allformats_i.i (1212728B)
1 /* 2 * DO NOT EDIT THIS FILE! 3 * This file is auto-generated from the registers file. 4 * Edits to this file will be lost when it is regenerated. 5 * 6 * 7 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 8 * 9 * Copyright 2007-2020 Broadcom Inc. All rights reserved. 10 * 11 * File: allformats_i.i 12 * Purpose: Independent format descriptions. 13 */ 14 15 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 16 { /* SOC_FORMAT_INT_IARB_EOP_BUSfmt */ 17 /* format IARB_EOP_BUSfmt */ 18 /* nFields */ 4, 19 /* *fields */ soc_IARB_EOP_BUSfmt_fields, 20 /* bits */ 24, 21 /* flags */ 0, 22 }, 23 #endif /* chips */ 24 25 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 26 { /* SOC_FORMAT_INT_IARB_EOP_EVENT_QUEUEfmt */ 27 /* format IARB_EOP_EVENT_QUEUEfmt */ 28 /* nFields */ 2, 29 /* *fields */ soc_IARB_EOP_EVENT_QUEUEfmt_fields, 30 /* bits */ 15, 31 /* flags */ 0, 32 }, 33 #endif /* chips */ 34 35 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 36 { /* SOC_FORMAT_INT_IARB_EVENT_FIFOfmt */ 37 /* format IARB_EVENT_FIFOfmt */ 38 /* nFields */ 4, 39 /* *fields */ soc_IARB_EVENT_FIFOfmt_fields, 40 /* bits */ 1244, 41 /* flags */ 0, 42 }, 43 #endif /* chips */ 44 45 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 46 defined(BCM_56870_A0) || defined(BCM_56960_A0) || \ 47 defined(BCM_56965_A0) || defined(BCM_56970_A0) || \ 48 defined(BCM_56980_A0) || defined(BCM_56980_B0) 49 { /* SOC_FORMAT_INT_IARB_TO_L2_MGMT_ACKfmt */ 50 /* format IARB_TO_L2_MGMT_ACKfmt */ 51 /* nFields */ 1, 52 /* *fields */ soc_IARB_TO_L2_MGMT_ACKfmt_fields, 53 /* bits */ 1, 54 /* flags */ 0, 55 }, 56 #endif /* chips */ 57 58 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 59 defined(BCM_56870_A0) 60 { /* SOC_FORMAT_INT_ICFG_DOPfmt */ 61 /* format ICFG_DOPfmt */ 62 /* nFields */ 18, 63 /* *fields */ soc_ICFG_DOPfmt_fields, 64 /* bits */ 256, 65 /* flags */ 0, 66 }, 67 #endif /* chips */ 68 69 #if defined(BCM_56870_A0) 70 { /* SOC_FORMAT_INT_ICFG_TO_ISW2_BUSfmt */ 71 /* format ICFG_TO_ISW2_BUSfmt */ 72 /* nFields */ 7, 73 /* *fields */ soc_IPARS_TO_ISW2_BUS_BCM56960_A0fmt_fields, 74 /* bits */ 34, 75 /* flags */ 0, 76 }, 77 #endif /* chips */ 78 79 #if defined(BCM_56370_A0) 80 { /* SOC_FORMAT_INT_ICFG_TO_ISW2_BUS_BCM56370_A0fmt */ 81 /* format ICFG_TO_ISW2_BUSfmt */ 82 /* nFields */ 8, 83 /* *fields */ soc_ICFG_TO_ISW2_BUSfmt_fields, 84 /* bits */ 102, 85 /* flags */ 0, 86 }, 87 #endif /* chips */ 88 89 #if defined(BCM_56770_A0) 90 { /* SOC_FORMAT_INT_ICFG_TO_ISW2_BUS_BCM56770_A0fmt */ 91 /* format ICFG_TO_ISW2_BUSfmt */ 92 /* nFields */ 7, 93 /* *fields */ soc_IPARS_TO_ISW2_BUS_BCM56960_A0fmt_fields, 94 /* bits */ 34, 95 /* flags */ 0, 96 }, 97 #endif /* chips */ 98 99 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 100 defined(BCM_56870_A0) 101 { /* SOC_FORMAT_INT_ICFG_TO_ISW3_BUSfmt */ 102 /* format ICFG_TO_ISW3_BUSfmt */ 103 /* nFields */ 2, 104 /* *fields */ soc_ICFG_TO_ISW3_BUSfmt_fields, 105 /* bits */ 129, 106 /* flags */ 0, 107 }, 108 #endif /* chips */ 109 110 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \ 111 defined(BCM_56450_A0) || defined(BCM_56450_B0) || \ 112 defined(BCM_56450_B1) || defined(BCM_56640_A0) || \ 113 defined(BCM_56850_A0) || defined(BCM_56860_A0) 114 { /* SOC_FORMAT_INT_ICMP_TYPEfmt */ 115 /* format ICMP_TYPEfmt */ 116 /* nFields */ 1, 117 /* *fields */ soc_ICMP_TYPEfmt_fields, 118 /* bits */ 8, 119 /* flags */ 0, 120 }, 121 #endif /* chips */ 122 123 #if defined(BCM_53400_A0) 124 { /* SOC_FORMAT_INT_ICMP_TYPE_BCM53400_A0fmt */ 125 /* format ICMP_TYPEfmt */ 126 /* nFields */ 1, 127 /* *fields */ soc_ICMP_TYPE_BCM53400_A0fmt_fields, 128 /* bits */ 8, 129 /* flags */ 0, 130 }, 131 #endif /* chips */ 132 133 #if defined(BCM_53540_A0) 134 { /* SOC_FORMAT_INT_ICMP_TYPE_BCM53540_A0fmt */ 135 /* format ICMP_TYPEfmt */ 136 /* nFields */ 1, 137 /* *fields */ soc_ICMP_TYPE_BCM53400_A0fmt_fields, 138 /* bits */ 8, 139 /* flags */ 0, 140 }, 141 #endif /* chips */ 142 143 #if defined(BCM_53570_A0) 144 { /* SOC_FORMAT_INT_ICMP_TYPE_BCM53570_A0fmt */ 145 /* format ICMP_TYPEfmt */ 146 /* nFields */ 1, 147 /* *fields */ soc_ICMP_TYPE_BCM53400_A0fmt_fields, 148 /* bits */ 8, 149 /* flags */ 0, 150 }, 151 #endif /* chips */ 152 153 #if defined(BCM_53570_B0) 154 { /* SOC_FORMAT_INT_ICMP_TYPE_BCM53570_B0fmt */ 155 /* format ICMP_TYPEfmt */ 156 /* nFields */ 1, 157 /* *fields */ soc_ICMP_TYPE_BCM53400_A0fmt_fields, 158 /* bits */ 8, 159 /* flags */ 0, 160 }, 161 #endif /* chips */ 162 163 #if defined(BCM_56160_A0) 164 { /* SOC_FORMAT_INT_ICMP_TYPE_BCM56160_A0fmt */ 165 /* format ICMP_TYPEfmt */ 166 /* nFields */ 1, 167 /* *fields */ soc_ICMP_TYPE_BCM53400_A0fmt_fields, 168 /* bits */ 8, 169 /* flags */ 0, 170 }, 171 #endif /* chips */ 172 173 #if defined(BCM_56260_A0) 174 { /* SOC_FORMAT_INT_ICMP_TYPE_BCM56260_A0fmt */ 175 /* format ICMP_TYPEfmt */ 176 /* nFields */ 1, 177 /* *fields */ soc_ICMP_TYPE_BCM53400_A0fmt_fields, 178 /* bits */ 8, 179 /* flags */ 0, 180 }, 181 #endif /* chips */ 182 183 #if defined(BCM_56260_B0) 184 { /* SOC_FORMAT_INT_ICMP_TYPE_BCM56260_B0fmt */ 185 /* format ICMP_TYPEfmt */ 186 /* nFields */ 1, 187 /* *fields */ soc_ICMP_TYPE_BCM53400_A0fmt_fields, 188 /* bits */ 8, 189 /* flags */ 0, 190 }, 191 #endif /* chips */ 192 193 #if defined(BCM_56270_A0) 194 { /* SOC_FORMAT_INT_ICMP_TYPE_BCM56270_A0fmt */ 195 /* format ICMP_TYPEfmt */ 196 /* nFields */ 1, 197 /* *fields */ soc_ICMP_TYPE_BCM53400_A0fmt_fields, 198 /* bits */ 8, 199 /* flags */ 0, 200 }, 201 #endif /* chips */ 202 203 #if defined(BCM_56370_A0) 204 { /* SOC_FORMAT_INT_ICMP_TYPE_BCM56370_A0fmt */ 205 /* format ICMP_TYPEfmt */ 206 /* nFields */ 1, 207 /* *fields */ soc_ICMP_TYPE_BCM53400_A0fmt_fields, 208 /* bits */ 8, 209 /* flags */ 0, 210 }, 211 #endif /* chips */ 212 213 #if defined(BCM_56560_A0) 214 { /* SOC_FORMAT_INT_ICMP_TYPE_BCM56560_A0fmt */ 215 /* format ICMP_TYPEfmt */ 216 /* nFields */ 1, 217 /* *fields */ soc_ICMP_TYPE_BCM53400_A0fmt_fields, 218 /* bits */ 8, 219 /* flags */ 0, 220 }, 221 #endif /* chips */ 222 223 #if defined(BCM_56560_B0) 224 { /* SOC_FORMAT_INT_ICMP_TYPE_BCM56560_B0fmt */ 225 /* format ICMP_TYPEfmt */ 226 /* nFields */ 1, 227 /* *fields */ soc_ICMP_TYPE_BCM53400_A0fmt_fields, 228 /* bits */ 8, 229 /* flags */ 0, 230 }, 231 #endif /* chips */ 232 233 #if defined(BCM_56670_A0) 234 { /* SOC_FORMAT_INT_ICMP_TYPE_BCM56670_A0fmt */ 235 /* format ICMP_TYPEfmt */ 236 /* nFields */ 1, 237 /* *fields */ soc_ICMP_TYPE_BCM53400_A0fmt_fields, 238 /* bits */ 8, 239 /* flags */ 0, 240 }, 241 #endif /* chips */ 242 243 #if defined(BCM_56670_B0) 244 { /* SOC_FORMAT_INT_ICMP_TYPE_BCM56670_B0fmt */ 245 /* format ICMP_TYPEfmt */ 246 /* nFields */ 1, 247 /* *fields */ soc_ICMP_TYPE_BCM53400_A0fmt_fields, 248 /* bits */ 8, 249 /* flags */ 0, 250 }, 251 #endif /* chips */ 252 253 #if defined(BCM_56770_A0) 254 { /* SOC_FORMAT_INT_ICMP_TYPE_BCM56770_A0fmt */ 255 /* format ICMP_TYPEfmt */ 256 /* nFields */ 1, 257 /* *fields */ soc_ICMP_TYPE_BCM53400_A0fmt_fields, 258 /* bits */ 8, 259 /* flags */ 0, 260 }, 261 #endif /* chips */ 262 263 #if defined(BCM_56870_A0) 264 { /* SOC_FORMAT_INT_ICMP_TYPE_BCM56870_A0fmt */ 265 /* format ICMP_TYPEfmt */ 266 /* nFields */ 1, 267 /* *fields */ soc_ICMP_TYPE_BCM53400_A0fmt_fields, 268 /* bits */ 8, 269 /* flags */ 0, 270 }, 271 #endif /* chips */ 272 273 #if defined(BCM_56960_A0) 274 { /* SOC_FORMAT_INT_ICMP_TYPE_BCM56960_A0fmt */ 275 /* format ICMP_TYPEfmt */ 276 /* nFields */ 1, 277 /* *fields */ soc_ICMP_TYPE_BCM53400_A0fmt_fields, 278 /* bits */ 8, 279 /* flags */ 0, 280 }, 281 #endif /* chips */ 282 283 #if defined(BCM_56965_A0) 284 { /* SOC_FORMAT_INT_ICMP_TYPE_BCM56965_A0fmt */ 285 /* format ICMP_TYPEfmt */ 286 /* nFields */ 1, 287 /* *fields */ soc_ICMP_TYPE_BCM53400_A0fmt_fields, 288 /* bits */ 8, 289 /* flags */ 0, 290 }, 291 #endif /* chips */ 292 293 #if defined(BCM_56970_A0) 294 { /* SOC_FORMAT_INT_ICMP_TYPE_BCM56970_A0fmt */ 295 /* format ICMP_TYPEfmt */ 296 /* nFields */ 1, 297 /* *fields */ soc_ICMP_TYPE_BCM53400_A0fmt_fields, 298 /* bits */ 8, 299 /* flags */ 0, 300 }, 301 #endif /* chips */ 302 303 #if defined(BCM_56980_A0) 304 { /* SOC_FORMAT_INT_ICMP_TYPE_BCM56980_A0fmt */ 305 /* format ICMP_TYPEfmt */ 306 /* nFields */ 1, 307 /* *fields */ soc_ICMP_TYPE_BCM53400_A0fmt_fields, 308 /* bits */ 8, 309 /* flags */ 0, 310 }, 311 #endif /* chips */ 312 313 #if defined(BCM_56980_B0) 314 { /* SOC_FORMAT_INT_ICMP_TYPE_BCM56980_B0fmt */ 315 /* format ICMP_TYPEfmt */ 316 /* nFields */ 1, 317 /* *fields */ soc_ICMP_TYPE_BCM53400_A0fmt_fields, 318 /* bits */ 8, 319 /* flags */ 0, 320 }, 321 #endif /* chips */ 322 323 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 324 { /* SOC_FORMAT_INT_IDB_CA0_CTRLfmt */ 325 /* format IDB_CA0_CTRLfmt */ 326 /* nFields */ 8, 327 /* *fields */ soc_IDB_CA0_CTRLfmt_fields, 328 /* bits */ 22, 329 /* flags */ 0, 330 }, 331 #endif /* chips */ 332 333 #if defined(BCM_56370_A0) 334 { /* SOC_FORMAT_INT_IDB_CA_Q_TO_OBM_BUSfmt */ 335 /* format IDB_CA_Q_TO_OBM_BUSfmt */ 336 /* nFields */ 55, 337 /* *fields */ soc_IDB_CA_Q_TO_OBM_BUSfmt_fields, 338 /* bits */ 441, 339 /* flags */ 0, 340 }, 341 #endif /* chips */ 342 343 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 344 { /* SOC_FORMAT_INT_IDB_CA_TO_IP_CTRLfmt */ 345 /* format IDB_CA_TO_IP_CTRLfmt */ 346 /* nFields */ 11, 347 /* *fields */ soc_IDB_CA_TO_IP_CTRLfmt_fields, 348 /* bits */ 63, 349 /* flags */ 0, 350 }, 351 #endif /* chips */ 352 353 #if defined(BCM_56370_A0) 354 { /* SOC_FORMAT_INT_IDB_CA_TO_OBM_BUSfmt */ 355 /* format IDB_CA_TO_OBM_BUSfmt */ 356 /* nFields */ 22, 357 /* *fields */ soc_IDB_CA_TO_OBM_BUSfmt_fields, 358 /* bits */ 104, 359 /* flags */ 0, 360 }, 361 #endif /* chips */ 362 363 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 364 { /* SOC_FORMAT_INT_IDB_CTRL_BUSfmt */ 365 /* format IDB_CTRL_BUSfmt */ 366 /* nFields */ 17, 367 /* *fields */ soc_IDB_CTRL_BUSfmt_fields, 368 /* bits */ 72, 369 /* flags */ 0, 370 }, 371 #endif /* chips */ 372 373 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \ 374 defined(BCM_56970_A0) 375 { /* SOC_FORMAT_INT_IDB_EOP_BUSfmt */ 376 /* format IDB_EOP_BUSfmt */ 377 /* nFields */ 4, 378 /* *fields */ soc_IDB_EOP_BUSfmt_fields, 379 /* bits */ 24, 380 /* flags */ 0, 381 }, 382 #endif /* chips */ 383 384 #if defined(BCM_56370_A0) 385 { /* SOC_FORMAT_INT_IDB_EOP_BUS_BCM56370_A0fmt */ 386 /* format IDB_EOP_BUSfmt */ 387 /* nFields */ 4, 388 /* *fields */ soc_IDB_EOP_BUS_BCM56370_A0fmt_fields, 389 /* bits */ 23, 390 /* flags */ 0, 391 }, 392 #endif /* chips */ 393 394 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 395 defined(BCM_56870_A0) || defined(BCM_56970_A0) 396 { /* SOC_FORMAT_INT_IDB_EOP_EVENT_QUEUEfmt */ 397 /* format IDB_EOP_EVENT_QUEUEfmt */ 398 /* nFields */ 4, 399 /* *fields */ soc_IDB_EOP_EVENT_QUEUEfmt_fields, 400 /* bits */ 17, 401 /* flags */ 0, 402 }, 403 #endif /* chips */ 404 405 #if defined(BCM_56370_A0) 406 { /* SOC_FORMAT_INT_IDB_OBM0_48_DATAfmt */ 407 /* format IDB_OBM0_48_DATAfmt */ 408 /* nFields */ 12, 409 /* *fields */ soc_IDB_OBM0_48_DATAfmt_fields, 410 /* bits */ 417, 411 /* flags */ 0, 412 }, 413 #endif /* chips */ 414 415 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 416 { /* SOC_FORMAT_INT_IDB_OBM0_CTRLfmt */ 417 /* format IDB_OBM0_CTRLfmt */ 418 /* nFields */ 14, 419 /* *fields */ soc_IDB_OBM0_CTRLfmt_fields, 420 /* bits */ 58, 421 /* flags */ 0, 422 }, 423 #endif /* chips */ 424 425 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) 426 { /* SOC_FORMAT_INT_IDB_OBM0_DATAfmt */ 427 /* format IDB_OBM0_DATAfmt */ 428 /* nFields */ 12, 429 /* *fields */ soc_IDB_OBM0_DATAfmt_fields, 430 /* bits */ 432, 431 /* flags */ 0, 432 }, 433 #endif /* chips */ 434 435 #if defined(BCM_56370_A0) 436 { /* SOC_FORMAT_INT_IDB_OBM0_DATA_BCM56370_A0fmt */ 437 /* format IDB_OBM0_DATAfmt */ 438 /* nFields */ 12, 439 /* *fields */ soc_IDB_OBM0_DATA_BCM56870_A0fmt_fields, 440 /* bits */ 155, 441 /* flags */ 0, 442 }, 443 #endif /* chips */ 444 445 #if defined(BCM_56560_A0) 446 { /* SOC_FORMAT_INT_IDB_OBM0_DATA_BCM56560_A0fmt */ 447 /* format IDB_OBM0_DATAfmt */ 448 /* nFields */ 12, 449 /* *fields */ soc_IDB_OBM0_DATA_BCM56560_A0fmt_fields, 450 /* bits */ 432, 451 /* flags */ 0, 452 }, 453 #endif /* chips */ 454 455 #if defined(BCM_56560_B0) 456 { /* SOC_FORMAT_INT_IDB_OBM0_DATA_BCM56560_B0fmt */ 457 /* format IDB_OBM0_DATAfmt */ 458 /* nFields */ 12, 459 /* *fields */ soc_IDB_OBM0_DATA_BCM56560_A0fmt_fields, 460 /* bits */ 432, 461 /* flags */ 0, 462 }, 463 #endif /* chips */ 464 465 #if defined(BCM_56670_A0) 466 { /* SOC_FORMAT_INT_IDB_OBM0_DATA_BCM56670_A0fmt */ 467 /* format IDB_OBM0_DATAfmt */ 468 /* nFields */ 12, 469 /* *fields */ soc_IDB_OBM0_DATA_BCM56670_A0fmt_fields, 470 /* bits */ 430, 471 /* flags */ 0, 472 }, 473 #endif /* chips */ 474 475 #if defined(BCM_56670_B0) 476 { /* SOC_FORMAT_INT_IDB_OBM0_DATA_BCM56670_B0fmt */ 477 /* format IDB_OBM0_DATAfmt */ 478 /* nFields */ 12, 479 /* *fields */ soc_IDB_OBM0_DATA_BCM56670_A0fmt_fields, 480 /* bits */ 430, 481 /* flags */ 0, 482 }, 483 #endif /* chips */ 484 485 #if defined(BCM_56770_A0) 486 { /* SOC_FORMAT_INT_IDB_OBM0_DATA_BCM56770_A0fmt */ 487 /* format IDB_OBM0_DATAfmt */ 488 /* nFields */ 12, 489 /* *fields */ soc_IDB_OBM0_DATA_BCM56870_A0fmt_fields, 490 /* bits */ 155, 491 /* flags */ 0, 492 }, 493 #endif /* chips */ 494 495 #if defined(BCM_56870_A0) 496 { /* SOC_FORMAT_INT_IDB_OBM0_DATA_BCM56870_A0fmt */ 497 /* format IDB_OBM0_DATAfmt */ 498 /* nFields */ 12, 499 /* *fields */ soc_IDB_OBM0_DATA_BCM56870_A0fmt_fields, 500 /* bits */ 155, 501 /* flags */ 0, 502 }, 503 #endif /* chips */ 504 505 #if defined(BCM_56970_A0) 506 { /* SOC_FORMAT_INT_IDB_OBM0_DATA_BCM56970_A0fmt */ 507 /* format IDB_OBM0_DATAfmt */ 508 /* nFields */ 11, 509 /* *fields */ soc_IDB_OBM0_DATA_BCM56970_A0fmt_fields, 510 /* bits */ 153, 511 /* flags */ 0, 512 }, 513 #endif /* chips */ 514 515 #if defined(BCM_56370_A0) 516 { /* SOC_FORMAT_INT_IDB_OBM0_Q_DATAfmt */ 517 /* format IDB_OBM0_Q_DATAfmt */ 518 /* nFields */ 12, 519 /* *fields */ soc_IDB_OBM0_Q_DATAfmt_fields, 520 /* bits */ 155, 521 /* flags */ 0, 522 }, 523 #endif /* chips */ 524 525 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 526 { /* SOC_FORMAT_INT_IDB_OBM0_RESIDUE_CTRLfmt */ 527 /* format IDB_OBM0_RESIDUE_CTRLfmt */ 528 /* nFields */ 17, 529 /* *fields */ soc_IDB_OBM0_RESIDUE_CTRLfmt_fields, 530 /* bits */ 100, 531 /* flags */ 0, 532 }, 533 #endif /* chips */ 534 535 #if defined(BCM_56370_A0) 536 { /* SOC_FORMAT_INT_IDB_OBM_Q_TO_CA_BUSfmt */ 537 /* format IDB_OBM_Q_TO_CA_BUSfmt */ 538 /* nFields */ 19, 539 /* *fields */ soc_IDB_OBM_Q_TO_CA_BUSfmt_fields, 540 /* bits */ 167, 541 /* flags */ 0, 542 }, 543 #endif /* chips */ 544 545 #if defined(BCM_56370_A0) 546 { /* SOC_FORMAT_INT_IDB_OBM_TO_CA_BUSfmt */ 547 /* format IDB_OBM_TO_CA_BUSfmt */ 548 /* nFields */ 22, 549 /* *fields */ soc_IDB_OBM_TO_CA_BUSfmt_fields, 550 /* bits */ 78, 551 /* flags */ 0, 552 }, 553 #endif /* chips */ 554 555 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 556 { /* SOC_FORMAT_INT_IDB_OBM_TO_CA_CTRLfmt */ 557 /* format IDB_OBM_TO_CA_CTRLfmt */ 558 /* nFields */ 10, 559 /* *fields */ soc_IDB_OBM_TO_CA_CTRLfmt_fields, 560 /* bits */ 18, 561 /* flags */ 0, 562 }, 563 #endif /* chips */ 564 565 #if defined(BCM_56970_A0) 566 { /* SOC_FORMAT_INT_IDB_SOP_EVENT_FIFOfmt */ 567 /* format IDB_SOP_EVENT_FIFOfmt */ 568 /* nFields */ 12, 569 /* *fields */ soc_IDB_SOP_EVENT_FIFOfmt_fields, 570 /* bits */ 1474, 571 /* flags */ 0, 572 }, 573 #endif /* chips */ 574 575 #if defined(BCM_56370_A0) 576 { /* SOC_FORMAT_INT_IDB_SOP_EVENT_FIFO_BCM56370_A0fmt */ 577 /* format IDB_SOP_EVENT_FIFOfmt */ 578 /* nFields */ 12, 579 /* *fields */ soc_IDB_SOP_EVENT_FIFO_BCM56870_A0fmt_fields, 580 /* bits */ 1475, 581 /* flags */ 0, 582 }, 583 #endif /* chips */ 584 585 #if defined(BCM_56770_A0) 586 { /* SOC_FORMAT_INT_IDB_SOP_EVENT_FIFO_BCM56770_A0fmt */ 587 /* format IDB_SOP_EVENT_FIFOfmt */ 588 /* nFields */ 12, 589 /* *fields */ soc_IDB_SOP_EVENT_FIFO_BCM56870_A0fmt_fields, 590 /* bits */ 1475, 591 /* flags */ 0, 592 }, 593 #endif /* chips */ 594 595 #if defined(BCM_56870_A0) 596 { /* SOC_FORMAT_INT_IDB_SOP_EVENT_FIFO_BCM56870_A0fmt */ 597 /* format IDB_SOP_EVENT_FIFOfmt */ 598 /* nFields */ 12, 599 /* *fields */ soc_IDB_SOP_EVENT_FIFO_BCM56870_A0fmt_fields, 600 /* bits */ 1475, 601 /* flags */ 0, 602 }, 603 #endif /* chips */ 604 605 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 606 { /* SOC_FORMAT_INT_IDB_TO_IPOST_BUSfmt */ 607 /* format IDB_TO_IPOST_BUSfmt */ 608 /* nFields */ 7, 609 /* *fields */ soc_IDB_TO_IPOST_BUSfmt_fields, 610 /* bits */ 18, 611 /* flags */ 0, 612 }, 613 #endif /* chips */ 614 615 #if defined(BCM_56970_A0) 616 { /* SOC_FORMAT_INT_IDB_TO_ISW4_BUSfmt */ 617 /* format IDB_TO_ISW4_BUSfmt */ 618 /* nFields */ 8, 619 /* *fields */ soc_IDB_TO_ISW4_BUSfmt_fields, 620 /* bits */ 22, 621 /* flags */ 0, 622 }, 623 #endif /* chips */ 624 625 #if defined(BCM_56370_A0) 626 { /* SOC_FORMAT_INT_IDB_TO_ISW4_BUS_BCM56370_A0fmt */ 627 /* format IDB_TO_ISW4_BUSfmt */ 628 /* nFields */ 9, 629 /* *fields */ soc_IDB_TO_ISW4_BUS_BCM56370_A0fmt_fields, 630 /* bits */ 23, 631 /* flags */ 0, 632 }, 633 #endif /* chips */ 634 635 #if defined(BCM_56770_A0) 636 { /* SOC_FORMAT_INT_IDB_TO_ISW4_BUS_BCM56770_A0fmt */ 637 /* format IDB_TO_ISW4_BUSfmt */ 638 /* nFields */ 8, 639 /* *fields */ soc_IDB_TO_ISW4_BUS_BCM56870_A0fmt_fields, 640 /* bits */ 23, 641 /* flags */ 0, 642 }, 643 #endif /* chips */ 644 645 #if defined(BCM_56870_A0) 646 { /* SOC_FORMAT_INT_IDB_TO_ISW4_BUS_BCM56870_A0fmt */ 647 /* format IDB_TO_ISW4_BUSfmt */ 648 /* nFields */ 8, 649 /* *fields */ soc_IDB_TO_ISW4_BUS_BCM56870_A0fmt_fields, 650 /* bits */ 23, 651 /* flags */ 0, 652 }, 653 #endif /* chips */ 654 655 #if defined(BCM_56340_A0) || defined(BCM_56640_A0) 656 { /* SOC_FORMAT_INT_IDISC_DROPfmt */ 657 /* format IDISC_DROPfmt */ 658 /* nFields */ 19, 659 /* *fields */ soc_IDISC_DROPfmt_fields, 660 /* bits */ 18, 661 /* flags */ 0, 662 }, 663 #endif /* chips */ 664 665 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) 666 { /* SOC_FORMAT_INT_IFP_0_DOPfmt */ 667 /* format IFP_0_DOPfmt */ 668 /* nFields */ 6, 669 /* *fields */ soc_IFP_0_DOPfmt_fields, 670 /* bits */ 32, 671 /* flags */ 0, 672 }, 673 #endif /* chips */ 674 675 #if defined(BCM_56370_A0) 676 { /* SOC_FORMAT_INT_IFP_0_DOP_BCM56370_A0fmt */ 677 /* format IFP_0_DOPfmt */ 678 /* nFields */ 6, 679 /* *fields */ soc_IFP_0_DOP_BCM56370_A0fmt_fields, 680 /* bits */ 32, 681 /* flags */ 0, 682 }, 683 #endif /* chips */ 684 685 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 686 defined(BCM_56870_A0) 687 { /* SOC_FORMAT_INT_IFP_BFD_BUS_FORMATfmt */ 688 /* format IFP_BFD_BUS_FORMATfmt */ 689 /* nFields */ 4, 690 /* *fields */ soc_IFP_BFD_BUS_FORMATfmt_fields, 691 /* bits */ 8, 692 /* flags */ 0, 693 }, 694 #endif /* chips */ 695 696 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) 697 { /* SOC_FORMAT_INT_IFP_CHANGE_COS_OR_INT_PRI_SETfmt */ 698 /* format IFP_CHANGE_COS_OR_INT_PRI_SETfmt */ 699 /* nFields */ 6, 700 /* *fields */ soc_IFP_CHANGE_COS_OR_INT_PRI_SETfmt_fields, 701 /* bits */ 36, 702 /* flags */ 0, 703 }, 704 #endif /* chips */ 705 706 #if defined(BCM_56370_A0) 707 { /* SOC_FORMAT_INT_IFP_CHANGE_COS_OR_INT_PRI_SET_BCM56370_A0fmt */ 708 /* format IFP_CHANGE_COS_OR_INT_PRI_SETfmt */ 709 /* nFields */ 6, 710 /* *fields */ soc_IFP_CHANGE_COS_OR_INT_PRI_SET_BCM56370_A0fmt_fields, 711 /* bits */ 42, 712 /* flags */ 0, 713 }, 714 #endif /* chips */ 715 716 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 717 defined(BCM_56870_A0) || defined(BCM_56960_A0) || \ 718 defined(BCM_56965_A0) || defined(BCM_56970_A0) 719 { /* SOC_FORMAT_INT_IFP_CHANGE_CPU_COS_SETfmt */ 720 /* format IFP_CHANGE_CPU_COS_SETfmt */ 721 /* nFields */ 2, 722 /* *fields */ soc_IFP_CHANGE_CPU_COS_SETfmt_fields, 723 /* bits */ 8, 724 /* flags */ 0, 725 }, 726 #endif /* chips */ 727 728 #if defined(BCM_56980_A0) 729 { /* SOC_FORMAT_INT_IFP_CHANGE_CPU_COS_SET_BCM56980_A0fmt */ 730 /* format IFP_CHANGE_CPU_COS_SETfmt */ 731 /* nFields */ 2, 732 /* *fields */ soc_IFP_CHANGE_CPU_COS_SET_BCM56980_A0fmt_fields, 733 /* bits */ 8, 734 /* flags */ 0, 735 }, 736 #endif /* chips */ 737 738 #if defined(BCM_56980_B0) 739 { /* SOC_FORMAT_INT_IFP_CHANGE_CPU_COS_SET_BCM56980_B0fmt */ 740 /* format IFP_CHANGE_CPU_COS_SETfmt */ 741 /* nFields */ 2, 742 /* *fields */ soc_IFP_CHANGE_CPU_COS_SET_BCM56980_A0fmt_fields, 743 /* bits */ 8, 744 /* flags */ 0, 745 }, 746 #endif /* chips */ 747 748 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 749 defined(BCM_56870_A0) 750 { /* SOC_FORMAT_INT_IFP_CHANGE_DROP_PRECEDENCE_SETfmt */ 751 /* format IFP_CHANGE_DROP_PRECEDENCE_SETfmt */ 752 /* nFields */ 3, 753 /* *fields */ soc_IFP_CHANGE_DROP_PRECEDENCE_SETfmt_fields, 754 /* bits */ 6, 755 /* flags */ 0, 756 }, 757 #endif /* chips */ 758 759 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 760 defined(BCM_56870_A0) 761 { /* SOC_FORMAT_INT_IFP_CHANGE_DSCP_TOS_SETfmt */ 762 /* format IFP_CHANGE_DSCP_TOS_SETfmt */ 763 /* nFields */ 6, 764 /* *fields */ soc_IFP_CHANGE_DSCP_TOS_SETfmt_fields, 765 /* bits */ 25, 766 /* flags */ 0, 767 }, 768 #endif /* chips */ 769 770 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 771 defined(BCM_56870_A0) 772 { /* SOC_FORMAT_INT_IFP_CHANGE_ECN_SETfmt */ 773 /* format IFP_CHANGE_ECN_SETfmt */ 774 /* nFields */ 6, 775 /* *fields */ soc_IFP_CHANGE_ECN_SETfmt_fields, 776 /* bits */ 9, 777 /* flags */ 0, 778 }, 779 #endif /* chips */ 780 781 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 782 defined(BCM_56870_A0) 783 { /* SOC_FORMAT_INT_IFP_CHANGE_INPUT_PRIORITY_SETfmt */ 784 /* format IFP_CHANGE_INPUT_PRIORITY_SETfmt */ 785 /* nFields */ 2, 786 /* *fields */ soc_IFP_CHANGE_INPUT_PRIORITY_SETfmt_fields, 787 /* bits */ 5, 788 /* flags */ 0, 789 }, 790 #endif /* chips */ 791 792 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 793 defined(BCM_56870_A0) 794 { /* SOC_FORMAT_INT_IFP_CHANGE_INT_CN_SETfmt */ 795 /* format IFP_CHANGE_INT_CN_SETfmt */ 796 /* nFields */ 6, 797 /* *fields */ soc_IFP_CHANGE_INT_CN_SETfmt_fields, 798 /* bits */ 9, 799 /* flags */ 0, 800 }, 801 #endif /* chips */ 802 803 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 804 defined(BCM_56870_A0) 805 { /* SOC_FORMAT_INT_IFP_CHANGE_PKT_PRI_SETfmt */ 806 /* format IFP_CHANGE_PKT_PRI_SETfmt */ 807 /* nFields */ 6, 808 /* *fields */ soc_IFP_CHANGE_PKT_PRI_SETfmt_fields, 809 /* bits */ 18, 810 /* flags */ 0, 811 }, 812 #endif /* chips */ 813 814 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 815 defined(BCM_56870_A0) || defined(BCM_56960_A0) || \ 816 defined(BCM_56965_A0) || defined(BCM_56970_A0) 817 { /* SOC_FORMAT_INT_IFP_COPY_TO_CPU_SETfmt */ 818 /* format IFP_COPY_TO_CPU_SETfmt */ 819 /* nFields */ 4, 820 /* *fields */ soc_IFP_COPY_TO_CPU_SETfmt_fields, 821 /* bits */ 17, 822 /* flags */ 0, 823 }, 824 #endif /* chips */ 825 826 #if defined(BCM_56980_A0) 827 { /* SOC_FORMAT_INT_IFP_COPY_TO_CPU_SET_BCM56980_A0fmt */ 828 /* format IFP_COPY_TO_CPU_SETfmt */ 829 /* nFields */ 4, 830 /* *fields */ soc_IFP_COPY_TO_CPU_SET_BCM56980_A0fmt_fields, 831 /* bits */ 17, 832 /* flags */ 0, 833 }, 834 #endif /* chips */ 835 836 #if defined(BCM_56980_B0) 837 { /* SOC_FORMAT_INT_IFP_COPY_TO_CPU_SET_BCM56980_B0fmt */ 838 /* format IFP_COPY_TO_CPU_SETfmt */ 839 /* nFields */ 4, 840 /* *fields */ soc_IFP_COPY_TO_CPU_SET_BCM56980_A0fmt_fields, 841 /* bits */ 17, 842 /* flags */ 0, 843 }, 844 #endif /* chips */ 845 846 #if defined(BCM_56840_A0) || defined(BCM_56840_B0) 847 { /* SOC_FORMAT_INT_IFP_COUNTER_MUX_DATA_STAGINGfmt */ 848 /* format IFP_COUNTER_MUX_DATA_STAGINGfmt */ 849 /* nFields */ 22, 850 /* *fields */ soc_IFP_COUNTER_MUX_DATA_STAGINGfmt_fields, 851 /* bits */ 92, 852 /* flags */ 0, 853 }, 854 #endif /* chips */ 855 856 #if defined(BCM_56340_A0) 857 { /* SOC_FORMAT_INT_IFP_COUNTER_MUX_DATA_STAGING_BCM56340_A0fmt */ 858 /* format IFP_COUNTER_MUX_DATA_STAGINGfmt */ 859 /* nFields */ 4, 860 /* *fields */ soc_IFP_COUNTER_MUX_DATA_STAGING_BCM56640_A0fmt_fields, 861 /* bits */ 16, 862 /* flags */ 0, 863 }, 864 #endif /* chips */ 865 866 #if defined(BCM_56560_A0) 867 { /* SOC_FORMAT_INT_IFP_COUNTER_MUX_DATA_STAGING_BCM56560_A0fmt */ 868 /* format IFP_COUNTER_MUX_DATA_STAGINGfmt */ 869 /* nFields */ 26, 870 /* *fields */ soc_IFP_COUNTER_MUX_DATA_STAGING_BCM56560_A0fmt_fields, 871 /* bits */ 152, 872 /* flags */ 0, 873 }, 874 #endif /* chips */ 875 876 #if defined(BCM_56560_B0) 877 { /* SOC_FORMAT_INT_IFP_COUNTER_MUX_DATA_STAGING_BCM56560_B0fmt */ 878 /* format IFP_COUNTER_MUX_DATA_STAGINGfmt */ 879 /* nFields */ 26, 880 /* *fields */ soc_IFP_COUNTER_MUX_DATA_STAGING_BCM56560_A0fmt_fields, 881 /* bits */ 152, 882 /* flags */ 0, 883 }, 884 #endif /* chips */ 885 886 #if defined(BCM_56640_A0) 887 { /* SOC_FORMAT_INT_IFP_COUNTER_MUX_DATA_STAGING_BCM56640_A0fmt */ 888 /* format IFP_COUNTER_MUX_DATA_STAGINGfmt */ 889 /* nFields */ 4, 890 /* *fields */ soc_IFP_COUNTER_MUX_DATA_STAGING_BCM56640_A0fmt_fields, 891 /* bits */ 16, 892 /* flags */ 0, 893 }, 894 #endif /* chips */ 895 896 #if defined(BCM_56670_A0) 897 { /* SOC_FORMAT_INT_IFP_COUNTER_MUX_DATA_STAGING_BCM56670_A0fmt */ 898 /* format IFP_COUNTER_MUX_DATA_STAGINGfmt */ 899 /* nFields */ 38, 900 /* *fields */ soc_IFP_COUNTER_MUX_DATA_STAGING_BCM56670_A0fmt_fields, 901 /* bits */ 164, 902 /* flags */ 0, 903 }, 904 #endif /* chips */ 905 906 #if defined(BCM_56670_B0) 907 { /* SOC_FORMAT_INT_IFP_COUNTER_MUX_DATA_STAGING_BCM56670_B0fmt */ 908 /* format IFP_COUNTER_MUX_DATA_STAGINGfmt */ 909 /* nFields */ 38, 910 /* *fields */ soc_IFP_COUNTER_MUX_DATA_STAGING_BCM56670_A0fmt_fields, 911 /* bits */ 164, 912 /* flags */ 0, 913 }, 914 #endif /* chips */ 915 916 #if defined(BCM_56850_A0) 917 { /* SOC_FORMAT_INT_IFP_COUNTER_MUX_DATA_STAGING_BCM56850_A0fmt */ 918 /* format IFP_COUNTER_MUX_DATA_STAGINGfmt */ 919 /* nFields */ 26, 920 /* *fields */ soc_IFP_COUNTER_MUX_DATA_STAGING_BCM56850_A0fmt_fields, 921 /* bits */ 124, 922 /* flags */ 0, 923 }, 924 #endif /* chips */ 925 926 #if defined(BCM_56860_A0) 927 { /* SOC_FORMAT_INT_IFP_COUNTER_MUX_DATA_STAGING_BCM56860_A0fmt */ 928 /* format IFP_COUNTER_MUX_DATA_STAGINGfmt */ 929 /* nFields */ 26, 930 /* *fields */ soc_IFP_COUNTER_MUX_DATA_STAGING_BCM56860_A0fmt_fields, 931 /* bits */ 152, 932 /* flags */ 0, 933 }, 934 #endif /* chips */ 935 936 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) 937 { /* SOC_FORMAT_INT_IFP_COUNTER_SETfmt */ 938 /* format IFP_COUNTER_SETfmt */ 939 /* nFields */ 6, 940 /* *fields */ soc_IFP_COUNTER_SETfmt_fields, 941 /* bits */ 25, 942 /* flags */ 0, 943 }, 944 #endif /* chips */ 945 946 #if defined(BCM_56370_A0) 947 { /* SOC_FORMAT_INT_IFP_COUNTER_SET_BCM56370_A0fmt */ 948 /* format IFP_COUNTER_SETfmt */ 949 /* nFields */ 7, 950 /* *fields */ soc_IFP_COUNTER_SET_BCM56370_A0fmt_fields, 951 /* bits */ 26, 952 /* flags */ 0, 953 }, 954 #endif /* chips */ 955 956 #if defined(BCM_56770_A0) 957 { /* SOC_FORMAT_INT_IFP_COUNTER_SET_BCM56770_A0fmt */ 958 /* format IFP_COUNTER_SETfmt */ 959 /* nFields */ 6, 960 /* *fields */ soc_IFP_COUNTER_SET_BCM56970_A0fmt_fields, 961 /* bits */ 26, 962 /* flags */ 0, 963 }, 964 #endif /* chips */ 965 966 #if defined(BCM_56870_A0) 967 { /* SOC_FORMAT_INT_IFP_COUNTER_SET_BCM56870_A0fmt */ 968 /* format IFP_COUNTER_SETfmt */ 969 /* nFields */ 6, 970 /* *fields */ soc_IFP_COUNTER_SET_BCM56970_A0fmt_fields, 971 /* bits */ 26, 972 /* flags */ 0, 973 }, 974 #endif /* chips */ 975 976 #if defined(BCM_56970_A0) 977 { /* SOC_FORMAT_INT_IFP_COUNTER_SET_BCM56970_A0fmt */ 978 /* format IFP_COUNTER_SETfmt */ 979 /* nFields */ 6, 980 /* *fields */ soc_IFP_COUNTER_SET_BCM56970_A0fmt_fields, 981 /* bits */ 26, 982 /* flags */ 0, 983 }, 984 #endif /* chips */ 985 986 #if defined(BCM_56980_A0) 987 { /* SOC_FORMAT_INT_IFP_COUNTER_SET_BCM56980_A0fmt */ 988 /* format IFP_COUNTER_SETfmt */ 989 /* nFields */ 6, 990 /* *fields */ soc_IFP_COUNTER_SET_BCM56980_A0fmt_fields, 991 /* bits */ 25, 992 /* flags */ 0, 993 }, 994 #endif /* chips */ 995 996 #if defined(BCM_56980_B0) 997 { /* SOC_FORMAT_INT_IFP_COUNTER_SET_BCM56980_B0fmt */ 998 /* format IFP_COUNTER_SETfmt */ 999 /* nFields */ 6, 1000 /* *fields */ soc_IFP_COUNTER_SET_BCM56980_A0fmt_fields, 1001 /* bits */ 25, 1002 /* flags */ 0, 1003 }, 1004 #endif /* chips */ 1005 1006 #if defined(BCM_56340_A0) || defined(BCM_56640_A0) 1007 { /* SOC_FORMAT_INT_IFP_COUNTER_TABLE_COV_DEFSfmt */ 1008 /* format IFP_COUNTER_TABLE_COV_DEFSfmt */ 1009 /* nFields */ 6, 1010 /* *fields */ soc_IFP_COUNTER_TABLE_COV_DEFSfmt_fields, 1011 /* bits */ 17, 1012 /* flags */ 0, 1013 }, 1014 #endif /* chips */ 1015 1016 #if defined(BCM_53400_A0) 1017 { /* SOC_FORMAT_INT_IFP_COUNTER_TABLE_COV_DEFS_BCM53400_A0fmt */ 1018 /* format IFP_COUNTER_TABLE_COV_DEFSfmt */ 1019 /* nFields */ 6, 1020 /* *fields */ soc_EGR_PERQ_XMT_COUNTERS_COV_DEFS_BCM53400_A0fmt_fields, 1021 /* bits */ 14, 1022 /* flags */ 0, 1023 }, 1024 #endif /* chips */ 1025 1026 #if defined(BCM_53540_A0) 1027 { /* SOC_FORMAT_INT_IFP_COUNTER_TABLE_COV_DEFS_BCM53540_A0fmt */ 1028 /* format IFP_COUNTER_TABLE_COV_DEFSfmt */ 1029 /* nFields */ 6, 1030 /* *fields */ soc_EGR_PERQ_XMT_COUNTERS_COV_DEFS_BCM53400_A0fmt_fields, 1031 /* bits */ 14, 1032 /* flags */ 0, 1033 }, 1034 #endif /* chips */ 1035 1036 #if defined(BCM_53570_A0) 1037 { /* SOC_FORMAT_INT_IFP_COUNTER_TABLE_COV_DEFS_BCM53570_A0fmt */ 1038 /* format IFP_COUNTER_TABLE_COV_DEFSfmt */ 1039 /* nFields */ 6, 1040 /* *fields */ soc_EGR_PERQ_XMT_COUNTERS_COV_DEFS_BCM53400_A0fmt_fields, 1041 /* bits */ 14, 1042 /* flags */ 0, 1043 }, 1044 #endif /* chips */ 1045 1046 #if defined(BCM_53570_B0) 1047 { /* SOC_FORMAT_INT_IFP_COUNTER_TABLE_COV_DEFS_BCM53570_B0fmt */ 1048 /* format IFP_COUNTER_TABLE_COV_DEFSfmt */ 1049 /* nFields */ 6, 1050 /* *fields */ soc_EGR_PERQ_XMT_COUNTERS_COV_DEFS_BCM53400_A0fmt_fields, 1051 /* bits */ 14, 1052 /* flags */ 0, 1053 }, 1054 #endif /* chips */ 1055 1056 #if defined(BCM_56150_A0) 1057 { /* SOC_FORMAT_INT_IFP_COUNTER_TABLE_COV_DEFS_BCM56150_A0fmt */ 1058 /* format IFP_COUNTER_TABLE_COV_DEFSfmt */ 1059 /* nFields */ 6, 1060 /* *fields */ soc_EGR_PERQ_XMT_COUNTERS_COV_DEFSfmt_fields, 1061 /* bits */ 14, 1062 /* flags */ 0, 1063 }, 1064 #endif /* chips */ 1065 1066 #if defined(BCM_56160_A0) 1067 { /* SOC_FORMAT_INT_IFP_COUNTER_TABLE_COV_DEFS_BCM56160_A0fmt */ 1068 /* format IFP_COUNTER_TABLE_COV_DEFSfmt */ 1069 /* nFields */ 6, 1070 /* *fields */ soc_EGR_PERQ_XMT_COUNTERS_COV_DEFS_BCM53400_A0fmt_fields, 1071 /* bits */ 14, 1072 /* flags */ 0, 1073 }, 1074 #endif /* chips */ 1075 1076 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 1077 defined(BCM_56870_A0) || defined(BCM_56960_A0) || \ 1078 defined(BCM_56965_A0) || defined(BCM_56970_A0) || \ 1079 defined(BCM_56980_A0) || defined(BCM_56980_B0) 1080 { /* SOC_FORMAT_INT_IFP_CUT_THRU_OVERRIDE_SETfmt */ 1081 /* format IFP_CUT_THRU_OVERRIDE_SETfmt */ 1082 /* nFields */ 1, 1083 /* *fields */ soc_IFP_CUT_THRU_OVERRIDE_SETfmt_fields, 1084 /* bits */ 1, 1085 /* flags */ 0, 1086 }, 1087 #endif /* chips */ 1088 1089 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 1090 { /* SOC_FORMAT_INT_IFP_DELAYED_DROP_SETfmt */ 1091 /* format IFP_DELAYED_DROP_SETfmt */ 1092 /* nFields */ 2, 1093 /* *fields */ soc_IFP_DELAYED_DROP_SETfmt_fields, 1094 /* bits */ 8, 1095 /* flags */ 0, 1096 }, 1097 #endif /* chips */ 1098 1099 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 1100 { /* SOC_FORMAT_INT_IFP_DELAYED_REDIRECT_SETfmt */ 1101 /* format IFP_DELAYED_REDIRECT_SETfmt */ 1102 /* nFields */ 3, 1103 /* *fields */ soc_IFP_DELAYED_REDIRECT_SETfmt_fields, 1104 /* bits */ 16, 1105 /* flags */ 0, 1106 }, 1107 #endif /* chips */ 1108 1109 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 1110 defined(BCM_56870_A0) || defined(BCM_56970_A0) 1111 { /* SOC_FORMAT_INT_IFP_DLB_ALTERNATE_PATH_CONTROL_SETfmt */ 1112 /* format IFP_DLB_ALTERNATE_PATH_CONTROL_SETfmt */ 1113 /* nFields */ 4, 1114 /* *fields */ soc_IFP_DLB_ALTERNATE_PATH_CONTROL_SETfmt_fields, 1115 /* bits */ 10, 1116 /* flags */ 0, 1117 }, 1118 #endif /* chips */ 1119 1120 #if defined(BCM_56980_A0) 1121 { /* SOC_FORMAT_INT_IFP_DLB_ALTERNATE_PATH_CONTROL_SET_BCM56980_A0fmt */ 1122 /* format IFP_DLB_ALTERNATE_PATH_CONTROL_SETfmt */ 1123 /* nFields */ 4, 1124 /* *fields */ soc_IFP_DLB_ALTERNATE_PATH_CONTROL_SET_BCM56980_A0fmt_fields, 1125 /* bits */ 10, 1126 /* flags */ 0, 1127 }, 1128 #endif /* chips */ 1129 1130 #if defined(BCM_56980_B0) 1131 { /* SOC_FORMAT_INT_IFP_DLB_ALTERNATE_PATH_CONTROL_SET_BCM56980_B0fmt */ 1132 /* format IFP_DLB_ALTERNATE_PATH_CONTROL_SETfmt */ 1133 /* nFields */ 4, 1134 /* *fields */ soc_IFP_DLB_ALTERNATE_PATH_CONTROL_SET_BCM56980_A0fmt_fields, 1135 /* bits */ 10, 1136 /* flags */ 0, 1137 }, 1138 #endif /* chips */ 1139 1140 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 1141 { /* SOC_FORMAT_INT_IFP_DLB_ECMP_MONITOR_SETfmt */ 1142 /* format IFP_DLB_ECMP_MONITOR_SETfmt */ 1143 /* nFields */ 2, 1144 /* *fields */ soc_IFP_DLB_ECMP_MONITOR_SETfmt_fields, 1145 /* bits */ 2, 1146 /* flags */ 0, 1147 }, 1148 #endif /* chips */ 1149 1150 #if defined(BCM_56970_A0) 1151 { /* SOC_FORMAT_INT_IFP_DLB_ECMP_SETfmt */ 1152 /* format IFP_DLB_ECMP_SETfmt */ 1153 /* nFields */ 2, 1154 /* *fields */ soc_IFP_DLB_ECMP_SETfmt_fields, 1155 /* bits */ 2, 1156 /* flags */ 0, 1157 }, 1158 #endif /* chips */ 1159 1160 #if defined(BCM_56980_A0) 1161 { /* SOC_FORMAT_INT_IFP_DLB_ECMP_SET_BCM56980_A0fmt */ 1162 /* format IFP_DLB_ECMP_SETfmt */ 1163 /* nFields */ 2, 1164 /* *fields */ soc_IFP_DLB_ECMP_SET_BCM56980_A0fmt_fields, 1165 /* bits */ 2, 1166 /* flags */ 0, 1167 }, 1168 #endif /* chips */ 1169 1170 #if defined(BCM_56980_B0) 1171 { /* SOC_FORMAT_INT_IFP_DLB_ECMP_SET_BCM56980_B0fmt */ 1172 /* format IFP_DLB_ECMP_SETfmt */ 1173 /* nFields */ 2, 1174 /* *fields */ soc_IFP_DLB_ECMP_SET_BCM56980_A0fmt_fields, 1175 /* bits */ 2, 1176 /* flags */ 0, 1177 }, 1178 #endif /* chips */ 1179 1180 #if defined(BCM_56970_A0) 1181 { /* SOC_FORMAT_INT_IFP_DLB_HGT_LAG_SETfmt */ 1182 /* format IFP_DLB_HGT_LAG_SETfmt */ 1183 /* nFields */ 2, 1184 /* *fields */ soc_IFP_DLB_HGT_LAG_SETfmt_fields, 1185 /* bits */ 2, 1186 /* flags */ 0, 1187 }, 1188 #endif /* chips */ 1189 1190 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) 1191 { /* SOC_FORMAT_INT_IFP_DOPfmt */ 1192 /* format IFP_DOPfmt */ 1193 /* nFields */ 84, 1194 /* *fields */ soc_IFP_DOPfmt_fields, 1195 /* bits */ 2592, 1196 /* flags */ 0, 1197 }, 1198 #endif /* chips */ 1199 1200 #if defined(BCM_56370_A0) 1201 { /* SOC_FORMAT_INT_IFP_DOP_BCM56370_A0fmt */ 1202 /* format IFP_DOPfmt */ 1203 /* nFields */ 120, 1204 /* *fields */ soc_IFP_DOP_BCM56370_A0fmt_fields, 1205 /* bits */ 3840, 1206 /* flags */ 0, 1207 }, 1208 #endif /* chips */ 1209 1210 #if defined(BCM_56340_A0) || defined(BCM_56640_A0) 1211 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F0fmt */ 1212 /* format IFP_DOUBLE_WIDE_F0fmt */ 1213 /* nFields */ 6, 1214 /* *fields */ soc_IFP_DOUBLE_WIDE_F0fmt_fields, 1215 /* bits */ 88, 1216 /* flags */ 0, 1217 }, 1218 #endif /* chips */ 1219 1220 #if defined(BCM_56624_A0) || defined(BCM_56680_A0) 1221 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F1fmt */ 1222 /* format IFP_DOUBLE_WIDE_F1fmt */ 1223 /* nFields */ 4, 1224 /* *fields */ soc_IFP_DOUBLE_WIDE_F1fmt_fields, 1225 /* bits */ 41, 1226 /* flags */ 0, 1227 }, 1228 #endif /* chips */ 1229 1230 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \ 1231 defined(BCM_56334_B0) || defined(BCM_56440_A0) || \ 1232 defined(BCM_56440_B0) || defined(BCM_56524_A0) || \ 1233 defined(BCM_56624_A0) || defined(BCM_56624_B0) || \ 1234 defined(BCM_56634_A0) || defined(BCM_56634_B0) || \ 1235 defined(BCM_56680_A0) || defined(BCM_56685_A0) || \ 1236 defined(BCM_56725_A0) 1237 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F3fmt */ 1238 /* format IFP_DOUBLE_WIDE_F3fmt */ 1239 /* nFields */ 4, 1240 /* *fields */ soc_IFP_DOUBLE_WIDE_F3fmt_fields, 1241 /* bits */ 32, 1242 /* flags */ 0, 1243 }, 1244 #endif /* chips */ 1245 1246 #if defined(BCM_53540_A0) || defined(BCM_56160_A0) 1247 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F1_0fmt */ 1248 /* format IFP_DOUBLE_WIDE_F1_0fmt */ 1249 /* nFields */ 8, 1250 /* *fields */ soc_IFP_DOUBLE_WIDE_F1_0fmt_fields, 1251 /* bits */ 66, 1252 /* flags */ 0, 1253 }, 1254 #endif /* chips */ 1255 1256 #if defined(BCM_56340_A0) || defined(BCM_56640_A0) 1257 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F1_1fmt */ 1258 /* format IFP_DOUBLE_WIDE_F1_1fmt */ 1259 /* nFields */ 6, 1260 /* *fields */ soc_IFP_DOUBLE_WIDE_F1_1fmt_fields, 1261 /* bits */ 66, 1262 /* flags */ 0, 1263 }, 1264 #endif /* chips */ 1265 1266 #if defined(BCM_53570_A0) || defined(BCM_53570_B0) 1267 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F1_2fmt */ 1268 /* format IFP_DOUBLE_WIDE_F1_2fmt */ 1269 /* nFields */ 7, 1270 /* *fields */ soc_IFP_DOUBLE_WIDE_F1_2fmt_fields, 1271 /* bits */ 66, 1272 /* flags */ 0, 1273 }, 1274 #endif /* chips */ 1275 1276 #if defined(BCM_53570_A0) 1277 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F1_0_BCM53570_A0fmt */ 1278 /* format IFP_DOUBLE_WIDE_F1_0fmt */ 1279 /* nFields */ 8, 1280 /* *fields */ soc_IFP_DOUBLE_WIDE_F1_0_BCM53570_A0fmt_fields, 1281 /* bits */ 66, 1282 /* flags */ 0, 1283 }, 1284 #endif /* chips */ 1285 1286 #if defined(BCM_53570_B0) 1287 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F1_0_BCM53570_B0fmt */ 1288 /* format IFP_DOUBLE_WIDE_F1_0fmt */ 1289 /* nFields */ 8, 1290 /* *fields */ soc_IFP_DOUBLE_WIDE_F1_0_BCM53570_A0fmt_fields, 1291 /* bits */ 66, 1292 /* flags */ 0, 1293 }, 1294 #endif /* chips */ 1295 1296 #if defined(BCM_53540_A0) 1297 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F1_1_BCM53540_A0fmt */ 1298 /* format IFP_DOUBLE_WIDE_F1_1fmt */ 1299 /* nFields */ 5, 1300 /* *fields */ soc_IFP_DOUBLE_WIDE_F1_1_BCM56160_A0fmt_fields, 1301 /* bits */ 66, 1302 /* flags */ 0, 1303 }, 1304 #endif /* chips */ 1305 1306 #if defined(BCM_53570_A0) 1307 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F1_1_BCM53570_A0fmt */ 1308 /* format IFP_DOUBLE_WIDE_F1_1fmt */ 1309 /* nFields */ 5, 1310 /* *fields */ soc_IFP_DOUBLE_WIDE_F1_1_BCM56160_A0fmt_fields, 1311 /* bits */ 66, 1312 /* flags */ 0, 1313 }, 1314 #endif /* chips */ 1315 1316 #if defined(BCM_53570_B0) 1317 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F1_1_BCM53570_B0fmt */ 1318 /* format IFP_DOUBLE_WIDE_F1_1fmt */ 1319 /* nFields */ 5, 1320 /* *fields */ soc_IFP_DOUBLE_WIDE_F1_1_BCM56160_A0fmt_fields, 1321 /* bits */ 66, 1322 /* flags */ 0, 1323 }, 1324 #endif /* chips */ 1325 1326 #if defined(BCM_56160_A0) 1327 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F1_1_BCM56160_A0fmt */ 1328 /* format IFP_DOUBLE_WIDE_F1_1fmt */ 1329 /* nFields */ 5, 1330 /* *fields */ soc_IFP_DOUBLE_WIDE_F1_1_BCM56160_A0fmt_fields, 1331 /* bits */ 66, 1332 /* flags */ 0, 1333 }, 1334 #endif /* chips */ 1335 1336 #if defined(BCM_56260_A0) 1337 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F1_1_BCM56260_A0fmt */ 1338 /* format IFP_DOUBLE_WIDE_F1_1fmt */ 1339 /* nFields */ 5, 1340 /* *fields */ soc_IFP_DOUBLE_WIDE_F1_1_BCM56260_A0fmt_fields, 1341 /* bits */ 62, 1342 /* flags */ 0, 1343 }, 1344 #endif /* chips */ 1345 1346 #if defined(BCM_56260_B0) 1347 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F1_1_BCM56260_B0fmt */ 1348 /* format IFP_DOUBLE_WIDE_F1_1fmt */ 1349 /* nFields */ 5, 1350 /* *fields */ soc_IFP_DOUBLE_WIDE_F1_1_BCM56260_A0fmt_fields, 1351 /* bits */ 62, 1352 /* flags */ 0, 1353 }, 1354 #endif /* chips */ 1355 1356 #if defined(BCM_56270_A0) 1357 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F1_1_BCM56270_A0fmt */ 1358 /* format IFP_DOUBLE_WIDE_F1_1fmt */ 1359 /* nFields */ 5, 1360 /* *fields */ soc_IFP_DOUBLE_WIDE_F1_1_BCM56260_A0fmt_fields, 1361 /* bits */ 62, 1362 /* flags */ 0, 1363 }, 1364 #endif /* chips */ 1365 1366 #if defined(BCM_56450_A0) 1367 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F1_1_BCM56450_A0fmt */ 1368 /* format IFP_DOUBLE_WIDE_F1_1fmt */ 1369 /* nFields */ 5, 1370 /* *fields */ soc_IFP_DOUBLE_WIDE_F1_1_BCM56450_A0fmt_fields, 1371 /* bits */ 62, 1372 /* flags */ 0, 1373 }, 1374 #endif /* chips */ 1375 1376 #if defined(BCM_56450_B0) 1377 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F1_1_BCM56450_B0fmt */ 1378 /* format IFP_DOUBLE_WIDE_F1_1fmt */ 1379 /* nFields */ 5, 1380 /* *fields */ soc_IFP_DOUBLE_WIDE_F1_1_BCM56450_A0fmt_fields, 1381 /* bits */ 62, 1382 /* flags */ 0, 1383 }, 1384 #endif /* chips */ 1385 1386 #if defined(BCM_56450_B1) 1387 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F1_1_BCM56450_B1fmt */ 1388 /* format IFP_DOUBLE_WIDE_F1_1fmt */ 1389 /* nFields */ 5, 1390 /* *fields */ soc_IFP_DOUBLE_WIDE_F1_1_BCM56450_A0fmt_fields, 1391 /* bits */ 62, 1392 /* flags */ 0, 1393 }, 1394 #endif /* chips */ 1395 1396 #if defined(BCM_53400_A0) 1397 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F1_BCM53400_A0fmt */ 1398 /* format IFP_DOUBLE_WIDE_F1fmt */ 1399 /* nFields */ 8, 1400 /* *fields */ soc_IFP_DOUBLE_WIDE_F1_BCM53400_A0fmt_fields, 1401 /* bits */ 62, 1402 /* flags */ 0, 1403 }, 1404 #endif /* chips */ 1405 1406 #if defined(BCM_56142_A0) 1407 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F1_BCM56142_A0fmt */ 1408 /* format IFP_DOUBLE_WIDE_F1fmt */ 1409 /* nFields */ 7, 1410 /* *fields */ soc_IFP_DOUBLE_WIDE_F1_BCM56634_A0fmt_fields, 1411 /* bits */ 62, 1412 /* flags */ 0, 1413 }, 1414 #endif /* chips */ 1415 1416 #if defined(BCM_56150_A0) 1417 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F1_BCM56150_A0fmt */ 1418 /* format IFP_DOUBLE_WIDE_F1fmt */ 1419 /* nFields */ 7, 1420 /* *fields */ soc_IFP_DOUBLE_WIDE_F1_BCM56150_A0fmt_fields, 1421 /* bits */ 62, 1422 /* flags */ 0, 1423 }, 1424 #endif /* chips */ 1425 1426 #if defined(BCM_56260_A0) 1427 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F1_BCM56260_A0fmt */ 1428 /* format IFP_DOUBLE_WIDE_F1fmt */ 1429 /* nFields */ 7, 1430 /* *fields */ soc_IFP_DOUBLE_WIDE_F1_BCM56260_A0fmt_fields, 1431 /* bits */ 62, 1432 /* flags */ 0, 1433 }, 1434 #endif /* chips */ 1435 1436 #if defined(BCM_56260_B0) 1437 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F1_BCM56260_B0fmt */ 1438 /* format IFP_DOUBLE_WIDE_F1fmt */ 1439 /* nFields */ 7, 1440 /* *fields */ soc_IFP_DOUBLE_WIDE_F1_BCM56260_A0fmt_fields, 1441 /* bits */ 62, 1442 /* flags */ 0, 1443 }, 1444 #endif /* chips */ 1445 1446 #if defined(BCM_56270_A0) 1447 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F1_BCM56270_A0fmt */ 1448 /* format IFP_DOUBLE_WIDE_F1fmt */ 1449 /* nFields */ 7, 1450 /* *fields */ soc_IFP_DOUBLE_WIDE_F1_BCM56260_A0fmt_fields, 1451 /* bits */ 62, 1452 /* flags */ 0, 1453 }, 1454 #endif /* chips */ 1455 1456 #if defined(BCM_56334_A0) 1457 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F1_BCM56334_A0fmt */ 1458 /* format IFP_DOUBLE_WIDE_F1fmt */ 1459 /* nFields */ 7, 1460 /* *fields */ soc_IFP_DOUBLE_WIDE_F1_BCM56634_A0fmt_fields, 1461 /* bits */ 62, 1462 /* flags */ 0, 1463 }, 1464 #endif /* chips */ 1465 1466 #if defined(BCM_56334_B0) 1467 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F1_BCM56334_B0fmt */ 1468 /* format IFP_DOUBLE_WIDE_F1fmt */ 1469 /* nFields */ 7, 1470 /* *fields */ soc_IFP_DOUBLE_WIDE_F1_BCM56634_A0fmt_fields, 1471 /* bits */ 62, 1472 /* flags */ 0, 1473 }, 1474 #endif /* chips */ 1475 1476 #if defined(BCM_56340_A0) 1477 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F1_BCM56340_A0fmt */ 1478 /* format IFP_DOUBLE_WIDE_F1fmt */ 1479 /* nFields */ 7, 1480 /* *fields */ soc_IFP_DOUBLE_WIDE_F1_BCM56640_A0fmt_fields, 1481 /* bits */ 66, 1482 /* flags */ 0, 1483 }, 1484 #endif /* chips */ 1485 1486 #if defined(BCM_56440_A0) 1487 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F1_BCM56440_A0fmt */ 1488 /* format IFP_DOUBLE_WIDE_F1fmt */ 1489 /* nFields */ 7, 1490 /* *fields */ soc_IFP_DOUBLE_WIDE_F1_BCM56440_A0fmt_fields, 1491 /* bits */ 62, 1492 /* flags */ 0, 1493 }, 1494 #endif /* chips */ 1495 1496 #if defined(BCM_56440_B0) 1497 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F1_BCM56440_B0fmt */ 1498 /* format IFP_DOUBLE_WIDE_F1fmt */ 1499 /* nFields */ 7, 1500 /* *fields */ soc_IFP_DOUBLE_WIDE_F1_BCM56440_A0fmt_fields, 1501 /* bits */ 62, 1502 /* flags */ 0, 1503 }, 1504 #endif /* chips */ 1505 1506 #if defined(BCM_56450_A0) 1507 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F1_BCM56450_A0fmt */ 1508 /* format IFP_DOUBLE_WIDE_F1fmt */ 1509 /* nFields */ 7, 1510 /* *fields */ soc_IFP_DOUBLE_WIDE_F1_BCM56450_A0fmt_fields, 1511 /* bits */ 62, 1512 /* flags */ 0, 1513 }, 1514 #endif /* chips */ 1515 1516 #if defined(BCM_56450_B0) 1517 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F1_BCM56450_B0fmt */ 1518 /* format IFP_DOUBLE_WIDE_F1fmt */ 1519 /* nFields */ 7, 1520 /* *fields */ soc_IFP_DOUBLE_WIDE_F1_BCM56450_A0fmt_fields, 1521 /* bits */ 62, 1522 /* flags */ 0, 1523 }, 1524 #endif /* chips */ 1525 1526 #if defined(BCM_56450_B1) 1527 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F1_BCM56450_B1fmt */ 1528 /* format IFP_DOUBLE_WIDE_F1fmt */ 1529 /* nFields */ 7, 1530 /* *fields */ soc_IFP_DOUBLE_WIDE_F1_BCM56450_A0fmt_fields, 1531 /* bits */ 62, 1532 /* flags */ 0, 1533 }, 1534 #endif /* chips */ 1535 1536 #if defined(BCM_56524_A0) 1537 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F1_BCM56524_A0fmt */ 1538 /* format IFP_DOUBLE_WIDE_F1fmt */ 1539 /* nFields */ 7, 1540 /* *fields */ soc_IFP_DOUBLE_WIDE_F1_BCM56634_A0fmt_fields, 1541 /* bits */ 62, 1542 /* flags */ 0, 1543 }, 1544 #endif /* chips */ 1545 1546 #if defined(BCM_56524_B0) 1547 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F1_BCM56524_B0fmt */ 1548 /* format IFP_DOUBLE_WIDE_F1fmt */ 1549 /* nFields */ 7, 1550 /* *fields */ soc_IFP_DOUBLE_WIDE_F1_BCM56634_A0fmt_fields, 1551 /* bits */ 62, 1552 /* flags */ 0, 1553 }, 1554 #endif /* chips */ 1555 1556 #if defined(BCM_56624_B0) 1557 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F1_BCM56624_B0fmt */ 1558 /* format IFP_DOUBLE_WIDE_F1fmt */ 1559 /* nFields */ 4, 1560 /* *fields */ soc_IFP_DOUBLE_WIDE_F1fmt_fields, 1561 /* bits */ 41, 1562 /* flags */ 0, 1563 }, 1564 #endif /* chips */ 1565 1566 #if defined(BCM_56634_A0) 1567 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F1_BCM56634_A0fmt */ 1568 /* format IFP_DOUBLE_WIDE_F1fmt */ 1569 /* nFields */ 7, 1570 /* *fields */ soc_IFP_DOUBLE_WIDE_F1_BCM56634_A0fmt_fields, 1571 /* bits */ 62, 1572 /* flags */ 0, 1573 }, 1574 #endif /* chips */ 1575 1576 #if defined(BCM_56634_B0) 1577 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F1_BCM56634_B0fmt */ 1578 /* format IFP_DOUBLE_WIDE_F1fmt */ 1579 /* nFields */ 7, 1580 /* *fields */ soc_IFP_DOUBLE_WIDE_F1_BCM56634_A0fmt_fields, 1581 /* bits */ 62, 1582 /* flags */ 0, 1583 }, 1584 #endif /* chips */ 1585 1586 #if defined(BCM_56640_A0) 1587 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F1_BCM56640_A0fmt */ 1588 /* format IFP_DOUBLE_WIDE_F1fmt */ 1589 /* nFields */ 7, 1590 /* *fields */ soc_IFP_DOUBLE_WIDE_F1_BCM56640_A0fmt_fields, 1591 /* bits */ 66, 1592 /* flags */ 0, 1593 }, 1594 #endif /* chips */ 1595 1596 #if defined(BCM_56680_B0) 1597 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F1_BCM56680_B0fmt */ 1598 /* format IFP_DOUBLE_WIDE_F1fmt */ 1599 /* nFields */ 4, 1600 /* *fields */ soc_IFP_DOUBLE_WIDE_F1fmt_fields, 1601 /* bits */ 41, 1602 /* flags */ 0, 1603 }, 1604 #endif /* chips */ 1605 1606 #if defined(BCM_56685_A0) 1607 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F1_BCM56685_A0fmt */ 1608 /* format IFP_DOUBLE_WIDE_F1fmt */ 1609 /* nFields */ 7, 1610 /* *fields */ soc_IFP_DOUBLE_WIDE_F1_BCM56634_A0fmt_fields, 1611 /* bits */ 62, 1612 /* flags */ 0, 1613 }, 1614 #endif /* chips */ 1615 1616 #if defined(BCM_56685_B0) 1617 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F1_BCM56685_B0fmt */ 1618 /* format IFP_DOUBLE_WIDE_F1fmt */ 1619 /* nFields */ 7, 1620 /* *fields */ soc_IFP_DOUBLE_WIDE_F1_BCM56634_A0fmt_fields, 1621 /* bits */ 62, 1622 /* flags */ 0, 1623 }, 1624 #endif /* chips */ 1625 1626 #if defined(BCM_56725_A0) 1627 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F1_BCM56725_A0fmt */ 1628 /* format IFP_DOUBLE_WIDE_F1fmt */ 1629 /* nFields */ 4, 1630 /* *fields */ soc_IFP_DOUBLE_WIDE_F1fmt_fields, 1631 /* bits */ 41, 1632 /* flags */ 0, 1633 }, 1634 #endif /* chips */ 1635 1636 #if defined(BCM_56820_A0) 1637 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F1_BCM56820_A0fmt */ 1638 /* format IFP_DOUBLE_WIDE_F1fmt */ 1639 /* nFields */ 4, 1640 /* *fields */ soc_IFP_DOUBLE_WIDE_F1fmt_fields, 1641 /* bits */ 41, 1642 /* flags */ 0, 1643 }, 1644 #endif /* chips */ 1645 1646 #if defined(BCM_88732_A0) 1647 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F1_BCM88732_A0fmt */ 1648 /* format IFP_DOUBLE_WIDE_F1fmt */ 1649 /* nFields */ 4, 1650 /* *fields */ soc_IFP_DOUBLE_WIDE_F1fmt_fields, 1651 /* bits */ 41, 1652 /* flags */ 0, 1653 }, 1654 #endif /* chips */ 1655 1656 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \ 1657 defined(BCM_56680_A0) || defined(BCM_56725_A0) || \ 1658 defined(BCM_56820_A0) 1659 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_0fmt */ 1660 /* format IFP_DOUBLE_WIDE_F2_0fmt */ 1661 /* nFields */ 6, 1662 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_0fmt_fields, 1663 /* bits */ 128, 1664 /* flags */ 0, 1665 }, 1666 #endif /* chips */ 1667 1668 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \ 1669 defined(BCM_56334_B0) || defined(BCM_56440_A0) || \ 1670 defined(BCM_56440_B0) || defined(BCM_56524_A0) || \ 1671 defined(BCM_56524_B0) || defined(BCM_56624_A0) || \ 1672 defined(BCM_56624_B0) || defined(BCM_56634_B0) || \ 1673 defined(BCM_56680_A0) || defined(BCM_56680_B0) || \ 1674 defined(BCM_56685_A0) || defined(BCM_56685_B0) || \ 1675 defined(BCM_56725_A0) || defined(BCM_56820_A0) 1676 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_1fmt */ 1677 /* format IFP_DOUBLE_WIDE_F2_1fmt */ 1678 /* nFields */ 1, 1679 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_1fmt_fields, 1680 /* bits */ 128, 1681 /* flags */ 0, 1682 }, 1683 #endif /* chips */ 1684 1685 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \ 1686 defined(BCM_56680_A0) || defined(BCM_56680_B0) || \ 1687 defined(BCM_56725_A0) || defined(BCM_56820_A0) || \ 1688 defined(BCM_88732_A0) 1689 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_2fmt */ 1690 /* format IFP_DOUBLE_WIDE_F2_2fmt */ 1691 /* nFields */ 1, 1692 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_2fmt_fields, 1693 /* bits */ 128, 1694 /* flags */ 0, 1695 }, 1696 #endif /* chips */ 1697 1698 #if defined(BCM_56634_A0) 1699 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_3fmt */ 1700 /* format IFP_DOUBLE_WIDE_F2_3fmt */ 1701 /* nFields */ 1, 1702 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_2fmt_fields, 1703 /* bits */ 128, 1704 /* flags */ 0, 1705 }, 1706 #endif /* chips */ 1707 1708 #if defined(BCM_53540_A0) || defined(BCM_53570_A0) || \ 1709 defined(BCM_53570_B0) || defined(BCM_56160_A0) 1710 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_4fmt */ 1711 /* format IFP_DOUBLE_WIDE_F2_4fmt */ 1712 /* nFields */ 4, 1713 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_4fmt_fields, 1714 /* bits */ 128, 1715 /* flags */ 0, 1716 }, 1717 #endif /* chips */ 1718 1719 #if defined(BCM_53540_A0) || defined(BCM_53570_A0) || \ 1720 defined(BCM_53570_B0) || defined(BCM_56160_A0) 1721 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_5fmt */ 1722 /* format IFP_DOUBLE_WIDE_F2_5fmt */ 1723 /* nFields */ 7, 1724 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_5fmt_fields, 1725 /* bits */ 128, 1726 /* flags */ 0, 1727 }, 1728 #endif /* chips */ 1729 1730 #if defined(BCM_53540_A0) || defined(BCM_53570_A0) || \ 1731 defined(BCM_53570_B0) || defined(BCM_56160_A0) 1732 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_6fmt */ 1733 /* format IFP_DOUBLE_WIDE_F2_6fmt */ 1734 /* nFields */ 1, 1735 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_6fmt_fields, 1736 /* bits */ 128, 1737 /* flags */ 0, 1738 }, 1739 #endif /* chips */ 1740 1741 #if defined(BCM_53540_A0) || defined(BCM_53570_A0) || \ 1742 defined(BCM_53570_B0) || defined(BCM_56160_A0) 1743 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_7fmt */ 1744 /* format IFP_DOUBLE_WIDE_F2_7fmt */ 1745 /* nFields */ 1, 1746 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_7fmt_fields, 1747 /* bits */ 128, 1748 /* flags */ 0, 1749 }, 1750 #endif /* chips */ 1751 1752 #if defined(BCM_53400_A0) 1753 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_0_BCM53400_A0fmt */ 1754 /* format IFP_DOUBLE_WIDE_F2_0fmt */ 1755 /* nFields */ 6, 1756 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_0_BCM53400_A0fmt_fields, 1757 /* bits */ 128, 1758 /* flags */ 0, 1759 }, 1760 #endif /* chips */ 1761 1762 #if defined(BCM_53540_A0) 1763 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_0_BCM53540_A0fmt */ 1764 /* format IFP_DOUBLE_WIDE_F2_0fmt */ 1765 /* nFields */ 6, 1766 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_0_BCM53400_A0fmt_fields, 1767 /* bits */ 128, 1768 /* flags */ 0, 1769 }, 1770 #endif /* chips */ 1771 1772 #if defined(BCM_53570_A0) 1773 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_0_BCM53570_A0fmt */ 1774 /* format IFP_DOUBLE_WIDE_F2_0fmt */ 1775 /* nFields */ 6, 1776 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_0_BCM53400_A0fmt_fields, 1777 /* bits */ 128, 1778 /* flags */ 0, 1779 }, 1780 #endif /* chips */ 1781 1782 #if defined(BCM_53570_B0) 1783 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_0_BCM53570_B0fmt */ 1784 /* format IFP_DOUBLE_WIDE_F2_0fmt */ 1785 /* nFields */ 6, 1786 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_0_BCM53400_A0fmt_fields, 1787 /* bits */ 128, 1788 /* flags */ 0, 1789 }, 1790 #endif /* chips */ 1791 1792 #if defined(BCM_56142_A0) 1793 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_0_BCM56142_A0fmt */ 1794 /* format IFP_DOUBLE_WIDE_F2_0fmt */ 1795 /* nFields */ 6, 1796 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_0_BCM56634_A0fmt_fields, 1797 /* bits */ 128, 1798 /* flags */ 0, 1799 }, 1800 #endif /* chips */ 1801 1802 #if defined(BCM_56150_A0) 1803 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_0_BCM56150_A0fmt */ 1804 /* format IFP_DOUBLE_WIDE_F2_0fmt */ 1805 /* nFields */ 6, 1806 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_0_BCM56150_A0fmt_fields, 1807 /* bits */ 128, 1808 /* flags */ 0, 1809 }, 1810 #endif /* chips */ 1811 1812 #if defined(BCM_56160_A0) 1813 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_0_BCM56160_A0fmt */ 1814 /* format IFP_DOUBLE_WIDE_F2_0fmt */ 1815 /* nFields */ 6, 1816 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_0_BCM53400_A0fmt_fields, 1817 /* bits */ 128, 1818 /* flags */ 0, 1819 }, 1820 #endif /* chips */ 1821 1822 #if defined(BCM_56260_A0) 1823 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_0_BCM56260_A0fmt */ 1824 /* format IFP_DOUBLE_WIDE_F2_0fmt */ 1825 /* nFields */ 6, 1826 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_0_BCM56260_A0fmt_fields, 1827 /* bits */ 128, 1828 /* flags */ 0, 1829 }, 1830 #endif /* chips */ 1831 1832 #if defined(BCM_56260_B0) 1833 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_0_BCM56260_B0fmt */ 1834 /* format IFP_DOUBLE_WIDE_F2_0fmt */ 1835 /* nFields */ 6, 1836 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_0_BCM56260_A0fmt_fields, 1837 /* bits */ 128, 1838 /* flags */ 0, 1839 }, 1840 #endif /* chips */ 1841 1842 #if defined(BCM_56270_A0) 1843 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_0_BCM56270_A0fmt */ 1844 /* format IFP_DOUBLE_WIDE_F2_0fmt */ 1845 /* nFields */ 6, 1846 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_0_BCM56260_A0fmt_fields, 1847 /* bits */ 128, 1848 /* flags */ 0, 1849 }, 1850 #endif /* chips */ 1851 1852 #if defined(BCM_56334_A0) 1853 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_0_BCM56334_A0fmt */ 1854 /* format IFP_DOUBLE_WIDE_F2_0fmt */ 1855 /* nFields */ 6, 1856 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_0_BCM56634_A0fmt_fields, 1857 /* bits */ 128, 1858 /* flags */ 0, 1859 }, 1860 #endif /* chips */ 1861 1862 #if defined(BCM_56334_B0) 1863 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_0_BCM56334_B0fmt */ 1864 /* format IFP_DOUBLE_WIDE_F2_0fmt */ 1865 /* nFields */ 6, 1866 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_0_BCM56634_A0fmt_fields, 1867 /* bits */ 128, 1868 /* flags */ 0, 1869 }, 1870 #endif /* chips */ 1871 1872 #if defined(BCM_56340_A0) 1873 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_0_BCM56340_A0fmt */ 1874 /* format IFP_DOUBLE_WIDE_F2_0fmt */ 1875 /* nFields */ 7, 1876 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_0_BCM56640_A0fmt_fields, 1877 /* bits */ 128, 1878 /* flags */ 0, 1879 }, 1880 #endif /* chips */ 1881 1882 #if defined(BCM_56440_A0) 1883 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_0_BCM56440_A0fmt */ 1884 /* format IFP_DOUBLE_WIDE_F2_0fmt */ 1885 /* nFields */ 6, 1886 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_0_BCM56634_A0fmt_fields, 1887 /* bits */ 128, 1888 /* flags */ 0, 1889 }, 1890 #endif /* chips */ 1891 1892 #if defined(BCM_56440_B0) 1893 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_0_BCM56440_B0fmt */ 1894 /* format IFP_DOUBLE_WIDE_F2_0fmt */ 1895 /* nFields */ 6, 1896 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_0_BCM56634_A0fmt_fields, 1897 /* bits */ 128, 1898 /* flags */ 0, 1899 }, 1900 #endif /* chips */ 1901 1902 #if defined(BCM_56450_A0) 1903 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_0_BCM56450_A0fmt */ 1904 /* format IFP_DOUBLE_WIDE_F2_0fmt */ 1905 /* nFields */ 6, 1906 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_0_BCM56450_A0fmt_fields, 1907 /* bits */ 128, 1908 /* flags */ 0, 1909 }, 1910 #endif /* chips */ 1911 1912 #if defined(BCM_56450_B0) 1913 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_0_BCM56450_B0fmt */ 1914 /* format IFP_DOUBLE_WIDE_F2_0fmt */ 1915 /* nFields */ 6, 1916 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_0_BCM56450_A0fmt_fields, 1917 /* bits */ 128, 1918 /* flags */ 0, 1919 }, 1920 #endif /* chips */ 1921 1922 #if defined(BCM_56450_B1) 1923 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_0_BCM56450_B1fmt */ 1924 /* format IFP_DOUBLE_WIDE_F2_0fmt */ 1925 /* nFields */ 6, 1926 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_0_BCM56450_A0fmt_fields, 1927 /* bits */ 128, 1928 /* flags */ 0, 1929 }, 1930 #endif /* chips */ 1931 1932 #if defined(BCM_56524_A0) 1933 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_0_BCM56524_A0fmt */ 1934 /* format IFP_DOUBLE_WIDE_F2_0fmt */ 1935 /* nFields */ 6, 1936 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_0_BCM56634_A0fmt_fields, 1937 /* bits */ 128, 1938 /* flags */ 0, 1939 }, 1940 #endif /* chips */ 1941 1942 #if defined(BCM_56524_B0) 1943 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_0_BCM56524_B0fmt */ 1944 /* format IFP_DOUBLE_WIDE_F2_0fmt */ 1945 /* nFields */ 6, 1946 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_0_BCM56634_A0fmt_fields, 1947 /* bits */ 128, 1948 /* flags */ 0, 1949 }, 1950 #endif /* chips */ 1951 1952 #if defined(BCM_56634_A0) 1953 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_0_BCM56634_A0fmt */ 1954 /* format IFP_DOUBLE_WIDE_F2_0fmt */ 1955 /* nFields */ 6, 1956 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_0_BCM56634_A0fmt_fields, 1957 /* bits */ 128, 1958 /* flags */ 0, 1959 }, 1960 #endif /* chips */ 1961 1962 #if defined(BCM_56634_B0) 1963 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_0_BCM56634_B0fmt */ 1964 /* format IFP_DOUBLE_WIDE_F2_0fmt */ 1965 /* nFields */ 6, 1966 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_0_BCM56634_A0fmt_fields, 1967 /* bits */ 128, 1968 /* flags */ 0, 1969 }, 1970 #endif /* chips */ 1971 1972 #if defined(BCM_56640_A0) 1973 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_0_BCM56640_A0fmt */ 1974 /* format IFP_DOUBLE_WIDE_F2_0fmt */ 1975 /* nFields */ 7, 1976 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_0_BCM56640_A0fmt_fields, 1977 /* bits */ 128, 1978 /* flags */ 0, 1979 }, 1980 #endif /* chips */ 1981 1982 #if defined(BCM_56680_B0) 1983 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_0_BCM56680_B0fmt */ 1984 /* format IFP_DOUBLE_WIDE_F2_0fmt */ 1985 /* nFields */ 6, 1986 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_0fmt_fields, 1987 /* bits */ 128, 1988 /* flags */ 0, 1989 }, 1990 #endif /* chips */ 1991 1992 #if defined(BCM_56685_A0) 1993 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_0_BCM56685_A0fmt */ 1994 /* format IFP_DOUBLE_WIDE_F2_0fmt */ 1995 /* nFields */ 6, 1996 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_0_BCM56634_A0fmt_fields, 1997 /* bits */ 128, 1998 /* flags */ 0, 1999 }, 2000 #endif /* chips */ 2001 2002 #if defined(BCM_56685_B0) 2003 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_0_BCM56685_B0fmt */ 2004 /* format IFP_DOUBLE_WIDE_F2_0fmt */ 2005 /* nFields */ 6, 2006 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_0_BCM56634_A0fmt_fields, 2007 /* bits */ 128, 2008 /* flags */ 0, 2009 }, 2010 #endif /* chips */ 2011 2012 #if defined(BCM_88732_A0) 2013 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_0_BCM88732_A0fmt */ 2014 /* format IFP_DOUBLE_WIDE_F2_0fmt */ 2015 /* nFields */ 6, 2016 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_0_BCM88732_A0fmt_fields, 2017 /* bits */ 128, 2018 /* flags */ 0, 2019 }, 2020 #endif /* chips */ 2021 2022 #if defined(BCM_53400_A0) 2023 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_1_BCM53400_A0fmt */ 2024 /* format IFP_DOUBLE_WIDE_F2_1fmt */ 2025 /* nFields */ 1, 2026 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_1_BCM53400_A0fmt_fields, 2027 /* bits */ 128, 2028 /* flags */ 0, 2029 }, 2030 #endif /* chips */ 2031 2032 #if defined(BCM_53540_A0) 2033 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_1_BCM53540_A0fmt */ 2034 /* format IFP_DOUBLE_WIDE_F2_1fmt */ 2035 /* nFields */ 1, 2036 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_1_BCM53400_A0fmt_fields, 2037 /* bits */ 128, 2038 /* flags */ 0, 2039 }, 2040 #endif /* chips */ 2041 2042 #if defined(BCM_53570_A0) 2043 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_1_BCM53570_A0fmt */ 2044 /* format IFP_DOUBLE_WIDE_F2_1fmt */ 2045 /* nFields */ 1, 2046 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_1_BCM53400_A0fmt_fields, 2047 /* bits */ 128, 2048 /* flags */ 0, 2049 }, 2050 #endif /* chips */ 2051 2052 #if defined(BCM_53570_B0) 2053 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_1_BCM53570_B0fmt */ 2054 /* format IFP_DOUBLE_WIDE_F2_1fmt */ 2055 /* nFields */ 1, 2056 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_1_BCM53400_A0fmt_fields, 2057 /* bits */ 128, 2058 /* flags */ 0, 2059 }, 2060 #endif /* chips */ 2061 2062 #if defined(BCM_56150_A0) 2063 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_1_BCM56150_A0fmt */ 2064 /* format IFP_DOUBLE_WIDE_F2_1fmt */ 2065 /* nFields */ 1, 2066 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_1_BCM56640_A0fmt_fields, 2067 /* bits */ 128, 2068 /* flags */ 0, 2069 }, 2070 #endif /* chips */ 2071 2072 #if defined(BCM_56160_A0) 2073 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_1_BCM56160_A0fmt */ 2074 /* format IFP_DOUBLE_WIDE_F2_1fmt */ 2075 /* nFields */ 1, 2076 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_1_BCM53400_A0fmt_fields, 2077 /* bits */ 128, 2078 /* flags */ 0, 2079 }, 2080 #endif /* chips */ 2081 2082 #if defined(BCM_56260_A0) 2083 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_1_BCM56260_A0fmt */ 2084 /* format IFP_DOUBLE_WIDE_F2_1fmt */ 2085 /* nFields */ 1, 2086 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_1_BCM53400_A0fmt_fields, 2087 /* bits */ 128, 2088 /* flags */ 0, 2089 }, 2090 #endif /* chips */ 2091 2092 #if defined(BCM_56260_B0) 2093 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_1_BCM56260_B0fmt */ 2094 /* format IFP_DOUBLE_WIDE_F2_1fmt */ 2095 /* nFields */ 1, 2096 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_1_BCM53400_A0fmt_fields, 2097 /* bits */ 128, 2098 /* flags */ 0, 2099 }, 2100 #endif /* chips */ 2101 2102 #if defined(BCM_56270_A0) 2103 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_1_BCM56270_A0fmt */ 2104 /* format IFP_DOUBLE_WIDE_F2_1fmt */ 2105 /* nFields */ 1, 2106 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_1_BCM53400_A0fmt_fields, 2107 /* bits */ 128, 2108 /* flags */ 0, 2109 }, 2110 #endif /* chips */ 2111 2112 #if defined(BCM_56340_A0) 2113 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_1_BCM56340_A0fmt */ 2114 /* format IFP_DOUBLE_WIDE_F2_1fmt */ 2115 /* nFields */ 1, 2116 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_1_BCM56640_A0fmt_fields, 2117 /* bits */ 128, 2118 /* flags */ 0, 2119 }, 2120 #endif /* chips */ 2121 2122 #if defined(BCM_56450_A0) 2123 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_1_BCM56450_A0fmt */ 2124 /* format IFP_DOUBLE_WIDE_F2_1fmt */ 2125 /* nFields */ 1, 2126 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_1_BCM56640_A0fmt_fields, 2127 /* bits */ 128, 2128 /* flags */ 0, 2129 }, 2130 #endif /* chips */ 2131 2132 #if defined(BCM_56450_B0) 2133 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_1_BCM56450_B0fmt */ 2134 /* format IFP_DOUBLE_WIDE_F2_1fmt */ 2135 /* nFields */ 1, 2136 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_1_BCM56640_A0fmt_fields, 2137 /* bits */ 128, 2138 /* flags */ 0, 2139 }, 2140 #endif /* chips */ 2141 2142 #if defined(BCM_56450_B1) 2143 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_1_BCM56450_B1fmt */ 2144 /* format IFP_DOUBLE_WIDE_F2_1fmt */ 2145 /* nFields */ 1, 2146 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_1_BCM56640_A0fmt_fields, 2147 /* bits */ 128, 2148 /* flags */ 0, 2149 }, 2150 #endif /* chips */ 2151 2152 #if defined(BCM_56634_A0) 2153 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_1_BCM56634_A0fmt */ 2154 /* format IFP_DOUBLE_WIDE_F2_1fmt */ 2155 /* nFields */ 1, 2156 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_1fmt_fields, 2157 /* bits */ 128, 2158 /* flags */ 0, 2159 }, 2160 #endif /* chips */ 2161 2162 #if defined(BCM_56640_A0) 2163 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_1_BCM56640_A0fmt */ 2164 /* format IFP_DOUBLE_WIDE_F2_1fmt */ 2165 /* nFields */ 1, 2166 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_1_BCM56640_A0fmt_fields, 2167 /* bits */ 128, 2168 /* flags */ 0, 2169 }, 2170 #endif /* chips */ 2171 2172 #if defined(BCM_88732_A0) 2173 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_1_BCM88732_A0fmt */ 2174 /* format IFP_DOUBLE_WIDE_F2_1fmt */ 2175 /* nFields */ 1, 2176 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_1_BCM88732_A0fmt_fields, 2177 /* bits */ 132, 2178 /* flags */ 0, 2179 }, 2180 #endif /* chips */ 2181 2182 #if defined(BCM_53400_A0) 2183 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_2_BCM53400_A0fmt */ 2184 /* format IFP_DOUBLE_WIDE_F2_2fmt */ 2185 /* nFields */ 1, 2186 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_2_BCM53400_A0fmt_fields, 2187 /* bits */ 128, 2188 /* flags */ 0, 2189 }, 2190 #endif /* chips */ 2191 2192 #if defined(BCM_53540_A0) 2193 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_2_BCM53540_A0fmt */ 2194 /* format IFP_DOUBLE_WIDE_F2_2fmt */ 2195 /* nFields */ 1, 2196 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_2_BCM53400_A0fmt_fields, 2197 /* bits */ 128, 2198 /* flags */ 0, 2199 }, 2200 #endif /* chips */ 2201 2202 #if defined(BCM_53570_A0) 2203 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_2_BCM53570_A0fmt */ 2204 /* format IFP_DOUBLE_WIDE_F2_2fmt */ 2205 /* nFields */ 1, 2206 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_2_BCM53400_A0fmt_fields, 2207 /* bits */ 128, 2208 /* flags */ 0, 2209 }, 2210 #endif /* chips */ 2211 2212 #if defined(BCM_53570_B0) 2213 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_2_BCM53570_B0fmt */ 2214 /* format IFP_DOUBLE_WIDE_F2_2fmt */ 2215 /* nFields */ 1, 2216 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_2_BCM53400_A0fmt_fields, 2217 /* bits */ 128, 2218 /* flags */ 0, 2219 }, 2220 #endif /* chips */ 2221 2222 #if defined(BCM_56142_A0) 2223 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_2_BCM56142_A0fmt */ 2224 /* format IFP_DOUBLE_WIDE_F2_2fmt */ 2225 /* nFields */ 1, 2226 /* *fields */ soc_IFP_SINGLE_WIDE_F2_3fmt_fields, 2227 /* bits */ 128, 2228 /* flags */ 0, 2229 }, 2230 #endif /* chips */ 2231 2232 #if defined(BCM_56150_A0) 2233 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_2_BCM56150_A0fmt */ 2234 /* format IFP_DOUBLE_WIDE_F2_2fmt */ 2235 /* nFields */ 1, 2236 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_2_BCM56640_A0fmt_fields, 2237 /* bits */ 128, 2238 /* flags */ 0, 2239 }, 2240 #endif /* chips */ 2241 2242 #if defined(BCM_56160_A0) 2243 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_2_BCM56160_A0fmt */ 2244 /* format IFP_DOUBLE_WIDE_F2_2fmt */ 2245 /* nFields */ 1, 2246 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_2_BCM53400_A0fmt_fields, 2247 /* bits */ 128, 2248 /* flags */ 0, 2249 }, 2250 #endif /* chips */ 2251 2252 #if defined(BCM_56260_A0) 2253 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_2_BCM56260_A0fmt */ 2254 /* format IFP_DOUBLE_WIDE_F2_2fmt */ 2255 /* nFields */ 1, 2256 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_2_BCM53400_A0fmt_fields, 2257 /* bits */ 128, 2258 /* flags */ 0, 2259 }, 2260 #endif /* chips */ 2261 2262 #if defined(BCM_56260_B0) 2263 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_2_BCM56260_B0fmt */ 2264 /* format IFP_DOUBLE_WIDE_F2_2fmt */ 2265 /* nFields */ 1, 2266 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_2_BCM53400_A0fmt_fields, 2267 /* bits */ 128, 2268 /* flags */ 0, 2269 }, 2270 #endif /* chips */ 2271 2272 #if defined(BCM_56270_A0) 2273 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_2_BCM56270_A0fmt */ 2274 /* format IFP_DOUBLE_WIDE_F2_2fmt */ 2275 /* nFields */ 1, 2276 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_2_BCM53400_A0fmt_fields, 2277 /* bits */ 128, 2278 /* flags */ 0, 2279 }, 2280 #endif /* chips */ 2281 2282 #if defined(BCM_56334_A0) 2283 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_2_BCM56334_A0fmt */ 2284 /* format IFP_DOUBLE_WIDE_F2_2fmt */ 2285 /* nFields */ 1, 2286 /* *fields */ soc_IFP_SINGLE_WIDE_F2_3fmt_fields, 2287 /* bits */ 128, 2288 /* flags */ 0, 2289 }, 2290 #endif /* chips */ 2291 2292 #if defined(BCM_56334_B0) 2293 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_2_BCM56334_B0fmt */ 2294 /* format IFP_DOUBLE_WIDE_F2_2fmt */ 2295 /* nFields */ 1, 2296 /* *fields */ soc_IFP_SINGLE_WIDE_F2_3fmt_fields, 2297 /* bits */ 128, 2298 /* flags */ 0, 2299 }, 2300 #endif /* chips */ 2301 2302 #if defined(BCM_56340_A0) 2303 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_2_BCM56340_A0fmt */ 2304 /* format IFP_DOUBLE_WIDE_F2_2fmt */ 2305 /* nFields */ 1, 2306 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_2_BCM56640_A0fmt_fields, 2307 /* bits */ 128, 2308 /* flags */ 0, 2309 }, 2310 #endif /* chips */ 2311 2312 #if defined(BCM_56440_A0) 2313 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_2_BCM56440_A0fmt */ 2314 /* format IFP_DOUBLE_WIDE_F2_2fmt */ 2315 /* nFields */ 1, 2316 /* *fields */ soc_IFP_SINGLE_WIDE_F2_3fmt_fields, 2317 /* bits */ 128, 2318 /* flags */ 0, 2319 }, 2320 #endif /* chips */ 2321 2322 #if defined(BCM_56440_B0) 2323 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_2_BCM56440_B0fmt */ 2324 /* format IFP_DOUBLE_WIDE_F2_2fmt */ 2325 /* nFields */ 1, 2326 /* *fields */ soc_IFP_SINGLE_WIDE_F2_3fmt_fields, 2327 /* bits */ 128, 2328 /* flags */ 0, 2329 }, 2330 #endif /* chips */ 2331 2332 #if defined(BCM_56450_A0) 2333 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_2_BCM56450_A0fmt */ 2334 /* format IFP_DOUBLE_WIDE_F2_2fmt */ 2335 /* nFields */ 1, 2336 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_2_BCM56640_A0fmt_fields, 2337 /* bits */ 128, 2338 /* flags */ 0, 2339 }, 2340 #endif /* chips */ 2341 2342 #if defined(BCM_56450_B0) 2343 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_2_BCM56450_B0fmt */ 2344 /* format IFP_DOUBLE_WIDE_F2_2fmt */ 2345 /* nFields */ 1, 2346 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_2_BCM56640_A0fmt_fields, 2347 /* bits */ 128, 2348 /* flags */ 0, 2349 }, 2350 #endif /* chips */ 2351 2352 #if defined(BCM_56450_B1) 2353 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_2_BCM56450_B1fmt */ 2354 /* format IFP_DOUBLE_WIDE_F2_2fmt */ 2355 /* nFields */ 1, 2356 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_2_BCM56640_A0fmt_fields, 2357 /* bits */ 128, 2358 /* flags */ 0, 2359 }, 2360 #endif /* chips */ 2361 2362 #if defined(BCM_56524_A0) 2363 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_2_BCM56524_A0fmt */ 2364 /* format IFP_DOUBLE_WIDE_F2_2fmt */ 2365 /* nFields */ 1, 2366 /* *fields */ soc_IFP_SINGLE_WIDE_F2_3fmt_fields, 2367 /* bits */ 128, 2368 /* flags */ 0, 2369 }, 2370 #endif /* chips */ 2371 2372 #if defined(BCM_56524_B0) 2373 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_2_BCM56524_B0fmt */ 2374 /* format IFP_DOUBLE_WIDE_F2_2fmt */ 2375 /* nFields */ 1, 2376 /* *fields */ soc_IFP_SINGLE_WIDE_F2_3fmt_fields, 2377 /* bits */ 128, 2378 /* flags */ 0, 2379 }, 2380 #endif /* chips */ 2381 2382 #if defined(BCM_56634_A0) 2383 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_2_BCM56634_A0fmt */ 2384 /* format IFP_DOUBLE_WIDE_F2_2fmt */ 2385 /* nFields */ 1, 2386 /* *fields */ soc_IFP_SINGLE_WIDE_F2_3fmt_fields, 2387 /* bits */ 128, 2388 /* flags */ 0, 2389 }, 2390 #endif /* chips */ 2391 2392 #if defined(BCM_56634_B0) 2393 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_2_BCM56634_B0fmt */ 2394 /* format IFP_DOUBLE_WIDE_F2_2fmt */ 2395 /* nFields */ 1, 2396 /* *fields */ soc_IFP_SINGLE_WIDE_F2_3fmt_fields, 2397 /* bits */ 128, 2398 /* flags */ 0, 2399 }, 2400 #endif /* chips */ 2401 2402 #if defined(BCM_56640_A0) 2403 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_2_BCM56640_A0fmt */ 2404 /* format IFP_DOUBLE_WIDE_F2_2fmt */ 2405 /* nFields */ 1, 2406 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_2_BCM56640_A0fmt_fields, 2407 /* bits */ 128, 2408 /* flags */ 0, 2409 }, 2410 #endif /* chips */ 2411 2412 #if defined(BCM_56685_A0) 2413 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_2_BCM56685_A0fmt */ 2414 /* format IFP_DOUBLE_WIDE_F2_2fmt */ 2415 /* nFields */ 1, 2416 /* *fields */ soc_IFP_SINGLE_WIDE_F2_3fmt_fields, 2417 /* bits */ 128, 2418 /* flags */ 0, 2419 }, 2420 #endif /* chips */ 2421 2422 #if defined(BCM_56685_B0) 2423 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_2_BCM56685_B0fmt */ 2424 /* format IFP_DOUBLE_WIDE_F2_2fmt */ 2425 /* nFields */ 1, 2426 /* *fields */ soc_IFP_SINGLE_WIDE_F2_3fmt_fields, 2427 /* bits */ 128, 2428 /* flags */ 0, 2429 }, 2430 #endif /* chips */ 2431 2432 #if defined(BCM_53400_A0) 2433 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_3_BCM53400_A0fmt */ 2434 /* format IFP_DOUBLE_WIDE_F2_3fmt */ 2435 /* nFields */ 1, 2436 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_3_BCM53400_A0fmt_fields, 2437 /* bits */ 128, 2438 /* flags */ 0, 2439 }, 2440 #endif /* chips */ 2441 2442 #if defined(BCM_53540_A0) 2443 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_3_BCM53540_A0fmt */ 2444 /* format IFP_DOUBLE_WIDE_F2_3fmt */ 2445 /* nFields */ 1, 2446 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_3_BCM53400_A0fmt_fields, 2447 /* bits */ 128, 2448 /* flags */ 0, 2449 }, 2450 #endif /* chips */ 2451 2452 #if defined(BCM_53570_A0) 2453 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_3_BCM53570_A0fmt */ 2454 /* format IFP_DOUBLE_WIDE_F2_3fmt */ 2455 /* nFields */ 1, 2456 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_3_BCM53400_A0fmt_fields, 2457 /* bits */ 128, 2458 /* flags */ 0, 2459 }, 2460 #endif /* chips */ 2461 2462 #if defined(BCM_53570_B0) 2463 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_3_BCM53570_B0fmt */ 2464 /* format IFP_DOUBLE_WIDE_F2_3fmt */ 2465 /* nFields */ 1, 2466 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_3_BCM53400_A0fmt_fields, 2467 /* bits */ 128, 2468 /* flags */ 0, 2469 }, 2470 #endif /* chips */ 2471 2472 #if defined(BCM_56142_A0) 2473 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_3_BCM56142_A0fmt */ 2474 /* format IFP_DOUBLE_WIDE_F2_3fmt */ 2475 /* nFields */ 1, 2476 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_2fmt_fields, 2477 /* bits */ 128, 2478 /* flags */ 0, 2479 }, 2480 #endif /* chips */ 2481 2482 #if defined(BCM_56150_A0) 2483 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_3_BCM56150_A0fmt */ 2484 /* format IFP_DOUBLE_WIDE_F2_3fmt */ 2485 /* nFields */ 1, 2486 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_3fmt_fields, 2487 /* bits */ 128, 2488 /* flags */ 0, 2489 }, 2490 #endif /* chips */ 2491 2492 #if defined(BCM_56160_A0) 2493 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_3_BCM56160_A0fmt */ 2494 /* format IFP_DOUBLE_WIDE_F2_3fmt */ 2495 /* nFields */ 1, 2496 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_3_BCM53400_A0fmt_fields, 2497 /* bits */ 128, 2498 /* flags */ 0, 2499 }, 2500 #endif /* chips */ 2501 2502 #if defined(BCM_56260_A0) 2503 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_3_BCM56260_A0fmt */ 2504 /* format IFP_DOUBLE_WIDE_F2_3fmt */ 2505 /* nFields */ 1, 2506 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_3_BCM53400_A0fmt_fields, 2507 /* bits */ 128, 2508 /* flags */ 0, 2509 }, 2510 #endif /* chips */ 2511 2512 #if defined(BCM_56260_B0) 2513 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_3_BCM56260_B0fmt */ 2514 /* format IFP_DOUBLE_WIDE_F2_3fmt */ 2515 /* nFields */ 1, 2516 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_3_BCM53400_A0fmt_fields, 2517 /* bits */ 128, 2518 /* flags */ 0, 2519 }, 2520 #endif /* chips */ 2521 2522 #if defined(BCM_56270_A0) 2523 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_3_BCM56270_A0fmt */ 2524 /* format IFP_DOUBLE_WIDE_F2_3fmt */ 2525 /* nFields */ 1, 2526 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_3_BCM53400_A0fmt_fields, 2527 /* bits */ 128, 2528 /* flags */ 0, 2529 }, 2530 #endif /* chips */ 2531 2532 #if defined(BCM_56334_A0) 2533 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_3_BCM56334_A0fmt */ 2534 /* format IFP_DOUBLE_WIDE_F2_3fmt */ 2535 /* nFields */ 1, 2536 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_2fmt_fields, 2537 /* bits */ 128, 2538 /* flags */ 0, 2539 }, 2540 #endif /* chips */ 2541 2542 #if defined(BCM_56334_B0) 2543 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_3_BCM56334_B0fmt */ 2544 /* format IFP_DOUBLE_WIDE_F2_3fmt */ 2545 /* nFields */ 1, 2546 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_2fmt_fields, 2547 /* bits */ 128, 2548 /* flags */ 0, 2549 }, 2550 #endif /* chips */ 2551 2552 #if defined(BCM_56340_A0) 2553 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_3_BCM56340_A0fmt */ 2554 /* format IFP_DOUBLE_WIDE_F2_3fmt */ 2555 /* nFields */ 1, 2556 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_3fmt_fields, 2557 /* bits */ 128, 2558 /* flags */ 0, 2559 }, 2560 #endif /* chips */ 2561 2562 #if defined(BCM_56440_A0) 2563 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_3_BCM56440_A0fmt */ 2564 /* format IFP_DOUBLE_WIDE_F2_3fmt */ 2565 /* nFields */ 1, 2566 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_2fmt_fields, 2567 /* bits */ 128, 2568 /* flags */ 0, 2569 }, 2570 #endif /* chips */ 2571 2572 #if defined(BCM_56440_B0) 2573 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_3_BCM56440_B0fmt */ 2574 /* format IFP_DOUBLE_WIDE_F2_3fmt */ 2575 /* nFields */ 1, 2576 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_2fmt_fields, 2577 /* bits */ 128, 2578 /* flags */ 0, 2579 }, 2580 #endif /* chips */ 2581 2582 #if defined(BCM_56450_A0) 2583 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_3_BCM56450_A0fmt */ 2584 /* format IFP_DOUBLE_WIDE_F2_3fmt */ 2585 /* nFields */ 1, 2586 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_3fmt_fields, 2587 /* bits */ 128, 2588 /* flags */ 0, 2589 }, 2590 #endif /* chips */ 2591 2592 #if defined(BCM_56450_B0) 2593 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_3_BCM56450_B0fmt */ 2594 /* format IFP_DOUBLE_WIDE_F2_3fmt */ 2595 /* nFields */ 1, 2596 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_3fmt_fields, 2597 /* bits */ 128, 2598 /* flags */ 0, 2599 }, 2600 #endif /* chips */ 2601 2602 #if defined(BCM_56450_B1) 2603 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_3_BCM56450_B1fmt */ 2604 /* format IFP_DOUBLE_WIDE_F2_3fmt */ 2605 /* nFields */ 1, 2606 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_3fmt_fields, 2607 /* bits */ 128, 2608 /* flags */ 0, 2609 }, 2610 #endif /* chips */ 2611 2612 #if defined(BCM_56524_A0) 2613 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_3_BCM56524_A0fmt */ 2614 /* format IFP_DOUBLE_WIDE_F2_3fmt */ 2615 /* nFields */ 1, 2616 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_2fmt_fields, 2617 /* bits */ 128, 2618 /* flags */ 0, 2619 }, 2620 #endif /* chips */ 2621 2622 #if defined(BCM_56524_B0) 2623 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_3_BCM56524_B0fmt */ 2624 /* format IFP_DOUBLE_WIDE_F2_3fmt */ 2625 /* nFields */ 1, 2626 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_2fmt_fields, 2627 /* bits */ 128, 2628 /* flags */ 0, 2629 }, 2630 #endif /* chips */ 2631 2632 #if defined(BCM_56634_B0) 2633 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_3_BCM56634_B0fmt */ 2634 /* format IFP_DOUBLE_WIDE_F2_3fmt */ 2635 /* nFields */ 1, 2636 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_2fmt_fields, 2637 /* bits */ 128, 2638 /* flags */ 0, 2639 }, 2640 #endif /* chips */ 2641 2642 #if defined(BCM_56640_A0) 2643 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_3_BCM56640_A0fmt */ 2644 /* format IFP_DOUBLE_WIDE_F2_3fmt */ 2645 /* nFields */ 1, 2646 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_3fmt_fields, 2647 /* bits */ 128, 2648 /* flags */ 0, 2649 }, 2650 #endif /* chips */ 2651 2652 #if defined(BCM_56685_A0) 2653 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_3_BCM56685_A0fmt */ 2654 /* format IFP_DOUBLE_WIDE_F2_3fmt */ 2655 /* nFields */ 1, 2656 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_2fmt_fields, 2657 /* bits */ 128, 2658 /* flags */ 0, 2659 }, 2660 #endif /* chips */ 2661 2662 #if defined(BCM_56685_B0) 2663 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F2_3_BCM56685_B0fmt */ 2664 /* format IFP_DOUBLE_WIDE_F2_3fmt */ 2665 /* nFields */ 1, 2666 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_2fmt_fields, 2667 /* bits */ 128, 2668 /* flags */ 0, 2669 }, 2670 #endif /* chips */ 2671 2672 #if defined(BCM_53400_A0) 2673 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F3_BCM53400_A0fmt */ 2674 /* format IFP_DOUBLE_WIDE_F3fmt */ 2675 /* nFields */ 4, 2676 /* *fields */ soc_IFP_DOUBLE_WIDE_F3_BCM53400_A0fmt_fields, 2677 /* bits */ 32, 2678 /* flags */ 0, 2679 }, 2680 #endif /* chips */ 2681 2682 #if defined(BCM_53540_A0) 2683 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F3_BCM53540_A0fmt */ 2684 /* format IFP_DOUBLE_WIDE_F3fmt */ 2685 /* nFields */ 4, 2686 /* *fields */ soc_IFP_DOUBLE_WIDE_F3_BCM53400_A0fmt_fields, 2687 /* bits */ 32, 2688 /* flags */ 0, 2689 }, 2690 #endif /* chips */ 2691 2692 #if defined(BCM_53570_A0) 2693 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F3_BCM53570_A0fmt */ 2694 /* format IFP_DOUBLE_WIDE_F3fmt */ 2695 /* nFields */ 4, 2696 /* *fields */ soc_IFP_DOUBLE_WIDE_F3_BCM53400_A0fmt_fields, 2697 /* bits */ 32, 2698 /* flags */ 0, 2699 }, 2700 #endif /* chips */ 2701 2702 #if defined(BCM_53570_B0) 2703 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F3_BCM53570_B0fmt */ 2704 /* format IFP_DOUBLE_WIDE_F3fmt */ 2705 /* nFields */ 4, 2706 /* *fields */ soc_IFP_DOUBLE_WIDE_F3_BCM53400_A0fmt_fields, 2707 /* bits */ 32, 2708 /* flags */ 0, 2709 }, 2710 #endif /* chips */ 2711 2712 #if defined(BCM_56150_A0) 2713 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F3_BCM56150_A0fmt */ 2714 /* format IFP_DOUBLE_WIDE_F3fmt */ 2715 /* nFields */ 4, 2716 /* *fields */ soc_IFP_DOUBLE_WIDE_F3_BCM56450_A0fmt_fields, 2717 /* bits */ 32, 2718 /* flags */ 0, 2719 }, 2720 #endif /* chips */ 2721 2722 #if defined(BCM_56160_A0) 2723 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F3_BCM56160_A0fmt */ 2724 /* format IFP_DOUBLE_WIDE_F3fmt */ 2725 /* nFields */ 4, 2726 /* *fields */ soc_IFP_DOUBLE_WIDE_F3_BCM53400_A0fmt_fields, 2727 /* bits */ 32, 2728 /* flags */ 0, 2729 }, 2730 #endif /* chips */ 2731 2732 #if defined(BCM_56260_A0) 2733 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F3_BCM56260_A0fmt */ 2734 /* format IFP_DOUBLE_WIDE_F3fmt */ 2735 /* nFields */ 4, 2736 /* *fields */ soc_IFP_DOUBLE_WIDE_F3_BCM53400_A0fmt_fields, 2737 /* bits */ 32, 2738 /* flags */ 0, 2739 }, 2740 #endif /* chips */ 2741 2742 #if defined(BCM_56260_B0) 2743 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F3_BCM56260_B0fmt */ 2744 /* format IFP_DOUBLE_WIDE_F3fmt */ 2745 /* nFields */ 4, 2746 /* *fields */ soc_IFP_DOUBLE_WIDE_F3_BCM53400_A0fmt_fields, 2747 /* bits */ 32, 2748 /* flags */ 0, 2749 }, 2750 #endif /* chips */ 2751 2752 #if defined(BCM_56270_A0) 2753 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F3_BCM56270_A0fmt */ 2754 /* format IFP_DOUBLE_WIDE_F3fmt */ 2755 /* nFields */ 4, 2756 /* *fields */ soc_IFP_DOUBLE_WIDE_F3_BCM53400_A0fmt_fields, 2757 /* bits */ 32, 2758 /* flags */ 0, 2759 }, 2760 #endif /* chips */ 2761 2762 #if defined(BCM_56340_A0) 2763 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F3_BCM56340_A0fmt */ 2764 /* format IFP_DOUBLE_WIDE_F3fmt */ 2765 /* nFields */ 4, 2766 /* *fields */ soc_IFP_DOUBLE_WIDE_F3_BCM56640_A0fmt_fields, 2767 /* bits */ 32, 2768 /* flags */ 0, 2769 }, 2770 #endif /* chips */ 2771 2772 #if defined(BCM_56450_A0) 2773 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F3_BCM56450_A0fmt */ 2774 /* format IFP_DOUBLE_WIDE_F3fmt */ 2775 /* nFields */ 4, 2776 /* *fields */ soc_IFP_DOUBLE_WIDE_F3_BCM56450_A0fmt_fields, 2777 /* bits */ 32, 2778 /* flags */ 0, 2779 }, 2780 #endif /* chips */ 2781 2782 #if defined(BCM_56450_B0) 2783 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F3_BCM56450_B0fmt */ 2784 /* format IFP_DOUBLE_WIDE_F3fmt */ 2785 /* nFields */ 4, 2786 /* *fields */ soc_IFP_DOUBLE_WIDE_F3_BCM56450_A0fmt_fields, 2787 /* bits */ 32, 2788 /* flags */ 0, 2789 }, 2790 #endif /* chips */ 2791 2792 #if defined(BCM_56450_B1) 2793 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F3_BCM56450_B1fmt */ 2794 /* format IFP_DOUBLE_WIDE_F3fmt */ 2795 /* nFields */ 4, 2796 /* *fields */ soc_IFP_DOUBLE_WIDE_F3_BCM56450_A0fmt_fields, 2797 /* bits */ 32, 2798 /* flags */ 0, 2799 }, 2800 #endif /* chips */ 2801 2802 #if defined(BCM_56524_B0) 2803 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F3_BCM56524_B0fmt */ 2804 /* format IFP_DOUBLE_WIDE_F3fmt */ 2805 /* nFields */ 4, 2806 /* *fields */ soc_IFP_DOUBLE_WIDE_F3fmt_fields, 2807 /* bits */ 32, 2808 /* flags */ 0, 2809 }, 2810 #endif /* chips */ 2811 2812 #if defined(BCM_56640_A0) 2813 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F3_BCM56640_A0fmt */ 2814 /* format IFP_DOUBLE_WIDE_F3fmt */ 2815 /* nFields */ 4, 2816 /* *fields */ soc_IFP_DOUBLE_WIDE_F3_BCM56640_A0fmt_fields, 2817 /* bits */ 32, 2818 /* flags */ 0, 2819 }, 2820 #endif /* chips */ 2821 2822 #if defined(BCM_56680_B0) 2823 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F3_BCM56680_B0fmt */ 2824 /* format IFP_DOUBLE_WIDE_F3fmt */ 2825 /* nFields */ 4, 2826 /* *fields */ soc_IFP_DOUBLE_WIDE_F3fmt_fields, 2827 /* bits */ 32, 2828 /* flags */ 0, 2829 }, 2830 #endif /* chips */ 2831 2832 #if defined(BCM_56685_B0) 2833 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F3_BCM56685_B0fmt */ 2834 /* format IFP_DOUBLE_WIDE_F3fmt */ 2835 /* nFields */ 4, 2836 /* *fields */ soc_IFP_DOUBLE_WIDE_F3fmt_fields, 2837 /* bits */ 32, 2838 /* flags */ 0, 2839 }, 2840 #endif /* chips */ 2841 2842 #if defined(BCM_56820_A0) 2843 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F3_BCM56820_A0fmt */ 2844 /* format IFP_DOUBLE_WIDE_F3fmt */ 2845 /* nFields */ 4, 2846 /* *fields */ soc_IFP_DOUBLE_WIDE_F3fmt_fields, 2847 /* bits */ 32, 2848 /* flags */ 0, 2849 }, 2850 #endif /* chips */ 2851 2852 #if defined(BCM_88732_A0) 2853 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F3_BCM88732_A0fmt */ 2854 /* format IFP_DOUBLE_WIDE_F3fmt */ 2855 /* nFields */ 4, 2856 /* *fields */ soc_IFP_DOUBLE_WIDE_F3fmt_fields, 2857 /* bits */ 32, 2858 /* flags */ 0, 2859 }, 2860 #endif /* chips */ 2861 2862 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \ 2863 defined(BCM_56680_A0) || defined(BCM_56680_B0) || \ 2864 defined(BCM_56725_A0) || defined(BCM_56820_A0) || \ 2865 defined(BCM_88732_A0) 2866 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F4_0fmt */ 2867 /* format IFP_DOUBLE_WIDE_F4_0fmt */ 2868 /* nFields */ 1, 2869 /* *fields */ soc_IFP_DOUBLE_WIDE_F4_0fmt_fields, 2870 /* bits */ 6, 2871 /* flags */ 0, 2872 }, 2873 #endif /* chips */ 2874 2875 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \ 2876 defined(BCM_56680_A0) || defined(BCM_56680_B0) || \ 2877 defined(BCM_56725_A0) || defined(BCM_56820_A0) || \ 2878 defined(BCM_88732_A0) 2879 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F4_1fmt */ 2880 /* format IFP_DOUBLE_WIDE_F4_1fmt */ 2881 /* nFields */ 1, 2882 /* *fields */ soc_IFP_DOUBLE_WIDE_F4_1fmt_fields, 2883 /* bits */ 6, 2884 /* flags */ 0, 2885 }, 2886 #endif /* chips */ 2887 2888 #if defined(BCM_53400_A0) 2889 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F4_0_BCM53400_A0fmt */ 2890 /* format IFP_DOUBLE_WIDE_F4_0fmt */ 2891 /* nFields */ 1, 2892 /* *fields */ soc_IFP_DOUBLE_WIDE_F4_0_BCM53400_A0fmt_fields, 2893 /* bits */ 7, 2894 /* flags */ 0, 2895 }, 2896 #endif /* chips */ 2897 2898 #if defined(BCM_53540_A0) 2899 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F4_0_BCM53540_A0fmt */ 2900 /* format IFP_DOUBLE_WIDE_F4_0fmt */ 2901 /* nFields */ 1, 2902 /* *fields */ soc_IFP_DOUBLE_WIDE_F4_0_BCM53400_A0fmt_fields, 2903 /* bits */ 7, 2904 /* flags */ 0, 2905 }, 2906 #endif /* chips */ 2907 2908 #if defined(BCM_53570_A0) 2909 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F4_0_BCM53570_A0fmt */ 2910 /* format IFP_DOUBLE_WIDE_F4_0fmt */ 2911 /* nFields */ 1, 2912 /* *fields */ soc_IFP_SINGLE_WIDE_F4_BCM56560_A0fmt_fields, 2913 /* bits */ 8, 2914 /* flags */ 0, 2915 }, 2916 #endif /* chips */ 2917 2918 #if defined(BCM_53570_B0) 2919 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F4_0_BCM53570_B0fmt */ 2920 /* format IFP_DOUBLE_WIDE_F4_0fmt */ 2921 /* nFields */ 1, 2922 /* *fields */ soc_IFP_SINGLE_WIDE_F4_BCM56560_A0fmt_fields, 2923 /* bits */ 8, 2924 /* flags */ 0, 2925 }, 2926 #endif /* chips */ 2927 2928 #if defined(BCM_56142_A0) 2929 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F4_0_BCM56142_A0fmt */ 2930 /* format IFP_DOUBLE_WIDE_F4_0fmt */ 2931 /* nFields */ 1, 2932 /* *fields */ soc_IFP_DOUBLE_WIDE_F4_0_BCM56634_A0fmt_fields, 2933 /* bits */ 7, 2934 /* flags */ 0, 2935 }, 2936 #endif /* chips */ 2937 2938 #if defined(BCM_56150_A0) 2939 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F4_0_BCM56150_A0fmt */ 2940 /* format IFP_DOUBLE_WIDE_F4_0fmt */ 2941 /* nFields */ 1, 2942 /* *fields */ soc_IFP_DOUBLE_WIDE_F4_0_BCM56640_A0fmt_fields, 2943 /* bits */ 7, 2944 /* flags */ 0, 2945 }, 2946 #endif /* chips */ 2947 2948 #if defined(BCM_56160_A0) 2949 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F4_0_BCM56160_A0fmt */ 2950 /* format IFP_DOUBLE_WIDE_F4_0fmt */ 2951 /* nFields */ 1, 2952 /* *fields */ soc_IFP_DOUBLE_WIDE_F4_0_BCM53400_A0fmt_fields, 2953 /* bits */ 7, 2954 /* flags */ 0, 2955 }, 2956 #endif /* chips */ 2957 2958 #if defined(BCM_56260_A0) 2959 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F4_0_BCM56260_A0fmt */ 2960 /* format IFP_DOUBLE_WIDE_F4_0fmt */ 2961 /* nFields */ 1, 2962 /* *fields */ soc_IFP_SINGLE_WIDE_F4_BCM56560_A0fmt_fields, 2963 /* bits */ 8, 2964 /* flags */ 0, 2965 }, 2966 #endif /* chips */ 2967 2968 #if defined(BCM_56260_B0) 2969 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F4_0_BCM56260_B0fmt */ 2970 /* format IFP_DOUBLE_WIDE_F4_0fmt */ 2971 /* nFields */ 1, 2972 /* *fields */ soc_IFP_SINGLE_WIDE_F4_BCM56560_A0fmt_fields, 2973 /* bits */ 8, 2974 /* flags */ 0, 2975 }, 2976 #endif /* chips */ 2977 2978 #if defined(BCM_56270_A0) 2979 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F4_0_BCM56270_A0fmt */ 2980 /* format IFP_DOUBLE_WIDE_F4_0fmt */ 2981 /* nFields */ 1, 2982 /* *fields */ soc_IFP_SINGLE_WIDE_F4_BCM56560_A0fmt_fields, 2983 /* bits */ 8, 2984 /* flags */ 0, 2985 }, 2986 #endif /* chips */ 2987 2988 #if defined(BCM_56334_A0) 2989 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F4_0_BCM56334_A0fmt */ 2990 /* format IFP_DOUBLE_WIDE_F4_0fmt */ 2991 /* nFields */ 1, 2992 /* *fields */ soc_IFP_DOUBLE_WIDE_F4_0_BCM56634_A0fmt_fields, 2993 /* bits */ 7, 2994 /* flags */ 0, 2995 }, 2996 #endif /* chips */ 2997 2998 #if defined(BCM_56334_B0) 2999 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F4_0_BCM56334_B0fmt */ 3000 /* format IFP_DOUBLE_WIDE_F4_0fmt */ 3001 /* nFields */ 1, 3002 /* *fields */ soc_IFP_DOUBLE_WIDE_F4_0_BCM56634_A0fmt_fields, 3003 /* bits */ 7, 3004 /* flags */ 0, 3005 }, 3006 #endif /* chips */ 3007 3008 #if defined(BCM_56340_A0) 3009 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F4_0_BCM56340_A0fmt */ 3010 /* format IFP_DOUBLE_WIDE_F4_0fmt */ 3011 /* nFields */ 1, 3012 /* *fields */ soc_IFP_DOUBLE_WIDE_F4_0_BCM56640_A0fmt_fields, 3013 /* bits */ 7, 3014 /* flags */ 0, 3015 }, 3016 #endif /* chips */ 3017 3018 #if defined(BCM_56440_A0) 3019 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F4_0_BCM56440_A0fmt */ 3020 /* format IFP_DOUBLE_WIDE_F4_0fmt */ 3021 /* nFields */ 1, 3022 /* *fields */ soc_IFP_DOUBLE_WIDE_F4_0_BCM56634_A0fmt_fields, 3023 /* bits */ 7, 3024 /* flags */ 0, 3025 }, 3026 #endif /* chips */ 3027 3028 #if defined(BCM_56440_B0) 3029 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F4_0_BCM56440_B0fmt */ 3030 /* format IFP_DOUBLE_WIDE_F4_0fmt */ 3031 /* nFields */ 1, 3032 /* *fields */ soc_IFP_DOUBLE_WIDE_F4_0_BCM56634_A0fmt_fields, 3033 /* bits */ 7, 3034 /* flags */ 0, 3035 }, 3036 #endif /* chips */ 3037 3038 #if defined(BCM_56450_A0) 3039 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F4_0_BCM56450_A0fmt */ 3040 /* format IFP_DOUBLE_WIDE_F4_0fmt */ 3041 /* nFields */ 1, 3042 /* *fields */ soc_IFP_SINGLE_WIDE_F4fmt_fields, 3043 /* bits */ 8, 3044 /* flags */ 0, 3045 }, 3046 #endif /* chips */ 3047 3048 #if defined(BCM_56450_B0) 3049 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F4_0_BCM56450_B0fmt */ 3050 /* format IFP_DOUBLE_WIDE_F4_0fmt */ 3051 /* nFields */ 1, 3052 /* *fields */ soc_IFP_SINGLE_WIDE_F4fmt_fields, 3053 /* bits */ 8, 3054 /* flags */ 0, 3055 }, 3056 #endif /* chips */ 3057 3058 #if defined(BCM_56450_B1) 3059 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F4_0_BCM56450_B1fmt */ 3060 /* format IFP_DOUBLE_WIDE_F4_0fmt */ 3061 /* nFields */ 1, 3062 /* *fields */ soc_IFP_SINGLE_WIDE_F4fmt_fields, 3063 /* bits */ 8, 3064 /* flags */ 0, 3065 }, 3066 #endif /* chips */ 3067 3068 #if defined(BCM_56524_A0) 3069 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F4_0_BCM56524_A0fmt */ 3070 /* format IFP_DOUBLE_WIDE_F4_0fmt */ 3071 /* nFields */ 1, 3072 /* *fields */ soc_IFP_DOUBLE_WIDE_F4_0_BCM56634_A0fmt_fields, 3073 /* bits */ 7, 3074 /* flags */ 0, 3075 }, 3076 #endif /* chips */ 3077 3078 #if defined(BCM_56524_B0) 3079 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F4_0_BCM56524_B0fmt */ 3080 /* format IFP_DOUBLE_WIDE_F4_0fmt */ 3081 /* nFields */ 1, 3082 /* *fields */ soc_IFP_DOUBLE_WIDE_F4_0_BCM56634_A0fmt_fields, 3083 /* bits */ 7, 3084 /* flags */ 0, 3085 }, 3086 #endif /* chips */ 3087 3088 #if defined(BCM_56634_A0) 3089 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F4_0_BCM56634_A0fmt */ 3090 /* format IFP_DOUBLE_WIDE_F4_0fmt */ 3091 /* nFields */ 1, 3092 /* *fields */ soc_IFP_DOUBLE_WIDE_F4_0_BCM56634_A0fmt_fields, 3093 /* bits */ 7, 3094 /* flags */ 0, 3095 }, 3096 #endif /* chips */ 3097 3098 #if defined(BCM_56634_B0) 3099 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F4_0_BCM56634_B0fmt */ 3100 /* format IFP_DOUBLE_WIDE_F4_0fmt */ 3101 /* nFields */ 1, 3102 /* *fields */ soc_IFP_DOUBLE_WIDE_F4_0_BCM56634_A0fmt_fields, 3103 /* bits */ 7, 3104 /* flags */ 0, 3105 }, 3106 #endif /* chips */ 3107 3108 #if defined(BCM_56640_A0) 3109 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F4_0_BCM56640_A0fmt */ 3110 /* format IFP_DOUBLE_WIDE_F4_0fmt */ 3111 /* nFields */ 1, 3112 /* *fields */ soc_IFP_DOUBLE_WIDE_F4_0_BCM56640_A0fmt_fields, 3113 /* bits */ 7, 3114 /* flags */ 0, 3115 }, 3116 #endif /* chips */ 3117 3118 #if defined(BCM_56685_A0) 3119 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F4_0_BCM56685_A0fmt */ 3120 /* format IFP_DOUBLE_WIDE_F4_0fmt */ 3121 /* nFields */ 1, 3122 /* *fields */ soc_IFP_DOUBLE_WIDE_F4_0_BCM56634_A0fmt_fields, 3123 /* bits */ 7, 3124 /* flags */ 0, 3125 }, 3126 #endif /* chips */ 3127 3128 #if defined(BCM_56685_B0) 3129 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F4_0_BCM56685_B0fmt */ 3130 /* format IFP_DOUBLE_WIDE_F4_0fmt */ 3131 /* nFields */ 1, 3132 /* *fields */ soc_IFP_DOUBLE_WIDE_F4_0_BCM56634_A0fmt_fields, 3133 /* bits */ 7, 3134 /* flags */ 0, 3135 }, 3136 #endif /* chips */ 3137 3138 #if defined(BCM_53400_A0) 3139 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F4_1_BCM53400_A0fmt */ 3140 /* format IFP_DOUBLE_WIDE_F4_1fmt */ 3141 /* nFields */ 2, 3142 /* *fields */ soc_IFP_DOUBLE_WIDE_F4_1_BCM53400_A0fmt_fields, 3143 /* bits */ 7, 3144 /* flags */ 0, 3145 }, 3146 #endif /* chips */ 3147 3148 #if defined(BCM_53540_A0) 3149 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F4_1_BCM53540_A0fmt */ 3150 /* format IFP_DOUBLE_WIDE_F4_1fmt */ 3151 /* nFields */ 2, 3152 /* *fields */ soc_IFP_DOUBLE_WIDE_F4_1_BCM53400_A0fmt_fields, 3153 /* bits */ 7, 3154 /* flags */ 0, 3155 }, 3156 #endif /* chips */ 3157 3158 #if defined(BCM_53570_A0) 3159 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F4_1_BCM53570_A0fmt */ 3160 /* format IFP_DOUBLE_WIDE_F4_1fmt */ 3161 /* nFields */ 2, 3162 /* *fields */ soc_IFP_DOUBLE_WIDE_F4_1_BCM56260_A0fmt_fields, 3163 /* bits */ 8, 3164 /* flags */ 0, 3165 }, 3166 #endif /* chips */ 3167 3168 #if defined(BCM_53570_B0) 3169 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F4_1_BCM53570_B0fmt */ 3170 /* format IFP_DOUBLE_WIDE_F4_1fmt */ 3171 /* nFields */ 2, 3172 /* *fields */ soc_IFP_DOUBLE_WIDE_F4_1_BCM56260_A0fmt_fields, 3173 /* bits */ 8, 3174 /* flags */ 0, 3175 }, 3176 #endif /* chips */ 3177 3178 #if defined(BCM_56142_A0) 3179 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F4_1_BCM56142_A0fmt */ 3180 /* format IFP_DOUBLE_WIDE_F4_1fmt */ 3181 /* nFields */ 2, 3182 /* *fields */ soc_IFP_DOUBLE_WIDE_F4_1_BCM56634_A0fmt_fields, 3183 /* bits */ 7, 3184 /* flags */ 0, 3185 }, 3186 #endif /* chips */ 3187 3188 #if defined(BCM_56150_A0) 3189 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F4_1_BCM56150_A0fmt */ 3190 /* format IFP_DOUBLE_WIDE_F4_1fmt */ 3191 /* nFields */ 2, 3192 /* *fields */ soc_IFP_DOUBLE_WIDE_F4_1_BCM56640_A0fmt_fields, 3193 /* bits */ 7, 3194 /* flags */ 0, 3195 }, 3196 #endif /* chips */ 3197 3198 #if defined(BCM_56160_A0) 3199 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F4_1_BCM56160_A0fmt */ 3200 /* format IFP_DOUBLE_WIDE_F4_1fmt */ 3201 /* nFields */ 2, 3202 /* *fields */ soc_IFP_DOUBLE_WIDE_F4_1_BCM53400_A0fmt_fields, 3203 /* bits */ 7, 3204 /* flags */ 0, 3205 }, 3206 #endif /* chips */ 3207 3208 #if defined(BCM_56260_A0) 3209 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F4_1_BCM56260_A0fmt */ 3210 /* format IFP_DOUBLE_WIDE_F4_1fmt */ 3211 /* nFields */ 2, 3212 /* *fields */ soc_IFP_DOUBLE_WIDE_F4_1_BCM56260_A0fmt_fields, 3213 /* bits */ 8, 3214 /* flags */ 0, 3215 }, 3216 #endif /* chips */ 3217 3218 #if defined(BCM_56260_B0) 3219 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F4_1_BCM56260_B0fmt */ 3220 /* format IFP_DOUBLE_WIDE_F4_1fmt */ 3221 /* nFields */ 2, 3222 /* *fields */ soc_IFP_DOUBLE_WIDE_F4_1_BCM56260_A0fmt_fields, 3223 /* bits */ 8, 3224 /* flags */ 0, 3225 }, 3226 #endif /* chips */ 3227 3228 #if defined(BCM_56270_A0) 3229 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F4_1_BCM56270_A0fmt */ 3230 /* format IFP_DOUBLE_WIDE_F4_1fmt */ 3231 /* nFields */ 2, 3232 /* *fields */ soc_IFP_DOUBLE_WIDE_F4_1_BCM56260_A0fmt_fields, 3233 /* bits */ 8, 3234 /* flags */ 0, 3235 }, 3236 #endif /* chips */ 3237 3238 #if defined(BCM_56334_A0) 3239 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F4_1_BCM56334_A0fmt */ 3240 /* format IFP_DOUBLE_WIDE_F4_1fmt */ 3241 /* nFields */ 2, 3242 /* *fields */ soc_IFP_DOUBLE_WIDE_F4_1_BCM56634_A0fmt_fields, 3243 /* bits */ 7, 3244 /* flags */ 0, 3245 }, 3246 #endif /* chips */ 3247 3248 #if defined(BCM_56334_B0) 3249 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F4_1_BCM56334_B0fmt */ 3250 /* format IFP_DOUBLE_WIDE_F4_1fmt */ 3251 /* nFields */ 2, 3252 /* *fields */ soc_IFP_DOUBLE_WIDE_F4_1_BCM56634_A0fmt_fields, 3253 /* bits */ 7, 3254 /* flags */ 0, 3255 }, 3256 #endif /* chips */ 3257 3258 #if defined(BCM_56340_A0) 3259 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F4_1_BCM56340_A0fmt */ 3260 /* format IFP_DOUBLE_WIDE_F4_1fmt */ 3261 /* nFields */ 2, 3262 /* *fields */ soc_IFP_DOUBLE_WIDE_F4_1_BCM56640_A0fmt_fields, 3263 /* bits */ 7, 3264 /* flags */ 0, 3265 }, 3266 #endif /* chips */ 3267 3268 #if defined(BCM_56440_A0) 3269 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F4_1_BCM56440_A0fmt */ 3270 /* format IFP_DOUBLE_WIDE_F4_1fmt */ 3271 /* nFields */ 2, 3272 /* *fields */ soc_IFP_DOUBLE_WIDE_F4_1_BCM56634_A0fmt_fields, 3273 /* bits */ 7, 3274 /* flags */ 0, 3275 }, 3276 #endif /* chips */ 3277 3278 #if defined(BCM_56440_B0) 3279 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F4_1_BCM56440_B0fmt */ 3280 /* format IFP_DOUBLE_WIDE_F4_1fmt */ 3281 /* nFields */ 2, 3282 /* *fields */ soc_IFP_DOUBLE_WIDE_F4_1_BCM56634_A0fmt_fields, 3283 /* bits */ 7, 3284 /* flags */ 0, 3285 }, 3286 #endif /* chips */ 3287 3288 #if defined(BCM_56450_A0) 3289 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F4_1_BCM56450_A0fmt */ 3290 /* format IFP_DOUBLE_WIDE_F4_1fmt */ 3291 /* nFields */ 2, 3292 /* *fields */ soc_IFP_DOUBLE_WIDE_F4_1_BCM56450_A0fmt_fields, 3293 /* bits */ 8, 3294 /* flags */ 0, 3295 }, 3296 #endif /* chips */ 3297 3298 #if defined(BCM_56450_B0) 3299 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F4_1_BCM56450_B0fmt */ 3300 /* format IFP_DOUBLE_WIDE_F4_1fmt */ 3301 /* nFields */ 2, 3302 /* *fields */ soc_IFP_DOUBLE_WIDE_F4_1_BCM56450_A0fmt_fields, 3303 /* bits */ 8, 3304 /* flags */ 0, 3305 }, 3306 #endif /* chips */ 3307 3308 #if defined(BCM_56450_B1) 3309 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F4_1_BCM56450_B1fmt */ 3310 /* format IFP_DOUBLE_WIDE_F4_1fmt */ 3311 /* nFields */ 2, 3312 /* *fields */ soc_IFP_DOUBLE_WIDE_F4_1_BCM56450_A0fmt_fields, 3313 /* bits */ 8, 3314 /* flags */ 0, 3315 }, 3316 #endif /* chips */ 3317 3318 #if defined(BCM_56524_A0) 3319 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F4_1_BCM56524_A0fmt */ 3320 /* format IFP_DOUBLE_WIDE_F4_1fmt */ 3321 /* nFields */ 2, 3322 /* *fields */ soc_IFP_DOUBLE_WIDE_F4_1_BCM56634_A0fmt_fields, 3323 /* bits */ 7, 3324 /* flags */ 0, 3325 }, 3326 #endif /* chips */ 3327 3328 #if defined(BCM_56524_B0) 3329 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F4_1_BCM56524_B0fmt */ 3330 /* format IFP_DOUBLE_WIDE_F4_1fmt */ 3331 /* nFields */ 2, 3332 /* *fields */ soc_IFP_DOUBLE_WIDE_F4_1_BCM56634_A0fmt_fields, 3333 /* bits */ 7, 3334 /* flags */ 0, 3335 }, 3336 #endif /* chips */ 3337 3338 #if defined(BCM_56634_A0) 3339 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F4_1_BCM56634_A0fmt */ 3340 /* format IFP_DOUBLE_WIDE_F4_1fmt */ 3341 /* nFields */ 2, 3342 /* *fields */ soc_IFP_DOUBLE_WIDE_F4_1_BCM56634_A0fmt_fields, 3343 /* bits */ 7, 3344 /* flags */ 0, 3345 }, 3346 #endif /* chips */ 3347 3348 #if defined(BCM_56634_B0) 3349 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F4_1_BCM56634_B0fmt */ 3350 /* format IFP_DOUBLE_WIDE_F4_1fmt */ 3351 /* nFields */ 2, 3352 /* *fields */ soc_IFP_DOUBLE_WIDE_F4_1_BCM56634_A0fmt_fields, 3353 /* bits */ 7, 3354 /* flags */ 0, 3355 }, 3356 #endif /* chips */ 3357 3358 #if defined(BCM_56640_A0) 3359 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F4_1_BCM56640_A0fmt */ 3360 /* format IFP_DOUBLE_WIDE_F4_1fmt */ 3361 /* nFields */ 2, 3362 /* *fields */ soc_IFP_DOUBLE_WIDE_F4_1_BCM56640_A0fmt_fields, 3363 /* bits */ 7, 3364 /* flags */ 0, 3365 }, 3366 #endif /* chips */ 3367 3368 #if defined(BCM_56685_A0) 3369 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F4_1_BCM56685_A0fmt */ 3370 /* format IFP_DOUBLE_WIDE_F4_1fmt */ 3371 /* nFields */ 2, 3372 /* *fields */ soc_IFP_DOUBLE_WIDE_F4_1_BCM56634_A0fmt_fields, 3373 /* bits */ 7, 3374 /* flags */ 0, 3375 }, 3376 #endif /* chips */ 3377 3378 #if defined(BCM_56685_B0) 3379 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_F4_1_BCM56685_B0fmt */ 3380 /* format IFP_DOUBLE_WIDE_F4_1fmt */ 3381 /* nFields */ 2, 3382 /* *fields */ soc_IFP_DOUBLE_WIDE_F4_1_BCM56634_A0fmt_fields, 3383 /* bits */ 7, 3384 /* flags */ 0, 3385 }, 3386 #endif /* chips */ 3387 3388 #if defined(BCM_56524_A0) || defined(BCM_56634_A0) || \ 3389 defined(BCM_56634_B0) 3390 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_IPBM_F0fmt */ 3391 /* format IFP_DOUBLE_WIDE_IPBM_F0fmt */ 3392 /* nFields */ 5, 3393 /* *fields */ soc_IFP_DOUBLE_WIDE_IPBM_F0fmt_fields, 3394 /* bits */ 56, 3395 /* flags */ 0, 3396 }, 3397 #endif /* chips */ 3398 3399 #if defined(BCM_53400_A0) 3400 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_IPBM_F0_BCM53400_A0fmt */ 3401 /* format IFP_DOUBLE_WIDE_IPBM_F0fmt */ 3402 /* nFields */ 4, 3403 /* *fields */ soc_IFP_DOUBLE_WIDE_IPBM_F0_BCM53400_A0fmt_fields, 3404 /* bits */ 30, 3405 /* flags */ 0, 3406 }, 3407 #endif /* chips */ 3408 3409 #if defined(BCM_53540_A0) 3410 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_IPBM_F0_BCM53540_A0fmt */ 3411 /* format IFP_DOUBLE_WIDE_IPBM_F0fmt */ 3412 /* nFields */ 3, 3413 /* *fields */ soc_IFP_DOUBLE_WIDE_IPBM_F0_BCM56160_A0fmt_fields, 3414 /* bits */ 31, 3415 /* flags */ 0, 3416 }, 3417 #endif /* chips */ 3418 3419 #if defined(BCM_53570_A0) 3420 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_IPBM_F0_BCM53570_A0fmt */ 3421 /* format IFP_DOUBLE_WIDE_IPBM_F0fmt */ 3422 /* nFields */ 4, 3423 /* *fields */ soc_IFP_DOUBLE_WIDE_IPBM_F0_BCM53570_A0fmt_fields, 3424 /* bits */ 66, 3425 /* flags */ 0, 3426 }, 3427 #endif /* chips */ 3428 3429 #if defined(BCM_53570_B0) 3430 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_IPBM_F0_BCM53570_B0fmt */ 3431 /* format IFP_DOUBLE_WIDE_IPBM_F0fmt */ 3432 /* nFields */ 4, 3433 /* *fields */ soc_IFP_DOUBLE_WIDE_IPBM_F0_BCM53570_A0fmt_fields, 3434 /* bits */ 66, 3435 /* flags */ 0, 3436 }, 3437 #endif /* chips */ 3438 3439 #if defined(BCM_56142_A0) 3440 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_IPBM_F0_BCM56142_A0fmt */ 3441 /* format IFP_DOUBLE_WIDE_IPBM_F0fmt */ 3442 /* nFields */ 4, 3443 /* *fields */ soc_IFP_DOUBLE_WIDE_IPBM_F0_BCM56334_A0fmt_fields, 3444 /* bits */ 30, 3445 /* flags */ 0, 3446 }, 3447 #endif /* chips */ 3448 3449 #if defined(BCM_56150_A0) 3450 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_IPBM_F0_BCM56150_A0fmt */ 3451 /* format IFP_DOUBLE_WIDE_IPBM_F0fmt */ 3452 /* nFields */ 4, 3453 /* *fields */ soc_IFP_DOUBLE_WIDE_IPBM_F0_BCM56150_A0fmt_fields, 3454 /* bits */ 30, 3455 /* flags */ 0, 3456 }, 3457 #endif /* chips */ 3458 3459 #if defined(BCM_56160_A0) 3460 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_IPBM_F0_BCM56160_A0fmt */ 3461 /* format IFP_DOUBLE_WIDE_IPBM_F0fmt */ 3462 /* nFields */ 3, 3463 /* *fields */ soc_IFP_DOUBLE_WIDE_IPBM_F0_BCM56160_A0fmt_fields, 3464 /* bits */ 31, 3465 /* flags */ 0, 3466 }, 3467 #endif /* chips */ 3468 3469 #if defined(BCM_56260_A0) 3470 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_IPBM_F0_BCM56260_A0fmt */ 3471 /* format IFP_DOUBLE_WIDE_IPBM_F0fmt */ 3472 /* nFields */ 4, 3473 /* *fields */ soc_IFP_DOUBLE_WIDE_IPBM_F0_BCM56260_A0fmt_fields, 3474 /* bits */ 40, 3475 /* flags */ 0, 3476 }, 3477 #endif /* chips */ 3478 3479 #if defined(BCM_56260_B0) 3480 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_IPBM_F0_BCM56260_B0fmt */ 3481 /* format IFP_DOUBLE_WIDE_IPBM_F0fmt */ 3482 /* nFields */ 4, 3483 /* *fields */ soc_IFP_DOUBLE_WIDE_IPBM_F0_BCM56260_A0fmt_fields, 3484 /* bits */ 40, 3485 /* flags */ 0, 3486 }, 3487 #endif /* chips */ 3488 3489 #if defined(BCM_56270_A0) 3490 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_IPBM_F0_BCM56270_A0fmt */ 3491 /* format IFP_DOUBLE_WIDE_IPBM_F0fmt */ 3492 /* nFields */ 4, 3493 /* *fields */ soc_IFP_DOUBLE_WIDE_IPBM_F0_BCM56260_A0fmt_fields, 3494 /* bits */ 40, 3495 /* flags */ 0, 3496 }, 3497 #endif /* chips */ 3498 3499 #if defined(BCM_56334_A0) 3500 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_IPBM_F0_BCM56334_A0fmt */ 3501 /* format IFP_DOUBLE_WIDE_IPBM_F0fmt */ 3502 /* nFields */ 4, 3503 /* *fields */ soc_IFP_DOUBLE_WIDE_IPBM_F0_BCM56334_A0fmt_fields, 3504 /* bits */ 30, 3505 /* flags */ 0, 3506 }, 3507 #endif /* chips */ 3508 3509 #if defined(BCM_56334_B0) 3510 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_IPBM_F0_BCM56334_B0fmt */ 3511 /* format IFP_DOUBLE_WIDE_IPBM_F0fmt */ 3512 /* nFields */ 4, 3513 /* *fields */ soc_IFP_DOUBLE_WIDE_IPBM_F0_BCM56334_A0fmt_fields, 3514 /* bits */ 30, 3515 /* flags */ 0, 3516 }, 3517 #endif /* chips */ 3518 3519 #if defined(BCM_56440_A0) 3520 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_IPBM_F0_BCM56440_A0fmt */ 3521 /* format IFP_DOUBLE_WIDE_IPBM_F0fmt */ 3522 /* nFields */ 4, 3523 /* *fields */ soc_IFP_DOUBLE_WIDE_IPBM_F0_BCM56440_A0fmt_fields, 3524 /* bits */ 40, 3525 /* flags */ 0, 3526 }, 3527 #endif /* chips */ 3528 3529 #if defined(BCM_56440_B0) 3530 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_IPBM_F0_BCM56440_B0fmt */ 3531 /* format IFP_DOUBLE_WIDE_IPBM_F0fmt */ 3532 /* nFields */ 4, 3533 /* *fields */ soc_IFP_DOUBLE_WIDE_IPBM_F0_BCM56440_A0fmt_fields, 3534 /* bits */ 40, 3535 /* flags */ 0, 3536 }, 3537 #endif /* chips */ 3538 3539 #if defined(BCM_56450_A0) 3540 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_IPBM_F0_BCM56450_A0fmt */ 3541 /* format IFP_DOUBLE_WIDE_IPBM_F0fmt */ 3542 /* nFields */ 4, 3543 /* *fields */ soc_IFP_DOUBLE_WIDE_IPBM_F0_BCM56450_A0fmt_fields, 3544 /* bits */ 40, 3545 /* flags */ 0, 3546 }, 3547 #endif /* chips */ 3548 3549 #if defined(BCM_56450_B0) 3550 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_IPBM_F0_BCM56450_B0fmt */ 3551 /* format IFP_DOUBLE_WIDE_IPBM_F0fmt */ 3552 /* nFields */ 4, 3553 /* *fields */ soc_IFP_DOUBLE_WIDE_IPBM_F0_BCM56450_A0fmt_fields, 3554 /* bits */ 40, 3555 /* flags */ 0, 3556 }, 3557 #endif /* chips */ 3558 3559 #if defined(BCM_56450_B1) 3560 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_IPBM_F0_BCM56450_B1fmt */ 3561 /* format IFP_DOUBLE_WIDE_IPBM_F0fmt */ 3562 /* nFields */ 4, 3563 /* *fields */ soc_IFP_DOUBLE_WIDE_IPBM_F0_BCM56450_A0fmt_fields, 3564 /* bits */ 40, 3565 /* flags */ 0, 3566 }, 3567 #endif /* chips */ 3568 3569 #if defined(BCM_56524_B0) 3570 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_IPBM_F0_BCM56524_B0fmt */ 3571 /* format IFP_DOUBLE_WIDE_IPBM_F0fmt */ 3572 /* nFields */ 5, 3573 /* *fields */ soc_IFP_DOUBLE_WIDE_IPBM_F0fmt_fields, 3574 /* bits */ 56, 3575 /* flags */ 0, 3576 }, 3577 #endif /* chips */ 3578 3579 #if defined(BCM_56685_A0) 3580 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_IPBM_F0_BCM56685_A0fmt */ 3581 /* format IFP_DOUBLE_WIDE_IPBM_F0fmt */ 3582 /* nFields */ 5, 3583 /* *fields */ soc_IFP_DOUBLE_WIDE_IPBM_F0fmt_fields, 3584 /* bits */ 56, 3585 /* flags */ 0, 3586 }, 3587 #endif /* chips */ 3588 3589 #if defined(BCM_56685_B0) 3590 { /* SOC_FORMAT_INT_IFP_DOUBLE_WIDE_IPBM_F0_BCM56685_B0fmt */ 3591 /* format IFP_DOUBLE_WIDE_IPBM_F0fmt */ 3592 /* nFields */ 5, 3593 /* *fields */ soc_IFP_DOUBLE_WIDE_IPBM_F0fmt_fields, 3594 /* bits */ 56, 3595 /* flags */ 0, 3596 }, 3597 #endif /* chips */ 3598 3599 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 3600 defined(BCM_56870_A0) || defined(BCM_56960_A0) || \ 3601 defined(BCM_56965_A0) || defined(BCM_56970_A0) 3602 { /* SOC_FORMAT_INT_IFP_DROP_SETfmt */ 3603 /* format IFP_DROP_SETfmt */ 3604 /* nFields */ 3, 3605 /* *fields */ soc_IFP_DROP_SETfmt_fields, 3606 /* bits */ 6, 3607 /* flags */ 0, 3608 }, 3609 #endif /* chips */ 3610 3611 #if defined(BCM_56980_A0) 3612 { /* SOC_FORMAT_INT_IFP_DROP_SET_BCM56980_A0fmt */ 3613 /* format IFP_DROP_SETfmt */ 3614 /* nFields */ 3, 3615 /* *fields */ soc_IFP_DROP_SET_BCM56980_A0fmt_fields, 3616 /* bits */ 6, 3617 /* flags */ 0, 3618 }, 3619 #endif /* chips */ 3620 3621 #if defined(BCM_56980_B0) 3622 { /* SOC_FORMAT_INT_IFP_DROP_SET_BCM56980_B0fmt */ 3623 /* format IFP_DROP_SETfmt */ 3624 /* nFields */ 3, 3625 /* *fields */ soc_IFP_DROP_SET_BCM56980_A0fmt_fields, 3626 /* bits */ 6, 3627 /* flags */ 0, 3628 }, 3629 #endif /* chips */ 3630 3631 #if defined(BCM_56850_A0) 3632 { /* SOC_FORMAT_INT_IFP_DUAL_COUNTER_TABLE_COV_DEFSfmt */ 3633 /* format IFP_DUAL_COUNTER_TABLE_COV_DEFSfmt */ 3634 /* nFields */ 6, 3635 /* *fields */ soc_IFP_COUNTER_TABLE_COV_DEFSfmt_fields, 3636 /* bits */ 17, 3637 /* flags */ 0, 3638 }, 3639 #endif /* chips */ 3640 3641 #if defined(BCM_56560_A0) 3642 { /* SOC_FORMAT_INT_IFP_DUAL_COUNTER_TABLE_COV_DEFS_BCM56560_A0fmt */ 3643 /* format IFP_DUAL_COUNTER_TABLE_COV_DEFSfmt */ 3644 /* nFields */ 7, 3645 /* *fields */ soc_IFP_DUAL_COUNTER_TABLE_COV_DEFS_BCM56560_A0fmt_fields, 3646 /* bits */ 20, 3647 /* flags */ 0, 3648 }, 3649 #endif /* chips */ 3650 3651 #if defined(BCM_56560_B0) 3652 { /* SOC_FORMAT_INT_IFP_DUAL_COUNTER_TABLE_COV_DEFS_BCM56560_B0fmt */ 3653 /* format IFP_DUAL_COUNTER_TABLE_COV_DEFSfmt */ 3654 /* nFields */ 7, 3655 /* *fields */ soc_IFP_DUAL_COUNTER_TABLE_COV_DEFS_BCM56560_A0fmt_fields, 3656 /* bits */ 20, 3657 /* flags */ 0, 3658 }, 3659 #endif /* chips */ 3660 3661 #if defined(BCM_56670_A0) 3662 { /* SOC_FORMAT_INT_IFP_DUAL_COUNTER_TABLE_COV_DEFS_BCM56670_A0fmt */ 3663 /* format IFP_DUAL_COUNTER_TABLE_COV_DEFSfmt */ 3664 /* nFields */ 7, 3665 /* *fields */ soc_IFP_DUAL_COUNTER_TABLE_COV_DEFS_BCM56560_A0fmt_fields, 3666 /* bits */ 20, 3667 /* flags */ 0, 3668 }, 3669 #endif /* chips */ 3670 3671 #if defined(BCM_56670_B0) 3672 { /* SOC_FORMAT_INT_IFP_DUAL_COUNTER_TABLE_COV_DEFS_BCM56670_B0fmt */ 3673 /* format IFP_DUAL_COUNTER_TABLE_COV_DEFSfmt */ 3674 /* nFields */ 7, 3675 /* *fields */ soc_IFP_DUAL_COUNTER_TABLE_COV_DEFS_BCM56560_A0fmt_fields, 3676 /* bits */ 20, 3677 /* flags */ 0, 3678 }, 3679 #endif /* chips */ 3680 3681 #if defined(BCM_56860_A0) 3682 { /* SOC_FORMAT_INT_IFP_DUAL_COUNTER_TABLE_COV_DEFS_BCM56860_A0fmt */ 3683 /* format IFP_DUAL_COUNTER_TABLE_COV_DEFSfmt */ 3684 /* nFields */ 7, 3685 /* *fields */ soc_IFP_DUAL_COUNTER_TABLE_COV_DEFS_BCM56860_A0fmt_fields, 3686 /* bits */ 20, 3687 /* flags */ 0, 3688 }, 3689 #endif /* chips */ 3690 3691 #if defined(BCM_56960_A0) 3692 { /* SOC_FORMAT_INT_IFP_DUAL_COUNTER_TABLE_COV_DEFS_BCM56960_A0fmt */ 3693 /* format IFP_DUAL_COUNTER_TABLE_COV_DEFSfmt */ 3694 /* nFields */ 6, 3695 /* *fields */ soc_IFP_DUAL_COUNTER_TABLE_COV_DEFSfmt_fields, 3696 /* bits */ 17, 3697 /* flags */ 0, 3698 }, 3699 #endif /* chips */ 3700 3701 #if defined(BCM_56965_A0) 3702 { /* SOC_FORMAT_INT_IFP_DUAL_COUNTER_TABLE_COV_DEFS_BCM56965_A0fmt */ 3703 /* format IFP_DUAL_COUNTER_TABLE_COV_DEFSfmt */ 3704 /* nFields */ 6, 3705 /* *fields */ soc_IFP_DUAL_COUNTER_TABLE_COV_DEFSfmt_fields, 3706 /* bits */ 17, 3707 /* flags */ 0, 3708 }, 3709 #endif /* chips */ 3710 3711 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 3712 defined(BCM_56870_A0) 3713 { /* SOC_FORMAT_INT_IFP_EDIT_CTRL_ID_ACTION_SETfmt */ 3714 /* format IFP_EDIT_CTRL_ID_ACTION_SETfmt */ 3715 /* nFields */ 2, 3716 /* *fields */ soc_IFP_EDIT_CTRL_ID_ACTION_SETfmt_fields, 3717 /* bits */ 16, 3718 /* flags */ 0, 3719 }, 3720 #endif /* chips */ 3721 3722 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 3723 { /* SOC_FORMAT_INT_IFP_ELEPHANT_TRAP_SETfmt */ 3724 /* format IFP_ELEPHANT_TRAP_SETfmt */ 3725 /* nFields */ 6, 3726 /* *fields */ soc_IFP_ELEPHANT_TRAP_SETfmt_fields, 3727 /* bits */ 6, 3728 /* flags */ 0, 3729 }, 3730 #endif /* chips */ 3731 3732 #if defined(BCM_56340_A0) || defined(BCM_56640_A0) 3733 { /* SOC_FORMAT_INT_IFP_EVEN_METER_COV_DEFSfmt */ 3734 /* format IFP_EVEN_METER_COV_DEFSfmt */ 3735 /* nFields */ 7, 3736 /* *fields */ soc_IFP_EVEN_METER_COV_DEFSfmt_fields, 3737 /* bits */ 27, 3738 /* flags */ 0, 3739 }, 3740 #endif /* chips */ 3741 3742 #if defined(BCM_53400_A0) 3743 { /* SOC_FORMAT_INT_IFP_EVEN_METER_COV_DEFS_BCM53400_A0fmt */ 3744 /* format IFP_EVEN_METER_COV_DEFSfmt */ 3745 /* nFields */ 7, 3746 /* *fields */ soc_IFP_EVEN_METER_COV_DEFS_BCM53400_A0fmt_fields, 3747 /* bits */ 14, 3748 /* flags */ 0, 3749 }, 3750 #endif /* chips */ 3751 3752 #if defined(BCM_53540_A0) 3753 { /* SOC_FORMAT_INT_IFP_EVEN_METER_COV_DEFS_BCM53540_A0fmt */ 3754 /* format IFP_EVEN_METER_COV_DEFSfmt */ 3755 /* nFields */ 7, 3756 /* *fields */ soc_IFP_EVEN_METER_COV_DEFS_BCM53400_A0fmt_fields, 3757 /* bits */ 14, 3758 /* flags */ 0, 3759 }, 3760 #endif /* chips */ 3761 3762 #if defined(BCM_53570_A0) 3763 { /* SOC_FORMAT_INT_IFP_EVEN_METER_COV_DEFS_BCM53570_A0fmt */ 3764 /* format IFP_EVEN_METER_COV_DEFSfmt */ 3765 /* nFields */ 7, 3766 /* *fields */ soc_IFP_EVEN_METER_COV_DEFS_BCM53400_A0fmt_fields, 3767 /* bits */ 14, 3768 /* flags */ 0, 3769 }, 3770 #endif /* chips */ 3771 3772 #if defined(BCM_53570_B0) 3773 { /* SOC_FORMAT_INT_IFP_EVEN_METER_COV_DEFS_BCM53570_B0fmt */ 3774 /* format IFP_EVEN_METER_COV_DEFSfmt */ 3775 /* nFields */ 7, 3776 /* *fields */ soc_IFP_EVEN_METER_COV_DEFS_BCM53400_A0fmt_fields, 3777 /* bits */ 14, 3778 /* flags */ 0, 3779 }, 3780 #endif /* chips */ 3781 3782 #if defined(BCM_56150_A0) 3783 { /* SOC_FORMAT_INT_IFP_EVEN_METER_COV_DEFS_BCM56150_A0fmt */ 3784 /* format IFP_EVEN_METER_COV_DEFSfmt */ 3785 /* nFields */ 7, 3786 /* *fields */ soc_EFP_EVEN_METER_COV_DEFS_BCM56850_A0fmt_fields, 3787 /* bits */ 14, 3788 /* flags */ 0, 3789 }, 3790 #endif /* chips */ 3791 3792 #if defined(BCM_56160_A0) 3793 { /* SOC_FORMAT_INT_IFP_EVEN_METER_COV_DEFS_BCM56160_A0fmt */ 3794 /* format IFP_EVEN_METER_COV_DEFSfmt */ 3795 /* nFields */ 7, 3796 /* *fields */ soc_IFP_EVEN_METER_COV_DEFS_BCM53400_A0fmt_fields, 3797 /* bits */ 14, 3798 /* flags */ 0, 3799 }, 3800 #endif /* chips */ 3801 3802 #if defined(BCM_56370_A0) 3803 { /* SOC_FORMAT_INT_IFP_EVEN_METER_COV_DEFS_BCM56370_A0fmt */ 3804 /* format IFP_EVEN_METER_COV_DEFSfmt */ 3805 /* nFields */ 7, 3806 /* *fields */ soc_IFP_EVEN_METER_COV_DEFS_BCM56970_A0fmt_fields, 3807 /* bits */ 17, 3808 /* flags */ 0, 3809 }, 3810 #endif /* chips */ 3811 3812 #if defined(BCM_56560_A0) 3813 { /* SOC_FORMAT_INT_IFP_EVEN_METER_COV_DEFS_BCM56560_A0fmt */ 3814 /* format IFP_EVEN_METER_COV_DEFSfmt */ 3815 /* nFields */ 10, 3816 /* *fields */ soc_IFP_EVEN_METER_COV_DEFS_BCM56560_A0fmt_fields, 3817 /* bits */ 27, 3818 /* flags */ 0, 3819 }, 3820 #endif /* chips */ 3821 3822 #if defined(BCM_56560_B0) 3823 { /* SOC_FORMAT_INT_IFP_EVEN_METER_COV_DEFS_BCM56560_B0fmt */ 3824 /* format IFP_EVEN_METER_COV_DEFSfmt */ 3825 /* nFields */ 10, 3826 /* *fields */ soc_IFP_EVEN_METER_COV_DEFS_BCM56560_A0fmt_fields, 3827 /* bits */ 27, 3828 /* flags */ 0, 3829 }, 3830 #endif /* chips */ 3831 3832 #if defined(BCM_56670_A0) 3833 { /* SOC_FORMAT_INT_IFP_EVEN_METER_COV_DEFS_BCM56670_A0fmt */ 3834 /* format IFP_EVEN_METER_COV_DEFSfmt */ 3835 /* nFields */ 10, 3836 /* *fields */ soc_IFP_EVEN_METER_COV_DEFS_BCM56560_A0fmt_fields, 3837 /* bits */ 27, 3838 /* flags */ 0, 3839 }, 3840 #endif /* chips */ 3841 3842 #if defined(BCM_56670_B0) 3843 { /* SOC_FORMAT_INT_IFP_EVEN_METER_COV_DEFS_BCM56670_B0fmt */ 3844 /* format IFP_EVEN_METER_COV_DEFSfmt */ 3845 /* nFields */ 10, 3846 /* *fields */ soc_IFP_EVEN_METER_COV_DEFS_BCM56560_A0fmt_fields, 3847 /* bits */ 27, 3848 /* flags */ 0, 3849 }, 3850 #endif /* chips */ 3851 3852 #if defined(BCM_56770_A0) 3853 { /* SOC_FORMAT_INT_IFP_EVEN_METER_COV_DEFS_BCM56770_A0fmt */ 3854 /* format IFP_EVEN_METER_COV_DEFSfmt */ 3855 /* nFields */ 7, 3856 /* *fields */ soc_IFP_EVEN_METER_COV_DEFS_BCM56970_A0fmt_fields, 3857 /* bits */ 17, 3858 /* flags */ 0, 3859 }, 3860 #endif /* chips */ 3861 3862 #if defined(BCM_56850_A0) 3863 { /* SOC_FORMAT_INT_IFP_EVEN_METER_COV_DEFS_BCM56850_A0fmt */ 3864 /* format IFP_EVEN_METER_COV_DEFSfmt */ 3865 /* nFields */ 9, 3866 /* *fields */ soc_IFP_EVEN_METER_COV_DEFS_BCM56850_A0fmt_fields, 3867 /* bits */ 26, 3868 /* flags */ 0, 3869 }, 3870 #endif /* chips */ 3871 3872 #if defined(BCM_56860_A0) 3873 { /* SOC_FORMAT_INT_IFP_EVEN_METER_COV_DEFS_BCM56860_A0fmt */ 3874 /* format IFP_EVEN_METER_COV_DEFSfmt */ 3875 /* nFields */ 10, 3876 /* *fields */ soc_IFP_EVEN_METER_COV_DEFS_BCM56860_A0fmt_fields, 3877 /* bits */ 27, 3878 /* flags */ 0, 3879 }, 3880 #endif /* chips */ 3881 3882 #if defined(BCM_56870_A0) 3883 { /* SOC_FORMAT_INT_IFP_EVEN_METER_COV_DEFS_BCM56870_A0fmt */ 3884 /* format IFP_EVEN_METER_COV_DEFSfmt */ 3885 /* nFields */ 7, 3886 /* *fields */ soc_IFP_EVEN_METER_COV_DEFS_BCM56970_A0fmt_fields, 3887 /* bits */ 17, 3888 /* flags */ 0, 3889 }, 3890 #endif /* chips */ 3891 3892 #if defined(BCM_56960_A0) 3893 { /* SOC_FORMAT_INT_IFP_EVEN_METER_COV_DEFS_BCM56960_A0fmt */ 3894 /* format IFP_EVEN_METER_COV_DEFSfmt */ 3895 /* nFields */ 9, 3896 /* *fields */ soc_IFP_EVEN_METER_COV_DEFS_BCM56960_A0fmt_fields, 3897 /* bits */ 26, 3898 /* flags */ 0, 3899 }, 3900 #endif /* chips */ 3901 3902 #if defined(BCM_56965_A0) 3903 { /* SOC_FORMAT_INT_IFP_EVEN_METER_COV_DEFS_BCM56965_A0fmt */ 3904 /* format IFP_EVEN_METER_COV_DEFSfmt */ 3905 /* nFields */ 9, 3906 /* *fields */ soc_IFP_EVEN_METER_COV_DEFS_BCM56960_A0fmt_fields, 3907 /* bits */ 26, 3908 /* flags */ 0, 3909 }, 3910 #endif /* chips */ 3911 3912 #if defined(BCM_56970_A0) 3913 { /* SOC_FORMAT_INT_IFP_EVEN_METER_COV_DEFS_BCM56970_A0fmt */ 3914 /* format IFP_EVEN_METER_COV_DEFSfmt */ 3915 /* nFields */ 7, 3916 /* *fields */ soc_IFP_EVEN_METER_COV_DEFS_BCM56970_A0fmt_fields, 3917 /* bits */ 17, 3918 /* flags */ 0, 3919 }, 3920 #endif /* chips */ 3921 3922 #if defined(BCM_56980_A0) 3923 { /* SOC_FORMAT_INT_IFP_EVEN_METER_COV_DEFS_BCM56980_A0fmt */ 3924 /* format IFP_EVEN_METER_COV_DEFSfmt */ 3925 /* nFields */ 7, 3926 /* *fields */ soc_IFP_EVEN_METER_COV_DEFS_BCM56970_A0fmt_fields, 3927 /* bits */ 17, 3928 /* flags */ 0, 3929 }, 3930 #endif /* chips */ 3931 3932 #if defined(BCM_56980_B0) 3933 { /* SOC_FORMAT_INT_IFP_EVEN_METER_COV_DEFS_BCM56980_B0fmt */ 3934 /* format IFP_EVEN_METER_COV_DEFSfmt */ 3935 /* nFields */ 7, 3936 /* *fields */ soc_IFP_EVEN_METER_COV_DEFS_BCM56970_A0fmt_fields, 3937 /* bits */ 17, 3938 /* flags */ 0, 3939 }, 3940 #endif /* chips */ 3941 3942 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 3943 defined(BCM_56870_A0) 3944 { /* SOC_FORMAT_INT_IFP_FCOE_VSAN_SETfmt */ 3945 /* format IFP_FCOE_VSAN_SETfmt */ 3946 /* nFields */ 3, 3947 /* *fields */ soc_IFP_FCOE_VSAN_SETfmt_fields, 3948 /* bits */ 16, 3949 /* flags */ 0, 3950 }, 3951 #endif /* chips */ 3952 3953 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 3954 defined(BCM_56870_A0) || defined(BCM_56960_A0) || \ 3955 defined(BCM_56965_A0) || defined(BCM_56970_A0) || \ 3956 defined(BCM_56980_A0) || defined(BCM_56980_B0) 3957 { /* SOC_FORMAT_INT_IFP_GREEN_TO_PID_SETfmt */ 3958 /* format IFP_GREEN_TO_PID_SETfmt */ 3959 /* nFields */ 1, 3960 /* *fields */ soc_IFP_GREEN_TO_PID_SETfmt_fields, 3961 /* bits */ 1, 3962 /* flags */ 0, 3963 }, 3964 #endif /* chips */ 3965 3966 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 3967 defined(BCM_56870_A0) 3968 { /* SOC_FORMAT_INT_IFP_IGNORE_FCOE_ZONE_CHECK_SETfmt */ 3969 /* format IFP_IGNORE_FCOE_ZONE_CHECK_SETfmt */ 3970 /* nFields */ 1, 3971 /* *fields */ soc_IFP_IGNORE_FCOE_ZONE_CHECK_SETfmt_fields, 3972 /* bits */ 1, 3973 /* flags */ 0, 3974 }, 3975 #endif /* chips */ 3976 3977 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 3978 { /* SOC_FORMAT_INT_IFP_INBAND_TELEMETRY_SETfmt */ 3979 /* format IFP_INBAND_TELEMETRY_SETfmt */ 3980 /* nFields */ 2, 3981 /* *fields */ soc_IFP_INBAND_TELEMETRY_SETfmt_fields, 3982 /* bits */ 2, 3983 /* flags */ 0, 3984 }, 3985 #endif /* chips */ 3986 3987 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 3988 defined(BCM_56870_A0) || defined(BCM_56970_A0) || \ 3989 defined(BCM_56980_A0) || defined(BCM_56980_B0) 3990 { /* SOC_FORMAT_INT_IFP_INSTRUMENTATION_SETfmt */ 3991 /* format IFP_INSTRUMENTATION_SETfmt */ 3992 /* nFields */ 1, 3993 /* *fields */ soc_IFP_INSTRUMENTATION_SETfmt_fields, 3994 /* bits */ 1, 3995 /* flags */ 0, 3996 }, 3997 #endif /* chips */ 3998 3999 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 4000 defined(BCM_56870_A0) || defined(BCM_56960_A0) || \ 4001 defined(BCM_56965_A0) || defined(BCM_56970_A0) || \ 4002 defined(BCM_56980_A0) || defined(BCM_56980_B0) 4003 { /* SOC_FORMAT_INT_IFP_KEY_320Bfmt */ 4004 /* format IFP_KEY_320Bfmt */ 4005 /* nFields */ 1, 4006 /* *fields */ soc_IFP_KEY_320Bfmt_fields, 4007 /* bits */ 320, 4008 /* flags */ 0, 4009 }, 4010 #endif /* chips */ 4011 4012 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 4013 defined(BCM_56870_A0) || defined(BCM_56960_A0) || \ 4014 defined(BCM_56965_A0) || defined(BCM_56970_A0) || \ 4015 defined(BCM_56980_A0) || defined(BCM_56980_B0) 4016 { /* SOC_FORMAT_INT_IFP_KEY_480Bfmt */ 4017 /* format IFP_KEY_480Bfmt */ 4018 /* nFields */ 1, 4019 /* *fields */ soc_IFP_KEY_480Bfmt_fields, 4020 /* bits */ 480, 4021 /* flags */ 0, 4022 }, 4023 #endif /* chips */ 4024 4025 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 4026 defined(BCM_56870_A0) || defined(BCM_56960_A0) || \ 4027 defined(BCM_56965_A0) || defined(BCM_56970_A0) 4028 { /* SOC_FORMAT_INT_IFP_KEY_POST_MUXfmt */ 4029 /* format IFP_KEY_POST_MUXfmt */ 4030 /* nFields */ 19, 4031 /* *fields */ soc_IFP_KEY_POST_MUXfmt_fields, 4032 /* bits */ 160, 4033 /* flags */ 0, 4034 }, 4035 #endif /* chips */ 4036 4037 #if defined(BCM_56980_A0) 4038 { /* SOC_FORMAT_INT_IFP_KEY_POST_MUX_BCM56980_A0fmt */ 4039 /* format IFP_KEY_POST_MUXfmt */ 4040 /* nFields */ 20, 4041 /* *fields */ soc_IFP_KEY_POST_MUX_BCM56980_A0fmt_fields, 4042 /* bits */ 160, 4043 /* flags */ 0, 4044 }, 4045 #endif /* chips */ 4046 4047 #if defined(BCM_56980_B0) 4048 { /* SOC_FORMAT_INT_IFP_KEY_POST_MUX_BCM56980_B0fmt */ 4049 /* format IFP_KEY_POST_MUXfmt */ 4050 /* nFields */ 20, 4051 /* *fields */ soc_IFP_KEY_POST_MUX_BCM56980_A0fmt_fields, 4052 /* bits */ 160, 4053 /* flags */ 0, 4054 }, 4055 #endif /* chips */ 4056 4057 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 4058 defined(BCM_56870_A0) 4059 { /* SOC_FORMAT_INT_IFP_KEY_SEL_LOGICAL_TABLE_ID_AND_CLASS_IDfmt */ 4060 /* format IFP_KEY_SEL_LOGICAL_TABLE_ID_AND_CLASS_IDfmt */ 4061 /* nFields */ 3, 4062 /* *fields */ soc_IFP_KEY_SEL_LOGICAL_TABLE_ID_AND_CLASS_IDfmt_fields, 4063 /* bits */ 8, 4064 /* flags */ 0, 4065 }, 4066 #endif /* chips */ 4067 4068 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) || \ 4069 defined(BCM_56970_A0) 4070 { /* SOC_FORMAT_INT_IFP_L0_BUSfmt */ 4071 /* format IFP_L0_BUSfmt */ 4072 /* nFields */ 5, 4073 /* *fields */ soc_IFP_L0_BUSfmt_fields, 4074 /* bits */ 1460, 4075 /* flags */ 0, 4076 }, 4077 #endif /* chips */ 4078 4079 #if defined(BCM_56370_A0) 4080 { /* SOC_FORMAT_INT_IFP_L0_BUS_BCM56370_A0fmt */ 4081 /* format IFP_L0_BUSfmt */ 4082 /* nFields */ 5, 4083 /* *fields */ soc_IFP_L0_BUS_BCM56370_A0fmt_fields, 4084 /* bits */ 1904, 4085 /* flags */ 0, 4086 }, 4087 #endif /* chips */ 4088 4089 #if defined(BCM_56770_A0) 4090 { /* SOC_FORMAT_INT_IFP_L0_BUS_BCM56770_A0fmt */ 4091 /* format IFP_L0_BUSfmt */ 4092 /* nFields */ 5, 4093 /* *fields */ soc_IFP_L0_BUS_BCM56770_A0fmt_fields, 4094 /* bits */ 1838, 4095 /* flags */ 0, 4096 }, 4097 #endif /* chips */ 4098 4099 #if defined(BCM_56870_A0) 4100 { /* SOC_FORMAT_INT_IFP_L0_BUS_BCM56870_A0fmt */ 4101 /* format IFP_L0_BUSfmt */ 4102 /* nFields */ 5, 4103 /* *fields */ soc_IFP_L0_BUS_BCM56870_A0fmt_fields, 4104 /* bits */ 1822, 4105 /* flags */ 0, 4106 }, 4107 #endif /* chips */ 4108 4109 #if defined(BCM_56980_A0) 4110 { /* SOC_FORMAT_INT_IFP_L0_BUS_BCM56980_A0fmt */ 4111 /* format IFP_L0_BUSfmt */ 4112 /* nFields */ 4, 4113 /* *fields */ soc_IFP_L0_BUS_BCM56980_A0fmt_fields, 4114 /* bits */ 1052, 4115 /* flags */ 0, 4116 }, 4117 #endif /* chips */ 4118 4119 #if defined(BCM_56980_B0) 4120 { /* SOC_FORMAT_INT_IFP_L0_BUS_BCM56980_B0fmt */ 4121 /* format IFP_L0_BUSfmt */ 4122 /* nFields */ 4, 4123 /* *fields */ soc_IFP_L0_BUS_BCM56980_A0fmt_fields, 4124 /* bits */ 1052, 4125 /* flags */ 0, 4126 }, 4127 #endif /* chips */ 4128 4129 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) || \ 4130 defined(BCM_56970_A0) 4131 { /* SOC_FORMAT_INT_IFP_L0_BUS_SECTION_16BITfmt */ 4132 /* format IFP_L0_BUS_SECTION_16BITfmt */ 4133 /* nFields */ 32, 4134 /* *fields */ soc_IFP_L0_BUS_SECTION_16BITfmt_fields, 4135 /* bits */ 512, 4136 /* flags */ 0, 4137 }, 4138 #endif /* chips */ 4139 4140 #if defined(BCM_56370_A0) 4141 { /* SOC_FORMAT_INT_IFP_L0_BUS_SECTION_16BIT_BCM56370_A0fmt */ 4142 /* format IFP_L0_BUS_SECTION_16BITfmt */ 4143 /* nFields */ 54, 4144 /* *fields */ soc_IFP_L0_BUS_SECTION_16BIT_BCM56370_A0fmt_fields, 4145 /* bits */ 864, 4146 /* flags */ 0, 4147 }, 4148 #endif /* chips */ 4149 4150 #if defined(BCM_56770_A0) 4151 { /* SOC_FORMAT_INT_IFP_L0_BUS_SECTION_16BIT_BCM56770_A0fmt */ 4152 /* format IFP_L0_BUS_SECTION_16BITfmt */ 4153 /* nFields */ 50, 4154 /* *fields */ soc_IFP_L0_BUS_SECTION_16BIT_BCM56870_A0fmt_fields, 4155 /* bits */ 800, 4156 /* flags */ 0, 4157 }, 4158 #endif /* chips */ 4159 4160 #if defined(BCM_56870_A0) 4161 { /* SOC_FORMAT_INT_IFP_L0_BUS_SECTION_16BIT_BCM56870_A0fmt */ 4162 /* format IFP_L0_BUS_SECTION_16BITfmt */ 4163 /* nFields */ 50, 4164 /* *fields */ soc_IFP_L0_BUS_SECTION_16BIT_BCM56870_A0fmt_fields, 4165 /* bits */ 800, 4166 /* flags */ 0, 4167 }, 4168 #endif /* chips */ 4169 4170 #if defined(BCM_56980_A0) 4171 { /* SOC_FORMAT_INT_IFP_L0_BUS_SECTION_16BIT_BCM56980_A0fmt */ 4172 /* format IFP_L0_BUS_SECTION_16BITfmt */ 4173 /* nFields */ 27, 4174 /* *fields */ soc_IFP_L0_BUS_SECTION_16BIT_BCM56980_A0fmt_fields, 4175 /* bits */ 416, 4176 /* flags */ 0, 4177 }, 4178 #endif /* chips */ 4179 4180 #if defined(BCM_56980_B0) 4181 { /* SOC_FORMAT_INT_IFP_L0_BUS_SECTION_16BIT_BCM56980_B0fmt */ 4182 /* format IFP_L0_BUS_SECTION_16BITfmt */ 4183 /* nFields */ 27, 4184 /* *fields */ soc_IFP_L0_BUS_SECTION_16BIT_BCM56980_A0fmt_fields, 4185 /* bits */ 416, 4186 /* flags */ 0, 4187 }, 4188 #endif /* chips */ 4189 4190 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) 4191 { /* SOC_FORMAT_INT_IFP_L0_BUS_SECTION_2BITfmt */ 4192 /* format IFP_L0_BUS_SECTION_2BITfmt */ 4193 /* nFields */ 30, 4194 /* *fields */ soc_IFP_L0_BUS_SECTION_2BITfmt_fields, 4195 /* bits */ 60, 4196 /* flags */ 0, 4197 }, 4198 #endif /* chips */ 4199 4200 #if defined(BCM_56370_A0) 4201 { /* SOC_FORMAT_INT_IFP_L0_BUS_SECTION_2BIT_BCM56370_A0fmt */ 4202 /* format IFP_L0_BUS_SECTION_2BITfmt */ 4203 /* nFields */ 28, 4204 /* *fields */ soc_IFP_L0_BUS_SECTION_2BIT_BCM56370_A0fmt_fields, 4205 /* bits */ 56, 4206 /* flags */ 0, 4207 }, 4208 #endif /* chips */ 4209 4210 #if defined(BCM_56770_A0) 4211 { /* SOC_FORMAT_INT_IFP_L0_BUS_SECTION_2BIT_BCM56770_A0fmt */ 4212 /* format IFP_L0_BUS_SECTION_2BITfmt */ 4213 /* nFields */ 27, 4214 /* *fields */ soc_IFP_L0_BUS_SECTION_2BIT_BCM56870_A0fmt_fields, 4215 /* bits */ 54, 4216 /* flags */ 0, 4217 }, 4218 #endif /* chips */ 4219 4220 #if defined(BCM_56870_A0) 4221 { /* SOC_FORMAT_INT_IFP_L0_BUS_SECTION_2BIT_BCM56870_A0fmt */ 4222 /* format IFP_L0_BUS_SECTION_2BITfmt */ 4223 /* nFields */ 27, 4224 /* *fields */ soc_IFP_L0_BUS_SECTION_2BIT_BCM56870_A0fmt_fields, 4225 /* bits */ 54, 4226 /* flags */ 0, 4227 }, 4228 #endif /* chips */ 4229 4230 #if defined(BCM_56970_A0) 4231 { /* SOC_FORMAT_INT_IFP_L0_BUS_SECTION_2BIT_BCM56970_A0fmt */ 4232 /* format IFP_L0_BUS_SECTION_2BITfmt */ 4233 /* nFields */ 30, 4234 /* *fields */ soc_IFP_L0_BUS_SECTION_2BIT_BCM56970_A0fmt_fields, 4235 /* bits */ 60, 4236 /* flags */ 0, 4237 }, 4238 #endif /* chips */ 4239 4240 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 4241 defined(BCM_56870_A0) || defined(BCM_56960_A0) || \ 4242 defined(BCM_56965_A0) || defined(BCM_56970_A0) 4243 { /* SOC_FORMAT_INT_IFP_L0_BUS_SECTION_32BITfmt */ 4244 /* format IFP_L0_BUS_SECTION_32BITfmt */ 4245 /* nFields */ 19, 4246 /* *fields */ soc_IFP_L0_BUS_SECTION_32BITfmt_fields, 4247 /* bits */ 608, 4248 /* flags */ 0, 4249 }, 4250 #endif /* chips */ 4251 4252 #if defined(BCM_56980_A0) 4253 { /* SOC_FORMAT_INT_IFP_L0_BUS_SECTION_32BIT_BCM56980_A0fmt */ 4254 /* format IFP_L0_BUS_SECTION_32BITfmt */ 4255 /* nFields */ 12, 4256 /* *fields */ soc_IFP_L0_BUS_SECTION_32BIT_BCM56980_A0fmt_fields, 4257 /* bits */ 384, 4258 /* flags */ 0, 4259 }, 4260 #endif /* chips */ 4261 4262 #if defined(BCM_56980_B0) 4263 { /* SOC_FORMAT_INT_IFP_L0_BUS_SECTION_32BIT_BCM56980_B0fmt */ 4264 /* format IFP_L0_BUS_SECTION_32BITfmt */ 4265 /* nFields */ 12, 4266 /* *fields */ soc_IFP_L0_BUS_SECTION_32BIT_BCM56980_A0fmt_fields, 4267 /* bits */ 384, 4268 /* flags */ 0, 4269 }, 4270 #endif /* chips */ 4271 4272 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) || \ 4273 defined(BCM_56970_A0) 4274 { /* SOC_FORMAT_INT_IFP_L0_BUS_SECTION_4BITfmt */ 4275 /* format IFP_L0_BUS_SECTION_4BITfmt */ 4276 /* nFields */ 30, 4277 /* *fields */ soc_IFP_L0_BUS_SECTION_4BITfmt_fields, 4278 /* bits */ 120, 4279 /* flags */ 0, 4280 }, 4281 #endif /* chips */ 4282 4283 #if defined(BCM_56370_A0) 4284 { /* SOC_FORMAT_INT_IFP_L0_BUS_SECTION_4BIT_BCM56370_A0fmt */ 4285 /* format IFP_L0_BUS_SECTION_4BITfmt */ 4286 /* nFields */ 38, 4287 /* *fields */ soc_IFP_L0_BUS_SECTION_4BIT_BCM56870_A0fmt_fields, 4288 /* bits */ 152, 4289 /* flags */ 0, 4290 }, 4291 #endif /* chips */ 4292 4293 #if defined(BCM_56770_A0) 4294 { /* SOC_FORMAT_INT_IFP_L0_BUS_SECTION_4BIT_BCM56770_A0fmt */ 4295 /* format IFP_L0_BUS_SECTION_4BITfmt */ 4296 /* nFields */ 38, 4297 /* *fields */ soc_IFP_L0_BUS_SECTION_4BIT_BCM56870_A0fmt_fields, 4298 /* bits */ 152, 4299 /* flags */ 0, 4300 }, 4301 #endif /* chips */ 4302 4303 #if defined(BCM_56870_A0) 4304 { /* SOC_FORMAT_INT_IFP_L0_BUS_SECTION_4BIT_BCM56870_A0fmt */ 4305 /* format IFP_L0_BUS_SECTION_4BITfmt */ 4306 /* nFields */ 38, 4307 /* *fields */ soc_IFP_L0_BUS_SECTION_4BIT_BCM56870_A0fmt_fields, 4308 /* bits */ 152, 4309 /* flags */ 0, 4310 }, 4311 #endif /* chips */ 4312 4313 #if defined(BCM_56980_A0) 4314 { /* SOC_FORMAT_INT_IFP_L0_BUS_SECTION_4BIT_BCM56980_A0fmt */ 4315 /* format IFP_L0_BUS_SECTION_4BITfmt */ 4316 /* nFields */ 25, 4317 /* *fields */ soc_IFP_L0_BUS_SECTION_4BIT_BCM56980_A0fmt_fields, 4318 /* bits */ 100, 4319 /* flags */ 0, 4320 }, 4321 #endif /* chips */ 4322 4323 #if defined(BCM_56980_B0) 4324 { /* SOC_FORMAT_INT_IFP_L0_BUS_SECTION_4BIT_BCM56980_B0fmt */ 4325 /* format IFP_L0_BUS_SECTION_4BITfmt */ 4326 /* nFields */ 25, 4327 /* *fields */ soc_IFP_L0_BUS_SECTION_4BIT_BCM56980_A0fmt_fields, 4328 /* bits */ 100, 4329 /* flags */ 0, 4330 }, 4331 #endif /* chips */ 4332 4333 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) || \ 4334 defined(BCM_56970_A0) 4335 { /* SOC_FORMAT_INT_IFP_L0_BUS_SECTION_8BITfmt */ 4336 /* format IFP_L0_BUS_SECTION_8BITfmt */ 4337 /* nFields */ 20, 4338 /* *fields */ soc_IFP_L0_BUS_SECTION_8BITfmt_fields, 4339 /* bits */ 160, 4340 /* flags */ 0, 4341 }, 4342 #endif /* chips */ 4343 4344 #if defined(BCM_56370_A0) 4345 { /* SOC_FORMAT_INT_IFP_L0_BUS_SECTION_8BIT_BCM56370_A0fmt */ 4346 /* format IFP_L0_BUS_SECTION_8BITfmt */ 4347 /* nFields */ 28, 4348 /* *fields */ soc_IFP_L0_BUS_SECTION_8BIT_BCM56370_A0fmt_fields, 4349 /* bits */ 224, 4350 /* flags */ 0, 4351 }, 4352 #endif /* chips */ 4353 4354 #if defined(BCM_56770_A0) 4355 { /* SOC_FORMAT_INT_IFP_L0_BUS_SECTION_8BIT_BCM56770_A0fmt */ 4356 /* format IFP_L0_BUS_SECTION_8BITfmt */ 4357 /* nFields */ 28, 4358 /* *fields */ soc_IFP_L0_BUS_SECTION_8BIT_BCM56370_A0fmt_fields, 4359 /* bits */ 224, 4360 /* flags */ 0, 4361 }, 4362 #endif /* chips */ 4363 4364 #if defined(BCM_56870_A0) 4365 { /* SOC_FORMAT_INT_IFP_L0_BUS_SECTION_8BIT_BCM56870_A0fmt */ 4366 /* format IFP_L0_BUS_SECTION_8BITfmt */ 4367 /* nFields */ 26, 4368 /* *fields */ soc_IFP_L0_BUS_SECTION_8BIT_BCM56870_A0fmt_fields, 4369 /* bits */ 208, 4370 /* flags */ 0, 4371 }, 4372 #endif /* chips */ 4373 4374 #if defined(BCM_56980_A0) 4375 { /* SOC_FORMAT_INT_IFP_L0_BUS_SECTION_8BIT_BCM56980_A0fmt */ 4376 /* format IFP_L0_BUS_SECTION_8BITfmt */ 4377 /* nFields */ 19, 4378 /* *fields */ soc_IFP_L0_BUS_SECTION_8BIT_BCM56980_A0fmt_fields, 4379 /* bits */ 152, 4380 /* flags */ 0, 4381 }, 4382 #endif /* chips */ 4383 4384 #if defined(BCM_56980_B0) 4385 { /* SOC_FORMAT_INT_IFP_L0_BUS_SECTION_8BIT_BCM56980_B0fmt */ 4386 /* format IFP_L0_BUS_SECTION_8BITfmt */ 4387 /* nFields */ 19, 4388 /* *fields */ soc_IFP_L0_BUS_SECTION_8BIT_BCM56980_A0fmt_fields, 4389 /* bits */ 152, 4390 /* flags */ 0, 4391 }, 4392 #endif /* chips */ 4393 4394 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 4395 defined(BCM_56870_A0) || defined(BCM_56960_A0) || \ 4396 defined(BCM_56965_A0) || defined(BCM_56970_A0) 4397 { /* SOC_FORMAT_INT_IFP_L1_BUSfmt */ 4398 /* format IFP_L1_BUSfmt */ 4399 /* nFields */ 2, 4400 /* *fields */ soc_IFP_L1_BUSfmt_fields, 4401 /* bits */ 344, 4402 /* flags */ 0, 4403 }, 4404 #endif /* chips */ 4405 4406 #if defined(BCM_56980_A0) 4407 { /* SOC_FORMAT_INT_IFP_L1_BUS_BCM56980_A0fmt */ 4408 /* format IFP_L1_BUSfmt */ 4409 /* nFields */ 3, 4410 /* *fields */ soc_IFP_L1_BUS_BCM56980_A0fmt_fields, 4411 /* bits */ 376, 4412 /* flags */ 0, 4413 }, 4414 #endif /* chips */ 4415 4416 #if defined(BCM_56980_B0) 4417 { /* SOC_FORMAT_INT_IFP_L1_BUS_BCM56980_B0fmt */ 4418 /* format IFP_L1_BUSfmt */ 4419 /* nFields */ 3, 4420 /* *fields */ soc_IFP_L1_BUS_BCM56980_A0fmt_fields, 4421 /* bits */ 376, 4422 /* flags */ 0, 4423 }, 4424 #endif /* chips */ 4425 4426 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 4427 { /* SOC_FORMAT_INT_IFP_L1_BUS_SECTION_Afmt */ 4428 /* format IFP_L1_BUS_SECTION_Afmt */ 4429 /* nFields */ 16, 4430 /* *fields */ soc_IFP_L1_BUS_SECTION_Afmt_fields, 4431 /* bits */ 88, 4432 /* flags */ 0, 4433 }, 4434 #endif /* chips */ 4435 4436 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 4437 { /* SOC_FORMAT_INT_IFP_L1_BUS_SECTION_Bfmt */ 4438 /* format IFP_L1_BUS_SECTION_Bfmt */ 4439 /* nFields */ 7, 4440 /* *fields */ soc_IFP_L1_BUS_SECTION_Bfmt_fields, 4441 /* bits */ 144, 4442 /* flags */ 0, 4443 }, 4444 #endif /* chips */ 4445 4446 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 4447 { /* SOC_FORMAT_INT_IFP_L1_BUS_SECTION_Cfmt */ 4448 /* format IFP_L1_BUS_SECTION_Cfmt */ 4449 /* nFields */ 7, 4450 /* *fields */ soc_IFP_L1_BUS_SECTION_Cfmt_fields, 4451 /* bits */ 144, 4452 /* flags */ 0, 4453 }, 4454 #endif /* chips */ 4455 4456 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 4457 defined(BCM_56870_A0) || defined(BCM_56960_A0) || \ 4458 defined(BCM_56965_A0) || defined(BCM_56970_A0) 4459 { /* SOC_FORMAT_INT_IFP_L2_BUSfmt */ 4460 /* format IFP_L2_BUSfmt */ 4461 /* nFields */ 6, 4462 /* *fields */ soc_IFP_L2_BUSfmt_fields, 4463 /* bits */ 264, 4464 /* flags */ 0, 4465 }, 4466 #endif /* chips */ 4467 4468 #if defined(BCM_56980_A0) 4469 { /* SOC_FORMAT_INT_IFP_L2_BUS_BCM56980_A0fmt */ 4470 /* format IFP_L2_BUSfmt */ 4471 /* nFields */ 30, 4472 /* *fields */ soc_IFP_L2_BUS_BCM56980_A0fmt_fields, 4473 /* bits */ 160, 4474 /* flags */ 0, 4475 }, 4476 #endif /* chips */ 4477 4478 #if defined(BCM_56980_B0) 4479 { /* SOC_FORMAT_INT_IFP_L2_BUS_BCM56980_B0fmt */ 4480 /* format IFP_L2_BUSfmt */ 4481 /* nFields */ 30, 4482 /* *fields */ soc_IFP_L2_BUS_BCM56980_A0fmt_fields, 4483 /* bits */ 160, 4484 /* flags */ 0, 4485 }, 4486 #endif /* chips */ 4487 4488 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) 4489 { /* SOC_FORMAT_INT_IFP_L3SW_CHANGE_L2_SETfmt */ 4490 /* format IFP_L3SW_CHANGE_L2_SETfmt */ 4491 /* nFields */ 15, 4492 /* *fields */ soc_IFP_L3SW_CHANGE_L2_SETfmt_fields, 4493 /* bits */ 23, 4494 /* flags */ 0, 4495 }, 4496 #endif /* chips */ 4497 4498 #if defined(BCM_56370_A0) 4499 { /* SOC_FORMAT_INT_IFP_L3SW_CHANGE_L2_SET_BCM56370_A0fmt */ 4500 /* format IFP_L3SW_CHANGE_L2_SETfmt */ 4501 /* nFields */ 15, 4502 /* *fields */ soc_IFP_L3SW_CHANGE_L2_SET_BCM56370_A0fmt_fields, 4503 /* bits */ 23, 4504 /* flags */ 0, 4505 }, 4506 #endif /* chips */ 4507 4508 #if defined(BCM_56770_A0) 4509 { /* SOC_FORMAT_INT_IFP_L3SW_CHANGE_L2_SET_BCM56770_A0fmt */ 4510 /* format IFP_L3SW_CHANGE_L2_SETfmt */ 4511 /* nFields */ 15, 4512 /* *fields */ soc_IFP_L3SW_CHANGE_L2_SET_BCM56970_A0fmt_fields, 4513 /* bits */ 23, 4514 /* flags */ 0, 4515 }, 4516 #endif /* chips */ 4517 4518 #if defined(BCM_56870_A0) 4519 { /* SOC_FORMAT_INT_IFP_L3SW_CHANGE_L2_SET_BCM56870_A0fmt */ 4520 /* format IFP_L3SW_CHANGE_L2_SETfmt */ 4521 /* nFields */ 15, 4522 /* *fields */ soc_IFP_L3SW_CHANGE_L2_SET_BCM56970_A0fmt_fields, 4523 /* bits */ 23, 4524 /* flags */ 0, 4525 }, 4526 #endif /* chips */ 4527 4528 #if defined(BCM_56970_A0) 4529 { /* SOC_FORMAT_INT_IFP_L3SW_CHANGE_L2_SET_BCM56970_A0fmt */ 4530 /* format IFP_L3SW_CHANGE_L2_SETfmt */ 4531 /* nFields */ 15, 4532 /* *fields */ soc_IFP_L3SW_CHANGE_L2_SET_BCM56970_A0fmt_fields, 4533 /* bits */ 23, 4534 /* flags */ 0, 4535 }, 4536 #endif /* chips */ 4537 4538 #if defined(BCM_56980_A0) 4539 { /* SOC_FORMAT_INT_IFP_L3SW_CHANGE_L2_SET_BCM56980_A0fmt */ 4540 /* format IFP_L3SW_CHANGE_L2_SETfmt */ 4541 /* nFields */ 15, 4542 /* *fields */ soc_IFP_L3SW_CHANGE_L2_SET_BCM56980_A0fmt_fields, 4543 /* bits */ 23, 4544 /* flags */ 0, 4545 }, 4546 #endif /* chips */ 4547 4548 #if defined(BCM_56980_B0) 4549 { /* SOC_FORMAT_INT_IFP_L3SW_CHANGE_L2_SET_BCM56980_B0fmt */ 4550 /* format IFP_L3SW_CHANGE_L2_SETfmt */ 4551 /* nFields */ 15, 4552 /* *fields */ soc_IFP_L3SW_CHANGE_L2_SET_BCM56980_A0fmt_fields, 4553 /* bits */ 23, 4554 /* flags */ 0, 4555 }, 4556 #endif /* chips */ 4557 4558 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 4559 defined(BCM_56870_A0) || defined(BCM_56960_A0) || \ 4560 defined(BCM_56965_A0) || defined(BCM_56970_A0) 4561 { /* SOC_FORMAT_INT_IFP_L3_BUSfmt */ 4562 /* format IFP_L3_BUSfmt */ 4563 /* nFields */ 32, 4564 /* *fields */ soc_IFP_L3_BUSfmt_fields, 4565 /* bits */ 160, 4566 /* flags */ 0, 4567 }, 4568 #endif /* chips */ 4569 4570 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 4571 defined(BCM_56870_A0) || defined(BCM_56960_A0) || \ 4572 defined(BCM_56965_A0) || defined(BCM_56970_A0) 4573 { /* SOC_FORMAT_INT_IFP_LB_CONTROLS_SETfmt */ 4574 /* format IFP_LB_CONTROLS_SETfmt */ 4575 /* nFields */ 3, 4576 /* *fields */ soc_IFP_LB_CONTROLS_SETfmt_fields, 4577 /* bits */ 3, 4578 /* flags */ 0, 4579 }, 4580 #endif /* chips */ 4581 4582 #if defined(BCM_56980_A0) 4583 { /* SOC_FORMAT_INT_IFP_LB_CONTROLS_SET_BCM56980_A0fmt */ 4584 /* format IFP_LB_CONTROLS_SETfmt */ 4585 /* nFields */ 2, 4586 /* *fields */ soc_IFP_LB_CONTROLS_SET_BCM56980_A0fmt_fields, 4587 /* bits */ 2, 4588 /* flags */ 0, 4589 }, 4590 #endif /* chips */ 4591 4592 #if defined(BCM_56980_B0) 4593 { /* SOC_FORMAT_INT_IFP_LB_CONTROLS_SET_BCM56980_B0fmt */ 4594 /* format IFP_LB_CONTROLS_SETfmt */ 4595 /* nFields */ 2, 4596 /* *fields */ soc_IFP_LB_CONTROLS_SET_BCM56980_A0fmt_fields, 4597 /* bits */ 2, 4598 /* flags */ 0, 4599 }, 4600 #endif /* chips */ 4601 4602 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 4603 { /* SOC_FORMAT_INT_IFP_LOGICAL_TABLE_SELECT_DATA_FORMATfmt */ 4604 /* format IFP_LOGICAL_TABLE_SELECT_DATA_FORMATfmt */ 4605 /* nFields */ 25, 4606 /* *fields */ soc_IFP_LOGICAL_TABLE_SELECT_DATA_FORMATfmt_fields, 4607 /* bits */ 58, 4608 /* flags */ 0, 4609 }, 4610 #endif /* chips */ 4611 4612 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 4613 { /* SOC_FORMAT_INT_IFP_LOGICAL_TABLE_SELECT_TCAM_FORMATfmt */ 4614 /* format IFP_LOGICAL_TABLE_SELECT_TCAM_FORMATfmt */ 4615 /* nFields */ 39, 4616 /* *fields */ soc_IFP_LOGICAL_TABLE_SELECT_TCAM_FORMATfmt_fields, 4617 /* bits */ 201, 4618 /* flags */ 0, 4619 }, 4620 #endif /* chips */ 4621 4622 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) 4623 { /* SOC_FORMAT_INT_IFP_LOGICAL_TBL_DOPfmt */ 4624 /* format IFP_LOGICAL_TBL_DOPfmt */ 4625 /* nFields */ 26, 4626 /* *fields */ soc_IFP_LOGICAL_TBL_DOPfmt_fields, 4627 /* bits */ 128, 4628 /* flags */ 0, 4629 }, 4630 #endif /* chips */ 4631 4632 #if defined(BCM_56370_A0) 4633 { /* SOC_FORMAT_INT_IFP_LOGICAL_TBL_DOP_BCM56370_A0fmt */ 4634 /* format IFP_LOGICAL_TBL_DOPfmt */ 4635 /* nFields */ 38, 4636 /* *fields */ soc_IFP_LOGICAL_TBL_DOP_BCM56370_A0fmt_fields, 4637 /* bits */ 224, 4638 /* flags */ 0, 4639 }, 4640 #endif /* chips */ 4641 4642 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) 4643 { /* SOC_FORMAT_INT_IFP_LOOKUP_STATUS_VECTORfmt */ 4644 /* format IFP_LOOKUP_STATUS_VECTORfmt */ 4645 /* nFields */ 17, 4646 /* *fields */ soc_IFP_LOOKUP_STATUS_VECTORfmt_fields, 4647 /* bits */ 20, 4648 /* flags */ 0, 4649 }, 4650 #endif /* chips */ 4651 4652 #if defined(BCM_56370_A0) 4653 { /* SOC_FORMAT_INT_IFP_LOOKUP_STATUS_VECTOR_BCM56370_A0fmt */ 4654 /* format IFP_LOOKUP_STATUS_VECTORfmt */ 4655 /* nFields */ 19, 4656 /* *fields */ soc_IFP_LOOKUP_STATUS_VECTOR_BCM56870_A0fmt_fields, 4657 /* bits */ 24, 4658 /* flags */ 0, 4659 }, 4660 #endif /* chips */ 4661 4662 #if defined(BCM_56770_A0) 4663 { /* SOC_FORMAT_INT_IFP_LOOKUP_STATUS_VECTOR_BCM56770_A0fmt */ 4664 /* format IFP_LOOKUP_STATUS_VECTORfmt */ 4665 /* nFields */ 19, 4666 /* *fields */ soc_IFP_LOOKUP_STATUS_VECTOR_BCM56870_A0fmt_fields, 4667 /* bits */ 24, 4668 /* flags */ 0, 4669 }, 4670 #endif /* chips */ 4671 4672 #if defined(BCM_56870_A0) 4673 { /* SOC_FORMAT_INT_IFP_LOOKUP_STATUS_VECTOR_BCM56870_A0fmt */ 4674 /* format IFP_LOOKUP_STATUS_VECTORfmt */ 4675 /* nFields */ 19, 4676 /* *fields */ soc_IFP_LOOKUP_STATUS_VECTOR_BCM56870_A0fmt_fields, 4677 /* bits */ 24, 4678 /* flags */ 0, 4679 }, 4680 #endif /* chips */ 4681 4682 #if defined(BCM_56970_A0) 4683 { /* SOC_FORMAT_INT_IFP_LOOKUP_STATUS_VECTOR_BCM56970_A0fmt */ 4684 /* format IFP_LOOKUP_STATUS_VECTORfmt */ 4685 /* nFields */ 16, 4686 /* *fields */ soc_IFP_LOOKUP_STATUS_VECTOR_BCM56970_A0fmt_fields, 4687 /* bits */ 19, 4688 /* flags */ 0, 4689 }, 4690 #endif /* chips */ 4691 4692 #if defined(BCM_56980_A0) 4693 { /* SOC_FORMAT_INT_IFP_LOOKUP_STATUS_VECTOR_BCM56980_A0fmt */ 4694 /* format IFP_LOOKUP_STATUS_VECTORfmt */ 4695 /* nFields */ 7, 4696 /* *fields */ soc_IFP_LOOKUP_STATUS_VECTOR_BCM56980_A0fmt_fields, 4697 /* bits */ 8, 4698 /* flags */ 0, 4699 }, 4700 #endif /* chips */ 4701 4702 #if defined(BCM_56980_B0) 4703 { /* SOC_FORMAT_INT_IFP_LOOKUP_STATUS_VECTOR_BCM56980_B0fmt */ 4704 /* format IFP_LOOKUP_STATUS_VECTORfmt */ 4705 /* nFields */ 7, 4706 /* *fields */ soc_IFP_LOOKUP_STATUS_VECTOR_BCM56980_A0fmt_fields, 4707 /* bits */ 8, 4708 /* flags */ 0, 4709 }, 4710 #endif /* chips */ 4711 4712 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 4713 defined(BCM_56870_A0) 4714 { /* SOC_FORMAT_INT_IFP_LOOKUP_STATUS_VECTOR_DOPfmt */ 4715 /* format IFP_LOOKUP_STATUS_VECTOR_DOPfmt */ 4716 /* nFields */ 3, 4717 /* *fields */ soc_IFP_LOOKUP_STATUS_VECTOR_DOPfmt_fields, 4718 /* bits */ 32, 4719 /* flags */ 0, 4720 }, 4721 #endif /* chips */ 4722 4723 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 4724 { /* SOC_FORMAT_INT_IFP_LOOKUP_STATUS_VECTOR_POSTfmt */ 4725 /* format IFP_LOOKUP_STATUS_VECTOR_POSTfmt */ 4726 /* nFields */ 8, 4727 /* *fields */ soc_IFP_LOOKUP_STATUS_VECTOR_POSTfmt_fields, 4728 /* bits */ 8, 4729 /* flags */ 0, 4730 }, 4731 #endif /* chips */ 4732 4733 #if defined(BCM_56840_A0) || defined(BCM_56840_B0) 4734 { /* SOC_FORMAT_INT_IFP_METER_MUX_DATA_STAGINGfmt */ 4735 /* format IFP_METER_MUX_DATA_STAGINGfmt */ 4736 /* nFields */ 6, 4737 /* *fields */ soc_IFP_METER_MUX_DATA_STAGINGfmt_fields, 4738 /* bits */ 32, 4739 /* flags */ 0, 4740 }, 4741 #endif /* chips */ 4742 4743 #if defined(BCM_56340_A0) 4744 { /* SOC_FORMAT_INT_IFP_METER_MUX_DATA_STAGING_BCM56340_A0fmt */ 4745 /* format IFP_METER_MUX_DATA_STAGINGfmt */ 4746 /* nFields */ 6, 4747 /* *fields */ soc_IFP_METER_MUX_DATA_STAGING_BCM56640_A0fmt_fields, 4748 /* bits */ 32, 4749 /* flags */ 0, 4750 }, 4751 #endif /* chips */ 4752 4753 #if defined(BCM_56560_A0) 4754 { /* SOC_FORMAT_INT_IFP_METER_MUX_DATA_STAGING_BCM56560_A0fmt */ 4755 /* format IFP_METER_MUX_DATA_STAGINGfmt */ 4756 /* nFields */ 6, 4757 /* *fields */ soc_IFP_METER_MUX_DATA_STAGING_BCM56560_A0fmt_fields, 4758 /* bits */ 40, 4759 /* flags */ 0, 4760 }, 4761 #endif /* chips */ 4762 4763 #if defined(BCM_56560_B0) 4764 { /* SOC_FORMAT_INT_IFP_METER_MUX_DATA_STAGING_BCM56560_B0fmt */ 4765 /* format IFP_METER_MUX_DATA_STAGINGfmt */ 4766 /* nFields */ 6, 4767 /* *fields */ soc_IFP_METER_MUX_DATA_STAGING_BCM56560_A0fmt_fields, 4768 /* bits */ 40, 4769 /* flags */ 0, 4770 }, 4771 #endif /* chips */ 4772 4773 #if defined(BCM_56640_A0) 4774 { /* SOC_FORMAT_INT_IFP_METER_MUX_DATA_STAGING_BCM56640_A0fmt */ 4775 /* format IFP_METER_MUX_DATA_STAGINGfmt */ 4776 /* nFields */ 6, 4777 /* *fields */ soc_IFP_METER_MUX_DATA_STAGING_BCM56640_A0fmt_fields, 4778 /* bits */ 32, 4779 /* flags */ 0, 4780 }, 4781 #endif /* chips */ 4782 4783 #if defined(BCM_56670_A0) 4784 { /* SOC_FORMAT_INT_IFP_METER_MUX_DATA_STAGING_BCM56670_A0fmt */ 4785 /* format IFP_METER_MUX_DATA_STAGINGfmt */ 4786 /* nFields */ 8, 4787 /* *fields */ soc_IFP_METER_MUX_DATA_STAGING_BCM56670_A0fmt_fields, 4788 /* bits */ 40, 4789 /* flags */ 0, 4790 }, 4791 #endif /* chips */ 4792 4793 #if defined(BCM_56670_B0) 4794 { /* SOC_FORMAT_INT_IFP_METER_MUX_DATA_STAGING_BCM56670_B0fmt */ 4795 /* format IFP_METER_MUX_DATA_STAGINGfmt */ 4796 /* nFields */ 8, 4797 /* *fields */ soc_IFP_METER_MUX_DATA_STAGING_BCM56670_A0fmt_fields, 4798 /* bits */ 40, 4799 /* flags */ 0, 4800 }, 4801 #endif /* chips */ 4802 4803 #if defined(BCM_56850_A0) 4804 { /* SOC_FORMAT_INT_IFP_METER_MUX_DATA_STAGING_BCM56850_A0fmt */ 4805 /* format IFP_METER_MUX_DATA_STAGINGfmt */ 4806 /* nFields */ 6, 4807 /* *fields */ soc_IFP_METER_MUX_DATA_STAGING_BCM56850_A0fmt_fields, 4808 /* bits */ 34, 4809 /* flags */ 0, 4810 }, 4811 #endif /* chips */ 4812 4813 #if defined(BCM_56860_A0) 4814 { /* SOC_FORMAT_INT_IFP_METER_MUX_DATA_STAGING_BCM56860_A0fmt */ 4815 /* format IFP_METER_MUX_DATA_STAGINGfmt */ 4816 /* nFields */ 6, 4817 /* *fields */ soc_IFP_METER_MUX_DATA_STAGING_BCM56860_A0fmt_fields, 4818 /* bits */ 40, 4819 /* flags */ 0, 4820 }, 4821 #endif /* chips */ 4822 4823 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) || \ 4824 defined(BCM_56970_A0) 4825 { /* SOC_FORMAT_INT_IFP_METER_SETfmt */ 4826 /* format IFP_METER_SETfmt */ 4827 /* nFields */ 7, 4828 /* *fields */ soc_IFP_METER_SETfmt_fields, 4829 /* bits */ 18, 4830 /* flags */ 0, 4831 }, 4832 #endif /* chips */ 4833 4834 #if defined(BCM_56370_A0) 4835 { /* SOC_FORMAT_INT_IFP_METER_SET_BCM56370_A0fmt */ 4836 /* format IFP_METER_SETfmt */ 4837 /* nFields */ 8, 4838 /* *fields */ soc_IFP_METER_SET_BCM56870_A0fmt_fields, 4839 /* bits */ 20, 4840 /* flags */ 0, 4841 }, 4842 #endif /* chips */ 4843 4844 #if defined(BCM_56770_A0) 4845 { /* SOC_FORMAT_INT_IFP_METER_SET_BCM56770_A0fmt */ 4846 /* format IFP_METER_SETfmt */ 4847 /* nFields */ 8, 4848 /* *fields */ soc_IFP_METER_SET_BCM56870_A0fmt_fields, 4849 /* bits */ 20, 4850 /* flags */ 0, 4851 }, 4852 #endif /* chips */ 4853 4854 #if defined(BCM_56870_A0) 4855 { /* SOC_FORMAT_INT_IFP_METER_SET_BCM56870_A0fmt */ 4856 /* format IFP_METER_SETfmt */ 4857 /* nFields */ 8, 4858 /* *fields */ soc_IFP_METER_SET_BCM56870_A0fmt_fields, 4859 /* bits */ 20, 4860 /* flags */ 0, 4861 }, 4862 #endif /* chips */ 4863 4864 #if defined(BCM_56980_A0) 4865 { /* SOC_FORMAT_INT_IFP_METER_SET_BCM56980_A0fmt */ 4866 /* format IFP_METER_SETfmt */ 4867 /* nFields */ 7, 4868 /* *fields */ soc_IFP_METER_SET_BCM56980_A0fmt_fields, 4869 /* bits */ 16, 4870 /* flags */ 0, 4871 }, 4872 #endif /* chips */ 4873 4874 #if defined(BCM_56980_B0) 4875 { /* SOC_FORMAT_INT_IFP_METER_SET_BCM56980_B0fmt */ 4876 /* format IFP_METER_SETfmt */ 4877 /* nFields */ 7, 4878 /* *fields */ soc_IFP_METER_SET_BCM56980_A0fmt_fields, 4879 /* bits */ 16, 4880 /* flags */ 0, 4881 }, 4882 #endif /* chips */ 4883 4884 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 4885 defined(BCM_56870_A0) || defined(BCM_56960_A0) || \ 4886 defined(BCM_56965_A0) || defined(BCM_56970_A0) || \ 4887 defined(BCM_56980_A0) || defined(BCM_56980_B0) 4888 { /* SOC_FORMAT_INT_IFP_MIRROR_OVERRIDE_SETfmt */ 4889 /* format IFP_MIRROR_OVERRIDE_SETfmt */ 4890 /* nFields */ 1, 4891 /* *fields */ soc_IFP_MIRROR_OVERRIDE_SETfmt_fields, 4892 /* bits */ 1, 4893 /* flags */ 0, 4894 }, 4895 #endif /* chips */ 4896 4897 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 4898 defined(BCM_56870_A0) || defined(BCM_56960_A0) || \ 4899 defined(BCM_56965_A0) || defined(BCM_56970_A0) 4900 { /* SOC_FORMAT_INT_IFP_MIRROR_SETfmt */ 4901 /* format IFP_MIRROR_SETfmt */ 4902 /* nFields */ 5, 4903 /* *fields */ soc_IFP_MIRROR_SETfmt_fields, 4904 /* bits */ 12, 4905 /* flags */ 0, 4906 }, 4907 #endif /* chips */ 4908 4909 #if defined(BCM_56980_A0) 4910 { /* SOC_FORMAT_INT_IFP_MIRROR_SET_BCM56980_A0fmt */ 4911 /* format IFP_MIRROR_SETfmt */ 4912 /* nFields */ 6, 4913 /* *fields */ soc_IFP_MIRROR_SET_BCM56980_A0fmt_fields, 4914 /* bits */ 15, 4915 /* flags */ 0, 4916 }, 4917 #endif /* chips */ 4918 4919 #if defined(BCM_56980_B0) 4920 { /* SOC_FORMAT_INT_IFP_MIRROR_SET_BCM56980_B0fmt */ 4921 /* format IFP_MIRROR_SETfmt */ 4922 /* nFields */ 6, 4923 /* *fields */ soc_IFP_MIRROR_SET_BCM56980_A0fmt_fields, 4924 /* bits */ 15, 4925 /* flags */ 0, 4926 }, 4927 #endif /* chips */ 4928 4929 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 4930 defined(BCM_56870_A0) || defined(BCM_56960_A0) || \ 4931 defined(BCM_56965_A0) || defined(BCM_56970_A0) || \ 4932 defined(BCM_56980_A0) || defined(BCM_56980_B0) 4933 { /* SOC_FORMAT_INT_IFP_MPLS_FORWARDING_LABEL_ACTIONfmt */ 4934 /* format IFP_MPLS_FORWARDING_LABEL_ACTIONfmt */ 4935 /* nFields */ 1, 4936 /* *fields */ soc_IFP_MPLS_FORWARDING_LABEL_ACTIONfmt_fields, 4937 /* bits */ 4, 4938 /* flags */ 0, 4939 }, 4940 #endif /* chips */ 4941 4942 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 4943 defined(BCM_56870_A0) || defined(BCM_56960_A0) || \ 4944 defined(BCM_56965_A0) || defined(BCM_56970_A0) 4945 { /* SOC_FORMAT_INT_IFP_NAT_OVERRIDE_SETfmt */ 4946 /* format IFP_NAT_OVERRIDE_SETfmt */ 4947 /* nFields */ 1, 4948 /* *fields */ soc_IFP_NAT_OVERRIDE_SETfmt_fields, 4949 /* bits */ 1, 4950 /* flags */ 0, 4951 }, 4952 #endif /* chips */ 4953 4954 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 4955 defined(BCM_56870_A0) || defined(BCM_56960_A0) || \ 4956 defined(BCM_56965_A0) || defined(BCM_56970_A0) 4957 { /* SOC_FORMAT_INT_IFP_NAT_SETfmt */ 4958 /* format IFP_NAT_SETfmt */ 4959 /* nFields */ 3, 4960 /* *fields */ soc_IFP_NAT_SETfmt_fields, 4961 /* bits */ 12, 4962 /* flags */ 0, 4963 }, 4964 #endif /* chips */ 4965 4966 #if defined(BCM_56640_A0) 4967 { /* SOC_FORMAT_INT_IFP_ODD_METER_COV_DEFSfmt */ 4968 /* format IFP_ODD_METER_COV_DEFSfmt */ 4969 /* nFields */ 7, 4970 /* *fields */ soc_IFP_EVEN_METER_COV_DEFSfmt_fields, 4971 /* bits */ 27, 4972 /* flags */ 0, 4973 }, 4974 #endif /* chips */ 4975 4976 #if defined(BCM_53400_A0) 4977 { /* SOC_FORMAT_INT_IFP_ODD_METER_COV_DEFS_BCM53400_A0fmt */ 4978 /* format IFP_ODD_METER_COV_DEFSfmt */ 4979 /* nFields */ 7, 4980 /* *fields */ soc_IFP_EVEN_METER_COV_DEFS_BCM53400_A0fmt_fields, 4981 /* bits */ 14, 4982 /* flags */ 0, 4983 }, 4984 #endif /* chips */ 4985 4986 #if defined(BCM_53540_A0) 4987 { /* SOC_FORMAT_INT_IFP_ODD_METER_COV_DEFS_BCM53540_A0fmt */ 4988 /* format IFP_ODD_METER_COV_DEFSfmt */ 4989 /* nFields */ 7, 4990 /* *fields */ soc_IFP_EVEN_METER_COV_DEFS_BCM53400_A0fmt_fields, 4991 /* bits */ 14, 4992 /* flags */ 0, 4993 }, 4994 #endif /* chips */ 4995 4996 #if defined(BCM_53570_A0) 4997 { /* SOC_FORMAT_INT_IFP_ODD_METER_COV_DEFS_BCM53570_A0fmt */ 4998 /* format IFP_ODD_METER_COV_DEFSfmt */ 4999 /* nFields */ 7, 5000 /* *fields */ soc_IFP_EVEN_METER_COV_DEFS_BCM53400_A0fmt_fields, 5001 /* bits */ 14, 5002 /* flags */ 0, 5003 }, 5004 #endif /* chips */ 5005 5006 #if defined(BCM_53570_B0) 5007 { /* SOC_FORMAT_INT_IFP_ODD_METER_COV_DEFS_BCM53570_B0fmt */ 5008 /* format IFP_ODD_METER_COV_DEFSfmt */ 5009 /* nFields */ 7, 5010 /* *fields */ soc_IFP_EVEN_METER_COV_DEFS_BCM53400_A0fmt_fields, 5011 /* bits */ 14, 5012 /* flags */ 0, 5013 }, 5014 #endif /* chips */ 5015 5016 #if defined(BCM_56150_A0) 5017 { /* SOC_FORMAT_INT_IFP_ODD_METER_COV_DEFS_BCM56150_A0fmt */ 5018 /* format IFP_ODD_METER_COV_DEFSfmt */ 5019 /* nFields */ 7, 5020 /* *fields */ soc_EFP_EVEN_METER_COV_DEFS_BCM56850_A0fmt_fields, 5021 /* bits */ 14, 5022 /* flags */ 0, 5023 }, 5024 #endif /* chips */ 5025 5026 #if defined(BCM_56160_A0) 5027 { /* SOC_FORMAT_INT_IFP_ODD_METER_COV_DEFS_BCM56160_A0fmt */ 5028 /* format IFP_ODD_METER_COV_DEFSfmt */ 5029 /* nFields */ 7, 5030 /* *fields */ soc_IFP_EVEN_METER_COV_DEFS_BCM53400_A0fmt_fields, 5031 /* bits */ 14, 5032 /* flags */ 0, 5033 }, 5034 #endif /* chips */ 5035 5036 #if defined(BCM_56340_A0) 5037 { /* SOC_FORMAT_INT_IFP_ODD_METER_COV_DEFS_BCM56340_A0fmt */ 5038 /* format IFP_ODD_METER_COV_DEFSfmt */ 5039 /* nFields */ 7, 5040 /* *fields */ soc_IFP_EVEN_METER_COV_DEFSfmt_fields, 5041 /* bits */ 27, 5042 /* flags */ 0, 5043 }, 5044 #endif /* chips */ 5045 5046 #if defined(BCM_56370_A0) 5047 { /* SOC_FORMAT_INT_IFP_ODD_METER_COV_DEFS_BCM56370_A0fmt */ 5048 /* format IFP_ODD_METER_COV_DEFSfmt */ 5049 /* nFields */ 7, 5050 /* *fields */ soc_IFP_EVEN_METER_COV_DEFS_BCM56970_A0fmt_fields, 5051 /* bits */ 17, 5052 /* flags */ 0, 5053 }, 5054 #endif /* chips */ 5055 5056 #if defined(BCM_56560_A0) 5057 { /* SOC_FORMAT_INT_IFP_ODD_METER_COV_DEFS_BCM56560_A0fmt */ 5058 /* format IFP_ODD_METER_COV_DEFSfmt */ 5059 /* nFields */ 10, 5060 /* *fields */ soc_IFP_EVEN_METER_COV_DEFS_BCM56560_A0fmt_fields, 5061 /* bits */ 27, 5062 /* flags */ 0, 5063 }, 5064 #endif /* chips */ 5065 5066 #if defined(BCM_56560_B0) 5067 { /* SOC_FORMAT_INT_IFP_ODD_METER_COV_DEFS_BCM56560_B0fmt */ 5068 /* format IFP_ODD_METER_COV_DEFSfmt */ 5069 /* nFields */ 10, 5070 /* *fields */ soc_IFP_EVEN_METER_COV_DEFS_BCM56560_A0fmt_fields, 5071 /* bits */ 27, 5072 /* flags */ 0, 5073 }, 5074 #endif /* chips */ 5075 5076 #if defined(BCM_56670_A0) 5077 { /* SOC_FORMAT_INT_IFP_ODD_METER_COV_DEFS_BCM56670_A0fmt */ 5078 /* format IFP_ODD_METER_COV_DEFSfmt */ 5079 /* nFields */ 10, 5080 /* *fields */ soc_IFP_EVEN_METER_COV_DEFS_BCM56560_A0fmt_fields, 5081 /* bits */ 27, 5082 /* flags */ 0, 5083 }, 5084 #endif /* chips */ 5085 5086 #if defined(BCM_56670_B0) 5087 { /* SOC_FORMAT_INT_IFP_ODD_METER_COV_DEFS_BCM56670_B0fmt */ 5088 /* format IFP_ODD_METER_COV_DEFSfmt */ 5089 /* nFields */ 10, 5090 /* *fields */ soc_IFP_EVEN_METER_COV_DEFS_BCM56560_A0fmt_fields, 5091 /* bits */ 27, 5092 /* flags */ 0, 5093 }, 5094 #endif /* chips */ 5095 5096 #if defined(BCM_56770_A0) 5097 { /* SOC_FORMAT_INT_IFP_ODD_METER_COV_DEFS_BCM56770_A0fmt */ 5098 /* format IFP_ODD_METER_COV_DEFSfmt */ 5099 /* nFields */ 7, 5100 /* *fields */ soc_IFP_EVEN_METER_COV_DEFS_BCM56970_A0fmt_fields, 5101 /* bits */ 17, 5102 /* flags */ 0, 5103 }, 5104 #endif /* chips */ 5105 5106 #if defined(BCM_56850_A0) 5107 { /* SOC_FORMAT_INT_IFP_ODD_METER_COV_DEFS_BCM56850_A0fmt */ 5108 /* format IFP_ODD_METER_COV_DEFSfmt */ 5109 /* nFields */ 9, 5110 /* *fields */ soc_IFP_EVEN_METER_COV_DEFS_BCM56850_A0fmt_fields, 5111 /* bits */ 26, 5112 /* flags */ 0, 5113 }, 5114 #endif /* chips */ 5115 5116 #if defined(BCM_56860_A0) 5117 { /* SOC_FORMAT_INT_IFP_ODD_METER_COV_DEFS_BCM56860_A0fmt */ 5118 /* format IFP_ODD_METER_COV_DEFSfmt */ 5119 /* nFields */ 10, 5120 /* *fields */ soc_IFP_EVEN_METER_COV_DEFS_BCM56860_A0fmt_fields, 5121 /* bits */ 27, 5122 /* flags */ 0, 5123 }, 5124 #endif /* chips */ 5125 5126 #if defined(BCM_56870_A0) 5127 { /* SOC_FORMAT_INT_IFP_ODD_METER_COV_DEFS_BCM56870_A0fmt */ 5128 /* format IFP_ODD_METER_COV_DEFSfmt */ 5129 /* nFields */ 7, 5130 /* *fields */ soc_IFP_EVEN_METER_COV_DEFS_BCM56970_A0fmt_fields, 5131 /* bits */ 17, 5132 /* flags */ 0, 5133 }, 5134 #endif /* chips */ 5135 5136 #if defined(BCM_56960_A0) 5137 { /* SOC_FORMAT_INT_IFP_ODD_METER_COV_DEFS_BCM56960_A0fmt */ 5138 /* format IFP_ODD_METER_COV_DEFSfmt */ 5139 /* nFields */ 9, 5140 /* *fields */ soc_IFP_EVEN_METER_COV_DEFS_BCM56960_A0fmt_fields, 5141 /* bits */ 26, 5142 /* flags */ 0, 5143 }, 5144 #endif /* chips */ 5145 5146 #if defined(BCM_56965_A0) 5147 { /* SOC_FORMAT_INT_IFP_ODD_METER_COV_DEFS_BCM56965_A0fmt */ 5148 /* format IFP_ODD_METER_COV_DEFSfmt */ 5149 /* nFields */ 9, 5150 /* *fields */ soc_IFP_EVEN_METER_COV_DEFS_BCM56960_A0fmt_fields, 5151 /* bits */ 26, 5152 /* flags */ 0, 5153 }, 5154 #endif /* chips */ 5155 5156 #if defined(BCM_56970_A0) 5157 { /* SOC_FORMAT_INT_IFP_ODD_METER_COV_DEFS_BCM56970_A0fmt */ 5158 /* format IFP_ODD_METER_COV_DEFSfmt */ 5159 /* nFields */ 7, 5160 /* *fields */ soc_IFP_EVEN_METER_COV_DEFS_BCM56970_A0fmt_fields, 5161 /* bits */ 17, 5162 /* flags */ 0, 5163 }, 5164 #endif /* chips */ 5165 5166 #if defined(BCM_56980_A0) 5167 { /* SOC_FORMAT_INT_IFP_ODD_METER_COV_DEFS_BCM56980_A0fmt */ 5168 /* format IFP_ODD_METER_COV_DEFSfmt */ 5169 /* nFields */ 7, 5170 /* *fields */ soc_IFP_EVEN_METER_COV_DEFS_BCM56970_A0fmt_fields, 5171 /* bits */ 17, 5172 /* flags */ 0, 5173 }, 5174 #endif /* chips */ 5175 5176 #if defined(BCM_56980_B0) 5177 { /* SOC_FORMAT_INT_IFP_ODD_METER_COV_DEFS_BCM56980_B0fmt */ 5178 /* format IFP_ODD_METER_COV_DEFSfmt */ 5179 /* nFields */ 7, 5180 /* *fields */ soc_IFP_EVEN_METER_COV_DEFS_BCM56970_A0fmt_fields, 5181 /* bits */ 17, 5182 /* flags */ 0, 5183 }, 5184 #endif /* chips */ 5185 5186 #if defined(BCM_56840_A0) || defined(BCM_56840_B0) 5187 { /* SOC_FORMAT_INT_IFP_PAIRING_F1fmt */ 5188 /* format IFP_PAIRING_F1fmt */ 5189 /* nFields */ 4, 5190 /* *fields */ soc_IFP_PAIRING_F1fmt_fields, 5191 /* bits */ 19, 5192 /* flags */ 0, 5193 }, 5194 #endif /* chips */ 5195 5196 #if defined(BCM_56850_A0) 5197 { /* SOC_FORMAT_INT_IFP_PAIRING_FIXEDfmt */ 5198 /* format IFP_PAIRING_FIXEDfmt */ 5199 /* nFields */ 4, 5200 /* *fields */ soc_IFP_PAIRING_FIXEDfmt_fields, 5201 /* bits */ 22, 5202 /* flags */ 0, 5203 }, 5204 #endif /* chips */ 5205 5206 #if defined(BCM_56560_A0) 5207 { /* SOC_FORMAT_INT_IFP_PAIRING_FIXED_BCM56560_A0fmt */ 5208 /* format IFP_PAIRING_FIXEDfmt */ 5209 /* nFields */ 4, 5210 /* *fields */ soc_IFP_PAIRING_FIXED_BCM56560_A0fmt_fields, 5211 /* bits */ 24, 5212 /* flags */ 0, 5213 }, 5214 #endif /* chips */ 5215 5216 #if defined(BCM_56560_B0) 5217 { /* SOC_FORMAT_INT_IFP_PAIRING_FIXED_BCM56560_B0fmt */ 5218 /* format IFP_PAIRING_FIXEDfmt */ 5219 /* nFields */ 4, 5220 /* *fields */ soc_IFP_PAIRING_FIXED_BCM56560_A0fmt_fields, 5221 /* bits */ 24, 5222 /* flags */ 0, 5223 }, 5224 #endif /* chips */ 5225 5226 #if defined(BCM_56670_A0) 5227 { /* SOC_FORMAT_INT_IFP_PAIRING_FIXED_BCM56670_A0fmt */ 5228 /* format IFP_PAIRING_FIXEDfmt */ 5229 /* nFields */ 4, 5230 /* *fields */ soc_IFP_PAIRING_FIXED_BCM56670_A0fmt_fields, 5231 /* bits */ 25, 5232 /* flags */ 0, 5233 }, 5234 #endif /* chips */ 5235 5236 #if defined(BCM_56670_B0) 5237 { /* SOC_FORMAT_INT_IFP_PAIRING_FIXED_BCM56670_B0fmt */ 5238 /* format IFP_PAIRING_FIXEDfmt */ 5239 /* nFields */ 4, 5240 /* *fields */ soc_IFP_PAIRING_FIXED_BCM56670_A0fmt_fields, 5241 /* bits */ 25, 5242 /* flags */ 0, 5243 }, 5244 #endif /* chips */ 5245 5246 #if defined(BCM_56860_A0) 5247 { /* SOC_FORMAT_INT_IFP_PAIRING_FIXED_BCM56860_A0fmt */ 5248 /* format IFP_PAIRING_FIXEDfmt */ 5249 /* nFields */ 4, 5250 /* *fields */ soc_IFP_PAIRING_FIXED_BCM56860_A0fmt_fields, 5251 /* bits */ 24, 5252 /* flags */ 0, 5253 }, 5254 #endif /* chips */ 5255 5256 #if defined(BCM_56840_A0) || defined(BCM_56840_B0) 5257 { /* SOC_FORMAT_INT_IFP_PAIRING_IPBM_F0fmt */ 5258 /* format IFP_PAIRING_IPBM_F0fmt */ 5259 /* nFields */ 8, 5260 /* *fields */ soc_IFP_PAIRING_IPBM_F0fmt_fields, 5261 /* bits */ 66, 5262 /* flags */ 0, 5263 }, 5264 #endif /* chips */ 5265 5266 #if defined(BCM_56560_A0) 5267 { /* SOC_FORMAT_INT_IFP_PAIRING_IPBM_F0_BCM56560_A0fmt */ 5268 /* format IFP_PAIRING_IPBM_F0fmt */ 5269 /* nFields */ 5, 5270 /* *fields */ soc_IFP_PAIRING_IPBM_F0_BCM56560_A0fmt_fields, 5271 /* bits */ 75, 5272 /* flags */ 0, 5273 }, 5274 #endif /* chips */ 5275 5276 #if defined(BCM_56560_B0) 5277 { /* SOC_FORMAT_INT_IFP_PAIRING_IPBM_F0_BCM56560_B0fmt */ 5278 /* format IFP_PAIRING_IPBM_F0fmt */ 5279 /* nFields */ 5, 5280 /* *fields */ soc_IFP_PAIRING_IPBM_F0_BCM56560_A0fmt_fields, 5281 /* bits */ 75, 5282 /* flags */ 0, 5283 }, 5284 #endif /* chips */ 5285 5286 #if defined(BCM_56670_A0) 5287 { /* SOC_FORMAT_INT_IFP_PAIRING_IPBM_F0_BCM56670_A0fmt */ 5288 /* format IFP_PAIRING_IPBM_F0fmt */ 5289 /* nFields */ 5, 5290 /* *fields */ soc_IFP_PAIRING_IPBM_F0_BCM56560_A0fmt_fields, 5291 /* bits */ 75, 5292 /* flags */ 0, 5293 }, 5294 #endif /* chips */ 5295 5296 #if defined(BCM_56670_B0) 5297 { /* SOC_FORMAT_INT_IFP_PAIRING_IPBM_F0_BCM56670_B0fmt */ 5298 /* format IFP_PAIRING_IPBM_F0fmt */ 5299 /* nFields */ 5, 5300 /* *fields */ soc_IFP_PAIRING_IPBM_F0_BCM56560_A0fmt_fields, 5301 /* bits */ 75, 5302 /* flags */ 0, 5303 }, 5304 #endif /* chips */ 5305 5306 #if defined(BCM_56850_A0) 5307 { /* SOC_FORMAT_INT_IFP_PAIRING_IPBM_F0_BCM56850_A0fmt */ 5308 /* format IFP_PAIRING_IPBM_F0fmt */ 5309 /* nFields */ 5, 5310 /* *fields */ soc_IFP_PAIRING_IPBM_F0_BCM56850_A0fmt_fields, 5311 /* bits */ 53, 5312 /* flags */ 0, 5313 }, 5314 #endif /* chips */ 5315 5316 #if defined(BCM_56860_A0) 5317 { /* SOC_FORMAT_INT_IFP_PAIRING_IPBM_F0_BCM56860_A0fmt */ 5318 /* format IFP_PAIRING_IPBM_F0fmt */ 5319 /* nFields */ 7, 5320 /* *fields */ soc_IFP_PAIRING_IPBM_F0_BCM56860_A0fmt_fields, 5321 /* bits */ 53, 5322 /* flags */ 0, 5323 }, 5324 #endif /* chips */ 5325 5326 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) 5327 { /* SOC_FORMAT_INT_IFP_POLICY_PDD_OUT_BUSfmt */ 5328 /* format IFP_POLICY_PDD_OUT_BUSfmt */ 5329 /* nFields */ 131, 5330 /* *fields */ soc_IFP_POLICY_PDD_OUT_BUSfmt_fields, 5331 /* bits */ 426, 5332 /* flags */ 0, 5333 }, 5334 #endif /* chips */ 5335 5336 #if defined(BCM_56370_A0) 5337 { /* SOC_FORMAT_INT_IFP_POLICY_PDD_OUT_BUS_BCM56370_A0fmt */ 5338 /* format IFP_POLICY_PDD_OUT_BUSfmt */ 5339 /* nFields */ 131, 5340 /* *fields */ soc_IFP_POLICY_PDD_OUT_BUS_BCM56370_A0fmt_fields, 5341 /* bits */ 432, 5342 /* flags */ 0, 5343 }, 5344 #endif /* chips */ 5345 5346 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 5347 defined(BCM_56870_A0) || defined(BCM_56960_A0) || \ 5348 defined(BCM_56965_A0) || defined(BCM_56970_A0) 5349 { /* SOC_FORMAT_INT_IFP_POST_MUX_CONTROLSfmt */ 5350 /* format IFP_POST_MUX_CONTROLSfmt */ 5351 /* nFields */ 15, 5352 /* *fields */ soc_IFP_POST_MUX_CONTROLSfmt_fields, 5353 /* bits */ 15, 5354 /* flags */ 0, 5355 }, 5356 #endif /* chips */ 5357 5358 #if defined(BCM_56980_A0) 5359 { /* SOC_FORMAT_INT_IFP_POST_MUX_CONTROLS_BCM56980_A0fmt */ 5360 /* format IFP_POST_MUX_CONTROLSfmt */ 5361 /* nFields */ 15, 5362 /* *fields */ soc_IFP_POST_MUX_CONTROLS_BCM56980_A0fmt_fields, 5363 /* bits */ 15, 5364 /* flags */ 0, 5365 }, 5366 #endif /* chips */ 5367 5368 #if defined(BCM_56980_B0) 5369 { /* SOC_FORMAT_INT_IFP_POST_MUX_CONTROLS_BCM56980_B0fmt */ 5370 /* format IFP_POST_MUX_CONTROLSfmt */ 5371 /* nFields */ 15, 5372 /* *fields */ soc_IFP_POST_MUX_CONTROLS_BCM56980_A0fmt_fields, 5373 /* bits */ 15, 5374 /* flags */ 0, 5375 }, 5376 #endif /* chips */ 5377 5378 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \ 5379 defined(BCM_56960_A0) || defined(BCM_56965_A0) || \ 5380 defined(BCM_56970_A0) 5381 { /* SOC_FORMAT_INT_IFP_PROFILE_SET_1fmt */ 5382 /* format IFP_PROFILE_SET_1fmt */ 5383 /* nFields */ 17, 5384 /* *fields */ soc_IFP_PROFILE_SET_1fmt_fields, 5385 /* bits */ 56, 5386 /* flags */ 0, 5387 }, 5388 #endif /* chips */ 5389 5390 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 5391 defined(BCM_56870_A0) || defined(BCM_56960_A0) || \ 5392 defined(BCM_56965_A0) || defined(BCM_56970_A0) 5393 { /* SOC_FORMAT_INT_IFP_PROFILE_SET_2fmt */ 5394 /* format IFP_PROFILE_SET_2fmt */ 5395 /* nFields */ 18, 5396 /* *fields */ soc_IFP_PROFILE_SET_2fmt_fields, 5397 /* bits */ 52, 5398 /* flags */ 0, 5399 }, 5400 #endif /* chips */ 5401 5402 #if defined(BCM_56370_A0) 5403 { /* SOC_FORMAT_INT_IFP_PROFILE_SET_1_BCM56370_A0fmt */ 5404 /* format IFP_PROFILE_SET_1fmt */ 5405 /* nFields */ 17, 5406 /* *fields */ soc_IFP_PROFILE_SET_1_BCM56370_A0fmt_fields, 5407 /* bits */ 62, 5408 /* flags */ 0, 5409 }, 5410 #endif /* chips */ 5411 5412 #if defined(BCM_56980_A0) 5413 { /* SOC_FORMAT_INT_IFP_PROFILE_SET_1_BCM56980_A0fmt */ 5414 /* format IFP_PROFILE_SET_1fmt */ 5415 /* nFields */ 17, 5416 /* *fields */ soc_IFP_PROFILE_SET_1_BCM56980_A0fmt_fields, 5417 /* bits */ 56, 5418 /* flags */ 0, 5419 }, 5420 #endif /* chips */ 5421 5422 #if defined(BCM_56980_B0) 5423 { /* SOC_FORMAT_INT_IFP_PROFILE_SET_1_BCM56980_B0fmt */ 5424 /* format IFP_PROFILE_SET_1fmt */ 5425 /* nFields */ 17, 5426 /* *fields */ soc_IFP_PROFILE_SET_1_BCM56980_A0fmt_fields, 5427 /* bits */ 56, 5428 /* flags */ 0, 5429 }, 5430 #endif /* chips */ 5431 5432 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 5433 { /* SOC_FORMAT_INT_IFP_PROFILE_SET_1_DATA_FORMATfmt */ 5434 /* format IFP_PROFILE_SET_1_DATA_FORMATfmt */ 5435 /* nFields */ 7, 5436 /* *fields */ soc_IFP_PROFILE_SET_1_DATA_FORMATfmt_fields, 5437 /* bits */ 34, 5438 /* flags */ 0, 5439 }, 5440 #endif /* chips */ 5441 5442 #if defined(BCM_56980_A0) 5443 { /* SOC_FORMAT_INT_IFP_PROFILE_SET_2_BCM56980_A0fmt */ 5444 /* format IFP_PROFILE_SET_2fmt */ 5445 /* nFields */ 18, 5446 /* *fields */ soc_IFP_PROFILE_SET_2_BCM56980_A0fmt_fields, 5447 /* bits */ 52, 5448 /* flags */ 0, 5449 }, 5450 #endif /* chips */ 5451 5452 #if defined(BCM_56980_B0) 5453 { /* SOC_FORMAT_INT_IFP_PROFILE_SET_2_BCM56980_B0fmt */ 5454 /* format IFP_PROFILE_SET_2fmt */ 5455 /* nFields */ 18, 5456 /* *fields */ soc_IFP_PROFILE_SET_2_BCM56980_A0fmt_fields, 5457 /* bits */ 52, 5458 /* flags */ 0, 5459 }, 5460 #endif /* chips */ 5461 5462 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 5463 { /* SOC_FORMAT_INT_IFP_PROFILE_SET_2_DATA_FORMATfmt */ 5464 /* format IFP_PROFILE_SET_2_DATA_FORMATfmt */ 5465 /* nFields */ 9, 5466 /* *fields */ soc_IFP_PROFILE_SET_2_DATA_FORMATfmt_fields, 5467 /* bits */ 33, 5468 /* flags */ 0, 5469 }, 5470 #endif /* chips */ 5471 5472 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 5473 defined(BCM_56870_A0) 5474 { /* SOC_FORMAT_INT_IFP_PROTECTION_SWITCHING_DROP_OVERIDE_SETfmt */ 5475 /* format IFP_PROTECTION_SWITCHING_DROP_OVERIDE_SETfmt */ 5476 /* nFields */ 1, 5477 /* *fields */ soc_IFP_PROTECTION_SWITCHING_DROP_OVERIDE_SETfmt_fields, 5478 /* bits */ 1, 5479 /* flags */ 0, 5480 }, 5481 #endif /* chips */ 5482 5483 #if defined(BCM_56970_A0) || defined(BCM_56980_A0) || \ 5484 defined(BCM_56980_B0) 5485 { /* SOC_FORMAT_INT_IFP_PROTECTION_SWITCHING_SETfmt */ 5486 /* format IFP_PROTECTION_SWITCHING_SETfmt */ 5487 /* nFields */ 1, 5488 /* *fields */ soc_IFP_PROTECTION_SWITCHING_SETfmt_fields, 5489 /* bits */ 1, 5490 /* flags */ 0, 5491 }, 5492 #endif /* chips */ 5493 5494 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) 5495 { /* SOC_FORMAT_INT_IFP_REDIRECT_SETfmt */ 5496 /* format IFP_REDIRECT_SETfmt */ 5497 /* nFields */ 17, 5498 /* *fields */ soc_IFP_REDIRECT_SETfmt_fields, 5499 /* bits */ 38, 5500 /* flags */ 0, 5501 }, 5502 #endif /* chips */ 5503 5504 #if defined(BCM_56370_A0) 5505 { /* SOC_FORMAT_INT_IFP_REDIRECT_SET_BCM56370_A0fmt */ 5506 /* format IFP_REDIRECT_SETfmt */ 5507 /* nFields */ 4, 5508 /* *fields */ soc_IFP_REDIRECT_SET_BCM56870_A0fmt_fields, 5509 /* bits */ 38, 5510 /* flags */ 0, 5511 }, 5512 #endif /* chips */ 5513 5514 #if defined(BCM_56770_A0) 5515 { /* SOC_FORMAT_INT_IFP_REDIRECT_SET_BCM56770_A0fmt */ 5516 /* format IFP_REDIRECT_SETfmt */ 5517 /* nFields */ 4, 5518 /* *fields */ soc_IFP_REDIRECT_SET_BCM56870_A0fmt_fields, 5519 /* bits */ 38, 5520 /* flags */ 0, 5521 }, 5522 #endif /* chips */ 5523 5524 #if defined(BCM_56870_A0) 5525 { /* SOC_FORMAT_INT_IFP_REDIRECT_SET_BCM56870_A0fmt */ 5526 /* format IFP_REDIRECT_SETfmt */ 5527 /* nFields */ 4, 5528 /* *fields */ soc_IFP_REDIRECT_SET_BCM56870_A0fmt_fields, 5529 /* bits */ 38, 5530 /* flags */ 0, 5531 }, 5532 #endif /* chips */ 5533 5534 #if defined(BCM_56970_A0) 5535 { /* SOC_FORMAT_INT_IFP_REDIRECT_SET_BCM56970_A0fmt */ 5536 /* format IFP_REDIRECT_SETfmt */ 5537 /* nFields */ 17, 5538 /* *fields */ soc_IFP_REDIRECT_SET_BCM56970_A0fmt_fields, 5539 /* bits */ 38, 5540 /* flags */ 0, 5541 }, 5542 #endif /* chips */ 5543 5544 #if defined(BCM_56980_A0) 5545 { /* SOC_FORMAT_INT_IFP_REDIRECT_SET_BCM56980_A0fmt */ 5546 /* format IFP_REDIRECT_SETfmt */ 5547 /* nFields */ 17, 5548 /* *fields */ soc_IFP_REDIRECT_SET_BCM56980_A0fmt_fields, 5549 /* bits */ 38, 5550 /* flags */ 0, 5551 }, 5552 #endif /* chips */ 5553 5554 #if defined(BCM_56980_B0) 5555 { /* SOC_FORMAT_INT_IFP_REDIRECT_SET_BCM56980_B0fmt */ 5556 /* format IFP_REDIRECT_SETfmt */ 5557 /* nFields */ 17, 5558 /* *fields */ soc_IFP_REDIRECT_SET_BCM56980_A0fmt_fields, 5559 /* bits */ 38, 5560 /* flags */ 0, 5561 }, 5562 #endif /* chips */ 5563 5564 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 5565 defined(BCM_56870_A0) || defined(BCM_56960_A0) || \ 5566 defined(BCM_56965_A0) || defined(BCM_56970_A0) || \ 5567 defined(BCM_56980_A0) || defined(BCM_56980_B0) 5568 { /* SOC_FORMAT_INT_IFP_RESOLUTIONfmt */ 5569 /* format IFP_RESOLUTIONfmt */ 5570 /* nFields */ 1, 5571 /* *fields */ soc_IFP_RESOLUTIONfmt_fields, 5572 /* bits */ 6, 5573 /* flags */ 0, 5574 }, 5575 #endif /* chips */ 5576 5577 #if defined(BCM_88732_A0) 5578 { /* SOC_FORMAT_INT_IFP_SECURITY_STATUSfmt */ 5579 /* format IFP_SECURITY_STATUSfmt */ 5580 /* nFields */ 10, 5581 /* *fields */ soc_IFP_SECURITY_STATUSfmt_fields, 5582 /* bits */ 10, 5583 /* flags */ 0, 5584 }, 5585 #endif /* chips */ 5586 5587 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 5588 defined(BCM_56870_A0) || defined(BCM_56960_A0) || \ 5589 defined(BCM_56965_A0) || defined(BCM_56970_A0) || \ 5590 defined(BCM_56980_A0) || defined(BCM_56980_B0) 5591 { /* SOC_FORMAT_INT_IFP_SFLOW_SETfmt */ 5592 /* format IFP_SFLOW_SETfmt */ 5593 /* nFields */ 1, 5594 /* *fields */ soc_IFP_SFLOW_SETfmt_fields, 5595 /* bits */ 1, 5596 /* flags */ 0, 5597 }, 5598 #endif /* chips */ 5599 5600 #if defined(BCM_56850_A0) 5601 { /* SOC_FORMAT_INT_IFP_SHARED_TO_IFP_CTR_BUSfmt */ 5602 /* format IFP_SHARED_TO_IFP_CTR_BUSfmt */ 5603 /* nFields */ 1, 5604 /* *fields */ soc_IFP_SHARED_TO_IFP_CTR_BUSfmt_fields, 5605 /* bits */ 148, 5606 /* flags */ 0, 5607 }, 5608 #endif /* chips */ 5609 5610 #if defined(BCM_56560_A0) 5611 { /* SOC_FORMAT_INT_IFP_SHARED_TO_IFP_CTR_BUS_BCM56560_A0fmt */ 5612 /* format IFP_SHARED_TO_IFP_CTR_BUSfmt */ 5613 /* nFields */ 1, 5614 /* *fields */ soc_IFP_SHARED_TO_IFP_CTR_BUS_BCM56560_A0fmt_fields, 5615 /* bits */ 78, 5616 /* flags */ 0, 5617 }, 5618 #endif /* chips */ 5619 5620 #if defined(BCM_56560_B0) 5621 { /* SOC_FORMAT_INT_IFP_SHARED_TO_IFP_CTR_BUS_BCM56560_B0fmt */ 5622 /* format IFP_SHARED_TO_IFP_CTR_BUSfmt */ 5623 /* nFields */ 1, 5624 /* *fields */ soc_IFP_SHARED_TO_IFP_CTR_BUS_BCM56560_A0fmt_fields, 5625 /* bits */ 78, 5626 /* flags */ 0, 5627 }, 5628 #endif /* chips */ 5629 5630 #if defined(BCM_56670_A0) 5631 { /* SOC_FORMAT_INT_IFP_SHARED_TO_IFP_CTR_BUS_BCM56670_A0fmt */ 5632 /* format IFP_SHARED_TO_IFP_CTR_BUSfmt */ 5633 /* nFields */ 1, 5634 /* *fields */ soc_IFP_SHARED_TO_IFP_CTR_BUS_BCM56560_A0fmt_fields, 5635 /* bits */ 78, 5636 /* flags */ 0, 5637 }, 5638 #endif /* chips */ 5639 5640 #if defined(BCM_56670_B0) 5641 { /* SOC_FORMAT_INT_IFP_SHARED_TO_IFP_CTR_BUS_BCM56670_B0fmt */ 5642 /* format IFP_SHARED_TO_IFP_CTR_BUSfmt */ 5643 /* nFields */ 1, 5644 /* *fields */ soc_IFP_SHARED_TO_IFP_CTR_BUS_BCM56560_A0fmt_fields, 5645 /* bits */ 78, 5646 /* flags */ 0, 5647 }, 5648 #endif /* chips */ 5649 5650 #if defined(BCM_56860_A0) 5651 { /* SOC_FORMAT_INT_IFP_SHARED_TO_IFP_CTR_BUS_BCM56860_A0fmt */ 5652 /* format IFP_SHARED_TO_IFP_CTR_BUSfmt */ 5653 /* nFields */ 1, 5654 /* *fields */ soc_IFP_SHARED_TO_IFP_CTR_BUS_BCM56860_A0fmt_fields, 5655 /* bits */ 78, 5656 /* flags */ 0, 5657 }, 5658 #endif /* chips */ 5659 5660 #if defined(BCM_56850_A0) 5661 { /* SOC_FORMAT_INT_IFP_SHARED_TO_IFP_DATA_BUSfmt */ 5662 /* format IFP_SHARED_TO_IFP_DATA_BUSfmt */ 5663 /* nFields */ 1, 5664 /* *fields */ soc_IFP_SHARED_TO_IFP_DATA_BUSfmt_fields, 5665 /* bits */ 400, 5666 /* flags */ 0, 5667 }, 5668 #endif /* chips */ 5669 5670 #if defined(BCM_56560_A0) 5671 { /* SOC_FORMAT_INT_IFP_SHARED_TO_IFP_DATA_BUS_BCM56560_A0fmt */ 5672 /* format IFP_SHARED_TO_IFP_DATA_BUSfmt */ 5673 /* nFields */ 1, 5674 /* *fields */ soc_IFP_SHARED_TO_IFP_DATA_BUS_BCM56560_A0fmt_fields, 5675 /* bits */ 1376, 5676 /* flags */ 0, 5677 }, 5678 #endif /* chips */ 5679 5680 #if defined(BCM_56560_B0) 5681 { /* SOC_FORMAT_INT_IFP_SHARED_TO_IFP_DATA_BUS_BCM56560_B0fmt */ 5682 /* format IFP_SHARED_TO_IFP_DATA_BUSfmt */ 5683 /* nFields */ 1, 5684 /* *fields */ soc_IFP_SHARED_TO_IFP_DATA_BUS_BCM56560_A0fmt_fields, 5685 /* bits */ 1376, 5686 /* flags */ 0, 5687 }, 5688 #endif /* chips */ 5689 5690 #if defined(BCM_56670_A0) 5691 { /* SOC_FORMAT_INT_IFP_SHARED_TO_IFP_DATA_BUS_BCM56670_A0fmt */ 5692 /* format IFP_SHARED_TO_IFP_DATA_BUSfmt */ 5693 /* nFields */ 1, 5694 /* *fields */ soc_IFP_SHARED_TO_IFP_DATA_BUS_BCM56560_A0fmt_fields, 5695 /* bits */ 1376, 5696 /* flags */ 0, 5697 }, 5698 #endif /* chips */ 5699 5700 #if defined(BCM_56670_B0) 5701 { /* SOC_FORMAT_INT_IFP_SHARED_TO_IFP_DATA_BUS_BCM56670_B0fmt */ 5702 /* format IFP_SHARED_TO_IFP_DATA_BUSfmt */ 5703 /* nFields */ 1, 5704 /* *fields */ soc_IFP_SHARED_TO_IFP_DATA_BUS_BCM56560_A0fmt_fields, 5705 /* bits */ 1376, 5706 /* flags */ 0, 5707 }, 5708 #endif /* chips */ 5709 5710 #if defined(BCM_56860_A0) 5711 { /* SOC_FORMAT_INT_IFP_SHARED_TO_IFP_DATA_BUS_BCM56860_A0fmt */ 5712 /* format IFP_SHARED_TO_IFP_DATA_BUSfmt */ 5713 /* nFields */ 1, 5714 /* *fields */ soc_IFP_SHARED_TO_IFP_DATA_BUS_BCM56860_A0fmt_fields, 5715 /* bits */ 1376, 5716 /* flags */ 0, 5717 }, 5718 #endif /* chips */ 5719 5720 #if defined(BCM_56850_A0) 5721 { /* SOC_FORMAT_INT_IFP_SINGLE_COUNTER_TABLE_COV_DEFSfmt */ 5722 /* format IFP_SINGLE_COUNTER_TABLE_COV_DEFSfmt */ 5723 /* nFields */ 6, 5724 /* *fields */ soc_IFP_COUNTER_TABLE_COV_DEFSfmt_fields, 5725 /* bits */ 17, 5726 /* flags */ 0, 5727 }, 5728 #endif /* chips */ 5729 5730 #if defined(BCM_56560_A0) 5731 { /* SOC_FORMAT_INT_IFP_SINGLE_COUNTER_TABLE_COV_DEFS_BCM56560_A0fmt */ 5732 /* format IFP_SINGLE_COUNTER_TABLE_COV_DEFSfmt */ 5733 /* nFields */ 7, 5734 /* *fields */ soc_IFP_DUAL_COUNTER_TABLE_COV_DEFS_BCM56560_A0fmt_fields, 5735 /* bits */ 20, 5736 /* flags */ 0, 5737 }, 5738 #endif /* chips */ 5739 5740 #if defined(BCM_56560_B0) 5741 { /* SOC_FORMAT_INT_IFP_SINGLE_COUNTER_TABLE_COV_DEFS_BCM56560_B0fmt */ 5742 /* format IFP_SINGLE_COUNTER_TABLE_COV_DEFSfmt */ 5743 /* nFields */ 7, 5744 /* *fields */ soc_IFP_DUAL_COUNTER_TABLE_COV_DEFS_BCM56560_A0fmt_fields, 5745 /* bits */ 20, 5746 /* flags */ 0, 5747 }, 5748 #endif /* chips */ 5749 5750 #if defined(BCM_56670_A0) 5751 { /* SOC_FORMAT_INT_IFP_SINGLE_COUNTER_TABLE_COV_DEFS_BCM56670_A0fmt */ 5752 /* format IFP_SINGLE_COUNTER_TABLE_COV_DEFSfmt */ 5753 /* nFields */ 7, 5754 /* *fields */ soc_IFP_DUAL_COUNTER_TABLE_COV_DEFS_BCM56560_A0fmt_fields, 5755 /* bits */ 20, 5756 /* flags */ 0, 5757 }, 5758 #endif /* chips */ 5759 5760 #if defined(BCM_56670_B0) 5761 { /* SOC_FORMAT_INT_IFP_SINGLE_COUNTER_TABLE_COV_DEFS_BCM56670_B0fmt */ 5762 /* format IFP_SINGLE_COUNTER_TABLE_COV_DEFSfmt */ 5763 /* nFields */ 7, 5764 /* *fields */ soc_IFP_DUAL_COUNTER_TABLE_COV_DEFS_BCM56560_A0fmt_fields, 5765 /* bits */ 20, 5766 /* flags */ 0, 5767 }, 5768 #endif /* chips */ 5769 5770 #if defined(BCM_56860_A0) 5771 { /* SOC_FORMAT_INT_IFP_SINGLE_COUNTER_TABLE_COV_DEFS_BCM56860_A0fmt */ 5772 /* format IFP_SINGLE_COUNTER_TABLE_COV_DEFSfmt */ 5773 /* nFields */ 7, 5774 /* *fields */ soc_IFP_DUAL_COUNTER_TABLE_COV_DEFS_BCM56860_A0fmt_fields, 5775 /* bits */ 20, 5776 /* flags */ 0, 5777 }, 5778 #endif /* chips */ 5779 5780 #if defined(BCM_56960_A0) 5781 { /* SOC_FORMAT_INT_IFP_SINGLE_COUNTER_TABLE_COV_DEFS_BCM56960_A0fmt */ 5782 /* format IFP_SINGLE_COUNTER_TABLE_COV_DEFSfmt */ 5783 /* nFields */ 6, 5784 /* *fields */ soc_IFP_DUAL_COUNTER_TABLE_COV_DEFSfmt_fields, 5785 /* bits */ 17, 5786 /* flags */ 0, 5787 }, 5788 #endif /* chips */ 5789 5790 #if defined(BCM_56965_A0) 5791 { /* SOC_FORMAT_INT_IFP_SINGLE_COUNTER_TABLE_COV_DEFS_BCM56965_A0fmt */ 5792 /* format IFP_SINGLE_COUNTER_TABLE_COV_DEFSfmt */ 5793 /* nFields */ 6, 5794 /* *fields */ soc_IFP_DUAL_COUNTER_TABLE_COV_DEFSfmt_fields, 5795 /* bits */ 17, 5796 /* flags */ 0, 5797 }, 5798 #endif /* chips */ 5799 5800 #if defined(BCM_56624_A0) 5801 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F4fmt */ 5802 /* format IFP_SINGLE_WIDE_F4fmt */ 5803 /* nFields */ 1, 5804 /* *fields */ soc_IFP_DOUBLE_WIDE_F4_0fmt_fields, 5805 /* bits */ 6, 5806 /* flags */ 0, 5807 }, 5808 #endif /* chips */ 5809 5810 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \ 5811 defined(BCM_56680_A0) || defined(BCM_56725_A0) || \ 5812 defined(BCM_56820_A0) 5813 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_0fmt */ 5814 /* format IFP_SINGLE_WIDE_F1_0fmt */ 5815 /* nFields */ 3, 5816 /* *fields */ soc_IFP_SINGLE_WIDE_F1_0fmt_fields, 5817 /* bits */ 34, 5818 /* flags */ 0, 5819 }, 5820 #endif /* chips */ 5821 5822 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \ 5823 defined(BCM_56680_A0) || defined(BCM_56680_B0) 5824 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_1fmt */ 5825 /* format IFP_SINGLE_WIDE_F1_1fmt */ 5826 /* nFields */ 8, 5827 /* *fields */ soc_IFP_SINGLE_WIDE_F1_1fmt_fields, 5828 /* bits */ 34, 5829 /* flags */ 0, 5830 }, 5831 #endif /* chips */ 5832 5833 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \ 5834 defined(BCM_56680_A0) 5835 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_2fmt */ 5836 /* format IFP_SINGLE_WIDE_F1_2fmt */ 5837 /* nFields */ 6, 5838 /* *fields */ soc_IFP_SINGLE_WIDE_F1_2fmt_fields, 5839 /* bits */ 34, 5840 /* flags */ 0, 5841 }, 5842 #endif /* chips */ 5843 5844 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \ 5845 defined(BCM_56680_A0) || defined(BCM_88732_A0) 5846 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_3fmt */ 5847 /* format IFP_SINGLE_WIDE_F1_3fmt */ 5848 /* nFields */ 3, 5849 /* *fields */ soc_IFP_SINGLE_WIDE_F1_3fmt_fields, 5850 /* bits */ 34, 5851 /* flags */ 0, 5852 }, 5853 #endif /* chips */ 5854 5855 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \ 5856 defined(BCM_56680_A0) || defined(BCM_56680_B0) || \ 5857 defined(BCM_56725_A0) 5858 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_4fmt */ 5859 /* format IFP_SINGLE_WIDE_F1_4fmt */ 5860 /* nFields */ 3, 5861 /* *fields */ soc_IFP_SINGLE_WIDE_F1_4fmt_fields, 5862 /* bits */ 34, 5863 /* flags */ 0, 5864 }, 5865 #endif /* chips */ 5866 5867 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \ 5868 defined(BCM_56680_A0) || defined(BCM_88732_A0) 5869 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_5fmt */ 5870 /* format IFP_SINGLE_WIDE_F1_5fmt */ 5871 /* nFields */ 3, 5872 /* *fields */ soc_IFP_SINGLE_WIDE_F1_5fmt_fields, 5873 /* bits */ 34, 5874 /* flags */ 0, 5875 }, 5876 #endif /* chips */ 5877 5878 #if defined(BCM_56624_A0) 5879 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_6fmt */ 5880 /* format IFP_SINGLE_WIDE_F1_6fmt */ 5881 /* nFields */ 6, 5882 /* *fields */ soc_IFP_SINGLE_WIDE_F1_6fmt_fields, 5883 /* bits */ 32, 5884 /* flags */ 0, 5885 }, 5886 #endif /* chips */ 5887 5888 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \ 5889 defined(BCM_56680_A0) || defined(BCM_56820_A0) 5890 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_7fmt */ 5891 /* format IFP_SINGLE_WIDE_F1_7fmt */ 5892 /* nFields */ 4, 5893 /* *fields */ soc_IFP_SINGLE_WIDE_F1_7fmt_fields, 5894 /* bits */ 34, 5895 /* flags */ 0, 5896 }, 5897 #endif /* chips */ 5898 5899 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \ 5900 defined(BCM_56680_A0) || defined(BCM_56820_A0) 5901 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_8fmt */ 5902 /* format IFP_SINGLE_WIDE_F1_8fmt */ 5903 /* nFields */ 5, 5904 /* *fields */ soc_IFP_SINGLE_WIDE_F1_8fmt_fields, 5905 /* bits */ 34, 5906 /* flags */ 0, 5907 }, 5908 #endif /* chips */ 5909 5910 #if defined(BCM_56524_A0) || defined(BCM_56634_A0) || \ 5911 defined(BCM_56634_B0) 5912 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_9fmt */ 5913 /* format IFP_SINGLE_WIDE_F1_9fmt */ 5914 /* nFields */ 4, 5915 /* *fields */ soc_IFP_SINGLE_WIDE_F1_9fmt_fields, 5916 /* bits */ 37, 5917 /* flags */ 0, 5918 }, 5919 #endif /* chips */ 5920 5921 #if defined(BCM_56334_A0) || defined(BCM_56524_A0) || \ 5922 defined(BCM_56634_A0) || defined(BCM_56634_B0) || \ 5923 defined(BCM_56685_A0) 5924 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_10fmt */ 5925 /* format IFP_SINGLE_WIDE_F1_10fmt */ 5926 /* nFields */ 4, 5927 /* *fields */ soc_IFP_SINGLE_WIDE_F1_10fmt_fields, 5928 /* bits */ 37, 5929 /* flags */ 0, 5930 }, 5931 #endif /* chips */ 5932 5933 #if defined(BCM_56634_A0) 5934 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_11fmt */ 5935 /* format IFP_SINGLE_WIDE_F1_11fmt */ 5936 /* nFields */ 4, 5937 /* *fields */ soc_IFP_SINGLE_WIDE_F1_11fmt_fields, 5938 /* bits */ 37, 5939 /* flags */ 0, 5940 }, 5941 #endif /* chips */ 5942 5943 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \ 5944 defined(BCM_56634_A0) || defined(BCM_56634_B0) 5945 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_12fmt */ 5946 /* format IFP_SINGLE_WIDE_F1_12fmt */ 5947 /* nFields */ 3, 5948 /* *fields */ soc_IFP_SINGLE_WIDE_F1_12fmt_fields, 5949 /* bits */ 37, 5950 /* flags */ 0, 5951 }, 5952 #endif /* chips */ 5953 5954 #if defined(BCM_56840_A0) 5955 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_13fmt */ 5956 /* format IFP_SINGLE_WIDE_F1_13fmt */ 5957 /* nFields */ 3, 5958 /* *fields */ soc_IFP_SINGLE_WIDE_F1_13fmt_fields, 5959 /* bits */ 39, 5960 /* flags */ 0, 5961 }, 5962 #endif /* chips */ 5963 5964 #if defined(BCM_56850_A0) 5965 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_14fmt */ 5966 /* format IFP_SINGLE_WIDE_F1_14fmt */ 5967 /* nFields */ 2, 5968 /* *fields */ soc_IFP_SINGLE_WIDE_F1_14fmt_fields, 5969 /* bits */ 49, 5970 /* flags */ 0, 5971 }, 5972 #endif /* chips */ 5973 5974 #if defined(BCM_56850_A0) 5975 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_15fmt */ 5976 /* format IFP_SINGLE_WIDE_F1_15fmt */ 5977 /* nFields */ 6, 5978 /* *fields */ soc_IFP_SINGLE_WIDE_F1_15fmt_fields, 5979 /* bits */ 49, 5980 /* flags */ 0, 5981 }, 5982 #endif /* chips */ 5983 5984 #if defined(BCM_56850_A0) 5985 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_16fmt */ 5986 /* format IFP_SINGLE_WIDE_F1_16fmt */ 5987 /* nFields */ 12, 5988 /* *fields */ soc_IFP_SINGLE_WIDE_F1_16fmt_fields, 5989 /* bits */ 49, 5990 /* flags */ 0, 5991 }, 5992 #endif /* chips */ 5993 5994 #if defined(BCM_53400_A0) 5995 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_0_BCM53400_A0fmt */ 5996 /* format IFP_SINGLE_WIDE_F1_0fmt */ 5997 /* nFields */ 3, 5998 /* *fields */ soc_IFP_SINGLE_WIDE_F1_0_BCM53400_A0fmt_fields, 5999 /* bits */ 37, 6000 /* flags */ 0, 6001 }, 6002 #endif /* chips */ 6003 6004 #if defined(BCM_53540_A0) 6005 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_0_BCM53540_A0fmt */ 6006 /* format IFP_SINGLE_WIDE_F1_0fmt */ 6007 /* nFields */ 3, 6008 /* *fields */ soc_IFP_SINGLE_WIDE_F1_0_BCM53400_A0fmt_fields, 6009 /* bits */ 37, 6010 /* flags */ 0, 6011 }, 6012 #endif /* chips */ 6013 6014 #if defined(BCM_53570_A0) 6015 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_0_BCM53570_A0fmt */ 6016 /* format IFP_SINGLE_WIDE_F1_0fmt */ 6017 /* nFields */ 4, 6018 /* *fields */ soc_IFP_SINGLE_WIDE_F1_0_BCM53570_A0fmt_fields, 6019 /* bits */ 39, 6020 /* flags */ 0, 6021 }, 6022 #endif /* chips */ 6023 6024 #if defined(BCM_53570_B0) 6025 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_0_BCM53570_B0fmt */ 6026 /* format IFP_SINGLE_WIDE_F1_0fmt */ 6027 /* nFields */ 4, 6028 /* *fields */ soc_IFP_SINGLE_WIDE_F1_0_BCM53570_A0fmt_fields, 6029 /* bits */ 39, 6030 /* flags */ 0, 6031 }, 6032 #endif /* chips */ 6033 6034 #if defined(BCM_56142_A0) 6035 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_0_BCM56142_A0fmt */ 6036 /* format IFP_SINGLE_WIDE_F1_0fmt */ 6037 /* nFields */ 3, 6038 /* *fields */ soc_IFP_SINGLE_WIDE_F1_0_BCM56634_A0fmt_fields, 6039 /* bits */ 37, 6040 /* flags */ 0, 6041 }, 6042 #endif /* chips */ 6043 6044 #if defined(BCM_56150_A0) 6045 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_0_BCM56150_A0fmt */ 6046 /* format IFP_SINGLE_WIDE_F1_0fmt */ 6047 /* nFields */ 3, 6048 /* *fields */ soc_IFP_SINGLE_WIDE_F1_0_BCM56150_A0fmt_fields, 6049 /* bits */ 37, 6050 /* flags */ 0, 6051 }, 6052 #endif /* chips */ 6053 6054 #if defined(BCM_56160_A0) 6055 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_0_BCM56160_A0fmt */ 6056 /* format IFP_SINGLE_WIDE_F1_0fmt */ 6057 /* nFields */ 3, 6058 /* *fields */ soc_IFP_SINGLE_WIDE_F1_0_BCM53400_A0fmt_fields, 6059 /* bits */ 37, 6060 /* flags */ 0, 6061 }, 6062 #endif /* chips */ 6063 6064 #if defined(BCM_56260_A0) 6065 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_0_BCM56260_A0fmt */ 6066 /* format IFP_SINGLE_WIDE_F1_0fmt */ 6067 /* nFields */ 4, 6068 /* *fields */ soc_IFP_SINGLE_WIDE_F1_0_BCM56260_A0fmt_fields, 6069 /* bits */ 40, 6070 /* flags */ 0, 6071 }, 6072 #endif /* chips */ 6073 6074 #if defined(BCM_56260_B0) 6075 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_0_BCM56260_B0fmt */ 6076 /* format IFP_SINGLE_WIDE_F1_0fmt */ 6077 /* nFields */ 4, 6078 /* *fields */ soc_IFP_SINGLE_WIDE_F1_0_BCM56260_A0fmt_fields, 6079 /* bits */ 40, 6080 /* flags */ 0, 6081 }, 6082 #endif /* chips */ 6083 6084 #if defined(BCM_56270_A0) 6085 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_0_BCM56270_A0fmt */ 6086 /* format IFP_SINGLE_WIDE_F1_0fmt */ 6087 /* nFields */ 4, 6088 /* *fields */ soc_IFP_SINGLE_WIDE_F1_0_BCM56260_A0fmt_fields, 6089 /* bits */ 40, 6090 /* flags */ 0, 6091 }, 6092 #endif /* chips */ 6093 6094 #if defined(BCM_56334_A0) 6095 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_0_BCM56334_A0fmt */ 6096 /* format IFP_SINGLE_WIDE_F1_0fmt */ 6097 /* nFields */ 3, 6098 /* *fields */ soc_IFP_SINGLE_WIDE_F1_0_BCM56634_A0fmt_fields, 6099 /* bits */ 37, 6100 /* flags */ 0, 6101 }, 6102 #endif /* chips */ 6103 6104 #if defined(BCM_56334_B0) 6105 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_0_BCM56334_B0fmt */ 6106 /* format IFP_SINGLE_WIDE_F1_0fmt */ 6107 /* nFields */ 3, 6108 /* *fields */ soc_IFP_SINGLE_WIDE_F1_0_BCM56634_A0fmt_fields, 6109 /* bits */ 37, 6110 /* flags */ 0, 6111 }, 6112 #endif /* chips */ 6113 6114 #if defined(BCM_56340_A0) 6115 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_0_BCM56340_A0fmt */ 6116 /* format IFP_SINGLE_WIDE_F1_0fmt */ 6117 /* nFields */ 4, 6118 /* *fields */ soc_IFP_SINGLE_WIDE_F1_0_BCM56340_A0fmt_fields, 6119 /* bits */ 49, 6120 /* flags */ 0, 6121 }, 6122 #endif /* chips */ 6123 6124 #if defined(BCM_56440_A0) 6125 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_0_BCM56440_A0fmt */ 6126 /* format IFP_SINGLE_WIDE_F1_0fmt */ 6127 /* nFields */ 4, 6128 /* *fields */ soc_IFP_SINGLE_WIDE_F1_0_BCM56840_A0fmt_fields, 6129 /* bits */ 39, 6130 /* flags */ 0, 6131 }, 6132 #endif /* chips */ 6133 6134 #if defined(BCM_56440_B0) 6135 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_0_BCM56440_B0fmt */ 6136 /* format IFP_SINGLE_WIDE_F1_0fmt */ 6137 /* nFields */ 4, 6138 /* *fields */ soc_IFP_SINGLE_WIDE_F1_0_BCM56840_A0fmt_fields, 6139 /* bits */ 39, 6140 /* flags */ 0, 6141 }, 6142 #endif /* chips */ 6143 6144 #if defined(BCM_56450_A0) 6145 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_0_BCM56450_A0fmt */ 6146 /* format IFP_SINGLE_WIDE_F1_0fmt */ 6147 /* nFields */ 4, 6148 /* *fields */ soc_IFP_SINGLE_WIDE_F1_0_BCM56450_A0fmt_fields, 6149 /* bits */ 40, 6150 /* flags */ 0, 6151 }, 6152 #endif /* chips */ 6153 6154 #if defined(BCM_56450_B0) 6155 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_0_BCM56450_B0fmt */ 6156 /* format IFP_SINGLE_WIDE_F1_0fmt */ 6157 /* nFields */ 4, 6158 /* *fields */ soc_IFP_SINGLE_WIDE_F1_0_BCM56450_A0fmt_fields, 6159 /* bits */ 40, 6160 /* flags */ 0, 6161 }, 6162 #endif /* chips */ 6163 6164 #if defined(BCM_56450_B1) 6165 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_0_BCM56450_B1fmt */ 6166 /* format IFP_SINGLE_WIDE_F1_0fmt */ 6167 /* nFields */ 4, 6168 /* *fields */ soc_IFP_SINGLE_WIDE_F1_0_BCM56450_A0fmt_fields, 6169 /* bits */ 40, 6170 /* flags */ 0, 6171 }, 6172 #endif /* chips */ 6173 6174 #if defined(BCM_56524_A0) 6175 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_0_BCM56524_A0fmt */ 6176 /* format IFP_SINGLE_WIDE_F1_0fmt */ 6177 /* nFields */ 3, 6178 /* *fields */ soc_IFP_SINGLE_WIDE_F1_0_BCM56634_A0fmt_fields, 6179 /* bits */ 37, 6180 /* flags */ 0, 6181 }, 6182 #endif /* chips */ 6183 6184 #if defined(BCM_56524_B0) 6185 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_0_BCM56524_B0fmt */ 6186 /* format IFP_SINGLE_WIDE_F1_0fmt */ 6187 /* nFields */ 3, 6188 /* *fields */ soc_IFP_SINGLE_WIDE_F1_0_BCM56634_A0fmt_fields, 6189 /* bits */ 37, 6190 /* flags */ 0, 6191 }, 6192 #endif /* chips */ 6193 6194 #if defined(BCM_56560_A0) 6195 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_0_BCM56560_A0fmt */ 6196 /* format IFP_SINGLE_WIDE_F1_0fmt */ 6197 /* nFields */ 5, 6198 /* *fields */ soc_IFP_SINGLE_WIDE_F1_0_BCM56560_A0fmt_fields, 6199 /* bits */ 50, 6200 /* flags */ 0, 6201 }, 6202 #endif /* chips */ 6203 6204 #if defined(BCM_56560_B0) 6205 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_0_BCM56560_B0fmt */ 6206 /* format IFP_SINGLE_WIDE_F1_0fmt */ 6207 /* nFields */ 5, 6208 /* *fields */ soc_IFP_SINGLE_WIDE_F1_0_BCM56560_A0fmt_fields, 6209 /* bits */ 50, 6210 /* flags */ 0, 6211 }, 6212 #endif /* chips */ 6213 6214 #if defined(BCM_56634_A0) 6215 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_0_BCM56634_A0fmt */ 6216 /* format IFP_SINGLE_WIDE_F1_0fmt */ 6217 /* nFields */ 3, 6218 /* *fields */ soc_IFP_SINGLE_WIDE_F1_0_BCM56634_A0fmt_fields, 6219 /* bits */ 37, 6220 /* flags */ 0, 6221 }, 6222 #endif /* chips */ 6223 6224 #if defined(BCM_56634_B0) 6225 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_0_BCM56634_B0fmt */ 6226 /* format IFP_SINGLE_WIDE_F1_0fmt */ 6227 /* nFields */ 3, 6228 /* *fields */ soc_IFP_SINGLE_WIDE_F1_0_BCM56634_A0fmt_fields, 6229 /* bits */ 37, 6230 /* flags */ 0, 6231 }, 6232 #endif /* chips */ 6233 6234 #if defined(BCM_56640_A0) 6235 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_0_BCM56640_A0fmt */ 6236 /* format IFP_SINGLE_WIDE_F1_0fmt */ 6237 /* nFields */ 4, 6238 /* *fields */ soc_IFP_SINGLE_WIDE_F1_0_BCM56640_A0fmt_fields, 6239 /* bits */ 49, 6240 /* flags */ 0, 6241 }, 6242 #endif /* chips */ 6243 6244 #if defined(BCM_56670_A0) 6245 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_0_BCM56670_A0fmt */ 6246 /* format IFP_SINGLE_WIDE_F1_0fmt */ 6247 /* nFields */ 5, 6248 /* *fields */ soc_IFP_SINGLE_WIDE_F1_0_BCM56560_A0fmt_fields, 6249 /* bits */ 50, 6250 /* flags */ 0, 6251 }, 6252 #endif /* chips */ 6253 6254 #if defined(BCM_56670_B0) 6255 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_0_BCM56670_B0fmt */ 6256 /* format IFP_SINGLE_WIDE_F1_0fmt */ 6257 /* nFields */ 5, 6258 /* *fields */ soc_IFP_SINGLE_WIDE_F1_0_BCM56560_A0fmt_fields, 6259 /* bits */ 50, 6260 /* flags */ 0, 6261 }, 6262 #endif /* chips */ 6263 6264 #if defined(BCM_56680_B0) 6265 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_0_BCM56680_B0fmt */ 6266 /* format IFP_SINGLE_WIDE_F1_0fmt */ 6267 /* nFields */ 3, 6268 /* *fields */ soc_IFP_SINGLE_WIDE_F1_0fmt_fields, 6269 /* bits */ 34, 6270 /* flags */ 0, 6271 }, 6272 #endif /* chips */ 6273 6274 #if defined(BCM_56685_A0) 6275 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_0_BCM56685_A0fmt */ 6276 /* format IFP_SINGLE_WIDE_F1_0fmt */ 6277 /* nFields */ 3, 6278 /* *fields */ soc_IFP_SINGLE_WIDE_F1_0_BCM56634_A0fmt_fields, 6279 /* bits */ 37, 6280 /* flags */ 0, 6281 }, 6282 #endif /* chips */ 6283 6284 #if defined(BCM_56685_B0) 6285 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_0_BCM56685_B0fmt */ 6286 /* format IFP_SINGLE_WIDE_F1_0fmt */ 6287 /* nFields */ 3, 6288 /* *fields */ soc_IFP_SINGLE_WIDE_F1_0_BCM56634_A0fmt_fields, 6289 /* bits */ 37, 6290 /* flags */ 0, 6291 }, 6292 #endif /* chips */ 6293 6294 #if defined(BCM_56840_A0) 6295 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_0_BCM56840_A0fmt */ 6296 /* format IFP_SINGLE_WIDE_F1_0fmt */ 6297 /* nFields */ 4, 6298 /* *fields */ soc_IFP_SINGLE_WIDE_F1_0_BCM56840_A0fmt_fields, 6299 /* bits */ 39, 6300 /* flags */ 0, 6301 }, 6302 #endif /* chips */ 6303 6304 #if defined(BCM_56840_B0) 6305 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_0_BCM56840_B0fmt */ 6306 /* format IFP_SINGLE_WIDE_F1_0fmt */ 6307 /* nFields */ 4, 6308 /* *fields */ soc_IFP_SINGLE_WIDE_F1_0_BCM56840_A0fmt_fields, 6309 /* bits */ 39, 6310 /* flags */ 0, 6311 }, 6312 #endif /* chips */ 6313 6314 #if defined(BCM_56850_A0) 6315 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_0_BCM56850_A0fmt */ 6316 /* format IFP_SINGLE_WIDE_F1_0fmt */ 6317 /* nFields */ 4, 6318 /* *fields */ soc_IFP_SINGLE_WIDE_F1_0_BCM56850_A0fmt_fields, 6319 /* bits */ 49, 6320 /* flags */ 0, 6321 }, 6322 #endif /* chips */ 6323 6324 #if defined(BCM_56860_A0) 6325 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_0_BCM56860_A0fmt */ 6326 /* format IFP_SINGLE_WIDE_F1_0fmt */ 6327 /* nFields */ 5, 6328 /* *fields */ soc_IFP_SINGLE_WIDE_F1_0_BCM56860_A0fmt_fields, 6329 /* bits */ 50, 6330 /* flags */ 0, 6331 }, 6332 #endif /* chips */ 6333 6334 #if defined(BCM_53400_A0) 6335 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_10_BCM53400_A0fmt */ 6336 /* format IFP_SINGLE_WIDE_F1_10fmt */ 6337 /* nFields */ 4, 6338 /* *fields */ soc_IFP_SINGLE_WIDE_F1_10_BCM53400_A0fmt_fields, 6339 /* bits */ 37, 6340 /* flags */ 0, 6341 }, 6342 #endif /* chips */ 6343 6344 #if defined(BCM_53540_A0) 6345 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_10_BCM53540_A0fmt */ 6346 /* format IFP_SINGLE_WIDE_F1_10fmt */ 6347 /* nFields */ 4, 6348 /* *fields */ soc_IFP_SINGLE_WIDE_F1_10_BCM56160_A0fmt_fields, 6349 /* bits */ 37, 6350 /* flags */ 0, 6351 }, 6352 #endif /* chips */ 6353 6354 #if defined(BCM_53570_A0) 6355 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_10_BCM53570_A0fmt */ 6356 /* format IFP_SINGLE_WIDE_F1_10fmt */ 6357 /* nFields */ 4, 6358 /* *fields */ soc_IFP_SINGLE_WIDE_F1_10_BCM53570_A0fmt_fields, 6359 /* bits */ 39, 6360 /* flags */ 0, 6361 }, 6362 #endif /* chips */ 6363 6364 #if defined(BCM_53570_B0) 6365 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_10_BCM53570_B0fmt */ 6366 /* format IFP_SINGLE_WIDE_F1_10fmt */ 6367 /* nFields */ 4, 6368 /* *fields */ soc_IFP_SINGLE_WIDE_F1_10_BCM53570_A0fmt_fields, 6369 /* bits */ 39, 6370 /* flags */ 0, 6371 }, 6372 #endif /* chips */ 6373 6374 #if defined(BCM_56142_A0) 6375 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_10_BCM56142_A0fmt */ 6376 /* format IFP_SINGLE_WIDE_F1_10fmt */ 6377 /* nFields */ 4, 6378 /* *fields */ soc_IFP_SINGLE_WIDE_F1_10fmt_fields, 6379 /* bits */ 37, 6380 /* flags */ 0, 6381 }, 6382 #endif /* chips */ 6383 6384 #if defined(BCM_56150_A0) 6385 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_10_BCM56150_A0fmt */ 6386 /* format IFP_SINGLE_WIDE_F1_10fmt */ 6387 /* nFields */ 4, 6388 /* *fields */ soc_IFP_SINGLE_WIDE_F1_10_BCM56150_A0fmt_fields, 6389 /* bits */ 37, 6390 /* flags */ 0, 6391 }, 6392 #endif /* chips */ 6393 6394 #if defined(BCM_56160_A0) 6395 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_10_BCM56160_A0fmt */ 6396 /* format IFP_SINGLE_WIDE_F1_10fmt */ 6397 /* nFields */ 4, 6398 /* *fields */ soc_IFP_SINGLE_WIDE_F1_10_BCM56160_A0fmt_fields, 6399 /* bits */ 37, 6400 /* flags */ 0, 6401 }, 6402 #endif /* chips */ 6403 6404 #if defined(BCM_56260_A0) 6405 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_10_BCM56260_A0fmt */ 6406 /* format IFP_SINGLE_WIDE_F1_10fmt */ 6407 /* nFields */ 4, 6408 /* *fields */ soc_IFP_SINGLE_WIDE_F1_10_BCM56260_A0fmt_fields, 6409 /* bits */ 40, 6410 /* flags */ 0, 6411 }, 6412 #endif /* chips */ 6413 6414 #if defined(BCM_56260_B0) 6415 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_10_BCM56260_B0fmt */ 6416 /* format IFP_SINGLE_WIDE_F1_10fmt */ 6417 /* nFields */ 4, 6418 /* *fields */ soc_IFP_SINGLE_WIDE_F1_10_BCM56260_A0fmt_fields, 6419 /* bits */ 40, 6420 /* flags */ 0, 6421 }, 6422 #endif /* chips */ 6423 6424 #if defined(BCM_56270_A0) 6425 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_10_BCM56270_A0fmt */ 6426 /* format IFP_SINGLE_WIDE_F1_10fmt */ 6427 /* nFields */ 4, 6428 /* *fields */ soc_IFP_SINGLE_WIDE_F1_10_BCM56260_A0fmt_fields, 6429 /* bits */ 40, 6430 /* flags */ 0, 6431 }, 6432 #endif /* chips */ 6433 6434 #if defined(BCM_56334_B0) 6435 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_10_BCM56334_B0fmt */ 6436 /* format IFP_SINGLE_WIDE_F1_10fmt */ 6437 /* nFields */ 4, 6438 /* *fields */ soc_IFP_SINGLE_WIDE_F1_10fmt_fields, 6439 /* bits */ 37, 6440 /* flags */ 0, 6441 }, 6442 #endif /* chips */ 6443 6444 #if defined(BCM_56340_A0) 6445 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_10_BCM56340_A0fmt */ 6446 /* format IFP_SINGLE_WIDE_F1_10fmt */ 6447 /* nFields */ 4, 6448 /* *fields */ soc_IFP_SINGLE_WIDE_F1_10_BCM56640_A0fmt_fields, 6449 /* bits */ 49, 6450 /* flags */ 0, 6451 }, 6452 #endif /* chips */ 6453 6454 #if defined(BCM_56440_A0) 6455 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_10_BCM56440_A0fmt */ 6456 /* format IFP_SINGLE_WIDE_F1_10fmt */ 6457 /* nFields */ 4, 6458 /* *fields */ soc_IFP_SINGLE_WIDE_F1_10_BCM56840_A0fmt_fields, 6459 /* bits */ 39, 6460 /* flags */ 0, 6461 }, 6462 #endif /* chips */ 6463 6464 #if defined(BCM_56440_B0) 6465 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_10_BCM56440_B0fmt */ 6466 /* format IFP_SINGLE_WIDE_F1_10fmt */ 6467 /* nFields */ 4, 6468 /* *fields */ soc_IFP_SINGLE_WIDE_F1_10_BCM56840_A0fmt_fields, 6469 /* bits */ 39, 6470 /* flags */ 0, 6471 }, 6472 #endif /* chips */ 6473 6474 #if defined(BCM_56450_A0) 6475 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_10_BCM56450_A0fmt */ 6476 /* format IFP_SINGLE_WIDE_F1_10fmt */ 6477 /* nFields */ 4, 6478 /* *fields */ soc_IFP_SINGLE_WIDE_F1_10_BCM56450_A0fmt_fields, 6479 /* bits */ 40, 6480 /* flags */ 0, 6481 }, 6482 #endif /* chips */ 6483 6484 #if defined(BCM_56450_B0) 6485 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_10_BCM56450_B0fmt */ 6486 /* format IFP_SINGLE_WIDE_F1_10fmt */ 6487 /* nFields */ 4, 6488 /* *fields */ soc_IFP_SINGLE_WIDE_F1_10_BCM56450_A0fmt_fields, 6489 /* bits */ 40, 6490 /* flags */ 0, 6491 }, 6492 #endif /* chips */ 6493 6494 #if defined(BCM_56450_B1) 6495 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_10_BCM56450_B1fmt */ 6496 /* format IFP_SINGLE_WIDE_F1_10fmt */ 6497 /* nFields */ 4, 6498 /* *fields */ soc_IFP_SINGLE_WIDE_F1_10_BCM56450_A0fmt_fields, 6499 /* bits */ 40, 6500 /* flags */ 0, 6501 }, 6502 #endif /* chips */ 6503 6504 #if defined(BCM_56524_B0) 6505 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_10_BCM56524_B0fmt */ 6506 /* format IFP_SINGLE_WIDE_F1_10fmt */ 6507 /* nFields */ 4, 6508 /* *fields */ soc_IFP_SINGLE_WIDE_F1_10fmt_fields, 6509 /* bits */ 37, 6510 /* flags */ 0, 6511 }, 6512 #endif /* chips */ 6513 6514 #if defined(BCM_56560_A0) 6515 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_10_BCM56560_A0fmt */ 6516 /* format IFP_SINGLE_WIDE_F1_10fmt */ 6517 /* nFields */ 4, 6518 /* *fields */ soc_IFP_SINGLE_WIDE_F1_10_BCM56560_A0fmt_fields, 6519 /* bits */ 50, 6520 /* flags */ 0, 6521 }, 6522 #endif /* chips */ 6523 6524 #if defined(BCM_56560_B0) 6525 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_10_BCM56560_B0fmt */ 6526 /* format IFP_SINGLE_WIDE_F1_10fmt */ 6527 /* nFields */ 4, 6528 /* *fields */ soc_IFP_SINGLE_WIDE_F1_10_BCM56560_A0fmt_fields, 6529 /* bits */ 50, 6530 /* flags */ 0, 6531 }, 6532 #endif /* chips */ 6533 6534 #if defined(BCM_56640_A0) 6535 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_10_BCM56640_A0fmt */ 6536 /* format IFP_SINGLE_WIDE_F1_10fmt */ 6537 /* nFields */ 4, 6538 /* *fields */ soc_IFP_SINGLE_WIDE_F1_10_BCM56640_A0fmt_fields, 6539 /* bits */ 49, 6540 /* flags */ 0, 6541 }, 6542 #endif /* chips */ 6543 6544 #if defined(BCM_56670_A0) 6545 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_10_BCM56670_A0fmt */ 6546 /* format IFP_SINGLE_WIDE_F1_10fmt */ 6547 /* nFields */ 4, 6548 /* *fields */ soc_IFP_SINGLE_WIDE_F1_10_BCM56560_A0fmt_fields, 6549 /* bits */ 50, 6550 /* flags */ 0, 6551 }, 6552 #endif /* chips */ 6553 6554 #if defined(BCM_56670_B0) 6555 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_10_BCM56670_B0fmt */ 6556 /* format IFP_SINGLE_WIDE_F1_10fmt */ 6557 /* nFields */ 4, 6558 /* *fields */ soc_IFP_SINGLE_WIDE_F1_10_BCM56560_A0fmt_fields, 6559 /* bits */ 50, 6560 /* flags */ 0, 6561 }, 6562 #endif /* chips */ 6563 6564 #if defined(BCM_56685_B0) 6565 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_10_BCM56685_B0fmt */ 6566 /* format IFP_SINGLE_WIDE_F1_10fmt */ 6567 /* nFields */ 4, 6568 /* *fields */ soc_IFP_SINGLE_WIDE_F1_10fmt_fields, 6569 /* bits */ 37, 6570 /* flags */ 0, 6571 }, 6572 #endif /* chips */ 6573 6574 #if defined(BCM_56840_A0) 6575 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_10_BCM56840_A0fmt */ 6576 /* format IFP_SINGLE_WIDE_F1_10fmt */ 6577 /* nFields */ 4, 6578 /* *fields */ soc_IFP_SINGLE_WIDE_F1_10_BCM56840_A0fmt_fields, 6579 /* bits */ 39, 6580 /* flags */ 0, 6581 }, 6582 #endif /* chips */ 6583 6584 #if defined(BCM_56840_B0) 6585 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_10_BCM56840_B0fmt */ 6586 /* format IFP_SINGLE_WIDE_F1_10fmt */ 6587 /* nFields */ 4, 6588 /* *fields */ soc_IFP_SINGLE_WIDE_F1_10_BCM56840_A0fmt_fields, 6589 /* bits */ 39, 6590 /* flags */ 0, 6591 }, 6592 #endif /* chips */ 6593 6594 #if defined(BCM_56850_A0) 6595 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_10_BCM56850_A0fmt */ 6596 /* format IFP_SINGLE_WIDE_F1_10fmt */ 6597 /* nFields */ 4, 6598 /* *fields */ soc_IFP_SINGLE_WIDE_F1_10_BCM56640_A0fmt_fields, 6599 /* bits */ 49, 6600 /* flags */ 0, 6601 }, 6602 #endif /* chips */ 6603 6604 #if defined(BCM_56860_A0) 6605 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_10_BCM56860_A0fmt */ 6606 /* format IFP_SINGLE_WIDE_F1_10fmt */ 6607 /* nFields */ 4, 6608 /* *fields */ soc_IFP_SINGLE_WIDE_F1_10_BCM56860_A0fmt_fields, 6609 /* bits */ 50, 6610 /* flags */ 0, 6611 }, 6612 #endif /* chips */ 6613 6614 #if defined(BCM_53400_A0) 6615 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_11_BCM53400_A0fmt */ 6616 /* format IFP_SINGLE_WIDE_F1_11fmt */ 6617 /* nFields */ 4, 6618 /* *fields */ soc_IFP_SINGLE_WIDE_F1_11_BCM53400_A0fmt_fields, 6619 /* bits */ 37, 6620 /* flags */ 0, 6621 }, 6622 #endif /* chips */ 6623 6624 #if defined(BCM_53540_A0) 6625 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_11_BCM53540_A0fmt */ 6626 /* format IFP_SINGLE_WIDE_F1_11fmt */ 6627 /* nFields */ 4, 6628 /* *fields */ soc_IFP_SINGLE_WIDE_F1_11_BCM56160_A0fmt_fields, 6629 /* bits */ 37, 6630 /* flags */ 0, 6631 }, 6632 #endif /* chips */ 6633 6634 #if defined(BCM_53570_A0) 6635 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_11_BCM53570_A0fmt */ 6636 /* format IFP_SINGLE_WIDE_F1_11fmt */ 6637 /* nFields */ 4, 6638 /* *fields */ soc_IFP_SINGLE_WIDE_F1_11_BCM53570_A0fmt_fields, 6639 /* bits */ 39, 6640 /* flags */ 0, 6641 }, 6642 #endif /* chips */ 6643 6644 #if defined(BCM_53570_B0) 6645 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_11_BCM53570_B0fmt */ 6646 /* format IFP_SINGLE_WIDE_F1_11fmt */ 6647 /* nFields */ 4, 6648 /* *fields */ soc_IFP_SINGLE_WIDE_F1_11_BCM53570_A0fmt_fields, 6649 /* bits */ 39, 6650 /* flags */ 0, 6651 }, 6652 #endif /* chips */ 6653 6654 #if defined(BCM_56142_A0) 6655 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_11_BCM56142_A0fmt */ 6656 /* format IFP_SINGLE_WIDE_F1_11fmt */ 6657 /* nFields */ 4, 6658 /* *fields */ soc_IFP_SINGLE_WIDE_F1_11fmt_fields, 6659 /* bits */ 37, 6660 /* flags */ 0, 6661 }, 6662 #endif /* chips */ 6663 6664 #if defined(BCM_56150_A0) 6665 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_11_BCM56150_A0fmt */ 6666 /* format IFP_SINGLE_WIDE_F1_11fmt */ 6667 /* nFields */ 4, 6668 /* *fields */ soc_IFP_SINGLE_WIDE_F1_11_BCM56150_A0fmt_fields, 6669 /* bits */ 37, 6670 /* flags */ 0, 6671 }, 6672 #endif /* chips */ 6673 6674 #if defined(BCM_56160_A0) 6675 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_11_BCM56160_A0fmt */ 6676 /* format IFP_SINGLE_WIDE_F1_11fmt */ 6677 /* nFields */ 4, 6678 /* *fields */ soc_IFP_SINGLE_WIDE_F1_11_BCM56160_A0fmt_fields, 6679 /* bits */ 37, 6680 /* flags */ 0, 6681 }, 6682 #endif /* chips */ 6683 6684 #if defined(BCM_56260_A0) 6685 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_11_BCM56260_A0fmt */ 6686 /* format IFP_SINGLE_WIDE_F1_11fmt */ 6687 /* nFields */ 6, 6688 /* *fields */ soc_IFP_SINGLE_WIDE_F1_11_BCM56260_A0fmt_fields, 6689 /* bits */ 40, 6690 /* flags */ 0, 6691 }, 6692 #endif /* chips */ 6693 6694 #if defined(BCM_56260_B0) 6695 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_11_BCM56260_B0fmt */ 6696 /* format IFP_SINGLE_WIDE_F1_11fmt */ 6697 /* nFields */ 6, 6698 /* *fields */ soc_IFP_SINGLE_WIDE_F1_11_BCM56260_A0fmt_fields, 6699 /* bits */ 40, 6700 /* flags */ 0, 6701 }, 6702 #endif /* chips */ 6703 6704 #if defined(BCM_56270_A0) 6705 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_11_BCM56270_A0fmt */ 6706 /* format IFP_SINGLE_WIDE_F1_11fmt */ 6707 /* nFields */ 6, 6708 /* *fields */ soc_IFP_SINGLE_WIDE_F1_11_BCM56260_A0fmt_fields, 6709 /* bits */ 40, 6710 /* flags */ 0, 6711 }, 6712 #endif /* chips */ 6713 6714 #if defined(BCM_56334_A0) 6715 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_11_BCM56334_A0fmt */ 6716 /* format IFP_SINGLE_WIDE_F1_11fmt */ 6717 /* nFields */ 4, 6718 /* *fields */ soc_IFP_SINGLE_WIDE_F1_11fmt_fields, 6719 /* bits */ 37, 6720 /* flags */ 0, 6721 }, 6722 #endif /* chips */ 6723 6724 #if defined(BCM_56334_B0) 6725 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_11_BCM56334_B0fmt */ 6726 /* format IFP_SINGLE_WIDE_F1_11fmt */ 6727 /* nFields */ 4, 6728 /* *fields */ soc_IFP_SINGLE_WIDE_F1_11fmt_fields, 6729 /* bits */ 37, 6730 /* flags */ 0, 6731 }, 6732 #endif /* chips */ 6733 6734 #if defined(BCM_56340_A0) 6735 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_11_BCM56340_A0fmt */ 6736 /* format IFP_SINGLE_WIDE_F1_11fmt */ 6737 /* nFields */ 6, 6738 /* *fields */ soc_IFP_SINGLE_WIDE_F1_11_BCM56340_A0fmt_fields, 6739 /* bits */ 49, 6740 /* flags */ 0, 6741 }, 6742 #endif /* chips */ 6743 6744 #if defined(BCM_56440_A0) 6745 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_11_BCM56440_A0fmt */ 6746 /* format IFP_SINGLE_WIDE_F1_11fmt */ 6747 /* nFields */ 6, 6748 /* *fields */ soc_IFP_SINGLE_WIDE_F1_11_BCM56440_A0fmt_fields, 6749 /* bits */ 39, 6750 /* flags */ 0, 6751 }, 6752 #endif /* chips */ 6753 6754 #if defined(BCM_56440_B0) 6755 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_11_BCM56440_B0fmt */ 6756 /* format IFP_SINGLE_WIDE_F1_11fmt */ 6757 /* nFields */ 6, 6758 /* *fields */ soc_IFP_SINGLE_WIDE_F1_11_BCM56440_A0fmt_fields, 6759 /* bits */ 39, 6760 /* flags */ 0, 6761 }, 6762 #endif /* chips */ 6763 6764 #if defined(BCM_56450_A0) 6765 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_11_BCM56450_A0fmt */ 6766 /* format IFP_SINGLE_WIDE_F1_11fmt */ 6767 /* nFields */ 6, 6768 /* *fields */ soc_IFP_SINGLE_WIDE_F1_11_BCM56450_A0fmt_fields, 6769 /* bits */ 40, 6770 /* flags */ 0, 6771 }, 6772 #endif /* chips */ 6773 6774 #if defined(BCM_56450_B0) 6775 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_11_BCM56450_B0fmt */ 6776 /* format IFP_SINGLE_WIDE_F1_11fmt */ 6777 /* nFields */ 6, 6778 /* *fields */ soc_IFP_SINGLE_WIDE_F1_11_BCM56450_A0fmt_fields, 6779 /* bits */ 40, 6780 /* flags */ 0, 6781 }, 6782 #endif /* chips */ 6783 6784 #if defined(BCM_56450_B1) 6785 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_11_BCM56450_B1fmt */ 6786 /* format IFP_SINGLE_WIDE_F1_11fmt */ 6787 /* nFields */ 6, 6788 /* *fields */ soc_IFP_SINGLE_WIDE_F1_11_BCM56450_A0fmt_fields, 6789 /* bits */ 40, 6790 /* flags */ 0, 6791 }, 6792 #endif /* chips */ 6793 6794 #if defined(BCM_56524_A0) 6795 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_11_BCM56524_A0fmt */ 6796 /* format IFP_SINGLE_WIDE_F1_11fmt */ 6797 /* nFields */ 4, 6798 /* *fields */ soc_IFP_SINGLE_WIDE_F1_11fmt_fields, 6799 /* bits */ 37, 6800 /* flags */ 0, 6801 }, 6802 #endif /* chips */ 6803 6804 #if defined(BCM_56524_B0) 6805 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_11_BCM56524_B0fmt */ 6806 /* format IFP_SINGLE_WIDE_F1_11fmt */ 6807 /* nFields */ 4, 6808 /* *fields */ soc_IFP_SINGLE_WIDE_F1_11fmt_fields, 6809 /* bits */ 37, 6810 /* flags */ 0, 6811 }, 6812 #endif /* chips */ 6813 6814 #if defined(BCM_56560_A0) 6815 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_11_BCM56560_A0fmt */ 6816 /* format IFP_SINGLE_WIDE_F1_11fmt */ 6817 /* nFields */ 5, 6818 /* *fields */ soc_IFP_SINGLE_WIDE_F1_11_BCM56560_A0fmt_fields, 6819 /* bits */ 50, 6820 /* flags */ 0, 6821 }, 6822 #endif /* chips */ 6823 6824 #if defined(BCM_56560_B0) 6825 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_11_BCM56560_B0fmt */ 6826 /* format IFP_SINGLE_WIDE_F1_11fmt */ 6827 /* nFields */ 5, 6828 /* *fields */ soc_IFP_SINGLE_WIDE_F1_11_BCM56560_A0fmt_fields, 6829 /* bits */ 50, 6830 /* flags */ 0, 6831 }, 6832 #endif /* chips */ 6833 6834 #if defined(BCM_56634_B0) 6835 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_11_BCM56634_B0fmt */ 6836 /* format IFP_SINGLE_WIDE_F1_11fmt */ 6837 /* nFields */ 4, 6838 /* *fields */ soc_IFP_SINGLE_WIDE_F1_11fmt_fields, 6839 /* bits */ 37, 6840 /* flags */ 0, 6841 }, 6842 #endif /* chips */ 6843 6844 #if defined(BCM_56640_A0) 6845 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_11_BCM56640_A0fmt */ 6846 /* format IFP_SINGLE_WIDE_F1_11fmt */ 6847 /* nFields */ 6, 6848 /* *fields */ soc_IFP_SINGLE_WIDE_F1_11_BCM56640_A0fmt_fields, 6849 /* bits */ 49, 6850 /* flags */ 0, 6851 }, 6852 #endif /* chips */ 6853 6854 #if defined(BCM_56670_A0) 6855 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_11_BCM56670_A0fmt */ 6856 /* format IFP_SINGLE_WIDE_F1_11fmt */ 6857 /* nFields */ 5, 6858 /* *fields */ soc_IFP_SINGLE_WIDE_F1_11_BCM56560_A0fmt_fields, 6859 /* bits */ 50, 6860 /* flags */ 0, 6861 }, 6862 #endif /* chips */ 6863 6864 #if defined(BCM_56670_B0) 6865 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_11_BCM56670_B0fmt */ 6866 /* format IFP_SINGLE_WIDE_F1_11fmt */ 6867 /* nFields */ 5, 6868 /* *fields */ soc_IFP_SINGLE_WIDE_F1_11_BCM56560_A0fmt_fields, 6869 /* bits */ 50, 6870 /* flags */ 0, 6871 }, 6872 #endif /* chips */ 6873 6874 #if defined(BCM_56685_A0) 6875 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_11_BCM56685_A0fmt */ 6876 /* format IFP_SINGLE_WIDE_F1_11fmt */ 6877 /* nFields */ 4, 6878 /* *fields */ soc_IFP_SINGLE_WIDE_F1_11fmt_fields, 6879 /* bits */ 37, 6880 /* flags */ 0, 6881 }, 6882 #endif /* chips */ 6883 6884 #if defined(BCM_56685_B0) 6885 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_11_BCM56685_B0fmt */ 6886 /* format IFP_SINGLE_WIDE_F1_11fmt */ 6887 /* nFields */ 4, 6888 /* *fields */ soc_IFP_SINGLE_WIDE_F1_11fmt_fields, 6889 /* bits */ 37, 6890 /* flags */ 0, 6891 }, 6892 #endif /* chips */ 6893 6894 #if defined(BCM_56840_A0) 6895 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_11_BCM56840_A0fmt */ 6896 /* format IFP_SINGLE_WIDE_F1_11fmt */ 6897 /* nFields */ 4, 6898 /* *fields */ soc_IFP_SINGLE_WIDE_F1_11_BCM56840_A0fmt_fields, 6899 /* bits */ 39, 6900 /* flags */ 0, 6901 }, 6902 #endif /* chips */ 6903 6904 #if defined(BCM_56840_B0) 6905 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_11_BCM56840_B0fmt */ 6906 /* format IFP_SINGLE_WIDE_F1_11fmt */ 6907 /* nFields */ 4, 6908 /* *fields */ soc_IFP_SINGLE_WIDE_F1_11_BCM56840_A0fmt_fields, 6909 /* bits */ 39, 6910 /* flags */ 0, 6911 }, 6912 #endif /* chips */ 6913 6914 #if defined(BCM_56850_A0) 6915 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_11_BCM56850_A0fmt */ 6916 /* format IFP_SINGLE_WIDE_F1_11fmt */ 6917 /* nFields */ 5, 6918 /* *fields */ soc_IFP_SINGLE_WIDE_F1_11_BCM56850_A0fmt_fields, 6919 /* bits */ 49, 6920 /* flags */ 0, 6921 }, 6922 #endif /* chips */ 6923 6924 #if defined(BCM_56860_A0) 6925 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_11_BCM56860_A0fmt */ 6926 /* format IFP_SINGLE_WIDE_F1_11fmt */ 6927 /* nFields */ 5, 6928 /* *fields */ soc_IFP_SINGLE_WIDE_F1_11_BCM56860_A0fmt_fields, 6929 /* bits */ 50, 6930 /* flags */ 0, 6931 }, 6932 #endif /* chips */ 6933 6934 #if defined(BCM_53400_A0) 6935 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_12_BCM53400_A0fmt */ 6936 /* format IFP_SINGLE_WIDE_F1_12fmt */ 6937 /* nFields */ 3, 6938 /* *fields */ soc_IFP_SINGLE_WIDE_F1_12_BCM53400_A0fmt_fields, 6939 /* bits */ 37, 6940 /* flags */ 0, 6941 }, 6942 #endif /* chips */ 6943 6944 #if defined(BCM_53540_A0) 6945 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_12_BCM53540_A0fmt */ 6946 /* format IFP_SINGLE_WIDE_F1_12fmt */ 6947 /* nFields */ 3, 6948 /* *fields */ soc_IFP_SINGLE_WIDE_F1_12_BCM53400_A0fmt_fields, 6949 /* bits */ 37, 6950 /* flags */ 0, 6951 }, 6952 #endif /* chips */ 6953 6954 #if defined(BCM_53570_A0) 6955 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_12_BCM53570_A0fmt */ 6956 /* format IFP_SINGLE_WIDE_F1_12fmt */ 6957 /* nFields */ 3, 6958 /* *fields */ soc_IFP_SINGLE_WIDE_F1_12_BCM53570_A0fmt_fields, 6959 /* bits */ 39, 6960 /* flags */ 0, 6961 }, 6962 #endif /* chips */ 6963 6964 #if defined(BCM_53570_B0) 6965 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_12_BCM53570_B0fmt */ 6966 /* format IFP_SINGLE_WIDE_F1_12fmt */ 6967 /* nFields */ 3, 6968 /* *fields */ soc_IFP_SINGLE_WIDE_F1_12_BCM53570_A0fmt_fields, 6969 /* bits */ 39, 6970 /* flags */ 0, 6971 }, 6972 #endif /* chips */ 6973 6974 #if defined(BCM_56150_A0) 6975 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_12_BCM56150_A0fmt */ 6976 /* format IFP_SINGLE_WIDE_F1_12fmt */ 6977 /* nFields */ 3, 6978 /* *fields */ soc_IFP_SINGLE_WIDE_F1_12_BCM56150_A0fmt_fields, 6979 /* bits */ 37, 6980 /* flags */ 0, 6981 }, 6982 #endif /* chips */ 6983 6984 #if defined(BCM_56160_A0) 6985 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_12_BCM56160_A0fmt */ 6986 /* format IFP_SINGLE_WIDE_F1_12fmt */ 6987 /* nFields */ 3, 6988 /* *fields */ soc_IFP_SINGLE_WIDE_F1_12_BCM53400_A0fmt_fields, 6989 /* bits */ 37, 6990 /* flags */ 0, 6991 }, 6992 #endif /* chips */ 6993 6994 #if defined(BCM_56260_A0) 6995 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_12_BCM56260_A0fmt */ 6996 /* format IFP_SINGLE_WIDE_F1_12fmt */ 6997 /* nFields */ 4, 6998 /* *fields */ soc_IFP_SINGLE_WIDE_F1_12_BCM56260_A0fmt_fields, 6999 /* bits */ 40, 7000 /* flags */ 0, 7001 }, 7002 #endif /* chips */ 7003 7004 #if defined(BCM_56260_B0) 7005 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_12_BCM56260_B0fmt */ 7006 /* format IFP_SINGLE_WIDE_F1_12fmt */ 7007 /* nFields */ 4, 7008 /* *fields */ soc_IFP_SINGLE_WIDE_F1_12_BCM56260_A0fmt_fields, 7009 /* bits */ 40, 7010 /* flags */ 0, 7011 }, 7012 #endif /* chips */ 7013 7014 #if defined(BCM_56270_A0) 7015 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_12_BCM56270_A0fmt */ 7016 /* format IFP_SINGLE_WIDE_F1_12fmt */ 7017 /* nFields */ 4, 7018 /* *fields */ soc_IFP_SINGLE_WIDE_F1_12_BCM56260_A0fmt_fields, 7019 /* bits */ 40, 7020 /* flags */ 0, 7021 }, 7022 #endif /* chips */ 7023 7024 #if defined(BCM_56334_B0) 7025 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_12_BCM56334_B0fmt */ 7026 /* format IFP_SINGLE_WIDE_F1_12fmt */ 7027 /* nFields */ 3, 7028 /* *fields */ soc_IFP_SINGLE_WIDE_F1_12fmt_fields, 7029 /* bits */ 37, 7030 /* flags */ 0, 7031 }, 7032 #endif /* chips */ 7033 7034 #if defined(BCM_56340_A0) 7035 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_12_BCM56340_A0fmt */ 7036 /* format IFP_SINGLE_WIDE_F1_12fmt */ 7037 /* nFields */ 5, 7038 /* *fields */ soc_IFP_SINGLE_WIDE_F1_12_BCM56340_A0fmt_fields, 7039 /* bits */ 49, 7040 /* flags */ 0, 7041 }, 7042 #endif /* chips */ 7043 7044 #if defined(BCM_56440_A0) 7045 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_12_BCM56440_A0fmt */ 7046 /* format IFP_SINGLE_WIDE_F1_12fmt */ 7047 /* nFields */ 4, 7048 /* *fields */ soc_IFP_SINGLE_WIDE_F1_12_BCM56840_A0fmt_fields, 7049 /* bits */ 39, 7050 /* flags */ 0, 7051 }, 7052 #endif /* chips */ 7053 7054 #if defined(BCM_56440_B0) 7055 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_12_BCM56440_B0fmt */ 7056 /* format IFP_SINGLE_WIDE_F1_12fmt */ 7057 /* nFields */ 4, 7058 /* *fields */ soc_IFP_SINGLE_WIDE_F1_12_BCM56840_A0fmt_fields, 7059 /* bits */ 39, 7060 /* flags */ 0, 7061 }, 7062 #endif /* chips */ 7063 7064 #if defined(BCM_56450_A0) 7065 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_12_BCM56450_A0fmt */ 7066 /* format IFP_SINGLE_WIDE_F1_12fmt */ 7067 /* nFields */ 4, 7068 /* *fields */ soc_IFP_SINGLE_WIDE_F1_12_BCM56450_A0fmt_fields, 7069 /* bits */ 40, 7070 /* flags */ 0, 7071 }, 7072 #endif /* chips */ 7073 7074 #if defined(BCM_56450_B0) 7075 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_12_BCM56450_B0fmt */ 7076 /* format IFP_SINGLE_WIDE_F1_12fmt */ 7077 /* nFields */ 4, 7078 /* *fields */ soc_IFP_SINGLE_WIDE_F1_12_BCM56450_A0fmt_fields, 7079 /* bits */ 40, 7080 /* flags */ 0, 7081 }, 7082 #endif /* chips */ 7083 7084 #if defined(BCM_56450_B1) 7085 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_12_BCM56450_B1fmt */ 7086 /* format IFP_SINGLE_WIDE_F1_12fmt */ 7087 /* nFields */ 4, 7088 /* *fields */ soc_IFP_SINGLE_WIDE_F1_12_BCM56450_A0fmt_fields, 7089 /* bits */ 40, 7090 /* flags */ 0, 7091 }, 7092 #endif /* chips */ 7093 7094 #if defined(BCM_56524_A0) 7095 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_12_BCM56524_A0fmt */ 7096 /* format IFP_SINGLE_WIDE_F1_12fmt */ 7097 /* nFields */ 3, 7098 /* *fields */ soc_IFP_SINGLE_WIDE_F1_12fmt_fields, 7099 /* bits */ 37, 7100 /* flags */ 0, 7101 }, 7102 #endif /* chips */ 7103 7104 #if defined(BCM_56524_B0) 7105 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_12_BCM56524_B0fmt */ 7106 /* format IFP_SINGLE_WIDE_F1_12fmt */ 7107 /* nFields */ 3, 7108 /* *fields */ soc_IFP_SINGLE_WIDE_F1_12fmt_fields, 7109 /* bits */ 37, 7110 /* flags */ 0, 7111 }, 7112 #endif /* chips */ 7113 7114 #if defined(BCM_56560_A0) 7115 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_12_BCM56560_A0fmt */ 7116 /* format IFP_SINGLE_WIDE_F1_12fmt */ 7117 /* nFields */ 5, 7118 /* *fields */ soc_IFP_SINGLE_WIDE_F1_12_BCM56560_A0fmt_fields, 7119 /* bits */ 50, 7120 /* flags */ 0, 7121 }, 7122 #endif /* chips */ 7123 7124 #if defined(BCM_56560_B0) 7125 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_12_BCM56560_B0fmt */ 7126 /* format IFP_SINGLE_WIDE_F1_12fmt */ 7127 /* nFields */ 5, 7128 /* *fields */ soc_IFP_SINGLE_WIDE_F1_12_BCM56560_A0fmt_fields, 7129 /* bits */ 50, 7130 /* flags */ 0, 7131 }, 7132 #endif /* chips */ 7133 7134 #if defined(BCM_56640_A0) 7135 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_12_BCM56640_A0fmt */ 7136 /* format IFP_SINGLE_WIDE_F1_12fmt */ 7137 /* nFields */ 5, 7138 /* *fields */ soc_IFP_SINGLE_WIDE_F1_12_BCM56640_A0fmt_fields, 7139 /* bits */ 49, 7140 /* flags */ 0, 7141 }, 7142 #endif /* chips */ 7143 7144 #if defined(BCM_56670_A0) 7145 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_12_BCM56670_A0fmt */ 7146 /* format IFP_SINGLE_WIDE_F1_12fmt */ 7147 /* nFields */ 5, 7148 /* *fields */ soc_IFP_SINGLE_WIDE_F1_12_BCM56560_A0fmt_fields, 7149 /* bits */ 50, 7150 /* flags */ 0, 7151 }, 7152 #endif /* chips */ 7153 7154 #if defined(BCM_56670_B0) 7155 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_12_BCM56670_B0fmt */ 7156 /* format IFP_SINGLE_WIDE_F1_12fmt */ 7157 /* nFields */ 5, 7158 /* *fields */ soc_IFP_SINGLE_WIDE_F1_12_BCM56560_A0fmt_fields, 7159 /* bits */ 50, 7160 /* flags */ 0, 7161 }, 7162 #endif /* chips */ 7163 7164 #if defined(BCM_56685_A0) 7165 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_12_BCM56685_A0fmt */ 7166 /* format IFP_SINGLE_WIDE_F1_12fmt */ 7167 /* nFields */ 3, 7168 /* *fields */ soc_IFP_SINGLE_WIDE_F1_12fmt_fields, 7169 /* bits */ 37, 7170 /* flags */ 0, 7171 }, 7172 #endif /* chips */ 7173 7174 #if defined(BCM_56685_B0) 7175 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_12_BCM56685_B0fmt */ 7176 /* format IFP_SINGLE_WIDE_F1_12fmt */ 7177 /* nFields */ 3, 7178 /* *fields */ soc_IFP_SINGLE_WIDE_F1_12fmt_fields, 7179 /* bits */ 37, 7180 /* flags */ 0, 7181 }, 7182 #endif /* chips */ 7183 7184 #if defined(BCM_56840_A0) 7185 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_12_BCM56840_A0fmt */ 7186 /* format IFP_SINGLE_WIDE_F1_12fmt */ 7187 /* nFields */ 4, 7188 /* *fields */ soc_IFP_SINGLE_WIDE_F1_12_BCM56840_A0fmt_fields, 7189 /* bits */ 39, 7190 /* flags */ 0, 7191 }, 7192 #endif /* chips */ 7193 7194 #if defined(BCM_56840_B0) 7195 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_12_BCM56840_B0fmt */ 7196 /* format IFP_SINGLE_WIDE_F1_12fmt */ 7197 /* nFields */ 4, 7198 /* *fields */ soc_IFP_SINGLE_WIDE_F1_12_BCM56840_A0fmt_fields, 7199 /* bits */ 39, 7200 /* flags */ 0, 7201 }, 7202 #endif /* chips */ 7203 7204 #if defined(BCM_56850_A0) 7205 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_12_BCM56850_A0fmt */ 7206 /* format IFP_SINGLE_WIDE_F1_12fmt */ 7207 /* nFields */ 5, 7208 /* *fields */ soc_IFP_SINGLE_WIDE_F1_12_BCM56640_A0fmt_fields, 7209 /* bits */ 49, 7210 /* flags */ 0, 7211 }, 7212 #endif /* chips */ 7213 7214 #if defined(BCM_56860_A0) 7215 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_12_BCM56860_A0fmt */ 7216 /* format IFP_SINGLE_WIDE_F1_12fmt */ 7217 /* nFields */ 5, 7218 /* *fields */ soc_IFP_SINGLE_WIDE_F1_12_BCM56860_A0fmt_fields, 7219 /* bits */ 50, 7220 /* flags */ 0, 7221 }, 7222 #endif /* chips */ 7223 7224 #if defined(BCM_53400_A0) 7225 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_13_BCM53400_A0fmt */ 7226 /* format IFP_SINGLE_WIDE_F1_13fmt */ 7227 /* nFields */ 3, 7228 /* *fields */ soc_IFP_SINGLE_WIDE_F1_13_BCM53400_A0fmt_fields, 7229 /* bits */ 37, 7230 /* flags */ 0, 7231 }, 7232 #endif /* chips */ 7233 7234 #if defined(BCM_53540_A0) 7235 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_13_BCM53540_A0fmt */ 7236 /* format IFP_SINGLE_WIDE_F1_13fmt */ 7237 /* nFields */ 3, 7238 /* *fields */ soc_IFP_SINGLE_WIDE_F1_13_BCM53400_A0fmt_fields, 7239 /* bits */ 37, 7240 /* flags */ 0, 7241 }, 7242 #endif /* chips */ 7243 7244 #if defined(BCM_53570_A0) 7245 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_13_BCM53570_A0fmt */ 7246 /* format IFP_SINGLE_WIDE_F1_13fmt */ 7247 /* nFields */ 3, 7248 /* *fields */ soc_IFP_SINGLE_WIDE_F1_13_BCM53570_A0fmt_fields, 7249 /* bits */ 39, 7250 /* flags */ 0, 7251 }, 7252 #endif /* chips */ 7253 7254 #if defined(BCM_53570_B0) 7255 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_13_BCM53570_B0fmt */ 7256 /* format IFP_SINGLE_WIDE_F1_13fmt */ 7257 /* nFields */ 3, 7258 /* *fields */ soc_IFP_SINGLE_WIDE_F1_13_BCM53570_A0fmt_fields, 7259 /* bits */ 39, 7260 /* flags */ 0, 7261 }, 7262 #endif /* chips */ 7263 7264 #if defined(BCM_56160_A0) 7265 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_13_BCM56160_A0fmt */ 7266 /* format IFP_SINGLE_WIDE_F1_13fmt */ 7267 /* nFields */ 3, 7268 /* *fields */ soc_IFP_SINGLE_WIDE_F1_13_BCM53400_A0fmt_fields, 7269 /* bits */ 37, 7270 /* flags */ 0, 7271 }, 7272 #endif /* chips */ 7273 7274 #if defined(BCM_56260_A0) 7275 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_13_BCM56260_A0fmt */ 7276 /* format IFP_SINGLE_WIDE_F1_13fmt */ 7277 /* nFields */ 5, 7278 /* *fields */ soc_IFP_SINGLE_WIDE_F1_13_BCM56260_A0fmt_fields, 7279 /* bits */ 40, 7280 /* flags */ 0, 7281 }, 7282 #endif /* chips */ 7283 7284 #if defined(BCM_56260_B0) 7285 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_13_BCM56260_B0fmt */ 7286 /* format IFP_SINGLE_WIDE_F1_13fmt */ 7287 /* nFields */ 5, 7288 /* *fields */ soc_IFP_SINGLE_WIDE_F1_13_BCM56260_A0fmt_fields, 7289 /* bits */ 40, 7290 /* flags */ 0, 7291 }, 7292 #endif /* chips */ 7293 7294 #if defined(BCM_56270_A0) 7295 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_13_BCM56270_A0fmt */ 7296 /* format IFP_SINGLE_WIDE_F1_13fmt */ 7297 /* nFields */ 5, 7298 /* *fields */ soc_IFP_SINGLE_WIDE_F1_13_BCM56260_A0fmt_fields, 7299 /* bits */ 40, 7300 /* flags */ 0, 7301 }, 7302 #endif /* chips */ 7303 7304 #if defined(BCM_56340_A0) 7305 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_13_BCM56340_A0fmt */ 7306 /* format IFP_SINGLE_WIDE_F1_13fmt */ 7307 /* nFields */ 9, 7308 /* *fields */ soc_IFP_SINGLE_WIDE_F1_13_BCM56640_A0fmt_fields, 7309 /* bits */ 49, 7310 /* flags */ 0, 7311 }, 7312 #endif /* chips */ 7313 7314 #if defined(BCM_56440_A0) 7315 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_13_BCM56440_A0fmt */ 7316 /* format IFP_SINGLE_WIDE_F1_13fmt */ 7317 /* nFields */ 3, 7318 /* *fields */ soc_IFP_SINGLE_WIDE_F1_13fmt_fields, 7319 /* bits */ 39, 7320 /* flags */ 0, 7321 }, 7322 #endif /* chips */ 7323 7324 #if defined(BCM_56440_B0) 7325 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_13_BCM56440_B0fmt */ 7326 /* format IFP_SINGLE_WIDE_F1_13fmt */ 7327 /* nFields */ 3, 7328 /* *fields */ soc_IFP_SINGLE_WIDE_F1_13fmt_fields, 7329 /* bits */ 39, 7330 /* flags */ 0, 7331 }, 7332 #endif /* chips */ 7333 7334 #if defined(BCM_56450_A0) 7335 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_13_BCM56450_A0fmt */ 7336 /* format IFP_SINGLE_WIDE_F1_13fmt */ 7337 /* nFields */ 5, 7338 /* *fields */ soc_IFP_SINGLE_WIDE_F1_13_BCM56450_A0fmt_fields, 7339 /* bits */ 40, 7340 /* flags */ 0, 7341 }, 7342 #endif /* chips */ 7343 7344 #if defined(BCM_56450_B0) 7345 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_13_BCM56450_B0fmt */ 7346 /* format IFP_SINGLE_WIDE_F1_13fmt */ 7347 /* nFields */ 5, 7348 /* *fields */ soc_IFP_SINGLE_WIDE_F1_13_BCM56450_A0fmt_fields, 7349 /* bits */ 40, 7350 /* flags */ 0, 7351 }, 7352 #endif /* chips */ 7353 7354 #if defined(BCM_56450_B1) 7355 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_13_BCM56450_B1fmt */ 7356 /* format IFP_SINGLE_WIDE_F1_13fmt */ 7357 /* nFields */ 5, 7358 /* *fields */ soc_IFP_SINGLE_WIDE_F1_13_BCM56450_A0fmt_fields, 7359 /* bits */ 40, 7360 /* flags */ 0, 7361 }, 7362 #endif /* chips */ 7363 7364 #if defined(BCM_56560_A0) 7365 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_13_BCM56560_A0fmt */ 7366 /* format IFP_SINGLE_WIDE_F1_13fmt */ 7367 /* nFields */ 12, 7368 /* *fields */ soc_IFP_SINGLE_WIDE_F1_13_BCM56560_A0fmt_fields, 7369 /* bits */ 50, 7370 /* flags */ 0, 7371 }, 7372 #endif /* chips */ 7373 7374 #if defined(BCM_56560_B0) 7375 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_13_BCM56560_B0fmt */ 7376 /* format IFP_SINGLE_WIDE_F1_13fmt */ 7377 /* nFields */ 12, 7378 /* *fields */ soc_IFP_SINGLE_WIDE_F1_13_BCM56560_A0fmt_fields, 7379 /* bits */ 50, 7380 /* flags */ 0, 7381 }, 7382 #endif /* chips */ 7383 7384 #if defined(BCM_56640_A0) 7385 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_13_BCM56640_A0fmt */ 7386 /* format IFP_SINGLE_WIDE_F1_13fmt */ 7387 /* nFields */ 9, 7388 /* *fields */ soc_IFP_SINGLE_WIDE_F1_13_BCM56640_A0fmt_fields, 7389 /* bits */ 49, 7390 /* flags */ 0, 7391 }, 7392 #endif /* chips */ 7393 7394 #if defined(BCM_56670_A0) 7395 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_13_BCM56670_A0fmt */ 7396 /* format IFP_SINGLE_WIDE_F1_13fmt */ 7397 /* nFields */ 12, 7398 /* *fields */ soc_IFP_SINGLE_WIDE_F1_13_BCM56560_A0fmt_fields, 7399 /* bits */ 50, 7400 /* flags */ 0, 7401 }, 7402 #endif /* chips */ 7403 7404 #if defined(BCM_56670_B0) 7405 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_13_BCM56670_B0fmt */ 7406 /* format IFP_SINGLE_WIDE_F1_13fmt */ 7407 /* nFields */ 12, 7408 /* *fields */ soc_IFP_SINGLE_WIDE_F1_13_BCM56560_A0fmt_fields, 7409 /* bits */ 50, 7410 /* flags */ 0, 7411 }, 7412 #endif /* chips */ 7413 7414 #if defined(BCM_56840_B0) 7415 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_13_BCM56840_B0fmt */ 7416 /* format IFP_SINGLE_WIDE_F1_13fmt */ 7417 /* nFields */ 3, 7418 /* *fields */ soc_IFP_SINGLE_WIDE_F1_13fmt_fields, 7419 /* bits */ 39, 7420 /* flags */ 0, 7421 }, 7422 #endif /* chips */ 7423 7424 #if defined(BCM_56850_A0) 7425 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_13_BCM56850_A0fmt */ 7426 /* format IFP_SINGLE_WIDE_F1_13fmt */ 7427 /* nFields */ 11, 7428 /* *fields */ soc_IFP_SINGLE_WIDE_F1_13_BCM56850_A0fmt_fields, 7429 /* bits */ 49, 7430 /* flags */ 0, 7431 }, 7432 #endif /* chips */ 7433 7434 #if defined(BCM_56860_A0) 7435 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_13_BCM56860_A0fmt */ 7436 /* format IFP_SINGLE_WIDE_F1_13fmt */ 7437 /* nFields */ 12, 7438 /* *fields */ soc_IFP_SINGLE_WIDE_F1_13_BCM56860_A0fmt_fields, 7439 /* bits */ 50, 7440 /* flags */ 0, 7441 }, 7442 #endif /* chips */ 7443 7444 #if defined(BCM_53570_A0) 7445 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_14_BCM53570_A0fmt */ 7446 /* format IFP_SINGLE_WIDE_F1_14fmt */ 7447 /* nFields */ 9, 7448 /* *fields */ soc_IFP_SINGLE_WIDE_F1_14_BCM53570_A0fmt_fields, 7449 /* bits */ 39, 7450 /* flags */ 0, 7451 }, 7452 #endif /* chips */ 7453 7454 #if defined(BCM_53570_B0) 7455 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_14_BCM53570_B0fmt */ 7456 /* format IFP_SINGLE_WIDE_F1_14fmt */ 7457 /* nFields */ 9, 7458 /* *fields */ soc_IFP_SINGLE_WIDE_F1_14_BCM53570_A0fmt_fields, 7459 /* bits */ 39, 7460 /* flags */ 0, 7461 }, 7462 #endif /* chips */ 7463 7464 #if defined(BCM_56560_A0) 7465 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_14_BCM56560_A0fmt */ 7466 /* format IFP_SINGLE_WIDE_F1_14fmt */ 7467 /* nFields */ 3, 7468 /* *fields */ soc_IFP_SINGLE_WIDE_F1_14_BCM56560_A0fmt_fields, 7469 /* bits */ 50, 7470 /* flags */ 0, 7471 }, 7472 #endif /* chips */ 7473 7474 #if defined(BCM_56560_B0) 7475 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_14_BCM56560_B0fmt */ 7476 /* format IFP_SINGLE_WIDE_F1_14fmt */ 7477 /* nFields */ 3, 7478 /* *fields */ soc_IFP_SINGLE_WIDE_F1_14_BCM56560_A0fmt_fields, 7479 /* bits */ 50, 7480 /* flags */ 0, 7481 }, 7482 #endif /* chips */ 7483 7484 #if defined(BCM_56670_A0) 7485 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_14_BCM56670_A0fmt */ 7486 /* format IFP_SINGLE_WIDE_F1_14fmt */ 7487 /* nFields */ 3, 7488 /* *fields */ soc_IFP_SINGLE_WIDE_F1_14_BCM56560_A0fmt_fields, 7489 /* bits */ 50, 7490 /* flags */ 0, 7491 }, 7492 #endif /* chips */ 7493 7494 #if defined(BCM_56670_B0) 7495 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_14_BCM56670_B0fmt */ 7496 /* format IFP_SINGLE_WIDE_F1_14fmt */ 7497 /* nFields */ 3, 7498 /* *fields */ soc_IFP_SINGLE_WIDE_F1_14_BCM56560_A0fmt_fields, 7499 /* bits */ 50, 7500 /* flags */ 0, 7501 }, 7502 #endif /* chips */ 7503 7504 #if defined(BCM_56860_A0) 7505 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_14_BCM56860_A0fmt */ 7506 /* format IFP_SINGLE_WIDE_F1_14fmt */ 7507 /* nFields */ 3, 7508 /* *fields */ soc_IFP_SINGLE_WIDE_F1_14_BCM56860_A0fmt_fields, 7509 /* bits */ 50, 7510 /* flags */ 0, 7511 }, 7512 #endif /* chips */ 7513 7514 #if defined(BCM_53570_A0) 7515 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_15_BCM53570_A0fmt */ 7516 /* format IFP_SINGLE_WIDE_F1_15fmt */ 7517 /* nFields */ 7, 7518 /* *fields */ soc_IFP_SINGLE_WIDE_F1_15_BCM53570_A0fmt_fields, 7519 /* bits */ 39, 7520 /* flags */ 0, 7521 }, 7522 #endif /* chips */ 7523 7524 #if defined(BCM_53570_B0) 7525 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_15_BCM53570_B0fmt */ 7526 /* format IFP_SINGLE_WIDE_F1_15fmt */ 7527 /* nFields */ 7, 7528 /* *fields */ soc_IFP_SINGLE_WIDE_F1_15_BCM53570_A0fmt_fields, 7529 /* bits */ 39, 7530 /* flags */ 0, 7531 }, 7532 #endif /* chips */ 7533 7534 #if defined(BCM_56560_A0) 7535 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_15_BCM56560_A0fmt */ 7536 /* format IFP_SINGLE_WIDE_F1_15fmt */ 7537 /* nFields */ 7, 7538 /* *fields */ soc_IFP_SINGLE_WIDE_F1_15_BCM56560_A0fmt_fields, 7539 /* bits */ 50, 7540 /* flags */ 0, 7541 }, 7542 #endif /* chips */ 7543 7544 #if defined(BCM_56560_B0) 7545 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_15_BCM56560_B0fmt */ 7546 /* format IFP_SINGLE_WIDE_F1_15fmt */ 7547 /* nFields */ 7, 7548 /* *fields */ soc_IFP_SINGLE_WIDE_F1_15_BCM56560_A0fmt_fields, 7549 /* bits */ 50, 7550 /* flags */ 0, 7551 }, 7552 #endif /* chips */ 7553 7554 #if defined(BCM_56670_A0) 7555 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_15_BCM56670_A0fmt */ 7556 /* format IFP_SINGLE_WIDE_F1_15fmt */ 7557 /* nFields */ 7, 7558 /* *fields */ soc_IFP_SINGLE_WIDE_F1_15_BCM56560_A0fmt_fields, 7559 /* bits */ 50, 7560 /* flags */ 0, 7561 }, 7562 #endif /* chips */ 7563 7564 #if defined(BCM_56670_B0) 7565 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_15_BCM56670_B0fmt */ 7566 /* format IFP_SINGLE_WIDE_F1_15fmt */ 7567 /* nFields */ 7, 7568 /* *fields */ soc_IFP_SINGLE_WIDE_F1_15_BCM56560_A0fmt_fields, 7569 /* bits */ 50, 7570 /* flags */ 0, 7571 }, 7572 #endif /* chips */ 7573 7574 #if defined(BCM_56860_A0) 7575 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_15_BCM56860_A0fmt */ 7576 /* format IFP_SINGLE_WIDE_F1_15fmt */ 7577 /* nFields */ 9, 7578 /* *fields */ soc_IFP_SINGLE_WIDE_F1_15_BCM56860_A0fmt_fields, 7579 /* bits */ 50, 7580 /* flags */ 0, 7581 }, 7582 #endif /* chips */ 7583 7584 #if defined(BCM_56560_A0) 7585 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_16_BCM56560_A0fmt */ 7586 /* format IFP_SINGLE_WIDE_F1_16fmt */ 7587 /* nFields */ 13, 7588 /* *fields */ soc_IFP_SINGLE_WIDE_F1_16_BCM56560_A0fmt_fields, 7589 /* bits */ 50, 7590 /* flags */ 0, 7591 }, 7592 #endif /* chips */ 7593 7594 #if defined(BCM_56560_B0) 7595 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_16_BCM56560_B0fmt */ 7596 /* format IFP_SINGLE_WIDE_F1_16fmt */ 7597 /* nFields */ 13, 7598 /* *fields */ soc_IFP_SINGLE_WIDE_F1_16_BCM56560_A0fmt_fields, 7599 /* bits */ 50, 7600 /* flags */ 0, 7601 }, 7602 #endif /* chips */ 7603 7604 #if defined(BCM_56670_A0) 7605 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_16_BCM56670_A0fmt */ 7606 /* format IFP_SINGLE_WIDE_F1_16fmt */ 7607 /* nFields */ 13, 7608 /* *fields */ soc_IFP_SINGLE_WIDE_F1_16_BCM56560_A0fmt_fields, 7609 /* bits */ 50, 7610 /* flags */ 0, 7611 }, 7612 #endif /* chips */ 7613 7614 #if defined(BCM_56670_B0) 7615 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_16_BCM56670_B0fmt */ 7616 /* format IFP_SINGLE_WIDE_F1_16fmt */ 7617 /* nFields */ 13, 7618 /* *fields */ soc_IFP_SINGLE_WIDE_F1_16_BCM56560_A0fmt_fields, 7619 /* bits */ 50, 7620 /* flags */ 0, 7621 }, 7622 #endif /* chips */ 7623 7624 #if defined(BCM_56860_A0) 7625 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_16_BCM56860_A0fmt */ 7626 /* format IFP_SINGLE_WIDE_F1_16fmt */ 7627 /* nFields */ 13, 7628 /* *fields */ soc_IFP_SINGLE_WIDE_F1_16_BCM56860_A0fmt_fields, 7629 /* bits */ 50, 7630 /* flags */ 0, 7631 }, 7632 #endif /* chips */ 7633 7634 #if defined(BCM_53400_A0) 7635 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_1_BCM53400_A0fmt */ 7636 /* format IFP_SINGLE_WIDE_F1_1fmt */ 7637 /* nFields */ 6, 7638 /* *fields */ soc_IFP_SINGLE_WIDE_F1_1_BCM53400_A0fmt_fields, 7639 /* bits */ 37, 7640 /* flags */ 0, 7641 }, 7642 #endif /* chips */ 7643 7644 #if defined(BCM_53540_A0) 7645 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_1_BCM53540_A0fmt */ 7646 /* format IFP_SINGLE_WIDE_F1_1fmt */ 7647 /* nFields */ 5, 7648 /* *fields */ soc_IFP_SINGLE_WIDE_F1_1_BCM56160_A0fmt_fields, 7649 /* bits */ 37, 7650 /* flags */ 0, 7651 }, 7652 #endif /* chips */ 7653 7654 #if defined(BCM_53570_A0) 7655 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_1_BCM53570_A0fmt */ 7656 /* format IFP_SINGLE_WIDE_F1_1fmt */ 7657 /* nFields */ 5, 7658 /* *fields */ soc_IFP_SINGLE_WIDE_F1_1_BCM53570_A0fmt_fields, 7659 /* bits */ 39, 7660 /* flags */ 0, 7661 }, 7662 #endif /* chips */ 7663 7664 #if defined(BCM_53570_B0) 7665 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_1_BCM53570_B0fmt */ 7666 /* format IFP_SINGLE_WIDE_F1_1fmt */ 7667 /* nFields */ 5, 7668 /* *fields */ soc_IFP_SINGLE_WIDE_F1_1_BCM53570_A0fmt_fields, 7669 /* bits */ 39, 7670 /* flags */ 0, 7671 }, 7672 #endif /* chips */ 7673 7674 #if defined(BCM_56142_A0) 7675 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_1_BCM56142_A0fmt */ 7676 /* format IFP_SINGLE_WIDE_F1_1fmt */ 7677 /* nFields */ 6, 7678 /* *fields */ soc_IFP_SINGLE_WIDE_F1_1_BCM56634_A0fmt_fields, 7679 /* bits */ 37, 7680 /* flags */ 0, 7681 }, 7682 #endif /* chips */ 7683 7684 #if defined(BCM_56150_A0) 7685 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_1_BCM56150_A0fmt */ 7686 /* format IFP_SINGLE_WIDE_F1_1fmt */ 7687 /* nFields */ 6, 7688 /* *fields */ soc_IFP_SINGLE_WIDE_F1_1_BCM56150_A0fmt_fields, 7689 /* bits */ 37, 7690 /* flags */ 0, 7691 }, 7692 #endif /* chips */ 7693 7694 #if defined(BCM_56160_A0) 7695 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_1_BCM56160_A0fmt */ 7696 /* format IFP_SINGLE_WIDE_F1_1fmt */ 7697 /* nFields */ 5, 7698 /* *fields */ soc_IFP_SINGLE_WIDE_F1_1_BCM56160_A0fmt_fields, 7699 /* bits */ 37, 7700 /* flags */ 0, 7701 }, 7702 #endif /* chips */ 7703 7704 #if defined(BCM_56260_A0) 7705 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_1_BCM56260_A0fmt */ 7706 /* format IFP_SINGLE_WIDE_F1_1fmt */ 7707 /* nFields */ 6, 7708 /* *fields */ soc_IFP_SINGLE_WIDE_F1_1_BCM56260_A0fmt_fields, 7709 /* bits */ 40, 7710 /* flags */ 0, 7711 }, 7712 #endif /* chips */ 7713 7714 #if defined(BCM_56260_B0) 7715 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_1_BCM56260_B0fmt */ 7716 /* format IFP_SINGLE_WIDE_F1_1fmt */ 7717 /* nFields */ 6, 7718 /* *fields */ soc_IFP_SINGLE_WIDE_F1_1_BCM56260_A0fmt_fields, 7719 /* bits */ 40, 7720 /* flags */ 0, 7721 }, 7722 #endif /* chips */ 7723 7724 #if defined(BCM_56270_A0) 7725 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_1_BCM56270_A0fmt */ 7726 /* format IFP_SINGLE_WIDE_F1_1fmt */ 7727 /* nFields */ 6, 7728 /* *fields */ soc_IFP_SINGLE_WIDE_F1_1_BCM56260_A0fmt_fields, 7729 /* bits */ 40, 7730 /* flags */ 0, 7731 }, 7732 #endif /* chips */ 7733 7734 #if defined(BCM_56334_A0) 7735 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_1_BCM56334_A0fmt */ 7736 /* format IFP_SINGLE_WIDE_F1_1fmt */ 7737 /* nFields */ 6, 7738 /* *fields */ soc_IFP_SINGLE_WIDE_F1_1_BCM56634_A0fmt_fields, 7739 /* bits */ 37, 7740 /* flags */ 0, 7741 }, 7742 #endif /* chips */ 7743 7744 #if defined(BCM_56334_B0) 7745 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_1_BCM56334_B0fmt */ 7746 /* format IFP_SINGLE_WIDE_F1_1fmt */ 7747 /* nFields */ 6, 7748 /* *fields */ soc_IFP_SINGLE_WIDE_F1_1_BCM56634_A0fmt_fields, 7749 /* bits */ 37, 7750 /* flags */ 0, 7751 }, 7752 #endif /* chips */ 7753 7754 #if defined(BCM_56340_A0) 7755 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_1_BCM56340_A0fmt */ 7756 /* format IFP_SINGLE_WIDE_F1_1fmt */ 7757 /* nFields */ 6, 7758 /* *fields */ soc_IFP_SINGLE_WIDE_F1_1_BCM56640_A0fmt_fields, 7759 /* bits */ 49, 7760 /* flags */ 0, 7761 }, 7762 #endif /* chips */ 7763 7764 #if defined(BCM_56440_A0) 7765 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_1_BCM56440_A0fmt */ 7766 /* format IFP_SINGLE_WIDE_F1_1fmt */ 7767 /* nFields */ 5, 7768 /* *fields */ soc_IFP_SINGLE_WIDE_F1_1_BCM56840_A0fmt_fields, 7769 /* bits */ 39, 7770 /* flags */ 0, 7771 }, 7772 #endif /* chips */ 7773 7774 #if defined(BCM_56440_B0) 7775 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_1_BCM56440_B0fmt */ 7776 /* format IFP_SINGLE_WIDE_F1_1fmt */ 7777 /* nFields */ 5, 7778 /* *fields */ soc_IFP_SINGLE_WIDE_F1_1_BCM56840_A0fmt_fields, 7779 /* bits */ 39, 7780 /* flags */ 0, 7781 }, 7782 #endif /* chips */ 7783 7784 #if defined(BCM_56450_A0) 7785 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_1_BCM56450_A0fmt */ 7786 /* format IFP_SINGLE_WIDE_F1_1fmt */ 7787 /* nFields */ 6, 7788 /* *fields */ soc_IFP_SINGLE_WIDE_F1_1_BCM56450_A0fmt_fields, 7789 /* bits */ 40, 7790 /* flags */ 0, 7791 }, 7792 #endif /* chips */ 7793 7794 #if defined(BCM_56450_B0) 7795 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_1_BCM56450_B0fmt */ 7796 /* format IFP_SINGLE_WIDE_F1_1fmt */ 7797 /* nFields */ 6, 7798 /* *fields */ soc_IFP_SINGLE_WIDE_F1_1_BCM56450_A0fmt_fields, 7799 /* bits */ 40, 7800 /* flags */ 0, 7801 }, 7802 #endif /* chips */ 7803 7804 #if defined(BCM_56450_B1) 7805 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_1_BCM56450_B1fmt */ 7806 /* format IFP_SINGLE_WIDE_F1_1fmt */ 7807 /* nFields */ 6, 7808 /* *fields */ soc_IFP_SINGLE_WIDE_F1_1_BCM56450_A0fmt_fields, 7809 /* bits */ 40, 7810 /* flags */ 0, 7811 }, 7812 #endif /* chips */ 7813 7814 #if defined(BCM_56524_A0) 7815 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_1_BCM56524_A0fmt */ 7816 /* format IFP_SINGLE_WIDE_F1_1fmt */ 7817 /* nFields */ 6, 7818 /* *fields */ soc_IFP_SINGLE_WIDE_F1_1_BCM56634_A0fmt_fields, 7819 /* bits */ 37, 7820 /* flags */ 0, 7821 }, 7822 #endif /* chips */ 7823 7824 #if defined(BCM_56524_B0) 7825 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_1_BCM56524_B0fmt */ 7826 /* format IFP_SINGLE_WIDE_F1_1fmt */ 7827 /* nFields */ 6, 7828 /* *fields */ soc_IFP_SINGLE_WIDE_F1_1_BCM56634_A0fmt_fields, 7829 /* bits */ 37, 7830 /* flags */ 0, 7831 }, 7832 #endif /* chips */ 7833 7834 #if defined(BCM_56560_A0) 7835 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_1_BCM56560_A0fmt */ 7836 /* format IFP_SINGLE_WIDE_F1_1fmt */ 7837 /* nFields */ 5, 7838 /* *fields */ soc_IFP_SINGLE_WIDE_F1_1_BCM56560_A0fmt_fields, 7839 /* bits */ 50, 7840 /* flags */ 0, 7841 }, 7842 #endif /* chips */ 7843 7844 #if defined(BCM_56560_B0) 7845 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_1_BCM56560_B0fmt */ 7846 /* format IFP_SINGLE_WIDE_F1_1fmt */ 7847 /* nFields */ 5, 7848 /* *fields */ soc_IFP_SINGLE_WIDE_F1_1_BCM56560_A0fmt_fields, 7849 /* bits */ 50, 7850 /* flags */ 0, 7851 }, 7852 #endif /* chips */ 7853 7854 #if defined(BCM_56634_A0) 7855 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_1_BCM56634_A0fmt */ 7856 /* format IFP_SINGLE_WIDE_F1_1fmt */ 7857 /* nFields */ 6, 7858 /* *fields */ soc_IFP_SINGLE_WIDE_F1_1_BCM56634_A0fmt_fields, 7859 /* bits */ 37, 7860 /* flags */ 0, 7861 }, 7862 #endif /* chips */ 7863 7864 #if defined(BCM_56634_B0) 7865 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_1_BCM56634_B0fmt */ 7866 /* format IFP_SINGLE_WIDE_F1_1fmt */ 7867 /* nFields */ 6, 7868 /* *fields */ soc_IFP_SINGLE_WIDE_F1_1_BCM56634_A0fmt_fields, 7869 /* bits */ 37, 7870 /* flags */ 0, 7871 }, 7872 #endif /* chips */ 7873 7874 #if defined(BCM_56640_A0) 7875 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_1_BCM56640_A0fmt */ 7876 /* format IFP_SINGLE_WIDE_F1_1fmt */ 7877 /* nFields */ 6, 7878 /* *fields */ soc_IFP_SINGLE_WIDE_F1_1_BCM56640_A0fmt_fields, 7879 /* bits */ 49, 7880 /* flags */ 0, 7881 }, 7882 #endif /* chips */ 7883 7884 #if defined(BCM_56670_A0) 7885 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_1_BCM56670_A0fmt */ 7886 /* format IFP_SINGLE_WIDE_F1_1fmt */ 7887 /* nFields */ 5, 7888 /* *fields */ soc_IFP_SINGLE_WIDE_F1_1_BCM56560_A0fmt_fields, 7889 /* bits */ 50, 7890 /* flags */ 0, 7891 }, 7892 #endif /* chips */ 7893 7894 #if defined(BCM_56670_B0) 7895 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_1_BCM56670_B0fmt */ 7896 /* format IFP_SINGLE_WIDE_F1_1fmt */ 7897 /* nFields */ 5, 7898 /* *fields */ soc_IFP_SINGLE_WIDE_F1_1_BCM56560_A0fmt_fields, 7899 /* bits */ 50, 7900 /* flags */ 0, 7901 }, 7902 #endif /* chips */ 7903 7904 #if defined(BCM_56685_A0) 7905 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_1_BCM56685_A0fmt */ 7906 /* format IFP_SINGLE_WIDE_F1_1fmt */ 7907 /* nFields */ 6, 7908 /* *fields */ soc_IFP_SINGLE_WIDE_F1_1_BCM56634_A0fmt_fields, 7909 /* bits */ 37, 7910 /* flags */ 0, 7911 }, 7912 #endif /* chips */ 7913 7914 #if defined(BCM_56685_B0) 7915 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_1_BCM56685_B0fmt */ 7916 /* format IFP_SINGLE_WIDE_F1_1fmt */ 7917 /* nFields */ 6, 7918 /* *fields */ soc_IFP_SINGLE_WIDE_F1_1_BCM56634_A0fmt_fields, 7919 /* bits */ 37, 7920 /* flags */ 0, 7921 }, 7922 #endif /* chips */ 7923 7924 #if defined(BCM_56725_A0) 7925 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_1_BCM56725_A0fmt */ 7926 /* format IFP_SINGLE_WIDE_F1_1fmt */ 7927 /* nFields */ 8, 7928 /* *fields */ soc_IFP_SINGLE_WIDE_F1_1_BCM56820_A0fmt_fields, 7929 /* bits */ 34, 7930 /* flags */ 0, 7931 }, 7932 #endif /* chips */ 7933 7934 #if defined(BCM_56820_A0) 7935 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_1_BCM56820_A0fmt */ 7936 /* format IFP_SINGLE_WIDE_F1_1fmt */ 7937 /* nFields */ 8, 7938 /* *fields */ soc_IFP_SINGLE_WIDE_F1_1_BCM56820_A0fmt_fields, 7939 /* bits */ 34, 7940 /* flags */ 0, 7941 }, 7942 #endif /* chips */ 7943 7944 #if defined(BCM_56840_A0) 7945 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_1_BCM56840_A0fmt */ 7946 /* format IFP_SINGLE_WIDE_F1_1fmt */ 7947 /* nFields */ 5, 7948 /* *fields */ soc_IFP_SINGLE_WIDE_F1_1_BCM56840_A0fmt_fields, 7949 /* bits */ 39, 7950 /* flags */ 0, 7951 }, 7952 #endif /* chips */ 7953 7954 #if defined(BCM_56840_B0) 7955 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_1_BCM56840_B0fmt */ 7956 /* format IFP_SINGLE_WIDE_F1_1fmt */ 7957 /* nFields */ 5, 7958 /* *fields */ soc_IFP_SINGLE_WIDE_F1_1_BCM56840_A0fmt_fields, 7959 /* bits */ 39, 7960 /* flags */ 0, 7961 }, 7962 #endif /* chips */ 7963 7964 #if defined(BCM_56850_A0) 7965 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_1_BCM56850_A0fmt */ 7966 /* format IFP_SINGLE_WIDE_F1_1fmt */ 7967 /* nFields */ 5, 7968 /* *fields */ soc_IFP_SINGLE_WIDE_F1_1_BCM56850_A0fmt_fields, 7969 /* bits */ 49, 7970 /* flags */ 0, 7971 }, 7972 #endif /* chips */ 7973 7974 #if defined(BCM_56860_A0) 7975 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_1_BCM56860_A0fmt */ 7976 /* format IFP_SINGLE_WIDE_F1_1fmt */ 7977 /* nFields */ 5, 7978 /* *fields */ soc_IFP_SINGLE_WIDE_F1_1_BCM56860_A0fmt_fields, 7979 /* bits */ 50, 7980 /* flags */ 0, 7981 }, 7982 #endif /* chips */ 7983 7984 #if defined(BCM_88732_A0) 7985 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_1_BCM88732_A0fmt */ 7986 /* format IFP_SINGLE_WIDE_F1_1fmt */ 7987 /* nFields */ 8, 7988 /* *fields */ soc_IFP_SINGLE_WIDE_F1_1_BCM88732_A0fmt_fields, 7989 /* bits */ 34, 7990 /* flags */ 0, 7991 }, 7992 #endif /* chips */ 7993 7994 #if defined(BCM_53400_A0) 7995 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_2_BCM53400_A0fmt */ 7996 /* format IFP_SINGLE_WIDE_F1_2fmt */ 7997 /* nFields */ 5, 7998 /* *fields */ soc_IFP_SINGLE_WIDE_F1_2_BCM53400_A0fmt_fields, 7999 /* bits */ 37, 8000 /* flags */ 0, 8001 }, 8002 #endif /* chips */ 8003 8004 #if defined(BCM_53540_A0) 8005 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_2_BCM53540_A0fmt */ 8006 /* format IFP_SINGLE_WIDE_F1_2fmt */ 8007 /* nFields */ 5, 8008 /* *fields */ soc_IFP_SINGLE_WIDE_F1_2_BCM56160_A0fmt_fields, 8009 /* bits */ 37, 8010 /* flags */ 0, 8011 }, 8012 #endif /* chips */ 8013 8014 #if defined(BCM_53570_A0) 8015 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_2_BCM53570_A0fmt */ 8016 /* format IFP_SINGLE_WIDE_F1_2fmt */ 8017 /* nFields */ 5, 8018 /* *fields */ soc_IFP_SINGLE_WIDE_F1_2_BCM53570_A0fmt_fields, 8019 /* bits */ 39, 8020 /* flags */ 0, 8021 }, 8022 #endif /* chips */ 8023 8024 #if defined(BCM_53570_B0) 8025 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_2_BCM53570_B0fmt */ 8026 /* format IFP_SINGLE_WIDE_F1_2fmt */ 8027 /* nFields */ 5, 8028 /* *fields */ soc_IFP_SINGLE_WIDE_F1_2_BCM53570_A0fmt_fields, 8029 /* bits */ 39, 8030 /* flags */ 0, 8031 }, 8032 #endif /* chips */ 8033 8034 #if defined(BCM_56142_A0) 8035 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_2_BCM56142_A0fmt */ 8036 /* format IFP_SINGLE_WIDE_F1_2fmt */ 8037 /* nFields */ 5, 8038 /* *fields */ soc_IFP_SINGLE_WIDE_F1_2_BCM56634_A0fmt_fields, 8039 /* bits */ 37, 8040 /* flags */ 0, 8041 }, 8042 #endif /* chips */ 8043 8044 #if defined(BCM_56150_A0) 8045 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_2_BCM56150_A0fmt */ 8046 /* format IFP_SINGLE_WIDE_F1_2fmt */ 8047 /* nFields */ 5, 8048 /* *fields */ soc_IFP_SINGLE_WIDE_F1_2_BCM56150_A0fmt_fields, 8049 /* bits */ 37, 8050 /* flags */ 0, 8051 }, 8052 #endif /* chips */ 8053 8054 #if defined(BCM_56160_A0) 8055 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_2_BCM56160_A0fmt */ 8056 /* format IFP_SINGLE_WIDE_F1_2fmt */ 8057 /* nFields */ 5, 8058 /* *fields */ soc_IFP_SINGLE_WIDE_F1_2_BCM56160_A0fmt_fields, 8059 /* bits */ 37, 8060 /* flags */ 0, 8061 }, 8062 #endif /* chips */ 8063 8064 #if defined(BCM_56260_A0) 8065 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_2_BCM56260_A0fmt */ 8066 /* format IFP_SINGLE_WIDE_F1_2fmt */ 8067 /* nFields */ 5, 8068 /* *fields */ soc_IFP_SINGLE_WIDE_F1_2_BCM56260_A0fmt_fields, 8069 /* bits */ 40, 8070 /* flags */ 0, 8071 }, 8072 #endif /* chips */ 8073 8074 #if defined(BCM_56260_B0) 8075 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_2_BCM56260_B0fmt */ 8076 /* format IFP_SINGLE_WIDE_F1_2fmt */ 8077 /* nFields */ 5, 8078 /* *fields */ soc_IFP_SINGLE_WIDE_F1_2_BCM56260_A0fmt_fields, 8079 /* bits */ 40, 8080 /* flags */ 0, 8081 }, 8082 #endif /* chips */ 8083 8084 #if defined(BCM_56270_A0) 8085 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_2_BCM56270_A0fmt */ 8086 /* format IFP_SINGLE_WIDE_F1_2fmt */ 8087 /* nFields */ 5, 8088 /* *fields */ soc_IFP_SINGLE_WIDE_F1_2_BCM56260_A0fmt_fields, 8089 /* bits */ 40, 8090 /* flags */ 0, 8091 }, 8092 #endif /* chips */ 8093 8094 #if defined(BCM_56334_A0) 8095 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_2_BCM56334_A0fmt */ 8096 /* format IFP_SINGLE_WIDE_F1_2fmt */ 8097 /* nFields */ 5, 8098 /* *fields */ soc_IFP_SINGLE_WIDE_F1_2_BCM56634_A0fmt_fields, 8099 /* bits */ 37, 8100 /* flags */ 0, 8101 }, 8102 #endif /* chips */ 8103 8104 #if defined(BCM_56334_B0) 8105 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_2_BCM56334_B0fmt */ 8106 /* format IFP_SINGLE_WIDE_F1_2fmt */ 8107 /* nFields */ 5, 8108 /* *fields */ soc_IFP_SINGLE_WIDE_F1_2_BCM56634_A0fmt_fields, 8109 /* bits */ 37, 8110 /* flags */ 0, 8111 }, 8112 #endif /* chips */ 8113 8114 #if defined(BCM_56340_A0) 8115 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_2_BCM56340_A0fmt */ 8116 /* format IFP_SINGLE_WIDE_F1_2fmt */ 8117 /* nFields */ 6, 8118 /* *fields */ soc_IFP_SINGLE_WIDE_F1_2_BCM56640_A0fmt_fields, 8119 /* bits */ 49, 8120 /* flags */ 0, 8121 }, 8122 #endif /* chips */ 8123 8124 #if defined(BCM_56440_A0) 8125 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_2_BCM56440_A0fmt */ 8126 /* format IFP_SINGLE_WIDE_F1_2fmt */ 8127 /* nFields */ 5, 8128 /* *fields */ soc_IFP_SINGLE_WIDE_F1_2_BCM56840_A0fmt_fields, 8129 /* bits */ 39, 8130 /* flags */ 0, 8131 }, 8132 #endif /* chips */ 8133 8134 #if defined(BCM_56440_B0) 8135 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_2_BCM56440_B0fmt */ 8136 /* format IFP_SINGLE_WIDE_F1_2fmt */ 8137 /* nFields */ 5, 8138 /* *fields */ soc_IFP_SINGLE_WIDE_F1_2_BCM56840_A0fmt_fields, 8139 /* bits */ 39, 8140 /* flags */ 0, 8141 }, 8142 #endif /* chips */ 8143 8144 #if defined(BCM_56450_A0) 8145 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_2_BCM56450_A0fmt */ 8146 /* format IFP_SINGLE_WIDE_F1_2fmt */ 8147 /* nFields */ 5, 8148 /* *fields */ soc_IFP_SINGLE_WIDE_F1_2_BCM56450_A0fmt_fields, 8149 /* bits */ 40, 8150 /* flags */ 0, 8151 }, 8152 #endif /* chips */ 8153 8154 #if defined(BCM_56450_B0) 8155 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_2_BCM56450_B0fmt */ 8156 /* format IFP_SINGLE_WIDE_F1_2fmt */ 8157 /* nFields */ 5, 8158 /* *fields */ soc_IFP_SINGLE_WIDE_F1_2_BCM56450_A0fmt_fields, 8159 /* bits */ 40, 8160 /* flags */ 0, 8161 }, 8162 #endif /* chips */ 8163 8164 #if defined(BCM_56450_B1) 8165 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_2_BCM56450_B1fmt */ 8166 /* format IFP_SINGLE_WIDE_F1_2fmt */ 8167 /* nFields */ 5, 8168 /* *fields */ soc_IFP_SINGLE_WIDE_F1_2_BCM56450_A0fmt_fields, 8169 /* bits */ 40, 8170 /* flags */ 0, 8171 }, 8172 #endif /* chips */ 8173 8174 #if defined(BCM_56524_A0) 8175 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_2_BCM56524_A0fmt */ 8176 /* format IFP_SINGLE_WIDE_F1_2fmt */ 8177 /* nFields */ 5, 8178 /* *fields */ soc_IFP_SINGLE_WIDE_F1_2_BCM56634_A0fmt_fields, 8179 /* bits */ 37, 8180 /* flags */ 0, 8181 }, 8182 #endif /* chips */ 8183 8184 #if defined(BCM_56524_B0) 8185 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_2_BCM56524_B0fmt */ 8186 /* format IFP_SINGLE_WIDE_F1_2fmt */ 8187 /* nFields */ 5, 8188 /* *fields */ soc_IFP_SINGLE_WIDE_F1_2_BCM56634_A0fmt_fields, 8189 /* bits */ 37, 8190 /* flags */ 0, 8191 }, 8192 #endif /* chips */ 8193 8194 #if defined(BCM_56560_A0) 8195 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_2_BCM56560_A0fmt */ 8196 /* format IFP_SINGLE_WIDE_F1_2fmt */ 8197 /* nFields */ 6, 8198 /* *fields */ soc_IFP_SINGLE_WIDE_F1_2_BCM56560_A0fmt_fields, 8199 /* bits */ 50, 8200 /* flags */ 0, 8201 }, 8202 #endif /* chips */ 8203 8204 #if defined(BCM_56560_B0) 8205 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_2_BCM56560_B0fmt */ 8206 /* format IFP_SINGLE_WIDE_F1_2fmt */ 8207 /* nFields */ 6, 8208 /* *fields */ soc_IFP_SINGLE_WIDE_F1_2_BCM56560_A0fmt_fields, 8209 /* bits */ 50, 8210 /* flags */ 0, 8211 }, 8212 #endif /* chips */ 8213 8214 #if defined(BCM_56634_A0) 8215 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_2_BCM56634_A0fmt */ 8216 /* format IFP_SINGLE_WIDE_F1_2fmt */ 8217 /* nFields */ 5, 8218 /* *fields */ soc_IFP_SINGLE_WIDE_F1_2_BCM56634_A0fmt_fields, 8219 /* bits */ 37, 8220 /* flags */ 0, 8221 }, 8222 #endif /* chips */ 8223 8224 #if defined(BCM_56634_B0) 8225 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_2_BCM56634_B0fmt */ 8226 /* format IFP_SINGLE_WIDE_F1_2fmt */ 8227 /* nFields */ 5, 8228 /* *fields */ soc_IFP_SINGLE_WIDE_F1_2_BCM56634_A0fmt_fields, 8229 /* bits */ 37, 8230 /* flags */ 0, 8231 }, 8232 #endif /* chips */ 8233 8234 #if defined(BCM_56640_A0) 8235 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_2_BCM56640_A0fmt */ 8236 /* format IFP_SINGLE_WIDE_F1_2fmt */ 8237 /* nFields */ 6, 8238 /* *fields */ soc_IFP_SINGLE_WIDE_F1_2_BCM56640_A0fmt_fields, 8239 /* bits */ 49, 8240 /* flags */ 0, 8241 }, 8242 #endif /* chips */ 8243 8244 #if defined(BCM_56670_A0) 8245 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_2_BCM56670_A0fmt */ 8246 /* format IFP_SINGLE_WIDE_F1_2fmt */ 8247 /* nFields */ 7, 8248 /* *fields */ soc_IFP_SINGLE_WIDE_F1_2_BCM56670_A0fmt_fields, 8249 /* bits */ 50, 8250 /* flags */ 0, 8251 }, 8252 #endif /* chips */ 8253 8254 #if defined(BCM_56670_B0) 8255 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_2_BCM56670_B0fmt */ 8256 /* format IFP_SINGLE_WIDE_F1_2fmt */ 8257 /* nFields */ 7, 8258 /* *fields */ soc_IFP_SINGLE_WIDE_F1_2_BCM56670_A0fmt_fields, 8259 /* bits */ 50, 8260 /* flags */ 0, 8261 }, 8262 #endif /* chips */ 8263 8264 #if defined(BCM_56680_B0) 8265 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_2_BCM56680_B0fmt */ 8266 /* format IFP_SINGLE_WIDE_F1_2fmt */ 8267 /* nFields */ 6, 8268 /* *fields */ soc_IFP_SINGLE_WIDE_F1_2fmt_fields, 8269 /* bits */ 34, 8270 /* flags */ 0, 8271 }, 8272 #endif /* chips */ 8273 8274 #if defined(BCM_56685_A0) 8275 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_2_BCM56685_A0fmt */ 8276 /* format IFP_SINGLE_WIDE_F1_2fmt */ 8277 /* nFields */ 5, 8278 /* *fields */ soc_IFP_SINGLE_WIDE_F1_2_BCM56634_A0fmt_fields, 8279 /* bits */ 37, 8280 /* flags */ 0, 8281 }, 8282 #endif /* chips */ 8283 8284 #if defined(BCM_56685_B0) 8285 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_2_BCM56685_B0fmt */ 8286 /* format IFP_SINGLE_WIDE_F1_2fmt */ 8287 /* nFields */ 5, 8288 /* *fields */ soc_IFP_SINGLE_WIDE_F1_2_BCM56634_A0fmt_fields, 8289 /* bits */ 37, 8290 /* flags */ 0, 8291 }, 8292 #endif /* chips */ 8293 8294 #if defined(BCM_56725_A0) 8295 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_2_BCM56725_A0fmt */ 8296 /* format IFP_SINGLE_WIDE_F1_2fmt */ 8297 /* nFields */ 6, 8298 /* *fields */ soc_IFP_SINGLE_WIDE_F1_2_BCM56820_A0fmt_fields, 8299 /* bits */ 34, 8300 /* flags */ 0, 8301 }, 8302 #endif /* chips */ 8303 8304 #if defined(BCM_56820_A0) 8305 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_2_BCM56820_A0fmt */ 8306 /* format IFP_SINGLE_WIDE_F1_2fmt */ 8307 /* nFields */ 6, 8308 /* *fields */ soc_IFP_SINGLE_WIDE_F1_2_BCM56820_A0fmt_fields, 8309 /* bits */ 34, 8310 /* flags */ 0, 8311 }, 8312 #endif /* chips */ 8313 8314 #if defined(BCM_56840_A0) 8315 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_2_BCM56840_A0fmt */ 8316 /* format IFP_SINGLE_WIDE_F1_2fmt */ 8317 /* nFields */ 5, 8318 /* *fields */ soc_IFP_SINGLE_WIDE_F1_2_BCM56840_A0fmt_fields, 8319 /* bits */ 39, 8320 /* flags */ 0, 8321 }, 8322 #endif /* chips */ 8323 8324 #if defined(BCM_56840_B0) 8325 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_2_BCM56840_B0fmt */ 8326 /* format IFP_SINGLE_WIDE_F1_2fmt */ 8327 /* nFields */ 5, 8328 /* *fields */ soc_IFP_SINGLE_WIDE_F1_2_BCM56840_A0fmt_fields, 8329 /* bits */ 39, 8330 /* flags */ 0, 8331 }, 8332 #endif /* chips */ 8333 8334 #if defined(BCM_56850_A0) 8335 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_2_BCM56850_A0fmt */ 8336 /* format IFP_SINGLE_WIDE_F1_2fmt */ 8337 /* nFields */ 6, 8338 /* *fields */ soc_IFP_SINGLE_WIDE_F1_2_BCM56640_A0fmt_fields, 8339 /* bits */ 49, 8340 /* flags */ 0, 8341 }, 8342 #endif /* chips */ 8343 8344 #if defined(BCM_56860_A0) 8345 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_2_BCM56860_A0fmt */ 8346 /* format IFP_SINGLE_WIDE_F1_2fmt */ 8347 /* nFields */ 6, 8348 /* *fields */ soc_IFP_SINGLE_WIDE_F1_2_BCM56860_A0fmt_fields, 8349 /* bits */ 50, 8350 /* flags */ 0, 8351 }, 8352 #endif /* chips */ 8353 8354 #if defined(BCM_88732_A0) 8355 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_2_BCM88732_A0fmt */ 8356 /* format IFP_SINGLE_WIDE_F1_2fmt */ 8357 /* nFields */ 6, 8358 /* *fields */ soc_IFP_SINGLE_WIDE_F1_2_BCM88732_A0fmt_fields, 8359 /* bits */ 34, 8360 /* flags */ 0, 8361 }, 8362 #endif /* chips */ 8363 8364 #if defined(BCM_53400_A0) 8365 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_3_BCM53400_A0fmt */ 8366 /* format IFP_SINGLE_WIDE_F1_3fmt */ 8367 /* nFields */ 4, 8368 /* *fields */ soc_IFP_SINGLE_WIDE_F1_3_BCM53400_A0fmt_fields, 8369 /* bits */ 37, 8370 /* flags */ 0, 8371 }, 8372 #endif /* chips */ 8373 8374 #if defined(BCM_53540_A0) 8375 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_3_BCM53540_A0fmt */ 8376 /* format IFP_SINGLE_WIDE_F1_3fmt */ 8377 /* nFields */ 4, 8378 /* *fields */ soc_IFP_SINGLE_WIDE_F1_3_BCM53400_A0fmt_fields, 8379 /* bits */ 37, 8380 /* flags */ 0, 8381 }, 8382 #endif /* chips */ 8383 8384 #if defined(BCM_53570_A0) 8385 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_3_BCM53570_A0fmt */ 8386 /* format IFP_SINGLE_WIDE_F1_3fmt */ 8387 /* nFields */ 4, 8388 /* *fields */ soc_IFP_SINGLE_WIDE_F1_3_BCM53570_A0fmt_fields, 8389 /* bits */ 39, 8390 /* flags */ 0, 8391 }, 8392 #endif /* chips */ 8393 8394 #if defined(BCM_53570_B0) 8395 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_3_BCM53570_B0fmt */ 8396 /* format IFP_SINGLE_WIDE_F1_3fmt */ 8397 /* nFields */ 4, 8398 /* *fields */ soc_IFP_SINGLE_WIDE_F1_3_BCM53570_A0fmt_fields, 8399 /* bits */ 39, 8400 /* flags */ 0, 8401 }, 8402 #endif /* chips */ 8403 8404 #if defined(BCM_56142_A0) 8405 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_3_BCM56142_A0fmt */ 8406 /* format IFP_SINGLE_WIDE_F1_3fmt */ 8407 /* nFields */ 4, 8408 /* *fields */ soc_IFP_SINGLE_WIDE_F1_3_BCM56634_A0fmt_fields, 8409 /* bits */ 37, 8410 /* flags */ 0, 8411 }, 8412 #endif /* chips */ 8413 8414 #if defined(BCM_56150_A0) 8415 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_3_BCM56150_A0fmt */ 8416 /* format IFP_SINGLE_WIDE_F1_3fmt */ 8417 /* nFields */ 4, 8418 /* *fields */ soc_IFP_SINGLE_WIDE_F1_3_BCM56150_A0fmt_fields, 8419 /* bits */ 37, 8420 /* flags */ 0, 8421 }, 8422 #endif /* chips */ 8423 8424 #if defined(BCM_56160_A0) 8425 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_3_BCM56160_A0fmt */ 8426 /* format IFP_SINGLE_WIDE_F1_3fmt */ 8427 /* nFields */ 4, 8428 /* *fields */ soc_IFP_SINGLE_WIDE_F1_3_BCM53400_A0fmt_fields, 8429 /* bits */ 37, 8430 /* flags */ 0, 8431 }, 8432 #endif /* chips */ 8433 8434 #if defined(BCM_56260_A0) 8435 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_3_BCM56260_A0fmt */ 8436 /* format IFP_SINGLE_WIDE_F1_3fmt */ 8437 /* nFields */ 4, 8438 /* *fields */ soc_IFP_SINGLE_WIDE_F1_3_BCM56260_A0fmt_fields, 8439 /* bits */ 40, 8440 /* flags */ 0, 8441 }, 8442 #endif /* chips */ 8443 8444 #if defined(BCM_56260_B0) 8445 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_3_BCM56260_B0fmt */ 8446 /* format IFP_SINGLE_WIDE_F1_3fmt */ 8447 /* nFields */ 4, 8448 /* *fields */ soc_IFP_SINGLE_WIDE_F1_3_BCM56260_A0fmt_fields, 8449 /* bits */ 40, 8450 /* flags */ 0, 8451 }, 8452 #endif /* chips */ 8453 8454 #if defined(BCM_56270_A0) 8455 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_3_BCM56270_A0fmt */ 8456 /* format IFP_SINGLE_WIDE_F1_3fmt */ 8457 /* nFields */ 4, 8458 /* *fields */ soc_IFP_SINGLE_WIDE_F1_3_BCM56260_A0fmt_fields, 8459 /* bits */ 40, 8460 /* flags */ 0, 8461 }, 8462 #endif /* chips */ 8463 8464 #if defined(BCM_56334_A0) 8465 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_3_BCM56334_A0fmt */ 8466 /* format IFP_SINGLE_WIDE_F1_3fmt */ 8467 /* nFields */ 4, 8468 /* *fields */ soc_IFP_SINGLE_WIDE_F1_3_BCM56634_A0fmt_fields, 8469 /* bits */ 37, 8470 /* flags */ 0, 8471 }, 8472 #endif /* chips */ 8473 8474 #if defined(BCM_56334_B0) 8475 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_3_BCM56334_B0fmt */ 8476 /* format IFP_SINGLE_WIDE_F1_3fmt */ 8477 /* nFields */ 4, 8478 /* *fields */ soc_IFP_SINGLE_WIDE_F1_3_BCM56634_A0fmt_fields, 8479 /* bits */ 37, 8480 /* flags */ 0, 8481 }, 8482 #endif /* chips */ 8483 8484 #if defined(BCM_56340_A0) 8485 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_3_BCM56340_A0fmt */ 8486 /* format IFP_SINGLE_WIDE_F1_3fmt */ 8487 /* nFields */ 4, 8488 /* *fields */ soc_IFP_SINGLE_WIDE_F1_3_BCM56640_A0fmt_fields, 8489 /* bits */ 49, 8490 /* flags */ 0, 8491 }, 8492 #endif /* chips */ 8493 8494 #if defined(BCM_56440_A0) 8495 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_3_BCM56440_A0fmt */ 8496 /* format IFP_SINGLE_WIDE_F1_3fmt */ 8497 /* nFields */ 4, 8498 /* *fields */ soc_IFP_SINGLE_WIDE_F1_3_BCM56840_A0fmt_fields, 8499 /* bits */ 39, 8500 /* flags */ 0, 8501 }, 8502 #endif /* chips */ 8503 8504 #if defined(BCM_56440_B0) 8505 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_3_BCM56440_B0fmt */ 8506 /* format IFP_SINGLE_WIDE_F1_3fmt */ 8507 /* nFields */ 4, 8508 /* *fields */ soc_IFP_SINGLE_WIDE_F1_3_BCM56840_A0fmt_fields, 8509 /* bits */ 39, 8510 /* flags */ 0, 8511 }, 8512 #endif /* chips */ 8513 8514 #if defined(BCM_56450_A0) 8515 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_3_BCM56450_A0fmt */ 8516 /* format IFP_SINGLE_WIDE_F1_3fmt */ 8517 /* nFields */ 4, 8518 /* *fields */ soc_IFP_SINGLE_WIDE_F1_3_BCM56450_A0fmt_fields, 8519 /* bits */ 40, 8520 /* flags */ 0, 8521 }, 8522 #endif /* chips */ 8523 8524 #if defined(BCM_56450_B0) 8525 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_3_BCM56450_B0fmt */ 8526 /* format IFP_SINGLE_WIDE_F1_3fmt */ 8527 /* nFields */ 4, 8528 /* *fields */ soc_IFP_SINGLE_WIDE_F1_3_BCM56450_A0fmt_fields, 8529 /* bits */ 40, 8530 /* flags */ 0, 8531 }, 8532 #endif /* chips */ 8533 8534 #if defined(BCM_56450_B1) 8535 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_3_BCM56450_B1fmt */ 8536 /* format IFP_SINGLE_WIDE_F1_3fmt */ 8537 /* nFields */ 4, 8538 /* *fields */ soc_IFP_SINGLE_WIDE_F1_3_BCM56450_A0fmt_fields, 8539 /* bits */ 40, 8540 /* flags */ 0, 8541 }, 8542 #endif /* chips */ 8543 8544 #if defined(BCM_56524_A0) 8545 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_3_BCM56524_A0fmt */ 8546 /* format IFP_SINGLE_WIDE_F1_3fmt */ 8547 /* nFields */ 4, 8548 /* *fields */ soc_IFP_SINGLE_WIDE_F1_3_BCM56634_A0fmt_fields, 8549 /* bits */ 37, 8550 /* flags */ 0, 8551 }, 8552 #endif /* chips */ 8553 8554 #if defined(BCM_56524_B0) 8555 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_3_BCM56524_B0fmt */ 8556 /* format IFP_SINGLE_WIDE_F1_3fmt */ 8557 /* nFields */ 4, 8558 /* *fields */ soc_IFP_SINGLE_WIDE_F1_3_BCM56634_A0fmt_fields, 8559 /* bits */ 37, 8560 /* flags */ 0, 8561 }, 8562 #endif /* chips */ 8563 8564 #if defined(BCM_56560_A0) 8565 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_3_BCM56560_A0fmt */ 8566 /* format IFP_SINGLE_WIDE_F1_3fmt */ 8567 /* nFields */ 4, 8568 /* *fields */ soc_IFP_SINGLE_WIDE_F1_3_BCM56560_A0fmt_fields, 8569 /* bits */ 50, 8570 /* flags */ 0, 8571 }, 8572 #endif /* chips */ 8573 8574 #if defined(BCM_56560_B0) 8575 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_3_BCM56560_B0fmt */ 8576 /* format IFP_SINGLE_WIDE_F1_3fmt */ 8577 /* nFields */ 4, 8578 /* *fields */ soc_IFP_SINGLE_WIDE_F1_3_BCM56560_A0fmt_fields, 8579 /* bits */ 50, 8580 /* flags */ 0, 8581 }, 8582 #endif /* chips */ 8583 8584 #if defined(BCM_56634_A0) 8585 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_3_BCM56634_A0fmt */ 8586 /* format IFP_SINGLE_WIDE_F1_3fmt */ 8587 /* nFields */ 4, 8588 /* *fields */ soc_IFP_SINGLE_WIDE_F1_3_BCM56634_A0fmt_fields, 8589 /* bits */ 37, 8590 /* flags */ 0, 8591 }, 8592 #endif /* chips */ 8593 8594 #if defined(BCM_56634_B0) 8595 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_3_BCM56634_B0fmt */ 8596 /* format IFP_SINGLE_WIDE_F1_3fmt */ 8597 /* nFields */ 4, 8598 /* *fields */ soc_IFP_SINGLE_WIDE_F1_3_BCM56634_A0fmt_fields, 8599 /* bits */ 37, 8600 /* flags */ 0, 8601 }, 8602 #endif /* chips */ 8603 8604 #if defined(BCM_56640_A0) 8605 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_3_BCM56640_A0fmt */ 8606 /* format IFP_SINGLE_WIDE_F1_3fmt */ 8607 /* nFields */ 4, 8608 /* *fields */ soc_IFP_SINGLE_WIDE_F1_3_BCM56640_A0fmt_fields, 8609 /* bits */ 49, 8610 /* flags */ 0, 8611 }, 8612 #endif /* chips */ 8613 8614 #if defined(BCM_56670_A0) 8615 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_3_BCM56670_A0fmt */ 8616 /* format IFP_SINGLE_WIDE_F1_3fmt */ 8617 /* nFields */ 6, 8618 /* *fields */ soc_IFP_SINGLE_WIDE_F1_3_BCM56670_A0fmt_fields, 8619 /* bits */ 50, 8620 /* flags */ 0, 8621 }, 8622 #endif /* chips */ 8623 8624 #if defined(BCM_56670_B0) 8625 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_3_BCM56670_B0fmt */ 8626 /* format IFP_SINGLE_WIDE_F1_3fmt */ 8627 /* nFields */ 6, 8628 /* *fields */ soc_IFP_SINGLE_WIDE_F1_3_BCM56670_A0fmt_fields, 8629 /* bits */ 50, 8630 /* flags */ 0, 8631 }, 8632 #endif /* chips */ 8633 8634 #if defined(BCM_56680_B0) 8635 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_3_BCM56680_B0fmt */ 8636 /* format IFP_SINGLE_WIDE_F1_3fmt */ 8637 /* nFields */ 3, 8638 /* *fields */ soc_IFP_SINGLE_WIDE_F1_3fmt_fields, 8639 /* bits */ 34, 8640 /* flags */ 0, 8641 }, 8642 #endif /* chips */ 8643 8644 #if defined(BCM_56685_A0) 8645 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_3_BCM56685_A0fmt */ 8646 /* format IFP_SINGLE_WIDE_F1_3fmt */ 8647 /* nFields */ 4, 8648 /* *fields */ soc_IFP_SINGLE_WIDE_F1_3_BCM56634_A0fmt_fields, 8649 /* bits */ 37, 8650 /* flags */ 0, 8651 }, 8652 #endif /* chips */ 8653 8654 #if defined(BCM_56685_B0) 8655 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_3_BCM56685_B0fmt */ 8656 /* format IFP_SINGLE_WIDE_F1_3fmt */ 8657 /* nFields */ 4, 8658 /* *fields */ soc_IFP_SINGLE_WIDE_F1_3_BCM56634_A0fmt_fields, 8659 /* bits */ 37, 8660 /* flags */ 0, 8661 }, 8662 #endif /* chips */ 8663 8664 #if defined(BCM_56725_A0) 8665 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_3_BCM56725_A0fmt */ 8666 /* format IFP_SINGLE_WIDE_F1_3fmt */ 8667 /* nFields */ 3, 8668 /* *fields */ soc_IFP_SINGLE_WIDE_F1_3fmt_fields, 8669 /* bits */ 34, 8670 /* flags */ 0, 8671 }, 8672 #endif /* chips */ 8673 8674 #if defined(BCM_56820_A0) 8675 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_3_BCM56820_A0fmt */ 8676 /* format IFP_SINGLE_WIDE_F1_3fmt */ 8677 /* nFields */ 3, 8678 /* *fields */ soc_IFP_SINGLE_WIDE_F1_3fmt_fields, 8679 /* bits */ 34, 8680 /* flags */ 0, 8681 }, 8682 #endif /* chips */ 8683 8684 #if defined(BCM_56840_A0) 8685 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_3_BCM56840_A0fmt */ 8686 /* format IFP_SINGLE_WIDE_F1_3fmt */ 8687 /* nFields */ 4, 8688 /* *fields */ soc_IFP_SINGLE_WIDE_F1_3_BCM56840_A0fmt_fields, 8689 /* bits */ 39, 8690 /* flags */ 0, 8691 }, 8692 #endif /* chips */ 8693 8694 #if defined(BCM_56840_B0) 8695 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_3_BCM56840_B0fmt */ 8696 /* format IFP_SINGLE_WIDE_F1_3fmt */ 8697 /* nFields */ 4, 8698 /* *fields */ soc_IFP_SINGLE_WIDE_F1_3_BCM56840_A0fmt_fields, 8699 /* bits */ 39, 8700 /* flags */ 0, 8701 }, 8702 #endif /* chips */ 8703 8704 #if defined(BCM_56850_A0) 8705 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_3_BCM56850_A0fmt */ 8706 /* format IFP_SINGLE_WIDE_F1_3fmt */ 8707 /* nFields */ 4, 8708 /* *fields */ soc_IFP_SINGLE_WIDE_F1_3_BCM56640_A0fmt_fields, 8709 /* bits */ 49, 8710 /* flags */ 0, 8711 }, 8712 #endif /* chips */ 8713 8714 #if defined(BCM_56860_A0) 8715 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_3_BCM56860_A0fmt */ 8716 /* format IFP_SINGLE_WIDE_F1_3fmt */ 8717 /* nFields */ 4, 8718 /* *fields */ soc_IFP_SINGLE_WIDE_F1_3_BCM56860_A0fmt_fields, 8719 /* bits */ 50, 8720 /* flags */ 0, 8721 }, 8722 #endif /* chips */ 8723 8724 #if defined(BCM_53400_A0) 8725 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_4_BCM53400_A0fmt */ 8726 /* format IFP_SINGLE_WIDE_F1_4fmt */ 8727 /* nFields */ 3, 8728 /* *fields */ soc_IFP_SINGLE_WIDE_F1_4_BCM53400_A0fmt_fields, 8729 /* bits */ 37, 8730 /* flags */ 0, 8731 }, 8732 #endif /* chips */ 8733 8734 #if defined(BCM_53540_A0) 8735 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_4_BCM53540_A0fmt */ 8736 /* format IFP_SINGLE_WIDE_F1_4fmt */ 8737 /* nFields */ 3, 8738 /* *fields */ soc_IFP_SINGLE_WIDE_F1_4_BCM53400_A0fmt_fields, 8739 /* bits */ 37, 8740 /* flags */ 0, 8741 }, 8742 #endif /* chips */ 8743 8744 #if defined(BCM_53570_A0) 8745 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_4_BCM53570_A0fmt */ 8746 /* format IFP_SINGLE_WIDE_F1_4fmt */ 8747 /* nFields */ 3, 8748 /* *fields */ soc_IFP_SINGLE_WIDE_F1_4_BCM53570_A0fmt_fields, 8749 /* bits */ 39, 8750 /* flags */ 0, 8751 }, 8752 #endif /* chips */ 8753 8754 #if defined(BCM_53570_B0) 8755 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_4_BCM53570_B0fmt */ 8756 /* format IFP_SINGLE_WIDE_F1_4fmt */ 8757 /* nFields */ 3, 8758 /* *fields */ soc_IFP_SINGLE_WIDE_F1_4_BCM53570_A0fmt_fields, 8759 /* bits */ 39, 8760 /* flags */ 0, 8761 }, 8762 #endif /* chips */ 8763 8764 #if defined(BCM_56142_A0) 8765 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_4_BCM56142_A0fmt */ 8766 /* format IFP_SINGLE_WIDE_F1_4fmt */ 8767 /* nFields */ 3, 8768 /* *fields */ soc_IFP_SINGLE_WIDE_F1_4_BCM56634_A0fmt_fields, 8769 /* bits */ 37, 8770 /* flags */ 0, 8771 }, 8772 #endif /* chips */ 8773 8774 #if defined(BCM_56150_A0) 8775 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_4_BCM56150_A0fmt */ 8776 /* format IFP_SINGLE_WIDE_F1_4fmt */ 8777 /* nFields */ 3, 8778 /* *fields */ soc_IFP_SINGLE_WIDE_F1_4_BCM56150_A0fmt_fields, 8779 /* bits */ 37, 8780 /* flags */ 0, 8781 }, 8782 #endif /* chips */ 8783 8784 #if defined(BCM_56160_A0) 8785 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_4_BCM56160_A0fmt */ 8786 /* format IFP_SINGLE_WIDE_F1_4fmt */ 8787 /* nFields */ 3, 8788 /* *fields */ soc_IFP_SINGLE_WIDE_F1_4_BCM53400_A0fmt_fields, 8789 /* bits */ 37, 8790 /* flags */ 0, 8791 }, 8792 #endif /* chips */ 8793 8794 #if defined(BCM_56260_A0) 8795 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_4_BCM56260_A0fmt */ 8796 /* format IFP_SINGLE_WIDE_F1_4fmt */ 8797 /* nFields */ 3, 8798 /* *fields */ soc_IFP_SINGLE_WIDE_F1_4_BCM56260_A0fmt_fields, 8799 /* bits */ 40, 8800 /* flags */ 0, 8801 }, 8802 #endif /* chips */ 8803 8804 #if defined(BCM_56260_B0) 8805 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_4_BCM56260_B0fmt */ 8806 /* format IFP_SINGLE_WIDE_F1_4fmt */ 8807 /* nFields */ 3, 8808 /* *fields */ soc_IFP_SINGLE_WIDE_F1_4_BCM56260_A0fmt_fields, 8809 /* bits */ 40, 8810 /* flags */ 0, 8811 }, 8812 #endif /* chips */ 8813 8814 #if defined(BCM_56270_A0) 8815 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_4_BCM56270_A0fmt */ 8816 /* format IFP_SINGLE_WIDE_F1_4fmt */ 8817 /* nFields */ 3, 8818 /* *fields */ soc_IFP_SINGLE_WIDE_F1_4_BCM56260_A0fmt_fields, 8819 /* bits */ 40, 8820 /* flags */ 0, 8821 }, 8822 #endif /* chips */ 8823 8824 #if defined(BCM_56334_A0) 8825 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_4_BCM56334_A0fmt */ 8826 /* format IFP_SINGLE_WIDE_F1_4fmt */ 8827 /* nFields */ 3, 8828 /* *fields */ soc_IFP_SINGLE_WIDE_F1_4_BCM56634_A0fmt_fields, 8829 /* bits */ 37, 8830 /* flags */ 0, 8831 }, 8832 #endif /* chips */ 8833 8834 #if defined(BCM_56334_B0) 8835 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_4_BCM56334_B0fmt */ 8836 /* format IFP_SINGLE_WIDE_F1_4fmt */ 8837 /* nFields */ 3, 8838 /* *fields */ soc_IFP_SINGLE_WIDE_F1_4_BCM56634_A0fmt_fields, 8839 /* bits */ 37, 8840 /* flags */ 0, 8841 }, 8842 #endif /* chips */ 8843 8844 #if defined(BCM_56340_A0) 8845 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_4_BCM56340_A0fmt */ 8846 /* format IFP_SINGLE_WIDE_F1_4fmt */ 8847 /* nFields */ 5, 8848 /* *fields */ soc_IFP_SINGLE_WIDE_F1_4_BCM56640_A0fmt_fields, 8849 /* bits */ 49, 8850 /* flags */ 0, 8851 }, 8852 #endif /* chips */ 8853 8854 #if defined(BCM_56440_A0) 8855 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_4_BCM56440_A0fmt */ 8856 /* format IFP_SINGLE_WIDE_F1_4fmt */ 8857 /* nFields */ 3, 8858 /* *fields */ soc_IFP_SINGLE_WIDE_F1_4_BCM56440_A0fmt_fields, 8859 /* bits */ 39, 8860 /* flags */ 0, 8861 }, 8862 #endif /* chips */ 8863 8864 #if defined(BCM_56440_B0) 8865 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_4_BCM56440_B0fmt */ 8866 /* format IFP_SINGLE_WIDE_F1_4fmt */ 8867 /* nFields */ 3, 8868 /* *fields */ soc_IFP_SINGLE_WIDE_F1_4_BCM56440_A0fmt_fields, 8869 /* bits */ 39, 8870 /* flags */ 0, 8871 }, 8872 #endif /* chips */ 8873 8874 #if defined(BCM_56450_A0) 8875 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_4_BCM56450_A0fmt */ 8876 /* format IFP_SINGLE_WIDE_F1_4fmt */ 8877 /* nFields */ 3, 8878 /* *fields */ soc_IFP_SINGLE_WIDE_F1_4_BCM56450_A0fmt_fields, 8879 /* bits */ 40, 8880 /* flags */ 0, 8881 }, 8882 #endif /* chips */ 8883 8884 #if defined(BCM_56450_B0) 8885 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_4_BCM56450_B0fmt */ 8886 /* format IFP_SINGLE_WIDE_F1_4fmt */ 8887 /* nFields */ 3, 8888 /* *fields */ soc_IFP_SINGLE_WIDE_F1_4_BCM56450_A0fmt_fields, 8889 /* bits */ 40, 8890 /* flags */ 0, 8891 }, 8892 #endif /* chips */ 8893 8894 #if defined(BCM_56450_B1) 8895 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_4_BCM56450_B1fmt */ 8896 /* format IFP_SINGLE_WIDE_F1_4fmt */ 8897 /* nFields */ 3, 8898 /* *fields */ soc_IFP_SINGLE_WIDE_F1_4_BCM56450_A0fmt_fields, 8899 /* bits */ 40, 8900 /* flags */ 0, 8901 }, 8902 #endif /* chips */ 8903 8904 #if defined(BCM_56524_A0) 8905 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_4_BCM56524_A0fmt */ 8906 /* format IFP_SINGLE_WIDE_F1_4fmt */ 8907 /* nFields */ 3, 8908 /* *fields */ soc_IFP_SINGLE_WIDE_F1_4_BCM56634_A0fmt_fields, 8909 /* bits */ 37, 8910 /* flags */ 0, 8911 }, 8912 #endif /* chips */ 8913 8914 #if defined(BCM_56524_B0) 8915 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_4_BCM56524_B0fmt */ 8916 /* format IFP_SINGLE_WIDE_F1_4fmt */ 8917 /* nFields */ 3, 8918 /* *fields */ soc_IFP_SINGLE_WIDE_F1_4_BCM56634_A0fmt_fields, 8919 /* bits */ 37, 8920 /* flags */ 0, 8921 }, 8922 #endif /* chips */ 8923 8924 #if defined(BCM_56560_A0) 8925 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_4_BCM56560_A0fmt */ 8926 /* format IFP_SINGLE_WIDE_F1_4fmt */ 8927 /* nFields */ 5, 8928 /* *fields */ soc_IFP_SINGLE_WIDE_F1_4_BCM56560_A0fmt_fields, 8929 /* bits */ 50, 8930 /* flags */ 0, 8931 }, 8932 #endif /* chips */ 8933 8934 #if defined(BCM_56560_B0) 8935 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_4_BCM56560_B0fmt */ 8936 /* format IFP_SINGLE_WIDE_F1_4fmt */ 8937 /* nFields */ 5, 8938 /* *fields */ soc_IFP_SINGLE_WIDE_F1_4_BCM56560_A0fmt_fields, 8939 /* bits */ 50, 8940 /* flags */ 0, 8941 }, 8942 #endif /* chips */ 8943 8944 #if defined(BCM_56634_A0) 8945 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_4_BCM56634_A0fmt */ 8946 /* format IFP_SINGLE_WIDE_F1_4fmt */ 8947 /* nFields */ 3, 8948 /* *fields */ soc_IFP_SINGLE_WIDE_F1_4_BCM56634_A0fmt_fields, 8949 /* bits */ 37, 8950 /* flags */ 0, 8951 }, 8952 #endif /* chips */ 8953 8954 #if defined(BCM_56634_B0) 8955 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_4_BCM56634_B0fmt */ 8956 /* format IFP_SINGLE_WIDE_F1_4fmt */ 8957 /* nFields */ 3, 8958 /* *fields */ soc_IFP_SINGLE_WIDE_F1_4_BCM56634_A0fmt_fields, 8959 /* bits */ 37, 8960 /* flags */ 0, 8961 }, 8962 #endif /* chips */ 8963 8964 #if defined(BCM_56640_A0) 8965 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_4_BCM56640_A0fmt */ 8966 /* format IFP_SINGLE_WIDE_F1_4fmt */ 8967 /* nFields */ 5, 8968 /* *fields */ soc_IFP_SINGLE_WIDE_F1_4_BCM56640_A0fmt_fields, 8969 /* bits */ 49, 8970 /* flags */ 0, 8971 }, 8972 #endif /* chips */ 8973 8974 #if defined(BCM_56670_A0) 8975 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_4_BCM56670_A0fmt */ 8976 /* format IFP_SINGLE_WIDE_F1_4fmt */ 8977 /* nFields */ 6, 8978 /* *fields */ soc_IFP_SINGLE_WIDE_F1_4_BCM56670_A0fmt_fields, 8979 /* bits */ 50, 8980 /* flags */ 0, 8981 }, 8982 #endif /* chips */ 8983 8984 #if defined(BCM_56670_B0) 8985 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_4_BCM56670_B0fmt */ 8986 /* format IFP_SINGLE_WIDE_F1_4fmt */ 8987 /* nFields */ 6, 8988 /* *fields */ soc_IFP_SINGLE_WIDE_F1_4_BCM56670_A0fmt_fields, 8989 /* bits */ 50, 8990 /* flags */ 0, 8991 }, 8992 #endif /* chips */ 8993 8994 #if defined(BCM_56685_A0) 8995 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_4_BCM56685_A0fmt */ 8996 /* format IFP_SINGLE_WIDE_F1_4fmt */ 8997 /* nFields */ 3, 8998 /* *fields */ soc_IFP_SINGLE_WIDE_F1_4_BCM56634_A0fmt_fields, 8999 /* bits */ 37, 9000 /* flags */ 0, 9001 }, 9002 #endif /* chips */ 9003 9004 #if defined(BCM_56685_B0) 9005 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_4_BCM56685_B0fmt */ 9006 /* format IFP_SINGLE_WIDE_F1_4fmt */ 9007 /* nFields */ 3, 9008 /* *fields */ soc_IFP_SINGLE_WIDE_F1_4_BCM56634_A0fmt_fields, 9009 /* bits */ 37, 9010 /* flags */ 0, 9011 }, 9012 #endif /* chips */ 9013 9014 #if defined(BCM_56820_A0) 9015 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_4_BCM56820_A0fmt */ 9016 /* format IFP_SINGLE_WIDE_F1_4fmt */ 9017 /* nFields */ 3, 9018 /* *fields */ soc_IFP_SINGLE_WIDE_F1_4fmt_fields, 9019 /* bits */ 34, 9020 /* flags */ 0, 9021 }, 9022 #endif /* chips */ 9023 9024 #if defined(BCM_56840_A0) 9025 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_4_BCM56840_A0fmt */ 9026 /* format IFP_SINGLE_WIDE_F1_4fmt */ 9027 /* nFields */ 5, 9028 /* *fields */ soc_IFP_SINGLE_WIDE_F1_4_BCM56840_A0fmt_fields, 9029 /* bits */ 39, 9030 /* flags */ 0, 9031 }, 9032 #endif /* chips */ 9033 9034 #if defined(BCM_56840_B0) 9035 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_4_BCM56840_B0fmt */ 9036 /* format IFP_SINGLE_WIDE_F1_4fmt */ 9037 /* nFields */ 5, 9038 /* *fields */ soc_IFP_SINGLE_WIDE_F1_4_BCM56840_A0fmt_fields, 9039 /* bits */ 39, 9040 /* flags */ 0, 9041 }, 9042 #endif /* chips */ 9043 9044 #if defined(BCM_56850_A0) 9045 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_4_BCM56850_A0fmt */ 9046 /* format IFP_SINGLE_WIDE_F1_4fmt */ 9047 /* nFields */ 5, 9048 /* *fields */ soc_IFP_SINGLE_WIDE_F1_4_BCM56640_A0fmt_fields, 9049 /* bits */ 49, 9050 /* flags */ 0, 9051 }, 9052 #endif /* chips */ 9053 9054 #if defined(BCM_56860_A0) 9055 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_4_BCM56860_A0fmt */ 9056 /* format IFP_SINGLE_WIDE_F1_4fmt */ 9057 /* nFields */ 5, 9058 /* *fields */ soc_IFP_SINGLE_WIDE_F1_4_BCM56860_A0fmt_fields, 9059 /* bits */ 50, 9060 /* flags */ 0, 9061 }, 9062 #endif /* chips */ 9063 9064 #if defined(BCM_88732_A0) 9065 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_4_BCM88732_A0fmt */ 9066 /* format IFP_SINGLE_WIDE_F1_4fmt */ 9067 /* nFields */ 3, 9068 /* *fields */ soc_IFP_SINGLE_WIDE_F1_4_BCM88732_A0fmt_fields, 9069 /* bits */ 34, 9070 /* flags */ 0, 9071 }, 9072 #endif /* chips */ 9073 9074 #if defined(BCM_53400_A0) 9075 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_5_BCM53400_A0fmt */ 9076 /* format IFP_SINGLE_WIDE_F1_5fmt */ 9077 /* nFields */ 4, 9078 /* *fields */ soc_IFP_SINGLE_WIDE_F1_5_BCM53400_A0fmt_fields, 9079 /* bits */ 37, 9080 /* flags */ 0, 9081 }, 9082 #endif /* chips */ 9083 9084 #if defined(BCM_53540_A0) 9085 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_5_BCM53540_A0fmt */ 9086 /* format IFP_SINGLE_WIDE_F1_5fmt */ 9087 /* nFields */ 4, 9088 /* *fields */ soc_IFP_SINGLE_WIDE_F1_5_BCM53400_A0fmt_fields, 9089 /* bits */ 37, 9090 /* flags */ 0, 9091 }, 9092 #endif /* chips */ 9093 9094 #if defined(BCM_53570_A0) 9095 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_5_BCM53570_A0fmt */ 9096 /* format IFP_SINGLE_WIDE_F1_5fmt */ 9097 /* nFields */ 4, 9098 /* *fields */ soc_IFP_SINGLE_WIDE_F1_5_BCM53570_A0fmt_fields, 9099 /* bits */ 39, 9100 /* flags */ 0, 9101 }, 9102 #endif /* chips */ 9103 9104 #if defined(BCM_53570_B0) 9105 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_5_BCM53570_B0fmt */ 9106 /* format IFP_SINGLE_WIDE_F1_5fmt */ 9107 /* nFields */ 4, 9108 /* *fields */ soc_IFP_SINGLE_WIDE_F1_5_BCM53570_A0fmt_fields, 9109 /* bits */ 39, 9110 /* flags */ 0, 9111 }, 9112 #endif /* chips */ 9113 9114 #if defined(BCM_56142_A0) 9115 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_5_BCM56142_A0fmt */ 9116 /* format IFP_SINGLE_WIDE_F1_5fmt */ 9117 /* nFields */ 4, 9118 /* *fields */ soc_IFP_SINGLE_WIDE_F1_5_BCM56634_A0fmt_fields, 9119 /* bits */ 37, 9120 /* flags */ 0, 9121 }, 9122 #endif /* chips */ 9123 9124 #if defined(BCM_56150_A0) 9125 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_5_BCM56150_A0fmt */ 9126 /* format IFP_SINGLE_WIDE_F1_5fmt */ 9127 /* nFields */ 4, 9128 /* *fields */ soc_IFP_SINGLE_WIDE_F1_5_BCM56150_A0fmt_fields, 9129 /* bits */ 37, 9130 /* flags */ 0, 9131 }, 9132 #endif /* chips */ 9133 9134 #if defined(BCM_56160_A0) 9135 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_5_BCM56160_A0fmt */ 9136 /* format IFP_SINGLE_WIDE_F1_5fmt */ 9137 /* nFields */ 4, 9138 /* *fields */ soc_IFP_SINGLE_WIDE_F1_5_BCM53400_A0fmt_fields, 9139 /* bits */ 37, 9140 /* flags */ 0, 9141 }, 9142 #endif /* chips */ 9143 9144 #if defined(BCM_56260_A0) 9145 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_5_BCM56260_A0fmt */ 9146 /* format IFP_SINGLE_WIDE_F1_5fmt */ 9147 /* nFields */ 4, 9148 /* *fields */ soc_IFP_SINGLE_WIDE_F1_5_BCM56260_A0fmt_fields, 9149 /* bits */ 40, 9150 /* flags */ 0, 9151 }, 9152 #endif /* chips */ 9153 9154 #if defined(BCM_56260_B0) 9155 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_5_BCM56260_B0fmt */ 9156 /* format IFP_SINGLE_WIDE_F1_5fmt */ 9157 /* nFields */ 4, 9158 /* *fields */ soc_IFP_SINGLE_WIDE_F1_5_BCM56260_A0fmt_fields, 9159 /* bits */ 40, 9160 /* flags */ 0, 9161 }, 9162 #endif /* chips */ 9163 9164 #if defined(BCM_56270_A0) 9165 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_5_BCM56270_A0fmt */ 9166 /* format IFP_SINGLE_WIDE_F1_5fmt */ 9167 /* nFields */ 4, 9168 /* *fields */ soc_IFP_SINGLE_WIDE_F1_5_BCM56260_A0fmt_fields, 9169 /* bits */ 40, 9170 /* flags */ 0, 9171 }, 9172 #endif /* chips */ 9173 9174 #if defined(BCM_56334_A0) 9175 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_5_BCM56334_A0fmt */ 9176 /* format IFP_SINGLE_WIDE_F1_5fmt */ 9177 /* nFields */ 4, 9178 /* *fields */ soc_IFP_SINGLE_WIDE_F1_5_BCM56634_A0fmt_fields, 9179 /* bits */ 37, 9180 /* flags */ 0, 9181 }, 9182 #endif /* chips */ 9183 9184 #if defined(BCM_56334_B0) 9185 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_5_BCM56334_B0fmt */ 9186 /* format IFP_SINGLE_WIDE_F1_5fmt */ 9187 /* nFields */ 4, 9188 /* *fields */ soc_IFP_SINGLE_WIDE_F1_5_BCM56634_A0fmt_fields, 9189 /* bits */ 37, 9190 /* flags */ 0, 9191 }, 9192 #endif /* chips */ 9193 9194 #if defined(BCM_56340_A0) 9195 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_5_BCM56340_A0fmt */ 9196 /* format IFP_SINGLE_WIDE_F1_5fmt */ 9197 /* nFields */ 5, 9198 /* *fields */ soc_IFP_SINGLE_WIDE_F1_5_BCM56640_A0fmt_fields, 9199 /* bits */ 49, 9200 /* flags */ 0, 9201 }, 9202 #endif /* chips */ 9203 9204 #if defined(BCM_56440_A0) 9205 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_5_BCM56440_A0fmt */ 9206 /* format IFP_SINGLE_WIDE_F1_5fmt */ 9207 /* nFields */ 4, 9208 /* *fields */ soc_IFP_SINGLE_WIDE_F1_5_BCM56840_A0fmt_fields, 9209 /* bits */ 39, 9210 /* flags */ 0, 9211 }, 9212 #endif /* chips */ 9213 9214 #if defined(BCM_56440_B0) 9215 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_5_BCM56440_B0fmt */ 9216 /* format IFP_SINGLE_WIDE_F1_5fmt */ 9217 /* nFields */ 4, 9218 /* *fields */ soc_IFP_SINGLE_WIDE_F1_5_BCM56840_A0fmt_fields, 9219 /* bits */ 39, 9220 /* flags */ 0, 9221 }, 9222 #endif /* chips */ 9223 9224 #if defined(BCM_56450_A0) 9225 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_5_BCM56450_A0fmt */ 9226 /* format IFP_SINGLE_WIDE_F1_5fmt */ 9227 /* nFields */ 4, 9228 /* *fields */ soc_IFP_SINGLE_WIDE_F1_5_BCM56450_A0fmt_fields, 9229 /* bits */ 40, 9230 /* flags */ 0, 9231 }, 9232 #endif /* chips */ 9233 9234 #if defined(BCM_56450_B0) 9235 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_5_BCM56450_B0fmt */ 9236 /* format IFP_SINGLE_WIDE_F1_5fmt */ 9237 /* nFields */ 4, 9238 /* *fields */ soc_IFP_SINGLE_WIDE_F1_5_BCM56450_A0fmt_fields, 9239 /* bits */ 40, 9240 /* flags */ 0, 9241 }, 9242 #endif /* chips */ 9243 9244 #if defined(BCM_56450_B1) 9245 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_5_BCM56450_B1fmt */ 9246 /* format IFP_SINGLE_WIDE_F1_5fmt */ 9247 /* nFields */ 4, 9248 /* *fields */ soc_IFP_SINGLE_WIDE_F1_5_BCM56450_A0fmt_fields, 9249 /* bits */ 40, 9250 /* flags */ 0, 9251 }, 9252 #endif /* chips */ 9253 9254 #if defined(BCM_56524_A0) 9255 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_5_BCM56524_A0fmt */ 9256 /* format IFP_SINGLE_WIDE_F1_5fmt */ 9257 /* nFields */ 4, 9258 /* *fields */ soc_IFP_SINGLE_WIDE_F1_5_BCM56634_A0fmt_fields, 9259 /* bits */ 37, 9260 /* flags */ 0, 9261 }, 9262 #endif /* chips */ 9263 9264 #if defined(BCM_56524_B0) 9265 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_5_BCM56524_B0fmt */ 9266 /* format IFP_SINGLE_WIDE_F1_5fmt */ 9267 /* nFields */ 4, 9268 /* *fields */ soc_IFP_SINGLE_WIDE_F1_5_BCM56634_A0fmt_fields, 9269 /* bits */ 37, 9270 /* flags */ 0, 9271 }, 9272 #endif /* chips */ 9273 9274 #if defined(BCM_56560_A0) 9275 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_5_BCM56560_A0fmt */ 9276 /* format IFP_SINGLE_WIDE_F1_5fmt */ 9277 /* nFields */ 5, 9278 /* *fields */ soc_IFP_SINGLE_WIDE_F1_5_BCM56560_A0fmt_fields, 9279 /* bits */ 50, 9280 /* flags */ 0, 9281 }, 9282 #endif /* chips */ 9283 9284 #if defined(BCM_56560_B0) 9285 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_5_BCM56560_B0fmt */ 9286 /* format IFP_SINGLE_WIDE_F1_5fmt */ 9287 /* nFields */ 5, 9288 /* *fields */ soc_IFP_SINGLE_WIDE_F1_5_BCM56560_A0fmt_fields, 9289 /* bits */ 50, 9290 /* flags */ 0, 9291 }, 9292 #endif /* chips */ 9293 9294 #if defined(BCM_56634_A0) 9295 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_5_BCM56634_A0fmt */ 9296 /* format IFP_SINGLE_WIDE_F1_5fmt */ 9297 /* nFields */ 4, 9298 /* *fields */ soc_IFP_SINGLE_WIDE_F1_5_BCM56634_A0fmt_fields, 9299 /* bits */ 37, 9300 /* flags */ 0, 9301 }, 9302 #endif /* chips */ 9303 9304 #if defined(BCM_56634_B0) 9305 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_5_BCM56634_B0fmt */ 9306 /* format IFP_SINGLE_WIDE_F1_5fmt */ 9307 /* nFields */ 4, 9308 /* *fields */ soc_IFP_SINGLE_WIDE_F1_5_BCM56634_A0fmt_fields, 9309 /* bits */ 37, 9310 /* flags */ 0, 9311 }, 9312 #endif /* chips */ 9313 9314 #if defined(BCM_56640_A0) 9315 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_5_BCM56640_A0fmt */ 9316 /* format IFP_SINGLE_WIDE_F1_5fmt */ 9317 /* nFields */ 5, 9318 /* *fields */ soc_IFP_SINGLE_WIDE_F1_5_BCM56640_A0fmt_fields, 9319 /* bits */ 49, 9320 /* flags */ 0, 9321 }, 9322 #endif /* chips */ 9323 9324 #if defined(BCM_56670_A0) 9325 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_5_BCM56670_A0fmt */ 9326 /* format IFP_SINGLE_WIDE_F1_5fmt */ 9327 /* nFields */ 6, 9328 /* *fields */ soc_IFP_SINGLE_WIDE_F1_5_BCM56670_A0fmt_fields, 9329 /* bits */ 50, 9330 /* flags */ 0, 9331 }, 9332 #endif /* chips */ 9333 9334 #if defined(BCM_56670_B0) 9335 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_5_BCM56670_B0fmt */ 9336 /* format IFP_SINGLE_WIDE_F1_5fmt */ 9337 /* nFields */ 6, 9338 /* *fields */ soc_IFP_SINGLE_WIDE_F1_5_BCM56670_A0fmt_fields, 9339 /* bits */ 50, 9340 /* flags */ 0, 9341 }, 9342 #endif /* chips */ 9343 9344 #if defined(BCM_56680_B0) 9345 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_5_BCM56680_B0fmt */ 9346 /* format IFP_SINGLE_WIDE_F1_5fmt */ 9347 /* nFields */ 3, 9348 /* *fields */ soc_IFP_SINGLE_WIDE_F1_5fmt_fields, 9349 /* bits */ 34, 9350 /* flags */ 0, 9351 }, 9352 #endif /* chips */ 9353 9354 #if defined(BCM_56685_A0) 9355 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_5_BCM56685_A0fmt */ 9356 /* format IFP_SINGLE_WIDE_F1_5fmt */ 9357 /* nFields */ 4, 9358 /* *fields */ soc_IFP_SINGLE_WIDE_F1_5_BCM56634_A0fmt_fields, 9359 /* bits */ 37, 9360 /* flags */ 0, 9361 }, 9362 #endif /* chips */ 9363 9364 #if defined(BCM_56685_B0) 9365 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_5_BCM56685_B0fmt */ 9366 /* format IFP_SINGLE_WIDE_F1_5fmt */ 9367 /* nFields */ 4, 9368 /* *fields */ soc_IFP_SINGLE_WIDE_F1_5_BCM56634_A0fmt_fields, 9369 /* bits */ 37, 9370 /* flags */ 0, 9371 }, 9372 #endif /* chips */ 9373 9374 #if defined(BCM_56725_A0) 9375 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_5_BCM56725_A0fmt */ 9376 /* format IFP_SINGLE_WIDE_F1_5fmt */ 9377 /* nFields */ 3, 9378 /* *fields */ soc_IFP_SINGLE_WIDE_F1_5fmt_fields, 9379 /* bits */ 34, 9380 /* flags */ 0, 9381 }, 9382 #endif /* chips */ 9383 9384 #if defined(BCM_56820_A0) 9385 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_5_BCM56820_A0fmt */ 9386 /* format IFP_SINGLE_WIDE_F1_5fmt */ 9387 /* nFields */ 3, 9388 /* *fields */ soc_IFP_SINGLE_WIDE_F1_5fmt_fields, 9389 /* bits */ 34, 9390 /* flags */ 0, 9391 }, 9392 #endif /* chips */ 9393 9394 #if defined(BCM_56840_A0) 9395 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_5_BCM56840_A0fmt */ 9396 /* format IFP_SINGLE_WIDE_F1_5fmt */ 9397 /* nFields */ 4, 9398 /* *fields */ soc_IFP_SINGLE_WIDE_F1_5_BCM56840_A0fmt_fields, 9399 /* bits */ 39, 9400 /* flags */ 0, 9401 }, 9402 #endif /* chips */ 9403 9404 #if defined(BCM_56840_B0) 9405 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_5_BCM56840_B0fmt */ 9406 /* format IFP_SINGLE_WIDE_F1_5fmt */ 9407 /* nFields */ 4, 9408 /* *fields */ soc_IFP_SINGLE_WIDE_F1_5_BCM56840_A0fmt_fields, 9409 /* bits */ 39, 9410 /* flags */ 0, 9411 }, 9412 #endif /* chips */ 9413 9414 #if defined(BCM_56850_A0) 9415 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_5_BCM56850_A0fmt */ 9416 /* format IFP_SINGLE_WIDE_F1_5fmt */ 9417 /* nFields */ 5, 9418 /* *fields */ soc_IFP_SINGLE_WIDE_F1_5_BCM56640_A0fmt_fields, 9419 /* bits */ 49, 9420 /* flags */ 0, 9421 }, 9422 #endif /* chips */ 9423 9424 #if defined(BCM_56860_A0) 9425 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_5_BCM56860_A0fmt */ 9426 /* format IFP_SINGLE_WIDE_F1_5fmt */ 9427 /* nFields */ 5, 9428 /* *fields */ soc_IFP_SINGLE_WIDE_F1_5_BCM56860_A0fmt_fields, 9429 /* bits */ 50, 9430 /* flags */ 0, 9431 }, 9432 #endif /* chips */ 9433 9434 #if defined(BCM_53400_A0) 9435 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_6_BCM53400_A0fmt */ 9436 /* format IFP_SINGLE_WIDE_F1_6fmt */ 9437 /* nFields */ 7, 9438 /* *fields */ soc_IFP_SINGLE_WIDE_F1_6_BCM53400_A0fmt_fields, 9439 /* bits */ 37, 9440 /* flags */ 0, 9441 }, 9442 #endif /* chips */ 9443 9444 #if defined(BCM_53540_A0) 9445 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_6_BCM53540_A0fmt */ 9446 /* format IFP_SINGLE_WIDE_F1_6fmt */ 9447 /* nFields */ 7, 9448 /* *fields */ soc_IFP_SINGLE_WIDE_F1_6_BCM53400_A0fmt_fields, 9449 /* bits */ 37, 9450 /* flags */ 0, 9451 }, 9452 #endif /* chips */ 9453 9454 #if defined(BCM_53570_A0) 9455 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_6_BCM53570_A0fmt */ 9456 /* format IFP_SINGLE_WIDE_F1_6fmt */ 9457 /* nFields */ 7, 9458 /* *fields */ soc_IFP_SINGLE_WIDE_F1_6_BCM53570_A0fmt_fields, 9459 /* bits */ 39, 9460 /* flags */ 0, 9461 }, 9462 #endif /* chips */ 9463 9464 #if defined(BCM_53570_B0) 9465 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_6_BCM53570_B0fmt */ 9466 /* format IFP_SINGLE_WIDE_F1_6fmt */ 9467 /* nFields */ 7, 9468 /* *fields */ soc_IFP_SINGLE_WIDE_F1_6_BCM53570_A0fmt_fields, 9469 /* bits */ 39, 9470 /* flags */ 0, 9471 }, 9472 #endif /* chips */ 9473 9474 #if defined(BCM_56142_A0) 9475 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_6_BCM56142_A0fmt */ 9476 /* format IFP_SINGLE_WIDE_F1_6fmt */ 9477 /* nFields */ 7, 9478 /* *fields */ soc_IFP_SINGLE_WIDE_F1_6_BCM56634_A0fmt_fields, 9479 /* bits */ 37, 9480 /* flags */ 0, 9481 }, 9482 #endif /* chips */ 9483 9484 #if defined(BCM_56150_A0) 9485 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_6_BCM56150_A0fmt */ 9486 /* format IFP_SINGLE_WIDE_F1_6fmt */ 9487 /* nFields */ 7, 9488 /* *fields */ soc_IFP_SINGLE_WIDE_F1_6_BCM56150_A0fmt_fields, 9489 /* bits */ 37, 9490 /* flags */ 0, 9491 }, 9492 #endif /* chips */ 9493 9494 #if defined(BCM_56160_A0) 9495 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_6_BCM56160_A0fmt */ 9496 /* format IFP_SINGLE_WIDE_F1_6fmt */ 9497 /* nFields */ 7, 9498 /* *fields */ soc_IFP_SINGLE_WIDE_F1_6_BCM53400_A0fmt_fields, 9499 /* bits */ 37, 9500 /* flags */ 0, 9501 }, 9502 #endif /* chips */ 9503 9504 #if defined(BCM_56260_A0) 9505 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_6_BCM56260_A0fmt */ 9506 /* format IFP_SINGLE_WIDE_F1_6fmt */ 9507 /* nFields */ 7, 9508 /* *fields */ soc_IFP_SINGLE_WIDE_F1_6_BCM56260_A0fmt_fields, 9509 /* bits */ 40, 9510 /* flags */ 0, 9511 }, 9512 #endif /* chips */ 9513 9514 #if defined(BCM_56260_B0) 9515 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_6_BCM56260_B0fmt */ 9516 /* format IFP_SINGLE_WIDE_F1_6fmt */ 9517 /* nFields */ 7, 9518 /* *fields */ soc_IFP_SINGLE_WIDE_F1_6_BCM56260_A0fmt_fields, 9519 /* bits */ 40, 9520 /* flags */ 0, 9521 }, 9522 #endif /* chips */ 9523 9524 #if defined(BCM_56270_A0) 9525 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_6_BCM56270_A0fmt */ 9526 /* format IFP_SINGLE_WIDE_F1_6fmt */ 9527 /* nFields */ 7, 9528 /* *fields */ soc_IFP_SINGLE_WIDE_F1_6_BCM56260_A0fmt_fields, 9529 /* bits */ 40, 9530 /* flags */ 0, 9531 }, 9532 #endif /* chips */ 9533 9534 #if defined(BCM_56334_A0) 9535 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_6_BCM56334_A0fmt */ 9536 /* format IFP_SINGLE_WIDE_F1_6fmt */ 9537 /* nFields */ 7, 9538 /* *fields */ soc_IFP_SINGLE_WIDE_F1_6_BCM56634_A0fmt_fields, 9539 /* bits */ 37, 9540 /* flags */ 0, 9541 }, 9542 #endif /* chips */ 9543 9544 #if defined(BCM_56334_B0) 9545 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_6_BCM56334_B0fmt */ 9546 /* format IFP_SINGLE_WIDE_F1_6fmt */ 9547 /* nFields */ 7, 9548 /* *fields */ soc_IFP_SINGLE_WIDE_F1_6_BCM56634_A0fmt_fields, 9549 /* bits */ 37, 9550 /* flags */ 0, 9551 }, 9552 #endif /* chips */ 9553 9554 #if defined(BCM_56340_A0) 9555 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_6_BCM56340_A0fmt */ 9556 /* format IFP_SINGLE_WIDE_F1_6fmt */ 9557 /* nFields */ 9, 9558 /* *fields */ soc_IFP_SINGLE_WIDE_F1_6_BCM56640_A0fmt_fields, 9559 /* bits */ 49, 9560 /* flags */ 0, 9561 }, 9562 #endif /* chips */ 9563 9564 #if defined(BCM_56440_A0) 9565 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_6_BCM56440_A0fmt */ 9566 /* format IFP_SINGLE_WIDE_F1_6fmt */ 9567 /* nFields */ 7, 9568 /* *fields */ soc_IFP_SINGLE_WIDE_F1_6_BCM56440_A0fmt_fields, 9569 /* bits */ 39, 9570 /* flags */ 0, 9571 }, 9572 #endif /* chips */ 9573 9574 #if defined(BCM_56440_B0) 9575 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_6_BCM56440_B0fmt */ 9576 /* format IFP_SINGLE_WIDE_F1_6fmt */ 9577 /* nFields */ 7, 9578 /* *fields */ soc_IFP_SINGLE_WIDE_F1_6_BCM56440_A0fmt_fields, 9579 /* bits */ 39, 9580 /* flags */ 0, 9581 }, 9582 #endif /* chips */ 9583 9584 #if defined(BCM_56450_A0) 9585 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_6_BCM56450_A0fmt */ 9586 /* format IFP_SINGLE_WIDE_F1_6fmt */ 9587 /* nFields */ 7, 9588 /* *fields */ soc_IFP_SINGLE_WIDE_F1_6_BCM56450_A0fmt_fields, 9589 /* bits */ 40, 9590 /* flags */ 0, 9591 }, 9592 #endif /* chips */ 9593 9594 #if defined(BCM_56450_B0) 9595 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_6_BCM56450_B0fmt */ 9596 /* format IFP_SINGLE_WIDE_F1_6fmt */ 9597 /* nFields */ 7, 9598 /* *fields */ soc_IFP_SINGLE_WIDE_F1_6_BCM56450_A0fmt_fields, 9599 /* bits */ 40, 9600 /* flags */ 0, 9601 }, 9602 #endif /* chips */ 9603 9604 #if defined(BCM_56450_B1) 9605 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_6_BCM56450_B1fmt */ 9606 /* format IFP_SINGLE_WIDE_F1_6fmt */ 9607 /* nFields */ 7, 9608 /* *fields */ soc_IFP_SINGLE_WIDE_F1_6_BCM56450_A0fmt_fields, 9609 /* bits */ 40, 9610 /* flags */ 0, 9611 }, 9612 #endif /* chips */ 9613 9614 #if defined(BCM_56524_A0) 9615 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_6_BCM56524_A0fmt */ 9616 /* format IFP_SINGLE_WIDE_F1_6fmt */ 9617 /* nFields */ 7, 9618 /* *fields */ soc_IFP_SINGLE_WIDE_F1_6_BCM56634_A0fmt_fields, 9619 /* bits */ 37, 9620 /* flags */ 0, 9621 }, 9622 #endif /* chips */ 9623 9624 #if defined(BCM_56524_B0) 9625 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_6_BCM56524_B0fmt */ 9626 /* format IFP_SINGLE_WIDE_F1_6fmt */ 9627 /* nFields */ 7, 9628 /* *fields */ soc_IFP_SINGLE_WIDE_F1_6_BCM56634_A0fmt_fields, 9629 /* bits */ 37, 9630 /* flags */ 0, 9631 }, 9632 #endif /* chips */ 9633 9634 #if defined(BCM_56560_A0) 9635 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_6_BCM56560_A0fmt */ 9636 /* format IFP_SINGLE_WIDE_F1_6fmt */ 9637 /* nFields */ 8, 9638 /* *fields */ soc_IFP_SINGLE_WIDE_F1_6_BCM56560_A0fmt_fields, 9639 /* bits */ 50, 9640 /* flags */ 0, 9641 }, 9642 #endif /* chips */ 9643 9644 #if defined(BCM_56560_B0) 9645 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_6_BCM56560_B0fmt */ 9646 /* format IFP_SINGLE_WIDE_F1_6fmt */ 9647 /* nFields */ 8, 9648 /* *fields */ soc_IFP_SINGLE_WIDE_F1_6_BCM56560_A0fmt_fields, 9649 /* bits */ 50, 9650 /* flags */ 0, 9651 }, 9652 #endif /* chips */ 9653 9654 #if defined(BCM_56624_B0) 9655 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_6_BCM56624_B0fmt */ 9656 /* format IFP_SINGLE_WIDE_F1_6fmt */ 9657 /* nFields */ 6, 9658 /* *fields */ soc_IFP_SINGLE_WIDE_F1_6fmt_fields, 9659 /* bits */ 32, 9660 /* flags */ 0, 9661 }, 9662 #endif /* chips */ 9663 9664 #if defined(BCM_56634_A0) 9665 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_6_BCM56634_A0fmt */ 9666 /* format IFP_SINGLE_WIDE_F1_6fmt */ 9667 /* nFields */ 7, 9668 /* *fields */ soc_IFP_SINGLE_WIDE_F1_6_BCM56634_A0fmt_fields, 9669 /* bits */ 37, 9670 /* flags */ 0, 9671 }, 9672 #endif /* chips */ 9673 9674 #if defined(BCM_56634_B0) 9675 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_6_BCM56634_B0fmt */ 9676 /* format IFP_SINGLE_WIDE_F1_6fmt */ 9677 /* nFields */ 7, 9678 /* *fields */ soc_IFP_SINGLE_WIDE_F1_6_BCM56634_A0fmt_fields, 9679 /* bits */ 37, 9680 /* flags */ 0, 9681 }, 9682 #endif /* chips */ 9683 9684 #if defined(BCM_56640_A0) 9685 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_6_BCM56640_A0fmt */ 9686 /* format IFP_SINGLE_WIDE_F1_6fmt */ 9687 /* nFields */ 9, 9688 /* *fields */ soc_IFP_SINGLE_WIDE_F1_6_BCM56640_A0fmt_fields, 9689 /* bits */ 49, 9690 /* flags */ 0, 9691 }, 9692 #endif /* chips */ 9693 9694 #if defined(BCM_56670_A0) 9695 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_6_BCM56670_A0fmt */ 9696 /* format IFP_SINGLE_WIDE_F1_6fmt */ 9697 /* nFields */ 8, 9698 /* *fields */ soc_IFP_SINGLE_WIDE_F1_6_BCM56560_A0fmt_fields, 9699 /* bits */ 50, 9700 /* flags */ 0, 9701 }, 9702 #endif /* chips */ 9703 9704 #if defined(BCM_56670_B0) 9705 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_6_BCM56670_B0fmt */ 9706 /* format IFP_SINGLE_WIDE_F1_6fmt */ 9707 /* nFields */ 8, 9708 /* *fields */ soc_IFP_SINGLE_WIDE_F1_6_BCM56560_A0fmt_fields, 9709 /* bits */ 50, 9710 /* flags */ 0, 9711 }, 9712 #endif /* chips */ 9713 9714 #if defined(BCM_56680_A0) 9715 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_6_BCM56680_A0fmt */ 9716 /* format IFP_SINGLE_WIDE_F1_6fmt */ 9717 /* nFields */ 6, 9718 /* *fields */ soc_IFP_SINGLE_WIDE_F1_6fmt_fields, 9719 /* bits */ 32, 9720 /* flags */ 0, 9721 }, 9722 #endif /* chips */ 9723 9724 #if defined(BCM_56680_B0) 9725 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_6_BCM56680_B0fmt */ 9726 /* format IFP_SINGLE_WIDE_F1_6fmt */ 9727 /* nFields */ 6, 9728 /* *fields */ soc_IFP_SINGLE_WIDE_F1_6fmt_fields, 9729 /* bits */ 32, 9730 /* flags */ 0, 9731 }, 9732 #endif /* chips */ 9733 9734 #if defined(BCM_56685_A0) 9735 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_6_BCM56685_A0fmt */ 9736 /* format IFP_SINGLE_WIDE_F1_6fmt */ 9737 /* nFields */ 7, 9738 /* *fields */ soc_IFP_SINGLE_WIDE_F1_6_BCM56634_A0fmt_fields, 9739 /* bits */ 37, 9740 /* flags */ 0, 9741 }, 9742 #endif /* chips */ 9743 9744 #if defined(BCM_56685_B0) 9745 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_6_BCM56685_B0fmt */ 9746 /* format IFP_SINGLE_WIDE_F1_6fmt */ 9747 /* nFields */ 7, 9748 /* *fields */ soc_IFP_SINGLE_WIDE_F1_6_BCM56634_A0fmt_fields, 9749 /* bits */ 37, 9750 /* flags */ 0, 9751 }, 9752 #endif /* chips */ 9753 9754 #if defined(BCM_56725_A0) 9755 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_6_BCM56725_A0fmt */ 9756 /* format IFP_SINGLE_WIDE_F1_6fmt */ 9757 /* nFields */ 6, 9758 /* *fields */ soc_IFP_SINGLE_WIDE_F1_6fmt_fields, 9759 /* bits */ 32, 9760 /* flags */ 0, 9761 }, 9762 #endif /* chips */ 9763 9764 #if defined(BCM_56820_A0) 9765 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_6_BCM56820_A0fmt */ 9766 /* format IFP_SINGLE_WIDE_F1_6fmt */ 9767 /* nFields */ 6, 9768 /* *fields */ soc_IFP_SINGLE_WIDE_F1_6fmt_fields, 9769 /* bits */ 32, 9770 /* flags */ 0, 9771 }, 9772 #endif /* chips */ 9773 9774 #if defined(BCM_56840_A0) 9775 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_6_BCM56840_A0fmt */ 9776 /* format IFP_SINGLE_WIDE_F1_6fmt */ 9777 /* nFields */ 8, 9778 /* *fields */ soc_IFP_SINGLE_WIDE_F1_6_BCM56840_A0fmt_fields, 9779 /* bits */ 39, 9780 /* flags */ 0, 9781 }, 9782 #endif /* chips */ 9783 9784 #if defined(BCM_56840_B0) 9785 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_6_BCM56840_B0fmt */ 9786 /* format IFP_SINGLE_WIDE_F1_6fmt */ 9787 /* nFields */ 8, 9788 /* *fields */ soc_IFP_SINGLE_WIDE_F1_6_BCM56840_A0fmt_fields, 9789 /* bits */ 39, 9790 /* flags */ 0, 9791 }, 9792 #endif /* chips */ 9793 9794 #if defined(BCM_56850_A0) 9795 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_6_BCM56850_A0fmt */ 9796 /* format IFP_SINGLE_WIDE_F1_6fmt */ 9797 /* nFields */ 7, 9798 /* *fields */ soc_IFP_SINGLE_WIDE_F1_6_BCM56850_A0fmt_fields, 9799 /* bits */ 49, 9800 /* flags */ 0, 9801 }, 9802 #endif /* chips */ 9803 9804 #if defined(BCM_56860_A0) 9805 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_6_BCM56860_A0fmt */ 9806 /* format IFP_SINGLE_WIDE_F1_6fmt */ 9807 /* nFields */ 8, 9808 /* *fields */ soc_IFP_SINGLE_WIDE_F1_6_BCM56860_A0fmt_fields, 9809 /* bits */ 50, 9810 /* flags */ 0, 9811 }, 9812 #endif /* chips */ 9813 9814 #if defined(BCM_88732_A0) 9815 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_6_BCM88732_A0fmt */ 9816 /* format IFP_SINGLE_WIDE_F1_6fmt */ 9817 /* nFields */ 6, 9818 /* *fields */ soc_IFP_SINGLE_WIDE_F1_6_BCM88732_A0fmt_fields, 9819 /* bits */ 32, 9820 /* flags */ 0, 9821 }, 9822 #endif /* chips */ 9823 9824 #if defined(BCM_53400_A0) 9825 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_7_BCM53400_A0fmt */ 9826 /* format IFP_SINGLE_WIDE_F1_7fmt */ 9827 /* nFields */ 5, 9828 /* *fields */ soc_IFP_SINGLE_WIDE_F1_7_BCM53400_A0fmt_fields, 9829 /* bits */ 37, 9830 /* flags */ 0, 9831 }, 9832 #endif /* chips */ 9833 9834 #if defined(BCM_53540_A0) 9835 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_7_BCM53540_A0fmt */ 9836 /* format IFP_SINGLE_WIDE_F1_7fmt */ 9837 /* nFields */ 5, 9838 /* *fields */ soc_IFP_SINGLE_WIDE_F1_7_BCM53400_A0fmt_fields, 9839 /* bits */ 37, 9840 /* flags */ 0, 9841 }, 9842 #endif /* chips */ 9843 9844 #if defined(BCM_53570_A0) 9845 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_7_BCM53570_A0fmt */ 9846 /* format IFP_SINGLE_WIDE_F1_7fmt */ 9847 /* nFields */ 5, 9848 /* *fields */ soc_IFP_SINGLE_WIDE_F1_7_BCM53570_A0fmt_fields, 9849 /* bits */ 39, 9850 /* flags */ 0, 9851 }, 9852 #endif /* chips */ 9853 9854 #if defined(BCM_53570_B0) 9855 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_7_BCM53570_B0fmt */ 9856 /* format IFP_SINGLE_WIDE_F1_7fmt */ 9857 /* nFields */ 5, 9858 /* *fields */ soc_IFP_SINGLE_WIDE_F1_7_BCM53570_A0fmt_fields, 9859 /* bits */ 39, 9860 /* flags */ 0, 9861 }, 9862 #endif /* chips */ 9863 9864 #if defined(BCM_56142_A0) 9865 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_7_BCM56142_A0fmt */ 9866 /* format IFP_SINGLE_WIDE_F1_7fmt */ 9867 /* nFields */ 5, 9868 /* *fields */ soc_IFP_SINGLE_WIDE_F1_7_BCM56634_A0fmt_fields, 9869 /* bits */ 37, 9870 /* flags */ 0, 9871 }, 9872 #endif /* chips */ 9873 9874 #if defined(BCM_56150_A0) 9875 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_7_BCM56150_A0fmt */ 9876 /* format IFP_SINGLE_WIDE_F1_7fmt */ 9877 /* nFields */ 5, 9878 /* *fields */ soc_IFP_SINGLE_WIDE_F1_7_BCM56150_A0fmt_fields, 9879 /* bits */ 37, 9880 /* flags */ 0, 9881 }, 9882 #endif /* chips */ 9883 9884 #if defined(BCM_56160_A0) 9885 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_7_BCM56160_A0fmt */ 9886 /* format IFP_SINGLE_WIDE_F1_7fmt */ 9887 /* nFields */ 5, 9888 /* *fields */ soc_IFP_SINGLE_WIDE_F1_7_BCM53400_A0fmt_fields, 9889 /* bits */ 37, 9890 /* flags */ 0, 9891 }, 9892 #endif /* chips */ 9893 9894 #if defined(BCM_56260_A0) 9895 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_7_BCM56260_A0fmt */ 9896 /* format IFP_SINGLE_WIDE_F1_7fmt */ 9897 /* nFields */ 6, 9898 /* *fields */ soc_IFP_SINGLE_WIDE_F1_7_BCM56260_A0fmt_fields, 9899 /* bits */ 40, 9900 /* flags */ 0, 9901 }, 9902 #endif /* chips */ 9903 9904 #if defined(BCM_56260_B0) 9905 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_7_BCM56260_B0fmt */ 9906 /* format IFP_SINGLE_WIDE_F1_7fmt */ 9907 /* nFields */ 6, 9908 /* *fields */ soc_IFP_SINGLE_WIDE_F1_7_BCM56260_A0fmt_fields, 9909 /* bits */ 40, 9910 /* flags */ 0, 9911 }, 9912 #endif /* chips */ 9913 9914 #if defined(BCM_56270_A0) 9915 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_7_BCM56270_A0fmt */ 9916 /* format IFP_SINGLE_WIDE_F1_7fmt */ 9917 /* nFields */ 6, 9918 /* *fields */ soc_IFP_SINGLE_WIDE_F1_7_BCM56260_A0fmt_fields, 9919 /* bits */ 40, 9920 /* flags */ 0, 9921 }, 9922 #endif /* chips */ 9923 9924 #if defined(BCM_56334_A0) 9925 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_7_BCM56334_A0fmt */ 9926 /* format IFP_SINGLE_WIDE_F1_7fmt */ 9927 /* nFields */ 5, 9928 /* *fields */ soc_IFP_SINGLE_WIDE_F1_7_BCM56634_A0fmt_fields, 9929 /* bits */ 37, 9930 /* flags */ 0, 9931 }, 9932 #endif /* chips */ 9933 9934 #if defined(BCM_56334_B0) 9935 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_7_BCM56334_B0fmt */ 9936 /* format IFP_SINGLE_WIDE_F1_7fmt */ 9937 /* nFields */ 5, 9938 /* *fields */ soc_IFP_SINGLE_WIDE_F1_7_BCM56634_A0fmt_fields, 9939 /* bits */ 37, 9940 /* flags */ 0, 9941 }, 9942 #endif /* chips */ 9943 9944 #if defined(BCM_56340_A0) 9945 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_7_BCM56340_A0fmt */ 9946 /* format IFP_SINGLE_WIDE_F1_7fmt */ 9947 /* nFields */ 5, 9948 /* *fields */ soc_IFP_SINGLE_WIDE_F1_7_BCM56640_A0fmt_fields, 9949 /* bits */ 49, 9950 /* flags */ 0, 9951 }, 9952 #endif /* chips */ 9953 9954 #if defined(BCM_56440_A0) 9955 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_7_BCM56440_A0fmt */ 9956 /* format IFP_SINGLE_WIDE_F1_7fmt */ 9957 /* nFields */ 5, 9958 /* *fields */ soc_IFP_SINGLE_WIDE_F1_7_BCM56840_A0fmt_fields, 9959 /* bits */ 39, 9960 /* flags */ 0, 9961 }, 9962 #endif /* chips */ 9963 9964 #if defined(BCM_56440_B0) 9965 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_7_BCM56440_B0fmt */ 9966 /* format IFP_SINGLE_WIDE_F1_7fmt */ 9967 /* nFields */ 5, 9968 /* *fields */ soc_IFP_SINGLE_WIDE_F1_7_BCM56840_A0fmt_fields, 9969 /* bits */ 39, 9970 /* flags */ 0, 9971 }, 9972 #endif /* chips */ 9973 9974 #if defined(BCM_56450_A0) 9975 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_7_BCM56450_A0fmt */ 9976 /* format IFP_SINGLE_WIDE_F1_7fmt */ 9977 /* nFields */ 6, 9978 /* *fields */ soc_IFP_SINGLE_WIDE_F1_7_BCM56450_A0fmt_fields, 9979 /* bits */ 40, 9980 /* flags */ 0, 9981 }, 9982 #endif /* chips */ 9983 9984 #if defined(BCM_56450_B0) 9985 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_7_BCM56450_B0fmt */ 9986 /* format IFP_SINGLE_WIDE_F1_7fmt */ 9987 /* nFields */ 6, 9988 /* *fields */ soc_IFP_SINGLE_WIDE_F1_7_BCM56450_A0fmt_fields, 9989 /* bits */ 40, 9990 /* flags */ 0, 9991 }, 9992 #endif /* chips */ 9993 9994 #if defined(BCM_56450_B1) 9995 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_7_BCM56450_B1fmt */ 9996 /* format IFP_SINGLE_WIDE_F1_7fmt */ 9997 /* nFields */ 6, 9998 /* *fields */ soc_IFP_SINGLE_WIDE_F1_7_BCM56450_A0fmt_fields, 9999 /* bits */ 40, 10000 /* flags */ 0, 10001 }, 10002 #endif /* chips */ 10003 10004 #if defined(BCM_56524_A0) 10005 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_7_BCM56524_A0fmt */ 10006 /* format IFP_SINGLE_WIDE_F1_7fmt */ 10007 /* nFields */ 5, 10008 /* *fields */ soc_IFP_SINGLE_WIDE_F1_7_BCM56634_A0fmt_fields, 10009 /* bits */ 37, 10010 /* flags */ 0, 10011 }, 10012 #endif /* chips */ 10013 10014 #if defined(BCM_56524_B0) 10015 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_7_BCM56524_B0fmt */ 10016 /* format IFP_SINGLE_WIDE_F1_7fmt */ 10017 /* nFields */ 5, 10018 /* *fields */ soc_IFP_SINGLE_WIDE_F1_7_BCM56634_A0fmt_fields, 10019 /* bits */ 37, 10020 /* flags */ 0, 10021 }, 10022 #endif /* chips */ 10023 10024 #if defined(BCM_56560_A0) 10025 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_7_BCM56560_A0fmt */ 10026 /* format IFP_SINGLE_WIDE_F1_7fmt */ 10027 /* nFields */ 5, 10028 /* *fields */ soc_IFP_SINGLE_WIDE_F1_7_BCM56560_A0fmt_fields, 10029 /* bits */ 50, 10030 /* flags */ 0, 10031 }, 10032 #endif /* chips */ 10033 10034 #if defined(BCM_56560_B0) 10035 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_7_BCM56560_B0fmt */ 10036 /* format IFP_SINGLE_WIDE_F1_7fmt */ 10037 /* nFields */ 5, 10038 /* *fields */ soc_IFP_SINGLE_WIDE_F1_7_BCM56560_A0fmt_fields, 10039 /* bits */ 50, 10040 /* flags */ 0, 10041 }, 10042 #endif /* chips */ 10043 10044 #if defined(BCM_56634_A0) 10045 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_7_BCM56634_A0fmt */ 10046 /* format IFP_SINGLE_WIDE_F1_7fmt */ 10047 /* nFields */ 5, 10048 /* *fields */ soc_IFP_SINGLE_WIDE_F1_7_BCM56634_A0fmt_fields, 10049 /* bits */ 37, 10050 /* flags */ 0, 10051 }, 10052 #endif /* chips */ 10053 10054 #if defined(BCM_56634_B0) 10055 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_7_BCM56634_B0fmt */ 10056 /* format IFP_SINGLE_WIDE_F1_7fmt */ 10057 /* nFields */ 5, 10058 /* *fields */ soc_IFP_SINGLE_WIDE_F1_7_BCM56634_A0fmt_fields, 10059 /* bits */ 37, 10060 /* flags */ 0, 10061 }, 10062 #endif /* chips */ 10063 10064 #if defined(BCM_56640_A0) 10065 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_7_BCM56640_A0fmt */ 10066 /* format IFP_SINGLE_WIDE_F1_7fmt */ 10067 /* nFields */ 5, 10068 /* *fields */ soc_IFP_SINGLE_WIDE_F1_7_BCM56640_A0fmt_fields, 10069 /* bits */ 49, 10070 /* flags */ 0, 10071 }, 10072 #endif /* chips */ 10073 10074 #if defined(BCM_56670_A0) 10075 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_7_BCM56670_A0fmt */ 10076 /* format IFP_SINGLE_WIDE_F1_7fmt */ 10077 /* nFields */ 5, 10078 /* *fields */ soc_IFP_SINGLE_WIDE_F1_7_BCM56560_A0fmt_fields, 10079 /* bits */ 50, 10080 /* flags */ 0, 10081 }, 10082 #endif /* chips */ 10083 10084 #if defined(BCM_56670_B0) 10085 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_7_BCM56670_B0fmt */ 10086 /* format IFP_SINGLE_WIDE_F1_7fmt */ 10087 /* nFields */ 5, 10088 /* *fields */ soc_IFP_SINGLE_WIDE_F1_7_BCM56560_A0fmt_fields, 10089 /* bits */ 50, 10090 /* flags */ 0, 10091 }, 10092 #endif /* chips */ 10093 10094 #if defined(BCM_56680_B0) 10095 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_7_BCM56680_B0fmt */ 10096 /* format IFP_SINGLE_WIDE_F1_7fmt */ 10097 /* nFields */ 4, 10098 /* *fields */ soc_IFP_SINGLE_WIDE_F1_7fmt_fields, 10099 /* bits */ 34, 10100 /* flags */ 0, 10101 }, 10102 #endif /* chips */ 10103 10104 #if defined(BCM_56685_A0) 10105 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_7_BCM56685_A0fmt */ 10106 /* format IFP_SINGLE_WIDE_F1_7fmt */ 10107 /* nFields */ 5, 10108 /* *fields */ soc_IFP_SINGLE_WIDE_F1_7_BCM56634_A0fmt_fields, 10109 /* bits */ 37, 10110 /* flags */ 0, 10111 }, 10112 #endif /* chips */ 10113 10114 #if defined(BCM_56685_B0) 10115 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_7_BCM56685_B0fmt */ 10116 /* format IFP_SINGLE_WIDE_F1_7fmt */ 10117 /* nFields */ 5, 10118 /* *fields */ soc_IFP_SINGLE_WIDE_F1_7_BCM56634_A0fmt_fields, 10119 /* bits */ 37, 10120 /* flags */ 0, 10121 }, 10122 #endif /* chips */ 10123 10124 #if defined(BCM_56725_A0) 10125 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_7_BCM56725_A0fmt */ 10126 /* format IFP_SINGLE_WIDE_F1_7fmt */ 10127 /* nFields */ 4, 10128 /* *fields */ soc_IFP_SINGLE_WIDE_F1_7fmt_fields, 10129 /* bits */ 34, 10130 /* flags */ 0, 10131 }, 10132 #endif /* chips */ 10133 10134 #if defined(BCM_56840_A0) 10135 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_7_BCM56840_A0fmt */ 10136 /* format IFP_SINGLE_WIDE_F1_7fmt */ 10137 /* nFields */ 5, 10138 /* *fields */ soc_IFP_SINGLE_WIDE_F1_7_BCM56840_A0fmt_fields, 10139 /* bits */ 39, 10140 /* flags */ 0, 10141 }, 10142 #endif /* chips */ 10143 10144 #if defined(BCM_56840_B0) 10145 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_7_BCM56840_B0fmt */ 10146 /* format IFP_SINGLE_WIDE_F1_7fmt */ 10147 /* nFields */ 5, 10148 /* *fields */ soc_IFP_SINGLE_WIDE_F1_7_BCM56840_A0fmt_fields, 10149 /* bits */ 39, 10150 /* flags */ 0, 10151 }, 10152 #endif /* chips */ 10153 10154 #if defined(BCM_56850_A0) 10155 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_7_BCM56850_A0fmt */ 10156 /* format IFP_SINGLE_WIDE_F1_7fmt */ 10157 /* nFields */ 5, 10158 /* *fields */ soc_IFP_SINGLE_WIDE_F1_7_BCM56850_A0fmt_fields, 10159 /* bits */ 49, 10160 /* flags */ 0, 10161 }, 10162 #endif /* chips */ 10163 10164 #if defined(BCM_56860_A0) 10165 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_7_BCM56860_A0fmt */ 10166 /* format IFP_SINGLE_WIDE_F1_7fmt */ 10167 /* nFields */ 5, 10168 /* *fields */ soc_IFP_SINGLE_WIDE_F1_7_BCM56860_A0fmt_fields, 10169 /* bits */ 50, 10170 /* flags */ 0, 10171 }, 10172 #endif /* chips */ 10173 10174 #if defined(BCM_53400_A0) 10175 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_8_BCM53400_A0fmt */ 10176 /* format IFP_SINGLE_WIDE_F1_8fmt */ 10177 /* nFields */ 6, 10178 /* *fields */ soc_IFP_SINGLE_WIDE_F1_8_BCM53400_A0fmt_fields, 10179 /* bits */ 37, 10180 /* flags */ 0, 10181 }, 10182 #endif /* chips */ 10183 10184 #if defined(BCM_53540_A0) 10185 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_8_BCM53540_A0fmt */ 10186 /* format IFP_SINGLE_WIDE_F1_8fmt */ 10187 /* nFields */ 6, 10188 /* *fields */ soc_IFP_SINGLE_WIDE_F1_8_BCM53400_A0fmt_fields, 10189 /* bits */ 37, 10190 /* flags */ 0, 10191 }, 10192 #endif /* chips */ 10193 10194 #if defined(BCM_53570_A0) 10195 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_8_BCM53570_A0fmt */ 10196 /* format IFP_SINGLE_WIDE_F1_8fmt */ 10197 /* nFields */ 6, 10198 /* *fields */ soc_IFP_SINGLE_WIDE_F1_8_BCM53570_A0fmt_fields, 10199 /* bits */ 39, 10200 /* flags */ 0, 10201 }, 10202 #endif /* chips */ 10203 10204 #if defined(BCM_53570_B0) 10205 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_8_BCM53570_B0fmt */ 10206 /* format IFP_SINGLE_WIDE_F1_8fmt */ 10207 /* nFields */ 6, 10208 /* *fields */ soc_IFP_SINGLE_WIDE_F1_8_BCM53570_A0fmt_fields, 10209 /* bits */ 39, 10210 /* flags */ 0, 10211 }, 10212 #endif /* chips */ 10213 10214 #if defined(BCM_56142_A0) 10215 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_8_BCM56142_A0fmt */ 10216 /* format IFP_SINGLE_WIDE_F1_8fmt */ 10217 /* nFields */ 5, 10218 /* *fields */ soc_IFP_SINGLE_WIDE_F1_8_BCM56634_A0fmt_fields, 10219 /* bits */ 37, 10220 /* flags */ 0, 10221 }, 10222 #endif /* chips */ 10223 10224 #if defined(BCM_56150_A0) 10225 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_8_BCM56150_A0fmt */ 10226 /* format IFP_SINGLE_WIDE_F1_8fmt */ 10227 /* nFields */ 5, 10228 /* *fields */ soc_IFP_SINGLE_WIDE_F1_8_BCM56150_A0fmt_fields, 10229 /* bits */ 37, 10230 /* flags */ 0, 10231 }, 10232 #endif /* chips */ 10233 10234 #if defined(BCM_56160_A0) 10235 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_8_BCM56160_A0fmt */ 10236 /* format IFP_SINGLE_WIDE_F1_8fmt */ 10237 /* nFields */ 6, 10238 /* *fields */ soc_IFP_SINGLE_WIDE_F1_8_BCM53400_A0fmt_fields, 10239 /* bits */ 37, 10240 /* flags */ 0, 10241 }, 10242 #endif /* chips */ 10243 10244 #if defined(BCM_56260_A0) 10245 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_8_BCM56260_A0fmt */ 10246 /* format IFP_SINGLE_WIDE_F1_8fmt */ 10247 /* nFields */ 5, 10248 /* *fields */ soc_IFP_SINGLE_WIDE_F1_8_BCM56260_A0fmt_fields, 10249 /* bits */ 40, 10250 /* flags */ 0, 10251 }, 10252 #endif /* chips */ 10253 10254 #if defined(BCM_56260_B0) 10255 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_8_BCM56260_B0fmt */ 10256 /* format IFP_SINGLE_WIDE_F1_8fmt */ 10257 /* nFields */ 5, 10258 /* *fields */ soc_IFP_SINGLE_WIDE_F1_8_BCM56260_A0fmt_fields, 10259 /* bits */ 40, 10260 /* flags */ 0, 10261 }, 10262 #endif /* chips */ 10263 10264 #if defined(BCM_56270_A0) 10265 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_8_BCM56270_A0fmt */ 10266 /* format IFP_SINGLE_WIDE_F1_8fmt */ 10267 /* nFields */ 5, 10268 /* *fields */ soc_IFP_SINGLE_WIDE_F1_8_BCM56260_A0fmt_fields, 10269 /* bits */ 40, 10270 /* flags */ 0, 10271 }, 10272 #endif /* chips */ 10273 10274 #if defined(BCM_56334_A0) 10275 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_8_BCM56334_A0fmt */ 10276 /* format IFP_SINGLE_WIDE_F1_8fmt */ 10277 /* nFields */ 5, 10278 /* *fields */ soc_IFP_SINGLE_WIDE_F1_8_BCM56634_A0fmt_fields, 10279 /* bits */ 37, 10280 /* flags */ 0, 10281 }, 10282 #endif /* chips */ 10283 10284 #if defined(BCM_56334_B0) 10285 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_8_BCM56334_B0fmt */ 10286 /* format IFP_SINGLE_WIDE_F1_8fmt */ 10287 /* nFields */ 5, 10288 /* *fields */ soc_IFP_SINGLE_WIDE_F1_8_BCM56634_A0fmt_fields, 10289 /* bits */ 37, 10290 /* flags */ 0, 10291 }, 10292 #endif /* chips */ 10293 10294 #if defined(BCM_56340_A0) 10295 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_8_BCM56340_A0fmt */ 10296 /* format IFP_SINGLE_WIDE_F1_8fmt */ 10297 /* nFields */ 8, 10298 /* *fields */ soc_IFP_SINGLE_WIDE_F1_8_BCM56640_A0fmt_fields, 10299 /* bits */ 49, 10300 /* flags */ 0, 10301 }, 10302 #endif /* chips */ 10303 10304 #if defined(BCM_56440_A0) 10305 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_8_BCM56440_A0fmt */ 10306 /* format IFP_SINGLE_WIDE_F1_8fmt */ 10307 /* nFields */ 5, 10308 /* *fields */ soc_IFP_SINGLE_WIDE_F1_8_BCM56440_A0fmt_fields, 10309 /* bits */ 39, 10310 /* flags */ 0, 10311 }, 10312 #endif /* chips */ 10313 10314 #if defined(BCM_56440_B0) 10315 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_8_BCM56440_B0fmt */ 10316 /* format IFP_SINGLE_WIDE_F1_8fmt */ 10317 /* nFields */ 5, 10318 /* *fields */ soc_IFP_SINGLE_WIDE_F1_8_BCM56440_A0fmt_fields, 10319 /* bits */ 39, 10320 /* flags */ 0, 10321 }, 10322 #endif /* chips */ 10323 10324 #if defined(BCM_56450_A0) 10325 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_8_BCM56450_A0fmt */ 10326 /* format IFP_SINGLE_WIDE_F1_8fmt */ 10327 /* nFields */ 5, 10328 /* *fields */ soc_IFP_SINGLE_WIDE_F1_8_BCM56450_A0fmt_fields, 10329 /* bits */ 40, 10330 /* flags */ 0, 10331 }, 10332 #endif /* chips */ 10333 10334 #if defined(BCM_56450_B0) 10335 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_8_BCM56450_B0fmt */ 10336 /* format IFP_SINGLE_WIDE_F1_8fmt */ 10337 /* nFields */ 5, 10338 /* *fields */ soc_IFP_SINGLE_WIDE_F1_8_BCM56450_A0fmt_fields, 10339 /* bits */ 40, 10340 /* flags */ 0, 10341 }, 10342 #endif /* chips */ 10343 10344 #if defined(BCM_56450_B1) 10345 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_8_BCM56450_B1fmt */ 10346 /* format IFP_SINGLE_WIDE_F1_8fmt */ 10347 /* nFields */ 5, 10348 /* *fields */ soc_IFP_SINGLE_WIDE_F1_8_BCM56450_A0fmt_fields, 10349 /* bits */ 40, 10350 /* flags */ 0, 10351 }, 10352 #endif /* chips */ 10353 10354 #if defined(BCM_56524_A0) 10355 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_8_BCM56524_A0fmt */ 10356 /* format IFP_SINGLE_WIDE_F1_8fmt */ 10357 /* nFields */ 5, 10358 /* *fields */ soc_IFP_SINGLE_WIDE_F1_8_BCM56634_A0fmt_fields, 10359 /* bits */ 37, 10360 /* flags */ 0, 10361 }, 10362 #endif /* chips */ 10363 10364 #if defined(BCM_56524_B0) 10365 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_8_BCM56524_B0fmt */ 10366 /* format IFP_SINGLE_WIDE_F1_8fmt */ 10367 /* nFields */ 5, 10368 /* *fields */ soc_IFP_SINGLE_WIDE_F1_8_BCM56634_A0fmt_fields, 10369 /* bits */ 37, 10370 /* flags */ 0, 10371 }, 10372 #endif /* chips */ 10373 10374 #if defined(BCM_56560_A0) 10375 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_8_BCM56560_A0fmt */ 10376 /* format IFP_SINGLE_WIDE_F1_8fmt */ 10377 /* nFields */ 12, 10378 /* *fields */ soc_IFP_SINGLE_WIDE_F1_8_BCM56560_A0fmt_fields, 10379 /* bits */ 50, 10380 /* flags */ 0, 10381 }, 10382 #endif /* chips */ 10383 10384 #if defined(BCM_56560_B0) 10385 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_8_BCM56560_B0fmt */ 10386 /* format IFP_SINGLE_WIDE_F1_8fmt */ 10387 /* nFields */ 12, 10388 /* *fields */ soc_IFP_SINGLE_WIDE_F1_8_BCM56560_A0fmt_fields, 10389 /* bits */ 50, 10390 /* flags */ 0, 10391 }, 10392 #endif /* chips */ 10393 10394 #if defined(BCM_56634_A0) 10395 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_8_BCM56634_A0fmt */ 10396 /* format IFP_SINGLE_WIDE_F1_8fmt */ 10397 /* nFields */ 5, 10398 /* *fields */ soc_IFP_SINGLE_WIDE_F1_8_BCM56634_A0fmt_fields, 10399 /* bits */ 37, 10400 /* flags */ 0, 10401 }, 10402 #endif /* chips */ 10403 10404 #if defined(BCM_56634_B0) 10405 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_8_BCM56634_B0fmt */ 10406 /* format IFP_SINGLE_WIDE_F1_8fmt */ 10407 /* nFields */ 5, 10408 /* *fields */ soc_IFP_SINGLE_WIDE_F1_8_BCM56634_A0fmt_fields, 10409 /* bits */ 37, 10410 /* flags */ 0, 10411 }, 10412 #endif /* chips */ 10413 10414 #if defined(BCM_56640_A0) 10415 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_8_BCM56640_A0fmt */ 10416 /* format IFP_SINGLE_WIDE_F1_8fmt */ 10417 /* nFields */ 8, 10418 /* *fields */ soc_IFP_SINGLE_WIDE_F1_8_BCM56640_A0fmt_fields, 10419 /* bits */ 49, 10420 /* flags */ 0, 10421 }, 10422 #endif /* chips */ 10423 10424 #if defined(BCM_56670_A0) 10425 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_8_BCM56670_A0fmt */ 10426 /* format IFP_SINGLE_WIDE_F1_8fmt */ 10427 /* nFields */ 12, 10428 /* *fields */ soc_IFP_SINGLE_WIDE_F1_8_BCM56560_A0fmt_fields, 10429 /* bits */ 50, 10430 /* flags */ 0, 10431 }, 10432 #endif /* chips */ 10433 10434 #if defined(BCM_56670_B0) 10435 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_8_BCM56670_B0fmt */ 10436 /* format IFP_SINGLE_WIDE_F1_8fmt */ 10437 /* nFields */ 12, 10438 /* *fields */ soc_IFP_SINGLE_WIDE_F1_8_BCM56560_A0fmt_fields, 10439 /* bits */ 50, 10440 /* flags */ 0, 10441 }, 10442 #endif /* chips */ 10443 10444 #if defined(BCM_56680_B0) 10445 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_8_BCM56680_B0fmt */ 10446 /* format IFP_SINGLE_WIDE_F1_8fmt */ 10447 /* nFields */ 5, 10448 /* *fields */ soc_IFP_SINGLE_WIDE_F1_8fmt_fields, 10449 /* bits */ 34, 10450 /* flags */ 0, 10451 }, 10452 #endif /* chips */ 10453 10454 #if defined(BCM_56685_A0) 10455 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_8_BCM56685_A0fmt */ 10456 /* format IFP_SINGLE_WIDE_F1_8fmt */ 10457 /* nFields */ 5, 10458 /* *fields */ soc_IFP_SINGLE_WIDE_F1_8_BCM56634_A0fmt_fields, 10459 /* bits */ 37, 10460 /* flags */ 0, 10461 }, 10462 #endif /* chips */ 10463 10464 #if defined(BCM_56685_B0) 10465 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_8_BCM56685_B0fmt */ 10466 /* format IFP_SINGLE_WIDE_F1_8fmt */ 10467 /* nFields */ 5, 10468 /* *fields */ soc_IFP_SINGLE_WIDE_F1_8_BCM56634_A0fmt_fields, 10469 /* bits */ 37, 10470 /* flags */ 0, 10471 }, 10472 #endif /* chips */ 10473 10474 #if defined(BCM_56725_A0) 10475 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_8_BCM56725_A0fmt */ 10476 /* format IFP_SINGLE_WIDE_F1_8fmt */ 10477 /* nFields */ 5, 10478 /* *fields */ soc_IFP_SINGLE_WIDE_F1_8fmt_fields, 10479 /* bits */ 34, 10480 /* flags */ 0, 10481 }, 10482 #endif /* chips */ 10483 10484 #if defined(BCM_56840_A0) 10485 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_8_BCM56840_A0fmt */ 10486 /* format IFP_SINGLE_WIDE_F1_8fmt */ 10487 /* nFields */ 5, 10488 /* *fields */ soc_IFP_SINGLE_WIDE_F1_8_BCM56840_A0fmt_fields, 10489 /* bits */ 39, 10490 /* flags */ 0, 10491 }, 10492 #endif /* chips */ 10493 10494 #if defined(BCM_56840_B0) 10495 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_8_BCM56840_B0fmt */ 10496 /* format IFP_SINGLE_WIDE_F1_8fmt */ 10497 /* nFields */ 5, 10498 /* *fields */ soc_IFP_SINGLE_WIDE_F1_8_BCM56840_A0fmt_fields, 10499 /* bits */ 39, 10500 /* flags */ 0, 10501 }, 10502 #endif /* chips */ 10503 10504 #if defined(BCM_56850_A0) 10505 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_8_BCM56850_A0fmt */ 10506 /* format IFP_SINGLE_WIDE_F1_8fmt */ 10507 /* nFields */ 12, 10508 /* *fields */ soc_IFP_SINGLE_WIDE_F1_8_BCM56850_A0fmt_fields, 10509 /* bits */ 49, 10510 /* flags */ 0, 10511 }, 10512 #endif /* chips */ 10513 10514 #if defined(BCM_56860_A0) 10515 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_8_BCM56860_A0fmt */ 10516 /* format IFP_SINGLE_WIDE_F1_8fmt */ 10517 /* nFields */ 12, 10518 /* *fields */ soc_IFP_SINGLE_WIDE_F1_8_BCM56860_A0fmt_fields, 10519 /* bits */ 50, 10520 /* flags */ 0, 10521 }, 10522 #endif /* chips */ 10523 10524 #if defined(BCM_88732_A0) 10525 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_8_BCM88732_A0fmt */ 10526 /* format IFP_SINGLE_WIDE_F1_8fmt */ 10527 /* nFields */ 4, 10528 /* *fields */ soc_IFP_SINGLE_WIDE_F1_8_BCM88732_A0fmt_fields, 10529 /* bits */ 34, 10530 /* flags */ 0, 10531 }, 10532 #endif /* chips */ 10533 10534 #if defined(BCM_53400_A0) 10535 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_9_BCM53400_A0fmt */ 10536 /* format IFP_SINGLE_WIDE_F1_9fmt */ 10537 /* nFields */ 3, 10538 /* *fields */ soc_IFP_SINGLE_WIDE_F1_9_BCM53400_A0fmt_fields, 10539 /* bits */ 37, 10540 /* flags */ 0, 10541 }, 10542 #endif /* chips */ 10543 10544 #if defined(BCM_53540_A0) 10545 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_9_BCM53540_A0fmt */ 10546 /* format IFP_SINGLE_WIDE_F1_9fmt */ 10547 /* nFields */ 3, 10548 /* *fields */ soc_IFP_SINGLE_WIDE_F1_9_BCM53400_A0fmt_fields, 10549 /* bits */ 37, 10550 /* flags */ 0, 10551 }, 10552 #endif /* chips */ 10553 10554 #if defined(BCM_53570_A0) 10555 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_9_BCM53570_A0fmt */ 10556 /* format IFP_SINGLE_WIDE_F1_9fmt */ 10557 /* nFields */ 3, 10558 /* *fields */ soc_IFP_SINGLE_WIDE_F1_9_BCM53570_A0fmt_fields, 10559 /* bits */ 39, 10560 /* flags */ 0, 10561 }, 10562 #endif /* chips */ 10563 10564 #if defined(BCM_53570_B0) 10565 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_9_BCM53570_B0fmt */ 10566 /* format IFP_SINGLE_WIDE_F1_9fmt */ 10567 /* nFields */ 3, 10568 /* *fields */ soc_IFP_SINGLE_WIDE_F1_9_BCM53570_A0fmt_fields, 10569 /* bits */ 39, 10570 /* flags */ 0, 10571 }, 10572 #endif /* chips */ 10573 10574 #if defined(BCM_56142_A0) 10575 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_9_BCM56142_A0fmt */ 10576 /* format IFP_SINGLE_WIDE_F1_9fmt */ 10577 /* nFields */ 3, 10578 /* *fields */ soc_IFP_SINGLE_WIDE_F1_9_BCM56334_A0fmt_fields, 10579 /* bits */ 37, 10580 /* flags */ 0, 10581 }, 10582 #endif /* chips */ 10583 10584 #if defined(BCM_56150_A0) 10585 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_9_BCM56150_A0fmt */ 10586 /* format IFP_SINGLE_WIDE_F1_9fmt */ 10587 /* nFields */ 3, 10588 /* *fields */ soc_IFP_SINGLE_WIDE_F1_9_BCM56150_A0fmt_fields, 10589 /* bits */ 37, 10590 /* flags */ 0, 10591 }, 10592 #endif /* chips */ 10593 10594 #if defined(BCM_56160_A0) 10595 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_9_BCM56160_A0fmt */ 10596 /* format IFP_SINGLE_WIDE_F1_9fmt */ 10597 /* nFields */ 3, 10598 /* *fields */ soc_IFP_SINGLE_WIDE_F1_9_BCM53400_A0fmt_fields, 10599 /* bits */ 37, 10600 /* flags */ 0, 10601 }, 10602 #endif /* chips */ 10603 10604 #if defined(BCM_56260_A0) 10605 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_9_BCM56260_A0fmt */ 10606 /* format IFP_SINGLE_WIDE_F1_9fmt */ 10607 /* nFields */ 5, 10608 /* *fields */ soc_IFP_SINGLE_WIDE_F1_9_BCM56260_A0fmt_fields, 10609 /* bits */ 40, 10610 /* flags */ 0, 10611 }, 10612 #endif /* chips */ 10613 10614 #if defined(BCM_56260_B0) 10615 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_9_BCM56260_B0fmt */ 10616 /* format IFP_SINGLE_WIDE_F1_9fmt */ 10617 /* nFields */ 5, 10618 /* *fields */ soc_IFP_SINGLE_WIDE_F1_9_BCM56260_A0fmt_fields, 10619 /* bits */ 40, 10620 /* flags */ 0, 10621 }, 10622 #endif /* chips */ 10623 10624 #if defined(BCM_56270_A0) 10625 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_9_BCM56270_A0fmt */ 10626 /* format IFP_SINGLE_WIDE_F1_9fmt */ 10627 /* nFields */ 5, 10628 /* *fields */ soc_IFP_SINGLE_WIDE_F1_9_BCM56260_A0fmt_fields, 10629 /* bits */ 40, 10630 /* flags */ 0, 10631 }, 10632 #endif /* chips */ 10633 10634 #if defined(BCM_56334_A0) 10635 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_9_BCM56334_A0fmt */ 10636 /* format IFP_SINGLE_WIDE_F1_9fmt */ 10637 /* nFields */ 3, 10638 /* *fields */ soc_IFP_SINGLE_WIDE_F1_9_BCM56334_A0fmt_fields, 10639 /* bits */ 37, 10640 /* flags */ 0, 10641 }, 10642 #endif /* chips */ 10643 10644 #if defined(BCM_56334_B0) 10645 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_9_BCM56334_B0fmt */ 10646 /* format IFP_SINGLE_WIDE_F1_9fmt */ 10647 /* nFields */ 3, 10648 /* *fields */ soc_IFP_SINGLE_WIDE_F1_9_BCM56334_A0fmt_fields, 10649 /* bits */ 37, 10650 /* flags */ 0, 10651 }, 10652 #endif /* chips */ 10653 10654 #if defined(BCM_56340_A0) 10655 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_9_BCM56340_A0fmt */ 10656 /* format IFP_SINGLE_WIDE_F1_9fmt */ 10657 /* nFields */ 4, 10658 /* *fields */ soc_IFP_SINGLE_WIDE_F1_9_BCM56640_A0fmt_fields, 10659 /* bits */ 49, 10660 /* flags */ 0, 10661 }, 10662 #endif /* chips */ 10663 10664 #if defined(BCM_56440_A0) 10665 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_9_BCM56440_A0fmt */ 10666 /* format IFP_SINGLE_WIDE_F1_9fmt */ 10667 /* nFields */ 4, 10668 /* *fields */ soc_IFP_SINGLE_WIDE_F1_9_BCM56840_A0fmt_fields, 10669 /* bits */ 39, 10670 /* flags */ 0, 10671 }, 10672 #endif /* chips */ 10673 10674 #if defined(BCM_56440_B0) 10675 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_9_BCM56440_B0fmt */ 10676 /* format IFP_SINGLE_WIDE_F1_9fmt */ 10677 /* nFields */ 4, 10678 /* *fields */ soc_IFP_SINGLE_WIDE_F1_9_BCM56840_A0fmt_fields, 10679 /* bits */ 39, 10680 /* flags */ 0, 10681 }, 10682 #endif /* chips */ 10683 10684 #if defined(BCM_56450_A0) 10685 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_9_BCM56450_A0fmt */ 10686 /* format IFP_SINGLE_WIDE_F1_9fmt */ 10687 /* nFields */ 5, 10688 /* *fields */ soc_IFP_SINGLE_WIDE_F1_9_BCM56450_A0fmt_fields, 10689 /* bits */ 40, 10690 /* flags */ 0, 10691 }, 10692 #endif /* chips */ 10693 10694 #if defined(BCM_56450_B0) 10695 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_9_BCM56450_B0fmt */ 10696 /* format IFP_SINGLE_WIDE_F1_9fmt */ 10697 /* nFields */ 5, 10698 /* *fields */ soc_IFP_SINGLE_WIDE_F1_9_BCM56450_A0fmt_fields, 10699 /* bits */ 40, 10700 /* flags */ 0, 10701 }, 10702 #endif /* chips */ 10703 10704 #if defined(BCM_56450_B1) 10705 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_9_BCM56450_B1fmt */ 10706 /* format IFP_SINGLE_WIDE_F1_9fmt */ 10707 /* nFields */ 5, 10708 /* *fields */ soc_IFP_SINGLE_WIDE_F1_9_BCM56450_A0fmt_fields, 10709 /* bits */ 40, 10710 /* flags */ 0, 10711 }, 10712 #endif /* chips */ 10713 10714 #if defined(BCM_56524_B0) 10715 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_9_BCM56524_B0fmt */ 10716 /* format IFP_SINGLE_WIDE_F1_9fmt */ 10717 /* nFields */ 4, 10718 /* *fields */ soc_IFP_SINGLE_WIDE_F1_9fmt_fields, 10719 /* bits */ 37, 10720 /* flags */ 0, 10721 }, 10722 #endif /* chips */ 10723 10724 #if defined(BCM_56560_A0) 10725 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_9_BCM56560_A0fmt */ 10726 /* format IFP_SINGLE_WIDE_F1_9fmt */ 10727 /* nFields */ 4, 10728 /* *fields */ soc_IFP_SINGLE_WIDE_F1_9_BCM56560_A0fmt_fields, 10729 /* bits */ 50, 10730 /* flags */ 0, 10731 }, 10732 #endif /* chips */ 10733 10734 #if defined(BCM_56560_B0) 10735 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_9_BCM56560_B0fmt */ 10736 /* format IFP_SINGLE_WIDE_F1_9fmt */ 10737 /* nFields */ 4, 10738 /* *fields */ soc_IFP_SINGLE_WIDE_F1_9_BCM56560_A0fmt_fields, 10739 /* bits */ 50, 10740 /* flags */ 0, 10741 }, 10742 #endif /* chips */ 10743 10744 #if defined(BCM_56640_A0) 10745 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_9_BCM56640_A0fmt */ 10746 /* format IFP_SINGLE_WIDE_F1_9fmt */ 10747 /* nFields */ 4, 10748 /* *fields */ soc_IFP_SINGLE_WIDE_F1_9_BCM56640_A0fmt_fields, 10749 /* bits */ 49, 10750 /* flags */ 0, 10751 }, 10752 #endif /* chips */ 10753 10754 #if defined(BCM_56670_A0) 10755 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_9_BCM56670_A0fmt */ 10756 /* format IFP_SINGLE_WIDE_F1_9fmt */ 10757 /* nFields */ 4, 10758 /* *fields */ soc_IFP_SINGLE_WIDE_F1_9_BCM56560_A0fmt_fields, 10759 /* bits */ 50, 10760 /* flags */ 0, 10761 }, 10762 #endif /* chips */ 10763 10764 #if defined(BCM_56670_B0) 10765 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_9_BCM56670_B0fmt */ 10766 /* format IFP_SINGLE_WIDE_F1_9fmt */ 10767 /* nFields */ 4, 10768 /* *fields */ soc_IFP_SINGLE_WIDE_F1_9_BCM56560_A0fmt_fields, 10769 /* bits */ 50, 10770 /* flags */ 0, 10771 }, 10772 #endif /* chips */ 10773 10774 #if defined(BCM_56685_A0) 10775 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_9_BCM56685_A0fmt */ 10776 /* format IFP_SINGLE_WIDE_F1_9fmt */ 10777 /* nFields */ 4, 10778 /* *fields */ soc_IFP_SINGLE_WIDE_F1_9fmt_fields, 10779 /* bits */ 37, 10780 /* flags */ 0, 10781 }, 10782 #endif /* chips */ 10783 10784 #if defined(BCM_56685_B0) 10785 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_9_BCM56685_B0fmt */ 10786 /* format IFP_SINGLE_WIDE_F1_9fmt */ 10787 /* nFields */ 4, 10788 /* *fields */ soc_IFP_SINGLE_WIDE_F1_9fmt_fields, 10789 /* bits */ 37, 10790 /* flags */ 0, 10791 }, 10792 #endif /* chips */ 10793 10794 #if defined(BCM_56840_A0) 10795 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_9_BCM56840_A0fmt */ 10796 /* format IFP_SINGLE_WIDE_F1_9fmt */ 10797 /* nFields */ 4, 10798 /* *fields */ soc_IFP_SINGLE_WIDE_F1_9_BCM56840_A0fmt_fields, 10799 /* bits */ 39, 10800 /* flags */ 0, 10801 }, 10802 #endif /* chips */ 10803 10804 #if defined(BCM_56840_B0) 10805 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_9_BCM56840_B0fmt */ 10806 /* format IFP_SINGLE_WIDE_F1_9fmt */ 10807 /* nFields */ 4, 10808 /* *fields */ soc_IFP_SINGLE_WIDE_F1_9_BCM56840_A0fmt_fields, 10809 /* bits */ 39, 10810 /* flags */ 0, 10811 }, 10812 #endif /* chips */ 10813 10814 #if defined(BCM_56850_A0) 10815 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_9_BCM56850_A0fmt */ 10816 /* format IFP_SINGLE_WIDE_F1_9fmt */ 10817 /* nFields */ 4, 10818 /* *fields */ soc_IFP_SINGLE_WIDE_F1_9_BCM56850_A0fmt_fields, 10819 /* bits */ 49, 10820 /* flags */ 0, 10821 }, 10822 #endif /* chips */ 10823 10824 #if defined(BCM_56860_A0) 10825 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F1_9_BCM56860_A0fmt */ 10826 /* format IFP_SINGLE_WIDE_F1_9fmt */ 10827 /* nFields */ 4, 10828 /* *fields */ soc_IFP_SINGLE_WIDE_F1_9_BCM56860_A0fmt_fields, 10829 /* bits */ 50, 10830 /* flags */ 0, 10831 }, 10832 #endif /* chips */ 10833 10834 #if defined(BCM_56334_B0) || defined(BCM_56440_A0) || \ 10835 defined(BCM_56440_B0) || defined(BCM_56524_A0) || \ 10836 defined(BCM_56524_B0) || defined(BCM_56624_A0) || \ 10837 defined(BCM_56624_B0) || defined(BCM_56634_A0) || \ 10838 defined(BCM_56634_B0) || defined(BCM_56680_A0) || \ 10839 defined(BCM_56685_A0) || defined(BCM_56725_A0) || \ 10840 defined(BCM_56820_A0) 10841 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_0fmt */ 10842 /* format IFP_SINGLE_WIDE_F2_0fmt */ 10843 /* nFields */ 9, 10844 /* *fields */ soc_IFP_SINGLE_WIDE_F2_0fmt_fields, 10845 /* bits */ 128, 10846 /* flags */ 0, 10847 }, 10848 #endif /* chips */ 10849 10850 #if defined(BCM_56334_B0) || defined(BCM_56440_A0) || \ 10851 defined(BCM_56440_B0) || defined(BCM_56524_A0) || \ 10852 defined(BCM_56524_B0) || defined(BCM_56624_A0) || \ 10853 defined(BCM_56624_B0) || defined(BCM_56634_A0) || \ 10854 defined(BCM_56634_B0) || defined(BCM_56680_A0) || \ 10855 defined(BCM_56685_A0) || defined(BCM_56725_A0) || \ 10856 defined(BCM_56820_A0) 10857 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_1fmt */ 10858 /* format IFP_SINGLE_WIDE_F2_1fmt */ 10859 /* nFields */ 9, 10860 /* *fields */ soc_IFP_SINGLE_WIDE_F2_1fmt_fields, 10861 /* bits */ 128, 10862 /* flags */ 0, 10863 }, 10864 #endif /* chips */ 10865 10866 #if defined(BCM_56624_A0) 10867 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_2fmt */ 10868 /* format IFP_SINGLE_WIDE_F2_2fmt */ 10869 /* nFields */ 1, 10870 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_1fmt_fields, 10871 /* bits */ 128, 10872 /* flags */ 0, 10873 }, 10874 #endif /* chips */ 10875 10876 #if defined(BCM_56142_A0) || defined(BCM_56334_B0) || \ 10877 defined(BCM_56440_A0) || defined(BCM_56440_B0) || \ 10878 defined(BCM_56524_A0) || defined(BCM_56524_B0) || \ 10879 defined(BCM_56624_A0) || defined(BCM_56624_B0) || \ 10880 defined(BCM_56634_A0) || defined(BCM_56634_B0) || \ 10881 defined(BCM_56680_A0) || defined(BCM_56685_A0) || \ 10882 defined(BCM_56725_A0) || defined(BCM_56820_A0) || \ 10883 defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 10884 defined(BCM_88732_A0) 10885 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_3fmt */ 10886 /* format IFP_SINGLE_WIDE_F2_3fmt */ 10887 /* nFields */ 1, 10888 /* *fields */ soc_IFP_SINGLE_WIDE_F2_3fmt_fields, 10889 /* bits */ 128, 10890 /* flags */ 0, 10891 }, 10892 #endif /* chips */ 10893 10894 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \ 10895 defined(BCM_56680_A0) || defined(BCM_56725_A0) || \ 10896 defined(BCM_56820_A0) 10897 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_4fmt */ 10898 /* format IFP_SINGLE_WIDE_F2_4fmt */ 10899 /* nFields */ 7, 10900 /* *fields */ soc_IFP_SINGLE_WIDE_F2_4fmt_fields, 10901 /* bits */ 128, 10902 /* flags */ 0, 10903 }, 10904 #endif /* chips */ 10905 10906 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \ 10907 defined(BCM_56524_A0) || defined(BCM_56524_B0) || \ 10908 defined(BCM_56624_A0) || defined(BCM_56624_B0) || \ 10909 defined(BCM_56634_A0) || defined(BCM_56634_B0) || \ 10910 defined(BCM_56680_A0) || defined(BCM_56685_A0) || \ 10911 defined(BCM_56725_A0) || defined(BCM_56820_A0) || \ 10912 defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 10913 defined(BCM_88732_A0) 10914 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_5fmt */ 10915 /* format IFP_SINGLE_WIDE_F2_5fmt */ 10916 /* nFields */ 4, 10917 /* *fields */ soc_IFP_SINGLE_WIDE_F2_5fmt_fields, 10918 /* bits */ 128, 10919 /* flags */ 0, 10920 }, 10921 #endif /* chips */ 10922 10923 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \ 10924 defined(BCM_56680_A0) || defined(BCM_56725_A0) || \ 10925 defined(BCM_56820_A0) 10926 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_6fmt */ 10927 /* format IFP_SINGLE_WIDE_F2_6fmt */ 10928 /* nFields */ 5, 10929 /* *fields */ soc_IFP_SINGLE_WIDE_F2_6fmt_fields, 10930 /* bits */ 128, 10931 /* flags */ 0, 10932 }, 10933 #endif /* chips */ 10934 10935 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \ 10936 defined(BCM_56680_A0) || defined(BCM_56725_A0) || \ 10937 defined(BCM_56820_A0) 10938 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_7fmt */ 10939 /* format IFP_SINGLE_WIDE_F2_7fmt */ 10940 /* nFields */ 5, 10941 /* *fields */ soc_IFP_SINGLE_WIDE_F2_7fmt_fields, 10942 /* bits */ 128, 10943 /* flags */ 0, 10944 }, 10945 #endif /* chips */ 10946 10947 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \ 10948 defined(BCM_56334_B0) || defined(BCM_56440_A0) || \ 10949 defined(BCM_56440_B0) || defined(BCM_56524_A0) || \ 10950 defined(BCM_56524_B0) || defined(BCM_56624_A0) || \ 10951 defined(BCM_56624_B0) || defined(BCM_56634_B0) || \ 10952 defined(BCM_56680_A0) || defined(BCM_56680_B0) || \ 10953 defined(BCM_56685_A0) || defined(BCM_56685_B0) || \ 10954 defined(BCM_56725_A0) || defined(BCM_56820_A0) || \ 10955 defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 10956 defined(BCM_88732_A0) 10957 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_8fmt */ 10958 /* format IFP_SINGLE_WIDE_F2_8fmt */ 10959 /* nFields */ 1, 10960 /* *fields */ soc_IFP_SINGLE_WIDE_F2_8fmt_fields, 10961 /* bits */ 128, 10962 /* flags */ 0, 10963 }, 10964 #endif /* chips */ 10965 10966 #if defined(BCM_56624_A0) 10967 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_9fmt */ 10968 /* format IFP_SINGLE_WIDE_F2_9fmt */ 10969 /* nFields */ 1, 10970 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_2fmt_fields, 10971 /* bits */ 128, 10972 /* flags */ 0, 10973 }, 10974 #endif /* chips */ 10975 10976 #if defined(BCM_56142_A0) || defined(BCM_56334_B0) || \ 10977 defined(BCM_56440_A0) || defined(BCM_56440_B0) || \ 10978 defined(BCM_56524_A0) || defined(BCM_56524_B0) || \ 10979 defined(BCM_56624_A0) || defined(BCM_56624_B0) || \ 10980 defined(BCM_56634_A0) || defined(BCM_56634_B0) || \ 10981 defined(BCM_56680_A0) || defined(BCM_56685_A0) || \ 10982 defined(BCM_56725_A0) || defined(BCM_56820_A0) || \ 10983 defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 10984 defined(BCM_88732_A0) 10985 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_10fmt */ 10986 /* format IFP_SINGLE_WIDE_F2_10fmt */ 10987 /* nFields */ 2, 10988 /* *fields */ soc_IFP_SINGLE_WIDE_F2_10fmt_fields, 10989 /* bits */ 128, 10990 /* flags */ 0, 10991 }, 10992 #endif /* chips */ 10993 10994 #if defined(BCM_56334_B0) || defined(BCM_56440_A0) || \ 10995 defined(BCM_56440_B0) || defined(BCM_56524_A0) || \ 10996 defined(BCM_56524_B0) || defined(BCM_56634_A0) || \ 10997 defined(BCM_56634_B0) || defined(BCM_56685_A0) || \ 10998 defined(BCM_56840_A0) || defined(BCM_56840_B0) 10999 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_11fmt */ 11000 /* format IFP_SINGLE_WIDE_F2_11fmt */ 11001 /* nFields */ 3, 11002 /* *fields */ soc_IFP_SINGLE_WIDE_F2_11fmt_fields, 11003 /* bits */ 128, 11004 /* flags */ 0, 11005 }, 11006 #endif /* chips */ 11007 11008 #if defined(BCM_56850_A0) || defined(BCM_56860_A0) 11009 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_12fmt */ 11010 /* format IFP_SINGLE_WIDE_F2_12fmt */ 11011 /* nFields */ 8, 11012 /* *fields */ soc_IFP_SINGLE_WIDE_F2_12fmt_fields, 11013 /* bits */ 128, 11014 /* flags */ 0, 11015 }, 11016 #endif /* chips */ 11017 11018 #if defined(BCM_56160_A0) 11019 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_13fmt */ 11020 /* format IFP_SINGLE_WIDE_F2_13fmt */ 11021 /* nFields */ 4, 11022 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_4fmt_fields, 11023 /* bits */ 128, 11024 /* flags */ 0, 11025 }, 11026 #endif /* chips */ 11027 11028 #if defined(BCM_56160_A0) 11029 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_14fmt */ 11030 /* format IFP_SINGLE_WIDE_F2_14fmt */ 11031 /* nFields */ 7, 11032 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_5fmt_fields, 11033 /* bits */ 128, 11034 /* flags */ 0, 11035 }, 11036 #endif /* chips */ 11037 11038 #if defined(BCM_56160_A0) 11039 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_15fmt */ 11040 /* format IFP_SINGLE_WIDE_F2_15fmt */ 11041 /* nFields */ 1, 11042 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_6fmt_fields, 11043 /* bits */ 128, 11044 /* flags */ 0, 11045 }, 11046 #endif /* chips */ 11047 11048 #if defined(BCM_56160_A0) 11049 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_16fmt */ 11050 /* format IFP_SINGLE_WIDE_F2_16fmt */ 11051 /* nFields */ 1, 11052 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_7fmt_fields, 11053 /* bits */ 128, 11054 /* flags */ 0, 11055 }, 11056 #endif /* chips */ 11057 11058 #if defined(BCM_53570_A0) 11059 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_17fmt */ 11060 /* format IFP_SINGLE_WIDE_F2_17fmt */ 11061 /* nFields */ 36, 11062 /* *fields */ soc_IFP_SINGLE_WIDE_F2_17fmt_fields, 11063 /* bits */ 128, 11064 /* flags */ 0, 11065 }, 11066 #endif /* chips */ 11067 11068 #if defined(BCM_53570_A0) || defined(BCM_53570_B0) 11069 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_18fmt */ 11070 /* format IFP_SINGLE_WIDE_F2_18fmt */ 11071 /* nFields */ 6, 11072 /* *fields */ soc_IFP_SINGLE_WIDE_F2_18fmt_fields, 11073 /* bits */ 128, 11074 /* flags */ 0, 11075 }, 11076 #endif /* chips */ 11077 11078 #if defined(BCM_53400_A0) 11079 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_0_BCM53400_A0fmt */ 11080 /* format IFP_SINGLE_WIDE_F2_0fmt */ 11081 /* nFields */ 9, 11082 /* *fields */ soc_IFP_SINGLE_WIDE_F2_0_BCM53400_A0fmt_fields, 11083 /* bits */ 128, 11084 /* flags */ 0, 11085 }, 11086 #endif /* chips */ 11087 11088 #if defined(BCM_53540_A0) 11089 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_0_BCM53540_A0fmt */ 11090 /* format IFP_SINGLE_WIDE_F2_0fmt */ 11091 /* nFields */ 9, 11092 /* *fields */ soc_IFP_SINGLE_WIDE_F2_0_BCM53400_A0fmt_fields, 11093 /* bits */ 128, 11094 /* flags */ 0, 11095 }, 11096 #endif /* chips */ 11097 11098 #if defined(BCM_53570_A0) 11099 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_0_BCM53570_A0fmt */ 11100 /* format IFP_SINGLE_WIDE_F2_0fmt */ 11101 /* nFields */ 9, 11102 /* *fields */ soc_IFP_SINGLE_WIDE_F2_0_BCM53400_A0fmt_fields, 11103 /* bits */ 128, 11104 /* flags */ 0, 11105 }, 11106 #endif /* chips */ 11107 11108 #if defined(BCM_53570_B0) 11109 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_0_BCM53570_B0fmt */ 11110 /* format IFP_SINGLE_WIDE_F2_0fmt */ 11111 /* nFields */ 9, 11112 /* *fields */ soc_IFP_SINGLE_WIDE_F2_0_BCM53400_A0fmt_fields, 11113 /* bits */ 128, 11114 /* flags */ 0, 11115 }, 11116 #endif /* chips */ 11117 11118 #if defined(BCM_56142_A0) 11119 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_0_BCM56142_A0fmt */ 11120 /* format IFP_SINGLE_WIDE_F2_0fmt */ 11121 /* nFields */ 9, 11122 /* *fields */ soc_IFP_SINGLE_WIDE_F2_0fmt_fields, 11123 /* bits */ 128, 11124 /* flags */ 0, 11125 }, 11126 #endif /* chips */ 11127 11128 #if defined(BCM_56150_A0) 11129 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_0_BCM56150_A0fmt */ 11130 /* format IFP_SINGLE_WIDE_F2_0fmt */ 11131 /* nFields */ 9, 11132 /* *fields */ soc_IFP_SINGLE_WIDE_F2_0_BCM56450_A0fmt_fields, 11133 /* bits */ 128, 11134 /* flags */ 0, 11135 }, 11136 #endif /* chips */ 11137 11138 #if defined(BCM_56160_A0) 11139 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_0_BCM56160_A0fmt */ 11140 /* format IFP_SINGLE_WIDE_F2_0fmt */ 11141 /* nFields */ 9, 11142 /* *fields */ soc_IFP_SINGLE_WIDE_F2_0_BCM53400_A0fmt_fields, 11143 /* bits */ 128, 11144 /* flags */ 0, 11145 }, 11146 #endif /* chips */ 11147 11148 #if defined(BCM_56260_A0) 11149 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_0_BCM56260_A0fmt */ 11150 /* format IFP_SINGLE_WIDE_F2_0fmt */ 11151 /* nFields */ 9, 11152 /* *fields */ soc_IFP_SINGLE_WIDE_F2_0_BCM53400_A0fmt_fields, 11153 /* bits */ 128, 11154 /* flags */ 0, 11155 }, 11156 #endif /* chips */ 11157 11158 #if defined(BCM_56260_B0) 11159 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_0_BCM56260_B0fmt */ 11160 /* format IFP_SINGLE_WIDE_F2_0fmt */ 11161 /* nFields */ 9, 11162 /* *fields */ soc_IFP_SINGLE_WIDE_F2_0_BCM53400_A0fmt_fields, 11163 /* bits */ 128, 11164 /* flags */ 0, 11165 }, 11166 #endif /* chips */ 11167 11168 #if defined(BCM_56270_A0) 11169 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_0_BCM56270_A0fmt */ 11170 /* format IFP_SINGLE_WIDE_F2_0fmt */ 11171 /* nFields */ 9, 11172 /* *fields */ soc_IFP_SINGLE_WIDE_F2_0_BCM53400_A0fmt_fields, 11173 /* bits */ 128, 11174 /* flags */ 0, 11175 }, 11176 #endif /* chips */ 11177 11178 #if defined(BCM_56334_A0) 11179 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_0_BCM56334_A0fmt */ 11180 /* format IFP_SINGLE_WIDE_F2_0fmt */ 11181 /* nFields */ 9, 11182 /* *fields */ soc_IFP_SINGLE_WIDE_F2_0fmt_fields, 11183 /* bits */ 128, 11184 /* flags */ 0, 11185 }, 11186 #endif /* chips */ 11187 11188 #if defined(BCM_56340_A0) 11189 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_0_BCM56340_A0fmt */ 11190 /* format IFP_SINGLE_WIDE_F2_0fmt */ 11191 /* nFields */ 9, 11192 /* *fields */ soc_IFP_SINGLE_WIDE_F2_0_BCM56640_A0fmt_fields, 11193 /* bits */ 128, 11194 /* flags */ 0, 11195 }, 11196 #endif /* chips */ 11197 11198 #if defined(BCM_56450_A0) 11199 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_0_BCM56450_A0fmt */ 11200 /* format IFP_SINGLE_WIDE_F2_0fmt */ 11201 /* nFields */ 9, 11202 /* *fields */ soc_IFP_SINGLE_WIDE_F2_0_BCM56450_A0fmt_fields, 11203 /* bits */ 128, 11204 /* flags */ 0, 11205 }, 11206 #endif /* chips */ 11207 11208 #if defined(BCM_56450_B0) 11209 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_0_BCM56450_B0fmt */ 11210 /* format IFP_SINGLE_WIDE_F2_0fmt */ 11211 /* nFields */ 9, 11212 /* *fields */ soc_IFP_SINGLE_WIDE_F2_0_BCM56450_A0fmt_fields, 11213 /* bits */ 128, 11214 /* flags */ 0, 11215 }, 11216 #endif /* chips */ 11217 11218 #if defined(BCM_56450_B1) 11219 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_0_BCM56450_B1fmt */ 11220 /* format IFP_SINGLE_WIDE_F2_0fmt */ 11221 /* nFields */ 9, 11222 /* *fields */ soc_IFP_SINGLE_WIDE_F2_0_BCM56450_A0fmt_fields, 11223 /* bits */ 128, 11224 /* flags */ 0, 11225 }, 11226 #endif /* chips */ 11227 11228 #if defined(BCM_56560_A0) 11229 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_0_BCM56560_A0fmt */ 11230 /* format IFP_SINGLE_WIDE_F2_0fmt */ 11231 /* nFields */ 9, 11232 /* *fields */ soc_IFP_SINGLE_WIDE_F2_0_BCM56560_A0fmt_fields, 11233 /* bits */ 128, 11234 /* flags */ 0, 11235 }, 11236 #endif /* chips */ 11237 11238 #if defined(BCM_56560_B0) 11239 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_0_BCM56560_B0fmt */ 11240 /* format IFP_SINGLE_WIDE_F2_0fmt */ 11241 /* nFields */ 9, 11242 /* *fields */ soc_IFP_SINGLE_WIDE_F2_0_BCM56560_A0fmt_fields, 11243 /* bits */ 128, 11244 /* flags */ 0, 11245 }, 11246 #endif /* chips */ 11247 11248 #if defined(BCM_56640_A0) 11249 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_0_BCM56640_A0fmt */ 11250 /* format IFP_SINGLE_WIDE_F2_0fmt */ 11251 /* nFields */ 9, 11252 /* *fields */ soc_IFP_SINGLE_WIDE_F2_0_BCM56640_A0fmt_fields, 11253 /* bits */ 128, 11254 /* flags */ 0, 11255 }, 11256 #endif /* chips */ 11257 11258 #if defined(BCM_56670_A0) 11259 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_0_BCM56670_A0fmt */ 11260 /* format IFP_SINGLE_WIDE_F2_0fmt */ 11261 /* nFields */ 9, 11262 /* *fields */ soc_IFP_SINGLE_WIDE_F2_0_BCM56560_A0fmt_fields, 11263 /* bits */ 128, 11264 /* flags */ 0, 11265 }, 11266 #endif /* chips */ 11267 11268 #if defined(BCM_56670_B0) 11269 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_0_BCM56670_B0fmt */ 11270 /* format IFP_SINGLE_WIDE_F2_0fmt */ 11271 /* nFields */ 9, 11272 /* *fields */ soc_IFP_SINGLE_WIDE_F2_0_BCM56560_A0fmt_fields, 11273 /* bits */ 128, 11274 /* flags */ 0, 11275 }, 11276 #endif /* chips */ 11277 11278 #if defined(BCM_56680_B0) 11279 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_0_BCM56680_B0fmt */ 11280 /* format IFP_SINGLE_WIDE_F2_0fmt */ 11281 /* nFields */ 9, 11282 /* *fields */ soc_IFP_SINGLE_WIDE_F2_0fmt_fields, 11283 /* bits */ 128, 11284 /* flags */ 0, 11285 }, 11286 #endif /* chips */ 11287 11288 #if defined(BCM_56685_B0) 11289 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_0_BCM56685_B0fmt */ 11290 /* format IFP_SINGLE_WIDE_F2_0fmt */ 11291 /* nFields */ 9, 11292 /* *fields */ soc_IFP_SINGLE_WIDE_F2_0fmt_fields, 11293 /* bits */ 128, 11294 /* flags */ 0, 11295 }, 11296 #endif /* chips */ 11297 11298 #if defined(BCM_56840_A0) 11299 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_0_BCM56840_A0fmt */ 11300 /* format IFP_SINGLE_WIDE_F2_0fmt */ 11301 /* nFields */ 9, 11302 /* *fields */ soc_IFP_SINGLE_WIDE_F2_0_BCM56840_A0fmt_fields, 11303 /* bits */ 128, 11304 /* flags */ 0, 11305 }, 11306 #endif /* chips */ 11307 11308 #if defined(BCM_56840_B0) 11309 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_0_BCM56840_B0fmt */ 11310 /* format IFP_SINGLE_WIDE_F2_0fmt */ 11311 /* nFields */ 9, 11312 /* *fields */ soc_IFP_SINGLE_WIDE_F2_0_BCM56840_A0fmt_fields, 11313 /* bits */ 128, 11314 /* flags */ 0, 11315 }, 11316 #endif /* chips */ 11317 11318 #if defined(BCM_56850_A0) 11319 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_0_BCM56850_A0fmt */ 11320 /* format IFP_SINGLE_WIDE_F2_0fmt */ 11321 /* nFields */ 9, 11322 /* *fields */ soc_IFP_SINGLE_WIDE_F2_0_BCM56640_A0fmt_fields, 11323 /* bits */ 128, 11324 /* flags */ 0, 11325 }, 11326 #endif /* chips */ 11327 11328 #if defined(BCM_56860_A0) 11329 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_0_BCM56860_A0fmt */ 11330 /* format IFP_SINGLE_WIDE_F2_0fmt */ 11331 /* nFields */ 11, 11332 /* *fields */ soc_IFP_SINGLE_WIDE_F2_0_BCM56860_A0fmt_fields, 11333 /* bits */ 128, 11334 /* flags */ 0, 11335 }, 11336 #endif /* chips */ 11337 11338 #if defined(BCM_88732_A0) 11339 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_0_BCM88732_A0fmt */ 11340 /* format IFP_SINGLE_WIDE_F2_0fmt */ 11341 /* nFields */ 9, 11342 /* *fields */ soc_IFP_SINGLE_WIDE_F2_0fmt_fields, 11343 /* bits */ 128, 11344 /* flags */ 0, 11345 }, 11346 #endif /* chips */ 11347 11348 #if defined(BCM_53400_A0) 11349 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_10_BCM53400_A0fmt */ 11350 /* format IFP_SINGLE_WIDE_F2_10fmt */ 11351 /* nFields */ 2, 11352 /* *fields */ soc_IFP_SINGLE_WIDE_F2_10_BCM53400_A0fmt_fields, 11353 /* bits */ 128, 11354 /* flags */ 0, 11355 }, 11356 #endif /* chips */ 11357 11358 #if defined(BCM_53540_A0) 11359 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_10_BCM53540_A0fmt */ 11360 /* format IFP_SINGLE_WIDE_F2_10fmt */ 11361 /* nFields */ 2, 11362 /* *fields */ soc_IFP_SINGLE_WIDE_F2_10_BCM53400_A0fmt_fields, 11363 /* bits */ 128, 11364 /* flags */ 0, 11365 }, 11366 #endif /* chips */ 11367 11368 #if defined(BCM_53570_A0) 11369 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_10_BCM53570_A0fmt */ 11370 /* format IFP_SINGLE_WIDE_F2_10fmt */ 11371 /* nFields */ 2, 11372 /* *fields */ soc_IFP_SINGLE_WIDE_F2_10_BCM53400_A0fmt_fields, 11373 /* bits */ 128, 11374 /* flags */ 0, 11375 }, 11376 #endif /* chips */ 11377 11378 #if defined(BCM_53570_B0) 11379 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_10_BCM53570_B0fmt */ 11380 /* format IFP_SINGLE_WIDE_F2_10fmt */ 11381 /* nFields */ 2, 11382 /* *fields */ soc_IFP_SINGLE_WIDE_F2_10_BCM53400_A0fmt_fields, 11383 /* bits */ 128, 11384 /* flags */ 0, 11385 }, 11386 #endif /* chips */ 11387 11388 #if defined(BCM_56150_A0) 11389 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_10_BCM56150_A0fmt */ 11390 /* format IFP_SINGLE_WIDE_F2_10fmt */ 11391 /* nFields */ 2, 11392 /* *fields */ soc_IFP_SINGLE_WIDE_F2_10_BCM56640_A0fmt_fields, 11393 /* bits */ 128, 11394 /* flags */ 0, 11395 }, 11396 #endif /* chips */ 11397 11398 #if defined(BCM_56160_A0) 11399 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_10_BCM56160_A0fmt */ 11400 /* format IFP_SINGLE_WIDE_F2_10fmt */ 11401 /* nFields */ 2, 11402 /* *fields */ soc_IFP_SINGLE_WIDE_F2_10_BCM53400_A0fmt_fields, 11403 /* bits */ 128, 11404 /* flags */ 0, 11405 }, 11406 #endif /* chips */ 11407 11408 #if defined(BCM_56260_A0) 11409 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_10_BCM56260_A0fmt */ 11410 /* format IFP_SINGLE_WIDE_F2_10fmt */ 11411 /* nFields */ 2, 11412 /* *fields */ soc_IFP_SINGLE_WIDE_F2_10_BCM53400_A0fmt_fields, 11413 /* bits */ 128, 11414 /* flags */ 0, 11415 }, 11416 #endif /* chips */ 11417 11418 #if defined(BCM_56260_B0) 11419 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_10_BCM56260_B0fmt */ 11420 /* format IFP_SINGLE_WIDE_F2_10fmt */ 11421 /* nFields */ 2, 11422 /* *fields */ soc_IFP_SINGLE_WIDE_F2_10_BCM53400_A0fmt_fields, 11423 /* bits */ 128, 11424 /* flags */ 0, 11425 }, 11426 #endif /* chips */ 11427 11428 #if defined(BCM_56270_A0) 11429 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_10_BCM56270_A0fmt */ 11430 /* format IFP_SINGLE_WIDE_F2_10fmt */ 11431 /* nFields */ 2, 11432 /* *fields */ soc_IFP_SINGLE_WIDE_F2_10_BCM53400_A0fmt_fields, 11433 /* bits */ 128, 11434 /* flags */ 0, 11435 }, 11436 #endif /* chips */ 11437 11438 #if defined(BCM_56334_A0) 11439 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_10_BCM56334_A0fmt */ 11440 /* format IFP_SINGLE_WIDE_F2_10fmt */ 11441 /* nFields */ 2, 11442 /* *fields */ soc_IFP_SINGLE_WIDE_F2_10fmt_fields, 11443 /* bits */ 128, 11444 /* flags */ 0, 11445 }, 11446 #endif /* chips */ 11447 11448 #if defined(BCM_56340_A0) 11449 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_10_BCM56340_A0fmt */ 11450 /* format IFP_SINGLE_WIDE_F2_10fmt */ 11451 /* nFields */ 2, 11452 /* *fields */ soc_IFP_SINGLE_WIDE_F2_10_BCM56640_A0fmt_fields, 11453 /* bits */ 128, 11454 /* flags */ 0, 11455 }, 11456 #endif /* chips */ 11457 11458 #if defined(BCM_56450_A0) 11459 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_10_BCM56450_A0fmt */ 11460 /* format IFP_SINGLE_WIDE_F2_10fmt */ 11461 /* nFields */ 2, 11462 /* *fields */ soc_IFP_SINGLE_WIDE_F2_10_BCM56640_A0fmt_fields, 11463 /* bits */ 128, 11464 /* flags */ 0, 11465 }, 11466 #endif /* chips */ 11467 11468 #if defined(BCM_56450_B0) 11469 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_10_BCM56450_B0fmt */ 11470 /* format IFP_SINGLE_WIDE_F2_10fmt */ 11471 /* nFields */ 2, 11472 /* *fields */ soc_IFP_SINGLE_WIDE_F2_10_BCM56640_A0fmt_fields, 11473 /* bits */ 128, 11474 /* flags */ 0, 11475 }, 11476 #endif /* chips */ 11477 11478 #if defined(BCM_56450_B1) 11479 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_10_BCM56450_B1fmt */ 11480 /* format IFP_SINGLE_WIDE_F2_10fmt */ 11481 /* nFields */ 2, 11482 /* *fields */ soc_IFP_SINGLE_WIDE_F2_10_BCM56640_A0fmt_fields, 11483 /* bits */ 128, 11484 /* flags */ 0, 11485 }, 11486 #endif /* chips */ 11487 11488 #if defined(BCM_56560_A0) 11489 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_10_BCM56560_A0fmt */ 11490 /* format IFP_SINGLE_WIDE_F2_10fmt */ 11491 /* nFields */ 2, 11492 /* *fields */ soc_IFP_SINGLE_WIDE_F2_10_BCM53400_A0fmt_fields, 11493 /* bits */ 128, 11494 /* flags */ 0, 11495 }, 11496 #endif /* chips */ 11497 11498 #if defined(BCM_56560_B0) 11499 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_10_BCM56560_B0fmt */ 11500 /* format IFP_SINGLE_WIDE_F2_10fmt */ 11501 /* nFields */ 2, 11502 /* *fields */ soc_IFP_SINGLE_WIDE_F2_10_BCM53400_A0fmt_fields, 11503 /* bits */ 128, 11504 /* flags */ 0, 11505 }, 11506 #endif /* chips */ 11507 11508 #if defined(BCM_56640_A0) 11509 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_10_BCM56640_A0fmt */ 11510 /* format IFP_SINGLE_WIDE_F2_10fmt */ 11511 /* nFields */ 2, 11512 /* *fields */ soc_IFP_SINGLE_WIDE_F2_10_BCM56640_A0fmt_fields, 11513 /* bits */ 128, 11514 /* flags */ 0, 11515 }, 11516 #endif /* chips */ 11517 11518 #if defined(BCM_56670_A0) 11519 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_10_BCM56670_A0fmt */ 11520 /* format IFP_SINGLE_WIDE_F2_10fmt */ 11521 /* nFields */ 2, 11522 /* *fields */ soc_IFP_SINGLE_WIDE_F2_10_BCM53400_A0fmt_fields, 11523 /* bits */ 128, 11524 /* flags */ 0, 11525 }, 11526 #endif /* chips */ 11527 11528 #if defined(BCM_56670_B0) 11529 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_10_BCM56670_B0fmt */ 11530 /* format IFP_SINGLE_WIDE_F2_10fmt */ 11531 /* nFields */ 2, 11532 /* *fields */ soc_IFP_SINGLE_WIDE_F2_10_BCM53400_A0fmt_fields, 11533 /* bits */ 128, 11534 /* flags */ 0, 11535 }, 11536 #endif /* chips */ 11537 11538 #if defined(BCM_56680_B0) 11539 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_10_BCM56680_B0fmt */ 11540 /* format IFP_SINGLE_WIDE_F2_10fmt */ 11541 /* nFields */ 2, 11542 /* *fields */ soc_IFP_SINGLE_WIDE_F2_10fmt_fields, 11543 /* bits */ 128, 11544 /* flags */ 0, 11545 }, 11546 #endif /* chips */ 11547 11548 #if defined(BCM_56685_B0) 11549 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_10_BCM56685_B0fmt */ 11550 /* format IFP_SINGLE_WIDE_F2_10fmt */ 11551 /* nFields */ 2, 11552 /* *fields */ soc_IFP_SINGLE_WIDE_F2_10fmt_fields, 11553 /* bits */ 128, 11554 /* flags */ 0, 11555 }, 11556 #endif /* chips */ 11557 11558 #if defined(BCM_56850_A0) 11559 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_10_BCM56850_A0fmt */ 11560 /* format IFP_SINGLE_WIDE_F2_10fmt */ 11561 /* nFields */ 2, 11562 /* *fields */ soc_IFP_SINGLE_WIDE_F2_10_BCM56640_A0fmt_fields, 11563 /* bits */ 128, 11564 /* flags */ 0, 11565 }, 11566 #endif /* chips */ 11567 11568 #if defined(BCM_56860_A0) 11569 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_10_BCM56860_A0fmt */ 11570 /* format IFP_SINGLE_WIDE_F2_10fmt */ 11571 /* nFields */ 2, 11572 /* *fields */ soc_IFP_SINGLE_WIDE_F2_10_BCM56640_A0fmt_fields, 11573 /* bits */ 128, 11574 /* flags */ 0, 11575 }, 11576 #endif /* chips */ 11577 11578 #if defined(BCM_53400_A0) 11579 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_11_BCM53400_A0fmt */ 11580 /* format IFP_SINGLE_WIDE_F2_11fmt */ 11581 /* nFields */ 3, 11582 /* *fields */ soc_IFP_SINGLE_WIDE_F2_11_BCM53400_A0fmt_fields, 11583 /* bits */ 128, 11584 /* flags */ 0, 11585 }, 11586 #endif /* chips */ 11587 11588 #if defined(BCM_53540_A0) 11589 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_11_BCM53540_A0fmt */ 11590 /* format IFP_SINGLE_WIDE_F2_11fmt */ 11591 /* nFields */ 3, 11592 /* *fields */ soc_IFP_SINGLE_WIDE_F2_11_BCM53400_A0fmt_fields, 11593 /* bits */ 128, 11594 /* flags */ 0, 11595 }, 11596 #endif /* chips */ 11597 11598 #if defined(BCM_53570_A0) 11599 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_11_BCM53570_A0fmt */ 11600 /* format IFP_SINGLE_WIDE_F2_11fmt */ 11601 /* nFields */ 3, 11602 /* *fields */ soc_IFP_SINGLE_WIDE_F2_11_BCM53400_A0fmt_fields, 11603 /* bits */ 128, 11604 /* flags */ 0, 11605 }, 11606 #endif /* chips */ 11607 11608 #if defined(BCM_53570_B0) 11609 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_11_BCM53570_B0fmt */ 11610 /* format IFP_SINGLE_WIDE_F2_11fmt */ 11611 /* nFields */ 3, 11612 /* *fields */ soc_IFP_SINGLE_WIDE_F2_11_BCM53400_A0fmt_fields, 11613 /* bits */ 128, 11614 /* flags */ 0, 11615 }, 11616 #endif /* chips */ 11617 11618 #if defined(BCM_56142_A0) 11619 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_11_BCM56142_A0fmt */ 11620 /* format IFP_SINGLE_WIDE_F2_11fmt */ 11621 /* nFields */ 3, 11622 /* *fields */ soc_IFP_SINGLE_WIDE_F2_11fmt_fields, 11623 /* bits */ 128, 11624 /* flags */ 0, 11625 }, 11626 #endif /* chips */ 11627 11628 #if defined(BCM_56150_A0) 11629 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_11_BCM56150_A0fmt */ 11630 /* format IFP_SINGLE_WIDE_F2_11fmt */ 11631 /* nFields */ 3, 11632 /* *fields */ soc_IFP_SINGLE_WIDE_F2_11_BCM56640_A0fmt_fields, 11633 /* bits */ 128, 11634 /* flags */ 0, 11635 }, 11636 #endif /* chips */ 11637 11638 #if defined(BCM_56160_A0) 11639 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_11_BCM56160_A0fmt */ 11640 /* format IFP_SINGLE_WIDE_F2_11fmt */ 11641 /* nFields */ 3, 11642 /* *fields */ soc_IFP_SINGLE_WIDE_F2_11_BCM53400_A0fmt_fields, 11643 /* bits */ 128, 11644 /* flags */ 0, 11645 }, 11646 #endif /* chips */ 11647 11648 #if defined(BCM_56260_A0) 11649 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_11_BCM56260_A0fmt */ 11650 /* format IFP_SINGLE_WIDE_F2_11fmt */ 11651 /* nFields */ 3, 11652 /* *fields */ soc_IFP_SINGLE_WIDE_F2_11_BCM53400_A0fmt_fields, 11653 /* bits */ 128, 11654 /* flags */ 0, 11655 }, 11656 #endif /* chips */ 11657 11658 #if defined(BCM_56260_B0) 11659 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_11_BCM56260_B0fmt */ 11660 /* format IFP_SINGLE_WIDE_F2_11fmt */ 11661 /* nFields */ 3, 11662 /* *fields */ soc_IFP_SINGLE_WIDE_F2_11_BCM53400_A0fmt_fields, 11663 /* bits */ 128, 11664 /* flags */ 0, 11665 }, 11666 #endif /* chips */ 11667 11668 #if defined(BCM_56270_A0) 11669 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_11_BCM56270_A0fmt */ 11670 /* format IFP_SINGLE_WIDE_F2_11fmt */ 11671 /* nFields */ 3, 11672 /* *fields */ soc_IFP_SINGLE_WIDE_F2_11_BCM53400_A0fmt_fields, 11673 /* bits */ 128, 11674 /* flags */ 0, 11675 }, 11676 #endif /* chips */ 11677 11678 #if defined(BCM_56334_A0) 11679 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_11_BCM56334_A0fmt */ 11680 /* format IFP_SINGLE_WIDE_F2_11fmt */ 11681 /* nFields */ 3, 11682 /* *fields */ soc_IFP_SINGLE_WIDE_F2_11fmt_fields, 11683 /* bits */ 128, 11684 /* flags */ 0, 11685 }, 11686 #endif /* chips */ 11687 11688 #if defined(BCM_56340_A0) 11689 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_11_BCM56340_A0fmt */ 11690 /* format IFP_SINGLE_WIDE_F2_11fmt */ 11691 /* nFields */ 3, 11692 /* *fields */ soc_IFP_SINGLE_WIDE_F2_11_BCM56640_A0fmt_fields, 11693 /* bits */ 128, 11694 /* flags */ 0, 11695 }, 11696 #endif /* chips */ 11697 11698 #if defined(BCM_56450_A0) 11699 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_11_BCM56450_A0fmt */ 11700 /* format IFP_SINGLE_WIDE_F2_11fmt */ 11701 /* nFields */ 3, 11702 /* *fields */ soc_IFP_SINGLE_WIDE_F2_11_BCM56640_A0fmt_fields, 11703 /* bits */ 128, 11704 /* flags */ 0, 11705 }, 11706 #endif /* chips */ 11707 11708 #if defined(BCM_56450_B0) 11709 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_11_BCM56450_B0fmt */ 11710 /* format IFP_SINGLE_WIDE_F2_11fmt */ 11711 /* nFields */ 3, 11712 /* *fields */ soc_IFP_SINGLE_WIDE_F2_11_BCM56640_A0fmt_fields, 11713 /* bits */ 128, 11714 /* flags */ 0, 11715 }, 11716 #endif /* chips */ 11717 11718 #if defined(BCM_56450_B1) 11719 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_11_BCM56450_B1fmt */ 11720 /* format IFP_SINGLE_WIDE_F2_11fmt */ 11721 /* nFields */ 3, 11722 /* *fields */ soc_IFP_SINGLE_WIDE_F2_11_BCM56640_A0fmt_fields, 11723 /* bits */ 128, 11724 /* flags */ 0, 11725 }, 11726 #endif /* chips */ 11727 11728 #if defined(BCM_56560_A0) 11729 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_11_BCM56560_A0fmt */ 11730 /* format IFP_SINGLE_WIDE_F2_11fmt */ 11731 /* nFields */ 3, 11732 /* *fields */ soc_IFP_SINGLE_WIDE_F2_11_BCM53400_A0fmt_fields, 11733 /* bits */ 128, 11734 /* flags */ 0, 11735 }, 11736 #endif /* chips */ 11737 11738 #if defined(BCM_56560_B0) 11739 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_11_BCM56560_B0fmt */ 11740 /* format IFP_SINGLE_WIDE_F2_11fmt */ 11741 /* nFields */ 3, 11742 /* *fields */ soc_IFP_SINGLE_WIDE_F2_11_BCM53400_A0fmt_fields, 11743 /* bits */ 128, 11744 /* flags */ 0, 11745 }, 11746 #endif /* chips */ 11747 11748 #if defined(BCM_56640_A0) 11749 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_11_BCM56640_A0fmt */ 11750 /* format IFP_SINGLE_WIDE_F2_11fmt */ 11751 /* nFields */ 3, 11752 /* *fields */ soc_IFP_SINGLE_WIDE_F2_11_BCM56640_A0fmt_fields, 11753 /* bits */ 128, 11754 /* flags */ 0, 11755 }, 11756 #endif /* chips */ 11757 11758 #if defined(BCM_56670_A0) 11759 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_11_BCM56670_A0fmt */ 11760 /* format IFP_SINGLE_WIDE_F2_11fmt */ 11761 /* nFields */ 3, 11762 /* *fields */ soc_IFP_SINGLE_WIDE_F2_11_BCM53400_A0fmt_fields, 11763 /* bits */ 128, 11764 /* flags */ 0, 11765 }, 11766 #endif /* chips */ 11767 11768 #if defined(BCM_56670_B0) 11769 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_11_BCM56670_B0fmt */ 11770 /* format IFP_SINGLE_WIDE_F2_11fmt */ 11771 /* nFields */ 3, 11772 /* *fields */ soc_IFP_SINGLE_WIDE_F2_11_BCM53400_A0fmt_fields, 11773 /* bits */ 128, 11774 /* flags */ 0, 11775 }, 11776 #endif /* chips */ 11777 11778 #if defined(BCM_56685_B0) 11779 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_11_BCM56685_B0fmt */ 11780 /* format IFP_SINGLE_WIDE_F2_11fmt */ 11781 /* nFields */ 3, 11782 /* *fields */ soc_IFP_SINGLE_WIDE_F2_11fmt_fields, 11783 /* bits */ 128, 11784 /* flags */ 0, 11785 }, 11786 #endif /* chips */ 11787 11788 #if defined(BCM_56850_A0) 11789 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_11_BCM56850_A0fmt */ 11790 /* format IFP_SINGLE_WIDE_F2_11fmt */ 11791 /* nFields */ 3, 11792 /* *fields */ soc_IFP_SINGLE_WIDE_F2_11_BCM56640_A0fmt_fields, 11793 /* bits */ 128, 11794 /* flags */ 0, 11795 }, 11796 #endif /* chips */ 11797 11798 #if defined(BCM_56860_A0) 11799 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_11_BCM56860_A0fmt */ 11800 /* format IFP_SINGLE_WIDE_F2_11fmt */ 11801 /* nFields */ 3, 11802 /* *fields */ soc_IFP_SINGLE_WIDE_F2_11_BCM56640_A0fmt_fields, 11803 /* bits */ 128, 11804 /* flags */ 0, 11805 }, 11806 #endif /* chips */ 11807 11808 #if defined(BCM_53540_A0) 11809 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_12_BCM53540_A0fmt */ 11810 /* format IFP_SINGLE_WIDE_F2_12fmt */ 11811 /* nFields */ 4, 11812 /* *fields */ soc_IFP_SINGLE_WIDE_F2_12_BCM56160_A0fmt_fields, 11813 /* bits */ 128, 11814 /* flags */ 0, 11815 }, 11816 #endif /* chips */ 11817 11818 #if defined(BCM_53570_A0) 11819 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_12_BCM53570_A0fmt */ 11820 /* format IFP_SINGLE_WIDE_F2_12fmt */ 11821 /* nFields */ 4, 11822 /* *fields */ soc_IFP_SINGLE_WIDE_F2_12_BCM56160_A0fmt_fields, 11823 /* bits */ 128, 11824 /* flags */ 0, 11825 }, 11826 #endif /* chips */ 11827 11828 #if defined(BCM_53570_B0) 11829 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_12_BCM53570_B0fmt */ 11830 /* format IFP_SINGLE_WIDE_F2_12fmt */ 11831 /* nFields */ 4, 11832 /* *fields */ soc_IFP_SINGLE_WIDE_F2_12_BCM56160_A0fmt_fields, 11833 /* bits */ 128, 11834 /* flags */ 0, 11835 }, 11836 #endif /* chips */ 11837 11838 #if defined(BCM_56160_A0) 11839 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_12_BCM56160_A0fmt */ 11840 /* format IFP_SINGLE_WIDE_F2_12fmt */ 11841 /* nFields */ 4, 11842 /* *fields */ soc_IFP_SINGLE_WIDE_F2_12_BCM56160_A0fmt_fields, 11843 /* bits */ 128, 11844 /* flags */ 0, 11845 }, 11846 #endif /* chips */ 11847 11848 #if defined(BCM_56560_A0) 11849 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_12_BCM56560_A0fmt */ 11850 /* format IFP_SINGLE_WIDE_F2_12fmt */ 11851 /* nFields */ 8, 11852 /* *fields */ soc_IFP_SINGLE_WIDE_F2_12_BCM56560_A0fmt_fields, 11853 /* bits */ 128, 11854 /* flags */ 0, 11855 }, 11856 #endif /* chips */ 11857 11858 #if defined(BCM_56560_B0) 11859 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_12_BCM56560_B0fmt */ 11860 /* format IFP_SINGLE_WIDE_F2_12fmt */ 11861 /* nFields */ 8, 11862 /* *fields */ soc_IFP_SINGLE_WIDE_F2_12_BCM56560_A0fmt_fields, 11863 /* bits */ 128, 11864 /* flags */ 0, 11865 }, 11866 #endif /* chips */ 11867 11868 #if defined(BCM_56670_A0) 11869 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_12_BCM56670_A0fmt */ 11870 /* format IFP_SINGLE_WIDE_F2_12fmt */ 11871 /* nFields */ 8, 11872 /* *fields */ soc_IFP_SINGLE_WIDE_F2_12_BCM56560_A0fmt_fields, 11873 /* bits */ 128, 11874 /* flags */ 0, 11875 }, 11876 #endif /* chips */ 11877 11878 #if defined(BCM_56670_B0) 11879 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_12_BCM56670_B0fmt */ 11880 /* format IFP_SINGLE_WIDE_F2_12fmt */ 11881 /* nFields */ 8, 11882 /* *fields */ soc_IFP_SINGLE_WIDE_F2_12_BCM56560_A0fmt_fields, 11883 /* bits */ 128, 11884 /* flags */ 0, 11885 }, 11886 #endif /* chips */ 11887 11888 #if defined(BCM_53540_A0) 11889 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_13_BCM53540_A0fmt */ 11890 /* format IFP_SINGLE_WIDE_F2_13fmt */ 11891 /* nFields */ 4, 11892 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_4fmt_fields, 11893 /* bits */ 128, 11894 /* flags */ 0, 11895 }, 11896 #endif /* chips */ 11897 11898 #if defined(BCM_53570_A0) 11899 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_13_BCM53570_A0fmt */ 11900 /* format IFP_SINGLE_WIDE_F2_13fmt */ 11901 /* nFields */ 4, 11902 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_4fmt_fields, 11903 /* bits */ 128, 11904 /* flags */ 0, 11905 }, 11906 #endif /* chips */ 11907 11908 #if defined(BCM_53570_B0) 11909 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_13_BCM53570_B0fmt */ 11910 /* format IFP_SINGLE_WIDE_F2_13fmt */ 11911 /* nFields */ 4, 11912 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_4fmt_fields, 11913 /* bits */ 128, 11914 /* flags */ 0, 11915 }, 11916 #endif /* chips */ 11917 11918 #if defined(BCM_53540_A0) 11919 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_14_BCM53540_A0fmt */ 11920 /* format IFP_SINGLE_WIDE_F2_14fmt */ 11921 /* nFields */ 7, 11922 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_5fmt_fields, 11923 /* bits */ 128, 11924 /* flags */ 0, 11925 }, 11926 #endif /* chips */ 11927 11928 #if defined(BCM_53570_A0) 11929 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_14_BCM53570_A0fmt */ 11930 /* format IFP_SINGLE_WIDE_F2_14fmt */ 11931 /* nFields */ 7, 11932 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_5fmt_fields, 11933 /* bits */ 128, 11934 /* flags */ 0, 11935 }, 11936 #endif /* chips */ 11937 11938 #if defined(BCM_53570_B0) 11939 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_14_BCM53570_B0fmt */ 11940 /* format IFP_SINGLE_WIDE_F2_14fmt */ 11941 /* nFields */ 7, 11942 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_5fmt_fields, 11943 /* bits */ 128, 11944 /* flags */ 0, 11945 }, 11946 #endif /* chips */ 11947 11948 #if defined(BCM_53540_A0) 11949 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_15_BCM53540_A0fmt */ 11950 /* format IFP_SINGLE_WIDE_F2_15fmt */ 11951 /* nFields */ 1, 11952 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_6fmt_fields, 11953 /* bits */ 128, 11954 /* flags */ 0, 11955 }, 11956 #endif /* chips */ 11957 11958 #if defined(BCM_53570_A0) 11959 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_15_BCM53570_A0fmt */ 11960 /* format IFP_SINGLE_WIDE_F2_15fmt */ 11961 /* nFields */ 1, 11962 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_6fmt_fields, 11963 /* bits */ 128, 11964 /* flags */ 0, 11965 }, 11966 #endif /* chips */ 11967 11968 #if defined(BCM_53570_B0) 11969 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_15_BCM53570_B0fmt */ 11970 /* format IFP_SINGLE_WIDE_F2_15fmt */ 11971 /* nFields */ 1, 11972 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_6fmt_fields, 11973 /* bits */ 128, 11974 /* flags */ 0, 11975 }, 11976 #endif /* chips */ 11977 11978 #if defined(BCM_53540_A0) 11979 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_16_BCM53540_A0fmt */ 11980 /* format IFP_SINGLE_WIDE_F2_16fmt */ 11981 /* nFields */ 1, 11982 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_7fmt_fields, 11983 /* bits */ 128, 11984 /* flags */ 0, 11985 }, 11986 #endif /* chips */ 11987 11988 #if defined(BCM_53570_A0) 11989 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_16_BCM53570_A0fmt */ 11990 /* format IFP_SINGLE_WIDE_F2_16fmt */ 11991 /* nFields */ 1, 11992 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_7fmt_fields, 11993 /* bits */ 128, 11994 /* flags */ 0, 11995 }, 11996 #endif /* chips */ 11997 11998 #if defined(BCM_53570_B0) 11999 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_16_BCM53570_B0fmt */ 12000 /* format IFP_SINGLE_WIDE_F2_16fmt */ 12001 /* nFields */ 1, 12002 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_7fmt_fields, 12003 /* bits */ 128, 12004 /* flags */ 0, 12005 }, 12006 #endif /* chips */ 12007 12008 #if defined(BCM_53570_B0) 12009 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_17_BCM53570_B0fmt */ 12010 /* format IFP_SINGLE_WIDE_F2_17fmt */ 12011 /* nFields */ 40, 12012 /* *fields */ soc_IFP_SINGLE_WIDE_F2_17_BCM53570_B0fmt_fields, 12013 /* bits */ 128, 12014 /* flags */ 0, 12015 }, 12016 #endif /* chips */ 12017 12018 #if defined(BCM_53400_A0) 12019 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_1_BCM53400_A0fmt */ 12020 /* format IFP_SINGLE_WIDE_F2_1fmt */ 12021 /* nFields */ 9, 12022 /* *fields */ soc_IFP_SINGLE_WIDE_F2_1_BCM53400_A0fmt_fields, 12023 /* bits */ 128, 12024 /* flags */ 0, 12025 }, 12026 #endif /* chips */ 12027 12028 #if defined(BCM_53540_A0) 12029 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_1_BCM53540_A0fmt */ 12030 /* format IFP_SINGLE_WIDE_F2_1fmt */ 12031 /* nFields */ 9, 12032 /* *fields */ soc_IFP_SINGLE_WIDE_F2_1_BCM53400_A0fmt_fields, 12033 /* bits */ 128, 12034 /* flags */ 0, 12035 }, 12036 #endif /* chips */ 12037 12038 #if defined(BCM_53570_A0) 12039 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_1_BCM53570_A0fmt */ 12040 /* format IFP_SINGLE_WIDE_F2_1fmt */ 12041 /* nFields */ 9, 12042 /* *fields */ soc_IFP_SINGLE_WIDE_F2_1_BCM53400_A0fmt_fields, 12043 /* bits */ 128, 12044 /* flags */ 0, 12045 }, 12046 #endif /* chips */ 12047 12048 #if defined(BCM_53570_B0) 12049 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_1_BCM53570_B0fmt */ 12050 /* format IFP_SINGLE_WIDE_F2_1fmt */ 12051 /* nFields */ 9, 12052 /* *fields */ soc_IFP_SINGLE_WIDE_F2_1_BCM53400_A0fmt_fields, 12053 /* bits */ 128, 12054 /* flags */ 0, 12055 }, 12056 #endif /* chips */ 12057 12058 #if defined(BCM_56142_A0) 12059 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_1_BCM56142_A0fmt */ 12060 /* format IFP_SINGLE_WIDE_F2_1fmt */ 12061 /* nFields */ 9, 12062 /* *fields */ soc_IFP_SINGLE_WIDE_F2_1fmt_fields, 12063 /* bits */ 128, 12064 /* flags */ 0, 12065 }, 12066 #endif /* chips */ 12067 12068 #if defined(BCM_56150_A0) 12069 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_1_BCM56150_A0fmt */ 12070 /* format IFP_SINGLE_WIDE_F2_1fmt */ 12071 /* nFields */ 9, 12072 /* *fields */ soc_IFP_SINGLE_WIDE_F2_1_BCM56450_A0fmt_fields, 12073 /* bits */ 128, 12074 /* flags */ 0, 12075 }, 12076 #endif /* chips */ 12077 12078 #if defined(BCM_56160_A0) 12079 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_1_BCM56160_A0fmt */ 12080 /* format IFP_SINGLE_WIDE_F2_1fmt */ 12081 /* nFields */ 9, 12082 /* *fields */ soc_IFP_SINGLE_WIDE_F2_1_BCM53400_A0fmt_fields, 12083 /* bits */ 128, 12084 /* flags */ 0, 12085 }, 12086 #endif /* chips */ 12087 12088 #if defined(BCM_56260_A0) 12089 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_1_BCM56260_A0fmt */ 12090 /* format IFP_SINGLE_WIDE_F2_1fmt */ 12091 /* nFields */ 9, 12092 /* *fields */ soc_IFP_SINGLE_WIDE_F2_1_BCM53400_A0fmt_fields, 12093 /* bits */ 128, 12094 /* flags */ 0, 12095 }, 12096 #endif /* chips */ 12097 12098 #if defined(BCM_56260_B0) 12099 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_1_BCM56260_B0fmt */ 12100 /* format IFP_SINGLE_WIDE_F2_1fmt */ 12101 /* nFields */ 9, 12102 /* *fields */ soc_IFP_SINGLE_WIDE_F2_1_BCM53400_A0fmt_fields, 12103 /* bits */ 128, 12104 /* flags */ 0, 12105 }, 12106 #endif /* chips */ 12107 12108 #if defined(BCM_56270_A0) 12109 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_1_BCM56270_A0fmt */ 12110 /* format IFP_SINGLE_WIDE_F2_1fmt */ 12111 /* nFields */ 9, 12112 /* *fields */ soc_IFP_SINGLE_WIDE_F2_1_BCM53400_A0fmt_fields, 12113 /* bits */ 128, 12114 /* flags */ 0, 12115 }, 12116 #endif /* chips */ 12117 12118 #if defined(BCM_56334_A0) 12119 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_1_BCM56334_A0fmt */ 12120 /* format IFP_SINGLE_WIDE_F2_1fmt */ 12121 /* nFields */ 9, 12122 /* *fields */ soc_IFP_SINGLE_WIDE_F2_1fmt_fields, 12123 /* bits */ 128, 12124 /* flags */ 0, 12125 }, 12126 #endif /* chips */ 12127 12128 #if defined(BCM_56340_A0) 12129 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_1_BCM56340_A0fmt */ 12130 /* format IFP_SINGLE_WIDE_F2_1fmt */ 12131 /* nFields */ 9, 12132 /* *fields */ soc_IFP_SINGLE_WIDE_F2_1_BCM56640_A0fmt_fields, 12133 /* bits */ 128, 12134 /* flags */ 0, 12135 }, 12136 #endif /* chips */ 12137 12138 #if defined(BCM_56450_A0) 12139 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_1_BCM56450_A0fmt */ 12140 /* format IFP_SINGLE_WIDE_F2_1fmt */ 12141 /* nFields */ 9, 12142 /* *fields */ soc_IFP_SINGLE_WIDE_F2_1_BCM56450_A0fmt_fields, 12143 /* bits */ 128, 12144 /* flags */ 0, 12145 }, 12146 #endif /* chips */ 12147 12148 #if defined(BCM_56450_B0) 12149 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_1_BCM56450_B0fmt */ 12150 /* format IFP_SINGLE_WIDE_F2_1fmt */ 12151 /* nFields */ 9, 12152 /* *fields */ soc_IFP_SINGLE_WIDE_F2_1_BCM56450_A0fmt_fields, 12153 /* bits */ 128, 12154 /* flags */ 0, 12155 }, 12156 #endif /* chips */ 12157 12158 #if defined(BCM_56450_B1) 12159 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_1_BCM56450_B1fmt */ 12160 /* format IFP_SINGLE_WIDE_F2_1fmt */ 12161 /* nFields */ 9, 12162 /* *fields */ soc_IFP_SINGLE_WIDE_F2_1_BCM56450_A0fmt_fields, 12163 /* bits */ 128, 12164 /* flags */ 0, 12165 }, 12166 #endif /* chips */ 12167 12168 #if defined(BCM_56560_A0) 12169 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_1_BCM56560_A0fmt */ 12170 /* format IFP_SINGLE_WIDE_F2_1fmt */ 12171 /* nFields */ 9, 12172 /* *fields */ soc_IFP_SINGLE_WIDE_F2_1_BCM56560_A0fmt_fields, 12173 /* bits */ 128, 12174 /* flags */ 0, 12175 }, 12176 #endif /* chips */ 12177 12178 #if defined(BCM_56560_B0) 12179 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_1_BCM56560_B0fmt */ 12180 /* format IFP_SINGLE_WIDE_F2_1fmt */ 12181 /* nFields */ 9, 12182 /* *fields */ soc_IFP_SINGLE_WIDE_F2_1_BCM56560_A0fmt_fields, 12183 /* bits */ 128, 12184 /* flags */ 0, 12185 }, 12186 #endif /* chips */ 12187 12188 #if defined(BCM_56640_A0) 12189 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_1_BCM56640_A0fmt */ 12190 /* format IFP_SINGLE_WIDE_F2_1fmt */ 12191 /* nFields */ 9, 12192 /* *fields */ soc_IFP_SINGLE_WIDE_F2_1_BCM56640_A0fmt_fields, 12193 /* bits */ 128, 12194 /* flags */ 0, 12195 }, 12196 #endif /* chips */ 12197 12198 #if defined(BCM_56670_A0) 12199 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_1_BCM56670_A0fmt */ 12200 /* format IFP_SINGLE_WIDE_F2_1fmt */ 12201 /* nFields */ 9, 12202 /* *fields */ soc_IFP_SINGLE_WIDE_F2_1_BCM56560_A0fmt_fields, 12203 /* bits */ 128, 12204 /* flags */ 0, 12205 }, 12206 #endif /* chips */ 12207 12208 #if defined(BCM_56670_B0) 12209 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_1_BCM56670_B0fmt */ 12210 /* format IFP_SINGLE_WIDE_F2_1fmt */ 12211 /* nFields */ 9, 12212 /* *fields */ soc_IFP_SINGLE_WIDE_F2_1_BCM56560_A0fmt_fields, 12213 /* bits */ 128, 12214 /* flags */ 0, 12215 }, 12216 #endif /* chips */ 12217 12218 #if defined(BCM_56680_B0) 12219 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_1_BCM56680_B0fmt */ 12220 /* format IFP_SINGLE_WIDE_F2_1fmt */ 12221 /* nFields */ 9, 12222 /* *fields */ soc_IFP_SINGLE_WIDE_F2_1fmt_fields, 12223 /* bits */ 128, 12224 /* flags */ 0, 12225 }, 12226 #endif /* chips */ 12227 12228 #if defined(BCM_56685_B0) 12229 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_1_BCM56685_B0fmt */ 12230 /* format IFP_SINGLE_WIDE_F2_1fmt */ 12231 /* nFields */ 9, 12232 /* *fields */ soc_IFP_SINGLE_WIDE_F2_1fmt_fields, 12233 /* bits */ 128, 12234 /* flags */ 0, 12235 }, 12236 #endif /* chips */ 12237 12238 #if defined(BCM_56840_A0) 12239 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_1_BCM56840_A0fmt */ 12240 /* format IFP_SINGLE_WIDE_F2_1fmt */ 12241 /* nFields */ 9, 12242 /* *fields */ soc_IFP_SINGLE_WIDE_F2_1_BCM56840_A0fmt_fields, 12243 /* bits */ 128, 12244 /* flags */ 0, 12245 }, 12246 #endif /* chips */ 12247 12248 #if defined(BCM_56840_B0) 12249 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_1_BCM56840_B0fmt */ 12250 /* format IFP_SINGLE_WIDE_F2_1fmt */ 12251 /* nFields */ 9, 12252 /* *fields */ soc_IFP_SINGLE_WIDE_F2_1_BCM56840_A0fmt_fields, 12253 /* bits */ 128, 12254 /* flags */ 0, 12255 }, 12256 #endif /* chips */ 12257 12258 #if defined(BCM_56850_A0) 12259 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_1_BCM56850_A0fmt */ 12260 /* format IFP_SINGLE_WIDE_F2_1fmt */ 12261 /* nFields */ 9, 12262 /* *fields */ soc_IFP_SINGLE_WIDE_F2_1_BCM56640_A0fmt_fields, 12263 /* bits */ 128, 12264 /* flags */ 0, 12265 }, 12266 #endif /* chips */ 12267 12268 #if defined(BCM_56860_A0) 12269 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_1_BCM56860_A0fmt */ 12270 /* format IFP_SINGLE_WIDE_F2_1fmt */ 12271 /* nFields */ 11, 12272 /* *fields */ soc_IFP_SINGLE_WIDE_F2_1_BCM56860_A0fmt_fields, 12273 /* bits */ 128, 12274 /* flags */ 0, 12275 }, 12276 #endif /* chips */ 12277 12278 #if defined(BCM_88732_A0) 12279 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_1_BCM88732_A0fmt */ 12280 /* format IFP_SINGLE_WIDE_F2_1fmt */ 12281 /* nFields */ 9, 12282 /* *fields */ soc_IFP_SINGLE_WIDE_F2_1fmt_fields, 12283 /* bits */ 128, 12284 /* flags */ 0, 12285 }, 12286 #endif /* chips */ 12287 12288 #if defined(BCM_53400_A0) 12289 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_2_BCM53400_A0fmt */ 12290 /* format IFP_SINGLE_WIDE_F2_2fmt */ 12291 /* nFields */ 1, 12292 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_1_BCM53400_A0fmt_fields, 12293 /* bits */ 128, 12294 /* flags */ 0, 12295 }, 12296 #endif /* chips */ 12297 12298 #if defined(BCM_53540_A0) 12299 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_2_BCM53540_A0fmt */ 12300 /* format IFP_SINGLE_WIDE_F2_2fmt */ 12301 /* nFields */ 1, 12302 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_1_BCM53400_A0fmt_fields, 12303 /* bits */ 128, 12304 /* flags */ 0, 12305 }, 12306 #endif /* chips */ 12307 12308 #if defined(BCM_53570_A0) 12309 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_2_BCM53570_A0fmt */ 12310 /* format IFP_SINGLE_WIDE_F2_2fmt */ 12311 /* nFields */ 1, 12312 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_1_BCM53400_A0fmt_fields, 12313 /* bits */ 128, 12314 /* flags */ 0, 12315 }, 12316 #endif /* chips */ 12317 12318 #if defined(BCM_53570_B0) 12319 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_2_BCM53570_B0fmt */ 12320 /* format IFP_SINGLE_WIDE_F2_2fmt */ 12321 /* nFields */ 1, 12322 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_1_BCM53400_A0fmt_fields, 12323 /* bits */ 128, 12324 /* flags */ 0, 12325 }, 12326 #endif /* chips */ 12327 12328 #if defined(BCM_56142_A0) 12329 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_2_BCM56142_A0fmt */ 12330 /* format IFP_SINGLE_WIDE_F2_2fmt */ 12331 /* nFields */ 1, 12332 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_1fmt_fields, 12333 /* bits */ 128, 12334 /* flags */ 0, 12335 }, 12336 #endif /* chips */ 12337 12338 #if defined(BCM_56150_A0) 12339 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_2_BCM56150_A0fmt */ 12340 /* format IFP_SINGLE_WIDE_F2_2fmt */ 12341 /* nFields */ 1, 12342 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_1_BCM56640_A0fmt_fields, 12343 /* bits */ 128, 12344 /* flags */ 0, 12345 }, 12346 #endif /* chips */ 12347 12348 #if defined(BCM_56160_A0) 12349 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_2_BCM56160_A0fmt */ 12350 /* format IFP_SINGLE_WIDE_F2_2fmt */ 12351 /* nFields */ 1, 12352 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_1_BCM53400_A0fmt_fields, 12353 /* bits */ 128, 12354 /* flags */ 0, 12355 }, 12356 #endif /* chips */ 12357 12358 #if defined(BCM_56260_A0) 12359 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_2_BCM56260_A0fmt */ 12360 /* format IFP_SINGLE_WIDE_F2_2fmt */ 12361 /* nFields */ 1, 12362 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_1_BCM53400_A0fmt_fields, 12363 /* bits */ 128, 12364 /* flags */ 0, 12365 }, 12366 #endif /* chips */ 12367 12368 #if defined(BCM_56260_B0) 12369 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_2_BCM56260_B0fmt */ 12370 /* format IFP_SINGLE_WIDE_F2_2fmt */ 12371 /* nFields */ 1, 12372 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_1_BCM53400_A0fmt_fields, 12373 /* bits */ 128, 12374 /* flags */ 0, 12375 }, 12376 #endif /* chips */ 12377 12378 #if defined(BCM_56270_A0) 12379 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_2_BCM56270_A0fmt */ 12380 /* format IFP_SINGLE_WIDE_F2_2fmt */ 12381 /* nFields */ 1, 12382 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_1_BCM53400_A0fmt_fields, 12383 /* bits */ 128, 12384 /* flags */ 0, 12385 }, 12386 #endif /* chips */ 12387 12388 #if defined(BCM_56334_A0) 12389 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_2_BCM56334_A0fmt */ 12390 /* format IFP_SINGLE_WIDE_F2_2fmt */ 12391 /* nFields */ 1, 12392 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_1fmt_fields, 12393 /* bits */ 128, 12394 /* flags */ 0, 12395 }, 12396 #endif /* chips */ 12397 12398 #if defined(BCM_56334_B0) 12399 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_2_BCM56334_B0fmt */ 12400 /* format IFP_SINGLE_WIDE_F2_2fmt */ 12401 /* nFields */ 1, 12402 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_1fmt_fields, 12403 /* bits */ 128, 12404 /* flags */ 0, 12405 }, 12406 #endif /* chips */ 12407 12408 #if defined(BCM_56340_A0) 12409 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_2_BCM56340_A0fmt */ 12410 /* format IFP_SINGLE_WIDE_F2_2fmt */ 12411 /* nFields */ 1, 12412 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_1_BCM56640_A0fmt_fields, 12413 /* bits */ 128, 12414 /* flags */ 0, 12415 }, 12416 #endif /* chips */ 12417 12418 #if defined(BCM_56440_A0) 12419 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_2_BCM56440_A0fmt */ 12420 /* format IFP_SINGLE_WIDE_F2_2fmt */ 12421 /* nFields */ 1, 12422 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_1fmt_fields, 12423 /* bits */ 128, 12424 /* flags */ 0, 12425 }, 12426 #endif /* chips */ 12427 12428 #if defined(BCM_56440_B0) 12429 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_2_BCM56440_B0fmt */ 12430 /* format IFP_SINGLE_WIDE_F2_2fmt */ 12431 /* nFields */ 1, 12432 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_1fmt_fields, 12433 /* bits */ 128, 12434 /* flags */ 0, 12435 }, 12436 #endif /* chips */ 12437 12438 #if defined(BCM_56450_A0) 12439 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_2_BCM56450_A0fmt */ 12440 /* format IFP_SINGLE_WIDE_F2_2fmt */ 12441 /* nFields */ 1, 12442 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_1_BCM56640_A0fmt_fields, 12443 /* bits */ 128, 12444 /* flags */ 0, 12445 }, 12446 #endif /* chips */ 12447 12448 #if defined(BCM_56450_B0) 12449 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_2_BCM56450_B0fmt */ 12450 /* format IFP_SINGLE_WIDE_F2_2fmt */ 12451 /* nFields */ 1, 12452 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_1_BCM56640_A0fmt_fields, 12453 /* bits */ 128, 12454 /* flags */ 0, 12455 }, 12456 #endif /* chips */ 12457 12458 #if defined(BCM_56450_B1) 12459 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_2_BCM56450_B1fmt */ 12460 /* format IFP_SINGLE_WIDE_F2_2fmt */ 12461 /* nFields */ 1, 12462 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_1_BCM56640_A0fmt_fields, 12463 /* bits */ 128, 12464 /* flags */ 0, 12465 }, 12466 #endif /* chips */ 12467 12468 #if defined(BCM_56524_A0) 12469 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_2_BCM56524_A0fmt */ 12470 /* format IFP_SINGLE_WIDE_F2_2fmt */ 12471 /* nFields */ 1, 12472 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_1fmt_fields, 12473 /* bits */ 128, 12474 /* flags */ 0, 12475 }, 12476 #endif /* chips */ 12477 12478 #if defined(BCM_56524_B0) 12479 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_2_BCM56524_B0fmt */ 12480 /* format IFP_SINGLE_WIDE_F2_2fmt */ 12481 /* nFields */ 1, 12482 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_1fmt_fields, 12483 /* bits */ 128, 12484 /* flags */ 0, 12485 }, 12486 #endif /* chips */ 12487 12488 #if defined(BCM_56560_A0) 12489 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_2_BCM56560_A0fmt */ 12490 /* format IFP_SINGLE_WIDE_F2_2fmt */ 12491 /* nFields */ 1, 12492 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_1_BCM53400_A0fmt_fields, 12493 /* bits */ 128, 12494 /* flags */ 0, 12495 }, 12496 #endif /* chips */ 12497 12498 #if defined(BCM_56560_B0) 12499 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_2_BCM56560_B0fmt */ 12500 /* format IFP_SINGLE_WIDE_F2_2fmt */ 12501 /* nFields */ 1, 12502 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_1_BCM53400_A0fmt_fields, 12503 /* bits */ 128, 12504 /* flags */ 0, 12505 }, 12506 #endif /* chips */ 12507 12508 #if defined(BCM_56624_B0) 12509 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_2_BCM56624_B0fmt */ 12510 /* format IFP_SINGLE_WIDE_F2_2fmt */ 12511 /* nFields */ 1, 12512 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_1fmt_fields, 12513 /* bits */ 128, 12514 /* flags */ 0, 12515 }, 12516 #endif /* chips */ 12517 12518 #if defined(BCM_56634_A0) 12519 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_2_BCM56634_A0fmt */ 12520 /* format IFP_SINGLE_WIDE_F2_2fmt */ 12521 /* nFields */ 1, 12522 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_1fmt_fields, 12523 /* bits */ 128, 12524 /* flags */ 0, 12525 }, 12526 #endif /* chips */ 12527 12528 #if defined(BCM_56634_B0) 12529 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_2_BCM56634_B0fmt */ 12530 /* format IFP_SINGLE_WIDE_F2_2fmt */ 12531 /* nFields */ 1, 12532 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_1fmt_fields, 12533 /* bits */ 128, 12534 /* flags */ 0, 12535 }, 12536 #endif /* chips */ 12537 12538 #if defined(BCM_56640_A0) 12539 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_2_BCM56640_A0fmt */ 12540 /* format IFP_SINGLE_WIDE_F2_2fmt */ 12541 /* nFields */ 1, 12542 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_1_BCM56640_A0fmt_fields, 12543 /* bits */ 128, 12544 /* flags */ 0, 12545 }, 12546 #endif /* chips */ 12547 12548 #if defined(BCM_56670_A0) 12549 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_2_BCM56670_A0fmt */ 12550 /* format IFP_SINGLE_WIDE_F2_2fmt */ 12551 /* nFields */ 1, 12552 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_1_BCM53400_A0fmt_fields, 12553 /* bits */ 128, 12554 /* flags */ 0, 12555 }, 12556 #endif /* chips */ 12557 12558 #if defined(BCM_56670_B0) 12559 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_2_BCM56670_B0fmt */ 12560 /* format IFP_SINGLE_WIDE_F2_2fmt */ 12561 /* nFields */ 1, 12562 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_1_BCM53400_A0fmt_fields, 12563 /* bits */ 128, 12564 /* flags */ 0, 12565 }, 12566 #endif /* chips */ 12567 12568 #if defined(BCM_56680_A0) 12569 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_2_BCM56680_A0fmt */ 12570 /* format IFP_SINGLE_WIDE_F2_2fmt */ 12571 /* nFields */ 1, 12572 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_1fmt_fields, 12573 /* bits */ 128, 12574 /* flags */ 0, 12575 }, 12576 #endif /* chips */ 12577 12578 #if defined(BCM_56680_B0) 12579 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_2_BCM56680_B0fmt */ 12580 /* format IFP_SINGLE_WIDE_F2_2fmt */ 12581 /* nFields */ 1, 12582 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_1fmt_fields, 12583 /* bits */ 128, 12584 /* flags */ 0, 12585 }, 12586 #endif /* chips */ 12587 12588 #if defined(BCM_56685_A0) 12589 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_2_BCM56685_A0fmt */ 12590 /* format IFP_SINGLE_WIDE_F2_2fmt */ 12591 /* nFields */ 1, 12592 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_1fmt_fields, 12593 /* bits */ 128, 12594 /* flags */ 0, 12595 }, 12596 #endif /* chips */ 12597 12598 #if defined(BCM_56685_B0) 12599 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_2_BCM56685_B0fmt */ 12600 /* format IFP_SINGLE_WIDE_F2_2fmt */ 12601 /* nFields */ 1, 12602 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_1fmt_fields, 12603 /* bits */ 128, 12604 /* flags */ 0, 12605 }, 12606 #endif /* chips */ 12607 12608 #if defined(BCM_56725_A0) 12609 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_2_BCM56725_A0fmt */ 12610 /* format IFP_SINGLE_WIDE_F2_2fmt */ 12611 /* nFields */ 1, 12612 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_1fmt_fields, 12613 /* bits */ 128, 12614 /* flags */ 0, 12615 }, 12616 #endif /* chips */ 12617 12618 #if defined(BCM_56820_A0) 12619 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_2_BCM56820_A0fmt */ 12620 /* format IFP_SINGLE_WIDE_F2_2fmt */ 12621 /* nFields */ 1, 12622 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_1fmt_fields, 12623 /* bits */ 128, 12624 /* flags */ 0, 12625 }, 12626 #endif /* chips */ 12627 12628 #if defined(BCM_56840_A0) 12629 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_2_BCM56840_A0fmt */ 12630 /* format IFP_SINGLE_WIDE_F2_2fmt */ 12631 /* nFields */ 1, 12632 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_1fmt_fields, 12633 /* bits */ 128, 12634 /* flags */ 0, 12635 }, 12636 #endif /* chips */ 12637 12638 #if defined(BCM_56840_B0) 12639 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_2_BCM56840_B0fmt */ 12640 /* format IFP_SINGLE_WIDE_F2_2fmt */ 12641 /* nFields */ 1, 12642 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_1fmt_fields, 12643 /* bits */ 128, 12644 /* flags */ 0, 12645 }, 12646 #endif /* chips */ 12647 12648 #if defined(BCM_56850_A0) 12649 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_2_BCM56850_A0fmt */ 12650 /* format IFP_SINGLE_WIDE_F2_2fmt */ 12651 /* nFields */ 1, 12652 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_1_BCM56640_A0fmt_fields, 12653 /* bits */ 128, 12654 /* flags */ 0, 12655 }, 12656 #endif /* chips */ 12657 12658 #if defined(BCM_56860_A0) 12659 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_2_BCM56860_A0fmt */ 12660 /* format IFP_SINGLE_WIDE_F2_2fmt */ 12661 /* nFields */ 1, 12662 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_1_BCM56640_A0fmt_fields, 12663 /* bits */ 128, 12664 /* flags */ 0, 12665 }, 12666 #endif /* chips */ 12667 12668 #if defined(BCM_88732_A0) 12669 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_2_BCM88732_A0fmt */ 12670 /* format IFP_SINGLE_WIDE_F2_2fmt */ 12671 /* nFields */ 1, 12672 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_1fmt_fields, 12673 /* bits */ 128, 12674 /* flags */ 0, 12675 }, 12676 #endif /* chips */ 12677 12678 #if defined(BCM_53400_A0) 12679 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_3_BCM53400_A0fmt */ 12680 /* format IFP_SINGLE_WIDE_F2_3fmt */ 12681 /* nFields */ 1, 12682 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_2_BCM53400_A0fmt_fields, 12683 /* bits */ 128, 12684 /* flags */ 0, 12685 }, 12686 #endif /* chips */ 12687 12688 #if defined(BCM_53540_A0) 12689 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_3_BCM53540_A0fmt */ 12690 /* format IFP_SINGLE_WIDE_F2_3fmt */ 12691 /* nFields */ 1, 12692 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_2_BCM53400_A0fmt_fields, 12693 /* bits */ 128, 12694 /* flags */ 0, 12695 }, 12696 #endif /* chips */ 12697 12698 #if defined(BCM_53570_A0) 12699 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_3_BCM53570_A0fmt */ 12700 /* format IFP_SINGLE_WIDE_F2_3fmt */ 12701 /* nFields */ 1, 12702 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_2_BCM53400_A0fmt_fields, 12703 /* bits */ 128, 12704 /* flags */ 0, 12705 }, 12706 #endif /* chips */ 12707 12708 #if defined(BCM_53570_B0) 12709 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_3_BCM53570_B0fmt */ 12710 /* format IFP_SINGLE_WIDE_F2_3fmt */ 12711 /* nFields */ 1, 12712 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_2_BCM53400_A0fmt_fields, 12713 /* bits */ 128, 12714 /* flags */ 0, 12715 }, 12716 #endif /* chips */ 12717 12718 #if defined(BCM_56150_A0) 12719 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_3_BCM56150_A0fmt */ 12720 /* format IFP_SINGLE_WIDE_F2_3fmt */ 12721 /* nFields */ 1, 12722 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_2_BCM56640_A0fmt_fields, 12723 /* bits */ 128, 12724 /* flags */ 0, 12725 }, 12726 #endif /* chips */ 12727 12728 #if defined(BCM_56160_A0) 12729 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_3_BCM56160_A0fmt */ 12730 /* format IFP_SINGLE_WIDE_F2_3fmt */ 12731 /* nFields */ 1, 12732 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_2_BCM53400_A0fmt_fields, 12733 /* bits */ 128, 12734 /* flags */ 0, 12735 }, 12736 #endif /* chips */ 12737 12738 #if defined(BCM_56260_A0) 12739 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_3_BCM56260_A0fmt */ 12740 /* format IFP_SINGLE_WIDE_F2_3fmt */ 12741 /* nFields */ 1, 12742 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_2_BCM53400_A0fmt_fields, 12743 /* bits */ 128, 12744 /* flags */ 0, 12745 }, 12746 #endif /* chips */ 12747 12748 #if defined(BCM_56260_B0) 12749 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_3_BCM56260_B0fmt */ 12750 /* format IFP_SINGLE_WIDE_F2_3fmt */ 12751 /* nFields */ 1, 12752 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_2_BCM53400_A0fmt_fields, 12753 /* bits */ 128, 12754 /* flags */ 0, 12755 }, 12756 #endif /* chips */ 12757 12758 #if defined(BCM_56270_A0) 12759 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_3_BCM56270_A0fmt */ 12760 /* format IFP_SINGLE_WIDE_F2_3fmt */ 12761 /* nFields */ 1, 12762 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_2_BCM53400_A0fmt_fields, 12763 /* bits */ 128, 12764 /* flags */ 0, 12765 }, 12766 #endif /* chips */ 12767 12768 #if defined(BCM_56334_A0) 12769 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_3_BCM56334_A0fmt */ 12770 /* format IFP_SINGLE_WIDE_F2_3fmt */ 12771 /* nFields */ 1, 12772 /* *fields */ soc_IFP_SINGLE_WIDE_F2_3fmt_fields, 12773 /* bits */ 128, 12774 /* flags */ 0, 12775 }, 12776 #endif /* chips */ 12777 12778 #if defined(BCM_56340_A0) 12779 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_3_BCM56340_A0fmt */ 12780 /* format IFP_SINGLE_WIDE_F2_3fmt */ 12781 /* nFields */ 1, 12782 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_2_BCM56640_A0fmt_fields, 12783 /* bits */ 128, 12784 /* flags */ 0, 12785 }, 12786 #endif /* chips */ 12787 12788 #if defined(BCM_56450_A0) 12789 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_3_BCM56450_A0fmt */ 12790 /* format IFP_SINGLE_WIDE_F2_3fmt */ 12791 /* nFields */ 1, 12792 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_2_BCM56640_A0fmt_fields, 12793 /* bits */ 128, 12794 /* flags */ 0, 12795 }, 12796 #endif /* chips */ 12797 12798 #if defined(BCM_56450_B0) 12799 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_3_BCM56450_B0fmt */ 12800 /* format IFP_SINGLE_WIDE_F2_3fmt */ 12801 /* nFields */ 1, 12802 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_2_BCM56640_A0fmt_fields, 12803 /* bits */ 128, 12804 /* flags */ 0, 12805 }, 12806 #endif /* chips */ 12807 12808 #if defined(BCM_56450_B1) 12809 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_3_BCM56450_B1fmt */ 12810 /* format IFP_SINGLE_WIDE_F2_3fmt */ 12811 /* nFields */ 1, 12812 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_2_BCM56640_A0fmt_fields, 12813 /* bits */ 128, 12814 /* flags */ 0, 12815 }, 12816 #endif /* chips */ 12817 12818 #if defined(BCM_56560_A0) 12819 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_3_BCM56560_A0fmt */ 12820 /* format IFP_SINGLE_WIDE_F2_3fmt */ 12821 /* nFields */ 28, 12822 /* *fields */ soc_IFP_SINGLE_WIDE_F2_3_BCM56560_A0fmt_fields, 12823 /* bits */ 128, 12824 /* flags */ 0, 12825 }, 12826 #endif /* chips */ 12827 12828 #if defined(BCM_56560_B0) 12829 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_3_BCM56560_B0fmt */ 12830 /* format IFP_SINGLE_WIDE_F2_3fmt */ 12831 /* nFields */ 28, 12832 /* *fields */ soc_IFP_SINGLE_WIDE_F2_3_BCM56560_A0fmt_fields, 12833 /* bits */ 128, 12834 /* flags */ 0, 12835 }, 12836 #endif /* chips */ 12837 12838 #if defined(BCM_56640_A0) 12839 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_3_BCM56640_A0fmt */ 12840 /* format IFP_SINGLE_WIDE_F2_3fmt */ 12841 /* nFields */ 1, 12842 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_2_BCM56640_A0fmt_fields, 12843 /* bits */ 128, 12844 /* flags */ 0, 12845 }, 12846 #endif /* chips */ 12847 12848 #if defined(BCM_56670_A0) 12849 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_3_BCM56670_A0fmt */ 12850 /* format IFP_SINGLE_WIDE_F2_3fmt */ 12851 /* nFields */ 28, 12852 /* *fields */ soc_IFP_SINGLE_WIDE_F2_3_BCM56560_A0fmt_fields, 12853 /* bits */ 128, 12854 /* flags */ 0, 12855 }, 12856 #endif /* chips */ 12857 12858 #if defined(BCM_56670_B0) 12859 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_3_BCM56670_B0fmt */ 12860 /* format IFP_SINGLE_WIDE_F2_3fmt */ 12861 /* nFields */ 29, 12862 /* *fields */ soc_IFP_SINGLE_WIDE_F2_3_BCM56670_B0fmt_fields, 12863 /* bits */ 128, 12864 /* flags */ 0, 12865 }, 12866 #endif /* chips */ 12867 12868 #if defined(BCM_56680_B0) 12869 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_3_BCM56680_B0fmt */ 12870 /* format IFP_SINGLE_WIDE_F2_3fmt */ 12871 /* nFields */ 1, 12872 /* *fields */ soc_IFP_SINGLE_WIDE_F2_3fmt_fields, 12873 /* bits */ 128, 12874 /* flags */ 0, 12875 }, 12876 #endif /* chips */ 12877 12878 #if defined(BCM_56685_B0) 12879 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_3_BCM56685_B0fmt */ 12880 /* format IFP_SINGLE_WIDE_F2_3fmt */ 12881 /* nFields */ 1, 12882 /* *fields */ soc_IFP_SINGLE_WIDE_F2_3fmt_fields, 12883 /* bits */ 128, 12884 /* flags */ 0, 12885 }, 12886 #endif /* chips */ 12887 12888 #if defined(BCM_56850_A0) 12889 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_3_BCM56850_A0fmt */ 12890 /* format IFP_SINGLE_WIDE_F2_3fmt */ 12891 /* nFields */ 1, 12892 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_2_BCM56640_A0fmt_fields, 12893 /* bits */ 128, 12894 /* flags */ 0, 12895 }, 12896 #endif /* chips */ 12897 12898 #if defined(BCM_56860_A0) 12899 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_3_BCM56860_A0fmt */ 12900 /* format IFP_SINGLE_WIDE_F2_3fmt */ 12901 /* nFields */ 28, 12902 /* *fields */ soc_IFP_SINGLE_WIDE_F2_3_BCM56860_A0fmt_fields, 12903 /* bits */ 128, 12904 /* flags */ 0, 12905 }, 12906 #endif /* chips */ 12907 12908 #if defined(BCM_53400_A0) 12909 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_4_BCM53400_A0fmt */ 12910 /* format IFP_SINGLE_WIDE_F2_4fmt */ 12911 /* nFields */ 8, 12912 /* *fields */ soc_IFP_SINGLE_WIDE_F2_4_BCM53400_A0fmt_fields, 12913 /* bits */ 128, 12914 /* flags */ 0, 12915 }, 12916 #endif /* chips */ 12917 12918 #if defined(BCM_53540_A0) 12919 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_4_BCM53540_A0fmt */ 12920 /* format IFP_SINGLE_WIDE_F2_4fmt */ 12921 /* nFields */ 8, 12922 /* *fields */ soc_IFP_SINGLE_WIDE_F2_4_BCM53400_A0fmt_fields, 12923 /* bits */ 128, 12924 /* flags */ 0, 12925 }, 12926 #endif /* chips */ 12927 12928 #if defined(BCM_53570_A0) 12929 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_4_BCM53570_A0fmt */ 12930 /* format IFP_SINGLE_WIDE_F2_4fmt */ 12931 /* nFields */ 8, 12932 /* *fields */ soc_IFP_SINGLE_WIDE_F2_4_BCM53400_A0fmt_fields, 12933 /* bits */ 128, 12934 /* flags */ 0, 12935 }, 12936 #endif /* chips */ 12937 12938 #if defined(BCM_53570_B0) 12939 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_4_BCM53570_B0fmt */ 12940 /* format IFP_SINGLE_WIDE_F2_4fmt */ 12941 /* nFields */ 8, 12942 /* *fields */ soc_IFP_SINGLE_WIDE_F2_4_BCM53400_A0fmt_fields, 12943 /* bits */ 128, 12944 /* flags */ 0, 12945 }, 12946 #endif /* chips */ 12947 12948 #if defined(BCM_56142_A0) 12949 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_4_BCM56142_A0fmt */ 12950 /* format IFP_SINGLE_WIDE_F2_4fmt */ 12951 /* nFields */ 7, 12952 /* *fields */ soc_IFP_SINGLE_WIDE_F2_4_BCM56634_A0fmt_fields, 12953 /* bits */ 128, 12954 /* flags */ 0, 12955 }, 12956 #endif /* chips */ 12957 12958 #if defined(BCM_56150_A0) 12959 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_4_BCM56150_A0fmt */ 12960 /* format IFP_SINGLE_WIDE_F2_4fmt */ 12961 /* nFields */ 7, 12962 /* *fields */ soc_IFP_SINGLE_WIDE_F2_4_BCM56450_A0fmt_fields, 12963 /* bits */ 128, 12964 /* flags */ 0, 12965 }, 12966 #endif /* chips */ 12967 12968 #if defined(BCM_56160_A0) 12969 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_4_BCM56160_A0fmt */ 12970 /* format IFP_SINGLE_WIDE_F2_4fmt */ 12971 /* nFields */ 8, 12972 /* *fields */ soc_IFP_SINGLE_WIDE_F2_4_BCM53400_A0fmt_fields, 12973 /* bits */ 128, 12974 /* flags */ 0, 12975 }, 12976 #endif /* chips */ 12977 12978 #if defined(BCM_56260_A0) 12979 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_4_BCM56260_A0fmt */ 12980 /* format IFP_SINGLE_WIDE_F2_4fmt */ 12981 /* nFields */ 7, 12982 /* *fields */ soc_IFP_SINGLE_WIDE_F2_4_BCM56260_A0fmt_fields, 12983 /* bits */ 128, 12984 /* flags */ 0, 12985 }, 12986 #endif /* chips */ 12987 12988 #if defined(BCM_56260_B0) 12989 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_4_BCM56260_B0fmt */ 12990 /* format IFP_SINGLE_WIDE_F2_4fmt */ 12991 /* nFields */ 7, 12992 /* *fields */ soc_IFP_SINGLE_WIDE_F2_4_BCM56260_A0fmt_fields, 12993 /* bits */ 128, 12994 /* flags */ 0, 12995 }, 12996 #endif /* chips */ 12997 12998 #if defined(BCM_56270_A0) 12999 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_4_BCM56270_A0fmt */ 13000 /* format IFP_SINGLE_WIDE_F2_4fmt */ 13001 /* nFields */ 7, 13002 /* *fields */ soc_IFP_SINGLE_WIDE_F2_4_BCM56260_A0fmt_fields, 13003 /* bits */ 128, 13004 /* flags */ 0, 13005 }, 13006 #endif /* chips */ 13007 13008 #if defined(BCM_56334_A0) 13009 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_4_BCM56334_A0fmt */ 13010 /* format IFP_SINGLE_WIDE_F2_4fmt */ 13011 /* nFields */ 7, 13012 /* *fields */ soc_IFP_SINGLE_WIDE_F2_4_BCM56634_A0fmt_fields, 13013 /* bits */ 128, 13014 /* flags */ 0, 13015 }, 13016 #endif /* chips */ 13017 13018 #if defined(BCM_56334_B0) 13019 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_4_BCM56334_B0fmt */ 13020 /* format IFP_SINGLE_WIDE_F2_4fmt */ 13021 /* nFields */ 7, 13022 /* *fields */ soc_IFP_SINGLE_WIDE_F2_4_BCM56634_A0fmt_fields, 13023 /* bits */ 128, 13024 /* flags */ 0, 13025 }, 13026 #endif /* chips */ 13027 13028 #if defined(BCM_56340_A0) 13029 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_4_BCM56340_A0fmt */ 13030 /* format IFP_SINGLE_WIDE_F2_4fmt */ 13031 /* nFields */ 7, 13032 /* *fields */ soc_IFP_SINGLE_WIDE_F2_4_BCM56640_A0fmt_fields, 13033 /* bits */ 128, 13034 /* flags */ 0, 13035 }, 13036 #endif /* chips */ 13037 13038 #if defined(BCM_56440_A0) 13039 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_4_BCM56440_A0fmt */ 13040 /* format IFP_SINGLE_WIDE_F2_4fmt */ 13041 /* nFields */ 7, 13042 /* *fields */ soc_IFP_SINGLE_WIDE_F2_4_BCM56634_A0fmt_fields, 13043 /* bits */ 128, 13044 /* flags */ 0, 13045 }, 13046 #endif /* chips */ 13047 13048 #if defined(BCM_56440_B0) 13049 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_4_BCM56440_B0fmt */ 13050 /* format IFP_SINGLE_WIDE_F2_4fmt */ 13051 /* nFields */ 7, 13052 /* *fields */ soc_IFP_SINGLE_WIDE_F2_4_BCM56634_A0fmt_fields, 13053 /* bits */ 128, 13054 /* flags */ 0, 13055 }, 13056 #endif /* chips */ 13057 13058 #if defined(BCM_56450_A0) 13059 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_4_BCM56450_A0fmt */ 13060 /* format IFP_SINGLE_WIDE_F2_4fmt */ 13061 /* nFields */ 7, 13062 /* *fields */ soc_IFP_SINGLE_WIDE_F2_4_BCM56450_A0fmt_fields, 13063 /* bits */ 128, 13064 /* flags */ 0, 13065 }, 13066 #endif /* chips */ 13067 13068 #if defined(BCM_56450_B0) 13069 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_4_BCM56450_B0fmt */ 13070 /* format IFP_SINGLE_WIDE_F2_4fmt */ 13071 /* nFields */ 7, 13072 /* *fields */ soc_IFP_SINGLE_WIDE_F2_4_BCM56450_A0fmt_fields, 13073 /* bits */ 128, 13074 /* flags */ 0, 13075 }, 13076 #endif /* chips */ 13077 13078 #if defined(BCM_56450_B1) 13079 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_4_BCM56450_B1fmt */ 13080 /* format IFP_SINGLE_WIDE_F2_4fmt */ 13081 /* nFields */ 7, 13082 /* *fields */ soc_IFP_SINGLE_WIDE_F2_4_BCM56450_A0fmt_fields, 13083 /* bits */ 128, 13084 /* flags */ 0, 13085 }, 13086 #endif /* chips */ 13087 13088 #if defined(BCM_56524_A0) 13089 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_4_BCM56524_A0fmt */ 13090 /* format IFP_SINGLE_WIDE_F2_4fmt */ 13091 /* nFields */ 7, 13092 /* *fields */ soc_IFP_SINGLE_WIDE_F2_4_BCM56634_A0fmt_fields, 13093 /* bits */ 128, 13094 /* flags */ 0, 13095 }, 13096 #endif /* chips */ 13097 13098 #if defined(BCM_56524_B0) 13099 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_4_BCM56524_B0fmt */ 13100 /* format IFP_SINGLE_WIDE_F2_4fmt */ 13101 /* nFields */ 7, 13102 /* *fields */ soc_IFP_SINGLE_WIDE_F2_4_BCM56634_A0fmt_fields, 13103 /* bits */ 128, 13104 /* flags */ 0, 13105 }, 13106 #endif /* chips */ 13107 13108 #if defined(BCM_56560_A0) 13109 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_4_BCM56560_A0fmt */ 13110 /* format IFP_SINGLE_WIDE_F2_4fmt */ 13111 /* nFields */ 7, 13112 /* *fields */ soc_IFP_SINGLE_WIDE_F2_4_BCM56560_A0fmt_fields, 13113 /* bits */ 128, 13114 /* flags */ 0, 13115 }, 13116 #endif /* chips */ 13117 13118 #if defined(BCM_56560_B0) 13119 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_4_BCM56560_B0fmt */ 13120 /* format IFP_SINGLE_WIDE_F2_4fmt */ 13121 /* nFields */ 7, 13122 /* *fields */ soc_IFP_SINGLE_WIDE_F2_4_BCM56560_A0fmt_fields, 13123 /* bits */ 128, 13124 /* flags */ 0, 13125 }, 13126 #endif /* chips */ 13127 13128 #if defined(BCM_56634_A0) 13129 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_4_BCM56634_A0fmt */ 13130 /* format IFP_SINGLE_WIDE_F2_4fmt */ 13131 /* nFields */ 7, 13132 /* *fields */ soc_IFP_SINGLE_WIDE_F2_4_BCM56634_A0fmt_fields, 13133 /* bits */ 128, 13134 /* flags */ 0, 13135 }, 13136 #endif /* chips */ 13137 13138 #if defined(BCM_56634_B0) 13139 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_4_BCM56634_B0fmt */ 13140 /* format IFP_SINGLE_WIDE_F2_4fmt */ 13141 /* nFields */ 7, 13142 /* *fields */ soc_IFP_SINGLE_WIDE_F2_4_BCM56634_A0fmt_fields, 13143 /* bits */ 128, 13144 /* flags */ 0, 13145 }, 13146 #endif /* chips */ 13147 13148 #if defined(BCM_56640_A0) 13149 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_4_BCM56640_A0fmt */ 13150 /* format IFP_SINGLE_WIDE_F2_4fmt */ 13151 /* nFields */ 7, 13152 /* *fields */ soc_IFP_SINGLE_WIDE_F2_4_BCM56640_A0fmt_fields, 13153 /* bits */ 128, 13154 /* flags */ 0, 13155 }, 13156 #endif /* chips */ 13157 13158 #if defined(BCM_56670_A0) 13159 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_4_BCM56670_A0fmt */ 13160 /* format IFP_SINGLE_WIDE_F2_4fmt */ 13161 /* nFields */ 7, 13162 /* *fields */ soc_IFP_SINGLE_WIDE_F2_4_BCM56560_A0fmt_fields, 13163 /* bits */ 128, 13164 /* flags */ 0, 13165 }, 13166 #endif /* chips */ 13167 13168 #if defined(BCM_56670_B0) 13169 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_4_BCM56670_B0fmt */ 13170 /* format IFP_SINGLE_WIDE_F2_4fmt */ 13171 /* nFields */ 7, 13172 /* *fields */ soc_IFP_SINGLE_WIDE_F2_4_BCM56560_A0fmt_fields, 13173 /* bits */ 128, 13174 /* flags */ 0, 13175 }, 13176 #endif /* chips */ 13177 13178 #if defined(BCM_56680_B0) 13179 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_4_BCM56680_B0fmt */ 13180 /* format IFP_SINGLE_WIDE_F2_4fmt */ 13181 /* nFields */ 7, 13182 /* *fields */ soc_IFP_SINGLE_WIDE_F2_4fmt_fields, 13183 /* bits */ 128, 13184 /* flags */ 0, 13185 }, 13186 #endif /* chips */ 13187 13188 #if defined(BCM_56685_A0) 13189 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_4_BCM56685_A0fmt */ 13190 /* format IFP_SINGLE_WIDE_F2_4fmt */ 13191 /* nFields */ 7, 13192 /* *fields */ soc_IFP_SINGLE_WIDE_F2_4_BCM56634_A0fmt_fields, 13193 /* bits */ 128, 13194 /* flags */ 0, 13195 }, 13196 #endif /* chips */ 13197 13198 #if defined(BCM_56685_B0) 13199 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_4_BCM56685_B0fmt */ 13200 /* format IFP_SINGLE_WIDE_F2_4fmt */ 13201 /* nFields */ 7, 13202 /* *fields */ soc_IFP_SINGLE_WIDE_F2_4_BCM56634_A0fmt_fields, 13203 /* bits */ 128, 13204 /* flags */ 0, 13205 }, 13206 #endif /* chips */ 13207 13208 #if defined(BCM_56840_A0) 13209 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_4_BCM56840_A0fmt */ 13210 /* format IFP_SINGLE_WIDE_F2_4fmt */ 13211 /* nFields */ 7, 13212 /* *fields */ soc_IFP_SINGLE_WIDE_F2_4_BCM56840_A0fmt_fields, 13213 /* bits */ 128, 13214 /* flags */ 0, 13215 }, 13216 #endif /* chips */ 13217 13218 #if defined(BCM_56840_B0) 13219 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_4_BCM56840_B0fmt */ 13220 /* format IFP_SINGLE_WIDE_F2_4fmt */ 13221 /* nFields */ 7, 13222 /* *fields */ soc_IFP_SINGLE_WIDE_F2_4_BCM56840_A0fmt_fields, 13223 /* bits */ 128, 13224 /* flags */ 0, 13225 }, 13226 #endif /* chips */ 13227 13228 #if defined(BCM_56850_A0) 13229 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_4_BCM56850_A0fmt */ 13230 /* format IFP_SINGLE_WIDE_F2_4fmt */ 13231 /* nFields */ 8, 13232 /* *fields */ soc_IFP_SINGLE_WIDE_F2_4_BCM56850_A0fmt_fields, 13233 /* bits */ 128, 13234 /* flags */ 0, 13235 }, 13236 #endif /* chips */ 13237 13238 #if defined(BCM_56860_A0) 13239 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_4_BCM56860_A0fmt */ 13240 /* format IFP_SINGLE_WIDE_F2_4fmt */ 13241 /* nFields */ 7, 13242 /* *fields */ soc_IFP_SINGLE_WIDE_F2_4_BCM56860_A0fmt_fields, 13243 /* bits */ 128, 13244 /* flags */ 0, 13245 }, 13246 #endif /* chips */ 13247 13248 #if defined(BCM_88732_A0) 13249 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_4_BCM88732_A0fmt */ 13250 /* format IFP_SINGLE_WIDE_F2_4fmt */ 13251 /* nFields */ 7, 13252 /* *fields */ soc_IFP_SINGLE_WIDE_F2_4_BCM88732_A0fmt_fields, 13253 /* bits */ 128, 13254 /* flags */ 0, 13255 }, 13256 #endif /* chips */ 13257 13258 #if defined(BCM_53400_A0) 13259 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_5_BCM53400_A0fmt */ 13260 /* format IFP_SINGLE_WIDE_F2_5fmt */ 13261 /* nFields */ 4, 13262 /* *fields */ soc_IFP_SINGLE_WIDE_F2_5_BCM53400_A0fmt_fields, 13263 /* bits */ 128, 13264 /* flags */ 0, 13265 }, 13266 #endif /* chips */ 13267 13268 #if defined(BCM_53540_A0) 13269 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_5_BCM53540_A0fmt */ 13270 /* format IFP_SINGLE_WIDE_F2_5fmt */ 13271 /* nFields */ 4, 13272 /* *fields */ soc_IFP_SINGLE_WIDE_F2_5_BCM53400_A0fmt_fields, 13273 /* bits */ 128, 13274 /* flags */ 0, 13275 }, 13276 #endif /* chips */ 13277 13278 #if defined(BCM_53570_A0) 13279 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_5_BCM53570_A0fmt */ 13280 /* format IFP_SINGLE_WIDE_F2_5fmt */ 13281 /* nFields */ 4, 13282 /* *fields */ soc_IFP_SINGLE_WIDE_F2_5_BCM53400_A0fmt_fields, 13283 /* bits */ 128, 13284 /* flags */ 0, 13285 }, 13286 #endif /* chips */ 13287 13288 #if defined(BCM_53570_B0) 13289 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_5_BCM53570_B0fmt */ 13290 /* format IFP_SINGLE_WIDE_F2_5fmt */ 13291 /* nFields */ 4, 13292 /* *fields */ soc_IFP_SINGLE_WIDE_F2_5_BCM53400_A0fmt_fields, 13293 /* bits */ 128, 13294 /* flags */ 0, 13295 }, 13296 #endif /* chips */ 13297 13298 #if defined(BCM_56142_A0) 13299 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_5_BCM56142_A0fmt */ 13300 /* format IFP_SINGLE_WIDE_F2_5fmt */ 13301 /* nFields */ 4, 13302 /* *fields */ soc_IFP_SINGLE_WIDE_F2_5fmt_fields, 13303 /* bits */ 128, 13304 /* flags */ 0, 13305 }, 13306 #endif /* chips */ 13307 13308 #if defined(BCM_56150_A0) 13309 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_5_BCM56150_A0fmt */ 13310 /* format IFP_SINGLE_WIDE_F2_5fmt */ 13311 /* nFields */ 4, 13312 /* *fields */ soc_IFP_SINGLE_WIDE_F2_5_BCM56640_A0fmt_fields, 13313 /* bits */ 128, 13314 /* flags */ 0, 13315 }, 13316 #endif /* chips */ 13317 13318 #if defined(BCM_56160_A0) 13319 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_5_BCM56160_A0fmt */ 13320 /* format IFP_SINGLE_WIDE_F2_5fmt */ 13321 /* nFields */ 4, 13322 /* *fields */ soc_IFP_SINGLE_WIDE_F2_5_BCM53400_A0fmt_fields, 13323 /* bits */ 128, 13324 /* flags */ 0, 13325 }, 13326 #endif /* chips */ 13327 13328 #if defined(BCM_56260_A0) 13329 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_5_BCM56260_A0fmt */ 13330 /* format IFP_SINGLE_WIDE_F2_5fmt */ 13331 /* nFields */ 4, 13332 /* *fields */ soc_IFP_SINGLE_WIDE_F2_5_BCM53400_A0fmt_fields, 13333 /* bits */ 128, 13334 /* flags */ 0, 13335 }, 13336 #endif /* chips */ 13337 13338 #if defined(BCM_56260_B0) 13339 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_5_BCM56260_B0fmt */ 13340 /* format IFP_SINGLE_WIDE_F2_5fmt */ 13341 /* nFields */ 4, 13342 /* *fields */ soc_IFP_SINGLE_WIDE_F2_5_BCM53400_A0fmt_fields, 13343 /* bits */ 128, 13344 /* flags */ 0, 13345 }, 13346 #endif /* chips */ 13347 13348 #if defined(BCM_56270_A0) 13349 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_5_BCM56270_A0fmt */ 13350 /* format IFP_SINGLE_WIDE_F2_5fmt */ 13351 /* nFields */ 4, 13352 /* *fields */ soc_IFP_SINGLE_WIDE_F2_5_BCM53400_A0fmt_fields, 13353 /* bits */ 128, 13354 /* flags */ 0, 13355 }, 13356 #endif /* chips */ 13357 13358 #if defined(BCM_56334_A0) 13359 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_5_BCM56334_A0fmt */ 13360 /* format IFP_SINGLE_WIDE_F2_5fmt */ 13361 /* nFields */ 4, 13362 /* *fields */ soc_IFP_SINGLE_WIDE_F2_5fmt_fields, 13363 /* bits */ 128, 13364 /* flags */ 0, 13365 }, 13366 #endif /* chips */ 13367 13368 #if defined(BCM_56334_B0) 13369 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_5_BCM56334_B0fmt */ 13370 /* format IFP_SINGLE_WIDE_F2_5fmt */ 13371 /* nFields */ 4, 13372 /* *fields */ soc_IFP_SINGLE_WIDE_F2_5fmt_fields, 13373 /* bits */ 128, 13374 /* flags */ 0, 13375 }, 13376 #endif /* chips */ 13377 13378 #if defined(BCM_56340_A0) 13379 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_5_BCM56340_A0fmt */ 13380 /* format IFP_SINGLE_WIDE_F2_5fmt */ 13381 /* nFields */ 4, 13382 /* *fields */ soc_IFP_SINGLE_WIDE_F2_5_BCM56640_A0fmt_fields, 13383 /* bits */ 128, 13384 /* flags */ 0, 13385 }, 13386 #endif /* chips */ 13387 13388 #if defined(BCM_56450_A0) 13389 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_5_BCM56450_A0fmt */ 13390 /* format IFP_SINGLE_WIDE_F2_5fmt */ 13391 /* nFields */ 4, 13392 /* *fields */ soc_IFP_SINGLE_WIDE_F2_5_BCM56640_A0fmt_fields, 13393 /* bits */ 128, 13394 /* flags */ 0, 13395 }, 13396 #endif /* chips */ 13397 13398 #if defined(BCM_56450_B0) 13399 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_5_BCM56450_B0fmt */ 13400 /* format IFP_SINGLE_WIDE_F2_5fmt */ 13401 /* nFields */ 4, 13402 /* *fields */ soc_IFP_SINGLE_WIDE_F2_5_BCM56640_A0fmt_fields, 13403 /* bits */ 128, 13404 /* flags */ 0, 13405 }, 13406 #endif /* chips */ 13407 13408 #if defined(BCM_56450_B1) 13409 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_5_BCM56450_B1fmt */ 13410 /* format IFP_SINGLE_WIDE_F2_5fmt */ 13411 /* nFields */ 4, 13412 /* *fields */ soc_IFP_SINGLE_WIDE_F2_5_BCM56640_A0fmt_fields, 13413 /* bits */ 128, 13414 /* flags */ 0, 13415 }, 13416 #endif /* chips */ 13417 13418 #if defined(BCM_56560_A0) 13419 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_5_BCM56560_A0fmt */ 13420 /* format IFP_SINGLE_WIDE_F2_5fmt */ 13421 /* nFields */ 4, 13422 /* *fields */ soc_IFP_SINGLE_WIDE_F2_5_BCM53400_A0fmt_fields, 13423 /* bits */ 128, 13424 /* flags */ 0, 13425 }, 13426 #endif /* chips */ 13427 13428 #if defined(BCM_56560_B0) 13429 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_5_BCM56560_B0fmt */ 13430 /* format IFP_SINGLE_WIDE_F2_5fmt */ 13431 /* nFields */ 4, 13432 /* *fields */ soc_IFP_SINGLE_WIDE_F2_5_BCM53400_A0fmt_fields, 13433 /* bits */ 128, 13434 /* flags */ 0, 13435 }, 13436 #endif /* chips */ 13437 13438 #if defined(BCM_56640_A0) 13439 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_5_BCM56640_A0fmt */ 13440 /* format IFP_SINGLE_WIDE_F2_5fmt */ 13441 /* nFields */ 4, 13442 /* *fields */ soc_IFP_SINGLE_WIDE_F2_5_BCM56640_A0fmt_fields, 13443 /* bits */ 128, 13444 /* flags */ 0, 13445 }, 13446 #endif /* chips */ 13447 13448 #if defined(BCM_56670_A0) 13449 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_5_BCM56670_A0fmt */ 13450 /* format IFP_SINGLE_WIDE_F2_5fmt */ 13451 /* nFields */ 4, 13452 /* *fields */ soc_IFP_SINGLE_WIDE_F2_5_BCM53400_A0fmt_fields, 13453 /* bits */ 128, 13454 /* flags */ 0, 13455 }, 13456 #endif /* chips */ 13457 13458 #if defined(BCM_56670_B0) 13459 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_5_BCM56670_B0fmt */ 13460 /* format IFP_SINGLE_WIDE_F2_5fmt */ 13461 /* nFields */ 4, 13462 /* *fields */ soc_IFP_SINGLE_WIDE_F2_5_BCM53400_A0fmt_fields, 13463 /* bits */ 128, 13464 /* flags */ 0, 13465 }, 13466 #endif /* chips */ 13467 13468 #if defined(BCM_56680_B0) 13469 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_5_BCM56680_B0fmt */ 13470 /* format IFP_SINGLE_WIDE_F2_5fmt */ 13471 /* nFields */ 4, 13472 /* *fields */ soc_IFP_SINGLE_WIDE_F2_5fmt_fields, 13473 /* bits */ 128, 13474 /* flags */ 0, 13475 }, 13476 #endif /* chips */ 13477 13478 #if defined(BCM_56685_B0) 13479 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_5_BCM56685_B0fmt */ 13480 /* format IFP_SINGLE_WIDE_F2_5fmt */ 13481 /* nFields */ 4, 13482 /* *fields */ soc_IFP_SINGLE_WIDE_F2_5fmt_fields, 13483 /* bits */ 128, 13484 /* flags */ 0, 13485 }, 13486 #endif /* chips */ 13487 13488 #if defined(BCM_56850_A0) 13489 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_5_BCM56850_A0fmt */ 13490 /* format IFP_SINGLE_WIDE_F2_5fmt */ 13491 /* nFields */ 4, 13492 /* *fields */ soc_IFP_SINGLE_WIDE_F2_5_BCM56640_A0fmt_fields, 13493 /* bits */ 128, 13494 /* flags */ 0, 13495 }, 13496 #endif /* chips */ 13497 13498 #if defined(BCM_56860_A0) 13499 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_5_BCM56860_A0fmt */ 13500 /* format IFP_SINGLE_WIDE_F2_5fmt */ 13501 /* nFields */ 4, 13502 /* *fields */ soc_IFP_SINGLE_WIDE_F2_5_BCM56640_A0fmt_fields, 13503 /* bits */ 128, 13504 /* flags */ 0, 13505 }, 13506 #endif /* chips */ 13507 13508 #if defined(BCM_53400_A0) 13509 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_6_BCM53400_A0fmt */ 13510 /* format IFP_SINGLE_WIDE_F2_6fmt */ 13511 /* nFields */ 5, 13512 /* *fields */ soc_IFP_SINGLE_WIDE_F2_6_BCM53400_A0fmt_fields, 13513 /* bits */ 128, 13514 /* flags */ 0, 13515 }, 13516 #endif /* chips */ 13517 13518 #if defined(BCM_53540_A0) 13519 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_6_BCM53540_A0fmt */ 13520 /* format IFP_SINGLE_WIDE_F2_6fmt */ 13521 /* nFields */ 5, 13522 /* *fields */ soc_IFP_SINGLE_WIDE_F2_6_BCM53400_A0fmt_fields, 13523 /* bits */ 128, 13524 /* flags */ 0, 13525 }, 13526 #endif /* chips */ 13527 13528 #if defined(BCM_53570_A0) 13529 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_6_BCM53570_A0fmt */ 13530 /* format IFP_SINGLE_WIDE_F2_6fmt */ 13531 /* nFields */ 5, 13532 /* *fields */ soc_IFP_SINGLE_WIDE_F2_6_BCM53400_A0fmt_fields, 13533 /* bits */ 128, 13534 /* flags */ 0, 13535 }, 13536 #endif /* chips */ 13537 13538 #if defined(BCM_53570_B0) 13539 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_6_BCM53570_B0fmt */ 13540 /* format IFP_SINGLE_WIDE_F2_6fmt */ 13541 /* nFields */ 5, 13542 /* *fields */ soc_IFP_SINGLE_WIDE_F2_6_BCM53400_A0fmt_fields, 13543 /* bits */ 128, 13544 /* flags */ 0, 13545 }, 13546 #endif /* chips */ 13547 13548 #if defined(BCM_56142_A0) 13549 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_6_BCM56142_A0fmt */ 13550 /* format IFP_SINGLE_WIDE_F2_6fmt */ 13551 /* nFields */ 5, 13552 /* *fields */ soc_IFP_SINGLE_WIDE_F2_6_BCM56634_A0fmt_fields, 13553 /* bits */ 128, 13554 /* flags */ 0, 13555 }, 13556 #endif /* chips */ 13557 13558 #if defined(BCM_56150_A0) 13559 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_6_BCM56150_A0fmt */ 13560 /* format IFP_SINGLE_WIDE_F2_6fmt */ 13561 /* nFields */ 5, 13562 /* *fields */ soc_IFP_SINGLE_WIDE_F2_6_BCM56640_A0fmt_fields, 13563 /* bits */ 128, 13564 /* flags */ 0, 13565 }, 13566 #endif /* chips */ 13567 13568 #if defined(BCM_56160_A0) 13569 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_6_BCM56160_A0fmt */ 13570 /* format IFP_SINGLE_WIDE_F2_6fmt */ 13571 /* nFields */ 5, 13572 /* *fields */ soc_IFP_SINGLE_WIDE_F2_6_BCM53400_A0fmt_fields, 13573 /* bits */ 128, 13574 /* flags */ 0, 13575 }, 13576 #endif /* chips */ 13577 13578 #if defined(BCM_56260_A0) 13579 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_6_BCM56260_A0fmt */ 13580 /* format IFP_SINGLE_WIDE_F2_6fmt */ 13581 /* nFields */ 5, 13582 /* *fields */ soc_IFP_SINGLE_WIDE_F2_6_BCM53400_A0fmt_fields, 13583 /* bits */ 128, 13584 /* flags */ 0, 13585 }, 13586 #endif /* chips */ 13587 13588 #if defined(BCM_56260_B0) 13589 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_6_BCM56260_B0fmt */ 13590 /* format IFP_SINGLE_WIDE_F2_6fmt */ 13591 /* nFields */ 5, 13592 /* *fields */ soc_IFP_SINGLE_WIDE_F2_6_BCM53400_A0fmt_fields, 13593 /* bits */ 128, 13594 /* flags */ 0, 13595 }, 13596 #endif /* chips */ 13597 13598 #if defined(BCM_56270_A0) 13599 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_6_BCM56270_A0fmt */ 13600 /* format IFP_SINGLE_WIDE_F2_6fmt */ 13601 /* nFields */ 5, 13602 /* *fields */ soc_IFP_SINGLE_WIDE_F2_6_BCM53400_A0fmt_fields, 13603 /* bits */ 128, 13604 /* flags */ 0, 13605 }, 13606 #endif /* chips */ 13607 13608 #if defined(BCM_56334_A0) 13609 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_6_BCM56334_A0fmt */ 13610 /* format IFP_SINGLE_WIDE_F2_6fmt */ 13611 /* nFields */ 5, 13612 /* *fields */ soc_IFP_SINGLE_WIDE_F2_6_BCM56634_A0fmt_fields, 13613 /* bits */ 128, 13614 /* flags */ 0, 13615 }, 13616 #endif /* chips */ 13617 13618 #if defined(BCM_56334_B0) 13619 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_6_BCM56334_B0fmt */ 13620 /* format IFP_SINGLE_WIDE_F2_6fmt */ 13621 /* nFields */ 5, 13622 /* *fields */ soc_IFP_SINGLE_WIDE_F2_6_BCM56634_A0fmt_fields, 13623 /* bits */ 128, 13624 /* flags */ 0, 13625 }, 13626 #endif /* chips */ 13627 13628 #if defined(BCM_56340_A0) 13629 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_6_BCM56340_A0fmt */ 13630 /* format IFP_SINGLE_WIDE_F2_6fmt */ 13631 /* nFields */ 5, 13632 /* *fields */ soc_IFP_SINGLE_WIDE_F2_6_BCM56640_A0fmt_fields, 13633 /* bits */ 128, 13634 /* flags */ 0, 13635 }, 13636 #endif /* chips */ 13637 13638 #if defined(BCM_56440_A0) 13639 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_6_BCM56440_A0fmt */ 13640 /* format IFP_SINGLE_WIDE_F2_6fmt */ 13641 /* nFields */ 5, 13642 /* *fields */ soc_IFP_SINGLE_WIDE_F2_6_BCM56634_A0fmt_fields, 13643 /* bits */ 128, 13644 /* flags */ 0, 13645 }, 13646 #endif /* chips */ 13647 13648 #if defined(BCM_56440_B0) 13649 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_6_BCM56440_B0fmt */ 13650 /* format IFP_SINGLE_WIDE_F2_6fmt */ 13651 /* nFields */ 5, 13652 /* *fields */ soc_IFP_SINGLE_WIDE_F2_6_BCM56634_A0fmt_fields, 13653 /* bits */ 128, 13654 /* flags */ 0, 13655 }, 13656 #endif /* chips */ 13657 13658 #if defined(BCM_56450_A0) 13659 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_6_BCM56450_A0fmt */ 13660 /* format IFP_SINGLE_WIDE_F2_6fmt */ 13661 /* nFields */ 5, 13662 /* *fields */ soc_IFP_SINGLE_WIDE_F2_6_BCM56640_A0fmt_fields, 13663 /* bits */ 128, 13664 /* flags */ 0, 13665 }, 13666 #endif /* chips */ 13667 13668 #if defined(BCM_56450_B0) 13669 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_6_BCM56450_B0fmt */ 13670 /* format IFP_SINGLE_WIDE_F2_6fmt */ 13671 /* nFields */ 5, 13672 /* *fields */ soc_IFP_SINGLE_WIDE_F2_6_BCM56640_A0fmt_fields, 13673 /* bits */ 128, 13674 /* flags */ 0, 13675 }, 13676 #endif /* chips */ 13677 13678 #if defined(BCM_56450_B1) 13679 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_6_BCM56450_B1fmt */ 13680 /* format IFP_SINGLE_WIDE_F2_6fmt */ 13681 /* nFields */ 5, 13682 /* *fields */ soc_IFP_SINGLE_WIDE_F2_6_BCM56640_A0fmt_fields, 13683 /* bits */ 128, 13684 /* flags */ 0, 13685 }, 13686 #endif /* chips */ 13687 13688 #if defined(BCM_56524_A0) 13689 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_6_BCM56524_A0fmt */ 13690 /* format IFP_SINGLE_WIDE_F2_6fmt */ 13691 /* nFields */ 5, 13692 /* *fields */ soc_IFP_SINGLE_WIDE_F2_6_BCM56634_A0fmt_fields, 13693 /* bits */ 128, 13694 /* flags */ 0, 13695 }, 13696 #endif /* chips */ 13697 13698 #if defined(BCM_56524_B0) 13699 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_6_BCM56524_B0fmt */ 13700 /* format IFP_SINGLE_WIDE_F2_6fmt */ 13701 /* nFields */ 5, 13702 /* *fields */ soc_IFP_SINGLE_WIDE_F2_6_BCM56634_A0fmt_fields, 13703 /* bits */ 128, 13704 /* flags */ 0, 13705 }, 13706 #endif /* chips */ 13707 13708 #if defined(BCM_56560_A0) 13709 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_6_BCM56560_A0fmt */ 13710 /* format IFP_SINGLE_WIDE_F2_6fmt */ 13711 /* nFields */ 5, 13712 /* *fields */ soc_IFP_SINGLE_WIDE_F2_6_BCM53400_A0fmt_fields, 13713 /* bits */ 128, 13714 /* flags */ 0, 13715 }, 13716 #endif /* chips */ 13717 13718 #if defined(BCM_56560_B0) 13719 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_6_BCM56560_B0fmt */ 13720 /* format IFP_SINGLE_WIDE_F2_6fmt */ 13721 /* nFields */ 5, 13722 /* *fields */ soc_IFP_SINGLE_WIDE_F2_6_BCM53400_A0fmt_fields, 13723 /* bits */ 128, 13724 /* flags */ 0, 13725 }, 13726 #endif /* chips */ 13727 13728 #if defined(BCM_56634_A0) 13729 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_6_BCM56634_A0fmt */ 13730 /* format IFP_SINGLE_WIDE_F2_6fmt */ 13731 /* nFields */ 5, 13732 /* *fields */ soc_IFP_SINGLE_WIDE_F2_6_BCM56634_A0fmt_fields, 13733 /* bits */ 128, 13734 /* flags */ 0, 13735 }, 13736 #endif /* chips */ 13737 13738 #if defined(BCM_56634_B0) 13739 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_6_BCM56634_B0fmt */ 13740 /* format IFP_SINGLE_WIDE_F2_6fmt */ 13741 /* nFields */ 5, 13742 /* *fields */ soc_IFP_SINGLE_WIDE_F2_6_BCM56634_A0fmt_fields, 13743 /* bits */ 128, 13744 /* flags */ 0, 13745 }, 13746 #endif /* chips */ 13747 13748 #if defined(BCM_56640_A0) 13749 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_6_BCM56640_A0fmt */ 13750 /* format IFP_SINGLE_WIDE_F2_6fmt */ 13751 /* nFields */ 5, 13752 /* *fields */ soc_IFP_SINGLE_WIDE_F2_6_BCM56640_A0fmt_fields, 13753 /* bits */ 128, 13754 /* flags */ 0, 13755 }, 13756 #endif /* chips */ 13757 13758 #if defined(BCM_56670_A0) 13759 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_6_BCM56670_A0fmt */ 13760 /* format IFP_SINGLE_WIDE_F2_6fmt */ 13761 /* nFields */ 5, 13762 /* *fields */ soc_IFP_SINGLE_WIDE_F2_6_BCM53400_A0fmt_fields, 13763 /* bits */ 128, 13764 /* flags */ 0, 13765 }, 13766 #endif /* chips */ 13767 13768 #if defined(BCM_56670_B0) 13769 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_6_BCM56670_B0fmt */ 13770 /* format IFP_SINGLE_WIDE_F2_6fmt */ 13771 /* nFields */ 5, 13772 /* *fields */ soc_IFP_SINGLE_WIDE_F2_6_BCM53400_A0fmt_fields, 13773 /* bits */ 128, 13774 /* flags */ 0, 13775 }, 13776 #endif /* chips */ 13777 13778 #if defined(BCM_56680_B0) 13779 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_6_BCM56680_B0fmt */ 13780 /* format IFP_SINGLE_WIDE_F2_6fmt */ 13781 /* nFields */ 5, 13782 /* *fields */ soc_IFP_SINGLE_WIDE_F2_6fmt_fields, 13783 /* bits */ 128, 13784 /* flags */ 0, 13785 }, 13786 #endif /* chips */ 13787 13788 #if defined(BCM_56685_A0) 13789 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_6_BCM56685_A0fmt */ 13790 /* format IFP_SINGLE_WIDE_F2_6fmt */ 13791 /* nFields */ 5, 13792 /* *fields */ soc_IFP_SINGLE_WIDE_F2_6_BCM56634_A0fmt_fields, 13793 /* bits */ 128, 13794 /* flags */ 0, 13795 }, 13796 #endif /* chips */ 13797 13798 #if defined(BCM_56685_B0) 13799 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_6_BCM56685_B0fmt */ 13800 /* format IFP_SINGLE_WIDE_F2_6fmt */ 13801 /* nFields */ 5, 13802 /* *fields */ soc_IFP_SINGLE_WIDE_F2_6_BCM56634_A0fmt_fields, 13803 /* bits */ 128, 13804 /* flags */ 0, 13805 }, 13806 #endif /* chips */ 13807 13808 #if defined(BCM_56840_A0) 13809 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_6_BCM56840_A0fmt */ 13810 /* format IFP_SINGLE_WIDE_F2_6fmt */ 13811 /* nFields */ 5, 13812 /* *fields */ soc_IFP_SINGLE_WIDE_F2_6_BCM56634_A0fmt_fields, 13813 /* bits */ 128, 13814 /* flags */ 0, 13815 }, 13816 #endif /* chips */ 13817 13818 #if defined(BCM_56840_B0) 13819 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_6_BCM56840_B0fmt */ 13820 /* format IFP_SINGLE_WIDE_F2_6fmt */ 13821 /* nFields */ 5, 13822 /* *fields */ soc_IFP_SINGLE_WIDE_F2_6_BCM56634_A0fmt_fields, 13823 /* bits */ 128, 13824 /* flags */ 0, 13825 }, 13826 #endif /* chips */ 13827 13828 #if defined(BCM_56850_A0) 13829 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_6_BCM56850_A0fmt */ 13830 /* format IFP_SINGLE_WIDE_F2_6fmt */ 13831 /* nFields */ 5, 13832 /* *fields */ soc_IFP_SINGLE_WIDE_F2_6_BCM56640_A0fmt_fields, 13833 /* bits */ 128, 13834 /* flags */ 0, 13835 }, 13836 #endif /* chips */ 13837 13838 #if defined(BCM_56860_A0) 13839 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_6_BCM56860_A0fmt */ 13840 /* format IFP_SINGLE_WIDE_F2_6fmt */ 13841 /* nFields */ 5, 13842 /* *fields */ soc_IFP_SINGLE_WIDE_F2_6_BCM56640_A0fmt_fields, 13843 /* bits */ 128, 13844 /* flags */ 0, 13845 }, 13846 #endif /* chips */ 13847 13848 #if defined(BCM_88732_A0) 13849 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_6_BCM88732_A0fmt */ 13850 /* format IFP_SINGLE_WIDE_F2_6fmt */ 13851 /* nFields */ 5, 13852 /* *fields */ soc_IFP_SINGLE_WIDE_F2_6_BCM88732_A0fmt_fields, 13853 /* bits */ 128, 13854 /* flags */ 0, 13855 }, 13856 #endif /* chips */ 13857 13858 #if defined(BCM_53400_A0) 13859 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_7_BCM53400_A0fmt */ 13860 /* format IFP_SINGLE_WIDE_F2_7fmt */ 13861 /* nFields */ 6, 13862 /* *fields */ soc_IFP_SINGLE_WIDE_F2_7_BCM53400_A0fmt_fields, 13863 /* bits */ 128, 13864 /* flags */ 0, 13865 }, 13866 #endif /* chips */ 13867 13868 #if defined(BCM_53540_A0) 13869 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_7_BCM53540_A0fmt */ 13870 /* format IFP_SINGLE_WIDE_F2_7fmt */ 13871 /* nFields */ 6, 13872 /* *fields */ soc_IFP_SINGLE_WIDE_F2_7_BCM53400_A0fmt_fields, 13873 /* bits */ 128, 13874 /* flags */ 0, 13875 }, 13876 #endif /* chips */ 13877 13878 #if defined(BCM_53570_A0) 13879 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_7_BCM53570_A0fmt */ 13880 /* format IFP_SINGLE_WIDE_F2_7fmt */ 13881 /* nFields */ 6, 13882 /* *fields */ soc_IFP_SINGLE_WIDE_F2_7_BCM53400_A0fmt_fields, 13883 /* bits */ 128, 13884 /* flags */ 0, 13885 }, 13886 #endif /* chips */ 13887 13888 #if defined(BCM_53570_B0) 13889 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_7_BCM53570_B0fmt */ 13890 /* format IFP_SINGLE_WIDE_F2_7fmt */ 13891 /* nFields */ 6, 13892 /* *fields */ soc_IFP_SINGLE_WIDE_F2_7_BCM53400_A0fmt_fields, 13893 /* bits */ 128, 13894 /* flags */ 0, 13895 }, 13896 #endif /* chips */ 13897 13898 #if defined(BCM_56142_A0) 13899 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_7_BCM56142_A0fmt */ 13900 /* format IFP_SINGLE_WIDE_F2_7fmt */ 13901 /* nFields */ 6, 13902 /* *fields */ soc_IFP_SINGLE_WIDE_F2_7_BCM56634_A0fmt_fields, 13903 /* bits */ 128, 13904 /* flags */ 0, 13905 }, 13906 #endif /* chips */ 13907 13908 #if defined(BCM_56150_A0) 13909 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_7_BCM56150_A0fmt */ 13910 /* format IFP_SINGLE_WIDE_F2_7fmt */ 13911 /* nFields */ 6, 13912 /* *fields */ soc_IFP_SINGLE_WIDE_F2_7_BCM56450_A0fmt_fields, 13913 /* bits */ 128, 13914 /* flags */ 0, 13915 }, 13916 #endif /* chips */ 13917 13918 #if defined(BCM_56160_A0) 13919 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_7_BCM56160_A0fmt */ 13920 /* format IFP_SINGLE_WIDE_F2_7fmt */ 13921 /* nFields */ 6, 13922 /* *fields */ soc_IFP_SINGLE_WIDE_F2_7_BCM53400_A0fmt_fields, 13923 /* bits */ 128, 13924 /* flags */ 0, 13925 }, 13926 #endif /* chips */ 13927 13928 #if defined(BCM_56260_A0) 13929 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_7_BCM56260_A0fmt */ 13930 /* format IFP_SINGLE_WIDE_F2_7fmt */ 13931 /* nFields */ 6, 13932 /* *fields */ soc_IFP_SINGLE_WIDE_F2_7_BCM53400_A0fmt_fields, 13933 /* bits */ 128, 13934 /* flags */ 0, 13935 }, 13936 #endif /* chips */ 13937 13938 #if defined(BCM_56260_B0) 13939 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_7_BCM56260_B0fmt */ 13940 /* format IFP_SINGLE_WIDE_F2_7fmt */ 13941 /* nFields */ 6, 13942 /* *fields */ soc_IFP_SINGLE_WIDE_F2_7_BCM53400_A0fmt_fields, 13943 /* bits */ 128, 13944 /* flags */ 0, 13945 }, 13946 #endif /* chips */ 13947 13948 #if defined(BCM_56270_A0) 13949 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_7_BCM56270_A0fmt */ 13950 /* format IFP_SINGLE_WIDE_F2_7fmt */ 13951 /* nFields */ 6, 13952 /* *fields */ soc_IFP_SINGLE_WIDE_F2_7_BCM53400_A0fmt_fields, 13953 /* bits */ 128, 13954 /* flags */ 0, 13955 }, 13956 #endif /* chips */ 13957 13958 #if defined(BCM_56334_A0) 13959 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_7_BCM56334_A0fmt */ 13960 /* format IFP_SINGLE_WIDE_F2_7fmt */ 13961 /* nFields */ 6, 13962 /* *fields */ soc_IFP_SINGLE_WIDE_F2_7_BCM56634_A0fmt_fields, 13963 /* bits */ 128, 13964 /* flags */ 0, 13965 }, 13966 #endif /* chips */ 13967 13968 #if defined(BCM_56334_B0) 13969 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_7_BCM56334_B0fmt */ 13970 /* format IFP_SINGLE_WIDE_F2_7fmt */ 13971 /* nFields */ 6, 13972 /* *fields */ soc_IFP_SINGLE_WIDE_F2_7_BCM56634_A0fmt_fields, 13973 /* bits */ 128, 13974 /* flags */ 0, 13975 }, 13976 #endif /* chips */ 13977 13978 #if defined(BCM_56340_A0) 13979 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_7_BCM56340_A0fmt */ 13980 /* format IFP_SINGLE_WIDE_F2_7fmt */ 13981 /* nFields */ 6, 13982 /* *fields */ soc_IFP_SINGLE_WIDE_F2_7_BCM56640_A0fmt_fields, 13983 /* bits */ 128, 13984 /* flags */ 0, 13985 }, 13986 #endif /* chips */ 13987 13988 #if defined(BCM_56440_A0) 13989 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_7_BCM56440_A0fmt */ 13990 /* format IFP_SINGLE_WIDE_F2_7fmt */ 13991 /* nFields */ 6, 13992 /* *fields */ soc_IFP_SINGLE_WIDE_F2_7_BCM56634_A0fmt_fields, 13993 /* bits */ 128, 13994 /* flags */ 0, 13995 }, 13996 #endif /* chips */ 13997 13998 #if defined(BCM_56440_B0) 13999 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_7_BCM56440_B0fmt */ 14000 /* format IFP_SINGLE_WIDE_F2_7fmt */ 14001 /* nFields */ 6, 14002 /* *fields */ soc_IFP_SINGLE_WIDE_F2_7_BCM56634_A0fmt_fields, 14003 /* bits */ 128, 14004 /* flags */ 0, 14005 }, 14006 #endif /* chips */ 14007 14008 #if defined(BCM_56450_A0) 14009 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_7_BCM56450_A0fmt */ 14010 /* format IFP_SINGLE_WIDE_F2_7fmt */ 14011 /* nFields */ 6, 14012 /* *fields */ soc_IFP_SINGLE_WIDE_F2_7_BCM56450_A0fmt_fields, 14013 /* bits */ 128, 14014 /* flags */ 0, 14015 }, 14016 #endif /* chips */ 14017 14018 #if defined(BCM_56450_B0) 14019 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_7_BCM56450_B0fmt */ 14020 /* format IFP_SINGLE_WIDE_F2_7fmt */ 14021 /* nFields */ 6, 14022 /* *fields */ soc_IFP_SINGLE_WIDE_F2_7_BCM56450_A0fmt_fields, 14023 /* bits */ 128, 14024 /* flags */ 0, 14025 }, 14026 #endif /* chips */ 14027 14028 #if defined(BCM_56450_B1) 14029 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_7_BCM56450_B1fmt */ 14030 /* format IFP_SINGLE_WIDE_F2_7fmt */ 14031 /* nFields */ 6, 14032 /* *fields */ soc_IFP_SINGLE_WIDE_F2_7_BCM56450_A0fmt_fields, 14033 /* bits */ 128, 14034 /* flags */ 0, 14035 }, 14036 #endif /* chips */ 14037 14038 #if defined(BCM_56524_A0) 14039 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_7_BCM56524_A0fmt */ 14040 /* format IFP_SINGLE_WIDE_F2_7fmt */ 14041 /* nFields */ 6, 14042 /* *fields */ soc_IFP_SINGLE_WIDE_F2_7_BCM56634_A0fmt_fields, 14043 /* bits */ 128, 14044 /* flags */ 0, 14045 }, 14046 #endif /* chips */ 14047 14048 #if defined(BCM_56524_B0) 14049 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_7_BCM56524_B0fmt */ 14050 /* format IFP_SINGLE_WIDE_F2_7fmt */ 14051 /* nFields */ 6, 14052 /* *fields */ soc_IFP_SINGLE_WIDE_F2_7_BCM56634_A0fmt_fields, 14053 /* bits */ 128, 14054 /* flags */ 0, 14055 }, 14056 #endif /* chips */ 14057 14058 #if defined(BCM_56560_A0) 14059 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_7_BCM56560_A0fmt */ 14060 /* format IFP_SINGLE_WIDE_F2_7fmt */ 14061 /* nFields */ 6, 14062 /* *fields */ soc_IFP_SINGLE_WIDE_F2_7_BCM56560_A0fmt_fields, 14063 /* bits */ 128, 14064 /* flags */ 0, 14065 }, 14066 #endif /* chips */ 14067 14068 #if defined(BCM_56560_B0) 14069 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_7_BCM56560_B0fmt */ 14070 /* format IFP_SINGLE_WIDE_F2_7fmt */ 14071 /* nFields */ 6, 14072 /* *fields */ soc_IFP_SINGLE_WIDE_F2_7_BCM56560_A0fmt_fields, 14073 /* bits */ 128, 14074 /* flags */ 0, 14075 }, 14076 #endif /* chips */ 14077 14078 #if defined(BCM_56634_A0) 14079 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_7_BCM56634_A0fmt */ 14080 /* format IFP_SINGLE_WIDE_F2_7fmt */ 14081 /* nFields */ 6, 14082 /* *fields */ soc_IFP_SINGLE_WIDE_F2_7_BCM56634_A0fmt_fields, 14083 /* bits */ 128, 14084 /* flags */ 0, 14085 }, 14086 #endif /* chips */ 14087 14088 #if defined(BCM_56634_B0) 14089 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_7_BCM56634_B0fmt */ 14090 /* format IFP_SINGLE_WIDE_F2_7fmt */ 14091 /* nFields */ 6, 14092 /* *fields */ soc_IFP_SINGLE_WIDE_F2_7_BCM56634_A0fmt_fields, 14093 /* bits */ 128, 14094 /* flags */ 0, 14095 }, 14096 #endif /* chips */ 14097 14098 #if defined(BCM_56640_A0) 14099 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_7_BCM56640_A0fmt */ 14100 /* format IFP_SINGLE_WIDE_F2_7fmt */ 14101 /* nFields */ 6, 14102 /* *fields */ soc_IFP_SINGLE_WIDE_F2_7_BCM56640_A0fmt_fields, 14103 /* bits */ 128, 14104 /* flags */ 0, 14105 }, 14106 #endif /* chips */ 14107 14108 #if defined(BCM_56670_A0) 14109 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_7_BCM56670_A0fmt */ 14110 /* format IFP_SINGLE_WIDE_F2_7fmt */ 14111 /* nFields */ 6, 14112 /* *fields */ soc_IFP_SINGLE_WIDE_F2_7_BCM56560_A0fmt_fields, 14113 /* bits */ 128, 14114 /* flags */ 0, 14115 }, 14116 #endif /* chips */ 14117 14118 #if defined(BCM_56670_B0) 14119 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_7_BCM56670_B0fmt */ 14120 /* format IFP_SINGLE_WIDE_F2_7fmt */ 14121 /* nFields */ 6, 14122 /* *fields */ soc_IFP_SINGLE_WIDE_F2_7_BCM56560_A0fmt_fields, 14123 /* bits */ 128, 14124 /* flags */ 0, 14125 }, 14126 #endif /* chips */ 14127 14128 #if defined(BCM_56680_B0) 14129 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_7_BCM56680_B0fmt */ 14130 /* format IFP_SINGLE_WIDE_F2_7fmt */ 14131 /* nFields */ 5, 14132 /* *fields */ soc_IFP_SINGLE_WIDE_F2_7fmt_fields, 14133 /* bits */ 128, 14134 /* flags */ 0, 14135 }, 14136 #endif /* chips */ 14137 14138 #if defined(BCM_56685_A0) 14139 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_7_BCM56685_A0fmt */ 14140 /* format IFP_SINGLE_WIDE_F2_7fmt */ 14141 /* nFields */ 6, 14142 /* *fields */ soc_IFP_SINGLE_WIDE_F2_7_BCM56634_A0fmt_fields, 14143 /* bits */ 128, 14144 /* flags */ 0, 14145 }, 14146 #endif /* chips */ 14147 14148 #if defined(BCM_56685_B0) 14149 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_7_BCM56685_B0fmt */ 14150 /* format IFP_SINGLE_WIDE_F2_7fmt */ 14151 /* nFields */ 6, 14152 /* *fields */ soc_IFP_SINGLE_WIDE_F2_7_BCM56634_A0fmt_fields, 14153 /* bits */ 128, 14154 /* flags */ 0, 14155 }, 14156 #endif /* chips */ 14157 14158 #if defined(BCM_56840_A0) 14159 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_7_BCM56840_A0fmt */ 14160 /* format IFP_SINGLE_WIDE_F2_7fmt */ 14161 /* nFields */ 6, 14162 /* *fields */ soc_IFP_SINGLE_WIDE_F2_7_BCM56840_A0fmt_fields, 14163 /* bits */ 128, 14164 /* flags */ 0, 14165 }, 14166 #endif /* chips */ 14167 14168 #if defined(BCM_56840_B0) 14169 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_7_BCM56840_B0fmt */ 14170 /* format IFP_SINGLE_WIDE_F2_7fmt */ 14171 /* nFields */ 6, 14172 /* *fields */ soc_IFP_SINGLE_WIDE_F2_7_BCM56840_A0fmt_fields, 14173 /* bits */ 128, 14174 /* flags */ 0, 14175 }, 14176 #endif /* chips */ 14177 14178 #if defined(BCM_56850_A0) 14179 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_7_BCM56850_A0fmt */ 14180 /* format IFP_SINGLE_WIDE_F2_7fmt */ 14181 /* nFields */ 6, 14182 /* *fields */ soc_IFP_SINGLE_WIDE_F2_7_BCM56640_A0fmt_fields, 14183 /* bits */ 128, 14184 /* flags */ 0, 14185 }, 14186 #endif /* chips */ 14187 14188 #if defined(BCM_56860_A0) 14189 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_7_BCM56860_A0fmt */ 14190 /* format IFP_SINGLE_WIDE_F2_7fmt */ 14191 /* nFields */ 6, 14192 /* *fields */ soc_IFP_SINGLE_WIDE_F2_7_BCM56640_A0fmt_fields, 14193 /* bits */ 128, 14194 /* flags */ 0, 14195 }, 14196 #endif /* chips */ 14197 14198 #if defined(BCM_88732_A0) 14199 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_7_BCM88732_A0fmt */ 14200 /* format IFP_SINGLE_WIDE_F2_7fmt */ 14201 /* nFields */ 5, 14202 /* *fields */ soc_IFP_SINGLE_WIDE_F2_7_BCM88732_A0fmt_fields, 14203 /* bits */ 128, 14204 /* flags */ 0, 14205 }, 14206 #endif /* chips */ 14207 14208 #if defined(BCM_53400_A0) 14209 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_8_BCM53400_A0fmt */ 14210 /* format IFP_SINGLE_WIDE_F2_8fmt */ 14211 /* nFields */ 1, 14212 /* *fields */ soc_IFP_SINGLE_WIDE_F2_8_BCM53400_A0fmt_fields, 14213 /* bits */ 128, 14214 /* flags */ 0, 14215 }, 14216 #endif /* chips */ 14217 14218 #if defined(BCM_53540_A0) 14219 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_8_BCM53540_A0fmt */ 14220 /* format IFP_SINGLE_WIDE_F2_8fmt */ 14221 /* nFields */ 1, 14222 /* *fields */ soc_IFP_SINGLE_WIDE_F2_8_BCM53400_A0fmt_fields, 14223 /* bits */ 128, 14224 /* flags */ 0, 14225 }, 14226 #endif /* chips */ 14227 14228 #if defined(BCM_53570_A0) 14229 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_8_BCM53570_A0fmt */ 14230 /* format IFP_SINGLE_WIDE_F2_8fmt */ 14231 /* nFields */ 1, 14232 /* *fields */ soc_IFP_SINGLE_WIDE_F2_8_BCM53400_A0fmt_fields, 14233 /* bits */ 128, 14234 /* flags */ 0, 14235 }, 14236 #endif /* chips */ 14237 14238 #if defined(BCM_53570_B0) 14239 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_8_BCM53570_B0fmt */ 14240 /* format IFP_SINGLE_WIDE_F2_8fmt */ 14241 /* nFields */ 1, 14242 /* *fields */ soc_IFP_SINGLE_WIDE_F2_8_BCM53400_A0fmt_fields, 14243 /* bits */ 128, 14244 /* flags */ 0, 14245 }, 14246 #endif /* chips */ 14247 14248 #if defined(BCM_56150_A0) 14249 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_8_BCM56150_A0fmt */ 14250 /* format IFP_SINGLE_WIDE_F2_8fmt */ 14251 /* nFields */ 1, 14252 /* *fields */ soc_IFP_SINGLE_WIDE_F2_8_BCM56640_A0fmt_fields, 14253 /* bits */ 128, 14254 /* flags */ 0, 14255 }, 14256 #endif /* chips */ 14257 14258 #if defined(BCM_56160_A0) 14259 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_8_BCM56160_A0fmt */ 14260 /* format IFP_SINGLE_WIDE_F2_8fmt */ 14261 /* nFields */ 1, 14262 /* *fields */ soc_IFP_SINGLE_WIDE_F2_8_BCM53400_A0fmt_fields, 14263 /* bits */ 128, 14264 /* flags */ 0, 14265 }, 14266 #endif /* chips */ 14267 14268 #if defined(BCM_56260_A0) 14269 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_8_BCM56260_A0fmt */ 14270 /* format IFP_SINGLE_WIDE_F2_8fmt */ 14271 /* nFields */ 1, 14272 /* *fields */ soc_IFP_SINGLE_WIDE_F2_8_BCM53400_A0fmt_fields, 14273 /* bits */ 128, 14274 /* flags */ 0, 14275 }, 14276 #endif /* chips */ 14277 14278 #if defined(BCM_56260_B0) 14279 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_8_BCM56260_B0fmt */ 14280 /* format IFP_SINGLE_WIDE_F2_8fmt */ 14281 /* nFields */ 1, 14282 /* *fields */ soc_IFP_SINGLE_WIDE_F2_8_BCM53400_A0fmt_fields, 14283 /* bits */ 128, 14284 /* flags */ 0, 14285 }, 14286 #endif /* chips */ 14287 14288 #if defined(BCM_56270_A0) 14289 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_8_BCM56270_A0fmt */ 14290 /* format IFP_SINGLE_WIDE_F2_8fmt */ 14291 /* nFields */ 1, 14292 /* *fields */ soc_IFP_SINGLE_WIDE_F2_8_BCM53400_A0fmt_fields, 14293 /* bits */ 128, 14294 /* flags */ 0, 14295 }, 14296 #endif /* chips */ 14297 14298 #if defined(BCM_56340_A0) 14299 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_8_BCM56340_A0fmt */ 14300 /* format IFP_SINGLE_WIDE_F2_8fmt */ 14301 /* nFields */ 1, 14302 /* *fields */ soc_IFP_SINGLE_WIDE_F2_8_BCM56640_A0fmt_fields, 14303 /* bits */ 128, 14304 /* flags */ 0, 14305 }, 14306 #endif /* chips */ 14307 14308 #if defined(BCM_56450_A0) 14309 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_8_BCM56450_A0fmt */ 14310 /* format IFP_SINGLE_WIDE_F2_8fmt */ 14311 /* nFields */ 1, 14312 /* *fields */ soc_IFP_SINGLE_WIDE_F2_8_BCM56640_A0fmt_fields, 14313 /* bits */ 128, 14314 /* flags */ 0, 14315 }, 14316 #endif /* chips */ 14317 14318 #if defined(BCM_56450_B0) 14319 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_8_BCM56450_B0fmt */ 14320 /* format IFP_SINGLE_WIDE_F2_8fmt */ 14321 /* nFields */ 1, 14322 /* *fields */ soc_IFP_SINGLE_WIDE_F2_8_BCM56640_A0fmt_fields, 14323 /* bits */ 128, 14324 /* flags */ 0, 14325 }, 14326 #endif /* chips */ 14327 14328 #if defined(BCM_56450_B1) 14329 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_8_BCM56450_B1fmt */ 14330 /* format IFP_SINGLE_WIDE_F2_8fmt */ 14331 /* nFields */ 1, 14332 /* *fields */ soc_IFP_SINGLE_WIDE_F2_8_BCM56640_A0fmt_fields, 14333 /* bits */ 128, 14334 /* flags */ 0, 14335 }, 14336 #endif /* chips */ 14337 14338 #if defined(BCM_56560_A0) 14339 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_8_BCM56560_A0fmt */ 14340 /* format IFP_SINGLE_WIDE_F2_8fmt */ 14341 /* nFields */ 1, 14342 /* *fields */ soc_IFP_SINGLE_WIDE_F2_8_BCM53400_A0fmt_fields, 14343 /* bits */ 128, 14344 /* flags */ 0, 14345 }, 14346 #endif /* chips */ 14347 14348 #if defined(BCM_56560_B0) 14349 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_8_BCM56560_B0fmt */ 14350 /* format IFP_SINGLE_WIDE_F2_8fmt */ 14351 /* nFields */ 1, 14352 /* *fields */ soc_IFP_SINGLE_WIDE_F2_8_BCM53400_A0fmt_fields, 14353 /* bits */ 128, 14354 /* flags */ 0, 14355 }, 14356 #endif /* chips */ 14357 14358 #if defined(BCM_56634_A0) 14359 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_8_BCM56634_A0fmt */ 14360 /* format IFP_SINGLE_WIDE_F2_8fmt */ 14361 /* nFields */ 1, 14362 /* *fields */ soc_IFP_SINGLE_WIDE_F2_8fmt_fields, 14363 /* bits */ 128, 14364 /* flags */ 0, 14365 }, 14366 #endif /* chips */ 14367 14368 #if defined(BCM_56640_A0) 14369 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_8_BCM56640_A0fmt */ 14370 /* format IFP_SINGLE_WIDE_F2_8fmt */ 14371 /* nFields */ 1, 14372 /* *fields */ soc_IFP_SINGLE_WIDE_F2_8_BCM56640_A0fmt_fields, 14373 /* bits */ 128, 14374 /* flags */ 0, 14375 }, 14376 #endif /* chips */ 14377 14378 #if defined(BCM_56670_A0) 14379 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_8_BCM56670_A0fmt */ 14380 /* format IFP_SINGLE_WIDE_F2_8fmt */ 14381 /* nFields */ 1, 14382 /* *fields */ soc_IFP_SINGLE_WIDE_F2_8_BCM53400_A0fmt_fields, 14383 /* bits */ 128, 14384 /* flags */ 0, 14385 }, 14386 #endif /* chips */ 14387 14388 #if defined(BCM_56670_B0) 14389 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_8_BCM56670_B0fmt */ 14390 /* format IFP_SINGLE_WIDE_F2_8fmt */ 14391 /* nFields */ 1, 14392 /* *fields */ soc_IFP_SINGLE_WIDE_F2_8_BCM53400_A0fmt_fields, 14393 /* bits */ 128, 14394 /* flags */ 0, 14395 }, 14396 #endif /* chips */ 14397 14398 #if defined(BCM_56850_A0) 14399 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_8_BCM56850_A0fmt */ 14400 /* format IFP_SINGLE_WIDE_F2_8fmt */ 14401 /* nFields */ 1, 14402 /* *fields */ soc_IFP_SINGLE_WIDE_F2_8_BCM56640_A0fmt_fields, 14403 /* bits */ 128, 14404 /* flags */ 0, 14405 }, 14406 #endif /* chips */ 14407 14408 #if defined(BCM_56860_A0) 14409 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_8_BCM56860_A0fmt */ 14410 /* format IFP_SINGLE_WIDE_F2_8fmt */ 14411 /* nFields */ 1, 14412 /* *fields */ soc_IFP_SINGLE_WIDE_F2_8_BCM56640_A0fmt_fields, 14413 /* bits */ 128, 14414 /* flags */ 0, 14415 }, 14416 #endif /* chips */ 14417 14418 #if defined(BCM_53400_A0) 14419 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_9_BCM53400_A0fmt */ 14420 /* format IFP_SINGLE_WIDE_F2_9fmt */ 14421 /* nFields */ 1, 14422 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_3_BCM53400_A0fmt_fields, 14423 /* bits */ 128, 14424 /* flags */ 0, 14425 }, 14426 #endif /* chips */ 14427 14428 #if defined(BCM_53540_A0) 14429 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_9_BCM53540_A0fmt */ 14430 /* format IFP_SINGLE_WIDE_F2_9fmt */ 14431 /* nFields */ 1, 14432 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_3_BCM53400_A0fmt_fields, 14433 /* bits */ 128, 14434 /* flags */ 0, 14435 }, 14436 #endif /* chips */ 14437 14438 #if defined(BCM_53570_A0) 14439 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_9_BCM53570_A0fmt */ 14440 /* format IFP_SINGLE_WIDE_F2_9fmt */ 14441 /* nFields */ 1, 14442 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_3_BCM53400_A0fmt_fields, 14443 /* bits */ 128, 14444 /* flags */ 0, 14445 }, 14446 #endif /* chips */ 14447 14448 #if defined(BCM_53570_B0) 14449 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_9_BCM53570_B0fmt */ 14450 /* format IFP_SINGLE_WIDE_F2_9fmt */ 14451 /* nFields */ 1, 14452 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_3_BCM53400_A0fmt_fields, 14453 /* bits */ 128, 14454 /* flags */ 0, 14455 }, 14456 #endif /* chips */ 14457 14458 #if defined(BCM_56142_A0) 14459 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_9_BCM56142_A0fmt */ 14460 /* format IFP_SINGLE_WIDE_F2_9fmt */ 14461 /* nFields */ 1, 14462 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_2fmt_fields, 14463 /* bits */ 128, 14464 /* flags */ 0, 14465 }, 14466 #endif /* chips */ 14467 14468 #if defined(BCM_56150_A0) 14469 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_9_BCM56150_A0fmt */ 14470 /* format IFP_SINGLE_WIDE_F2_9fmt */ 14471 /* nFields */ 1, 14472 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_3fmt_fields, 14473 /* bits */ 128, 14474 /* flags */ 0, 14475 }, 14476 #endif /* chips */ 14477 14478 #if defined(BCM_56160_A0) 14479 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_9_BCM56160_A0fmt */ 14480 /* format IFP_SINGLE_WIDE_F2_9fmt */ 14481 /* nFields */ 1, 14482 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_3_BCM53400_A0fmt_fields, 14483 /* bits */ 128, 14484 /* flags */ 0, 14485 }, 14486 #endif /* chips */ 14487 14488 #if defined(BCM_56260_A0) 14489 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_9_BCM56260_A0fmt */ 14490 /* format IFP_SINGLE_WIDE_F2_9fmt */ 14491 /* nFields */ 1, 14492 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_3_BCM53400_A0fmt_fields, 14493 /* bits */ 128, 14494 /* flags */ 0, 14495 }, 14496 #endif /* chips */ 14497 14498 #if defined(BCM_56260_B0) 14499 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_9_BCM56260_B0fmt */ 14500 /* format IFP_SINGLE_WIDE_F2_9fmt */ 14501 /* nFields */ 1, 14502 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_3_BCM53400_A0fmt_fields, 14503 /* bits */ 128, 14504 /* flags */ 0, 14505 }, 14506 #endif /* chips */ 14507 14508 #if defined(BCM_56270_A0) 14509 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_9_BCM56270_A0fmt */ 14510 /* format IFP_SINGLE_WIDE_F2_9fmt */ 14511 /* nFields */ 1, 14512 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_3_BCM53400_A0fmt_fields, 14513 /* bits */ 128, 14514 /* flags */ 0, 14515 }, 14516 #endif /* chips */ 14517 14518 #if defined(BCM_56334_A0) 14519 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_9_BCM56334_A0fmt */ 14520 /* format IFP_SINGLE_WIDE_F2_9fmt */ 14521 /* nFields */ 1, 14522 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_2fmt_fields, 14523 /* bits */ 128, 14524 /* flags */ 0, 14525 }, 14526 #endif /* chips */ 14527 14528 #if defined(BCM_56334_B0) 14529 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_9_BCM56334_B0fmt */ 14530 /* format IFP_SINGLE_WIDE_F2_9fmt */ 14531 /* nFields */ 1, 14532 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_2fmt_fields, 14533 /* bits */ 128, 14534 /* flags */ 0, 14535 }, 14536 #endif /* chips */ 14537 14538 #if defined(BCM_56340_A0) 14539 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_9_BCM56340_A0fmt */ 14540 /* format IFP_SINGLE_WIDE_F2_9fmt */ 14541 /* nFields */ 1, 14542 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_3fmt_fields, 14543 /* bits */ 128, 14544 /* flags */ 0, 14545 }, 14546 #endif /* chips */ 14547 14548 #if defined(BCM_56440_A0) 14549 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_9_BCM56440_A0fmt */ 14550 /* format IFP_SINGLE_WIDE_F2_9fmt */ 14551 /* nFields */ 1, 14552 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_2fmt_fields, 14553 /* bits */ 128, 14554 /* flags */ 0, 14555 }, 14556 #endif /* chips */ 14557 14558 #if defined(BCM_56440_B0) 14559 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_9_BCM56440_B0fmt */ 14560 /* format IFP_SINGLE_WIDE_F2_9fmt */ 14561 /* nFields */ 1, 14562 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_2fmt_fields, 14563 /* bits */ 128, 14564 /* flags */ 0, 14565 }, 14566 #endif /* chips */ 14567 14568 #if defined(BCM_56450_A0) 14569 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_9_BCM56450_A0fmt */ 14570 /* format IFP_SINGLE_WIDE_F2_9fmt */ 14571 /* nFields */ 1, 14572 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_3fmt_fields, 14573 /* bits */ 128, 14574 /* flags */ 0, 14575 }, 14576 #endif /* chips */ 14577 14578 #if defined(BCM_56450_B0) 14579 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_9_BCM56450_B0fmt */ 14580 /* format IFP_SINGLE_WIDE_F2_9fmt */ 14581 /* nFields */ 1, 14582 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_3fmt_fields, 14583 /* bits */ 128, 14584 /* flags */ 0, 14585 }, 14586 #endif /* chips */ 14587 14588 #if defined(BCM_56450_B1) 14589 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_9_BCM56450_B1fmt */ 14590 /* format IFP_SINGLE_WIDE_F2_9fmt */ 14591 /* nFields */ 1, 14592 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_3fmt_fields, 14593 /* bits */ 128, 14594 /* flags */ 0, 14595 }, 14596 #endif /* chips */ 14597 14598 #if defined(BCM_56524_A0) 14599 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_9_BCM56524_A0fmt */ 14600 /* format IFP_SINGLE_WIDE_F2_9fmt */ 14601 /* nFields */ 1, 14602 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_2fmt_fields, 14603 /* bits */ 128, 14604 /* flags */ 0, 14605 }, 14606 #endif /* chips */ 14607 14608 #if defined(BCM_56524_B0) 14609 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_9_BCM56524_B0fmt */ 14610 /* format IFP_SINGLE_WIDE_F2_9fmt */ 14611 /* nFields */ 1, 14612 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_2fmt_fields, 14613 /* bits */ 128, 14614 /* flags */ 0, 14615 }, 14616 #endif /* chips */ 14617 14618 #if defined(BCM_56560_A0) 14619 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_9_BCM56560_A0fmt */ 14620 /* format IFP_SINGLE_WIDE_F2_9fmt */ 14621 /* nFields */ 1, 14622 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_3_BCM53400_A0fmt_fields, 14623 /* bits */ 128, 14624 /* flags */ 0, 14625 }, 14626 #endif /* chips */ 14627 14628 #if defined(BCM_56560_B0) 14629 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_9_BCM56560_B0fmt */ 14630 /* format IFP_SINGLE_WIDE_F2_9fmt */ 14631 /* nFields */ 1, 14632 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_3_BCM53400_A0fmt_fields, 14633 /* bits */ 128, 14634 /* flags */ 0, 14635 }, 14636 #endif /* chips */ 14637 14638 #if defined(BCM_56624_B0) 14639 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_9_BCM56624_B0fmt */ 14640 /* format IFP_SINGLE_WIDE_F2_9fmt */ 14641 /* nFields */ 1, 14642 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_2fmt_fields, 14643 /* bits */ 128, 14644 /* flags */ 0, 14645 }, 14646 #endif /* chips */ 14647 14648 #if defined(BCM_56634_A0) 14649 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_9_BCM56634_A0fmt */ 14650 /* format IFP_SINGLE_WIDE_F2_9fmt */ 14651 /* nFields */ 1, 14652 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_2fmt_fields, 14653 /* bits */ 128, 14654 /* flags */ 0, 14655 }, 14656 #endif /* chips */ 14657 14658 #if defined(BCM_56634_B0) 14659 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_9_BCM56634_B0fmt */ 14660 /* format IFP_SINGLE_WIDE_F2_9fmt */ 14661 /* nFields */ 1, 14662 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_2fmt_fields, 14663 /* bits */ 128, 14664 /* flags */ 0, 14665 }, 14666 #endif /* chips */ 14667 14668 #if defined(BCM_56640_A0) 14669 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_9_BCM56640_A0fmt */ 14670 /* format IFP_SINGLE_WIDE_F2_9fmt */ 14671 /* nFields */ 1, 14672 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_3fmt_fields, 14673 /* bits */ 128, 14674 /* flags */ 0, 14675 }, 14676 #endif /* chips */ 14677 14678 #if defined(BCM_56670_A0) 14679 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_9_BCM56670_A0fmt */ 14680 /* format IFP_SINGLE_WIDE_F2_9fmt */ 14681 /* nFields */ 1, 14682 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_3_BCM53400_A0fmt_fields, 14683 /* bits */ 128, 14684 /* flags */ 0, 14685 }, 14686 #endif /* chips */ 14687 14688 #if defined(BCM_56670_B0) 14689 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_9_BCM56670_B0fmt */ 14690 /* format IFP_SINGLE_WIDE_F2_9fmt */ 14691 /* nFields */ 1, 14692 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_3_BCM53400_A0fmt_fields, 14693 /* bits */ 128, 14694 /* flags */ 0, 14695 }, 14696 #endif /* chips */ 14697 14698 #if defined(BCM_56680_A0) 14699 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_9_BCM56680_A0fmt */ 14700 /* format IFP_SINGLE_WIDE_F2_9fmt */ 14701 /* nFields */ 1, 14702 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_2fmt_fields, 14703 /* bits */ 128, 14704 /* flags */ 0, 14705 }, 14706 #endif /* chips */ 14707 14708 #if defined(BCM_56680_B0) 14709 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_9_BCM56680_B0fmt */ 14710 /* format IFP_SINGLE_WIDE_F2_9fmt */ 14711 /* nFields */ 1, 14712 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_2fmt_fields, 14713 /* bits */ 128, 14714 /* flags */ 0, 14715 }, 14716 #endif /* chips */ 14717 14718 #if defined(BCM_56685_A0) 14719 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_9_BCM56685_A0fmt */ 14720 /* format IFP_SINGLE_WIDE_F2_9fmt */ 14721 /* nFields */ 1, 14722 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_2fmt_fields, 14723 /* bits */ 128, 14724 /* flags */ 0, 14725 }, 14726 #endif /* chips */ 14727 14728 #if defined(BCM_56685_B0) 14729 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_9_BCM56685_B0fmt */ 14730 /* format IFP_SINGLE_WIDE_F2_9fmt */ 14731 /* nFields */ 1, 14732 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_2fmt_fields, 14733 /* bits */ 128, 14734 /* flags */ 0, 14735 }, 14736 #endif /* chips */ 14737 14738 #if defined(BCM_56725_A0) 14739 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_9_BCM56725_A0fmt */ 14740 /* format IFP_SINGLE_WIDE_F2_9fmt */ 14741 /* nFields */ 1, 14742 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_2fmt_fields, 14743 /* bits */ 128, 14744 /* flags */ 0, 14745 }, 14746 #endif /* chips */ 14747 14748 #if defined(BCM_56820_A0) 14749 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_9_BCM56820_A0fmt */ 14750 /* format IFP_SINGLE_WIDE_F2_9fmt */ 14751 /* nFields */ 1, 14752 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_2fmt_fields, 14753 /* bits */ 128, 14754 /* flags */ 0, 14755 }, 14756 #endif /* chips */ 14757 14758 #if defined(BCM_56840_A0) 14759 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_9_BCM56840_A0fmt */ 14760 /* format IFP_SINGLE_WIDE_F2_9fmt */ 14761 /* nFields */ 1, 14762 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_2fmt_fields, 14763 /* bits */ 128, 14764 /* flags */ 0, 14765 }, 14766 #endif /* chips */ 14767 14768 #if defined(BCM_56840_B0) 14769 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_9_BCM56840_B0fmt */ 14770 /* format IFP_SINGLE_WIDE_F2_9fmt */ 14771 /* nFields */ 1, 14772 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_2fmt_fields, 14773 /* bits */ 128, 14774 /* flags */ 0, 14775 }, 14776 #endif /* chips */ 14777 14778 #if defined(BCM_56850_A0) 14779 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_9_BCM56850_A0fmt */ 14780 /* format IFP_SINGLE_WIDE_F2_9fmt */ 14781 /* nFields */ 1, 14782 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_3fmt_fields, 14783 /* bits */ 128, 14784 /* flags */ 0, 14785 }, 14786 #endif /* chips */ 14787 14788 #if defined(BCM_56860_A0) 14789 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_9_BCM56860_A0fmt */ 14790 /* format IFP_SINGLE_WIDE_F2_9fmt */ 14791 /* nFields */ 1, 14792 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_3fmt_fields, 14793 /* bits */ 128, 14794 /* flags */ 0, 14795 }, 14796 #endif /* chips */ 14797 14798 #if defined(BCM_88732_A0) 14799 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F2_9_BCM88732_A0fmt */ 14800 /* format IFP_SINGLE_WIDE_F2_9fmt */ 14801 /* nFields */ 1, 14802 /* *fields */ soc_IFP_DOUBLE_WIDE_F2_2fmt_fields, 14803 /* bits */ 128, 14804 /* flags */ 0, 14805 }, 14806 #endif /* chips */ 14807 14808 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \ 14809 defined(BCM_56680_A0) 14810 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_0fmt */ 14811 /* format IFP_SINGLE_WIDE_F3_0fmt */ 14812 /* nFields */ 3, 14813 /* *fields */ soc_IFP_SINGLE_WIDE_F3_0fmt_fields, 14814 /* bits */ 32, 14815 /* flags */ 0, 14816 }, 14817 #endif /* chips */ 14818 14819 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \ 14820 defined(BCM_56680_A0) 14821 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_1fmt */ 14822 /* format IFP_SINGLE_WIDE_F3_1fmt */ 14823 /* nFields */ 3, 14824 /* *fields */ soc_IFP_SINGLE_WIDE_F3_1fmt_fields, 14825 /* bits */ 32, 14826 /* flags */ 0, 14827 }, 14828 #endif /* chips */ 14829 14830 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \ 14831 defined(BCM_56680_A0) || defined(BCM_56680_B0) 14832 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_2fmt */ 14833 /* format IFP_SINGLE_WIDE_F3_2fmt */ 14834 /* nFields */ 8, 14835 /* *fields */ soc_IFP_SINGLE_WIDE_F3_2fmt_fields, 14836 /* bits */ 32, 14837 /* flags */ 0, 14838 }, 14839 #endif /* chips */ 14840 14841 #if defined(BCM_56624_A0) 14842 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_3fmt */ 14843 /* format IFP_SINGLE_WIDE_F3_3fmt */ 14844 /* nFields */ 6, 14845 /* *fields */ soc_IFP_SINGLE_WIDE_F3_3fmt_fields, 14846 /* bits */ 32, 14847 /* flags */ 0, 14848 }, 14849 #endif /* chips */ 14850 14851 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \ 14852 defined(BCM_56680_A0) 14853 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_4fmt */ 14854 /* format IFP_SINGLE_WIDE_F3_4fmt */ 14855 /* nFields */ 2, 14856 /* *fields */ soc_IFP_SINGLE_WIDE_F3_4fmt_fields, 14857 /* bits */ 32, 14858 /* flags */ 0, 14859 }, 14860 #endif /* chips */ 14861 14862 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \ 14863 defined(BCM_56680_A0) || defined(BCM_56680_B0) 14864 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_5fmt */ 14865 /* format IFP_SINGLE_WIDE_F3_5fmt */ 14866 /* nFields */ 2, 14867 /* *fields */ soc_IFP_SINGLE_WIDE_F3_5fmt_fields, 14868 /* bits */ 32, 14869 /* flags */ 0, 14870 }, 14871 #endif /* chips */ 14872 14873 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \ 14874 defined(BCM_56680_A0) 14875 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_6fmt */ 14876 /* format IFP_SINGLE_WIDE_F3_6fmt */ 14877 /* nFields */ 2, 14878 /* *fields */ soc_IFP_SINGLE_WIDE_F3_6fmt_fields, 14879 /* bits */ 32, 14880 /* flags */ 0, 14881 }, 14882 #endif /* chips */ 14883 14884 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \ 14885 defined(BCM_56680_A0) 14886 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_7fmt */ 14887 /* format IFP_SINGLE_WIDE_F3_7fmt */ 14888 /* nFields */ 2, 14889 /* *fields */ soc_IFP_SINGLE_WIDE_F3_7fmt_fields, 14890 /* bits */ 32, 14891 /* flags */ 0, 14892 }, 14893 #endif /* chips */ 14894 14895 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \ 14896 defined(BCM_56680_A0) 14897 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_8fmt */ 14898 /* format IFP_SINGLE_WIDE_F3_8fmt */ 14899 /* nFields */ 5, 14900 /* *fields */ soc_IFP_SINGLE_WIDE_F3_8fmt_fields, 14901 /* bits */ 32, 14902 /* flags */ 0, 14903 }, 14904 #endif /* chips */ 14905 14906 #if defined(BCM_56634_A0) || defined(BCM_56634_B0) 14907 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_9fmt */ 14908 /* format IFP_SINGLE_WIDE_F3_9fmt */ 14909 /* nFields */ 4, 14910 /* *fields */ soc_IFP_SINGLE_WIDE_F3_9fmt_fields, 14911 /* bits */ 37, 14912 /* flags */ 0, 14913 }, 14914 #endif /* chips */ 14915 14916 #if defined(BCM_56634_A0) 14917 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_10fmt */ 14918 /* format IFP_SINGLE_WIDE_F3_10fmt */ 14919 /* nFields */ 4, 14920 /* *fields */ soc_IFP_SINGLE_WIDE_F1_10fmt_fields, 14921 /* bits */ 37, 14922 /* flags */ 0, 14923 }, 14924 #endif /* chips */ 14925 14926 #if defined(BCM_56634_A0) 14927 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_11fmt */ 14928 /* format IFP_SINGLE_WIDE_F3_11fmt */ 14929 /* nFields */ 4, 14930 /* *fields */ soc_IFP_SINGLE_WIDE_F1_11fmt_fields, 14931 /* bits */ 37, 14932 /* flags */ 0, 14933 }, 14934 #endif /* chips */ 14935 14936 #if defined(BCM_56840_A0) 14937 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_12fmt */ 14938 /* format IFP_SINGLE_WIDE_F3_12fmt */ 14939 /* nFields */ 3, 14940 /* *fields */ soc_IFP_SINGLE_WIDE_F3_12fmt_fields, 14941 /* bits */ 39, 14942 /* flags */ 0, 14943 }, 14944 #endif /* chips */ 14945 14946 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \ 14947 defined(BCM_56840_A0) || defined(BCM_56840_B0) 14948 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_13fmt */ 14949 /* format IFP_SINGLE_WIDE_F3_13fmt */ 14950 /* nFields */ 5, 14951 /* *fields */ soc_IFP_SINGLE_WIDE_F3_13fmt_fields, 14952 /* bits */ 39, 14953 /* flags */ 0, 14954 }, 14955 #endif /* chips */ 14956 14957 #if defined(BCM_56850_A0) || defined(BCM_56860_A0) 14958 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_14fmt */ 14959 /* format IFP_SINGLE_WIDE_F3_14fmt */ 14960 /* nFields */ 2, 14961 /* *fields */ soc_IFP_SINGLE_WIDE_F3_14fmt_fields, 14962 /* bits */ 49, 14963 /* flags */ 0, 14964 }, 14965 #endif /* chips */ 14966 14967 #if defined(BCM_56850_A0) || defined(BCM_56860_A0) 14968 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_15fmt */ 14969 /* format IFP_SINGLE_WIDE_F3_15fmt */ 14970 /* nFields */ 4, 14971 /* *fields */ soc_IFP_SINGLE_WIDE_F3_15fmt_fields, 14972 /* bits */ 49, 14973 /* flags */ 0, 14974 }, 14975 #endif /* chips */ 14976 14977 #if defined(BCM_56850_A0) 14978 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_16fmt */ 14979 /* format IFP_SINGLE_WIDE_F3_16fmt */ 14980 /* nFields */ 12, 14981 /* *fields */ soc_IFP_SINGLE_WIDE_F1_16fmt_fields, 14982 /* bits */ 49, 14983 /* flags */ 0, 14984 }, 14985 #endif /* chips */ 14986 14987 #if defined(BCM_53400_A0) 14988 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_0_BCM53400_A0fmt */ 14989 /* format IFP_SINGLE_WIDE_F3_0fmt */ 14990 /* nFields */ 3, 14991 /* *fields */ soc_IFP_SINGLE_WIDE_F3_0_BCM53400_A0fmt_fields, 14992 /* bits */ 37, 14993 /* flags */ 0, 14994 }, 14995 #endif /* chips */ 14996 14997 #if defined(BCM_53540_A0) 14998 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_0_BCM53540_A0fmt */ 14999 /* format IFP_SINGLE_WIDE_F3_0fmt */ 15000 /* nFields */ 3, 15001 /* *fields */ soc_IFP_SINGLE_WIDE_F3_0_BCM53400_A0fmt_fields, 15002 /* bits */ 37, 15003 /* flags */ 0, 15004 }, 15005 #endif /* chips */ 15006 15007 #if defined(BCM_53570_A0) 15008 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_0_BCM53570_A0fmt */ 15009 /* format IFP_SINGLE_WIDE_F3_0fmt */ 15010 /* nFields */ 4, 15011 /* *fields */ soc_IFP_SINGLE_WIDE_F3_0_BCM53570_A0fmt_fields, 15012 /* bits */ 39, 15013 /* flags */ 0, 15014 }, 15015 #endif /* chips */ 15016 15017 #if defined(BCM_53570_B0) 15018 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_0_BCM53570_B0fmt */ 15019 /* format IFP_SINGLE_WIDE_F3_0fmt */ 15020 /* nFields */ 4, 15021 /* *fields */ soc_IFP_SINGLE_WIDE_F3_0_BCM53570_A0fmt_fields, 15022 /* bits */ 39, 15023 /* flags */ 0, 15024 }, 15025 #endif /* chips */ 15026 15027 #if defined(BCM_56142_A0) 15028 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_0_BCM56142_A0fmt */ 15029 /* format IFP_SINGLE_WIDE_F3_0fmt */ 15030 /* nFields */ 3, 15031 /* *fields */ soc_IFP_SINGLE_WIDE_F3_0_BCM56634_A0fmt_fields, 15032 /* bits */ 37, 15033 /* flags */ 0, 15034 }, 15035 #endif /* chips */ 15036 15037 #if defined(BCM_56150_A0) 15038 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_0_BCM56150_A0fmt */ 15039 /* format IFP_SINGLE_WIDE_F3_0fmt */ 15040 /* nFields */ 3, 15041 /* *fields */ soc_IFP_SINGLE_WIDE_F3_0_BCM56150_A0fmt_fields, 15042 /* bits */ 37, 15043 /* flags */ 0, 15044 }, 15045 #endif /* chips */ 15046 15047 #if defined(BCM_56160_A0) 15048 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_0_BCM56160_A0fmt */ 15049 /* format IFP_SINGLE_WIDE_F3_0fmt */ 15050 /* nFields */ 3, 15051 /* *fields */ soc_IFP_SINGLE_WIDE_F3_0_BCM53400_A0fmt_fields, 15052 /* bits */ 37, 15053 /* flags */ 0, 15054 }, 15055 #endif /* chips */ 15056 15057 #if defined(BCM_56260_A0) 15058 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_0_BCM56260_A0fmt */ 15059 /* format IFP_SINGLE_WIDE_F3_0fmt */ 15060 /* nFields */ 4, 15061 /* *fields */ soc_IFP_SINGLE_WIDE_F3_0_BCM56260_A0fmt_fields, 15062 /* bits */ 40, 15063 /* flags */ 0, 15064 }, 15065 #endif /* chips */ 15066 15067 #if defined(BCM_56260_B0) 15068 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_0_BCM56260_B0fmt */ 15069 /* format IFP_SINGLE_WIDE_F3_0fmt */ 15070 /* nFields */ 4, 15071 /* *fields */ soc_IFP_SINGLE_WIDE_F3_0_BCM56260_A0fmt_fields, 15072 /* bits */ 40, 15073 /* flags */ 0, 15074 }, 15075 #endif /* chips */ 15076 15077 #if defined(BCM_56270_A0) 15078 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_0_BCM56270_A0fmt */ 15079 /* format IFP_SINGLE_WIDE_F3_0fmt */ 15080 /* nFields */ 4, 15081 /* *fields */ soc_IFP_SINGLE_WIDE_F3_0_BCM56260_A0fmt_fields, 15082 /* bits */ 40, 15083 /* flags */ 0, 15084 }, 15085 #endif /* chips */ 15086 15087 #if defined(BCM_56334_A0) 15088 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_0_BCM56334_A0fmt */ 15089 /* format IFP_SINGLE_WIDE_F3_0fmt */ 15090 /* nFields */ 3, 15091 /* *fields */ soc_IFP_SINGLE_WIDE_F3_0_BCM56634_A0fmt_fields, 15092 /* bits */ 37, 15093 /* flags */ 0, 15094 }, 15095 #endif /* chips */ 15096 15097 #if defined(BCM_56334_B0) 15098 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_0_BCM56334_B0fmt */ 15099 /* format IFP_SINGLE_WIDE_F3_0fmt */ 15100 /* nFields */ 3, 15101 /* *fields */ soc_IFP_SINGLE_WIDE_F3_0_BCM56634_A0fmt_fields, 15102 /* bits */ 37, 15103 /* flags */ 0, 15104 }, 15105 #endif /* chips */ 15106 15107 #if defined(BCM_56340_A0) 15108 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_0_BCM56340_A0fmt */ 15109 /* format IFP_SINGLE_WIDE_F3_0fmt */ 15110 /* nFields */ 4, 15111 /* *fields */ soc_IFP_SINGLE_WIDE_F1_0_BCM56340_A0fmt_fields, 15112 /* bits */ 49, 15113 /* flags */ 0, 15114 }, 15115 #endif /* chips */ 15116 15117 #if defined(BCM_56440_A0) 15118 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_0_BCM56440_A0fmt */ 15119 /* format IFP_SINGLE_WIDE_F3_0fmt */ 15120 /* nFields */ 4, 15121 /* *fields */ soc_IFP_SINGLE_WIDE_F3_0_BCM56840_A0fmt_fields, 15122 /* bits */ 39, 15123 /* flags */ 0, 15124 }, 15125 #endif /* chips */ 15126 15127 #if defined(BCM_56440_B0) 15128 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_0_BCM56440_B0fmt */ 15129 /* format IFP_SINGLE_WIDE_F3_0fmt */ 15130 /* nFields */ 4, 15131 /* *fields */ soc_IFP_SINGLE_WIDE_F3_0_BCM56840_A0fmt_fields, 15132 /* bits */ 39, 15133 /* flags */ 0, 15134 }, 15135 #endif /* chips */ 15136 15137 #if defined(BCM_56450_A0) 15138 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_0_BCM56450_A0fmt */ 15139 /* format IFP_SINGLE_WIDE_F3_0fmt */ 15140 /* nFields */ 4, 15141 /* *fields */ soc_IFP_SINGLE_WIDE_F3_0_BCM56450_A0fmt_fields, 15142 /* bits */ 40, 15143 /* flags */ 0, 15144 }, 15145 #endif /* chips */ 15146 15147 #if defined(BCM_56450_B0) 15148 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_0_BCM56450_B0fmt */ 15149 /* format IFP_SINGLE_WIDE_F3_0fmt */ 15150 /* nFields */ 4, 15151 /* *fields */ soc_IFP_SINGLE_WIDE_F3_0_BCM56450_A0fmt_fields, 15152 /* bits */ 40, 15153 /* flags */ 0, 15154 }, 15155 #endif /* chips */ 15156 15157 #if defined(BCM_56450_B1) 15158 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_0_BCM56450_B1fmt */ 15159 /* format IFP_SINGLE_WIDE_F3_0fmt */ 15160 /* nFields */ 4, 15161 /* *fields */ soc_IFP_SINGLE_WIDE_F3_0_BCM56450_A0fmt_fields, 15162 /* bits */ 40, 15163 /* flags */ 0, 15164 }, 15165 #endif /* chips */ 15166 15167 #if defined(BCM_56524_A0) 15168 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_0_BCM56524_A0fmt */ 15169 /* format IFP_SINGLE_WIDE_F3_0fmt */ 15170 /* nFields */ 3, 15171 /* *fields */ soc_IFP_SINGLE_WIDE_F3_0_BCM56634_A0fmt_fields, 15172 /* bits */ 37, 15173 /* flags */ 0, 15174 }, 15175 #endif /* chips */ 15176 15177 #if defined(BCM_56524_B0) 15178 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_0_BCM56524_B0fmt */ 15179 /* format IFP_SINGLE_WIDE_F3_0fmt */ 15180 /* nFields */ 3, 15181 /* *fields */ soc_IFP_SINGLE_WIDE_F3_0_BCM56634_A0fmt_fields, 15182 /* bits */ 37, 15183 /* flags */ 0, 15184 }, 15185 #endif /* chips */ 15186 15187 #if defined(BCM_56560_A0) 15188 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_0_BCM56560_A0fmt */ 15189 /* format IFP_SINGLE_WIDE_F3_0fmt */ 15190 /* nFields */ 4, 15191 /* *fields */ soc_IFP_SINGLE_WIDE_F3_0_BCM56560_A0fmt_fields, 15192 /* bits */ 49, 15193 /* flags */ 0, 15194 }, 15195 #endif /* chips */ 15196 15197 #if defined(BCM_56560_B0) 15198 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_0_BCM56560_B0fmt */ 15199 /* format IFP_SINGLE_WIDE_F3_0fmt */ 15200 /* nFields */ 4, 15201 /* *fields */ soc_IFP_SINGLE_WIDE_F3_0_BCM56560_A0fmt_fields, 15202 /* bits */ 49, 15203 /* flags */ 0, 15204 }, 15205 #endif /* chips */ 15206 15207 #if defined(BCM_56634_A0) 15208 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_0_BCM56634_A0fmt */ 15209 /* format IFP_SINGLE_WIDE_F3_0fmt */ 15210 /* nFields */ 3, 15211 /* *fields */ soc_IFP_SINGLE_WIDE_F3_0_BCM56634_A0fmt_fields, 15212 /* bits */ 37, 15213 /* flags */ 0, 15214 }, 15215 #endif /* chips */ 15216 15217 #if defined(BCM_56634_B0) 15218 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_0_BCM56634_B0fmt */ 15219 /* format IFP_SINGLE_WIDE_F3_0fmt */ 15220 /* nFields */ 3, 15221 /* *fields */ soc_IFP_SINGLE_WIDE_F3_0_BCM56634_A0fmt_fields, 15222 /* bits */ 37, 15223 /* flags */ 0, 15224 }, 15225 #endif /* chips */ 15226 15227 #if defined(BCM_56640_A0) 15228 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_0_BCM56640_A0fmt */ 15229 /* format IFP_SINGLE_WIDE_F3_0fmt */ 15230 /* nFields */ 4, 15231 /* *fields */ soc_IFP_SINGLE_WIDE_F1_0_BCM56640_A0fmt_fields, 15232 /* bits */ 49, 15233 /* flags */ 0, 15234 }, 15235 #endif /* chips */ 15236 15237 #if defined(BCM_56670_A0) 15238 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_0_BCM56670_A0fmt */ 15239 /* format IFP_SINGLE_WIDE_F3_0fmt */ 15240 /* nFields */ 4, 15241 /* *fields */ soc_IFP_SINGLE_WIDE_F3_0_BCM56560_A0fmt_fields, 15242 /* bits */ 49, 15243 /* flags */ 0, 15244 }, 15245 #endif /* chips */ 15246 15247 #if defined(BCM_56670_B0) 15248 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_0_BCM56670_B0fmt */ 15249 /* format IFP_SINGLE_WIDE_F3_0fmt */ 15250 /* nFields */ 4, 15251 /* *fields */ soc_IFP_SINGLE_WIDE_F3_0_BCM56560_A0fmt_fields, 15252 /* bits */ 49, 15253 /* flags */ 0, 15254 }, 15255 #endif /* chips */ 15256 15257 #if defined(BCM_56680_B0) 15258 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_0_BCM56680_B0fmt */ 15259 /* format IFP_SINGLE_WIDE_F3_0fmt */ 15260 /* nFields */ 3, 15261 /* *fields */ soc_IFP_SINGLE_WIDE_F3_0fmt_fields, 15262 /* bits */ 32, 15263 /* flags */ 0, 15264 }, 15265 #endif /* chips */ 15266 15267 #if defined(BCM_56685_A0) 15268 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_0_BCM56685_A0fmt */ 15269 /* format IFP_SINGLE_WIDE_F3_0fmt */ 15270 /* nFields */ 3, 15271 /* *fields */ soc_IFP_SINGLE_WIDE_F3_0_BCM56634_A0fmt_fields, 15272 /* bits */ 37, 15273 /* flags */ 0, 15274 }, 15275 #endif /* chips */ 15276 15277 #if defined(BCM_56685_B0) 15278 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_0_BCM56685_B0fmt */ 15279 /* format IFP_SINGLE_WIDE_F3_0fmt */ 15280 /* nFields */ 3, 15281 /* *fields */ soc_IFP_SINGLE_WIDE_F3_0_BCM56634_A0fmt_fields, 15282 /* bits */ 37, 15283 /* flags */ 0, 15284 }, 15285 #endif /* chips */ 15286 15287 #if defined(BCM_56725_A0) 15288 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_0_BCM56725_A0fmt */ 15289 /* format IFP_SINGLE_WIDE_F3_0fmt */ 15290 /* nFields */ 4, 15291 /* *fields */ soc_IFP_SINGLE_WIDE_F3_0_BCM56820_A0fmt_fields, 15292 /* bits */ 33, 15293 /* flags */ 0, 15294 }, 15295 #endif /* chips */ 15296 15297 #if defined(BCM_56820_A0) 15298 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_0_BCM56820_A0fmt */ 15299 /* format IFP_SINGLE_WIDE_F3_0fmt */ 15300 /* nFields */ 4, 15301 /* *fields */ soc_IFP_SINGLE_WIDE_F3_0_BCM56820_A0fmt_fields, 15302 /* bits */ 33, 15303 /* flags */ 0, 15304 }, 15305 #endif /* chips */ 15306 15307 #if defined(BCM_56840_A0) 15308 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_0_BCM56840_A0fmt */ 15309 /* format IFP_SINGLE_WIDE_F3_0fmt */ 15310 /* nFields */ 4, 15311 /* *fields */ soc_IFP_SINGLE_WIDE_F3_0_BCM56840_A0fmt_fields, 15312 /* bits */ 39, 15313 /* flags */ 0, 15314 }, 15315 #endif /* chips */ 15316 15317 #if defined(BCM_56840_B0) 15318 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_0_BCM56840_B0fmt */ 15319 /* format IFP_SINGLE_WIDE_F3_0fmt */ 15320 /* nFields */ 4, 15321 /* *fields */ soc_IFP_SINGLE_WIDE_F3_0_BCM56840_A0fmt_fields, 15322 /* bits */ 39, 15323 /* flags */ 0, 15324 }, 15325 #endif /* chips */ 15326 15327 #if defined(BCM_56850_A0) 15328 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_0_BCM56850_A0fmt */ 15329 /* format IFP_SINGLE_WIDE_F3_0fmt */ 15330 /* nFields */ 4, 15331 /* *fields */ soc_IFP_SINGLE_WIDE_F1_0_BCM56850_A0fmt_fields, 15332 /* bits */ 49, 15333 /* flags */ 0, 15334 }, 15335 #endif /* chips */ 15336 15337 #if defined(BCM_56860_A0) 15338 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_0_BCM56860_A0fmt */ 15339 /* format IFP_SINGLE_WIDE_F3_0fmt */ 15340 /* nFields */ 4, 15341 /* *fields */ soc_IFP_SINGLE_WIDE_F1_0_BCM56850_A0fmt_fields, 15342 /* bits */ 49, 15343 /* flags */ 0, 15344 }, 15345 #endif /* chips */ 15346 15347 #if defined(BCM_53400_A0) 15348 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_10_BCM53400_A0fmt */ 15349 /* format IFP_SINGLE_WIDE_F3_10fmt */ 15350 /* nFields */ 4, 15351 /* *fields */ soc_IFP_SINGLE_WIDE_F1_10_BCM53400_A0fmt_fields, 15352 /* bits */ 37, 15353 /* flags */ 0, 15354 }, 15355 #endif /* chips */ 15356 15357 #if defined(BCM_53540_A0) 15358 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_10_BCM53540_A0fmt */ 15359 /* format IFP_SINGLE_WIDE_F3_10fmt */ 15360 /* nFields */ 4, 15361 /* *fields */ soc_IFP_SINGLE_WIDE_F1_10_BCM56160_A0fmt_fields, 15362 /* bits */ 37, 15363 /* flags */ 0, 15364 }, 15365 #endif /* chips */ 15366 15367 #if defined(BCM_53570_A0) 15368 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_10_BCM53570_A0fmt */ 15369 /* format IFP_SINGLE_WIDE_F3_10fmt */ 15370 /* nFields */ 4, 15371 /* *fields */ soc_IFP_SINGLE_WIDE_F1_10_BCM53570_A0fmt_fields, 15372 /* bits */ 39, 15373 /* flags */ 0, 15374 }, 15375 #endif /* chips */ 15376 15377 #if defined(BCM_53570_B0) 15378 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_10_BCM53570_B0fmt */ 15379 /* format IFP_SINGLE_WIDE_F3_10fmt */ 15380 /* nFields */ 4, 15381 /* *fields */ soc_IFP_SINGLE_WIDE_F1_10_BCM53570_A0fmt_fields, 15382 /* bits */ 39, 15383 /* flags */ 0, 15384 }, 15385 #endif /* chips */ 15386 15387 #if defined(BCM_56142_A0) 15388 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_10_BCM56142_A0fmt */ 15389 /* format IFP_SINGLE_WIDE_F3_10fmt */ 15390 /* nFields */ 4, 15391 /* *fields */ soc_IFP_SINGLE_WIDE_F1_10fmt_fields, 15392 /* bits */ 37, 15393 /* flags */ 0, 15394 }, 15395 #endif /* chips */ 15396 15397 #if defined(BCM_56150_A0) 15398 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_10_BCM56150_A0fmt */ 15399 /* format IFP_SINGLE_WIDE_F3_10fmt */ 15400 /* nFields */ 4, 15401 /* *fields */ soc_IFP_SINGLE_WIDE_F1_10_BCM56150_A0fmt_fields, 15402 /* bits */ 37, 15403 /* flags */ 0, 15404 }, 15405 #endif /* chips */ 15406 15407 #if defined(BCM_56160_A0) 15408 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_10_BCM56160_A0fmt */ 15409 /* format IFP_SINGLE_WIDE_F3_10fmt */ 15410 /* nFields */ 4, 15411 /* *fields */ soc_IFP_SINGLE_WIDE_F1_10_BCM56160_A0fmt_fields, 15412 /* bits */ 37, 15413 /* flags */ 0, 15414 }, 15415 #endif /* chips */ 15416 15417 #if defined(BCM_56260_A0) 15418 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_10_BCM56260_A0fmt */ 15419 /* format IFP_SINGLE_WIDE_F3_10fmt */ 15420 /* nFields */ 4, 15421 /* *fields */ soc_IFP_SINGLE_WIDE_F1_10_BCM56260_A0fmt_fields, 15422 /* bits */ 40, 15423 /* flags */ 0, 15424 }, 15425 #endif /* chips */ 15426 15427 #if defined(BCM_56260_B0) 15428 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_10_BCM56260_B0fmt */ 15429 /* format IFP_SINGLE_WIDE_F3_10fmt */ 15430 /* nFields */ 4, 15431 /* *fields */ soc_IFP_SINGLE_WIDE_F1_10_BCM56260_A0fmt_fields, 15432 /* bits */ 40, 15433 /* flags */ 0, 15434 }, 15435 #endif /* chips */ 15436 15437 #if defined(BCM_56270_A0) 15438 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_10_BCM56270_A0fmt */ 15439 /* format IFP_SINGLE_WIDE_F3_10fmt */ 15440 /* nFields */ 4, 15441 /* *fields */ soc_IFP_SINGLE_WIDE_F1_10_BCM56260_A0fmt_fields, 15442 /* bits */ 40, 15443 /* flags */ 0, 15444 }, 15445 #endif /* chips */ 15446 15447 #if defined(BCM_56334_A0) 15448 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_10_BCM56334_A0fmt */ 15449 /* format IFP_SINGLE_WIDE_F3_10fmt */ 15450 /* nFields */ 4, 15451 /* *fields */ soc_IFP_SINGLE_WIDE_F1_10fmt_fields, 15452 /* bits */ 37, 15453 /* flags */ 0, 15454 }, 15455 #endif /* chips */ 15456 15457 #if defined(BCM_56334_B0) 15458 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_10_BCM56334_B0fmt */ 15459 /* format IFP_SINGLE_WIDE_F3_10fmt */ 15460 /* nFields */ 4, 15461 /* *fields */ soc_IFP_SINGLE_WIDE_F1_10fmt_fields, 15462 /* bits */ 37, 15463 /* flags */ 0, 15464 }, 15465 #endif /* chips */ 15466 15467 #if defined(BCM_56340_A0) 15468 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_10_BCM56340_A0fmt */ 15469 /* format IFP_SINGLE_WIDE_F3_10fmt */ 15470 /* nFields */ 4, 15471 /* *fields */ soc_IFP_SINGLE_WIDE_F1_10_BCM56640_A0fmt_fields, 15472 /* bits */ 49, 15473 /* flags */ 0, 15474 }, 15475 #endif /* chips */ 15476 15477 #if defined(BCM_56440_A0) 15478 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_10_BCM56440_A0fmt */ 15479 /* format IFP_SINGLE_WIDE_F3_10fmt */ 15480 /* nFields */ 4, 15481 /* *fields */ soc_IFP_SINGLE_WIDE_F1_10_BCM56840_A0fmt_fields, 15482 /* bits */ 39, 15483 /* flags */ 0, 15484 }, 15485 #endif /* chips */ 15486 15487 #if defined(BCM_56440_B0) 15488 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_10_BCM56440_B0fmt */ 15489 /* format IFP_SINGLE_WIDE_F3_10fmt */ 15490 /* nFields */ 4, 15491 /* *fields */ soc_IFP_SINGLE_WIDE_F1_10_BCM56840_A0fmt_fields, 15492 /* bits */ 39, 15493 /* flags */ 0, 15494 }, 15495 #endif /* chips */ 15496 15497 #if defined(BCM_56450_A0) 15498 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_10_BCM56450_A0fmt */ 15499 /* format IFP_SINGLE_WIDE_F3_10fmt */ 15500 /* nFields */ 4, 15501 /* *fields */ soc_IFP_SINGLE_WIDE_F1_10_BCM56450_A0fmt_fields, 15502 /* bits */ 40, 15503 /* flags */ 0, 15504 }, 15505 #endif /* chips */ 15506 15507 #if defined(BCM_56450_B0) 15508 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_10_BCM56450_B0fmt */ 15509 /* format IFP_SINGLE_WIDE_F3_10fmt */ 15510 /* nFields */ 4, 15511 /* *fields */ soc_IFP_SINGLE_WIDE_F1_10_BCM56450_A0fmt_fields, 15512 /* bits */ 40, 15513 /* flags */ 0, 15514 }, 15515 #endif /* chips */ 15516 15517 #if defined(BCM_56450_B1) 15518 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_10_BCM56450_B1fmt */ 15519 /* format IFP_SINGLE_WIDE_F3_10fmt */ 15520 /* nFields */ 4, 15521 /* *fields */ soc_IFP_SINGLE_WIDE_F1_10_BCM56450_A0fmt_fields, 15522 /* bits */ 40, 15523 /* flags */ 0, 15524 }, 15525 #endif /* chips */ 15526 15527 #if defined(BCM_56524_A0) 15528 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_10_BCM56524_A0fmt */ 15529 /* format IFP_SINGLE_WIDE_F3_10fmt */ 15530 /* nFields */ 4, 15531 /* *fields */ soc_IFP_SINGLE_WIDE_F1_10fmt_fields, 15532 /* bits */ 37, 15533 /* flags */ 0, 15534 }, 15535 #endif /* chips */ 15536 15537 #if defined(BCM_56524_B0) 15538 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_10_BCM56524_B0fmt */ 15539 /* format IFP_SINGLE_WIDE_F3_10fmt */ 15540 /* nFields */ 4, 15541 /* *fields */ soc_IFP_SINGLE_WIDE_F1_10fmt_fields, 15542 /* bits */ 37, 15543 /* flags */ 0, 15544 }, 15545 #endif /* chips */ 15546 15547 #if defined(BCM_56560_A0) 15548 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_10_BCM56560_A0fmt */ 15549 /* format IFP_SINGLE_WIDE_F3_10fmt */ 15550 /* nFields */ 4, 15551 /* *fields */ soc_IFP_SINGLE_WIDE_F3_10fmt_fields, 15552 /* bits */ 49, 15553 /* flags */ 0, 15554 }, 15555 #endif /* chips */ 15556 15557 #if defined(BCM_56560_B0) 15558 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_10_BCM56560_B0fmt */ 15559 /* format IFP_SINGLE_WIDE_F3_10fmt */ 15560 /* nFields */ 4, 15561 /* *fields */ soc_IFP_SINGLE_WIDE_F3_10fmt_fields, 15562 /* bits */ 49, 15563 /* flags */ 0, 15564 }, 15565 #endif /* chips */ 15566 15567 #if defined(BCM_56634_B0) 15568 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_10_BCM56634_B0fmt */ 15569 /* format IFP_SINGLE_WIDE_F3_10fmt */ 15570 /* nFields */ 4, 15571 /* *fields */ soc_IFP_SINGLE_WIDE_F1_10fmt_fields, 15572 /* bits */ 37, 15573 /* flags */ 0, 15574 }, 15575 #endif /* chips */ 15576 15577 #if defined(BCM_56640_A0) 15578 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_10_BCM56640_A0fmt */ 15579 /* format IFP_SINGLE_WIDE_F3_10fmt */ 15580 /* nFields */ 4, 15581 /* *fields */ soc_IFP_SINGLE_WIDE_F1_10_BCM56640_A0fmt_fields, 15582 /* bits */ 49, 15583 /* flags */ 0, 15584 }, 15585 #endif /* chips */ 15586 15587 #if defined(BCM_56670_A0) 15588 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_10_BCM56670_A0fmt */ 15589 /* format IFP_SINGLE_WIDE_F3_10fmt */ 15590 /* nFields */ 7, 15591 /* *fields */ soc_IFP_SINGLE_WIDE_F3_10_BCM56670_A0fmt_fields, 15592 /* bits */ 49, 15593 /* flags */ 0, 15594 }, 15595 #endif /* chips */ 15596 15597 #if defined(BCM_56670_B0) 15598 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_10_BCM56670_B0fmt */ 15599 /* format IFP_SINGLE_WIDE_F3_10fmt */ 15600 /* nFields */ 7, 15601 /* *fields */ soc_IFP_SINGLE_WIDE_F3_10_BCM56670_A0fmt_fields, 15602 /* bits */ 49, 15603 /* flags */ 0, 15604 }, 15605 #endif /* chips */ 15606 15607 #if defined(BCM_56685_A0) 15608 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_10_BCM56685_A0fmt */ 15609 /* format IFP_SINGLE_WIDE_F3_10fmt */ 15610 /* nFields */ 4, 15611 /* *fields */ soc_IFP_SINGLE_WIDE_F1_10fmt_fields, 15612 /* bits */ 37, 15613 /* flags */ 0, 15614 }, 15615 #endif /* chips */ 15616 15617 #if defined(BCM_56685_B0) 15618 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_10_BCM56685_B0fmt */ 15619 /* format IFP_SINGLE_WIDE_F3_10fmt */ 15620 /* nFields */ 4, 15621 /* *fields */ soc_IFP_SINGLE_WIDE_F1_10fmt_fields, 15622 /* bits */ 37, 15623 /* flags */ 0, 15624 }, 15625 #endif /* chips */ 15626 15627 #if defined(BCM_56840_A0) 15628 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_10_BCM56840_A0fmt */ 15629 /* format IFP_SINGLE_WIDE_F3_10fmt */ 15630 /* nFields */ 4, 15631 /* *fields */ soc_IFP_SINGLE_WIDE_F1_10_BCM56840_A0fmt_fields, 15632 /* bits */ 39, 15633 /* flags */ 0, 15634 }, 15635 #endif /* chips */ 15636 15637 #if defined(BCM_56840_B0) 15638 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_10_BCM56840_B0fmt */ 15639 /* format IFP_SINGLE_WIDE_F3_10fmt */ 15640 /* nFields */ 4, 15641 /* *fields */ soc_IFP_SINGLE_WIDE_F1_10_BCM56840_A0fmt_fields, 15642 /* bits */ 39, 15643 /* flags */ 0, 15644 }, 15645 #endif /* chips */ 15646 15647 #if defined(BCM_56850_A0) 15648 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_10_BCM56850_A0fmt */ 15649 /* format IFP_SINGLE_WIDE_F3_10fmt */ 15650 /* nFields */ 4, 15651 /* *fields */ soc_IFP_SINGLE_WIDE_F1_10_BCM56640_A0fmt_fields, 15652 /* bits */ 49, 15653 /* flags */ 0, 15654 }, 15655 #endif /* chips */ 15656 15657 #if defined(BCM_56860_A0) 15658 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_10_BCM56860_A0fmt */ 15659 /* format IFP_SINGLE_WIDE_F3_10fmt */ 15660 /* nFields */ 4, 15661 /* *fields */ soc_IFP_SINGLE_WIDE_F1_10_BCM56640_A0fmt_fields, 15662 /* bits */ 49, 15663 /* flags */ 0, 15664 }, 15665 #endif /* chips */ 15666 15667 #if defined(BCM_53400_A0) 15668 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_11_BCM53400_A0fmt */ 15669 /* format IFP_SINGLE_WIDE_F3_11fmt */ 15670 /* nFields */ 4, 15671 /* *fields */ soc_IFP_SINGLE_WIDE_F1_11_BCM53400_A0fmt_fields, 15672 /* bits */ 37, 15673 /* flags */ 0, 15674 }, 15675 #endif /* chips */ 15676 15677 #if defined(BCM_53540_A0) 15678 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_11_BCM53540_A0fmt */ 15679 /* format IFP_SINGLE_WIDE_F3_11fmt */ 15680 /* nFields */ 4, 15681 /* *fields */ soc_IFP_SINGLE_WIDE_F1_11_BCM56160_A0fmt_fields, 15682 /* bits */ 37, 15683 /* flags */ 0, 15684 }, 15685 #endif /* chips */ 15686 15687 #if defined(BCM_53570_A0) 15688 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_11_BCM53570_A0fmt */ 15689 /* format IFP_SINGLE_WIDE_F3_11fmt */ 15690 /* nFields */ 4, 15691 /* *fields */ soc_IFP_SINGLE_WIDE_F1_11_BCM53570_A0fmt_fields, 15692 /* bits */ 39, 15693 /* flags */ 0, 15694 }, 15695 #endif /* chips */ 15696 15697 #if defined(BCM_53570_B0) 15698 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_11_BCM53570_B0fmt */ 15699 /* format IFP_SINGLE_WIDE_F3_11fmt */ 15700 /* nFields */ 4, 15701 /* *fields */ soc_IFP_SINGLE_WIDE_F1_11_BCM53570_A0fmt_fields, 15702 /* bits */ 39, 15703 /* flags */ 0, 15704 }, 15705 #endif /* chips */ 15706 15707 #if defined(BCM_56142_A0) 15708 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_11_BCM56142_A0fmt */ 15709 /* format IFP_SINGLE_WIDE_F3_11fmt */ 15710 /* nFields */ 4, 15711 /* *fields */ soc_IFP_SINGLE_WIDE_F1_11fmt_fields, 15712 /* bits */ 37, 15713 /* flags */ 0, 15714 }, 15715 #endif /* chips */ 15716 15717 #if defined(BCM_56150_A0) 15718 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_11_BCM56150_A0fmt */ 15719 /* format IFP_SINGLE_WIDE_F3_11fmt */ 15720 /* nFields */ 4, 15721 /* *fields */ soc_IFP_SINGLE_WIDE_F1_11_BCM56150_A0fmt_fields, 15722 /* bits */ 37, 15723 /* flags */ 0, 15724 }, 15725 #endif /* chips */ 15726 15727 #if defined(BCM_56160_A0) 15728 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_11_BCM56160_A0fmt */ 15729 /* format IFP_SINGLE_WIDE_F3_11fmt */ 15730 /* nFields */ 4, 15731 /* *fields */ soc_IFP_SINGLE_WIDE_F1_11_BCM56160_A0fmt_fields, 15732 /* bits */ 37, 15733 /* flags */ 0, 15734 }, 15735 #endif /* chips */ 15736 15737 #if defined(BCM_56260_A0) 15738 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_11_BCM56260_A0fmt */ 15739 /* format IFP_SINGLE_WIDE_F3_11fmt */ 15740 /* nFields */ 4, 15741 /* *fields */ soc_IFP_SINGLE_WIDE_F3_11_BCM56260_A0fmt_fields, 15742 /* bits */ 40, 15743 /* flags */ 0, 15744 }, 15745 #endif /* chips */ 15746 15747 #if defined(BCM_56260_B0) 15748 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_11_BCM56260_B0fmt */ 15749 /* format IFP_SINGLE_WIDE_F3_11fmt */ 15750 /* nFields */ 4, 15751 /* *fields */ soc_IFP_SINGLE_WIDE_F3_11_BCM56260_A0fmt_fields, 15752 /* bits */ 40, 15753 /* flags */ 0, 15754 }, 15755 #endif /* chips */ 15756 15757 #if defined(BCM_56270_A0) 15758 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_11_BCM56270_A0fmt */ 15759 /* format IFP_SINGLE_WIDE_F3_11fmt */ 15760 /* nFields */ 4, 15761 /* *fields */ soc_IFP_SINGLE_WIDE_F3_11_BCM56260_A0fmt_fields, 15762 /* bits */ 40, 15763 /* flags */ 0, 15764 }, 15765 #endif /* chips */ 15766 15767 #if defined(BCM_56334_A0) 15768 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_11_BCM56334_A0fmt */ 15769 /* format IFP_SINGLE_WIDE_F3_11fmt */ 15770 /* nFields */ 4, 15771 /* *fields */ soc_IFP_SINGLE_WIDE_F1_11fmt_fields, 15772 /* bits */ 37, 15773 /* flags */ 0, 15774 }, 15775 #endif /* chips */ 15776 15777 #if defined(BCM_56334_B0) 15778 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_11_BCM56334_B0fmt */ 15779 /* format IFP_SINGLE_WIDE_F3_11fmt */ 15780 /* nFields */ 4, 15781 /* *fields */ soc_IFP_SINGLE_WIDE_F1_11fmt_fields, 15782 /* bits */ 37, 15783 /* flags */ 0, 15784 }, 15785 #endif /* chips */ 15786 15787 #if defined(BCM_56340_A0) 15788 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_11_BCM56340_A0fmt */ 15789 /* format IFP_SINGLE_WIDE_F3_11fmt */ 15790 /* nFields */ 4, 15791 /* *fields */ soc_IFP_SINGLE_WIDE_F3_11_BCM56340_A0fmt_fields, 15792 /* bits */ 49, 15793 /* flags */ 0, 15794 }, 15795 #endif /* chips */ 15796 15797 #if defined(BCM_56440_A0) 15798 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_11_BCM56440_A0fmt */ 15799 /* format IFP_SINGLE_WIDE_F3_11fmt */ 15800 /* nFields */ 4, 15801 /* *fields */ soc_IFP_SINGLE_WIDE_F1_11_BCM56840_A0fmt_fields, 15802 /* bits */ 39, 15803 /* flags */ 0, 15804 }, 15805 #endif /* chips */ 15806 15807 #if defined(BCM_56440_B0) 15808 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_11_BCM56440_B0fmt */ 15809 /* format IFP_SINGLE_WIDE_F3_11fmt */ 15810 /* nFields */ 4, 15811 /* *fields */ soc_IFP_SINGLE_WIDE_F1_11_BCM56840_A0fmt_fields, 15812 /* bits */ 39, 15813 /* flags */ 0, 15814 }, 15815 #endif /* chips */ 15816 15817 #if defined(BCM_56450_A0) 15818 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_11_BCM56450_A0fmt */ 15819 /* format IFP_SINGLE_WIDE_F3_11fmt */ 15820 /* nFields */ 4, 15821 /* *fields */ soc_IFP_SINGLE_WIDE_F3_11_BCM56450_A0fmt_fields, 15822 /* bits */ 40, 15823 /* flags */ 0, 15824 }, 15825 #endif /* chips */ 15826 15827 #if defined(BCM_56450_B0) 15828 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_11_BCM56450_B0fmt */ 15829 /* format IFP_SINGLE_WIDE_F3_11fmt */ 15830 /* nFields */ 4, 15831 /* *fields */ soc_IFP_SINGLE_WIDE_F3_11_BCM56450_A0fmt_fields, 15832 /* bits */ 40, 15833 /* flags */ 0, 15834 }, 15835 #endif /* chips */ 15836 15837 #if defined(BCM_56450_B1) 15838 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_11_BCM56450_B1fmt */ 15839 /* format IFP_SINGLE_WIDE_F3_11fmt */ 15840 /* nFields */ 4, 15841 /* *fields */ soc_IFP_SINGLE_WIDE_F3_11_BCM56450_A0fmt_fields, 15842 /* bits */ 40, 15843 /* flags */ 0, 15844 }, 15845 #endif /* chips */ 15846 15847 #if defined(BCM_56524_A0) 15848 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_11_BCM56524_A0fmt */ 15849 /* format IFP_SINGLE_WIDE_F3_11fmt */ 15850 /* nFields */ 4, 15851 /* *fields */ soc_IFP_SINGLE_WIDE_F1_11fmt_fields, 15852 /* bits */ 37, 15853 /* flags */ 0, 15854 }, 15855 #endif /* chips */ 15856 15857 #if defined(BCM_56524_B0) 15858 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_11_BCM56524_B0fmt */ 15859 /* format IFP_SINGLE_WIDE_F3_11fmt */ 15860 /* nFields */ 4, 15861 /* *fields */ soc_IFP_SINGLE_WIDE_F1_11fmt_fields, 15862 /* bits */ 37, 15863 /* flags */ 0, 15864 }, 15865 #endif /* chips */ 15866 15867 #if defined(BCM_56560_A0) 15868 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_11_BCM56560_A0fmt */ 15869 /* format IFP_SINGLE_WIDE_F3_11fmt */ 15870 /* nFields */ 3, 15871 /* *fields */ soc_IFP_SINGLE_WIDE_F3_11_BCM56560_A0fmt_fields, 15872 /* bits */ 49, 15873 /* flags */ 0, 15874 }, 15875 #endif /* chips */ 15876 15877 #if defined(BCM_56560_B0) 15878 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_11_BCM56560_B0fmt */ 15879 /* format IFP_SINGLE_WIDE_F3_11fmt */ 15880 /* nFields */ 3, 15881 /* *fields */ soc_IFP_SINGLE_WIDE_F3_11_BCM56560_A0fmt_fields, 15882 /* bits */ 49, 15883 /* flags */ 0, 15884 }, 15885 #endif /* chips */ 15886 15887 #if defined(BCM_56634_B0) 15888 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_11_BCM56634_B0fmt */ 15889 /* format IFP_SINGLE_WIDE_F3_11fmt */ 15890 /* nFields */ 4, 15891 /* *fields */ soc_IFP_SINGLE_WIDE_F1_11fmt_fields, 15892 /* bits */ 37, 15893 /* flags */ 0, 15894 }, 15895 #endif /* chips */ 15896 15897 #if defined(BCM_56640_A0) 15898 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_11_BCM56640_A0fmt */ 15899 /* format IFP_SINGLE_WIDE_F3_11fmt */ 15900 /* nFields */ 4, 15901 /* *fields */ soc_IFP_SINGLE_WIDE_F3_11fmt_fields, 15902 /* bits */ 49, 15903 /* flags */ 0, 15904 }, 15905 #endif /* chips */ 15906 15907 #if defined(BCM_56670_A0) 15908 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_11_BCM56670_A0fmt */ 15909 /* format IFP_SINGLE_WIDE_F3_11fmt */ 15910 /* nFields */ 6, 15911 /* *fields */ soc_IFP_SINGLE_WIDE_F3_11_BCM56670_A0fmt_fields, 15912 /* bits */ 49, 15913 /* flags */ 0, 15914 }, 15915 #endif /* chips */ 15916 15917 #if defined(BCM_56670_B0) 15918 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_11_BCM56670_B0fmt */ 15919 /* format IFP_SINGLE_WIDE_F3_11fmt */ 15920 /* nFields */ 6, 15921 /* *fields */ soc_IFP_SINGLE_WIDE_F3_11_BCM56670_A0fmt_fields, 15922 /* bits */ 49, 15923 /* flags */ 0, 15924 }, 15925 #endif /* chips */ 15926 15927 #if defined(BCM_56685_A0) 15928 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_11_BCM56685_A0fmt */ 15929 /* format IFP_SINGLE_WIDE_F3_11fmt */ 15930 /* nFields */ 4, 15931 /* *fields */ soc_IFP_SINGLE_WIDE_F1_11fmt_fields, 15932 /* bits */ 37, 15933 /* flags */ 0, 15934 }, 15935 #endif /* chips */ 15936 15937 #if defined(BCM_56685_B0) 15938 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_11_BCM56685_B0fmt */ 15939 /* format IFP_SINGLE_WIDE_F3_11fmt */ 15940 /* nFields */ 4, 15941 /* *fields */ soc_IFP_SINGLE_WIDE_F1_11fmt_fields, 15942 /* bits */ 37, 15943 /* flags */ 0, 15944 }, 15945 #endif /* chips */ 15946 15947 #if defined(BCM_56840_A0) 15948 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_11_BCM56840_A0fmt */ 15949 /* format IFP_SINGLE_WIDE_F3_11fmt */ 15950 /* nFields */ 4, 15951 /* *fields */ soc_IFP_SINGLE_WIDE_F1_11_BCM56840_A0fmt_fields, 15952 /* bits */ 39, 15953 /* flags */ 0, 15954 }, 15955 #endif /* chips */ 15956 15957 #if defined(BCM_56840_B0) 15958 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_11_BCM56840_B0fmt */ 15959 /* format IFP_SINGLE_WIDE_F3_11fmt */ 15960 /* nFields */ 4, 15961 /* *fields */ soc_IFP_SINGLE_WIDE_F1_11_BCM56840_A0fmt_fields, 15962 /* bits */ 39, 15963 /* flags */ 0, 15964 }, 15965 #endif /* chips */ 15966 15967 #if defined(BCM_56850_A0) 15968 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_11_BCM56850_A0fmt */ 15969 /* format IFP_SINGLE_WIDE_F3_11fmt */ 15970 /* nFields */ 3, 15971 /* *fields */ soc_IFP_SINGLE_WIDE_F3_11_BCM56850_A0fmt_fields, 15972 /* bits */ 49, 15973 /* flags */ 0, 15974 }, 15975 #endif /* chips */ 15976 15977 #if defined(BCM_56860_A0) 15978 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_11_BCM56860_A0fmt */ 15979 /* format IFP_SINGLE_WIDE_F3_11fmt */ 15980 /* nFields */ 3, 15981 /* *fields */ soc_IFP_SINGLE_WIDE_F3_11_BCM56850_A0fmt_fields, 15982 /* bits */ 49, 15983 /* flags */ 0, 15984 }, 15985 #endif /* chips */ 15986 15987 #if defined(BCM_53400_A0) 15988 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_12_BCM53400_A0fmt */ 15989 /* format IFP_SINGLE_WIDE_F3_12fmt */ 15990 /* nFields */ 3, 15991 /* *fields */ soc_IFP_SINGLE_WIDE_F3_12_BCM53400_A0fmt_fields, 15992 /* bits */ 37, 15993 /* flags */ 0, 15994 }, 15995 #endif /* chips */ 15996 15997 #if defined(BCM_53540_A0) 15998 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_12_BCM53540_A0fmt */ 15999 /* format IFP_SINGLE_WIDE_F3_12fmt */ 16000 /* nFields */ 3, 16001 /* *fields */ soc_IFP_SINGLE_WIDE_F3_12_BCM53400_A0fmt_fields, 16002 /* bits */ 37, 16003 /* flags */ 0, 16004 }, 16005 #endif /* chips */ 16006 16007 #if defined(BCM_53570_A0) 16008 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_12_BCM53570_A0fmt */ 16009 /* format IFP_SINGLE_WIDE_F3_12fmt */ 16010 /* nFields */ 3, 16011 /* *fields */ soc_IFP_SINGLE_WIDE_F3_12_BCM53570_A0fmt_fields, 16012 /* bits */ 39, 16013 /* flags */ 0, 16014 }, 16015 #endif /* chips */ 16016 16017 #if defined(BCM_53570_B0) 16018 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_12_BCM53570_B0fmt */ 16019 /* format IFP_SINGLE_WIDE_F3_12fmt */ 16020 /* nFields */ 3, 16021 /* *fields */ soc_IFP_SINGLE_WIDE_F3_12_BCM53570_A0fmt_fields, 16022 /* bits */ 39, 16023 /* flags */ 0, 16024 }, 16025 #endif /* chips */ 16026 16027 #if defined(BCM_56160_A0) 16028 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_12_BCM56160_A0fmt */ 16029 /* format IFP_SINGLE_WIDE_F3_12fmt */ 16030 /* nFields */ 3, 16031 /* *fields */ soc_IFP_SINGLE_WIDE_F3_12_BCM53400_A0fmt_fields, 16032 /* bits */ 37, 16033 /* flags */ 0, 16034 }, 16035 #endif /* chips */ 16036 16037 #if defined(BCM_56260_A0) 16038 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_12_BCM56260_A0fmt */ 16039 /* format IFP_SINGLE_WIDE_F3_12fmt */ 16040 /* nFields */ 4, 16041 /* *fields */ soc_IFP_SINGLE_WIDE_F3_12_BCM56260_A0fmt_fields, 16042 /* bits */ 40, 16043 /* flags */ 0, 16044 }, 16045 #endif /* chips */ 16046 16047 #if defined(BCM_56260_B0) 16048 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_12_BCM56260_B0fmt */ 16049 /* format IFP_SINGLE_WIDE_F3_12fmt */ 16050 /* nFields */ 4, 16051 /* *fields */ soc_IFP_SINGLE_WIDE_F3_12_BCM56260_A0fmt_fields, 16052 /* bits */ 40, 16053 /* flags */ 0, 16054 }, 16055 #endif /* chips */ 16056 16057 #if defined(BCM_56270_A0) 16058 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_12_BCM56270_A0fmt */ 16059 /* format IFP_SINGLE_WIDE_F3_12fmt */ 16060 /* nFields */ 4, 16061 /* *fields */ soc_IFP_SINGLE_WIDE_F3_12_BCM56260_A0fmt_fields, 16062 /* bits */ 40, 16063 /* flags */ 0, 16064 }, 16065 #endif /* chips */ 16066 16067 #if defined(BCM_56340_A0) 16068 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_12_BCM56340_A0fmt */ 16069 /* format IFP_SINGLE_WIDE_F3_12fmt */ 16070 /* nFields */ 9, 16071 /* *fields */ soc_IFP_SINGLE_WIDE_F3_12_BCM56640_A0fmt_fields, 16072 /* bits */ 49, 16073 /* flags */ 0, 16074 }, 16075 #endif /* chips */ 16076 16077 #if defined(BCM_56440_A0) 16078 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_12_BCM56440_A0fmt */ 16079 /* format IFP_SINGLE_WIDE_F3_12fmt */ 16080 /* nFields */ 3, 16081 /* *fields */ soc_IFP_SINGLE_WIDE_F3_12fmt_fields, 16082 /* bits */ 39, 16083 /* flags */ 0, 16084 }, 16085 #endif /* chips */ 16086 16087 #if defined(BCM_56440_B0) 16088 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_12_BCM56440_B0fmt */ 16089 /* format IFP_SINGLE_WIDE_F3_12fmt */ 16090 /* nFields */ 3, 16091 /* *fields */ soc_IFP_SINGLE_WIDE_F3_12fmt_fields, 16092 /* bits */ 39, 16093 /* flags */ 0, 16094 }, 16095 #endif /* chips */ 16096 16097 #if defined(BCM_56450_A0) 16098 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_12_BCM56450_A0fmt */ 16099 /* format IFP_SINGLE_WIDE_F3_12fmt */ 16100 /* nFields */ 4, 16101 /* *fields */ soc_IFP_SINGLE_WIDE_F3_12_BCM56450_A0fmt_fields, 16102 /* bits */ 40, 16103 /* flags */ 0, 16104 }, 16105 #endif /* chips */ 16106 16107 #if defined(BCM_56450_B0) 16108 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_12_BCM56450_B0fmt */ 16109 /* format IFP_SINGLE_WIDE_F3_12fmt */ 16110 /* nFields */ 4, 16111 /* *fields */ soc_IFP_SINGLE_WIDE_F3_12_BCM56450_A0fmt_fields, 16112 /* bits */ 40, 16113 /* flags */ 0, 16114 }, 16115 #endif /* chips */ 16116 16117 #if defined(BCM_56450_B1) 16118 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_12_BCM56450_B1fmt */ 16119 /* format IFP_SINGLE_WIDE_F3_12fmt */ 16120 /* nFields */ 4, 16121 /* *fields */ soc_IFP_SINGLE_WIDE_F3_12_BCM56450_A0fmt_fields, 16122 /* bits */ 40, 16123 /* flags */ 0, 16124 }, 16125 #endif /* chips */ 16126 16127 #if defined(BCM_56560_A0) 16128 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_12_BCM56560_A0fmt */ 16129 /* format IFP_SINGLE_WIDE_F3_12fmt */ 16130 /* nFields */ 12, 16131 /* *fields */ soc_IFP_SINGLE_WIDE_F3_12_BCM56560_A0fmt_fields, 16132 /* bits */ 49, 16133 /* flags */ 0, 16134 }, 16135 #endif /* chips */ 16136 16137 #if defined(BCM_56560_B0) 16138 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_12_BCM56560_B0fmt */ 16139 /* format IFP_SINGLE_WIDE_F3_12fmt */ 16140 /* nFields */ 12, 16141 /* *fields */ soc_IFP_SINGLE_WIDE_F3_12_BCM56560_A0fmt_fields, 16142 /* bits */ 49, 16143 /* flags */ 0, 16144 }, 16145 #endif /* chips */ 16146 16147 #if defined(BCM_56640_A0) 16148 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_12_BCM56640_A0fmt */ 16149 /* format IFP_SINGLE_WIDE_F3_12fmt */ 16150 /* nFields */ 9, 16151 /* *fields */ soc_IFP_SINGLE_WIDE_F3_12_BCM56640_A0fmt_fields, 16152 /* bits */ 49, 16153 /* flags */ 0, 16154 }, 16155 #endif /* chips */ 16156 16157 #if defined(BCM_56670_A0) 16158 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_12_BCM56670_A0fmt */ 16159 /* format IFP_SINGLE_WIDE_F3_12fmt */ 16160 /* nFields */ 12, 16161 /* *fields */ soc_IFP_SINGLE_WIDE_F3_12_BCM56560_A0fmt_fields, 16162 /* bits */ 49, 16163 /* flags */ 0, 16164 }, 16165 #endif /* chips */ 16166 16167 #if defined(BCM_56670_B0) 16168 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_12_BCM56670_B0fmt */ 16169 /* format IFP_SINGLE_WIDE_F3_12fmt */ 16170 /* nFields */ 12, 16171 /* *fields */ soc_IFP_SINGLE_WIDE_F3_12_BCM56560_A0fmt_fields, 16172 /* bits */ 49, 16173 /* flags */ 0, 16174 }, 16175 #endif /* chips */ 16176 16177 #if defined(BCM_56840_B0) 16178 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_12_BCM56840_B0fmt */ 16179 /* format IFP_SINGLE_WIDE_F3_12fmt */ 16180 /* nFields */ 3, 16181 /* *fields */ soc_IFP_SINGLE_WIDE_F3_12fmt_fields, 16182 /* bits */ 39, 16183 /* flags */ 0, 16184 }, 16185 #endif /* chips */ 16186 16187 #if defined(BCM_56850_A0) 16188 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_12_BCM56850_A0fmt */ 16189 /* format IFP_SINGLE_WIDE_F3_12fmt */ 16190 /* nFields */ 11, 16191 /* *fields */ soc_IFP_SINGLE_WIDE_F3_12_BCM56850_A0fmt_fields, 16192 /* bits */ 49, 16193 /* flags */ 0, 16194 }, 16195 #endif /* chips */ 16196 16197 #if defined(BCM_56860_A0) 16198 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_12_BCM56860_A0fmt */ 16199 /* format IFP_SINGLE_WIDE_F3_12fmt */ 16200 /* nFields */ 12, 16201 /* *fields */ soc_IFP_SINGLE_WIDE_F3_12_BCM56860_A0fmt_fields, 16202 /* bits */ 49, 16203 /* flags */ 0, 16204 }, 16205 #endif /* chips */ 16206 16207 #if defined(BCM_53570_A0) 16208 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_13_BCM53570_A0fmt */ 16209 /* format IFP_SINGLE_WIDE_F3_13fmt */ 16210 /* nFields */ 5, 16211 /* *fields */ soc_IFP_SINGLE_WIDE_F3_13_BCM53570_A0fmt_fields, 16212 /* bits */ 39, 16213 /* flags */ 0, 16214 }, 16215 #endif /* chips */ 16216 16217 #if defined(BCM_53570_B0) 16218 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_13_BCM53570_B0fmt */ 16219 /* format IFP_SINGLE_WIDE_F3_13fmt */ 16220 /* nFields */ 5, 16221 /* *fields */ soc_IFP_SINGLE_WIDE_F3_13_BCM53570_A0fmt_fields, 16222 /* bits */ 39, 16223 /* flags */ 0, 16224 }, 16225 #endif /* chips */ 16226 16227 #if defined(BCM_56260_A0) 16228 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_13_BCM56260_A0fmt */ 16229 /* format IFP_SINGLE_WIDE_F3_13fmt */ 16230 /* nFields */ 5, 16231 /* *fields */ soc_IFP_SINGLE_WIDE_F3_13_BCM56260_A0fmt_fields, 16232 /* bits */ 40, 16233 /* flags */ 0, 16234 }, 16235 #endif /* chips */ 16236 16237 #if defined(BCM_56260_B0) 16238 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_13_BCM56260_B0fmt */ 16239 /* format IFP_SINGLE_WIDE_F3_13fmt */ 16240 /* nFields */ 5, 16241 /* *fields */ soc_IFP_SINGLE_WIDE_F3_13_BCM56260_A0fmt_fields, 16242 /* bits */ 40, 16243 /* flags */ 0, 16244 }, 16245 #endif /* chips */ 16246 16247 #if defined(BCM_56270_A0) 16248 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_13_BCM56270_A0fmt */ 16249 /* format IFP_SINGLE_WIDE_F3_13fmt */ 16250 /* nFields */ 5, 16251 /* *fields */ soc_IFP_SINGLE_WIDE_F3_13_BCM56260_A0fmt_fields, 16252 /* bits */ 40, 16253 /* flags */ 0, 16254 }, 16255 #endif /* chips */ 16256 16257 #if defined(BCM_56340_A0) 16258 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_13_BCM56340_A0fmt */ 16259 /* format IFP_SINGLE_WIDE_F3_13fmt */ 16260 /* nFields */ 8, 16261 /* *fields */ soc_IFP_SINGLE_WIDE_F3_13_BCM56640_A0fmt_fields, 16262 /* bits */ 49, 16263 /* flags */ 0, 16264 }, 16265 #endif /* chips */ 16266 16267 #if defined(BCM_56450_A0) 16268 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_13_BCM56450_A0fmt */ 16269 /* format IFP_SINGLE_WIDE_F3_13fmt */ 16270 /* nFields */ 5, 16271 /* *fields */ soc_IFP_SINGLE_WIDE_F3_13_BCM56450_A0fmt_fields, 16272 /* bits */ 40, 16273 /* flags */ 0, 16274 }, 16275 #endif /* chips */ 16276 16277 #if defined(BCM_56450_B0) 16278 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_13_BCM56450_B0fmt */ 16279 /* format IFP_SINGLE_WIDE_F3_13fmt */ 16280 /* nFields */ 5, 16281 /* *fields */ soc_IFP_SINGLE_WIDE_F3_13_BCM56450_A0fmt_fields, 16282 /* bits */ 40, 16283 /* flags */ 0, 16284 }, 16285 #endif /* chips */ 16286 16287 #if defined(BCM_56450_B1) 16288 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_13_BCM56450_B1fmt */ 16289 /* format IFP_SINGLE_WIDE_F3_13fmt */ 16290 /* nFields */ 5, 16291 /* *fields */ soc_IFP_SINGLE_WIDE_F3_13_BCM56450_A0fmt_fields, 16292 /* bits */ 40, 16293 /* flags */ 0, 16294 }, 16295 #endif /* chips */ 16296 16297 #if defined(BCM_56560_A0) 16298 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_13_BCM56560_A0fmt */ 16299 /* format IFP_SINGLE_WIDE_F3_13fmt */ 16300 /* nFields */ 8, 16301 /* *fields */ soc_IFP_SINGLE_WIDE_F3_13_BCM56560_A0fmt_fields, 16302 /* bits */ 49, 16303 /* flags */ 0, 16304 }, 16305 #endif /* chips */ 16306 16307 #if defined(BCM_56560_B0) 16308 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_13_BCM56560_B0fmt */ 16309 /* format IFP_SINGLE_WIDE_F3_13fmt */ 16310 /* nFields */ 8, 16311 /* *fields */ soc_IFP_SINGLE_WIDE_F3_13_BCM56560_A0fmt_fields, 16312 /* bits */ 49, 16313 /* flags */ 0, 16314 }, 16315 #endif /* chips */ 16316 16317 #if defined(BCM_56640_A0) 16318 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_13_BCM56640_A0fmt */ 16319 /* format IFP_SINGLE_WIDE_F3_13fmt */ 16320 /* nFields */ 8, 16321 /* *fields */ soc_IFP_SINGLE_WIDE_F3_13_BCM56640_A0fmt_fields, 16322 /* bits */ 49, 16323 /* flags */ 0, 16324 }, 16325 #endif /* chips */ 16326 16327 #if defined(BCM_56670_A0) 16328 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_13_BCM56670_A0fmt */ 16329 /* format IFP_SINGLE_WIDE_F3_13fmt */ 16330 /* nFields */ 8, 16331 /* *fields */ soc_IFP_SINGLE_WIDE_F3_13_BCM56560_A0fmt_fields, 16332 /* bits */ 49, 16333 /* flags */ 0, 16334 }, 16335 #endif /* chips */ 16336 16337 #if defined(BCM_56670_B0) 16338 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_13_BCM56670_B0fmt */ 16339 /* format IFP_SINGLE_WIDE_F3_13fmt */ 16340 /* nFields */ 8, 16341 /* *fields */ soc_IFP_SINGLE_WIDE_F3_13_BCM56560_A0fmt_fields, 16342 /* bits */ 49, 16343 /* flags */ 0, 16344 }, 16345 #endif /* chips */ 16346 16347 #if defined(BCM_56850_A0) 16348 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_13_BCM56850_A0fmt */ 16349 /* format IFP_SINGLE_WIDE_F3_13fmt */ 16350 /* nFields */ 9, 16351 /* *fields */ soc_IFP_SINGLE_WIDE_F3_13_BCM56850_A0fmt_fields, 16352 /* bits */ 49, 16353 /* flags */ 0, 16354 }, 16355 #endif /* chips */ 16356 16357 #if defined(BCM_56860_A0) 16358 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_13_BCM56860_A0fmt */ 16359 /* format IFP_SINGLE_WIDE_F3_13fmt */ 16360 /* nFields */ 8, 16361 /* *fields */ soc_IFP_SINGLE_WIDE_F3_13_BCM56860_A0fmt_fields, 16362 /* bits */ 49, 16363 /* flags */ 0, 16364 }, 16365 #endif /* chips */ 16366 16367 #if defined(BCM_56560_A0) 16368 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_14_BCM56560_A0fmt */ 16369 /* format IFP_SINGLE_WIDE_F3_14fmt */ 16370 /* nFields */ 2, 16371 /* *fields */ soc_IFP_SINGLE_WIDE_F3_14_BCM56560_A0fmt_fields, 16372 /* bits */ 49, 16373 /* flags */ 0, 16374 }, 16375 #endif /* chips */ 16376 16377 #if defined(BCM_56560_B0) 16378 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_14_BCM56560_B0fmt */ 16379 /* format IFP_SINGLE_WIDE_F3_14fmt */ 16380 /* nFields */ 2, 16381 /* *fields */ soc_IFP_SINGLE_WIDE_F3_14_BCM56560_A0fmt_fields, 16382 /* bits */ 49, 16383 /* flags */ 0, 16384 }, 16385 #endif /* chips */ 16386 16387 #if defined(BCM_56670_A0) 16388 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_14_BCM56670_A0fmt */ 16389 /* format IFP_SINGLE_WIDE_F3_14fmt */ 16390 /* nFields */ 2, 16391 /* *fields */ soc_IFP_SINGLE_WIDE_F3_14_BCM56560_A0fmt_fields, 16392 /* bits */ 49, 16393 /* flags */ 0, 16394 }, 16395 #endif /* chips */ 16396 16397 #if defined(BCM_56670_B0) 16398 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_14_BCM56670_B0fmt */ 16399 /* format IFP_SINGLE_WIDE_F3_14fmt */ 16400 /* nFields */ 2, 16401 /* *fields */ soc_IFP_SINGLE_WIDE_F3_14_BCM56560_A0fmt_fields, 16402 /* bits */ 49, 16403 /* flags */ 0, 16404 }, 16405 #endif /* chips */ 16406 16407 #if defined(BCM_56560_A0) 16408 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_15_BCM56560_A0fmt */ 16409 /* format IFP_SINGLE_WIDE_F3_15fmt */ 16410 /* nFields */ 4, 16411 /* *fields */ soc_IFP_SINGLE_WIDE_F3_15_BCM56560_A0fmt_fields, 16412 /* bits */ 49, 16413 /* flags */ 0, 16414 }, 16415 #endif /* chips */ 16416 16417 #if defined(BCM_56560_B0) 16418 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_15_BCM56560_B0fmt */ 16419 /* format IFP_SINGLE_WIDE_F3_15fmt */ 16420 /* nFields */ 4, 16421 /* *fields */ soc_IFP_SINGLE_WIDE_F3_15_BCM56560_A0fmt_fields, 16422 /* bits */ 49, 16423 /* flags */ 0, 16424 }, 16425 #endif /* chips */ 16426 16427 #if defined(BCM_56670_A0) 16428 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_15_BCM56670_A0fmt */ 16429 /* format IFP_SINGLE_WIDE_F3_15fmt */ 16430 /* nFields */ 4, 16431 /* *fields */ soc_IFP_SINGLE_WIDE_F3_15_BCM56560_A0fmt_fields, 16432 /* bits */ 49, 16433 /* flags */ 0, 16434 }, 16435 #endif /* chips */ 16436 16437 #if defined(BCM_56670_B0) 16438 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_15_BCM56670_B0fmt */ 16439 /* format IFP_SINGLE_WIDE_F3_15fmt */ 16440 /* nFields */ 4, 16441 /* *fields */ soc_IFP_SINGLE_WIDE_F3_15_BCM56560_A0fmt_fields, 16442 /* bits */ 49, 16443 /* flags */ 0, 16444 }, 16445 #endif /* chips */ 16446 16447 #if defined(BCM_56560_A0) 16448 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_16_BCM56560_A0fmt */ 16449 /* format IFP_SINGLE_WIDE_F3_16fmt */ 16450 /* nFields */ 12, 16451 /* *fields */ soc_IFP_SINGLE_WIDE_F3_16fmt_fields, 16452 /* bits */ 49, 16453 /* flags */ 0, 16454 }, 16455 #endif /* chips */ 16456 16457 #if defined(BCM_56560_B0) 16458 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_16_BCM56560_B0fmt */ 16459 /* format IFP_SINGLE_WIDE_F3_16fmt */ 16460 /* nFields */ 12, 16461 /* *fields */ soc_IFP_SINGLE_WIDE_F3_16fmt_fields, 16462 /* bits */ 49, 16463 /* flags */ 0, 16464 }, 16465 #endif /* chips */ 16466 16467 #if defined(BCM_56670_A0) 16468 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_16_BCM56670_A0fmt */ 16469 /* format IFP_SINGLE_WIDE_F3_16fmt */ 16470 /* nFields */ 12, 16471 /* *fields */ soc_IFP_SINGLE_WIDE_F3_16fmt_fields, 16472 /* bits */ 49, 16473 /* flags */ 0, 16474 }, 16475 #endif /* chips */ 16476 16477 #if defined(BCM_56670_B0) 16478 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_16_BCM56670_B0fmt */ 16479 /* format IFP_SINGLE_WIDE_F3_16fmt */ 16480 /* nFields */ 12, 16481 /* *fields */ soc_IFP_SINGLE_WIDE_F3_16fmt_fields, 16482 /* bits */ 49, 16483 /* flags */ 0, 16484 }, 16485 #endif /* chips */ 16486 16487 #if defined(BCM_56860_A0) 16488 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_16_BCM56860_A0fmt */ 16489 /* format IFP_SINGLE_WIDE_F3_16fmt */ 16490 /* nFields */ 12, 16491 /* *fields */ soc_IFP_SINGLE_WIDE_F1_16fmt_fields, 16492 /* bits */ 49, 16493 /* flags */ 0, 16494 }, 16495 #endif /* chips */ 16496 16497 #if defined(BCM_53400_A0) 16498 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_1_BCM53400_A0fmt */ 16499 /* format IFP_SINGLE_WIDE_F3_1fmt */ 16500 /* nFields */ 4, 16501 /* *fields */ soc_IFP_SINGLE_WIDE_F3_1_BCM53400_A0fmt_fields, 16502 /* bits */ 37, 16503 /* flags */ 0, 16504 }, 16505 #endif /* chips */ 16506 16507 #if defined(BCM_53540_A0) 16508 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_1_BCM53540_A0fmt */ 16509 /* format IFP_SINGLE_WIDE_F3_1fmt */ 16510 /* nFields */ 4, 16511 /* *fields */ soc_IFP_SINGLE_WIDE_F3_1_BCM53400_A0fmt_fields, 16512 /* bits */ 37, 16513 /* flags */ 0, 16514 }, 16515 #endif /* chips */ 16516 16517 #if defined(BCM_53570_A0) 16518 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_1_BCM53570_A0fmt */ 16519 /* format IFP_SINGLE_WIDE_F3_1fmt */ 16520 /* nFields */ 4, 16521 /* *fields */ soc_IFP_SINGLE_WIDE_F3_1_BCM53570_A0fmt_fields, 16522 /* bits */ 39, 16523 /* flags */ 0, 16524 }, 16525 #endif /* chips */ 16526 16527 #if defined(BCM_53570_B0) 16528 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_1_BCM53570_B0fmt */ 16529 /* format IFP_SINGLE_WIDE_F3_1fmt */ 16530 /* nFields */ 4, 16531 /* *fields */ soc_IFP_SINGLE_WIDE_F3_1_BCM53570_A0fmt_fields, 16532 /* bits */ 39, 16533 /* flags */ 0, 16534 }, 16535 #endif /* chips */ 16536 16537 #if defined(BCM_56142_A0) 16538 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_1_BCM56142_A0fmt */ 16539 /* format IFP_SINGLE_WIDE_F3_1fmt */ 16540 /* nFields */ 4, 16541 /* *fields */ soc_IFP_SINGLE_WIDE_F3_1_BCM56634_A0fmt_fields, 16542 /* bits */ 37, 16543 /* flags */ 0, 16544 }, 16545 #endif /* chips */ 16546 16547 #if defined(BCM_56150_A0) 16548 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_1_BCM56150_A0fmt */ 16549 /* format IFP_SINGLE_WIDE_F3_1fmt */ 16550 /* nFields */ 4, 16551 /* *fields */ soc_IFP_SINGLE_WIDE_F3_1_BCM56150_A0fmt_fields, 16552 /* bits */ 37, 16553 /* flags */ 0, 16554 }, 16555 #endif /* chips */ 16556 16557 #if defined(BCM_56160_A0) 16558 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_1_BCM56160_A0fmt */ 16559 /* format IFP_SINGLE_WIDE_F3_1fmt */ 16560 /* nFields */ 4, 16561 /* *fields */ soc_IFP_SINGLE_WIDE_F3_1_BCM53400_A0fmt_fields, 16562 /* bits */ 37, 16563 /* flags */ 0, 16564 }, 16565 #endif /* chips */ 16566 16567 #if defined(BCM_56260_A0) 16568 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_1_BCM56260_A0fmt */ 16569 /* format IFP_SINGLE_WIDE_F3_1fmt */ 16570 /* nFields */ 4, 16571 /* *fields */ soc_IFP_SINGLE_WIDE_F3_1_BCM56260_A0fmt_fields, 16572 /* bits */ 40, 16573 /* flags */ 0, 16574 }, 16575 #endif /* chips */ 16576 16577 #if defined(BCM_56260_B0) 16578 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_1_BCM56260_B0fmt */ 16579 /* format IFP_SINGLE_WIDE_F3_1fmt */ 16580 /* nFields */ 4, 16581 /* *fields */ soc_IFP_SINGLE_WIDE_F3_1_BCM56260_A0fmt_fields, 16582 /* bits */ 40, 16583 /* flags */ 0, 16584 }, 16585 #endif /* chips */ 16586 16587 #if defined(BCM_56270_A0) 16588 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_1_BCM56270_A0fmt */ 16589 /* format IFP_SINGLE_WIDE_F3_1fmt */ 16590 /* nFields */ 4, 16591 /* *fields */ soc_IFP_SINGLE_WIDE_F3_1_BCM56260_A0fmt_fields, 16592 /* bits */ 40, 16593 /* flags */ 0, 16594 }, 16595 #endif /* chips */ 16596 16597 #if defined(BCM_56334_A0) 16598 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_1_BCM56334_A0fmt */ 16599 /* format IFP_SINGLE_WIDE_F3_1fmt */ 16600 /* nFields */ 4, 16601 /* *fields */ soc_IFP_SINGLE_WIDE_F3_1_BCM56634_A0fmt_fields, 16602 /* bits */ 37, 16603 /* flags */ 0, 16604 }, 16605 #endif /* chips */ 16606 16607 #if defined(BCM_56334_B0) 16608 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_1_BCM56334_B0fmt */ 16609 /* format IFP_SINGLE_WIDE_F3_1fmt */ 16610 /* nFields */ 4, 16611 /* *fields */ soc_IFP_SINGLE_WIDE_F3_1_BCM56634_A0fmt_fields, 16612 /* bits */ 37, 16613 /* flags */ 0, 16614 }, 16615 #endif /* chips */ 16616 16617 #if defined(BCM_56340_A0) 16618 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_1_BCM56340_A0fmt */ 16619 /* format IFP_SINGLE_WIDE_F3_1fmt */ 16620 /* nFields */ 5, 16621 /* *fields */ soc_IFP_SINGLE_WIDE_F3_1_BCM56640_A0fmt_fields, 16622 /* bits */ 49, 16623 /* flags */ 0, 16624 }, 16625 #endif /* chips */ 16626 16627 #if defined(BCM_56440_A0) 16628 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_1_BCM56440_A0fmt */ 16629 /* format IFP_SINGLE_WIDE_F3_1fmt */ 16630 /* nFields */ 4, 16631 /* *fields */ soc_IFP_SINGLE_WIDE_F3_1_BCM56840_A0fmt_fields, 16632 /* bits */ 39, 16633 /* flags */ 0, 16634 }, 16635 #endif /* chips */ 16636 16637 #if defined(BCM_56440_B0) 16638 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_1_BCM56440_B0fmt */ 16639 /* format IFP_SINGLE_WIDE_F3_1fmt */ 16640 /* nFields */ 4, 16641 /* *fields */ soc_IFP_SINGLE_WIDE_F3_1_BCM56840_A0fmt_fields, 16642 /* bits */ 39, 16643 /* flags */ 0, 16644 }, 16645 #endif /* chips */ 16646 16647 #if defined(BCM_56450_A0) 16648 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_1_BCM56450_A0fmt */ 16649 /* format IFP_SINGLE_WIDE_F3_1fmt */ 16650 /* nFields */ 4, 16651 /* *fields */ soc_IFP_SINGLE_WIDE_F3_1_BCM56450_A0fmt_fields, 16652 /* bits */ 40, 16653 /* flags */ 0, 16654 }, 16655 #endif /* chips */ 16656 16657 #if defined(BCM_56450_B0) 16658 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_1_BCM56450_B0fmt */ 16659 /* format IFP_SINGLE_WIDE_F3_1fmt */ 16660 /* nFields */ 4, 16661 /* *fields */ soc_IFP_SINGLE_WIDE_F3_1_BCM56450_A0fmt_fields, 16662 /* bits */ 40, 16663 /* flags */ 0, 16664 }, 16665 #endif /* chips */ 16666 16667 #if defined(BCM_56450_B1) 16668 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_1_BCM56450_B1fmt */ 16669 /* format IFP_SINGLE_WIDE_F3_1fmt */ 16670 /* nFields */ 4, 16671 /* *fields */ soc_IFP_SINGLE_WIDE_F3_1_BCM56450_A0fmt_fields, 16672 /* bits */ 40, 16673 /* flags */ 0, 16674 }, 16675 #endif /* chips */ 16676 16677 #if defined(BCM_56524_A0) 16678 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_1_BCM56524_A0fmt */ 16679 /* format IFP_SINGLE_WIDE_F3_1fmt */ 16680 /* nFields */ 4, 16681 /* *fields */ soc_IFP_SINGLE_WIDE_F3_1_BCM56634_A0fmt_fields, 16682 /* bits */ 37, 16683 /* flags */ 0, 16684 }, 16685 #endif /* chips */ 16686 16687 #if defined(BCM_56524_B0) 16688 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_1_BCM56524_B0fmt */ 16689 /* format IFP_SINGLE_WIDE_F3_1fmt */ 16690 /* nFields */ 4, 16691 /* *fields */ soc_IFP_SINGLE_WIDE_F3_1_BCM56634_A0fmt_fields, 16692 /* bits */ 37, 16693 /* flags */ 0, 16694 }, 16695 #endif /* chips */ 16696 16697 #if defined(BCM_56560_A0) 16698 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_1_BCM56560_A0fmt */ 16699 /* format IFP_SINGLE_WIDE_F3_1fmt */ 16700 /* nFields */ 5, 16701 /* *fields */ soc_IFP_SINGLE_WIDE_F3_1_BCM56560_A0fmt_fields, 16702 /* bits */ 49, 16703 /* flags */ 0, 16704 }, 16705 #endif /* chips */ 16706 16707 #if defined(BCM_56560_B0) 16708 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_1_BCM56560_B0fmt */ 16709 /* format IFP_SINGLE_WIDE_F3_1fmt */ 16710 /* nFields */ 5, 16711 /* *fields */ soc_IFP_SINGLE_WIDE_F3_1_BCM56560_A0fmt_fields, 16712 /* bits */ 49, 16713 /* flags */ 0, 16714 }, 16715 #endif /* chips */ 16716 16717 #if defined(BCM_56634_A0) 16718 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_1_BCM56634_A0fmt */ 16719 /* format IFP_SINGLE_WIDE_F3_1fmt */ 16720 /* nFields */ 4, 16721 /* *fields */ soc_IFP_SINGLE_WIDE_F3_1_BCM56634_A0fmt_fields, 16722 /* bits */ 37, 16723 /* flags */ 0, 16724 }, 16725 #endif /* chips */ 16726 16727 #if defined(BCM_56634_B0) 16728 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_1_BCM56634_B0fmt */ 16729 /* format IFP_SINGLE_WIDE_F3_1fmt */ 16730 /* nFields */ 4, 16731 /* *fields */ soc_IFP_SINGLE_WIDE_F3_1_BCM56634_A0fmt_fields, 16732 /* bits */ 37, 16733 /* flags */ 0, 16734 }, 16735 #endif /* chips */ 16736 16737 #if defined(BCM_56640_A0) 16738 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_1_BCM56640_A0fmt */ 16739 /* format IFP_SINGLE_WIDE_F3_1fmt */ 16740 /* nFields */ 5, 16741 /* *fields */ soc_IFP_SINGLE_WIDE_F3_1_BCM56640_A0fmt_fields, 16742 /* bits */ 49, 16743 /* flags */ 0, 16744 }, 16745 #endif /* chips */ 16746 16747 #if defined(BCM_56670_A0) 16748 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_1_BCM56670_A0fmt */ 16749 /* format IFP_SINGLE_WIDE_F3_1fmt */ 16750 /* nFields */ 5, 16751 /* *fields */ soc_IFP_SINGLE_WIDE_F3_1_BCM56560_A0fmt_fields, 16752 /* bits */ 49, 16753 /* flags */ 0, 16754 }, 16755 #endif /* chips */ 16756 16757 #if defined(BCM_56670_B0) 16758 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_1_BCM56670_B0fmt */ 16759 /* format IFP_SINGLE_WIDE_F3_1fmt */ 16760 /* nFields */ 5, 16761 /* *fields */ soc_IFP_SINGLE_WIDE_F3_1_BCM56560_A0fmt_fields, 16762 /* bits */ 49, 16763 /* flags */ 0, 16764 }, 16765 #endif /* chips */ 16766 16767 #if defined(BCM_56680_B0) 16768 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_1_BCM56680_B0fmt */ 16769 /* format IFP_SINGLE_WIDE_F3_1fmt */ 16770 /* nFields */ 3, 16771 /* *fields */ soc_IFP_SINGLE_WIDE_F3_1fmt_fields, 16772 /* bits */ 32, 16773 /* flags */ 0, 16774 }, 16775 #endif /* chips */ 16776 16777 #if defined(BCM_56685_A0) 16778 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_1_BCM56685_A0fmt */ 16779 /* format IFP_SINGLE_WIDE_F3_1fmt */ 16780 /* nFields */ 4, 16781 /* *fields */ soc_IFP_SINGLE_WIDE_F3_1_BCM56634_A0fmt_fields, 16782 /* bits */ 37, 16783 /* flags */ 0, 16784 }, 16785 #endif /* chips */ 16786 16787 #if defined(BCM_56685_B0) 16788 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_1_BCM56685_B0fmt */ 16789 /* format IFP_SINGLE_WIDE_F3_1fmt */ 16790 /* nFields */ 4, 16791 /* *fields */ soc_IFP_SINGLE_WIDE_F3_1_BCM56634_A0fmt_fields, 16792 /* bits */ 37, 16793 /* flags */ 0, 16794 }, 16795 #endif /* chips */ 16796 16797 #if defined(BCM_56725_A0) 16798 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_1_BCM56725_A0fmt */ 16799 /* format IFP_SINGLE_WIDE_F3_1fmt */ 16800 /* nFields */ 4, 16801 /* *fields */ soc_IFP_SINGLE_WIDE_F3_1_BCM56820_A0fmt_fields, 16802 /* bits */ 33, 16803 /* flags */ 0, 16804 }, 16805 #endif /* chips */ 16806 16807 #if defined(BCM_56820_A0) 16808 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_1_BCM56820_A0fmt */ 16809 /* format IFP_SINGLE_WIDE_F3_1fmt */ 16810 /* nFields */ 4, 16811 /* *fields */ soc_IFP_SINGLE_WIDE_F3_1_BCM56820_A0fmt_fields, 16812 /* bits */ 33, 16813 /* flags */ 0, 16814 }, 16815 #endif /* chips */ 16816 16817 #if defined(BCM_56840_A0) 16818 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_1_BCM56840_A0fmt */ 16819 /* format IFP_SINGLE_WIDE_F3_1fmt */ 16820 /* nFields */ 4, 16821 /* *fields */ soc_IFP_SINGLE_WIDE_F3_1_BCM56840_A0fmt_fields, 16822 /* bits */ 39, 16823 /* flags */ 0, 16824 }, 16825 #endif /* chips */ 16826 16827 #if defined(BCM_56840_B0) 16828 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_1_BCM56840_B0fmt */ 16829 /* format IFP_SINGLE_WIDE_F3_1fmt */ 16830 /* nFields */ 4, 16831 /* *fields */ soc_IFP_SINGLE_WIDE_F3_1_BCM56840_A0fmt_fields, 16832 /* bits */ 39, 16833 /* flags */ 0, 16834 }, 16835 #endif /* chips */ 16836 16837 #if defined(BCM_56850_A0) 16838 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_1_BCM56850_A0fmt */ 16839 /* format IFP_SINGLE_WIDE_F3_1fmt */ 16840 /* nFields */ 5, 16841 /* *fields */ soc_IFP_SINGLE_WIDE_F3_1_BCM56850_A0fmt_fields, 16842 /* bits */ 49, 16843 /* flags */ 0, 16844 }, 16845 #endif /* chips */ 16846 16847 #if defined(BCM_56860_A0) 16848 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_1_BCM56860_A0fmt */ 16849 /* format IFP_SINGLE_WIDE_F3_1fmt */ 16850 /* nFields */ 5, 16851 /* *fields */ soc_IFP_SINGLE_WIDE_F3_1_BCM56850_A0fmt_fields, 16852 /* bits */ 49, 16853 /* flags */ 0, 16854 }, 16855 #endif /* chips */ 16856 16857 #if defined(BCM_53400_A0) 16858 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_2_BCM53400_A0fmt */ 16859 /* format IFP_SINGLE_WIDE_F3_2fmt */ 16860 /* nFields */ 6, 16861 /* *fields */ soc_IFP_SINGLE_WIDE_F1_1_BCM53400_A0fmt_fields, 16862 /* bits */ 37, 16863 /* flags */ 0, 16864 }, 16865 #endif /* chips */ 16866 16867 #if defined(BCM_53540_A0) 16868 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_2_BCM53540_A0fmt */ 16869 /* format IFP_SINGLE_WIDE_F3_2fmt */ 16870 /* nFields */ 5, 16871 /* *fields */ soc_IFP_SINGLE_WIDE_F1_1_BCM56160_A0fmt_fields, 16872 /* bits */ 37, 16873 /* flags */ 0, 16874 }, 16875 #endif /* chips */ 16876 16877 #if defined(BCM_53570_A0) 16878 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_2_BCM53570_A0fmt */ 16879 /* format IFP_SINGLE_WIDE_F3_2fmt */ 16880 /* nFields */ 5, 16881 /* *fields */ soc_IFP_SINGLE_WIDE_F1_1_BCM53570_A0fmt_fields, 16882 /* bits */ 39, 16883 /* flags */ 0, 16884 }, 16885 #endif /* chips */ 16886 16887 #if defined(BCM_53570_B0) 16888 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_2_BCM53570_B0fmt */ 16889 /* format IFP_SINGLE_WIDE_F3_2fmt */ 16890 /* nFields */ 5, 16891 /* *fields */ soc_IFP_SINGLE_WIDE_F1_1_BCM53570_A0fmt_fields, 16892 /* bits */ 39, 16893 /* flags */ 0, 16894 }, 16895 #endif /* chips */ 16896 16897 #if defined(BCM_56142_A0) 16898 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_2_BCM56142_A0fmt */ 16899 /* format IFP_SINGLE_WIDE_F3_2fmt */ 16900 /* nFields */ 6, 16901 /* *fields */ soc_IFP_SINGLE_WIDE_F1_1_BCM56634_A0fmt_fields, 16902 /* bits */ 37, 16903 /* flags */ 0, 16904 }, 16905 #endif /* chips */ 16906 16907 #if defined(BCM_56150_A0) 16908 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_2_BCM56150_A0fmt */ 16909 /* format IFP_SINGLE_WIDE_F3_2fmt */ 16910 /* nFields */ 6, 16911 /* *fields */ soc_IFP_SINGLE_WIDE_F1_1_BCM56150_A0fmt_fields, 16912 /* bits */ 37, 16913 /* flags */ 0, 16914 }, 16915 #endif /* chips */ 16916 16917 #if defined(BCM_56160_A0) 16918 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_2_BCM56160_A0fmt */ 16919 /* format IFP_SINGLE_WIDE_F3_2fmt */ 16920 /* nFields */ 5, 16921 /* *fields */ soc_IFP_SINGLE_WIDE_F1_1_BCM56160_A0fmt_fields, 16922 /* bits */ 37, 16923 /* flags */ 0, 16924 }, 16925 #endif /* chips */ 16926 16927 #if defined(BCM_56260_A0) 16928 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_2_BCM56260_A0fmt */ 16929 /* format IFP_SINGLE_WIDE_F3_2fmt */ 16930 /* nFields */ 6, 16931 /* *fields */ soc_IFP_SINGLE_WIDE_F1_1_BCM56260_A0fmt_fields, 16932 /* bits */ 40, 16933 /* flags */ 0, 16934 }, 16935 #endif /* chips */ 16936 16937 #if defined(BCM_56260_B0) 16938 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_2_BCM56260_B0fmt */ 16939 /* format IFP_SINGLE_WIDE_F3_2fmt */ 16940 /* nFields */ 6, 16941 /* *fields */ soc_IFP_SINGLE_WIDE_F1_1_BCM56260_A0fmt_fields, 16942 /* bits */ 40, 16943 /* flags */ 0, 16944 }, 16945 #endif /* chips */ 16946 16947 #if defined(BCM_56270_A0) 16948 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_2_BCM56270_A0fmt */ 16949 /* format IFP_SINGLE_WIDE_F3_2fmt */ 16950 /* nFields */ 6, 16951 /* *fields */ soc_IFP_SINGLE_WIDE_F1_1_BCM56260_A0fmt_fields, 16952 /* bits */ 40, 16953 /* flags */ 0, 16954 }, 16955 #endif /* chips */ 16956 16957 #if defined(BCM_56334_A0) 16958 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_2_BCM56334_A0fmt */ 16959 /* format IFP_SINGLE_WIDE_F3_2fmt */ 16960 /* nFields */ 6, 16961 /* *fields */ soc_IFP_SINGLE_WIDE_F1_1_BCM56634_A0fmt_fields, 16962 /* bits */ 37, 16963 /* flags */ 0, 16964 }, 16965 #endif /* chips */ 16966 16967 #if defined(BCM_56334_B0) 16968 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_2_BCM56334_B0fmt */ 16969 /* format IFP_SINGLE_WIDE_F3_2fmt */ 16970 /* nFields */ 6, 16971 /* *fields */ soc_IFP_SINGLE_WIDE_F1_1_BCM56634_A0fmt_fields, 16972 /* bits */ 37, 16973 /* flags */ 0, 16974 }, 16975 #endif /* chips */ 16976 16977 #if defined(BCM_56340_A0) 16978 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_2_BCM56340_A0fmt */ 16979 /* format IFP_SINGLE_WIDE_F3_2fmt */ 16980 /* nFields */ 6, 16981 /* *fields */ soc_IFP_SINGLE_WIDE_F1_1_BCM56640_A0fmt_fields, 16982 /* bits */ 49, 16983 /* flags */ 0, 16984 }, 16985 #endif /* chips */ 16986 16987 #if defined(BCM_56440_A0) 16988 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_2_BCM56440_A0fmt */ 16989 /* format IFP_SINGLE_WIDE_F3_2fmt */ 16990 /* nFields */ 5, 16991 /* *fields */ soc_IFP_SINGLE_WIDE_F1_1_BCM56840_A0fmt_fields, 16992 /* bits */ 39, 16993 /* flags */ 0, 16994 }, 16995 #endif /* chips */ 16996 16997 #if defined(BCM_56440_B0) 16998 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_2_BCM56440_B0fmt */ 16999 /* format IFP_SINGLE_WIDE_F3_2fmt */ 17000 /* nFields */ 5, 17001 /* *fields */ soc_IFP_SINGLE_WIDE_F1_1_BCM56840_A0fmt_fields, 17002 /* bits */ 39, 17003 /* flags */ 0, 17004 }, 17005 #endif /* chips */ 17006 17007 #if defined(BCM_56450_A0) 17008 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_2_BCM56450_A0fmt */ 17009 /* format IFP_SINGLE_WIDE_F3_2fmt */ 17010 /* nFields */ 6, 17011 /* *fields */ soc_IFP_SINGLE_WIDE_F1_1_BCM56450_A0fmt_fields, 17012 /* bits */ 40, 17013 /* flags */ 0, 17014 }, 17015 #endif /* chips */ 17016 17017 #if defined(BCM_56450_B0) 17018 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_2_BCM56450_B0fmt */ 17019 /* format IFP_SINGLE_WIDE_F3_2fmt */ 17020 /* nFields */ 6, 17021 /* *fields */ soc_IFP_SINGLE_WIDE_F1_1_BCM56450_A0fmt_fields, 17022 /* bits */ 40, 17023 /* flags */ 0, 17024 }, 17025 #endif /* chips */ 17026 17027 #if defined(BCM_56450_B1) 17028 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_2_BCM56450_B1fmt */ 17029 /* format IFP_SINGLE_WIDE_F3_2fmt */ 17030 /* nFields */ 6, 17031 /* *fields */ soc_IFP_SINGLE_WIDE_F1_1_BCM56450_A0fmt_fields, 17032 /* bits */ 40, 17033 /* flags */ 0, 17034 }, 17035 #endif /* chips */ 17036 17037 #if defined(BCM_56524_A0) 17038 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_2_BCM56524_A0fmt */ 17039 /* format IFP_SINGLE_WIDE_F3_2fmt */ 17040 /* nFields */ 6, 17041 /* *fields */ soc_IFP_SINGLE_WIDE_F1_1_BCM56634_A0fmt_fields, 17042 /* bits */ 37, 17043 /* flags */ 0, 17044 }, 17045 #endif /* chips */ 17046 17047 #if defined(BCM_56524_B0) 17048 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_2_BCM56524_B0fmt */ 17049 /* format IFP_SINGLE_WIDE_F3_2fmt */ 17050 /* nFields */ 6, 17051 /* *fields */ soc_IFP_SINGLE_WIDE_F1_1_BCM56634_A0fmt_fields, 17052 /* bits */ 37, 17053 /* flags */ 0, 17054 }, 17055 #endif /* chips */ 17056 17057 #if defined(BCM_56560_A0) 17058 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_2_BCM56560_A0fmt */ 17059 /* format IFP_SINGLE_WIDE_F3_2fmt */ 17060 /* nFields */ 5, 17061 /* *fields */ soc_IFP_SINGLE_WIDE_F3_2_BCM56560_A0fmt_fields, 17062 /* bits */ 49, 17063 /* flags */ 0, 17064 }, 17065 #endif /* chips */ 17066 17067 #if defined(BCM_56560_B0) 17068 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_2_BCM56560_B0fmt */ 17069 /* format IFP_SINGLE_WIDE_F3_2fmt */ 17070 /* nFields */ 5, 17071 /* *fields */ soc_IFP_SINGLE_WIDE_F3_2_BCM56560_A0fmt_fields, 17072 /* bits */ 49, 17073 /* flags */ 0, 17074 }, 17075 #endif /* chips */ 17076 17077 #if defined(BCM_56634_A0) 17078 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_2_BCM56634_A0fmt */ 17079 /* format IFP_SINGLE_WIDE_F3_2fmt */ 17080 /* nFields */ 6, 17081 /* *fields */ soc_IFP_SINGLE_WIDE_F1_1_BCM56634_A0fmt_fields, 17082 /* bits */ 37, 17083 /* flags */ 0, 17084 }, 17085 #endif /* chips */ 17086 17087 #if defined(BCM_56634_B0) 17088 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_2_BCM56634_B0fmt */ 17089 /* format IFP_SINGLE_WIDE_F3_2fmt */ 17090 /* nFields */ 6, 17091 /* *fields */ soc_IFP_SINGLE_WIDE_F1_1_BCM56634_A0fmt_fields, 17092 /* bits */ 37, 17093 /* flags */ 0, 17094 }, 17095 #endif /* chips */ 17096 17097 #if defined(BCM_56640_A0) 17098 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_2_BCM56640_A0fmt */ 17099 /* format IFP_SINGLE_WIDE_F3_2fmt */ 17100 /* nFields */ 6, 17101 /* *fields */ soc_IFP_SINGLE_WIDE_F1_1_BCM56640_A0fmt_fields, 17102 /* bits */ 49, 17103 /* flags */ 0, 17104 }, 17105 #endif /* chips */ 17106 17107 #if defined(BCM_56670_A0) 17108 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_2_BCM56670_A0fmt */ 17109 /* format IFP_SINGLE_WIDE_F3_2fmt */ 17110 /* nFields */ 5, 17111 /* *fields */ soc_IFP_SINGLE_WIDE_F3_2_BCM56560_A0fmt_fields, 17112 /* bits */ 49, 17113 /* flags */ 0, 17114 }, 17115 #endif /* chips */ 17116 17117 #if defined(BCM_56670_B0) 17118 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_2_BCM56670_B0fmt */ 17119 /* format IFP_SINGLE_WIDE_F3_2fmt */ 17120 /* nFields */ 5, 17121 /* *fields */ soc_IFP_SINGLE_WIDE_F3_2_BCM56560_A0fmt_fields, 17122 /* bits */ 49, 17123 /* flags */ 0, 17124 }, 17125 #endif /* chips */ 17126 17127 #if defined(BCM_56685_A0) 17128 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_2_BCM56685_A0fmt */ 17129 /* format IFP_SINGLE_WIDE_F3_2fmt */ 17130 /* nFields */ 6, 17131 /* *fields */ soc_IFP_SINGLE_WIDE_F1_1_BCM56634_A0fmt_fields, 17132 /* bits */ 37, 17133 /* flags */ 0, 17134 }, 17135 #endif /* chips */ 17136 17137 #if defined(BCM_56685_B0) 17138 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_2_BCM56685_B0fmt */ 17139 /* format IFP_SINGLE_WIDE_F3_2fmt */ 17140 /* nFields */ 6, 17141 /* *fields */ soc_IFP_SINGLE_WIDE_F1_1_BCM56634_A0fmt_fields, 17142 /* bits */ 37, 17143 /* flags */ 0, 17144 }, 17145 #endif /* chips */ 17146 17147 #if defined(BCM_56725_A0) 17148 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_2_BCM56725_A0fmt */ 17149 /* format IFP_SINGLE_WIDE_F3_2fmt */ 17150 /* nFields */ 7, 17151 /* *fields */ soc_IFP_SINGLE_WIDE_F3_2_BCM56820_A0fmt_fields, 17152 /* bits */ 33, 17153 /* flags */ 0, 17154 }, 17155 #endif /* chips */ 17156 17157 #if defined(BCM_56820_A0) 17158 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_2_BCM56820_A0fmt */ 17159 /* format IFP_SINGLE_WIDE_F3_2fmt */ 17160 /* nFields */ 7, 17161 /* *fields */ soc_IFP_SINGLE_WIDE_F3_2_BCM56820_A0fmt_fields, 17162 /* bits */ 33, 17163 /* flags */ 0, 17164 }, 17165 #endif /* chips */ 17166 17167 #if defined(BCM_56840_A0) 17168 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_2_BCM56840_A0fmt */ 17169 /* format IFP_SINGLE_WIDE_F3_2fmt */ 17170 /* nFields */ 5, 17171 /* *fields */ soc_IFP_SINGLE_WIDE_F1_1_BCM56840_A0fmt_fields, 17172 /* bits */ 39, 17173 /* flags */ 0, 17174 }, 17175 #endif /* chips */ 17176 17177 #if defined(BCM_56840_B0) 17178 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_2_BCM56840_B0fmt */ 17179 /* format IFP_SINGLE_WIDE_F3_2fmt */ 17180 /* nFields */ 5, 17181 /* *fields */ soc_IFP_SINGLE_WIDE_F1_1_BCM56840_A0fmt_fields, 17182 /* bits */ 39, 17183 /* flags */ 0, 17184 }, 17185 #endif /* chips */ 17186 17187 #if defined(BCM_56850_A0) 17188 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_2_BCM56850_A0fmt */ 17189 /* format IFP_SINGLE_WIDE_F3_2fmt */ 17190 /* nFields */ 5, 17191 /* *fields */ soc_IFP_SINGLE_WIDE_F1_1_BCM56850_A0fmt_fields, 17192 /* bits */ 49, 17193 /* flags */ 0, 17194 }, 17195 #endif /* chips */ 17196 17197 #if defined(BCM_56860_A0) 17198 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_2_BCM56860_A0fmt */ 17199 /* format IFP_SINGLE_WIDE_F3_2fmt */ 17200 /* nFields */ 5, 17201 /* *fields */ soc_IFP_SINGLE_WIDE_F1_1_BCM56850_A0fmt_fields, 17202 /* bits */ 49, 17203 /* flags */ 0, 17204 }, 17205 #endif /* chips */ 17206 17207 #if defined(BCM_88732_A0) 17208 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_2_BCM88732_A0fmt */ 17209 /* format IFP_SINGLE_WIDE_F3_2fmt */ 17210 /* nFields */ 7, 17211 /* *fields */ soc_IFP_SINGLE_WIDE_F3_2_BCM56820_A0fmt_fields, 17212 /* bits */ 33, 17213 /* flags */ 0, 17214 }, 17215 #endif /* chips */ 17216 17217 #if defined(BCM_53400_A0) 17218 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_3_BCM53400_A0fmt */ 17219 /* format IFP_SINGLE_WIDE_F3_3fmt */ 17220 /* nFields */ 7, 17221 /* *fields */ soc_IFP_SINGLE_WIDE_F1_6_BCM53400_A0fmt_fields, 17222 /* bits */ 37, 17223 /* flags */ 0, 17224 }, 17225 #endif /* chips */ 17226 17227 #if defined(BCM_53540_A0) 17228 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_3_BCM53540_A0fmt */ 17229 /* format IFP_SINGLE_WIDE_F3_3fmt */ 17230 /* nFields */ 7, 17231 /* *fields */ soc_IFP_SINGLE_WIDE_F1_6_BCM53400_A0fmt_fields, 17232 /* bits */ 37, 17233 /* flags */ 0, 17234 }, 17235 #endif /* chips */ 17236 17237 #if defined(BCM_53570_A0) 17238 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_3_BCM53570_A0fmt */ 17239 /* format IFP_SINGLE_WIDE_F3_3fmt */ 17240 /* nFields */ 7, 17241 /* *fields */ soc_IFP_SINGLE_WIDE_F1_6_BCM53570_A0fmt_fields, 17242 /* bits */ 39, 17243 /* flags */ 0, 17244 }, 17245 #endif /* chips */ 17246 17247 #if defined(BCM_53570_B0) 17248 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_3_BCM53570_B0fmt */ 17249 /* format IFP_SINGLE_WIDE_F3_3fmt */ 17250 /* nFields */ 7, 17251 /* *fields */ soc_IFP_SINGLE_WIDE_F1_6_BCM53570_A0fmt_fields, 17252 /* bits */ 39, 17253 /* flags */ 0, 17254 }, 17255 #endif /* chips */ 17256 17257 #if defined(BCM_56142_A0) 17258 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_3_BCM56142_A0fmt */ 17259 /* format IFP_SINGLE_WIDE_F3_3fmt */ 17260 /* nFields */ 7, 17261 /* *fields */ soc_IFP_SINGLE_WIDE_F1_6_BCM56634_A0fmt_fields, 17262 /* bits */ 37, 17263 /* flags */ 0, 17264 }, 17265 #endif /* chips */ 17266 17267 #if defined(BCM_56150_A0) 17268 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_3_BCM56150_A0fmt */ 17269 /* format IFP_SINGLE_WIDE_F3_3fmt */ 17270 /* nFields */ 7, 17271 /* *fields */ soc_IFP_SINGLE_WIDE_F1_6_BCM56150_A0fmt_fields, 17272 /* bits */ 37, 17273 /* flags */ 0, 17274 }, 17275 #endif /* chips */ 17276 17277 #if defined(BCM_56160_A0) 17278 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_3_BCM56160_A0fmt */ 17279 /* format IFP_SINGLE_WIDE_F3_3fmt */ 17280 /* nFields */ 7, 17281 /* *fields */ soc_IFP_SINGLE_WIDE_F1_6_BCM53400_A0fmt_fields, 17282 /* bits */ 37, 17283 /* flags */ 0, 17284 }, 17285 #endif /* chips */ 17286 17287 #if defined(BCM_56260_A0) 17288 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_3_BCM56260_A0fmt */ 17289 /* format IFP_SINGLE_WIDE_F3_3fmt */ 17290 /* nFields */ 7, 17291 /* *fields */ soc_IFP_SINGLE_WIDE_F1_6_BCM56260_A0fmt_fields, 17292 /* bits */ 40, 17293 /* flags */ 0, 17294 }, 17295 #endif /* chips */ 17296 17297 #if defined(BCM_56260_B0) 17298 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_3_BCM56260_B0fmt */ 17299 /* format IFP_SINGLE_WIDE_F3_3fmt */ 17300 /* nFields */ 7, 17301 /* *fields */ soc_IFP_SINGLE_WIDE_F1_6_BCM56260_A0fmt_fields, 17302 /* bits */ 40, 17303 /* flags */ 0, 17304 }, 17305 #endif /* chips */ 17306 17307 #if defined(BCM_56270_A0) 17308 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_3_BCM56270_A0fmt */ 17309 /* format IFP_SINGLE_WIDE_F3_3fmt */ 17310 /* nFields */ 7, 17311 /* *fields */ soc_IFP_SINGLE_WIDE_F1_6_BCM56260_A0fmt_fields, 17312 /* bits */ 40, 17313 /* flags */ 0, 17314 }, 17315 #endif /* chips */ 17316 17317 #if defined(BCM_56334_A0) 17318 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_3_BCM56334_A0fmt */ 17319 /* format IFP_SINGLE_WIDE_F3_3fmt */ 17320 /* nFields */ 7, 17321 /* *fields */ soc_IFP_SINGLE_WIDE_F1_6_BCM56634_A0fmt_fields, 17322 /* bits */ 37, 17323 /* flags */ 0, 17324 }, 17325 #endif /* chips */ 17326 17327 #if defined(BCM_56334_B0) 17328 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_3_BCM56334_B0fmt */ 17329 /* format IFP_SINGLE_WIDE_F3_3fmt */ 17330 /* nFields */ 7, 17331 /* *fields */ soc_IFP_SINGLE_WIDE_F1_6_BCM56634_A0fmt_fields, 17332 /* bits */ 37, 17333 /* flags */ 0, 17334 }, 17335 #endif /* chips */ 17336 17337 #if defined(BCM_56340_A0) 17338 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_3_BCM56340_A0fmt */ 17339 /* format IFP_SINGLE_WIDE_F3_3fmt */ 17340 /* nFields */ 9, 17341 /* *fields */ soc_IFP_SINGLE_WIDE_F1_6_BCM56640_A0fmt_fields, 17342 /* bits */ 49, 17343 /* flags */ 0, 17344 }, 17345 #endif /* chips */ 17346 17347 #if defined(BCM_56440_A0) 17348 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_3_BCM56440_A0fmt */ 17349 /* format IFP_SINGLE_WIDE_F3_3fmt */ 17350 /* nFields */ 7, 17351 /* *fields */ soc_IFP_SINGLE_WIDE_F1_6_BCM56440_A0fmt_fields, 17352 /* bits */ 39, 17353 /* flags */ 0, 17354 }, 17355 #endif /* chips */ 17356 17357 #if defined(BCM_56440_B0) 17358 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_3_BCM56440_B0fmt */ 17359 /* format IFP_SINGLE_WIDE_F3_3fmt */ 17360 /* nFields */ 7, 17361 /* *fields */ soc_IFP_SINGLE_WIDE_F1_6_BCM56440_A0fmt_fields, 17362 /* bits */ 39, 17363 /* flags */ 0, 17364 }, 17365 #endif /* chips */ 17366 17367 #if defined(BCM_56450_A0) 17368 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_3_BCM56450_A0fmt */ 17369 /* format IFP_SINGLE_WIDE_F3_3fmt */ 17370 /* nFields */ 7, 17371 /* *fields */ soc_IFP_SINGLE_WIDE_F1_6_BCM56450_A0fmt_fields, 17372 /* bits */ 40, 17373 /* flags */ 0, 17374 }, 17375 #endif /* chips */ 17376 17377 #if defined(BCM_56450_B0) 17378 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_3_BCM56450_B0fmt */ 17379 /* format IFP_SINGLE_WIDE_F3_3fmt */ 17380 /* nFields */ 7, 17381 /* *fields */ soc_IFP_SINGLE_WIDE_F1_6_BCM56450_A0fmt_fields, 17382 /* bits */ 40, 17383 /* flags */ 0, 17384 }, 17385 #endif /* chips */ 17386 17387 #if defined(BCM_56450_B1) 17388 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_3_BCM56450_B1fmt */ 17389 /* format IFP_SINGLE_WIDE_F3_3fmt */ 17390 /* nFields */ 7, 17391 /* *fields */ soc_IFP_SINGLE_WIDE_F1_6_BCM56450_A0fmt_fields, 17392 /* bits */ 40, 17393 /* flags */ 0, 17394 }, 17395 #endif /* chips */ 17396 17397 #if defined(BCM_56524_A0) 17398 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_3_BCM56524_A0fmt */ 17399 /* format IFP_SINGLE_WIDE_F3_3fmt */ 17400 /* nFields */ 7, 17401 /* *fields */ soc_IFP_SINGLE_WIDE_F1_6_BCM56634_A0fmt_fields, 17402 /* bits */ 37, 17403 /* flags */ 0, 17404 }, 17405 #endif /* chips */ 17406 17407 #if defined(BCM_56524_B0) 17408 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_3_BCM56524_B0fmt */ 17409 /* format IFP_SINGLE_WIDE_F3_3fmt */ 17410 /* nFields */ 7, 17411 /* *fields */ soc_IFP_SINGLE_WIDE_F1_6_BCM56634_A0fmt_fields, 17412 /* bits */ 37, 17413 /* flags */ 0, 17414 }, 17415 #endif /* chips */ 17416 17417 #if defined(BCM_56560_A0) 17418 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_3_BCM56560_A0fmt */ 17419 /* format IFP_SINGLE_WIDE_F3_3fmt */ 17420 /* nFields */ 7, 17421 /* *fields */ soc_IFP_SINGLE_WIDE_F3_3_BCM56560_A0fmt_fields, 17422 /* bits */ 49, 17423 /* flags */ 0, 17424 }, 17425 #endif /* chips */ 17426 17427 #if defined(BCM_56560_B0) 17428 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_3_BCM56560_B0fmt */ 17429 /* format IFP_SINGLE_WIDE_F3_3fmt */ 17430 /* nFields */ 7, 17431 /* *fields */ soc_IFP_SINGLE_WIDE_F3_3_BCM56560_A0fmt_fields, 17432 /* bits */ 49, 17433 /* flags */ 0, 17434 }, 17435 #endif /* chips */ 17436 17437 #if defined(BCM_56624_B0) 17438 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_3_BCM56624_B0fmt */ 17439 /* format IFP_SINGLE_WIDE_F3_3fmt */ 17440 /* nFields */ 6, 17441 /* *fields */ soc_IFP_SINGLE_WIDE_F3_3fmt_fields, 17442 /* bits */ 32, 17443 /* flags */ 0, 17444 }, 17445 #endif /* chips */ 17446 17447 #if defined(BCM_56634_A0) 17448 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_3_BCM56634_A0fmt */ 17449 /* format IFP_SINGLE_WIDE_F3_3fmt */ 17450 /* nFields */ 7, 17451 /* *fields */ soc_IFP_SINGLE_WIDE_F1_6_BCM56634_A0fmt_fields, 17452 /* bits */ 37, 17453 /* flags */ 0, 17454 }, 17455 #endif /* chips */ 17456 17457 #if defined(BCM_56634_B0) 17458 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_3_BCM56634_B0fmt */ 17459 /* format IFP_SINGLE_WIDE_F3_3fmt */ 17460 /* nFields */ 7, 17461 /* *fields */ soc_IFP_SINGLE_WIDE_F1_6_BCM56634_A0fmt_fields, 17462 /* bits */ 37, 17463 /* flags */ 0, 17464 }, 17465 #endif /* chips */ 17466 17467 #if defined(BCM_56640_A0) 17468 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_3_BCM56640_A0fmt */ 17469 /* format IFP_SINGLE_WIDE_F3_3fmt */ 17470 /* nFields */ 9, 17471 /* *fields */ soc_IFP_SINGLE_WIDE_F1_6_BCM56640_A0fmt_fields, 17472 /* bits */ 49, 17473 /* flags */ 0, 17474 }, 17475 #endif /* chips */ 17476 17477 #if defined(BCM_56670_A0) 17478 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_3_BCM56670_A0fmt */ 17479 /* format IFP_SINGLE_WIDE_F3_3fmt */ 17480 /* nFields */ 7, 17481 /* *fields */ soc_IFP_SINGLE_WIDE_F3_3_BCM56560_A0fmt_fields, 17482 /* bits */ 49, 17483 /* flags */ 0, 17484 }, 17485 #endif /* chips */ 17486 17487 #if defined(BCM_56670_B0) 17488 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_3_BCM56670_B0fmt */ 17489 /* format IFP_SINGLE_WIDE_F3_3fmt */ 17490 /* nFields */ 7, 17491 /* *fields */ soc_IFP_SINGLE_WIDE_F3_3_BCM56560_A0fmt_fields, 17492 /* bits */ 49, 17493 /* flags */ 0, 17494 }, 17495 #endif /* chips */ 17496 17497 #if defined(BCM_56680_A0) 17498 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_3_BCM56680_A0fmt */ 17499 /* format IFP_SINGLE_WIDE_F3_3fmt */ 17500 /* nFields */ 6, 17501 /* *fields */ soc_IFP_SINGLE_WIDE_F3_3fmt_fields, 17502 /* bits */ 32, 17503 /* flags */ 0, 17504 }, 17505 #endif /* chips */ 17506 17507 #if defined(BCM_56680_B0) 17508 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_3_BCM56680_B0fmt */ 17509 /* format IFP_SINGLE_WIDE_F3_3fmt */ 17510 /* nFields */ 6, 17511 /* *fields */ soc_IFP_SINGLE_WIDE_F3_3fmt_fields, 17512 /* bits */ 32, 17513 /* flags */ 0, 17514 }, 17515 #endif /* chips */ 17516 17517 #if defined(BCM_56685_A0) 17518 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_3_BCM56685_A0fmt */ 17519 /* format IFP_SINGLE_WIDE_F3_3fmt */ 17520 /* nFields */ 7, 17521 /* *fields */ soc_IFP_SINGLE_WIDE_F1_6_BCM56634_A0fmt_fields, 17522 /* bits */ 37, 17523 /* flags */ 0, 17524 }, 17525 #endif /* chips */ 17526 17527 #if defined(BCM_56685_B0) 17528 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_3_BCM56685_B0fmt */ 17529 /* format IFP_SINGLE_WIDE_F3_3fmt */ 17530 /* nFields */ 7, 17531 /* *fields */ soc_IFP_SINGLE_WIDE_F1_6_BCM56634_A0fmt_fields, 17532 /* bits */ 37, 17533 /* flags */ 0, 17534 }, 17535 #endif /* chips */ 17536 17537 #if defined(BCM_56725_A0) 17538 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_3_BCM56725_A0fmt */ 17539 /* format IFP_SINGLE_WIDE_F3_3fmt */ 17540 /* nFields */ 6, 17541 /* *fields */ soc_IFP_SINGLE_WIDE_F3_3_BCM56820_A0fmt_fields, 17542 /* bits */ 33, 17543 /* flags */ 0, 17544 }, 17545 #endif /* chips */ 17546 17547 #if defined(BCM_56820_A0) 17548 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_3_BCM56820_A0fmt */ 17549 /* format IFP_SINGLE_WIDE_F3_3fmt */ 17550 /* nFields */ 6, 17551 /* *fields */ soc_IFP_SINGLE_WIDE_F3_3_BCM56820_A0fmt_fields, 17552 /* bits */ 33, 17553 /* flags */ 0, 17554 }, 17555 #endif /* chips */ 17556 17557 #if defined(BCM_56840_A0) 17558 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_3_BCM56840_A0fmt */ 17559 /* format IFP_SINGLE_WIDE_F3_3fmt */ 17560 /* nFields */ 8, 17561 /* *fields */ soc_IFP_SINGLE_WIDE_F1_6_BCM56840_A0fmt_fields, 17562 /* bits */ 39, 17563 /* flags */ 0, 17564 }, 17565 #endif /* chips */ 17566 17567 #if defined(BCM_56840_B0) 17568 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_3_BCM56840_B0fmt */ 17569 /* format IFP_SINGLE_WIDE_F3_3fmt */ 17570 /* nFields */ 8, 17571 /* *fields */ soc_IFP_SINGLE_WIDE_F1_6_BCM56840_A0fmt_fields, 17572 /* bits */ 39, 17573 /* flags */ 0, 17574 }, 17575 #endif /* chips */ 17576 17577 #if defined(BCM_56850_A0) 17578 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_3_BCM56850_A0fmt */ 17579 /* format IFP_SINGLE_WIDE_F3_3fmt */ 17580 /* nFields */ 7, 17581 /* *fields */ soc_IFP_SINGLE_WIDE_F1_6_BCM56850_A0fmt_fields, 17582 /* bits */ 49, 17583 /* flags */ 0, 17584 }, 17585 #endif /* chips */ 17586 17587 #if defined(BCM_56860_A0) 17588 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_3_BCM56860_A0fmt */ 17589 /* format IFP_SINGLE_WIDE_F3_3fmt */ 17590 /* nFields */ 7, 17591 /* *fields */ soc_IFP_SINGLE_WIDE_F1_6_BCM56850_A0fmt_fields, 17592 /* bits */ 49, 17593 /* flags */ 0, 17594 }, 17595 #endif /* chips */ 17596 17597 #if defined(BCM_88732_A0) 17598 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_3_BCM88732_A0fmt */ 17599 /* format IFP_SINGLE_WIDE_F3_3fmt */ 17600 /* nFields */ 6, 17601 /* *fields */ soc_IFP_SINGLE_WIDE_F3_3_BCM88732_A0fmt_fields, 17602 /* bits */ 33, 17603 /* flags */ 0, 17604 }, 17605 #endif /* chips */ 17606 17607 #if defined(BCM_53400_A0) 17608 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_4_BCM53400_A0fmt */ 17609 /* format IFP_SINGLE_WIDE_F3_4fmt */ 17610 /* nFields */ 3, 17611 /* *fields */ soc_IFP_SINGLE_WIDE_F3_4_BCM53400_A0fmt_fields, 17612 /* bits */ 37, 17613 /* flags */ 0, 17614 }, 17615 #endif /* chips */ 17616 17617 #if defined(BCM_53540_A0) 17618 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_4_BCM53540_A0fmt */ 17619 /* format IFP_SINGLE_WIDE_F3_4fmt */ 17620 /* nFields */ 3, 17621 /* *fields */ soc_IFP_SINGLE_WIDE_F3_4_BCM53400_A0fmt_fields, 17622 /* bits */ 37, 17623 /* flags */ 0, 17624 }, 17625 #endif /* chips */ 17626 17627 #if defined(BCM_53570_A0) 17628 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_4_BCM53570_A0fmt */ 17629 /* format IFP_SINGLE_WIDE_F3_4fmt */ 17630 /* nFields */ 3, 17631 /* *fields */ soc_IFP_SINGLE_WIDE_F3_4_BCM53570_A0fmt_fields, 17632 /* bits */ 39, 17633 /* flags */ 0, 17634 }, 17635 #endif /* chips */ 17636 17637 #if defined(BCM_53570_B0) 17638 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_4_BCM53570_B0fmt */ 17639 /* format IFP_SINGLE_WIDE_F3_4fmt */ 17640 /* nFields */ 3, 17641 /* *fields */ soc_IFP_SINGLE_WIDE_F3_4_BCM53570_A0fmt_fields, 17642 /* bits */ 39, 17643 /* flags */ 0, 17644 }, 17645 #endif /* chips */ 17646 17647 #if defined(BCM_56142_A0) 17648 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_4_BCM56142_A0fmt */ 17649 /* format IFP_SINGLE_WIDE_F3_4fmt */ 17650 /* nFields */ 3, 17651 /* *fields */ soc_IFP_SINGLE_WIDE_F3_4_BCM56634_A0fmt_fields, 17652 /* bits */ 37, 17653 /* flags */ 0, 17654 }, 17655 #endif /* chips */ 17656 17657 #if defined(BCM_56150_A0) 17658 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_4_BCM56150_A0fmt */ 17659 /* format IFP_SINGLE_WIDE_F3_4fmt */ 17660 /* nFields */ 3, 17661 /* *fields */ soc_IFP_SINGLE_WIDE_F3_4_BCM56150_A0fmt_fields, 17662 /* bits */ 37, 17663 /* flags */ 0, 17664 }, 17665 #endif /* chips */ 17666 17667 #if defined(BCM_56160_A0) 17668 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_4_BCM56160_A0fmt */ 17669 /* format IFP_SINGLE_WIDE_F3_4fmt */ 17670 /* nFields */ 3, 17671 /* *fields */ soc_IFP_SINGLE_WIDE_F3_4_BCM53400_A0fmt_fields, 17672 /* bits */ 37, 17673 /* flags */ 0, 17674 }, 17675 #endif /* chips */ 17676 17677 #if defined(BCM_56260_A0) 17678 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_4_BCM56260_A0fmt */ 17679 /* format IFP_SINGLE_WIDE_F3_4fmt */ 17680 /* nFields */ 5, 17681 /* *fields */ soc_IFP_SINGLE_WIDE_F3_4_BCM56260_A0fmt_fields, 17682 /* bits */ 40, 17683 /* flags */ 0, 17684 }, 17685 #endif /* chips */ 17686 17687 #if defined(BCM_56260_B0) 17688 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_4_BCM56260_B0fmt */ 17689 /* format IFP_SINGLE_WIDE_F3_4fmt */ 17690 /* nFields */ 5, 17691 /* *fields */ soc_IFP_SINGLE_WIDE_F3_4_BCM56260_A0fmt_fields, 17692 /* bits */ 40, 17693 /* flags */ 0, 17694 }, 17695 #endif /* chips */ 17696 17697 #if defined(BCM_56270_A0) 17698 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_4_BCM56270_A0fmt */ 17699 /* format IFP_SINGLE_WIDE_F3_4fmt */ 17700 /* nFields */ 5, 17701 /* *fields */ soc_IFP_SINGLE_WIDE_F3_4_BCM56260_A0fmt_fields, 17702 /* bits */ 40, 17703 /* flags */ 0, 17704 }, 17705 #endif /* chips */ 17706 17707 #if defined(BCM_56334_A0) 17708 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_4_BCM56334_A0fmt */ 17709 /* format IFP_SINGLE_WIDE_F3_4fmt */ 17710 /* nFields */ 3, 17711 /* *fields */ soc_IFP_SINGLE_WIDE_F3_4_BCM56634_A0fmt_fields, 17712 /* bits */ 37, 17713 /* flags */ 0, 17714 }, 17715 #endif /* chips */ 17716 17717 #if defined(BCM_56334_B0) 17718 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_4_BCM56334_B0fmt */ 17719 /* format IFP_SINGLE_WIDE_F3_4fmt */ 17720 /* nFields */ 3, 17721 /* *fields */ soc_IFP_SINGLE_WIDE_F3_4_BCM56634_A0fmt_fields, 17722 /* bits */ 37, 17723 /* flags */ 0, 17724 }, 17725 #endif /* chips */ 17726 17727 #if defined(BCM_56340_A0) 17728 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_4_BCM56340_A0fmt */ 17729 /* format IFP_SINGLE_WIDE_F3_4fmt */ 17730 /* nFields */ 6, 17731 /* *fields */ soc_IFP_SINGLE_WIDE_F3_4_BCM56640_A0fmt_fields, 17732 /* bits */ 49, 17733 /* flags */ 0, 17734 }, 17735 #endif /* chips */ 17736 17737 #if defined(BCM_56440_A0) 17738 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_4_BCM56440_A0fmt */ 17739 /* format IFP_SINGLE_WIDE_F3_4fmt */ 17740 /* nFields */ 5, 17741 /* *fields */ soc_IFP_SINGLE_WIDE_F3_4_BCM56440_A0fmt_fields, 17742 /* bits */ 39, 17743 /* flags */ 0, 17744 }, 17745 #endif /* chips */ 17746 17747 #if defined(BCM_56440_B0) 17748 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_4_BCM56440_B0fmt */ 17749 /* format IFP_SINGLE_WIDE_F3_4fmt */ 17750 /* nFields */ 5, 17751 /* *fields */ soc_IFP_SINGLE_WIDE_F3_4_BCM56440_A0fmt_fields, 17752 /* bits */ 39, 17753 /* flags */ 0, 17754 }, 17755 #endif /* chips */ 17756 17757 #if defined(BCM_56450_A0) 17758 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_4_BCM56450_A0fmt */ 17759 /* format IFP_SINGLE_WIDE_F3_4fmt */ 17760 /* nFields */ 5, 17761 /* *fields */ soc_IFP_SINGLE_WIDE_F3_4_BCM56450_A0fmt_fields, 17762 /* bits */ 40, 17763 /* flags */ 0, 17764 }, 17765 #endif /* chips */ 17766 17767 #if defined(BCM_56450_B0) 17768 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_4_BCM56450_B0fmt */ 17769 /* format IFP_SINGLE_WIDE_F3_4fmt */ 17770 /* nFields */ 5, 17771 /* *fields */ soc_IFP_SINGLE_WIDE_F3_4_BCM56450_A0fmt_fields, 17772 /* bits */ 40, 17773 /* flags */ 0, 17774 }, 17775 #endif /* chips */ 17776 17777 #if defined(BCM_56450_B1) 17778 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_4_BCM56450_B1fmt */ 17779 /* format IFP_SINGLE_WIDE_F3_4fmt */ 17780 /* nFields */ 5, 17781 /* *fields */ soc_IFP_SINGLE_WIDE_F3_4_BCM56450_A0fmt_fields, 17782 /* bits */ 40, 17783 /* flags */ 0, 17784 }, 17785 #endif /* chips */ 17786 17787 #if defined(BCM_56524_A0) 17788 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_4_BCM56524_A0fmt */ 17789 /* format IFP_SINGLE_WIDE_F3_4fmt */ 17790 /* nFields */ 3, 17791 /* *fields */ soc_IFP_SINGLE_WIDE_F3_4_BCM56634_A0fmt_fields, 17792 /* bits */ 37, 17793 /* flags */ 0, 17794 }, 17795 #endif /* chips */ 17796 17797 #if defined(BCM_56524_B0) 17798 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_4_BCM56524_B0fmt */ 17799 /* format IFP_SINGLE_WIDE_F3_4fmt */ 17800 /* nFields */ 3, 17801 /* *fields */ soc_IFP_SINGLE_WIDE_F3_4_BCM56634_A0fmt_fields, 17802 /* bits */ 37, 17803 /* flags */ 0, 17804 }, 17805 #endif /* chips */ 17806 17807 #if defined(BCM_56560_A0) 17808 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_4_BCM56560_A0fmt */ 17809 /* format IFP_SINGLE_WIDE_F3_4fmt */ 17810 /* nFields */ 6, 17811 /* *fields */ soc_IFP_SINGLE_WIDE_F3_4_BCM56560_A0fmt_fields, 17812 /* bits */ 49, 17813 /* flags */ 0, 17814 }, 17815 #endif /* chips */ 17816 17817 #if defined(BCM_56560_B0) 17818 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_4_BCM56560_B0fmt */ 17819 /* format IFP_SINGLE_WIDE_F3_4fmt */ 17820 /* nFields */ 6, 17821 /* *fields */ soc_IFP_SINGLE_WIDE_F3_4_BCM56560_A0fmt_fields, 17822 /* bits */ 49, 17823 /* flags */ 0, 17824 }, 17825 #endif /* chips */ 17826 17827 #if defined(BCM_56634_A0) 17828 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_4_BCM56634_A0fmt */ 17829 /* format IFP_SINGLE_WIDE_F3_4fmt */ 17830 /* nFields */ 3, 17831 /* *fields */ soc_IFP_SINGLE_WIDE_F3_4_BCM56634_A0fmt_fields, 17832 /* bits */ 37, 17833 /* flags */ 0, 17834 }, 17835 #endif /* chips */ 17836 17837 #if defined(BCM_56634_B0) 17838 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_4_BCM56634_B0fmt */ 17839 /* format IFP_SINGLE_WIDE_F3_4fmt */ 17840 /* nFields */ 3, 17841 /* *fields */ soc_IFP_SINGLE_WIDE_F3_4_BCM56634_A0fmt_fields, 17842 /* bits */ 37, 17843 /* flags */ 0, 17844 }, 17845 #endif /* chips */ 17846 17847 #if defined(BCM_56640_A0) 17848 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_4_BCM56640_A0fmt */ 17849 /* format IFP_SINGLE_WIDE_F3_4fmt */ 17850 /* nFields */ 6, 17851 /* *fields */ soc_IFP_SINGLE_WIDE_F3_4_BCM56640_A0fmt_fields, 17852 /* bits */ 49, 17853 /* flags */ 0, 17854 }, 17855 #endif /* chips */ 17856 17857 #if defined(BCM_56670_A0) 17858 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_4_BCM56670_A0fmt */ 17859 /* format IFP_SINGLE_WIDE_F3_4fmt */ 17860 /* nFields */ 6, 17861 /* *fields */ soc_IFP_SINGLE_WIDE_F3_4_BCM56560_A0fmt_fields, 17862 /* bits */ 49, 17863 /* flags */ 0, 17864 }, 17865 #endif /* chips */ 17866 17867 #if defined(BCM_56670_B0) 17868 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_4_BCM56670_B0fmt */ 17869 /* format IFP_SINGLE_WIDE_F3_4fmt */ 17870 /* nFields */ 6, 17871 /* *fields */ soc_IFP_SINGLE_WIDE_F3_4_BCM56560_A0fmt_fields, 17872 /* bits */ 49, 17873 /* flags */ 0, 17874 }, 17875 #endif /* chips */ 17876 17877 #if defined(BCM_56680_B0) 17878 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_4_BCM56680_B0fmt */ 17879 /* format IFP_SINGLE_WIDE_F3_4fmt */ 17880 /* nFields */ 2, 17881 /* *fields */ soc_IFP_SINGLE_WIDE_F3_4fmt_fields, 17882 /* bits */ 32, 17883 /* flags */ 0, 17884 }, 17885 #endif /* chips */ 17886 17887 #if defined(BCM_56685_A0) 17888 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_4_BCM56685_A0fmt */ 17889 /* format IFP_SINGLE_WIDE_F3_4fmt */ 17890 /* nFields */ 3, 17891 /* *fields */ soc_IFP_SINGLE_WIDE_F3_4_BCM56634_A0fmt_fields, 17892 /* bits */ 37, 17893 /* flags */ 0, 17894 }, 17895 #endif /* chips */ 17896 17897 #if defined(BCM_56685_B0) 17898 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_4_BCM56685_B0fmt */ 17899 /* format IFP_SINGLE_WIDE_F3_4fmt */ 17900 /* nFields */ 3, 17901 /* *fields */ soc_IFP_SINGLE_WIDE_F3_4_BCM56634_A0fmt_fields, 17902 /* bits */ 37, 17903 /* flags */ 0, 17904 }, 17905 #endif /* chips */ 17906 17907 #if defined(BCM_56725_A0) 17908 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_4_BCM56725_A0fmt */ 17909 /* format IFP_SINGLE_WIDE_F3_4fmt */ 17910 /* nFields */ 3, 17911 /* *fields */ soc_IFP_SINGLE_WIDE_F3_4_BCM56820_A0fmt_fields, 17912 /* bits */ 33, 17913 /* flags */ 0, 17914 }, 17915 #endif /* chips */ 17916 17917 #if defined(BCM_56820_A0) 17918 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_4_BCM56820_A0fmt */ 17919 /* format IFP_SINGLE_WIDE_F3_4fmt */ 17920 /* nFields */ 3, 17921 /* *fields */ soc_IFP_SINGLE_WIDE_F3_4_BCM56820_A0fmt_fields, 17922 /* bits */ 33, 17923 /* flags */ 0, 17924 }, 17925 #endif /* chips */ 17926 17927 #if defined(BCM_56840_A0) 17928 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_4_BCM56840_A0fmt */ 17929 /* format IFP_SINGLE_WIDE_F3_4fmt */ 17930 /* nFields */ 3, 17931 /* *fields */ soc_IFP_SINGLE_WIDE_F3_4_BCM56840_A0fmt_fields, 17932 /* bits */ 39, 17933 /* flags */ 0, 17934 }, 17935 #endif /* chips */ 17936 17937 #if defined(BCM_56840_B0) 17938 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_4_BCM56840_B0fmt */ 17939 /* format IFP_SINGLE_WIDE_F3_4fmt */ 17940 /* nFields */ 3, 17941 /* *fields */ soc_IFP_SINGLE_WIDE_F3_4_BCM56840_A0fmt_fields, 17942 /* bits */ 39, 17943 /* flags */ 0, 17944 }, 17945 #endif /* chips */ 17946 17947 #if defined(BCM_56850_A0) 17948 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_4_BCM56850_A0fmt */ 17949 /* format IFP_SINGLE_WIDE_F3_4fmt */ 17950 /* nFields */ 6, 17951 /* *fields */ soc_IFP_SINGLE_WIDE_F3_4_BCM56850_A0fmt_fields, 17952 /* bits */ 49, 17953 /* flags */ 0, 17954 }, 17955 #endif /* chips */ 17956 17957 #if defined(BCM_56860_A0) 17958 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_4_BCM56860_A0fmt */ 17959 /* format IFP_SINGLE_WIDE_F3_4fmt */ 17960 /* nFields */ 6, 17961 /* *fields */ soc_IFP_SINGLE_WIDE_F3_4_BCM56850_A0fmt_fields, 17962 /* bits */ 49, 17963 /* flags */ 0, 17964 }, 17965 #endif /* chips */ 17966 17967 #if defined(BCM_88732_A0) 17968 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_4_BCM88732_A0fmt */ 17969 /* format IFP_SINGLE_WIDE_F3_4fmt */ 17970 /* nFields */ 3, 17971 /* *fields */ soc_IFP_SINGLE_WIDE_F3_4_BCM88732_A0fmt_fields, 17972 /* bits */ 33, 17973 /* flags */ 0, 17974 }, 17975 #endif /* chips */ 17976 17977 #if defined(BCM_53400_A0) 17978 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_5_BCM53400_A0fmt */ 17979 /* format IFP_SINGLE_WIDE_F3_5fmt */ 17980 /* nFields */ 3, 17981 /* *fields */ soc_IFP_SINGLE_WIDE_F1_4_BCM53400_A0fmt_fields, 17982 /* bits */ 37, 17983 /* flags */ 0, 17984 }, 17985 #endif /* chips */ 17986 17987 #if defined(BCM_53540_A0) 17988 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_5_BCM53540_A0fmt */ 17989 /* format IFP_SINGLE_WIDE_F3_5fmt */ 17990 /* nFields */ 3, 17991 /* *fields */ soc_IFP_SINGLE_WIDE_F1_4_BCM53400_A0fmt_fields, 17992 /* bits */ 37, 17993 /* flags */ 0, 17994 }, 17995 #endif /* chips */ 17996 17997 #if defined(BCM_53570_A0) 17998 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_5_BCM53570_A0fmt */ 17999 /* format IFP_SINGLE_WIDE_F3_5fmt */ 18000 /* nFields */ 3, 18001 /* *fields */ soc_IFP_SINGLE_WIDE_F1_4_BCM53570_A0fmt_fields, 18002 /* bits */ 39, 18003 /* flags */ 0, 18004 }, 18005 #endif /* chips */ 18006 18007 #if defined(BCM_53570_B0) 18008 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_5_BCM53570_B0fmt */ 18009 /* format IFP_SINGLE_WIDE_F3_5fmt */ 18010 /* nFields */ 3, 18011 /* *fields */ soc_IFP_SINGLE_WIDE_F1_4_BCM53570_A0fmt_fields, 18012 /* bits */ 39, 18013 /* flags */ 0, 18014 }, 18015 #endif /* chips */ 18016 18017 #if defined(BCM_56142_A0) 18018 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_5_BCM56142_A0fmt */ 18019 /* format IFP_SINGLE_WIDE_F3_5fmt */ 18020 /* nFields */ 3, 18021 /* *fields */ soc_IFP_SINGLE_WIDE_F1_4_BCM56634_A0fmt_fields, 18022 /* bits */ 37, 18023 /* flags */ 0, 18024 }, 18025 #endif /* chips */ 18026 18027 #if defined(BCM_56150_A0) 18028 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_5_BCM56150_A0fmt */ 18029 /* format IFP_SINGLE_WIDE_F3_5fmt */ 18030 /* nFields */ 3, 18031 /* *fields */ soc_IFP_SINGLE_WIDE_F1_4_BCM56150_A0fmt_fields, 18032 /* bits */ 37, 18033 /* flags */ 0, 18034 }, 18035 #endif /* chips */ 18036 18037 #if defined(BCM_56160_A0) 18038 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_5_BCM56160_A0fmt */ 18039 /* format IFP_SINGLE_WIDE_F3_5fmt */ 18040 /* nFields */ 3, 18041 /* *fields */ soc_IFP_SINGLE_WIDE_F1_4_BCM53400_A0fmt_fields, 18042 /* bits */ 37, 18043 /* flags */ 0, 18044 }, 18045 #endif /* chips */ 18046 18047 #if defined(BCM_56260_A0) 18048 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_5_BCM56260_A0fmt */ 18049 /* format IFP_SINGLE_WIDE_F3_5fmt */ 18050 /* nFields */ 3, 18051 /* *fields */ soc_IFP_SINGLE_WIDE_F1_4_BCM56260_A0fmt_fields, 18052 /* bits */ 40, 18053 /* flags */ 0, 18054 }, 18055 #endif /* chips */ 18056 18057 #if defined(BCM_56260_B0) 18058 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_5_BCM56260_B0fmt */ 18059 /* format IFP_SINGLE_WIDE_F3_5fmt */ 18060 /* nFields */ 3, 18061 /* *fields */ soc_IFP_SINGLE_WIDE_F1_4_BCM56260_A0fmt_fields, 18062 /* bits */ 40, 18063 /* flags */ 0, 18064 }, 18065 #endif /* chips */ 18066 18067 #if defined(BCM_56270_A0) 18068 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_5_BCM56270_A0fmt */ 18069 /* format IFP_SINGLE_WIDE_F3_5fmt */ 18070 /* nFields */ 3, 18071 /* *fields */ soc_IFP_SINGLE_WIDE_F1_4_BCM56260_A0fmt_fields, 18072 /* bits */ 40, 18073 /* flags */ 0, 18074 }, 18075 #endif /* chips */ 18076 18077 #if defined(BCM_56334_A0) 18078 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_5_BCM56334_A0fmt */ 18079 /* format IFP_SINGLE_WIDE_F3_5fmt */ 18080 /* nFields */ 3, 18081 /* *fields */ soc_IFP_SINGLE_WIDE_F1_4_BCM56634_A0fmt_fields, 18082 /* bits */ 37, 18083 /* flags */ 0, 18084 }, 18085 #endif /* chips */ 18086 18087 #if defined(BCM_56334_B0) 18088 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_5_BCM56334_B0fmt */ 18089 /* format IFP_SINGLE_WIDE_F3_5fmt */ 18090 /* nFields */ 3, 18091 /* *fields */ soc_IFP_SINGLE_WIDE_F1_4_BCM56634_A0fmt_fields, 18092 /* bits */ 37, 18093 /* flags */ 0, 18094 }, 18095 #endif /* chips */ 18096 18097 #if defined(BCM_56340_A0) 18098 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_5_BCM56340_A0fmt */ 18099 /* format IFP_SINGLE_WIDE_F3_5fmt */ 18100 /* nFields */ 5, 18101 /* *fields */ soc_IFP_SINGLE_WIDE_F1_4_BCM56640_A0fmt_fields, 18102 /* bits */ 49, 18103 /* flags */ 0, 18104 }, 18105 #endif /* chips */ 18106 18107 #if defined(BCM_56440_A0) 18108 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_5_BCM56440_A0fmt */ 18109 /* format IFP_SINGLE_WIDE_F3_5fmt */ 18110 /* nFields */ 3, 18111 /* *fields */ soc_IFP_SINGLE_WIDE_F1_4_BCM56440_A0fmt_fields, 18112 /* bits */ 39, 18113 /* flags */ 0, 18114 }, 18115 #endif /* chips */ 18116 18117 #if defined(BCM_56440_B0) 18118 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_5_BCM56440_B0fmt */ 18119 /* format IFP_SINGLE_WIDE_F3_5fmt */ 18120 /* nFields */ 3, 18121 /* *fields */ soc_IFP_SINGLE_WIDE_F1_4_BCM56440_A0fmt_fields, 18122 /* bits */ 39, 18123 /* flags */ 0, 18124 }, 18125 #endif /* chips */ 18126 18127 #if defined(BCM_56450_A0) 18128 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_5_BCM56450_A0fmt */ 18129 /* format IFP_SINGLE_WIDE_F3_5fmt */ 18130 /* nFields */ 3, 18131 /* *fields */ soc_IFP_SINGLE_WIDE_F1_4_BCM56450_A0fmt_fields, 18132 /* bits */ 40, 18133 /* flags */ 0, 18134 }, 18135 #endif /* chips */ 18136 18137 #if defined(BCM_56450_B0) 18138 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_5_BCM56450_B0fmt */ 18139 /* format IFP_SINGLE_WIDE_F3_5fmt */ 18140 /* nFields */ 3, 18141 /* *fields */ soc_IFP_SINGLE_WIDE_F1_4_BCM56450_A0fmt_fields, 18142 /* bits */ 40, 18143 /* flags */ 0, 18144 }, 18145 #endif /* chips */ 18146 18147 #if defined(BCM_56450_B1) 18148 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_5_BCM56450_B1fmt */ 18149 /* format IFP_SINGLE_WIDE_F3_5fmt */ 18150 /* nFields */ 3, 18151 /* *fields */ soc_IFP_SINGLE_WIDE_F1_4_BCM56450_A0fmt_fields, 18152 /* bits */ 40, 18153 /* flags */ 0, 18154 }, 18155 #endif /* chips */ 18156 18157 #if defined(BCM_56524_A0) 18158 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_5_BCM56524_A0fmt */ 18159 /* format IFP_SINGLE_WIDE_F3_5fmt */ 18160 /* nFields */ 3, 18161 /* *fields */ soc_IFP_SINGLE_WIDE_F1_4_BCM56634_A0fmt_fields, 18162 /* bits */ 37, 18163 /* flags */ 0, 18164 }, 18165 #endif /* chips */ 18166 18167 #if defined(BCM_56524_B0) 18168 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_5_BCM56524_B0fmt */ 18169 /* format IFP_SINGLE_WIDE_F3_5fmt */ 18170 /* nFields */ 3, 18171 /* *fields */ soc_IFP_SINGLE_WIDE_F1_4_BCM56634_A0fmt_fields, 18172 /* bits */ 37, 18173 /* flags */ 0, 18174 }, 18175 #endif /* chips */ 18176 18177 #if defined(BCM_56560_A0) 18178 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_5_BCM56560_A0fmt */ 18179 /* format IFP_SINGLE_WIDE_F3_5fmt */ 18180 /* nFields */ 5, 18181 /* *fields */ soc_IFP_SINGLE_WIDE_F3_5_BCM56560_A0fmt_fields, 18182 /* bits */ 49, 18183 /* flags */ 0, 18184 }, 18185 #endif /* chips */ 18186 18187 #if defined(BCM_56560_B0) 18188 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_5_BCM56560_B0fmt */ 18189 /* format IFP_SINGLE_WIDE_F3_5fmt */ 18190 /* nFields */ 5, 18191 /* *fields */ soc_IFP_SINGLE_WIDE_F3_5_BCM56560_A0fmt_fields, 18192 /* bits */ 49, 18193 /* flags */ 0, 18194 }, 18195 #endif /* chips */ 18196 18197 #if defined(BCM_56634_A0) 18198 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_5_BCM56634_A0fmt */ 18199 /* format IFP_SINGLE_WIDE_F3_5fmt */ 18200 /* nFields */ 3, 18201 /* *fields */ soc_IFP_SINGLE_WIDE_F1_4_BCM56634_A0fmt_fields, 18202 /* bits */ 37, 18203 /* flags */ 0, 18204 }, 18205 #endif /* chips */ 18206 18207 #if defined(BCM_56634_B0) 18208 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_5_BCM56634_B0fmt */ 18209 /* format IFP_SINGLE_WIDE_F3_5fmt */ 18210 /* nFields */ 3, 18211 /* *fields */ soc_IFP_SINGLE_WIDE_F1_4_BCM56634_A0fmt_fields, 18212 /* bits */ 37, 18213 /* flags */ 0, 18214 }, 18215 #endif /* chips */ 18216 18217 #if defined(BCM_56640_A0) 18218 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_5_BCM56640_A0fmt */ 18219 /* format IFP_SINGLE_WIDE_F3_5fmt */ 18220 /* nFields */ 5, 18221 /* *fields */ soc_IFP_SINGLE_WIDE_F1_4_BCM56640_A0fmt_fields, 18222 /* bits */ 49, 18223 /* flags */ 0, 18224 }, 18225 #endif /* chips */ 18226 18227 #if defined(BCM_56670_A0) 18228 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_5_BCM56670_A0fmt */ 18229 /* format IFP_SINGLE_WIDE_F3_5fmt */ 18230 /* nFields */ 5, 18231 /* *fields */ soc_IFP_SINGLE_WIDE_F3_5_BCM56560_A0fmt_fields, 18232 /* bits */ 49, 18233 /* flags */ 0, 18234 }, 18235 #endif /* chips */ 18236 18237 #if defined(BCM_56670_B0) 18238 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_5_BCM56670_B0fmt */ 18239 /* format IFP_SINGLE_WIDE_F3_5fmt */ 18240 /* nFields */ 5, 18241 /* *fields */ soc_IFP_SINGLE_WIDE_F3_5_BCM56560_A0fmt_fields, 18242 /* bits */ 49, 18243 /* flags */ 0, 18244 }, 18245 #endif /* chips */ 18246 18247 #if defined(BCM_56685_A0) 18248 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_5_BCM56685_A0fmt */ 18249 /* format IFP_SINGLE_WIDE_F3_5fmt */ 18250 /* nFields */ 3, 18251 /* *fields */ soc_IFP_SINGLE_WIDE_F1_4_BCM56634_A0fmt_fields, 18252 /* bits */ 37, 18253 /* flags */ 0, 18254 }, 18255 #endif /* chips */ 18256 18257 #if defined(BCM_56685_B0) 18258 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_5_BCM56685_B0fmt */ 18259 /* format IFP_SINGLE_WIDE_F3_5fmt */ 18260 /* nFields */ 3, 18261 /* *fields */ soc_IFP_SINGLE_WIDE_F1_4_BCM56634_A0fmt_fields, 18262 /* bits */ 37, 18263 /* flags */ 0, 18264 }, 18265 #endif /* chips */ 18266 18267 #if defined(BCM_56725_A0) 18268 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_5_BCM56725_A0fmt */ 18269 /* format IFP_SINGLE_WIDE_F3_5fmt */ 18270 /* nFields */ 3, 18271 /* *fields */ soc_IFP_SINGLE_WIDE_F3_5_BCM56820_A0fmt_fields, 18272 /* bits */ 33, 18273 /* flags */ 0, 18274 }, 18275 #endif /* chips */ 18276 18277 #if defined(BCM_56820_A0) 18278 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_5_BCM56820_A0fmt */ 18279 /* format IFP_SINGLE_WIDE_F3_5fmt */ 18280 /* nFields */ 3, 18281 /* *fields */ soc_IFP_SINGLE_WIDE_F3_5_BCM56820_A0fmt_fields, 18282 /* bits */ 33, 18283 /* flags */ 0, 18284 }, 18285 #endif /* chips */ 18286 18287 #if defined(BCM_56840_A0) 18288 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_5_BCM56840_A0fmt */ 18289 /* format IFP_SINGLE_WIDE_F3_5fmt */ 18290 /* nFields */ 5, 18291 /* *fields */ soc_IFP_SINGLE_WIDE_F1_4_BCM56840_A0fmt_fields, 18292 /* bits */ 39, 18293 /* flags */ 0, 18294 }, 18295 #endif /* chips */ 18296 18297 #if defined(BCM_56840_B0) 18298 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_5_BCM56840_B0fmt */ 18299 /* format IFP_SINGLE_WIDE_F3_5fmt */ 18300 /* nFields */ 5, 18301 /* *fields */ soc_IFP_SINGLE_WIDE_F1_4_BCM56840_A0fmt_fields, 18302 /* bits */ 39, 18303 /* flags */ 0, 18304 }, 18305 #endif /* chips */ 18306 18307 #if defined(BCM_56850_A0) 18308 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_5_BCM56850_A0fmt */ 18309 /* format IFP_SINGLE_WIDE_F3_5fmt */ 18310 /* nFields */ 5, 18311 /* *fields */ soc_IFP_SINGLE_WIDE_F1_4_BCM56640_A0fmt_fields, 18312 /* bits */ 49, 18313 /* flags */ 0, 18314 }, 18315 #endif /* chips */ 18316 18317 #if defined(BCM_56860_A0) 18318 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_5_BCM56860_A0fmt */ 18319 /* format IFP_SINGLE_WIDE_F3_5fmt */ 18320 /* nFields */ 5, 18321 /* *fields */ soc_IFP_SINGLE_WIDE_F1_4_BCM56640_A0fmt_fields, 18322 /* bits */ 49, 18323 /* flags */ 0, 18324 }, 18325 #endif /* chips */ 18326 18327 #if defined(BCM_88732_A0) 18328 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_5_BCM88732_A0fmt */ 18329 /* format IFP_SINGLE_WIDE_F3_5fmt */ 18330 /* nFields */ 3, 18331 /* *fields */ soc_IFP_SINGLE_WIDE_F3_5_BCM88732_A0fmt_fields, 18332 /* bits */ 33, 18333 /* flags */ 0, 18334 }, 18335 #endif /* chips */ 18336 18337 #if defined(BCM_53400_A0) 18338 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_6_BCM53400_A0fmt */ 18339 /* format IFP_SINGLE_WIDE_F3_6fmt */ 18340 /* nFields */ 3, 18341 /* *fields */ soc_IFP_SINGLE_WIDE_F3_6_BCM53400_A0fmt_fields, 18342 /* bits */ 37, 18343 /* flags */ 0, 18344 }, 18345 #endif /* chips */ 18346 18347 #if defined(BCM_53540_A0) 18348 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_6_BCM53540_A0fmt */ 18349 /* format IFP_SINGLE_WIDE_F3_6fmt */ 18350 /* nFields */ 3, 18351 /* *fields */ soc_IFP_SINGLE_WIDE_F3_6_BCM53400_A0fmt_fields, 18352 /* bits */ 37, 18353 /* flags */ 0, 18354 }, 18355 #endif /* chips */ 18356 18357 #if defined(BCM_53570_A0) 18358 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_6_BCM53570_A0fmt */ 18359 /* format IFP_SINGLE_WIDE_F3_6fmt */ 18360 /* nFields */ 3, 18361 /* *fields */ soc_IFP_SINGLE_WIDE_F3_6_BCM53570_A0fmt_fields, 18362 /* bits */ 39, 18363 /* flags */ 0, 18364 }, 18365 #endif /* chips */ 18366 18367 #if defined(BCM_53570_B0) 18368 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_6_BCM53570_B0fmt */ 18369 /* format IFP_SINGLE_WIDE_F3_6fmt */ 18370 /* nFields */ 3, 18371 /* *fields */ soc_IFP_SINGLE_WIDE_F3_6_BCM53570_A0fmt_fields, 18372 /* bits */ 39, 18373 /* flags */ 0, 18374 }, 18375 #endif /* chips */ 18376 18377 #if defined(BCM_56142_A0) 18378 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_6_BCM56142_A0fmt */ 18379 /* format IFP_SINGLE_WIDE_F3_6fmt */ 18380 /* nFields */ 3, 18381 /* *fields */ soc_IFP_SINGLE_WIDE_F3_6_BCM56634_A0fmt_fields, 18382 /* bits */ 37, 18383 /* flags */ 0, 18384 }, 18385 #endif /* chips */ 18386 18387 #if defined(BCM_56150_A0) 18388 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_6_BCM56150_A0fmt */ 18389 /* format IFP_SINGLE_WIDE_F3_6fmt */ 18390 /* nFields */ 3, 18391 /* *fields */ soc_IFP_SINGLE_WIDE_F3_6_BCM56150_A0fmt_fields, 18392 /* bits */ 37, 18393 /* flags */ 0, 18394 }, 18395 #endif /* chips */ 18396 18397 #if defined(BCM_56160_A0) 18398 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_6_BCM56160_A0fmt */ 18399 /* format IFP_SINGLE_WIDE_F3_6fmt */ 18400 /* nFields */ 3, 18401 /* *fields */ soc_IFP_SINGLE_WIDE_F3_6_BCM53400_A0fmt_fields, 18402 /* bits */ 37, 18403 /* flags */ 0, 18404 }, 18405 #endif /* chips */ 18406 18407 #if defined(BCM_56260_A0) 18408 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_6_BCM56260_A0fmt */ 18409 /* format IFP_SINGLE_WIDE_F3_6fmt */ 18410 /* nFields */ 3, 18411 /* *fields */ soc_IFP_SINGLE_WIDE_F3_6_BCM56260_A0fmt_fields, 18412 /* bits */ 40, 18413 /* flags */ 0, 18414 }, 18415 #endif /* chips */ 18416 18417 #if defined(BCM_56260_B0) 18418 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_6_BCM56260_B0fmt */ 18419 /* format IFP_SINGLE_WIDE_F3_6fmt */ 18420 /* nFields */ 3, 18421 /* *fields */ soc_IFP_SINGLE_WIDE_F3_6_BCM56260_A0fmt_fields, 18422 /* bits */ 40, 18423 /* flags */ 0, 18424 }, 18425 #endif /* chips */ 18426 18427 #if defined(BCM_56270_A0) 18428 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_6_BCM56270_A0fmt */ 18429 /* format IFP_SINGLE_WIDE_F3_6fmt */ 18430 /* nFields */ 3, 18431 /* *fields */ soc_IFP_SINGLE_WIDE_F3_6_BCM56260_A0fmt_fields, 18432 /* bits */ 40, 18433 /* flags */ 0, 18434 }, 18435 #endif /* chips */ 18436 18437 #if defined(BCM_56334_A0) 18438 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_6_BCM56334_A0fmt */ 18439 /* format IFP_SINGLE_WIDE_F3_6fmt */ 18440 /* nFields */ 3, 18441 /* *fields */ soc_IFP_SINGLE_WIDE_F3_6_BCM56634_A0fmt_fields, 18442 /* bits */ 37, 18443 /* flags */ 0, 18444 }, 18445 #endif /* chips */ 18446 18447 #if defined(BCM_56334_B0) 18448 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_6_BCM56334_B0fmt */ 18449 /* format IFP_SINGLE_WIDE_F3_6fmt */ 18450 /* nFields */ 3, 18451 /* *fields */ soc_IFP_SINGLE_WIDE_F3_6_BCM56634_A0fmt_fields, 18452 /* bits */ 37, 18453 /* flags */ 0, 18454 }, 18455 #endif /* chips */ 18456 18457 #if defined(BCM_56340_A0) 18458 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_6_BCM56340_A0fmt */ 18459 /* format IFP_SINGLE_WIDE_F3_6fmt */ 18460 /* nFields */ 4, 18461 /* *fields */ soc_IFP_SINGLE_WIDE_F3_6_BCM56640_A0fmt_fields, 18462 /* bits */ 49, 18463 /* flags */ 0, 18464 }, 18465 #endif /* chips */ 18466 18467 #if defined(BCM_56440_A0) 18468 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_6_BCM56440_A0fmt */ 18469 /* format IFP_SINGLE_WIDE_F3_6fmt */ 18470 /* nFields */ 3, 18471 /* *fields */ soc_IFP_SINGLE_WIDE_F3_6_BCM56840_A0fmt_fields, 18472 /* bits */ 39, 18473 /* flags */ 0, 18474 }, 18475 #endif /* chips */ 18476 18477 #if defined(BCM_56440_B0) 18478 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_6_BCM56440_B0fmt */ 18479 /* format IFP_SINGLE_WIDE_F3_6fmt */ 18480 /* nFields */ 3, 18481 /* *fields */ soc_IFP_SINGLE_WIDE_F3_6_BCM56840_A0fmt_fields, 18482 /* bits */ 39, 18483 /* flags */ 0, 18484 }, 18485 #endif /* chips */ 18486 18487 #if defined(BCM_56450_A0) 18488 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_6_BCM56450_A0fmt */ 18489 /* format IFP_SINGLE_WIDE_F3_6fmt */ 18490 /* nFields */ 3, 18491 /* *fields */ soc_IFP_SINGLE_WIDE_F3_6_BCM56450_A0fmt_fields, 18492 /* bits */ 40, 18493 /* flags */ 0, 18494 }, 18495 #endif /* chips */ 18496 18497 #if defined(BCM_56450_B0) 18498 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_6_BCM56450_B0fmt */ 18499 /* format IFP_SINGLE_WIDE_F3_6fmt */ 18500 /* nFields */ 3, 18501 /* *fields */ soc_IFP_SINGLE_WIDE_F3_6_BCM56450_A0fmt_fields, 18502 /* bits */ 40, 18503 /* flags */ 0, 18504 }, 18505 #endif /* chips */ 18506 18507 #if defined(BCM_56450_B1) 18508 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_6_BCM56450_B1fmt */ 18509 /* format IFP_SINGLE_WIDE_F3_6fmt */ 18510 /* nFields */ 3, 18511 /* *fields */ soc_IFP_SINGLE_WIDE_F3_6_BCM56450_A0fmt_fields, 18512 /* bits */ 40, 18513 /* flags */ 0, 18514 }, 18515 #endif /* chips */ 18516 18517 #if defined(BCM_56524_A0) 18518 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_6_BCM56524_A0fmt */ 18519 /* format IFP_SINGLE_WIDE_F3_6fmt */ 18520 /* nFields */ 3, 18521 /* *fields */ soc_IFP_SINGLE_WIDE_F3_6_BCM56634_A0fmt_fields, 18522 /* bits */ 37, 18523 /* flags */ 0, 18524 }, 18525 #endif /* chips */ 18526 18527 #if defined(BCM_56524_B0) 18528 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_6_BCM56524_B0fmt */ 18529 /* format IFP_SINGLE_WIDE_F3_6fmt */ 18530 /* nFields */ 3, 18531 /* *fields */ soc_IFP_SINGLE_WIDE_F3_6_BCM56634_A0fmt_fields, 18532 /* bits */ 37, 18533 /* flags */ 0, 18534 }, 18535 #endif /* chips */ 18536 18537 #if defined(BCM_56560_A0) 18538 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_6_BCM56560_A0fmt */ 18539 /* format IFP_SINGLE_WIDE_F3_6fmt */ 18540 /* nFields */ 4, 18541 /* *fields */ soc_IFP_SINGLE_WIDE_F3_6_BCM56560_A0fmt_fields, 18542 /* bits */ 49, 18543 /* flags */ 0, 18544 }, 18545 #endif /* chips */ 18546 18547 #if defined(BCM_56560_B0) 18548 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_6_BCM56560_B0fmt */ 18549 /* format IFP_SINGLE_WIDE_F3_6fmt */ 18550 /* nFields */ 4, 18551 /* *fields */ soc_IFP_SINGLE_WIDE_F3_6_BCM56560_A0fmt_fields, 18552 /* bits */ 49, 18553 /* flags */ 0, 18554 }, 18555 #endif /* chips */ 18556 18557 #if defined(BCM_56634_A0) 18558 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_6_BCM56634_A0fmt */ 18559 /* format IFP_SINGLE_WIDE_F3_6fmt */ 18560 /* nFields */ 3, 18561 /* *fields */ soc_IFP_SINGLE_WIDE_F3_6_BCM56634_A0fmt_fields, 18562 /* bits */ 37, 18563 /* flags */ 0, 18564 }, 18565 #endif /* chips */ 18566 18567 #if defined(BCM_56634_B0) 18568 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_6_BCM56634_B0fmt */ 18569 /* format IFP_SINGLE_WIDE_F3_6fmt */ 18570 /* nFields */ 3, 18571 /* *fields */ soc_IFP_SINGLE_WIDE_F3_6_BCM56634_A0fmt_fields, 18572 /* bits */ 37, 18573 /* flags */ 0, 18574 }, 18575 #endif /* chips */ 18576 18577 #if defined(BCM_56640_A0) 18578 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_6_BCM56640_A0fmt */ 18579 /* format IFP_SINGLE_WIDE_F3_6fmt */ 18580 /* nFields */ 4, 18581 /* *fields */ soc_IFP_SINGLE_WIDE_F3_6_BCM56640_A0fmt_fields, 18582 /* bits */ 49, 18583 /* flags */ 0, 18584 }, 18585 #endif /* chips */ 18586 18587 #if defined(BCM_56670_A0) 18588 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_6_BCM56670_A0fmt */ 18589 /* format IFP_SINGLE_WIDE_F3_6fmt */ 18590 /* nFields */ 4, 18591 /* *fields */ soc_IFP_SINGLE_WIDE_F3_6_BCM56560_A0fmt_fields, 18592 /* bits */ 49, 18593 /* flags */ 0, 18594 }, 18595 #endif /* chips */ 18596 18597 #if defined(BCM_56670_B0) 18598 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_6_BCM56670_B0fmt */ 18599 /* format IFP_SINGLE_WIDE_F3_6fmt */ 18600 /* nFields */ 4, 18601 /* *fields */ soc_IFP_SINGLE_WIDE_F3_6_BCM56560_A0fmt_fields, 18602 /* bits */ 49, 18603 /* flags */ 0, 18604 }, 18605 #endif /* chips */ 18606 18607 #if defined(BCM_56680_B0) 18608 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_6_BCM56680_B0fmt */ 18609 /* format IFP_SINGLE_WIDE_F3_6fmt */ 18610 /* nFields */ 2, 18611 /* *fields */ soc_IFP_SINGLE_WIDE_F3_6fmt_fields, 18612 /* bits */ 32, 18613 /* flags */ 0, 18614 }, 18615 #endif /* chips */ 18616 18617 #if defined(BCM_56685_A0) 18618 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_6_BCM56685_A0fmt */ 18619 /* format IFP_SINGLE_WIDE_F3_6fmt */ 18620 /* nFields */ 3, 18621 /* *fields */ soc_IFP_SINGLE_WIDE_F3_6_BCM56634_A0fmt_fields, 18622 /* bits */ 37, 18623 /* flags */ 0, 18624 }, 18625 #endif /* chips */ 18626 18627 #if defined(BCM_56685_B0) 18628 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_6_BCM56685_B0fmt */ 18629 /* format IFP_SINGLE_WIDE_F3_6fmt */ 18630 /* nFields */ 3, 18631 /* *fields */ soc_IFP_SINGLE_WIDE_F3_6_BCM56634_A0fmt_fields, 18632 /* bits */ 37, 18633 /* flags */ 0, 18634 }, 18635 #endif /* chips */ 18636 18637 #if defined(BCM_56725_A0) 18638 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_6_BCM56725_A0fmt */ 18639 /* format IFP_SINGLE_WIDE_F3_6fmt */ 18640 /* nFields */ 3, 18641 /* *fields */ soc_IFP_SINGLE_WIDE_F3_6_BCM56820_A0fmt_fields, 18642 /* bits */ 33, 18643 /* flags */ 0, 18644 }, 18645 #endif /* chips */ 18646 18647 #if defined(BCM_56820_A0) 18648 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_6_BCM56820_A0fmt */ 18649 /* format IFP_SINGLE_WIDE_F3_6fmt */ 18650 /* nFields */ 3, 18651 /* *fields */ soc_IFP_SINGLE_WIDE_F3_6_BCM56820_A0fmt_fields, 18652 /* bits */ 33, 18653 /* flags */ 0, 18654 }, 18655 #endif /* chips */ 18656 18657 #if defined(BCM_56840_A0) 18658 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_6_BCM56840_A0fmt */ 18659 /* format IFP_SINGLE_WIDE_F3_6fmt */ 18660 /* nFields */ 3, 18661 /* *fields */ soc_IFP_SINGLE_WIDE_F3_6_BCM56840_A0fmt_fields, 18662 /* bits */ 39, 18663 /* flags */ 0, 18664 }, 18665 #endif /* chips */ 18666 18667 #if defined(BCM_56840_B0) 18668 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_6_BCM56840_B0fmt */ 18669 /* format IFP_SINGLE_WIDE_F3_6fmt */ 18670 /* nFields */ 3, 18671 /* *fields */ soc_IFP_SINGLE_WIDE_F3_6_BCM56840_A0fmt_fields, 18672 /* bits */ 39, 18673 /* flags */ 0, 18674 }, 18675 #endif /* chips */ 18676 18677 #if defined(BCM_56850_A0) 18678 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_6_BCM56850_A0fmt */ 18679 /* format IFP_SINGLE_WIDE_F3_6fmt */ 18680 /* nFields */ 4, 18681 /* *fields */ soc_IFP_SINGLE_WIDE_F3_6_BCM56640_A0fmt_fields, 18682 /* bits */ 49, 18683 /* flags */ 0, 18684 }, 18685 #endif /* chips */ 18686 18687 #if defined(BCM_56860_A0) 18688 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_6_BCM56860_A0fmt */ 18689 /* format IFP_SINGLE_WIDE_F3_6fmt */ 18690 /* nFields */ 4, 18691 /* *fields */ soc_IFP_SINGLE_WIDE_F3_6_BCM56640_A0fmt_fields, 18692 /* bits */ 49, 18693 /* flags */ 0, 18694 }, 18695 #endif /* chips */ 18696 18697 #if defined(BCM_88732_A0) 18698 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_6_BCM88732_A0fmt */ 18699 /* format IFP_SINGLE_WIDE_F3_6fmt */ 18700 /* nFields */ 3, 18701 /* *fields */ soc_IFP_SINGLE_WIDE_F3_6_BCM88732_A0fmt_fields, 18702 /* bits */ 33, 18703 /* flags */ 0, 18704 }, 18705 #endif /* chips */ 18706 18707 #if defined(BCM_53400_A0) 18708 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_7_BCM53400_A0fmt */ 18709 /* format IFP_SINGLE_WIDE_F3_7fmt */ 18710 /* nFields */ 3, 18711 /* *fields */ soc_IFP_SINGLE_WIDE_F3_7_BCM53400_A0fmt_fields, 18712 /* bits */ 37, 18713 /* flags */ 0, 18714 }, 18715 #endif /* chips */ 18716 18717 #if defined(BCM_53540_A0) 18718 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_7_BCM53540_A0fmt */ 18719 /* format IFP_SINGLE_WIDE_F3_7fmt */ 18720 /* nFields */ 3, 18721 /* *fields */ soc_IFP_SINGLE_WIDE_F3_7_BCM53400_A0fmt_fields, 18722 /* bits */ 37, 18723 /* flags */ 0, 18724 }, 18725 #endif /* chips */ 18726 18727 #if defined(BCM_53570_A0) 18728 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_7_BCM53570_A0fmt */ 18729 /* format IFP_SINGLE_WIDE_F3_7fmt */ 18730 /* nFields */ 3, 18731 /* *fields */ soc_IFP_SINGLE_WIDE_F3_7_BCM53570_A0fmt_fields, 18732 /* bits */ 39, 18733 /* flags */ 0, 18734 }, 18735 #endif /* chips */ 18736 18737 #if defined(BCM_53570_B0) 18738 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_7_BCM53570_B0fmt */ 18739 /* format IFP_SINGLE_WIDE_F3_7fmt */ 18740 /* nFields */ 3, 18741 /* *fields */ soc_IFP_SINGLE_WIDE_F3_7_BCM53570_A0fmt_fields, 18742 /* bits */ 39, 18743 /* flags */ 0, 18744 }, 18745 #endif /* chips */ 18746 18747 #if defined(BCM_56142_A0) 18748 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_7_BCM56142_A0fmt */ 18749 /* format IFP_SINGLE_WIDE_F3_7fmt */ 18750 /* nFields */ 3, 18751 /* *fields */ soc_IFP_SINGLE_WIDE_F3_7_BCM56634_A0fmt_fields, 18752 /* bits */ 37, 18753 /* flags */ 0, 18754 }, 18755 #endif /* chips */ 18756 18757 #if defined(BCM_56150_A0) 18758 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_7_BCM56150_A0fmt */ 18759 /* format IFP_SINGLE_WIDE_F3_7fmt */ 18760 /* nFields */ 3, 18761 /* *fields */ soc_IFP_SINGLE_WIDE_F3_7_BCM56150_A0fmt_fields, 18762 /* bits */ 37, 18763 /* flags */ 0, 18764 }, 18765 #endif /* chips */ 18766 18767 #if defined(BCM_56160_A0) 18768 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_7_BCM56160_A0fmt */ 18769 /* format IFP_SINGLE_WIDE_F3_7fmt */ 18770 /* nFields */ 3, 18771 /* *fields */ soc_IFP_SINGLE_WIDE_F3_7_BCM53400_A0fmt_fields, 18772 /* bits */ 37, 18773 /* flags */ 0, 18774 }, 18775 #endif /* chips */ 18776 18777 #if defined(BCM_56260_A0) 18778 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_7_BCM56260_A0fmt */ 18779 /* format IFP_SINGLE_WIDE_F3_7fmt */ 18780 /* nFields */ 3, 18781 /* *fields */ soc_IFP_SINGLE_WIDE_F3_7_BCM56260_A0fmt_fields, 18782 /* bits */ 40, 18783 /* flags */ 0, 18784 }, 18785 #endif /* chips */ 18786 18787 #if defined(BCM_56260_B0) 18788 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_7_BCM56260_B0fmt */ 18789 /* format IFP_SINGLE_WIDE_F3_7fmt */ 18790 /* nFields */ 3, 18791 /* *fields */ soc_IFP_SINGLE_WIDE_F3_7_BCM56260_A0fmt_fields, 18792 /* bits */ 40, 18793 /* flags */ 0, 18794 }, 18795 #endif /* chips */ 18796 18797 #if defined(BCM_56270_A0) 18798 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_7_BCM56270_A0fmt */ 18799 /* format IFP_SINGLE_WIDE_F3_7fmt */ 18800 /* nFields */ 3, 18801 /* *fields */ soc_IFP_SINGLE_WIDE_F3_7_BCM56260_A0fmt_fields, 18802 /* bits */ 40, 18803 /* flags */ 0, 18804 }, 18805 #endif /* chips */ 18806 18807 #if defined(BCM_56334_A0) 18808 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_7_BCM56334_A0fmt */ 18809 /* format IFP_SINGLE_WIDE_F3_7fmt */ 18810 /* nFields */ 3, 18811 /* *fields */ soc_IFP_SINGLE_WIDE_F3_7_BCM56634_A0fmt_fields, 18812 /* bits */ 37, 18813 /* flags */ 0, 18814 }, 18815 #endif /* chips */ 18816 18817 #if defined(BCM_56334_B0) 18818 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_7_BCM56334_B0fmt */ 18819 /* format IFP_SINGLE_WIDE_F3_7fmt */ 18820 /* nFields */ 3, 18821 /* *fields */ soc_IFP_SINGLE_WIDE_F3_7_BCM56634_A0fmt_fields, 18822 /* bits */ 37, 18823 /* flags */ 0, 18824 }, 18825 #endif /* chips */ 18826 18827 #if defined(BCM_56340_A0) 18828 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_7_BCM56340_A0fmt */ 18829 /* format IFP_SINGLE_WIDE_F3_7fmt */ 18830 /* nFields */ 3, 18831 /* *fields */ soc_IFP_SINGLE_WIDE_F3_7_BCM56640_A0fmt_fields, 18832 /* bits */ 49, 18833 /* flags */ 0, 18834 }, 18835 #endif /* chips */ 18836 18837 #if defined(BCM_56440_A0) 18838 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_7_BCM56440_A0fmt */ 18839 /* format IFP_SINGLE_WIDE_F3_7fmt */ 18840 /* nFields */ 3, 18841 /* *fields */ soc_IFP_SINGLE_WIDE_F3_7_BCM56840_A0fmt_fields, 18842 /* bits */ 39, 18843 /* flags */ 0, 18844 }, 18845 #endif /* chips */ 18846 18847 #if defined(BCM_56440_B0) 18848 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_7_BCM56440_B0fmt */ 18849 /* format IFP_SINGLE_WIDE_F3_7fmt */ 18850 /* nFields */ 3, 18851 /* *fields */ soc_IFP_SINGLE_WIDE_F3_7_BCM56840_A0fmt_fields, 18852 /* bits */ 39, 18853 /* flags */ 0, 18854 }, 18855 #endif /* chips */ 18856 18857 #if defined(BCM_56450_A0) 18858 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_7_BCM56450_A0fmt */ 18859 /* format IFP_SINGLE_WIDE_F3_7fmt */ 18860 /* nFields */ 3, 18861 /* *fields */ soc_IFP_SINGLE_WIDE_F3_7_BCM56450_A0fmt_fields, 18862 /* bits */ 40, 18863 /* flags */ 0, 18864 }, 18865 #endif /* chips */ 18866 18867 #if defined(BCM_56450_B0) 18868 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_7_BCM56450_B0fmt */ 18869 /* format IFP_SINGLE_WIDE_F3_7fmt */ 18870 /* nFields */ 3, 18871 /* *fields */ soc_IFP_SINGLE_WIDE_F3_7_BCM56450_A0fmt_fields, 18872 /* bits */ 40, 18873 /* flags */ 0, 18874 }, 18875 #endif /* chips */ 18876 18877 #if defined(BCM_56450_B1) 18878 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_7_BCM56450_B1fmt */ 18879 /* format IFP_SINGLE_WIDE_F3_7fmt */ 18880 /* nFields */ 3, 18881 /* *fields */ soc_IFP_SINGLE_WIDE_F3_7_BCM56450_A0fmt_fields, 18882 /* bits */ 40, 18883 /* flags */ 0, 18884 }, 18885 #endif /* chips */ 18886 18887 #if defined(BCM_56524_A0) 18888 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_7_BCM56524_A0fmt */ 18889 /* format IFP_SINGLE_WIDE_F3_7fmt */ 18890 /* nFields */ 3, 18891 /* *fields */ soc_IFP_SINGLE_WIDE_F3_7_BCM56634_A0fmt_fields, 18892 /* bits */ 37, 18893 /* flags */ 0, 18894 }, 18895 #endif /* chips */ 18896 18897 #if defined(BCM_56524_B0) 18898 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_7_BCM56524_B0fmt */ 18899 /* format IFP_SINGLE_WIDE_F3_7fmt */ 18900 /* nFields */ 3, 18901 /* *fields */ soc_IFP_SINGLE_WIDE_F3_7_BCM56634_A0fmt_fields, 18902 /* bits */ 37, 18903 /* flags */ 0, 18904 }, 18905 #endif /* chips */ 18906 18907 #if defined(BCM_56560_A0) 18908 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_7_BCM56560_A0fmt */ 18909 /* format IFP_SINGLE_WIDE_F3_7fmt */ 18910 /* nFields */ 3, 18911 /* *fields */ soc_IFP_SINGLE_WIDE_F3_7_BCM56560_A0fmt_fields, 18912 /* bits */ 49, 18913 /* flags */ 0, 18914 }, 18915 #endif /* chips */ 18916 18917 #if defined(BCM_56560_B0) 18918 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_7_BCM56560_B0fmt */ 18919 /* format IFP_SINGLE_WIDE_F3_7fmt */ 18920 /* nFields */ 3, 18921 /* *fields */ soc_IFP_SINGLE_WIDE_F3_7_BCM56560_A0fmt_fields, 18922 /* bits */ 49, 18923 /* flags */ 0, 18924 }, 18925 #endif /* chips */ 18926 18927 #if defined(BCM_56634_A0) 18928 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_7_BCM56634_A0fmt */ 18929 /* format IFP_SINGLE_WIDE_F3_7fmt */ 18930 /* nFields */ 3, 18931 /* *fields */ soc_IFP_SINGLE_WIDE_F3_7_BCM56634_A0fmt_fields, 18932 /* bits */ 37, 18933 /* flags */ 0, 18934 }, 18935 #endif /* chips */ 18936 18937 #if defined(BCM_56634_B0) 18938 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_7_BCM56634_B0fmt */ 18939 /* format IFP_SINGLE_WIDE_F3_7fmt */ 18940 /* nFields */ 3, 18941 /* *fields */ soc_IFP_SINGLE_WIDE_F3_7_BCM56634_A0fmt_fields, 18942 /* bits */ 37, 18943 /* flags */ 0, 18944 }, 18945 #endif /* chips */ 18946 18947 #if defined(BCM_56640_A0) 18948 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_7_BCM56640_A0fmt */ 18949 /* format IFP_SINGLE_WIDE_F3_7fmt */ 18950 /* nFields */ 3, 18951 /* *fields */ soc_IFP_SINGLE_WIDE_F3_7_BCM56640_A0fmt_fields, 18952 /* bits */ 49, 18953 /* flags */ 0, 18954 }, 18955 #endif /* chips */ 18956 18957 #if defined(BCM_56670_A0) 18958 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_7_BCM56670_A0fmt */ 18959 /* format IFP_SINGLE_WIDE_F3_7fmt */ 18960 /* nFields */ 3, 18961 /* *fields */ soc_IFP_SINGLE_WIDE_F3_7_BCM56560_A0fmt_fields, 18962 /* bits */ 49, 18963 /* flags */ 0, 18964 }, 18965 #endif /* chips */ 18966 18967 #if defined(BCM_56670_B0) 18968 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_7_BCM56670_B0fmt */ 18969 /* format IFP_SINGLE_WIDE_F3_7fmt */ 18970 /* nFields */ 3, 18971 /* *fields */ soc_IFP_SINGLE_WIDE_F3_7_BCM56560_A0fmt_fields, 18972 /* bits */ 49, 18973 /* flags */ 0, 18974 }, 18975 #endif /* chips */ 18976 18977 #if defined(BCM_56680_B0) 18978 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_7_BCM56680_B0fmt */ 18979 /* format IFP_SINGLE_WIDE_F3_7fmt */ 18980 /* nFields */ 2, 18981 /* *fields */ soc_IFP_SINGLE_WIDE_F3_7fmt_fields, 18982 /* bits */ 32, 18983 /* flags */ 0, 18984 }, 18985 #endif /* chips */ 18986 18987 #if defined(BCM_56685_A0) 18988 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_7_BCM56685_A0fmt */ 18989 /* format IFP_SINGLE_WIDE_F3_7fmt */ 18990 /* nFields */ 3, 18991 /* *fields */ soc_IFP_SINGLE_WIDE_F3_7_BCM56634_A0fmt_fields, 18992 /* bits */ 37, 18993 /* flags */ 0, 18994 }, 18995 #endif /* chips */ 18996 18997 #if defined(BCM_56685_B0) 18998 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_7_BCM56685_B0fmt */ 18999 /* format IFP_SINGLE_WIDE_F3_7fmt */ 19000 /* nFields */ 3, 19001 /* *fields */ soc_IFP_SINGLE_WIDE_F3_7_BCM56634_A0fmt_fields, 19002 /* bits */ 37, 19003 /* flags */ 0, 19004 }, 19005 #endif /* chips */ 19006 19007 #if defined(BCM_56725_A0) 19008 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_7_BCM56725_A0fmt */ 19009 /* format IFP_SINGLE_WIDE_F3_7fmt */ 19010 /* nFields */ 3, 19011 /* *fields */ soc_IFP_SINGLE_WIDE_F3_7_BCM56820_A0fmt_fields, 19012 /* bits */ 33, 19013 /* flags */ 0, 19014 }, 19015 #endif /* chips */ 19016 19017 #if defined(BCM_56820_A0) 19018 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_7_BCM56820_A0fmt */ 19019 /* format IFP_SINGLE_WIDE_F3_7fmt */ 19020 /* nFields */ 3, 19021 /* *fields */ soc_IFP_SINGLE_WIDE_F3_7_BCM56820_A0fmt_fields, 19022 /* bits */ 33, 19023 /* flags */ 0, 19024 }, 19025 #endif /* chips */ 19026 19027 #if defined(BCM_56840_A0) 19028 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_7_BCM56840_A0fmt */ 19029 /* format IFP_SINGLE_WIDE_F3_7fmt */ 19030 /* nFields */ 3, 19031 /* *fields */ soc_IFP_SINGLE_WIDE_F3_7_BCM56840_A0fmt_fields, 19032 /* bits */ 39, 19033 /* flags */ 0, 19034 }, 19035 #endif /* chips */ 19036 19037 #if defined(BCM_56840_B0) 19038 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_7_BCM56840_B0fmt */ 19039 /* format IFP_SINGLE_WIDE_F3_7fmt */ 19040 /* nFields */ 3, 19041 /* *fields */ soc_IFP_SINGLE_WIDE_F3_7_BCM56840_A0fmt_fields, 19042 /* bits */ 39, 19043 /* flags */ 0, 19044 }, 19045 #endif /* chips */ 19046 19047 #if defined(BCM_56850_A0) 19048 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_7_BCM56850_A0fmt */ 19049 /* format IFP_SINGLE_WIDE_F3_7fmt */ 19050 /* nFields */ 3, 19051 /* *fields */ soc_IFP_SINGLE_WIDE_F3_7_BCM56640_A0fmt_fields, 19052 /* bits */ 49, 19053 /* flags */ 0, 19054 }, 19055 #endif /* chips */ 19056 19057 #if defined(BCM_56860_A0) 19058 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_7_BCM56860_A0fmt */ 19059 /* format IFP_SINGLE_WIDE_F3_7fmt */ 19060 /* nFields */ 3, 19061 /* *fields */ soc_IFP_SINGLE_WIDE_F3_7_BCM56640_A0fmt_fields, 19062 /* bits */ 49, 19063 /* flags */ 0, 19064 }, 19065 #endif /* chips */ 19066 19067 #if defined(BCM_88732_A0) 19068 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_7_BCM88732_A0fmt */ 19069 /* format IFP_SINGLE_WIDE_F3_7fmt */ 19070 /* nFields */ 3, 19071 /* *fields */ soc_IFP_SINGLE_WIDE_F3_7_BCM88732_A0fmt_fields, 19072 /* bits */ 33, 19073 /* flags */ 0, 19074 }, 19075 #endif /* chips */ 19076 19077 #if defined(BCM_53400_A0) 19078 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_8_BCM53400_A0fmt */ 19079 /* format IFP_SINGLE_WIDE_F3_8fmt */ 19080 /* nFields */ 6, 19081 /* *fields */ soc_IFP_SINGLE_WIDE_F3_8_BCM53400_A0fmt_fields, 19082 /* bits */ 37, 19083 /* flags */ 0, 19084 }, 19085 #endif /* chips */ 19086 19087 #if defined(BCM_53540_A0) 19088 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_8_BCM53540_A0fmt */ 19089 /* format IFP_SINGLE_WIDE_F3_8fmt */ 19090 /* nFields */ 6, 19091 /* *fields */ soc_IFP_SINGLE_WIDE_F3_8_BCM53400_A0fmt_fields, 19092 /* bits */ 37, 19093 /* flags */ 0, 19094 }, 19095 #endif /* chips */ 19096 19097 #if defined(BCM_53570_A0) 19098 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_8_BCM53570_A0fmt */ 19099 /* format IFP_SINGLE_WIDE_F3_8fmt */ 19100 /* nFields */ 6, 19101 /* *fields */ soc_IFP_SINGLE_WIDE_F3_8_BCM53570_A0fmt_fields, 19102 /* bits */ 39, 19103 /* flags */ 0, 19104 }, 19105 #endif /* chips */ 19106 19107 #if defined(BCM_53570_B0) 19108 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_8_BCM53570_B0fmt */ 19109 /* format IFP_SINGLE_WIDE_F3_8fmt */ 19110 /* nFields */ 6, 19111 /* *fields */ soc_IFP_SINGLE_WIDE_F3_8_BCM53570_A0fmt_fields, 19112 /* bits */ 39, 19113 /* flags */ 0, 19114 }, 19115 #endif /* chips */ 19116 19117 #if defined(BCM_56142_A0) 19118 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_8_BCM56142_A0fmt */ 19119 /* format IFP_SINGLE_WIDE_F3_8fmt */ 19120 /* nFields */ 6, 19121 /* *fields */ soc_IFP_SINGLE_WIDE_F3_8_BCM56634_A0fmt_fields, 19122 /* bits */ 37, 19123 /* flags */ 0, 19124 }, 19125 #endif /* chips */ 19126 19127 #if defined(BCM_56150_A0) 19128 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_8_BCM56150_A0fmt */ 19129 /* format IFP_SINGLE_WIDE_F3_8fmt */ 19130 /* nFields */ 6, 19131 /* *fields */ soc_IFP_SINGLE_WIDE_F3_8_BCM56150_A0fmt_fields, 19132 /* bits */ 37, 19133 /* flags */ 0, 19134 }, 19135 #endif /* chips */ 19136 19137 #if defined(BCM_56160_A0) 19138 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_8_BCM56160_A0fmt */ 19139 /* format IFP_SINGLE_WIDE_F3_8fmt */ 19140 /* nFields */ 6, 19141 /* *fields */ soc_IFP_SINGLE_WIDE_F3_8_BCM53400_A0fmt_fields, 19142 /* bits */ 37, 19143 /* flags */ 0, 19144 }, 19145 #endif /* chips */ 19146 19147 #if defined(BCM_56260_A0) 19148 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_8_BCM56260_A0fmt */ 19149 /* format IFP_SINGLE_WIDE_F3_8fmt */ 19150 /* nFields */ 6, 19151 /* *fields */ soc_IFP_SINGLE_WIDE_F3_8_BCM56260_A0fmt_fields, 19152 /* bits */ 40, 19153 /* flags */ 0, 19154 }, 19155 #endif /* chips */ 19156 19157 #if defined(BCM_56260_B0) 19158 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_8_BCM56260_B0fmt */ 19159 /* format IFP_SINGLE_WIDE_F3_8fmt */ 19160 /* nFields */ 6, 19161 /* *fields */ soc_IFP_SINGLE_WIDE_F3_8_BCM56260_A0fmt_fields, 19162 /* bits */ 40, 19163 /* flags */ 0, 19164 }, 19165 #endif /* chips */ 19166 19167 #if defined(BCM_56270_A0) 19168 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_8_BCM56270_A0fmt */ 19169 /* format IFP_SINGLE_WIDE_F3_8fmt */ 19170 /* nFields */ 6, 19171 /* *fields */ soc_IFP_SINGLE_WIDE_F3_8_BCM56260_A0fmt_fields, 19172 /* bits */ 40, 19173 /* flags */ 0, 19174 }, 19175 #endif /* chips */ 19176 19177 #if defined(BCM_56334_A0) 19178 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_8_BCM56334_A0fmt */ 19179 /* format IFP_SINGLE_WIDE_F3_8fmt */ 19180 /* nFields */ 6, 19181 /* *fields */ soc_IFP_SINGLE_WIDE_F3_8_BCM56634_A0fmt_fields, 19182 /* bits */ 37, 19183 /* flags */ 0, 19184 }, 19185 #endif /* chips */ 19186 19187 #if defined(BCM_56334_B0) 19188 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_8_BCM56334_B0fmt */ 19189 /* format IFP_SINGLE_WIDE_F3_8fmt */ 19190 /* nFields */ 6, 19191 /* *fields */ soc_IFP_SINGLE_WIDE_F3_8_BCM56634_A0fmt_fields, 19192 /* bits */ 37, 19193 /* flags */ 0, 19194 }, 19195 #endif /* chips */ 19196 19197 #if defined(BCM_56340_A0) 19198 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_8_BCM56340_A0fmt */ 19199 /* format IFP_SINGLE_WIDE_F3_8fmt */ 19200 /* nFields */ 6, 19201 /* *fields */ soc_IFP_SINGLE_WIDE_F3_8_BCM56640_A0fmt_fields, 19202 /* bits */ 49, 19203 /* flags */ 0, 19204 }, 19205 #endif /* chips */ 19206 19207 #if defined(BCM_56440_A0) 19208 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_8_BCM56440_A0fmt */ 19209 /* format IFP_SINGLE_WIDE_F3_8fmt */ 19210 /* nFields */ 6, 19211 /* *fields */ soc_IFP_SINGLE_WIDE_F3_8_BCM56840_A0fmt_fields, 19212 /* bits */ 39, 19213 /* flags */ 0, 19214 }, 19215 #endif /* chips */ 19216 19217 #if defined(BCM_56440_B0) 19218 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_8_BCM56440_B0fmt */ 19219 /* format IFP_SINGLE_WIDE_F3_8fmt */ 19220 /* nFields */ 6, 19221 /* *fields */ soc_IFP_SINGLE_WIDE_F3_8_BCM56840_A0fmt_fields, 19222 /* bits */ 39, 19223 /* flags */ 0, 19224 }, 19225 #endif /* chips */ 19226 19227 #if defined(BCM_56450_A0) 19228 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_8_BCM56450_A0fmt */ 19229 /* format IFP_SINGLE_WIDE_F3_8fmt */ 19230 /* nFields */ 6, 19231 /* *fields */ soc_IFP_SINGLE_WIDE_F3_8_BCM56450_A0fmt_fields, 19232 /* bits */ 40, 19233 /* flags */ 0, 19234 }, 19235 #endif /* chips */ 19236 19237 #if defined(BCM_56450_B0) 19238 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_8_BCM56450_B0fmt */ 19239 /* format IFP_SINGLE_WIDE_F3_8fmt */ 19240 /* nFields */ 6, 19241 /* *fields */ soc_IFP_SINGLE_WIDE_F3_8_BCM56450_A0fmt_fields, 19242 /* bits */ 40, 19243 /* flags */ 0, 19244 }, 19245 #endif /* chips */ 19246 19247 #if defined(BCM_56450_B1) 19248 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_8_BCM56450_B1fmt */ 19249 /* format IFP_SINGLE_WIDE_F3_8fmt */ 19250 /* nFields */ 6, 19251 /* *fields */ soc_IFP_SINGLE_WIDE_F3_8_BCM56450_A0fmt_fields, 19252 /* bits */ 40, 19253 /* flags */ 0, 19254 }, 19255 #endif /* chips */ 19256 19257 #if defined(BCM_56524_A0) 19258 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_8_BCM56524_A0fmt */ 19259 /* format IFP_SINGLE_WIDE_F3_8fmt */ 19260 /* nFields */ 6, 19261 /* *fields */ soc_IFP_SINGLE_WIDE_F3_8_BCM56634_A0fmt_fields, 19262 /* bits */ 37, 19263 /* flags */ 0, 19264 }, 19265 #endif /* chips */ 19266 19267 #if defined(BCM_56524_B0) 19268 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_8_BCM56524_B0fmt */ 19269 /* format IFP_SINGLE_WIDE_F3_8fmt */ 19270 /* nFields */ 6, 19271 /* *fields */ soc_IFP_SINGLE_WIDE_F3_8_BCM56634_A0fmt_fields, 19272 /* bits */ 37, 19273 /* flags */ 0, 19274 }, 19275 #endif /* chips */ 19276 19277 #if defined(BCM_56560_A0) 19278 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_8_BCM56560_A0fmt */ 19279 /* format IFP_SINGLE_WIDE_F3_8fmt */ 19280 /* nFields */ 6, 19281 /* *fields */ soc_IFP_SINGLE_WIDE_F3_8_BCM56560_A0fmt_fields, 19282 /* bits */ 49, 19283 /* flags */ 0, 19284 }, 19285 #endif /* chips */ 19286 19287 #if defined(BCM_56560_B0) 19288 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_8_BCM56560_B0fmt */ 19289 /* format IFP_SINGLE_WIDE_F3_8fmt */ 19290 /* nFields */ 6, 19291 /* *fields */ soc_IFP_SINGLE_WIDE_F3_8_BCM56560_A0fmt_fields, 19292 /* bits */ 49, 19293 /* flags */ 0, 19294 }, 19295 #endif /* chips */ 19296 19297 #if defined(BCM_56634_A0) 19298 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_8_BCM56634_A0fmt */ 19299 /* format IFP_SINGLE_WIDE_F3_8fmt */ 19300 /* nFields */ 6, 19301 /* *fields */ soc_IFP_SINGLE_WIDE_F3_8_BCM56634_A0fmt_fields, 19302 /* bits */ 37, 19303 /* flags */ 0, 19304 }, 19305 #endif /* chips */ 19306 19307 #if defined(BCM_56634_B0) 19308 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_8_BCM56634_B0fmt */ 19309 /* format IFP_SINGLE_WIDE_F3_8fmt */ 19310 /* nFields */ 6, 19311 /* *fields */ soc_IFP_SINGLE_WIDE_F3_8_BCM56634_A0fmt_fields, 19312 /* bits */ 37, 19313 /* flags */ 0, 19314 }, 19315 #endif /* chips */ 19316 19317 #if defined(BCM_56640_A0) 19318 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_8_BCM56640_A0fmt */ 19319 /* format IFP_SINGLE_WIDE_F3_8fmt */ 19320 /* nFields */ 6, 19321 /* *fields */ soc_IFP_SINGLE_WIDE_F3_8_BCM56640_A0fmt_fields, 19322 /* bits */ 49, 19323 /* flags */ 0, 19324 }, 19325 #endif /* chips */ 19326 19327 #if defined(BCM_56670_A0) 19328 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_8_BCM56670_A0fmt */ 19329 /* format IFP_SINGLE_WIDE_F3_8fmt */ 19330 /* nFields */ 6, 19331 /* *fields */ soc_IFP_SINGLE_WIDE_F3_8_BCM56560_A0fmt_fields, 19332 /* bits */ 49, 19333 /* flags */ 0, 19334 }, 19335 #endif /* chips */ 19336 19337 #if defined(BCM_56670_B0) 19338 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_8_BCM56670_B0fmt */ 19339 /* format IFP_SINGLE_WIDE_F3_8fmt */ 19340 /* nFields */ 6, 19341 /* *fields */ soc_IFP_SINGLE_WIDE_F3_8_BCM56560_A0fmt_fields, 19342 /* bits */ 49, 19343 /* flags */ 0, 19344 }, 19345 #endif /* chips */ 19346 19347 #if defined(BCM_56680_B0) 19348 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_8_BCM56680_B0fmt */ 19349 /* format IFP_SINGLE_WIDE_F3_8fmt */ 19350 /* nFields */ 5, 19351 /* *fields */ soc_IFP_SINGLE_WIDE_F3_8fmt_fields, 19352 /* bits */ 32, 19353 /* flags */ 0, 19354 }, 19355 #endif /* chips */ 19356 19357 #if defined(BCM_56685_A0) 19358 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_8_BCM56685_A0fmt */ 19359 /* format IFP_SINGLE_WIDE_F3_8fmt */ 19360 /* nFields */ 6, 19361 /* *fields */ soc_IFP_SINGLE_WIDE_F3_8_BCM56634_A0fmt_fields, 19362 /* bits */ 37, 19363 /* flags */ 0, 19364 }, 19365 #endif /* chips */ 19366 19367 #if defined(BCM_56685_B0) 19368 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_8_BCM56685_B0fmt */ 19369 /* format IFP_SINGLE_WIDE_F3_8fmt */ 19370 /* nFields */ 6, 19371 /* *fields */ soc_IFP_SINGLE_WIDE_F3_8_BCM56634_A0fmt_fields, 19372 /* bits */ 37, 19373 /* flags */ 0, 19374 }, 19375 #endif /* chips */ 19376 19377 #if defined(BCM_56725_A0) 19378 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_8_BCM56725_A0fmt */ 19379 /* format IFP_SINGLE_WIDE_F3_8fmt */ 19380 /* nFields */ 5, 19381 /* *fields */ soc_IFP_SINGLE_WIDE_F3_8_BCM56820_A0fmt_fields, 19382 /* bits */ 33, 19383 /* flags */ 0, 19384 }, 19385 #endif /* chips */ 19386 19387 #if defined(BCM_56820_A0) 19388 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_8_BCM56820_A0fmt */ 19389 /* format IFP_SINGLE_WIDE_F3_8fmt */ 19390 /* nFields */ 5, 19391 /* *fields */ soc_IFP_SINGLE_WIDE_F3_8_BCM56820_A0fmt_fields, 19392 /* bits */ 33, 19393 /* flags */ 0, 19394 }, 19395 #endif /* chips */ 19396 19397 #if defined(BCM_56840_A0) 19398 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_8_BCM56840_A0fmt */ 19399 /* format IFP_SINGLE_WIDE_F3_8fmt */ 19400 /* nFields */ 6, 19401 /* *fields */ soc_IFP_SINGLE_WIDE_F3_8_BCM56840_A0fmt_fields, 19402 /* bits */ 39, 19403 /* flags */ 0, 19404 }, 19405 #endif /* chips */ 19406 19407 #if defined(BCM_56840_B0) 19408 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_8_BCM56840_B0fmt */ 19409 /* format IFP_SINGLE_WIDE_F3_8fmt */ 19410 /* nFields */ 6, 19411 /* *fields */ soc_IFP_SINGLE_WIDE_F3_8_BCM56840_A0fmt_fields, 19412 /* bits */ 39, 19413 /* flags */ 0, 19414 }, 19415 #endif /* chips */ 19416 19417 #if defined(BCM_56850_A0) 19418 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_8_BCM56850_A0fmt */ 19419 /* format IFP_SINGLE_WIDE_F3_8fmt */ 19420 /* nFields */ 6, 19421 /* *fields */ soc_IFP_SINGLE_WIDE_F3_8_BCM56640_A0fmt_fields, 19422 /* bits */ 49, 19423 /* flags */ 0, 19424 }, 19425 #endif /* chips */ 19426 19427 #if defined(BCM_56860_A0) 19428 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_8_BCM56860_A0fmt */ 19429 /* format IFP_SINGLE_WIDE_F3_8fmt */ 19430 /* nFields */ 6, 19431 /* *fields */ soc_IFP_SINGLE_WIDE_F3_8_BCM56640_A0fmt_fields, 19432 /* bits */ 49, 19433 /* flags */ 0, 19434 }, 19435 #endif /* chips */ 19436 19437 #if defined(BCM_88732_A0) 19438 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_8_BCM88732_A0fmt */ 19439 /* format IFP_SINGLE_WIDE_F3_8fmt */ 19440 /* nFields */ 5, 19441 /* *fields */ soc_IFP_SINGLE_WIDE_F3_8_BCM88732_A0fmt_fields, 19442 /* bits */ 33, 19443 /* flags */ 0, 19444 }, 19445 #endif /* chips */ 19446 19447 #if defined(BCM_53400_A0) 19448 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_9_BCM53400_A0fmt */ 19449 /* format IFP_SINGLE_WIDE_F3_9fmt */ 19450 /* nFields */ 3, 19451 /* *fields */ soc_IFP_SINGLE_WIDE_F3_9_BCM53400_A0fmt_fields, 19452 /* bits */ 37, 19453 /* flags */ 0, 19454 }, 19455 #endif /* chips */ 19456 19457 #if defined(BCM_53540_A0) 19458 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_9_BCM53540_A0fmt */ 19459 /* format IFP_SINGLE_WIDE_F3_9fmt */ 19460 /* nFields */ 3, 19461 /* *fields */ soc_IFP_SINGLE_WIDE_F3_9_BCM53400_A0fmt_fields, 19462 /* bits */ 37, 19463 /* flags */ 0, 19464 }, 19465 #endif /* chips */ 19466 19467 #if defined(BCM_53570_A0) 19468 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_9_BCM53570_A0fmt */ 19469 /* format IFP_SINGLE_WIDE_F3_9fmt */ 19470 /* nFields */ 3, 19471 /* *fields */ soc_IFP_SINGLE_WIDE_F3_9_BCM53570_A0fmt_fields, 19472 /* bits */ 39, 19473 /* flags */ 0, 19474 }, 19475 #endif /* chips */ 19476 19477 #if defined(BCM_53570_B0) 19478 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_9_BCM53570_B0fmt */ 19479 /* format IFP_SINGLE_WIDE_F3_9fmt */ 19480 /* nFields */ 3, 19481 /* *fields */ soc_IFP_SINGLE_WIDE_F3_9_BCM53570_A0fmt_fields, 19482 /* bits */ 39, 19483 /* flags */ 0, 19484 }, 19485 #endif /* chips */ 19486 19487 #if defined(BCM_56142_A0) 19488 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_9_BCM56142_A0fmt */ 19489 /* format IFP_SINGLE_WIDE_F3_9fmt */ 19490 /* nFields */ 3, 19491 /* *fields */ soc_IFP_SINGLE_WIDE_F3_9_BCM56334_A0fmt_fields, 19492 /* bits */ 37, 19493 /* flags */ 0, 19494 }, 19495 #endif /* chips */ 19496 19497 #if defined(BCM_56150_A0) 19498 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_9_BCM56150_A0fmt */ 19499 /* format IFP_SINGLE_WIDE_F3_9fmt */ 19500 /* nFields */ 3, 19501 /* *fields */ soc_IFP_SINGLE_WIDE_F3_9_BCM56150_A0fmt_fields, 19502 /* bits */ 37, 19503 /* flags */ 0, 19504 }, 19505 #endif /* chips */ 19506 19507 #if defined(BCM_56160_A0) 19508 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_9_BCM56160_A0fmt */ 19509 /* format IFP_SINGLE_WIDE_F3_9fmt */ 19510 /* nFields */ 3, 19511 /* *fields */ soc_IFP_SINGLE_WIDE_F3_9_BCM53400_A0fmt_fields, 19512 /* bits */ 37, 19513 /* flags */ 0, 19514 }, 19515 #endif /* chips */ 19516 19517 #if defined(BCM_56260_A0) 19518 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_9_BCM56260_A0fmt */ 19519 /* format IFP_SINGLE_WIDE_F3_9fmt */ 19520 /* nFields */ 5, 19521 /* *fields */ soc_IFP_SINGLE_WIDE_F3_9_BCM56260_A0fmt_fields, 19522 /* bits */ 40, 19523 /* flags */ 0, 19524 }, 19525 #endif /* chips */ 19526 19527 #if defined(BCM_56260_B0) 19528 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_9_BCM56260_B0fmt */ 19529 /* format IFP_SINGLE_WIDE_F3_9fmt */ 19530 /* nFields */ 5, 19531 /* *fields */ soc_IFP_SINGLE_WIDE_F3_9_BCM56260_A0fmt_fields, 19532 /* bits */ 40, 19533 /* flags */ 0, 19534 }, 19535 #endif /* chips */ 19536 19537 #if defined(BCM_56270_A0) 19538 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_9_BCM56270_A0fmt */ 19539 /* format IFP_SINGLE_WIDE_F3_9fmt */ 19540 /* nFields */ 5, 19541 /* *fields */ soc_IFP_SINGLE_WIDE_F3_9_BCM56260_A0fmt_fields, 19542 /* bits */ 40, 19543 /* flags */ 0, 19544 }, 19545 #endif /* chips */ 19546 19547 #if defined(BCM_56334_A0) 19548 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_9_BCM56334_A0fmt */ 19549 /* format IFP_SINGLE_WIDE_F3_9fmt */ 19550 /* nFields */ 3, 19551 /* *fields */ soc_IFP_SINGLE_WIDE_F3_9_BCM56334_A0fmt_fields, 19552 /* bits */ 37, 19553 /* flags */ 0, 19554 }, 19555 #endif /* chips */ 19556 19557 #if defined(BCM_56334_B0) 19558 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_9_BCM56334_B0fmt */ 19559 /* format IFP_SINGLE_WIDE_F3_9fmt */ 19560 /* nFields */ 3, 19561 /* *fields */ soc_IFP_SINGLE_WIDE_F3_9_BCM56334_A0fmt_fields, 19562 /* bits */ 37, 19563 /* flags */ 0, 19564 }, 19565 #endif /* chips */ 19566 19567 #if defined(BCM_56340_A0) 19568 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_9_BCM56340_A0fmt */ 19569 /* format IFP_SINGLE_WIDE_F3_9fmt */ 19570 /* nFields */ 4, 19571 /* *fields */ soc_IFP_SINGLE_WIDE_F3_9_BCM56640_A0fmt_fields, 19572 /* bits */ 49, 19573 /* flags */ 0, 19574 }, 19575 #endif /* chips */ 19576 19577 #if defined(BCM_56440_A0) 19578 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_9_BCM56440_A0fmt */ 19579 /* format IFP_SINGLE_WIDE_F3_9fmt */ 19580 /* nFields */ 4, 19581 /* *fields */ soc_IFP_SINGLE_WIDE_F3_9_BCM56840_A0fmt_fields, 19582 /* bits */ 39, 19583 /* flags */ 0, 19584 }, 19585 #endif /* chips */ 19586 19587 #if defined(BCM_56440_B0) 19588 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_9_BCM56440_B0fmt */ 19589 /* format IFP_SINGLE_WIDE_F3_9fmt */ 19590 /* nFields */ 4, 19591 /* *fields */ soc_IFP_SINGLE_WIDE_F3_9_BCM56840_A0fmt_fields, 19592 /* bits */ 39, 19593 /* flags */ 0, 19594 }, 19595 #endif /* chips */ 19596 19597 #if defined(BCM_56450_A0) 19598 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_9_BCM56450_A0fmt */ 19599 /* format IFP_SINGLE_WIDE_F3_9fmt */ 19600 /* nFields */ 5, 19601 /* *fields */ soc_IFP_SINGLE_WIDE_F3_9_BCM56450_A0fmt_fields, 19602 /* bits */ 40, 19603 /* flags */ 0, 19604 }, 19605 #endif /* chips */ 19606 19607 #if defined(BCM_56450_B0) 19608 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_9_BCM56450_B0fmt */ 19609 /* format IFP_SINGLE_WIDE_F3_9fmt */ 19610 /* nFields */ 5, 19611 /* *fields */ soc_IFP_SINGLE_WIDE_F3_9_BCM56450_A0fmt_fields, 19612 /* bits */ 40, 19613 /* flags */ 0, 19614 }, 19615 #endif /* chips */ 19616 19617 #if defined(BCM_56450_B1) 19618 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_9_BCM56450_B1fmt */ 19619 /* format IFP_SINGLE_WIDE_F3_9fmt */ 19620 /* nFields */ 5, 19621 /* *fields */ soc_IFP_SINGLE_WIDE_F3_9_BCM56450_A0fmt_fields, 19622 /* bits */ 40, 19623 /* flags */ 0, 19624 }, 19625 #endif /* chips */ 19626 19627 #if defined(BCM_56524_A0) 19628 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_9_BCM56524_A0fmt */ 19629 /* format IFP_SINGLE_WIDE_F3_9fmt */ 19630 /* nFields */ 4, 19631 /* *fields */ soc_IFP_SINGLE_WIDE_F3_9fmt_fields, 19632 /* bits */ 37, 19633 /* flags */ 0, 19634 }, 19635 #endif /* chips */ 19636 19637 #if defined(BCM_56524_B0) 19638 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_9_BCM56524_B0fmt */ 19639 /* format IFP_SINGLE_WIDE_F3_9fmt */ 19640 /* nFields */ 4, 19641 /* *fields */ soc_IFP_SINGLE_WIDE_F3_9fmt_fields, 19642 /* bits */ 37, 19643 /* flags */ 0, 19644 }, 19645 #endif /* chips */ 19646 19647 #if defined(BCM_56560_A0) 19648 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_9_BCM56560_A0fmt */ 19649 /* format IFP_SINGLE_WIDE_F3_9fmt */ 19650 /* nFields */ 4, 19651 /* *fields */ soc_IFP_SINGLE_WIDE_F3_9_BCM56560_A0fmt_fields, 19652 /* bits */ 49, 19653 /* flags */ 0, 19654 }, 19655 #endif /* chips */ 19656 19657 #if defined(BCM_56560_B0) 19658 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_9_BCM56560_B0fmt */ 19659 /* format IFP_SINGLE_WIDE_F3_9fmt */ 19660 /* nFields */ 4, 19661 /* *fields */ soc_IFP_SINGLE_WIDE_F3_9_BCM56560_A0fmt_fields, 19662 /* bits */ 49, 19663 /* flags */ 0, 19664 }, 19665 #endif /* chips */ 19666 19667 #if defined(BCM_56640_A0) 19668 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_9_BCM56640_A0fmt */ 19669 /* format IFP_SINGLE_WIDE_F3_9fmt */ 19670 /* nFields */ 4, 19671 /* *fields */ soc_IFP_SINGLE_WIDE_F3_9_BCM56640_A0fmt_fields, 19672 /* bits */ 49, 19673 /* flags */ 0, 19674 }, 19675 #endif /* chips */ 19676 19677 #if defined(BCM_56670_A0) 19678 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_9_BCM56670_A0fmt */ 19679 /* format IFP_SINGLE_WIDE_F3_9fmt */ 19680 /* nFields */ 4, 19681 /* *fields */ soc_IFP_SINGLE_WIDE_F3_9_BCM56560_A0fmt_fields, 19682 /* bits */ 49, 19683 /* flags */ 0, 19684 }, 19685 #endif /* chips */ 19686 19687 #if defined(BCM_56670_B0) 19688 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_9_BCM56670_B0fmt */ 19689 /* format IFP_SINGLE_WIDE_F3_9fmt */ 19690 /* nFields */ 4, 19691 /* *fields */ soc_IFP_SINGLE_WIDE_F3_9_BCM56560_A0fmt_fields, 19692 /* bits */ 49, 19693 /* flags */ 0, 19694 }, 19695 #endif /* chips */ 19696 19697 #if defined(BCM_56685_A0) 19698 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_9_BCM56685_A0fmt */ 19699 /* format IFP_SINGLE_WIDE_F3_9fmt */ 19700 /* nFields */ 4, 19701 /* *fields */ soc_IFP_SINGLE_WIDE_F3_9fmt_fields, 19702 /* bits */ 37, 19703 /* flags */ 0, 19704 }, 19705 #endif /* chips */ 19706 19707 #if defined(BCM_56685_B0) 19708 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_9_BCM56685_B0fmt */ 19709 /* format IFP_SINGLE_WIDE_F3_9fmt */ 19710 /* nFields */ 4, 19711 /* *fields */ soc_IFP_SINGLE_WIDE_F3_9fmt_fields, 19712 /* bits */ 37, 19713 /* flags */ 0, 19714 }, 19715 #endif /* chips */ 19716 19717 #if defined(BCM_56840_A0) 19718 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_9_BCM56840_A0fmt */ 19719 /* format IFP_SINGLE_WIDE_F3_9fmt */ 19720 /* nFields */ 4, 19721 /* *fields */ soc_IFP_SINGLE_WIDE_F3_9_BCM56840_A0fmt_fields, 19722 /* bits */ 39, 19723 /* flags */ 0, 19724 }, 19725 #endif /* chips */ 19726 19727 #if defined(BCM_56840_B0) 19728 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_9_BCM56840_B0fmt */ 19729 /* format IFP_SINGLE_WIDE_F3_9fmt */ 19730 /* nFields */ 4, 19731 /* *fields */ soc_IFP_SINGLE_WIDE_F3_9_BCM56840_A0fmt_fields, 19732 /* bits */ 39, 19733 /* flags */ 0, 19734 }, 19735 #endif /* chips */ 19736 19737 #if defined(BCM_56850_A0) 19738 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_9_BCM56850_A0fmt */ 19739 /* format IFP_SINGLE_WIDE_F3_9fmt */ 19740 /* nFields */ 4, 19741 /* *fields */ soc_IFP_SINGLE_WIDE_F3_9_BCM56640_A0fmt_fields, 19742 /* bits */ 49, 19743 /* flags */ 0, 19744 }, 19745 #endif /* chips */ 19746 19747 #if defined(BCM_56860_A0) 19748 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F3_9_BCM56860_A0fmt */ 19749 /* format IFP_SINGLE_WIDE_F3_9fmt */ 19750 /* nFields */ 4, 19751 /* *fields */ soc_IFP_SINGLE_WIDE_F3_9_BCM56640_A0fmt_fields, 19752 /* bits */ 49, 19753 /* flags */ 0, 19754 }, 19755 #endif /* chips */ 19756 19757 #if defined(BCM_53400_A0) 19758 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F4_BCM53400_A0fmt */ 19759 /* format IFP_SINGLE_WIDE_F4fmt */ 19760 /* nFields */ 1, 19761 /* *fields */ soc_IFP_DOUBLE_WIDE_F4_0_BCM53400_A0fmt_fields, 19762 /* bits */ 7, 19763 /* flags */ 0, 19764 }, 19765 #endif /* chips */ 19766 19767 #if defined(BCM_53540_A0) 19768 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F4_BCM53540_A0fmt */ 19769 /* format IFP_SINGLE_WIDE_F4fmt */ 19770 /* nFields */ 1, 19771 /* *fields */ soc_IFP_DOUBLE_WIDE_F4_0_BCM53400_A0fmt_fields, 19772 /* bits */ 7, 19773 /* flags */ 0, 19774 }, 19775 #endif /* chips */ 19776 19777 #if defined(BCM_53570_A0) 19778 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F4_BCM53570_A0fmt */ 19779 /* format IFP_SINGLE_WIDE_F4fmt */ 19780 /* nFields */ 1, 19781 /* *fields */ soc_IFP_SINGLE_WIDE_F4_BCM56560_A0fmt_fields, 19782 /* bits */ 8, 19783 /* flags */ 0, 19784 }, 19785 #endif /* chips */ 19786 19787 #if defined(BCM_53570_B0) 19788 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F4_BCM53570_B0fmt */ 19789 /* format IFP_SINGLE_WIDE_F4fmt */ 19790 /* nFields */ 1, 19791 /* *fields */ soc_IFP_SINGLE_WIDE_F4_BCM56560_A0fmt_fields, 19792 /* bits */ 8, 19793 /* flags */ 0, 19794 }, 19795 #endif /* chips */ 19796 19797 #if defined(BCM_56142_A0) 19798 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F4_BCM56142_A0fmt */ 19799 /* format IFP_SINGLE_WIDE_F4fmt */ 19800 /* nFields */ 1, 19801 /* *fields */ soc_IFP_DOUBLE_WIDE_F4_0_BCM56634_A0fmt_fields, 19802 /* bits */ 7, 19803 /* flags */ 0, 19804 }, 19805 #endif /* chips */ 19806 19807 #if defined(BCM_56150_A0) 19808 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F4_BCM56150_A0fmt */ 19809 /* format IFP_SINGLE_WIDE_F4fmt */ 19810 /* nFields */ 1, 19811 /* *fields */ soc_IFP_DOUBLE_WIDE_F4_0_BCM56640_A0fmt_fields, 19812 /* bits */ 7, 19813 /* flags */ 0, 19814 }, 19815 #endif /* chips */ 19816 19817 #if defined(BCM_56160_A0) 19818 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F4_BCM56160_A0fmt */ 19819 /* format IFP_SINGLE_WIDE_F4fmt */ 19820 /* nFields */ 1, 19821 /* *fields */ soc_IFP_DOUBLE_WIDE_F4_0_BCM53400_A0fmt_fields, 19822 /* bits */ 7, 19823 /* flags */ 0, 19824 }, 19825 #endif /* chips */ 19826 19827 #if defined(BCM_56260_A0) 19828 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F4_BCM56260_A0fmt */ 19829 /* format IFP_SINGLE_WIDE_F4fmt */ 19830 /* nFields */ 1, 19831 /* *fields */ soc_IFP_SINGLE_WIDE_F4_BCM56560_A0fmt_fields, 19832 /* bits */ 8, 19833 /* flags */ 0, 19834 }, 19835 #endif /* chips */ 19836 19837 #if defined(BCM_56260_B0) 19838 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F4_BCM56260_B0fmt */ 19839 /* format IFP_SINGLE_WIDE_F4fmt */ 19840 /* nFields */ 1, 19841 /* *fields */ soc_IFP_SINGLE_WIDE_F4_BCM56560_A0fmt_fields, 19842 /* bits */ 8, 19843 /* flags */ 0, 19844 }, 19845 #endif /* chips */ 19846 19847 #if defined(BCM_56270_A0) 19848 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F4_BCM56270_A0fmt */ 19849 /* format IFP_SINGLE_WIDE_F4fmt */ 19850 /* nFields */ 1, 19851 /* *fields */ soc_IFP_SINGLE_WIDE_F4_BCM56560_A0fmt_fields, 19852 /* bits */ 8, 19853 /* flags */ 0, 19854 }, 19855 #endif /* chips */ 19856 19857 #if defined(BCM_56334_A0) 19858 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F4_BCM56334_A0fmt */ 19859 /* format IFP_SINGLE_WIDE_F4fmt */ 19860 /* nFields */ 1, 19861 /* *fields */ soc_IFP_DOUBLE_WIDE_F4_0_BCM56634_A0fmt_fields, 19862 /* bits */ 7, 19863 /* flags */ 0, 19864 }, 19865 #endif /* chips */ 19866 19867 #if defined(BCM_56334_B0) 19868 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F4_BCM56334_B0fmt */ 19869 /* format IFP_SINGLE_WIDE_F4fmt */ 19870 /* nFields */ 1, 19871 /* *fields */ soc_IFP_DOUBLE_WIDE_F4_0_BCM56634_A0fmt_fields, 19872 /* bits */ 7, 19873 /* flags */ 0, 19874 }, 19875 #endif /* chips */ 19876 19877 #if defined(BCM_56340_A0) 19878 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F4_BCM56340_A0fmt */ 19879 /* format IFP_SINGLE_WIDE_F4fmt */ 19880 /* nFields */ 1, 19881 /* *fields */ soc_IFP_DOUBLE_WIDE_F4_0_BCM56640_A0fmt_fields, 19882 /* bits */ 7, 19883 /* flags */ 0, 19884 }, 19885 #endif /* chips */ 19886 19887 #if defined(BCM_56440_A0) 19888 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F4_BCM56440_A0fmt */ 19889 /* format IFP_SINGLE_WIDE_F4fmt */ 19890 /* nFields */ 1, 19891 /* *fields */ soc_IFP_DOUBLE_WIDE_F4_0_BCM56634_A0fmt_fields, 19892 /* bits */ 7, 19893 /* flags */ 0, 19894 }, 19895 #endif /* chips */ 19896 19897 #if defined(BCM_56440_B0) 19898 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F4_BCM56440_B0fmt */ 19899 /* format IFP_SINGLE_WIDE_F4fmt */ 19900 /* nFields */ 1, 19901 /* *fields */ soc_IFP_DOUBLE_WIDE_F4_0_BCM56634_A0fmt_fields, 19902 /* bits */ 7, 19903 /* flags */ 0, 19904 }, 19905 #endif /* chips */ 19906 19907 #if defined(BCM_56450_A0) 19908 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F4_BCM56450_A0fmt */ 19909 /* format IFP_SINGLE_WIDE_F4fmt */ 19910 /* nFields */ 1, 19911 /* *fields */ soc_IFP_SINGLE_WIDE_F4fmt_fields, 19912 /* bits */ 8, 19913 /* flags */ 0, 19914 }, 19915 #endif /* chips */ 19916 19917 #if defined(BCM_56450_B0) 19918 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F4_BCM56450_B0fmt */ 19919 /* format IFP_SINGLE_WIDE_F4fmt */ 19920 /* nFields */ 1, 19921 /* *fields */ soc_IFP_SINGLE_WIDE_F4fmt_fields, 19922 /* bits */ 8, 19923 /* flags */ 0, 19924 }, 19925 #endif /* chips */ 19926 19927 #if defined(BCM_56450_B1) 19928 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F4_BCM56450_B1fmt */ 19929 /* format IFP_SINGLE_WIDE_F4fmt */ 19930 /* nFields */ 1, 19931 /* *fields */ soc_IFP_SINGLE_WIDE_F4fmt_fields, 19932 /* bits */ 8, 19933 /* flags */ 0, 19934 }, 19935 #endif /* chips */ 19936 19937 #if defined(BCM_56524_A0) 19938 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F4_BCM56524_A0fmt */ 19939 /* format IFP_SINGLE_WIDE_F4fmt */ 19940 /* nFields */ 1, 19941 /* *fields */ soc_IFP_DOUBLE_WIDE_F4_0_BCM56634_A0fmt_fields, 19942 /* bits */ 7, 19943 /* flags */ 0, 19944 }, 19945 #endif /* chips */ 19946 19947 #if defined(BCM_56524_B0) 19948 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F4_BCM56524_B0fmt */ 19949 /* format IFP_SINGLE_WIDE_F4fmt */ 19950 /* nFields */ 1, 19951 /* *fields */ soc_IFP_DOUBLE_WIDE_F4_0_BCM56634_A0fmt_fields, 19952 /* bits */ 7, 19953 /* flags */ 0, 19954 }, 19955 #endif /* chips */ 19956 19957 #if defined(BCM_56560_A0) 19958 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F4_BCM56560_A0fmt */ 19959 /* format IFP_SINGLE_WIDE_F4fmt */ 19960 /* nFields */ 1, 19961 /* *fields */ soc_IFP_SINGLE_WIDE_F4_BCM56560_A0fmt_fields, 19962 /* bits */ 8, 19963 /* flags */ 0, 19964 }, 19965 #endif /* chips */ 19966 19967 #if defined(BCM_56560_B0) 19968 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F4_BCM56560_B0fmt */ 19969 /* format IFP_SINGLE_WIDE_F4fmt */ 19970 /* nFields */ 1, 19971 /* *fields */ soc_IFP_SINGLE_WIDE_F4_BCM56560_A0fmt_fields, 19972 /* bits */ 8, 19973 /* flags */ 0, 19974 }, 19975 #endif /* chips */ 19976 19977 #if defined(BCM_56624_B0) 19978 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F4_BCM56624_B0fmt */ 19979 /* format IFP_SINGLE_WIDE_F4fmt */ 19980 /* nFields */ 1, 19981 /* *fields */ soc_IFP_DOUBLE_WIDE_F4_0fmt_fields, 19982 /* bits */ 6, 19983 /* flags */ 0, 19984 }, 19985 #endif /* chips */ 19986 19987 #if defined(BCM_56634_A0) 19988 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F4_BCM56634_A0fmt */ 19989 /* format IFP_SINGLE_WIDE_F4fmt */ 19990 /* nFields */ 1, 19991 /* *fields */ soc_IFP_DOUBLE_WIDE_F4_0_BCM56634_A0fmt_fields, 19992 /* bits */ 7, 19993 /* flags */ 0, 19994 }, 19995 #endif /* chips */ 19996 19997 #if defined(BCM_56634_B0) 19998 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F4_BCM56634_B0fmt */ 19999 /* format IFP_SINGLE_WIDE_F4fmt */ 20000 /* nFields */ 1, 20001 /* *fields */ soc_IFP_DOUBLE_WIDE_F4_0_BCM56634_A0fmt_fields, 20002 /* bits */ 7, 20003 /* flags */ 0, 20004 }, 20005 #endif /* chips */ 20006 20007 #if defined(BCM_56640_A0) 20008 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F4_BCM56640_A0fmt */ 20009 /* format IFP_SINGLE_WIDE_F4fmt */ 20010 /* nFields */ 1, 20011 /* *fields */ soc_IFP_DOUBLE_WIDE_F4_0_BCM56640_A0fmt_fields, 20012 /* bits */ 7, 20013 /* flags */ 0, 20014 }, 20015 #endif /* chips */ 20016 20017 #if defined(BCM_56670_A0) 20018 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F4_BCM56670_A0fmt */ 20019 /* format IFP_SINGLE_WIDE_F4fmt */ 20020 /* nFields */ 1, 20021 /* *fields */ soc_IFP_SINGLE_WIDE_F4_BCM56560_A0fmt_fields, 20022 /* bits */ 8, 20023 /* flags */ 0, 20024 }, 20025 #endif /* chips */ 20026 20027 #if defined(BCM_56670_B0) 20028 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F4_BCM56670_B0fmt */ 20029 /* format IFP_SINGLE_WIDE_F4fmt */ 20030 /* nFields */ 1, 20031 /* *fields */ soc_IFP_SINGLE_WIDE_F4_BCM56560_A0fmt_fields, 20032 /* bits */ 8, 20033 /* flags */ 0, 20034 }, 20035 #endif /* chips */ 20036 20037 #if defined(BCM_56680_A0) 20038 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F4_BCM56680_A0fmt */ 20039 /* format IFP_SINGLE_WIDE_F4fmt */ 20040 /* nFields */ 1, 20041 /* *fields */ soc_IFP_DOUBLE_WIDE_F4_0fmt_fields, 20042 /* bits */ 6, 20043 /* flags */ 0, 20044 }, 20045 #endif /* chips */ 20046 20047 #if defined(BCM_56680_B0) 20048 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F4_BCM56680_B0fmt */ 20049 /* format IFP_SINGLE_WIDE_F4fmt */ 20050 /* nFields */ 1, 20051 /* *fields */ soc_IFP_DOUBLE_WIDE_F4_0fmt_fields, 20052 /* bits */ 6, 20053 /* flags */ 0, 20054 }, 20055 #endif /* chips */ 20056 20057 #if defined(BCM_56685_A0) 20058 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F4_BCM56685_A0fmt */ 20059 /* format IFP_SINGLE_WIDE_F4fmt */ 20060 /* nFields */ 1, 20061 /* *fields */ soc_IFP_DOUBLE_WIDE_F4_0_BCM56634_A0fmt_fields, 20062 /* bits */ 7, 20063 /* flags */ 0, 20064 }, 20065 #endif /* chips */ 20066 20067 #if defined(BCM_56685_B0) 20068 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F4_BCM56685_B0fmt */ 20069 /* format IFP_SINGLE_WIDE_F4fmt */ 20070 /* nFields */ 1, 20071 /* *fields */ soc_IFP_DOUBLE_WIDE_F4_0_BCM56634_A0fmt_fields, 20072 /* bits */ 7, 20073 /* flags */ 0, 20074 }, 20075 #endif /* chips */ 20076 20077 #if defined(BCM_56725_A0) 20078 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F4_BCM56725_A0fmt */ 20079 /* format IFP_SINGLE_WIDE_F4fmt */ 20080 /* nFields */ 1, 20081 /* *fields */ soc_IFP_DOUBLE_WIDE_F4_0fmt_fields, 20082 /* bits */ 6, 20083 /* flags */ 0, 20084 }, 20085 #endif /* chips */ 20086 20087 #if defined(BCM_56820_A0) 20088 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F4_BCM56820_A0fmt */ 20089 /* format IFP_SINGLE_WIDE_F4fmt */ 20090 /* nFields */ 1, 20091 /* *fields */ soc_IFP_DOUBLE_WIDE_F4_0fmt_fields, 20092 /* bits */ 6, 20093 /* flags */ 0, 20094 }, 20095 #endif /* chips */ 20096 20097 #if defined(BCM_56840_A0) 20098 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F4_BCM56840_A0fmt */ 20099 /* format IFP_SINGLE_WIDE_F4fmt */ 20100 /* nFields */ 1, 20101 /* *fields */ soc_IFP_DOUBLE_WIDE_F4_0_BCM56634_A0fmt_fields, 20102 /* bits */ 7, 20103 /* flags */ 0, 20104 }, 20105 #endif /* chips */ 20106 20107 #if defined(BCM_56840_B0) 20108 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F4_BCM56840_B0fmt */ 20109 /* format IFP_SINGLE_WIDE_F4fmt */ 20110 /* nFields */ 1, 20111 /* *fields */ soc_IFP_DOUBLE_WIDE_F4_0_BCM56634_A0fmt_fields, 20112 /* bits */ 7, 20113 /* flags */ 0, 20114 }, 20115 #endif /* chips */ 20116 20117 #if defined(BCM_56850_A0) 20118 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F4_BCM56850_A0fmt */ 20119 /* format IFP_SINGLE_WIDE_F4fmt */ 20120 /* nFields */ 1, 20121 /* *fields */ soc_IFP_SINGLE_WIDE_F4fmt_fields, 20122 /* bits */ 8, 20123 /* flags */ 0, 20124 }, 20125 #endif /* chips */ 20126 20127 #if defined(BCM_56860_A0) 20128 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F4_BCM56860_A0fmt */ 20129 /* format IFP_SINGLE_WIDE_F4fmt */ 20130 /* nFields */ 1, 20131 /* *fields */ soc_IFP_SINGLE_WIDE_F4fmt_fields, 20132 /* bits */ 8, 20133 /* flags */ 0, 20134 }, 20135 #endif /* chips */ 20136 20137 #if defined(BCM_88732_A0) 20138 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_F4_BCM88732_A0fmt */ 20139 /* format IFP_SINGLE_WIDE_F4fmt */ 20140 /* nFields */ 1, 20141 /* *fields */ soc_IFP_DOUBLE_WIDE_F4_0fmt_fields, 20142 /* bits */ 6, 20143 /* flags */ 0, 20144 }, 20145 #endif /* chips */ 20146 20147 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \ 20148 defined(BCM_56680_A0) || defined(BCM_56680_B0) 20149 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_FIXEDfmt */ 20150 /* format IFP_SINGLE_WIDE_FIXEDfmt */ 20151 /* nFields */ 8, 20152 /* *fields */ soc_IFP_SINGLE_WIDE_FIXEDfmt_fields, 20153 /* bits */ 13, 20154 /* flags */ 0, 20155 }, 20156 #endif /* chips */ 20157 20158 #if defined(BCM_53400_A0) 20159 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_FIXED_BCM53400_A0fmt */ 20160 /* format IFP_SINGLE_WIDE_FIXEDfmt */ 20161 /* nFields */ 9, 20162 /* *fields */ soc_IFP_SINGLE_WIDE_FIXED_BCM53400_A0fmt_fields, 20163 /* bits */ 17, 20164 /* flags */ 0, 20165 }, 20166 #endif /* chips */ 20167 20168 #if defined(BCM_53540_A0) 20169 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_FIXED_BCM53540_A0fmt */ 20170 /* format IFP_SINGLE_WIDE_FIXEDfmt */ 20171 /* nFields */ 11, 20172 /* *fields */ soc_IFP_SINGLE_WIDE_FIXED_BCM56160_A0fmt_fields, 20173 /* bits */ 19, 20174 /* flags */ 0, 20175 }, 20176 #endif /* chips */ 20177 20178 #if defined(BCM_53570_A0) 20179 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_FIXED_BCM53570_A0fmt */ 20180 /* format IFP_SINGLE_WIDE_FIXEDfmt */ 20181 /* nFields */ 13, 20182 /* *fields */ soc_IFP_SINGLE_WIDE_FIXED_BCM53570_A0fmt_fields, 20183 /* bits */ 21, 20184 /* flags */ 0, 20185 }, 20186 #endif /* chips */ 20187 20188 #if defined(BCM_53570_B0) 20189 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_FIXED_BCM53570_B0fmt */ 20190 /* format IFP_SINGLE_WIDE_FIXEDfmt */ 20191 /* nFields */ 13, 20192 /* *fields */ soc_IFP_SINGLE_WIDE_FIXED_BCM53570_A0fmt_fields, 20193 /* bits */ 21, 20194 /* flags */ 0, 20195 }, 20196 #endif /* chips */ 20197 20198 #if defined(BCM_56142_A0) 20199 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_FIXED_BCM56142_A0fmt */ 20200 /* format IFP_SINGLE_WIDE_FIXEDfmt */ 20201 /* nFields */ 9, 20202 /* *fields */ soc_IFP_SINGLE_WIDE_FIXED_BCM56634_A0fmt_fields, 20203 /* bits */ 17, 20204 /* flags */ 0, 20205 }, 20206 #endif /* chips */ 20207 20208 #if defined(BCM_56150_A0) 20209 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_FIXED_BCM56150_A0fmt */ 20210 /* format IFP_SINGLE_WIDE_FIXEDfmt */ 20211 /* nFields */ 9, 20212 /* *fields */ soc_IFP_SINGLE_WIDE_FIXED_BCM56150_A0fmt_fields, 20213 /* bits */ 17, 20214 /* flags */ 0, 20215 }, 20216 #endif /* chips */ 20217 20218 #if defined(BCM_56160_A0) 20219 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_FIXED_BCM56160_A0fmt */ 20220 /* format IFP_SINGLE_WIDE_FIXEDfmt */ 20221 /* nFields */ 11, 20222 /* *fields */ soc_IFP_SINGLE_WIDE_FIXED_BCM56160_A0fmt_fields, 20223 /* bits */ 19, 20224 /* flags */ 0, 20225 }, 20226 #endif /* chips */ 20227 20228 #if defined(BCM_56260_A0) 20229 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_FIXED_BCM56260_A0fmt */ 20230 /* format IFP_SINGLE_WIDE_FIXEDfmt */ 20231 /* nFields */ 11, 20232 /* *fields */ soc_IFP_SINGLE_WIDE_FIXED_BCM56260_A0fmt_fields, 20233 /* bits */ 20, 20234 /* flags */ 0, 20235 }, 20236 #endif /* chips */ 20237 20238 #if defined(BCM_56260_B0) 20239 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_FIXED_BCM56260_B0fmt */ 20240 /* format IFP_SINGLE_WIDE_FIXEDfmt */ 20241 /* nFields */ 11, 20242 /* *fields */ soc_IFP_SINGLE_WIDE_FIXED_BCM56260_A0fmt_fields, 20243 /* bits */ 20, 20244 /* flags */ 0, 20245 }, 20246 #endif /* chips */ 20247 20248 #if defined(BCM_56270_A0) 20249 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_FIXED_BCM56270_A0fmt */ 20250 /* format IFP_SINGLE_WIDE_FIXEDfmt */ 20251 /* nFields */ 11, 20252 /* *fields */ soc_IFP_SINGLE_WIDE_FIXED_BCM56260_A0fmt_fields, 20253 /* bits */ 20, 20254 /* flags */ 0, 20255 }, 20256 #endif /* chips */ 20257 20258 #if defined(BCM_56334_A0) 20259 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_FIXED_BCM56334_A0fmt */ 20260 /* format IFP_SINGLE_WIDE_FIXEDfmt */ 20261 /* nFields */ 9, 20262 /* *fields */ soc_IFP_SINGLE_WIDE_FIXED_BCM56634_A0fmt_fields, 20263 /* bits */ 17, 20264 /* flags */ 0, 20265 }, 20266 #endif /* chips */ 20267 20268 #if defined(BCM_56334_B0) 20269 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_FIXED_BCM56334_B0fmt */ 20270 /* format IFP_SINGLE_WIDE_FIXEDfmt */ 20271 /* nFields */ 9, 20272 /* *fields */ soc_IFP_SINGLE_WIDE_FIXED_BCM56634_A0fmt_fields, 20273 /* bits */ 17, 20274 /* flags */ 0, 20275 }, 20276 #endif /* chips */ 20277 20278 #if defined(BCM_56340_A0) 20279 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_FIXED_BCM56340_A0fmt */ 20280 /* format IFP_SINGLE_WIDE_FIXEDfmt */ 20281 /* nFields */ 12, 20282 /* *fields */ soc_IFP_SINGLE_WIDE_FIXED_BCM56640_A0fmt_fields, 20283 /* bits */ 22, 20284 /* flags */ 0, 20285 }, 20286 #endif /* chips */ 20287 20288 #if defined(BCM_56440_A0) 20289 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_FIXED_BCM56440_A0fmt */ 20290 /* format IFP_SINGLE_WIDE_FIXEDfmt */ 20291 /* nFields */ 10, 20292 /* *fields */ soc_IFP_SINGLE_WIDE_FIXED_BCM56440_A0fmt_fields, 20293 /* bits */ 18, 20294 /* flags */ 0, 20295 }, 20296 #endif /* chips */ 20297 20298 #if defined(BCM_56440_B0) 20299 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_FIXED_BCM56440_B0fmt */ 20300 /* format IFP_SINGLE_WIDE_FIXEDfmt */ 20301 /* nFields */ 10, 20302 /* *fields */ soc_IFP_SINGLE_WIDE_FIXED_BCM56440_A0fmt_fields, 20303 /* bits */ 18, 20304 /* flags */ 0, 20305 }, 20306 #endif /* chips */ 20307 20308 #if defined(BCM_56450_A0) 20309 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_FIXED_BCM56450_A0fmt */ 20310 /* format IFP_SINGLE_WIDE_FIXEDfmt */ 20311 /* nFields */ 10, 20312 /* *fields */ soc_IFP_SINGLE_WIDE_FIXED_BCM56450_A0fmt_fields, 20313 /* bits */ 19, 20314 /* flags */ 0, 20315 }, 20316 #endif /* chips */ 20317 20318 #if defined(BCM_56450_B0) 20319 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_FIXED_BCM56450_B0fmt */ 20320 /* format IFP_SINGLE_WIDE_FIXEDfmt */ 20321 /* nFields */ 10, 20322 /* *fields */ soc_IFP_SINGLE_WIDE_FIXED_BCM56450_A0fmt_fields, 20323 /* bits */ 19, 20324 /* flags */ 0, 20325 }, 20326 #endif /* chips */ 20327 20328 #if defined(BCM_56450_B1) 20329 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_FIXED_BCM56450_B1fmt */ 20330 /* format IFP_SINGLE_WIDE_FIXEDfmt */ 20331 /* nFields */ 10, 20332 /* *fields */ soc_IFP_SINGLE_WIDE_FIXED_BCM56450_A0fmt_fields, 20333 /* bits */ 19, 20334 /* flags */ 0, 20335 }, 20336 #endif /* chips */ 20337 20338 #if defined(BCM_56524_A0) 20339 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_FIXED_BCM56524_A0fmt */ 20340 /* format IFP_SINGLE_WIDE_FIXEDfmt */ 20341 /* nFields */ 9, 20342 /* *fields */ soc_IFP_SINGLE_WIDE_FIXED_BCM56634_A0fmt_fields, 20343 /* bits */ 17, 20344 /* flags */ 0, 20345 }, 20346 #endif /* chips */ 20347 20348 #if defined(BCM_56524_B0) 20349 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_FIXED_BCM56524_B0fmt */ 20350 /* format IFP_SINGLE_WIDE_FIXEDfmt */ 20351 /* nFields */ 9, 20352 /* *fields */ soc_IFP_SINGLE_WIDE_FIXED_BCM56634_A0fmt_fields, 20353 /* bits */ 17, 20354 /* flags */ 0, 20355 }, 20356 #endif /* chips */ 20357 20358 #if defined(BCM_56560_A0) 20359 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_FIXED_BCM56560_A0fmt */ 20360 /* format IFP_SINGLE_WIDE_FIXEDfmt */ 20361 /* nFields */ 13, 20362 /* *fields */ soc_IFP_SINGLE_WIDE_FIXED_BCM56560_A0fmt_fields, 20363 /* bits */ 24, 20364 /* flags */ 0, 20365 }, 20366 #endif /* chips */ 20367 20368 #if defined(BCM_56560_B0) 20369 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_FIXED_BCM56560_B0fmt */ 20370 /* format IFP_SINGLE_WIDE_FIXEDfmt */ 20371 /* nFields */ 13, 20372 /* *fields */ soc_IFP_SINGLE_WIDE_FIXED_BCM56560_A0fmt_fields, 20373 /* bits */ 24, 20374 /* flags */ 0, 20375 }, 20376 #endif /* chips */ 20377 20378 #if defined(BCM_56634_A0) 20379 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_FIXED_BCM56634_A0fmt */ 20380 /* format IFP_SINGLE_WIDE_FIXEDfmt */ 20381 /* nFields */ 9, 20382 /* *fields */ soc_IFP_SINGLE_WIDE_FIXED_BCM56634_A0fmt_fields, 20383 /* bits */ 17, 20384 /* flags */ 0, 20385 }, 20386 #endif /* chips */ 20387 20388 #if defined(BCM_56634_B0) 20389 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_FIXED_BCM56634_B0fmt */ 20390 /* format IFP_SINGLE_WIDE_FIXEDfmt */ 20391 /* nFields */ 9, 20392 /* *fields */ soc_IFP_SINGLE_WIDE_FIXED_BCM56634_A0fmt_fields, 20393 /* bits */ 17, 20394 /* flags */ 0, 20395 }, 20396 #endif /* chips */ 20397 20398 #if defined(BCM_56640_A0) 20399 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_FIXED_BCM56640_A0fmt */ 20400 /* format IFP_SINGLE_WIDE_FIXEDfmt */ 20401 /* nFields */ 12, 20402 /* *fields */ soc_IFP_SINGLE_WIDE_FIXED_BCM56640_A0fmt_fields, 20403 /* bits */ 22, 20404 /* flags */ 0, 20405 }, 20406 #endif /* chips */ 20407 20408 #if defined(BCM_56670_A0) 20409 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_FIXED_BCM56670_A0fmt */ 20410 /* format IFP_SINGLE_WIDE_FIXEDfmt */ 20411 /* nFields */ 14, 20412 /* *fields */ soc_IFP_SINGLE_WIDE_FIXED_BCM56670_A0fmt_fields, 20413 /* bits */ 25, 20414 /* flags */ 0, 20415 }, 20416 #endif /* chips */ 20417 20418 #if defined(BCM_56670_B0) 20419 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_FIXED_BCM56670_B0fmt */ 20420 /* format IFP_SINGLE_WIDE_FIXEDfmt */ 20421 /* nFields */ 14, 20422 /* *fields */ soc_IFP_SINGLE_WIDE_FIXED_BCM56670_A0fmt_fields, 20423 /* bits */ 25, 20424 /* flags */ 0, 20425 }, 20426 #endif /* chips */ 20427 20428 #if defined(BCM_56685_A0) 20429 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_FIXED_BCM56685_A0fmt */ 20430 /* format IFP_SINGLE_WIDE_FIXEDfmt */ 20431 /* nFields */ 9, 20432 /* *fields */ soc_IFP_SINGLE_WIDE_FIXED_BCM56634_A0fmt_fields, 20433 /* bits */ 17, 20434 /* flags */ 0, 20435 }, 20436 #endif /* chips */ 20437 20438 #if defined(BCM_56685_B0) 20439 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_FIXED_BCM56685_B0fmt */ 20440 /* format IFP_SINGLE_WIDE_FIXEDfmt */ 20441 /* nFields */ 9, 20442 /* *fields */ soc_IFP_SINGLE_WIDE_FIXED_BCM56634_A0fmt_fields, 20443 /* bits */ 17, 20444 /* flags */ 0, 20445 }, 20446 #endif /* chips */ 20447 20448 #if defined(BCM_56725_A0) 20449 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_FIXED_BCM56725_A0fmt */ 20450 /* format IFP_SINGLE_WIDE_FIXEDfmt */ 20451 /* nFields */ 8, 20452 /* *fields */ soc_IFP_SINGLE_WIDE_FIXED_BCM56820_A0fmt_fields, 20453 /* bits */ 12, 20454 /* flags */ 0, 20455 }, 20456 #endif /* chips */ 20457 20458 #if defined(BCM_56820_A0) 20459 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_FIXED_BCM56820_A0fmt */ 20460 /* format IFP_SINGLE_WIDE_FIXEDfmt */ 20461 /* nFields */ 8, 20462 /* *fields */ soc_IFP_SINGLE_WIDE_FIXED_BCM56820_A0fmt_fields, 20463 /* bits */ 12, 20464 /* flags */ 0, 20465 }, 20466 #endif /* chips */ 20467 20468 #if defined(BCM_56840_A0) 20469 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_FIXED_BCM56840_A0fmt */ 20470 /* format IFP_SINGLE_WIDE_FIXEDfmt */ 20471 /* nFields */ 9, 20472 /* *fields */ soc_IFP_SINGLE_WIDE_FIXED_BCM56634_A0fmt_fields, 20473 /* bits */ 17, 20474 /* flags */ 0, 20475 }, 20476 #endif /* chips */ 20477 20478 #if defined(BCM_56840_B0) 20479 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_FIXED_BCM56840_B0fmt */ 20480 /* format IFP_SINGLE_WIDE_FIXEDfmt */ 20481 /* nFields */ 10, 20482 /* *fields */ soc_IFP_SINGLE_WIDE_FIXED_BCM56840_B0fmt_fields, 20483 /* bits */ 18, 20484 /* flags */ 0, 20485 }, 20486 #endif /* chips */ 20487 20488 #if defined(BCM_56850_A0) 20489 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_FIXED_BCM56850_A0fmt */ 20490 /* format IFP_SINGLE_WIDE_FIXEDfmt */ 20491 /* nFields */ 12, 20492 /* *fields */ soc_IFP_SINGLE_WIDE_FIXED_BCM56850_A0fmt_fields, 20493 /* bits */ 22, 20494 /* flags */ 0, 20495 }, 20496 #endif /* chips */ 20497 20498 #if defined(BCM_56860_A0) 20499 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_FIXED_BCM56860_A0fmt */ 20500 /* format IFP_SINGLE_WIDE_FIXEDfmt */ 20501 /* nFields */ 13, 20502 /* *fields */ soc_IFP_SINGLE_WIDE_FIXED_BCM56860_A0fmt_fields, 20503 /* bits */ 24, 20504 /* flags */ 0, 20505 }, 20506 #endif /* chips */ 20507 20508 #if defined(BCM_88732_A0) 20509 { /* SOC_FORMAT_INT_IFP_SINGLE_WIDE_FIXED_BCM88732_A0fmt */ 20510 /* format IFP_SINGLE_WIDE_FIXEDfmt */ 20511 /* nFields */ 7, 20512 /* *fields */ soc_IFP_SINGLE_WIDE_FIXED_BCM88732_A0fmt_fields, 20513 /* bits */ 12, 20514 /* flags */ 0, 20515 }, 20516 #endif /* chips */ 20517 20518 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 20519 defined(BCM_56870_A0) || defined(BCM_56960_A0) || \ 20520 defined(BCM_56965_A0) || defined(BCM_56970_A0) 20521 { /* SOC_FORMAT_INT_IFP_SLICE_CONTROL_BUSfmt */ 20522 /* format IFP_SLICE_CONTROL_BUSfmt */ 20523 /* nFields */ 9, 20524 /* *fields */ soc_IFP_SLICE_CONTROL_BUSfmt_fields, 20525 /* bits */ 195, 20526 /* flags */ 0, 20527 }, 20528 #endif /* chips */ 20529 20530 #if defined(BCM_56980_A0) 20531 { /* SOC_FORMAT_INT_IFP_SLICE_CONTROL_BUS_BCM56980_A0fmt */ 20532 /* format IFP_SLICE_CONTROL_BUSfmt */ 20533 /* nFields */ 11, 20534 /* *fields */ soc_IFP_SLICE_CONTROL_BUS_BCM56980_A0fmt_fields, 20535 /* bits */ 200, 20536 /* flags */ 0, 20537 }, 20538 #endif /* chips */ 20539 20540 #if defined(BCM_56980_B0) 20541 { /* SOC_FORMAT_INT_IFP_SLICE_CONTROL_BUS_BCM56980_B0fmt */ 20542 /* format IFP_SLICE_CONTROL_BUSfmt */ 20543 /* nFields */ 11, 20544 /* *fields */ soc_IFP_SLICE_CONTROL_BUS_BCM56980_A0fmt_fields, 20545 /* bits */ 200, 20546 /* flags */ 0, 20547 }, 20548 #endif /* chips */ 20549 20550 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \ 20551 defined(BCM_56960_A0) || defined(BCM_56965_A0) || \ 20552 defined(BCM_56970_A0) 20553 { /* SOC_FORMAT_INT_IFP_SLICE_KEY_CONTROL_BUSfmt */ 20554 /* format IFP_SLICE_KEY_CONTROL_BUSfmt */ 20555 /* nFields */ 12, 20556 /* *fields */ soc_IFP_SLICE_KEY_CONTROL_BUSfmt_fields, 20557 /* bits */ 2340, 20558 /* flags */ 0, 20559 }, 20560 #endif /* chips */ 20561 20562 #if defined(BCM_56370_A0) 20563 { /* SOC_FORMAT_INT_IFP_SLICE_KEY_CONTROL_BUS_BCM56370_A0fmt */ 20564 /* format IFP_SLICE_KEY_CONTROL_BUSfmt */ 20565 /* nFields */ 18, 20566 /* *fields */ soc_IFP_SLICE_KEY_CONTROL_BUS_BCM56370_A0fmt_fields, 20567 /* bits */ 3510, 20568 /* flags */ 0, 20569 }, 20570 #endif /* chips */ 20571 20572 #if defined(BCM_56980_A0) 20573 { /* SOC_FORMAT_INT_IFP_SLICE_KEY_CONTROL_BUS_BCM56980_A0fmt */ 20574 /* format IFP_SLICE_KEY_CONTROL_BUSfmt */ 20575 /* nFields */ 9, 20576 /* *fields */ soc_IFP_SLICE_KEY_CONTROL_BUS_BCM56980_A0fmt_fields, 20577 /* bits */ 1800, 20578 /* flags */ 0, 20579 }, 20580 #endif /* chips */ 20581 20582 #if defined(BCM_56980_B0) 20583 { /* SOC_FORMAT_INT_IFP_SLICE_KEY_CONTROL_BUS_BCM56980_B0fmt */ 20584 /* format IFP_SLICE_KEY_CONTROL_BUSfmt */ 20585 /* nFields */ 9, 20586 /* *fields */ soc_IFP_SLICE_KEY_CONTROL_BUS_BCM56980_A0fmt_fields, 20587 /* bits */ 1800, 20588 /* flags */ 0, 20589 }, 20590 #endif /* chips */ 20591 20592 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) || \ 20593 defined(BCM_56970_A0) 20594 { /* SOC_FORMAT_INT_IFP_SOURCE_CLASS_FORMAT_0fmt */ 20595 /* format IFP_SOURCE_CLASS_FORMAT_0fmt */ 20596 /* nFields */ 4, 20597 /* *fields */ soc_IFP_SOURCE_CLASS_FORMAT_0fmt_fields, 20598 /* bits */ 32, 20599 /* flags */ 0, 20600 }, 20601 #endif /* chips */ 20602 20603 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) || \ 20604 defined(BCM_56970_A0) 20605 { /* SOC_FORMAT_INT_IFP_SOURCE_CLASS_FORMAT_1fmt */ 20606 /* format IFP_SOURCE_CLASS_FORMAT_1fmt */ 20607 /* nFields */ 6, 20608 /* *fields */ soc_IFP_SOURCE_CLASS_FORMAT_1fmt_fields, 20609 /* bits */ 32, 20610 /* flags */ 0, 20611 }, 20612 #endif /* chips */ 20613 20614 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) || \ 20615 defined(BCM_56970_A0) 20616 { /* SOC_FORMAT_INT_IFP_SOURCE_CLASS_FORMAT_2fmt */ 20617 /* format IFP_SOURCE_CLASS_FORMAT_2fmt */ 20618 /* nFields */ 6, 20619 /* *fields */ soc_IFP_SOURCE_CLASS_FORMAT_2fmt_fields, 20620 /* bits */ 32, 20621 /* flags */ 0, 20622 }, 20623 #endif /* chips */ 20624 20625 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) || \ 20626 defined(BCM_56970_A0) 20627 { /* SOC_FORMAT_INT_IFP_SOURCE_CLASS_FORMAT_3fmt */ 20628 /* format IFP_SOURCE_CLASS_FORMAT_3fmt */ 20629 /* nFields */ 5, 20630 /* *fields */ soc_IFP_SOURCE_CLASS_FORMAT_3fmt_fields, 20631 /* bits */ 32, 20632 /* flags */ 0, 20633 }, 20634 #endif /* chips */ 20635 20636 #if defined(BCM_56370_A0) 20637 { /* SOC_FORMAT_INT_IFP_SOURCE_CLASS_FORMAT_0_BCM56370_A0fmt */ 20638 /* format IFP_SOURCE_CLASS_FORMAT_0fmt */ 20639 /* nFields */ 4, 20640 /* *fields */ soc_IFP_SOURCE_CLASS_FORMAT_0_BCM56870_A0fmt_fields, 20641 /* bits */ 32, 20642 /* flags */ 0, 20643 }, 20644 #endif /* chips */ 20645 20646 #if defined(BCM_56770_A0) 20647 { /* SOC_FORMAT_INT_IFP_SOURCE_CLASS_FORMAT_0_BCM56770_A0fmt */ 20648 /* format IFP_SOURCE_CLASS_FORMAT_0fmt */ 20649 /* nFields */ 4, 20650 /* *fields */ soc_IFP_SOURCE_CLASS_FORMAT_0_BCM56870_A0fmt_fields, 20651 /* bits */ 32, 20652 /* flags */ 0, 20653 }, 20654 #endif /* chips */ 20655 20656 #if defined(BCM_56870_A0) 20657 { /* SOC_FORMAT_INT_IFP_SOURCE_CLASS_FORMAT_0_BCM56870_A0fmt */ 20658 /* format IFP_SOURCE_CLASS_FORMAT_0fmt */ 20659 /* nFields */ 4, 20660 /* *fields */ soc_IFP_SOURCE_CLASS_FORMAT_0_BCM56870_A0fmt_fields, 20661 /* bits */ 32, 20662 /* flags */ 0, 20663 }, 20664 #endif /* chips */ 20665 20666 #if defined(BCM_56980_A0) 20667 { /* SOC_FORMAT_INT_IFP_SOURCE_CLASS_FORMAT_0_BCM56980_A0fmt */ 20668 /* format IFP_SOURCE_CLASS_FORMAT_0fmt */ 20669 /* nFields */ 4, 20670 /* *fields */ soc_IFP_SOURCE_CLASS_FORMAT_0_BCM56980_A0fmt_fields, 20671 /* bits */ 32, 20672 /* flags */ 0, 20673 }, 20674 #endif /* chips */ 20675 20676 #if defined(BCM_56980_B0) 20677 { /* SOC_FORMAT_INT_IFP_SOURCE_CLASS_FORMAT_0_BCM56980_B0fmt */ 20678 /* format IFP_SOURCE_CLASS_FORMAT_0fmt */ 20679 /* nFields */ 4, 20680 /* *fields */ soc_IFP_SOURCE_CLASS_FORMAT_0_BCM56980_A0fmt_fields, 20681 /* bits */ 32, 20682 /* flags */ 0, 20683 }, 20684 #endif /* chips */ 20685 20686 #if defined(BCM_56370_A0) 20687 { /* SOC_FORMAT_INT_IFP_SOURCE_CLASS_FORMAT_1_BCM56370_A0fmt */ 20688 /* format IFP_SOURCE_CLASS_FORMAT_1fmt */ 20689 /* nFields */ 6, 20690 /* *fields */ soc_IFP_SOURCE_CLASS_FORMAT_1_BCM56870_A0fmt_fields, 20691 /* bits */ 32, 20692 /* flags */ 0, 20693 }, 20694 #endif /* chips */ 20695 20696 #if defined(BCM_56770_A0) 20697 { /* SOC_FORMAT_INT_IFP_SOURCE_CLASS_FORMAT_1_BCM56770_A0fmt */ 20698 /* format IFP_SOURCE_CLASS_FORMAT_1fmt */ 20699 /* nFields */ 6, 20700 /* *fields */ soc_IFP_SOURCE_CLASS_FORMAT_1_BCM56870_A0fmt_fields, 20701 /* bits */ 32, 20702 /* flags */ 0, 20703 }, 20704 #endif /* chips */ 20705 20706 #if defined(BCM_56870_A0) 20707 { /* SOC_FORMAT_INT_IFP_SOURCE_CLASS_FORMAT_1_BCM56870_A0fmt */ 20708 /* format IFP_SOURCE_CLASS_FORMAT_1fmt */ 20709 /* nFields */ 6, 20710 /* *fields */ soc_IFP_SOURCE_CLASS_FORMAT_1_BCM56870_A0fmt_fields, 20711 /* bits */ 32, 20712 /* flags */ 0, 20713 }, 20714 #endif /* chips */ 20715 20716 #if defined(BCM_56980_A0) 20717 { /* SOC_FORMAT_INT_IFP_SOURCE_CLASS_FORMAT_1_BCM56980_A0fmt */ 20718 /* format IFP_SOURCE_CLASS_FORMAT_1fmt */ 20719 /* nFields */ 6, 20720 /* *fields */ soc_IFP_SOURCE_CLASS_FORMAT_1_BCM56980_A0fmt_fields, 20721 /* bits */ 32, 20722 /* flags */ 0, 20723 }, 20724 #endif /* chips */ 20725 20726 #if defined(BCM_56980_B0) 20727 { /* SOC_FORMAT_INT_IFP_SOURCE_CLASS_FORMAT_1_BCM56980_B0fmt */ 20728 /* format IFP_SOURCE_CLASS_FORMAT_1fmt */ 20729 /* nFields */ 6, 20730 /* *fields */ soc_IFP_SOURCE_CLASS_FORMAT_1_BCM56980_A0fmt_fields, 20731 /* bits */ 32, 20732 /* flags */ 0, 20733 }, 20734 #endif /* chips */ 20735 20736 #if defined(BCM_56370_A0) 20737 { /* SOC_FORMAT_INT_IFP_SOURCE_CLASS_FORMAT_2_BCM56370_A0fmt */ 20738 /* format IFP_SOURCE_CLASS_FORMAT_2fmt */ 20739 /* nFields */ 6, 20740 /* *fields */ soc_IFP_SOURCE_CLASS_FORMAT_2_BCM56870_A0fmt_fields, 20741 /* bits */ 32, 20742 /* flags */ 0, 20743 }, 20744 #endif /* chips */ 20745 20746 #if defined(BCM_56770_A0) 20747 { /* SOC_FORMAT_INT_IFP_SOURCE_CLASS_FORMAT_2_BCM56770_A0fmt */ 20748 /* format IFP_SOURCE_CLASS_FORMAT_2fmt */ 20749 /* nFields */ 6, 20750 /* *fields */ soc_IFP_SOURCE_CLASS_FORMAT_2_BCM56870_A0fmt_fields, 20751 /* bits */ 32, 20752 /* flags */ 0, 20753 }, 20754 #endif /* chips */ 20755 20756 #if defined(BCM_56870_A0) 20757 { /* SOC_FORMAT_INT_IFP_SOURCE_CLASS_FORMAT_2_BCM56870_A0fmt */ 20758 /* format IFP_SOURCE_CLASS_FORMAT_2fmt */ 20759 /* nFields */ 6, 20760 /* *fields */ soc_IFP_SOURCE_CLASS_FORMAT_2_BCM56870_A0fmt_fields, 20761 /* bits */ 32, 20762 /* flags */ 0, 20763 }, 20764 #endif /* chips */ 20765 20766 #if defined(BCM_56980_A0) 20767 { /* SOC_FORMAT_INT_IFP_SOURCE_CLASS_FORMAT_2_BCM56980_A0fmt */ 20768 /* format IFP_SOURCE_CLASS_FORMAT_2fmt */ 20769 /* nFields */ 6, 20770 /* *fields */ soc_IFP_SOURCE_CLASS_FORMAT_2_BCM56980_A0fmt_fields, 20771 /* bits */ 32, 20772 /* flags */ 0, 20773 }, 20774 #endif /* chips */ 20775 20776 #if defined(BCM_56980_B0) 20777 { /* SOC_FORMAT_INT_IFP_SOURCE_CLASS_FORMAT_2_BCM56980_B0fmt */ 20778 /* format IFP_SOURCE_CLASS_FORMAT_2fmt */ 20779 /* nFields */ 6, 20780 /* *fields */ soc_IFP_SOURCE_CLASS_FORMAT_2_BCM56980_A0fmt_fields, 20781 /* bits */ 32, 20782 /* flags */ 0, 20783 }, 20784 #endif /* chips */ 20785 20786 #if defined(BCM_56370_A0) 20787 { /* SOC_FORMAT_INT_IFP_SOURCE_CLASS_FORMAT_3_BCM56370_A0fmt */ 20788 /* format IFP_SOURCE_CLASS_FORMAT_3fmt */ 20789 /* nFields */ 5, 20790 /* *fields */ soc_IFP_SOURCE_CLASS_FORMAT_3_BCM56870_A0fmt_fields, 20791 /* bits */ 32, 20792 /* flags */ 0, 20793 }, 20794 #endif /* chips */ 20795 20796 #if defined(BCM_56770_A0) 20797 { /* SOC_FORMAT_INT_IFP_SOURCE_CLASS_FORMAT_3_BCM56770_A0fmt */ 20798 /* format IFP_SOURCE_CLASS_FORMAT_3fmt */ 20799 /* nFields */ 5, 20800 /* *fields */ soc_IFP_SOURCE_CLASS_FORMAT_3_BCM56870_A0fmt_fields, 20801 /* bits */ 32, 20802 /* flags */ 0, 20803 }, 20804 #endif /* chips */ 20805 20806 #if defined(BCM_56870_A0) 20807 { /* SOC_FORMAT_INT_IFP_SOURCE_CLASS_FORMAT_3_BCM56870_A0fmt */ 20808 /* format IFP_SOURCE_CLASS_FORMAT_3fmt */ 20809 /* nFields */ 5, 20810 /* *fields */ soc_IFP_SOURCE_CLASS_FORMAT_3_BCM56870_A0fmt_fields, 20811 /* bits */ 32, 20812 /* flags */ 0, 20813 }, 20814 #endif /* chips */ 20815 20816 #if defined(BCM_56980_A0) 20817 { /* SOC_FORMAT_INT_IFP_SOURCE_CLASS_FORMAT_3_BCM56980_A0fmt */ 20818 /* format IFP_SOURCE_CLASS_FORMAT_3fmt */ 20819 /* nFields */ 5, 20820 /* *fields */ soc_IFP_SOURCE_CLASS_FORMAT_3_BCM56980_A0fmt_fields, 20821 /* bits */ 32, 20822 /* flags */ 0, 20823 }, 20824 #endif /* chips */ 20825 20826 #if defined(BCM_56980_B0) 20827 { /* SOC_FORMAT_INT_IFP_SOURCE_CLASS_FORMAT_3_BCM56980_B0fmt */ 20828 /* format IFP_SOURCE_CLASS_FORMAT_3fmt */ 20829 /* nFields */ 5, 20830 /* *fields */ soc_IFP_SOURCE_CLASS_FORMAT_3_BCM56980_A0fmt_fields, 20831 /* bits */ 32, 20832 /* flags */ 0, 20833 }, 20834 #endif /* chips */ 20835 20836 #if defined(BCM_56340_A0) || defined(BCM_56640_A0) || \ 20837 defined(BCM_56850_A0) 20838 { /* SOC_FORMAT_INT_IFP_STORM_METER_COV_DEFSfmt */ 20839 /* format IFP_STORM_METER_COV_DEFSfmt */ 20840 /* nFields */ 7, 20841 /* *fields */ soc_IFP_STORM_METER_COV_DEFSfmt_fields, 20842 /* bits */ 17, 20843 /* flags */ 0, 20844 }, 20845 #endif /* chips */ 20846 20847 #if defined(BCM_53400_A0) 20848 { /* SOC_FORMAT_INT_IFP_STORM_METER_COV_DEFS_BCM53400_A0fmt */ 20849 /* format IFP_STORM_METER_COV_DEFSfmt */ 20850 /* nFields */ 7, 20851 /* *fields */ soc_IFP_EVEN_METER_COV_DEFS_BCM53400_A0fmt_fields, 20852 /* bits */ 14, 20853 /* flags */ 0, 20854 }, 20855 #endif /* chips */ 20856 20857 #if defined(BCM_53540_A0) 20858 { /* SOC_FORMAT_INT_IFP_STORM_METER_COV_DEFS_BCM53540_A0fmt */ 20859 /* format IFP_STORM_METER_COV_DEFSfmt */ 20860 /* nFields */ 7, 20861 /* *fields */ soc_IFP_EVEN_METER_COV_DEFS_BCM53400_A0fmt_fields, 20862 /* bits */ 14, 20863 /* flags */ 0, 20864 }, 20865 #endif /* chips */ 20866 20867 #if defined(BCM_53570_A0) 20868 { /* SOC_FORMAT_INT_IFP_STORM_METER_COV_DEFS_BCM53570_A0fmt */ 20869 /* format IFP_STORM_METER_COV_DEFSfmt */ 20870 /* nFields */ 7, 20871 /* *fields */ soc_IFP_EVEN_METER_COV_DEFS_BCM53400_A0fmt_fields, 20872 /* bits */ 14, 20873 /* flags */ 0, 20874 }, 20875 #endif /* chips */ 20876 20877 #if defined(BCM_53570_B0) 20878 { /* SOC_FORMAT_INT_IFP_STORM_METER_COV_DEFS_BCM53570_B0fmt */ 20879 /* format IFP_STORM_METER_COV_DEFSfmt */ 20880 /* nFields */ 7, 20881 /* *fields */ soc_IFP_EVEN_METER_COV_DEFS_BCM53400_A0fmt_fields, 20882 /* bits */ 14, 20883 /* flags */ 0, 20884 }, 20885 #endif /* chips */ 20886 20887 #if defined(BCM_56150_A0) 20888 { /* SOC_FORMAT_INT_IFP_STORM_METER_COV_DEFS_BCM56150_A0fmt */ 20889 /* format IFP_STORM_METER_COV_DEFSfmt */ 20890 /* nFields */ 7, 20891 /* *fields */ soc_EFP_EVEN_METER_COV_DEFS_BCM56850_A0fmt_fields, 20892 /* bits */ 14, 20893 /* flags */ 0, 20894 }, 20895 #endif /* chips */ 20896 20897 #if defined(BCM_56160_A0) 20898 { /* SOC_FORMAT_INT_IFP_STORM_METER_COV_DEFS_BCM56160_A0fmt */ 20899 /* format IFP_STORM_METER_COV_DEFSfmt */ 20900 /* nFields */ 7, 20901 /* *fields */ soc_IFP_EVEN_METER_COV_DEFS_BCM53400_A0fmt_fields, 20902 /* bits */ 14, 20903 /* flags */ 0, 20904 }, 20905 #endif /* chips */ 20906 20907 #if defined(BCM_56370_A0) 20908 { /* SOC_FORMAT_INT_IFP_STORM_METER_COV_DEFS_BCM56370_A0fmt */ 20909 /* format IFP_STORM_METER_COV_DEFSfmt */ 20910 /* nFields */ 7, 20911 /* *fields */ soc_IFP_STORM_METER_COV_DEFS_BCM56960_A0fmt_fields, 20912 /* bits */ 17, 20913 /* flags */ 0, 20914 }, 20915 #endif /* chips */ 20916 20917 #if defined(BCM_56560_A0) 20918 { /* SOC_FORMAT_INT_IFP_STORM_METER_COV_DEFS_BCM56560_A0fmt */ 20919 /* format IFP_STORM_METER_COV_DEFSfmt */ 20920 /* nFields */ 8, 20921 /* *fields */ soc_IFP_STORM_METER_COV_DEFS_BCM56560_A0fmt_fields, 20922 /* bits */ 18, 20923 /* flags */ 0, 20924 }, 20925 #endif /* chips */ 20926 20927 #if defined(BCM_56560_B0) 20928 { /* SOC_FORMAT_INT_IFP_STORM_METER_COV_DEFS_BCM56560_B0fmt */ 20929 /* format IFP_STORM_METER_COV_DEFSfmt */ 20930 /* nFields */ 8, 20931 /* *fields */ soc_IFP_STORM_METER_COV_DEFS_BCM56560_A0fmt_fields, 20932 /* bits */ 18, 20933 /* flags */ 0, 20934 }, 20935 #endif /* chips */ 20936 20937 #if defined(BCM_56670_A0) 20938 { /* SOC_FORMAT_INT_IFP_STORM_METER_COV_DEFS_BCM56670_A0fmt */ 20939 /* format IFP_STORM_METER_COV_DEFSfmt */ 20940 /* nFields */ 8, 20941 /* *fields */ soc_IFP_STORM_METER_COV_DEFS_BCM56560_A0fmt_fields, 20942 /* bits */ 18, 20943 /* flags */ 0, 20944 }, 20945 #endif /* chips */ 20946 20947 #if defined(BCM_56670_B0) 20948 { /* SOC_FORMAT_INT_IFP_STORM_METER_COV_DEFS_BCM56670_B0fmt */ 20949 /* format IFP_STORM_METER_COV_DEFSfmt */ 20950 /* nFields */ 8, 20951 /* *fields */ soc_IFP_STORM_METER_COV_DEFS_BCM56560_A0fmt_fields, 20952 /* bits */ 18, 20953 /* flags */ 0, 20954 }, 20955 #endif /* chips */ 20956 20957 #if defined(BCM_56770_A0) 20958 { /* SOC_FORMAT_INT_IFP_STORM_METER_COV_DEFS_BCM56770_A0fmt */ 20959 /* format IFP_STORM_METER_COV_DEFSfmt */ 20960 /* nFields */ 7, 20961 /* *fields */ soc_IFP_STORM_METER_COV_DEFS_BCM56960_A0fmt_fields, 20962 /* bits */ 17, 20963 /* flags */ 0, 20964 }, 20965 #endif /* chips */ 20966 20967 #if defined(BCM_56860_A0) 20968 { /* SOC_FORMAT_INT_IFP_STORM_METER_COV_DEFS_BCM56860_A0fmt */ 20969 /* format IFP_STORM_METER_COV_DEFSfmt */ 20970 /* nFields */ 8, 20971 /* *fields */ soc_IFP_STORM_METER_COV_DEFS_BCM56860_A0fmt_fields, 20972 /* bits */ 18, 20973 /* flags */ 0, 20974 }, 20975 #endif /* chips */ 20976 20977 #if defined(BCM_56870_A0) 20978 { /* SOC_FORMAT_INT_IFP_STORM_METER_COV_DEFS_BCM56870_A0fmt */ 20979 /* format IFP_STORM_METER_COV_DEFSfmt */ 20980 /* nFields */ 7, 20981 /* *fields */ soc_IFP_STORM_METER_COV_DEFS_BCM56960_A0fmt_fields, 20982 /* bits */ 17, 20983 /* flags */ 0, 20984 }, 20985 #endif /* chips */ 20986 20987 #if defined(BCM_56960_A0) 20988 { /* SOC_FORMAT_INT_IFP_STORM_METER_COV_DEFS_BCM56960_A0fmt */ 20989 /* format IFP_STORM_METER_COV_DEFSfmt */ 20990 /* nFields */ 7, 20991 /* *fields */ soc_IFP_STORM_METER_COV_DEFS_BCM56960_A0fmt_fields, 20992 /* bits */ 17, 20993 /* flags */ 0, 20994 }, 20995 #endif /* chips */ 20996 20997 #if defined(BCM_56965_A0) 20998 { /* SOC_FORMAT_INT_IFP_STORM_METER_COV_DEFS_BCM56965_A0fmt */ 20999 /* format IFP_STORM_METER_COV_DEFSfmt */ 21000 /* nFields */ 7, 21001 /* *fields */ soc_IFP_STORM_METER_COV_DEFS_BCM56960_A0fmt_fields, 21002 /* bits */ 17, 21003 /* flags */ 0, 21004 }, 21005 #endif /* chips */ 21006 21007 #if defined(BCM_56970_A0) 21008 { /* SOC_FORMAT_INT_IFP_STORM_METER_COV_DEFS_BCM56970_A0fmt */ 21009 /* format IFP_STORM_METER_COV_DEFSfmt */ 21010 /* nFields */ 7, 21011 /* *fields */ soc_IFP_STORM_METER_COV_DEFS_BCM56960_A0fmt_fields, 21012 /* bits */ 17, 21013 /* flags */ 0, 21014 }, 21015 #endif /* chips */ 21016 21017 #if defined(BCM_56980_A0) 21018 { /* SOC_FORMAT_INT_IFP_STORM_METER_COV_DEFS_BCM56980_A0fmt */ 21019 /* format IFP_STORM_METER_COV_DEFSfmt */ 21020 /* nFields */ 7, 21021 /* *fields */ soc_IFP_STORM_METER_COV_DEFS_BCM56960_A0fmt_fields, 21022 /* bits */ 17, 21023 /* flags */ 0, 21024 }, 21025 #endif /* chips */ 21026 21027 #if defined(BCM_56980_B0) 21028 { /* SOC_FORMAT_INT_IFP_STORM_METER_COV_DEFS_BCM56980_B0fmt */ 21029 /* format IFP_STORM_METER_COV_DEFSfmt */ 21030 /* nFields */ 7, 21031 /* *fields */ soc_IFP_STORM_METER_COV_DEFS_BCM56960_A0fmt_fields, 21032 /* bits */ 17, 21033 /* flags */ 0, 21034 }, 21035 #endif /* chips */ 21036 21037 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) 21038 { /* SOC_FORMAT_INT_IFP_TCAM_DOP_DOPfmt */ 21039 /* format IFP_TCAM_DOP_DOPfmt */ 21040 /* nFields */ 14, 21041 /* *fields */ soc_IFP_TCAM_DOP_DOPfmt_fields, 21042 /* bits */ 192, 21043 /* flags */ 0, 21044 }, 21045 #endif /* chips */ 21046 21047 #if defined(BCM_56370_A0) 21048 { /* SOC_FORMAT_INT_IFP_TCAM_DOP_DOP_BCM56370_A0fmt */ 21049 /* format IFP_TCAM_DOP_DOPfmt */ 21050 /* nFields */ 20, 21051 /* *fields */ soc_IFP_TCAM_DOP_DOP_BCM56370_A0fmt_fields, 21052 /* bits */ 288, 21053 /* flags */ 0, 21054 }, 21055 #endif /* chips */ 21056 21057 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 21058 defined(BCM_56870_A0) 21059 { /* SOC_FORMAT_INT_IFP_TCAM_KEY_0_DOPfmt */ 21060 /* format IFP_TCAM_KEY_0_DOPfmt */ 21061 /* nFields */ 2, 21062 /* *fields */ soc_IFP_TCAM_KEY_0_DOPfmt_fields, 21063 /* bits */ 160, 21064 /* flags */ 0, 21065 }, 21066 #endif /* chips */ 21067 21068 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 21069 defined(BCM_56870_A0) 21070 { /* SOC_FORMAT_INT_IFP_TCAM_KEY_10_DOPfmt */ 21071 /* format IFP_TCAM_KEY_10_DOPfmt */ 21072 /* nFields */ 2, 21073 /* *fields */ soc_IFP_TCAM_KEY_10_DOPfmt_fields, 21074 /* bits */ 160, 21075 /* flags */ 0, 21076 }, 21077 #endif /* chips */ 21078 21079 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 21080 defined(BCM_56870_A0) 21081 { /* SOC_FORMAT_INT_IFP_TCAM_KEY_11_DOPfmt */ 21082 /* format IFP_TCAM_KEY_11_DOPfmt */ 21083 /* nFields */ 2, 21084 /* *fields */ soc_IFP_TCAM_KEY_11_DOPfmt_fields, 21085 /* bits */ 160, 21086 /* flags */ 0, 21087 }, 21088 #endif /* chips */ 21089 21090 #if defined(BCM_56370_A0) 21091 { /* SOC_FORMAT_INT_IFP_TCAM_KEY_12_DOPfmt */ 21092 /* format IFP_TCAM_KEY_12_DOPfmt */ 21093 /* nFields */ 2, 21094 /* *fields */ soc_IFP_TCAM_KEY_12_DOPfmt_fields, 21095 /* bits */ 160, 21096 /* flags */ 0, 21097 }, 21098 #endif /* chips */ 21099 21100 #if defined(BCM_56370_A0) 21101 { /* SOC_FORMAT_INT_IFP_TCAM_KEY_13_DOPfmt */ 21102 /* format IFP_TCAM_KEY_13_DOPfmt */ 21103 /* nFields */ 2, 21104 /* *fields */ soc_IFP_TCAM_KEY_13_DOPfmt_fields, 21105 /* bits */ 160, 21106 /* flags */ 0, 21107 }, 21108 #endif /* chips */ 21109 21110 #if defined(BCM_56370_A0) 21111 { /* SOC_FORMAT_INT_IFP_TCAM_KEY_14_DOPfmt */ 21112 /* format IFP_TCAM_KEY_14_DOPfmt */ 21113 /* nFields */ 2, 21114 /* *fields */ soc_IFP_TCAM_KEY_14_DOPfmt_fields, 21115 /* bits */ 160, 21116 /* flags */ 0, 21117 }, 21118 #endif /* chips */ 21119 21120 #if defined(BCM_56370_A0) 21121 { /* SOC_FORMAT_INT_IFP_TCAM_KEY_15_DOPfmt */ 21122 /* format IFP_TCAM_KEY_15_DOPfmt */ 21123 /* nFields */ 2, 21124 /* *fields */ soc_IFP_TCAM_KEY_15_DOPfmt_fields, 21125 /* bits */ 160, 21126 /* flags */ 0, 21127 }, 21128 #endif /* chips */ 21129 21130 #if defined(BCM_56370_A0) 21131 { /* SOC_FORMAT_INT_IFP_TCAM_KEY_16_DOPfmt */ 21132 /* format IFP_TCAM_KEY_16_DOPfmt */ 21133 /* nFields */ 2, 21134 /* *fields */ soc_IFP_TCAM_KEY_16_DOPfmt_fields, 21135 /* bits */ 160, 21136 /* flags */ 0, 21137 }, 21138 #endif /* chips */ 21139 21140 #if defined(BCM_56370_A0) 21141 { /* SOC_FORMAT_INT_IFP_TCAM_KEY_17_DOPfmt */ 21142 /* format IFP_TCAM_KEY_17_DOPfmt */ 21143 /* nFields */ 2, 21144 /* *fields */ soc_IFP_TCAM_KEY_17_DOPfmt_fields, 21145 /* bits */ 160, 21146 /* flags */ 0, 21147 }, 21148 #endif /* chips */ 21149 21150 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 21151 defined(BCM_56870_A0) 21152 { /* SOC_FORMAT_INT_IFP_TCAM_KEY_1_DOPfmt */ 21153 /* format IFP_TCAM_KEY_1_DOPfmt */ 21154 /* nFields */ 2, 21155 /* *fields */ soc_IFP_TCAM_KEY_1_DOPfmt_fields, 21156 /* bits */ 160, 21157 /* flags */ 0, 21158 }, 21159 #endif /* chips */ 21160 21161 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 21162 defined(BCM_56870_A0) 21163 { /* SOC_FORMAT_INT_IFP_TCAM_KEY_2_DOPfmt */ 21164 /* format IFP_TCAM_KEY_2_DOPfmt */ 21165 /* nFields */ 2, 21166 /* *fields */ soc_IFP_TCAM_KEY_2_DOPfmt_fields, 21167 /* bits */ 160, 21168 /* flags */ 0, 21169 }, 21170 #endif /* chips */ 21171 21172 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 21173 defined(BCM_56870_A0) 21174 { /* SOC_FORMAT_INT_IFP_TCAM_KEY_3_DOPfmt */ 21175 /* format IFP_TCAM_KEY_3_DOPfmt */ 21176 /* nFields */ 2, 21177 /* *fields */ soc_IFP_TCAM_KEY_3_DOPfmt_fields, 21178 /* bits */ 160, 21179 /* flags */ 0, 21180 }, 21181 #endif /* chips */ 21182 21183 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 21184 defined(BCM_56870_A0) 21185 { /* SOC_FORMAT_INT_IFP_TCAM_KEY_4_DOPfmt */ 21186 /* format IFP_TCAM_KEY_4_DOPfmt */ 21187 /* nFields */ 2, 21188 /* *fields */ soc_IFP_TCAM_KEY_4_DOPfmt_fields, 21189 /* bits */ 160, 21190 /* flags */ 0, 21191 }, 21192 #endif /* chips */ 21193 21194 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 21195 defined(BCM_56870_A0) 21196 { /* SOC_FORMAT_INT_IFP_TCAM_KEY_5_DOPfmt */ 21197 /* format IFP_TCAM_KEY_5_DOPfmt */ 21198 /* nFields */ 2, 21199 /* *fields */ soc_IFP_TCAM_KEY_5_DOPfmt_fields, 21200 /* bits */ 160, 21201 /* flags */ 0, 21202 }, 21203 #endif /* chips */ 21204 21205 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 21206 defined(BCM_56870_A0) 21207 { /* SOC_FORMAT_INT_IFP_TCAM_KEY_6_DOPfmt */ 21208 /* format IFP_TCAM_KEY_6_DOPfmt */ 21209 /* nFields */ 2, 21210 /* *fields */ soc_IFP_TCAM_KEY_6_DOPfmt_fields, 21211 /* bits */ 160, 21212 /* flags */ 0, 21213 }, 21214 #endif /* chips */ 21215 21216 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 21217 defined(BCM_56870_A0) 21218 { /* SOC_FORMAT_INT_IFP_TCAM_KEY_7_DOPfmt */ 21219 /* format IFP_TCAM_KEY_7_DOPfmt */ 21220 /* nFields */ 2, 21221 /* *fields */ soc_IFP_TCAM_KEY_7_DOPfmt_fields, 21222 /* bits */ 160, 21223 /* flags */ 0, 21224 }, 21225 #endif /* chips */ 21226 21227 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 21228 defined(BCM_56870_A0) 21229 { /* SOC_FORMAT_INT_IFP_TCAM_KEY_8_DOPfmt */ 21230 /* format IFP_TCAM_KEY_8_DOPfmt */ 21231 /* nFields */ 2, 21232 /* *fields */ soc_IFP_TCAM_KEY_8_DOPfmt_fields, 21233 /* bits */ 160, 21234 /* flags */ 0, 21235 }, 21236 #endif /* chips */ 21237 21238 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 21239 defined(BCM_56870_A0) 21240 { /* SOC_FORMAT_INT_IFP_TCAM_KEY_9_DOPfmt */ 21241 /* format IFP_TCAM_KEY_9_DOPfmt */ 21242 /* nFields */ 2, 21243 /* *fields */ soc_IFP_TCAM_KEY_9_DOPfmt_fields, 21244 /* bits */ 160, 21245 /* flags */ 0, 21246 }, 21247 #endif /* chips */ 21248 21249 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 21250 defined(BCM_56870_A0) 21251 { /* SOC_FORMAT_INT_IFP_TIMESTAMP_INSERTION_SETfmt */ 21252 /* format IFP_TIMESTAMP_INSERTION_SETfmt */ 21253 /* nFields */ 1, 21254 /* *fields */ soc_IFP_TIMESTAMP_INSERTION_SETfmt_fields, 21255 /* bits */ 2, 21256 /* flags */ 0, 21257 }, 21258 #endif /* chips */ 21259 21260 #if defined(BCM_56970_A0) || defined(BCM_56980_A0) || \ 21261 defined(BCM_56980_B0) 21262 { /* SOC_FORMAT_INT_IFP_TIMESTAMP_SETfmt */ 21263 /* format IFP_TIMESTAMP_SETfmt */ 21264 /* nFields */ 2, 21265 /* *fields */ soc_IFP_TIMESTAMP_SETfmt_fields, 21266 /* bits */ 4, 21267 /* flags */ 0, 21268 }, 21269 #endif /* chips */ 21270 21271 #if defined(BCM_56850_A0) 21272 { /* SOC_FORMAT_INT_IFP_TO_IFP_SHARED_CTR_BUSfmt */ 21273 /* format IFP_TO_IFP_SHARED_CTR_BUSfmt */ 21274 /* nFields */ 1, 21275 /* *fields */ soc_IFP_TO_IFP_SHARED_CTR_BUSfmt_fields, 21276 /* bits */ 118, 21277 /* flags */ 0, 21278 }, 21279 #endif /* chips */ 21280 21281 #if defined(BCM_56560_A0) 21282 { /* SOC_FORMAT_INT_IFP_TO_IFP_SHARED_CTR_BUS_BCM56560_A0fmt */ 21283 /* format IFP_TO_IFP_SHARED_CTR_BUSfmt */ 21284 /* nFields */ 1, 21285 /* *fields */ soc_IFP_TO_IFP_SHARED_CTR_BUS_BCM56560_A0fmt_fields, 21286 /* bits */ 108, 21287 /* flags */ 0, 21288 }, 21289 #endif /* chips */ 21290 21291 #if defined(BCM_56560_B0) 21292 { /* SOC_FORMAT_INT_IFP_TO_IFP_SHARED_CTR_BUS_BCM56560_B0fmt */ 21293 /* format IFP_TO_IFP_SHARED_CTR_BUSfmt */ 21294 /* nFields */ 1, 21295 /* *fields */ soc_IFP_TO_IFP_SHARED_CTR_BUS_BCM56560_A0fmt_fields, 21296 /* bits */ 108, 21297 /* flags */ 0, 21298 }, 21299 #endif /* chips */ 21300 21301 #if defined(BCM_56670_A0) 21302 { /* SOC_FORMAT_INT_IFP_TO_IFP_SHARED_CTR_BUS_BCM56670_A0fmt */ 21303 /* format IFP_TO_IFP_SHARED_CTR_BUSfmt */ 21304 /* nFields */ 1, 21305 /* *fields */ soc_IFP_TO_IFP_SHARED_CTR_BUS_BCM56670_A0fmt_fields, 21306 /* bits */ 109, 21307 /* flags */ 0, 21308 }, 21309 #endif /* chips */ 21310 21311 #if defined(BCM_56670_B0) 21312 { /* SOC_FORMAT_INT_IFP_TO_IFP_SHARED_CTR_BUS_BCM56670_B0fmt */ 21313 /* format IFP_TO_IFP_SHARED_CTR_BUSfmt */ 21314 /* nFields */ 1, 21315 /* *fields */ soc_IFP_TO_IFP_SHARED_CTR_BUS_BCM56670_A0fmt_fields, 21316 /* bits */ 109, 21317 /* flags */ 0, 21318 }, 21319 #endif /* chips */ 21320 21321 #if defined(BCM_56860_A0) 21322 { /* SOC_FORMAT_INT_IFP_TO_IFP_SHARED_CTR_BUS_BCM56860_A0fmt */ 21323 /* format IFP_TO_IFP_SHARED_CTR_BUSfmt */ 21324 /* nFields */ 1, 21325 /* *fields */ soc_IFP_TO_IFP_SHARED_CTR_BUS_BCM56860_A0fmt_fields, 21326 /* bits */ 97, 21327 /* flags */ 0, 21328 }, 21329 #endif /* chips */ 21330 21331 #if defined(BCM_56850_A0) 21332 { /* SOC_FORMAT_INT_IFP_TO_IFP_SHARED_DATA_BUSfmt */ 21333 /* format IFP_TO_IFP_SHARED_DATA_BUSfmt */ 21334 /* nFields */ 1, 21335 /* *fields */ soc_IFP_TO_IFP_SHARED_DATA_BUSfmt_fields, 21336 /* bits */ 167, 21337 /* flags */ 0, 21338 }, 21339 #endif /* chips */ 21340 21341 #if defined(BCM_56560_A0) 21342 { /* SOC_FORMAT_INT_IFP_TO_IFP_SHARED_DATA_BUS_BCM56560_A0fmt */ 21343 /* format IFP_TO_IFP_SHARED_DATA_BUSfmt */ 21344 /* nFields */ 1, 21345 /* *fields */ soc_IFP_TO_IFP_SHARED_DATA_BUS_BCM56560_A0fmt_fields, 21346 /* bits */ 191, 21347 /* flags */ 0, 21348 }, 21349 #endif /* chips */ 21350 21351 #if defined(BCM_56560_B0) 21352 { /* SOC_FORMAT_INT_IFP_TO_IFP_SHARED_DATA_BUS_BCM56560_B0fmt */ 21353 /* format IFP_TO_IFP_SHARED_DATA_BUSfmt */ 21354 /* nFields */ 1, 21355 /* *fields */ soc_IFP_TO_IFP_SHARED_DATA_BUS_BCM56560_A0fmt_fields, 21356 /* bits */ 191, 21357 /* flags */ 0, 21358 }, 21359 #endif /* chips */ 21360 21361 #if defined(BCM_56670_A0) 21362 { /* SOC_FORMAT_INT_IFP_TO_IFP_SHARED_DATA_BUS_BCM56670_A0fmt */ 21363 /* format IFP_TO_IFP_SHARED_DATA_BUSfmt */ 21364 /* nFields */ 1, 21365 /* *fields */ soc_IFP_TO_IFP_SHARED_DATA_BUS_BCM56560_A0fmt_fields, 21366 /* bits */ 191, 21367 /* flags */ 0, 21368 }, 21369 #endif /* chips */ 21370 21371 #if defined(BCM_56670_B0) 21372 { /* SOC_FORMAT_INT_IFP_TO_IFP_SHARED_DATA_BUS_BCM56670_B0fmt */ 21373 /* format IFP_TO_IFP_SHARED_DATA_BUSfmt */ 21374 /* nFields */ 1, 21375 /* *fields */ soc_IFP_TO_IFP_SHARED_DATA_BUS_BCM56560_A0fmt_fields, 21376 /* bits */ 191, 21377 /* flags */ 0, 21378 }, 21379 #endif /* chips */ 21380 21381 #if defined(BCM_56860_A0) 21382 { /* SOC_FORMAT_INT_IFP_TO_IFP_SHARED_DATA_BUS_BCM56860_A0fmt */ 21383 /* format IFP_TO_IFP_SHARED_DATA_BUSfmt */ 21384 /* nFields */ 1, 21385 /* *fields */ soc_IFP_TO_IFP_SHARED_DATA_BUS_BCM56860_A0fmt_fields, 21386 /* bits */ 191, 21387 /* flags */ 0, 21388 }, 21389 #endif /* chips */ 21390 21391 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) || \ 21392 defined(BCM_56970_A0) || defined(BCM_56980_A0) || \ 21393 defined(BCM_56980_B0) 21394 { /* SOC_FORMAT_INT_IFP_TTL_OVERRIDE_SETfmt */ 21395 /* format IFP_TTL_OVERRIDE_SETfmt */ 21396 /* nFields */ 1, 21397 /* *fields */ soc_IFP_TTL_OVERRIDE_SETfmt_fields, 21398 /* bits */ 1, 21399 /* flags */ 0, 21400 }, 21401 #endif /* chips */ 21402 21403 #if defined(BCM_56370_A0) 21404 { /* SOC_FORMAT_INT_IFP_TTL_OVERRIDE_SET_BCM56370_A0fmt */ 21405 /* format IFP_TTL_OVERRIDE_SETfmt */ 21406 /* nFields */ 1, 21407 /* *fields */ soc_IFP_TTL_OVERRIDE_SET_BCM56870_A0fmt_fields, 21408 /* bits */ 1, 21409 /* flags */ 0, 21410 }, 21411 #endif /* chips */ 21412 21413 #if defined(BCM_56770_A0) 21414 { /* SOC_FORMAT_INT_IFP_TTL_OVERRIDE_SET_BCM56770_A0fmt */ 21415 /* format IFP_TTL_OVERRIDE_SETfmt */ 21416 /* nFields */ 1, 21417 /* *fields */ soc_IFP_TTL_OVERRIDE_SET_BCM56870_A0fmt_fields, 21418 /* bits */ 1, 21419 /* flags */ 0, 21420 }, 21421 #endif /* chips */ 21422 21423 #if defined(BCM_56870_A0) 21424 { /* SOC_FORMAT_INT_IFP_TTL_OVERRIDE_SET_BCM56870_A0fmt */ 21425 /* format IFP_TTL_OVERRIDE_SETfmt */ 21426 /* nFields */ 1, 21427 /* *fields */ soc_IFP_TTL_OVERRIDE_SET_BCM56870_A0fmt_fields, 21428 /* bits */ 1, 21429 /* flags */ 0, 21430 }, 21431 #endif /* chips */ 21432 21433 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 21434 defined(BCM_56870_A0) || defined(BCM_56960_A0) || \ 21435 defined(BCM_56965_A0) || defined(BCM_56970_A0) 21436 { /* SOC_FORMAT_INT_IFP_URPF_OVERRIDE_SETfmt */ 21437 /* format IFP_URPF_OVERRIDE_SETfmt */ 21438 /* nFields */ 1, 21439 /* *fields */ soc_IFP_URPF_OVERRIDE_SETfmt_fields, 21440 /* bits */ 1, 21441 /* flags */ 0, 21442 }, 21443 #endif /* chips */ 21444 21445 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 21446 defined(BCM_56870_A0) 21447 { /* SOC_FORMAT_INT_IFWD1_DOPfmt */ 21448 /* format IFWD1_DOPfmt */ 21449 /* nFields */ 30, 21450 /* *fields */ soc_IFWD1_DOPfmt_fields, 21451 /* bits */ 416, 21452 /* flags */ 0, 21453 }, 21454 #endif /* chips */ 21455 21456 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 21457 defined(BCM_56870_A0) 21458 { /* SOC_FORMAT_INT_IFWD2_DOPfmt */ 21459 /* format IFWD2_DOPfmt */ 21460 /* nFields */ 102, 21461 /* *fields */ soc_IFWD2_DOPfmt_fields, 21462 /* bits */ 4480, 21463 /* flags */ 0, 21464 }, 21465 #endif /* chips */ 21466 21467 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) || \ 21468 defined(BCM_56970_A0) 21469 { /* SOC_FORMAT_INT_IL2LU_DATAfmt */ 21470 /* format IL2LU_DATAfmt */ 21471 /* nFields */ 2, 21472 /* *fields */ soc_IL2LU_DATAfmt_fields, 21473 /* bits */ 106, 21474 /* flags */ 0, 21475 }, 21476 #endif /* chips */ 21477 21478 #if defined(BCM_56370_A0) 21479 { /* SOC_FORMAT_INT_IL2LU_DATA_BCM56370_A0fmt */ 21480 /* format IL2LU_DATAfmt */ 21481 /* nFields */ 2, 21482 /* *fields */ soc_IL2LU_DATA_BCM56870_A0fmt_fields, 21483 /* bits */ 109, 21484 /* flags */ 0, 21485 }, 21486 #endif /* chips */ 21487 21488 #if defined(BCM_56770_A0) 21489 { /* SOC_FORMAT_INT_IL2LU_DATA_BCM56770_A0fmt */ 21490 /* format IL2LU_DATAfmt */ 21491 /* nFields */ 2, 21492 /* *fields */ soc_IL2LU_DATA_BCM56870_A0fmt_fields, 21493 /* bits */ 109, 21494 /* flags */ 0, 21495 }, 21496 #endif /* chips */ 21497 21498 #if defined(BCM_56870_A0) 21499 { /* SOC_FORMAT_INT_IL2LU_DATA_BCM56870_A0fmt */ 21500 /* format IL2LU_DATAfmt */ 21501 /* nFields */ 2, 21502 /* *fields */ soc_IL2LU_DATA_BCM56870_A0fmt_fields, 21503 /* bits */ 109, 21504 /* flags */ 0, 21505 }, 21506 #endif /* chips */ 21507 21508 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) 21509 { /* SOC_FORMAT_INT_IL2LU_TO_L2_MGMT_STATUSfmt */ 21510 /* format IL2LU_TO_L2_MGMT_STATUSfmt */ 21511 /* nFields */ 8, 21512 /* *fields */ soc_IL2LU_TO_L2_MGMT_STATUSfmt_fields, 21513 /* bits */ 29, 21514 /* flags */ 0, 21515 }, 21516 #endif /* chips */ 21517 21518 #if defined(BCM_56370_A0) 21519 { /* SOC_FORMAT_INT_IL2LU_TO_L2_MGMT_STATUS_BCM56370_A0fmt */ 21520 /* format IL2LU_TO_L2_MGMT_STATUSfmt */ 21521 /* nFields */ 8, 21522 /* *fields */ soc_IL2LU_TO_L2_MGMT_STATUS_BCM56870_A0fmt_fields, 21523 /* bits */ 31, 21524 /* flags */ 0, 21525 }, 21526 #endif /* chips */ 21527 21528 #if defined(BCM_56770_A0) 21529 { /* SOC_FORMAT_INT_IL2LU_TO_L2_MGMT_STATUS_BCM56770_A0fmt */ 21530 /* format IL2LU_TO_L2_MGMT_STATUSfmt */ 21531 /* nFields */ 8, 21532 /* *fields */ soc_IL2LU_TO_L2_MGMT_STATUS_BCM56870_A0fmt_fields, 21533 /* bits */ 31, 21534 /* flags */ 0, 21535 }, 21536 #endif /* chips */ 21537 21538 #if defined(BCM_56870_A0) 21539 { /* SOC_FORMAT_INT_IL2LU_TO_L2_MGMT_STATUS_BCM56870_A0fmt */ 21540 /* format IL2LU_TO_L2_MGMT_STATUSfmt */ 21541 /* nFields */ 8, 21542 /* *fields */ soc_IL2LU_TO_L2_MGMT_STATUS_BCM56870_A0fmt_fields, 21543 /* bits */ 31, 21544 /* flags */ 0, 21545 }, 21546 #endif /* chips */ 21547 21548 #if defined(BCM_56970_A0) 21549 { /* SOC_FORMAT_INT_IL2LU_TO_L2_MGMT_STATUS_BCM56970_A0fmt */ 21550 /* format IL2LU_TO_L2_MGMT_STATUSfmt */ 21551 /* nFields */ 8, 21552 /* *fields */ soc_IL2LU_TO_L2_MGMT_STATUS_BCM56970_A0fmt_fields, 21553 /* bits */ 30, 21554 /* flags */ 0, 21555 }, 21556 #endif /* chips */ 21557 21558 #if defined(BCM_56980_A0) 21559 { /* SOC_FORMAT_INT_IL2LU_TO_L2_MGMT_STATUS_BCM56980_A0fmt */ 21560 /* format IL2LU_TO_L2_MGMT_STATUSfmt */ 21561 /* nFields */ 8, 21562 /* *fields */ soc_IL2LU_TO_L2_MGMT_STATUS_BCM56870_A0fmt_fields, 21563 /* bits */ 31, 21564 /* flags */ 0, 21565 }, 21566 #endif /* chips */ 21567 21568 #if defined(BCM_56980_B0) 21569 { /* SOC_FORMAT_INT_IL2LU_TO_L2_MGMT_STATUS_BCM56980_B0fmt */ 21570 /* format IL2LU_TO_L2_MGMT_STATUSfmt */ 21571 /* nFields */ 8, 21572 /* *fields */ soc_IL2LU_TO_L2_MGMT_STATUS_BCM56870_A0fmt_fields, 21573 /* bits */ 31, 21574 /* flags */ 0, 21575 }, 21576 #endif /* chips */ 21577 21578 #if defined(BCM_88732_A0) 21579 { /* SOC_FORMAT_INT_INGRESS_ASSP_HEADERfmt */ 21580 /* format INGRESS_ASSP_HEADERfmt */ 21581 /* nFields */ 33, 21582 /* *fields */ soc_INGRESS_ASSP_HEADERfmt_fields, 21583 /* bits */ 128, 21584 /* flags */ 0, 21585 }, 21586 #endif /* chips */ 21587 21588 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) 21589 { /* SOC_FORMAT_INT_INGRESS_COUNTER_UPDATE_VECTORfmt */ 21590 /* format INGRESS_COUNTER_UPDATE_VECTORfmt */ 21591 /* nFields */ 2, 21592 /* *fields */ soc_INGRESS_COUNTER_UPDATE_VECTORfmt_fields, 21593 /* bits */ 128, 21594 /* flags */ 0, 21595 }, 21596 #endif /* chips */ 21597 21598 #if defined(BCM_56370_A0) 21599 { /* SOC_FORMAT_INT_INGRESS_COUNTER_UPDATE_VECTOR_BCM56370_A0fmt */ 21600 /* format INGRESS_COUNTER_UPDATE_VECTORfmt */ 21601 /* nFields */ 2, 21602 /* *fields */ soc_INGRESS_COUNTER_UPDATE_VECTOR_BCM56370_A0fmt_fields, 21603 /* bits */ 131, 21604 /* flags */ 0, 21605 }, 21606 #endif /* chips */ 21607 21608 #if defined(BCM_56980_A0) 21609 { /* SOC_FORMAT_INT_INGRESS_COUNTER_UPDATE_VECTOR_BCM56980_A0fmt */ 21610 /* format INGRESS_COUNTER_UPDATE_VECTORfmt */ 21611 /* nFields */ 3, 21612 /* *fields */ soc_INGRESS_COUNTER_UPDATE_VECTOR_BCM56980_A0fmt_fields, 21613 /* bits */ 128, 21614 /* flags */ 0, 21615 }, 21616 #endif /* chips */ 21617 21618 #if defined(BCM_56980_B0) 21619 { /* SOC_FORMAT_INT_INGRESS_COUNTER_UPDATE_VECTOR_BCM56980_B0fmt */ 21620 /* format INGRESS_COUNTER_UPDATE_VECTORfmt */ 21621 /* nFields */ 3, 21622 /* *fields */ soc_INGRESS_COUNTER_UPDATE_VECTOR_BCM56980_A0fmt_fields, 21623 /* bits */ 128, 21624 /* flags */ 0, 21625 }, 21626 #endif /* chips */ 21627 21628 #if defined(BCM_56870_A0) 21629 { /* SOC_FORMAT_INT_INGRESS_DOP_TOP_FORMATfmt */ 21630 /* format INGRESS_DOP_TOP_FORMATfmt */ 21631 /* nFields */ 13, 21632 /* *fields */ soc_INGRESS_DOP_TOP_FORMATfmt_fields, 21633 /* bits */ 16320, 21634 /* flags */ 0, 21635 }, 21636 #endif /* chips */ 21637 21638 #if defined(BCM_56370_A0) 21639 { /* SOC_FORMAT_INT_INGRESS_DOP_TOP_FORMAT_BCM56370_A0fmt */ 21640 /* format INGRESS_DOP_TOP_FORMATfmt */ 21641 /* nFields */ 13, 21642 /* *fields */ soc_INGRESS_DOP_TOP_FORMAT_BCM56370_A0fmt_fields, 21643 /* bits */ 16177, 21644 /* flags */ 0, 21645 }, 21646 #endif /* chips */ 21647 21648 #if defined(BCM_56770_A0) 21649 { /* SOC_FORMAT_INT_INGRESS_DOP_TOP_FORMAT_BCM56770_A0fmt */ 21650 /* format INGRESS_DOP_TOP_FORMATfmt */ 21651 /* nFields */ 13, 21652 /* *fields */ soc_INGRESS_DOP_TOP_FORMAT_BCM56770_A0fmt_fields, 21653 /* bits */ 17408, 21654 /* flags */ 0, 21655 }, 21656 #endif /* chips */ 21657 21658 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 21659 defined(BCM_56870_A0) 21660 { /* SOC_FORMAT_INT_INGRESS_FIELD_BUSfmt */ 21661 /* format INGRESS_FIELD_BUSfmt */ 21662 /* nFields */ 40, 21663 /* *fields */ soc_INGRESS_FIELD_BUSfmt_fields, 21664 /* bits */ 1024, 21665 /* flags */ 0, 21666 }, 21667 #endif /* chips */ 21668 21669 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 21670 defined(BCM_56870_A0) 21671 { /* SOC_FORMAT_INT_INGRESS_FIELD_BUS_1_L2_FIELDS_DOPfmt */ 21672 /* format INGRESS_FIELD_BUS_1_L2_FIELDS_DOPfmt */ 21673 /* nFields */ 7, 21674 /* *fields */ soc_INGRESS_FIELD_BUS_1_L2_FIELDS_DOPfmt_fields, 21675 /* bits */ 224, 21676 /* flags */ 0, 21677 }, 21678 #endif /* chips */ 21679 21680 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 21681 defined(BCM_56870_A0) 21682 { /* SOC_FORMAT_INT_INGRESS_FIELD_BUS_1_L3_FIELDS_DOPfmt */ 21683 /* format INGRESS_FIELD_BUS_1_L3_FIELDS_DOPfmt */ 21684 /* nFields */ 3, 21685 /* *fields */ soc_INGRESS_FIELD_BUS_1_L3_FIELDS_DOPfmt_fields, 21686 /* bits */ 256, 21687 /* flags */ 0, 21688 }, 21689 #endif /* chips */ 21690 21691 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 21692 defined(BCM_56870_A0) 21693 { /* SOC_FORMAT_INT_INGRESS_FIELD_BUS_1_L4_FIELDS_DOPfmt */ 21694 /* format INGRESS_FIELD_BUS_1_L4_FIELDS_DOPfmt */ 21695 /* nFields */ 2, 21696 /* *fields */ soc_INGRESS_FIELD_BUS_1_L4_FIELDS_DOPfmt_fields, 21697 /* bits */ 32, 21698 /* flags */ 0, 21699 }, 21700 #endif /* chips */ 21701 21702 #if defined(BCM_56870_A0) 21703 { /* SOC_FORMAT_INT_INGRESS_FIELD_BUS_2_L2_FIELDS_DOPfmt */ 21704 /* format INGRESS_FIELD_BUS_2_L2_FIELDS_DOPfmt */ 21705 /* nFields */ 7, 21706 /* *fields */ soc_INGRESS_FIELD_BUS_1_L2_FIELDS_DOPfmt_fields, 21707 /* bits */ 224, 21708 /* flags */ 0, 21709 }, 21710 #endif /* chips */ 21711 21712 #if defined(BCM_56370_A0) 21713 { /* SOC_FORMAT_INT_INGRESS_FIELD_BUS_2_L2_FIELDS_DOP_BCM56370_A0fmt */ 21714 /* format INGRESS_FIELD_BUS_2_L2_FIELDS_DOPfmt */ 21715 /* nFields */ 7, 21716 /* *fields */ soc_INGRESS_FIELD_BUS_1_L2_FIELDS_DOPfmt_fields, 21717 /* bits */ 224, 21718 /* flags */ 0, 21719 }, 21720 #endif /* chips */ 21721 21722 #if defined(BCM_56770_A0) 21723 { /* SOC_FORMAT_INT_INGRESS_FIELD_BUS_2_L2_FIELDS_DOP_BCM56770_A0fmt */ 21724 /* format INGRESS_FIELD_BUS_2_L2_FIELDS_DOPfmt */ 21725 /* nFields */ 7, 21726 /* *fields */ soc_INGRESS_FIELD_BUS_1_L2_FIELDS_DOPfmt_fields, 21727 /* bits */ 224, 21728 /* flags */ 0, 21729 }, 21730 #endif /* chips */ 21731 21732 #if defined(BCM_56870_A0) 21733 { /* SOC_FORMAT_INT_INGRESS_FIELD_BUS_2_L3_FIELDS_DOPfmt */ 21734 /* format INGRESS_FIELD_BUS_2_L3_FIELDS_DOPfmt */ 21735 /* nFields */ 3, 21736 /* *fields */ soc_INGRESS_FIELD_BUS_1_L3_FIELDS_DOPfmt_fields, 21737 /* bits */ 256, 21738 /* flags */ 0, 21739 }, 21740 #endif /* chips */ 21741 21742 #if defined(BCM_56370_A0) 21743 { /* SOC_FORMAT_INT_INGRESS_FIELD_BUS_2_L3_FIELDS_DOP_BCM56370_A0fmt */ 21744 /* format INGRESS_FIELD_BUS_2_L3_FIELDS_DOPfmt */ 21745 /* nFields */ 3, 21746 /* *fields */ soc_INGRESS_FIELD_BUS_1_L3_FIELDS_DOPfmt_fields, 21747 /* bits */ 256, 21748 /* flags */ 0, 21749 }, 21750 #endif /* chips */ 21751 21752 #if defined(BCM_56770_A0) 21753 { /* SOC_FORMAT_INT_INGRESS_FIELD_BUS_2_L3_FIELDS_DOP_BCM56770_A0fmt */ 21754 /* format INGRESS_FIELD_BUS_2_L3_FIELDS_DOPfmt */ 21755 /* nFields */ 3, 21756 /* *fields */ soc_INGRESS_FIELD_BUS_1_L3_FIELDS_DOPfmt_fields, 21757 /* bits */ 256, 21758 /* flags */ 0, 21759 }, 21760 #endif /* chips */ 21761 21762 #if defined(BCM_56870_A0) 21763 { /* SOC_FORMAT_INT_INGRESS_FIELD_BUS_2_L4_FIELDS_DOPfmt */ 21764 /* format INGRESS_FIELD_BUS_2_L4_FIELDS_DOPfmt */ 21765 /* nFields */ 2, 21766 /* *fields */ soc_INGRESS_FIELD_BUS_1_L4_FIELDS_DOPfmt_fields, 21767 /* bits */ 32, 21768 /* flags */ 0, 21769 }, 21770 #endif /* chips */ 21771 21772 #if defined(BCM_56370_A0) 21773 { /* SOC_FORMAT_INT_INGRESS_FIELD_BUS_2_L4_FIELDS_DOP_BCM56370_A0fmt */ 21774 /* format INGRESS_FIELD_BUS_2_L4_FIELDS_DOPfmt */ 21775 /* nFields */ 2, 21776 /* *fields */ soc_INGRESS_FIELD_BUS_1_L4_FIELDS_DOPfmt_fields, 21777 /* bits */ 32, 21778 /* flags */ 0, 21779 }, 21780 #endif /* chips */ 21781 21782 #if defined(BCM_56770_A0) 21783 { /* SOC_FORMAT_INT_INGRESS_FIELD_BUS_2_L4_FIELDS_DOP_BCM56770_A0fmt */ 21784 /* format INGRESS_FIELD_BUS_2_L4_FIELDS_DOPfmt */ 21785 /* nFields */ 2, 21786 /* *fields */ soc_INGRESS_FIELD_BUS_1_L4_FIELDS_DOPfmt_fields, 21787 /* bits */ 32, 21788 /* flags */ 0, 21789 }, 21790 #endif /* chips */ 21791 21792 #if defined(BCM_56870_A0) 21793 { /* SOC_FORMAT_INT_INGRESS_OBJECT_BUSfmt */ 21794 /* format INGRESS_OBJECT_BUSfmt */ 21795 /* nFields */ 87, 21796 /* *fields */ soc_INGRESS_OBJECT_BUSfmt_fields, 21797 /* bits */ 814, 21798 /* flags */ 0, 21799 }, 21800 #endif /* chips */ 21801 21802 #if defined(BCM_56370_A0) 21803 { /* SOC_FORMAT_INT_INGRESS_OBJECT_BUS_BCM56370_A0fmt */ 21804 /* format INGRESS_OBJECT_BUSfmt */ 21805 /* nFields */ 94, 21806 /* *fields */ soc_INGRESS_OBJECT_BUS_BCM56370_A0fmt_fields, 21807 /* bits */ 826, 21808 /* flags */ 0, 21809 }, 21810 #endif /* chips */ 21811 21812 #if defined(BCM_56770_A0) 21813 { /* SOC_FORMAT_INT_INGRESS_OBJECT_BUS_BCM56770_A0fmt */ 21814 /* format INGRESS_OBJECT_BUSfmt */ 21815 /* nFields */ 87, 21816 /* *fields */ soc_INGRESS_OBJECT_BUS_BCM56770_A0fmt_fields, 21817 /* bits */ 825, 21818 /* flags */ 0, 21819 }, 21820 #endif /* chips */ 21821 21822 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 21823 defined(BCM_56870_A0) || defined(BCM_56960_A0) || \ 21824 defined(BCM_56965_A0) || defined(BCM_56970_A0) || \ 21825 defined(BCM_56980_A0) || defined(BCM_56980_B0) 21826 { /* SOC_FORMAT_INT_ING_DISTR_MONITOR_BUS_POOLfmt */ 21827 /* format ING_DISTR_MONITOR_BUS_POOLfmt */ 21828 /* nFields */ 2, 21829 /* *fields */ soc_ING_DISTR_MONITOR_BUS_POOLfmt_fields, 21830 /* bits */ 7, 21831 /* flags */ 0, 21832 }, 21833 #endif /* chips */ 21834 21835 #if defined(BCM_56960_A0) 21836 { /* SOC_FORMAT_INT_ING_ECN_COUNTER_COV_DEFSfmt */ 21837 /* format ING_ECN_COUNTER_COV_DEFSfmt */ 21838 /* nFields */ 6, 21839 /* *fields */ soc_ISC_HG_STATS_COV_DEFS_BCM53400_A0fmt_fields, 21840 /* bits */ 11, 21841 /* flags */ 0, 21842 }, 21843 #endif /* chips */ 21844 21845 #if defined(BCM_56370_A0) 21846 { /* SOC_FORMAT_INT_ING_ECN_COUNTER_COV_DEFS_BCM56370_A0fmt */ 21847 /* format ING_ECN_COUNTER_COV_DEFSfmt */ 21848 /* nFields */ 6, 21849 /* *fields */ soc_EGR_FCOE_DELIMITER_ERROR_FRAMES_TABLE_COV_DEFS_BCM56960_A0fmt_fields, 21850 /* bits */ 13, 21851 /* flags */ 0, 21852 }, 21853 #endif /* chips */ 21854 21855 #if defined(BCM_56770_A0) 21856 { /* SOC_FORMAT_INT_ING_ECN_COUNTER_COV_DEFS_BCM56770_A0fmt */ 21857 /* format ING_ECN_COUNTER_COV_DEFSfmt */ 21858 /* nFields */ 6, 21859 /* *fields */ soc_EGR_FCOE_DELIMITER_ERROR_FRAMES_TABLE_COV_DEFS_BCM56960_A0fmt_fields, 21860 /* bits */ 13, 21861 /* flags */ 0, 21862 }, 21863 #endif /* chips */ 21864 21865 #if defined(BCM_56870_A0) 21866 { /* SOC_FORMAT_INT_ING_ECN_COUNTER_COV_DEFS_BCM56870_A0fmt */ 21867 /* format ING_ECN_COUNTER_COV_DEFSfmt */ 21868 /* nFields */ 6, 21869 /* *fields */ soc_EGR_FCOE_DELIMITER_ERROR_FRAMES_TABLE_COV_DEFS_BCM56960_A0fmt_fields, 21870 /* bits */ 13, 21871 /* flags */ 0, 21872 }, 21873 #endif /* chips */ 21874 21875 #if defined(BCM_56965_A0) 21876 { /* SOC_FORMAT_INT_ING_ECN_COUNTER_COV_DEFS_BCM56965_A0fmt */ 21877 /* format ING_ECN_COUNTER_COV_DEFSfmt */ 21878 /* nFields */ 6, 21879 /* *fields */ soc_ISC_HG_STATS_COV_DEFS_BCM53400_A0fmt_fields, 21880 /* bits */ 11, 21881 /* flags */ 0, 21882 }, 21883 #endif /* chips */ 21884 21885 #if defined(BCM_56970_A0) 21886 { /* SOC_FORMAT_INT_ING_ECN_COUNTER_COV_DEFS_BCM56970_A0fmt */ 21887 /* format ING_ECN_COUNTER_COV_DEFSfmt */ 21888 /* nFields */ 6, 21889 /* *fields */ soc_ISC_HG_STATS_COV_DEFS_BCM53400_A0fmt_fields, 21890 /* bits */ 11, 21891 /* flags */ 0, 21892 }, 21893 #endif /* chips */ 21894 21895 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 21896 defined(BCM_56870_A0) 21897 { /* SOC_FORMAT_INT_ING_ETAG_PCP_MAPPING_INDEXfmt */ 21898 /* format ING_ETAG_PCP_MAPPING_INDEXfmt */ 21899 /* nFields */ 3, 21900 /* *fields */ soc_ING_ETAG_PCP_MAPPING_INDEXfmt_fields, 21901 /* bits */ 10, 21902 /* flags */ 0, 21903 }, 21904 #endif /* chips */ 21905 21906 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 21907 defined(BCM_56870_A0) 21908 { /* SOC_FORMAT_INT_ING_EXP_TO_ECN_MAPPING_INDEXfmt */ 21909 /* format ING_EXP_TO_ECN_MAPPING_INDEXfmt */ 21910 /* nFields */ 4, 21911 /* *fields */ soc_ING_EXP_TO_ECN_MAPPING_INDEXfmt_fields, 21912 /* bits */ 8, 21913 /* flags */ 0, 21914 }, 21915 #endif /* chips */ 21916 21917 #if defined(BCM_56440_A0) 21918 { /* SOC_FORMAT_INT_ING_FLEX_CTR_ADDR_DEFINEfmt */ 21919 /* format ING_FLEX_CTR_ADDR_DEFINEfmt */ 21920 /* nFields */ 2, 21921 /* *fields */ soc_EGR_FLEX_CTR_ADDR_DEFINEfmt_fields, 21922 /* bits */ 20, 21923 /* flags */ 0, 21924 }, 21925 #endif /* chips */ 21926 21927 #if defined(BCM_56260_A0) 21928 { /* SOC_FORMAT_INT_ING_FLEX_CTR_ADDR_DEFINE_BCM56260_A0fmt */ 21929 /* format ING_FLEX_CTR_ADDR_DEFINEfmt */ 21930 /* nFields */ 2, 21931 /* *fields */ soc_EGR_FLEX_CTR_ADDR_DEFINE_BCM56960_A0fmt_fields, 21932 /* bits */ 26, 21933 /* flags */ 0, 21934 }, 21935 #endif /* chips */ 21936 21937 #if defined(BCM_56260_B0) 21938 { /* SOC_FORMAT_INT_ING_FLEX_CTR_ADDR_DEFINE_BCM56260_B0fmt */ 21939 /* format ING_FLEX_CTR_ADDR_DEFINEfmt */ 21940 /* nFields */ 2, 21941 /* *fields */ soc_EGR_FLEX_CTR_ADDR_DEFINE_BCM56960_A0fmt_fields, 21942 /* bits */ 26, 21943 /* flags */ 0, 21944 }, 21945 #endif /* chips */ 21946 21947 #if defined(BCM_56270_A0) 21948 { /* SOC_FORMAT_INT_ING_FLEX_CTR_ADDR_DEFINE_BCM56270_A0fmt */ 21949 /* format ING_FLEX_CTR_ADDR_DEFINEfmt */ 21950 /* nFields */ 2, 21951 /* *fields */ soc_EGR_FLEX_CTR_ADDR_DEFINE_BCM56960_A0fmt_fields, 21952 /* bits */ 26, 21953 /* flags */ 0, 21954 }, 21955 #endif /* chips */ 21956 21957 #if defined(BCM_56340_A0) 21958 { /* SOC_FORMAT_INT_ING_FLEX_CTR_ADDR_DEFINE_BCM56340_A0fmt */ 21959 /* format ING_FLEX_CTR_ADDR_DEFINEfmt */ 21960 /* nFields */ 2, 21961 /* *fields */ soc_EGR_FLEX_CTR_ADDR_DEFINE_BCM56640_A0fmt_fields, 21962 /* bits */ 26, 21963 /* flags */ 0, 21964 }, 21965 #endif /* chips */ 21966 21967 #if defined(BCM_56370_A0) 21968 { /* SOC_FORMAT_INT_ING_FLEX_CTR_ADDR_DEFINE_BCM56370_A0fmt */ 21969 /* format ING_FLEX_CTR_ADDR_DEFINEfmt */ 21970 /* nFields */ 2, 21971 /* *fields */ soc_EGR_FLEX_CTR_ADDR_DEFINE_BCM56970_A0fmt_fields, 21972 /* bits */ 17, 21973 /* flags */ 0, 21974 }, 21975 #endif /* chips */ 21976 21977 #if defined(BCM_56440_B0) 21978 { /* SOC_FORMAT_INT_ING_FLEX_CTR_ADDR_DEFINE_BCM56440_B0fmt */ 21979 /* format ING_FLEX_CTR_ADDR_DEFINEfmt */ 21980 /* nFields */ 2, 21981 /* *fields */ soc_EGR_FLEX_CTR_ADDR_DEFINEfmt_fields, 21982 /* bits */ 20, 21983 /* flags */ 0, 21984 }, 21985 #endif /* chips */ 21986 21987 #if defined(BCM_56450_A0) 21988 { /* SOC_FORMAT_INT_ING_FLEX_CTR_ADDR_DEFINE_BCM56450_A0fmt */ 21989 /* format ING_FLEX_CTR_ADDR_DEFINEfmt */ 21990 /* nFields */ 2, 21991 /* *fields */ soc_EGR_FLEX_CTR_ADDR_DEFINE_BCM56640_A0fmt_fields, 21992 /* bits */ 26, 21993 /* flags */ 0, 21994 }, 21995 #endif /* chips */ 21996 21997 #if defined(BCM_56450_B0) 21998 { /* SOC_FORMAT_INT_ING_FLEX_CTR_ADDR_DEFINE_BCM56450_B0fmt */ 21999 /* format ING_FLEX_CTR_ADDR_DEFINEfmt */ 22000 /* nFields */ 2, 22001 /* *fields */ soc_EGR_FLEX_CTR_ADDR_DEFINE_BCM56640_A0fmt_fields, 22002 /* bits */ 26, 22003 /* flags */ 0, 22004 }, 22005 #endif /* chips */ 22006 22007 #if defined(BCM_56450_B1) 22008 { /* SOC_FORMAT_INT_ING_FLEX_CTR_ADDR_DEFINE_BCM56450_B1fmt */ 22009 /* format ING_FLEX_CTR_ADDR_DEFINEfmt */ 22010 /* nFields */ 2, 22011 /* *fields */ soc_EGR_FLEX_CTR_ADDR_DEFINE_BCM56640_A0fmt_fields, 22012 /* bits */ 26, 22013 /* flags */ 0, 22014 }, 22015 #endif /* chips */ 22016 22017 #if defined(BCM_56560_A0) 22018 { /* SOC_FORMAT_INT_ING_FLEX_CTR_ADDR_DEFINE_BCM56560_A0fmt */ 22019 /* format ING_FLEX_CTR_ADDR_DEFINEfmt */ 22020 /* nFields */ 2, 22021 /* *fields */ soc_EGR_FLEX_CTR_ADDR_DEFINE_BCM56960_A0fmt_fields, 22022 /* bits */ 26, 22023 /* flags */ 0, 22024 }, 22025 #endif /* chips */ 22026 22027 #if defined(BCM_56560_B0) 22028 { /* SOC_FORMAT_INT_ING_FLEX_CTR_ADDR_DEFINE_BCM56560_B0fmt */ 22029 /* format ING_FLEX_CTR_ADDR_DEFINEfmt */ 22030 /* nFields */ 2, 22031 /* *fields */ soc_EGR_FLEX_CTR_ADDR_DEFINE_BCM56960_A0fmt_fields, 22032 /* bits */ 26, 22033 /* flags */ 0, 22034 }, 22035 #endif /* chips */ 22036 22037 #if defined(BCM_56640_A0) 22038 { /* SOC_FORMAT_INT_ING_FLEX_CTR_ADDR_DEFINE_BCM56640_A0fmt */ 22039 /* format ING_FLEX_CTR_ADDR_DEFINEfmt */ 22040 /* nFields */ 2, 22041 /* *fields */ soc_EGR_FLEX_CTR_ADDR_DEFINE_BCM56640_A0fmt_fields, 22042 /* bits */ 26, 22043 /* flags */ 0, 22044 }, 22045 #endif /* chips */ 22046 22047 #if defined(BCM_56670_A0) 22048 { /* SOC_FORMAT_INT_ING_FLEX_CTR_ADDR_DEFINE_BCM56670_A0fmt */ 22049 /* format ING_FLEX_CTR_ADDR_DEFINEfmt */ 22050 /* nFields */ 2, 22051 /* *fields */ soc_EGR_FLEX_CTR_ADDR_DEFINE_BCM56960_A0fmt_fields, 22052 /* bits */ 26, 22053 /* flags */ 0, 22054 }, 22055 #endif /* chips */ 22056 22057 #if defined(BCM_56670_B0) 22058 { /* SOC_FORMAT_INT_ING_FLEX_CTR_ADDR_DEFINE_BCM56670_B0fmt */ 22059 /* format ING_FLEX_CTR_ADDR_DEFINEfmt */ 22060 /* nFields */ 2, 22061 /* *fields */ soc_EGR_FLEX_CTR_ADDR_DEFINE_BCM56960_A0fmt_fields, 22062 /* bits */ 26, 22063 /* flags */ 0, 22064 }, 22065 #endif /* chips */ 22066 22067 #if defined(BCM_56770_A0) 22068 { /* SOC_FORMAT_INT_ING_FLEX_CTR_ADDR_DEFINE_BCM56770_A0fmt */ 22069 /* format ING_FLEX_CTR_ADDR_DEFINEfmt */ 22070 /* nFields */ 2, 22071 /* *fields */ soc_EGR_FLEX_CTR_ADDR_DEFINE_BCM56970_A0fmt_fields, 22072 /* bits */ 17, 22073 /* flags */ 0, 22074 }, 22075 #endif /* chips */ 22076 22077 #if defined(BCM_56850_A0) 22078 { /* SOC_FORMAT_INT_ING_FLEX_CTR_ADDR_DEFINE_BCM56850_A0fmt */ 22079 /* format ING_FLEX_CTR_ADDR_DEFINEfmt */ 22080 /* nFields */ 2, 22081 /* *fields */ soc_EGR_FLEX_CTR_ADDR_DEFINE_BCM56640_A0fmt_fields, 22082 /* bits */ 26, 22083 /* flags */ 0, 22084 }, 22085 #endif /* chips */ 22086 22087 #if defined(BCM_56860_A0) 22088 { /* SOC_FORMAT_INT_ING_FLEX_CTR_ADDR_DEFINE_BCM56860_A0fmt */ 22089 /* format ING_FLEX_CTR_ADDR_DEFINEfmt */ 22090 /* nFields */ 2, 22091 /* *fields */ soc_EGR_FLEX_CTR_ADDR_DEFINE_BCM56640_A0fmt_fields, 22092 /* bits */ 26, 22093 /* flags */ 0, 22094 }, 22095 #endif /* chips */ 22096 22097 #if defined(BCM_56870_A0) 22098 { /* SOC_FORMAT_INT_ING_FLEX_CTR_ADDR_DEFINE_BCM56870_A0fmt */ 22099 /* format ING_FLEX_CTR_ADDR_DEFINEfmt */ 22100 /* nFields */ 2, 22101 /* *fields */ soc_EGR_FLEX_CTR_ADDR_DEFINE_BCM56970_A0fmt_fields, 22102 /* bits */ 17, 22103 /* flags */ 0, 22104 }, 22105 #endif /* chips */ 22106 22107 #if defined(BCM_56960_A0) 22108 { /* SOC_FORMAT_INT_ING_FLEX_CTR_ADDR_DEFINE_BCM56960_A0fmt */ 22109 /* format ING_FLEX_CTR_ADDR_DEFINEfmt */ 22110 /* nFields */ 2, 22111 /* *fields */ soc_EGR_FLEX_CTR_ADDR_DEFINE_BCM56960_A0fmt_fields, 22112 /* bits */ 26, 22113 /* flags */ 0, 22114 }, 22115 #endif /* chips */ 22116 22117 #if defined(BCM_56965_A0) 22118 { /* SOC_FORMAT_INT_ING_FLEX_CTR_ADDR_DEFINE_BCM56965_A0fmt */ 22119 /* format ING_FLEX_CTR_ADDR_DEFINEfmt */ 22120 /* nFields */ 2, 22121 /* *fields */ soc_EGR_FLEX_CTR_ADDR_DEFINE_BCM56960_A0fmt_fields, 22122 /* bits */ 26, 22123 /* flags */ 0, 22124 }, 22125 #endif /* chips */ 22126 22127 #if defined(BCM_56970_A0) 22128 { /* SOC_FORMAT_INT_ING_FLEX_CTR_ADDR_DEFINE_BCM56970_A0fmt */ 22129 /* format ING_FLEX_CTR_ADDR_DEFINEfmt */ 22130 /* nFields */ 2, 22131 /* *fields */ soc_EGR_FLEX_CTR_ADDR_DEFINE_BCM56970_A0fmt_fields, 22132 /* bits */ 17, 22133 /* flags */ 0, 22134 }, 22135 #endif /* chips */ 22136 22137 #if defined(BCM_56980_A0) 22138 { /* SOC_FORMAT_INT_ING_FLEX_CTR_ADDR_DEFINE_BCM56980_A0fmt */ 22139 /* format ING_FLEX_CTR_ADDR_DEFINEfmt */ 22140 /* nFields */ 2, 22141 /* *fields */ soc_EGR_FLEX_CTR_ADDR_DEFINE_BCM56970_A0fmt_fields, 22142 /* bits */ 17, 22143 /* flags */ 0, 22144 }, 22145 #endif /* chips */ 22146 22147 #if defined(BCM_56980_B0) 22148 { /* SOC_FORMAT_INT_ING_FLEX_CTR_ADDR_DEFINE_BCM56980_B0fmt */ 22149 /* format ING_FLEX_CTR_ADDR_DEFINEfmt */ 22150 /* nFields */ 2, 22151 /* *fields */ soc_EGR_FLEX_CTR_ADDR_DEFINE_BCM56970_A0fmt_fields, 22152 /* bits */ 17, 22153 /* flags */ 0, 22154 }, 22155 #endif /* chips */ 22156 22157 #if defined(BCM_56440_A0) 22158 { /* SOC_FORMAT_INT_ING_FLEX_CTR_BUSfmt */ 22159 /* format ING_FLEX_CTR_BUSfmt */ 22160 /* nFields */ 8, 22161 /* *fields */ soc_EGR_FLEX_CTR_BUSfmt_fields, 22162 /* bits */ 128, 22163 /* flags */ 0, 22164 }, 22165 #endif /* chips */ 22166 22167 #if defined(BCM_56260_A0) 22168 { /* SOC_FORMAT_INT_ING_FLEX_CTR_BUS_BCM56260_A0fmt */ 22169 /* format ING_FLEX_CTR_BUSfmt */ 22170 /* nFields */ 8, 22171 /* *fields */ soc_ING_FLEX_CTR_BUS_BCM56560_A0fmt_fields, 22172 /* bits */ 128, 22173 /* flags */ 0, 22174 }, 22175 #endif /* chips */ 22176 22177 #if defined(BCM_56260_B0) 22178 { /* SOC_FORMAT_INT_ING_FLEX_CTR_BUS_BCM56260_B0fmt */ 22179 /* format ING_FLEX_CTR_BUSfmt */ 22180 /* nFields */ 8, 22181 /* *fields */ soc_ING_FLEX_CTR_BUS_BCM56560_A0fmt_fields, 22182 /* bits */ 128, 22183 /* flags */ 0, 22184 }, 22185 #endif /* chips */ 22186 22187 #if defined(BCM_56270_A0) 22188 { /* SOC_FORMAT_INT_ING_FLEX_CTR_BUS_BCM56270_A0fmt */ 22189 /* format ING_FLEX_CTR_BUSfmt */ 22190 /* nFields */ 8, 22191 /* *fields */ soc_EGR_FLEX_CTR_BUS_BCM56270_A0fmt_fields, 22192 /* bits */ 128, 22193 /* flags */ 0, 22194 }, 22195 #endif /* chips */ 22196 22197 #if defined(BCM_56340_A0) 22198 { /* SOC_FORMAT_INT_ING_FLEX_CTR_BUS_BCM56340_A0fmt */ 22199 /* format ING_FLEX_CTR_BUSfmt */ 22200 /* nFields */ 8, 22201 /* *fields */ soc_EGR_FLEX_CTR_BUS_BCM56340_A0fmt_fields, 22202 /* bits */ 104, 22203 /* flags */ 0, 22204 }, 22205 #endif /* chips */ 22206 22207 #if defined(BCM_56370_A0) 22208 { /* SOC_FORMAT_INT_ING_FLEX_CTR_BUS_BCM56370_A0fmt */ 22209 /* format ING_FLEX_CTR_BUSfmt */ 22210 /* nFields */ 20, 22211 /* *fields */ soc_ING_FLEX_CTR_BUS_BCM56960_A0fmt_fields, 22212 /* bits */ 320, 22213 /* flags */ 0, 22214 }, 22215 #endif /* chips */ 22216 22217 #if defined(BCM_56440_B0) 22218 { /* SOC_FORMAT_INT_ING_FLEX_CTR_BUS_BCM56440_B0fmt */ 22219 /* format ING_FLEX_CTR_BUSfmt */ 22220 /* nFields */ 8, 22221 /* *fields */ soc_EGR_FLEX_CTR_BUSfmt_fields, 22222 /* bits */ 128, 22223 /* flags */ 0, 22224 }, 22225 #endif /* chips */ 22226 22227 #if defined(BCM_56450_A0) 22228 { /* SOC_FORMAT_INT_ING_FLEX_CTR_BUS_BCM56450_A0fmt */ 22229 /* format ING_FLEX_CTR_BUSfmt */ 22230 /* nFields */ 8, 22231 /* *fields */ soc_EGR_FLEX_CTR_BUS_BCM56640_A0fmt_fields, 22232 /* bits */ 128, 22233 /* flags */ 0, 22234 }, 22235 #endif /* chips */ 22236 22237 #if defined(BCM_56450_B0) 22238 { /* SOC_FORMAT_INT_ING_FLEX_CTR_BUS_BCM56450_B0fmt */ 22239 /* format ING_FLEX_CTR_BUSfmt */ 22240 /* nFields */ 8, 22241 /* *fields */ soc_EGR_FLEX_CTR_BUS_BCM56640_A0fmt_fields, 22242 /* bits */ 128, 22243 /* flags */ 0, 22244 }, 22245 #endif /* chips */ 22246 22247 #if defined(BCM_56450_B1) 22248 { /* SOC_FORMAT_INT_ING_FLEX_CTR_BUS_BCM56450_B1fmt */ 22249 /* format ING_FLEX_CTR_BUSfmt */ 22250 /* nFields */ 8, 22251 /* *fields */ soc_EGR_FLEX_CTR_BUS_BCM56640_A0fmt_fields, 22252 /* bits */ 128, 22253 /* flags */ 0, 22254 }, 22255 #endif /* chips */ 22256 22257 #if defined(BCM_56560_A0) 22258 { /* SOC_FORMAT_INT_ING_FLEX_CTR_BUS_BCM56560_A0fmt */ 22259 /* format ING_FLEX_CTR_BUSfmt */ 22260 /* nFields */ 8, 22261 /* *fields */ soc_ING_FLEX_CTR_BUS_BCM56560_A0fmt_fields, 22262 /* bits */ 128, 22263 /* flags */ 0, 22264 }, 22265 #endif /* chips */ 22266 22267 #if defined(BCM_56560_B0) 22268 { /* SOC_FORMAT_INT_ING_FLEX_CTR_BUS_BCM56560_B0fmt */ 22269 /* format ING_FLEX_CTR_BUSfmt */ 22270 /* nFields */ 8, 22271 /* *fields */ soc_ING_FLEX_CTR_BUS_BCM56560_A0fmt_fields, 22272 /* bits */ 128, 22273 /* flags */ 0, 22274 }, 22275 #endif /* chips */ 22276 22277 #if defined(BCM_56640_A0) 22278 { /* SOC_FORMAT_INT_ING_FLEX_CTR_BUS_BCM56640_A0fmt */ 22279 /* format ING_FLEX_CTR_BUSfmt */ 22280 /* nFields */ 16, 22281 /* *fields */ soc_ING_FLEX_CTR_BUSfmt_fields, 22282 /* bits */ 256, 22283 /* flags */ 0, 22284 }, 22285 #endif /* chips */ 22286 22287 #if defined(BCM_56670_A0) 22288 { /* SOC_FORMAT_INT_ING_FLEX_CTR_BUS_BCM56670_A0fmt */ 22289 /* format ING_FLEX_CTR_BUSfmt */ 22290 /* nFields */ 8, 22291 /* *fields */ soc_ING_FLEX_CTR_BUS_BCM56560_A0fmt_fields, 22292 /* bits */ 128, 22293 /* flags */ 0, 22294 }, 22295 #endif /* chips */ 22296 22297 #if defined(BCM_56670_B0) 22298 { /* SOC_FORMAT_INT_ING_FLEX_CTR_BUS_BCM56670_B0fmt */ 22299 /* format ING_FLEX_CTR_BUSfmt */ 22300 /* nFields */ 8, 22301 /* *fields */ soc_ING_FLEX_CTR_BUS_BCM56560_A0fmt_fields, 22302 /* bits */ 128, 22303 /* flags */ 0, 22304 }, 22305 #endif /* chips */ 22306 22307 #if defined(BCM_56770_A0) 22308 { /* SOC_FORMAT_INT_ING_FLEX_CTR_BUS_BCM56770_A0fmt */ 22309 /* format ING_FLEX_CTR_BUSfmt */ 22310 /* nFields */ 20, 22311 /* *fields */ soc_ING_FLEX_CTR_BUS_BCM56960_A0fmt_fields, 22312 /* bits */ 320, 22313 /* flags */ 0, 22314 }, 22315 #endif /* chips */ 22316 22317 #if defined(BCM_56850_A0) 22318 { /* SOC_FORMAT_INT_ING_FLEX_CTR_BUS_BCM56850_A0fmt */ 22319 /* format ING_FLEX_CTR_BUSfmt */ 22320 /* nFields */ 8, 22321 /* *fields */ soc_EGR_FLEX_CTR_BUS_BCM56640_A0fmt_fields, 22322 /* bits */ 128, 22323 /* flags */ 0, 22324 }, 22325 #endif /* chips */ 22326 22327 #if defined(BCM_56860_A0) 22328 { /* SOC_FORMAT_INT_ING_FLEX_CTR_BUS_BCM56860_A0fmt */ 22329 /* format ING_FLEX_CTR_BUSfmt */ 22330 /* nFields */ 8, 22331 /* *fields */ soc_EGR_FLEX_CTR_BUS_BCM56640_A0fmt_fields, 22332 /* bits */ 128, 22333 /* flags */ 0, 22334 }, 22335 #endif /* chips */ 22336 22337 #if defined(BCM_56870_A0) 22338 { /* SOC_FORMAT_INT_ING_FLEX_CTR_BUS_BCM56870_A0fmt */ 22339 /* format ING_FLEX_CTR_BUSfmt */ 22340 /* nFields */ 20, 22341 /* *fields */ soc_ING_FLEX_CTR_BUS_BCM56960_A0fmt_fields, 22342 /* bits */ 320, 22343 /* flags */ 0, 22344 }, 22345 #endif /* chips */ 22346 22347 #if defined(BCM_56960_A0) 22348 { /* SOC_FORMAT_INT_ING_FLEX_CTR_BUS_BCM56960_A0fmt */ 22349 /* format ING_FLEX_CTR_BUSfmt */ 22350 /* nFields */ 20, 22351 /* *fields */ soc_ING_FLEX_CTR_BUS_BCM56960_A0fmt_fields, 22352 /* bits */ 320, 22353 /* flags */ 0, 22354 }, 22355 #endif /* chips */ 22356 22357 #if defined(BCM_56965_A0) 22358 { /* SOC_FORMAT_INT_ING_FLEX_CTR_BUS_BCM56965_A0fmt */ 22359 /* format ING_FLEX_CTR_BUSfmt */ 22360 /* nFields */ 20, 22361 /* *fields */ soc_ING_FLEX_CTR_BUS_BCM56960_A0fmt_fields, 22362 /* bits */ 320, 22363 /* flags */ 0, 22364 }, 22365 #endif /* chips */ 22366 22367 #if defined(BCM_56970_A0) 22368 { /* SOC_FORMAT_INT_ING_FLEX_CTR_BUS_BCM56970_A0fmt */ 22369 /* format ING_FLEX_CTR_BUSfmt */ 22370 /* nFields */ 20, 22371 /* *fields */ soc_ING_FLEX_CTR_BUS_BCM56960_A0fmt_fields, 22372 /* bits */ 320, 22373 /* flags */ 0, 22374 }, 22375 #endif /* chips */ 22376 22377 #if defined(BCM_56980_A0) 22378 { /* SOC_FORMAT_INT_ING_FLEX_CTR_BUS_BCM56980_A0fmt */ 22379 /* format ING_FLEX_CTR_BUSfmt */ 22380 /* nFields */ 20, 22381 /* *fields */ soc_ING_FLEX_CTR_BUS_BCM56980_A0fmt_fields, 22382 /* bits */ 300, 22383 /* flags */ 0, 22384 }, 22385 #endif /* chips */ 22386 22387 #if defined(BCM_56980_B0) 22388 { /* SOC_FORMAT_INT_ING_FLEX_CTR_BUS_BCM56980_B0fmt */ 22389 /* format ING_FLEX_CTR_BUSfmt */ 22390 /* nFields */ 20, 22391 /* *fields */ soc_ING_FLEX_CTR_BUS_BCM56980_A0fmt_fields, 22392 /* bits */ 300, 22393 /* flags */ 0, 22394 }, 22395 #endif /* chips */ 22396 22397 #if defined(BCM_56440_A0) 22398 { /* SOC_FORMAT_INT_ING_FLEX_CTR_BUS_POOLfmt */ 22399 /* format ING_FLEX_CTR_BUS_POOLfmt */ 22400 /* nFields */ 3, 22401 /* *fields */ soc_EGR_FLEX_CTR_BUS_POOLfmt_fields, 22402 /* bits */ 16, 22403 /* flags */ 0, 22404 }, 22405 #endif /* chips */ 22406 22407 #if defined(BCM_56260_A0) 22408 { /* SOC_FORMAT_INT_ING_FLEX_CTR_BUS_POOL_BCM56260_A0fmt */ 22409 /* format ING_FLEX_CTR_BUS_POOLfmt */ 22410 /* nFields */ 3, 22411 /* *fields */ soc_EGR_FLEX_CTR_BUS_POOL_BCM56960_A0fmt_fields, 22412 /* bits */ 16, 22413 /* flags */ 0, 22414 }, 22415 #endif /* chips */ 22416 22417 #if defined(BCM_56260_B0) 22418 { /* SOC_FORMAT_INT_ING_FLEX_CTR_BUS_POOL_BCM56260_B0fmt */ 22419 /* format ING_FLEX_CTR_BUS_POOLfmt */ 22420 /* nFields */ 3, 22421 /* *fields */ soc_EGR_FLEX_CTR_BUS_POOL_BCM56960_A0fmt_fields, 22422 /* bits */ 16, 22423 /* flags */ 0, 22424 }, 22425 #endif /* chips */ 22426 22427 #if defined(BCM_56270_A0) 22428 { /* SOC_FORMAT_INT_ING_FLEX_CTR_BUS_POOL_BCM56270_A0fmt */ 22429 /* format ING_FLEX_CTR_BUS_POOLfmt */ 22430 /* nFields */ 4, 22431 /* *fields */ soc_EGR_FLEX_CTR_BUS_POOL_BCM56270_A0fmt_fields, 22432 /* bits */ 16, 22433 /* flags */ 0, 22434 }, 22435 #endif /* chips */ 22436 22437 #if defined(BCM_56340_A0) 22438 { /* SOC_FORMAT_INT_ING_FLEX_CTR_BUS_POOL_BCM56340_A0fmt */ 22439 /* format ING_FLEX_CTR_BUS_POOLfmt */ 22440 /* nFields */ 3, 22441 /* *fields */ soc_EGR_FLEX_CTR_BUS_POOL_BCM56340_A0fmt_fields, 22442 /* bits */ 13, 22443 /* flags */ 0, 22444 }, 22445 #endif /* chips */ 22446 22447 #if defined(BCM_56370_A0) 22448 { /* SOC_FORMAT_INT_ING_FLEX_CTR_BUS_POOL_BCM56370_A0fmt */ 22449 /* format ING_FLEX_CTR_BUS_POOLfmt */ 22450 /* nFields */ 3, 22451 /* *fields */ soc_EGR_FLEX_CTR_BUS_POOL_BCM56960_A0fmt_fields, 22452 /* bits */ 16, 22453 /* flags */ 0, 22454 }, 22455 #endif /* chips */ 22456 22457 #if defined(BCM_56440_B0) 22458 { /* SOC_FORMAT_INT_ING_FLEX_CTR_BUS_POOL_BCM56440_B0fmt */ 22459 /* format ING_FLEX_CTR_BUS_POOLfmt */ 22460 /* nFields */ 3, 22461 /* *fields */ soc_EGR_FLEX_CTR_BUS_POOLfmt_fields, 22462 /* bits */ 16, 22463 /* flags */ 0, 22464 }, 22465 #endif /* chips */ 22466 22467 #if defined(BCM_56450_A0) 22468 { /* SOC_FORMAT_INT_ING_FLEX_CTR_BUS_POOL_BCM56450_A0fmt */ 22469 /* format ING_FLEX_CTR_BUS_POOLfmt */ 22470 /* nFields */ 3, 22471 /* *fields */ soc_EGR_FLEX_CTR_BUS_POOL_BCM56640_A0fmt_fields, 22472 /* bits */ 16, 22473 /* flags */ 0, 22474 }, 22475 #endif /* chips */ 22476 22477 #if defined(BCM_56450_B0) 22478 { /* SOC_FORMAT_INT_ING_FLEX_CTR_BUS_POOL_BCM56450_B0fmt */ 22479 /* format ING_FLEX_CTR_BUS_POOLfmt */ 22480 /* nFields */ 3, 22481 /* *fields */ soc_EGR_FLEX_CTR_BUS_POOL_BCM56640_A0fmt_fields, 22482 /* bits */ 16, 22483 /* flags */ 0, 22484 }, 22485 #endif /* chips */ 22486 22487 #if defined(BCM_56450_B1) 22488 { /* SOC_FORMAT_INT_ING_FLEX_CTR_BUS_POOL_BCM56450_B1fmt */ 22489 /* format ING_FLEX_CTR_BUS_POOLfmt */ 22490 /* nFields */ 3, 22491 /* *fields */ soc_EGR_FLEX_CTR_BUS_POOL_BCM56640_A0fmt_fields, 22492 /* bits */ 16, 22493 /* flags */ 0, 22494 }, 22495 #endif /* chips */ 22496 22497 #if defined(BCM_56560_A0) 22498 { /* SOC_FORMAT_INT_ING_FLEX_CTR_BUS_POOL_BCM56560_A0fmt */ 22499 /* format ING_FLEX_CTR_BUS_POOLfmt */ 22500 /* nFields */ 3, 22501 /* *fields */ soc_EGR_FLEX_CTR_BUS_POOL_BCM56960_A0fmt_fields, 22502 /* bits */ 16, 22503 /* flags */ 0, 22504 }, 22505 #endif /* chips */ 22506 22507 #if defined(BCM_56560_B0) 22508 { /* SOC_FORMAT_INT_ING_FLEX_CTR_BUS_POOL_BCM56560_B0fmt */ 22509 /* format ING_FLEX_CTR_BUS_POOLfmt */ 22510 /* nFields */ 3, 22511 /* *fields */ soc_EGR_FLEX_CTR_BUS_POOL_BCM56960_A0fmt_fields, 22512 /* bits */ 16, 22513 /* flags */ 0, 22514 }, 22515 #endif /* chips */ 22516 22517 #if defined(BCM_56640_A0) 22518 { /* SOC_FORMAT_INT_ING_FLEX_CTR_BUS_POOL_BCM56640_A0fmt */ 22519 /* format ING_FLEX_CTR_BUS_POOLfmt */ 22520 /* nFields */ 3, 22521 /* *fields */ soc_EGR_FLEX_CTR_BUS_POOL_BCM56640_A0fmt_fields, 22522 /* bits */ 16, 22523 /* flags */ 0, 22524 }, 22525 #endif /* chips */ 22526 22527 #if defined(BCM_56670_A0) 22528 { /* SOC_FORMAT_INT_ING_FLEX_CTR_BUS_POOL_BCM56670_A0fmt */ 22529 /* format ING_FLEX_CTR_BUS_POOLfmt */ 22530 /* nFields */ 3, 22531 /* *fields */ soc_EGR_FLEX_CTR_BUS_POOL_BCM56960_A0fmt_fields, 22532 /* bits */ 16, 22533 /* flags */ 0, 22534 }, 22535 #endif /* chips */ 22536 22537 #if defined(BCM_56670_B0) 22538 { /* SOC_FORMAT_INT_ING_FLEX_CTR_BUS_POOL_BCM56670_B0fmt */ 22539 /* format ING_FLEX_CTR_BUS_POOLfmt */ 22540 /* nFields */ 3, 22541 /* *fields */ soc_EGR_FLEX_CTR_BUS_POOL_BCM56960_A0fmt_fields, 22542 /* bits */ 16, 22543 /* flags */ 0, 22544 }, 22545 #endif /* chips */ 22546 22547 #if defined(BCM_56770_A0) 22548 { /* SOC_FORMAT_INT_ING_FLEX_CTR_BUS_POOL_BCM56770_A0fmt */ 22549 /* format ING_FLEX_CTR_BUS_POOLfmt */ 22550 /* nFields */ 3, 22551 /* *fields */ soc_EGR_FLEX_CTR_BUS_POOL_BCM56960_A0fmt_fields, 22552 /* bits */ 16, 22553 /* flags */ 0, 22554 }, 22555 #endif /* chips */ 22556 22557 #if defined(BCM_56850_A0) 22558 { /* SOC_FORMAT_INT_ING_FLEX_CTR_BUS_POOL_BCM56850_A0fmt */ 22559 /* format ING_FLEX_CTR_BUS_POOLfmt */ 22560 /* nFields */ 3, 22561 /* *fields */ soc_EGR_FLEX_CTR_BUS_POOL_BCM56640_A0fmt_fields, 22562 /* bits */ 16, 22563 /* flags */ 0, 22564 }, 22565 #endif /* chips */ 22566 22567 #if defined(BCM_56860_A0) 22568 { /* SOC_FORMAT_INT_ING_FLEX_CTR_BUS_POOL_BCM56860_A0fmt */ 22569 /* format ING_FLEX_CTR_BUS_POOLfmt */ 22570 /* nFields */ 3, 22571 /* *fields */ soc_EGR_FLEX_CTR_BUS_POOL_BCM56640_A0fmt_fields, 22572 /* bits */ 16, 22573 /* flags */ 0, 22574 }, 22575 #endif /* chips */ 22576 22577 #if defined(BCM_56870_A0) 22578 { /* SOC_FORMAT_INT_ING_FLEX_CTR_BUS_POOL_BCM56870_A0fmt */ 22579 /* format ING_FLEX_CTR_BUS_POOLfmt */ 22580 /* nFields */ 3, 22581 /* *fields */ soc_EGR_FLEX_CTR_BUS_POOL_BCM56960_A0fmt_fields, 22582 /* bits */ 16, 22583 /* flags */ 0, 22584 }, 22585 #endif /* chips */ 22586 22587 #if defined(BCM_56960_A0) 22588 { /* SOC_FORMAT_INT_ING_FLEX_CTR_BUS_POOL_BCM56960_A0fmt */ 22589 /* format ING_FLEX_CTR_BUS_POOLfmt */ 22590 /* nFields */ 3, 22591 /* *fields */ soc_EGR_FLEX_CTR_BUS_POOL_BCM56960_A0fmt_fields, 22592 /* bits */ 16, 22593 /* flags */ 0, 22594 }, 22595 #endif /* chips */ 22596 22597 #if defined(BCM_56965_A0) 22598 { /* SOC_FORMAT_INT_ING_FLEX_CTR_BUS_POOL_BCM56965_A0fmt */ 22599 /* format ING_FLEX_CTR_BUS_POOLfmt */ 22600 /* nFields */ 3, 22601 /* *fields */ soc_EGR_FLEX_CTR_BUS_POOL_BCM56960_A0fmt_fields, 22602 /* bits */ 16, 22603 /* flags */ 0, 22604 }, 22605 #endif /* chips */ 22606 22607 #if defined(BCM_56970_A0) 22608 { /* SOC_FORMAT_INT_ING_FLEX_CTR_BUS_POOL_BCM56970_A0fmt */ 22609 /* format ING_FLEX_CTR_BUS_POOLfmt */ 22610 /* nFields */ 3, 22611 /* *fields */ soc_EGR_FLEX_CTR_BUS_POOL_BCM56960_A0fmt_fields, 22612 /* bits */ 16, 22613 /* flags */ 0, 22614 }, 22615 #endif /* chips */ 22616 22617 #if defined(BCM_56980_A0) 22618 { /* SOC_FORMAT_INT_ING_FLEX_CTR_BUS_POOL_BCM56980_A0fmt */ 22619 /* format ING_FLEX_CTR_BUS_POOLfmt */ 22620 /* nFields */ 3, 22621 /* *fields */ soc_EGR_FLEX_CTR_BUS_POOL_BCM56980_A0fmt_fields, 22622 /* bits */ 15, 22623 /* flags */ 0, 22624 }, 22625 #endif /* chips */ 22626 22627 #if defined(BCM_56980_B0) 22628 { /* SOC_FORMAT_INT_ING_FLEX_CTR_BUS_POOL_BCM56980_B0fmt */ 22629 /* format ING_FLEX_CTR_BUS_POOLfmt */ 22630 /* nFields */ 3, 22631 /* *fields */ soc_EGR_FLEX_CTR_BUS_POOL_BCM56980_A0fmt_fields, 22632 /* bits */ 15, 22633 /* flags */ 0, 22634 }, 22635 #endif /* chips */ 22636 22637 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) 22638 { /* SOC_FORMAT_INT_ING_FLEX_CTR_COMPRESSED_PKT_ATTRfmt */ 22639 /* format ING_FLEX_CTR_COMPRESSED_PKT_ATTRfmt */ 22640 /* nFields */ 6, 22641 /* *fields */ soc_ING_FLEX_CTR_COMPRESSED_PKT_ATTRfmt_fields, 22642 /* bits */ 39, 22643 /* flags */ 0, 22644 }, 22645 #endif /* chips */ 22646 22647 #if defined(BCM_56260_A0) 22648 { /* SOC_FORMAT_INT_ING_FLEX_CTR_COMPRESSED_PKT_ATTR_BCM56260_A0fmt */ 22649 /* format ING_FLEX_CTR_COMPRESSED_PKT_ATTRfmt */ 22650 /* nFields */ 6, 22651 /* *fields */ soc_ING_FLEX_CTR_COMPRESSED_PKT_ATTR_BCM56260_A0fmt_fields, 22652 /* bits */ 40, 22653 /* flags */ 0, 22654 }, 22655 #endif /* chips */ 22656 22657 #if defined(BCM_56260_B0) 22658 { /* SOC_FORMAT_INT_ING_FLEX_CTR_COMPRESSED_PKT_ATTR_BCM56260_B0fmt */ 22659 /* format ING_FLEX_CTR_COMPRESSED_PKT_ATTRfmt */ 22660 /* nFields */ 6, 22661 /* *fields */ soc_ING_FLEX_CTR_COMPRESSED_PKT_ATTR_BCM56260_A0fmt_fields, 22662 /* bits */ 40, 22663 /* flags */ 0, 22664 }, 22665 #endif /* chips */ 22666 22667 #if defined(BCM_56270_A0) 22668 { /* SOC_FORMAT_INT_ING_FLEX_CTR_COMPRESSED_PKT_ATTR_BCM56270_A0fmt */ 22669 /* format ING_FLEX_CTR_COMPRESSED_PKT_ATTRfmt */ 22670 /* nFields */ 6, 22671 /* *fields */ soc_ING_FLEX_CTR_COMPRESSED_PKT_ATTR_BCM56260_A0fmt_fields, 22672 /* bits */ 40, 22673 /* flags */ 0, 22674 }, 22675 #endif /* chips */ 22676 22677 #if defined(BCM_56340_A0) 22678 { /* SOC_FORMAT_INT_ING_FLEX_CTR_COMPRESSED_PKT_ATTR_BCM56340_A0fmt */ 22679 /* format ING_FLEX_CTR_COMPRESSED_PKT_ATTRfmt */ 22680 /* nFields */ 6, 22681 /* *fields */ soc_ING_FLEX_CTR_COMPRESSED_PKT_ATTR_BCM56640_A0fmt_fields, 22682 /* bits */ 39, 22683 /* flags */ 0, 22684 }, 22685 #endif /* chips */ 22686 22687 #if defined(BCM_56370_A0) 22688 { /* SOC_FORMAT_INT_ING_FLEX_CTR_COMPRESSED_PKT_ATTR_BCM56370_A0fmt */ 22689 /* format ING_FLEX_CTR_COMPRESSED_PKT_ATTRfmt */ 22690 /* nFields */ 6, 22691 /* *fields */ soc_ING_FLEX_CTR_COMPRESSED_PKT_ATTR_BCM56960_A0fmt_fields, 22692 /* bits */ 41, 22693 /* flags */ 0, 22694 }, 22695 #endif /* chips */ 22696 22697 #if defined(BCM_56450_A0) 22698 { /* SOC_FORMAT_INT_ING_FLEX_CTR_COMPRESSED_PKT_ATTR_BCM56450_A0fmt */ 22699 /* format ING_FLEX_CTR_COMPRESSED_PKT_ATTRfmt */ 22700 /* nFields */ 6, 22701 /* *fields */ soc_ING_FLEX_CTR_COMPRESSED_PKT_ATTR_BCM56450_A0fmt_fields, 22702 /* bits */ 41, 22703 /* flags */ 0, 22704 }, 22705 #endif /* chips */ 22706 22707 #if defined(BCM_56450_B0) 22708 { /* SOC_FORMAT_INT_ING_FLEX_CTR_COMPRESSED_PKT_ATTR_BCM56450_B0fmt */ 22709 /* format ING_FLEX_CTR_COMPRESSED_PKT_ATTRfmt */ 22710 /* nFields */ 6, 22711 /* *fields */ soc_ING_FLEX_CTR_COMPRESSED_PKT_ATTR_BCM56450_A0fmt_fields, 22712 /* bits */ 41, 22713 /* flags */ 0, 22714 }, 22715 #endif /* chips */ 22716 22717 #if defined(BCM_56450_B1) 22718 { /* SOC_FORMAT_INT_ING_FLEX_CTR_COMPRESSED_PKT_ATTR_BCM56450_B1fmt */ 22719 /* format ING_FLEX_CTR_COMPRESSED_PKT_ATTRfmt */ 22720 /* nFields */ 6, 22721 /* *fields */ soc_ING_FLEX_CTR_COMPRESSED_PKT_ATTR_BCM56450_A0fmt_fields, 22722 /* bits */ 41, 22723 /* flags */ 0, 22724 }, 22725 #endif /* chips */ 22726 22727 #if defined(BCM_56560_A0) 22728 { /* SOC_FORMAT_INT_ING_FLEX_CTR_COMPRESSED_PKT_ATTR_BCM56560_A0fmt */ 22729 /* format ING_FLEX_CTR_COMPRESSED_PKT_ATTRfmt */ 22730 /* nFields */ 14, 22731 /* *fields */ soc_ING_FLEX_CTR_COMPRESSED_PKT_ATTR_BCM56560_A0fmt_fields, 22732 /* bits */ 64, 22733 /* flags */ 0, 22734 }, 22735 #endif /* chips */ 22736 22737 #if defined(BCM_56560_B0) 22738 { /* SOC_FORMAT_INT_ING_FLEX_CTR_COMPRESSED_PKT_ATTR_BCM56560_B0fmt */ 22739 /* format ING_FLEX_CTR_COMPRESSED_PKT_ATTRfmt */ 22740 /* nFields */ 14, 22741 /* *fields */ soc_ING_FLEX_CTR_COMPRESSED_PKT_ATTR_BCM56560_A0fmt_fields, 22742 /* bits */ 64, 22743 /* flags */ 0, 22744 }, 22745 #endif /* chips */ 22746 22747 #if defined(BCM_56640_A0) 22748 { /* SOC_FORMAT_INT_ING_FLEX_CTR_COMPRESSED_PKT_ATTR_BCM56640_A0fmt */ 22749 /* format ING_FLEX_CTR_COMPRESSED_PKT_ATTRfmt */ 22750 /* nFields */ 6, 22751 /* *fields */ soc_ING_FLEX_CTR_COMPRESSED_PKT_ATTR_BCM56640_A0fmt_fields, 22752 /* bits */ 39, 22753 /* flags */ 0, 22754 }, 22755 #endif /* chips */ 22756 22757 #if defined(BCM_56670_A0) 22758 { /* SOC_FORMAT_INT_ING_FLEX_CTR_COMPRESSED_PKT_ATTR_BCM56670_A0fmt */ 22759 /* format ING_FLEX_CTR_COMPRESSED_PKT_ATTRfmt */ 22760 /* nFields */ 14, 22761 /* *fields */ soc_ING_FLEX_CTR_COMPRESSED_PKT_ATTR_BCM56560_A0fmt_fields, 22762 /* bits */ 64, 22763 /* flags */ 0, 22764 }, 22765 #endif /* chips */ 22766 22767 #if defined(BCM_56670_B0) 22768 { /* SOC_FORMAT_INT_ING_FLEX_CTR_COMPRESSED_PKT_ATTR_BCM56670_B0fmt */ 22769 /* format ING_FLEX_CTR_COMPRESSED_PKT_ATTRfmt */ 22770 /* nFields */ 14, 22771 /* *fields */ soc_ING_FLEX_CTR_COMPRESSED_PKT_ATTR_BCM56560_A0fmt_fields, 22772 /* bits */ 64, 22773 /* flags */ 0, 22774 }, 22775 #endif /* chips */ 22776 22777 #if defined(BCM_56770_A0) 22778 { /* SOC_FORMAT_INT_ING_FLEX_CTR_COMPRESSED_PKT_ATTR_BCM56770_A0fmt */ 22779 /* format ING_FLEX_CTR_COMPRESSED_PKT_ATTRfmt */ 22780 /* nFields */ 6, 22781 /* *fields */ soc_ING_FLEX_CTR_COMPRESSED_PKT_ATTR_BCM56960_A0fmt_fields, 22782 /* bits */ 41, 22783 /* flags */ 0, 22784 }, 22785 #endif /* chips */ 22786 22787 #if defined(BCM_56850_A0) 22788 { /* SOC_FORMAT_INT_ING_FLEX_CTR_COMPRESSED_PKT_ATTR_BCM56850_A0fmt */ 22789 /* format ING_FLEX_CTR_COMPRESSED_PKT_ATTRfmt */ 22790 /* nFields */ 6, 22791 /* *fields */ soc_ING_FLEX_CTR_COMPRESSED_PKT_ATTR_BCM56850_A0fmt_fields, 22792 /* bits */ 40, 22793 /* flags */ 0, 22794 }, 22795 #endif /* chips */ 22796 22797 #if defined(BCM_56860_A0) 22798 { /* SOC_FORMAT_INT_ING_FLEX_CTR_COMPRESSED_PKT_ATTR_BCM56860_A0fmt */ 22799 /* format ING_FLEX_CTR_COMPRESSED_PKT_ATTRfmt */ 22800 /* nFields */ 6, 22801 /* *fields */ soc_ING_FLEX_CTR_COMPRESSED_PKT_ATTR_BCM56850_A0fmt_fields, 22802 /* bits */ 40, 22803 /* flags */ 0, 22804 }, 22805 #endif /* chips */ 22806 22807 #if defined(BCM_56870_A0) 22808 { /* SOC_FORMAT_INT_ING_FLEX_CTR_COMPRESSED_PKT_ATTR_BCM56870_A0fmt */ 22809 /* format ING_FLEX_CTR_COMPRESSED_PKT_ATTRfmt */ 22810 /* nFields */ 6, 22811 /* *fields */ soc_ING_FLEX_CTR_COMPRESSED_PKT_ATTR_BCM56960_A0fmt_fields, 22812 /* bits */ 41, 22813 /* flags */ 0, 22814 }, 22815 #endif /* chips */ 22816 22817 #if defined(BCM_56960_A0) 22818 { /* SOC_FORMAT_INT_ING_FLEX_CTR_COMPRESSED_PKT_ATTR_BCM56960_A0fmt */ 22819 /* format ING_FLEX_CTR_COMPRESSED_PKT_ATTRfmt */ 22820 /* nFields */ 6, 22821 /* *fields */ soc_ING_FLEX_CTR_COMPRESSED_PKT_ATTR_BCM56960_A0fmt_fields, 22822 /* bits */ 41, 22823 /* flags */ 0, 22824 }, 22825 #endif /* chips */ 22826 22827 #if defined(BCM_56965_A0) 22828 { /* SOC_FORMAT_INT_ING_FLEX_CTR_COMPRESSED_PKT_ATTR_BCM56965_A0fmt */ 22829 /* format ING_FLEX_CTR_COMPRESSED_PKT_ATTRfmt */ 22830 /* nFields */ 6, 22831 /* *fields */ soc_ING_FLEX_CTR_COMPRESSED_PKT_ATTR_BCM56960_A0fmt_fields, 22832 /* bits */ 41, 22833 /* flags */ 0, 22834 }, 22835 #endif /* chips */ 22836 22837 #if defined(BCM_56970_A0) 22838 { /* SOC_FORMAT_INT_ING_FLEX_CTR_COMPRESSED_PKT_ATTR_BCM56970_A0fmt */ 22839 /* format ING_FLEX_CTR_COMPRESSED_PKT_ATTRfmt */ 22840 /* nFields */ 6, 22841 /* *fields */ soc_ING_FLEX_CTR_COMPRESSED_PKT_ATTR_BCM56960_A0fmt_fields, 22842 /* bits */ 41, 22843 /* flags */ 0, 22844 }, 22845 #endif /* chips */ 22846 22847 #if defined(BCM_56440_A0) 22848 { /* SOC_FORMAT_INT_ING_FLEX_CTR_PKT_ATTRfmt */ 22849 /* format ING_FLEX_CTR_PKT_ATTRfmt */ 22850 /* nFields */ 12, 22851 /* *fields */ soc_ING_FLEX_CTR_PKT_ATTRfmt_fields, 22852 /* bits */ 39, 22853 /* flags */ 0, 22854 }, 22855 #endif /* chips */ 22856 22857 #if defined(BCM_56260_A0) 22858 { /* SOC_FORMAT_INT_ING_FLEX_CTR_PKT_ATTR_BCM56260_A0fmt */ 22859 /* format ING_FLEX_CTR_PKT_ATTRfmt */ 22860 /* nFields */ 13, 22861 /* *fields */ soc_ING_FLEX_CTR_PKT_ATTR_BCM56260_A0fmt_fields, 22862 /* bits */ 43, 22863 /* flags */ 0, 22864 }, 22865 #endif /* chips */ 22866 22867 #if defined(BCM_56260_B0) 22868 { /* SOC_FORMAT_INT_ING_FLEX_CTR_PKT_ATTR_BCM56260_B0fmt */ 22869 /* format ING_FLEX_CTR_PKT_ATTRfmt */ 22870 /* nFields */ 13, 22871 /* *fields */ soc_ING_FLEX_CTR_PKT_ATTR_BCM56260_A0fmt_fields, 22872 /* bits */ 43, 22873 /* flags */ 0, 22874 }, 22875 #endif /* chips */ 22876 22877 #if defined(BCM_56270_A0) 22878 { /* SOC_FORMAT_INT_ING_FLEX_CTR_PKT_ATTR_BCM56270_A0fmt */ 22879 /* format ING_FLEX_CTR_PKT_ATTRfmt */ 22880 /* nFields */ 13, 22881 /* *fields */ soc_ING_FLEX_CTR_PKT_ATTR_BCM56260_A0fmt_fields, 22882 /* bits */ 43, 22883 /* flags */ 0, 22884 }, 22885 #endif /* chips */ 22886 22887 #if defined(BCM_56340_A0) 22888 { /* SOC_FORMAT_INT_ING_FLEX_CTR_PKT_ATTR_BCM56340_A0fmt */ 22889 /* format ING_FLEX_CTR_PKT_ATTRfmt */ 22890 /* nFields */ 12, 22891 /* *fields */ soc_ING_FLEX_CTR_PKT_ATTR_BCM56640_A0fmt_fields, 22892 /* bits */ 39, 22893 /* flags */ 0, 22894 }, 22895 #endif /* chips */ 22896 22897 #if defined(BCM_56370_A0) 22898 { /* SOC_FORMAT_INT_ING_FLEX_CTR_PKT_ATTR_BCM56370_A0fmt */ 22899 /* format ING_FLEX_CTR_PKT_ATTRfmt */ 22900 /* nFields */ 15, 22901 /* *fields */ soc_ING_FLEX_CTR_PKT_ATTR_BCM56370_A0fmt_fields, 22902 /* bits */ 53, 22903 /* flags */ 0, 22904 }, 22905 #endif /* chips */ 22906 22907 #if defined(BCM_56440_B0) 22908 { /* SOC_FORMAT_INT_ING_FLEX_CTR_PKT_ATTR_BCM56440_B0fmt */ 22909 /* format ING_FLEX_CTR_PKT_ATTRfmt */ 22910 /* nFields */ 12, 22911 /* *fields */ soc_ING_FLEX_CTR_PKT_ATTRfmt_fields, 22912 /* bits */ 39, 22913 /* flags */ 0, 22914 }, 22915 #endif /* chips */ 22916 22917 #if defined(BCM_56450_A0) 22918 { /* SOC_FORMAT_INT_ING_FLEX_CTR_PKT_ATTR_BCM56450_A0fmt */ 22919 /* format ING_FLEX_CTR_PKT_ATTRfmt */ 22920 /* nFields */ 12, 22921 /* *fields */ soc_ING_FLEX_CTR_PKT_ATTR_BCM56450_A0fmt_fields, 22922 /* bits */ 43, 22923 /* flags */ 0, 22924 }, 22925 #endif /* chips */ 22926 22927 #if defined(BCM_56450_B0) 22928 { /* SOC_FORMAT_INT_ING_FLEX_CTR_PKT_ATTR_BCM56450_B0fmt */ 22929 /* format ING_FLEX_CTR_PKT_ATTRfmt */ 22930 /* nFields */ 12, 22931 /* *fields */ soc_ING_FLEX_CTR_PKT_ATTR_BCM56450_A0fmt_fields, 22932 /* bits */ 43, 22933 /* flags */ 0, 22934 }, 22935 #endif /* chips */ 22936 22937 #if defined(BCM_56450_B1) 22938 { /* SOC_FORMAT_INT_ING_FLEX_CTR_PKT_ATTR_BCM56450_B1fmt */ 22939 /* format ING_FLEX_CTR_PKT_ATTRfmt */ 22940 /* nFields */ 12, 22941 /* *fields */ soc_ING_FLEX_CTR_PKT_ATTR_BCM56450_A0fmt_fields, 22942 /* bits */ 43, 22943 /* flags */ 0, 22944 }, 22945 #endif /* chips */ 22946 22947 #if defined(BCM_56560_A0) 22948 { /* SOC_FORMAT_INT_ING_FLEX_CTR_PKT_ATTR_BCM56560_A0fmt */ 22949 /* format ING_FLEX_CTR_PKT_ATTRfmt */ 22950 /* nFields */ 19, 22951 /* *fields */ soc_ING_FLEX_CTR_PKT_ATTR_BCM56560_A0fmt_fields, 22952 /* bits */ 64, 22953 /* flags */ 0, 22954 }, 22955 #endif /* chips */ 22956 22957 #if defined(BCM_56560_B0) 22958 { /* SOC_FORMAT_INT_ING_FLEX_CTR_PKT_ATTR_BCM56560_B0fmt */ 22959 /* format ING_FLEX_CTR_PKT_ATTRfmt */ 22960 /* nFields */ 19, 22961 /* *fields */ soc_ING_FLEX_CTR_PKT_ATTR_BCM56560_A0fmt_fields, 22962 /* bits */ 64, 22963 /* flags */ 0, 22964 }, 22965 #endif /* chips */ 22966 22967 #if defined(BCM_56640_A0) 22968 { /* SOC_FORMAT_INT_ING_FLEX_CTR_PKT_ATTR_BCM56640_A0fmt */ 22969 /* format ING_FLEX_CTR_PKT_ATTRfmt */ 22970 /* nFields */ 12, 22971 /* *fields */ soc_ING_FLEX_CTR_PKT_ATTR_BCM56640_A0fmt_fields, 22972 /* bits */ 39, 22973 /* flags */ 0, 22974 }, 22975 #endif /* chips */ 22976 22977 #if defined(BCM_56670_A0) 22978 { /* SOC_FORMAT_INT_ING_FLEX_CTR_PKT_ATTR_BCM56670_A0fmt */ 22979 /* format ING_FLEX_CTR_PKT_ATTRfmt */ 22980 /* nFields */ 19, 22981 /* *fields */ soc_ING_FLEX_CTR_PKT_ATTR_BCM56560_A0fmt_fields, 22982 /* bits */ 64, 22983 /* flags */ 0, 22984 }, 22985 #endif /* chips */ 22986 22987 #if defined(BCM_56670_B0) 22988 { /* SOC_FORMAT_INT_ING_FLEX_CTR_PKT_ATTR_BCM56670_B0fmt */ 22989 /* format ING_FLEX_CTR_PKT_ATTRfmt */ 22990 /* nFields */ 19, 22991 /* *fields */ soc_ING_FLEX_CTR_PKT_ATTR_BCM56560_A0fmt_fields, 22992 /* bits */ 64, 22993 /* flags */ 0, 22994 }, 22995 #endif /* chips */ 22996 22997 #if defined(BCM_56770_A0) 22998 { /* SOC_FORMAT_INT_ING_FLEX_CTR_PKT_ATTR_BCM56770_A0fmt */ 22999 /* format ING_FLEX_CTR_PKT_ATTRfmt */ 23000 /* nFields */ 13, 23001 /* *fields */ soc_ING_FLEX_CTR_PKT_ATTR_BCM56770_A0fmt_fields, 23002 /* bits */ 51, 23003 /* flags */ 0, 23004 }, 23005 #endif /* chips */ 23006 23007 #if defined(BCM_56850_A0) 23008 { /* SOC_FORMAT_INT_ING_FLEX_CTR_PKT_ATTR_BCM56850_A0fmt */ 23009 /* format ING_FLEX_CTR_PKT_ATTRfmt */ 23010 /* nFields */ 12, 23011 /* *fields */ soc_ING_FLEX_CTR_PKT_ATTR_BCM56850_A0fmt_fields, 23012 /* bits */ 40, 23013 /* flags */ 0, 23014 }, 23015 #endif /* chips */ 23016 23017 #if defined(BCM_56860_A0) 23018 { /* SOC_FORMAT_INT_ING_FLEX_CTR_PKT_ATTR_BCM56860_A0fmt */ 23019 /* format ING_FLEX_CTR_PKT_ATTRfmt */ 23020 /* nFields */ 12, 23021 /* *fields */ soc_ING_FLEX_CTR_PKT_ATTR_BCM56850_A0fmt_fields, 23022 /* bits */ 40, 23023 /* flags */ 0, 23024 }, 23025 #endif /* chips */ 23026 23027 #if defined(BCM_56870_A0) 23028 { /* SOC_FORMAT_INT_ING_FLEX_CTR_PKT_ATTR_BCM56870_A0fmt */ 23029 /* format ING_FLEX_CTR_PKT_ATTRfmt */ 23030 /* nFields */ 12, 23031 /* *fields */ soc_ING_FLEX_CTR_PKT_ATTR_BCM56870_A0fmt_fields, 23032 /* bits */ 43, 23033 /* flags */ 0, 23034 }, 23035 #endif /* chips */ 23036 23037 #if defined(BCM_56960_A0) 23038 { /* SOC_FORMAT_INT_ING_FLEX_CTR_PKT_ATTR_BCM56960_A0fmt */ 23039 /* format ING_FLEX_CTR_PKT_ATTRfmt */ 23040 /* nFields */ 12, 23041 /* *fields */ soc_ING_FLEX_CTR_PKT_ATTR_BCM56960_A0fmt_fields, 23042 /* bits */ 41, 23043 /* flags */ 0, 23044 }, 23045 #endif /* chips */ 23046 23047 #if defined(BCM_56965_A0) 23048 { /* SOC_FORMAT_INT_ING_FLEX_CTR_PKT_ATTR_BCM56965_A0fmt */ 23049 /* format ING_FLEX_CTR_PKT_ATTRfmt */ 23050 /* nFields */ 12, 23051 /* *fields */ soc_ING_FLEX_CTR_PKT_ATTR_BCM56960_A0fmt_fields, 23052 /* bits */ 41, 23053 /* flags */ 0, 23054 }, 23055 #endif /* chips */ 23056 23057 #if defined(BCM_56970_A0) 23058 { /* SOC_FORMAT_INT_ING_FLEX_CTR_PKT_ATTR_BCM56970_A0fmt */ 23059 /* format ING_FLEX_CTR_PKT_ATTRfmt */ 23060 /* nFields */ 12, 23061 /* *fields */ soc_ING_FLEX_CTR_PKT_ATTR_BCM56960_A0fmt_fields, 23062 /* bits */ 41, 23063 /* flags */ 0, 23064 }, 23065 #endif /* chips */ 23066 23067 #if defined(BCM_56980_A0) 23068 { /* SOC_FORMAT_INT_ING_FLEX_CTR_PKT_ATTR_BCM56980_A0fmt */ 23069 /* format ING_FLEX_CTR_PKT_ATTRfmt */ 23070 /* nFields */ 15, 23071 /* *fields */ soc_ING_FLEX_CTR_PKT_ATTR_BCM56980_A0fmt_fields, 23072 /* bits */ 50, 23073 /* flags */ 0, 23074 }, 23075 #endif /* chips */ 23076 23077 #if defined(BCM_56980_B0) 23078 { /* SOC_FORMAT_INT_ING_FLEX_CTR_PKT_ATTR_BCM56980_B0fmt */ 23079 /* format ING_FLEX_CTR_PKT_ATTRfmt */ 23080 /* nFields */ 15, 23081 /* *fields */ soc_ING_FLEX_CTR_PKT_ATTR_BCM56980_A0fmt_fields, 23082 /* bits */ 50, 23083 /* flags */ 0, 23084 }, 23085 #endif /* chips */ 23086 23087 #if defined(BCM_56440_A0) 23088 { /* SOC_FORMAT_INT_ING_FLEX_CTR_UDFfmt */ 23089 /* format ING_FLEX_CTR_UDFfmt */ 23090 /* nFields */ 3, 23091 /* *fields */ soc_ING_FLEX_CTR_UDFfmt_fields, 23092 /* bits */ 33, 23093 /* flags */ 0, 23094 }, 23095 #endif /* chips */ 23096 23097 #if defined(BCM_56260_A0) 23098 { /* SOC_FORMAT_INT_ING_FLEX_CTR_UDF_BCM56260_A0fmt */ 23099 /* format ING_FLEX_CTR_UDFfmt */ 23100 /* nFields */ 3, 23101 /* *fields */ soc_EGR_FLEX_CTR_UDF_BCM56960_A0fmt_fields, 23102 /* bits */ 33, 23103 /* flags */ 0, 23104 }, 23105 #endif /* chips */ 23106 23107 #if defined(BCM_56260_B0) 23108 { /* SOC_FORMAT_INT_ING_FLEX_CTR_UDF_BCM56260_B0fmt */ 23109 /* format ING_FLEX_CTR_UDFfmt */ 23110 /* nFields */ 3, 23111 /* *fields */ soc_EGR_FLEX_CTR_UDF_BCM56960_A0fmt_fields, 23112 /* bits */ 33, 23113 /* flags */ 0, 23114 }, 23115 #endif /* chips */ 23116 23117 #if defined(BCM_56270_A0) 23118 { /* SOC_FORMAT_INT_ING_FLEX_CTR_UDF_BCM56270_A0fmt */ 23119 /* format ING_FLEX_CTR_UDFfmt */ 23120 /* nFields */ 3, 23121 /* *fields */ soc_EGR_FLEX_CTR_UDF_BCM56960_A0fmt_fields, 23122 /* bits */ 33, 23123 /* flags */ 0, 23124 }, 23125 #endif /* chips */ 23126 23127 #if defined(BCM_56340_A0) 23128 { /* SOC_FORMAT_INT_ING_FLEX_CTR_UDF_BCM56340_A0fmt */ 23129 /* format ING_FLEX_CTR_UDFfmt */ 23130 /* nFields */ 3, 23131 /* *fields */ soc_EGR_FLEX_CTR_UDFfmt_fields, 23132 /* bits */ 33, 23133 /* flags */ 0, 23134 }, 23135 #endif /* chips */ 23136 23137 #if defined(BCM_56370_A0) 23138 { /* SOC_FORMAT_INT_ING_FLEX_CTR_UDF_BCM56370_A0fmt */ 23139 /* format ING_FLEX_CTR_UDFfmt */ 23140 /* nFields */ 3, 23141 /* *fields */ soc_EGR_FLEX_CTR_UDF_BCM56960_A0fmt_fields, 23142 /* bits */ 33, 23143 /* flags */ 0, 23144 }, 23145 #endif /* chips */ 23146 23147 #if defined(BCM_56440_B0) 23148 { /* SOC_FORMAT_INT_ING_FLEX_CTR_UDF_BCM56440_B0fmt */ 23149 /* format ING_FLEX_CTR_UDFfmt */ 23150 /* nFields */ 3, 23151 /* *fields */ soc_ING_FLEX_CTR_UDFfmt_fields, 23152 /* bits */ 33, 23153 /* flags */ 0, 23154 }, 23155 #endif /* chips */ 23156 23157 #if defined(BCM_56450_A0) 23158 { /* SOC_FORMAT_INT_ING_FLEX_CTR_UDF_BCM56450_A0fmt */ 23159 /* format ING_FLEX_CTR_UDFfmt */ 23160 /* nFields */ 3, 23161 /* *fields */ soc_EGR_FLEX_CTR_UDFfmt_fields, 23162 /* bits */ 33, 23163 /* flags */ 0, 23164 }, 23165 #endif /* chips */ 23166 23167 #if defined(BCM_56450_B0) 23168 { /* SOC_FORMAT_INT_ING_FLEX_CTR_UDF_BCM56450_B0fmt */ 23169 /* format ING_FLEX_CTR_UDFfmt */ 23170 /* nFields */ 3, 23171 /* *fields */ soc_EGR_FLEX_CTR_UDFfmt_fields, 23172 /* bits */ 33, 23173 /* flags */ 0, 23174 }, 23175 #endif /* chips */ 23176 23177 #if defined(BCM_56450_B1) 23178 { /* SOC_FORMAT_INT_ING_FLEX_CTR_UDF_BCM56450_B1fmt */ 23179 /* format ING_FLEX_CTR_UDFfmt */ 23180 /* nFields */ 3, 23181 /* *fields */ soc_EGR_FLEX_CTR_UDFfmt_fields, 23182 /* bits */ 33, 23183 /* flags */ 0, 23184 }, 23185 #endif /* chips */ 23186 23187 #if defined(BCM_56640_A0) 23188 { /* SOC_FORMAT_INT_ING_FLEX_CTR_UDF_BCM56640_A0fmt */ 23189 /* format ING_FLEX_CTR_UDFfmt */ 23190 /* nFields */ 3, 23191 /* *fields */ soc_EGR_FLEX_CTR_UDFfmt_fields, 23192 /* bits */ 33, 23193 /* flags */ 0, 23194 }, 23195 #endif /* chips */ 23196 23197 #if defined(BCM_56770_A0) 23198 { /* SOC_FORMAT_INT_ING_FLEX_CTR_UDF_BCM56770_A0fmt */ 23199 /* format ING_FLEX_CTR_UDFfmt */ 23200 /* nFields */ 3, 23201 /* *fields */ soc_EGR_FLEX_CTR_UDF_BCM56960_A0fmt_fields, 23202 /* bits */ 33, 23203 /* flags */ 0, 23204 }, 23205 #endif /* chips */ 23206 23207 #if defined(BCM_56850_A0) 23208 { /* SOC_FORMAT_INT_ING_FLEX_CTR_UDF_BCM56850_A0fmt */ 23209 /* format ING_FLEX_CTR_UDFfmt */ 23210 /* nFields */ 3, 23211 /* *fields */ soc_EGR_FLEX_CTR_UDFfmt_fields, 23212 /* bits */ 33, 23213 /* flags */ 0, 23214 }, 23215 #endif /* chips */ 23216 23217 #if defined(BCM_56870_A0) 23218 { /* SOC_FORMAT_INT_ING_FLEX_CTR_UDF_BCM56870_A0fmt */ 23219 /* format ING_FLEX_CTR_UDFfmt */ 23220 /* nFields */ 3, 23221 /* *fields */ soc_EGR_FLEX_CTR_UDF_BCM56960_A0fmt_fields, 23222 /* bits */ 33, 23223 /* flags */ 0, 23224 }, 23225 #endif /* chips */ 23226 23227 #if defined(BCM_56960_A0) 23228 { /* SOC_FORMAT_INT_ING_FLEX_CTR_UDF_BCM56960_A0fmt */ 23229 /* format ING_FLEX_CTR_UDFfmt */ 23230 /* nFields */ 3, 23231 /* *fields */ soc_EGR_FLEX_CTR_UDF_BCM56960_A0fmt_fields, 23232 /* bits */ 33, 23233 /* flags */ 0, 23234 }, 23235 #endif /* chips */ 23236 23237 #if defined(BCM_56965_A0) 23238 { /* SOC_FORMAT_INT_ING_FLEX_CTR_UDF_BCM56965_A0fmt */ 23239 /* format ING_FLEX_CTR_UDFfmt */ 23240 /* nFields */ 3, 23241 /* *fields */ soc_EGR_FLEX_CTR_UDF_BCM56960_A0fmt_fields, 23242 /* bits */ 33, 23243 /* flags */ 0, 23244 }, 23245 #endif /* chips */ 23246 23247 #if defined(BCM_56970_A0) 23248 { /* SOC_FORMAT_INT_ING_FLEX_CTR_UDF_BCM56970_A0fmt */ 23249 /* format ING_FLEX_CTR_UDFfmt */ 23250 /* nFields */ 3, 23251 /* *fields */ soc_EGR_FLEX_CTR_UDF_BCM56960_A0fmt_fields, 23252 /* bits */ 33, 23253 /* flags */ 0, 23254 }, 23255 #endif /* chips */ 23256 23257 #if defined(BCM_56980_A0) 23258 { /* SOC_FORMAT_INT_ING_FLEX_CTR_UDF_BCM56980_A0fmt */ 23259 /* format ING_FLEX_CTR_UDFfmt */ 23260 /* nFields */ 3, 23261 /* *fields */ soc_EGR_FLEX_CTR_UDF_BCM56960_A0fmt_fields, 23262 /* bits */ 33, 23263 /* flags */ 0, 23264 }, 23265 #endif /* chips */ 23266 23267 #if defined(BCM_56980_B0) 23268 { /* SOC_FORMAT_INT_ING_FLEX_CTR_UDF_BCM56980_B0fmt */ 23269 /* format ING_FLEX_CTR_UDFfmt */ 23270 /* nFields */ 3, 23271 /* *fields */ soc_EGR_FLEX_CTR_UDF_BCM56960_A0fmt_fields, 23272 /* bits */ 33, 23273 /* flags */ 0, 23274 }, 23275 #endif /* chips */ 23276 23277 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) 23278 { /* SOC_FORMAT_INT_ING_FLEX_CTR_UDF_PKT_ATTRfmt */ 23279 /* format ING_FLEX_CTR_UDF_PKT_ATTRfmt */ 23280 /* nFields */ 5, 23281 /* *fields */ soc_ING_FLEX_CTR_UDF_PKT_ATTRfmt_fields, 23282 /* bits */ 35, 23283 /* flags */ 0, 23284 }, 23285 #endif /* chips */ 23286 23287 #if defined(BCM_56260_A0) 23288 { /* SOC_FORMAT_INT_ING_FLEX_CTR_UDF_PKT_ATTR_BCM56260_A0fmt */ 23289 /* format ING_FLEX_CTR_UDF_PKT_ATTRfmt */ 23290 /* nFields */ 5, 23291 /* *fields */ soc_ING_FLEX_CTR_UDF_PKT_ATTR_BCM56960_A0fmt_fields, 23292 /* bits */ 35, 23293 /* flags */ 0, 23294 }, 23295 #endif /* chips */ 23296 23297 #if defined(BCM_56260_B0) 23298 { /* SOC_FORMAT_INT_ING_FLEX_CTR_UDF_PKT_ATTR_BCM56260_B0fmt */ 23299 /* format ING_FLEX_CTR_UDF_PKT_ATTRfmt */ 23300 /* nFields */ 5, 23301 /* *fields */ soc_ING_FLEX_CTR_UDF_PKT_ATTR_BCM56960_A0fmt_fields, 23302 /* bits */ 35, 23303 /* flags */ 0, 23304 }, 23305 #endif /* chips */ 23306 23307 #if defined(BCM_56270_A0) 23308 { /* SOC_FORMAT_INT_ING_FLEX_CTR_UDF_PKT_ATTR_BCM56270_A0fmt */ 23309 /* format ING_FLEX_CTR_UDF_PKT_ATTRfmt */ 23310 /* nFields */ 5, 23311 /* *fields */ soc_ING_FLEX_CTR_UDF_PKT_ATTR_BCM56960_A0fmt_fields, 23312 /* bits */ 35, 23313 /* flags */ 0, 23314 }, 23315 #endif /* chips */ 23316 23317 #if defined(BCM_56340_A0) 23318 { /* SOC_FORMAT_INT_ING_FLEX_CTR_UDF_PKT_ATTR_BCM56340_A0fmt */ 23319 /* format ING_FLEX_CTR_UDF_PKT_ATTRfmt */ 23320 /* nFields */ 5, 23321 /* *fields */ soc_ING_FLEX_CTR_UDF_PKT_ATTR_BCM56640_A0fmt_fields, 23322 /* bits */ 35, 23323 /* flags */ 0, 23324 }, 23325 #endif /* chips */ 23326 23327 #if defined(BCM_56370_A0) 23328 { /* SOC_FORMAT_INT_ING_FLEX_CTR_UDF_PKT_ATTR_BCM56370_A0fmt */ 23329 /* format ING_FLEX_CTR_UDF_PKT_ATTRfmt */ 23330 /* nFields */ 5, 23331 /* *fields */ soc_ING_FLEX_CTR_UDF_PKT_ATTR_BCM56960_A0fmt_fields, 23332 /* bits */ 35, 23333 /* flags */ 0, 23334 }, 23335 #endif /* chips */ 23336 23337 #if defined(BCM_56450_A0) 23338 { /* SOC_FORMAT_INT_ING_FLEX_CTR_UDF_PKT_ATTR_BCM56450_A0fmt */ 23339 /* format ING_FLEX_CTR_UDF_PKT_ATTRfmt */ 23340 /* nFields */ 5, 23341 /* *fields */ soc_ING_FLEX_CTR_UDF_PKT_ATTR_BCM56640_A0fmt_fields, 23342 /* bits */ 35, 23343 /* flags */ 0, 23344 }, 23345 #endif /* chips */ 23346 23347 #if defined(BCM_56450_B0) 23348 { /* SOC_FORMAT_INT_ING_FLEX_CTR_UDF_PKT_ATTR_BCM56450_B0fmt */ 23349 /* format ING_FLEX_CTR_UDF_PKT_ATTRfmt */ 23350 /* nFields */ 5, 23351 /* *fields */ soc_ING_FLEX_CTR_UDF_PKT_ATTR_BCM56640_A0fmt_fields, 23352 /* bits */ 35, 23353 /* flags */ 0, 23354 }, 23355 #endif /* chips */ 23356 23357 #if defined(BCM_56450_B1) 23358 { /* SOC_FORMAT_INT_ING_FLEX_CTR_UDF_PKT_ATTR_BCM56450_B1fmt */ 23359 /* format ING_FLEX_CTR_UDF_PKT_ATTRfmt */ 23360 /* nFields */ 5, 23361 /* *fields */ soc_ING_FLEX_CTR_UDF_PKT_ATTR_BCM56640_A0fmt_fields, 23362 /* bits */ 35, 23363 /* flags */ 0, 23364 }, 23365 #endif /* chips */ 23366 23367 #if defined(BCM_56560_A0) 23368 { /* SOC_FORMAT_INT_ING_FLEX_CTR_UDF_PKT_ATTR_BCM56560_A0fmt */ 23369 /* format ING_FLEX_CTR_UDF_PKT_ATTRfmt */ 23370 /* nFields */ 5, 23371 /* *fields */ soc_ING_FLEX_CTR_UDF_PKT_ATTR_BCM56960_A0fmt_fields, 23372 /* bits */ 35, 23373 /* flags */ 0, 23374 }, 23375 #endif /* chips */ 23376 23377 #if defined(BCM_56560_B0) 23378 { /* SOC_FORMAT_INT_ING_FLEX_CTR_UDF_PKT_ATTR_BCM56560_B0fmt */ 23379 /* format ING_FLEX_CTR_UDF_PKT_ATTRfmt */ 23380 /* nFields */ 5, 23381 /* *fields */ soc_ING_FLEX_CTR_UDF_PKT_ATTR_BCM56960_A0fmt_fields, 23382 /* bits */ 35, 23383 /* flags */ 0, 23384 }, 23385 #endif /* chips */ 23386 23387 #if defined(BCM_56640_A0) 23388 { /* SOC_FORMAT_INT_ING_FLEX_CTR_UDF_PKT_ATTR_BCM56640_A0fmt */ 23389 /* format ING_FLEX_CTR_UDF_PKT_ATTRfmt */ 23390 /* nFields */ 5, 23391 /* *fields */ soc_ING_FLEX_CTR_UDF_PKT_ATTR_BCM56640_A0fmt_fields, 23392 /* bits */ 35, 23393 /* flags */ 0, 23394 }, 23395 #endif /* chips */ 23396 23397 #if defined(BCM_56670_A0) 23398 { /* SOC_FORMAT_INT_ING_FLEX_CTR_UDF_PKT_ATTR_BCM56670_A0fmt */ 23399 /* format ING_FLEX_CTR_UDF_PKT_ATTRfmt */ 23400 /* nFields */ 5, 23401 /* *fields */ soc_ING_FLEX_CTR_UDF_PKT_ATTR_BCM56960_A0fmt_fields, 23402 /* bits */ 35, 23403 /* flags */ 0, 23404 }, 23405 #endif /* chips */ 23406 23407 #if defined(BCM_56670_B0) 23408 { /* SOC_FORMAT_INT_ING_FLEX_CTR_UDF_PKT_ATTR_BCM56670_B0fmt */ 23409 /* format ING_FLEX_CTR_UDF_PKT_ATTRfmt */ 23410 /* nFields */ 5, 23411 /* *fields */ soc_ING_FLEX_CTR_UDF_PKT_ATTR_BCM56960_A0fmt_fields, 23412 /* bits */ 35, 23413 /* flags */ 0, 23414 }, 23415 #endif /* chips */ 23416 23417 #if defined(BCM_56770_A0) 23418 { /* SOC_FORMAT_INT_ING_FLEX_CTR_UDF_PKT_ATTR_BCM56770_A0fmt */ 23419 /* format ING_FLEX_CTR_UDF_PKT_ATTRfmt */ 23420 /* nFields */ 5, 23421 /* *fields */ soc_ING_FLEX_CTR_UDF_PKT_ATTR_BCM56960_A0fmt_fields, 23422 /* bits */ 35, 23423 /* flags */ 0, 23424 }, 23425 #endif /* chips */ 23426 23427 #if defined(BCM_56850_A0) 23428 { /* SOC_FORMAT_INT_ING_FLEX_CTR_UDF_PKT_ATTR_BCM56850_A0fmt */ 23429 /* format ING_FLEX_CTR_UDF_PKT_ATTRfmt */ 23430 /* nFields */ 5, 23431 /* *fields */ soc_ING_FLEX_CTR_UDF_PKT_ATTR_BCM56640_A0fmt_fields, 23432 /* bits */ 35, 23433 /* flags */ 0, 23434 }, 23435 #endif /* chips */ 23436 23437 #if defined(BCM_56860_A0) 23438 { /* SOC_FORMAT_INT_ING_FLEX_CTR_UDF_PKT_ATTR_BCM56860_A0fmt */ 23439 /* format ING_FLEX_CTR_UDF_PKT_ATTRfmt */ 23440 /* nFields */ 5, 23441 /* *fields */ soc_ING_FLEX_CTR_UDF_PKT_ATTR_BCM56640_A0fmt_fields, 23442 /* bits */ 35, 23443 /* flags */ 0, 23444 }, 23445 #endif /* chips */ 23446 23447 #if defined(BCM_56870_A0) 23448 { /* SOC_FORMAT_INT_ING_FLEX_CTR_UDF_PKT_ATTR_BCM56870_A0fmt */ 23449 /* format ING_FLEX_CTR_UDF_PKT_ATTRfmt */ 23450 /* nFields */ 5, 23451 /* *fields */ soc_ING_FLEX_CTR_UDF_PKT_ATTR_BCM56960_A0fmt_fields, 23452 /* bits */ 35, 23453 /* flags */ 0, 23454 }, 23455 #endif /* chips */ 23456 23457 #if defined(BCM_56960_A0) 23458 { /* SOC_FORMAT_INT_ING_FLEX_CTR_UDF_PKT_ATTR_BCM56960_A0fmt */ 23459 /* format ING_FLEX_CTR_UDF_PKT_ATTRfmt */ 23460 /* nFields */ 5, 23461 /* *fields */ soc_ING_FLEX_CTR_UDF_PKT_ATTR_BCM56960_A0fmt_fields, 23462 /* bits */ 35, 23463 /* flags */ 0, 23464 }, 23465 #endif /* chips */ 23466 23467 #if defined(BCM_56965_A0) 23468 { /* SOC_FORMAT_INT_ING_FLEX_CTR_UDF_PKT_ATTR_BCM56965_A0fmt */ 23469 /* format ING_FLEX_CTR_UDF_PKT_ATTRfmt */ 23470 /* nFields */ 5, 23471 /* *fields */ soc_ING_FLEX_CTR_UDF_PKT_ATTR_BCM56960_A0fmt_fields, 23472 /* bits */ 35, 23473 /* flags */ 0, 23474 }, 23475 #endif /* chips */ 23476 23477 #if defined(BCM_56970_A0) 23478 { /* SOC_FORMAT_INT_ING_FLEX_CTR_UDF_PKT_ATTR_BCM56970_A0fmt */ 23479 /* format ING_FLEX_CTR_UDF_PKT_ATTRfmt */ 23480 /* nFields */ 5, 23481 /* *fields */ soc_ING_FLEX_CTR_UDF_PKT_ATTR_BCM56960_A0fmt_fields, 23482 /* bits */ 35, 23483 /* flags */ 0, 23484 }, 23485 #endif /* chips */ 23486 23487 #if defined(BCM_56980_A0) 23488 { /* SOC_FORMAT_INT_ING_FLEX_CTR_UDF_PKT_ATTR_BCM56980_A0fmt */ 23489 /* format ING_FLEX_CTR_UDF_PKT_ATTRfmt */ 23490 /* nFields */ 5, 23491 /* *fields */ soc_ING_FLEX_CTR_UDF_PKT_ATTR_BCM56960_A0fmt_fields, 23492 /* bits */ 35, 23493 /* flags */ 0, 23494 }, 23495 #endif /* chips */ 23496 23497 #if defined(BCM_56980_B0) 23498 { /* SOC_FORMAT_INT_ING_FLEX_CTR_UDF_PKT_ATTR_BCM56980_B0fmt */ 23499 /* format ING_FLEX_CTR_UDF_PKT_ATTRfmt */ 23500 /* nFields */ 5, 23501 /* *fields */ soc_ING_FLEX_CTR_UDF_PKT_ATTR_BCM56960_A0fmt_fields, 23502 /* bits */ 35, 23503 /* flags */ 0, 23504 }, 23505 #endif /* chips */ 23506 23507 #if defined(BCM_56340_A0) || defined(BCM_56640_A0) 23508 { /* SOC_FORMAT_INT_ING_NIV_RX_FRAMES_ERROR_DROP_COV_DEFSfmt */ 23509 /* format ING_NIV_RX_FRAMES_ERROR_DROP_COV_DEFSfmt */ 23510 /* nFields */ 6, 23511 /* *fields */ soc_ING_NIV_RX_FRAMES_ERROR_DROP_COV_DEFSfmt_fields, 23512 /* bits */ 13, 23513 /* flags */ 0, 23514 }, 23515 #endif /* chips */ 23516 23517 #if defined(BCM_56370_A0) 23518 { /* SOC_FORMAT_INT_ING_NIV_RX_FRAMES_ERROR_DROP_COV_DEFS_BCM56370_A0fmt */ 23519 /* format ING_NIV_RX_FRAMES_ERROR_DROP_COV_DEFSfmt */ 23520 /* nFields */ 6, 23521 /* *fields */ soc_EGR_FCOE_DELIMITER_ERROR_FRAMES_TABLE_COV_DEFS_BCM56960_A0fmt_fields, 23522 /* bits */ 13, 23523 /* flags */ 0, 23524 }, 23525 #endif /* chips */ 23526 23527 #if defined(BCM_56560_A0) 23528 { /* SOC_FORMAT_INT_ING_NIV_RX_FRAMES_ERROR_DROP_COV_DEFS_BCM56560_A0fmt */ 23529 /* format ING_NIV_RX_FRAMES_ERROR_DROP_COV_DEFSfmt */ 23530 /* nFields */ 6, 23531 /* *fields */ soc_ISC_IP_STATS_COV_DEFS_BCM56960_A0fmt_fields, 23532 /* bits */ 14, 23533 /* flags */ 0, 23534 }, 23535 #endif /* chips */ 23536 23537 #if defined(BCM_56560_B0) 23538 { /* SOC_FORMAT_INT_ING_NIV_RX_FRAMES_ERROR_DROP_COV_DEFS_BCM56560_B0fmt */ 23539 /* format ING_NIV_RX_FRAMES_ERROR_DROP_COV_DEFSfmt */ 23540 /* nFields */ 6, 23541 /* *fields */ soc_ISC_IP_STATS_COV_DEFS_BCM56960_A0fmt_fields, 23542 /* bits */ 14, 23543 /* flags */ 0, 23544 }, 23545 #endif /* chips */ 23546 23547 #if defined(BCM_56670_A0) 23548 { /* SOC_FORMAT_INT_ING_NIV_RX_FRAMES_ERROR_DROP_COV_DEFS_BCM56670_A0fmt */ 23549 /* format ING_NIV_RX_FRAMES_ERROR_DROP_COV_DEFSfmt */ 23550 /* nFields */ 6, 23551 /* *fields */ soc_ISC_IP_STATS_COV_DEFS_BCM56960_A0fmt_fields, 23552 /* bits */ 14, 23553 /* flags */ 0, 23554 }, 23555 #endif /* chips */ 23556 23557 #if defined(BCM_56670_B0) 23558 { /* SOC_FORMAT_INT_ING_NIV_RX_FRAMES_ERROR_DROP_COV_DEFS_BCM56670_B0fmt */ 23559 /* format ING_NIV_RX_FRAMES_ERROR_DROP_COV_DEFSfmt */ 23560 /* nFields */ 6, 23561 /* *fields */ soc_ISC_IP_STATS_COV_DEFS_BCM56960_A0fmt_fields, 23562 /* bits */ 14, 23563 /* flags */ 0, 23564 }, 23565 #endif /* chips */ 23566 23567 #if defined(BCM_56770_A0) 23568 { /* SOC_FORMAT_INT_ING_NIV_RX_FRAMES_ERROR_DROP_COV_DEFS_BCM56770_A0fmt */ 23569 /* format ING_NIV_RX_FRAMES_ERROR_DROP_COV_DEFSfmt */ 23570 /* nFields */ 6, 23571 /* *fields */ soc_EGR_FCOE_DELIMITER_ERROR_FRAMES_TABLE_COV_DEFS_BCM56960_A0fmt_fields, 23572 /* bits */ 13, 23573 /* flags */ 0, 23574 }, 23575 #endif /* chips */ 23576 23577 #if defined(BCM_56850_A0) 23578 { /* SOC_FORMAT_INT_ING_NIV_RX_FRAMES_ERROR_DROP_COV_DEFS_BCM56850_A0fmt */ 23579 /* format ING_NIV_RX_FRAMES_ERROR_DROP_COV_DEFSfmt */ 23580 /* nFields */ 6, 23581 /* *fields */ soc_ISC_IP_STATS_COV_DEFSfmt_fields, 23582 /* bits */ 14, 23583 /* flags */ 0, 23584 }, 23585 #endif /* chips */ 23586 23587 #if defined(BCM_56860_A0) 23588 { /* SOC_FORMAT_INT_ING_NIV_RX_FRAMES_ERROR_DROP_COV_DEFS_BCM56860_A0fmt */ 23589 /* format ING_NIV_RX_FRAMES_ERROR_DROP_COV_DEFSfmt */ 23590 /* nFields */ 6, 23591 /* *fields */ soc_ISC_IP_STATS_COV_DEFSfmt_fields, 23592 /* bits */ 14, 23593 /* flags */ 0, 23594 }, 23595 #endif /* chips */ 23596 23597 #if defined(BCM_56870_A0) 23598 { /* SOC_FORMAT_INT_ING_NIV_RX_FRAMES_ERROR_DROP_COV_DEFS_BCM56870_A0fmt */ 23599 /* format ING_NIV_RX_FRAMES_ERROR_DROP_COV_DEFSfmt */ 23600 /* nFields */ 6, 23601 /* *fields */ soc_EGR_FCOE_DELIMITER_ERROR_FRAMES_TABLE_COV_DEFS_BCM56960_A0fmt_fields, 23602 /* bits */ 13, 23603 /* flags */ 0, 23604 }, 23605 #endif /* chips */ 23606 23607 #if defined(BCM_56960_A0) 23608 { /* SOC_FORMAT_INT_ING_NIV_RX_FRAMES_ERROR_DROP_COV_DEFS_BCM56960_A0fmt */ 23609 /* format ING_NIV_RX_FRAMES_ERROR_DROP_COV_DEFSfmt */ 23610 /* nFields */ 6, 23611 /* *fields */ soc_ISC_HG_STATS_COV_DEFS_BCM53400_A0fmt_fields, 23612 /* bits */ 11, 23613 /* flags */ 0, 23614 }, 23615 #endif /* chips */ 23616 23617 #if defined(BCM_56965_A0) 23618 { /* SOC_FORMAT_INT_ING_NIV_RX_FRAMES_ERROR_DROP_COV_DEFS_BCM56965_A0fmt */ 23619 /* format ING_NIV_RX_FRAMES_ERROR_DROP_COV_DEFSfmt */ 23620 /* nFields */ 6, 23621 /* *fields */ soc_ISC_HG_STATS_COV_DEFS_BCM53400_A0fmt_fields, 23622 /* bits */ 11, 23623 /* flags */ 0, 23624 }, 23625 #endif /* chips */ 23626 23627 #if defined(BCM_56970_A0) 23628 { /* SOC_FORMAT_INT_ING_NIV_RX_FRAMES_ERROR_DROP_COV_DEFS_BCM56970_A0fmt */ 23629 /* format ING_NIV_RX_FRAMES_ERROR_DROP_COV_DEFSfmt */ 23630 /* nFields */ 6, 23631 /* *fields */ soc_ISC_HG_STATS_COV_DEFS_BCM53400_A0fmt_fields, 23632 /* bits */ 11, 23633 /* flags */ 0, 23634 }, 23635 #endif /* chips */ 23636 23637 #if defined(BCM_56640_A0) 23638 { /* SOC_FORMAT_INT_ING_NIV_RX_FRAMES_FORWARDING_DROP_COV_DEFSfmt */ 23639 /* format ING_NIV_RX_FRAMES_FORWARDING_DROP_COV_DEFSfmt */ 23640 /* nFields */ 6, 23641 /* *fields */ soc_ING_NIV_RX_FRAMES_ERROR_DROP_COV_DEFSfmt_fields, 23642 /* bits */ 13, 23643 /* flags */ 0, 23644 }, 23645 #endif /* chips */ 23646 23647 #if defined(BCM_56340_A0) 23648 { /* SOC_FORMAT_INT_ING_NIV_RX_FRAMES_FORWARDING_DROP_COV_DEFS_BCM56340_A0fmt */ 23649 /* format ING_NIV_RX_FRAMES_FORWARDING_DROP_COV_DEFSfmt */ 23650 /* nFields */ 6, 23651 /* *fields */ soc_ING_NIV_RX_FRAMES_ERROR_DROP_COV_DEFSfmt_fields, 23652 /* bits */ 13, 23653 /* flags */ 0, 23654 }, 23655 #endif /* chips */ 23656 23657 #if defined(BCM_56370_A0) 23658 { /* SOC_FORMAT_INT_ING_NIV_RX_FRAMES_FORWARDING_DROP_COV_DEFS_BCM56370_A0fmt */ 23659 /* format ING_NIV_RX_FRAMES_FORWARDING_DROP_COV_DEFSfmt */ 23660 /* nFields */ 6, 23661 /* *fields */ soc_EGR_FCOE_DELIMITER_ERROR_FRAMES_TABLE_COV_DEFS_BCM56960_A0fmt_fields, 23662 /* bits */ 13, 23663 /* flags */ 0, 23664 }, 23665 #endif /* chips */ 23666 23667 #if defined(BCM_56560_A0) 23668 { /* SOC_FORMAT_INT_ING_NIV_RX_FRAMES_FORWARDING_DROP_COV_DEFS_BCM56560_A0fmt */ 23669 /* format ING_NIV_RX_FRAMES_FORWARDING_DROP_COV_DEFSfmt */ 23670 /* nFields */ 6, 23671 /* *fields */ soc_ISC_IP_STATS_COV_DEFS_BCM56960_A0fmt_fields, 23672 /* bits */ 14, 23673 /* flags */ 0, 23674 }, 23675 #endif /* chips */ 23676 23677 #if defined(BCM_56560_B0) 23678 { /* SOC_FORMAT_INT_ING_NIV_RX_FRAMES_FORWARDING_DROP_COV_DEFS_BCM56560_B0fmt */ 23679 /* format ING_NIV_RX_FRAMES_FORWARDING_DROP_COV_DEFSfmt */ 23680 /* nFields */ 6, 23681 /* *fields */ soc_ISC_IP_STATS_COV_DEFS_BCM56960_A0fmt_fields, 23682 /* bits */ 14, 23683 /* flags */ 0, 23684 }, 23685 #endif /* chips */ 23686 23687 #if defined(BCM_56670_A0) 23688 { /* SOC_FORMAT_INT_ING_NIV_RX_FRAMES_FORWARDING_DROP_COV_DEFS_BCM56670_A0fmt */ 23689 /* format ING_NIV_RX_FRAMES_FORWARDING_DROP_COV_DEFSfmt */ 23690 /* nFields */ 6, 23691 /* *fields */ soc_ISC_IP_STATS_COV_DEFS_BCM56960_A0fmt_fields, 23692 /* bits */ 14, 23693 /* flags */ 0, 23694 }, 23695 #endif /* chips */ 23696 23697 #if defined(BCM_56670_B0) 23698 { /* SOC_FORMAT_INT_ING_NIV_RX_FRAMES_FORWARDING_DROP_COV_DEFS_BCM56670_B0fmt */ 23699 /* format ING_NIV_RX_FRAMES_FORWARDING_DROP_COV_DEFSfmt */ 23700 /* nFields */ 6, 23701 /* *fields */ soc_ISC_IP_STATS_COV_DEFS_BCM56960_A0fmt_fields, 23702 /* bits */ 14, 23703 /* flags */ 0, 23704 }, 23705 #endif /* chips */ 23706 23707 #if defined(BCM_56770_A0) 23708 { /* SOC_FORMAT_INT_ING_NIV_RX_FRAMES_FORWARDING_DROP_COV_DEFS_BCM56770_A0fmt */ 23709 /* format ING_NIV_RX_FRAMES_FORWARDING_DROP_COV_DEFSfmt */ 23710 /* nFields */ 6, 23711 /* *fields */ soc_EGR_FCOE_DELIMITER_ERROR_FRAMES_TABLE_COV_DEFS_BCM56960_A0fmt_fields, 23712 /* bits */ 13, 23713 /* flags */ 0, 23714 }, 23715 #endif /* chips */ 23716 23717 #if defined(BCM_56850_A0) 23718 { /* SOC_FORMAT_INT_ING_NIV_RX_FRAMES_FORWARDING_DROP_COV_DEFS_BCM56850_A0fmt */ 23719 /* format ING_NIV_RX_FRAMES_FORWARDING_DROP_COV_DEFSfmt */ 23720 /* nFields */ 6, 23721 /* *fields */ soc_ISC_IP_STATS_COV_DEFSfmt_fields, 23722 /* bits */ 14, 23723 /* flags */ 0, 23724 }, 23725 #endif /* chips */ 23726 23727 #if defined(BCM_56860_A0) 23728 { /* SOC_FORMAT_INT_ING_NIV_RX_FRAMES_FORWARDING_DROP_COV_DEFS_BCM56860_A0fmt */ 23729 /* format ING_NIV_RX_FRAMES_FORWARDING_DROP_COV_DEFSfmt */ 23730 /* nFields */ 6, 23731 /* *fields */ soc_ISC_IP_STATS_COV_DEFSfmt_fields, 23732 /* bits */ 14, 23733 /* flags */ 0, 23734 }, 23735 #endif /* chips */ 23736 23737 #if defined(BCM_56870_A0) 23738 { /* SOC_FORMAT_INT_ING_NIV_RX_FRAMES_FORWARDING_DROP_COV_DEFS_BCM56870_A0fmt */ 23739 /* format ING_NIV_RX_FRAMES_FORWARDING_DROP_COV_DEFSfmt */ 23740 /* nFields */ 6, 23741 /* *fields */ soc_EGR_FCOE_DELIMITER_ERROR_FRAMES_TABLE_COV_DEFS_BCM56960_A0fmt_fields, 23742 /* bits */ 13, 23743 /* flags */ 0, 23744 }, 23745 #endif /* chips */ 23746 23747 #if defined(BCM_56960_A0) 23748 { /* SOC_FORMAT_INT_ING_NIV_RX_FRAMES_FORWARDING_DROP_COV_DEFS_BCM56960_A0fmt */ 23749 /* format ING_NIV_RX_FRAMES_FORWARDING_DROP_COV_DEFSfmt */ 23750 /* nFields */ 6, 23751 /* *fields */ soc_ISC_HG_STATS_COV_DEFS_BCM53400_A0fmt_fields, 23752 /* bits */ 11, 23753 /* flags */ 0, 23754 }, 23755 #endif /* chips */ 23756 23757 #if defined(BCM_56965_A0) 23758 { /* SOC_FORMAT_INT_ING_NIV_RX_FRAMES_FORWARDING_DROP_COV_DEFS_BCM56965_A0fmt */ 23759 /* format ING_NIV_RX_FRAMES_FORWARDING_DROP_COV_DEFSfmt */ 23760 /* nFields */ 6, 23761 /* *fields */ soc_ISC_HG_STATS_COV_DEFS_BCM53400_A0fmt_fields, 23762 /* bits */ 11, 23763 /* flags */ 0, 23764 }, 23765 #endif /* chips */ 23766 23767 #if defined(BCM_56970_A0) 23768 { /* SOC_FORMAT_INT_ING_NIV_RX_FRAMES_FORWARDING_DROP_COV_DEFS_BCM56970_A0fmt */ 23769 /* format ING_NIV_RX_FRAMES_FORWARDING_DROP_COV_DEFSfmt */ 23770 /* nFields */ 6, 23771 /* *fields */ soc_ISC_HG_STATS_COV_DEFS_BCM53400_A0fmt_fields, 23772 /* bits */ 11, 23773 /* flags */ 0, 23774 }, 23775 #endif /* chips */ 23776 23777 #if defined(BCM_56640_A0) 23778 { /* SOC_FORMAT_INT_ING_NIV_RX_FRAMES_VLAN_TAGGED_COV_DEFSfmt */ 23779 /* format ING_NIV_RX_FRAMES_VLAN_TAGGED_COV_DEFSfmt */ 23780 /* nFields */ 6, 23781 /* *fields */ soc_ING_NIV_RX_FRAMES_ERROR_DROP_COV_DEFSfmt_fields, 23782 /* bits */ 13, 23783 /* flags */ 0, 23784 }, 23785 #endif /* chips */ 23786 23787 #if defined(BCM_56340_A0) 23788 { /* SOC_FORMAT_INT_ING_NIV_RX_FRAMES_VLAN_TAGGED_COV_DEFS_BCM56340_A0fmt */ 23789 /* format ING_NIV_RX_FRAMES_VLAN_TAGGED_COV_DEFSfmt */ 23790 /* nFields */ 6, 23791 /* *fields */ soc_ING_NIV_RX_FRAMES_ERROR_DROP_COV_DEFSfmt_fields, 23792 /* bits */ 13, 23793 /* flags */ 0, 23794 }, 23795 #endif /* chips */ 23796 23797 #if defined(BCM_56370_A0) 23798 { /* SOC_FORMAT_INT_ING_NIV_RX_FRAMES_VLAN_TAGGED_COV_DEFS_BCM56370_A0fmt */ 23799 /* format ING_NIV_RX_FRAMES_VLAN_TAGGED_COV_DEFSfmt */ 23800 /* nFields */ 6, 23801 /* *fields */ soc_EGR_FCOE_DELIMITER_ERROR_FRAMES_TABLE_COV_DEFS_BCM56960_A0fmt_fields, 23802 /* bits */ 13, 23803 /* flags */ 0, 23804 }, 23805 #endif /* chips */ 23806 23807 #if defined(BCM_56560_A0) 23808 { /* SOC_FORMAT_INT_ING_NIV_RX_FRAMES_VLAN_TAGGED_COV_DEFS_BCM56560_A0fmt */ 23809 /* format ING_NIV_RX_FRAMES_VLAN_TAGGED_COV_DEFSfmt */ 23810 /* nFields */ 6, 23811 /* *fields */ soc_ISC_IP_STATS_COV_DEFS_BCM56960_A0fmt_fields, 23812 /* bits */ 14, 23813 /* flags */ 0, 23814 }, 23815 #endif /* chips */ 23816 23817 #if defined(BCM_56560_B0) 23818 { /* SOC_FORMAT_INT_ING_NIV_RX_FRAMES_VLAN_TAGGED_COV_DEFS_BCM56560_B0fmt */ 23819 /* format ING_NIV_RX_FRAMES_VLAN_TAGGED_COV_DEFSfmt */ 23820 /* nFields */ 6, 23821 /* *fields */ soc_ISC_IP_STATS_COV_DEFS_BCM56960_A0fmt_fields, 23822 /* bits */ 14, 23823 /* flags */ 0, 23824 }, 23825 #endif /* chips */ 23826 23827 #if defined(BCM_56670_A0) 23828 { /* SOC_FORMAT_INT_ING_NIV_RX_FRAMES_VLAN_TAGGED_COV_DEFS_BCM56670_A0fmt */ 23829 /* format ING_NIV_RX_FRAMES_VLAN_TAGGED_COV_DEFSfmt */ 23830 /* nFields */ 6, 23831 /* *fields */ soc_ISC_IP_STATS_COV_DEFS_BCM56960_A0fmt_fields, 23832 /* bits */ 14, 23833 /* flags */ 0, 23834 }, 23835 #endif /* chips */ 23836 23837 #if defined(BCM_56670_B0) 23838 { /* SOC_FORMAT_INT_ING_NIV_RX_FRAMES_VLAN_TAGGED_COV_DEFS_BCM56670_B0fmt */ 23839 /* format ING_NIV_RX_FRAMES_VLAN_TAGGED_COV_DEFSfmt */ 23840 /* nFields */ 6, 23841 /* *fields */ soc_ISC_IP_STATS_COV_DEFS_BCM56960_A0fmt_fields, 23842 /* bits */ 14, 23843 /* flags */ 0, 23844 }, 23845 #endif /* chips */ 23846 23847 #if defined(BCM_56770_A0) 23848 { /* SOC_FORMAT_INT_ING_NIV_RX_FRAMES_VLAN_TAGGED_COV_DEFS_BCM56770_A0fmt */ 23849 /* format ING_NIV_RX_FRAMES_VLAN_TAGGED_COV_DEFSfmt */ 23850 /* nFields */ 6, 23851 /* *fields */ soc_EGR_FCOE_DELIMITER_ERROR_FRAMES_TABLE_COV_DEFS_BCM56960_A0fmt_fields, 23852 /* bits */ 13, 23853 /* flags */ 0, 23854 }, 23855 #endif /* chips */ 23856 23857 #if defined(BCM_56850_A0) 23858 { /* SOC_FORMAT_INT_ING_NIV_RX_FRAMES_VLAN_TAGGED_COV_DEFS_BCM56850_A0fmt */ 23859 /* format ING_NIV_RX_FRAMES_VLAN_TAGGED_COV_DEFSfmt */ 23860 /* nFields */ 6, 23861 /* *fields */ soc_ISC_IP_STATS_COV_DEFSfmt_fields, 23862 /* bits */ 14, 23863 /* flags */ 0, 23864 }, 23865 #endif /* chips */ 23866 23867 #if defined(BCM_56860_A0) 23868 { /* SOC_FORMAT_INT_ING_NIV_RX_FRAMES_VLAN_TAGGED_COV_DEFS_BCM56860_A0fmt */ 23869 /* format ING_NIV_RX_FRAMES_VLAN_TAGGED_COV_DEFSfmt */ 23870 /* nFields */ 6, 23871 /* *fields */ soc_ISC_IP_STATS_COV_DEFSfmt_fields, 23872 /* bits */ 14, 23873 /* flags */ 0, 23874 }, 23875 #endif /* chips */ 23876 23877 #if defined(BCM_56870_A0) 23878 { /* SOC_FORMAT_INT_ING_NIV_RX_FRAMES_VLAN_TAGGED_COV_DEFS_BCM56870_A0fmt */ 23879 /* format ING_NIV_RX_FRAMES_VLAN_TAGGED_COV_DEFSfmt */ 23880 /* nFields */ 6, 23881 /* *fields */ soc_EGR_FCOE_DELIMITER_ERROR_FRAMES_TABLE_COV_DEFS_BCM56960_A0fmt_fields, 23882 /* bits */ 13, 23883 /* flags */ 0, 23884 }, 23885 #endif /* chips */ 23886 23887 #if defined(BCM_56960_A0) 23888 { /* SOC_FORMAT_INT_ING_NIV_RX_FRAMES_VLAN_TAGGED_COV_DEFS_BCM56960_A0fmt */ 23889 /* format ING_NIV_RX_FRAMES_VLAN_TAGGED_COV_DEFSfmt */ 23890 /* nFields */ 6, 23891 /* *fields */ soc_ISC_HG_STATS_COV_DEFS_BCM53400_A0fmt_fields, 23892 /* bits */ 11, 23893 /* flags */ 0, 23894 }, 23895 #endif /* chips */ 23896 23897 #if defined(BCM_56965_A0) 23898 { /* SOC_FORMAT_INT_ING_NIV_RX_FRAMES_VLAN_TAGGED_COV_DEFS_BCM56965_A0fmt */ 23899 /* format ING_NIV_RX_FRAMES_VLAN_TAGGED_COV_DEFSfmt */ 23900 /* nFields */ 6, 23901 /* *fields */ soc_ISC_HG_STATS_COV_DEFS_BCM53400_A0fmt_fields, 23902 /* bits */ 11, 23903 /* flags */ 0, 23904 }, 23905 #endif /* chips */ 23906 23907 #if defined(BCM_56970_A0) 23908 { /* SOC_FORMAT_INT_ING_NIV_RX_FRAMES_VLAN_TAGGED_COV_DEFS_BCM56970_A0fmt */ 23909 /* format ING_NIV_RX_FRAMES_VLAN_TAGGED_COV_DEFSfmt */ 23910 /* nFields */ 6, 23911 /* *fields */ soc_ISC_HG_STATS_COV_DEFS_BCM53400_A0fmt_fields, 23912 /* bits */ 11, 23913 /* flags */ 0, 23914 }, 23915 #endif /* chips */ 23916 23917 #if defined(BCM_56640_A0) 23918 { /* SOC_FORMAT_INT_ING_PW_TERM_SEQ_NUM_COV_DEFSfmt */ 23919 /* format ING_PW_TERM_SEQ_NUM_COV_DEFSfmt */ 23920 /* nFields */ 6, 23921 /* *fields */ soc_EP_PW_INIT_COUNTER_COV_DEFSfmt_fields, 23922 /* bits */ 20, 23923 /* flags */ 0, 23924 }, 23925 #endif /* chips */ 23926 23927 #if defined(BCM_56340_A0) 23928 { /* SOC_FORMAT_INT_ING_PW_TERM_SEQ_NUM_COV_DEFS_BCM56340_A0fmt */ 23929 /* format ING_PW_TERM_SEQ_NUM_COV_DEFSfmt */ 23930 /* nFields */ 6, 23931 /* *fields */ soc_EP_PW_INIT_COUNTER_COV_DEFSfmt_fields, 23932 /* bits */ 20, 23933 /* flags */ 0, 23934 }, 23935 #endif /* chips */ 23936 23937 #if defined(BCM_56370_A0) 23938 { /* SOC_FORMAT_INT_ING_PW_TERM_SEQ_NUM_COV_DEFS_BCM56370_A0fmt */ 23939 /* format ING_PW_TERM_SEQ_NUM_COV_DEFSfmt */ 23940 /* nFields */ 6, 23941 /* *fields */ soc_EGR_SEQUENCE_NUMBER_TABLE_COV_DEFSfmt_fields, 23942 /* bits */ 20, 23943 /* flags */ 0, 23944 }, 23945 #endif /* chips */ 23946 23947 #if defined(BCM_56560_A0) 23948 { /* SOC_FORMAT_INT_ING_PW_TERM_SEQ_NUM_COV_DEFS_BCM56560_A0fmt */ 23949 /* format ING_PW_TERM_SEQ_NUM_COV_DEFSfmt */ 23950 /* nFields */ 7, 23951 /* *fields */ soc_ING_PW_TERM_SEQ_NUM_COV_DEFS_BCM56560_A0fmt_fields, 23952 /* bits */ 21, 23953 /* flags */ 0, 23954 }, 23955 #endif /* chips */ 23956 23957 #if defined(BCM_56560_B0) 23958 { /* SOC_FORMAT_INT_ING_PW_TERM_SEQ_NUM_COV_DEFS_BCM56560_B0fmt */ 23959 /* format ING_PW_TERM_SEQ_NUM_COV_DEFSfmt */ 23960 /* nFields */ 7, 23961 /* *fields */ soc_ING_PW_TERM_SEQ_NUM_COV_DEFS_BCM56560_A0fmt_fields, 23962 /* bits */ 21, 23963 /* flags */ 0, 23964 }, 23965 #endif /* chips */ 23966 23967 #if defined(BCM_56670_A0) 23968 { /* SOC_FORMAT_INT_ING_PW_TERM_SEQ_NUM_COV_DEFS_BCM56670_A0fmt */ 23969 /* format ING_PW_TERM_SEQ_NUM_COV_DEFSfmt */ 23970 /* nFields */ 7, 23971 /* *fields */ soc_ING_PW_TERM_SEQ_NUM_COV_DEFS_BCM56560_A0fmt_fields, 23972 /* bits */ 21, 23973 /* flags */ 0, 23974 }, 23975 #endif /* chips */ 23976 23977 #if defined(BCM_56670_B0) 23978 { /* SOC_FORMAT_INT_ING_PW_TERM_SEQ_NUM_COV_DEFS_BCM56670_B0fmt */ 23979 /* format ING_PW_TERM_SEQ_NUM_COV_DEFSfmt */ 23980 /* nFields */ 7, 23981 /* *fields */ soc_ING_PW_TERM_SEQ_NUM_COV_DEFS_BCM56560_A0fmt_fields, 23982 /* bits */ 21, 23983 /* flags */ 0, 23984 }, 23985 #endif /* chips */ 23986 23987 #if defined(BCM_56770_A0) 23988 { /* SOC_FORMAT_INT_ING_PW_TERM_SEQ_NUM_COV_DEFS_BCM56770_A0fmt */ 23989 /* format ING_PW_TERM_SEQ_NUM_COV_DEFSfmt */ 23990 /* nFields */ 6, 23991 /* *fields */ soc_EGR_SEQUENCE_NUMBER_TABLE_COV_DEFSfmt_fields, 23992 /* bits */ 20, 23993 /* flags */ 0, 23994 }, 23995 #endif /* chips */ 23996 23997 #if defined(BCM_56850_A0) 23998 { /* SOC_FORMAT_INT_ING_PW_TERM_SEQ_NUM_COV_DEFS_BCM56850_A0fmt */ 23999 /* format ING_PW_TERM_SEQ_NUM_COV_DEFSfmt */ 24000 /* nFields */ 6, 24001 /* *fields */ soc_EP_PW_INIT_COUNTER_COV_DEFSfmt_fields, 24002 /* bits */ 20, 24003 /* flags */ 0, 24004 }, 24005 #endif /* chips */ 24006 24007 #if defined(BCM_56860_A0) 24008 { /* SOC_FORMAT_INT_ING_PW_TERM_SEQ_NUM_COV_DEFS_BCM56860_A0fmt */ 24009 /* format ING_PW_TERM_SEQ_NUM_COV_DEFSfmt */ 24010 /* nFields */ 7, 24011 /* *fields */ soc_ING_PW_TERM_SEQ_NUM_COV_DEFS_BCM56860_A0fmt_fields, 24012 /* bits */ 21, 24013 /* flags */ 0, 24014 }, 24015 #endif /* chips */ 24016 24017 #if defined(BCM_56870_A0) 24018 { /* SOC_FORMAT_INT_ING_PW_TERM_SEQ_NUM_COV_DEFS_BCM56870_A0fmt */ 24019 /* format ING_PW_TERM_SEQ_NUM_COV_DEFSfmt */ 24020 /* nFields */ 6, 24021 /* *fields */ soc_EGR_SEQUENCE_NUMBER_TABLE_COV_DEFSfmt_fields, 24022 /* bits */ 20, 24023 /* flags */ 0, 24024 }, 24025 #endif /* chips */ 24026 24027 #if defined(BCM_56960_A0) 24028 { /* SOC_FORMAT_INT_ING_PW_TERM_SEQ_NUM_COV_DEFS_BCM56960_A0fmt */ 24029 /* format ING_PW_TERM_SEQ_NUM_COV_DEFSfmt */ 24030 /* nFields */ 6, 24031 /* *fields */ soc_ING_PW_TERM_SEQ_NUM_COV_DEFSfmt_fields, 24032 /* bits */ 19, 24033 /* flags */ 0, 24034 }, 24035 #endif /* chips */ 24036 24037 #if defined(BCM_56965_A0) 24038 { /* SOC_FORMAT_INT_ING_PW_TERM_SEQ_NUM_COV_DEFS_BCM56965_A0fmt */ 24039 /* format ING_PW_TERM_SEQ_NUM_COV_DEFSfmt */ 24040 /* nFields */ 6, 24041 /* *fields */ soc_ING_PW_TERM_SEQ_NUM_COV_DEFSfmt_fields, 24042 /* bits */ 19, 24043 /* flags */ 0, 24044 }, 24045 #endif /* chips */ 24046 24047 #if defined(BCM_56970_A0) 24048 { /* SOC_FORMAT_INT_ING_PW_TERM_SEQ_NUM_COV_DEFS_BCM56970_A0fmt */ 24049 /* format ING_PW_TERM_SEQ_NUM_COV_DEFSfmt */ 24050 /* nFields */ 6, 24051 /* *fields */ soc_EGR_PERQ_XMT_COUNTERS_COV_DEFS_BCM56960_A0fmt_fields, 24052 /* bits */ 17, 24053 /* flags */ 0, 24054 }, 24055 #endif /* chips */ 24056 24057 #if defined(BCM_56840_B0) 24058 { /* SOC_FORMAT_INT_ING_Q_BUSfmt */ 24059 /* format ING_Q_BUSfmt */ 24060 /* nFields */ 5, 24061 /* *fields */ soc_ING_Q_BUSfmt_fields, 24062 /* bits */ 32, 24063 /* flags */ 0, 24064 }, 24065 #endif /* chips */ 24066 24067 #if defined(BCM_56370_A0) 24068 { /* SOC_FORMAT_INT_ING_Q_BUS_BCM56370_A0fmt */ 24069 /* format ING_Q_BUSfmt */ 24070 /* nFields */ 2, 24071 /* *fields */ soc_ING_Q_BUS_BCM56370_A0fmt_fields, 24072 /* bits */ 32, 24073 /* flags */ 0, 24074 }, 24075 #endif /* chips */ 24076 24077 #if defined(BCM_56560_A0) 24078 { /* SOC_FORMAT_INT_ING_Q_BUS_BCM56560_A0fmt */ 24079 /* format ING_Q_BUSfmt */ 24080 /* nFields */ 3, 24081 /* *fields */ soc_ING_Q_BUS_BCM56560_A0fmt_fields, 24082 /* bits */ 32, 24083 /* flags */ 0, 24084 }, 24085 #endif /* chips */ 24086 24087 #if defined(BCM_56560_B0) 24088 { /* SOC_FORMAT_INT_ING_Q_BUS_BCM56560_B0fmt */ 24089 /* format ING_Q_BUSfmt */ 24090 /* nFields */ 3, 24091 /* *fields */ soc_ING_Q_BUS_BCM56560_A0fmt_fields, 24092 /* bits */ 32, 24093 /* flags */ 0, 24094 }, 24095 #endif /* chips */ 24096 24097 #if defined(BCM_56670_A0) 24098 { /* SOC_FORMAT_INT_ING_Q_BUS_BCM56670_A0fmt */ 24099 /* format ING_Q_BUSfmt */ 24100 /* nFields */ 3, 24101 /* *fields */ soc_ING_Q_BUS_BCM56560_A0fmt_fields, 24102 /* bits */ 32, 24103 /* flags */ 0, 24104 }, 24105 #endif /* chips */ 24106 24107 #if defined(BCM_56670_B0) 24108 { /* SOC_FORMAT_INT_ING_Q_BUS_BCM56670_B0fmt */ 24109 /* format ING_Q_BUSfmt */ 24110 /* nFields */ 3, 24111 /* *fields */ soc_ING_Q_BUS_BCM56560_A0fmt_fields, 24112 /* bits */ 32, 24113 /* flags */ 0, 24114 }, 24115 #endif /* chips */ 24116 24117 #if defined(BCM_56770_A0) 24118 { /* SOC_FORMAT_INT_ING_Q_BUS_BCM56770_A0fmt */ 24119 /* format ING_Q_BUSfmt */ 24120 /* nFields */ 4, 24121 /* *fields */ soc_ING_Q_BUS_BCM56770_A0fmt_fields, 24122 /* bits */ 32, 24123 /* flags */ 0, 24124 }, 24125 #endif /* chips */ 24126 24127 #if defined(BCM_56850_A0) 24128 { /* SOC_FORMAT_INT_ING_Q_BUS_BCM56850_A0fmt */ 24129 /* format ING_Q_BUSfmt */ 24130 /* nFields */ 3, 24131 /* *fields */ soc_ING_Q_BUS_BCM56850_A0fmt_fields, 24132 /* bits */ 32, 24133 /* flags */ 0, 24134 }, 24135 #endif /* chips */ 24136 24137 #if defined(BCM_56860_A0) 24138 { /* SOC_FORMAT_INT_ING_Q_BUS_BCM56860_A0fmt */ 24139 /* format ING_Q_BUSfmt */ 24140 /* nFields */ 3, 24141 /* *fields */ soc_ING_Q_BUS_BCM56860_A0fmt_fields, 24142 /* bits */ 32, 24143 /* flags */ 0, 24144 }, 24145 #endif /* chips */ 24146 24147 #if defined(BCM_56870_A0) 24148 { /* SOC_FORMAT_INT_ING_Q_BUS_BCM56870_A0fmt */ 24149 /* format ING_Q_BUSfmt */ 24150 /* nFields */ 1, 24151 /* *fields */ soc_ING_Q_BUS_BCM56870_A0fmt_fields, 24152 /* bits */ 32, 24153 /* flags */ 0, 24154 }, 24155 #endif /* chips */ 24156 24157 #if defined(BCM_56960_A0) 24158 { /* SOC_FORMAT_INT_ING_Q_BUS_BCM56960_A0fmt */ 24159 /* format ING_Q_BUSfmt */ 24160 /* nFields */ 3, 24161 /* *fields */ soc_ING_Q_BUS_BCM56960_A0fmt_fields, 24162 /* bits */ 32, 24163 /* flags */ 0, 24164 }, 24165 #endif /* chips */ 24166 24167 #if defined(BCM_56965_A0) 24168 { /* SOC_FORMAT_INT_ING_Q_BUS_BCM56965_A0fmt */ 24169 /* format ING_Q_BUSfmt */ 24170 /* nFields */ 3, 24171 /* *fields */ soc_ING_Q_BUS_BCM56960_A0fmt_fields, 24172 /* bits */ 32, 24173 /* flags */ 0, 24174 }, 24175 #endif /* chips */ 24176 24177 #if defined(BCM_56970_A0) 24178 { /* SOC_FORMAT_INT_ING_Q_BUS_BCM56970_A0fmt */ 24179 /* format ING_Q_BUSfmt */ 24180 /* nFields */ 3, 24181 /* *fields */ soc_ING_Q_BUS_BCM56960_A0fmt_fields, 24182 /* bits */ 32, 24183 /* flags */ 0, 24184 }, 24185 #endif /* chips */ 24186 24187 #if defined(BCM_56980_A0) 24188 { /* SOC_FORMAT_INT_ING_Q_BUS_BCM56980_A0fmt */ 24189 /* format ING_Q_BUSfmt */ 24190 /* nFields */ 3, 24191 /* *fields */ soc_ING_Q_BUS_BCM56560_A0fmt_fields, 24192 /* bits */ 32, 24193 /* flags */ 0, 24194 }, 24195 #endif /* chips */ 24196 24197 #if defined(BCM_56980_B0) 24198 { /* SOC_FORMAT_INT_ING_Q_BUS_BCM56980_B0fmt */ 24199 /* format ING_Q_BUSfmt */ 24200 /* nFields */ 3, 24201 /* *fields */ soc_ING_Q_BUS_BCM56560_A0fmt_fields, 24202 /* bits */ 32, 24203 /* flags */ 0, 24204 }, 24205 #endif /* chips */ 24206 24207 #if defined(BCM_56440_A0) 24208 { /* SOC_FORMAT_INT_ING_SVM_UDF_PKT_ATTRfmt */ 24209 /* format ING_SVM_UDF_PKT_ATTRfmt */ 24210 /* nFields */ 5, 24211 /* *fields */ soc_ING_FLEX_CTR_UDF_PKT_ATTRfmt_fields, 24212 /* bits */ 35, 24213 /* flags */ 0, 24214 }, 24215 #endif /* chips */ 24216 24217 #if defined(BCM_53570_A0) 24218 { /* SOC_FORMAT_INT_ING_SVM_UDF_PKT_ATTR_BCM53570_A0fmt */ 24219 /* format ING_SVM_UDF_PKT_ATTRfmt */ 24220 /* nFields */ 4, 24221 /* *fields */ soc_ING_SVM_UDF_PKT_ATTRfmt_fields, 24222 /* bits */ 34, 24223 /* flags */ 0, 24224 }, 24225 #endif /* chips */ 24226 24227 #if defined(BCM_53570_B0) 24228 { /* SOC_FORMAT_INT_ING_SVM_UDF_PKT_ATTR_BCM53570_B0fmt */ 24229 /* format ING_SVM_UDF_PKT_ATTRfmt */ 24230 /* nFields */ 4, 24231 /* *fields */ soc_ING_SVM_UDF_PKT_ATTRfmt_fields, 24232 /* bits */ 34, 24233 /* flags */ 0, 24234 }, 24235 #endif /* chips */ 24236 24237 #if defined(BCM_56260_A0) 24238 { /* SOC_FORMAT_INT_ING_SVM_UDF_PKT_ATTR_BCM56260_A0fmt */ 24239 /* format ING_SVM_UDF_PKT_ATTRfmt */ 24240 /* nFields */ 5, 24241 /* *fields */ soc_ING_FLEX_CTR_UDF_PKT_ATTR_BCM56960_A0fmt_fields, 24242 /* bits */ 35, 24243 /* flags */ 0, 24244 }, 24245 #endif /* chips */ 24246 24247 #if defined(BCM_56260_B0) 24248 { /* SOC_FORMAT_INT_ING_SVM_UDF_PKT_ATTR_BCM56260_B0fmt */ 24249 /* format ING_SVM_UDF_PKT_ATTRfmt */ 24250 /* nFields */ 5, 24251 /* *fields */ soc_ING_FLEX_CTR_UDF_PKT_ATTR_BCM56960_A0fmt_fields, 24252 /* bits */ 35, 24253 /* flags */ 0, 24254 }, 24255 #endif /* chips */ 24256 24257 #if defined(BCM_56270_A0) 24258 { /* SOC_FORMAT_INT_ING_SVM_UDF_PKT_ATTR_BCM56270_A0fmt */ 24259 /* format ING_SVM_UDF_PKT_ATTRfmt */ 24260 /* nFields */ 5, 24261 /* *fields */ soc_ING_FLEX_CTR_UDF_PKT_ATTR_BCM56960_A0fmt_fields, 24262 /* bits */ 35, 24263 /* flags */ 0, 24264 }, 24265 #endif /* chips */ 24266 24267 #if defined(BCM_56340_A0) 24268 { /* SOC_FORMAT_INT_ING_SVM_UDF_PKT_ATTR_BCM56340_A0fmt */ 24269 /* format ING_SVM_UDF_PKT_ATTRfmt */ 24270 /* nFields */ 5, 24271 /* *fields */ soc_ING_FLEX_CTR_UDF_PKT_ATTR_BCM56640_A0fmt_fields, 24272 /* bits */ 35, 24273 /* flags */ 0, 24274 }, 24275 #endif /* chips */ 24276 24277 #if defined(BCM_56440_B0) 24278 { /* SOC_FORMAT_INT_ING_SVM_UDF_PKT_ATTR_BCM56440_B0fmt */ 24279 /* format ING_SVM_UDF_PKT_ATTRfmt */ 24280 /* nFields */ 5, 24281 /* *fields */ soc_ING_FLEX_CTR_UDF_PKT_ATTRfmt_fields, 24282 /* bits */ 35, 24283 /* flags */ 0, 24284 }, 24285 #endif /* chips */ 24286 24287 #if defined(BCM_56450_A0) 24288 { /* SOC_FORMAT_INT_ING_SVM_UDF_PKT_ATTR_BCM56450_A0fmt */ 24289 /* format ING_SVM_UDF_PKT_ATTRfmt */ 24290 /* nFields */ 5, 24291 /* *fields */ soc_ING_FLEX_CTR_UDF_PKT_ATTR_BCM56640_A0fmt_fields, 24292 /* bits */ 35, 24293 /* flags */ 0, 24294 }, 24295 #endif /* chips */ 24296 24297 #if defined(BCM_56450_B0) 24298 { /* SOC_FORMAT_INT_ING_SVM_UDF_PKT_ATTR_BCM56450_B0fmt */ 24299 /* format ING_SVM_UDF_PKT_ATTRfmt */ 24300 /* nFields */ 5, 24301 /* *fields */ soc_ING_FLEX_CTR_UDF_PKT_ATTR_BCM56640_A0fmt_fields, 24302 /* bits */ 35, 24303 /* flags */ 0, 24304 }, 24305 #endif /* chips */ 24306 24307 #if defined(BCM_56450_B1) 24308 { /* SOC_FORMAT_INT_ING_SVM_UDF_PKT_ATTR_BCM56450_B1fmt */ 24309 /* format ING_SVM_UDF_PKT_ATTRfmt */ 24310 /* nFields */ 5, 24311 /* *fields */ soc_ING_FLEX_CTR_UDF_PKT_ATTR_BCM56640_A0fmt_fields, 24312 /* bits */ 35, 24313 /* flags */ 0, 24314 }, 24315 #endif /* chips */ 24316 24317 #if defined(BCM_56560_A0) 24318 { /* SOC_FORMAT_INT_ING_SVM_UDF_PKT_ATTR_BCM56560_A0fmt */ 24319 /* format ING_SVM_UDF_PKT_ATTRfmt */ 24320 /* nFields */ 5, 24321 /* *fields */ soc_ING_FLEX_CTR_UDF_PKT_ATTR_BCM56960_A0fmt_fields, 24322 /* bits */ 35, 24323 /* flags */ 0, 24324 }, 24325 #endif /* chips */ 24326 24327 #if defined(BCM_56560_B0) 24328 { /* SOC_FORMAT_INT_ING_SVM_UDF_PKT_ATTR_BCM56560_B0fmt */ 24329 /* format ING_SVM_UDF_PKT_ATTRfmt */ 24330 /* nFields */ 5, 24331 /* *fields */ soc_ING_FLEX_CTR_UDF_PKT_ATTR_BCM56960_A0fmt_fields, 24332 /* bits */ 35, 24333 /* flags */ 0, 24334 }, 24335 #endif /* chips */ 24336 24337 #if defined(BCM_56640_A0) 24338 { /* SOC_FORMAT_INT_ING_SVM_UDF_PKT_ATTR_BCM56640_A0fmt */ 24339 /* format ING_SVM_UDF_PKT_ATTRfmt */ 24340 /* nFields */ 5, 24341 /* *fields */ soc_ING_FLEX_CTR_UDF_PKT_ATTR_BCM56640_A0fmt_fields, 24342 /* bits */ 35, 24343 /* flags */ 0, 24344 }, 24345 #endif /* chips */ 24346 24347 #if defined(BCM_56670_A0) 24348 { /* SOC_FORMAT_INT_ING_SVM_UDF_PKT_ATTR_BCM56670_A0fmt */ 24349 /* format ING_SVM_UDF_PKT_ATTRfmt */ 24350 /* nFields */ 5, 24351 /* *fields */ soc_ING_FLEX_CTR_UDF_PKT_ATTR_BCM56960_A0fmt_fields, 24352 /* bits */ 35, 24353 /* flags */ 0, 24354 }, 24355 #endif /* chips */ 24356 24357 #if defined(BCM_56670_B0) 24358 { /* SOC_FORMAT_INT_ING_SVM_UDF_PKT_ATTR_BCM56670_B0fmt */ 24359 /* format ING_SVM_UDF_PKT_ATTRfmt */ 24360 /* nFields */ 5, 24361 /* *fields */ soc_ING_FLEX_CTR_UDF_PKT_ATTR_BCM56960_A0fmt_fields, 24362 /* bits */ 35, 24363 /* flags */ 0, 24364 }, 24365 #endif /* chips */ 24366 24367 #if defined(BCM_56640_A0) 24368 { /* SOC_FORMAT_INT_ING_TRILL_RX_ACCESS_PORT_TRILL_PKTS_DISCARDED_COV_DEFSfmt */ 24369 /* format ING_TRILL_RX_ACCESS_PORT_TRILL_PKTS_DISCARDED_COV_DEFSfmt */ 24370 /* nFields */ 6, 24371 /* *fields */ soc_ING_NIV_RX_FRAMES_ERROR_DROP_COV_DEFSfmt_fields, 24372 /* bits */ 13, 24373 /* flags */ 0, 24374 }, 24375 #endif /* chips */ 24376 24377 #if defined(BCM_56340_A0) 24378 { /* SOC_FORMAT_INT_ING_TRILL_RX_ACCESS_PORT_TRILL_PKTS_DISCARDED_COV_DEFS_BCM56340_A0fmt */ 24379 /* format ING_TRILL_RX_ACCESS_PORT_TRILL_PKTS_DISCARDED_COV_DEFSfmt */ 24380 /* nFields */ 6, 24381 /* *fields */ soc_ING_NIV_RX_FRAMES_ERROR_DROP_COV_DEFSfmt_fields, 24382 /* bits */ 13, 24383 /* flags */ 0, 24384 }, 24385 #endif /* chips */ 24386 24387 #if defined(BCM_56560_A0) 24388 { /* SOC_FORMAT_INT_ING_TRILL_RX_ACCESS_PORT_TRILL_PKTS_DISCARDED_COV_DEFS_BCM56560_A0fmt */ 24389 /* format ING_TRILL_RX_ACCESS_PORT_TRILL_PKTS_DISCARDED_COV_DEFSfmt */ 24390 /* nFields */ 6, 24391 /* *fields */ soc_ISC_IP_STATS_COV_DEFS_BCM56960_A0fmt_fields, 24392 /* bits */ 14, 24393 /* flags */ 0, 24394 }, 24395 #endif /* chips */ 24396 24397 #if defined(BCM_56560_B0) 24398 { /* SOC_FORMAT_INT_ING_TRILL_RX_ACCESS_PORT_TRILL_PKTS_DISCARDED_COV_DEFS_BCM56560_B0fmt */ 24399 /* format ING_TRILL_RX_ACCESS_PORT_TRILL_PKTS_DISCARDED_COV_DEFSfmt */ 24400 /* nFields */ 6, 24401 /* *fields */ soc_ISC_IP_STATS_COV_DEFS_BCM56960_A0fmt_fields, 24402 /* bits */ 14, 24403 /* flags */ 0, 24404 }, 24405 #endif /* chips */ 24406 24407 #if defined(BCM_56670_A0) 24408 { /* SOC_FORMAT_INT_ING_TRILL_RX_ACCESS_PORT_TRILL_PKTS_DISCARDED_COV_DEFS_BCM56670_A0fmt */ 24409 /* format ING_TRILL_RX_ACCESS_PORT_TRILL_PKTS_DISCARDED_COV_DEFSfmt */ 24410 /* nFields */ 6, 24411 /* *fields */ soc_ISC_IP_STATS_COV_DEFS_BCM56960_A0fmt_fields, 24412 /* bits */ 14, 24413 /* flags */ 0, 24414 }, 24415 #endif /* chips */ 24416 24417 #if defined(BCM_56670_B0) 24418 { /* SOC_FORMAT_INT_ING_TRILL_RX_ACCESS_PORT_TRILL_PKTS_DISCARDED_COV_DEFS_BCM56670_B0fmt */ 24419 /* format ING_TRILL_RX_ACCESS_PORT_TRILL_PKTS_DISCARDED_COV_DEFSfmt */ 24420 /* nFields */ 6, 24421 /* *fields */ soc_ISC_IP_STATS_COV_DEFS_BCM56960_A0fmt_fields, 24422 /* bits */ 14, 24423 /* flags */ 0, 24424 }, 24425 #endif /* chips */ 24426 24427 #if defined(BCM_56850_A0) 24428 { /* SOC_FORMAT_INT_ING_TRILL_RX_ACCESS_PORT_TRILL_PKTS_DISCARDED_COV_DEFS_BCM56850_A0fmt */ 24429 /* format ING_TRILL_RX_ACCESS_PORT_TRILL_PKTS_DISCARDED_COV_DEFSfmt */ 24430 /* nFields */ 6, 24431 /* *fields */ soc_ISC_IP_STATS_COV_DEFSfmt_fields, 24432 /* bits */ 14, 24433 /* flags */ 0, 24434 }, 24435 #endif /* chips */ 24436 24437 #if defined(BCM_56860_A0) 24438 { /* SOC_FORMAT_INT_ING_TRILL_RX_ACCESS_PORT_TRILL_PKTS_DISCARDED_COV_DEFS_BCM56860_A0fmt */ 24439 /* format ING_TRILL_RX_ACCESS_PORT_TRILL_PKTS_DISCARDED_COV_DEFSfmt */ 24440 /* nFields */ 6, 24441 /* *fields */ soc_ISC_IP_STATS_COV_DEFSfmt_fields, 24442 /* bits */ 14, 24443 /* flags */ 0, 24444 }, 24445 #endif /* chips */ 24446 24447 #if defined(BCM_56960_A0) 24448 { /* SOC_FORMAT_INT_ING_TRILL_RX_ACCESS_PORT_TRILL_PKTS_DISCARDED_COV_DEFS_BCM56960_A0fmt */ 24449 /* format ING_TRILL_RX_ACCESS_PORT_TRILL_PKTS_DISCARDED_COV_DEFSfmt */ 24450 /* nFields */ 6, 24451 /* *fields */ soc_ISC_HG_STATS_COV_DEFS_BCM53400_A0fmt_fields, 24452 /* bits */ 11, 24453 /* flags */ 0, 24454 }, 24455 #endif /* chips */ 24456 24457 #if defined(BCM_56965_A0) 24458 { /* SOC_FORMAT_INT_ING_TRILL_RX_ACCESS_PORT_TRILL_PKTS_DISCARDED_COV_DEFS_BCM56965_A0fmt */ 24459 /* format ING_TRILL_RX_ACCESS_PORT_TRILL_PKTS_DISCARDED_COV_DEFSfmt */ 24460 /* nFields */ 6, 24461 /* *fields */ soc_ISC_HG_STATS_COV_DEFS_BCM53400_A0fmt_fields, 24462 /* bits */ 11, 24463 /* flags */ 0, 24464 }, 24465 #endif /* chips */ 24466 24467 #if defined(BCM_56970_A0) 24468 { /* SOC_FORMAT_INT_ING_TRILL_RX_ACCESS_PORT_TRILL_PKTS_DISCARDED_COV_DEFS_BCM56970_A0fmt */ 24469 /* format ING_TRILL_RX_ACCESS_PORT_TRILL_PKTS_DISCARDED_COV_DEFSfmt */ 24470 /* nFields */ 6, 24471 /* *fields */ soc_ISC_HG_STATS_COV_DEFS_BCM53400_A0fmt_fields, 24472 /* bits */ 11, 24473 /* flags */ 0, 24474 }, 24475 #endif /* chips */ 24476 24477 #if defined(BCM_56640_A0) 24478 { /* SOC_FORMAT_INT_ING_TRILL_RX_NETWORK_PORT_NON_TRILL_PKTS_DISCARDED_COV_DEFSfmt */ 24479 /* format ING_TRILL_RX_NETWORK_PORT_NON_TRILL_PKTS_DISCARDED_COV_DEFSfmt */ 24480 /* nFields */ 6, 24481 /* *fields */ soc_ING_NIV_RX_FRAMES_ERROR_DROP_COV_DEFSfmt_fields, 24482 /* bits */ 13, 24483 /* flags */ 0, 24484 }, 24485 #endif /* chips */ 24486 24487 #if defined(BCM_56340_A0) 24488 { /* SOC_FORMAT_INT_ING_TRILL_RX_NETWORK_PORT_NON_TRILL_PKTS_DISCARDED_COV_DEFS_BCM56340_A0fmt */ 24489 /* format ING_TRILL_RX_NETWORK_PORT_NON_TRILL_PKTS_DISCARDED_COV_DEFSfmt */ 24490 /* nFields */ 6, 24491 /* *fields */ soc_ING_NIV_RX_FRAMES_ERROR_DROP_COV_DEFSfmt_fields, 24492 /* bits */ 13, 24493 /* flags */ 0, 24494 }, 24495 #endif /* chips */ 24496 24497 #if defined(BCM_56560_A0) 24498 { /* SOC_FORMAT_INT_ING_TRILL_RX_NETWORK_PORT_NON_TRILL_PKTS_DISCARDED_COV_DEFS_BCM56560_A0fmt */ 24499 /* format ING_TRILL_RX_NETWORK_PORT_NON_TRILL_PKTS_DISCARDED_COV_DEFSfmt */ 24500 /* nFields */ 6, 24501 /* *fields */ soc_ISC_IP_STATS_COV_DEFS_BCM56960_A0fmt_fields, 24502 /* bits */ 14, 24503 /* flags */ 0, 24504 }, 24505 #endif /* chips */ 24506 24507 #if defined(BCM_56560_B0) 24508 { /* SOC_FORMAT_INT_ING_TRILL_RX_NETWORK_PORT_NON_TRILL_PKTS_DISCARDED_COV_DEFS_BCM56560_B0fmt */ 24509 /* format ING_TRILL_RX_NETWORK_PORT_NON_TRILL_PKTS_DISCARDED_COV_DEFSfmt */ 24510 /* nFields */ 6, 24511 /* *fields */ soc_ISC_IP_STATS_COV_DEFS_BCM56960_A0fmt_fields, 24512 /* bits */ 14, 24513 /* flags */ 0, 24514 }, 24515 #endif /* chips */ 24516 24517 #if defined(BCM_56670_A0) 24518 { /* SOC_FORMAT_INT_ING_TRILL_RX_NETWORK_PORT_NON_TRILL_PKTS_DISCARDED_COV_DEFS_BCM56670_A0fmt */ 24519 /* format ING_TRILL_RX_NETWORK_PORT_NON_TRILL_PKTS_DISCARDED_COV_DEFSfmt */ 24520 /* nFields */ 6, 24521 /* *fields */ soc_ISC_IP_STATS_COV_DEFS_BCM56960_A0fmt_fields, 24522 /* bits */ 14, 24523 /* flags */ 0, 24524 }, 24525 #endif /* chips */ 24526 24527 #if defined(BCM_56670_B0) 24528 { /* SOC_FORMAT_INT_ING_TRILL_RX_NETWORK_PORT_NON_TRILL_PKTS_DISCARDED_COV_DEFS_BCM56670_B0fmt */ 24529 /* format ING_TRILL_RX_NETWORK_PORT_NON_TRILL_PKTS_DISCARDED_COV_DEFSfmt */ 24530 /* nFields */ 6, 24531 /* *fields */ soc_ISC_IP_STATS_COV_DEFS_BCM56960_A0fmt_fields, 24532 /* bits */ 14, 24533 /* flags */ 0, 24534 }, 24535 #endif /* chips */ 24536 24537 #if defined(BCM_56850_A0) 24538 { /* SOC_FORMAT_INT_ING_TRILL_RX_NETWORK_PORT_NON_TRILL_PKTS_DISCARDED_COV_DEFS_BCM56850_A0fmt */ 24539 /* format ING_TRILL_RX_NETWORK_PORT_NON_TRILL_PKTS_DISCARDED_COV_DEFSfmt */ 24540 /* nFields */ 6, 24541 /* *fields */ soc_ISC_IP_STATS_COV_DEFSfmt_fields, 24542 /* bits */ 14, 24543 /* flags */ 0, 24544 }, 24545 #endif /* chips */ 24546 24547 #if defined(BCM_56860_A0) 24548 { /* SOC_FORMAT_INT_ING_TRILL_RX_NETWORK_PORT_NON_TRILL_PKTS_DISCARDED_COV_DEFS_BCM56860_A0fmt */ 24549 /* format ING_TRILL_RX_NETWORK_PORT_NON_TRILL_PKTS_DISCARDED_COV_DEFSfmt */ 24550 /* nFields */ 6, 24551 /* *fields */ soc_ISC_IP_STATS_COV_DEFSfmt_fields, 24552 /* bits */ 14, 24553 /* flags */ 0, 24554 }, 24555 #endif /* chips */ 24556 24557 #if defined(BCM_56960_A0) 24558 { /* SOC_FORMAT_INT_ING_TRILL_RX_NETWORK_PORT_NON_TRILL_PKTS_DISCARDED_COV_DEFS_BCM56960_A0fmt */ 24559 /* format ING_TRILL_RX_NETWORK_PORT_NON_TRILL_PKTS_DISCARDED_COV_DEFSfmt */ 24560 /* nFields */ 6, 24561 /* *fields */ soc_ISC_HG_STATS_COV_DEFS_BCM53400_A0fmt_fields, 24562 /* bits */ 11, 24563 /* flags */ 0, 24564 }, 24565 #endif /* chips */ 24566 24567 #if defined(BCM_56965_A0) 24568 { /* SOC_FORMAT_INT_ING_TRILL_RX_NETWORK_PORT_NON_TRILL_PKTS_DISCARDED_COV_DEFS_BCM56965_A0fmt */ 24569 /* format ING_TRILL_RX_NETWORK_PORT_NON_TRILL_PKTS_DISCARDED_COV_DEFSfmt */ 24570 /* nFields */ 6, 24571 /* *fields */ soc_ISC_HG_STATS_COV_DEFS_BCM53400_A0fmt_fields, 24572 /* bits */ 11, 24573 /* flags */ 0, 24574 }, 24575 #endif /* chips */ 24576 24577 #if defined(BCM_56970_A0) 24578 { /* SOC_FORMAT_INT_ING_TRILL_RX_NETWORK_PORT_NON_TRILL_PKTS_DISCARDED_COV_DEFS_BCM56970_A0fmt */ 24579 /* format ING_TRILL_RX_NETWORK_PORT_NON_TRILL_PKTS_DISCARDED_COV_DEFSfmt */ 24580 /* nFields */ 6, 24581 /* *fields */ soc_ISC_HG_STATS_COV_DEFS_BCM53400_A0fmt_fields, 24582 /* bits */ 11, 24583 /* flags */ 0, 24584 }, 24585 #endif /* chips */ 24586 24587 #if defined(BCM_56640_A0) 24588 { /* SOC_FORMAT_INT_ING_TRILL_RX_PKTS_COV_DEFSfmt */ 24589 /* format ING_TRILL_RX_PKTS_COV_DEFSfmt */ 24590 /* nFields */ 6, 24591 /* *fields */ soc_ING_NIV_RX_FRAMES_ERROR_DROP_COV_DEFSfmt_fields, 24592 /* bits */ 13, 24593 /* flags */ 0, 24594 }, 24595 #endif /* chips */ 24596 24597 #if defined(BCM_56340_A0) 24598 { /* SOC_FORMAT_INT_ING_TRILL_RX_PKTS_COV_DEFS_BCM56340_A0fmt */ 24599 /* format ING_TRILL_RX_PKTS_COV_DEFSfmt */ 24600 /* nFields */ 6, 24601 /* *fields */ soc_ING_NIV_RX_FRAMES_ERROR_DROP_COV_DEFSfmt_fields, 24602 /* bits */ 13, 24603 /* flags */ 0, 24604 }, 24605 #endif /* chips */ 24606 24607 #if defined(BCM_56560_A0) 24608 { /* SOC_FORMAT_INT_ING_TRILL_RX_PKTS_COV_DEFS_BCM56560_A0fmt */ 24609 /* format ING_TRILL_RX_PKTS_COV_DEFSfmt */ 24610 /* nFields */ 6, 24611 /* *fields */ soc_ISC_IP_STATS_COV_DEFS_BCM56960_A0fmt_fields, 24612 /* bits */ 14, 24613 /* flags */ 0, 24614 }, 24615 #endif /* chips */ 24616 24617 #if defined(BCM_56560_B0) 24618 { /* SOC_FORMAT_INT_ING_TRILL_RX_PKTS_COV_DEFS_BCM56560_B0fmt */ 24619 /* format ING_TRILL_RX_PKTS_COV_DEFSfmt */ 24620 /* nFields */ 6, 24621 /* *fields */ soc_ISC_IP_STATS_COV_DEFS_BCM56960_A0fmt_fields, 24622 /* bits */ 14, 24623 /* flags */ 0, 24624 }, 24625 #endif /* chips */ 24626 24627 #if defined(BCM_56670_A0) 24628 { /* SOC_FORMAT_INT_ING_TRILL_RX_PKTS_COV_DEFS_BCM56670_A0fmt */ 24629 /* format ING_TRILL_RX_PKTS_COV_DEFSfmt */ 24630 /* nFields */ 6, 24631 /* *fields */ soc_ISC_IP_STATS_COV_DEFS_BCM56960_A0fmt_fields, 24632 /* bits */ 14, 24633 /* flags */ 0, 24634 }, 24635 #endif /* chips */ 24636 24637 #if defined(BCM_56670_B0) 24638 { /* SOC_FORMAT_INT_ING_TRILL_RX_PKTS_COV_DEFS_BCM56670_B0fmt */ 24639 /* format ING_TRILL_RX_PKTS_COV_DEFSfmt */ 24640 /* nFields */ 6, 24641 /* *fields */ soc_ISC_IP_STATS_COV_DEFS_BCM56960_A0fmt_fields, 24642 /* bits */ 14, 24643 /* flags */ 0, 24644 }, 24645 #endif /* chips */ 24646 24647 #if defined(BCM_56850_A0) 24648 { /* SOC_FORMAT_INT_ING_TRILL_RX_PKTS_COV_DEFS_BCM56850_A0fmt */ 24649 /* format ING_TRILL_RX_PKTS_COV_DEFSfmt */ 24650 /* nFields */ 6, 24651 /* *fields */ soc_ISC_IP_STATS_COV_DEFSfmt_fields, 24652 /* bits */ 14, 24653 /* flags */ 0, 24654 }, 24655 #endif /* chips */ 24656 24657 #if defined(BCM_56860_A0) 24658 { /* SOC_FORMAT_INT_ING_TRILL_RX_PKTS_COV_DEFS_BCM56860_A0fmt */ 24659 /* format ING_TRILL_RX_PKTS_COV_DEFSfmt */ 24660 /* nFields */ 6, 24661 /* *fields */ soc_ISC_IP_STATS_COV_DEFSfmt_fields, 24662 /* bits */ 14, 24663 /* flags */ 0, 24664 }, 24665 #endif /* chips */ 24666 24667 #if defined(BCM_56960_A0) 24668 { /* SOC_FORMAT_INT_ING_TRILL_RX_PKTS_COV_DEFS_BCM56960_A0fmt */ 24669 /* format ING_TRILL_RX_PKTS_COV_DEFSfmt */ 24670 /* nFields */ 6, 24671 /* *fields */ soc_ISC_HG_STATS_COV_DEFS_BCM53400_A0fmt_fields, 24672 /* bits */ 11, 24673 /* flags */ 0, 24674 }, 24675 #endif /* chips */ 24676 24677 #if defined(BCM_56965_A0) 24678 { /* SOC_FORMAT_INT_ING_TRILL_RX_PKTS_COV_DEFS_BCM56965_A0fmt */ 24679 /* format ING_TRILL_RX_PKTS_COV_DEFSfmt */ 24680 /* nFields */ 6, 24681 /* *fields */ soc_ISC_HG_STATS_COV_DEFS_BCM53400_A0fmt_fields, 24682 /* bits */ 11, 24683 /* flags */ 0, 24684 }, 24685 #endif /* chips */ 24686 24687 #if defined(BCM_56970_A0) 24688 { /* SOC_FORMAT_INT_ING_TRILL_RX_PKTS_COV_DEFS_BCM56970_A0fmt */ 24689 /* format ING_TRILL_RX_PKTS_COV_DEFSfmt */ 24690 /* nFields */ 6, 24691 /* *fields */ soc_ISC_HG_STATS_COV_DEFS_BCM53400_A0fmt_fields, 24692 /* bits */ 11, 24693 /* flags */ 0, 24694 }, 24695 #endif /* chips */ 24696 24697 #if defined(BCM_56870_A0) 24698 { /* SOC_FORMAT_INT_ING_TUNNEL_ADAPT_1_DOPfmt */ 24699 /* format ING_TUNNEL_ADAPT_1_DOPfmt */ 24700 /* nFields */ 10, 24701 /* *fields */ soc_ING_TUNNEL_ADAPT_1_DOPfmt_fields, 24702 /* bits */ 64, 24703 /* flags */ 0, 24704 }, 24705 #endif /* chips */ 24706 24707 #if defined(BCM_56370_A0) 24708 { /* SOC_FORMAT_INT_ING_TUNNEL_ADAPT_1_DOP_BCM56370_A0fmt */ 24709 /* format ING_TUNNEL_ADAPT_1_DOPfmt */ 24710 /* nFields */ 10, 24711 /* *fields */ soc_ING_TUNNEL_ADAPT_1_DOP_BCM56370_A0fmt_fields, 24712 /* bits */ 64, 24713 /* flags */ 0, 24714 }, 24715 #endif /* chips */ 24716 24717 #if defined(BCM_56770_A0) 24718 { /* SOC_FORMAT_INT_ING_TUNNEL_ADAPT_1_DOP_BCM56770_A0fmt */ 24719 /* format ING_TUNNEL_ADAPT_1_DOPfmt */ 24720 /* nFields */ 9, 24721 /* *fields */ soc_ING_TUNNEL_ADAPT_1_DOP_BCM56770_A0fmt_fields, 24722 /* bits */ 64, 24723 /* flags */ 0, 24724 }, 24725 #endif /* chips */ 24726 24727 #if defined(BCM_56770_A0) 24728 { /* SOC_FORMAT_INT_ING_TUNNEL_ADAPT_1_KEY_0_DOPfmt */ 24729 /* format ING_TUNNEL_ADAPT_1_KEY_0_DOPfmt */ 24730 /* nFields */ 4, 24731 /* *fields */ soc_ING_TUNNEL_ADAPT_1_KEY_0_DOPfmt_fields, 24732 /* bits */ 224, 24733 /* flags */ 0, 24734 }, 24735 #endif /* chips */ 24736 24737 #if defined(BCM_56870_A0) 24738 { /* SOC_FORMAT_INT_ING_TUNNEL_ADAPT_1_KEY_1_DOPfmt */ 24739 /* format ING_TUNNEL_ADAPT_1_KEY_1_DOPfmt */ 24740 /* nFields */ 3, 24741 /* *fields */ soc_ING_TUNNEL_ADAPT_1_KEY_1_DOPfmt_fields, 24742 /* bits */ 128, 24743 /* flags */ 0, 24744 }, 24745 #endif /* chips */ 24746 24747 #if defined(BCM_56370_A0) 24748 { /* SOC_FORMAT_INT_ING_TUNNEL_ADAPT_1_KEY_1_DOP_BCM56370_A0fmt */ 24749 /* format ING_TUNNEL_ADAPT_1_KEY_1_DOPfmt */ 24750 /* nFields */ 3, 24751 /* *fields */ soc_ING_TUNNEL_ADAPT_1_KEY_1_DOP_BCM56370_A0fmt_fields, 24752 /* bits */ 128, 24753 /* flags */ 0, 24754 }, 24755 #endif /* chips */ 24756 24757 #if defined(BCM_56770_A0) 24758 { /* SOC_FORMAT_INT_ING_TUNNEL_ADAPT_1_KEY_1_DOP_BCM56770_A0fmt */ 24759 /* format ING_TUNNEL_ADAPT_1_KEY_1_DOPfmt */ 24760 /* nFields */ 4, 24761 /* *fields */ soc_ING_TUNNEL_ADAPT_1_KEY_0_DOPfmt_fields, 24762 /* bits */ 224, 24763 /* flags */ 0, 24764 }, 24765 #endif /* chips */ 24766 24767 #if defined(BCM_56870_A0) 24768 { /* SOC_FORMAT_INT_ING_TUNNEL_ADAPT_2_DOPfmt */ 24769 /* format ING_TUNNEL_ADAPT_2_DOPfmt */ 24770 /* nFields */ 10, 24771 /* *fields */ soc_ING_TUNNEL_ADAPT_1_DOPfmt_fields, 24772 /* bits */ 64, 24773 /* flags */ 0, 24774 }, 24775 #endif /* chips */ 24776 24777 #if defined(BCM_56370_A0) 24778 { /* SOC_FORMAT_INT_ING_TUNNEL_ADAPT_2_DOP_BCM56370_A0fmt */ 24779 /* format ING_TUNNEL_ADAPT_2_DOPfmt */ 24780 /* nFields */ 10, 24781 /* *fields */ soc_ING_TUNNEL_ADAPT_1_DOP_BCM56370_A0fmt_fields, 24782 /* bits */ 64, 24783 /* flags */ 0, 24784 }, 24785 #endif /* chips */ 24786 24787 #if defined(BCM_56770_A0) 24788 { /* SOC_FORMAT_INT_ING_TUNNEL_ADAPT_2_DOP_BCM56770_A0fmt */ 24789 /* format ING_TUNNEL_ADAPT_2_DOPfmt */ 24790 /* nFields */ 9, 24791 /* *fields */ soc_ING_TUNNEL_ADAPT_1_DOP_BCM56770_A0fmt_fields, 24792 /* bits */ 64, 24793 /* flags */ 0, 24794 }, 24795 #endif /* chips */ 24796 24797 #if defined(BCM_56770_A0) 24798 { /* SOC_FORMAT_INT_ING_TUNNEL_ADAPT_2_KEY_0_DOPfmt */ 24799 /* format ING_TUNNEL_ADAPT_2_KEY_0_DOPfmt */ 24800 /* nFields */ 4, 24801 /* *fields */ soc_ING_TUNNEL_ADAPT_1_KEY_0_DOPfmt_fields, 24802 /* bits */ 224, 24803 /* flags */ 0, 24804 }, 24805 #endif /* chips */ 24806 24807 #if defined(BCM_56870_A0) 24808 { /* SOC_FORMAT_INT_ING_TUNNEL_ADAPT_2_KEY_1_DOPfmt */ 24809 /* format ING_TUNNEL_ADAPT_2_KEY_1_DOPfmt */ 24810 /* nFields */ 3, 24811 /* *fields */ soc_ING_TUNNEL_ADAPT_2_KEY_1_DOPfmt_fields, 24812 /* bits */ 128, 24813 /* flags */ 0, 24814 }, 24815 #endif /* chips */ 24816 24817 #if defined(BCM_56370_A0) 24818 { /* SOC_FORMAT_INT_ING_TUNNEL_ADAPT_2_KEY_1_DOP_BCM56370_A0fmt */ 24819 /* format ING_TUNNEL_ADAPT_2_KEY_1_DOPfmt */ 24820 /* nFields */ 3, 24821 /* *fields */ soc_ING_TUNNEL_ADAPT_2_KEY_1_DOP_BCM56370_A0fmt_fields, 24822 /* bits */ 128, 24823 /* flags */ 0, 24824 }, 24825 #endif /* chips */ 24826 24827 #if defined(BCM_56770_A0) 24828 { /* SOC_FORMAT_INT_ING_TUNNEL_ADAPT_2_KEY_1_DOP_BCM56770_A0fmt */ 24829 /* format ING_TUNNEL_ADAPT_2_KEY_1_DOPfmt */ 24830 /* nFields */ 4, 24831 /* *fields */ soc_ING_TUNNEL_ADAPT_1_KEY_0_DOPfmt_fields, 24832 /* bits */ 224, 24833 /* flags */ 0, 24834 }, 24835 #endif /* chips */ 24836 24837 #if defined(BCM_56870_A0) 24838 { /* SOC_FORMAT_INT_ING_TUNNEL_ADAPT_3_LKUP_DOPfmt */ 24839 /* format ING_TUNNEL_ADAPT_3_LKUP_DOPfmt */ 24840 /* nFields */ 6, 24841 /* *fields */ soc_ING_TUNNEL_ADAPT_3_LKUP_DOPfmt_fields, 24842 /* bits */ 32, 24843 /* flags */ 0, 24844 }, 24845 #endif /* chips */ 24846 24847 #if defined(BCM_56370_A0) 24848 { /* SOC_FORMAT_INT_ING_TUNNEL_ADAPT_3_LKUP_DOP_BCM56370_A0fmt */ 24849 /* format ING_TUNNEL_ADAPT_3_LKUP_DOPfmt */ 24850 /* nFields */ 6, 24851 /* *fields */ soc_ING_TUNNEL_ADAPT_3_LKUP_DOP_BCM56370_A0fmt_fields, 24852 /* bits */ 32, 24853 /* flags */ 0, 24854 }, 24855 #endif /* chips */ 24856 24857 #if defined(BCM_56770_A0) 24858 { /* SOC_FORMAT_INT_ING_TUNNEL_ADAPT_3_LKUP_DOP_BCM56770_A0fmt */ 24859 /* format ING_TUNNEL_ADAPT_3_LKUP_DOPfmt */ 24860 /* nFields */ 5, 24861 /* *fields */ soc_ING_TUNNEL_ADAPT_3_LKUP_DOP_BCM56770_A0fmt_fields, 24862 /* bits */ 32, 24863 /* flags */ 0, 24864 }, 24865 #endif /* chips */ 24866 24867 #if defined(BCM_56870_A0) 24868 { /* SOC_FORMAT_INT_ING_TUNNEL_ADAPT_4_DOPfmt */ 24869 /* format ING_TUNNEL_ADAPT_4_DOPfmt */ 24870 /* nFields */ 10, 24871 /* *fields */ soc_ING_TUNNEL_ADAPT_1_DOPfmt_fields, 24872 /* bits */ 64, 24873 /* flags */ 0, 24874 }, 24875 #endif /* chips */ 24876 24877 #if defined(BCM_56370_A0) 24878 { /* SOC_FORMAT_INT_ING_TUNNEL_ADAPT_4_DOP_BCM56370_A0fmt */ 24879 /* format ING_TUNNEL_ADAPT_4_DOPfmt */ 24880 /* nFields */ 10, 24881 /* *fields */ soc_ING_TUNNEL_ADAPT_1_DOP_BCM56370_A0fmt_fields, 24882 /* bits */ 64, 24883 /* flags */ 0, 24884 }, 24885 #endif /* chips */ 24886 24887 #if defined(BCM_56770_A0) 24888 { /* SOC_FORMAT_INT_ING_TUNNEL_ADAPT_4_DOP_BCM56770_A0fmt */ 24889 /* format ING_TUNNEL_ADAPT_4_DOPfmt */ 24890 /* nFields */ 9, 24891 /* *fields */ soc_ING_TUNNEL_ADAPT_4_DOPfmt_fields, 24892 /* bits */ 64, 24893 /* flags */ 0, 24894 }, 24895 #endif /* chips */ 24896 24897 #if defined(BCM_56770_A0) 24898 { /* SOC_FORMAT_INT_ING_TUNNEL_ADAPT_4_KEY_0_DOPfmt */ 24899 /* format ING_TUNNEL_ADAPT_4_KEY_0_DOPfmt */ 24900 /* nFields */ 4, 24901 /* *fields */ soc_ING_TUNNEL_ADAPT_1_KEY_0_DOPfmt_fields, 24902 /* bits */ 224, 24903 /* flags */ 0, 24904 }, 24905 #endif /* chips */ 24906 24907 #if defined(BCM_56870_A0) 24908 { /* SOC_FORMAT_INT_ING_TUNNEL_ADAPT_4_KEY_1_DOPfmt */ 24909 /* format ING_TUNNEL_ADAPT_4_KEY_1_DOPfmt */ 24910 /* nFields */ 3, 24911 /* *fields */ soc_ING_TUNNEL_ADAPT_4_KEY_1_DOPfmt_fields, 24912 /* bits */ 128, 24913 /* flags */ 0, 24914 }, 24915 #endif /* chips */ 24916 24917 #if defined(BCM_56370_A0) 24918 { /* SOC_FORMAT_INT_ING_TUNNEL_ADAPT_4_KEY_1_DOP_BCM56370_A0fmt */ 24919 /* format ING_TUNNEL_ADAPT_4_KEY_1_DOPfmt */ 24920 /* nFields */ 3, 24921 /* *fields */ soc_ING_TUNNEL_ADAPT_4_KEY_1_DOP_BCM56370_A0fmt_fields, 24922 /* bits */ 128, 24923 /* flags */ 0, 24924 }, 24925 #endif /* chips */ 24926 24927 #if defined(BCM_56770_A0) 24928 { /* SOC_FORMAT_INT_ING_TUNNEL_ADAPT_4_KEY_1_DOP_BCM56770_A0fmt */ 24929 /* format ING_TUNNEL_ADAPT_4_KEY_1_DOPfmt */ 24930 /* nFields */ 4, 24931 /* *fields */ soc_ING_TUNNEL_ADAPT_1_KEY_0_DOPfmt_fields, 24932 /* bits */ 224, 24933 /* flags */ 0, 24934 }, 24935 #endif /* chips */ 24936 24937 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 24938 defined(BCM_56870_A0) 24939 { /* SOC_FORMAT_INT_ING_TUNNEL_ECN_DECAP_INDEXfmt */ 24940 /* format ING_TUNNEL_ECN_DECAP_INDEXfmt */ 24941 /* nFields */ 4, 24942 /* *fields */ soc_ING_TUNNEL_ECN_DECAP_INDEXfmt_fields, 24943 /* bits */ 8, 24944 /* flags */ 0, 24945 }, 24946 #endif /* chips */ 24947 24948 #if defined(BCM_56370_A0) 24949 { /* SOC_FORMAT_INT_INLINE_FF_KEYfmt */ 24950 /* format INLINE_FF_KEYfmt */ 24951 /* nFields */ 11, 24952 /* *fields */ soc_INLINE_FF_KEYfmt_fields, 24953 /* bits */ 387, 24954 /* flags */ 0, 24955 }, 24956 #endif /* chips */ 24957 24958 #if defined(BCM_56370_A0) 24959 { /* SOC_FORMAT_INT_INLINE_FF_KEY_INDEXfmt */ 24960 /* format INLINE_FF_KEY_INDEXfmt */ 24961 /* nFields */ 10, 24962 /* *fields */ soc_INLINE_FF_KEY_INDEXfmt_fields, 24963 /* bits */ 20, 24964 /* flags */ 0, 24965 }, 24966 #endif /* chips */ 24967 24968 #if defined(BCM_56370_A0) 24969 { /* SOC_FORMAT_INT_INLINE_LEARN_CONTEXT_BUFFERfmt */ 24970 /* format INLINE_LEARN_CONTEXT_BUFFERfmt */ 24971 /* nFields */ 8, 24972 /* *fields */ soc_INLINE_LEARN_CONTEXT_BUFFERfmt_fields, 24973 /* bits */ 398, 24974 /* flags */ 0, 24975 }, 24976 #endif /* chips */ 24977 24978 #if defined(BCM_56370_A0) 24979 { /* SOC_FORMAT_INT_INLINE_LEARN_CONTEXT_BUFFER_WO_KEYfmt */ 24980 /* format INLINE_LEARN_CONTEXT_BUFFER_WO_KEYfmt */ 24981 /* nFields */ 7, 24982 /* *fields */ soc_INLINE_LEARN_CONTEXT_BUFFER_WO_KEYfmt_fields, 24983 /* bits */ 22, 24984 /* flags */ 0, 24985 }, 24986 #endif /* chips */ 24987 24988 #if defined(BCM_56370_A0) 24989 { /* SOC_FORMAT_INT_INLINE_LEARN_SW_INSTRUTIONfmt */ 24990 /* format INLINE_LEARN_SW_INSTRUTIONfmt */ 24991 /* nFields */ 1, 24992 /* *fields */ soc_INLINE_LEARN_SW_INSTRUTIONfmt_fields, 24993 /* bits */ 2, 24994 /* flags */ 0, 24995 }, 24996 #endif /* chips */ 24997 24998 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 24999 { /* SOC_FORMAT_INT_INSTR_BUFFER_IADAPT_DW0fmt */ 25000 /* format INSTR_BUFFER_IADAPT_DW0fmt */ 25001 /* nFields */ 3, 25002 /* *fields */ soc_INSTR_BUFFER_IADAPT_DW0fmt_fields, 25003 /* bits */ 14, 25004 /* flags */ 0, 25005 }, 25006 #endif /* chips */ 25007 25008 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 25009 { /* SOC_FORMAT_INT_INSTR_BUFFER_IFWD_DW0fmt */ 25010 /* format INSTR_BUFFER_IFWD_DW0fmt */ 25011 /* nFields */ 7, 25012 /* *fields */ soc_INSTR_BUFFER_IFWD_DW0fmt_fields, 25013 /* bits */ 34, 25014 /* flags */ 0, 25015 }, 25016 #endif /* chips */ 25017 25018 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 25019 { /* SOC_FORMAT_INT_INSTR_BUFFER_IFWD_DW1fmt */ 25020 /* format INSTR_BUFFER_IFWD_DW1fmt */ 25021 /* nFields */ 6, 25022 /* *fields */ soc_INSTR_BUFFER_IFWD_DW1fmt_fields, 25023 /* bits */ 34, 25024 /* flags */ 0, 25025 }, 25026 #endif /* chips */ 25027 25028 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 25029 { /* SOC_FORMAT_INT_INSTR_BUFFER_IFWD_DW2fmt */ 25030 /* format INSTR_BUFFER_IFWD_DW2fmt */ 25031 /* nFields */ 6, 25032 /* *fields */ soc_INSTR_BUFFER_IFWD_DW2fmt_fields, 25033 /* bits */ 31, 25034 /* flags */ 0, 25035 }, 25036 #endif /* chips */ 25037 25038 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 25039 { /* SOC_FORMAT_INT_INSTR_BUFFER_IFWD_DW3fmt */ 25040 /* format INSTR_BUFFER_IFWD_DW3fmt */ 25041 /* nFields */ 4, 25042 /* *fields */ soc_INSTR_BUFFER_IFWD_DW3fmt_fields, 25043 /* bits */ 58, 25044 /* flags */ 0, 25045 }, 25046 #endif /* chips */ 25047 25048 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 25049 { /* SOC_FORMAT_INT_INSTR_BUFFER_IPARS_DW0fmt */ 25050 /* format INSTR_BUFFER_IPARS_DW0fmt */ 25051 /* nFields */ 9, 25052 /* *fields */ soc_INSTR_BUFFER_IPARS_DW0fmt_fields, 25053 /* bits */ 51, 25054 /* flags */ 0, 25055 }, 25056 #endif /* chips */ 25057 25058 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) 25059 { /* SOC_FORMAT_INT_INSTR_BUFFER_ISW1_DW0fmt */ 25060 /* format INSTR_BUFFER_ISW1_DW0fmt */ 25061 /* nFields */ 7, 25062 /* *fields */ soc_INSTR_BUFFER_ISW1_DW0fmt_fields, 25063 /* bits */ 64, 25064 /* flags */ 0, 25065 }, 25066 #endif /* chips */ 25067 25068 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) 25069 { /* SOC_FORMAT_INT_INSTR_BUFFER_ISW1_DW1fmt */ 25070 /* format INSTR_BUFFER_ISW1_DW1fmt */ 25071 /* nFields */ 10, 25072 /* *fields */ soc_INSTR_BUFFER_ISW1_DW1fmt_fields, 25073 /* bits */ 64, 25074 /* flags */ 0, 25075 }, 25076 #endif /* chips */ 25077 25078 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) 25079 { /* SOC_FORMAT_INT_INSTR_BUFFER_ISW1_DW2fmt */ 25080 /* format INSTR_BUFFER_ISW1_DW2fmt */ 25081 /* nFields */ 15, 25082 /* *fields */ soc_INSTR_BUFFER_ISW1_DW2fmt_fields, 25083 /* bits */ 64, 25084 /* flags */ 0, 25085 }, 25086 #endif /* chips */ 25087 25088 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) || \ 25089 defined(BCM_56970_A0) 25090 { /* SOC_FORMAT_INT_INSTR_BUFFER_ISW1_DW3fmt */ 25091 /* format INSTR_BUFFER_ISW1_DW3fmt */ 25092 /* nFields */ 5, 25093 /* *fields */ soc_INSTR_BUFFER_ISW1_DW3fmt_fields, 25094 /* bits */ 64, 25095 /* flags */ 0, 25096 }, 25097 #endif /* chips */ 25098 25099 #if defined(BCM_56970_A0) 25100 { /* SOC_FORMAT_INT_INSTR_BUFFER_ISW1_DW0_BCM56970_A0fmt */ 25101 /* format INSTR_BUFFER_ISW1_DW0fmt */ 25102 /* nFields */ 8, 25103 /* *fields */ soc_INSTR_BUFFER_ISW1_DW0_BCM56970_A0fmt_fields, 25104 /* bits */ 64, 25105 /* flags */ 0, 25106 }, 25107 #endif /* chips */ 25108 25109 #if defined(BCM_56970_A0) 25110 { /* SOC_FORMAT_INT_INSTR_BUFFER_ISW1_DW1_BCM56970_A0fmt */ 25111 /* format INSTR_BUFFER_ISW1_DW1fmt */ 25112 /* nFields */ 9, 25113 /* *fields */ soc_INSTR_BUFFER_ISW1_DW1_BCM56970_A0fmt_fields, 25114 /* bits */ 64, 25115 /* flags */ 0, 25116 }, 25117 #endif /* chips */ 25118 25119 #if defined(BCM_56970_A0) 25120 { /* SOC_FORMAT_INT_INSTR_BUFFER_ISW1_DW2_BCM56970_A0fmt */ 25121 /* format INSTR_BUFFER_ISW1_DW2fmt */ 25122 /* nFields */ 15, 25123 /* *fields */ soc_INSTR_BUFFER_ISW1_DW2_BCM56970_A0fmt_fields, 25124 /* bits */ 64, 25125 /* flags */ 0, 25126 }, 25127 #endif /* chips */ 25128 25129 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) 25130 { /* SOC_FORMAT_INT_INSTR_BUFFER_ISW2_DW0fmt */ 25131 /* format INSTR_BUFFER_ISW2_DW0fmt */ 25132 /* nFields */ 6, 25133 /* *fields */ soc_INSTR_BUFFER_ISW2_DW0fmt_fields, 25134 /* bits */ 64, 25135 /* flags */ 0, 25136 }, 25137 #endif /* chips */ 25138 25139 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) 25140 { /* SOC_FORMAT_INT_INSTR_BUFFER_ISW2_DW1fmt */ 25141 /* format INSTR_BUFFER_ISW2_DW1fmt */ 25142 /* nFields */ 8, 25143 /* *fields */ soc_INSTR_BUFFER_ISW2_DW1fmt_fields, 25144 /* bits */ 64, 25145 /* flags */ 0, 25146 }, 25147 #endif /* chips */ 25148 25149 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) || \ 25150 defined(BCM_56970_A0) 25151 { /* SOC_FORMAT_INT_INSTR_BUFFER_ISW2_DW2fmt */ 25152 /* format INSTR_BUFFER_ISW2_DW2fmt */ 25153 /* nFields */ 8, 25154 /* *fields */ soc_INSTR_BUFFER_ISW2_DW2fmt_fields, 25155 /* bits */ 64, 25156 /* flags */ 0, 25157 }, 25158 #endif /* chips */ 25159 25160 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) || \ 25161 defined(BCM_56970_A0) 25162 { /* SOC_FORMAT_INT_INSTR_BUFFER_ISW2_DW3fmt */ 25163 /* format INSTR_BUFFER_ISW2_DW3fmt */ 25164 /* nFields */ 7, 25165 /* *fields */ soc_INSTR_BUFFER_ISW2_DW3fmt_fields, 25166 /* bits */ 64, 25167 /* flags */ 0, 25168 }, 25169 #endif /* chips */ 25170 25171 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) || \ 25172 defined(BCM_56970_A0) 25173 { /* SOC_FORMAT_INT_INSTR_BUFFER_ISW2_DW4fmt */ 25174 /* format INSTR_BUFFER_ISW2_DW4fmt */ 25175 /* nFields */ 7, 25176 /* *fields */ soc_INSTR_BUFFER_ISW2_DW4fmt_fields, 25177 /* bits */ 64, 25178 /* flags */ 0, 25179 }, 25180 #endif /* chips */ 25181 25182 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) || \ 25183 defined(BCM_56970_A0) 25184 { /* SOC_FORMAT_INT_INSTR_BUFFER_ISW2_DW5fmt */ 25185 /* format INSTR_BUFFER_ISW2_DW5fmt */ 25186 /* nFields */ 10, 25187 /* *fields */ soc_INSTR_BUFFER_ISW2_DW5fmt_fields, 25188 /* bits */ 64, 25189 /* flags */ 0, 25190 }, 25191 #endif /* chips */ 25192 25193 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) || \ 25194 defined(BCM_56970_A0) 25195 { /* SOC_FORMAT_INT_INSTR_BUFFER_ISW2_DW6fmt */ 25196 /* format INSTR_BUFFER_ISW2_DW6fmt */ 25197 /* nFields */ 1, 25198 /* *fields */ soc_INSTR_BUFFER_ISW2_DW6fmt_fields, 25199 /* bits */ 64, 25200 /* flags */ 0, 25201 }, 25202 #endif /* chips */ 25203 25204 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) || \ 25205 defined(BCM_56970_A0) 25206 { /* SOC_FORMAT_INT_INSTR_BUFFER_ISW2_DW7fmt */ 25207 /* format INSTR_BUFFER_ISW2_DW7fmt */ 25208 /* nFields */ 1, 25209 /* *fields */ soc_INSTR_BUFFER_ISW2_DW7fmt_fields, 25210 /* bits */ 64, 25211 /* flags */ 0, 25212 }, 25213 #endif /* chips */ 25214 25215 #if defined(BCM_56970_A0) 25216 { /* SOC_FORMAT_INT_INSTR_BUFFER_ISW2_DW0_BCM56970_A0fmt */ 25217 /* format INSTR_BUFFER_ISW2_DW0fmt */ 25218 /* nFields */ 8, 25219 /* *fields */ soc_INSTR_BUFFER_ISW2_DW0_BCM56970_A0fmt_fields, 25220 /* bits */ 64, 25221 /* flags */ 0, 25222 }, 25223 #endif /* chips */ 25224 25225 #if defined(BCM_56970_A0) 25226 { /* SOC_FORMAT_INT_INSTR_BUFFER_ISW2_DW1_BCM56970_A0fmt */ 25227 /* format INSTR_BUFFER_ISW2_DW1fmt */ 25228 /* nFields */ 8, 25229 /* *fields */ soc_INSTR_BUFFER_ISW2_DW1_BCM56970_A0fmt_fields, 25230 /* bits */ 64, 25231 /* flags */ 0, 25232 }, 25233 #endif /* chips */ 25234 25235 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 25236 { /* SOC_FORMAT_INT_INSTR_BUFFER_ISW_DW0fmt */ 25237 /* format INSTR_BUFFER_ISW_DW0fmt */ 25238 /* nFields */ 5, 25239 /* *fields */ soc_INSTR_BUFFER_ISW_DW0fmt_fields, 25240 /* bits */ 49, 25241 /* flags */ 0, 25242 }, 25243 #endif /* chips */ 25244 25245 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 25246 { /* SOC_FORMAT_INT_INSTR_BUFFER_ISW_DW1fmt */ 25247 /* format INSTR_BUFFER_ISW_DW1fmt */ 25248 /* nFields */ 6, 25249 /* *fields */ soc_INSTR_BUFFER_ISW_DW1fmt_fields, 25250 /* bits */ 54, 25251 /* flags */ 0, 25252 }, 25253 #endif /* chips */ 25254 25255 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 25256 { /* SOC_FORMAT_INT_INSTR_BUFFER_ISW_DW2fmt */ 25257 /* format INSTR_BUFFER_ISW_DW2fmt */ 25258 /* nFields */ 6, 25259 /* *fields */ soc_INSTR_BUFFER_ISW_DW2fmt_fields, 25260 /* bits */ 53, 25261 /* flags */ 0, 25262 }, 25263 #endif /* chips */ 25264 25265 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 25266 { /* SOC_FORMAT_INT_INSTR_BUFFER_ISW_DW3fmt */ 25267 /* format INSTR_BUFFER_ISW_DW3fmt */ 25268 /* nFields */ 6, 25269 /* *fields */ soc_INSTR_BUFFER_ISW_DW3fmt_fields, 25270 /* bits */ 51, 25271 /* flags */ 0, 25272 }, 25273 #endif /* chips */ 25274 25275 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 25276 { /* SOC_FORMAT_INT_INSTR_BUFFER_ISW_DW4fmt */ 25277 /* format INSTR_BUFFER_ISW_DW4fmt */ 25278 /* nFields */ 8, 25279 /* *fields */ soc_INSTR_BUFFER_ISW_DW4fmt_fields, 25280 /* bits */ 35, 25281 /* flags */ 0, 25282 }, 25283 #endif /* chips */ 25284 25285 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 25286 { /* SOC_FORMAT_INT_INSTR_BUFFER_ISW_DW5fmt */ 25287 /* format INSTR_BUFFER_ISW_DW5fmt */ 25288 /* nFields */ 1, 25289 /* *fields */ soc_INSTR_BUFFER_ISW_DW5fmt_fields, 25290 /* bits */ 64, 25291 /* flags */ 0, 25292 }, 25293 #endif /* chips */ 25294 25295 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 25296 { /* SOC_FORMAT_INT_INSTR_BUFFER_ISW_DW6fmt */ 25297 /* format INSTR_BUFFER_ISW_DW6fmt */ 25298 /* nFields */ 1, 25299 /* *fields */ soc_INSTR_BUFFER_ISW_DW6fmt_fields, 25300 /* bits */ 32, 25301 /* flags */ 0, 25302 }, 25303 #endif /* chips */ 25304 25305 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) 25306 { /* SOC_FORMAT_INT_INSTR_BUFFER_IVP_DW0fmt */ 25307 /* format INSTR_BUFFER_IVP_DW0fmt */ 25308 /* nFields */ 11, 25309 /* *fields */ soc_INSTR_BUFFER_IVP_DW0fmt_fields, 25310 /* bits */ 64, 25311 /* flags */ 0, 25312 }, 25313 #endif /* chips */ 25314 25315 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) 25316 { /* SOC_FORMAT_INT_INSTR_BUFFER_IVP_DW1fmt */ 25317 /* format INSTR_BUFFER_IVP_DW1fmt */ 25318 /* nFields */ 6, 25319 /* *fields */ soc_INSTR_BUFFER_IVP_DW1fmt_fields, 25320 /* bits */ 64, 25321 /* flags */ 0, 25322 }, 25323 #endif /* chips */ 25324 25325 #if defined(BCM_56970_A0) 25326 { /* SOC_FORMAT_INT_INSTR_BUFFER_IVP_DW0_BCM56970_A0fmt */ 25327 /* format INSTR_BUFFER_IVP_DW0fmt */ 25328 /* nFields */ 13, 25329 /* *fields */ soc_INSTR_BUFFER_IVP_DW0_BCM56970_A0fmt_fields, 25330 /* bits */ 64, 25331 /* flags */ 0, 25332 }, 25333 #endif /* chips */ 25334 25335 #if defined(BCM_56970_A0) 25336 { /* SOC_FORMAT_INT_INSTR_BUFFER_IVP_DW1_BCM56970_A0fmt */ 25337 /* format INSTR_BUFFER_IVP_DW1fmt */ 25338 /* nFields */ 5, 25339 /* *fields */ soc_INSTR_BUFFER_IVP_DW1_BCM56970_A0fmt_fields, 25340 /* bits */ 64, 25341 /* flags */ 0, 25342 }, 25343 #endif /* chips */ 25344 25345 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) 25346 { /* SOC_FORMAT_INT_INTFI_E2ECC_PKTfmt */ 25347 /* format INTFI_E2ECC_PKTfmt */ 25348 /* nFields */ 3, 25349 /* *fields */ soc_INTFI_E2ECC_PKTfmt_fields, 25350 /* bits */ 528, 25351 /* flags */ 0, 25352 }, 25353 #endif /* chips */ 25354 25355 #if defined(BCM_56440_A0) 25356 { /* SOC_FORMAT_INT_INTFI_OOB_HCFC_PKTfmt */ 25357 /* format INTFI_OOB_HCFC_PKTfmt */ 25358 /* nFields */ 6, 25359 /* *fields */ soc_INTFI_OOB_HCFC_PKTfmt_fields, 25360 /* bits */ 120, 25361 /* flags */ 0, 25362 }, 25363 #endif /* chips */ 25364 25365 #if defined(BCM_56440_B0) 25366 { /* SOC_FORMAT_INT_INTFI_OOB_HCFC_PKT_BCM56440_B0fmt */ 25367 /* format INTFI_OOB_HCFC_PKTfmt */ 25368 /* nFields */ 6, 25369 /* *fields */ soc_INTFI_OOB_HCFC_PKTfmt_fields, 25370 /* bits */ 120, 25371 /* flags */ 0, 25372 }, 25373 #endif /* chips */ 25374 25375 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \ 25376 defined(BCM_56840_A0) || defined(BCM_56840_B0) 25377 { /* SOC_FORMAT_INT_INTFI_TO_ES_S1fmt */ 25378 /* format INTFI_TO_ES_S1fmt */ 25379 /* nFields */ 3, 25380 /* *fields */ soc_INTFI_TO_ES_S1fmt_fields, 25381 /* bits */ 3, 25382 /* flags */ 0, 25383 }, 25384 #endif /* chips */ 25385 25386 #if defined(BCM_56440_A0) 25387 { /* SOC_FORMAT_INT_INTFI_TO_LLS_INFOfmt */ 25388 /* format INTFI_TO_LLS_INFOfmt */ 25389 /* nFields */ 5, 25390 /* *fields */ soc_INTFI_TO_LLS_INFOfmt_fields, 25391 /* bits */ 84, 25392 /* flags */ 0, 25393 }, 25394 #endif /* chips */ 25395 25396 #if defined(BCM_56260_A0) 25397 { /* SOC_FORMAT_INT_INTFI_TO_LLS_INFO_BCM56260_A0fmt */ 25398 /* format INTFI_TO_LLS_INFOfmt */ 25399 /* nFields */ 5, 25400 /* *fields */ soc_INTFI_TO_LLS_INFO_BCM56260_A0fmt_fields, 25401 /* bits */ 84, 25402 /* flags */ 0, 25403 }, 25404 #endif /* chips */ 25405 25406 #if defined(BCM_56260_B0) 25407 { /* SOC_FORMAT_INT_INTFI_TO_LLS_INFO_BCM56260_B0fmt */ 25408 /* format INTFI_TO_LLS_INFOfmt */ 25409 /* nFields */ 5, 25410 /* *fields */ soc_INTFI_TO_LLS_INFO_BCM56260_A0fmt_fields, 25411 /* bits */ 84, 25412 /* flags */ 0, 25413 }, 25414 #endif /* chips */ 25415 25416 #if defined(BCM_56270_A0) 25417 { /* SOC_FORMAT_INT_INTFI_TO_LLS_INFO_BCM56270_A0fmt */ 25418 /* format INTFI_TO_LLS_INFOfmt */ 25419 /* nFields */ 5, 25420 /* *fields */ soc_INTFI_TO_LLS_INFO_BCM56260_A0fmt_fields, 25421 /* bits */ 84, 25422 /* flags */ 0, 25423 }, 25424 #endif /* chips */ 25425 25426 #if defined(BCM_56440_B0) 25427 { /* SOC_FORMAT_INT_INTFI_TO_LLS_INFO_BCM56440_B0fmt */ 25428 /* format INTFI_TO_LLS_INFOfmt */ 25429 /* nFields */ 5, 25430 /* *fields */ soc_INTFI_TO_LLS_INFOfmt_fields, 25431 /* bits */ 84, 25432 /* flags */ 0, 25433 }, 25434 #endif /* chips */ 25435 25436 #if defined(BCM_56450_A0) 25437 { /* SOC_FORMAT_INT_INTFI_TO_LLS_INFO_BCM56450_A0fmt */ 25438 /* format INTFI_TO_LLS_INFOfmt */ 25439 /* nFields */ 5, 25440 /* *fields */ soc_INTFI_TO_LLS_INFO_BCM56450_A0fmt_fields, 25441 /* bits */ 84, 25442 /* flags */ 0, 25443 }, 25444 #endif /* chips */ 25445 25446 #if defined(BCM_56450_B0) 25447 { /* SOC_FORMAT_INT_INTFI_TO_LLS_INFO_BCM56450_B0fmt */ 25448 /* format INTFI_TO_LLS_INFOfmt */ 25449 /* nFields */ 5, 25450 /* *fields */ soc_INTFI_TO_LLS_INFO_BCM56450_A0fmt_fields, 25451 /* bits */ 84, 25452 /* flags */ 0, 25453 }, 25454 #endif /* chips */ 25455 25456 #if defined(BCM_56450_B1) 25457 { /* SOC_FORMAT_INT_INTFI_TO_LLS_INFO_BCM56450_B1fmt */ 25458 /* format INTFI_TO_LLS_INFOfmt */ 25459 /* nFields */ 5, 25460 /* *fields */ soc_INTFI_TO_LLS_INFO_BCM56450_A0fmt_fields, 25461 /* bits */ 84, 25462 /* flags */ 0, 25463 }, 25464 #endif /* chips */ 25465 25466 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \ 25467 defined(BCM_56960_A0) || defined(BCM_56965_A0) || \ 25468 defined(BCM_56970_A0) 25469 { /* SOC_FORMAT_INT_INTFI_TO_VBSfmt */ 25470 /* format INTFI_TO_VBSfmt */ 25471 /* nFields */ 6, 25472 /* *fields */ soc_INTFI_TO_VBSfmt_fields, 25473 /* bits */ 20, 25474 /* flags */ 0, 25475 }, 25476 #endif /* chips */ 25477 25478 #if defined(BCM_56370_A0) 25479 { /* SOC_FORMAT_INT_INTFI_TO_VBS_BCM56370_A0fmt */ 25480 /* format INTFI_TO_VBSfmt */ 25481 /* nFields */ 10, 25482 /* *fields */ soc_INTFI_TO_VBS_BCM56370_A0fmt_fields, 25483 /* bits */ 52, 25484 /* flags */ 0, 25485 }, 25486 #endif /* chips */ 25487 25488 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) 25489 { /* SOC_FORMAT_INT_INTF_ACTION_SETfmt */ 25490 /* format INTF_ACTION_SETfmt */ 25491 /* nFields */ 2, 25492 /* *fields */ soc_INTF_ACTION_SETfmt_fields, 25493 /* bits */ 15, 25494 /* flags */ 0, 25495 }, 25496 #endif /* chips */ 25497 25498 #if defined(BCM_56370_A0) 25499 { /* SOC_FORMAT_INT_INTF_ACTION_SET_BCM56370_A0fmt */ 25500 /* format INTF_ACTION_SETfmt */ 25501 /* nFields */ 2, 25502 /* *fields */ soc_INTF_ACTION_SET_BCM56370_A0fmt_fields, 25503 /* bits */ 14, 25504 /* flags */ 0, 25505 }, 25506 #endif /* chips */ 25507 25508 #if defined(BCM_56504_A0) 25509 { /* SOC_FORMAT_INT_IPAD_BUSfmt */ 25510 /* format IPAD_BUSfmt */ 25511 /* nFields */ 12, 25512 /* *fields */ soc_IPAD_BUSfmt_fields, 25513 /* bits */ 65, 25514 /* flags */ 0, 25515 }, 25516 #endif /* chips */ 25517 25518 #if defined(BCM_53314_A0) 25519 { /* SOC_FORMAT_INT_IPAD_BUS_BCM53314_A0fmt */ 25520 /* format IPAD_BUSfmt */ 25521 /* nFields */ 13, 25522 /* *fields */ soc_IPAD_BUS_BCM53314_A0fmt_fields, 25523 /* bits */ 82, 25524 /* flags */ 0, 25525 }, 25526 #endif /* chips */ 25527 25528 #if defined(BCM_53324_A0) 25529 { /* SOC_FORMAT_INT_IPAD_BUS_BCM53324_A0fmt */ 25530 /* format IPAD_BUSfmt */ 25531 /* nFields */ 13, 25532 /* *fields */ soc_IPAD_BUS_BCM53314_A0fmt_fields, 25533 /* bits */ 82, 25534 /* flags */ 0, 25535 }, 25536 #endif /* chips */ 25537 25538 #if defined(BCM_53400_A0) 25539 { /* SOC_FORMAT_INT_IPAD_BUS_BCM53400_A0fmt */ 25540 /* format IPAD_BUSfmt */ 25541 /* nFields */ 23, 25542 /* *fields */ soc_IPAD_BUS_BCM53400_A0fmt_fields, 25543 /* bits */ 137, 25544 /* flags */ 0, 25545 }, 25546 #endif /* chips */ 25547 25548 #if defined(BCM_53540_A0) 25549 { /* SOC_FORMAT_INT_IPAD_BUS_BCM53540_A0fmt */ 25550 /* format IPAD_BUSfmt */ 25551 /* nFields */ 23, 25552 /* *fields */ soc_IPAD_BUS_BCM53400_A0fmt_fields, 25553 /* bits */ 137, 25554 /* flags */ 0, 25555 }, 25556 #endif /* chips */ 25557 25558 #if defined(BCM_53570_A0) 25559 { /* SOC_FORMAT_INT_IPAD_BUS_BCM53570_A0fmt */ 25560 /* format IPAD_BUSfmt */ 25561 /* nFields */ 26, 25562 /* *fields */ soc_IPAD_BUS_BCM53570_A0fmt_fields, 25563 /* bits */ 137, 25564 /* flags */ 0, 25565 }, 25566 #endif /* chips */ 25567 25568 #if defined(BCM_53570_B0) 25569 { /* SOC_FORMAT_INT_IPAD_BUS_BCM53570_B0fmt */ 25570 /* format IPAD_BUSfmt */ 25571 /* nFields */ 26, 25572 /* *fields */ soc_IPAD_BUS_BCM53570_A0fmt_fields, 25573 /* bits */ 137, 25574 /* flags */ 0, 25575 }, 25576 #endif /* chips */ 25577 25578 #if defined(BCM_56142_A0) 25579 { /* SOC_FORMAT_INT_IPAD_BUS_BCM56142_A0fmt */ 25580 /* format IPAD_BUSfmt */ 25581 /* nFields */ 18, 25582 /* *fields */ soc_IPAD_BUS_BCM56634_A0fmt_fields, 25583 /* bits */ 117, 25584 /* flags */ 0, 25585 }, 25586 #endif /* chips */ 25587 25588 #if defined(BCM_56150_A0) 25589 { /* SOC_FORMAT_INT_IPAD_BUS_BCM56150_A0fmt */ 25590 /* format IPAD_BUSfmt */ 25591 /* nFields */ 23, 25592 /* *fields */ soc_IPAD_BUS_BCM56150_A0fmt_fields, 25593 /* bits */ 137, 25594 /* flags */ 0, 25595 }, 25596 #endif /* chips */ 25597 25598 #if defined(BCM_56160_A0) 25599 { /* SOC_FORMAT_INT_IPAD_BUS_BCM56160_A0fmt */ 25600 /* format IPAD_BUSfmt */ 25601 /* nFields */ 23, 25602 /* *fields */ soc_IPAD_BUS_BCM53400_A0fmt_fields, 25603 /* bits */ 137, 25604 /* flags */ 0, 25605 }, 25606 #endif /* chips */ 25607 25608 #if defined(BCM_56224_A0) 25609 { /* SOC_FORMAT_INT_IPAD_BUS_BCM56224_A0fmt */ 25610 /* format IPAD_BUSfmt */ 25611 /* nFields */ 12, 25612 /* *fields */ soc_IPAD_BUS_BCM56224_A0fmt_fields, 25613 /* bits */ 50, 25614 /* flags */ 0, 25615 }, 25616 #endif /* chips */ 25617 25618 #if defined(BCM_56224_B0) 25619 { /* SOC_FORMAT_INT_IPAD_BUS_BCM56224_B0fmt */ 25620 /* format IPAD_BUSfmt */ 25621 /* nFields */ 12, 25622 /* *fields */ soc_IPAD_BUS_BCM56224_A0fmt_fields, 25623 /* bits */ 50, 25624 /* flags */ 0, 25625 }, 25626 #endif /* chips */ 25627 25628 #if defined(BCM_56260_A0) 25629 { /* SOC_FORMAT_INT_IPAD_BUS_BCM56260_A0fmt */ 25630 /* format IPAD_BUSfmt */ 25631 /* nFields */ 33, 25632 /* *fields */ soc_IPAD_BUS_BCM56260_A0fmt_fields, 25633 /* bits */ 195, 25634 /* flags */ 0, 25635 }, 25636 #endif /* chips */ 25637 25638 #if defined(BCM_56260_B0) 25639 { /* SOC_FORMAT_INT_IPAD_BUS_BCM56260_B0fmt */ 25640 /* format IPAD_BUSfmt */ 25641 /* nFields */ 33, 25642 /* *fields */ soc_IPAD_BUS_BCM56260_A0fmt_fields, 25643 /* bits */ 195, 25644 /* flags */ 0, 25645 }, 25646 #endif /* chips */ 25647 25648 #if defined(BCM_56270_A0) 25649 { /* SOC_FORMAT_INT_IPAD_BUS_BCM56270_A0fmt */ 25650 /* format IPAD_BUSfmt */ 25651 /* nFields */ 35, 25652 /* *fields */ soc_IPAD_BUS_BCM56270_A0fmt_fields, 25653 /* bits */ 195, 25654 /* flags */ 0, 25655 }, 25656 #endif /* chips */ 25657 25658 #if defined(BCM_56314_A0) 25659 { /* SOC_FORMAT_INT_IPAD_BUS_BCM56314_A0fmt */ 25660 /* format IPAD_BUSfmt */ 25661 /* nFields */ 12, 25662 /* *fields */ soc_IPAD_BUSfmt_fields, 25663 /* bits */ 65, 25664 /* flags */ 0, 25665 }, 25666 #endif /* chips */ 25667 25668 #if defined(BCM_56334_A0) 25669 { /* SOC_FORMAT_INT_IPAD_BUS_BCM56334_A0fmt */ 25670 /* format IPAD_BUSfmt */ 25671 /* nFields */ 18, 25672 /* *fields */ soc_IPAD_BUS_BCM56634_A0fmt_fields, 25673 /* bits */ 117, 25674 /* flags */ 0, 25675 }, 25676 #endif /* chips */ 25677 25678 #if defined(BCM_56334_B0) 25679 { /* SOC_FORMAT_INT_IPAD_BUS_BCM56334_B0fmt */ 25680 /* format IPAD_BUSfmt */ 25681 /* nFields */ 18, 25682 /* *fields */ soc_IPAD_BUS_BCM56634_A0fmt_fields, 25683 /* bits */ 117, 25684 /* flags */ 0, 25685 }, 25686 #endif /* chips */ 25687 25688 #if defined(BCM_56340_A0) 25689 { /* SOC_FORMAT_INT_IPAD_BUS_BCM56340_A0fmt */ 25690 /* format IPAD_BUSfmt */ 25691 /* nFields */ 22, 25692 /* *fields */ soc_IPAD_BUS_BCM56340_A0fmt_fields, 25693 /* bits */ 175, 25694 /* flags */ 0, 25695 }, 25696 #endif /* chips */ 25697 25698 #if defined(BCM_56370_A0) 25699 { /* SOC_FORMAT_INT_IPAD_BUS_BCM56370_A0fmt */ 25700 /* format IPAD_BUSfmt */ 25701 /* nFields */ 24, 25702 /* *fields */ soc_IPAD_BUS_BCM56370_A0fmt_fields, 25703 /* bits */ 153, 25704 /* flags */ 0, 25705 }, 25706 #endif /* chips */ 25707 25708 #if defined(BCM_56440_A0) 25709 { /* SOC_FORMAT_INT_IPAD_BUS_BCM56440_A0fmt */ 25710 /* format IPAD_BUSfmt */ 25711 /* nFields */ 29, 25712 /* *fields */ soc_IPAD_BUS_BCM56440_A0fmt_fields, 25713 /* bits */ 186, 25714 /* flags */ 0, 25715 }, 25716 #endif /* chips */ 25717 25718 #if defined(BCM_56440_B0) 25719 { /* SOC_FORMAT_INT_IPAD_BUS_BCM56440_B0fmt */ 25720 /* format IPAD_BUSfmt */ 25721 /* nFields */ 29, 25722 /* *fields */ soc_IPAD_BUS_BCM56440_A0fmt_fields, 25723 /* bits */ 186, 25724 /* flags */ 0, 25725 }, 25726 #endif /* chips */ 25727 25728 #if defined(BCM_56450_A0) 25729 { /* SOC_FORMAT_INT_IPAD_BUS_BCM56450_A0fmt */ 25730 /* format IPAD_BUSfmt */ 25731 /* nFields */ 32, 25732 /* *fields */ soc_IPAD_BUS_BCM56450_A0fmt_fields, 25733 /* bits */ 195, 25734 /* flags */ 0, 25735 }, 25736 #endif /* chips */ 25737 25738 #if defined(BCM_56450_B0) 25739 { /* SOC_FORMAT_INT_IPAD_BUS_BCM56450_B0fmt */ 25740 /* format IPAD_BUSfmt */ 25741 /* nFields */ 32, 25742 /* *fields */ soc_IPAD_BUS_BCM56450_A0fmt_fields, 25743 /* bits */ 195, 25744 /* flags */ 0, 25745 }, 25746 #endif /* chips */ 25747 25748 #if defined(BCM_56450_B1) 25749 { /* SOC_FORMAT_INT_IPAD_BUS_BCM56450_B1fmt */ 25750 /* format IPAD_BUSfmt */ 25751 /* nFields */ 32, 25752 /* *fields */ soc_IPAD_BUS_BCM56450_A0fmt_fields, 25753 /* bits */ 195, 25754 /* flags */ 0, 25755 }, 25756 #endif /* chips */ 25757 25758 #if defined(BCM_56504_B0) 25759 { /* SOC_FORMAT_INT_IPAD_BUS_BCM56504_B0fmt */ 25760 /* format IPAD_BUSfmt */ 25761 /* nFields */ 12, 25762 /* *fields */ soc_IPAD_BUSfmt_fields, 25763 /* bits */ 65, 25764 /* flags */ 0, 25765 }, 25766 #endif /* chips */ 25767 25768 #if defined(BCM_56514_A0) 25769 { /* SOC_FORMAT_INT_IPAD_BUS_BCM56514_A0fmt */ 25770 /* format IPAD_BUSfmt */ 25771 /* nFields */ 12, 25772 /* *fields */ soc_IPAD_BUS_BCM56514_A0fmt_fields, 25773 /* bits */ 66, 25774 /* flags */ 0, 25775 }, 25776 #endif /* chips */ 25777 25778 #if defined(BCM_56524_A0) 25779 { /* SOC_FORMAT_INT_IPAD_BUS_BCM56524_A0fmt */ 25780 /* format IPAD_BUSfmt */ 25781 /* nFields */ 18, 25782 /* *fields */ soc_IPAD_BUS_BCM56634_A0fmt_fields, 25783 /* bits */ 117, 25784 /* flags */ 0, 25785 }, 25786 #endif /* chips */ 25787 25788 #if defined(BCM_56524_B0) 25789 { /* SOC_FORMAT_INT_IPAD_BUS_BCM56524_B0fmt */ 25790 /* format IPAD_BUSfmt */ 25791 /* nFields */ 18, 25792 /* *fields */ soc_IPAD_BUS_BCM56634_A0fmt_fields, 25793 /* bits */ 117, 25794 /* flags */ 0, 25795 }, 25796 #endif /* chips */ 25797 25798 #if defined(BCM_56560_A0) 25799 { /* SOC_FORMAT_INT_IPAD_BUS_BCM56560_A0fmt */ 25800 /* format IPAD_BUSfmt */ 25801 /* nFields */ 28, 25802 /* *fields */ soc_IPAD_BUS_BCM56560_A0fmt_fields, 25803 /* bits */ 184, 25804 /* flags */ 0, 25805 }, 25806 #endif /* chips */ 25807 25808 #if defined(BCM_56560_B0) 25809 { /* SOC_FORMAT_INT_IPAD_BUS_BCM56560_B0fmt */ 25810 /* format IPAD_BUSfmt */ 25811 /* nFields */ 28, 25812 /* *fields */ soc_IPAD_BUS_BCM56560_A0fmt_fields, 25813 /* bits */ 184, 25814 /* flags */ 0, 25815 }, 25816 #endif /* chips */ 25817 25818 #if defined(BCM_56624_A0) 25819 { /* SOC_FORMAT_INT_IPAD_BUS_BCM56624_A0fmt */ 25820 /* format IPAD_BUSfmt */ 25821 /* nFields */ 16, 25822 /* *fields */ soc_IPAD_BUS_BCM56624_A0fmt_fields, 25823 /* bits */ 76, 25824 /* flags */ 0, 25825 }, 25826 #endif /* chips */ 25827 25828 #if defined(BCM_56624_B0) 25829 { /* SOC_FORMAT_INT_IPAD_BUS_BCM56624_B0fmt */ 25830 /* format IPAD_BUSfmt */ 25831 /* nFields */ 16, 25832 /* *fields */ soc_IPAD_BUS_BCM56624_A0fmt_fields, 25833 /* bits */ 76, 25834 /* flags */ 0, 25835 }, 25836 #endif /* chips */ 25837 25838 #if defined(BCM_56634_A0) 25839 { /* SOC_FORMAT_INT_IPAD_BUS_BCM56634_A0fmt */ 25840 /* format IPAD_BUSfmt */ 25841 /* nFields */ 18, 25842 /* *fields */ soc_IPAD_BUS_BCM56634_A0fmt_fields, 25843 /* bits */ 117, 25844 /* flags */ 0, 25845 }, 25846 #endif /* chips */ 25847 25848 #if defined(BCM_56634_B0) 25849 { /* SOC_FORMAT_INT_IPAD_BUS_BCM56634_B0fmt */ 25850 /* format IPAD_BUSfmt */ 25851 /* nFields */ 18, 25852 /* *fields */ soc_IPAD_BUS_BCM56634_A0fmt_fields, 25853 /* bits */ 117, 25854 /* flags */ 0, 25855 }, 25856 #endif /* chips */ 25857 25858 #if defined(BCM_56640_A0) 25859 { /* SOC_FORMAT_INT_IPAD_BUS_BCM56640_A0fmt */ 25860 /* format IPAD_BUSfmt */ 25861 /* nFields */ 22, 25862 /* *fields */ soc_IPAD_BUS_BCM56640_A0fmt_fields, 25863 /* bits */ 176, 25864 /* flags */ 0, 25865 }, 25866 #endif /* chips */ 25867 25868 #if defined(BCM_56670_A0) 25869 { /* SOC_FORMAT_INT_IPAD_BUS_BCM56670_A0fmt */ 25870 /* format IPAD_BUSfmt */ 25871 /* nFields */ 30, 25872 /* *fields */ soc_IPAD_BUS_BCM56670_A0fmt_fields, 25873 /* bits */ 183, 25874 /* flags */ 0, 25875 }, 25876 #endif /* chips */ 25877 25878 #if defined(BCM_56670_B0) 25879 { /* SOC_FORMAT_INT_IPAD_BUS_BCM56670_B0fmt */ 25880 /* format IPAD_BUSfmt */ 25881 /* nFields */ 30, 25882 /* *fields */ soc_IPAD_BUS_BCM56670_A0fmt_fields, 25883 /* bits */ 183, 25884 /* flags */ 0, 25885 }, 25886 #endif /* chips */ 25887 25888 #if defined(BCM_56680_A0) 25889 { /* SOC_FORMAT_INT_IPAD_BUS_BCM56680_A0fmt */ 25890 /* format IPAD_BUSfmt */ 25891 /* nFields */ 16, 25892 /* *fields */ soc_IPAD_BUS_BCM56624_A0fmt_fields, 25893 /* bits */ 76, 25894 /* flags */ 0, 25895 }, 25896 #endif /* chips */ 25897 25898 #if defined(BCM_56680_B0) 25899 { /* SOC_FORMAT_INT_IPAD_BUS_BCM56680_B0fmt */ 25900 /* format IPAD_BUSfmt */ 25901 /* nFields */ 16, 25902 /* *fields */ soc_IPAD_BUS_BCM56624_A0fmt_fields, 25903 /* bits */ 76, 25904 /* flags */ 0, 25905 }, 25906 #endif /* chips */ 25907 25908 #if defined(BCM_56685_A0) 25909 { /* SOC_FORMAT_INT_IPAD_BUS_BCM56685_A0fmt */ 25910 /* format IPAD_BUSfmt */ 25911 /* nFields */ 18, 25912 /* *fields */ soc_IPAD_BUS_BCM56634_A0fmt_fields, 25913 /* bits */ 117, 25914 /* flags */ 0, 25915 }, 25916 #endif /* chips */ 25917 25918 #if defined(BCM_56685_B0) 25919 { /* SOC_FORMAT_INT_IPAD_BUS_BCM56685_B0fmt */ 25920 /* format IPAD_BUSfmt */ 25921 /* nFields */ 18, 25922 /* *fields */ soc_IPAD_BUS_BCM56634_A0fmt_fields, 25923 /* bits */ 117, 25924 /* flags */ 0, 25925 }, 25926 #endif /* chips */ 25927 25928 #if defined(BCM_56725_A0) 25929 { /* SOC_FORMAT_INT_IPAD_BUS_BCM56725_A0fmt */ 25930 /* format IPAD_BUSfmt */ 25931 /* nFields */ 12, 25932 /* *fields */ soc_IPAD_BUS_BCM56820_A0fmt_fields, 25933 /* bits */ 43, 25934 /* flags */ 0, 25935 }, 25936 #endif /* chips */ 25937 25938 #if defined(BCM_56770_A0) 25939 { /* SOC_FORMAT_INT_IPAD_BUS_BCM56770_A0fmt */ 25940 /* format IPAD_BUSfmt */ 25941 /* nFields */ 23, 25942 /* *fields */ soc_IPAD_BUS_BCM56870_A0fmt_fields, 25943 /* bits */ 153, 25944 /* flags */ 0, 25945 }, 25946 #endif /* chips */ 25947 25948 #if defined(BCM_56800_A0) 25949 { /* SOC_FORMAT_INT_IPAD_BUS_BCM56800_A0fmt */ 25950 /* format IPAD_BUSfmt */ 25951 /* nFields */ 12, 25952 /* *fields */ soc_IPAD_BUS_BCM56800_A0fmt_fields, 25953 /* bits */ 42, 25954 /* flags */ 0, 25955 }, 25956 #endif /* chips */ 25957 25958 #if defined(BCM_56820_A0) 25959 { /* SOC_FORMAT_INT_IPAD_BUS_BCM56820_A0fmt */ 25960 /* format IPAD_BUSfmt */ 25961 /* nFields */ 12, 25962 /* *fields */ soc_IPAD_BUS_BCM56820_A0fmt_fields, 25963 /* bits */ 43, 25964 /* flags */ 0, 25965 }, 25966 #endif /* chips */ 25967 25968 #if defined(BCM_56840_A0) 25969 { /* SOC_FORMAT_INT_IPAD_BUS_BCM56840_A0fmt */ 25970 /* format IPAD_BUSfmt */ 25971 /* nFields */ 23, 25972 /* *fields */ soc_IPAD_BUS_BCM56840_A0fmt_fields, 25973 /* bits */ 176, 25974 /* flags */ 0, 25975 }, 25976 #endif /* chips */ 25977 25978 #if defined(BCM_56840_B0) 25979 { /* SOC_FORMAT_INT_IPAD_BUS_BCM56840_B0fmt */ 25980 /* format IPAD_BUSfmt */ 25981 /* nFields */ 23, 25982 /* *fields */ soc_IPAD_BUS_BCM56840_A0fmt_fields, 25983 /* bits */ 176, 25984 /* flags */ 0, 25985 }, 25986 #endif /* chips */ 25987 25988 #if defined(BCM_56850_A0) 25989 { /* SOC_FORMAT_INT_IPAD_BUS_BCM56850_A0fmt */ 25990 /* format IPAD_BUSfmt */ 25991 /* nFields */ 24, 25992 /* *fields */ soc_IPAD_BUS_BCM56850_A0fmt_fields, 25993 /* bits */ 180, 25994 /* flags */ 0, 25995 }, 25996 #endif /* chips */ 25997 25998 #if defined(BCM_56860_A0) 25999 { /* SOC_FORMAT_INT_IPAD_BUS_BCM56860_A0fmt */ 26000 /* format IPAD_BUSfmt */ 26001 /* nFields */ 26, 26002 /* *fields */ soc_IPAD_BUS_BCM56860_A0fmt_fields, 26003 /* bits */ 182, 26004 /* flags */ 0, 26005 }, 26006 #endif /* chips */ 26007 26008 #if defined(BCM_56870_A0) 26009 { /* SOC_FORMAT_INT_IPAD_BUS_BCM56870_A0fmt */ 26010 /* format IPAD_BUSfmt */ 26011 /* nFields */ 23, 26012 /* *fields */ soc_IPAD_BUS_BCM56870_A0fmt_fields, 26013 /* bits */ 153, 26014 /* flags */ 0, 26015 }, 26016 #endif /* chips */ 26017 26018 #if defined(BCM_56960_A0) 26019 { /* SOC_FORMAT_INT_IPAD_BUS_BCM56960_A0fmt */ 26020 /* format IPAD_BUSfmt */ 26021 /* nFields */ 22, 26022 /* *fields */ soc_IPAD_BUS_BCM56960_A0fmt_fields, 26023 /* bits */ 141, 26024 /* flags */ 0, 26025 }, 26026 #endif /* chips */ 26027 26028 #if defined(BCM_56965_A0) 26029 { /* SOC_FORMAT_INT_IPAD_BUS_BCM56965_A0fmt */ 26030 /* format IPAD_BUSfmt */ 26031 /* nFields */ 22, 26032 /* *fields */ soc_IPAD_BUS_BCM56960_A0fmt_fields, 26033 /* bits */ 141, 26034 /* flags */ 0, 26035 }, 26036 #endif /* chips */ 26037 26038 #if defined(BCM_56970_A0) 26039 { /* SOC_FORMAT_INT_IPAD_BUS_BCM56970_A0fmt */ 26040 /* format IPAD_BUSfmt */ 26041 /* nFields */ 22, 26042 /* *fields */ soc_IPAD_BUS_BCM56960_A0fmt_fields, 26043 /* bits */ 141, 26044 /* flags */ 0, 26045 }, 26046 #endif /* chips */ 26047 26048 #if defined(BCM_56980_A0) 26049 { /* SOC_FORMAT_INT_IPAD_BUS_BCM56980_A0fmt */ 26050 /* format IPAD_BUSfmt */ 26051 /* nFields */ 20, 26052 /* *fields */ soc_IPAD_BUS_BCM56980_A0fmt_fields, 26053 /* bits */ 109, 26054 /* flags */ 0, 26055 }, 26056 #endif /* chips */ 26057 26058 #if defined(BCM_56980_B0) 26059 { /* SOC_FORMAT_INT_IPAD_BUS_BCM56980_B0fmt */ 26060 /* format IPAD_BUSfmt */ 26061 /* nFields */ 23, 26062 /* *fields */ soc_IPAD_BUS_BCM56980_B0fmt_fields, 26063 /* bits */ 109, 26064 /* flags */ 0, 26065 }, 26066 #endif /* chips */ 26067 26068 #if defined(BCM_88732_A0) 26069 { /* SOC_FORMAT_INT_IPAD_BUS_BCM88732_A0fmt */ 26070 /* format IPAD_BUSfmt */ 26071 /* nFields */ 12, 26072 /* *fields */ soc_IPAD_BUS_BCM88732_A0fmt_fields, 26073 /* bits */ 52, 26074 /* flags */ 0, 26075 }, 26076 #endif /* chips */ 26077 26078 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 26079 defined(BCM_56870_A0) 26080 { /* SOC_FORMAT_INT_IPARS1_DOPfmt */ 26081 /* format IPARS1_DOPfmt */ 26082 /* nFields */ 30, 26083 /* *fields */ soc_IPARS1_DOPfmt_fields, 26084 /* bits */ 896, 26085 /* flags */ 0, 26086 }, 26087 #endif /* chips */ 26088 26089 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) 26090 { /* SOC_FORMAT_INT_IPARS2_0_DOPfmt */ 26091 /* format IPARS2_0_DOPfmt */ 26092 /* nFields */ 3, 26093 /* *fields */ soc_IPARS2_0_DOPfmt_fields, 26094 /* bits */ 224, 26095 /* flags */ 0, 26096 }, 26097 #endif /* chips */ 26098 26099 #if defined(BCM_56370_A0) 26100 { /* SOC_FORMAT_INT_IPARS2_0_DOP_BCM56370_A0fmt */ 26101 /* format IPARS2_0_DOPfmt */ 26102 /* nFields */ 3, 26103 /* *fields */ soc_IPARS2_0_DOP_BCM56370_A0fmt_fields, 26104 /* bits */ 224, 26105 /* flags */ 0, 26106 }, 26107 #endif /* chips */ 26108 26109 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 26110 defined(BCM_56870_A0) 26111 { /* SOC_FORMAT_INT_IPARS2_DOPfmt */ 26112 /* format IPARS2_DOPfmt */ 26113 /* nFields */ 30, 26114 /* *fields */ soc_IPARS2_DOPfmt_fields, 26115 /* bits */ 960, 26116 /* flags */ 0, 26117 }, 26118 #endif /* chips */ 26119 26120 #if defined(BCM_88732_A0) 26121 { /* SOC_FORMAT_INT_IPARS_EOP_BUFFERfmt */ 26122 /* format IPARS_EOP_BUFFERfmt */ 26123 /* nFields */ 3, 26124 /* *fields */ soc_IPARS_EOP_BUFFERfmt_fields, 26125 /* bits */ 25, 26126 /* flags */ 0, 26127 }, 26128 #endif /* chips */ 26129 26130 #if defined(BCM_56670_A0) 26131 { /* SOC_FORMAT_INT_IPARS_EOP_BUFFER_BCM56670_A0fmt */ 26132 /* format IPARS_EOP_BUFFERfmt */ 26133 /* nFields */ 1, 26134 /* *fields */ soc_IPARS_EOP_BUFFER_BCM56670_A0fmt_fields, 26135 /* bits */ 7, 26136 /* flags */ 0, 26137 }, 26138 #endif /* chips */ 26139 26140 #if defined(BCM_56670_B0) 26141 { /* SOC_FORMAT_INT_IPARS_EOP_BUFFER_BCM56670_B0fmt */ 26142 /* format IPARS_EOP_BUFFERfmt */ 26143 /* nFields */ 1, 26144 /* *fields */ soc_IPARS_EOP_BUFFER_BCM56670_A0fmt_fields, 26145 /* bits */ 7, 26146 /* flags */ 0, 26147 }, 26148 #endif /* chips */ 26149 26150 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \ 26151 defined(BCM_56840_A0) || defined(BCM_56840_B0) 26152 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_FCOE_FIELDS_BUSfmt */ 26153 /* format IPARS_TO_IMPLS_FCOE_FIELDS_BUSfmt */ 26154 /* nFields */ 8, 26155 /* *fields */ soc_IPARS_TO_IMPLS_FCOE_FIELDS_BUSfmt_fields, 26156 /* bits */ 208, 26157 /* flags */ 0, 26158 }, 26159 #endif /* chips */ 26160 26161 #if defined(BCM_56260_A0) 26162 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_FCOE_FIELDS_BUS_BCM56260_A0fmt */ 26163 /* format IPARS_TO_IMPLS_FCOE_FIELDS_BUSfmt */ 26164 /* nFields */ 8, 26165 /* *fields */ soc_IPARS_TO_IMPLS_FCOE_FIELDS_BUS_BCM56260_A0fmt_fields, 26166 /* bits */ 208, 26167 /* flags */ 0, 26168 }, 26169 #endif /* chips */ 26170 26171 #if defined(BCM_56260_B0) 26172 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_FCOE_FIELDS_BUS_BCM56260_B0fmt */ 26173 /* format IPARS_TO_IMPLS_FCOE_FIELDS_BUSfmt */ 26174 /* nFields */ 8, 26175 /* *fields */ soc_IPARS_TO_IMPLS_FCOE_FIELDS_BUS_BCM56260_A0fmt_fields, 26176 /* bits */ 208, 26177 /* flags */ 0, 26178 }, 26179 #endif /* chips */ 26180 26181 #if defined(BCM_56270_A0) 26182 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_FCOE_FIELDS_BUS_BCM56270_A0fmt */ 26183 /* format IPARS_TO_IMPLS_FCOE_FIELDS_BUSfmt */ 26184 /* nFields */ 8, 26185 /* *fields */ soc_IPARS_TO_IMPLS_FCOE_FIELDS_BUS_BCM56260_A0fmt_fields, 26186 /* bits */ 208, 26187 /* flags */ 0, 26188 }, 26189 #endif /* chips */ 26190 26191 #if defined(BCM_56340_A0) 26192 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_FCOE_FIELDS_BUS_BCM56340_A0fmt */ 26193 /* format IPARS_TO_IMPLS_FCOE_FIELDS_BUSfmt */ 26194 /* nFields */ 8, 26195 /* *fields */ soc_IPARS_TO_IMPLS_FCOE_FIELDS_BUS_BCM56640_A0fmt_fields, 26196 /* bits */ 209, 26197 /* flags */ 0, 26198 }, 26199 #endif /* chips */ 26200 26201 #if defined(BCM_56370_A0) 26202 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_FCOE_FIELDS_BUS_BCM56370_A0fmt */ 26203 /* format IPARS_TO_IMPLS_FCOE_FIELDS_BUSfmt */ 26204 /* nFields */ 19, 26205 /* *fields */ soc_IPARS_TO_IMPLS_FCOE_FIELDS_BUS_BCM56960_A0fmt_fields, 26206 /* bits */ 209, 26207 /* flags */ 0, 26208 }, 26209 #endif /* chips */ 26210 26211 #if defined(BCM_56450_A0) 26212 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_FCOE_FIELDS_BUS_BCM56450_A0fmt */ 26213 /* format IPARS_TO_IMPLS_FCOE_FIELDS_BUSfmt */ 26214 /* nFields */ 8, 26215 /* *fields */ soc_IPARS_TO_IMPLS_FCOE_FIELDS_BUS_BCM56450_A0fmt_fields, 26216 /* bits */ 208, 26217 /* flags */ 0, 26218 }, 26219 #endif /* chips */ 26220 26221 #if defined(BCM_56450_B0) 26222 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_FCOE_FIELDS_BUS_BCM56450_B0fmt */ 26223 /* format IPARS_TO_IMPLS_FCOE_FIELDS_BUSfmt */ 26224 /* nFields */ 8, 26225 /* *fields */ soc_IPARS_TO_IMPLS_FCOE_FIELDS_BUS_BCM56450_A0fmt_fields, 26226 /* bits */ 208, 26227 /* flags */ 0, 26228 }, 26229 #endif /* chips */ 26230 26231 #if defined(BCM_56450_B1) 26232 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_FCOE_FIELDS_BUS_BCM56450_B1fmt */ 26233 /* format IPARS_TO_IMPLS_FCOE_FIELDS_BUSfmt */ 26234 /* nFields */ 8, 26235 /* *fields */ soc_IPARS_TO_IMPLS_FCOE_FIELDS_BUS_BCM56450_A0fmt_fields, 26236 /* bits */ 208, 26237 /* flags */ 0, 26238 }, 26239 #endif /* chips */ 26240 26241 #if defined(BCM_56560_A0) 26242 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_FCOE_FIELDS_BUS_BCM56560_A0fmt */ 26243 /* format IPARS_TO_IMPLS_FCOE_FIELDS_BUSfmt */ 26244 /* nFields */ 19, 26245 /* *fields */ soc_IPARS_TO_IMPLS_FCOE_FIELDS_BUS_BCM56960_A0fmt_fields, 26246 /* bits */ 209, 26247 /* flags */ 0, 26248 }, 26249 #endif /* chips */ 26250 26251 #if defined(BCM_56560_B0) 26252 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_FCOE_FIELDS_BUS_BCM56560_B0fmt */ 26253 /* format IPARS_TO_IMPLS_FCOE_FIELDS_BUSfmt */ 26254 /* nFields */ 19, 26255 /* *fields */ soc_IPARS_TO_IMPLS_FCOE_FIELDS_BUS_BCM56960_A0fmt_fields, 26256 /* bits */ 209, 26257 /* flags */ 0, 26258 }, 26259 #endif /* chips */ 26260 26261 #if defined(BCM_56640_A0) 26262 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_FCOE_FIELDS_BUS_BCM56640_A0fmt */ 26263 /* format IPARS_TO_IMPLS_FCOE_FIELDS_BUSfmt */ 26264 /* nFields */ 8, 26265 /* *fields */ soc_IPARS_TO_IMPLS_FCOE_FIELDS_BUS_BCM56640_A0fmt_fields, 26266 /* bits */ 209, 26267 /* flags */ 0, 26268 }, 26269 #endif /* chips */ 26270 26271 #if defined(BCM_56670_A0) 26272 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_FCOE_FIELDS_BUS_BCM56670_A0fmt */ 26273 /* format IPARS_TO_IMPLS_FCOE_FIELDS_BUSfmt */ 26274 /* nFields */ 19, 26275 /* *fields */ soc_IPARS_TO_IMPLS_FCOE_FIELDS_BUS_BCM56960_A0fmt_fields, 26276 /* bits */ 209, 26277 /* flags */ 0, 26278 }, 26279 #endif /* chips */ 26280 26281 #if defined(BCM_56670_B0) 26282 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_FCOE_FIELDS_BUS_BCM56670_B0fmt */ 26283 /* format IPARS_TO_IMPLS_FCOE_FIELDS_BUSfmt */ 26284 /* nFields */ 19, 26285 /* *fields */ soc_IPARS_TO_IMPLS_FCOE_FIELDS_BUS_BCM56960_A0fmt_fields, 26286 /* bits */ 209, 26287 /* flags */ 0, 26288 }, 26289 #endif /* chips */ 26290 26291 #if defined(BCM_56770_A0) 26292 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_FCOE_FIELDS_BUS_BCM56770_A0fmt */ 26293 /* format IPARS_TO_IMPLS_FCOE_FIELDS_BUSfmt */ 26294 /* nFields */ 19, 26295 /* *fields */ soc_IPARS_TO_IMPLS_FCOE_FIELDS_BUS_BCM56960_A0fmt_fields, 26296 /* bits */ 209, 26297 /* flags */ 0, 26298 }, 26299 #endif /* chips */ 26300 26301 #if defined(BCM_56850_A0) 26302 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_FCOE_FIELDS_BUS_BCM56850_A0fmt */ 26303 /* format IPARS_TO_IMPLS_FCOE_FIELDS_BUSfmt */ 26304 /* nFields */ 19, 26305 /* *fields */ soc_IPARS_TO_IMPLS_FCOE_FIELDS_BUS_BCM56850_A0fmt_fields, 26306 /* bits */ 209, 26307 /* flags */ 0, 26308 }, 26309 #endif /* chips */ 26310 26311 #if defined(BCM_56860_A0) 26312 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_FCOE_FIELDS_BUS_BCM56860_A0fmt */ 26313 /* format IPARS_TO_IMPLS_FCOE_FIELDS_BUSfmt */ 26314 /* nFields */ 19, 26315 /* *fields */ soc_IPARS_TO_IMPLS_FCOE_FIELDS_BUS_BCM56850_A0fmt_fields, 26316 /* bits */ 209, 26317 /* flags */ 0, 26318 }, 26319 #endif /* chips */ 26320 26321 #if defined(BCM_56870_A0) 26322 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_FCOE_FIELDS_BUS_BCM56870_A0fmt */ 26323 /* format IPARS_TO_IMPLS_FCOE_FIELDS_BUSfmt */ 26324 /* nFields */ 19, 26325 /* *fields */ soc_IPARS_TO_IMPLS_FCOE_FIELDS_BUS_BCM56960_A0fmt_fields, 26326 /* bits */ 209, 26327 /* flags */ 0, 26328 }, 26329 #endif /* chips */ 26330 26331 #if defined(BCM_56960_A0) 26332 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_FCOE_FIELDS_BUS_BCM56960_A0fmt */ 26333 /* format IPARS_TO_IMPLS_FCOE_FIELDS_BUSfmt */ 26334 /* nFields */ 19, 26335 /* *fields */ soc_IPARS_TO_IMPLS_FCOE_FIELDS_BUS_BCM56960_A0fmt_fields, 26336 /* bits */ 209, 26337 /* flags */ 0, 26338 }, 26339 #endif /* chips */ 26340 26341 #if defined(BCM_56965_A0) 26342 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_FCOE_FIELDS_BUS_BCM56965_A0fmt */ 26343 /* format IPARS_TO_IMPLS_FCOE_FIELDS_BUSfmt */ 26344 /* nFields */ 19, 26345 /* *fields */ soc_IPARS_TO_IMPLS_FCOE_FIELDS_BUS_BCM56960_A0fmt_fields, 26346 /* bits */ 209, 26347 /* flags */ 0, 26348 }, 26349 #endif /* chips */ 26350 26351 #if defined(BCM_56970_A0) 26352 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_FCOE_FIELDS_BUS_BCM56970_A0fmt */ 26353 /* format IPARS_TO_IMPLS_FCOE_FIELDS_BUSfmt */ 26354 /* nFields */ 19, 26355 /* *fields */ soc_IPARS_TO_IMPLS_FCOE_FIELDS_BUS_BCM56960_A0fmt_fields, 26356 /* bits */ 209, 26357 /* flags */ 0, 26358 }, 26359 #endif /* chips */ 26360 26361 #if defined(BCM_56980_A0) 26362 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_FCOE_FIELDS_BUS_BCM56980_A0fmt */ 26363 /* format IPARS_TO_IMPLS_FCOE_FIELDS_BUSfmt */ 26364 /* nFields */ 19, 26365 /* *fields */ soc_IPARS_TO_IMPLS_FCOE_FIELDS_BUS_BCM56960_A0fmt_fields, 26366 /* bits */ 209, 26367 /* flags */ 0, 26368 }, 26369 #endif /* chips */ 26370 26371 #if defined(BCM_56980_B0) 26372 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_FCOE_FIELDS_BUS_BCM56980_B0fmt */ 26373 /* format IPARS_TO_IMPLS_FCOE_FIELDS_BUSfmt */ 26374 /* nFields */ 19, 26375 /* *fields */ soc_IPARS_TO_IMPLS_FCOE_FIELDS_BUS_BCM56960_A0fmt_fields, 26376 /* bits */ 209, 26377 /* flags */ 0, 26378 }, 26379 #endif /* chips */ 26380 26381 #if defined(BCM_56840_A0) || defined(BCM_56840_B0) 26382 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_IP_FIELDS_BUSfmt */ 26383 /* format IPARS_TO_IMPLS_IP_FIELDS_BUSfmt */ 26384 /* nFields */ 37, 26385 /* *fields */ soc_IPARS_TO_IMPLS_IP_FIELDS_BUSfmt_fields, 26386 /* bits */ 208, 26387 /* flags */ 0, 26388 }, 26389 #endif /* chips */ 26390 26391 #if defined(BCM_56260_A0) 26392 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_IP_FIELDS_BUS_BCM56260_A0fmt */ 26393 /* format IPARS_TO_IMPLS_IP_FIELDS_BUSfmt */ 26394 /* nFields */ 37, 26395 /* *fields */ soc_IPARS_TO_IMPLS_IP_FIELDS_BUS_BCM56260_A0fmt_fields, 26396 /* bits */ 208, 26397 /* flags */ 0, 26398 }, 26399 #endif /* chips */ 26400 26401 #if defined(BCM_56260_B0) 26402 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_IP_FIELDS_BUS_BCM56260_B0fmt */ 26403 /* format IPARS_TO_IMPLS_IP_FIELDS_BUSfmt */ 26404 /* nFields */ 37, 26405 /* *fields */ soc_IPARS_TO_IMPLS_IP_FIELDS_BUS_BCM56260_A0fmt_fields, 26406 /* bits */ 208, 26407 /* flags */ 0, 26408 }, 26409 #endif /* chips */ 26410 26411 #if defined(BCM_56270_A0) 26412 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_IP_FIELDS_BUS_BCM56270_A0fmt */ 26413 /* format IPARS_TO_IMPLS_IP_FIELDS_BUSfmt */ 26414 /* nFields */ 37, 26415 /* *fields */ soc_IPARS_TO_IMPLS_IP_FIELDS_BUS_BCM56260_A0fmt_fields, 26416 /* bits */ 208, 26417 /* flags */ 0, 26418 }, 26419 #endif /* chips */ 26420 26421 #if defined(BCM_56340_A0) 26422 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_IP_FIELDS_BUS_BCM56340_A0fmt */ 26423 /* format IPARS_TO_IMPLS_IP_FIELDS_BUSfmt */ 26424 /* nFields */ 37, 26425 /* *fields */ soc_IPARS_TO_IMPLS_IP_FIELDS_BUS_BCM56450_A0fmt_fields, 26426 /* bits */ 208, 26427 /* flags */ 0, 26428 }, 26429 #endif /* chips */ 26430 26431 #if defined(BCM_56370_A0) 26432 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_IP_FIELDS_BUS_BCM56370_A0fmt */ 26433 /* format IPARS_TO_IMPLS_IP_FIELDS_BUSfmt */ 26434 /* nFields */ 37, 26435 /* *fields */ soc_IPARS_TO_IMPLS_IP_FIELDS_BUS_BCM56560_A0fmt_fields, 26436 /* bits */ 209, 26437 /* flags */ 0, 26438 }, 26439 #endif /* chips */ 26440 26441 #if defined(BCM_56440_A0) 26442 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_IP_FIELDS_BUS_BCM56440_A0fmt */ 26443 /* format IPARS_TO_IMPLS_IP_FIELDS_BUSfmt */ 26444 /* nFields */ 37, 26445 /* *fields */ soc_IPARS_TO_IMPLS_IP_FIELDS_BUS_BCM56440_A0fmt_fields, 26446 /* bits */ 208, 26447 /* flags */ 0, 26448 }, 26449 #endif /* chips */ 26450 26451 #if defined(BCM_56440_B0) 26452 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_IP_FIELDS_BUS_BCM56440_B0fmt */ 26453 /* format IPARS_TO_IMPLS_IP_FIELDS_BUSfmt */ 26454 /* nFields */ 37, 26455 /* *fields */ soc_IPARS_TO_IMPLS_IP_FIELDS_BUS_BCM56440_A0fmt_fields, 26456 /* bits */ 208, 26457 /* flags */ 0, 26458 }, 26459 #endif /* chips */ 26460 26461 #if defined(BCM_56450_A0) 26462 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_IP_FIELDS_BUS_BCM56450_A0fmt */ 26463 /* format IPARS_TO_IMPLS_IP_FIELDS_BUSfmt */ 26464 /* nFields */ 37, 26465 /* *fields */ soc_IPARS_TO_IMPLS_IP_FIELDS_BUS_BCM56450_A0fmt_fields, 26466 /* bits */ 208, 26467 /* flags */ 0, 26468 }, 26469 #endif /* chips */ 26470 26471 #if defined(BCM_56450_B0) 26472 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_IP_FIELDS_BUS_BCM56450_B0fmt */ 26473 /* format IPARS_TO_IMPLS_IP_FIELDS_BUSfmt */ 26474 /* nFields */ 37, 26475 /* *fields */ soc_IPARS_TO_IMPLS_IP_FIELDS_BUS_BCM56450_A0fmt_fields, 26476 /* bits */ 208, 26477 /* flags */ 0, 26478 }, 26479 #endif /* chips */ 26480 26481 #if defined(BCM_56450_B1) 26482 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_IP_FIELDS_BUS_BCM56450_B1fmt */ 26483 /* format IPARS_TO_IMPLS_IP_FIELDS_BUSfmt */ 26484 /* nFields */ 37, 26485 /* *fields */ soc_IPARS_TO_IMPLS_IP_FIELDS_BUS_BCM56450_A0fmt_fields, 26486 /* bits */ 208, 26487 /* flags */ 0, 26488 }, 26489 #endif /* chips */ 26490 26491 #if defined(BCM_56560_A0) 26492 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_IP_FIELDS_BUS_BCM56560_A0fmt */ 26493 /* format IPARS_TO_IMPLS_IP_FIELDS_BUSfmt */ 26494 /* nFields */ 37, 26495 /* *fields */ soc_IPARS_TO_IMPLS_IP_FIELDS_BUS_BCM56560_A0fmt_fields, 26496 /* bits */ 209, 26497 /* flags */ 0, 26498 }, 26499 #endif /* chips */ 26500 26501 #if defined(BCM_56560_B0) 26502 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_IP_FIELDS_BUS_BCM56560_B0fmt */ 26503 /* format IPARS_TO_IMPLS_IP_FIELDS_BUSfmt */ 26504 /* nFields */ 37, 26505 /* *fields */ soc_IPARS_TO_IMPLS_IP_FIELDS_BUS_BCM56560_A0fmt_fields, 26506 /* bits */ 209, 26507 /* flags */ 0, 26508 }, 26509 #endif /* chips */ 26510 26511 #if defined(BCM_56640_A0) 26512 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_IP_FIELDS_BUS_BCM56640_A0fmt */ 26513 /* format IPARS_TO_IMPLS_IP_FIELDS_BUSfmt */ 26514 /* nFields */ 37, 26515 /* *fields */ soc_IPARS_TO_IMPLS_IP_FIELDS_BUS_BCM56640_A0fmt_fields, 26516 /* bits */ 209, 26517 /* flags */ 0, 26518 }, 26519 #endif /* chips */ 26520 26521 #if defined(BCM_56670_A0) 26522 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_IP_FIELDS_BUS_BCM56670_A0fmt */ 26523 /* format IPARS_TO_IMPLS_IP_FIELDS_BUSfmt */ 26524 /* nFields */ 37, 26525 /* *fields */ soc_IPARS_TO_IMPLS_IP_FIELDS_BUS_BCM56560_A0fmt_fields, 26526 /* bits */ 209, 26527 /* flags */ 0, 26528 }, 26529 #endif /* chips */ 26530 26531 #if defined(BCM_56670_B0) 26532 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_IP_FIELDS_BUS_BCM56670_B0fmt */ 26533 /* format IPARS_TO_IMPLS_IP_FIELDS_BUSfmt */ 26534 /* nFields */ 37, 26535 /* *fields */ soc_IPARS_TO_IMPLS_IP_FIELDS_BUS_BCM56560_A0fmt_fields, 26536 /* bits */ 209, 26537 /* flags */ 0, 26538 }, 26539 #endif /* chips */ 26540 26541 #if defined(BCM_56770_A0) 26542 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_IP_FIELDS_BUS_BCM56770_A0fmt */ 26543 /* format IPARS_TO_IMPLS_IP_FIELDS_BUSfmt */ 26544 /* nFields */ 37, 26545 /* *fields */ soc_IPARS_TO_IMPLS_IP_FIELDS_BUS_BCM56560_A0fmt_fields, 26546 /* bits */ 209, 26547 /* flags */ 0, 26548 }, 26549 #endif /* chips */ 26550 26551 #if defined(BCM_56850_A0) 26552 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_IP_FIELDS_BUS_BCM56850_A0fmt */ 26553 /* format IPARS_TO_IMPLS_IP_FIELDS_BUSfmt */ 26554 /* nFields */ 38, 26555 /* *fields */ soc_IPARS_TO_IMPLS_IP_FIELDS_BUS_BCM56850_A0fmt_fields, 26556 /* bits */ 209, 26557 /* flags */ 0, 26558 }, 26559 #endif /* chips */ 26560 26561 #if defined(BCM_56860_A0) 26562 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_IP_FIELDS_BUS_BCM56860_A0fmt */ 26563 /* format IPARS_TO_IMPLS_IP_FIELDS_BUSfmt */ 26564 /* nFields */ 37, 26565 /* *fields */ soc_IPARS_TO_IMPLS_IP_FIELDS_BUS_BCM56640_A0fmt_fields, 26566 /* bits */ 209, 26567 /* flags */ 0, 26568 }, 26569 #endif /* chips */ 26570 26571 #if defined(BCM_56870_A0) 26572 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_IP_FIELDS_BUS_BCM56870_A0fmt */ 26573 /* format IPARS_TO_IMPLS_IP_FIELDS_BUSfmt */ 26574 /* nFields */ 37, 26575 /* *fields */ soc_IPARS_TO_IMPLS_IP_FIELDS_BUS_BCM56560_A0fmt_fields, 26576 /* bits */ 209, 26577 /* flags */ 0, 26578 }, 26579 #endif /* chips */ 26580 26581 #if defined(BCM_56960_A0) 26582 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_IP_FIELDS_BUS_BCM56960_A0fmt */ 26583 /* format IPARS_TO_IMPLS_IP_FIELDS_BUSfmt */ 26584 /* nFields */ 38, 26585 /* *fields */ soc_IPARS_TO_IMPLS_IP_FIELDS_BUS_BCM56960_A0fmt_fields, 26586 /* bits */ 209, 26587 /* flags */ 0, 26588 }, 26589 #endif /* chips */ 26590 26591 #if defined(BCM_56965_A0) 26592 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_IP_FIELDS_BUS_BCM56965_A0fmt */ 26593 /* format IPARS_TO_IMPLS_IP_FIELDS_BUSfmt */ 26594 /* nFields */ 38, 26595 /* *fields */ soc_IPARS_TO_IMPLS_IP_FIELDS_BUS_BCM56960_A0fmt_fields, 26596 /* bits */ 209, 26597 /* flags */ 0, 26598 }, 26599 #endif /* chips */ 26600 26601 #if defined(BCM_56970_A0) 26602 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_IP_FIELDS_BUS_BCM56970_A0fmt */ 26603 /* format IPARS_TO_IMPLS_IP_FIELDS_BUSfmt */ 26604 /* nFields */ 38, 26605 /* *fields */ soc_IPARS_TO_IMPLS_IP_FIELDS_BUS_BCM56960_A0fmt_fields, 26606 /* bits */ 209, 26607 /* flags */ 0, 26608 }, 26609 #endif /* chips */ 26610 26611 #if defined(BCM_56980_A0) 26612 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_IP_FIELDS_BUS_BCM56980_A0fmt */ 26613 /* format IPARS_TO_IMPLS_IP_FIELDS_BUSfmt */ 26614 /* nFields */ 38, 26615 /* *fields */ soc_IPARS_TO_IMPLS_IP_FIELDS_BUS_BCM56960_A0fmt_fields, 26616 /* bits */ 209, 26617 /* flags */ 0, 26618 }, 26619 #endif /* chips */ 26620 26621 #if defined(BCM_56980_B0) 26622 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_IP_FIELDS_BUS_BCM56980_B0fmt */ 26623 /* format IPARS_TO_IMPLS_IP_FIELDS_BUSfmt */ 26624 /* nFields */ 38, 26625 /* *fields */ soc_IPARS_TO_IMPLS_IP_FIELDS_BUS_BCM56960_A0fmt_fields, 26626 /* bits */ 209, 26627 /* flags */ 0, 26628 }, 26629 #endif /* chips */ 26630 26631 #if defined(BCM_56840_A0) || defined(BCM_56840_B0) 26632 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_L3_FIELDS_BUSfmt */ 26633 /* format IPARS_TO_IMPLS_L3_FIELDS_BUSfmt */ 26634 /* nFields */ 1, 26635 /* *fields */ soc_IPARS_TO_IMPLS_L3_FIELDS_BUSfmt_fields, 26636 /* bits */ 208, 26637 /* flags */ 0, 26638 }, 26639 #endif /* chips */ 26640 26641 #if defined(BCM_56260_A0) 26642 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_L3_FIELDS_BUS_BCM56260_A0fmt */ 26643 /* format IPARS_TO_IMPLS_L3_FIELDS_BUSfmt */ 26644 /* nFields */ 4, 26645 /* *fields */ soc_IPARS_TO_IMPLS_L3_FIELDS_BUS_BCM56260_A0fmt_fields, 26646 /* bits */ 208, 26647 /* flags */ 0, 26648 }, 26649 #endif /* chips */ 26650 26651 #if defined(BCM_56260_B0) 26652 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_L3_FIELDS_BUS_BCM56260_B0fmt */ 26653 /* format IPARS_TO_IMPLS_L3_FIELDS_BUSfmt */ 26654 /* nFields */ 4, 26655 /* *fields */ soc_IPARS_TO_IMPLS_L3_FIELDS_BUS_BCM56260_A0fmt_fields, 26656 /* bits */ 208, 26657 /* flags */ 0, 26658 }, 26659 #endif /* chips */ 26660 26661 #if defined(BCM_56270_A0) 26662 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_L3_FIELDS_BUS_BCM56270_A0fmt */ 26663 /* format IPARS_TO_IMPLS_L3_FIELDS_BUSfmt */ 26664 /* nFields */ 4, 26665 /* *fields */ soc_IPARS_TO_IMPLS_L3_FIELDS_BUS_BCM56260_A0fmt_fields, 26666 /* bits */ 208, 26667 /* flags */ 0, 26668 }, 26669 #endif /* chips */ 26670 26671 #if defined(BCM_56340_A0) 26672 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_L3_FIELDS_BUS_BCM56340_A0fmt */ 26673 /* format IPARS_TO_IMPLS_L3_FIELDS_BUSfmt */ 26674 /* nFields */ 4, 26675 /* *fields */ soc_IPARS_TO_IMPLS_L3_FIELDS_BUS_BCM56640_A0fmt_fields, 26676 /* bits */ 209, 26677 /* flags */ 0, 26678 }, 26679 #endif /* chips */ 26680 26681 #if defined(BCM_56370_A0) 26682 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_L3_FIELDS_BUS_BCM56370_A0fmt */ 26683 /* format IPARS_TO_IMPLS_L3_FIELDS_BUSfmt */ 26684 /* nFields */ 1, 26685 /* *fields */ soc_IPARS_TO_IMPLS_L3_FIELDS_BUS_BCM56960_A0fmt_fields, 26686 /* bits */ 209, 26687 /* flags */ 0, 26688 }, 26689 #endif /* chips */ 26690 26691 #if defined(BCM_56440_A0) 26692 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_L3_FIELDS_BUS_BCM56440_A0fmt */ 26693 /* format IPARS_TO_IMPLS_L3_FIELDS_BUSfmt */ 26694 /* nFields */ 2, 26695 /* *fields */ soc_IPARS_TO_IMPLS_L3_FIELDS_BUS_BCM56440_A0fmt_fields, 26696 /* bits */ 208, 26697 /* flags */ 0, 26698 }, 26699 #endif /* chips */ 26700 26701 #if defined(BCM_56440_B0) 26702 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_L3_FIELDS_BUS_BCM56440_B0fmt */ 26703 /* format IPARS_TO_IMPLS_L3_FIELDS_BUSfmt */ 26704 /* nFields */ 2, 26705 /* *fields */ soc_IPARS_TO_IMPLS_L3_FIELDS_BUS_BCM56440_A0fmt_fields, 26706 /* bits */ 208, 26707 /* flags */ 0, 26708 }, 26709 #endif /* chips */ 26710 26711 #if defined(BCM_56450_A0) 26712 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_L3_FIELDS_BUS_BCM56450_A0fmt */ 26713 /* format IPARS_TO_IMPLS_L3_FIELDS_BUSfmt */ 26714 /* nFields */ 4, 26715 /* *fields */ soc_IPARS_TO_IMPLS_L3_FIELDS_BUS_BCM56450_A0fmt_fields, 26716 /* bits */ 208, 26717 /* flags */ 0, 26718 }, 26719 #endif /* chips */ 26720 26721 #if defined(BCM_56450_B0) 26722 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_L3_FIELDS_BUS_BCM56450_B0fmt */ 26723 /* format IPARS_TO_IMPLS_L3_FIELDS_BUSfmt */ 26724 /* nFields */ 4, 26725 /* *fields */ soc_IPARS_TO_IMPLS_L3_FIELDS_BUS_BCM56450_A0fmt_fields, 26726 /* bits */ 208, 26727 /* flags */ 0, 26728 }, 26729 #endif /* chips */ 26730 26731 #if defined(BCM_56450_B1) 26732 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_L3_FIELDS_BUS_BCM56450_B1fmt */ 26733 /* format IPARS_TO_IMPLS_L3_FIELDS_BUSfmt */ 26734 /* nFields */ 4, 26735 /* *fields */ soc_IPARS_TO_IMPLS_L3_FIELDS_BUS_BCM56450_A0fmt_fields, 26736 /* bits */ 208, 26737 /* flags */ 0, 26738 }, 26739 #endif /* chips */ 26740 26741 #if defined(BCM_56560_A0) 26742 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_L3_FIELDS_BUS_BCM56560_A0fmt */ 26743 /* format IPARS_TO_IMPLS_L3_FIELDS_BUSfmt */ 26744 /* nFields */ 1, 26745 /* *fields */ soc_IPARS_TO_IMPLS_L3_FIELDS_BUS_BCM56960_A0fmt_fields, 26746 /* bits */ 209, 26747 /* flags */ 0, 26748 }, 26749 #endif /* chips */ 26750 26751 #if defined(BCM_56560_B0) 26752 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_L3_FIELDS_BUS_BCM56560_B0fmt */ 26753 /* format IPARS_TO_IMPLS_L3_FIELDS_BUSfmt */ 26754 /* nFields */ 1, 26755 /* *fields */ soc_IPARS_TO_IMPLS_L3_FIELDS_BUS_BCM56960_A0fmt_fields, 26756 /* bits */ 209, 26757 /* flags */ 0, 26758 }, 26759 #endif /* chips */ 26760 26761 #if defined(BCM_56640_A0) 26762 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_L3_FIELDS_BUS_BCM56640_A0fmt */ 26763 /* format IPARS_TO_IMPLS_L3_FIELDS_BUSfmt */ 26764 /* nFields */ 4, 26765 /* *fields */ soc_IPARS_TO_IMPLS_L3_FIELDS_BUS_BCM56640_A0fmt_fields, 26766 /* bits */ 209, 26767 /* flags */ 0, 26768 }, 26769 #endif /* chips */ 26770 26771 #if defined(BCM_56670_A0) 26772 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_L3_FIELDS_BUS_BCM56670_A0fmt */ 26773 /* format IPARS_TO_IMPLS_L3_FIELDS_BUSfmt */ 26774 /* nFields */ 1, 26775 /* *fields */ soc_IPARS_TO_IMPLS_L3_FIELDS_BUS_BCM56960_A0fmt_fields, 26776 /* bits */ 209, 26777 /* flags */ 0, 26778 }, 26779 #endif /* chips */ 26780 26781 #if defined(BCM_56670_B0) 26782 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_L3_FIELDS_BUS_BCM56670_B0fmt */ 26783 /* format IPARS_TO_IMPLS_L3_FIELDS_BUSfmt */ 26784 /* nFields */ 1, 26785 /* *fields */ soc_IPARS_TO_IMPLS_L3_FIELDS_BUS_BCM56960_A0fmt_fields, 26786 /* bits */ 209, 26787 /* flags */ 0, 26788 }, 26789 #endif /* chips */ 26790 26791 #if defined(BCM_56770_A0) 26792 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_L3_FIELDS_BUS_BCM56770_A0fmt */ 26793 /* format IPARS_TO_IMPLS_L3_FIELDS_BUSfmt */ 26794 /* nFields */ 1, 26795 /* *fields */ soc_IPARS_TO_IMPLS_L3_FIELDS_BUS_BCM56960_A0fmt_fields, 26796 /* bits */ 209, 26797 /* flags */ 0, 26798 }, 26799 #endif /* chips */ 26800 26801 #if defined(BCM_56850_A0) 26802 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_L3_FIELDS_BUS_BCM56850_A0fmt */ 26803 /* format IPARS_TO_IMPLS_L3_FIELDS_BUSfmt */ 26804 /* nFields */ 1, 26805 /* *fields */ soc_IPARS_TO_IMPLS_L3_FIELDS_BUS_BCM56850_A0fmt_fields, 26806 /* bits */ 209, 26807 /* flags */ 0, 26808 }, 26809 #endif /* chips */ 26810 26811 #if defined(BCM_56860_A0) 26812 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_L3_FIELDS_BUS_BCM56860_A0fmt */ 26813 /* format IPARS_TO_IMPLS_L3_FIELDS_BUSfmt */ 26814 /* nFields */ 1, 26815 /* *fields */ soc_IPARS_TO_IMPLS_L3_FIELDS_BUS_BCM56850_A0fmt_fields, 26816 /* bits */ 209, 26817 /* flags */ 0, 26818 }, 26819 #endif /* chips */ 26820 26821 #if defined(BCM_56870_A0) 26822 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_L3_FIELDS_BUS_BCM56870_A0fmt */ 26823 /* format IPARS_TO_IMPLS_L3_FIELDS_BUSfmt */ 26824 /* nFields */ 1, 26825 /* *fields */ soc_IPARS_TO_IMPLS_L3_FIELDS_BUS_BCM56960_A0fmt_fields, 26826 /* bits */ 209, 26827 /* flags */ 0, 26828 }, 26829 #endif /* chips */ 26830 26831 #if defined(BCM_56960_A0) 26832 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_L3_FIELDS_BUS_BCM56960_A0fmt */ 26833 /* format IPARS_TO_IMPLS_L3_FIELDS_BUSfmt */ 26834 /* nFields */ 1, 26835 /* *fields */ soc_IPARS_TO_IMPLS_L3_FIELDS_BUS_BCM56960_A0fmt_fields, 26836 /* bits */ 209, 26837 /* flags */ 0, 26838 }, 26839 #endif /* chips */ 26840 26841 #if defined(BCM_56965_A0) 26842 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_L3_FIELDS_BUS_BCM56965_A0fmt */ 26843 /* format IPARS_TO_IMPLS_L3_FIELDS_BUSfmt */ 26844 /* nFields */ 1, 26845 /* *fields */ soc_IPARS_TO_IMPLS_L3_FIELDS_BUS_BCM56960_A0fmt_fields, 26846 /* bits */ 209, 26847 /* flags */ 0, 26848 }, 26849 #endif /* chips */ 26850 26851 #if defined(BCM_56970_A0) 26852 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_L3_FIELDS_BUS_BCM56970_A0fmt */ 26853 /* format IPARS_TO_IMPLS_L3_FIELDS_BUSfmt */ 26854 /* nFields */ 1, 26855 /* *fields */ soc_IPARS_TO_IMPLS_L3_FIELDS_BUS_BCM56960_A0fmt_fields, 26856 /* bits */ 209, 26857 /* flags */ 0, 26858 }, 26859 #endif /* chips */ 26860 26861 #if defined(BCM_56980_A0) 26862 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_L3_FIELDS_BUS_BCM56980_A0fmt */ 26863 /* format IPARS_TO_IMPLS_L3_FIELDS_BUSfmt */ 26864 /* nFields */ 3, 26865 /* *fields */ soc_IPARS_TO_IMPLS_L3_FIELDS_BUS_BCM56980_A0fmt_fields, 26866 /* bits */ 209, 26867 /* flags */ 0, 26868 }, 26869 #endif /* chips */ 26870 26871 #if defined(BCM_56980_B0) 26872 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_L3_FIELDS_BUS_BCM56980_B0fmt */ 26873 /* format IPARS_TO_IMPLS_L3_FIELDS_BUSfmt */ 26874 /* nFields */ 3, 26875 /* *fields */ soc_IPARS_TO_IMPLS_L3_FIELDS_BUS_BCM56980_A0fmt_fields, 26876 /* bits */ 209, 26877 /* flags */ 0, 26878 }, 26879 #endif /* chips */ 26880 26881 #if defined(BCM_56840_A0) 26882 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_OAM_FIELDS_BUSfmt */ 26883 /* format IPARS_TO_IMPLS_OAM_FIELDS_BUSfmt */ 26884 /* nFields */ 0, 26885 /* *fields */ soc_IPARS_TO_IMPLS_OAM_FIELDS_BUSfmt_fields, 26886 /* bits */ 1, 26887 /* flags */ 0, 26888 }, 26889 #endif /* chips */ 26890 26891 #if defined(BCM_56260_A0) 26892 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_OAM_FIELDS_BUS_BCM56260_A0fmt */ 26893 /* format IPARS_TO_IMPLS_OAM_FIELDS_BUSfmt */ 26894 /* nFields */ 22, 26895 /* *fields */ soc_IPARS_TO_IMPLS_OAM_FIELDS_BUS_BCM56260_A0fmt_fields, 26896 /* bits */ 208, 26897 /* flags */ 0, 26898 }, 26899 #endif /* chips */ 26900 26901 #if defined(BCM_56260_B0) 26902 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_OAM_FIELDS_BUS_BCM56260_B0fmt */ 26903 /* format IPARS_TO_IMPLS_OAM_FIELDS_BUSfmt */ 26904 /* nFields */ 22, 26905 /* *fields */ soc_IPARS_TO_IMPLS_OAM_FIELDS_BUS_BCM56260_A0fmt_fields, 26906 /* bits */ 208, 26907 /* flags */ 0, 26908 }, 26909 #endif /* chips */ 26910 26911 #if defined(BCM_56270_A0) 26912 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_OAM_FIELDS_BUS_BCM56270_A0fmt */ 26913 /* format IPARS_TO_IMPLS_OAM_FIELDS_BUSfmt */ 26914 /* nFields */ 22, 26915 /* *fields */ soc_IPARS_TO_IMPLS_OAM_FIELDS_BUS_BCM56260_A0fmt_fields, 26916 /* bits */ 208, 26917 /* flags */ 0, 26918 }, 26919 #endif /* chips */ 26920 26921 #if defined(BCM_56340_A0) 26922 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_OAM_FIELDS_BUS_BCM56340_A0fmt */ 26923 /* format IPARS_TO_IMPLS_OAM_FIELDS_BUSfmt */ 26924 /* nFields */ 22, 26925 /* *fields */ soc_IPARS_TO_IMPLS_OAM_FIELDS_BUS_BCM56640_A0fmt_fields, 26926 /* bits */ 209, 26927 /* flags */ 0, 26928 }, 26929 #endif /* chips */ 26930 26931 #if defined(BCM_56440_A0) 26932 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_OAM_FIELDS_BUS_BCM56440_A0fmt */ 26933 /* format IPARS_TO_IMPLS_OAM_FIELDS_BUSfmt */ 26934 /* nFields */ 21, 26935 /* *fields */ soc_IPARS_TO_IMPLS_OAM_FIELDS_BUS_BCM56440_A0fmt_fields, 26936 /* bits */ 71, 26937 /* flags */ 0, 26938 }, 26939 #endif /* chips */ 26940 26941 #if defined(BCM_56440_B0) 26942 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_OAM_FIELDS_BUS_BCM56440_B0fmt */ 26943 /* format IPARS_TO_IMPLS_OAM_FIELDS_BUSfmt */ 26944 /* nFields */ 21, 26945 /* *fields */ soc_IPARS_TO_IMPLS_OAM_FIELDS_BUS_BCM56440_A0fmt_fields, 26946 /* bits */ 71, 26947 /* flags */ 0, 26948 }, 26949 #endif /* chips */ 26950 26951 #if defined(BCM_56450_A0) 26952 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_OAM_FIELDS_BUS_BCM56450_A0fmt */ 26953 /* format IPARS_TO_IMPLS_OAM_FIELDS_BUSfmt */ 26954 /* nFields */ 22, 26955 /* *fields */ soc_IPARS_TO_IMPLS_OAM_FIELDS_BUS_BCM56450_A0fmt_fields, 26956 /* bits */ 208, 26957 /* flags */ 0, 26958 }, 26959 #endif /* chips */ 26960 26961 #if defined(BCM_56450_B0) 26962 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_OAM_FIELDS_BUS_BCM56450_B0fmt */ 26963 /* format IPARS_TO_IMPLS_OAM_FIELDS_BUSfmt */ 26964 /* nFields */ 22, 26965 /* *fields */ soc_IPARS_TO_IMPLS_OAM_FIELDS_BUS_BCM56450_A0fmt_fields, 26966 /* bits */ 208, 26967 /* flags */ 0, 26968 }, 26969 #endif /* chips */ 26970 26971 #if defined(BCM_56450_B1) 26972 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_OAM_FIELDS_BUS_BCM56450_B1fmt */ 26973 /* format IPARS_TO_IMPLS_OAM_FIELDS_BUSfmt */ 26974 /* nFields */ 22, 26975 /* *fields */ soc_IPARS_TO_IMPLS_OAM_FIELDS_BUS_BCM56450_A0fmt_fields, 26976 /* bits */ 208, 26977 /* flags */ 0, 26978 }, 26979 #endif /* chips */ 26980 26981 #if defined(BCM_56560_A0) 26982 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_OAM_FIELDS_BUS_BCM56560_A0fmt */ 26983 /* format IPARS_TO_IMPLS_OAM_FIELDS_BUSfmt */ 26984 /* nFields */ 0, 26985 /* *fields */ soc_IPARS_TO_IMPLS_OAM_FIELDS_BUS_BCM56560_A0fmt_fields, 26986 /* bits */ 1, 26987 /* flags */ 0, 26988 }, 26989 #endif /* chips */ 26990 26991 #if defined(BCM_56560_B0) 26992 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_OAM_FIELDS_BUS_BCM56560_B0fmt */ 26993 /* format IPARS_TO_IMPLS_OAM_FIELDS_BUSfmt */ 26994 /* nFields */ 0, 26995 /* *fields */ soc_IPARS_TO_IMPLS_OAM_FIELDS_BUS_BCM56560_A0fmt_fields, 26996 /* bits */ 1, 26997 /* flags */ 0, 26998 }, 26999 #endif /* chips */ 27000 27001 #if defined(BCM_56640_A0) 27002 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_OAM_FIELDS_BUS_BCM56640_A0fmt */ 27003 /* format IPARS_TO_IMPLS_OAM_FIELDS_BUSfmt */ 27004 /* nFields */ 22, 27005 /* *fields */ soc_IPARS_TO_IMPLS_OAM_FIELDS_BUS_BCM56640_A0fmt_fields, 27006 /* bits */ 209, 27007 /* flags */ 0, 27008 }, 27009 #endif /* chips */ 27010 27011 #if defined(BCM_56670_A0) 27012 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_OAM_FIELDS_BUS_BCM56670_A0fmt */ 27013 /* format IPARS_TO_IMPLS_OAM_FIELDS_BUSfmt */ 27014 /* nFields */ 0, 27015 /* *fields */ soc_IPARS_TO_IMPLS_OAM_FIELDS_BUS_BCM56560_A0fmt_fields, 27016 /* bits */ 1, 27017 /* flags */ 0, 27018 }, 27019 #endif /* chips */ 27020 27021 #if defined(BCM_56670_B0) 27022 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_OAM_FIELDS_BUS_BCM56670_B0fmt */ 27023 /* format IPARS_TO_IMPLS_OAM_FIELDS_BUSfmt */ 27024 /* nFields */ 0, 27025 /* *fields */ soc_IPARS_TO_IMPLS_OAM_FIELDS_BUS_BCM56560_A0fmt_fields, 27026 /* bits */ 1, 27027 /* flags */ 0, 27028 }, 27029 #endif /* chips */ 27030 27031 #if defined(BCM_56840_B0) 27032 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_OAM_FIELDS_BUS_BCM56840_B0fmt */ 27033 /* format IPARS_TO_IMPLS_OAM_FIELDS_BUSfmt */ 27034 /* nFields */ 0, 27035 /* *fields */ soc_IPARS_TO_IMPLS_OAM_FIELDS_BUSfmt_fields, 27036 /* bits */ 1, 27037 /* flags */ 0, 27038 }, 27039 #endif /* chips */ 27040 27041 #if defined(BCM_56850_A0) 27042 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_OAM_FIELDS_BUS_BCM56850_A0fmt */ 27043 /* format IPARS_TO_IMPLS_OAM_FIELDS_BUSfmt */ 27044 /* nFields */ 0, 27045 /* *fields */ soc_IPARS_TO_IMPLS_OAM_FIELDS_BUS_BCM56850_A0fmt_fields, 27046 /* bits */ 1, 27047 /* flags */ 0, 27048 }, 27049 #endif /* chips */ 27050 27051 #if defined(BCM_56860_A0) 27052 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_OAM_FIELDS_BUS_BCM56860_A0fmt */ 27053 /* format IPARS_TO_IMPLS_OAM_FIELDS_BUSfmt */ 27054 /* nFields */ 0, 27055 /* *fields */ soc_IPARS_TO_IMPLS_OAM_FIELDS_BUS_BCM56850_A0fmt_fields, 27056 /* bits */ 1, 27057 /* flags */ 0, 27058 }, 27059 #endif /* chips */ 27060 27061 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \ 27062 defined(BCM_56840_A0) || defined(BCM_56840_B0) 27063 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_RTAG7_FIELDS_BUSfmt */ 27064 /* format IPARS_TO_IMPLS_RTAG7_FIELDS_BUSfmt */ 27065 /* nFields */ 11, 27066 /* *fields */ soc_IPARS_TO_IMPLS_RTAG7_FIELDS_BUSfmt_fields, 27067 /* bits */ 208, 27068 /* flags */ 0, 27069 }, 27070 #endif /* chips */ 27071 27072 #if defined(BCM_56260_A0) 27073 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_RTAG7_FIELDS_BUS_BCM56260_A0fmt */ 27074 /* format IPARS_TO_IMPLS_RTAG7_FIELDS_BUSfmt */ 27075 /* nFields */ 12, 27076 /* *fields */ soc_IPARS_TO_IMPLS_RTAG7_FIELDS_BUS_BCM56960_A0fmt_fields, 27077 /* bits */ 209, 27078 /* flags */ 0, 27079 }, 27080 #endif /* chips */ 27081 27082 #if defined(BCM_56260_B0) 27083 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_RTAG7_FIELDS_BUS_BCM56260_B0fmt */ 27084 /* format IPARS_TO_IMPLS_RTAG7_FIELDS_BUSfmt */ 27085 /* nFields */ 12, 27086 /* *fields */ soc_IPARS_TO_IMPLS_RTAG7_FIELDS_BUS_BCM56960_A0fmt_fields, 27087 /* bits */ 209, 27088 /* flags */ 0, 27089 }, 27090 #endif /* chips */ 27091 27092 #if defined(BCM_56270_A0) 27093 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_RTAG7_FIELDS_BUS_BCM56270_A0fmt */ 27094 /* format IPARS_TO_IMPLS_RTAG7_FIELDS_BUSfmt */ 27095 /* nFields */ 12, 27096 /* *fields */ soc_IPARS_TO_IMPLS_RTAG7_FIELDS_BUS_BCM56960_A0fmt_fields, 27097 /* bits */ 209, 27098 /* flags */ 0, 27099 }, 27100 #endif /* chips */ 27101 27102 #if defined(BCM_56340_A0) 27103 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_RTAG7_FIELDS_BUS_BCM56340_A0fmt */ 27104 /* format IPARS_TO_IMPLS_RTAG7_FIELDS_BUSfmt */ 27105 /* nFields */ 12, 27106 /* *fields */ soc_IPARS_TO_IMPLS_RTAG7_FIELDS_BUS_BCM56640_A0fmt_fields, 27107 /* bits */ 209, 27108 /* flags */ 0, 27109 }, 27110 #endif /* chips */ 27111 27112 #if defined(BCM_56370_A0) 27113 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_RTAG7_FIELDS_BUS_BCM56370_A0fmt */ 27114 /* format IPARS_TO_IMPLS_RTAG7_FIELDS_BUSfmt */ 27115 /* nFields */ 12, 27116 /* *fields */ soc_IPARS_TO_IMPLS_RTAG7_FIELDS_BUS_BCM56960_A0fmt_fields, 27117 /* bits */ 209, 27118 /* flags */ 0, 27119 }, 27120 #endif /* chips */ 27121 27122 #if defined(BCM_56450_A0) 27123 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_RTAG7_FIELDS_BUS_BCM56450_A0fmt */ 27124 /* format IPARS_TO_IMPLS_RTAG7_FIELDS_BUSfmt */ 27125 /* nFields */ 12, 27126 /* *fields */ soc_IPARS_TO_IMPLS_RTAG7_FIELDS_BUS_BCM56640_A0fmt_fields, 27127 /* bits */ 209, 27128 /* flags */ 0, 27129 }, 27130 #endif /* chips */ 27131 27132 #if defined(BCM_56450_B0) 27133 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_RTAG7_FIELDS_BUS_BCM56450_B0fmt */ 27134 /* format IPARS_TO_IMPLS_RTAG7_FIELDS_BUSfmt */ 27135 /* nFields */ 12, 27136 /* *fields */ soc_IPARS_TO_IMPLS_RTAG7_FIELDS_BUS_BCM56640_A0fmt_fields, 27137 /* bits */ 209, 27138 /* flags */ 0, 27139 }, 27140 #endif /* chips */ 27141 27142 #if defined(BCM_56450_B1) 27143 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_RTAG7_FIELDS_BUS_BCM56450_B1fmt */ 27144 /* format IPARS_TO_IMPLS_RTAG7_FIELDS_BUSfmt */ 27145 /* nFields */ 12, 27146 /* *fields */ soc_IPARS_TO_IMPLS_RTAG7_FIELDS_BUS_BCM56640_A0fmt_fields, 27147 /* bits */ 209, 27148 /* flags */ 0, 27149 }, 27150 #endif /* chips */ 27151 27152 #if defined(BCM_56560_A0) 27153 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_RTAG7_FIELDS_BUS_BCM56560_A0fmt */ 27154 /* format IPARS_TO_IMPLS_RTAG7_FIELDS_BUSfmt */ 27155 /* nFields */ 12, 27156 /* *fields */ soc_IPARS_TO_IMPLS_RTAG7_FIELDS_BUS_BCM56960_A0fmt_fields, 27157 /* bits */ 209, 27158 /* flags */ 0, 27159 }, 27160 #endif /* chips */ 27161 27162 #if defined(BCM_56560_B0) 27163 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_RTAG7_FIELDS_BUS_BCM56560_B0fmt */ 27164 /* format IPARS_TO_IMPLS_RTAG7_FIELDS_BUSfmt */ 27165 /* nFields */ 12, 27166 /* *fields */ soc_IPARS_TO_IMPLS_RTAG7_FIELDS_BUS_BCM56960_A0fmt_fields, 27167 /* bits */ 209, 27168 /* flags */ 0, 27169 }, 27170 #endif /* chips */ 27171 27172 #if defined(BCM_56640_A0) 27173 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_RTAG7_FIELDS_BUS_BCM56640_A0fmt */ 27174 /* format IPARS_TO_IMPLS_RTAG7_FIELDS_BUSfmt */ 27175 /* nFields */ 12, 27176 /* *fields */ soc_IPARS_TO_IMPLS_RTAG7_FIELDS_BUS_BCM56640_A0fmt_fields, 27177 /* bits */ 209, 27178 /* flags */ 0, 27179 }, 27180 #endif /* chips */ 27181 27182 #if defined(BCM_56670_A0) 27183 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_RTAG7_FIELDS_BUS_BCM56670_A0fmt */ 27184 /* format IPARS_TO_IMPLS_RTAG7_FIELDS_BUSfmt */ 27185 /* nFields */ 12, 27186 /* *fields */ soc_IPARS_TO_IMPLS_RTAG7_FIELDS_BUS_BCM56960_A0fmt_fields, 27187 /* bits */ 209, 27188 /* flags */ 0, 27189 }, 27190 #endif /* chips */ 27191 27192 #if defined(BCM_56670_B0) 27193 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_RTAG7_FIELDS_BUS_BCM56670_B0fmt */ 27194 /* format IPARS_TO_IMPLS_RTAG7_FIELDS_BUSfmt */ 27195 /* nFields */ 12, 27196 /* *fields */ soc_IPARS_TO_IMPLS_RTAG7_FIELDS_BUS_BCM56960_A0fmt_fields, 27197 /* bits */ 209, 27198 /* flags */ 0, 27199 }, 27200 #endif /* chips */ 27201 27202 #if defined(BCM_56770_A0) 27203 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_RTAG7_FIELDS_BUS_BCM56770_A0fmt */ 27204 /* format IPARS_TO_IMPLS_RTAG7_FIELDS_BUSfmt */ 27205 /* nFields */ 12, 27206 /* *fields */ soc_IPARS_TO_IMPLS_RTAG7_FIELDS_BUS_BCM56960_A0fmt_fields, 27207 /* bits */ 209, 27208 /* flags */ 0, 27209 }, 27210 #endif /* chips */ 27211 27212 #if defined(BCM_56850_A0) 27213 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_RTAG7_FIELDS_BUS_BCM56850_A0fmt */ 27214 /* format IPARS_TO_IMPLS_RTAG7_FIELDS_BUSfmt */ 27215 /* nFields */ 12, 27216 /* *fields */ soc_IPARS_TO_IMPLS_RTAG7_FIELDS_BUS_BCM56640_A0fmt_fields, 27217 /* bits */ 209, 27218 /* flags */ 0, 27219 }, 27220 #endif /* chips */ 27221 27222 #if defined(BCM_56860_A0) 27223 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_RTAG7_FIELDS_BUS_BCM56860_A0fmt */ 27224 /* format IPARS_TO_IMPLS_RTAG7_FIELDS_BUSfmt */ 27225 /* nFields */ 12, 27226 /* *fields */ soc_IPARS_TO_IMPLS_RTAG7_FIELDS_BUS_BCM56640_A0fmt_fields, 27227 /* bits */ 209, 27228 /* flags */ 0, 27229 }, 27230 #endif /* chips */ 27231 27232 #if defined(BCM_56870_A0) 27233 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_RTAG7_FIELDS_BUS_BCM56870_A0fmt */ 27234 /* format IPARS_TO_IMPLS_RTAG7_FIELDS_BUSfmt */ 27235 /* nFields */ 12, 27236 /* *fields */ soc_IPARS_TO_IMPLS_RTAG7_FIELDS_BUS_BCM56960_A0fmt_fields, 27237 /* bits */ 209, 27238 /* flags */ 0, 27239 }, 27240 #endif /* chips */ 27241 27242 #if defined(BCM_56960_A0) 27243 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_RTAG7_FIELDS_BUS_BCM56960_A0fmt */ 27244 /* format IPARS_TO_IMPLS_RTAG7_FIELDS_BUSfmt */ 27245 /* nFields */ 12, 27246 /* *fields */ soc_IPARS_TO_IMPLS_RTAG7_FIELDS_BUS_BCM56960_A0fmt_fields, 27247 /* bits */ 209, 27248 /* flags */ 0, 27249 }, 27250 #endif /* chips */ 27251 27252 #if defined(BCM_56965_A0) 27253 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_RTAG7_FIELDS_BUS_BCM56965_A0fmt */ 27254 /* format IPARS_TO_IMPLS_RTAG7_FIELDS_BUSfmt */ 27255 /* nFields */ 12, 27256 /* *fields */ soc_IPARS_TO_IMPLS_RTAG7_FIELDS_BUS_BCM56960_A0fmt_fields, 27257 /* bits */ 209, 27258 /* flags */ 0, 27259 }, 27260 #endif /* chips */ 27261 27262 #if defined(BCM_56970_A0) 27263 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_RTAG7_FIELDS_BUS_BCM56970_A0fmt */ 27264 /* format IPARS_TO_IMPLS_RTAG7_FIELDS_BUSfmt */ 27265 /* nFields */ 12, 27266 /* *fields */ soc_IPARS_TO_IMPLS_RTAG7_FIELDS_BUS_BCM56960_A0fmt_fields, 27267 /* bits */ 209, 27268 /* flags */ 0, 27269 }, 27270 #endif /* chips */ 27271 27272 #if defined(BCM_56980_A0) 27273 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_RTAG7_FIELDS_BUS_BCM56980_A0fmt */ 27274 /* format IPARS_TO_IMPLS_RTAG7_FIELDS_BUSfmt */ 27275 /* nFields */ 12, 27276 /* *fields */ soc_IPARS_TO_IMPLS_RTAG7_FIELDS_BUS_BCM56960_A0fmt_fields, 27277 /* bits */ 209, 27278 /* flags */ 0, 27279 }, 27280 #endif /* chips */ 27281 27282 #if defined(BCM_56980_B0) 27283 { /* SOC_FORMAT_INT_IPARS_TO_IMPLS_RTAG7_FIELDS_BUS_BCM56980_B0fmt */ 27284 /* format IPARS_TO_IMPLS_RTAG7_FIELDS_BUSfmt */ 27285 /* nFields */ 12, 27286 /* *fields */ soc_IPARS_TO_IMPLS_RTAG7_FIELDS_BUS_BCM56960_A0fmt_fields, 27287 /* bits */ 209, 27288 /* flags */ 0, 27289 }, 27290 #endif /* chips */ 27291 27292 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \ 27293 defined(BCM_56840_A0) || defined(BCM_56840_B0) 27294 { /* SOC_FORMAT_INT_IPARS_TO_ISW2_BUSfmt */ 27295 /* format IPARS_TO_ISW2_BUSfmt */ 27296 /* nFields */ 7, 27297 /* *fields */ soc_IPARS_TO_ISW2_BUSfmt_fields, 27298 /* bits */ 33, 27299 /* flags */ 0, 27300 }, 27301 #endif /* chips */ 27302 27303 #if defined(BCM_56450_A0) 27304 { /* SOC_FORMAT_INT_IPARS_TO_ISW2_BUS_BCM56450_A0fmt */ 27305 /* format IPARS_TO_ISW2_BUSfmt */ 27306 /* nFields */ 7, 27307 /* *fields */ soc_IPARS_TO_ISW2_BUS_BCM56450_A0fmt_fields, 27308 /* bits */ 33, 27309 /* flags */ 0, 27310 }, 27311 #endif /* chips */ 27312 27313 #if defined(BCM_56450_B0) 27314 { /* SOC_FORMAT_INT_IPARS_TO_ISW2_BUS_BCM56450_B0fmt */ 27315 /* format IPARS_TO_ISW2_BUSfmt */ 27316 /* nFields */ 7, 27317 /* *fields */ soc_IPARS_TO_ISW2_BUS_BCM56450_A0fmt_fields, 27318 /* bits */ 33, 27319 /* flags */ 0, 27320 }, 27321 #endif /* chips */ 27322 27323 #if defined(BCM_56450_B1) 27324 { /* SOC_FORMAT_INT_IPARS_TO_ISW2_BUS_BCM56450_B1fmt */ 27325 /* format IPARS_TO_ISW2_BUSfmt */ 27326 /* nFields */ 7, 27327 /* *fields */ soc_IPARS_TO_ISW2_BUS_BCM56450_A0fmt_fields, 27328 /* bits */ 33, 27329 /* flags */ 0, 27330 }, 27331 #endif /* chips */ 27332 27333 #if defined(BCM_56960_A0) 27334 { /* SOC_FORMAT_INT_IPARS_TO_ISW2_BUS_BCM56960_A0fmt */ 27335 /* format IPARS_TO_ISW2_BUSfmt */ 27336 /* nFields */ 7, 27337 /* *fields */ soc_IPARS_TO_ISW2_BUS_BCM56960_A0fmt_fields, 27338 /* bits */ 34, 27339 /* flags */ 0, 27340 }, 27341 #endif /* chips */ 27342 27343 #if defined(BCM_56965_A0) 27344 { /* SOC_FORMAT_INT_IPARS_TO_ISW2_BUS_BCM56965_A0fmt */ 27345 /* format IPARS_TO_ISW2_BUSfmt */ 27346 /* nFields */ 7, 27347 /* *fields */ soc_IPARS_TO_ISW2_BUS_BCM56960_A0fmt_fields, 27348 /* bits */ 34, 27349 /* flags */ 0, 27350 }, 27351 #endif /* chips */ 27352 27353 #if defined(BCM_56142_A0) || defined(BCM_56624_A0) || \ 27354 defined(BCM_56624_B0) || defined(BCM_56634_A0) || \ 27355 defined(BCM_56634_B0) || defined(BCM_56680_A0) || \ 27356 defined(BCM_56685_A0) 27357 { /* SOC_FORMAT_INT_IPFIX_DATA_INFOfmt */ 27358 /* format IPFIX_DATA_INFOfmt */ 27359 /* nFields */ 8, 27360 /* *fields */ soc_IPFIX_DATA_INFOfmt_fields, 27361 /* bits */ 34, 27362 /* flags */ 0, 27363 }, 27364 #endif /* chips */ 27365 27366 #if defined(BCM_53400_A0) 27367 { /* SOC_FORMAT_INT_IPFIX_DATA_INFO_BCM53400_A0fmt */ 27368 /* format IPFIX_DATA_INFOfmt */ 27369 /* nFields */ 8, 27370 /* *fields */ soc_IPFIX_DATA_INFO_BCM53400_A0fmt_fields, 27371 /* bits */ 34, 27372 /* flags */ 0, 27373 }, 27374 #endif /* chips */ 27375 27376 #if defined(BCM_53540_A0) 27377 { /* SOC_FORMAT_INT_IPFIX_DATA_INFO_BCM53540_A0fmt */ 27378 /* format IPFIX_DATA_INFOfmt */ 27379 /* nFields */ 8, 27380 /* *fields */ soc_IPFIX_DATA_INFO_BCM53400_A0fmt_fields, 27381 /* bits */ 34, 27382 /* flags */ 0, 27383 }, 27384 #endif /* chips */ 27385 27386 #if defined(BCM_53570_A0) 27387 { /* SOC_FORMAT_INT_IPFIX_DATA_INFO_BCM53570_A0fmt */ 27388 /* format IPFIX_DATA_INFOfmt */ 27389 /* nFields */ 8, 27390 /* *fields */ soc_IPFIX_DATA_INFO_BCM53400_A0fmt_fields, 27391 /* bits */ 34, 27392 /* flags */ 0, 27393 }, 27394 #endif /* chips */ 27395 27396 #if defined(BCM_53570_B0) 27397 { /* SOC_FORMAT_INT_IPFIX_DATA_INFO_BCM53570_B0fmt */ 27398 /* format IPFIX_DATA_INFOfmt */ 27399 /* nFields */ 8, 27400 /* *fields */ soc_IPFIX_DATA_INFO_BCM53400_A0fmt_fields, 27401 /* bits */ 34, 27402 /* flags */ 0, 27403 }, 27404 #endif /* chips */ 27405 27406 #if defined(BCM_56150_A0) 27407 { /* SOC_FORMAT_INT_IPFIX_DATA_INFO_BCM56150_A0fmt */ 27408 /* format IPFIX_DATA_INFOfmt */ 27409 /* nFields */ 8, 27410 /* *fields */ soc_IPFIX_DATA_INFO_BCM56150_A0fmt_fields, 27411 /* bits */ 34, 27412 /* flags */ 0, 27413 }, 27414 #endif /* chips */ 27415 27416 #if defined(BCM_56160_A0) 27417 { /* SOC_FORMAT_INT_IPFIX_DATA_INFO_BCM56160_A0fmt */ 27418 /* format IPFIX_DATA_INFOfmt */ 27419 /* nFields */ 8, 27420 /* *fields */ soc_IPFIX_DATA_INFO_BCM53400_A0fmt_fields, 27421 /* bits */ 34, 27422 /* flags */ 0, 27423 }, 27424 #endif /* chips */ 27425 27426 #if defined(BCM_56334_A0) 27427 { /* SOC_FORMAT_INT_IPFIX_DATA_INFO_BCM56334_A0fmt */ 27428 /* format IPFIX_DATA_INFOfmt */ 27429 /* nFields */ 8, 27430 /* *fields */ soc_IPFIX_DATA_INFOfmt_fields, 27431 /* bits */ 34, 27432 /* flags */ 0, 27433 }, 27434 #endif /* chips */ 27435 27436 #if defined(BCM_56334_B0) 27437 { /* SOC_FORMAT_INT_IPFIX_DATA_INFO_BCM56334_B0fmt */ 27438 /* format IPFIX_DATA_INFOfmt */ 27439 /* nFields */ 8, 27440 /* *fields */ soc_IPFIX_DATA_INFOfmt_fields, 27441 /* bits */ 34, 27442 /* flags */ 0, 27443 }, 27444 #endif /* chips */ 27445 27446 #if defined(BCM_56524_A0) 27447 { /* SOC_FORMAT_INT_IPFIX_DATA_INFO_BCM56524_A0fmt */ 27448 /* format IPFIX_DATA_INFOfmt */ 27449 /* nFields */ 8, 27450 /* *fields */ soc_IPFIX_DATA_INFOfmt_fields, 27451 /* bits */ 34, 27452 /* flags */ 0, 27453 }, 27454 #endif /* chips */ 27455 27456 #if defined(BCM_56524_B0) 27457 { /* SOC_FORMAT_INT_IPFIX_DATA_INFO_BCM56524_B0fmt */ 27458 /* format IPFIX_DATA_INFOfmt */ 27459 /* nFields */ 8, 27460 /* *fields */ soc_IPFIX_DATA_INFOfmt_fields, 27461 /* bits */ 34, 27462 /* flags */ 0, 27463 }, 27464 #endif /* chips */ 27465 27466 #if defined(BCM_56640_A0) 27467 { /* SOC_FORMAT_INT_IPFIX_DATA_INFO_BCM56640_A0fmt */ 27468 /* format IPFIX_DATA_INFOfmt */ 27469 /* nFields */ 8, 27470 /* *fields */ soc_IPFIX_DATA_INFO_BCM56640_A0fmt_fields, 27471 /* bits */ 36, 27472 /* flags */ 0, 27473 }, 27474 #endif /* chips */ 27475 27476 #if defined(BCM_56680_B0) 27477 { /* SOC_FORMAT_INT_IPFIX_DATA_INFO_BCM56680_B0fmt */ 27478 /* format IPFIX_DATA_INFOfmt */ 27479 /* nFields */ 8, 27480 /* *fields */ soc_IPFIX_DATA_INFOfmt_fields, 27481 /* bits */ 34, 27482 /* flags */ 0, 27483 }, 27484 #endif /* chips */ 27485 27486 #if defined(BCM_56685_B0) 27487 { /* SOC_FORMAT_INT_IPFIX_DATA_INFO_BCM56685_B0fmt */ 27488 /* format IPFIX_DATA_INFOfmt */ 27489 /* nFields */ 8, 27490 /* *fields */ soc_IPFIX_DATA_INFOfmt_fields, 27491 /* bits */ 34, 27492 /* flags */ 0, 27493 }, 27494 #endif /* chips */ 27495 27496 #if defined(BCM_56340_A0) || defined(BCM_56640_A0) 27497 { /* SOC_FORMAT_INT_IPFIX_FLOW_COV_DEFSfmt */ 27498 /* format IPFIX_FLOW_COV_DEFSfmt */ 27499 /* nFields */ 7, 27500 /* *fields */ soc_IPFIX_FLOW_COV_DEFSfmt_fields, 27501 /* bits */ 16, 27502 /* flags */ 0, 27503 }, 27504 #endif /* chips */ 27505 27506 #if defined(BCM_56142_A0) || defined(BCM_56624_A0) || \ 27507 defined(BCM_56624_B0) || defined(BCM_56680_A0) || \ 27508 defined(BCM_56680_B0) 27509 { /* SOC_FORMAT_INT_IPFIX_IPV4_KEYfmt */ 27510 /* format IPFIX_IPV4_KEYfmt */ 27511 /* nFields */ 9, 27512 /* *fields */ soc_IPFIX_IPV4_KEYfmt_fields, 27513 /* bits */ 128, 27514 /* flags */ 0, 27515 }, 27516 #endif /* chips */ 27517 27518 #if defined(BCM_53400_A0) 27519 { /* SOC_FORMAT_INT_IPFIX_IPV4_KEY_BCM53400_A0fmt */ 27520 /* format IPFIX_IPV4_KEYfmt */ 27521 /* nFields */ 9, 27522 /* *fields */ soc_IPFIX_IPV4_KEY_BCM53400_A0fmt_fields, 27523 /* bits */ 128, 27524 /* flags */ 0, 27525 }, 27526 #endif /* chips */ 27527 27528 #if defined(BCM_53540_A0) 27529 { /* SOC_FORMAT_INT_IPFIX_IPV4_KEY_BCM53540_A0fmt */ 27530 /* format IPFIX_IPV4_KEYfmt */ 27531 /* nFields */ 9, 27532 /* *fields */ soc_IPFIX_IPV4_KEY_BCM53400_A0fmt_fields, 27533 /* bits */ 128, 27534 /* flags */ 0, 27535 }, 27536 #endif /* chips */ 27537 27538 #if defined(BCM_53570_A0) 27539 { /* SOC_FORMAT_INT_IPFIX_IPV4_KEY_BCM53570_A0fmt */ 27540 /* format IPFIX_IPV4_KEYfmt */ 27541 /* nFields */ 9, 27542 /* *fields */ soc_IPFIX_IPV4_KEY_BCM53400_A0fmt_fields, 27543 /* bits */ 128, 27544 /* flags */ 0, 27545 }, 27546 #endif /* chips */ 27547 27548 #if defined(BCM_53570_B0) 27549 { /* SOC_FORMAT_INT_IPFIX_IPV4_KEY_BCM53570_B0fmt */ 27550 /* format IPFIX_IPV4_KEYfmt */ 27551 /* nFields */ 9, 27552 /* *fields */ soc_IPFIX_IPV4_KEY_BCM53400_A0fmt_fields, 27553 /* bits */ 128, 27554 /* flags */ 0, 27555 }, 27556 #endif /* chips */ 27557 27558 #if defined(BCM_56150_A0) 27559 { /* SOC_FORMAT_INT_IPFIX_IPV4_KEY_BCM56150_A0fmt */ 27560 /* format IPFIX_IPV4_KEYfmt */ 27561 /* nFields */ 9, 27562 /* *fields */ soc_IPFIX_IPV4_KEY_BCM56150_A0fmt_fields, 27563 /* bits */ 128, 27564 /* flags */ 0, 27565 }, 27566 #endif /* chips */ 27567 27568 #if defined(BCM_56160_A0) 27569 { /* SOC_FORMAT_INT_IPFIX_IPV4_KEY_BCM56160_A0fmt */ 27570 /* format IPFIX_IPV4_KEYfmt */ 27571 /* nFields */ 9, 27572 /* *fields */ soc_IPFIX_IPV4_KEY_BCM53400_A0fmt_fields, 27573 /* bits */ 128, 27574 /* flags */ 0, 27575 }, 27576 #endif /* chips */ 27577 27578 #if defined(BCM_56334_A0) 27579 { /* SOC_FORMAT_INT_IPFIX_IPV4_KEY_BCM56334_A0fmt */ 27580 /* format IPFIX_IPV4_KEYfmt */ 27581 /* nFields */ 9, 27582 /* *fields */ soc_IPFIX_IPV4_KEYfmt_fields, 27583 /* bits */ 128, 27584 /* flags */ 0, 27585 }, 27586 #endif /* chips */ 27587 27588 #if defined(BCM_56334_B0) 27589 { /* SOC_FORMAT_INT_IPFIX_IPV4_KEY_BCM56334_B0fmt */ 27590 /* format IPFIX_IPV4_KEYfmt */ 27591 /* nFields */ 9, 27592 /* *fields */ soc_IPFIX_IPV4_KEYfmt_fields, 27593 /* bits */ 128, 27594 /* flags */ 0, 27595 }, 27596 #endif /* chips */ 27597 27598 #if defined(BCM_56524_A0) 27599 { /* SOC_FORMAT_INT_IPFIX_IPV4_KEY_BCM56524_A0fmt */ 27600 /* format IPFIX_IPV4_KEYfmt */ 27601 /* nFields */ 9, 27602 /* *fields */ soc_IPFIX_IPV4_KEY_BCM56634_A0fmt_fields, 27603 /* bits */ 133, 27604 /* flags */ 0, 27605 }, 27606 #endif /* chips */ 27607 27608 #if defined(BCM_56524_B0) 27609 { /* SOC_FORMAT_INT_IPFIX_IPV4_KEY_BCM56524_B0fmt */ 27610 /* format IPFIX_IPV4_KEYfmt */ 27611 /* nFields */ 9, 27612 /* *fields */ soc_IPFIX_IPV4_KEY_BCM56634_A0fmt_fields, 27613 /* bits */ 133, 27614 /* flags */ 0, 27615 }, 27616 #endif /* chips */ 27617 27618 #if defined(BCM_56634_A0) 27619 { /* SOC_FORMAT_INT_IPFIX_IPV4_KEY_BCM56634_A0fmt */ 27620 /* format IPFIX_IPV4_KEYfmt */ 27621 /* nFields */ 9, 27622 /* *fields */ soc_IPFIX_IPV4_KEY_BCM56634_A0fmt_fields, 27623 /* bits */ 133, 27624 /* flags */ 0, 27625 }, 27626 #endif /* chips */ 27627 27628 #if defined(BCM_56634_B0) 27629 { /* SOC_FORMAT_INT_IPFIX_IPV4_KEY_BCM56634_B0fmt */ 27630 /* format IPFIX_IPV4_KEYfmt */ 27631 /* nFields */ 9, 27632 /* *fields */ soc_IPFIX_IPV4_KEY_BCM56634_A0fmt_fields, 27633 /* bits */ 133, 27634 /* flags */ 0, 27635 }, 27636 #endif /* chips */ 27637 27638 #if defined(BCM_56640_A0) 27639 { /* SOC_FORMAT_INT_IPFIX_IPV4_KEY_BCM56640_A0fmt */ 27640 /* format IPFIX_IPV4_KEYfmt */ 27641 /* nFields */ 9, 27642 /* *fields */ soc_IPFIX_IPV4_KEY_BCM56640_A0fmt_fields, 27643 /* bits */ 136, 27644 /* flags */ 0, 27645 }, 27646 #endif /* chips */ 27647 27648 #if defined(BCM_56685_A0) 27649 { /* SOC_FORMAT_INT_IPFIX_IPV4_KEY_BCM56685_A0fmt */ 27650 /* format IPFIX_IPV4_KEYfmt */ 27651 /* nFields */ 9, 27652 /* *fields */ soc_IPFIX_IPV4_KEY_BCM56634_A0fmt_fields, 27653 /* bits */ 133, 27654 /* flags */ 0, 27655 }, 27656 #endif /* chips */ 27657 27658 #if defined(BCM_56685_B0) 27659 { /* SOC_FORMAT_INT_IPFIX_IPV4_KEY_BCM56685_B0fmt */ 27660 /* format IPFIX_IPV4_KEYfmt */ 27661 /* nFields */ 9, 27662 /* *fields */ soc_IPFIX_IPV4_KEY_BCM56634_A0fmt_fields, 27663 /* bits */ 133, 27664 /* flags */ 0, 27665 }, 27666 #endif /* chips */ 27667 27668 #if defined(BCM_56142_A0) || defined(BCM_56624_A0) || \ 27669 defined(BCM_56624_B0) || defined(BCM_56680_A0) 27670 { /* SOC_FORMAT_INT_IPFIX_IPV6_LOWER_KEYfmt */ 27671 /* format IPFIX_IPV6_LOWER_KEYfmt */ 27672 /* nFields */ 10, 27673 /* *fields */ soc_IPFIX_IPV6_LOWER_KEYfmt_fields, 27674 /* bits */ 224, 27675 /* flags */ 0, 27676 }, 27677 #endif /* chips */ 27678 27679 #if defined(BCM_53400_A0) 27680 { /* SOC_FORMAT_INT_IPFIX_IPV6_LOWER_KEY_BCM53400_A0fmt */ 27681 /* format IPFIX_IPV6_LOWER_KEYfmt */ 27682 /* nFields */ 10, 27683 /* *fields */ soc_IPFIX_IPV6_LOWER_KEY_BCM53400_A0fmt_fields, 27684 /* bits */ 224, 27685 /* flags */ 0, 27686 }, 27687 #endif /* chips */ 27688 27689 #if defined(BCM_53540_A0) 27690 { /* SOC_FORMAT_INT_IPFIX_IPV6_LOWER_KEY_BCM53540_A0fmt */ 27691 /* format IPFIX_IPV6_LOWER_KEYfmt */ 27692 /* nFields */ 10, 27693 /* *fields */ soc_IPFIX_IPV6_LOWER_KEY_BCM53400_A0fmt_fields, 27694 /* bits */ 224, 27695 /* flags */ 0, 27696 }, 27697 #endif /* chips */ 27698 27699 #if defined(BCM_53570_A0) 27700 { /* SOC_FORMAT_INT_IPFIX_IPV6_LOWER_KEY_BCM53570_A0fmt */ 27701 /* format IPFIX_IPV6_LOWER_KEYfmt */ 27702 /* nFields */ 10, 27703 /* *fields */ soc_IPFIX_IPV6_LOWER_KEY_BCM53400_A0fmt_fields, 27704 /* bits */ 224, 27705 /* flags */ 0, 27706 }, 27707 #endif /* chips */ 27708 27709 #if defined(BCM_53570_B0) 27710 { /* SOC_FORMAT_INT_IPFIX_IPV6_LOWER_KEY_BCM53570_B0fmt */ 27711 /* format IPFIX_IPV6_LOWER_KEYfmt */ 27712 /* nFields */ 10, 27713 /* *fields */ soc_IPFIX_IPV6_LOWER_KEY_BCM53400_A0fmt_fields, 27714 /* bits */ 224, 27715 /* flags */ 0, 27716 }, 27717 #endif /* chips */ 27718 27719 #if defined(BCM_56150_A0) 27720 { /* SOC_FORMAT_INT_IPFIX_IPV6_LOWER_KEY_BCM56150_A0fmt */ 27721 /* format IPFIX_IPV6_LOWER_KEYfmt */ 27722 /* nFields */ 10, 27723 /* *fields */ soc_IPFIX_IPV6_LOWER_KEY_BCM56150_A0fmt_fields, 27724 /* bits */ 224, 27725 /* flags */ 0, 27726 }, 27727 #endif /* chips */ 27728 27729 #if defined(BCM_56160_A0) 27730 { /* SOC_FORMAT_INT_IPFIX_IPV6_LOWER_KEY_BCM56160_A0fmt */ 27731 /* format IPFIX_IPV6_LOWER_KEYfmt */ 27732 /* nFields */ 10, 27733 /* *fields */ soc_IPFIX_IPV6_LOWER_KEY_BCM53400_A0fmt_fields, 27734 /* bits */ 224, 27735 /* flags */ 0, 27736 }, 27737 #endif /* chips */ 27738 27739 #if defined(BCM_56334_A0) 27740 { /* SOC_FORMAT_INT_IPFIX_IPV6_LOWER_KEY_BCM56334_A0fmt */ 27741 /* format IPFIX_IPV6_LOWER_KEYfmt */ 27742 /* nFields */ 10, 27743 /* *fields */ soc_IPFIX_IPV6_LOWER_KEYfmt_fields, 27744 /* bits */ 224, 27745 /* flags */ 0, 27746 }, 27747 #endif /* chips */ 27748 27749 #if defined(BCM_56334_B0) 27750 { /* SOC_FORMAT_INT_IPFIX_IPV6_LOWER_KEY_BCM56334_B0fmt */ 27751 /* format IPFIX_IPV6_LOWER_KEYfmt */ 27752 /* nFields */ 10, 27753 /* *fields */ soc_IPFIX_IPV6_LOWER_KEYfmt_fields, 27754 /* bits */ 224, 27755 /* flags */ 0, 27756 }, 27757 #endif /* chips */ 27758 27759 #if defined(BCM_56524_A0) 27760 { /* SOC_FORMAT_INT_IPFIX_IPV6_LOWER_KEY_BCM56524_A0fmt */ 27761 /* format IPFIX_IPV6_LOWER_KEYfmt */ 27762 /* nFields */ 10, 27763 /* *fields */ soc_IPFIX_IPV6_LOWER_KEY_BCM56634_A0fmt_fields, 27764 /* bits */ 229, 27765 /* flags */ 0, 27766 }, 27767 #endif /* chips */ 27768 27769 #if defined(BCM_56524_B0) 27770 { /* SOC_FORMAT_INT_IPFIX_IPV6_LOWER_KEY_BCM56524_B0fmt */ 27771 /* format IPFIX_IPV6_LOWER_KEYfmt */ 27772 /* nFields */ 10, 27773 /* *fields */ soc_IPFIX_IPV6_LOWER_KEY_BCM56634_A0fmt_fields, 27774 /* bits */ 229, 27775 /* flags */ 0, 27776 }, 27777 #endif /* chips */ 27778 27779 #if defined(BCM_56634_A0) 27780 { /* SOC_FORMAT_INT_IPFIX_IPV6_LOWER_KEY_BCM56634_A0fmt */ 27781 /* format IPFIX_IPV6_LOWER_KEYfmt */ 27782 /* nFields */ 10, 27783 /* *fields */ soc_IPFIX_IPV6_LOWER_KEY_BCM56634_A0fmt_fields, 27784 /* bits */ 229, 27785 /* flags */ 0, 27786 }, 27787 #endif /* chips */ 27788 27789 #if defined(BCM_56634_B0) 27790 { /* SOC_FORMAT_INT_IPFIX_IPV6_LOWER_KEY_BCM56634_B0fmt */ 27791 /* format IPFIX_IPV6_LOWER_KEYfmt */ 27792 /* nFields */ 10, 27793 /* *fields */ soc_IPFIX_IPV6_LOWER_KEY_BCM56634_A0fmt_fields, 27794 /* bits */ 229, 27795 /* flags */ 0, 27796 }, 27797 #endif /* chips */ 27798 27799 #if defined(BCM_56640_A0) 27800 { /* SOC_FORMAT_INT_IPFIX_IPV6_LOWER_KEY_BCM56640_A0fmt */ 27801 /* format IPFIX_IPV6_LOWER_KEYfmt */ 27802 /* nFields */ 10, 27803 /* *fields */ soc_IPFIX_IPV6_LOWER_KEY_BCM56640_A0fmt_fields, 27804 /* bits */ 232, 27805 /* flags */ 0, 27806 }, 27807 #endif /* chips */ 27808 27809 #if defined(BCM_56680_B0) 27810 { /* SOC_FORMAT_INT_IPFIX_IPV6_LOWER_KEY_BCM56680_B0fmt */ 27811 /* format IPFIX_IPV6_LOWER_KEYfmt */ 27812 /* nFields */ 10, 27813 /* *fields */ soc_IPFIX_IPV6_LOWER_KEYfmt_fields, 27814 /* bits */ 224, 27815 /* flags */ 0, 27816 }, 27817 #endif /* chips */ 27818 27819 #if defined(BCM_56685_A0) 27820 { /* SOC_FORMAT_INT_IPFIX_IPV6_LOWER_KEY_BCM56685_A0fmt */ 27821 /* format IPFIX_IPV6_LOWER_KEYfmt */ 27822 /* nFields */ 10, 27823 /* *fields */ soc_IPFIX_IPV6_LOWER_KEY_BCM56634_A0fmt_fields, 27824 /* bits */ 229, 27825 /* flags */ 0, 27826 }, 27827 #endif /* chips */ 27828 27829 #if defined(BCM_56685_B0) 27830 { /* SOC_FORMAT_INT_IPFIX_IPV6_LOWER_KEY_BCM56685_B0fmt */ 27831 /* format IPFIX_IPV6_LOWER_KEYfmt */ 27832 /* nFields */ 10, 27833 /* *fields */ soc_IPFIX_IPV6_LOWER_KEY_BCM56634_A0fmt_fields, 27834 /* bits */ 229, 27835 /* flags */ 0, 27836 }, 27837 #endif /* chips */ 27838 27839 #if defined(BCM_56142_A0) || defined(BCM_56524_A0) || \ 27840 defined(BCM_56524_B0) || defined(BCM_56624_A0) || \ 27841 defined(BCM_56624_B0) || defined(BCM_56634_B0) || \ 27842 defined(BCM_56680_A0) || defined(BCM_56680_B0) || \ 27843 defined(BCM_56685_A0) || defined(BCM_56685_B0) 27844 { /* SOC_FORMAT_INT_IPFIX_IPV6_UPPER_KEYfmt */ 27845 /* format IPFIX_IPV6_UPPER_KEYfmt */ 27846 /* nFields */ 1, 27847 /* *fields */ soc_IPFIX_IPV6_UPPER_KEYfmt_fields, 27848 /* bits */ 116, 27849 /* flags */ 0, 27850 }, 27851 #endif /* chips */ 27852 27853 #if defined(BCM_53400_A0) 27854 { /* SOC_FORMAT_INT_IPFIX_IPV6_UPPER_KEY_BCM53400_A0fmt */ 27855 /* format IPFIX_IPV6_UPPER_KEYfmt */ 27856 /* nFields */ 1, 27857 /* *fields */ soc_IPFIX_IPV6_UPPER_KEY_BCM53400_A0fmt_fields, 27858 /* bits */ 116, 27859 /* flags */ 0, 27860 }, 27861 #endif /* chips */ 27862 27863 #if defined(BCM_53540_A0) 27864 { /* SOC_FORMAT_INT_IPFIX_IPV6_UPPER_KEY_BCM53540_A0fmt */ 27865 /* format IPFIX_IPV6_UPPER_KEYfmt */ 27866 /* nFields */ 1, 27867 /* *fields */ soc_IPFIX_IPV6_UPPER_KEY_BCM53400_A0fmt_fields, 27868 /* bits */ 116, 27869 /* flags */ 0, 27870 }, 27871 #endif /* chips */ 27872 27873 #if defined(BCM_53570_A0) 27874 { /* SOC_FORMAT_INT_IPFIX_IPV6_UPPER_KEY_BCM53570_A0fmt */ 27875 /* format IPFIX_IPV6_UPPER_KEYfmt */ 27876 /* nFields */ 1, 27877 /* *fields */ soc_IPFIX_IPV6_UPPER_KEY_BCM53400_A0fmt_fields, 27878 /* bits */ 116, 27879 /* flags */ 0, 27880 }, 27881 #endif /* chips */ 27882 27883 #if defined(BCM_53570_B0) 27884 { /* SOC_FORMAT_INT_IPFIX_IPV6_UPPER_KEY_BCM53570_B0fmt */ 27885 /* format IPFIX_IPV6_UPPER_KEYfmt */ 27886 /* nFields */ 1, 27887 /* *fields */ soc_IPFIX_IPV6_UPPER_KEY_BCM53400_A0fmt_fields, 27888 /* bits */ 116, 27889 /* flags */ 0, 27890 }, 27891 #endif /* chips */ 27892 27893 #if defined(BCM_56150_A0) 27894 { /* SOC_FORMAT_INT_IPFIX_IPV6_UPPER_KEY_BCM56150_A0fmt */ 27895 /* format IPFIX_IPV6_UPPER_KEYfmt */ 27896 /* nFields */ 1, 27897 /* *fields */ soc_IPFIX_IPV6_UPPER_KEY_BCM56640_A0fmt_fields, 27898 /* bits */ 116, 27899 /* flags */ 0, 27900 }, 27901 #endif /* chips */ 27902 27903 #if defined(BCM_56160_A0) 27904 { /* SOC_FORMAT_INT_IPFIX_IPV6_UPPER_KEY_BCM56160_A0fmt */ 27905 /* format IPFIX_IPV6_UPPER_KEYfmt */ 27906 /* nFields */ 1, 27907 /* *fields */ soc_IPFIX_IPV6_UPPER_KEY_BCM53400_A0fmt_fields, 27908 /* bits */ 116, 27909 /* flags */ 0, 27910 }, 27911 #endif /* chips */ 27912 27913 #if defined(BCM_56334_A0) 27914 { /* SOC_FORMAT_INT_IPFIX_IPV6_UPPER_KEY_BCM56334_A0fmt */ 27915 /* format IPFIX_IPV6_UPPER_KEYfmt */ 27916 /* nFields */ 1, 27917 /* *fields */ soc_IPFIX_IPV6_UPPER_KEYfmt_fields, 27918 /* bits */ 116, 27919 /* flags */ 0, 27920 }, 27921 #endif /* chips */ 27922 27923 #if defined(BCM_56334_B0) 27924 { /* SOC_FORMAT_INT_IPFIX_IPV6_UPPER_KEY_BCM56334_B0fmt */ 27925 /* format IPFIX_IPV6_UPPER_KEYfmt */ 27926 /* nFields */ 1, 27927 /* *fields */ soc_IPFIX_IPV6_UPPER_KEYfmt_fields, 27928 /* bits */ 116, 27929 /* flags */ 0, 27930 }, 27931 #endif /* chips */ 27932 27933 #if defined(BCM_56634_A0) 27934 { /* SOC_FORMAT_INT_IPFIX_IPV6_UPPER_KEY_BCM56634_A0fmt */ 27935 /* format IPFIX_IPV6_UPPER_KEYfmt */ 27936 /* nFields */ 1, 27937 /* *fields */ soc_IPFIX_IPV6_UPPER_KEYfmt_fields, 27938 /* bits */ 116, 27939 /* flags */ 0, 27940 }, 27941 #endif /* chips */ 27942 27943 #if defined(BCM_56640_A0) 27944 { /* SOC_FORMAT_INT_IPFIX_IPV6_UPPER_KEY_BCM56640_A0fmt */ 27945 /* format IPFIX_IPV6_UPPER_KEYfmt */ 27946 /* nFields */ 1, 27947 /* *fields */ soc_IPFIX_IPV6_UPPER_KEY_BCM56640_A0fmt_fields, 27948 /* bits */ 116, 27949 /* flags */ 0, 27950 }, 27951 #endif /* chips */ 27952 27953 #if defined(BCM_56142_A0) || defined(BCM_56524_B0) || \ 27954 defined(BCM_56624_A0) || defined(BCM_56624_B0) || \ 27955 defined(BCM_56634_A0) || defined(BCM_56680_A0) || \ 27956 defined(BCM_56680_B0) || defined(BCM_56685_A0) || \ 27957 defined(BCM_56685_B0) 27958 { /* SOC_FORMAT_INT_IPFIX_L2_KEYfmt */ 27959 /* format IPFIX_L2_KEYfmt */ 27960 /* nFields */ 7, 27961 /* *fields */ soc_IPFIX_L2_KEYfmt_fields, 27962 /* bits */ 134, 27963 /* flags */ 0, 27964 }, 27965 #endif /* chips */ 27966 27967 #if defined(BCM_53400_A0) 27968 { /* SOC_FORMAT_INT_IPFIX_L2_KEY_BCM53400_A0fmt */ 27969 /* format IPFIX_L2_KEYfmt */ 27970 /* nFields */ 7, 27971 /* *fields */ soc_IPFIX_L2_KEY_BCM53400_A0fmt_fields, 27972 /* bits */ 134, 27973 /* flags */ 0, 27974 }, 27975 #endif /* chips */ 27976 27977 #if defined(BCM_53540_A0) 27978 { /* SOC_FORMAT_INT_IPFIX_L2_KEY_BCM53540_A0fmt */ 27979 /* format IPFIX_L2_KEYfmt */ 27980 /* nFields */ 7, 27981 /* *fields */ soc_IPFIX_L2_KEY_BCM53400_A0fmt_fields, 27982 /* bits */ 134, 27983 /* flags */ 0, 27984 }, 27985 #endif /* chips */ 27986 27987 #if defined(BCM_53570_A0) 27988 { /* SOC_FORMAT_INT_IPFIX_L2_KEY_BCM53570_A0fmt */ 27989 /* format IPFIX_L2_KEYfmt */ 27990 /* nFields */ 7, 27991 /* *fields */ soc_IPFIX_L2_KEY_BCM53400_A0fmt_fields, 27992 /* bits */ 134, 27993 /* flags */ 0, 27994 }, 27995 #endif /* chips */ 27996 27997 #if defined(BCM_53570_B0) 27998 { /* SOC_FORMAT_INT_IPFIX_L2_KEY_BCM53570_B0fmt */ 27999 /* format IPFIX_L2_KEYfmt */ 28000 /* nFields */ 7, 28001 /* *fields */ soc_IPFIX_L2_KEY_BCM53400_A0fmt_fields, 28002 /* bits */ 134, 28003 /* flags */ 0, 28004 }, 28005 #endif /* chips */ 28006 28007 #if defined(BCM_56150_A0) 28008 { /* SOC_FORMAT_INT_IPFIX_L2_KEY_BCM56150_A0fmt */ 28009 /* format IPFIX_L2_KEYfmt */ 28010 /* nFields */ 7, 28011 /* *fields */ soc_IPFIX_L2_KEY_BCM56640_A0fmt_fields, 28012 /* bits */ 134, 28013 /* flags */ 0, 28014 }, 28015 #endif /* chips */ 28016 28017 #if defined(BCM_56160_A0) 28018 { /* SOC_FORMAT_INT_IPFIX_L2_KEY_BCM56160_A0fmt */ 28019 /* format IPFIX_L2_KEYfmt */ 28020 /* nFields */ 7, 28021 /* *fields */ soc_IPFIX_L2_KEY_BCM53400_A0fmt_fields, 28022 /* bits */ 134, 28023 /* flags */ 0, 28024 }, 28025 #endif /* chips */ 28026 28027 #if defined(BCM_56334_A0) 28028 { /* SOC_FORMAT_INT_IPFIX_L2_KEY_BCM56334_A0fmt */ 28029 /* format IPFIX_L2_KEYfmt */ 28030 /* nFields */ 7, 28031 /* *fields */ soc_IPFIX_L2_KEYfmt_fields, 28032 /* bits */ 134, 28033 /* flags */ 0, 28034 }, 28035 #endif /* chips */ 28036 28037 #if defined(BCM_56334_B0) 28038 { /* SOC_FORMAT_INT_IPFIX_L2_KEY_BCM56334_B0fmt */ 28039 /* format IPFIX_L2_KEYfmt */ 28040 /* nFields */ 7, 28041 /* *fields */ soc_IPFIX_L2_KEYfmt_fields, 28042 /* bits */ 134, 28043 /* flags */ 0, 28044 }, 28045 #endif /* chips */ 28046 28047 #if defined(BCM_56524_A0) 28048 { /* SOC_FORMAT_INT_IPFIX_L2_KEY_BCM56524_A0fmt */ 28049 /* format IPFIX_L2_KEYfmt */ 28050 /* nFields */ 7, 28051 /* *fields */ soc_IPFIX_L2_KEYfmt_fields, 28052 /* bits */ 134, 28053 /* flags */ 0, 28054 }, 28055 #endif /* chips */ 28056 28057 #if defined(BCM_56634_B0) 28058 { /* SOC_FORMAT_INT_IPFIX_L2_KEY_BCM56634_B0fmt */ 28059 /* format IPFIX_L2_KEYfmt */ 28060 /* nFields */ 7, 28061 /* *fields */ soc_IPFIX_L2_KEYfmt_fields, 28062 /* bits */ 134, 28063 /* flags */ 0, 28064 }, 28065 #endif /* chips */ 28066 28067 #if defined(BCM_56640_A0) 28068 { /* SOC_FORMAT_INT_IPFIX_L2_KEY_BCM56640_A0fmt */ 28069 /* format IPFIX_L2_KEYfmt */ 28070 /* nFields */ 7, 28071 /* *fields */ soc_IPFIX_L2_KEY_BCM56640_A0fmt_fields, 28072 /* bits */ 134, 28073 /* flags */ 0, 28074 }, 28075 #endif /* chips */ 28076 28077 #if defined(BCM_56340_A0) || defined(BCM_56640_A0) 28078 { /* SOC_FORMAT_INT_IPFIX_SESSION_COV_DEFSfmt */ 28079 /* format IPFIX_SESSION_COV_DEFSfmt */ 28080 /* nFields */ 5, 28081 /* *fields */ soc_IPFIX_SESSION_COV_DEFSfmt_fields, 28082 /* bits */ 17, 28083 /* flags */ 0, 28084 }, 28085 #endif /* chips */ 28086 28087 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \ 28088 defined(BCM_56680_B0) 28089 { /* SOC_FORMAT_INT_IPFIX_SESSION_INFO_ALLfmt */ 28090 /* format IPFIX_SESSION_INFO_ALLfmt */ 28091 /* nFields */ 7, 28092 /* *fields */ soc_IPFIX_SESSION_INFO_ALLfmt_fields, 28093 /* bits */ 95, 28094 /* flags */ 0, 28095 }, 28096 #endif /* chips */ 28097 28098 #if defined(BCM_53400_A0) 28099 { /* SOC_FORMAT_INT_IPFIX_SESSION_INFO_ALL_BCM53400_A0fmt */ 28100 /* format IPFIX_SESSION_INFO_ALLfmt */ 28101 /* nFields */ 7, 28102 /* *fields */ soc_IPFIX_SESSION_INFO_ALL_BCM53400_A0fmt_fields, 28103 /* bits */ 95, 28104 /* flags */ 0, 28105 }, 28106 #endif /* chips */ 28107 28108 #if defined(BCM_53540_A0) 28109 { /* SOC_FORMAT_INT_IPFIX_SESSION_INFO_ALL_BCM53540_A0fmt */ 28110 /* format IPFIX_SESSION_INFO_ALLfmt */ 28111 /* nFields */ 7, 28112 /* *fields */ soc_IPFIX_SESSION_INFO_ALL_BCM53400_A0fmt_fields, 28113 /* bits */ 95, 28114 /* flags */ 0, 28115 }, 28116 #endif /* chips */ 28117 28118 #if defined(BCM_53570_A0) 28119 { /* SOC_FORMAT_INT_IPFIX_SESSION_INFO_ALL_BCM53570_A0fmt */ 28120 /* format IPFIX_SESSION_INFO_ALLfmt */ 28121 /* nFields */ 7, 28122 /* *fields */ soc_IPFIX_SESSION_INFO_ALL_BCM53400_A0fmt_fields, 28123 /* bits */ 95, 28124 /* flags */ 0, 28125 }, 28126 #endif /* chips */ 28127 28128 #if defined(BCM_53570_B0) 28129 { /* SOC_FORMAT_INT_IPFIX_SESSION_INFO_ALL_BCM53570_B0fmt */ 28130 /* format IPFIX_SESSION_INFO_ALLfmt */ 28131 /* nFields */ 7, 28132 /* *fields */ soc_IPFIX_SESSION_INFO_ALL_BCM53400_A0fmt_fields, 28133 /* bits */ 95, 28134 /* flags */ 0, 28135 }, 28136 #endif /* chips */ 28137 28138 #if defined(BCM_56142_A0) 28139 { /* SOC_FORMAT_INT_IPFIX_SESSION_INFO_ALL_BCM56142_A0fmt */ 28140 /* format IPFIX_SESSION_INFO_ALLfmt */ 28141 /* nFields */ 7, 28142 /* *fields */ soc_IPFIX_SESSION_INFO_ALLfmt_fields, 28143 /* bits */ 95, 28144 /* flags */ 0, 28145 }, 28146 #endif /* chips */ 28147 28148 #if defined(BCM_56150_A0) 28149 { /* SOC_FORMAT_INT_IPFIX_SESSION_INFO_ALL_BCM56150_A0fmt */ 28150 /* format IPFIX_SESSION_INFO_ALLfmt */ 28151 /* nFields */ 7, 28152 /* *fields */ soc_IPFIX_SESSION_INFO_ALL_BCM56150_A0fmt_fields, 28153 /* bits */ 95, 28154 /* flags */ 0, 28155 }, 28156 #endif /* chips */ 28157 28158 #if defined(BCM_56160_A0) 28159 { /* SOC_FORMAT_INT_IPFIX_SESSION_INFO_ALL_BCM56160_A0fmt */ 28160 /* format IPFIX_SESSION_INFO_ALLfmt */ 28161 /* nFields */ 7, 28162 /* *fields */ soc_IPFIX_SESSION_INFO_ALL_BCM53400_A0fmt_fields, 28163 /* bits */ 95, 28164 /* flags */ 0, 28165 }, 28166 #endif /* chips */ 28167 28168 #if defined(BCM_56334_A0) 28169 { /* SOC_FORMAT_INT_IPFIX_SESSION_INFO_ALL_BCM56334_A0fmt */ 28170 /* format IPFIX_SESSION_INFO_ALLfmt */ 28171 /* nFields */ 7, 28172 /* *fields */ soc_IPFIX_SESSION_INFO_ALLfmt_fields, 28173 /* bits */ 95, 28174 /* flags */ 0, 28175 }, 28176 #endif /* chips */ 28177 28178 #if defined(BCM_56334_B0) 28179 { /* SOC_FORMAT_INT_IPFIX_SESSION_INFO_ALL_BCM56334_B0fmt */ 28180 /* format IPFIX_SESSION_INFO_ALLfmt */ 28181 /* nFields */ 7, 28182 /* *fields */ soc_IPFIX_SESSION_INFO_ALLfmt_fields, 28183 /* bits */ 95, 28184 /* flags */ 0, 28185 }, 28186 #endif /* chips */ 28187 28188 #if defined(BCM_56524_A0) 28189 { /* SOC_FORMAT_INT_IPFIX_SESSION_INFO_ALL_BCM56524_A0fmt */ 28190 /* format IPFIX_SESSION_INFO_ALLfmt */ 28191 /* nFields */ 8, 28192 /* *fields */ soc_IPFIX_SESSION_INFO_ALL_BCM56634_A0fmt_fields, 28193 /* bits */ 96, 28194 /* flags */ 0, 28195 }, 28196 #endif /* chips */ 28197 28198 #if defined(BCM_56524_B0) 28199 { /* SOC_FORMAT_INT_IPFIX_SESSION_INFO_ALL_BCM56524_B0fmt */ 28200 /* format IPFIX_SESSION_INFO_ALLfmt */ 28201 /* nFields */ 8, 28202 /* *fields */ soc_IPFIX_SESSION_INFO_ALL_BCM56634_A0fmt_fields, 28203 /* bits */ 96, 28204 /* flags */ 0, 28205 }, 28206 #endif /* chips */ 28207 28208 #if defined(BCM_56634_A0) 28209 { /* SOC_FORMAT_INT_IPFIX_SESSION_INFO_ALL_BCM56634_A0fmt */ 28210 /* format IPFIX_SESSION_INFO_ALLfmt */ 28211 /* nFields */ 8, 28212 /* *fields */ soc_IPFIX_SESSION_INFO_ALL_BCM56634_A0fmt_fields, 28213 /* bits */ 96, 28214 /* flags */ 0, 28215 }, 28216 #endif /* chips */ 28217 28218 #if defined(BCM_56634_B0) 28219 { /* SOC_FORMAT_INT_IPFIX_SESSION_INFO_ALL_BCM56634_B0fmt */ 28220 /* format IPFIX_SESSION_INFO_ALLfmt */ 28221 /* nFields */ 8, 28222 /* *fields */ soc_IPFIX_SESSION_INFO_ALL_BCM56634_A0fmt_fields, 28223 /* bits */ 96, 28224 /* flags */ 0, 28225 }, 28226 #endif /* chips */ 28227 28228 #if defined(BCM_56640_A0) 28229 { /* SOC_FORMAT_INT_IPFIX_SESSION_INFO_ALL_BCM56640_A0fmt */ 28230 /* format IPFIX_SESSION_INFO_ALLfmt */ 28231 /* nFields */ 8, 28232 /* *fields */ soc_IPFIX_SESSION_INFO_ALL_BCM56640_A0fmt_fields, 28233 /* bits */ 96, 28234 /* flags */ 0, 28235 }, 28236 #endif /* chips */ 28237 28238 #if defined(BCM_56680_A0) 28239 { /* SOC_FORMAT_INT_IPFIX_SESSION_INFO_ALL_BCM56680_A0fmt */ 28240 /* format IPFIX_SESSION_INFO_ALLfmt */ 28241 /* nFields */ 7, 28242 /* *fields */ soc_IPFIX_SESSION_INFO_ALLfmt_fields, 28243 /* bits */ 95, 28244 /* flags */ 0, 28245 }, 28246 #endif /* chips */ 28247 28248 #if defined(BCM_56685_A0) 28249 { /* SOC_FORMAT_INT_IPFIX_SESSION_INFO_ALL_BCM56685_A0fmt */ 28250 /* format IPFIX_SESSION_INFO_ALLfmt */ 28251 /* nFields */ 8, 28252 /* *fields */ soc_IPFIX_SESSION_INFO_ALL_BCM56634_A0fmt_fields, 28253 /* bits */ 96, 28254 /* flags */ 0, 28255 }, 28256 #endif /* chips */ 28257 28258 #if defined(BCM_56685_B0) 28259 { /* SOC_FORMAT_INT_IPFIX_SESSION_INFO_ALL_BCM56685_B0fmt */ 28260 /* format IPFIX_SESSION_INFO_ALLfmt */ 28261 /* nFields */ 8, 28262 /* *fields */ soc_IPFIX_SESSION_INFO_ALL_BCM56634_A0fmt_fields, 28263 /* bits */ 96, 28264 /* flags */ 0, 28265 }, 28266 #endif /* chips */ 28267 28268 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \ 28269 defined(BCM_56680_A0) || defined(BCM_56680_B0) 28270 { /* SOC_FORMAT_INT_IPFIX_SESSION_INFO_FIFOfmt */ 28271 /* format IPFIX_SESSION_INFO_FIFOfmt */ 28272 /* nFields */ 4, 28273 /* *fields */ soc_IPFIX_SESSION_INFO_FIFOfmt_fields, 28274 /* bits */ 90, 28275 /* flags */ 0, 28276 }, 28277 #endif /* chips */ 28278 28279 #if defined(BCM_53400_A0) 28280 { /* SOC_FORMAT_INT_IPFIX_SESSION_INFO_FIFO_BCM53400_A0fmt */ 28281 /* format IPFIX_SESSION_INFO_FIFOfmt */ 28282 /* nFields */ 4, 28283 /* *fields */ soc_IPFIX_SESSION_INFO_FIFO_BCM53400_A0fmt_fields, 28284 /* bits */ 90, 28285 /* flags */ 0, 28286 }, 28287 #endif /* chips */ 28288 28289 #if defined(BCM_53540_A0) 28290 { /* SOC_FORMAT_INT_IPFIX_SESSION_INFO_FIFO_BCM53540_A0fmt */ 28291 /* format IPFIX_SESSION_INFO_FIFOfmt */ 28292 /* nFields */ 4, 28293 /* *fields */ soc_IPFIX_SESSION_INFO_FIFO_BCM53400_A0fmt_fields, 28294 /* bits */ 90, 28295 /* flags */ 0, 28296 }, 28297 #endif /* chips */ 28298 28299 #if defined(BCM_53570_A0) 28300 { /* SOC_FORMAT_INT_IPFIX_SESSION_INFO_FIFO_BCM53570_A0fmt */ 28301 /* format IPFIX_SESSION_INFO_FIFOfmt */ 28302 /* nFields */ 4, 28303 /* *fields */ soc_IPFIX_SESSION_INFO_FIFO_BCM53400_A0fmt_fields, 28304 /* bits */ 90, 28305 /* flags */ 0, 28306 }, 28307 #endif /* chips */ 28308 28309 #if defined(BCM_53570_B0) 28310 { /* SOC_FORMAT_INT_IPFIX_SESSION_INFO_FIFO_BCM53570_B0fmt */ 28311 /* format IPFIX_SESSION_INFO_FIFOfmt */ 28312 /* nFields */ 4, 28313 /* *fields */ soc_IPFIX_SESSION_INFO_FIFO_BCM53400_A0fmt_fields, 28314 /* bits */ 90, 28315 /* flags */ 0, 28316 }, 28317 #endif /* chips */ 28318 28319 #if defined(BCM_56142_A0) 28320 { /* SOC_FORMAT_INT_IPFIX_SESSION_INFO_FIFO_BCM56142_A0fmt */ 28321 /* format IPFIX_SESSION_INFO_FIFOfmt */ 28322 /* nFields */ 4, 28323 /* *fields */ soc_IPFIX_SESSION_INFO_FIFOfmt_fields, 28324 /* bits */ 90, 28325 /* flags */ 0, 28326 }, 28327 #endif /* chips */ 28328 28329 #if defined(BCM_56150_A0) 28330 { /* SOC_FORMAT_INT_IPFIX_SESSION_INFO_FIFO_BCM56150_A0fmt */ 28331 /* format IPFIX_SESSION_INFO_FIFOfmt */ 28332 /* nFields */ 4, 28333 /* *fields */ soc_IPFIX_SESSION_INFO_FIFO_BCM56150_A0fmt_fields, 28334 /* bits */ 90, 28335 /* flags */ 0, 28336 }, 28337 #endif /* chips */ 28338 28339 #if defined(BCM_56160_A0) 28340 { /* SOC_FORMAT_INT_IPFIX_SESSION_INFO_FIFO_BCM56160_A0fmt */ 28341 /* format IPFIX_SESSION_INFO_FIFOfmt */ 28342 /* nFields */ 4, 28343 /* *fields */ soc_IPFIX_SESSION_INFO_FIFO_BCM53400_A0fmt_fields, 28344 /* bits */ 90, 28345 /* flags */ 0, 28346 }, 28347 #endif /* chips */ 28348 28349 #if defined(BCM_56334_A0) 28350 { /* SOC_FORMAT_INT_IPFIX_SESSION_INFO_FIFO_BCM56334_A0fmt */ 28351 /* format IPFIX_SESSION_INFO_FIFOfmt */ 28352 /* nFields */ 4, 28353 /* *fields */ soc_IPFIX_SESSION_INFO_FIFOfmt_fields, 28354 /* bits */ 90, 28355 /* flags */ 0, 28356 }, 28357 #endif /* chips */ 28358 28359 #if defined(BCM_56334_B0) 28360 { /* SOC_FORMAT_INT_IPFIX_SESSION_INFO_FIFO_BCM56334_B0fmt */ 28361 /* format IPFIX_SESSION_INFO_FIFOfmt */ 28362 /* nFields */ 4, 28363 /* *fields */ soc_IPFIX_SESSION_INFO_FIFOfmt_fields, 28364 /* bits */ 90, 28365 /* flags */ 0, 28366 }, 28367 #endif /* chips */ 28368 28369 #if defined(BCM_56524_A0) 28370 { /* SOC_FORMAT_INT_IPFIX_SESSION_INFO_FIFO_BCM56524_A0fmt */ 28371 /* format IPFIX_SESSION_INFO_FIFOfmt */ 28372 /* nFields */ 5, 28373 /* *fields */ soc_IPFIX_SESSION_INFO_FIFO_BCM56634_A0fmt_fields, 28374 /* bits */ 91, 28375 /* flags */ 0, 28376 }, 28377 #endif /* chips */ 28378 28379 #if defined(BCM_56524_B0) 28380 { /* SOC_FORMAT_INT_IPFIX_SESSION_INFO_FIFO_BCM56524_B0fmt */ 28381 /* format IPFIX_SESSION_INFO_FIFOfmt */ 28382 /* nFields */ 5, 28383 /* *fields */ soc_IPFIX_SESSION_INFO_FIFO_BCM56634_A0fmt_fields, 28384 /* bits */ 91, 28385 /* flags */ 0, 28386 }, 28387 #endif /* chips */ 28388 28389 #if defined(BCM_56634_A0) 28390 { /* SOC_FORMAT_INT_IPFIX_SESSION_INFO_FIFO_BCM56634_A0fmt */ 28391 /* format IPFIX_SESSION_INFO_FIFOfmt */ 28392 /* nFields */ 5, 28393 /* *fields */ soc_IPFIX_SESSION_INFO_FIFO_BCM56634_A0fmt_fields, 28394 /* bits */ 91, 28395 /* flags */ 0, 28396 }, 28397 #endif /* chips */ 28398 28399 #if defined(BCM_56634_B0) 28400 { /* SOC_FORMAT_INT_IPFIX_SESSION_INFO_FIFO_BCM56634_B0fmt */ 28401 /* format IPFIX_SESSION_INFO_FIFOfmt */ 28402 /* nFields */ 5, 28403 /* *fields */ soc_IPFIX_SESSION_INFO_FIFO_BCM56634_A0fmt_fields, 28404 /* bits */ 91, 28405 /* flags */ 0, 28406 }, 28407 #endif /* chips */ 28408 28409 #if defined(BCM_56640_A0) 28410 { /* SOC_FORMAT_INT_IPFIX_SESSION_INFO_FIFO_BCM56640_A0fmt */ 28411 /* format IPFIX_SESSION_INFO_FIFOfmt */ 28412 /* nFields */ 5, 28413 /* *fields */ soc_IPFIX_SESSION_INFO_FIFO_BCM56640_A0fmt_fields, 28414 /* bits */ 91, 28415 /* flags */ 0, 28416 }, 28417 #endif /* chips */ 28418 28419 #if defined(BCM_56685_A0) 28420 { /* SOC_FORMAT_INT_IPFIX_SESSION_INFO_FIFO_BCM56685_A0fmt */ 28421 /* format IPFIX_SESSION_INFO_FIFOfmt */ 28422 /* nFields */ 5, 28423 /* *fields */ soc_IPFIX_SESSION_INFO_FIFO_BCM56634_A0fmt_fields, 28424 /* bits */ 91, 28425 /* flags */ 0, 28426 }, 28427 #endif /* chips */ 28428 28429 #if defined(BCM_56685_B0) 28430 { /* SOC_FORMAT_INT_IPFIX_SESSION_INFO_FIFO_BCM56685_B0fmt */ 28431 /* format IPFIX_SESSION_INFO_FIFOfmt */ 28432 /* nFields */ 5, 28433 /* *fields */ soc_IPFIX_SESSION_INFO_FIFO_BCM56634_A0fmt_fields, 28434 /* bits */ 91, 28435 /* flags */ 0, 28436 }, 28437 #endif /* chips */ 28438 28439 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \ 28440 defined(BCM_56624_A0) || defined(BCM_56624_B0) || \ 28441 defined(BCM_56634_A0) || defined(BCM_56680_A0) || \ 28442 defined(BCM_56685_A0) || defined(BCM_56685_B0) 28443 { /* SOC_FORMAT_INT_IPMC_GRP_8_S_RFfmt */ 28444 /* format IPMC_GRP_8_S_RFfmt */ 28445 /* nFields */ 1, 28446 /* *fields */ soc_IPMC_GRP_8_S_RFfmt_fields, 28447 /* bits */ 112, 28448 /* flags */ 0, 28449 }, 28450 #endif /* chips */ 28451 28452 #if defined(BCM_56634_B0) 28453 { /* SOC_FORMAT_INT_IPMC_GRP_8_S_RF_BCM56634_B0fmt */ 28454 /* format IPMC_GRP_8_S_RFfmt */ 28455 /* nFields */ 1, 28456 /* *fields */ soc_IPMC_GRP_8_S_RFfmt_fields, 28457 /* bits */ 112, 28458 /* flags */ 0, 28459 }, 28460 #endif /* chips */ 28461 28462 #if defined(BCM_56680_B0) 28463 { /* SOC_FORMAT_INT_IPMC_GRP_8_S_RF_BCM56680_B0fmt */ 28464 /* format IPMC_GRP_8_S_RFfmt */ 28465 /* nFields */ 1, 28466 /* *fields */ soc_IPMC_GRP_8_S_RFfmt_fields, 28467 /* bits */ 112, 28468 /* flags */ 0, 28469 }, 28470 #endif /* chips */ 28471 28472 #if defined(BCM_56800_A0) 28473 { /* SOC_FORMAT_INT_IPMC_GRP_S_RFfmt */ 28474 /* format IPMC_GRP_S_RFfmt */ 28475 /* nFields */ 1, 28476 /* *fields */ soc_IPMC_GRP_S_RFfmt_fields, 28477 /* bits */ 28, 28478 /* flags */ 0, 28479 }, 28480 #endif /* chips */ 28481 28482 #if defined(BCM_56334_A0) 28483 { /* SOC_FORMAT_INT_IPMC_GRP_S_RF_BCM56334_A0fmt */ 28484 /* format IPMC_GRP_S_RFfmt */ 28485 /* nFields */ 1, 28486 /* *fields */ soc_IPMC_GRP_S_RF_BCM56334_A0fmt_fields, 28487 /* bits */ 18, 28488 /* flags */ 0, 28489 }, 28490 #endif /* chips */ 28491 28492 #if defined(BCM_56334_B0) 28493 { /* SOC_FORMAT_INT_IPMC_GRP_S_RF_BCM56334_B0fmt */ 28494 /* format IPMC_GRP_S_RFfmt */ 28495 /* nFields */ 1, 28496 /* *fields */ soc_IPMC_GRP_S_RF_BCM56334_A0fmt_fields, 28497 /* bits */ 18, 28498 /* flags */ 0, 28499 }, 28500 #endif /* chips */ 28501 28502 #if defined(BCM_56524_A0) 28503 { /* SOC_FORMAT_INT_IPMC_GRP_S_RF_BCM56524_A0fmt */ 28504 /* format IPMC_GRP_S_RFfmt */ 28505 /* nFields */ 1, 28506 /* *fields */ soc_IPMC_GRP_S_RF_BCM56624_A0fmt_fields, 28507 /* bits */ 64, 28508 /* flags */ 0, 28509 }, 28510 #endif /* chips */ 28511 28512 #if defined(BCM_56524_B0) 28513 { /* SOC_FORMAT_INT_IPMC_GRP_S_RF_BCM56524_B0fmt */ 28514 /* format IPMC_GRP_S_RFfmt */ 28515 /* nFields */ 1, 28516 /* *fields */ soc_IPMC_GRP_S_RF_BCM56624_A0fmt_fields, 28517 /* bits */ 64, 28518 /* flags */ 0, 28519 }, 28520 #endif /* chips */ 28521 28522 #if defined(BCM_56624_A0) 28523 { /* SOC_FORMAT_INT_IPMC_GRP_S_RF_BCM56624_A0fmt */ 28524 /* format IPMC_GRP_S_RFfmt */ 28525 /* nFields */ 1, 28526 /* *fields */ soc_IPMC_GRP_S_RF_BCM56624_A0fmt_fields, 28527 /* bits */ 64, 28528 /* flags */ 0, 28529 }, 28530 #endif /* chips */ 28531 28532 #if defined(BCM_56624_B0) 28533 { /* SOC_FORMAT_INT_IPMC_GRP_S_RF_BCM56624_B0fmt */ 28534 /* format IPMC_GRP_S_RFfmt */ 28535 /* nFields */ 1, 28536 /* *fields */ soc_IPMC_GRP_S_RF_BCM56624_A0fmt_fields, 28537 /* bits */ 64, 28538 /* flags */ 0, 28539 }, 28540 #endif /* chips */ 28541 28542 #if defined(BCM_56634_A0) 28543 { /* SOC_FORMAT_INT_IPMC_GRP_S_RF_BCM56634_A0fmt */ 28544 /* format IPMC_GRP_S_RFfmt */ 28545 /* nFields */ 1, 28546 /* *fields */ soc_IPMC_GRP_S_RF_BCM56624_A0fmt_fields, 28547 /* bits */ 64, 28548 /* flags */ 0, 28549 }, 28550 #endif /* chips */ 28551 28552 #if defined(BCM_56634_B0) 28553 { /* SOC_FORMAT_INT_IPMC_GRP_S_RF_BCM56634_B0fmt */ 28554 /* format IPMC_GRP_S_RFfmt */ 28555 /* nFields */ 1, 28556 /* *fields */ soc_IPMC_GRP_S_RF_BCM56624_A0fmt_fields, 28557 /* bits */ 64, 28558 /* flags */ 0, 28559 }, 28560 #endif /* chips */ 28561 28562 #if defined(BCM_56680_A0) 28563 { /* SOC_FORMAT_INT_IPMC_GRP_S_RF_BCM56680_A0fmt */ 28564 /* format IPMC_GRP_S_RFfmt */ 28565 /* nFields */ 1, 28566 /* *fields */ soc_IPMC_GRP_S_RF_BCM56624_A0fmt_fields, 28567 /* bits */ 64, 28568 /* flags */ 0, 28569 }, 28570 #endif /* chips */ 28571 28572 #if defined(BCM_56680_B0) 28573 { /* SOC_FORMAT_INT_IPMC_GRP_S_RF_BCM56680_B0fmt */ 28574 /* format IPMC_GRP_S_RFfmt */ 28575 /* nFields */ 1, 28576 /* *fields */ soc_IPMC_GRP_S_RF_BCM56624_A0fmt_fields, 28577 /* bits */ 64, 28578 /* flags */ 0, 28579 }, 28580 #endif /* chips */ 28581 28582 #if defined(BCM_56685_A0) 28583 { /* SOC_FORMAT_INT_IPMC_GRP_S_RF_BCM56685_A0fmt */ 28584 /* format IPMC_GRP_S_RFfmt */ 28585 /* nFields */ 1, 28586 /* *fields */ soc_IPMC_GRP_S_RF_BCM56624_A0fmt_fields, 28587 /* bits */ 64, 28588 /* flags */ 0, 28589 }, 28590 #endif /* chips */ 28591 28592 #if defined(BCM_56685_B0) 28593 { /* SOC_FORMAT_INT_IPMC_GRP_S_RF_BCM56685_B0fmt */ 28594 /* format IPMC_GRP_S_RFfmt */ 28595 /* nFields */ 1, 28596 /* *fields */ soc_IPMC_GRP_S_RF_BCM56624_A0fmt_fields, 28597 /* bits */ 64, 28598 /* flags */ 0, 28599 }, 28600 #endif /* chips */ 28601 28602 #if defined(BCM_56725_A0) 28603 { /* SOC_FORMAT_INT_IPMC_GRP_S_RF_BCM56725_A0fmt */ 28604 /* format IPMC_GRP_S_RFfmt */ 28605 /* nFields */ 1, 28606 /* *fields */ soc_IPMC_GRP_S_RFfmt_fields, 28607 /* bits */ 28, 28608 /* flags */ 0, 28609 }, 28610 #endif /* chips */ 28611 28612 #if defined(BCM_56820_A0) 28613 { /* SOC_FORMAT_INT_IPMC_GRP_S_RF_BCM56820_A0fmt */ 28614 /* format IPMC_GRP_S_RFfmt */ 28615 /* nFields */ 1, 28616 /* *fields */ soc_IPMC_GRP_S_RFfmt_fields, 28617 /* bits */ 28, 28618 /* flags */ 0, 28619 }, 28620 #endif /* chips */ 28621 28622 #if defined(BCM_56800_A0) 28623 { /* SOC_FORMAT_INT_IPMC_VLAN_S_RFfmt */ 28624 /* format IPMC_VLAN_S_RFfmt */ 28625 /* nFields */ 1, 28626 /* *fields */ soc_IPMC_VLAN_S_RFfmt_fields, 28627 /* bits */ 28, 28628 /* flags */ 0, 28629 }, 28630 #endif /* chips */ 28631 28632 #if defined(BCM_56334_A0) 28633 { /* SOC_FORMAT_INT_IPMC_VLAN_S_RF_BCM56334_A0fmt */ 28634 /* format IPMC_VLAN_S_RFfmt */ 28635 /* nFields */ 1, 28636 /* *fields */ soc_IPMC_VLAN_S_RF_BCM56334_A0fmt_fields, 28637 /* bits */ 36, 28638 /* flags */ 0, 28639 }, 28640 #endif /* chips */ 28641 28642 #if defined(BCM_56334_B0) 28643 { /* SOC_FORMAT_INT_IPMC_VLAN_S_RF_BCM56334_B0fmt */ 28644 /* format IPMC_VLAN_S_RFfmt */ 28645 /* nFields */ 1, 28646 /* *fields */ soc_IPMC_VLAN_S_RF_BCM56334_A0fmt_fields, 28647 /* bits */ 36, 28648 /* flags */ 0, 28649 }, 28650 #endif /* chips */ 28651 28652 #if defined(BCM_56524_A0) 28653 { /* SOC_FORMAT_INT_IPMC_VLAN_S_RF_BCM56524_A0fmt */ 28654 /* format IPMC_VLAN_S_RFfmt */ 28655 /* nFields */ 1, 28656 /* *fields */ soc_IPMC_VLAN_S_RF_BCM56624_A0fmt_fields, 28657 /* bits */ 112, 28658 /* flags */ 0, 28659 }, 28660 #endif /* chips */ 28661 28662 #if defined(BCM_56524_B0) 28663 { /* SOC_FORMAT_INT_IPMC_VLAN_S_RF_BCM56524_B0fmt */ 28664 /* format IPMC_VLAN_S_RFfmt */ 28665 /* nFields */ 1, 28666 /* *fields */ soc_IPMC_VLAN_S_RF_BCM56624_A0fmt_fields, 28667 /* bits */ 112, 28668 /* flags */ 0, 28669 }, 28670 #endif /* chips */ 28671 28672 #if defined(BCM_56624_A0) 28673 { /* SOC_FORMAT_INT_IPMC_VLAN_S_RF_BCM56624_A0fmt */ 28674 /* format IPMC_VLAN_S_RFfmt */ 28675 /* nFields */ 1, 28676 /* *fields */ soc_IPMC_VLAN_S_RF_BCM56624_A0fmt_fields, 28677 /* bits */ 112, 28678 /* flags */ 0, 28679 }, 28680 #endif /* chips */ 28681 28682 #if defined(BCM_56624_B0) 28683 { /* SOC_FORMAT_INT_IPMC_VLAN_S_RF_BCM56624_B0fmt */ 28684 /* format IPMC_VLAN_S_RFfmt */ 28685 /* nFields */ 1, 28686 /* *fields */ soc_IPMC_VLAN_S_RF_BCM56624_A0fmt_fields, 28687 /* bits */ 112, 28688 /* flags */ 0, 28689 }, 28690 #endif /* chips */ 28691 28692 #if defined(BCM_56634_A0) 28693 { /* SOC_FORMAT_INT_IPMC_VLAN_S_RF_BCM56634_A0fmt */ 28694 /* format IPMC_VLAN_S_RFfmt */ 28695 /* nFields */ 1, 28696 /* *fields */ soc_IPMC_VLAN_S_RF_BCM56624_A0fmt_fields, 28697 /* bits */ 112, 28698 /* flags */ 0, 28699 }, 28700 #endif /* chips */ 28701 28702 #if defined(BCM_56634_B0) 28703 { /* SOC_FORMAT_INT_IPMC_VLAN_S_RF_BCM56634_B0fmt */ 28704 /* format IPMC_VLAN_S_RFfmt */ 28705 /* nFields */ 1, 28706 /* *fields */ soc_IPMC_VLAN_S_RF_BCM56624_A0fmt_fields, 28707 /* bits */ 112, 28708 /* flags */ 0, 28709 }, 28710 #endif /* chips */ 28711 28712 #if defined(BCM_56680_A0) 28713 { /* SOC_FORMAT_INT_IPMC_VLAN_S_RF_BCM56680_A0fmt */ 28714 /* format IPMC_VLAN_S_RFfmt */ 28715 /* nFields */ 1, 28716 /* *fields */ soc_IPMC_VLAN_S_RF_BCM56624_A0fmt_fields, 28717 /* bits */ 112, 28718 /* flags */ 0, 28719 }, 28720 #endif /* chips */ 28721 28722 #if defined(BCM_56680_B0) 28723 { /* SOC_FORMAT_INT_IPMC_VLAN_S_RF_BCM56680_B0fmt */ 28724 /* format IPMC_VLAN_S_RFfmt */ 28725 /* nFields */ 1, 28726 /* *fields */ soc_IPMC_VLAN_S_RF_BCM56624_A0fmt_fields, 28727 /* bits */ 112, 28728 /* flags */ 0, 28729 }, 28730 #endif /* chips */ 28731 28732 #if defined(BCM_56685_A0) 28733 { /* SOC_FORMAT_INT_IPMC_VLAN_S_RF_BCM56685_A0fmt */ 28734 /* format IPMC_VLAN_S_RFfmt */ 28735 /* nFields */ 1, 28736 /* *fields */ soc_IPMC_VLAN_S_RF_BCM56624_A0fmt_fields, 28737 /* bits */ 112, 28738 /* flags */ 0, 28739 }, 28740 #endif /* chips */ 28741 28742 #if defined(BCM_56685_B0) 28743 { /* SOC_FORMAT_INT_IPMC_VLAN_S_RF_BCM56685_B0fmt */ 28744 /* format IPMC_VLAN_S_RFfmt */ 28745 /* nFields */ 1, 28746 /* *fields */ soc_IPMC_VLAN_S_RF_BCM56624_A0fmt_fields, 28747 /* bits */ 112, 28748 /* flags */ 0, 28749 }, 28750 #endif /* chips */ 28751 28752 #if defined(BCM_56725_A0) 28753 { /* SOC_FORMAT_INT_IPMC_VLAN_S_RF_BCM56725_A0fmt */ 28754 /* format IPMC_VLAN_S_RFfmt */ 28755 /* nFields */ 1, 28756 /* *fields */ soc_IPMC_VLAN_S_RF_BCM56820_A0fmt_fields, 28757 /* bits */ 56, 28758 /* flags */ 0, 28759 }, 28760 #endif /* chips */ 28761 28762 #if defined(BCM_56820_A0) 28763 { /* SOC_FORMAT_INT_IPMC_VLAN_S_RF_BCM56820_A0fmt */ 28764 /* format IPMC_VLAN_S_RFfmt */ 28765 /* nFields */ 1, 28766 /* *fields */ soc_IPMC_VLAN_S_RF_BCM56820_A0fmt_fields, 28767 /* bits */ 56, 28768 /* flags */ 0, 28769 }, 28770 #endif /* chips */ 28771 28772 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 28773 { /* SOC_FORMAT_INT_IPOST_CELL_QUEUES_DATAfmt */ 28774 /* format IPOST_CELL_QUEUES_DATAfmt */ 28775 /* nFields */ 6, 28776 /* *fields */ soc_IPOST_CELL_QUEUES_DATAfmt_fields, 28777 /* bits */ 21, 28778 /* flags */ 0, 28779 }, 28780 #endif /* chips */ 28781 28782 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 28783 { /* SOC_FORMAT_INT_IPOST_SLOT_PIPELINE_DATAfmt */ 28784 /* format IPOST_SLOT_PIPELINE_DATAfmt */ 28785 /* nFields */ 3, 28786 /* *fields */ soc_IPOST_SLOT_PIPELINE_DATAfmt_fields, 28787 /* bits */ 9, 28788 /* flags */ 0, 28789 }, 28790 #endif /* chips */ 28791 28792 #if defined(BCM_56504_A0) 28793 { /* SOC_FORMAT_INT_IPRC_BUSfmt */ 28794 /* format IPRC_BUSfmt */ 28795 /* nFields */ 4, 28796 /* *fields */ soc_IPRC_BUSfmt_fields, 28797 /* bits */ 42, 28798 /* flags */ 0, 28799 }, 28800 #endif /* chips */ 28801 28802 #if defined(BCM_53314_A0) 28803 { /* SOC_FORMAT_INT_IPRC_BUS_BCM53314_A0fmt */ 28804 /* format IPRC_BUSfmt */ 28805 /* nFields */ 4, 28806 /* *fields */ soc_IPRC_BUSfmt_fields, 28807 /* bits */ 42, 28808 /* flags */ 0, 28809 }, 28810 #endif /* chips */ 28811 28812 #if defined(BCM_53324_A0) 28813 { /* SOC_FORMAT_INT_IPRC_BUS_BCM53324_A0fmt */ 28814 /* format IPRC_BUSfmt */ 28815 /* nFields */ 4, 28816 /* *fields */ soc_IPRC_BUSfmt_fields, 28817 /* bits */ 42, 28818 /* flags */ 0, 28819 }, 28820 #endif /* chips */ 28821 28822 #if defined(BCM_53400_A0) 28823 { /* SOC_FORMAT_INT_IPRC_BUS_BCM53400_A0fmt */ 28824 /* format IPRC_BUSfmt */ 28825 /* nFields */ 4, 28826 /* *fields */ soc_IPRC_BUS_BCM53400_A0fmt_fields, 28827 /* bits */ 43, 28828 /* flags */ 0, 28829 }, 28830 #endif /* chips */ 28831 28832 #if defined(BCM_53540_A0) 28833 { /* SOC_FORMAT_INT_IPRC_BUS_BCM53540_A0fmt */ 28834 /* format IPRC_BUSfmt */ 28835 /* nFields */ 4, 28836 /* *fields */ soc_IPRC_BUS_BCM53400_A0fmt_fields, 28837 /* bits */ 43, 28838 /* flags */ 0, 28839 }, 28840 #endif /* chips */ 28841 28842 #if defined(BCM_53570_A0) 28843 { /* SOC_FORMAT_INT_IPRC_BUS_BCM53570_A0fmt */ 28844 /* format IPRC_BUSfmt */ 28845 /* nFields */ 4, 28846 /* *fields */ soc_IPRC_BUS_BCM53400_A0fmt_fields, 28847 /* bits */ 43, 28848 /* flags */ 0, 28849 }, 28850 #endif /* chips */ 28851 28852 #if defined(BCM_53570_B0) 28853 { /* SOC_FORMAT_INT_IPRC_BUS_BCM53570_B0fmt */ 28854 /* format IPRC_BUSfmt */ 28855 /* nFields */ 4, 28856 /* *fields */ soc_IPRC_BUS_BCM53400_A0fmt_fields, 28857 /* bits */ 43, 28858 /* flags */ 0, 28859 }, 28860 #endif /* chips */ 28861 28862 #if defined(BCM_56142_A0) 28863 { /* SOC_FORMAT_INT_IPRC_BUS_BCM56142_A0fmt */ 28864 /* format IPRC_BUSfmt */ 28865 /* nFields */ 4, 28866 /* *fields */ soc_IPRC_BUSfmt_fields, 28867 /* bits */ 42, 28868 /* flags */ 0, 28869 }, 28870 #endif /* chips */ 28871 28872 #if defined(BCM_56150_A0) 28873 { /* SOC_FORMAT_INT_IPRC_BUS_BCM56150_A0fmt */ 28874 /* format IPRC_BUSfmt */ 28875 /* nFields */ 4, 28876 /* *fields */ soc_IPRC_BUS_BCM56640_A0fmt_fields, 28877 /* bits */ 43, 28878 /* flags */ 0, 28879 }, 28880 #endif /* chips */ 28881 28882 #if defined(BCM_56160_A0) 28883 { /* SOC_FORMAT_INT_IPRC_BUS_BCM56160_A0fmt */ 28884 /* format IPRC_BUSfmt */ 28885 /* nFields */ 4, 28886 /* *fields */ soc_IPRC_BUS_BCM53400_A0fmt_fields, 28887 /* bits */ 43, 28888 /* flags */ 0, 28889 }, 28890 #endif /* chips */ 28891 28892 #if defined(BCM_56224_A0) 28893 { /* SOC_FORMAT_INT_IPRC_BUS_BCM56224_A0fmt */ 28894 /* format IPRC_BUSfmt */ 28895 /* nFields */ 4, 28896 /* *fields */ soc_IPRC_BUSfmt_fields, 28897 /* bits */ 42, 28898 /* flags */ 0, 28899 }, 28900 #endif /* chips */ 28901 28902 #if defined(BCM_56224_B0) 28903 { /* SOC_FORMAT_INT_IPRC_BUS_BCM56224_B0fmt */ 28904 /* format IPRC_BUSfmt */ 28905 /* nFields */ 4, 28906 /* *fields */ soc_IPRC_BUSfmt_fields, 28907 /* bits */ 42, 28908 /* flags */ 0, 28909 }, 28910 #endif /* chips */ 28911 28912 #if defined(BCM_56260_A0) 28913 { /* SOC_FORMAT_INT_IPRC_BUS_BCM56260_A0fmt */ 28914 /* format IPRC_BUSfmt */ 28915 /* nFields */ 4, 28916 /* *fields */ soc_IPRC_BUS_BCM53400_A0fmt_fields, 28917 /* bits */ 43, 28918 /* flags */ 0, 28919 }, 28920 #endif /* chips */ 28921 28922 #if defined(BCM_56260_B0) 28923 { /* SOC_FORMAT_INT_IPRC_BUS_BCM56260_B0fmt */ 28924 /* format IPRC_BUSfmt */ 28925 /* nFields */ 4, 28926 /* *fields */ soc_IPRC_BUS_BCM53400_A0fmt_fields, 28927 /* bits */ 43, 28928 /* flags */ 0, 28929 }, 28930 #endif /* chips */ 28931 28932 #if defined(BCM_56270_A0) 28933 { /* SOC_FORMAT_INT_IPRC_BUS_BCM56270_A0fmt */ 28934 /* format IPRC_BUSfmt */ 28935 /* nFields */ 4, 28936 /* *fields */ soc_IPRC_BUS_BCM53400_A0fmt_fields, 28937 /* bits */ 43, 28938 /* flags */ 0, 28939 }, 28940 #endif /* chips */ 28941 28942 #if defined(BCM_56314_A0) 28943 { /* SOC_FORMAT_INT_IPRC_BUS_BCM56314_A0fmt */ 28944 /* format IPRC_BUSfmt */ 28945 /* nFields */ 4, 28946 /* *fields */ soc_IPRC_BUSfmt_fields, 28947 /* bits */ 42, 28948 /* flags */ 0, 28949 }, 28950 #endif /* chips */ 28951 28952 #if defined(BCM_56334_A0) 28953 { /* SOC_FORMAT_INT_IPRC_BUS_BCM56334_A0fmt */ 28954 /* format IPRC_BUSfmt */ 28955 /* nFields */ 4, 28956 /* *fields */ soc_IPRC_BUSfmt_fields, 28957 /* bits */ 42, 28958 /* flags */ 0, 28959 }, 28960 #endif /* chips */ 28961 28962 #if defined(BCM_56334_B0) 28963 { /* SOC_FORMAT_INT_IPRC_BUS_BCM56334_B0fmt */ 28964 /* format IPRC_BUSfmt */ 28965 /* nFields */ 4, 28966 /* *fields */ soc_IPRC_BUSfmt_fields, 28967 /* bits */ 42, 28968 /* flags */ 0, 28969 }, 28970 #endif /* chips */ 28971 28972 #if defined(BCM_56340_A0) 28973 { /* SOC_FORMAT_INT_IPRC_BUS_BCM56340_A0fmt */ 28974 /* format IPRC_BUSfmt */ 28975 /* nFields */ 4, 28976 /* *fields */ soc_IPRC_BUS_BCM56640_A0fmt_fields, 28977 /* bits */ 43, 28978 /* flags */ 0, 28979 }, 28980 #endif /* chips */ 28981 28982 #if defined(BCM_56370_A0) 28983 { /* SOC_FORMAT_INT_IPRC_BUS_BCM56370_A0fmt */ 28984 /* format IPRC_BUSfmt */ 28985 /* nFields */ 4, 28986 /* *fields */ soc_IPRC_BUS_BCM56960_A0fmt_fields, 28987 /* bits */ 44, 28988 /* flags */ 0, 28989 }, 28990 #endif /* chips */ 28991 28992 #if defined(BCM_56440_A0) 28993 { /* SOC_FORMAT_INT_IPRC_BUS_BCM56440_A0fmt */ 28994 /* format IPRC_BUSfmt */ 28995 /* nFields */ 4, 28996 /* *fields */ soc_IPRC_BUS_BCM56840_A0fmt_fields, 28997 /* bits */ 43, 28998 /* flags */ 0, 28999 }, 29000 #endif /* chips */ 29001 29002 #if defined(BCM_56440_B0) 29003 { /* SOC_FORMAT_INT_IPRC_BUS_BCM56440_B0fmt */ 29004 /* format IPRC_BUSfmt */ 29005 /* nFields */ 4, 29006 /* *fields */ soc_IPRC_BUS_BCM56840_A0fmt_fields, 29007 /* bits */ 43, 29008 /* flags */ 0, 29009 }, 29010 #endif /* chips */ 29011 29012 #if defined(BCM_56450_A0) 29013 { /* SOC_FORMAT_INT_IPRC_BUS_BCM56450_A0fmt */ 29014 /* format IPRC_BUSfmt */ 29015 /* nFields */ 4, 29016 /* *fields */ soc_IPRC_BUS_BCM56640_A0fmt_fields, 29017 /* bits */ 43, 29018 /* flags */ 0, 29019 }, 29020 #endif /* chips */ 29021 29022 #if defined(BCM_56450_B0) 29023 { /* SOC_FORMAT_INT_IPRC_BUS_BCM56450_B0fmt */ 29024 /* format IPRC_BUSfmt */ 29025 /* nFields */ 4, 29026 /* *fields */ soc_IPRC_BUS_BCM56640_A0fmt_fields, 29027 /* bits */ 43, 29028 /* flags */ 0, 29029 }, 29030 #endif /* chips */ 29031 29032 #if defined(BCM_56450_B1) 29033 { /* SOC_FORMAT_INT_IPRC_BUS_BCM56450_B1fmt */ 29034 /* format IPRC_BUSfmt */ 29035 /* nFields */ 4, 29036 /* *fields */ soc_IPRC_BUS_BCM56640_A0fmt_fields, 29037 /* bits */ 43, 29038 /* flags */ 0, 29039 }, 29040 #endif /* chips */ 29041 29042 #if defined(BCM_56504_B0) 29043 { /* SOC_FORMAT_INT_IPRC_BUS_BCM56504_B0fmt */ 29044 /* format IPRC_BUSfmt */ 29045 /* nFields */ 4, 29046 /* *fields */ soc_IPRC_BUSfmt_fields, 29047 /* bits */ 42, 29048 /* flags */ 0, 29049 }, 29050 #endif /* chips */ 29051 29052 #if defined(BCM_56514_A0) 29053 { /* SOC_FORMAT_INT_IPRC_BUS_BCM56514_A0fmt */ 29054 /* format IPRC_BUSfmt */ 29055 /* nFields */ 4, 29056 /* *fields */ soc_IPRC_BUSfmt_fields, 29057 /* bits */ 42, 29058 /* flags */ 0, 29059 }, 29060 #endif /* chips */ 29061 29062 #if defined(BCM_56524_A0) 29063 { /* SOC_FORMAT_INT_IPRC_BUS_BCM56524_A0fmt */ 29064 /* format IPRC_BUSfmt */ 29065 /* nFields */ 4, 29066 /* *fields */ soc_IPRC_BUSfmt_fields, 29067 /* bits */ 42, 29068 /* flags */ 0, 29069 }, 29070 #endif /* chips */ 29071 29072 #if defined(BCM_56524_B0) 29073 { /* SOC_FORMAT_INT_IPRC_BUS_BCM56524_B0fmt */ 29074 /* format IPRC_BUSfmt */ 29075 /* nFields */ 4, 29076 /* *fields */ soc_IPRC_BUSfmt_fields, 29077 /* bits */ 42, 29078 /* flags */ 0, 29079 }, 29080 #endif /* chips */ 29081 29082 #if defined(BCM_56560_A0) 29083 { /* SOC_FORMAT_INT_IPRC_BUS_BCM56560_A0fmt */ 29084 /* format IPRC_BUSfmt */ 29085 /* nFields */ 4, 29086 /* *fields */ soc_IPRC_BUS_BCM53400_A0fmt_fields, 29087 /* bits */ 43, 29088 /* flags */ 0, 29089 }, 29090 #endif /* chips */ 29091 29092 #if defined(BCM_56560_B0) 29093 { /* SOC_FORMAT_INT_IPRC_BUS_BCM56560_B0fmt */ 29094 /* format IPRC_BUSfmt */ 29095 /* nFields */ 4, 29096 /* *fields */ soc_IPRC_BUS_BCM53400_A0fmt_fields, 29097 /* bits */ 43, 29098 /* flags */ 0, 29099 }, 29100 #endif /* chips */ 29101 29102 #if defined(BCM_56624_A0) 29103 { /* SOC_FORMAT_INT_IPRC_BUS_BCM56624_A0fmt */ 29104 /* format IPRC_BUSfmt */ 29105 /* nFields */ 4, 29106 /* *fields */ soc_IPRC_BUSfmt_fields, 29107 /* bits */ 42, 29108 /* flags */ 0, 29109 }, 29110 #endif /* chips */ 29111 29112 #if defined(BCM_56624_B0) 29113 { /* SOC_FORMAT_INT_IPRC_BUS_BCM56624_B0fmt */ 29114 /* format IPRC_BUSfmt */ 29115 /* nFields */ 4, 29116 /* *fields */ soc_IPRC_BUSfmt_fields, 29117 /* bits */ 42, 29118 /* flags */ 0, 29119 }, 29120 #endif /* chips */ 29121 29122 #if defined(BCM_56634_A0) 29123 { /* SOC_FORMAT_INT_IPRC_BUS_BCM56634_A0fmt */ 29124 /* format IPRC_BUSfmt */ 29125 /* nFields */ 4, 29126 /* *fields */ soc_IPRC_BUSfmt_fields, 29127 /* bits */ 42, 29128 /* flags */ 0, 29129 }, 29130 #endif /* chips */ 29131 29132 #if defined(BCM_56634_B0) 29133 { /* SOC_FORMAT_INT_IPRC_BUS_BCM56634_B0fmt */ 29134 /* format IPRC_BUSfmt */ 29135 /* nFields */ 4, 29136 /* *fields */ soc_IPRC_BUSfmt_fields, 29137 /* bits */ 42, 29138 /* flags */ 0, 29139 }, 29140 #endif /* chips */ 29141 29142 #if defined(BCM_56640_A0) 29143 { /* SOC_FORMAT_INT_IPRC_BUS_BCM56640_A0fmt */ 29144 /* format IPRC_BUSfmt */ 29145 /* nFields */ 4, 29146 /* *fields */ soc_IPRC_BUS_BCM56640_A0fmt_fields, 29147 /* bits */ 43, 29148 /* flags */ 0, 29149 }, 29150 #endif /* chips */ 29151 29152 #if defined(BCM_56670_A0) 29153 { /* SOC_FORMAT_INT_IPRC_BUS_BCM56670_A0fmt */ 29154 /* format IPRC_BUSfmt */ 29155 /* nFields */ 4, 29156 /* *fields */ soc_IPRC_BUS_BCM53400_A0fmt_fields, 29157 /* bits */ 43, 29158 /* flags */ 0, 29159 }, 29160 #endif /* chips */ 29161 29162 #if defined(BCM_56670_B0) 29163 { /* SOC_FORMAT_INT_IPRC_BUS_BCM56670_B0fmt */ 29164 /* format IPRC_BUSfmt */ 29165 /* nFields */ 4, 29166 /* *fields */ soc_IPRC_BUS_BCM53400_A0fmt_fields, 29167 /* bits */ 43, 29168 /* flags */ 0, 29169 }, 29170 #endif /* chips */ 29171 29172 #if defined(BCM_56680_A0) 29173 { /* SOC_FORMAT_INT_IPRC_BUS_BCM56680_A0fmt */ 29174 /* format IPRC_BUSfmt */ 29175 /* nFields */ 4, 29176 /* *fields */ soc_IPRC_BUSfmt_fields, 29177 /* bits */ 42, 29178 /* flags */ 0, 29179 }, 29180 #endif /* chips */ 29181 29182 #if defined(BCM_56680_B0) 29183 { /* SOC_FORMAT_INT_IPRC_BUS_BCM56680_B0fmt */ 29184 /* format IPRC_BUSfmt */ 29185 /* nFields */ 4, 29186 /* *fields */ soc_IPRC_BUSfmt_fields, 29187 /* bits */ 42, 29188 /* flags */ 0, 29189 }, 29190 #endif /* chips */ 29191 29192 #if defined(BCM_56685_A0) 29193 { /* SOC_FORMAT_INT_IPRC_BUS_BCM56685_A0fmt */ 29194 /* format IPRC_BUSfmt */ 29195 /* nFields */ 4, 29196 /* *fields */ soc_IPRC_BUSfmt_fields, 29197 /* bits */ 42, 29198 /* flags */ 0, 29199 }, 29200 #endif /* chips */ 29201 29202 #if defined(BCM_56685_B0) 29203 { /* SOC_FORMAT_INT_IPRC_BUS_BCM56685_B0fmt */ 29204 /* format IPRC_BUSfmt */ 29205 /* nFields */ 4, 29206 /* *fields */ soc_IPRC_BUSfmt_fields, 29207 /* bits */ 42, 29208 /* flags */ 0, 29209 }, 29210 #endif /* chips */ 29211 29212 #if defined(BCM_56725_A0) 29213 { /* SOC_FORMAT_INT_IPRC_BUS_BCM56725_A0fmt */ 29214 /* format IPRC_BUSfmt */ 29215 /* nFields */ 4, 29216 /* *fields */ soc_IPRC_BUSfmt_fields, 29217 /* bits */ 42, 29218 /* flags */ 0, 29219 }, 29220 #endif /* chips */ 29221 29222 #if defined(BCM_56770_A0) 29223 { /* SOC_FORMAT_INT_IPRC_BUS_BCM56770_A0fmt */ 29224 /* format IPRC_BUSfmt */ 29225 /* nFields */ 4, 29226 /* *fields */ soc_IPRC_BUS_BCM56960_A0fmt_fields, 29227 /* bits */ 44, 29228 /* flags */ 0, 29229 }, 29230 #endif /* chips */ 29231 29232 #if defined(BCM_56800_A0) 29233 { /* SOC_FORMAT_INT_IPRC_BUS_BCM56800_A0fmt */ 29234 /* format IPRC_BUSfmt */ 29235 /* nFields */ 4, 29236 /* *fields */ soc_IPRC_BUSfmt_fields, 29237 /* bits */ 42, 29238 /* flags */ 0, 29239 }, 29240 #endif /* chips */ 29241 29242 #if defined(BCM_56820_A0) 29243 { /* SOC_FORMAT_INT_IPRC_BUS_BCM56820_A0fmt */ 29244 /* format IPRC_BUSfmt */ 29245 /* nFields */ 4, 29246 /* *fields */ soc_IPRC_BUSfmt_fields, 29247 /* bits */ 42, 29248 /* flags */ 0, 29249 }, 29250 #endif /* chips */ 29251 29252 #if defined(BCM_56840_A0) 29253 { /* SOC_FORMAT_INT_IPRC_BUS_BCM56840_A0fmt */ 29254 /* format IPRC_BUSfmt */ 29255 /* nFields */ 4, 29256 /* *fields */ soc_IPRC_BUS_BCM56840_A0fmt_fields, 29257 /* bits */ 43, 29258 /* flags */ 0, 29259 }, 29260 #endif /* chips */ 29261 29262 #if defined(BCM_56840_B0) 29263 { /* SOC_FORMAT_INT_IPRC_BUS_BCM56840_B0fmt */ 29264 /* format IPRC_BUSfmt */ 29265 /* nFields */ 4, 29266 /* *fields */ soc_IPRC_BUS_BCM56840_A0fmt_fields, 29267 /* bits */ 43, 29268 /* flags */ 0, 29269 }, 29270 #endif /* chips */ 29271 29272 #if defined(BCM_56850_A0) 29273 { /* SOC_FORMAT_INT_IPRC_BUS_BCM56850_A0fmt */ 29274 /* format IPRC_BUSfmt */ 29275 /* nFields */ 4, 29276 /* *fields */ soc_IPRC_BUS_BCM56640_A0fmt_fields, 29277 /* bits */ 43, 29278 /* flags */ 0, 29279 }, 29280 #endif /* chips */ 29281 29282 #if defined(BCM_56860_A0) 29283 { /* SOC_FORMAT_INT_IPRC_BUS_BCM56860_A0fmt */ 29284 /* format IPRC_BUSfmt */ 29285 /* nFields */ 4, 29286 /* *fields */ soc_IPRC_BUS_BCM56640_A0fmt_fields, 29287 /* bits */ 43, 29288 /* flags */ 0, 29289 }, 29290 #endif /* chips */ 29291 29292 #if defined(BCM_56870_A0) 29293 { /* SOC_FORMAT_INT_IPRC_BUS_BCM56870_A0fmt */ 29294 /* format IPRC_BUSfmt */ 29295 /* nFields */ 4, 29296 /* *fields */ soc_IPRC_BUS_BCM56960_A0fmt_fields, 29297 /* bits */ 44, 29298 /* flags */ 0, 29299 }, 29300 #endif /* chips */ 29301 29302 #if defined(BCM_56960_A0) 29303 { /* SOC_FORMAT_INT_IPRC_BUS_BCM56960_A0fmt */ 29304 /* format IPRC_BUSfmt */ 29305 /* nFields */ 4, 29306 /* *fields */ soc_IPRC_BUS_BCM56960_A0fmt_fields, 29307 /* bits */ 44, 29308 /* flags */ 0, 29309 }, 29310 #endif /* chips */ 29311 29312 #if defined(BCM_56965_A0) 29313 { /* SOC_FORMAT_INT_IPRC_BUS_BCM56965_A0fmt */ 29314 /* format IPRC_BUSfmt */ 29315 /* nFields */ 4, 29316 /* *fields */ soc_IPRC_BUS_BCM56960_A0fmt_fields, 29317 /* bits */ 44, 29318 /* flags */ 0, 29319 }, 29320 #endif /* chips */ 29321 29322 #if defined(BCM_56970_A0) 29323 { /* SOC_FORMAT_INT_IPRC_BUS_BCM56970_A0fmt */ 29324 /* format IPRC_BUSfmt */ 29325 /* nFields */ 4, 29326 /* *fields */ soc_IPRC_BUS_BCM56960_A0fmt_fields, 29327 /* bits */ 44, 29328 /* flags */ 0, 29329 }, 29330 #endif /* chips */ 29331 29332 #if defined(BCM_56980_A0) 29333 { /* SOC_FORMAT_INT_IPRC_BUS_BCM56980_A0fmt */ 29334 /* format IPRC_BUSfmt */ 29335 /* nFields */ 4, 29336 /* *fields */ soc_IPRC_BUS_BCM56960_A0fmt_fields, 29337 /* bits */ 44, 29338 /* flags */ 0, 29339 }, 29340 #endif /* chips */ 29341 29342 #if defined(BCM_56980_B0) 29343 { /* SOC_FORMAT_INT_IPRC_BUS_BCM56980_B0fmt */ 29344 /* format IPRC_BUSfmt */ 29345 /* nFields */ 4, 29346 /* *fields */ soc_IPRC_BUS_BCM56960_A0fmt_fields, 29347 /* bits */ 44, 29348 /* flags */ 0, 29349 }, 29350 #endif /* chips */ 29351 29352 #if defined(BCM_88732_A0) 29353 { /* SOC_FORMAT_INT_IPRC_BUS_BCM88732_A0fmt */ 29354 /* format IPRC_BUSfmt */ 29355 /* nFields */ 6, 29356 /* *fields */ soc_IPRC_BUS_BCM88732_A0fmt_fields, 29357 /* bits */ 42, 29358 /* flags */ 0, 29359 }, 29360 #endif /* chips */ 29361 29362 #if defined(BCM_53570_B0) 29363 { /* SOC_FORMAT_INT_IPRC_LEARN_BUSfmt */ 29364 /* format IPRC_LEARN_BUSfmt */ 29365 /* nFields */ 3, 29366 /* *fields */ soc_IPRC_LEARN_BUSfmt_fields, 29367 /* bits */ 181, 29368 /* flags */ 0, 29369 }, 29370 #endif /* chips */ 29371 29372 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \ 29373 defined(BCM_56450_B0) || defined(BCM_56450_B1) 29374 { /* SOC_FORMAT_INT_IPROC_INTERRUPTSfmt */ 29375 /* format IPROC_INTERRUPTSfmt */ 29376 /* nFields */ 81, 29377 /* *fields */ soc_IPROC_INTERRUPTSfmt_fields, 29378 /* bits */ 245, 29379 /* flags */ 0, 29380 }, 29381 #endif /* chips */ 29382 29383 #if defined(BCM_53400_A0) 29384 { /* SOC_FORMAT_INT_IPROC_INTERRUPTS_BCM53400_A0fmt */ 29385 /* format IPROC_INTERRUPTSfmt */ 29386 /* nFields */ 204, 29387 /* *fields */ soc_IPROC_INTERRUPTS_BCM53400_A0fmt_fields, 29388 /* bits */ 225, 29389 /* flags */ 0, 29390 }, 29391 #endif /* chips */ 29392 29393 #if defined(BCM_53540_A0) 29394 { /* SOC_FORMAT_INT_IPROC_INTERRUPTS_BCM53540_A0fmt */ 29395 /* format IPROC_INTERRUPTSfmt */ 29396 /* nFields */ 168, 29397 /* *fields */ soc_IPROC_INTERRUPTS_BCM56160_A0fmt_fields, 29398 /* bits */ 189, 29399 /* flags */ 0, 29400 }, 29401 #endif /* chips */ 29402 29403 #if defined(BCM_53570_A0) 29404 { /* SOC_FORMAT_INT_IPROC_INTERRUPTS_BCM53570_A0fmt */ 29405 /* format IPROC_INTERRUPTSfmt */ 29406 /* nFields */ 203, 29407 /* *fields */ soc_IPROC_INTERRUPTS_BCM53570_A0fmt_fields, 29408 /* bits */ 225, 29409 /* flags */ 0, 29410 }, 29411 #endif /* chips */ 29412 29413 #if defined(BCM_53570_B0) 29414 { /* SOC_FORMAT_INT_IPROC_INTERRUPTS_BCM53570_B0fmt */ 29415 /* format IPROC_INTERRUPTSfmt */ 29416 /* nFields */ 203, 29417 /* *fields */ soc_IPROC_INTERRUPTS_BCM53570_A0fmt_fields, 29418 /* bits */ 225, 29419 /* flags */ 0, 29420 }, 29421 #endif /* chips */ 29422 29423 #if defined(BCM_56150_A0) 29424 { /* SOC_FORMAT_INT_IPROC_INTERRUPTS_BCM56150_A0fmt */ 29425 /* format IPROC_INTERRUPTSfmt */ 29426 /* nFields */ 80, 29427 /* *fields */ soc_IPROC_INTERRUPTS_BCM56150_A0fmt_fields, 29428 /* bits */ 246, 29429 /* flags */ 0, 29430 }, 29431 #endif /* chips */ 29432 29433 #if defined(BCM_56160_A0) 29434 { /* SOC_FORMAT_INT_IPROC_INTERRUPTS_BCM56160_A0fmt */ 29435 /* format IPROC_INTERRUPTSfmt */ 29436 /* nFields */ 168, 29437 /* *fields */ soc_IPROC_INTERRUPTS_BCM56160_A0fmt_fields, 29438 /* bits */ 189, 29439 /* flags */ 0, 29440 }, 29441 #endif /* chips */ 29442 29443 #if defined(BCM_56260_A0) 29444 { /* SOC_FORMAT_INT_IPROC_INTERRUPTS_BCM56260_A0fmt */ 29445 /* format IPROC_INTERRUPTSfmt */ 29446 /* nFields */ 204, 29447 /* *fields */ soc_IPROC_INTERRUPTS_BCM53400_A0fmt_fields, 29448 /* bits */ 225, 29449 /* flags */ 0, 29450 }, 29451 #endif /* chips */ 29452 29453 #if defined(BCM_56260_B0) 29454 { /* SOC_FORMAT_INT_IPROC_INTERRUPTS_BCM56260_B0fmt */ 29455 /* format IPROC_INTERRUPTSfmt */ 29456 /* nFields */ 204, 29457 /* *fields */ soc_IPROC_INTERRUPTS_BCM53400_A0fmt_fields, 29458 /* bits */ 225, 29459 /* flags */ 0, 29460 }, 29461 #endif /* chips */ 29462 29463 #if defined(BCM_56270_A0) 29464 { /* SOC_FORMAT_INT_IPROC_INTERRUPTS_BCM56270_A0fmt */ 29465 /* format IPROC_INTERRUPTSfmt */ 29466 /* nFields */ 114, 29467 /* *fields */ soc_IPROC_INTERRUPTS_BCM56960_A0fmt_fields, 29468 /* bits */ 143, 29469 /* flags */ 0, 29470 }, 29471 #endif /* chips */ 29472 29473 #if defined(BCM_56370_A0) 29474 { /* SOC_FORMAT_INT_IPROC_INTERRUPTS_BCM56370_A0fmt */ 29475 /* format IPROC_INTERRUPTSfmt */ 29476 /* nFields */ 225, 29477 /* *fields */ soc_IPROC_INTERRUPTS_BCM56370_A0fmt_fields, 29478 /* bits */ 256, 29479 /* flags */ 0, 29480 }, 29481 #endif /* chips */ 29482 29483 #if defined(BCM_56560_A0) 29484 { /* SOC_FORMAT_INT_IPROC_INTERRUPTS_BCM56560_A0fmt */ 29485 /* format IPROC_INTERRUPTSfmt */ 29486 /* nFields */ 145, 29487 /* *fields */ soc_IPROC_INTERRUPTS_BCM56560_A0fmt_fields, 29488 /* bits */ 168, 29489 /* flags */ 0, 29490 }, 29491 #endif /* chips */ 29492 29493 #if defined(BCM_56560_B0) 29494 { /* SOC_FORMAT_INT_IPROC_INTERRUPTS_BCM56560_B0fmt */ 29495 /* format IPROC_INTERRUPTSfmt */ 29496 /* nFields */ 145, 29497 /* *fields */ soc_IPROC_INTERRUPTS_BCM56560_A0fmt_fields, 29498 /* bits */ 168, 29499 /* flags */ 0, 29500 }, 29501 #endif /* chips */ 29502 29503 #if defined(BCM_56670_A0) 29504 { /* SOC_FORMAT_INT_IPROC_INTERRUPTS_BCM56670_A0fmt */ 29505 /* format IPROC_INTERRUPTSfmt */ 29506 /* nFields */ 148, 29507 /* *fields */ soc_IPROC_INTERRUPTS_BCM56670_A0fmt_fields, 29508 /* bits */ 168, 29509 /* flags */ 0, 29510 }, 29511 #endif /* chips */ 29512 29513 #if defined(BCM_56670_B0) 29514 { /* SOC_FORMAT_INT_IPROC_INTERRUPTS_BCM56670_B0fmt */ 29515 /* format IPROC_INTERRUPTSfmt */ 29516 /* nFields */ 148, 29517 /* *fields */ soc_IPROC_INTERRUPTS_BCM56670_A0fmt_fields, 29518 /* bits */ 168, 29519 /* flags */ 0, 29520 }, 29521 #endif /* chips */ 29522 29523 #if defined(BCM_56770_A0) 29524 { /* SOC_FORMAT_INT_IPROC_INTERRUPTS_BCM56770_A0fmt */ 29525 /* format IPROC_INTERRUPTSfmt */ 29526 /* nFields */ 211, 29527 /* *fields */ soc_IPROC_INTERRUPTS_BCM56870_A0fmt_fields, 29528 /* bits */ 256, 29529 /* flags */ 0, 29530 }, 29531 #endif /* chips */ 29532 29533 #if defined(BCM_56870_A0) 29534 { /* SOC_FORMAT_INT_IPROC_INTERRUPTS_BCM56870_A0fmt */ 29535 /* format IPROC_INTERRUPTSfmt */ 29536 /* nFields */ 211, 29537 /* *fields */ soc_IPROC_INTERRUPTS_BCM56870_A0fmt_fields, 29538 /* bits */ 256, 29539 /* flags */ 0, 29540 }, 29541 #endif /* chips */ 29542 29543 #if defined(BCM_56960_A0) 29544 { /* SOC_FORMAT_INT_IPROC_INTERRUPTS_BCM56960_A0fmt */ 29545 /* format IPROC_INTERRUPTSfmt */ 29546 /* nFields */ 114, 29547 /* *fields */ soc_IPROC_INTERRUPTS_BCM56960_A0fmt_fields, 29548 /* bits */ 143, 29549 /* flags */ 0, 29550 }, 29551 #endif /* chips */ 29552 29553 #if defined(BCM_56965_A0) 29554 { /* SOC_FORMAT_INT_IPROC_INTERRUPTS_BCM56965_A0fmt */ 29555 /* format IPROC_INTERRUPTSfmt */ 29556 /* nFields */ 114, 29557 /* *fields */ soc_IPROC_INTERRUPTS_BCM56960_A0fmt_fields, 29558 /* bits */ 143, 29559 /* flags */ 0, 29560 }, 29561 #endif /* chips */ 29562 29563 #if defined(BCM_56970_A0) 29564 { /* SOC_FORMAT_INT_IPROC_INTERRUPTS_BCM56970_A0fmt */ 29565 /* format IPROC_INTERRUPTSfmt */ 29566 /* nFields */ 152, 29567 /* *fields */ soc_IPROC_INTERRUPTS_BCM56970_A0fmt_fields, 29568 /* bits */ 169, 29569 /* flags */ 0, 29570 }, 29571 #endif /* chips */ 29572 29573 #if defined(BCM_56980_A0) 29574 { /* SOC_FORMAT_INT_IPROC_INTERRUPTS_BCM56980_A0fmt */ 29575 /* format IPROC_INTERRUPTSfmt */ 29576 /* nFields */ 211, 29577 /* *fields */ soc_IPROC_INTERRUPTS_BCM56870_A0fmt_fields, 29578 /* bits */ 256, 29579 /* flags */ 0, 29580 }, 29581 #endif /* chips */ 29582 29583 #if defined(BCM_56980_B0) 29584 { /* SOC_FORMAT_INT_IPROC_INTERRUPTS_BCM56980_B0fmt */ 29585 /* format IPROC_INTERRUPTSfmt */ 29586 /* nFields */ 211, 29587 /* *fields */ soc_IPROC_INTERRUPTS_BCM56870_A0fmt_fields, 29588 /* bits */ 256, 29589 /* flags */ 0, 29590 }, 29591 #endif /* chips */ 29592 29593 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \ 29594 defined(BCM_56450_A0) || defined(BCM_56450_B0) || \ 29595 defined(BCM_56450_B1) || defined(BCM_56640_A0) || \ 29596 defined(BCM_56850_A0) || defined(BCM_56860_A0) 29597 { /* SOC_FORMAT_INT_IPV4_HDRfmt */ 29598 /* format IPV4_HDRfmt */ 29599 /* nFields */ 14, 29600 /* *fields */ soc_IPV4_HDRfmt_fields, 29601 /* bits */ 160, 29602 /* flags */ 0, 29603 }, 29604 #endif /* chips */ 29605 29606 #if defined(BCM_53400_A0) 29607 { /* SOC_FORMAT_INT_IPV4_HDR_BCM53400_A0fmt */ 29608 /* format IPV4_HDRfmt */ 29609 /* nFields */ 14, 29610 /* *fields */ soc_IPV4_HDR_BCM53400_A0fmt_fields, 29611 /* bits */ 160, 29612 /* flags */ 0, 29613 }, 29614 #endif /* chips */ 29615 29616 #if defined(BCM_53540_A0) 29617 { /* SOC_FORMAT_INT_IPV4_HDR_BCM53540_A0fmt */ 29618 /* format IPV4_HDRfmt */ 29619 /* nFields */ 14, 29620 /* *fields */ soc_IPV4_HDR_BCM53400_A0fmt_fields, 29621 /* bits */ 160, 29622 /* flags */ 0, 29623 }, 29624 #endif /* chips */ 29625 29626 #if defined(BCM_53570_A0) 29627 { /* SOC_FORMAT_INT_IPV4_HDR_BCM53570_A0fmt */ 29628 /* format IPV4_HDRfmt */ 29629 /* nFields */ 14, 29630 /* *fields */ soc_IPV4_HDR_BCM53400_A0fmt_fields, 29631 /* bits */ 160, 29632 /* flags */ 0, 29633 }, 29634 #endif /* chips */ 29635 29636 #if defined(BCM_53570_B0) 29637 { /* SOC_FORMAT_INT_IPV4_HDR_BCM53570_B0fmt */ 29638 /* format IPV4_HDRfmt */ 29639 /* nFields */ 14, 29640 /* *fields */ soc_IPV4_HDR_BCM53400_A0fmt_fields, 29641 /* bits */ 160, 29642 /* flags */ 0, 29643 }, 29644 #endif /* chips */ 29645 29646 #if defined(BCM_56160_A0) 29647 { /* SOC_FORMAT_INT_IPV4_HDR_BCM56160_A0fmt */ 29648 /* format IPV4_HDRfmt */ 29649 /* nFields */ 14, 29650 /* *fields */ soc_IPV4_HDR_BCM53400_A0fmt_fields, 29651 /* bits */ 160, 29652 /* flags */ 0, 29653 }, 29654 #endif /* chips */ 29655 29656 #if defined(BCM_56260_A0) 29657 { /* SOC_FORMAT_INT_IPV4_HDR_BCM56260_A0fmt */ 29658 /* format IPV4_HDRfmt */ 29659 /* nFields */ 14, 29660 /* *fields */ soc_IPV4_HDR_BCM53400_A0fmt_fields, 29661 /* bits */ 160, 29662 /* flags */ 0, 29663 }, 29664 #endif /* chips */ 29665 29666 #if defined(BCM_56260_B0) 29667 { /* SOC_FORMAT_INT_IPV4_HDR_BCM56260_B0fmt */ 29668 /* format IPV4_HDRfmt */ 29669 /* nFields */ 14, 29670 /* *fields */ soc_IPV4_HDR_BCM53400_A0fmt_fields, 29671 /* bits */ 160, 29672 /* flags */ 0, 29673 }, 29674 #endif /* chips */ 29675 29676 #if defined(BCM_56270_A0) 29677 { /* SOC_FORMAT_INT_IPV4_HDR_BCM56270_A0fmt */ 29678 /* format IPV4_HDRfmt */ 29679 /* nFields */ 14, 29680 /* *fields */ soc_IPV4_HDR_BCM53400_A0fmt_fields, 29681 /* bits */ 160, 29682 /* flags */ 0, 29683 }, 29684 #endif /* chips */ 29685 29686 #if defined(BCM_56370_A0) 29687 { /* SOC_FORMAT_INT_IPV4_HDR_BCM56370_A0fmt */ 29688 /* format IPV4_HDRfmt */ 29689 /* nFields */ 14, 29690 /* *fields */ soc_IPV4_HDR_BCM56870_A0fmt_fields, 29691 /* bits */ 160, 29692 /* flags */ 0, 29693 }, 29694 #endif /* chips */ 29695 29696 #if defined(BCM_56560_A0) 29697 { /* SOC_FORMAT_INT_IPV4_HDR_BCM56560_A0fmt */ 29698 /* format IPV4_HDRfmt */ 29699 /* nFields */ 14, 29700 /* *fields */ soc_IPV4_HDR_BCM53400_A0fmt_fields, 29701 /* bits */ 160, 29702 /* flags */ 0, 29703 }, 29704 #endif /* chips */ 29705 29706 #if defined(BCM_56560_B0) 29707 { /* SOC_FORMAT_INT_IPV4_HDR_BCM56560_B0fmt */ 29708 /* format IPV4_HDRfmt */ 29709 /* nFields */ 14, 29710 /* *fields */ soc_IPV4_HDR_BCM53400_A0fmt_fields, 29711 /* bits */ 160, 29712 /* flags */ 0, 29713 }, 29714 #endif /* chips */ 29715 29716 #if defined(BCM_56670_A0) 29717 { /* SOC_FORMAT_INT_IPV4_HDR_BCM56670_A0fmt */ 29718 /* format IPV4_HDRfmt */ 29719 /* nFields */ 14, 29720 /* *fields */ soc_IPV4_HDR_BCM53400_A0fmt_fields, 29721 /* bits */ 160, 29722 /* flags */ 0, 29723 }, 29724 #endif /* chips */ 29725 29726 #if defined(BCM_56670_B0) 29727 { /* SOC_FORMAT_INT_IPV4_HDR_BCM56670_B0fmt */ 29728 /* format IPV4_HDRfmt */ 29729 /* nFields */ 14, 29730 /* *fields */ soc_IPV4_HDR_BCM53400_A0fmt_fields, 29731 /* bits */ 160, 29732 /* flags */ 0, 29733 }, 29734 #endif /* chips */ 29735 29736 #if defined(BCM_56770_A0) 29737 { /* SOC_FORMAT_INT_IPV4_HDR_BCM56770_A0fmt */ 29738 /* format IPV4_HDRfmt */ 29739 /* nFields */ 14, 29740 /* *fields */ soc_IPV4_HDR_BCM56870_A0fmt_fields, 29741 /* bits */ 160, 29742 /* flags */ 0, 29743 }, 29744 #endif /* chips */ 29745 29746 #if defined(BCM_56870_A0) 29747 { /* SOC_FORMAT_INT_IPV4_HDR_BCM56870_A0fmt */ 29748 /* format IPV4_HDRfmt */ 29749 /* nFields */ 14, 29750 /* *fields */ soc_IPV4_HDR_BCM56870_A0fmt_fields, 29751 /* bits */ 160, 29752 /* flags */ 0, 29753 }, 29754 #endif /* chips */ 29755 29756 #if defined(BCM_56960_A0) 29757 { /* SOC_FORMAT_INT_IPV4_HDR_BCM56960_A0fmt */ 29758 /* format IPV4_HDRfmt */ 29759 /* nFields */ 14, 29760 /* *fields */ soc_IPV4_HDR_BCM53400_A0fmt_fields, 29761 /* bits */ 160, 29762 /* flags */ 0, 29763 }, 29764 #endif /* chips */ 29765 29766 #if defined(BCM_56965_A0) 29767 { /* SOC_FORMAT_INT_IPV4_HDR_BCM56965_A0fmt */ 29768 /* format IPV4_HDRfmt */ 29769 /* nFields */ 14, 29770 /* *fields */ soc_IPV4_HDR_BCM53400_A0fmt_fields, 29771 /* bits */ 160, 29772 /* flags */ 0, 29773 }, 29774 #endif /* chips */ 29775 29776 #if defined(BCM_56970_A0) 29777 { /* SOC_FORMAT_INT_IPV4_HDR_BCM56970_A0fmt */ 29778 /* format IPV4_HDRfmt */ 29779 /* nFields */ 14, 29780 /* *fields */ soc_IPV4_HDR_BCM53400_A0fmt_fields, 29781 /* bits */ 160, 29782 /* flags */ 0, 29783 }, 29784 #endif /* chips */ 29785 29786 #if defined(BCM_56980_A0) 29787 { /* SOC_FORMAT_INT_IPV4_HDR_BCM56980_A0fmt */ 29788 /* format IPV4_HDRfmt */ 29789 /* nFields */ 14, 29790 /* *fields */ soc_IPV4_HDR_BCM53400_A0fmt_fields, 29791 /* bits */ 160, 29792 /* flags */ 0, 29793 }, 29794 #endif /* chips */ 29795 29796 #if defined(BCM_56980_B0) 29797 { /* SOC_FORMAT_INT_IPV4_HDR_BCM56980_B0fmt */ 29798 /* format IPV4_HDRfmt */ 29799 /* nFields */ 14, 29800 /* *fields */ soc_IPV4_HDR_BCM53400_A0fmt_fields, 29801 /* bits */ 160, 29802 /* flags */ 0, 29803 }, 29804 #endif /* chips */ 29805 29806 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \ 29807 defined(BCM_56450_A0) || defined(BCM_56450_B0) || \ 29808 defined(BCM_56450_B1) || defined(BCM_56640_A0) || \ 29809 defined(BCM_56850_A0) || defined(BCM_56860_A0) 29810 { /* SOC_FORMAT_INT_IPV6_HDRfmt */ 29811 /* format IPV6_HDRfmt */ 29812 /* nFields */ 8, 29813 /* *fields */ soc_IPV6_HDRfmt_fields, 29814 /* bits */ 320, 29815 /* flags */ 0, 29816 }, 29817 #endif /* chips */ 29818 29819 #if defined(BCM_53400_A0) 29820 { /* SOC_FORMAT_INT_IPV6_HDR_BCM53400_A0fmt */ 29821 /* format IPV6_HDRfmt */ 29822 /* nFields */ 8, 29823 /* *fields */ soc_IPV6_HDR_BCM53400_A0fmt_fields, 29824 /* bits */ 320, 29825 /* flags */ 0, 29826 }, 29827 #endif /* chips */ 29828 29829 #if defined(BCM_53540_A0) 29830 { /* SOC_FORMAT_INT_IPV6_HDR_BCM53540_A0fmt */ 29831 /* format IPV6_HDRfmt */ 29832 /* nFields */ 8, 29833 /* *fields */ soc_IPV6_HDR_BCM53400_A0fmt_fields, 29834 /* bits */ 320, 29835 /* flags */ 0, 29836 }, 29837 #endif /* chips */ 29838 29839 #if defined(BCM_53570_A0) 29840 { /* SOC_FORMAT_INT_IPV6_HDR_BCM53570_A0fmt */ 29841 /* format IPV6_HDRfmt */ 29842 /* nFields */ 8, 29843 /* *fields */ soc_IPV6_HDR_BCM53400_A0fmt_fields, 29844 /* bits */ 320, 29845 /* flags */ 0, 29846 }, 29847 #endif /* chips */ 29848 29849 #if defined(BCM_53570_B0) 29850 { /* SOC_FORMAT_INT_IPV6_HDR_BCM53570_B0fmt */ 29851 /* format IPV6_HDRfmt */ 29852 /* nFields */ 8, 29853 /* *fields */ soc_IPV6_HDR_BCM53400_A0fmt_fields, 29854 /* bits */ 320, 29855 /* flags */ 0, 29856 }, 29857 #endif /* chips */ 29858 29859 #if defined(BCM_56160_A0) 29860 { /* SOC_FORMAT_INT_IPV6_HDR_BCM56160_A0fmt */ 29861 /* format IPV6_HDRfmt */ 29862 /* nFields */ 8, 29863 /* *fields */ soc_IPV6_HDR_BCM53400_A0fmt_fields, 29864 /* bits */ 320, 29865 /* flags */ 0, 29866 }, 29867 #endif /* chips */ 29868 29869 #if defined(BCM_56260_A0) 29870 { /* SOC_FORMAT_INT_IPV6_HDR_BCM56260_A0fmt */ 29871 /* format IPV6_HDRfmt */ 29872 /* nFields */ 8, 29873 /* *fields */ soc_IPV6_HDR_BCM53400_A0fmt_fields, 29874 /* bits */ 320, 29875 /* flags */ 0, 29876 }, 29877 #endif /* chips */ 29878 29879 #if defined(BCM_56260_B0) 29880 { /* SOC_FORMAT_INT_IPV6_HDR_BCM56260_B0fmt */ 29881 /* format IPV6_HDRfmt */ 29882 /* nFields */ 8, 29883 /* *fields */ soc_IPV6_HDR_BCM53400_A0fmt_fields, 29884 /* bits */ 320, 29885 /* flags */ 0, 29886 }, 29887 #endif /* chips */ 29888 29889 #if defined(BCM_56270_A0) 29890 { /* SOC_FORMAT_INT_IPV6_HDR_BCM56270_A0fmt */ 29891 /* format IPV6_HDRfmt */ 29892 /* nFields */ 8, 29893 /* *fields */ soc_IPV6_HDR_BCM53400_A0fmt_fields, 29894 /* bits */ 320, 29895 /* flags */ 0, 29896 }, 29897 #endif /* chips */ 29898 29899 #if defined(BCM_56370_A0) 29900 { /* SOC_FORMAT_INT_IPV6_HDR_BCM56370_A0fmt */ 29901 /* format IPV6_HDRfmt */ 29902 /* nFields */ 8, 29903 /* *fields */ soc_IPV6_HDR_BCM56870_A0fmt_fields, 29904 /* bits */ 320, 29905 /* flags */ 0, 29906 }, 29907 #endif /* chips */ 29908 29909 #if defined(BCM_56560_A0) 29910 { /* SOC_FORMAT_INT_IPV6_HDR_BCM56560_A0fmt */ 29911 /* format IPV6_HDRfmt */ 29912 /* nFields */ 8, 29913 /* *fields */ soc_IPV6_HDR_BCM53400_A0fmt_fields, 29914 /* bits */ 320, 29915 /* flags */ 0, 29916 }, 29917 #endif /* chips */ 29918 29919 #if defined(BCM_56560_B0) 29920 { /* SOC_FORMAT_INT_IPV6_HDR_BCM56560_B0fmt */ 29921 /* format IPV6_HDRfmt */ 29922 /* nFields */ 8, 29923 /* *fields */ soc_IPV6_HDR_BCM53400_A0fmt_fields, 29924 /* bits */ 320, 29925 /* flags */ 0, 29926 }, 29927 #endif /* chips */ 29928 29929 #if defined(BCM_56670_A0) 29930 { /* SOC_FORMAT_INT_IPV6_HDR_BCM56670_A0fmt */ 29931 /* format IPV6_HDRfmt */ 29932 /* nFields */ 8, 29933 /* *fields */ soc_IPV6_HDR_BCM53400_A0fmt_fields, 29934 /* bits */ 320, 29935 /* flags */ 0, 29936 }, 29937 #endif /* chips */ 29938 29939 #if defined(BCM_56670_B0) 29940 { /* SOC_FORMAT_INT_IPV6_HDR_BCM56670_B0fmt */ 29941 /* format IPV6_HDRfmt */ 29942 /* nFields */ 8, 29943 /* *fields */ soc_IPV6_HDR_BCM53400_A0fmt_fields, 29944 /* bits */ 320, 29945 /* flags */ 0, 29946 }, 29947 #endif /* chips */ 29948 29949 #if defined(BCM_56770_A0) 29950 { /* SOC_FORMAT_INT_IPV6_HDR_BCM56770_A0fmt */ 29951 /* format IPV6_HDRfmt */ 29952 /* nFields */ 8, 29953 /* *fields */ soc_IPV6_HDR_BCM56870_A0fmt_fields, 29954 /* bits */ 320, 29955 /* flags */ 0, 29956 }, 29957 #endif /* chips */ 29958 29959 #if defined(BCM_56870_A0) 29960 { /* SOC_FORMAT_INT_IPV6_HDR_BCM56870_A0fmt */ 29961 /* format IPV6_HDRfmt */ 29962 /* nFields */ 8, 29963 /* *fields */ soc_IPV6_HDR_BCM56870_A0fmt_fields, 29964 /* bits */ 320, 29965 /* flags */ 0, 29966 }, 29967 #endif /* chips */ 29968 29969 #if defined(BCM_56960_A0) 29970 { /* SOC_FORMAT_INT_IPV6_HDR_BCM56960_A0fmt */ 29971 /* format IPV6_HDRfmt */ 29972 /* nFields */ 8, 29973 /* *fields */ soc_IPV6_HDR_BCM53400_A0fmt_fields, 29974 /* bits */ 320, 29975 /* flags */ 0, 29976 }, 29977 #endif /* chips */ 29978 29979 #if defined(BCM_56965_A0) 29980 { /* SOC_FORMAT_INT_IPV6_HDR_BCM56965_A0fmt */ 29981 /* format IPV6_HDRfmt */ 29982 /* nFields */ 8, 29983 /* *fields */ soc_IPV6_HDR_BCM53400_A0fmt_fields, 29984 /* bits */ 320, 29985 /* flags */ 0, 29986 }, 29987 #endif /* chips */ 29988 29989 #if defined(BCM_56970_A0) 29990 { /* SOC_FORMAT_INT_IPV6_HDR_BCM56970_A0fmt */ 29991 /* format IPV6_HDRfmt */ 29992 /* nFields */ 8, 29993 /* *fields */ soc_IPV6_HDR_BCM53400_A0fmt_fields, 29994 /* bits */ 320, 29995 /* flags */ 0, 29996 }, 29997 #endif /* chips */ 29998 29999 #if defined(BCM_56980_A0) 30000 { /* SOC_FORMAT_INT_IPV6_HDR_BCM56980_A0fmt */ 30001 /* format IPV6_HDRfmt */ 30002 /* nFields */ 8, 30003 /* *fields */ soc_IPV6_HDR_BCM53400_A0fmt_fields, 30004 /* bits */ 320, 30005 /* flags */ 0, 30006 }, 30007 #endif /* chips */ 30008 30009 #if defined(BCM_56980_B0) 30010 { /* SOC_FORMAT_INT_IPV6_HDR_BCM56980_B0fmt */ 30011 /* format IPV6_HDRfmt */ 30012 /* nFields */ 8, 30013 /* *fields */ soc_IPV6_HDR_BCM53400_A0fmt_fields, 30014 /* bits */ 320, 30015 /* flags */ 0, 30016 }, 30017 #endif /* chips */ 30018 30019 #if defined(BCM_56640_A0) 30020 { /* SOC_FORMAT_INT_IP_AXP_INFOfmt */ 30021 /* format IP_AXP_INFOfmt */ 30022 /* nFields */ 1, 30023 /* *fields */ soc_AXP_NLF_INFOfmt_fields, 30024 /* bits */ 1, 30025 /* flags */ 0, 30026 }, 30027 #endif /* chips */ 30028 30029 #if defined(BCM_56340_A0) 30030 { /* SOC_FORMAT_INT_IP_AXP_INFO_BCM56340_A0fmt */ 30031 /* format IP_AXP_INFOfmt */ 30032 /* nFields */ 1, 30033 /* *fields */ soc_AXP_NLF_INFOfmt_fields, 30034 /* bits */ 1, 30035 /* flags */ 0, 30036 }, 30037 #endif /* chips */ 30038 30039 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 30040 defined(BCM_56870_A0) 30041 { /* SOC_FORMAT_INT_IP_IN_IP_TUNNEL_ACTION_SETfmt */ 30042 /* format IP_IN_IP_TUNNEL_ACTION_SETfmt */ 30043 /* nFields */ 10, 30044 /* *fields */ soc_IP_IN_IP_TUNNEL_ACTION_SETfmt_fields, 30045 /* bits */ 12, 30046 /* flags */ 0, 30047 }, 30048 #endif /* chips */ 30049 30050 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 30051 defined(BCM_56870_A0) 30052 { /* SOC_FORMAT_INT_IP_OPTION_CONTROL_PROFILE_TABLE_INDEXfmt */ 30053 /* format IP_OPTION_CONTROL_PROFILE_TABLE_INDEXfmt */ 30054 /* nFields */ 2, 30055 /* *fields */ soc_IP_OPTION_CONTROL_PROFILE_TABLE_INDEXfmt_fields, 30056 /* bits */ 10, 30057 /* flags */ 0, 30058 }, 30059 #endif /* chips */ 30060 30061 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 30062 defined(BCM_56870_A0) 30063 { /* SOC_FORMAT_INT_IP_PARSER0_FLEX_HVE_CONTROLSfmt */ 30064 /* format IP_PARSER0_FLEX_HVE_CONTROLSfmt */ 30065 /* nFields */ 33, 30066 /* *fields */ soc_IP_PARSER0_FLEX_HVE_CONTROLSfmt_fields, 30067 /* bits */ 33, 30068 /* flags */ 0, 30069 }, 30070 #endif /* chips */ 30071 30072 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 30073 defined(BCM_56870_A0) 30074 { /* SOC_FORMAT_INT_IP_PARSER0_FLEX_HVE_IN_BUSfmt */ 30075 /* format IP_PARSER0_FLEX_HVE_IN_BUSfmt */ 30076 /* nFields */ 36, 30077 /* *fields */ soc_IP_PARSER0_FLEX_HVE_IN_BUSfmt_fields, 30078 /* bits */ 733, 30079 /* flags */ 0, 30080 }, 30081 #endif /* chips */ 30082 30083 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 30084 defined(BCM_56870_A0) 30085 { /* SOC_FORMAT_INT_IP_PARSER0_FLEX_HVE_OUT_BUSfmt */ 30086 /* format IP_PARSER0_FLEX_HVE_OUT_BUSfmt */ 30087 /* nFields */ 44, 30088 /* *fields */ soc_IP_PARSER0_FLEX_HVE_OUT_BUSfmt_fields, 30089 /* bits */ 110, 30090 /* flags */ 0, 30091 }, 30092 #endif /* chips */ 30093 30094 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 30095 defined(BCM_56870_A0) 30096 { /* SOC_FORMAT_INT_IP_PARSER0_FLEX_HVE_OUT_CHECKfmt */ 30097 /* format IP_PARSER0_FLEX_HVE_OUT_CHECKfmt */ 30098 /* nFields */ 3, 30099 /* *fields */ soc_IP_PARSER0_FLEX_HVE_OUT_CHECKfmt_fields, 30100 /* bits */ 10, 30101 /* flags */ 0, 30102 }, 30103 #endif /* chips */ 30104 30105 #if defined(BCM_56870_A0) 30106 { /* SOC_FORMAT_INT_IP_PARSER0_HFE_CMD_POLICY_DATAfmt */ 30107 /* format IP_PARSER0_HFE_CMD_POLICY_DATAfmt */ 30108 /* nFields */ 78, 30109 /* *fields */ soc_EP_PARSER0_HFE_CMD_POLICY_DATAfmt_fields, 30110 /* bits */ 262, 30111 /* flags */ 0, 30112 }, 30113 #endif /* chips */ 30114 30115 #if defined(BCM_56370_A0) 30116 { /* SOC_FORMAT_INT_IP_PARSER0_HFE_CMD_POLICY_DATA_BCM56370_A0fmt */ 30117 /* format IP_PARSER0_HFE_CMD_POLICY_DATAfmt */ 30118 /* nFields */ 78, 30119 /* *fields */ soc_EP_PARSER0_HFE_CMD_POLICY_DATAfmt_fields, 30120 /* bits */ 262, 30121 /* flags */ 0, 30122 }, 30123 #endif /* chips */ 30124 30125 #if defined(BCM_56770_A0) 30126 { /* SOC_FORMAT_INT_IP_PARSER0_HFE_CMD_POLICY_DATA_BCM56770_A0fmt */ 30127 /* format IP_PARSER0_HFE_CMD_POLICY_DATAfmt */ 30128 /* nFields */ 78, 30129 /* *fields */ soc_EP_PARSER0_HFE_CMD_POLICY_DATAfmt_fields, 30130 /* bits */ 262, 30131 /* flags */ 0, 30132 }, 30133 #endif /* chips */ 30134 30135 #if defined(BCM_56870_A0) 30136 { /* SOC_FORMAT_INT_IP_PARSER0_HFE_CONSTANTSfmt */ 30137 /* format IP_PARSER0_HFE_CONSTANTSfmt */ 30138 /* nFields */ 1, 30139 /* *fields */ soc_EP_PARSER0_HFE_CONSTANTSfmt_fields, 30140 /* bits */ 1, 30141 /* flags */ 0, 30142 }, 30143 #endif /* chips */ 30144 30145 #if defined(BCM_56370_A0) 30146 { /* SOC_FORMAT_INT_IP_PARSER0_HFE_CONSTANTS_BCM56370_A0fmt */ 30147 /* format IP_PARSER0_HFE_CONSTANTSfmt */ 30148 /* nFields */ 1, 30149 /* *fields */ soc_EP_PARSER0_HFE_CONSTANTSfmt_fields, 30150 /* bits */ 1, 30151 /* flags */ 0, 30152 }, 30153 #endif /* chips */ 30154 30155 #if defined(BCM_56770_A0) 30156 { /* SOC_FORMAT_INT_IP_PARSER0_HFE_CONSTANTS_BCM56770_A0fmt */ 30157 /* format IP_PARSER0_HFE_CONSTANTSfmt */ 30158 /* nFields */ 1, 30159 /* *fields */ soc_EP_PARSER0_HFE_CONSTANTSfmt_fields, 30160 /* bits */ 1, 30161 /* flags */ 0, 30162 }, 30163 #endif /* chips */ 30164 30165 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 30166 defined(BCM_56870_A0) 30167 { /* SOC_FORMAT_INT_IP_PARSER0_HFE_CONTROLSfmt */ 30168 /* format IP_PARSER0_HFE_CONTROLSfmt */ 30169 /* nFields */ 8, 30170 /* *fields */ soc_IP_PARSER0_HFE_CONTROLSfmt_fields, 30171 /* bits */ 38, 30172 /* flags */ 0, 30173 }, 30174 #endif /* chips */ 30175 30176 #if defined(BCM_56870_A0) 30177 { /* SOC_FORMAT_INT_IP_PARSER0_HFE_CONT_PROFILEfmt */ 30178 /* format IP_PARSER0_HFE_CONT_PROFILEfmt */ 30179 /* nFields */ 3, 30180 /* *fields */ soc_EP_PARSER0_HFE_CONT_PROFILEfmt_fields, 30181 /* bits */ 5, 30182 /* flags */ 0, 30183 }, 30184 #endif /* chips */ 30185 30186 #if defined(BCM_56370_A0) 30187 { /* SOC_FORMAT_INT_IP_PARSER0_HFE_CONT_PROFILE_BCM56370_A0fmt */ 30188 /* format IP_PARSER0_HFE_CONT_PROFILEfmt */ 30189 /* nFields */ 3, 30190 /* *fields */ soc_EP_PARSER0_HFE_CONT_PROFILEfmt_fields, 30191 /* bits */ 5, 30192 /* flags */ 0, 30193 }, 30194 #endif /* chips */ 30195 30196 #if defined(BCM_56770_A0) 30197 { /* SOC_FORMAT_INT_IP_PARSER0_HFE_CONT_PROFILE_BCM56770_A0fmt */ 30198 /* format IP_PARSER0_HFE_CONT_PROFILEfmt */ 30199 /* nFields */ 3, 30200 /* *fields */ soc_EP_PARSER0_HFE_CONT_PROFILEfmt_fields, 30201 /* bits */ 5, 30202 /* flags */ 0, 30203 }, 30204 #endif /* chips */ 30205 30206 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 30207 defined(BCM_56870_A0) 30208 { /* SOC_FORMAT_INT_IP_PARSER0_HFE_IN_BUSfmt */ 30209 /* format IP_PARSER0_HFE_IN_BUSfmt */ 30210 /* nFields */ 10, 30211 /* *fields */ soc_IP_PARSER0_HFE_IN_BUSfmt_fields, 30212 /* bits */ 1318, 30213 /* flags */ 0, 30214 }, 30215 #endif /* chips */ 30216 30217 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 30218 defined(BCM_56870_A0) 30219 { /* SOC_FORMAT_INT_IP_PARSER0_HFE_MUX_CONTROLSfmt */ 30220 /* format IP_PARSER0_HFE_MUX_CONTROLSfmt */ 30221 /* nFields */ 5, 30222 /* *fields */ soc_IP_PARSER0_HFE_MUX_CONTROLSfmt_fields, 30223 /* bits */ 30, 30224 /* flags */ 0, 30225 }, 30226 #endif /* chips */ 30227 30228 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 30229 defined(BCM_56870_A0) 30230 { /* SOC_FORMAT_INT_IP_PARSER0_HFE_MUX_IN_BUSfmt */ 30231 /* format IP_PARSER0_HFE_MUX_IN_BUSfmt */ 30232 /* nFields */ 20, 30233 /* *fields */ soc_IP_PARSER0_HFE_MUX_IN_BUSfmt_fields, 30234 /* bits */ 1632, 30235 /* flags */ 0, 30236 }, 30237 #endif /* chips */ 30238 30239 #if defined(BCM_56870_A0) 30240 { /* SOC_FORMAT_INT_IP_PARSER0_HFE_MUX_OUT_BUSfmt */ 30241 /* format IP_PARSER0_HFE_MUX_OUT_BUSfmt */ 30242 /* nFields */ 97, 30243 /* *fields */ soc_EP_PARSER0_HFE_MUX_OUT_BUSfmt_fields, 30244 /* bits */ 699, 30245 /* flags */ 0, 30246 }, 30247 #endif /* chips */ 30248 30249 #if defined(BCM_56370_A0) 30250 { /* SOC_FORMAT_INT_IP_PARSER0_HFE_MUX_OUT_BUS_BCM56370_A0fmt */ 30251 /* format IP_PARSER0_HFE_MUX_OUT_BUSfmt */ 30252 /* nFields */ 97, 30253 /* *fields */ soc_EP_PARSER0_HFE_MUX_OUT_BUSfmt_fields, 30254 /* bits */ 699, 30255 /* flags */ 0, 30256 }, 30257 #endif /* chips */ 30258 30259 #if defined(BCM_56770_A0) 30260 { /* SOC_FORMAT_INT_IP_PARSER0_HFE_MUX_OUT_BUS_BCM56770_A0fmt */ 30261 /* format IP_PARSER0_HFE_MUX_OUT_BUSfmt */ 30262 /* nFields */ 97, 30263 /* *fields */ soc_EP_PARSER0_HFE_MUX_OUT_BUSfmt_fields, 30264 /* bits */ 699, 30265 /* flags */ 0, 30266 }, 30267 #endif /* chips */ 30268 30269 #if defined(BCM_56870_A0) 30270 { /* SOC_FORMAT_INT_IP_PARSER0_HFE_OUT_BUSfmt */ 30271 /* format IP_PARSER0_HFE_OUT_BUSfmt */ 30272 /* nFields */ 98, 30273 /* *fields */ soc_EP_PARSER0_HFE_OUT_BUSfmt_fields, 30274 /* bits */ 699, 30275 /* flags */ 0, 30276 }, 30277 #endif /* chips */ 30278 30279 #if defined(BCM_56370_A0) 30280 { /* SOC_FORMAT_INT_IP_PARSER0_HFE_OUT_BUS_BCM56370_A0fmt */ 30281 /* format IP_PARSER0_HFE_OUT_BUSfmt */ 30282 /* nFields */ 98, 30283 /* *fields */ soc_EP_PARSER0_HFE_OUT_BUSfmt_fields, 30284 /* bits */ 699, 30285 /* flags */ 0, 30286 }, 30287 #endif /* chips */ 30288 30289 #if defined(BCM_56770_A0) 30290 { /* SOC_FORMAT_INT_IP_PARSER0_HFE_OUT_BUS_BCM56770_A0fmt */ 30291 /* format IP_PARSER0_HFE_OUT_BUSfmt */ 30292 /* nFields */ 98, 30293 /* *fields */ soc_EP_PARSER0_HFE_OUT_BUSfmt_fields, 30294 /* bits */ 699, 30295 /* flags */ 0, 30296 }, 30297 #endif /* chips */ 30298 30299 #if defined(BCM_56870_A0) 30300 { /* SOC_FORMAT_INT_IP_PARSER0_HFE_POLICY_COMMAND_Afmt */ 30301 /* format IP_PARSER0_HFE_POLICY_COMMAND_Afmt */ 30302 /* nFields */ 2, 30303 /* *fields */ soc_EP_PARSER0_HFE_POLICY_COMMAND_Afmt_fields, 30304 /* bits */ 10, 30305 /* flags */ 0, 30306 }, 30307 #endif /* chips */ 30308 30309 #if defined(BCM_56370_A0) 30310 { /* SOC_FORMAT_INT_IP_PARSER0_HFE_POLICY_COMMAND_A_BCM56370_A0fmt */ 30311 /* format IP_PARSER0_HFE_POLICY_COMMAND_Afmt */ 30312 /* nFields */ 2, 30313 /* *fields */ soc_EP_PARSER0_HFE_POLICY_COMMAND_Afmt_fields, 30314 /* bits */ 10, 30315 /* flags */ 0, 30316 }, 30317 #endif /* chips */ 30318 30319 #if defined(BCM_56770_A0) 30320 { /* SOC_FORMAT_INT_IP_PARSER0_HFE_POLICY_COMMAND_A_BCM56770_A0fmt */ 30321 /* format IP_PARSER0_HFE_POLICY_COMMAND_Afmt */ 30322 /* nFields */ 2, 30323 /* *fields */ soc_EP_PARSER0_HFE_POLICY_COMMAND_Afmt_fields, 30324 /* bits */ 10, 30325 /* flags */ 0, 30326 }, 30327 #endif /* chips */ 30328 30329 #if defined(BCM_56870_A0) 30330 { /* SOC_FORMAT_INT_IP_PARSER0_HFE_POLICY_COMMAND_Bfmt */ 30331 /* format IP_PARSER0_HFE_POLICY_COMMAND_Bfmt */ 30332 /* nFields */ 5, 30333 /* *fields */ soc_EP_PARSER0_HFE_POLICY_COMMAND_Bfmt_fields, 30334 /* bits */ 21, 30335 /* flags */ 0, 30336 }, 30337 #endif /* chips */ 30338 30339 #if defined(BCM_56370_A0) 30340 { /* SOC_FORMAT_INT_IP_PARSER0_HFE_POLICY_COMMAND_B_BCM56370_A0fmt */ 30341 /* format IP_PARSER0_HFE_POLICY_COMMAND_Bfmt */ 30342 /* nFields */ 5, 30343 /* *fields */ soc_EP_PARSER0_HFE_POLICY_COMMAND_Bfmt_fields, 30344 /* bits */ 21, 30345 /* flags */ 0, 30346 }, 30347 #endif /* chips */ 30348 30349 #if defined(BCM_56770_A0) 30350 { /* SOC_FORMAT_INT_IP_PARSER0_HFE_POLICY_COMMAND_B_BCM56770_A0fmt */ 30351 /* format IP_PARSER0_HFE_POLICY_COMMAND_Bfmt */ 30352 /* nFields */ 5, 30353 /* *fields */ soc_EP_PARSER0_HFE_POLICY_COMMAND_Bfmt_fields, 30354 /* bits */ 21, 30355 /* flags */ 0, 30356 }, 30357 #endif /* chips */ 30358 30359 #if defined(BCM_56870_A0) 30360 { /* SOC_FORMAT_INT_IP_PARSER0_HFE_POLICY_COMMAND_Cfmt */ 30361 /* format IP_PARSER0_HFE_POLICY_COMMAND_Cfmt */ 30362 /* nFields */ 4, 30363 /* *fields */ soc_EP_PARSER0_HFE_POLICY_COMMAND_Cfmt_fields, 30364 /* bits */ 2, 30365 /* flags */ 0, 30366 }, 30367 #endif /* chips */ 30368 30369 #if defined(BCM_56370_A0) 30370 { /* SOC_FORMAT_INT_IP_PARSER0_HFE_POLICY_COMMAND_C_BCM56370_A0fmt */ 30371 /* format IP_PARSER0_HFE_POLICY_COMMAND_Cfmt */ 30372 /* nFields */ 4, 30373 /* *fields */ soc_EP_PARSER0_HFE_POLICY_COMMAND_Cfmt_fields, 30374 /* bits */ 2, 30375 /* flags */ 0, 30376 }, 30377 #endif /* chips */ 30378 30379 #if defined(BCM_56770_A0) 30380 { /* SOC_FORMAT_INT_IP_PARSER0_HFE_POLICY_COMMAND_C_BCM56770_A0fmt */ 30381 /* format IP_PARSER0_HFE_POLICY_COMMAND_Cfmt */ 30382 /* nFields */ 4, 30383 /* *fields */ soc_EP_PARSER0_HFE_POLICY_COMMAND_Cfmt_fields, 30384 /* bits */ 2, 30385 /* flags */ 0, 30386 }, 30387 #endif /* chips */ 30388 30389 #if defined(BCM_56870_A0) 30390 { /* SOC_FORMAT_INT_IP_PARSER0_HFE_POLICY_COMMAND_Dfmt */ 30391 /* format IP_PARSER0_HFE_POLICY_COMMAND_Dfmt */ 30392 /* nFields */ 5, 30393 /* *fields */ soc_EP_PARSER0_HFE_POLICY_COMMAND_Dfmt_fields, 30394 /* bits */ 4, 30395 /* flags */ 0, 30396 }, 30397 #endif /* chips */ 30398 30399 #if defined(BCM_56370_A0) 30400 { /* SOC_FORMAT_INT_IP_PARSER0_HFE_POLICY_COMMAND_D_BCM56370_A0fmt */ 30401 /* format IP_PARSER0_HFE_POLICY_COMMAND_Dfmt */ 30402 /* nFields */ 5, 30403 /* *fields */ soc_EP_PARSER0_HFE_POLICY_COMMAND_Dfmt_fields, 30404 /* bits */ 4, 30405 /* flags */ 0, 30406 }, 30407 #endif /* chips */ 30408 30409 #if defined(BCM_56770_A0) 30410 { /* SOC_FORMAT_INT_IP_PARSER0_HFE_POLICY_COMMAND_D_BCM56770_A0fmt */ 30411 /* format IP_PARSER0_HFE_POLICY_COMMAND_Dfmt */ 30412 /* nFields */ 5, 30413 /* *fields */ soc_EP_PARSER0_HFE_POLICY_COMMAND_Dfmt_fields, 30414 /* bits */ 4, 30415 /* flags */ 0, 30416 }, 30417 #endif /* chips */ 30418 30419 #if defined(BCM_56870_A0) 30420 { /* SOC_FORMAT_INT_IP_PARSER0_HFE_POLICY_TABLE_DATAfmt */ 30421 /* format IP_PARSER0_HFE_POLICY_TABLE_DATAfmt */ 30422 /* nFields */ 13, 30423 /* *fields */ soc_EP_PARSER0_HFE_POLICY_TABLE_DATAfmt_fields, 30424 /* bits */ 286, 30425 /* flags */ 0, 30426 }, 30427 #endif /* chips */ 30428 30429 #if defined(BCM_56370_A0) 30430 { /* SOC_FORMAT_INT_IP_PARSER0_HFE_POLICY_TABLE_DATA_BCM56370_A0fmt */ 30431 /* format IP_PARSER0_HFE_POLICY_TABLE_DATAfmt */ 30432 /* nFields */ 13, 30433 /* *fields */ soc_EP_PARSER0_HFE_POLICY_TABLE_DATAfmt_fields, 30434 /* bits */ 286, 30435 /* flags */ 0, 30436 }, 30437 #endif /* chips */ 30438 30439 #if defined(BCM_56770_A0) 30440 { /* SOC_FORMAT_INT_IP_PARSER0_HFE_POLICY_TABLE_DATA_BCM56770_A0fmt */ 30441 /* format IP_PARSER0_HFE_POLICY_TABLE_DATAfmt */ 30442 /* nFields */ 13, 30443 /* *fields */ soc_EP_PARSER0_HFE_POLICY_TABLE_DATAfmt_fields, 30444 /* bits */ 286, 30445 /* flags */ 0, 30446 }, 30447 #endif /* chips */ 30448 30449 #if defined(BCM_56870_A0) 30450 { /* SOC_FORMAT_INT_IP_PARSER0_HME_CONSTANTSfmt */ 30451 /* format IP_PARSER0_HME_CONSTANTSfmt */ 30452 /* nFields */ 1, 30453 /* *fields */ soc_EP_PARSER0_HFE_CONSTANTSfmt_fields, 30454 /* bits */ 1, 30455 /* flags */ 0, 30456 }, 30457 #endif /* chips */ 30458 30459 #if defined(BCM_56370_A0) 30460 { /* SOC_FORMAT_INT_IP_PARSER0_HME_CONSTANTS_BCM56370_A0fmt */ 30461 /* format IP_PARSER0_HME_CONSTANTSfmt */ 30462 /* nFields */ 1, 30463 /* *fields */ soc_EP_PARSER0_HFE_CONSTANTSfmt_fields, 30464 /* bits */ 1, 30465 /* flags */ 0, 30466 }, 30467 #endif /* chips */ 30468 30469 #if defined(BCM_56770_A0) 30470 { /* SOC_FORMAT_INT_IP_PARSER0_HME_CONSTANTS_BCM56770_A0fmt */ 30471 /* format IP_PARSER0_HME_CONSTANTSfmt */ 30472 /* nFields */ 1, 30473 /* *fields */ soc_EP_PARSER0_HFE_CONSTANTSfmt_fields, 30474 /* bits */ 1, 30475 /* flags */ 0, 30476 }, 30477 #endif /* chips */ 30478 30479 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 30480 defined(BCM_56870_A0) 30481 { /* SOC_FORMAT_INT_IP_PARSER0_HME_IN_BUSfmt */ 30482 /* format IP_PARSER0_HME_IN_BUSfmt */ 30483 /* nFields */ 11, 30484 /* *fields */ soc_IP_PARSER0_HME_IN_BUSfmt_fields, 30485 /* bits */ 1363, 30486 /* flags */ 0, 30487 }, 30488 #endif /* chips */ 30489 30490 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 30491 defined(BCM_56870_A0) 30492 { /* SOC_FORMAT_INT_IP_PARSER0_HME_LATENCY_CONTROLSfmt */ 30493 /* format IP_PARSER0_HME_LATENCY_CONTROLSfmt */ 30494 /* nFields */ 2, 30495 /* *fields */ soc_IP_PARSER0_HME_LATENCY_CONTROLSfmt_fields, 30496 /* bits */ 2, 30497 /* flags */ 0, 30498 }, 30499 #endif /* chips */ 30500 30501 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 30502 defined(BCM_56870_A0) 30503 { /* SOC_FORMAT_INT_IP_PARSER0_HME_OUT_BUSfmt */ 30504 /* format IP_PARSER0_HME_OUT_BUSfmt */ 30505 /* nFields */ 16, 30506 /* *fields */ soc_IP_PARSER0_HME_OUT_BUSfmt_fields, 30507 /* bits */ 1415, 30508 /* flags */ 0, 30509 }, 30510 #endif /* chips */ 30511 30512 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 30513 defined(BCM_56870_A0) 30514 { /* SOC_FORMAT_INT_IP_PARSER0_HME_PASSTHROUGH_BUSfmt */ 30515 /* format IP_PARSER0_HME_PASSTHROUGH_BUSfmt */ 30516 /* nFields */ 4, 30517 /* *fields */ soc_IP_PARSER0_HME_PASSTHROUGH_BUSfmt_fields, 30518 /* bits */ 3, 30519 /* flags */ 0, 30520 }, 30521 #endif /* chips */ 30522 30523 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 30524 defined(BCM_56870_A0) 30525 { /* SOC_FORMAT_INT_IP_PARSER0_HME_POLICY_ACTIONfmt */ 30526 /* format IP_PARSER0_HME_POLICY_ACTIONfmt */ 30527 /* nFields */ 3, 30528 /* *fields */ soc_IP_PARSER0_HME_POLICY_ACTIONfmt_fields, 30529 /* bits */ 3, 30530 /* flags */ 0, 30531 }, 30532 #endif /* chips */ 30533 30534 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 30535 defined(BCM_56870_A0) 30536 { /* SOC_FORMAT_INT_IP_PARSER0_HME_STAGE_COMMON_BUSfmt */ 30537 /* format IP_PARSER0_HME_STAGE_COMMON_BUSfmt */ 30538 /* nFields */ 3, 30539 /* *fields */ soc_IP_PARSER0_HME_STAGE_COMMON_BUSfmt_fields, 30540 /* bits */ 10, 30541 /* flags */ 0, 30542 }, 30543 #endif /* chips */ 30544 30545 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 30546 defined(BCM_56870_A0) 30547 { /* SOC_FORMAT_INT_IP_PARSER0_HME_STAGE_IN_BUSfmt */ 30548 /* format IP_PARSER0_HME_STAGE_IN_BUSfmt */ 30549 /* nFields */ 13, 30550 /* *fields */ soc_IP_PARSER0_HME_STAGE_IN_BUSfmt_fields, 30551 /* bits */ 1358, 30552 /* flags */ 0, 30553 }, 30554 #endif /* chips */ 30555 30556 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 30557 defined(BCM_56870_A0) 30558 { /* SOC_FORMAT_INT_IP_PARSER0_HME_STAGE_KEY_VALID_BYTES_CHECK_DATAfmt */ 30559 /* format IP_PARSER0_HME_STAGE_KEY_VALID_BYTES_CHECK_DATAfmt */ 30560 /* nFields */ 17, 30561 /* *fields */ soc_IP_PARSER0_HME_STAGE_KEY_VALID_BYTES_CHECK_DATAfmt_fields, 30562 /* bits */ 1, 30563 /* flags */ 0, 30564 }, 30565 #endif /* chips */ 30566 30567 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 30568 defined(BCM_56870_A0) 30569 { /* SOC_FORMAT_INT_IP_PARSER0_HME_STAGE_OUT_BUSfmt */ 30570 /* format IP_PARSER0_HME_STAGE_OUT_BUSfmt */ 30571 /* nFields */ 20, 30572 /* *fields */ soc_IP_PARSER0_HME_STAGE_OUT_BUSfmt_fields, 30573 /* bits */ 1416, 30574 /* flags */ 0, 30575 }, 30576 #endif /* chips */ 30577 30578 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 30579 defined(BCM_56870_A0) 30580 { /* SOC_FORMAT_INT_IP_PARSER0_HME_STAGE_OUT_ONLY_BUSfmt */ 30581 /* format IP_PARSER0_HME_STAGE_OUT_ONLY_BUSfmt */ 30582 /* nFields */ 9, 30583 /* *fields */ soc_IP_PARSER0_HME_STAGE_OUT_ONLY_BUSfmt_fields, 30584 /* bits */ 67, 30585 /* flags */ 0, 30586 }, 30587 #endif /* chips */ 30588 30589 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 30590 defined(BCM_56870_A0) 30591 { /* SOC_FORMAT_INT_IP_PARSER0_HME_STAGE_PIPE_BUSfmt */ 30592 /* format IP_PARSER0_HME_STAGE_PIPE_BUSfmt */ 30593 /* nFields */ 8, 30594 /* *fields */ soc_IP_PARSER0_HME_STAGE_PIPE_BUSfmt_fields, 30595 /* bits */ 1348, 30596 /* flags */ 0, 30597 }, 30598 #endif /* chips */ 30599 30600 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 30601 defined(BCM_56870_A0) 30602 { /* SOC_FORMAT_INT_IP_PARSER0_HME_STAGE_TCAM_DATAfmt */ 30603 /* format IP_PARSER0_HME_STAGE_TCAM_DATAfmt */ 30604 /* nFields */ 29, 30605 /* *fields */ soc_IP_PARSER0_HME_STAGE_TCAM_DATAfmt_fields, 30606 /* bits */ 180, 30607 /* flags */ 0, 30608 }, 30609 #endif /* chips */ 30610 30611 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 30612 defined(BCM_56870_A0) 30613 { /* SOC_FORMAT_INT_IP_PARSER0_HME_STAGE_TCAM_KEYfmt */ 30614 /* format IP_PARSER0_HME_STAGE_TCAM_KEYfmt */ 30615 /* nFields */ 6, 30616 /* *fields */ soc_IP_PARSER0_HME_STAGE_TCAM_KEYfmt_fields, 30617 /* bits */ 192, 30618 /* flags */ 0, 30619 }, 30620 #endif /* chips */ 30621 30622 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 30623 defined(BCM_56870_A0) 30624 { /* SOC_FORMAT_INT_IP_PARSER0_HME_STAGE_TCAM_KEY_NARROWfmt */ 30625 /* format IP_PARSER0_HME_STAGE_TCAM_KEY_NARROWfmt */ 30626 /* nFields */ 6, 30627 /* *fields */ soc_IP_PARSER0_HME_STAGE_TCAM_KEY_NARROWfmt_fields, 30628 /* bits */ 96, 30629 /* flags */ 0, 30630 }, 30631 #endif /* chips */ 30632 30633 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 30634 defined(BCM_56870_A0) 30635 { /* SOC_FORMAT_INT_IP_PARSER0_HVE_CONTROLSfmt */ 30636 /* format IP_PARSER0_HVE_CONTROLSfmt */ 30637 /* nFields */ 4, 30638 /* *fields */ soc_IP_PARSER0_HVE_CONTROLSfmt_fields, 30639 /* bits */ 43, 30640 /* flags */ 0, 30641 }, 30642 #endif /* chips */ 30643 30644 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 30645 defined(BCM_56870_A0) 30646 { /* SOC_FORMAT_INT_IP_PARSER0_HVE_IN_BUSfmt */ 30647 /* format IP_PARSER0_HVE_IN_BUSfmt */ 30648 /* nFields */ 7, 30649 /* *fields */ soc_IP_PARSER0_HVE_IN_BUSfmt_fields, 30650 /* bits */ 743, 30651 /* flags */ 0, 30652 }, 30653 #endif /* chips */ 30654 30655 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 30656 defined(BCM_56870_A0) 30657 { /* SOC_FORMAT_INT_IP_PARSER0_HVE_OUT_BUSfmt */ 30658 /* format IP_PARSER0_HVE_OUT_BUSfmt */ 30659 /* nFields */ 1, 30660 /* *fields */ soc_IP_PARSER0_HVE_OUT_BUSfmt_fields, 30661 /* bits */ 11, 30662 /* flags */ 0, 30663 }, 30664 #endif /* chips */ 30665 30666 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 30667 defined(BCM_56870_A0) 30668 { /* SOC_FORMAT_INT_IP_PARSER0_HVE_RC_PROFILEfmt */ 30669 /* format IP_PARSER0_HVE_RC_PROFILEfmt */ 30670 /* nFields */ 2, 30671 /* *fields */ soc_IP_PARSER0_HVE_RC_PROFILEfmt_fields, 30672 /* bits */ 3, 30673 /* flags */ 0, 30674 }, 30675 #endif /* chips */ 30676 30677 #if defined(BCM_56870_A0) 30678 { /* SOC_FORMAT_INT_IP_PARSER0_HVE_SCC_PROFILEfmt */ 30679 /* format IP_PARSER0_HVE_SCC_PROFILEfmt */ 30680 /* nFields */ 2, 30681 /* *fields */ soc_IP_PARSER0_HVE_RC_PROFILEfmt_fields, 30682 /* bits */ 3, 30683 /* flags */ 0, 30684 }, 30685 #endif /* chips */ 30686 30687 #if defined(BCM_56370_A0) 30688 { /* SOC_FORMAT_INT_IP_PARSER0_HVE_SCC_PROFILE_BCM56370_A0fmt */ 30689 /* format IP_PARSER0_HVE_SCC_PROFILEfmt */ 30690 /* nFields */ 2, 30691 /* *fields */ soc_IP_PARSER0_HVE_RC_PROFILEfmt_fields, 30692 /* bits */ 3, 30693 /* flags */ 0, 30694 }, 30695 #endif /* chips */ 30696 30697 #if defined(BCM_56770_A0) 30698 { /* SOC_FORMAT_INT_IP_PARSER0_HVE_SCC_PROFILE_BCM56770_A0fmt */ 30699 /* format IP_PARSER0_HVE_SCC_PROFILEfmt */ 30700 /* nFields */ 2, 30701 /* *fields */ soc_IP_PARSER0_HVE_RC_PROFILEfmt_fields, 30702 /* bits */ 3, 30703 /* flags */ 0, 30704 }, 30705 #endif /* chips */ 30706 30707 #if defined(BCM_56870_A0) 30708 { /* SOC_FORMAT_INT_IP_PARSER0_HVE_SCF_PROFILEfmt */ 30709 /* format IP_PARSER0_HVE_SCF_PROFILEfmt */ 30710 /* nFields */ 2, 30711 /* *fields */ soc_IP_PARSER0_HVE_RC_PROFILEfmt_fields, 30712 /* bits */ 3, 30713 /* flags */ 0, 30714 }, 30715 #endif /* chips */ 30716 30717 #if defined(BCM_56370_A0) 30718 { /* SOC_FORMAT_INT_IP_PARSER0_HVE_SCF_PROFILE_BCM56370_A0fmt */ 30719 /* format IP_PARSER0_HVE_SCF_PROFILEfmt */ 30720 /* nFields */ 2, 30721 /* *fields */ soc_IP_PARSER0_HVE_RC_PROFILEfmt_fields, 30722 /* bits */ 3, 30723 /* flags */ 0, 30724 }, 30725 #endif /* chips */ 30726 30727 #if defined(BCM_56770_A0) 30728 { /* SOC_FORMAT_INT_IP_PARSER0_HVE_SCF_PROFILE_BCM56770_A0fmt */ 30729 /* format IP_PARSER0_HVE_SCF_PROFILEfmt */ 30730 /* nFields */ 2, 30731 /* *fields */ soc_IP_PARSER0_HVE_RC_PROFILEfmt_fields, 30732 /* bits */ 3, 30733 /* flags */ 0, 30734 }, 30735 #endif /* chips */ 30736 30737 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 30738 defined(BCM_56870_A0) 30739 { /* SOC_FORMAT_INT_IP_PARSER0_IN_BUSfmt */ 30740 /* format IP_PARSER0_IN_BUSfmt */ 30741 /* nFields */ 14, 30742 /* *fields */ soc_IP_PARSER0_IN_BUSfmt_fields, 30743 /* bits */ 1364, 30744 /* flags */ 0, 30745 }, 30746 #endif /* chips */ 30747 30748 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 30749 defined(BCM_56870_A0) 30750 { /* SOC_FORMAT_INT_IP_PARSER0_MICE_IN_BUSfmt */ 30751 /* format IP_PARSER0_MICE_IN_BUSfmt */ 30752 /* nFields */ 5, 30753 /* *fields */ soc_IP_PARSER0_MICE_IN_BUSfmt_fields, 30754 /* bits */ 36, 30755 /* flags */ 0, 30756 }, 30757 #endif /* chips */ 30758 30759 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 30760 defined(BCM_56870_A0) 30761 { /* SOC_FORMAT_INT_IP_PARSER0_MICE_OUT_BUSfmt */ 30762 /* format IP_PARSER0_MICE_OUT_BUSfmt */ 30763 /* nFields */ 6, 30764 /* *fields */ soc_IP_PARSER0_MICE_OUT_BUSfmt_fields, 30765 /* bits */ 59, 30766 /* flags */ 0, 30767 }, 30768 #endif /* chips */ 30769 30770 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 30771 defined(BCM_56870_A0) 30772 { /* SOC_FORMAT_INT_IP_PARSER0_OUT_BUSfmt */ 30773 /* format IP_PARSER0_OUT_BUSfmt */ 30774 /* nFields */ 15, 30775 /* *fields */ soc_IP_PARSER0_OUT_BUSfmt_fields, 30776 /* bits */ 2089, 30777 /* flags */ 0, 30778 }, 30779 #endif /* chips */ 30780 30781 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 30782 defined(BCM_56870_A0) 30783 { /* SOC_FORMAT_INT_IP_PARSER0_TOP_HME_OUT_BUSfmt */ 30784 /* format IP_PARSER0_TOP_HME_OUT_BUSfmt */ 30785 /* nFields */ 5, 30786 /* *fields */ soc_IP_PARSER0_TOP_HME_OUT_BUSfmt_fields, 30787 /* bits */ 51, 30788 /* flags */ 0, 30789 }, 30790 #endif /* chips */ 30791 30792 #if defined(BCM_56870_A0) 30793 { /* SOC_FORMAT_INT_IP_PARSER1_FLEX_HVE_CONTROLSfmt */ 30794 /* format IP_PARSER1_FLEX_HVE_CONTROLSfmt */ 30795 /* nFields */ 33, 30796 /* *fields */ soc_IP_PARSER0_FLEX_HVE_CONTROLSfmt_fields, 30797 /* bits */ 33, 30798 /* flags */ 0, 30799 }, 30800 #endif /* chips */ 30801 30802 #if defined(BCM_56370_A0) 30803 { /* SOC_FORMAT_INT_IP_PARSER1_FLEX_HVE_CONTROLS_BCM56370_A0fmt */ 30804 /* format IP_PARSER1_FLEX_HVE_CONTROLSfmt */ 30805 /* nFields */ 33, 30806 /* *fields */ soc_IP_PARSER0_FLEX_HVE_CONTROLSfmt_fields, 30807 /* bits */ 33, 30808 /* flags */ 0, 30809 }, 30810 #endif /* chips */ 30811 30812 #if defined(BCM_56770_A0) 30813 { /* SOC_FORMAT_INT_IP_PARSER1_FLEX_HVE_CONTROLS_BCM56770_A0fmt */ 30814 /* format IP_PARSER1_FLEX_HVE_CONTROLSfmt */ 30815 /* nFields */ 33, 30816 /* *fields */ soc_IP_PARSER0_FLEX_HVE_CONTROLSfmt_fields, 30817 /* bits */ 33, 30818 /* flags */ 0, 30819 }, 30820 #endif /* chips */ 30821 30822 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 30823 defined(BCM_56870_A0) 30824 { /* SOC_FORMAT_INT_IP_PARSER1_FLEX_HVE_IN_BUSfmt */ 30825 /* format IP_PARSER1_FLEX_HVE_IN_BUSfmt */ 30826 /* nFields */ 36, 30827 /* *fields */ soc_IP_PARSER1_FLEX_HVE_IN_BUSfmt_fields, 30828 /* bits */ 1420, 30829 /* flags */ 0, 30830 }, 30831 #endif /* chips */ 30832 30833 #if defined(BCM_56870_A0) 30834 { /* SOC_FORMAT_INT_IP_PARSER1_FLEX_HVE_OUT_BUSfmt */ 30835 /* format IP_PARSER1_FLEX_HVE_OUT_BUSfmt */ 30836 /* nFields */ 44, 30837 /* *fields */ soc_IP_PARSER0_FLEX_HVE_OUT_BUSfmt_fields, 30838 /* bits */ 110, 30839 /* flags */ 0, 30840 }, 30841 #endif /* chips */ 30842 30843 #if defined(BCM_56370_A0) 30844 { /* SOC_FORMAT_INT_IP_PARSER1_FLEX_HVE_OUT_BUS_BCM56370_A0fmt */ 30845 /* format IP_PARSER1_FLEX_HVE_OUT_BUSfmt */ 30846 /* nFields */ 44, 30847 /* *fields */ soc_IP_PARSER0_FLEX_HVE_OUT_BUSfmt_fields, 30848 /* bits */ 110, 30849 /* flags */ 0, 30850 }, 30851 #endif /* chips */ 30852 30853 #if defined(BCM_56770_A0) 30854 { /* SOC_FORMAT_INT_IP_PARSER1_FLEX_HVE_OUT_BUS_BCM56770_A0fmt */ 30855 /* format IP_PARSER1_FLEX_HVE_OUT_BUSfmt */ 30856 /* nFields */ 44, 30857 /* *fields */ soc_IP_PARSER0_FLEX_HVE_OUT_BUSfmt_fields, 30858 /* bits */ 110, 30859 /* flags */ 0, 30860 }, 30861 #endif /* chips */ 30862 30863 #if defined(BCM_56870_A0) 30864 { /* SOC_FORMAT_INT_IP_PARSER1_FLEX_HVE_OUT_CHECKfmt */ 30865 /* format IP_PARSER1_FLEX_HVE_OUT_CHECKfmt */ 30866 /* nFields */ 3, 30867 /* *fields */ soc_IP_PARSER0_FLEX_HVE_OUT_CHECKfmt_fields, 30868 /* bits */ 10, 30869 /* flags */ 0, 30870 }, 30871 #endif /* chips */ 30872 30873 #if defined(BCM_56370_A0) 30874 { /* SOC_FORMAT_INT_IP_PARSER1_FLEX_HVE_OUT_CHECK_BCM56370_A0fmt */ 30875 /* format IP_PARSER1_FLEX_HVE_OUT_CHECKfmt */ 30876 /* nFields */ 3, 30877 /* *fields */ soc_IP_PARSER0_FLEX_HVE_OUT_CHECKfmt_fields, 30878 /* bits */ 10, 30879 /* flags */ 0, 30880 }, 30881 #endif /* chips */ 30882 30883 #if defined(BCM_56770_A0) 30884 { /* SOC_FORMAT_INT_IP_PARSER1_FLEX_HVE_OUT_CHECK_BCM56770_A0fmt */ 30885 /* format IP_PARSER1_FLEX_HVE_OUT_CHECKfmt */ 30886 /* nFields */ 3, 30887 /* *fields */ soc_IP_PARSER0_FLEX_HVE_OUT_CHECKfmt_fields, 30888 /* bits */ 10, 30889 /* flags */ 0, 30890 }, 30891 #endif /* chips */ 30892 30893 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 30894 defined(BCM_56870_A0) 30895 { /* SOC_FORMAT_INT_IP_PARSER1_HFE_CMD_POLICY_DATAfmt */ 30896 /* format IP_PARSER1_HFE_CMD_POLICY_DATAfmt */ 30897 /* nFields */ 48, 30898 /* *fields */ soc_IP_PARSER1_HFE_CMD_POLICY_DATAfmt_fields, 30899 /* bits */ 180, 30900 /* flags */ 0, 30901 }, 30902 #endif /* chips */ 30903 30904 #if defined(BCM_56870_A0) 30905 { /* SOC_FORMAT_INT_IP_PARSER1_HFE_CONSTANTSfmt */ 30906 /* format IP_PARSER1_HFE_CONSTANTSfmt */ 30907 /* nFields */ 1, 30908 /* *fields */ soc_EP_PARSER0_HFE_CONSTANTSfmt_fields, 30909 /* bits */ 1, 30910 /* flags */ 0, 30911 }, 30912 #endif /* chips */ 30913 30914 #if defined(BCM_56370_A0) 30915 { /* SOC_FORMAT_INT_IP_PARSER1_HFE_CONSTANTS_BCM56370_A0fmt */ 30916 /* format IP_PARSER1_HFE_CONSTANTSfmt */ 30917 /* nFields */ 1, 30918 /* *fields */ soc_EP_PARSER0_HFE_CONSTANTSfmt_fields, 30919 /* bits */ 1, 30920 /* flags */ 0, 30921 }, 30922 #endif /* chips */ 30923 30924 #if defined(BCM_56770_A0) 30925 { /* SOC_FORMAT_INT_IP_PARSER1_HFE_CONSTANTS_BCM56770_A0fmt */ 30926 /* format IP_PARSER1_HFE_CONSTANTSfmt */ 30927 /* nFields */ 1, 30928 /* *fields */ soc_EP_PARSER0_HFE_CONSTANTSfmt_fields, 30929 /* bits */ 1, 30930 /* flags */ 0, 30931 }, 30932 #endif /* chips */ 30933 30934 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 30935 defined(BCM_56870_A0) 30936 { /* SOC_FORMAT_INT_IP_PARSER1_HFE_CONTROLSfmt */ 30937 /* format IP_PARSER1_HFE_CONTROLSfmt */ 30938 /* nFields */ 8, 30939 /* *fields */ soc_IP_PARSER1_HFE_CONTROLSfmt_fields, 30940 /* bits */ 98, 30941 /* flags */ 0, 30942 }, 30943 #endif /* chips */ 30944 30945 #if defined(BCM_56870_A0) 30946 { /* SOC_FORMAT_INT_IP_PARSER1_HFE_CONT_PROFILEfmt */ 30947 /* format IP_PARSER1_HFE_CONT_PROFILEfmt */ 30948 /* nFields */ 2, 30949 /* *fields */ soc_EP_PARSER1_HFE_CONT_PROFILEfmt_fields, 30950 /* bits */ 10, 30951 /* flags */ 0, 30952 }, 30953 #endif /* chips */ 30954 30955 #if defined(BCM_56370_A0) 30956 { /* SOC_FORMAT_INT_IP_PARSER1_HFE_CONT_PROFILE_BCM56370_A0fmt */ 30957 /* format IP_PARSER1_HFE_CONT_PROFILEfmt */ 30958 /* nFields */ 2, 30959 /* *fields */ soc_EP_PARSER1_HFE_CONT_PROFILEfmt_fields, 30960 /* bits */ 10, 30961 /* flags */ 0, 30962 }, 30963 #endif /* chips */ 30964 30965 #if defined(BCM_56770_A0) 30966 { /* SOC_FORMAT_INT_IP_PARSER1_HFE_CONT_PROFILE_BCM56770_A0fmt */ 30967 /* format IP_PARSER1_HFE_CONT_PROFILEfmt */ 30968 /* nFields */ 2, 30969 /* *fields */ soc_EP_PARSER1_HFE_CONT_PROFILEfmt_fields, 30970 /* bits */ 10, 30971 /* flags */ 0, 30972 }, 30973 #endif /* chips */ 30974 30975 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 30976 defined(BCM_56870_A0) 30977 { /* SOC_FORMAT_INT_IP_PARSER1_HFE_IN_BUSfmt */ 30978 /* format IP_PARSER1_HFE_IN_BUSfmt */ 30979 /* nFields */ 10, 30980 /* *fields */ soc_IP_PARSER1_HFE_IN_BUSfmt_fields, 30981 /* bits */ 1250, 30982 /* flags */ 0, 30983 }, 30984 #endif /* chips */ 30985 30986 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 30987 defined(BCM_56870_A0) 30988 { /* SOC_FORMAT_INT_IP_PARSER1_HFE_MUX_CONTROLSfmt */ 30989 /* format IP_PARSER1_HFE_MUX_CONTROLSfmt */ 30990 /* nFields */ 5, 30991 /* *fields */ soc_IP_PARSER1_HFE_MUX_CONTROLSfmt_fields, 30992 /* bits */ 58, 30993 /* flags */ 0, 30994 }, 30995 #endif /* chips */ 30996 30997 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 30998 defined(BCM_56870_A0) 30999 { /* SOC_FORMAT_INT_IP_PARSER1_HFE_MUX_IN_BUSfmt */ 31000 /* format IP_PARSER1_HFE_MUX_IN_BUSfmt */ 31001 /* nFields */ 22, 31002 /* *fields */ soc_IP_PARSER1_HFE_MUX_IN_BUSfmt_fields, 31003 /* bits */ 2210, 31004 /* flags */ 0, 31005 }, 31006 #endif /* chips */ 31007 31008 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 31009 defined(BCM_56870_A0) 31010 { /* SOC_FORMAT_INT_IP_PARSER1_HFE_MUX_OUT_BUSfmt */ 31011 /* format IP_PARSER1_HFE_MUX_OUT_BUSfmt */ 31012 /* nFields */ 97, 31013 /* *fields */ soc_IP_PARSER1_HFE_MUX_OUT_BUSfmt_fields, 31014 /* bits */ 1386, 31015 /* flags */ 0, 31016 }, 31017 #endif /* chips */ 31018 31019 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 31020 defined(BCM_56870_A0) 31021 { /* SOC_FORMAT_INT_IP_PARSER1_HFE_OUT_BUSfmt */ 31022 /* format IP_PARSER1_HFE_OUT_BUSfmt */ 31023 /* nFields */ 98, 31024 /* *fields */ soc_IP_PARSER1_HFE_OUT_BUSfmt_fields, 31025 /* bits */ 1386, 31026 /* flags */ 0, 31027 }, 31028 #endif /* chips */ 31029 31030 #if defined(BCM_56870_A0) 31031 { /* SOC_FORMAT_INT_IP_PARSER1_HFE_POLICY_COMMAND_Afmt */ 31032 /* format IP_PARSER1_HFE_POLICY_COMMAND_Afmt */ 31033 /* nFields */ 3, 31034 /* *fields */ soc_EP_PARSER1_HFE_POLICY_COMMAND_Afmt_fields, 31035 /* bits */ 2, 31036 /* flags */ 0, 31037 }, 31038 #endif /* chips */ 31039 31040 #if defined(BCM_56370_A0) 31041 { /* SOC_FORMAT_INT_IP_PARSER1_HFE_POLICY_COMMAND_A_BCM56370_A0fmt */ 31042 /* format IP_PARSER1_HFE_POLICY_COMMAND_Afmt */ 31043 /* nFields */ 3, 31044 /* *fields */ soc_EP_PARSER1_HFE_POLICY_COMMAND_Afmt_fields, 31045 /* bits */ 2, 31046 /* flags */ 0, 31047 }, 31048 #endif /* chips */ 31049 31050 #if defined(BCM_56770_A0) 31051 { /* SOC_FORMAT_INT_IP_PARSER1_HFE_POLICY_COMMAND_A_BCM56770_A0fmt */ 31052 /* format IP_PARSER1_HFE_POLICY_COMMAND_Afmt */ 31053 /* nFields */ 3, 31054 /* *fields */ soc_EP_PARSER1_HFE_POLICY_COMMAND_Afmt_fields, 31055 /* bits */ 2, 31056 /* flags */ 0, 31057 }, 31058 #endif /* chips */ 31059 31060 #if defined(BCM_56870_A0) 31061 { /* SOC_FORMAT_INT_IP_PARSER1_HFE_POLICY_COMMAND_Bfmt */ 31062 /* format IP_PARSER1_HFE_POLICY_COMMAND_Bfmt */ 31063 /* nFields */ 6, 31064 /* *fields */ soc_EP_PARSER1_HFE_POLICY_COMMAND_Bfmt_fields, 31065 /* bits */ 2, 31066 /* flags */ 0, 31067 }, 31068 #endif /* chips */ 31069 31070 #if defined(BCM_56370_A0) 31071 { /* SOC_FORMAT_INT_IP_PARSER1_HFE_POLICY_COMMAND_B_BCM56370_A0fmt */ 31072 /* format IP_PARSER1_HFE_POLICY_COMMAND_Bfmt */ 31073 /* nFields */ 6, 31074 /* *fields */ soc_EP_PARSER1_HFE_POLICY_COMMAND_Bfmt_fields, 31075 /* bits */ 2, 31076 /* flags */ 0, 31077 }, 31078 #endif /* chips */ 31079 31080 #if defined(BCM_56770_A0) 31081 { /* SOC_FORMAT_INT_IP_PARSER1_HFE_POLICY_COMMAND_B_BCM56770_A0fmt */ 31082 /* format IP_PARSER1_HFE_POLICY_COMMAND_Bfmt */ 31083 /* nFields */ 6, 31084 /* *fields */ soc_EP_PARSER1_HFE_POLICY_COMMAND_Bfmt_fields, 31085 /* bits */ 2, 31086 /* flags */ 0, 31087 }, 31088 #endif /* chips */ 31089 31090 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 31091 defined(BCM_56870_A0) 31092 { /* SOC_FORMAT_INT_IP_PARSER1_HFE_POLICY_COMMAND_Cfmt */ 31093 /* format IP_PARSER1_HFE_POLICY_COMMAND_Cfmt */ 31094 /* nFields */ 3, 31095 /* *fields */ soc_IP_PARSER1_HFE_POLICY_COMMAND_Cfmt_fields, 31096 /* bits */ 15, 31097 /* flags */ 0, 31098 }, 31099 #endif /* chips */ 31100 31101 #if defined(BCM_56870_A0) 31102 { /* SOC_FORMAT_INT_IP_PARSER1_HFE_POLICY_COMMAND_Dfmt */ 31103 /* format IP_PARSER1_HFE_POLICY_COMMAND_Dfmt */ 31104 /* nFields */ 5, 31105 /* *fields */ soc_EP_PARSER0_HFE_POLICY_COMMAND_Dfmt_fields, 31106 /* bits */ 4, 31107 /* flags */ 0, 31108 }, 31109 #endif /* chips */ 31110 31111 #if defined(BCM_56370_A0) 31112 { /* SOC_FORMAT_INT_IP_PARSER1_HFE_POLICY_COMMAND_D_BCM56370_A0fmt */ 31113 /* format IP_PARSER1_HFE_POLICY_COMMAND_Dfmt */ 31114 /* nFields */ 5, 31115 /* *fields */ soc_EP_PARSER0_HFE_POLICY_COMMAND_Dfmt_fields, 31116 /* bits */ 4, 31117 /* flags */ 0, 31118 }, 31119 #endif /* chips */ 31120 31121 #if defined(BCM_56770_A0) 31122 { /* SOC_FORMAT_INT_IP_PARSER1_HFE_POLICY_COMMAND_D_BCM56770_A0fmt */ 31123 /* format IP_PARSER1_HFE_POLICY_COMMAND_Dfmt */ 31124 /* nFields */ 5, 31125 /* *fields */ soc_EP_PARSER0_HFE_POLICY_COMMAND_Dfmt_fields, 31126 /* bits */ 4, 31127 /* flags */ 0, 31128 }, 31129 #endif /* chips */ 31130 31131 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 31132 defined(BCM_56870_A0) 31133 { /* SOC_FORMAT_INT_IP_PARSER1_HFE_POLICY_TABLE_DATAfmt */ 31134 /* format IP_PARSER1_HFE_POLICY_TABLE_DATAfmt */ 31135 /* nFields */ 11, 31136 /* *fields */ soc_IP_PARSER1_HFE_POLICY_TABLE_DATAfmt_fields, 31137 /* bits */ 200, 31138 /* flags */ 0, 31139 }, 31140 #endif /* chips */ 31141 31142 #if defined(BCM_56870_A0) 31143 { /* SOC_FORMAT_INT_IP_PARSER1_HME_CONSTANTSfmt */ 31144 /* format IP_PARSER1_HME_CONSTANTSfmt */ 31145 /* nFields */ 1, 31146 /* *fields */ soc_EP_PARSER0_HFE_CONSTANTSfmt_fields, 31147 /* bits */ 1, 31148 /* flags */ 0, 31149 }, 31150 #endif /* chips */ 31151 31152 #if defined(BCM_56370_A0) 31153 { /* SOC_FORMAT_INT_IP_PARSER1_HME_CONSTANTS_BCM56370_A0fmt */ 31154 /* format IP_PARSER1_HME_CONSTANTSfmt */ 31155 /* nFields */ 1, 31156 /* *fields */ soc_EP_PARSER0_HFE_CONSTANTSfmt_fields, 31157 /* bits */ 1, 31158 /* flags */ 0, 31159 }, 31160 #endif /* chips */ 31161 31162 #if defined(BCM_56770_A0) 31163 { /* SOC_FORMAT_INT_IP_PARSER1_HME_CONSTANTS_BCM56770_A0fmt */ 31164 /* format IP_PARSER1_HME_CONSTANTSfmt */ 31165 /* nFields */ 1, 31166 /* *fields */ soc_EP_PARSER0_HFE_CONSTANTSfmt_fields, 31167 /* bits */ 1, 31168 /* flags */ 0, 31169 }, 31170 #endif /* chips */ 31171 31172 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 31173 defined(BCM_56870_A0) 31174 { /* SOC_FORMAT_INT_IP_PARSER1_HME_IN_BUSfmt */ 31175 /* format IP_PARSER1_HME_IN_BUSfmt */ 31176 /* nFields */ 11, 31177 /* *fields */ soc_IP_PARSER1_HME_IN_BUSfmt_fields, 31178 /* bits */ 1251, 31179 /* flags */ 0, 31180 }, 31181 #endif /* chips */ 31182 31183 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 31184 defined(BCM_56870_A0) 31185 { /* SOC_FORMAT_INT_IP_PARSER1_HME_LATENCY_CONTROLSfmt */ 31186 /* format IP_PARSER1_HME_LATENCY_CONTROLSfmt */ 31187 /* nFields */ 2, 31188 /* *fields */ soc_IP_PARSER1_HME_LATENCY_CONTROLSfmt_fields, 31189 /* bits */ 6, 31190 /* flags */ 0, 31191 }, 31192 #endif /* chips */ 31193 31194 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 31195 defined(BCM_56870_A0) 31196 { /* SOC_FORMAT_INT_IP_PARSER1_HME_OUT_BUSfmt */ 31197 /* format IP_PARSER1_HME_OUT_BUSfmt */ 31198 /* nFields */ 17, 31199 /* *fields */ soc_IP_PARSER1_HME_OUT_BUSfmt_fields, 31200 /* bits */ 1361, 31201 /* flags */ 0, 31202 }, 31203 #endif /* chips */ 31204 31205 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 31206 defined(BCM_56870_A0) 31207 { /* SOC_FORMAT_INT_IP_PARSER1_HME_PASSTHROUGH_BUSfmt */ 31208 /* format IP_PARSER1_HME_PASSTHROUGH_BUSfmt */ 31209 /* nFields */ 3, 31210 /* *fields */ soc_IP_PARSER1_HME_PASSTHROUGH_BUSfmt_fields, 31211 /* bits */ 10, 31212 /* flags */ 0, 31213 }, 31214 #endif /* chips */ 31215 31216 #if defined(BCM_56870_A0) 31217 { /* SOC_FORMAT_INT_IP_PARSER1_HME_POLICY_ACTIONfmt */ 31218 /* format IP_PARSER1_HME_POLICY_ACTIONfmt */ 31219 /* nFields */ 3, 31220 /* *fields */ soc_IP_PARSER0_HME_POLICY_ACTIONfmt_fields, 31221 /* bits */ 3, 31222 /* flags */ 0, 31223 }, 31224 #endif /* chips */ 31225 31226 #if defined(BCM_56370_A0) 31227 { /* SOC_FORMAT_INT_IP_PARSER1_HME_POLICY_ACTION_BCM56370_A0fmt */ 31228 /* format IP_PARSER1_HME_POLICY_ACTIONfmt */ 31229 /* nFields */ 3, 31230 /* *fields */ soc_IP_PARSER0_HME_POLICY_ACTIONfmt_fields, 31231 /* bits */ 3, 31232 /* flags */ 0, 31233 }, 31234 #endif /* chips */ 31235 31236 #if defined(BCM_56770_A0) 31237 { /* SOC_FORMAT_INT_IP_PARSER1_HME_POLICY_ACTION_BCM56770_A0fmt */ 31238 /* format IP_PARSER1_HME_POLICY_ACTIONfmt */ 31239 /* nFields */ 3, 31240 /* *fields */ soc_IP_PARSER0_HME_POLICY_ACTIONfmt_fields, 31241 /* bits */ 3, 31242 /* flags */ 0, 31243 }, 31244 #endif /* chips */ 31245 31246 #if defined(BCM_56870_A0) 31247 { /* SOC_FORMAT_INT_IP_PARSER1_HME_STAGE_COMMON_BUSfmt */ 31248 /* format IP_PARSER1_HME_STAGE_COMMON_BUSfmt */ 31249 /* nFields */ 3, 31250 /* *fields */ soc_IP_PARSER0_HME_STAGE_COMMON_BUSfmt_fields, 31251 /* bits */ 10, 31252 /* flags */ 0, 31253 }, 31254 #endif /* chips */ 31255 31256 #if defined(BCM_56370_A0) 31257 { /* SOC_FORMAT_INT_IP_PARSER1_HME_STAGE_COMMON_BUS_BCM56370_A0fmt */ 31258 /* format IP_PARSER1_HME_STAGE_COMMON_BUSfmt */ 31259 /* nFields */ 3, 31260 /* *fields */ soc_IP_PARSER0_HME_STAGE_COMMON_BUSfmt_fields, 31261 /* bits */ 10, 31262 /* flags */ 0, 31263 }, 31264 #endif /* chips */ 31265 31266 #if defined(BCM_56770_A0) 31267 { /* SOC_FORMAT_INT_IP_PARSER1_HME_STAGE_COMMON_BUS_BCM56770_A0fmt */ 31268 /* format IP_PARSER1_HME_STAGE_COMMON_BUSfmt */ 31269 /* nFields */ 3, 31270 /* *fields */ soc_IP_PARSER0_HME_STAGE_COMMON_BUSfmt_fields, 31271 /* bits */ 10, 31272 /* flags */ 0, 31273 }, 31274 #endif /* chips */ 31275 31276 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 31277 defined(BCM_56870_A0) 31278 { /* SOC_FORMAT_INT_IP_PARSER1_HME_STAGE_IN_BUSfmt */ 31279 /* format IP_PARSER1_HME_STAGE_IN_BUSfmt */ 31280 /* nFields */ 13, 31281 /* *fields */ soc_IP_PARSER1_HME_STAGE_IN_BUSfmt_fields, 31282 /* bits */ 1246, 31283 /* flags */ 0, 31284 }, 31285 #endif /* chips */ 31286 31287 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 31288 defined(BCM_56870_A0) 31289 { /* SOC_FORMAT_INT_IP_PARSER1_HME_STAGE_KEY_VALID_BYTES_CHECK_DATAfmt */ 31290 /* format IP_PARSER1_HME_STAGE_KEY_VALID_BYTES_CHECK_DATAfmt */ 31291 /* nFields */ 16, 31292 /* *fields */ soc_IP_PARSER1_HME_STAGE_KEY_VALID_BYTES_CHECK_DATAfmt_fields, 31293 /* bits */ 128, 31294 /* flags */ 0, 31295 }, 31296 #endif /* chips */ 31297 31298 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 31299 defined(BCM_56870_A0) 31300 { /* SOC_FORMAT_INT_IP_PARSER1_HME_STAGE_OUT_BUSfmt */ 31301 /* format IP_PARSER1_HME_STAGE_OUT_BUSfmt */ 31302 /* nFields */ 20, 31303 /* *fields */ soc_IP_PARSER1_HME_STAGE_OUT_BUSfmt_fields, 31304 /* bits */ 1262, 31305 /* flags */ 0, 31306 }, 31307 #endif /* chips */ 31308 31309 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 31310 defined(BCM_56870_A0) 31311 { /* SOC_FORMAT_INT_IP_PARSER1_HME_STAGE_OUT_ONLY_BUSfmt */ 31312 /* format IP_PARSER1_HME_STAGE_OUT_ONLY_BUSfmt */ 31313 /* nFields */ 10, 31314 /* *fields */ soc_IP_PARSER1_HME_STAGE_OUT_ONLY_BUSfmt_fields, 31315 /* bits */ 25, 31316 /* flags */ 0, 31317 }, 31318 #endif /* chips */ 31319 31320 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 31321 defined(BCM_56870_A0) 31322 { /* SOC_FORMAT_INT_IP_PARSER1_HME_STAGE_PIPE_BUSfmt */ 31323 /* format IP_PARSER1_HME_STAGE_PIPE_BUSfmt */ 31324 /* nFields */ 8, 31325 /* *fields */ soc_IP_PARSER1_HME_STAGE_PIPE_BUSfmt_fields, 31326 /* bits */ 1236, 31327 /* flags */ 0, 31328 }, 31329 #endif /* chips */ 31330 31331 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 31332 defined(BCM_56870_A0) 31333 { /* SOC_FORMAT_INT_IP_PARSER1_HME_STAGE_TCAM_DATAfmt */ 31334 /* format IP_PARSER1_HME_STAGE_TCAM_DATAfmt */ 31335 /* nFields */ 30, 31336 /* *fields */ soc_IP_PARSER1_HME_STAGE_TCAM_DATAfmt_fields, 31337 /* bits */ 140, 31338 /* flags */ 0, 31339 }, 31340 #endif /* chips */ 31341 31342 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 31343 defined(BCM_56870_A0) 31344 { /* SOC_FORMAT_INT_IP_PARSER1_HME_STAGE_TCAM_KEYfmt */ 31345 /* format IP_PARSER1_HME_STAGE_TCAM_KEYfmt */ 31346 /* nFields */ 5, 31347 /* *fields */ soc_IP_PARSER1_HME_STAGE_TCAM_KEYfmt_fields, 31348 /* bits */ 192, 31349 /* flags */ 0, 31350 }, 31351 #endif /* chips */ 31352 31353 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 31354 defined(BCM_56870_A0) 31355 { /* SOC_FORMAT_INT_IP_PARSER1_HME_STAGE_TCAM_KEY_NARROWfmt */ 31356 /* format IP_PARSER1_HME_STAGE_TCAM_KEY_NARROWfmt */ 31357 /* nFields */ 5, 31358 /* *fields */ soc_IP_PARSER1_HME_STAGE_TCAM_KEY_NARROWfmt_fields, 31359 /* bits */ 96, 31360 /* flags */ 0, 31361 }, 31362 #endif /* chips */ 31363 31364 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 31365 defined(BCM_56870_A0) 31366 { /* SOC_FORMAT_INT_IP_PARSER1_HVE_CONTROLSfmt */ 31367 /* format IP_PARSER1_HVE_CONTROLSfmt */ 31368 /* nFields */ 4, 31369 /* *fields */ soc_IP_PARSER1_HVE_CONTROLSfmt_fields, 31370 /* bits */ 65, 31371 /* flags */ 0, 31372 }, 31373 #endif /* chips */ 31374 31375 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 31376 defined(BCM_56870_A0) 31377 { /* SOC_FORMAT_INT_IP_PARSER1_HVE_IN_BUSfmt */ 31378 /* format IP_PARSER1_HVE_IN_BUSfmt */ 31379 /* nFields */ 7, 31380 /* *fields */ soc_IP_PARSER1_HVE_IN_BUSfmt_fields, 31381 /* bits */ 1452, 31382 /* flags */ 0, 31383 }, 31384 #endif /* chips */ 31385 31386 #if defined(BCM_56870_A0) 31387 { /* SOC_FORMAT_INT_IP_PARSER1_HVE_OUT_BUSfmt */ 31388 /* format IP_PARSER1_HVE_OUT_BUSfmt */ 31389 /* nFields */ 1, 31390 /* *fields */ soc_IP_PARSER0_HVE_OUT_BUSfmt_fields, 31391 /* bits */ 11, 31392 /* flags */ 0, 31393 }, 31394 #endif /* chips */ 31395 31396 #if defined(BCM_56370_A0) 31397 { /* SOC_FORMAT_INT_IP_PARSER1_HVE_OUT_BUS_BCM56370_A0fmt */ 31398 /* format IP_PARSER1_HVE_OUT_BUSfmt */ 31399 /* nFields */ 1, 31400 /* *fields */ soc_IP_PARSER0_HVE_OUT_BUSfmt_fields, 31401 /* bits */ 11, 31402 /* flags */ 0, 31403 }, 31404 #endif /* chips */ 31405 31406 #if defined(BCM_56770_A0) 31407 { /* SOC_FORMAT_INT_IP_PARSER1_HVE_OUT_BUS_BCM56770_A0fmt */ 31408 /* format IP_PARSER1_HVE_OUT_BUSfmt */ 31409 /* nFields */ 1, 31410 /* *fields */ soc_IP_PARSER0_HVE_OUT_BUSfmt_fields, 31411 /* bits */ 11, 31412 /* flags */ 0, 31413 }, 31414 #endif /* chips */ 31415 31416 #if defined(BCM_56870_A0) 31417 { /* SOC_FORMAT_INT_IP_PARSER1_HVE_RC_PROFILEfmt */ 31418 /* format IP_PARSER1_HVE_RC_PROFILEfmt */ 31419 /* nFields */ 2, 31420 /* *fields */ soc_IP_PARSER0_HVE_RC_PROFILEfmt_fields, 31421 /* bits */ 3, 31422 /* flags */ 0, 31423 }, 31424 #endif /* chips */ 31425 31426 #if defined(BCM_56370_A0) 31427 { /* SOC_FORMAT_INT_IP_PARSER1_HVE_RC_PROFILE_BCM56370_A0fmt */ 31428 /* format IP_PARSER1_HVE_RC_PROFILEfmt */ 31429 /* nFields */ 2, 31430 /* *fields */ soc_IP_PARSER0_HVE_RC_PROFILEfmt_fields, 31431 /* bits */ 3, 31432 /* flags */ 0, 31433 }, 31434 #endif /* chips */ 31435 31436 #if defined(BCM_56770_A0) 31437 { /* SOC_FORMAT_INT_IP_PARSER1_HVE_RC_PROFILE_BCM56770_A0fmt */ 31438 /* format IP_PARSER1_HVE_RC_PROFILEfmt */ 31439 /* nFields */ 2, 31440 /* *fields */ soc_IP_PARSER0_HVE_RC_PROFILEfmt_fields, 31441 /* bits */ 3, 31442 /* flags */ 0, 31443 }, 31444 #endif /* chips */ 31445 31446 #if defined(BCM_56870_A0) 31447 { /* SOC_FORMAT_INT_IP_PARSER1_HVE_SCC_PROFILEfmt */ 31448 /* format IP_PARSER1_HVE_SCC_PROFILEfmt */ 31449 /* nFields */ 2, 31450 /* *fields */ soc_IP_PARSER0_HVE_RC_PROFILEfmt_fields, 31451 /* bits */ 3, 31452 /* flags */ 0, 31453 }, 31454 #endif /* chips */ 31455 31456 #if defined(BCM_56370_A0) 31457 { /* SOC_FORMAT_INT_IP_PARSER1_HVE_SCC_PROFILE_BCM56370_A0fmt */ 31458 /* format IP_PARSER1_HVE_SCC_PROFILEfmt */ 31459 /* nFields */ 2, 31460 /* *fields */ soc_IP_PARSER0_HVE_RC_PROFILEfmt_fields, 31461 /* bits */ 3, 31462 /* flags */ 0, 31463 }, 31464 #endif /* chips */ 31465 31466 #if defined(BCM_56770_A0) 31467 { /* SOC_FORMAT_INT_IP_PARSER1_HVE_SCC_PROFILE_BCM56770_A0fmt */ 31468 /* format IP_PARSER1_HVE_SCC_PROFILEfmt */ 31469 /* nFields */ 2, 31470 /* *fields */ soc_IP_PARSER0_HVE_RC_PROFILEfmt_fields, 31471 /* bits */ 3, 31472 /* flags */ 0, 31473 }, 31474 #endif /* chips */ 31475 31476 #if defined(BCM_56870_A0) 31477 { /* SOC_FORMAT_INT_IP_PARSER1_HVE_SCF_PROFILEfmt */ 31478 /* format IP_PARSER1_HVE_SCF_PROFILEfmt */ 31479 /* nFields */ 2, 31480 /* *fields */ soc_IP_PARSER0_HVE_RC_PROFILEfmt_fields, 31481 /* bits */ 3, 31482 /* flags */ 0, 31483 }, 31484 #endif /* chips */ 31485 31486 #if defined(BCM_56370_A0) 31487 { /* SOC_FORMAT_INT_IP_PARSER1_HVE_SCF_PROFILE_BCM56370_A0fmt */ 31488 /* format IP_PARSER1_HVE_SCF_PROFILEfmt */ 31489 /* nFields */ 2, 31490 /* *fields */ soc_IP_PARSER0_HVE_RC_PROFILEfmt_fields, 31491 /* bits */ 3, 31492 /* flags */ 0, 31493 }, 31494 #endif /* chips */ 31495 31496 #if defined(BCM_56770_A0) 31497 { /* SOC_FORMAT_INT_IP_PARSER1_HVE_SCF_PROFILE_BCM56770_A0fmt */ 31498 /* format IP_PARSER1_HVE_SCF_PROFILEfmt */ 31499 /* nFields */ 2, 31500 /* *fields */ soc_IP_PARSER0_HVE_RC_PROFILEfmt_fields, 31501 /* bits */ 3, 31502 /* flags */ 0, 31503 }, 31504 #endif /* chips */ 31505 31506 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 31507 defined(BCM_56870_A0) 31508 { /* SOC_FORMAT_INT_IP_PARSER1_IN_BUSfmt */ 31509 /* format IP_PARSER1_IN_BUSfmt */ 31510 /* nFields */ 13, 31511 /* *fields */ soc_IP_PARSER1_IN_BUSfmt_fields, 31512 /* bits */ 1259, 31513 /* flags */ 0, 31514 }, 31515 #endif /* chips */ 31516 31517 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 31518 defined(BCM_56870_A0) 31519 { /* SOC_FORMAT_INT_IP_PARSER1_MICE_IN_BUSfmt */ 31520 /* format IP_PARSER1_MICE_IN_BUSfmt */ 31521 /* nFields */ 5, 31522 /* *fields */ soc_IP_PARSER1_MICE_IN_BUSfmt_fields, 31523 /* bits */ 92, 31524 /* flags */ 0, 31525 }, 31526 #endif /* chips */ 31527 31528 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 31529 defined(BCM_56870_A0) 31530 { /* SOC_FORMAT_INT_IP_PARSER1_MICE_OUT_BUSfmt */ 31531 /* format IP_PARSER1_MICE_OUT_BUSfmt */ 31532 /* nFields */ 6, 31533 /* *fields */ soc_IP_PARSER1_MICE_OUT_BUSfmt_fields, 31534 /* bits */ 97, 31535 /* flags */ 0, 31536 }, 31537 #endif /* chips */ 31538 31539 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 31540 defined(BCM_56870_A0) 31541 { /* SOC_FORMAT_INT_IP_PARSER1_MICE_TCAM_DATAfmt */ 31542 /* format IP_PARSER1_MICE_TCAM_DATAfmt */ 31543 /* nFields */ 9, 31544 /* *fields */ soc_IP_PARSER1_MICE_TCAM_DATAfmt_fields, 31545 /* bits */ 102, 31546 /* flags */ 0, 31547 }, 31548 #endif /* chips */ 31549 31550 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 31551 defined(BCM_56870_A0) 31552 { /* SOC_FORMAT_INT_IP_PARSER1_MICE_TCAM_KEYfmt */ 31553 /* format IP_PARSER1_MICE_TCAM_KEYfmt */ 31554 /* nFields */ 3, 31555 /* *fields */ soc_IP_PARSER1_MICE_TCAM_KEYfmt_fields, 31556 /* bits */ 64, 31557 /* flags */ 0, 31558 }, 31559 #endif /* chips */ 31560 31561 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 31562 defined(BCM_56870_A0) 31563 { /* SOC_FORMAT_INT_IP_PARSER1_OUT_BUSfmt */ 31564 /* format IP_PARSER1_OUT_BUSfmt */ 31565 /* nFields */ 15, 31566 /* *fields */ soc_IP_PARSER1_OUT_BUSfmt_fields, 31567 /* bits */ 2686, 31568 /* flags */ 0, 31569 }, 31570 #endif /* chips */ 31571 31572 #if defined(BCM_56870_A0) 31573 { /* SOC_FORMAT_INT_IP_PARSER1_TOP_HME_OUT_BUSfmt */ 31574 /* format IP_PARSER1_TOP_HME_OUT_BUSfmt */ 31575 /* nFields */ 5, 31576 /* *fields */ soc_IP_PARSER0_TOP_HME_OUT_BUSfmt_fields, 31577 /* bits */ 51, 31578 /* flags */ 0, 31579 }, 31580 #endif /* chips */ 31581 31582 #if defined(BCM_56370_A0) 31583 { /* SOC_FORMAT_INT_IP_PARSER1_TOP_HME_OUT_BUS_BCM56370_A0fmt */ 31584 /* format IP_PARSER1_TOP_HME_OUT_BUSfmt */ 31585 /* nFields */ 5, 31586 /* *fields */ soc_IP_PARSER0_TOP_HME_OUT_BUSfmt_fields, 31587 /* bits */ 51, 31588 /* flags */ 0, 31589 }, 31590 #endif /* chips */ 31591 31592 #if defined(BCM_56770_A0) 31593 { /* SOC_FORMAT_INT_IP_PARSER1_TOP_HME_OUT_BUS_BCM56770_A0fmt */ 31594 /* format IP_PARSER1_TOP_HME_OUT_BUSfmt */ 31595 /* nFields */ 5, 31596 /* *fields */ soc_IP_PARSER0_TOP_HME_OUT_BUSfmt_fields, 31597 /* bits */ 51, 31598 /* flags */ 0, 31599 }, 31600 #endif /* chips */ 31601 31602 #if defined(BCM_56870_A0) 31603 { /* SOC_FORMAT_INT_IP_PARSER2_FLEX_HVE_CONTROLSfmt */ 31604 /* format IP_PARSER2_FLEX_HVE_CONTROLSfmt */ 31605 /* nFields */ 33, 31606 /* *fields */ soc_IP_PARSER0_FLEX_HVE_CONTROLSfmt_fields, 31607 /* bits */ 33, 31608 /* flags */ 0, 31609 }, 31610 #endif /* chips */ 31611 31612 #if defined(BCM_56370_A0) 31613 { /* SOC_FORMAT_INT_IP_PARSER2_FLEX_HVE_CONTROLS_BCM56370_A0fmt */ 31614 /* format IP_PARSER2_FLEX_HVE_CONTROLSfmt */ 31615 /* nFields */ 33, 31616 /* *fields */ soc_IP_PARSER0_FLEX_HVE_CONTROLSfmt_fields, 31617 /* bits */ 33, 31618 /* flags */ 0, 31619 }, 31620 #endif /* chips */ 31621 31622 #if defined(BCM_56770_A0) 31623 { /* SOC_FORMAT_INT_IP_PARSER2_FLEX_HVE_CONTROLS_BCM56770_A0fmt */ 31624 /* format IP_PARSER2_FLEX_HVE_CONTROLSfmt */ 31625 /* nFields */ 33, 31626 /* *fields */ soc_IP_PARSER0_FLEX_HVE_CONTROLSfmt_fields, 31627 /* bits */ 33, 31628 /* flags */ 0, 31629 }, 31630 #endif /* chips */ 31631 31632 #if defined(BCM_56870_A0) 31633 { /* SOC_FORMAT_INT_IP_PARSER2_FLEX_HVE_IN_BUSfmt */ 31634 /* format IP_PARSER2_FLEX_HVE_IN_BUSfmt */ 31635 /* nFields */ 36, 31636 /* *fields */ soc_IP_PARSER1_FLEX_HVE_IN_BUSfmt_fields, 31637 /* bits */ 1420, 31638 /* flags */ 0, 31639 }, 31640 #endif /* chips */ 31641 31642 #if defined(BCM_56370_A0) 31643 { /* SOC_FORMAT_INT_IP_PARSER2_FLEX_HVE_IN_BUS_BCM56370_A0fmt */ 31644 /* format IP_PARSER2_FLEX_HVE_IN_BUSfmt */ 31645 /* nFields */ 36, 31646 /* *fields */ soc_IP_PARSER1_FLEX_HVE_IN_BUSfmt_fields, 31647 /* bits */ 1420, 31648 /* flags */ 0, 31649 }, 31650 #endif /* chips */ 31651 31652 #if defined(BCM_56770_A0) 31653 { /* SOC_FORMAT_INT_IP_PARSER2_FLEX_HVE_IN_BUS_BCM56770_A0fmt */ 31654 /* format IP_PARSER2_FLEX_HVE_IN_BUSfmt */ 31655 /* nFields */ 36, 31656 /* *fields */ soc_IP_PARSER1_FLEX_HVE_IN_BUSfmt_fields, 31657 /* bits */ 1420, 31658 /* flags */ 0, 31659 }, 31660 #endif /* chips */ 31661 31662 #if defined(BCM_56870_A0) 31663 { /* SOC_FORMAT_INT_IP_PARSER2_FLEX_HVE_OUT_BUSfmt */ 31664 /* format IP_PARSER2_FLEX_HVE_OUT_BUSfmt */ 31665 /* nFields */ 44, 31666 /* *fields */ soc_IP_PARSER0_FLEX_HVE_OUT_BUSfmt_fields, 31667 /* bits */ 110, 31668 /* flags */ 0, 31669 }, 31670 #endif /* chips */ 31671 31672 #if defined(BCM_56370_A0) 31673 { /* SOC_FORMAT_INT_IP_PARSER2_FLEX_HVE_OUT_BUS_BCM56370_A0fmt */ 31674 /* format IP_PARSER2_FLEX_HVE_OUT_BUSfmt */ 31675 /* nFields */ 44, 31676 /* *fields */ soc_IP_PARSER0_FLEX_HVE_OUT_BUSfmt_fields, 31677 /* bits */ 110, 31678 /* flags */ 0, 31679 }, 31680 #endif /* chips */ 31681 31682 #if defined(BCM_56770_A0) 31683 { /* SOC_FORMAT_INT_IP_PARSER2_FLEX_HVE_OUT_BUS_BCM56770_A0fmt */ 31684 /* format IP_PARSER2_FLEX_HVE_OUT_BUSfmt */ 31685 /* nFields */ 44, 31686 /* *fields */ soc_IP_PARSER0_FLEX_HVE_OUT_BUSfmt_fields, 31687 /* bits */ 110, 31688 /* flags */ 0, 31689 }, 31690 #endif /* chips */ 31691 31692 #if defined(BCM_56870_A0) 31693 { /* SOC_FORMAT_INT_IP_PARSER2_FLEX_HVE_OUT_CHECKfmt */ 31694 /* format IP_PARSER2_FLEX_HVE_OUT_CHECKfmt */ 31695 /* nFields */ 3, 31696 /* *fields */ soc_IP_PARSER0_FLEX_HVE_OUT_CHECKfmt_fields, 31697 /* bits */ 10, 31698 /* flags */ 0, 31699 }, 31700 #endif /* chips */ 31701 31702 #if defined(BCM_56370_A0) 31703 { /* SOC_FORMAT_INT_IP_PARSER2_FLEX_HVE_OUT_CHECK_BCM56370_A0fmt */ 31704 /* format IP_PARSER2_FLEX_HVE_OUT_CHECKfmt */ 31705 /* nFields */ 3, 31706 /* *fields */ soc_IP_PARSER0_FLEX_HVE_OUT_CHECKfmt_fields, 31707 /* bits */ 10, 31708 /* flags */ 0, 31709 }, 31710 #endif /* chips */ 31711 31712 #if defined(BCM_56770_A0) 31713 { /* SOC_FORMAT_INT_IP_PARSER2_FLEX_HVE_OUT_CHECK_BCM56770_A0fmt */ 31714 /* format IP_PARSER2_FLEX_HVE_OUT_CHECKfmt */ 31715 /* nFields */ 3, 31716 /* *fields */ soc_IP_PARSER0_FLEX_HVE_OUT_CHECKfmt_fields, 31717 /* bits */ 10, 31718 /* flags */ 0, 31719 }, 31720 #endif /* chips */ 31721 31722 #if defined(BCM_56870_A0) 31723 { /* SOC_FORMAT_INT_IP_PARSER2_HFE_CMD_POLICY_DATAfmt */ 31724 /* format IP_PARSER2_HFE_CMD_POLICY_DATAfmt */ 31725 /* nFields */ 48, 31726 /* *fields */ soc_IP_PARSER1_HFE_CMD_POLICY_DATAfmt_fields, 31727 /* bits */ 180, 31728 /* flags */ 0, 31729 }, 31730 #endif /* chips */ 31731 31732 #if defined(BCM_56370_A0) 31733 { /* SOC_FORMAT_INT_IP_PARSER2_HFE_CMD_POLICY_DATA_BCM56370_A0fmt */ 31734 /* format IP_PARSER2_HFE_CMD_POLICY_DATAfmt */ 31735 /* nFields */ 48, 31736 /* *fields */ soc_IP_PARSER1_HFE_CMD_POLICY_DATAfmt_fields, 31737 /* bits */ 180, 31738 /* flags */ 0, 31739 }, 31740 #endif /* chips */ 31741 31742 #if defined(BCM_56770_A0) 31743 { /* SOC_FORMAT_INT_IP_PARSER2_HFE_CMD_POLICY_DATA_BCM56770_A0fmt */ 31744 /* format IP_PARSER2_HFE_CMD_POLICY_DATAfmt */ 31745 /* nFields */ 48, 31746 /* *fields */ soc_IP_PARSER1_HFE_CMD_POLICY_DATAfmt_fields, 31747 /* bits */ 180, 31748 /* flags */ 0, 31749 }, 31750 #endif /* chips */ 31751 31752 #if defined(BCM_56870_A0) 31753 { /* SOC_FORMAT_INT_IP_PARSER2_HFE_CONSTANTSfmt */ 31754 /* format IP_PARSER2_HFE_CONSTANTSfmt */ 31755 /* nFields */ 1, 31756 /* *fields */ soc_EP_PARSER0_HFE_CONSTANTSfmt_fields, 31757 /* bits */ 1, 31758 /* flags */ 0, 31759 }, 31760 #endif /* chips */ 31761 31762 #if defined(BCM_56370_A0) 31763 { /* SOC_FORMAT_INT_IP_PARSER2_HFE_CONSTANTS_BCM56370_A0fmt */ 31764 /* format IP_PARSER2_HFE_CONSTANTSfmt */ 31765 /* nFields */ 1, 31766 /* *fields */ soc_EP_PARSER0_HFE_CONSTANTSfmt_fields, 31767 /* bits */ 1, 31768 /* flags */ 0, 31769 }, 31770 #endif /* chips */ 31771 31772 #if defined(BCM_56770_A0) 31773 { /* SOC_FORMAT_INT_IP_PARSER2_HFE_CONSTANTS_BCM56770_A0fmt */ 31774 /* format IP_PARSER2_HFE_CONSTANTSfmt */ 31775 /* nFields */ 1, 31776 /* *fields */ soc_EP_PARSER0_HFE_CONSTANTSfmt_fields, 31777 /* bits */ 1, 31778 /* flags */ 0, 31779 }, 31780 #endif /* chips */ 31781 31782 #if defined(BCM_56870_A0) 31783 { /* SOC_FORMAT_INT_IP_PARSER2_HFE_CONTROLSfmt */ 31784 /* format IP_PARSER2_HFE_CONTROLSfmt */ 31785 /* nFields */ 8, 31786 /* *fields */ soc_IP_PARSER1_HFE_CONTROLSfmt_fields, 31787 /* bits */ 98, 31788 /* flags */ 0, 31789 }, 31790 #endif /* chips */ 31791 31792 #if defined(BCM_56370_A0) 31793 { /* SOC_FORMAT_INT_IP_PARSER2_HFE_CONTROLS_BCM56370_A0fmt */ 31794 /* format IP_PARSER2_HFE_CONTROLSfmt */ 31795 /* nFields */ 8, 31796 /* *fields */ soc_IP_PARSER1_HFE_CONTROLSfmt_fields, 31797 /* bits */ 98, 31798 /* flags */ 0, 31799 }, 31800 #endif /* chips */ 31801 31802 #if defined(BCM_56770_A0) 31803 { /* SOC_FORMAT_INT_IP_PARSER2_HFE_CONTROLS_BCM56770_A0fmt */ 31804 /* format IP_PARSER2_HFE_CONTROLSfmt */ 31805 /* nFields */ 8, 31806 /* *fields */ soc_IP_PARSER1_HFE_CONTROLSfmt_fields, 31807 /* bits */ 98, 31808 /* flags */ 0, 31809 }, 31810 #endif /* chips */ 31811 31812 #if defined(BCM_56870_A0) 31813 { /* SOC_FORMAT_INT_IP_PARSER2_HFE_CONT_PROFILEfmt */ 31814 /* format IP_PARSER2_HFE_CONT_PROFILEfmt */ 31815 /* nFields */ 2, 31816 /* *fields */ soc_EP_PARSER1_HFE_CONT_PROFILEfmt_fields, 31817 /* bits */ 10, 31818 /* flags */ 0, 31819 }, 31820 #endif /* chips */ 31821 31822 #if defined(BCM_56370_A0) 31823 { /* SOC_FORMAT_INT_IP_PARSER2_HFE_CONT_PROFILE_BCM56370_A0fmt */ 31824 /* format IP_PARSER2_HFE_CONT_PROFILEfmt */ 31825 /* nFields */ 2, 31826 /* *fields */ soc_EP_PARSER1_HFE_CONT_PROFILEfmt_fields, 31827 /* bits */ 10, 31828 /* flags */ 0, 31829 }, 31830 #endif /* chips */ 31831 31832 #if defined(BCM_56770_A0) 31833 { /* SOC_FORMAT_INT_IP_PARSER2_HFE_CONT_PROFILE_BCM56770_A0fmt */ 31834 /* format IP_PARSER2_HFE_CONT_PROFILEfmt */ 31835 /* nFields */ 2, 31836 /* *fields */ soc_EP_PARSER1_HFE_CONT_PROFILEfmt_fields, 31837 /* bits */ 10, 31838 /* flags */ 0, 31839 }, 31840 #endif /* chips */ 31841 31842 #if defined(BCM_56870_A0) 31843 { /* SOC_FORMAT_INT_IP_PARSER2_HFE_IN_BUSfmt */ 31844 /* format IP_PARSER2_HFE_IN_BUSfmt */ 31845 /* nFields */ 10, 31846 /* *fields */ soc_IP_PARSER1_HFE_IN_BUSfmt_fields, 31847 /* bits */ 1250, 31848 /* flags */ 0, 31849 }, 31850 #endif /* chips */ 31851 31852 #if defined(BCM_56370_A0) 31853 { /* SOC_FORMAT_INT_IP_PARSER2_HFE_IN_BUS_BCM56370_A0fmt */ 31854 /* format IP_PARSER2_HFE_IN_BUSfmt */ 31855 /* nFields */ 10, 31856 /* *fields */ soc_IP_PARSER1_HFE_IN_BUSfmt_fields, 31857 /* bits */ 1250, 31858 /* flags */ 0, 31859 }, 31860 #endif /* chips */ 31861 31862 #if defined(BCM_56770_A0) 31863 { /* SOC_FORMAT_INT_IP_PARSER2_HFE_IN_BUS_BCM56770_A0fmt */ 31864 /* format IP_PARSER2_HFE_IN_BUSfmt */ 31865 /* nFields */ 10, 31866 /* *fields */ soc_IP_PARSER1_HFE_IN_BUSfmt_fields, 31867 /* bits */ 1250, 31868 /* flags */ 0, 31869 }, 31870 #endif /* chips */ 31871 31872 #if defined(BCM_56870_A0) 31873 { /* SOC_FORMAT_INT_IP_PARSER2_HFE_MUX_CONTROLSfmt */ 31874 /* format IP_PARSER2_HFE_MUX_CONTROLSfmt */ 31875 /* nFields */ 5, 31876 /* *fields */ soc_IP_PARSER1_HFE_MUX_CONTROLSfmt_fields, 31877 /* bits */ 58, 31878 /* flags */ 0, 31879 }, 31880 #endif /* chips */ 31881 31882 #if defined(BCM_56370_A0) 31883 { /* SOC_FORMAT_INT_IP_PARSER2_HFE_MUX_CONTROLS_BCM56370_A0fmt */ 31884 /* format IP_PARSER2_HFE_MUX_CONTROLSfmt */ 31885 /* nFields */ 5, 31886 /* *fields */ soc_IP_PARSER1_HFE_MUX_CONTROLSfmt_fields, 31887 /* bits */ 58, 31888 /* flags */ 0, 31889 }, 31890 #endif /* chips */ 31891 31892 #if defined(BCM_56770_A0) 31893 { /* SOC_FORMAT_INT_IP_PARSER2_HFE_MUX_CONTROLS_BCM56770_A0fmt */ 31894 /* format IP_PARSER2_HFE_MUX_CONTROLSfmt */ 31895 /* nFields */ 5, 31896 /* *fields */ soc_IP_PARSER1_HFE_MUX_CONTROLSfmt_fields, 31897 /* bits */ 58, 31898 /* flags */ 0, 31899 }, 31900 #endif /* chips */ 31901 31902 #if defined(BCM_56870_A0) 31903 { /* SOC_FORMAT_INT_IP_PARSER2_HFE_MUX_IN_BUSfmt */ 31904 /* format IP_PARSER2_HFE_MUX_IN_BUSfmt */ 31905 /* nFields */ 22, 31906 /* *fields */ soc_IP_PARSER1_HFE_MUX_IN_BUSfmt_fields, 31907 /* bits */ 2210, 31908 /* flags */ 0, 31909 }, 31910 #endif /* chips */ 31911 31912 #if defined(BCM_56370_A0) 31913 { /* SOC_FORMAT_INT_IP_PARSER2_HFE_MUX_IN_BUS_BCM56370_A0fmt */ 31914 /* format IP_PARSER2_HFE_MUX_IN_BUSfmt */ 31915 /* nFields */ 22, 31916 /* *fields */ soc_IP_PARSER1_HFE_MUX_IN_BUSfmt_fields, 31917 /* bits */ 2210, 31918 /* flags */ 0, 31919 }, 31920 #endif /* chips */ 31921 31922 #if defined(BCM_56770_A0) 31923 { /* SOC_FORMAT_INT_IP_PARSER2_HFE_MUX_IN_BUS_BCM56770_A0fmt */ 31924 /* format IP_PARSER2_HFE_MUX_IN_BUSfmt */ 31925 /* nFields */ 22, 31926 /* *fields */ soc_IP_PARSER1_HFE_MUX_IN_BUSfmt_fields, 31927 /* bits */ 2210, 31928 /* flags */ 0, 31929 }, 31930 #endif /* chips */ 31931 31932 #if defined(BCM_56870_A0) 31933 { /* SOC_FORMAT_INT_IP_PARSER2_HFE_MUX_OUT_BUSfmt */ 31934 /* format IP_PARSER2_HFE_MUX_OUT_BUSfmt */ 31935 /* nFields */ 97, 31936 /* *fields */ soc_IP_PARSER1_HFE_MUX_OUT_BUSfmt_fields, 31937 /* bits */ 1386, 31938 /* flags */ 0, 31939 }, 31940 #endif /* chips */ 31941 31942 #if defined(BCM_56370_A0) 31943 { /* SOC_FORMAT_INT_IP_PARSER2_HFE_MUX_OUT_BUS_BCM56370_A0fmt */ 31944 /* format IP_PARSER2_HFE_MUX_OUT_BUSfmt */ 31945 /* nFields */ 97, 31946 /* *fields */ soc_IP_PARSER1_HFE_MUX_OUT_BUSfmt_fields, 31947 /* bits */ 1386, 31948 /* flags */ 0, 31949 }, 31950 #endif /* chips */ 31951 31952 #if defined(BCM_56770_A0) 31953 { /* SOC_FORMAT_INT_IP_PARSER2_HFE_MUX_OUT_BUS_BCM56770_A0fmt */ 31954 /* format IP_PARSER2_HFE_MUX_OUT_BUSfmt */ 31955 /* nFields */ 97, 31956 /* *fields */ soc_IP_PARSER1_HFE_MUX_OUT_BUSfmt_fields, 31957 /* bits */ 1386, 31958 /* flags */ 0, 31959 }, 31960 #endif /* chips */ 31961 31962 #if defined(BCM_56870_A0) 31963 { /* SOC_FORMAT_INT_IP_PARSER2_HFE_OUT_BUSfmt */ 31964 /* format IP_PARSER2_HFE_OUT_BUSfmt */ 31965 /* nFields */ 98, 31966 /* *fields */ soc_IP_PARSER1_HFE_OUT_BUSfmt_fields, 31967 /* bits */ 1386, 31968 /* flags */ 0, 31969 }, 31970 #endif /* chips */ 31971 31972 #if defined(BCM_56370_A0) 31973 { /* SOC_FORMAT_INT_IP_PARSER2_HFE_OUT_BUS_BCM56370_A0fmt */ 31974 /* format IP_PARSER2_HFE_OUT_BUSfmt */ 31975 /* nFields */ 98, 31976 /* *fields */ soc_IP_PARSER1_HFE_OUT_BUSfmt_fields, 31977 /* bits */ 1386, 31978 /* flags */ 0, 31979 }, 31980 #endif /* chips */ 31981 31982 #if defined(BCM_56770_A0) 31983 { /* SOC_FORMAT_INT_IP_PARSER2_HFE_OUT_BUS_BCM56770_A0fmt */ 31984 /* format IP_PARSER2_HFE_OUT_BUSfmt */ 31985 /* nFields */ 98, 31986 /* *fields */ soc_IP_PARSER1_HFE_OUT_BUSfmt_fields, 31987 /* bits */ 1386, 31988 /* flags */ 0, 31989 }, 31990 #endif /* chips */ 31991 31992 #if defined(BCM_56870_A0) 31993 { /* SOC_FORMAT_INT_IP_PARSER2_HFE_POLICY_COMMAND_Afmt */ 31994 /* format IP_PARSER2_HFE_POLICY_COMMAND_Afmt */ 31995 /* nFields */ 3, 31996 /* *fields */ soc_EP_PARSER1_HFE_POLICY_COMMAND_Afmt_fields, 31997 /* bits */ 2, 31998 /* flags */ 0, 31999 }, 32000 #endif /* chips */ 32001 32002 #if defined(BCM_56370_A0) 32003 { /* SOC_FORMAT_INT_IP_PARSER2_HFE_POLICY_COMMAND_A_BCM56370_A0fmt */ 32004 /* format IP_PARSER2_HFE_POLICY_COMMAND_Afmt */ 32005 /* nFields */ 3, 32006 /* *fields */ soc_EP_PARSER1_HFE_POLICY_COMMAND_Afmt_fields, 32007 /* bits */ 2, 32008 /* flags */ 0, 32009 }, 32010 #endif /* chips */ 32011 32012 #if defined(BCM_56770_A0) 32013 { /* SOC_FORMAT_INT_IP_PARSER2_HFE_POLICY_COMMAND_A_BCM56770_A0fmt */ 32014 /* format IP_PARSER2_HFE_POLICY_COMMAND_Afmt */ 32015 /* nFields */ 3, 32016 /* *fields */ soc_EP_PARSER1_HFE_POLICY_COMMAND_Afmt_fields, 32017 /* bits */ 2, 32018 /* flags */ 0, 32019 }, 32020 #endif /* chips */ 32021 32022 #if defined(BCM_56870_A0) 32023 { /* SOC_FORMAT_INT_IP_PARSER2_HFE_POLICY_COMMAND_Bfmt */ 32024 /* format IP_PARSER2_HFE_POLICY_COMMAND_Bfmt */ 32025 /* nFields */ 6, 32026 /* *fields */ soc_EP_PARSER1_HFE_POLICY_COMMAND_Bfmt_fields, 32027 /* bits */ 2, 32028 /* flags */ 0, 32029 }, 32030 #endif /* chips */ 32031 32032 #if defined(BCM_56370_A0) 32033 { /* SOC_FORMAT_INT_IP_PARSER2_HFE_POLICY_COMMAND_B_BCM56370_A0fmt */ 32034 /* format IP_PARSER2_HFE_POLICY_COMMAND_Bfmt */ 32035 /* nFields */ 6, 32036 /* *fields */ soc_EP_PARSER1_HFE_POLICY_COMMAND_Bfmt_fields, 32037 /* bits */ 2, 32038 /* flags */ 0, 32039 }, 32040 #endif /* chips */ 32041 32042 #if defined(BCM_56770_A0) 32043 { /* SOC_FORMAT_INT_IP_PARSER2_HFE_POLICY_COMMAND_B_BCM56770_A0fmt */ 32044 /* format IP_PARSER2_HFE_POLICY_COMMAND_Bfmt */ 32045 /* nFields */ 6, 32046 /* *fields */ soc_EP_PARSER1_HFE_POLICY_COMMAND_Bfmt_fields, 32047 /* bits */ 2, 32048 /* flags */ 0, 32049 }, 32050 #endif /* chips */ 32051 32052 #if defined(BCM_56870_A0) 32053 { /* SOC_FORMAT_INT_IP_PARSER2_HFE_POLICY_COMMAND_Cfmt */ 32054 /* format IP_PARSER2_HFE_POLICY_COMMAND_Cfmt */ 32055 /* nFields */ 3, 32056 /* *fields */ soc_IP_PARSER1_HFE_POLICY_COMMAND_Cfmt_fields, 32057 /* bits */ 15, 32058 /* flags */ 0, 32059 }, 32060 #endif /* chips */ 32061 32062 #if defined(BCM_56370_A0) 32063 { /* SOC_FORMAT_INT_IP_PARSER2_HFE_POLICY_COMMAND_C_BCM56370_A0fmt */ 32064 /* format IP_PARSER2_HFE_POLICY_COMMAND_Cfmt */ 32065 /* nFields */ 3, 32066 /* *fields */ soc_IP_PARSER1_HFE_POLICY_COMMAND_Cfmt_fields, 32067 /* bits */ 15, 32068 /* flags */ 0, 32069 }, 32070 #endif /* chips */ 32071 32072 #if defined(BCM_56770_A0) 32073 { /* SOC_FORMAT_INT_IP_PARSER2_HFE_POLICY_COMMAND_C_BCM56770_A0fmt */ 32074 /* format IP_PARSER2_HFE_POLICY_COMMAND_Cfmt */ 32075 /* nFields */ 3, 32076 /* *fields */ soc_IP_PARSER1_HFE_POLICY_COMMAND_Cfmt_fields, 32077 /* bits */ 15, 32078 /* flags */ 0, 32079 }, 32080 #endif /* chips */ 32081 32082 #if defined(BCM_56870_A0) 32083 { /* SOC_FORMAT_INT_IP_PARSER2_HFE_POLICY_COMMAND_Dfmt */ 32084 /* format IP_PARSER2_HFE_POLICY_COMMAND_Dfmt */ 32085 /* nFields */ 5, 32086 /* *fields */ soc_EP_PARSER0_HFE_POLICY_COMMAND_Dfmt_fields, 32087 /* bits */ 4, 32088 /* flags */ 0, 32089 }, 32090 #endif /* chips */ 32091 32092 #if defined(BCM_56370_A0) 32093 { /* SOC_FORMAT_INT_IP_PARSER2_HFE_POLICY_COMMAND_D_BCM56370_A0fmt */ 32094 /* format IP_PARSER2_HFE_POLICY_COMMAND_Dfmt */ 32095 /* nFields */ 5, 32096 /* *fields */ soc_EP_PARSER0_HFE_POLICY_COMMAND_Dfmt_fields, 32097 /* bits */ 4, 32098 /* flags */ 0, 32099 }, 32100 #endif /* chips */ 32101 32102 #if defined(BCM_56770_A0) 32103 { /* SOC_FORMAT_INT_IP_PARSER2_HFE_POLICY_COMMAND_D_BCM56770_A0fmt */ 32104 /* format IP_PARSER2_HFE_POLICY_COMMAND_Dfmt */ 32105 /* nFields */ 5, 32106 /* *fields */ soc_EP_PARSER0_HFE_POLICY_COMMAND_Dfmt_fields, 32107 /* bits */ 4, 32108 /* flags */ 0, 32109 }, 32110 #endif /* chips */ 32111 32112 #if defined(BCM_56870_A0) 32113 { /* SOC_FORMAT_INT_IP_PARSER2_HFE_POLICY_TABLE_DATAfmt */ 32114 /* format IP_PARSER2_HFE_POLICY_TABLE_DATAfmt */ 32115 /* nFields */ 11, 32116 /* *fields */ soc_IP_PARSER1_HFE_POLICY_TABLE_DATAfmt_fields, 32117 /* bits */ 200, 32118 /* flags */ 0, 32119 }, 32120 #endif /* chips */ 32121 32122 #if defined(BCM_56370_A0) 32123 { /* SOC_FORMAT_INT_IP_PARSER2_HFE_POLICY_TABLE_DATA_BCM56370_A0fmt */ 32124 /* format IP_PARSER2_HFE_POLICY_TABLE_DATAfmt */ 32125 /* nFields */ 11, 32126 /* *fields */ soc_IP_PARSER1_HFE_POLICY_TABLE_DATAfmt_fields, 32127 /* bits */ 200, 32128 /* flags */ 0, 32129 }, 32130 #endif /* chips */ 32131 32132 #if defined(BCM_56770_A0) 32133 { /* SOC_FORMAT_INT_IP_PARSER2_HFE_POLICY_TABLE_DATA_BCM56770_A0fmt */ 32134 /* format IP_PARSER2_HFE_POLICY_TABLE_DATAfmt */ 32135 /* nFields */ 11, 32136 /* *fields */ soc_IP_PARSER1_HFE_POLICY_TABLE_DATAfmt_fields, 32137 /* bits */ 200, 32138 /* flags */ 0, 32139 }, 32140 #endif /* chips */ 32141 32142 #if defined(BCM_56870_A0) 32143 { /* SOC_FORMAT_INT_IP_PARSER2_HME_CONSTANTSfmt */ 32144 /* format IP_PARSER2_HME_CONSTANTSfmt */ 32145 /* nFields */ 1, 32146 /* *fields */ soc_EP_PARSER0_HFE_CONSTANTSfmt_fields, 32147 /* bits */ 1, 32148 /* flags */ 0, 32149 }, 32150 #endif /* chips */ 32151 32152 #if defined(BCM_56370_A0) 32153 { /* SOC_FORMAT_INT_IP_PARSER2_HME_CONSTANTS_BCM56370_A0fmt */ 32154 /* format IP_PARSER2_HME_CONSTANTSfmt */ 32155 /* nFields */ 1, 32156 /* *fields */ soc_EP_PARSER0_HFE_CONSTANTSfmt_fields, 32157 /* bits */ 1, 32158 /* flags */ 0, 32159 }, 32160 #endif /* chips */ 32161 32162 #if defined(BCM_56770_A0) 32163 { /* SOC_FORMAT_INT_IP_PARSER2_HME_CONSTANTS_BCM56770_A0fmt */ 32164 /* format IP_PARSER2_HME_CONSTANTSfmt */ 32165 /* nFields */ 1, 32166 /* *fields */ soc_EP_PARSER0_HFE_CONSTANTSfmt_fields, 32167 /* bits */ 1, 32168 /* flags */ 0, 32169 }, 32170 #endif /* chips */ 32171 32172 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 32173 defined(BCM_56870_A0) 32174 { /* SOC_FORMAT_INT_IP_PARSER2_HME_IN_BUSfmt */ 32175 /* format IP_PARSER2_HME_IN_BUSfmt */ 32176 /* nFields */ 11, 32177 /* *fields */ soc_IP_PARSER2_HME_IN_BUSfmt_fields, 32178 /* bits */ 1269, 32179 /* flags */ 0, 32180 }, 32181 #endif /* chips */ 32182 32183 #if defined(BCM_56870_A0) 32184 { /* SOC_FORMAT_INT_IP_PARSER2_HME_LATENCY_CONTROLSfmt */ 32185 /* format IP_PARSER2_HME_LATENCY_CONTROLSfmt */ 32186 /* nFields */ 2, 32187 /* *fields */ soc_IP_PARSER1_HME_LATENCY_CONTROLSfmt_fields, 32188 /* bits */ 6, 32189 /* flags */ 0, 32190 }, 32191 #endif /* chips */ 32192 32193 #if defined(BCM_56370_A0) 32194 { /* SOC_FORMAT_INT_IP_PARSER2_HME_LATENCY_CONTROLS_BCM56370_A0fmt */ 32195 /* format IP_PARSER2_HME_LATENCY_CONTROLSfmt */ 32196 /* nFields */ 2, 32197 /* *fields */ soc_IP_PARSER1_HME_LATENCY_CONTROLSfmt_fields, 32198 /* bits */ 6, 32199 /* flags */ 0, 32200 }, 32201 #endif /* chips */ 32202 32203 #if defined(BCM_56770_A0) 32204 { /* SOC_FORMAT_INT_IP_PARSER2_HME_LATENCY_CONTROLS_BCM56770_A0fmt */ 32205 /* format IP_PARSER2_HME_LATENCY_CONTROLSfmt */ 32206 /* nFields */ 2, 32207 /* *fields */ soc_IP_PARSER1_HME_LATENCY_CONTROLSfmt_fields, 32208 /* bits */ 6, 32209 /* flags */ 0, 32210 }, 32211 #endif /* chips */ 32212 32213 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 32214 defined(BCM_56870_A0) 32215 { /* SOC_FORMAT_INT_IP_PARSER2_HME_OUT_BUSfmt */ 32216 /* format IP_PARSER2_HME_OUT_BUSfmt */ 32217 /* nFields */ 17, 32218 /* *fields */ soc_IP_PARSER2_HME_OUT_BUSfmt_fields, 32219 /* bits */ 1379, 32220 /* flags */ 0, 32221 }, 32222 #endif /* chips */ 32223 32224 #if defined(BCM_56870_A0) 32225 { /* SOC_FORMAT_INT_IP_PARSER2_HME_PASSTHROUGH_BUSfmt */ 32226 /* format IP_PARSER2_HME_PASSTHROUGH_BUSfmt */ 32227 /* nFields */ 3, 32228 /* *fields */ soc_IP_PARSER1_HME_PASSTHROUGH_BUSfmt_fields, 32229 /* bits */ 10, 32230 /* flags */ 0, 32231 }, 32232 #endif /* chips */ 32233 32234 #if defined(BCM_56370_A0) 32235 { /* SOC_FORMAT_INT_IP_PARSER2_HME_PASSTHROUGH_BUS_BCM56370_A0fmt */ 32236 /* format IP_PARSER2_HME_PASSTHROUGH_BUSfmt */ 32237 /* nFields */ 3, 32238 /* *fields */ soc_IP_PARSER1_HME_PASSTHROUGH_BUSfmt_fields, 32239 /* bits */ 10, 32240 /* flags */ 0, 32241 }, 32242 #endif /* chips */ 32243 32244 #if defined(BCM_56770_A0) 32245 { /* SOC_FORMAT_INT_IP_PARSER2_HME_PASSTHROUGH_BUS_BCM56770_A0fmt */ 32246 /* format IP_PARSER2_HME_PASSTHROUGH_BUSfmt */ 32247 /* nFields */ 3, 32248 /* *fields */ soc_IP_PARSER1_HME_PASSTHROUGH_BUSfmt_fields, 32249 /* bits */ 10, 32250 /* flags */ 0, 32251 }, 32252 #endif /* chips */ 32253 32254 #if defined(BCM_56870_A0) 32255 { /* SOC_FORMAT_INT_IP_PARSER2_HME_POLICY_ACTIONfmt */ 32256 /* format IP_PARSER2_HME_POLICY_ACTIONfmt */ 32257 /* nFields */ 3, 32258 /* *fields */ soc_IP_PARSER0_HME_POLICY_ACTIONfmt_fields, 32259 /* bits */ 3, 32260 /* flags */ 0, 32261 }, 32262 #endif /* chips */ 32263 32264 #if defined(BCM_56370_A0) 32265 { /* SOC_FORMAT_INT_IP_PARSER2_HME_POLICY_ACTION_BCM56370_A0fmt */ 32266 /* format IP_PARSER2_HME_POLICY_ACTIONfmt */ 32267 /* nFields */ 3, 32268 /* *fields */ soc_IP_PARSER0_HME_POLICY_ACTIONfmt_fields, 32269 /* bits */ 3, 32270 /* flags */ 0, 32271 }, 32272 #endif /* chips */ 32273 32274 #if defined(BCM_56770_A0) 32275 { /* SOC_FORMAT_INT_IP_PARSER2_HME_POLICY_ACTION_BCM56770_A0fmt */ 32276 /* format IP_PARSER2_HME_POLICY_ACTIONfmt */ 32277 /* nFields */ 3, 32278 /* *fields */ soc_IP_PARSER0_HME_POLICY_ACTIONfmt_fields, 32279 /* bits */ 3, 32280 /* flags */ 0, 32281 }, 32282 #endif /* chips */ 32283 32284 #if defined(BCM_56870_A0) 32285 { /* SOC_FORMAT_INT_IP_PARSER2_HME_STAGE_COMMON_BUSfmt */ 32286 /* format IP_PARSER2_HME_STAGE_COMMON_BUSfmt */ 32287 /* nFields */ 3, 32288 /* *fields */ soc_IP_PARSER0_HME_STAGE_COMMON_BUSfmt_fields, 32289 /* bits */ 10, 32290 /* flags */ 0, 32291 }, 32292 #endif /* chips */ 32293 32294 #if defined(BCM_56370_A0) 32295 { /* SOC_FORMAT_INT_IP_PARSER2_HME_STAGE_COMMON_BUS_BCM56370_A0fmt */ 32296 /* format IP_PARSER2_HME_STAGE_COMMON_BUSfmt */ 32297 /* nFields */ 3, 32298 /* *fields */ soc_IP_PARSER0_HME_STAGE_COMMON_BUSfmt_fields, 32299 /* bits */ 10, 32300 /* flags */ 0, 32301 }, 32302 #endif /* chips */ 32303 32304 #if defined(BCM_56770_A0) 32305 { /* SOC_FORMAT_INT_IP_PARSER2_HME_STAGE_COMMON_BUS_BCM56770_A0fmt */ 32306 /* format IP_PARSER2_HME_STAGE_COMMON_BUSfmt */ 32307 /* nFields */ 3, 32308 /* *fields */ soc_IP_PARSER0_HME_STAGE_COMMON_BUSfmt_fields, 32309 /* bits */ 10, 32310 /* flags */ 0, 32311 }, 32312 #endif /* chips */ 32313 32314 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 32315 defined(BCM_56870_A0) 32316 { /* SOC_FORMAT_INT_IP_PARSER2_HME_STAGE_IN_BUSfmt */ 32317 /* format IP_PARSER2_HME_STAGE_IN_BUSfmt */ 32318 /* nFields */ 13, 32319 /* *fields */ soc_IP_PARSER2_HME_STAGE_IN_BUSfmt_fields, 32320 /* bits */ 1264, 32321 /* flags */ 0, 32322 }, 32323 #endif /* chips */ 32324 32325 #if defined(BCM_56870_A0) 32326 { /* SOC_FORMAT_INT_IP_PARSER2_HME_STAGE_KEY_VALID_BYTES_CHECK_DATAfmt */ 32327 /* format IP_PARSER2_HME_STAGE_KEY_VALID_BYTES_CHECK_DATAfmt */ 32328 /* nFields */ 16, 32329 /* *fields */ soc_IP_PARSER1_HME_STAGE_KEY_VALID_BYTES_CHECK_DATAfmt_fields, 32330 /* bits */ 128, 32331 /* flags */ 0, 32332 }, 32333 #endif /* chips */ 32334 32335 #if defined(BCM_56370_A0) 32336 { /* SOC_FORMAT_INT_IP_PARSER2_HME_STAGE_KEY_VALID_BYTES_CHECK_DATA_BCM56370_A0fmt */ 32337 /* format IP_PARSER2_HME_STAGE_KEY_VALID_BYTES_CHECK_DATAfmt */ 32338 /* nFields */ 16, 32339 /* *fields */ soc_IP_PARSER1_HME_STAGE_KEY_VALID_BYTES_CHECK_DATAfmt_fields, 32340 /* bits */ 128, 32341 /* flags */ 0, 32342 }, 32343 #endif /* chips */ 32344 32345 #if defined(BCM_56770_A0) 32346 { /* SOC_FORMAT_INT_IP_PARSER2_HME_STAGE_KEY_VALID_BYTES_CHECK_DATA_BCM56770_A0fmt */ 32347 /* format IP_PARSER2_HME_STAGE_KEY_VALID_BYTES_CHECK_DATAfmt */ 32348 /* nFields */ 16, 32349 /* *fields */ soc_IP_PARSER1_HME_STAGE_KEY_VALID_BYTES_CHECK_DATAfmt_fields, 32350 /* bits */ 128, 32351 /* flags */ 0, 32352 }, 32353 #endif /* chips */ 32354 32355 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 32356 defined(BCM_56870_A0) 32357 { /* SOC_FORMAT_INT_IP_PARSER2_HME_STAGE_OUT_BUSfmt */ 32358 /* format IP_PARSER2_HME_STAGE_OUT_BUSfmt */ 32359 /* nFields */ 20, 32360 /* *fields */ soc_IP_PARSER2_HME_STAGE_OUT_BUSfmt_fields, 32361 /* bits */ 1280, 32362 /* flags */ 0, 32363 }, 32364 #endif /* chips */ 32365 32366 #if defined(BCM_56870_A0) 32367 { /* SOC_FORMAT_INT_IP_PARSER2_HME_STAGE_OUT_ONLY_BUSfmt */ 32368 /* format IP_PARSER2_HME_STAGE_OUT_ONLY_BUSfmt */ 32369 /* nFields */ 10, 32370 /* *fields */ soc_IP_PARSER1_HME_STAGE_OUT_ONLY_BUSfmt_fields, 32371 /* bits */ 25, 32372 /* flags */ 0, 32373 }, 32374 #endif /* chips */ 32375 32376 #if defined(BCM_56370_A0) 32377 { /* SOC_FORMAT_INT_IP_PARSER2_HME_STAGE_OUT_ONLY_BUS_BCM56370_A0fmt */ 32378 /* format IP_PARSER2_HME_STAGE_OUT_ONLY_BUSfmt */ 32379 /* nFields */ 10, 32380 /* *fields */ soc_IP_PARSER1_HME_STAGE_OUT_ONLY_BUSfmt_fields, 32381 /* bits */ 25, 32382 /* flags */ 0, 32383 }, 32384 #endif /* chips */ 32385 32386 #if defined(BCM_56770_A0) 32387 { /* SOC_FORMAT_INT_IP_PARSER2_HME_STAGE_OUT_ONLY_BUS_BCM56770_A0fmt */ 32388 /* format IP_PARSER2_HME_STAGE_OUT_ONLY_BUSfmt */ 32389 /* nFields */ 10, 32390 /* *fields */ soc_IP_PARSER1_HME_STAGE_OUT_ONLY_BUSfmt_fields, 32391 /* bits */ 25, 32392 /* flags */ 0, 32393 }, 32394 #endif /* chips */ 32395 32396 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 32397 defined(BCM_56870_A0) 32398 { /* SOC_FORMAT_INT_IP_PARSER2_HME_STAGE_PIPE_BUSfmt */ 32399 /* format IP_PARSER2_HME_STAGE_PIPE_BUSfmt */ 32400 /* nFields */ 8, 32401 /* *fields */ soc_IP_PARSER2_HME_STAGE_PIPE_BUSfmt_fields, 32402 /* bits */ 1254, 32403 /* flags */ 0, 32404 }, 32405 #endif /* chips */ 32406 32407 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 32408 defined(BCM_56870_A0) 32409 { /* SOC_FORMAT_INT_IP_PARSER2_HME_STAGE_TCAM_DATAfmt */ 32410 /* format IP_PARSER2_HME_STAGE_TCAM_DATAfmt */ 32411 /* nFields */ 30, 32412 /* *fields */ soc_IP_PARSER2_HME_STAGE_TCAM_DATAfmt_fields, 32413 /* bits */ 140, 32414 /* flags */ 0, 32415 }, 32416 #endif /* chips */ 32417 32418 #if defined(BCM_56870_A0) 32419 { /* SOC_FORMAT_INT_IP_PARSER2_HME_STAGE_TCAM_KEYfmt */ 32420 /* format IP_PARSER2_HME_STAGE_TCAM_KEYfmt */ 32421 /* nFields */ 5, 32422 /* *fields */ soc_IP_PARSER1_HME_STAGE_TCAM_KEYfmt_fields, 32423 /* bits */ 192, 32424 /* flags */ 0, 32425 }, 32426 #endif /* chips */ 32427 32428 #if defined(BCM_56370_A0) 32429 { /* SOC_FORMAT_INT_IP_PARSER2_HME_STAGE_TCAM_KEY_BCM56370_A0fmt */ 32430 /* format IP_PARSER2_HME_STAGE_TCAM_KEYfmt */ 32431 /* nFields */ 5, 32432 /* *fields */ soc_IP_PARSER1_HME_STAGE_TCAM_KEYfmt_fields, 32433 /* bits */ 192, 32434 /* flags */ 0, 32435 }, 32436 #endif /* chips */ 32437 32438 #if defined(BCM_56770_A0) 32439 { /* SOC_FORMAT_INT_IP_PARSER2_HME_STAGE_TCAM_KEY_BCM56770_A0fmt */ 32440 /* format IP_PARSER2_HME_STAGE_TCAM_KEYfmt */ 32441 /* nFields */ 5, 32442 /* *fields */ soc_IP_PARSER1_HME_STAGE_TCAM_KEYfmt_fields, 32443 /* bits */ 192, 32444 /* flags */ 0, 32445 }, 32446 #endif /* chips */ 32447 32448 #if defined(BCM_56870_A0) 32449 { /* SOC_FORMAT_INT_IP_PARSER2_HME_STAGE_TCAM_KEY_NARROWfmt */ 32450 /* format IP_PARSER2_HME_STAGE_TCAM_KEY_NARROWfmt */ 32451 /* nFields */ 5, 32452 /* *fields */ soc_IP_PARSER1_HME_STAGE_TCAM_KEY_NARROWfmt_fields, 32453 /* bits */ 96, 32454 /* flags */ 0, 32455 }, 32456 #endif /* chips */ 32457 32458 #if defined(BCM_56370_A0) 32459 { /* SOC_FORMAT_INT_IP_PARSER2_HME_STAGE_TCAM_KEY_NARROW_BCM56370_A0fmt */ 32460 /* format IP_PARSER2_HME_STAGE_TCAM_KEY_NARROWfmt */ 32461 /* nFields */ 5, 32462 /* *fields */ soc_IP_PARSER1_HME_STAGE_TCAM_KEY_NARROWfmt_fields, 32463 /* bits */ 96, 32464 /* flags */ 0, 32465 }, 32466 #endif /* chips */ 32467 32468 #if defined(BCM_56770_A0) 32469 { /* SOC_FORMAT_INT_IP_PARSER2_HME_STAGE_TCAM_KEY_NARROW_BCM56770_A0fmt */ 32470 /* format IP_PARSER2_HME_STAGE_TCAM_KEY_NARROWfmt */ 32471 /* nFields */ 5, 32472 /* *fields */ soc_IP_PARSER1_HME_STAGE_TCAM_KEY_NARROWfmt_fields, 32473 /* bits */ 96, 32474 /* flags */ 0, 32475 }, 32476 #endif /* chips */ 32477 32478 #if defined(BCM_56870_A0) 32479 { /* SOC_FORMAT_INT_IP_PARSER2_HVE_CONTROLSfmt */ 32480 /* format IP_PARSER2_HVE_CONTROLSfmt */ 32481 /* nFields */ 4, 32482 /* *fields */ soc_IP_PARSER1_HVE_CONTROLSfmt_fields, 32483 /* bits */ 65, 32484 /* flags */ 0, 32485 }, 32486 #endif /* chips */ 32487 32488 #if defined(BCM_56370_A0) 32489 { /* SOC_FORMAT_INT_IP_PARSER2_HVE_CONTROLS_BCM56370_A0fmt */ 32490 /* format IP_PARSER2_HVE_CONTROLSfmt */ 32491 /* nFields */ 4, 32492 /* *fields */ soc_IP_PARSER1_HVE_CONTROLSfmt_fields, 32493 /* bits */ 65, 32494 /* flags */ 0, 32495 }, 32496 #endif /* chips */ 32497 32498 #if defined(BCM_56770_A0) 32499 { /* SOC_FORMAT_INT_IP_PARSER2_HVE_CONTROLS_BCM56770_A0fmt */ 32500 /* format IP_PARSER2_HVE_CONTROLSfmt */ 32501 /* nFields */ 4, 32502 /* *fields */ soc_IP_PARSER1_HVE_CONTROLSfmt_fields, 32503 /* bits */ 65, 32504 /* flags */ 0, 32505 }, 32506 #endif /* chips */ 32507 32508 #if defined(BCM_56870_A0) 32509 { /* SOC_FORMAT_INT_IP_PARSER2_HVE_IN_BUSfmt */ 32510 /* format IP_PARSER2_HVE_IN_BUSfmt */ 32511 /* nFields */ 7, 32512 /* *fields */ soc_IP_PARSER1_HVE_IN_BUSfmt_fields, 32513 /* bits */ 1452, 32514 /* flags */ 0, 32515 }, 32516 #endif /* chips */ 32517 32518 #if defined(BCM_56370_A0) 32519 { /* SOC_FORMAT_INT_IP_PARSER2_HVE_IN_BUS_BCM56370_A0fmt */ 32520 /* format IP_PARSER2_HVE_IN_BUSfmt */ 32521 /* nFields */ 7, 32522 /* *fields */ soc_IP_PARSER1_HVE_IN_BUSfmt_fields, 32523 /* bits */ 1452, 32524 /* flags */ 0, 32525 }, 32526 #endif /* chips */ 32527 32528 #if defined(BCM_56770_A0) 32529 { /* SOC_FORMAT_INT_IP_PARSER2_HVE_IN_BUS_BCM56770_A0fmt */ 32530 /* format IP_PARSER2_HVE_IN_BUSfmt */ 32531 /* nFields */ 7, 32532 /* *fields */ soc_IP_PARSER1_HVE_IN_BUSfmt_fields, 32533 /* bits */ 1452, 32534 /* flags */ 0, 32535 }, 32536 #endif /* chips */ 32537 32538 #if defined(BCM_56870_A0) 32539 { /* SOC_FORMAT_INT_IP_PARSER2_HVE_OUT_BUSfmt */ 32540 /* format IP_PARSER2_HVE_OUT_BUSfmt */ 32541 /* nFields */ 1, 32542 /* *fields */ soc_IP_PARSER0_HVE_OUT_BUSfmt_fields, 32543 /* bits */ 11, 32544 /* flags */ 0, 32545 }, 32546 #endif /* chips */ 32547 32548 #if defined(BCM_56370_A0) 32549 { /* SOC_FORMAT_INT_IP_PARSER2_HVE_OUT_BUS_BCM56370_A0fmt */ 32550 /* format IP_PARSER2_HVE_OUT_BUSfmt */ 32551 /* nFields */ 1, 32552 /* *fields */ soc_IP_PARSER0_HVE_OUT_BUSfmt_fields, 32553 /* bits */ 11, 32554 /* flags */ 0, 32555 }, 32556 #endif /* chips */ 32557 32558 #if defined(BCM_56770_A0) 32559 { /* SOC_FORMAT_INT_IP_PARSER2_HVE_OUT_BUS_BCM56770_A0fmt */ 32560 /* format IP_PARSER2_HVE_OUT_BUSfmt */ 32561 /* nFields */ 1, 32562 /* *fields */ soc_IP_PARSER0_HVE_OUT_BUSfmt_fields, 32563 /* bits */ 11, 32564 /* flags */ 0, 32565 }, 32566 #endif /* chips */ 32567 32568 #if defined(BCM_56870_A0) 32569 { /* SOC_FORMAT_INT_IP_PARSER2_HVE_RC_PROFILEfmt */ 32570 /* format IP_PARSER2_HVE_RC_PROFILEfmt */ 32571 /* nFields */ 2, 32572 /* *fields */ soc_IP_PARSER0_HVE_RC_PROFILEfmt_fields, 32573 /* bits */ 3, 32574 /* flags */ 0, 32575 }, 32576 #endif /* chips */ 32577 32578 #if defined(BCM_56370_A0) 32579 { /* SOC_FORMAT_INT_IP_PARSER2_HVE_RC_PROFILE_BCM56370_A0fmt */ 32580 /* format IP_PARSER2_HVE_RC_PROFILEfmt */ 32581 /* nFields */ 2, 32582 /* *fields */ soc_IP_PARSER0_HVE_RC_PROFILEfmt_fields, 32583 /* bits */ 3, 32584 /* flags */ 0, 32585 }, 32586 #endif /* chips */ 32587 32588 #if defined(BCM_56770_A0) 32589 { /* SOC_FORMAT_INT_IP_PARSER2_HVE_RC_PROFILE_BCM56770_A0fmt */ 32590 /* format IP_PARSER2_HVE_RC_PROFILEfmt */ 32591 /* nFields */ 2, 32592 /* *fields */ soc_IP_PARSER0_HVE_RC_PROFILEfmt_fields, 32593 /* bits */ 3, 32594 /* flags */ 0, 32595 }, 32596 #endif /* chips */ 32597 32598 #if defined(BCM_56870_A0) 32599 { /* SOC_FORMAT_INT_IP_PARSER2_HVE_SCC_PROFILEfmt */ 32600 /* format IP_PARSER2_HVE_SCC_PROFILEfmt */ 32601 /* nFields */ 2, 32602 /* *fields */ soc_IP_PARSER0_HVE_RC_PROFILEfmt_fields, 32603 /* bits */ 3, 32604 /* flags */ 0, 32605 }, 32606 #endif /* chips */ 32607 32608 #if defined(BCM_56370_A0) 32609 { /* SOC_FORMAT_INT_IP_PARSER2_HVE_SCC_PROFILE_BCM56370_A0fmt */ 32610 /* format IP_PARSER2_HVE_SCC_PROFILEfmt */ 32611 /* nFields */ 2, 32612 /* *fields */ soc_IP_PARSER0_HVE_RC_PROFILEfmt_fields, 32613 /* bits */ 3, 32614 /* flags */ 0, 32615 }, 32616 #endif /* chips */ 32617 32618 #if defined(BCM_56770_A0) 32619 { /* SOC_FORMAT_INT_IP_PARSER2_HVE_SCC_PROFILE_BCM56770_A0fmt */ 32620 /* format IP_PARSER2_HVE_SCC_PROFILEfmt */ 32621 /* nFields */ 2, 32622 /* *fields */ soc_IP_PARSER0_HVE_RC_PROFILEfmt_fields, 32623 /* bits */ 3, 32624 /* flags */ 0, 32625 }, 32626 #endif /* chips */ 32627 32628 #if defined(BCM_56870_A0) 32629 { /* SOC_FORMAT_INT_IP_PARSER2_HVE_SCF_PROFILEfmt */ 32630 /* format IP_PARSER2_HVE_SCF_PROFILEfmt */ 32631 /* nFields */ 2, 32632 /* *fields */ soc_IP_PARSER0_HVE_RC_PROFILEfmt_fields, 32633 /* bits */ 3, 32634 /* flags */ 0, 32635 }, 32636 #endif /* chips */ 32637 32638 #if defined(BCM_56370_A0) 32639 { /* SOC_FORMAT_INT_IP_PARSER2_HVE_SCF_PROFILE_BCM56370_A0fmt */ 32640 /* format IP_PARSER2_HVE_SCF_PROFILEfmt */ 32641 /* nFields */ 2, 32642 /* *fields */ soc_IP_PARSER0_HVE_RC_PROFILEfmt_fields, 32643 /* bits */ 3, 32644 /* flags */ 0, 32645 }, 32646 #endif /* chips */ 32647 32648 #if defined(BCM_56770_A0) 32649 { /* SOC_FORMAT_INT_IP_PARSER2_HVE_SCF_PROFILE_BCM56770_A0fmt */ 32650 /* format IP_PARSER2_HVE_SCF_PROFILEfmt */ 32651 /* nFields */ 2, 32652 /* *fields */ soc_IP_PARSER0_HVE_RC_PROFILEfmt_fields, 32653 /* bits */ 3, 32654 /* flags */ 0, 32655 }, 32656 #endif /* chips */ 32657 32658 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 32659 defined(BCM_56870_A0) 32660 { /* SOC_FORMAT_INT_IP_PARSER2_IN_BUSfmt */ 32661 /* format IP_PARSER2_IN_BUSfmt */ 32662 /* nFields */ 13, 32663 /* *fields */ soc_IP_PARSER2_IN_BUSfmt_fields, 32664 /* bits */ 1277, 32665 /* flags */ 0, 32666 }, 32667 #endif /* chips */ 32668 32669 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 32670 defined(BCM_56870_A0) 32671 { /* SOC_FORMAT_INT_IP_PARSER2_MICE_IN_BUSfmt */ 32672 /* format IP_PARSER2_MICE_IN_BUSfmt */ 32673 /* nFields */ 5, 32674 /* *fields */ soc_IP_PARSER2_MICE_IN_BUSfmt_fields, 32675 /* bits */ 110, 32676 /* flags */ 0, 32677 }, 32678 #endif /* chips */ 32679 32680 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 32681 defined(BCM_56870_A0) 32682 { /* SOC_FORMAT_INT_IP_PARSER2_MICE_OUT_BUSfmt */ 32683 /* format IP_PARSER2_MICE_OUT_BUSfmt */ 32684 /* nFields */ 6, 32685 /* *fields */ soc_IP_PARSER2_MICE_OUT_BUSfmt_fields, 32686 /* bits */ 115, 32687 /* flags */ 0, 32688 }, 32689 #endif /* chips */ 32690 32691 #if defined(BCM_56870_A0) 32692 { /* SOC_FORMAT_INT_IP_PARSER2_MICE_TCAM_DATAfmt */ 32693 /* format IP_PARSER2_MICE_TCAM_DATAfmt */ 32694 /* nFields */ 9, 32695 /* *fields */ soc_IP_PARSER1_MICE_TCAM_DATAfmt_fields, 32696 /* bits */ 102, 32697 /* flags */ 0, 32698 }, 32699 #endif /* chips */ 32700 32701 #if defined(BCM_56370_A0) 32702 { /* SOC_FORMAT_INT_IP_PARSER2_MICE_TCAM_DATA_BCM56370_A0fmt */ 32703 /* format IP_PARSER2_MICE_TCAM_DATAfmt */ 32704 /* nFields */ 9, 32705 /* *fields */ soc_IP_PARSER1_MICE_TCAM_DATAfmt_fields, 32706 /* bits */ 102, 32707 /* flags */ 0, 32708 }, 32709 #endif /* chips */ 32710 32711 #if defined(BCM_56770_A0) 32712 { /* SOC_FORMAT_INT_IP_PARSER2_MICE_TCAM_DATA_BCM56770_A0fmt */ 32713 /* format IP_PARSER2_MICE_TCAM_DATAfmt */ 32714 /* nFields */ 9, 32715 /* *fields */ soc_IP_PARSER1_MICE_TCAM_DATAfmt_fields, 32716 /* bits */ 102, 32717 /* flags */ 0, 32718 }, 32719 #endif /* chips */ 32720 32721 #if defined(BCM_56870_A0) 32722 { /* SOC_FORMAT_INT_IP_PARSER2_MICE_TCAM_KEYfmt */ 32723 /* format IP_PARSER2_MICE_TCAM_KEYfmt */ 32724 /* nFields */ 3, 32725 /* *fields */ soc_IP_PARSER1_MICE_TCAM_KEYfmt_fields, 32726 /* bits */ 64, 32727 /* flags */ 0, 32728 }, 32729 #endif /* chips */ 32730 32731 #if defined(BCM_56370_A0) 32732 { /* SOC_FORMAT_INT_IP_PARSER2_MICE_TCAM_KEY_BCM56370_A0fmt */ 32733 /* format IP_PARSER2_MICE_TCAM_KEYfmt */ 32734 /* nFields */ 3, 32735 /* *fields */ soc_IP_PARSER1_MICE_TCAM_KEYfmt_fields, 32736 /* bits */ 64, 32737 /* flags */ 0, 32738 }, 32739 #endif /* chips */ 32740 32741 #if defined(BCM_56770_A0) 32742 { /* SOC_FORMAT_INT_IP_PARSER2_MICE_TCAM_KEY_BCM56770_A0fmt */ 32743 /* format IP_PARSER2_MICE_TCAM_KEYfmt */ 32744 /* nFields */ 3, 32745 /* *fields */ soc_IP_PARSER1_MICE_TCAM_KEYfmt_fields, 32746 /* bits */ 64, 32747 /* flags */ 0, 32748 }, 32749 #endif /* chips */ 32750 32751 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 32752 defined(BCM_56870_A0) 32753 { /* SOC_FORMAT_INT_IP_PARSER2_OUT_BUSfmt */ 32754 /* format IP_PARSER2_OUT_BUSfmt */ 32755 /* nFields */ 15, 32756 /* *fields */ soc_IP_PARSER2_OUT_BUSfmt_fields, 32757 /* bits */ 2704, 32758 /* flags */ 0, 32759 }, 32760 #endif /* chips */ 32761 32762 #if defined(BCM_56870_A0) 32763 { /* SOC_FORMAT_INT_IP_PARSER2_TOP_HME_OUT_BUSfmt */ 32764 /* format IP_PARSER2_TOP_HME_OUT_BUSfmt */ 32765 /* nFields */ 5, 32766 /* *fields */ soc_IP_PARSER0_TOP_HME_OUT_BUSfmt_fields, 32767 /* bits */ 51, 32768 /* flags */ 0, 32769 }, 32770 #endif /* chips */ 32771 32772 #if defined(BCM_56370_A0) 32773 { /* SOC_FORMAT_INT_IP_PARSER2_TOP_HME_OUT_BUS_BCM56370_A0fmt */ 32774 /* format IP_PARSER2_TOP_HME_OUT_BUSfmt */ 32775 /* nFields */ 5, 32776 /* *fields */ soc_IP_PARSER0_TOP_HME_OUT_BUSfmt_fields, 32777 /* bits */ 51, 32778 /* flags */ 0, 32779 }, 32780 #endif /* chips */ 32781 32782 #if defined(BCM_56770_A0) 32783 { /* SOC_FORMAT_INT_IP_PARSER2_TOP_HME_OUT_BUS_BCM56770_A0fmt */ 32784 /* format IP_PARSER2_TOP_HME_OUT_BUSfmt */ 32785 /* nFields */ 5, 32786 /* *fields */ soc_IP_PARSER0_TOP_HME_OUT_BUSfmt_fields, 32787 /* bits */ 51, 32788 /* flags */ 0, 32789 }, 32790 #endif /* chips */ 32791 32792 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 32793 defined(BCM_56870_A0) 32794 { /* SOC_FORMAT_INT_IP_PARSER_0_HME_STAGE_TCAM_DOPfmt */ 32795 /* format IP_PARSER_0_HME_STAGE_TCAM_DOPfmt */ 32796 /* nFields */ 3, 32797 /* *fields */ soc_IP_PARSER_0_HME_STAGE_TCAM_DOPfmt_fields, 32798 /* bits */ 32, 32799 /* flags */ 0, 32800 }, 32801 #endif /* chips */ 32802 32803 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \ 32804 defined(BCM_56450_A0) || defined(BCM_56450_B0) || \ 32805 defined(BCM_56450_B1) || defined(BCM_56640_A0) || \ 32806 defined(BCM_56850_A0) || defined(BCM_56860_A0) 32807 { /* SOC_FORMAT_INT_IP_PROTOCOLfmt */ 32808 /* format IP_PROTOCOLfmt */ 32809 /* nFields */ 1, 32810 /* *fields */ soc_IP_PROTOCOLfmt_fields, 32811 /* bits */ 8, 32812 /* flags */ 0, 32813 }, 32814 #endif /* chips */ 32815 32816 #if defined(BCM_53400_A0) 32817 { /* SOC_FORMAT_INT_IP_PROTOCOL_BCM53400_A0fmt */ 32818 /* format IP_PROTOCOLfmt */ 32819 /* nFields */ 1, 32820 /* *fields */ soc_IP_PROTOCOL_BCM53400_A0fmt_fields, 32821 /* bits */ 8, 32822 /* flags */ 0, 32823 }, 32824 #endif /* chips */ 32825 32826 #if defined(BCM_53540_A0) 32827 { /* SOC_FORMAT_INT_IP_PROTOCOL_BCM53540_A0fmt */ 32828 /* format IP_PROTOCOLfmt */ 32829 /* nFields */ 1, 32830 /* *fields */ soc_IP_PROTOCOL_BCM53400_A0fmt_fields, 32831 /* bits */ 8, 32832 /* flags */ 0, 32833 }, 32834 #endif /* chips */ 32835 32836 #if defined(BCM_53570_A0) 32837 { /* SOC_FORMAT_INT_IP_PROTOCOL_BCM53570_A0fmt */ 32838 /* format IP_PROTOCOLfmt */ 32839 /* nFields */ 1, 32840 /* *fields */ soc_IP_PROTOCOL_BCM53400_A0fmt_fields, 32841 /* bits */ 8, 32842 /* flags */ 0, 32843 }, 32844 #endif /* chips */ 32845 32846 #if defined(BCM_53570_B0) 32847 { /* SOC_FORMAT_INT_IP_PROTOCOL_BCM53570_B0fmt */ 32848 /* format IP_PROTOCOLfmt */ 32849 /* nFields */ 1, 32850 /* *fields */ soc_IP_PROTOCOL_BCM53400_A0fmt_fields, 32851 /* bits */ 8, 32852 /* flags */ 0, 32853 }, 32854 #endif /* chips */ 32855 32856 #if defined(BCM_56160_A0) 32857 { /* SOC_FORMAT_INT_IP_PROTOCOL_BCM56160_A0fmt */ 32858 /* format IP_PROTOCOLfmt */ 32859 /* nFields */ 1, 32860 /* *fields */ soc_IP_PROTOCOL_BCM53400_A0fmt_fields, 32861 /* bits */ 8, 32862 /* flags */ 0, 32863 }, 32864 #endif /* chips */ 32865 32866 #if defined(BCM_56260_A0) 32867 { /* SOC_FORMAT_INT_IP_PROTOCOL_BCM56260_A0fmt */ 32868 /* format IP_PROTOCOLfmt */ 32869 /* nFields */ 1, 32870 /* *fields */ soc_IP_PROTOCOL_BCM53400_A0fmt_fields, 32871 /* bits */ 8, 32872 /* flags */ 0, 32873 }, 32874 #endif /* chips */ 32875 32876 #if defined(BCM_56260_B0) 32877 { /* SOC_FORMAT_INT_IP_PROTOCOL_BCM56260_B0fmt */ 32878 /* format IP_PROTOCOLfmt */ 32879 /* nFields */ 1, 32880 /* *fields */ soc_IP_PROTOCOL_BCM53400_A0fmt_fields, 32881 /* bits */ 8, 32882 /* flags */ 0, 32883 }, 32884 #endif /* chips */ 32885 32886 #if defined(BCM_56270_A0) 32887 { /* SOC_FORMAT_INT_IP_PROTOCOL_BCM56270_A0fmt */ 32888 /* format IP_PROTOCOLfmt */ 32889 /* nFields */ 1, 32890 /* *fields */ soc_IP_PROTOCOL_BCM53400_A0fmt_fields, 32891 /* bits */ 8, 32892 /* flags */ 0, 32893 }, 32894 #endif /* chips */ 32895 32896 #if defined(BCM_56370_A0) 32897 { /* SOC_FORMAT_INT_IP_PROTOCOL_BCM56370_A0fmt */ 32898 /* format IP_PROTOCOLfmt */ 32899 /* nFields */ 1, 32900 /* *fields */ soc_IP_PROTOCOL_BCM53400_A0fmt_fields, 32901 /* bits */ 8, 32902 /* flags */ 0, 32903 }, 32904 #endif /* chips */ 32905 32906 #if defined(BCM_56560_A0) 32907 { /* SOC_FORMAT_INT_IP_PROTOCOL_BCM56560_A0fmt */ 32908 /* format IP_PROTOCOLfmt */ 32909 /* nFields */ 1, 32910 /* *fields */ soc_IP_PROTOCOL_BCM53400_A0fmt_fields, 32911 /* bits */ 8, 32912 /* flags */ 0, 32913 }, 32914 #endif /* chips */ 32915 32916 #if defined(BCM_56560_B0) 32917 { /* SOC_FORMAT_INT_IP_PROTOCOL_BCM56560_B0fmt */ 32918 /* format IP_PROTOCOLfmt */ 32919 /* nFields */ 1, 32920 /* *fields */ soc_IP_PROTOCOL_BCM53400_A0fmt_fields, 32921 /* bits */ 8, 32922 /* flags */ 0, 32923 }, 32924 #endif /* chips */ 32925 32926 #if defined(BCM_56670_A0) 32927 { /* SOC_FORMAT_INT_IP_PROTOCOL_BCM56670_A0fmt */ 32928 /* format IP_PROTOCOLfmt */ 32929 /* nFields */ 1, 32930 /* *fields */ soc_IP_PROTOCOL_BCM53400_A0fmt_fields, 32931 /* bits */ 8, 32932 /* flags */ 0, 32933 }, 32934 #endif /* chips */ 32935 32936 #if defined(BCM_56670_B0) 32937 { /* SOC_FORMAT_INT_IP_PROTOCOL_BCM56670_B0fmt */ 32938 /* format IP_PROTOCOLfmt */ 32939 /* nFields */ 1, 32940 /* *fields */ soc_IP_PROTOCOL_BCM53400_A0fmt_fields, 32941 /* bits */ 8, 32942 /* flags */ 0, 32943 }, 32944 #endif /* chips */ 32945 32946 #if defined(BCM_56770_A0) 32947 { /* SOC_FORMAT_INT_IP_PROTOCOL_BCM56770_A0fmt */ 32948 /* format IP_PROTOCOLfmt */ 32949 /* nFields */ 1, 32950 /* *fields */ soc_IP_PROTOCOL_BCM53400_A0fmt_fields, 32951 /* bits */ 8, 32952 /* flags */ 0, 32953 }, 32954 #endif /* chips */ 32955 32956 #if defined(BCM_56870_A0) 32957 { /* SOC_FORMAT_INT_IP_PROTOCOL_BCM56870_A0fmt */ 32958 /* format IP_PROTOCOLfmt */ 32959 /* nFields */ 1, 32960 /* *fields */ soc_IP_PROTOCOL_BCM53400_A0fmt_fields, 32961 /* bits */ 8, 32962 /* flags */ 0, 32963 }, 32964 #endif /* chips */ 32965 32966 #if defined(BCM_56960_A0) 32967 { /* SOC_FORMAT_INT_IP_PROTOCOL_BCM56960_A0fmt */ 32968 /* format IP_PROTOCOLfmt */ 32969 /* nFields */ 1, 32970 /* *fields */ soc_IP_PROTOCOL_BCM53400_A0fmt_fields, 32971 /* bits */ 8, 32972 /* flags */ 0, 32973 }, 32974 #endif /* chips */ 32975 32976 #if defined(BCM_56965_A0) 32977 { /* SOC_FORMAT_INT_IP_PROTOCOL_BCM56965_A0fmt */ 32978 /* format IP_PROTOCOLfmt */ 32979 /* nFields */ 1, 32980 /* *fields */ soc_IP_PROTOCOL_BCM53400_A0fmt_fields, 32981 /* bits */ 8, 32982 /* flags */ 0, 32983 }, 32984 #endif /* chips */ 32985 32986 #if defined(BCM_56970_A0) 32987 { /* SOC_FORMAT_INT_IP_PROTOCOL_BCM56970_A0fmt */ 32988 /* format IP_PROTOCOLfmt */ 32989 /* nFields */ 1, 32990 /* *fields */ soc_IP_PROTOCOL_BCM53400_A0fmt_fields, 32991 /* bits */ 8, 32992 /* flags */ 0, 32993 }, 32994 #endif /* chips */ 32995 32996 #if defined(BCM_56980_A0) 32997 { /* SOC_FORMAT_INT_IP_PROTOCOL_BCM56980_A0fmt */ 32998 /* format IP_PROTOCOLfmt */ 32999 /* nFields */ 1, 33000 /* *fields */ soc_IP_PROTOCOL_BCM53400_A0fmt_fields, 33001 /* bits */ 8, 33002 /* flags */ 0, 33003 }, 33004 #endif /* chips */ 33005 33006 #if defined(BCM_56980_B0) 33007 { /* SOC_FORMAT_INT_IP_PROTOCOL_BCM56980_B0fmt */ 33008 /* format IP_PROTOCOLfmt */ 33009 /* nFields */ 1, 33010 /* *fields */ soc_IP_PROTOCOL_BCM53400_A0fmt_fields, 33011 /* bits */ 8, 33012 /* flags */ 0, 33013 }, 33014 #endif /* chips */ 33015 33016 #if defined(BCM_56970_A0) 33017 { /* SOC_FORMAT_INT_IP_SBUS_META_DATAfmt */ 33018 /* format IP_SBUS_META_DATAfmt */ 33019 /* nFields */ 7, 33020 /* *fields */ soc_IP_SBUS_META_DATAfmt_fields, 33021 /* bits */ 528, 33022 /* flags */ 0, 33023 }, 33024 #endif /* chips */ 33025 33026 #if defined(BCM_56370_A0) 33027 { /* SOC_FORMAT_INT_IP_SBUS_META_DATA_BCM56370_A0fmt */ 33028 /* format IP_SBUS_META_DATAfmt */ 33029 /* nFields */ 7, 33030 /* *fields */ soc_IP_SBUS_META_DATA_BCM56870_A0fmt_fields, 33031 /* bits */ 656, 33032 /* flags */ 0, 33033 }, 33034 #endif /* chips */ 33035 33036 #if defined(BCM_56770_A0) 33037 { /* SOC_FORMAT_INT_IP_SBUS_META_DATA_BCM56770_A0fmt */ 33038 /* format IP_SBUS_META_DATAfmt */ 33039 /* nFields */ 7, 33040 /* *fields */ soc_IP_SBUS_META_DATA_BCM56870_A0fmt_fields, 33041 /* bits */ 656, 33042 /* flags */ 0, 33043 }, 33044 #endif /* chips */ 33045 33046 #if defined(BCM_56870_A0) 33047 { /* SOC_FORMAT_INT_IP_SBUS_META_DATA_BCM56870_A0fmt */ 33048 /* format IP_SBUS_META_DATAfmt */ 33049 /* nFields */ 7, 33050 /* *fields */ soc_IP_SBUS_META_DATA_BCM56870_A0fmt_fields, 33051 /* bits */ 656, 33052 /* flags */ 0, 33053 }, 33054 #endif /* chips */ 33055 33056 #if defined(BCM_56980_A0) 33057 { /* SOC_FORMAT_INT_IP_SBUS_META_DATA_BCM56980_A0fmt */ 33058 /* format IP_SBUS_META_DATAfmt */ 33059 /* nFields */ 8, 33060 /* *fields */ soc_IP_SBUS_META_DATA_BCM56980_A0fmt_fields, 33061 /* bits */ 688, 33062 /* flags */ 0, 33063 }, 33064 #endif /* chips */ 33065 33066 #if defined(BCM_56980_B0) 33067 { /* SOC_FORMAT_INT_IP_SBUS_META_DATA_BCM56980_B0fmt */ 33068 /* format IP_SBUS_META_DATAfmt */ 33069 /* nFields */ 8, 33070 /* *fields */ soc_IP_SBUS_META_DATA_BCM56980_A0fmt_fields, 33071 /* bits */ 688, 33072 /* flags */ 0, 33073 }, 33074 #endif /* chips */ 33075 33076 #if defined(BCM_56624_B0) || defined(BCM_56680_B0) 33077 { /* SOC_FORMAT_INT_IQ_BUSfmt */ 33078 /* format IQ_BUSfmt */ 33079 /* nFields */ 3, 33080 /* *fields */ soc_IQ_BUSfmt_fields, 33081 /* bits */ 32, 33082 /* flags */ 0, 33083 }, 33084 #endif /* chips */ 33085 33086 #if defined(BCM_53400_A0) 33087 { /* SOC_FORMAT_INT_IQ_BUS_BCM53400_A0fmt */ 33088 /* format IQ_BUSfmt */ 33089 /* nFields */ 1, 33090 /* *fields */ soc_IQ_BUS_BCM53400_A0fmt_fields, 33091 /* bits */ 32, 33092 /* flags */ 0, 33093 }, 33094 #endif /* chips */ 33095 33096 #if defined(BCM_53540_A0) 33097 { /* SOC_FORMAT_INT_IQ_BUS_BCM53540_A0fmt */ 33098 /* format IQ_BUSfmt */ 33099 /* nFields */ 1, 33100 /* *fields */ soc_IQ_BUS_BCM53400_A0fmt_fields, 33101 /* bits */ 32, 33102 /* flags */ 0, 33103 }, 33104 #endif /* chips */ 33105 33106 #if defined(BCM_53570_A0) 33107 { /* SOC_FORMAT_INT_IQ_BUS_BCM53570_A0fmt */ 33108 /* format IQ_BUSfmt */ 33109 /* nFields */ 1, 33110 /* *fields */ soc_IQ_BUS_BCM53400_A0fmt_fields, 33111 /* bits */ 32, 33112 /* flags */ 0, 33113 }, 33114 #endif /* chips */ 33115 33116 #if defined(BCM_53570_B0) 33117 { /* SOC_FORMAT_INT_IQ_BUS_BCM53570_B0fmt */ 33118 /* format IQ_BUSfmt */ 33119 /* nFields */ 1, 33120 /* *fields */ soc_IQ_BUS_BCM53400_A0fmt_fields, 33121 /* bits */ 32, 33122 /* flags */ 0, 33123 }, 33124 #endif /* chips */ 33125 33126 #if defined(BCM_56142_A0) 33127 { /* SOC_FORMAT_INT_IQ_BUS_BCM56142_A0fmt */ 33128 /* format IQ_BUSfmt */ 33129 /* nFields */ 1, 33130 /* *fields */ soc_IQ_BUS_BCM56142_A0fmt_fields, 33131 /* bits */ 32, 33132 /* flags */ 0, 33133 }, 33134 #endif /* chips */ 33135 33136 #if defined(BCM_56150_A0) 33137 { /* SOC_FORMAT_INT_IQ_BUS_BCM56150_A0fmt */ 33138 /* format IQ_BUSfmt */ 33139 /* nFields */ 1, 33140 /* *fields */ soc_IQ_BUS_BCM56150_A0fmt_fields, 33141 /* bits */ 32, 33142 /* flags */ 0, 33143 }, 33144 #endif /* chips */ 33145 33146 #if defined(BCM_56160_A0) 33147 { /* SOC_FORMAT_INT_IQ_BUS_BCM56160_A0fmt */ 33148 /* format IQ_BUSfmt */ 33149 /* nFields */ 1, 33150 /* *fields */ soc_IQ_BUS_BCM53400_A0fmt_fields, 33151 /* bits */ 32, 33152 /* flags */ 0, 33153 }, 33154 #endif /* chips */ 33155 33156 #if defined(BCM_56334_A0) 33157 { /* SOC_FORMAT_INT_IQ_BUS_BCM56334_A0fmt */ 33158 /* format IQ_BUSfmt */ 33159 /* nFields */ 3, 33160 /* *fields */ soc_IQ_BUSfmt_fields, 33161 /* bits */ 32, 33162 /* flags */ 0, 33163 }, 33164 #endif /* chips */ 33165 33166 #if defined(BCM_56334_B0) 33167 { /* SOC_FORMAT_INT_IQ_BUS_BCM56334_B0fmt */ 33168 /* format IQ_BUSfmt */ 33169 /* nFields */ 5, 33170 /* *fields */ soc_IQ_BUS_BCM56334_B0fmt_fields, 33171 /* bits */ 32, 33172 /* flags */ 0, 33173 }, 33174 #endif /* chips */ 33175 33176 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) 33177 { /* SOC_FORMAT_INT_IRSEL1_DOPfmt */ 33178 /* format IRSEL1_DOPfmt */ 33179 /* nFields */ 66, 33180 /* *fields */ soc_IRSEL1_DOPfmt_fields, 33181 /* bits */ 896, 33182 /* flags */ 0, 33183 }, 33184 #endif /* chips */ 33185 33186 #if defined(BCM_56370_A0) 33187 { /* SOC_FORMAT_INT_IRSEL1_DOP_BCM56370_A0fmt */ 33188 /* format IRSEL1_DOPfmt */ 33189 /* nFields */ 66, 33190 /* *fields */ soc_IRSEL1_DOP_BCM56370_A0fmt_fields, 33191 /* bits */ 992, 33192 /* flags */ 0, 33193 }, 33194 #endif /* chips */ 33195 33196 #if defined(BCM_56370_A0) 33197 { /* SOC_FORMAT_INT_IRSEL1_TO_L2_MGMT_L2_BUSfmt */ 33198 /* format IRSEL1_TO_L2_MGMT_L2_BUSfmt */ 33199 /* nFields */ 6, 33200 /* *fields */ soc_ISW1_TO_L2_MGMT_L2_BUS_BCM56870_A0fmt_fields, 33201 /* bits */ 119, 33202 /* flags */ 0, 33203 }, 33204 #endif /* chips */ 33205 33206 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 33207 defined(BCM_56870_A0) 33208 { /* SOC_FORMAT_INT_IRSEL2_DOPfmt */ 33209 /* format IRSEL2_DOPfmt */ 33210 /* nFields */ 66, 33211 /* *fields */ soc_IRSEL2_DOPfmt_fields, 33212 /* bits */ 800, 33213 /* flags */ 0, 33214 }, 33215 #endif /* chips */ 33216 33217 #if defined(BCM_56970_A0) || defined(BCM_56980_A0) || \ 33218 defined(BCM_56980_B0) 33219 { /* SOC_FORMAT_INT_IRSEL2_NHOP_COMMON_COV_DEFSfmt */ 33220 /* format IRSEL2_NHOP_COMMON_COV_DEFSfmt */ 33221 /* nFields */ 8, 33222 /* *fields */ soc_IRSEL2_NHOP_COMMON_COV_DEFSfmt_fields, 33223 /* bits */ 39, 33224 /* flags */ 0, 33225 }, 33226 #endif /* chips */ 33227 33228 #if defined(BCM_56340_A0) || defined(BCM_56640_A0) || \ 33229 defined(BCM_56850_A0) || defined(BCM_56860_A0) 33230 { /* SOC_FORMAT_INT_ISC_HG_STATS_COV_DEFSfmt */ 33231 /* format ISC_HG_STATS_COV_DEFSfmt */ 33232 /* nFields */ 6, 33233 /* *fields */ soc_ISC_HG_STATS_COV_DEFSfmt_fields, 33234 /* bits */ 16, 33235 /* flags */ 0, 33236 }, 33237 #endif /* chips */ 33238 33239 #if defined(BCM_53400_A0) 33240 { /* SOC_FORMAT_INT_ISC_HG_STATS_COV_DEFS_BCM53400_A0fmt */ 33241 /* format ISC_HG_STATS_COV_DEFSfmt */ 33242 /* nFields */ 6, 33243 /* *fields */ soc_ISC_HG_STATS_COV_DEFS_BCM53400_A0fmt_fields, 33244 /* bits */ 11, 33245 /* flags */ 0, 33246 }, 33247 #endif /* chips */ 33248 33249 #if defined(BCM_53540_A0) 33250 { /* SOC_FORMAT_INT_ISC_HG_STATS_COV_DEFS_BCM53540_A0fmt */ 33251 /* format ISC_HG_STATS_COV_DEFSfmt */ 33252 /* nFields */ 6, 33253 /* *fields */ soc_ISC_HG_STATS_COV_DEFS_BCM53400_A0fmt_fields, 33254 /* bits */ 11, 33255 /* flags */ 0, 33256 }, 33257 #endif /* chips */ 33258 33259 #if defined(BCM_53570_A0) 33260 { /* SOC_FORMAT_INT_ISC_HG_STATS_COV_DEFS_BCM53570_A0fmt */ 33261 /* format ISC_HG_STATS_COV_DEFSfmt */ 33262 /* nFields */ 6, 33263 /* *fields */ soc_ISC_HG_STATS_COV_DEFS_BCM53400_A0fmt_fields, 33264 /* bits */ 11, 33265 /* flags */ 0, 33266 }, 33267 #endif /* chips */ 33268 33269 #if defined(BCM_53570_B0) 33270 { /* SOC_FORMAT_INT_ISC_HG_STATS_COV_DEFS_BCM53570_B0fmt */ 33271 /* format ISC_HG_STATS_COV_DEFSfmt */ 33272 /* nFields */ 6, 33273 /* *fields */ soc_ISC_HG_STATS_COV_DEFS_BCM53400_A0fmt_fields, 33274 /* bits */ 11, 33275 /* flags */ 0, 33276 }, 33277 #endif /* chips */ 33278 33279 #if defined(BCM_56150_A0) 33280 { /* SOC_FORMAT_INT_ISC_HG_STATS_COV_DEFS_BCM56150_A0fmt */ 33281 /* format ISC_HG_STATS_COV_DEFSfmt */ 33282 /* nFields */ 6, 33283 /* *fields */ soc_ISC_HG_STATS_COV_DEFS_BCM56150_A0fmt_fields, 33284 /* bits */ 11, 33285 /* flags */ 0, 33286 }, 33287 #endif /* chips */ 33288 33289 #if defined(BCM_56160_A0) 33290 { /* SOC_FORMAT_INT_ISC_HG_STATS_COV_DEFS_BCM56160_A0fmt */ 33291 /* format ISC_HG_STATS_COV_DEFSfmt */ 33292 /* nFields */ 6, 33293 /* *fields */ soc_ISC_HG_STATS_COV_DEFS_BCM53400_A0fmt_fields, 33294 /* bits */ 11, 33295 /* flags */ 0, 33296 }, 33297 #endif /* chips */ 33298 33299 #if defined(BCM_56370_A0) 33300 { /* SOC_FORMAT_INT_ISC_HG_STATS_COV_DEFS_BCM56370_A0fmt */ 33301 /* format ISC_HG_STATS_COV_DEFSfmt */ 33302 /* nFields */ 6, 33303 /* *fields */ soc_EFP_COUNTER_TABLE_COV_DEFS_BCM53400_A0fmt_fields, 33304 /* bits */ 15, 33305 /* flags */ 0, 33306 }, 33307 #endif /* chips */ 33308 33309 #if defined(BCM_56560_A0) 33310 { /* SOC_FORMAT_INT_ISC_HG_STATS_COV_DEFS_BCM56560_A0fmt */ 33311 /* format ISC_HG_STATS_COV_DEFSfmt */ 33312 /* nFields */ 6, 33313 /* *fields */ soc_ISC_HG_STATS_COV_DEFS_BCM56560_A0fmt_fields, 33314 /* bits */ 16, 33315 /* flags */ 0, 33316 }, 33317 #endif /* chips */ 33318 33319 #if defined(BCM_56560_B0) 33320 { /* SOC_FORMAT_INT_ISC_HG_STATS_COV_DEFS_BCM56560_B0fmt */ 33321 /* format ISC_HG_STATS_COV_DEFSfmt */ 33322 /* nFields */ 6, 33323 /* *fields */ soc_ISC_HG_STATS_COV_DEFS_BCM56560_A0fmt_fields, 33324 /* bits */ 16, 33325 /* flags */ 0, 33326 }, 33327 #endif /* chips */ 33328 33329 #if defined(BCM_56670_A0) 33330 { /* SOC_FORMAT_INT_ISC_HG_STATS_COV_DEFS_BCM56670_A0fmt */ 33331 /* format ISC_HG_STATS_COV_DEFSfmt */ 33332 /* nFields */ 6, 33333 /* *fields */ soc_ISC_HG_STATS_COV_DEFS_BCM56560_A0fmt_fields, 33334 /* bits */ 16, 33335 /* flags */ 0, 33336 }, 33337 #endif /* chips */ 33338 33339 #if defined(BCM_56670_B0) 33340 { /* SOC_FORMAT_INT_ISC_HG_STATS_COV_DEFS_BCM56670_B0fmt */ 33341 /* format ISC_HG_STATS_COV_DEFSfmt */ 33342 /* nFields */ 6, 33343 /* *fields */ soc_ISC_HG_STATS_COV_DEFS_BCM56560_A0fmt_fields, 33344 /* bits */ 16, 33345 /* flags */ 0, 33346 }, 33347 #endif /* chips */ 33348 33349 #if defined(BCM_56770_A0) 33350 { /* SOC_FORMAT_INT_ISC_HG_STATS_COV_DEFS_BCM56770_A0fmt */ 33351 /* format ISC_HG_STATS_COV_DEFSfmt */ 33352 /* nFields */ 6, 33353 /* *fields */ soc_EFP_COUNTER_TABLE_COV_DEFS_BCM53400_A0fmt_fields, 33354 /* bits */ 15, 33355 /* flags */ 0, 33356 }, 33357 #endif /* chips */ 33358 33359 #if defined(BCM_56870_A0) 33360 { /* SOC_FORMAT_INT_ISC_HG_STATS_COV_DEFS_BCM56870_A0fmt */ 33361 /* format ISC_HG_STATS_COV_DEFSfmt */ 33362 /* nFields */ 6, 33363 /* *fields */ soc_EFP_COUNTER_TABLE_COV_DEFS_BCM53400_A0fmt_fields, 33364 /* bits */ 15, 33365 /* flags */ 0, 33366 }, 33367 #endif /* chips */ 33368 33369 #if defined(BCM_56960_A0) 33370 { /* SOC_FORMAT_INT_ISC_HG_STATS_COV_DEFS_BCM56960_A0fmt */ 33371 /* format ISC_HG_STATS_COV_DEFSfmt */ 33372 /* nFields */ 6, 33373 /* *fields */ soc_ISC_HG_STATS_COV_DEFS_BCM56960_A0fmt_fields, 33374 /* bits */ 15, 33375 /* flags */ 0, 33376 }, 33377 #endif /* chips */ 33378 33379 #if defined(BCM_56965_A0) 33380 { /* SOC_FORMAT_INT_ISC_HG_STATS_COV_DEFS_BCM56965_A0fmt */ 33381 /* format ISC_HG_STATS_COV_DEFSfmt */ 33382 /* nFields */ 6, 33383 /* *fields */ soc_ISC_HG_STATS_COV_DEFS_BCM56960_A0fmt_fields, 33384 /* bits */ 15, 33385 /* flags */ 0, 33386 }, 33387 #endif /* chips */ 33388 33389 #if defined(BCM_56970_A0) 33390 { /* SOC_FORMAT_INT_ISC_HG_STATS_COV_DEFS_BCM56970_A0fmt */ 33391 /* format ISC_HG_STATS_COV_DEFSfmt */ 33392 /* nFields */ 6, 33393 /* *fields */ soc_ISC_HG_STATS_COV_DEFS_BCM56960_A0fmt_fields, 33394 /* bits */ 15, 33395 /* flags */ 0, 33396 }, 33397 #endif /* chips */ 33398 33399 #if defined(BCM_56340_A0) || defined(BCM_56640_A0) 33400 { /* SOC_FORMAT_INT_ISC_IP_STATS_COV_DEFSfmt */ 33401 /* format ISC_IP_STATS_COV_DEFSfmt */ 33402 /* nFields */ 6, 33403 /* *fields */ soc_ISC_IP_STATS_COV_DEFSfmt_fields, 33404 /* bits */ 14, 33405 /* flags */ 0, 33406 }, 33407 #endif /* chips */ 33408 33409 #if defined(BCM_53400_A0) 33410 { /* SOC_FORMAT_INT_ISC_IP_STATS_COV_DEFS_BCM53400_A0fmt */ 33411 /* format ISC_IP_STATS_COV_DEFSfmt */ 33412 /* nFields */ 6, 33413 /* *fields */ soc_ISC_HG_STATS_COV_DEFS_BCM53400_A0fmt_fields, 33414 /* bits */ 11, 33415 /* flags */ 0, 33416 }, 33417 #endif /* chips */ 33418 33419 #if defined(BCM_53540_A0) 33420 { /* SOC_FORMAT_INT_ISC_IP_STATS_COV_DEFS_BCM53540_A0fmt */ 33421 /* format ISC_IP_STATS_COV_DEFSfmt */ 33422 /* nFields */ 6, 33423 /* *fields */ soc_ISC_HG_STATS_COV_DEFS_BCM53400_A0fmt_fields, 33424 /* bits */ 11, 33425 /* flags */ 0, 33426 }, 33427 #endif /* chips */ 33428 33429 #if defined(BCM_53570_A0) 33430 { /* SOC_FORMAT_INT_ISC_IP_STATS_COV_DEFS_BCM53570_A0fmt */ 33431 /* format ISC_IP_STATS_COV_DEFSfmt */ 33432 /* nFields */ 6, 33433 /* *fields */ soc_ISC_HG_STATS_COV_DEFS_BCM53400_A0fmt_fields, 33434 /* bits */ 11, 33435 /* flags */ 0, 33436 }, 33437 #endif /* chips */ 33438 33439 #if defined(BCM_53570_B0) 33440 { /* SOC_FORMAT_INT_ISC_IP_STATS_COV_DEFS_BCM53570_B0fmt */ 33441 /* format ISC_IP_STATS_COV_DEFSfmt */ 33442 /* nFields */ 6, 33443 /* *fields */ soc_ISC_HG_STATS_COV_DEFS_BCM53400_A0fmt_fields, 33444 /* bits */ 11, 33445 /* flags */ 0, 33446 }, 33447 #endif /* chips */ 33448 33449 #if defined(BCM_56150_A0) 33450 { /* SOC_FORMAT_INT_ISC_IP_STATS_COV_DEFS_BCM56150_A0fmt */ 33451 /* format ISC_IP_STATS_COV_DEFSfmt */ 33452 /* nFields */ 6, 33453 /* *fields */ soc_ISC_HG_STATS_COV_DEFS_BCM56150_A0fmt_fields, 33454 /* bits */ 11, 33455 /* flags */ 0, 33456 }, 33457 #endif /* chips */ 33458 33459 #if defined(BCM_56160_A0) 33460 { /* SOC_FORMAT_INT_ISC_IP_STATS_COV_DEFS_BCM56160_A0fmt */ 33461 /* format ISC_IP_STATS_COV_DEFSfmt */ 33462 /* nFields */ 6, 33463 /* *fields */ soc_ISC_HG_STATS_COV_DEFS_BCM53400_A0fmt_fields, 33464 /* bits */ 11, 33465 /* flags */ 0, 33466 }, 33467 #endif /* chips */ 33468 33469 #if defined(BCM_56370_A0) 33470 { /* SOC_FORMAT_INT_ISC_IP_STATS_COV_DEFS_BCM56370_A0fmt */ 33471 /* format ISC_IP_STATS_COV_DEFSfmt */ 33472 /* nFields */ 6, 33473 /* *fields */ soc_EGR_PERQ_XMT_COUNTERS_COV_DEFS_BCM53400_A0fmt_fields, 33474 /* bits */ 14, 33475 /* flags */ 0, 33476 }, 33477 #endif /* chips */ 33478 33479 #if defined(BCM_56560_A0) 33480 { /* SOC_FORMAT_INT_ISC_IP_STATS_COV_DEFS_BCM56560_A0fmt */ 33481 /* format ISC_IP_STATS_COV_DEFSfmt */ 33482 /* nFields */ 6, 33483 /* *fields */ soc_ISC_HG_STATS_COV_DEFS_BCM56960_A0fmt_fields, 33484 /* bits */ 15, 33485 /* flags */ 0, 33486 }, 33487 #endif /* chips */ 33488 33489 #if defined(BCM_56560_B0) 33490 { /* SOC_FORMAT_INT_ISC_IP_STATS_COV_DEFS_BCM56560_B0fmt */ 33491 /* format ISC_IP_STATS_COV_DEFSfmt */ 33492 /* nFields */ 6, 33493 /* *fields */ soc_ISC_HG_STATS_COV_DEFS_BCM56960_A0fmt_fields, 33494 /* bits */ 15, 33495 /* flags */ 0, 33496 }, 33497 #endif /* chips */ 33498 33499 #if defined(BCM_56670_A0) 33500 { /* SOC_FORMAT_INT_ISC_IP_STATS_COV_DEFS_BCM56670_A0fmt */ 33501 /* format ISC_IP_STATS_COV_DEFSfmt */ 33502 /* nFields */ 6, 33503 /* *fields */ soc_ISC_HG_STATS_COV_DEFS_BCM56960_A0fmt_fields, 33504 /* bits */ 15, 33505 /* flags */ 0, 33506 }, 33507 #endif /* chips */ 33508 33509 #if defined(BCM_56670_B0) 33510 { /* SOC_FORMAT_INT_ISC_IP_STATS_COV_DEFS_BCM56670_B0fmt */ 33511 /* format ISC_IP_STATS_COV_DEFSfmt */ 33512 /* nFields */ 6, 33513 /* *fields */ soc_ISC_HG_STATS_COV_DEFS_BCM56960_A0fmt_fields, 33514 /* bits */ 15, 33515 /* flags */ 0, 33516 }, 33517 #endif /* chips */ 33518 33519 #if defined(BCM_56770_A0) 33520 { /* SOC_FORMAT_INT_ISC_IP_STATS_COV_DEFS_BCM56770_A0fmt */ 33521 /* format ISC_IP_STATS_COV_DEFSfmt */ 33522 /* nFields */ 6, 33523 /* *fields */ soc_EGR_PERQ_XMT_COUNTERS_COV_DEFS_BCM53400_A0fmt_fields, 33524 /* bits */ 14, 33525 /* flags */ 0, 33526 }, 33527 #endif /* chips */ 33528 33529 #if defined(BCM_56850_A0) 33530 { /* SOC_FORMAT_INT_ISC_IP_STATS_COV_DEFS_BCM56850_A0fmt */ 33531 /* format ISC_IP_STATS_COV_DEFSfmt */ 33532 /* nFields */ 6, 33533 /* *fields */ soc_ISC_IP_STATS_COV_DEFS_BCM56850_A0fmt_fields, 33534 /* bits */ 15, 33535 /* flags */ 0, 33536 }, 33537 #endif /* chips */ 33538 33539 #if defined(BCM_56860_A0) 33540 { /* SOC_FORMAT_INT_ISC_IP_STATS_COV_DEFS_BCM56860_A0fmt */ 33541 /* format ISC_IP_STATS_COV_DEFSfmt */ 33542 /* nFields */ 6, 33543 /* *fields */ soc_ISC_IP_STATS_COV_DEFS_BCM56850_A0fmt_fields, 33544 /* bits */ 15, 33545 /* flags */ 0, 33546 }, 33547 #endif /* chips */ 33548 33549 #if defined(BCM_56870_A0) 33550 { /* SOC_FORMAT_INT_ISC_IP_STATS_COV_DEFS_BCM56870_A0fmt */ 33551 /* format ISC_IP_STATS_COV_DEFSfmt */ 33552 /* nFields */ 6, 33553 /* *fields */ soc_EGR_PERQ_XMT_COUNTERS_COV_DEFS_BCM53400_A0fmt_fields, 33554 /* bits */ 14, 33555 /* flags */ 0, 33556 }, 33557 #endif /* chips */ 33558 33559 #if defined(BCM_56960_A0) 33560 { /* SOC_FORMAT_INT_ISC_IP_STATS_COV_DEFS_BCM56960_A0fmt */ 33561 /* format ISC_IP_STATS_COV_DEFSfmt */ 33562 /* nFields */ 6, 33563 /* *fields */ soc_ISC_IP_STATS_COV_DEFS_BCM56960_A0fmt_fields, 33564 /* bits */ 14, 33565 /* flags */ 0, 33566 }, 33567 #endif /* chips */ 33568 33569 #if defined(BCM_56965_A0) 33570 { /* SOC_FORMAT_INT_ISC_IP_STATS_COV_DEFS_BCM56965_A0fmt */ 33571 /* format ISC_IP_STATS_COV_DEFSfmt */ 33572 /* nFields */ 6, 33573 /* *fields */ soc_ISC_IP_STATS_COV_DEFS_BCM56960_A0fmt_fields, 33574 /* bits */ 14, 33575 /* flags */ 0, 33576 }, 33577 #endif /* chips */ 33578 33579 #if defined(BCM_56970_A0) 33580 { /* SOC_FORMAT_INT_ISC_IP_STATS_COV_DEFS_BCM56970_A0fmt */ 33581 /* format ISC_IP_STATS_COV_DEFSfmt */ 33582 /* nFields */ 6, 33583 /* *fields */ soc_EGR_FCOE_DELIMITER_ERROR_FRAMES_TABLE_COV_DEFS_BCM56960_A0fmt_fields, 33584 /* bits */ 13, 33585 /* flags */ 0, 33586 }, 33587 #endif /* chips */ 33588 33589 #if defined(BCM_56640_A0) 33590 { /* SOC_FORMAT_INT_ISC_STATS_INST0_COV_DEFSfmt */ 33591 /* format ISC_STATS_INST0_COV_DEFSfmt */ 33592 /* nFields */ 6, 33593 /* *fields */ soc_ING_NIV_RX_FRAMES_ERROR_DROP_COV_DEFSfmt_fields, 33594 /* bits */ 13, 33595 /* flags */ 0, 33596 }, 33597 #endif /* chips */ 33598 33599 #if defined(BCM_53400_A0) 33600 { /* SOC_FORMAT_INT_ISC_STATS_INST0_COV_DEFS_BCM53400_A0fmt */ 33601 /* format ISC_STATS_INST0_COV_DEFSfmt */ 33602 /* nFields */ 6, 33603 /* *fields */ soc_ISC_STATS_INST0_COV_DEFS_BCM53400_A0fmt_fields, 33604 /* bits */ 10, 33605 /* flags */ 0, 33606 }, 33607 #endif /* chips */ 33608 33609 #if defined(BCM_53540_A0) 33610 { /* SOC_FORMAT_INT_ISC_STATS_INST0_COV_DEFS_BCM53540_A0fmt */ 33611 /* format ISC_STATS_INST0_COV_DEFSfmt */ 33612 /* nFields */ 6, 33613 /* *fields */ soc_ISC_STATS_INST0_COV_DEFS_BCM53400_A0fmt_fields, 33614 /* bits */ 10, 33615 /* flags */ 0, 33616 }, 33617 #endif /* chips */ 33618 33619 #if defined(BCM_53570_A0) 33620 { /* SOC_FORMAT_INT_ISC_STATS_INST0_COV_DEFS_BCM53570_A0fmt */ 33621 /* format ISC_STATS_INST0_COV_DEFSfmt */ 33622 /* nFields */ 6, 33623 /* *fields */ soc_ISC_STATS_INST0_COV_DEFS_BCM53400_A0fmt_fields, 33624 /* bits */ 10, 33625 /* flags */ 0, 33626 }, 33627 #endif /* chips */ 33628 33629 #if defined(BCM_53570_B0) 33630 { /* SOC_FORMAT_INT_ISC_STATS_INST0_COV_DEFS_BCM53570_B0fmt */ 33631 /* format ISC_STATS_INST0_COV_DEFSfmt */ 33632 /* nFields */ 6, 33633 /* *fields */ soc_ISC_STATS_INST0_COV_DEFS_BCM53400_A0fmt_fields, 33634 /* bits */ 10, 33635 /* flags */ 0, 33636 }, 33637 #endif /* chips */ 33638 33639 #if defined(BCM_56150_A0) 33640 { /* SOC_FORMAT_INT_ISC_STATS_INST0_COV_DEFS_BCM56150_A0fmt */ 33641 /* format ISC_STATS_INST0_COV_DEFSfmt */ 33642 /* nFields */ 6, 33643 /* *fields */ soc_ISC_STATS_INST0_COV_DEFSfmt_fields, 33644 /* bits */ 10, 33645 /* flags */ 0, 33646 }, 33647 #endif /* chips */ 33648 33649 #if defined(BCM_56160_A0) 33650 { /* SOC_FORMAT_INT_ISC_STATS_INST0_COV_DEFS_BCM56160_A0fmt */ 33651 /* format ISC_STATS_INST0_COV_DEFSfmt */ 33652 /* nFields */ 6, 33653 /* *fields */ soc_ISC_STATS_INST0_COV_DEFS_BCM53400_A0fmt_fields, 33654 /* bits */ 10, 33655 /* flags */ 0, 33656 }, 33657 #endif /* chips */ 33658 33659 #if defined(BCM_56340_A0) 33660 { /* SOC_FORMAT_INT_ISC_STATS_INST0_COV_DEFS_BCM56340_A0fmt */ 33661 /* format ISC_STATS_INST0_COV_DEFSfmt */ 33662 /* nFields */ 6, 33663 /* *fields */ soc_ING_NIV_RX_FRAMES_ERROR_DROP_COV_DEFSfmt_fields, 33664 /* bits */ 13, 33665 /* flags */ 0, 33666 }, 33667 #endif /* chips */ 33668 33669 #if defined(BCM_56370_A0) 33670 { /* SOC_FORMAT_INT_ISC_STATS_INST0_COV_DEFS_BCM56370_A0fmt */ 33671 /* format ISC_STATS_INST0_COV_DEFSfmt */ 33672 /* nFields */ 6, 33673 /* *fields */ soc_EGR_FCOE_DELIMITER_ERROR_FRAMES_TABLE_COV_DEFS_BCM56960_A0fmt_fields, 33674 /* bits */ 13, 33675 /* flags */ 0, 33676 }, 33677 #endif /* chips */ 33678 33679 #if defined(BCM_56560_A0) 33680 { /* SOC_FORMAT_INT_ISC_STATS_INST0_COV_DEFS_BCM56560_A0fmt */ 33681 /* format ISC_STATS_INST0_COV_DEFSfmt */ 33682 /* nFields */ 6, 33683 /* *fields */ soc_ISC_IP_STATS_COV_DEFS_BCM56960_A0fmt_fields, 33684 /* bits */ 14, 33685 /* flags */ 0, 33686 }, 33687 #endif /* chips */ 33688 33689 #if defined(BCM_56560_B0) 33690 { /* SOC_FORMAT_INT_ISC_STATS_INST0_COV_DEFS_BCM56560_B0fmt */ 33691 /* format ISC_STATS_INST0_COV_DEFSfmt */ 33692 /* nFields */ 6, 33693 /* *fields */ soc_ISC_IP_STATS_COV_DEFS_BCM56960_A0fmt_fields, 33694 /* bits */ 14, 33695 /* flags */ 0, 33696 }, 33697 #endif /* chips */ 33698 33699 #if defined(BCM_56670_A0) 33700 { /* SOC_FORMAT_INT_ISC_STATS_INST0_COV_DEFS_BCM56670_A0fmt */ 33701 /* format ISC_STATS_INST0_COV_DEFSfmt */ 33702 /* nFields */ 6, 33703 /* *fields */ soc_ISC_IP_STATS_COV_DEFS_BCM56960_A0fmt_fields, 33704 /* bits */ 14, 33705 /* flags */ 0, 33706 }, 33707 #endif /* chips */ 33708 33709 #if defined(BCM_56670_B0) 33710 { /* SOC_FORMAT_INT_ISC_STATS_INST0_COV_DEFS_BCM56670_B0fmt */ 33711 /* format ISC_STATS_INST0_COV_DEFSfmt */ 33712 /* nFields */ 6, 33713 /* *fields */ soc_ISC_IP_STATS_COV_DEFS_BCM56960_A0fmt_fields, 33714 /* bits */ 14, 33715 /* flags */ 0, 33716 }, 33717 #endif /* chips */ 33718 33719 #if defined(BCM_56770_A0) 33720 { /* SOC_FORMAT_INT_ISC_STATS_INST0_COV_DEFS_BCM56770_A0fmt */ 33721 /* format ISC_STATS_INST0_COV_DEFSfmt */ 33722 /* nFields */ 6, 33723 /* *fields */ soc_EGR_FCOE_DELIMITER_ERROR_FRAMES_TABLE_COV_DEFS_BCM56960_A0fmt_fields, 33724 /* bits */ 13, 33725 /* flags */ 0, 33726 }, 33727 #endif /* chips */ 33728 33729 #if defined(BCM_56850_A0) 33730 { /* SOC_FORMAT_INT_ISC_STATS_INST0_COV_DEFS_BCM56850_A0fmt */ 33731 /* format ISC_STATS_INST0_COV_DEFSfmt */ 33732 /* nFields */ 6, 33733 /* *fields */ soc_ISC_IP_STATS_COV_DEFSfmt_fields, 33734 /* bits */ 14, 33735 /* flags */ 0, 33736 }, 33737 #endif /* chips */ 33738 33739 #if defined(BCM_56860_A0) 33740 { /* SOC_FORMAT_INT_ISC_STATS_INST0_COV_DEFS_BCM56860_A0fmt */ 33741 /* format ISC_STATS_INST0_COV_DEFSfmt */ 33742 /* nFields */ 6, 33743 /* *fields */ soc_ISC_IP_STATS_COV_DEFSfmt_fields, 33744 /* bits */ 14, 33745 /* flags */ 0, 33746 }, 33747 #endif /* chips */ 33748 33749 #if defined(BCM_56870_A0) 33750 { /* SOC_FORMAT_INT_ISC_STATS_INST0_COV_DEFS_BCM56870_A0fmt */ 33751 /* format ISC_STATS_INST0_COV_DEFSfmt */ 33752 /* nFields */ 6, 33753 /* *fields */ soc_EGR_FCOE_DELIMITER_ERROR_FRAMES_TABLE_COV_DEFS_BCM56960_A0fmt_fields, 33754 /* bits */ 13, 33755 /* flags */ 0, 33756 }, 33757 #endif /* chips */ 33758 33759 #if defined(BCM_56960_A0) 33760 { /* SOC_FORMAT_INT_ISC_STATS_INST0_COV_DEFS_BCM56960_A0fmt */ 33761 /* format ISC_STATS_INST0_COV_DEFSfmt */ 33762 /* nFields */ 6, 33763 /* *fields */ soc_ISC_IP_STATS_COV_DEFS_BCM56960_A0fmt_fields, 33764 /* bits */ 14, 33765 /* flags */ 0, 33766 }, 33767 #endif /* chips */ 33768 33769 #if defined(BCM_56965_A0) 33770 { /* SOC_FORMAT_INT_ISC_STATS_INST0_COV_DEFS_BCM56965_A0fmt */ 33771 /* format ISC_STATS_INST0_COV_DEFSfmt */ 33772 /* nFields */ 6, 33773 /* *fields */ soc_ISC_IP_STATS_COV_DEFS_BCM56960_A0fmt_fields, 33774 /* bits */ 14, 33775 /* flags */ 0, 33776 }, 33777 #endif /* chips */ 33778 33779 #if defined(BCM_56970_A0) 33780 { /* SOC_FORMAT_INT_ISC_STATS_INST0_COV_DEFS_BCM56970_A0fmt */ 33781 /* format ISC_STATS_INST0_COV_DEFSfmt */ 33782 /* nFields */ 6, 33783 /* *fields */ soc_ISC_STATS_INST0_COV_DEFS_BCM56970_A0fmt_fields, 33784 /* bits */ 12, 33785 /* flags */ 0, 33786 }, 33787 #endif /* chips */ 33788 33789 #if defined(BCM_56640_A0) 33790 { /* SOC_FORMAT_INT_ISC_STATS_INST1_COV_DEFSfmt */ 33791 /* format ISC_STATS_INST1_COV_DEFSfmt */ 33792 /* nFields */ 6, 33793 /* *fields */ soc_ING_NIV_RX_FRAMES_ERROR_DROP_COV_DEFSfmt_fields, 33794 /* bits */ 13, 33795 /* flags */ 0, 33796 }, 33797 #endif /* chips */ 33798 33799 #if defined(BCM_53400_A0) 33800 { /* SOC_FORMAT_INT_ISC_STATS_INST1_COV_DEFS_BCM53400_A0fmt */ 33801 /* format ISC_STATS_INST1_COV_DEFSfmt */ 33802 /* nFields */ 6, 33803 /* *fields */ soc_ISC_STATS_INST0_COV_DEFS_BCM53400_A0fmt_fields, 33804 /* bits */ 10, 33805 /* flags */ 0, 33806 }, 33807 #endif /* chips */ 33808 33809 #if defined(BCM_53540_A0) 33810 { /* SOC_FORMAT_INT_ISC_STATS_INST1_COV_DEFS_BCM53540_A0fmt */ 33811 /* format ISC_STATS_INST1_COV_DEFSfmt */ 33812 /* nFields */ 6, 33813 /* *fields */ soc_ISC_STATS_INST0_COV_DEFS_BCM53400_A0fmt_fields, 33814 /* bits */ 10, 33815 /* flags */ 0, 33816 }, 33817 #endif /* chips */ 33818 33819 #if defined(BCM_53570_A0) 33820 { /* SOC_FORMAT_INT_ISC_STATS_INST1_COV_DEFS_BCM53570_A0fmt */ 33821 /* format ISC_STATS_INST1_COV_DEFSfmt */ 33822 /* nFields */ 6, 33823 /* *fields */ soc_ISC_STATS_INST0_COV_DEFS_BCM53400_A0fmt_fields, 33824 /* bits */ 10, 33825 /* flags */ 0, 33826 }, 33827 #endif /* chips */ 33828 33829 #if defined(BCM_53570_B0) 33830 { /* SOC_FORMAT_INT_ISC_STATS_INST1_COV_DEFS_BCM53570_B0fmt */ 33831 /* format ISC_STATS_INST1_COV_DEFSfmt */ 33832 /* nFields */ 6, 33833 /* *fields */ soc_ISC_STATS_INST0_COV_DEFS_BCM53400_A0fmt_fields, 33834 /* bits */ 10, 33835 /* flags */ 0, 33836 }, 33837 #endif /* chips */ 33838 33839 #if defined(BCM_56150_A0) 33840 { /* SOC_FORMAT_INT_ISC_STATS_INST1_COV_DEFS_BCM56150_A0fmt */ 33841 /* format ISC_STATS_INST1_COV_DEFSfmt */ 33842 /* nFields */ 6, 33843 /* *fields */ soc_ISC_STATS_INST0_COV_DEFSfmt_fields, 33844 /* bits */ 10, 33845 /* flags */ 0, 33846 }, 33847 #endif /* chips */ 33848 33849 #if defined(BCM_56160_A0) 33850 { /* SOC_FORMAT_INT_ISC_STATS_INST1_COV_DEFS_BCM56160_A0fmt */ 33851 /* format ISC_STATS_INST1_COV_DEFSfmt */ 33852 /* nFields */ 6, 33853 /* *fields */ soc_ISC_STATS_INST0_COV_DEFS_BCM53400_A0fmt_fields, 33854 /* bits */ 10, 33855 /* flags */ 0, 33856 }, 33857 #endif /* chips */ 33858 33859 #if defined(BCM_56340_A0) 33860 { /* SOC_FORMAT_INT_ISC_STATS_INST1_COV_DEFS_BCM56340_A0fmt */ 33861 /* format ISC_STATS_INST1_COV_DEFSfmt */ 33862 /* nFields */ 6, 33863 /* *fields */ soc_ING_NIV_RX_FRAMES_ERROR_DROP_COV_DEFSfmt_fields, 33864 /* bits */ 13, 33865 /* flags */ 0, 33866 }, 33867 #endif /* chips */ 33868 33869 #if defined(BCM_56370_A0) 33870 { /* SOC_FORMAT_INT_ISC_STATS_INST1_COV_DEFS_BCM56370_A0fmt */ 33871 /* format ISC_STATS_INST1_COV_DEFSfmt */ 33872 /* nFields */ 6, 33873 /* *fields */ soc_EGR_FCOE_DELIMITER_ERROR_FRAMES_TABLE_COV_DEFS_BCM56960_A0fmt_fields, 33874 /* bits */ 13, 33875 /* flags */ 0, 33876 }, 33877 #endif /* chips */ 33878 33879 #if defined(BCM_56560_A0) 33880 { /* SOC_FORMAT_INT_ISC_STATS_INST1_COV_DEFS_BCM56560_A0fmt */ 33881 /* format ISC_STATS_INST1_COV_DEFSfmt */ 33882 /* nFields */ 6, 33883 /* *fields */ soc_ISC_IP_STATS_COV_DEFS_BCM56960_A0fmt_fields, 33884 /* bits */ 14, 33885 /* flags */ 0, 33886 }, 33887 #endif /* chips */ 33888 33889 #if defined(BCM_56560_B0) 33890 { /* SOC_FORMAT_INT_ISC_STATS_INST1_COV_DEFS_BCM56560_B0fmt */ 33891 /* format ISC_STATS_INST1_COV_DEFSfmt */ 33892 /* nFields */ 6, 33893 /* *fields */ soc_ISC_IP_STATS_COV_DEFS_BCM56960_A0fmt_fields, 33894 /* bits */ 14, 33895 /* flags */ 0, 33896 }, 33897 #endif /* chips */ 33898 33899 #if defined(BCM_56670_A0) 33900 { /* SOC_FORMAT_INT_ISC_STATS_INST1_COV_DEFS_BCM56670_A0fmt */ 33901 /* format ISC_STATS_INST1_COV_DEFSfmt */ 33902 /* nFields */ 6, 33903 /* *fields */ soc_ISC_IP_STATS_COV_DEFS_BCM56960_A0fmt_fields, 33904 /* bits */ 14, 33905 /* flags */ 0, 33906 }, 33907 #endif /* chips */ 33908 33909 #if defined(BCM_56670_B0) 33910 { /* SOC_FORMAT_INT_ISC_STATS_INST1_COV_DEFS_BCM56670_B0fmt */ 33911 /* format ISC_STATS_INST1_COV_DEFSfmt */ 33912 /* nFields */ 6, 33913 /* *fields */ soc_ISC_IP_STATS_COV_DEFS_BCM56960_A0fmt_fields, 33914 /* bits */ 14, 33915 /* flags */ 0, 33916 }, 33917 #endif /* chips */ 33918 33919 #if defined(BCM_56770_A0) 33920 { /* SOC_FORMAT_INT_ISC_STATS_INST1_COV_DEFS_BCM56770_A0fmt */ 33921 /* format ISC_STATS_INST1_COV_DEFSfmt */ 33922 /* nFields */ 6, 33923 /* *fields */ soc_EGR_FCOE_DELIMITER_ERROR_FRAMES_TABLE_COV_DEFS_BCM56960_A0fmt_fields, 33924 /* bits */ 13, 33925 /* flags */ 0, 33926 }, 33927 #endif /* chips */ 33928 33929 #if defined(BCM_56850_A0) 33930 { /* SOC_FORMAT_INT_ISC_STATS_INST1_COV_DEFS_BCM56850_A0fmt */ 33931 /* format ISC_STATS_INST1_COV_DEFSfmt */ 33932 /* nFields */ 6, 33933 /* *fields */ soc_ISC_IP_STATS_COV_DEFSfmt_fields, 33934 /* bits */ 14, 33935 /* flags */ 0, 33936 }, 33937 #endif /* chips */ 33938 33939 #if defined(BCM_56860_A0) 33940 { /* SOC_FORMAT_INT_ISC_STATS_INST1_COV_DEFS_BCM56860_A0fmt */ 33941 /* format ISC_STATS_INST1_COV_DEFSfmt */ 33942 /* nFields */ 6, 33943 /* *fields */ soc_ISC_IP_STATS_COV_DEFSfmt_fields, 33944 /* bits */ 14, 33945 /* flags */ 0, 33946 }, 33947 #endif /* chips */ 33948 33949 #if defined(BCM_56870_A0) 33950 { /* SOC_FORMAT_INT_ISC_STATS_INST1_COV_DEFS_BCM56870_A0fmt */ 33951 /* format ISC_STATS_INST1_COV_DEFSfmt */ 33952 /* nFields */ 6, 33953 /* *fields */ soc_EGR_FCOE_DELIMITER_ERROR_FRAMES_TABLE_COV_DEFS_BCM56960_A0fmt_fields, 33954 /* bits */ 13, 33955 /* flags */ 0, 33956 }, 33957 #endif /* chips */ 33958 33959 #if defined(BCM_56960_A0) 33960 { /* SOC_FORMAT_INT_ISC_STATS_INST1_COV_DEFS_BCM56960_A0fmt */ 33961 /* format ISC_STATS_INST1_COV_DEFSfmt */ 33962 /* nFields */ 6, 33963 /* *fields */ soc_ISC_STATS_INST1_COV_DEFSfmt_fields, 33964 /* bits */ 13, 33965 /* flags */ 0, 33966 }, 33967 #endif /* chips */ 33968 33969 #if defined(BCM_56965_A0) 33970 { /* SOC_FORMAT_INT_ISC_STATS_INST1_COV_DEFS_BCM56965_A0fmt */ 33971 /* format ISC_STATS_INST1_COV_DEFSfmt */ 33972 /* nFields */ 6, 33973 /* *fields */ soc_ISC_STATS_INST1_COV_DEFSfmt_fields, 33974 /* bits */ 13, 33975 /* flags */ 0, 33976 }, 33977 #endif /* chips */ 33978 33979 #if defined(BCM_56970_A0) 33980 { /* SOC_FORMAT_INT_ISC_STATS_INST1_COV_DEFS_BCM56970_A0fmt */ 33981 /* format ISC_STATS_INST1_COV_DEFSfmt */ 33982 /* nFields */ 6, 33983 /* *fields */ soc_ISC_STATS_INST0_COV_DEFS_BCM56970_A0fmt_fields, 33984 /* bits */ 12, 33985 /* flags */ 0, 33986 }, 33987 #endif /* chips */ 33988 33989 #if defined(BCM_56640_A0) 33990 { /* SOC_FORMAT_INT_ISC_STATS_INST2_COV_DEFSfmt */ 33991 /* format ISC_STATS_INST2_COV_DEFSfmt */ 33992 /* nFields */ 6, 33993 /* *fields */ soc_ING_NIV_RX_FRAMES_ERROR_DROP_COV_DEFSfmt_fields, 33994 /* bits */ 13, 33995 /* flags */ 0, 33996 }, 33997 #endif /* chips */ 33998 33999 #if defined(BCM_53400_A0) 34000 { /* SOC_FORMAT_INT_ISC_STATS_INST2_COV_DEFS_BCM53400_A0fmt */ 34001 /* format ISC_STATS_INST2_COV_DEFSfmt */ 34002 /* nFields */ 6, 34003 /* *fields */ soc_ISC_STATS_INST0_COV_DEFS_BCM53400_A0fmt_fields, 34004 /* bits */ 10, 34005 /* flags */ 0, 34006 }, 34007 #endif /* chips */ 34008 34009 #if defined(BCM_53540_A0) 34010 { /* SOC_FORMAT_INT_ISC_STATS_INST2_COV_DEFS_BCM53540_A0fmt */ 34011 /* format ISC_STATS_INST2_COV_DEFSfmt */ 34012 /* nFields */ 6, 34013 /* *fields */ soc_ISC_STATS_INST0_COV_DEFS_BCM53400_A0fmt_fields, 34014 /* bits */ 10, 34015 /* flags */ 0, 34016 }, 34017 #endif /* chips */ 34018 34019 #if defined(BCM_53570_A0) 34020 { /* SOC_FORMAT_INT_ISC_STATS_INST2_COV_DEFS_BCM53570_A0fmt */ 34021 /* format ISC_STATS_INST2_COV_DEFSfmt */ 34022 /* nFields */ 6, 34023 /* *fields */ soc_ISC_STATS_INST0_COV_DEFS_BCM53400_A0fmt_fields, 34024 /* bits */ 10, 34025 /* flags */ 0, 34026 }, 34027 #endif /* chips */ 34028 34029 #if defined(BCM_53570_B0) 34030 { /* SOC_FORMAT_INT_ISC_STATS_INST2_COV_DEFS_BCM53570_B0fmt */ 34031 /* format ISC_STATS_INST2_COV_DEFSfmt */ 34032 /* nFields */ 6, 34033 /* *fields */ soc_ISC_STATS_INST0_COV_DEFS_BCM53400_A0fmt_fields, 34034 /* bits */ 10, 34035 /* flags */ 0, 34036 }, 34037 #endif /* chips */ 34038 34039 #if defined(BCM_56150_A0) 34040 { /* SOC_FORMAT_INT_ISC_STATS_INST2_COV_DEFS_BCM56150_A0fmt */ 34041 /* format ISC_STATS_INST2_COV_DEFSfmt */ 34042 /* nFields */ 6, 34043 /* *fields */ soc_ISC_STATS_INST0_COV_DEFSfmt_fields, 34044 /* bits */ 10, 34045 /* flags */ 0, 34046 }, 34047 #endif /* chips */ 34048 34049 #if defined(BCM_56160_A0) 34050 { /* SOC_FORMAT_INT_ISC_STATS_INST2_COV_DEFS_BCM56160_A0fmt */ 34051 /* format ISC_STATS_INST2_COV_DEFSfmt */ 34052 /* nFields */ 6, 34053 /* *fields */ soc_ISC_STATS_INST0_COV_DEFS_BCM53400_A0fmt_fields, 34054 /* bits */ 10, 34055 /* flags */ 0, 34056 }, 34057 #endif /* chips */ 34058 34059 #if defined(BCM_56340_A0) 34060 { /* SOC_FORMAT_INT_ISC_STATS_INST2_COV_DEFS_BCM56340_A0fmt */ 34061 /* format ISC_STATS_INST2_COV_DEFSfmt */ 34062 /* nFields */ 6, 34063 /* *fields */ soc_ING_NIV_RX_FRAMES_ERROR_DROP_COV_DEFSfmt_fields, 34064 /* bits */ 13, 34065 /* flags */ 0, 34066 }, 34067 #endif /* chips */ 34068 34069 #if defined(BCM_56370_A0) 34070 { /* SOC_FORMAT_INT_ISC_STATS_INST2_COV_DEFS_BCM56370_A0fmt */ 34071 /* format ISC_STATS_INST2_COV_DEFSfmt */ 34072 /* nFields */ 6, 34073 /* *fields */ soc_EGR_FCOE_DELIMITER_ERROR_FRAMES_TABLE_COV_DEFS_BCM56960_A0fmt_fields, 34074 /* bits */ 13, 34075 /* flags */ 0, 34076 }, 34077 #endif /* chips */ 34078 34079 #if defined(BCM_56560_A0) 34080 { /* SOC_FORMAT_INT_ISC_STATS_INST2_COV_DEFS_BCM56560_A0fmt */ 34081 /* format ISC_STATS_INST2_COV_DEFSfmt */ 34082 /* nFields */ 6, 34083 /* *fields */ soc_ISC_IP_STATS_COV_DEFS_BCM56960_A0fmt_fields, 34084 /* bits */ 14, 34085 /* flags */ 0, 34086 }, 34087 #endif /* chips */ 34088 34089 #if defined(BCM_56560_B0) 34090 { /* SOC_FORMAT_INT_ISC_STATS_INST2_COV_DEFS_BCM56560_B0fmt */ 34091 /* format ISC_STATS_INST2_COV_DEFSfmt */ 34092 /* nFields */ 6, 34093 /* *fields */ soc_ISC_IP_STATS_COV_DEFS_BCM56960_A0fmt_fields, 34094 /* bits */ 14, 34095 /* flags */ 0, 34096 }, 34097 #endif /* chips */ 34098 34099 #if defined(BCM_56670_A0) 34100 { /* SOC_FORMAT_INT_ISC_STATS_INST2_COV_DEFS_BCM56670_A0fmt */ 34101 /* format ISC_STATS_INST2_COV_DEFSfmt */ 34102 /* nFields */ 6, 34103 /* *fields */ soc_ISC_IP_STATS_COV_DEFS_BCM56960_A0fmt_fields, 34104 /* bits */ 14, 34105 /* flags */ 0, 34106 }, 34107 #endif /* chips */ 34108 34109 #if defined(BCM_56670_B0) 34110 { /* SOC_FORMAT_INT_ISC_STATS_INST2_COV_DEFS_BCM56670_B0fmt */ 34111 /* format ISC_STATS_INST2_COV_DEFSfmt */ 34112 /* nFields */ 6, 34113 /* *fields */ soc_ISC_IP_STATS_COV_DEFS_BCM56960_A0fmt_fields, 34114 /* bits */ 14, 34115 /* flags */ 0, 34116 }, 34117 #endif /* chips */ 34118 34119 #if defined(BCM_56770_A0) 34120 { /* SOC_FORMAT_INT_ISC_STATS_INST2_COV_DEFS_BCM56770_A0fmt */ 34121 /* format ISC_STATS_INST2_COV_DEFSfmt */ 34122 /* nFields */ 6, 34123 /* *fields */ soc_EGR_FCOE_DELIMITER_ERROR_FRAMES_TABLE_COV_DEFS_BCM56960_A0fmt_fields, 34124 /* bits */ 13, 34125 /* flags */ 0, 34126 }, 34127 #endif /* chips */ 34128 34129 #if defined(BCM_56850_A0) 34130 { /* SOC_FORMAT_INT_ISC_STATS_INST2_COV_DEFS_BCM56850_A0fmt */ 34131 /* format ISC_STATS_INST2_COV_DEFSfmt */ 34132 /* nFields */ 6, 34133 /* *fields */ soc_ISC_IP_STATS_COV_DEFSfmt_fields, 34134 /* bits */ 14, 34135 /* flags */ 0, 34136 }, 34137 #endif /* chips */ 34138 34139 #if defined(BCM_56860_A0) 34140 { /* SOC_FORMAT_INT_ISC_STATS_INST2_COV_DEFS_BCM56860_A0fmt */ 34141 /* format ISC_STATS_INST2_COV_DEFSfmt */ 34142 /* nFields */ 6, 34143 /* *fields */ soc_ISC_IP_STATS_COV_DEFSfmt_fields, 34144 /* bits */ 14, 34145 /* flags */ 0, 34146 }, 34147 #endif /* chips */ 34148 34149 #if defined(BCM_56870_A0) 34150 { /* SOC_FORMAT_INT_ISC_STATS_INST2_COV_DEFS_BCM56870_A0fmt */ 34151 /* format ISC_STATS_INST2_COV_DEFSfmt */ 34152 /* nFields */ 6, 34153 /* *fields */ soc_EGR_FCOE_DELIMITER_ERROR_FRAMES_TABLE_COV_DEFS_BCM56960_A0fmt_fields, 34154 /* bits */ 13, 34155 /* flags */ 0, 34156 }, 34157 #endif /* chips */ 34158 34159 #if defined(BCM_56960_A0) 34160 { /* SOC_FORMAT_INT_ISC_STATS_INST2_COV_DEFS_BCM56960_A0fmt */ 34161 /* format ISC_STATS_INST2_COV_DEFSfmt */ 34162 /* nFields */ 6, 34163 /* *fields */ soc_ISC_STATS_INST1_COV_DEFSfmt_fields, 34164 /* bits */ 13, 34165 /* flags */ 0, 34166 }, 34167 #endif /* chips */ 34168 34169 #if defined(BCM_56965_A0) 34170 { /* SOC_FORMAT_INT_ISC_STATS_INST2_COV_DEFS_BCM56965_A0fmt */ 34171 /* format ISC_STATS_INST2_COV_DEFSfmt */ 34172 /* nFields */ 6, 34173 /* *fields */ soc_ISC_STATS_INST1_COV_DEFSfmt_fields, 34174 /* bits */ 13, 34175 /* flags */ 0, 34176 }, 34177 #endif /* chips */ 34178 34179 #if defined(BCM_56970_A0) 34180 { /* SOC_FORMAT_INT_ISC_STATS_INST2_COV_DEFS_BCM56970_A0fmt */ 34181 /* format ISC_STATS_INST2_COV_DEFSfmt */ 34182 /* nFields */ 6, 34183 /* *fields */ soc_ISC_STATS_INST0_COV_DEFS_BCM56970_A0fmt_fields, 34184 /* bits */ 12, 34185 /* flags */ 0, 34186 }, 34187 #endif /* chips */ 34188 34189 #if defined(BCM_56870_A0) 34190 { /* SOC_FORMAT_INT_ISC_STATS_INST3_COV_DEFSfmt */ 34191 /* format ISC_STATS_INST3_COV_DEFSfmt */ 34192 /* nFields */ 6, 34193 /* *fields */ soc_EGR_FCOE_DELIMITER_ERROR_FRAMES_TABLE_COV_DEFS_BCM56960_A0fmt_fields, 34194 /* bits */ 13, 34195 /* flags */ 0, 34196 }, 34197 #endif /* chips */ 34198 34199 #if defined(BCM_56370_A0) 34200 { /* SOC_FORMAT_INT_ISC_STATS_INST3_COV_DEFS_BCM56370_A0fmt */ 34201 /* format ISC_STATS_INST3_COV_DEFSfmt */ 34202 /* nFields */ 6, 34203 /* *fields */ soc_EGR_FCOE_DELIMITER_ERROR_FRAMES_TABLE_COV_DEFS_BCM56960_A0fmt_fields, 34204 /* bits */ 13, 34205 /* flags */ 0, 34206 }, 34207 #endif /* chips */ 34208 34209 #if defined(BCM_56770_A0) 34210 { /* SOC_FORMAT_INT_ISC_STATS_INST3_COV_DEFS_BCM56770_A0fmt */ 34211 /* format ISC_STATS_INST3_COV_DEFSfmt */ 34212 /* nFields */ 6, 34213 /* *fields */ soc_EGR_FCOE_DELIMITER_ERROR_FRAMES_TABLE_COV_DEFS_BCM56960_A0fmt_fields, 34214 /* bits */ 13, 34215 /* flags */ 0, 34216 }, 34217 #endif /* chips */ 34218 34219 #if defined(BCM_56870_A0) 34220 { /* SOC_FORMAT_INT_ISC_STATS_INST4_COV_DEFSfmt */ 34221 /* format ISC_STATS_INST4_COV_DEFSfmt */ 34222 /* nFields */ 6, 34223 /* *fields */ soc_EGR_FCOE_DELIMITER_ERROR_FRAMES_TABLE_COV_DEFS_BCM56960_A0fmt_fields, 34224 /* bits */ 13, 34225 /* flags */ 0, 34226 }, 34227 #endif /* chips */ 34228 34229 #if defined(BCM_56370_A0) 34230 { /* SOC_FORMAT_INT_ISC_STATS_INST4_COV_DEFS_BCM56370_A0fmt */ 34231 /* format ISC_STATS_INST4_COV_DEFSfmt */ 34232 /* nFields */ 6, 34233 /* *fields */ soc_EGR_FCOE_DELIMITER_ERROR_FRAMES_TABLE_COV_DEFS_BCM56960_A0fmt_fields, 34234 /* bits */ 13, 34235 /* flags */ 0, 34236 }, 34237 #endif /* chips */ 34238 34239 #if defined(BCM_56770_A0) 34240 { /* SOC_FORMAT_INT_ISC_STATS_INST4_COV_DEFS_BCM56770_A0fmt */ 34241 /* format ISC_STATS_INST4_COV_DEFSfmt */ 34242 /* nFields */ 6, 34243 /* *fields */ soc_EGR_FCOE_DELIMITER_ERROR_FRAMES_TABLE_COV_DEFS_BCM56960_A0fmt_fields, 34244 /* bits */ 13, 34245 /* flags */ 0, 34246 }, 34247 #endif /* chips */ 34248 34249 #if defined(BCM_56970_A0) || defined(BCM_56980_A0) || \ 34250 defined(BCM_56980_B0) 34251 { /* SOC_FORMAT_INT_ISM_ENTRY_16KBY420_2P_COV_DEFSfmt */ 34252 /* format ISM_ENTRY_16KBY420_2P_COV_DEFSfmt */ 34253 /* nFields */ 10, 34254 /* *fields */ soc_ISM_ENTRY_16KBY420_2P_COV_DEFSfmt_fields, 34255 /* bits */ 59, 34256 /* flags */ 0, 34257 }, 34258 #endif /* chips */ 34259 34260 #if defined(BCM_56870_A0) 34261 { /* SOC_FORMAT_INT_ISM_ENTRY_1BASE_2P_COV_DEFSfmt */ 34262 /* format ISM_ENTRY_1BASE_2P_COV_DEFSfmt */ 34263 /* nFields */ 10, 34264 /* *fields */ soc_ISM_ENTRY_16KBY420_2P_COV_DEFSfmt_fields, 34265 /* bits */ 59, 34266 /* flags */ 0, 34267 }, 34268 #endif /* chips */ 34269 34270 #if defined(BCM_56370_A0) 34271 { /* SOC_FORMAT_INT_ISM_ENTRY_1BASE_2P_COV_DEFS_BCM56370_A0fmt */ 34272 /* format ISM_ENTRY_1BASE_2P_COV_DEFSfmt */ 34273 /* nFields */ 10, 34274 /* *fields */ soc_ISM_ENTRY_16KBY420_2P_COV_DEFSfmt_fields, 34275 /* bits */ 59, 34276 /* flags */ 0, 34277 }, 34278 #endif /* chips */ 34279 34280 #if defined(BCM_56770_A0) 34281 { /* SOC_FORMAT_INT_ISM_ENTRY_1BASE_2P_COV_DEFS_BCM56770_A0fmt */ 34282 /* format ISM_ENTRY_1BASE_2P_COV_DEFSfmt */ 34283 /* nFields */ 10, 34284 /* *fields */ soc_ISM_ENTRY_16KBY420_2P_COV_DEFSfmt_fields, 34285 /* bits */ 59, 34286 /* flags */ 0, 34287 }, 34288 #endif /* chips */ 34289 34290 #if defined(BCM_56980_A0) 34291 { /* SOC_FORMAT_INT_ISM_ENTRY_1BASE_2P_COV_DEFS_BCM56980_A0fmt */ 34292 /* format ISM_ENTRY_1BASE_2P_COV_DEFSfmt */ 34293 /* nFields */ 10, 34294 /* *fields */ soc_ISM_ENTRY_16KBY420_2P_COV_DEFSfmt_fields, 34295 /* bits */ 59, 34296 /* flags */ 0, 34297 }, 34298 #endif /* chips */ 34299 34300 #if defined(BCM_56980_B0) 34301 { /* SOC_FORMAT_INT_ISM_ENTRY_1BASE_2P_COV_DEFS_BCM56980_B0fmt */ 34302 /* format ISM_ENTRY_1BASE_2P_COV_DEFSfmt */ 34303 /* nFields */ 10, 34304 /* *fields */ soc_ISM_ENTRY_16KBY420_2P_COV_DEFSfmt_fields, 34305 /* bits */ 59, 34306 /* flags */ 0, 34307 }, 34308 #endif /* chips */ 34309 34310 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 34311 { /* SOC_FORMAT_INT_ISM_ENTRY_1BASE_4P_COV_DEFSfmt */ 34312 /* format ISM_ENTRY_1BASE_4P_COV_DEFSfmt */ 34313 /* nFields */ 27, 34314 /* *fields */ soc_ISM_ENTRY_1BASE_4P_COV_DEFSfmt_fields, 34315 /* bits */ 124, 34316 /* flags */ 0, 34317 }, 34318 #endif /* chips */ 34319 34320 #if defined(BCM_56870_A0) 34321 { /* SOC_FORMAT_INT_ISM_ENTRY_2BASE_2P_COV_DEFSfmt */ 34322 /* format ISM_ENTRY_2BASE_2P_COV_DEFSfmt */ 34323 /* nFields */ 10, 34324 /* *fields */ soc_ISM_ENTRY_16KBY420_2P_COV_DEFSfmt_fields, 34325 /* bits */ 59, 34326 /* flags */ 0, 34327 }, 34328 #endif /* chips */ 34329 34330 #if defined(BCM_56370_A0) 34331 { /* SOC_FORMAT_INT_ISM_ENTRY_2BASE_2P_COV_DEFS_BCM56370_A0fmt */ 34332 /* format ISM_ENTRY_2BASE_2P_COV_DEFSfmt */ 34333 /* nFields */ 10, 34334 /* *fields */ soc_ISM_ENTRY_16KBY420_2P_COV_DEFSfmt_fields, 34335 /* bits */ 59, 34336 /* flags */ 0, 34337 }, 34338 #endif /* chips */ 34339 34340 #if defined(BCM_56770_A0) 34341 { /* SOC_FORMAT_INT_ISM_ENTRY_2BASE_2P_COV_DEFS_BCM56770_A0fmt */ 34342 /* format ISM_ENTRY_2BASE_2P_COV_DEFSfmt */ 34343 /* nFields */ 10, 34344 /* *fields */ soc_ISM_ENTRY_16KBY420_2P_COV_DEFSfmt_fields, 34345 /* bits */ 59, 34346 /* flags */ 0, 34347 }, 34348 #endif /* chips */ 34349 34350 #if defined(BCM_56980_A0) 34351 { /* SOC_FORMAT_INT_ISM_ENTRY_2BASE_2P_COV_DEFS_BCM56980_A0fmt */ 34352 /* format ISM_ENTRY_2BASE_2P_COV_DEFSfmt */ 34353 /* nFields */ 10, 34354 /* *fields */ soc_ISM_ENTRY_16KBY420_2P_COV_DEFSfmt_fields, 34355 /* bits */ 59, 34356 /* flags */ 0, 34357 }, 34358 #endif /* chips */ 34359 34360 #if defined(BCM_56980_B0) 34361 { /* SOC_FORMAT_INT_ISM_ENTRY_2BASE_2P_COV_DEFS_BCM56980_B0fmt */ 34362 /* format ISM_ENTRY_2BASE_2P_COV_DEFSfmt */ 34363 /* nFields */ 10, 34364 /* *fields */ soc_ISM_ENTRY_16KBY420_2P_COV_DEFSfmt_fields, 34365 /* bits */ 59, 34366 /* flags */ 0, 34367 }, 34368 #endif /* chips */ 34369 34370 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 34371 { /* SOC_FORMAT_INT_ISM_ENTRY_2BASE_4P_COV_DEFSfmt */ 34372 /* format ISM_ENTRY_2BASE_4P_COV_DEFSfmt */ 34373 /* nFields */ 25, 34374 /* *fields */ soc_ISM_ENTRY_2BASE_4P_COV_DEFSfmt_fields, 34375 /* bits */ 124, 34376 /* flags */ 0, 34377 }, 34378 #endif /* chips */ 34379 34380 #if defined(BCM_56870_A0) 34381 { /* SOC_FORMAT_INT_ISM_ENTRY_4BASE_2P_COV_DEFSfmt */ 34382 /* format ISM_ENTRY_4BASE_2P_COV_DEFSfmt */ 34383 /* nFields */ 10, 34384 /* *fields */ soc_ISM_ENTRY_16KBY420_2P_COV_DEFSfmt_fields, 34385 /* bits */ 59, 34386 /* flags */ 0, 34387 }, 34388 #endif /* chips */ 34389 34390 #if defined(BCM_56370_A0) 34391 { /* SOC_FORMAT_INT_ISM_ENTRY_4BASE_2P_COV_DEFS_BCM56370_A0fmt */ 34392 /* format ISM_ENTRY_4BASE_2P_COV_DEFSfmt */ 34393 /* nFields */ 10, 34394 /* *fields */ soc_ISM_ENTRY_16KBY420_2P_COV_DEFSfmt_fields, 34395 /* bits */ 59, 34396 /* flags */ 0, 34397 }, 34398 #endif /* chips */ 34399 34400 #if defined(BCM_56770_A0) 34401 { /* SOC_FORMAT_INT_ISM_ENTRY_4BASE_2P_COV_DEFS_BCM56770_A0fmt */ 34402 /* format ISM_ENTRY_4BASE_2P_COV_DEFSfmt */ 34403 /* nFields */ 10, 34404 /* *fields */ soc_ISM_ENTRY_16KBY420_2P_COV_DEFSfmt_fields, 34405 /* bits */ 59, 34406 /* flags */ 0, 34407 }, 34408 #endif /* chips */ 34409 34410 #if defined(BCM_56980_A0) 34411 { /* SOC_FORMAT_INT_ISM_ENTRY_4BASE_2P_COV_DEFS_BCM56980_A0fmt */ 34412 /* format ISM_ENTRY_4BASE_2P_COV_DEFSfmt */ 34413 /* nFields */ 10, 34414 /* *fields */ soc_ISM_ENTRY_16KBY420_2P_COV_DEFSfmt_fields, 34415 /* bits */ 59, 34416 /* flags */ 0, 34417 }, 34418 #endif /* chips */ 34419 34420 #if defined(BCM_56980_B0) 34421 { /* SOC_FORMAT_INT_ISM_ENTRY_4BASE_2P_COV_DEFS_BCM56980_B0fmt */ 34422 /* format ISM_ENTRY_4BASE_2P_COV_DEFSfmt */ 34423 /* nFields */ 10, 34424 /* *fields */ soc_ISM_ENTRY_16KBY420_2P_COV_DEFSfmt_fields, 34425 /* bits */ 59, 34426 /* flags */ 0, 34427 }, 34428 #endif /* chips */ 34429 34430 #if defined(BCM_56980_A0) 34431 { /* SOC_FORMAT_INT_ISM_ENTRY_4BASE_4P_COV_DEFSfmt */ 34432 /* format ISM_ENTRY_4BASE_4P_COV_DEFSfmt */ 34433 /* nFields */ 27, 34434 /* *fields */ soc_ISM_ENTRY_1BASE_4P_COV_DEFSfmt_fields, 34435 /* bits */ 124, 34436 /* flags */ 0, 34437 }, 34438 #endif /* chips */ 34439 34440 #if defined(BCM_56980_B0) 34441 { /* SOC_FORMAT_INT_ISM_ENTRY_4BASE_4P_COV_DEFS_BCM56980_B0fmt */ 34442 /* format ISM_ENTRY_4BASE_4P_COV_DEFSfmt */ 34443 /* nFields */ 27, 34444 /* *fields */ soc_ISM_ENTRY_1BASE_4P_COV_DEFSfmt_fields, 34445 /* bits */ 124, 34446 /* flags */ 0, 34447 }, 34448 #endif /* chips */ 34449 34450 #if defined(BCM_56970_A0) || defined(BCM_56980_A0) || \ 34451 defined(BCM_56980_B0) 34452 { /* SOC_FORMAT_INT_ISM_ENTRY_8KBY105_2P_COV_DEFSfmt */ 34453 /* format ISM_ENTRY_8KBY105_2P_COV_DEFSfmt */ 34454 /* nFields */ 10, 34455 /* *fields */ soc_ISM_ENTRY_8KBY105_2P_COV_DEFSfmt_fields, 34456 /* bits */ 37, 34457 /* flags */ 0, 34458 }, 34459 #endif /* chips */ 34460 34461 #if defined(BCM_56970_A0) 34462 { /* SOC_FORMAT_INT_ISM_ENTRY_8KBY140_2P_COV_DEFSfmt */ 34463 /* format ISM_ENTRY_8KBY140_2P_COV_DEFSfmt */ 34464 /* nFields */ 10, 34465 /* *fields */ soc_ISM_ENTRY_8KBY105_2P_COV_DEFSfmt_fields, 34466 /* bits */ 37, 34467 /* flags */ 0, 34468 }, 34469 #endif /* chips */ 34470 34471 #if defined(BCM_56980_A0) 34472 { /* SOC_FORMAT_INT_ISM_ENTRY_8KBY140_2P_COV_DEFS_BCM56980_A0fmt */ 34473 /* format ISM_ENTRY_8KBY140_2P_COV_DEFSfmt */ 34474 /* nFields */ 10, 34475 /* *fields */ soc_ISM_ENTRY_8KBY105_2P_COV_DEFSfmt_fields, 34476 /* bits */ 37, 34477 /* flags */ 0, 34478 }, 34479 #endif /* chips */ 34480 34481 #if defined(BCM_56980_B0) 34482 { /* SOC_FORMAT_INT_ISM_ENTRY_8KBY140_2P_COV_DEFS_BCM56980_B0fmt */ 34483 /* format ISM_ENTRY_8KBY140_2P_COV_DEFSfmt */ 34484 /* nFields */ 10, 34485 /* *fields */ soc_ISM_ENTRY_8KBY105_2P_COV_DEFSfmt_fields, 34486 /* bits */ 37, 34487 /* flags */ 0, 34488 }, 34489 #endif /* chips */ 34490 34491 #if defined(BCM_56340_A0) || defined(BCM_56640_A0) 34492 { /* SOC_FORMAT_INT_ISM_LEARN_BUSfmt */ 34493 /* format ISM_LEARN_BUSfmt */ 34494 /* nFields */ 15, 34495 /* *fields */ soc_ISM_LEARN_BUSfmt_fields, 34496 /* bits */ 95, 34497 /* flags */ 0, 34498 }, 34499 #endif /* chips */ 34500 34501 #if defined(BCM_56340_A0) || defined(BCM_56640_A0) || \ 34502 defined(BCM_56850_A0) || defined(BCM_56860_A0) 34503 { /* SOC_FORMAT_INT_ISM_RSP_WORDfmt */ 34504 /* format ISM_RSP_WORDfmt */ 34505 /* nFields */ 4, 34506 /* *fields */ soc_ISM_RSP_WORDfmt_fields, 34507 /* bits */ 32, 34508 /* flags */ 0, 34509 }, 34510 #endif /* chips */ 34511 34512 #if defined(BCM_56260_A0) 34513 { /* SOC_FORMAT_INT_ISM_RSP_WORD_BCM56260_A0fmt */ 34514 /* format ISM_RSP_WORDfmt */ 34515 /* nFields */ 4, 34516 /* *fields */ soc_ISM_RSP_WORD_BCM56960_A0fmt_fields, 34517 /* bits */ 32, 34518 /* flags */ 0, 34519 }, 34520 #endif /* chips */ 34521 34522 #if defined(BCM_56260_B0) 34523 { /* SOC_FORMAT_INT_ISM_RSP_WORD_BCM56260_B0fmt */ 34524 /* format ISM_RSP_WORDfmt */ 34525 /* nFields */ 4, 34526 /* *fields */ soc_ISM_RSP_WORD_BCM56960_A0fmt_fields, 34527 /* bits */ 32, 34528 /* flags */ 0, 34529 }, 34530 #endif /* chips */ 34531 34532 #if defined(BCM_56270_A0) 34533 { /* SOC_FORMAT_INT_ISM_RSP_WORD_BCM56270_A0fmt */ 34534 /* format ISM_RSP_WORDfmt */ 34535 /* nFields */ 4, 34536 /* *fields */ soc_ISM_RSP_WORD_BCM56960_A0fmt_fields, 34537 /* bits */ 32, 34538 /* flags */ 0, 34539 }, 34540 #endif /* chips */ 34541 34542 #if defined(BCM_56370_A0) 34543 { /* SOC_FORMAT_INT_ISM_RSP_WORD_BCM56370_A0fmt */ 34544 /* format ISM_RSP_WORDfmt */ 34545 /* nFields */ 4, 34546 /* *fields */ soc_ISM_RSP_WORD_BCM56960_A0fmt_fields, 34547 /* bits */ 32, 34548 /* flags */ 0, 34549 }, 34550 #endif /* chips */ 34551 34552 #if defined(BCM_56560_A0) 34553 { /* SOC_FORMAT_INT_ISM_RSP_WORD_BCM56560_A0fmt */ 34554 /* format ISM_RSP_WORDfmt */ 34555 /* nFields */ 4, 34556 /* *fields */ soc_ISM_RSP_WORD_BCM56960_A0fmt_fields, 34557 /* bits */ 32, 34558 /* flags */ 0, 34559 }, 34560 #endif /* chips */ 34561 34562 #if defined(BCM_56560_B0) 34563 { /* SOC_FORMAT_INT_ISM_RSP_WORD_BCM56560_B0fmt */ 34564 /* format ISM_RSP_WORDfmt */ 34565 /* nFields */ 4, 34566 /* *fields */ soc_ISM_RSP_WORD_BCM56960_A0fmt_fields, 34567 /* bits */ 32, 34568 /* flags */ 0, 34569 }, 34570 #endif /* chips */ 34571 34572 #if defined(BCM_56670_A0) 34573 { /* SOC_FORMAT_INT_ISM_RSP_WORD_BCM56670_A0fmt */ 34574 /* format ISM_RSP_WORDfmt */ 34575 /* nFields */ 4, 34576 /* *fields */ soc_ISM_RSP_WORD_BCM56960_A0fmt_fields, 34577 /* bits */ 32, 34578 /* flags */ 0, 34579 }, 34580 #endif /* chips */ 34581 34582 #if defined(BCM_56670_B0) 34583 { /* SOC_FORMAT_INT_ISM_RSP_WORD_BCM56670_B0fmt */ 34584 /* format ISM_RSP_WORDfmt */ 34585 /* nFields */ 4, 34586 /* *fields */ soc_ISM_RSP_WORD_BCM56960_A0fmt_fields, 34587 /* bits */ 32, 34588 /* flags */ 0, 34589 }, 34590 #endif /* chips */ 34591 34592 #if defined(BCM_56770_A0) 34593 { /* SOC_FORMAT_INT_ISM_RSP_WORD_BCM56770_A0fmt */ 34594 /* format ISM_RSP_WORDfmt */ 34595 /* nFields */ 4, 34596 /* *fields */ soc_ISM_RSP_WORD_BCM56960_A0fmt_fields, 34597 /* bits */ 32, 34598 /* flags */ 0, 34599 }, 34600 #endif /* chips */ 34601 34602 #if defined(BCM_56870_A0) 34603 { /* SOC_FORMAT_INT_ISM_RSP_WORD_BCM56870_A0fmt */ 34604 /* format ISM_RSP_WORDfmt */ 34605 /* nFields */ 4, 34606 /* *fields */ soc_ISM_RSP_WORD_BCM56960_A0fmt_fields, 34607 /* bits */ 32, 34608 /* flags */ 0, 34609 }, 34610 #endif /* chips */ 34611 34612 #if defined(BCM_56960_A0) 34613 { /* SOC_FORMAT_INT_ISM_RSP_WORD_BCM56960_A0fmt */ 34614 /* format ISM_RSP_WORDfmt */ 34615 /* nFields */ 4, 34616 /* *fields */ soc_ISM_RSP_WORD_BCM56960_A0fmt_fields, 34617 /* bits */ 32, 34618 /* flags */ 0, 34619 }, 34620 #endif /* chips */ 34621 34622 #if defined(BCM_56965_A0) 34623 { /* SOC_FORMAT_INT_ISM_RSP_WORD_BCM56965_A0fmt */ 34624 /* format ISM_RSP_WORDfmt */ 34625 /* nFields */ 4, 34626 /* *fields */ soc_ISM_RSP_WORD_BCM56960_A0fmt_fields, 34627 /* bits */ 32, 34628 /* flags */ 0, 34629 }, 34630 #endif /* chips */ 34631 34632 #if defined(BCM_56970_A0) 34633 { /* SOC_FORMAT_INT_ISM_RSP_WORD_BCM56970_A0fmt */ 34634 /* format ISM_RSP_WORDfmt */ 34635 /* nFields */ 4, 34636 /* *fields */ soc_ISM_RSP_WORD_BCM56960_A0fmt_fields, 34637 /* bits */ 32, 34638 /* flags */ 0, 34639 }, 34640 #endif /* chips */ 34641 34642 #if defined(BCM_56980_A0) 34643 { /* SOC_FORMAT_INT_ISM_RSP_WORD_BCM56980_A0fmt */ 34644 /* format ISM_RSP_WORDfmt */ 34645 /* nFields */ 4, 34646 /* *fields */ soc_ISM_RSP_WORD_BCM56960_A0fmt_fields, 34647 /* bits */ 32, 34648 /* flags */ 0, 34649 }, 34650 #endif /* chips */ 34651 34652 #if defined(BCM_56980_B0) 34653 { /* SOC_FORMAT_INT_ISM_RSP_WORD_BCM56980_B0fmt */ 34654 /* format ISM_RSP_WORDfmt */ 34655 /* nFields */ 4, 34656 /* *fields */ soc_ISM_RSP_WORD_BCM56960_A0fmt_fields, 34657 /* bits */ 32, 34658 /* flags */ 0, 34659 }, 34660 #endif /* chips */ 34661 34662 #if defined(BCM_56504_A0) 34663 { /* SOC_FORMAT_INT_ISW1_DROPfmt */ 34664 /* format ISW1_DROPfmt */ 34665 /* nFields */ 12, 34666 /* *fields */ soc_ISW1_DROPfmt_fields, 34667 /* bits */ 12, 34668 /* flags */ 0, 34669 }, 34670 #endif /* chips */ 34671 34672 #if defined(BCM_53314_A0) 34673 { /* SOC_FORMAT_INT_ISW1_DROP_BCM53314_A0fmt */ 34674 /* format ISW1_DROPfmt */ 34675 /* nFields */ 17, 34676 /* *fields */ soc_ISW1_DROP_BCM56224_A0fmt_fields, 34677 /* bits */ 15, 34678 /* flags */ 0, 34679 }, 34680 #endif /* chips */ 34681 34682 #if defined(BCM_53324_A0) 34683 { /* SOC_FORMAT_INT_ISW1_DROP_BCM53324_A0fmt */ 34684 /* format ISW1_DROPfmt */ 34685 /* nFields */ 17, 34686 /* *fields */ soc_ISW1_DROP_BCM56224_A0fmt_fields, 34687 /* bits */ 15, 34688 /* flags */ 0, 34689 }, 34690 #endif /* chips */ 34691 34692 #if defined(BCM_53400_A0) 34693 { /* SOC_FORMAT_INT_ISW1_DROP_BCM53400_A0fmt */ 34694 /* format ISW1_DROPfmt */ 34695 /* nFields */ 29, 34696 /* *fields */ soc_ISW1_DROP_BCM53400_A0fmt_fields, 34697 /* bits */ 29, 34698 /* flags */ 0, 34699 }, 34700 #endif /* chips */ 34701 34702 #if defined(BCM_53540_A0) 34703 { /* SOC_FORMAT_INT_ISW1_DROP_BCM53540_A0fmt */ 34704 /* format ISW1_DROPfmt */ 34705 /* nFields */ 29, 34706 /* *fields */ soc_ISW1_DROP_BCM53400_A0fmt_fields, 34707 /* bits */ 29, 34708 /* flags */ 0, 34709 }, 34710 #endif /* chips */ 34711 34712 #if defined(BCM_53570_A0) 34713 { /* SOC_FORMAT_INT_ISW1_DROP_BCM53570_A0fmt */ 34714 /* format ISW1_DROPfmt */ 34715 /* nFields */ 30, 34716 /* *fields */ soc_ISW1_DROP_BCM53570_A0fmt_fields, 34717 /* bits */ 30, 34718 /* flags */ 0, 34719 }, 34720 #endif /* chips */ 34721 34722 #if defined(BCM_53570_B0) 34723 { /* SOC_FORMAT_INT_ISW1_DROP_BCM53570_B0fmt */ 34724 /* format ISW1_DROPfmt */ 34725 /* nFields */ 31, 34726 /* *fields */ soc_ISW1_DROP_BCM53570_B0fmt_fields, 34727 /* bits */ 31, 34728 /* flags */ 0, 34729 }, 34730 #endif /* chips */ 34731 34732 #if defined(BCM_56142_A0) 34733 { /* SOC_FORMAT_INT_ISW1_DROP_BCM56142_A0fmt */ 34734 /* format ISW1_DROPfmt */ 34735 /* nFields */ 28, 34736 /* *fields */ soc_ISW1_DROP_BCM56334_A0fmt_fields, 34737 /* bits */ 28, 34738 /* flags */ 0, 34739 }, 34740 #endif /* chips */ 34741 34742 #if defined(BCM_56150_A0) 34743 { /* SOC_FORMAT_INT_ISW1_DROP_BCM56150_A0fmt */ 34744 /* format ISW1_DROPfmt */ 34745 /* nFields */ 28, 34746 /* *fields */ soc_ISW1_DROP_BCM56150_A0fmt_fields, 34747 /* bits */ 28, 34748 /* flags */ 0, 34749 }, 34750 #endif /* chips */ 34751 34752 #if defined(BCM_56160_A0) 34753 { /* SOC_FORMAT_INT_ISW1_DROP_BCM56160_A0fmt */ 34754 /* format ISW1_DROPfmt */ 34755 /* nFields */ 29, 34756 /* *fields */ soc_ISW1_DROP_BCM53400_A0fmt_fields, 34757 /* bits */ 29, 34758 /* flags */ 0, 34759 }, 34760 #endif /* chips */ 34761 34762 #if defined(BCM_56224_A0) 34763 { /* SOC_FORMAT_INT_ISW1_DROP_BCM56224_A0fmt */ 34764 /* format ISW1_DROPfmt */ 34765 /* nFields */ 17, 34766 /* *fields */ soc_ISW1_DROP_BCM56224_A0fmt_fields, 34767 /* bits */ 15, 34768 /* flags */ 0, 34769 }, 34770 #endif /* chips */ 34771 34772 #if defined(BCM_56224_B0) 34773 { /* SOC_FORMAT_INT_ISW1_DROP_BCM56224_B0fmt */ 34774 /* format ISW1_DROPfmt */ 34775 /* nFields */ 17, 34776 /* *fields */ soc_ISW1_DROP_BCM56224_A0fmt_fields, 34777 /* bits */ 15, 34778 /* flags */ 0, 34779 }, 34780 #endif /* chips */ 34781 34782 #if defined(BCM_56260_A0) 34783 { /* SOC_FORMAT_INT_ISW1_DROP_BCM56260_A0fmt */ 34784 /* format ISW1_DROPfmt */ 34785 /* nFields */ 45, 34786 /* *fields */ soc_ISW1_DROP_BCM56260_A0fmt_fields, 34787 /* bits */ 45, 34788 /* flags */ 0, 34789 }, 34790 #endif /* chips */ 34791 34792 #if defined(BCM_56260_B0) 34793 { /* SOC_FORMAT_INT_ISW1_DROP_BCM56260_B0fmt */ 34794 /* format ISW1_DROPfmt */ 34795 /* nFields */ 45, 34796 /* *fields */ soc_ISW1_DROP_BCM56260_A0fmt_fields, 34797 /* bits */ 45, 34798 /* flags */ 0, 34799 }, 34800 #endif /* chips */ 34801 34802 #if defined(BCM_56270_A0) 34803 { /* SOC_FORMAT_INT_ISW1_DROP_BCM56270_A0fmt */ 34804 /* format ISW1_DROPfmt */ 34805 /* nFields */ 44, 34806 /* *fields */ soc_ISW1_DROP_BCM56270_A0fmt_fields, 34807 /* bits */ 44, 34808 /* flags */ 0, 34809 }, 34810 #endif /* chips */ 34811 34812 #if defined(BCM_56314_A0) 34813 { /* SOC_FORMAT_INT_ISW1_DROP_BCM56314_A0fmt */ 34814 /* format ISW1_DROPfmt */ 34815 /* nFields */ 12, 34816 /* *fields */ soc_ISW1_DROP_BCM56504_B0fmt_fields, 34817 /* bits */ 12, 34818 /* flags */ 0, 34819 }, 34820 #endif /* chips */ 34821 34822 #if defined(BCM_56334_A0) 34823 { /* SOC_FORMAT_INT_ISW1_DROP_BCM56334_A0fmt */ 34824 /* format ISW1_DROPfmt */ 34825 /* nFields */ 28, 34826 /* *fields */ soc_ISW1_DROP_BCM56334_A0fmt_fields, 34827 /* bits */ 28, 34828 /* flags */ 0, 34829 }, 34830 #endif /* chips */ 34831 34832 #if defined(BCM_56334_B0) 34833 { /* SOC_FORMAT_INT_ISW1_DROP_BCM56334_B0fmt */ 34834 /* format ISW1_DROPfmt */ 34835 /* nFields */ 28, 34836 /* *fields */ soc_ISW1_DROP_BCM56334_A0fmt_fields, 34837 /* bits */ 28, 34838 /* flags */ 0, 34839 }, 34840 #endif /* chips */ 34841 34842 #if defined(BCM_56340_A0) 34843 { /* SOC_FORMAT_INT_ISW1_DROP_BCM56340_A0fmt */ 34844 /* format ISW1_DROPfmt */ 34845 /* nFields */ 47, 34846 /* *fields */ soc_ISW1_DROP_BCM56640_A0fmt_fields, 34847 /* bits */ 46, 34848 /* flags */ 0, 34849 }, 34850 #endif /* chips */ 34851 34852 #if defined(BCM_56440_A0) 34853 { /* SOC_FORMAT_INT_ISW1_DROP_BCM56440_A0fmt */ 34854 /* format ISW1_DROPfmt */ 34855 /* nFields */ 41, 34856 /* *fields */ soc_ISW1_DROP_BCM56440_A0fmt_fields, 34857 /* bits */ 41, 34858 /* flags */ 0, 34859 }, 34860 #endif /* chips */ 34861 34862 #if defined(BCM_56440_B0) 34863 { /* SOC_FORMAT_INT_ISW1_DROP_BCM56440_B0fmt */ 34864 /* format ISW1_DROPfmt */ 34865 /* nFields */ 41, 34866 /* *fields */ soc_ISW1_DROP_BCM56440_A0fmt_fields, 34867 /* bits */ 41, 34868 /* flags */ 0, 34869 }, 34870 #endif /* chips */ 34871 34872 #if defined(BCM_56450_A0) 34873 { /* SOC_FORMAT_INT_ISW1_DROP_BCM56450_A0fmt */ 34874 /* format ISW1_DROPfmt */ 34875 /* nFields */ 43, 34876 /* *fields */ soc_ISW1_DROP_BCM56450_A0fmt_fields, 34877 /* bits */ 43, 34878 /* flags */ 0, 34879 }, 34880 #endif /* chips */ 34881 34882 #if defined(BCM_56450_B0) 34883 { /* SOC_FORMAT_INT_ISW1_DROP_BCM56450_B0fmt */ 34884 /* format ISW1_DROPfmt */ 34885 /* nFields */ 43, 34886 /* *fields */ soc_ISW1_DROP_BCM56450_A0fmt_fields, 34887 /* bits */ 43, 34888 /* flags */ 0, 34889 }, 34890 #endif /* chips */ 34891 34892 #if defined(BCM_56450_B1) 34893 { /* SOC_FORMAT_INT_ISW1_DROP_BCM56450_B1fmt */ 34894 /* format ISW1_DROPfmt */ 34895 /* nFields */ 43, 34896 /* *fields */ soc_ISW1_DROP_BCM56450_A0fmt_fields, 34897 /* bits */ 43, 34898 /* flags */ 0, 34899 }, 34900 #endif /* chips */ 34901 34902 #if defined(BCM_56504_B0) 34903 { /* SOC_FORMAT_INT_ISW1_DROP_BCM56504_B0fmt */ 34904 /* format ISW1_DROPfmt */ 34905 /* nFields */ 12, 34906 /* *fields */ soc_ISW1_DROP_BCM56504_B0fmt_fields, 34907 /* bits */ 12, 34908 /* flags */ 0, 34909 }, 34910 #endif /* chips */ 34911 34912 #if defined(BCM_56514_A0) 34913 { /* SOC_FORMAT_INT_ISW1_DROP_BCM56514_A0fmt */ 34914 /* format ISW1_DROPfmt */ 34915 /* nFields */ 15, 34916 /* *fields */ soc_ISW1_DROP_BCM56514_A0fmt_fields, 34917 /* bits */ 15, 34918 /* flags */ 0, 34919 }, 34920 #endif /* chips */ 34921 34922 #if defined(BCM_56524_A0) 34923 { /* SOC_FORMAT_INT_ISW1_DROP_BCM56524_A0fmt */ 34924 /* format ISW1_DROPfmt */ 34925 /* nFields */ 28, 34926 /* *fields */ soc_ISW1_DROP_BCM56634_A0fmt_fields, 34927 /* bits */ 28, 34928 /* flags */ 0, 34929 }, 34930 #endif /* chips */ 34931 34932 #if defined(BCM_56524_B0) 34933 { /* SOC_FORMAT_INT_ISW1_DROP_BCM56524_B0fmt */ 34934 /* format ISW1_DROPfmt */ 34935 /* nFields */ 28, 34936 /* *fields */ soc_ISW1_DROP_BCM56634_A0fmt_fields, 34937 /* bits */ 28, 34938 /* flags */ 0, 34939 }, 34940 #endif /* chips */ 34941 34942 #if defined(BCM_56560_A0) 34943 { /* SOC_FORMAT_INT_ISW1_DROP_BCM56560_A0fmt */ 34944 /* format ISW1_DROPfmt */ 34945 /* nFields */ 39, 34946 /* *fields */ soc_ISW1_DROP_BCM56560_A0fmt_fields, 34947 /* bits */ 44, 34948 /* flags */ 0, 34949 }, 34950 #endif /* chips */ 34951 34952 #if defined(BCM_56560_B0) 34953 { /* SOC_FORMAT_INT_ISW1_DROP_BCM56560_B0fmt */ 34954 /* format ISW1_DROPfmt */ 34955 /* nFields */ 39, 34956 /* *fields */ soc_ISW1_DROP_BCM56560_A0fmt_fields, 34957 /* bits */ 44, 34958 /* flags */ 0, 34959 }, 34960 #endif /* chips */ 34961 34962 #if defined(BCM_56624_A0) 34963 { /* SOC_FORMAT_INT_ISW1_DROP_BCM56624_A0fmt */ 34964 /* format ISW1_DROPfmt */ 34965 /* nFields */ 20, 34966 /* *fields */ soc_ISW1_DROP_BCM56624_A0fmt_fields, 34967 /* bits */ 20, 34968 /* flags */ 0, 34969 }, 34970 #endif /* chips */ 34971 34972 #if defined(BCM_56624_B0) 34973 { /* SOC_FORMAT_INT_ISW1_DROP_BCM56624_B0fmt */ 34974 /* format ISW1_DROPfmt */ 34975 /* nFields */ 20, 34976 /* *fields */ soc_ISW1_DROP_BCM56624_A0fmt_fields, 34977 /* bits */ 20, 34978 /* flags */ 0, 34979 }, 34980 #endif /* chips */ 34981 34982 #if defined(BCM_56634_A0) 34983 { /* SOC_FORMAT_INT_ISW1_DROP_BCM56634_A0fmt */ 34984 /* format ISW1_DROPfmt */ 34985 /* nFields */ 28, 34986 /* *fields */ soc_ISW1_DROP_BCM56634_A0fmt_fields, 34987 /* bits */ 28, 34988 /* flags */ 0, 34989 }, 34990 #endif /* chips */ 34991 34992 #if defined(BCM_56634_B0) 34993 { /* SOC_FORMAT_INT_ISW1_DROP_BCM56634_B0fmt */ 34994 /* format ISW1_DROPfmt */ 34995 /* nFields */ 28, 34996 /* *fields */ soc_ISW1_DROP_BCM56634_A0fmt_fields, 34997 /* bits */ 28, 34998 /* flags */ 0, 34999 }, 35000 #endif /* chips */ 35001 35002 #if defined(BCM_56640_A0) 35003 { /* SOC_FORMAT_INT_ISW1_DROP_BCM56640_A0fmt */ 35004 /* format ISW1_DROPfmt */ 35005 /* nFields */ 47, 35006 /* *fields */ soc_ISW1_DROP_BCM56640_A0fmt_fields, 35007 /* bits */ 46, 35008 /* flags */ 0, 35009 }, 35010 #endif /* chips */ 35011 35012 #if defined(BCM_56670_A0) 35013 { /* SOC_FORMAT_INT_ISW1_DROP_BCM56670_A0fmt */ 35014 /* format ISW1_DROPfmt */ 35015 /* nFields */ 39, 35016 /* *fields */ soc_ISW1_DROP_BCM56560_A0fmt_fields, 35017 /* bits */ 44, 35018 /* flags */ 0, 35019 }, 35020 #endif /* chips */ 35021 35022 #if defined(BCM_56670_B0) 35023 { /* SOC_FORMAT_INT_ISW1_DROP_BCM56670_B0fmt */ 35024 /* format ISW1_DROPfmt */ 35025 /* nFields */ 39, 35026 /* *fields */ soc_ISW1_DROP_BCM56560_A0fmt_fields, 35027 /* bits */ 44, 35028 /* flags */ 0, 35029 }, 35030 #endif /* chips */ 35031 35032 #if defined(BCM_56680_A0) 35033 { /* SOC_FORMAT_INT_ISW1_DROP_BCM56680_A0fmt */ 35034 /* format ISW1_DROPfmt */ 35035 /* nFields */ 20, 35036 /* *fields */ soc_ISW1_DROP_BCM56624_A0fmt_fields, 35037 /* bits */ 20, 35038 /* flags */ 0, 35039 }, 35040 #endif /* chips */ 35041 35042 #if defined(BCM_56680_B0) 35043 { /* SOC_FORMAT_INT_ISW1_DROP_BCM56680_B0fmt */ 35044 /* format ISW1_DROPfmt */ 35045 /* nFields */ 20, 35046 /* *fields */ soc_ISW1_DROP_BCM56624_A0fmt_fields, 35047 /* bits */ 20, 35048 /* flags */ 0, 35049 }, 35050 #endif /* chips */ 35051 35052 #if defined(BCM_56685_A0) 35053 { /* SOC_FORMAT_INT_ISW1_DROP_BCM56685_A0fmt */ 35054 /* format ISW1_DROPfmt */ 35055 /* nFields */ 28, 35056 /* *fields */ soc_ISW1_DROP_BCM56634_A0fmt_fields, 35057 /* bits */ 28, 35058 /* flags */ 0, 35059 }, 35060 #endif /* chips */ 35061 35062 #if defined(BCM_56685_B0) 35063 { /* SOC_FORMAT_INT_ISW1_DROP_BCM56685_B0fmt */ 35064 /* format ISW1_DROPfmt */ 35065 /* nFields */ 28, 35066 /* *fields */ soc_ISW1_DROP_BCM56634_A0fmt_fields, 35067 /* bits */ 28, 35068 /* flags */ 0, 35069 }, 35070 #endif /* chips */ 35071 35072 #if defined(BCM_56725_A0) 35073 { /* SOC_FORMAT_INT_ISW1_DROP_BCM56725_A0fmt */ 35074 /* format ISW1_DROPfmt */ 35075 /* nFields */ 19, 35076 /* *fields */ soc_ISW1_DROP_BCM56820_A0fmt_fields, 35077 /* bits */ 19, 35078 /* flags */ 0, 35079 }, 35080 #endif /* chips */ 35081 35082 #if defined(BCM_56800_A0) 35083 { /* SOC_FORMAT_INT_ISW1_DROP_BCM56800_A0fmt */ 35084 /* format ISW1_DROPfmt */ 35085 /* nFields */ 14, 35086 /* *fields */ soc_ISW1_DROP_BCM56800_A0fmt_fields, 35087 /* bits */ 14, 35088 /* flags */ 0, 35089 }, 35090 #endif /* chips */ 35091 35092 #if defined(BCM_56820_A0) 35093 { /* SOC_FORMAT_INT_ISW1_DROP_BCM56820_A0fmt */ 35094 /* format ISW1_DROPfmt */ 35095 /* nFields */ 19, 35096 /* *fields */ soc_ISW1_DROP_BCM56820_A0fmt_fields, 35097 /* bits */ 19, 35098 /* flags */ 0, 35099 }, 35100 #endif /* chips */ 35101 35102 #if defined(BCM_56840_A0) 35103 { /* SOC_FORMAT_INT_ISW1_DROP_BCM56840_A0fmt */ 35104 /* format ISW1_DROPfmt */ 35105 /* nFields */ 35, 35106 /* *fields */ soc_ISW1_DROP_BCM56840_A0fmt_fields, 35107 /* bits */ 40, 35108 /* flags */ 0, 35109 }, 35110 #endif /* chips */ 35111 35112 #if defined(BCM_56840_B0) 35113 { /* SOC_FORMAT_INT_ISW1_DROP_BCM56840_B0fmt */ 35114 /* format ISW1_DROPfmt */ 35115 /* nFields */ 36, 35116 /* *fields */ soc_ISW1_DROP_BCM56840_B0fmt_fields, 35117 /* bits */ 41, 35118 /* flags */ 0, 35119 }, 35120 #endif /* chips */ 35121 35122 #if defined(BCM_56850_A0) 35123 { /* SOC_FORMAT_INT_ISW1_DROP_BCM56850_A0fmt */ 35124 /* format ISW1_DROPfmt */ 35125 /* nFields */ 38, 35126 /* *fields */ soc_ISW1_DROP_BCM56850_A0fmt_fields, 35127 /* bits */ 43, 35128 /* flags */ 0, 35129 }, 35130 #endif /* chips */ 35131 35132 #if defined(BCM_56860_A0) 35133 { /* SOC_FORMAT_INT_ISW1_DROP_BCM56860_A0fmt */ 35134 /* format ISW1_DROPfmt */ 35135 /* nFields */ 39, 35136 /* *fields */ soc_ISW1_DROP_BCM56860_A0fmt_fields, 35137 /* bits */ 44, 35138 /* flags */ 0, 35139 }, 35140 #endif /* chips */ 35141 35142 #if defined(BCM_56960_A0) 35143 { /* SOC_FORMAT_INT_ISW1_DROP_BCM56960_A0fmt */ 35144 /* format ISW1_DROPfmt */ 35145 /* nFields */ 42, 35146 /* *fields */ soc_ISW1_DROP_BCM56960_A0fmt_fields, 35147 /* bits */ 64, 35148 /* flags */ 0, 35149 }, 35150 #endif /* chips */ 35151 35152 #if defined(BCM_56965_A0) 35153 { /* SOC_FORMAT_INT_ISW1_DROP_BCM56965_A0fmt */ 35154 /* format ISW1_DROPfmt */ 35155 /* nFields */ 42, 35156 /* *fields */ soc_ISW1_DROP_BCM56960_A0fmt_fields, 35157 /* bits */ 64, 35158 /* flags */ 0, 35159 }, 35160 #endif /* chips */ 35161 35162 #if defined(BCM_56970_A0) 35163 { /* SOC_FORMAT_INT_ISW1_DROP_BCM56970_A0fmt */ 35164 /* format ISW1_DROPfmt */ 35165 /* nFields */ 42, 35166 /* *fields */ soc_ISW1_DROP_BCM56960_A0fmt_fields, 35167 /* bits */ 64, 35168 /* flags */ 0, 35169 }, 35170 #endif /* chips */ 35171 35172 #if defined(BCM_56224_A0) || defined(BCM_56224_B0) 35173 { /* SOC_FORMAT_INT_ISW1_PROTOCOL_PKTfmt */ 35174 /* format ISW1_PROTOCOL_PKTfmt */ 35175 /* nFields */ 8, 35176 /* *fields */ soc_ISW1_PROTOCOL_PKTfmt_fields, 35177 /* bits */ 8, 35178 /* flags */ 0, 35179 }, 35180 #endif /* chips */ 35181 35182 #if defined(BCM_53314_A0) 35183 { /* SOC_FORMAT_INT_ISW1_PROTOCOL_PKT_BCM53314_A0fmt */ 35184 /* format ISW1_PROTOCOL_PKTfmt */ 35185 /* nFields */ 11, 35186 /* *fields */ soc_ISW1_PROTOCOL_PKT_BCM53314_A0fmt_fields, 35187 /* bits */ 11, 35188 /* flags */ 0, 35189 }, 35190 #endif /* chips */ 35191 35192 #if defined(BCM_53324_A0) 35193 { /* SOC_FORMAT_INT_ISW1_PROTOCOL_PKT_BCM53324_A0fmt */ 35194 /* format ISW1_PROTOCOL_PKTfmt */ 35195 /* nFields */ 11, 35196 /* *fields */ soc_ISW1_PROTOCOL_PKT_BCM53314_A0fmt_fields, 35197 /* bits */ 11, 35198 /* flags */ 0, 35199 }, 35200 #endif /* chips */ 35201 35202 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) 35203 { /* SOC_FORMAT_INT_ISW1_TO_L2_MGMT_L2_BUSfmt */ 35204 /* format ISW1_TO_L2_MGMT_L2_BUSfmt */ 35205 /* nFields */ 5, 35206 /* *fields */ soc_ISW1_TO_L2_MGMT_L2_BUSfmt_fields, 35207 /* bits */ 116, 35208 /* flags */ 0, 35209 }, 35210 #endif /* chips */ 35211 35212 #if defined(BCM_56770_A0) 35213 { /* SOC_FORMAT_INT_ISW1_TO_L2_MGMT_L2_BUS_BCM56770_A0fmt */ 35214 /* format ISW1_TO_L2_MGMT_L2_BUSfmt */ 35215 /* nFields */ 6, 35216 /* *fields */ soc_ISW1_TO_L2_MGMT_L2_BUS_BCM56870_A0fmt_fields, 35217 /* bits */ 119, 35218 /* flags */ 0, 35219 }, 35220 #endif /* chips */ 35221 35222 #if defined(BCM_56870_A0) 35223 { /* SOC_FORMAT_INT_ISW1_TO_L2_MGMT_L2_BUS_BCM56870_A0fmt */ 35224 /* format ISW1_TO_L2_MGMT_L2_BUSfmt */ 35225 /* nFields */ 6, 35226 /* *fields */ soc_ISW1_TO_L2_MGMT_L2_BUS_BCM56870_A0fmt_fields, 35227 /* bits */ 119, 35228 /* flags */ 0, 35229 }, 35230 #endif /* chips */ 35231 35232 #if defined(BCM_56970_A0) 35233 { /* SOC_FORMAT_INT_ISW1_TO_L2_MGMT_L2_BUS_BCM56970_A0fmt */ 35234 /* format ISW1_TO_L2_MGMT_L2_BUSfmt */ 35235 /* nFields */ 6, 35236 /* *fields */ soc_ISW1_TO_L2_MGMT_L2_BUS_BCM56970_A0fmt_fields, 35237 /* bits */ 116, 35238 /* flags */ 0, 35239 }, 35240 #endif /* chips */ 35241 35242 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 35243 defined(BCM_56870_A0) 35244 { /* SOC_FORMAT_INT_ISW2_DOPfmt */ 35245 /* format ISW2_DOPfmt */ 35246 /* nFields */ 18, 35247 /* *fields */ soc_ISW2_DOPfmt_fields, 35248 /* bits */ 256, 35249 /* flags */ 0, 35250 }, 35251 #endif /* chips */ 35252 35253 #if defined(BCM_56870_A0) 35254 { /* SOC_FORMAT_INT_ISW2_TO_ICFG_BUSfmt */ 35255 /* format ISW2_TO_ICFG_BUSfmt */ 35256 /* nFields */ 2, 35257 /* *fields */ soc_ISW2_TO_IPARS_BUS_BCM56960_A0fmt_fields, 35258 /* bits */ 9, 35259 /* flags */ 0, 35260 }, 35261 #endif /* chips */ 35262 35263 #if defined(BCM_56370_A0) 35264 { /* SOC_FORMAT_INT_ISW2_TO_ICFG_BUS_BCM56370_A0fmt */ 35265 /* format ISW2_TO_ICFG_BUSfmt */ 35266 /* nFields */ 2, 35267 /* *fields */ soc_ISW2_TO_IPARS_BUS_BCM56960_A0fmt_fields, 35268 /* bits */ 9, 35269 /* flags */ 0, 35270 }, 35271 #endif /* chips */ 35272 35273 #if defined(BCM_56770_A0) 35274 { /* SOC_FORMAT_INT_ISW2_TO_ICFG_BUS_BCM56770_A0fmt */ 35275 /* format ISW2_TO_ICFG_BUSfmt */ 35276 /* nFields */ 2, 35277 /* *fields */ soc_ISW2_TO_IPARS_BUS_BCM56960_A0fmt_fields, 35278 /* bits */ 9, 35279 /* flags */ 0, 35280 }, 35281 #endif /* chips */ 35282 35283 #if defined(BCM_56840_A0) || defined(BCM_56840_B0) 35284 { /* SOC_FORMAT_INT_ISW2_TO_IPARS_BUSfmt */ 35285 /* format ISW2_TO_IPARS_BUSfmt */ 35286 /* nFields */ 2, 35287 /* *fields */ soc_ISW2_TO_IPARS_BUSfmt_fields, 35288 /* bits */ 9, 35289 /* flags */ 0, 35290 }, 35291 #endif /* chips */ 35292 35293 #if defined(BCM_53400_A0) 35294 { /* SOC_FORMAT_INT_ISW2_TO_IPARS_BUS_BCM53400_A0fmt */ 35295 /* format ISW2_TO_IPARS_BUSfmt */ 35296 /* nFields */ 1, 35297 /* *fields */ soc_ISW2_TO_IPARS_BUS_BCM53400_A0fmt_fields, 35298 /* bits */ 1, 35299 /* flags */ 0, 35300 }, 35301 #endif /* chips */ 35302 35303 #if defined(BCM_53540_A0) 35304 { /* SOC_FORMAT_INT_ISW2_TO_IPARS_BUS_BCM53540_A0fmt */ 35305 /* format ISW2_TO_IPARS_BUSfmt */ 35306 /* nFields */ 1, 35307 /* *fields */ soc_ISW2_TO_IPARS_BUS_BCM53400_A0fmt_fields, 35308 /* bits */ 1, 35309 /* flags */ 0, 35310 }, 35311 #endif /* chips */ 35312 35313 #if defined(BCM_53570_A0) 35314 { /* SOC_FORMAT_INT_ISW2_TO_IPARS_BUS_BCM53570_A0fmt */ 35315 /* format ISW2_TO_IPARS_BUSfmt */ 35316 /* nFields */ 1, 35317 /* *fields */ soc_ISW2_TO_IPARS_BUS_BCM53400_A0fmt_fields, 35318 /* bits */ 1, 35319 /* flags */ 0, 35320 }, 35321 #endif /* chips */ 35322 35323 #if defined(BCM_53570_B0) 35324 { /* SOC_FORMAT_INT_ISW2_TO_IPARS_BUS_BCM53570_B0fmt */ 35325 /* format ISW2_TO_IPARS_BUSfmt */ 35326 /* nFields */ 1, 35327 /* *fields */ soc_ISW2_TO_IPARS_BUS_BCM53400_A0fmt_fields, 35328 /* bits */ 1, 35329 /* flags */ 0, 35330 }, 35331 #endif /* chips */ 35332 35333 #if defined(BCM_56150_A0) 35334 { /* SOC_FORMAT_INT_ISW2_TO_IPARS_BUS_BCM56150_A0fmt */ 35335 /* format ISW2_TO_IPARS_BUSfmt */ 35336 /* nFields */ 1, 35337 /* *fields */ soc_ISW2_TO_IPARS_BUS_BCM56640_A0fmt_fields, 35338 /* bits */ 1, 35339 /* flags */ 0, 35340 }, 35341 #endif /* chips */ 35342 35343 #if defined(BCM_56160_A0) 35344 { /* SOC_FORMAT_INT_ISW2_TO_IPARS_BUS_BCM56160_A0fmt */ 35345 /* format ISW2_TO_IPARS_BUSfmt */ 35346 /* nFields */ 1, 35347 /* *fields */ soc_ISW2_TO_IPARS_BUS_BCM53400_A0fmt_fields, 35348 /* bits */ 1, 35349 /* flags */ 0, 35350 }, 35351 #endif /* chips */ 35352 35353 #if defined(BCM_56260_A0) 35354 { /* SOC_FORMAT_INT_ISW2_TO_IPARS_BUS_BCM56260_A0fmt */ 35355 /* format ISW2_TO_IPARS_BUSfmt */ 35356 /* nFields */ 1, 35357 /* *fields */ soc_ISW2_TO_IPARS_BUS_BCM53400_A0fmt_fields, 35358 /* bits */ 1, 35359 /* flags */ 0, 35360 }, 35361 #endif /* chips */ 35362 35363 #if defined(BCM_56260_B0) 35364 { /* SOC_FORMAT_INT_ISW2_TO_IPARS_BUS_BCM56260_B0fmt */ 35365 /* format ISW2_TO_IPARS_BUSfmt */ 35366 /* nFields */ 1, 35367 /* *fields */ soc_ISW2_TO_IPARS_BUS_BCM53400_A0fmt_fields, 35368 /* bits */ 1, 35369 /* flags */ 0, 35370 }, 35371 #endif /* chips */ 35372 35373 #if defined(BCM_56270_A0) 35374 { /* SOC_FORMAT_INT_ISW2_TO_IPARS_BUS_BCM56270_A0fmt */ 35375 /* format ISW2_TO_IPARS_BUSfmt */ 35376 /* nFields */ 1, 35377 /* *fields */ soc_ISW2_TO_IPARS_BUS_BCM53400_A0fmt_fields, 35378 /* bits */ 1, 35379 /* flags */ 0, 35380 }, 35381 #endif /* chips */ 35382 35383 #if defined(BCM_56340_A0) 35384 { /* SOC_FORMAT_INT_ISW2_TO_IPARS_BUS_BCM56340_A0fmt */ 35385 /* format ISW2_TO_IPARS_BUSfmt */ 35386 /* nFields */ 1, 35387 /* *fields */ soc_ISW2_TO_IPARS_BUS_BCM56640_A0fmt_fields, 35388 /* bits */ 1, 35389 /* flags */ 0, 35390 }, 35391 #endif /* chips */ 35392 35393 #if defined(BCM_56440_A0) 35394 { /* SOC_FORMAT_INT_ISW2_TO_IPARS_BUS_BCM56440_A0fmt */ 35395 /* format ISW2_TO_IPARS_BUSfmt */ 35396 /* nFields */ 2, 35397 /* *fields */ soc_ISW2_TO_IPARS_BUSfmt_fields, 35398 /* bits */ 9, 35399 /* flags */ 0, 35400 }, 35401 #endif /* chips */ 35402 35403 #if defined(BCM_56440_B0) 35404 { /* SOC_FORMAT_INT_ISW2_TO_IPARS_BUS_BCM56440_B0fmt */ 35405 /* format ISW2_TO_IPARS_BUSfmt */ 35406 /* nFields */ 2, 35407 /* *fields */ soc_ISW2_TO_IPARS_BUSfmt_fields, 35408 /* bits */ 9, 35409 /* flags */ 0, 35410 }, 35411 #endif /* chips */ 35412 35413 #if defined(BCM_56450_A0) 35414 { /* SOC_FORMAT_INT_ISW2_TO_IPARS_BUS_BCM56450_A0fmt */ 35415 /* format ISW2_TO_IPARS_BUSfmt */ 35416 /* nFields */ 2, 35417 /* *fields */ soc_ISW2_TO_IPARS_BUS_BCM56450_A0fmt_fields, 35418 /* bits */ 9, 35419 /* flags */ 0, 35420 }, 35421 #endif /* chips */ 35422 35423 #if defined(BCM_56450_B0) 35424 { /* SOC_FORMAT_INT_ISW2_TO_IPARS_BUS_BCM56450_B0fmt */ 35425 /* format ISW2_TO_IPARS_BUSfmt */ 35426 /* nFields */ 2, 35427 /* *fields */ soc_ISW2_TO_IPARS_BUS_BCM56450_A0fmt_fields, 35428 /* bits */ 9, 35429 /* flags */ 0, 35430 }, 35431 #endif /* chips */ 35432 35433 #if defined(BCM_56450_B1) 35434 { /* SOC_FORMAT_INT_ISW2_TO_IPARS_BUS_BCM56450_B1fmt */ 35435 /* format ISW2_TO_IPARS_BUSfmt */ 35436 /* nFields */ 2, 35437 /* *fields */ soc_ISW2_TO_IPARS_BUS_BCM56450_A0fmt_fields, 35438 /* bits */ 9, 35439 /* flags */ 0, 35440 }, 35441 #endif /* chips */ 35442 35443 #if defined(BCM_56560_A0) 35444 { /* SOC_FORMAT_INT_ISW2_TO_IPARS_BUS_BCM56560_A0fmt */ 35445 /* format ISW2_TO_IPARS_BUSfmt */ 35446 /* nFields */ 1, 35447 /* *fields */ soc_ISW2_TO_IPARS_BUS_BCM53400_A0fmt_fields, 35448 /* bits */ 1, 35449 /* flags */ 0, 35450 }, 35451 #endif /* chips */ 35452 35453 #if defined(BCM_56560_B0) 35454 { /* SOC_FORMAT_INT_ISW2_TO_IPARS_BUS_BCM56560_B0fmt */ 35455 /* format ISW2_TO_IPARS_BUSfmt */ 35456 /* nFields */ 1, 35457 /* *fields */ soc_ISW2_TO_IPARS_BUS_BCM53400_A0fmt_fields, 35458 /* bits */ 1, 35459 /* flags */ 0, 35460 }, 35461 #endif /* chips */ 35462 35463 #if defined(BCM_56640_A0) 35464 { /* SOC_FORMAT_INT_ISW2_TO_IPARS_BUS_BCM56640_A0fmt */ 35465 /* format ISW2_TO_IPARS_BUSfmt */ 35466 /* nFields */ 1, 35467 /* *fields */ soc_ISW2_TO_IPARS_BUS_BCM56640_A0fmt_fields, 35468 /* bits */ 1, 35469 /* flags */ 0, 35470 }, 35471 #endif /* chips */ 35472 35473 #if defined(BCM_56670_A0) 35474 { /* SOC_FORMAT_INT_ISW2_TO_IPARS_BUS_BCM56670_A0fmt */ 35475 /* format ISW2_TO_IPARS_BUSfmt */ 35476 /* nFields */ 1, 35477 /* *fields */ soc_ISW2_TO_IPARS_BUS_BCM53400_A0fmt_fields, 35478 /* bits */ 1, 35479 /* flags */ 0, 35480 }, 35481 #endif /* chips */ 35482 35483 #if defined(BCM_56670_B0) 35484 { /* SOC_FORMAT_INT_ISW2_TO_IPARS_BUS_BCM56670_B0fmt */ 35485 /* format ISW2_TO_IPARS_BUSfmt */ 35486 /* nFields */ 1, 35487 /* *fields */ soc_ISW2_TO_IPARS_BUS_BCM53400_A0fmt_fields, 35488 /* bits */ 1, 35489 /* flags */ 0, 35490 }, 35491 #endif /* chips */ 35492 35493 #if defined(BCM_56850_A0) 35494 { /* SOC_FORMAT_INT_ISW2_TO_IPARS_BUS_BCM56850_A0fmt */ 35495 /* format ISW2_TO_IPARS_BUSfmt */ 35496 /* nFields */ 1, 35497 /* *fields */ soc_ISW2_TO_IPARS_BUS_BCM56640_A0fmt_fields, 35498 /* bits */ 1, 35499 /* flags */ 0, 35500 }, 35501 #endif /* chips */ 35502 35503 #if defined(BCM_56860_A0) 35504 { /* SOC_FORMAT_INT_ISW2_TO_IPARS_BUS_BCM56860_A0fmt */ 35505 /* format ISW2_TO_IPARS_BUSfmt */ 35506 /* nFields */ 1, 35507 /* *fields */ soc_ISW2_TO_IPARS_BUS_BCM56640_A0fmt_fields, 35508 /* bits */ 1, 35509 /* flags */ 0, 35510 }, 35511 #endif /* chips */ 35512 35513 #if defined(BCM_56960_A0) 35514 { /* SOC_FORMAT_INT_ISW2_TO_IPARS_BUS_BCM56960_A0fmt */ 35515 /* format ISW2_TO_IPARS_BUSfmt */ 35516 /* nFields */ 2, 35517 /* *fields */ soc_ISW2_TO_IPARS_BUS_BCM56960_A0fmt_fields, 35518 /* bits */ 9, 35519 /* flags */ 0, 35520 }, 35521 #endif /* chips */ 35522 35523 #if defined(BCM_56965_A0) 35524 { /* SOC_FORMAT_INT_ISW2_TO_IPARS_BUS_BCM56965_A0fmt */ 35525 /* format ISW2_TO_IPARS_BUSfmt */ 35526 /* nFields */ 2, 35527 /* *fields */ soc_ISW2_TO_IPARS_BUS_BCM56960_A0fmt_fields, 35528 /* bits */ 9, 35529 /* flags */ 0, 35530 }, 35531 #endif /* chips */ 35532 35533 #if defined(BCM_56870_A0) 35534 { /* SOC_FORMAT_INT_ISW3_DOPfmt */ 35535 /* format ISW3_DOPfmt */ 35536 /* nFields */ 60, 35537 /* *fields */ soc_ISW3_DOPfmt_fields, 35538 /* bits */ 1088, 35539 /* flags */ 0, 35540 }, 35541 #endif /* chips */ 35542 35543 #if defined(BCM_56370_A0) 35544 { /* SOC_FORMAT_INT_ISW3_DOP_BCM56370_A0fmt */ 35545 /* format ISW3_DOPfmt */ 35546 /* nFields */ 60, 35547 /* *fields */ soc_ISW3_DOP_BCM56370_A0fmt_fields, 35548 /* bits */ 1024, 35549 /* flags */ 0, 35550 }, 35551 #endif /* chips */ 35552 35553 #if defined(BCM_56770_A0) 35554 { /* SOC_FORMAT_INT_ISW3_DOP_BCM56770_A0fmt */ 35555 /* format ISW3_DOPfmt */ 35556 /* nFields */ 60, 35557 /* *fields */ soc_ISW3_DOP_BCM56770_A0fmt_fields, 35558 /* bits */ 1120, 35559 /* flags */ 0, 35560 }, 35561 #endif /* chips */ 35562 35563 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) || \ 35564 defined(BCM_56970_A0) 35565 { /* SOC_FORMAT_INT_ISW3_DROPfmt */ 35566 /* format ISW3_DROPfmt */ 35567 /* nFields */ 26, 35568 /* *fields */ soc_ISW3_DROPfmt_fields, 35569 /* bits */ 64, 35570 /* flags */ 0, 35571 }, 35572 #endif /* chips */ 35573 35574 #if defined(BCM_56370_A0) 35575 { /* SOC_FORMAT_INT_ISW3_DROP_BCM56370_A0fmt */ 35576 /* format ISW3_DROPfmt */ 35577 /* nFields */ 2, 35578 /* *fields */ soc_ISW3_DROP_BCM56370_A0fmt_fields, 35579 /* bits */ 67, 35580 /* flags */ 0, 35581 }, 35582 #endif /* chips */ 35583 35584 #if defined(BCM_56770_A0) 35585 { /* SOC_FORMAT_INT_ISW3_DROP_BCM56770_A0fmt */ 35586 /* format ISW3_DROPfmt */ 35587 /* nFields */ 2, 35588 /* *fields */ soc_ISW3_DROP_BCM56870_A0fmt_fields, 35589 /* bits */ 64, 35590 /* flags */ 0, 35591 }, 35592 #endif /* chips */ 35593 35594 #if defined(BCM_56870_A0) 35595 { /* SOC_FORMAT_INT_ISW3_DROP_BCM56870_A0fmt */ 35596 /* format ISW3_DROPfmt */ 35597 /* nFields */ 2, 35598 /* *fields */ soc_ISW3_DROP_BCM56870_A0fmt_fields, 35599 /* bits */ 64, 35600 /* flags */ 0, 35601 }, 35602 #endif /* chips */ 35603 35604 #if defined(BCM_56960_A0) 35605 { /* SOC_FORMAT_INT_ISW3_TO_IPARS_BUSfmt */ 35606 /* format ISW3_TO_IPARS_BUSfmt */ 35607 /* nFields */ 1, 35608 /* *fields */ soc_ISW2_TO_IPARS_BUS_BCM53400_A0fmt_fields, 35609 /* bits */ 1, 35610 /* flags */ 0, 35611 }, 35612 #endif /* chips */ 35613 35614 #if defined(BCM_56370_A0) 35615 { /* SOC_FORMAT_INT_ISW3_TO_IPARS_BUS_BCM56370_A0fmt */ 35616 /* format ISW3_TO_IPARS_BUSfmt */ 35617 /* nFields */ 1, 35618 /* *fields */ soc_ISW2_TO_IPARS_BUS_BCM53400_A0fmt_fields, 35619 /* bits */ 1, 35620 /* flags */ 0, 35621 }, 35622 #endif /* chips */ 35623 35624 #if defined(BCM_56770_A0) 35625 { /* SOC_FORMAT_INT_ISW3_TO_IPARS_BUS_BCM56770_A0fmt */ 35626 /* format ISW3_TO_IPARS_BUSfmt */ 35627 /* nFields */ 1, 35628 /* *fields */ soc_ISW2_TO_IPARS_BUS_BCM53400_A0fmt_fields, 35629 /* bits */ 1, 35630 /* flags */ 0, 35631 }, 35632 #endif /* chips */ 35633 35634 #if defined(BCM_56870_A0) 35635 { /* SOC_FORMAT_INT_ISW3_TO_IPARS_BUS_BCM56870_A0fmt */ 35636 /* format ISW3_TO_IPARS_BUSfmt */ 35637 /* nFields */ 1, 35638 /* *fields */ soc_ISW2_TO_IPARS_BUS_BCM53400_A0fmt_fields, 35639 /* bits */ 1, 35640 /* flags */ 0, 35641 }, 35642 #endif /* chips */ 35643 35644 #if defined(BCM_56965_A0) 35645 { /* SOC_FORMAT_INT_ISW3_TO_IPARS_BUS_BCM56965_A0fmt */ 35646 /* format ISW3_TO_IPARS_BUSfmt */ 35647 /* nFields */ 1, 35648 /* *fields */ soc_ISW2_TO_IPARS_BUS_BCM53400_A0fmt_fields, 35649 /* bits */ 1, 35650 /* flags */ 0, 35651 }, 35652 #endif /* chips */ 35653 35654 #if defined(BCM_56970_A0) 35655 { /* SOC_FORMAT_INT_ISW3_TO_ISW4_BUSfmt */ 35656 /* format ISW3_TO_ISW4_BUSfmt */ 35657 /* nFields */ 7, 35658 /* *fields */ soc_ISW3_TO_ISW4_BUSfmt_fields, 35659 /* bits */ 988, 35660 /* flags */ 0, 35661 }, 35662 #endif /* chips */ 35663 35664 #if defined(BCM_56370_A0) 35665 { /* SOC_FORMAT_INT_ISW3_TO_ISW4_BUS_BCM56370_A0fmt */ 35666 /* format ISW3_TO_ISW4_BUSfmt */ 35667 /* nFields */ 4, 35668 /* *fields */ soc_ISW3_TO_ISW4_BUS_BCM56870_A0fmt_fields, 35669 /* bits */ 1015, 35670 /* flags */ 0, 35671 }, 35672 #endif /* chips */ 35673 35674 #if defined(BCM_56770_A0) 35675 { /* SOC_FORMAT_INT_ISW3_TO_ISW4_BUS_BCM56770_A0fmt */ 35676 /* format ISW3_TO_ISW4_BUSfmt */ 35677 /* nFields */ 4, 35678 /* *fields */ soc_ISW3_TO_ISW4_BUS_BCM56870_A0fmt_fields, 35679 /* bits */ 1015, 35680 /* flags */ 0, 35681 }, 35682 #endif /* chips */ 35683 35684 #if defined(BCM_56870_A0) 35685 { /* SOC_FORMAT_INT_ISW3_TO_ISW4_BUS_BCM56870_A0fmt */ 35686 /* format ISW3_TO_ISW4_BUSfmt */ 35687 /* nFields */ 4, 35688 /* *fields */ soc_ISW3_TO_ISW4_BUS_BCM56870_A0fmt_fields, 35689 /* bits */ 1015, 35690 /* flags */ 0, 35691 }, 35692 #endif /* chips */ 35693 35694 #if defined(BCM_56970_A0) 35695 { /* SOC_FORMAT_INT_ISW4_CELL_QUEUES_DATAfmt */ 35696 /* format ISW4_CELL_QUEUES_DATAfmt */ 35697 /* nFields */ 7, 35698 /* *fields */ soc_ISW4_CELL_QUEUES_DATAfmt_fields, 35699 /* bits */ 27, 35700 /* flags */ 0, 35701 }, 35702 #endif /* chips */ 35703 35704 #if defined(BCM_56370_A0) 35705 { /* SOC_FORMAT_INT_ISW4_CELL_QUEUES_DATA_BCM56370_A0fmt */ 35706 /* format ISW4_CELL_QUEUES_DATAfmt */ 35707 /* nFields */ 7, 35708 /* *fields */ soc_ISW4_CELL_QUEUES_DATA_BCM56870_A0fmt_fields, 35709 /* bits */ 27, 35710 /* flags */ 0, 35711 }, 35712 #endif /* chips */ 35713 35714 #if defined(BCM_56770_A0) 35715 { /* SOC_FORMAT_INT_ISW4_CELL_QUEUES_DATA_BCM56770_A0fmt */ 35716 /* format ISW4_CELL_QUEUES_DATAfmt */ 35717 /* nFields */ 7, 35718 /* *fields */ soc_ISW4_CELL_QUEUES_DATA_BCM56870_A0fmt_fields, 35719 /* bits */ 27, 35720 /* flags */ 0, 35721 }, 35722 #endif /* chips */ 35723 35724 #if defined(BCM_56870_A0) 35725 { /* SOC_FORMAT_INT_ISW4_CELL_QUEUES_DATA_BCM56870_A0fmt */ 35726 /* format ISW4_CELL_QUEUES_DATAfmt */ 35727 /* nFields */ 7, 35728 /* *fields */ soc_ISW4_CELL_QUEUES_DATA_BCM56870_A0fmt_fields, 35729 /* bits */ 27, 35730 /* flags */ 0, 35731 }, 35732 #endif /* chips */ 35733 35734 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) || \ 35735 defined(BCM_56970_A0) 35736 { /* SOC_FORMAT_INT_ISW4_SLOT_PIPELINE_DATAfmt */ 35737 /* format ISW4_SLOT_PIPELINE_DATAfmt */ 35738 /* nFields */ 3, 35739 /* *fields */ soc_ISW4_SLOT_PIPELINE_DATAfmt_fields, 35740 /* bits */ 13, 35741 /* flags */ 0, 35742 }, 35743 #endif /* chips */ 35744 35745 #if defined(BCM_56370_A0) 35746 { /* SOC_FORMAT_INT_ISW4_SLOT_PIPELINE_DATA_BCM56370_A0fmt */ 35747 /* format ISW4_SLOT_PIPELINE_DATAfmt */ 35748 /* nFields */ 4, 35749 /* *fields */ soc_ISW4_SLOT_PIPELINE_DATA_BCM56370_A0fmt_fields, 35750 /* bits */ 13, 35751 /* flags */ 0, 35752 }, 35753 #endif /* chips */ 35754 35755 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 35756 { /* SOC_FORMAT_INT_ISW_TO_IPOST_BUSfmt */ 35757 /* format ISW_TO_IPOST_BUSfmt */ 35758 /* nFields */ 7, 35759 /* *fields */ soc_ISW_TO_IPOST_BUSfmt_fields, 35760 /* bits */ 779, 35761 /* flags */ 0, 35762 }, 35763 #endif /* chips */ 35764 35765 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 35766 defined(BCM_56870_A0) 35767 { /* SOC_FORMAT_INT_ITAG_ACTION_SETfmt */ 35768 /* format ITAG_ACTION_SETfmt */ 35769 /* nFields */ 6, 35770 /* *fields */ soc_ITAG_ACTION_SETfmt_fields, 35771 /* bits */ 20, 35772 /* flags */ 0, 35773 }, 35774 #endif /* chips */ 35775 35776 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 35777 defined(BCM_56870_A0) 35778 { /* SOC_FORMAT_INT_ITAG_HDRfmt */ 35779 /* format ITAG_HDRfmt */ 35780 /* nFields */ 5, 35781 /* *fields */ soc_ITAG_HDRfmt_fields, 35782 /* bits */ 32, 35783 /* flags */ 0, 35784 }, 35785 #endif /* chips */ 35786 35787 #if defined(BCM_56440_A0) 35788 { /* SOC_FORMAT_INT_ITE_TO_EMC_WR_INFOfmt */ 35789 /* format ITE_TO_EMC_WR_INFOfmt */ 35790 /* nFields */ 8, 35791 /* *fields */ soc_ITE_TO_EMC_WR_INFOfmt_fields, 35792 /* bits */ 42, 35793 /* flags */ 0, 35794 }, 35795 #endif /* chips */ 35796 35797 #if defined(BCM_56260_A0) 35798 { /* SOC_FORMAT_INT_ITE_TO_EMC_WR_INFO_BCM56260_A0fmt */ 35799 /* format ITE_TO_EMC_WR_INFOfmt */ 35800 /* nFields */ 7, 35801 /* *fields */ soc_ITE_TO_EMC_WR_INFO_BCM56260_A0fmt_fields, 35802 /* bits */ 38, 35803 /* flags */ 0, 35804 }, 35805 #endif /* chips */ 35806 35807 #if defined(BCM_56260_B0) 35808 { /* SOC_FORMAT_INT_ITE_TO_EMC_WR_INFO_BCM56260_B0fmt */ 35809 /* format ITE_TO_EMC_WR_INFOfmt */ 35810 /* nFields */ 7, 35811 /* *fields */ soc_ITE_TO_EMC_WR_INFO_BCM56260_A0fmt_fields, 35812 /* bits */ 38, 35813 /* flags */ 0, 35814 }, 35815 #endif /* chips */ 35816 35817 #if defined(BCM_56270_A0) 35818 { /* SOC_FORMAT_INT_ITE_TO_EMC_WR_INFO_BCM56270_A0fmt */ 35819 /* format ITE_TO_EMC_WR_INFOfmt */ 35820 /* nFields */ 7, 35821 /* *fields */ soc_ITE_TO_EMC_WR_INFO_BCM56260_A0fmt_fields, 35822 /* bits */ 38, 35823 /* flags */ 0, 35824 }, 35825 #endif /* chips */ 35826 35827 #if defined(BCM_56440_B0) 35828 { /* SOC_FORMAT_INT_ITE_TO_EMC_WR_INFO_BCM56440_B0fmt */ 35829 /* format ITE_TO_EMC_WR_INFOfmt */ 35830 /* nFields */ 8, 35831 /* *fields */ soc_ITE_TO_EMC_WR_INFOfmt_fields, 35832 /* bits */ 42, 35833 /* flags */ 0, 35834 }, 35835 #endif /* chips */ 35836 35837 #if defined(BCM_56450_A0) 35838 { /* SOC_FORMAT_INT_ITE_TO_EMC_WR_INFO_BCM56450_A0fmt */ 35839 /* format ITE_TO_EMC_WR_INFOfmt */ 35840 /* nFields */ 7, 35841 /* *fields */ soc_ITE_TO_EMC_WR_INFO_BCM56450_A0fmt_fields, 35842 /* bits */ 43, 35843 /* flags */ 0, 35844 }, 35845 #endif /* chips */ 35846 35847 #if defined(BCM_56450_B0) 35848 { /* SOC_FORMAT_INT_ITE_TO_EMC_WR_INFO_BCM56450_B0fmt */ 35849 /* format ITE_TO_EMC_WR_INFOfmt */ 35850 /* nFields */ 7, 35851 /* *fields */ soc_ITE_TO_EMC_WR_INFO_BCM56450_A0fmt_fields, 35852 /* bits */ 43, 35853 /* flags */ 0, 35854 }, 35855 #endif /* chips */ 35856 35857 #if defined(BCM_56450_B1) 35858 { /* SOC_FORMAT_INT_ITE_TO_EMC_WR_INFO_BCM56450_B1fmt */ 35859 /* format ITE_TO_EMC_WR_INFOfmt */ 35860 /* nFields */ 7, 35861 /* *fields */ soc_ITE_TO_EMC_WR_INFO_BCM56450_A0fmt_fields, 35862 /* bits */ 43, 35863 /* flags */ 0, 35864 }, 35865 #endif /* chips */ 35866 35867 #if defined(BCM_56440_A0) 35868 { /* SOC_FORMAT_INT_ITE_TO_RQE_EXT_INFOfmt */ 35869 /* format ITE_TO_RQE_EXT_INFOfmt */ 35870 /* nFields */ 3, 35871 /* *fields */ soc_ENQ_TO_RQE_INT_INFOfmt_fields, 35872 /* bits */ 29, 35873 /* flags */ 0, 35874 }, 35875 #endif /* chips */ 35876 35877 #if defined(BCM_56260_A0) 35878 { /* SOC_FORMAT_INT_ITE_TO_RQE_EXT_INFO_BCM56260_A0fmt */ 35879 /* format ITE_TO_RQE_EXT_INFOfmt */ 35880 /* nFields */ 3, 35881 /* *fields */ soc_ENQ_TO_RQE_INT_INFO_BCM56260_A0fmt_fields, 35882 /* bits */ 28, 35883 /* flags */ 0, 35884 }, 35885 #endif /* chips */ 35886 35887 #if defined(BCM_56260_B0) 35888 { /* SOC_FORMAT_INT_ITE_TO_RQE_EXT_INFO_BCM56260_B0fmt */ 35889 /* format ITE_TO_RQE_EXT_INFOfmt */ 35890 /* nFields */ 3, 35891 /* *fields */ soc_ENQ_TO_RQE_INT_INFO_BCM56260_A0fmt_fields, 35892 /* bits */ 28, 35893 /* flags */ 0, 35894 }, 35895 #endif /* chips */ 35896 35897 #if defined(BCM_56270_A0) 35898 { /* SOC_FORMAT_INT_ITE_TO_RQE_EXT_INFO_BCM56270_A0fmt */ 35899 /* format ITE_TO_RQE_EXT_INFOfmt */ 35900 /* nFields */ 3, 35901 /* *fields */ soc_ENQ_TO_RQE_INT_INFO_BCM56260_A0fmt_fields, 35902 /* bits */ 28, 35903 /* flags */ 0, 35904 }, 35905 #endif /* chips */ 35906 35907 #if defined(BCM_56440_B0) 35908 { /* SOC_FORMAT_INT_ITE_TO_RQE_EXT_INFO_BCM56440_B0fmt */ 35909 /* format ITE_TO_RQE_EXT_INFOfmt */ 35910 /* nFields */ 3, 35911 /* *fields */ soc_ENQ_TO_RQE_INT_INFOfmt_fields, 35912 /* bits */ 29, 35913 /* flags */ 0, 35914 }, 35915 #endif /* chips */ 35916 35917 #if defined(BCM_56450_A0) 35918 { /* SOC_FORMAT_INT_ITE_TO_RQE_EXT_INFO_BCM56450_A0fmt */ 35919 /* format ITE_TO_RQE_EXT_INFOfmt */ 35920 /* nFields */ 3, 35921 /* *fields */ soc_ENQ_TO_RQE_INT_INFO_BCM56450_A0fmt_fields, 35922 /* bits */ 29, 35923 /* flags */ 0, 35924 }, 35925 #endif /* chips */ 35926 35927 #if defined(BCM_56450_B0) 35928 { /* SOC_FORMAT_INT_ITE_TO_RQE_EXT_INFO_BCM56450_B0fmt */ 35929 /* format ITE_TO_RQE_EXT_INFOfmt */ 35930 /* nFields */ 3, 35931 /* *fields */ soc_ENQ_TO_RQE_INT_INFO_BCM56450_A0fmt_fields, 35932 /* bits */ 29, 35933 /* flags */ 0, 35934 }, 35935 #endif /* chips */ 35936 35937 #if defined(BCM_56450_B1) 35938 { /* SOC_FORMAT_INT_ITE_TO_RQE_EXT_INFO_BCM56450_B1fmt */ 35939 /* format ITE_TO_RQE_EXT_INFOfmt */ 35940 /* nFields */ 3, 35941 /* *fields */ soc_ENQ_TO_RQE_INT_INFO_BCM56450_A0fmt_fields, 35942 /* bits */ 29, 35943 /* flags */ 0, 35944 }, 35945 #endif /* chips */ 35946 35947 #if defined(BCM_56440_A0) 35948 { /* SOC_FORMAT_INT_ITE_TO_TOQ_WCE_INFOfmt */ 35949 /* format ITE_TO_TOQ_WCE_INFOfmt */ 35950 /* nFields */ 8, 35951 /* *fields */ soc_ENQ_TO_TOQ_WCI_INFOfmt_fields, 35952 /* bits */ 41, 35953 /* flags */ 0, 35954 }, 35955 #endif /* chips */ 35956 35957 #if defined(BCM_56260_A0) 35958 { /* SOC_FORMAT_INT_ITE_TO_TOQ_WCE_INFO_BCM56260_A0fmt */ 35959 /* format ITE_TO_TOQ_WCE_INFOfmt */ 35960 /* nFields */ 14, 35961 /* *fields */ soc_ITE_TO_TOQ_WCE_INFO_BCM56260_A0fmt_fields, 35962 /* bits */ 65, 35963 /* flags */ 0, 35964 }, 35965 #endif /* chips */ 35966 35967 #if defined(BCM_56260_B0) 35968 { /* SOC_FORMAT_INT_ITE_TO_TOQ_WCE_INFO_BCM56260_B0fmt */ 35969 /* format ITE_TO_TOQ_WCE_INFOfmt */ 35970 /* nFields */ 14, 35971 /* *fields */ soc_ITE_TO_TOQ_WCE_INFO_BCM56260_A0fmt_fields, 35972 /* bits */ 65, 35973 /* flags */ 0, 35974 }, 35975 #endif /* chips */ 35976 35977 #if defined(BCM_56270_A0) 35978 { /* SOC_FORMAT_INT_ITE_TO_TOQ_WCE_INFO_BCM56270_A0fmt */ 35979 /* format ITE_TO_TOQ_WCE_INFOfmt */ 35980 /* nFields */ 14, 35981 /* *fields */ soc_ITE_TO_TOQ_WCE_INFO_BCM56260_A0fmt_fields, 35982 /* bits */ 65, 35983 /* flags */ 0, 35984 }, 35985 #endif /* chips */ 35986 35987 #if defined(BCM_56440_B0) 35988 { /* SOC_FORMAT_INT_ITE_TO_TOQ_WCE_INFO_BCM56440_B0fmt */ 35989 /* format ITE_TO_TOQ_WCE_INFOfmt */ 35990 /* nFields */ 8, 35991 /* *fields */ soc_ENQ_TO_TOQ_WCI_INFOfmt_fields, 35992 /* bits */ 41, 35993 /* flags */ 0, 35994 }, 35995 #endif /* chips */ 35996 35997 #if defined(BCM_56450_A0) 35998 { /* SOC_FORMAT_INT_ITE_TO_TOQ_WCE_INFO_BCM56450_A0fmt */ 35999 /* format ITE_TO_TOQ_WCE_INFOfmt */ 36000 /* nFields */ 14, 36001 /* *fields */ soc_ITE_TO_TOQ_WCE_INFOfmt_fields, 36002 /* bits */ 73, 36003 /* flags */ 0, 36004 }, 36005 #endif /* chips */ 36006 36007 #if defined(BCM_56450_B0) 36008 { /* SOC_FORMAT_INT_ITE_TO_TOQ_WCE_INFO_BCM56450_B0fmt */ 36009 /* format ITE_TO_TOQ_WCE_INFOfmt */ 36010 /* nFields */ 14, 36011 /* *fields */ soc_ITE_TO_TOQ_WCE_INFOfmt_fields, 36012 /* bits */ 73, 36013 /* flags */ 0, 36014 }, 36015 #endif /* chips */ 36016 36017 #if defined(BCM_56450_B1) 36018 { /* SOC_FORMAT_INT_ITE_TO_TOQ_WCE_INFO_BCM56450_B1fmt */ 36019 /* format ITE_TO_TOQ_WCE_INFOfmt */ 36020 /* nFields */ 14, 36021 /* *fields */ soc_ITE_TO_TOQ_WCE_INFOfmt_fields, 36022 /* bits */ 73, 36023 /* flags */ 0, 36024 }, 36025 #endif /* chips */ 36026 36027 #if defined(BCM_56440_A0) 36028 { /* SOC_FORMAT_INT_ITE_WORK_QUEUE_MEMfmt */ 36029 /* format ITE_WORK_QUEUE_MEMfmt */ 36030 /* nFields */ 26, 36031 /* *fields */ soc_ITE_WORK_QUEUE_MEMfmt_fields, 36032 /* bits */ 105, 36033 /* flags */ 0, 36034 }, 36035 #endif /* chips */ 36036 36037 #if defined(BCM_56440_B0) 36038 { /* SOC_FORMAT_INT_ITE_WORK_QUEUE_MEM_BCM56440_B0fmt */ 36039 /* format ITE_WORK_QUEUE_MEMfmt */ 36040 /* nFields */ 26, 36041 /* *fields */ soc_ITE_WORK_QUEUE_MEMfmt_fields, 36042 /* bits */ 105, 36043 /* flags */ 0, 36044 }, 36045 #endif /* chips */ 36046 36047 #if defined(BCM_56450_A0) 36048 { /* SOC_FORMAT_INT_ITE_WORK_QUEUE_MEM_BCM56450_A0fmt */ 36049 /* format ITE_WORK_QUEUE_MEMfmt */ 36050 /* nFields */ 27, 36051 /* *fields */ soc_ITE_WORK_QUEUE_MEM_BCM56450_A0fmt_fields, 36052 /* bits */ 122, 36053 /* flags */ 0, 36054 }, 36055 #endif /* chips */ 36056 36057 #if defined(BCM_56450_B0) 36058 { /* SOC_FORMAT_INT_ITE_WORK_QUEUE_MEM_BCM56450_B0fmt */ 36059 /* format ITE_WORK_QUEUE_MEMfmt */ 36060 /* nFields */ 27, 36061 /* *fields */ soc_ITE_WORK_QUEUE_MEM_BCM56450_A0fmt_fields, 36062 /* bits */ 122, 36063 /* flags */ 0, 36064 }, 36065 #endif /* chips */ 36066 36067 #if defined(BCM_56450_B1) 36068 { /* SOC_FORMAT_INT_ITE_WORK_QUEUE_MEM_BCM56450_B1fmt */ 36069 /* format ITE_WORK_QUEUE_MEMfmt */ 36070 /* nFields */ 27, 36071 /* *fields */ soc_ITE_WORK_QUEUE_MEM_BCM56450_A0fmt_fields, 36072 /* bits */ 122, 36073 /* flags */ 0, 36074 }, 36075 #endif /* chips */ 36076 36077 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 36078 defined(BCM_56870_A0) 36079 { /* SOC_FORMAT_INT_IVLAN_ACTION_SETfmt */ 36080 /* format IVLAN_ACTION_SETfmt */ 36081 /* nFields */ 3, 36082 /* *fields */ soc_IVLAN_ACTION_SETfmt_fields, 36083 /* bits */ 16, 36084 /* flags */ 0, 36085 }, 36086 #endif /* chips */ 36087 36088 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 36089 defined(BCM_56870_A0) 36090 { /* SOC_FORMAT_INT_IVP_DOPfmt */ 36091 /* format IVP_DOPfmt */ 36092 /* nFields */ 12, 36093 /* *fields */ soc_IVP_DOPfmt_fields, 36094 /* bits */ 160, 36095 /* flags */ 0, 36096 }, 36097 #endif /* chips */ 36098 36099 #if defined(BCM_56370_A0) || defined(BCM_56870_A0) 36100 { /* SOC_FORMAT_INT_IVXLT1_DOPfmt */ 36101 /* format IVXLT1_DOPfmt */ 36102 /* nFields */ 90, 36103 /* *fields */ soc_IVXLT1_DOPfmt_fields, 36104 /* bits */ 3104, 36105 /* flags */ 0, 36106 }, 36107 #endif /* chips */ 36108 36109 #if defined(BCM_56770_A0) 36110 { /* SOC_FORMAT_INT_IVXLT1_DOP_BCM56770_A0fmt */ 36111 /* format IVXLT1_DOPfmt */ 36112 /* nFields */ 102, 36113 /* *fields */ soc_IVXLT1_DOP_BCM56770_A0fmt_fields, 36114 /* bits */ 3808, 36115 /* flags */ 0, 36116 }, 36117 #endif /* chips */ 36118 36119 #if defined(BCM_56370_A0) || defined(BCM_56870_A0) 36120 { /* SOC_FORMAT_INT_IVXLT2_DOPfmt */ 36121 /* format IVXLT2_DOPfmt */ 36122 /* nFields */ 24, 36123 /* *fields */ soc_IVXLT2_DOPfmt_fields, 36124 /* bits */ 416, 36125 /* flags */ 0, 36126 }, 36127 #endif /* chips */ 36128 36129 #if defined(BCM_56770_A0) 36130 { /* SOC_FORMAT_INT_IVXLT2_DOP_BCM56770_A0fmt */ 36131 /* format IVXLT2_DOPfmt */ 36132 /* nFields */ 30, 36133 /* *fields */ soc_IVXLT2_DOP_BCM56770_A0fmt_fields, 36134 /* bits */ 768, 36135 /* flags */ 0, 36136 }, 36137 #endif /* chips */ 36138