allformats_h.i (42626B)
1 /* 2 * DO NOT EDIT THIS FILE! 3 * This file is auto-generated from the registers file. 4 * Edits to this file will be lost when it is regenerated. 5 * 6 * 7 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 8 * 9 * Copyright 2007-2020 Broadcom Inc. All rights reserved. 10 * 11 * File: allformats_h.i 12 * Purpose: Independent format descriptions. 13 */ 14 15 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) 16 { /* SOC_FORMAT_INT_HASH_CONTROL_FULL_SETfmt */ 17 /* format HASH_CONTROL_FULL_SETfmt */ 18 /* nFields */ 30, 19 /* *fields */ soc_HASH_CONTROL_FULL_SETfmt_fields, 20 /* bits */ 112, 21 /* flags */ 0, 22 }, 23 #endif /* chips */ 24 25 #if defined(BCM_56370_A0) 26 { /* SOC_FORMAT_INT_HASH_CONTROL_FULL_SET_BCM56370_A0fmt */ 27 /* format HASH_CONTROL_FULL_SETfmt */ 28 /* nFields */ 31, 29 /* *fields */ soc_HASH_CONTROL_FULL_SET_BCM56980_A0fmt_fields, 30 /* bits */ 114, 31 /* flags */ 0, 32 }, 33 #endif /* chips */ 34 35 #if defined(BCM_56980_A0) 36 { /* SOC_FORMAT_INT_HASH_CONTROL_FULL_SET_BCM56980_A0fmt */ 37 /* format HASH_CONTROL_FULL_SETfmt */ 38 /* nFields */ 31, 39 /* *fields */ soc_HASH_CONTROL_FULL_SET_BCM56980_A0fmt_fields, 40 /* bits */ 114, 41 /* flags */ 0, 42 }, 43 #endif /* chips */ 44 45 #if defined(BCM_56980_B0) 46 { /* SOC_FORMAT_INT_HASH_CONTROL_FULL_SET_BCM56980_B0fmt */ 47 /* format HASH_CONTROL_FULL_SETfmt */ 48 /* nFields */ 31, 49 /* *fields */ soc_HASH_CONTROL_FULL_SET_BCM56980_A0fmt_fields, 50 /* bits */ 114, 51 /* flags */ 0, 52 }, 53 #endif /* chips */ 54 55 #if defined(BCM_56370_A0) 56 { /* SOC_FORMAT_INT_HDR_UPDATE_CTRLfmt */ 57 /* format HDR_UPDATE_CTRLfmt */ 58 /* nFields */ 7, 59 /* *fields */ soc_HDR_UPDATE_CTRLfmt_fields, 60 /* bits */ 24, 61 /* flags */ 0, 62 }, 63 #endif /* chips */ 64 65 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \ 66 defined(BCM_56450_B0) || defined(BCM_56450_B1) || \ 67 defined(BCM_56640_A0) || defined(BCM_56850_A0) || \ 68 defined(BCM_56860_A0) 69 { /* SOC_FORMAT_INT_HG2_EH_CLASSID_TYPEfmt */ 70 /* format HG2_EH_CLASSID_TYPEfmt */ 71 /* nFields */ 1, 72 /* *fields */ soc_HG2_EH_CLASSID_TYPEfmt_fields, 73 /* bits */ 4, 74 /* flags */ 0, 75 }, 76 #endif /* chips */ 77 78 #if defined(BCM_56260_A0) 79 { /* SOC_FORMAT_INT_HG2_EH_CLASSID_TYPE_BCM56260_A0fmt */ 80 /* format HG2_EH_CLASSID_TYPEfmt */ 81 /* nFields */ 1, 82 /* *fields */ soc_HG2_EH_CLASSID_TYPE_BCM56960_A0fmt_fields, 83 /* bits */ 4, 84 /* flags */ 0, 85 }, 86 #endif /* chips */ 87 88 #if defined(BCM_56260_B0) 89 { /* SOC_FORMAT_INT_HG2_EH_CLASSID_TYPE_BCM56260_B0fmt */ 90 /* format HG2_EH_CLASSID_TYPEfmt */ 91 /* nFields */ 1, 92 /* *fields */ soc_HG2_EH_CLASSID_TYPE_BCM56960_A0fmt_fields, 93 /* bits */ 4, 94 /* flags */ 0, 95 }, 96 #endif /* chips */ 97 98 #if defined(BCM_56270_A0) 99 { /* SOC_FORMAT_INT_HG2_EH_CLASSID_TYPE_BCM56270_A0fmt */ 100 /* format HG2_EH_CLASSID_TYPEfmt */ 101 /* nFields */ 1, 102 /* *fields */ soc_HG2_EH_CLASSID_TYPE_BCM56960_A0fmt_fields, 103 /* bits */ 4, 104 /* flags */ 0, 105 }, 106 #endif /* chips */ 107 108 #if defined(BCM_56370_A0) 109 { /* SOC_FORMAT_INT_HG2_EH_CLASSID_TYPE_BCM56370_A0fmt */ 110 /* format HG2_EH_CLASSID_TYPEfmt */ 111 /* nFields */ 1, 112 /* *fields */ soc_HG2_EH_CLASSID_TYPE_BCM56960_A0fmt_fields, 113 /* bits */ 4, 114 /* flags */ 0, 115 }, 116 #endif /* chips */ 117 118 #if defined(BCM_56560_A0) 119 { /* SOC_FORMAT_INT_HG2_EH_CLASSID_TYPE_BCM56560_A0fmt */ 120 /* format HG2_EH_CLASSID_TYPEfmt */ 121 /* nFields */ 1, 122 /* *fields */ soc_HG2_EH_CLASSID_TYPE_BCM56960_A0fmt_fields, 123 /* bits */ 4, 124 /* flags */ 0, 125 }, 126 #endif /* chips */ 127 128 #if defined(BCM_56560_B0) 129 { /* SOC_FORMAT_INT_HG2_EH_CLASSID_TYPE_BCM56560_B0fmt */ 130 /* format HG2_EH_CLASSID_TYPEfmt */ 131 /* nFields */ 1, 132 /* *fields */ soc_HG2_EH_CLASSID_TYPE_BCM56960_A0fmt_fields, 133 /* bits */ 4, 134 /* flags */ 0, 135 }, 136 #endif /* chips */ 137 138 #if defined(BCM_56670_A0) 139 { /* SOC_FORMAT_INT_HG2_EH_CLASSID_TYPE_BCM56670_A0fmt */ 140 /* format HG2_EH_CLASSID_TYPEfmt */ 141 /* nFields */ 1, 142 /* *fields */ soc_HG2_EH_CLASSID_TYPE_BCM56960_A0fmt_fields, 143 /* bits */ 4, 144 /* flags */ 0, 145 }, 146 #endif /* chips */ 147 148 #if defined(BCM_56670_B0) 149 { /* SOC_FORMAT_INT_HG2_EH_CLASSID_TYPE_BCM56670_B0fmt */ 150 /* format HG2_EH_CLASSID_TYPEfmt */ 151 /* nFields */ 1, 152 /* *fields */ soc_HG2_EH_CLASSID_TYPE_BCM56960_A0fmt_fields, 153 /* bits */ 4, 154 /* flags */ 0, 155 }, 156 #endif /* chips */ 157 158 #if defined(BCM_56770_A0) 159 { /* SOC_FORMAT_INT_HG2_EH_CLASSID_TYPE_BCM56770_A0fmt */ 160 /* format HG2_EH_CLASSID_TYPEfmt */ 161 /* nFields */ 1, 162 /* *fields */ soc_HG2_EH_CLASSID_TYPE_BCM56960_A0fmt_fields, 163 /* bits */ 4, 164 /* flags */ 0, 165 }, 166 #endif /* chips */ 167 168 #if defined(BCM_56870_A0) 169 { /* SOC_FORMAT_INT_HG2_EH_CLASSID_TYPE_BCM56870_A0fmt */ 170 /* format HG2_EH_CLASSID_TYPEfmt */ 171 /* nFields */ 1, 172 /* *fields */ soc_HG2_EH_CLASSID_TYPE_BCM56960_A0fmt_fields, 173 /* bits */ 4, 174 /* flags */ 0, 175 }, 176 #endif /* chips */ 177 178 #if defined(BCM_56960_A0) 179 { /* SOC_FORMAT_INT_HG2_EH_CLASSID_TYPE_BCM56960_A0fmt */ 180 /* format HG2_EH_CLASSID_TYPEfmt */ 181 /* nFields */ 1, 182 /* *fields */ soc_HG2_EH_CLASSID_TYPE_BCM56960_A0fmt_fields, 183 /* bits */ 4, 184 /* flags */ 0, 185 }, 186 #endif /* chips */ 187 188 #if defined(BCM_56965_A0) 189 { /* SOC_FORMAT_INT_HG2_EH_CLASSID_TYPE_BCM56965_A0fmt */ 190 /* format HG2_EH_CLASSID_TYPEfmt */ 191 /* nFields */ 1, 192 /* *fields */ soc_HG2_EH_CLASSID_TYPE_BCM56960_A0fmt_fields, 193 /* bits */ 4, 194 /* flags */ 0, 195 }, 196 #endif /* chips */ 197 198 #if defined(BCM_56970_A0) 199 { /* SOC_FORMAT_INT_HG2_EH_CLASSID_TYPE_BCM56970_A0fmt */ 200 /* format HG2_EH_CLASSID_TYPEfmt */ 201 /* nFields */ 1, 202 /* *fields */ soc_HG2_EH_CLASSID_TYPE_BCM56960_A0fmt_fields, 203 /* bits */ 4, 204 /* flags */ 0, 205 }, 206 #endif /* chips */ 207 208 #if defined(BCM_56980_A0) 209 { /* SOC_FORMAT_INT_HG2_EH_CLASSID_TYPE_BCM56980_A0fmt */ 210 /* format HG2_EH_CLASSID_TYPEfmt */ 211 /* nFields */ 1, 212 /* *fields */ soc_HG2_EH_CLASSID_TYPE_BCM56960_A0fmt_fields, 213 /* bits */ 4, 214 /* flags */ 0, 215 }, 216 #endif /* chips */ 217 218 #if defined(BCM_56980_B0) 219 { /* SOC_FORMAT_INT_HG2_EH_CLASSID_TYPE_BCM56980_B0fmt */ 220 /* format HG2_EH_CLASSID_TYPEfmt */ 221 /* nFields */ 1, 222 /* *fields */ soc_HG2_EH_CLASSID_TYPE_BCM56960_A0fmt_fields, 223 /* bits */ 4, 224 /* flags */ 0, 225 }, 226 #endif /* chips */ 227 228 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 229 defined(BCM_56870_A0) 230 { /* SOC_FORMAT_INT_HG2_UNUSED_FIELDSfmt */ 231 /* format HG2_UNUSED_FIELDSfmt */ 232 /* nFields */ 10, 233 /* *fields */ soc_HG2_UNUSED_FIELDSfmt_fields, 234 /* bits */ 21, 235 /* flags */ 0, 236 }, 237 #endif /* chips */ 238 239 #if defined(BCM_56870_A0) 240 { /* SOC_FORMAT_INT_HGT_LAG_DLB_ACTION_SETfmt */ 241 /* format HGT_LAG_DLB_ACTION_SETfmt */ 242 /* nFields */ 2, 243 /* *fields */ soc_ECMP_DLB_ACTION_SETfmt_fields, 244 /* bits */ 2, 245 /* flags */ 0, 246 }, 247 #endif /* chips */ 248 249 #if defined(BCM_56370_A0) 250 { /* SOC_FORMAT_INT_HGT_LAG_DLB_ACTION_SET_BCM56370_A0fmt */ 251 /* format HGT_LAG_DLB_ACTION_SETfmt */ 252 /* nFields */ 2, 253 /* *fields */ soc_ECMP_DLB_ACTION_SETfmt_fields, 254 /* bits */ 2, 255 /* flags */ 0, 256 }, 257 #endif /* chips */ 258 259 #if defined(BCM_56770_A0) 260 { /* SOC_FORMAT_INT_HGT_LAG_DLB_ACTION_SET_BCM56770_A0fmt */ 261 /* format HGT_LAG_DLB_ACTION_SETfmt */ 262 /* nFields */ 2, 263 /* *fields */ soc_ECMP_DLB_ACTION_SETfmt_fields, 264 /* bits */ 2, 265 /* flags */ 0, 266 }, 267 #endif /* chips */ 268 269 #if defined(BCM_56870_A0) 270 { /* SOC_FORMAT_INT_HGT_RH_ACTION_SETfmt */ 271 /* format HGT_RH_ACTION_SETfmt */ 272 /* nFields */ 2, 273 /* *fields */ soc_ECMP_DLB_ACTION_SETfmt_fields, 274 /* bits */ 2, 275 /* flags */ 0, 276 }, 277 #endif /* chips */ 278 279 #if defined(BCM_56370_A0) 280 { /* SOC_FORMAT_INT_HGT_RH_ACTION_SET_BCM56370_A0fmt */ 281 /* format HGT_RH_ACTION_SETfmt */ 282 /* nFields */ 2, 283 /* *fields */ soc_ECMP_DLB_ACTION_SETfmt_fields, 284 /* bits */ 2, 285 /* flags */ 0, 286 }, 287 #endif /* chips */ 288 289 #if defined(BCM_56770_A0) 290 { /* SOC_FORMAT_INT_HGT_RH_ACTION_SET_BCM56770_A0fmt */ 291 /* format HGT_RH_ACTION_SETfmt */ 292 /* nFields */ 2, 293 /* *fields */ soc_ECMP_DLB_ACTION_SETfmt_fields, 294 /* bits */ 2, 295 /* flags */ 0, 296 }, 297 #endif /* chips */ 298 299 #if defined(BCM_56334_A0) || defined(BCM_56440_A0) || \ 300 defined(BCM_56440_B0) || defined(BCM_56524_B0) || \ 301 defined(BCM_56624_A0) || defined(BCM_56624_B0) || \ 302 defined(BCM_56634_A0) || defined(BCM_56634_B0) || \ 303 defined(BCM_56680_A0) || defined(BCM_56685_B0) || \ 304 defined(BCM_56725_A0) || defined(BCM_56800_A0) || \ 305 defined(BCM_56820_A0) || defined(BCM_56840_B0) 306 { /* SOC_FORMAT_INT_HG_COUNTERfmt */ 307 /* format HG_COUNTERfmt */ 308 /* nFields */ 1, 309 /* *fields */ soc_HG_COUNTERfmt_fields, 310 /* bits */ 3, 311 /* flags */ 0, 312 }, 313 #endif /* chips */ 314 315 #if defined(BCM_53400_A0) 316 { /* SOC_FORMAT_INT_HG_COUNTER_BCM53400_A0fmt */ 317 /* format HG_COUNTERfmt */ 318 /* nFields */ 1, 319 /* *fields */ soc_HG_COUNTER_BCM53400_A0fmt_fields, 320 /* bits */ 3, 321 /* flags */ 0, 322 }, 323 #endif /* chips */ 324 325 #if defined(BCM_53540_A0) 326 { /* SOC_FORMAT_INT_HG_COUNTER_BCM53540_A0fmt */ 327 /* format HG_COUNTERfmt */ 328 /* nFields */ 1, 329 /* *fields */ soc_HG_COUNTER_BCM53400_A0fmt_fields, 330 /* bits */ 3, 331 /* flags */ 0, 332 }, 333 #endif /* chips */ 334 335 #if defined(BCM_53570_A0) 336 { /* SOC_FORMAT_INT_HG_COUNTER_BCM53570_A0fmt */ 337 /* format HG_COUNTERfmt */ 338 /* nFields */ 1, 339 /* *fields */ soc_HG_COUNTER_BCM53400_A0fmt_fields, 340 /* bits */ 3, 341 /* flags */ 0, 342 }, 343 #endif /* chips */ 344 345 #if defined(BCM_53570_B0) 346 { /* SOC_FORMAT_INT_HG_COUNTER_BCM53570_B0fmt */ 347 /* format HG_COUNTERfmt */ 348 /* nFields */ 1, 349 /* *fields */ soc_HG_COUNTER_BCM53400_A0fmt_fields, 350 /* bits */ 3, 351 /* flags */ 0, 352 }, 353 #endif /* chips */ 354 355 #if defined(BCM_56142_A0) 356 { /* SOC_FORMAT_INT_HG_COUNTER_BCM56142_A0fmt */ 357 /* format HG_COUNTERfmt */ 358 /* nFields */ 1, 359 /* *fields */ soc_HG_COUNTERfmt_fields, 360 /* bits */ 3, 361 /* flags */ 0, 362 }, 363 #endif /* chips */ 364 365 #if defined(BCM_56150_A0) 366 { /* SOC_FORMAT_INT_HG_COUNTER_BCM56150_A0fmt */ 367 /* format HG_COUNTERfmt */ 368 /* nFields */ 1, 369 /* *fields */ soc_HG_COUNTER_BCM56640_A0fmt_fields, 370 /* bits */ 3, 371 /* flags */ 0, 372 }, 373 #endif /* chips */ 374 375 #if defined(BCM_56160_A0) 376 { /* SOC_FORMAT_INT_HG_COUNTER_BCM56160_A0fmt */ 377 /* format HG_COUNTERfmt */ 378 /* nFields */ 1, 379 /* *fields */ soc_HG_COUNTER_BCM53400_A0fmt_fields, 380 /* bits */ 3, 381 /* flags */ 0, 382 }, 383 #endif /* chips */ 384 385 #if defined(BCM_56260_A0) 386 { /* SOC_FORMAT_INT_HG_COUNTER_BCM56260_A0fmt */ 387 /* format HG_COUNTERfmt */ 388 /* nFields */ 1, 389 /* *fields */ soc_HG_COUNTER_BCM53400_A0fmt_fields, 390 /* bits */ 3, 391 /* flags */ 0, 392 }, 393 #endif /* chips */ 394 395 #if defined(BCM_56260_B0) 396 { /* SOC_FORMAT_INT_HG_COUNTER_BCM56260_B0fmt */ 397 /* format HG_COUNTERfmt */ 398 /* nFields */ 1, 399 /* *fields */ soc_HG_COUNTER_BCM53400_A0fmt_fields, 400 /* bits */ 3, 401 /* flags */ 0, 402 }, 403 #endif /* chips */ 404 405 #if defined(BCM_56270_A0) 406 { /* SOC_FORMAT_INT_HG_COUNTER_BCM56270_A0fmt */ 407 /* format HG_COUNTERfmt */ 408 /* nFields */ 1, 409 /* *fields */ soc_HG_COUNTER_BCM53400_A0fmt_fields, 410 /* bits */ 3, 411 /* flags */ 0, 412 }, 413 #endif /* chips */ 414 415 #if defined(BCM_56334_B0) 416 { /* SOC_FORMAT_INT_HG_COUNTER_BCM56334_B0fmt */ 417 /* format HG_COUNTERfmt */ 418 /* nFields */ 1, 419 /* *fields */ soc_HG_COUNTERfmt_fields, 420 /* bits */ 3, 421 /* flags */ 0, 422 }, 423 #endif /* chips */ 424 425 #if defined(BCM_56340_A0) 426 { /* SOC_FORMAT_INT_HG_COUNTER_BCM56340_A0fmt */ 427 /* format HG_COUNTERfmt */ 428 /* nFields */ 1, 429 /* *fields */ soc_HG_COUNTER_BCM56640_A0fmt_fields, 430 /* bits */ 3, 431 /* flags */ 0, 432 }, 433 #endif /* chips */ 434 435 #if defined(BCM_56370_A0) 436 { /* SOC_FORMAT_INT_HG_COUNTER_BCM56370_A0fmt */ 437 /* format HG_COUNTERfmt */ 438 /* nFields */ 1, 439 /* *fields */ soc_HG_COUNTER_BCM53400_A0fmt_fields, 440 /* bits */ 3, 441 /* flags */ 0, 442 }, 443 #endif /* chips */ 444 445 #if defined(BCM_56450_A0) 446 { /* SOC_FORMAT_INT_HG_COUNTER_BCM56450_A0fmt */ 447 /* format HG_COUNTERfmt */ 448 /* nFields */ 1, 449 /* *fields */ soc_HG_COUNTER_BCM56640_A0fmt_fields, 450 /* bits */ 3, 451 /* flags */ 0, 452 }, 453 #endif /* chips */ 454 455 #if defined(BCM_56450_B0) 456 { /* SOC_FORMAT_INT_HG_COUNTER_BCM56450_B0fmt */ 457 /* format HG_COUNTERfmt */ 458 /* nFields */ 1, 459 /* *fields */ soc_HG_COUNTER_BCM56640_A0fmt_fields, 460 /* bits */ 3, 461 /* flags */ 0, 462 }, 463 #endif /* chips */ 464 465 #if defined(BCM_56450_B1) 466 { /* SOC_FORMAT_INT_HG_COUNTER_BCM56450_B1fmt */ 467 /* format HG_COUNTERfmt */ 468 /* nFields */ 1, 469 /* *fields */ soc_HG_COUNTER_BCM56640_A0fmt_fields, 470 /* bits */ 3, 471 /* flags */ 0, 472 }, 473 #endif /* chips */ 474 475 #if defined(BCM_56524_A0) 476 { /* SOC_FORMAT_INT_HG_COUNTER_BCM56524_A0fmt */ 477 /* format HG_COUNTERfmt */ 478 /* nFields */ 1, 479 /* *fields */ soc_HG_COUNTERfmt_fields, 480 /* bits */ 3, 481 /* flags */ 0, 482 }, 483 #endif /* chips */ 484 485 #if defined(BCM_56560_A0) 486 { /* SOC_FORMAT_INT_HG_COUNTER_BCM56560_A0fmt */ 487 /* format HG_COUNTERfmt */ 488 /* nFields */ 1, 489 /* *fields */ soc_HG_COUNTER_BCM53400_A0fmt_fields, 490 /* bits */ 3, 491 /* flags */ 0, 492 }, 493 #endif /* chips */ 494 495 #if defined(BCM_56560_B0) 496 { /* SOC_FORMAT_INT_HG_COUNTER_BCM56560_B0fmt */ 497 /* format HG_COUNTERfmt */ 498 /* nFields */ 1, 499 /* *fields */ soc_HG_COUNTER_BCM53400_A0fmt_fields, 500 /* bits */ 3, 501 /* flags */ 0, 502 }, 503 #endif /* chips */ 504 505 #if defined(BCM_56640_A0) 506 { /* SOC_FORMAT_INT_HG_COUNTER_BCM56640_A0fmt */ 507 /* format HG_COUNTERfmt */ 508 /* nFields */ 1, 509 /* *fields */ soc_HG_COUNTER_BCM56640_A0fmt_fields, 510 /* bits */ 3, 511 /* flags */ 0, 512 }, 513 #endif /* chips */ 514 515 #if defined(BCM_56670_A0) 516 { /* SOC_FORMAT_INT_HG_COUNTER_BCM56670_A0fmt */ 517 /* format HG_COUNTERfmt */ 518 /* nFields */ 1, 519 /* *fields */ soc_HG_COUNTER_BCM53400_A0fmt_fields, 520 /* bits */ 3, 521 /* flags */ 0, 522 }, 523 #endif /* chips */ 524 525 #if defined(BCM_56670_B0) 526 { /* SOC_FORMAT_INT_HG_COUNTER_BCM56670_B0fmt */ 527 /* format HG_COUNTERfmt */ 528 /* nFields */ 1, 529 /* *fields */ soc_HG_COUNTER_BCM53400_A0fmt_fields, 530 /* bits */ 3, 531 /* flags */ 0, 532 }, 533 #endif /* chips */ 534 535 #if defined(BCM_56680_B0) 536 { /* SOC_FORMAT_INT_HG_COUNTER_BCM56680_B0fmt */ 537 /* format HG_COUNTERfmt */ 538 /* nFields */ 1, 539 /* *fields */ soc_HG_COUNTERfmt_fields, 540 /* bits */ 3, 541 /* flags */ 0, 542 }, 543 #endif /* chips */ 544 545 #if defined(BCM_56685_A0) 546 { /* SOC_FORMAT_INT_HG_COUNTER_BCM56685_A0fmt */ 547 /* format HG_COUNTERfmt */ 548 /* nFields */ 1, 549 /* *fields */ soc_HG_COUNTERfmt_fields, 550 /* bits */ 3, 551 /* flags */ 0, 552 }, 553 #endif /* chips */ 554 555 #if defined(BCM_56770_A0) 556 { /* SOC_FORMAT_INT_HG_COUNTER_BCM56770_A0fmt */ 557 /* format HG_COUNTERfmt */ 558 /* nFields */ 1, 559 /* *fields */ soc_HG_COUNTER_BCM53400_A0fmt_fields, 560 /* bits */ 3, 561 /* flags */ 0, 562 }, 563 #endif /* chips */ 564 565 #if defined(BCM_56840_A0) 566 { /* SOC_FORMAT_INT_HG_COUNTER_BCM56840_A0fmt */ 567 /* format HG_COUNTERfmt */ 568 /* nFields */ 1, 569 /* *fields */ soc_HG_COUNTERfmt_fields, 570 /* bits */ 3, 571 /* flags */ 0, 572 }, 573 #endif /* chips */ 574 575 #if defined(BCM_56850_A0) 576 { /* SOC_FORMAT_INT_HG_COUNTER_BCM56850_A0fmt */ 577 /* format HG_COUNTERfmt */ 578 /* nFields */ 1, 579 /* *fields */ soc_HG_COUNTER_BCM56640_A0fmt_fields, 580 /* bits */ 3, 581 /* flags */ 0, 582 }, 583 #endif /* chips */ 584 585 #if defined(BCM_56860_A0) 586 { /* SOC_FORMAT_INT_HG_COUNTER_BCM56860_A0fmt */ 587 /* format HG_COUNTERfmt */ 588 /* nFields */ 1, 589 /* *fields */ soc_HG_COUNTER_BCM56640_A0fmt_fields, 590 /* bits */ 3, 591 /* flags */ 0, 592 }, 593 #endif /* chips */ 594 595 #if defined(BCM_56870_A0) 596 { /* SOC_FORMAT_INT_HG_COUNTER_BCM56870_A0fmt */ 597 /* format HG_COUNTERfmt */ 598 /* nFields */ 1, 599 /* *fields */ soc_HG_COUNTER_BCM53400_A0fmt_fields, 600 /* bits */ 3, 601 /* flags */ 0, 602 }, 603 #endif /* chips */ 604 605 #if defined(BCM_56960_A0) 606 { /* SOC_FORMAT_INT_HG_COUNTER_BCM56960_A0fmt */ 607 /* format HG_COUNTERfmt */ 608 /* nFields */ 1, 609 /* *fields */ soc_HG_COUNTER_BCM53400_A0fmt_fields, 610 /* bits */ 3, 611 /* flags */ 0, 612 }, 613 #endif /* chips */ 614 615 #if defined(BCM_56965_A0) 616 { /* SOC_FORMAT_INT_HG_COUNTER_BCM56965_A0fmt */ 617 /* format HG_COUNTERfmt */ 618 /* nFields */ 1, 619 /* *fields */ soc_HG_COUNTER_BCM53400_A0fmt_fields, 620 /* bits */ 3, 621 /* flags */ 0, 622 }, 623 #endif /* chips */ 624 625 #if defined(BCM_56970_A0) 626 { /* SOC_FORMAT_INT_HG_COUNTER_BCM56970_A0fmt */ 627 /* format HG_COUNTERfmt */ 628 /* nFields */ 1, 629 /* *fields */ soc_HG_COUNTER_BCM53400_A0fmt_fields, 630 /* bits */ 3, 631 /* flags */ 0, 632 }, 633 #endif /* chips */ 634 635 #if defined(BCM_56980_A0) 636 { /* SOC_FORMAT_INT_HG_COUNTER_BCM56980_A0fmt */ 637 /* format HG_COUNTERfmt */ 638 /* nFields */ 1, 639 /* *fields */ soc_HG_COUNTER_BCM53400_A0fmt_fields, 640 /* bits */ 3, 641 /* flags */ 0, 642 }, 643 #endif /* chips */ 644 645 #if defined(BCM_56980_B0) 646 { /* SOC_FORMAT_INT_HG_COUNTER_BCM56980_B0fmt */ 647 /* format HG_COUNTERfmt */ 648 /* nFields */ 1, 649 /* *fields */ soc_HG_COUNTER_BCM53400_A0fmt_fields, 650 /* bits */ 3, 651 /* flags */ 0, 652 }, 653 #endif /* chips */ 654 655 #if defined(BCM_88732_A0) 656 { /* SOC_FORMAT_INT_HG_COUNTER_BCM88732_A0fmt */ 657 /* format HG_COUNTERfmt */ 658 /* nFields */ 1, 659 /* *fields */ soc_HG_COUNTERfmt_fields, 660 /* bits */ 3, 661 /* flags */ 0, 662 }, 663 #endif /* chips */ 664 665 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) 666 { /* SOC_FORMAT_INT_HG_TRUNK_DOPfmt */ 667 /* format HG_TRUNK_DOPfmt */ 668 /* nFields */ 7, 669 /* *fields */ soc_HG_TRUNK_DOPfmt_fields, 670 /* bits */ 32, 671 /* flags */ 0, 672 }, 673 #endif /* chips */ 674 675 #if defined(BCM_56370_A0) 676 { /* SOC_FORMAT_INT_HG_TRUNK_DOP_BCM56370_A0fmt */ 677 /* format HG_TRUNK_DOPfmt */ 678 /* nFields */ 7, 679 /* *fields */ soc_HG_TRUNK_DOP_BCM56370_A0fmt_fields, 680 /* bits */ 32, 681 /* flags */ 0, 682 }, 683 #endif /* chips */ 684 685 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 686 defined(BCM_56870_A0) || defined(BCM_56960_A0) || \ 687 defined(BCM_56965_A0) || defined(BCM_56970_A0) 688 { /* SOC_FORMAT_INT_HG_TRUNK_GROUP_RRLB_CNT_COV_DEFSfmt */ 689 /* format HG_TRUNK_GROUP_RRLB_CNT_COV_DEFSfmt */ 690 /* nFields */ 8, 691 /* *fields */ soc_HG_TRUNK_GROUP_RRLB_CNT_COV_DEFSfmt_fields, 692 /* bits */ 19, 693 /* flags */ 0, 694 }, 695 #endif /* chips */ 696 697 #if defined(BCM_56725_A0) || defined(BCM_56800_A0) || \ 698 defined(BCM_56820_A0) 699 { /* SOC_FORMAT_INT_HIGIG2fmt */ 700 /* format HIGIG2fmt */ 701 /* nFields */ 31, 702 /* *fields */ soc_HIGIG2fmt_fields, 703 /* bits */ 128, 704 /* flags */ 0, 705 }, 706 #endif /* chips */ 707 708 #if defined(BCM_53400_A0) 709 { /* SOC_FORMAT_INT_HIGIG2_BCM53400_A0fmt */ 710 /* format HIGIG2fmt */ 711 /* nFields */ 75, 712 /* *fields */ soc_HIGIG2_BCM53400_A0fmt_fields, 713 /* bits */ 128, 714 /* flags */ 0, 715 }, 716 #endif /* chips */ 717 718 #if defined(BCM_53540_A0) 719 { /* SOC_FORMAT_INT_HIGIG2_BCM53540_A0fmt */ 720 /* format HIGIG2fmt */ 721 /* nFields */ 75, 722 /* *fields */ soc_HIGIG2_BCM53400_A0fmt_fields, 723 /* bits */ 128, 724 /* flags */ 0, 725 }, 726 #endif /* chips */ 727 728 #if defined(BCM_53570_A0) 729 { /* SOC_FORMAT_INT_HIGIG2_BCM53570_A0fmt */ 730 /* format HIGIG2fmt */ 731 /* nFields */ 75, 732 /* *fields */ soc_HIGIG2_BCM53400_A0fmt_fields, 733 /* bits */ 128, 734 /* flags */ 0, 735 }, 736 #endif /* chips */ 737 738 #if defined(BCM_53570_B0) 739 { /* SOC_FORMAT_INT_HIGIG2_BCM53570_B0fmt */ 740 /* format HIGIG2fmt */ 741 /* nFields */ 75, 742 /* *fields */ soc_HIGIG2_BCM53400_A0fmt_fields, 743 /* bits */ 128, 744 /* flags */ 0, 745 }, 746 #endif /* chips */ 747 748 #if defined(BCM_56142_A0) 749 { /* SOC_FORMAT_INT_HIGIG2_BCM56142_A0fmt */ 750 /* format HIGIG2fmt */ 751 /* nFields */ 74, 752 /* *fields */ soc_HIGIG2_BCM56634_A0fmt_fields, 753 /* bits */ 128, 754 /* flags */ 0, 755 }, 756 #endif /* chips */ 757 758 #if defined(BCM_56150_A0) 759 { /* SOC_FORMAT_INT_HIGIG2_BCM56150_A0fmt */ 760 /* format HIGIG2fmt */ 761 /* nFields */ 74, 762 /* *fields */ soc_HIGIG2_BCM56450_A0fmt_fields, 763 /* bits */ 128, 764 /* flags */ 0, 765 }, 766 #endif /* chips */ 767 768 #if defined(BCM_56160_A0) 769 { /* SOC_FORMAT_INT_HIGIG2_BCM56160_A0fmt */ 770 /* format HIGIG2fmt */ 771 /* nFields */ 75, 772 /* *fields */ soc_HIGIG2_BCM53400_A0fmt_fields, 773 /* bits */ 128, 774 /* flags */ 0, 775 }, 776 #endif /* chips */ 777 778 #if defined(BCM_56260_A0) 779 { /* SOC_FORMAT_INT_HIGIG2_BCM56260_A0fmt */ 780 /* format HIGIG2fmt */ 781 /* nFields */ 74, 782 /* *fields */ soc_HIGIG2_BCM56260_A0fmt_fields, 783 /* bits */ 128, 784 /* flags */ 0, 785 }, 786 #endif /* chips */ 787 788 #if defined(BCM_56260_B0) 789 { /* SOC_FORMAT_INT_HIGIG2_BCM56260_B0fmt */ 790 /* format HIGIG2fmt */ 791 /* nFields */ 74, 792 /* *fields */ soc_HIGIG2_BCM56260_A0fmt_fields, 793 /* bits */ 128, 794 /* flags */ 0, 795 }, 796 #endif /* chips */ 797 798 #if defined(BCM_56270_A0) 799 { /* SOC_FORMAT_INT_HIGIG2_BCM56270_A0fmt */ 800 /* format HIGIG2fmt */ 801 /* nFields */ 74, 802 /* *fields */ soc_HIGIG2_BCM56260_A0fmt_fields, 803 /* bits */ 128, 804 /* flags */ 0, 805 }, 806 #endif /* chips */ 807 808 #if defined(BCM_56334_A0) 809 { /* SOC_FORMAT_INT_HIGIG2_BCM56334_A0fmt */ 810 /* format HIGIG2fmt */ 811 /* nFields */ 74, 812 /* *fields */ soc_HIGIG2_BCM56634_A0fmt_fields, 813 /* bits */ 128, 814 /* flags */ 0, 815 }, 816 #endif /* chips */ 817 818 #if defined(BCM_56334_B0) 819 { /* SOC_FORMAT_INT_HIGIG2_BCM56334_B0fmt */ 820 /* format HIGIG2fmt */ 821 /* nFields */ 74, 822 /* *fields */ soc_HIGIG2_BCM56634_A0fmt_fields, 823 /* bits */ 128, 824 /* flags */ 0, 825 }, 826 #endif /* chips */ 827 828 #if defined(BCM_56340_A0) 829 { /* SOC_FORMAT_INT_HIGIG2_BCM56340_A0fmt */ 830 /* format HIGIG2fmt */ 831 /* nFields */ 78, 832 /* *fields */ soc_HIGIG2_BCM56640_A0fmt_fields, 833 /* bits */ 128, 834 /* flags */ 0, 835 }, 836 #endif /* chips */ 837 838 #if defined(BCM_56370_A0) 839 { /* SOC_FORMAT_INT_HIGIG2_BCM56370_A0fmt */ 840 /* format HIGIG2fmt */ 841 /* nFields */ 80, 842 /* *fields */ soc_HIGIG2_BCM56870_A0fmt_fields, 843 /* bits */ 128, 844 /* flags */ 0, 845 }, 846 #endif /* chips */ 847 848 #if defined(BCM_56440_A0) 849 { /* SOC_FORMAT_INT_HIGIG2_BCM56440_A0fmt */ 850 /* format HIGIG2fmt */ 851 /* nFields */ 74, 852 /* *fields */ soc_HIGIG2_BCM56634_A0fmt_fields, 853 /* bits */ 128, 854 /* flags */ 0, 855 }, 856 #endif /* chips */ 857 858 #if defined(BCM_56440_B0) 859 { /* SOC_FORMAT_INT_HIGIG2_BCM56440_B0fmt */ 860 /* format HIGIG2fmt */ 861 /* nFields */ 74, 862 /* *fields */ soc_HIGIG2_BCM56634_A0fmt_fields, 863 /* bits */ 128, 864 /* flags */ 0, 865 }, 866 #endif /* chips */ 867 868 #if defined(BCM_56450_A0) 869 { /* SOC_FORMAT_INT_HIGIG2_BCM56450_A0fmt */ 870 /* format HIGIG2fmt */ 871 /* nFields */ 74, 872 /* *fields */ soc_HIGIG2_BCM56450_A0fmt_fields, 873 /* bits */ 128, 874 /* flags */ 0, 875 }, 876 #endif /* chips */ 877 878 #if defined(BCM_56450_B0) 879 { /* SOC_FORMAT_INT_HIGIG2_BCM56450_B0fmt */ 880 /* format HIGIG2fmt */ 881 /* nFields */ 74, 882 /* *fields */ soc_HIGIG2_BCM56450_A0fmt_fields, 883 /* bits */ 128, 884 /* flags */ 0, 885 }, 886 #endif /* chips */ 887 888 #if defined(BCM_56450_B1) 889 { /* SOC_FORMAT_INT_HIGIG2_BCM56450_B1fmt */ 890 /* format HIGIG2fmt */ 891 /* nFields */ 74, 892 /* *fields */ soc_HIGIG2_BCM56450_A0fmt_fields, 893 /* bits */ 128, 894 /* flags */ 0, 895 }, 896 #endif /* chips */ 897 898 #if defined(BCM_56524_A0) 899 { /* SOC_FORMAT_INT_HIGIG2_BCM56524_A0fmt */ 900 /* format HIGIG2fmt */ 901 /* nFields */ 74, 902 /* *fields */ soc_HIGIG2_BCM56634_A0fmt_fields, 903 /* bits */ 128, 904 /* flags */ 0, 905 }, 906 #endif /* chips */ 907 908 #if defined(BCM_56524_B0) 909 { /* SOC_FORMAT_INT_HIGIG2_BCM56524_B0fmt */ 910 /* format HIGIG2fmt */ 911 /* nFields */ 74, 912 /* *fields */ soc_HIGIG2_BCM56634_A0fmt_fields, 913 /* bits */ 128, 914 /* flags */ 0, 915 }, 916 #endif /* chips */ 917 918 #if defined(BCM_56560_A0) 919 { /* SOC_FORMAT_INT_HIGIG2_BCM56560_A0fmt */ 920 /* format HIGIG2fmt */ 921 /* nFields */ 77, 922 /* *fields */ soc_HIGIG2_BCM56560_A0fmt_fields, 923 /* bits */ 128, 924 /* flags */ 0, 925 }, 926 #endif /* chips */ 927 928 #if defined(BCM_56560_B0) 929 { /* SOC_FORMAT_INT_HIGIG2_BCM56560_B0fmt */ 930 /* format HIGIG2fmt */ 931 /* nFields */ 77, 932 /* *fields */ soc_HIGIG2_BCM56560_A0fmt_fields, 933 /* bits */ 128, 934 /* flags */ 0, 935 }, 936 #endif /* chips */ 937 938 #if defined(BCM_56624_A0) 939 { /* SOC_FORMAT_INT_HIGIG2_BCM56624_A0fmt */ 940 /* format HIGIG2fmt */ 941 /* nFields */ 32, 942 /* *fields */ soc_HIGIG2_BCM56624_A0fmt_fields, 943 /* bits */ 128, 944 /* flags */ 0, 945 }, 946 #endif /* chips */ 947 948 #if defined(BCM_56624_B0) 949 { /* SOC_FORMAT_INT_HIGIG2_BCM56624_B0fmt */ 950 /* format HIGIG2fmt */ 951 /* nFields */ 32, 952 /* *fields */ soc_HIGIG2_BCM56624_A0fmt_fields, 953 /* bits */ 128, 954 /* flags */ 0, 955 }, 956 #endif /* chips */ 957 958 #if defined(BCM_56634_A0) 959 { /* SOC_FORMAT_INT_HIGIG2_BCM56634_A0fmt */ 960 /* format HIGIG2fmt */ 961 /* nFields */ 74, 962 /* *fields */ soc_HIGIG2_BCM56634_A0fmt_fields, 963 /* bits */ 128, 964 /* flags */ 0, 965 }, 966 #endif /* chips */ 967 968 #if defined(BCM_56634_B0) 969 { /* SOC_FORMAT_INT_HIGIG2_BCM56634_B0fmt */ 970 /* format HIGIG2fmt */ 971 /* nFields */ 74, 972 /* *fields */ soc_HIGIG2_BCM56634_A0fmt_fields, 973 /* bits */ 128, 974 /* flags */ 0, 975 }, 976 #endif /* chips */ 977 978 #if defined(BCM_56640_A0) 979 { /* SOC_FORMAT_INT_HIGIG2_BCM56640_A0fmt */ 980 /* format HIGIG2fmt */ 981 /* nFields */ 78, 982 /* *fields */ soc_HIGIG2_BCM56640_A0fmt_fields, 983 /* bits */ 128, 984 /* flags */ 0, 985 }, 986 #endif /* chips */ 987 988 #if defined(BCM_56670_A0) 989 { /* SOC_FORMAT_INT_HIGIG2_BCM56670_A0fmt */ 990 /* format HIGIG2fmt */ 991 /* nFields */ 77, 992 /* *fields */ soc_HIGIG2_BCM56560_A0fmt_fields, 993 /* bits */ 128, 994 /* flags */ 0, 995 }, 996 #endif /* chips */ 997 998 #if defined(BCM_56670_B0) 999 { /* SOC_FORMAT_INT_HIGIG2_BCM56670_B0fmt */ 1000 /* format HIGIG2fmt */ 1001 /* nFields */ 77, 1002 /* *fields */ soc_HIGIG2_BCM56560_A0fmt_fields, 1003 /* bits */ 128, 1004 /* flags */ 0, 1005 }, 1006 #endif /* chips */ 1007 1008 #if defined(BCM_56680_A0) 1009 { /* SOC_FORMAT_INT_HIGIG2_BCM56680_A0fmt */ 1010 /* format HIGIG2fmt */ 1011 /* nFields */ 32, 1012 /* *fields */ soc_HIGIG2_BCM56624_A0fmt_fields, 1013 /* bits */ 128, 1014 /* flags */ 0, 1015 }, 1016 #endif /* chips */ 1017 1018 #if defined(BCM_56680_B0) 1019 { /* SOC_FORMAT_INT_HIGIG2_BCM56680_B0fmt */ 1020 /* format HIGIG2fmt */ 1021 /* nFields */ 32, 1022 /* *fields */ soc_HIGIG2_BCM56624_A0fmt_fields, 1023 /* bits */ 128, 1024 /* flags */ 0, 1025 }, 1026 #endif /* chips */ 1027 1028 #if defined(BCM_56685_A0) 1029 { /* SOC_FORMAT_INT_HIGIG2_BCM56685_A0fmt */ 1030 /* format HIGIG2fmt */ 1031 /* nFields */ 74, 1032 /* *fields */ soc_HIGIG2_BCM56634_A0fmt_fields, 1033 /* bits */ 128, 1034 /* flags */ 0, 1035 }, 1036 #endif /* chips */ 1037 1038 #if defined(BCM_56685_B0) 1039 { /* SOC_FORMAT_INT_HIGIG2_BCM56685_B0fmt */ 1040 /* format HIGIG2fmt */ 1041 /* nFields */ 74, 1042 /* *fields */ soc_HIGIG2_BCM56634_A0fmt_fields, 1043 /* bits */ 128, 1044 /* flags */ 0, 1045 }, 1046 #endif /* chips */ 1047 1048 #if defined(BCM_56770_A0) 1049 { /* SOC_FORMAT_INT_HIGIG2_BCM56770_A0fmt */ 1050 /* format HIGIG2fmt */ 1051 /* nFields */ 80, 1052 /* *fields */ soc_HIGIG2_BCM56870_A0fmt_fields, 1053 /* bits */ 128, 1054 /* flags */ 0, 1055 }, 1056 #endif /* chips */ 1057 1058 #if defined(BCM_56840_A0) 1059 { /* SOC_FORMAT_INT_HIGIG2_BCM56840_A0fmt */ 1060 /* format HIGIG2fmt */ 1061 /* nFields */ 74, 1062 /* *fields */ soc_HIGIG2_BCM56634_A0fmt_fields, 1063 /* bits */ 128, 1064 /* flags */ 0, 1065 }, 1066 #endif /* chips */ 1067 1068 #if defined(BCM_56840_B0) 1069 { /* SOC_FORMAT_INT_HIGIG2_BCM56840_B0fmt */ 1070 /* format HIGIG2fmt */ 1071 /* nFields */ 74, 1072 /* *fields */ soc_HIGIG2_BCM56634_A0fmt_fields, 1073 /* bits */ 128, 1074 /* flags */ 0, 1075 }, 1076 #endif /* chips */ 1077 1078 #if defined(BCM_56850_A0) 1079 { /* SOC_FORMAT_INT_HIGIG2_BCM56850_A0fmt */ 1080 /* format HIGIG2fmt */ 1081 /* nFields */ 77, 1082 /* *fields */ soc_HIGIG2_BCM56850_A0fmt_fields, 1083 /* bits */ 128, 1084 /* flags */ 0, 1085 }, 1086 #endif /* chips */ 1087 1088 #if defined(BCM_56860_A0) 1089 { /* SOC_FORMAT_INT_HIGIG2_BCM56860_A0fmt */ 1090 /* format HIGIG2fmt */ 1091 /* nFields */ 77, 1092 /* *fields */ soc_HIGIG2_BCM56850_A0fmt_fields, 1093 /* bits */ 128, 1094 /* flags */ 0, 1095 }, 1096 #endif /* chips */ 1097 1098 #if defined(BCM_56870_A0) 1099 { /* SOC_FORMAT_INT_HIGIG2_BCM56870_A0fmt */ 1100 /* format HIGIG2fmt */ 1101 /* nFields */ 80, 1102 /* *fields */ soc_HIGIG2_BCM56870_A0fmt_fields, 1103 /* bits */ 128, 1104 /* flags */ 0, 1105 }, 1106 #endif /* chips */ 1107 1108 #if defined(BCM_56960_A0) 1109 { /* SOC_FORMAT_INT_HIGIG2_BCM56960_A0fmt */ 1110 /* format HIGIG2fmt */ 1111 /* nFields */ 78, 1112 /* *fields */ soc_HIGIG2_BCM56960_A0fmt_fields, 1113 /* bits */ 128, 1114 /* flags */ 0, 1115 }, 1116 #endif /* chips */ 1117 1118 #if defined(BCM_56965_A0) 1119 { /* SOC_FORMAT_INT_HIGIG2_BCM56965_A0fmt */ 1120 /* format HIGIG2fmt */ 1121 /* nFields */ 78, 1122 /* *fields */ soc_HIGIG2_BCM56960_A0fmt_fields, 1123 /* bits */ 128, 1124 /* flags */ 0, 1125 }, 1126 #endif /* chips */ 1127 1128 #if defined(BCM_56970_A0) 1129 { /* SOC_FORMAT_INT_HIGIG2_BCM56970_A0fmt */ 1130 /* format HIGIG2fmt */ 1131 /* nFields */ 78, 1132 /* *fields */ soc_HIGIG2_BCM56960_A0fmt_fields, 1133 /* bits */ 128, 1134 /* flags */ 0, 1135 }, 1136 #endif /* chips */ 1137 1138 #if defined(BCM_56980_A0) 1139 { /* SOC_FORMAT_INT_HIGIG2_BCM56980_A0fmt */ 1140 /* format HIGIG2fmt */ 1141 /* nFields */ 78, 1142 /* *fields */ soc_HIGIG2_BCM56960_A0fmt_fields, 1143 /* bits */ 128, 1144 /* flags */ 0, 1145 }, 1146 #endif /* chips */ 1147 1148 #if defined(BCM_56980_B0) 1149 { /* SOC_FORMAT_INT_HIGIG2_BCM56980_B0fmt */ 1150 /* format HIGIG2fmt */ 1151 /* nFields */ 78, 1152 /* *fields */ soc_HIGIG2_BCM56960_A0fmt_fields, 1153 /* bits */ 128, 1154 /* flags */ 0, 1155 }, 1156 #endif /* chips */ 1157 1158 #if defined(BCM_88732_A0) 1159 { /* SOC_FORMAT_INT_HIGIG2_BCM88732_A0fmt */ 1160 /* format HIGIG2fmt */ 1161 /* nFields */ 31, 1162 /* *fields */ soc_HIGIG2fmt_fields, 1163 /* bits */ 128, 1164 /* flags */ 0, 1165 }, 1166 #endif /* chips */ 1167 1168 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 1169 defined(BCM_56870_A0) 1170 { /* SOC_FORMAT_INT_HIGIG_AUX_HDR_BITMAPfmt */ 1171 /* format HIGIG_AUX_HDR_BITMAPfmt */ 1172 /* nFields */ 12, 1173 /* *fields */ soc_HIGIG_AUX_HDR_BITMAPfmt_fields, 1174 /* bits */ 12, 1175 /* flags */ 0, 1176 }, 1177 #endif /* chips */ 1178 1179 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 1180 defined(BCM_56870_A0) 1181 { /* SOC_FORMAT_INT_HIGIG_CHANGE_DEST_ACTION_SETfmt */ 1182 /* format HIGIG_CHANGE_DEST_ACTION_SETfmt */ 1183 /* nFields */ 5, 1184 /* *fields */ soc_HIGIG_CHANGE_DEST_ACTION_SETfmt_fields, 1185 /* bits */ 20, 1186 /* flags */ 0, 1187 }, 1188 #endif /* chips */ 1189 1190 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 1191 defined(BCM_56870_A0) 1192 { /* SOC_FORMAT_INT_HIGIG_CONTROLS_ACTION_SETfmt */ 1193 /* format HIGIG_CONTROLS_ACTION_SETfmt */ 1194 /* nFields */ 4, 1195 /* *fields */ soc_HIGIG_CONTROLS_ACTION_SETfmt_fields, 1196 /* bits */ 4, 1197 /* flags */ 0, 1198 }, 1199 #endif /* chips */ 1200 1201 #if defined(BCM_56340_A0) || defined(BCM_56640_A0) 1202 { /* SOC_FORMAT_INT_HITREQ_BUSfmt */ 1203 /* format HITREQ_BUSfmt */ 1204 /* nFields */ 5, 1205 /* *fields */ soc_HITREQ_BUSfmt_fields, 1206 /* bits */ 64, 1207 /* flags */ 0, 1208 }, 1209 #endif /* chips */ 1210 1211 #if defined(BCM_56640_A0) 1212 { /* SOC_FORMAT_INT_HITREQ_BUS_C_MODELfmt */ 1213 /* format HITREQ_BUS_C_MODELfmt */ 1214 /* nFields */ 5, 1215 /* *fields */ soc_HITREQ_BUSfmt_fields, 1216 /* bits */ 64, 1217 /* flags */ 0, 1218 }, 1219 #endif /* chips */ 1220 1221 #if defined(BCM_56340_A0) 1222 { /* SOC_FORMAT_INT_HITREQ_BUS_C_MODEL_BCM56340_A0fmt */ 1223 /* format HITREQ_BUS_C_MODELfmt */ 1224 /* nFields */ 5, 1225 /* *fields */ soc_HITREQ_BUSfmt_fields, 1226 /* bits */ 64, 1227 /* flags */ 0, 1228 }, 1229 #endif /* chips */ 1230 1231 #if defined(BCM_56640_A0) 1232 { /* SOC_FORMAT_INT_HITRST_BUSfmt */ 1233 /* format HITRST_BUSfmt */ 1234 /* nFields */ 1, 1235 /* *fields */ soc_BANK_HITRST_BUS_OUTfmt_fields, 1236 /* bits */ 12, 1237 /* flags */ 0, 1238 }, 1239 #endif /* chips */ 1240 1241 #if defined(BCM_56340_A0) 1242 { /* SOC_FORMAT_INT_HITRST_BUS_BCM56340_A0fmt */ 1243 /* format HITRST_BUSfmt */ 1244 /* nFields */ 1, 1245 /* *fields */ soc_BANK_HITRST_BUS_OUTfmt_fields, 1246 /* bits */ 12, 1247 /* flags */ 0, 1248 }, 1249 #endif /* chips */ 1250 1251 #if defined(BCM_56640_A0) 1252 { /* SOC_FORMAT_INT_HITRST_BUS_C_MODELfmt */ 1253 /* format HITRST_BUS_C_MODELfmt */ 1254 /* nFields */ 1, 1255 /* *fields */ soc_BANK_HITRST_BUS_OUTfmt_fields, 1256 /* bits */ 12, 1257 /* flags */ 0, 1258 }, 1259 #endif /* chips */ 1260 1261 #if defined(BCM_56340_A0) 1262 { /* SOC_FORMAT_INT_HITRST_BUS_C_MODEL_BCM56340_A0fmt */ 1263 /* format HITRST_BUS_C_MODELfmt */ 1264 /* nFields */ 1, 1265 /* *fields */ soc_BANK_HITRST_BUS_OUTfmt_fields, 1266 /* bits */ 12, 1267 /* flags */ 0, 1268 }, 1269 #endif /* chips */ 1270 1271 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 1272 defined(BCM_56870_A0) 1273 { /* SOC_FORMAT_INT_HVE0_BUSfmt */ 1274 /* format HVE0_BUSfmt */ 1275 /* nFields */ 13, 1276 /* *fields */ soc_HVE0_BUSfmt_fields, 1277 /* bits */ 20, 1278 /* flags */ 0, 1279 }, 1280 #endif /* chips */ 1281 1282 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 1283 defined(BCM_56870_A0) 1284 { /* SOC_FORMAT_INT_HVE0_IN_BUSfmt */ 1285 /* format HVE0_IN_BUSfmt */ 1286 /* nFields */ 2, 1287 /* *fields */ soc_HVE0_IN_BUSfmt_fields, 1288 /* bits */ 43, 1289 /* flags */ 0, 1290 }, 1291 #endif /* chips */ 1292 1293 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) 1294 { /* SOC_FORMAT_INT_HVE_DOS_ATTACK_RESULTS_FORMATfmt */ 1295 /* format HVE_DOS_ATTACK_RESULTS_FORMATfmt */ 1296 /* nFields */ 15, 1297 /* *fields */ soc_HVE_DOS_ATTACK_RESULTS_FORMATfmt_fields, 1298 /* bits */ 20, 1299 /* flags */ 0, 1300 }, 1301 #endif /* chips */ 1302 1303 #if defined(BCM_56370_A0) 1304 { /* SOC_FORMAT_INT_HVE_DOS_ATTACK_RESULTS_FORMAT_BCM56370_A0fmt */ 1305 /* format HVE_DOS_ATTACK_RESULTS_FORMATfmt */ 1306 /* nFields */ 29, 1307 /* *fields */ soc_HVE_DOS_ATTACK_RESULTS_FORMAT_BCM56370_A0fmt_fields, 1308 /* bits */ 32, 1309 /* flags */ 0, 1310 }, 1311 #endif /* chips */ 1312 1313 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 1314 defined(BCM_56870_A0) 1315 { /* SOC_FORMAT_INT_HVE_IN_BUSfmt */ 1316 /* format HVE_IN_BUSfmt */ 1317 /* nFields */ 2, 1318 /* *fields */ soc_HVE_IN_BUSfmt_fields, 1319 /* bits */ 65, 1320 /* flags */ 0, 1321 }, 1322 #endif /* chips */ 1323 1324 #if defined(BCM_56870_A0) 1325 { /* SOC_FORMAT_INT_HVE_RESULTS_FORMATfmt */ 1326 /* format HVE_RESULTS_FORMATfmt */ 1327 /* nFields */ 123, 1328 /* *fields */ soc_HVE_RESULTS_FORMATfmt_fields, 1329 /* bits */ 182, 1330 /* flags */ 0, 1331 }, 1332 #endif /* chips */ 1333 1334 #if defined(BCM_56370_A0) 1335 { /* SOC_FORMAT_INT_HVE_RESULTS_FORMAT_BCM56370_A0fmt */ 1336 /* format HVE_RESULTS_FORMATfmt */ 1337 /* nFields */ 125, 1338 /* *fields */ soc_HVE_RESULTS_FORMAT_BCM56370_A0fmt_fields, 1339 /* bits */ 182, 1340 /* flags */ 0, 1341 }, 1342 #endif /* chips */ 1343 1344 #if defined(BCM_56770_A0) 1345 { /* SOC_FORMAT_INT_HVE_RESULTS_FORMAT_BCM56770_A0fmt */ 1346 /* format HVE_RESULTS_FORMATfmt */ 1347 /* nFields */ 125, 1348 /* *fields */ soc_HVE_RESULTS_FORMAT_BCM56370_A0fmt_fields, 1349 /* bits */ 182, 1350 /* flags */ 0, 1351 }, 1352 #endif /* chips */ 1353 1354 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) 1355 { /* SOC_FORMAT_INT_HVE_RESULT_BUS_1_DOPfmt */ 1356 /* format HVE_RESULT_BUS_1_DOPfmt */ 1357 /* nFields */ 3, 1358 /* *fields */ soc_HVE_RESULT_BUS_1_DOPfmt_fields, 1359 /* bits */ 192, 1360 /* flags */ 0, 1361 }, 1362 #endif /* chips */ 1363 1364 #if defined(BCM_56370_A0) 1365 { /* SOC_FORMAT_INT_HVE_RESULT_BUS_1_DOP_BCM56370_A0fmt */ 1366 /* format HVE_RESULT_BUS_1_DOPfmt */ 1367 /* nFields */ 3, 1368 /* *fields */ soc_HVE_RESULT_BUS_1_DOP_BCM56370_A0fmt_fields, 1369 /* bits */ 192, 1370 /* flags */ 0, 1371 }, 1372 #endif /* chips */ 1373