allformats_e.i (716981B)
1 /* 2 * DO NOT EDIT THIS FILE! 3 * This file is auto-generated from the registers file. 4 * Edits to this file will be lost when it is regenerated. 5 * 6 * 7 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 8 * 9 * Copyright 2007-2020 Broadcom Inc. All rights reserved. 10 * 11 * File: allformats_e.i 12 * Purpose: Independent format descriptions. 13 */ 14 15 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) 16 { /* SOC_FORMAT_INT_E2EFC_TO_CFG_INFOfmt */ 17 /* format E2EFC_TO_CFG_INFOfmt */ 18 /* nFields */ 1, 19 /* *fields */ soc_E2EFC_TO_CFG_INFOfmt_fields, 20 /* bits */ 3, 21 /* flags */ 0, 22 }, 23 #endif /* chips */ 24 25 #if defined(BCM_56260_A0) 26 { /* SOC_FORMAT_INT_E2EFC_TO_CFG_INFO_BCM56260_A0fmt */ 27 /* format E2EFC_TO_CFG_INFOfmt */ 28 /* nFields */ 1, 29 /* *fields */ soc_E2EFC_TO_CFG_INFO_BCM56260_A0fmt_fields, 30 /* bits */ 3, 31 /* flags */ 0, 32 }, 33 #endif /* chips */ 34 35 #if defined(BCM_56260_B0) 36 { /* SOC_FORMAT_INT_E2EFC_TO_CFG_INFO_BCM56260_B0fmt */ 37 /* format E2EFC_TO_CFG_INFOfmt */ 38 /* nFields */ 1, 39 /* *fields */ soc_E2EFC_TO_CFG_INFO_BCM56260_A0fmt_fields, 40 /* bits */ 3, 41 /* flags */ 0, 42 }, 43 #endif /* chips */ 44 45 #if defined(BCM_56270_A0) 46 { /* SOC_FORMAT_INT_E2EFC_TO_CFG_INFO_BCM56270_A0fmt */ 47 /* format E2EFC_TO_CFG_INFOfmt */ 48 /* nFields */ 1, 49 /* *fields */ soc_E2EFC_TO_CFG_INFO_BCM56260_A0fmt_fields, 50 /* bits */ 3, 51 /* flags */ 0, 52 }, 53 #endif /* chips */ 54 55 #if defined(BCM_56450_A0) 56 { /* SOC_FORMAT_INT_E2EFC_TO_CFG_INFO_BCM56450_A0fmt */ 57 /* format E2EFC_TO_CFG_INFOfmt */ 58 /* nFields */ 1, 59 /* *fields */ soc_E2EFC_TO_CFG_INFO_BCM56450_A0fmt_fields, 60 /* bits */ 3, 61 /* flags */ 0, 62 }, 63 #endif /* chips */ 64 65 #if defined(BCM_56450_B0) 66 { /* SOC_FORMAT_INT_E2EFC_TO_CFG_INFO_BCM56450_B0fmt */ 67 /* format E2EFC_TO_CFG_INFOfmt */ 68 /* nFields */ 1, 69 /* *fields */ soc_E2EFC_TO_CFG_INFO_BCM56450_A0fmt_fields, 70 /* bits */ 3, 71 /* flags */ 0, 72 }, 73 #endif /* chips */ 74 75 #if defined(BCM_56450_B1) 76 { /* SOC_FORMAT_INT_E2EFC_TO_CFG_INFO_BCM56450_B1fmt */ 77 /* format E2EFC_TO_CFG_INFOfmt */ 78 /* nFields */ 1, 79 /* *fields */ soc_E2EFC_TO_CFG_INFO_BCM56450_A0fmt_fields, 80 /* bits */ 3, 81 /* flags */ 0, 82 }, 83 #endif /* chips */ 84 85 #if defined(BCM_56524_A0) || defined(BCM_56634_A0) || \ 86 defined(BCM_56634_B0) 87 { /* SOC_FORMAT_INT_E2EFC_TO_ENQ_INFO_BUSfmt */ 88 /* format E2EFC_TO_ENQ_INFO_BUSfmt */ 89 /* nFields */ 4, 90 /* *fields */ soc_E2EFC_TO_ENQ_INFO_BUSfmt_fields, 91 /* bits */ 15, 92 /* flags */ 0, 93 }, 94 #endif /* chips */ 95 96 #if defined(BCM_56260_A0) 97 { /* SOC_FORMAT_INT_E2EFC_TO_ENQ_INFO_BUS_BCM56260_A0fmt */ 98 /* format E2EFC_TO_ENQ_INFO_BUSfmt */ 99 /* nFields */ 2, 100 /* *fields */ soc_E2EFC_TO_ENQ_INFO_BUS_BCM56260_A0fmt_fields, 101 /* bits */ 6, 102 /* flags */ 0, 103 }, 104 #endif /* chips */ 105 106 #if defined(BCM_56260_B0) 107 { /* SOC_FORMAT_INT_E2EFC_TO_ENQ_INFO_BUS_BCM56260_B0fmt */ 108 /* format E2EFC_TO_ENQ_INFO_BUSfmt */ 109 /* nFields */ 2, 110 /* *fields */ soc_E2EFC_TO_ENQ_INFO_BUS_BCM56260_A0fmt_fields, 111 /* bits */ 6, 112 /* flags */ 0, 113 }, 114 #endif /* chips */ 115 116 #if defined(BCM_56270_A0) 117 { /* SOC_FORMAT_INT_E2EFC_TO_ENQ_INFO_BUS_BCM56270_A0fmt */ 118 /* format E2EFC_TO_ENQ_INFO_BUSfmt */ 119 /* nFields */ 2, 120 /* *fields */ soc_E2EFC_TO_ENQ_INFO_BUS_BCM56260_A0fmt_fields, 121 /* bits */ 6, 122 /* flags */ 0, 123 }, 124 #endif /* chips */ 125 126 #if defined(BCM_56440_A0) 127 { /* SOC_FORMAT_INT_E2EFC_TO_ENQ_INFO_BUS_BCM56440_A0fmt */ 128 /* format E2EFC_TO_ENQ_INFO_BUSfmt */ 129 /* nFields */ 2, 130 /* *fields */ soc_E2EFC_TO_ENQ_INFO_BUS_BCM56440_A0fmt_fields, 131 /* bits */ 7, 132 /* flags */ 0, 133 }, 134 #endif /* chips */ 135 136 #if defined(BCM_56440_B0) 137 { /* SOC_FORMAT_INT_E2EFC_TO_ENQ_INFO_BUS_BCM56440_B0fmt */ 138 /* format E2EFC_TO_ENQ_INFO_BUSfmt */ 139 /* nFields */ 2, 140 /* *fields */ soc_E2EFC_TO_ENQ_INFO_BUS_BCM56440_A0fmt_fields, 141 /* bits */ 7, 142 /* flags */ 0, 143 }, 144 #endif /* chips */ 145 146 #if defined(BCM_56450_A0) 147 { /* SOC_FORMAT_INT_E2EFC_TO_ENQ_INFO_BUS_BCM56450_A0fmt */ 148 /* format E2EFC_TO_ENQ_INFO_BUSfmt */ 149 /* nFields */ 2, 150 /* *fields */ soc_E2EFC_TO_ENQ_INFO_BUS_BCM56450_A0fmt_fields, 151 /* bits */ 7, 152 /* flags */ 0, 153 }, 154 #endif /* chips */ 155 156 #if defined(BCM_56450_B0) 157 { /* SOC_FORMAT_INT_E2EFC_TO_ENQ_INFO_BUS_BCM56450_B0fmt */ 158 /* format E2EFC_TO_ENQ_INFO_BUSfmt */ 159 /* nFields */ 2, 160 /* *fields */ soc_E2EFC_TO_ENQ_INFO_BUS_BCM56450_A0fmt_fields, 161 /* bits */ 7, 162 /* flags */ 0, 163 }, 164 #endif /* chips */ 165 166 #if defined(BCM_56450_B1) 167 { /* SOC_FORMAT_INT_E2EFC_TO_ENQ_INFO_BUS_BCM56450_B1fmt */ 168 /* format E2EFC_TO_ENQ_INFO_BUSfmt */ 169 /* nFields */ 2, 170 /* *fields */ soc_E2EFC_TO_ENQ_INFO_BUS_BCM56450_A0fmt_fields, 171 /* bits */ 7, 172 /* flags */ 0, 173 }, 174 #endif /* chips */ 175 176 #if defined(BCM_56524_B0) 177 { /* SOC_FORMAT_INT_E2EFC_TO_ENQ_INFO_BUS_BCM56524_B0fmt */ 178 /* format E2EFC_TO_ENQ_INFO_BUSfmt */ 179 /* nFields */ 4, 180 /* *fields */ soc_E2EFC_TO_ENQ_INFO_BUSfmt_fields, 181 /* bits */ 15, 182 /* flags */ 0, 183 }, 184 #endif /* chips */ 185 186 #if defined(BCM_56685_A0) 187 { /* SOC_FORMAT_INT_E2EFC_TO_ENQ_INFO_BUS_BCM56685_A0fmt */ 188 /* format E2EFC_TO_ENQ_INFO_BUSfmt */ 189 /* nFields */ 4, 190 /* *fields */ soc_E2EFC_TO_ENQ_INFO_BUSfmt_fields, 191 /* bits */ 15, 192 /* flags */ 0, 193 }, 194 #endif /* chips */ 195 196 #if defined(BCM_56685_B0) 197 { /* SOC_FORMAT_INT_E2EFC_TO_ENQ_INFO_BUS_BCM56685_B0fmt */ 198 /* format E2EFC_TO_ENQ_INFO_BUSfmt */ 199 /* nFields */ 4, 200 /* *fields */ soc_E2EFC_TO_ENQ_INFO_BUSfmt_fields, 201 /* bits */ 15, 202 /* flags */ 0, 203 }, 204 #endif /* chips */ 205 206 #if defined(BCM_56860_A0) 207 { /* SOC_FORMAT_INT_E2E_HOL_STATUS_COV_DEFSfmt */ 208 /* format E2E_HOL_STATUS_COV_DEFSfmt */ 209 /* nFields */ 8, 210 /* *fields */ soc_E2E_HOL_STATUS_COV_DEFSfmt_fields, 211 /* bits */ 21, 212 /* flags */ 0, 213 }, 214 #endif /* chips */ 215 216 #if defined(BCM_56560_A0) 217 { /* SOC_FORMAT_INT_E2E_HOL_STATUS_COV_DEFS_BCM56560_A0fmt */ 218 /* format E2E_HOL_STATUS_COV_DEFSfmt */ 219 /* nFields */ 8, 220 /* *fields */ soc_E2E_HOL_STATUS_COV_DEFS_BCM56560_A0fmt_fields, 221 /* bits */ 21, 222 /* flags */ 0, 223 }, 224 #endif /* chips */ 225 226 #if defined(BCM_56560_B0) 227 { /* SOC_FORMAT_INT_E2E_HOL_STATUS_COV_DEFS_BCM56560_B0fmt */ 228 /* format E2E_HOL_STATUS_COV_DEFSfmt */ 229 /* nFields */ 8, 230 /* *fields */ soc_E2E_HOL_STATUS_COV_DEFS_BCM56560_A0fmt_fields, 231 /* bits */ 21, 232 /* flags */ 0, 233 }, 234 #endif /* chips */ 235 236 #if defined(BCM_56670_A0) 237 { /* SOC_FORMAT_INT_E2E_HOL_STATUS_COV_DEFS_BCM56670_A0fmt */ 238 /* format E2E_HOL_STATUS_COV_DEFSfmt */ 239 /* nFields */ 8, 240 /* *fields */ soc_E2E_HOL_STATUS_COV_DEFS_BCM56560_A0fmt_fields, 241 /* bits */ 21, 242 /* flags */ 0, 243 }, 244 #endif /* chips */ 245 246 #if defined(BCM_56670_B0) 247 { /* SOC_FORMAT_INT_E2E_HOL_STATUS_COV_DEFS_BCM56670_B0fmt */ 248 /* format E2E_HOL_STATUS_COV_DEFSfmt */ 249 /* nFields */ 8, 250 /* *fields */ soc_E2E_HOL_STATUS_COV_DEFS_BCM56560_A0fmt_fields, 251 /* bits */ 21, 252 /* flags */ 0, 253 }, 254 #endif /* chips */ 255 256 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 257 { /* SOC_FORMAT_INT_EARB_TO_EPOST_CTRL_BUSfmt */ 258 /* format EARB_TO_EPOST_CTRL_BUSfmt */ 259 /* nFields */ 15, 260 /* *fields */ soc_EARB_TO_EPOST_CTRL_BUSfmt_fields, 261 /* bits */ 57, 262 /* flags */ 0, 263 }, 264 #endif /* chips */ 265 266 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 267 { /* SOC_FORMAT_INT_EARB_TO_EPOST_DATA_BUSfmt */ 268 /* format EARB_TO_EPOST_DATA_BUSfmt */ 269 /* nFields */ 2, 270 /* *fields */ soc_EARB_TO_EPOST_DATA_BUSfmt_fields, 271 /* bits */ 2048, 272 /* flags */ 0, 273 }, 274 #endif /* chips */ 275 276 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 277 defined(BCM_56870_A0) 278 { /* SOC_FORMAT_INT_ECMP_DLB_ACTION_SETfmt */ 279 /* format ECMP_DLB_ACTION_SETfmt */ 280 /* nFields */ 2, 281 /* *fields */ soc_ECMP_DLB_ACTION_SETfmt_fields, 282 /* bits */ 2, 283 /* flags */ 0, 284 }, 285 #endif /* chips */ 286 287 #if defined(BCM_56870_A0) 288 { /* SOC_FORMAT_INT_ECMP_RH_ACTION_SETfmt */ 289 /* format ECMP_RH_ACTION_SETfmt */ 290 /* nFields */ 2, 291 /* *fields */ soc_ECMP_DLB_ACTION_SETfmt_fields, 292 /* bits */ 2, 293 /* flags */ 0, 294 }, 295 #endif /* chips */ 296 297 #if defined(BCM_56370_A0) 298 { /* SOC_FORMAT_INT_ECMP_RH_ACTION_SET_BCM56370_A0fmt */ 299 /* format ECMP_RH_ACTION_SETfmt */ 300 /* nFields */ 2, 301 /* *fields */ soc_ECMP_DLB_ACTION_SETfmt_fields, 302 /* bits */ 2, 303 /* flags */ 0, 304 }, 305 #endif /* chips */ 306 307 #if defined(BCM_56770_A0) 308 { /* SOC_FORMAT_INT_ECMP_RH_ACTION_SET_BCM56770_A0fmt */ 309 /* format ECMP_RH_ACTION_SETfmt */ 310 /* nFields */ 2, 311 /* *fields */ soc_ECMP_DLB_ACTION_SETfmt_fields, 312 /* bits */ 2, 313 /* flags */ 0, 314 }, 315 #endif /* chips */ 316 317 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 318 defined(BCM_56870_A0) 319 { /* SOC_FORMAT_INT_ECN_ACTION_SETfmt */ 320 /* format ECN_ACTION_SETfmt */ 321 /* nFields */ 3, 322 /* *fields */ soc_ECN_ACTION_SETfmt_fields, 323 /* bits */ 3, 324 /* flags */ 0, 325 }, 326 #endif /* chips */ 327 328 #if defined(BCM_56440_A0) 329 { /* SOC_FORMAT_INT_EDATABUF_ALGN_TO_BUFFER_CTRLfmt */ 330 /* format EDATABUF_ALGN_TO_BUFFER_CTRLfmt */ 331 /* nFields */ 13, 332 /* *fields */ soc_EDATABUF_ALGN_TO_BUFFER_CTRLfmt_fields, 333 /* bits */ 29, 334 /* flags */ 0, 335 }, 336 #endif /* chips */ 337 338 #if defined(BCM_56260_A0) 339 { /* SOC_FORMAT_INT_EDATABUF_ALGN_TO_BUFFER_CTRL_BCM56260_A0fmt */ 340 /* format EDATABUF_ALGN_TO_BUFFER_CTRLfmt */ 341 /* nFields */ 13, 342 /* *fields */ soc_EDATABUF_ALGN_TO_BUFFER_CTRL_BCM56260_A0fmt_fields, 343 /* bits */ 29, 344 /* flags */ 0, 345 }, 346 #endif /* chips */ 347 348 #if defined(BCM_56260_B0) 349 { /* SOC_FORMAT_INT_EDATABUF_ALGN_TO_BUFFER_CTRL_BCM56260_B0fmt */ 350 /* format EDATABUF_ALGN_TO_BUFFER_CTRLfmt */ 351 /* nFields */ 13, 352 /* *fields */ soc_EDATABUF_ALGN_TO_BUFFER_CTRL_BCM56260_A0fmt_fields, 353 /* bits */ 29, 354 /* flags */ 0, 355 }, 356 #endif /* chips */ 357 358 #if defined(BCM_56270_A0) 359 { /* SOC_FORMAT_INT_EDATABUF_ALGN_TO_BUFFER_CTRL_BCM56270_A0fmt */ 360 /* format EDATABUF_ALGN_TO_BUFFER_CTRLfmt */ 361 /* nFields */ 13, 362 /* *fields */ soc_EDATABUF_ALGN_TO_BUFFER_CTRL_BCM56260_A0fmt_fields, 363 /* bits */ 29, 364 /* flags */ 0, 365 }, 366 #endif /* chips */ 367 368 #if defined(BCM_56440_B0) 369 { /* SOC_FORMAT_INT_EDATABUF_ALGN_TO_BUFFER_CTRL_BCM56440_B0fmt */ 370 /* format EDATABUF_ALGN_TO_BUFFER_CTRLfmt */ 371 /* nFields */ 13, 372 /* *fields */ soc_EDATABUF_ALGN_TO_BUFFER_CTRLfmt_fields, 373 /* bits */ 29, 374 /* flags */ 0, 375 }, 376 #endif /* chips */ 377 378 #if defined(BCM_56450_A0) 379 { /* SOC_FORMAT_INT_EDATABUF_ALGN_TO_BUFFER_CTRL_BCM56450_A0fmt */ 380 /* format EDATABUF_ALGN_TO_BUFFER_CTRLfmt */ 381 /* nFields */ 13, 382 /* *fields */ soc_EDATABUF_ALGN_TO_BUFFER_CTRL_BCM56450_A0fmt_fields, 383 /* bits */ 29, 384 /* flags */ 0, 385 }, 386 #endif /* chips */ 387 388 #if defined(BCM_56450_B0) 389 { /* SOC_FORMAT_INT_EDATABUF_ALGN_TO_BUFFER_CTRL_BCM56450_B0fmt */ 390 /* format EDATABUF_ALGN_TO_BUFFER_CTRLfmt */ 391 /* nFields */ 13, 392 /* *fields */ soc_EDATABUF_ALGN_TO_BUFFER_CTRL_BCM56450_A0fmt_fields, 393 /* bits */ 29, 394 /* flags */ 0, 395 }, 396 #endif /* chips */ 397 398 #if defined(BCM_56450_B1) 399 { /* SOC_FORMAT_INT_EDATABUF_ALGN_TO_BUFFER_CTRL_BCM56450_B1fmt */ 400 /* format EDATABUF_ALGN_TO_BUFFER_CTRLfmt */ 401 /* nFields */ 13, 402 /* *fields */ soc_EDATABUF_ALGN_TO_BUFFER_CTRL_BCM56450_A0fmt_fields, 403 /* bits */ 29, 404 /* flags */ 0, 405 }, 406 #endif /* chips */ 407 408 #if defined(BCM_56440_A0) 409 { /* SOC_FORMAT_INT_EDATABUF_BUFFER_TO_CMPORT_CTRLfmt */ 410 /* format EDATABUF_BUFFER_TO_CMPORT_CTRLfmt */ 411 /* nFields */ 5, 412 /* *fields */ soc_EDATABUF_BUFFER_TO_CMPORT_CTRLfmt_fields, 413 /* bits */ 11, 414 /* flags */ 0, 415 }, 416 #endif /* chips */ 417 418 #if defined(BCM_56260_A0) 419 { /* SOC_FORMAT_INT_EDATABUF_BUFFER_TO_CMPORT_CTRL_BCM56260_A0fmt */ 420 /* format EDATABUF_BUFFER_TO_CMPORT_CTRLfmt */ 421 /* nFields */ 5, 422 /* *fields */ soc_EDATABUF_BUFFER_TO_CMPORT_CTRL_BCM56260_A0fmt_fields, 423 /* bits */ 11, 424 /* flags */ 0, 425 }, 426 #endif /* chips */ 427 428 #if defined(BCM_56260_B0) 429 { /* SOC_FORMAT_INT_EDATABUF_BUFFER_TO_CMPORT_CTRL_BCM56260_B0fmt */ 430 /* format EDATABUF_BUFFER_TO_CMPORT_CTRLfmt */ 431 /* nFields */ 5, 432 /* *fields */ soc_EDATABUF_BUFFER_TO_CMPORT_CTRL_BCM56260_A0fmt_fields, 433 /* bits */ 11, 434 /* flags */ 0, 435 }, 436 #endif /* chips */ 437 438 #if defined(BCM_56270_A0) 439 { /* SOC_FORMAT_INT_EDATABUF_BUFFER_TO_CMPORT_CTRL_BCM56270_A0fmt */ 440 /* format EDATABUF_BUFFER_TO_CMPORT_CTRLfmt */ 441 /* nFields */ 5, 442 /* *fields */ soc_EDATABUF_BUFFER_TO_CMPORT_CTRL_BCM56260_A0fmt_fields, 443 /* bits */ 11, 444 /* flags */ 0, 445 }, 446 #endif /* chips */ 447 448 #if defined(BCM_56440_B0) 449 { /* SOC_FORMAT_INT_EDATABUF_BUFFER_TO_CMPORT_CTRL_BCM56440_B0fmt */ 450 /* format EDATABUF_BUFFER_TO_CMPORT_CTRLfmt */ 451 /* nFields */ 5, 452 /* *fields */ soc_EDATABUF_BUFFER_TO_CMPORT_CTRLfmt_fields, 453 /* bits */ 11, 454 /* flags */ 0, 455 }, 456 #endif /* chips */ 457 458 #if defined(BCM_56450_A0) 459 { /* SOC_FORMAT_INT_EDATABUF_BUFFER_TO_CMPORT_CTRL_BCM56450_A0fmt */ 460 /* format EDATABUF_BUFFER_TO_CMPORT_CTRLfmt */ 461 /* nFields */ 5, 462 /* *fields */ soc_EDATABUF_BUFFER_TO_CMPORT_CTRL_BCM56450_A0fmt_fields, 463 /* bits */ 11, 464 /* flags */ 0, 465 }, 466 #endif /* chips */ 467 468 #if defined(BCM_56450_B0) 469 { /* SOC_FORMAT_INT_EDATABUF_BUFFER_TO_CMPORT_CTRL_BCM56450_B0fmt */ 470 /* format EDATABUF_BUFFER_TO_CMPORT_CTRLfmt */ 471 /* nFields */ 5, 472 /* *fields */ soc_EDATABUF_BUFFER_TO_CMPORT_CTRL_BCM56450_A0fmt_fields, 473 /* bits */ 11, 474 /* flags */ 0, 475 }, 476 #endif /* chips */ 477 478 #if defined(BCM_56450_B1) 479 { /* SOC_FORMAT_INT_EDATABUF_BUFFER_TO_CMPORT_CTRL_BCM56450_B1fmt */ 480 /* format EDATABUF_BUFFER_TO_CMPORT_CTRLfmt */ 481 /* nFields */ 5, 482 /* *fields */ soc_EDATABUF_BUFFER_TO_CMPORT_CTRL_BCM56450_A0fmt_fields, 483 /* bits */ 11, 484 /* flags */ 0, 485 }, 486 #endif /* chips */ 487 488 #if defined(BCM_56440_A0) 489 { /* SOC_FORMAT_INT_EDATABUF_BUFFER_TO_GPORT_CTRLfmt */ 490 /* format EDATABUF_BUFFER_TO_GPORT_CTRLfmt */ 491 /* nFields */ 11, 492 /* *fields */ soc_EDATABUF_BUFFER_TO_GPORT_CTRLfmt_fields, 493 /* bits */ 26, 494 /* flags */ 0, 495 }, 496 #endif /* chips */ 497 498 #if defined(BCM_56440_B0) 499 { /* SOC_FORMAT_INT_EDATABUF_BUFFER_TO_GPORT_CTRL_BCM56440_B0fmt */ 500 /* format EDATABUF_BUFFER_TO_GPORT_CTRLfmt */ 501 /* nFields */ 11, 502 /* *fields */ soc_EDATABUF_BUFFER_TO_GPORT_CTRLfmt_fields, 503 /* bits */ 26, 504 /* flags */ 0, 505 }, 506 #endif /* chips */ 507 508 #if defined(BCM_56440_A0) 509 { /* SOC_FORMAT_INT_EDATABUF_BUFFER_TO_XQPORT_CTRLfmt */ 510 /* format EDATABUF_BUFFER_TO_XQPORT_CTRLfmt */ 511 /* nFields */ 11, 512 /* *fields */ soc_EDATABUF_BUFFER_TO_XQPORT_CTRLfmt_fields, 513 /* bits */ 25, 514 /* flags */ 0, 515 }, 516 #endif /* chips */ 517 518 #if defined(BCM_56260_A0) 519 { /* SOC_FORMAT_INT_EDATABUF_BUFFER_TO_XQPORT_CTRL_BCM56260_A0fmt */ 520 /* format EDATABUF_BUFFER_TO_XQPORT_CTRLfmt */ 521 /* nFields */ 11, 522 /* *fields */ soc_EDATABUF_BUFFER_TO_XQPORT_CTRL_BCM56260_A0fmt_fields, 523 /* bits */ 25, 524 /* flags */ 0, 525 }, 526 #endif /* chips */ 527 528 #if defined(BCM_56260_B0) 529 { /* SOC_FORMAT_INT_EDATABUF_BUFFER_TO_XQPORT_CTRL_BCM56260_B0fmt */ 530 /* format EDATABUF_BUFFER_TO_XQPORT_CTRLfmt */ 531 /* nFields */ 11, 532 /* *fields */ soc_EDATABUF_BUFFER_TO_XQPORT_CTRL_BCM56260_A0fmt_fields, 533 /* bits */ 25, 534 /* flags */ 0, 535 }, 536 #endif /* chips */ 537 538 #if defined(BCM_56270_A0) 539 { /* SOC_FORMAT_INT_EDATABUF_BUFFER_TO_XQPORT_CTRL_BCM56270_A0fmt */ 540 /* format EDATABUF_BUFFER_TO_XQPORT_CTRLfmt */ 541 /* nFields */ 11, 542 /* *fields */ soc_EDATABUF_BUFFER_TO_XQPORT_CTRL_BCM56260_A0fmt_fields, 543 /* bits */ 25, 544 /* flags */ 0, 545 }, 546 #endif /* chips */ 547 548 #if defined(BCM_56440_B0) 549 { /* SOC_FORMAT_INT_EDATABUF_BUFFER_TO_XQPORT_CTRL_BCM56440_B0fmt */ 550 /* format EDATABUF_BUFFER_TO_XQPORT_CTRLfmt */ 551 /* nFields */ 11, 552 /* *fields */ soc_EDATABUF_BUFFER_TO_XQPORT_CTRLfmt_fields, 553 /* bits */ 25, 554 /* flags */ 0, 555 }, 556 #endif /* chips */ 557 558 #if defined(BCM_56450_A0) 559 { /* SOC_FORMAT_INT_EDATABUF_BUFFER_TO_XQPORT_CTRL_BCM56450_A0fmt */ 560 /* format EDATABUF_BUFFER_TO_XQPORT_CTRLfmt */ 561 /* nFields */ 11, 562 /* *fields */ soc_EDATABUF_BUFFER_TO_XQPORT_CTRL_BCM56450_A0fmt_fields, 563 /* bits */ 25, 564 /* flags */ 0, 565 }, 566 #endif /* chips */ 567 568 #if defined(BCM_56450_B0) 569 { /* SOC_FORMAT_INT_EDATABUF_BUFFER_TO_XQPORT_CTRL_BCM56450_B0fmt */ 570 /* format EDATABUF_BUFFER_TO_XQPORT_CTRLfmt */ 571 /* nFields */ 11, 572 /* *fields */ soc_EDATABUF_BUFFER_TO_XQPORT_CTRL_BCM56450_A0fmt_fields, 573 /* bits */ 25, 574 /* flags */ 0, 575 }, 576 #endif /* chips */ 577 578 #if defined(BCM_56450_B1) 579 { /* SOC_FORMAT_INT_EDATABUF_BUFFER_TO_XQPORT_CTRL_BCM56450_B1fmt */ 580 /* format EDATABUF_BUFFER_TO_XQPORT_CTRLfmt */ 581 /* nFields */ 11, 582 /* *fields */ soc_EDATABUF_BUFFER_TO_XQPORT_CTRL_BCM56450_A0fmt_fields, 583 /* bits */ 25, 584 /* flags */ 0, 585 }, 586 #endif /* chips */ 587 588 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 589 { /* SOC_FORMAT_INT_EDB_TO_IDB_BYTE_COUNTfmt */ 590 /* format EDB_TO_IDB_BYTE_COUNTfmt */ 591 /* nFields */ 1, 592 /* *fields */ soc_EDB_TO_IDB_BYTE_COUNTfmt_fields, 593 /* bits */ 7, 594 /* flags */ 0, 595 }, 596 #endif /* chips */ 597 598 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 599 { /* SOC_FORMAT_INT_EDB_TO_IDB_DATAfmt */ 600 /* format EDB_TO_IDB_DATAfmt */ 601 /* nFields */ 1, 602 /* *fields */ soc_EDB_TO_IDB_DATAfmt_fields, 603 /* bits */ 257, 604 /* flags */ 0, 605 }, 606 #endif /* chips */ 607 608 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 609 { /* SOC_FORMAT_INT_EDB_TO_MMU_CREDIT_REQfmt */ 610 /* format EDB_TO_MMU_CREDIT_REQfmt */ 611 /* nFields */ 1, 612 /* *fields */ soc_EDB_TO_MMU_CREDIT_REQfmt_fields, 613 /* bits */ 35, 614 /* flags */ 0, 615 }, 616 #endif /* chips */ 617 618 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 619 { /* SOC_FORMAT_INT_EDB_TO_PM_1588_PT_BUSfmt */ 620 /* format EDB_TO_PM_1588_PT_BUSfmt */ 621 /* nFields */ 5, 622 /* *fields */ soc_EDB_TO_PM_1588_PT_BUSfmt_fields, 623 /* bits */ 12, 624 /* flags */ 0, 625 }, 626 #endif /* chips */ 627 628 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 629 { /* SOC_FORMAT_INT_EDB_TO_PM_BYTE_COUNTfmt */ 630 /* format EDB_TO_PM_BYTE_COUNTfmt */ 631 /* nFields */ 1, 632 /* *fields */ soc_EDB_TO_PM_BYTE_COUNTfmt_fields, 633 /* bits */ 5, 634 /* flags */ 0, 635 }, 636 #endif /* chips */ 637 638 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 639 { /* SOC_FORMAT_INT_EDB_TO_PM_DATA_BUSfmt */ 640 /* format EDB_TO_PM_DATA_BUSfmt */ 641 /* nFields */ 1, 642 /* *fields */ soc_EDB_TO_PM_DATA_BUSfmt_fields, 643 /* bits */ 512, 644 /* flags */ 0, 645 }, 646 #endif /* chips */ 647 648 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 649 { /* SOC_FORMAT_INT_EDB_TO_PM_PORT_NUMfmt */ 650 /* format EDB_TO_PM_PORT_NUMfmt */ 651 /* nFields */ 1, 652 /* *fields */ soc_EDB_TO_PM_PORT_NUMfmt_fields, 653 /* bits */ 3, 654 /* flags */ 0, 655 }, 656 #endif /* chips */ 657 658 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 659 defined(BCM_56870_A0) 660 { /* SOC_FORMAT_INT_EDITOR_CONTROL_BLOCK_IN_BUSfmt */ 661 /* format EDITOR_CONTROL_BLOCK_IN_BUSfmt */ 662 /* nFields */ 70, 663 /* *fields */ soc_EDITOR_CONTROL_BLOCK_IN_BUSfmt_fields, 664 /* bits */ 257, 665 /* flags */ 0, 666 }, 667 #endif /* chips */ 668 669 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 670 defined(BCM_56870_A0) 671 { /* SOC_FORMAT_INT_EDITOR_DROP_VECTOR_DOPfmt */ 672 /* format EDITOR_DROP_VECTOR_DOPfmt */ 673 /* nFields */ 3, 674 /* *fields */ soc_EDITOR_DROP_VECTOR_DOPfmt_fields, 675 /* bits */ 32, 676 /* flags */ 0, 677 }, 678 #endif /* chips */ 679 680 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 681 defined(BCM_56870_A0) 682 { /* SOC_FORMAT_INT_EDITOR_ENGINE_ID_ENCODING_FORMATfmt */ 683 /* format EDITOR_ENGINE_ID_ENCODING_FORMATfmt */ 684 /* nFields */ 1, 685 /* *fields */ soc_EDITOR_ENGINE_ID_ENCODING_FORMATfmt_fields, 686 /* bits */ 4, 687 /* flags */ 0, 688 }, 689 #endif /* chips */ 690 691 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) 692 { /* SOC_FORMAT_INT_EDIT_CTRL_ID_ACTION_SETfmt */ 693 /* format EDIT_CTRL_ID_ACTION_SETfmt */ 694 /* nFields */ 1, 695 /* *fields */ soc_EDIT_CTRL_ID_ACTION_SETfmt_fields, 696 /* bits */ 8, 697 /* flags */ 0, 698 }, 699 #endif /* chips */ 700 701 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 702 defined(BCM_56870_A0) 703 { /* SOC_FORMAT_INT_EDIT_CTRL_ID_SEL_ENCODING_FORMATfmt */ 704 /* format EDIT_CTRL_ID_SEL_ENCODING_FORMATfmt */ 705 /* nFields */ 1, 706 /* *fields */ soc_EDIT_CTRL_ID_SEL_ENCODING_FORMATfmt_fields, 707 /* bits */ 4, 708 /* flags */ 0, 709 }, 710 #endif /* chips */ 711 712 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \ 713 defined(BCM_56270_A0) 714 { /* SOC_FORMAT_INT_EFPMOD_PARITY_STATUS_BUSfmt */ 715 /* format EFPMOD_PARITY_STATUS_BUSfmt */ 716 /* nFields */ 3, 717 /* *fields */ soc_EFPMOD_PARITY_STATUS_BUSfmt_fields, 718 /* bits */ 6, 719 /* flags */ 0, 720 }, 721 #endif /* chips */ 722 723 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) 724 { /* SOC_FORMAT_INT_EFPMOD_PKT_ATTRfmt */ 725 /* format EFPMOD_PKT_ATTRfmt */ 726 /* nFields */ 32, 727 /* *fields */ soc_EFPMOD_PKT_ATTRfmt_fields, 728 /* bits */ 115, 729 /* flags */ 0, 730 }, 731 #endif /* chips */ 732 733 #if defined(BCM_56370_A0) 734 { /* SOC_FORMAT_INT_EFPMOD_PKT_ATTR_BCM56370_A0fmt */ 735 /* format EFPMOD_PKT_ATTRfmt */ 736 /* nFields */ 33, 737 /* *fields */ soc_EFPMOD_PKT_ATTR_BCM56370_A0fmt_fields, 738 /* bits */ 116, 739 /* flags */ 0, 740 }, 741 #endif /* chips */ 742 743 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 744 defined(BCM_56870_A0) 745 { /* SOC_FORMAT_INT_EFPMOD_PKT_HDRSfmt */ 746 /* format EFPMOD_PKT_HDRSfmt */ 747 /* nFields */ 8, 748 /* *fields */ soc_EFPMOD_PKT_HDRSfmt_fields, 749 /* bits */ 56, 750 /* flags */ 0, 751 }, 752 #endif /* chips */ 753 754 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) 755 { /* SOC_FORMAT_INT_EFPMOD_PKT_MOD_ACTIONSfmt */ 756 /* format EFPMOD_PKT_MOD_ACTIONSfmt */ 757 /* nFields */ 56, 758 /* *fields */ soc_EFPMOD_PKT_MOD_ACTIONSfmt_fields, 759 /* bits */ 333, 760 /* flags */ 0, 761 }, 762 #endif /* chips */ 763 764 #if defined(BCM_56370_A0) 765 { /* SOC_FORMAT_INT_EFPMOD_PKT_MOD_ACTIONS_BCM56370_A0fmt */ 766 /* format EFPMOD_PKT_MOD_ACTIONSfmt */ 767 /* nFields */ 56, 768 /* *fields */ soc_EFPMOD_PKT_MOD_ACTIONS_BCM56370_A0fmt_fields, 769 /* bits */ 333, 770 /* flags */ 0, 771 }, 772 #endif /* chips */ 773 774 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 775 { /* SOC_FORMAT_INT_EFPMOD_TO_EPOST_CTRL_BUSfmt */ 776 /* format EFPMOD_TO_EPOST_CTRL_BUSfmt */ 777 /* nFields */ 44, 778 /* *fields */ soc_EFPMOD_TO_EPOST_CTRL_BUSfmt_fields, 779 /* bits */ 572, 780 /* flags */ 0, 781 }, 782 #endif /* chips */ 783 784 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 785 { /* SOC_FORMAT_INT_EFPMOD_TO_EPOST_DATA_BUSfmt */ 786 /* format EFPMOD_TO_EPOST_DATA_BUSfmt */ 787 /* nFields */ 1, 788 /* *fields */ soc_EFPMOD_TO_EPOST_DATA_BUSfmt_fields, 789 /* bits */ 2608, 790 /* flags */ 0, 791 }, 792 #endif /* chips */ 793 794 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \ 795 defined(BCM_56270_A0) 796 { /* SOC_FORMAT_INT_EFPPARS_PARITY_STATUS_BUSfmt */ 797 /* format EFPPARS_PARITY_STATUS_BUSfmt */ 798 /* nFields */ 3, 799 /* *fields */ soc_EFPPARS_PARITY_STATUS_BUSfmt_fields, 800 /* bits */ 6, 801 /* flags */ 0, 802 }, 803 #endif /* chips */ 804 805 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 806 defined(BCM_56870_A0) 807 { /* SOC_FORMAT_INT_EFP_CLASSID_B_SELECTOR_SLICE_FORMATfmt */ 808 /* format EFP_CLASSID_B_SELECTOR_SLICE_FORMATfmt */ 809 /* nFields */ 1, 810 /* *fields */ soc_EFP_CLASSID_B_SELECTOR_SLICE_FORMATfmt_fields, 811 /* bits */ 4, 812 /* flags */ 0, 813 }, 814 #endif /* chips */ 815 816 #if defined(BCM_56340_A0) || defined(BCM_56640_A0) || \ 817 defined(BCM_56850_A0) || defined(BCM_56860_A0) 818 { /* SOC_FORMAT_INT_EFP_COUNTER_TABLE_COV_DEFSfmt */ 819 /* format EFP_COUNTER_TABLE_COV_DEFSfmt */ 820 /* nFields */ 6, 821 /* *fields */ soc_EFP_COUNTER_TABLE_COV_DEFSfmt_fields, 822 /* bits */ 16, 823 /* flags */ 0, 824 }, 825 #endif /* chips */ 826 827 #if defined(BCM_53400_A0) 828 { /* SOC_FORMAT_INT_EFP_COUNTER_TABLE_COV_DEFS_BCM53400_A0fmt */ 829 /* format EFP_COUNTER_TABLE_COV_DEFSfmt */ 830 /* nFields */ 6, 831 /* *fields */ soc_EFP_COUNTER_TABLE_COV_DEFS_BCM53400_A0fmt_fields, 832 /* bits */ 15, 833 /* flags */ 0, 834 }, 835 #endif /* chips */ 836 837 #if defined(BCM_53540_A0) 838 { /* SOC_FORMAT_INT_EFP_COUNTER_TABLE_COV_DEFS_BCM53540_A0fmt */ 839 /* format EFP_COUNTER_TABLE_COV_DEFSfmt */ 840 /* nFields */ 6, 841 /* *fields */ soc_EFP_COUNTER_TABLE_COV_DEFS_BCM53400_A0fmt_fields, 842 /* bits */ 15, 843 /* flags */ 0, 844 }, 845 #endif /* chips */ 846 847 #if defined(BCM_53570_A0) 848 { /* SOC_FORMAT_INT_EFP_COUNTER_TABLE_COV_DEFS_BCM53570_A0fmt */ 849 /* format EFP_COUNTER_TABLE_COV_DEFSfmt */ 850 /* nFields */ 6, 851 /* *fields */ soc_EFP_COUNTER_TABLE_COV_DEFS_BCM53400_A0fmt_fields, 852 /* bits */ 15, 853 /* flags */ 0, 854 }, 855 #endif /* chips */ 856 857 #if defined(BCM_53570_B0) 858 { /* SOC_FORMAT_INT_EFP_COUNTER_TABLE_COV_DEFS_BCM53570_B0fmt */ 859 /* format EFP_COUNTER_TABLE_COV_DEFSfmt */ 860 /* nFields */ 6, 861 /* *fields */ soc_EFP_COUNTER_TABLE_COV_DEFS_BCM53400_A0fmt_fields, 862 /* bits */ 15, 863 /* flags */ 0, 864 }, 865 #endif /* chips */ 866 867 #if defined(BCM_56150_A0) 868 { /* SOC_FORMAT_INT_EFP_COUNTER_TABLE_COV_DEFS_BCM56150_A0fmt */ 869 /* format EFP_COUNTER_TABLE_COV_DEFSfmt */ 870 /* nFields */ 6, 871 /* *fields */ soc_EGR_FRAGMENT_ID_TABLE_COV_DEFS_BCM56850_A0fmt_fields, 872 /* bits */ 15, 873 /* flags */ 0, 874 }, 875 #endif /* chips */ 876 877 #if defined(BCM_56160_A0) 878 { /* SOC_FORMAT_INT_EFP_COUNTER_TABLE_COV_DEFS_BCM56160_A0fmt */ 879 /* format EFP_COUNTER_TABLE_COV_DEFSfmt */ 880 /* nFields */ 6, 881 /* *fields */ soc_EFP_COUNTER_TABLE_COV_DEFS_BCM53400_A0fmt_fields, 882 /* bits */ 15, 883 /* flags */ 0, 884 }, 885 #endif /* chips */ 886 887 #if defined(BCM_56370_A0) 888 { /* SOC_FORMAT_INT_EFP_COUNTER_TABLE_COV_DEFS_BCM56370_A0fmt */ 889 /* format EFP_COUNTER_TABLE_COV_DEFSfmt */ 890 /* nFields */ 6, 891 /* *fields */ soc_EGR_PERQ_XMT_COUNTERS_COV_DEFS_BCM56960_A0fmt_fields, 892 /* bits */ 17, 893 /* flags */ 0, 894 }, 895 #endif /* chips */ 896 897 #if defined(BCM_56560_A0) 898 { /* SOC_FORMAT_INT_EFP_COUNTER_TABLE_COV_DEFS_BCM56560_A0fmt */ 899 /* format EFP_COUNTER_TABLE_COV_DEFSfmt */ 900 /* nFields */ 6, 901 /* *fields */ soc_EFP_COUNTER_TABLE_COV_DEFS_BCM56960_A0fmt_fields, 902 /* bits */ 16, 903 /* flags */ 0, 904 }, 905 #endif /* chips */ 906 907 #if defined(BCM_56560_B0) 908 { /* SOC_FORMAT_INT_EFP_COUNTER_TABLE_COV_DEFS_BCM56560_B0fmt */ 909 /* format EFP_COUNTER_TABLE_COV_DEFSfmt */ 910 /* nFields */ 6, 911 /* *fields */ soc_EFP_COUNTER_TABLE_COV_DEFS_BCM56960_A0fmt_fields, 912 /* bits */ 16, 913 /* flags */ 0, 914 }, 915 #endif /* chips */ 916 917 #if defined(BCM_56670_A0) 918 { /* SOC_FORMAT_INT_EFP_COUNTER_TABLE_COV_DEFS_BCM56670_A0fmt */ 919 /* format EFP_COUNTER_TABLE_COV_DEFSfmt */ 920 /* nFields */ 6, 921 /* *fields */ soc_EFP_COUNTER_TABLE_COV_DEFS_BCM56960_A0fmt_fields, 922 /* bits */ 16, 923 /* flags */ 0, 924 }, 925 #endif /* chips */ 926 927 #if defined(BCM_56670_B0) 928 { /* SOC_FORMAT_INT_EFP_COUNTER_TABLE_COV_DEFS_BCM56670_B0fmt */ 929 /* format EFP_COUNTER_TABLE_COV_DEFSfmt */ 930 /* nFields */ 6, 931 /* *fields */ soc_EFP_COUNTER_TABLE_COV_DEFS_BCM56960_A0fmt_fields, 932 /* bits */ 16, 933 /* flags */ 0, 934 }, 935 #endif /* chips */ 936 937 #if defined(BCM_56770_A0) 938 { /* SOC_FORMAT_INT_EFP_COUNTER_TABLE_COV_DEFS_BCM56770_A0fmt */ 939 /* format EFP_COUNTER_TABLE_COV_DEFSfmt */ 940 /* nFields */ 6, 941 /* *fields */ soc_EGR_PERQ_XMT_COUNTERS_COV_DEFS_BCM56960_A0fmt_fields, 942 /* bits */ 17, 943 /* flags */ 0, 944 }, 945 #endif /* chips */ 946 947 #if defined(BCM_56870_A0) 948 { /* SOC_FORMAT_INT_EFP_COUNTER_TABLE_COV_DEFS_BCM56870_A0fmt */ 949 /* format EFP_COUNTER_TABLE_COV_DEFSfmt */ 950 /* nFields */ 6, 951 /* *fields */ soc_EGR_PERQ_XMT_COUNTERS_COV_DEFS_BCM56960_A0fmt_fields, 952 /* bits */ 17, 953 /* flags */ 0, 954 }, 955 #endif /* chips */ 956 957 #if defined(BCM_56960_A0) 958 { /* SOC_FORMAT_INT_EFP_COUNTER_TABLE_COV_DEFS_BCM56960_A0fmt */ 959 /* format EFP_COUNTER_TABLE_COV_DEFSfmt */ 960 /* nFields */ 6, 961 /* *fields */ soc_EFP_COUNTER_TABLE_COV_DEFS_BCM56960_A0fmt_fields, 962 /* bits */ 16, 963 /* flags */ 0, 964 }, 965 #endif /* chips */ 966 967 #if defined(BCM_56965_A0) 968 { /* SOC_FORMAT_INT_EFP_COUNTER_TABLE_COV_DEFS_BCM56965_A0fmt */ 969 /* format EFP_COUNTER_TABLE_COV_DEFSfmt */ 970 /* nFields */ 6, 971 /* *fields */ soc_EFP_COUNTER_TABLE_COV_DEFS_BCM56960_A0fmt_fields, 972 /* bits */ 16, 973 /* flags */ 0, 974 }, 975 #endif /* chips */ 976 977 #if defined(BCM_56970_A0) 978 { /* SOC_FORMAT_INT_EFP_COUNTER_TABLE_COV_DEFS_BCM56970_A0fmt */ 979 /* format EFP_COUNTER_TABLE_COV_DEFSfmt */ 980 /* nFields */ 6, 981 /* *fields */ soc_EFP_COUNTER_TABLE_COV_DEFS_BCM56970_A0fmt_fields, 982 /* bits */ 17, 983 /* flags */ 0, 984 }, 985 #endif /* chips */ 986 987 #if defined(BCM_56980_A0) 988 { /* SOC_FORMAT_INT_EFP_COUNTER_TABLE_COV_DEFS_BCM56980_A0fmt */ 989 /* format EFP_COUNTER_TABLE_COV_DEFSfmt */ 990 /* nFields */ 6, 991 /* *fields */ soc_EFP_COUNTER_TABLE_COV_DEFS_BCM56970_A0fmt_fields, 992 /* bits */ 17, 993 /* flags */ 0, 994 }, 995 #endif /* chips */ 996 997 #if defined(BCM_56980_B0) 998 { /* SOC_FORMAT_INT_EFP_COUNTER_TABLE_COV_DEFS_BCM56980_B0fmt */ 999 /* format EFP_COUNTER_TABLE_COV_DEFSfmt */ 1000 /* nFields */ 6, 1001 /* *fields */ soc_EFP_COUNTER_TABLE_COV_DEFS_BCM56970_A0fmt_fields, 1002 /* bits */ 17, 1003 /* flags */ 0, 1004 }, 1005 #endif /* chips */ 1006 1007 #if defined(BCM_56340_A0) || defined(BCM_56640_A0) 1008 { /* SOC_FORMAT_INT_EFP_EVEN_METER_COV_DEFSfmt */ 1009 /* format EFP_EVEN_METER_COV_DEFSfmt */ 1010 /* nFields */ 7, 1011 /* *fields */ soc_EFP_EVEN_METER_COV_DEFSfmt_fields, 1012 /* bits */ 16, 1013 /* flags */ 0, 1014 }, 1015 #endif /* chips */ 1016 1017 #if defined(BCM_53400_A0) 1018 { /* SOC_FORMAT_INT_EFP_EVEN_METER_COV_DEFS_BCM53400_A0fmt */ 1019 /* format EFP_EVEN_METER_COV_DEFSfmt */ 1020 /* nFields */ 7, 1021 /* *fields */ soc_EFP_EVEN_METER_COV_DEFS_BCM53400_A0fmt_fields, 1022 /* bits */ 13, 1023 /* flags */ 0, 1024 }, 1025 #endif /* chips */ 1026 1027 #if defined(BCM_53540_A0) 1028 { /* SOC_FORMAT_INT_EFP_EVEN_METER_COV_DEFS_BCM53540_A0fmt */ 1029 /* format EFP_EVEN_METER_COV_DEFSfmt */ 1030 /* nFields */ 7, 1031 /* *fields */ soc_EFP_EVEN_METER_COV_DEFS_BCM53400_A0fmt_fields, 1032 /* bits */ 13, 1033 /* flags */ 0, 1034 }, 1035 #endif /* chips */ 1036 1037 #if defined(BCM_53570_A0) 1038 { /* SOC_FORMAT_INT_EFP_EVEN_METER_COV_DEFS_BCM53570_A0fmt */ 1039 /* format EFP_EVEN_METER_COV_DEFSfmt */ 1040 /* nFields */ 7, 1041 /* *fields */ soc_EFP_EVEN_METER_COV_DEFS_BCM53400_A0fmt_fields, 1042 /* bits */ 13, 1043 /* flags */ 0, 1044 }, 1045 #endif /* chips */ 1046 1047 #if defined(BCM_53570_B0) 1048 { /* SOC_FORMAT_INT_EFP_EVEN_METER_COV_DEFS_BCM53570_B0fmt */ 1049 /* format EFP_EVEN_METER_COV_DEFSfmt */ 1050 /* nFields */ 7, 1051 /* *fields */ soc_EFP_EVEN_METER_COV_DEFS_BCM53400_A0fmt_fields, 1052 /* bits */ 13, 1053 /* flags */ 0, 1054 }, 1055 #endif /* chips */ 1056 1057 #if defined(BCM_56150_A0) 1058 { /* SOC_FORMAT_INT_EFP_EVEN_METER_COV_DEFS_BCM56150_A0fmt */ 1059 /* format EFP_EVEN_METER_COV_DEFSfmt */ 1060 /* nFields */ 7, 1061 /* *fields */ soc_EFP_EVEN_METER_COV_DEFS_BCM56150_A0fmt_fields, 1062 /* bits */ 13, 1063 /* flags */ 0, 1064 }, 1065 #endif /* chips */ 1066 1067 #if defined(BCM_56160_A0) 1068 { /* SOC_FORMAT_INT_EFP_EVEN_METER_COV_DEFS_BCM56160_A0fmt */ 1069 /* format EFP_EVEN_METER_COV_DEFSfmt */ 1070 /* nFields */ 7, 1071 /* *fields */ soc_EFP_EVEN_METER_COV_DEFS_BCM53400_A0fmt_fields, 1072 /* bits */ 13, 1073 /* flags */ 0, 1074 }, 1075 #endif /* chips */ 1076 1077 #if defined(BCM_56370_A0) 1078 { /* SOC_FORMAT_INT_EFP_EVEN_METER_COV_DEFS_BCM56370_A0fmt */ 1079 /* format EFP_EVEN_METER_COV_DEFSfmt */ 1080 /* nFields */ 7, 1081 /* *fields */ soc_IFP_EVEN_METER_COV_DEFS_BCM53400_A0fmt_fields, 1082 /* bits */ 14, 1083 /* flags */ 0, 1084 }, 1085 #endif /* chips */ 1086 1087 #if defined(BCM_56560_A0) 1088 { /* SOC_FORMAT_INT_EFP_EVEN_METER_COV_DEFS_BCM56560_A0fmt */ 1089 /* format EFP_EVEN_METER_COV_DEFSfmt */ 1090 /* nFields */ 8, 1091 /* *fields */ soc_EFP_EVEN_METER_COV_DEFS_BCM56560_A0fmt_fields, 1092 /* bits */ 15, 1093 /* flags */ 0, 1094 }, 1095 #endif /* chips */ 1096 1097 #if defined(BCM_56560_B0) 1098 { /* SOC_FORMAT_INT_EFP_EVEN_METER_COV_DEFS_BCM56560_B0fmt */ 1099 /* format EFP_EVEN_METER_COV_DEFSfmt */ 1100 /* nFields */ 8, 1101 /* *fields */ soc_EFP_EVEN_METER_COV_DEFS_BCM56560_A0fmt_fields, 1102 /* bits */ 15, 1103 /* flags */ 0, 1104 }, 1105 #endif /* chips */ 1106 1107 #if defined(BCM_56670_A0) 1108 { /* SOC_FORMAT_INT_EFP_EVEN_METER_COV_DEFS_BCM56670_A0fmt */ 1109 /* format EFP_EVEN_METER_COV_DEFSfmt */ 1110 /* nFields */ 8, 1111 /* *fields */ soc_EFP_EVEN_METER_COV_DEFS_BCM56560_A0fmt_fields, 1112 /* bits */ 15, 1113 /* flags */ 0, 1114 }, 1115 #endif /* chips */ 1116 1117 #if defined(BCM_56670_B0) 1118 { /* SOC_FORMAT_INT_EFP_EVEN_METER_COV_DEFS_BCM56670_B0fmt */ 1119 /* format EFP_EVEN_METER_COV_DEFSfmt */ 1120 /* nFields */ 8, 1121 /* *fields */ soc_EFP_EVEN_METER_COV_DEFS_BCM56560_A0fmt_fields, 1122 /* bits */ 15, 1123 /* flags */ 0, 1124 }, 1125 #endif /* chips */ 1126 1127 #if defined(BCM_56770_A0) 1128 { /* SOC_FORMAT_INT_EFP_EVEN_METER_COV_DEFS_BCM56770_A0fmt */ 1129 /* format EFP_EVEN_METER_COV_DEFSfmt */ 1130 /* nFields */ 7, 1131 /* *fields */ soc_EFP_EVEN_METER_COV_DEFS_BCM56870_A0fmt_fields, 1132 /* bits */ 15, 1133 /* flags */ 0, 1134 }, 1135 #endif /* chips */ 1136 1137 #if defined(BCM_56850_A0) 1138 { /* SOC_FORMAT_INT_EFP_EVEN_METER_COV_DEFS_BCM56850_A0fmt */ 1139 /* format EFP_EVEN_METER_COV_DEFSfmt */ 1140 /* nFields */ 7, 1141 /* *fields */ soc_EFP_EVEN_METER_COV_DEFS_BCM56850_A0fmt_fields, 1142 /* bits */ 14, 1143 /* flags */ 0, 1144 }, 1145 #endif /* chips */ 1146 1147 #if defined(BCM_56860_A0) 1148 { /* SOC_FORMAT_INT_EFP_EVEN_METER_COV_DEFS_BCM56860_A0fmt */ 1149 /* format EFP_EVEN_METER_COV_DEFSfmt */ 1150 /* nFields */ 8, 1151 /* *fields */ soc_EFP_EVEN_METER_COV_DEFS_BCM56860_A0fmt_fields, 1152 /* bits */ 15, 1153 /* flags */ 0, 1154 }, 1155 #endif /* chips */ 1156 1157 #if defined(BCM_56870_A0) 1158 { /* SOC_FORMAT_INT_EFP_EVEN_METER_COV_DEFS_BCM56870_A0fmt */ 1159 /* format EFP_EVEN_METER_COV_DEFSfmt */ 1160 /* nFields */ 7, 1161 /* *fields */ soc_EFP_EVEN_METER_COV_DEFS_BCM56870_A0fmt_fields, 1162 /* bits */ 15, 1163 /* flags */ 0, 1164 }, 1165 #endif /* chips */ 1166 1167 #if defined(BCM_56960_A0) 1168 { /* SOC_FORMAT_INT_EFP_EVEN_METER_COV_DEFS_BCM56960_A0fmt */ 1169 /* format EFP_EVEN_METER_COV_DEFSfmt */ 1170 /* nFields */ 7, 1171 /* *fields */ soc_IFP_EVEN_METER_COV_DEFS_BCM53400_A0fmt_fields, 1172 /* bits */ 14, 1173 /* flags */ 0, 1174 }, 1175 #endif /* chips */ 1176 1177 #if defined(BCM_56965_A0) 1178 { /* SOC_FORMAT_INT_EFP_EVEN_METER_COV_DEFS_BCM56965_A0fmt */ 1179 /* format EFP_EVEN_METER_COV_DEFSfmt */ 1180 /* nFields */ 7, 1181 /* *fields */ soc_IFP_EVEN_METER_COV_DEFS_BCM53400_A0fmt_fields, 1182 /* bits */ 14, 1183 /* flags */ 0, 1184 }, 1185 #endif /* chips */ 1186 1187 #if defined(BCM_56970_A0) 1188 { /* SOC_FORMAT_INT_EFP_EVEN_METER_COV_DEFS_BCM56970_A0fmt */ 1189 /* format EFP_EVEN_METER_COV_DEFSfmt */ 1190 /* nFields */ 7, 1191 /* *fields */ soc_IFP_EVEN_METER_COV_DEFS_BCM53400_A0fmt_fields, 1192 /* bits */ 14, 1193 /* flags */ 0, 1194 }, 1195 #endif /* chips */ 1196 1197 #if defined(BCM_56980_A0) 1198 { /* SOC_FORMAT_INT_EFP_EVEN_METER_COV_DEFS_BCM56980_A0fmt */ 1199 /* format EFP_EVEN_METER_COV_DEFSfmt */ 1200 /* nFields */ 7, 1201 /* *fields */ soc_IFP_EVEN_METER_COV_DEFS_BCM53400_A0fmt_fields, 1202 /* bits */ 14, 1203 /* flags */ 0, 1204 }, 1205 #endif /* chips */ 1206 1207 #if defined(BCM_56980_B0) 1208 { /* SOC_FORMAT_INT_EFP_EVEN_METER_COV_DEFS_BCM56980_B0fmt */ 1209 /* format EFP_EVEN_METER_COV_DEFSfmt */ 1210 /* nFields */ 7, 1211 /* *fields */ soc_IFP_EVEN_METER_COV_DEFS_BCM53400_A0fmt_fields, 1212 /* bits */ 14, 1213 /* flags */ 0, 1214 }, 1215 #endif /* chips */ 1216 1217 #if defined(BCM_56514_A0) 1218 { /* SOC_FORMAT_INT_EFP_KEY1fmt */ 1219 /* format EFP_KEY1fmt */ 1220 /* nFields */ 21, 1221 /* *fields */ soc_EFP_KEY1fmt_fields, 1222 /* bits */ 184, 1223 /* flags */ 0, 1224 }, 1225 #endif /* chips */ 1226 1227 #if defined(BCM_56514_A0) 1228 { /* SOC_FORMAT_INT_EFP_KEY2fmt */ 1229 /* format EFP_KEY2fmt */ 1230 /* nFields */ 14, 1231 /* *fields */ soc_EFP_KEY2fmt_fields, 1232 /* bits */ 184, 1233 /* flags */ 0, 1234 }, 1235 #endif /* chips */ 1236 1237 #if defined(BCM_56514_A0) 1238 { /* SOC_FORMAT_INT_EFP_KEY3fmt */ 1239 /* format EFP_KEY3fmt */ 1240 /* nFields */ 8, 1241 /* *fields */ soc_EFP_KEY3fmt_fields, 1242 /* bits */ 184, 1243 /* flags */ 0, 1244 }, 1245 #endif /* chips */ 1246 1247 #if defined(BCM_56514_A0) 1248 { /* SOC_FORMAT_INT_EFP_KEY4fmt */ 1249 /* format EFP_KEY4fmt */ 1250 /* nFields */ 15, 1251 /* *fields */ soc_EFP_KEY4fmt_fields, 1252 /* bits */ 184, 1253 /* flags */ 0, 1254 }, 1255 #endif /* chips */ 1256 1257 #if defined(BCM_56850_A0) 1258 { /* SOC_FORMAT_INT_EFP_KEY5fmt */ 1259 /* format EFP_KEY5fmt */ 1260 /* nFields */ 31, 1261 /* *fields */ soc_EFP_KEY5fmt_fields, 1262 /* bits */ 234, 1263 /* flags */ 0, 1264 }, 1265 #endif /* chips */ 1266 1267 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) || \ 1268 defined(BCM_56970_A0) 1269 { /* SOC_FORMAT_INT_EFP_KEY6fmt */ 1270 /* format EFP_KEY6fmt */ 1271 /* nFields */ 17, 1272 /* *fields */ soc_EFP_KEY6fmt_fields, 1273 /* bits */ 240, 1274 /* flags */ 0, 1275 }, 1276 #endif /* chips */ 1277 1278 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) || \ 1279 defined(BCM_56970_A0) 1280 { /* SOC_FORMAT_INT_EFP_KEY7fmt */ 1281 /* format EFP_KEY7fmt */ 1282 /* nFields */ 18, 1283 /* *fields */ soc_EFP_KEY7fmt_fields, 1284 /* bits */ 240, 1285 /* flags */ 0, 1286 }, 1287 #endif /* chips */ 1288 1289 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) || \ 1290 defined(BCM_56970_A0) 1291 { /* SOC_FORMAT_INT_EFP_KEY8fmt */ 1292 /* format EFP_KEY8fmt */ 1293 /* nFields */ 27, 1294 /* *fields */ soc_EFP_KEY8fmt_fields, 1295 /* bits */ 240, 1296 /* flags */ 0, 1297 }, 1298 #endif /* chips */ 1299 1300 #if defined(BCM_53400_A0) 1301 { /* SOC_FORMAT_INT_EFP_KEY1_BCM53400_A0fmt */ 1302 /* format EFP_KEY1fmt */ 1303 /* nFields */ 28, 1304 /* *fields */ soc_EFP_KEY1_BCM53400_A0fmt_fields, 1305 /* bits */ 214, 1306 /* flags */ 0, 1307 }, 1308 #endif /* chips */ 1309 1310 #if defined(BCM_53540_A0) 1311 { /* SOC_FORMAT_INT_EFP_KEY1_BCM53540_A0fmt */ 1312 /* format EFP_KEY1fmt */ 1313 /* nFields */ 28, 1314 /* *fields */ soc_EFP_KEY1_BCM53400_A0fmt_fields, 1315 /* bits */ 214, 1316 /* flags */ 0, 1317 }, 1318 #endif /* chips */ 1319 1320 #if defined(BCM_53570_A0) 1321 { /* SOC_FORMAT_INT_EFP_KEY1_BCM53570_A0fmt */ 1322 /* format EFP_KEY1fmt */ 1323 /* nFields */ 29, 1324 /* *fields */ soc_EFP_KEY1_BCM53570_A0fmt_fields, 1325 /* bits */ 217, 1326 /* flags */ 0, 1327 }, 1328 #endif /* chips */ 1329 1330 #if defined(BCM_53570_B0) 1331 { /* SOC_FORMAT_INT_EFP_KEY1_BCM53570_B0fmt */ 1332 /* format EFP_KEY1fmt */ 1333 /* nFields */ 30, 1334 /* *fields */ soc_EFP_KEY1_BCM53570_B0fmt_fields, 1335 /* bits */ 217, 1336 /* flags */ 0, 1337 }, 1338 #endif /* chips */ 1339 1340 #if defined(BCM_56142_A0) 1341 { /* SOC_FORMAT_INT_EFP_KEY1_BCM56142_A0fmt */ 1342 /* format EFP_KEY1fmt */ 1343 /* nFields */ 27, 1344 /* *fields */ soc_EFP_KEY1_BCM56624_A0fmt_fields, 1345 /* bits */ 214, 1346 /* flags */ 0, 1347 }, 1348 #endif /* chips */ 1349 1350 #if defined(BCM_56150_A0) 1351 { /* SOC_FORMAT_INT_EFP_KEY1_BCM56150_A0fmt */ 1352 /* format EFP_KEY1fmt */ 1353 /* nFields */ 27, 1354 /* *fields */ soc_EFP_KEY1_BCM56150_A0fmt_fields, 1355 /* bits */ 214, 1356 /* flags */ 0, 1357 }, 1358 #endif /* chips */ 1359 1360 #if defined(BCM_56160_A0) 1361 { /* SOC_FORMAT_INT_EFP_KEY1_BCM56160_A0fmt */ 1362 /* format EFP_KEY1fmt */ 1363 /* nFields */ 28, 1364 /* *fields */ soc_EFP_KEY1_BCM53400_A0fmt_fields, 1365 /* bits */ 214, 1366 /* flags */ 0, 1367 }, 1368 #endif /* chips */ 1369 1370 #if defined(BCM_56260_A0) 1371 { /* SOC_FORMAT_INT_EFP_KEY1_BCM56260_A0fmt */ 1372 /* format EFP_KEY1fmt */ 1373 /* nFields */ 37, 1374 /* *fields */ soc_EFP_KEY1_BCM56260_A0fmt_fields, 1375 /* bits */ 234, 1376 /* flags */ 0, 1377 }, 1378 #endif /* chips */ 1379 1380 #if defined(BCM_56260_B0) 1381 { /* SOC_FORMAT_INT_EFP_KEY1_BCM56260_B0fmt */ 1382 /* format EFP_KEY1fmt */ 1383 /* nFields */ 37, 1384 /* *fields */ soc_EFP_KEY1_BCM56260_A0fmt_fields, 1385 /* bits */ 234, 1386 /* flags */ 0, 1387 }, 1388 #endif /* chips */ 1389 1390 #if defined(BCM_56270_A0) 1391 { /* SOC_FORMAT_INT_EFP_KEY1_BCM56270_A0fmt */ 1392 /* format EFP_KEY1fmt */ 1393 /* nFields */ 37, 1394 /* *fields */ soc_EFP_KEY1_BCM56260_A0fmt_fields, 1395 /* bits */ 234, 1396 /* flags */ 0, 1397 }, 1398 #endif /* chips */ 1399 1400 #if defined(BCM_56334_A0) 1401 { /* SOC_FORMAT_INT_EFP_KEY1_BCM56334_A0fmt */ 1402 /* format EFP_KEY1fmt */ 1403 /* nFields */ 27, 1404 /* *fields */ soc_EFP_KEY1_BCM56624_A0fmt_fields, 1405 /* bits */ 214, 1406 /* flags */ 0, 1407 }, 1408 #endif /* chips */ 1409 1410 #if defined(BCM_56334_B0) 1411 { /* SOC_FORMAT_INT_EFP_KEY1_BCM56334_B0fmt */ 1412 /* format EFP_KEY1fmt */ 1413 /* nFields */ 27, 1414 /* *fields */ soc_EFP_KEY1_BCM56624_A0fmt_fields, 1415 /* bits */ 214, 1416 /* flags */ 0, 1417 }, 1418 #endif /* chips */ 1419 1420 #if defined(BCM_56340_A0) 1421 { /* SOC_FORMAT_INT_EFP_KEY1_BCM56340_A0fmt */ 1422 /* format EFP_KEY1fmt */ 1423 /* nFields */ 35, 1424 /* *fields */ soc_EFP_KEY1_BCM56640_A0fmt_fields, 1425 /* bits */ 234, 1426 /* flags */ 0, 1427 }, 1428 #endif /* chips */ 1429 1430 #if defined(BCM_56370_A0) 1431 { /* SOC_FORMAT_INT_EFP_KEY1_BCM56370_A0fmt */ 1432 /* format EFP_KEY1fmt */ 1433 /* nFields */ 39, 1434 /* *fields */ soc_EFP_KEY1_BCM56870_A0fmt_fields, 1435 /* bits */ 272, 1436 /* flags */ 0, 1437 }, 1438 #endif /* chips */ 1439 1440 #if defined(BCM_56440_A0) 1441 { /* SOC_FORMAT_INT_EFP_KEY1_BCM56440_A0fmt */ 1442 /* format EFP_KEY1fmt */ 1443 /* nFields */ 31, 1444 /* *fields */ soc_EFP_KEY1_BCM56440_A0fmt_fields, 1445 /* bits */ 214, 1446 /* flags */ 0, 1447 }, 1448 #endif /* chips */ 1449 1450 #if defined(BCM_56440_B0) 1451 { /* SOC_FORMAT_INT_EFP_KEY1_BCM56440_B0fmt */ 1452 /* format EFP_KEY1fmt */ 1453 /* nFields */ 31, 1454 /* *fields */ soc_EFP_KEY1_BCM56440_A0fmt_fields, 1455 /* bits */ 214, 1456 /* flags */ 0, 1457 }, 1458 #endif /* chips */ 1459 1460 #if defined(BCM_56450_A0) 1461 { /* SOC_FORMAT_INT_EFP_KEY1_BCM56450_A0fmt */ 1462 /* format EFP_KEY1fmt */ 1463 /* nFields */ 35, 1464 /* *fields */ soc_EFP_KEY1_BCM56450_A0fmt_fields, 1465 /* bits */ 234, 1466 /* flags */ 0, 1467 }, 1468 #endif /* chips */ 1469 1470 #if defined(BCM_56450_B0) 1471 { /* SOC_FORMAT_INT_EFP_KEY1_BCM56450_B0fmt */ 1472 /* format EFP_KEY1fmt */ 1473 /* nFields */ 35, 1474 /* *fields */ soc_EFP_KEY1_BCM56450_A0fmt_fields, 1475 /* bits */ 234, 1476 /* flags */ 0, 1477 }, 1478 #endif /* chips */ 1479 1480 #if defined(BCM_56450_B1) 1481 { /* SOC_FORMAT_INT_EFP_KEY1_BCM56450_B1fmt */ 1482 /* format EFP_KEY1fmt */ 1483 /* nFields */ 35, 1484 /* *fields */ soc_EFP_KEY1_BCM56450_A0fmt_fields, 1485 /* bits */ 234, 1486 /* flags */ 0, 1487 }, 1488 #endif /* chips */ 1489 1490 #if defined(BCM_56524_A0) 1491 { /* SOC_FORMAT_INT_EFP_KEY1_BCM56524_A0fmt */ 1492 /* format EFP_KEY1fmt */ 1493 /* nFields */ 29, 1494 /* *fields */ soc_EFP_KEY1_BCM56634_A0fmt_fields, 1495 /* bits */ 214, 1496 /* flags */ 0, 1497 }, 1498 #endif /* chips */ 1499 1500 #if defined(BCM_56524_B0) 1501 { /* SOC_FORMAT_INT_EFP_KEY1_BCM56524_B0fmt */ 1502 /* format EFP_KEY1fmt */ 1503 /* nFields */ 29, 1504 /* *fields */ soc_EFP_KEY1_BCM56634_A0fmt_fields, 1505 /* bits */ 214, 1506 /* flags */ 0, 1507 }, 1508 #endif /* chips */ 1509 1510 #if defined(BCM_56560_A0) 1511 { /* SOC_FORMAT_INT_EFP_KEY1_BCM56560_A0fmt */ 1512 /* format EFP_KEY1fmt */ 1513 /* nFields */ 35, 1514 /* *fields */ soc_EFP_KEY1_BCM56560_A0fmt_fields, 1515 /* bits */ 234, 1516 /* flags */ 0, 1517 }, 1518 #endif /* chips */ 1519 1520 #if defined(BCM_56560_B0) 1521 { /* SOC_FORMAT_INT_EFP_KEY1_BCM56560_B0fmt */ 1522 /* format EFP_KEY1fmt */ 1523 /* nFields */ 35, 1524 /* *fields */ soc_EFP_KEY1_BCM56560_A0fmt_fields, 1525 /* bits */ 234, 1526 /* flags */ 0, 1527 }, 1528 #endif /* chips */ 1529 1530 #if defined(BCM_56624_A0) 1531 { /* SOC_FORMAT_INT_EFP_KEY1_BCM56624_A0fmt */ 1532 /* format EFP_KEY1fmt */ 1533 /* nFields */ 27, 1534 /* *fields */ soc_EFP_KEY1_BCM56624_A0fmt_fields, 1535 /* bits */ 214, 1536 /* flags */ 0, 1537 }, 1538 #endif /* chips */ 1539 1540 #if defined(BCM_56624_B0) 1541 { /* SOC_FORMAT_INT_EFP_KEY1_BCM56624_B0fmt */ 1542 /* format EFP_KEY1fmt */ 1543 /* nFields */ 27, 1544 /* *fields */ soc_EFP_KEY1_BCM56624_A0fmt_fields, 1545 /* bits */ 214, 1546 /* flags */ 0, 1547 }, 1548 #endif /* chips */ 1549 1550 #if defined(BCM_56634_A0) 1551 { /* SOC_FORMAT_INT_EFP_KEY1_BCM56634_A0fmt */ 1552 /* format EFP_KEY1fmt */ 1553 /* nFields */ 29, 1554 /* *fields */ soc_EFP_KEY1_BCM56634_A0fmt_fields, 1555 /* bits */ 214, 1556 /* flags */ 0, 1557 }, 1558 #endif /* chips */ 1559 1560 #if defined(BCM_56634_B0) 1561 { /* SOC_FORMAT_INT_EFP_KEY1_BCM56634_B0fmt */ 1562 /* format EFP_KEY1fmt */ 1563 /* nFields */ 29, 1564 /* *fields */ soc_EFP_KEY1_BCM56634_A0fmt_fields, 1565 /* bits */ 214, 1566 /* flags */ 0, 1567 }, 1568 #endif /* chips */ 1569 1570 #if defined(BCM_56640_A0) 1571 { /* SOC_FORMAT_INT_EFP_KEY1_BCM56640_A0fmt */ 1572 /* format EFP_KEY1fmt */ 1573 /* nFields */ 35, 1574 /* *fields */ soc_EFP_KEY1_BCM56640_A0fmt_fields, 1575 /* bits */ 234, 1576 /* flags */ 0, 1577 }, 1578 #endif /* chips */ 1579 1580 #if defined(BCM_56670_A0) 1581 { /* SOC_FORMAT_INT_EFP_KEY1_BCM56670_A0fmt */ 1582 /* format EFP_KEY1fmt */ 1583 /* nFields */ 36, 1584 /* *fields */ soc_EFP_KEY1_BCM56670_A0fmt_fields, 1585 /* bits */ 234, 1586 /* flags */ 0, 1587 }, 1588 #endif /* chips */ 1589 1590 #if defined(BCM_56670_B0) 1591 { /* SOC_FORMAT_INT_EFP_KEY1_BCM56670_B0fmt */ 1592 /* format EFP_KEY1fmt */ 1593 /* nFields */ 36, 1594 /* *fields */ soc_EFP_KEY1_BCM56670_A0fmt_fields, 1595 /* bits */ 234, 1596 /* flags */ 0, 1597 }, 1598 #endif /* chips */ 1599 1600 #if defined(BCM_56680_A0) 1601 { /* SOC_FORMAT_INT_EFP_KEY1_BCM56680_A0fmt */ 1602 /* format EFP_KEY1fmt */ 1603 /* nFields */ 27, 1604 /* *fields */ soc_EFP_KEY1_BCM56624_A0fmt_fields, 1605 /* bits */ 214, 1606 /* flags */ 0, 1607 }, 1608 #endif /* chips */ 1609 1610 #if defined(BCM_56680_B0) 1611 { /* SOC_FORMAT_INT_EFP_KEY1_BCM56680_B0fmt */ 1612 /* format EFP_KEY1fmt */ 1613 /* nFields */ 27, 1614 /* *fields */ soc_EFP_KEY1_BCM56624_A0fmt_fields, 1615 /* bits */ 214, 1616 /* flags */ 0, 1617 }, 1618 #endif /* chips */ 1619 1620 #if defined(BCM_56685_A0) 1621 { /* SOC_FORMAT_INT_EFP_KEY1_BCM56685_A0fmt */ 1622 /* format EFP_KEY1fmt */ 1623 /* nFields */ 29, 1624 /* *fields */ soc_EFP_KEY1_BCM56634_A0fmt_fields, 1625 /* bits */ 214, 1626 /* flags */ 0, 1627 }, 1628 #endif /* chips */ 1629 1630 #if defined(BCM_56685_B0) 1631 { /* SOC_FORMAT_INT_EFP_KEY1_BCM56685_B0fmt */ 1632 /* format EFP_KEY1fmt */ 1633 /* nFields */ 29, 1634 /* *fields */ soc_EFP_KEY1_BCM56634_A0fmt_fields, 1635 /* bits */ 214, 1636 /* flags */ 0, 1637 }, 1638 #endif /* chips */ 1639 1640 #if defined(BCM_56725_A0) 1641 { /* SOC_FORMAT_INT_EFP_KEY1_BCM56725_A0fmt */ 1642 /* format EFP_KEY1fmt */ 1643 /* nFields */ 27, 1644 /* *fields */ soc_EFP_KEY1_BCM56820_A0fmt_fields, 1645 /* bits */ 210, 1646 /* flags */ 0, 1647 }, 1648 #endif /* chips */ 1649 1650 #if defined(BCM_56770_A0) 1651 { /* SOC_FORMAT_INT_EFP_KEY1_BCM56770_A0fmt */ 1652 /* format EFP_KEY1fmt */ 1653 /* nFields */ 39, 1654 /* *fields */ soc_EFP_KEY1_BCM56870_A0fmt_fields, 1655 /* bits */ 272, 1656 /* flags */ 0, 1657 }, 1658 #endif /* chips */ 1659 1660 #if defined(BCM_56820_A0) 1661 { /* SOC_FORMAT_INT_EFP_KEY1_BCM56820_A0fmt */ 1662 /* format EFP_KEY1fmt */ 1663 /* nFields */ 27, 1664 /* *fields */ soc_EFP_KEY1_BCM56820_A0fmt_fields, 1665 /* bits */ 210, 1666 /* flags */ 0, 1667 }, 1668 #endif /* chips */ 1669 1670 #if defined(BCM_56840_A0) 1671 { /* SOC_FORMAT_INT_EFP_KEY1_BCM56840_A0fmt */ 1672 /* format EFP_KEY1fmt */ 1673 /* nFields */ 29, 1674 /* *fields */ soc_EFP_KEY1_BCM56840_A0fmt_fields, 1675 /* bits */ 214, 1676 /* flags */ 0, 1677 }, 1678 #endif /* chips */ 1679 1680 #if defined(BCM_56840_B0) 1681 { /* SOC_FORMAT_INT_EFP_KEY1_BCM56840_B0fmt */ 1682 /* format EFP_KEY1fmt */ 1683 /* nFields */ 29, 1684 /* *fields */ soc_EFP_KEY1_BCM56840_A0fmt_fields, 1685 /* bits */ 214, 1686 /* flags */ 0, 1687 }, 1688 #endif /* chips */ 1689 1690 #if defined(BCM_56850_A0) 1691 { /* SOC_FORMAT_INT_EFP_KEY1_BCM56850_A0fmt */ 1692 /* format EFP_KEY1fmt */ 1693 /* nFields */ 33, 1694 /* *fields */ soc_EFP_KEY1_BCM56850_A0fmt_fields, 1695 /* bits */ 234, 1696 /* flags */ 0, 1697 }, 1698 #endif /* chips */ 1699 1700 #if defined(BCM_56860_A0) 1701 { /* SOC_FORMAT_INT_EFP_KEY1_BCM56860_A0fmt */ 1702 /* format EFP_KEY1fmt */ 1703 /* nFields */ 37, 1704 /* *fields */ soc_EFP_KEY1_BCM56860_A0fmt_fields, 1705 /* bits */ 234, 1706 /* flags */ 0, 1707 }, 1708 #endif /* chips */ 1709 1710 #if defined(BCM_56870_A0) 1711 { /* SOC_FORMAT_INT_EFP_KEY1_BCM56870_A0fmt */ 1712 /* format EFP_KEY1fmt */ 1713 /* nFields */ 39, 1714 /* *fields */ soc_EFP_KEY1_BCM56870_A0fmt_fields, 1715 /* bits */ 272, 1716 /* flags */ 0, 1717 }, 1718 #endif /* chips */ 1719 1720 #if defined(BCM_56960_A0) 1721 { /* SOC_FORMAT_INT_EFP_KEY1_BCM56960_A0fmt */ 1722 /* format EFP_KEY1fmt */ 1723 /* nFields */ 36, 1724 /* *fields */ soc_EFP_KEY1_BCM56960_A0fmt_fields, 1725 /* bits */ 240, 1726 /* flags */ 0, 1727 }, 1728 #endif /* chips */ 1729 1730 #if defined(BCM_56965_A0) 1731 { /* SOC_FORMAT_INT_EFP_KEY1_BCM56965_A0fmt */ 1732 /* format EFP_KEY1fmt */ 1733 /* nFields */ 36, 1734 /* *fields */ soc_EFP_KEY1_BCM56960_A0fmt_fields, 1735 /* bits */ 240, 1736 /* flags */ 0, 1737 }, 1738 #endif /* chips */ 1739 1740 #if defined(BCM_56970_A0) 1741 { /* SOC_FORMAT_INT_EFP_KEY1_BCM56970_A0fmt */ 1742 /* format EFP_KEY1fmt */ 1743 /* nFields */ 36, 1744 /* *fields */ soc_EFP_KEY1_BCM56960_A0fmt_fields, 1745 /* bits */ 240, 1746 /* flags */ 0, 1747 }, 1748 #endif /* chips */ 1749 1750 #if defined(BCM_56980_A0) 1751 { /* SOC_FORMAT_INT_EFP_KEY1_BCM56980_A0fmt */ 1752 /* format EFP_KEY1fmt */ 1753 /* nFields */ 33, 1754 /* *fields */ soc_EFP_KEY1_BCM56980_A0fmt_fields, 1755 /* bits */ 240, 1756 /* flags */ 0, 1757 }, 1758 #endif /* chips */ 1759 1760 #if defined(BCM_56980_B0) 1761 { /* SOC_FORMAT_INT_EFP_KEY1_BCM56980_B0fmt */ 1762 /* format EFP_KEY1fmt */ 1763 /* nFields */ 33, 1764 /* *fields */ soc_EFP_KEY1_BCM56980_A0fmt_fields, 1765 /* bits */ 240, 1766 /* flags */ 0, 1767 }, 1768 #endif /* chips */ 1769 1770 #if defined(BCM_53400_A0) 1771 { /* SOC_FORMAT_INT_EFP_KEY2_BCM53400_A0fmt */ 1772 /* format EFP_KEY2fmt */ 1773 /* nFields */ 23, 1774 /* *fields */ soc_EFP_KEY2_BCM53400_A0fmt_fields, 1775 /* bits */ 214, 1776 /* flags */ 0, 1777 }, 1778 #endif /* chips */ 1779 1780 #if defined(BCM_53540_A0) 1781 { /* SOC_FORMAT_INT_EFP_KEY2_BCM53540_A0fmt */ 1782 /* format EFP_KEY2fmt */ 1783 /* nFields */ 23, 1784 /* *fields */ soc_EFP_KEY2_BCM53400_A0fmt_fields, 1785 /* bits */ 214, 1786 /* flags */ 0, 1787 }, 1788 #endif /* chips */ 1789 1790 #if defined(BCM_53570_A0) 1791 { /* SOC_FORMAT_INT_EFP_KEY2_BCM53570_A0fmt */ 1792 /* format EFP_KEY2fmt */ 1793 /* nFields */ 24, 1794 /* *fields */ soc_EFP_KEY2_BCM53570_A0fmt_fields, 1795 /* bits */ 217, 1796 /* flags */ 0, 1797 }, 1798 #endif /* chips */ 1799 1800 #if defined(BCM_53570_B0) 1801 { /* SOC_FORMAT_INT_EFP_KEY2_BCM53570_B0fmt */ 1802 /* format EFP_KEY2fmt */ 1803 /* nFields */ 25, 1804 /* *fields */ soc_EFP_KEY2_BCM53570_B0fmt_fields, 1805 /* bits */ 217, 1806 /* flags */ 0, 1807 }, 1808 #endif /* chips */ 1809 1810 #if defined(BCM_56142_A0) 1811 { /* SOC_FORMAT_INT_EFP_KEY2_BCM56142_A0fmt */ 1812 /* format EFP_KEY2fmt */ 1813 /* nFields */ 22, 1814 /* *fields */ soc_EFP_KEY2_BCM56624_A0fmt_fields, 1815 /* bits */ 214, 1816 /* flags */ 0, 1817 }, 1818 #endif /* chips */ 1819 1820 #if defined(BCM_56150_A0) 1821 { /* SOC_FORMAT_INT_EFP_KEY2_BCM56150_A0fmt */ 1822 /* format EFP_KEY2fmt */ 1823 /* nFields */ 22, 1824 /* *fields */ soc_EFP_KEY2_BCM56150_A0fmt_fields, 1825 /* bits */ 214, 1826 /* flags */ 0, 1827 }, 1828 #endif /* chips */ 1829 1830 #if defined(BCM_56160_A0) 1831 { /* SOC_FORMAT_INT_EFP_KEY2_BCM56160_A0fmt */ 1832 /* format EFP_KEY2fmt */ 1833 /* nFields */ 23, 1834 /* *fields */ soc_EFP_KEY2_BCM53400_A0fmt_fields, 1835 /* bits */ 214, 1836 /* flags */ 0, 1837 }, 1838 #endif /* chips */ 1839 1840 #if defined(BCM_56260_A0) 1841 { /* SOC_FORMAT_INT_EFP_KEY2_BCM56260_A0fmt */ 1842 /* format EFP_KEY2fmt */ 1843 /* nFields */ 28, 1844 /* *fields */ soc_EFP_KEY2_BCM56260_A0fmt_fields, 1845 /* bits */ 234, 1846 /* flags */ 0, 1847 }, 1848 #endif /* chips */ 1849 1850 #if defined(BCM_56260_B0) 1851 { /* SOC_FORMAT_INT_EFP_KEY2_BCM56260_B0fmt */ 1852 /* format EFP_KEY2fmt */ 1853 /* nFields */ 28, 1854 /* *fields */ soc_EFP_KEY2_BCM56260_A0fmt_fields, 1855 /* bits */ 234, 1856 /* flags */ 0, 1857 }, 1858 #endif /* chips */ 1859 1860 #if defined(BCM_56270_A0) 1861 { /* SOC_FORMAT_INT_EFP_KEY2_BCM56270_A0fmt */ 1862 /* format EFP_KEY2fmt */ 1863 /* nFields */ 28, 1864 /* *fields */ soc_EFP_KEY2_BCM56260_A0fmt_fields, 1865 /* bits */ 234, 1866 /* flags */ 0, 1867 }, 1868 #endif /* chips */ 1869 1870 #if defined(BCM_56334_A0) 1871 { /* SOC_FORMAT_INT_EFP_KEY2_BCM56334_A0fmt */ 1872 /* format EFP_KEY2fmt */ 1873 /* nFields */ 22, 1874 /* *fields */ soc_EFP_KEY2_BCM56624_A0fmt_fields, 1875 /* bits */ 214, 1876 /* flags */ 0, 1877 }, 1878 #endif /* chips */ 1879 1880 #if defined(BCM_56334_B0) 1881 { /* SOC_FORMAT_INT_EFP_KEY2_BCM56334_B0fmt */ 1882 /* format EFP_KEY2fmt */ 1883 /* nFields */ 22, 1884 /* *fields */ soc_EFP_KEY2_BCM56624_A0fmt_fields, 1885 /* bits */ 214, 1886 /* flags */ 0, 1887 }, 1888 #endif /* chips */ 1889 1890 #if defined(BCM_56340_A0) 1891 { /* SOC_FORMAT_INT_EFP_KEY2_BCM56340_A0fmt */ 1892 /* format EFP_KEY2fmt */ 1893 /* nFields */ 27, 1894 /* *fields */ soc_EFP_KEY2_BCM56640_A0fmt_fields, 1895 /* bits */ 234, 1896 /* flags */ 0, 1897 }, 1898 #endif /* chips */ 1899 1900 #if defined(BCM_56370_A0) 1901 { /* SOC_FORMAT_INT_EFP_KEY2_BCM56370_A0fmt */ 1902 /* format EFP_KEY2fmt */ 1903 /* nFields */ 31, 1904 /* *fields */ soc_EFP_KEY2_BCM56870_A0fmt_fields, 1905 /* bits */ 272, 1906 /* flags */ 0, 1907 }, 1908 #endif /* chips */ 1909 1910 #if defined(BCM_56440_A0) 1911 { /* SOC_FORMAT_INT_EFP_KEY2_BCM56440_A0fmt */ 1912 /* format EFP_KEY2fmt */ 1913 /* nFields */ 22, 1914 /* *fields */ soc_EFP_KEY2_BCM56440_A0fmt_fields, 1915 /* bits */ 214, 1916 /* flags */ 0, 1917 }, 1918 #endif /* chips */ 1919 1920 #if defined(BCM_56440_B0) 1921 { /* SOC_FORMAT_INT_EFP_KEY2_BCM56440_B0fmt */ 1922 /* format EFP_KEY2fmt */ 1923 /* nFields */ 22, 1924 /* *fields */ soc_EFP_KEY2_BCM56440_A0fmt_fields, 1925 /* bits */ 214, 1926 /* flags */ 0, 1927 }, 1928 #endif /* chips */ 1929 1930 #if defined(BCM_56450_A0) 1931 { /* SOC_FORMAT_INT_EFP_KEY2_BCM56450_A0fmt */ 1932 /* format EFP_KEY2fmt */ 1933 /* nFields */ 27, 1934 /* *fields */ soc_EFP_KEY2_BCM56450_A0fmt_fields, 1935 /* bits */ 234, 1936 /* flags */ 0, 1937 }, 1938 #endif /* chips */ 1939 1940 #if defined(BCM_56450_B0) 1941 { /* SOC_FORMAT_INT_EFP_KEY2_BCM56450_B0fmt */ 1942 /* format EFP_KEY2fmt */ 1943 /* nFields */ 27, 1944 /* *fields */ soc_EFP_KEY2_BCM56450_A0fmt_fields, 1945 /* bits */ 234, 1946 /* flags */ 0, 1947 }, 1948 #endif /* chips */ 1949 1950 #if defined(BCM_56450_B1) 1951 { /* SOC_FORMAT_INT_EFP_KEY2_BCM56450_B1fmt */ 1952 /* format EFP_KEY2fmt */ 1953 /* nFields */ 27, 1954 /* *fields */ soc_EFP_KEY2_BCM56450_A0fmt_fields, 1955 /* bits */ 234, 1956 /* flags */ 0, 1957 }, 1958 #endif /* chips */ 1959 1960 #if defined(BCM_56524_A0) 1961 { /* SOC_FORMAT_INT_EFP_KEY2_BCM56524_A0fmt */ 1962 /* format EFP_KEY2fmt */ 1963 /* nFields */ 20, 1964 /* *fields */ soc_EFP_KEY2_BCM56634_A0fmt_fields, 1965 /* bits */ 214, 1966 /* flags */ 0, 1967 }, 1968 #endif /* chips */ 1969 1970 #if defined(BCM_56524_B0) 1971 { /* SOC_FORMAT_INT_EFP_KEY2_BCM56524_B0fmt */ 1972 /* format EFP_KEY2fmt */ 1973 /* nFields */ 20, 1974 /* *fields */ soc_EFP_KEY2_BCM56634_A0fmt_fields, 1975 /* bits */ 214, 1976 /* flags */ 0, 1977 }, 1978 #endif /* chips */ 1979 1980 #if defined(BCM_56560_A0) 1981 { /* SOC_FORMAT_INT_EFP_KEY2_BCM56560_A0fmt */ 1982 /* format EFP_KEY2fmt */ 1983 /* nFields */ 27, 1984 /* *fields */ soc_EFP_KEY2_BCM56560_A0fmt_fields, 1985 /* bits */ 234, 1986 /* flags */ 0, 1987 }, 1988 #endif /* chips */ 1989 1990 #if defined(BCM_56560_B0) 1991 { /* SOC_FORMAT_INT_EFP_KEY2_BCM56560_B0fmt */ 1992 /* format EFP_KEY2fmt */ 1993 /* nFields */ 27, 1994 /* *fields */ soc_EFP_KEY2_BCM56560_A0fmt_fields, 1995 /* bits */ 234, 1996 /* flags */ 0, 1997 }, 1998 #endif /* chips */ 1999 2000 #if defined(BCM_56624_A0) 2001 { /* SOC_FORMAT_INT_EFP_KEY2_BCM56624_A0fmt */ 2002 /* format EFP_KEY2fmt */ 2003 /* nFields */ 22, 2004 /* *fields */ soc_EFP_KEY2_BCM56624_A0fmt_fields, 2005 /* bits */ 214, 2006 /* flags */ 0, 2007 }, 2008 #endif /* chips */ 2009 2010 #if defined(BCM_56624_B0) 2011 { /* SOC_FORMAT_INT_EFP_KEY2_BCM56624_B0fmt */ 2012 /* format EFP_KEY2fmt */ 2013 /* nFields */ 22, 2014 /* *fields */ soc_EFP_KEY2_BCM56624_A0fmt_fields, 2015 /* bits */ 214, 2016 /* flags */ 0, 2017 }, 2018 #endif /* chips */ 2019 2020 #if defined(BCM_56634_A0) 2021 { /* SOC_FORMAT_INT_EFP_KEY2_BCM56634_A0fmt */ 2022 /* format EFP_KEY2fmt */ 2023 /* nFields */ 20, 2024 /* *fields */ soc_EFP_KEY2_BCM56634_A0fmt_fields, 2025 /* bits */ 214, 2026 /* flags */ 0, 2027 }, 2028 #endif /* chips */ 2029 2030 #if defined(BCM_56634_B0) 2031 { /* SOC_FORMAT_INT_EFP_KEY2_BCM56634_B0fmt */ 2032 /* format EFP_KEY2fmt */ 2033 /* nFields */ 20, 2034 /* *fields */ soc_EFP_KEY2_BCM56634_A0fmt_fields, 2035 /* bits */ 214, 2036 /* flags */ 0, 2037 }, 2038 #endif /* chips */ 2039 2040 #if defined(BCM_56640_A0) 2041 { /* SOC_FORMAT_INT_EFP_KEY2_BCM56640_A0fmt */ 2042 /* format EFP_KEY2fmt */ 2043 /* nFields */ 27, 2044 /* *fields */ soc_EFP_KEY2_BCM56640_A0fmt_fields, 2045 /* bits */ 234, 2046 /* flags */ 0, 2047 }, 2048 #endif /* chips */ 2049 2050 #if defined(BCM_56670_A0) 2051 { /* SOC_FORMAT_INT_EFP_KEY2_BCM56670_A0fmt */ 2052 /* format EFP_KEY2fmt */ 2053 /* nFields */ 27, 2054 /* *fields */ soc_EFP_KEY2_BCM56670_A0fmt_fields, 2055 /* bits */ 234, 2056 /* flags */ 0, 2057 }, 2058 #endif /* chips */ 2059 2060 #if defined(BCM_56670_B0) 2061 { /* SOC_FORMAT_INT_EFP_KEY2_BCM56670_B0fmt */ 2062 /* format EFP_KEY2fmt */ 2063 /* nFields */ 27, 2064 /* *fields */ soc_EFP_KEY2_BCM56670_A0fmt_fields, 2065 /* bits */ 234, 2066 /* flags */ 0, 2067 }, 2068 #endif /* chips */ 2069 2070 #if defined(BCM_56680_A0) 2071 { /* SOC_FORMAT_INT_EFP_KEY2_BCM56680_A0fmt */ 2072 /* format EFP_KEY2fmt */ 2073 /* nFields */ 22, 2074 /* *fields */ soc_EFP_KEY2_BCM56624_A0fmt_fields, 2075 /* bits */ 214, 2076 /* flags */ 0, 2077 }, 2078 #endif /* chips */ 2079 2080 #if defined(BCM_56680_B0) 2081 { /* SOC_FORMAT_INT_EFP_KEY2_BCM56680_B0fmt */ 2082 /* format EFP_KEY2fmt */ 2083 /* nFields */ 22, 2084 /* *fields */ soc_EFP_KEY2_BCM56624_A0fmt_fields, 2085 /* bits */ 214, 2086 /* flags */ 0, 2087 }, 2088 #endif /* chips */ 2089 2090 #if defined(BCM_56685_A0) 2091 { /* SOC_FORMAT_INT_EFP_KEY2_BCM56685_A0fmt */ 2092 /* format EFP_KEY2fmt */ 2093 /* nFields */ 20, 2094 /* *fields */ soc_EFP_KEY2_BCM56634_A0fmt_fields, 2095 /* bits */ 214, 2096 /* flags */ 0, 2097 }, 2098 #endif /* chips */ 2099 2100 #if defined(BCM_56685_B0) 2101 { /* SOC_FORMAT_INT_EFP_KEY2_BCM56685_B0fmt */ 2102 /* format EFP_KEY2fmt */ 2103 /* nFields */ 20, 2104 /* *fields */ soc_EFP_KEY2_BCM56634_A0fmt_fields, 2105 /* bits */ 214, 2106 /* flags */ 0, 2107 }, 2108 #endif /* chips */ 2109 2110 #if defined(BCM_56725_A0) 2111 { /* SOC_FORMAT_INT_EFP_KEY2_BCM56725_A0fmt */ 2112 /* format EFP_KEY2fmt */ 2113 /* nFields */ 22, 2114 /* *fields */ soc_EFP_KEY2_BCM56820_A0fmt_fields, 2115 /* bits */ 210, 2116 /* flags */ 0, 2117 }, 2118 #endif /* chips */ 2119 2120 #if defined(BCM_56770_A0) 2121 { /* SOC_FORMAT_INT_EFP_KEY2_BCM56770_A0fmt */ 2122 /* format EFP_KEY2fmt */ 2123 /* nFields */ 31, 2124 /* *fields */ soc_EFP_KEY2_BCM56870_A0fmt_fields, 2125 /* bits */ 272, 2126 /* flags */ 0, 2127 }, 2128 #endif /* chips */ 2129 2130 #if defined(BCM_56820_A0) 2131 { /* SOC_FORMAT_INT_EFP_KEY2_BCM56820_A0fmt */ 2132 /* format EFP_KEY2fmt */ 2133 /* nFields */ 22, 2134 /* *fields */ soc_EFP_KEY2_BCM56820_A0fmt_fields, 2135 /* bits */ 210, 2136 /* flags */ 0, 2137 }, 2138 #endif /* chips */ 2139 2140 #if defined(BCM_56840_A0) 2141 { /* SOC_FORMAT_INT_EFP_KEY2_BCM56840_A0fmt */ 2142 /* format EFP_KEY2fmt */ 2143 /* nFields */ 20, 2144 /* *fields */ soc_EFP_KEY2_BCM56840_A0fmt_fields, 2145 /* bits */ 214, 2146 /* flags */ 0, 2147 }, 2148 #endif /* chips */ 2149 2150 #if defined(BCM_56840_B0) 2151 { /* SOC_FORMAT_INT_EFP_KEY2_BCM56840_B0fmt */ 2152 /* format EFP_KEY2fmt */ 2153 /* nFields */ 20, 2154 /* *fields */ soc_EFP_KEY2_BCM56840_A0fmt_fields, 2155 /* bits */ 214, 2156 /* flags */ 0, 2157 }, 2158 #endif /* chips */ 2159 2160 #if defined(BCM_56850_A0) 2161 { /* SOC_FORMAT_INT_EFP_KEY2_BCM56850_A0fmt */ 2162 /* format EFP_KEY2fmt */ 2163 /* nFields */ 25, 2164 /* *fields */ soc_EFP_KEY2_BCM56850_A0fmt_fields, 2165 /* bits */ 234, 2166 /* flags */ 0, 2167 }, 2168 #endif /* chips */ 2169 2170 #if defined(BCM_56860_A0) 2171 { /* SOC_FORMAT_INT_EFP_KEY2_BCM56860_A0fmt */ 2172 /* format EFP_KEY2fmt */ 2173 /* nFields */ 27, 2174 /* *fields */ soc_EFP_KEY2_BCM56860_A0fmt_fields, 2175 /* bits */ 234, 2176 /* flags */ 0, 2177 }, 2178 #endif /* chips */ 2179 2180 #if defined(BCM_56870_A0) 2181 { /* SOC_FORMAT_INT_EFP_KEY2_BCM56870_A0fmt */ 2182 /* format EFP_KEY2fmt */ 2183 /* nFields */ 31, 2184 /* *fields */ soc_EFP_KEY2_BCM56870_A0fmt_fields, 2185 /* bits */ 272, 2186 /* flags */ 0, 2187 }, 2188 #endif /* chips */ 2189 2190 #if defined(BCM_56960_A0) 2191 { /* SOC_FORMAT_INT_EFP_KEY2_BCM56960_A0fmt */ 2192 /* format EFP_KEY2fmt */ 2193 /* nFields */ 28, 2194 /* *fields */ soc_EFP_KEY2_BCM56960_A0fmt_fields, 2195 /* bits */ 240, 2196 /* flags */ 0, 2197 }, 2198 #endif /* chips */ 2199 2200 #if defined(BCM_56965_A0) 2201 { /* SOC_FORMAT_INT_EFP_KEY2_BCM56965_A0fmt */ 2202 /* format EFP_KEY2fmt */ 2203 /* nFields */ 28, 2204 /* *fields */ soc_EFP_KEY2_BCM56960_A0fmt_fields, 2205 /* bits */ 240, 2206 /* flags */ 0, 2207 }, 2208 #endif /* chips */ 2209 2210 #if defined(BCM_56970_A0) 2211 { /* SOC_FORMAT_INT_EFP_KEY2_BCM56970_A0fmt */ 2212 /* format EFP_KEY2fmt */ 2213 /* nFields */ 28, 2214 /* *fields */ soc_EFP_KEY2_BCM56960_A0fmt_fields, 2215 /* bits */ 240, 2216 /* flags */ 0, 2217 }, 2218 #endif /* chips */ 2219 2220 #if defined(BCM_56980_A0) 2221 { /* SOC_FORMAT_INT_EFP_KEY2_BCM56980_A0fmt */ 2222 /* format EFP_KEY2fmt */ 2223 /* nFields */ 25, 2224 /* *fields */ soc_EFP_KEY2_BCM56980_A0fmt_fields, 2225 /* bits */ 240, 2226 /* flags */ 0, 2227 }, 2228 #endif /* chips */ 2229 2230 #if defined(BCM_56980_B0) 2231 { /* SOC_FORMAT_INT_EFP_KEY2_BCM56980_B0fmt */ 2232 /* format EFP_KEY2fmt */ 2233 /* nFields */ 25, 2234 /* *fields */ soc_EFP_KEY2_BCM56980_A0fmt_fields, 2235 /* bits */ 240, 2236 /* flags */ 0, 2237 }, 2238 #endif /* chips */ 2239 2240 #if defined(BCM_53400_A0) 2241 { /* SOC_FORMAT_INT_EFP_KEY3_BCM53400_A0fmt */ 2242 /* format EFP_KEY3fmt */ 2243 /* nFields */ 14, 2244 /* *fields */ soc_EFP_KEY3_BCM53400_A0fmt_fields, 2245 /* bits */ 214, 2246 /* flags */ 0, 2247 }, 2248 #endif /* chips */ 2249 2250 #if defined(BCM_53540_A0) 2251 { /* SOC_FORMAT_INT_EFP_KEY3_BCM53540_A0fmt */ 2252 /* format EFP_KEY3fmt */ 2253 /* nFields */ 14, 2254 /* *fields */ soc_EFP_KEY3_BCM53400_A0fmt_fields, 2255 /* bits */ 214, 2256 /* flags */ 0, 2257 }, 2258 #endif /* chips */ 2259 2260 #if defined(BCM_53570_A0) 2261 { /* SOC_FORMAT_INT_EFP_KEY3_BCM53570_A0fmt */ 2262 /* format EFP_KEY3fmt */ 2263 /* nFields */ 16, 2264 /* *fields */ soc_EFP_KEY3_BCM53570_A0fmt_fields, 2265 /* bits */ 217, 2266 /* flags */ 0, 2267 }, 2268 #endif /* chips */ 2269 2270 #if defined(BCM_53570_B0) 2271 { /* SOC_FORMAT_INT_EFP_KEY3_BCM53570_B0fmt */ 2272 /* format EFP_KEY3fmt */ 2273 /* nFields */ 17, 2274 /* *fields */ soc_EFP_KEY3_BCM53570_B0fmt_fields, 2275 /* bits */ 217, 2276 /* flags */ 0, 2277 }, 2278 #endif /* chips */ 2279 2280 #if defined(BCM_56142_A0) 2281 { /* SOC_FORMAT_INT_EFP_KEY3_BCM56142_A0fmt */ 2282 /* format EFP_KEY3fmt */ 2283 /* nFields */ 13, 2284 /* *fields */ soc_EFP_KEY3_BCM56624_A0fmt_fields, 2285 /* bits */ 214, 2286 /* flags */ 0, 2287 }, 2288 #endif /* chips */ 2289 2290 #if defined(BCM_56150_A0) 2291 { /* SOC_FORMAT_INT_EFP_KEY3_BCM56150_A0fmt */ 2292 /* format EFP_KEY3fmt */ 2293 /* nFields */ 13, 2294 /* *fields */ soc_EFP_KEY3_BCM56150_A0fmt_fields, 2295 /* bits */ 214, 2296 /* flags */ 0, 2297 }, 2298 #endif /* chips */ 2299 2300 #if defined(BCM_56160_A0) 2301 { /* SOC_FORMAT_INT_EFP_KEY3_BCM56160_A0fmt */ 2302 /* format EFP_KEY3fmt */ 2303 /* nFields */ 14, 2304 /* *fields */ soc_EFP_KEY3_BCM53400_A0fmt_fields, 2305 /* bits */ 214, 2306 /* flags */ 0, 2307 }, 2308 #endif /* chips */ 2309 2310 #if defined(BCM_56260_A0) 2311 { /* SOC_FORMAT_INT_EFP_KEY3_BCM56260_A0fmt */ 2312 /* format EFP_KEY3fmt */ 2313 /* nFields */ 19, 2314 /* *fields */ soc_EFP_KEY3_BCM56260_A0fmt_fields, 2315 /* bits */ 234, 2316 /* flags */ 0, 2317 }, 2318 #endif /* chips */ 2319 2320 #if defined(BCM_56260_B0) 2321 { /* SOC_FORMAT_INT_EFP_KEY3_BCM56260_B0fmt */ 2322 /* format EFP_KEY3fmt */ 2323 /* nFields */ 19, 2324 /* *fields */ soc_EFP_KEY3_BCM56260_A0fmt_fields, 2325 /* bits */ 234, 2326 /* flags */ 0, 2327 }, 2328 #endif /* chips */ 2329 2330 #if defined(BCM_56270_A0) 2331 { /* SOC_FORMAT_INT_EFP_KEY3_BCM56270_A0fmt */ 2332 /* format EFP_KEY3fmt */ 2333 /* nFields */ 19, 2334 /* *fields */ soc_EFP_KEY3_BCM56260_A0fmt_fields, 2335 /* bits */ 234, 2336 /* flags */ 0, 2337 }, 2338 #endif /* chips */ 2339 2340 #if defined(BCM_56334_A0) 2341 { /* SOC_FORMAT_INT_EFP_KEY3_BCM56334_A0fmt */ 2342 /* format EFP_KEY3fmt */ 2343 /* nFields */ 13, 2344 /* *fields */ soc_EFP_KEY3_BCM56624_A0fmt_fields, 2345 /* bits */ 214, 2346 /* flags */ 0, 2347 }, 2348 #endif /* chips */ 2349 2350 #if defined(BCM_56334_B0) 2351 { /* SOC_FORMAT_INT_EFP_KEY3_BCM56334_B0fmt */ 2352 /* format EFP_KEY3fmt */ 2353 /* nFields */ 13, 2354 /* *fields */ soc_EFP_KEY3_BCM56624_A0fmt_fields, 2355 /* bits */ 214, 2356 /* flags */ 0, 2357 }, 2358 #endif /* chips */ 2359 2360 #if defined(BCM_56340_A0) 2361 { /* SOC_FORMAT_INT_EFP_KEY3_BCM56340_A0fmt */ 2362 /* format EFP_KEY3fmt */ 2363 /* nFields */ 19, 2364 /* *fields */ soc_EFP_KEY3_BCM56640_A0fmt_fields, 2365 /* bits */ 234, 2366 /* flags */ 0, 2367 }, 2368 #endif /* chips */ 2369 2370 #if defined(BCM_56370_A0) 2371 { /* SOC_FORMAT_INT_EFP_KEY3_BCM56370_A0fmt */ 2372 /* format EFP_KEY3fmt */ 2373 /* nFields */ 22, 2374 /* *fields */ soc_EFP_KEY3_BCM56870_A0fmt_fields, 2375 /* bits */ 272, 2376 /* flags */ 0, 2377 }, 2378 #endif /* chips */ 2379 2380 #if defined(BCM_56440_A0) 2381 { /* SOC_FORMAT_INT_EFP_KEY3_BCM56440_A0fmt */ 2382 /* format EFP_KEY3fmt */ 2383 /* nFields */ 15, 2384 /* *fields */ soc_EFP_KEY3_BCM56440_A0fmt_fields, 2385 /* bits */ 214, 2386 /* flags */ 0, 2387 }, 2388 #endif /* chips */ 2389 2390 #if defined(BCM_56440_B0) 2391 { /* SOC_FORMAT_INT_EFP_KEY3_BCM56440_B0fmt */ 2392 /* format EFP_KEY3fmt */ 2393 /* nFields */ 15, 2394 /* *fields */ soc_EFP_KEY3_BCM56440_A0fmt_fields, 2395 /* bits */ 214, 2396 /* flags */ 0, 2397 }, 2398 #endif /* chips */ 2399 2400 #if defined(BCM_56450_A0) 2401 { /* SOC_FORMAT_INT_EFP_KEY3_BCM56450_A0fmt */ 2402 /* format EFP_KEY3fmt */ 2403 /* nFields */ 19, 2404 /* *fields */ soc_EFP_KEY3_BCM56640_A0fmt_fields, 2405 /* bits */ 234, 2406 /* flags */ 0, 2407 }, 2408 #endif /* chips */ 2409 2410 #if defined(BCM_56450_B0) 2411 { /* SOC_FORMAT_INT_EFP_KEY3_BCM56450_B0fmt */ 2412 /* format EFP_KEY3fmt */ 2413 /* nFields */ 19, 2414 /* *fields */ soc_EFP_KEY3_BCM56640_A0fmt_fields, 2415 /* bits */ 234, 2416 /* flags */ 0, 2417 }, 2418 #endif /* chips */ 2419 2420 #if defined(BCM_56450_B1) 2421 { /* SOC_FORMAT_INT_EFP_KEY3_BCM56450_B1fmt */ 2422 /* format EFP_KEY3fmt */ 2423 /* nFields */ 19, 2424 /* *fields */ soc_EFP_KEY3_BCM56640_A0fmt_fields, 2425 /* bits */ 234, 2426 /* flags */ 0, 2427 }, 2428 #endif /* chips */ 2429 2430 #if defined(BCM_56524_A0) 2431 { /* SOC_FORMAT_INT_EFP_KEY3_BCM56524_A0fmt */ 2432 /* format EFP_KEY3fmt */ 2433 /* nFields */ 15, 2434 /* *fields */ soc_EFP_KEY3_BCM56634_A0fmt_fields, 2435 /* bits */ 214, 2436 /* flags */ 0, 2437 }, 2438 #endif /* chips */ 2439 2440 #if defined(BCM_56524_B0) 2441 { /* SOC_FORMAT_INT_EFP_KEY3_BCM56524_B0fmt */ 2442 /* format EFP_KEY3fmt */ 2443 /* nFields */ 15, 2444 /* *fields */ soc_EFP_KEY3_BCM56634_A0fmt_fields, 2445 /* bits */ 214, 2446 /* flags */ 0, 2447 }, 2448 #endif /* chips */ 2449 2450 #if defined(BCM_56560_A0) 2451 { /* SOC_FORMAT_INT_EFP_KEY3_BCM56560_A0fmt */ 2452 /* format EFP_KEY3fmt */ 2453 /* nFields */ 17, 2454 /* *fields */ soc_EFP_KEY3_BCM56560_A0fmt_fields, 2455 /* bits */ 234, 2456 /* flags */ 0, 2457 }, 2458 #endif /* chips */ 2459 2460 #if defined(BCM_56560_B0) 2461 { /* SOC_FORMAT_INT_EFP_KEY3_BCM56560_B0fmt */ 2462 /* format EFP_KEY3fmt */ 2463 /* nFields */ 17, 2464 /* *fields */ soc_EFP_KEY3_BCM56560_A0fmt_fields, 2465 /* bits */ 234, 2466 /* flags */ 0, 2467 }, 2468 #endif /* chips */ 2469 2470 #if defined(BCM_56624_A0) 2471 { /* SOC_FORMAT_INT_EFP_KEY3_BCM56624_A0fmt */ 2472 /* format EFP_KEY3fmt */ 2473 /* nFields */ 13, 2474 /* *fields */ soc_EFP_KEY3_BCM56624_A0fmt_fields, 2475 /* bits */ 214, 2476 /* flags */ 0, 2477 }, 2478 #endif /* chips */ 2479 2480 #if defined(BCM_56624_B0) 2481 { /* SOC_FORMAT_INT_EFP_KEY3_BCM56624_B0fmt */ 2482 /* format EFP_KEY3fmt */ 2483 /* nFields */ 13, 2484 /* *fields */ soc_EFP_KEY3_BCM56624_A0fmt_fields, 2485 /* bits */ 214, 2486 /* flags */ 0, 2487 }, 2488 #endif /* chips */ 2489 2490 #if defined(BCM_56634_A0) 2491 { /* SOC_FORMAT_INT_EFP_KEY3_BCM56634_A0fmt */ 2492 /* format EFP_KEY3fmt */ 2493 /* nFields */ 15, 2494 /* *fields */ soc_EFP_KEY3_BCM56634_A0fmt_fields, 2495 /* bits */ 214, 2496 /* flags */ 0, 2497 }, 2498 #endif /* chips */ 2499 2500 #if defined(BCM_56634_B0) 2501 { /* SOC_FORMAT_INT_EFP_KEY3_BCM56634_B0fmt */ 2502 /* format EFP_KEY3fmt */ 2503 /* nFields */ 15, 2504 /* *fields */ soc_EFP_KEY3_BCM56634_A0fmt_fields, 2505 /* bits */ 214, 2506 /* flags */ 0, 2507 }, 2508 #endif /* chips */ 2509 2510 #if defined(BCM_56640_A0) 2511 { /* SOC_FORMAT_INT_EFP_KEY3_BCM56640_A0fmt */ 2512 /* format EFP_KEY3fmt */ 2513 /* nFields */ 19, 2514 /* *fields */ soc_EFP_KEY3_BCM56640_A0fmt_fields, 2515 /* bits */ 234, 2516 /* flags */ 0, 2517 }, 2518 #endif /* chips */ 2519 2520 #if defined(BCM_56670_A0) 2521 { /* SOC_FORMAT_INT_EFP_KEY3_BCM56670_A0fmt */ 2522 /* format EFP_KEY3fmt */ 2523 /* nFields */ 18, 2524 /* *fields */ soc_EFP_KEY3_BCM56670_A0fmt_fields, 2525 /* bits */ 234, 2526 /* flags */ 0, 2527 }, 2528 #endif /* chips */ 2529 2530 #if defined(BCM_56670_B0) 2531 { /* SOC_FORMAT_INT_EFP_KEY3_BCM56670_B0fmt */ 2532 /* format EFP_KEY3fmt */ 2533 /* nFields */ 18, 2534 /* *fields */ soc_EFP_KEY3_BCM56670_A0fmt_fields, 2535 /* bits */ 234, 2536 /* flags */ 0, 2537 }, 2538 #endif /* chips */ 2539 2540 #if defined(BCM_56680_A0) 2541 { /* SOC_FORMAT_INT_EFP_KEY3_BCM56680_A0fmt */ 2542 /* format EFP_KEY3fmt */ 2543 /* nFields */ 13, 2544 /* *fields */ soc_EFP_KEY3_BCM56624_A0fmt_fields, 2545 /* bits */ 214, 2546 /* flags */ 0, 2547 }, 2548 #endif /* chips */ 2549 2550 #if defined(BCM_56680_B0) 2551 { /* SOC_FORMAT_INT_EFP_KEY3_BCM56680_B0fmt */ 2552 /* format EFP_KEY3fmt */ 2553 /* nFields */ 13, 2554 /* *fields */ soc_EFP_KEY3_BCM56624_A0fmt_fields, 2555 /* bits */ 214, 2556 /* flags */ 0, 2557 }, 2558 #endif /* chips */ 2559 2560 #if defined(BCM_56685_A0) 2561 { /* SOC_FORMAT_INT_EFP_KEY3_BCM56685_A0fmt */ 2562 /* format EFP_KEY3fmt */ 2563 /* nFields */ 15, 2564 /* *fields */ soc_EFP_KEY3_BCM56634_A0fmt_fields, 2565 /* bits */ 214, 2566 /* flags */ 0, 2567 }, 2568 #endif /* chips */ 2569 2570 #if defined(BCM_56685_B0) 2571 { /* SOC_FORMAT_INT_EFP_KEY3_BCM56685_B0fmt */ 2572 /* format EFP_KEY3fmt */ 2573 /* nFields */ 15, 2574 /* *fields */ soc_EFP_KEY3_BCM56634_A0fmt_fields, 2575 /* bits */ 214, 2576 /* flags */ 0, 2577 }, 2578 #endif /* chips */ 2579 2580 #if defined(BCM_56725_A0) 2581 { /* SOC_FORMAT_INT_EFP_KEY3_BCM56725_A0fmt */ 2582 /* format EFP_KEY3fmt */ 2583 /* nFields */ 13, 2584 /* *fields */ soc_EFP_KEY3_BCM56820_A0fmt_fields, 2585 /* bits */ 210, 2586 /* flags */ 0, 2587 }, 2588 #endif /* chips */ 2589 2590 #if defined(BCM_56770_A0) 2591 { /* SOC_FORMAT_INT_EFP_KEY3_BCM56770_A0fmt */ 2592 /* format EFP_KEY3fmt */ 2593 /* nFields */ 22, 2594 /* *fields */ soc_EFP_KEY3_BCM56870_A0fmt_fields, 2595 /* bits */ 272, 2596 /* flags */ 0, 2597 }, 2598 #endif /* chips */ 2599 2600 #if defined(BCM_56820_A0) 2601 { /* SOC_FORMAT_INT_EFP_KEY3_BCM56820_A0fmt */ 2602 /* format EFP_KEY3fmt */ 2603 /* nFields */ 13, 2604 /* *fields */ soc_EFP_KEY3_BCM56820_A0fmt_fields, 2605 /* bits */ 210, 2606 /* flags */ 0, 2607 }, 2608 #endif /* chips */ 2609 2610 #if defined(BCM_56840_A0) 2611 { /* SOC_FORMAT_INT_EFP_KEY3_BCM56840_A0fmt */ 2612 /* format EFP_KEY3fmt */ 2613 /* nFields */ 15, 2614 /* *fields */ soc_EFP_KEY3_BCM56634_A0fmt_fields, 2615 /* bits */ 214, 2616 /* flags */ 0, 2617 }, 2618 #endif /* chips */ 2619 2620 #if defined(BCM_56840_B0) 2621 { /* SOC_FORMAT_INT_EFP_KEY3_BCM56840_B0fmt */ 2622 /* format EFP_KEY3fmt */ 2623 /* nFields */ 15, 2624 /* *fields */ soc_EFP_KEY3_BCM56634_A0fmt_fields, 2625 /* bits */ 214, 2626 /* flags */ 0, 2627 }, 2628 #endif /* chips */ 2629 2630 #if defined(BCM_56850_A0) 2631 { /* SOC_FORMAT_INT_EFP_KEY3_BCM56850_A0fmt */ 2632 /* format EFP_KEY3fmt */ 2633 /* nFields */ 17, 2634 /* *fields */ soc_EFP_KEY3_BCM56850_A0fmt_fields, 2635 /* bits */ 234, 2636 /* flags */ 0, 2637 }, 2638 #endif /* chips */ 2639 2640 #if defined(BCM_56860_A0) 2641 { /* SOC_FORMAT_INT_EFP_KEY3_BCM56860_A0fmt */ 2642 /* format EFP_KEY3fmt */ 2643 /* nFields */ 19, 2644 /* *fields */ soc_EFP_KEY3_BCM56860_A0fmt_fields, 2645 /* bits */ 234, 2646 /* flags */ 0, 2647 }, 2648 #endif /* chips */ 2649 2650 #if defined(BCM_56870_A0) 2651 { /* SOC_FORMAT_INT_EFP_KEY3_BCM56870_A0fmt */ 2652 /* format EFP_KEY3fmt */ 2653 /* nFields */ 22, 2654 /* *fields */ soc_EFP_KEY3_BCM56870_A0fmt_fields, 2655 /* bits */ 272, 2656 /* flags */ 0, 2657 }, 2658 #endif /* chips */ 2659 2660 #if defined(BCM_56960_A0) 2661 { /* SOC_FORMAT_INT_EFP_KEY3_BCM56960_A0fmt */ 2662 /* format EFP_KEY3fmt */ 2663 /* nFields */ 20, 2664 /* *fields */ soc_EFP_KEY3_BCM56960_A0fmt_fields, 2665 /* bits */ 240, 2666 /* flags */ 0, 2667 }, 2668 #endif /* chips */ 2669 2670 #if defined(BCM_56965_A0) 2671 { /* SOC_FORMAT_INT_EFP_KEY3_BCM56965_A0fmt */ 2672 /* format EFP_KEY3fmt */ 2673 /* nFields */ 20, 2674 /* *fields */ soc_EFP_KEY3_BCM56960_A0fmt_fields, 2675 /* bits */ 240, 2676 /* flags */ 0, 2677 }, 2678 #endif /* chips */ 2679 2680 #if defined(BCM_56970_A0) 2681 { /* SOC_FORMAT_INT_EFP_KEY3_BCM56970_A0fmt */ 2682 /* format EFP_KEY3fmt */ 2683 /* nFields */ 20, 2684 /* *fields */ soc_EFP_KEY3_BCM56960_A0fmt_fields, 2685 /* bits */ 240, 2686 /* flags */ 0, 2687 }, 2688 #endif /* chips */ 2689 2690 #if defined(BCM_56980_A0) 2691 { /* SOC_FORMAT_INT_EFP_KEY3_BCM56980_A0fmt */ 2692 /* format EFP_KEY3fmt */ 2693 /* nFields */ 20, 2694 /* *fields */ soc_EFP_KEY3_BCM56980_A0fmt_fields, 2695 /* bits */ 240, 2696 /* flags */ 0, 2697 }, 2698 #endif /* chips */ 2699 2700 #if defined(BCM_56980_B0) 2701 { /* SOC_FORMAT_INT_EFP_KEY3_BCM56980_B0fmt */ 2702 /* format EFP_KEY3fmt */ 2703 /* nFields */ 20, 2704 /* *fields */ soc_EFP_KEY3_BCM56980_A0fmt_fields, 2705 /* bits */ 240, 2706 /* flags */ 0, 2707 }, 2708 #endif /* chips */ 2709 2710 #if defined(BCM_53400_A0) 2711 { /* SOC_FORMAT_INT_EFP_KEY4_BCM53400_A0fmt */ 2712 /* format EFP_KEY4fmt */ 2713 /* nFields */ 27, 2714 /* *fields */ soc_EFP_KEY4_BCM53400_A0fmt_fields, 2715 /* bits */ 214, 2716 /* flags */ 0, 2717 }, 2718 #endif /* chips */ 2719 2720 #if defined(BCM_53540_A0) 2721 { /* SOC_FORMAT_INT_EFP_KEY4_BCM53540_A0fmt */ 2722 /* format EFP_KEY4fmt */ 2723 /* nFields */ 27, 2724 /* *fields */ soc_EFP_KEY4_BCM53400_A0fmt_fields, 2725 /* bits */ 214, 2726 /* flags */ 0, 2727 }, 2728 #endif /* chips */ 2729 2730 #if defined(BCM_53570_A0) 2731 { /* SOC_FORMAT_INT_EFP_KEY4_BCM53570_A0fmt */ 2732 /* format EFP_KEY4fmt */ 2733 /* nFields */ 28, 2734 /* *fields */ soc_EFP_KEY4_BCM53570_A0fmt_fields, 2735 /* bits */ 217, 2736 /* flags */ 0, 2737 }, 2738 #endif /* chips */ 2739 2740 #if defined(BCM_53570_B0) 2741 { /* SOC_FORMAT_INT_EFP_KEY4_BCM53570_B0fmt */ 2742 /* format EFP_KEY4fmt */ 2743 /* nFields */ 29, 2744 /* *fields */ soc_EFP_KEY4_BCM53570_B0fmt_fields, 2745 /* bits */ 217, 2746 /* flags */ 0, 2747 }, 2748 #endif /* chips */ 2749 2750 #if defined(BCM_56142_A0) 2751 { /* SOC_FORMAT_INT_EFP_KEY4_BCM56142_A0fmt */ 2752 /* format EFP_KEY4fmt */ 2753 /* nFields */ 25, 2754 /* *fields */ soc_EFP_KEY4_BCM56624_A0fmt_fields, 2755 /* bits */ 214, 2756 /* flags */ 0, 2757 }, 2758 #endif /* chips */ 2759 2760 #if defined(BCM_56150_A0) 2761 { /* SOC_FORMAT_INT_EFP_KEY4_BCM56150_A0fmt */ 2762 /* format EFP_KEY4fmt */ 2763 /* nFields */ 26, 2764 /* *fields */ soc_EFP_KEY4_BCM56150_A0fmt_fields, 2765 /* bits */ 214, 2766 /* flags */ 0, 2767 }, 2768 #endif /* chips */ 2769 2770 #if defined(BCM_56160_A0) 2771 { /* SOC_FORMAT_INT_EFP_KEY4_BCM56160_A0fmt */ 2772 /* format EFP_KEY4fmt */ 2773 /* nFields */ 27, 2774 /* *fields */ soc_EFP_KEY4_BCM53400_A0fmt_fields, 2775 /* bits */ 214, 2776 /* flags */ 0, 2777 }, 2778 #endif /* chips */ 2779 2780 #if defined(BCM_56260_A0) 2781 { /* SOC_FORMAT_INT_EFP_KEY4_BCM56260_A0fmt */ 2782 /* format EFP_KEY4fmt */ 2783 /* nFields */ 40, 2784 /* *fields */ soc_EFP_KEY4_BCM56260_A0fmt_fields, 2785 /* bits */ 234, 2786 /* flags */ 0, 2787 }, 2788 #endif /* chips */ 2789 2790 #if defined(BCM_56260_B0) 2791 { /* SOC_FORMAT_INT_EFP_KEY4_BCM56260_B0fmt */ 2792 /* format EFP_KEY4fmt */ 2793 /* nFields */ 40, 2794 /* *fields */ soc_EFP_KEY4_BCM56260_A0fmt_fields, 2795 /* bits */ 234, 2796 /* flags */ 0, 2797 }, 2798 #endif /* chips */ 2799 2800 #if defined(BCM_56270_A0) 2801 { /* SOC_FORMAT_INT_EFP_KEY4_BCM56270_A0fmt */ 2802 /* format EFP_KEY4fmt */ 2803 /* nFields */ 40, 2804 /* *fields */ soc_EFP_KEY4_BCM56260_A0fmt_fields, 2805 /* bits */ 234, 2806 /* flags */ 0, 2807 }, 2808 #endif /* chips */ 2809 2810 #if defined(BCM_56334_A0) 2811 { /* SOC_FORMAT_INT_EFP_KEY4_BCM56334_A0fmt */ 2812 /* format EFP_KEY4fmt */ 2813 /* nFields */ 25, 2814 /* *fields */ soc_EFP_KEY4_BCM56624_A0fmt_fields, 2815 /* bits */ 214, 2816 /* flags */ 0, 2817 }, 2818 #endif /* chips */ 2819 2820 #if defined(BCM_56334_B0) 2821 { /* SOC_FORMAT_INT_EFP_KEY4_BCM56334_B0fmt */ 2822 /* format EFP_KEY4fmt */ 2823 /* nFields */ 25, 2824 /* *fields */ soc_EFP_KEY4_BCM56624_A0fmt_fields, 2825 /* bits */ 214, 2826 /* flags */ 0, 2827 }, 2828 #endif /* chips */ 2829 2830 #if defined(BCM_56340_A0) 2831 { /* SOC_FORMAT_INT_EFP_KEY4_BCM56340_A0fmt */ 2832 /* format EFP_KEY4fmt */ 2833 /* nFields */ 38, 2834 /* *fields */ soc_EFP_KEY4_BCM56340_A0fmt_fields, 2835 /* bits */ 234, 2836 /* flags */ 0, 2837 }, 2838 #endif /* chips */ 2839 2840 #if defined(BCM_56370_A0) 2841 { /* SOC_FORMAT_INT_EFP_KEY4_BCM56370_A0fmt */ 2842 /* format EFP_KEY4fmt */ 2843 /* nFields */ 44, 2844 /* *fields */ soc_EFP_KEY4_BCM56870_A0fmt_fields, 2845 /* bits */ 272, 2846 /* flags */ 0, 2847 }, 2848 #endif /* chips */ 2849 2850 #if defined(BCM_56440_A0) 2851 { /* SOC_FORMAT_INT_EFP_KEY4_BCM56440_A0fmt */ 2852 /* format EFP_KEY4fmt */ 2853 /* nFields */ 31, 2854 /* *fields */ soc_EFP_KEY4_BCM56440_A0fmt_fields, 2855 /* bits */ 214, 2856 /* flags */ 0, 2857 }, 2858 #endif /* chips */ 2859 2860 #if defined(BCM_56440_B0) 2861 { /* SOC_FORMAT_INT_EFP_KEY4_BCM56440_B0fmt */ 2862 /* format EFP_KEY4fmt */ 2863 /* nFields */ 31, 2864 /* *fields */ soc_EFP_KEY4_BCM56440_A0fmt_fields, 2865 /* bits */ 214, 2866 /* flags */ 0, 2867 }, 2868 #endif /* chips */ 2869 2870 #if defined(BCM_56450_A0) 2871 { /* SOC_FORMAT_INT_EFP_KEY4_BCM56450_A0fmt */ 2872 /* format EFP_KEY4fmt */ 2873 /* nFields */ 39, 2874 /* *fields */ soc_EFP_KEY4_BCM56450_A0fmt_fields, 2875 /* bits */ 234, 2876 /* flags */ 0, 2877 }, 2878 #endif /* chips */ 2879 2880 #if defined(BCM_56450_B0) 2881 { /* SOC_FORMAT_INT_EFP_KEY4_BCM56450_B0fmt */ 2882 /* format EFP_KEY4fmt */ 2883 /* nFields */ 39, 2884 /* *fields */ soc_EFP_KEY4_BCM56450_A0fmt_fields, 2885 /* bits */ 234, 2886 /* flags */ 0, 2887 }, 2888 #endif /* chips */ 2889 2890 #if defined(BCM_56450_B1) 2891 { /* SOC_FORMAT_INT_EFP_KEY4_BCM56450_B1fmt */ 2892 /* format EFP_KEY4fmt */ 2893 /* nFields */ 39, 2894 /* *fields */ soc_EFP_KEY4_BCM56450_A0fmt_fields, 2895 /* bits */ 234, 2896 /* flags */ 0, 2897 }, 2898 #endif /* chips */ 2899 2900 #if defined(BCM_56524_A0) 2901 { /* SOC_FORMAT_INT_EFP_KEY4_BCM56524_A0fmt */ 2902 /* format EFP_KEY4fmt */ 2903 /* nFields */ 27, 2904 /* *fields */ soc_EFP_KEY4_BCM56634_A0fmt_fields, 2905 /* bits */ 214, 2906 /* flags */ 0, 2907 }, 2908 #endif /* chips */ 2909 2910 #if defined(BCM_56524_B0) 2911 { /* SOC_FORMAT_INT_EFP_KEY4_BCM56524_B0fmt */ 2912 /* format EFP_KEY4fmt */ 2913 /* nFields */ 27, 2914 /* *fields */ soc_EFP_KEY4_BCM56634_A0fmt_fields, 2915 /* bits */ 214, 2916 /* flags */ 0, 2917 }, 2918 #endif /* chips */ 2919 2920 #if defined(BCM_56560_A0) 2921 { /* SOC_FORMAT_INT_EFP_KEY4_BCM56560_A0fmt */ 2922 /* format EFP_KEY4fmt */ 2923 /* nFields */ 43, 2924 /* *fields */ soc_EFP_KEY4_BCM56560_A0fmt_fields, 2925 /* bits */ 234, 2926 /* flags */ 0, 2927 }, 2928 #endif /* chips */ 2929 2930 #if defined(BCM_56560_B0) 2931 { /* SOC_FORMAT_INT_EFP_KEY4_BCM56560_B0fmt */ 2932 /* format EFP_KEY4fmt */ 2933 /* nFields */ 43, 2934 /* *fields */ soc_EFP_KEY4_BCM56560_A0fmt_fields, 2935 /* bits */ 234, 2936 /* flags */ 0, 2937 }, 2938 #endif /* chips */ 2939 2940 #if defined(BCM_56624_A0) 2941 { /* SOC_FORMAT_INT_EFP_KEY4_BCM56624_A0fmt */ 2942 /* format EFP_KEY4fmt */ 2943 /* nFields */ 25, 2944 /* *fields */ soc_EFP_KEY4_BCM56624_A0fmt_fields, 2945 /* bits */ 214, 2946 /* flags */ 0, 2947 }, 2948 #endif /* chips */ 2949 2950 #if defined(BCM_56624_B0) 2951 { /* SOC_FORMAT_INT_EFP_KEY4_BCM56624_B0fmt */ 2952 /* format EFP_KEY4fmt */ 2953 /* nFields */ 25, 2954 /* *fields */ soc_EFP_KEY4_BCM56624_A0fmt_fields, 2955 /* bits */ 214, 2956 /* flags */ 0, 2957 }, 2958 #endif /* chips */ 2959 2960 #if defined(BCM_56634_A0) 2961 { /* SOC_FORMAT_INT_EFP_KEY4_BCM56634_A0fmt */ 2962 /* format EFP_KEY4fmt */ 2963 /* nFields */ 27, 2964 /* *fields */ soc_EFP_KEY4_BCM56634_A0fmt_fields, 2965 /* bits */ 214, 2966 /* flags */ 0, 2967 }, 2968 #endif /* chips */ 2969 2970 #if defined(BCM_56634_B0) 2971 { /* SOC_FORMAT_INT_EFP_KEY4_BCM56634_B0fmt */ 2972 /* format EFP_KEY4fmt */ 2973 /* nFields */ 27, 2974 /* *fields */ soc_EFP_KEY4_BCM56634_A0fmt_fields, 2975 /* bits */ 214, 2976 /* flags */ 0, 2977 }, 2978 #endif /* chips */ 2979 2980 #if defined(BCM_56640_A0) 2981 { /* SOC_FORMAT_INT_EFP_KEY4_BCM56640_A0fmt */ 2982 /* format EFP_KEY4fmt */ 2983 /* nFields */ 37, 2984 /* *fields */ soc_EFP_KEY4_BCM56640_A0fmt_fields, 2985 /* bits */ 234, 2986 /* flags */ 0, 2987 }, 2988 #endif /* chips */ 2989 2990 #if defined(BCM_56670_A0) 2991 { /* SOC_FORMAT_INT_EFP_KEY4_BCM56670_A0fmt */ 2992 /* format EFP_KEY4fmt */ 2993 /* nFields */ 43, 2994 /* *fields */ soc_EFP_KEY4_BCM56670_A0fmt_fields, 2995 /* bits */ 234, 2996 /* flags */ 0, 2997 }, 2998 #endif /* chips */ 2999 3000 #if defined(BCM_56670_B0) 3001 { /* SOC_FORMAT_INT_EFP_KEY4_BCM56670_B0fmt */ 3002 /* format EFP_KEY4fmt */ 3003 /* nFields */ 43, 3004 /* *fields */ soc_EFP_KEY4_BCM56670_A0fmt_fields, 3005 /* bits */ 234, 3006 /* flags */ 0, 3007 }, 3008 #endif /* chips */ 3009 3010 #if defined(BCM_56680_A0) 3011 { /* SOC_FORMAT_INT_EFP_KEY4_BCM56680_A0fmt */ 3012 /* format EFP_KEY4fmt */ 3013 /* nFields */ 25, 3014 /* *fields */ soc_EFP_KEY4_BCM56624_A0fmt_fields, 3015 /* bits */ 214, 3016 /* flags */ 0, 3017 }, 3018 #endif /* chips */ 3019 3020 #if defined(BCM_56680_B0) 3021 { /* SOC_FORMAT_INT_EFP_KEY4_BCM56680_B0fmt */ 3022 /* format EFP_KEY4fmt */ 3023 /* nFields */ 25, 3024 /* *fields */ soc_EFP_KEY4_BCM56624_A0fmt_fields, 3025 /* bits */ 214, 3026 /* flags */ 0, 3027 }, 3028 #endif /* chips */ 3029 3030 #if defined(BCM_56685_A0) 3031 { /* SOC_FORMAT_INT_EFP_KEY4_BCM56685_A0fmt */ 3032 /* format EFP_KEY4fmt */ 3033 /* nFields */ 27, 3034 /* *fields */ soc_EFP_KEY4_BCM56634_A0fmt_fields, 3035 /* bits */ 214, 3036 /* flags */ 0, 3037 }, 3038 #endif /* chips */ 3039 3040 #if defined(BCM_56685_B0) 3041 { /* SOC_FORMAT_INT_EFP_KEY4_BCM56685_B0fmt */ 3042 /* format EFP_KEY4fmt */ 3043 /* nFields */ 27, 3044 /* *fields */ soc_EFP_KEY4_BCM56634_A0fmt_fields, 3045 /* bits */ 214, 3046 /* flags */ 0, 3047 }, 3048 #endif /* chips */ 3049 3050 #if defined(BCM_56725_A0) 3051 { /* SOC_FORMAT_INT_EFP_KEY4_BCM56725_A0fmt */ 3052 /* format EFP_KEY4fmt */ 3053 /* nFields */ 25, 3054 /* *fields */ soc_EFP_KEY4_BCM56820_A0fmt_fields, 3055 /* bits */ 210, 3056 /* flags */ 0, 3057 }, 3058 #endif /* chips */ 3059 3060 #if defined(BCM_56770_A0) 3061 { /* SOC_FORMAT_INT_EFP_KEY4_BCM56770_A0fmt */ 3062 /* format EFP_KEY4fmt */ 3063 /* nFields */ 44, 3064 /* *fields */ soc_EFP_KEY4_BCM56870_A0fmt_fields, 3065 /* bits */ 272, 3066 /* flags */ 0, 3067 }, 3068 #endif /* chips */ 3069 3070 #if defined(BCM_56820_A0) 3071 { /* SOC_FORMAT_INT_EFP_KEY4_BCM56820_A0fmt */ 3072 /* format EFP_KEY4fmt */ 3073 /* nFields */ 25, 3074 /* *fields */ soc_EFP_KEY4_BCM56820_A0fmt_fields, 3075 /* bits */ 210, 3076 /* flags */ 0, 3077 }, 3078 #endif /* chips */ 3079 3080 #if defined(BCM_56840_A0) 3081 { /* SOC_FORMAT_INT_EFP_KEY4_BCM56840_A0fmt */ 3082 /* format EFP_KEY4fmt */ 3083 /* nFields */ 29, 3084 /* *fields */ soc_EFP_KEY4_BCM56840_A0fmt_fields, 3085 /* bits */ 214, 3086 /* flags */ 0, 3087 }, 3088 #endif /* chips */ 3089 3090 #if defined(BCM_56840_B0) 3091 { /* SOC_FORMAT_INT_EFP_KEY4_BCM56840_B0fmt */ 3092 /* format EFP_KEY4fmt */ 3093 /* nFields */ 29, 3094 /* *fields */ soc_EFP_KEY4_BCM56840_B0fmt_fields, 3095 /* bits */ 214, 3096 /* flags */ 0, 3097 }, 3098 #endif /* chips */ 3099 3100 #if defined(BCM_56850_A0) 3101 { /* SOC_FORMAT_INT_EFP_KEY4_BCM56850_A0fmt */ 3102 /* format EFP_KEY4fmt */ 3103 /* nFields */ 37, 3104 /* *fields */ soc_EFP_KEY4_BCM56850_A0fmt_fields, 3105 /* bits */ 234, 3106 /* flags */ 0, 3107 }, 3108 #endif /* chips */ 3109 3110 #if defined(BCM_56860_A0) 3111 { /* SOC_FORMAT_INT_EFP_KEY4_BCM56860_A0fmt */ 3112 /* format EFP_KEY4fmt */ 3113 /* nFields */ 43, 3114 /* *fields */ soc_EFP_KEY4_BCM56860_A0fmt_fields, 3115 /* bits */ 234, 3116 /* flags */ 0, 3117 }, 3118 #endif /* chips */ 3119 3120 #if defined(BCM_56870_A0) 3121 { /* SOC_FORMAT_INT_EFP_KEY4_BCM56870_A0fmt */ 3122 /* format EFP_KEY4fmt */ 3123 /* nFields */ 44, 3124 /* *fields */ soc_EFP_KEY4_BCM56870_A0fmt_fields, 3125 /* bits */ 272, 3126 /* flags */ 0, 3127 }, 3128 #endif /* chips */ 3129 3130 #if defined(BCM_56960_A0) 3131 { /* SOC_FORMAT_INT_EFP_KEY4_BCM56960_A0fmt */ 3132 /* format EFP_KEY4fmt */ 3133 /* nFields */ 38, 3134 /* *fields */ soc_EFP_KEY4_BCM56960_A0fmt_fields, 3135 /* bits */ 240, 3136 /* flags */ 0, 3137 }, 3138 #endif /* chips */ 3139 3140 #if defined(BCM_56965_A0) 3141 { /* SOC_FORMAT_INT_EFP_KEY4_BCM56965_A0fmt */ 3142 /* format EFP_KEY4fmt */ 3143 /* nFields */ 38, 3144 /* *fields */ soc_EFP_KEY4_BCM56960_A0fmt_fields, 3145 /* bits */ 240, 3146 /* flags */ 0, 3147 }, 3148 #endif /* chips */ 3149 3150 #if defined(BCM_56970_A0) 3151 { /* SOC_FORMAT_INT_EFP_KEY4_BCM56970_A0fmt */ 3152 /* format EFP_KEY4fmt */ 3153 /* nFields */ 39, 3154 /* *fields */ soc_EFP_KEY4_BCM56970_A0fmt_fields, 3155 /* bits */ 240, 3156 /* flags */ 0, 3157 }, 3158 #endif /* chips */ 3159 3160 #if defined(BCM_56980_A0) 3161 { /* SOC_FORMAT_INT_EFP_KEY4_BCM56980_A0fmt */ 3162 /* format EFP_KEY4fmt */ 3163 /* nFields */ 32, 3164 /* *fields */ soc_EFP_KEY4_BCM56980_A0fmt_fields, 3165 /* bits */ 240, 3166 /* flags */ 0, 3167 }, 3168 #endif /* chips */ 3169 3170 #if defined(BCM_56980_B0) 3171 { /* SOC_FORMAT_INT_EFP_KEY4_BCM56980_B0fmt */ 3172 /* format EFP_KEY4fmt */ 3173 /* nFields */ 32, 3174 /* *fields */ soc_EFP_KEY4_BCM56980_A0fmt_fields, 3175 /* bits */ 240, 3176 /* flags */ 0, 3177 }, 3178 #endif /* chips */ 3179 3180 #if defined(BCM_53570_A0) 3181 { /* SOC_FORMAT_INT_EFP_KEY5_BCM53570_A0fmt */ 3182 /* format EFP_KEY5fmt */ 3183 /* nFields */ 34, 3184 /* *fields */ soc_EFP_KEY5_BCM53570_A0fmt_fields, 3185 /* bits */ 217, 3186 /* flags */ 0, 3187 }, 3188 #endif /* chips */ 3189 3190 #if defined(BCM_53570_B0) 3191 { /* SOC_FORMAT_INT_EFP_KEY5_BCM53570_B0fmt */ 3192 /* format EFP_KEY5fmt */ 3193 /* nFields */ 34, 3194 /* *fields */ soc_EFP_KEY5_BCM53570_A0fmt_fields, 3195 /* bits */ 217, 3196 /* flags */ 0, 3197 }, 3198 #endif /* chips */ 3199 3200 #if defined(BCM_56370_A0) 3201 { /* SOC_FORMAT_INT_EFP_KEY5_BCM56370_A0fmt */ 3202 /* format EFP_KEY5fmt */ 3203 /* nFields */ 34, 3204 /* *fields */ soc_EFP_KEY5_BCM56370_A0fmt_fields, 3205 /* bits */ 272, 3206 /* flags */ 0, 3207 }, 3208 #endif /* chips */ 3209 3210 #if defined(BCM_56560_A0) 3211 { /* SOC_FORMAT_INT_EFP_KEY5_BCM56560_A0fmt */ 3212 /* format EFP_KEY5fmt */ 3213 /* nFields */ 33, 3214 /* *fields */ soc_EFP_KEY5_BCM56560_A0fmt_fields, 3215 /* bits */ 234, 3216 /* flags */ 0, 3217 }, 3218 #endif /* chips */ 3219 3220 #if defined(BCM_56560_B0) 3221 { /* SOC_FORMAT_INT_EFP_KEY5_BCM56560_B0fmt */ 3222 /* format EFP_KEY5fmt */ 3223 /* nFields */ 33, 3224 /* *fields */ soc_EFP_KEY5_BCM56560_A0fmt_fields, 3225 /* bits */ 234, 3226 /* flags */ 0, 3227 }, 3228 #endif /* chips */ 3229 3230 #if defined(BCM_56670_A0) 3231 { /* SOC_FORMAT_INT_EFP_KEY5_BCM56670_A0fmt */ 3232 /* format EFP_KEY5fmt */ 3233 /* nFields */ 34, 3234 /* *fields */ soc_EFP_KEY5_BCM56670_A0fmt_fields, 3235 /* bits */ 234, 3236 /* flags */ 0, 3237 }, 3238 #endif /* chips */ 3239 3240 #if defined(BCM_56670_B0) 3241 { /* SOC_FORMAT_INT_EFP_KEY5_BCM56670_B0fmt */ 3242 /* format EFP_KEY5fmt */ 3243 /* nFields */ 34, 3244 /* *fields */ soc_EFP_KEY5_BCM56670_A0fmt_fields, 3245 /* bits */ 234, 3246 /* flags */ 0, 3247 }, 3248 #endif /* chips */ 3249 3250 #if defined(BCM_56770_A0) 3251 { /* SOC_FORMAT_INT_EFP_KEY5_BCM56770_A0fmt */ 3252 /* format EFP_KEY5fmt */ 3253 /* nFields */ 33, 3254 /* *fields */ soc_EFP_KEY5_BCM56870_A0fmt_fields, 3255 /* bits */ 272, 3256 /* flags */ 0, 3257 }, 3258 #endif /* chips */ 3259 3260 #if defined(BCM_56860_A0) 3261 { /* SOC_FORMAT_INT_EFP_KEY5_BCM56860_A0fmt */ 3262 /* format EFP_KEY5fmt */ 3263 /* nFields */ 33, 3264 /* *fields */ soc_EFP_KEY5_BCM56860_A0fmt_fields, 3265 /* bits */ 234, 3266 /* flags */ 0, 3267 }, 3268 #endif /* chips */ 3269 3270 #if defined(BCM_56870_A0) 3271 { /* SOC_FORMAT_INT_EFP_KEY5_BCM56870_A0fmt */ 3272 /* format EFP_KEY5fmt */ 3273 /* nFields */ 33, 3274 /* *fields */ soc_EFP_KEY5_BCM56870_A0fmt_fields, 3275 /* bits */ 272, 3276 /* flags */ 0, 3277 }, 3278 #endif /* chips */ 3279 3280 #if defined(BCM_56370_A0) 3281 { /* SOC_FORMAT_INT_EFP_KEY6_BCM56370_A0fmt */ 3282 /* format EFP_KEY6fmt */ 3283 /* nFields */ 18, 3284 /* *fields */ soc_EFP_KEY6_BCM56870_A0fmt_fields, 3285 /* bits */ 272, 3286 /* flags */ 0, 3287 }, 3288 #endif /* chips */ 3289 3290 #if defined(BCM_56560_A0) 3291 { /* SOC_FORMAT_INT_EFP_KEY6_BCM56560_A0fmt */ 3292 /* format EFP_KEY6fmt */ 3293 /* nFields */ 35, 3294 /* *fields */ soc_EFP_KEY6_BCM56560_A0fmt_fields, 3295 /* bits */ 234, 3296 /* flags */ 0, 3297 }, 3298 #endif /* chips */ 3299 3300 #if defined(BCM_56560_B0) 3301 { /* SOC_FORMAT_INT_EFP_KEY6_BCM56560_B0fmt */ 3302 /* format EFP_KEY6fmt */ 3303 /* nFields */ 35, 3304 /* *fields */ soc_EFP_KEY6_BCM56560_A0fmt_fields, 3305 /* bits */ 234, 3306 /* flags */ 0, 3307 }, 3308 #endif /* chips */ 3309 3310 #if defined(BCM_56670_A0) 3311 { /* SOC_FORMAT_INT_EFP_KEY6_BCM56670_A0fmt */ 3312 /* format EFP_KEY6fmt */ 3313 /* nFields */ 35, 3314 /* *fields */ soc_EFP_KEY6_BCM56560_A0fmt_fields, 3315 /* bits */ 234, 3316 /* flags */ 0, 3317 }, 3318 #endif /* chips */ 3319 3320 #if defined(BCM_56670_B0) 3321 { /* SOC_FORMAT_INT_EFP_KEY6_BCM56670_B0fmt */ 3322 /* format EFP_KEY6fmt */ 3323 /* nFields */ 35, 3324 /* *fields */ soc_EFP_KEY6_BCM56560_A0fmt_fields, 3325 /* bits */ 234, 3326 /* flags */ 0, 3327 }, 3328 #endif /* chips */ 3329 3330 #if defined(BCM_56770_A0) 3331 { /* SOC_FORMAT_INT_EFP_KEY6_BCM56770_A0fmt */ 3332 /* format EFP_KEY6fmt */ 3333 /* nFields */ 18, 3334 /* *fields */ soc_EFP_KEY6_BCM56870_A0fmt_fields, 3335 /* bits */ 272, 3336 /* flags */ 0, 3337 }, 3338 #endif /* chips */ 3339 3340 #if defined(BCM_56870_A0) 3341 { /* SOC_FORMAT_INT_EFP_KEY6_BCM56870_A0fmt */ 3342 /* format EFP_KEY6fmt */ 3343 /* nFields */ 18, 3344 /* *fields */ soc_EFP_KEY6_BCM56870_A0fmt_fields, 3345 /* bits */ 272, 3346 /* flags */ 0, 3347 }, 3348 #endif /* chips */ 3349 3350 #if defined(BCM_56980_A0) 3351 { /* SOC_FORMAT_INT_EFP_KEY6_BCM56980_A0fmt */ 3352 /* format EFP_KEY6fmt */ 3353 /* nFields */ 14, 3354 /* *fields */ soc_EFP_KEY6_BCM56980_A0fmt_fields, 3355 /* bits */ 240, 3356 /* flags */ 0, 3357 }, 3358 #endif /* chips */ 3359 3360 #if defined(BCM_56980_B0) 3361 { /* SOC_FORMAT_INT_EFP_KEY6_BCM56980_B0fmt */ 3362 /* format EFP_KEY6fmt */ 3363 /* nFields */ 14, 3364 /* *fields */ soc_EFP_KEY6_BCM56980_A0fmt_fields, 3365 /* bits */ 240, 3366 /* flags */ 0, 3367 }, 3368 #endif /* chips */ 3369 3370 #if defined(BCM_56370_A0) 3371 { /* SOC_FORMAT_INT_EFP_KEY7_BCM56370_A0fmt */ 3372 /* format EFP_KEY7fmt */ 3373 /* nFields */ 19, 3374 /* *fields */ soc_EFP_KEY7_BCM56870_A0fmt_fields, 3375 /* bits */ 272, 3376 /* flags */ 0, 3377 }, 3378 #endif /* chips */ 3379 3380 #if defined(BCM_56770_A0) 3381 { /* SOC_FORMAT_INT_EFP_KEY7_BCM56770_A0fmt */ 3382 /* format EFP_KEY7fmt */ 3383 /* nFields */ 19, 3384 /* *fields */ soc_EFP_KEY7_BCM56870_A0fmt_fields, 3385 /* bits */ 272, 3386 /* flags */ 0, 3387 }, 3388 #endif /* chips */ 3389 3390 #if defined(BCM_56870_A0) 3391 { /* SOC_FORMAT_INT_EFP_KEY7_BCM56870_A0fmt */ 3392 /* format EFP_KEY7fmt */ 3393 /* nFields */ 19, 3394 /* *fields */ soc_EFP_KEY7_BCM56870_A0fmt_fields, 3395 /* bits */ 272, 3396 /* flags */ 0, 3397 }, 3398 #endif /* chips */ 3399 3400 #if defined(BCM_56980_A0) 3401 { /* SOC_FORMAT_INT_EFP_KEY7_BCM56980_A0fmt */ 3402 /* format EFP_KEY7fmt */ 3403 /* nFields */ 16, 3404 /* *fields */ soc_EFP_KEY7_BCM56980_A0fmt_fields, 3405 /* bits */ 240, 3406 /* flags */ 0, 3407 }, 3408 #endif /* chips */ 3409 3410 #if defined(BCM_56980_B0) 3411 { /* SOC_FORMAT_INT_EFP_KEY7_BCM56980_B0fmt */ 3412 /* format EFP_KEY7fmt */ 3413 /* nFields */ 16, 3414 /* *fields */ soc_EFP_KEY7_BCM56980_A0fmt_fields, 3415 /* bits */ 240, 3416 /* flags */ 0, 3417 }, 3418 #endif /* chips */ 3419 3420 #if defined(BCM_56370_A0) 3421 { /* SOC_FORMAT_INT_EFP_KEY8_BCM56370_A0fmt */ 3422 /* format EFP_KEY8fmt */ 3423 /* nFields */ 28, 3424 /* *fields */ soc_EFP_KEY8_BCM56870_A0fmt_fields, 3425 /* bits */ 272, 3426 /* flags */ 0, 3427 }, 3428 #endif /* chips */ 3429 3430 #if defined(BCM_56770_A0) 3431 { /* SOC_FORMAT_INT_EFP_KEY8_BCM56770_A0fmt */ 3432 /* format EFP_KEY8fmt */ 3433 /* nFields */ 28, 3434 /* *fields */ soc_EFP_KEY8_BCM56870_A0fmt_fields, 3435 /* bits */ 272, 3436 /* flags */ 0, 3437 }, 3438 #endif /* chips */ 3439 3440 #if defined(BCM_56870_A0) 3441 { /* SOC_FORMAT_INT_EFP_KEY8_BCM56870_A0fmt */ 3442 /* format EFP_KEY8fmt */ 3443 /* nFields */ 28, 3444 /* *fields */ soc_EFP_KEY8_BCM56870_A0fmt_fields, 3445 /* bits */ 272, 3446 /* flags */ 0, 3447 }, 3448 #endif /* chips */ 3449 3450 #if defined(BCM_56980_A0) 3451 { /* SOC_FORMAT_INT_EFP_KEY8_BCM56980_A0fmt */ 3452 /* format EFP_KEY8fmt */ 3453 /* nFields */ 24, 3454 /* *fields */ soc_EFP_KEY8_BCM56980_A0fmt_fields, 3455 /* bits */ 240, 3456 /* flags */ 0, 3457 }, 3458 #endif /* chips */ 3459 3460 #if defined(BCM_56980_B0) 3461 { /* SOC_FORMAT_INT_EFP_KEY8_BCM56980_B0fmt */ 3462 /* format EFP_KEY8fmt */ 3463 /* nFields */ 24, 3464 /* *fields */ soc_EFP_KEY8_BCM56980_A0fmt_fields, 3465 /* bits */ 240, 3466 /* flags */ 0, 3467 }, 3468 #endif /* chips */ 3469 3470 #if defined(BCM_56640_A0) 3471 { /* SOC_FORMAT_INT_EFP_ODD_METER_COV_DEFSfmt */ 3472 /* format EFP_ODD_METER_COV_DEFSfmt */ 3473 /* nFields */ 7, 3474 /* *fields */ soc_EFP_EVEN_METER_COV_DEFSfmt_fields, 3475 /* bits */ 16, 3476 /* flags */ 0, 3477 }, 3478 #endif /* chips */ 3479 3480 #if defined(BCM_53400_A0) 3481 { /* SOC_FORMAT_INT_EFP_ODD_METER_COV_DEFS_BCM53400_A0fmt */ 3482 /* format EFP_ODD_METER_COV_DEFSfmt */ 3483 /* nFields */ 7, 3484 /* *fields */ soc_EFP_EVEN_METER_COV_DEFS_BCM53400_A0fmt_fields, 3485 /* bits */ 13, 3486 /* flags */ 0, 3487 }, 3488 #endif /* chips */ 3489 3490 #if defined(BCM_53540_A0) 3491 { /* SOC_FORMAT_INT_EFP_ODD_METER_COV_DEFS_BCM53540_A0fmt */ 3492 /* format EFP_ODD_METER_COV_DEFSfmt */ 3493 /* nFields */ 7, 3494 /* *fields */ soc_EFP_EVEN_METER_COV_DEFS_BCM53400_A0fmt_fields, 3495 /* bits */ 13, 3496 /* flags */ 0, 3497 }, 3498 #endif /* chips */ 3499 3500 #if defined(BCM_53570_A0) 3501 { /* SOC_FORMAT_INT_EFP_ODD_METER_COV_DEFS_BCM53570_A0fmt */ 3502 /* format EFP_ODD_METER_COV_DEFSfmt */ 3503 /* nFields */ 7, 3504 /* *fields */ soc_EFP_EVEN_METER_COV_DEFS_BCM53400_A0fmt_fields, 3505 /* bits */ 13, 3506 /* flags */ 0, 3507 }, 3508 #endif /* chips */ 3509 3510 #if defined(BCM_53570_B0) 3511 { /* SOC_FORMAT_INT_EFP_ODD_METER_COV_DEFS_BCM53570_B0fmt */ 3512 /* format EFP_ODD_METER_COV_DEFSfmt */ 3513 /* nFields */ 7, 3514 /* *fields */ soc_EFP_EVEN_METER_COV_DEFS_BCM53400_A0fmt_fields, 3515 /* bits */ 13, 3516 /* flags */ 0, 3517 }, 3518 #endif /* chips */ 3519 3520 #if defined(BCM_56150_A0) 3521 { /* SOC_FORMAT_INT_EFP_ODD_METER_COV_DEFS_BCM56150_A0fmt */ 3522 /* format EFP_ODD_METER_COV_DEFSfmt */ 3523 /* nFields */ 7, 3524 /* *fields */ soc_EFP_EVEN_METER_COV_DEFS_BCM56150_A0fmt_fields, 3525 /* bits */ 13, 3526 /* flags */ 0, 3527 }, 3528 #endif /* chips */ 3529 3530 #if defined(BCM_56160_A0) 3531 { /* SOC_FORMAT_INT_EFP_ODD_METER_COV_DEFS_BCM56160_A0fmt */ 3532 /* format EFP_ODD_METER_COV_DEFSfmt */ 3533 /* nFields */ 7, 3534 /* *fields */ soc_EFP_EVEN_METER_COV_DEFS_BCM53400_A0fmt_fields, 3535 /* bits */ 13, 3536 /* flags */ 0, 3537 }, 3538 #endif /* chips */ 3539 3540 #if defined(BCM_56340_A0) 3541 { /* SOC_FORMAT_INT_EFP_ODD_METER_COV_DEFS_BCM56340_A0fmt */ 3542 /* format EFP_ODD_METER_COV_DEFSfmt */ 3543 /* nFields */ 7, 3544 /* *fields */ soc_EFP_EVEN_METER_COV_DEFSfmt_fields, 3545 /* bits */ 16, 3546 /* flags */ 0, 3547 }, 3548 #endif /* chips */ 3549 3550 #if defined(BCM_56370_A0) 3551 { /* SOC_FORMAT_INT_EFP_ODD_METER_COV_DEFS_BCM56370_A0fmt */ 3552 /* format EFP_ODD_METER_COV_DEFSfmt */ 3553 /* nFields */ 7, 3554 /* *fields */ soc_IFP_EVEN_METER_COV_DEFS_BCM53400_A0fmt_fields, 3555 /* bits */ 14, 3556 /* flags */ 0, 3557 }, 3558 #endif /* chips */ 3559 3560 #if defined(BCM_56560_A0) 3561 { /* SOC_FORMAT_INT_EFP_ODD_METER_COV_DEFS_BCM56560_A0fmt */ 3562 /* format EFP_ODD_METER_COV_DEFSfmt */ 3563 /* nFields */ 8, 3564 /* *fields */ soc_EFP_EVEN_METER_COV_DEFS_BCM56560_A0fmt_fields, 3565 /* bits */ 15, 3566 /* flags */ 0, 3567 }, 3568 #endif /* chips */ 3569 3570 #if defined(BCM_56560_B0) 3571 { /* SOC_FORMAT_INT_EFP_ODD_METER_COV_DEFS_BCM56560_B0fmt */ 3572 /* format EFP_ODD_METER_COV_DEFSfmt */ 3573 /* nFields */ 8, 3574 /* *fields */ soc_EFP_EVEN_METER_COV_DEFS_BCM56560_A0fmt_fields, 3575 /* bits */ 15, 3576 /* flags */ 0, 3577 }, 3578 #endif /* chips */ 3579 3580 #if defined(BCM_56670_A0) 3581 { /* SOC_FORMAT_INT_EFP_ODD_METER_COV_DEFS_BCM56670_A0fmt */ 3582 /* format EFP_ODD_METER_COV_DEFSfmt */ 3583 /* nFields */ 8, 3584 /* *fields */ soc_EFP_EVEN_METER_COV_DEFS_BCM56560_A0fmt_fields, 3585 /* bits */ 15, 3586 /* flags */ 0, 3587 }, 3588 #endif /* chips */ 3589 3590 #if defined(BCM_56670_B0) 3591 { /* SOC_FORMAT_INT_EFP_ODD_METER_COV_DEFS_BCM56670_B0fmt */ 3592 /* format EFP_ODD_METER_COV_DEFSfmt */ 3593 /* nFields */ 8, 3594 /* *fields */ soc_EFP_EVEN_METER_COV_DEFS_BCM56560_A0fmt_fields, 3595 /* bits */ 15, 3596 /* flags */ 0, 3597 }, 3598 #endif /* chips */ 3599 3600 #if defined(BCM_56770_A0) 3601 { /* SOC_FORMAT_INT_EFP_ODD_METER_COV_DEFS_BCM56770_A0fmt */ 3602 /* format EFP_ODD_METER_COV_DEFSfmt */ 3603 /* nFields */ 7, 3604 /* *fields */ soc_EFP_EVEN_METER_COV_DEFS_BCM56870_A0fmt_fields, 3605 /* bits */ 15, 3606 /* flags */ 0, 3607 }, 3608 #endif /* chips */ 3609 3610 #if defined(BCM_56850_A0) 3611 { /* SOC_FORMAT_INT_EFP_ODD_METER_COV_DEFS_BCM56850_A0fmt */ 3612 /* format EFP_ODD_METER_COV_DEFSfmt */ 3613 /* nFields */ 7, 3614 /* *fields */ soc_EFP_EVEN_METER_COV_DEFS_BCM56850_A0fmt_fields, 3615 /* bits */ 14, 3616 /* flags */ 0, 3617 }, 3618 #endif /* chips */ 3619 3620 #if defined(BCM_56860_A0) 3621 { /* SOC_FORMAT_INT_EFP_ODD_METER_COV_DEFS_BCM56860_A0fmt */ 3622 /* format EFP_ODD_METER_COV_DEFSfmt */ 3623 /* nFields */ 8, 3624 /* *fields */ soc_EFP_EVEN_METER_COV_DEFS_BCM56860_A0fmt_fields, 3625 /* bits */ 15, 3626 /* flags */ 0, 3627 }, 3628 #endif /* chips */ 3629 3630 #if defined(BCM_56870_A0) 3631 { /* SOC_FORMAT_INT_EFP_ODD_METER_COV_DEFS_BCM56870_A0fmt */ 3632 /* format EFP_ODD_METER_COV_DEFSfmt */ 3633 /* nFields */ 7, 3634 /* *fields */ soc_EFP_EVEN_METER_COV_DEFS_BCM56870_A0fmt_fields, 3635 /* bits */ 15, 3636 /* flags */ 0, 3637 }, 3638 #endif /* chips */ 3639 3640 #if defined(BCM_56960_A0) 3641 { /* SOC_FORMAT_INT_EFP_ODD_METER_COV_DEFS_BCM56960_A0fmt */ 3642 /* format EFP_ODD_METER_COV_DEFSfmt */ 3643 /* nFields */ 7, 3644 /* *fields */ soc_IFP_EVEN_METER_COV_DEFS_BCM53400_A0fmt_fields, 3645 /* bits */ 14, 3646 /* flags */ 0, 3647 }, 3648 #endif /* chips */ 3649 3650 #if defined(BCM_56965_A0) 3651 { /* SOC_FORMAT_INT_EFP_ODD_METER_COV_DEFS_BCM56965_A0fmt */ 3652 /* format EFP_ODD_METER_COV_DEFSfmt */ 3653 /* nFields */ 7, 3654 /* *fields */ soc_IFP_EVEN_METER_COV_DEFS_BCM53400_A0fmt_fields, 3655 /* bits */ 14, 3656 /* flags */ 0, 3657 }, 3658 #endif /* chips */ 3659 3660 #if defined(BCM_56970_A0) 3661 { /* SOC_FORMAT_INT_EFP_ODD_METER_COV_DEFS_BCM56970_A0fmt */ 3662 /* format EFP_ODD_METER_COV_DEFSfmt */ 3663 /* nFields */ 7, 3664 /* *fields */ soc_IFP_EVEN_METER_COV_DEFS_BCM53400_A0fmt_fields, 3665 /* bits */ 14, 3666 /* flags */ 0, 3667 }, 3668 #endif /* chips */ 3669 3670 #if defined(BCM_56980_A0) 3671 { /* SOC_FORMAT_INT_EFP_ODD_METER_COV_DEFS_BCM56980_A0fmt */ 3672 /* format EFP_ODD_METER_COV_DEFSfmt */ 3673 /* nFields */ 7, 3674 /* *fields */ soc_IFP_EVEN_METER_COV_DEFS_BCM53400_A0fmt_fields, 3675 /* bits */ 14, 3676 /* flags */ 0, 3677 }, 3678 #endif /* chips */ 3679 3680 #if defined(BCM_56980_B0) 3681 { /* SOC_FORMAT_INT_EFP_ODD_METER_COV_DEFS_BCM56980_B0fmt */ 3682 /* format EFP_ODD_METER_COV_DEFSfmt */ 3683 /* nFields */ 7, 3684 /* *fields */ soc_IFP_EVEN_METER_COV_DEFS_BCM53400_A0fmt_fields, 3685 /* bits */ 14, 3686 /* flags */ 0, 3687 }, 3688 #endif /* chips */ 3689 3690 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \ 3691 defined(BCM_56270_A0) 3692 { /* SOC_FORMAT_INT_EFP_PARITY_STATUS_BUSfmt */ 3693 /* format EFP_PARITY_STATUS_BUSfmt */ 3694 /* nFields */ 4, 3695 /* *fields */ soc_EFP_PARITY_STATUS_BUSfmt_fields, 3696 /* bits */ 9, 3697 /* flags */ 0, 3698 }, 3699 #endif /* chips */ 3700 3701 #if defined(BCM_56634_A0) || defined(BCM_56634_B0) 3702 { /* SOC_FORMAT_INT_EFP_REDIRECTION_BUSfmt */ 3703 /* format EFP_REDIRECTION_BUSfmt */ 3704 /* nFields */ 16, 3705 /* *fields */ soc_EFP_REDIRECTION_BUSfmt_fields, 3706 /* bits */ 48, 3707 /* flags */ 0, 3708 }, 3709 #endif /* chips */ 3710 3711 #if defined(BCM_56260_A0) 3712 { /* SOC_FORMAT_INT_EFP_REDIRECTION_BUS_BCM56260_A0fmt */ 3713 /* format EFP_REDIRECTION_BUSfmt */ 3714 /* nFields */ 16, 3715 /* *fields */ soc_EFP_REDIRECTION_BUS_BCM56260_A0fmt_fields, 3716 /* bits */ 48, 3717 /* flags */ 0, 3718 }, 3719 #endif /* chips */ 3720 3721 #if defined(BCM_56260_B0) 3722 { /* SOC_FORMAT_INT_EFP_REDIRECTION_BUS_BCM56260_B0fmt */ 3723 /* format EFP_REDIRECTION_BUSfmt */ 3724 /* nFields */ 16, 3725 /* *fields */ soc_EFP_REDIRECTION_BUS_BCM56260_A0fmt_fields, 3726 /* bits */ 48, 3727 /* flags */ 0, 3728 }, 3729 #endif /* chips */ 3730 3731 #if defined(BCM_56270_A0) 3732 { /* SOC_FORMAT_INT_EFP_REDIRECTION_BUS_BCM56270_A0fmt */ 3733 /* format EFP_REDIRECTION_BUSfmt */ 3734 /* nFields */ 16, 3735 /* *fields */ soc_EFP_REDIRECTION_BUS_BCM56260_A0fmt_fields, 3736 /* bits */ 48, 3737 /* flags */ 0, 3738 }, 3739 #endif /* chips */ 3740 3741 #if defined(BCM_56340_A0) 3742 { /* SOC_FORMAT_INT_EFP_REDIRECTION_BUS_BCM56340_A0fmt */ 3743 /* format EFP_REDIRECTION_BUSfmt */ 3744 /* nFields */ 16, 3745 /* *fields */ soc_EFP_REDIRECTION_BUS_BCM56640_A0fmt_fields, 3746 /* bits */ 48, 3747 /* flags */ 0, 3748 }, 3749 #endif /* chips */ 3750 3751 #if defined(BCM_56450_A0) 3752 { /* SOC_FORMAT_INT_EFP_REDIRECTION_BUS_BCM56450_A0fmt */ 3753 /* format EFP_REDIRECTION_BUSfmt */ 3754 /* nFields */ 16, 3755 /* *fields */ soc_EFP_REDIRECTION_BUS_BCM56640_A0fmt_fields, 3756 /* bits */ 48, 3757 /* flags */ 0, 3758 }, 3759 #endif /* chips */ 3760 3761 #if defined(BCM_56450_B0) 3762 { /* SOC_FORMAT_INT_EFP_REDIRECTION_BUS_BCM56450_B0fmt */ 3763 /* format EFP_REDIRECTION_BUSfmt */ 3764 /* nFields */ 16, 3765 /* *fields */ soc_EFP_REDIRECTION_BUS_BCM56640_A0fmt_fields, 3766 /* bits */ 48, 3767 /* flags */ 0, 3768 }, 3769 #endif /* chips */ 3770 3771 #if defined(BCM_56450_B1) 3772 { /* SOC_FORMAT_INT_EFP_REDIRECTION_BUS_BCM56450_B1fmt */ 3773 /* format EFP_REDIRECTION_BUSfmt */ 3774 /* nFields */ 16, 3775 /* *fields */ soc_EFP_REDIRECTION_BUS_BCM56640_A0fmt_fields, 3776 /* bits */ 48, 3777 /* flags */ 0, 3778 }, 3779 #endif /* chips */ 3780 3781 #if defined(BCM_56524_A0) 3782 { /* SOC_FORMAT_INT_EFP_REDIRECTION_BUS_BCM56524_A0fmt */ 3783 /* format EFP_REDIRECTION_BUSfmt */ 3784 /* nFields */ 16, 3785 /* *fields */ soc_EFP_REDIRECTION_BUSfmt_fields, 3786 /* bits */ 48, 3787 /* flags */ 0, 3788 }, 3789 #endif /* chips */ 3790 3791 #if defined(BCM_56524_B0) 3792 { /* SOC_FORMAT_INT_EFP_REDIRECTION_BUS_BCM56524_B0fmt */ 3793 /* format EFP_REDIRECTION_BUSfmt */ 3794 /* nFields */ 16, 3795 /* *fields */ soc_EFP_REDIRECTION_BUSfmt_fields, 3796 /* bits */ 48, 3797 /* flags */ 0, 3798 }, 3799 #endif /* chips */ 3800 3801 #if defined(BCM_56640_A0) 3802 { /* SOC_FORMAT_INT_EFP_REDIRECTION_BUS_BCM56640_A0fmt */ 3803 /* format EFP_REDIRECTION_BUSfmt */ 3804 /* nFields */ 16, 3805 /* *fields */ soc_EFP_REDIRECTION_BUS_BCM56640_A0fmt_fields, 3806 /* bits */ 48, 3807 /* flags */ 0, 3808 }, 3809 #endif /* chips */ 3810 3811 #if defined(BCM_56685_A0) 3812 { /* SOC_FORMAT_INT_EFP_REDIRECTION_BUS_BCM56685_A0fmt */ 3813 /* format EFP_REDIRECTION_BUSfmt */ 3814 /* nFields */ 16, 3815 /* *fields */ soc_EFP_REDIRECTION_BUSfmt_fields, 3816 /* bits */ 48, 3817 /* flags */ 0, 3818 }, 3819 #endif /* chips */ 3820 3821 #if defined(BCM_56685_B0) 3822 { /* SOC_FORMAT_INT_EFP_REDIRECTION_BUS_BCM56685_B0fmt */ 3823 /* format EFP_REDIRECTION_BUSfmt */ 3824 /* nFields */ 16, 3825 /* *fields */ soc_EFP_REDIRECTION_BUSfmt_fields, 3826 /* bits */ 48, 3827 /* flags */ 0, 3828 }, 3829 #endif /* chips */ 3830 3831 #if defined(BCM_88732_A0) 3832 { /* SOC_FORMAT_INT_EGRESS_ASSP_HEADERfmt */ 3833 /* format EGRESS_ASSP_HEADERfmt */ 3834 /* nFields */ 9, 3835 /* *fields */ soc_EGRESS_ASSP_HEADERfmt_fields, 3836 /* bits */ 128, 3837 /* flags */ 0, 3838 }, 3839 #endif /* chips */ 3840 3841 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 3842 defined(BCM_56870_A0) 3843 { /* SOC_FORMAT_INT_EGRESS_COMPUTED_FIELD_BUSfmt */ 3844 /* format EGRESS_COMPUTED_FIELD_BUSfmt */ 3845 /* nFields */ 1, 3846 /* *fields */ soc_EGRESS_COMPUTED_FIELD_BUSfmt_fields, 3847 /* bits */ 112, 3848 /* flags */ 0, 3849 }, 3850 #endif /* chips */ 3851 3852 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) 3853 { /* SOC_FORMAT_INT_EGRESS_DOP_TOP_FORMATfmt */ 3854 /* format EGRESS_DOP_TOP_FORMATfmt */ 3855 /* nFields */ 3, 3856 /* *fields */ soc_EGRESS_DOP_TOP_FORMATfmt_fields, 3857 /* bits */ 1344, 3858 /* flags */ 0, 3859 }, 3860 #endif /* chips */ 3861 3862 #if defined(BCM_56370_A0) 3863 { /* SOC_FORMAT_INT_EGRESS_DOP_TOP_FORMAT_BCM56370_A0fmt */ 3864 /* format EGRESS_DOP_TOP_FORMATfmt */ 3865 /* nFields */ 4, 3866 /* *fields */ soc_EGRESS_DOP_TOP_FORMAT_BCM56370_A0fmt_fields, 3867 /* bits */ 1364, 3868 /* flags */ 0, 3869 }, 3870 #endif /* chips */ 3871 3872 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 3873 defined(BCM_56870_A0) 3874 { /* SOC_FORMAT_INT_EGRESS_FIELD_BUSfmt */ 3875 /* format EGRESS_FIELD_BUSfmt */ 3876 /* nFields */ 28, 3877 /* *fields */ soc_EGRESS_FIELD_BUSfmt_fields, 3878 /* bits */ 896, 3879 /* flags */ 0, 3880 }, 3881 #endif /* chips */ 3882 3883 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 3884 defined(BCM_56870_A0) 3885 { /* SOC_FORMAT_INT_EGRESS_L2_TAG_BUSfmt */ 3886 /* format EGRESS_L2_TAG_BUSfmt */ 3887 /* nFields */ 9, 3888 /* *fields */ soc_EGRESS_L2_TAG_BUSfmt_fields, 3889 /* bits */ 160, 3890 /* flags */ 0, 3891 }, 3892 #endif /* chips */ 3893 3894 #if defined(BCM_56870_A0) 3895 { /* SOC_FORMAT_INT_EGRESS_OBJECT_BUSfmt */ 3896 /* format EGRESS_OBJECT_BUSfmt */ 3897 /* nFields */ 113, 3898 /* *fields */ soc_EGRESS_OBJECT_BUSfmt_fields, 3899 /* bits */ 944, 3900 /* flags */ 0, 3901 }, 3902 #endif /* chips */ 3903 3904 #if defined(BCM_56370_A0) 3905 { /* SOC_FORMAT_INT_EGRESS_OBJECT_BUS_BCM56370_A0fmt */ 3906 /* format EGRESS_OBJECT_BUSfmt */ 3907 /* nFields */ 114, 3908 /* *fields */ soc_EGRESS_OBJECT_BUS_BCM56370_A0fmt_fields, 3909 /* bits */ 944, 3910 /* flags */ 0, 3911 }, 3912 #endif /* chips */ 3913 3914 #if defined(BCM_56770_A0) 3915 { /* SOC_FORMAT_INT_EGRESS_OBJECT_BUS_BCM56770_A0fmt */ 3916 /* format EGRESS_OBJECT_BUSfmt */ 3917 /* nFields */ 114, 3918 /* *fields */ soc_EGRESS_OBJECT_BUS_BCM56770_A0fmt_fields, 3919 /* bits */ 944, 3920 /* flags */ 0, 3921 }, 3922 #endif /* chips */ 3923 3924 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 3925 defined(BCM_56870_A0) 3926 { /* SOC_FORMAT_INT_EGR_ADAPT_1_FIXED_KEY_TABLE_ATTRS_INDEXfmt */ 3927 /* format EGR_ADAPT_1_FIXED_KEY_TABLE_ATTRS_INDEXfmt */ 3928 /* nFields */ 3, 3929 /* *fields */ soc_EGR_ADAPT_1_FIXED_KEY_TABLE_ATTRS_INDEXfmt_fields, 3930 /* bits */ 9, 3931 /* flags */ 0, 3932 }, 3933 #endif /* chips */ 3934 3935 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 3936 defined(BCM_56870_A0) 3937 { /* SOC_FORMAT_INT_EGR_ADAPT_1_FLEX_KEY_GEN_IN_CONTROL_BUSfmt */ 3938 /* format EGR_ADAPT_1_FLEX_KEY_GEN_IN_CONTROL_BUSfmt */ 3939 /* nFields */ 18, 3940 /* *fields */ soc_EGR_ADAPT_1_FLEX_KEY_GEN_IN_CONTROL_BUSfmt_fields, 3941 /* bits */ 120, 3942 /* flags */ 0, 3943 }, 3944 #endif /* chips */ 3945 3946 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 3947 defined(BCM_56870_A0) 3948 { /* SOC_FORMAT_INT_EGR_ADAPT_1_FLEX_KEY_GEN_OUT_BUSfmt */ 3949 /* format EGR_ADAPT_1_FLEX_KEY_GEN_OUT_BUSfmt */ 3950 /* nFields */ 8, 3951 /* *fields */ soc_EGR_ADAPT_1_FLEX_KEY_GEN_OUT_BUSfmt_fields, 3952 /* bits */ 256, 3953 /* flags */ 0, 3954 }, 3955 #endif /* chips */ 3956 3957 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 3958 defined(BCM_56870_A0) 3959 { /* SOC_FORMAT_INT_EGR_ADAPT_1_PDD_OUT_BUSfmt */ 3960 /* format EGR_ADAPT_1_PDD_OUT_BUSfmt */ 3961 /* nFields */ 125, 3962 /* *fields */ soc_EGR_ADAPT_1_PDD_OUT_BUSfmt_fields, 3963 /* bits */ 1115, 3964 /* flags */ 0, 3965 }, 3966 #endif /* chips */ 3967 3968 #if defined(BCM_56870_A0) 3969 { /* SOC_FORMAT_INT_EGR_ADAPT_2_FLEX_KEY_GEN_IN_CONTROL_BUSfmt */ 3970 /* format EGR_ADAPT_2_FLEX_KEY_GEN_IN_CONTROL_BUSfmt */ 3971 /* nFields */ 18, 3972 /* *fields */ soc_EGR_ADAPT_1_FLEX_KEY_GEN_IN_CONTROL_BUSfmt_fields, 3973 /* bits */ 120, 3974 /* flags */ 0, 3975 }, 3976 #endif /* chips */ 3977 3978 #if defined(BCM_56370_A0) 3979 { /* SOC_FORMAT_INT_EGR_ADAPT_2_FLEX_KEY_GEN_IN_CONTROL_BUS_BCM56370_A0fmt */ 3980 /* format EGR_ADAPT_2_FLEX_KEY_GEN_IN_CONTROL_BUSfmt */ 3981 /* nFields */ 18, 3982 /* *fields */ soc_EGR_ADAPT_1_FLEX_KEY_GEN_IN_CONTROL_BUSfmt_fields, 3983 /* bits */ 120, 3984 /* flags */ 0, 3985 }, 3986 #endif /* chips */ 3987 3988 #if defined(BCM_56770_A0) 3989 { /* SOC_FORMAT_INT_EGR_ADAPT_2_FLEX_KEY_GEN_IN_CONTROL_BUS_BCM56770_A0fmt */ 3990 /* format EGR_ADAPT_2_FLEX_KEY_GEN_IN_CONTROL_BUSfmt */ 3991 /* nFields */ 18, 3992 /* *fields */ soc_EGR_ADAPT_1_FLEX_KEY_GEN_IN_CONTROL_BUSfmt_fields, 3993 /* bits */ 120, 3994 /* flags */ 0, 3995 }, 3996 #endif /* chips */ 3997 3998 #if defined(BCM_56870_A0) 3999 { /* SOC_FORMAT_INT_EGR_ADAPT_2_FLEX_KEY_GEN_OUT_BUSfmt */ 4000 /* format EGR_ADAPT_2_FLEX_KEY_GEN_OUT_BUSfmt */ 4001 /* nFields */ 8, 4002 /* *fields */ soc_EGR_ADAPT_1_FLEX_KEY_GEN_OUT_BUSfmt_fields, 4003 /* bits */ 256, 4004 /* flags */ 0, 4005 }, 4006 #endif /* chips */ 4007 4008 #if defined(BCM_56370_A0) 4009 { /* SOC_FORMAT_INT_EGR_ADAPT_2_FLEX_KEY_GEN_OUT_BUS_BCM56370_A0fmt */ 4010 /* format EGR_ADAPT_2_FLEX_KEY_GEN_OUT_BUSfmt */ 4011 /* nFields */ 8, 4012 /* *fields */ soc_EGR_ADAPT_1_FLEX_KEY_GEN_OUT_BUSfmt_fields, 4013 /* bits */ 256, 4014 /* flags */ 0, 4015 }, 4016 #endif /* chips */ 4017 4018 #if defined(BCM_56770_A0) 4019 { /* SOC_FORMAT_INT_EGR_ADAPT_2_FLEX_KEY_GEN_OUT_BUS_BCM56770_A0fmt */ 4020 /* format EGR_ADAPT_2_FLEX_KEY_GEN_OUT_BUSfmt */ 4021 /* nFields */ 8, 4022 /* *fields */ soc_EGR_ADAPT_1_FLEX_KEY_GEN_OUT_BUSfmt_fields, 4023 /* bits */ 256, 4024 /* flags */ 0, 4025 }, 4026 #endif /* chips */ 4027 4028 #if defined(BCM_56870_A0) 4029 { /* SOC_FORMAT_INT_EGR_ADAPT_2_PDD_OUT_BUSfmt */ 4030 /* format EGR_ADAPT_2_PDD_OUT_BUSfmt */ 4031 /* nFields */ 125, 4032 /* *fields */ soc_EGR_ADAPT_1_PDD_OUT_BUSfmt_fields, 4033 /* bits */ 1115, 4034 /* flags */ 0, 4035 }, 4036 #endif /* chips */ 4037 4038 #if defined(BCM_56370_A0) 4039 { /* SOC_FORMAT_INT_EGR_ADAPT_2_PDD_OUT_BUS_BCM56370_A0fmt */ 4040 /* format EGR_ADAPT_2_PDD_OUT_BUSfmt */ 4041 /* nFields */ 125, 4042 /* *fields */ soc_EGR_ADAPT_1_PDD_OUT_BUSfmt_fields, 4043 /* bits */ 1115, 4044 /* flags */ 0, 4045 }, 4046 #endif /* chips */ 4047 4048 #if defined(BCM_56770_A0) 4049 { /* SOC_FORMAT_INT_EGR_ADAPT_2_PDD_OUT_BUS_BCM56770_A0fmt */ 4050 /* format EGR_ADAPT_2_PDD_OUT_BUSfmt */ 4051 /* nFields */ 125, 4052 /* *fields */ soc_EGR_ADAPT_1_PDD_OUT_BUSfmt_fields, 4053 /* bits */ 1115, 4054 /* flags */ 0, 4055 }, 4056 #endif /* chips */ 4057 4058 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 4059 defined(BCM_56870_A0) 4060 { /* SOC_FORMAT_INT_EGR_ADAPT_FLEX_KEY_GEN_IN_BUSfmt */ 4061 /* format EGR_ADAPT_FLEX_KEY_GEN_IN_BUSfmt */ 4062 /* nFields */ 7, 4063 /* *fields */ soc_EGR_ADAPT_FLEX_KEY_GEN_IN_BUSfmt_fields, 4064 /* bits */ 1936, 4065 /* flags */ 0, 4066 }, 4067 #endif /* chips */ 4068 4069 #if defined(BCM_56870_A0) 4070 { /* SOC_FORMAT_INT_EGR_ADAPT_KEYGEN_OBJECT_BUSfmt */ 4071 /* format EGR_ADAPT_KEYGEN_OBJECT_BUSfmt */ 4072 /* nFields */ 112, 4073 /* *fields */ soc_EGR_ADAPT_KEYGEN_OBJECT_BUSfmt_fields, 4074 /* bits */ 864, 4075 /* flags */ 0, 4076 }, 4077 #endif /* chips */ 4078 4079 #if defined(BCM_56370_A0) 4080 { /* SOC_FORMAT_INT_EGR_ADAPT_KEYGEN_OBJECT_BUS_BCM56370_A0fmt */ 4081 /* format EGR_ADAPT_KEYGEN_OBJECT_BUSfmt */ 4082 /* nFields */ 113, 4083 /* *fields */ soc_EGR_ADAPT_KEYGEN_OBJECT_BUS_BCM56370_A0fmt_fields, 4084 /* bits */ 864, 4085 /* flags */ 0, 4086 }, 4087 #endif /* chips */ 4088 4089 #if defined(BCM_56770_A0) 4090 { /* SOC_FORMAT_INT_EGR_ADAPT_KEYGEN_OBJECT_BUS_BCM56770_A0fmt */ 4091 /* format EGR_ADAPT_KEYGEN_OBJECT_BUSfmt */ 4092 /* nFields */ 113, 4093 /* *fields */ soc_EGR_ADAPT_KEYGEN_OBJECT_BUS_BCM56770_A0fmt_fields, 4094 /* bits */ 864, 4095 /* flags */ 0, 4096 }, 4097 #endif /* chips */ 4098 4099 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 4100 defined(BCM_56870_A0) 4101 { /* SOC_FORMAT_INT_EGR_ADAPT_ZONE_L2_TAGS_STATUSfmt */ 4102 /* format EGR_ADAPT_ZONE_L2_TAGS_STATUSfmt */ 4103 /* nFields */ 4, 4104 /* *fields */ soc_EGR_ADAPT_ZONE_L2_TAGS_STATUSfmt_fields, 4105 /* bits */ 4, 4106 /* flags */ 0, 4107 }, 4108 #endif /* chips */ 4109 4110 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 4111 defined(BCM_56870_A0) 4112 { /* SOC_FORMAT_INT_EGR_ADAPT_ZONE_L2_TAGS_VALUESfmt */ 4113 /* format EGR_ADAPT_ZONE_L2_TAGS_VALUESfmt */ 4114 /* nFields */ 4, 4115 /* *fields */ soc_EGR_ADAPT_ZONE_L2_TAGS_VALUESfmt_fields, 4116 /* bits */ 80, 4117 /* flags */ 0, 4118 }, 4119 #endif /* chips */ 4120 4121 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 4122 defined(BCM_56870_A0) 4123 { /* SOC_FORMAT_INT_EGR_DELETE_CONTROL_INDEXfmt */ 4124 /* format EGR_DELETE_CONTROL_INDEXfmt */ 4125 /* nFields */ 6, 4126 /* *fields */ soc_EGR_DELETE_CONTROL_INDEXfmt_fields, 4127 /* bits */ 10, 4128 /* flags */ 0, 4129 }, 4130 #endif /* chips */ 4131 4132 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 4133 defined(BCM_56870_A0) 4134 { /* SOC_FORMAT_INT_EGR_DROP_STATUS_VECTORfmt */ 4135 /* format EGR_DROP_STATUS_VECTORfmt */ 4136 /* nFields */ 2, 4137 /* *fields */ soc_EGR_DROP_STATUS_VECTORfmt_fields, 4138 /* bits */ 55, 4139 /* flags */ 0, 4140 }, 4141 #endif /* chips */ 4142 4143 #if defined(BCM_56370_A0) 4144 { /* SOC_FORMAT_INT_EGR_DVP_ATTRIBUTE_EARLY_PDD_OUT_BUSfmt */ 4145 /* format EGR_DVP_ATTRIBUTE_EARLY_PDD_OUT_BUSfmt */ 4146 /* nFields */ 85, 4147 /* *fields */ soc_EGR_DVP_ATTRIBUTE_EARLY_PDD_OUT_BUSfmt_fields, 4148 /* bits */ 15, 4149 /* flags */ 0, 4150 }, 4151 #endif /* chips */ 4152 4153 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 4154 defined(BCM_56870_A0) 4155 { /* SOC_FORMAT_INT_EGR_DVP_ATTRIBUTE_PDD_OUT_BUSfmt */ 4156 /* format EGR_DVP_ATTRIBUTE_PDD_OUT_BUSfmt */ 4157 /* nFields */ 156, 4158 /* *fields */ soc_EGR_DVP_ATTRIBUTE_PDD_OUT_BUSfmt_fields, 4159 /* bits */ 1632, 4160 /* flags */ 0, 4161 }, 4162 #endif /* chips */ 4163 4164 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \ 4165 defined(BCM_56450_B1) 4166 { /* SOC_FORMAT_INT_EGR_EDB_PRE_BUSfmt */ 4167 /* format EGR_EDB_PRE_BUSfmt */ 4168 /* nFields */ 5, 4169 /* *fields */ soc_EGR_EDB_PRE_BUSfmt_fields, 4170 /* bits */ 25, 4171 /* flags */ 0, 4172 }, 4173 #endif /* chips */ 4174 4175 #if defined(BCM_56260_A0) 4176 { /* SOC_FORMAT_INT_EGR_EDB_PRE_BUS_BCM56260_A0fmt */ 4177 /* format EGR_EDB_PRE_BUSfmt */ 4178 /* nFields */ 6, 4179 /* *fields */ soc_EGR_EDB_PRE_BUS_BCM56260_A0fmt_fields, 4180 /* bits */ 25, 4181 /* flags */ 0, 4182 }, 4183 #endif /* chips */ 4184 4185 #if defined(BCM_56260_B0) 4186 { /* SOC_FORMAT_INT_EGR_EDB_PRE_BUS_BCM56260_B0fmt */ 4187 /* format EGR_EDB_PRE_BUSfmt */ 4188 /* nFields */ 6, 4189 /* *fields */ soc_EGR_EDB_PRE_BUS_BCM56260_A0fmt_fields, 4190 /* bits */ 25, 4191 /* flags */ 0, 4192 }, 4193 #endif /* chips */ 4194 4195 #if defined(BCM_56270_A0) 4196 { /* SOC_FORMAT_INT_EGR_EDB_PRE_BUS_BCM56270_A0fmt */ 4197 /* format EGR_EDB_PRE_BUSfmt */ 4198 /* nFields */ 6, 4199 /* *fields */ soc_EGR_EDB_PRE_BUS_BCM56270_A0fmt_fields, 4200 /* bits */ 25, 4201 /* flags */ 0, 4202 }, 4203 #endif /* chips */ 4204 4205 #if defined(BCM_56270_A0) 4206 { /* SOC_FORMAT_INT_EGR_EFPMOD_MCPE_CNTXT_BUFFERfmt */ 4207 /* format EGR_EFPMOD_MCPE_CNTXT_BUFFERfmt */ 4208 /* nFields */ 6, 4209 /* *fields */ soc_EGR_EFPMOD_MCPE_CNTXT_BUFFERfmt_fields, 4210 /* bits */ 84, 4211 /* flags */ 0, 4212 }, 4213 #endif /* chips */ 4214 4215 #if defined(BCM_56270_A0) 4216 { /* SOC_FORMAT_INT_EGR_EFPMOD_MCPE_EDIT_REQfmt */ 4217 /* format EGR_EFPMOD_MCPE_EDIT_REQfmt */ 4218 /* nFields */ 5, 4219 /* *fields */ soc_EGR_EFPMOD_MCPE_EDIT_REQfmt_fields, 4220 /* bits */ 90, 4221 /* flags */ 0, 4222 }, 4223 #endif /* chips */ 4224 4225 #if defined(BCM_56270_A0) 4226 { /* SOC_FORMAT_INT_EGR_EFPMOD_MCPE_IN_BUSfmt */ 4227 /* format EGR_EFPMOD_MCPE_IN_BUSfmt */ 4228 /* nFields */ 4, 4229 /* *fields */ soc_EGR_EFPMOD_MCPE_IN_BUSfmt_fields, 4230 /* bits */ 187, 4231 /* flags */ 0, 4232 }, 4233 #endif /* chips */ 4234 4235 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 4236 defined(BCM_56870_A0) 4237 { /* SOC_FORMAT_INT_EGR_EL3_MPLS_LABEL_SRC_FORMATfmt */ 4238 /* format EGR_EL3_MPLS_LABEL_SRC_FORMATfmt */ 4239 /* nFields */ 1, 4240 /* *fields */ soc_EGR_EL3_MPLS_LABEL_SRC_FORMATfmt_fields, 4241 /* bits */ 5, 4242 /* flags */ 0, 4243 }, 4244 #endif /* chips */ 4245 4246 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 4247 defined(BCM_56870_A0) 4248 { /* SOC_FORMAT_INT_EGR_EL3_TBL_IDfmt */ 4249 /* format EGR_EL3_TBL_IDfmt */ 4250 /* nFields */ 1, 4251 /* *fields */ soc_EGR_EL3_TBL_IDfmt_fields, 4252 /* bits */ 4, 4253 /* flags */ 0, 4254 }, 4255 #endif /* chips */ 4256 4257 #if defined(BCM_56970_A0) || defined(BCM_56980_A0) || \ 4258 defined(BCM_56980_B0) 4259 { /* SOC_FORMAT_INT_EGR_EPMOD_EMOP_BUFFERfmt */ 4260 /* format EGR_EPMOD_EMOP_BUFFERfmt */ 4261 /* nFields */ 7, 4262 /* *fields */ soc_EGR_EPMOD_EMOP_BUFFERfmt_fields, 4263 /* bits */ 45, 4264 /* flags */ 0, 4265 }, 4266 #endif /* chips */ 4267 4268 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 4269 defined(BCM_56870_A0) 4270 { /* SOC_FORMAT_INT_EGR_EVLAN_DEST_ATTRfmt */ 4271 /* format EGR_EVLAN_DEST_ATTRfmt */ 4272 /* nFields */ 19, 4273 /* *fields */ soc_EGR_EVLAN_DEST_ATTRfmt_fields, 4274 /* bits */ 77, 4275 /* flags */ 0, 4276 }, 4277 #endif /* chips */ 4278 4279 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 4280 defined(BCM_56870_A0) 4281 { /* SOC_FORMAT_INT_EGR_EVLAN_FCOE_ATTRfmt */ 4282 /* format EGR_EVLAN_FCOE_ATTRfmt */ 4283 /* nFields */ 9, 4284 /* *fields */ soc_EGR_EVLAN_FCOE_ATTRfmt_fields, 4285 /* bits */ 57, 4286 /* flags */ 0, 4287 }, 4288 #endif /* chips */ 4289 4290 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 4291 defined(BCM_56870_A0) 4292 { /* SOC_FORMAT_INT_EGR_EVLAN_FWD_DOMAIN_ATTRfmt */ 4293 /* format EGR_EVLAN_FWD_DOMAIN_ATTRfmt */ 4294 /* nFields */ 13, 4295 /* *fields */ soc_EGR_EVLAN_FWD_DOMAIN_ATTRfmt_fields, 4296 /* bits */ 246, 4297 /* flags */ 0, 4298 }, 4299 #endif /* chips */ 4300 4301 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 4302 defined(BCM_56870_A0) 4303 { /* SOC_FORMAT_INT_EGR_EVLAN_QOS_ATTRfmt */ 4304 /* format EGR_EVLAN_QOS_ATTRfmt */ 4305 /* nFields */ 6, 4306 /* *fields */ soc_EGR_EVLAN_QOS_ATTRfmt_fields, 4307 /* bits */ 15, 4308 /* flags */ 0, 4309 }, 4310 #endif /* chips */ 4311 4312 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 4313 defined(BCM_56870_A0) 4314 { /* SOC_FORMAT_INT_EGR_EVLAN_SRC_ATTRfmt */ 4315 /* format EGR_EVLAN_SRC_ATTRfmt */ 4316 /* nFields */ 2, 4317 /* *fields */ soc_EGR_EVLAN_SRC_ATTRfmt_fields, 4318 /* bits */ 19, 4319 /* flags */ 0, 4320 }, 4321 #endif /* chips */ 4322 4323 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 4324 defined(BCM_56870_A0) 4325 { /* SOC_FORMAT_INT_EGR_EVLAN_STAGE_ATTRfmt */ 4326 /* format EGR_EVLAN_STAGE_ATTRfmt */ 4327 /* nFields */ 8, 4328 /* *fields */ soc_EGR_EVLAN_STAGE_ATTRfmt_fields, 4329 /* bits */ 2556, 4330 /* flags */ 0, 4331 }, 4332 #endif /* chips */ 4333 4334 #if defined(BCM_56870_A0) 4335 { /* SOC_FORMAT_INT_EGR_EVLAN_TBL_IDfmt */ 4336 /* format EGR_EVLAN_TBL_IDfmt */ 4337 /* nFields */ 1, 4338 /* *fields */ soc_EGR_EL3_TBL_IDfmt_fields, 4339 /* bits */ 4, 4340 /* flags */ 0, 4341 }, 4342 #endif /* chips */ 4343 4344 #if defined(BCM_56370_A0) 4345 { /* SOC_FORMAT_INT_EGR_EVLAN_TBL_ID_BCM56370_A0fmt */ 4346 /* format EGR_EVLAN_TBL_IDfmt */ 4347 /* nFields */ 1, 4348 /* *fields */ soc_EGR_EL3_TBL_IDfmt_fields, 4349 /* bits */ 4, 4350 /* flags */ 0, 4351 }, 4352 #endif /* chips */ 4353 4354 #if defined(BCM_56770_A0) 4355 { /* SOC_FORMAT_INT_EGR_EVLAN_TBL_ID_BCM56770_A0fmt */ 4356 /* format EGR_EVLAN_TBL_IDfmt */ 4357 /* nFields */ 1, 4358 /* *fields */ soc_EGR_EL3_TBL_IDfmt_fields, 4359 /* bits */ 4, 4360 /* flags */ 0, 4361 }, 4362 #endif /* chips */ 4363 4364 #if defined(BCM_56850_A0) || defined(BCM_56860_A0) 4365 { /* SOC_FORMAT_INT_EGR_FCOE_DELIMITER_ERROR_FRAMES_TABLE_COV_DEFSfmt */ 4366 /* format EGR_FCOE_DELIMITER_ERROR_FRAMES_TABLE_COV_DEFSfmt */ 4367 /* nFields */ 6, 4368 /* *fields */ soc_EGR_FCOE_DELIMITER_ERROR_FRAMES_TABLE_COV_DEFSfmt_fields, 4369 /* bits */ 13, 4370 /* flags */ 0, 4371 }, 4372 #endif /* chips */ 4373 4374 #if defined(BCM_56560_A0) 4375 { /* SOC_FORMAT_INT_EGR_FCOE_DELIMITER_ERROR_FRAMES_TABLE_COV_DEFS_BCM56560_A0fmt */ 4376 /* format EGR_FCOE_DELIMITER_ERROR_FRAMES_TABLE_COV_DEFSfmt */ 4377 /* nFields */ 6, 4378 /* *fields */ soc_EGR_FCOE_DELIMITER_ERROR_FRAMES_TABLE_COV_DEFS_BCM56960_A0fmt_fields, 4379 /* bits */ 13, 4380 /* flags */ 0, 4381 }, 4382 #endif /* chips */ 4383 4384 #if defined(BCM_56560_B0) 4385 { /* SOC_FORMAT_INT_EGR_FCOE_DELIMITER_ERROR_FRAMES_TABLE_COV_DEFS_BCM56560_B0fmt */ 4386 /* format EGR_FCOE_DELIMITER_ERROR_FRAMES_TABLE_COV_DEFSfmt */ 4387 /* nFields */ 6, 4388 /* *fields */ soc_EGR_FCOE_DELIMITER_ERROR_FRAMES_TABLE_COV_DEFS_BCM56960_A0fmt_fields, 4389 /* bits */ 13, 4390 /* flags */ 0, 4391 }, 4392 #endif /* chips */ 4393 4394 #if defined(BCM_56670_A0) 4395 { /* SOC_FORMAT_INT_EGR_FCOE_DELIMITER_ERROR_FRAMES_TABLE_COV_DEFS_BCM56670_A0fmt */ 4396 /* format EGR_FCOE_DELIMITER_ERROR_FRAMES_TABLE_COV_DEFSfmt */ 4397 /* nFields */ 6, 4398 /* *fields */ soc_EGR_FCOE_DELIMITER_ERROR_FRAMES_TABLE_COV_DEFS_BCM56960_A0fmt_fields, 4399 /* bits */ 13, 4400 /* flags */ 0, 4401 }, 4402 #endif /* chips */ 4403 4404 #if defined(BCM_56670_B0) 4405 { /* SOC_FORMAT_INT_EGR_FCOE_DELIMITER_ERROR_FRAMES_TABLE_COV_DEFS_BCM56670_B0fmt */ 4406 /* format EGR_FCOE_DELIMITER_ERROR_FRAMES_TABLE_COV_DEFSfmt */ 4407 /* nFields */ 6, 4408 /* *fields */ soc_EGR_FCOE_DELIMITER_ERROR_FRAMES_TABLE_COV_DEFS_BCM56960_A0fmt_fields, 4409 /* bits */ 13, 4410 /* flags */ 0, 4411 }, 4412 #endif /* chips */ 4413 4414 #if defined(BCM_56960_A0) 4415 { /* SOC_FORMAT_INT_EGR_FCOE_DELIMITER_ERROR_FRAMES_TABLE_COV_DEFS_BCM56960_A0fmt */ 4416 /* format EGR_FCOE_DELIMITER_ERROR_FRAMES_TABLE_COV_DEFSfmt */ 4417 /* nFields */ 6, 4418 /* *fields */ soc_EGR_FCOE_DELIMITER_ERROR_FRAMES_TABLE_COV_DEFS_BCM56960_A0fmt_fields, 4419 /* bits */ 13, 4420 /* flags */ 0, 4421 }, 4422 #endif /* chips */ 4423 4424 #if defined(BCM_56965_A0) 4425 { /* SOC_FORMAT_INT_EGR_FCOE_DELIMITER_ERROR_FRAMES_TABLE_COV_DEFS_BCM56965_A0fmt */ 4426 /* format EGR_FCOE_DELIMITER_ERROR_FRAMES_TABLE_COV_DEFSfmt */ 4427 /* nFields */ 6, 4428 /* *fields */ soc_EGR_FCOE_DELIMITER_ERROR_FRAMES_TABLE_COV_DEFS_BCM56960_A0fmt_fields, 4429 /* bits */ 13, 4430 /* flags */ 0, 4431 }, 4432 #endif /* chips */ 4433 4434 #if defined(BCM_56870_A0) 4435 { /* SOC_FORMAT_INT_EGR_FCOE_FRAMES_COUNTER_COV_DEFSfmt */ 4436 /* format EGR_FCOE_FRAMES_COUNTER_COV_DEFSfmt */ 4437 /* nFields */ 6, 4438 /* *fields */ soc_EGR_FCOE_DELIMITER_ERROR_FRAMES_TABLE_COV_DEFS_BCM56960_A0fmt_fields, 4439 /* bits */ 13, 4440 /* flags */ 0, 4441 }, 4442 #endif /* chips */ 4443 4444 #if defined(BCM_56370_A0) 4445 { /* SOC_FORMAT_INT_EGR_FCOE_FRAMES_COUNTER_COV_DEFS_BCM56370_A0fmt */ 4446 /* format EGR_FCOE_FRAMES_COUNTER_COV_DEFSfmt */ 4447 /* nFields */ 6, 4448 /* *fields */ soc_EGR_FCOE_DELIMITER_ERROR_FRAMES_TABLE_COV_DEFS_BCM56960_A0fmt_fields, 4449 /* bits */ 13, 4450 /* flags */ 0, 4451 }, 4452 #endif /* chips */ 4453 4454 #if defined(BCM_56770_A0) 4455 { /* SOC_FORMAT_INT_EGR_FCOE_FRAMES_COUNTER_COV_DEFS_BCM56770_A0fmt */ 4456 /* format EGR_FCOE_FRAMES_COUNTER_COV_DEFSfmt */ 4457 /* nFields */ 6, 4458 /* *fields */ soc_EGR_FCOE_DELIMITER_ERROR_FRAMES_TABLE_COV_DEFS_BCM56960_A0fmt_fields, 4459 /* bits */ 13, 4460 /* flags */ 0, 4461 }, 4462 #endif /* chips */ 4463 4464 #if defined(BCM_56850_A0) 4465 { /* SOC_FORMAT_INT_EGR_FCOE_INVALID_CRC_FRAMES_TABLE_COV_DEFSfmt */ 4466 /* format EGR_FCOE_INVALID_CRC_FRAMES_TABLE_COV_DEFSfmt */ 4467 /* nFields */ 6, 4468 /* *fields */ soc_EGR_FCOE_DELIMITER_ERROR_FRAMES_TABLE_COV_DEFSfmt_fields, 4469 /* bits */ 13, 4470 /* flags */ 0, 4471 }, 4472 #endif /* chips */ 4473 4474 #if defined(BCM_56560_A0) 4475 { /* SOC_FORMAT_INT_EGR_FCOE_INVALID_CRC_FRAMES_TABLE_COV_DEFS_BCM56560_A0fmt */ 4476 /* format EGR_FCOE_INVALID_CRC_FRAMES_TABLE_COV_DEFSfmt */ 4477 /* nFields */ 6, 4478 /* *fields */ soc_EGR_FCOE_DELIMITER_ERROR_FRAMES_TABLE_COV_DEFS_BCM56960_A0fmt_fields, 4479 /* bits */ 13, 4480 /* flags */ 0, 4481 }, 4482 #endif /* chips */ 4483 4484 #if defined(BCM_56560_B0) 4485 { /* SOC_FORMAT_INT_EGR_FCOE_INVALID_CRC_FRAMES_TABLE_COV_DEFS_BCM56560_B0fmt */ 4486 /* format EGR_FCOE_INVALID_CRC_FRAMES_TABLE_COV_DEFSfmt */ 4487 /* nFields */ 6, 4488 /* *fields */ soc_EGR_FCOE_DELIMITER_ERROR_FRAMES_TABLE_COV_DEFS_BCM56960_A0fmt_fields, 4489 /* bits */ 13, 4490 /* flags */ 0, 4491 }, 4492 #endif /* chips */ 4493 4494 #if defined(BCM_56670_A0) 4495 { /* SOC_FORMAT_INT_EGR_FCOE_INVALID_CRC_FRAMES_TABLE_COV_DEFS_BCM56670_A0fmt */ 4496 /* format EGR_FCOE_INVALID_CRC_FRAMES_TABLE_COV_DEFSfmt */ 4497 /* nFields */ 6, 4498 /* *fields */ soc_EGR_FCOE_DELIMITER_ERROR_FRAMES_TABLE_COV_DEFS_BCM56960_A0fmt_fields, 4499 /* bits */ 13, 4500 /* flags */ 0, 4501 }, 4502 #endif /* chips */ 4503 4504 #if defined(BCM_56670_B0) 4505 { /* SOC_FORMAT_INT_EGR_FCOE_INVALID_CRC_FRAMES_TABLE_COV_DEFS_BCM56670_B0fmt */ 4506 /* format EGR_FCOE_INVALID_CRC_FRAMES_TABLE_COV_DEFSfmt */ 4507 /* nFields */ 6, 4508 /* *fields */ soc_EGR_FCOE_DELIMITER_ERROR_FRAMES_TABLE_COV_DEFS_BCM56960_A0fmt_fields, 4509 /* bits */ 13, 4510 /* flags */ 0, 4511 }, 4512 #endif /* chips */ 4513 4514 #if defined(BCM_56860_A0) 4515 { /* SOC_FORMAT_INT_EGR_FCOE_INVALID_CRC_FRAMES_TABLE_COV_DEFS_BCM56860_A0fmt */ 4516 /* format EGR_FCOE_INVALID_CRC_FRAMES_TABLE_COV_DEFSfmt */ 4517 /* nFields */ 6, 4518 /* *fields */ soc_EGR_FCOE_DELIMITER_ERROR_FRAMES_TABLE_COV_DEFSfmt_fields, 4519 /* bits */ 13, 4520 /* flags */ 0, 4521 }, 4522 #endif /* chips */ 4523 4524 #if defined(BCM_56960_A0) 4525 { /* SOC_FORMAT_INT_EGR_FCOE_INVALID_CRC_FRAMES_TABLE_COV_DEFS_BCM56960_A0fmt */ 4526 /* format EGR_FCOE_INVALID_CRC_FRAMES_TABLE_COV_DEFSfmt */ 4527 /* nFields */ 6, 4528 /* *fields */ soc_EGR_FCOE_DELIMITER_ERROR_FRAMES_TABLE_COV_DEFS_BCM56960_A0fmt_fields, 4529 /* bits */ 13, 4530 /* flags */ 0, 4531 }, 4532 #endif /* chips */ 4533 4534 #if defined(BCM_56965_A0) 4535 { /* SOC_FORMAT_INT_EGR_FCOE_INVALID_CRC_FRAMES_TABLE_COV_DEFS_BCM56965_A0fmt */ 4536 /* format EGR_FCOE_INVALID_CRC_FRAMES_TABLE_COV_DEFSfmt */ 4537 /* nFields */ 6, 4538 /* *fields */ soc_EGR_FCOE_DELIMITER_ERROR_FRAMES_TABLE_COV_DEFS_BCM56960_A0fmt_fields, 4539 /* bits */ 13, 4540 /* flags */ 0, 4541 }, 4542 #endif /* chips */ 4543 4544 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 4545 defined(BCM_56870_A0) 4546 { /* SOC_FORMAT_INT_EGR_FIELD_EXTRACTION_PROFILE_CONTROL_IDXfmt */ 4547 /* format EGR_FIELD_EXTRACTION_PROFILE_CONTROL_IDXfmt */ 4548 /* nFields */ 3, 4549 /* *fields */ soc_EGR_FIELD_EXTRACTION_PROFILE_CONTROL_IDXfmt_fields, 4550 /* bits */ 5, 4551 /* flags */ 0, 4552 }, 4553 #endif /* chips */ 4554 4555 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 4556 defined(BCM_56870_A0) 4557 { /* SOC_FORMAT_INT_EGR_FLEX_CONTAINER_UPDATE_PROFILE_INDEXfmt */ 4558 /* format EGR_FLEX_CONTAINER_UPDATE_PROFILE_INDEXfmt */ 4559 /* nFields */ 3, 4560 /* *fields */ soc_EGR_FLEX_CONTAINER_UPDATE_PROFILE_INDEXfmt_fields, 4561 /* bits */ 6, 4562 /* flags */ 0, 4563 }, 4564 #endif /* chips */ 4565 4566 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) 4567 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_ACTION_SETfmt */ 4568 /* format EGR_FLEX_CTR_ACTION_SETfmt */ 4569 /* nFields */ 5, 4570 /* *fields */ soc_EGR_FLEX_CTR_ACTION_SETfmt_fields, 4571 /* bits */ 19, 4572 /* flags */ 0, 4573 }, 4574 #endif /* chips */ 4575 4576 #if defined(BCM_56370_A0) 4577 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_ACTION_SET_BCM56370_A0fmt */ 4578 /* format EGR_FLEX_CTR_ACTION_SETfmt */ 4579 /* nFields */ 5, 4580 /* *fields */ soc_EGR_FLEX_CTR_ACTION_SET_BCM56370_A0fmt_fields, 4581 /* bits */ 19, 4582 /* flags */ 0, 4583 }, 4584 #endif /* chips */ 4585 4586 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) 4587 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_ADDR_DEFINEfmt */ 4588 /* format EGR_FLEX_CTR_ADDR_DEFINEfmt */ 4589 /* nFields */ 2, 4590 /* *fields */ soc_EGR_FLEX_CTR_ADDR_DEFINEfmt_fields, 4591 /* bits */ 20, 4592 /* flags */ 0, 4593 }, 4594 #endif /* chips */ 4595 4596 #if defined(BCM_56260_A0) 4597 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_ADDR_DEFINE_BCM56260_A0fmt */ 4598 /* format EGR_FLEX_CTR_ADDR_DEFINEfmt */ 4599 /* nFields */ 2, 4600 /* *fields */ soc_EGR_FLEX_CTR_ADDR_DEFINE_BCM56960_A0fmt_fields, 4601 /* bits */ 26, 4602 /* flags */ 0, 4603 }, 4604 #endif /* chips */ 4605 4606 #if defined(BCM_56260_B0) 4607 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_ADDR_DEFINE_BCM56260_B0fmt */ 4608 /* format EGR_FLEX_CTR_ADDR_DEFINEfmt */ 4609 /* nFields */ 2, 4610 /* *fields */ soc_EGR_FLEX_CTR_ADDR_DEFINE_BCM56960_A0fmt_fields, 4611 /* bits */ 26, 4612 /* flags */ 0, 4613 }, 4614 #endif /* chips */ 4615 4616 #if defined(BCM_56270_A0) 4617 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_ADDR_DEFINE_BCM56270_A0fmt */ 4618 /* format EGR_FLEX_CTR_ADDR_DEFINEfmt */ 4619 /* nFields */ 2, 4620 /* *fields */ soc_EGR_FLEX_CTR_ADDR_DEFINE_BCM56960_A0fmt_fields, 4621 /* bits */ 26, 4622 /* flags */ 0, 4623 }, 4624 #endif /* chips */ 4625 4626 #if defined(BCM_56340_A0) 4627 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_ADDR_DEFINE_BCM56340_A0fmt */ 4628 /* format EGR_FLEX_CTR_ADDR_DEFINEfmt */ 4629 /* nFields */ 2, 4630 /* *fields */ soc_EGR_FLEX_CTR_ADDR_DEFINE_BCM56640_A0fmt_fields, 4631 /* bits */ 26, 4632 /* flags */ 0, 4633 }, 4634 #endif /* chips */ 4635 4636 #if defined(BCM_56370_A0) 4637 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_ADDR_DEFINE_BCM56370_A0fmt */ 4638 /* format EGR_FLEX_CTR_ADDR_DEFINEfmt */ 4639 /* nFields */ 2, 4640 /* *fields */ soc_EGR_FLEX_CTR_ADDR_DEFINE_BCM56970_A0fmt_fields, 4641 /* bits */ 17, 4642 /* flags */ 0, 4643 }, 4644 #endif /* chips */ 4645 4646 #if defined(BCM_56450_A0) 4647 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_ADDR_DEFINE_BCM56450_A0fmt */ 4648 /* format EGR_FLEX_CTR_ADDR_DEFINEfmt */ 4649 /* nFields */ 2, 4650 /* *fields */ soc_EGR_FLEX_CTR_ADDR_DEFINE_BCM56640_A0fmt_fields, 4651 /* bits */ 26, 4652 /* flags */ 0, 4653 }, 4654 #endif /* chips */ 4655 4656 #if defined(BCM_56450_B0) 4657 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_ADDR_DEFINE_BCM56450_B0fmt */ 4658 /* format EGR_FLEX_CTR_ADDR_DEFINEfmt */ 4659 /* nFields */ 2, 4660 /* *fields */ soc_EGR_FLEX_CTR_ADDR_DEFINE_BCM56640_A0fmt_fields, 4661 /* bits */ 26, 4662 /* flags */ 0, 4663 }, 4664 #endif /* chips */ 4665 4666 #if defined(BCM_56450_B1) 4667 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_ADDR_DEFINE_BCM56450_B1fmt */ 4668 /* format EGR_FLEX_CTR_ADDR_DEFINEfmt */ 4669 /* nFields */ 2, 4670 /* *fields */ soc_EGR_FLEX_CTR_ADDR_DEFINE_BCM56640_A0fmt_fields, 4671 /* bits */ 26, 4672 /* flags */ 0, 4673 }, 4674 #endif /* chips */ 4675 4676 #if defined(BCM_56560_A0) 4677 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_ADDR_DEFINE_BCM56560_A0fmt */ 4678 /* format EGR_FLEX_CTR_ADDR_DEFINEfmt */ 4679 /* nFields */ 2, 4680 /* *fields */ soc_EGR_FLEX_CTR_ADDR_DEFINE_BCM56960_A0fmt_fields, 4681 /* bits */ 26, 4682 /* flags */ 0, 4683 }, 4684 #endif /* chips */ 4685 4686 #if defined(BCM_56560_B0) 4687 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_ADDR_DEFINE_BCM56560_B0fmt */ 4688 /* format EGR_FLEX_CTR_ADDR_DEFINEfmt */ 4689 /* nFields */ 2, 4690 /* *fields */ soc_EGR_FLEX_CTR_ADDR_DEFINE_BCM56960_A0fmt_fields, 4691 /* bits */ 26, 4692 /* flags */ 0, 4693 }, 4694 #endif /* chips */ 4695 4696 #if defined(BCM_56640_A0) 4697 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_ADDR_DEFINE_BCM56640_A0fmt */ 4698 /* format EGR_FLEX_CTR_ADDR_DEFINEfmt */ 4699 /* nFields */ 2, 4700 /* *fields */ soc_EGR_FLEX_CTR_ADDR_DEFINE_BCM56640_A0fmt_fields, 4701 /* bits */ 26, 4702 /* flags */ 0, 4703 }, 4704 #endif /* chips */ 4705 4706 #if defined(BCM_56670_A0) 4707 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_ADDR_DEFINE_BCM56670_A0fmt */ 4708 /* format EGR_FLEX_CTR_ADDR_DEFINEfmt */ 4709 /* nFields */ 2, 4710 /* *fields */ soc_EGR_FLEX_CTR_ADDR_DEFINE_BCM56960_A0fmt_fields, 4711 /* bits */ 26, 4712 /* flags */ 0, 4713 }, 4714 #endif /* chips */ 4715 4716 #if defined(BCM_56670_B0) 4717 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_ADDR_DEFINE_BCM56670_B0fmt */ 4718 /* format EGR_FLEX_CTR_ADDR_DEFINEfmt */ 4719 /* nFields */ 2, 4720 /* *fields */ soc_EGR_FLEX_CTR_ADDR_DEFINE_BCM56960_A0fmt_fields, 4721 /* bits */ 26, 4722 /* flags */ 0, 4723 }, 4724 #endif /* chips */ 4725 4726 #if defined(BCM_56770_A0) 4727 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_ADDR_DEFINE_BCM56770_A0fmt */ 4728 /* format EGR_FLEX_CTR_ADDR_DEFINEfmt */ 4729 /* nFields */ 2, 4730 /* *fields */ soc_EGR_FLEX_CTR_ADDR_DEFINE_BCM56970_A0fmt_fields, 4731 /* bits */ 17, 4732 /* flags */ 0, 4733 }, 4734 #endif /* chips */ 4735 4736 #if defined(BCM_56850_A0) 4737 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_ADDR_DEFINE_BCM56850_A0fmt */ 4738 /* format EGR_FLEX_CTR_ADDR_DEFINEfmt */ 4739 /* nFields */ 2, 4740 /* *fields */ soc_EGR_FLEX_CTR_ADDR_DEFINE_BCM56640_A0fmt_fields, 4741 /* bits */ 26, 4742 /* flags */ 0, 4743 }, 4744 #endif /* chips */ 4745 4746 #if defined(BCM_56860_A0) 4747 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_ADDR_DEFINE_BCM56860_A0fmt */ 4748 /* format EGR_FLEX_CTR_ADDR_DEFINEfmt */ 4749 /* nFields */ 2, 4750 /* *fields */ soc_EGR_FLEX_CTR_ADDR_DEFINE_BCM56640_A0fmt_fields, 4751 /* bits */ 26, 4752 /* flags */ 0, 4753 }, 4754 #endif /* chips */ 4755 4756 #if defined(BCM_56870_A0) 4757 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_ADDR_DEFINE_BCM56870_A0fmt */ 4758 /* format EGR_FLEX_CTR_ADDR_DEFINEfmt */ 4759 /* nFields */ 2, 4760 /* *fields */ soc_EGR_FLEX_CTR_ADDR_DEFINE_BCM56970_A0fmt_fields, 4761 /* bits */ 17, 4762 /* flags */ 0, 4763 }, 4764 #endif /* chips */ 4765 4766 #if defined(BCM_56960_A0) 4767 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_ADDR_DEFINE_BCM56960_A0fmt */ 4768 /* format EGR_FLEX_CTR_ADDR_DEFINEfmt */ 4769 /* nFields */ 2, 4770 /* *fields */ soc_EGR_FLEX_CTR_ADDR_DEFINE_BCM56960_A0fmt_fields, 4771 /* bits */ 26, 4772 /* flags */ 0, 4773 }, 4774 #endif /* chips */ 4775 4776 #if defined(BCM_56965_A0) 4777 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_ADDR_DEFINE_BCM56965_A0fmt */ 4778 /* format EGR_FLEX_CTR_ADDR_DEFINEfmt */ 4779 /* nFields */ 2, 4780 /* *fields */ soc_EGR_FLEX_CTR_ADDR_DEFINE_BCM56960_A0fmt_fields, 4781 /* bits */ 26, 4782 /* flags */ 0, 4783 }, 4784 #endif /* chips */ 4785 4786 #if defined(BCM_56970_A0) 4787 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_ADDR_DEFINE_BCM56970_A0fmt */ 4788 /* format EGR_FLEX_CTR_ADDR_DEFINEfmt */ 4789 /* nFields */ 2, 4790 /* *fields */ soc_EGR_FLEX_CTR_ADDR_DEFINE_BCM56970_A0fmt_fields, 4791 /* bits */ 17, 4792 /* flags */ 0, 4793 }, 4794 #endif /* chips */ 4795 4796 #if defined(BCM_56980_A0) 4797 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_ADDR_DEFINE_BCM56980_A0fmt */ 4798 /* format EGR_FLEX_CTR_ADDR_DEFINEfmt */ 4799 /* nFields */ 2, 4800 /* *fields */ soc_EGR_FLEX_CTR_ADDR_DEFINE_BCM56970_A0fmt_fields, 4801 /* bits */ 17, 4802 /* flags */ 0, 4803 }, 4804 #endif /* chips */ 4805 4806 #if defined(BCM_56980_B0) 4807 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_ADDR_DEFINE_BCM56980_B0fmt */ 4808 /* format EGR_FLEX_CTR_ADDR_DEFINEfmt */ 4809 /* nFields */ 2, 4810 /* *fields */ soc_EGR_FLEX_CTR_ADDR_DEFINE_BCM56970_A0fmt_fields, 4811 /* bits */ 17, 4812 /* flags */ 0, 4813 }, 4814 #endif /* chips */ 4815 4816 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) 4817 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_BUSfmt */ 4818 /* format EGR_FLEX_CTR_BUSfmt */ 4819 /* nFields */ 8, 4820 /* *fields */ soc_EGR_FLEX_CTR_BUSfmt_fields, 4821 /* bits */ 128, 4822 /* flags */ 0, 4823 }, 4824 #endif /* chips */ 4825 4826 #if defined(BCM_56260_A0) 4827 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_BUS_BCM56260_A0fmt */ 4828 /* format EGR_FLEX_CTR_BUSfmt */ 4829 /* nFields */ 8, 4830 /* *fields */ soc_ING_FLEX_CTR_BUS_BCM56560_A0fmt_fields, 4831 /* bits */ 128, 4832 /* flags */ 0, 4833 }, 4834 #endif /* chips */ 4835 4836 #if defined(BCM_56260_B0) 4837 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_BUS_BCM56260_B0fmt */ 4838 /* format EGR_FLEX_CTR_BUSfmt */ 4839 /* nFields */ 8, 4840 /* *fields */ soc_ING_FLEX_CTR_BUS_BCM56560_A0fmt_fields, 4841 /* bits */ 128, 4842 /* flags */ 0, 4843 }, 4844 #endif /* chips */ 4845 4846 #if defined(BCM_56270_A0) 4847 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_BUS_BCM56270_A0fmt */ 4848 /* format EGR_FLEX_CTR_BUSfmt */ 4849 /* nFields */ 8, 4850 /* *fields */ soc_EGR_FLEX_CTR_BUS_BCM56270_A0fmt_fields, 4851 /* bits */ 128, 4852 /* flags */ 0, 4853 }, 4854 #endif /* chips */ 4855 4856 #if defined(BCM_56340_A0) 4857 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_BUS_BCM56340_A0fmt */ 4858 /* format EGR_FLEX_CTR_BUSfmt */ 4859 /* nFields */ 8, 4860 /* *fields */ soc_EGR_FLEX_CTR_BUS_BCM56340_A0fmt_fields, 4861 /* bits */ 104, 4862 /* flags */ 0, 4863 }, 4864 #endif /* chips */ 4865 4866 #if defined(BCM_56370_A0) 4867 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_BUS_BCM56370_A0fmt */ 4868 /* format EGR_FLEX_CTR_BUSfmt */ 4869 /* nFields */ 4, 4870 /* *fields */ soc_EGR_FLEX_CTR_BUS_BCM56960_A0fmt_fields, 4871 /* bits */ 64, 4872 /* flags */ 0, 4873 }, 4874 #endif /* chips */ 4875 4876 #if defined(BCM_56450_A0) 4877 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_BUS_BCM56450_A0fmt */ 4878 /* format EGR_FLEX_CTR_BUSfmt */ 4879 /* nFields */ 8, 4880 /* *fields */ soc_EGR_FLEX_CTR_BUS_BCM56640_A0fmt_fields, 4881 /* bits */ 128, 4882 /* flags */ 0, 4883 }, 4884 #endif /* chips */ 4885 4886 #if defined(BCM_56450_B0) 4887 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_BUS_BCM56450_B0fmt */ 4888 /* format EGR_FLEX_CTR_BUSfmt */ 4889 /* nFields */ 8, 4890 /* *fields */ soc_EGR_FLEX_CTR_BUS_BCM56640_A0fmt_fields, 4891 /* bits */ 128, 4892 /* flags */ 0, 4893 }, 4894 #endif /* chips */ 4895 4896 #if defined(BCM_56450_B1) 4897 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_BUS_BCM56450_B1fmt */ 4898 /* format EGR_FLEX_CTR_BUSfmt */ 4899 /* nFields */ 8, 4900 /* *fields */ soc_EGR_FLEX_CTR_BUS_BCM56640_A0fmt_fields, 4901 /* bits */ 128, 4902 /* flags */ 0, 4903 }, 4904 #endif /* chips */ 4905 4906 #if defined(BCM_56560_A0) 4907 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_BUS_BCM56560_A0fmt */ 4908 /* format EGR_FLEX_CTR_BUSfmt */ 4909 /* nFields */ 4, 4910 /* *fields */ soc_EGR_FLEX_CTR_BUS_BCM56960_A0fmt_fields, 4911 /* bits */ 64, 4912 /* flags */ 0, 4913 }, 4914 #endif /* chips */ 4915 4916 #if defined(BCM_56560_B0) 4917 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_BUS_BCM56560_B0fmt */ 4918 /* format EGR_FLEX_CTR_BUSfmt */ 4919 /* nFields */ 4, 4920 /* *fields */ soc_EGR_FLEX_CTR_BUS_BCM56960_A0fmt_fields, 4921 /* bits */ 64, 4922 /* flags */ 0, 4923 }, 4924 #endif /* chips */ 4925 4926 #if defined(BCM_56640_A0) 4927 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_BUS_BCM56640_A0fmt */ 4928 /* format EGR_FLEX_CTR_BUSfmt */ 4929 /* nFields */ 8, 4930 /* *fields */ soc_EGR_FLEX_CTR_BUS_BCM56640_A0fmt_fields, 4931 /* bits */ 128, 4932 /* flags */ 0, 4933 }, 4934 #endif /* chips */ 4935 4936 #if defined(BCM_56670_A0) 4937 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_BUS_BCM56670_A0fmt */ 4938 /* format EGR_FLEX_CTR_BUSfmt */ 4939 /* nFields */ 4, 4940 /* *fields */ soc_EGR_FLEX_CTR_BUS_BCM56960_A0fmt_fields, 4941 /* bits */ 64, 4942 /* flags */ 0, 4943 }, 4944 #endif /* chips */ 4945 4946 #if defined(BCM_56670_B0) 4947 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_BUS_BCM56670_B0fmt */ 4948 /* format EGR_FLEX_CTR_BUSfmt */ 4949 /* nFields */ 4, 4950 /* *fields */ soc_EGR_FLEX_CTR_BUS_BCM56960_A0fmt_fields, 4951 /* bits */ 64, 4952 /* flags */ 0, 4953 }, 4954 #endif /* chips */ 4955 4956 #if defined(BCM_56770_A0) 4957 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_BUS_BCM56770_A0fmt */ 4958 /* format EGR_FLEX_CTR_BUSfmt */ 4959 /* nFields */ 4, 4960 /* *fields */ soc_EGR_FLEX_CTR_BUS_BCM56960_A0fmt_fields, 4961 /* bits */ 64, 4962 /* flags */ 0, 4963 }, 4964 #endif /* chips */ 4965 4966 #if defined(BCM_56850_A0) 4967 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_BUS_BCM56850_A0fmt */ 4968 /* format EGR_FLEX_CTR_BUSfmt */ 4969 /* nFields */ 4, 4970 /* *fields */ soc_EGR_FLEX_CTR_BUS_BCM56850_A0fmt_fields, 4971 /* bits */ 64, 4972 /* flags */ 0, 4973 }, 4974 #endif /* chips */ 4975 4976 #if defined(BCM_56860_A0) 4977 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_BUS_BCM56860_A0fmt */ 4978 /* format EGR_FLEX_CTR_BUSfmt */ 4979 /* nFields */ 4, 4980 /* *fields */ soc_EGR_FLEX_CTR_BUS_BCM56850_A0fmt_fields, 4981 /* bits */ 64, 4982 /* flags */ 0, 4983 }, 4984 #endif /* chips */ 4985 4986 #if defined(BCM_56870_A0) 4987 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_BUS_BCM56870_A0fmt */ 4988 /* format EGR_FLEX_CTR_BUSfmt */ 4989 /* nFields */ 4, 4990 /* *fields */ soc_EGR_FLEX_CTR_BUS_BCM56960_A0fmt_fields, 4991 /* bits */ 64, 4992 /* flags */ 0, 4993 }, 4994 #endif /* chips */ 4995 4996 #if defined(BCM_56960_A0) 4997 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_BUS_BCM56960_A0fmt */ 4998 /* format EGR_FLEX_CTR_BUSfmt */ 4999 /* nFields */ 4, 5000 /* *fields */ soc_EGR_FLEX_CTR_BUS_BCM56960_A0fmt_fields, 5001 /* bits */ 64, 5002 /* flags */ 0, 5003 }, 5004 #endif /* chips */ 5005 5006 #if defined(BCM_56965_A0) 5007 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_BUS_BCM56965_A0fmt */ 5008 /* format EGR_FLEX_CTR_BUSfmt */ 5009 /* nFields */ 4, 5010 /* *fields */ soc_EGR_FLEX_CTR_BUS_BCM56960_A0fmt_fields, 5011 /* bits */ 64, 5012 /* flags */ 0, 5013 }, 5014 #endif /* chips */ 5015 5016 #if defined(BCM_56970_A0) 5017 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_BUS_BCM56970_A0fmt */ 5018 /* format EGR_FLEX_CTR_BUSfmt */ 5019 /* nFields */ 4, 5020 /* *fields */ soc_EGR_FLEX_CTR_BUS_BCM56960_A0fmt_fields, 5021 /* bits */ 64, 5022 /* flags */ 0, 5023 }, 5024 #endif /* chips */ 5025 5026 #if defined(BCM_56980_A0) 5027 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_BUS_BCM56980_A0fmt */ 5028 /* format EGR_FLEX_CTR_BUSfmt */ 5029 /* nFields */ 4, 5030 /* *fields */ soc_EGR_FLEX_CTR_BUS_BCM56980_A0fmt_fields, 5031 /* bits */ 60, 5032 /* flags */ 0, 5033 }, 5034 #endif /* chips */ 5035 5036 #if defined(BCM_56980_B0) 5037 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_BUS_BCM56980_B0fmt */ 5038 /* format EGR_FLEX_CTR_BUSfmt */ 5039 /* nFields */ 4, 5040 /* *fields */ soc_EGR_FLEX_CTR_BUS_BCM56980_A0fmt_fields, 5041 /* bits */ 60, 5042 /* flags */ 0, 5043 }, 5044 #endif /* chips */ 5045 5046 #if defined(BCM_56440_A0) 5047 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_BUS_POOLfmt */ 5048 /* format EGR_FLEX_CTR_BUS_POOLfmt */ 5049 /* nFields */ 3, 5050 /* *fields */ soc_EGR_FLEX_CTR_BUS_POOLfmt_fields, 5051 /* bits */ 16, 5052 /* flags */ 0, 5053 }, 5054 #endif /* chips */ 5055 5056 #if defined(BCM_56260_A0) 5057 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_BUS_POOL_BCM56260_A0fmt */ 5058 /* format EGR_FLEX_CTR_BUS_POOLfmt */ 5059 /* nFields */ 3, 5060 /* *fields */ soc_EGR_FLEX_CTR_BUS_POOL_BCM56960_A0fmt_fields, 5061 /* bits */ 16, 5062 /* flags */ 0, 5063 }, 5064 #endif /* chips */ 5065 5066 #if defined(BCM_56260_B0) 5067 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_BUS_POOL_BCM56260_B0fmt */ 5068 /* format EGR_FLEX_CTR_BUS_POOLfmt */ 5069 /* nFields */ 3, 5070 /* *fields */ soc_EGR_FLEX_CTR_BUS_POOL_BCM56960_A0fmt_fields, 5071 /* bits */ 16, 5072 /* flags */ 0, 5073 }, 5074 #endif /* chips */ 5075 5076 #if defined(BCM_56270_A0) 5077 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_BUS_POOL_BCM56270_A0fmt */ 5078 /* format EGR_FLEX_CTR_BUS_POOLfmt */ 5079 /* nFields */ 4, 5080 /* *fields */ soc_EGR_FLEX_CTR_BUS_POOL_BCM56270_A0fmt_fields, 5081 /* bits */ 16, 5082 /* flags */ 0, 5083 }, 5084 #endif /* chips */ 5085 5086 #if defined(BCM_56340_A0) 5087 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_BUS_POOL_BCM56340_A0fmt */ 5088 /* format EGR_FLEX_CTR_BUS_POOLfmt */ 5089 /* nFields */ 3, 5090 /* *fields */ soc_EGR_FLEX_CTR_BUS_POOL_BCM56340_A0fmt_fields, 5091 /* bits */ 13, 5092 /* flags */ 0, 5093 }, 5094 #endif /* chips */ 5095 5096 #if defined(BCM_56370_A0) 5097 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_BUS_POOL_BCM56370_A0fmt */ 5098 /* format EGR_FLEX_CTR_BUS_POOLfmt */ 5099 /* nFields */ 3, 5100 /* *fields */ soc_EGR_FLEX_CTR_BUS_POOL_BCM56960_A0fmt_fields, 5101 /* bits */ 16, 5102 /* flags */ 0, 5103 }, 5104 #endif /* chips */ 5105 5106 #if defined(BCM_56440_B0) 5107 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_BUS_POOL_BCM56440_B0fmt */ 5108 /* format EGR_FLEX_CTR_BUS_POOLfmt */ 5109 /* nFields */ 3, 5110 /* *fields */ soc_EGR_FLEX_CTR_BUS_POOLfmt_fields, 5111 /* bits */ 16, 5112 /* flags */ 0, 5113 }, 5114 #endif /* chips */ 5115 5116 #if defined(BCM_56450_A0) 5117 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_BUS_POOL_BCM56450_A0fmt */ 5118 /* format EGR_FLEX_CTR_BUS_POOLfmt */ 5119 /* nFields */ 3, 5120 /* *fields */ soc_EGR_FLEX_CTR_BUS_POOL_BCM56640_A0fmt_fields, 5121 /* bits */ 16, 5122 /* flags */ 0, 5123 }, 5124 #endif /* chips */ 5125 5126 #if defined(BCM_56450_B0) 5127 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_BUS_POOL_BCM56450_B0fmt */ 5128 /* format EGR_FLEX_CTR_BUS_POOLfmt */ 5129 /* nFields */ 3, 5130 /* *fields */ soc_EGR_FLEX_CTR_BUS_POOL_BCM56640_A0fmt_fields, 5131 /* bits */ 16, 5132 /* flags */ 0, 5133 }, 5134 #endif /* chips */ 5135 5136 #if defined(BCM_56450_B1) 5137 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_BUS_POOL_BCM56450_B1fmt */ 5138 /* format EGR_FLEX_CTR_BUS_POOLfmt */ 5139 /* nFields */ 3, 5140 /* *fields */ soc_EGR_FLEX_CTR_BUS_POOL_BCM56640_A0fmt_fields, 5141 /* bits */ 16, 5142 /* flags */ 0, 5143 }, 5144 #endif /* chips */ 5145 5146 #if defined(BCM_56560_A0) 5147 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_BUS_POOL_BCM56560_A0fmt */ 5148 /* format EGR_FLEX_CTR_BUS_POOLfmt */ 5149 /* nFields */ 3, 5150 /* *fields */ soc_EGR_FLEX_CTR_BUS_POOL_BCM56960_A0fmt_fields, 5151 /* bits */ 16, 5152 /* flags */ 0, 5153 }, 5154 #endif /* chips */ 5155 5156 #if defined(BCM_56560_B0) 5157 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_BUS_POOL_BCM56560_B0fmt */ 5158 /* format EGR_FLEX_CTR_BUS_POOLfmt */ 5159 /* nFields */ 3, 5160 /* *fields */ soc_EGR_FLEX_CTR_BUS_POOL_BCM56960_A0fmt_fields, 5161 /* bits */ 16, 5162 /* flags */ 0, 5163 }, 5164 #endif /* chips */ 5165 5166 #if defined(BCM_56640_A0) 5167 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_BUS_POOL_BCM56640_A0fmt */ 5168 /* format EGR_FLEX_CTR_BUS_POOLfmt */ 5169 /* nFields */ 3, 5170 /* *fields */ soc_EGR_FLEX_CTR_BUS_POOL_BCM56640_A0fmt_fields, 5171 /* bits */ 16, 5172 /* flags */ 0, 5173 }, 5174 #endif /* chips */ 5175 5176 #if defined(BCM_56670_A0) 5177 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_BUS_POOL_BCM56670_A0fmt */ 5178 /* format EGR_FLEX_CTR_BUS_POOLfmt */ 5179 /* nFields */ 3, 5180 /* *fields */ soc_EGR_FLEX_CTR_BUS_POOL_BCM56960_A0fmt_fields, 5181 /* bits */ 16, 5182 /* flags */ 0, 5183 }, 5184 #endif /* chips */ 5185 5186 #if defined(BCM_56670_B0) 5187 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_BUS_POOL_BCM56670_B0fmt */ 5188 /* format EGR_FLEX_CTR_BUS_POOLfmt */ 5189 /* nFields */ 3, 5190 /* *fields */ soc_EGR_FLEX_CTR_BUS_POOL_BCM56960_A0fmt_fields, 5191 /* bits */ 16, 5192 /* flags */ 0, 5193 }, 5194 #endif /* chips */ 5195 5196 #if defined(BCM_56770_A0) 5197 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_BUS_POOL_BCM56770_A0fmt */ 5198 /* format EGR_FLEX_CTR_BUS_POOLfmt */ 5199 /* nFields */ 3, 5200 /* *fields */ soc_EGR_FLEX_CTR_BUS_POOL_BCM56960_A0fmt_fields, 5201 /* bits */ 16, 5202 /* flags */ 0, 5203 }, 5204 #endif /* chips */ 5205 5206 #if defined(BCM_56850_A0) 5207 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_BUS_POOL_BCM56850_A0fmt */ 5208 /* format EGR_FLEX_CTR_BUS_POOLfmt */ 5209 /* nFields */ 3, 5210 /* *fields */ soc_EGR_FLEX_CTR_BUS_POOL_BCM56640_A0fmt_fields, 5211 /* bits */ 16, 5212 /* flags */ 0, 5213 }, 5214 #endif /* chips */ 5215 5216 #if defined(BCM_56860_A0) 5217 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_BUS_POOL_BCM56860_A0fmt */ 5218 /* format EGR_FLEX_CTR_BUS_POOLfmt */ 5219 /* nFields */ 3, 5220 /* *fields */ soc_EGR_FLEX_CTR_BUS_POOL_BCM56640_A0fmt_fields, 5221 /* bits */ 16, 5222 /* flags */ 0, 5223 }, 5224 #endif /* chips */ 5225 5226 #if defined(BCM_56870_A0) 5227 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_BUS_POOL_BCM56870_A0fmt */ 5228 /* format EGR_FLEX_CTR_BUS_POOLfmt */ 5229 /* nFields */ 3, 5230 /* *fields */ soc_EGR_FLEX_CTR_BUS_POOL_BCM56960_A0fmt_fields, 5231 /* bits */ 16, 5232 /* flags */ 0, 5233 }, 5234 #endif /* chips */ 5235 5236 #if defined(BCM_56960_A0) 5237 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_BUS_POOL_BCM56960_A0fmt */ 5238 /* format EGR_FLEX_CTR_BUS_POOLfmt */ 5239 /* nFields */ 3, 5240 /* *fields */ soc_EGR_FLEX_CTR_BUS_POOL_BCM56960_A0fmt_fields, 5241 /* bits */ 16, 5242 /* flags */ 0, 5243 }, 5244 #endif /* chips */ 5245 5246 #if defined(BCM_56965_A0) 5247 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_BUS_POOL_BCM56965_A0fmt */ 5248 /* format EGR_FLEX_CTR_BUS_POOLfmt */ 5249 /* nFields */ 3, 5250 /* *fields */ soc_EGR_FLEX_CTR_BUS_POOL_BCM56960_A0fmt_fields, 5251 /* bits */ 16, 5252 /* flags */ 0, 5253 }, 5254 #endif /* chips */ 5255 5256 #if defined(BCM_56970_A0) 5257 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_BUS_POOL_BCM56970_A0fmt */ 5258 /* format EGR_FLEX_CTR_BUS_POOLfmt */ 5259 /* nFields */ 3, 5260 /* *fields */ soc_EGR_FLEX_CTR_BUS_POOL_BCM56960_A0fmt_fields, 5261 /* bits */ 16, 5262 /* flags */ 0, 5263 }, 5264 #endif /* chips */ 5265 5266 #if defined(BCM_56980_A0) 5267 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_BUS_POOL_BCM56980_A0fmt */ 5268 /* format EGR_FLEX_CTR_BUS_POOLfmt */ 5269 /* nFields */ 3, 5270 /* *fields */ soc_EGR_FLEX_CTR_BUS_POOL_BCM56980_A0fmt_fields, 5271 /* bits */ 15, 5272 /* flags */ 0, 5273 }, 5274 #endif /* chips */ 5275 5276 #if defined(BCM_56980_B0) 5277 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_BUS_POOL_BCM56980_B0fmt */ 5278 /* format EGR_FLEX_CTR_BUS_POOLfmt */ 5279 /* nFields */ 3, 5280 /* *fields */ soc_EGR_FLEX_CTR_BUS_POOL_BCM56980_A0fmt_fields, 5281 /* bits */ 15, 5282 /* flags */ 0, 5283 }, 5284 #endif /* chips */ 5285 5286 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) 5287 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_COMPRESSED_PKT_ATTRfmt */ 5288 /* format EGR_FLEX_CTR_COMPRESSED_PKT_ATTRfmt */ 5289 /* nFields */ 7, 5290 /* *fields */ soc_EGR_FLEX_CTR_COMPRESSED_PKT_ATTRfmt_fields, 5291 /* bits */ 39, 5292 /* flags */ 0, 5293 }, 5294 #endif /* chips */ 5295 5296 #if defined(BCM_56260_A0) 5297 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_COMPRESSED_PKT_ATTR_BCM56260_A0fmt */ 5298 /* format EGR_FLEX_CTR_COMPRESSED_PKT_ATTRfmt */ 5299 /* nFields */ 7, 5300 /* *fields */ soc_EGR_FLEX_CTR_COMPRESSED_PKT_ATTR_BCM56260_A0fmt_fields, 5301 /* bits */ 39, 5302 /* flags */ 0, 5303 }, 5304 #endif /* chips */ 5305 5306 #if defined(BCM_56260_B0) 5307 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_COMPRESSED_PKT_ATTR_BCM56260_B0fmt */ 5308 /* format EGR_FLEX_CTR_COMPRESSED_PKT_ATTRfmt */ 5309 /* nFields */ 7, 5310 /* *fields */ soc_EGR_FLEX_CTR_COMPRESSED_PKT_ATTR_BCM56260_A0fmt_fields, 5311 /* bits */ 39, 5312 /* flags */ 0, 5313 }, 5314 #endif /* chips */ 5315 5316 #if defined(BCM_56270_A0) 5317 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_COMPRESSED_PKT_ATTR_BCM56270_A0fmt */ 5318 /* format EGR_FLEX_CTR_COMPRESSED_PKT_ATTRfmt */ 5319 /* nFields */ 7, 5320 /* *fields */ soc_EGR_FLEX_CTR_COMPRESSED_PKT_ATTR_BCM56260_A0fmt_fields, 5321 /* bits */ 39, 5322 /* flags */ 0, 5323 }, 5324 #endif /* chips */ 5325 5326 #if defined(BCM_56340_A0) 5327 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_COMPRESSED_PKT_ATTR_BCM56340_A0fmt */ 5328 /* format EGR_FLEX_CTR_COMPRESSED_PKT_ATTRfmt */ 5329 /* nFields */ 7, 5330 /* *fields */ soc_EGR_FLEX_CTR_COMPRESSED_PKT_ATTR_BCM56640_A0fmt_fields, 5331 /* bits */ 39, 5332 /* flags */ 0, 5333 }, 5334 #endif /* chips */ 5335 5336 #if defined(BCM_56370_A0) 5337 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_COMPRESSED_PKT_ATTR_BCM56370_A0fmt */ 5338 /* format EGR_FLEX_CTR_COMPRESSED_PKT_ATTRfmt */ 5339 /* nFields */ 8, 5340 /* *fields */ soc_EGR_FLEX_CTR_COMPRESSED_PKT_ATTR_BCM56960_A0fmt_fields, 5341 /* bits */ 41, 5342 /* flags */ 0, 5343 }, 5344 #endif /* chips */ 5345 5346 #if defined(BCM_56450_A0) 5347 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_COMPRESSED_PKT_ATTR_BCM56450_A0fmt */ 5348 /* format EGR_FLEX_CTR_COMPRESSED_PKT_ATTRfmt */ 5349 /* nFields */ 7, 5350 /* *fields */ soc_EGR_FLEX_CTR_COMPRESSED_PKT_ATTR_BCM56450_A0fmt_fields, 5351 /* bits */ 39, 5352 /* flags */ 0, 5353 }, 5354 #endif /* chips */ 5355 5356 #if defined(BCM_56450_B0) 5357 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_COMPRESSED_PKT_ATTR_BCM56450_B0fmt */ 5358 /* format EGR_FLEX_CTR_COMPRESSED_PKT_ATTRfmt */ 5359 /* nFields */ 7, 5360 /* *fields */ soc_EGR_FLEX_CTR_COMPRESSED_PKT_ATTR_BCM56450_A0fmt_fields, 5361 /* bits */ 39, 5362 /* flags */ 0, 5363 }, 5364 #endif /* chips */ 5365 5366 #if defined(BCM_56450_B1) 5367 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_COMPRESSED_PKT_ATTR_BCM56450_B1fmt */ 5368 /* format EGR_FLEX_CTR_COMPRESSED_PKT_ATTRfmt */ 5369 /* nFields */ 7, 5370 /* *fields */ soc_EGR_FLEX_CTR_COMPRESSED_PKT_ATTR_BCM56450_A0fmt_fields, 5371 /* bits */ 39, 5372 /* flags */ 0, 5373 }, 5374 #endif /* chips */ 5375 5376 #if defined(BCM_56560_A0) 5377 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_COMPRESSED_PKT_ATTR_BCM56560_A0fmt */ 5378 /* format EGR_FLEX_CTR_COMPRESSED_PKT_ATTRfmt */ 5379 /* nFields */ 14, 5380 /* *fields */ soc_EGR_FLEX_CTR_COMPRESSED_PKT_ATTR_BCM56560_A0fmt_fields, 5381 /* bits */ 64, 5382 /* flags */ 0, 5383 }, 5384 #endif /* chips */ 5385 5386 #if defined(BCM_56560_B0) 5387 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_COMPRESSED_PKT_ATTR_BCM56560_B0fmt */ 5388 /* format EGR_FLEX_CTR_COMPRESSED_PKT_ATTRfmt */ 5389 /* nFields */ 14, 5390 /* *fields */ soc_EGR_FLEX_CTR_COMPRESSED_PKT_ATTR_BCM56560_A0fmt_fields, 5391 /* bits */ 64, 5392 /* flags */ 0, 5393 }, 5394 #endif /* chips */ 5395 5396 #if defined(BCM_56640_A0) 5397 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_COMPRESSED_PKT_ATTR_BCM56640_A0fmt */ 5398 /* format EGR_FLEX_CTR_COMPRESSED_PKT_ATTRfmt */ 5399 /* nFields */ 7, 5400 /* *fields */ soc_EGR_FLEX_CTR_COMPRESSED_PKT_ATTR_BCM56640_A0fmt_fields, 5401 /* bits */ 39, 5402 /* flags */ 0, 5403 }, 5404 #endif /* chips */ 5405 5406 #if defined(BCM_56670_A0) 5407 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_COMPRESSED_PKT_ATTR_BCM56670_A0fmt */ 5408 /* format EGR_FLEX_CTR_COMPRESSED_PKT_ATTRfmt */ 5409 /* nFields */ 14, 5410 /* *fields */ soc_EGR_FLEX_CTR_COMPRESSED_PKT_ATTR_BCM56560_A0fmt_fields, 5411 /* bits */ 64, 5412 /* flags */ 0, 5413 }, 5414 #endif /* chips */ 5415 5416 #if defined(BCM_56670_B0) 5417 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_COMPRESSED_PKT_ATTR_BCM56670_B0fmt */ 5418 /* format EGR_FLEX_CTR_COMPRESSED_PKT_ATTRfmt */ 5419 /* nFields */ 14, 5420 /* *fields */ soc_EGR_FLEX_CTR_COMPRESSED_PKT_ATTR_BCM56560_A0fmt_fields, 5421 /* bits */ 64, 5422 /* flags */ 0, 5423 }, 5424 #endif /* chips */ 5425 5426 #if defined(BCM_56770_A0) 5427 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_COMPRESSED_PKT_ATTR_BCM56770_A0fmt */ 5428 /* format EGR_FLEX_CTR_COMPRESSED_PKT_ATTRfmt */ 5429 /* nFields */ 8, 5430 /* *fields */ soc_EGR_FLEX_CTR_COMPRESSED_PKT_ATTR_BCM56960_A0fmt_fields, 5431 /* bits */ 41, 5432 /* flags */ 0, 5433 }, 5434 #endif /* chips */ 5435 5436 #if defined(BCM_56850_A0) 5437 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_COMPRESSED_PKT_ATTR_BCM56850_A0fmt */ 5438 /* format EGR_FLEX_CTR_COMPRESSED_PKT_ATTRfmt */ 5439 /* nFields */ 7, 5440 /* *fields */ soc_EGR_FLEX_CTR_COMPRESSED_PKT_ATTR_BCM56850_A0fmt_fields, 5441 /* bits */ 40, 5442 /* flags */ 0, 5443 }, 5444 #endif /* chips */ 5445 5446 #if defined(BCM_56860_A0) 5447 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_COMPRESSED_PKT_ATTR_BCM56860_A0fmt */ 5448 /* format EGR_FLEX_CTR_COMPRESSED_PKT_ATTRfmt */ 5449 /* nFields */ 7, 5450 /* *fields */ soc_EGR_FLEX_CTR_COMPRESSED_PKT_ATTR_BCM56850_A0fmt_fields, 5451 /* bits */ 40, 5452 /* flags */ 0, 5453 }, 5454 #endif /* chips */ 5455 5456 #if defined(BCM_56870_A0) 5457 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_COMPRESSED_PKT_ATTR_BCM56870_A0fmt */ 5458 /* format EGR_FLEX_CTR_COMPRESSED_PKT_ATTRfmt */ 5459 /* nFields */ 8, 5460 /* *fields */ soc_EGR_FLEX_CTR_COMPRESSED_PKT_ATTR_BCM56960_A0fmt_fields, 5461 /* bits */ 41, 5462 /* flags */ 0, 5463 }, 5464 #endif /* chips */ 5465 5466 #if defined(BCM_56960_A0) 5467 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_COMPRESSED_PKT_ATTR_BCM56960_A0fmt */ 5468 /* format EGR_FLEX_CTR_COMPRESSED_PKT_ATTRfmt */ 5469 /* nFields */ 8, 5470 /* *fields */ soc_EGR_FLEX_CTR_COMPRESSED_PKT_ATTR_BCM56960_A0fmt_fields, 5471 /* bits */ 41, 5472 /* flags */ 0, 5473 }, 5474 #endif /* chips */ 5475 5476 #if defined(BCM_56965_A0) 5477 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_COMPRESSED_PKT_ATTR_BCM56965_A0fmt */ 5478 /* format EGR_FLEX_CTR_COMPRESSED_PKT_ATTRfmt */ 5479 /* nFields */ 8, 5480 /* *fields */ soc_EGR_FLEX_CTR_COMPRESSED_PKT_ATTR_BCM56960_A0fmt_fields, 5481 /* bits */ 41, 5482 /* flags */ 0, 5483 }, 5484 #endif /* chips */ 5485 5486 #if defined(BCM_56970_A0) 5487 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_COMPRESSED_PKT_ATTR_BCM56970_A0fmt */ 5488 /* format EGR_FLEX_CTR_COMPRESSED_PKT_ATTRfmt */ 5489 /* nFields */ 8, 5490 /* *fields */ soc_EGR_FLEX_CTR_COMPRESSED_PKT_ATTR_BCM56960_A0fmt_fields, 5491 /* bits */ 41, 5492 /* flags */ 0, 5493 }, 5494 #endif /* chips */ 5495 5496 #if defined(BCM_56440_A0) 5497 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_PKT_ATTRfmt */ 5498 /* format EGR_FLEX_CTR_PKT_ATTRfmt */ 5499 /* nFields */ 13, 5500 /* *fields */ soc_EGR_FLEX_CTR_PKT_ATTRfmt_fields, 5501 /* bits */ 39, 5502 /* flags */ 0, 5503 }, 5504 #endif /* chips */ 5505 5506 #if defined(BCM_56260_A0) 5507 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_PKT_ATTR_BCM56260_A0fmt */ 5508 /* format EGR_FLEX_CTR_PKT_ATTRfmt */ 5509 /* nFields */ 14, 5510 /* *fields */ soc_EGR_FLEX_CTR_PKT_ATTR_BCM56260_A0fmt_fields, 5511 /* bits */ 43, 5512 /* flags */ 0, 5513 }, 5514 #endif /* chips */ 5515 5516 #if defined(BCM_56260_B0) 5517 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_PKT_ATTR_BCM56260_B0fmt */ 5518 /* format EGR_FLEX_CTR_PKT_ATTRfmt */ 5519 /* nFields */ 14, 5520 /* *fields */ soc_EGR_FLEX_CTR_PKT_ATTR_BCM56260_A0fmt_fields, 5521 /* bits */ 43, 5522 /* flags */ 0, 5523 }, 5524 #endif /* chips */ 5525 5526 #if defined(BCM_56270_A0) 5527 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_PKT_ATTR_BCM56270_A0fmt */ 5528 /* format EGR_FLEX_CTR_PKT_ATTRfmt */ 5529 /* nFields */ 14, 5530 /* *fields */ soc_EGR_FLEX_CTR_PKT_ATTR_BCM56270_A0fmt_fields, 5531 /* bits */ 43, 5532 /* flags */ 0, 5533 }, 5534 #endif /* chips */ 5535 5536 #if defined(BCM_56340_A0) 5537 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_PKT_ATTR_BCM56340_A0fmt */ 5538 /* format EGR_FLEX_CTR_PKT_ATTRfmt */ 5539 /* nFields */ 13, 5540 /* *fields */ soc_EGR_FLEX_CTR_PKT_ATTR_BCM56640_A0fmt_fields, 5541 /* bits */ 39, 5542 /* flags */ 0, 5543 }, 5544 #endif /* chips */ 5545 5546 #if defined(BCM_56370_A0) 5547 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_PKT_ATTR_BCM56370_A0fmt */ 5548 /* format EGR_FLEX_CTR_PKT_ATTRfmt */ 5549 /* nFields */ 16, 5550 /* *fields */ soc_EGR_FLEX_CTR_PKT_ATTR_BCM56370_A0fmt_fields, 5551 /* bits */ 48, 5552 /* flags */ 0, 5553 }, 5554 #endif /* chips */ 5555 5556 #if defined(BCM_56440_B0) 5557 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_PKT_ATTR_BCM56440_B0fmt */ 5558 /* format EGR_FLEX_CTR_PKT_ATTRfmt */ 5559 /* nFields */ 13, 5560 /* *fields */ soc_EGR_FLEX_CTR_PKT_ATTRfmt_fields, 5561 /* bits */ 39, 5562 /* flags */ 0, 5563 }, 5564 #endif /* chips */ 5565 5566 #if defined(BCM_56450_A0) 5567 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_PKT_ATTR_BCM56450_A0fmt */ 5568 /* format EGR_FLEX_CTR_PKT_ATTRfmt */ 5569 /* nFields */ 13, 5570 /* *fields */ soc_EGR_FLEX_CTR_PKT_ATTR_BCM56450_A0fmt_fields, 5571 /* bits */ 43, 5572 /* flags */ 0, 5573 }, 5574 #endif /* chips */ 5575 5576 #if defined(BCM_56450_B0) 5577 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_PKT_ATTR_BCM56450_B0fmt */ 5578 /* format EGR_FLEX_CTR_PKT_ATTRfmt */ 5579 /* nFields */ 13, 5580 /* *fields */ soc_EGR_FLEX_CTR_PKT_ATTR_BCM56450_A0fmt_fields, 5581 /* bits */ 43, 5582 /* flags */ 0, 5583 }, 5584 #endif /* chips */ 5585 5586 #if defined(BCM_56450_B1) 5587 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_PKT_ATTR_BCM56450_B1fmt */ 5588 /* format EGR_FLEX_CTR_PKT_ATTRfmt */ 5589 /* nFields */ 13, 5590 /* *fields */ soc_EGR_FLEX_CTR_PKT_ATTR_BCM56450_A0fmt_fields, 5591 /* bits */ 43, 5592 /* flags */ 0, 5593 }, 5594 #endif /* chips */ 5595 5596 #if defined(BCM_56560_A0) 5597 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_PKT_ATTR_BCM56560_A0fmt */ 5598 /* format EGR_FLEX_CTR_PKT_ATTRfmt */ 5599 /* nFields */ 20, 5600 /* *fields */ soc_EGR_FLEX_CTR_PKT_ATTR_BCM56560_A0fmt_fields, 5601 /* bits */ 64, 5602 /* flags */ 0, 5603 }, 5604 #endif /* chips */ 5605 5606 #if defined(BCM_56560_B0) 5607 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_PKT_ATTR_BCM56560_B0fmt */ 5608 /* format EGR_FLEX_CTR_PKT_ATTRfmt */ 5609 /* nFields */ 20, 5610 /* *fields */ soc_EGR_FLEX_CTR_PKT_ATTR_BCM56560_A0fmt_fields, 5611 /* bits */ 64, 5612 /* flags */ 0, 5613 }, 5614 #endif /* chips */ 5615 5616 #if defined(BCM_56640_A0) 5617 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_PKT_ATTR_BCM56640_A0fmt */ 5618 /* format EGR_FLEX_CTR_PKT_ATTRfmt */ 5619 /* nFields */ 13, 5620 /* *fields */ soc_EGR_FLEX_CTR_PKT_ATTR_BCM56640_A0fmt_fields, 5621 /* bits */ 39, 5622 /* flags */ 0, 5623 }, 5624 #endif /* chips */ 5625 5626 #if defined(BCM_56670_A0) 5627 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_PKT_ATTR_BCM56670_A0fmt */ 5628 /* format EGR_FLEX_CTR_PKT_ATTRfmt */ 5629 /* nFields */ 20, 5630 /* *fields */ soc_EGR_FLEX_CTR_PKT_ATTR_BCM56560_A0fmt_fields, 5631 /* bits */ 64, 5632 /* flags */ 0, 5633 }, 5634 #endif /* chips */ 5635 5636 #if defined(BCM_56670_B0) 5637 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_PKT_ATTR_BCM56670_B0fmt */ 5638 /* format EGR_FLEX_CTR_PKT_ATTRfmt */ 5639 /* nFields */ 20, 5640 /* *fields */ soc_EGR_FLEX_CTR_PKT_ATTR_BCM56560_A0fmt_fields, 5641 /* bits */ 64, 5642 /* flags */ 0, 5643 }, 5644 #endif /* chips */ 5645 5646 #if defined(BCM_56770_A0) 5647 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_PKT_ATTR_BCM56770_A0fmt */ 5648 /* format EGR_FLEX_CTR_PKT_ATTRfmt */ 5649 /* nFields */ 15, 5650 /* *fields */ soc_EGR_FLEX_CTR_PKT_ATTR_BCM56870_A0fmt_fields, 5651 /* bits */ 45, 5652 /* flags */ 0, 5653 }, 5654 #endif /* chips */ 5655 5656 #if defined(BCM_56850_A0) 5657 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_PKT_ATTR_BCM56850_A0fmt */ 5658 /* format EGR_FLEX_CTR_PKT_ATTRfmt */ 5659 /* nFields */ 13, 5660 /* *fields */ soc_EGR_FLEX_CTR_PKT_ATTR_BCM56850_A0fmt_fields, 5661 /* bits */ 40, 5662 /* flags */ 0, 5663 }, 5664 #endif /* chips */ 5665 5666 #if defined(BCM_56860_A0) 5667 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_PKT_ATTR_BCM56860_A0fmt */ 5668 /* format EGR_FLEX_CTR_PKT_ATTRfmt */ 5669 /* nFields */ 13, 5670 /* *fields */ soc_EGR_FLEX_CTR_PKT_ATTR_BCM56850_A0fmt_fields, 5671 /* bits */ 40, 5672 /* flags */ 0, 5673 }, 5674 #endif /* chips */ 5675 5676 #if defined(BCM_56870_A0) 5677 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_PKT_ATTR_BCM56870_A0fmt */ 5678 /* format EGR_FLEX_CTR_PKT_ATTRfmt */ 5679 /* nFields */ 15, 5680 /* *fields */ soc_EGR_FLEX_CTR_PKT_ATTR_BCM56870_A0fmt_fields, 5681 /* bits */ 45, 5682 /* flags */ 0, 5683 }, 5684 #endif /* chips */ 5685 5686 #if defined(BCM_56960_A0) 5687 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_PKT_ATTR_BCM56960_A0fmt */ 5688 /* format EGR_FLEX_CTR_PKT_ATTRfmt */ 5689 /* nFields */ 15, 5690 /* *fields */ soc_EGR_FLEX_CTR_PKT_ATTR_BCM56960_A0fmt_fields, 5691 /* bits */ 41, 5692 /* flags */ 0, 5693 }, 5694 #endif /* chips */ 5695 5696 #if defined(BCM_56965_A0) 5697 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_PKT_ATTR_BCM56965_A0fmt */ 5698 /* format EGR_FLEX_CTR_PKT_ATTRfmt */ 5699 /* nFields */ 15, 5700 /* *fields */ soc_EGR_FLEX_CTR_PKT_ATTR_BCM56960_A0fmt_fields, 5701 /* bits */ 41, 5702 /* flags */ 0, 5703 }, 5704 #endif /* chips */ 5705 5706 #if defined(BCM_56970_A0) 5707 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_PKT_ATTR_BCM56970_A0fmt */ 5708 /* format EGR_FLEX_CTR_PKT_ATTRfmt */ 5709 /* nFields */ 15, 5710 /* *fields */ soc_EGR_FLEX_CTR_PKT_ATTR_BCM56960_A0fmt_fields, 5711 /* bits */ 41, 5712 /* flags */ 0, 5713 }, 5714 #endif /* chips */ 5715 5716 #if defined(BCM_56980_A0) 5717 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_PKT_ATTR_BCM56980_A0fmt */ 5718 /* format EGR_FLEX_CTR_PKT_ATTRfmt */ 5719 /* nFields */ 15, 5720 /* *fields */ soc_EGR_FLEX_CTR_PKT_ATTR_BCM56980_A0fmt_fields, 5721 /* bits */ 41, 5722 /* flags */ 0, 5723 }, 5724 #endif /* chips */ 5725 5726 #if defined(BCM_56980_B0) 5727 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_PKT_ATTR_BCM56980_B0fmt */ 5728 /* format EGR_FLEX_CTR_PKT_ATTRfmt */ 5729 /* nFields */ 15, 5730 /* *fields */ soc_EGR_FLEX_CTR_PKT_ATTR_BCM56980_A0fmt_fields, 5731 /* bits */ 41, 5732 /* flags */ 0, 5733 }, 5734 #endif /* chips */ 5735 5736 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 5737 defined(BCM_56870_A0) 5738 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_PKT_RES_MAP_INDEXfmt */ 5739 /* format EGR_FLEX_CTR_PKT_RES_MAP_INDEXfmt */ 5740 /* nFields */ 4, 5741 /* *fields */ soc_EGR_FLEX_CTR_PKT_RES_MAP_INDEXfmt_fields, 5742 /* bits */ 8, 5743 /* flags */ 0, 5744 }, 5745 #endif /* chips */ 5746 5747 #if defined(BCM_56340_A0) || defined(BCM_56640_A0) || \ 5748 defined(BCM_56850_A0) 5749 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_UDFfmt */ 5750 /* format EGR_FLEX_CTR_UDFfmt */ 5751 /* nFields */ 3, 5752 /* *fields */ soc_EGR_FLEX_CTR_UDFfmt_fields, 5753 /* bits */ 33, 5754 /* flags */ 0, 5755 }, 5756 #endif /* chips */ 5757 5758 #if defined(BCM_56370_A0) 5759 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_UDF_BCM56370_A0fmt */ 5760 /* format EGR_FLEX_CTR_UDFfmt */ 5761 /* nFields */ 3, 5762 /* *fields */ soc_EGR_FLEX_CTR_UDF_BCM56960_A0fmt_fields, 5763 /* bits */ 33, 5764 /* flags */ 0, 5765 }, 5766 #endif /* chips */ 5767 5768 #if defined(BCM_56770_A0) 5769 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_UDF_BCM56770_A0fmt */ 5770 /* format EGR_FLEX_CTR_UDFfmt */ 5771 /* nFields */ 3, 5772 /* *fields */ soc_EGR_FLEX_CTR_UDF_BCM56960_A0fmt_fields, 5773 /* bits */ 33, 5774 /* flags */ 0, 5775 }, 5776 #endif /* chips */ 5777 5778 #if defined(BCM_56870_A0) 5779 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_UDF_BCM56870_A0fmt */ 5780 /* format EGR_FLEX_CTR_UDFfmt */ 5781 /* nFields */ 3, 5782 /* *fields */ soc_EGR_FLEX_CTR_UDF_BCM56960_A0fmt_fields, 5783 /* bits */ 33, 5784 /* flags */ 0, 5785 }, 5786 #endif /* chips */ 5787 5788 #if defined(BCM_56960_A0) 5789 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_UDF_BCM56960_A0fmt */ 5790 /* format EGR_FLEX_CTR_UDFfmt */ 5791 /* nFields */ 3, 5792 /* *fields */ soc_EGR_FLEX_CTR_UDF_BCM56960_A0fmt_fields, 5793 /* bits */ 33, 5794 /* flags */ 0, 5795 }, 5796 #endif /* chips */ 5797 5798 #if defined(BCM_56965_A0) 5799 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_UDF_BCM56965_A0fmt */ 5800 /* format EGR_FLEX_CTR_UDFfmt */ 5801 /* nFields */ 3, 5802 /* *fields */ soc_EGR_FLEX_CTR_UDF_BCM56960_A0fmt_fields, 5803 /* bits */ 33, 5804 /* flags */ 0, 5805 }, 5806 #endif /* chips */ 5807 5808 #if defined(BCM_56970_A0) 5809 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_UDF_BCM56970_A0fmt */ 5810 /* format EGR_FLEX_CTR_UDFfmt */ 5811 /* nFields */ 3, 5812 /* *fields */ soc_EGR_FLEX_CTR_UDF_BCM56960_A0fmt_fields, 5813 /* bits */ 33, 5814 /* flags */ 0, 5815 }, 5816 #endif /* chips */ 5817 5818 #if defined(BCM_56980_A0) 5819 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_UDF_BCM56980_A0fmt */ 5820 /* format EGR_FLEX_CTR_UDFfmt */ 5821 /* nFields */ 3, 5822 /* *fields */ soc_EGR_FLEX_CTR_UDF_BCM56960_A0fmt_fields, 5823 /* bits */ 33, 5824 /* flags */ 0, 5825 }, 5826 #endif /* chips */ 5827 5828 #if defined(BCM_56980_B0) 5829 { /* SOC_FORMAT_INT_EGR_FLEX_CTR_UDF_BCM56980_B0fmt */ 5830 /* format EGR_FLEX_CTR_UDFfmt */ 5831 /* nFields */ 3, 5832 /* *fields */ soc_EGR_FLEX_CTR_UDF_BCM56960_A0fmt_fields, 5833 /* bits */ 33, 5834 /* flags */ 0, 5835 }, 5836 #endif /* chips */ 5837 5838 #if defined(BCM_56670_A0) || defined(BCM_56670_B0) 5839 { /* SOC_FORMAT_INT_EGR_FLEX_PREEMPT_LOOKUPfmt */ 5840 /* format EGR_FLEX_PREEMPT_LOOKUPfmt */ 5841 /* nFields */ 5, 5842 /* *fields */ soc_EGR_FLEX_PREEMPT_LOOKUPfmt_fields, 5843 /* bits */ 84, 5844 /* flags */ 0, 5845 }, 5846 #endif /* chips */ 5847 5848 #if defined(BCM_56670_A0) || defined(BCM_56670_B0) 5849 { /* SOC_FORMAT_INT_EGR_FLEX_PREEMPT_XFR_COUNTfmt */ 5850 /* format EGR_FLEX_PREEMPT_XFR_COUNTfmt */ 5851 /* nFields */ 12, 5852 /* *fields */ soc_EGR_FLEX_PREEMPT_XFR_COUNTfmt_fields, 5853 /* bits */ 64, 5854 /* flags */ 0, 5855 }, 5856 #endif /* chips */ 5857 5858 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) 5859 { /* SOC_FORMAT_INT_EGR_FPMOD_EMOP_BUFFERfmt */ 5860 /* format EGR_FPMOD_EMOP_BUFFERfmt */ 5861 /* nFields */ 6, 5862 /* *fields */ soc_EGR_FPMOD_EMOP_BUFFERfmt_fields, 5863 /* bits */ 32, 5864 /* flags */ 0, 5865 }, 5866 #endif /* chips */ 5867 5868 #if defined(BCM_56670_A0) 5869 { /* SOC_FORMAT_INT_EGR_FPMOD_EMOP_BUFFER_BCM56670_A0fmt */ 5870 /* format EGR_FPMOD_EMOP_BUFFERfmt */ 5871 /* nFields */ 4, 5872 /* *fields */ soc_EGR_FPMOD_EMOP_BUFFER_BCM56670_A0fmt_fields, 5873 /* bits */ 30, 5874 /* flags */ 0, 5875 }, 5876 #endif /* chips */ 5877 5878 #if defined(BCM_56670_B0) 5879 { /* SOC_FORMAT_INT_EGR_FPMOD_EMOP_BUFFER_BCM56670_B0fmt */ 5880 /* format EGR_FPMOD_EMOP_BUFFERfmt */ 5881 /* nFields */ 4, 5882 /* *fields */ soc_EGR_FPMOD_EMOP_BUFFER_BCM56670_A0fmt_fields, 5883 /* bits */ 30, 5884 /* flags */ 0, 5885 }, 5886 #endif /* chips */ 5887 5888 #if defined(BCM_56340_A0) || defined(BCM_56640_A0) 5889 { /* SOC_FORMAT_INT_EGR_FRAGMENT_ID_TABLE_COV_DEFSfmt */ 5890 /* format EGR_FRAGMENT_ID_TABLE_COV_DEFSfmt */ 5891 /* nFields */ 6, 5892 /* *fields */ soc_EGR_FRAGMENT_ID_TABLE_COV_DEFSfmt_fields, 5893 /* bits */ 17, 5894 /* flags */ 0, 5895 }, 5896 #endif /* chips */ 5897 5898 #if defined(BCM_56560_A0) 5899 { /* SOC_FORMAT_INT_EGR_FRAGMENT_ID_TABLE_COV_DEFS_BCM56560_A0fmt */ 5900 /* format EGR_FRAGMENT_ID_TABLE_COV_DEFSfmt */ 5901 /* nFields */ 6, 5902 /* *fields */ soc_EFP_COUNTER_TABLE_COV_DEFS_BCM53400_A0fmt_fields, 5903 /* bits */ 15, 5904 /* flags */ 0, 5905 }, 5906 #endif /* chips */ 5907 5908 #if defined(BCM_56560_B0) 5909 { /* SOC_FORMAT_INT_EGR_FRAGMENT_ID_TABLE_COV_DEFS_BCM56560_B0fmt */ 5910 /* format EGR_FRAGMENT_ID_TABLE_COV_DEFSfmt */ 5911 /* nFields */ 6, 5912 /* *fields */ soc_EFP_COUNTER_TABLE_COV_DEFS_BCM53400_A0fmt_fields, 5913 /* bits */ 15, 5914 /* flags */ 0, 5915 }, 5916 #endif /* chips */ 5917 5918 #if defined(BCM_56670_A0) 5919 { /* SOC_FORMAT_INT_EGR_FRAGMENT_ID_TABLE_COV_DEFS_BCM56670_A0fmt */ 5920 /* format EGR_FRAGMENT_ID_TABLE_COV_DEFSfmt */ 5921 /* nFields */ 6, 5922 /* *fields */ soc_EFP_COUNTER_TABLE_COV_DEFS_BCM53400_A0fmt_fields, 5923 /* bits */ 15, 5924 /* flags */ 0, 5925 }, 5926 #endif /* chips */ 5927 5928 #if defined(BCM_56670_B0) 5929 { /* SOC_FORMAT_INT_EGR_FRAGMENT_ID_TABLE_COV_DEFS_BCM56670_B0fmt */ 5930 /* format EGR_FRAGMENT_ID_TABLE_COV_DEFSfmt */ 5931 /* nFields */ 6, 5932 /* *fields */ soc_EFP_COUNTER_TABLE_COV_DEFS_BCM53400_A0fmt_fields, 5933 /* bits */ 15, 5934 /* flags */ 0, 5935 }, 5936 #endif /* chips */ 5937 5938 #if defined(BCM_56850_A0) 5939 { /* SOC_FORMAT_INT_EGR_FRAGMENT_ID_TABLE_COV_DEFS_BCM56850_A0fmt */ 5940 /* format EGR_FRAGMENT_ID_TABLE_COV_DEFSfmt */ 5941 /* nFields */ 6, 5942 /* *fields */ soc_EGR_FRAGMENT_ID_TABLE_COV_DEFS_BCM56850_A0fmt_fields, 5943 /* bits */ 15, 5944 /* flags */ 0, 5945 }, 5946 #endif /* chips */ 5947 5948 #if defined(BCM_56860_A0) 5949 { /* SOC_FORMAT_INT_EGR_FRAGMENT_ID_TABLE_COV_DEFS_BCM56860_A0fmt */ 5950 /* format EGR_FRAGMENT_ID_TABLE_COV_DEFSfmt */ 5951 /* nFields */ 6, 5952 /* *fields */ soc_EGR_FRAGMENT_ID_TABLE_COV_DEFS_BCM56850_A0fmt_fields, 5953 /* bits */ 15, 5954 /* flags */ 0, 5955 }, 5956 #endif /* chips */ 5957 5958 #if defined(BCM_56960_A0) 5959 { /* SOC_FORMAT_INT_EGR_FRAGMENT_ID_TABLE_COV_DEFS_BCM56960_A0fmt */ 5960 /* format EGR_FRAGMENT_ID_TABLE_COV_DEFSfmt */ 5961 /* nFields */ 6, 5962 /* *fields */ soc_EFP_COUNTER_TABLE_COV_DEFS_BCM53400_A0fmt_fields, 5963 /* bits */ 15, 5964 /* flags */ 0, 5965 }, 5966 #endif /* chips */ 5967 5968 #if defined(BCM_56965_A0) 5969 { /* SOC_FORMAT_INT_EGR_FRAGMENT_ID_TABLE_COV_DEFS_BCM56965_A0fmt */ 5970 /* format EGR_FRAGMENT_ID_TABLE_COV_DEFSfmt */ 5971 /* nFields */ 6, 5972 /* *fields */ soc_EFP_COUNTER_TABLE_COV_DEFS_BCM53400_A0fmt_fields, 5973 /* bits */ 15, 5974 /* flags */ 0, 5975 }, 5976 #endif /* chips */ 5977 5978 #if defined(BCM_56970_A0) 5979 { /* SOC_FORMAT_INT_EGR_FRAGMENT_ID_TABLE_COV_DEFS_BCM56970_A0fmt */ 5980 /* format EGR_FRAGMENT_ID_TABLE_COV_DEFSfmt */ 5981 /* nFields */ 6, 5982 /* *fields */ soc_EGR_PERQ_XMT_COUNTERS_COV_DEFS_BCM56960_A0fmt_fields, 5983 /* bits */ 17, 5984 /* flags */ 0, 5985 }, 5986 #endif /* chips */ 5987 5988 #if defined(BCM_56980_A0) 5989 { /* SOC_FORMAT_INT_EGR_FRAGMENT_ID_TABLE_COV_DEFS_BCM56980_A0fmt */ 5990 /* format EGR_FRAGMENT_ID_TABLE_COV_DEFSfmt */ 5991 /* nFields */ 6, 5992 /* *fields */ soc_EGR_PERQ_XMT_COUNTERS_COV_DEFS_BCM56960_A0fmt_fields, 5993 /* bits */ 17, 5994 /* flags */ 0, 5995 }, 5996 #endif /* chips */ 5997 5998 #if defined(BCM_56980_B0) 5999 { /* SOC_FORMAT_INT_EGR_FRAGMENT_ID_TABLE_COV_DEFS_BCM56980_B0fmt */ 6000 /* format EGR_FRAGMENT_ID_TABLE_COV_DEFSfmt */ 6001 /* nFields */ 6, 6002 /* *fields */ soc_EGR_PERQ_XMT_COUNTERS_COV_DEFS_BCM56960_A0fmt_fields, 6003 /* bits */ 17, 6004 /* flags */ 0, 6005 }, 6006 #endif /* chips */ 6007 6008 #if defined(BCM_56840_B0) 6009 { /* SOC_FORMAT_INT_EGR_HW_CTRL_Q_BUSfmt */ 6010 /* format EGR_HW_CTRL_Q_BUSfmt */ 6011 /* nFields */ 2, 6012 /* *fields */ soc_EGR_HW_CTRL_Q_BUSfmt_fields, 6013 /* bits */ 12, 6014 /* flags */ 0, 6015 }, 6016 #endif /* chips */ 6017 6018 #if defined(BCM_56370_A0) 6019 { /* SOC_FORMAT_INT_EGR_HW_CTRL_Q_BUS_BCM56370_A0fmt */ 6020 /* format EGR_HW_CTRL_Q_BUSfmt */ 6021 /* nFields */ 1, 6022 /* *fields */ soc_EGR_HW_CTRL_Q_BUS_BCM56870_A0fmt_fields, 6023 /* bits */ 12, 6024 /* flags */ 0, 6025 }, 6026 #endif /* chips */ 6027 6028 #if defined(BCM_56560_A0) 6029 { /* SOC_FORMAT_INT_EGR_HW_CTRL_Q_BUS_BCM56560_A0fmt */ 6030 /* format EGR_HW_CTRL_Q_BUSfmt */ 6031 /* nFields */ 2, 6032 /* *fields */ soc_EGR_HW_CTRL_Q_BUS_BCM56960_A0fmt_fields, 6033 /* bits */ 12, 6034 /* flags */ 0, 6035 }, 6036 #endif /* chips */ 6037 6038 #if defined(BCM_56560_B0) 6039 { /* SOC_FORMAT_INT_EGR_HW_CTRL_Q_BUS_BCM56560_B0fmt */ 6040 /* format EGR_HW_CTRL_Q_BUSfmt */ 6041 /* nFields */ 2, 6042 /* *fields */ soc_EGR_HW_CTRL_Q_BUS_BCM56960_A0fmt_fields, 6043 /* bits */ 12, 6044 /* flags */ 0, 6045 }, 6046 #endif /* chips */ 6047 6048 #if defined(BCM_56670_A0) 6049 { /* SOC_FORMAT_INT_EGR_HW_CTRL_Q_BUS_BCM56670_A0fmt */ 6050 /* format EGR_HW_CTRL_Q_BUSfmt */ 6051 /* nFields */ 2, 6052 /* *fields */ soc_EGR_HW_CTRL_Q_BUS_BCM56960_A0fmt_fields, 6053 /* bits */ 12, 6054 /* flags */ 0, 6055 }, 6056 #endif /* chips */ 6057 6058 #if defined(BCM_56670_B0) 6059 { /* SOC_FORMAT_INT_EGR_HW_CTRL_Q_BUS_BCM56670_B0fmt */ 6060 /* format EGR_HW_CTRL_Q_BUSfmt */ 6061 /* nFields */ 2, 6062 /* *fields */ soc_EGR_HW_CTRL_Q_BUS_BCM56960_A0fmt_fields, 6063 /* bits */ 12, 6064 /* flags */ 0, 6065 }, 6066 #endif /* chips */ 6067 6068 #if defined(BCM_56770_A0) 6069 { /* SOC_FORMAT_INT_EGR_HW_CTRL_Q_BUS_BCM56770_A0fmt */ 6070 /* format EGR_HW_CTRL_Q_BUSfmt */ 6071 /* nFields */ 1, 6072 /* *fields */ soc_EGR_HW_CTRL_Q_BUS_BCM56870_A0fmt_fields, 6073 /* bits */ 12, 6074 /* flags */ 0, 6075 }, 6076 #endif /* chips */ 6077 6078 #if defined(BCM_56850_A0) 6079 { /* SOC_FORMAT_INT_EGR_HW_CTRL_Q_BUS_BCM56850_A0fmt */ 6080 /* format EGR_HW_CTRL_Q_BUSfmt */ 6081 /* nFields */ 2, 6082 /* *fields */ soc_EGR_HW_CTRL_Q_BUS_BCM56850_A0fmt_fields, 6083 /* bits */ 12, 6084 /* flags */ 0, 6085 }, 6086 #endif /* chips */ 6087 6088 #if defined(BCM_56860_A0) 6089 { /* SOC_FORMAT_INT_EGR_HW_CTRL_Q_BUS_BCM56860_A0fmt */ 6090 /* format EGR_HW_CTRL_Q_BUSfmt */ 6091 /* nFields */ 2, 6092 /* *fields */ soc_EGR_HW_CTRL_Q_BUS_BCM56850_A0fmt_fields, 6093 /* bits */ 12, 6094 /* flags */ 0, 6095 }, 6096 #endif /* chips */ 6097 6098 #if defined(BCM_56870_A0) 6099 { /* SOC_FORMAT_INT_EGR_HW_CTRL_Q_BUS_BCM56870_A0fmt */ 6100 /* format EGR_HW_CTRL_Q_BUSfmt */ 6101 /* nFields */ 1, 6102 /* *fields */ soc_EGR_HW_CTRL_Q_BUS_BCM56870_A0fmt_fields, 6103 /* bits */ 12, 6104 /* flags */ 0, 6105 }, 6106 #endif /* chips */ 6107 6108 #if defined(BCM_56960_A0) 6109 { /* SOC_FORMAT_INT_EGR_HW_CTRL_Q_BUS_BCM56960_A0fmt */ 6110 /* format EGR_HW_CTRL_Q_BUSfmt */ 6111 /* nFields */ 2, 6112 /* *fields */ soc_EGR_HW_CTRL_Q_BUS_BCM56960_A0fmt_fields, 6113 /* bits */ 12, 6114 /* flags */ 0, 6115 }, 6116 #endif /* chips */ 6117 6118 #if defined(BCM_56965_A0) 6119 { /* SOC_FORMAT_INT_EGR_HW_CTRL_Q_BUS_BCM56965_A0fmt */ 6120 /* format EGR_HW_CTRL_Q_BUSfmt */ 6121 /* nFields */ 2, 6122 /* *fields */ soc_EGR_HW_CTRL_Q_BUS_BCM56960_A0fmt_fields, 6123 /* bits */ 12, 6124 /* flags */ 0, 6125 }, 6126 #endif /* chips */ 6127 6128 #if defined(BCM_56970_A0) 6129 { /* SOC_FORMAT_INT_EGR_HW_CTRL_Q_BUS_BCM56970_A0fmt */ 6130 /* format EGR_HW_CTRL_Q_BUSfmt */ 6131 /* nFields */ 2, 6132 /* *fields */ soc_EGR_HW_CTRL_Q_BUS_BCM56960_A0fmt_fields, 6133 /* bits */ 12, 6134 /* flags */ 0, 6135 }, 6136 #endif /* chips */ 6137 6138 #if defined(BCM_56980_A0) 6139 { /* SOC_FORMAT_INT_EGR_HW_CTRL_Q_BUS_BCM56980_A0fmt */ 6140 /* format EGR_HW_CTRL_Q_BUSfmt */ 6141 /* nFields */ 2, 6142 /* *fields */ soc_EGR_HW_CTRL_Q_BUS_BCM56960_A0fmt_fields, 6143 /* bits */ 12, 6144 /* flags */ 0, 6145 }, 6146 #endif /* chips */ 6147 6148 #if defined(BCM_56980_B0) 6149 { /* SOC_FORMAT_INT_EGR_HW_CTRL_Q_BUS_BCM56980_B0fmt */ 6150 /* format EGR_HW_CTRL_Q_BUSfmt */ 6151 /* nFields */ 2, 6152 /* *fields */ soc_EGR_HW_CTRL_Q_BUS_BCM56960_A0fmt_fields, 6153 /* bits */ 12, 6154 /* flags */ 0, 6155 }, 6156 #endif /* chips */ 6157 6158 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 6159 defined(BCM_56870_A0) 6160 { /* SOC_FORMAT_INT_EGR_INT_CN_TO_PKT_ECN_MAPPING_INDEXfmt */ 6161 /* format EGR_INT_CN_TO_PKT_ECN_MAPPING_INDEXfmt */ 6162 /* nFields */ 4, 6163 /* *fields */ soc_EGR_INT_CN_TO_PKT_ECN_MAPPING_INDEXfmt_fields, 6164 /* bits */ 9, 6165 /* flags */ 0, 6166 }, 6167 #endif /* chips */ 6168 6169 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 6170 defined(BCM_56870_A0) 6171 { /* SOC_FORMAT_INT_EGR_INT_CN_UPDATE_INDEXfmt */ 6172 /* format EGR_INT_CN_UPDATE_INDEXfmt */ 6173 /* nFields */ 3, 6174 /* *fields */ soc_EGR_INT_CN_UPDATE_INDEXfmt_fields, 6175 /* bits */ 5, 6176 /* flags */ 0, 6177 }, 6178 #endif /* chips */ 6179 6180 #if defined(BCM_56524_A0) || defined(BCM_56624_A0) || \ 6181 defined(BCM_56634_B0) 6182 { /* SOC_FORMAT_INT_EGR_IP_TUNNEL_MPLS_ENTRY_0_3fmt */ 6183 /* format EGR_IP_TUNNEL_MPLS_ENTRY_0_3fmt */ 6184 /* nFields */ 9, 6185 /* *fields */ soc_EGR_IP_TUNNEL_MPLS_ENTRY_0_3fmt_fields, 6186 /* bits */ 40, 6187 /* flags */ 0, 6188 }, 6189 #endif /* chips */ 6190 6191 #if defined(BCM_56560_A0) || defined(BCM_56560_B0) || \ 6192 defined(BCM_56670_A0) || defined(BCM_56670_B0) 6193 { /* SOC_FORMAT_INT_EGR_IP_TUNNEL_MPLS_ENTRY_0_7fmt */ 6194 /* format EGR_IP_TUNNEL_MPLS_ENTRY_0_7fmt */ 6195 /* nFields */ 13, 6196 /* *fields */ soc_EGR_IP_TUNNEL_MPLS_ENTRY_0_7fmt_fields, 6197 /* bits */ 59, 6198 /* flags */ 0, 6199 }, 6200 #endif /* chips */ 6201 6202 #if defined(BCM_56260_A0) 6203 { /* SOC_FORMAT_INT_EGR_IP_TUNNEL_MPLS_ENTRY_0_3_BCM56260_A0fmt */ 6204 /* format EGR_IP_TUNNEL_MPLS_ENTRY_0_3fmt */ 6205 /* nFields */ 9, 6206 /* *fields */ soc_EGR_IP_TUNNEL_MPLS_ENTRY_0_3_BCM56260_A0fmt_fields, 6207 /* bits */ 40, 6208 /* flags */ 0, 6209 }, 6210 #endif /* chips */ 6211 6212 #if defined(BCM_56260_B0) 6213 { /* SOC_FORMAT_INT_EGR_IP_TUNNEL_MPLS_ENTRY_0_3_BCM56260_B0fmt */ 6214 /* format EGR_IP_TUNNEL_MPLS_ENTRY_0_3fmt */ 6215 /* nFields */ 9, 6216 /* *fields */ soc_EGR_IP_TUNNEL_MPLS_ENTRY_0_3_BCM56260_A0fmt_fields, 6217 /* bits */ 40, 6218 /* flags */ 0, 6219 }, 6220 #endif /* chips */ 6221 6222 #if defined(BCM_56270_A0) 6223 { /* SOC_FORMAT_INT_EGR_IP_TUNNEL_MPLS_ENTRY_0_3_BCM56270_A0fmt */ 6224 /* format EGR_IP_TUNNEL_MPLS_ENTRY_0_3fmt */ 6225 /* nFields */ 9, 6226 /* *fields */ soc_EGR_IP_TUNNEL_MPLS_ENTRY_0_3_BCM56260_A0fmt_fields, 6227 /* bits */ 40, 6228 /* flags */ 0, 6229 }, 6230 #endif /* chips */ 6231 6232 #if defined(BCM_56334_A0) 6233 { /* SOC_FORMAT_INT_EGR_IP_TUNNEL_MPLS_ENTRY_0_3_BCM56334_A0fmt */ 6234 /* format EGR_IP_TUNNEL_MPLS_ENTRY_0_3fmt */ 6235 /* nFields */ 9, 6236 /* *fields */ soc_EGR_IP_TUNNEL_MPLS_ENTRY_0_3fmt_fields, 6237 /* bits */ 40, 6238 /* flags */ 0, 6239 }, 6240 #endif /* chips */ 6241 6242 #if defined(BCM_56334_B0) 6243 { /* SOC_FORMAT_INT_EGR_IP_TUNNEL_MPLS_ENTRY_0_3_BCM56334_B0fmt */ 6244 /* format EGR_IP_TUNNEL_MPLS_ENTRY_0_3fmt */ 6245 /* nFields */ 9, 6246 /* *fields */ soc_EGR_IP_TUNNEL_MPLS_ENTRY_0_3fmt_fields, 6247 /* bits */ 40, 6248 /* flags */ 0, 6249 }, 6250 #endif /* chips */ 6251 6252 #if defined(BCM_56340_A0) 6253 { /* SOC_FORMAT_INT_EGR_IP_TUNNEL_MPLS_ENTRY_0_3_BCM56340_A0fmt */ 6254 /* format EGR_IP_TUNNEL_MPLS_ENTRY_0_3fmt */ 6255 /* nFields */ 10, 6256 /* *fields */ soc_EGR_IP_TUNNEL_MPLS_ENTRY_0_3_BCM56640_A0fmt_fields, 6257 /* bits */ 41, 6258 /* flags */ 0, 6259 }, 6260 #endif /* chips */ 6261 6262 #if defined(BCM_56440_A0) 6263 { /* SOC_FORMAT_INT_EGR_IP_TUNNEL_MPLS_ENTRY_0_3_BCM56440_A0fmt */ 6264 /* format EGR_IP_TUNNEL_MPLS_ENTRY_0_3fmt */ 6265 /* nFields */ 9, 6266 /* *fields */ soc_EGR_IP_TUNNEL_MPLS_ENTRY_0_3_BCM56440_A0fmt_fields, 6267 /* bits */ 40, 6268 /* flags */ 0, 6269 }, 6270 #endif /* chips */ 6271 6272 #if defined(BCM_56440_B0) 6273 { /* SOC_FORMAT_INT_EGR_IP_TUNNEL_MPLS_ENTRY_0_3_BCM56440_B0fmt */ 6274 /* format EGR_IP_TUNNEL_MPLS_ENTRY_0_3fmt */ 6275 /* nFields */ 9, 6276 /* *fields */ soc_EGR_IP_TUNNEL_MPLS_ENTRY_0_3_BCM56440_A0fmt_fields, 6277 /* bits */ 40, 6278 /* flags */ 0, 6279 }, 6280 #endif /* chips */ 6281 6282 #if defined(BCM_56450_A0) 6283 { /* SOC_FORMAT_INT_EGR_IP_TUNNEL_MPLS_ENTRY_0_3_BCM56450_A0fmt */ 6284 /* format EGR_IP_TUNNEL_MPLS_ENTRY_0_3fmt */ 6285 /* nFields */ 9, 6286 /* *fields */ soc_EGR_IP_TUNNEL_MPLS_ENTRY_0_3_BCM56450_A0fmt_fields, 6287 /* bits */ 40, 6288 /* flags */ 0, 6289 }, 6290 #endif /* chips */ 6291 6292 #if defined(BCM_56450_B0) 6293 { /* SOC_FORMAT_INT_EGR_IP_TUNNEL_MPLS_ENTRY_0_3_BCM56450_B0fmt */ 6294 /* format EGR_IP_TUNNEL_MPLS_ENTRY_0_3fmt */ 6295 /* nFields */ 9, 6296 /* *fields */ soc_EGR_IP_TUNNEL_MPLS_ENTRY_0_3_BCM56450_A0fmt_fields, 6297 /* bits */ 40, 6298 /* flags */ 0, 6299 }, 6300 #endif /* chips */ 6301 6302 #if defined(BCM_56450_B1) 6303 { /* SOC_FORMAT_INT_EGR_IP_TUNNEL_MPLS_ENTRY_0_3_BCM56450_B1fmt */ 6304 /* format EGR_IP_TUNNEL_MPLS_ENTRY_0_3fmt */ 6305 /* nFields */ 9, 6306 /* *fields */ soc_EGR_IP_TUNNEL_MPLS_ENTRY_0_3_BCM56450_A0fmt_fields, 6307 /* bits */ 40, 6308 /* flags */ 0, 6309 }, 6310 #endif /* chips */ 6311 6312 #if defined(BCM_56524_B0) 6313 { /* SOC_FORMAT_INT_EGR_IP_TUNNEL_MPLS_ENTRY_0_3_BCM56524_B0fmt */ 6314 /* format EGR_IP_TUNNEL_MPLS_ENTRY_0_3fmt */ 6315 /* nFields */ 9, 6316 /* *fields */ soc_EGR_IP_TUNNEL_MPLS_ENTRY_0_3fmt_fields, 6317 /* bits */ 40, 6318 /* flags */ 0, 6319 }, 6320 #endif /* chips */ 6321 6322 #if defined(BCM_56624_B0) 6323 { /* SOC_FORMAT_INT_EGR_IP_TUNNEL_MPLS_ENTRY_0_3_BCM56624_B0fmt */ 6324 /* format EGR_IP_TUNNEL_MPLS_ENTRY_0_3fmt */ 6325 /* nFields */ 9, 6326 /* *fields */ soc_EGR_IP_TUNNEL_MPLS_ENTRY_0_3fmt_fields, 6327 /* bits */ 40, 6328 /* flags */ 0, 6329 }, 6330 #endif /* chips */ 6331 6332 #if defined(BCM_56634_A0) 6333 { /* SOC_FORMAT_INT_EGR_IP_TUNNEL_MPLS_ENTRY_0_3_BCM56634_A0fmt */ 6334 /* format EGR_IP_TUNNEL_MPLS_ENTRY_0_3fmt */ 6335 /* nFields */ 9, 6336 /* *fields */ soc_EGR_IP_TUNNEL_MPLS_ENTRY_0_3fmt_fields, 6337 /* bits */ 40, 6338 /* flags */ 0, 6339 }, 6340 #endif /* chips */ 6341 6342 #if defined(BCM_56640_A0) 6343 { /* SOC_FORMAT_INT_EGR_IP_TUNNEL_MPLS_ENTRY_0_3_BCM56640_A0fmt */ 6344 /* format EGR_IP_TUNNEL_MPLS_ENTRY_0_3fmt */ 6345 /* nFields */ 10, 6346 /* *fields */ soc_EGR_IP_TUNNEL_MPLS_ENTRY_0_3_BCM56640_A0fmt_fields, 6347 /* bits */ 41, 6348 /* flags */ 0, 6349 }, 6350 #endif /* chips */ 6351 6352 #if defined(BCM_56680_A0) 6353 { /* SOC_FORMAT_INT_EGR_IP_TUNNEL_MPLS_ENTRY_0_3_BCM56680_A0fmt */ 6354 /* format EGR_IP_TUNNEL_MPLS_ENTRY_0_3fmt */ 6355 /* nFields */ 9, 6356 /* *fields */ soc_EGR_IP_TUNNEL_MPLS_ENTRY_0_3fmt_fields, 6357 /* bits */ 40, 6358 /* flags */ 0, 6359 }, 6360 #endif /* chips */ 6361 6362 #if defined(BCM_56680_B0) 6363 { /* SOC_FORMAT_INT_EGR_IP_TUNNEL_MPLS_ENTRY_0_3_BCM56680_B0fmt */ 6364 /* format EGR_IP_TUNNEL_MPLS_ENTRY_0_3fmt */ 6365 /* nFields */ 9, 6366 /* *fields */ soc_EGR_IP_TUNNEL_MPLS_ENTRY_0_3fmt_fields, 6367 /* bits */ 40, 6368 /* flags */ 0, 6369 }, 6370 #endif /* chips */ 6371 6372 #if defined(BCM_56685_A0) 6373 { /* SOC_FORMAT_INT_EGR_IP_TUNNEL_MPLS_ENTRY_0_3_BCM56685_A0fmt */ 6374 /* format EGR_IP_TUNNEL_MPLS_ENTRY_0_3fmt */ 6375 /* nFields */ 9, 6376 /* *fields */ soc_EGR_IP_TUNNEL_MPLS_ENTRY_0_3fmt_fields, 6377 /* bits */ 40, 6378 /* flags */ 0, 6379 }, 6380 #endif /* chips */ 6381 6382 #if defined(BCM_56685_B0) 6383 { /* SOC_FORMAT_INT_EGR_IP_TUNNEL_MPLS_ENTRY_0_3_BCM56685_B0fmt */ 6384 /* format EGR_IP_TUNNEL_MPLS_ENTRY_0_3fmt */ 6385 /* nFields */ 9, 6386 /* *fields */ soc_EGR_IP_TUNNEL_MPLS_ENTRY_0_3fmt_fields, 6387 /* bits */ 40, 6388 /* flags */ 0, 6389 }, 6390 #endif /* chips */ 6391 6392 #if defined(BCM_56840_A0) 6393 { /* SOC_FORMAT_INT_EGR_IP_TUNNEL_MPLS_ENTRY_0_3_BCM56840_A0fmt */ 6394 /* format EGR_IP_TUNNEL_MPLS_ENTRY_0_3fmt */ 6395 /* nFields */ 9, 6396 /* *fields */ soc_EGR_IP_TUNNEL_MPLS_ENTRY_0_3fmt_fields, 6397 /* bits */ 40, 6398 /* flags */ 0, 6399 }, 6400 #endif /* chips */ 6401 6402 #if defined(BCM_56840_B0) 6403 { /* SOC_FORMAT_INT_EGR_IP_TUNNEL_MPLS_ENTRY_0_3_BCM56840_B0fmt */ 6404 /* format EGR_IP_TUNNEL_MPLS_ENTRY_0_3fmt */ 6405 /* nFields */ 9, 6406 /* *fields */ soc_EGR_IP_TUNNEL_MPLS_ENTRY_0_3fmt_fields, 6407 /* bits */ 40, 6408 /* flags */ 0, 6409 }, 6410 #endif /* chips */ 6411 6412 #if defined(BCM_56850_A0) 6413 { /* SOC_FORMAT_INT_EGR_IP_TUNNEL_MPLS_ENTRY_0_3_BCM56850_A0fmt */ 6414 /* format EGR_IP_TUNNEL_MPLS_ENTRY_0_3fmt */ 6415 /* nFields */ 9, 6416 /* *fields */ soc_EGR_IP_TUNNEL_MPLS_ENTRY_0_3_BCM56850_A0fmt_fields, 6417 /* bits */ 40, 6418 /* flags */ 0, 6419 }, 6420 #endif /* chips */ 6421 6422 #if defined(BCM_56860_A0) 6423 { /* SOC_FORMAT_INT_EGR_IP_TUNNEL_MPLS_ENTRY_0_3_BCM56860_A0fmt */ 6424 /* format EGR_IP_TUNNEL_MPLS_ENTRY_0_3fmt */ 6425 /* nFields */ 14, 6426 /* *fields */ soc_EGR_IP_TUNNEL_MPLS_ENTRY_0_3_BCM56860_A0fmt_fields, 6427 /* bits */ 59, 6428 /* flags */ 0, 6429 }, 6430 #endif /* chips */ 6431 6432 #if defined(BCM_56960_A0) 6433 { /* SOC_FORMAT_INT_EGR_IP_TUNNEL_MPLS_ENTRY_0_3_BCM56960_A0fmt */ 6434 /* format EGR_IP_TUNNEL_MPLS_ENTRY_0_3fmt */ 6435 /* nFields */ 9, 6436 /* *fields */ soc_EGR_IP_TUNNEL_MPLS_ENTRY_0_3_BCM56960_A0fmt_fields, 6437 /* bits */ 40, 6438 /* flags */ 0, 6439 }, 6440 #endif /* chips */ 6441 6442 #if defined(BCM_56965_A0) 6443 { /* SOC_FORMAT_INT_EGR_IP_TUNNEL_MPLS_ENTRY_0_3_BCM56965_A0fmt */ 6444 /* format EGR_IP_TUNNEL_MPLS_ENTRY_0_3fmt */ 6445 /* nFields */ 9, 6446 /* *fields */ soc_EGR_IP_TUNNEL_MPLS_ENTRY_0_3_BCM56960_A0fmt_fields, 6447 /* bits */ 40, 6448 /* flags */ 0, 6449 }, 6450 #endif /* chips */ 6451 6452 #if defined(BCM_56970_A0) 6453 { /* SOC_FORMAT_INT_EGR_IP_TUNNEL_MPLS_ENTRY_0_7_BCM56970_A0fmt */ 6454 /* format EGR_IP_TUNNEL_MPLS_ENTRY_0_7fmt */ 6455 /* nFields */ 12, 6456 /* *fields */ soc_EGR_IP_TUNNEL_MPLS_ENTRY_0_7_BCM56970_A0fmt_fields, 6457 /* bits */ 45, 6458 /* flags */ 0, 6459 }, 6460 #endif /* chips */ 6461 6462 #if defined(BCM_56980_A0) 6463 { /* SOC_FORMAT_INT_EGR_IP_TUNNEL_MPLS_ENTRY_0_7_BCM56980_A0fmt */ 6464 /* format EGR_IP_TUNNEL_MPLS_ENTRY_0_7fmt */ 6465 /* nFields */ 12, 6466 /* *fields */ soc_EGR_IP_TUNNEL_MPLS_ENTRY_0_7_BCM56970_A0fmt_fields, 6467 /* bits */ 45, 6468 /* flags */ 0, 6469 }, 6470 #endif /* chips */ 6471 6472 #if defined(BCM_56980_B0) 6473 { /* SOC_FORMAT_INT_EGR_IP_TUNNEL_MPLS_ENTRY_0_7_BCM56980_B0fmt */ 6474 /* format EGR_IP_TUNNEL_MPLS_ENTRY_0_7fmt */ 6475 /* nFields */ 12, 6476 /* *fields */ soc_EGR_IP_TUNNEL_MPLS_ENTRY_0_7_BCM56970_A0fmt_fields, 6477 /* bits */ 45, 6478 /* flags */ 0, 6479 }, 6480 #endif /* chips */ 6481 6482 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) 6483 { /* SOC_FORMAT_INT_EGR_IP_TUNNEL_MPLS_ENTRY_FORMATfmt */ 6484 /* format EGR_IP_TUNNEL_MPLS_ENTRY_FORMATfmt */ 6485 /* nFields */ 22, 6486 /* *fields */ soc_EGR_IP_TUNNEL_MPLS_ENTRY_FORMATfmt_fields, 6487 /* bits */ 71, 6488 /* flags */ 0, 6489 }, 6490 #endif /* chips */ 6491 6492 #if defined(BCM_56370_A0) 6493 { /* SOC_FORMAT_INT_EGR_IP_TUNNEL_MPLS_ENTRY_FORMAT_BCM56370_A0fmt */ 6494 /* format EGR_IP_TUNNEL_MPLS_ENTRY_FORMATfmt */ 6495 /* nFields */ 22, 6496 /* *fields */ soc_EGR_IP_TUNNEL_MPLS_ENTRY_FORMAT_BCM56370_A0fmt_fields, 6497 /* bits */ 71, 6498 /* flags */ 0, 6499 }, 6500 #endif /* chips */ 6501 6502 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 6503 defined(BCM_56870_A0) 6504 { /* SOC_FORMAT_INT_EGR_IP_TUNNEL_PDD_OUT_BUSfmt */ 6505 /* format EGR_IP_TUNNEL_PDD_OUT_BUSfmt */ 6506 /* nFields */ 162, 6507 /* *fields */ soc_EGR_IP_TUNNEL_PDD_OUT_BUSfmt_fields, 6508 /* bits */ 1958, 6509 /* flags */ 0, 6510 }, 6511 #endif /* chips */ 6512 6513 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 6514 defined(BCM_56870_A0) 6515 { /* SOC_FORMAT_INT_EGR_ISID_DOT1P_ATTRIBUTESfmt */ 6516 /* format EGR_ISID_DOT1P_ATTRIBUTESfmt */ 6517 /* nFields */ 8, 6518 /* *fields */ soc_EGR_ISID_DOT1P_ATTRIBUTESfmt_fields, 6519 /* bits */ 15, 6520 /* flags */ 0, 6521 }, 6522 #endif /* chips */ 6523 6524 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 6525 defined(BCM_56870_A0) 6526 { /* SOC_FORMAT_INT_EGR_L2_TAG_CONTROL_PROFILE_DEL_INDEXfmt */ 6527 /* format EGR_L2_TAG_CONTROL_PROFILE_DEL_INDEXfmt */ 6528 /* nFields */ 8, 6529 /* *fields */ soc_EGR_L2_TAG_CONTROL_PROFILE_DEL_INDEXfmt_fields, 6530 /* bits */ 9, 6531 /* flags */ 0, 6532 }, 6533 #endif /* chips */ 6534 6535 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 6536 defined(BCM_56870_A0) 6537 { /* SOC_FORMAT_INT_EGR_L2_TAG_CONTROL_PROFILE_INS_INDEXfmt */ 6538 /* format EGR_L2_TAG_CONTROL_PROFILE_INS_INDEXfmt */ 6539 /* nFields */ 8, 6540 /* *fields */ soc_EGR_L2_TAG_CONTROL_PROFILE_INS_INDEXfmt_fields, 6541 /* bits */ 9, 6542 /* flags */ 0, 6543 }, 6544 #endif /* chips */ 6545 6546 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 6547 defined(BCM_56870_A0) 6548 { /* SOC_FORMAT_INT_EGR_L2_TAG_CONTROL_PROFILE_RW_INDEXfmt */ 6549 /* format EGR_L2_TAG_CONTROL_PROFILE_RW_INDEXfmt */ 6550 /* nFields */ 8, 6551 /* *fields */ soc_EGR_L2_TAG_CONTROL_PROFILE_RW_INDEXfmt_fields, 6552 /* bits */ 9, 6553 /* flags */ 0, 6554 }, 6555 #endif /* chips */ 6556 6557 #if defined(BCM_56370_A0) 6558 { /* SOC_FORMAT_INT_EGR_L3_INTF_EARLY_PDD_OUT_BUSfmt */ 6559 /* format EGR_L3_INTF_EARLY_PDD_OUT_BUSfmt */ 6560 /* nFields */ 88, 6561 /* *fields */ soc_EGR_L3_INTF_EARLY_PDD_OUT_BUSfmt_fields, 6562 /* bits */ 75, 6563 /* flags */ 0, 6564 }, 6565 #endif /* chips */ 6566 6567 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) 6568 { /* SOC_FORMAT_INT_EGR_L3_INTF_PDD_OUT_BUSfmt */ 6569 /* format EGR_L3_INTF_PDD_OUT_BUSfmt */ 6570 /* nFields */ 151, 6571 /* *fields */ soc_EGR_L3_INTF_PDD_OUT_BUSfmt_fields, 6572 /* bits */ 1510, 6573 /* flags */ 0, 6574 }, 6575 #endif /* chips */ 6576 6577 #if defined(BCM_56370_A0) 6578 { /* SOC_FORMAT_INT_EGR_L3_INTF_PDD_OUT_BUS_BCM56370_A0fmt */ 6579 /* format EGR_L3_INTF_PDD_OUT_BUSfmt */ 6580 /* nFields */ 151, 6581 /* *fields */ soc_EGR_L3_INTF_PDD_OUT_BUS_BCM56370_A0fmt_fields, 6582 /* bits */ 1510, 6583 /* flags */ 0, 6584 }, 6585 #endif /* chips */ 6586 6587 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 6588 { /* SOC_FORMAT_INT_EGR_L3_NEXT_HOP_COMMON_COV_DEFSfmt */ 6589 /* format EGR_L3_NEXT_HOP_COMMON_COV_DEFSfmt */ 6590 /* nFields */ 8, 6591 /* *fields */ soc_EGR_L3_NEXT_HOP_COMMON_COV_DEFSfmt_fields, 6592 /* bits */ 39, 6593 /* flags */ 0, 6594 }, 6595 #endif /* chips */ 6596 6597 #if defined(BCM_56370_A0) 6598 { /* SOC_FORMAT_INT_EGR_L3_NEXT_HOP_EARLY_PDD_OUT_BUSfmt */ 6599 /* format EGR_L3_NEXT_HOP_EARLY_PDD_OUT_BUSfmt */ 6600 /* nFields */ 88, 6601 /* *fields */ soc_EGR_L3_NEXT_HOP_EARLY_PDD_OUT_BUSfmt_fields, 6602 /* bits */ 60, 6603 /* flags */ 0, 6604 }, 6605 #endif /* chips */ 6606 6607 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) 6608 { /* SOC_FORMAT_INT_EGR_L3_NEXT_HOP_PDD_OUT_BUSfmt */ 6609 /* format EGR_L3_NEXT_HOP_PDD_OUT_BUSfmt */ 6610 /* nFields */ 160, 6611 /* *fields */ soc_EGR_L3_NEXT_HOP_PDD_OUT_BUSfmt_fields, 6612 /* bits */ 1656, 6613 /* flags */ 0, 6614 }, 6615 #endif /* chips */ 6616 6617 #if defined(BCM_56370_A0) 6618 { /* SOC_FORMAT_INT_EGR_L3_NEXT_HOP_PDD_OUT_BUS_BCM56370_A0fmt */ 6619 /* format EGR_L3_NEXT_HOP_PDD_OUT_BUSfmt */ 6620 /* nFields */ 160, 6621 /* *fields */ soc_EGR_L3_NEXT_HOP_PDD_OUT_BUS_BCM56370_A0fmt_fields, 6622 /* bits */ 1655, 6623 /* flags */ 0, 6624 }, 6625 #endif /* chips */ 6626 6627 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 6628 defined(BCM_56870_A0) 6629 { /* SOC_FORMAT_INT_EGR_MPLS_PRI_MAPPING_INDEXfmt */ 6630 /* format EGR_MPLS_PRI_MAPPING_INDEXfmt */ 6631 /* nFields */ 4, 6632 /* *fields */ soc_EGR_MPLS_PRI_MAPPING_INDEXfmt_fields, 6633 /* bits */ 10, 6634 /* flags */ 0, 6635 }, 6636 #endif /* chips */ 6637 6638 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 6639 defined(BCM_56870_A0) 6640 { /* SOC_FORMAT_INT_EGR_NAT_PACKET_EDIT_ACTION_PROFILE_FORMATfmt */ 6641 /* format EGR_NAT_PACKET_EDIT_ACTION_PROFILE_FORMATfmt */ 6642 /* nFields */ 3, 6643 /* *fields */ soc_EGR_NAT_PACKET_EDIT_ACTION_PROFILE_FORMATfmt_fields, 6644 /* bits */ 30, 6645 /* flags */ 0, 6646 }, 6647 #endif /* chips */ 6648 6649 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) 6650 { /* SOC_FORMAT_INT_EGR_NAT_PACKET_EDIT_INFO_FORMATfmt */ 6651 /* format EGR_NAT_PACKET_EDIT_INFO_FORMATfmt */ 6652 /* nFields */ 10, 6653 /* *fields */ soc_EGR_NAT_PACKET_EDIT_INFO_FORMATfmt_fields, 6654 /* bits */ 70, 6655 /* flags */ 0, 6656 }, 6657 #endif /* chips */ 6658 6659 #if defined(BCM_56370_A0) 6660 { /* SOC_FORMAT_INT_EGR_NAT_PACKET_EDIT_INFO_FORMAT_BCM56370_A0fmt */ 6661 /* format EGR_NAT_PACKET_EDIT_INFO_FORMATfmt */ 6662 /* nFields */ 10, 6663 /* *fields */ soc_EGR_NAT_PACKET_EDIT_INFO_FORMAT_BCM56370_A0fmt_fields, 6664 /* bits */ 70, 6665 /* flags */ 0, 6666 }, 6667 #endif /* chips */ 6668 6669 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 6670 defined(BCM_56870_A0) 6671 { /* SOC_FORMAT_INT_EGR_NAT_PACKET_EDIT_PDD_OUT_BUSfmt */ 6672 /* format EGR_NAT_PACKET_EDIT_PDD_OUT_BUSfmt */ 6673 /* nFields */ 114, 6674 /* *fields */ soc_EGR_NAT_PACKET_EDIT_PDD_OUT_BUSfmt_fields, 6675 /* bits */ 935, 6676 /* flags */ 0, 6677 }, 6678 #endif /* chips */ 6679 6680 #if defined(BCM_56640_A0) 6681 { /* SOC_FORMAT_INT_EGR_PERQ_XMT_COUNTERS_COV_DEFSfmt */ 6682 /* format EGR_PERQ_XMT_COUNTERS_COV_DEFSfmt */ 6683 /* nFields */ 6, 6684 /* *fields */ soc_EGR_FRAGMENT_ID_TABLE_COV_DEFSfmt_fields, 6685 /* bits */ 17, 6686 /* flags */ 0, 6687 }, 6688 #endif /* chips */ 6689 6690 #if defined(BCM_53400_A0) 6691 { /* SOC_FORMAT_INT_EGR_PERQ_XMT_COUNTERS_COV_DEFS_BCM53400_A0fmt */ 6692 /* format EGR_PERQ_XMT_COUNTERS_COV_DEFSfmt */ 6693 /* nFields */ 6, 6694 /* *fields */ soc_EGR_PERQ_XMT_COUNTERS_COV_DEFS_BCM53400_A0fmt_fields, 6695 /* bits */ 14, 6696 /* flags */ 0, 6697 }, 6698 #endif /* chips */ 6699 6700 #if defined(BCM_53540_A0) 6701 { /* SOC_FORMAT_INT_EGR_PERQ_XMT_COUNTERS_COV_DEFS_BCM53540_A0fmt */ 6702 /* format EGR_PERQ_XMT_COUNTERS_COV_DEFSfmt */ 6703 /* nFields */ 6, 6704 /* *fields */ soc_EGR_PERQ_XMT_COUNTERS_COV_DEFS_BCM53400_A0fmt_fields, 6705 /* bits */ 14, 6706 /* flags */ 0, 6707 }, 6708 #endif /* chips */ 6709 6710 #if defined(BCM_53570_A0) 6711 { /* SOC_FORMAT_INT_EGR_PERQ_XMT_COUNTERS_COV_DEFS_BCM53570_A0fmt */ 6712 /* format EGR_PERQ_XMT_COUNTERS_COV_DEFSfmt */ 6713 /* nFields */ 6, 6714 /* *fields */ soc_EGR_PERQ_XMT_COUNTERS_COV_DEFS_BCM53400_A0fmt_fields, 6715 /* bits */ 14, 6716 /* flags */ 0, 6717 }, 6718 #endif /* chips */ 6719 6720 #if defined(BCM_53570_B0) 6721 { /* SOC_FORMAT_INT_EGR_PERQ_XMT_COUNTERS_COV_DEFS_BCM53570_B0fmt */ 6722 /* format EGR_PERQ_XMT_COUNTERS_COV_DEFSfmt */ 6723 /* nFields */ 6, 6724 /* *fields */ soc_EGR_PERQ_XMT_COUNTERS_COV_DEFS_BCM53400_A0fmt_fields, 6725 /* bits */ 14, 6726 /* flags */ 0, 6727 }, 6728 #endif /* chips */ 6729 6730 #if defined(BCM_56150_A0) 6731 { /* SOC_FORMAT_INT_EGR_PERQ_XMT_COUNTERS_COV_DEFS_BCM56150_A0fmt */ 6732 /* format EGR_PERQ_XMT_COUNTERS_COV_DEFSfmt */ 6733 /* nFields */ 6, 6734 /* *fields */ soc_EGR_PERQ_XMT_COUNTERS_COV_DEFSfmt_fields, 6735 /* bits */ 14, 6736 /* flags */ 0, 6737 }, 6738 #endif /* chips */ 6739 6740 #if defined(BCM_56160_A0) 6741 { /* SOC_FORMAT_INT_EGR_PERQ_XMT_COUNTERS_COV_DEFS_BCM56160_A0fmt */ 6742 /* format EGR_PERQ_XMT_COUNTERS_COV_DEFSfmt */ 6743 /* nFields */ 6, 6744 /* *fields */ soc_EGR_PERQ_XMT_COUNTERS_COV_DEFS_BCM53400_A0fmt_fields, 6745 /* bits */ 14, 6746 /* flags */ 0, 6747 }, 6748 #endif /* chips */ 6749 6750 #if defined(BCM_56340_A0) 6751 { /* SOC_FORMAT_INT_EGR_PERQ_XMT_COUNTERS_COV_DEFS_BCM56340_A0fmt */ 6752 /* format EGR_PERQ_XMT_COUNTERS_COV_DEFSfmt */ 6753 /* nFields */ 6, 6754 /* *fields */ soc_EGR_FRAGMENT_ID_TABLE_COV_DEFSfmt_fields, 6755 /* bits */ 17, 6756 /* flags */ 0, 6757 }, 6758 #endif /* chips */ 6759 6760 #if defined(BCM_56370_A0) 6761 { /* SOC_FORMAT_INT_EGR_PERQ_XMT_COUNTERS_COV_DEFS_BCM56370_A0fmt */ 6762 /* format EGR_PERQ_XMT_COUNTERS_COV_DEFSfmt */ 6763 /* nFields */ 6, 6764 /* *fields */ soc_EGR_PERQ_XMT_COUNTERS_COV_DEFS_BCM56960_A0fmt_fields, 6765 /* bits */ 17, 6766 /* flags */ 0, 6767 }, 6768 #endif /* chips */ 6769 6770 #if defined(BCM_56560_A0) 6771 { /* SOC_FORMAT_INT_EGR_PERQ_XMT_COUNTERS_COV_DEFS_BCM56560_A0fmt */ 6772 /* format EGR_PERQ_XMT_COUNTERS_COV_DEFSfmt */ 6773 /* nFields */ 6, 6774 /* *fields */ soc_EGR_PERQ_XMT_COUNTERS_COV_DEFS_BCM56960_A0fmt_fields, 6775 /* bits */ 17, 6776 /* flags */ 0, 6777 }, 6778 #endif /* chips */ 6779 6780 #if defined(BCM_56560_B0) 6781 { /* SOC_FORMAT_INT_EGR_PERQ_XMT_COUNTERS_COV_DEFS_BCM56560_B0fmt */ 6782 /* format EGR_PERQ_XMT_COUNTERS_COV_DEFSfmt */ 6783 /* nFields */ 6, 6784 /* *fields */ soc_EGR_PERQ_XMT_COUNTERS_COV_DEFS_BCM56960_A0fmt_fields, 6785 /* bits */ 17, 6786 /* flags */ 0, 6787 }, 6788 #endif /* chips */ 6789 6790 #if defined(BCM_56670_A0) 6791 { /* SOC_FORMAT_INT_EGR_PERQ_XMT_COUNTERS_COV_DEFS_BCM56670_A0fmt */ 6792 /* format EGR_PERQ_XMT_COUNTERS_COV_DEFSfmt */ 6793 /* nFields */ 6, 6794 /* *fields */ soc_EGR_PERQ_XMT_COUNTERS_COV_DEFS_BCM56960_A0fmt_fields, 6795 /* bits */ 17, 6796 /* flags */ 0, 6797 }, 6798 #endif /* chips */ 6799 6800 #if defined(BCM_56670_B0) 6801 { /* SOC_FORMAT_INT_EGR_PERQ_XMT_COUNTERS_COV_DEFS_BCM56670_B0fmt */ 6802 /* format EGR_PERQ_XMT_COUNTERS_COV_DEFSfmt */ 6803 /* nFields */ 6, 6804 /* *fields */ soc_EGR_PERQ_XMT_COUNTERS_COV_DEFS_BCM56960_A0fmt_fields, 6805 /* bits */ 17, 6806 /* flags */ 0, 6807 }, 6808 #endif /* chips */ 6809 6810 #if defined(BCM_56770_A0) 6811 { /* SOC_FORMAT_INT_EGR_PERQ_XMT_COUNTERS_COV_DEFS_BCM56770_A0fmt */ 6812 /* format EGR_PERQ_XMT_COUNTERS_COV_DEFSfmt */ 6813 /* nFields */ 6, 6814 /* *fields */ soc_EGR_PERQ_XMT_COUNTERS_COV_DEFS_BCM56960_A0fmt_fields, 6815 /* bits */ 17, 6816 /* flags */ 0, 6817 }, 6818 #endif /* chips */ 6819 6820 #if defined(BCM_56850_A0) 6821 { /* SOC_FORMAT_INT_EGR_PERQ_XMT_COUNTERS_COV_DEFS_BCM56850_A0fmt */ 6822 /* format EGR_PERQ_XMT_COUNTERS_COV_DEFSfmt */ 6823 /* nFields */ 6, 6824 /* *fields */ soc_EGR_FRAGMENT_ID_TABLE_COV_DEFSfmt_fields, 6825 /* bits */ 17, 6826 /* flags */ 0, 6827 }, 6828 #endif /* chips */ 6829 6830 #if defined(BCM_56860_A0) 6831 { /* SOC_FORMAT_INT_EGR_PERQ_XMT_COUNTERS_COV_DEFS_BCM56860_A0fmt */ 6832 /* format EGR_PERQ_XMT_COUNTERS_COV_DEFSfmt */ 6833 /* nFields */ 6, 6834 /* *fields */ soc_EGR_FRAGMENT_ID_TABLE_COV_DEFSfmt_fields, 6835 /* bits */ 17, 6836 /* flags */ 0, 6837 }, 6838 #endif /* chips */ 6839 6840 #if defined(BCM_56870_A0) 6841 { /* SOC_FORMAT_INT_EGR_PERQ_XMT_COUNTERS_COV_DEFS_BCM56870_A0fmt */ 6842 /* format EGR_PERQ_XMT_COUNTERS_COV_DEFSfmt */ 6843 /* nFields */ 6, 6844 /* *fields */ soc_EGR_PERQ_XMT_COUNTERS_COV_DEFS_BCM56960_A0fmt_fields, 6845 /* bits */ 17, 6846 /* flags */ 0, 6847 }, 6848 #endif /* chips */ 6849 6850 #if defined(BCM_56960_A0) 6851 { /* SOC_FORMAT_INT_EGR_PERQ_XMT_COUNTERS_COV_DEFS_BCM56960_A0fmt */ 6852 /* format EGR_PERQ_XMT_COUNTERS_COV_DEFSfmt */ 6853 /* nFields */ 6, 6854 /* *fields */ soc_EGR_PERQ_XMT_COUNTERS_COV_DEFS_BCM56960_A0fmt_fields, 6855 /* bits */ 17, 6856 /* flags */ 0, 6857 }, 6858 #endif /* chips */ 6859 6860 #if defined(BCM_56965_A0) 6861 { /* SOC_FORMAT_INT_EGR_PERQ_XMT_COUNTERS_COV_DEFS_BCM56965_A0fmt */ 6862 /* format EGR_PERQ_XMT_COUNTERS_COV_DEFSfmt */ 6863 /* nFields */ 6, 6864 /* *fields */ soc_EGR_PERQ_XMT_COUNTERS_COV_DEFS_BCM56960_A0fmt_fields, 6865 /* bits */ 17, 6866 /* flags */ 0, 6867 }, 6868 #endif /* chips */ 6869 6870 #if defined(BCM_56970_A0) 6871 { /* SOC_FORMAT_INT_EGR_PERQ_XMT_COUNTERS_COV_DEFS_BCM56970_A0fmt */ 6872 /* format EGR_PERQ_XMT_COUNTERS_COV_DEFSfmt */ 6873 /* nFields */ 6, 6874 /* *fields */ soc_L3_ECMP_GROUP_A_RRLB_CNT_COV_DEFSfmt_fields, 6875 /* bits */ 18, 6876 /* flags */ 0, 6877 }, 6878 #endif /* chips */ 6879 6880 #if defined(BCM_56980_A0) 6881 { /* SOC_FORMAT_INT_EGR_PERQ_XMT_COUNTERS_COV_DEFS_BCM56980_A0fmt */ 6882 /* format EGR_PERQ_XMT_COUNTERS_COV_DEFSfmt */ 6883 /* nFields */ 6, 6884 /* *fields */ soc_L3_ECMP_GROUP_A_RRLB_CNT_COV_DEFSfmt_fields, 6885 /* bits */ 18, 6886 /* flags */ 0, 6887 }, 6888 #endif /* chips */ 6889 6890 #if defined(BCM_56980_B0) 6891 { /* SOC_FORMAT_INT_EGR_PERQ_XMT_COUNTERS_COV_DEFS_BCM56980_B0fmt */ 6892 /* format EGR_PERQ_XMT_COUNTERS_COV_DEFSfmt */ 6893 /* nFields */ 6, 6894 /* *fields */ soc_L3_ECMP_GROUP_A_RRLB_CNT_COV_DEFSfmt_fields, 6895 /* bits */ 18, 6896 /* flags */ 0, 6897 }, 6898 #endif /* chips */ 6899 6900 #if defined(BCM_56670_A0) || defined(BCM_56670_B0) 6901 { /* SOC_FORMAT_INT_EGR_PIPE_PKTINFOfmt */ 6902 /* format EGR_PIPE_PKTINFOfmt */ 6903 /* nFields */ 5, 6904 /* *fields */ soc_EGR_PIPE_PKTINFOfmt_fields, 6905 /* bits */ 11, 6906 /* flags */ 0, 6907 }, 6908 #endif /* chips */ 6909 6910 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 6911 defined(BCM_56870_A0) 6912 { /* SOC_FORMAT_INT_EGR_PKT_ECN_TO_EXP_MAPPING_INDEXfmt */ 6913 /* format EGR_PKT_ECN_TO_EXP_MAPPING_INDEXfmt */ 6914 /* nFields */ 4, 6915 /* *fields */ soc_EGR_PKT_ECN_TO_EXP_MAPPING_INDEXfmt_fields, 6916 /* bits */ 8, 6917 /* flags */ 0, 6918 }, 6919 #endif /* chips */ 6920 6921 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 6922 defined(BCM_56870_A0) 6923 { /* SOC_FORMAT_INT_EGR_PKT_FLOW_SELECT_TCAM_DOP_DOPfmt */ 6924 /* format EGR_PKT_FLOW_SELECT_TCAM_DOP_DOPfmt */ 6925 /* nFields */ 4, 6926 /* *fields */ soc_EGR_PKT_FLOW_SELECT_TCAM_DOP_DOPfmt_fields, 6927 /* bits */ 32, 6928 /* flags */ 0, 6929 }, 6930 #endif /* chips */ 6931 6932 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 6933 defined(BCM_56870_A0) 6934 { /* SOC_FORMAT_INT_EGR_PKT_FLOW_SELECT_TCAM_INDEX_DOP_DOPfmt */ 6935 /* format EGR_PKT_FLOW_SELECT_TCAM_INDEX_DOP_DOPfmt */ 6936 /* nFields */ 3, 6937 /* *fields */ soc_EGR_PKT_FLOW_SELECT_TCAM_INDEX_DOP_DOPfmt_fields, 6938 /* bits */ 32, 6939 /* flags */ 0, 6940 }, 6941 #endif /* chips */ 6942 6943 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 6944 defined(BCM_56870_A0) 6945 { /* SOC_FORMAT_INT_EGR_PKT_FLOW_ZONE_SELECT_FORMATfmt */ 6946 /* format EGR_PKT_FLOW_ZONE_SELECT_FORMATfmt */ 6947 /* nFields */ 9, 6948 /* *fields */ soc_EGR_PKT_FLOW_ZONE_SELECT_FORMATfmt_fields, 6949 /* bits */ 27, 6950 /* flags */ 0, 6951 }, 6952 #endif /* chips */ 6953 6954 #if defined(BCM_56670_A0) || defined(BCM_56670_B0) 6955 { /* SOC_FORMAT_INT_EGR_PREEMPT_PKT_LEN_MEMfmt */ 6956 /* format EGR_PREEMPT_PKT_LEN_MEMfmt */ 6957 /* nFields */ 5, 6958 /* *fields */ soc_EGR_PREEMPT_PKT_LEN_MEMfmt_fields, 6959 /* bits */ 24, 6960 /* flags */ 0, 6961 }, 6962 #endif /* chips */ 6963 6964 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 6965 defined(BCM_56870_A0) 6966 { /* SOC_FORMAT_INT_EGR_QOS_CTRL_TCAM_DOP_DOPfmt */ 6967 /* format EGR_QOS_CTRL_TCAM_DOP_DOPfmt */ 6968 /* nFields */ 4, 6969 /* *fields */ soc_EGR_QOS_CTRL_TCAM_DOP_DOPfmt_fields, 6970 /* bits */ 32, 6971 /* flags */ 0, 6972 }, 6973 #endif /* chips */ 6974 6975 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 6976 defined(BCM_56870_A0) 6977 { /* SOC_FORMAT_INT_EGR_SEQUENCE_NUMBER_TABLE_COV_DEFSfmt */ 6978 /* format EGR_SEQUENCE_NUMBER_TABLE_COV_DEFSfmt */ 6979 /* nFields */ 6, 6980 /* *fields */ soc_EGR_SEQUENCE_NUMBER_TABLE_COV_DEFSfmt_fields, 6981 /* bits */ 20, 6982 /* flags */ 0, 6983 }, 6984 #endif /* chips */ 6985 6986 #if defined(BCM_56314_A0) || defined(BCM_56504_B0) 6987 { /* SOC_FORMAT_INT_EGR_SHAPEfmt */ 6988 /* format EGR_SHAPEfmt */ 6989 /* nFields */ 3, 6990 /* *fields */ soc_EGR_SHAPEfmt_fields, 6991 /* bits */ 16, 6992 /* flags */ 0, 6993 }, 6994 #endif /* chips */ 6995 6996 #if defined(BCM_53314_A0) 6997 { /* SOC_FORMAT_INT_EGR_SHAPE_BCM53314_A0fmt */ 6998 /* format EGR_SHAPEfmt */ 6999 /* nFields */ 3, 7000 /* *fields */ soc_EGR_SHAPE_BCM56224_A0fmt_fields, 7001 /* bits */ 17, 7002 /* flags */ 0, 7003 }, 7004 #endif /* chips */ 7005 7006 #if defined(BCM_53324_A0) 7007 { /* SOC_FORMAT_INT_EGR_SHAPE_BCM53324_A0fmt */ 7008 /* format EGR_SHAPEfmt */ 7009 /* nFields */ 3, 7010 /* *fields */ soc_EGR_SHAPE_BCM56224_A0fmt_fields, 7011 /* bits */ 17, 7012 /* flags */ 0, 7013 }, 7014 #endif /* chips */ 7015 7016 #if defined(BCM_53400_A0) 7017 { /* SOC_FORMAT_INT_EGR_SHAPE_BCM53400_A0fmt */ 7018 /* format EGR_SHAPEfmt */ 7019 /* nFields */ 5, 7020 /* *fields */ soc_EGR_SHAPE_BCM53400_A0fmt_fields, 7021 /* bits */ 22, 7022 /* flags */ 0, 7023 }, 7024 #endif /* chips */ 7025 7026 #if defined(BCM_53540_A0) 7027 { /* SOC_FORMAT_INT_EGR_SHAPE_BCM53540_A0fmt */ 7028 /* format EGR_SHAPEfmt */ 7029 /* nFields */ 5, 7030 /* *fields */ soc_EGR_SHAPE_BCM53400_A0fmt_fields, 7031 /* bits */ 22, 7032 /* flags */ 0, 7033 }, 7034 #endif /* chips */ 7035 7036 #if defined(BCM_53570_A0) 7037 { /* SOC_FORMAT_INT_EGR_SHAPE_BCM53570_A0fmt */ 7038 /* format EGR_SHAPEfmt */ 7039 /* nFields */ 5, 7040 /* *fields */ soc_EGR_SHAPE_BCM53570_A0fmt_fields, 7041 /* bits */ 24, 7042 /* flags */ 0, 7043 }, 7044 #endif /* chips */ 7045 7046 #if defined(BCM_53570_B0) 7047 { /* SOC_FORMAT_INT_EGR_SHAPE_BCM53570_B0fmt */ 7048 /* format EGR_SHAPEfmt */ 7049 /* nFields */ 5, 7050 /* *fields */ soc_EGR_SHAPE_BCM53570_A0fmt_fields, 7051 /* bits */ 24, 7052 /* flags */ 0, 7053 }, 7054 #endif /* chips */ 7055 7056 #if defined(BCM_56142_A0) 7057 { /* SOC_FORMAT_INT_EGR_SHAPE_BCM56142_A0fmt */ 7058 /* format EGR_SHAPEfmt */ 7059 /* nFields */ 4, 7060 /* *fields */ soc_EGR_SHAPE_BCM56142_A0fmt_fields, 7061 /* bits */ 21, 7062 /* flags */ 0, 7063 }, 7064 #endif /* chips */ 7065 7066 #if defined(BCM_56150_A0) 7067 { /* SOC_FORMAT_INT_EGR_SHAPE_BCM56150_A0fmt */ 7068 /* format EGR_SHAPEfmt */ 7069 /* nFields */ 5, 7070 /* *fields */ soc_EGR_SHAPE_BCM56150_A0fmt_fields, 7071 /* bits */ 22, 7072 /* flags */ 0, 7073 }, 7074 #endif /* chips */ 7075 7076 #if defined(BCM_56160_A0) 7077 { /* SOC_FORMAT_INT_EGR_SHAPE_BCM56160_A0fmt */ 7078 /* format EGR_SHAPEfmt */ 7079 /* nFields */ 5, 7080 /* *fields */ soc_EGR_SHAPE_BCM53400_A0fmt_fields, 7081 /* bits */ 22, 7082 /* flags */ 0, 7083 }, 7084 #endif /* chips */ 7085 7086 #if defined(BCM_56224_A0) 7087 { /* SOC_FORMAT_INT_EGR_SHAPE_BCM56224_A0fmt */ 7088 /* format EGR_SHAPEfmt */ 7089 /* nFields */ 3, 7090 /* *fields */ soc_EGR_SHAPE_BCM56224_A0fmt_fields, 7091 /* bits */ 17, 7092 /* flags */ 0, 7093 }, 7094 #endif /* chips */ 7095 7096 #if defined(BCM_56224_B0) 7097 { /* SOC_FORMAT_INT_EGR_SHAPE_BCM56224_B0fmt */ 7098 /* format EGR_SHAPEfmt */ 7099 /* nFields */ 3, 7100 /* *fields */ soc_EGR_SHAPE_BCM56224_A0fmt_fields, 7101 /* bits */ 17, 7102 /* flags */ 0, 7103 }, 7104 #endif /* chips */ 7105 7106 #if defined(BCM_56260_A0) 7107 { /* SOC_FORMAT_INT_EGR_SHAPE_BCM56260_A0fmt */ 7108 /* format EGR_SHAPEfmt */ 7109 /* nFields */ 8, 7110 /* *fields */ soc_EGR_SHAPE_BCM56260_A0fmt_fields, 7111 /* bits */ 56, 7112 /* flags */ 0, 7113 }, 7114 #endif /* chips */ 7115 7116 #if defined(BCM_56260_B0) 7117 { /* SOC_FORMAT_INT_EGR_SHAPE_BCM56260_B0fmt */ 7118 /* format EGR_SHAPEfmt */ 7119 /* nFields */ 8, 7120 /* *fields */ soc_EGR_SHAPE_BCM56260_A0fmt_fields, 7121 /* bits */ 56, 7122 /* flags */ 0, 7123 }, 7124 #endif /* chips */ 7125 7126 #if defined(BCM_56270_A0) 7127 { /* SOC_FORMAT_INT_EGR_SHAPE_BCM56270_A0fmt */ 7128 /* format EGR_SHAPEfmt */ 7129 /* nFields */ 8, 7130 /* *fields */ soc_EGR_SHAPE_BCM56270_A0fmt_fields, 7131 /* bits */ 54, 7132 /* flags */ 0, 7133 }, 7134 #endif /* chips */ 7135 7136 #if defined(BCM_56334_A0) 7137 { /* SOC_FORMAT_INT_EGR_SHAPE_BCM56334_A0fmt */ 7138 /* format EGR_SHAPEfmt */ 7139 /* nFields */ 5, 7140 /* *fields */ soc_EGR_SHAPE_BCM56624_A0fmt_fields, 7141 /* bits */ 23, 7142 /* flags */ 0, 7143 }, 7144 #endif /* chips */ 7145 7146 #if defined(BCM_56334_B0) 7147 { /* SOC_FORMAT_INT_EGR_SHAPE_BCM56334_B0fmt */ 7148 /* format EGR_SHAPEfmt */ 7149 /* nFields */ 5, 7150 /* *fields */ soc_EGR_SHAPE_BCM56624_A0fmt_fields, 7151 /* bits */ 23, 7152 /* flags */ 0, 7153 }, 7154 #endif /* chips */ 7155 7156 #if defined(BCM_56340_A0) 7157 { /* SOC_FORMAT_INT_EGR_SHAPE_BCM56340_A0fmt */ 7158 /* format EGR_SHAPEfmt */ 7159 /* nFields */ 11, 7160 /* *fields */ soc_EGR_SHAPE_BCM56640_A0fmt_fields, 7161 /* bits */ 55, 7162 /* flags */ 0, 7163 }, 7164 #endif /* chips */ 7165 7166 #if defined(BCM_56370_A0) 7167 { /* SOC_FORMAT_INT_EGR_SHAPE_BCM56370_A0fmt */ 7168 /* format EGR_SHAPEfmt */ 7169 /* nFields */ 9, 7170 /* *fields */ soc_EGR_SHAPE_BCM56370_A0fmt_fields, 7171 /* bits */ 41, 7172 /* flags */ 0, 7173 }, 7174 #endif /* chips */ 7175 7176 #if defined(BCM_56440_A0) 7177 { /* SOC_FORMAT_INT_EGR_SHAPE_BCM56440_A0fmt */ 7178 /* format EGR_SHAPEfmt */ 7179 /* nFields */ 9, 7180 /* *fields */ soc_EGR_SHAPE_BCM56440_A0fmt_fields, 7181 /* bits */ 51, 7182 /* flags */ 0, 7183 }, 7184 #endif /* chips */ 7185 7186 #if defined(BCM_56440_B0) 7187 { /* SOC_FORMAT_INT_EGR_SHAPE_BCM56440_B0fmt */ 7188 /* format EGR_SHAPEfmt */ 7189 /* nFields */ 9, 7190 /* *fields */ soc_EGR_SHAPE_BCM56440_A0fmt_fields, 7191 /* bits */ 51, 7192 /* flags */ 0, 7193 }, 7194 #endif /* chips */ 7195 7196 #if defined(BCM_56450_A0) 7197 { /* SOC_FORMAT_INT_EGR_SHAPE_BCM56450_A0fmt */ 7198 /* format EGR_SHAPEfmt */ 7199 /* nFields */ 11, 7200 /* *fields */ soc_EGR_SHAPE_BCM56450_A0fmt_fields, 7201 /* bits */ 56, 7202 /* flags */ 0, 7203 }, 7204 #endif /* chips */ 7205 7206 #if defined(BCM_56450_B0) 7207 { /* SOC_FORMAT_INT_EGR_SHAPE_BCM56450_B0fmt */ 7208 /* format EGR_SHAPEfmt */ 7209 /* nFields */ 11, 7210 /* *fields */ soc_EGR_SHAPE_BCM56450_A0fmt_fields, 7211 /* bits */ 56, 7212 /* flags */ 0, 7213 }, 7214 #endif /* chips */ 7215 7216 #if defined(BCM_56450_B1) 7217 { /* SOC_FORMAT_INT_EGR_SHAPE_BCM56450_B1fmt */ 7218 /* format EGR_SHAPEfmt */ 7219 /* nFields */ 11, 7220 /* *fields */ soc_EGR_SHAPE_BCM56450_A0fmt_fields, 7221 /* bits */ 56, 7222 /* flags */ 0, 7223 }, 7224 #endif /* chips */ 7225 7226 #if defined(BCM_56514_A0) 7227 { /* SOC_FORMAT_INT_EGR_SHAPE_BCM56514_A0fmt */ 7228 /* format EGR_SHAPEfmt */ 7229 /* nFields */ 3, 7230 /* *fields */ soc_EGR_SHAPEfmt_fields, 7231 /* bits */ 16, 7232 /* flags */ 0, 7233 }, 7234 #endif /* chips */ 7235 7236 #if defined(BCM_56524_A0) 7237 { /* SOC_FORMAT_INT_EGR_SHAPE_BCM56524_A0fmt */ 7238 /* format EGR_SHAPEfmt */ 7239 /* nFields */ 5, 7240 /* *fields */ soc_EGR_SHAPE_BCM56634_A0fmt_fields, 7241 /* bits */ 24, 7242 /* flags */ 0, 7243 }, 7244 #endif /* chips */ 7245 7246 #if defined(BCM_56524_B0) 7247 { /* SOC_FORMAT_INT_EGR_SHAPE_BCM56524_B0fmt */ 7248 /* format EGR_SHAPEfmt */ 7249 /* nFields */ 5, 7250 /* *fields */ soc_EGR_SHAPE_BCM56634_A0fmt_fields, 7251 /* bits */ 24, 7252 /* flags */ 0, 7253 }, 7254 #endif /* chips */ 7255 7256 #if defined(BCM_56560_A0) 7257 { /* SOC_FORMAT_INT_EGR_SHAPE_BCM56560_A0fmt */ 7258 /* format EGR_SHAPEfmt */ 7259 /* nFields */ 8, 7260 /* *fields */ soc_EGR_SHAPE_BCM56560_A0fmt_fields, 7261 /* bits */ 72, 7262 /* flags */ 0, 7263 }, 7264 #endif /* chips */ 7265 7266 #if defined(BCM_56560_B0) 7267 { /* SOC_FORMAT_INT_EGR_SHAPE_BCM56560_B0fmt */ 7268 /* format EGR_SHAPEfmt */ 7269 /* nFields */ 8, 7270 /* *fields */ soc_EGR_SHAPE_BCM56560_A0fmt_fields, 7271 /* bits */ 72, 7272 /* flags */ 0, 7273 }, 7274 #endif /* chips */ 7275 7276 #if defined(BCM_56624_A0) 7277 { /* SOC_FORMAT_INT_EGR_SHAPE_BCM56624_A0fmt */ 7278 /* format EGR_SHAPEfmt */ 7279 /* nFields */ 5, 7280 /* *fields */ soc_EGR_SHAPE_BCM56624_A0fmt_fields, 7281 /* bits */ 23, 7282 /* flags */ 0, 7283 }, 7284 #endif /* chips */ 7285 7286 #if defined(BCM_56624_B0) 7287 { /* SOC_FORMAT_INT_EGR_SHAPE_BCM56624_B0fmt */ 7288 /* format EGR_SHAPEfmt */ 7289 /* nFields */ 5, 7290 /* *fields */ soc_EGR_SHAPE_BCM56624_A0fmt_fields, 7291 /* bits */ 23, 7292 /* flags */ 0, 7293 }, 7294 #endif /* chips */ 7295 7296 #if defined(BCM_56634_A0) 7297 { /* SOC_FORMAT_INT_EGR_SHAPE_BCM56634_A0fmt */ 7298 /* format EGR_SHAPEfmt */ 7299 /* nFields */ 5, 7300 /* *fields */ soc_EGR_SHAPE_BCM56634_A0fmt_fields, 7301 /* bits */ 24, 7302 /* flags */ 0, 7303 }, 7304 #endif /* chips */ 7305 7306 #if defined(BCM_56634_B0) 7307 { /* SOC_FORMAT_INT_EGR_SHAPE_BCM56634_B0fmt */ 7308 /* format EGR_SHAPEfmt */ 7309 /* nFields */ 5, 7310 /* *fields */ soc_EGR_SHAPE_BCM56634_A0fmt_fields, 7311 /* bits */ 24, 7312 /* flags */ 0, 7313 }, 7314 #endif /* chips */ 7315 7316 #if defined(BCM_56640_A0) 7317 { /* SOC_FORMAT_INT_EGR_SHAPE_BCM56640_A0fmt */ 7318 /* format EGR_SHAPEfmt */ 7319 /* nFields */ 11, 7320 /* *fields */ soc_EGR_SHAPE_BCM56640_A0fmt_fields, 7321 /* bits */ 55, 7322 /* flags */ 0, 7323 }, 7324 #endif /* chips */ 7325 7326 #if defined(BCM_56670_A0) 7327 { /* SOC_FORMAT_INT_EGR_SHAPE_BCM56670_A0fmt */ 7328 /* format EGR_SHAPEfmt */ 7329 /* nFields */ 8, 7330 /* *fields */ soc_EGR_SHAPE_BCM56560_A0fmt_fields, 7331 /* bits */ 72, 7332 /* flags */ 0, 7333 }, 7334 #endif /* chips */ 7335 7336 #if defined(BCM_56670_B0) 7337 { /* SOC_FORMAT_INT_EGR_SHAPE_BCM56670_B0fmt */ 7338 /* format EGR_SHAPEfmt */ 7339 /* nFields */ 8, 7340 /* *fields */ soc_EGR_SHAPE_BCM56560_A0fmt_fields, 7341 /* bits */ 72, 7342 /* flags */ 0, 7343 }, 7344 #endif /* chips */ 7345 7346 #if defined(BCM_56680_A0) 7347 { /* SOC_FORMAT_INT_EGR_SHAPE_BCM56680_A0fmt */ 7348 /* format EGR_SHAPEfmt */ 7349 /* nFields */ 5, 7350 /* *fields */ soc_EGR_SHAPE_BCM56624_A0fmt_fields, 7351 /* bits */ 23, 7352 /* flags */ 0, 7353 }, 7354 #endif /* chips */ 7355 7356 #if defined(BCM_56680_B0) 7357 { /* SOC_FORMAT_INT_EGR_SHAPE_BCM56680_B0fmt */ 7358 /* format EGR_SHAPEfmt */ 7359 /* nFields */ 5, 7360 /* *fields */ soc_EGR_SHAPE_BCM56624_A0fmt_fields, 7361 /* bits */ 23, 7362 /* flags */ 0, 7363 }, 7364 #endif /* chips */ 7365 7366 #if defined(BCM_56685_A0) 7367 { /* SOC_FORMAT_INT_EGR_SHAPE_BCM56685_A0fmt */ 7368 /* format EGR_SHAPEfmt */ 7369 /* nFields */ 5, 7370 /* *fields */ soc_EGR_SHAPE_BCM56634_A0fmt_fields, 7371 /* bits */ 24, 7372 /* flags */ 0, 7373 }, 7374 #endif /* chips */ 7375 7376 #if defined(BCM_56685_B0) 7377 { /* SOC_FORMAT_INT_EGR_SHAPE_BCM56685_B0fmt */ 7378 /* format EGR_SHAPEfmt */ 7379 /* nFields */ 5, 7380 /* *fields */ soc_EGR_SHAPE_BCM56634_A0fmt_fields, 7381 /* bits */ 24, 7382 /* flags */ 0, 7383 }, 7384 #endif /* chips */ 7385 7386 #if defined(BCM_56725_A0) 7387 { /* SOC_FORMAT_INT_EGR_SHAPE_BCM56725_A0fmt */ 7388 /* format EGR_SHAPEfmt */ 7389 /* nFields */ 5, 7390 /* *fields */ soc_EGR_SHAPE_BCM56820_A0fmt_fields, 7391 /* bits */ 20, 7392 /* flags */ 0, 7393 }, 7394 #endif /* chips */ 7395 7396 #if defined(BCM_56770_A0) 7397 { /* SOC_FORMAT_INT_EGR_SHAPE_BCM56770_A0fmt */ 7398 /* format EGR_SHAPEfmt */ 7399 /* nFields */ 9, 7400 /* *fields */ soc_EGR_SHAPE_BCM56870_A0fmt_fields, 7401 /* bits */ 40, 7402 /* flags */ 0, 7403 }, 7404 #endif /* chips */ 7405 7406 #if defined(BCM_56800_A0) 7407 { /* SOC_FORMAT_INT_EGR_SHAPE_BCM56800_A0fmt */ 7408 /* format EGR_SHAPEfmt */ 7409 /* nFields */ 3, 7410 /* *fields */ soc_EGR_SHAPE_BCM56800_A0fmt_fields, 7411 /* bits */ 17, 7412 /* flags */ 0, 7413 }, 7414 #endif /* chips */ 7415 7416 #if defined(BCM_56820_A0) 7417 { /* SOC_FORMAT_INT_EGR_SHAPE_BCM56820_A0fmt */ 7418 /* format EGR_SHAPEfmt */ 7419 /* nFields */ 5, 7420 /* *fields */ soc_EGR_SHAPE_BCM56820_A0fmt_fields, 7421 /* bits */ 20, 7422 /* flags */ 0, 7423 }, 7424 #endif /* chips */ 7425 7426 #if defined(BCM_56840_A0) 7427 { /* SOC_FORMAT_INT_EGR_SHAPE_BCM56840_A0fmt */ 7428 /* format EGR_SHAPEfmt */ 7429 /* nFields */ 10, 7430 /* *fields */ soc_EGR_SHAPE_BCM56840_A0fmt_fields, 7431 /* bits */ 37, 7432 /* flags */ 0, 7433 }, 7434 #endif /* chips */ 7435 7436 #if defined(BCM_56840_B0) 7437 { /* SOC_FORMAT_INT_EGR_SHAPE_BCM56840_B0fmt */ 7438 /* format EGR_SHAPEfmt */ 7439 /* nFields */ 10, 7440 /* *fields */ soc_EGR_SHAPE_BCM56840_A0fmt_fields, 7441 /* bits */ 37, 7442 /* flags */ 0, 7443 }, 7444 #endif /* chips */ 7445 7446 #if defined(BCM_56850_A0) 7447 { /* SOC_FORMAT_INT_EGR_SHAPE_BCM56850_A0fmt */ 7448 /* format EGR_SHAPEfmt */ 7449 /* nFields */ 14, 7450 /* *fields */ soc_EGR_SHAPE_BCM56850_A0fmt_fields, 7451 /* bits */ 57, 7452 /* flags */ 0, 7453 }, 7454 #endif /* chips */ 7455 7456 #if defined(BCM_56860_A0) 7457 { /* SOC_FORMAT_INT_EGR_SHAPE_BCM56860_A0fmt */ 7458 /* format EGR_SHAPEfmt */ 7459 /* nFields */ 15, 7460 /* *fields */ soc_EGR_SHAPE_BCM56860_A0fmt_fields, 7461 /* bits */ 58, 7462 /* flags */ 0, 7463 }, 7464 #endif /* chips */ 7465 7466 #if defined(BCM_56870_A0) 7467 { /* SOC_FORMAT_INT_EGR_SHAPE_BCM56870_A0fmt */ 7468 /* format EGR_SHAPEfmt */ 7469 /* nFields */ 9, 7470 /* *fields */ soc_EGR_SHAPE_BCM56870_A0fmt_fields, 7471 /* bits */ 40, 7472 /* flags */ 0, 7473 }, 7474 #endif /* chips */ 7475 7476 #if defined(BCM_56960_A0) 7477 { /* SOC_FORMAT_INT_EGR_SHAPE_BCM56960_A0fmt */ 7478 /* format EGR_SHAPEfmt */ 7479 /* nFields */ 7, 7480 /* *fields */ soc_EGR_SHAPE_BCM56960_A0fmt_fields, 7481 /* bits */ 38, 7482 /* flags */ 0, 7483 }, 7484 #endif /* chips */ 7485 7486 #if defined(BCM_56965_A0) 7487 { /* SOC_FORMAT_INT_EGR_SHAPE_BCM56965_A0fmt */ 7488 /* format EGR_SHAPEfmt */ 7489 /* nFields */ 7, 7490 /* *fields */ soc_EGR_SHAPE_BCM56960_A0fmt_fields, 7491 /* bits */ 38, 7492 /* flags */ 0, 7493 }, 7494 #endif /* chips */ 7495 7496 #if defined(BCM_56970_A0) 7497 { /* SOC_FORMAT_INT_EGR_SHAPE_BCM56970_A0fmt */ 7498 /* format EGR_SHAPEfmt */ 7499 /* nFields */ 8, 7500 /* *fields */ soc_EGR_SHAPE_BCM56970_A0fmt_fields, 7501 /* bits */ 39, 7502 /* flags */ 0, 7503 }, 7504 #endif /* chips */ 7505 7506 #if defined(BCM_56980_A0) 7507 { /* SOC_FORMAT_INT_EGR_SHAPE_BCM56980_A0fmt */ 7508 /* format EGR_SHAPEfmt */ 7509 /* nFields */ 6, 7510 /* *fields */ soc_EGR_SHAPE_BCM56980_A0fmt_fields, 7511 /* bits */ 33, 7512 /* flags */ 0, 7513 }, 7514 #endif /* chips */ 7515 7516 #if defined(BCM_56980_B0) 7517 { /* SOC_FORMAT_INT_EGR_SHAPE_BCM56980_B0fmt */ 7518 /* format EGR_SHAPEfmt */ 7519 /* nFields */ 6, 7520 /* *fields */ soc_EGR_SHAPE_BCM56980_A0fmt_fields, 7521 /* bits */ 33, 7522 /* flags */ 0, 7523 }, 7524 #endif /* chips */ 7525 7526 #if defined(BCM_88732_A0) 7527 { /* SOC_FORMAT_INT_EGR_SHAPE_BCM88732_A0fmt */ 7528 /* format EGR_SHAPEfmt */ 7529 /* nFields */ 8, 7530 /* *fields */ soc_EGR_SHAPE_BCM88732_A0fmt_fields, 7531 /* bits */ 24, 7532 /* flags */ 0, 7533 }, 7534 #endif /* chips */ 7535 7536 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) 7537 { /* SOC_FORMAT_INT_EGR_SHAPE_INFOfmt */ 7538 /* format EGR_SHAPE_INFOfmt */ 7539 /* nFields */ 8, 7540 /* *fields */ soc_EGR_SHAPE_INFOfmt_fields, 7541 /* bits */ 19, 7542 /* flags */ 0, 7543 }, 7544 #endif /* chips */ 7545 7546 #if defined(BCM_56370_A0) 7547 { /* SOC_FORMAT_INT_EGR_SHAPE_INFO_BCM56370_A0fmt */ 7548 /* format EGR_SHAPE_INFOfmt */ 7549 /* nFields */ 9, 7550 /* *fields */ soc_EGR_SHAPE_INFO_BCM56370_A0fmt_fields, 7551 /* bits */ 20, 7552 /* flags */ 0, 7553 }, 7554 #endif /* chips */ 7555 7556 #if defined(BCM_56770_A0) 7557 { /* SOC_FORMAT_INT_EGR_SHAPE_INFO_BCM56770_A0fmt */ 7558 /* format EGR_SHAPE_INFOfmt */ 7559 /* nFields */ 4, 7560 /* *fields */ soc_EGR_SHAPE_INFO_BCM56870_A0fmt_fields, 7561 /* bits */ 19, 7562 /* flags */ 0, 7563 }, 7564 #endif /* chips */ 7565 7566 #if defined(BCM_56870_A0) 7567 { /* SOC_FORMAT_INT_EGR_SHAPE_INFO_BCM56870_A0fmt */ 7568 /* format EGR_SHAPE_INFOfmt */ 7569 /* nFields */ 4, 7570 /* *fields */ soc_EGR_SHAPE_INFO_BCM56870_A0fmt_fields, 7571 /* bits */ 19, 7572 /* flags */ 0, 7573 }, 7574 #endif /* chips */ 7575 7576 #if defined(BCM_56970_A0) 7577 { /* SOC_FORMAT_INT_EGR_SHAPE_INFO_BCM56970_A0fmt */ 7578 /* format EGR_SHAPE_INFOfmt */ 7579 /* nFields */ 5, 7580 /* *fields */ soc_EGR_SHAPE_INFO_BCM56970_A0fmt_fields, 7581 /* bits */ 19, 7582 /* flags */ 0, 7583 }, 7584 #endif /* chips */ 7585 7586 #if defined(BCM_56980_A0) 7587 { /* SOC_FORMAT_INT_EGR_SHAPE_INFO_BCM56980_A0fmt */ 7588 /* format EGR_SHAPE_INFOfmt */ 7589 /* nFields */ 6, 7590 /* *fields */ soc_EGR_SHAPE_INFO_BCM56980_A0fmt_fields, 7591 /* bits */ 15, 7592 /* flags */ 0, 7593 }, 7594 #endif /* chips */ 7595 7596 #if defined(BCM_56980_B0) 7597 { /* SOC_FORMAT_INT_EGR_SHAPE_INFO_BCM56980_B0fmt */ 7598 /* format EGR_SHAPE_INFOfmt */ 7599 /* nFields */ 6, 7600 /* *fields */ soc_EGR_SHAPE_INFO_BCM56980_A0fmt_fields, 7601 /* bits */ 15, 7602 /* flags */ 0, 7603 }, 7604 #endif /* chips */ 7605 7606 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 7607 defined(BCM_56870_A0) 7608 { /* SOC_FORMAT_INT_EGR_SPECIAL_PKT_HANDLING_PROFILE_IDfmt */ 7609 /* format EGR_SPECIAL_PKT_HANDLING_PROFILE_IDfmt */ 7610 /* nFields */ 6, 7611 /* *fields */ soc_EGR_SPECIAL_PKT_HANDLING_PROFILE_IDfmt_fields, 7612 /* bits */ 8, 7613 /* flags */ 0, 7614 }, 7615 #endif /* chips */ 7616 7617 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 7618 defined(BCM_56870_A0) 7619 { /* SOC_FORMAT_INT_EGR_STATS_FORMATfmt */ 7620 /* format EGR_STATS_FORMATfmt */ 7621 /* nFields */ 18, 7622 /* *fields */ soc_EGR_STATS_FORMATfmt_fields, 7623 /* bits */ 20, 7624 /* flags */ 0, 7625 }, 7626 #endif /* chips */ 7627 7628 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 7629 defined(BCM_56870_A0) 7630 { /* SOC_FORMAT_INT_EGR_TAG_STATUSfmt */ 7631 /* format EGR_TAG_STATUSfmt */ 7632 /* nFields */ 1, 7633 /* *fields */ soc_EGR_TAG_STATUSfmt_fields, 7634 /* bits */ 1, 7635 /* flags */ 0, 7636 }, 7637 #endif /* chips */ 7638 7639 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 7640 defined(BCM_56870_A0) 7641 { /* SOC_FORMAT_INT_EGR_TAPfmt */ 7642 /* format EGR_TAPfmt */ 7643 /* nFields */ 2, 7644 /* *fields */ soc_EGR_TAPfmt_fields, 7645 /* bits */ 3, 7646 /* flags */ 0, 7647 }, 7648 #endif /* chips */ 7649 7650 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 7651 defined(BCM_56870_A0) 7652 { /* SOC_FORMAT_INT_EGR_TUNNEL_ECN_ENCAP_TABLE_INDEXfmt */ 7653 /* format EGR_TUNNEL_ECN_ENCAP_TABLE_INDEXfmt */ 7654 /* nFields */ 4, 7655 /* *fields */ soc_EGR_TUNNEL_ECN_ENCAP_TABLE_INDEXfmt_fields, 7656 /* bits */ 7, 7657 /* flags */ 0, 7658 }, 7659 #endif /* chips */ 7660 7661 #if defined(BCM_56370_A0) 7662 { /* SOC_FORMAT_INT_EGR_VC_AND_SWAP_EARLY_PDD_OUT_BUSfmt */ 7663 /* format EGR_VC_AND_SWAP_EARLY_PDD_OUT_BUSfmt */ 7664 /* nFields */ 85, 7665 /* *fields */ soc_EGR_VC_AND_SWAP_EARLY_PDD_OUT_BUSfmt_fields, 7666 /* bits */ 56, 7667 /* flags */ 0, 7668 }, 7669 #endif /* chips */ 7670 7671 #if defined(BCM_56870_A0) 7672 { /* SOC_FORMAT_INT_EGR_VC_AND_SWAP_PDD_OUT_BUSfmt */ 7673 /* format EGR_VC_AND_SWAP_PDD_OUT_BUSfmt */ 7674 /* nFields */ 156, 7675 /* *fields */ soc_EGR_DVP_ATTRIBUTE_PDD_OUT_BUSfmt_fields, 7676 /* bits */ 1632, 7677 /* flags */ 0, 7678 }, 7679 #endif /* chips */ 7680 7681 #if defined(BCM_56370_A0) 7682 { /* SOC_FORMAT_INT_EGR_VC_AND_SWAP_PDD_OUT_BUS_BCM56370_A0fmt */ 7683 /* format EGR_VC_AND_SWAP_PDD_OUT_BUSfmt */ 7684 /* nFields */ 156, 7685 /* *fields */ soc_EGR_VC_AND_SWAP_PDD_OUT_BUSfmt_fields, 7686 /* bits */ 1632, 7687 /* flags */ 0, 7688 }, 7689 #endif /* chips */ 7690 7691 #if defined(BCM_56770_A0) 7692 { /* SOC_FORMAT_INT_EGR_VC_AND_SWAP_PDD_OUT_BUS_BCM56770_A0fmt */ 7693 /* format EGR_VC_AND_SWAP_PDD_OUT_BUSfmt */ 7694 /* nFields */ 156, 7695 /* *fields */ soc_EGR_DVP_ATTRIBUTE_PDD_OUT_BUSfmt_fields, 7696 /* bits */ 1632, 7697 /* flags */ 0, 7698 }, 7699 #endif /* chips */ 7700 7701 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 7702 defined(BCM_56870_A0) 7703 { /* SOC_FORMAT_INT_EGR_VFT_PRI_MAP_INDEXfmt */ 7704 /* format EGR_VFT_PRI_MAP_INDEXfmt */ 7705 /* nFields */ 2, 7706 /* *fields */ soc_EGR_VFT_PRI_MAP_INDEXfmt_fields, 7707 /* bits */ 5, 7708 /* flags */ 0, 7709 }, 7710 #endif /* chips */ 7711 7712 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 7713 defined(BCM_56870_A0) 7714 { /* SOC_FORMAT_INT_EGR_VLAN_ACTION_MASK_PROFILE_FORMATfmt */ 7715 /* format EGR_VLAN_ACTION_MASK_PROFILE_FORMATfmt */ 7716 /* nFields */ 8, 7717 /* *fields */ soc_EGR_VLAN_ACTION_MASK_PROFILE_FORMATfmt_fields, 7718 /* bits */ 8, 7719 /* flags */ 0, 7720 }, 7721 #endif /* chips */ 7722 7723 #if defined(BCM_56860_A0) 7724 { /* SOC_FORMAT_INT_EGR_VLAN_XLATE_TUNNEL_DATAfmt */ 7725 /* format EGR_VLAN_XLATE_TUNNEL_DATAfmt */ 7726 /* nFields */ 12, 7727 /* *fields */ soc_EGR_VLAN_XLATE_TUNNEL_DATAfmt_fields, 7728 /* bits */ 83, 7729 /* flags */ 0, 7730 }, 7731 #endif /* chips */ 7732 7733 #if defined(BCM_56560_A0) 7734 { /* SOC_FORMAT_INT_EGR_VLAN_XLATE_TUNNEL_DATA_BCM56560_A0fmt */ 7735 /* format EGR_VLAN_XLATE_TUNNEL_DATAfmt */ 7736 /* nFields */ 12, 7737 /* *fields */ soc_EGR_VLAN_XLATE_TUNNEL_DATA_BCM56560_A0fmt_fields, 7738 /* bits */ 83, 7739 /* flags */ 0, 7740 }, 7741 #endif /* chips */ 7742 7743 #if defined(BCM_56560_B0) 7744 { /* SOC_FORMAT_INT_EGR_VLAN_XLATE_TUNNEL_DATA_BCM56560_B0fmt */ 7745 /* format EGR_VLAN_XLATE_TUNNEL_DATAfmt */ 7746 /* nFields */ 12, 7747 /* *fields */ soc_EGR_VLAN_XLATE_TUNNEL_DATA_BCM56560_A0fmt_fields, 7748 /* bits */ 83, 7749 /* flags */ 0, 7750 }, 7751 #endif /* chips */ 7752 7753 #if defined(BCM_56670_A0) 7754 { /* SOC_FORMAT_INT_EGR_VLAN_XLATE_TUNNEL_DATA_BCM56670_A0fmt */ 7755 /* format EGR_VLAN_XLATE_TUNNEL_DATAfmt */ 7756 /* nFields */ 12, 7757 /* *fields */ soc_EGR_VLAN_XLATE_TUNNEL_DATA_BCM56560_A0fmt_fields, 7758 /* bits */ 83, 7759 /* flags */ 0, 7760 }, 7761 #endif /* chips */ 7762 7763 #if defined(BCM_56670_B0) 7764 { /* SOC_FORMAT_INT_EGR_VLAN_XLATE_TUNNEL_DATA_BCM56670_B0fmt */ 7765 /* format EGR_VLAN_XLATE_TUNNEL_DATAfmt */ 7766 /* nFields */ 12, 7767 /* *fields */ soc_EGR_VLAN_XLATE_TUNNEL_DATA_BCM56560_A0fmt_fields, 7768 /* bits */ 83, 7769 /* flags */ 0, 7770 }, 7771 #endif /* chips */ 7772 7773 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) 7774 { /* SOC_FORMAT_INT_EGR_VLAN_XLATE_TUNNEL_DATA_DOUBLEfmt */ 7775 /* format EGR_VLAN_XLATE_TUNNEL_DATA_DOUBLEfmt */ 7776 /* nFields */ 11, 7777 /* *fields */ soc_EGR_VLAN_XLATE_TUNNEL_DATA_DOUBLEfmt_fields, 7778 /* bits */ 83, 7779 /* flags */ 0, 7780 }, 7781 #endif /* chips */ 7782 7783 #if defined(BCM_56370_A0) 7784 { /* SOC_FORMAT_INT_EGR_VLAN_XLATE_TUNNEL_DATA_DOUBLE_BCM56370_A0fmt */ 7785 /* format EGR_VLAN_XLATE_TUNNEL_DATA_DOUBLEfmt */ 7786 /* nFields */ 11, 7787 /* *fields */ soc_EGR_VLAN_XLATE_TUNNEL_DATA_DOUBLE_BCM56370_A0fmt_fields, 7788 /* bits */ 83, 7789 /* flags */ 0, 7790 }, 7791 #endif /* chips */ 7792 7793 #if defined(BCM_56860_A0) 7794 { /* SOC_FORMAT_INT_EGR_VLAN_XLATE_XLATE_DATAfmt */ 7795 /* format EGR_VLAN_XLATE_XLATE_DATAfmt */ 7796 /* nFields */ 27, 7797 /* *fields */ soc_EGR_VLAN_XLATE_XLATE_DATAfmt_fields, 7798 /* bits */ 79, 7799 /* flags */ 0, 7800 }, 7801 #endif /* chips */ 7802 7803 #if defined(BCM_56560_A0) 7804 { /* SOC_FORMAT_INT_EGR_VLAN_XLATE_XLATE_DATA_BCM56560_A0fmt */ 7805 /* format EGR_VLAN_XLATE_XLATE_DATAfmt */ 7806 /* nFields */ 27, 7807 /* *fields */ soc_EGR_VLAN_XLATE_XLATE_DATA_BCM56560_A0fmt_fields, 7808 /* bits */ 79, 7809 /* flags */ 0, 7810 }, 7811 #endif /* chips */ 7812 7813 #if defined(BCM_56560_B0) 7814 { /* SOC_FORMAT_INT_EGR_VLAN_XLATE_XLATE_DATA_BCM56560_B0fmt */ 7815 /* format EGR_VLAN_XLATE_XLATE_DATAfmt */ 7816 /* nFields */ 27, 7817 /* *fields */ soc_EGR_VLAN_XLATE_XLATE_DATA_BCM56560_A0fmt_fields, 7818 /* bits */ 79, 7819 /* flags */ 0, 7820 }, 7821 #endif /* chips */ 7822 7823 #if defined(BCM_56670_A0) 7824 { /* SOC_FORMAT_INT_EGR_VLAN_XLATE_XLATE_DATA_BCM56670_A0fmt */ 7825 /* format EGR_VLAN_XLATE_XLATE_DATAfmt */ 7826 /* nFields */ 22, 7827 /* *fields */ soc_EGR_VLAN_XLATE_XLATE_DATA_BCM56670_A0fmt_fields, 7828 /* bits */ 60, 7829 /* flags */ 0, 7830 }, 7831 #endif /* chips */ 7832 7833 #if defined(BCM_56670_B0) 7834 { /* SOC_FORMAT_INT_EGR_VLAN_XLATE_XLATE_DATA_BCM56670_B0fmt */ 7835 /* format EGR_VLAN_XLATE_XLATE_DATAfmt */ 7836 /* nFields */ 22, 7837 /* *fields */ soc_EGR_VLAN_XLATE_XLATE_DATA_BCM56670_A0fmt_fields, 7838 /* bits */ 60, 7839 /* flags */ 0, 7840 }, 7841 #endif /* chips */ 7842 7843 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) 7844 { /* SOC_FORMAT_INT_EGR_VLAN_XLATE_XLATE_DATA_DOUBLEfmt */ 7845 /* format EGR_VLAN_XLATE_XLATE_DATA_DOUBLEfmt */ 7846 /* nFields */ 26, 7847 /* *fields */ soc_EGR_VLAN_XLATE_XLATE_DATA_DOUBLEfmt_fields, 7848 /* bits */ 80, 7849 /* flags */ 0, 7850 }, 7851 #endif /* chips */ 7852 7853 #if defined(BCM_56370_A0) 7854 { /* SOC_FORMAT_INT_EGR_VLAN_XLATE_XLATE_DATA_DOUBLE_BCM56370_A0fmt */ 7855 /* format EGR_VLAN_XLATE_XLATE_DATA_DOUBLEfmt */ 7856 /* nFields */ 26, 7857 /* *fields */ soc_EGR_VLAN_XLATE_XLATE_DATA_DOUBLE_BCM56370_A0fmt_fields, 7858 /* bits */ 80, 7859 /* flags */ 0, 7860 }, 7861 #endif /* chips */ 7862 7863 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 7864 defined(BCM_56870_A0) 7865 { /* SOC_FORMAT_INT_EGR_ZONE_DOT1P_MAPPING_TABLE_INDEXfmt */ 7866 /* format EGR_ZONE_DOT1P_MAPPING_TABLE_INDEXfmt */ 7867 /* nFields */ 3, 7868 /* *fields */ soc_EGR_ZONE_DOT1P_MAPPING_TABLE_INDEXfmt_fields, 7869 /* bits */ 10, 7870 /* flags */ 0, 7871 }, 7872 #endif /* chips */ 7873 7874 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) 7875 { /* SOC_FORMAT_INT_EGR_ZONE_QOS_MAPPING_TABLE_INDEXfmt */ 7876 /* format EGR_ZONE_QOS_MAPPING_TABLE_INDEXfmt */ 7877 /* nFields */ 3, 7878 /* *fields */ soc_EGR_ZONE_QOS_MAPPING_TABLE_INDEXfmt_fields, 7879 /* bits */ 14, 7880 /* flags */ 0, 7881 }, 7882 #endif /* chips */ 7883 7884 #if defined(BCM_56370_A0) 7885 { /* SOC_FORMAT_INT_EGR_ZONE_QOS_MAPPING_TABLE_INDEX_BCM56370_A0fmt */ 7886 /* format EGR_ZONE_QOS_MAPPING_TABLE_INDEXfmt */ 7887 /* nFields */ 3, 7888 /* *fields */ soc_EGR_ZONE_QOS_MAPPING_TABLE_INDEX_BCM56370_A0fmt_fields, 7889 /* bits */ 13, 7890 /* flags */ 0, 7891 }, 7892 #endif /* chips */ 7893 7894 #if defined(BCM_56524_A0) || defined(BCM_56634_A0) || \ 7895 defined(BCM_56634_B0) 7896 { /* SOC_FORMAT_INT_EHG_HEADERfmt */ 7897 /* format EHG_HEADERfmt */ 7898 /* nFields */ 5, 7899 /* *fields */ soc_EHG_HEADERfmt_fields, 7900 /* bits */ 32, 7901 /* flags */ 0, 7902 }, 7903 #endif /* chips */ 7904 7905 #if defined(BCM_56260_A0) 7906 { /* SOC_FORMAT_INT_EHG_HEADER_BCM56260_A0fmt */ 7907 /* format EHG_HEADERfmt */ 7908 /* nFields */ 5, 7909 /* *fields */ soc_EHG_HEADER_BCM56260_A0fmt_fields, 7910 /* bits */ 32, 7911 /* flags */ 0, 7912 }, 7913 #endif /* chips */ 7914 7915 #if defined(BCM_56260_B0) 7916 { /* SOC_FORMAT_INT_EHG_HEADER_BCM56260_B0fmt */ 7917 /* format EHG_HEADERfmt */ 7918 /* nFields */ 5, 7919 /* *fields */ soc_EHG_HEADER_BCM56260_A0fmt_fields, 7920 /* bits */ 32, 7921 /* flags */ 0, 7922 }, 7923 #endif /* chips */ 7924 7925 #if defined(BCM_56270_A0) 7926 { /* SOC_FORMAT_INT_EHG_HEADER_BCM56270_A0fmt */ 7927 /* format EHG_HEADERfmt */ 7928 /* nFields */ 5, 7929 /* *fields */ soc_EHG_HEADER_BCM56260_A0fmt_fields, 7930 /* bits */ 32, 7931 /* flags */ 0, 7932 }, 7933 #endif /* chips */ 7934 7935 #if defined(BCM_56340_A0) 7936 { /* SOC_FORMAT_INT_EHG_HEADER_BCM56340_A0fmt */ 7937 /* format EHG_HEADERfmt */ 7938 /* nFields */ 6, 7939 /* *fields */ soc_EHG_HEADER_BCM56640_A0fmt_fields, 7940 /* bits */ 32, 7941 /* flags */ 0, 7942 }, 7943 #endif /* chips */ 7944 7945 #if defined(BCM_56370_A0) 7946 { /* SOC_FORMAT_INT_EHG_HEADER_BCM56370_A0fmt */ 7947 /* format EHG_HEADERfmt */ 7948 /* nFields */ 6, 7949 /* *fields */ soc_EHG_HEADER_BCM56960_A0fmt_fields, 7950 /* bits */ 32, 7951 /* flags */ 0, 7952 }, 7953 #endif /* chips */ 7954 7955 #if defined(BCM_56440_A0) 7956 { /* SOC_FORMAT_INT_EHG_HEADER_BCM56440_A0fmt */ 7957 /* format EHG_HEADERfmt */ 7958 /* nFields */ 5, 7959 /* *fields */ soc_EHG_HEADER_BCM56840_A0fmt_fields, 7960 /* bits */ 32, 7961 /* flags */ 0, 7962 }, 7963 #endif /* chips */ 7964 7965 #if defined(BCM_56440_B0) 7966 { /* SOC_FORMAT_INT_EHG_HEADER_BCM56440_B0fmt */ 7967 /* format EHG_HEADERfmt */ 7968 /* nFields */ 5, 7969 /* *fields */ soc_EHG_HEADER_BCM56840_A0fmt_fields, 7970 /* bits */ 32, 7971 /* flags */ 0, 7972 }, 7973 #endif /* chips */ 7974 7975 #if defined(BCM_56450_A0) 7976 { /* SOC_FORMAT_INT_EHG_HEADER_BCM56450_A0fmt */ 7977 /* format EHG_HEADERfmt */ 7978 /* nFields */ 5, 7979 /* *fields */ soc_EHG_HEADER_BCM56450_A0fmt_fields, 7980 /* bits */ 32, 7981 /* flags */ 0, 7982 }, 7983 #endif /* chips */ 7984 7985 #if defined(BCM_56450_B0) 7986 { /* SOC_FORMAT_INT_EHG_HEADER_BCM56450_B0fmt */ 7987 /* format EHG_HEADERfmt */ 7988 /* nFields */ 5, 7989 /* *fields */ soc_EHG_HEADER_BCM56450_A0fmt_fields, 7990 /* bits */ 32, 7991 /* flags */ 0, 7992 }, 7993 #endif /* chips */ 7994 7995 #if defined(BCM_56450_B1) 7996 { /* SOC_FORMAT_INT_EHG_HEADER_BCM56450_B1fmt */ 7997 /* format EHG_HEADERfmt */ 7998 /* nFields */ 5, 7999 /* *fields */ soc_EHG_HEADER_BCM56450_A0fmt_fields, 8000 /* bits */ 32, 8001 /* flags */ 0, 8002 }, 8003 #endif /* chips */ 8004 8005 #if defined(BCM_56524_B0) 8006 { /* SOC_FORMAT_INT_EHG_HEADER_BCM56524_B0fmt */ 8007 /* format EHG_HEADERfmt */ 8008 /* nFields */ 5, 8009 /* *fields */ soc_EHG_HEADERfmt_fields, 8010 /* bits */ 32, 8011 /* flags */ 0, 8012 }, 8013 #endif /* chips */ 8014 8015 #if defined(BCM_56560_A0) 8016 { /* SOC_FORMAT_INT_EHG_HEADER_BCM56560_A0fmt */ 8017 /* format EHG_HEADERfmt */ 8018 /* nFields */ 6, 8019 /* *fields */ soc_EHG_HEADER_BCM56960_A0fmt_fields, 8020 /* bits */ 32, 8021 /* flags */ 0, 8022 }, 8023 #endif /* chips */ 8024 8025 #if defined(BCM_56560_B0) 8026 { /* SOC_FORMAT_INT_EHG_HEADER_BCM56560_B0fmt */ 8027 /* format EHG_HEADERfmt */ 8028 /* nFields */ 6, 8029 /* *fields */ soc_EHG_HEADER_BCM56960_A0fmt_fields, 8030 /* bits */ 32, 8031 /* flags */ 0, 8032 }, 8033 #endif /* chips */ 8034 8035 #if defined(BCM_56640_A0) 8036 { /* SOC_FORMAT_INT_EHG_HEADER_BCM56640_A0fmt */ 8037 /* format EHG_HEADERfmt */ 8038 /* nFields */ 6, 8039 /* *fields */ soc_EHG_HEADER_BCM56640_A0fmt_fields, 8040 /* bits */ 32, 8041 /* flags */ 0, 8042 }, 8043 #endif /* chips */ 8044 8045 #if defined(BCM_56670_A0) 8046 { /* SOC_FORMAT_INT_EHG_HEADER_BCM56670_A0fmt */ 8047 /* format EHG_HEADERfmt */ 8048 /* nFields */ 6, 8049 /* *fields */ soc_EHG_HEADER_BCM56960_A0fmt_fields, 8050 /* bits */ 32, 8051 /* flags */ 0, 8052 }, 8053 #endif /* chips */ 8054 8055 #if defined(BCM_56670_B0) 8056 { /* SOC_FORMAT_INT_EHG_HEADER_BCM56670_B0fmt */ 8057 /* format EHG_HEADERfmt */ 8058 /* nFields */ 6, 8059 /* *fields */ soc_EHG_HEADER_BCM56960_A0fmt_fields, 8060 /* bits */ 32, 8061 /* flags */ 0, 8062 }, 8063 #endif /* chips */ 8064 8065 #if defined(BCM_56685_A0) 8066 { /* SOC_FORMAT_INT_EHG_HEADER_BCM56685_A0fmt */ 8067 /* format EHG_HEADERfmt */ 8068 /* nFields */ 5, 8069 /* *fields */ soc_EHG_HEADERfmt_fields, 8070 /* bits */ 32, 8071 /* flags */ 0, 8072 }, 8073 #endif /* chips */ 8074 8075 #if defined(BCM_56685_B0) 8076 { /* SOC_FORMAT_INT_EHG_HEADER_BCM56685_B0fmt */ 8077 /* format EHG_HEADERfmt */ 8078 /* nFields */ 5, 8079 /* *fields */ soc_EHG_HEADERfmt_fields, 8080 /* bits */ 32, 8081 /* flags */ 0, 8082 }, 8083 #endif /* chips */ 8084 8085 #if defined(BCM_56770_A0) 8086 { /* SOC_FORMAT_INT_EHG_HEADER_BCM56770_A0fmt */ 8087 /* format EHG_HEADERfmt */ 8088 /* nFields */ 6, 8089 /* *fields */ soc_EHG_HEADER_BCM56960_A0fmt_fields, 8090 /* bits */ 32, 8091 /* flags */ 0, 8092 }, 8093 #endif /* chips */ 8094 8095 #if defined(BCM_56840_A0) 8096 { /* SOC_FORMAT_INT_EHG_HEADER_BCM56840_A0fmt */ 8097 /* format EHG_HEADERfmt */ 8098 /* nFields */ 5, 8099 /* *fields */ soc_EHG_HEADER_BCM56840_A0fmt_fields, 8100 /* bits */ 32, 8101 /* flags */ 0, 8102 }, 8103 #endif /* chips */ 8104 8105 #if defined(BCM_56840_B0) 8106 { /* SOC_FORMAT_INT_EHG_HEADER_BCM56840_B0fmt */ 8107 /* format EHG_HEADERfmt */ 8108 /* nFields */ 5, 8109 /* *fields */ soc_EHG_HEADER_BCM56840_A0fmt_fields, 8110 /* bits */ 32, 8111 /* flags */ 0, 8112 }, 8113 #endif /* chips */ 8114 8115 #if defined(BCM_56850_A0) 8116 { /* SOC_FORMAT_INT_EHG_HEADER_BCM56850_A0fmt */ 8117 /* format EHG_HEADERfmt */ 8118 /* nFields */ 6, 8119 /* *fields */ soc_EHG_HEADER_BCM56640_A0fmt_fields, 8120 /* bits */ 32, 8121 /* flags */ 0, 8122 }, 8123 #endif /* chips */ 8124 8125 #if defined(BCM_56860_A0) 8126 { /* SOC_FORMAT_INT_EHG_HEADER_BCM56860_A0fmt */ 8127 /* format EHG_HEADERfmt */ 8128 /* nFields */ 6, 8129 /* *fields */ soc_EHG_HEADER_BCM56640_A0fmt_fields, 8130 /* bits */ 32, 8131 /* flags */ 0, 8132 }, 8133 #endif /* chips */ 8134 8135 #if defined(BCM_56870_A0) 8136 { /* SOC_FORMAT_INT_EHG_HEADER_BCM56870_A0fmt */ 8137 /* format EHG_HEADERfmt */ 8138 /* nFields */ 6, 8139 /* *fields */ soc_EHG_HEADER_BCM56960_A0fmt_fields, 8140 /* bits */ 32, 8141 /* flags */ 0, 8142 }, 8143 #endif /* chips */ 8144 8145 #if defined(BCM_56960_A0) 8146 { /* SOC_FORMAT_INT_EHG_HEADER_BCM56960_A0fmt */ 8147 /* format EHG_HEADERfmt */ 8148 /* nFields */ 6, 8149 /* *fields */ soc_EHG_HEADER_BCM56960_A0fmt_fields, 8150 /* bits */ 32, 8151 /* flags */ 0, 8152 }, 8153 #endif /* chips */ 8154 8155 #if defined(BCM_56965_A0) 8156 { /* SOC_FORMAT_INT_EHG_HEADER_BCM56965_A0fmt */ 8157 /* format EHG_HEADERfmt */ 8158 /* nFields */ 6, 8159 /* *fields */ soc_EHG_HEADER_BCM56960_A0fmt_fields, 8160 /* bits */ 32, 8161 /* flags */ 0, 8162 }, 8163 #endif /* chips */ 8164 8165 #if defined(BCM_56970_A0) 8166 { /* SOC_FORMAT_INT_EHG_HEADER_BCM56970_A0fmt */ 8167 /* format EHG_HEADERfmt */ 8168 /* nFields */ 6, 8169 /* *fields */ soc_EHG_HEADER_BCM56960_A0fmt_fields, 8170 /* bits */ 32, 8171 /* flags */ 0, 8172 }, 8173 #endif /* chips */ 8174 8175 #if defined(BCM_56980_A0) 8176 { /* SOC_FORMAT_INT_EHG_HEADER_BCM56980_A0fmt */ 8177 /* format EHG_HEADERfmt */ 8178 /* nFields */ 6, 8179 /* *fields */ soc_EHG_HEADER_BCM56960_A0fmt_fields, 8180 /* bits */ 32, 8181 /* flags */ 0, 8182 }, 8183 #endif /* chips */ 8184 8185 #if defined(BCM_56980_B0) 8186 { /* SOC_FORMAT_INT_EHG_HEADER_BCM56980_B0fmt */ 8187 /* format EHG_HEADERfmt */ 8188 /* nFields */ 6, 8189 /* *fields */ soc_EHG_HEADER_BCM56960_A0fmt_fields, 8190 /* bits */ 32, 8191 /* flags */ 0, 8192 }, 8193 #endif /* chips */ 8194 8195 #if defined(BCM_56850_A0) || defined(BCM_56860_A0) 8196 { /* SOC_FORMAT_INT_EH_SEG_SEL_ENCODINGfmt */ 8197 /* format EH_SEG_SEL_ENCODINGfmt */ 8198 /* nFields */ 1, 8199 /* *fields */ soc_EH_SEG_SEL_ENCODINGfmt_fields, 8200 /* bits */ 3, 8201 /* flags */ 0, 8202 }, 8203 #endif /* chips */ 8204 8205 #if defined(BCM_56370_A0) 8206 { /* SOC_FORMAT_INT_EH_SEG_SEL_ENCODING_BCM56370_A0fmt */ 8207 /* format EH_SEG_SEL_ENCODINGfmt */ 8208 /* nFields */ 1, 8209 /* *fields */ soc_NIV_CPU_OPCODE_ENCODING_BCM53400_A0fmt_fields, 8210 /* bits */ 3, 8211 /* flags */ 0, 8212 }, 8213 #endif /* chips */ 8214 8215 #if defined(BCM_56560_A0) 8216 { /* SOC_FORMAT_INT_EH_SEG_SEL_ENCODING_BCM56560_A0fmt */ 8217 /* format EH_SEG_SEL_ENCODINGfmt */ 8218 /* nFields */ 1, 8219 /* *fields */ soc_NIV_CPU_OPCODE_ENCODING_BCM53400_A0fmt_fields, 8220 /* bits */ 3, 8221 /* flags */ 0, 8222 }, 8223 #endif /* chips */ 8224 8225 #if defined(BCM_56560_B0) 8226 { /* SOC_FORMAT_INT_EH_SEG_SEL_ENCODING_BCM56560_B0fmt */ 8227 /* format EH_SEG_SEL_ENCODINGfmt */ 8228 /* nFields */ 1, 8229 /* *fields */ soc_NIV_CPU_OPCODE_ENCODING_BCM53400_A0fmt_fields, 8230 /* bits */ 3, 8231 /* flags */ 0, 8232 }, 8233 #endif /* chips */ 8234 8235 #if defined(BCM_56670_A0) 8236 { /* SOC_FORMAT_INT_EH_SEG_SEL_ENCODING_BCM56670_A0fmt */ 8237 /* format EH_SEG_SEL_ENCODINGfmt */ 8238 /* nFields */ 1, 8239 /* *fields */ soc_NIV_CPU_OPCODE_ENCODING_BCM53400_A0fmt_fields, 8240 /* bits */ 3, 8241 /* flags */ 0, 8242 }, 8243 #endif /* chips */ 8244 8245 #if defined(BCM_56670_B0) 8246 { /* SOC_FORMAT_INT_EH_SEG_SEL_ENCODING_BCM56670_B0fmt */ 8247 /* format EH_SEG_SEL_ENCODINGfmt */ 8248 /* nFields */ 1, 8249 /* *fields */ soc_NIV_CPU_OPCODE_ENCODING_BCM53400_A0fmt_fields, 8250 /* bits */ 3, 8251 /* flags */ 0, 8252 }, 8253 #endif /* chips */ 8254 8255 #if defined(BCM_56770_A0) 8256 { /* SOC_FORMAT_INT_EH_SEG_SEL_ENCODING_BCM56770_A0fmt */ 8257 /* format EH_SEG_SEL_ENCODINGfmt */ 8258 /* nFields */ 1, 8259 /* *fields */ soc_NIV_CPU_OPCODE_ENCODING_BCM53400_A0fmt_fields, 8260 /* bits */ 3, 8261 /* flags */ 0, 8262 }, 8263 #endif /* chips */ 8264 8265 #if defined(BCM_56870_A0) 8266 { /* SOC_FORMAT_INT_EH_SEG_SEL_ENCODING_BCM56870_A0fmt */ 8267 /* format EH_SEG_SEL_ENCODINGfmt */ 8268 /* nFields */ 1, 8269 /* *fields */ soc_NIV_CPU_OPCODE_ENCODING_BCM53400_A0fmt_fields, 8270 /* bits */ 3, 8271 /* flags */ 0, 8272 }, 8273 #endif /* chips */ 8274 8275 #if defined(BCM_56960_A0) 8276 { /* SOC_FORMAT_INT_EH_SEG_SEL_ENCODING_BCM56960_A0fmt */ 8277 /* format EH_SEG_SEL_ENCODINGfmt */ 8278 /* nFields */ 1, 8279 /* *fields */ soc_NIV_CPU_OPCODE_ENCODING_BCM53400_A0fmt_fields, 8280 /* bits */ 3, 8281 /* flags */ 0, 8282 }, 8283 #endif /* chips */ 8284 8285 #if defined(BCM_56965_A0) 8286 { /* SOC_FORMAT_INT_EH_SEG_SEL_ENCODING_BCM56965_A0fmt */ 8287 /* format EH_SEG_SEL_ENCODINGfmt */ 8288 /* nFields */ 1, 8289 /* *fields */ soc_NIV_CPU_OPCODE_ENCODING_BCM53400_A0fmt_fields, 8290 /* bits */ 3, 8291 /* flags */ 0, 8292 }, 8293 #endif /* chips */ 8294 8295 #if defined(BCM_56970_A0) 8296 { /* SOC_FORMAT_INT_EH_SEG_SEL_ENCODING_BCM56970_A0fmt */ 8297 /* format EH_SEG_SEL_ENCODINGfmt */ 8298 /* nFields */ 1, 8299 /* *fields */ soc_NIV_CPU_OPCODE_ENCODING_BCM53400_A0fmt_fields, 8300 /* bits */ 3, 8301 /* flags */ 0, 8302 }, 8303 #endif /* chips */ 8304 8305 #if defined(BCM_56980_A0) 8306 { /* SOC_FORMAT_INT_EH_SEG_SEL_ENCODING_BCM56980_A0fmt */ 8307 /* format EH_SEG_SEL_ENCODINGfmt */ 8308 /* nFields */ 1, 8309 /* *fields */ soc_NIV_CPU_OPCODE_ENCODING_BCM53400_A0fmt_fields, 8310 /* bits */ 3, 8311 /* flags */ 0, 8312 }, 8313 #endif /* chips */ 8314 8315 #if defined(BCM_56980_B0) 8316 { /* SOC_FORMAT_INT_EH_SEG_SEL_ENCODING_BCM56980_B0fmt */ 8317 /* format EH_SEG_SEL_ENCODINGfmt */ 8318 /* nFields */ 1, 8319 /* *fields */ soc_NIV_CPU_OPCODE_ENCODING_BCM53400_A0fmt_fields, 8320 /* bits */ 3, 8321 /* flags */ 0, 8322 }, 8323 #endif /* chips */ 8324 8325 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 8326 defined(BCM_56870_A0) 8327 { /* SOC_FORMAT_INT_EH_TYPE_0_FORMATfmt */ 8328 /* format EH_TYPE_0_FORMATfmt */ 8329 /* nFields */ 7, 8330 /* *fields */ soc_EH_TYPE_0_FORMATfmt_fields, 8331 /* bits */ 32, 8332 /* flags */ 0, 8333 }, 8334 #endif /* chips */ 8335 8336 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) 8337 { /* SOC_FORMAT_INT_EH_TYPE_1_FORMATfmt */ 8338 /* format EH_TYPE_1_FORMATfmt */ 8339 /* nFields */ 5, 8340 /* *fields */ soc_EH_TYPE_1_FORMATfmt_fields, 8341 /* bits */ 32, 8342 /* flags */ 0, 8343 }, 8344 #endif /* chips */ 8345 8346 #if defined(BCM_56370_A0) 8347 { /* SOC_FORMAT_INT_EH_TYPE_1_FORMAT_BCM56370_A0fmt */ 8348 /* format EH_TYPE_1_FORMATfmt */ 8349 /* nFields */ 6, 8350 /* *fields */ soc_EH_TYPE_1_FORMAT_BCM56370_A0fmt_fields, 8351 /* bits */ 32, 8352 /* flags */ 0, 8353 }, 8354 #endif /* chips */ 8355 8356 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) 8357 { /* SOC_FORMAT_INT_EH_TYPE_2_FORMATfmt */ 8358 /* format EH_TYPE_2_FORMATfmt */ 8359 /* nFields */ 5, 8360 /* *fields */ soc_EH_TYPE_2_FORMATfmt_fields, 8361 /* bits */ 32, 8362 /* flags */ 0, 8363 }, 8364 #endif /* chips */ 8365 8366 #if defined(BCM_56370_A0) 8367 { /* SOC_FORMAT_INT_EH_TYPE_2_FORMAT_BCM56370_A0fmt */ 8368 /* format EH_TYPE_2_FORMATfmt */ 8369 /* nFields */ 6, 8370 /* *fields */ soc_EH_TYPE_2_FORMAT_BCM56370_A0fmt_fields, 8371 /* bits */ 32, 8372 /* flags */ 0, 8373 }, 8374 #endif /* chips */ 8375 8376 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) 8377 { /* SOC_FORMAT_INT_EL3_0_DOPfmt */ 8378 /* format EL3_0_DOPfmt */ 8379 /* nFields */ 6, 8380 /* *fields */ soc_EL3_0_DOPfmt_fields, 8381 /* bits */ 96, 8382 /* flags */ 0, 8383 }, 8384 #endif /* chips */ 8385 8386 #if defined(BCM_56370_A0) 8387 { /* SOC_FORMAT_INT_EL3_0_DOP_BCM56370_A0fmt */ 8388 /* format EL3_0_DOPfmt */ 8389 /* nFields */ 6, 8390 /* *fields */ soc_EL3_0_DOP_BCM56370_A0fmt_fields, 8391 /* bits */ 96, 8392 /* flags */ 0, 8393 }, 8394 #endif /* chips */ 8395 8396 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 8397 defined(BCM_56870_A0) 8398 { /* SOC_FORMAT_INT_EL3_1_DOPfmt */ 8399 /* format EL3_1_DOPfmt */ 8400 /* nFields */ 4, 8401 /* *fields */ soc_EL3_1_DOPfmt_fields, 8402 /* bits */ 32, 8403 /* flags */ 0, 8404 }, 8405 #endif /* chips */ 8406 8407 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) 8408 { /* SOC_FORMAT_INT_EL3_2_DOPfmt */ 8409 /* format EL3_2_DOPfmt */ 8410 /* nFields */ 3, 8411 /* *fields */ soc_EL3_2_DOPfmt_fields, 8412 /* bits */ 32, 8413 /* flags */ 0, 8414 }, 8415 #endif /* chips */ 8416 8417 #if defined(BCM_56370_A0) 8418 { /* SOC_FORMAT_INT_EL3_2_DOP_BCM56370_A0fmt */ 8419 /* format EL3_2_DOPfmt */ 8420 /* nFields */ 3, 8421 /* *fields */ soc_EL3_2_DOP_BCM56370_A0fmt_fields, 8422 /* bits */ 32, 8423 /* flags */ 0, 8424 }, 8425 #endif /* chips */ 8426 8427 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) 8428 { /* SOC_FORMAT_INT_EL3_3_DOPfmt */ 8429 /* format EL3_3_DOPfmt */ 8430 /* nFields */ 4, 8431 /* *fields */ soc_EL3_3_DOPfmt_fields, 8432 /* bits */ 32, 8433 /* flags */ 0, 8434 }, 8435 #endif /* chips */ 8436 8437 #if defined(BCM_56370_A0) 8438 { /* SOC_FORMAT_INT_EL3_3_DOP_BCM56370_A0fmt */ 8439 /* format EL3_3_DOPfmt */ 8440 /* nFields */ 4, 8441 /* *fields */ soc_EL3_3_DOP_BCM56370_A0fmt_fields, 8442 /* bits */ 32, 8443 /* flags */ 0, 8444 }, 8445 #endif /* chips */ 8446 8447 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) 8448 { /* SOC_FORMAT_INT_EL3_4_DOPfmt */ 8449 /* format EL3_4_DOPfmt */ 8450 /* nFields */ 4, 8451 /* *fields */ soc_EL3_4_DOPfmt_fields, 8452 /* bits */ 32, 8453 /* flags */ 0, 8454 }, 8455 #endif /* chips */ 8456 8457 #if defined(BCM_56370_A0) 8458 { /* SOC_FORMAT_INT_EL3_4_DOP_BCM56370_A0fmt */ 8459 /* format EL3_4_DOPfmt */ 8460 /* nFields */ 4, 8461 /* *fields */ soc_EL3_4_DOP_BCM56370_A0fmt_fields, 8462 /* bits */ 32, 8463 /* flags */ 0, 8464 }, 8465 #endif /* chips */ 8466 8467 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) 8468 { /* SOC_FORMAT_INT_EL3_5_DOPfmt */ 8469 /* format EL3_5_DOPfmt */ 8470 /* nFields */ 5, 8471 /* *fields */ soc_EL3_5_DOPfmt_fields, 8472 /* bits */ 32, 8473 /* flags */ 0, 8474 }, 8475 #endif /* chips */ 8476 8477 #if defined(BCM_56370_A0) 8478 { /* SOC_FORMAT_INT_EL3_5_DOP_BCM56370_A0fmt */ 8479 /* format EL3_5_DOPfmt */ 8480 /* nFields */ 4, 8481 /* *fields */ soc_EPMOD_0_DOPfmt_fields, 8482 /* bits */ 32, 8483 /* flags */ 0, 8484 }, 8485 #endif /* chips */ 8486 8487 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 8488 defined(BCM_56870_A0) 8489 { /* SOC_FORMAT_INT_EL3_DOPfmt */ 8490 /* format EL3_DOPfmt */ 8491 /* nFields */ 48, 8492 /* *fields */ soc_EL3_DOPfmt_fields, 8493 /* bits */ 576, 8494 /* flags */ 0, 8495 }, 8496 #endif /* chips */ 8497 8498 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) 8499 { /* SOC_FORMAT_INT_EL3_EMOP_BUFFERfmt */ 8500 /* format EL3_EMOP_BUFFERfmt */ 8501 /* nFields */ 13, 8502 /* *fields */ soc_EL3_EMOP_BUFFERfmt_fields, 8503 /* bits */ 106, 8504 /* flags */ 0, 8505 }, 8506 #endif /* chips */ 8507 8508 #if defined(BCM_56370_A0) 8509 { /* SOC_FORMAT_INT_EL3_EMOP_BUFFER_BCM56370_A0fmt */ 8510 /* format EL3_EMOP_BUFFERfmt */ 8511 /* nFields */ 14, 8512 /* *fields */ soc_EL3_EMOP_BUFFER_BCM56370_A0fmt_fields, 8513 /* bits */ 106, 8514 /* flags */ 0, 8515 }, 8516 #endif /* chips */ 8517 8518 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 8519 defined(BCM_56870_A0) 8520 { /* SOC_FORMAT_INT_EL3_FCfmt */ 8521 /* format EL3_FCfmt */ 8522 /* nFields */ 1, 8523 /* *fields */ soc_EL3_FCfmt_fields, 8524 /* bits */ 2, 8525 /* flags */ 0, 8526 }, 8527 #endif /* chips */ 8528 8529 #if defined(BCM_56870_A0) 8530 { /* SOC_FORMAT_INT_EL3_OBJECT_BUSfmt */ 8531 /* format EL3_OBJECT_BUSfmt */ 8532 /* nFields */ 131, 8533 /* *fields */ soc_EL3_OBJECT_BUSfmt_fields, 8534 /* bits */ 1302, 8535 /* flags */ 0, 8536 }, 8537 #endif /* chips */ 8538 8539 #if defined(BCM_56370_A0) 8540 { /* SOC_FORMAT_INT_EL3_OBJECT_BUS_BCM56370_A0fmt */ 8541 /* format EL3_OBJECT_BUSfmt */ 8542 /* nFields */ 140, 8543 /* *fields */ soc_EL3_OBJECT_BUS_BCM56370_A0fmt_fields, 8544 /* bits */ 1326, 8545 /* flags */ 0, 8546 }, 8547 #endif /* chips */ 8548 8549 #if defined(BCM_56770_A0) 8550 { /* SOC_FORMAT_INT_EL3_OBJECT_BUS_BCM56770_A0fmt */ 8551 /* format EL3_OBJECT_BUSfmt */ 8552 /* nFields */ 133, 8553 /* *fields */ soc_EL3_OBJECT_BUS_BCM56770_A0fmt_fields, 8554 /* bits */ 1326, 8555 /* flags */ 0, 8556 }, 8557 #endif /* chips */ 8558 8559 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 8560 defined(BCM_56870_A0) 8561 { /* SOC_FORMAT_INT_EL3_TIMESTAMP_ACTION_SETfmt */ 8562 /* format EL3_TIMESTAMP_ACTION_SETfmt */ 8563 /* nFields */ 3, 8564 /* *fields */ soc_EL3_TIMESTAMP_ACTION_SETfmt_fields, 8565 /* bits */ 3, 8566 /* flags */ 0, 8567 }, 8568 #endif /* chips */ 8569 8570 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) 8571 { /* SOC_FORMAT_INT_EMC_TO_DEQ_RD_REQ_COMPLETE_INFOfmt */ 8572 /* format EMC_TO_DEQ_RD_REQ_COMPLETE_INFOfmt */ 8573 /* nFields */ 1, 8574 /* *fields */ soc_EMC_TO_DEQ_RD_REQ_COMPLETE_INFOfmt_fields, 8575 /* bits */ 39, 8576 /* flags */ 0, 8577 }, 8578 #endif /* chips */ 8579 8580 #if defined(BCM_56450_A0) 8581 { /* SOC_FORMAT_INT_EMC_TO_DEQ_RD_REQ_COMPLETE_INFO_BCM56450_A0fmt */ 8582 /* format EMC_TO_DEQ_RD_REQ_COMPLETE_INFOfmt */ 8583 /* nFields */ 1, 8584 /* *fields */ soc_EMC_TO_DEQ_RD_REQ_COMPLETE_INFO_BCM56450_A0fmt_fields, 8585 /* bits */ 39, 8586 /* flags */ 0, 8587 }, 8588 #endif /* chips */ 8589 8590 #if defined(BCM_56450_B0) 8591 { /* SOC_FORMAT_INT_EMC_TO_DEQ_RD_REQ_COMPLETE_INFO_BCM56450_B0fmt */ 8592 /* format EMC_TO_DEQ_RD_REQ_COMPLETE_INFOfmt */ 8593 /* nFields */ 1, 8594 /* *fields */ soc_EMC_TO_DEQ_RD_REQ_COMPLETE_INFO_BCM56450_A0fmt_fields, 8595 /* bits */ 39, 8596 /* flags */ 0, 8597 }, 8598 #endif /* chips */ 8599 8600 #if defined(BCM_56450_B1) 8601 { /* SOC_FORMAT_INT_EMC_TO_DEQ_RD_REQ_COMPLETE_INFO_BCM56450_B1fmt */ 8602 /* format EMC_TO_DEQ_RD_REQ_COMPLETE_INFOfmt */ 8603 /* nFields */ 1, 8604 /* *fields */ soc_EMC_TO_DEQ_RD_REQ_COMPLETE_INFO_BCM56450_A0fmt_fields, 8605 /* bits */ 39, 8606 /* flags */ 0, 8607 }, 8608 #endif /* chips */ 8609 8610 #if defined(BCM_56440_A0) 8611 { /* SOC_FORMAT_INT_EMC_TO_DEQ_RD_REQ_INFOfmt */ 8612 /* format EMC_TO_DEQ_RD_REQ_INFOfmt */ 8613 /* nFields */ 4, 8614 /* *fields */ soc_EMC_TO_DEQ_RD_REQ_INFOfmt_fields, 8615 /* bits */ 38, 8616 /* flags */ 0, 8617 }, 8618 #endif /* chips */ 8619 8620 #if defined(BCM_56440_B0) 8621 { /* SOC_FORMAT_INT_EMC_TO_DEQ_RD_REQ_INFO_BCM56440_B0fmt */ 8622 /* format EMC_TO_DEQ_RD_REQ_INFOfmt */ 8623 /* nFields */ 4, 8624 /* *fields */ soc_EMC_TO_DEQ_RD_REQ_INFOfmt_fields, 8625 /* bits */ 38, 8626 /* flags */ 0, 8627 }, 8628 #endif /* chips */ 8629 8630 #if defined(BCM_56450_A0) 8631 { /* SOC_FORMAT_INT_EMC_TO_DEQ_RD_REQ_INFO_BCM56450_A0fmt */ 8632 /* format EMC_TO_DEQ_RD_REQ_INFOfmt */ 8633 /* nFields */ 4, 8634 /* *fields */ soc_EMC_TO_DEQ_RD_REQ_INFO_BCM56450_A0fmt_fields, 8635 /* bits */ 38, 8636 /* flags */ 0, 8637 }, 8638 #endif /* chips */ 8639 8640 #if defined(BCM_56450_B0) 8641 { /* SOC_FORMAT_INT_EMC_TO_DEQ_RD_REQ_INFO_BCM56450_B0fmt */ 8642 /* format EMC_TO_DEQ_RD_REQ_INFOfmt */ 8643 /* nFields */ 4, 8644 /* *fields */ soc_EMC_TO_DEQ_RD_REQ_INFO_BCM56450_A0fmt_fields, 8645 /* bits */ 38, 8646 /* flags */ 0, 8647 }, 8648 #endif /* chips */ 8649 8650 #if defined(BCM_56450_B1) 8651 { /* SOC_FORMAT_INT_EMC_TO_DEQ_RD_REQ_INFO_BCM56450_B1fmt */ 8652 /* format EMC_TO_DEQ_RD_REQ_INFOfmt */ 8653 /* nFields */ 4, 8654 /* *fields */ soc_EMC_TO_DEQ_RD_REQ_INFO_BCM56450_A0fmt_fields, 8655 /* bits */ 38, 8656 /* flags */ 0, 8657 }, 8658 #endif /* chips */ 8659 8660 #if defined(BCM_56440_A0) 8661 { /* SOC_FORMAT_INT_EMC_TO_ITE_WR_REQ_PKT_COMPLETE_INFOfmt */ 8662 /* format EMC_TO_ITE_WR_REQ_PKT_COMPLETE_INFOfmt */ 8663 /* nFields */ 5, 8664 /* *fields */ soc_EMC_TO_ITE_WR_REQ_PKT_COMPLETE_INFOfmt_fields, 8665 /* bits */ 37, 8666 /* flags */ 0, 8667 }, 8668 #endif /* chips */ 8669 8670 #if defined(BCM_56440_B0) 8671 { /* SOC_FORMAT_INT_EMC_TO_ITE_WR_REQ_PKT_COMPLETE_INFO_BCM56440_B0fmt */ 8672 /* format EMC_TO_ITE_WR_REQ_PKT_COMPLETE_INFOfmt */ 8673 /* nFields */ 5, 8674 /* *fields */ soc_EMC_TO_ITE_WR_REQ_PKT_COMPLETE_INFOfmt_fields, 8675 /* bits */ 37, 8676 /* flags */ 0, 8677 }, 8678 #endif /* chips */ 8679 8680 #if defined(BCM_56450_A0) 8681 { /* SOC_FORMAT_INT_EMC_TO_ITE_WR_REQ_PKT_COMPLETE_INFO_BCM56450_A0fmt */ 8682 /* format EMC_TO_ITE_WR_REQ_PKT_COMPLETE_INFOfmt */ 8683 /* nFields */ 5, 8684 /* *fields */ soc_EMC_TO_ITE_WR_REQ_PKT_COMPLETE_INFO_BCM56450_A0fmt_fields, 8685 /* bits */ 37, 8686 /* flags */ 0, 8687 }, 8688 #endif /* chips */ 8689 8690 #if defined(BCM_56450_B0) 8691 { /* SOC_FORMAT_INT_EMC_TO_ITE_WR_REQ_PKT_COMPLETE_INFO_BCM56450_B0fmt */ 8692 /* format EMC_TO_ITE_WR_REQ_PKT_COMPLETE_INFOfmt */ 8693 /* nFields */ 5, 8694 /* *fields */ soc_EMC_TO_ITE_WR_REQ_PKT_COMPLETE_INFO_BCM56450_A0fmt_fields, 8695 /* bits */ 37, 8696 /* flags */ 0, 8697 }, 8698 #endif /* chips */ 8699 8700 #if defined(BCM_56450_B1) 8701 { /* SOC_FORMAT_INT_EMC_TO_ITE_WR_REQ_PKT_COMPLETE_INFO_BCM56450_B1fmt */ 8702 /* format EMC_TO_ITE_WR_REQ_PKT_COMPLETE_INFOfmt */ 8703 /* nFields */ 5, 8704 /* *fields */ soc_EMC_TO_ITE_WR_REQ_PKT_COMPLETE_INFO_BCM56450_A0fmt_fields, 8705 /* bits */ 37, 8706 /* flags */ 0, 8707 }, 8708 #endif /* chips */ 8709 8710 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) 8711 { /* SOC_FORMAT_INT_EMC_TO_LLS_INFOfmt */ 8712 /* format EMC_TO_LLS_INFOfmt */ 8713 /* nFields */ 1, 8714 /* *fields */ soc_EMC_TO_LLS_INFOfmt_fields, 8715 /* bits */ 2, 8716 /* flags */ 0, 8717 }, 8718 #endif /* chips */ 8719 8720 #if defined(BCM_56450_A0) 8721 { /* SOC_FORMAT_INT_EMC_TO_LLS_INFO_BCM56450_A0fmt */ 8722 /* format EMC_TO_LLS_INFOfmt */ 8723 /* nFields */ 1, 8724 /* *fields */ soc_EMC_TO_LLS_INFO_BCM56450_A0fmt_fields, 8725 /* bits */ 2, 8726 /* flags */ 0, 8727 }, 8728 #endif /* chips */ 8729 8730 #if defined(BCM_56450_B0) 8731 { /* SOC_FORMAT_INT_EMC_TO_LLS_INFO_BCM56450_B0fmt */ 8732 /* format EMC_TO_LLS_INFOfmt */ 8733 /* nFields */ 1, 8734 /* *fields */ soc_EMC_TO_LLS_INFO_BCM56450_A0fmt_fields, 8735 /* bits */ 2, 8736 /* flags */ 0, 8737 }, 8738 #endif /* chips */ 8739 8740 #if defined(BCM_56450_B1) 8741 { /* SOC_FORMAT_INT_EMC_TO_LLS_INFO_BCM56450_B1fmt */ 8742 /* format EMC_TO_LLS_INFOfmt */ 8743 /* nFields */ 1, 8744 /* *fields */ soc_EMC_TO_LLS_INFO_BCM56450_A0fmt_fields, 8745 /* bits */ 2, 8746 /* flags */ 0, 8747 }, 8748 #endif /* chips */ 8749 8750 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) 8751 { /* SOC_FORMAT_INT_ENGINE_CTRL_DOP_DOPfmt */ 8752 /* format ENGINE_CTRL_DOP_DOPfmt */ 8753 /* nFields */ 26, 8754 /* *fields */ soc_ENGINE_CTRL_DOP_DOPfmt_fields, 8755 /* bits */ 192, 8756 /* flags */ 0, 8757 }, 8758 #endif /* chips */ 8759 8760 #if defined(BCM_56370_A0) 8761 { /* SOC_FORMAT_INT_ENGINE_CTRL_DOP_DOP_BCM56370_A0fmt */ 8762 /* format ENGINE_CTRL_DOP_DOPfmt */ 8763 /* nFields */ 26, 8764 /* *fields */ soc_ENGINE_CTRL_DOP_DOP_BCM56370_A0fmt_fields, 8765 /* bits */ 192, 8766 /* flags */ 0, 8767 }, 8768 #endif /* chips */ 8769 8770 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) 8771 { /* SOC_FORMAT_INT_ENQS_CT_BYPfmt */ 8772 /* format ENQS_CT_BYPfmt */ 8773 /* nFields */ 14, 8774 /* *fields */ soc_ENQS_CT_BYPfmt_fields, 8775 /* bits */ 70, 8776 /* flags */ 0, 8777 }, 8778 #endif /* chips */ 8779 8780 #if defined(BCM_56770_A0) 8781 { /* SOC_FORMAT_INT_ENQS_CT_BYP_BCM56770_A0fmt */ 8782 /* format ENQS_CT_BYPfmt */ 8783 /* nFields */ 13, 8784 /* *fields */ soc_ENQS_CT_BYP_BCM56870_A0fmt_fields, 8785 /* bits */ 74, 8786 /* flags */ 0, 8787 }, 8788 #endif /* chips */ 8789 8790 #if defined(BCM_56870_A0) 8791 { /* SOC_FORMAT_INT_ENQS_CT_BYP_BCM56870_A0fmt */ 8792 /* format ENQS_CT_BYPfmt */ 8793 /* nFields */ 13, 8794 /* *fields */ soc_ENQS_CT_BYP_BCM56870_A0fmt_fields, 8795 /* bits */ 74, 8796 /* flags */ 0, 8797 }, 8798 #endif /* chips */ 8799 8800 #if defined(BCM_56970_A0) 8801 { /* SOC_FORMAT_INT_ENQS_CT_BYP_BCM56970_A0fmt */ 8802 /* format ENQS_CT_BYPfmt */ 8803 /* nFields */ 14, 8804 /* *fields */ soc_ENQS_CT_BYP_BCM56970_A0fmt_fields, 8805 /* bits */ 71, 8806 /* flags */ 0, 8807 }, 8808 #endif /* chips */ 8809 8810 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) 8811 { /* SOC_FORMAT_INT_ENQS_PIPEfmt */ 8812 /* format ENQS_PIPEfmt */ 8813 /* nFields */ 39, 8814 /* *fields */ soc_ENQS_PIPEfmt_fields, 8815 /* bits */ 311, 8816 /* flags */ 0, 8817 }, 8818 #endif /* chips */ 8819 8820 #if defined(BCM_56370_A0) 8821 { /* SOC_FORMAT_INT_ENQS_PIPE_BCM56370_A0fmt */ 8822 /* format ENQS_PIPEfmt */ 8823 /* nFields */ 43, 8824 /* *fields */ soc_ENQS_PIPE_BCM56370_A0fmt_fields, 8825 /* bits */ 380, 8826 /* flags */ 0, 8827 }, 8828 #endif /* chips */ 8829 8830 #if defined(BCM_56770_A0) 8831 { /* SOC_FORMAT_INT_ENQS_PIPE_BCM56770_A0fmt */ 8832 /* format ENQS_PIPEfmt */ 8833 /* nFields */ 43, 8834 /* *fields */ soc_ENQS_PIPE_BCM56870_A0fmt_fields, 8835 /* bits */ 505, 8836 /* flags */ 0, 8837 }, 8838 #endif /* chips */ 8839 8840 #if defined(BCM_56870_A0) 8841 { /* SOC_FORMAT_INT_ENQS_PIPE_BCM56870_A0fmt */ 8842 /* format ENQS_PIPEfmt */ 8843 /* nFields */ 43, 8844 /* *fields */ soc_ENQS_PIPE_BCM56870_A0fmt_fields, 8845 /* bits */ 505, 8846 /* flags */ 0, 8847 }, 8848 #endif /* chips */ 8849 8850 #if defined(BCM_56970_A0) 8851 { /* SOC_FORMAT_INT_ENQS_PIPE_BCM56970_A0fmt */ 8852 /* format ENQS_PIPEfmt */ 8853 /* nFields */ 43, 8854 /* *fields */ soc_ENQS_PIPE_BCM56970_A0fmt_fields, 8855 /* bits */ 361, 8856 /* flags */ 0, 8857 }, 8858 #endif /* chips */ 8859 8860 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) 8861 { /* SOC_FORMAT_INT_ENQS_TO_DEQ_ASF_INFOfmt */ 8862 /* format ENQS_TO_DEQ_ASF_INFOfmt */ 8863 /* nFields */ 14, 8864 /* *fields */ soc_ENQS_TO_DEQ_ASF_INFOfmt_fields, 8865 /* bits */ 66, 8866 /* flags */ 0, 8867 }, 8868 #endif /* chips */ 8869 8870 #if defined(BCM_56370_A0) 8871 { /* SOC_FORMAT_INT_ENQS_TO_DEQ_ASF_INFO_BCM56370_A0fmt */ 8872 /* format ENQS_TO_DEQ_ASF_INFOfmt */ 8873 /* nFields */ 13, 8874 /* *fields */ soc_ENQS_TO_DEQ_ASF_INFO_BCM56370_A0fmt_fields, 8875 /* bits */ 71, 8876 /* flags */ 0, 8877 }, 8878 #endif /* chips */ 8879 8880 #if defined(BCM_56770_A0) 8881 { /* SOC_FORMAT_INT_ENQS_TO_DEQ_ASF_INFO_BCM56770_A0fmt */ 8882 /* format ENQS_TO_DEQ_ASF_INFOfmt */ 8883 /* nFields */ 13, 8884 /* *fields */ soc_ENQS_TO_DEQ_ASF_INFO_BCM56870_A0fmt_fields, 8885 /* bits */ 71, 8886 /* flags */ 0, 8887 }, 8888 #endif /* chips */ 8889 8890 #if defined(BCM_56870_A0) 8891 { /* SOC_FORMAT_INT_ENQS_TO_DEQ_ASF_INFO_BCM56870_A0fmt */ 8892 /* format ENQS_TO_DEQ_ASF_INFOfmt */ 8893 /* nFields */ 13, 8894 /* *fields */ soc_ENQS_TO_DEQ_ASF_INFO_BCM56870_A0fmt_fields, 8895 /* bits */ 71, 8896 /* flags */ 0, 8897 }, 8898 #endif /* chips */ 8899 8900 #if defined(BCM_56970_A0) 8901 { /* SOC_FORMAT_INT_ENQS_TO_DEQ_ASF_INFO_BCM56970_A0fmt */ 8902 /* format ENQS_TO_DEQ_ASF_INFOfmt */ 8903 /* nFields */ 14, 8904 /* *fields */ soc_ENQS_TO_DEQ_ASF_INFO_BCM56970_A0fmt_fields, 8905 /* bits */ 67, 8906 /* flags */ 0, 8907 }, 8908 #endif /* chips */ 8909 8910 #if defined(BCM_56960_A0) 8911 { /* SOC_FORMAT_INT_ENQS_TO_ENQX_INFOfmt */ 8912 /* format ENQS_TO_ENQX_INFOfmt */ 8913 /* nFields */ 39, 8914 /* *fields */ soc_ENQS_PIPEfmt_fields, 8915 /* bits */ 311, 8916 /* flags */ 0, 8917 }, 8918 #endif /* chips */ 8919 8920 #if defined(BCM_56370_A0) 8921 { /* SOC_FORMAT_INT_ENQS_TO_ENQX_INFO_BCM56370_A0fmt */ 8922 /* format ENQS_TO_ENQX_INFOfmt */ 8923 /* nFields */ 44, 8924 /* *fields */ soc_ENQS_TO_ENQX_INFO_BCM56370_A0fmt_fields, 8925 /* bits */ 380, 8926 /* flags */ 0, 8927 }, 8928 #endif /* chips */ 8929 8930 #if defined(BCM_56770_A0) 8931 { /* SOC_FORMAT_INT_ENQS_TO_ENQX_INFO_BCM56770_A0fmt */ 8932 /* format ENQS_TO_ENQX_INFOfmt */ 8933 /* nFields */ 44, 8934 /* *fields */ soc_ENQS_TO_ENQX_INFO_BCM56870_A0fmt_fields, 8935 /* bits */ 505, 8936 /* flags */ 0, 8937 }, 8938 #endif /* chips */ 8939 8940 #if defined(BCM_56870_A0) 8941 { /* SOC_FORMAT_INT_ENQS_TO_ENQX_INFO_BCM56870_A0fmt */ 8942 /* format ENQS_TO_ENQX_INFOfmt */ 8943 /* nFields */ 44, 8944 /* *fields */ soc_ENQS_TO_ENQX_INFO_BCM56870_A0fmt_fields, 8945 /* bits */ 505, 8946 /* flags */ 0, 8947 }, 8948 #endif /* chips */ 8949 8950 #if defined(BCM_56965_A0) 8951 { /* SOC_FORMAT_INT_ENQS_TO_ENQX_INFO_BCM56965_A0fmt */ 8952 /* format ENQS_TO_ENQX_INFOfmt */ 8953 /* nFields */ 39, 8954 /* *fields */ soc_ENQS_PIPEfmt_fields, 8955 /* bits */ 311, 8956 /* flags */ 0, 8957 }, 8958 #endif /* chips */ 8959 8960 #if defined(BCM_56970_A0) 8961 { /* SOC_FORMAT_INT_ENQS_TO_ENQX_INFO_BCM56970_A0fmt */ 8962 /* format ENQS_TO_ENQX_INFOfmt */ 8963 /* nFields */ 44, 8964 /* *fields */ soc_ENQS_TO_ENQX_INFOfmt_fields, 8965 /* bits */ 361, 8966 /* flags */ 0, 8967 }, 8968 #endif /* chips */ 8969 8970 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) 8971 { /* SOC_FORMAT_INT_ENQS_TO_TOQ_CELLLINK_WDATAfmt */ 8972 /* format ENQS_TO_TOQ_CELLLINK_WDATAfmt */ 8973 /* nFields */ 2, 8974 /* *fields */ soc_ENQS_TO_TOQ_CELLLINK_WDATAfmt_fields, 8975 /* bits */ 16, 8976 /* flags */ 0, 8977 }, 8978 #endif /* chips */ 8979 8980 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) || \ 8981 defined(BCM_56970_A0) 8982 { /* SOC_FORMAT_INT_ENQX_TO_CTR_TX_PKT_INFOfmt */ 8983 /* format ENQX_TO_CTR_TX_PKT_INFOfmt */ 8984 /* nFields */ 7, 8985 /* *fields */ soc_ENQX_TO_CTR_TX_PKT_INFOfmt_fields, 8986 /* bits */ 25, 8987 /* flags */ 0, 8988 }, 8989 #endif /* chips */ 8990 8991 #if defined(BCM_56370_A0) 8992 { /* SOC_FORMAT_INT_ENQX_TO_CTR_TX_PKT_INFO_BCM56370_A0fmt */ 8993 /* format ENQX_TO_CTR_TX_PKT_INFOfmt */ 8994 /* nFields */ 7, 8995 /* *fields */ soc_ENQX_TO_CTR_TX_PKT_INFO_BCM56370_A0fmt_fields, 8996 /* bits */ 32, 8997 /* flags */ 0, 8998 }, 8999 #endif /* chips */ 9000 9001 #if defined(BCM_56770_A0) 9002 { /* SOC_FORMAT_INT_ENQX_TO_CTR_TX_PKT_INFO_BCM56770_A0fmt */ 9003 /* format ENQX_TO_CTR_TX_PKT_INFOfmt */ 9004 /* nFields */ 7, 9005 /* *fields */ soc_ENQX_TO_CTR_TX_PKT_INFO_BCM56870_A0fmt_fields, 9006 /* bits */ 26, 9007 /* flags */ 0, 9008 }, 9009 #endif /* chips */ 9010 9011 #if defined(BCM_56870_A0) 9012 { /* SOC_FORMAT_INT_ENQX_TO_CTR_TX_PKT_INFO_BCM56870_A0fmt */ 9013 /* format ENQX_TO_CTR_TX_PKT_INFOfmt */ 9014 /* nFields */ 7, 9015 /* *fields */ soc_ENQX_TO_CTR_TX_PKT_INFO_BCM56870_A0fmt_fields, 9016 /* bits */ 26, 9017 /* flags */ 0, 9018 }, 9019 #endif /* chips */ 9020 9021 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) 9022 { /* SOC_FORMAT_INT_ENQX_TO_PQE_INFOfmt */ 9023 /* format ENQX_TO_PQE_INFOfmt */ 9024 /* nFields */ 5, 9025 /* *fields */ soc_ENQX_TO_PQE_INFOfmt_fields, 9026 /* bits */ 24, 9027 /* flags */ 0, 9028 }, 9029 #endif /* chips */ 9030 9031 #if defined(BCM_56370_A0) 9032 { /* SOC_FORMAT_INT_ENQX_TO_PQE_INFO_BCM56370_A0fmt */ 9033 /* format ENQX_TO_PQE_INFOfmt */ 9034 /* nFields */ 5, 9035 /* *fields */ soc_ENQX_TO_PQE_INFO_BCM56370_A0fmt_fields, 9036 /* bits */ 26, 9037 /* flags */ 0, 9038 }, 9039 #endif /* chips */ 9040 9041 #if defined(BCM_56770_A0) 9042 { /* SOC_FORMAT_INT_ENQX_TO_PQE_INFO_BCM56770_A0fmt */ 9043 /* format ENQX_TO_PQE_INFOfmt */ 9044 /* nFields */ 5, 9045 /* *fields */ soc_ENQX_TO_PQE_INFO_BCM56870_A0fmt_fields, 9046 /* bits */ 28, 9047 /* flags */ 0, 9048 }, 9049 #endif /* chips */ 9050 9051 #if defined(BCM_56870_A0) 9052 { /* SOC_FORMAT_INT_ENQX_TO_PQE_INFO_BCM56870_A0fmt */ 9053 /* format ENQX_TO_PQE_INFOfmt */ 9054 /* nFields */ 5, 9055 /* *fields */ soc_ENQX_TO_PQE_INFO_BCM56870_A0fmt_fields, 9056 /* bits */ 28, 9057 /* flags */ 0, 9058 }, 9059 #endif /* chips */ 9060 9061 #if defined(BCM_56970_A0) 9062 { /* SOC_FORMAT_INT_ENQX_TO_PQE_INFO_BCM56970_A0fmt */ 9063 /* format ENQX_TO_PQE_INFOfmt */ 9064 /* nFields */ 5, 9065 /* *fields */ soc_ENQX_TO_PQE_INFO_BCM56970_A0fmt_fields, 9066 /* bits */ 25, 9067 /* flags */ 0, 9068 }, 9069 #endif /* chips */ 9070 9071 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 9072 defined(BCM_56870_A0) || defined(BCM_56970_A0) 9073 { /* SOC_FORMAT_INT_ENQX_TO_TCB_DROP_TYPEfmt */ 9074 /* format ENQX_TO_TCB_DROP_TYPEfmt */ 9075 /* nFields */ 5, 9076 /* *fields */ soc_ENQX_TO_TCB_DROP_TYPEfmt_fields, 9077 /* bits */ 5, 9078 /* flags */ 0, 9079 }, 9080 #endif /* chips */ 9081 9082 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 9083 defined(BCM_56870_A0) || defined(BCM_56970_A0) 9084 { /* SOC_FORMAT_INT_ENQX_TO_TCB_MPB_INFOfmt */ 9085 /* format ENQX_TO_TCB_MPB_INFOfmt */ 9086 /* nFields */ 3, 9087 /* *fields */ soc_ENQX_TO_TCB_MPB_INFOfmt_fields, 9088 /* bits */ 49, 9089 /* flags */ 0, 9090 }, 9091 #endif /* chips */ 9092 9093 #if defined(BCM_56370_A0) || defined(BCM_56970_A0) 9094 { /* SOC_FORMAT_INT_ENQX_TO_TOQ_CELLLINK_WDATAfmt */ 9095 /* format ENQX_TO_TOQ_CELLLINK_WDATAfmt */ 9096 /* nFields */ 2, 9097 /* *fields */ soc_ENQX_TO_TOQ_CELLLINK_WDATAfmt_fields, 9098 /* bits */ 17, 9099 /* flags */ 0, 9100 }, 9101 #endif /* chips */ 9102 9103 #if defined(BCM_56770_A0) 9104 { /* SOC_FORMAT_INT_ENQX_TO_TOQ_CELLLINK_WDATA_BCM56770_A0fmt */ 9105 /* format ENQX_TO_TOQ_CELLLINK_WDATAfmt */ 9106 /* nFields */ 2, 9107 /* *fields */ soc_ENQX_TO_TOQ_CELLLINK_WDATA_BCM56870_A0fmt_fields, 9108 /* bits */ 19, 9109 /* flags */ 0, 9110 }, 9111 #endif /* chips */ 9112 9113 #if defined(BCM_56870_A0) 9114 { /* SOC_FORMAT_INT_ENQX_TO_TOQ_CELLLINK_WDATA_BCM56870_A0fmt */ 9115 /* format ENQX_TO_TOQ_CELLLINK_WDATAfmt */ 9116 /* nFields */ 2, 9117 /* *fields */ soc_ENQX_TO_TOQ_CELLLINK_WDATA_BCM56870_A0fmt_fields, 9118 /* bits */ 19, 9119 /* flags */ 0, 9120 }, 9121 #endif /* chips */ 9122 9123 #if defined(BCM_56965_A0) || defined(BCM_56970_A0) 9124 { /* SOC_FORMAT_INT_ENQX_TO_TOQ_SRCPORT_INFOfmt */ 9125 /* format ENQX_TO_TOQ_SRCPORT_INFOfmt */ 9126 /* nFields */ 2, 9127 /* *fields */ soc_ENQX_TO_TOQ_SRCPORT_INFOfmt_fields, 9128 /* bits */ 7, 9129 /* flags */ 0, 9130 }, 9131 #endif /* chips */ 9132 9133 #if defined(BCM_56370_A0) 9134 { /* SOC_FORMAT_INT_ENQX_TO_TOQ_SRCPORT_INFO_BCM56370_A0fmt */ 9135 /* format ENQX_TO_TOQ_SRCPORT_INFOfmt */ 9136 /* nFields */ 2, 9137 /* *fields */ soc_ENQX_TO_TOQ_SRCPORT_INFO_BCM56870_A0fmt_fields, 9138 /* bits */ 8, 9139 /* flags */ 0, 9140 }, 9141 #endif /* chips */ 9142 9143 #if defined(BCM_56770_A0) 9144 { /* SOC_FORMAT_INT_ENQX_TO_TOQ_SRCPORT_INFO_BCM56770_A0fmt */ 9145 /* format ENQX_TO_TOQ_SRCPORT_INFOfmt */ 9146 /* nFields */ 2, 9147 /* *fields */ soc_ENQX_TO_TOQ_SRCPORT_INFO_BCM56870_A0fmt_fields, 9148 /* bits */ 8, 9149 /* flags */ 0, 9150 }, 9151 #endif /* chips */ 9152 9153 #if defined(BCM_56870_A0) 9154 { /* SOC_FORMAT_INT_ENQX_TO_TOQ_SRCPORT_INFO_BCM56870_A0fmt */ 9155 /* format ENQX_TO_TOQ_SRCPORT_INFOfmt */ 9156 /* nFields */ 2, 9157 /* *fields */ soc_ENQX_TO_TOQ_SRCPORT_INFO_BCM56870_A0fmt_fields, 9158 /* bits */ 8, 9159 /* flags */ 0, 9160 }, 9161 #endif /* chips */ 9162 9163 #if defined(BCM_56850_A0) || defined(BCM_56860_A0) 9164 { /* SOC_FORMAT_INT_ENQ_CT_DATA_DELAY_INFOfmt */ 9165 /* format ENQ_CT_DATA_DELAY_INFOfmt */ 9166 /* nFields */ 18, 9167 /* *fields */ soc_ENQ_CT_DATA_DELAY_INFOfmt_fields, 9168 /* bits */ 429, 9169 /* flags */ 0, 9170 }, 9171 #endif /* chips */ 9172 9173 #if defined(BCM_56560_A0) 9174 { /* SOC_FORMAT_INT_ENQ_CT_DATA_DELAY_INFO_BCM56560_A0fmt */ 9175 /* format ENQ_CT_DATA_DELAY_INFOfmt */ 9176 /* nFields */ 18, 9177 /* *fields */ soc_ENQ_CT_DATA_DELAY_INFO_BCM56560_A0fmt_fields, 9178 /* bits */ 338, 9179 /* flags */ 0, 9180 }, 9181 #endif /* chips */ 9182 9183 #if defined(BCM_56560_B0) 9184 { /* SOC_FORMAT_INT_ENQ_CT_DATA_DELAY_INFO_BCM56560_B0fmt */ 9185 /* format ENQ_CT_DATA_DELAY_INFOfmt */ 9186 /* nFields */ 18, 9187 /* *fields */ soc_ENQ_CT_DATA_DELAY_INFO_BCM56560_A0fmt_fields, 9188 /* bits */ 338, 9189 /* flags */ 0, 9190 }, 9191 #endif /* chips */ 9192 9193 #if defined(BCM_56670_A0) 9194 { /* SOC_FORMAT_INT_ENQ_CT_DATA_DELAY_INFO_BCM56670_A0fmt */ 9195 /* format ENQ_CT_DATA_DELAY_INFOfmt */ 9196 /* nFields */ 18, 9197 /* *fields */ soc_ENQ_CT_DATA_DELAY_INFO_BCM56670_A0fmt_fields, 9198 /* bits */ 312, 9199 /* flags */ 0, 9200 }, 9201 #endif /* chips */ 9202 9203 #if defined(BCM_56670_B0) 9204 { /* SOC_FORMAT_INT_ENQ_CT_DATA_DELAY_INFO_BCM56670_B0fmt */ 9205 /* format ENQ_CT_DATA_DELAY_INFOfmt */ 9206 /* nFields */ 18, 9207 /* *fields */ soc_ENQ_CT_DATA_DELAY_INFO_BCM56670_A0fmt_fields, 9208 /* bits */ 312, 9209 /* flags */ 0, 9210 }, 9211 #endif /* chips */ 9212 9213 #if defined(BCM_56800_A0) 9214 { /* SOC_FORMAT_INT_ENQ_DEFfmt */ 9215 /* format ENQ_DEFfmt */ 9216 /* nFields */ 1, 9217 /* *fields */ soc_ENQ_DEFfmt_fields, 9218 /* bits */ 14, 9219 /* flags */ 0, 9220 }, 9221 #endif /* chips */ 9222 9223 #if defined(BCM_56334_A0) 9224 { /* SOC_FORMAT_INT_ENQ_DEF_BCM56334_A0fmt */ 9225 /* format ENQ_DEFfmt */ 9226 /* nFields */ 1, 9227 /* *fields */ soc_ENQ_DEFfmt_fields, 9228 /* bits */ 14, 9229 /* flags */ 0, 9230 }, 9231 #endif /* chips */ 9232 9233 #if defined(BCM_56334_B0) 9234 { /* SOC_FORMAT_INT_ENQ_DEF_BCM56334_B0fmt */ 9235 /* format ENQ_DEFfmt */ 9236 /* nFields */ 1, 9237 /* *fields */ soc_ENQ_DEFfmt_fields, 9238 /* bits */ 14, 9239 /* flags */ 0, 9240 }, 9241 #endif /* chips */ 9242 9243 #if defined(BCM_56440_A0) 9244 { /* SOC_FORMAT_INT_ENQ_DEF_BCM56440_A0fmt */ 9245 /* format ENQ_DEFfmt */ 9246 /* nFields */ 1, 9247 /* *fields */ soc_ENQ_DEF_BCM56840_A0fmt_fields, 9248 /* bits */ 16, 9249 /* flags */ 0, 9250 }, 9251 #endif /* chips */ 9252 9253 #if defined(BCM_56440_B0) 9254 { /* SOC_FORMAT_INT_ENQ_DEF_BCM56440_B0fmt */ 9255 /* format ENQ_DEFfmt */ 9256 /* nFields */ 1, 9257 /* *fields */ soc_ENQ_DEF_BCM56840_A0fmt_fields, 9258 /* bits */ 16, 9259 /* flags */ 0, 9260 }, 9261 #endif /* chips */ 9262 9263 #if defined(BCM_56450_A0) 9264 { /* SOC_FORMAT_INT_ENQ_DEF_BCM56450_A0fmt */ 9265 /* format ENQ_DEFfmt */ 9266 /* nFields */ 1, 9267 /* *fields */ soc_ENQ_DEF_BCM56450_A0fmt_fields, 9268 /* bits */ 16, 9269 /* flags */ 0, 9270 }, 9271 #endif /* chips */ 9272 9273 #if defined(BCM_56450_B0) 9274 { /* SOC_FORMAT_INT_ENQ_DEF_BCM56450_B0fmt */ 9275 /* format ENQ_DEFfmt */ 9276 /* nFields */ 1, 9277 /* *fields */ soc_ENQ_DEF_BCM56450_A0fmt_fields, 9278 /* bits */ 16, 9279 /* flags */ 0, 9280 }, 9281 #endif /* chips */ 9282 9283 #if defined(BCM_56450_B1) 9284 { /* SOC_FORMAT_INT_ENQ_DEF_BCM56450_B1fmt */ 9285 /* format ENQ_DEFfmt */ 9286 /* nFields */ 1, 9287 /* *fields */ soc_ENQ_DEF_BCM56450_A0fmt_fields, 9288 /* bits */ 16, 9289 /* flags */ 0, 9290 }, 9291 #endif /* chips */ 9292 9293 #if defined(BCM_56524_A0) 9294 { /* SOC_FORMAT_INT_ENQ_DEF_BCM56524_A0fmt */ 9295 /* format ENQ_DEFfmt */ 9296 /* nFields */ 1, 9297 /* *fields */ soc_ENQ_DEFfmt_fields, 9298 /* bits */ 14, 9299 /* flags */ 0, 9300 }, 9301 #endif /* chips */ 9302 9303 #if defined(BCM_56524_B0) 9304 { /* SOC_FORMAT_INT_ENQ_DEF_BCM56524_B0fmt */ 9305 /* format ENQ_DEFfmt */ 9306 /* nFields */ 1, 9307 /* *fields */ soc_ENQ_DEFfmt_fields, 9308 /* bits */ 14, 9309 /* flags */ 0, 9310 }, 9311 #endif /* chips */ 9312 9313 #if defined(BCM_56624_A0) 9314 { /* SOC_FORMAT_INT_ENQ_DEF_BCM56624_A0fmt */ 9315 /* format ENQ_DEFfmt */ 9316 /* nFields */ 1, 9317 /* *fields */ soc_ENQ_DEFfmt_fields, 9318 /* bits */ 14, 9319 /* flags */ 0, 9320 }, 9321 #endif /* chips */ 9322 9323 #if defined(BCM_56624_B0) 9324 { /* SOC_FORMAT_INT_ENQ_DEF_BCM56624_B0fmt */ 9325 /* format ENQ_DEFfmt */ 9326 /* nFields */ 1, 9327 /* *fields */ soc_ENQ_DEFfmt_fields, 9328 /* bits */ 14, 9329 /* flags */ 0, 9330 }, 9331 #endif /* chips */ 9332 9333 #if defined(BCM_56634_A0) 9334 { /* SOC_FORMAT_INT_ENQ_DEF_BCM56634_A0fmt */ 9335 /* format ENQ_DEFfmt */ 9336 /* nFields */ 1, 9337 /* *fields */ soc_ENQ_DEFfmt_fields, 9338 /* bits */ 14, 9339 /* flags */ 0, 9340 }, 9341 #endif /* chips */ 9342 9343 #if defined(BCM_56634_B0) 9344 { /* SOC_FORMAT_INT_ENQ_DEF_BCM56634_B0fmt */ 9345 /* format ENQ_DEFfmt */ 9346 /* nFields */ 1, 9347 /* *fields */ soc_ENQ_DEFfmt_fields, 9348 /* bits */ 14, 9349 /* flags */ 0, 9350 }, 9351 #endif /* chips */ 9352 9353 #if defined(BCM_56680_A0) 9354 { /* SOC_FORMAT_INT_ENQ_DEF_BCM56680_A0fmt */ 9355 /* format ENQ_DEFfmt */ 9356 /* nFields */ 1, 9357 /* *fields */ soc_ENQ_DEFfmt_fields, 9358 /* bits */ 14, 9359 /* flags */ 0, 9360 }, 9361 #endif /* chips */ 9362 9363 #if defined(BCM_56680_B0) 9364 { /* SOC_FORMAT_INT_ENQ_DEF_BCM56680_B0fmt */ 9365 /* format ENQ_DEFfmt */ 9366 /* nFields */ 1, 9367 /* *fields */ soc_ENQ_DEFfmt_fields, 9368 /* bits */ 14, 9369 /* flags */ 0, 9370 }, 9371 #endif /* chips */ 9372 9373 #if defined(BCM_56685_A0) 9374 { /* SOC_FORMAT_INT_ENQ_DEF_BCM56685_A0fmt */ 9375 /* format ENQ_DEFfmt */ 9376 /* nFields */ 1, 9377 /* *fields */ soc_ENQ_DEFfmt_fields, 9378 /* bits */ 14, 9379 /* flags */ 0, 9380 }, 9381 #endif /* chips */ 9382 9383 #if defined(BCM_56685_B0) 9384 { /* SOC_FORMAT_INT_ENQ_DEF_BCM56685_B0fmt */ 9385 /* format ENQ_DEFfmt */ 9386 /* nFields */ 1, 9387 /* *fields */ soc_ENQ_DEFfmt_fields, 9388 /* bits */ 14, 9389 /* flags */ 0, 9390 }, 9391 #endif /* chips */ 9392 9393 #if defined(BCM_56725_A0) 9394 { /* SOC_FORMAT_INT_ENQ_DEF_BCM56725_A0fmt */ 9395 /* format ENQ_DEFfmt */ 9396 /* nFields */ 1, 9397 /* *fields */ soc_ENQ_DEFfmt_fields, 9398 /* bits */ 14, 9399 /* flags */ 0, 9400 }, 9401 #endif /* chips */ 9402 9403 #if defined(BCM_56820_A0) 9404 { /* SOC_FORMAT_INT_ENQ_DEF_BCM56820_A0fmt */ 9405 /* format ENQ_DEFfmt */ 9406 /* nFields */ 1, 9407 /* *fields */ soc_ENQ_DEFfmt_fields, 9408 /* bits */ 14, 9409 /* flags */ 0, 9410 }, 9411 #endif /* chips */ 9412 9413 #if defined(BCM_56840_A0) 9414 { /* SOC_FORMAT_INT_ENQ_DEF_BCM56840_A0fmt */ 9415 /* format ENQ_DEFfmt */ 9416 /* nFields */ 1, 9417 /* *fields */ soc_ENQ_DEF_BCM56840_A0fmt_fields, 9418 /* bits */ 16, 9419 /* flags */ 0, 9420 }, 9421 #endif /* chips */ 9422 9423 #if defined(BCM_56840_B0) 9424 { /* SOC_FORMAT_INT_ENQ_DEF_BCM56840_B0fmt */ 9425 /* format ENQ_DEFfmt */ 9426 /* nFields */ 1, 9427 /* *fields */ soc_ENQ_DEF_BCM56840_A0fmt_fields, 9428 /* bits */ 16, 9429 /* flags */ 0, 9430 }, 9431 #endif /* chips */ 9432 9433 #if defined(BCM_88732_A0) 9434 { /* SOC_FORMAT_INT_ENQ_DEF_BCM88732_A0fmt */ 9435 /* format ENQ_DEFfmt */ 9436 /* nFields */ 1, 9437 /* *fields */ soc_ENQ_DEF_BCM88732_A0fmt_fields, 9438 /* bits */ 17, 9439 /* flags */ 0, 9440 }, 9441 #endif /* chips */ 9442 9443 #if defined(BCM_56634_A0) || defined(BCM_56634_B0) 9444 { /* SOC_FORMAT_INT_ENQ_DELAY_HOLD_INFOfmt */ 9445 /* format ENQ_DELAY_HOLD_INFOfmt */ 9446 /* nFields */ 9, 9447 /* *fields */ soc_ENQ_DELAY_HOLD_INFOfmt_fields, 9448 /* bits */ 110, 9449 /* flags */ 0, 9450 }, 9451 #endif /* chips */ 9452 9453 #if defined(BCM_56524_A0) 9454 { /* SOC_FORMAT_INT_ENQ_DELAY_HOLD_INFO_BCM56524_A0fmt */ 9455 /* format ENQ_DELAY_HOLD_INFOfmt */ 9456 /* nFields */ 9, 9457 /* *fields */ soc_ENQ_DELAY_HOLD_INFOfmt_fields, 9458 /* bits */ 110, 9459 /* flags */ 0, 9460 }, 9461 #endif /* chips */ 9462 9463 #if defined(BCM_56524_B0) 9464 { /* SOC_FORMAT_INT_ENQ_DELAY_HOLD_INFO_BCM56524_B0fmt */ 9465 /* format ENQ_DELAY_HOLD_INFOfmt */ 9466 /* nFields */ 9, 9467 /* *fields */ soc_ENQ_DELAY_HOLD_INFOfmt_fields, 9468 /* bits */ 110, 9469 /* flags */ 0, 9470 }, 9471 #endif /* chips */ 9472 9473 #if defined(BCM_56685_A0) 9474 { /* SOC_FORMAT_INT_ENQ_DELAY_HOLD_INFO_BCM56685_A0fmt */ 9475 /* format ENQ_DELAY_HOLD_INFOfmt */ 9476 /* nFields */ 9, 9477 /* *fields */ soc_ENQ_DELAY_HOLD_INFOfmt_fields, 9478 /* bits */ 110, 9479 /* flags */ 0, 9480 }, 9481 #endif /* chips */ 9482 9483 #if defined(BCM_56685_B0) 9484 { /* SOC_FORMAT_INT_ENQ_DELAY_HOLD_INFO_BCM56685_B0fmt */ 9485 /* format ENQ_DELAY_HOLD_INFOfmt */ 9486 /* nFields */ 9, 9487 /* *fields */ soc_ENQ_DELAY_HOLD_INFOfmt_fields, 9488 /* bits */ 110, 9489 /* flags */ 0, 9490 }, 9491 #endif /* chips */ 9492 9493 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) 9494 { /* SOC_FORMAT_INT_ENQ_EXT_PTRfmt */ 9495 /* format ENQ_EXT_PTRfmt */ 9496 /* nFields */ 1, 9497 /* *fields */ soc_ENQ_EXT_PTRfmt_fields, 9498 /* bits */ 18, 9499 /* flags */ 0, 9500 }, 9501 #endif /* chips */ 9502 9503 #if defined(BCM_56260_A0) 9504 { /* SOC_FORMAT_INT_ENQ_EXT_PTR_BCM56260_A0fmt */ 9505 /* format ENQ_EXT_PTRfmt */ 9506 /* nFields */ 1, 9507 /* *fields */ soc_ENQ_EXT_PTR_BCM56260_A0fmt_fields, 9508 /* bits */ 16, 9509 /* flags */ 0, 9510 }, 9511 #endif /* chips */ 9512 9513 #if defined(BCM_56260_B0) 9514 { /* SOC_FORMAT_INT_ENQ_EXT_PTR_BCM56260_B0fmt */ 9515 /* format ENQ_EXT_PTRfmt */ 9516 /* nFields */ 1, 9517 /* *fields */ soc_ENQ_EXT_PTR_BCM56260_A0fmt_fields, 9518 /* bits */ 16, 9519 /* flags */ 0, 9520 }, 9521 #endif /* chips */ 9522 9523 #if defined(BCM_56450_A0) 9524 { /* SOC_FORMAT_INT_ENQ_EXT_PTR_BCM56450_A0fmt */ 9525 /* format ENQ_EXT_PTRfmt */ 9526 /* nFields */ 1, 9527 /* *fields */ soc_ENQ_EXT_PTR_BCM56450_A0fmt_fields, 9528 /* bits */ 18, 9529 /* flags */ 0, 9530 }, 9531 #endif /* chips */ 9532 9533 #if defined(BCM_56450_B0) 9534 { /* SOC_FORMAT_INT_ENQ_EXT_PTR_BCM56450_B0fmt */ 9535 /* format ENQ_EXT_PTRfmt */ 9536 /* nFields */ 1, 9537 /* *fields */ soc_ENQ_EXT_PTR_BCM56450_A0fmt_fields, 9538 /* bits */ 18, 9539 /* flags */ 0, 9540 }, 9541 #endif /* chips */ 9542 9543 #if defined(BCM_56450_B1) 9544 { /* SOC_FORMAT_INT_ENQ_EXT_PTR_BCM56450_B1fmt */ 9545 /* format ENQ_EXT_PTRfmt */ 9546 /* nFields */ 1, 9547 /* *fields */ soc_ENQ_EXT_PTR_BCM56450_A0fmt_fields, 9548 /* bits */ 18, 9549 /* flags */ 0, 9550 }, 9551 #endif /* chips */ 9552 9553 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) 9554 { /* SOC_FORMAT_INT_ENQ_INT_PTRfmt */ 9555 /* format ENQ_INT_PTRfmt */ 9556 /* nFields */ 1, 9557 /* *fields */ soc_ENQ_INT_PTRfmt_fields, 9558 /* bits */ 14, 9559 /* flags */ 0, 9560 }, 9561 #endif /* chips */ 9562 9563 #if defined(BCM_56260_A0) 9564 { /* SOC_FORMAT_INT_ENQ_INT_PTR_BCM56260_A0fmt */ 9565 /* format ENQ_INT_PTRfmt */ 9566 /* nFields */ 1, 9567 /* *fields */ soc_ENQ_INT_PTR_BCM56260_A0fmt_fields, 9568 /* bits */ 14, 9569 /* flags */ 0, 9570 }, 9571 #endif /* chips */ 9572 9573 #if defined(BCM_56260_B0) 9574 { /* SOC_FORMAT_INT_ENQ_INT_PTR_BCM56260_B0fmt */ 9575 /* format ENQ_INT_PTRfmt */ 9576 /* nFields */ 1, 9577 /* *fields */ soc_ENQ_INT_PTR_BCM56260_A0fmt_fields, 9578 /* bits */ 14, 9579 /* flags */ 0, 9580 }, 9581 #endif /* chips */ 9582 9583 #if defined(BCM_56270_A0) 9584 { /* SOC_FORMAT_INT_ENQ_INT_PTR_BCM56270_A0fmt */ 9585 /* format ENQ_INT_PTRfmt */ 9586 /* nFields */ 1, 9587 /* *fields */ soc_ENQ_INT_PTR_BCM56260_A0fmt_fields, 9588 /* bits */ 14, 9589 /* flags */ 0, 9590 }, 9591 #endif /* chips */ 9592 9593 #if defined(BCM_56450_A0) 9594 { /* SOC_FORMAT_INT_ENQ_INT_PTR_BCM56450_A0fmt */ 9595 /* format ENQ_INT_PTRfmt */ 9596 /* nFields */ 1, 9597 /* *fields */ soc_ENQ_INT_PTR_BCM56450_A0fmt_fields, 9598 /* bits */ 14, 9599 /* flags */ 0, 9600 }, 9601 #endif /* chips */ 9602 9603 #if defined(BCM_56450_B0) 9604 { /* SOC_FORMAT_INT_ENQ_INT_PTR_BCM56450_B0fmt */ 9605 /* format ENQ_INT_PTRfmt */ 9606 /* nFields */ 1, 9607 /* *fields */ soc_ENQ_INT_PTR_BCM56450_A0fmt_fields, 9608 /* bits */ 14, 9609 /* flags */ 0, 9610 }, 9611 #endif /* chips */ 9612 9613 #if defined(BCM_56450_B1) 9614 { /* SOC_FORMAT_INT_ENQ_INT_PTR_BCM56450_B1fmt */ 9615 /* format ENQ_INT_PTRfmt */ 9616 /* nFields */ 1, 9617 /* *fields */ soc_ENQ_INT_PTR_BCM56450_A0fmt_fields, 9618 /* bits */ 14, 9619 /* flags */ 0, 9620 }, 9621 #endif /* chips */ 9622 9623 #if defined(BCM_56850_A0) || defined(BCM_56860_A0) 9624 { /* SOC_FORMAT_INT_ENQ_PBI_SOP_INFOfmt */ 9625 /* format ENQ_PBI_SOP_INFOfmt */ 9626 /* nFields */ 27, 9627 /* *fields */ soc_ENQ_PBI_SOP_INFOfmt_fields, 9628 /* bits */ 329, 9629 /* flags */ 0, 9630 }, 9631 #endif /* chips */ 9632 9633 #if defined(BCM_56560_A0) 9634 { /* SOC_FORMAT_INT_ENQ_PBI_SOP_INFO_BCM56560_A0fmt */ 9635 /* format ENQ_PBI_SOP_INFOfmt */ 9636 /* nFields */ 28, 9637 /* *fields */ soc_ENQ_PBI_SOP_INFO_BCM56560_A0fmt_fields, 9638 /* bits */ 266, 9639 /* flags */ 0, 9640 }, 9641 #endif /* chips */ 9642 9643 #if defined(BCM_56560_B0) 9644 { /* SOC_FORMAT_INT_ENQ_PBI_SOP_INFO_BCM56560_B0fmt */ 9645 /* format ENQ_PBI_SOP_INFOfmt */ 9646 /* nFields */ 28, 9647 /* *fields */ soc_ENQ_PBI_SOP_INFO_BCM56560_A0fmt_fields, 9648 /* bits */ 266, 9649 /* flags */ 0, 9650 }, 9651 #endif /* chips */ 9652 9653 #if defined(BCM_56670_A0) 9654 { /* SOC_FORMAT_INT_ENQ_PBI_SOP_INFO_BCM56670_A0fmt */ 9655 /* format ENQ_PBI_SOP_INFOfmt */ 9656 /* nFields */ 28, 9657 /* *fields */ soc_ENQ_PBI_SOP_INFO_BCM56670_A0fmt_fields, 9658 /* bits */ 246, 9659 /* flags */ 0, 9660 }, 9661 #endif /* chips */ 9662 9663 #if defined(BCM_56670_B0) 9664 { /* SOC_FORMAT_INT_ENQ_PBI_SOP_INFO_BCM56670_B0fmt */ 9665 /* format ENQ_PBI_SOP_INFOfmt */ 9666 /* nFields */ 28, 9667 /* *fields */ soc_ENQ_PBI_SOP_INFO_BCM56670_A0fmt_fields, 9668 /* bits */ 246, 9669 /* flags */ 0, 9670 }, 9671 #endif /* chips */ 9672 9673 #if defined(BCM_56800_A0) 9674 { /* SOC_FORMAT_INT_ENQ_PIPEfmt */ 9675 /* format ENQ_PIPEfmt */ 9676 /* nFields */ 18, 9677 /* *fields */ soc_ENQ_PIPEfmt_fields, 9678 /* bits */ 102, 9679 /* flags */ 0, 9680 }, 9681 #endif /* chips */ 9682 9683 #if defined(BCM_56260_A0) 9684 { /* SOC_FORMAT_INT_ENQ_PIPE_BCM56260_A0fmt */ 9685 /* format ENQ_PIPEfmt */ 9686 /* nFields */ 55, 9687 /* *fields */ soc_ENQ_PIPE_BCM56260_A0fmt_fields, 9688 /* bits */ 411, 9689 /* flags */ 0, 9690 }, 9691 #endif /* chips */ 9692 9693 #if defined(BCM_56260_B0) 9694 { /* SOC_FORMAT_INT_ENQ_PIPE_BCM56260_B0fmt */ 9695 /* format ENQ_PIPEfmt */ 9696 /* nFields */ 55, 9697 /* *fields */ soc_ENQ_PIPE_BCM56260_A0fmt_fields, 9698 /* bits */ 411, 9699 /* flags */ 0, 9700 }, 9701 #endif /* chips */ 9702 9703 #if defined(BCM_56270_A0) 9704 { /* SOC_FORMAT_INT_ENQ_PIPE_BCM56270_A0fmt */ 9705 /* format ENQ_PIPEfmt */ 9706 /* nFields */ 43, 9707 /* *fields */ soc_ENQ_PIPE_BCM56270_A0fmt_fields, 9708 /* bits */ 240, 9709 /* flags */ 0, 9710 }, 9711 #endif /* chips */ 9712 9713 #if defined(BCM_56334_A0) 9714 { /* SOC_FORMAT_INT_ENQ_PIPE_BCM56334_A0fmt */ 9715 /* format ENQ_PIPEfmt */ 9716 /* nFields */ 28, 9717 /* *fields */ soc_ENQ_PIPE_BCM56334_A0fmt_fields, 9718 /* bits */ 192, 9719 /* flags */ 0, 9720 }, 9721 #endif /* chips */ 9722 9723 #if defined(BCM_56334_B0) 9724 { /* SOC_FORMAT_INT_ENQ_PIPE_BCM56334_B0fmt */ 9725 /* format ENQ_PIPEfmt */ 9726 /* nFields */ 28, 9727 /* *fields */ soc_ENQ_PIPE_BCM56334_A0fmt_fields, 9728 /* bits */ 192, 9729 /* flags */ 0, 9730 }, 9731 #endif /* chips */ 9732 9733 #if defined(BCM_56340_A0) 9734 { /* SOC_FORMAT_INT_ENQ_PIPE_BCM56340_A0fmt */ 9735 /* format ENQ_PIPEfmt */ 9736 /* nFields */ 31, 9737 /* *fields */ soc_ENQ_PIPE_BCM56640_A0fmt_fields, 9738 /* bits */ 251, 9739 /* flags */ 0, 9740 }, 9741 #endif /* chips */ 9742 9743 #if defined(BCM_56440_A0) 9744 { /* SOC_FORMAT_INT_ENQ_PIPE_BCM56440_A0fmt */ 9745 /* format ENQ_PIPEfmt */ 9746 /* nFields */ 46, 9747 /* *fields */ soc_ENQ_PIPE_BCM56440_A0fmt_fields, 9748 /* bits */ 253, 9749 /* flags */ 0, 9750 }, 9751 #endif /* chips */ 9752 9753 #if defined(BCM_56440_B0) 9754 { /* SOC_FORMAT_INT_ENQ_PIPE_BCM56440_B0fmt */ 9755 /* format ENQ_PIPEfmt */ 9756 /* nFields */ 46, 9757 /* *fields */ soc_ENQ_PIPE_BCM56440_A0fmt_fields, 9758 /* bits */ 253, 9759 /* flags */ 0, 9760 }, 9761 #endif /* chips */ 9762 9763 #if defined(BCM_56450_A0) 9764 { /* SOC_FORMAT_INT_ENQ_PIPE_BCM56450_A0fmt */ 9765 /* format ENQ_PIPEfmt */ 9766 /* nFields */ 55, 9767 /* *fields */ soc_ENQ_PIPE_BCM56450_A0fmt_fields, 9768 /* bits */ 581, 9769 /* flags */ 0, 9770 }, 9771 #endif /* chips */ 9772 9773 #if defined(BCM_56450_B0) 9774 { /* SOC_FORMAT_INT_ENQ_PIPE_BCM56450_B0fmt */ 9775 /* format ENQ_PIPEfmt */ 9776 /* nFields */ 55, 9777 /* *fields */ soc_ENQ_PIPE_BCM56450_A0fmt_fields, 9778 /* bits */ 581, 9779 /* flags */ 0, 9780 }, 9781 #endif /* chips */ 9782 9783 #if defined(BCM_56450_B1) 9784 { /* SOC_FORMAT_INT_ENQ_PIPE_BCM56450_B1fmt */ 9785 /* format ENQ_PIPEfmt */ 9786 /* nFields */ 55, 9787 /* *fields */ soc_ENQ_PIPE_BCM56450_A0fmt_fields, 9788 /* bits */ 581, 9789 /* flags */ 0, 9790 }, 9791 #endif /* chips */ 9792 9793 #if defined(BCM_56524_A0) 9794 { /* SOC_FORMAT_INT_ENQ_PIPE_BCM56524_A0fmt */ 9795 /* format ENQ_PIPEfmt */ 9796 /* nFields */ 33, 9797 /* *fields */ soc_ENQ_PIPE_BCM56634_A0fmt_fields, 9798 /* bits */ 310, 9799 /* flags */ 0, 9800 }, 9801 #endif /* chips */ 9802 9803 #if defined(BCM_56524_B0) 9804 { /* SOC_FORMAT_INT_ENQ_PIPE_BCM56524_B0fmt */ 9805 /* format ENQ_PIPEfmt */ 9806 /* nFields */ 33, 9807 /* *fields */ soc_ENQ_PIPE_BCM56634_A0fmt_fields, 9808 /* bits */ 310, 9809 /* flags */ 0, 9810 }, 9811 #endif /* chips */ 9812 9813 #if defined(BCM_56560_A0) 9814 { /* SOC_FORMAT_INT_ENQ_PIPE_BCM56560_A0fmt */ 9815 /* format ENQ_PIPEfmt */ 9816 /* nFields */ 29, 9817 /* *fields */ soc_ENQ_PIPE_BCM56560_A0fmt_fields, 9818 /* bits */ 297, 9819 /* flags */ 0, 9820 }, 9821 #endif /* chips */ 9822 9823 #if defined(BCM_56560_B0) 9824 { /* SOC_FORMAT_INT_ENQ_PIPE_BCM56560_B0fmt */ 9825 /* format ENQ_PIPEfmt */ 9826 /* nFields */ 29, 9827 /* *fields */ soc_ENQ_PIPE_BCM56560_A0fmt_fields, 9828 /* bits */ 297, 9829 /* flags */ 0, 9830 }, 9831 #endif /* chips */ 9832 9833 #if defined(BCM_56624_A0) 9834 { /* SOC_FORMAT_INT_ENQ_PIPE_BCM56624_A0fmt */ 9835 /* format ENQ_PIPEfmt */ 9836 /* nFields */ 28, 9837 /* *fields */ soc_ENQ_PIPE_BCM56624_A0fmt_fields, 9838 /* bits */ 267, 9839 /* flags */ 0, 9840 }, 9841 #endif /* chips */ 9842 9843 #if defined(BCM_56624_B0) 9844 { /* SOC_FORMAT_INT_ENQ_PIPE_BCM56624_B0fmt */ 9845 /* format ENQ_PIPEfmt */ 9846 /* nFields */ 28, 9847 /* *fields */ soc_ENQ_PIPE_BCM56624_A0fmt_fields, 9848 /* bits */ 267, 9849 /* flags */ 0, 9850 }, 9851 #endif /* chips */ 9852 9853 #if defined(BCM_56634_A0) 9854 { /* SOC_FORMAT_INT_ENQ_PIPE_BCM56634_A0fmt */ 9855 /* format ENQ_PIPEfmt */ 9856 /* nFields */ 33, 9857 /* *fields */ soc_ENQ_PIPE_BCM56634_A0fmt_fields, 9858 /* bits */ 310, 9859 /* flags */ 0, 9860 }, 9861 #endif /* chips */ 9862 9863 #if defined(BCM_56634_B0) 9864 { /* SOC_FORMAT_INT_ENQ_PIPE_BCM56634_B0fmt */ 9865 /* format ENQ_PIPEfmt */ 9866 /* nFields */ 33, 9867 /* *fields */ soc_ENQ_PIPE_BCM56634_A0fmt_fields, 9868 /* bits */ 310, 9869 /* flags */ 0, 9870 }, 9871 #endif /* chips */ 9872 9873 #if defined(BCM_56640_A0) 9874 { /* SOC_FORMAT_INT_ENQ_PIPE_BCM56640_A0fmt */ 9875 /* format ENQ_PIPEfmt */ 9876 /* nFields */ 31, 9877 /* *fields */ soc_ENQ_PIPE_BCM56640_A0fmt_fields, 9878 /* bits */ 251, 9879 /* flags */ 0, 9880 }, 9881 #endif /* chips */ 9882 9883 #if defined(BCM_56670_A0) 9884 { /* SOC_FORMAT_INT_ENQ_PIPE_BCM56670_A0fmt */ 9885 /* format ENQ_PIPEfmt */ 9886 /* nFields */ 32, 9887 /* *fields */ soc_ENQ_PIPE_BCM56670_A0fmt_fields, 9888 /* bits */ 281, 9889 /* flags */ 0, 9890 }, 9891 #endif /* chips */ 9892 9893 #if defined(BCM_56670_B0) 9894 { /* SOC_FORMAT_INT_ENQ_PIPE_BCM56670_B0fmt */ 9895 /* format ENQ_PIPEfmt */ 9896 /* nFields */ 32, 9897 /* *fields */ soc_ENQ_PIPE_BCM56670_A0fmt_fields, 9898 /* bits */ 281, 9899 /* flags */ 0, 9900 }, 9901 #endif /* chips */ 9902 9903 #if defined(BCM_56680_A0) 9904 { /* SOC_FORMAT_INT_ENQ_PIPE_BCM56680_A0fmt */ 9905 /* format ENQ_PIPEfmt */ 9906 /* nFields */ 28, 9907 /* *fields */ soc_ENQ_PIPE_BCM56624_A0fmt_fields, 9908 /* bits */ 267, 9909 /* flags */ 0, 9910 }, 9911 #endif /* chips */ 9912 9913 #if defined(BCM_56680_B0) 9914 { /* SOC_FORMAT_INT_ENQ_PIPE_BCM56680_B0fmt */ 9915 /* format ENQ_PIPEfmt */ 9916 /* nFields */ 28, 9917 /* *fields */ soc_ENQ_PIPE_BCM56624_A0fmt_fields, 9918 /* bits */ 267, 9919 /* flags */ 0, 9920 }, 9921 #endif /* chips */ 9922 9923 #if defined(BCM_56685_A0) 9924 { /* SOC_FORMAT_INT_ENQ_PIPE_BCM56685_A0fmt */ 9925 /* format ENQ_PIPEfmt */ 9926 /* nFields */ 33, 9927 /* *fields */ soc_ENQ_PIPE_BCM56634_A0fmt_fields, 9928 /* bits */ 310, 9929 /* flags */ 0, 9930 }, 9931 #endif /* chips */ 9932 9933 #if defined(BCM_56685_B0) 9934 { /* SOC_FORMAT_INT_ENQ_PIPE_BCM56685_B0fmt */ 9935 /* format ENQ_PIPEfmt */ 9936 /* nFields */ 33, 9937 /* *fields */ soc_ENQ_PIPE_BCM56634_A0fmt_fields, 9938 /* bits */ 310, 9939 /* flags */ 0, 9940 }, 9941 #endif /* chips */ 9942 9943 #if defined(BCM_56725_A0) 9944 { /* SOC_FORMAT_INT_ENQ_PIPE_BCM56725_A0fmt */ 9945 /* format ENQ_PIPEfmt */ 9946 /* nFields */ 26, 9947 /* *fields */ soc_ENQ_PIPE_BCM56820_A0fmt_fields, 9948 /* bits */ 170, 9949 /* flags */ 0, 9950 }, 9951 #endif /* chips */ 9952 9953 #if defined(BCM_56820_A0) 9954 { /* SOC_FORMAT_INT_ENQ_PIPE_BCM56820_A0fmt */ 9955 /* format ENQ_PIPEfmt */ 9956 /* nFields */ 26, 9957 /* *fields */ soc_ENQ_PIPE_BCM56820_A0fmt_fields, 9958 /* bits */ 170, 9959 /* flags */ 0, 9960 }, 9961 #endif /* chips */ 9962 9963 #if defined(BCM_56840_A0) 9964 { /* SOC_FORMAT_INT_ENQ_PIPE_BCM56840_A0fmt */ 9965 /* format ENQ_PIPEfmt */ 9966 /* nFields */ 26, 9967 /* *fields */ soc_ENQ_PIPE_BCM56840_A0fmt_fields, 9968 /* bits */ 248, 9969 /* flags */ 0, 9970 }, 9971 #endif /* chips */ 9972 9973 #if defined(BCM_56840_B0) 9974 { /* SOC_FORMAT_INT_ENQ_PIPE_BCM56840_B0fmt */ 9975 /* format ENQ_PIPEfmt */ 9976 /* nFields */ 26, 9977 /* *fields */ soc_ENQ_PIPE_BCM56840_A0fmt_fields, 9978 /* bits */ 248, 9979 /* flags */ 0, 9980 }, 9981 #endif /* chips */ 9982 9983 #if defined(BCM_56850_A0) 9984 { /* SOC_FORMAT_INT_ENQ_PIPE_BCM56850_A0fmt */ 9985 /* format ENQ_PIPEfmt */ 9986 /* nFields */ 29, 9987 /* *fields */ soc_ENQ_PIPE_BCM56850_A0fmt_fields, 9988 /* bits */ 365, 9989 /* flags */ 0, 9990 }, 9991 #endif /* chips */ 9992 9993 #if defined(BCM_56860_A0) 9994 { /* SOC_FORMAT_INT_ENQ_PIPE_BCM56860_A0fmt */ 9995 /* format ENQ_PIPEfmt */ 9996 /* nFields */ 29, 9997 /* *fields */ soc_ENQ_PIPE_BCM56850_A0fmt_fields, 9998 /* bits */ 365, 9999 /* flags */ 0, 10000 }, 10001 #endif /* chips */ 10002 10003 #if defined(BCM_88732_A0) 10004 { /* SOC_FORMAT_INT_ENQ_PIPE_BCM88732_A0fmt */ 10005 /* format ENQ_PIPEfmt */ 10006 /* nFields */ 13, 10007 /* *fields */ soc_ENQ_PIPE_BCM88732_A0fmt_fields, 10008 /* bits */ 78, 10009 /* flags */ 0, 10010 }, 10011 #endif /* chips */ 10012 10013 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) 10014 { /* SOC_FORMAT_INT_ENQ_POST_PAC_SAE_SRCPORT_CTXT_FIFOfmt */ 10015 /* format ENQ_POST_PAC_SAE_SRCPORT_CTXT_FIFOfmt */ 10016 /* nFields */ 4, 10017 /* *fields */ soc_ENQ_POST_PAC_SAE_SRCPORT_CTXT_FIFOfmt_fields, 10018 /* bits */ 209, 10019 /* flags */ 0, 10020 }, 10021 #endif /* chips */ 10022 10023 #if defined(BCM_56270_A0) 10024 { /* SOC_FORMAT_INT_ENQ_POST_PAC_SAE_SRCPORT_CTXT_FIFO_BCM56270_A0fmt */ 10025 /* format ENQ_POST_PAC_SAE_SRCPORT_CTXT_FIFOfmt */ 10026 /* nFields */ 5, 10027 /* *fields */ soc_ENQ_POST_PAC_SAE_SRCPORT_CTXT_FIFO_BCM56270_A0fmt_fields, 10028 /* bits */ 22, 10029 /* flags */ 0, 10030 }, 10031 #endif /* chips */ 10032 10033 #if defined(BCM_56800_A0) 10034 { /* SOC_FORMAT_INT_ENQ_PREV_CELL_INFOfmt */ 10035 /* format ENQ_PREV_CELL_INFOfmt */ 10036 /* nFields */ 3, 10037 /* *fields */ soc_ENQ_PREV_CELL_INFOfmt_fields, 10038 /* bits */ 16, 10039 /* flags */ 0, 10040 }, 10041 #endif /* chips */ 10042 10043 #if defined(BCM_56334_A0) 10044 { /* SOC_FORMAT_INT_ENQ_PREV_CELL_INFO_BCM56334_A0fmt */ 10045 /* format ENQ_PREV_CELL_INFOfmt */ 10046 /* nFields */ 4, 10047 /* *fields */ soc_ENQ_PREV_CELL_INFO_BCM56334_A0fmt_fields, 10048 /* bits */ 17, 10049 /* flags */ 0, 10050 }, 10051 #endif /* chips */ 10052 10053 #if defined(BCM_56334_B0) 10054 { /* SOC_FORMAT_INT_ENQ_PREV_CELL_INFO_BCM56334_B0fmt */ 10055 /* format ENQ_PREV_CELL_INFOfmt */ 10056 /* nFields */ 4, 10057 /* *fields */ soc_ENQ_PREV_CELL_INFO_BCM56334_A0fmt_fields, 10058 /* bits */ 17, 10059 /* flags */ 0, 10060 }, 10061 #endif /* chips */ 10062 10063 #if defined(BCM_56340_A0) 10064 { /* SOC_FORMAT_INT_ENQ_PREV_CELL_INFO_BCM56340_A0fmt */ 10065 /* format ENQ_PREV_CELL_INFOfmt */ 10066 /* nFields */ 1, 10067 /* *fields */ soc_ENQ_PREV_CELL_INFO_BCM56640_A0fmt_fields, 10068 /* bits */ 15, 10069 /* flags */ 0, 10070 }, 10071 #endif /* chips */ 10072 10073 #if defined(BCM_56440_A0) 10074 { /* SOC_FORMAT_INT_ENQ_PREV_CELL_INFO_BCM56440_A0fmt */ 10075 /* format ENQ_PREV_CELL_INFOfmt */ 10076 /* nFields */ 1, 10077 /* *fields */ soc_ENQ_PREV_CELL_INFO_BCM56840_A0fmt_fields, 10078 /* bits */ 16, 10079 /* flags */ 0, 10080 }, 10081 #endif /* chips */ 10082 10083 #if defined(BCM_56440_B0) 10084 { /* SOC_FORMAT_INT_ENQ_PREV_CELL_INFO_BCM56440_B0fmt */ 10085 /* format ENQ_PREV_CELL_INFOfmt */ 10086 /* nFields */ 1, 10087 /* *fields */ soc_ENQ_PREV_CELL_INFO_BCM56840_A0fmt_fields, 10088 /* bits */ 16, 10089 /* flags */ 0, 10090 }, 10091 #endif /* chips */ 10092 10093 #if defined(BCM_56450_A0) 10094 { /* SOC_FORMAT_INT_ENQ_PREV_CELL_INFO_BCM56450_A0fmt */ 10095 /* format ENQ_PREV_CELL_INFOfmt */ 10096 /* nFields */ 1, 10097 /* *fields */ soc_ENQ_PREV_CELL_INFO_BCM56450_A0fmt_fields, 10098 /* bits */ 16, 10099 /* flags */ 0, 10100 }, 10101 #endif /* chips */ 10102 10103 #if defined(BCM_56450_B0) 10104 { /* SOC_FORMAT_INT_ENQ_PREV_CELL_INFO_BCM56450_B0fmt */ 10105 /* format ENQ_PREV_CELL_INFOfmt */ 10106 /* nFields */ 1, 10107 /* *fields */ soc_ENQ_PREV_CELL_INFO_BCM56450_A0fmt_fields, 10108 /* bits */ 16, 10109 /* flags */ 0, 10110 }, 10111 #endif /* chips */ 10112 10113 #if defined(BCM_56450_B1) 10114 { /* SOC_FORMAT_INT_ENQ_PREV_CELL_INFO_BCM56450_B1fmt */ 10115 /* format ENQ_PREV_CELL_INFOfmt */ 10116 /* nFields */ 1, 10117 /* *fields */ soc_ENQ_PREV_CELL_INFO_BCM56450_A0fmt_fields, 10118 /* bits */ 16, 10119 /* flags */ 0, 10120 }, 10121 #endif /* chips */ 10122 10123 #if defined(BCM_56524_A0) 10124 { /* SOC_FORMAT_INT_ENQ_PREV_CELL_INFO_BCM56524_A0fmt */ 10125 /* format ENQ_PREV_CELL_INFOfmt */ 10126 /* nFields */ 4, 10127 /* *fields */ soc_ENQ_PREV_CELL_INFO_BCM56624_A0fmt_fields, 10128 /* bits */ 18, 10129 /* flags */ 0, 10130 }, 10131 #endif /* chips */ 10132 10133 #if defined(BCM_56524_B0) 10134 { /* SOC_FORMAT_INT_ENQ_PREV_CELL_INFO_BCM56524_B0fmt */ 10135 /* format ENQ_PREV_CELL_INFOfmt */ 10136 /* nFields */ 4, 10137 /* *fields */ soc_ENQ_PREV_CELL_INFO_BCM56624_A0fmt_fields, 10138 /* bits */ 18, 10139 /* flags */ 0, 10140 }, 10141 #endif /* chips */ 10142 10143 #if defined(BCM_56560_A0) 10144 { /* SOC_FORMAT_INT_ENQ_PREV_CELL_INFO_BCM56560_A0fmt */ 10145 /* format ENQ_PREV_CELL_INFOfmt */ 10146 /* nFields */ 1, 10147 /* *fields */ soc_ENQ_PREV_CELL_INFO_BCM56560_A0fmt_fields, 10148 /* bits */ 16, 10149 /* flags */ 0, 10150 }, 10151 #endif /* chips */ 10152 10153 #if defined(BCM_56560_B0) 10154 { /* SOC_FORMAT_INT_ENQ_PREV_CELL_INFO_BCM56560_B0fmt */ 10155 /* format ENQ_PREV_CELL_INFOfmt */ 10156 /* nFields */ 1, 10157 /* *fields */ soc_ENQ_PREV_CELL_INFO_BCM56560_A0fmt_fields, 10158 /* bits */ 16, 10159 /* flags */ 0, 10160 }, 10161 #endif /* chips */ 10162 10163 #if defined(BCM_56624_A0) 10164 { /* SOC_FORMAT_INT_ENQ_PREV_CELL_INFO_BCM56624_A0fmt */ 10165 /* format ENQ_PREV_CELL_INFOfmt */ 10166 /* nFields */ 4, 10167 /* *fields */ soc_ENQ_PREV_CELL_INFO_BCM56624_A0fmt_fields, 10168 /* bits */ 18, 10169 /* flags */ 0, 10170 }, 10171 #endif /* chips */ 10172 10173 #if defined(BCM_56624_B0) 10174 { /* SOC_FORMAT_INT_ENQ_PREV_CELL_INFO_BCM56624_B0fmt */ 10175 /* format ENQ_PREV_CELL_INFOfmt */ 10176 /* nFields */ 4, 10177 /* *fields */ soc_ENQ_PREV_CELL_INFO_BCM56624_A0fmt_fields, 10178 /* bits */ 18, 10179 /* flags */ 0, 10180 }, 10181 #endif /* chips */ 10182 10183 #if defined(BCM_56634_A0) 10184 { /* SOC_FORMAT_INT_ENQ_PREV_CELL_INFO_BCM56634_A0fmt */ 10185 /* format ENQ_PREV_CELL_INFOfmt */ 10186 /* nFields */ 4, 10187 /* *fields */ soc_ENQ_PREV_CELL_INFO_BCM56624_A0fmt_fields, 10188 /* bits */ 18, 10189 /* flags */ 0, 10190 }, 10191 #endif /* chips */ 10192 10193 #if defined(BCM_56634_B0) 10194 { /* SOC_FORMAT_INT_ENQ_PREV_CELL_INFO_BCM56634_B0fmt */ 10195 /* format ENQ_PREV_CELL_INFOfmt */ 10196 /* nFields */ 4, 10197 /* *fields */ soc_ENQ_PREV_CELL_INFO_BCM56624_A0fmt_fields, 10198 /* bits */ 18, 10199 /* flags */ 0, 10200 }, 10201 #endif /* chips */ 10202 10203 #if defined(BCM_56640_A0) 10204 { /* SOC_FORMAT_INT_ENQ_PREV_CELL_INFO_BCM56640_A0fmt */ 10205 /* format ENQ_PREV_CELL_INFOfmt */ 10206 /* nFields */ 1, 10207 /* *fields */ soc_ENQ_PREV_CELL_INFO_BCM56640_A0fmt_fields, 10208 /* bits */ 15, 10209 /* flags */ 0, 10210 }, 10211 #endif /* chips */ 10212 10213 #if defined(BCM_56670_A0) 10214 { /* SOC_FORMAT_INT_ENQ_PREV_CELL_INFO_BCM56670_A0fmt */ 10215 /* format ENQ_PREV_CELL_INFOfmt */ 10216 /* nFields */ 1, 10217 /* *fields */ soc_ENQ_PREV_CELL_INFO_BCM56670_A0fmt_fields, 10218 /* bits */ 15, 10219 /* flags */ 0, 10220 }, 10221 #endif /* chips */ 10222 10223 #if defined(BCM_56670_B0) 10224 { /* SOC_FORMAT_INT_ENQ_PREV_CELL_INFO_BCM56670_B0fmt */ 10225 /* format ENQ_PREV_CELL_INFOfmt */ 10226 /* nFields */ 1, 10227 /* *fields */ soc_ENQ_PREV_CELL_INFO_BCM56670_A0fmt_fields, 10228 /* bits */ 15, 10229 /* flags */ 0, 10230 }, 10231 #endif /* chips */ 10232 10233 #if defined(BCM_56680_A0) 10234 { /* SOC_FORMAT_INT_ENQ_PREV_CELL_INFO_BCM56680_A0fmt */ 10235 /* format ENQ_PREV_CELL_INFOfmt */ 10236 /* nFields */ 4, 10237 /* *fields */ soc_ENQ_PREV_CELL_INFO_BCM56624_A0fmt_fields, 10238 /* bits */ 18, 10239 /* flags */ 0, 10240 }, 10241 #endif /* chips */ 10242 10243 #if defined(BCM_56680_B0) 10244 { /* SOC_FORMAT_INT_ENQ_PREV_CELL_INFO_BCM56680_B0fmt */ 10245 /* format ENQ_PREV_CELL_INFOfmt */ 10246 /* nFields */ 4, 10247 /* *fields */ soc_ENQ_PREV_CELL_INFO_BCM56624_A0fmt_fields, 10248 /* bits */ 18, 10249 /* flags */ 0, 10250 }, 10251 #endif /* chips */ 10252 10253 #if defined(BCM_56685_A0) 10254 { /* SOC_FORMAT_INT_ENQ_PREV_CELL_INFO_BCM56685_A0fmt */ 10255 /* format ENQ_PREV_CELL_INFOfmt */ 10256 /* nFields */ 4, 10257 /* *fields */ soc_ENQ_PREV_CELL_INFO_BCM56624_A0fmt_fields, 10258 /* bits */ 18, 10259 /* flags */ 0, 10260 }, 10261 #endif /* chips */ 10262 10263 #if defined(BCM_56685_B0) 10264 { /* SOC_FORMAT_INT_ENQ_PREV_CELL_INFO_BCM56685_B0fmt */ 10265 /* format ENQ_PREV_CELL_INFOfmt */ 10266 /* nFields */ 4, 10267 /* *fields */ soc_ENQ_PREV_CELL_INFO_BCM56624_A0fmt_fields, 10268 /* bits */ 18, 10269 /* flags */ 0, 10270 }, 10271 #endif /* chips */ 10272 10273 #if defined(BCM_56725_A0) 10274 { /* SOC_FORMAT_INT_ENQ_PREV_CELL_INFO_BCM56725_A0fmt */ 10275 /* format ENQ_PREV_CELL_INFOfmt */ 10276 /* nFields */ 3, 10277 /* *fields */ soc_ENQ_PREV_CELL_INFOfmt_fields, 10278 /* bits */ 16, 10279 /* flags */ 0, 10280 }, 10281 #endif /* chips */ 10282 10283 #if defined(BCM_56820_A0) 10284 { /* SOC_FORMAT_INT_ENQ_PREV_CELL_INFO_BCM56820_A0fmt */ 10285 /* format ENQ_PREV_CELL_INFOfmt */ 10286 /* nFields */ 3, 10287 /* *fields */ soc_ENQ_PREV_CELL_INFOfmt_fields, 10288 /* bits */ 16, 10289 /* flags */ 0, 10290 }, 10291 #endif /* chips */ 10292 10293 #if defined(BCM_56840_A0) 10294 { /* SOC_FORMAT_INT_ENQ_PREV_CELL_INFO_BCM56840_A0fmt */ 10295 /* format ENQ_PREV_CELL_INFOfmt */ 10296 /* nFields */ 1, 10297 /* *fields */ soc_ENQ_PREV_CELL_INFO_BCM56840_A0fmt_fields, 10298 /* bits */ 16, 10299 /* flags */ 0, 10300 }, 10301 #endif /* chips */ 10302 10303 #if defined(BCM_56840_B0) 10304 { /* SOC_FORMAT_INT_ENQ_PREV_CELL_INFO_BCM56840_B0fmt */ 10305 /* format ENQ_PREV_CELL_INFOfmt */ 10306 /* nFields */ 1, 10307 /* *fields */ soc_ENQ_PREV_CELL_INFO_BCM56840_A0fmt_fields, 10308 /* bits */ 16, 10309 /* flags */ 0, 10310 }, 10311 #endif /* chips */ 10312 10313 #if defined(BCM_56850_A0) 10314 { /* SOC_FORMAT_INT_ENQ_PREV_CELL_INFO_BCM56850_A0fmt */ 10315 /* format ENQ_PREV_CELL_INFOfmt */ 10316 /* nFields */ 1, 10317 /* *fields */ soc_ENQ_PREV_CELL_INFO_BCM56850_A0fmt_fields, 10318 /* bits */ 17, 10319 /* flags */ 0, 10320 }, 10321 #endif /* chips */ 10322 10323 #if defined(BCM_56860_A0) 10324 { /* SOC_FORMAT_INT_ENQ_PREV_CELL_INFO_BCM56860_A0fmt */ 10325 /* format ENQ_PREV_CELL_INFOfmt */ 10326 /* nFields */ 1, 10327 /* *fields */ soc_ENQ_PREV_CELL_INFO_BCM56850_A0fmt_fields, 10328 /* bits */ 17, 10329 /* flags */ 0, 10330 }, 10331 #endif /* chips */ 10332 10333 #if defined(BCM_88732_A0) 10334 { /* SOC_FORMAT_INT_ENQ_PREV_CELL_INFO_BCM88732_A0fmt */ 10335 /* format ENQ_PREV_CELL_INFOfmt */ 10336 /* nFields */ 3, 10337 /* *fields */ soc_ENQ_PREV_CELL_INFO_BCM88732_A0fmt_fields, 10338 /* bits */ 35, 10339 /* flags */ 0, 10340 }, 10341 #endif /* chips */ 10342 10343 #if defined(BCM_56800_A0) 10344 { /* SOC_FORMAT_INT_ENQ_SOP_CELLHDRfmt */ 10345 /* format ENQ_SOP_CELLHDRfmt */ 10346 /* nFields */ 4, 10347 /* *fields */ soc_ENQ_SOP_CELLHDRfmt_fields, 10348 /* bits */ 11, 10349 /* flags */ 0, 10350 }, 10351 #endif /* chips */ 10352 10353 #if defined(BCM_56334_A0) 10354 { /* SOC_FORMAT_INT_ENQ_SOP_CELLHDR_BCM56334_A0fmt */ 10355 /* format ENQ_SOP_CELLHDRfmt */ 10356 /* nFields */ 2, 10357 /* *fields */ soc_ENQ_SOP_CELLHDR_BCM56624_A0fmt_fields, 10358 /* bits */ 2, 10359 /* flags */ 0, 10360 }, 10361 #endif /* chips */ 10362 10363 #if defined(BCM_56334_B0) 10364 { /* SOC_FORMAT_INT_ENQ_SOP_CELLHDR_BCM56334_B0fmt */ 10365 /* format ENQ_SOP_CELLHDRfmt */ 10366 /* nFields */ 2, 10367 /* *fields */ soc_ENQ_SOP_CELLHDR_BCM56624_A0fmt_fields, 10368 /* bits */ 2, 10369 /* flags */ 0, 10370 }, 10371 #endif /* chips */ 10372 10373 #if defined(BCM_56440_A0) 10374 { /* SOC_FORMAT_INT_ENQ_SOP_CELLHDR_BCM56440_A0fmt */ 10375 /* format ENQ_SOP_CELLHDRfmt */ 10376 /* nFields */ 2, 10377 /* *fields */ soc_ENQ_SOP_CELLHDR_BCM56624_A0fmt_fields, 10378 /* bits */ 2, 10379 /* flags */ 0, 10380 }, 10381 #endif /* chips */ 10382 10383 #if defined(BCM_56440_B0) 10384 { /* SOC_FORMAT_INT_ENQ_SOP_CELLHDR_BCM56440_B0fmt */ 10385 /* format ENQ_SOP_CELLHDRfmt */ 10386 /* nFields */ 2, 10387 /* *fields */ soc_ENQ_SOP_CELLHDR_BCM56624_A0fmt_fields, 10388 /* bits */ 2, 10389 /* flags */ 0, 10390 }, 10391 #endif /* chips */ 10392 10393 #if defined(BCM_56450_A0) 10394 { /* SOC_FORMAT_INT_ENQ_SOP_CELLHDR_BCM56450_A0fmt */ 10395 /* format ENQ_SOP_CELLHDRfmt */ 10396 /* nFields */ 2, 10397 /* *fields */ soc_ENQ_SOP_CELLHDR_BCM56450_A0fmt_fields, 10398 /* bits */ 2, 10399 /* flags */ 0, 10400 }, 10401 #endif /* chips */ 10402 10403 #if defined(BCM_56450_B0) 10404 { /* SOC_FORMAT_INT_ENQ_SOP_CELLHDR_BCM56450_B0fmt */ 10405 /* format ENQ_SOP_CELLHDRfmt */ 10406 /* nFields */ 2, 10407 /* *fields */ soc_ENQ_SOP_CELLHDR_BCM56450_A0fmt_fields, 10408 /* bits */ 2, 10409 /* flags */ 0, 10410 }, 10411 #endif /* chips */ 10412 10413 #if defined(BCM_56450_B1) 10414 { /* SOC_FORMAT_INT_ENQ_SOP_CELLHDR_BCM56450_B1fmt */ 10415 /* format ENQ_SOP_CELLHDRfmt */ 10416 /* nFields */ 2, 10417 /* *fields */ soc_ENQ_SOP_CELLHDR_BCM56450_A0fmt_fields, 10418 /* bits */ 2, 10419 /* flags */ 0, 10420 }, 10421 #endif /* chips */ 10422 10423 #if defined(BCM_56524_A0) 10424 { /* SOC_FORMAT_INT_ENQ_SOP_CELLHDR_BCM56524_A0fmt */ 10425 /* format ENQ_SOP_CELLHDRfmt */ 10426 /* nFields */ 2, 10427 /* *fields */ soc_ENQ_SOP_CELLHDR_BCM56624_A0fmt_fields, 10428 /* bits */ 2, 10429 /* flags */ 0, 10430 }, 10431 #endif /* chips */ 10432 10433 #if defined(BCM_56524_B0) 10434 { /* SOC_FORMAT_INT_ENQ_SOP_CELLHDR_BCM56524_B0fmt */ 10435 /* format ENQ_SOP_CELLHDRfmt */ 10436 /* nFields */ 2, 10437 /* *fields */ soc_ENQ_SOP_CELLHDR_BCM56624_A0fmt_fields, 10438 /* bits */ 2, 10439 /* flags */ 0, 10440 }, 10441 #endif /* chips */ 10442 10443 #if defined(BCM_56624_A0) 10444 { /* SOC_FORMAT_INT_ENQ_SOP_CELLHDR_BCM56624_A0fmt */ 10445 /* format ENQ_SOP_CELLHDRfmt */ 10446 /* nFields */ 2, 10447 /* *fields */ soc_ENQ_SOP_CELLHDR_BCM56624_A0fmt_fields, 10448 /* bits */ 2, 10449 /* flags */ 0, 10450 }, 10451 #endif /* chips */ 10452 10453 #if defined(BCM_56624_B0) 10454 { /* SOC_FORMAT_INT_ENQ_SOP_CELLHDR_BCM56624_B0fmt */ 10455 /* format ENQ_SOP_CELLHDRfmt */ 10456 /* nFields */ 2, 10457 /* *fields */ soc_ENQ_SOP_CELLHDR_BCM56624_A0fmt_fields, 10458 /* bits */ 2, 10459 /* flags */ 0, 10460 }, 10461 #endif /* chips */ 10462 10463 #if defined(BCM_56634_A0) 10464 { /* SOC_FORMAT_INT_ENQ_SOP_CELLHDR_BCM56634_A0fmt */ 10465 /* format ENQ_SOP_CELLHDRfmt */ 10466 /* nFields */ 2, 10467 /* *fields */ soc_ENQ_SOP_CELLHDR_BCM56624_A0fmt_fields, 10468 /* bits */ 2, 10469 /* flags */ 0, 10470 }, 10471 #endif /* chips */ 10472 10473 #if defined(BCM_56634_B0) 10474 { /* SOC_FORMAT_INT_ENQ_SOP_CELLHDR_BCM56634_B0fmt */ 10475 /* format ENQ_SOP_CELLHDRfmt */ 10476 /* nFields */ 2, 10477 /* *fields */ soc_ENQ_SOP_CELLHDR_BCM56624_A0fmt_fields, 10478 /* bits */ 2, 10479 /* flags */ 0, 10480 }, 10481 #endif /* chips */ 10482 10483 #if defined(BCM_56680_A0) 10484 { /* SOC_FORMAT_INT_ENQ_SOP_CELLHDR_BCM56680_A0fmt */ 10485 /* format ENQ_SOP_CELLHDRfmt */ 10486 /* nFields */ 2, 10487 /* *fields */ soc_ENQ_SOP_CELLHDR_BCM56624_A0fmt_fields, 10488 /* bits */ 2, 10489 /* flags */ 0, 10490 }, 10491 #endif /* chips */ 10492 10493 #if defined(BCM_56680_B0) 10494 { /* SOC_FORMAT_INT_ENQ_SOP_CELLHDR_BCM56680_B0fmt */ 10495 /* format ENQ_SOP_CELLHDRfmt */ 10496 /* nFields */ 2, 10497 /* *fields */ soc_ENQ_SOP_CELLHDR_BCM56624_A0fmt_fields, 10498 /* bits */ 2, 10499 /* flags */ 0, 10500 }, 10501 #endif /* chips */ 10502 10503 #if defined(BCM_56685_A0) 10504 { /* SOC_FORMAT_INT_ENQ_SOP_CELLHDR_BCM56685_A0fmt */ 10505 /* format ENQ_SOP_CELLHDRfmt */ 10506 /* nFields */ 2, 10507 /* *fields */ soc_ENQ_SOP_CELLHDR_BCM56624_A0fmt_fields, 10508 /* bits */ 2, 10509 /* flags */ 0, 10510 }, 10511 #endif /* chips */ 10512 10513 #if defined(BCM_56685_B0) 10514 { /* SOC_FORMAT_INT_ENQ_SOP_CELLHDR_BCM56685_B0fmt */ 10515 /* format ENQ_SOP_CELLHDRfmt */ 10516 /* nFields */ 2, 10517 /* *fields */ soc_ENQ_SOP_CELLHDR_BCM56624_A0fmt_fields, 10518 /* bits */ 2, 10519 /* flags */ 0, 10520 }, 10521 #endif /* chips */ 10522 10523 #if defined(BCM_56725_A0) 10524 { /* SOC_FORMAT_INT_ENQ_SOP_CELLHDR_BCM56725_A0fmt */ 10525 /* format ENQ_SOP_CELLHDRfmt */ 10526 /* nFields */ 3, 10527 /* *fields */ soc_ENQ_SOP_CELLHDR_BCM56820_A0fmt_fields, 10528 /* bits */ 3, 10529 /* flags */ 0, 10530 }, 10531 #endif /* chips */ 10532 10533 #if defined(BCM_56820_A0) 10534 { /* SOC_FORMAT_INT_ENQ_SOP_CELLHDR_BCM56820_A0fmt */ 10535 /* format ENQ_SOP_CELLHDRfmt */ 10536 /* nFields */ 3, 10537 /* *fields */ soc_ENQ_SOP_CELLHDR_BCM56820_A0fmt_fields, 10538 /* bits */ 3, 10539 /* flags */ 0, 10540 }, 10541 #endif /* chips */ 10542 10543 #if defined(BCM_56840_A0) 10544 { /* SOC_FORMAT_INT_ENQ_SOP_CELLHDR_BCM56840_A0fmt */ 10545 /* format ENQ_SOP_CELLHDRfmt */ 10546 /* nFields */ 2, 10547 /* *fields */ soc_ENQ_SOP_CELLHDR_BCM56624_A0fmt_fields, 10548 /* bits */ 2, 10549 /* flags */ 0, 10550 }, 10551 #endif /* chips */ 10552 10553 #if defined(BCM_56840_B0) 10554 { /* SOC_FORMAT_INT_ENQ_SOP_CELLHDR_BCM56840_B0fmt */ 10555 /* format ENQ_SOP_CELLHDRfmt */ 10556 /* nFields */ 2, 10557 /* *fields */ soc_ENQ_SOP_CELLHDR_BCM56624_A0fmt_fields, 10558 /* bits */ 2, 10559 /* flags */ 0, 10560 }, 10561 #endif /* chips */ 10562 10563 #if defined(BCM_56800_A0) 10564 { /* SOC_FORMAT_INT_ENQ_SOP_INFOfmt */ 10565 /* format ENQ_SOP_INFOfmt */ 10566 /* nFields */ 9, 10567 /* *fields */ soc_ENQ_SOP_INFOfmt_fields, 10568 /* bits */ 341, 10569 /* flags */ 0, 10570 }, 10571 #endif /* chips */ 10572 10573 #if defined(BCM_56334_A0) 10574 { /* SOC_FORMAT_INT_ENQ_SOP_INFO_BCM56334_A0fmt */ 10575 /* format ENQ_SOP_INFOfmt */ 10576 /* nFields */ 7, 10577 /* *fields */ soc_ENQ_SOP_INFO_BCM56334_A0fmt_fields, 10578 /* bits */ 148, 10579 /* flags */ 0, 10580 }, 10581 #endif /* chips */ 10582 10583 #if defined(BCM_56334_B0) 10584 { /* SOC_FORMAT_INT_ENQ_SOP_INFO_BCM56334_B0fmt */ 10585 /* format ENQ_SOP_INFOfmt */ 10586 /* nFields */ 7, 10587 /* *fields */ soc_ENQ_SOP_INFO_BCM56334_A0fmt_fields, 10588 /* bits */ 148, 10589 /* flags */ 0, 10590 }, 10591 #endif /* chips */ 10592 10593 #if defined(BCM_56340_A0) 10594 { /* SOC_FORMAT_INT_ENQ_SOP_INFO_BCM56340_A0fmt */ 10595 /* format ENQ_SOP_INFOfmt */ 10596 /* nFields */ 21, 10597 /* *fields */ soc_ENQ_SOP_INFO_BCM56640_A0fmt_fields, 10598 /* bits */ 228, 10599 /* flags */ 0, 10600 }, 10601 #endif /* chips */ 10602 10603 #if defined(BCM_56440_A0) 10604 { /* SOC_FORMAT_INT_ENQ_SOP_INFO_BCM56440_A0fmt */ 10605 /* format ENQ_SOP_INFOfmt */ 10606 /* nFields */ 23, 10607 /* *fields */ soc_ENQ_SOP_INFO_BCM56840_A0fmt_fields, 10608 /* bits */ 237, 10609 /* flags */ 0, 10610 }, 10611 #endif /* chips */ 10612 10613 #if defined(BCM_56440_B0) 10614 { /* SOC_FORMAT_INT_ENQ_SOP_INFO_BCM56440_B0fmt */ 10615 /* format ENQ_SOP_INFOfmt */ 10616 /* nFields */ 23, 10617 /* *fields */ soc_ENQ_SOP_INFO_BCM56840_A0fmt_fields, 10618 /* bits */ 237, 10619 /* flags */ 0, 10620 }, 10621 #endif /* chips */ 10622 10623 #if defined(BCM_56450_A0) 10624 { /* SOC_FORMAT_INT_ENQ_SOP_INFO_BCM56450_A0fmt */ 10625 /* format ENQ_SOP_INFOfmt */ 10626 /* nFields */ 23, 10627 /* *fields */ soc_ENQ_SOP_INFO_BCM56450_A0fmt_fields, 10628 /* bits */ 237, 10629 /* flags */ 0, 10630 }, 10631 #endif /* chips */ 10632 10633 #if defined(BCM_56450_B0) 10634 { /* SOC_FORMAT_INT_ENQ_SOP_INFO_BCM56450_B0fmt */ 10635 /* format ENQ_SOP_INFOfmt */ 10636 /* nFields */ 23, 10637 /* *fields */ soc_ENQ_SOP_INFO_BCM56450_A0fmt_fields, 10638 /* bits */ 237, 10639 /* flags */ 0, 10640 }, 10641 #endif /* chips */ 10642 10643 #if defined(BCM_56450_B1) 10644 { /* SOC_FORMAT_INT_ENQ_SOP_INFO_BCM56450_B1fmt */ 10645 /* format ENQ_SOP_INFOfmt */ 10646 /* nFields */ 23, 10647 /* *fields */ soc_ENQ_SOP_INFO_BCM56450_A0fmt_fields, 10648 /* bits */ 237, 10649 /* flags */ 0, 10650 }, 10651 #endif /* chips */ 10652 10653 #if defined(BCM_56524_A0) 10654 { /* SOC_FORMAT_INT_ENQ_SOP_INFO_BCM56524_A0fmt */ 10655 /* format ENQ_SOP_INFOfmt */ 10656 /* nFields */ 15, 10657 /* *fields */ soc_ENQ_SOP_INFO_BCM56634_A0fmt_fields, 10658 /* bits */ 243, 10659 /* flags */ 0, 10660 }, 10661 #endif /* chips */ 10662 10663 #if defined(BCM_56524_B0) 10664 { /* SOC_FORMAT_INT_ENQ_SOP_INFO_BCM56524_B0fmt */ 10665 /* format ENQ_SOP_INFOfmt */ 10666 /* nFields */ 15, 10667 /* *fields */ soc_ENQ_SOP_INFO_BCM56634_A0fmt_fields, 10668 /* bits */ 243, 10669 /* flags */ 0, 10670 }, 10671 #endif /* chips */ 10672 10673 #if defined(BCM_56624_A0) 10674 { /* SOC_FORMAT_INT_ENQ_SOP_INFO_BCM56624_A0fmt */ 10675 /* format ENQ_SOP_INFOfmt */ 10676 /* nFields */ 7, 10677 /* *fields */ soc_ENQ_SOP_INFO_BCM56624_A0fmt_fields, 10678 /* bits */ 196, 10679 /* flags */ 0, 10680 }, 10681 #endif /* chips */ 10682 10683 #if defined(BCM_56624_B0) 10684 { /* SOC_FORMAT_INT_ENQ_SOP_INFO_BCM56624_B0fmt */ 10685 /* format ENQ_SOP_INFOfmt */ 10686 /* nFields */ 7, 10687 /* *fields */ soc_ENQ_SOP_INFO_BCM56624_A0fmt_fields, 10688 /* bits */ 196, 10689 /* flags */ 0, 10690 }, 10691 #endif /* chips */ 10692 10693 #if defined(BCM_56634_A0) 10694 { /* SOC_FORMAT_INT_ENQ_SOP_INFO_BCM56634_A0fmt */ 10695 /* format ENQ_SOP_INFOfmt */ 10696 /* nFields */ 15, 10697 /* *fields */ soc_ENQ_SOP_INFO_BCM56634_A0fmt_fields, 10698 /* bits */ 243, 10699 /* flags */ 0, 10700 }, 10701 #endif /* chips */ 10702 10703 #if defined(BCM_56634_B0) 10704 { /* SOC_FORMAT_INT_ENQ_SOP_INFO_BCM56634_B0fmt */ 10705 /* format ENQ_SOP_INFOfmt */ 10706 /* nFields */ 15, 10707 /* *fields */ soc_ENQ_SOP_INFO_BCM56634_A0fmt_fields, 10708 /* bits */ 243, 10709 /* flags */ 0, 10710 }, 10711 #endif /* chips */ 10712 10713 #if defined(BCM_56640_A0) 10714 { /* SOC_FORMAT_INT_ENQ_SOP_INFO_BCM56640_A0fmt */ 10715 /* format ENQ_SOP_INFOfmt */ 10716 /* nFields */ 21, 10717 /* *fields */ soc_ENQ_SOP_INFO_BCM56640_A0fmt_fields, 10718 /* bits */ 228, 10719 /* flags */ 0, 10720 }, 10721 #endif /* chips */ 10722 10723 #if defined(BCM_56680_A0) 10724 { /* SOC_FORMAT_INT_ENQ_SOP_INFO_BCM56680_A0fmt */ 10725 /* format ENQ_SOP_INFOfmt */ 10726 /* nFields */ 7, 10727 /* *fields */ soc_ENQ_SOP_INFO_BCM56624_A0fmt_fields, 10728 /* bits */ 196, 10729 /* flags */ 0, 10730 }, 10731 #endif /* chips */ 10732 10733 #if defined(BCM_56680_B0) 10734 { /* SOC_FORMAT_INT_ENQ_SOP_INFO_BCM56680_B0fmt */ 10735 /* format ENQ_SOP_INFOfmt */ 10736 /* nFields */ 7, 10737 /* *fields */ soc_ENQ_SOP_INFO_BCM56624_A0fmt_fields, 10738 /* bits */ 196, 10739 /* flags */ 0, 10740 }, 10741 #endif /* chips */ 10742 10743 #if defined(BCM_56685_A0) 10744 { /* SOC_FORMAT_INT_ENQ_SOP_INFO_BCM56685_A0fmt */ 10745 /* format ENQ_SOP_INFOfmt */ 10746 /* nFields */ 15, 10747 /* *fields */ soc_ENQ_SOP_INFO_BCM56634_A0fmt_fields, 10748 /* bits */ 243, 10749 /* flags */ 0, 10750 }, 10751 #endif /* chips */ 10752 10753 #if defined(BCM_56685_B0) 10754 { /* SOC_FORMAT_INT_ENQ_SOP_INFO_BCM56685_B0fmt */ 10755 /* format ENQ_SOP_INFOfmt */ 10756 /* nFields */ 15, 10757 /* *fields */ soc_ENQ_SOP_INFO_BCM56634_A0fmt_fields, 10758 /* bits */ 243, 10759 /* flags */ 0, 10760 }, 10761 #endif /* chips */ 10762 10763 #if defined(BCM_56725_A0) 10764 { /* SOC_FORMAT_INT_ENQ_SOP_INFO_BCM56725_A0fmt */ 10765 /* format ENQ_SOP_INFOfmt */ 10766 /* nFields */ 5, 10767 /* *fields */ soc_ENQ_SOP_INFO_BCM56820_A0fmt_fields, 10768 /* bits */ 121, 10769 /* flags */ 0, 10770 }, 10771 #endif /* chips */ 10772 10773 #if defined(BCM_56820_A0) 10774 { /* SOC_FORMAT_INT_ENQ_SOP_INFO_BCM56820_A0fmt */ 10775 /* format ENQ_SOP_INFOfmt */ 10776 /* nFields */ 5, 10777 /* *fields */ soc_ENQ_SOP_INFO_BCM56820_A0fmt_fields, 10778 /* bits */ 121, 10779 /* flags */ 0, 10780 }, 10781 #endif /* chips */ 10782 10783 #if defined(BCM_56840_A0) 10784 { /* SOC_FORMAT_INT_ENQ_SOP_INFO_BCM56840_A0fmt */ 10785 /* format ENQ_SOP_INFOfmt */ 10786 /* nFields */ 23, 10787 /* *fields */ soc_ENQ_SOP_INFO_BCM56840_A0fmt_fields, 10788 /* bits */ 237, 10789 /* flags */ 0, 10790 }, 10791 #endif /* chips */ 10792 10793 #if defined(BCM_56840_B0) 10794 { /* SOC_FORMAT_INT_ENQ_SOP_INFO_BCM56840_B0fmt */ 10795 /* format ENQ_SOP_INFOfmt */ 10796 /* nFields */ 23, 10797 /* *fields */ soc_ENQ_SOP_INFO_BCM56840_A0fmt_fields, 10798 /* bits */ 237, 10799 /* flags */ 0, 10800 }, 10801 #endif /* chips */ 10802 10803 #if defined(BCM_88732_A0) 10804 { /* SOC_FORMAT_INT_ENQ_SOP_INFO_BCM88732_A0fmt */ 10805 /* format ENQ_SOP_INFOfmt */ 10806 /* nFields */ 8, 10807 /* *fields */ soc_ENQ_SOP_INFO_BCM88732_A0fmt_fields, 10808 /* bits */ 38, 10809 /* flags */ 0, 10810 }, 10811 #endif /* chips */ 10812 10813 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \ 10814 defined(BCM_56450_B1) 10815 { /* SOC_FORMAT_INT_ENQ_SRC_CTXT_FIFOfmt */ 10816 /* format ENQ_SRC_CTXT_FIFOfmt */ 10817 /* nFields */ 40, 10818 /* *fields */ soc_ENQ_SRC_CTXT_FIFOfmt_fields, 10819 /* bits */ 529, 10820 /* flags */ 0, 10821 }, 10822 #endif /* chips */ 10823 10824 #if defined(BCM_56260_A0) 10825 { /* SOC_FORMAT_INT_ENQ_SRC_CTXT_FIFO_BCM56260_A0fmt */ 10826 /* format ENQ_SRC_CTXT_FIFOfmt */ 10827 /* nFields */ 40, 10828 /* *fields */ soc_ENQ_SRC_CTXT_FIFO_BCM56260_A0fmt_fields, 10829 /* bits */ 368, 10830 /* flags */ 0, 10831 }, 10832 #endif /* chips */ 10833 10834 #if defined(BCM_56260_B0) 10835 { /* SOC_FORMAT_INT_ENQ_SRC_CTXT_FIFO_BCM56260_B0fmt */ 10836 /* format ENQ_SRC_CTXT_FIFOfmt */ 10837 /* nFields */ 40, 10838 /* *fields */ soc_ENQ_SRC_CTXT_FIFO_BCM56260_A0fmt_fields, 10839 /* bits */ 368, 10840 /* flags */ 0, 10841 }, 10842 #endif /* chips */ 10843 10844 #if defined(BCM_56270_A0) 10845 { /* SOC_FORMAT_INT_ENQ_SRC_CTXT_FIFO_BCM56270_A0fmt */ 10846 /* format ENQ_SRC_CTXT_FIFOfmt */ 10847 /* nFields */ 35, 10848 /* *fields */ soc_ENQ_SRC_CTXT_FIFO_BCM56270_A0fmt_fields, 10849 /* bits */ 225, 10850 /* flags */ 0, 10851 }, 10852 #endif /* chips */ 10853 10854 #if defined(BCM_56634_A0) || defined(BCM_56634_B0) 10855 { /* SOC_FORMAT_INT_ENQ_ST7_TO_ENQOUTfmt */ 10856 /* format ENQ_ST7_TO_ENQOUTfmt */ 10857 /* nFields */ 11, 10858 /* *fields */ soc_ENQ_ST7_TO_ENQOUTfmt_fields, 10859 /* bits */ 54, 10860 /* flags */ 0, 10861 }, 10862 #endif /* chips */ 10863 10864 #if defined(BCM_56340_A0) 10865 { /* SOC_FORMAT_INT_ENQ_ST7_TO_ENQOUT_BCM56340_A0fmt */ 10866 /* format ENQ_ST7_TO_ENQOUTfmt */ 10867 /* nFields */ 7, 10868 /* *fields */ soc_ENQ_ST7_TO_ENQOUT_BCM56640_A0fmt_fields, 10869 /* bits */ 24, 10870 /* flags */ 0, 10871 }, 10872 #endif /* chips */ 10873 10874 #if defined(BCM_56440_A0) 10875 { /* SOC_FORMAT_INT_ENQ_ST7_TO_ENQOUT_BCM56440_A0fmt */ 10876 /* format ENQ_ST7_TO_ENQOUTfmt */ 10877 /* nFields */ 3, 10878 /* *fields */ soc_ENQ_ST7_TO_ENQOUT_BCM56840_A0fmt_fields, 10879 /* bits */ 18, 10880 /* flags */ 0, 10881 }, 10882 #endif /* chips */ 10883 10884 #if defined(BCM_56440_B0) 10885 { /* SOC_FORMAT_INT_ENQ_ST7_TO_ENQOUT_BCM56440_B0fmt */ 10886 /* format ENQ_ST7_TO_ENQOUTfmt */ 10887 /* nFields */ 3, 10888 /* *fields */ soc_ENQ_ST7_TO_ENQOUT_BCM56840_A0fmt_fields, 10889 /* bits */ 18, 10890 /* flags */ 0, 10891 }, 10892 #endif /* chips */ 10893 10894 #if defined(BCM_56450_A0) 10895 { /* SOC_FORMAT_INT_ENQ_ST7_TO_ENQOUT_BCM56450_A0fmt */ 10896 /* format ENQ_ST7_TO_ENQOUTfmt */ 10897 /* nFields */ 3, 10898 /* *fields */ soc_ENQ_ST7_TO_ENQOUT_BCM56450_A0fmt_fields, 10899 /* bits */ 18, 10900 /* flags */ 0, 10901 }, 10902 #endif /* chips */ 10903 10904 #if defined(BCM_56450_B0) 10905 { /* SOC_FORMAT_INT_ENQ_ST7_TO_ENQOUT_BCM56450_B0fmt */ 10906 /* format ENQ_ST7_TO_ENQOUTfmt */ 10907 /* nFields */ 3, 10908 /* *fields */ soc_ENQ_ST7_TO_ENQOUT_BCM56450_A0fmt_fields, 10909 /* bits */ 18, 10910 /* flags */ 0, 10911 }, 10912 #endif /* chips */ 10913 10914 #if defined(BCM_56450_B1) 10915 { /* SOC_FORMAT_INT_ENQ_ST7_TO_ENQOUT_BCM56450_B1fmt */ 10916 /* format ENQ_ST7_TO_ENQOUTfmt */ 10917 /* nFields */ 3, 10918 /* *fields */ soc_ENQ_ST7_TO_ENQOUT_BCM56450_A0fmt_fields, 10919 /* bits */ 18, 10920 /* flags */ 0, 10921 }, 10922 #endif /* chips */ 10923 10924 #if defined(BCM_56524_A0) 10925 { /* SOC_FORMAT_INT_ENQ_ST7_TO_ENQOUT_BCM56524_A0fmt */ 10926 /* format ENQ_ST7_TO_ENQOUTfmt */ 10927 /* nFields */ 11, 10928 /* *fields */ soc_ENQ_ST7_TO_ENQOUTfmt_fields, 10929 /* bits */ 54, 10930 /* flags */ 0, 10931 }, 10932 #endif /* chips */ 10933 10934 #if defined(BCM_56524_B0) 10935 { /* SOC_FORMAT_INT_ENQ_ST7_TO_ENQOUT_BCM56524_B0fmt */ 10936 /* format ENQ_ST7_TO_ENQOUTfmt */ 10937 /* nFields */ 11, 10938 /* *fields */ soc_ENQ_ST7_TO_ENQOUTfmt_fields, 10939 /* bits */ 54, 10940 /* flags */ 0, 10941 }, 10942 #endif /* chips */ 10943 10944 #if defined(BCM_56560_A0) 10945 { /* SOC_FORMAT_INT_ENQ_ST7_TO_ENQOUT_BCM56560_A0fmt */ 10946 /* format ENQ_ST7_TO_ENQOUTfmt */ 10947 /* nFields */ 22, 10948 /* *fields */ soc_ENQ_ST7_TO_ENQOUT_BCM56560_A0fmt_fields, 10949 /* bits */ 279, 10950 /* flags */ 0, 10951 }, 10952 #endif /* chips */ 10953 10954 #if defined(BCM_56560_B0) 10955 { /* SOC_FORMAT_INT_ENQ_ST7_TO_ENQOUT_BCM56560_B0fmt */ 10956 /* format ENQ_ST7_TO_ENQOUTfmt */ 10957 /* nFields */ 22, 10958 /* *fields */ soc_ENQ_ST7_TO_ENQOUT_BCM56560_A0fmt_fields, 10959 /* bits */ 279, 10960 /* flags */ 0, 10961 }, 10962 #endif /* chips */ 10963 10964 #if defined(BCM_56640_A0) 10965 { /* SOC_FORMAT_INT_ENQ_ST7_TO_ENQOUT_BCM56640_A0fmt */ 10966 /* format ENQ_ST7_TO_ENQOUTfmt */ 10967 /* nFields */ 7, 10968 /* *fields */ soc_ENQ_ST7_TO_ENQOUT_BCM56640_A0fmt_fields, 10969 /* bits */ 24, 10970 /* flags */ 0, 10971 }, 10972 #endif /* chips */ 10973 10974 #if defined(BCM_56670_A0) 10975 { /* SOC_FORMAT_INT_ENQ_ST7_TO_ENQOUT_BCM56670_A0fmt */ 10976 /* format ENQ_ST7_TO_ENQOUTfmt */ 10977 /* nFields */ 23, 10978 /* *fields */ soc_ENQ_ST7_TO_ENQOUT_BCM56670_A0fmt_fields, 10979 /* bits */ 266, 10980 /* flags */ 0, 10981 }, 10982 #endif /* chips */ 10983 10984 #if defined(BCM_56670_B0) 10985 { /* SOC_FORMAT_INT_ENQ_ST7_TO_ENQOUT_BCM56670_B0fmt */ 10986 /* format ENQ_ST7_TO_ENQOUTfmt */ 10987 /* nFields */ 23, 10988 /* *fields */ soc_ENQ_ST7_TO_ENQOUT_BCM56670_A0fmt_fields, 10989 /* bits */ 266, 10990 /* flags */ 0, 10991 }, 10992 #endif /* chips */ 10993 10994 #if defined(BCM_56685_A0) 10995 { /* SOC_FORMAT_INT_ENQ_ST7_TO_ENQOUT_BCM56685_A0fmt */ 10996 /* format ENQ_ST7_TO_ENQOUTfmt */ 10997 /* nFields */ 11, 10998 /* *fields */ soc_ENQ_ST7_TO_ENQOUTfmt_fields, 10999 /* bits */ 54, 11000 /* flags */ 0, 11001 }, 11002 #endif /* chips */ 11003 11004 #if defined(BCM_56685_B0) 11005 { /* SOC_FORMAT_INT_ENQ_ST7_TO_ENQOUT_BCM56685_B0fmt */ 11006 /* format ENQ_ST7_TO_ENQOUTfmt */ 11007 /* nFields */ 11, 11008 /* *fields */ soc_ENQ_ST7_TO_ENQOUTfmt_fields, 11009 /* bits */ 54, 11010 /* flags */ 0, 11011 }, 11012 #endif /* chips */ 11013 11014 #if defined(BCM_56840_A0) 11015 { /* SOC_FORMAT_INT_ENQ_ST7_TO_ENQOUT_BCM56840_A0fmt */ 11016 /* format ENQ_ST7_TO_ENQOUTfmt */ 11017 /* nFields */ 3, 11018 /* *fields */ soc_ENQ_ST7_TO_ENQOUT_BCM56840_A0fmt_fields, 11019 /* bits */ 18, 11020 /* flags */ 0, 11021 }, 11022 #endif /* chips */ 11023 11024 #if defined(BCM_56840_B0) 11025 { /* SOC_FORMAT_INT_ENQ_ST7_TO_ENQOUT_BCM56840_B0fmt */ 11026 /* format ENQ_ST7_TO_ENQOUTfmt */ 11027 /* nFields */ 3, 11028 /* *fields */ soc_ENQ_ST7_TO_ENQOUT_BCM56840_A0fmt_fields, 11029 /* bits */ 18, 11030 /* flags */ 0, 11031 }, 11032 #endif /* chips */ 11033 11034 #if defined(BCM_56850_A0) 11035 { /* SOC_FORMAT_INT_ENQ_ST7_TO_ENQOUT_BCM56850_A0fmt */ 11036 /* format ENQ_ST7_TO_ENQOUTfmt */ 11037 /* nFields */ 22, 11038 /* *fields */ soc_ENQ_ST7_TO_ENQOUT_BCM56850_A0fmt_fields, 11039 /* bits */ 344, 11040 /* flags */ 0, 11041 }, 11042 #endif /* chips */ 11043 11044 #if defined(BCM_56860_A0) 11045 { /* SOC_FORMAT_INT_ENQ_ST7_TO_ENQOUT_BCM56860_A0fmt */ 11046 /* format ENQ_ST7_TO_ENQOUTfmt */ 11047 /* nFields */ 22, 11048 /* *fields */ soc_ENQ_ST7_TO_ENQOUT_BCM56850_A0fmt_fields, 11049 /* bits */ 344, 11050 /* flags */ 0, 11051 }, 11052 #endif /* chips */ 11053 11054 #if defined(BCM_56850_A0) || defined(BCM_56860_A0) 11055 { /* SOC_FORMAT_INT_ENQ_TOP_PIPE_TO_CT_INFOfmt */ 11056 /* format ENQ_TOP_PIPE_TO_CT_INFOfmt */ 11057 /* nFields */ 31, 11058 /* *fields */ soc_ENQ_TOP_PIPE_TO_CT_INFOfmt_fields, 11059 /* bits */ 1177, 11060 /* flags */ 0, 11061 }, 11062 #endif /* chips */ 11063 11064 #if defined(BCM_56560_A0) 11065 { /* SOC_FORMAT_INT_ENQ_TOP_PIPE_TO_CT_INFO_BCM56560_A0fmt */ 11066 /* format ENQ_TOP_PIPE_TO_CT_INFOfmt */ 11067 /* nFields */ 31, 11068 /* *fields */ soc_ENQ_TOP_PIPE_TO_CT_INFO_BCM56560_A0fmt_fields, 11069 /* bits */ 869, 11070 /* flags */ 0, 11071 }, 11072 #endif /* chips */ 11073 11074 #if defined(BCM_56560_B0) 11075 { /* SOC_FORMAT_INT_ENQ_TOP_PIPE_TO_CT_INFO_BCM56560_B0fmt */ 11076 /* format ENQ_TOP_PIPE_TO_CT_INFOfmt */ 11077 /* nFields */ 31, 11078 /* *fields */ soc_ENQ_TOP_PIPE_TO_CT_INFO_BCM56560_A0fmt_fields, 11079 /* bits */ 869, 11080 /* flags */ 0, 11081 }, 11082 #endif /* chips */ 11083 11084 #if defined(BCM_56670_A0) 11085 { /* SOC_FORMAT_INT_ENQ_TOP_PIPE_TO_CT_INFO_BCM56670_A0fmt */ 11086 /* format ENQ_TOP_PIPE_TO_CT_INFOfmt */ 11087 /* nFields */ 31, 11088 /* *fields */ soc_ENQ_TOP_PIPE_TO_CT_INFO_BCM56670_A0fmt_fields, 11089 /* bits */ 789, 11090 /* flags */ 0, 11091 }, 11092 #endif /* chips */ 11093 11094 #if defined(BCM_56670_B0) 11095 { /* SOC_FORMAT_INT_ENQ_TOP_PIPE_TO_CT_INFO_BCM56670_B0fmt */ 11096 /* format ENQ_TOP_PIPE_TO_CT_INFOfmt */ 11097 /* nFields */ 31, 11098 /* *fields */ soc_ENQ_TOP_PIPE_TO_CT_INFO_BCM56670_A0fmt_fields, 11099 /* bits */ 789, 11100 /* flags */ 0, 11101 }, 11102 #endif /* chips */ 11103 11104 #if defined(BCM_56440_A0) 11105 { /* SOC_FORMAT_INT_ENQ_TO_ADM_INFOfmt */ 11106 /* format ENQ_TO_ADM_INFOfmt */ 11107 /* nFields */ 20, 11108 /* *fields */ soc_ENQ_TO_ADM_INFOfmt_fields, 11109 /* bits */ 46, 11110 /* flags */ 0, 11111 }, 11112 #endif /* chips */ 11113 11114 #if defined(BCM_56260_A0) 11115 { /* SOC_FORMAT_INT_ENQ_TO_ADM_INFO_BCM56260_A0fmt */ 11116 /* format ENQ_TO_ADM_INFOfmt */ 11117 /* nFields */ 38, 11118 /* *fields */ soc_ENQ_TO_ADM_INFO_BCM56260_A0fmt_fields, 11119 /* bits */ 134, 11120 /* flags */ 0, 11121 }, 11122 #endif /* chips */ 11123 11124 #if defined(BCM_56260_B0) 11125 { /* SOC_FORMAT_INT_ENQ_TO_ADM_INFO_BCM56260_B0fmt */ 11126 /* format ENQ_TO_ADM_INFOfmt */ 11127 /* nFields */ 38, 11128 /* *fields */ soc_ENQ_TO_ADM_INFO_BCM56260_A0fmt_fields, 11129 /* bits */ 134, 11130 /* flags */ 0, 11131 }, 11132 #endif /* chips */ 11133 11134 #if defined(BCM_56270_A0) 11135 { /* SOC_FORMAT_INT_ENQ_TO_ADM_INFO_BCM56270_A0fmt */ 11136 /* format ENQ_TO_ADM_INFOfmt */ 11137 /* nFields */ 20, 11138 /* *fields */ soc_ENQ_TO_ADM_INFO_BCM56270_A0fmt_fields, 11139 /* bits */ 71, 11140 /* flags */ 0, 11141 }, 11142 #endif /* chips */ 11143 11144 #if defined(BCM_56440_B0) 11145 { /* SOC_FORMAT_INT_ENQ_TO_ADM_INFO_BCM56440_B0fmt */ 11146 /* format ENQ_TO_ADM_INFOfmt */ 11147 /* nFields */ 20, 11148 /* *fields */ soc_ENQ_TO_ADM_INFOfmt_fields, 11149 /* bits */ 46, 11150 /* flags */ 0, 11151 }, 11152 #endif /* chips */ 11153 11154 #if defined(BCM_56450_A0) 11155 { /* SOC_FORMAT_INT_ENQ_TO_ADM_INFO_BCM56450_A0fmt */ 11156 /* format ENQ_TO_ADM_INFOfmt */ 11157 /* nFields */ 37, 11158 /* *fields */ soc_ENQ_TO_ADM_INFO_BCM56450_A0fmt_fields, 11159 /* bits */ 148, 11160 /* flags */ 0, 11161 }, 11162 #endif /* chips */ 11163 11164 #if defined(BCM_56450_B0) 11165 { /* SOC_FORMAT_INT_ENQ_TO_ADM_INFO_BCM56450_B0fmt */ 11166 /* format ENQ_TO_ADM_INFOfmt */ 11167 /* nFields */ 37, 11168 /* *fields */ soc_ENQ_TO_ADM_INFO_BCM56450_A0fmt_fields, 11169 /* bits */ 148, 11170 /* flags */ 0, 11171 }, 11172 #endif /* chips */ 11173 11174 #if defined(BCM_56450_B1) 11175 { /* SOC_FORMAT_INT_ENQ_TO_ADM_INFO_BCM56450_B1fmt */ 11176 /* format ENQ_TO_ADM_INFOfmt */ 11177 /* nFields */ 37, 11178 /* *fields */ soc_ENQ_TO_ADM_INFO_BCM56450_A0fmt_fields, 11179 /* bits */ 148, 11180 /* flags */ 0, 11181 }, 11182 #endif /* chips */ 11183 11184 #if defined(BCM_56440_A0) 11185 { /* SOC_FORMAT_INT_ENQ_TO_ADM_PIPEfmt */ 11186 /* format ENQ_TO_ADM_PIPEfmt */ 11187 /* nFields */ 16, 11188 /* *fields */ soc_ENQ_TO_ADM_PIPEfmt_fields, 11189 /* bits */ 25, 11190 /* flags */ 0, 11191 }, 11192 #endif /* chips */ 11193 11194 #if defined(BCM_56260_A0) 11195 { /* SOC_FORMAT_INT_ENQ_TO_ADM_PIPE_BCM56260_A0fmt */ 11196 /* format ENQ_TO_ADM_PIPEfmt */ 11197 /* nFields */ 15, 11198 /* *fields */ soc_ENQ_TO_ADM_PIPE_BCM56260_A0fmt_fields, 11199 /* bits */ 24, 11200 /* flags */ 0, 11201 }, 11202 #endif /* chips */ 11203 11204 #if defined(BCM_56260_B0) 11205 { /* SOC_FORMAT_INT_ENQ_TO_ADM_PIPE_BCM56260_B0fmt */ 11206 /* format ENQ_TO_ADM_PIPEfmt */ 11207 /* nFields */ 15, 11208 /* *fields */ soc_ENQ_TO_ADM_PIPE_BCM56260_A0fmt_fields, 11209 /* bits */ 24, 11210 /* flags */ 0, 11211 }, 11212 #endif /* chips */ 11213 11214 #if defined(BCM_56270_A0) 11215 { /* SOC_FORMAT_INT_ENQ_TO_ADM_PIPE_BCM56270_A0fmt */ 11216 /* format ENQ_TO_ADM_PIPEfmt */ 11217 /* nFields */ 9, 11218 /* *fields */ soc_ENQ_TO_ADM_PIPE_BCM56270_A0fmt_fields, 11219 /* bits */ 16, 11220 /* flags */ 0, 11221 }, 11222 #endif /* chips */ 11223 11224 #if defined(BCM_56440_B0) 11225 { /* SOC_FORMAT_INT_ENQ_TO_ADM_PIPE_BCM56440_B0fmt */ 11226 /* format ENQ_TO_ADM_PIPEfmt */ 11227 /* nFields */ 16, 11228 /* *fields */ soc_ENQ_TO_ADM_PIPEfmt_fields, 11229 /* bits */ 25, 11230 /* flags */ 0, 11231 }, 11232 #endif /* chips */ 11233 11234 #if defined(BCM_56450_A0) 11235 { /* SOC_FORMAT_INT_ENQ_TO_ADM_PIPE_BCM56450_A0fmt */ 11236 /* format ENQ_TO_ADM_PIPEfmt */ 11237 /* nFields */ 15, 11238 /* *fields */ soc_ENQ_TO_ADM_PIPE_BCM56450_A0fmt_fields, 11239 /* bits */ 24, 11240 /* flags */ 0, 11241 }, 11242 #endif /* chips */ 11243 11244 #if defined(BCM_56450_B0) 11245 { /* SOC_FORMAT_INT_ENQ_TO_ADM_PIPE_BCM56450_B0fmt */ 11246 /* format ENQ_TO_ADM_PIPEfmt */ 11247 /* nFields */ 15, 11248 /* *fields */ soc_ENQ_TO_ADM_PIPE_BCM56450_A0fmt_fields, 11249 /* bits */ 24, 11250 /* flags */ 0, 11251 }, 11252 #endif /* chips */ 11253 11254 #if defined(BCM_56450_B1) 11255 { /* SOC_FORMAT_INT_ENQ_TO_ADM_PIPE_BCM56450_B1fmt */ 11256 /* format ENQ_TO_ADM_PIPEfmt */ 11257 /* nFields */ 15, 11258 /* *fields */ soc_ENQ_TO_ADM_PIPE_BCM56450_A0fmt_fields, 11259 /* bits */ 24, 11260 /* flags */ 0, 11261 }, 11262 #endif /* chips */ 11263 11264 #if defined(BCM_56800_A0) 11265 { /* SOC_FORMAT_INT_ENQ_TO_AGING_PKT_PTRfmt */ 11266 /* format ENQ_TO_AGING_PKT_PTRfmt */ 11267 /* nFields */ 2, 11268 /* *fields */ soc_ENQ_TO_AGING_PKT_PTRfmt_fields, 11269 /* bits */ 18, 11270 /* flags */ 0, 11271 }, 11272 #endif /* chips */ 11273 11274 #if defined(BCM_56334_A0) 11275 { /* SOC_FORMAT_INT_ENQ_TO_AGING_PKT_PTR_BCM56334_A0fmt */ 11276 /* format ENQ_TO_AGING_PKT_PTRfmt */ 11277 /* nFields */ 2, 11278 /* *fields */ soc_ENQ_TO_AGING_PKT_PTR_BCM56334_A0fmt_fields, 11279 /* bits */ 17, 11280 /* flags */ 0, 11281 }, 11282 #endif /* chips */ 11283 11284 #if defined(BCM_56334_B0) 11285 { /* SOC_FORMAT_INT_ENQ_TO_AGING_PKT_PTR_BCM56334_B0fmt */ 11286 /* format ENQ_TO_AGING_PKT_PTRfmt */ 11287 /* nFields */ 2, 11288 /* *fields */ soc_ENQ_TO_AGING_PKT_PTR_BCM56334_A0fmt_fields, 11289 /* bits */ 17, 11290 /* flags */ 0, 11291 }, 11292 #endif /* chips */ 11293 11294 #if defined(BCM_56340_A0) 11295 { /* SOC_FORMAT_INT_ENQ_TO_AGING_PKT_PTR_BCM56340_A0fmt */ 11296 /* format ENQ_TO_AGING_PKT_PTRfmt */ 11297 /* nFields */ 2, 11298 /* *fields */ soc_ENQ_TO_AGING_PKT_PTR_BCM56640_A0fmt_fields, 11299 /* bits */ 19, 11300 /* flags */ 0, 11301 }, 11302 #endif /* chips */ 11303 11304 #if defined(BCM_56440_A0) 11305 { /* SOC_FORMAT_INT_ENQ_TO_AGING_PKT_PTR_BCM56440_A0fmt */ 11306 /* format ENQ_TO_AGING_PKT_PTRfmt */ 11307 /* nFields */ 2, 11308 /* *fields */ soc_ENQ_TO_AGING_PKT_PTR_BCM56840_A0fmt_fields, 11309 /* bits */ 20, 11310 /* flags */ 0, 11311 }, 11312 #endif /* chips */ 11313 11314 #if defined(BCM_56440_B0) 11315 { /* SOC_FORMAT_INT_ENQ_TO_AGING_PKT_PTR_BCM56440_B0fmt */ 11316 /* format ENQ_TO_AGING_PKT_PTRfmt */ 11317 /* nFields */ 2, 11318 /* *fields */ soc_ENQ_TO_AGING_PKT_PTR_BCM56840_A0fmt_fields, 11319 /* bits */ 20, 11320 /* flags */ 0, 11321 }, 11322 #endif /* chips */ 11323 11324 #if defined(BCM_56450_A0) 11325 { /* SOC_FORMAT_INT_ENQ_TO_AGING_PKT_PTR_BCM56450_A0fmt */ 11326 /* format ENQ_TO_AGING_PKT_PTRfmt */ 11327 /* nFields */ 2, 11328 /* *fields */ soc_ENQ_TO_AGING_PKT_PTR_BCM56450_A0fmt_fields, 11329 /* bits */ 20, 11330 /* flags */ 0, 11331 }, 11332 #endif /* chips */ 11333 11334 #if defined(BCM_56450_B0) 11335 { /* SOC_FORMAT_INT_ENQ_TO_AGING_PKT_PTR_BCM56450_B0fmt */ 11336 /* format ENQ_TO_AGING_PKT_PTRfmt */ 11337 /* nFields */ 2, 11338 /* *fields */ soc_ENQ_TO_AGING_PKT_PTR_BCM56450_A0fmt_fields, 11339 /* bits */ 20, 11340 /* flags */ 0, 11341 }, 11342 #endif /* chips */ 11343 11344 #if defined(BCM_56450_B1) 11345 { /* SOC_FORMAT_INT_ENQ_TO_AGING_PKT_PTR_BCM56450_B1fmt */ 11346 /* format ENQ_TO_AGING_PKT_PTRfmt */ 11347 /* nFields */ 2, 11348 /* *fields */ soc_ENQ_TO_AGING_PKT_PTR_BCM56450_A0fmt_fields, 11349 /* bits */ 20, 11350 /* flags */ 0, 11351 }, 11352 #endif /* chips */ 11353 11354 #if defined(BCM_56524_A0) 11355 { /* SOC_FORMAT_INT_ENQ_TO_AGING_PKT_PTR_BCM56524_A0fmt */ 11356 /* format ENQ_TO_AGING_PKT_PTRfmt */ 11357 /* nFields */ 2, 11358 /* *fields */ soc_ENQ_TO_AGING_PKT_PTR_BCM56624_A0fmt_fields, 11359 /* bits */ 18, 11360 /* flags */ 0, 11361 }, 11362 #endif /* chips */ 11363 11364 #if defined(BCM_56524_B0) 11365 { /* SOC_FORMAT_INT_ENQ_TO_AGING_PKT_PTR_BCM56524_B0fmt */ 11366 /* format ENQ_TO_AGING_PKT_PTRfmt */ 11367 /* nFields */ 2, 11368 /* *fields */ soc_ENQ_TO_AGING_PKT_PTR_BCM56624_A0fmt_fields, 11369 /* bits */ 18, 11370 /* flags */ 0, 11371 }, 11372 #endif /* chips */ 11373 11374 #if defined(BCM_56560_A0) 11375 { /* SOC_FORMAT_INT_ENQ_TO_AGING_PKT_PTR_BCM56560_A0fmt */ 11376 /* format ENQ_TO_AGING_PKT_PTRfmt */ 11377 /* nFields */ 2, 11378 /* *fields */ soc_ENQ_TO_AGING_PKT_PTR_BCM56560_A0fmt_fields, 11379 /* bits */ 20, 11380 /* flags */ 0, 11381 }, 11382 #endif /* chips */ 11383 11384 #if defined(BCM_56560_B0) 11385 { /* SOC_FORMAT_INT_ENQ_TO_AGING_PKT_PTR_BCM56560_B0fmt */ 11386 /* format ENQ_TO_AGING_PKT_PTRfmt */ 11387 /* nFields */ 2, 11388 /* *fields */ soc_ENQ_TO_AGING_PKT_PTR_BCM56560_A0fmt_fields, 11389 /* bits */ 20, 11390 /* flags */ 0, 11391 }, 11392 #endif /* chips */ 11393 11394 #if defined(BCM_56624_A0) 11395 { /* SOC_FORMAT_INT_ENQ_TO_AGING_PKT_PTR_BCM56624_A0fmt */ 11396 /* format ENQ_TO_AGING_PKT_PTRfmt */ 11397 /* nFields */ 2, 11398 /* *fields */ soc_ENQ_TO_AGING_PKT_PTR_BCM56624_A0fmt_fields, 11399 /* bits */ 18, 11400 /* flags */ 0, 11401 }, 11402 #endif /* chips */ 11403 11404 #if defined(BCM_56624_B0) 11405 { /* SOC_FORMAT_INT_ENQ_TO_AGING_PKT_PTR_BCM56624_B0fmt */ 11406 /* format ENQ_TO_AGING_PKT_PTRfmt */ 11407 /* nFields */ 2, 11408 /* *fields */ soc_ENQ_TO_AGING_PKT_PTR_BCM56624_A0fmt_fields, 11409 /* bits */ 18, 11410 /* flags */ 0, 11411 }, 11412 #endif /* chips */ 11413 11414 #if defined(BCM_56634_A0) 11415 { /* SOC_FORMAT_INT_ENQ_TO_AGING_PKT_PTR_BCM56634_A0fmt */ 11416 /* format ENQ_TO_AGING_PKT_PTRfmt */ 11417 /* nFields */ 2, 11418 /* *fields */ soc_ENQ_TO_AGING_PKT_PTR_BCM56624_A0fmt_fields, 11419 /* bits */ 18, 11420 /* flags */ 0, 11421 }, 11422 #endif /* chips */ 11423 11424 #if defined(BCM_56634_B0) 11425 { /* SOC_FORMAT_INT_ENQ_TO_AGING_PKT_PTR_BCM56634_B0fmt */ 11426 /* format ENQ_TO_AGING_PKT_PTRfmt */ 11427 /* nFields */ 2, 11428 /* *fields */ soc_ENQ_TO_AGING_PKT_PTR_BCM56624_A0fmt_fields, 11429 /* bits */ 18, 11430 /* flags */ 0, 11431 }, 11432 #endif /* chips */ 11433 11434 #if defined(BCM_56640_A0) 11435 { /* SOC_FORMAT_INT_ENQ_TO_AGING_PKT_PTR_BCM56640_A0fmt */ 11436 /* format ENQ_TO_AGING_PKT_PTRfmt */ 11437 /* nFields */ 2, 11438 /* *fields */ soc_ENQ_TO_AGING_PKT_PTR_BCM56640_A0fmt_fields, 11439 /* bits */ 19, 11440 /* flags */ 0, 11441 }, 11442 #endif /* chips */ 11443 11444 #if defined(BCM_56670_A0) 11445 { /* SOC_FORMAT_INT_ENQ_TO_AGING_PKT_PTR_BCM56670_A0fmt */ 11446 /* format ENQ_TO_AGING_PKT_PTRfmt */ 11447 /* nFields */ 2, 11448 /* *fields */ soc_ENQ_TO_AGING_PKT_PTR_BCM56670_A0fmt_fields, 11449 /* bits */ 19, 11450 /* flags */ 0, 11451 }, 11452 #endif /* chips */ 11453 11454 #if defined(BCM_56670_B0) 11455 { /* SOC_FORMAT_INT_ENQ_TO_AGING_PKT_PTR_BCM56670_B0fmt */ 11456 /* format ENQ_TO_AGING_PKT_PTRfmt */ 11457 /* nFields */ 2, 11458 /* *fields */ soc_ENQ_TO_AGING_PKT_PTR_BCM56670_A0fmt_fields, 11459 /* bits */ 19, 11460 /* flags */ 0, 11461 }, 11462 #endif /* chips */ 11463 11464 #if defined(BCM_56680_A0) 11465 { /* SOC_FORMAT_INT_ENQ_TO_AGING_PKT_PTR_BCM56680_A0fmt */ 11466 /* format ENQ_TO_AGING_PKT_PTRfmt */ 11467 /* nFields */ 2, 11468 /* *fields */ soc_ENQ_TO_AGING_PKT_PTR_BCM56624_A0fmt_fields, 11469 /* bits */ 18, 11470 /* flags */ 0, 11471 }, 11472 #endif /* chips */ 11473 11474 #if defined(BCM_56680_B0) 11475 { /* SOC_FORMAT_INT_ENQ_TO_AGING_PKT_PTR_BCM56680_B0fmt */ 11476 /* format ENQ_TO_AGING_PKT_PTRfmt */ 11477 /* nFields */ 2, 11478 /* *fields */ soc_ENQ_TO_AGING_PKT_PTR_BCM56624_A0fmt_fields, 11479 /* bits */ 18, 11480 /* flags */ 0, 11481 }, 11482 #endif /* chips */ 11483 11484 #if defined(BCM_56685_A0) 11485 { /* SOC_FORMAT_INT_ENQ_TO_AGING_PKT_PTR_BCM56685_A0fmt */ 11486 /* format ENQ_TO_AGING_PKT_PTRfmt */ 11487 /* nFields */ 2, 11488 /* *fields */ soc_ENQ_TO_AGING_PKT_PTR_BCM56624_A0fmt_fields, 11489 /* bits */ 18, 11490 /* flags */ 0, 11491 }, 11492 #endif /* chips */ 11493 11494 #if defined(BCM_56685_B0) 11495 { /* SOC_FORMAT_INT_ENQ_TO_AGING_PKT_PTR_BCM56685_B0fmt */ 11496 /* format ENQ_TO_AGING_PKT_PTRfmt */ 11497 /* nFields */ 2, 11498 /* *fields */ soc_ENQ_TO_AGING_PKT_PTR_BCM56624_A0fmt_fields, 11499 /* bits */ 18, 11500 /* flags */ 0, 11501 }, 11502 #endif /* chips */ 11503 11504 #if defined(BCM_56725_A0) 11505 { /* SOC_FORMAT_INT_ENQ_TO_AGING_PKT_PTR_BCM56725_A0fmt */ 11506 /* format ENQ_TO_AGING_PKT_PTRfmt */ 11507 /* nFields */ 2, 11508 /* *fields */ soc_ENQ_TO_AGING_PKT_PTR_BCM56820_A0fmt_fields, 11509 /* bits */ 18, 11510 /* flags */ 0, 11511 }, 11512 #endif /* chips */ 11513 11514 #if defined(BCM_56820_A0) 11515 { /* SOC_FORMAT_INT_ENQ_TO_AGING_PKT_PTR_BCM56820_A0fmt */ 11516 /* format ENQ_TO_AGING_PKT_PTRfmt */ 11517 /* nFields */ 2, 11518 /* *fields */ soc_ENQ_TO_AGING_PKT_PTR_BCM56820_A0fmt_fields, 11519 /* bits */ 18, 11520 /* flags */ 0, 11521 }, 11522 #endif /* chips */ 11523 11524 #if defined(BCM_56840_A0) 11525 { /* SOC_FORMAT_INT_ENQ_TO_AGING_PKT_PTR_BCM56840_A0fmt */ 11526 /* format ENQ_TO_AGING_PKT_PTRfmt */ 11527 /* nFields */ 2, 11528 /* *fields */ soc_ENQ_TO_AGING_PKT_PTR_BCM56840_A0fmt_fields, 11529 /* bits */ 20, 11530 /* flags */ 0, 11531 }, 11532 #endif /* chips */ 11533 11534 #if defined(BCM_56840_B0) 11535 { /* SOC_FORMAT_INT_ENQ_TO_AGING_PKT_PTR_BCM56840_B0fmt */ 11536 /* format ENQ_TO_AGING_PKT_PTRfmt */ 11537 /* nFields */ 2, 11538 /* *fields */ soc_ENQ_TO_AGING_PKT_PTR_BCM56840_A0fmt_fields, 11539 /* bits */ 20, 11540 /* flags */ 0, 11541 }, 11542 #endif /* chips */ 11543 11544 #if defined(BCM_56850_A0) 11545 { /* SOC_FORMAT_INT_ENQ_TO_AGING_PKT_PTR_BCM56850_A0fmt */ 11546 /* format ENQ_TO_AGING_PKT_PTRfmt */ 11547 /* nFields */ 2, 11548 /* *fields */ soc_ENQ_TO_AGING_PKT_PTR_BCM56850_A0fmt_fields, 11549 /* bits */ 21, 11550 /* flags */ 0, 11551 }, 11552 #endif /* chips */ 11553 11554 #if defined(BCM_56860_A0) 11555 { /* SOC_FORMAT_INT_ENQ_TO_AGING_PKT_PTR_BCM56860_A0fmt */ 11556 /* format ENQ_TO_AGING_PKT_PTRfmt */ 11557 /* nFields */ 2, 11558 /* *fields */ soc_ENQ_TO_AGING_PKT_PTR_BCM56850_A0fmt_fields, 11559 /* bits */ 21, 11560 /* flags */ 0, 11561 }, 11562 #endif /* chips */ 11563 11564 #if defined(BCM_88732_A0) 11565 { /* SOC_FORMAT_INT_ENQ_TO_AGING_PKT_PTR_BCM88732_A0fmt */ 11566 /* format ENQ_TO_AGING_PKT_PTRfmt */ 11567 /* nFields */ 2, 11568 /* *fields */ soc_ENQ_TO_AGING_PKT_PTR_BCM88732_A0fmt_fields, 11569 /* bits */ 21, 11570 /* flags */ 0, 11571 }, 11572 #endif /* chips */ 11573 11574 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) 11575 { /* SOC_FORMAT_INT_ENQ_TO_CLINKE_INFOfmt */ 11576 /* format ENQ_TO_CLINKE_INFOfmt */ 11577 /* nFields */ 2, 11578 /* *fields */ soc_ENQ_TO_CLINKE_INFOfmt_fields, 11579 /* bits */ 23, 11580 /* flags */ 0, 11581 }, 11582 #endif /* chips */ 11583 11584 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) 11585 { /* SOC_FORMAT_INT_ENQ_TO_CLINKI_INFOfmt */ 11586 /* format ENQ_TO_CLINKI_INFOfmt */ 11587 /* nFields */ 2, 11588 /* *fields */ soc_ENQ_TO_CLINKI_INFOfmt_fields, 11589 /* bits */ 15, 11590 /* flags */ 0, 11591 }, 11592 #endif /* chips */ 11593 11594 #if defined(BCM_56260_A0) 11595 { /* SOC_FORMAT_INT_ENQ_TO_CLINKI_INFO_BCM56260_A0fmt */ 11596 /* format ENQ_TO_CLINKI_INFOfmt */ 11597 /* nFields */ 2, 11598 /* *fields */ soc_ENQ_TO_CLINKI_INFO_BCM56260_A0fmt_fields, 11599 /* bits */ 15, 11600 /* flags */ 0, 11601 }, 11602 #endif /* chips */ 11603 11604 #if defined(BCM_56260_B0) 11605 { /* SOC_FORMAT_INT_ENQ_TO_CLINKI_INFO_BCM56260_B0fmt */ 11606 /* format ENQ_TO_CLINKI_INFOfmt */ 11607 /* nFields */ 2, 11608 /* *fields */ soc_ENQ_TO_CLINKI_INFO_BCM56260_A0fmt_fields, 11609 /* bits */ 15, 11610 /* flags */ 0, 11611 }, 11612 #endif /* chips */ 11613 11614 #if defined(BCM_56270_A0) 11615 { /* SOC_FORMAT_INT_ENQ_TO_CLINKI_INFO_BCM56270_A0fmt */ 11616 /* format ENQ_TO_CLINKI_INFOfmt */ 11617 /* nFields */ 2, 11618 /* *fields */ soc_ENQ_TO_CLINKI_INFO_BCM56260_A0fmt_fields, 11619 /* bits */ 15, 11620 /* flags */ 0, 11621 }, 11622 #endif /* chips */ 11623 11624 #if defined(BCM_56450_A0) 11625 { /* SOC_FORMAT_INT_ENQ_TO_CLINKI_INFO_BCM56450_A0fmt */ 11626 /* format ENQ_TO_CLINKI_INFOfmt */ 11627 /* nFields */ 2, 11628 /* *fields */ soc_ENQ_TO_CLINKI_INFO_BCM56450_A0fmt_fields, 11629 /* bits */ 15, 11630 /* flags */ 0, 11631 }, 11632 #endif /* chips */ 11633 11634 #if defined(BCM_56450_B0) 11635 { /* SOC_FORMAT_INT_ENQ_TO_CLINKI_INFO_BCM56450_B0fmt */ 11636 /* format ENQ_TO_CLINKI_INFOfmt */ 11637 /* nFields */ 2, 11638 /* *fields */ soc_ENQ_TO_CLINKI_INFO_BCM56450_A0fmt_fields, 11639 /* bits */ 15, 11640 /* flags */ 0, 11641 }, 11642 #endif /* chips */ 11643 11644 #if defined(BCM_56450_B1) 11645 { /* SOC_FORMAT_INT_ENQ_TO_CLINKI_INFO_BCM56450_B1fmt */ 11646 /* format ENQ_TO_CLINKI_INFOfmt */ 11647 /* nFields */ 2, 11648 /* *fields */ soc_ENQ_TO_CLINKI_INFO_BCM56450_A0fmt_fields, 11649 /* bits */ 15, 11650 /* flags */ 0, 11651 }, 11652 #endif /* chips */ 11653 11654 #if defined(BCM_56440_A0) 11655 { /* SOC_FORMAT_INT_ENQ_TO_CTR_INFOfmt */ 11656 /* format ENQ_TO_CTR_INFOfmt */ 11657 /* nFields */ 1, 11658 /* *fields */ soc_CFG_TO_CTR_REG_INFOfmt_fields, 11659 /* bits */ 1, 11660 /* flags */ 0, 11661 }, 11662 #endif /* chips */ 11663 11664 #if defined(BCM_56260_A0) 11665 { /* SOC_FORMAT_INT_ENQ_TO_CTR_INFO_BCM56260_A0fmt */ 11666 /* format ENQ_TO_CTR_INFOfmt */ 11667 /* nFields */ 1, 11668 /* *fields */ soc_CFG_TO_CTR_REG_INFO_BCM56260_A0fmt_fields, 11669 /* bits */ 1, 11670 /* flags */ 0, 11671 }, 11672 #endif /* chips */ 11673 11674 #if defined(BCM_56260_B0) 11675 { /* SOC_FORMAT_INT_ENQ_TO_CTR_INFO_BCM56260_B0fmt */ 11676 /* format ENQ_TO_CTR_INFOfmt */ 11677 /* nFields */ 1, 11678 /* *fields */ soc_CFG_TO_CTR_REG_INFO_BCM56260_A0fmt_fields, 11679 /* bits */ 1, 11680 /* flags */ 0, 11681 }, 11682 #endif /* chips */ 11683 11684 #if defined(BCM_56270_A0) 11685 { /* SOC_FORMAT_INT_ENQ_TO_CTR_INFO_BCM56270_A0fmt */ 11686 /* format ENQ_TO_CTR_INFOfmt */ 11687 /* nFields */ 1, 11688 /* *fields */ soc_CFG_TO_CTR_REG_INFO_BCM56260_A0fmt_fields, 11689 /* bits */ 1, 11690 /* flags */ 0, 11691 }, 11692 #endif /* chips */ 11693 11694 #if defined(BCM_56440_B0) 11695 { /* SOC_FORMAT_INT_ENQ_TO_CTR_INFO_BCM56440_B0fmt */ 11696 /* format ENQ_TO_CTR_INFOfmt */ 11697 /* nFields */ 1, 11698 /* *fields */ soc_CFG_TO_CTR_REG_INFOfmt_fields, 11699 /* bits */ 1, 11700 /* flags */ 0, 11701 }, 11702 #endif /* chips */ 11703 11704 #if defined(BCM_56450_A0) 11705 { /* SOC_FORMAT_INT_ENQ_TO_CTR_INFO_BCM56450_A0fmt */ 11706 /* format ENQ_TO_CTR_INFOfmt */ 11707 /* nFields */ 1, 11708 /* *fields */ soc_CFG_TO_CTR_REG_INFO_BCM56450_A0fmt_fields, 11709 /* bits */ 1, 11710 /* flags */ 0, 11711 }, 11712 #endif /* chips */ 11713 11714 #if defined(BCM_56450_B0) 11715 { /* SOC_FORMAT_INT_ENQ_TO_CTR_INFO_BCM56450_B0fmt */ 11716 /* format ENQ_TO_CTR_INFOfmt */ 11717 /* nFields */ 1, 11718 /* *fields */ soc_CFG_TO_CTR_REG_INFO_BCM56450_A0fmt_fields, 11719 /* bits */ 1, 11720 /* flags */ 0, 11721 }, 11722 #endif /* chips */ 11723 11724 #if defined(BCM_56450_B1) 11725 { /* SOC_FORMAT_INT_ENQ_TO_CTR_INFO_BCM56450_B1fmt */ 11726 /* format ENQ_TO_CTR_INFOfmt */ 11727 /* nFields */ 1, 11728 /* *fields */ soc_CFG_TO_CTR_REG_INFO_BCM56450_A0fmt_fields, 11729 /* bits */ 1, 11730 /* flags */ 0, 11731 }, 11732 #endif /* chips */ 11733 11734 #if defined(BCM_56725_A0) || defined(BCM_56800_A0) || \ 11735 defined(BCM_56820_A0) 11736 { /* SOC_FORMAT_INT_ENQ_TO_CTR_TX_PKT_INFOfmt */ 11737 /* format ENQ_TO_CTR_TX_PKT_INFOfmt */ 11738 /* nFields */ 3, 11739 /* *fields */ soc_ENQ_TO_CTR_TX_PKT_INFOfmt_fields, 11740 /* bits */ 13, 11741 /* flags */ 0, 11742 }, 11743 #endif /* chips */ 11744 11745 #if defined(BCM_56334_A0) 11746 { /* SOC_FORMAT_INT_ENQ_TO_CTR_TX_PKT_INFO_BCM56334_A0fmt */ 11747 /* format ENQ_TO_CTR_TX_PKT_INFOfmt */ 11748 /* nFields */ 3, 11749 /* *fields */ soc_ENQ_TO_CTR_TX_PKT_INFO_BCM56624_A0fmt_fields, 11750 /* bits */ 13, 11751 /* flags */ 0, 11752 }, 11753 #endif /* chips */ 11754 11755 #if defined(BCM_56334_B0) 11756 { /* SOC_FORMAT_INT_ENQ_TO_CTR_TX_PKT_INFO_BCM56334_B0fmt */ 11757 /* format ENQ_TO_CTR_TX_PKT_INFOfmt */ 11758 /* nFields */ 3, 11759 /* *fields */ soc_ENQ_TO_CTR_TX_PKT_INFO_BCM56624_A0fmt_fields, 11760 /* bits */ 13, 11761 /* flags */ 0, 11762 }, 11763 #endif /* chips */ 11764 11765 #if defined(BCM_56340_A0) 11766 { /* SOC_FORMAT_INT_ENQ_TO_CTR_TX_PKT_INFO_BCM56340_A0fmt */ 11767 /* format ENQ_TO_CTR_TX_PKT_INFOfmt */ 11768 /* nFields */ 8, 11769 /* *fields */ soc_ENQ_TO_CTR_TX_PKT_INFO_BCM56640_A0fmt_fields, 11770 /* bits */ 22, 11771 /* flags */ 0, 11772 }, 11773 #endif /* chips */ 11774 11775 #if defined(BCM_56440_A0) 11776 { /* SOC_FORMAT_INT_ENQ_TO_CTR_TX_PKT_INFO_BCM56440_A0fmt */ 11777 /* format ENQ_TO_CTR_TX_PKT_INFOfmt */ 11778 /* nFields */ 7, 11779 /* *fields */ soc_ENQ_TO_CTR_TX_PKT_INFO_BCM56840_A0fmt_fields, 11780 /* bits */ 23, 11781 /* flags */ 0, 11782 }, 11783 #endif /* chips */ 11784 11785 #if defined(BCM_56440_B0) 11786 { /* SOC_FORMAT_INT_ENQ_TO_CTR_TX_PKT_INFO_BCM56440_B0fmt */ 11787 /* format ENQ_TO_CTR_TX_PKT_INFOfmt */ 11788 /* nFields */ 7, 11789 /* *fields */ soc_ENQ_TO_CTR_TX_PKT_INFO_BCM56840_A0fmt_fields, 11790 /* bits */ 23, 11791 /* flags */ 0, 11792 }, 11793 #endif /* chips */ 11794 11795 #if defined(BCM_56450_A0) 11796 { /* SOC_FORMAT_INT_ENQ_TO_CTR_TX_PKT_INFO_BCM56450_A0fmt */ 11797 /* format ENQ_TO_CTR_TX_PKT_INFOfmt */ 11798 /* nFields */ 7, 11799 /* *fields */ soc_ENQ_TO_CTR_TX_PKT_INFO_BCM56450_A0fmt_fields, 11800 /* bits */ 23, 11801 /* flags */ 0, 11802 }, 11803 #endif /* chips */ 11804 11805 #if defined(BCM_56450_B0) 11806 { /* SOC_FORMAT_INT_ENQ_TO_CTR_TX_PKT_INFO_BCM56450_B0fmt */ 11807 /* format ENQ_TO_CTR_TX_PKT_INFOfmt */ 11808 /* nFields */ 7, 11809 /* *fields */ soc_ENQ_TO_CTR_TX_PKT_INFO_BCM56450_A0fmt_fields, 11810 /* bits */ 23, 11811 /* flags */ 0, 11812 }, 11813 #endif /* chips */ 11814 11815 #if defined(BCM_56450_B1) 11816 { /* SOC_FORMAT_INT_ENQ_TO_CTR_TX_PKT_INFO_BCM56450_B1fmt */ 11817 /* format ENQ_TO_CTR_TX_PKT_INFOfmt */ 11818 /* nFields */ 7, 11819 /* *fields */ soc_ENQ_TO_CTR_TX_PKT_INFO_BCM56450_A0fmt_fields, 11820 /* bits */ 23, 11821 /* flags */ 0, 11822 }, 11823 #endif /* chips */ 11824 11825 #if defined(BCM_56524_A0) 11826 { /* SOC_FORMAT_INT_ENQ_TO_CTR_TX_PKT_INFO_BCM56524_A0fmt */ 11827 /* format ENQ_TO_CTR_TX_PKT_INFOfmt */ 11828 /* nFields */ 3, 11829 /* *fields */ soc_ENQ_TO_CTR_TX_PKT_INFO_BCM56624_A0fmt_fields, 11830 /* bits */ 13, 11831 /* flags */ 0, 11832 }, 11833 #endif /* chips */ 11834 11835 #if defined(BCM_56524_B0) 11836 { /* SOC_FORMAT_INT_ENQ_TO_CTR_TX_PKT_INFO_BCM56524_B0fmt */ 11837 /* format ENQ_TO_CTR_TX_PKT_INFOfmt */ 11838 /* nFields */ 3, 11839 /* *fields */ soc_ENQ_TO_CTR_TX_PKT_INFO_BCM56624_A0fmt_fields, 11840 /* bits */ 13, 11841 /* flags */ 0, 11842 }, 11843 #endif /* chips */ 11844 11845 #if defined(BCM_56560_A0) 11846 { /* SOC_FORMAT_INT_ENQ_TO_CTR_TX_PKT_INFO_BCM56560_A0fmt */ 11847 /* format ENQ_TO_CTR_TX_PKT_INFOfmt */ 11848 /* nFields */ 8, 11849 /* *fields */ soc_ENQ_TO_CTR_TX_PKT_INFO_BCM56560_A0fmt_fields, 11850 /* bits */ 36, 11851 /* flags */ 0, 11852 }, 11853 #endif /* chips */ 11854 11855 #if defined(BCM_56560_B0) 11856 { /* SOC_FORMAT_INT_ENQ_TO_CTR_TX_PKT_INFO_BCM56560_B0fmt */ 11857 /* format ENQ_TO_CTR_TX_PKT_INFOfmt */ 11858 /* nFields */ 8, 11859 /* *fields */ soc_ENQ_TO_CTR_TX_PKT_INFO_BCM56560_A0fmt_fields, 11860 /* bits */ 36, 11861 /* flags */ 0, 11862 }, 11863 #endif /* chips */ 11864 11865 #if defined(BCM_56624_A0) 11866 { /* SOC_FORMAT_INT_ENQ_TO_CTR_TX_PKT_INFO_BCM56624_A0fmt */ 11867 /* format ENQ_TO_CTR_TX_PKT_INFOfmt */ 11868 /* nFields */ 3, 11869 /* *fields */ soc_ENQ_TO_CTR_TX_PKT_INFO_BCM56624_A0fmt_fields, 11870 /* bits */ 13, 11871 /* flags */ 0, 11872 }, 11873 #endif /* chips */ 11874 11875 #if defined(BCM_56624_B0) 11876 { /* SOC_FORMAT_INT_ENQ_TO_CTR_TX_PKT_INFO_BCM56624_B0fmt */ 11877 /* format ENQ_TO_CTR_TX_PKT_INFOfmt */ 11878 /* nFields */ 3, 11879 /* *fields */ soc_ENQ_TO_CTR_TX_PKT_INFO_BCM56624_A0fmt_fields, 11880 /* bits */ 13, 11881 /* flags */ 0, 11882 }, 11883 #endif /* chips */ 11884 11885 #if defined(BCM_56634_A0) 11886 { /* SOC_FORMAT_INT_ENQ_TO_CTR_TX_PKT_INFO_BCM56634_A0fmt */ 11887 /* format ENQ_TO_CTR_TX_PKT_INFOfmt */ 11888 /* nFields */ 3, 11889 /* *fields */ soc_ENQ_TO_CTR_TX_PKT_INFO_BCM56624_A0fmt_fields, 11890 /* bits */ 13, 11891 /* flags */ 0, 11892 }, 11893 #endif /* chips */ 11894 11895 #if defined(BCM_56634_B0) 11896 { /* SOC_FORMAT_INT_ENQ_TO_CTR_TX_PKT_INFO_BCM56634_B0fmt */ 11897 /* format ENQ_TO_CTR_TX_PKT_INFOfmt */ 11898 /* nFields */ 3, 11899 /* *fields */ soc_ENQ_TO_CTR_TX_PKT_INFO_BCM56624_A0fmt_fields, 11900 /* bits */ 13, 11901 /* flags */ 0, 11902 }, 11903 #endif /* chips */ 11904 11905 #if defined(BCM_56640_A0) 11906 { /* SOC_FORMAT_INT_ENQ_TO_CTR_TX_PKT_INFO_BCM56640_A0fmt */ 11907 /* format ENQ_TO_CTR_TX_PKT_INFOfmt */ 11908 /* nFields */ 8, 11909 /* *fields */ soc_ENQ_TO_CTR_TX_PKT_INFO_BCM56640_A0fmt_fields, 11910 /* bits */ 22, 11911 /* flags */ 0, 11912 }, 11913 #endif /* chips */ 11914 11915 #if defined(BCM_56670_A0) 11916 { /* SOC_FORMAT_INT_ENQ_TO_CTR_TX_PKT_INFO_BCM56670_A0fmt */ 11917 /* format ENQ_TO_CTR_TX_PKT_INFOfmt */ 11918 /* nFields */ 8, 11919 /* *fields */ soc_ENQ_TO_CTR_TX_PKT_INFO_BCM56670_A0fmt_fields, 11920 /* bits */ 32, 11921 /* flags */ 0, 11922 }, 11923 #endif /* chips */ 11924 11925 #if defined(BCM_56670_B0) 11926 { /* SOC_FORMAT_INT_ENQ_TO_CTR_TX_PKT_INFO_BCM56670_B0fmt */ 11927 /* format ENQ_TO_CTR_TX_PKT_INFOfmt */ 11928 /* nFields */ 8, 11929 /* *fields */ soc_ENQ_TO_CTR_TX_PKT_INFO_BCM56670_A0fmt_fields, 11930 /* bits */ 32, 11931 /* flags */ 0, 11932 }, 11933 #endif /* chips */ 11934 11935 #if defined(BCM_56680_A0) 11936 { /* SOC_FORMAT_INT_ENQ_TO_CTR_TX_PKT_INFO_BCM56680_A0fmt */ 11937 /* format ENQ_TO_CTR_TX_PKT_INFOfmt */ 11938 /* nFields */ 3, 11939 /* *fields */ soc_ENQ_TO_CTR_TX_PKT_INFO_BCM56624_A0fmt_fields, 11940 /* bits */ 13, 11941 /* flags */ 0, 11942 }, 11943 #endif /* chips */ 11944 11945 #if defined(BCM_56680_B0) 11946 { /* SOC_FORMAT_INT_ENQ_TO_CTR_TX_PKT_INFO_BCM56680_B0fmt */ 11947 /* format ENQ_TO_CTR_TX_PKT_INFOfmt */ 11948 /* nFields */ 3, 11949 /* *fields */ soc_ENQ_TO_CTR_TX_PKT_INFO_BCM56624_A0fmt_fields, 11950 /* bits */ 13, 11951 /* flags */ 0, 11952 }, 11953 #endif /* chips */ 11954 11955 #if defined(BCM_56685_A0) 11956 { /* SOC_FORMAT_INT_ENQ_TO_CTR_TX_PKT_INFO_BCM56685_A0fmt */ 11957 /* format ENQ_TO_CTR_TX_PKT_INFOfmt */ 11958 /* nFields */ 3, 11959 /* *fields */ soc_ENQ_TO_CTR_TX_PKT_INFO_BCM56624_A0fmt_fields, 11960 /* bits */ 13, 11961 /* flags */ 0, 11962 }, 11963 #endif /* chips */ 11964 11965 #if defined(BCM_56685_B0) 11966 { /* SOC_FORMAT_INT_ENQ_TO_CTR_TX_PKT_INFO_BCM56685_B0fmt */ 11967 /* format ENQ_TO_CTR_TX_PKT_INFOfmt */ 11968 /* nFields */ 3, 11969 /* *fields */ soc_ENQ_TO_CTR_TX_PKT_INFO_BCM56624_A0fmt_fields, 11970 /* bits */ 13, 11971 /* flags */ 0, 11972 }, 11973 #endif /* chips */ 11974 11975 #if defined(BCM_56840_A0) 11976 { /* SOC_FORMAT_INT_ENQ_TO_CTR_TX_PKT_INFO_BCM56840_A0fmt */ 11977 /* format ENQ_TO_CTR_TX_PKT_INFOfmt */ 11978 /* nFields */ 7, 11979 /* *fields */ soc_ENQ_TO_CTR_TX_PKT_INFO_BCM56840_A0fmt_fields, 11980 /* bits */ 23, 11981 /* flags */ 0, 11982 }, 11983 #endif /* chips */ 11984 11985 #if defined(BCM_56840_B0) 11986 { /* SOC_FORMAT_INT_ENQ_TO_CTR_TX_PKT_INFO_BCM56840_B0fmt */ 11987 /* format ENQ_TO_CTR_TX_PKT_INFOfmt */ 11988 /* nFields */ 7, 11989 /* *fields */ soc_ENQ_TO_CTR_TX_PKT_INFO_BCM56840_A0fmt_fields, 11990 /* bits */ 23, 11991 /* flags */ 0, 11992 }, 11993 #endif /* chips */ 11994 11995 #if defined(BCM_56850_A0) 11996 { /* SOC_FORMAT_INT_ENQ_TO_CTR_TX_PKT_INFO_BCM56850_A0fmt */ 11997 /* format ENQ_TO_CTR_TX_PKT_INFOfmt */ 11998 /* nFields */ 8, 11999 /* *fields */ soc_ENQ_TO_CTR_TX_PKT_INFO_BCM56850_A0fmt_fields, 12000 /* bits */ 34, 12001 /* flags */ 0, 12002 }, 12003 #endif /* chips */ 12004 12005 #if defined(BCM_56860_A0) 12006 { /* SOC_FORMAT_INT_ENQ_TO_CTR_TX_PKT_INFO_BCM56860_A0fmt */ 12007 /* format ENQ_TO_CTR_TX_PKT_INFOfmt */ 12008 /* nFields */ 8, 12009 /* *fields */ soc_ENQ_TO_CTR_TX_PKT_INFO_BCM56850_A0fmt_fields, 12010 /* bits */ 34, 12011 /* flags */ 0, 12012 }, 12013 #endif /* chips */ 12014 12015 #if defined(BCM_88732_A0) 12016 { /* SOC_FORMAT_INT_ENQ_TO_CTR_TX_PKT_INFO_BCM88732_A0fmt */ 12017 /* format ENQ_TO_CTR_TX_PKT_INFOfmt */ 12018 /* nFields */ 9, 12019 /* *fields */ soc_ENQ_TO_CTR_TX_PKT_INFO_BCM88732_A0fmt_fields, 12020 /* bits */ 27, 12021 /* flags */ 0, 12022 }, 12023 #endif /* chips */ 12024 12025 #if defined(BCM_56340_A0) || defined(BCM_56640_A0) 12026 { /* SOC_FORMAT_INT_ENQ_TO_DEQ_ASF_INFOfmt */ 12027 /* format ENQ_TO_DEQ_ASF_INFOfmt */ 12028 /* nFields */ 6, 12029 /* *fields */ soc_ENQ_TO_DEQ_ASF_INFOfmt_fields, 12030 /* bits */ 42, 12031 /* flags */ 0, 12032 }, 12033 #endif /* chips */ 12034 12035 #if defined(BCM_56560_A0) 12036 { /* SOC_FORMAT_INT_ENQ_TO_DEQ_ASF_INFO_BCM56560_A0fmt */ 12037 /* format ENQ_TO_DEQ_ASF_INFOfmt */ 12038 /* nFields */ 11, 12039 /* *fields */ soc_ENQ_TO_DEQ_ASF_INFO_BCM56560_A0fmt_fields, 12040 /* bits */ 63, 12041 /* flags */ 0, 12042 }, 12043 #endif /* chips */ 12044 12045 #if defined(BCM_56560_B0) 12046 { /* SOC_FORMAT_INT_ENQ_TO_DEQ_ASF_INFO_BCM56560_B0fmt */ 12047 /* format ENQ_TO_DEQ_ASF_INFOfmt */ 12048 /* nFields */ 11, 12049 /* *fields */ soc_ENQ_TO_DEQ_ASF_INFO_BCM56560_A0fmt_fields, 12050 /* bits */ 63, 12051 /* flags */ 0, 12052 }, 12053 #endif /* chips */ 12054 12055 #if defined(BCM_56670_A0) 12056 { /* SOC_FORMAT_INT_ENQ_TO_DEQ_ASF_INFO_BCM56670_A0fmt */ 12057 /* format ENQ_TO_DEQ_ASF_INFOfmt */ 12058 /* nFields */ 11, 12059 /* *fields */ soc_ENQ_TO_DEQ_ASF_INFO_BCM56670_A0fmt_fields, 12060 /* bits */ 57, 12061 /* flags */ 0, 12062 }, 12063 #endif /* chips */ 12064 12065 #if defined(BCM_56670_B0) 12066 { /* SOC_FORMAT_INT_ENQ_TO_DEQ_ASF_INFO_BCM56670_B0fmt */ 12067 /* format ENQ_TO_DEQ_ASF_INFOfmt */ 12068 /* nFields */ 11, 12069 /* *fields */ soc_ENQ_TO_DEQ_ASF_INFO_BCM56670_A0fmt_fields, 12070 /* bits */ 57, 12071 /* flags */ 0, 12072 }, 12073 #endif /* chips */ 12074 12075 #if defined(BCM_56850_A0) 12076 { /* SOC_FORMAT_INT_ENQ_TO_DEQ_ASF_INFO_BCM56850_A0fmt */ 12077 /* format ENQ_TO_DEQ_ASF_INFOfmt */ 12078 /* nFields */ 11, 12079 /* *fields */ soc_ENQ_TO_DEQ_ASF_INFO_BCM56850_A0fmt_fields, 12080 /* bits */ 64, 12081 /* flags */ 0, 12082 }, 12083 #endif /* chips */ 12084 12085 #if defined(BCM_56860_A0) 12086 { /* SOC_FORMAT_INT_ENQ_TO_DEQ_ASF_INFO_BCM56860_A0fmt */ 12087 /* format ENQ_TO_DEQ_ASF_INFOfmt */ 12088 /* nFields */ 11, 12089 /* *fields */ soc_ENQ_TO_DEQ_ASF_INFO_BCM56850_A0fmt_fields, 12090 /* bits */ 64, 12091 /* flags */ 0, 12092 }, 12093 #endif /* chips */ 12094 12095 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) 12096 { /* SOC_FORMAT_INT_ENQ_TO_E2EFC_INFO_BUSfmt */ 12097 /* format ENQ_TO_E2EFC_INFO_BUSfmt */ 12098 /* nFields */ 9, 12099 /* *fields */ soc_ENQ_TO_E2EFC_INFO_BUSfmt_fields, 12100 /* bits */ 90, 12101 /* flags */ 0, 12102 }, 12103 #endif /* chips */ 12104 12105 #if defined(BCM_56260_A0) 12106 { /* SOC_FORMAT_INT_ENQ_TO_E2EFC_INFO_BUS_BCM56260_A0fmt */ 12107 /* format ENQ_TO_E2EFC_INFO_BUSfmt */ 12108 /* nFields */ 9, 12109 /* *fields */ soc_ENQ_TO_E2EFC_INFO_BUS_BCM56260_A0fmt_fields, 12110 /* bits */ 89, 12111 /* flags */ 0, 12112 }, 12113 #endif /* chips */ 12114 12115 #if defined(BCM_56260_B0) 12116 { /* SOC_FORMAT_INT_ENQ_TO_E2EFC_INFO_BUS_BCM56260_B0fmt */ 12117 /* format ENQ_TO_E2EFC_INFO_BUSfmt */ 12118 /* nFields */ 9, 12119 /* *fields */ soc_ENQ_TO_E2EFC_INFO_BUS_BCM56260_A0fmt_fields, 12120 /* bits */ 89, 12121 /* flags */ 0, 12122 }, 12123 #endif /* chips */ 12124 12125 #if defined(BCM_56270_A0) 12126 { /* SOC_FORMAT_INT_ENQ_TO_E2EFC_INFO_BUS_BCM56270_A0fmt */ 12127 /* format ENQ_TO_E2EFC_INFO_BUSfmt */ 12128 /* nFields */ 9, 12129 /* *fields */ soc_ENQ_TO_E2EFC_INFO_BUS_BCM56270_A0fmt_fields, 12130 /* bits */ 88, 12131 /* flags */ 0, 12132 }, 12133 #endif /* chips */ 12134 12135 #if defined(BCM_56450_A0) 12136 { /* SOC_FORMAT_INT_ENQ_TO_E2EFC_INFO_BUS_BCM56450_A0fmt */ 12137 /* format ENQ_TO_E2EFC_INFO_BUSfmt */ 12138 /* nFields */ 9, 12139 /* *fields */ soc_ENQ_TO_E2EFC_INFO_BUS_BCM56450_A0fmt_fields, 12140 /* bits */ 90, 12141 /* flags */ 0, 12142 }, 12143 #endif /* chips */ 12144 12145 #if defined(BCM_56450_B0) 12146 { /* SOC_FORMAT_INT_ENQ_TO_E2EFC_INFO_BUS_BCM56450_B0fmt */ 12147 /* format ENQ_TO_E2EFC_INFO_BUSfmt */ 12148 /* nFields */ 9, 12149 /* *fields */ soc_ENQ_TO_E2EFC_INFO_BUS_BCM56450_A0fmt_fields, 12150 /* bits */ 90, 12151 /* flags */ 0, 12152 }, 12153 #endif /* chips */ 12154 12155 #if defined(BCM_56450_B1) 12156 { /* SOC_FORMAT_INT_ENQ_TO_E2EFC_INFO_BUS_BCM56450_B1fmt */ 12157 /* format ENQ_TO_E2EFC_INFO_BUSfmt */ 12158 /* nFields */ 9, 12159 /* *fields */ soc_ENQ_TO_E2EFC_INFO_BUS_BCM56450_A0fmt_fields, 12160 /* bits */ 90, 12161 /* flags */ 0, 12162 }, 12163 #endif /* chips */ 12164 12165 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) 12166 { /* SOC_FORMAT_INT_ENQ_TO_E2EFC_QEN_PURGE_INFOfmt */ 12167 /* format ENQ_TO_E2EFC_QEN_PURGE_INFOfmt */ 12168 /* nFields */ 1, 12169 /* *fields */ soc_ENQ_TO_E2EFC_QEN_PURGE_INFOfmt_fields, 12170 /* bits */ 10, 12171 /* flags */ 0, 12172 }, 12173 #endif /* chips */ 12174 12175 #if defined(BCM_56260_A0) 12176 { /* SOC_FORMAT_INT_ENQ_TO_E2EFC_QEN_PURGE_INFO_BCM56260_A0fmt */ 12177 /* format ENQ_TO_E2EFC_QEN_PURGE_INFOfmt */ 12178 /* nFields */ 1, 12179 /* *fields */ soc_ENQ_TO_E2EFC_QEN_PURGE_INFO_BCM56260_A0fmt_fields, 12180 /* bits */ 10, 12181 /* flags */ 0, 12182 }, 12183 #endif /* chips */ 12184 12185 #if defined(BCM_56260_B0) 12186 { /* SOC_FORMAT_INT_ENQ_TO_E2EFC_QEN_PURGE_INFO_BCM56260_B0fmt */ 12187 /* format ENQ_TO_E2EFC_QEN_PURGE_INFOfmt */ 12188 /* nFields */ 1, 12189 /* *fields */ soc_ENQ_TO_E2EFC_QEN_PURGE_INFO_BCM56260_A0fmt_fields, 12190 /* bits */ 10, 12191 /* flags */ 0, 12192 }, 12193 #endif /* chips */ 12194 12195 #if defined(BCM_56270_A0) 12196 { /* SOC_FORMAT_INT_ENQ_TO_E2EFC_QEN_PURGE_INFO_BCM56270_A0fmt */ 12197 /* format ENQ_TO_E2EFC_QEN_PURGE_INFOfmt */ 12198 /* nFields */ 1, 12199 /* *fields */ soc_ENQ_TO_E2EFC_QEN_PURGE_INFO_BCM56260_A0fmt_fields, 12200 /* bits */ 10, 12201 /* flags */ 0, 12202 }, 12203 #endif /* chips */ 12204 12205 #if defined(BCM_56450_A0) 12206 { /* SOC_FORMAT_INT_ENQ_TO_E2EFC_QEN_PURGE_INFO_BCM56450_A0fmt */ 12207 /* format ENQ_TO_E2EFC_QEN_PURGE_INFOfmt */ 12208 /* nFields */ 1, 12209 /* *fields */ soc_ENQ_TO_E2EFC_QEN_PURGE_INFO_BCM56450_A0fmt_fields, 12210 /* bits */ 10, 12211 /* flags */ 0, 12212 }, 12213 #endif /* chips */ 12214 12215 #if defined(BCM_56450_B0) 12216 { /* SOC_FORMAT_INT_ENQ_TO_E2EFC_QEN_PURGE_INFO_BCM56450_B0fmt */ 12217 /* format ENQ_TO_E2EFC_QEN_PURGE_INFOfmt */ 12218 /* nFields */ 1, 12219 /* *fields */ soc_ENQ_TO_E2EFC_QEN_PURGE_INFO_BCM56450_A0fmt_fields, 12220 /* bits */ 10, 12221 /* flags */ 0, 12222 }, 12223 #endif /* chips */ 12224 12225 #if defined(BCM_56450_B1) 12226 { /* SOC_FORMAT_INT_ENQ_TO_E2EFC_QEN_PURGE_INFO_BCM56450_B1fmt */ 12227 /* format ENQ_TO_E2EFC_QEN_PURGE_INFOfmt */ 12228 /* nFields */ 1, 12229 /* *fields */ soc_ENQ_TO_E2EFC_QEN_PURGE_INFO_BCM56450_A0fmt_fields, 12230 /* bits */ 10, 12231 /* flags */ 0, 12232 }, 12233 #endif /* chips */ 12234 12235 #if defined(BCM_56440_A0) 12236 { /* SOC_FORMAT_INT_ENQ_TO_INTFI_INFOfmt */ 12237 /* format ENQ_TO_INTFI_INFOfmt */ 12238 /* nFields */ 4, 12239 /* *fields */ soc_ENQ_TO_INTFI_INFOfmt_fields, 12240 /* bits */ 528, 12241 /* flags */ 0, 12242 }, 12243 #endif /* chips */ 12244 12245 #if defined(BCM_56260_A0) 12246 { /* SOC_FORMAT_INT_ENQ_TO_INTFI_INFO_BCM56260_A0fmt */ 12247 /* format ENQ_TO_INTFI_INFOfmt */ 12248 /* nFields */ 4, 12249 /* *fields */ soc_ENQ_TO_INTFI_INFO_BCM56260_A0fmt_fields, 12250 /* bits */ 528, 12251 /* flags */ 0, 12252 }, 12253 #endif /* chips */ 12254 12255 #if defined(BCM_56260_B0) 12256 { /* SOC_FORMAT_INT_ENQ_TO_INTFI_INFO_BCM56260_B0fmt */ 12257 /* format ENQ_TO_INTFI_INFOfmt */ 12258 /* nFields */ 4, 12259 /* *fields */ soc_ENQ_TO_INTFI_INFO_BCM56260_A0fmt_fields, 12260 /* bits */ 528, 12261 /* flags */ 0, 12262 }, 12263 #endif /* chips */ 12264 12265 #if defined(BCM_56270_A0) 12266 { /* SOC_FORMAT_INT_ENQ_TO_INTFI_INFO_BCM56270_A0fmt */ 12267 /* format ENQ_TO_INTFI_INFOfmt */ 12268 /* nFields */ 4, 12269 /* *fields */ soc_ENQ_TO_INTFI_INFO_BCM56260_A0fmt_fields, 12270 /* bits */ 528, 12271 /* flags */ 0, 12272 }, 12273 #endif /* chips */ 12274 12275 #if defined(BCM_56440_B0) 12276 { /* SOC_FORMAT_INT_ENQ_TO_INTFI_INFO_BCM56440_B0fmt */ 12277 /* format ENQ_TO_INTFI_INFOfmt */ 12278 /* nFields */ 4, 12279 /* *fields */ soc_ENQ_TO_INTFI_INFOfmt_fields, 12280 /* bits */ 528, 12281 /* flags */ 0, 12282 }, 12283 #endif /* chips */ 12284 12285 #if defined(BCM_56450_A0) 12286 { /* SOC_FORMAT_INT_ENQ_TO_INTFI_INFO_BCM56450_A0fmt */ 12287 /* format ENQ_TO_INTFI_INFOfmt */ 12288 /* nFields */ 4, 12289 /* *fields */ soc_ENQ_TO_INTFI_INFO_BCM56450_A0fmt_fields, 12290 /* bits */ 528, 12291 /* flags */ 0, 12292 }, 12293 #endif /* chips */ 12294 12295 #if defined(BCM_56450_B0) 12296 { /* SOC_FORMAT_INT_ENQ_TO_INTFI_INFO_BCM56450_B0fmt */ 12297 /* format ENQ_TO_INTFI_INFOfmt */ 12298 /* nFields */ 4, 12299 /* *fields */ soc_ENQ_TO_INTFI_INFO_BCM56450_A0fmt_fields, 12300 /* bits */ 528, 12301 /* flags */ 0, 12302 }, 12303 #endif /* chips */ 12304 12305 #if defined(BCM_56450_B1) 12306 { /* SOC_FORMAT_INT_ENQ_TO_INTFI_INFO_BCM56450_B1fmt */ 12307 /* format ENQ_TO_INTFI_INFOfmt */ 12308 /* nFields */ 4, 12309 /* *fields */ soc_ENQ_TO_INTFI_INFO_BCM56450_A0fmt_fields, 12310 /* bits */ 528, 12311 /* flags */ 0, 12312 }, 12313 #endif /* chips */ 12314 12315 #if defined(BCM_56440_A0) 12316 { /* SOC_FORMAT_INT_ENQ_TO_ITE_CTRL_INFOfmt */ 12317 /* format ENQ_TO_ITE_CTRL_INFOfmt */ 12318 /* nFields */ 1, 12319 /* *fields */ soc_ENQ_EXT_PTRfmt_fields, 12320 /* bits */ 18, 12321 /* flags */ 0, 12322 }, 12323 #endif /* chips */ 12324 12325 #if defined(BCM_56440_B0) 12326 { /* SOC_FORMAT_INT_ENQ_TO_ITE_CTRL_INFO_BCM56440_B0fmt */ 12327 /* format ENQ_TO_ITE_CTRL_INFOfmt */ 12328 /* nFields */ 1, 12329 /* *fields */ soc_ENQ_EXT_PTRfmt_fields, 12330 /* bits */ 18, 12331 /* flags */ 0, 12332 }, 12333 #endif /* chips */ 12334 12335 #if defined(BCM_56450_A0) 12336 { /* SOC_FORMAT_INT_ENQ_TO_ITE_CTRL_INFO_BCM56450_A0fmt */ 12337 /* format ENQ_TO_ITE_CTRL_INFOfmt */ 12338 /* nFields */ 1, 12339 /* *fields */ soc_ENQ_EXT_PTR_BCM56450_A0fmt_fields, 12340 /* bits */ 18, 12341 /* flags */ 0, 12342 }, 12343 #endif /* chips */ 12344 12345 #if defined(BCM_56450_B0) 12346 { /* SOC_FORMAT_INT_ENQ_TO_ITE_CTRL_INFO_BCM56450_B0fmt */ 12347 /* format ENQ_TO_ITE_CTRL_INFOfmt */ 12348 /* nFields */ 1, 12349 /* *fields */ soc_ENQ_EXT_PTR_BCM56450_A0fmt_fields, 12350 /* bits */ 18, 12351 /* flags */ 0, 12352 }, 12353 #endif /* chips */ 12354 12355 #if defined(BCM_56450_B1) 12356 { /* SOC_FORMAT_INT_ENQ_TO_ITE_CTRL_INFO_BCM56450_B1fmt */ 12357 /* format ENQ_TO_ITE_CTRL_INFOfmt */ 12358 /* nFields */ 1, 12359 /* *fields */ soc_ENQ_EXT_PTR_BCM56450_A0fmt_fields, 12360 /* bits */ 18, 12361 /* flags */ 0, 12362 }, 12363 #endif /* chips */ 12364 12365 #if defined(BCM_56440_A0) 12366 { /* SOC_FORMAT_INT_ENQ_TO_ITE_EMA_INFOfmt */ 12367 /* format ENQ_TO_ITE_EMA_INFOfmt */ 12368 /* nFields */ 24, 12369 /* *fields */ soc_ENQ_TO_ITE_EMA_INFOfmt_fields, 12370 /* bits */ 108, 12371 /* flags */ 0, 12372 }, 12373 #endif /* chips */ 12374 12375 #if defined(BCM_56260_A0) 12376 { /* SOC_FORMAT_INT_ENQ_TO_ITE_EMA_INFO_BCM56260_A0fmt */ 12377 /* format ENQ_TO_ITE_EMA_INFOfmt */ 12378 /* nFields */ 26, 12379 /* *fields */ soc_ENQ_TO_ITE_EMA_INFO_BCM56260_A0fmt_fields, 12380 /* bits */ 117, 12381 /* flags */ 0, 12382 }, 12383 #endif /* chips */ 12384 12385 #if defined(BCM_56260_B0) 12386 { /* SOC_FORMAT_INT_ENQ_TO_ITE_EMA_INFO_BCM56260_B0fmt */ 12387 /* format ENQ_TO_ITE_EMA_INFOfmt */ 12388 /* nFields */ 26, 12389 /* *fields */ soc_ENQ_TO_ITE_EMA_INFO_BCM56260_A0fmt_fields, 12390 /* bits */ 117, 12391 /* flags */ 0, 12392 }, 12393 #endif /* chips */ 12394 12395 #if defined(BCM_56440_B0) 12396 { /* SOC_FORMAT_INT_ENQ_TO_ITE_EMA_INFO_BCM56440_B0fmt */ 12397 /* format ENQ_TO_ITE_EMA_INFOfmt */ 12398 /* nFields */ 24, 12399 /* *fields */ soc_ENQ_TO_ITE_EMA_INFOfmt_fields, 12400 /* bits */ 108, 12401 /* flags */ 0, 12402 }, 12403 #endif /* chips */ 12404 12405 #if defined(BCM_56450_A0) 12406 { /* SOC_FORMAT_INT_ENQ_TO_ITE_EMA_INFO_BCM56450_A0fmt */ 12407 /* format ENQ_TO_ITE_EMA_INFOfmt */ 12408 /* nFields */ 25, 12409 /* *fields */ soc_ENQ_TO_ITE_EMA_INFO_BCM56450_A0fmt_fields, 12410 /* bits */ 125, 12411 /* flags */ 0, 12412 }, 12413 #endif /* chips */ 12414 12415 #if defined(BCM_56450_B0) 12416 { /* SOC_FORMAT_INT_ENQ_TO_ITE_EMA_INFO_BCM56450_B0fmt */ 12417 /* format ENQ_TO_ITE_EMA_INFOfmt */ 12418 /* nFields */ 25, 12419 /* *fields */ soc_ENQ_TO_ITE_EMA_INFO_BCM56450_A0fmt_fields, 12420 /* bits */ 125, 12421 /* flags */ 0, 12422 }, 12423 #endif /* chips */ 12424 12425 #if defined(BCM_56450_B1) 12426 { /* SOC_FORMAT_INT_ENQ_TO_ITE_EMA_INFO_BCM56450_B1fmt */ 12427 /* format ENQ_TO_ITE_EMA_INFOfmt */ 12428 /* nFields */ 25, 12429 /* *fields */ soc_ENQ_TO_ITE_EMA_INFO_BCM56450_A0fmt_fields, 12430 /* bits */ 125, 12431 /* flags */ 0, 12432 }, 12433 #endif /* chips */ 12434 12435 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) 12436 { /* SOC_FORMAT_INT_ENQ_TO_MTRI_INC_INFOfmt */ 12437 /* format ENQ_TO_MTRI_INC_INFOfmt */ 12438 /* nFields */ 4, 12439 /* *fields */ soc_ENQ_TO_MTRI_INC_INFOfmt_fields, 12440 /* bits */ 27, 12441 /* flags */ 0, 12442 }, 12443 #endif /* chips */ 12444 12445 #if defined(BCM_56260_A0) 12446 { /* SOC_FORMAT_INT_ENQ_TO_MTRI_INC_INFO_BCM56260_A0fmt */ 12447 /* format ENQ_TO_MTRI_INC_INFOfmt */ 12448 /* nFields */ 4, 12449 /* *fields */ soc_ENQ_TO_MTRI_INC_INFO_BCM56260_A0fmt_fields, 12450 /* bits */ 25, 12451 /* flags */ 0, 12452 }, 12453 #endif /* chips */ 12454 12455 #if defined(BCM_56260_B0) 12456 { /* SOC_FORMAT_INT_ENQ_TO_MTRI_INC_INFO_BCM56260_B0fmt */ 12457 /* format ENQ_TO_MTRI_INC_INFOfmt */ 12458 /* nFields */ 4, 12459 /* *fields */ soc_ENQ_TO_MTRI_INC_INFO_BCM56260_A0fmt_fields, 12460 /* bits */ 25, 12461 /* flags */ 0, 12462 }, 12463 #endif /* chips */ 12464 12465 #if defined(BCM_56270_A0) 12466 { /* SOC_FORMAT_INT_ENQ_TO_MTRI_INC_INFO_BCM56270_A0fmt */ 12467 /* format ENQ_TO_MTRI_INC_INFOfmt */ 12468 /* nFields */ 4, 12469 /* *fields */ soc_ENQ_TO_MTRI_INC_INFO_BCM56270_A0fmt_fields, 12470 /* bits */ 23, 12471 /* flags */ 0, 12472 }, 12473 #endif /* chips */ 12474 12475 #if defined(BCM_56450_A0) 12476 { /* SOC_FORMAT_INT_ENQ_TO_MTRI_INC_INFO_BCM56450_A0fmt */ 12477 /* format ENQ_TO_MTRI_INC_INFOfmt */ 12478 /* nFields */ 4, 12479 /* *fields */ soc_ENQ_TO_MTRI_INC_INFO_BCM56450_A0fmt_fields, 12480 /* bits */ 27, 12481 /* flags */ 0, 12482 }, 12483 #endif /* chips */ 12484 12485 #if defined(BCM_56450_B0) 12486 { /* SOC_FORMAT_INT_ENQ_TO_MTRI_INC_INFO_BCM56450_B0fmt */ 12487 /* format ENQ_TO_MTRI_INC_INFOfmt */ 12488 /* nFields */ 4, 12489 /* *fields */ soc_ENQ_TO_MTRI_INC_INFO_BCM56450_A0fmt_fields, 12490 /* bits */ 27, 12491 /* flags */ 0, 12492 }, 12493 #endif /* chips */ 12494 12495 #if defined(BCM_56450_B1) 12496 { /* SOC_FORMAT_INT_ENQ_TO_MTRI_INC_INFO_BCM56450_B1fmt */ 12497 /* format ENQ_TO_MTRI_INC_INFOfmt */ 12498 /* nFields */ 4, 12499 /* *fields */ soc_ENQ_TO_MTRI_INC_INFO_BCM56450_A0fmt_fields, 12500 /* bits */ 27, 12501 /* flags */ 0, 12502 }, 12503 #endif /* chips */ 12504 12505 #if defined(BCM_56524_B0) || defined(BCM_56634_A0) || \ 12506 defined(BCM_56634_B0) 12507 { /* SOC_FORMAT_INT_ENQ_TO_PQE_INFOfmt */ 12508 /* format ENQ_TO_PQE_INFOfmt */ 12509 /* nFields */ 22, 12510 /* *fields */ soc_ENQ_TO_PQE_INFOfmt_fields, 12511 /* bits */ 138, 12512 /* flags */ 0, 12513 }, 12514 #endif /* chips */ 12515 12516 #if defined(BCM_56340_A0) 12517 { /* SOC_FORMAT_INT_ENQ_TO_PQE_INFO_BCM56340_A0fmt */ 12518 /* format ENQ_TO_PQE_INFOfmt */ 12519 /* nFields */ 6, 12520 /* *fields */ soc_ENQ_TO_PQE_INFO_BCM56640_A0fmt_fields, 12521 /* bits */ 25, 12522 /* flags */ 0, 12523 }, 12524 #endif /* chips */ 12525 12526 #if defined(BCM_56440_A0) 12527 { /* SOC_FORMAT_INT_ENQ_TO_PQE_INFO_BCM56440_A0fmt */ 12528 /* format ENQ_TO_PQE_INFOfmt */ 12529 /* nFields */ 25, 12530 /* *fields */ soc_ENQ_TO_PQE_INFO_BCM56840_A0fmt_fields, 12531 /* bits */ 169, 12532 /* flags */ 0, 12533 }, 12534 #endif /* chips */ 12535 12536 #if defined(BCM_56440_B0) 12537 { /* SOC_FORMAT_INT_ENQ_TO_PQE_INFO_BCM56440_B0fmt */ 12538 /* format ENQ_TO_PQE_INFOfmt */ 12539 /* nFields */ 25, 12540 /* *fields */ soc_ENQ_TO_PQE_INFO_BCM56840_A0fmt_fields, 12541 /* bits */ 169, 12542 /* flags */ 0, 12543 }, 12544 #endif /* chips */ 12545 12546 #if defined(BCM_56450_A0) 12547 { /* SOC_FORMAT_INT_ENQ_TO_PQE_INFO_BCM56450_A0fmt */ 12548 /* format ENQ_TO_PQE_INFOfmt */ 12549 /* nFields */ 25, 12550 /* *fields */ soc_ENQ_TO_PQE_INFO_BCM56450_A0fmt_fields, 12551 /* bits */ 169, 12552 /* flags */ 0, 12553 }, 12554 #endif /* chips */ 12555 12556 #if defined(BCM_56450_B0) 12557 { /* SOC_FORMAT_INT_ENQ_TO_PQE_INFO_BCM56450_B0fmt */ 12558 /* format ENQ_TO_PQE_INFOfmt */ 12559 /* nFields */ 25, 12560 /* *fields */ soc_ENQ_TO_PQE_INFO_BCM56450_A0fmt_fields, 12561 /* bits */ 169, 12562 /* flags */ 0, 12563 }, 12564 #endif /* chips */ 12565 12566 #if defined(BCM_56450_B1) 12567 { /* SOC_FORMAT_INT_ENQ_TO_PQE_INFO_BCM56450_B1fmt */ 12568 /* format ENQ_TO_PQE_INFOfmt */ 12569 /* nFields */ 25, 12570 /* *fields */ soc_ENQ_TO_PQE_INFO_BCM56450_A0fmt_fields, 12571 /* bits */ 169, 12572 /* flags */ 0, 12573 }, 12574 #endif /* chips */ 12575 12576 #if defined(BCM_56524_A0) 12577 { /* SOC_FORMAT_INT_ENQ_TO_PQE_INFO_BCM56524_A0fmt */ 12578 /* format ENQ_TO_PQE_INFOfmt */ 12579 /* nFields */ 22, 12580 /* *fields */ soc_ENQ_TO_PQE_INFOfmt_fields, 12581 /* bits */ 138, 12582 /* flags */ 0, 12583 }, 12584 #endif /* chips */ 12585 12586 #if defined(BCM_56560_A0) 12587 { /* SOC_FORMAT_INT_ENQ_TO_PQE_INFO_BCM56560_A0fmt */ 12588 /* format ENQ_TO_PQE_INFOfmt */ 12589 /* nFields */ 7, 12590 /* *fields */ soc_ENQ_TO_PQE_INFO_BCM56560_A0fmt_fields, 12591 /* bits */ 28, 12592 /* flags */ 0, 12593 }, 12594 #endif /* chips */ 12595 12596 #if defined(BCM_56560_B0) 12597 { /* SOC_FORMAT_INT_ENQ_TO_PQE_INFO_BCM56560_B0fmt */ 12598 /* format ENQ_TO_PQE_INFOfmt */ 12599 /* nFields */ 7, 12600 /* *fields */ soc_ENQ_TO_PQE_INFO_BCM56560_A0fmt_fields, 12601 /* bits */ 28, 12602 /* flags */ 0, 12603 }, 12604 #endif /* chips */ 12605 12606 #if defined(BCM_56640_A0) 12607 { /* SOC_FORMAT_INT_ENQ_TO_PQE_INFO_BCM56640_A0fmt */ 12608 /* format ENQ_TO_PQE_INFOfmt */ 12609 /* nFields */ 6, 12610 /* *fields */ soc_ENQ_TO_PQE_INFO_BCM56640_A0fmt_fields, 12611 /* bits */ 25, 12612 /* flags */ 0, 12613 }, 12614 #endif /* chips */ 12615 12616 #if defined(BCM_56670_A0) 12617 { /* SOC_FORMAT_INT_ENQ_TO_PQE_INFO_BCM56670_A0fmt */ 12618 /* format ENQ_TO_PQE_INFOfmt */ 12619 /* nFields */ 7, 12620 /* *fields */ soc_ENQ_TO_PQE_INFO_BCM56670_A0fmt_fields, 12621 /* bits */ 28, 12622 /* flags */ 0, 12623 }, 12624 #endif /* chips */ 12625 12626 #if defined(BCM_56670_B0) 12627 { /* SOC_FORMAT_INT_ENQ_TO_PQE_INFO_BCM56670_B0fmt */ 12628 /* format ENQ_TO_PQE_INFOfmt */ 12629 /* nFields */ 7, 12630 /* *fields */ soc_ENQ_TO_PQE_INFO_BCM56670_A0fmt_fields, 12631 /* bits */ 28, 12632 /* flags */ 0, 12633 }, 12634 #endif /* chips */ 12635 12636 #if defined(BCM_56685_A0) 12637 { /* SOC_FORMAT_INT_ENQ_TO_PQE_INFO_BCM56685_A0fmt */ 12638 /* format ENQ_TO_PQE_INFOfmt */ 12639 /* nFields */ 22, 12640 /* *fields */ soc_ENQ_TO_PQE_INFOfmt_fields, 12641 /* bits */ 138, 12642 /* flags */ 0, 12643 }, 12644 #endif /* chips */ 12645 12646 #if defined(BCM_56685_B0) 12647 { /* SOC_FORMAT_INT_ENQ_TO_PQE_INFO_BCM56685_B0fmt */ 12648 /* format ENQ_TO_PQE_INFOfmt */ 12649 /* nFields */ 22, 12650 /* *fields */ soc_ENQ_TO_PQE_INFOfmt_fields, 12651 /* bits */ 138, 12652 /* flags */ 0, 12653 }, 12654 #endif /* chips */ 12655 12656 #if defined(BCM_56840_A0) 12657 { /* SOC_FORMAT_INT_ENQ_TO_PQE_INFO_BCM56840_A0fmt */ 12658 /* format ENQ_TO_PQE_INFOfmt */ 12659 /* nFields */ 25, 12660 /* *fields */ soc_ENQ_TO_PQE_INFO_BCM56840_A0fmt_fields, 12661 /* bits */ 169, 12662 /* flags */ 0, 12663 }, 12664 #endif /* chips */ 12665 12666 #if defined(BCM_56840_B0) 12667 { /* SOC_FORMAT_INT_ENQ_TO_PQE_INFO_BCM56840_B0fmt */ 12668 /* format ENQ_TO_PQE_INFOfmt */ 12669 /* nFields */ 25, 12670 /* *fields */ soc_ENQ_TO_PQE_INFO_BCM56840_A0fmt_fields, 12671 /* bits */ 169, 12672 /* flags */ 0, 12673 }, 12674 #endif /* chips */ 12675 12676 #if defined(BCM_56850_A0) 12677 { /* SOC_FORMAT_INT_ENQ_TO_PQE_INFO_BCM56850_A0fmt */ 12678 /* format ENQ_TO_PQE_INFOfmt */ 12679 /* nFields */ 7, 12680 /* *fields */ soc_ENQ_TO_PQE_INFO_BCM56850_A0fmt_fields, 12681 /* bits */ 28, 12682 /* flags */ 0, 12683 }, 12684 #endif /* chips */ 12685 12686 #if defined(BCM_56860_A0) 12687 { /* SOC_FORMAT_INT_ENQ_TO_PQE_INFO_BCM56860_A0fmt */ 12688 /* format ENQ_TO_PQE_INFOfmt */ 12689 /* nFields */ 7, 12690 /* *fields */ soc_ENQ_TO_PQE_INFO_BCM56850_A0fmt_fields, 12691 /* bits */ 28, 12692 /* flags */ 0, 12693 }, 12694 #endif /* chips */ 12695 12696 #if defined(BCM_56840_A0) 12697 { /* SOC_FORMAT_INT_ENQ_TO_QCN_INFOfmt */ 12698 /* format ENQ_TO_QCN_INFOfmt */ 12699 /* nFields */ 12, 12700 /* *fields */ soc_ENQ_TO_QCN_INFOfmt_fields, 12701 /* bits */ 55, 12702 /* flags */ 0, 12703 }, 12704 #endif /* chips */ 12705 12706 #if defined(BCM_56340_A0) 12707 { /* SOC_FORMAT_INT_ENQ_TO_QCN_INFO_BCM56340_A0fmt */ 12708 /* format ENQ_TO_QCN_INFOfmt */ 12709 /* nFields */ 10, 12710 /* *fields */ soc_ENQ_TO_QCN_INFO_BCM56640_A0fmt_fields, 12711 /* bits */ 50, 12712 /* flags */ 0, 12713 }, 12714 #endif /* chips */ 12715 12716 #if defined(BCM_56440_A0) 12717 { /* SOC_FORMAT_INT_ENQ_TO_QCN_INFO_BCM56440_A0fmt */ 12718 /* format ENQ_TO_QCN_INFOfmt */ 12719 /* nFields */ 12, 12720 /* *fields */ soc_ENQ_TO_QCN_INFOfmt_fields, 12721 /* bits */ 55, 12722 /* flags */ 0, 12723 }, 12724 #endif /* chips */ 12725 12726 #if defined(BCM_56440_B0) 12727 { /* SOC_FORMAT_INT_ENQ_TO_QCN_INFO_BCM56440_B0fmt */ 12728 /* format ENQ_TO_QCN_INFOfmt */ 12729 /* nFields */ 12, 12730 /* *fields */ soc_ENQ_TO_QCN_INFOfmt_fields, 12731 /* bits */ 55, 12732 /* flags */ 0, 12733 }, 12734 #endif /* chips */ 12735 12736 #if defined(BCM_56450_A0) 12737 { /* SOC_FORMAT_INT_ENQ_TO_QCN_INFO_BCM56450_A0fmt */ 12738 /* format ENQ_TO_QCN_INFOfmt */ 12739 /* nFields */ 12, 12740 /* *fields */ soc_ENQ_TO_QCN_INFO_BCM56450_A0fmt_fields, 12741 /* bits */ 55, 12742 /* flags */ 0, 12743 }, 12744 #endif /* chips */ 12745 12746 #if defined(BCM_56450_B0) 12747 { /* SOC_FORMAT_INT_ENQ_TO_QCN_INFO_BCM56450_B0fmt */ 12748 /* format ENQ_TO_QCN_INFOfmt */ 12749 /* nFields */ 12, 12750 /* *fields */ soc_ENQ_TO_QCN_INFO_BCM56450_A0fmt_fields, 12751 /* bits */ 55, 12752 /* flags */ 0, 12753 }, 12754 #endif /* chips */ 12755 12756 #if defined(BCM_56450_B1) 12757 { /* SOC_FORMAT_INT_ENQ_TO_QCN_INFO_BCM56450_B1fmt */ 12758 /* format ENQ_TO_QCN_INFOfmt */ 12759 /* nFields */ 12, 12760 /* *fields */ soc_ENQ_TO_QCN_INFO_BCM56450_A0fmt_fields, 12761 /* bits */ 55, 12762 /* flags */ 0, 12763 }, 12764 #endif /* chips */ 12765 12766 #if defined(BCM_56560_A0) 12767 { /* SOC_FORMAT_INT_ENQ_TO_QCN_INFO_BCM56560_A0fmt */ 12768 /* format ENQ_TO_QCN_INFOfmt */ 12769 /* nFields */ 10, 12770 /* *fields */ soc_ENQ_TO_QCN_INFO_BCM56560_A0fmt_fields, 12771 /* bits */ 57, 12772 /* flags */ 0, 12773 }, 12774 #endif /* chips */ 12775 12776 #if defined(BCM_56560_B0) 12777 { /* SOC_FORMAT_INT_ENQ_TO_QCN_INFO_BCM56560_B0fmt */ 12778 /* format ENQ_TO_QCN_INFOfmt */ 12779 /* nFields */ 10, 12780 /* *fields */ soc_ENQ_TO_QCN_INFO_BCM56560_A0fmt_fields, 12781 /* bits */ 57, 12782 /* flags */ 0, 12783 }, 12784 #endif /* chips */ 12785 12786 #if defined(BCM_56640_A0) 12787 { /* SOC_FORMAT_INT_ENQ_TO_QCN_INFO_BCM56640_A0fmt */ 12788 /* format ENQ_TO_QCN_INFOfmt */ 12789 /* nFields */ 10, 12790 /* *fields */ soc_ENQ_TO_QCN_INFO_BCM56640_A0fmt_fields, 12791 /* bits */ 50, 12792 /* flags */ 0, 12793 }, 12794 #endif /* chips */ 12795 12796 #if defined(BCM_56670_A0) 12797 { /* SOC_FORMAT_INT_ENQ_TO_QCN_INFO_BCM56670_A0fmt */ 12798 /* format ENQ_TO_QCN_INFOfmt */ 12799 /* nFields */ 10, 12800 /* *fields */ soc_ENQ_TO_QCN_INFO_BCM56670_A0fmt_fields, 12801 /* bits */ 52, 12802 /* flags */ 0, 12803 }, 12804 #endif /* chips */ 12805 12806 #if defined(BCM_56670_B0) 12807 { /* SOC_FORMAT_INT_ENQ_TO_QCN_INFO_BCM56670_B0fmt */ 12808 /* format ENQ_TO_QCN_INFOfmt */ 12809 /* nFields */ 10, 12810 /* *fields */ soc_ENQ_TO_QCN_INFO_BCM56670_A0fmt_fields, 12811 /* bits */ 52, 12812 /* flags */ 0, 12813 }, 12814 #endif /* chips */ 12815 12816 #if defined(BCM_56840_B0) 12817 { /* SOC_FORMAT_INT_ENQ_TO_QCN_INFO_BCM56840_B0fmt */ 12818 /* format ENQ_TO_QCN_INFOfmt */ 12819 /* nFields */ 12, 12820 /* *fields */ soc_ENQ_TO_QCN_INFOfmt_fields, 12821 /* bits */ 55, 12822 /* flags */ 0, 12823 }, 12824 #endif /* chips */ 12825 12826 #if defined(BCM_56850_A0) 12827 { /* SOC_FORMAT_INT_ENQ_TO_QCN_INFO_BCM56850_A0fmt */ 12828 /* format ENQ_TO_QCN_INFOfmt */ 12829 /* nFields */ 10, 12830 /* *fields */ soc_ENQ_TO_QCN_INFO_BCM56850_A0fmt_fields, 12831 /* bits */ 56, 12832 /* flags */ 0, 12833 }, 12834 #endif /* chips */ 12835 12836 #if defined(BCM_56860_A0) 12837 { /* SOC_FORMAT_INT_ENQ_TO_QCN_INFO_BCM56860_A0fmt */ 12838 /* format ENQ_TO_QCN_INFOfmt */ 12839 /* nFields */ 10, 12840 /* *fields */ soc_ENQ_TO_QCN_INFO_BCM56850_A0fmt_fields, 12841 /* bits */ 56, 12842 /* flags */ 0, 12843 }, 12844 #endif /* chips */ 12845 12846 #if defined(BCM_56670_A0) || defined(BCM_56670_B0) 12847 { /* SOC_FORMAT_INT_ENQ_TO_RQE_INFOfmt */ 12848 /* format ENQ_TO_RQE_INFOfmt */ 12849 /* nFields */ 15, 12850 /* *fields */ soc_ENQ_TO_RQE_INFOfmt_fields, 12851 /* bits */ 223, 12852 /* flags */ 0, 12853 }, 12854 #endif /* chips */ 12855 12856 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) 12857 { /* SOC_FORMAT_INT_ENQ_TO_RQE_INT_INFOfmt */ 12858 /* format ENQ_TO_RQE_INT_INFOfmt */ 12859 /* nFields */ 3, 12860 /* *fields */ soc_ENQ_TO_RQE_INT_INFOfmt_fields, 12861 /* bits */ 29, 12862 /* flags */ 0, 12863 }, 12864 #endif /* chips */ 12865 12866 #if defined(BCM_56260_A0) 12867 { /* SOC_FORMAT_INT_ENQ_TO_RQE_INT_INFO_BCM56260_A0fmt */ 12868 /* format ENQ_TO_RQE_INT_INFOfmt */ 12869 /* nFields */ 3, 12870 /* *fields */ soc_ENQ_TO_RQE_INT_INFO_BCM56260_A0fmt_fields, 12871 /* bits */ 28, 12872 /* flags */ 0, 12873 }, 12874 #endif /* chips */ 12875 12876 #if defined(BCM_56260_B0) 12877 { /* SOC_FORMAT_INT_ENQ_TO_RQE_INT_INFO_BCM56260_B0fmt */ 12878 /* format ENQ_TO_RQE_INT_INFOfmt */ 12879 /* nFields */ 3, 12880 /* *fields */ soc_ENQ_TO_RQE_INT_INFO_BCM56260_A0fmt_fields, 12881 /* bits */ 28, 12882 /* flags */ 0, 12883 }, 12884 #endif /* chips */ 12885 12886 #if defined(BCM_56270_A0) 12887 { /* SOC_FORMAT_INT_ENQ_TO_RQE_INT_INFO_BCM56270_A0fmt */ 12888 /* format ENQ_TO_RQE_INT_INFOfmt */ 12889 /* nFields */ 3, 12890 /* *fields */ soc_ENQ_TO_RQE_INT_INFO_BCM56270_A0fmt_fields, 12891 /* bits */ 25, 12892 /* flags */ 0, 12893 }, 12894 #endif /* chips */ 12895 12896 #if defined(BCM_56450_A0) 12897 { /* SOC_FORMAT_INT_ENQ_TO_RQE_INT_INFO_BCM56450_A0fmt */ 12898 /* format ENQ_TO_RQE_INT_INFOfmt */ 12899 /* nFields */ 3, 12900 /* *fields */ soc_ENQ_TO_RQE_INT_INFO_BCM56450_A0fmt_fields, 12901 /* bits */ 29, 12902 /* flags */ 0, 12903 }, 12904 #endif /* chips */ 12905 12906 #if defined(BCM_56450_B0) 12907 { /* SOC_FORMAT_INT_ENQ_TO_RQE_INT_INFO_BCM56450_B0fmt */ 12908 /* format ENQ_TO_RQE_INT_INFOfmt */ 12909 /* nFields */ 3, 12910 /* *fields */ soc_ENQ_TO_RQE_INT_INFO_BCM56450_A0fmt_fields, 12911 /* bits */ 29, 12912 /* flags */ 0, 12913 }, 12914 #endif /* chips */ 12915 12916 #if defined(BCM_56450_B1) 12917 { /* SOC_FORMAT_INT_ENQ_TO_RQE_INT_INFO_BCM56450_B1fmt */ 12918 /* format ENQ_TO_RQE_INT_INFOfmt */ 12919 /* nFields */ 3, 12920 /* *fields */ soc_ENQ_TO_RQE_INT_INFO_BCM56450_A0fmt_fields, 12921 /* bits */ 29, 12922 /* flags */ 0, 12923 }, 12924 #endif /* chips */ 12925 12926 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) 12927 { /* SOC_FORMAT_INT_ENQ_TO_RQE_RDDATA_INFOfmt */ 12928 /* format ENQ_TO_RQE_RDDATA_INFOfmt */ 12929 /* nFields */ 29, 12930 /* *fields */ soc_ENQ_TO_RQE_RDDATA_INFOfmt_fields, 12931 /* bits */ 200, 12932 /* flags */ 0, 12933 }, 12934 #endif /* chips */ 12935 12936 #if defined(BCM_56260_A0) 12937 { /* SOC_FORMAT_INT_ENQ_TO_RQE_RDDATA_INFO_BCM56260_A0fmt */ 12938 /* format ENQ_TO_RQE_RDDATA_INFOfmt */ 12939 /* nFields */ 36, 12940 /* *fields */ soc_ENQ_TO_RQE_RDDATA_INFO_BCM56260_A0fmt_fields, 12941 /* bits */ 343, 12942 /* flags */ 0, 12943 }, 12944 #endif /* chips */ 12945 12946 #if defined(BCM_56260_B0) 12947 { /* SOC_FORMAT_INT_ENQ_TO_RQE_RDDATA_INFO_BCM56260_B0fmt */ 12948 /* format ENQ_TO_RQE_RDDATA_INFOfmt */ 12949 /* nFields */ 36, 12950 /* *fields */ soc_ENQ_TO_RQE_RDDATA_INFO_BCM56260_A0fmt_fields, 12951 /* bits */ 343, 12952 /* flags */ 0, 12953 }, 12954 #endif /* chips */ 12955 12956 #if defined(BCM_56270_A0) 12957 { /* SOC_FORMAT_INT_ENQ_TO_RQE_RDDATA_INFO_BCM56270_A0fmt */ 12958 /* format ENQ_TO_RQE_RDDATA_INFOfmt */ 12959 /* nFields */ 33, 12960 /* *fields */ soc_ENQ_TO_RQE_RDDATA_INFO_BCM56270_A0fmt_fields, 12961 /* bits */ 186, 12962 /* flags */ 0, 12963 }, 12964 #endif /* chips */ 12965 12966 #if defined(BCM_56450_A0) 12967 { /* SOC_FORMAT_INT_ENQ_TO_RQE_RDDATA_INFO_BCM56450_A0fmt */ 12968 /* format ENQ_TO_RQE_RDDATA_INFOfmt */ 12969 /* nFields */ 36, 12970 /* *fields */ soc_ENQ_TO_RQE_RDDATA_INFO_BCM56450_A0fmt_fields, 12971 /* bits */ 505, 12972 /* flags */ 0, 12973 }, 12974 #endif /* chips */ 12975 12976 #if defined(BCM_56450_B0) 12977 { /* SOC_FORMAT_INT_ENQ_TO_RQE_RDDATA_INFO_BCM56450_B0fmt */ 12978 /* format ENQ_TO_RQE_RDDATA_INFOfmt */ 12979 /* nFields */ 36, 12980 /* *fields */ soc_ENQ_TO_RQE_RDDATA_INFO_BCM56450_A0fmt_fields, 12981 /* bits */ 505, 12982 /* flags */ 0, 12983 }, 12984 #endif /* chips */ 12985 12986 #if defined(BCM_56450_B1) 12987 { /* SOC_FORMAT_INT_ENQ_TO_RQE_RDDATA_INFO_BCM56450_B1fmt */ 12988 /* format ENQ_TO_RQE_RDDATA_INFOfmt */ 12989 /* nFields */ 36, 12990 /* *fields */ soc_ENQ_TO_RQE_RDDATA_INFO_BCM56450_A0fmt_fields, 12991 /* bits */ 505, 12992 /* flags */ 0, 12993 }, 12994 #endif /* chips */ 12995 12996 #if defined(BCM_56440_A0) 12997 { /* SOC_FORMAT_INT_ENQ_TO_RQE_UC_INFOfmt */ 12998 /* format ENQ_TO_RQE_UC_INFOfmt */ 12999 /* nFields */ 8, 13000 /* *fields */ soc_ENQ_TO_RQE_UC_INFOfmt_fields, 13001 /* bits */ 26, 13002 /* flags */ 0, 13003 }, 13004 #endif /* chips */ 13005 13006 #if defined(BCM_56260_A0) 13007 { /* SOC_FORMAT_INT_ENQ_TO_RQE_UC_INFO_BCM56260_A0fmt */ 13008 /* format ENQ_TO_RQE_UC_INFOfmt */ 13009 /* nFields */ 9, 13010 /* *fields */ soc_ENQ_TO_RQE_UC_INFO_BCM56260_A0fmt_fields, 13011 /* bits */ 31, 13012 /* flags */ 0, 13013 }, 13014 #endif /* chips */ 13015 13016 #if defined(BCM_56260_B0) 13017 { /* SOC_FORMAT_INT_ENQ_TO_RQE_UC_INFO_BCM56260_B0fmt */ 13018 /* format ENQ_TO_RQE_UC_INFOfmt */ 13019 /* nFields */ 9, 13020 /* *fields */ soc_ENQ_TO_RQE_UC_INFO_BCM56260_A0fmt_fields, 13021 /* bits */ 31, 13022 /* flags */ 0, 13023 }, 13024 #endif /* chips */ 13025 13026 #if defined(BCM_56270_A0) 13027 { /* SOC_FORMAT_INT_ENQ_TO_RQE_UC_INFO_BCM56270_A0fmt */ 13028 /* format ENQ_TO_RQE_UC_INFOfmt */ 13029 /* nFields */ 8, 13030 /* *fields */ soc_ENQ_TO_RQE_UC_INFO_BCM56270_A0fmt_fields, 13031 /* bits */ 29, 13032 /* flags */ 0, 13033 }, 13034 #endif /* chips */ 13035 13036 #if defined(BCM_56440_B0) 13037 { /* SOC_FORMAT_INT_ENQ_TO_RQE_UC_INFO_BCM56440_B0fmt */ 13038 /* format ENQ_TO_RQE_UC_INFOfmt */ 13039 /* nFields */ 8, 13040 /* *fields */ soc_ENQ_TO_RQE_UC_INFOfmt_fields, 13041 /* bits */ 26, 13042 /* flags */ 0, 13043 }, 13044 #endif /* chips */ 13045 13046 #if defined(BCM_56450_A0) 13047 { /* SOC_FORMAT_INT_ENQ_TO_RQE_UC_INFO_BCM56450_A0fmt */ 13048 /* format ENQ_TO_RQE_UC_INFOfmt */ 13049 /* nFields */ 9, 13050 /* *fields */ soc_ENQ_TO_RQE_UC_INFO_BCM56450_A0fmt_fields, 13051 /* bits */ 36, 13052 /* flags */ 0, 13053 }, 13054 #endif /* chips */ 13055 13056 #if defined(BCM_56450_B0) 13057 { /* SOC_FORMAT_INT_ENQ_TO_RQE_UC_INFO_BCM56450_B0fmt */ 13058 /* format ENQ_TO_RQE_UC_INFOfmt */ 13059 /* nFields */ 9, 13060 /* *fields */ soc_ENQ_TO_RQE_UC_INFO_BCM56450_A0fmt_fields, 13061 /* bits */ 36, 13062 /* flags */ 0, 13063 }, 13064 #endif /* chips */ 13065 13066 #if defined(BCM_56450_B1) 13067 { /* SOC_FORMAT_INT_ENQ_TO_RQE_UC_INFO_BCM56450_B1fmt */ 13068 /* format ENQ_TO_RQE_UC_INFOfmt */ 13069 /* nFields */ 9, 13070 /* *fields */ soc_ENQ_TO_RQE_UC_INFO_BCM56450_A0fmt_fields, 13071 /* bits */ 36, 13072 /* flags */ 0, 13073 }, 13074 #endif /* chips */ 13075 13076 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) 13077 { /* SOC_FORMAT_INT_ENQ_TO_THDI_EMA_INFOfmt */ 13078 /* format ENQ_TO_THDI_EMA_INFOfmt */ 13079 /* nFields */ 3, 13080 /* *fields */ soc_ENQ_TO_THDI_EMA_INFOfmt_fields, 13081 /* bits */ 9, 13082 /* flags */ 0, 13083 }, 13084 #endif /* chips */ 13085 13086 #if defined(BCM_56260_A0) 13087 { /* SOC_FORMAT_INT_ENQ_TO_THDI_EMA_INFO_BCM56260_A0fmt */ 13088 /* format ENQ_TO_THDI_EMA_INFOfmt */ 13089 /* nFields */ 3, 13090 /* *fields */ soc_ENQ_TO_THDI_EMA_INFO_BCM56260_A0fmt_fields, 13091 /* bits */ 9, 13092 /* flags */ 0, 13093 }, 13094 #endif /* chips */ 13095 13096 #if defined(BCM_56260_B0) 13097 { /* SOC_FORMAT_INT_ENQ_TO_THDI_EMA_INFO_BCM56260_B0fmt */ 13098 /* format ENQ_TO_THDI_EMA_INFOfmt */ 13099 /* nFields */ 3, 13100 /* *fields */ soc_ENQ_TO_THDI_EMA_INFO_BCM56260_A0fmt_fields, 13101 /* bits */ 9, 13102 /* flags */ 0, 13103 }, 13104 #endif /* chips */ 13105 13106 #if defined(BCM_56270_A0) 13107 { /* SOC_FORMAT_INT_ENQ_TO_THDI_EMA_INFO_BCM56270_A0fmt */ 13108 /* format ENQ_TO_THDI_EMA_INFOfmt */ 13109 /* nFields */ 3, 13110 /* *fields */ soc_ENQ_TO_THDI_EMA_INFO_BCM56260_A0fmt_fields, 13111 /* bits */ 9, 13112 /* flags */ 0, 13113 }, 13114 #endif /* chips */ 13115 13116 #if defined(BCM_56450_A0) 13117 { /* SOC_FORMAT_INT_ENQ_TO_THDI_EMA_INFO_BCM56450_A0fmt */ 13118 /* format ENQ_TO_THDI_EMA_INFOfmt */ 13119 /* nFields */ 3, 13120 /* *fields */ soc_ENQ_TO_THDI_EMA_INFO_BCM56450_A0fmt_fields, 13121 /* bits */ 9, 13122 /* flags */ 0, 13123 }, 13124 #endif /* chips */ 13125 13126 #if defined(BCM_56450_B0) 13127 { /* SOC_FORMAT_INT_ENQ_TO_THDI_EMA_INFO_BCM56450_B0fmt */ 13128 /* format ENQ_TO_THDI_EMA_INFOfmt */ 13129 /* nFields */ 3, 13130 /* *fields */ soc_ENQ_TO_THDI_EMA_INFO_BCM56450_A0fmt_fields, 13131 /* bits */ 9, 13132 /* flags */ 0, 13133 }, 13134 #endif /* chips */ 13135 13136 #if defined(BCM_56450_B1) 13137 { /* SOC_FORMAT_INT_ENQ_TO_THDI_EMA_INFO_BCM56450_B1fmt */ 13138 /* format ENQ_TO_THDI_EMA_INFOfmt */ 13139 /* nFields */ 3, 13140 /* *fields */ soc_ENQ_TO_THDI_EMA_INFO_BCM56450_A0fmt_fields, 13141 /* bits */ 9, 13142 /* flags */ 0, 13143 }, 13144 #endif /* chips */ 13145 13146 #if defined(BCM_56440_A0) 13147 { /* SOC_FORMAT_INT_ENQ_TO_THDI_EXT_INFOfmt */ 13148 /* format ENQ_TO_THDI_EXT_INFOfmt */ 13149 /* nFields */ 3, 13150 /* *fields */ soc_ENQ_TO_THDI_EMA_INFOfmt_fields, 13151 /* bits */ 9, 13152 /* flags */ 0, 13153 }, 13154 #endif /* chips */ 13155 13156 #if defined(BCM_56260_A0) 13157 { /* SOC_FORMAT_INT_ENQ_TO_THDI_EXT_INFO_BCM56260_A0fmt */ 13158 /* format ENQ_TO_THDI_EXT_INFOfmt */ 13159 /* nFields */ 5, 13160 /* *fields */ soc_ENQ_TO_THDI_EXT_INFO_BCM56260_A0fmt_fields, 13161 /* bits */ 10, 13162 /* flags */ 0, 13163 }, 13164 #endif /* chips */ 13165 13166 #if defined(BCM_56260_B0) 13167 { /* SOC_FORMAT_INT_ENQ_TO_THDI_EXT_INFO_BCM56260_B0fmt */ 13168 /* format ENQ_TO_THDI_EXT_INFOfmt */ 13169 /* nFields */ 5, 13170 /* *fields */ soc_ENQ_TO_THDI_EXT_INFO_BCM56260_A0fmt_fields, 13171 /* bits */ 10, 13172 /* flags */ 0, 13173 }, 13174 #endif /* chips */ 13175 13176 #if defined(BCM_56270_A0) 13177 { /* SOC_FORMAT_INT_ENQ_TO_THDI_EXT_INFO_BCM56270_A0fmt */ 13178 /* format ENQ_TO_THDI_EXT_INFOfmt */ 13179 /* nFields */ 5, 13180 /* *fields */ soc_ENQ_TO_THDI_EXT_INFO_BCM56260_A0fmt_fields, 13181 /* bits */ 10, 13182 /* flags */ 0, 13183 }, 13184 #endif /* chips */ 13185 13186 #if defined(BCM_56440_B0) 13187 { /* SOC_FORMAT_INT_ENQ_TO_THDI_EXT_INFO_BCM56440_B0fmt */ 13188 /* format ENQ_TO_THDI_EXT_INFOfmt */ 13189 /* nFields */ 3, 13190 /* *fields */ soc_ENQ_TO_THDI_EMA_INFOfmt_fields, 13191 /* bits */ 9, 13192 /* flags */ 0, 13193 }, 13194 #endif /* chips */ 13195 13196 #if defined(BCM_56450_A0) 13197 { /* SOC_FORMAT_INT_ENQ_TO_THDI_EXT_INFO_BCM56450_A0fmt */ 13198 /* format ENQ_TO_THDI_EXT_INFOfmt */ 13199 /* nFields */ 5, 13200 /* *fields */ soc_ENQ_TO_THDI_EXT_INFOfmt_fields, 13201 /* bits */ 11, 13202 /* flags */ 0, 13203 }, 13204 #endif /* chips */ 13205 13206 #if defined(BCM_56450_B0) 13207 { /* SOC_FORMAT_INT_ENQ_TO_THDI_EXT_INFO_BCM56450_B0fmt */ 13208 /* format ENQ_TO_THDI_EXT_INFOfmt */ 13209 /* nFields */ 5, 13210 /* *fields */ soc_ENQ_TO_THDI_EXT_INFOfmt_fields, 13211 /* bits */ 11, 13212 /* flags */ 0, 13213 }, 13214 #endif /* chips */ 13215 13216 #if defined(BCM_56450_B1) 13217 { /* SOC_FORMAT_INT_ENQ_TO_THDI_EXT_INFO_BCM56450_B1fmt */ 13218 /* format ENQ_TO_THDI_EXT_INFOfmt */ 13219 /* nFields */ 5, 13220 /* *fields */ soc_ENQ_TO_THDI_EXT_INFOfmt_fields, 13221 /* bits */ 11, 13222 /* flags */ 0, 13223 }, 13224 #endif /* chips */ 13225 13226 #if defined(BCM_56440_A0) 13227 { /* SOC_FORMAT_INT_ENQ_TO_THDI_INT_INFOfmt */ 13228 /* format ENQ_TO_THDI_INT_INFOfmt */ 13229 /* nFields */ 3, 13230 /* *fields */ soc_ENQ_TO_THDI_EMA_INFOfmt_fields, 13231 /* bits */ 9, 13232 /* flags */ 0, 13233 }, 13234 #endif /* chips */ 13235 13236 #if defined(BCM_56260_A0) 13237 { /* SOC_FORMAT_INT_ENQ_TO_THDI_INT_INFO_BCM56260_A0fmt */ 13238 /* format ENQ_TO_THDI_INT_INFOfmt */ 13239 /* nFields */ 3, 13240 /* *fields */ soc_ENQ_TO_THDI_EMA_INFO_BCM56260_A0fmt_fields, 13241 /* bits */ 9, 13242 /* flags */ 0, 13243 }, 13244 #endif /* chips */ 13245 13246 #if defined(BCM_56260_B0) 13247 { /* SOC_FORMAT_INT_ENQ_TO_THDI_INT_INFO_BCM56260_B0fmt */ 13248 /* format ENQ_TO_THDI_INT_INFOfmt */ 13249 /* nFields */ 3, 13250 /* *fields */ soc_ENQ_TO_THDI_EMA_INFO_BCM56260_A0fmt_fields, 13251 /* bits */ 9, 13252 /* flags */ 0, 13253 }, 13254 #endif /* chips */ 13255 13256 #if defined(BCM_56270_A0) 13257 { /* SOC_FORMAT_INT_ENQ_TO_THDI_INT_INFO_BCM56270_A0fmt */ 13258 /* format ENQ_TO_THDI_INT_INFOfmt */ 13259 /* nFields */ 3, 13260 /* *fields */ soc_ENQ_TO_THDI_EMA_INFO_BCM56260_A0fmt_fields, 13261 /* bits */ 9, 13262 /* flags */ 0, 13263 }, 13264 #endif /* chips */ 13265 13266 #if defined(BCM_56440_B0) 13267 { /* SOC_FORMAT_INT_ENQ_TO_THDI_INT_INFO_BCM56440_B0fmt */ 13268 /* format ENQ_TO_THDI_INT_INFOfmt */ 13269 /* nFields */ 3, 13270 /* *fields */ soc_ENQ_TO_THDI_EMA_INFOfmt_fields, 13271 /* bits */ 9, 13272 /* flags */ 0, 13273 }, 13274 #endif /* chips */ 13275 13276 #if defined(BCM_56450_A0) 13277 { /* SOC_FORMAT_INT_ENQ_TO_THDI_INT_INFO_BCM56450_A0fmt */ 13278 /* format ENQ_TO_THDI_INT_INFOfmt */ 13279 /* nFields */ 3, 13280 /* *fields */ soc_ENQ_TO_THDI_EMA_INFO_BCM56450_A0fmt_fields, 13281 /* bits */ 9, 13282 /* flags */ 0, 13283 }, 13284 #endif /* chips */ 13285 13286 #if defined(BCM_56450_B0) 13287 { /* SOC_FORMAT_INT_ENQ_TO_THDI_INT_INFO_BCM56450_B0fmt */ 13288 /* format ENQ_TO_THDI_INT_INFOfmt */ 13289 /* nFields */ 3, 13290 /* *fields */ soc_ENQ_TO_THDI_EMA_INFO_BCM56450_A0fmt_fields, 13291 /* bits */ 9, 13292 /* flags */ 0, 13293 }, 13294 #endif /* chips */ 13295 13296 #if defined(BCM_56450_B1) 13297 { /* SOC_FORMAT_INT_ENQ_TO_THDI_INT_INFO_BCM56450_B1fmt */ 13298 /* format ENQ_TO_THDI_INT_INFOfmt */ 13299 /* nFields */ 3, 13300 /* *fields */ soc_ENQ_TO_THDI_EMA_INFO_BCM56450_A0fmt_fields, 13301 /* bits */ 9, 13302 /* flags */ 0, 13303 }, 13304 #endif /* chips */ 13305 13306 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) 13307 { /* SOC_FORMAT_INT_ENQ_TO_THDI_QEN_INFOfmt */ 13308 /* format ENQ_TO_THDI_QEN_INFOfmt */ 13309 /* nFields */ 1, 13310 /* *fields */ soc_ENQ_TO_THDI_QEN_INFOfmt_fields, 13311 /* bits */ 10, 13312 /* flags */ 0, 13313 }, 13314 #endif /* chips */ 13315 13316 #if defined(BCM_56260_A0) 13317 { /* SOC_FORMAT_INT_ENQ_TO_THDI_QEN_INFO_BCM56260_A0fmt */ 13318 /* format ENQ_TO_THDI_QEN_INFOfmt */ 13319 /* nFields */ 1, 13320 /* *fields */ soc_ENQ_TO_THDI_QEN_INFO_BCM56260_A0fmt_fields, 13321 /* bits */ 10, 13322 /* flags */ 0, 13323 }, 13324 #endif /* chips */ 13325 13326 #if defined(BCM_56260_B0) 13327 { /* SOC_FORMAT_INT_ENQ_TO_THDI_QEN_INFO_BCM56260_B0fmt */ 13328 /* format ENQ_TO_THDI_QEN_INFOfmt */ 13329 /* nFields */ 1, 13330 /* *fields */ soc_ENQ_TO_THDI_QEN_INFO_BCM56260_A0fmt_fields, 13331 /* bits */ 10, 13332 /* flags */ 0, 13333 }, 13334 #endif /* chips */ 13335 13336 #if defined(BCM_56270_A0) 13337 { /* SOC_FORMAT_INT_ENQ_TO_THDI_QEN_INFO_BCM56270_A0fmt */ 13338 /* format ENQ_TO_THDI_QEN_INFOfmt */ 13339 /* nFields */ 1, 13340 /* *fields */ soc_ENQ_TO_THDI_QEN_INFO_BCM56260_A0fmt_fields, 13341 /* bits */ 10, 13342 /* flags */ 0, 13343 }, 13344 #endif /* chips */ 13345 13346 #if defined(BCM_56450_A0) 13347 { /* SOC_FORMAT_INT_ENQ_TO_THDI_QEN_INFO_BCM56450_A0fmt */ 13348 /* format ENQ_TO_THDI_QEN_INFOfmt */ 13349 /* nFields */ 1, 13350 /* *fields */ soc_ENQ_TO_THDI_QEN_INFO_BCM56450_A0fmt_fields, 13351 /* bits */ 10, 13352 /* flags */ 0, 13353 }, 13354 #endif /* chips */ 13355 13356 #if defined(BCM_56450_B0) 13357 { /* SOC_FORMAT_INT_ENQ_TO_THDI_QEN_INFO_BCM56450_B0fmt */ 13358 /* format ENQ_TO_THDI_QEN_INFOfmt */ 13359 /* nFields */ 1, 13360 /* *fields */ soc_ENQ_TO_THDI_QEN_INFO_BCM56450_A0fmt_fields, 13361 /* bits */ 10, 13362 /* flags */ 0, 13363 }, 13364 #endif /* chips */ 13365 13366 #if defined(BCM_56450_B1) 13367 { /* SOC_FORMAT_INT_ENQ_TO_THDI_QEN_INFO_BCM56450_B1fmt */ 13368 /* format ENQ_TO_THDI_QEN_INFOfmt */ 13369 /* nFields */ 1, 13370 /* *fields */ soc_ENQ_TO_THDI_QEN_INFO_BCM56450_A0fmt_fields, 13371 /* bits */ 10, 13372 /* flags */ 0, 13373 }, 13374 #endif /* chips */ 13375 13376 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) 13377 { /* SOC_FORMAT_INT_ENQ_TO_THDI_QEN_PURGE_INFOfmt */ 13378 /* format ENQ_TO_THDI_QEN_PURGE_INFOfmt */ 13379 /* nFields */ 3, 13380 /* *fields */ soc_ENQ_TO_THDI_QEN_PURGE_INFOfmt_fields, 13381 /* bits */ 20, 13382 /* flags */ 0, 13383 }, 13384 #endif /* chips */ 13385 13386 #if defined(BCM_56440_A0) 13387 { /* SOC_FORMAT_INT_ENQ_TO_THDI_RQE_INFOfmt */ 13388 /* format ENQ_TO_THDI_RQE_INFOfmt */ 13389 /* nFields */ 1, 13390 /* *fields */ soc_CFG_TO_CTR_REG_INFOfmt_fields, 13391 /* bits */ 1, 13392 /* flags */ 0, 13393 }, 13394 #endif /* chips */ 13395 13396 #if defined(BCM_56440_B0) 13397 { /* SOC_FORMAT_INT_ENQ_TO_THDI_RQE_INFO_BCM56440_B0fmt */ 13398 /* format ENQ_TO_THDI_RQE_INFOfmt */ 13399 /* nFields */ 1, 13400 /* *fields */ soc_CFG_TO_CTR_REG_INFOfmt_fields, 13401 /* bits */ 1, 13402 /* flags */ 0, 13403 }, 13404 #endif /* chips */ 13405 13406 #if defined(BCM_56450_A0) 13407 { /* SOC_FORMAT_INT_ENQ_TO_THDI_RQE_INFO_BCM56450_A0fmt */ 13408 /* format ENQ_TO_THDI_RQE_INFOfmt */ 13409 /* nFields */ 1, 13410 /* *fields */ soc_CFG_TO_CTR_REG_INFO_BCM56450_A0fmt_fields, 13411 /* bits */ 1, 13412 /* flags */ 0, 13413 }, 13414 #endif /* chips */ 13415 13416 #if defined(BCM_56450_B0) 13417 { /* SOC_FORMAT_INT_ENQ_TO_THDI_RQE_INFO_BCM56450_B0fmt */ 13418 /* format ENQ_TO_THDI_RQE_INFOfmt */ 13419 /* nFields */ 1, 13420 /* *fields */ soc_CFG_TO_CTR_REG_INFO_BCM56450_A0fmt_fields, 13421 /* bits */ 1, 13422 /* flags */ 0, 13423 }, 13424 #endif /* chips */ 13425 13426 #if defined(BCM_56450_B1) 13427 { /* SOC_FORMAT_INT_ENQ_TO_THDI_RQE_INFO_BCM56450_B1fmt */ 13428 /* format ENQ_TO_THDI_RQE_INFOfmt */ 13429 /* nFields */ 1, 13430 /* *fields */ soc_CFG_TO_CTR_REG_INFO_BCM56450_A0fmt_fields, 13431 /* bits */ 1, 13432 /* flags */ 0, 13433 }, 13434 #endif /* chips */ 13435 13436 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) 13437 { /* SOC_FORMAT_INT_ENQ_TO_THDO_EMA_INFOfmt */ 13438 /* format ENQ_TO_THDO_EMA_INFOfmt */ 13439 /* nFields */ 4, 13440 /* *fields */ soc_ENQ_TO_THDO_EMA_INFOfmt_fields, 13441 /* bits */ 12, 13442 /* flags */ 0, 13443 }, 13444 #endif /* chips */ 13445 13446 #if defined(BCM_56260_A0) 13447 { /* SOC_FORMAT_INT_ENQ_TO_THDO_EMA_INFO_BCM56260_A0fmt */ 13448 /* format ENQ_TO_THDO_EMA_INFOfmt */ 13449 /* nFields */ 5, 13450 /* *fields */ soc_ENQ_TO_THDO_EMA_INFO_BCM56260_A0fmt_fields, 13451 /* bits */ 19, 13452 /* flags */ 0, 13453 }, 13454 #endif /* chips */ 13455 13456 #if defined(BCM_56260_B0) 13457 { /* SOC_FORMAT_INT_ENQ_TO_THDO_EMA_INFO_BCM56260_B0fmt */ 13458 /* format ENQ_TO_THDO_EMA_INFOfmt */ 13459 /* nFields */ 5, 13460 /* *fields */ soc_ENQ_TO_THDO_EMA_INFO_BCM56260_A0fmt_fields, 13461 /* bits */ 19, 13462 /* flags */ 0, 13463 }, 13464 #endif /* chips */ 13465 13466 #if defined(BCM_56270_A0) 13467 { /* SOC_FORMAT_INT_ENQ_TO_THDO_EMA_INFO_BCM56270_A0fmt */ 13468 /* format ENQ_TO_THDO_EMA_INFOfmt */ 13469 /* nFields */ 5, 13470 /* *fields */ soc_ENQ_TO_THDO_EMA_INFO_BCM56260_A0fmt_fields, 13471 /* bits */ 19, 13472 /* flags */ 0, 13473 }, 13474 #endif /* chips */ 13475 13476 #if defined(BCM_56450_A0) 13477 { /* SOC_FORMAT_INT_ENQ_TO_THDO_EMA_INFO_BCM56450_A0fmt */ 13478 /* format ENQ_TO_THDO_EMA_INFOfmt */ 13479 /* nFields */ 5, 13480 /* *fields */ soc_ENQ_TO_THDO_EMA_INFO_BCM56450_A0fmt_fields, 13481 /* bits */ 22, 13482 /* flags */ 0, 13483 }, 13484 #endif /* chips */ 13485 13486 #if defined(BCM_56450_B0) 13487 { /* SOC_FORMAT_INT_ENQ_TO_THDO_EMA_INFO_BCM56450_B0fmt */ 13488 /* format ENQ_TO_THDO_EMA_INFOfmt */ 13489 /* nFields */ 5, 13490 /* *fields */ soc_ENQ_TO_THDO_EMA_INFO_BCM56450_A0fmt_fields, 13491 /* bits */ 22, 13492 /* flags */ 0, 13493 }, 13494 #endif /* chips */ 13495 13496 #if defined(BCM_56450_B1) 13497 { /* SOC_FORMAT_INT_ENQ_TO_THDO_EMA_INFO_BCM56450_B1fmt */ 13498 /* format ENQ_TO_THDO_EMA_INFOfmt */ 13499 /* nFields */ 5, 13500 /* *fields */ soc_ENQ_TO_THDO_EMA_INFO_BCM56450_A0fmt_fields, 13501 /* bits */ 22, 13502 /* flags */ 0, 13503 }, 13504 #endif /* chips */ 13505 13506 #if defined(BCM_56440_A0) 13507 { /* SOC_FORMAT_INT_ENQ_TO_THDO_RQEE_INFOfmt */ 13508 /* format ENQ_TO_THDO_RQEE_INFOfmt */ 13509 /* nFields */ 5, 13510 /* *fields */ soc_ENQ_TO_THDO_RQEE_INFOfmt_fields, 13511 /* bits */ 14, 13512 /* flags */ 0, 13513 }, 13514 #endif /* chips */ 13515 13516 #if defined(BCM_56260_A0) 13517 { /* SOC_FORMAT_INT_ENQ_TO_THDO_RQEE_INFO_BCM56260_A0fmt */ 13518 /* format ENQ_TO_THDO_RQEE_INFOfmt */ 13519 /* nFields */ 6, 13520 /* *fields */ soc_ENQ_TO_THDO_RQEE_INFO_BCM56260_A0fmt_fields, 13521 /* bits */ 21, 13522 /* flags */ 0, 13523 }, 13524 #endif /* chips */ 13525 13526 #if defined(BCM_56260_B0) 13527 { /* SOC_FORMAT_INT_ENQ_TO_THDO_RQEE_INFO_BCM56260_B0fmt */ 13528 /* format ENQ_TO_THDO_RQEE_INFOfmt */ 13529 /* nFields */ 6, 13530 /* *fields */ soc_ENQ_TO_THDO_RQEE_INFO_BCM56260_A0fmt_fields, 13531 /* bits */ 21, 13532 /* flags */ 0, 13533 }, 13534 #endif /* chips */ 13535 13536 #if defined(BCM_56270_A0) 13537 { /* SOC_FORMAT_INT_ENQ_TO_THDO_RQEE_INFO_BCM56270_A0fmt */ 13538 /* format ENQ_TO_THDO_RQEE_INFOfmt */ 13539 /* nFields */ 6, 13540 /* *fields */ soc_ENQ_TO_THDO_RQEE_INFO_BCM56260_A0fmt_fields, 13541 /* bits */ 21, 13542 /* flags */ 0, 13543 }, 13544 #endif /* chips */ 13545 13546 #if defined(BCM_56440_B0) 13547 { /* SOC_FORMAT_INT_ENQ_TO_THDO_RQEE_INFO_BCM56440_B0fmt */ 13548 /* format ENQ_TO_THDO_RQEE_INFOfmt */ 13549 /* nFields */ 5, 13550 /* *fields */ soc_ENQ_TO_THDO_RQEE_INFOfmt_fields, 13551 /* bits */ 14, 13552 /* flags */ 0, 13553 }, 13554 #endif /* chips */ 13555 13556 #if defined(BCM_56450_A0) 13557 { /* SOC_FORMAT_INT_ENQ_TO_THDO_RQEE_INFO_BCM56450_A0fmt */ 13558 /* format ENQ_TO_THDO_RQEE_INFOfmt */ 13559 /* nFields */ 6, 13560 /* *fields */ soc_ENQ_TO_THDO_RQEE_INFO_BCM56450_A0fmt_fields, 13561 /* bits */ 24, 13562 /* flags */ 0, 13563 }, 13564 #endif /* chips */ 13565 13566 #if defined(BCM_56450_B0) 13567 { /* SOC_FORMAT_INT_ENQ_TO_THDO_RQEE_INFO_BCM56450_B0fmt */ 13568 /* format ENQ_TO_THDO_RQEE_INFOfmt */ 13569 /* nFields */ 6, 13570 /* *fields */ soc_ENQ_TO_THDO_RQEE_INFO_BCM56450_A0fmt_fields, 13571 /* bits */ 24, 13572 /* flags */ 0, 13573 }, 13574 #endif /* chips */ 13575 13576 #if defined(BCM_56450_B1) 13577 { /* SOC_FORMAT_INT_ENQ_TO_THDO_RQEE_INFO_BCM56450_B1fmt */ 13578 /* format ENQ_TO_THDO_RQEE_INFOfmt */ 13579 /* nFields */ 6, 13580 /* *fields */ soc_ENQ_TO_THDO_RQEE_INFO_BCM56450_A0fmt_fields, 13581 /* bits */ 24, 13582 /* flags */ 0, 13583 }, 13584 #endif /* chips */ 13585 13586 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) 13587 { /* SOC_FORMAT_INT_ENQ_TO_THDO_RQEI_INFOfmt */ 13588 /* format ENQ_TO_THDO_RQEI_INFOfmt */ 13589 /* nFields */ 5, 13590 /* *fields */ soc_ENQ_TO_THDO_RQEE_INFOfmt_fields, 13591 /* bits */ 14, 13592 /* flags */ 0, 13593 }, 13594 #endif /* chips */ 13595 13596 #if defined(BCM_56260_A0) 13597 { /* SOC_FORMAT_INT_ENQ_TO_THDO_RQEI_INFO_BCM56260_A0fmt */ 13598 /* format ENQ_TO_THDO_RQEI_INFOfmt */ 13599 /* nFields */ 6, 13600 /* *fields */ soc_ENQ_TO_THDO_RQEE_INFO_BCM56260_A0fmt_fields, 13601 /* bits */ 21, 13602 /* flags */ 0, 13603 }, 13604 #endif /* chips */ 13605 13606 #if defined(BCM_56260_B0) 13607 { /* SOC_FORMAT_INT_ENQ_TO_THDO_RQEI_INFO_BCM56260_B0fmt */ 13608 /* format ENQ_TO_THDO_RQEI_INFOfmt */ 13609 /* nFields */ 6, 13610 /* *fields */ soc_ENQ_TO_THDO_RQEE_INFO_BCM56260_A0fmt_fields, 13611 /* bits */ 21, 13612 /* flags */ 0, 13613 }, 13614 #endif /* chips */ 13615 13616 #if defined(BCM_56270_A0) 13617 { /* SOC_FORMAT_INT_ENQ_TO_THDO_RQEI_INFO_BCM56270_A0fmt */ 13618 /* format ENQ_TO_THDO_RQEI_INFOfmt */ 13619 /* nFields */ 6, 13620 /* *fields */ soc_ENQ_TO_THDO_RQEE_INFO_BCM56260_A0fmt_fields, 13621 /* bits */ 21, 13622 /* flags */ 0, 13623 }, 13624 #endif /* chips */ 13625 13626 #if defined(BCM_56450_A0) 13627 { /* SOC_FORMAT_INT_ENQ_TO_THDO_RQEI_INFO_BCM56450_A0fmt */ 13628 /* format ENQ_TO_THDO_RQEI_INFOfmt */ 13629 /* nFields */ 6, 13630 /* *fields */ soc_ENQ_TO_THDO_RQEE_INFO_BCM56450_A0fmt_fields, 13631 /* bits */ 24, 13632 /* flags */ 0, 13633 }, 13634 #endif /* chips */ 13635 13636 #if defined(BCM_56450_B0) 13637 { /* SOC_FORMAT_INT_ENQ_TO_THDO_RQEI_INFO_BCM56450_B0fmt */ 13638 /* format ENQ_TO_THDO_RQEI_INFOfmt */ 13639 /* nFields */ 6, 13640 /* *fields */ soc_ENQ_TO_THDO_RQEE_INFO_BCM56450_A0fmt_fields, 13641 /* bits */ 24, 13642 /* flags */ 0, 13643 }, 13644 #endif /* chips */ 13645 13646 #if defined(BCM_56450_B1) 13647 { /* SOC_FORMAT_INT_ENQ_TO_THDO_RQEI_INFO_BCM56450_B1fmt */ 13648 /* format ENQ_TO_THDO_RQEI_INFOfmt */ 13649 /* nFields */ 6, 13650 /* *fields */ soc_ENQ_TO_THDO_RQEE_INFO_BCM56450_A0fmt_fields, 13651 /* bits */ 24, 13652 /* flags */ 0, 13653 }, 13654 #endif /* chips */ 13655 13656 #if defined(BCM_56440_A0) 13657 { /* SOC_FORMAT_INT_ENQ_TO_THDO_RQEQ_INFOfmt */ 13658 /* format ENQ_TO_THDO_RQEQ_INFOfmt */ 13659 /* nFields */ 3, 13660 /* *fields */ soc_ENQ_TO_THDO_RQEQ_INFOfmt_fields, 13661 /* bits */ 7, 13662 /* flags */ 0, 13663 }, 13664 #endif /* chips */ 13665 13666 #if defined(BCM_56260_A0) 13667 { /* SOC_FORMAT_INT_ENQ_TO_THDO_RQEQ_INFO_BCM56260_A0fmt */ 13668 /* format ENQ_TO_THDO_RQEQ_INFOfmt */ 13669 /* nFields */ 3, 13670 /* *fields */ soc_ENQ_TO_THDO_RQEQ_INFO_BCM56260_A0fmt_fields, 13671 /* bits */ 7, 13672 /* flags */ 0, 13673 }, 13674 #endif /* chips */ 13675 13676 #if defined(BCM_56260_B0) 13677 { /* SOC_FORMAT_INT_ENQ_TO_THDO_RQEQ_INFO_BCM56260_B0fmt */ 13678 /* format ENQ_TO_THDO_RQEQ_INFOfmt */ 13679 /* nFields */ 3, 13680 /* *fields */ soc_ENQ_TO_THDO_RQEQ_INFO_BCM56260_A0fmt_fields, 13681 /* bits */ 7, 13682 /* flags */ 0, 13683 }, 13684 #endif /* chips */ 13685 13686 #if defined(BCM_56270_A0) 13687 { /* SOC_FORMAT_INT_ENQ_TO_THDO_RQEQ_INFO_BCM56270_A0fmt */ 13688 /* format ENQ_TO_THDO_RQEQ_INFOfmt */ 13689 /* nFields */ 3, 13690 /* *fields */ soc_ENQ_TO_THDO_RQEQ_INFO_BCM56260_A0fmt_fields, 13691 /* bits */ 7, 13692 /* flags */ 0, 13693 }, 13694 #endif /* chips */ 13695 13696 #if defined(BCM_56440_B0) 13697 { /* SOC_FORMAT_INT_ENQ_TO_THDO_RQEQ_INFO_BCM56440_B0fmt */ 13698 /* format ENQ_TO_THDO_RQEQ_INFOfmt */ 13699 /* nFields */ 3, 13700 /* *fields */ soc_ENQ_TO_THDO_RQEQ_INFOfmt_fields, 13701 /* bits */ 7, 13702 /* flags */ 0, 13703 }, 13704 #endif /* chips */ 13705 13706 #if defined(BCM_56450_A0) 13707 { /* SOC_FORMAT_INT_ENQ_TO_THDO_RQEQ_INFO_BCM56450_A0fmt */ 13708 /* format ENQ_TO_THDO_RQEQ_INFOfmt */ 13709 /* nFields */ 3, 13710 /* *fields */ soc_ENQ_TO_THDO_RQEQ_INFO_BCM56450_A0fmt_fields, 13711 /* bits */ 7, 13712 /* flags */ 0, 13713 }, 13714 #endif /* chips */ 13715 13716 #if defined(BCM_56450_B0) 13717 { /* SOC_FORMAT_INT_ENQ_TO_THDO_RQEQ_INFO_BCM56450_B0fmt */ 13718 /* format ENQ_TO_THDO_RQEQ_INFOfmt */ 13719 /* nFields */ 3, 13720 /* *fields */ soc_ENQ_TO_THDO_RQEQ_INFO_BCM56450_A0fmt_fields, 13721 /* bits */ 7, 13722 /* flags */ 0, 13723 }, 13724 #endif /* chips */ 13725 13726 #if defined(BCM_56450_B1) 13727 { /* SOC_FORMAT_INT_ENQ_TO_THDO_RQEQ_INFO_BCM56450_B1fmt */ 13728 /* format ENQ_TO_THDO_RQEQ_INFOfmt */ 13729 /* nFields */ 3, 13730 /* *fields */ soc_ENQ_TO_THDO_RQEQ_INFO_BCM56450_A0fmt_fields, 13731 /* bits */ 7, 13732 /* flags */ 0, 13733 }, 13734 #endif /* chips */ 13735 13736 #if defined(BCM_56670_A0) || defined(BCM_56670_B0) 13737 { /* SOC_FORMAT_INT_ENQ_TO_TOQ_CELLLINK_WDATAfmt */ 13738 /* format ENQ_TO_TOQ_CELLLINK_WDATAfmt */ 13739 /* nFields */ 2, 13740 /* *fields */ soc_ENQ_TO_TOQ_CELLLINK_WDATAfmt_fields, 13741 /* bits */ 16, 13742 /* flags */ 0, 13743 }, 13744 #endif /* chips */ 13745 13746 #if defined(BCM_56670_A0) || defined(BCM_56670_B0) 13747 { /* SOC_FORMAT_INT_ENQ_TO_TOQ_SRCPORT_INFOfmt */ 13748 /* format ENQ_TO_TOQ_SRCPORT_INFOfmt */ 13749 /* nFields */ 2, 13750 /* *fields */ soc_ENQ_TO_TOQ_SRCPORT_INFOfmt_fields, 13751 /* bits */ 9, 13752 /* flags */ 0, 13753 }, 13754 #endif /* chips */ 13755 13756 #if defined(BCM_56440_A0) 13757 { /* SOC_FORMAT_INT_ENQ_TO_TOQ_WCI_INFOfmt */ 13758 /* format ENQ_TO_TOQ_WCI_INFOfmt */ 13759 /* nFields */ 8, 13760 /* *fields */ soc_ENQ_TO_TOQ_WCI_INFOfmt_fields, 13761 /* bits */ 41, 13762 /* flags */ 0, 13763 }, 13764 #endif /* chips */ 13765 13766 #if defined(BCM_56260_A0) 13767 { /* SOC_FORMAT_INT_ENQ_TO_TOQ_WCI_INFO_BCM56260_A0fmt */ 13768 /* format ENQ_TO_TOQ_WCI_INFOfmt */ 13769 /* nFields */ 9, 13770 /* *fields */ soc_ENQ_TO_TOQ_WCI_INFO_BCM56260_A0fmt_fields, 13771 /* bits */ 35, 13772 /* flags */ 0, 13773 }, 13774 #endif /* chips */ 13775 13776 #if defined(BCM_56260_B0) 13777 { /* SOC_FORMAT_INT_ENQ_TO_TOQ_WCI_INFO_BCM56260_B0fmt */ 13778 /* format ENQ_TO_TOQ_WCI_INFOfmt */ 13779 /* nFields */ 9, 13780 /* *fields */ soc_ENQ_TO_TOQ_WCI_INFO_BCM56260_A0fmt_fields, 13781 /* bits */ 35, 13782 /* flags */ 0, 13783 }, 13784 #endif /* chips */ 13785 13786 #if defined(BCM_56270_A0) 13787 { /* SOC_FORMAT_INT_ENQ_TO_TOQ_WCI_INFO_BCM56270_A0fmt */ 13788 /* format ENQ_TO_TOQ_WCI_INFOfmt */ 13789 /* nFields */ 9, 13790 /* *fields */ soc_ENQ_TO_TOQ_WCI_INFO_BCM56270_A0fmt_fields, 13791 /* bits */ 32, 13792 /* flags */ 0, 13793 }, 13794 #endif /* chips */ 13795 13796 #if defined(BCM_56440_B0) 13797 { /* SOC_FORMAT_INT_ENQ_TO_TOQ_WCI_INFO_BCM56440_B0fmt */ 13798 /* format ENQ_TO_TOQ_WCI_INFOfmt */ 13799 /* nFields */ 8, 13800 /* *fields */ soc_ENQ_TO_TOQ_WCI_INFOfmt_fields, 13801 /* bits */ 41, 13802 /* flags */ 0, 13803 }, 13804 #endif /* chips */ 13805 13806 #if defined(BCM_56450_A0) 13807 { /* SOC_FORMAT_INT_ENQ_TO_TOQ_WCI_INFO_BCM56450_A0fmt */ 13808 /* format ENQ_TO_TOQ_WCI_INFOfmt */ 13809 /* nFields */ 9, 13810 /* *fields */ soc_ENQ_TO_TOQ_WCI_INFO_BCM56450_A0fmt_fields, 13811 /* bits */ 39, 13812 /* flags */ 0, 13813 }, 13814 #endif /* chips */ 13815 13816 #if defined(BCM_56450_B0) 13817 { /* SOC_FORMAT_INT_ENQ_TO_TOQ_WCI_INFO_BCM56450_B0fmt */ 13818 /* format ENQ_TO_TOQ_WCI_INFOfmt */ 13819 /* nFields */ 9, 13820 /* *fields */ soc_ENQ_TO_TOQ_WCI_INFO_BCM56450_A0fmt_fields, 13821 /* bits */ 39, 13822 /* flags */ 0, 13823 }, 13824 #endif /* chips */ 13825 13826 #if defined(BCM_56450_B1) 13827 { /* SOC_FORMAT_INT_ENQ_TO_TOQ_WCI_INFO_BCM56450_B1fmt */ 13828 /* format ENQ_TO_TOQ_WCI_INFOfmt */ 13829 /* nFields */ 9, 13830 /* *fields */ soc_ENQ_TO_TOQ_WCI_INFO_BCM56450_A0fmt_fields, 13831 /* bits */ 39, 13832 /* flags */ 0, 13833 }, 13834 #endif /* chips */ 13835 13836 #if defined(BCM_56800_A0) 13837 { /* SOC_FORMAT_INT_ENQ_TO_TOQ_XQ_WR_INFOfmt */ 13838 /* format ENQ_TO_TOQ_XQ_WR_INFOfmt */ 13839 /* nFields */ 11, 13840 /* *fields */ soc_ENQ_TO_TOQ_XQ_WR_INFOfmt_fields, 13841 /* bits */ 390, 13842 /* flags */ 0, 13843 }, 13844 #endif /* chips */ 13845 13846 #if defined(BCM_56334_A0) 13847 { /* SOC_FORMAT_INT_ENQ_TO_TOQ_XQ_WR_INFO_BCM56334_A0fmt */ 13848 /* format ENQ_TO_TOQ_XQ_WR_INFOfmt */ 13849 /* nFields */ 9, 13850 /* *fields */ soc_ENQ_TO_TOQ_XQ_WR_INFO_BCM56334_A0fmt_fields, 13851 /* bits */ 206, 13852 /* flags */ 0, 13853 }, 13854 #endif /* chips */ 13855 13856 #if defined(BCM_56334_B0) 13857 { /* SOC_FORMAT_INT_ENQ_TO_TOQ_XQ_WR_INFO_BCM56334_B0fmt */ 13858 /* format ENQ_TO_TOQ_XQ_WR_INFOfmt */ 13859 /* nFields */ 9, 13860 /* *fields */ soc_ENQ_TO_TOQ_XQ_WR_INFO_BCM56334_A0fmt_fields, 13861 /* bits */ 206, 13862 /* flags */ 0, 13863 }, 13864 #endif /* chips */ 13865 13866 #if defined(BCM_56524_A0) 13867 { /* SOC_FORMAT_INT_ENQ_TO_TOQ_XQ_WR_INFO_BCM56524_A0fmt */ 13868 /* format ENQ_TO_TOQ_XQ_WR_INFOfmt */ 13869 /* nFields */ 8, 13870 /* *fields */ soc_ENQ_TO_TOQ_XQ_WR_INFO_BCM56634_A0fmt_fields, 13871 /* bits */ 252, 13872 /* flags */ 0, 13873 }, 13874 #endif /* chips */ 13875 13876 #if defined(BCM_56524_B0) 13877 { /* SOC_FORMAT_INT_ENQ_TO_TOQ_XQ_WR_INFO_BCM56524_B0fmt */ 13878 /* format ENQ_TO_TOQ_XQ_WR_INFOfmt */ 13879 /* nFields */ 8, 13880 /* *fields */ soc_ENQ_TO_TOQ_XQ_WR_INFO_BCM56634_A0fmt_fields, 13881 /* bits */ 252, 13882 /* flags */ 0, 13883 }, 13884 #endif /* chips */ 13885 13886 #if defined(BCM_56624_A0) 13887 { /* SOC_FORMAT_INT_ENQ_TO_TOQ_XQ_WR_INFO_BCM56624_A0fmt */ 13888 /* format ENQ_TO_TOQ_XQ_WR_INFOfmt */ 13889 /* nFields */ 9, 13890 /* *fields */ soc_ENQ_TO_TOQ_XQ_WR_INFO_BCM56624_A0fmt_fields, 13891 /* bits */ 302, 13892 /* flags */ 0, 13893 }, 13894 #endif /* chips */ 13895 13896 #if defined(BCM_56624_B0) 13897 { /* SOC_FORMAT_INT_ENQ_TO_TOQ_XQ_WR_INFO_BCM56624_B0fmt */ 13898 /* format ENQ_TO_TOQ_XQ_WR_INFOfmt */ 13899 /* nFields */ 9, 13900 /* *fields */ soc_ENQ_TO_TOQ_XQ_WR_INFO_BCM56624_A0fmt_fields, 13901 /* bits */ 302, 13902 /* flags */ 0, 13903 }, 13904 #endif /* chips */ 13905 13906 #if defined(BCM_56634_A0) 13907 { /* SOC_FORMAT_INT_ENQ_TO_TOQ_XQ_WR_INFO_BCM56634_A0fmt */ 13908 /* format ENQ_TO_TOQ_XQ_WR_INFOfmt */ 13909 /* nFields */ 8, 13910 /* *fields */ soc_ENQ_TO_TOQ_XQ_WR_INFO_BCM56634_A0fmt_fields, 13911 /* bits */ 252, 13912 /* flags */ 0, 13913 }, 13914 #endif /* chips */ 13915 13916 #if defined(BCM_56634_B0) 13917 { /* SOC_FORMAT_INT_ENQ_TO_TOQ_XQ_WR_INFO_BCM56634_B0fmt */ 13918 /* format ENQ_TO_TOQ_XQ_WR_INFOfmt */ 13919 /* nFields */ 8, 13920 /* *fields */ soc_ENQ_TO_TOQ_XQ_WR_INFO_BCM56634_A0fmt_fields, 13921 /* bits */ 252, 13922 /* flags */ 0, 13923 }, 13924 #endif /* chips */ 13925 13926 #if defined(BCM_56680_A0) 13927 { /* SOC_FORMAT_INT_ENQ_TO_TOQ_XQ_WR_INFO_BCM56680_A0fmt */ 13928 /* format ENQ_TO_TOQ_XQ_WR_INFOfmt */ 13929 /* nFields */ 9, 13930 /* *fields */ soc_ENQ_TO_TOQ_XQ_WR_INFO_BCM56624_A0fmt_fields, 13931 /* bits */ 302, 13932 /* flags */ 0, 13933 }, 13934 #endif /* chips */ 13935 13936 #if defined(BCM_56680_B0) 13937 { /* SOC_FORMAT_INT_ENQ_TO_TOQ_XQ_WR_INFO_BCM56680_B0fmt */ 13938 /* format ENQ_TO_TOQ_XQ_WR_INFOfmt */ 13939 /* nFields */ 9, 13940 /* *fields */ soc_ENQ_TO_TOQ_XQ_WR_INFO_BCM56624_A0fmt_fields, 13941 /* bits */ 302, 13942 /* flags */ 0, 13943 }, 13944 #endif /* chips */ 13945 13946 #if defined(BCM_56685_A0) 13947 { /* SOC_FORMAT_INT_ENQ_TO_TOQ_XQ_WR_INFO_BCM56685_A0fmt */ 13948 /* format ENQ_TO_TOQ_XQ_WR_INFOfmt */ 13949 /* nFields */ 8, 13950 /* *fields */ soc_ENQ_TO_TOQ_XQ_WR_INFO_BCM56634_A0fmt_fields, 13951 /* bits */ 252, 13952 /* flags */ 0, 13953 }, 13954 #endif /* chips */ 13955 13956 #if defined(BCM_56685_B0) 13957 { /* SOC_FORMAT_INT_ENQ_TO_TOQ_XQ_WR_INFO_BCM56685_B0fmt */ 13958 /* format ENQ_TO_TOQ_XQ_WR_INFOfmt */ 13959 /* nFields */ 8, 13960 /* *fields */ soc_ENQ_TO_TOQ_XQ_WR_INFO_BCM56634_A0fmt_fields, 13961 /* bits */ 252, 13962 /* flags */ 0, 13963 }, 13964 #endif /* chips */ 13965 13966 #if defined(BCM_56725_A0) 13967 { /* SOC_FORMAT_INT_ENQ_TO_TOQ_XQ_WR_INFO_BCM56725_A0fmt */ 13968 /* format ENQ_TO_TOQ_XQ_WR_INFOfmt */ 13969 /* nFields */ 7, 13970 /* *fields */ soc_ENQ_TO_TOQ_XQ_WR_INFO_BCM56820_A0fmt_fields, 13971 /* bits */ 178, 13972 /* flags */ 0, 13973 }, 13974 #endif /* chips */ 13975 13976 #if defined(BCM_56820_A0) 13977 { /* SOC_FORMAT_INT_ENQ_TO_TOQ_XQ_WR_INFO_BCM56820_A0fmt */ 13978 /* format ENQ_TO_TOQ_XQ_WR_INFOfmt */ 13979 /* nFields */ 7, 13980 /* *fields */ soc_ENQ_TO_TOQ_XQ_WR_INFO_BCM56820_A0fmt_fields, 13981 /* bits */ 178, 13982 /* flags */ 0, 13983 }, 13984 #endif /* chips */ 13985 13986 #if defined(BCM_88732_A0) 13987 { /* SOC_FORMAT_INT_ENQ_TO_TOQ_XQ_WR_INFO_BCM88732_A0fmt */ 13988 /* format ENQ_TO_TOQ_XQ_WR_INFOfmt */ 13989 /* nFields */ 5, 13990 /* *fields */ soc_ENQ_TO_TOQ_XQ_WR_INFO_BCM88732_A0fmt_fields, 13991 /* bits */ 28, 13992 /* flags */ 0, 13993 }, 13994 #endif /* chips */ 13995 13996 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \ 13997 defined(BCM_56634_A0) || defined(BCM_56634_B0) || \ 13998 defined(BCM_56685_B0) 13999 { /* SOC_FORMAT_INT_ENQ_TO_WAMU_INFOfmt */ 14000 /* format ENQ_TO_WAMU_INFOfmt */ 14001 /* nFields */ 12, 14002 /* *fields */ soc_ENQ_TO_WAMU_INFOfmt_fields, 14003 /* bits */ 101, 14004 /* flags */ 0, 14005 }, 14006 #endif /* chips */ 14007 14008 #if defined(BCM_56340_A0) 14009 { /* SOC_FORMAT_INT_ENQ_TO_WAMU_INFO_BCM56340_A0fmt */ 14010 /* format ENQ_TO_WAMU_INFOfmt */ 14011 /* nFields */ 17, 14012 /* *fields */ soc_ENQ_TO_WAMU_INFO_BCM56640_A0fmt_fields, 14013 /* bits */ 104, 14014 /* flags */ 0, 14015 }, 14016 #endif /* chips */ 14017 14018 #if defined(BCM_56640_A0) 14019 { /* SOC_FORMAT_INT_ENQ_TO_WAMU_INFO_BCM56640_A0fmt */ 14020 /* format ENQ_TO_WAMU_INFOfmt */ 14021 /* nFields */ 17, 14022 /* *fields */ soc_ENQ_TO_WAMU_INFO_BCM56640_A0fmt_fields, 14023 /* bits */ 104, 14024 /* flags */ 0, 14025 }, 14026 #endif /* chips */ 14027 14028 #if defined(BCM_56685_A0) 14029 { /* SOC_FORMAT_INT_ENQ_TO_WAMU_INFO_BCM56685_A0fmt */ 14030 /* format ENQ_TO_WAMU_INFOfmt */ 14031 /* nFields */ 12, 14032 /* *fields */ soc_ENQ_TO_WAMU_INFOfmt_fields, 14033 /* bits */ 101, 14034 /* flags */ 0, 14035 }, 14036 #endif /* chips */ 14037 14038 #if defined(BCM_56224_A0) 14039 { /* SOC_FORMAT_INT_EOP_BUFFERfmt */ 14040 /* format EOP_BUFFERfmt */ 14041 /* nFields */ 10, 14042 /* *fields */ soc_EOP_BUFFERfmt_fields, 14043 /* bits */ 107, 14044 /* flags */ 0, 14045 }, 14046 #endif /* chips */ 14047 14048 #if defined(BCM_53314_A0) 14049 { /* SOC_FORMAT_INT_EOP_BUFFER_BCM53314_A0fmt */ 14050 /* format EOP_BUFFERfmt */ 14051 /* nFields */ 10, 14052 /* *fields */ soc_EOP_BUFFERfmt_fields, 14053 /* bits */ 107, 14054 /* flags */ 0, 14055 }, 14056 #endif /* chips */ 14057 14058 #if defined(BCM_53324_A0) 14059 { /* SOC_FORMAT_INT_EOP_BUFFER_BCM53324_A0fmt */ 14060 /* format EOP_BUFFERfmt */ 14061 /* nFields */ 10, 14062 /* *fields */ soc_EOP_BUFFERfmt_fields, 14063 /* bits */ 107, 14064 /* flags */ 0, 14065 }, 14066 #endif /* chips */ 14067 14068 #if defined(BCM_56224_B0) 14069 { /* SOC_FORMAT_INT_EOP_BUFFER_BCM56224_B0fmt */ 14070 /* format EOP_BUFFERfmt */ 14071 /* nFields */ 10, 14072 /* *fields */ soc_EOP_BUFFERfmt_fields, 14073 /* bits */ 107, 14074 /* flags */ 0, 14075 }, 14076 #endif /* chips */ 14077 14078 #if defined(BCM_56970_A0) 14079 { /* SOC_FORMAT_INT_EOP_BUFFER_B_COV_DEFSfmt */ 14080 /* format EOP_BUFFER_B_COV_DEFSfmt */ 14081 /* nFields */ 6, 14082 /* *fields */ soc_EOP_BUFFER_B_COV_DEFSfmt_fields, 14083 /* bits */ 17, 14084 /* flags */ 0, 14085 }, 14086 #endif /* chips */ 14087 14088 #if defined(BCM_56370_A0) 14089 { /* SOC_FORMAT_INT_EOP_BUFFER_B_COV_DEFS_BCM56370_A0fmt */ 14090 /* format EOP_BUFFER_B_COV_DEFSfmt */ 14091 /* nFields */ 6, 14092 /* *fields */ soc_EOP_BUFFER_B_COV_DEFS_BCM56870_A0fmt_fields, 14093 /* bits */ 19, 14094 /* flags */ 0, 14095 }, 14096 #endif /* chips */ 14097 14098 #if defined(BCM_56770_A0) 14099 { /* SOC_FORMAT_INT_EOP_BUFFER_B_COV_DEFS_BCM56770_A0fmt */ 14100 /* format EOP_BUFFER_B_COV_DEFSfmt */ 14101 /* nFields */ 6, 14102 /* *fields */ soc_EOP_BUFFER_B_COV_DEFS_BCM56870_A0fmt_fields, 14103 /* bits */ 19, 14104 /* flags */ 0, 14105 }, 14106 #endif /* chips */ 14107 14108 #if defined(BCM_56870_A0) 14109 { /* SOC_FORMAT_INT_EOP_BUFFER_B_COV_DEFS_BCM56870_A0fmt */ 14110 /* format EOP_BUFFER_B_COV_DEFSfmt */ 14111 /* nFields */ 6, 14112 /* *fields */ soc_EOP_BUFFER_B_COV_DEFS_BCM56870_A0fmt_fields, 14113 /* bits */ 19, 14114 /* flags */ 0, 14115 }, 14116 #endif /* chips */ 14117 14118 #if defined(BCM_56980_A0) 14119 { /* SOC_FORMAT_INT_EOP_BUFFER_B_COV_DEFS_BCM56980_A0fmt */ 14120 /* format EOP_BUFFER_B_COV_DEFSfmt */ 14121 /* nFields */ 6, 14122 /* *fields */ soc_EOP_BUFFER_B_COV_DEFS_BCM56980_A0fmt_fields, 14123 /* bits */ 17, 14124 /* flags */ 0, 14125 }, 14126 #endif /* chips */ 14127 14128 #if defined(BCM_56980_B0) 14129 { /* SOC_FORMAT_INT_EOP_BUFFER_B_COV_DEFS_BCM56980_B0fmt */ 14130 /* format EOP_BUFFER_B_COV_DEFSfmt */ 14131 /* nFields */ 6, 14132 /* *fields */ soc_EOP_BUFFER_B_COV_DEFS_BCM56980_A0fmt_fields, 14133 /* bits */ 17, 14134 /* flags */ 0, 14135 }, 14136 #endif /* chips */ 14137 14138 #if defined(BCM_56970_A0) 14139 { /* SOC_FORMAT_INT_EOP_BUFFER_MTUfmt */ 14140 /* format EOP_BUFFER_MTUfmt */ 14141 /* nFields */ 4, 14142 /* *fields */ soc_EOP_BUFFER_MTUfmt_fields, 14143 /* bits */ 23, 14144 /* flags */ 0, 14145 }, 14146 #endif /* chips */ 14147 14148 #if defined(BCM_56980_A0) 14149 { /* SOC_FORMAT_INT_EOP_BUFFER_MTU_BCM56980_A0fmt */ 14150 /* format EOP_BUFFER_MTUfmt */ 14151 /* nFields */ 4, 14152 /* *fields */ soc_EOP_BUFFER_MTU_BCM56980_A0fmt_fields, 14153 /* bits */ 23, 14154 /* flags */ 0, 14155 }, 14156 #endif /* chips */ 14157 14158 #if defined(BCM_56980_B0) 14159 { /* SOC_FORMAT_INT_EOP_BUFFER_MTU_BCM56980_B0fmt */ 14160 /* format EOP_BUFFER_MTUfmt */ 14161 /* nFields */ 4, 14162 /* *fields */ soc_EOP_BUFFER_MTU_BCM56980_A0fmt_fields, 14163 /* bits */ 23, 14164 /* flags */ 0, 14165 }, 14166 #endif /* chips */ 14167 14168 #if defined(BCM_56850_A0) || defined(BCM_56860_A0) 14169 { /* SOC_FORMAT_INT_EP2CXLP_IFfmt */ 14170 /* format EP2CXLP_IFfmt */ 14171 /* nFields */ 12, 14172 /* *fields */ soc_EP2CXLP_IFfmt_fields, 14173 /* bits */ 151, 14174 /* flags */ 0, 14175 }, 14176 #endif /* chips */ 14177 14178 #if defined(BCM_56370_A0) 14179 { /* SOC_FORMAT_INT_EP2CXLP_IF_BCM56370_A0fmt */ 14180 /* format EP2CXLP_IFfmt */ 14181 /* nFields */ 13, 14182 /* *fields */ soc_EP2CXLP_IF_BCM56870_A0fmt_fields, 14183 /* bits */ 152, 14184 /* flags */ 0, 14185 }, 14186 #endif /* chips */ 14187 14188 #if defined(BCM_56560_A0) 14189 { /* SOC_FORMAT_INT_EP2CXLP_IF_BCM56560_A0fmt */ 14190 /* format EP2CXLP_IFfmt */ 14191 /* nFields */ 12, 14192 /* *fields */ soc_EP2CXLP_IF_BCM56960_A0fmt_fields, 14193 /* bits */ 151, 14194 /* flags */ 0, 14195 }, 14196 #endif /* chips */ 14197 14198 #if defined(BCM_56560_B0) 14199 { /* SOC_FORMAT_INT_EP2CXLP_IF_BCM56560_B0fmt */ 14200 /* format EP2CXLP_IFfmt */ 14201 /* nFields */ 12, 14202 /* *fields */ soc_EP2CXLP_IF_BCM56960_A0fmt_fields, 14203 /* bits */ 151, 14204 /* flags */ 0, 14205 }, 14206 #endif /* chips */ 14207 14208 #if defined(BCM_56670_A0) 14209 { /* SOC_FORMAT_INT_EP2CXLP_IF_BCM56670_A0fmt */ 14210 /* format EP2CXLP_IFfmt */ 14211 /* nFields */ 12, 14212 /* *fields */ soc_EP2CXLP_IF_BCM56960_A0fmt_fields, 14213 /* bits */ 151, 14214 /* flags */ 0, 14215 }, 14216 #endif /* chips */ 14217 14218 #if defined(BCM_56670_B0) 14219 { /* SOC_FORMAT_INT_EP2CXLP_IF_BCM56670_B0fmt */ 14220 /* format EP2CXLP_IFfmt */ 14221 /* nFields */ 12, 14222 /* *fields */ soc_EP2CXLP_IF_BCM56960_A0fmt_fields, 14223 /* bits */ 151, 14224 /* flags */ 0, 14225 }, 14226 #endif /* chips */ 14227 14228 #if defined(BCM_56770_A0) 14229 { /* SOC_FORMAT_INT_EP2CXLP_IF_BCM56770_A0fmt */ 14230 /* format EP2CXLP_IFfmt */ 14231 /* nFields */ 13, 14232 /* *fields */ soc_EP2CXLP_IF_BCM56870_A0fmt_fields, 14233 /* bits */ 152, 14234 /* flags */ 0, 14235 }, 14236 #endif /* chips */ 14237 14238 #if defined(BCM_56870_A0) 14239 { /* SOC_FORMAT_INT_EP2CXLP_IF_BCM56870_A0fmt */ 14240 /* format EP2CXLP_IFfmt */ 14241 /* nFields */ 13, 14242 /* *fields */ soc_EP2CXLP_IF_BCM56870_A0fmt_fields, 14243 /* bits */ 152, 14244 /* flags */ 0, 14245 }, 14246 #endif /* chips */ 14247 14248 #if defined(BCM_56960_A0) 14249 { /* SOC_FORMAT_INT_EP2CXLP_IF_BCM56960_A0fmt */ 14250 /* format EP2CXLP_IFfmt */ 14251 /* nFields */ 12, 14252 /* *fields */ soc_EP2CXLP_IF_BCM56960_A0fmt_fields, 14253 /* bits */ 151, 14254 /* flags */ 0, 14255 }, 14256 #endif /* chips */ 14257 14258 #if defined(BCM_56965_A0) 14259 { /* SOC_FORMAT_INT_EP2CXLP_IF_BCM56965_A0fmt */ 14260 /* format EP2CXLP_IFfmt */ 14261 /* nFields */ 12, 14262 /* *fields */ soc_EP2CXLP_IF_BCM56960_A0fmt_fields, 14263 /* bits */ 151, 14264 /* flags */ 0, 14265 }, 14266 #endif /* chips */ 14267 14268 #if defined(BCM_56970_A0) 14269 { /* SOC_FORMAT_INT_EP2CXLP_IF_BCM56970_A0fmt */ 14270 /* format EP2CXLP_IFfmt */ 14271 /* nFields */ 12, 14272 /* *fields */ soc_EP2CXLP_IF_BCM56960_A0fmt_fields, 14273 /* bits */ 151, 14274 /* flags */ 0, 14275 }, 14276 #endif /* chips */ 14277 14278 #if defined(BCM_56980_A0) 14279 { /* SOC_FORMAT_INT_EP2CXLP_IF_BCM56980_A0fmt */ 14280 /* format EP2CXLP_IFfmt */ 14281 /* nFields */ 12, 14282 /* *fields */ soc_EP2CXLP_IF_BCM56960_A0fmt_fields, 14283 /* bits */ 151, 14284 /* flags */ 0, 14285 }, 14286 #endif /* chips */ 14287 14288 #if defined(BCM_56980_B0) 14289 { /* SOC_FORMAT_INT_EP2CXLP_IF_BCM56980_B0fmt */ 14290 /* format EP2CXLP_IFfmt */ 14291 /* nFields */ 12, 14292 /* *fields */ soc_EP2CXLP_IF_BCM56960_A0fmt_fields, 14293 /* bits */ 151, 14294 /* flags */ 0, 14295 }, 14296 #endif /* chips */ 14297 14298 #if defined(BCM_56370_A0) 14299 { /* SOC_FORMAT_INT_EPFS_0_DOPfmt */ 14300 /* format EPFS_0_DOPfmt */ 14301 /* nFields */ 6, 14302 /* *fields */ soc_EPFS_0_DOPfmt_fields, 14303 /* bits */ 96, 14304 /* flags */ 0, 14305 }, 14306 #endif /* chips */ 14307 14308 #if defined(BCM_56370_A0) 14309 { /* SOC_FORMAT_INT_EPFS_1_DOPfmt */ 14310 /* format EPFS_1_DOPfmt */ 14311 /* nFields */ 5, 14312 /* *fields */ soc_EL3_5_DOPfmt_fields, 14313 /* bits */ 32, 14314 /* flags */ 0, 14315 }, 14316 #endif /* chips */ 14317 14318 #if defined(BCM_56370_A0) 14319 { /* SOC_FORMAT_INT_EPFS_DOPfmt */ 14320 /* format EPFS_DOPfmt */ 14321 /* nFields */ 24, 14322 /* *fields */ soc_EPFS_DOPfmt_fields, 14323 /* bits */ 320, 14324 /* flags */ 0, 14325 }, 14326 #endif /* chips */ 14327 14328 #if defined(BCM_56370_A0) 14329 { /* SOC_FORMAT_INT_EPFS_EMOP_BUFFERfmt */ 14330 /* format EPFS_EMOP_BUFFERfmt */ 14331 /* nFields */ 2, 14332 /* *fields */ soc_EPFS_EMOP_BUFFERfmt_fields, 14333 /* bits */ 2, 14334 /* flags */ 0, 14335 }, 14336 #endif /* chips */ 14337 14338 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 14339 defined(BCM_56870_A0) 14340 { /* SOC_FORMAT_INT_EPMOD_0_DOPfmt */ 14341 /* format EPMOD_0_DOPfmt */ 14342 /* nFields */ 4, 14343 /* *fields */ soc_EPMOD_0_DOPfmt_fields, 14344 /* bits */ 32, 14345 /* flags */ 0, 14346 }, 14347 #endif /* chips */ 14348 14349 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 14350 defined(BCM_56870_A0) 14351 { /* SOC_FORMAT_INT_EPMOD_1_DOPfmt */ 14352 /* format EPMOD_1_DOPfmt */ 14353 /* nFields */ 9, 14354 /* *fields */ soc_EPMOD_1_DOPfmt_fields, 14355 /* bits */ 32, 14356 /* flags */ 0, 14357 }, 14358 #endif /* chips */ 14359 14360 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 14361 defined(BCM_56870_A0) 14362 { /* SOC_FORMAT_INT_EPMOD_DOPfmt */ 14363 /* format EPMOD_DOPfmt */ 14364 /* nFields */ 36, 14365 /* *fields */ soc_EPMOD_DOPfmt_fields, 14366 /* bits */ 544, 14367 /* flags */ 0, 14368 }, 14369 #endif /* chips */ 14370 14371 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \ 14372 defined(BCM_56270_A0) 14373 { /* SOC_FORMAT_INT_EPMOD_PARITY_STATUS_BUSfmt */ 14374 /* format EPMOD_PARITY_STATUS_BUSfmt */ 14375 /* nFields */ 5, 14376 /* *fields */ soc_EPMOD_PARITY_STATUS_BUSfmt_fields, 14377 /* bits */ 6, 14378 /* flags */ 0, 14379 }, 14380 #endif /* chips */ 14381 14382 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 14383 { /* SOC_FORMAT_INT_EPOST_EMOP_BUFFERfmt */ 14384 /* format EPOST_EMOP_BUFFERfmt */ 14385 /* nFields */ 16, 14386 /* *fields */ soc_EPOST_EMOP_BUFFERfmt_fields, 14387 /* bits */ 86, 14388 /* flags */ 0, 14389 }, 14390 #endif /* chips */ 14391 14392 #if defined(BCM_56850_A0) || defined(BCM_56860_A0) 14393 { /* SOC_FORMAT_INT_EPRG_FIELDSfmt */ 14394 /* format EPRG_FIELDSfmt */ 14395 /* nFields */ 1, 14396 /* *fields */ soc_EPRG_FIELDSfmt_fields, 14397 /* bits */ 49, 14398 /* flags */ 0, 14399 }, 14400 #endif /* chips */ 14401 14402 #if defined(BCM_56370_A0) 14403 { /* SOC_FORMAT_INT_EPRG_FIELDS_BCM56370_A0fmt */ 14404 /* format EPRG_FIELDSfmt */ 14405 /* nFields */ 1, 14406 /* *fields */ soc_EPRG_FIELDS_BCM56970_A0fmt_fields, 14407 /* bits */ 49, 14408 /* flags */ 0, 14409 }, 14410 #endif /* chips */ 14411 14412 #if defined(BCM_56560_A0) 14413 { /* SOC_FORMAT_INT_EPRG_FIELDS_BCM56560_A0fmt */ 14414 /* format EPRG_FIELDSfmt */ 14415 /* nFields */ 1, 14416 /* *fields */ soc_EPRG_FIELDS_BCM56560_A0fmt_fields, 14417 /* bits */ 49, 14418 /* flags */ 0, 14419 }, 14420 #endif /* chips */ 14421 14422 #if defined(BCM_56560_B0) 14423 { /* SOC_FORMAT_INT_EPRG_FIELDS_BCM56560_B0fmt */ 14424 /* format EPRG_FIELDSfmt */ 14425 /* nFields */ 1, 14426 /* *fields */ soc_EPRG_FIELDS_BCM56560_A0fmt_fields, 14427 /* bits */ 49, 14428 /* flags */ 0, 14429 }, 14430 #endif /* chips */ 14431 14432 #if defined(BCM_56670_A0) 14433 { /* SOC_FORMAT_INT_EPRG_FIELDS_BCM56670_A0fmt */ 14434 /* format EPRG_FIELDSfmt */ 14435 /* nFields */ 1, 14436 /* *fields */ soc_EPRG_FIELDS_BCM56560_A0fmt_fields, 14437 /* bits */ 49, 14438 /* flags */ 0, 14439 }, 14440 #endif /* chips */ 14441 14442 #if defined(BCM_56670_B0) 14443 { /* SOC_FORMAT_INT_EPRG_FIELDS_BCM56670_B0fmt */ 14444 /* format EPRG_FIELDSfmt */ 14445 /* nFields */ 1, 14446 /* *fields */ soc_EPRG_FIELDS_BCM56560_A0fmt_fields, 14447 /* bits */ 49, 14448 /* flags */ 0, 14449 }, 14450 #endif /* chips */ 14451 14452 #if defined(BCM_56770_A0) 14453 { /* SOC_FORMAT_INT_EPRG_FIELDS_BCM56770_A0fmt */ 14454 /* format EPRG_FIELDSfmt */ 14455 /* nFields */ 1, 14456 /* *fields */ soc_EPRG_FIELDS_BCM56970_A0fmt_fields, 14457 /* bits */ 49, 14458 /* flags */ 0, 14459 }, 14460 #endif /* chips */ 14461 14462 #if defined(BCM_56870_A0) 14463 { /* SOC_FORMAT_INT_EPRG_FIELDS_BCM56870_A0fmt */ 14464 /* format EPRG_FIELDSfmt */ 14465 /* nFields */ 1, 14466 /* *fields */ soc_EPRG_FIELDS_BCM56970_A0fmt_fields, 14467 /* bits */ 49, 14468 /* flags */ 0, 14469 }, 14470 #endif /* chips */ 14471 14472 #if defined(BCM_56960_A0) 14473 { /* SOC_FORMAT_INT_EPRG_FIELDS_BCM56960_A0fmt */ 14474 /* format EPRG_FIELDSfmt */ 14475 /* nFields */ 1, 14476 /* *fields */ soc_EPRG_FIELDS_BCM56960_A0fmt_fields, 14477 /* bits */ 47, 14478 /* flags */ 0, 14479 }, 14480 #endif /* chips */ 14481 14482 #if defined(BCM_56965_A0) 14483 { /* SOC_FORMAT_INT_EPRG_FIELDS_BCM56965_A0fmt */ 14484 /* format EPRG_FIELDSfmt */ 14485 /* nFields */ 1, 14486 /* *fields */ soc_EPRG_FIELDS_BCM56960_A0fmt_fields, 14487 /* bits */ 47, 14488 /* flags */ 0, 14489 }, 14490 #endif /* chips */ 14491 14492 #if defined(BCM_56970_A0) 14493 { /* SOC_FORMAT_INT_EPRG_FIELDS_BCM56970_A0fmt */ 14494 /* format EPRG_FIELDSfmt */ 14495 /* nFields */ 1, 14496 /* *fields */ soc_EPRG_FIELDS_BCM56970_A0fmt_fields, 14497 /* bits */ 49, 14498 /* flags */ 0, 14499 }, 14500 #endif /* chips */ 14501 14502 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 14503 defined(BCM_56870_A0) 14504 { /* SOC_FORMAT_INT_EP_CPU_OPfmt */ 14505 /* format EP_CPU_OPfmt */ 14506 /* nFields */ 9, 14507 /* *fields */ soc_EP_CPU_OPfmt_fields, 14508 /* bits */ 680, 14509 /* flags */ 0, 14510 }, 14511 #endif /* chips */ 14512 14513 #if defined(BCM_56440_B0) || defined(BCM_56524_A0) || \ 14514 defined(BCM_56524_B0) || defined(BCM_56634_A0) || \ 14515 defined(BCM_56634_B0) || defined(BCM_56685_B0) || \ 14516 defined(BCM_56840_B0) 14517 { /* SOC_FORMAT_INT_EP_CPU_OPCODESfmt */ 14518 /* format EP_CPU_OPCODESfmt */ 14519 /* nFields */ 13, 14520 /* *fields */ soc_EP_CPU_OPCODESfmt_fields, 14521 /* bits */ 13, 14522 /* flags */ 0, 14523 }, 14524 #endif /* chips */ 14525 14526 #if defined(BCM_56260_A0) 14527 { /* SOC_FORMAT_INT_EP_CPU_OPCODES_BCM56260_A0fmt */ 14528 /* format EP_CPU_OPCODESfmt */ 14529 /* nFields */ 23, 14530 /* *fields */ soc_EP_CPU_OPCODES_BCM56260_A0fmt_fields, 14531 /* bits */ 20, 14532 /* flags */ 0, 14533 }, 14534 #endif /* chips */ 14535 14536 #if defined(BCM_56260_B0) 14537 { /* SOC_FORMAT_INT_EP_CPU_OPCODES_BCM56260_B0fmt */ 14538 /* format EP_CPU_OPCODESfmt */ 14539 /* nFields */ 23, 14540 /* *fields */ soc_EP_CPU_OPCODES_BCM56260_A0fmt_fields, 14541 /* bits */ 20, 14542 /* flags */ 0, 14543 }, 14544 #endif /* chips */ 14545 14546 #if defined(BCM_56270_A0) 14547 { /* SOC_FORMAT_INT_EP_CPU_OPCODES_BCM56270_A0fmt */ 14548 /* format EP_CPU_OPCODESfmt */ 14549 /* nFields */ 23, 14550 /* *fields */ soc_EP_CPU_OPCODES_BCM56260_A0fmt_fields, 14551 /* bits */ 20, 14552 /* flags */ 0, 14553 }, 14554 #endif /* chips */ 14555 14556 #if defined(BCM_56340_A0) 14557 { /* SOC_FORMAT_INT_EP_CPU_OPCODES_BCM56340_A0fmt */ 14558 /* format EP_CPU_OPCODESfmt */ 14559 /* nFields */ 16, 14560 /* *fields */ soc_EP_CPU_OPCODES_BCM56640_A0fmt_fields, 14561 /* bits */ 20, 14562 /* flags */ 0, 14563 }, 14564 #endif /* chips */ 14565 14566 #if defined(BCM_56370_A0) 14567 { /* SOC_FORMAT_INT_EP_CPU_OPCODES_BCM56370_A0fmt */ 14568 /* format EP_CPU_OPCODESfmt */ 14569 /* nFields */ 11, 14570 /* *fields */ soc_EP_CPU_OPCODES_BCM56960_A0fmt_fields, 14571 /* bits */ 11, 14572 /* flags */ 0, 14573 }, 14574 #endif /* chips */ 14575 14576 #if defined(BCM_56440_A0) 14577 { /* SOC_FORMAT_INT_EP_CPU_OPCODES_BCM56440_A0fmt */ 14578 /* format EP_CPU_OPCODESfmt */ 14579 /* nFields */ 13, 14580 /* *fields */ soc_EP_CPU_OPCODESfmt_fields, 14581 /* bits */ 13, 14582 /* flags */ 0, 14583 }, 14584 #endif /* chips */ 14585 14586 #if defined(BCM_56450_A0) 14587 { /* SOC_FORMAT_INT_EP_CPU_OPCODES_BCM56450_A0fmt */ 14588 /* format EP_CPU_OPCODESfmt */ 14589 /* nFields */ 20, 14590 /* *fields */ soc_EP_CPU_OPCODES_BCM56450_A0fmt_fields, 14591 /* bits */ 20, 14592 /* flags */ 0, 14593 }, 14594 #endif /* chips */ 14595 14596 #if defined(BCM_56450_B0) 14597 { /* SOC_FORMAT_INT_EP_CPU_OPCODES_BCM56450_B0fmt */ 14598 /* format EP_CPU_OPCODESfmt */ 14599 /* nFields */ 20, 14600 /* *fields */ soc_EP_CPU_OPCODES_BCM56450_A0fmt_fields, 14601 /* bits */ 20, 14602 /* flags */ 0, 14603 }, 14604 #endif /* chips */ 14605 14606 #if defined(BCM_56450_B1) 14607 { /* SOC_FORMAT_INT_EP_CPU_OPCODES_BCM56450_B1fmt */ 14608 /* format EP_CPU_OPCODESfmt */ 14609 /* nFields */ 20, 14610 /* *fields */ soc_EP_CPU_OPCODES_BCM56450_A0fmt_fields, 14611 /* bits */ 20, 14612 /* flags */ 0, 14613 }, 14614 #endif /* chips */ 14615 14616 #if defined(BCM_56560_A0) 14617 { /* SOC_FORMAT_INT_EP_CPU_OPCODES_BCM56560_A0fmt */ 14618 /* format EP_CPU_OPCODESfmt */ 14619 /* nFields */ 22, 14620 /* *fields */ soc_EP_CPU_OPCODES_BCM56560_A0fmt_fields, 14621 /* bits */ 22, 14622 /* flags */ 0, 14623 }, 14624 #endif /* chips */ 14625 14626 #if defined(BCM_56560_B0) 14627 { /* SOC_FORMAT_INT_EP_CPU_OPCODES_BCM56560_B0fmt */ 14628 /* format EP_CPU_OPCODESfmt */ 14629 /* nFields */ 22, 14630 /* *fields */ soc_EP_CPU_OPCODES_BCM56560_A0fmt_fields, 14631 /* bits */ 22, 14632 /* flags */ 0, 14633 }, 14634 #endif /* chips */ 14635 14636 #if defined(BCM_56640_A0) 14637 { /* SOC_FORMAT_INT_EP_CPU_OPCODES_BCM56640_A0fmt */ 14638 /* format EP_CPU_OPCODESfmt */ 14639 /* nFields */ 16, 14640 /* *fields */ soc_EP_CPU_OPCODES_BCM56640_A0fmt_fields, 14641 /* bits */ 20, 14642 /* flags */ 0, 14643 }, 14644 #endif /* chips */ 14645 14646 #if defined(BCM_56670_A0) 14647 { /* SOC_FORMAT_INT_EP_CPU_OPCODES_BCM56670_A0fmt */ 14648 /* format EP_CPU_OPCODESfmt */ 14649 /* nFields */ 22, 14650 /* *fields */ soc_EP_CPU_OPCODES_BCM56560_A0fmt_fields, 14651 /* bits */ 22, 14652 /* flags */ 0, 14653 }, 14654 #endif /* chips */ 14655 14656 #if defined(BCM_56670_B0) 14657 { /* SOC_FORMAT_INT_EP_CPU_OPCODES_BCM56670_B0fmt */ 14658 /* format EP_CPU_OPCODESfmt */ 14659 /* nFields */ 22, 14660 /* *fields */ soc_EP_CPU_OPCODES_BCM56560_A0fmt_fields, 14661 /* bits */ 22, 14662 /* flags */ 0, 14663 }, 14664 #endif /* chips */ 14665 14666 #if defined(BCM_56685_A0) 14667 { /* SOC_FORMAT_INT_EP_CPU_OPCODES_BCM56685_A0fmt */ 14668 /* format EP_CPU_OPCODESfmt */ 14669 /* nFields */ 13, 14670 /* *fields */ soc_EP_CPU_OPCODESfmt_fields, 14671 /* bits */ 13, 14672 /* flags */ 0, 14673 }, 14674 #endif /* chips */ 14675 14676 #if defined(BCM_56770_A0) 14677 { /* SOC_FORMAT_INT_EP_CPU_OPCODES_BCM56770_A0fmt */ 14678 /* format EP_CPU_OPCODESfmt */ 14679 /* nFields */ 11, 14680 /* *fields */ soc_EP_CPU_OPCODES_BCM56960_A0fmt_fields, 14681 /* bits */ 11, 14682 /* flags */ 0, 14683 }, 14684 #endif /* chips */ 14685 14686 #if defined(BCM_56840_A0) 14687 { /* SOC_FORMAT_INT_EP_CPU_OPCODES_BCM56840_A0fmt */ 14688 /* format EP_CPU_OPCODESfmt */ 14689 /* nFields */ 13, 14690 /* *fields */ soc_EP_CPU_OPCODESfmt_fields, 14691 /* bits */ 13, 14692 /* flags */ 0, 14693 }, 14694 #endif /* chips */ 14695 14696 #if defined(BCM_56850_A0) 14697 { /* SOC_FORMAT_INT_EP_CPU_OPCODES_BCM56850_A0fmt */ 14698 /* format EP_CPU_OPCODESfmt */ 14699 /* nFields */ 11, 14700 /* *fields */ soc_EP_CPU_OPCODES_BCM56850_A0fmt_fields, 14701 /* bits */ 11, 14702 /* flags */ 0, 14703 }, 14704 #endif /* chips */ 14705 14706 #if defined(BCM_56860_A0) 14707 { /* SOC_FORMAT_INT_EP_CPU_OPCODES_BCM56860_A0fmt */ 14708 /* format EP_CPU_OPCODESfmt */ 14709 /* nFields */ 11, 14710 /* *fields */ soc_EP_CPU_OPCODES_BCM56850_A0fmt_fields, 14711 /* bits */ 11, 14712 /* flags */ 0, 14713 }, 14714 #endif /* chips */ 14715 14716 #if defined(BCM_56870_A0) 14717 { /* SOC_FORMAT_INT_EP_CPU_OPCODES_BCM56870_A0fmt */ 14718 /* format EP_CPU_OPCODESfmt */ 14719 /* nFields */ 11, 14720 /* *fields */ soc_EP_CPU_OPCODES_BCM56960_A0fmt_fields, 14721 /* bits */ 11, 14722 /* flags */ 0, 14723 }, 14724 #endif /* chips */ 14725 14726 #if defined(BCM_56960_A0) 14727 { /* SOC_FORMAT_INT_EP_CPU_OPCODES_BCM56960_A0fmt */ 14728 /* format EP_CPU_OPCODESfmt */ 14729 /* nFields */ 11, 14730 /* *fields */ soc_EP_CPU_OPCODES_BCM56960_A0fmt_fields, 14731 /* bits */ 11, 14732 /* flags */ 0, 14733 }, 14734 #endif /* chips */ 14735 14736 #if defined(BCM_56965_A0) 14737 { /* SOC_FORMAT_INT_EP_CPU_OPCODES_BCM56965_A0fmt */ 14738 /* format EP_CPU_OPCODESfmt */ 14739 /* nFields */ 11, 14740 /* *fields */ soc_EP_CPU_OPCODES_BCM56960_A0fmt_fields, 14741 /* bits */ 11, 14742 /* flags */ 0, 14743 }, 14744 #endif /* chips */ 14745 14746 #if defined(BCM_56970_A0) 14747 { /* SOC_FORMAT_INT_EP_CPU_OPCODES_BCM56970_A0fmt */ 14748 /* format EP_CPU_OPCODESfmt */ 14749 /* nFields */ 11, 14750 /* *fields */ soc_EP_CPU_OPCODES_BCM56960_A0fmt_fields, 14751 /* bits */ 11, 14752 /* flags */ 0, 14753 }, 14754 #endif /* chips */ 14755 14756 #if defined(BCM_56980_A0) 14757 { /* SOC_FORMAT_INT_EP_CPU_OPCODES_BCM56980_A0fmt */ 14758 /* format EP_CPU_OPCODESfmt */ 14759 /* nFields */ 11, 14760 /* *fields */ soc_EP_CPU_OPCODES_BCM56960_A0fmt_fields, 14761 /* bits */ 11, 14762 /* flags */ 0, 14763 }, 14764 #endif /* chips */ 14765 14766 #if defined(BCM_56980_B0) 14767 { /* SOC_FORMAT_INT_EP_CPU_OPCODES_BCM56980_B0fmt */ 14768 /* format EP_CPU_OPCODESfmt */ 14769 /* nFields */ 11, 14770 /* *fields */ soc_EP_CPU_OPCODES_BCM56960_A0fmt_fields, 14771 /* bits */ 11, 14772 /* flags */ 0, 14773 }, 14774 #endif /* chips */ 14775 14776 #if defined(BCM_56980_A0) 14777 { /* SOC_FORMAT_INT_EP_CPU_OP_BCM56980_A0fmt */ 14778 /* format EP_CPU_OPfmt */ 14779 /* nFields */ 9, 14780 /* *fields */ soc_EP_CPU_OP_BCM56980_A0fmt_fields, 14781 /* bits */ 552, 14782 /* flags */ 0, 14783 }, 14784 #endif /* chips */ 14785 14786 #if defined(BCM_56980_B0) 14787 { /* SOC_FORMAT_INT_EP_CPU_OP_BCM56980_B0fmt */ 14788 /* format EP_CPU_OPfmt */ 14789 /* nFields */ 9, 14790 /* *fields */ soc_EP_CPU_OP_BCM56980_A0fmt_fields, 14791 /* bits */ 552, 14792 /* flags */ 0, 14793 }, 14794 #endif /* chips */ 14795 14796 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 14797 defined(BCM_56870_A0) 14798 { /* SOC_FORMAT_INT_EP_EFPPARS_CONTAINER_BASEfmt */ 14799 /* format EP_EFPPARS_CONTAINER_BASEfmt */ 14800 /* nFields */ 3, 14801 /* *fields */ soc_EP_EFPPARS_CONTAINER_BASEfmt_fields, 14802 /* bits */ 13, 14803 /* flags */ 0, 14804 }, 14805 #endif /* chips */ 14806 14807 #if defined(BCM_56340_A0) || defined(BCM_56640_A0) 14808 { /* SOC_FORMAT_INT_EP_EGRESS_STATS_COUNTER_COV_DEFSfmt */ 14809 /* format EP_EGRESS_STATS_COUNTER_COV_DEFSfmt */ 14810 /* nFields */ 6, 14811 /* *fields */ soc_EP_EGRESS_STATS_COUNTER_COV_DEFSfmt_fields, 14812 /* bits */ 12, 14813 /* flags */ 0, 14814 }, 14815 #endif /* chips */ 14816 14817 #if defined(BCM_53400_A0) 14818 { /* SOC_FORMAT_INT_EP_EGRESS_STATS_COUNTER_COV_DEFS_BCM53400_A0fmt */ 14819 /* format EP_EGRESS_STATS_COUNTER_COV_DEFSfmt */ 14820 /* nFields */ 6, 14821 /* *fields */ soc_EP_EGRESS_STATS_COUNTER_COV_DEFS_BCM53400_A0fmt_fields, 14822 /* bits */ 11, 14823 /* flags */ 0, 14824 }, 14825 #endif /* chips */ 14826 14827 #if defined(BCM_53540_A0) 14828 { /* SOC_FORMAT_INT_EP_EGRESS_STATS_COUNTER_COV_DEFS_BCM53540_A0fmt */ 14829 /* format EP_EGRESS_STATS_COUNTER_COV_DEFSfmt */ 14830 /* nFields */ 6, 14831 /* *fields */ soc_EP_EGRESS_STATS_COUNTER_COV_DEFS_BCM53400_A0fmt_fields, 14832 /* bits */ 11, 14833 /* flags */ 0, 14834 }, 14835 #endif /* chips */ 14836 14837 #if defined(BCM_53570_A0) 14838 { /* SOC_FORMAT_INT_EP_EGRESS_STATS_COUNTER_COV_DEFS_BCM53570_A0fmt */ 14839 /* format EP_EGRESS_STATS_COUNTER_COV_DEFSfmt */ 14840 /* nFields */ 6, 14841 /* *fields */ soc_EP_EGRESS_STATS_COUNTER_COV_DEFS_BCM53400_A0fmt_fields, 14842 /* bits */ 11, 14843 /* flags */ 0, 14844 }, 14845 #endif /* chips */ 14846 14847 #if defined(BCM_53570_B0) 14848 { /* SOC_FORMAT_INT_EP_EGRESS_STATS_COUNTER_COV_DEFS_BCM53570_B0fmt */ 14849 /* format EP_EGRESS_STATS_COUNTER_COV_DEFSfmt */ 14850 /* nFields */ 6, 14851 /* *fields */ soc_EP_EGRESS_STATS_COUNTER_COV_DEFS_BCM53400_A0fmt_fields, 14852 /* bits */ 11, 14853 /* flags */ 0, 14854 }, 14855 #endif /* chips */ 14856 14857 #if defined(BCM_56150_A0) 14858 { /* SOC_FORMAT_INT_EP_EGRESS_STATS_COUNTER_COV_DEFS_BCM56150_A0fmt */ 14859 /* format EP_EGRESS_STATS_COUNTER_COV_DEFSfmt */ 14860 /* nFields */ 6, 14861 /* *fields */ soc_EP_EGRESS_STATS_COUNTER_COV_DEFS_BCM56150_A0fmt_fields, 14862 /* bits */ 11, 14863 /* flags */ 0, 14864 }, 14865 #endif /* chips */ 14866 14867 #if defined(BCM_56160_A0) 14868 { /* SOC_FORMAT_INT_EP_EGRESS_STATS_COUNTER_COV_DEFS_BCM56160_A0fmt */ 14869 /* format EP_EGRESS_STATS_COUNTER_COV_DEFSfmt */ 14870 /* nFields */ 6, 14871 /* *fields */ soc_EP_EGRESS_STATS_COUNTER_COV_DEFS_BCM53400_A0fmt_fields, 14872 /* bits */ 11, 14873 /* flags */ 0, 14874 }, 14875 #endif /* chips */ 14876 14877 #if defined(BCM_56370_A0) 14878 { /* SOC_FORMAT_INT_EP_EGRESS_STATS_COUNTER_COV_DEFS_BCM56370_A0fmt */ 14879 /* format EP_EGRESS_STATS_COUNTER_COV_DEFSfmt */ 14880 /* nFields */ 6, 14881 /* *fields */ soc_EGR_FCOE_DELIMITER_ERROR_FRAMES_TABLE_COV_DEFS_BCM56960_A0fmt_fields, 14882 /* bits */ 13, 14883 /* flags */ 0, 14884 }, 14885 #endif /* chips */ 14886 14887 #if defined(BCM_56560_A0) 14888 { /* SOC_FORMAT_INT_EP_EGRESS_STATS_COUNTER_COV_DEFS_BCM56560_A0fmt */ 14889 /* format EP_EGRESS_STATS_COUNTER_COV_DEFSfmt */ 14890 /* nFields */ 6, 14891 /* *fields */ soc_EGR_FCOE_DELIMITER_ERROR_FRAMES_TABLE_COV_DEFS_BCM56960_A0fmt_fields, 14892 /* bits */ 13, 14893 /* flags */ 0, 14894 }, 14895 #endif /* chips */ 14896 14897 #if defined(BCM_56560_B0) 14898 { /* SOC_FORMAT_INT_EP_EGRESS_STATS_COUNTER_COV_DEFS_BCM56560_B0fmt */ 14899 /* format EP_EGRESS_STATS_COUNTER_COV_DEFSfmt */ 14900 /* nFields */ 6, 14901 /* *fields */ soc_EGR_FCOE_DELIMITER_ERROR_FRAMES_TABLE_COV_DEFS_BCM56960_A0fmt_fields, 14902 /* bits */ 13, 14903 /* flags */ 0, 14904 }, 14905 #endif /* chips */ 14906 14907 #if defined(BCM_56670_A0) 14908 { /* SOC_FORMAT_INT_EP_EGRESS_STATS_COUNTER_COV_DEFS_BCM56670_A0fmt */ 14909 /* format EP_EGRESS_STATS_COUNTER_COV_DEFSfmt */ 14910 /* nFields */ 6, 14911 /* *fields */ soc_EGR_FCOE_DELIMITER_ERROR_FRAMES_TABLE_COV_DEFS_BCM56960_A0fmt_fields, 14912 /* bits */ 13, 14913 /* flags */ 0, 14914 }, 14915 #endif /* chips */ 14916 14917 #if defined(BCM_56670_B0) 14918 { /* SOC_FORMAT_INT_EP_EGRESS_STATS_COUNTER_COV_DEFS_BCM56670_B0fmt */ 14919 /* format EP_EGRESS_STATS_COUNTER_COV_DEFSfmt */ 14920 /* nFields */ 6, 14921 /* *fields */ soc_EGR_FCOE_DELIMITER_ERROR_FRAMES_TABLE_COV_DEFS_BCM56960_A0fmt_fields, 14922 /* bits */ 13, 14923 /* flags */ 0, 14924 }, 14925 #endif /* chips */ 14926 14927 #if defined(BCM_56770_A0) 14928 { /* SOC_FORMAT_INT_EP_EGRESS_STATS_COUNTER_COV_DEFS_BCM56770_A0fmt */ 14929 /* format EP_EGRESS_STATS_COUNTER_COV_DEFSfmt */ 14930 /* nFields */ 6, 14931 /* *fields */ soc_EGR_FCOE_DELIMITER_ERROR_FRAMES_TABLE_COV_DEFS_BCM56960_A0fmt_fields, 14932 /* bits */ 13, 14933 /* flags */ 0, 14934 }, 14935 #endif /* chips */ 14936 14937 #if defined(BCM_56850_A0) 14938 { /* SOC_FORMAT_INT_EP_EGRESS_STATS_COUNTER_COV_DEFS_BCM56850_A0fmt */ 14939 /* format EP_EGRESS_STATS_COUNTER_COV_DEFSfmt */ 14940 /* nFields */ 6, 14941 /* *fields */ soc_EGR_FCOE_DELIMITER_ERROR_FRAMES_TABLE_COV_DEFSfmt_fields, 14942 /* bits */ 13, 14943 /* flags */ 0, 14944 }, 14945 #endif /* chips */ 14946 14947 #if defined(BCM_56860_A0) 14948 { /* SOC_FORMAT_INT_EP_EGRESS_STATS_COUNTER_COV_DEFS_BCM56860_A0fmt */ 14949 /* format EP_EGRESS_STATS_COUNTER_COV_DEFSfmt */ 14950 /* nFields */ 6, 14951 /* *fields */ soc_EGR_FCOE_DELIMITER_ERROR_FRAMES_TABLE_COV_DEFSfmt_fields, 14952 /* bits */ 13, 14953 /* flags */ 0, 14954 }, 14955 #endif /* chips */ 14956 14957 #if defined(BCM_56870_A0) 14958 { /* SOC_FORMAT_INT_EP_EGRESS_STATS_COUNTER_COV_DEFS_BCM56870_A0fmt */ 14959 /* format EP_EGRESS_STATS_COUNTER_COV_DEFSfmt */ 14960 /* nFields */ 6, 14961 /* *fields */ soc_EGR_FCOE_DELIMITER_ERROR_FRAMES_TABLE_COV_DEFS_BCM56960_A0fmt_fields, 14962 /* bits */ 13, 14963 /* flags */ 0, 14964 }, 14965 #endif /* chips */ 14966 14967 #if defined(BCM_56960_A0) 14968 { /* SOC_FORMAT_INT_EP_EGRESS_STATS_COUNTER_COV_DEFS_BCM56960_A0fmt */ 14969 /* format EP_EGRESS_STATS_COUNTER_COV_DEFSfmt */ 14970 /* nFields */ 6, 14971 /* *fields */ soc_EGR_FCOE_DELIMITER_ERROR_FRAMES_TABLE_COV_DEFS_BCM56960_A0fmt_fields, 14972 /* bits */ 13, 14973 /* flags */ 0, 14974 }, 14975 #endif /* chips */ 14976 14977 #if defined(BCM_56965_A0) 14978 { /* SOC_FORMAT_INT_EP_EGRESS_STATS_COUNTER_COV_DEFS_BCM56965_A0fmt */ 14979 /* format EP_EGRESS_STATS_COUNTER_COV_DEFSfmt */ 14980 /* nFields */ 6, 14981 /* *fields */ soc_EGR_FCOE_DELIMITER_ERROR_FRAMES_TABLE_COV_DEFS_BCM56960_A0fmt_fields, 14982 /* bits */ 13, 14983 /* flags */ 0, 14984 }, 14985 #endif /* chips */ 14986 14987 #if defined(BCM_56970_A0) 14988 { /* SOC_FORMAT_INT_EP_EGRESS_STATS_COUNTER_COV_DEFS_BCM56970_A0fmt */ 14989 /* format EP_EGRESS_STATS_COUNTER_COV_DEFSfmt */ 14990 /* nFields */ 6, 14991 /* *fields */ soc_EGR_FCOE_DELIMITER_ERROR_FRAMES_TABLE_COV_DEFS_BCM56960_A0fmt_fields, 14992 /* bits */ 13, 14993 /* flags */ 0, 14994 }, 14995 #endif /* chips */ 14996 14997 #if defined(BCM_56980_A0) 14998 { /* SOC_FORMAT_INT_EP_EGRESS_STATS_COUNTER_COV_DEFS_BCM56980_A0fmt */ 14999 /* format EP_EGRESS_STATS_COUNTER_COV_DEFSfmt */ 15000 /* nFields */ 6, 15001 /* *fields */ soc_EGR_FCOE_DELIMITER_ERROR_FRAMES_TABLE_COV_DEFS_BCM56960_A0fmt_fields, 15002 /* bits */ 13, 15003 /* flags */ 0, 15004 }, 15005 #endif /* chips */ 15006 15007 #if defined(BCM_56980_B0) 15008 { /* SOC_FORMAT_INT_EP_EGRESS_STATS_COUNTER_COV_DEFS_BCM56980_B0fmt */ 15009 /* format EP_EGRESS_STATS_COUNTER_COV_DEFSfmt */ 15010 /* nFields */ 6, 15011 /* *fields */ soc_EGR_FCOE_DELIMITER_ERROR_FRAMES_TABLE_COV_DEFS_BCM56960_A0fmt_fields, 15012 /* bits */ 13, 15013 /* flags */ 0, 15014 }, 15015 #endif /* chips */ 15016 15017 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 15018 { /* SOC_FORMAT_INT_EP_EGR_COUNTER_VECTORfmt */ 15019 /* format EP_EGR_COUNTER_VECTORfmt */ 15020 /* nFields */ 19, 15021 /* *fields */ soc_EP_EGR_COUNTER_VECTORfmt_fields, 15022 /* bits */ 19, 15023 /* flags */ 0, 15024 }, 15025 #endif /* chips */ 15026 15027 #if defined(BCM_56850_A0) 15028 { /* SOC_FORMAT_INT_EP_EGR_DROP_VECTORfmt */ 15029 /* format EP_EGR_DROP_VECTORfmt */ 15030 /* nFields */ 31, 15031 /* *fields */ soc_EP_EGR_DROP_VECTORfmt_fields, 15032 /* bits */ 32, 15033 /* flags */ 0, 15034 }, 15035 #endif /* chips */ 15036 15037 #if defined(BCM_56370_A0) 15038 { /* SOC_FORMAT_INT_EP_EGR_DROP_VECTOR_BCM56370_A0fmt */ 15039 /* format EP_EGR_DROP_VECTORfmt */ 15040 /* nFields */ 34, 15041 /* *fields */ soc_EP_EGR_DROP_VECTOR_BCM56870_A0fmt_fields, 15042 /* bits */ 35, 15043 /* flags */ 0, 15044 }, 15045 #endif /* chips */ 15046 15047 #if defined(BCM_56560_A0) 15048 { /* SOC_FORMAT_INT_EP_EGR_DROP_VECTOR_BCM56560_A0fmt */ 15049 /* format EP_EGR_DROP_VECTORfmt */ 15050 /* nFields */ 32, 15051 /* *fields */ soc_EP_EGR_DROP_VECTOR_BCM56560_A0fmt_fields, 15052 /* bits */ 33, 15053 /* flags */ 0, 15054 }, 15055 #endif /* chips */ 15056 15057 #if defined(BCM_56560_B0) 15058 { /* SOC_FORMAT_INT_EP_EGR_DROP_VECTOR_BCM56560_B0fmt */ 15059 /* format EP_EGR_DROP_VECTORfmt */ 15060 /* nFields */ 32, 15061 /* *fields */ soc_EP_EGR_DROP_VECTOR_BCM56560_A0fmt_fields, 15062 /* bits */ 33, 15063 /* flags */ 0, 15064 }, 15065 #endif /* chips */ 15066 15067 #if defined(BCM_56670_A0) 15068 { /* SOC_FORMAT_INT_EP_EGR_DROP_VECTOR_BCM56670_A0fmt */ 15069 /* format EP_EGR_DROP_VECTORfmt */ 15070 /* nFields */ 32, 15071 /* *fields */ soc_EP_EGR_DROP_VECTOR_BCM56560_A0fmt_fields, 15072 /* bits */ 33, 15073 /* flags */ 0, 15074 }, 15075 #endif /* chips */ 15076 15077 #if defined(BCM_56670_B0) 15078 { /* SOC_FORMAT_INT_EP_EGR_DROP_VECTOR_BCM56670_B0fmt */ 15079 /* format EP_EGR_DROP_VECTORfmt */ 15080 /* nFields */ 32, 15081 /* *fields */ soc_EP_EGR_DROP_VECTOR_BCM56560_A0fmt_fields, 15082 /* bits */ 33, 15083 /* flags */ 0, 15084 }, 15085 #endif /* chips */ 15086 15087 #if defined(BCM_56770_A0) 15088 { /* SOC_FORMAT_INT_EP_EGR_DROP_VECTOR_BCM56770_A0fmt */ 15089 /* format EP_EGR_DROP_VECTORfmt */ 15090 /* nFields */ 34, 15091 /* *fields */ soc_EP_EGR_DROP_VECTOR_BCM56870_A0fmt_fields, 15092 /* bits */ 35, 15093 /* flags */ 0, 15094 }, 15095 #endif /* chips */ 15096 15097 #if defined(BCM_56860_A0) 15098 { /* SOC_FORMAT_INT_EP_EGR_DROP_VECTOR_BCM56860_A0fmt */ 15099 /* format EP_EGR_DROP_VECTORfmt */ 15100 /* nFields */ 31, 15101 /* *fields */ soc_EP_EGR_DROP_VECTOR_BCM56860_A0fmt_fields, 15102 /* bits */ 32, 15103 /* flags */ 0, 15104 }, 15105 #endif /* chips */ 15106 15107 #if defined(BCM_56870_A0) 15108 { /* SOC_FORMAT_INT_EP_EGR_DROP_VECTOR_BCM56870_A0fmt */ 15109 /* format EP_EGR_DROP_VECTORfmt */ 15110 /* nFields */ 34, 15111 /* *fields */ soc_EP_EGR_DROP_VECTOR_BCM56870_A0fmt_fields, 15112 /* bits */ 35, 15113 /* flags */ 0, 15114 }, 15115 #endif /* chips */ 15116 15117 #if defined(BCM_56960_A0) 15118 { /* SOC_FORMAT_INT_EP_EGR_DROP_VECTOR_BCM56960_A0fmt */ 15119 /* format EP_EGR_DROP_VECTORfmt */ 15120 /* nFields */ 29, 15121 /* *fields */ soc_EP_EGR_DROP_VECTOR_BCM56960_A0fmt_fields, 15122 /* bits */ 30, 15123 /* flags */ 0, 15124 }, 15125 #endif /* chips */ 15126 15127 #if defined(BCM_56965_A0) 15128 { /* SOC_FORMAT_INT_EP_EGR_DROP_VECTOR_BCM56965_A0fmt */ 15129 /* format EP_EGR_DROP_VECTORfmt */ 15130 /* nFields */ 29, 15131 /* *fields */ soc_EP_EGR_DROP_VECTOR_BCM56960_A0fmt_fields, 15132 /* bits */ 30, 15133 /* flags */ 0, 15134 }, 15135 #endif /* chips */ 15136 15137 #if defined(BCM_56970_A0) 15138 { /* SOC_FORMAT_INT_EP_EGR_DROP_VECTOR_BCM56970_A0fmt */ 15139 /* format EP_EGR_DROP_VECTORfmt */ 15140 /* nFields */ 30, 15141 /* *fields */ soc_EP_EGR_DROP_VECTOR_BCM56970_A0fmt_fields, 15142 /* bits */ 31, 15143 /* flags */ 0, 15144 }, 15145 #endif /* chips */ 15146 15147 #if defined(BCM_56980_A0) 15148 { /* SOC_FORMAT_INT_EP_EGR_DROP_VECTOR_BCM56980_A0fmt */ 15149 /* format EP_EGR_DROP_VECTORfmt */ 15150 /* nFields */ 31, 15151 /* *fields */ soc_EP_EGR_DROP_VECTOR_BCM56980_A0fmt_fields, 15152 /* bits */ 31, 15153 /* flags */ 0, 15154 }, 15155 #endif /* chips */ 15156 15157 #if defined(BCM_56980_B0) 15158 { /* SOC_FORMAT_INT_EP_EGR_DROP_VECTOR_BCM56980_B0fmt */ 15159 /* format EP_EGR_DROP_VECTORfmt */ 15160 /* nFields */ 31, 15161 /* *fields */ soc_EP_EGR_DROP_VECTOR_BCM56980_A0fmt_fields, 15162 /* bits */ 31, 15163 /* flags */ 0, 15164 }, 15165 #endif /* chips */ 15166 15167 #if defined(BCM_56142_A0) 15168 { /* SOC_FORMAT_INT_EP_EVXLT_KEY_TYPEfmt */ 15169 /* format EP_EVXLT_KEY_TYPEfmt */ 15170 /* nFields */ 17, 15171 /* *fields */ soc_EP_EVXLT_KEY_TYPEfmt_fields, 15172 /* bits */ 40, 15173 /* flags */ 0, 15174 }, 15175 #endif /* chips */ 15176 15177 #if defined(BCM_53400_A0) 15178 { /* SOC_FORMAT_INT_EP_EVXLT_KEY_TYPE_BCM53400_A0fmt */ 15179 /* format EP_EVXLT_KEY_TYPEfmt */ 15180 /* nFields */ 17, 15181 /* *fields */ soc_EP_EVXLT_KEY_TYPE_BCM53400_A0fmt_fields, 15182 /* bits */ 40, 15183 /* flags */ 0, 15184 }, 15185 #endif /* chips */ 15186 15187 #if defined(BCM_53540_A0) 15188 { /* SOC_FORMAT_INT_EP_EVXLT_KEY_TYPE_BCM53540_A0fmt */ 15189 /* format EP_EVXLT_KEY_TYPEfmt */ 15190 /* nFields */ 17, 15191 /* *fields */ soc_EP_EVXLT_KEY_TYPE_BCM56160_A0fmt_fields, 15192 /* bits */ 41, 15193 /* flags */ 0, 15194 }, 15195 #endif /* chips */ 15196 15197 #if defined(BCM_53570_A0) 15198 { /* SOC_FORMAT_INT_EP_EVXLT_KEY_TYPE_BCM53570_A0fmt */ 15199 /* format EP_EVXLT_KEY_TYPEfmt */ 15200 /* nFields */ 17, 15201 /* *fields */ soc_EP_EVXLT_KEY_TYPE_BCM56160_A0fmt_fields, 15202 /* bits */ 41, 15203 /* flags */ 0, 15204 }, 15205 #endif /* chips */ 15206 15207 #if defined(BCM_53570_B0) 15208 { /* SOC_FORMAT_INT_EP_EVXLT_KEY_TYPE_BCM53570_B0fmt */ 15209 /* format EP_EVXLT_KEY_TYPEfmt */ 15210 /* nFields */ 17, 15211 /* *fields */ soc_EP_EVXLT_KEY_TYPE_BCM56160_A0fmt_fields, 15212 /* bits */ 41, 15213 /* flags */ 0, 15214 }, 15215 #endif /* chips */ 15216 15217 #if defined(BCM_56150_A0) 15218 { /* SOC_FORMAT_INT_EP_EVXLT_KEY_TYPE_BCM56150_A0fmt */ 15219 /* format EP_EVXLT_KEY_TYPEfmt */ 15220 /* nFields */ 17, 15221 /* *fields */ soc_EP_EVXLT_KEY_TYPE_BCM56150_A0fmt_fields, 15222 /* bits */ 40, 15223 /* flags */ 0, 15224 }, 15225 #endif /* chips */ 15226 15227 #if defined(BCM_56160_A0) 15228 { /* SOC_FORMAT_INT_EP_EVXLT_KEY_TYPE_BCM56160_A0fmt */ 15229 /* format EP_EVXLT_KEY_TYPEfmt */ 15230 /* nFields */ 17, 15231 /* *fields */ soc_EP_EVXLT_KEY_TYPE_BCM56160_A0fmt_fields, 15232 /* bits */ 41, 15233 /* flags */ 0, 15234 }, 15235 #endif /* chips */ 15236 15237 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 15238 defined(BCM_56870_A0) 15239 { /* SOC_FORMAT_INT_EP_HW_CTRLfmt */ 15240 /* format EP_HW_CTRLfmt */ 15241 /* nFields */ 5, 15242 /* *fields */ soc_EP_HW_CTRLfmt_fields, 15243 /* bits */ 20, 15244 /* flags */ 0, 15245 }, 15246 #endif /* chips */ 15247 15248 #if defined(BCM_56980_A0) 15249 { /* SOC_FORMAT_INT_EP_HW_CTRL_BCM56980_A0fmt */ 15250 /* format EP_HW_CTRLfmt */ 15251 /* nFields */ 5, 15252 /* *fields */ soc_EP_HW_CTRL_BCM56980_A0fmt_fields, 15253 /* bits */ 19, 15254 /* flags */ 0, 15255 }, 15256 #endif /* chips */ 15257 15258 #if defined(BCM_56980_B0) 15259 { /* SOC_FORMAT_INT_EP_HW_CTRL_BCM56980_B0fmt */ 15260 /* format EP_HW_CTRLfmt */ 15261 /* nFields */ 5, 15262 /* *fields */ soc_EP_HW_CTRL_BCM56980_A0fmt_fields, 15263 /* bits */ 19, 15264 /* flags */ 0, 15265 }, 15266 #endif /* chips */ 15267 15268 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 15269 defined(BCM_56870_A0) 15270 { /* SOC_FORMAT_INT_EP_PARSER0_HFE_CMD_POLICY_DATAfmt */ 15271 /* format EP_PARSER0_HFE_CMD_POLICY_DATAfmt */ 15272 /* nFields */ 78, 15273 /* *fields */ soc_EP_PARSER0_HFE_CMD_POLICY_DATAfmt_fields, 15274 /* bits */ 262, 15275 /* flags */ 0, 15276 }, 15277 #endif /* chips */ 15278 15279 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 15280 defined(BCM_56870_A0) 15281 { /* SOC_FORMAT_INT_EP_PARSER0_HFE_CONSTANTSfmt */ 15282 /* format EP_PARSER0_HFE_CONSTANTSfmt */ 15283 /* nFields */ 1, 15284 /* *fields */ soc_EP_PARSER0_HFE_CONSTANTSfmt_fields, 15285 /* bits */ 1, 15286 /* flags */ 0, 15287 }, 15288 #endif /* chips */ 15289 15290 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 15291 defined(BCM_56870_A0) 15292 { /* SOC_FORMAT_INT_EP_PARSER0_HFE_CONTROLSfmt */ 15293 /* format EP_PARSER0_HFE_CONTROLSfmt */ 15294 /* nFields */ 8, 15295 /* *fields */ soc_EP_PARSER0_HFE_CONTROLSfmt_fields, 15296 /* bits */ 25, 15297 /* flags */ 0, 15298 }, 15299 #endif /* chips */ 15300 15301 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 15302 defined(BCM_56870_A0) 15303 { /* SOC_FORMAT_INT_EP_PARSER0_HFE_CONT_PROFILEfmt */ 15304 /* format EP_PARSER0_HFE_CONT_PROFILEfmt */ 15305 /* nFields */ 3, 15306 /* *fields */ soc_EP_PARSER0_HFE_CONT_PROFILEfmt_fields, 15307 /* bits */ 5, 15308 /* flags */ 0, 15309 }, 15310 #endif /* chips */ 15311 15312 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 15313 defined(BCM_56870_A0) 15314 { /* SOC_FORMAT_INT_EP_PARSER0_HFE_IN_BUSfmt */ 15315 /* format EP_PARSER0_HFE_IN_BUSfmt */ 15316 /* nFields */ 10, 15317 /* *fields */ soc_EP_PARSER0_HFE_IN_BUSfmt_fields, 15318 /* bits */ 537, 15319 /* flags */ 0, 15320 }, 15321 #endif /* chips */ 15322 15323 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 15324 defined(BCM_56870_A0) 15325 { /* SOC_FORMAT_INT_EP_PARSER0_HFE_MUX_CONTROLSfmt */ 15326 /* format EP_PARSER0_HFE_MUX_CONTROLSfmt */ 15327 /* nFields */ 5, 15328 /* *fields */ soc_EP_PARSER0_HFE_MUX_CONTROLSfmt_fields, 15329 /* bits */ 17, 15330 /* flags */ 0, 15331 }, 15332 #endif /* chips */ 15333 15334 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 15335 defined(BCM_56870_A0) 15336 { /* SOC_FORMAT_INT_EP_PARSER0_HFE_MUX_IN_BUSfmt */ 15337 /* format EP_PARSER0_HFE_MUX_IN_BUSfmt */ 15338 /* nFields */ 20, 15339 /* *fields */ soc_EP_PARSER0_HFE_MUX_IN_BUSfmt_fields, 15340 /* bits */ 851, 15341 /* flags */ 0, 15342 }, 15343 #endif /* chips */ 15344 15345 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 15346 defined(BCM_56870_A0) 15347 { /* SOC_FORMAT_INT_EP_PARSER0_HFE_MUX_OUT_BUSfmt */ 15348 /* format EP_PARSER0_HFE_MUX_OUT_BUSfmt */ 15349 /* nFields */ 97, 15350 /* *fields */ soc_EP_PARSER0_HFE_MUX_OUT_BUSfmt_fields, 15351 /* bits */ 699, 15352 /* flags */ 0, 15353 }, 15354 #endif /* chips */ 15355 15356 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 15357 defined(BCM_56870_A0) 15358 { /* SOC_FORMAT_INT_EP_PARSER0_HFE_OUT_BUSfmt */ 15359 /* format EP_PARSER0_HFE_OUT_BUSfmt */ 15360 /* nFields */ 98, 15361 /* *fields */ soc_EP_PARSER0_HFE_OUT_BUSfmt_fields, 15362 /* bits */ 699, 15363 /* flags */ 0, 15364 }, 15365 #endif /* chips */ 15366 15367 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 15368 defined(BCM_56870_A0) 15369 { /* SOC_FORMAT_INT_EP_PARSER0_HFE_POLICY_COMMAND_Afmt */ 15370 /* format EP_PARSER0_HFE_POLICY_COMMAND_Afmt */ 15371 /* nFields */ 2, 15372 /* *fields */ soc_EP_PARSER0_HFE_POLICY_COMMAND_Afmt_fields, 15373 /* bits */ 10, 15374 /* flags */ 0, 15375 }, 15376 #endif /* chips */ 15377 15378 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 15379 defined(BCM_56870_A0) 15380 { /* SOC_FORMAT_INT_EP_PARSER0_HFE_POLICY_COMMAND_Bfmt */ 15381 /* format EP_PARSER0_HFE_POLICY_COMMAND_Bfmt */ 15382 /* nFields */ 5, 15383 /* *fields */ soc_EP_PARSER0_HFE_POLICY_COMMAND_Bfmt_fields, 15384 /* bits */ 21, 15385 /* flags */ 0, 15386 }, 15387 #endif /* chips */ 15388 15389 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 15390 defined(BCM_56870_A0) 15391 { /* SOC_FORMAT_INT_EP_PARSER0_HFE_POLICY_COMMAND_Cfmt */ 15392 /* format EP_PARSER0_HFE_POLICY_COMMAND_Cfmt */ 15393 /* nFields */ 4, 15394 /* *fields */ soc_EP_PARSER0_HFE_POLICY_COMMAND_Cfmt_fields, 15395 /* bits */ 2, 15396 /* flags */ 0, 15397 }, 15398 #endif /* chips */ 15399 15400 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 15401 defined(BCM_56870_A0) 15402 { /* SOC_FORMAT_INT_EP_PARSER0_HFE_POLICY_COMMAND_Dfmt */ 15403 /* format EP_PARSER0_HFE_POLICY_COMMAND_Dfmt */ 15404 /* nFields */ 5, 15405 /* *fields */ soc_EP_PARSER0_HFE_POLICY_COMMAND_Dfmt_fields, 15406 /* bits */ 4, 15407 /* flags */ 0, 15408 }, 15409 #endif /* chips */ 15410 15411 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 15412 defined(BCM_56870_A0) 15413 { /* SOC_FORMAT_INT_EP_PARSER0_HFE_POLICY_TABLE_DATAfmt */ 15414 /* format EP_PARSER0_HFE_POLICY_TABLE_DATAfmt */ 15415 /* nFields */ 13, 15416 /* *fields */ soc_EP_PARSER0_HFE_POLICY_TABLE_DATAfmt_fields, 15417 /* bits */ 286, 15418 /* flags */ 0, 15419 }, 15420 #endif /* chips */ 15421 15422 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 15423 defined(BCM_56870_A0) 15424 { /* SOC_FORMAT_INT_EP_PARSER0_HVE_TRIGGERSfmt */ 15425 /* format EP_PARSER0_HVE_TRIGGERSfmt */ 15426 /* nFields */ 5, 15427 /* *fields */ soc_EP_PARSER0_HVE_TRIGGERSfmt_fields, 15428 /* bits */ 12, 15429 /* flags */ 0, 15430 }, 15431 #endif /* chips */ 15432 15433 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 15434 defined(BCM_56870_A0) 15435 { /* SOC_FORMAT_INT_EP_PARSER1_HFE_CMD_POLICY_DATAfmt */ 15436 /* format EP_PARSER1_HFE_CMD_POLICY_DATAfmt */ 15437 /* nFields */ 60, 15438 /* *fields */ soc_EP_PARSER1_HFE_CMD_POLICY_DATAfmt_fields, 15439 /* bits */ 204, 15440 /* flags */ 0, 15441 }, 15442 #endif /* chips */ 15443 15444 #if defined(BCM_56870_A0) 15445 { /* SOC_FORMAT_INT_EP_PARSER1_HFE_CONSTANTSfmt */ 15446 /* format EP_PARSER1_HFE_CONSTANTSfmt */ 15447 /* nFields */ 1, 15448 /* *fields */ soc_EP_PARSER0_HFE_CONSTANTSfmt_fields, 15449 /* bits */ 1, 15450 /* flags */ 0, 15451 }, 15452 #endif /* chips */ 15453 15454 #if defined(BCM_56370_A0) 15455 { /* SOC_FORMAT_INT_EP_PARSER1_HFE_CONSTANTS_BCM56370_A0fmt */ 15456 /* format EP_PARSER1_HFE_CONSTANTSfmt */ 15457 /* nFields */ 1, 15458 /* *fields */ soc_EP_PARSER0_HFE_CONSTANTSfmt_fields, 15459 /* bits */ 1, 15460 /* flags */ 0, 15461 }, 15462 #endif /* chips */ 15463 15464 #if defined(BCM_56770_A0) 15465 { /* SOC_FORMAT_INT_EP_PARSER1_HFE_CONSTANTS_BCM56770_A0fmt */ 15466 /* format EP_PARSER1_HFE_CONSTANTSfmt */ 15467 /* nFields */ 1, 15468 /* *fields */ soc_EP_PARSER0_HFE_CONSTANTSfmt_fields, 15469 /* bits */ 1, 15470 /* flags */ 0, 15471 }, 15472 #endif /* chips */ 15473 15474 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 15475 defined(BCM_56870_A0) 15476 { /* SOC_FORMAT_INT_EP_PARSER1_HFE_CONTROLSfmt */ 15477 /* format EP_PARSER1_HFE_CONTROLSfmt */ 15478 /* nFields */ 8, 15479 /* *fields */ soc_EP_PARSER1_HFE_CONTROLSfmt_fields, 15480 /* bits */ 118, 15481 /* flags */ 0, 15482 }, 15483 #endif /* chips */ 15484 15485 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 15486 defined(BCM_56870_A0) 15487 { /* SOC_FORMAT_INT_EP_PARSER1_HFE_CONT_PROFILEfmt */ 15488 /* format EP_PARSER1_HFE_CONT_PROFILEfmt */ 15489 /* nFields */ 2, 15490 /* *fields */ soc_EP_PARSER1_HFE_CONT_PROFILEfmt_fields, 15491 /* bits */ 10, 15492 /* flags */ 0, 15493 }, 15494 #endif /* chips */ 15495 15496 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 15497 defined(BCM_56870_A0) 15498 { /* SOC_FORMAT_INT_EP_PARSER1_HFE_IN_BUSfmt */ 15499 /* format EP_PARSER1_HFE_IN_BUSfmt */ 15500 /* nFields */ 10, 15501 /* *fields */ soc_EP_PARSER1_HFE_IN_BUSfmt_fields, 15502 /* bits */ 1142, 15503 /* flags */ 0, 15504 }, 15505 #endif /* chips */ 15506 15507 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 15508 defined(BCM_56870_A0) 15509 { /* SOC_FORMAT_INT_EP_PARSER1_HFE_MUX_CONTROLSfmt */ 15510 /* format EP_PARSER1_HFE_MUX_CONTROLSfmt */ 15511 /* nFields */ 5, 15512 /* *fields */ soc_EP_PARSER1_HFE_MUX_CONTROLSfmt_fields, 15513 /* bits */ 86, 15514 /* flags */ 0, 15515 }, 15516 #endif /* chips */ 15517 15518 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 15519 defined(BCM_56870_A0) 15520 { /* SOC_FORMAT_INT_EP_PARSER1_HFE_MUX_IN_BUSfmt */ 15521 /* format EP_PARSER1_HFE_MUX_IN_BUSfmt */ 15522 /* nFields */ 23, 15523 /* *fields */ soc_EP_PARSER1_HFE_MUX_IN_BUSfmt_fields, 15524 /* bits */ 2046, 15525 /* flags */ 0, 15526 }, 15527 #endif /* chips */ 15528 15529 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 15530 defined(BCM_56870_A0) 15531 { /* SOC_FORMAT_INT_EP_PARSER1_HFE_MUX_OUT_BUSfmt */ 15532 /* format EP_PARSER1_HFE_MUX_OUT_BUSfmt */ 15533 /* nFields */ 97, 15534 /* *fields */ soc_EP_PARSER1_HFE_MUX_OUT_BUSfmt_fields, 15535 /* bits */ 1229, 15536 /* flags */ 0, 15537 }, 15538 #endif /* chips */ 15539 15540 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 15541 defined(BCM_56870_A0) 15542 { /* SOC_FORMAT_INT_EP_PARSER1_HFE_OUT_BUSfmt */ 15543 /* format EP_PARSER1_HFE_OUT_BUSfmt */ 15544 /* nFields */ 98, 15545 /* *fields */ soc_EP_PARSER1_HFE_OUT_BUSfmt_fields, 15546 /* bits */ 1229, 15547 /* flags */ 0, 15548 }, 15549 #endif /* chips */ 15550 15551 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 15552 defined(BCM_56870_A0) 15553 { /* SOC_FORMAT_INT_EP_PARSER1_HFE_POLICY_COMMAND_Afmt */ 15554 /* format EP_PARSER1_HFE_POLICY_COMMAND_Afmt */ 15555 /* nFields */ 3, 15556 /* *fields */ soc_EP_PARSER1_HFE_POLICY_COMMAND_Afmt_fields, 15557 /* bits */ 2, 15558 /* flags */ 0, 15559 }, 15560 #endif /* chips */ 15561 15562 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 15563 defined(BCM_56870_A0) 15564 { /* SOC_FORMAT_INT_EP_PARSER1_HFE_POLICY_COMMAND_Bfmt */ 15565 /* format EP_PARSER1_HFE_POLICY_COMMAND_Bfmt */ 15566 /* nFields */ 6, 15567 /* *fields */ soc_EP_PARSER1_HFE_POLICY_COMMAND_Bfmt_fields, 15568 /* bits */ 2, 15569 /* flags */ 0, 15570 }, 15571 #endif /* chips */ 15572 15573 #if defined(BCM_56870_A0) 15574 { /* SOC_FORMAT_INT_EP_PARSER1_HFE_POLICY_COMMAND_Cfmt */ 15575 /* format EP_PARSER1_HFE_POLICY_COMMAND_Cfmt */ 15576 /* nFields */ 4, 15577 /* *fields */ soc_EP_PARSER0_HFE_POLICY_COMMAND_Cfmt_fields, 15578 /* bits */ 2, 15579 /* flags */ 0, 15580 }, 15581 #endif /* chips */ 15582 15583 #if defined(BCM_56370_A0) 15584 { /* SOC_FORMAT_INT_EP_PARSER1_HFE_POLICY_COMMAND_C_BCM56370_A0fmt */ 15585 /* format EP_PARSER1_HFE_POLICY_COMMAND_Cfmt */ 15586 /* nFields */ 4, 15587 /* *fields */ soc_EP_PARSER0_HFE_POLICY_COMMAND_Cfmt_fields, 15588 /* bits */ 2, 15589 /* flags */ 0, 15590 }, 15591 #endif /* chips */ 15592 15593 #if defined(BCM_56770_A0) 15594 { /* SOC_FORMAT_INT_EP_PARSER1_HFE_POLICY_COMMAND_C_BCM56770_A0fmt */ 15595 /* format EP_PARSER1_HFE_POLICY_COMMAND_Cfmt */ 15596 /* nFields */ 4, 15597 /* *fields */ soc_EP_PARSER0_HFE_POLICY_COMMAND_Cfmt_fields, 15598 /* bits */ 2, 15599 /* flags */ 0, 15600 }, 15601 #endif /* chips */ 15602 15603 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 15604 defined(BCM_56870_A0) 15605 { /* SOC_FORMAT_INT_EP_PARSER1_HFE_POLICY_COMMAND_Dfmt */ 15606 /* format EP_PARSER1_HFE_POLICY_COMMAND_Dfmt */ 15607 /* nFields */ 4, 15608 /* *fields */ soc_EP_PARSER1_HFE_POLICY_COMMAND_Dfmt_fields, 15609 /* bits */ 17, 15610 /* flags */ 0, 15611 }, 15612 #endif /* chips */ 15613 15614 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 15615 defined(BCM_56870_A0) 15616 { /* SOC_FORMAT_INT_EP_PARSER1_HFE_POLICY_TABLE_DATAfmt */ 15617 /* format EP_PARSER1_HFE_POLICY_TABLE_DATAfmt */ 15618 /* nFields */ 13, 15619 /* *fields */ soc_EP_PARSER1_HFE_POLICY_TABLE_DATAfmt_fields, 15620 /* bits */ 228, 15621 /* flags */ 0, 15622 }, 15623 #endif /* chips */ 15624 15625 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 15626 defined(BCM_56870_A0) 15627 { /* SOC_FORMAT_INT_EP_PARSER1_HVE_TRIGGERSfmt */ 15628 /* format EP_PARSER1_HVE_TRIGGERSfmt */ 15629 /* nFields */ 14, 15630 /* *fields */ soc_EP_PARSER1_HVE_TRIGGERSfmt_fields, 15631 /* bits */ 14, 15632 /* flags */ 0, 15633 }, 15634 #endif /* chips */ 15635 15636 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 15637 defined(BCM_56870_A0) 15638 { /* SOC_FORMAT_INT_EP_PARSER2_HFE_CMD_POLICY_DATAfmt */ 15639 /* format EP_PARSER2_HFE_CMD_POLICY_DATAfmt */ 15640 /* nFields */ 64, 15641 /* *fields */ soc_EP_PARSER2_HFE_CMD_POLICY_DATAfmt_fields, 15642 /* bits */ 208, 15643 /* flags */ 0, 15644 }, 15645 #endif /* chips */ 15646 15647 #if defined(BCM_56870_A0) 15648 { /* SOC_FORMAT_INT_EP_PARSER2_HFE_CONSTANTSfmt */ 15649 /* format EP_PARSER2_HFE_CONSTANTSfmt */ 15650 /* nFields */ 1, 15651 /* *fields */ soc_EP_PARSER0_HFE_CONSTANTSfmt_fields, 15652 /* bits */ 1, 15653 /* flags */ 0, 15654 }, 15655 #endif /* chips */ 15656 15657 #if defined(BCM_56370_A0) 15658 { /* SOC_FORMAT_INT_EP_PARSER2_HFE_CONSTANTS_BCM56370_A0fmt */ 15659 /* format EP_PARSER2_HFE_CONSTANTSfmt */ 15660 /* nFields */ 1, 15661 /* *fields */ soc_EP_PARSER0_HFE_CONSTANTSfmt_fields, 15662 /* bits */ 1, 15663 /* flags */ 0, 15664 }, 15665 #endif /* chips */ 15666 15667 #if defined(BCM_56770_A0) 15668 { /* SOC_FORMAT_INT_EP_PARSER2_HFE_CONSTANTS_BCM56770_A0fmt */ 15669 /* format EP_PARSER2_HFE_CONSTANTSfmt */ 15670 /* nFields */ 1, 15671 /* *fields */ soc_EP_PARSER0_HFE_CONSTANTSfmt_fields, 15672 /* bits */ 1, 15673 /* flags */ 0, 15674 }, 15675 #endif /* chips */ 15676 15677 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 15678 defined(BCM_56870_A0) 15679 { /* SOC_FORMAT_INT_EP_PARSER2_HFE_CONT_PROFILEfmt */ 15680 /* format EP_PARSER2_HFE_CONT_PROFILEfmt */ 15681 /* nFields */ 3, 15682 /* *fields */ soc_EP_PARSER2_HFE_CONT_PROFILEfmt_fields, 15683 /* bits */ 1, 15684 /* flags */ 0, 15685 }, 15686 #endif /* chips */ 15687 15688 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 15689 defined(BCM_56870_A0) 15690 { /* SOC_FORMAT_INT_EP_PARSER2_HFE_MUX_CONTROLSfmt */ 15691 /* format EP_PARSER2_HFE_MUX_CONTROLSfmt */ 15692 /* nFields */ 5, 15693 /* *fields */ soc_EP_PARSER2_HFE_MUX_CONTROLSfmt_fields, 15694 /* bits */ 23, 15695 /* flags */ 0, 15696 }, 15697 #endif /* chips */ 15698 15699 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 15700 defined(BCM_56870_A0) 15701 { /* SOC_FORMAT_INT_EP_PARSER2_HFE_MUX_IN_BUSfmt */ 15702 /* format EP_PARSER2_HFE_MUX_IN_BUSfmt */ 15703 /* nFields */ 8, 15704 /* *fields */ soc_EP_PARSER2_HFE_MUX_IN_BUSfmt_fields, 15705 /* bits */ 1767, 15706 /* flags */ 0, 15707 }, 15708 #endif /* chips */ 15709 15710 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 15711 defined(BCM_56870_A0) 15712 { /* SOC_FORMAT_INT_EP_PARSER2_HFE_MUX_OUT_BUSfmt */ 15713 /* format EP_PARSER2_HFE_MUX_OUT_BUSfmt */ 15714 /* nFields */ 97, 15715 /* *fields */ soc_EP_PARSER2_HFE_MUX_OUT_BUSfmt_fields, 15716 /* bits */ 831, 15717 /* flags */ 0, 15718 }, 15719 #endif /* chips */ 15720 15721 #if defined(BCM_56870_A0) 15722 { /* SOC_FORMAT_INT_EP_PARSER2_HFE_POLICY_COMMAND_Afmt */ 15723 /* format EP_PARSER2_HFE_POLICY_COMMAND_Afmt */ 15724 /* nFields */ 3, 15725 /* *fields */ soc_EP_PARSER1_HFE_POLICY_COMMAND_Afmt_fields, 15726 /* bits */ 2, 15727 /* flags */ 0, 15728 }, 15729 #endif /* chips */ 15730 15731 #if defined(BCM_56370_A0) 15732 { /* SOC_FORMAT_INT_EP_PARSER2_HFE_POLICY_COMMAND_A_BCM56370_A0fmt */ 15733 /* format EP_PARSER2_HFE_POLICY_COMMAND_Afmt */ 15734 /* nFields */ 3, 15735 /* *fields */ soc_EP_PARSER1_HFE_POLICY_COMMAND_Afmt_fields, 15736 /* bits */ 2, 15737 /* flags */ 0, 15738 }, 15739 #endif /* chips */ 15740 15741 #if defined(BCM_56770_A0) 15742 { /* SOC_FORMAT_INT_EP_PARSER2_HFE_POLICY_COMMAND_A_BCM56770_A0fmt */ 15743 /* format EP_PARSER2_HFE_POLICY_COMMAND_Afmt */ 15744 /* nFields */ 3, 15745 /* *fields */ soc_EP_PARSER1_HFE_POLICY_COMMAND_Afmt_fields, 15746 /* bits */ 2, 15747 /* flags */ 0, 15748 }, 15749 #endif /* chips */ 15750 15751 #if defined(BCM_56870_A0) 15752 { /* SOC_FORMAT_INT_EP_PARSER2_HFE_POLICY_COMMAND_Bfmt */ 15753 /* format EP_PARSER2_HFE_POLICY_COMMAND_Bfmt */ 15754 /* nFields */ 6, 15755 /* *fields */ soc_EP_PARSER1_HFE_POLICY_COMMAND_Bfmt_fields, 15756 /* bits */ 2, 15757 /* flags */ 0, 15758 }, 15759 #endif /* chips */ 15760 15761 #if defined(BCM_56370_A0) 15762 { /* SOC_FORMAT_INT_EP_PARSER2_HFE_POLICY_COMMAND_B_BCM56370_A0fmt */ 15763 /* format EP_PARSER2_HFE_POLICY_COMMAND_Bfmt */ 15764 /* nFields */ 6, 15765 /* *fields */ soc_EP_PARSER1_HFE_POLICY_COMMAND_Bfmt_fields, 15766 /* bits */ 2, 15767 /* flags */ 0, 15768 }, 15769 #endif /* chips */ 15770 15771 #if defined(BCM_56770_A0) 15772 { /* SOC_FORMAT_INT_EP_PARSER2_HFE_POLICY_COMMAND_B_BCM56770_A0fmt */ 15773 /* format EP_PARSER2_HFE_POLICY_COMMAND_Bfmt */ 15774 /* nFields */ 6, 15775 /* *fields */ soc_EP_PARSER1_HFE_POLICY_COMMAND_Bfmt_fields, 15776 /* bits */ 2, 15777 /* flags */ 0, 15778 }, 15779 #endif /* chips */ 15780 15781 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 15782 defined(BCM_56870_A0) 15783 { /* SOC_FORMAT_INT_EP_PARSER2_HFE_POLICY_COMMAND_Cfmt */ 15784 /* format EP_PARSER2_HFE_POLICY_COMMAND_Cfmt */ 15785 /* nFields */ 3, 15786 /* *fields */ soc_EP_PARSER2_HFE_POLICY_COMMAND_Cfmt_fields, 15787 /* bits */ 13, 15788 /* flags */ 0, 15789 }, 15790 #endif /* chips */ 15791 15792 #if defined(BCM_56870_A0) 15793 { /* SOC_FORMAT_INT_EP_PARSER2_HFE_POLICY_COMMAND_Dfmt */ 15794 /* format EP_PARSER2_HFE_POLICY_COMMAND_Dfmt */ 15795 /* nFields */ 5, 15796 /* *fields */ soc_EP_PARSER0_HFE_POLICY_COMMAND_Dfmt_fields, 15797 /* bits */ 4, 15798 /* flags */ 0, 15799 }, 15800 #endif /* chips */ 15801 15802 #if defined(BCM_56370_A0) 15803 { /* SOC_FORMAT_INT_EP_PARSER2_HFE_POLICY_COMMAND_D_BCM56370_A0fmt */ 15804 /* format EP_PARSER2_HFE_POLICY_COMMAND_Dfmt */ 15805 /* nFields */ 5, 15806 /* *fields */ soc_EP_PARSER0_HFE_POLICY_COMMAND_Dfmt_fields, 15807 /* bits */ 4, 15808 /* flags */ 0, 15809 }, 15810 #endif /* chips */ 15811 15812 #if defined(BCM_56770_A0) 15813 { /* SOC_FORMAT_INT_EP_PARSER2_HFE_POLICY_COMMAND_D_BCM56770_A0fmt */ 15814 /* format EP_PARSER2_HFE_POLICY_COMMAND_Dfmt */ 15815 /* nFields */ 5, 15816 /* *fields */ soc_EP_PARSER0_HFE_POLICY_COMMAND_Dfmt_fields, 15817 /* bits */ 4, 15818 /* flags */ 0, 15819 }, 15820 #endif /* chips */ 15821 15822 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 15823 defined(BCM_56870_A0) 15824 { /* SOC_FORMAT_INT_EP_PARSER2_HFE_POLICY_TABLE_DATAfmt */ 15825 /* format EP_PARSER2_HFE_POLICY_TABLE_DATAfmt */ 15826 /* nFields */ 1, 15827 /* *fields */ soc_EP_PARSER2_HFE_POLICY_TABLE_DATAfmt_fields, 15828 /* bits */ 208, 15829 /* flags */ 0, 15830 }, 15831 #endif /* chips */ 15832 15833 #if defined(BCM_56340_A0) || defined(BCM_56640_A0) 15834 { /* SOC_FORMAT_INT_EP_PW_INIT_COUNTER_COV_DEFSfmt */ 15835 /* format EP_PW_INIT_COUNTER_COV_DEFSfmt */ 15836 /* nFields */ 6, 15837 /* *fields */ soc_EP_PW_INIT_COUNTER_COV_DEFSfmt_fields, 15838 /* bits */ 20, 15839 /* flags */ 0, 15840 }, 15841 #endif /* chips */ 15842 15843 #if defined(BCM_56560_A0) 15844 { /* SOC_FORMAT_INT_EP_PW_INIT_COUNTER_COV_DEFS_BCM56560_A0fmt */ 15845 /* format EP_PW_INIT_COUNTER_COV_DEFSfmt */ 15846 /* nFields */ 7, 15847 /* *fields */ soc_EP_PW_INIT_COUNTER_COV_DEFS_BCM56560_A0fmt_fields, 15848 /* bits */ 22, 15849 /* flags */ 0, 15850 }, 15851 #endif /* chips */ 15852 15853 #if defined(BCM_56560_B0) 15854 { /* SOC_FORMAT_INT_EP_PW_INIT_COUNTER_COV_DEFS_BCM56560_B0fmt */ 15855 /* format EP_PW_INIT_COUNTER_COV_DEFSfmt */ 15856 /* nFields */ 7, 15857 /* *fields */ soc_EP_PW_INIT_COUNTER_COV_DEFS_BCM56560_A0fmt_fields, 15858 /* bits */ 22, 15859 /* flags */ 0, 15860 }, 15861 #endif /* chips */ 15862 15863 #if defined(BCM_56670_A0) 15864 { /* SOC_FORMAT_INT_EP_PW_INIT_COUNTER_COV_DEFS_BCM56670_A0fmt */ 15865 /* format EP_PW_INIT_COUNTER_COV_DEFSfmt */ 15866 /* nFields */ 7, 15867 /* *fields */ soc_EP_PW_INIT_COUNTER_COV_DEFS_BCM56560_A0fmt_fields, 15868 /* bits */ 22, 15869 /* flags */ 0, 15870 }, 15871 #endif /* chips */ 15872 15873 #if defined(BCM_56670_B0) 15874 { /* SOC_FORMAT_INT_EP_PW_INIT_COUNTER_COV_DEFS_BCM56670_B0fmt */ 15875 /* format EP_PW_INIT_COUNTER_COV_DEFSfmt */ 15876 /* nFields */ 7, 15877 /* *fields */ soc_EP_PW_INIT_COUNTER_COV_DEFS_BCM56560_A0fmt_fields, 15878 /* bits */ 22, 15879 /* flags */ 0, 15880 }, 15881 #endif /* chips */ 15882 15883 #if defined(BCM_56850_A0) 15884 { /* SOC_FORMAT_INT_EP_PW_INIT_COUNTER_COV_DEFS_BCM56850_A0fmt */ 15885 /* format EP_PW_INIT_COUNTER_COV_DEFSfmt */ 15886 /* nFields */ 6, 15887 /* *fields */ soc_OAM_LM_COUNTERS_COV_DEFSfmt_fields, 15888 /* bits */ 21, 15889 /* flags */ 0, 15890 }, 15891 #endif /* chips */ 15892 15893 #if defined(BCM_56860_A0) 15894 { /* SOC_FORMAT_INT_EP_PW_INIT_COUNTER_COV_DEFS_BCM56860_A0fmt */ 15895 /* format EP_PW_INIT_COUNTER_COV_DEFSfmt */ 15896 /* nFields */ 7, 15897 /* *fields */ soc_EP_PW_INIT_COUNTER_COV_DEFS_BCM56860_A0fmt_fields, 15898 /* bits */ 22, 15899 /* flags */ 0, 15900 }, 15901 #endif /* chips */ 15902 15903 #if defined(BCM_56960_A0) 15904 { /* SOC_FORMAT_INT_EP_PW_INIT_COUNTER_COV_DEFS_BCM56960_A0fmt */ 15905 /* format EP_PW_INIT_COUNTER_COV_DEFSfmt */ 15906 /* nFields */ 6, 15907 /* *fields */ soc_EP_PW_INIT_COUNTER_COV_DEFS_BCM56960_A0fmt_fields, 15908 /* bits */ 21, 15909 /* flags */ 0, 15910 }, 15911 #endif /* chips */ 15912 15913 #if defined(BCM_56965_A0) 15914 { /* SOC_FORMAT_INT_EP_PW_INIT_COUNTER_COV_DEFS_BCM56965_A0fmt */ 15915 /* format EP_PW_INIT_COUNTER_COV_DEFSfmt */ 15916 /* nFields */ 6, 15917 /* *fields */ soc_EP_PW_INIT_COUNTER_COV_DEFS_BCM56960_A0fmt_fields, 15918 /* bits */ 21, 15919 /* flags */ 0, 15920 }, 15921 #endif /* chips */ 15922 15923 #if defined(BCM_56970_A0) 15924 { /* SOC_FORMAT_INT_EP_PW_INIT_COUNTER_COV_DEFS_BCM56970_A0fmt */ 15925 /* format EP_PW_INIT_COUNTER_COV_DEFSfmt */ 15926 /* nFields */ 6, 15927 /* *fields */ soc_EP_PW_INIT_COUNTER_COV_DEFS_BCM56970_A0fmt_fields, 15928 /* bits */ 20, 15929 /* flags */ 0, 15930 }, 15931 #endif /* chips */ 15932 15933 #if defined(BCM_56980_A0) 15934 { /* SOC_FORMAT_INT_EP_PW_INIT_COUNTER_COV_DEFS_BCM56980_A0fmt */ 15935 /* format EP_PW_INIT_COUNTER_COV_DEFSfmt */ 15936 /* nFields */ 6, 15937 /* *fields */ soc_EP_PW_INIT_COUNTER_COV_DEFS_BCM56970_A0fmt_fields, 15938 /* bits */ 20, 15939 /* flags */ 0, 15940 }, 15941 #endif /* chips */ 15942 15943 #if defined(BCM_56980_B0) 15944 { /* SOC_FORMAT_INT_EP_PW_INIT_COUNTER_COV_DEFS_BCM56980_B0fmt */ 15945 /* format EP_PW_INIT_COUNTER_COV_DEFSfmt */ 15946 /* nFields */ 6, 15947 /* *fields */ soc_EP_PW_INIT_COUNTER_COV_DEFS_BCM56970_A0fmt_fields, 15948 /* bits */ 20, 15949 /* flags */ 0, 15950 }, 15951 #endif /* chips */ 15952 15953 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 15954 defined(BCM_56870_A0) 15955 { /* SOC_FORMAT_INT_EP_REGfmt */ 15956 /* format EP_REGfmt */ 15957 /* nFields */ 2, 15958 /* *fields */ soc_EP_REGfmt_fields, 15959 /* bits */ 14, 15960 /* flags */ 0, 15961 }, 15962 #endif /* chips */ 15963 15964 #if defined(BCM_56850_A0) 15965 { /* SOC_FORMAT_INT_EP_TO_CLP_IF_BUSfmt */ 15966 /* format EP_TO_CLP_IF_BUSfmt */ 15967 /* nFields */ 14, 15968 /* *fields */ soc_EP_TO_CLP_IF_BUSfmt_fields, 15969 /* bits */ 535, 15970 /* flags */ 0, 15971 }, 15972 #endif /* chips */ 15973 15974 #if defined(BCM_56370_A0) 15975 { /* SOC_FORMAT_INT_EP_TO_CLP_IF_BUS_BCM56370_A0fmt */ 15976 /* format EP_TO_CLP_IF_BUSfmt */ 15977 /* nFields */ 14, 15978 /* *fields */ soc_EP_TO_CLP_IF_BUS_BCM56960_A0fmt_fields, 15979 /* bits */ 535, 15980 /* flags */ 0, 15981 }, 15982 #endif /* chips */ 15983 15984 #if defined(BCM_56560_A0) 15985 { /* SOC_FORMAT_INT_EP_TO_CLP_IF_BUS_BCM56560_A0fmt */ 15986 /* format EP_TO_CLP_IF_BUSfmt */ 15987 /* nFields */ 16, 15988 /* *fields */ soc_EP_TO_CLP_IF_BUS_BCM56560_A0fmt_fields, 15989 /* bits */ 456, 15990 /* flags */ 0, 15991 }, 15992 #endif /* chips */ 15993 15994 #if defined(BCM_56560_B0) 15995 { /* SOC_FORMAT_INT_EP_TO_CLP_IF_BUS_BCM56560_B0fmt */ 15996 /* format EP_TO_CLP_IF_BUSfmt */ 15997 /* nFields */ 16, 15998 /* *fields */ soc_EP_TO_CLP_IF_BUS_BCM56560_A0fmt_fields, 15999 /* bits */ 456, 16000 /* flags */ 0, 16001 }, 16002 #endif /* chips */ 16003 16004 #if defined(BCM_56670_A0) 16005 { /* SOC_FORMAT_INT_EP_TO_CLP_IF_BUS_BCM56670_A0fmt */ 16006 /* format EP_TO_CLP_IF_BUSfmt */ 16007 /* nFields */ 16, 16008 /* *fields */ soc_EP_TO_CLP_IF_BUS_BCM56560_A0fmt_fields, 16009 /* bits */ 456, 16010 /* flags */ 0, 16011 }, 16012 #endif /* chips */ 16013 16014 #if defined(BCM_56670_B0) 16015 { /* SOC_FORMAT_INT_EP_TO_CLP_IF_BUS_BCM56670_B0fmt */ 16016 /* format EP_TO_CLP_IF_BUSfmt */ 16017 /* nFields */ 16, 16018 /* *fields */ soc_EP_TO_CLP_IF_BUS_BCM56560_A0fmt_fields, 16019 /* bits */ 456, 16020 /* flags */ 0, 16021 }, 16022 #endif /* chips */ 16023 16024 #if defined(BCM_56770_A0) 16025 { /* SOC_FORMAT_INT_EP_TO_CLP_IF_BUS_BCM56770_A0fmt */ 16026 /* format EP_TO_CLP_IF_BUSfmt */ 16027 /* nFields */ 14, 16028 /* *fields */ soc_EP_TO_CLP_IF_BUS_BCM56960_A0fmt_fields, 16029 /* bits */ 535, 16030 /* flags */ 0, 16031 }, 16032 #endif /* chips */ 16033 16034 #if defined(BCM_56860_A0) 16035 { /* SOC_FORMAT_INT_EP_TO_CLP_IF_BUS_BCM56860_A0fmt */ 16036 /* format EP_TO_CLP_IF_BUSfmt */ 16037 /* nFields */ 16, 16038 /* *fields */ soc_EP_TO_CLP_IF_BUS_BCM56860_A0fmt_fields, 16039 /* bits */ 456, 16040 /* flags */ 0, 16041 }, 16042 #endif /* chips */ 16043 16044 #if defined(BCM_56870_A0) 16045 { /* SOC_FORMAT_INT_EP_TO_CLP_IF_BUS_BCM56870_A0fmt */ 16046 /* format EP_TO_CLP_IF_BUSfmt */ 16047 /* nFields */ 14, 16048 /* *fields */ soc_EP_TO_CLP_IF_BUS_BCM56960_A0fmt_fields, 16049 /* bits */ 535, 16050 /* flags */ 0, 16051 }, 16052 #endif /* chips */ 16053 16054 #if defined(BCM_56960_A0) 16055 { /* SOC_FORMAT_INT_EP_TO_CLP_IF_BUS_BCM56960_A0fmt */ 16056 /* format EP_TO_CLP_IF_BUSfmt */ 16057 /* nFields */ 14, 16058 /* *fields */ soc_EP_TO_CLP_IF_BUS_BCM56960_A0fmt_fields, 16059 /* bits */ 535, 16060 /* flags */ 0, 16061 }, 16062 #endif /* chips */ 16063 16064 #if defined(BCM_56965_A0) 16065 { /* SOC_FORMAT_INT_EP_TO_CLP_IF_BUS_BCM56965_A0fmt */ 16066 /* format EP_TO_CLP_IF_BUSfmt */ 16067 /* nFields */ 14, 16068 /* *fields */ soc_EP_TO_CLP_IF_BUS_BCM56960_A0fmt_fields, 16069 /* bits */ 535, 16070 /* flags */ 0, 16071 }, 16072 #endif /* chips */ 16073 16074 #if defined(BCM_56970_A0) 16075 { /* SOC_FORMAT_INT_EP_TO_CLP_IF_BUS_BCM56970_A0fmt */ 16076 /* format EP_TO_CLP_IF_BUSfmt */ 16077 /* nFields */ 14, 16078 /* *fields */ soc_EP_TO_CLP_IF_BUS_BCM56960_A0fmt_fields, 16079 /* bits */ 535, 16080 /* flags */ 0, 16081 }, 16082 #endif /* chips */ 16083 16084 #if defined(BCM_56980_A0) 16085 { /* SOC_FORMAT_INT_EP_TO_CLP_IF_BUS_BCM56980_A0fmt */ 16086 /* format EP_TO_CLP_IF_BUSfmt */ 16087 /* nFields */ 14, 16088 /* *fields */ soc_EP_TO_CLP_IF_BUS_BCM56960_A0fmt_fields, 16089 /* bits */ 535, 16090 /* flags */ 0, 16091 }, 16092 #endif /* chips */ 16093 16094 #if defined(BCM_56980_B0) 16095 { /* SOC_FORMAT_INT_EP_TO_CLP_IF_BUS_BCM56980_B0fmt */ 16096 /* format EP_TO_CLP_IF_BUSfmt */ 16097 /* nFields */ 14, 16098 /* *fields */ soc_EP_TO_CLP_IF_BUS_BCM56960_A0fmt_fields, 16099 /* bits */ 535, 16100 /* flags */ 0, 16101 }, 16102 #endif /* chips */ 16103 16104 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 16105 defined(BCM_56870_A0) || defined(BCM_56980_A0) || \ 16106 defined(BCM_56980_B0) 16107 { /* SOC_FORMAT_INT_EP_TO_CM_CPU_DMA_BUSfmt */ 16108 /* format EP_TO_CM_CPU_DMA_BUSfmt */ 16109 /* nFields */ 5, 16110 /* *fields */ soc_EP_TO_CM_CPU_DMA_BUSfmt_fields, 16111 /* bits */ 96, 16112 /* flags */ 0, 16113 }, 16114 #endif /* chips */ 16115 16116 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) 16117 { /* SOC_FORMAT_INT_EP_TO_CPU_COMPOSITES_BUSfmt */ 16118 /* format EP_TO_CPU_COMPOSITES_BUSfmt */ 16119 /* nFields */ 44, 16120 /* *fields */ soc_EP_TO_CPU_COMPOSITES_BUSfmt_fields, 16121 /* bits */ 320, 16122 /* flags */ 0, 16123 }, 16124 #endif /* chips */ 16125 16126 #if defined(BCM_56370_A0) 16127 { /* SOC_FORMAT_INT_EP_TO_CPU_COMPOSITES_BUS_BCM56370_A0fmt */ 16128 /* format EP_TO_CPU_COMPOSITES_BUSfmt */ 16129 /* nFields */ 48, 16130 /* *fields */ soc_EP_TO_CPU_COMPOSITES_BUS_BCM56370_A0fmt_fields, 16131 /* bits */ 320, 16132 /* flags */ 0, 16133 }, 16134 #endif /* chips */ 16135 16136 #if defined(BCM_56980_A0) 16137 { /* SOC_FORMAT_INT_EP_TO_CPU_COMPOSITES_BUS_BCM56980_A0fmt */ 16138 /* format EP_TO_CPU_COMPOSITES_BUSfmt */ 16139 /* nFields */ 45, 16140 /* *fields */ soc_EP_TO_CPU_COMPOSITES_BUS_BCM56980_A0fmt_fields, 16141 /* bits */ 288, 16142 /* flags */ 0, 16143 }, 16144 #endif /* chips */ 16145 16146 #if defined(BCM_56980_B0) 16147 { /* SOC_FORMAT_INT_EP_TO_CPU_COMPOSITES_BUS_BCM56980_B0fmt */ 16148 /* format EP_TO_CPU_COMPOSITES_BUSfmt */ 16149 /* nFields */ 45, 16150 /* *fields */ soc_EP_TO_CPU_COMPOSITES_BUS_BCM56980_A0fmt_fields, 16151 /* bits */ 288, 16152 /* flags */ 0, 16153 }, 16154 #endif /* chips */ 16155 16156 #if defined(BCM_56504_A0) 16157 { /* SOC_FORMAT_INT_EP_TO_CPU_HDRfmt */ 16158 /* format EP_TO_CPU_HDRfmt */ 16159 /* nFields */ 29, 16160 /* *fields */ soc_EP_TO_CPU_HDRfmt_fields, 16161 /* bits */ 256, 16162 /* flags */ 0, 16163 }, 16164 #endif /* chips */ 16165 16166 #if defined(BCM_53314_A0) 16167 { /* SOC_FORMAT_INT_EP_TO_CPU_HDR_BCM53314_A0fmt */ 16168 /* format EP_TO_CPU_HDRfmt */ 16169 /* nFields */ 33, 16170 /* *fields */ soc_EP_TO_CPU_HDR_BCM53314_A0fmt_fields, 16171 /* bits */ 256, 16172 /* flags */ 0, 16173 }, 16174 #endif /* chips */ 16175 16176 #if defined(BCM_53324_A0) 16177 { /* SOC_FORMAT_INT_EP_TO_CPU_HDR_BCM53324_A0fmt */ 16178 /* format EP_TO_CPU_HDRfmt */ 16179 /* nFields */ 33, 16180 /* *fields */ soc_EP_TO_CPU_HDR_BCM53314_A0fmt_fields, 16181 /* bits */ 256, 16182 /* flags */ 0, 16183 }, 16184 #endif /* chips */ 16185 16186 #if defined(BCM_53400_A0) 16187 { /* SOC_FORMAT_INT_EP_TO_CPU_HDR_BCM53400_A0fmt */ 16188 /* format EP_TO_CPU_HDRfmt */ 16189 /* nFields */ 49, 16190 /* *fields */ soc_EP_TO_CPU_HDR_BCM53400_A0fmt_fields, 16191 /* bits */ 416, 16192 /* flags */ 0, 16193 }, 16194 #endif /* chips */ 16195 16196 #if defined(BCM_53540_A0) 16197 { /* SOC_FORMAT_INT_EP_TO_CPU_HDR_BCM53540_A0fmt */ 16198 /* format EP_TO_CPU_HDRfmt */ 16199 /* nFields */ 51, 16200 /* *fields */ soc_EP_TO_CPU_HDR_BCM53540_A0fmt_fields, 16201 /* bits */ 416, 16202 /* flags */ 0, 16203 }, 16204 #endif /* chips */ 16205 16206 #if defined(BCM_53570_A0) 16207 { /* SOC_FORMAT_INT_EP_TO_CPU_HDR_BCM53570_A0fmt */ 16208 /* format EP_TO_CPU_HDRfmt */ 16209 /* nFields */ 50, 16210 /* *fields */ soc_EP_TO_CPU_HDR_BCM56160_A0fmt_fields, 16211 /* bits */ 416, 16212 /* flags */ 0, 16213 }, 16214 #endif /* chips */ 16215 16216 #if defined(BCM_53570_B0) 16217 { /* SOC_FORMAT_INT_EP_TO_CPU_HDR_BCM53570_B0fmt */ 16218 /* format EP_TO_CPU_HDRfmt */ 16219 /* nFields */ 52, 16220 /* *fields */ soc_EP_TO_CPU_HDR_BCM53570_B0fmt_fields, 16221 /* bits */ 416, 16222 /* flags */ 0, 16223 }, 16224 #endif /* chips */ 16225 16226 #if defined(BCM_56142_A0) 16227 { /* SOC_FORMAT_INT_EP_TO_CPU_HDR_BCM56142_A0fmt */ 16228 /* format EP_TO_CPU_HDRfmt */ 16229 /* nFields */ 53, 16230 /* *fields */ soc_EP_TO_CPU_HDR_BCM56142_A0fmt_fields, 16231 /* bits */ 416, 16232 /* flags */ 0, 16233 }, 16234 #endif /* chips */ 16235 16236 #if defined(BCM_56150_A0) 16237 { /* SOC_FORMAT_INT_EP_TO_CPU_HDR_BCM56150_A0fmt */ 16238 /* format EP_TO_CPU_HDRfmt */ 16239 /* nFields */ 56, 16240 /* *fields */ soc_EP_TO_CPU_HDR_BCM56150_A0fmt_fields, 16241 /* bits */ 416, 16242 /* flags */ 0, 16243 }, 16244 #endif /* chips */ 16245 16246 #if defined(BCM_56160_A0) 16247 { /* SOC_FORMAT_INT_EP_TO_CPU_HDR_BCM56160_A0fmt */ 16248 /* format EP_TO_CPU_HDRfmt */ 16249 /* nFields */ 50, 16250 /* *fields */ soc_EP_TO_CPU_HDR_BCM56160_A0fmt_fields, 16251 /* bits */ 416, 16252 /* flags */ 0, 16253 }, 16254 #endif /* chips */ 16255 16256 #if defined(BCM_56224_A0) 16257 { /* SOC_FORMAT_INT_EP_TO_CPU_HDR_BCM56224_A0fmt */ 16258 /* format EP_TO_CPU_HDRfmt */ 16259 /* nFields */ 31, 16260 /* *fields */ soc_EP_TO_CPU_HDR_BCM56224_A0fmt_fields, 16261 /* bits */ 256, 16262 /* flags */ 0, 16263 }, 16264 #endif /* chips */ 16265 16266 #if defined(BCM_56224_B0) 16267 { /* SOC_FORMAT_INT_EP_TO_CPU_HDR_BCM56224_B0fmt */ 16268 /* format EP_TO_CPU_HDRfmt */ 16269 /* nFields */ 31, 16270 /* *fields */ soc_EP_TO_CPU_HDR_BCM56224_B0fmt_fields, 16271 /* bits */ 256, 16272 /* flags */ 0, 16273 }, 16274 #endif /* chips */ 16275 16276 #if defined(BCM_56260_A0) 16277 { /* SOC_FORMAT_INT_EP_TO_CPU_HDR_BCM56260_A0fmt */ 16278 /* format EP_TO_CPU_HDRfmt */ 16279 /* nFields */ 59, 16280 /* *fields */ soc_EP_TO_CPU_HDR_BCM56260_A0fmt_fields, 16281 /* bits */ 448, 16282 /* flags */ 0, 16283 }, 16284 #endif /* chips */ 16285 16286 #if defined(BCM_56260_B0) 16287 { /* SOC_FORMAT_INT_EP_TO_CPU_HDR_BCM56260_B0fmt */ 16288 /* format EP_TO_CPU_HDRfmt */ 16289 /* nFields */ 59, 16290 /* *fields */ soc_EP_TO_CPU_HDR_BCM56260_A0fmt_fields, 16291 /* bits */ 448, 16292 /* flags */ 0, 16293 }, 16294 #endif /* chips */ 16295 16296 #if defined(BCM_56270_A0) 16297 { /* SOC_FORMAT_INT_EP_TO_CPU_HDR_BCM56270_A0fmt */ 16298 /* format EP_TO_CPU_HDRfmt */ 16299 /* nFields */ 59, 16300 /* *fields */ soc_EP_TO_CPU_HDR_BCM56260_A0fmt_fields, 16301 /* bits */ 448, 16302 /* flags */ 0, 16303 }, 16304 #endif /* chips */ 16305 16306 #if defined(BCM_56314_A0) 16307 { /* SOC_FORMAT_INT_EP_TO_CPU_HDR_BCM56314_A0fmt */ 16308 /* format EP_TO_CPU_HDRfmt */ 16309 /* nFields */ 29, 16310 /* *fields */ soc_EP_TO_CPU_HDR_BCM56504_B0fmt_fields, 16311 /* bits */ 256, 16312 /* flags */ 0, 16313 }, 16314 #endif /* chips */ 16315 16316 #if defined(BCM_56334_A0) 16317 { /* SOC_FORMAT_INT_EP_TO_CPU_HDR_BCM56334_A0fmt */ 16318 /* format EP_TO_CPU_HDRfmt */ 16319 /* nFields */ 53, 16320 /* *fields */ soc_EP_TO_CPU_HDR_BCM56334_A0fmt_fields, 16321 /* bits */ 416, 16322 /* flags */ 0, 16323 }, 16324 #endif /* chips */ 16325 16326 #if defined(BCM_56334_B0) 16327 { /* SOC_FORMAT_INT_EP_TO_CPU_HDR_BCM56334_B0fmt */ 16328 /* format EP_TO_CPU_HDRfmt */ 16329 /* nFields */ 53, 16330 /* *fields */ soc_EP_TO_CPU_HDR_BCM56334_A0fmt_fields, 16331 /* bits */ 416, 16332 /* flags */ 0, 16333 }, 16334 #endif /* chips */ 16335 16336 #if defined(BCM_56340_A0) 16337 { /* SOC_FORMAT_INT_EP_TO_CPU_HDR_BCM56340_A0fmt */ 16338 /* format EP_TO_CPU_HDRfmt */ 16339 /* nFields */ 57, 16340 /* *fields */ soc_EP_TO_CPU_HDR_BCM56340_A0fmt_fields, 16341 /* bits */ 416, 16342 /* flags */ 0, 16343 }, 16344 #endif /* chips */ 16345 16346 #if defined(BCM_56370_A0) 16347 { /* SOC_FORMAT_INT_EP_TO_CPU_HDR_BCM56370_A0fmt */ 16348 /* format EP_TO_CPU_HDRfmt */ 16349 /* nFields */ 21, 16350 /* *fields */ soc_EP_TO_CPU_HDR_BCM56370_A0fmt_fields, 16351 /* bits */ 480, 16352 /* flags */ 0, 16353 }, 16354 #endif /* chips */ 16355 16356 #if defined(BCM_56440_A0) 16357 { /* SOC_FORMAT_INT_EP_TO_CPU_HDR_BCM56440_A0fmt */ 16358 /* format EP_TO_CPU_HDRfmt */ 16359 /* nFields */ 58, 16360 /* *fields */ soc_EP_TO_CPU_HDR_BCM56440_A0fmt_fields, 16361 /* bits */ 448, 16362 /* flags */ 0, 16363 }, 16364 #endif /* chips */ 16365 16366 #if defined(BCM_56440_B0) 16367 { /* SOC_FORMAT_INT_EP_TO_CPU_HDR_BCM56440_B0fmt */ 16368 /* format EP_TO_CPU_HDRfmt */ 16369 /* nFields */ 58, 16370 /* *fields */ soc_EP_TO_CPU_HDR_BCM56440_A0fmt_fields, 16371 /* bits */ 448, 16372 /* flags */ 0, 16373 }, 16374 #endif /* chips */ 16375 16376 #if defined(BCM_56450_A0) 16377 { /* SOC_FORMAT_INT_EP_TO_CPU_HDR_BCM56450_A0fmt */ 16378 /* format EP_TO_CPU_HDRfmt */ 16379 /* nFields */ 57, 16380 /* *fields */ soc_EP_TO_CPU_HDR_BCM56450_A0fmt_fields, 16381 /* bits */ 448, 16382 /* flags */ 0, 16383 }, 16384 #endif /* chips */ 16385 16386 #if defined(BCM_56450_B0) 16387 { /* SOC_FORMAT_INT_EP_TO_CPU_HDR_BCM56450_B0fmt */ 16388 /* format EP_TO_CPU_HDRfmt */ 16389 /* nFields */ 57, 16390 /* *fields */ soc_EP_TO_CPU_HDR_BCM56450_A0fmt_fields, 16391 /* bits */ 448, 16392 /* flags */ 0, 16393 }, 16394 #endif /* chips */ 16395 16396 #if defined(BCM_56450_B1) 16397 { /* SOC_FORMAT_INT_EP_TO_CPU_HDR_BCM56450_B1fmt */ 16398 /* format EP_TO_CPU_HDRfmt */ 16399 /* nFields */ 57, 16400 /* *fields */ soc_EP_TO_CPU_HDR_BCM56450_A0fmt_fields, 16401 /* bits */ 448, 16402 /* flags */ 0, 16403 }, 16404 #endif /* chips */ 16405 16406 #if defined(BCM_56504_B0) 16407 { /* SOC_FORMAT_INT_EP_TO_CPU_HDR_BCM56504_B0fmt */ 16408 /* format EP_TO_CPU_HDRfmt */ 16409 /* nFields */ 29, 16410 /* *fields */ soc_EP_TO_CPU_HDR_BCM56504_B0fmt_fields, 16411 /* bits */ 256, 16412 /* flags */ 0, 16413 }, 16414 #endif /* chips */ 16415 16416 #if defined(BCM_56514_A0) 16417 { /* SOC_FORMAT_INT_EP_TO_CPU_HDR_BCM56514_A0fmt */ 16418 /* format EP_TO_CPU_HDRfmt */ 16419 /* nFields */ 30, 16420 /* *fields */ soc_EP_TO_CPU_HDR_BCM56514_A0fmt_fields, 16421 /* bits */ 256, 16422 /* flags */ 0, 16423 }, 16424 #endif /* chips */ 16425 16426 #if defined(BCM_56524_A0) 16427 { /* SOC_FORMAT_INT_EP_TO_CPU_HDR_BCM56524_A0fmt */ 16428 /* format EP_TO_CPU_HDRfmt */ 16429 /* nFields */ 57, 16430 /* *fields */ soc_EP_TO_CPU_HDR_BCM56634_A0fmt_fields, 16431 /* bits */ 416, 16432 /* flags */ 0, 16433 }, 16434 #endif /* chips */ 16435 16436 #if defined(BCM_56524_B0) 16437 { /* SOC_FORMAT_INT_EP_TO_CPU_HDR_BCM56524_B0fmt */ 16438 /* format EP_TO_CPU_HDRfmt */ 16439 /* nFields */ 57, 16440 /* *fields */ soc_EP_TO_CPU_HDR_BCM56634_A0fmt_fields, 16441 /* bits */ 416, 16442 /* flags */ 0, 16443 }, 16444 #endif /* chips */ 16445 16446 #if defined(BCM_56560_A0) 16447 { /* SOC_FORMAT_INT_EP_TO_CPU_HDR_BCM56560_A0fmt */ 16448 /* format EP_TO_CPU_HDRfmt */ 16449 /* nFields */ 75, 16450 /* *fields */ soc_EP_TO_CPU_HDR_BCM56560_A0fmt_fields, 16451 /* bits */ 416, 16452 /* flags */ 0, 16453 }, 16454 #endif /* chips */ 16455 16456 #if defined(BCM_56560_B0) 16457 { /* SOC_FORMAT_INT_EP_TO_CPU_HDR_BCM56560_B0fmt */ 16458 /* format EP_TO_CPU_HDRfmt */ 16459 /* nFields */ 75, 16460 /* *fields */ soc_EP_TO_CPU_HDR_BCM56560_A0fmt_fields, 16461 /* bits */ 416, 16462 /* flags */ 0, 16463 }, 16464 #endif /* chips */ 16465 16466 #if defined(BCM_56624_A0) 16467 { /* SOC_FORMAT_INT_EP_TO_CPU_HDR_BCM56624_A0fmt */ 16468 /* format EP_TO_CPU_HDRfmt */ 16469 /* nFields */ 55, 16470 /* *fields */ soc_EP_TO_CPU_HDR_BCM56624_A0fmt_fields, 16471 /* bits */ 416, 16472 /* flags */ 0, 16473 }, 16474 #endif /* chips */ 16475 16476 #if defined(BCM_56624_B0) 16477 { /* SOC_FORMAT_INT_EP_TO_CPU_HDR_BCM56624_B0fmt */ 16478 /* format EP_TO_CPU_HDRfmt */ 16479 /* nFields */ 55, 16480 /* *fields */ soc_EP_TO_CPU_HDR_BCM56624_A0fmt_fields, 16481 /* bits */ 416, 16482 /* flags */ 0, 16483 }, 16484 #endif /* chips */ 16485 16486 #if defined(BCM_56634_A0) 16487 { /* SOC_FORMAT_INT_EP_TO_CPU_HDR_BCM56634_A0fmt */ 16488 /* format EP_TO_CPU_HDRfmt */ 16489 /* nFields */ 57, 16490 /* *fields */ soc_EP_TO_CPU_HDR_BCM56634_A0fmt_fields, 16491 /* bits */ 416, 16492 /* flags */ 0, 16493 }, 16494 #endif /* chips */ 16495 16496 #if defined(BCM_56634_B0) 16497 { /* SOC_FORMAT_INT_EP_TO_CPU_HDR_BCM56634_B0fmt */ 16498 /* format EP_TO_CPU_HDRfmt */ 16499 /* nFields */ 57, 16500 /* *fields */ soc_EP_TO_CPU_HDR_BCM56634_A0fmt_fields, 16501 /* bits */ 416, 16502 /* flags */ 0, 16503 }, 16504 #endif /* chips */ 16505 16506 #if defined(BCM_56640_A0) 16507 { /* SOC_FORMAT_INT_EP_TO_CPU_HDR_BCM56640_A0fmt */ 16508 /* format EP_TO_CPU_HDRfmt */ 16509 /* nFields */ 56, 16510 /* *fields */ soc_EP_TO_CPU_HDR_BCM56640_A0fmt_fields, 16511 /* bits */ 416, 16512 /* flags */ 0, 16513 }, 16514 #endif /* chips */ 16515 16516 #if defined(BCM_56670_A0) 16517 { /* SOC_FORMAT_INT_EP_TO_CPU_HDR_BCM56670_A0fmt */ 16518 /* format EP_TO_CPU_HDRfmt */ 16519 /* nFields */ 76, 16520 /* *fields */ soc_EP_TO_CPU_HDR_BCM56670_A0fmt_fields, 16521 /* bits */ 416, 16522 /* flags */ 0, 16523 }, 16524 #endif /* chips */ 16525 16526 #if defined(BCM_56670_B0) 16527 { /* SOC_FORMAT_INT_EP_TO_CPU_HDR_BCM56670_B0fmt */ 16528 /* format EP_TO_CPU_HDRfmt */ 16529 /* nFields */ 76, 16530 /* *fields */ soc_EP_TO_CPU_HDR_BCM56670_A0fmt_fields, 16531 /* bits */ 416, 16532 /* flags */ 0, 16533 }, 16534 #endif /* chips */ 16535 16536 #if defined(BCM_56680_A0) 16537 { /* SOC_FORMAT_INT_EP_TO_CPU_HDR_BCM56680_A0fmt */ 16538 /* format EP_TO_CPU_HDRfmt */ 16539 /* nFields */ 55, 16540 /* *fields */ soc_EP_TO_CPU_HDR_BCM56624_A0fmt_fields, 16541 /* bits */ 416, 16542 /* flags */ 0, 16543 }, 16544 #endif /* chips */ 16545 16546 #if defined(BCM_56680_B0) 16547 { /* SOC_FORMAT_INT_EP_TO_CPU_HDR_BCM56680_B0fmt */ 16548 /* format EP_TO_CPU_HDRfmt */ 16549 /* nFields */ 55, 16550 /* *fields */ soc_EP_TO_CPU_HDR_BCM56624_A0fmt_fields, 16551 /* bits */ 416, 16552 /* flags */ 0, 16553 }, 16554 #endif /* chips */ 16555 16556 #if defined(BCM_56685_A0) 16557 { /* SOC_FORMAT_INT_EP_TO_CPU_HDR_BCM56685_A0fmt */ 16558 /* format EP_TO_CPU_HDRfmt */ 16559 /* nFields */ 57, 16560 /* *fields */ soc_EP_TO_CPU_HDR_BCM56634_A0fmt_fields, 16561 /* bits */ 416, 16562 /* flags */ 0, 16563 }, 16564 #endif /* chips */ 16565 16566 #if defined(BCM_56685_B0) 16567 { /* SOC_FORMAT_INT_EP_TO_CPU_HDR_BCM56685_B0fmt */ 16568 /* format EP_TO_CPU_HDRfmt */ 16569 /* nFields */ 57, 16570 /* *fields */ soc_EP_TO_CPU_HDR_BCM56634_A0fmt_fields, 16571 /* bits */ 416, 16572 /* flags */ 0, 16573 }, 16574 #endif /* chips */ 16575 16576 #if defined(BCM_56725_A0) 16577 { /* SOC_FORMAT_INT_EP_TO_CPU_HDR_BCM56725_A0fmt */ 16578 /* format EP_TO_CPU_HDRfmt */ 16579 /* nFields */ 50, 16580 /* *fields */ soc_EP_TO_CPU_HDR_BCM56820_A0fmt_fields, 16581 /* bits */ 416, 16582 /* flags */ 0, 16583 }, 16584 #endif /* chips */ 16585 16586 #if defined(BCM_56770_A0) 16587 { /* SOC_FORMAT_INT_EP_TO_CPU_HDR_BCM56770_A0fmt */ 16588 /* format EP_TO_CPU_HDRfmt */ 16589 /* nFields */ 19, 16590 /* *fields */ soc_EP_TO_CPU_HDR_BCM56870_A0fmt_fields, 16591 /* bits */ 480, 16592 /* flags */ 0, 16593 }, 16594 #endif /* chips */ 16595 16596 #if defined(BCM_56800_A0) 16597 { /* SOC_FORMAT_INT_EP_TO_CPU_HDR_BCM56800_A0fmt */ 16598 /* format EP_TO_CPU_HDRfmt */ 16599 /* nFields */ 33, 16600 /* *fields */ soc_EP_TO_CPU_HDR_BCM56800_A0fmt_fields, 16601 /* bits */ 256, 16602 /* flags */ 0, 16603 }, 16604 #endif /* chips */ 16605 16606 #if defined(BCM_56820_A0) 16607 { /* SOC_FORMAT_INT_EP_TO_CPU_HDR_BCM56820_A0fmt */ 16608 /* format EP_TO_CPU_HDRfmt */ 16609 /* nFields */ 50, 16610 /* *fields */ soc_EP_TO_CPU_HDR_BCM56820_A0fmt_fields, 16611 /* bits */ 416, 16612 /* flags */ 0, 16613 }, 16614 #endif /* chips */ 16615 16616 #if defined(BCM_56840_A0) 16617 { /* SOC_FORMAT_INT_EP_TO_CPU_HDR_BCM56840_A0fmt */ 16618 /* format EP_TO_CPU_HDRfmt */ 16619 /* nFields */ 63, 16620 /* *fields */ soc_EP_TO_CPU_HDR_BCM56840_A0fmt_fields, 16621 /* bits */ 416, 16622 /* flags */ 0, 16623 }, 16624 #endif /* chips */ 16625 16626 #if defined(BCM_56840_B0) 16627 { /* SOC_FORMAT_INT_EP_TO_CPU_HDR_BCM56840_B0fmt */ 16628 /* format EP_TO_CPU_HDRfmt */ 16629 /* nFields */ 62, 16630 /* *fields */ soc_EP_TO_CPU_HDR_BCM56840_B0fmt_fields, 16631 /* bits */ 416, 16632 /* flags */ 0, 16633 }, 16634 #endif /* chips */ 16635 16636 #if defined(BCM_56850_A0) 16637 { /* SOC_FORMAT_INT_EP_TO_CPU_HDR_BCM56850_A0fmt */ 16638 /* format EP_TO_CPU_HDRfmt */ 16639 /* nFields */ 70, 16640 /* *fields */ soc_EP_TO_CPU_HDR_BCM56850_A0fmt_fields, 16641 /* bits */ 416, 16642 /* flags */ 0, 16643 }, 16644 #endif /* chips */ 16645 16646 #if defined(BCM_56860_A0) 16647 { /* SOC_FORMAT_INT_EP_TO_CPU_HDR_BCM56860_A0fmt */ 16648 /* format EP_TO_CPU_HDRfmt */ 16649 /* nFields */ 70, 16650 /* *fields */ soc_EP_TO_CPU_HDR_BCM56860_A0fmt_fields, 16651 /* bits */ 416, 16652 /* flags */ 0, 16653 }, 16654 #endif /* chips */ 16655 16656 #if defined(BCM_56870_A0) 16657 { /* SOC_FORMAT_INT_EP_TO_CPU_HDR_BCM56870_A0fmt */ 16658 /* format EP_TO_CPU_HDRfmt */ 16659 /* nFields */ 19, 16660 /* *fields */ soc_EP_TO_CPU_HDR_BCM56870_A0fmt_fields, 16661 /* bits */ 480, 16662 /* flags */ 0, 16663 }, 16664 #endif /* chips */ 16665 16666 #if defined(BCM_56960_A0) 16667 { /* SOC_FORMAT_INT_EP_TO_CPU_HDR_BCM56960_A0fmt */ 16668 /* format EP_TO_CPU_HDRfmt */ 16669 /* nFields */ 70, 16670 /* *fields */ soc_EP_TO_CPU_HDR_BCM56960_A0fmt_fields, 16671 /* bits */ 416, 16672 /* flags */ 0, 16673 }, 16674 #endif /* chips */ 16675 16676 #if defined(BCM_56965_A0) 16677 { /* SOC_FORMAT_INT_EP_TO_CPU_HDR_BCM56965_A0fmt */ 16678 /* format EP_TO_CPU_HDRfmt */ 16679 /* nFields */ 70, 16680 /* *fields */ soc_EP_TO_CPU_HDR_BCM56960_A0fmt_fields, 16681 /* bits */ 416, 16682 /* flags */ 0, 16683 }, 16684 #endif /* chips */ 16685 16686 #if defined(BCM_56970_A0) 16687 { /* SOC_FORMAT_INT_EP_TO_CPU_HDR_BCM56970_A0fmt */ 16688 /* format EP_TO_CPU_HDRfmt */ 16689 /* nFields */ 69, 16690 /* *fields */ soc_EP_TO_CPU_HDR_BCM56970_A0fmt_fields, 16691 /* bits */ 416, 16692 /* flags */ 0, 16693 }, 16694 #endif /* chips */ 16695 16696 #if defined(BCM_56980_A0) 16697 { /* SOC_FORMAT_INT_EP_TO_CPU_HDR_BCM56980_A0fmt */ 16698 /* format EP_TO_CPU_HDRfmt */ 16699 /* nFields */ 2, 16700 /* *fields */ soc_EP_TO_CPU_HDR_BCM56980_A0fmt_fields, 16701 /* bits */ 416, 16702 /* flags */ 0, 16703 }, 16704 #endif /* chips */ 16705 16706 #if defined(BCM_56980_B0) 16707 { /* SOC_FORMAT_INT_EP_TO_CPU_HDR_BCM56980_B0fmt */ 16708 /* format EP_TO_CPU_HDRfmt */ 16709 /* nFields */ 2, 16710 /* *fields */ soc_EP_TO_CPU_HDR_BCM56980_A0fmt_fields, 16711 /* bits */ 416, 16712 /* flags */ 0, 16713 }, 16714 #endif /* chips */ 16715 16716 #if defined(BCM_88732_A0) 16717 { /* SOC_FORMAT_INT_EP_TO_CPU_HDR_BCM88732_A0fmt */ 16718 /* format EP_TO_CPU_HDRfmt */ 16719 /* nFields */ 57, 16720 /* *fields */ soc_EP_TO_CPU_HDR_BCM88732_A0fmt_fields, 16721 /* bits */ 416, 16722 /* flags */ 0, 16723 }, 16724 #endif /* chips */ 16725 16726 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 16727 { /* SOC_FORMAT_INT_EP_TO_EDB_CTRL_BUSfmt */ 16728 /* format EP_TO_EDB_CTRL_BUSfmt */ 16729 /* nFields */ 12, 16730 /* *fields */ soc_EP_TO_EDB_CTRL_BUSfmt_fields, 16731 /* bits */ 59, 16732 /* flags */ 0, 16733 }, 16734 #endif /* chips */ 16735 16736 #if defined(BCM_56980_A0) 16737 { /* SOC_FORMAT_INT_EP_TO_EDB_DATA_BUSfmt */ 16738 /* format EP_TO_EDB_DATA_BUSfmt */ 16739 /* nFields */ 1, 16740 /* *fields */ soc_EFPMOD_TO_EPOST_DATA_BUSfmt_fields, 16741 /* bits */ 2608, 16742 /* flags */ 0, 16743 }, 16744 #endif /* chips */ 16745 16746 #if defined(BCM_56980_B0) 16747 { /* SOC_FORMAT_INT_EP_TO_EDB_DATA_BUS_BCM56980_B0fmt */ 16748 /* format EP_TO_EDB_DATA_BUSfmt */ 16749 /* nFields */ 1, 16750 /* *fields */ soc_EFPMOD_TO_EPOST_DATA_BUSfmt_fields, 16751 /* bits */ 2608, 16752 /* flags */ 0, 16753 }, 16754 #endif /* chips */ 16755 16756 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 16757 { /* SOC_FORMAT_INT_EP_TO_EDB_EARLY_CTRL_BUSfmt */ 16758 /* format EP_TO_EDB_EARLY_CTRL_BUSfmt */ 16759 /* nFields */ 7, 16760 /* *fields */ soc_EP_TO_EDB_EARLY_CTRL_BUSfmt_fields, 16761 /* bits */ 28, 16762 /* flags */ 0, 16763 }, 16764 #endif /* chips */ 16765 16766 #if defined(BCM_56334_A0) 16767 { /* SOC_FORMAT_INT_EP_TO_GPORT_CTRL_BUSfmt */ 16768 /* format EP_TO_GPORT_CTRL_BUSfmt */ 16769 /* nFields */ 7, 16770 /* *fields */ soc_EP_TO_GPORT_CTRL_BUSfmt_fields, 16771 /* bits */ 13, 16772 /* flags */ 0, 16773 }, 16774 #endif /* chips */ 16775 16776 #if defined(BCM_53400_A0) 16777 { /* SOC_FORMAT_INT_EP_TO_GPORT_CTRL_BUS_BCM53400_A0fmt */ 16778 /* format EP_TO_GPORT_CTRL_BUSfmt */ 16779 /* nFields */ 7, 16780 /* *fields */ soc_EP_TO_GPORT_CTRL_BUS_BCM53400_A0fmt_fields, 16781 /* bits */ 13, 16782 /* flags */ 0, 16783 }, 16784 #endif /* chips */ 16785 16786 #if defined(BCM_53540_A0) 16787 { /* SOC_FORMAT_INT_EP_TO_GPORT_CTRL_BUS_BCM53540_A0fmt */ 16788 /* format EP_TO_GPORT_CTRL_BUSfmt */ 16789 /* nFields */ 7, 16790 /* *fields */ soc_EP_TO_GPORT_CTRL_BUS_BCM53400_A0fmt_fields, 16791 /* bits */ 13, 16792 /* flags */ 0, 16793 }, 16794 #endif /* chips */ 16795 16796 #if defined(BCM_53570_A0) 16797 { /* SOC_FORMAT_INT_EP_TO_GPORT_CTRL_BUS_BCM53570_A0fmt */ 16798 /* format EP_TO_GPORT_CTRL_BUSfmt */ 16799 /* nFields */ 7, 16800 /* *fields */ soc_EP_TO_GPORT_CTRL_BUS_BCM53400_A0fmt_fields, 16801 /* bits */ 13, 16802 /* flags */ 0, 16803 }, 16804 #endif /* chips */ 16805 16806 #if defined(BCM_53570_B0) 16807 { /* SOC_FORMAT_INT_EP_TO_GPORT_CTRL_BUS_BCM53570_B0fmt */ 16808 /* format EP_TO_GPORT_CTRL_BUSfmt */ 16809 /* nFields */ 7, 16810 /* *fields */ soc_EP_TO_GPORT_CTRL_BUS_BCM53400_A0fmt_fields, 16811 /* bits */ 13, 16812 /* flags */ 0, 16813 }, 16814 #endif /* chips */ 16815 16816 #if defined(BCM_56142_A0) 16817 { /* SOC_FORMAT_INT_EP_TO_GPORT_CTRL_BUS_BCM56142_A0fmt */ 16818 /* format EP_TO_GPORT_CTRL_BUSfmt */ 16819 /* nFields */ 7, 16820 /* *fields */ soc_EP_TO_GPORT_CTRL_BUSfmt_fields, 16821 /* bits */ 13, 16822 /* flags */ 0, 16823 }, 16824 #endif /* chips */ 16825 16826 #if defined(BCM_56150_A0) 16827 { /* SOC_FORMAT_INT_EP_TO_GPORT_CTRL_BUS_BCM56150_A0fmt */ 16828 /* format EP_TO_GPORT_CTRL_BUSfmt */ 16829 /* nFields */ 7, 16830 /* *fields */ soc_EP_TO_GPORT_CTRL_BUS_BCM56150_A0fmt_fields, 16831 /* bits */ 13, 16832 /* flags */ 0, 16833 }, 16834 #endif /* chips */ 16835 16836 #if defined(BCM_56160_A0) 16837 { /* SOC_FORMAT_INT_EP_TO_GPORT_CTRL_BUS_BCM56160_A0fmt */ 16838 /* format EP_TO_GPORT_CTRL_BUSfmt */ 16839 /* nFields */ 7, 16840 /* *fields */ soc_EP_TO_GPORT_CTRL_BUS_BCM53400_A0fmt_fields, 16841 /* bits */ 13, 16842 /* flags */ 0, 16843 }, 16844 #endif /* chips */ 16845 16846 #if defined(BCM_56260_A0) 16847 { /* SOC_FORMAT_INT_EP_TO_GPORT_CTRL_BUS_BCM56260_A0fmt */ 16848 /* format EP_TO_GPORT_CTRL_BUSfmt */ 16849 /* nFields */ 11, 16850 /* *fields */ soc_EP_TO_GPORT_CTRL_BUS_BCM56260_A0fmt_fields, 16851 /* bits */ 25, 16852 /* flags */ 0, 16853 }, 16854 #endif /* chips */ 16855 16856 #if defined(BCM_56260_B0) 16857 { /* SOC_FORMAT_INT_EP_TO_GPORT_CTRL_BUS_BCM56260_B0fmt */ 16858 /* format EP_TO_GPORT_CTRL_BUSfmt */ 16859 /* nFields */ 11, 16860 /* *fields */ soc_EP_TO_GPORT_CTRL_BUS_BCM56260_A0fmt_fields, 16861 /* bits */ 25, 16862 /* flags */ 0, 16863 }, 16864 #endif /* chips */ 16865 16866 #if defined(BCM_56270_A0) 16867 { /* SOC_FORMAT_INT_EP_TO_GPORT_CTRL_BUS_BCM56270_A0fmt */ 16868 /* format EP_TO_GPORT_CTRL_BUSfmt */ 16869 /* nFields */ 11, 16870 /* *fields */ soc_EP_TO_GPORT_CTRL_BUS_BCM56260_A0fmt_fields, 16871 /* bits */ 25, 16872 /* flags */ 0, 16873 }, 16874 #endif /* chips */ 16875 16876 #if defined(BCM_56334_B0) 16877 { /* SOC_FORMAT_INT_EP_TO_GPORT_CTRL_BUS_BCM56334_B0fmt */ 16878 /* format EP_TO_GPORT_CTRL_BUSfmt */ 16879 /* nFields */ 7, 16880 /* *fields */ soc_EP_TO_GPORT_CTRL_BUSfmt_fields, 16881 /* bits */ 13, 16882 /* flags */ 0, 16883 }, 16884 #endif /* chips */ 16885 16886 #if defined(BCM_56440_A0) 16887 { /* SOC_FORMAT_INT_EP_TO_GPORT_CTRL_BUS_BCM56440_A0fmt */ 16888 /* format EP_TO_GPORT_CTRL_BUSfmt */ 16889 /* nFields */ 11, 16890 /* *fields */ soc_EP_TO_GPORT_CTRL_BUS_BCM56440_A0fmt_fields, 16891 /* bits */ 25, 16892 /* flags */ 0, 16893 }, 16894 #endif /* chips */ 16895 16896 #if defined(BCM_56440_B0) 16897 { /* SOC_FORMAT_INT_EP_TO_GPORT_CTRL_BUS_BCM56440_B0fmt */ 16898 /* format EP_TO_GPORT_CTRL_BUSfmt */ 16899 /* nFields */ 11, 16900 /* *fields */ soc_EP_TO_GPORT_CTRL_BUS_BCM56440_A0fmt_fields, 16901 /* bits */ 25, 16902 /* flags */ 0, 16903 }, 16904 #endif /* chips */ 16905 16906 #if defined(BCM_56450_A0) 16907 { /* SOC_FORMAT_INT_EP_TO_GPORT_CTRL_BUS_BCM56450_A0fmt */ 16908 /* format EP_TO_GPORT_CTRL_BUSfmt */ 16909 /* nFields */ 11, 16910 /* *fields */ soc_EP_TO_GPORT_CTRL_BUS_BCM56450_A0fmt_fields, 16911 /* bits */ 25, 16912 /* flags */ 0, 16913 }, 16914 #endif /* chips */ 16915 16916 #if defined(BCM_56450_B0) 16917 { /* SOC_FORMAT_INT_EP_TO_GPORT_CTRL_BUS_BCM56450_B0fmt */ 16918 /* format EP_TO_GPORT_CTRL_BUSfmt */ 16919 /* nFields */ 11, 16920 /* *fields */ soc_EP_TO_GPORT_CTRL_BUS_BCM56450_A0fmt_fields, 16921 /* bits */ 25, 16922 /* flags */ 0, 16923 }, 16924 #endif /* chips */ 16925 16926 #if defined(BCM_56450_B1) 16927 { /* SOC_FORMAT_INT_EP_TO_GPORT_CTRL_BUS_BCM56450_B1fmt */ 16928 /* format EP_TO_GPORT_CTRL_BUSfmt */ 16929 /* nFields */ 11, 16930 /* *fields */ soc_EP_TO_GPORT_CTRL_BUS_BCM56450_A0fmt_fields, 16931 /* bits */ 25, 16932 /* flags */ 0, 16933 }, 16934 #endif /* chips */ 16935 16936 #if defined(BCM_56524_A0) || defined(BCM_56524_B0) || \ 16937 defined(BCM_56634_A0) || defined(BCM_56634_B0) 16938 { /* SOC_FORMAT_INT_EP_TO_MMU_REDIRECTION_BUSfmt */ 16939 /* format EP_TO_MMU_REDIRECTION_BUSfmt */ 16940 /* nFields */ 27, 16941 /* *fields */ soc_EP_TO_MMU_REDIRECTION_BUSfmt_fields, 16942 /* bits */ 203, 16943 /* flags */ 0, 16944 }, 16945 #endif /* chips */ 16946 16947 #if defined(BCM_56260_A0) 16948 { /* SOC_FORMAT_INT_EP_TO_MMU_REDIRECTION_BUS_BCM56260_A0fmt */ 16949 /* format EP_TO_MMU_REDIRECTION_BUSfmt */ 16950 /* nFields */ 37, 16951 /* *fields */ soc_EP_TO_MMU_REDIRECTION_BUS_BCM56260_A0fmt_fields, 16952 /* bits */ 302, 16953 /* flags */ 0, 16954 }, 16955 #endif /* chips */ 16956 16957 #if defined(BCM_56260_B0) 16958 { /* SOC_FORMAT_INT_EP_TO_MMU_REDIRECTION_BUS_BCM56260_B0fmt */ 16959 /* format EP_TO_MMU_REDIRECTION_BUSfmt */ 16960 /* nFields */ 37, 16961 /* *fields */ soc_EP_TO_MMU_REDIRECTION_BUS_BCM56260_A0fmt_fields, 16962 /* bits */ 302, 16963 /* flags */ 0, 16964 }, 16965 #endif /* chips */ 16966 16967 #if defined(BCM_56270_A0) 16968 { /* SOC_FORMAT_INT_EP_TO_MMU_REDIRECTION_BUS_BCM56270_A0fmt */ 16969 /* format EP_TO_MMU_REDIRECTION_BUSfmt */ 16970 /* nFields */ 38, 16971 /* *fields */ soc_EP_TO_MMU_REDIRECTION_BUS_BCM56270_A0fmt_fields, 16972 /* bits */ 302, 16973 /* flags */ 0, 16974 }, 16975 #endif /* chips */ 16976 16977 #if defined(BCM_56340_A0) 16978 { /* SOC_FORMAT_INT_EP_TO_MMU_REDIRECTION_BUS_BCM56340_A0fmt */ 16979 /* format EP_TO_MMU_REDIRECTION_BUSfmt */ 16980 /* nFields */ 25, 16981 /* *fields */ soc_EP_TO_MMU_REDIRECTION_BUS_BCM56340_A0fmt_fields, 16982 /* bits */ 170, 16983 /* flags */ 0, 16984 }, 16985 #endif /* chips */ 16986 16987 #if defined(BCM_56450_A0) 16988 { /* SOC_FORMAT_INT_EP_TO_MMU_REDIRECTION_BUS_BCM56450_A0fmt */ 16989 /* format EP_TO_MMU_REDIRECTION_BUSfmt */ 16990 /* nFields */ 36, 16991 /* *fields */ soc_EP_TO_MMU_REDIRECTION_BUS_BCM56450_A0fmt_fields, 16992 /* bits */ 302, 16993 /* flags */ 0, 16994 }, 16995 #endif /* chips */ 16996 16997 #if defined(BCM_56450_B0) 16998 { /* SOC_FORMAT_INT_EP_TO_MMU_REDIRECTION_BUS_BCM56450_B0fmt */ 16999 /* format EP_TO_MMU_REDIRECTION_BUSfmt */ 17000 /* nFields */ 36, 17001 /* *fields */ soc_EP_TO_MMU_REDIRECTION_BUS_BCM56450_A0fmt_fields, 17002 /* bits */ 302, 17003 /* flags */ 0, 17004 }, 17005 #endif /* chips */ 17006 17007 #if defined(BCM_56450_B1) 17008 { /* SOC_FORMAT_INT_EP_TO_MMU_REDIRECTION_BUS_BCM56450_B1fmt */ 17009 /* format EP_TO_MMU_REDIRECTION_BUSfmt */ 17010 /* nFields */ 36, 17011 /* *fields */ soc_EP_TO_MMU_REDIRECTION_BUS_BCM56450_A0fmt_fields, 17012 /* bits */ 302, 17013 /* flags */ 0, 17014 }, 17015 #endif /* chips */ 17016 17017 #if defined(BCM_56640_A0) 17018 { /* SOC_FORMAT_INT_EP_TO_MMU_REDIRECTION_BUS_BCM56640_A0fmt */ 17019 /* format EP_TO_MMU_REDIRECTION_BUSfmt */ 17020 /* nFields */ 24, 17021 /* *fields */ soc_EP_TO_MMU_REDIRECTION_BUS_BCM56640_A0fmt_fields, 17022 /* bits */ 170, 17023 /* flags */ 0, 17024 }, 17025 #endif /* chips */ 17026 17027 #if defined(BCM_56685_A0) 17028 { /* SOC_FORMAT_INT_EP_TO_MMU_REDIRECTION_BUS_BCM56685_A0fmt */ 17029 /* format EP_TO_MMU_REDIRECTION_BUSfmt */ 17030 /* nFields */ 27, 17031 /* *fields */ soc_EP_TO_MMU_REDIRECTION_BUSfmt_fields, 17032 /* bits */ 203, 17033 /* flags */ 0, 17034 }, 17035 #endif /* chips */ 17036 17037 #if defined(BCM_56685_B0) 17038 { /* SOC_FORMAT_INT_EP_TO_MMU_REDIRECTION_BUS_BCM56685_B0fmt */ 17039 /* format EP_TO_MMU_REDIRECTION_BUSfmt */ 17040 /* nFields */ 27, 17041 /* *fields */ soc_EP_TO_MMU_REDIRECTION_BUSfmt_fields, 17042 /* bits */ 203, 17043 /* flags */ 0, 17044 }, 17045 #endif /* chips */ 17046 17047 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \ 17048 defined(BCM_56450_A0) || defined(BCM_56450_B0) || \ 17049 defined(BCM_56450_B1) || defined(BCM_56640_A0) || \ 17050 defined(BCM_56850_A0) || defined(BCM_56860_A0) 17051 { /* SOC_FORMAT_INT_EP_TO_PORT_1588_CTRL_BUSfmt */ 17052 /* format EP_TO_PORT_1588_CTRL_BUSfmt */ 17053 /* nFields */ 5, 17054 /* *fields */ soc_EP_TO_PORT_1588_CTRL_BUSfmt_fields, 17055 /* bits */ 12, 17056 /* flags */ 0, 17057 }, 17058 #endif /* chips */ 17059 17060 #if defined(BCM_53400_A0) 17061 { /* SOC_FORMAT_INT_EP_TO_PORT_1588_CTRL_BUS_BCM53400_A0fmt */ 17062 /* format EP_TO_PORT_1588_CTRL_BUSfmt */ 17063 /* nFields */ 5, 17064 /* *fields */ soc_EP_TO_PORT_1588_CTRL_BUS_BCM53400_A0fmt_fields, 17065 /* bits */ 12, 17066 /* flags */ 0, 17067 }, 17068 #endif /* chips */ 17069 17070 #if defined(BCM_53540_A0) 17071 { /* SOC_FORMAT_INT_EP_TO_PORT_1588_CTRL_BUS_BCM53540_A0fmt */ 17072 /* format EP_TO_PORT_1588_CTRL_BUSfmt */ 17073 /* nFields */ 5, 17074 /* *fields */ soc_EP_TO_PORT_1588_CTRL_BUS_BCM53400_A0fmt_fields, 17075 /* bits */ 12, 17076 /* flags */ 0, 17077 }, 17078 #endif /* chips */ 17079 17080 #if defined(BCM_53570_A0) 17081 { /* SOC_FORMAT_INT_EP_TO_PORT_1588_CTRL_BUS_BCM53570_A0fmt */ 17082 /* format EP_TO_PORT_1588_CTRL_BUSfmt */ 17083 /* nFields */ 5, 17084 /* *fields */ soc_EP_TO_PORT_1588_CTRL_BUS_BCM53400_A0fmt_fields, 17085 /* bits */ 12, 17086 /* flags */ 0, 17087 }, 17088 #endif /* chips */ 17089 17090 #if defined(BCM_53570_B0) 17091 { /* SOC_FORMAT_INT_EP_TO_PORT_1588_CTRL_BUS_BCM53570_B0fmt */ 17092 /* format EP_TO_PORT_1588_CTRL_BUSfmt */ 17093 /* nFields */ 5, 17094 /* *fields */ soc_EP_TO_PORT_1588_CTRL_BUS_BCM53400_A0fmt_fields, 17095 /* bits */ 12, 17096 /* flags */ 0, 17097 }, 17098 #endif /* chips */ 17099 17100 #if defined(BCM_56160_A0) 17101 { /* SOC_FORMAT_INT_EP_TO_PORT_1588_CTRL_BUS_BCM56160_A0fmt */ 17102 /* format EP_TO_PORT_1588_CTRL_BUSfmt */ 17103 /* nFields */ 5, 17104 /* *fields */ soc_EP_TO_PORT_1588_CTRL_BUS_BCM53400_A0fmt_fields, 17105 /* bits */ 12, 17106 /* flags */ 0, 17107 }, 17108 #endif /* chips */ 17109 17110 #if defined(BCM_56260_A0) 17111 { /* SOC_FORMAT_INT_EP_TO_PORT_1588_CTRL_BUS_BCM56260_A0fmt */ 17112 /* format EP_TO_PORT_1588_CTRL_BUSfmt */ 17113 /* nFields */ 5, 17114 /* *fields */ soc_EP_TO_PORT_1588_CTRL_BUS_BCM53400_A0fmt_fields, 17115 /* bits */ 12, 17116 /* flags */ 0, 17117 }, 17118 #endif /* chips */ 17119 17120 #if defined(BCM_56260_B0) 17121 { /* SOC_FORMAT_INT_EP_TO_PORT_1588_CTRL_BUS_BCM56260_B0fmt */ 17122 /* format EP_TO_PORT_1588_CTRL_BUSfmt */ 17123 /* nFields */ 5, 17124 /* *fields */ soc_EP_TO_PORT_1588_CTRL_BUS_BCM53400_A0fmt_fields, 17125 /* bits */ 12, 17126 /* flags */ 0, 17127 }, 17128 #endif /* chips */ 17129 17130 #if defined(BCM_56270_A0) 17131 { /* SOC_FORMAT_INT_EP_TO_PORT_1588_CTRL_BUS_BCM56270_A0fmt */ 17132 /* format EP_TO_PORT_1588_CTRL_BUSfmt */ 17133 /* nFields */ 5, 17134 /* *fields */ soc_EP_TO_PORT_1588_CTRL_BUS_BCM53400_A0fmt_fields, 17135 /* bits */ 12, 17136 /* flags */ 0, 17137 }, 17138 #endif /* chips */ 17139 17140 #if defined(BCM_56370_A0) 17141 { /* SOC_FORMAT_INT_EP_TO_PORT_1588_CTRL_BUS_BCM56370_A0fmt */ 17142 /* format EP_TO_PORT_1588_CTRL_BUSfmt */ 17143 /* nFields */ 5, 17144 /* *fields */ soc_EP_TO_PORT_1588_CTRL_BUS_BCM53400_A0fmt_fields, 17145 /* bits */ 12, 17146 /* flags */ 0, 17147 }, 17148 #endif /* chips */ 17149 17150 #if defined(BCM_56560_A0) 17151 { /* SOC_FORMAT_INT_EP_TO_PORT_1588_CTRL_BUS_BCM56560_A0fmt */ 17152 /* format EP_TO_PORT_1588_CTRL_BUSfmt */ 17153 /* nFields */ 5, 17154 /* *fields */ soc_EP_TO_PORT_1588_CTRL_BUS_BCM53400_A0fmt_fields, 17155 /* bits */ 12, 17156 /* flags */ 0, 17157 }, 17158 #endif /* chips */ 17159 17160 #if defined(BCM_56560_B0) 17161 { /* SOC_FORMAT_INT_EP_TO_PORT_1588_CTRL_BUS_BCM56560_B0fmt */ 17162 /* format EP_TO_PORT_1588_CTRL_BUSfmt */ 17163 /* nFields */ 5, 17164 /* *fields */ soc_EP_TO_PORT_1588_CTRL_BUS_BCM53400_A0fmt_fields, 17165 /* bits */ 12, 17166 /* flags */ 0, 17167 }, 17168 #endif /* chips */ 17169 17170 #if defined(BCM_56670_A0) 17171 { /* SOC_FORMAT_INT_EP_TO_PORT_1588_CTRL_BUS_BCM56670_A0fmt */ 17172 /* format EP_TO_PORT_1588_CTRL_BUSfmt */ 17173 /* nFields */ 5, 17174 /* *fields */ soc_EP_TO_PORT_1588_CTRL_BUS_BCM53400_A0fmt_fields, 17175 /* bits */ 12, 17176 /* flags */ 0, 17177 }, 17178 #endif /* chips */ 17179 17180 #if defined(BCM_56670_B0) 17181 { /* SOC_FORMAT_INT_EP_TO_PORT_1588_CTRL_BUS_BCM56670_B0fmt */ 17182 /* format EP_TO_PORT_1588_CTRL_BUSfmt */ 17183 /* nFields */ 5, 17184 /* *fields */ soc_EP_TO_PORT_1588_CTRL_BUS_BCM53400_A0fmt_fields, 17185 /* bits */ 12, 17186 /* flags */ 0, 17187 }, 17188 #endif /* chips */ 17189 17190 #if defined(BCM_56770_A0) 17191 { /* SOC_FORMAT_INT_EP_TO_PORT_1588_CTRL_BUS_BCM56770_A0fmt */ 17192 /* format EP_TO_PORT_1588_CTRL_BUSfmt */ 17193 /* nFields */ 5, 17194 /* *fields */ soc_EP_TO_PORT_1588_CTRL_BUS_BCM53400_A0fmt_fields, 17195 /* bits */ 12, 17196 /* flags */ 0, 17197 }, 17198 #endif /* chips */ 17199 17200 #if defined(BCM_56870_A0) 17201 { /* SOC_FORMAT_INT_EP_TO_PORT_1588_CTRL_BUS_BCM56870_A0fmt */ 17202 /* format EP_TO_PORT_1588_CTRL_BUSfmt */ 17203 /* nFields */ 5, 17204 /* *fields */ soc_EP_TO_PORT_1588_CTRL_BUS_BCM53400_A0fmt_fields, 17205 /* bits */ 12, 17206 /* flags */ 0, 17207 }, 17208 #endif /* chips */ 17209 17210 #if defined(BCM_56960_A0) 17211 { /* SOC_FORMAT_INT_EP_TO_PORT_1588_CTRL_BUS_BCM56960_A0fmt */ 17212 /* format EP_TO_PORT_1588_CTRL_BUSfmt */ 17213 /* nFields */ 5, 17214 /* *fields */ soc_EP_TO_PORT_1588_CTRL_BUS_BCM53400_A0fmt_fields, 17215 /* bits */ 12, 17216 /* flags */ 0, 17217 }, 17218 #endif /* chips */ 17219 17220 #if defined(BCM_56965_A0) 17221 { /* SOC_FORMAT_INT_EP_TO_PORT_1588_CTRL_BUS_BCM56965_A0fmt */ 17222 /* format EP_TO_PORT_1588_CTRL_BUSfmt */ 17223 /* nFields */ 5, 17224 /* *fields */ soc_EP_TO_PORT_1588_CTRL_BUS_BCM53400_A0fmt_fields, 17225 /* bits */ 12, 17226 /* flags */ 0, 17227 }, 17228 #endif /* chips */ 17229 17230 #if defined(BCM_56970_A0) 17231 { /* SOC_FORMAT_INT_EP_TO_PORT_1588_CTRL_BUS_BCM56970_A0fmt */ 17232 /* format EP_TO_PORT_1588_CTRL_BUSfmt */ 17233 /* nFields */ 5, 17234 /* *fields */ soc_EP_TO_PORT_1588_CTRL_BUS_BCM53400_A0fmt_fields, 17235 /* bits */ 12, 17236 /* flags */ 0, 17237 }, 17238 #endif /* chips */ 17239 17240 #if defined(BCM_56980_A0) 17241 { /* SOC_FORMAT_INT_EP_TO_PORT_1588_CTRL_BUS_BCM56980_A0fmt */ 17242 /* format EP_TO_PORT_1588_CTRL_BUSfmt */ 17243 /* nFields */ 5, 17244 /* *fields */ soc_EP_TO_PORT_1588_CTRL_BUS_BCM53400_A0fmt_fields, 17245 /* bits */ 12, 17246 /* flags */ 0, 17247 }, 17248 #endif /* chips */ 17249 17250 #if defined(BCM_56980_B0) 17251 { /* SOC_FORMAT_INT_EP_TO_PORT_1588_CTRL_BUS_BCM56980_B0fmt */ 17252 /* format EP_TO_PORT_1588_CTRL_BUSfmt */ 17253 /* nFields */ 5, 17254 /* *fields */ soc_EP_TO_PORT_1588_CTRL_BUS_BCM53400_A0fmt_fields, 17255 /* bits */ 12, 17256 /* flags */ 0, 17257 }, 17258 #endif /* chips */ 17259 17260 #if defined(BCM_56725_A0) || defined(BCM_56820_A0) 17261 { /* SOC_FORMAT_INT_EP_TO_QGPORT_CTRL_BUSfmt */ 17262 /* format EP_TO_QGPORT_CTRL_BUSfmt */ 17263 /* nFields */ 6, 17264 /* *fields */ soc_EP_TO_QGPORT_CTRL_BUSfmt_fields, 17265 /* bits */ 11, 17266 /* flags */ 0, 17267 }, 17268 #endif /* chips */ 17269 17270 #if defined(BCM_56524_B0) || defined(BCM_56624_A0) || \ 17271 defined(BCM_56634_B0) 17272 { /* SOC_FORMAT_INT_EP_TO_SPORT_CTRL_BUSfmt */ 17273 /* format EP_TO_SPORT_CTRL_BUSfmt */ 17274 /* nFields */ 5, 17275 /* *fields */ soc_EP_TO_SPORT_CTRL_BUSfmt_fields, 17276 /* bits */ 7, 17277 /* flags */ 0, 17278 }, 17279 #endif /* chips */ 17280 17281 #if defined(BCM_56340_A0) 17282 { /* SOC_FORMAT_INT_EP_TO_SPORT_CTRL_BUS_BCM56340_A0fmt */ 17283 /* format EP_TO_SPORT_CTRL_BUSfmt */ 17284 /* nFields */ 5, 17285 /* *fields */ soc_EP_TO_SPORT_CTRL_BUS_BCM56640_A0fmt_fields, 17286 /* bits */ 7, 17287 /* flags */ 0, 17288 }, 17289 #endif /* chips */ 17290 17291 #if defined(BCM_56370_A0) 17292 { /* SOC_FORMAT_INT_EP_TO_SPORT_CTRL_BUS_BCM56370_A0fmt */ 17293 /* format EP_TO_SPORT_CTRL_BUSfmt */ 17294 /* nFields */ 5, 17295 /* *fields */ soc_EP_TO_SPORT_CTRL_BUS_BCM56960_A0fmt_fields, 17296 /* bits */ 7, 17297 /* flags */ 0, 17298 }, 17299 #endif /* chips */ 17300 17301 #if defined(BCM_56524_A0) 17302 { /* SOC_FORMAT_INT_EP_TO_SPORT_CTRL_BUS_BCM56524_A0fmt */ 17303 /* format EP_TO_SPORT_CTRL_BUSfmt */ 17304 /* nFields */ 5, 17305 /* *fields */ soc_EP_TO_SPORT_CTRL_BUSfmt_fields, 17306 /* bits */ 7, 17307 /* flags */ 0, 17308 }, 17309 #endif /* chips */ 17310 17311 #if defined(BCM_56560_A0) 17312 { /* SOC_FORMAT_INT_EP_TO_SPORT_CTRL_BUS_BCM56560_A0fmt */ 17313 /* format EP_TO_SPORT_CTRL_BUSfmt */ 17314 /* nFields */ 5, 17315 /* *fields */ soc_EP_TO_SPORT_CTRL_BUS_BCM56960_A0fmt_fields, 17316 /* bits */ 7, 17317 /* flags */ 0, 17318 }, 17319 #endif /* chips */ 17320 17321 #if defined(BCM_56560_B0) 17322 { /* SOC_FORMAT_INT_EP_TO_SPORT_CTRL_BUS_BCM56560_B0fmt */ 17323 /* format EP_TO_SPORT_CTRL_BUSfmt */ 17324 /* nFields */ 5, 17325 /* *fields */ soc_EP_TO_SPORT_CTRL_BUS_BCM56960_A0fmt_fields, 17326 /* bits */ 7, 17327 /* flags */ 0, 17328 }, 17329 #endif /* chips */ 17330 17331 #if defined(BCM_56624_B0) 17332 { /* SOC_FORMAT_INT_EP_TO_SPORT_CTRL_BUS_BCM56624_B0fmt */ 17333 /* format EP_TO_SPORT_CTRL_BUSfmt */ 17334 /* nFields */ 5, 17335 /* *fields */ soc_EP_TO_SPORT_CTRL_BUSfmt_fields, 17336 /* bits */ 7, 17337 /* flags */ 0, 17338 }, 17339 #endif /* chips */ 17340 17341 #if defined(BCM_56634_A0) 17342 { /* SOC_FORMAT_INT_EP_TO_SPORT_CTRL_BUS_BCM56634_A0fmt */ 17343 /* format EP_TO_SPORT_CTRL_BUSfmt */ 17344 /* nFields */ 5, 17345 /* *fields */ soc_EP_TO_SPORT_CTRL_BUSfmt_fields, 17346 /* bits */ 7, 17347 /* flags */ 0, 17348 }, 17349 #endif /* chips */ 17350 17351 #if defined(BCM_56640_A0) 17352 { /* SOC_FORMAT_INT_EP_TO_SPORT_CTRL_BUS_BCM56640_A0fmt */ 17353 /* format EP_TO_SPORT_CTRL_BUSfmt */ 17354 /* nFields */ 5, 17355 /* *fields */ soc_EP_TO_SPORT_CTRL_BUS_BCM56640_A0fmt_fields, 17356 /* bits */ 7, 17357 /* flags */ 0, 17358 }, 17359 #endif /* chips */ 17360 17361 #if defined(BCM_56670_A0) 17362 { /* SOC_FORMAT_INT_EP_TO_SPORT_CTRL_BUS_BCM56670_A0fmt */ 17363 /* format EP_TO_SPORT_CTRL_BUSfmt */ 17364 /* nFields */ 5, 17365 /* *fields */ soc_EP_TO_SPORT_CTRL_BUS_BCM56960_A0fmt_fields, 17366 /* bits */ 7, 17367 /* flags */ 0, 17368 }, 17369 #endif /* chips */ 17370 17371 #if defined(BCM_56670_B0) 17372 { /* SOC_FORMAT_INT_EP_TO_SPORT_CTRL_BUS_BCM56670_B0fmt */ 17373 /* format EP_TO_SPORT_CTRL_BUSfmt */ 17374 /* nFields */ 5, 17375 /* *fields */ soc_EP_TO_SPORT_CTRL_BUS_BCM56960_A0fmt_fields, 17376 /* bits */ 7, 17377 /* flags */ 0, 17378 }, 17379 #endif /* chips */ 17380 17381 #if defined(BCM_56680_A0) 17382 { /* SOC_FORMAT_INT_EP_TO_SPORT_CTRL_BUS_BCM56680_A0fmt */ 17383 /* format EP_TO_SPORT_CTRL_BUSfmt */ 17384 /* nFields */ 5, 17385 /* *fields */ soc_EP_TO_SPORT_CTRL_BUSfmt_fields, 17386 /* bits */ 7, 17387 /* flags */ 0, 17388 }, 17389 #endif /* chips */ 17390 17391 #if defined(BCM_56680_B0) 17392 { /* SOC_FORMAT_INT_EP_TO_SPORT_CTRL_BUS_BCM56680_B0fmt */ 17393 /* format EP_TO_SPORT_CTRL_BUSfmt */ 17394 /* nFields */ 5, 17395 /* *fields */ soc_EP_TO_SPORT_CTRL_BUSfmt_fields, 17396 /* bits */ 7, 17397 /* flags */ 0, 17398 }, 17399 #endif /* chips */ 17400 17401 #if defined(BCM_56685_A0) 17402 { /* SOC_FORMAT_INT_EP_TO_SPORT_CTRL_BUS_BCM56685_A0fmt */ 17403 /* format EP_TO_SPORT_CTRL_BUSfmt */ 17404 /* nFields */ 5, 17405 /* *fields */ soc_EP_TO_SPORT_CTRL_BUSfmt_fields, 17406 /* bits */ 7, 17407 /* flags */ 0, 17408 }, 17409 #endif /* chips */ 17410 17411 #if defined(BCM_56685_B0) 17412 { /* SOC_FORMAT_INT_EP_TO_SPORT_CTRL_BUS_BCM56685_B0fmt */ 17413 /* format EP_TO_SPORT_CTRL_BUSfmt */ 17414 /* nFields */ 5, 17415 /* *fields */ soc_EP_TO_SPORT_CTRL_BUSfmt_fields, 17416 /* bits */ 7, 17417 /* flags */ 0, 17418 }, 17419 #endif /* chips */ 17420 17421 #if defined(BCM_56770_A0) 17422 { /* SOC_FORMAT_INT_EP_TO_SPORT_CTRL_BUS_BCM56770_A0fmt */ 17423 /* format EP_TO_SPORT_CTRL_BUSfmt */ 17424 /* nFields */ 5, 17425 /* *fields */ soc_EP_TO_SPORT_CTRL_BUS_BCM56960_A0fmt_fields, 17426 /* bits */ 7, 17427 /* flags */ 0, 17428 }, 17429 #endif /* chips */ 17430 17431 #if defined(BCM_56840_A0) 17432 { /* SOC_FORMAT_INT_EP_TO_SPORT_CTRL_BUS_BCM56840_A0fmt */ 17433 /* format EP_TO_SPORT_CTRL_BUSfmt */ 17434 /* nFields */ 5, 17435 /* *fields */ soc_EP_TO_SPORT_CTRL_BUSfmt_fields, 17436 /* bits */ 7, 17437 /* flags */ 0, 17438 }, 17439 #endif /* chips */ 17440 17441 #if defined(BCM_56840_B0) 17442 { /* SOC_FORMAT_INT_EP_TO_SPORT_CTRL_BUS_BCM56840_B0fmt */ 17443 /* format EP_TO_SPORT_CTRL_BUSfmt */ 17444 /* nFields */ 5, 17445 /* *fields */ soc_EP_TO_SPORT_CTRL_BUSfmt_fields, 17446 /* bits */ 7, 17447 /* flags */ 0, 17448 }, 17449 #endif /* chips */ 17450 17451 #if defined(BCM_56850_A0) 17452 { /* SOC_FORMAT_INT_EP_TO_SPORT_CTRL_BUS_BCM56850_A0fmt */ 17453 /* format EP_TO_SPORT_CTRL_BUSfmt */ 17454 /* nFields */ 5, 17455 /* *fields */ soc_EP_TO_SPORT_CTRL_BUS_BCM56640_A0fmt_fields, 17456 /* bits */ 7, 17457 /* flags */ 0, 17458 }, 17459 #endif /* chips */ 17460 17461 #if defined(BCM_56860_A0) 17462 { /* SOC_FORMAT_INT_EP_TO_SPORT_CTRL_BUS_BCM56860_A0fmt */ 17463 /* format EP_TO_SPORT_CTRL_BUSfmt */ 17464 /* nFields */ 5, 17465 /* *fields */ soc_EP_TO_SPORT_CTRL_BUS_BCM56640_A0fmt_fields, 17466 /* bits */ 7, 17467 /* flags */ 0, 17468 }, 17469 #endif /* chips */ 17470 17471 #if defined(BCM_56870_A0) 17472 { /* SOC_FORMAT_INT_EP_TO_SPORT_CTRL_BUS_BCM56870_A0fmt */ 17473 /* format EP_TO_SPORT_CTRL_BUSfmt */ 17474 /* nFields */ 5, 17475 /* *fields */ soc_EP_TO_SPORT_CTRL_BUS_BCM56960_A0fmt_fields, 17476 /* bits */ 7, 17477 /* flags */ 0, 17478 }, 17479 #endif /* chips */ 17480 17481 #if defined(BCM_56960_A0) 17482 { /* SOC_FORMAT_INT_EP_TO_SPORT_CTRL_BUS_BCM56960_A0fmt */ 17483 /* format EP_TO_SPORT_CTRL_BUSfmt */ 17484 /* nFields */ 5, 17485 /* *fields */ soc_EP_TO_SPORT_CTRL_BUS_BCM56960_A0fmt_fields, 17486 /* bits */ 7, 17487 /* flags */ 0, 17488 }, 17489 #endif /* chips */ 17490 17491 #if defined(BCM_56965_A0) 17492 { /* SOC_FORMAT_INT_EP_TO_SPORT_CTRL_BUS_BCM56965_A0fmt */ 17493 /* format EP_TO_SPORT_CTRL_BUSfmt */ 17494 /* nFields */ 5, 17495 /* *fields */ soc_EP_TO_SPORT_CTRL_BUS_BCM56960_A0fmt_fields, 17496 /* bits */ 7, 17497 /* flags */ 0, 17498 }, 17499 #endif /* chips */ 17500 17501 #if defined(BCM_56970_A0) 17502 { /* SOC_FORMAT_INT_EP_TO_SPORT_CTRL_BUS_BCM56970_A0fmt */ 17503 /* format EP_TO_SPORT_CTRL_BUSfmt */ 17504 /* nFields */ 5, 17505 /* *fields */ soc_EP_TO_SPORT_CTRL_BUS_BCM56960_A0fmt_fields, 17506 /* bits */ 7, 17507 /* flags */ 0, 17508 }, 17509 #endif /* chips */ 17510 17511 #if defined(BCM_56980_A0) 17512 { /* SOC_FORMAT_INT_EP_TO_SPORT_CTRL_BUS_BCM56980_A0fmt */ 17513 /* format EP_TO_SPORT_CTRL_BUSfmt */ 17514 /* nFields */ 5, 17515 /* *fields */ soc_EP_TO_SPORT_CTRL_BUS_BCM56960_A0fmt_fields, 17516 /* bits */ 7, 17517 /* flags */ 0, 17518 }, 17519 #endif /* chips */ 17520 17521 #if defined(BCM_56980_B0) 17522 { /* SOC_FORMAT_INT_EP_TO_SPORT_CTRL_BUS_BCM56980_B0fmt */ 17523 /* format EP_TO_SPORT_CTRL_BUSfmt */ 17524 /* nFields */ 5, 17525 /* *fields */ soc_EP_TO_SPORT_CTRL_BUS_BCM56960_A0fmt_fields, 17526 /* bits */ 7, 17527 /* flags */ 0, 17528 }, 17529 #endif /* chips */ 17530 17531 #if defined(BCM_56524_B0) || defined(BCM_56624_A0) || \ 17532 defined(BCM_56634_B0) 17533 { /* SOC_FORMAT_INT_EP_TO_XGPORT_CTRL_BUSfmt */ 17534 /* format EP_TO_XGPORT_CTRL_BUSfmt */ 17535 /* nFields */ 6, 17536 /* *fields */ soc_EP_TO_XGPORT_CTRL_BUSfmt_fields, 17537 /* bits */ 13, 17538 /* flags */ 0, 17539 }, 17540 #endif /* chips */ 17541 17542 #if defined(BCM_56340_A0) 17543 { /* SOC_FORMAT_INT_EP_TO_XGPORT_CTRL_BUS_BCM56340_A0fmt */ 17544 /* format EP_TO_XGPORT_CTRL_BUSfmt */ 17545 /* nFields */ 6, 17546 /* *fields */ soc_EP_TO_XGPORT_CTRL_BUS_BCM56640_A0fmt_fields, 17547 /* bits */ 13, 17548 /* flags */ 0, 17549 }, 17550 #endif /* chips */ 17551 17552 #if defined(BCM_56370_A0) 17553 { /* SOC_FORMAT_INT_EP_TO_XGPORT_CTRL_BUS_BCM56370_A0fmt */ 17554 /* format EP_TO_XGPORT_CTRL_BUSfmt */ 17555 /* nFields */ 6, 17556 /* *fields */ soc_EP_TO_XGPORT_CTRL_BUS_BCM56960_A0fmt_fields, 17557 /* bits */ 13, 17558 /* flags */ 0, 17559 }, 17560 #endif /* chips */ 17561 17562 #if defined(BCM_56524_A0) 17563 { /* SOC_FORMAT_INT_EP_TO_XGPORT_CTRL_BUS_BCM56524_A0fmt */ 17564 /* format EP_TO_XGPORT_CTRL_BUSfmt */ 17565 /* nFields */ 6, 17566 /* *fields */ soc_EP_TO_XGPORT_CTRL_BUSfmt_fields, 17567 /* bits */ 13, 17568 /* flags */ 0, 17569 }, 17570 #endif /* chips */ 17571 17572 #if defined(BCM_56560_A0) 17573 { /* SOC_FORMAT_INT_EP_TO_XGPORT_CTRL_BUS_BCM56560_A0fmt */ 17574 /* format EP_TO_XGPORT_CTRL_BUSfmt */ 17575 /* nFields */ 6, 17576 /* *fields */ soc_EP_TO_XGPORT_CTRL_BUS_BCM56960_A0fmt_fields, 17577 /* bits */ 13, 17578 /* flags */ 0, 17579 }, 17580 #endif /* chips */ 17581 17582 #if defined(BCM_56560_B0) 17583 { /* SOC_FORMAT_INT_EP_TO_XGPORT_CTRL_BUS_BCM56560_B0fmt */ 17584 /* format EP_TO_XGPORT_CTRL_BUSfmt */ 17585 /* nFields */ 6, 17586 /* *fields */ soc_EP_TO_XGPORT_CTRL_BUS_BCM56960_A0fmt_fields, 17587 /* bits */ 13, 17588 /* flags */ 0, 17589 }, 17590 #endif /* chips */ 17591 17592 #if defined(BCM_56624_B0) 17593 { /* SOC_FORMAT_INT_EP_TO_XGPORT_CTRL_BUS_BCM56624_B0fmt */ 17594 /* format EP_TO_XGPORT_CTRL_BUSfmt */ 17595 /* nFields */ 6, 17596 /* *fields */ soc_EP_TO_XGPORT_CTRL_BUSfmt_fields, 17597 /* bits */ 13, 17598 /* flags */ 0, 17599 }, 17600 #endif /* chips */ 17601 17602 #if defined(BCM_56634_A0) 17603 { /* SOC_FORMAT_INT_EP_TO_XGPORT_CTRL_BUS_BCM56634_A0fmt */ 17604 /* format EP_TO_XGPORT_CTRL_BUSfmt */ 17605 /* nFields */ 6, 17606 /* *fields */ soc_EP_TO_XGPORT_CTRL_BUSfmt_fields, 17607 /* bits */ 13, 17608 /* flags */ 0, 17609 }, 17610 #endif /* chips */ 17611 17612 #if defined(BCM_56640_A0) 17613 { /* SOC_FORMAT_INT_EP_TO_XGPORT_CTRL_BUS_BCM56640_A0fmt */ 17614 /* format EP_TO_XGPORT_CTRL_BUSfmt */ 17615 /* nFields */ 6, 17616 /* *fields */ soc_EP_TO_XGPORT_CTRL_BUS_BCM56640_A0fmt_fields, 17617 /* bits */ 13, 17618 /* flags */ 0, 17619 }, 17620 #endif /* chips */ 17621 17622 #if defined(BCM_56670_A0) 17623 { /* SOC_FORMAT_INT_EP_TO_XGPORT_CTRL_BUS_BCM56670_A0fmt */ 17624 /* format EP_TO_XGPORT_CTRL_BUSfmt */ 17625 /* nFields */ 6, 17626 /* *fields */ soc_EP_TO_XGPORT_CTRL_BUS_BCM56960_A0fmt_fields, 17627 /* bits */ 13, 17628 /* flags */ 0, 17629 }, 17630 #endif /* chips */ 17631 17632 #if defined(BCM_56670_B0) 17633 { /* SOC_FORMAT_INT_EP_TO_XGPORT_CTRL_BUS_BCM56670_B0fmt */ 17634 /* format EP_TO_XGPORT_CTRL_BUSfmt */ 17635 /* nFields */ 6, 17636 /* *fields */ soc_EP_TO_XGPORT_CTRL_BUS_BCM56960_A0fmt_fields, 17637 /* bits */ 13, 17638 /* flags */ 0, 17639 }, 17640 #endif /* chips */ 17641 17642 #if defined(BCM_56680_A0) 17643 { /* SOC_FORMAT_INT_EP_TO_XGPORT_CTRL_BUS_BCM56680_A0fmt */ 17644 /* format EP_TO_XGPORT_CTRL_BUSfmt */ 17645 /* nFields */ 6, 17646 /* *fields */ soc_EP_TO_XGPORT_CTRL_BUSfmt_fields, 17647 /* bits */ 13, 17648 /* flags */ 0, 17649 }, 17650 #endif /* chips */ 17651 17652 #if defined(BCM_56680_B0) 17653 { /* SOC_FORMAT_INT_EP_TO_XGPORT_CTRL_BUS_BCM56680_B0fmt */ 17654 /* format EP_TO_XGPORT_CTRL_BUSfmt */ 17655 /* nFields */ 6, 17656 /* *fields */ soc_EP_TO_XGPORT_CTRL_BUSfmt_fields, 17657 /* bits */ 13, 17658 /* flags */ 0, 17659 }, 17660 #endif /* chips */ 17661 17662 #if defined(BCM_56685_A0) 17663 { /* SOC_FORMAT_INT_EP_TO_XGPORT_CTRL_BUS_BCM56685_A0fmt */ 17664 /* format EP_TO_XGPORT_CTRL_BUSfmt */ 17665 /* nFields */ 6, 17666 /* *fields */ soc_EP_TO_XGPORT_CTRL_BUSfmt_fields, 17667 /* bits */ 13, 17668 /* flags */ 0, 17669 }, 17670 #endif /* chips */ 17671 17672 #if defined(BCM_56685_B0) 17673 { /* SOC_FORMAT_INT_EP_TO_XGPORT_CTRL_BUS_BCM56685_B0fmt */ 17674 /* format EP_TO_XGPORT_CTRL_BUSfmt */ 17675 /* nFields */ 6, 17676 /* *fields */ soc_EP_TO_XGPORT_CTRL_BUSfmt_fields, 17677 /* bits */ 13, 17678 /* flags */ 0, 17679 }, 17680 #endif /* chips */ 17681 17682 #if defined(BCM_56770_A0) 17683 { /* SOC_FORMAT_INT_EP_TO_XGPORT_CTRL_BUS_BCM56770_A0fmt */ 17684 /* format EP_TO_XGPORT_CTRL_BUSfmt */ 17685 /* nFields */ 6, 17686 /* *fields */ soc_EP_TO_XGPORT_CTRL_BUS_BCM56960_A0fmt_fields, 17687 /* bits */ 13, 17688 /* flags */ 0, 17689 }, 17690 #endif /* chips */ 17691 17692 #if defined(BCM_56840_A0) 17693 { /* SOC_FORMAT_INT_EP_TO_XGPORT_CTRL_BUS_BCM56840_A0fmt */ 17694 /* format EP_TO_XGPORT_CTRL_BUSfmt */ 17695 /* nFields */ 6, 17696 /* *fields */ soc_EP_TO_XGPORT_CTRL_BUSfmt_fields, 17697 /* bits */ 13, 17698 /* flags */ 0, 17699 }, 17700 #endif /* chips */ 17701 17702 #if defined(BCM_56840_B0) 17703 { /* SOC_FORMAT_INT_EP_TO_XGPORT_CTRL_BUS_BCM56840_B0fmt */ 17704 /* format EP_TO_XGPORT_CTRL_BUSfmt */ 17705 /* nFields */ 6, 17706 /* *fields */ soc_EP_TO_XGPORT_CTRL_BUSfmt_fields, 17707 /* bits */ 13, 17708 /* flags */ 0, 17709 }, 17710 #endif /* chips */ 17711 17712 #if defined(BCM_56850_A0) 17713 { /* SOC_FORMAT_INT_EP_TO_XGPORT_CTRL_BUS_BCM56850_A0fmt */ 17714 /* format EP_TO_XGPORT_CTRL_BUSfmt */ 17715 /* nFields */ 6, 17716 /* *fields */ soc_EP_TO_XGPORT_CTRL_BUS_BCM56640_A0fmt_fields, 17717 /* bits */ 13, 17718 /* flags */ 0, 17719 }, 17720 #endif /* chips */ 17721 17722 #if defined(BCM_56860_A0) 17723 { /* SOC_FORMAT_INT_EP_TO_XGPORT_CTRL_BUS_BCM56860_A0fmt */ 17724 /* format EP_TO_XGPORT_CTRL_BUSfmt */ 17725 /* nFields */ 6, 17726 /* *fields */ soc_EP_TO_XGPORT_CTRL_BUS_BCM56640_A0fmt_fields, 17727 /* bits */ 13, 17728 /* flags */ 0, 17729 }, 17730 #endif /* chips */ 17731 17732 #if defined(BCM_56870_A0) 17733 { /* SOC_FORMAT_INT_EP_TO_XGPORT_CTRL_BUS_BCM56870_A0fmt */ 17734 /* format EP_TO_XGPORT_CTRL_BUSfmt */ 17735 /* nFields */ 6, 17736 /* *fields */ soc_EP_TO_XGPORT_CTRL_BUS_BCM56960_A0fmt_fields, 17737 /* bits */ 13, 17738 /* flags */ 0, 17739 }, 17740 #endif /* chips */ 17741 17742 #if defined(BCM_56960_A0) 17743 { /* SOC_FORMAT_INT_EP_TO_XGPORT_CTRL_BUS_BCM56960_A0fmt */ 17744 /* format EP_TO_XGPORT_CTRL_BUSfmt */ 17745 /* nFields */ 6, 17746 /* *fields */ soc_EP_TO_XGPORT_CTRL_BUS_BCM56960_A0fmt_fields, 17747 /* bits */ 13, 17748 /* flags */ 0, 17749 }, 17750 #endif /* chips */ 17751 17752 #if defined(BCM_56965_A0) 17753 { /* SOC_FORMAT_INT_EP_TO_XGPORT_CTRL_BUS_BCM56965_A0fmt */ 17754 /* format EP_TO_XGPORT_CTRL_BUSfmt */ 17755 /* nFields */ 6, 17756 /* *fields */ soc_EP_TO_XGPORT_CTRL_BUS_BCM56960_A0fmt_fields, 17757 /* bits */ 13, 17758 /* flags */ 0, 17759 }, 17760 #endif /* chips */ 17761 17762 #if defined(BCM_56970_A0) 17763 { /* SOC_FORMAT_INT_EP_TO_XGPORT_CTRL_BUS_BCM56970_A0fmt */ 17764 /* format EP_TO_XGPORT_CTRL_BUSfmt */ 17765 /* nFields */ 6, 17766 /* *fields */ soc_EP_TO_XGPORT_CTRL_BUS_BCM56960_A0fmt_fields, 17767 /* bits */ 13, 17768 /* flags */ 0, 17769 }, 17770 #endif /* chips */ 17771 17772 #if defined(BCM_56980_A0) 17773 { /* SOC_FORMAT_INT_EP_TO_XGPORT_CTRL_BUS_BCM56980_A0fmt */ 17774 /* format EP_TO_XGPORT_CTRL_BUSfmt */ 17775 /* nFields */ 6, 17776 /* *fields */ soc_EP_TO_XGPORT_CTRL_BUS_BCM56960_A0fmt_fields, 17777 /* bits */ 13, 17778 /* flags */ 0, 17779 }, 17780 #endif /* chips */ 17781 17782 #if defined(BCM_56980_B0) 17783 { /* SOC_FORMAT_INT_EP_TO_XGPORT_CTRL_BUS_BCM56980_B0fmt */ 17784 /* format EP_TO_XGPORT_CTRL_BUSfmt */ 17785 /* nFields */ 6, 17786 /* *fields */ soc_EP_TO_XGPORT_CTRL_BUS_BCM56960_A0fmt_fields, 17787 /* bits */ 13, 17788 /* flags */ 0, 17789 }, 17790 #endif /* chips */ 17791 17792 #if defined(BCM_56725_A0) || defined(BCM_56800_A0) || \ 17793 defined(BCM_56820_A0) 17794 { /* SOC_FORMAT_INT_EP_TO_XPORT_CTRL_BUSfmt */ 17795 /* format EP_TO_XPORT_CTRL_BUSfmt */ 17796 /* nFields */ 5, 17797 /* *fields */ soc_EP_TO_XPORT_CTRL_BUSfmt_fields, 17798 /* bits */ 9, 17799 /* flags */ 0, 17800 }, 17801 #endif /* chips */ 17802 17803 #if defined(BCM_56340_A0) 17804 { /* SOC_FORMAT_INT_EP_TO_XPORT_CTRL_BUS_BCM56340_A0fmt */ 17805 /* format EP_TO_XPORT_CTRL_BUSfmt */ 17806 /* nFields */ 5, 17807 /* *fields */ soc_EP_TO_XPORT_CTRL_BUS_BCM56640_A0fmt_fields, 17808 /* bits */ 9, 17809 /* flags */ 0, 17810 }, 17811 #endif /* chips */ 17812 17813 #if defined(BCM_56370_A0) 17814 { /* SOC_FORMAT_INT_EP_TO_XPORT_CTRL_BUS_BCM56370_A0fmt */ 17815 /* format EP_TO_XPORT_CTRL_BUSfmt */ 17816 /* nFields */ 5, 17817 /* *fields */ soc_EP_TO_XPORT_CTRL_BUS_BCM56960_A0fmt_fields, 17818 /* bits */ 9, 17819 /* flags */ 0, 17820 }, 17821 #endif /* chips */ 17822 17823 #if defined(BCM_56524_A0) 17824 { /* SOC_FORMAT_INT_EP_TO_XPORT_CTRL_BUS_BCM56524_A0fmt */ 17825 /* format EP_TO_XPORT_CTRL_BUSfmt */ 17826 /* nFields */ 5, 17827 /* *fields */ soc_EP_TO_XPORT_CTRL_BUS_BCM56624_A0fmt_fields, 17828 /* bits */ 9, 17829 /* flags */ 0, 17830 }, 17831 #endif /* chips */ 17832 17833 #if defined(BCM_56524_B0) 17834 { /* SOC_FORMAT_INT_EP_TO_XPORT_CTRL_BUS_BCM56524_B0fmt */ 17835 /* format EP_TO_XPORT_CTRL_BUSfmt */ 17836 /* nFields */ 5, 17837 /* *fields */ soc_EP_TO_XPORT_CTRL_BUS_BCM56624_A0fmt_fields, 17838 /* bits */ 9, 17839 /* flags */ 0, 17840 }, 17841 #endif /* chips */ 17842 17843 #if defined(BCM_56560_A0) 17844 { /* SOC_FORMAT_INT_EP_TO_XPORT_CTRL_BUS_BCM56560_A0fmt */ 17845 /* format EP_TO_XPORT_CTRL_BUSfmt */ 17846 /* nFields */ 5, 17847 /* *fields */ soc_EP_TO_XPORT_CTRL_BUS_BCM56960_A0fmt_fields, 17848 /* bits */ 9, 17849 /* flags */ 0, 17850 }, 17851 #endif /* chips */ 17852 17853 #if defined(BCM_56560_B0) 17854 { /* SOC_FORMAT_INT_EP_TO_XPORT_CTRL_BUS_BCM56560_B0fmt */ 17855 /* format EP_TO_XPORT_CTRL_BUSfmt */ 17856 /* nFields */ 5, 17857 /* *fields */ soc_EP_TO_XPORT_CTRL_BUS_BCM56960_A0fmt_fields, 17858 /* bits */ 9, 17859 /* flags */ 0, 17860 }, 17861 #endif /* chips */ 17862 17863 #if defined(BCM_56624_A0) 17864 { /* SOC_FORMAT_INT_EP_TO_XPORT_CTRL_BUS_BCM56624_A0fmt */ 17865 /* format EP_TO_XPORT_CTRL_BUSfmt */ 17866 /* nFields */ 5, 17867 /* *fields */ soc_EP_TO_XPORT_CTRL_BUS_BCM56624_A0fmt_fields, 17868 /* bits */ 9, 17869 /* flags */ 0, 17870 }, 17871 #endif /* chips */ 17872 17873 #if defined(BCM_56624_B0) 17874 { /* SOC_FORMAT_INT_EP_TO_XPORT_CTRL_BUS_BCM56624_B0fmt */ 17875 /* format EP_TO_XPORT_CTRL_BUSfmt */ 17876 /* nFields */ 5, 17877 /* *fields */ soc_EP_TO_XPORT_CTRL_BUS_BCM56624_A0fmt_fields, 17878 /* bits */ 9, 17879 /* flags */ 0, 17880 }, 17881 #endif /* chips */ 17882 17883 #if defined(BCM_56634_A0) 17884 { /* SOC_FORMAT_INT_EP_TO_XPORT_CTRL_BUS_BCM56634_A0fmt */ 17885 /* format EP_TO_XPORT_CTRL_BUSfmt */ 17886 /* nFields */ 5, 17887 /* *fields */ soc_EP_TO_XPORT_CTRL_BUS_BCM56624_A0fmt_fields, 17888 /* bits */ 9, 17889 /* flags */ 0, 17890 }, 17891 #endif /* chips */ 17892 17893 #if defined(BCM_56634_B0) 17894 { /* SOC_FORMAT_INT_EP_TO_XPORT_CTRL_BUS_BCM56634_B0fmt */ 17895 /* format EP_TO_XPORT_CTRL_BUSfmt */ 17896 /* nFields */ 5, 17897 /* *fields */ soc_EP_TO_XPORT_CTRL_BUS_BCM56624_A0fmt_fields, 17898 /* bits */ 9, 17899 /* flags */ 0, 17900 }, 17901 #endif /* chips */ 17902 17903 #if defined(BCM_56640_A0) 17904 { /* SOC_FORMAT_INT_EP_TO_XPORT_CTRL_BUS_BCM56640_A0fmt */ 17905 /* format EP_TO_XPORT_CTRL_BUSfmt */ 17906 /* nFields */ 5, 17907 /* *fields */ soc_EP_TO_XPORT_CTRL_BUS_BCM56640_A0fmt_fields, 17908 /* bits */ 9, 17909 /* flags */ 0, 17910 }, 17911 #endif /* chips */ 17912 17913 #if defined(BCM_56670_A0) 17914 { /* SOC_FORMAT_INT_EP_TO_XPORT_CTRL_BUS_BCM56670_A0fmt */ 17915 /* format EP_TO_XPORT_CTRL_BUSfmt */ 17916 /* nFields */ 5, 17917 /* *fields */ soc_EP_TO_XPORT_CTRL_BUS_BCM56960_A0fmt_fields, 17918 /* bits */ 9, 17919 /* flags */ 0, 17920 }, 17921 #endif /* chips */ 17922 17923 #if defined(BCM_56670_B0) 17924 { /* SOC_FORMAT_INT_EP_TO_XPORT_CTRL_BUS_BCM56670_B0fmt */ 17925 /* format EP_TO_XPORT_CTRL_BUSfmt */ 17926 /* nFields */ 5, 17927 /* *fields */ soc_EP_TO_XPORT_CTRL_BUS_BCM56960_A0fmt_fields, 17928 /* bits */ 9, 17929 /* flags */ 0, 17930 }, 17931 #endif /* chips */ 17932 17933 #if defined(BCM_56680_A0) 17934 { /* SOC_FORMAT_INT_EP_TO_XPORT_CTRL_BUS_BCM56680_A0fmt */ 17935 /* format EP_TO_XPORT_CTRL_BUSfmt */ 17936 /* nFields */ 5, 17937 /* *fields */ soc_EP_TO_XPORT_CTRL_BUS_BCM56624_A0fmt_fields, 17938 /* bits */ 9, 17939 /* flags */ 0, 17940 }, 17941 #endif /* chips */ 17942 17943 #if defined(BCM_56680_B0) 17944 { /* SOC_FORMAT_INT_EP_TO_XPORT_CTRL_BUS_BCM56680_B0fmt */ 17945 /* format EP_TO_XPORT_CTRL_BUSfmt */ 17946 /* nFields */ 5, 17947 /* *fields */ soc_EP_TO_XPORT_CTRL_BUS_BCM56624_A0fmt_fields, 17948 /* bits */ 9, 17949 /* flags */ 0, 17950 }, 17951 #endif /* chips */ 17952 17953 #if defined(BCM_56685_A0) 17954 { /* SOC_FORMAT_INT_EP_TO_XPORT_CTRL_BUS_BCM56685_A0fmt */ 17955 /* format EP_TO_XPORT_CTRL_BUSfmt */ 17956 /* nFields */ 5, 17957 /* *fields */ soc_EP_TO_XPORT_CTRL_BUS_BCM56624_A0fmt_fields, 17958 /* bits */ 9, 17959 /* flags */ 0, 17960 }, 17961 #endif /* chips */ 17962 17963 #if defined(BCM_56685_B0) 17964 { /* SOC_FORMAT_INT_EP_TO_XPORT_CTRL_BUS_BCM56685_B0fmt */ 17965 /* format EP_TO_XPORT_CTRL_BUSfmt */ 17966 /* nFields */ 5, 17967 /* *fields */ soc_EP_TO_XPORT_CTRL_BUS_BCM56624_A0fmt_fields, 17968 /* bits */ 9, 17969 /* flags */ 0, 17970 }, 17971 #endif /* chips */ 17972 17973 #if defined(BCM_56770_A0) 17974 { /* SOC_FORMAT_INT_EP_TO_XPORT_CTRL_BUS_BCM56770_A0fmt */ 17975 /* format EP_TO_XPORT_CTRL_BUSfmt */ 17976 /* nFields */ 5, 17977 /* *fields */ soc_EP_TO_XPORT_CTRL_BUS_BCM56960_A0fmt_fields, 17978 /* bits */ 9, 17979 /* flags */ 0, 17980 }, 17981 #endif /* chips */ 17982 17983 #if defined(BCM_56840_A0) 17984 { /* SOC_FORMAT_INT_EP_TO_XPORT_CTRL_BUS_BCM56840_A0fmt */ 17985 /* format EP_TO_XPORT_CTRL_BUSfmt */ 17986 /* nFields */ 5, 17987 /* *fields */ soc_EP_TO_XPORT_CTRL_BUS_BCM56624_A0fmt_fields, 17988 /* bits */ 9, 17989 /* flags */ 0, 17990 }, 17991 #endif /* chips */ 17992 17993 #if defined(BCM_56840_B0) 17994 { /* SOC_FORMAT_INT_EP_TO_XPORT_CTRL_BUS_BCM56840_B0fmt */ 17995 /* format EP_TO_XPORT_CTRL_BUSfmt */ 17996 /* nFields */ 5, 17997 /* *fields */ soc_EP_TO_XPORT_CTRL_BUS_BCM56624_A0fmt_fields, 17998 /* bits */ 9, 17999 /* flags */ 0, 18000 }, 18001 #endif /* chips */ 18002 18003 #if defined(BCM_56850_A0) 18004 { /* SOC_FORMAT_INT_EP_TO_XPORT_CTRL_BUS_BCM56850_A0fmt */ 18005 /* format EP_TO_XPORT_CTRL_BUSfmt */ 18006 /* nFields */ 5, 18007 /* *fields */ soc_EP_TO_XPORT_CTRL_BUS_BCM56640_A0fmt_fields, 18008 /* bits */ 9, 18009 /* flags */ 0, 18010 }, 18011 #endif /* chips */ 18012 18013 #if defined(BCM_56860_A0) 18014 { /* SOC_FORMAT_INT_EP_TO_XPORT_CTRL_BUS_BCM56860_A0fmt */ 18015 /* format EP_TO_XPORT_CTRL_BUSfmt */ 18016 /* nFields */ 5, 18017 /* *fields */ soc_EP_TO_XPORT_CTRL_BUS_BCM56640_A0fmt_fields, 18018 /* bits */ 9, 18019 /* flags */ 0, 18020 }, 18021 #endif /* chips */ 18022 18023 #if defined(BCM_56870_A0) 18024 { /* SOC_FORMAT_INT_EP_TO_XPORT_CTRL_BUS_BCM56870_A0fmt */ 18025 /* format EP_TO_XPORT_CTRL_BUSfmt */ 18026 /* nFields */ 5, 18027 /* *fields */ soc_EP_TO_XPORT_CTRL_BUS_BCM56960_A0fmt_fields, 18028 /* bits */ 9, 18029 /* flags */ 0, 18030 }, 18031 #endif /* chips */ 18032 18033 #if defined(BCM_56960_A0) 18034 { /* SOC_FORMAT_INT_EP_TO_XPORT_CTRL_BUS_BCM56960_A0fmt */ 18035 /* format EP_TO_XPORT_CTRL_BUSfmt */ 18036 /* nFields */ 5, 18037 /* *fields */ soc_EP_TO_XPORT_CTRL_BUS_BCM56960_A0fmt_fields, 18038 /* bits */ 9, 18039 /* flags */ 0, 18040 }, 18041 #endif /* chips */ 18042 18043 #if defined(BCM_56965_A0) 18044 { /* SOC_FORMAT_INT_EP_TO_XPORT_CTRL_BUS_BCM56965_A0fmt */ 18045 /* format EP_TO_XPORT_CTRL_BUSfmt */ 18046 /* nFields */ 5, 18047 /* *fields */ soc_EP_TO_XPORT_CTRL_BUS_BCM56960_A0fmt_fields, 18048 /* bits */ 9, 18049 /* flags */ 0, 18050 }, 18051 #endif /* chips */ 18052 18053 #if defined(BCM_56970_A0) 18054 { /* SOC_FORMAT_INT_EP_TO_XPORT_CTRL_BUS_BCM56970_A0fmt */ 18055 /* format EP_TO_XPORT_CTRL_BUSfmt */ 18056 /* nFields */ 5, 18057 /* *fields */ soc_EP_TO_XPORT_CTRL_BUS_BCM56960_A0fmt_fields, 18058 /* bits */ 9, 18059 /* flags */ 0, 18060 }, 18061 #endif /* chips */ 18062 18063 #if defined(BCM_56980_A0) 18064 { /* SOC_FORMAT_INT_EP_TO_XPORT_CTRL_BUS_BCM56980_A0fmt */ 18065 /* format EP_TO_XPORT_CTRL_BUSfmt */ 18066 /* nFields */ 5, 18067 /* *fields */ soc_EP_TO_XPORT_CTRL_BUS_BCM56960_A0fmt_fields, 18068 /* bits */ 9, 18069 /* flags */ 0, 18070 }, 18071 #endif /* chips */ 18072 18073 #if defined(BCM_56980_B0) 18074 { /* SOC_FORMAT_INT_EP_TO_XPORT_CTRL_BUS_BCM56980_B0fmt */ 18075 /* format EP_TO_XPORT_CTRL_BUSfmt */ 18076 /* nFields */ 5, 18077 /* *fields */ soc_EP_TO_XPORT_CTRL_BUS_BCM56960_A0fmt_fields, 18078 /* bits */ 9, 18079 /* flags */ 0, 18080 }, 18081 #endif /* chips */ 18082 18083 #if defined(BCM_56334_A0) 18084 { /* SOC_FORMAT_INT_EP_TO_XQPORT_CTRL_BUSfmt */ 18085 /* format EP_TO_XQPORT_CTRL_BUSfmt */ 18086 /* nFields */ 7, 18087 /* *fields */ soc_EP_TO_XQPORT_CTRL_BUSfmt_fields, 18088 /* bits */ 11, 18089 /* flags */ 0, 18090 }, 18091 #endif /* chips */ 18092 18093 #if defined(BCM_53400_A0) 18094 { /* SOC_FORMAT_INT_EP_TO_XQPORT_CTRL_BUS_BCM53400_A0fmt */ 18095 /* format EP_TO_XQPORT_CTRL_BUSfmt */ 18096 /* nFields */ 7, 18097 /* *fields */ soc_EP_TO_XQPORT_CTRL_BUS_BCM53400_A0fmt_fields, 18098 /* bits */ 11, 18099 /* flags */ 0, 18100 }, 18101 #endif /* chips */ 18102 18103 #if defined(BCM_53540_A0) 18104 { /* SOC_FORMAT_INT_EP_TO_XQPORT_CTRL_BUS_BCM53540_A0fmt */ 18105 /* format EP_TO_XQPORT_CTRL_BUSfmt */ 18106 /* nFields */ 7, 18107 /* *fields */ soc_EP_TO_XQPORT_CTRL_BUS_BCM53400_A0fmt_fields, 18108 /* bits */ 11, 18109 /* flags */ 0, 18110 }, 18111 #endif /* chips */ 18112 18113 #if defined(BCM_53570_A0) 18114 { /* SOC_FORMAT_INT_EP_TO_XQPORT_CTRL_BUS_BCM53570_A0fmt */ 18115 /* format EP_TO_XQPORT_CTRL_BUSfmt */ 18116 /* nFields */ 7, 18117 /* *fields */ soc_EP_TO_XQPORT_CTRL_BUS_BCM53400_A0fmt_fields, 18118 /* bits */ 11, 18119 /* flags */ 0, 18120 }, 18121 #endif /* chips */ 18122 18123 #if defined(BCM_53570_B0) 18124 { /* SOC_FORMAT_INT_EP_TO_XQPORT_CTRL_BUS_BCM53570_B0fmt */ 18125 /* format EP_TO_XQPORT_CTRL_BUSfmt */ 18126 /* nFields */ 7, 18127 /* *fields */ soc_EP_TO_XQPORT_CTRL_BUS_BCM53400_A0fmt_fields, 18128 /* bits */ 11, 18129 /* flags */ 0, 18130 }, 18131 #endif /* chips */ 18132 18133 #if defined(BCM_56142_A0) 18134 { /* SOC_FORMAT_INT_EP_TO_XQPORT_CTRL_BUS_BCM56142_A0fmt */ 18135 /* format EP_TO_XQPORT_CTRL_BUSfmt */ 18136 /* nFields */ 7, 18137 /* *fields */ soc_EP_TO_XQPORT_CTRL_BUSfmt_fields, 18138 /* bits */ 11, 18139 /* flags */ 0, 18140 }, 18141 #endif /* chips */ 18142 18143 #if defined(BCM_56150_A0) 18144 { /* SOC_FORMAT_INT_EP_TO_XQPORT_CTRL_BUS_BCM56150_A0fmt */ 18145 /* format EP_TO_XQPORT_CTRL_BUSfmt */ 18146 /* nFields */ 7, 18147 /* *fields */ soc_EP_TO_XQPORT_CTRL_BUS_BCM56150_A0fmt_fields, 18148 /* bits */ 11, 18149 /* flags */ 0, 18150 }, 18151 #endif /* chips */ 18152 18153 #if defined(BCM_56160_A0) 18154 { /* SOC_FORMAT_INT_EP_TO_XQPORT_CTRL_BUS_BCM56160_A0fmt */ 18155 /* format EP_TO_XQPORT_CTRL_BUSfmt */ 18156 /* nFields */ 7, 18157 /* *fields */ soc_EP_TO_XQPORT_CTRL_BUS_BCM53400_A0fmt_fields, 18158 /* bits */ 11, 18159 /* flags */ 0, 18160 }, 18161 #endif /* chips */ 18162 18163 #if defined(BCM_56260_A0) 18164 { /* SOC_FORMAT_INT_EP_TO_XQPORT_CTRL_BUS_BCM56260_A0fmt */ 18165 /* format EP_TO_XQPORT_CTRL_BUSfmt */ 18166 /* nFields */ 11, 18167 /* *fields */ soc_EP_TO_XQPORT_CTRL_BUS_BCM56260_A0fmt_fields, 18168 /* bits */ 24, 18169 /* flags */ 0, 18170 }, 18171 #endif /* chips */ 18172 18173 #if defined(BCM_56260_B0) 18174 { /* SOC_FORMAT_INT_EP_TO_XQPORT_CTRL_BUS_BCM56260_B0fmt */ 18175 /* format EP_TO_XQPORT_CTRL_BUSfmt */ 18176 /* nFields */ 11, 18177 /* *fields */ soc_EP_TO_XQPORT_CTRL_BUS_BCM56260_A0fmt_fields, 18178 /* bits */ 24, 18179 /* flags */ 0, 18180 }, 18181 #endif /* chips */ 18182 18183 #if defined(BCM_56270_A0) 18184 { /* SOC_FORMAT_INT_EP_TO_XQPORT_CTRL_BUS_BCM56270_A0fmt */ 18185 /* format EP_TO_XQPORT_CTRL_BUSfmt */ 18186 /* nFields */ 11, 18187 /* *fields */ soc_EP_TO_XQPORT_CTRL_BUS_BCM56260_A0fmt_fields, 18188 /* bits */ 24, 18189 /* flags */ 0, 18190 }, 18191 #endif /* chips */ 18192 18193 #if defined(BCM_56334_B0) 18194 { /* SOC_FORMAT_INT_EP_TO_XQPORT_CTRL_BUS_BCM56334_B0fmt */ 18195 /* format EP_TO_XQPORT_CTRL_BUSfmt */ 18196 /* nFields */ 7, 18197 /* *fields */ soc_EP_TO_XQPORT_CTRL_BUSfmt_fields, 18198 /* bits */ 11, 18199 /* flags */ 0, 18200 }, 18201 #endif /* chips */ 18202 18203 #if defined(BCM_56440_A0) 18204 { /* SOC_FORMAT_INT_EP_TO_XQPORT_CTRL_BUS_BCM56440_A0fmt */ 18205 /* format EP_TO_XQPORT_CTRL_BUSfmt */ 18206 /* nFields */ 11, 18207 /* *fields */ soc_EP_TO_XQPORT_CTRL_BUS_BCM56440_A0fmt_fields, 18208 /* bits */ 24, 18209 /* flags */ 0, 18210 }, 18211 #endif /* chips */ 18212 18213 #if defined(BCM_56440_B0) 18214 { /* SOC_FORMAT_INT_EP_TO_XQPORT_CTRL_BUS_BCM56440_B0fmt */ 18215 /* format EP_TO_XQPORT_CTRL_BUSfmt */ 18216 /* nFields */ 11, 18217 /* *fields */ soc_EP_TO_XQPORT_CTRL_BUS_BCM56440_A0fmt_fields, 18218 /* bits */ 24, 18219 /* flags */ 0, 18220 }, 18221 #endif /* chips */ 18222 18223 #if defined(BCM_56450_A0) 18224 { /* SOC_FORMAT_INT_EP_TO_XQPORT_CTRL_BUS_BCM56450_A0fmt */ 18225 /* format EP_TO_XQPORT_CTRL_BUSfmt */ 18226 /* nFields */ 11, 18227 /* *fields */ soc_EP_TO_XQPORT_CTRL_BUS_BCM56450_A0fmt_fields, 18228 /* bits */ 24, 18229 /* flags */ 0, 18230 }, 18231 #endif /* chips */ 18232 18233 #if defined(BCM_56450_B0) 18234 { /* SOC_FORMAT_INT_EP_TO_XQPORT_CTRL_BUS_BCM56450_B0fmt */ 18235 /* format EP_TO_XQPORT_CTRL_BUSfmt */ 18236 /* nFields */ 11, 18237 /* *fields */ soc_EP_TO_XQPORT_CTRL_BUS_BCM56450_A0fmt_fields, 18238 /* bits */ 24, 18239 /* flags */ 0, 18240 }, 18241 #endif /* chips */ 18242 18243 #if defined(BCM_56450_B1) 18244 { /* SOC_FORMAT_INT_EP_TO_XQPORT_CTRL_BUS_BCM56450_B1fmt */ 18245 /* format EP_TO_XQPORT_CTRL_BUSfmt */ 18246 /* nFields */ 11, 18247 /* *fields */ soc_EP_TO_XQPORT_CTRL_BUS_BCM56450_A0fmt_fields, 18248 /* bits */ 24, 18249 /* flags */ 0, 18250 }, 18251 #endif /* chips */ 18252 18253 #if defined(BCM_56640_A0) 18254 { /* SOC_FORMAT_INT_EP_VLAN_XLATE_1_DATAfmt */ 18255 /* format EP_VLAN_XLATE_1_DATAfmt */ 18256 /* nFields */ 47, 18257 /* *fields */ soc_EP_VLAN_XLATE_1_DATAfmt_fields, 18258 /* bits */ 69, 18259 /* flags */ 0, 18260 }, 18261 #endif /* chips */ 18262 18263 #if defined(BCM_56340_A0) 18264 { /* SOC_FORMAT_INT_EP_VLAN_XLATE_1_DATA_BCM56340_A0fmt */ 18265 /* format EP_VLAN_XLATE_1_DATAfmt */ 18266 /* nFields */ 51, 18267 /* *fields */ soc_EP_VLAN_XLATE_1_DATA_BCM56340_A0fmt_fields, 18268 /* bits */ 69, 18269 /* flags */ 0, 18270 }, 18271 #endif /* chips */ 18272 18273 #if defined(BCM_56640_A0) 18274 { /* SOC_FORMAT_INT_EP_VLAN_XLATE_KEYfmt */ 18275 /* format EP_VLAN_XLATE_KEYfmt */ 18276 /* nFields */ 20, 18277 /* *fields */ soc_EP_VLAN_XLATE_KEYfmt_fields, 18278 /* bits */ 43, 18279 /* flags */ 0, 18280 }, 18281 #endif /* chips */ 18282 18283 #if defined(BCM_56340_A0) 18284 { /* SOC_FORMAT_INT_EP_VLAN_XLATE_KEY_BCM56340_A0fmt */ 18285 /* format EP_VLAN_XLATE_KEYfmt */ 18286 /* nFields */ 23, 18287 /* *fields */ soc_EP_VLAN_XLATE_KEY_BCM56340_A0fmt_fields, 18288 /* bits */ 43, 18289 /* flags */ 0, 18290 }, 18291 #endif /* chips */ 18292 18293 #if defined(BCM_56334_A0) || defined(BCM_56524_A0) || \ 18294 defined(BCM_56524_B0) || defined(BCM_56624_A0) || \ 18295 defined(BCM_56624_B0) || defined(BCM_56634_A0) || \ 18296 defined(BCM_56634_B0) || defined(BCM_56680_A0) || \ 18297 defined(BCM_56685_B0) 18298 { /* SOC_FORMAT_INT_ESMIF_COUNTERfmt */ 18299 /* format ESMIF_COUNTERfmt */ 18300 /* nFields */ 9, 18301 /* *fields */ soc_ESMIF_COUNTERfmt_fields, 18302 /* bits */ 9, 18303 /* flags */ 0, 18304 }, 18305 #endif /* chips */ 18306 18307 #if defined(BCM_53400_A0) 18308 { /* SOC_FORMAT_INT_ESMIF_COUNTER_BCM53400_A0fmt */ 18309 /* format ESMIF_COUNTERfmt */ 18310 /* nFields */ 9, 18311 /* *fields */ soc_ESMIF_COUNTER_BCM53400_A0fmt_fields, 18312 /* bits */ 9, 18313 /* flags */ 0, 18314 }, 18315 #endif /* chips */ 18316 18317 #if defined(BCM_53540_A0) 18318 { /* SOC_FORMAT_INT_ESMIF_COUNTER_BCM53540_A0fmt */ 18319 /* format ESMIF_COUNTERfmt */ 18320 /* nFields */ 9, 18321 /* *fields */ soc_ESMIF_COUNTER_BCM53400_A0fmt_fields, 18322 /* bits */ 9, 18323 /* flags */ 0, 18324 }, 18325 #endif /* chips */ 18326 18327 #if defined(BCM_53570_A0) 18328 { /* SOC_FORMAT_INT_ESMIF_COUNTER_BCM53570_A0fmt */ 18329 /* format ESMIF_COUNTERfmt */ 18330 /* nFields */ 9, 18331 /* *fields */ soc_ESMIF_COUNTER_BCM53400_A0fmt_fields, 18332 /* bits */ 9, 18333 /* flags */ 0, 18334 }, 18335 #endif /* chips */ 18336 18337 #if defined(BCM_53570_B0) 18338 { /* SOC_FORMAT_INT_ESMIF_COUNTER_BCM53570_B0fmt */ 18339 /* format ESMIF_COUNTERfmt */ 18340 /* nFields */ 9, 18341 /* *fields */ soc_ESMIF_COUNTER_BCM53400_A0fmt_fields, 18342 /* bits */ 9, 18343 /* flags */ 0, 18344 }, 18345 #endif /* chips */ 18346 18347 #if defined(BCM_56142_A0) 18348 { /* SOC_FORMAT_INT_ESMIF_COUNTER_BCM56142_A0fmt */ 18349 /* format ESMIF_COUNTERfmt */ 18350 /* nFields */ 9, 18351 /* *fields */ soc_ESMIF_COUNTERfmt_fields, 18352 /* bits */ 9, 18353 /* flags */ 0, 18354 }, 18355 #endif /* chips */ 18356 18357 #if defined(BCM_56150_A0) 18358 { /* SOC_FORMAT_INT_ESMIF_COUNTER_BCM56150_A0fmt */ 18359 /* format ESMIF_COUNTERfmt */ 18360 /* nFields */ 9, 18361 /* *fields */ soc_ESMIF_COUNTER_BCM56150_A0fmt_fields, 18362 /* bits */ 9, 18363 /* flags */ 0, 18364 }, 18365 #endif /* chips */ 18366 18367 #if defined(BCM_56160_A0) 18368 { /* SOC_FORMAT_INT_ESMIF_COUNTER_BCM56160_A0fmt */ 18369 /* format ESMIF_COUNTERfmt */ 18370 /* nFields */ 9, 18371 /* *fields */ soc_ESMIF_COUNTER_BCM53400_A0fmt_fields, 18372 /* bits */ 9, 18373 /* flags */ 0, 18374 }, 18375 #endif /* chips */ 18376 18377 #if defined(BCM_56334_B0) 18378 { /* SOC_FORMAT_INT_ESMIF_COUNTER_BCM56334_B0fmt */ 18379 /* format ESMIF_COUNTERfmt */ 18380 /* nFields */ 9, 18381 /* *fields */ soc_ESMIF_COUNTERfmt_fields, 18382 /* bits */ 9, 18383 /* flags */ 0, 18384 }, 18385 #endif /* chips */ 18386 18387 #if defined(BCM_56680_B0) 18388 { /* SOC_FORMAT_INT_ESMIF_COUNTER_BCM56680_B0fmt */ 18389 /* format ESMIF_COUNTERfmt */ 18390 /* nFields */ 9, 18391 /* *fields */ soc_ESMIF_COUNTERfmt_fields, 18392 /* bits */ 9, 18393 /* flags */ 0, 18394 }, 18395 #endif /* chips */ 18396 18397 #if defined(BCM_56685_A0) 18398 { /* SOC_FORMAT_INT_ESMIF_COUNTER_BCM56685_A0fmt */ 18399 /* format ESMIF_COUNTERfmt */ 18400 /* nFields */ 9, 18401 /* *fields */ soc_ESMIF_COUNTERfmt_fields, 18402 /* bits */ 9, 18403 /* flags */ 0, 18404 }, 18405 #endif /* chips */ 18406 18407 #if defined(BCM_56524_B0) || defined(BCM_56624_A0) || \ 18408 defined(BCM_56634_B0) 18409 { /* SOC_FORMAT_INT_ESMIF_DROPfmt */ 18410 /* format ESMIF_DROPfmt */ 18411 /* nFields */ 9, 18412 /* *fields */ soc_ESMIF_DROPfmt_fields, 18413 /* bits */ 9, 18414 /* flags */ 0, 18415 }, 18416 #endif /* chips */ 18417 18418 #if defined(BCM_53400_A0) 18419 { /* SOC_FORMAT_INT_ESMIF_DROP_BCM53400_A0fmt */ 18420 /* format ESMIF_DROPfmt */ 18421 /* nFields */ 9, 18422 /* *fields */ soc_ESMIF_DROP_BCM53400_A0fmt_fields, 18423 /* bits */ 9, 18424 /* flags */ 0, 18425 }, 18426 #endif /* chips */ 18427 18428 #if defined(BCM_53540_A0) 18429 { /* SOC_FORMAT_INT_ESMIF_DROP_BCM53540_A0fmt */ 18430 /* format ESMIF_DROPfmt */ 18431 /* nFields */ 9, 18432 /* *fields */ soc_ESMIF_DROP_BCM53400_A0fmt_fields, 18433 /* bits */ 9, 18434 /* flags */ 0, 18435 }, 18436 #endif /* chips */ 18437 18438 #if defined(BCM_53570_A0) 18439 { /* SOC_FORMAT_INT_ESMIF_DROP_BCM53570_A0fmt */ 18440 /* format ESMIF_DROPfmt */ 18441 /* nFields */ 9, 18442 /* *fields */ soc_ESMIF_DROP_BCM53400_A0fmt_fields, 18443 /* bits */ 9, 18444 /* flags */ 0, 18445 }, 18446 #endif /* chips */ 18447 18448 #if defined(BCM_53570_B0) 18449 { /* SOC_FORMAT_INT_ESMIF_DROP_BCM53570_B0fmt */ 18450 /* format ESMIF_DROPfmt */ 18451 /* nFields */ 9, 18452 /* *fields */ soc_ESMIF_DROP_BCM53400_A0fmt_fields, 18453 /* bits */ 9, 18454 /* flags */ 0, 18455 }, 18456 #endif /* chips */ 18457 18458 #if defined(BCM_56142_A0) 18459 { /* SOC_FORMAT_INT_ESMIF_DROP_BCM56142_A0fmt */ 18460 /* format ESMIF_DROPfmt */ 18461 /* nFields */ 9, 18462 /* *fields */ soc_ESMIF_DROPfmt_fields, 18463 /* bits */ 9, 18464 /* flags */ 0, 18465 }, 18466 #endif /* chips */ 18467 18468 #if defined(BCM_56150_A0) 18469 { /* SOC_FORMAT_INT_ESMIF_DROP_BCM56150_A0fmt */ 18470 /* format ESMIF_DROPfmt */ 18471 /* nFields */ 9, 18472 /* *fields */ soc_ESMIF_DROP_BCM56150_A0fmt_fields, 18473 /* bits */ 9, 18474 /* flags */ 0, 18475 }, 18476 #endif /* chips */ 18477 18478 #if defined(BCM_56160_A0) 18479 { /* SOC_FORMAT_INT_ESMIF_DROP_BCM56160_A0fmt */ 18480 /* format ESMIF_DROPfmt */ 18481 /* nFields */ 9, 18482 /* *fields */ soc_ESMIF_DROP_BCM53400_A0fmt_fields, 18483 /* bits */ 9, 18484 /* flags */ 0, 18485 }, 18486 #endif /* chips */ 18487 18488 #if defined(BCM_56334_A0) 18489 { /* SOC_FORMAT_INT_ESMIF_DROP_BCM56334_A0fmt */ 18490 /* format ESMIF_DROPfmt */ 18491 /* nFields */ 9, 18492 /* *fields */ soc_ESMIF_DROPfmt_fields, 18493 /* bits */ 9, 18494 /* flags */ 0, 18495 }, 18496 #endif /* chips */ 18497 18498 #if defined(BCM_56334_B0) 18499 { /* SOC_FORMAT_INT_ESMIF_DROP_BCM56334_B0fmt */ 18500 /* format ESMIF_DROPfmt */ 18501 /* nFields */ 9, 18502 /* *fields */ soc_ESMIF_DROPfmt_fields, 18503 /* bits */ 9, 18504 /* flags */ 0, 18505 }, 18506 #endif /* chips */ 18507 18508 #if defined(BCM_56524_A0) 18509 { /* SOC_FORMAT_INT_ESMIF_DROP_BCM56524_A0fmt */ 18510 /* format ESMIF_DROPfmt */ 18511 /* nFields */ 9, 18512 /* *fields */ soc_ESMIF_DROPfmt_fields, 18513 /* bits */ 9, 18514 /* flags */ 0, 18515 }, 18516 #endif /* chips */ 18517 18518 #if defined(BCM_56624_B0) 18519 { /* SOC_FORMAT_INT_ESMIF_DROP_BCM56624_B0fmt */ 18520 /* format ESMIF_DROPfmt */ 18521 /* nFields */ 9, 18522 /* *fields */ soc_ESMIF_DROPfmt_fields, 18523 /* bits */ 9, 18524 /* flags */ 0, 18525 }, 18526 #endif /* chips */ 18527 18528 #if defined(BCM_56634_A0) 18529 { /* SOC_FORMAT_INT_ESMIF_DROP_BCM56634_A0fmt */ 18530 /* format ESMIF_DROPfmt */ 18531 /* nFields */ 9, 18532 /* *fields */ soc_ESMIF_DROPfmt_fields, 18533 /* bits */ 9, 18534 /* flags */ 0, 18535 }, 18536 #endif /* chips */ 18537 18538 #if defined(BCM_56680_A0) 18539 { /* SOC_FORMAT_INT_ESMIF_DROP_BCM56680_A0fmt */ 18540 /* format ESMIF_DROPfmt */ 18541 /* nFields */ 9, 18542 /* *fields */ soc_ESMIF_DROPfmt_fields, 18543 /* bits */ 9, 18544 /* flags */ 0, 18545 }, 18546 #endif /* chips */ 18547 18548 #if defined(BCM_56680_B0) 18549 { /* SOC_FORMAT_INT_ESMIF_DROP_BCM56680_B0fmt */ 18550 /* format ESMIF_DROPfmt */ 18551 /* nFields */ 9, 18552 /* *fields */ soc_ESMIF_DROPfmt_fields, 18553 /* bits */ 9, 18554 /* flags */ 0, 18555 }, 18556 #endif /* chips */ 18557 18558 #if defined(BCM_56685_A0) 18559 { /* SOC_FORMAT_INT_ESMIF_DROP_BCM56685_A0fmt */ 18560 /* format ESMIF_DROPfmt */ 18561 /* nFields */ 9, 18562 /* *fields */ soc_ESMIF_DROPfmt_fields, 18563 /* bits */ 9, 18564 /* flags */ 0, 18565 }, 18566 #endif /* chips */ 18567 18568 #if defined(BCM_56685_B0) 18569 { /* SOC_FORMAT_INT_ESMIF_DROP_BCM56685_B0fmt */ 18570 /* format ESMIF_DROPfmt */ 18571 /* nFields */ 9, 18572 /* *fields */ soc_ESMIF_DROPfmt_fields, 18573 /* bits */ 9, 18574 /* flags */ 0, 18575 }, 18576 #endif /* chips */ 18577 18578 #if defined(BCM_56640_A0) 18579 { /* SOC_FORMAT_INT_ESM_ADM_CTRL_FIFOfmt */ 18580 /* format ESM_ADM_CTRL_FIFOfmt */ 18581 /* nFields */ 5, 18582 /* *fields */ soc_ESM_ADM_CTRL_FIFOfmt_fields, 18583 /* bits */ 53, 18584 /* flags */ 0, 18585 }, 18586 #endif /* chips */ 18587 18588 #if defined(BCM_56640_A0) 18589 { /* SOC_FORMAT_INT_ESM_AUX1_FIFOfmt */ 18590 /* format ESM_AUX1_FIFOfmt */ 18591 /* nFields */ 11, 18592 /* *fields */ soc_ESM_AUX1_FIFOfmt_fields, 18593 /* bits */ 28, 18594 /* flags */ 0, 18595 }, 18596 #endif /* chips */ 18597 18598 #if defined(BCM_56340_A0) || defined(BCM_56640_A0) 18599 { /* SOC_FORMAT_INT_ESM_COUNTER_SETfmt */ 18600 /* format ESM_COUNTER_SETfmt */ 18601 /* nFields */ 4, 18602 /* *fields */ soc_ESM_COUNTER_SETfmt_fields, 18603 /* bits */ 20, 18604 /* flags */ 0, 18605 }, 18606 #endif /* chips */ 18607 18608 #if defined(BCM_56334_A0) || defined(BCM_56524_A0) || \ 18609 defined(BCM_56524_B0) || defined(BCM_56624_A0) || \ 18610 defined(BCM_56624_B0) || defined(BCM_56634_A0) || \ 18611 defined(BCM_56634_B0) || defined(BCM_56685_B0) 18612 { /* SOC_FORMAT_INT_ESM_FP_CNTR_REQfmt */ 18613 /* format ESM_FP_CNTR_REQfmt */ 18614 /* nFields */ 2, 18615 /* *fields */ soc_ESM_FP_CNTR_REQfmt_fields, 18616 /* bits */ 36, 18617 /* flags */ 0, 18618 }, 18619 #endif /* chips */ 18620 18621 #if defined(BCM_53400_A0) 18622 { /* SOC_FORMAT_INT_ESM_FP_CNTR_REQ_BCM53400_A0fmt */ 18623 /* format ESM_FP_CNTR_REQfmt */ 18624 /* nFields */ 2, 18625 /* *fields */ soc_ESM_FP_CNTR_REQ_BCM53400_A0fmt_fields, 18626 /* bits */ 36, 18627 /* flags */ 0, 18628 }, 18629 #endif /* chips */ 18630 18631 #if defined(BCM_53540_A0) 18632 { /* SOC_FORMAT_INT_ESM_FP_CNTR_REQ_BCM53540_A0fmt */ 18633 /* format ESM_FP_CNTR_REQfmt */ 18634 /* nFields */ 2, 18635 /* *fields */ soc_ESM_FP_CNTR_REQ_BCM53400_A0fmt_fields, 18636 /* bits */ 36, 18637 /* flags */ 0, 18638 }, 18639 #endif /* chips */ 18640 18641 #if defined(BCM_53570_A0) 18642 { /* SOC_FORMAT_INT_ESM_FP_CNTR_REQ_BCM53570_A0fmt */ 18643 /* format ESM_FP_CNTR_REQfmt */ 18644 /* nFields */ 2, 18645 /* *fields */ soc_ESM_FP_CNTR_REQ_BCM53400_A0fmt_fields, 18646 /* bits */ 36, 18647 /* flags */ 0, 18648 }, 18649 #endif /* chips */ 18650 18651 #if defined(BCM_53570_B0) 18652 { /* SOC_FORMAT_INT_ESM_FP_CNTR_REQ_BCM53570_B0fmt */ 18653 /* format ESM_FP_CNTR_REQfmt */ 18654 /* nFields */ 2, 18655 /* *fields */ soc_ESM_FP_CNTR_REQ_BCM53400_A0fmt_fields, 18656 /* bits */ 36, 18657 /* flags */ 0, 18658 }, 18659 #endif /* chips */ 18660 18661 #if defined(BCM_56142_A0) 18662 { /* SOC_FORMAT_INT_ESM_FP_CNTR_REQ_BCM56142_A0fmt */ 18663 /* format ESM_FP_CNTR_REQfmt */ 18664 /* nFields */ 2, 18665 /* *fields */ soc_ESM_FP_CNTR_REQfmt_fields, 18666 /* bits */ 36, 18667 /* flags */ 0, 18668 }, 18669 #endif /* chips */ 18670 18671 #if defined(BCM_56150_A0) 18672 { /* SOC_FORMAT_INT_ESM_FP_CNTR_REQ_BCM56150_A0fmt */ 18673 /* format ESM_FP_CNTR_REQfmt */ 18674 /* nFields */ 2, 18675 /* *fields */ soc_ESM_FP_CNTR_REQ_BCM56150_A0fmt_fields, 18676 /* bits */ 36, 18677 /* flags */ 0, 18678 }, 18679 #endif /* chips */ 18680 18681 #if defined(BCM_56160_A0) 18682 { /* SOC_FORMAT_INT_ESM_FP_CNTR_REQ_BCM56160_A0fmt */ 18683 /* format ESM_FP_CNTR_REQfmt */ 18684 /* nFields */ 2, 18685 /* *fields */ soc_ESM_FP_CNTR_REQ_BCM53400_A0fmt_fields, 18686 /* bits */ 36, 18687 /* flags */ 0, 18688 }, 18689 #endif /* chips */ 18690 18691 #if defined(BCM_56334_B0) 18692 { /* SOC_FORMAT_INT_ESM_FP_CNTR_REQ_BCM56334_B0fmt */ 18693 /* format ESM_FP_CNTR_REQfmt */ 18694 /* nFields */ 2, 18695 /* *fields */ soc_ESM_FP_CNTR_REQfmt_fields, 18696 /* bits */ 36, 18697 /* flags */ 0, 18698 }, 18699 #endif /* chips */ 18700 18701 #if defined(BCM_56685_A0) 18702 { /* SOC_FORMAT_INT_ESM_FP_CNTR_REQ_BCM56685_A0fmt */ 18703 /* format ESM_FP_CNTR_REQfmt */ 18704 /* nFields */ 2, 18705 /* *fields */ soc_ESM_FP_CNTR_REQfmt_fields, 18706 /* bits */ 36, 18707 /* flags */ 0, 18708 }, 18709 #endif /* chips */ 18710 18711 #if defined(BCM_56624_A0) 18712 { /* SOC_FORMAT_INT_ESM_FULL_IPV6_ACL_KEYfmt */ 18713 /* format ESM_FULL_IPV6_ACL_KEYfmt */ 18714 /* nFields */ 37, 18715 /* *fields */ soc_ESM_FULL_IPV6_ACL_KEYfmt_fields, 18716 /* bits */ 432, 18717 /* flags */ 0, 18718 }, 18719 #endif /* chips */ 18720 18721 #if defined(BCM_56624_B0) 18722 { /* SOC_FORMAT_INT_ESM_FULL_IPV6_ACL_KEY_BCM56624_B0fmt */ 18723 /* format ESM_FULL_IPV6_ACL_KEYfmt */ 18724 /* nFields */ 37, 18725 /* *fields */ soc_ESM_FULL_IPV6_ACL_KEYfmt_fields, 18726 /* bits */ 432, 18727 /* flags */ 0, 18728 }, 18729 #endif /* chips */ 18730 18731 #if defined(BCM_56634_A0) 18732 { /* SOC_FORMAT_INT_ESM_FULL_IPV6_ACL_KEY_BCM56634_A0fmt */ 18733 /* format ESM_FULL_IPV6_ACL_KEYfmt */ 18734 /* nFields */ 37, 18735 /* *fields */ soc_ESM_FULL_IPV6_ACL_KEYfmt_fields, 18736 /* bits */ 432, 18737 /* flags */ 0, 18738 }, 18739 #endif /* chips */ 18740 18741 #if defined(BCM_56634_B0) 18742 { /* SOC_FORMAT_INT_ESM_FULL_IPV6_ACL_KEY_BCM56634_B0fmt */ 18743 /* format ESM_FULL_IPV6_ACL_KEYfmt */ 18744 /* nFields */ 37, 18745 /* *fields */ soc_ESM_FULL_IPV6_ACL_KEYfmt_fields, 18746 /* bits */ 432, 18747 /* flags */ 0, 18748 }, 18749 #endif /* chips */ 18750 18751 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \ 18752 defined(BCM_56634_A0) || defined(BCM_56634_B0) 18753 { /* SOC_FORMAT_INT_ESM_IPV4_ACL144_KEYfmt */ 18754 /* format ESM_IPV4_ACL144_KEYfmt */ 18755 /* nFields */ 15, 18756 /* *fields */ soc_ESM_IPV4_ACL144_KEYfmt_fields, 18757 /* bits */ 144, 18758 /* flags */ 0, 18759 }, 18760 #endif /* chips */ 18761 18762 #if defined(BCM_56624_A0) 18763 { /* SOC_FORMAT_INT_ESM_IPV4_ACL_7K_KEYfmt */ 18764 /* format ESM_IPV4_ACL_7K_KEYfmt */ 18765 /* nFields */ 40, 18766 /* *fields */ soc_ESM_IPV4_ACL_7K_KEYfmt_fields, 18767 /* bits */ 288, 18768 /* flags */ 0, 18769 }, 18770 #endif /* chips */ 18771 18772 #if defined(BCM_56624_B0) 18773 { /* SOC_FORMAT_INT_ESM_IPV4_ACL_7K_KEY_BCM56624_B0fmt */ 18774 /* format ESM_IPV4_ACL_7K_KEYfmt */ 18775 /* nFields */ 40, 18776 /* *fields */ soc_ESM_IPV4_ACL_7K_KEYfmt_fields, 18777 /* bits */ 288, 18778 /* flags */ 0, 18779 }, 18780 #endif /* chips */ 18781 18782 #if defined(BCM_56634_A0) 18783 { /* SOC_FORMAT_INT_ESM_IPV4_ACL_7K_KEY_BCM56634_A0fmt */ 18784 /* format ESM_IPV4_ACL_7K_KEYfmt */ 18785 /* nFields */ 40, 18786 /* *fields */ soc_ESM_IPV4_ACL_7K_KEYfmt_fields, 18787 /* bits */ 288, 18788 /* flags */ 0, 18789 }, 18790 #endif /* chips */ 18791 18792 #if defined(BCM_56634_B0) 18793 { /* SOC_FORMAT_INT_ESM_IPV4_ACL_7K_KEY_BCM56634_B0fmt */ 18794 /* format ESM_IPV4_ACL_7K_KEYfmt */ 18795 /* nFields */ 40, 18796 /* *fields */ soc_ESM_IPV4_ACL_7K_KEYfmt_fields, 18797 /* bits */ 288, 18798 /* flags */ 0, 18799 }, 18800 #endif /* chips */ 18801 18802 #if defined(BCM_56624_A0) 18803 { /* SOC_FORMAT_INT_ESM_IPV4_ACL_KEYfmt */ 18804 /* format ESM_IPV4_ACL_KEYfmt */ 18805 /* nFields */ 37, 18806 /* *fields */ soc_ESM_IPV4_ACL_KEYfmt_fields, 18807 /* bits */ 288, 18808 /* flags */ 0, 18809 }, 18810 #endif /* chips */ 18811 18812 #if defined(BCM_56624_B0) 18813 { /* SOC_FORMAT_INT_ESM_IPV4_ACL_KEY_BCM56624_B0fmt */ 18814 /* format ESM_IPV4_ACL_KEYfmt */ 18815 /* nFields */ 37, 18816 /* *fields */ soc_ESM_IPV4_ACL_KEYfmt_fields, 18817 /* bits */ 288, 18818 /* flags */ 0, 18819 }, 18820 #endif /* chips */ 18821 18822 #if defined(BCM_56634_A0) 18823 { /* SOC_FORMAT_INT_ESM_IPV4_ACL_KEY_BCM56634_A0fmt */ 18824 /* format ESM_IPV4_ACL_KEYfmt */ 18825 /* nFields */ 37, 18826 /* *fields */ soc_ESM_IPV4_ACL_KEYfmt_fields, 18827 /* bits */ 288, 18828 /* flags */ 0, 18829 }, 18830 #endif /* chips */ 18831 18832 #if defined(BCM_56634_B0) 18833 { /* SOC_FORMAT_INT_ESM_IPV4_ACL_KEY_BCM56634_B0fmt */ 18834 /* format ESM_IPV4_ACL_KEYfmt */ 18835 /* nFields */ 37, 18836 /* *fields */ soc_ESM_IPV4_ACL_KEYfmt_fields, 18837 /* bits */ 288, 18838 /* flags */ 0, 18839 }, 18840 #endif /* chips */ 18841 18842 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \ 18843 defined(BCM_56634_A0) || defined(BCM_56634_B0) 18844 { /* SOC_FORMAT_INT_ESM_IPV6_ACL144_KEYfmt */ 18845 /* format ESM_IPV6_ACL144_KEYfmt */ 18846 /* nFields */ 4, 18847 /* *fields */ soc_ESM_IPV6_ACL144_KEYfmt_fields, 18848 /* bits */ 144, 18849 /* flags */ 0, 18850 }, 18851 #endif /* chips */ 18852 18853 #if defined(BCM_56340_A0) || defined(BCM_56640_A0) 18854 { /* SOC_FORMAT_INT_ESM_KEYGEN_F10_MUX_SELfmt */ 18855 /* format ESM_KEYGEN_F10_MUX_SELfmt */ 18856 /* nFields */ 1, 18857 /* *fields */ soc_ESM_KEYGEN_F10_MUX_SELfmt_fields, 18858 /* bits */ 3, 18859 /* flags */ 0, 18860 }, 18861 #endif /* chips */ 18862 18863 #if defined(BCM_56640_A0) 18864 { /* SOC_FORMAT_INT_ESM_KEYGEN_F11_MUX_SELfmt */ 18865 /* format ESM_KEYGEN_F11_MUX_SELfmt */ 18866 /* nFields */ 1, 18867 /* *fields */ soc_ESM_KEYGEN_F10_MUX_SELfmt_fields, 18868 /* bits */ 3, 18869 /* flags */ 0, 18870 }, 18871 #endif /* chips */ 18872 18873 #if defined(BCM_56340_A0) 18874 { /* SOC_FORMAT_INT_ESM_KEYGEN_F11_MUX_SEL_BCM56340_A0fmt */ 18875 /* format ESM_KEYGEN_F11_MUX_SELfmt */ 18876 /* nFields */ 1, 18877 /* *fields */ soc_ESM_KEYGEN_F10_MUX_SELfmt_fields, 18878 /* bits */ 3, 18879 /* flags */ 0, 18880 }, 18881 #endif /* chips */ 18882 18883 #if defined(BCM_56640_A0) 18884 { /* SOC_FORMAT_INT_ESM_KEYGEN_F1_MUX_SELfmt */ 18885 /* format ESM_KEYGEN_F1_MUX_SELfmt */ 18886 /* nFields */ 1, 18887 /* *fields */ soc_ESM_KEYGEN_F10_MUX_SELfmt_fields, 18888 /* bits */ 3, 18889 /* flags */ 0, 18890 }, 18891 #endif /* chips */ 18892 18893 #if defined(BCM_56340_A0) 18894 { /* SOC_FORMAT_INT_ESM_KEYGEN_F1_MUX_SEL_BCM56340_A0fmt */ 18895 /* format ESM_KEYGEN_F1_MUX_SELfmt */ 18896 /* nFields */ 1, 18897 /* *fields */ soc_ESM_KEYGEN_F10_MUX_SELfmt_fields, 18898 /* bits */ 3, 18899 /* flags */ 0, 18900 }, 18901 #endif /* chips */ 18902 18903 #if defined(BCM_56340_A0) || defined(BCM_56640_A0) 18904 { /* SOC_FORMAT_INT_ESM_KEYGEN_F3_MUX_SELfmt */ 18905 /* format ESM_KEYGEN_F3_MUX_SELfmt */ 18906 /* nFields */ 1, 18907 /* *fields */ soc_ESM_KEYGEN_F3_MUX_SELfmt_fields, 18908 /* bits */ 5, 18909 /* flags */ 0, 18910 }, 18911 #endif /* chips */ 18912 18913 #if defined(BCM_56640_A0) 18914 { /* SOC_FORMAT_INT_ESM_KEYGEN_F4_MUX_SELfmt */ 18915 /* format ESM_KEYGEN_F4_MUX_SELfmt */ 18916 /* nFields */ 1, 18917 /* *fields */ soc_ESM_KEYGEN_F3_MUX_SELfmt_fields, 18918 /* bits */ 5, 18919 /* flags */ 0, 18920 }, 18921 #endif /* chips */ 18922 18923 #if defined(BCM_56340_A0) 18924 { /* SOC_FORMAT_INT_ESM_KEYGEN_F4_MUX_SEL_BCM56340_A0fmt */ 18925 /* format ESM_KEYGEN_F4_MUX_SELfmt */ 18926 /* nFields */ 1, 18927 /* *fields */ soc_ESM_KEYGEN_F3_MUX_SELfmt_fields, 18928 /* bits */ 5, 18929 /* flags */ 0, 18930 }, 18931 #endif /* chips */ 18932 18933 #if defined(BCM_56640_A0) 18934 { /* SOC_FORMAT_INT_ESM_KEYGEN_F5_MUX_SELfmt */ 18935 /* format ESM_KEYGEN_F5_MUX_SELfmt */ 18936 /* nFields */ 1, 18937 /* *fields */ soc_ESM_KEYGEN_F3_MUX_SELfmt_fields, 18938 /* bits */ 5, 18939 /* flags */ 0, 18940 }, 18941 #endif /* chips */ 18942 18943 #if defined(BCM_56340_A0) 18944 { /* SOC_FORMAT_INT_ESM_KEYGEN_F5_MUX_SEL_BCM56340_A0fmt */ 18945 /* format ESM_KEYGEN_F5_MUX_SELfmt */ 18946 /* nFields */ 1, 18947 /* *fields */ soc_ESM_KEYGEN_F3_MUX_SELfmt_fields, 18948 /* bits */ 5, 18949 /* flags */ 0, 18950 }, 18951 #endif /* chips */ 18952 18953 #if defined(BCM_56640_A0) 18954 { /* SOC_FORMAT_INT_ESM_KEYGEN_F6_MUX_SELfmt */ 18955 /* format ESM_KEYGEN_F6_MUX_SELfmt */ 18956 /* nFields */ 1, 18957 /* *fields */ soc_ESM_KEYGEN_F3_MUX_SELfmt_fields, 18958 /* bits */ 5, 18959 /* flags */ 0, 18960 }, 18961 #endif /* chips */ 18962 18963 #if defined(BCM_56340_A0) 18964 { /* SOC_FORMAT_INT_ESM_KEYGEN_F6_MUX_SEL_BCM56340_A0fmt */ 18965 /* format ESM_KEYGEN_F6_MUX_SELfmt */ 18966 /* nFields */ 1, 18967 /* *fields */ soc_ESM_KEYGEN_F3_MUX_SELfmt_fields, 18968 /* bits */ 5, 18969 /* flags */ 0, 18970 }, 18971 #endif /* chips */ 18972 18973 #if defined(BCM_56640_A0) 18974 { /* SOC_FORMAT_INT_ESM_KEYGEN_F7_MUX_SELfmt */ 18975 /* format ESM_KEYGEN_F7_MUX_SELfmt */ 18976 /* nFields */ 1, 18977 /* *fields */ soc_ESM_KEYGEN_F3_MUX_SELfmt_fields, 18978 /* bits */ 5, 18979 /* flags */ 0, 18980 }, 18981 #endif /* chips */ 18982 18983 #if defined(BCM_56340_A0) 18984 { /* SOC_FORMAT_INT_ESM_KEYGEN_F7_MUX_SEL_BCM56340_A0fmt */ 18985 /* format ESM_KEYGEN_F7_MUX_SELfmt */ 18986 /* nFields */ 1, 18987 /* *fields */ soc_ESM_KEYGEN_F3_MUX_SELfmt_fields, 18988 /* bits */ 5, 18989 /* flags */ 0, 18990 }, 18991 #endif /* chips */ 18992 18993 #if defined(BCM_56640_A0) 18994 { /* SOC_FORMAT_INT_ESM_KEYGEN_F8_MUX_SELfmt */ 18995 /* format ESM_KEYGEN_F8_MUX_SELfmt */ 18996 /* nFields */ 1, 18997 /* *fields */ soc_ESM_KEYGEN_F3_MUX_SELfmt_fields, 18998 /* bits */ 5, 18999 /* flags */ 0, 19000 }, 19001 #endif /* chips */ 19002 19003 #if defined(BCM_56340_A0) 19004 { /* SOC_FORMAT_INT_ESM_KEYGEN_F8_MUX_SEL_BCM56340_A0fmt */ 19005 /* format ESM_KEYGEN_F8_MUX_SELfmt */ 19006 /* nFields */ 1, 19007 /* *fields */ soc_ESM_KEYGEN_F3_MUX_SELfmt_fields, 19008 /* bits */ 5, 19009 /* flags */ 0, 19010 }, 19011 #endif /* chips */ 19012 19013 #if defined(BCM_56640_A0) 19014 { /* SOC_FORMAT_INT_ESM_KEYGEN_F9_MUX_SELfmt */ 19015 /* format ESM_KEYGEN_F9_MUX_SELfmt */ 19016 /* nFields */ 1, 19017 /* *fields */ soc_ESM_KEYGEN_F10_MUX_SELfmt_fields, 19018 /* bits */ 3, 19019 /* flags */ 0, 19020 }, 19021 #endif /* chips */ 19022 19023 #if defined(BCM_56340_A0) 19024 { /* SOC_FORMAT_INT_ESM_KEYGEN_F9_MUX_SEL_BCM56340_A0fmt */ 19025 /* format ESM_KEYGEN_F9_MUX_SELfmt */ 19026 /* nFields */ 1, 19027 /* *fields */ soc_ESM_KEYGEN_F10_MUX_SELfmt_fields, 19028 /* bits */ 3, 19029 /* flags */ 0, 19030 }, 19031 #endif /* chips */ 19032 19033 #if defined(BCM_56340_A0) || defined(BCM_56640_A0) 19034 { /* SOC_FORMAT_INT_ESM_KEYGEN_FLAGS_MUX_SELfmt */ 19035 /* format ESM_KEYGEN_FLAGS_MUX_SELfmt */ 19036 /* nFields */ 1, 19037 /* *fields */ soc_ESM_KEYGEN_FLAGS_MUX_SELfmt_fields, 19038 /* bits */ 7, 19039 /* flags */ 0, 19040 }, 19041 #endif /* chips */ 19042 19043 #if defined(BCM_56624_A0) || defined(BCM_56634_A0) || \ 19044 defined(BCM_56634_B0) 19045 { /* SOC_FORMAT_INT_ESM_L2_ACL144_KEYfmt */ 19046 /* format ESM_L2_ACL144_KEYfmt */ 19047 /* nFields */ 8, 19048 /* *fields */ soc_ESM_L2_ACL144_KEYfmt_fields, 19049 /* bits */ 144, 19050 /* flags */ 0, 19051 }, 19052 #endif /* chips */ 19053 19054 #if defined(BCM_56624_B0) 19055 { /* SOC_FORMAT_INT_ESM_L2_ACL144_KEY_BCM56624_B0fmt */ 19056 /* format ESM_L2_ACL144_KEYfmt */ 19057 /* nFields */ 8, 19058 /* *fields */ soc_ESM_L2_ACL144_KEYfmt_fields, 19059 /* bits */ 144, 19060 /* flags */ 0, 19061 }, 19062 #endif /* chips */ 19063 19064 #if defined(BCM_56624_A0) || defined(BCM_56634_A0) || \ 19065 defined(BCM_56634_B0) 19066 { /* SOC_FORMAT_INT_ESM_L2_ACL_7K_KEYfmt */ 19067 /* format ESM_L2_ACL_7K_KEYfmt */ 19068 /* nFields */ 36, 19069 /* *fields */ soc_ESM_L2_ACL_7K_KEYfmt_fields, 19070 /* bits */ 288, 19071 /* flags */ 0, 19072 }, 19073 #endif /* chips */ 19074 19075 #if defined(BCM_56624_B0) 19076 { /* SOC_FORMAT_INT_ESM_L2_ACL_7K_KEY_BCM56624_B0fmt */ 19077 /* format ESM_L2_ACL_7K_KEYfmt */ 19078 /* nFields */ 36, 19079 /* *fields */ soc_ESM_L2_ACL_7K_KEYfmt_fields, 19080 /* bits */ 288, 19081 /* flags */ 0, 19082 }, 19083 #endif /* chips */ 19084 19085 #if defined(BCM_56624_A0) || defined(BCM_56634_A0) || \ 19086 defined(BCM_56634_B0) 19087 { /* SOC_FORMAT_INT_ESM_L2_ACL_KEYfmt */ 19088 /* format ESM_L2_ACL_KEYfmt */ 19089 /* nFields */ 32, 19090 /* *fields */ soc_ESM_L2_ACL_KEYfmt_fields, 19091 /* bits */ 288, 19092 /* flags */ 0, 19093 }, 19094 #endif /* chips */ 19095 19096 #if defined(BCM_56624_B0) 19097 { /* SOC_FORMAT_INT_ESM_L2_ACL_KEY_BCM56624_B0fmt */ 19098 /* format ESM_L2_ACL_KEYfmt */ 19099 /* nFields */ 32, 19100 /* *fields */ soc_ESM_L2_ACL_KEYfmt_fields, 19101 /* bits */ 288, 19102 /* flags */ 0, 19103 }, 19104 #endif /* chips */ 19105 19106 #if defined(BCM_56624_A0) 19107 { /* SOC_FORMAT_INT_ESM_L2_IPV4_ACL_KEYfmt */ 19108 /* format ESM_L2_IPV4_ACL_KEYfmt */ 19109 /* nFields */ 45, 19110 /* *fields */ soc_ESM_L2_IPV4_ACL_KEYfmt_fields, 19111 /* bits */ 432, 19112 /* flags */ 0, 19113 }, 19114 #endif /* chips */ 19115 19116 #if defined(BCM_56624_B0) 19117 { /* SOC_FORMAT_INT_ESM_L2_IPV4_ACL_KEY_BCM56624_B0fmt */ 19118 /* format ESM_L2_IPV4_ACL_KEYfmt */ 19119 /* nFields */ 45, 19120 /* *fields */ soc_ESM_L2_IPV4_ACL_KEYfmt_fields, 19121 /* bits */ 432, 19122 /* flags */ 0, 19123 }, 19124 #endif /* chips */ 19125 19126 #if defined(BCM_56634_A0) 19127 { /* SOC_FORMAT_INT_ESM_L2_IPV4_ACL_KEY_BCM56634_A0fmt */ 19128 /* format ESM_L2_IPV4_ACL_KEYfmt */ 19129 /* nFields */ 45, 19130 /* *fields */ soc_ESM_L2_IPV4_ACL_KEYfmt_fields, 19131 /* bits */ 432, 19132 /* flags */ 0, 19133 }, 19134 #endif /* chips */ 19135 19136 #if defined(BCM_56634_B0) 19137 { /* SOC_FORMAT_INT_ESM_L2_IPV4_ACL_KEY_BCM56634_B0fmt */ 19138 /* format ESM_L2_IPV4_ACL_KEYfmt */ 19139 /* nFields */ 45, 19140 /* *fields */ soc_ESM_L2_IPV4_ACL_KEYfmt_fields, 19141 /* bits */ 432, 19142 /* flags */ 0, 19143 }, 19144 #endif /* chips */ 19145 19146 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \ 19147 defined(BCM_56634_A0) || defined(BCM_56634_B0) 19148 { /* SOC_FORMAT_INT_ESM_L2_IPV6_ACL_KEYfmt */ 19149 /* format ESM_L2_IPV6_ACL_KEYfmt */ 19150 /* nFields */ 30, 19151 /* *fields */ soc_ESM_L2_IPV6_ACL_KEYfmt_fields, 19152 /* bits */ 432, 19153 /* flags */ 0, 19154 }, 19155 #endif /* chips */ 19156 19157 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \ 19158 defined(BCM_56634_B0) 19159 { /* SOC_FORMAT_INT_ESM_RSP_WORD_0_ERR_INFOfmt */ 19160 /* format ESM_RSP_WORD_0_ERR_INFOfmt */ 19161 /* nFields */ 4, 19162 /* *fields */ soc_ESM_RSP_WORD_0_ERR_INFOfmt_fields, 19163 /* bits */ 4, 19164 /* flags */ 0, 19165 }, 19166 #endif /* chips */ 19167 19168 #if defined(BCM_56634_A0) 19169 { /* SOC_FORMAT_INT_ESM_RSP_WORD_0_ERR_INFO_BCM56634_A0fmt */ 19170 /* format ESM_RSP_WORD_0_ERR_INFOfmt */ 19171 /* nFields */ 4, 19172 /* *fields */ soc_ESM_RSP_WORD_0_ERR_INFOfmt_fields, 19173 /* bits */ 4, 19174 /* flags */ 0, 19175 }, 19176 #endif /* chips */ 19177 19178 #if defined(BCM_56334_A0) || defined(BCM_56624_A0) || \ 19179 defined(BCM_56634_A0) 19180 { /* SOC_FORMAT_INT_ESM_SEARCH_REQUESTfmt */ 19181 /* format ESM_SEARCH_REQUESTfmt */ 19182 /* nFields */ 17, 19183 /* *fields */ soc_ESM_SEARCH_REQUESTfmt_fields, 19184 /* bits */ 576, 19185 /* flags */ 0, 19186 }, 19187 #endif /* chips */ 19188 19189 #if defined(BCM_53400_A0) 19190 { /* SOC_FORMAT_INT_ESM_SEARCH_REQUEST_BCM53400_A0fmt */ 19191 /* format ESM_SEARCH_REQUESTfmt */ 19192 /* nFields */ 17, 19193 /* *fields */ soc_ESM_SEARCH_REQUEST_BCM53400_A0fmt_fields, 19194 /* bits */ 576, 19195 /* flags */ 0, 19196 }, 19197 #endif /* chips */ 19198 19199 #if defined(BCM_53540_A0) 19200 { /* SOC_FORMAT_INT_ESM_SEARCH_REQUEST_BCM53540_A0fmt */ 19201 /* format ESM_SEARCH_REQUESTfmt */ 19202 /* nFields */ 17, 19203 /* *fields */ soc_ESM_SEARCH_REQUEST_BCM53400_A0fmt_fields, 19204 /* bits */ 576, 19205 /* flags */ 0, 19206 }, 19207 #endif /* chips */ 19208 19209 #if defined(BCM_53570_A0) 19210 { /* SOC_FORMAT_INT_ESM_SEARCH_REQUEST_BCM53570_A0fmt */ 19211 /* format ESM_SEARCH_REQUESTfmt */ 19212 /* nFields */ 17, 19213 /* *fields */ soc_ESM_SEARCH_REQUEST_BCM53400_A0fmt_fields, 19214 /* bits */ 576, 19215 /* flags */ 0, 19216 }, 19217 #endif /* chips */ 19218 19219 #if defined(BCM_53570_B0) 19220 { /* SOC_FORMAT_INT_ESM_SEARCH_REQUEST_BCM53570_B0fmt */ 19221 /* format ESM_SEARCH_REQUESTfmt */ 19222 /* nFields */ 17, 19223 /* *fields */ soc_ESM_SEARCH_REQUEST_BCM53400_A0fmt_fields, 19224 /* bits */ 576, 19225 /* flags */ 0, 19226 }, 19227 #endif /* chips */ 19228 19229 #if defined(BCM_56142_A0) 19230 { /* SOC_FORMAT_INT_ESM_SEARCH_REQUEST_BCM56142_A0fmt */ 19231 /* format ESM_SEARCH_REQUESTfmt */ 19232 /* nFields */ 17, 19233 /* *fields */ soc_ESM_SEARCH_REQUESTfmt_fields, 19234 /* bits */ 576, 19235 /* flags */ 0, 19236 }, 19237 #endif /* chips */ 19238 19239 #if defined(BCM_56150_A0) 19240 { /* SOC_FORMAT_INT_ESM_SEARCH_REQUEST_BCM56150_A0fmt */ 19241 /* format ESM_SEARCH_REQUESTfmt */ 19242 /* nFields */ 17, 19243 /* *fields */ soc_ESM_SEARCH_REQUEST_BCM56150_A0fmt_fields, 19244 /* bits */ 576, 19245 /* flags */ 0, 19246 }, 19247 #endif /* chips */ 19248 19249 #if defined(BCM_56160_A0) 19250 { /* SOC_FORMAT_INT_ESM_SEARCH_REQUEST_BCM56160_A0fmt */ 19251 /* format ESM_SEARCH_REQUESTfmt */ 19252 /* nFields */ 17, 19253 /* *fields */ soc_ESM_SEARCH_REQUEST_BCM53400_A0fmt_fields, 19254 /* bits */ 576, 19255 /* flags */ 0, 19256 }, 19257 #endif /* chips */ 19258 19259 #if defined(BCM_56334_B0) 19260 { /* SOC_FORMAT_INT_ESM_SEARCH_REQUEST_BCM56334_B0fmt */ 19261 /* format ESM_SEARCH_REQUESTfmt */ 19262 /* nFields */ 17, 19263 /* *fields */ soc_ESM_SEARCH_REQUESTfmt_fields, 19264 /* bits */ 576, 19265 /* flags */ 0, 19266 }, 19267 #endif /* chips */ 19268 19269 #if defined(BCM_56624_B0) 19270 { /* SOC_FORMAT_INT_ESM_SEARCH_REQUEST_BCM56624_B0fmt */ 19271 /* format ESM_SEARCH_REQUESTfmt */ 19272 /* nFields */ 17, 19273 /* *fields */ soc_ESM_SEARCH_REQUESTfmt_fields, 19274 /* bits */ 576, 19275 /* flags */ 0, 19276 }, 19277 #endif /* chips */ 19278 19279 #if defined(BCM_56634_B0) 19280 { /* SOC_FORMAT_INT_ESM_SEARCH_REQUEST_BCM56634_B0fmt */ 19281 /* format ESM_SEARCH_REQUESTfmt */ 19282 /* nFields */ 17, 19283 /* *fields */ soc_ESM_SEARCH_REQUESTfmt_fields, 19284 /* bits */ 576, 19285 /* flags */ 0, 19286 }, 19287 #endif /* chips */ 19288 19289 #if defined(BCM_56624_A0) 19290 { /* SOC_FORMAT_INT_ESM_SEARCH_RESULTSfmt */ 19291 /* format ESM_SEARCH_RESULTSfmt */ 19292 /* nFields */ 13, 19293 /* *fields */ soc_ESM_SEARCH_RESULTSfmt_fields, 19294 /* bits */ 288, 19295 /* flags */ 0, 19296 }, 19297 #endif /* chips */ 19298 19299 #if defined(BCM_53400_A0) 19300 { /* SOC_FORMAT_INT_ESM_SEARCH_RESULTS_BCM53400_A0fmt */ 19301 /* format ESM_SEARCH_RESULTSfmt */ 19302 /* nFields */ 13, 19303 /* *fields */ soc_ESM_SEARCH_RESULTS_BCM53400_A0fmt_fields, 19304 /* bits */ 288, 19305 /* flags */ 0, 19306 }, 19307 #endif /* chips */ 19308 19309 #if defined(BCM_53540_A0) 19310 { /* SOC_FORMAT_INT_ESM_SEARCH_RESULTS_BCM53540_A0fmt */ 19311 /* format ESM_SEARCH_RESULTSfmt */ 19312 /* nFields */ 13, 19313 /* *fields */ soc_ESM_SEARCH_RESULTS_BCM53400_A0fmt_fields, 19314 /* bits */ 288, 19315 /* flags */ 0, 19316 }, 19317 #endif /* chips */ 19318 19319 #if defined(BCM_53570_A0) 19320 { /* SOC_FORMAT_INT_ESM_SEARCH_RESULTS_BCM53570_A0fmt */ 19321 /* format ESM_SEARCH_RESULTSfmt */ 19322 /* nFields */ 13, 19323 /* *fields */ soc_ESM_SEARCH_RESULTS_BCM53400_A0fmt_fields, 19324 /* bits */ 288, 19325 /* flags */ 0, 19326 }, 19327 #endif /* chips */ 19328 19329 #if defined(BCM_53570_B0) 19330 { /* SOC_FORMAT_INT_ESM_SEARCH_RESULTS_BCM53570_B0fmt */ 19331 /* format ESM_SEARCH_RESULTSfmt */ 19332 /* nFields */ 13, 19333 /* *fields */ soc_ESM_SEARCH_RESULTS_BCM53400_A0fmt_fields, 19334 /* bits */ 288, 19335 /* flags */ 0, 19336 }, 19337 #endif /* chips */ 19338 19339 #if defined(BCM_56142_A0) 19340 { /* SOC_FORMAT_INT_ESM_SEARCH_RESULTS_BCM56142_A0fmt */ 19341 /* format ESM_SEARCH_RESULTSfmt */ 19342 /* nFields */ 13, 19343 /* *fields */ soc_ESM_SEARCH_RESULTSfmt_fields, 19344 /* bits */ 288, 19345 /* flags */ 0, 19346 }, 19347 #endif /* chips */ 19348 19349 #if defined(BCM_56150_A0) 19350 { /* SOC_FORMAT_INT_ESM_SEARCH_RESULTS_BCM56150_A0fmt */ 19351 /* format ESM_SEARCH_RESULTSfmt */ 19352 /* nFields */ 13, 19353 /* *fields */ soc_ESM_SEARCH_RESULTS_BCM56150_A0fmt_fields, 19354 /* bits */ 288, 19355 /* flags */ 0, 19356 }, 19357 #endif /* chips */ 19358 19359 #if defined(BCM_56160_A0) 19360 { /* SOC_FORMAT_INT_ESM_SEARCH_RESULTS_BCM56160_A0fmt */ 19361 /* format ESM_SEARCH_RESULTSfmt */ 19362 /* nFields */ 13, 19363 /* *fields */ soc_ESM_SEARCH_RESULTS_BCM53400_A0fmt_fields, 19364 /* bits */ 288, 19365 /* flags */ 0, 19366 }, 19367 #endif /* chips */ 19368 19369 #if defined(BCM_56334_A0) 19370 { /* SOC_FORMAT_INT_ESM_SEARCH_RESULTS_BCM56334_A0fmt */ 19371 /* format ESM_SEARCH_RESULTSfmt */ 19372 /* nFields */ 13, 19373 /* *fields */ soc_ESM_SEARCH_RESULTSfmt_fields, 19374 /* bits */ 288, 19375 /* flags */ 0, 19376 }, 19377 #endif /* chips */ 19378 19379 #if defined(BCM_56334_B0) 19380 { /* SOC_FORMAT_INT_ESM_SEARCH_RESULTS_BCM56334_B0fmt */ 19381 /* format ESM_SEARCH_RESULTSfmt */ 19382 /* nFields */ 13, 19383 /* *fields */ soc_ESM_SEARCH_RESULTSfmt_fields, 19384 /* bits */ 288, 19385 /* flags */ 0, 19386 }, 19387 #endif /* chips */ 19388 19389 #if defined(BCM_56624_B0) 19390 { /* SOC_FORMAT_INT_ESM_SEARCH_RESULTS_BCM56624_B0fmt */ 19391 /* format ESM_SEARCH_RESULTSfmt */ 19392 /* nFields */ 13, 19393 /* *fields */ soc_ESM_SEARCH_RESULTSfmt_fields, 19394 /* bits */ 288, 19395 /* flags */ 0, 19396 }, 19397 #endif /* chips */ 19398 19399 #if defined(BCM_56634_A0) 19400 { /* SOC_FORMAT_INT_ESM_SEARCH_RESULTS_BCM56634_A0fmt */ 19401 /* format ESM_SEARCH_RESULTSfmt */ 19402 /* nFields */ 13, 19403 /* *fields */ soc_ESM_SEARCH_RESULTS_BCM56634_A0fmt_fields, 19404 /* bits */ 288, 19405 /* flags */ 0, 19406 }, 19407 #endif /* chips */ 19408 19409 #if defined(BCM_56634_B0) 19410 { /* SOC_FORMAT_INT_ESM_SEARCH_RESULTS_BCM56634_B0fmt */ 19411 /* format ESM_SEARCH_RESULTSfmt */ 19412 /* nFields */ 13, 19413 /* *fields */ soc_ESM_SEARCH_RESULTS_BCM56634_A0fmt_fields, 19414 /* bits */ 288, 19415 /* flags */ 0, 19416 }, 19417 #endif /* chips */ 19418 19419 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \ 19420 defined(BCM_56634_A0) || defined(BCM_56634_B0) 19421 { /* SOC_FORMAT_INT_ESM_SHORT_IPV6_ACL_KEYfmt */ 19422 /* format ESM_SHORT_IPV6_ACL_KEYfmt */ 19423 /* nFields */ 25, 19424 /* *fields */ soc_ESM_SHORT_IPV6_ACL_KEYfmt_fields, 19425 /* bits */ 360, 19426 /* flags */ 0, 19427 }, 19428 #endif /* chips */ 19429 19430 #if defined(BCM_56340_A0) || defined(BCM_56640_A0) 19431 { /* SOC_FORMAT_INT_ESM_SVC_SETfmt */ 19432 /* format ESM_SVC_SETfmt */ 19433 /* nFields */ 3, 19434 /* *fields */ soc_ESM_SVC_SETfmt_fields, 19435 /* bits */ 19, 19436 /* flags */ 0, 19437 }, 19438 #endif /* chips */ 19439 19440 #if defined(BCM_56860_A0) 19441 { /* SOC_FORMAT_INT_ES_TO_DEQ_PORT_DEMAND_STfmt */ 19442 /* format ES_TO_DEQ_PORT_DEMAND_STfmt */ 19443 /* nFields */ 2, 19444 /* *fields */ soc_ES_TO_DEQ_PORT_DEMAND_STfmt_fields, 19445 /* bits */ 5, 19446 /* flags */ 0, 19447 }, 19448 #endif /* chips */ 19449 19450 #if defined(BCM_56560_A0) 19451 { /* SOC_FORMAT_INT_ES_TO_DEQ_PORT_DEMAND_ST_BCM56560_A0fmt */ 19452 /* format ES_TO_DEQ_PORT_DEMAND_STfmt */ 19453 /* nFields */ 2, 19454 /* *fields */ soc_ES_TO_DEQ_PORT_DEMAND_ST_BCM56560_A0fmt_fields, 19455 /* bits */ 5, 19456 /* flags */ 0, 19457 }, 19458 #endif /* chips */ 19459 19460 #if defined(BCM_56560_B0) 19461 { /* SOC_FORMAT_INT_ES_TO_DEQ_PORT_DEMAND_ST_BCM56560_B0fmt */ 19462 /* format ES_TO_DEQ_PORT_DEMAND_STfmt */ 19463 /* nFields */ 2, 19464 /* *fields */ soc_ES_TO_DEQ_PORT_DEMAND_ST_BCM56560_A0fmt_fields, 19465 /* bits */ 5, 19466 /* flags */ 0, 19467 }, 19468 #endif /* chips */ 19469 19470 #if defined(BCM_56670_A0) 19471 { /* SOC_FORMAT_INT_ES_TO_DEQ_PORT_DEMAND_ST_BCM56670_A0fmt */ 19472 /* format ES_TO_DEQ_PORT_DEMAND_STfmt */ 19473 /* nFields */ 2, 19474 /* *fields */ soc_ES_TO_DEQ_PORT_DEMAND_ST_BCM56560_A0fmt_fields, 19475 /* bits */ 5, 19476 /* flags */ 0, 19477 }, 19478 #endif /* chips */ 19479 19480 #if defined(BCM_56670_B0) 19481 { /* SOC_FORMAT_INT_ES_TO_DEQ_PORT_DEMAND_ST_BCM56670_B0fmt */ 19482 /* format ES_TO_DEQ_PORT_DEMAND_STfmt */ 19483 /* nFields */ 2, 19484 /* *fields */ soc_ES_TO_DEQ_PORT_DEMAND_ST_BCM56560_A0fmt_fields, 19485 /* bits */ 5, 19486 /* flags */ 0, 19487 }, 19488 #endif /* chips */ 19489 19490 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 19491 defined(BCM_56870_A0) 19492 { /* SOC_FORMAT_INT_ETAG_COMPOSITESfmt */ 19493 /* format ETAG_COMPOSITESfmt */ 19494 /* nFields */ 5, 19495 /* *fields */ soc_ETAG_COMPOSITESfmt_fields, 19496 /* bits */ 59, 19497 /* flags */ 0, 19498 }, 19499 #endif /* chips */ 19500 19501 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \ 19502 defined(BCM_56450_A0) || defined(BCM_56450_B0) || \ 19503 defined(BCM_56450_B1) || defined(BCM_56640_A0) || \ 19504 defined(BCM_56850_A0) || defined(BCM_56860_A0) 19505 { /* SOC_FORMAT_INT_ETAG_HDRfmt */ 19506 /* format ETAG_HDRfmt */ 19507 /* nFields */ 5, 19508 /* *fields */ soc_ETAG_HDRfmt_fields, 19509 /* bits */ 32, 19510 /* flags */ 0, 19511 }, 19512 #endif /* chips */ 19513 19514 #if defined(BCM_53400_A0) 19515 { /* SOC_FORMAT_INT_ETAG_HDR_BCM53400_A0fmt */ 19516 /* format ETAG_HDRfmt */ 19517 /* nFields */ 5, 19518 /* *fields */ soc_ETAG_HDR_BCM53400_A0fmt_fields, 19519 /* bits */ 32, 19520 /* flags */ 0, 19521 }, 19522 #endif /* chips */ 19523 19524 #if defined(BCM_53540_A0) 19525 { /* SOC_FORMAT_INT_ETAG_HDR_BCM53540_A0fmt */ 19526 /* format ETAG_HDRfmt */ 19527 /* nFields */ 5, 19528 /* *fields */ soc_ETAG_HDR_BCM53400_A0fmt_fields, 19529 /* bits */ 32, 19530 /* flags */ 0, 19531 }, 19532 #endif /* chips */ 19533 19534 #if defined(BCM_53570_A0) 19535 { /* SOC_FORMAT_INT_ETAG_HDR_BCM53570_A0fmt */ 19536 /* format ETAG_HDRfmt */ 19537 /* nFields */ 5, 19538 /* *fields */ soc_ETAG_HDR_BCM53400_A0fmt_fields, 19539 /* bits */ 32, 19540 /* flags */ 0, 19541 }, 19542 #endif /* chips */ 19543 19544 #if defined(BCM_53570_B0) 19545 { /* SOC_FORMAT_INT_ETAG_HDR_BCM53570_B0fmt */ 19546 /* format ETAG_HDRfmt */ 19547 /* nFields */ 5, 19548 /* *fields */ soc_ETAG_HDR_BCM53400_A0fmt_fields, 19549 /* bits */ 32, 19550 /* flags */ 0, 19551 }, 19552 #endif /* chips */ 19553 19554 #if defined(BCM_56160_A0) 19555 { /* SOC_FORMAT_INT_ETAG_HDR_BCM56160_A0fmt */ 19556 /* format ETAG_HDRfmt */ 19557 /* nFields */ 5, 19558 /* *fields */ soc_ETAG_HDR_BCM53400_A0fmt_fields, 19559 /* bits */ 32, 19560 /* flags */ 0, 19561 }, 19562 #endif /* chips */ 19563 19564 #if defined(BCM_56260_A0) 19565 { /* SOC_FORMAT_INT_ETAG_HDR_BCM56260_A0fmt */ 19566 /* format ETAG_HDRfmt */ 19567 /* nFields */ 5, 19568 /* *fields */ soc_ETAG_HDR_BCM53400_A0fmt_fields, 19569 /* bits */ 32, 19570 /* flags */ 0, 19571 }, 19572 #endif /* chips */ 19573 19574 #if defined(BCM_56260_B0) 19575 { /* SOC_FORMAT_INT_ETAG_HDR_BCM56260_B0fmt */ 19576 /* format ETAG_HDRfmt */ 19577 /* nFields */ 5, 19578 /* *fields */ soc_ETAG_HDR_BCM53400_A0fmt_fields, 19579 /* bits */ 32, 19580 /* flags */ 0, 19581 }, 19582 #endif /* chips */ 19583 19584 #if defined(BCM_56270_A0) 19585 { /* SOC_FORMAT_INT_ETAG_HDR_BCM56270_A0fmt */ 19586 /* format ETAG_HDRfmt */ 19587 /* nFields */ 5, 19588 /* *fields */ soc_ETAG_HDR_BCM53400_A0fmt_fields, 19589 /* bits */ 32, 19590 /* flags */ 0, 19591 }, 19592 #endif /* chips */ 19593 19594 #if defined(BCM_56370_A0) 19595 { /* SOC_FORMAT_INT_ETAG_HDR_BCM56370_A0fmt */ 19596 /* format ETAG_HDRfmt */ 19597 /* nFields */ 5, 19598 /* *fields */ soc_ETAG_HDR_BCM53400_A0fmt_fields, 19599 /* bits */ 32, 19600 /* flags */ 0, 19601 }, 19602 #endif /* chips */ 19603 19604 #if defined(BCM_56560_A0) 19605 { /* SOC_FORMAT_INT_ETAG_HDR_BCM56560_A0fmt */ 19606 /* format ETAG_HDRfmt */ 19607 /* nFields */ 5, 19608 /* *fields */ soc_ETAG_HDR_BCM53400_A0fmt_fields, 19609 /* bits */ 32, 19610 /* flags */ 0, 19611 }, 19612 #endif /* chips */ 19613 19614 #if defined(BCM_56560_B0) 19615 { /* SOC_FORMAT_INT_ETAG_HDR_BCM56560_B0fmt */ 19616 /* format ETAG_HDRfmt */ 19617 /* nFields */ 5, 19618 /* *fields */ soc_ETAG_HDR_BCM53400_A0fmt_fields, 19619 /* bits */ 32, 19620 /* flags */ 0, 19621 }, 19622 #endif /* chips */ 19623 19624 #if defined(BCM_56670_A0) 19625 { /* SOC_FORMAT_INT_ETAG_HDR_BCM56670_A0fmt */ 19626 /* format ETAG_HDRfmt */ 19627 /* nFields */ 5, 19628 /* *fields */ soc_ETAG_HDR_BCM53400_A0fmt_fields, 19629 /* bits */ 32, 19630 /* flags */ 0, 19631 }, 19632 #endif /* chips */ 19633 19634 #if defined(BCM_56670_B0) 19635 { /* SOC_FORMAT_INT_ETAG_HDR_BCM56670_B0fmt */ 19636 /* format ETAG_HDRfmt */ 19637 /* nFields */ 5, 19638 /* *fields */ soc_ETAG_HDR_BCM53400_A0fmt_fields, 19639 /* bits */ 32, 19640 /* flags */ 0, 19641 }, 19642 #endif /* chips */ 19643 19644 #if defined(BCM_56770_A0) 19645 { /* SOC_FORMAT_INT_ETAG_HDR_BCM56770_A0fmt */ 19646 /* format ETAG_HDRfmt */ 19647 /* nFields */ 5, 19648 /* *fields */ soc_ETAG_HDR_BCM53400_A0fmt_fields, 19649 /* bits */ 32, 19650 /* flags */ 0, 19651 }, 19652 #endif /* chips */ 19653 19654 #if defined(BCM_56870_A0) 19655 { /* SOC_FORMAT_INT_ETAG_HDR_BCM56870_A0fmt */ 19656 /* format ETAG_HDRfmt */ 19657 /* nFields */ 5, 19658 /* *fields */ soc_ETAG_HDR_BCM53400_A0fmt_fields, 19659 /* bits */ 32, 19660 /* flags */ 0, 19661 }, 19662 #endif /* chips */ 19663 19664 #if defined(BCM_56960_A0) 19665 { /* SOC_FORMAT_INT_ETAG_HDR_BCM56960_A0fmt */ 19666 /* format ETAG_HDRfmt */ 19667 /* nFields */ 5, 19668 /* *fields */ soc_ETAG_HDR_BCM53400_A0fmt_fields, 19669 /* bits */ 32, 19670 /* flags */ 0, 19671 }, 19672 #endif /* chips */ 19673 19674 #if defined(BCM_56965_A0) 19675 { /* SOC_FORMAT_INT_ETAG_HDR_BCM56965_A0fmt */ 19676 /* format ETAG_HDRfmt */ 19677 /* nFields */ 5, 19678 /* *fields */ soc_ETAG_HDR_BCM53400_A0fmt_fields, 19679 /* bits */ 32, 19680 /* flags */ 0, 19681 }, 19682 #endif /* chips */ 19683 19684 #if defined(BCM_56970_A0) 19685 { /* SOC_FORMAT_INT_ETAG_HDR_BCM56970_A0fmt */ 19686 /* format ETAG_HDRfmt */ 19687 /* nFields */ 5, 19688 /* *fields */ soc_ETAG_HDR_BCM53400_A0fmt_fields, 19689 /* bits */ 32, 19690 /* flags */ 0, 19691 }, 19692 #endif /* chips */ 19693 19694 #if defined(BCM_56980_A0) 19695 { /* SOC_FORMAT_INT_ETAG_HDR_BCM56980_A0fmt */ 19696 /* format ETAG_HDRfmt */ 19697 /* nFields */ 5, 19698 /* *fields */ soc_ETAG_HDR_BCM53400_A0fmt_fields, 19699 /* bits */ 32, 19700 /* flags */ 0, 19701 }, 19702 #endif /* chips */ 19703 19704 #if defined(BCM_56980_B0) 19705 { /* SOC_FORMAT_INT_ETAG_HDR_BCM56980_B0fmt */ 19706 /* format ETAG_HDRfmt */ 19707 /* nFields */ 5, 19708 /* *fields */ soc_ETAG_HDR_BCM53400_A0fmt_fields, 19709 /* bits */ 32, 19710 /* flags */ 0, 19711 }, 19712 #endif /* chips */ 19713 19714 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \ 19715 defined(BCM_56450_A0) || defined(BCM_56450_B0) || \ 19716 defined(BCM_56450_B1) || defined(BCM_56640_A0) || \ 19717 defined(BCM_56850_A0) || defined(BCM_56860_A0) 19718 { /* SOC_FORMAT_INT_ETHERTYPEfmt */ 19719 /* format ETHERTYPEfmt */ 19720 /* nFields */ 1, 19721 /* *fields */ soc_ETHERTYPEfmt_fields, 19722 /* bits */ 16, 19723 /* flags */ 0, 19724 }, 19725 #endif /* chips */ 19726 19727 #if defined(BCM_53400_A0) 19728 { /* SOC_FORMAT_INT_ETHERTYPE_BCM53400_A0fmt */ 19729 /* format ETHERTYPEfmt */ 19730 /* nFields */ 1, 19731 /* *fields */ soc_ETHERTYPE_BCM53400_A0fmt_fields, 19732 /* bits */ 16, 19733 /* flags */ 0, 19734 }, 19735 #endif /* chips */ 19736 19737 #if defined(BCM_53540_A0) 19738 { /* SOC_FORMAT_INT_ETHERTYPE_BCM53540_A0fmt */ 19739 /* format ETHERTYPEfmt */ 19740 /* nFields */ 1, 19741 /* *fields */ soc_ETHERTYPE_BCM53400_A0fmt_fields, 19742 /* bits */ 16, 19743 /* flags */ 0, 19744 }, 19745 #endif /* chips */ 19746 19747 #if defined(BCM_53570_A0) 19748 { /* SOC_FORMAT_INT_ETHERTYPE_BCM53570_A0fmt */ 19749 /* format ETHERTYPEfmt */ 19750 /* nFields */ 1, 19751 /* *fields */ soc_ETHERTYPE_BCM53400_A0fmt_fields, 19752 /* bits */ 16, 19753 /* flags */ 0, 19754 }, 19755 #endif /* chips */ 19756 19757 #if defined(BCM_53570_B0) 19758 { /* SOC_FORMAT_INT_ETHERTYPE_BCM53570_B0fmt */ 19759 /* format ETHERTYPEfmt */ 19760 /* nFields */ 1, 19761 /* *fields */ soc_ETHERTYPE_BCM53400_A0fmt_fields, 19762 /* bits */ 16, 19763 /* flags */ 0, 19764 }, 19765 #endif /* chips */ 19766 19767 #if defined(BCM_56160_A0) 19768 { /* SOC_FORMAT_INT_ETHERTYPE_BCM56160_A0fmt */ 19769 /* format ETHERTYPEfmt */ 19770 /* nFields */ 1, 19771 /* *fields */ soc_ETHERTYPE_BCM53400_A0fmt_fields, 19772 /* bits */ 16, 19773 /* flags */ 0, 19774 }, 19775 #endif /* chips */ 19776 19777 #if defined(BCM_56260_A0) 19778 { /* SOC_FORMAT_INT_ETHERTYPE_BCM56260_A0fmt */ 19779 /* format ETHERTYPEfmt */ 19780 /* nFields */ 1, 19781 /* *fields */ soc_ETHERTYPE_BCM53400_A0fmt_fields, 19782 /* bits */ 16, 19783 /* flags */ 0, 19784 }, 19785 #endif /* chips */ 19786 19787 #if defined(BCM_56260_B0) 19788 { /* SOC_FORMAT_INT_ETHERTYPE_BCM56260_B0fmt */ 19789 /* format ETHERTYPEfmt */ 19790 /* nFields */ 1, 19791 /* *fields */ soc_ETHERTYPE_BCM53400_A0fmt_fields, 19792 /* bits */ 16, 19793 /* flags */ 0, 19794 }, 19795 #endif /* chips */ 19796 19797 #if defined(BCM_56270_A0) 19798 { /* SOC_FORMAT_INT_ETHERTYPE_BCM56270_A0fmt */ 19799 /* format ETHERTYPEfmt */ 19800 /* nFields */ 1, 19801 /* *fields */ soc_ETHERTYPE_BCM53400_A0fmt_fields, 19802 /* bits */ 16, 19803 /* flags */ 0, 19804 }, 19805 #endif /* chips */ 19806 19807 #if defined(BCM_56370_A0) 19808 { /* SOC_FORMAT_INT_ETHERTYPE_BCM56370_A0fmt */ 19809 /* format ETHERTYPEfmt */ 19810 /* nFields */ 1, 19811 /* *fields */ soc_ETHERTYPE_BCM53400_A0fmt_fields, 19812 /* bits */ 16, 19813 /* flags */ 0, 19814 }, 19815 #endif /* chips */ 19816 19817 #if defined(BCM_56560_A0) 19818 { /* SOC_FORMAT_INT_ETHERTYPE_BCM56560_A0fmt */ 19819 /* format ETHERTYPEfmt */ 19820 /* nFields */ 1, 19821 /* *fields */ soc_ETHERTYPE_BCM53400_A0fmt_fields, 19822 /* bits */ 16, 19823 /* flags */ 0, 19824 }, 19825 #endif /* chips */ 19826 19827 #if defined(BCM_56560_B0) 19828 { /* SOC_FORMAT_INT_ETHERTYPE_BCM56560_B0fmt */ 19829 /* format ETHERTYPEfmt */ 19830 /* nFields */ 1, 19831 /* *fields */ soc_ETHERTYPE_BCM53400_A0fmt_fields, 19832 /* bits */ 16, 19833 /* flags */ 0, 19834 }, 19835 #endif /* chips */ 19836 19837 #if defined(BCM_56670_A0) 19838 { /* SOC_FORMAT_INT_ETHERTYPE_BCM56670_A0fmt */ 19839 /* format ETHERTYPEfmt */ 19840 /* nFields */ 1, 19841 /* *fields */ soc_ETHERTYPE_BCM53400_A0fmt_fields, 19842 /* bits */ 16, 19843 /* flags */ 0, 19844 }, 19845 #endif /* chips */ 19846 19847 #if defined(BCM_56670_B0) 19848 { /* SOC_FORMAT_INT_ETHERTYPE_BCM56670_B0fmt */ 19849 /* format ETHERTYPEfmt */ 19850 /* nFields */ 1, 19851 /* *fields */ soc_ETHERTYPE_BCM53400_A0fmt_fields, 19852 /* bits */ 16, 19853 /* flags */ 0, 19854 }, 19855 #endif /* chips */ 19856 19857 #if defined(BCM_56770_A0) 19858 { /* SOC_FORMAT_INT_ETHERTYPE_BCM56770_A0fmt */ 19859 /* format ETHERTYPEfmt */ 19860 /* nFields */ 1, 19861 /* *fields */ soc_ETHERTYPE_BCM53400_A0fmt_fields, 19862 /* bits */ 16, 19863 /* flags */ 0, 19864 }, 19865 #endif /* chips */ 19866 19867 #if defined(BCM_56870_A0) 19868 { /* SOC_FORMAT_INT_ETHERTYPE_BCM56870_A0fmt */ 19869 /* format ETHERTYPEfmt */ 19870 /* nFields */ 1, 19871 /* *fields */ soc_ETHERTYPE_BCM53400_A0fmt_fields, 19872 /* bits */ 16, 19873 /* flags */ 0, 19874 }, 19875 #endif /* chips */ 19876 19877 #if defined(BCM_56960_A0) 19878 { /* SOC_FORMAT_INT_ETHERTYPE_BCM56960_A0fmt */ 19879 /* format ETHERTYPEfmt */ 19880 /* nFields */ 1, 19881 /* *fields */ soc_ETHERTYPE_BCM53400_A0fmt_fields, 19882 /* bits */ 16, 19883 /* flags */ 0, 19884 }, 19885 #endif /* chips */ 19886 19887 #if defined(BCM_56965_A0) 19888 { /* SOC_FORMAT_INT_ETHERTYPE_BCM56965_A0fmt */ 19889 /* format ETHERTYPEfmt */ 19890 /* nFields */ 1, 19891 /* *fields */ soc_ETHERTYPE_BCM53400_A0fmt_fields, 19892 /* bits */ 16, 19893 /* flags */ 0, 19894 }, 19895 #endif /* chips */ 19896 19897 #if defined(BCM_56970_A0) 19898 { /* SOC_FORMAT_INT_ETHERTYPE_BCM56970_A0fmt */ 19899 /* format ETHERTYPEfmt */ 19900 /* nFields */ 1, 19901 /* *fields */ soc_ETHERTYPE_BCM53400_A0fmt_fields, 19902 /* bits */ 16, 19903 /* flags */ 0, 19904 }, 19905 #endif /* chips */ 19906 19907 #if defined(BCM_56980_A0) 19908 { /* SOC_FORMAT_INT_ETHERTYPE_BCM56980_A0fmt */ 19909 /* format ETHERTYPEfmt */ 19910 /* nFields */ 1, 19911 /* *fields */ soc_ETHERTYPE_BCM53400_A0fmt_fields, 19912 /* bits */ 16, 19913 /* flags */ 0, 19914 }, 19915 #endif /* chips */ 19916 19917 #if defined(BCM_56980_B0) 19918 { /* SOC_FORMAT_INT_ETHERTYPE_BCM56980_B0fmt */ 19919 /* format ETHERTYPEfmt */ 19920 /* nFields */ 1, 19921 /* *fields */ soc_ETHERTYPE_BCM53400_A0fmt_fields, 19922 /* bits */ 16, 19923 /* flags */ 0, 19924 }, 19925 #endif /* chips */ 19926 19927 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \ 19928 defined(BCM_56450_A0) || defined(BCM_56450_B0) || \ 19929 defined(BCM_56450_B1) || defined(BCM_56640_A0) || \ 19930 defined(BCM_56850_A0) || defined(BCM_56860_A0) 19931 { /* SOC_FORMAT_INT_ETH_II_DOUBLE_TAGGED_HDRfmt */ 19932 /* format ETH_II_DOUBLE_TAGGED_HDRfmt */ 19933 /* nFields */ 11, 19934 /* *fields */ soc_ETH_II_DOUBLE_TAGGED_HDRfmt_fields, 19935 /* bits */ 176, 19936 /* flags */ 0, 19937 }, 19938 #endif /* chips */ 19939 19940 #if defined(BCM_53400_A0) 19941 { /* SOC_FORMAT_INT_ETH_II_DOUBLE_TAGGED_HDR_BCM53400_A0fmt */ 19942 /* format ETH_II_DOUBLE_TAGGED_HDRfmt */ 19943 /* nFields */ 11, 19944 /* *fields */ soc_ETH_II_DOUBLE_TAGGED_HDR_BCM53400_A0fmt_fields, 19945 /* bits */ 176, 19946 /* flags */ 0, 19947 }, 19948 #endif /* chips */ 19949 19950 #if defined(BCM_53540_A0) 19951 { /* SOC_FORMAT_INT_ETH_II_DOUBLE_TAGGED_HDR_BCM53540_A0fmt */ 19952 /* format ETH_II_DOUBLE_TAGGED_HDRfmt */ 19953 /* nFields */ 11, 19954 /* *fields */ soc_ETH_II_DOUBLE_TAGGED_HDR_BCM53400_A0fmt_fields, 19955 /* bits */ 176, 19956 /* flags */ 0, 19957 }, 19958 #endif /* chips */ 19959 19960 #if defined(BCM_53570_A0) 19961 { /* SOC_FORMAT_INT_ETH_II_DOUBLE_TAGGED_HDR_BCM53570_A0fmt */ 19962 /* format ETH_II_DOUBLE_TAGGED_HDRfmt */ 19963 /* nFields */ 11, 19964 /* *fields */ soc_ETH_II_DOUBLE_TAGGED_HDR_BCM53400_A0fmt_fields, 19965 /* bits */ 176, 19966 /* flags */ 0, 19967 }, 19968 #endif /* chips */ 19969 19970 #if defined(BCM_53570_B0) 19971 { /* SOC_FORMAT_INT_ETH_II_DOUBLE_TAGGED_HDR_BCM53570_B0fmt */ 19972 /* format ETH_II_DOUBLE_TAGGED_HDRfmt */ 19973 /* nFields */ 11, 19974 /* *fields */ soc_ETH_II_DOUBLE_TAGGED_HDR_BCM53400_A0fmt_fields, 19975 /* bits */ 176, 19976 /* flags */ 0, 19977 }, 19978 #endif /* chips */ 19979 19980 #if defined(BCM_56160_A0) 19981 { /* SOC_FORMAT_INT_ETH_II_DOUBLE_TAGGED_HDR_BCM56160_A0fmt */ 19982 /* format ETH_II_DOUBLE_TAGGED_HDRfmt */ 19983 /* nFields */ 11, 19984 /* *fields */ soc_ETH_II_DOUBLE_TAGGED_HDR_BCM53400_A0fmt_fields, 19985 /* bits */ 176, 19986 /* flags */ 0, 19987 }, 19988 #endif /* chips */ 19989 19990 #if defined(BCM_56260_A0) 19991 { /* SOC_FORMAT_INT_ETH_II_DOUBLE_TAGGED_HDR_BCM56260_A0fmt */ 19992 /* format ETH_II_DOUBLE_TAGGED_HDRfmt */ 19993 /* nFields */ 11, 19994 /* *fields */ soc_ETH_II_DOUBLE_TAGGED_HDR_BCM53400_A0fmt_fields, 19995 /* bits */ 176, 19996 /* flags */ 0, 19997 }, 19998 #endif /* chips */ 19999 20000 #if defined(BCM_56260_B0) 20001 { /* SOC_FORMAT_INT_ETH_II_DOUBLE_TAGGED_HDR_BCM56260_B0fmt */ 20002 /* format ETH_II_DOUBLE_TAGGED_HDRfmt */ 20003 /* nFields */ 11, 20004 /* *fields */ soc_ETH_II_DOUBLE_TAGGED_HDR_BCM53400_A0fmt_fields, 20005 /* bits */ 176, 20006 /* flags */ 0, 20007 }, 20008 #endif /* chips */ 20009 20010 #if defined(BCM_56270_A0) 20011 { /* SOC_FORMAT_INT_ETH_II_DOUBLE_TAGGED_HDR_BCM56270_A0fmt */ 20012 /* format ETH_II_DOUBLE_TAGGED_HDRfmt */ 20013 /* nFields */ 11, 20014 /* *fields */ soc_ETH_II_DOUBLE_TAGGED_HDR_BCM53400_A0fmt_fields, 20015 /* bits */ 176, 20016 /* flags */ 0, 20017 }, 20018 #endif /* chips */ 20019 20020 #if defined(BCM_56560_A0) 20021 { /* SOC_FORMAT_INT_ETH_II_DOUBLE_TAGGED_HDR_BCM56560_A0fmt */ 20022 /* format ETH_II_DOUBLE_TAGGED_HDRfmt */ 20023 /* nFields */ 11, 20024 /* *fields */ soc_ETH_II_DOUBLE_TAGGED_HDR_BCM53400_A0fmt_fields, 20025 /* bits */ 176, 20026 /* flags */ 0, 20027 }, 20028 #endif /* chips */ 20029 20030 #if defined(BCM_56560_B0) 20031 { /* SOC_FORMAT_INT_ETH_II_DOUBLE_TAGGED_HDR_BCM56560_B0fmt */ 20032 /* format ETH_II_DOUBLE_TAGGED_HDRfmt */ 20033 /* nFields */ 11, 20034 /* *fields */ soc_ETH_II_DOUBLE_TAGGED_HDR_BCM53400_A0fmt_fields, 20035 /* bits */ 176, 20036 /* flags */ 0, 20037 }, 20038 #endif /* chips */ 20039 20040 #if defined(BCM_56670_A0) 20041 { /* SOC_FORMAT_INT_ETH_II_DOUBLE_TAGGED_HDR_BCM56670_A0fmt */ 20042 /* format ETH_II_DOUBLE_TAGGED_HDRfmt */ 20043 /* nFields */ 11, 20044 /* *fields */ soc_ETH_II_DOUBLE_TAGGED_HDR_BCM53400_A0fmt_fields, 20045 /* bits */ 176, 20046 /* flags */ 0, 20047 }, 20048 #endif /* chips */ 20049 20050 #if defined(BCM_56670_B0) 20051 { /* SOC_FORMAT_INT_ETH_II_DOUBLE_TAGGED_HDR_BCM56670_B0fmt */ 20052 /* format ETH_II_DOUBLE_TAGGED_HDRfmt */ 20053 /* nFields */ 11, 20054 /* *fields */ soc_ETH_II_DOUBLE_TAGGED_HDR_BCM53400_A0fmt_fields, 20055 /* bits */ 176, 20056 /* flags */ 0, 20057 }, 20058 #endif /* chips */ 20059 20060 #if defined(BCM_56960_A0) 20061 { /* SOC_FORMAT_INT_ETH_II_DOUBLE_TAGGED_HDR_BCM56960_A0fmt */ 20062 /* format ETH_II_DOUBLE_TAGGED_HDRfmt */ 20063 /* nFields */ 11, 20064 /* *fields */ soc_ETH_II_DOUBLE_TAGGED_HDR_BCM53400_A0fmt_fields, 20065 /* bits */ 176, 20066 /* flags */ 0, 20067 }, 20068 #endif /* chips */ 20069 20070 #if defined(BCM_56965_A0) 20071 { /* SOC_FORMAT_INT_ETH_II_DOUBLE_TAGGED_HDR_BCM56965_A0fmt */ 20072 /* format ETH_II_DOUBLE_TAGGED_HDRfmt */ 20073 /* nFields */ 11, 20074 /* *fields */ soc_ETH_II_DOUBLE_TAGGED_HDR_BCM53400_A0fmt_fields, 20075 /* bits */ 176, 20076 /* flags */ 0, 20077 }, 20078 #endif /* chips */ 20079 20080 #if defined(BCM_56970_A0) 20081 { /* SOC_FORMAT_INT_ETH_II_DOUBLE_TAGGED_HDR_BCM56970_A0fmt */ 20082 /* format ETH_II_DOUBLE_TAGGED_HDRfmt */ 20083 /* nFields */ 11, 20084 /* *fields */ soc_ETH_II_DOUBLE_TAGGED_HDR_BCM53400_A0fmt_fields, 20085 /* bits */ 176, 20086 /* flags */ 0, 20087 }, 20088 #endif /* chips */ 20089 20090 #if defined(BCM_56980_A0) 20091 { /* SOC_FORMAT_INT_ETH_II_DOUBLE_TAGGED_HDR_BCM56980_A0fmt */ 20092 /* format ETH_II_DOUBLE_TAGGED_HDRfmt */ 20093 /* nFields */ 11, 20094 /* *fields */ soc_ETH_II_DOUBLE_TAGGED_HDR_BCM53400_A0fmt_fields, 20095 /* bits */ 176, 20096 /* flags */ 0, 20097 }, 20098 #endif /* chips */ 20099 20100 #if defined(BCM_56980_B0) 20101 { /* SOC_FORMAT_INT_ETH_II_DOUBLE_TAGGED_HDR_BCM56980_B0fmt */ 20102 /* format ETH_II_DOUBLE_TAGGED_HDRfmt */ 20103 /* nFields */ 11, 20104 /* *fields */ soc_ETH_II_DOUBLE_TAGGED_HDR_BCM53400_A0fmt_fields, 20105 /* bits */ 176, 20106 /* flags */ 0, 20107 }, 20108 #endif /* chips */ 20109 20110 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \ 20111 defined(BCM_56450_A0) || defined(BCM_56450_B0) || \ 20112 defined(BCM_56450_B1) || defined(BCM_56640_A0) || \ 20113 defined(BCM_56850_A0) || defined(BCM_56860_A0) 20114 { /* SOC_FORMAT_INT_ETH_II_SINGLE_TAGGED_HDRfmt */ 20115 /* format ETH_II_SINGLE_TAGGED_HDRfmt */ 20116 /* nFields */ 7, 20117 /* *fields */ soc_ETH_II_SINGLE_TAGGED_HDRfmt_fields, 20118 /* bits */ 144, 20119 /* flags */ 0, 20120 }, 20121 #endif /* chips */ 20122 20123 #if defined(BCM_53400_A0) 20124 { /* SOC_FORMAT_INT_ETH_II_SINGLE_TAGGED_HDR_BCM53400_A0fmt */ 20125 /* format ETH_II_SINGLE_TAGGED_HDRfmt */ 20126 /* nFields */ 7, 20127 /* *fields */ soc_ETH_II_SINGLE_TAGGED_HDR_BCM53400_A0fmt_fields, 20128 /* bits */ 144, 20129 /* flags */ 0, 20130 }, 20131 #endif /* chips */ 20132 20133 #if defined(BCM_53540_A0) 20134 { /* SOC_FORMAT_INT_ETH_II_SINGLE_TAGGED_HDR_BCM53540_A0fmt */ 20135 /* format ETH_II_SINGLE_TAGGED_HDRfmt */ 20136 /* nFields */ 7, 20137 /* *fields */ soc_ETH_II_SINGLE_TAGGED_HDR_BCM53400_A0fmt_fields, 20138 /* bits */ 144, 20139 /* flags */ 0, 20140 }, 20141 #endif /* chips */ 20142 20143 #if defined(BCM_53570_A0) 20144 { /* SOC_FORMAT_INT_ETH_II_SINGLE_TAGGED_HDR_BCM53570_A0fmt */ 20145 /* format ETH_II_SINGLE_TAGGED_HDRfmt */ 20146 /* nFields */ 7, 20147 /* *fields */ soc_ETH_II_SINGLE_TAGGED_HDR_BCM53400_A0fmt_fields, 20148 /* bits */ 144, 20149 /* flags */ 0, 20150 }, 20151 #endif /* chips */ 20152 20153 #if defined(BCM_53570_B0) 20154 { /* SOC_FORMAT_INT_ETH_II_SINGLE_TAGGED_HDR_BCM53570_B0fmt */ 20155 /* format ETH_II_SINGLE_TAGGED_HDRfmt */ 20156 /* nFields */ 7, 20157 /* *fields */ soc_ETH_II_SINGLE_TAGGED_HDR_BCM53400_A0fmt_fields, 20158 /* bits */ 144, 20159 /* flags */ 0, 20160 }, 20161 #endif /* chips */ 20162 20163 #if defined(BCM_56160_A0) 20164 { /* SOC_FORMAT_INT_ETH_II_SINGLE_TAGGED_HDR_BCM56160_A0fmt */ 20165 /* format ETH_II_SINGLE_TAGGED_HDRfmt */ 20166 /* nFields */ 7, 20167 /* *fields */ soc_ETH_II_SINGLE_TAGGED_HDR_BCM53400_A0fmt_fields, 20168 /* bits */ 144, 20169 /* flags */ 0, 20170 }, 20171 #endif /* chips */ 20172 20173 #if defined(BCM_56260_A0) 20174 { /* SOC_FORMAT_INT_ETH_II_SINGLE_TAGGED_HDR_BCM56260_A0fmt */ 20175 /* format ETH_II_SINGLE_TAGGED_HDRfmt */ 20176 /* nFields */ 7, 20177 /* *fields */ soc_ETH_II_SINGLE_TAGGED_HDR_BCM53400_A0fmt_fields, 20178 /* bits */ 144, 20179 /* flags */ 0, 20180 }, 20181 #endif /* chips */ 20182 20183 #if defined(BCM_56260_B0) 20184 { /* SOC_FORMAT_INT_ETH_II_SINGLE_TAGGED_HDR_BCM56260_B0fmt */ 20185 /* format ETH_II_SINGLE_TAGGED_HDRfmt */ 20186 /* nFields */ 7, 20187 /* *fields */ soc_ETH_II_SINGLE_TAGGED_HDR_BCM53400_A0fmt_fields, 20188 /* bits */ 144, 20189 /* flags */ 0, 20190 }, 20191 #endif /* chips */ 20192 20193 #if defined(BCM_56270_A0) 20194 { /* SOC_FORMAT_INT_ETH_II_SINGLE_TAGGED_HDR_BCM56270_A0fmt */ 20195 /* format ETH_II_SINGLE_TAGGED_HDRfmt */ 20196 /* nFields */ 7, 20197 /* *fields */ soc_ETH_II_SINGLE_TAGGED_HDR_BCM53400_A0fmt_fields, 20198 /* bits */ 144, 20199 /* flags */ 0, 20200 }, 20201 #endif /* chips */ 20202 20203 #if defined(BCM_56560_A0) 20204 { /* SOC_FORMAT_INT_ETH_II_SINGLE_TAGGED_HDR_BCM56560_A0fmt */ 20205 /* format ETH_II_SINGLE_TAGGED_HDRfmt */ 20206 /* nFields */ 7, 20207 /* *fields */ soc_ETH_II_SINGLE_TAGGED_HDR_BCM53400_A0fmt_fields, 20208 /* bits */ 144, 20209 /* flags */ 0, 20210 }, 20211 #endif /* chips */ 20212 20213 #if defined(BCM_56560_B0) 20214 { /* SOC_FORMAT_INT_ETH_II_SINGLE_TAGGED_HDR_BCM56560_B0fmt */ 20215 /* format ETH_II_SINGLE_TAGGED_HDRfmt */ 20216 /* nFields */ 7, 20217 /* *fields */ soc_ETH_II_SINGLE_TAGGED_HDR_BCM53400_A0fmt_fields, 20218 /* bits */ 144, 20219 /* flags */ 0, 20220 }, 20221 #endif /* chips */ 20222 20223 #if defined(BCM_56670_A0) 20224 { /* SOC_FORMAT_INT_ETH_II_SINGLE_TAGGED_HDR_BCM56670_A0fmt */ 20225 /* format ETH_II_SINGLE_TAGGED_HDRfmt */ 20226 /* nFields */ 7, 20227 /* *fields */ soc_ETH_II_SINGLE_TAGGED_HDR_BCM53400_A0fmt_fields, 20228 /* bits */ 144, 20229 /* flags */ 0, 20230 }, 20231 #endif /* chips */ 20232 20233 #if defined(BCM_56670_B0) 20234 { /* SOC_FORMAT_INT_ETH_II_SINGLE_TAGGED_HDR_BCM56670_B0fmt */ 20235 /* format ETH_II_SINGLE_TAGGED_HDRfmt */ 20236 /* nFields */ 7, 20237 /* *fields */ soc_ETH_II_SINGLE_TAGGED_HDR_BCM53400_A0fmt_fields, 20238 /* bits */ 144, 20239 /* flags */ 0, 20240 }, 20241 #endif /* chips */ 20242 20243 #if defined(BCM_56960_A0) 20244 { /* SOC_FORMAT_INT_ETH_II_SINGLE_TAGGED_HDR_BCM56960_A0fmt */ 20245 /* format ETH_II_SINGLE_TAGGED_HDRfmt */ 20246 /* nFields */ 7, 20247 /* *fields */ soc_ETH_II_SINGLE_TAGGED_HDR_BCM53400_A0fmt_fields, 20248 /* bits */ 144, 20249 /* flags */ 0, 20250 }, 20251 #endif /* chips */ 20252 20253 #if defined(BCM_56965_A0) 20254 { /* SOC_FORMAT_INT_ETH_II_SINGLE_TAGGED_HDR_BCM56965_A0fmt */ 20255 /* format ETH_II_SINGLE_TAGGED_HDRfmt */ 20256 /* nFields */ 7, 20257 /* *fields */ soc_ETH_II_SINGLE_TAGGED_HDR_BCM53400_A0fmt_fields, 20258 /* bits */ 144, 20259 /* flags */ 0, 20260 }, 20261 #endif /* chips */ 20262 20263 #if defined(BCM_56970_A0) 20264 { /* SOC_FORMAT_INT_ETH_II_SINGLE_TAGGED_HDR_BCM56970_A0fmt */ 20265 /* format ETH_II_SINGLE_TAGGED_HDRfmt */ 20266 /* nFields */ 7, 20267 /* *fields */ soc_ETH_II_SINGLE_TAGGED_HDR_BCM53400_A0fmt_fields, 20268 /* bits */ 144, 20269 /* flags */ 0, 20270 }, 20271 #endif /* chips */ 20272 20273 #if defined(BCM_56980_A0) 20274 { /* SOC_FORMAT_INT_ETH_II_SINGLE_TAGGED_HDR_BCM56980_A0fmt */ 20275 /* format ETH_II_SINGLE_TAGGED_HDRfmt */ 20276 /* nFields */ 7, 20277 /* *fields */ soc_ETH_II_SINGLE_TAGGED_HDR_BCM53400_A0fmt_fields, 20278 /* bits */ 144, 20279 /* flags */ 0, 20280 }, 20281 #endif /* chips */ 20282 20283 #if defined(BCM_56980_B0) 20284 { /* SOC_FORMAT_INT_ETH_II_SINGLE_TAGGED_HDR_BCM56980_B0fmt */ 20285 /* format ETH_II_SINGLE_TAGGED_HDRfmt */ 20286 /* nFields */ 7, 20287 /* *fields */ soc_ETH_II_SINGLE_TAGGED_HDR_BCM53400_A0fmt_fields, 20288 /* bits */ 144, 20289 /* flags */ 0, 20290 }, 20291 #endif /* chips */ 20292 20293 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \ 20294 defined(BCM_56450_A0) || defined(BCM_56450_B0) || \ 20295 defined(BCM_56450_B1) || defined(BCM_56640_A0) || \ 20296 defined(BCM_56850_A0) || defined(BCM_56860_A0) 20297 { /* SOC_FORMAT_INT_ETH_II_UNTAGGED_HDRfmt */ 20298 /* format ETH_II_UNTAGGED_HDRfmt */ 20299 /* nFields */ 3, 20300 /* *fields */ soc_ETH_II_UNTAGGED_HDRfmt_fields, 20301 /* bits */ 112, 20302 /* flags */ 0, 20303 }, 20304 #endif /* chips */ 20305 20306 #if defined(BCM_53400_A0) 20307 { /* SOC_FORMAT_INT_ETH_II_UNTAGGED_HDR_BCM53400_A0fmt */ 20308 /* format ETH_II_UNTAGGED_HDRfmt */ 20309 /* nFields */ 3, 20310 /* *fields */ soc_ETH_II_UNTAGGED_HDR_BCM53400_A0fmt_fields, 20311 /* bits */ 112, 20312 /* flags */ 0, 20313 }, 20314 #endif /* chips */ 20315 20316 #if defined(BCM_53540_A0) 20317 { /* SOC_FORMAT_INT_ETH_II_UNTAGGED_HDR_BCM53540_A0fmt */ 20318 /* format ETH_II_UNTAGGED_HDRfmt */ 20319 /* nFields */ 3, 20320 /* *fields */ soc_ETH_II_UNTAGGED_HDR_BCM53400_A0fmt_fields, 20321 /* bits */ 112, 20322 /* flags */ 0, 20323 }, 20324 #endif /* chips */ 20325 20326 #if defined(BCM_53570_A0) 20327 { /* SOC_FORMAT_INT_ETH_II_UNTAGGED_HDR_BCM53570_A0fmt */ 20328 /* format ETH_II_UNTAGGED_HDRfmt */ 20329 /* nFields */ 3, 20330 /* *fields */ soc_ETH_II_UNTAGGED_HDR_BCM53400_A0fmt_fields, 20331 /* bits */ 112, 20332 /* flags */ 0, 20333 }, 20334 #endif /* chips */ 20335 20336 #if defined(BCM_53570_B0) 20337 { /* SOC_FORMAT_INT_ETH_II_UNTAGGED_HDR_BCM53570_B0fmt */ 20338 /* format ETH_II_UNTAGGED_HDRfmt */ 20339 /* nFields */ 3, 20340 /* *fields */ soc_ETH_II_UNTAGGED_HDR_BCM53400_A0fmt_fields, 20341 /* bits */ 112, 20342 /* flags */ 0, 20343 }, 20344 #endif /* chips */ 20345 20346 #if defined(BCM_56160_A0) 20347 { /* SOC_FORMAT_INT_ETH_II_UNTAGGED_HDR_BCM56160_A0fmt */ 20348 /* format ETH_II_UNTAGGED_HDRfmt */ 20349 /* nFields */ 3, 20350 /* *fields */ soc_ETH_II_UNTAGGED_HDR_BCM53400_A0fmt_fields, 20351 /* bits */ 112, 20352 /* flags */ 0, 20353 }, 20354 #endif /* chips */ 20355 20356 #if defined(BCM_56260_A0) 20357 { /* SOC_FORMAT_INT_ETH_II_UNTAGGED_HDR_BCM56260_A0fmt */ 20358 /* format ETH_II_UNTAGGED_HDRfmt */ 20359 /* nFields */ 3, 20360 /* *fields */ soc_ETH_II_UNTAGGED_HDR_BCM53400_A0fmt_fields, 20361 /* bits */ 112, 20362 /* flags */ 0, 20363 }, 20364 #endif /* chips */ 20365 20366 #if defined(BCM_56260_B0) 20367 { /* SOC_FORMAT_INT_ETH_II_UNTAGGED_HDR_BCM56260_B0fmt */ 20368 /* format ETH_II_UNTAGGED_HDRfmt */ 20369 /* nFields */ 3, 20370 /* *fields */ soc_ETH_II_UNTAGGED_HDR_BCM53400_A0fmt_fields, 20371 /* bits */ 112, 20372 /* flags */ 0, 20373 }, 20374 #endif /* chips */ 20375 20376 #if defined(BCM_56270_A0) 20377 { /* SOC_FORMAT_INT_ETH_II_UNTAGGED_HDR_BCM56270_A0fmt */ 20378 /* format ETH_II_UNTAGGED_HDRfmt */ 20379 /* nFields */ 3, 20380 /* *fields */ soc_ETH_II_UNTAGGED_HDR_BCM53400_A0fmt_fields, 20381 /* bits */ 112, 20382 /* flags */ 0, 20383 }, 20384 #endif /* chips */ 20385 20386 #if defined(BCM_56560_A0) 20387 { /* SOC_FORMAT_INT_ETH_II_UNTAGGED_HDR_BCM56560_A0fmt */ 20388 /* format ETH_II_UNTAGGED_HDRfmt */ 20389 /* nFields */ 3, 20390 /* *fields */ soc_ETH_II_UNTAGGED_HDR_BCM53400_A0fmt_fields, 20391 /* bits */ 112, 20392 /* flags */ 0, 20393 }, 20394 #endif /* chips */ 20395 20396 #if defined(BCM_56560_B0) 20397 { /* SOC_FORMAT_INT_ETH_II_UNTAGGED_HDR_BCM56560_B0fmt */ 20398 /* format ETH_II_UNTAGGED_HDRfmt */ 20399 /* nFields */ 3, 20400 /* *fields */ soc_ETH_II_UNTAGGED_HDR_BCM53400_A0fmt_fields, 20401 /* bits */ 112, 20402 /* flags */ 0, 20403 }, 20404 #endif /* chips */ 20405 20406 #if defined(BCM_56670_A0) 20407 { /* SOC_FORMAT_INT_ETH_II_UNTAGGED_HDR_BCM56670_A0fmt */ 20408 /* format ETH_II_UNTAGGED_HDRfmt */ 20409 /* nFields */ 3, 20410 /* *fields */ soc_ETH_II_UNTAGGED_HDR_BCM53400_A0fmt_fields, 20411 /* bits */ 112, 20412 /* flags */ 0, 20413 }, 20414 #endif /* chips */ 20415 20416 #if defined(BCM_56670_B0) 20417 { /* SOC_FORMAT_INT_ETH_II_UNTAGGED_HDR_BCM56670_B0fmt */ 20418 /* format ETH_II_UNTAGGED_HDRfmt */ 20419 /* nFields */ 3, 20420 /* *fields */ soc_ETH_II_UNTAGGED_HDR_BCM53400_A0fmt_fields, 20421 /* bits */ 112, 20422 /* flags */ 0, 20423 }, 20424 #endif /* chips */ 20425 20426 #if defined(BCM_56960_A0) 20427 { /* SOC_FORMAT_INT_ETH_II_UNTAGGED_HDR_BCM56960_A0fmt */ 20428 /* format ETH_II_UNTAGGED_HDRfmt */ 20429 /* nFields */ 3, 20430 /* *fields */ soc_ETH_II_UNTAGGED_HDR_BCM53400_A0fmt_fields, 20431 /* bits */ 112, 20432 /* flags */ 0, 20433 }, 20434 #endif /* chips */ 20435 20436 #if defined(BCM_56965_A0) 20437 { /* SOC_FORMAT_INT_ETH_II_UNTAGGED_HDR_BCM56965_A0fmt */ 20438 /* format ETH_II_UNTAGGED_HDRfmt */ 20439 /* nFields */ 3, 20440 /* *fields */ soc_ETH_II_UNTAGGED_HDR_BCM53400_A0fmt_fields, 20441 /* bits */ 112, 20442 /* flags */ 0, 20443 }, 20444 #endif /* chips */ 20445 20446 #if defined(BCM_56970_A0) 20447 { /* SOC_FORMAT_INT_ETH_II_UNTAGGED_HDR_BCM56970_A0fmt */ 20448 /* format ETH_II_UNTAGGED_HDRfmt */ 20449 /* nFields */ 3, 20450 /* *fields */ soc_ETH_II_UNTAGGED_HDR_BCM53400_A0fmt_fields, 20451 /* bits */ 112, 20452 /* flags */ 0, 20453 }, 20454 #endif /* chips */ 20455 20456 #if defined(BCM_56980_A0) 20457 { /* SOC_FORMAT_INT_ETH_II_UNTAGGED_HDR_BCM56980_A0fmt */ 20458 /* format ETH_II_UNTAGGED_HDRfmt */ 20459 /* nFields */ 3, 20460 /* *fields */ soc_ETH_II_UNTAGGED_HDR_BCM53400_A0fmt_fields, 20461 /* bits */ 112, 20462 /* flags */ 0, 20463 }, 20464 #endif /* chips */ 20465 20466 #if defined(BCM_56980_B0) 20467 { /* SOC_FORMAT_INT_ETH_II_UNTAGGED_HDR_BCM56980_B0fmt */ 20468 /* format ETH_II_UNTAGGED_HDRfmt */ 20469 /* nFields */ 3, 20470 /* *fields */ soc_ETH_II_UNTAGGED_HDR_BCM53400_A0fmt_fields, 20471 /* bits */ 112, 20472 /* flags */ 0, 20473 }, 20474 #endif /* chips */ 20475 20476 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 20477 { /* SOC_FORMAT_INT_ETRAP_FILTER_0_COV_DEFSfmt */ 20478 /* format ETRAP_FILTER_0_COV_DEFSfmt */ 20479 /* nFields */ 4, 20480 /* *fields */ soc_ETRAP_FILTER_0_COV_DEFSfmt_fields, 20481 /* bits */ 17, 20482 /* flags */ 0, 20483 }, 20484 #endif /* chips */ 20485 20486 #if defined(BCM_56980_A0) 20487 { /* SOC_FORMAT_INT_ETRAP_FILTER_1_COV_DEFSfmt */ 20488 /* format ETRAP_FILTER_1_COV_DEFSfmt */ 20489 /* nFields */ 4, 20490 /* *fields */ soc_ETRAP_FILTER_0_COV_DEFSfmt_fields, 20491 /* bits */ 17, 20492 /* flags */ 0, 20493 }, 20494 #endif /* chips */ 20495 20496 #if defined(BCM_56980_B0) 20497 { /* SOC_FORMAT_INT_ETRAP_FILTER_1_COV_DEFS_BCM56980_B0fmt */ 20498 /* format ETRAP_FILTER_1_COV_DEFSfmt */ 20499 /* nFields */ 4, 20500 /* *fields */ soc_ETRAP_FILTER_0_COV_DEFSfmt_fields, 20501 /* bits */ 17, 20502 /* flags */ 0, 20503 }, 20504 #endif /* chips */ 20505 20506 #if defined(BCM_56980_A0) 20507 { /* SOC_FORMAT_INT_ETRAP_FILTER_2_COV_DEFSfmt */ 20508 /* format ETRAP_FILTER_2_COV_DEFSfmt */ 20509 /* nFields */ 4, 20510 /* *fields */ soc_ETRAP_FILTER_0_COV_DEFSfmt_fields, 20511 /* bits */ 17, 20512 /* flags */ 0, 20513 }, 20514 #endif /* chips */ 20515 20516 #if defined(BCM_56980_B0) 20517 { /* SOC_FORMAT_INT_ETRAP_FILTER_2_COV_DEFS_BCM56980_B0fmt */ 20518 /* format ETRAP_FILTER_2_COV_DEFSfmt */ 20519 /* nFields */ 4, 20520 /* *fields */ soc_ETRAP_FILTER_0_COV_DEFSfmt_fields, 20521 /* bits */ 17, 20522 /* flags */ 0, 20523 }, 20524 #endif /* chips */ 20525 20526 #if defined(BCM_56980_A0) 20527 { /* SOC_FORMAT_INT_ETRAP_FILTER_3_COV_DEFSfmt */ 20528 /* format ETRAP_FILTER_3_COV_DEFSfmt */ 20529 /* nFields */ 4, 20530 /* *fields */ soc_ETRAP_FILTER_0_COV_DEFSfmt_fields, 20531 /* bits */ 17, 20532 /* flags */ 0, 20533 }, 20534 #endif /* chips */ 20535 20536 #if defined(BCM_56980_B0) 20537 { /* SOC_FORMAT_INT_ETRAP_FILTER_3_COV_DEFS_BCM56980_B0fmt */ 20538 /* format ETRAP_FILTER_3_COV_DEFSfmt */ 20539 /* nFields */ 4, 20540 /* *fields */ soc_ETRAP_FILTER_0_COV_DEFSfmt_fields, 20541 /* bits */ 17, 20542 /* flags */ 0, 20543 }, 20544 #endif /* chips */ 20545 20546 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 20547 { /* SOC_FORMAT_INT_ETRAP_FLOW_CNTRL_LEFT_COV_DEFSfmt */ 20548 /* format ETRAP_FLOW_CNTRL_LEFT_COV_DEFSfmt */ 20549 /* nFields */ 4, 20550 /* *fields */ soc_ETRAP_FLOW_CNTRL_LEFT_COV_DEFSfmt_fields, 20551 /* bits */ 14, 20552 /* flags */ 0, 20553 }, 20554 #endif /* chips */ 20555 20556 #if defined(BCM_56980_A0) 20557 { /* SOC_FORMAT_INT_ETRAP_FLOW_CNTRL_RIGHT_COV_DEFSfmt */ 20558 /* format ETRAP_FLOW_CNTRL_RIGHT_COV_DEFSfmt */ 20559 /* nFields */ 4, 20560 /* *fields */ soc_ETRAP_FLOW_CNTRL_LEFT_COV_DEFSfmt_fields, 20561 /* bits */ 14, 20562 /* flags */ 0, 20563 }, 20564 #endif /* chips */ 20565 20566 #if defined(BCM_56980_B0) 20567 { /* SOC_FORMAT_INT_ETRAP_FLOW_CNTRL_RIGHT_COV_DEFS_BCM56980_B0fmt */ 20568 /* format ETRAP_FLOW_CNTRL_RIGHT_COV_DEFSfmt */ 20569 /* nFields */ 4, 20570 /* *fields */ soc_ETRAP_FLOW_CNTRL_LEFT_COV_DEFSfmt_fields, 20571 /* bits */ 14, 20572 /* flags */ 0, 20573 }, 20574 #endif /* chips */ 20575 20576 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 20577 { /* SOC_FORMAT_INT_ETRAP_FLOW_COUNTfmt */ 20578 /* format ETRAP_FLOW_COUNTfmt */ 20579 /* nFields */ 1, 20580 /* *fields */ soc_ETRAP_FLOW_COUNTfmt_fields, 20581 /* bits */ 27, 20582 /* flags */ 0, 20583 }, 20584 #endif /* chips */ 20585 20586 #if defined(BCM_56980_A0) 20587 { /* SOC_FORMAT_INT_ETRAP_FLOW_COUNT_LEFT_COV_DEFSfmt */ 20588 /* format ETRAP_FLOW_COUNT_LEFT_COV_DEFSfmt */ 20589 /* nFields */ 4, 20590 /* *fields */ soc_ETRAP_FLOW_CNTRL_LEFT_COV_DEFSfmt_fields, 20591 /* bits */ 14, 20592 /* flags */ 0, 20593 }, 20594 #endif /* chips */ 20595 20596 #if defined(BCM_56980_B0) 20597 { /* SOC_FORMAT_INT_ETRAP_FLOW_COUNT_LEFT_COV_DEFS_BCM56980_B0fmt */ 20598 /* format ETRAP_FLOW_COUNT_LEFT_COV_DEFSfmt */ 20599 /* nFields */ 4, 20600 /* *fields */ soc_ETRAP_FLOW_CNTRL_LEFT_COV_DEFSfmt_fields, 20601 /* bits */ 14, 20602 /* flags */ 0, 20603 }, 20604 #endif /* chips */ 20605 20606 #if defined(BCM_56980_A0) 20607 { /* SOC_FORMAT_INT_ETRAP_FLOW_COUNT_RIGHT_COV_DEFSfmt */ 20608 /* format ETRAP_FLOW_COUNT_RIGHT_COV_DEFSfmt */ 20609 /* nFields */ 4, 20610 /* *fields */ soc_ETRAP_FLOW_CNTRL_LEFT_COV_DEFSfmt_fields, 20611 /* bits */ 14, 20612 /* flags */ 0, 20613 }, 20614 #endif /* chips */ 20615 20616 #if defined(BCM_56980_B0) 20617 { /* SOC_FORMAT_INT_ETRAP_FLOW_COUNT_RIGHT_COV_DEFS_BCM56980_B0fmt */ 20618 /* format ETRAP_FLOW_COUNT_RIGHT_COV_DEFSfmt */ 20619 /* nFields */ 4, 20620 /* *fields */ soc_ETRAP_FLOW_CNTRL_LEFT_COV_DEFSfmt_fields, 20621 /* bits */ 14, 20622 /* flags */ 0, 20623 }, 20624 #endif /* chips */ 20625 20626 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 20627 { /* SOC_FORMAT_INT_ETRAP_FLOW_CTRLfmt */ 20628 /* format ETRAP_FLOW_CTRLfmt */ 20629 /* nFields */ 4, 20630 /* *fields */ soc_ETRAP_FLOW_CTRLfmt_fields, 20631 /* bits */ 6, 20632 /* flags */ 0, 20633 }, 20634 #endif /* chips */ 20635 20636 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 20637 { /* SOC_FORMAT_INT_ETRAP_FLOW_HASHfmt */ 20638 /* format ETRAP_FLOW_HASHfmt */ 20639 /* nFields */ 6, 20640 /* *fields */ soc_ETRAP_FLOW_HASHfmt_fields, 20641 /* bits */ 73, 20642 /* flags */ 0, 20643 }, 20644 #endif /* chips */ 20645 20646 #if defined(BCM_56980_A0) 20647 { /* SOC_FORMAT_INT_ETRAP_FLOW_HASH_L0_COV_DEFSfmt */ 20648 /* format ETRAP_FLOW_HASH_L0_COV_DEFSfmt */ 20649 /* nFields */ 4, 20650 /* *fields */ soc_ETRAP_FLOW_CNTRL_LEFT_COV_DEFSfmt_fields, 20651 /* bits */ 14, 20652 /* flags */ 0, 20653 }, 20654 #endif /* chips */ 20655 20656 #if defined(BCM_56980_B0) 20657 { /* SOC_FORMAT_INT_ETRAP_FLOW_HASH_L0_COV_DEFS_BCM56980_B0fmt */ 20658 /* format ETRAP_FLOW_HASH_L0_COV_DEFSfmt */ 20659 /* nFields */ 4, 20660 /* *fields */ soc_ETRAP_FLOW_CNTRL_LEFT_COV_DEFSfmt_fields, 20661 /* bits */ 14, 20662 /* flags */ 0, 20663 }, 20664 #endif /* chips */ 20665 20666 #if defined(BCM_56980_A0) 20667 { /* SOC_FORMAT_INT_ETRAP_FLOW_HASH_L1_COV_DEFSfmt */ 20668 /* format ETRAP_FLOW_HASH_L1_COV_DEFSfmt */ 20669 /* nFields */ 4, 20670 /* *fields */ soc_ETRAP_FLOW_CNTRL_LEFT_COV_DEFSfmt_fields, 20671 /* bits */ 14, 20672 /* flags */ 0, 20673 }, 20674 #endif /* chips */ 20675 20676 #if defined(BCM_56980_B0) 20677 { /* SOC_FORMAT_INT_ETRAP_FLOW_HASH_L1_COV_DEFS_BCM56980_B0fmt */ 20678 /* format ETRAP_FLOW_HASH_L1_COV_DEFSfmt */ 20679 /* nFields */ 4, 20680 /* *fields */ soc_ETRAP_FLOW_CNTRL_LEFT_COV_DEFSfmt_fields, 20681 /* bits */ 14, 20682 /* flags */ 0, 20683 }, 20684 #endif /* chips */ 20685 20686 #if defined(BCM_56980_A0) 20687 { /* SOC_FORMAT_INT_ETRAP_FLOW_HASH_L2_COV_DEFSfmt */ 20688 /* format ETRAP_FLOW_HASH_L2_COV_DEFSfmt */ 20689 /* nFields */ 4, 20690 /* *fields */ soc_ETRAP_FLOW_CNTRL_LEFT_COV_DEFSfmt_fields, 20691 /* bits */ 14, 20692 /* flags */ 0, 20693 }, 20694 #endif /* chips */ 20695 20696 #if defined(BCM_56980_B0) 20697 { /* SOC_FORMAT_INT_ETRAP_FLOW_HASH_L2_COV_DEFS_BCM56980_B0fmt */ 20698 /* format ETRAP_FLOW_HASH_L2_COV_DEFSfmt */ 20699 /* nFields */ 4, 20700 /* *fields */ soc_ETRAP_FLOW_CNTRL_LEFT_COV_DEFSfmt_fields, 20701 /* bits */ 14, 20702 /* flags */ 0, 20703 }, 20704 #endif /* chips */ 20705 20706 #if defined(BCM_56980_A0) 20707 { /* SOC_FORMAT_INT_ETRAP_FLOW_HASH_L3_COV_DEFSfmt */ 20708 /* format ETRAP_FLOW_HASH_L3_COV_DEFSfmt */ 20709 /* nFields */ 4, 20710 /* *fields */ soc_ETRAP_FLOW_CNTRL_LEFT_COV_DEFSfmt_fields, 20711 /* bits */ 14, 20712 /* flags */ 0, 20713 }, 20714 #endif /* chips */ 20715 20716 #if defined(BCM_56980_B0) 20717 { /* SOC_FORMAT_INT_ETRAP_FLOW_HASH_L3_COV_DEFS_BCM56980_B0fmt */ 20718 /* format ETRAP_FLOW_HASH_L3_COV_DEFSfmt */ 20719 /* nFields */ 4, 20720 /* *fields */ soc_ETRAP_FLOW_CNTRL_LEFT_COV_DEFSfmt_fields, 20721 /* bits */ 14, 20722 /* flags */ 0, 20723 }, 20724 #endif /* chips */ 20725 20726 #if defined(BCM_56980_A0) 20727 { /* SOC_FORMAT_INT_ETRAP_FLOW_HASH_L4_COV_DEFSfmt */ 20728 /* format ETRAP_FLOW_HASH_L4_COV_DEFSfmt */ 20729 /* nFields */ 4, 20730 /* *fields */ soc_ETRAP_FLOW_CNTRL_LEFT_COV_DEFSfmt_fields, 20731 /* bits */ 14, 20732 /* flags */ 0, 20733 }, 20734 #endif /* chips */ 20735 20736 #if defined(BCM_56980_B0) 20737 { /* SOC_FORMAT_INT_ETRAP_FLOW_HASH_L4_COV_DEFS_BCM56980_B0fmt */ 20738 /* format ETRAP_FLOW_HASH_L4_COV_DEFSfmt */ 20739 /* nFields */ 4, 20740 /* *fields */ soc_ETRAP_FLOW_CNTRL_LEFT_COV_DEFSfmt_fields, 20741 /* bits */ 14, 20742 /* flags */ 0, 20743 }, 20744 #endif /* chips */ 20745 20746 #if defined(BCM_56980_A0) 20747 { /* SOC_FORMAT_INT_ETRAP_FLOW_HASH_R0_COV_DEFSfmt */ 20748 /* format ETRAP_FLOW_HASH_R0_COV_DEFSfmt */ 20749 /* nFields */ 4, 20750 /* *fields */ soc_ETRAP_FLOW_CNTRL_LEFT_COV_DEFSfmt_fields, 20751 /* bits */ 14, 20752 /* flags */ 0, 20753 }, 20754 #endif /* chips */ 20755 20756 #if defined(BCM_56980_B0) 20757 { /* SOC_FORMAT_INT_ETRAP_FLOW_HASH_R0_COV_DEFS_BCM56980_B0fmt */ 20758 /* format ETRAP_FLOW_HASH_R0_COV_DEFSfmt */ 20759 /* nFields */ 4, 20760 /* *fields */ soc_ETRAP_FLOW_CNTRL_LEFT_COV_DEFSfmt_fields, 20761 /* bits */ 14, 20762 /* flags */ 0, 20763 }, 20764 #endif /* chips */ 20765 20766 #if defined(BCM_56980_A0) 20767 { /* SOC_FORMAT_INT_ETRAP_FLOW_HASH_R1_COV_DEFSfmt */ 20768 /* format ETRAP_FLOW_HASH_R1_COV_DEFSfmt */ 20769 /* nFields */ 4, 20770 /* *fields */ soc_ETRAP_FLOW_CNTRL_LEFT_COV_DEFSfmt_fields, 20771 /* bits */ 14, 20772 /* flags */ 0, 20773 }, 20774 #endif /* chips */ 20775 20776 #if defined(BCM_56980_B0) 20777 { /* SOC_FORMAT_INT_ETRAP_FLOW_HASH_R1_COV_DEFS_BCM56980_B0fmt */ 20778 /* format ETRAP_FLOW_HASH_R1_COV_DEFSfmt */ 20779 /* nFields */ 4, 20780 /* *fields */ soc_ETRAP_FLOW_CNTRL_LEFT_COV_DEFSfmt_fields, 20781 /* bits */ 14, 20782 /* flags */ 0, 20783 }, 20784 #endif /* chips */ 20785 20786 #if defined(BCM_56980_A0) 20787 { /* SOC_FORMAT_INT_ETRAP_FLOW_HASH_R2_COV_DEFSfmt */ 20788 /* format ETRAP_FLOW_HASH_R2_COV_DEFSfmt */ 20789 /* nFields */ 4, 20790 /* *fields */ soc_ETRAP_FLOW_CNTRL_LEFT_COV_DEFSfmt_fields, 20791 /* bits */ 14, 20792 /* flags */ 0, 20793 }, 20794 #endif /* chips */ 20795 20796 #if defined(BCM_56980_B0) 20797 { /* SOC_FORMAT_INT_ETRAP_FLOW_HASH_R2_COV_DEFS_BCM56980_B0fmt */ 20798 /* format ETRAP_FLOW_HASH_R2_COV_DEFSfmt */ 20799 /* nFields */ 4, 20800 /* *fields */ soc_ETRAP_FLOW_CNTRL_LEFT_COV_DEFSfmt_fields, 20801 /* bits */ 14, 20802 /* flags */ 0, 20803 }, 20804 #endif /* chips */ 20805 20806 #if defined(BCM_56980_A0) 20807 { /* SOC_FORMAT_INT_ETRAP_FLOW_HASH_R3_COV_DEFSfmt */ 20808 /* format ETRAP_FLOW_HASH_R3_COV_DEFSfmt */ 20809 /* nFields */ 4, 20810 /* *fields */ soc_ETRAP_FLOW_CNTRL_LEFT_COV_DEFSfmt_fields, 20811 /* bits */ 14, 20812 /* flags */ 0, 20813 }, 20814 #endif /* chips */ 20815 20816 #if defined(BCM_56980_B0) 20817 { /* SOC_FORMAT_INT_ETRAP_FLOW_HASH_R3_COV_DEFS_BCM56980_B0fmt */ 20818 /* format ETRAP_FLOW_HASH_R3_COV_DEFSfmt */ 20819 /* nFields */ 4, 20820 /* *fields */ soc_ETRAP_FLOW_CNTRL_LEFT_COV_DEFSfmt_fields, 20821 /* bits */ 14, 20822 /* flags */ 0, 20823 }, 20824 #endif /* chips */ 20825 20826 #if defined(BCM_56980_A0) 20827 { /* SOC_FORMAT_INT_ETRAP_FLOW_HASH_R4_COV_DEFSfmt */ 20828 /* format ETRAP_FLOW_HASH_R4_COV_DEFSfmt */ 20829 /* nFields */ 4, 20830 /* *fields */ soc_ETRAP_FLOW_CNTRL_LEFT_COV_DEFSfmt_fields, 20831 /* bits */ 14, 20832 /* flags */ 0, 20833 }, 20834 #endif /* chips */ 20835 20836 #if defined(BCM_56980_B0) 20837 { /* SOC_FORMAT_INT_ETRAP_FLOW_HASH_R4_COV_DEFS_BCM56980_B0fmt */ 20838 /* format ETRAP_FLOW_HASH_R4_COV_DEFSfmt */ 20839 /* nFields */ 4, 20840 /* *fields */ soc_ETRAP_FLOW_CNTRL_LEFT_COV_DEFSfmt_fields, 20841 /* bits */ 14, 20842 /* flags */ 0, 20843 }, 20844 #endif /* chips */ 20845 20846 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 20847 { /* SOC_FORMAT_INT_ETRAP_HASH_SAVEfmt */ 20848 /* format ETRAP_HASH_SAVEfmt */ 20849 /* nFields */ 6, 20850 /* *fields */ soc_ETRAP_HASH_SAVEfmt_fields, 20851 /* bits */ 66, 20852 /* flags */ 0, 20853 }, 20854 #endif /* chips */ 20855 20856 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 20857 { /* SOC_FORMAT_INT_ETRAP_INfmt */ 20858 /* format ETRAP_INfmt */ 20859 /* nFields */ 11, 20860 /* *fields */ soc_ETRAP_INfmt_fields, 20861 /* bits */ 91, 20862 /* flags */ 0, 20863 }, 20864 #endif /* chips */ 20865 20866 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 20867 { /* SOC_FORMAT_INT_ETRAP_OUTfmt */ 20868 /* format ETRAP_OUTfmt */ 20869 /* nFields */ 4, 20870 /* *fields */ soc_ETRAP_OUTfmt_fields, 20871 /* bits */ 5, 20872 /* flags */ 0, 20873 }, 20874 #endif /* chips */ 20875 20876 #if defined(BCM_56640_A0) 20877 { /* SOC_FORMAT_INT_ETU_CP_MEM_ACC_REQfmt */ 20878 /* format ETU_CP_MEM_ACC_REQfmt */ 20879 /* nFields */ 36, 20880 /* *fields */ soc_ETU_CP_MEM_ACC_REQfmt_fields, 20881 /* bits */ 36, 20882 /* flags */ 0, 20883 }, 20884 #endif /* chips */ 20885 20886 #if defined(BCM_56640_A0) 20887 { /* SOC_FORMAT_INT_ETU_CP_XLAT_RESULTfmt */ 20888 /* format ETU_CP_XLAT_RESULTfmt */ 20889 /* nFields */ 12, 20890 /* *fields */ soc_ETU_CP_XLAT_RESULTfmt_fields, 20891 /* bits */ 58, 20892 /* flags */ 0, 20893 }, 20894 #endif /* chips */ 20895 20896 #if defined(BCM_56640_A0) 20897 { /* SOC_FORMAT_INT_ETU_TX_PIPE_CTL_FIFOfmt */ 20898 /* format ETU_TX_PIPE_CTL_FIFOfmt */ 20899 /* nFields */ 17, 20900 /* *fields */ soc_ETU_TX_PIPE_CTL_FIFOfmt_fields, 20901 /* bits */ 53, 20902 /* flags */ 0, 20903 }, 20904 #endif /* chips */ 20905 20906 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 20907 defined(BCM_56870_A0) 20908 { /* SOC_FORMAT_INT_EVLAN_DOPfmt */ 20909 /* format EVLAN_DOPfmt */ 20910 /* nFields */ 6, 20911 /* *fields */ soc_EVLAN_DOPfmt_fields, 20912 /* bits */ 224, 20913 /* flags */ 0, 20914 }, 20915 #endif /* chips */ 20916 20917 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \ 20918 defined(BCM_56270_A0) || defined(BCM_56560_A0) || \ 20919 defined(BCM_56560_B0) || defined(BCM_56670_A0) || \ 20920 defined(BCM_56670_B0) || defined(BCM_56960_A0) || \ 20921 defined(BCM_56965_A0) || defined(BCM_56970_A0) 20922 { /* SOC_FORMAT_INT_EXACT_MATCH_2_DATAfmt */ 20923 /* format EXACT_MATCH_2_DATAfmt */ 20924 /* nFields */ 12, 20925 /* *fields */ soc_EXACT_MATCH_2_DATAfmt_fields, 20926 /* bits */ 74, 20927 /* flags */ 0, 20928 }, 20929 #endif /* chips */ 20930 20931 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \ 20932 defined(BCM_56270_A0) || defined(BCM_56560_A0) || \ 20933 defined(BCM_56560_B0) || defined(BCM_56670_A0) || \ 20934 defined(BCM_56670_B0) || defined(BCM_56960_A0) || \ 20935 defined(BCM_56965_A0) || defined(BCM_56970_A0) 20936 { /* SOC_FORMAT_INT_EXACT_MATCH_4_DATAfmt */ 20937 /* format EXACT_MATCH_4_DATAfmt */ 20938 /* nFields */ 6, 20939 /* *fields */ soc_EXACT_MATCH_4_DATAfmt_fields, 20940 /* bits */ 84, 20941 /* flags */ 0, 20942 }, 20943 #endif /* chips */ 20944 20945 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 20946 defined(BCM_56870_A0) || defined(BCM_56960_A0) || \ 20947 defined(BCM_56965_A0) || defined(BCM_56970_A0) 20948 { /* SOC_FORMAT_INT_EXACT_MATCH_CTRLfmt */ 20949 /* format EXACT_MATCH_CTRLfmt */ 20950 /* nFields */ 5, 20951 /* *fields */ soc_EXACT_MATCH_CTRLfmt_fields, 20952 /* bits */ 13, 20953 /* flags */ 0, 20954 }, 20955 #endif /* chips */ 20956 20957 #if defined(BCM_56980_A0) 20958 { /* SOC_FORMAT_INT_EXACT_MATCH_CTRL_BCM56980_A0fmt */ 20959 /* format EXACT_MATCH_CTRLfmt */ 20960 /* nFields */ 7, 20961 /* *fields */ soc_EXACT_MATCH_CTRL_BCM56980_A0fmt_fields, 20962 /* bits */ 16, 20963 /* flags */ 0, 20964 }, 20965 #endif /* chips */ 20966 20967 #if defined(BCM_56980_B0) 20968 { /* SOC_FORMAT_INT_EXACT_MATCH_CTRL_BCM56980_B0fmt */ 20969 /* format EXACT_MATCH_CTRLfmt */ 20970 /* nFields */ 7, 20971 /* *fields */ soc_EXACT_MATCH_CTRL_BCM56980_A0fmt_fields, 20972 /* bits */ 16, 20973 /* flags */ 0, 20974 }, 20975 #endif /* chips */ 20976 20977 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 20978 defined(BCM_56870_A0) || defined(BCM_56960_A0) || \ 20979 defined(BCM_56965_A0) || defined(BCM_56970_A0) 20980 { /* SOC_FORMAT_INT_EXACT_MATCH_DATAfmt */ 20981 /* format EXACT_MATCH_DATAfmt */ 20982 /* nFields */ 5, 20983 /* *fields */ soc_EXACT_MATCH_DATAfmt_fields, 20984 /* bits */ 97, 20985 /* flags */ 0, 20986 }, 20987 #endif /* chips */ 20988 20989 #if defined(BCM_56980_A0) 20990 { /* SOC_FORMAT_INT_EXACT_MATCH_DATA_BCM56980_A0fmt */ 20991 /* format EXACT_MATCH_DATAfmt */ 20992 /* nFields */ 5, 20993 /* *fields */ soc_EXACT_MATCH_DATA_BCM56980_A0fmt_fields, 20994 /* bits */ 96, 20995 /* flags */ 0, 20996 }, 20997 #endif /* chips */ 20998 20999 #if defined(BCM_56980_B0) 21000 { /* SOC_FORMAT_INT_EXACT_MATCH_DATA_BCM56980_B0fmt */ 21001 /* format EXACT_MATCH_DATAfmt */ 21002 /* nFields */ 5, 21003 /* *fields */ soc_EXACT_MATCH_DATA_BCM56980_A0fmt_fields, 21004 /* bits */ 96, 21005 /* flags */ 0, 21006 }, 21007 #endif /* chips */ 21008 21009 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) 21010 { /* SOC_FORMAT_INT_EXACT_MATCH_DOPfmt */ 21011 /* format EXACT_MATCH_DOPfmt */ 21012 /* nFields */ 6, 21013 /* *fields */ soc_EXACT_MATCH_DOPfmt_fields, 21014 /* bits */ 64, 21015 /* flags */ 0, 21016 }, 21017 #endif /* chips */ 21018 21019 #if defined(BCM_56370_A0) 21020 { /* SOC_FORMAT_INT_EXACT_MATCH_DOP_BCM56370_A0fmt */ 21021 /* format EXACT_MATCH_DOPfmt */ 21022 /* nFields */ 6, 21023 /* *fields */ soc_EXACT_MATCH_DOP_BCM56370_A0fmt_fields, 21024 /* bits */ 64, 21025 /* flags */ 0, 21026 }, 21027 #endif /* chips */ 21028 21029 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \ 21030 defined(BCM_56270_A0) || defined(BCM_56560_A0) || \ 21031 defined(BCM_56560_B0) || defined(BCM_56670_A0) || \ 21032 defined(BCM_56670_B0) || defined(BCM_56960_A0) || \ 21033 defined(BCM_56965_A0) || defined(BCM_56970_A0) 21034 { /* SOC_FORMAT_INT_EXACT_MATCH_KEYfmt */ 21035 /* format EXACT_MATCH_KEYfmt */ 21036 /* nFields */ 15, 21037 /* *fields */ soc_EXACT_MATCH_KEYfmt_fields, 21038 /* bits */ 322, 21039 /* flags */ 0, 21040 }, 21041 #endif /* chips */ 21042 21043 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) 21044 { /* SOC_FORMAT_INT_EXACT_MATCH_KEY_DOPfmt */ 21045 /* format EXACT_MATCH_KEY_DOPfmt */ 21046 /* nFields */ 4, 21047 /* *fields */ soc_EXACT_MATCH_KEY_DOPfmt_fields, 21048 /* bits */ 672, 21049 /* flags */ 0, 21050 }, 21051 #endif /* chips */ 21052 21053 #if defined(BCM_56370_A0) 21054 { /* SOC_FORMAT_INT_EXACT_MATCH_KEY_DOP_BCM56370_A0fmt */ 21055 /* format EXACT_MATCH_KEY_DOPfmt */ 21056 /* nFields */ 4, 21057 /* *fields */ soc_EXACT_MATCH_KEY_DOP_BCM56370_A0fmt_fields, 21058 /* bits */ 672, 21059 /* flags */ 0, 21060 }, 21061 #endif /* chips */ 21062 21063 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) || \ 21064 defined(BCM_56270_A0) || defined(BCM_56960_A0) || \ 21065 defined(BCM_56965_A0) || defined(BCM_56970_A0) 21066 { /* SOC_FORMAT_INT_EXACT_MATCH_KEY_SPECIALfmt */ 21067 /* format EXACT_MATCH_KEY_SPECIALfmt */ 21068 /* nFields */ 16, 21069 /* *fields */ soc_EXACT_MATCH_KEY_SPECIALfmt_fields, 21070 /* bits */ 330, 21071 /* flags */ 0, 21072 }, 21073 #endif /* chips */ 21074 21075 #if defined(BCM_56560_A0) 21076 { /* SOC_FORMAT_INT_EXACT_MATCH_KEY_SPECIAL_BCM56560_A0fmt */ 21077 /* format EXACT_MATCH_KEY_SPECIALfmt */ 21078 /* nFields */ 17, 21079 /* *fields */ soc_EXACT_MATCH_KEY_SPECIAL_BCM56560_A0fmt_fields, 21080 /* bits */ 330, 21081 /* flags */ 0, 21082 }, 21083 #endif /* chips */ 21084 21085 #if defined(BCM_56560_B0) 21086 { /* SOC_FORMAT_INT_EXACT_MATCH_KEY_SPECIAL_BCM56560_B0fmt */ 21087 /* format EXACT_MATCH_KEY_SPECIALfmt */ 21088 /* nFields */ 17, 21089 /* *fields */ soc_EXACT_MATCH_KEY_SPECIAL_BCM56560_A0fmt_fields, 21090 /* bits */ 330, 21091 /* flags */ 0, 21092 }, 21093 #endif /* chips */ 21094 21095 #if defined(BCM_56670_A0) 21096 { /* SOC_FORMAT_INT_EXACT_MATCH_KEY_SPECIAL_BCM56670_A0fmt */ 21097 /* format EXACT_MATCH_KEY_SPECIALfmt */ 21098 /* nFields */ 17, 21099 /* *fields */ soc_EXACT_MATCH_KEY_SPECIAL_BCM56560_A0fmt_fields, 21100 /* bits */ 330, 21101 /* flags */ 0, 21102 }, 21103 #endif /* chips */ 21104 21105 #if defined(BCM_56670_B0) 21106 { /* SOC_FORMAT_INT_EXACT_MATCH_KEY_SPECIAL_BCM56670_B0fmt */ 21107 /* format EXACT_MATCH_KEY_SPECIALfmt */ 21108 /* nFields */ 17, 21109 /* *fields */ soc_EXACT_MATCH_KEY_SPECIAL_BCM56560_A0fmt_fields, 21110 /* bits */ 330, 21111 /* flags */ 0, 21112 }, 21113 #endif /* chips */ 21114 21115 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 21116 { /* SOC_FORMAT_INT_EXACT_MATCH_LOGICAL_TABLE_SELECT_DATA_FORMATfmt */ 21117 /* format EXACT_MATCH_LOGICAL_TABLE_SELECT_DATA_FORMATfmt */ 21118 /* nFields */ 23, 21119 /* *fields */ soc_EXACT_MATCH_LOGICAL_TABLE_SELECT_DATA_FORMATfmt_fields, 21120 /* bits */ 56, 21121 /* flags */ 0, 21122 }, 21123 #endif /* chips */ 21124 21125 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 21126 { /* SOC_FORMAT_INT_EXACT_MATCH_LOGICAL_TABLE_SELECT_TCAM_FORMATfmt */ 21127 /* format EXACT_MATCH_LOGICAL_TABLE_SELECT_TCAM_FORMATfmt */ 21128 /* nFields */ 33, 21129 /* *fields */ soc_EXACT_MATCH_LOGICAL_TABLE_SELECT_TCAM_FORMATfmt_fields, 21130 /* bits */ 169, 21131 /* flags */ 0, 21132 }, 21133 #endif /* chips */ 21134 21135 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 21136 defined(BCM_56870_A0) || defined(BCM_56960_A0) || \ 21137 defined(BCM_56965_A0) || defined(BCM_56970_A0) 21138 { /* SOC_FORMAT_INT_EXACT_MATCH_LOOKUP_STATUSfmt */ 21139 /* format EXACT_MATCH_LOOKUP_STATUSfmt */ 21140 /* nFields */ 5, 21141 /* *fields */ soc_EXACT_MATCH_LOOKUP_STATUSfmt_fields, 21142 /* bits */ 15, 21143 /* flags */ 0, 21144 }, 21145 #endif /* chips */ 21146 21147 #if defined(BCM_56980_A0) 21148 { /* SOC_FORMAT_INT_EXACT_MATCH_LOOKUP_STATUS_BCM56980_A0fmt */ 21149 /* format EXACT_MATCH_LOOKUP_STATUSfmt */ 21150 /* nFields */ 3, 21151 /* *fields */ soc_EXACT_MATCH_LOOKUP_STATUS_BCM56980_A0fmt_fields, 21152 /* bits */ 6, 21153 /* flags */ 0, 21154 }, 21155 #endif /* chips */ 21156 21157 #if defined(BCM_56980_B0) 21158 { /* SOC_FORMAT_INT_EXACT_MATCH_LOOKUP_STATUS_BCM56980_B0fmt */ 21159 /* format EXACT_MATCH_LOOKUP_STATUSfmt */ 21160 /* nFields */ 3, 21161 /* *fields */ soc_EXACT_MATCH_LOOKUP_STATUS_BCM56980_A0fmt_fields, 21162 /* bits */ 6, 21163 /* flags */ 0, 21164 }, 21165 #endif /* chips */ 21166 21167 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 21168 defined(BCM_56870_A0) 21169 { /* SOC_FORMAT_INT_EXACT_MATCH_LTS_DOPfmt */ 21170 /* format EXACT_MATCH_LTS_DOPfmt */ 21171 /* nFields */ 6, 21172 /* *fields */ soc_EXACT_MATCH_LTS_DOPfmt_fields, 21173 /* bits */ 32, 21174 /* flags */ 0, 21175 }, 21176 #endif /* chips */ 21177 21178 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 21179 defined(BCM_56870_A0) 21180 { /* SOC_FORMAT_INT_EXACT_MATCH_PDD_OUT_BUSfmt */ 21181 /* format EXACT_MATCH_PDD_OUT_BUSfmt */ 21182 /* nFields */ 121, 21183 /* *fields */ soc_EXACT_MATCH_PDD_OUT_BUSfmt_fields, 21184 /* bits */ 305, 21185 /* flags */ 0, 21186 }, 21187 #endif /* chips */ 21188 21189 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) 21190 { /* SOC_FORMAT_INT_EXACT_MATCH_POLICYfmt */ 21191 /* format EXACT_MATCH_POLICYfmt */ 21192 /* nFields */ 4, 21193 /* *fields */ soc_EXACT_MATCH_POLICYfmt_fields, 21194 /* bits */ 88, 21195 /* flags */ 0, 21196 }, 21197 #endif /* chips */ 21198 21199 #if defined(BCM_56370_A0) 21200 { /* SOC_FORMAT_INT_EXACT_MATCH_POLICY_BCM56370_A0fmt */ 21201 /* format EXACT_MATCH_POLICYfmt */ 21202 /* nFields */ 4, 21203 /* *fields */ soc_EXACT_MATCH_POLICY_BCM56870_A0fmt_fields, 21204 /* bits */ 84, 21205 /* flags */ 0, 21206 }, 21207 #endif /* chips */ 21208 21209 #if defined(BCM_56770_A0) 21210 { /* SOC_FORMAT_INT_EXACT_MATCH_POLICY_BCM56770_A0fmt */ 21211 /* format EXACT_MATCH_POLICYfmt */ 21212 /* nFields */ 6, 21213 /* *fields */ soc_EXACT_MATCH_POLICY_BCM56770_A0fmt_fields, 21214 /* bits */ 87, 21215 /* flags */ 0, 21216 }, 21217 #endif /* chips */ 21218 21219 #if defined(BCM_56870_A0) 21220 { /* SOC_FORMAT_INT_EXACT_MATCH_POLICY_BCM56870_A0fmt */ 21221 /* format EXACT_MATCH_POLICYfmt */ 21222 /* nFields */ 4, 21223 /* *fields */ soc_EXACT_MATCH_POLICY_BCM56870_A0fmt_fields, 21224 /* bits */ 84, 21225 /* flags */ 0, 21226 }, 21227 #endif /* chips */ 21228 21229 #if defined(BCM_56970_A0) 21230 { /* SOC_FORMAT_INT_EXACT_MATCH_POLICY_BCM56970_A0fmt */ 21231 /* format EXACT_MATCH_POLICYfmt */ 21232 /* nFields */ 4, 21233 /* *fields */ soc_EXACT_MATCH_POLICY_MODE320_BCM56965_A0fmt_fields, 21234 /* bits */ 84, 21235 /* flags */ 0, 21236 }, 21237 #endif /* chips */ 21238 21239 #if defined(BCM_56980_A0) 21240 { /* SOC_FORMAT_INT_EXACT_MATCH_POLICY_BCM56980_A0fmt */ 21241 /* format EXACT_MATCH_POLICYfmt */ 21242 /* nFields */ 4, 21243 /* *fields */ soc_EXACT_MATCH_POLICY_BCM56870_A0fmt_fields, 21244 /* bits */ 84, 21245 /* flags */ 0, 21246 }, 21247 #endif /* chips */ 21248 21249 #if defined(BCM_56980_B0) 21250 { /* SOC_FORMAT_INT_EXACT_MATCH_POLICY_BCM56980_B0fmt */ 21251 /* format EXACT_MATCH_POLICYfmt */ 21252 /* nFields */ 4, 21253 /* *fields */ soc_EXACT_MATCH_POLICY_BCM56870_A0fmt_fields, 21254 /* bits */ 84, 21255 /* flags */ 0, 21256 }, 21257 #endif /* chips */ 21258 21259 #if defined(BCM_56960_A0) 21260 { /* SOC_FORMAT_INT_EXACT_MATCH_POLICY_MODE128fmt */ 21261 /* format EXACT_MATCH_POLICY_MODE128fmt */ 21262 /* nFields */ 4, 21263 /* *fields */ soc_EXACT_MATCH_POLICY_MODE128fmt_fields, 21264 /* bits */ 74, 21265 /* flags */ 0, 21266 }, 21267 #endif /* chips */ 21268 21269 #if defined(BCM_56960_A0) 21270 { /* SOC_FORMAT_INT_EXACT_MATCH_POLICY_MODE160fmt */ 21271 /* format EXACT_MATCH_POLICY_MODE160fmt */ 21272 /* nFields */ 4, 21273 /* *fields */ soc_EXACT_MATCH_POLICY_MODE160fmt_fields, 21274 /* bits */ 42, 21275 /* flags */ 0, 21276 }, 21277 #endif /* chips */ 21278 21279 #if defined(BCM_56960_A0) 21280 { /* SOC_FORMAT_INT_EXACT_MATCH_POLICY_MODE320fmt */ 21281 /* format EXACT_MATCH_POLICY_MODE320fmt */ 21282 /* nFields */ 4, 21283 /* *fields */ soc_EXACT_MATCH_POLICY_MODE320fmt_fields, 21284 /* bits */ 84, 21285 /* flags */ 0, 21286 }, 21287 #endif /* chips */ 21288 21289 #if defined(BCM_56370_A0) 21290 { /* SOC_FORMAT_INT_EXACT_MATCH_POLICY_MODE128_BCM56370_A0fmt */ 21291 /* format EXACT_MATCH_POLICY_MODE128fmt */ 21292 /* nFields */ 4, 21293 /* *fields */ soc_EXACT_MATCH_POLICY_MODE128_BCM56870_A0fmt_fields, 21294 /* bits */ 74, 21295 /* flags */ 0, 21296 }, 21297 #endif /* chips */ 21298 21299 #if defined(BCM_56770_A0) 21300 { /* SOC_FORMAT_INT_EXACT_MATCH_POLICY_MODE128_BCM56770_A0fmt */ 21301 /* format EXACT_MATCH_POLICY_MODE128fmt */ 21302 /* nFields */ 6, 21303 /* *fields */ soc_EXACT_MATCH_POLICY_MODE128_BCM56770_A0fmt_fields, 21304 /* bits */ 77, 21305 /* flags */ 0, 21306 }, 21307 #endif /* chips */ 21308 21309 #if defined(BCM_56870_A0) 21310 { /* SOC_FORMAT_INT_EXACT_MATCH_POLICY_MODE128_BCM56870_A0fmt */ 21311 /* format EXACT_MATCH_POLICY_MODE128fmt */ 21312 /* nFields */ 4, 21313 /* *fields */ soc_EXACT_MATCH_POLICY_MODE128_BCM56870_A0fmt_fields, 21314 /* bits */ 74, 21315 /* flags */ 0, 21316 }, 21317 #endif /* chips */ 21318 21319 #if defined(BCM_56965_A0) 21320 { /* SOC_FORMAT_INT_EXACT_MATCH_POLICY_MODE128_BCM56965_A0fmt */ 21321 /* format EXACT_MATCH_POLICY_MODE128fmt */ 21322 /* nFields */ 4, 21323 /* *fields */ soc_EXACT_MATCH_POLICY_MODE128_BCM56965_A0fmt_fields, 21324 /* bits */ 74, 21325 /* flags */ 0, 21326 }, 21327 #endif /* chips */ 21328 21329 #if defined(BCM_56970_A0) 21330 { /* SOC_FORMAT_INT_EXACT_MATCH_POLICY_MODE128_BCM56970_A0fmt */ 21331 /* format EXACT_MATCH_POLICY_MODE128fmt */ 21332 /* nFields */ 4, 21333 /* *fields */ soc_EXACT_MATCH_POLICY_MODE128_BCM56965_A0fmt_fields, 21334 /* bits */ 74, 21335 /* flags */ 0, 21336 }, 21337 #endif /* chips */ 21338 21339 #if defined(BCM_56980_A0) 21340 { /* SOC_FORMAT_INT_EXACT_MATCH_POLICY_MODE128_BCM56980_A0fmt */ 21341 /* format EXACT_MATCH_POLICY_MODE128fmt */ 21342 /* nFields */ 4, 21343 /* *fields */ soc_EXACT_MATCH_POLICY_MODE128_BCM56870_A0fmt_fields, 21344 /* bits */ 74, 21345 /* flags */ 0, 21346 }, 21347 #endif /* chips */ 21348 21349 #if defined(BCM_56980_B0) 21350 { /* SOC_FORMAT_INT_EXACT_MATCH_POLICY_MODE128_BCM56980_B0fmt */ 21351 /* format EXACT_MATCH_POLICY_MODE128fmt */ 21352 /* nFields */ 4, 21353 /* *fields */ soc_EXACT_MATCH_POLICY_MODE128_BCM56870_A0fmt_fields, 21354 /* bits */ 74, 21355 /* flags */ 0, 21356 }, 21357 #endif /* chips */ 21358 21359 #if defined(BCM_56370_A0) 21360 { /* SOC_FORMAT_INT_EXACT_MATCH_POLICY_MODE160_BCM56370_A0fmt */ 21361 /* format EXACT_MATCH_POLICY_MODE160fmt */ 21362 /* nFields */ 4, 21363 /* *fields */ soc_EXACT_MATCH_POLICY_MODE160_BCM56870_A0fmt_fields, 21364 /* bits */ 42, 21365 /* flags */ 0, 21366 }, 21367 #endif /* chips */ 21368 21369 #if defined(BCM_56770_A0) 21370 { /* SOC_FORMAT_INT_EXACT_MATCH_POLICY_MODE160_BCM56770_A0fmt */ 21371 /* format EXACT_MATCH_POLICY_MODE160fmt */ 21372 /* nFields */ 6, 21373 /* *fields */ soc_EXACT_MATCH_POLICY_MODE160_BCM56770_A0fmt_fields, 21374 /* bits */ 45, 21375 /* flags */ 0, 21376 }, 21377 #endif /* chips */ 21378 21379 #if defined(BCM_56870_A0) 21380 { /* SOC_FORMAT_INT_EXACT_MATCH_POLICY_MODE160_BCM56870_A0fmt */ 21381 /* format EXACT_MATCH_POLICY_MODE160fmt */ 21382 /* nFields */ 4, 21383 /* *fields */ soc_EXACT_MATCH_POLICY_MODE160_BCM56870_A0fmt_fields, 21384 /* bits */ 42, 21385 /* flags */ 0, 21386 }, 21387 #endif /* chips */ 21388 21389 #if defined(BCM_56965_A0) 21390 { /* SOC_FORMAT_INT_EXACT_MATCH_POLICY_MODE160_BCM56965_A0fmt */ 21391 /* format EXACT_MATCH_POLICY_MODE160fmt */ 21392 /* nFields */ 4, 21393 /* *fields */ soc_EXACT_MATCH_POLICY_MODE160_BCM56965_A0fmt_fields, 21394 /* bits */ 42, 21395 /* flags */ 0, 21396 }, 21397 #endif /* chips */ 21398 21399 #if defined(BCM_56970_A0) 21400 { /* SOC_FORMAT_INT_EXACT_MATCH_POLICY_MODE160_BCM56970_A0fmt */ 21401 /* format EXACT_MATCH_POLICY_MODE160fmt */ 21402 /* nFields */ 4, 21403 /* *fields */ soc_EXACT_MATCH_POLICY_MODE160_BCM56965_A0fmt_fields, 21404 /* bits */ 42, 21405 /* flags */ 0, 21406 }, 21407 #endif /* chips */ 21408 21409 #if defined(BCM_56980_A0) 21410 { /* SOC_FORMAT_INT_EXACT_MATCH_POLICY_MODE160_BCM56980_A0fmt */ 21411 /* format EXACT_MATCH_POLICY_MODE160fmt */ 21412 /* nFields */ 4, 21413 /* *fields */ soc_EXACT_MATCH_POLICY_MODE160_BCM56870_A0fmt_fields, 21414 /* bits */ 42, 21415 /* flags */ 0, 21416 }, 21417 #endif /* chips */ 21418 21419 #if defined(BCM_56980_B0) 21420 { /* SOC_FORMAT_INT_EXACT_MATCH_POLICY_MODE160_BCM56980_B0fmt */ 21421 /* format EXACT_MATCH_POLICY_MODE160fmt */ 21422 /* nFields */ 4, 21423 /* *fields */ soc_EXACT_MATCH_POLICY_MODE160_BCM56870_A0fmt_fields, 21424 /* bits */ 42, 21425 /* flags */ 0, 21426 }, 21427 #endif /* chips */ 21428 21429 #if defined(BCM_56370_A0) 21430 { /* SOC_FORMAT_INT_EXACT_MATCH_POLICY_MODE320_BCM56370_A0fmt */ 21431 /* format EXACT_MATCH_POLICY_MODE320fmt */ 21432 /* nFields */ 4, 21433 /* *fields */ soc_EXACT_MATCH_POLICY_BCM56870_A0fmt_fields, 21434 /* bits */ 84, 21435 /* flags */ 0, 21436 }, 21437 #endif /* chips */ 21438 21439 #if defined(BCM_56770_A0) 21440 { /* SOC_FORMAT_INT_EXACT_MATCH_POLICY_MODE320_BCM56770_A0fmt */ 21441 /* format EXACT_MATCH_POLICY_MODE320fmt */ 21442 /* nFields */ 6, 21443 /* *fields */ soc_EXACT_MATCH_POLICY_BCM56770_A0fmt_fields, 21444 /* bits */ 87, 21445 /* flags */ 0, 21446 }, 21447 #endif /* chips */ 21448 21449 #if defined(BCM_56870_A0) 21450 { /* SOC_FORMAT_INT_EXACT_MATCH_POLICY_MODE320_BCM56870_A0fmt */ 21451 /* format EXACT_MATCH_POLICY_MODE320fmt */ 21452 /* nFields */ 4, 21453 /* *fields */ soc_EXACT_MATCH_POLICY_BCM56870_A0fmt_fields, 21454 /* bits */ 84, 21455 /* flags */ 0, 21456 }, 21457 #endif /* chips */ 21458 21459 #if defined(BCM_56965_A0) 21460 { /* SOC_FORMAT_INT_EXACT_MATCH_POLICY_MODE320_BCM56965_A0fmt */ 21461 /* format EXACT_MATCH_POLICY_MODE320fmt */ 21462 /* nFields */ 4, 21463 /* *fields */ soc_EXACT_MATCH_POLICY_MODE320_BCM56965_A0fmt_fields, 21464 /* bits */ 84, 21465 /* flags */ 0, 21466 }, 21467 #endif /* chips */ 21468 21469 #if defined(BCM_56970_A0) 21470 { /* SOC_FORMAT_INT_EXACT_MATCH_POLICY_MODE320_BCM56970_A0fmt */ 21471 /* format EXACT_MATCH_POLICY_MODE320fmt */ 21472 /* nFields */ 4, 21473 /* *fields */ soc_EXACT_MATCH_POLICY_MODE320_BCM56965_A0fmt_fields, 21474 /* bits */ 84, 21475 /* flags */ 0, 21476 }, 21477 #endif /* chips */ 21478 21479 #if defined(BCM_56980_A0) 21480 { /* SOC_FORMAT_INT_EXACT_MATCH_POLICY_MODE320_BCM56980_A0fmt */ 21481 /* format EXACT_MATCH_POLICY_MODE320fmt */ 21482 /* nFields */ 4, 21483 /* *fields */ soc_EXACT_MATCH_POLICY_BCM56870_A0fmt_fields, 21484 /* bits */ 84, 21485 /* flags */ 0, 21486 }, 21487 #endif /* chips */ 21488 21489 #if defined(BCM_56980_B0) 21490 { /* SOC_FORMAT_INT_EXACT_MATCH_POLICY_MODE320_BCM56980_B0fmt */ 21491 /* format EXACT_MATCH_POLICY_MODE320fmt */ 21492 /* nFields */ 4, 21493 /* *fields */ soc_EXACT_MATCH_POLICY_BCM56870_A0fmt_fields, 21494 /* bits */ 84, 21495 /* flags */ 0, 21496 }, 21497 #endif /* chips */ 21498 21499 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) 21500 { /* SOC_FORMAT_INT_EXACT_MATCH_REDIRECT_SETfmt */ 21501 /* format EXACT_MATCH_REDIRECT_SETfmt */ 21502 /* nFields */ 15, 21503 /* *fields */ soc_EXACT_MATCH_REDIRECT_SETfmt_fields, 21504 /* bits */ 25, 21505 /* flags */ 0, 21506 }, 21507 #endif /* chips */ 21508 21509 #if defined(BCM_56370_A0) 21510 { /* SOC_FORMAT_INT_EXACT_MATCH_REDIRECT_SET_BCM56370_A0fmt */ 21511 /* format EXACT_MATCH_REDIRECT_SETfmt */ 21512 /* nFields */ 15, 21513 /* *fields */ soc_EXACT_MATCH_REDIRECT_SET_BCM56370_A0fmt_fields, 21514 /* bits */ 25, 21515 /* flags */ 0, 21516 }, 21517 #endif /* chips */ 21518 21519 #if defined(BCM_56770_A0) 21520 { /* SOC_FORMAT_INT_EXACT_MATCH_REDIRECT_SET_BCM56770_A0fmt */ 21521 /* format EXACT_MATCH_REDIRECT_SETfmt */ 21522 /* nFields */ 15, 21523 /* *fields */ soc_EXACT_MATCH_REDIRECT_SET_BCM56870_A0fmt_fields, 21524 /* bits */ 25, 21525 /* flags */ 0, 21526 }, 21527 #endif /* chips */ 21528 21529 #if defined(BCM_56870_A0) 21530 { /* SOC_FORMAT_INT_EXACT_MATCH_REDIRECT_SET_BCM56870_A0fmt */ 21531 /* format EXACT_MATCH_REDIRECT_SETfmt */ 21532 /* nFields */ 15, 21533 /* *fields */ soc_EXACT_MATCH_REDIRECT_SET_BCM56870_A0fmt_fields, 21534 /* bits */ 25, 21535 /* flags */ 0, 21536 }, 21537 #endif /* chips */ 21538 21539 #if defined(BCM_56970_A0) 21540 { /* SOC_FORMAT_INT_EXACT_MATCH_REDIRECT_SET_BCM56970_A0fmt */ 21541 /* format EXACT_MATCH_REDIRECT_SETfmt */ 21542 /* nFields */ 15, 21543 /* *fields */ soc_EXACT_MATCH_REDIRECT_SET_BCM56970_A0fmt_fields, 21544 /* bits */ 25, 21545 /* flags */ 0, 21546 }, 21547 #endif /* chips */ 21548 21549 #if defined(BCM_56980_A0) 21550 { /* SOC_FORMAT_INT_EXACT_MATCH_REDIRECT_SET_BCM56980_A0fmt */ 21551 /* format EXACT_MATCH_REDIRECT_SETfmt */ 21552 /* nFields */ 15, 21553 /* *fields */ soc_EXACT_MATCH_REDIRECT_SET_BCM56980_A0fmt_fields, 21554 /* bits */ 25, 21555 /* flags */ 0, 21556 }, 21557 #endif /* chips */ 21558 21559 #if defined(BCM_56980_B0) 21560 { /* SOC_FORMAT_INT_EXACT_MATCH_REDIRECT_SET_BCM56980_B0fmt */ 21561 /* format EXACT_MATCH_REDIRECT_SETfmt */ 21562 /* nFields */ 15, 21563 /* *fields */ soc_EXACT_MATCH_REDIRECT_SET_BCM56980_A0fmt_fields, 21564 /* bits */ 25, 21565 /* flags */ 0, 21566 }, 21567 #endif /* chips */ 21568 21569 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 21570 defined(BCM_56870_A0) || defined(BCM_56960_A0) || \ 21571 defined(BCM_56965_A0) || defined(BCM_56970_A0) 21572 { /* SOC_FORMAT_INT_EXACT_MATCH_RESULT_BUSfmt */ 21573 /* format EXACT_MATCH_RESULT_BUSfmt */ 21574 /* nFields */ 2, 21575 /* *fields */ soc_EXACT_MATCH_RESULT_BUSfmt_fields, 21576 /* bits */ 194, 21577 /* flags */ 0, 21578 }, 21579 #endif /* chips */ 21580 21581 #if defined(BCM_56980_A0) 21582 { /* SOC_FORMAT_INT_EXACT_MATCH_RESULT_BUS_BCM56980_A0fmt */ 21583 /* format EXACT_MATCH_RESULT_BUSfmt */ 21584 /* nFields */ 1, 21585 /* *fields */ soc_EXACT_MATCH_RESULT_BUS_BCM56980_A0fmt_fields, 21586 /* bits */ 96, 21587 /* flags */ 0, 21588 }, 21589 #endif /* chips */ 21590 21591 #if defined(BCM_56980_B0) 21592 { /* SOC_FORMAT_INT_EXACT_MATCH_RESULT_BUS_BCM56980_B0fmt */ 21593 /* format EXACT_MATCH_RESULT_BUSfmt */ 21594 /* nFields */ 1, 21595 /* *fields */ soc_EXACT_MATCH_RESULT_BUS_BCM56980_A0fmt_fields, 21596 /* bits */ 96, 21597 /* flags */ 0, 21598 }, 21599 #endif /* chips */ 21600 21601 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 21602 defined(BCM_56870_A0) || defined(BCM_56960_A0) || \ 21603 defined(BCM_56965_A0) || defined(BCM_56970_A0) 21604 { /* SOC_FORMAT_INT_EXACT_MATCH_TO_FP_KEY_SEL_BUSfmt */ 21605 /* format EXACT_MATCH_TO_FP_KEY_SEL_BUSfmt */ 21606 /* nFields */ 2, 21607 /* *fields */ soc_EXACT_MATCH_TO_FP_KEY_SEL_BUSfmt_fields, 21608 /* bits */ 26, 21609 /* flags */ 0, 21610 }, 21611 #endif /* chips */ 21612 21613 #if defined(BCM_56980_A0) 21614 { /* SOC_FORMAT_INT_EXACT_MATCH_TO_FP_KEY_SEL_BUS_BCM56980_A0fmt */ 21615 /* format EXACT_MATCH_TO_FP_KEY_SEL_BUSfmt */ 21616 /* nFields */ 1, 21617 /* *fields */ soc_EXACT_MATCH_TO_FP_KEY_SEL_BUS_BCM56980_A0fmt_fields, 21618 /* bits */ 16, 21619 /* flags */ 0, 21620 }, 21621 #endif /* chips */ 21622 21623 #if defined(BCM_56980_B0) 21624 { /* SOC_FORMAT_INT_EXACT_MATCH_TO_FP_KEY_SEL_BUS_BCM56980_B0fmt */ 21625 /* format EXACT_MATCH_TO_FP_KEY_SEL_BUSfmt */ 21626 /* nFields */ 1, 21627 /* *fields */ soc_EXACT_MATCH_TO_FP_KEY_SEL_BUS_BCM56980_A0fmt_fields, 21628 /* bits */ 16, 21629 /* flags */ 0, 21630 }, 21631 #endif /* chips */ 21632 21633 #if defined(BCM_56370_A0) 21634 { /* SOC_FORMAT_INT_EXPORT_FIFO_DATAfmt */ 21635 /* format EXPORT_FIFO_DATAfmt */ 21636 /* nFields */ 40, 21637 /* *fields */ soc_EXPORT_FIFO_DATAfmt_fields, 21638 /* bits */ 1152, 21639 /* flags */ 0, 21640 }, 21641 #endif /* chips */ 21642 21643 #if defined(BCM_56370_A0) 21644 { /* SOC_FORMAT_INT_EXPORT_TIMER_BUSfmt */ 21645 /* format EXPORT_TIMER_BUSfmt */ 21646 /* nFields */ 8, 21647 /* *fields */ soc_EXPORT_TIMER_BUSfmt_fields, 21648 /* bits */ 56, 21649 /* flags */ 0, 21650 }, 21651 #endif /* chips */ 21652 21653 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) 21654 { /* SOC_FORMAT_INT_EXTENDED_VIEW_L3_OIF_ACTION_SETfmt */ 21655 /* format EXTENDED_VIEW_L3_OIF_ACTION_SETfmt */ 21656 /* nFields */ 1, 21657 /* *fields */ soc_EXTENDED_VIEW_L3_OIF_ACTION_SETfmt_fields, 21658 /* bits */ 14, 21659 /* flags */ 0, 21660 }, 21661 #endif /* chips */ 21662 21663 #if defined(BCM_56370_A0) 21664 { /* SOC_FORMAT_INT_EXTENDED_VIEW_L3_OIF_ACTION_SET_BCM56370_A0fmt */ 21665 /* format EXTENDED_VIEW_L3_OIF_ACTION_SETfmt */ 21666 /* nFields */ 2, 21667 /* *fields */ soc_EXTENDED_VIEW_L3_OIF_ACTION_SET_BCM56370_A0fmt_fields, 21668 /* bits */ 14, 21669 /* flags */ 0, 21670 }, 21671 #endif /* chips */ 21672 21673 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 21674 defined(BCM_56870_A0) 21675 { /* SOC_FORMAT_INT_EXTENDED_VIEW_MACDA_ACTION_SETfmt */ 21676 /* format EXTENDED_VIEW_MACDA_ACTION_SETfmt */ 21677 /* nFields */ 7, 21678 /* *fields */ soc_EXTENDED_VIEW_MACDA_ACTION_SETfmt_fields, 21679 /* bits */ 50, 21680 /* flags */ 0, 21681 }, 21682 #endif /* chips */ 21683 21684 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 21685 defined(BCM_56870_A0) 21686 { /* SOC_FORMAT_INT_EXTRACTION_CTRL_ID_ACTION_SETfmt */ 21687 /* format EXTRACTION_CTRL_ID_ACTION_SETfmt */ 21688 /* nFields */ 2, 21689 /* *fields */ soc_EXTRACTION_CTRL_ID_ACTION_SETfmt_fields, 21690 /* bits */ 16, 21691 /* flags */ 0, 21692 }, 21693 #endif /* chips */ 21694 21695 #if defined(BCM_56640_A0) 21696 { /* SOC_FORMAT_INT_EXT_AD_1Xfmt */ 21697 /* format EXT_AD_1Xfmt */ 21698 /* nFields */ 2, 21699 /* *fields */ soc_EXT_AD_1Xfmt_fields, 21700 /* bits */ 35, 21701 /* flags */ 0, 21702 }, 21703 #endif /* chips */ 21704 21705 #if defined(BCM_56640_A0) 21706 { /* SOC_FORMAT_INT_EXT_AD_2Xfmt */ 21707 /* format EXT_AD_2Xfmt */ 21708 /* nFields */ 2, 21709 /* *fields */ soc_EXT_AD_2Xfmt_fields, 21710 /* bits */ 70, 21711 /* flags */ 0, 21712 }, 21713 #endif /* chips */ 21714 21715 #if defined(BCM_56640_A0) 21716 { /* SOC_FORMAT_INT_EXT_AD_3Xfmt */ 21717 /* format EXT_AD_3Xfmt */ 21718 /* nFields */ 2, 21719 /* *fields */ soc_EXT_AD_3Xfmt_fields, 21720 /* bits */ 105, 21721 /* flags */ 0, 21722 }, 21723 #endif /* chips */ 21724 21725 #if defined(BCM_56640_A0) 21726 { /* SOC_FORMAT_INT_EXT_AD_4Xfmt */ 21727 /* format EXT_AD_4Xfmt */ 21728 /* nFields */ 2, 21729 /* *fields */ soc_EXT_AD_4Xfmt_fields, 21730 /* bits */ 140, 21731 /* flags */ 0, 21732 }, 21733 #endif /* chips */ 21734 21735 #if defined(BCM_56640_A0) 21736 { /* SOC_FORMAT_INT_EXT_AD_6Xfmt */ 21737 /* format EXT_AD_6Xfmt */ 21738 /* nFields */ 2, 21739 /* *fields */ soc_EXT_AD_6Xfmt_fields, 21740 /* bits */ 210, 21741 /* flags */ 0, 21742 }, 21743 #endif /* chips */ 21744 21745 #if defined(BCM_56640_A0) 21746 { /* SOC_FORMAT_INT_EXT_AD_REQ_ADDRfmt */ 21747 /* format EXT_AD_REQ_ADDRfmt */ 21748 /* nFields */ 4, 21749 /* *fields */ soc_EXT_AD_REQ_ADDRfmt_fields, 21750 /* bits */ 26, 21751 /* flags */ 0, 21752 }, 21753 #endif /* chips */ 21754 21755 #if defined(BCM_56640_A0) 21756 { /* SOC_FORMAT_INT_EXT_HBIT_CMDfmt */ 21757 /* format EXT_HBIT_CMDfmt */ 21758 /* nFields */ 7, 21759 /* *fields */ soc_EXT_HBIT_CMDfmt_fields, 21760 /* bits */ 64, 21761 /* flags */ 0, 21762 }, 21763 #endif /* chips */ 21764 21765 #if defined(BCM_56640_A0) 21766 { /* SOC_FORMAT_INT_EXT_TCAM_REQ_WDATAfmt */ 21767 /* format EXT_TCAM_REQ_WDATAfmt */ 21768 /* nFields */ 40, 21769 /* *fields */ soc_EXT_TCAM_REQ_WDATAfmt_fields, 21770 /* bits */ 885, 21771 /* flags */ 0, 21772 }, 21773 #endif /* chips */ 21774 21775 #if defined(BCM_56640_A0) 21776 { /* SOC_FORMAT_INT_EXT_TCAM_RSP_WDATAfmt */ 21777 /* format EXT_TCAM_RSP_WDATAfmt */ 21778 /* nFields */ 38, 21779 /* *fields */ soc_EXT_TCAM_RSP_WDATAfmt_fields, 21780 /* bits */ 220, 21781 /* flags */ 0, 21782 }, 21783 #endif /* chips */ 21784