allformats_desc.i (230654B)
1 /* 2 * DO NOT EDIT THIS FILE! 3 * This file is auto-generated from the registers file. 4 * Edits to this file will be lost when it is regenerated. 5 * 6 * 7 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 8 * 9 * Copyright 2007-2020 Broadcom Inc. All rights reserved. 10 * 11 * File: allformats_desc.i 12 * Purpose: Format descriptions. 13 */ 14 15 /* ACK_BUS_CP */ "Ack Bus for CB.", 16 /* ACK_BUS_EXT_AD */ "ESMIF Ack.", 17 /* ACK_BUS_MAC_LIMIT */ "Mac Limit Result for SOPs.", 18 /* ACK_BUS_MAC_LIMIT_CP */ "Requst Bus for Mac Limit Resource Block.", 19 /* ACK_BUS_MOD_FIFO_CP */ "Requst Bus for Mac Limit Resource Block.", 20 /* ACK_BUS_PIPE_TBL0 */ "Key Search Ack Bus for TBL0 (Ivxlt VLAN_XLATE request).", 21 /* ACK_BUS_PIPE_TBL1 */ "Key Search Ack Bus for TBL1 (Il2lu request).", 22 /* ACK_BUS_PIPE_TBL2 */ "Key Search Ack Bus for TBL2 (Il3lu request).", 23 /* ACK_BUS_PIPE_TBL3 */ "Key Search Ack Bus for TBL3 (Evxlt request).", 24 /* ACK_BUS_PIPE_TBL4 */ "Key Search Ack Bus for TBL4 (Ivxlt MPLS_ENTRY request).", 25 /* ACK_DATA_EXT_AD_CP */ "ETU Control Plane Ack. This is a 35-bit bus (ack_data_ext_ad_cp), multi-clock pulse ack_ext_ad_cp controls number of beats. Bits 34:0 are sent first, followed by bits 69:35, etc. If ack is due to WRITE, ack_ext_ad_cp is pulsed for one clock with nothing returned in RDATA.", 26 /* ACK_DATA_EXT_L2 */ "ETU External L2 Interface. This is a 35-bit bus (ack_data_ext_l2), multi-clock pulse ack_ext_l2 controls number of beats. Bits 34:0 are sent first, followed by bits 69:35, etc.", 27 /* ACTION_TABLE */ "Remapping table (key+1).", 28 /* ACTION_TABLE_ECC */ "Remapping table (key+1).", 29 /* ADM_TO_CLINKE_INFO */ "Position and description of bits", 30 /* ADM_TO_ENQ */ "adm to enq interface definition", 31 /* ADM_TO_ENQ_INFO */ "Position and description of bits in ADM->ENQ Accept/Drop interface", 32 /* ADM_TO_IPCTR_D_RESOURCE */ "ADM to IPCTR D_RESOURCE", 33 /* ADM_TO_THDI_QEN_PURGE_INFO */ "Position and description of bits", 34 /* ADM_TO_TOQ_EOPE */ "Position and description of bits", 35 /* AGING_CTR_S_RF */ "aging ctr memory s_rf width", 36 /* AGING_CTR_S_RF_0 */ "aging ctr memory s_rf width", 37 /* AGING_CTR_S_RF_1 */ "aging ctr memory s_rf width", 38 /* AGING_CTR_S_RF_2 */ "aging ctr memory s_rf width", 39 /* AGING_CTR_S_RF_3 */ "aging ctr memory s_rf width", 40 /* AGING_EXP_S_RF */ "aging exp memory s_rf width", 41 /* AGING_EXP_S_RF_0 */ "aging exp memory s_rf width", 42 /* AGING_EXP_S_RF_1 */ "aging exp memory s_rf width", 43 /* AGING_EXP_S_RF_2 */ "aging exp memory s_rf width", 44 /* AGING_EXP_S_RF_3 */ "aging exp memory s_rf width", 45 /* ALPM1_DATA */ "Associated Data Full Format.", 46 /* ALPM2_DATA */ "Associated Data Full Format.", 47 /* ALPM_KEY_MUX_FORMAT */ "L3 Defip ALPM Route Associated Data FMT7. 12 bytes, 5 entries per bank.", 48 /* ARP_HDR */ "ARP header specification", 49 /* ASSIGNED_VNTAG_ETAG_DOP */ "ASSIGNED_VNTAG_ETAG_DOP DOP description.", 50 /* ASSOC_DATA_FULL */ "Associated Data Full Format.", 51 /* ASSOC_DATA_REDUCED */ "Associated Data Full Format.", 52 /* AUX_HDR_BITMAP_DOP */ "AUX_HDR_BITMAP_DOP DOP description.", 53 /* AXP_CH_INBUF_CW */ "Control word information for Input Buffer Entries", 54 /* AXP_CH_OUTBUF_CW */ "Control word information for Input Buffer Entries", 55 /* AXP_IP_CTL */ "Control signals from AXP to NLF", 56 /* AXP_IP_DATA */ "Data transfers from AXP to IP", 57 /* AXP_META_DATA_COMMON */ "Control word information for Input Buffer Entries", 58 /* AXP_META_DATA_SM_NLF */ "Meta-data headaer for SM NLF", 59 /* AXP_META_DATA_WRX_NLF */ "Meta-data header for WLAN decap(receive) NLF", 60 /* AXP_META_DATA_WTX_NLF */ "Meta-data headaer for WLAN encap (transmit) NLF", 61 /* AXP_NLF_CTL */ "Format of the control signal bus from AXP to NLF for incoming data.", 62 /* AXP_NLF_DATA */ "Format of the data bus from AXP to NLF.", 63 /* AXP_NLF_INFO */ "Exchange of credits or other info", 64 /* AXP_NLF_SYSTEM_IN */ "System-level control signals from AXP to NLF", 65 /* AXP_SHAPE */ "Description of fields on the AXP_SHAPE Bus from AXP to MMU (These values are sent back with orignal values from the PBE).", 66 /* AXP_SM_EGRESS_LOOPBACK_HEADER */ "***NETWORK ORDER*** Loopback header sent with each packet.", 67 /* AXP_SM_INGRESS_METADATA_HEADER */ "Metadata header received with each packet.", 68 /* AXP_TO_IP_MDH */ "Header carrying meta data from AXP to IP", 69 /* AXP_WRX_EGRESS_LOOPBACK_HEADER */ "Loopback header prepended to each packet to AXP/IP.", 70 /* AXP_WTX_DP */ "Datapath format for WLAN TX NLF", 71 /* AXP_WTX_WCTL */ "Control information associated with data word", 72 /* BANK_BASE_VALID */ "Format used to align a raw key to base_0_key, base_1_key, base_2_key and base_3_key.", 73 /* BANK_HITREQ_BUS_IN */ "Search Stage Hit Request Bus.", 74 /* BANK_HITREQ_BUS_IN_C_MODEL */ "Search Stage Hit Request Bus.", 75 /* BANK_HITRST_BUS_OUT */ "Search Stage Hit Result Bus.", 76 /* BANK_HITRST_BUS_OUT_C_MODEL */ "Search Stage Hit Result Bus.", 77 /* BANK_REQ_BUS_IN */ "Search Stage Request Bus.", 78 /* BANK_REQ_BUS_IN_C_MODEL */ "Search Stage Request Bus.", 79 /* BANK_RST_BUS_IN */ "Search Stage Result Bus.", 80 /* BANK_RST_BUS_IN_C_MODEL */ "Search Stage Result Bus.", 81 /* BANK_RST_BUS_OUT */ "Search Stage Result Bus.", 82 /* BANK_RST_BUS_OUT_C_MODEL */ "Search Stage Result Bus.", 83 /* BANK_WR_INTF */ "This is the WR interface for BANK's PORT B .", 84 /* BASE_VALID_FORMAT */ "Format used to align a raw key to base_0_key, base_1_key, base_2_key and base_3_key.", 85 /* BFD */ "", 86 /* BOD_TO_IP_CONTROL_WORD */ "BOD to IP Control Word", 87 /* BROADSCAN_KEYGEN_IN_BUS */ "Broadscan Keygen Input Bus.", 88 /* BROADSCAN_KEYGEN_OUT_BUS */ "Broadscan Keygen Output Bus.", 89 /* BSC_AG_AGE_CONTROL_FLOW_METER_REFRESH_BUS */ "Bit Definitions of the Age control to Flow Meter Refresh Bus", 90 /* BSC_AG_AGE_CONTROL_INSTRUCTION_OUT_BUS */ "Bit Definitions of the Age control block instruction out Bus", 91 /* BSC_DG_GROUP_ALU16_PROFILE_BUS */ "Bit Definitions of the Group Glue In Bus", 92 /* BSC_DG_GROUP_ALU32_PROFILE_BUS */ "Bit Definitions of the Group Glue In Bus", 93 /* BSC_DT_ALU_OPERATION */ "Bit Definitions of the Group Glue In Bus", 94 /* BSC_DT_CHECK_OPERATION_BIT_SELECT_BUS */ "Bit Definitions of the 16b bus from which we select 4 x 1b to be fed to Flex switch logic", 95 /* BSC_DT_FLEX_OPERATION */ "Bit Definitions of the Group Glue In Bus", 96 /* BSC_DT_FLEX_STATE_TRANSITION_IN_BUS */ "Input bus to Flex State Transition Table.It is only valid for SOP cell.", 97 /* BSC_DT_FT_CONTROL_INPUT_BUS */ "Bit Definitions of the Data Table Controls coming from within Broadscan", 98 /* BSC_DT_INPUT_DATA_BUS */ "Bit Definitions of the Data Table Input Data Bus", 99 /* BSC_DT_KMAP_3_FLOW_DIRECTION_IN_BUS */ "Bit Definitions of the 8b bus from which we select 4 x 1b to be fed to Flex switch logic to generate FLOW_DIRECTION", 100 /* BSC_DT_METER_EOP_IN_BUS */ "BSC METER EOP IN BUS FORMAT", 101 /* BSC_DT_METER_EOP_OUT_BUS */ "BSC DT METER EOP OUT BUS FORMAT", 102 /* BSC_DT_METER_MASTER_REFRESH_IN_BUS */ "BSC METER MASTER IN BUS FORMAT", 103 /* BSC_DT_METER_PIPELINE_IN_BUS */ "BSC METER PIPELINE IN BUS FORMAT", 104 /* BSC_DT_METER_PIPELINE_OUT_BUS */ "BSC METER PIPELINE OUT BUS FORMAT", 105 /* BSC_DT_METER_PIPE_CTRL_BUS */ "BSC METER PIPE CTRL BUS FORMAT", 106 /* BSC_DT_METER_PIPE_DATA_BUS */ "BSC METER PIPE DATA BUS FORMAT", 107 /* BSC_DT_METER_SOP_IN_BUS */ "BSC METER SOP IN BUS FORMAT", 108 /* BSC_DT_METER_SOP_OUT_BUS */ "BSC METER SOP OUT BUS FORMAT", 109 /* BSC_DT_PIPELINE_CONTROL_INPUT_BUS */ "Bit Definitions of the Data Table Controls coming from Pipeline", 110 /* BSC_EX_EXPORT_FLAGS */ "Export Flags", 111 /* BSC_EX_EXPORT_REASON */ "Bit Definitions of the Group Glue Out Bus", 112 /* BSC_EX_EXPORT_RECORD */ "Export Record", 113 /* BSC_EX_SET_HEADER */ "Set Header", 114 /* BSC_IO_EVENT_VECTOR */ "Bit Definitions of the Event Vector", 115 /* BSC_IO_OUT_CONTROL_BUS */ "Bit Definitions of the Broadscan Core Output Control Bus (that goes to IFP)", 116 /* BSC_IPFIX_STATS_CNTR_TRIG_BUS */ "Bit Definitions of the Bus containing data for IPFIX STATS counters", 117 /* BSC_KMAP_CONTROL */ "Bit Definitions of the Kmap Control bus", 118 /* BSC_TL_DG_TO_DT_ALU16_CONTROL_BUS */ "Bit Definitions of the ALU16 Control Bus", 119 /* BSC_TL_DG_TO_DT_ALU16_SPECIFIC_CONTROL_BUS */ "Bit Definitions of the ALU16 Specific Control Bus", 120 /* BSC_TL_DG_TO_DT_ALU32_CONTROL_BUS */ "Bit Definitions of the ALU32 Control Bus", 121 /* BSC_TL_DG_TO_DT_ALU32_SPECIFIC_CONTROL_BUS */ "Bit Definitions of the ALU32 Specific Control Bus", 122 /* BSC_TL_DG_TO_DT_ALU_BASE_CONTROL_BUS */ "Bit Definitions of the ALU Base Control Bus", 123 /* BSC_TL_DG_TO_DT_COPY_TO_COLLECTOR_CONTROL_BUS */ "Bit Definitions of the Group Glue Out Bus", 124 /* BSC_TL_DG_TO_DT_LOAD16_CONTROL_BUS */ "Bit Definitions of the Group Glue In Bus", 125 /* BSC_TL_DG_TO_DT_LOAD8_CONTROL_BUS */ "Bit Definitions of the Group Glue In Bus", 126 /* BSC_TL_DG_TO_DT_METER_CONTROL_BUS */ "Bit Definitions of the Group Glue In Bus", 127 /* BSC_TL_DT_TO_DG_DEBUG_CNTR_TRIG_IN_BUS */ "Bit Definitions of the Data Table Debug Counters Trigger Bus", 128 /* BSC_TL_DT_TO_DG_TRIG_IN_BUS */ "Bit Definitions of the Group Glue In Bus", 129 /* BSC_TL_KF_TO_DT_DATA_BUS */ "Bit Definitions of the ALU Data Bus", 130 /* BSC_TL_KG_TO_KT_AGE_CONTROL_BUS */ "Bit Definitions of the Group Glue In Bus", 131 /* BSC_TL_KG_TO_KT_LIMITS_CONTROL_BUS */ "Bit Definitions of the Group Glue In Bus", 132 /* BSC_TL_KG_TO_KT_TRIG_CONTROL_OUT_BUS */ "Bit Definitions of the Group Glue Out Bus", 133 /* BSC_TL_KT_TO_DT_CONTROL_BUS */ "Description of fields on the BST_KEY_TO_DATA_BUS Bus from Broadscan Key Table to Broadscan Data Table.", 134 /* BSC_TL_KT_TO_KG_DEBUG_CNTR_TRIG_IN_BUS */ "Bit Definitions of the Bus containing inputs for Group Limit Count", 135 /* BSC_TL_KT_TO_KG_TRIG_IN_BUS */ "Bit Definitions of the Bus containing inputs for Group Limit Count", 136 /* BSD_EOP_CONTEXT_BUFFER */ "Broadscan Data Table- EOP Context Buffer", 137 /* BSD_EOP_DATA_BUFFER */ "Broadscan EOP Data Bypass Buffer Format", 138 /* BSD_EXPORT_VECTOR */ "Export Vector Format. Given out from Data Table", 139 /* BSD_FLEX_ALU16_TRACKING_PARAM_0 */ "PDD Output Bus generic format", 140 /* BSD_FLEX_ALU16_TRACKING_PARAM_1 */ "PDD Output Bus generic format", 141 /* BSD_FLEX_ALU16_TRACKING_PARAM_2 */ "PDD Output Bus generic format", 142 /* BSD_FLEX_ALU16_TRACKING_PARAM_3 */ "PDD Output Bus generic format", 143 /* BSD_FLEX_ALU16_TRACKING_PARAM_4 */ "PDD Output Bus generic format", 144 /* BSD_FLEX_ALU16_TRACKING_PARAM_5 */ "PDD Output Bus generic format", 145 /* BSD_FLEX_ALU16_TRACKING_PARAM_6 */ "PDD Output Bus generic format", 146 /* BSD_FLEX_ALU16_TRACKING_PARAM_7 */ "PDD Output Bus generic format", 147 /* BSD_FLEX_ALU32_TRACKING_PARAM_0 */ "PDD Output Bus generic format", 148 /* BSD_FLEX_ALU32_TRACKING_PARAM_1 */ "PDD Output Bus generic format", 149 /* BSD_FLEX_ALU32_TRACKING_PARAM_2 */ "PDD Output Bus generic format", 150 /* BSD_FLEX_ALU32_TRACKING_PARAM_3 */ "PDD Output Bus generic format", 151 /* BSD_FLEX_ALU32_TRACKING_PARAM_4 */ "PDD Output Bus generic format", 152 /* BSD_FLEX_ALU32_TRACKING_PARAM_5 */ "PDD Output Bus generic format", 153 /* BSD_FLEX_ALU32_TRACKING_PARAM_6 */ "PDD Output Bus generic format", 154 /* BSD_FLEX_ALU32_TRACKING_PARAM_7 */ "PDD Output Bus generic format", 155 /* BSD_FLEX_ALU32_TRACKING_PARAM_8 */ "PDD Output Bus generic format", 156 /* BSD_FLEX_ALU32_TRACKING_PARAM_9 */ "PDD Output Bus generic format", 157 /* BSD_FLEX_ALU32_TRACKING_PARAM_10 */ "PDD Output Bus generic format", 158 /* BSD_FLEX_ALU32_TRACKING_PARAM_11 */ "PDD Output Bus generic format", 159 /* BSD_FLEX_FLOW_COUNT_TO_CPU */ "PDD Output Bus generic format", 160 /* BSD_FLEX_FLOW_METER */ "PDD Output Bus generic format", 161 /* BSD_FLEX_FLOW_STATE */ "PDD Output Bus generic format", 162 /* BSD_FLEX_LOAD16_TRACKING_PARAM_0 */ "PDD Output Bus generic format", 163 /* BSD_FLEX_LOAD16_TRACKING_PARAM_1 */ "PDD Output Bus generic format", 164 /* BSD_FLEX_LOAD16_TRACKING_PARAM_2 */ "PDD Output Bus generic format", 165 /* BSD_FLEX_LOAD16_TRACKING_PARAM_3 */ "PDD Output Bus generic format", 166 /* BSD_FLEX_LOAD16_TRACKING_PARAM_4 */ "PDD Output Bus generic format", 167 /* BSD_FLEX_LOAD16_TRACKING_PARAM_5 */ "PDD Output Bus generic format", 168 /* BSD_FLEX_LOAD16_TRACKING_PARAM_6 */ "PDD Output Bus generic format", 169 /* BSD_FLEX_LOAD16_TRACKING_PARAM_7 */ "PDD Output Bus generic format", 170 /* BSD_FLEX_LOAD16_TRACKING_PARAM_8 */ "PDD Output Bus generic format", 171 /* BSD_FLEX_LOAD16_TRACKING_PARAM_9 */ "PDD Output Bus generic format", 172 /* BSD_FLEX_LOAD16_TRACKING_PARAM_10 */ "PDD Output Bus generic format", 173 /* BSD_FLEX_LOAD16_TRACKING_PARAM_11 */ "PDD Output Bus generic format", 174 /* BSD_FLEX_LOAD16_TRACKING_PARAM_12 */ "PDD Output Bus generic format", 175 /* BSD_FLEX_LOAD16_TRACKING_PARAM_13 */ "PDD Output Bus generic format", 176 /* BSD_FLEX_LOAD16_TRACKING_PARAM_14 */ "PDD Output Bus generic format", 177 /* BSD_FLEX_LOAD16_TRACKING_PARAM_15 */ "PDD Output Bus generic format", 178 /* BSD_FLEX_LOAD8_TRACKING_PARAM_0 */ "PDD Output Bus generic format", 179 /* BSD_FLEX_LOAD8_TRACKING_PARAM_1 */ "PDD Output Bus generic format", 180 /* BSD_FLEX_LOAD8_TRACKING_PARAM_2 */ "PDD Output Bus generic format", 181 /* BSD_FLEX_LOAD8_TRACKING_PARAM_3 */ "PDD Output Bus generic format", 182 /* BSD_FLEX_LOAD8_TRACKING_PARAM_4 */ "PDD Output Bus generic format", 183 /* BSD_FLEX_LOAD8_TRACKING_PARAM_5 */ "PDD Output Bus generic format", 184 /* BSD_FLEX_LOAD8_TRACKING_PARAM_6 */ "PDD Output Bus generic format", 185 /* BSD_FLEX_LOAD8_TRACKING_PARAM_7 */ "PDD Output Bus generic format", 186 /* BSD_FLEX_TIMESTAMP_0 */ "PDD Output Bus generic format", 187 /* BSD_FLEX_TIMESTAMP_1 */ "PDD Output Bus generic format", 188 /* BSD_FLEX_TIMESTAMP_2 */ "PDD Output Bus generic format", 189 /* BSD_FLEX_TIMESTAMP_3 */ "PDD Output Bus generic format", 190 /* BSD_PKT_HDR_BUFFER */ "Broadscan Data Table- Pakcet Header Buffer - Used to store ALU_DATA + SESSION_DATA till EOP of packet", 191 /* BSD_POLICY_PDD_OUT_BUS */ "PDD Output Bus generic format", 192 /* BSD_SOP_TO_SOP_DATA_BUFFER */ "Broadscan SOP to SOP Data Bypass Buffer Format", 193 /* BSKRC_BUS */ "Broadscan Resource Control Bus.", 194 /* BSK_BASE_VALID_FORMAT */ "Format used to align a raw key to base_0_key, base_1_key, base_2_key and base_3_key.", 195 /* BSK_CTRL_BUS */ "Control bus to connect between wrappers", 196 /* BSK_DATA_BUS */ "Data bus to connect between wrappers", 197 /* BSK_DT_KMAP_4_TIMESTAMP_TRIGGER_IN_BUS */ "Bit Definitions of the 8b bus from which we select 4 x 1b to be fed to Flex switch logic to generate TIMESTAMP_TRIGGER", 198 /* BSK_EXPORT_RECORD_CONTROL */ "Export Record", 199 /* BSK_FTFP_POLICY */ "", 200 /* BSK_FTFP_TCAM */ "", 201 /* BSK_IN_CONTROL_BUS */ "Ingress Broadscan Flex key gen control bus. It is only valid for SOP cell.", 202 /* BSK_IN_CTRL_BUS */ "Input Control bus to connect to broadscan_top", 203 /* BSK_IN_DATA_BUS */ "Ingress Broadscan Flex key gen fields bus. It is only valid for SOP cell.", 204 /* BSK_IN_DATA_BUS0 */ "Data bus0 to connect input side of broadscan top", 205 /* BSK_IN_DATA_BUS1 */ "Data bus0 to connect input side of broadscan top", 206 /* BSK_IN_HVE_BUS */ "Broadscan HVE Input Bus format.", 207 /* BSK_IN_OBJECT_BUS */ "Broadscan object bus portion of broadscan_key_gen_in_bus. It is only valid for SOP cell.", 208 /* BSK_IPFIX_TO_KEY_TABLE_RESERVATION_ACK */ "Export Fifo rreservation interface", 209 /* BSK_KEY_TABLE_TO_IPFIX_RESERVATION_REQ */ "Export Fifo rreservation interface", 210 /* BSK_KMAP_0_KEY_SWAPPED_IN_BUS */ "Bit Definitions of the 8b bus from which we select 4 x 1b to be fed to Flex switch logic to generate KEY_SWAPPED", 211 /* BSK_KMAP_1_KEY_DIRECTION_IN_BUS */ "Bit Definitions of the 8b bus from which we select 4 x 1b to be fed to Flex switch logic to generate KEY_DIRECTION", 212 /* BSK_KMAP_2_LEARN_DISABLE_IN_BUS */ "Bit Definitions of the 8b bus from which we select 4 x 1b to be fed to Flex switch logic to generate LEARN_DISABLE", 213 /* BSK_LTS_POLICY */ "", 214 /* BSK_LTS_TCAM */ "", 215 /* BSK_NORMALIZE_COMMAND_FORMAT */ "Normalize Command Format", 216 /* BSK_OUT_DATA_BUS */ "Out Data bus to connect input side of broadscan top", 217 /* BS_BANK_WR_INTF */ "Format used to resolve the insert decision between SS0,SS1 stages for Broadscan.", 218 /* BS_BASE_VALID_OUT_BUS */ "Format used to resolve the insert decision between SS0,SS1 stages for Broadscan.", 219 /* BS_ECC_ERR_ENTRY_BUS */ "Format used to resolve the insert decision between SS0,SS1 stages for Broadscan.", 220 /* BS_LOGICAL_BKT_IDX_OUT_BUS */ "Format used to resolve the insert decision between SS0,SS1 stages for Broadscan.", 221 /* BS_REQ_IN_KEY_BUS */ "Format used to resolve the insert decision between SS0,SS1 stages for Broadscan.", 222 /* CAM_BIST_CONFIG_64_FORMAT */ "TCAM BIST CONFIG_64 Format.", 223 /* CAPWAP_RADIOMAC_HDR */ "Capwap wireless specific header.", 224 /* CAPWAP_SHIM_BASE_HDR */ "Capwap shim base specification", 225 /* CAPWAP_WIRELESS_SPECIFIC_HDR */ "Capwap wireless specific header.", 226 /* CBP2M_COSQ */ "Define TOQ/DEQ Non CPU Port CoS queue range for CBP = 2M", 227 /* CBP2M_COSQ_CPU_PORT */ "Define TOQ/DEQ CPU Port CoS queue range for CBP = 2M", 228 /* CBP2M_EPORTS_S0 */ "Define TOQ/DEQ non-cpu ports range in slice 0 for CBP = 2M", 229 /* CBP2M_MEM */ "Define TOQ/DEQ memory range for CBP = 2M", 230 /* CBP2M_PORTS */ "Define TOQ/DEQ ports range for CBP = 2M", 231 /* CBP2M_PORTS_REL_S1 */ "Define TOQ/DEQ base 0 relative ports range in slice 1 for CBP = 2M", 232 /* CBP2M_PORTS_S0 */ "Define TOQ/DEQ ports range in slice 0 for CBP = 2M", 233 /* CBP2M_PORTS_S1 */ "Define TOQ/DEQ ports range in slice 1 for CBP = 2M", 234 /* CBP2M_Q */ "Define TOQ/DEQ Non CPU Port queue range for CBP = 2M", 235 /* CBP2M_Q_CPU_PORT */ "Define TOQ/DEQ CPU Port queue range for CBP = 2M", 236 /* CBP2M_SAVED_SOP_INFO_S0 */ "Define DEQ 0 saved SoP cell queue info, range for CBP = 2M", 237 /* CBP2M_SAVED_SOP_INFO_S1 */ "Define DEQ 1 saved SoP cell queue info, range for CBP = 2M", 238 /* CCBE */ "Position and description of bits in Cell Contol Bus From MMU to Egress pipeline.", 239 /* CCBI */ "Position and description of bits in Cell Control Bus From Ingress pipeline to MMU", 240 /* CCBI_A */ "Position and description of bits in Cell Control Bus A From Ingress pipeline to MMU", 241 /* CCBI_B */ "Position and description of bits in Cell Control Bus B From Ingress pipeline to MMU", 242 /* CCBI_C */ "Cell Control Bus C From Ingress pipeline to MMU. This is required to go along with packet data (CBI)", 243 /* CCP_RESEQ */ "Position and description of bits in the CCP Re-sequence", 244 /* CCP_S_RF */ "ccp memory s_rf width", 245 /* CCP_TO_ENQ_INFO_BUS */ "ccp enq interface for per dst port pkt count", 246 /* CCP_TO_RQE_INFO */ "Position and description of bits", 247 /* CCP_TO_THD0_INFO_BUS */ "Position and description of bits in the CCP to THD 0 INFO bus", 248 /* CCP_TO_THD1_INFO_BUS */ "Position and description of bits in the CCP to THD 1 INFO bus", 249 /* CCP_TO_THDI_INFO_BUS */ "Position and description of bits in the CCP to THDI INFO bus", 250 /* CCP_TO_THDM */ "CCP to THDM interface definition.", 251 /* CCP_TO_THDO_INFO_BUS */ "Position and description of bits in the CCP to THDO INFO bus", 252 /* CCP_TO_THD_INFO_BUS */ "Position and description of bits in the CCP to THD INFO bus", 253 /* CCP_UPDATE_META_DATA */ "Position and description of control bits in the CCP update module", 254 /* CELLCHK_S_RF */ "cellchk memory s_rf width", 255 /* CELLDATA_S_RF */ "celldata memory s_rf width", 256 /* CELLHDR_S_RF */ "cellhdr memory s_rf width", 257 /* CELLLINK_S_RF */ "celllink memory s_rf width", 258 /* CEV_CHAIN_ID */ "format of the counter eviction message", 259 /* CFAP_S_RF */ "cfap memory s_rf width", 260 /* CFG_EOP_BUFFER */ "ICFG EOP BUFFER, Per port register. Not visible to SW", 261 /* CFG_TO_CTR_REG_INFO */ "Position and description of bits", 262 /* CFG_TO_ENQ_REG_INFO */ "Position and description of bits", 263 /* CHIP_CONFIG_OTP */ "Chip config otp ROM image", 264 /* CHIP_FUNCTIONAL_INTR */ "Mapping for Chip functional interrupts to PCI", 265 /* CHIP_LP_INTR */ "Format of chip low priority interrupts hookup going from P&R blocks to iproc_top", 266 /* CHIP_PARITY_INTR */ "Mapping for Chip parity interrupts to PCI", 267 /* CMICD_TO_GIC_INTERUPTS */ "Embedded Higig header sent between EP and port modules", 268 /* CMIC_CMC_IRQ_STAT3 */ "Format of chip interrupt hookup going from P&R blocks to CMIC", 269 /* CMIC_CMC_IRQ_STAT4 */ "Format of chip interrupt hookup going from P&R blocks to CMIC", 270 /* CMIC_CMC_IRQ_STAT5 */ "Format of chip interrupt hookup going from P&R blocks to CMIC", 271 /* CMIC_CMC_IRQ_STAT6 */ "Format of chip interrupt hookup going from P&R blocks to CMIC", 272 /* CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_0 */ "CMIC CORE PLL0_CTRL_STATUS0 FORMAT", 273 /* CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_1 */ "CMIC CORE PLL0_CTRL_STATUS1 FORMAT", 274 /* CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_2 */ "CMIC CORE PLL0_CTRL_STATUS2 FORMAT", 275 /* CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3 */ "CMIC CORE PLL0_CTRL_STATUS3 FORMAT", 276 /* CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_4 */ "CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_4", 277 /* CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_0 */ "CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_0", 278 /* CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_1 */ "CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_1", 279 /* CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_2 */ "CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_2", 280 /* CMIC_CORE_PLL3_CTRL_STATUS_REGISTER_2 */ "ring OSC Control Register", 281 /* CMIC_CORE_PLL3_CTRL_STATUS_REGISTER_3 */ "Temperature Monitor Control Register", 282 /* CMIC_FASTRD_TO_RQE_INFO */ "CMIC backdoor read info to RQE", 283 /* CMIC_FUNC_INTR_STATUS */ "Format of functional interrupt hookup going from functional blocks to CMIC", 284 /* CMIC_INTERUPTS */ "128 bit interrupt status bus output from CMIC", 285 /* CMIC_INTR_STATUS */ "Format of parity interrupt hookup going from P&R blocks to CMIC", 286 /* CMIC_IRQ_STAT_1 */ "Format of functional interrupt hookup going from functional blocks to CMIC", 287 /* CMIC_MISC_CONTROL */ "Mapping for CMIC_MISC_CONTROL register in Scorpion", 288 /* CMIC_MISC_STATUS */ "Mapping for CMIC_MISC_STATUS register in Scorpion", 289 /* CMIC_PARITY_INTR_STATUS */ "Format of parity interrupt hookup going from P&R blocks to CMIC", 290 /* CMIC_SOFT_RESET_REG */ "CMIC SOFT RESET FORMAT", 291 /* CMIC_SOFT_RESET_REG_2 */ "CMIC Soft Reset register 2", 292 /* CMIC_THERMAL_MON_CTRL */ "Temperature Monitor Control Register", 293 /* CMIC_XGXS0_PLL_CONTROL_1 */ "CMIC XGXS PLL 0 Control register 1", 294 /* CMIC_XGXS0_PLL_CONTROL_2 */ "CMIC XGXS PLL 0 Control register 2", 295 /* CMIC_XGXS0_PLL_CONTROL_3 */ "CMIC XGXS PLL 0 Control register 3", 296 /* CMIC_XGXS0_PLL_CONTROL_4 */ "CMIC XGXS PLL 0 Control register 3", 297 /* CMIC_XGXS1_PLL_CONTROL_1 */ "CMIC XGXS PLL 0 Control register 1", 298 /* CMIC_XGXS1_PLL_CONTROL_2 */ "CMIC XGXS PLL 0 Control register 2", 299 /* CMIC_XGXS1_PLL_CONTROL_3 */ "CMIC XGXS PLL 0 Control register 3", 300 /* CMIC_XGXS1_PLL_CONTROL_4 */ "CMIC XGXS PLL 0 Control register 3", 301 /* CMIC_XGXS2_PLL_CONTROL_1 */ "CMIC XGXS PLL 0 Control register 1", 302 /* CMIC_XGXS2_PLL_CONTROL_2 */ "CMIC XGXS PLL 0 Control register 2", 303 /* CMIC_XGXS2_PLL_CONTROL_3 */ "CMIC XGXS PLL 0 Control register 3", 304 /* CMIC_XGXS2_PLL_CONTROL_4 */ "CMIC XGXS PLL 0 Control register 3", 305 /* CMIC_XGXS3_PLL_CONTROL_1 */ "CMIC XGXS PLL 0 Control register 1", 306 /* CMIC_XGXS3_PLL_CONTROL_2 */ "CMIC XGXS PLL 0 Control register 2", 307 /* CMIC_XGXS3_PLL_CONTROL_3 */ "CMIC XGXS PLL 0 Control register 3", 308 /* CMIC_XGXS3_PLL_CONTROL_4 */ "CMIC XGXS PLL 0 Control register 3", 309 /* CML_OFFSET */ "CML bit vector", 310 /* CNTAG_ACTION_SET */ "PDD Output Bus generic format", 311 /* CNTAG_HDR */ "CNTAG header specification", 312 /* COMMON_HEADER_TYPES */ "", 313 /* COPYTO_CPU */ "Bit Definitions of the copy to cpu vector", 314 /* COUNTER_UPDATE_CODE */ "Bit Definitions of the counter update code.", 315 /* COUNTER_UPDATE_VECTOR_DOP */ "COUNTER_UPDATE_VECTOR_DOP DOP description.", 316 /* CPUQ_QDB */ "Position and description of bits in CPUQ QDB register", 317 /* CPU_COS_MAP_DATA_FORMAT */ "format for CPU_COS_MAP data", 318 /* CPU_COS_MAP_KEY */ "CPU_COS_MAP Key", 319 /* CPU_COS_MAP_KEY0_PROBES_DOP */ "CPU_COS_MAP_KEY0_PROBES_DOP DOP description.", 320 /* CPU_COS_MAP_TCAM_FORMAT */ "format for CPU_COS_MAP TCAM", 321 /* CPU_COS_MAP_VAL_PROBES_DOP */ "CPU_COS_MAP_VAL_PROBES_DOP DOP description.", 322 /* CPU_OPCODES */ "Bit Definitions of the CPU Opcodes", 323 /* CPU_OPCODES_OVERLAY_TYPE_0 */ "Bit Definitions of the CPU Opcodes", 324 /* CPU_OPCODES_OVERLAY_TYPE_1 */ "Bit Definitions of the CPU Opcodes", 325 /* CPU_OPCODES_OVERLAY_TYPE_3 */ "Bit Definitions of the CPU Opcodes", 326 /* CPU_OPCODE_VAL_PROBES_DOP */ "CPU_OPCODE_VAL_PROBES_DOP DOP description.", 327 /* CPU_PROTOCOL */ "Copy-to-CPU protocol Types", 328 /* CPU_XQHDR_S_RF */ "CPU XQ Header memory s_rf width", 329 /* CP_REQ_BUS */ "Control plane to tx datapath request bus", 330 /* CTR_EVICTION_MESSAGE */ "format of the counter eviction message", 331 /* CUR_L3_INTF */ "Current L3 intf .", 332 /* CUR_NEXT_HOP */ "Current Next Hop.", 333 /* DELETE_TAG_ACTION_SET */ "PDD Output Bus generic format", 334 /* DEQ0_TO_CCP_INFO_BUS */ "Position and description of bits in the DEQ 0 to CCP INFO bus", 335 /* DEQ0_TO_CTR_INFO */ "Position and description of bits in the DEQ Slice 0 to CTR INFO bus", 336 /* DEQ1_TO_CCP_INFO_BUS */ "Position and description of bits in the DEQ 1 to CCP INFO bus", 337 /* DEQ1_TO_CTR_INFO */ "Position and description of bits in the DEQ Slice 1 to CTR INFO bus", 338 /* DEQ_DEF */ "enq specific defines", 339 /* DEQ_NON_CCBE_CONTROL_INFO */ "Non CCBE Data used for Cell updates passed from DEQ Rd Ctrl subblock thro' DEQ", 340 /* DEQ_RDTBL_TO_CDU_FT_INFO */ "Position and description of bits inside DEQ from read_tbl module to cdu module signaling signature matching bus", 341 /* DEQ_TO_CCPE_INFO */ "Position and description of bits", 342 /* DEQ_TO_CCPI_INFO */ "Position and description of bits in the MMU0 to MMU 1 DEQ to CCPI interface", 343 /* DEQ_TO_CCP_INFO_BUS */ "Position and description of bits in the DEQ to CCP INFO bus", 344 /* DEQ_TO_CTR_DEQ_INFO */ "Format TCACHE Location manager Allocation Structure", 345 /* DEQ_TO_CTR_INFO */ "Position and description of bits in the DEQ to CTR INFO bus", 346 /* DEQ_TO_EMC_RD_REQ_INFO */ "Position and description of bits in the DEQ to EMC Rd Req INFO bus", 347 /* DEQ_TO_LLS_SHAPE_BUS_INFO */ "Position and description of bits", 348 /* DEQ_TO_RDE_CELL_INFO */ "DEQ to RDE CCP information for a tx cell to EP", 349 /* DEQ_TO_RDE_HDR_RD_INFO */ "DEQ to RDE Redirect Header Read Request bus", 350 /* DEQ_TO_RDE_INFO */ "Position and description of bits in the DEQ to RDE bus", 351 /* DEQ_TO_RDE_INFO_BUS0 */ "Position and description of bits in the DEQ to RDE INFO bus 0", 352 /* DEQ_TO_RDE_INFO_BUS1 */ "Position and description of bits in the DEQ to RDE INFO bus 1", 353 /* DEQ_TO_RDE_PQE_CELL_INFO */ "DEQ to RDE CCP information for a tx cell to EP", 354 /* DEQ_TO_RDE_REDIR_INFO */ "DEQ to RDE Redirect bus - originally coming from EP, retimed and sent by DEQ", 355 /* DEQ_TO_SQS_INFO */ "Position and description of bits in the DEQ to SQS INFO", 356 /* DEQ_TO_TOQ_CREDIT_VECTOR_INFO */ "Position and description of bits", 357 /* DEQ_TO_TOQ_INFO */ "Position and description of bits in the DEQ to TOQ INFO", 358 /* DEQ_TO_TOQ_REG_INFO */ "Position and description of bits in the DEQ to TOQ REG INFO bus", 359 /* DEQ_TO_WRED_INFO */ "Position and description of bits", 360 /* DESCRIPTOR_RX_00 */ "Packet DMA RX Descriptor, Word 0 (Control)", 361 /* DESCRIPTOR_RX_01 */ "Packet DMA RX Descriptor, Word 1 (Control)", 362 /* DESCRIPTOR_RX_02 */ "Packet DMA RX Descriptor, Word 2 (Module Header)", 363 /* DESCRIPTOR_RX_03 */ "Packet DMA RX Descriptor, Word 3 (Module Header)", 364 /* DESCRIPTOR_RX_04 */ "Packet DMA RX Descriptor, Word 4 (Module Header)", 365 /* DESCRIPTOR_RX_05 */ "Packet DMA RX Descriptor, Word 5 (Packet Status Fields)", 366 /* DESCRIPTOR_RX_06 */ "Packet DMA RX Descriptor, Word 6 (Packet Status Fields)", 367 /* DESCRIPTOR_RX_07 */ "Packet DMA RX Descriptor, Word 7 (Packet Status Fields)", 368 /* DESCRIPTOR_RX_08 */ "Packet DMA RX Descriptor, Word 8 (Packet Status Fields)", 369 /* DESCRIPTOR_RX_09 */ "Packet DMA RX Descriptor, Word 9 (Packet Status Fields)", 370 /* DESCRIPTOR_RX_10 */ "Packet DMA RX Descriptor, Word 10 (Status)", 371 /* DESCRIPTOR_RX_11 */ "Packet DMA RX Descriptor, Word 11 (Packet Status Fields)", 372 /* DESCRIPTOR_RX_12 */ "Packet DMA RX Descriptor, Word 12 (Packet Status Fields)", 373 /* DESCRIPTOR_RX_13 */ "Packet DMA RX Descriptor, Word 13 (Packet Status Fields)", 374 /* DESCRIPTOR_RX_14 */ "Packet DMA RX Descriptor, Word 14 (Packet Status Fields)", 375 /* DESCRIPTOR_RX_15 */ "Packet DMA RX Descriptor, Word 15 (Status)", 376 /* DESCRIPTOR_TX_00 */ "Packet DMA TX Descriptor, Word 0 (Control)", 377 /* DESCRIPTOR_TX_01 */ "Packet DMA TX Descriptor, Word 1 (Control)", 378 /* DESCRIPTOR_TX_02 */ "Packet DMA TX Descriptor, Word 2 (Module Header)", 379 /* DESCRIPTOR_TX_03 */ "Packet DMA TX Descriptor, Word 3 (Module Header)", 380 /* DESCRIPTOR_TX_04 */ "Packet DMA TX Descriptor, Word 4 (Module Header)", 381 /* DESCRIPTOR_TX_05 */ "Packet DMA TX Descriptor, Word 5 (Unused)", 382 /* DESCRIPTOR_TX_06 */ "Packet DMA TX Descriptor, Word 6 (Unused)", 383 /* DESCRIPTOR_TX_07 */ "Packet DMA TX Descriptor, Word 7 (Unused)", 384 /* DESCRIPTOR_TX_08 */ "Packet DMA TX Descriptor, Word 8 (Unused)", 385 /* DESCRIPTOR_TX_09 */ "Packet DMA TX Descriptor, Word 9 (Unused)", 386 /* DESCRIPTOR_TX_10 */ "Packet DMA TX Descriptor, Word 10 (Status)", 387 /* DESCRIPTOR_TX_11 */ "Packet DMA TX Descriptor, Word 11 (Unused)", 388 /* DESCRIPTOR_TX_12 */ "Packet DMA TX Descriptor, Word 12 (Unused)", 389 /* DESCRIPTOR_TX_13 */ "Packet DMA TX Descriptor, Word 13 (Unused)", 390 /* DESCRIPTOR_TX_14 */ "Packet DMA TX Descriptor, Word 14 (Unused)", 391 /* DESCRIPTOR_TX_15 */ "Packet DMA TX Descriptor, Word 15 (Status)", 392 /* DESTINATION_FORMAT */ "Bit definition for DESTINATION field in various tabel.", 393 /* DESTINATION_MY_STATION */ "Bit Definitions of L2_ENTRY.DESTINATION field if it is considered as a MY_STATION hit.", 394 /* DISCARD_PROC_DROP_VECTOR */ "Bit Definitions of the DISC drop vector.", 395 /* DLB_ECMP_FLOWSET_COV_DEFS */ "defines for DLB ECMP Flowset coverage analysis", 396 /* DLB_ECMP_FLOWSET_TIMESTAMP_PAGE_COV_DEFS */ "defines for DLB ECMP Flowset timestamp page coverage analysis", 397 /* DLB_HGT_FLOWSET_COV_DEFS */ "defines for DLB HGT Flowset coverage analysis", 398 /* DLB_HGT_FLOWSET_TIMESTAMP_PAGE_COV_DEFS */ "defines for DLB HGT Flowset timestamp page coverage analysis", 399 /* DLB_HGT_PORT_LOADING_BUS */ "Description of fields on the DLB_HGT_PORT_LOADING_BUS Bus from EP to IP.", 400 /* DLB_HGT_PORT_QSIZE_BUS */ "Description of fields on the DLB_HGT_PORT_QSIZE_BUS Bus from MMU to IP.", 401 /* DLB_IP_LOADING_BUS */ "Description of fields on the DLB_IP_LOADING_BUS Bus from ip_ep_common to IP.", 402 /* DLB_ITM_PORT_QSIZE_BUS */ "Description of fields on the DLB_ITM_PORT_QSIZE_BUS Bus from MMU to ip_ep_common.", 403 /* DLB_LAG_FLOWSET_COV_DEFS */ "defines for DLB LAG Flowset coverage analysis", 404 /* DLB_LAG_FLOWSET_TIMESTAMP_PAGE_COV_DEFS */ "defines for DLB LAG Flowset timestamp page coverage analysis", 405 /* DLB_PORT_LOADING_BUS */ "Description of fields on the DLB_PORT_LOADING_BUS Bus from EP to IP.", 406 /* DLB_VIRTUAL_ACCOUNTING_LOADING_BUS */ "Description of fields on the DLB_VIRTUAL_ACCOUNTING_LOADING_BUS Bus from IP.", 407 /* DLB_XPE_PORT_QSIZE_BUS */ "Description of fields on the DLB_XPE_PORT_QSIZE_BUS Bus from MMU to IP.", 408 /* DM_TIMESTAMP */ "Position and description of bits in DM_TIMESTAMP Bus From Iarb to Isw2.", 409 /* DOP_BUS */ "DOP Command/Data bus flowing in the pipe", 410 /* DOP_COLLECTION_RESP_WORD */ "The collecction response word prepended to data by DOP", 411 /* DOP_DATA_BUS */ "DOP Data bus flowing in the pipe", 412 /* DQS_TO_DQX_CELL_INFO */ "Position and description of bits in the DQS to DQX Cell INFO.", 413 /* DQS_TO_DQX_REP_INFO */ "Position and description of bits in the DQS to DQX Rep INFO.", 414 /* DQS_TO_RIL_INFO */ "Position and description of bits in the DQS to RIL INFO", 415 /* DQS_TO_TOQ_INFO */ "Position and description of bits in the DQS to TOQ INFO", 416 /* DQX_TO_CCP_INFO_BUS */ "Position and description of bits in the DQX to CCP INFO bus.", 417 /* DQX_TO_CTR_INFO */ "Position and description of bits in the DQX to CTR INFO bus.", 418 /* DROP_VECTOR_1_DOP */ "DROP_VECTOR_1_DOP DOP description.", 419 /* DVP_SWITCHING_CTRLS_ACTION_SET */ "PDD Output Bus generic format", 420 /* E2EFC_TO_CFG_INFO */ "E2EFC to CFG interface format", 421 /* E2EFC_TO_ENQ_INFO_BUS */ "Position and description of bits in the E2EFC to ENQ INFO bus", 422 /* E2E_HOL_STATUS_COV_DEFS */ "defines for E2E_HOL_STATUS coverage analysis", 423 /* EARB_TO_EPOST_CTRL_BUS */ "Bit Definitions of the interface from Earb to Epost.", 424 /* EARB_TO_EPOST_DATA_BUS */ "Data Bus from EP to EDB.", 425 /* ECMP_DLB_ACTION_SET */ "PDD Output Bus generic format", 426 /* ECMP_RH_ACTION_SET */ "PDD Output Bus generic format", 427 /* ECN_ACTION_SET */ "PDD Output Bus generic format", 428 /* EDATABUF_ALGN_TO_BUFFER_CTRL */ "Position and description of bits in Aligner-2-Buffer control-signals", 429 /* EDATABUF_BUFFER_TO_CMPORT_CTRL */ "Position and description of bits in CMport Buffer-2-Port control-signals", 430 /* EDATABUF_BUFFER_TO_GPORT_CTRL */ "Position and description of bits in Gport Buffer-2-Port control-signals", 431 /* EDATABUF_BUFFER_TO_XQPORT_CTRL */ "Position and description of bits in XQport Buffer-2-Port control-signals", 432 /* EDB_TO_IDB_BYTE_COUNT */ "Data bus from EDB to IDB", 433 /* EDB_TO_IDB_DATA */ "Data bus from EDB to IDB", 434 /* EDB_TO_MMU_CREDIT_REQ */ "Credit request from EDB to MMU", 435 /* EDB_TO_PM_1588_PT_BUS */ "Passthrough signals from EP to PM through EDB.", 436 /* EDB_TO_PM_BYTE_COUNT */ "Byte Count from EDB to PM.", 437 /* EDB_TO_PM_DATA_BUS */ "Data Bus from EDB to PM.", 438 /* EDB_TO_PM_PORT_NUM */ "Port Number from EDB to PM.", 439 /* EDITOR_CONTROL_BLOCK_IN_BUS */ "Format for EGR_EVLAN's EDITOR_CONTROL_BLOCK_IN_BUS.", 440 /* EDITOR_DROP_VECTOR_DOP */ "EDITOR_DROP_VECTOR_DOP DOP description.", 441 /* EDITOR_ENGINE_ID_ENCODING_FORMAT */ "EGR_ZONE_*_EDITOR_CONTROL_TCAM_DATA_ONLY/EGR_ZONE_1/3_L2_TAG_CONTROL_PROFILE_INS/RW.ENGINE_ID* encoding format.", 442 /* EDIT_CTRL_ID_ACTION_SET */ "PDD Output Bus generic format", 443 /* EDIT_CTRL_ID_SEL_ENCODING_FORMAT */ "EGR_PKT_FLOW_SELECT_TCAM_DATA_ONLY.ZONE_*_EDIT_CTRL_ID_SEL_A/B/C/D encoding format.", 444 /* EFPMOD_PARITY_STATUS_BUS */ "Position and description of parity-error sigs flowing from EFPMOD->EDATABUF", 445 /* EFPMOD_PKT_ATTR */ "Efpmod pkt mod actions format.", 446 /* EFPMOD_PKT_HDRS */ "Efpmod pkt hdrs format.", 447 /* EFPMOD_PKT_MOD_ACTIONS */ "Efpmod pkt mod actions format.", 448 /* EFPMOD_TO_EPOST_CTRL_BUS */ "Arch shell signals from Efpmod to Epost", 449 /* EFPMOD_TO_EPOST_DATA_BUS */ "Data Bus from Efpmod to Epost.", 450 /* EFPPARS_PARITY_STATUS_BUS */ "Position and description of parity-error sigs flowing from EFPPARS->EDATABUF", 451 /* EFP_CLASSID_B_SELECTOR_SLICE_FORMAT */ "EFP CLASSID_B SELECTOR per SLICE format.", 452 /* EFP_COUNTER_TABLE_COV_DEFS */ "defines for ep pw init counter coverage analysis", 453 /* EFP_EVEN_METER_COV_DEFS */ "defines for efp even meter coverage analysis", 454 /* EFP_KEY1 */ "Position and description of bits in EFP_KEY1 FIELDS", 455 /* EFP_KEY2 */ "Position and description of bits in EFP_KEY2 fields", 456 /* EFP_KEY3 */ "Position and description of bits in EFP_KEY3 fields", 457 /* EFP_KEY4 */ "Position and description of bits in EFP_KEY4 fields", 458 /* EFP_KEY5 */ "Position and description of bits in EFP_KEY5 fields", 459 /* EFP_KEY6 */ "Position and description of bits in EFP_KEY6 fields", 460 /* EFP_KEY7 */ "Position and description of bits in EFP_KEY7 fields", 461 /* EFP_KEY8 */ "Position and description of bits in EFP_KEY8 fields", 462 /* EFP_ODD_METER_COV_DEFS */ "defines for efp odd meter coverage analysis", 463 /* EFP_PARITY_STATUS_BUS */ "Position and description of parity-error sigs flowing from EFP->EDATABUF", 464 /* EFP_REDIRECTION_BUS */ "EFP Redirection Bus", 465 /* EGRESS_ASSP_HEADER */ "FPGA-ASSP Egress Inter-chip Header", 466 /* EGRESS_COMPUTED_FIELD_BUS */ "Egress computed fields for seqence, TTL, TOS. It is only valid for SOP cell.", 467 /* EGRESS_DOP_TOP_FORMAT */ "Top level DOP", 468 /* EGRESS_FIELD_BUS */ "Egress Object Bus flow from MPB to rest of egress pipeline for various process. It is only valid for SOP cell.", 469 /* EGRESS_L2_TAG_BUS */ "Egress L2 Tag Bus for various TAGs. It is only valid for SOP cell.", 470 /* EGRESS_OBJECT_BUS */ "Egress Object Bus flow from MPB to rest of egress pipeline for various process. It is only valid for SOP cell.", 471 /* EGR_ADAPT_1_FIXED_KEY_TABLE_ATTRS_INDEX */ "Egress EGR_ADAPT_1_FIXED_KEY_TABLE_ATTRS index", 472 /* EGR_ADAPT_1_FLEX_KEY_GEN_IN_CONTROL_BUS */ "FlexKeyGen Input Control Bus for EVXLT tables", 473 /* EGR_ADAPT_1_FLEX_KEY_GEN_OUT_BUS */ "FlexKeyGen Output bus EGR_VXLT_1", 474 /* EGR_ADAPT_1_PDD_OUT_BUS */ "PDD Output Bus generic format", 475 /* EGR_ADAPT_2_FLEX_KEY_GEN_IN_CONTROL_BUS */ "FlexKeyGen Input Control Bus for EVXLT tables", 476 /* EGR_ADAPT_2_FLEX_KEY_GEN_OUT_BUS */ "FlexKeyGen Output bus EGR_VXLT_2", 477 /* EGR_ADAPT_2_PDD_OUT_BUS */ "PDD Output Bus generic format", 478 /* EGR_ADAPT_FLEX_KEY_GEN_IN_BUS */ "Egress Flex Keygen Input Bus. It is only valid for SOP cell.", 479 /* EGR_ADAPT_KEYGEN_OBJECT_BUS */ "Egress object portion of Flex Keygen Input Bus. It is only valid for SOP cell.", 480 /* EGR_ADAPT_ZONE_L2_TAGS_STATUS */ "Common Zone l2 tag presence format.", 481 /* EGR_ADAPT_ZONE_L2_TAGS_VALUES */ "Common Zone l2 tags values bus.", 482 /* EGR_DELETE_CONTROL_INDEX */ "Egress Delete Control index", 483 /* EGR_DROP_STATUS_VECTOR */ "EGR counter format for TDBGC vector.", 484 /* EGR_DVP_ATTRIBUTE_EARLY_PDD_OUT_BUS */ "PDD Output Bus generic format", 485 /* EGR_DVP_ATTRIBUTE_PDD_OUT_BUS */ "PDD Output Bus generic format, The following fields are not used:\n FIELD_66 /EGR_FLEX_CTR_1_ACTION_SET: No need for the second counter update action.\n FIELD_4 / HIGIG_CONTROLS_ACTION_SET: It would be good to fix. We have to rely on HG header selection from Next Hop\n FIELD_32 / FLEX_CONTAINER_UPDATE_ACTION_SET:\n ALU is controlled by EGR_PKT_FLOW_SELECT tcam only.\n Enhancing ALU profile selection to egress object table require\n a. 0 vs 1 alu operatio ...", 486 /* EGR_EDB_PRE_BUS */ "The bus that carries pre-signals from EFP->EDATABUF.It arrives 2-cycles early w.r.t packet into EDB.", 487 /* EGR_EFPMOD_MCPE_CNTXT_BUFFER */ "EFPMOD MCPE Context Buffer", 488 /* EGR_EFPMOD_MCPE_EDIT_REQ */ "EFPMOD MCPE EDIT_REQUEST", 489 /* EGR_EFPMOD_MCPE_IN_BUS */ "EFPMOD MCPE IN_BUS format", 490 /* EGR_EL3_MPLS_LABEL_SRC_FORMAT */ "Format for EGR_EL3 MPLS label source.", 491 /* EGR_EL3_TBL_ID */ "Format for EGR_EL3 TBL_ID.", 492 /* EGR_EPMOD_EMOP_BUFFER */ "Bit Definitions of EGR_EPMOD_EMOP_BUFFER.", 493 /* EGR_EVLAN_DEST_ATTR */ "Format for EGR_EVLAN DEST_ATTR.", 494 /* EGR_EVLAN_FCOE_ATTR */ "Format for EGR_EVLAN FCOE_ATTR.", 495 /* EGR_EVLAN_FWD_DOMAIN_ATTR */ "Format for EGR_EVLAN FWD_DOMAIN_ATTR.", 496 /* EGR_EVLAN_QOS_ATTR */ "Format for EGR_EVLAN QOS_ATTR.", 497 /* EGR_EVLAN_SRC_ATTR */ "Format for EGR_EVLAN SRC_ATTR.", 498 /* EGR_EVLAN_STAGE_ATTR */ "Format for EGR_EVLAN STAGE_ATTR.", 499 /* EGR_EVLAN_TBL_ID */ "Format for EGR_EVLAN TBL_ID.", 500 /* EGR_FCOE_DELIMITER_ERROR_FRAMES_TABLE_COV_DEFS */ "", 501 /* EGR_FCOE_FRAMES_COUNTER_COV_DEFS */ "Got 2 counters: FCOE_DELIMITER_ERROR_FRAMES and FCOE_INVALID_CRC_FRAMES", 502 /* EGR_FCOE_INVALID_CRC_FRAMES_TABLE_COV_DEFS */ "", 503 /* EGR_FIELD_EXTRACTION_PROFILE_CONTROL_IDX */ "Format for EGR_FIELD_EXTRACTION_PROFILE_CONTROL index.", 504 /* EGR_FLEX_CONTAINER_UPDATE_PROFILE_INDEX */ "Egress EGR_FLEX_CONTAINER_UPDATE_PROFILE index", 505 /* EGR_FLEX_CTR_ACTION_SET */ "PDD Output Bus generic format", 506 /* EGR_FLEX_CTR_ADDR_DEFINE */ "flex counters memory and register offset", 507 /* EGR_FLEX_CTR_BUS */ "flex counters bus define", 508 /* EGR_FLEX_CTR_BUS_POOL */ "flex counters bus define for a pool", 509 /* EGR_FLEX_CTR_COMPRESSED_PKT_ATTR */ "compressed packet attribute", 510 /* EGR_FLEX_CTR_PKT_ATTR */ "packet attribute", 511 /* EGR_FLEX_CTR_PKT_RES_MAP_INDEX */ "Egress FLEX_CTR_PKT_RES_MAP index", 512 /* EGR_FLEX_CTR_UDF */ "flex counters udf fields definition", 513 /* EGR_FLEX_PREEMPT_LOOKUP */ "flex preempt Lookup. Port IF View", 514 /* EGR_FLEX_PREEMPT_XFR_COUNT */ "Egress EDB Flex XFR COUNT Lookup.On ePkt arrival, provides guidance to ongoing preempt traffic on how many XFR cycles it could use before preemption", 515 /* EGR_FPMOD_EMOP_BUFFER */ "Bit Definitions of EGR_FPMOD_EMOP_BUFFER.", 516 /* EGR_FRAGMENT_ID_TABLE_COV_DEFS */ "defines for ep pw init counter coverage analysis", 517 /* EGR_HW_CTRL_Q_BUS */ "Bit Definitions of EGR_HW_CTRL_Q_BUS.", 518 /* EGR_INT_CN_TO_PKT_ECN_MAPPING_INDEX */ "Egress INT_CN_TO_PKT_ECN Mapping index", 519 /* EGR_INT_CN_UPDATE_INDEX */ "Egress INT_CN_UPDATE index", 520 /* EGR_IP_TUNNEL_MPLS_ENTRY_0_3 */ "Position and description of bits in EGR_IP_TUNNEL for each or the 4 MPLS entries at each table location", 521 /* EGR_IP_TUNNEL_MPLS_ENTRY_0_7 */ "Position and description of bits in EGR_IP_TUNNEL for each of the 8 MPLS entries at each table location.", 522 /* EGR_IP_TUNNEL_MPLS_ENTRY_FORMAT */ "Position and description of bits in EGR_IP_TUNNEL for each or the 4/8 MPLS entries at each table location.", 523 /* EGR_IP_TUNNEL_PDD_OUT_BUS */ "PDD Output Bus generic format", 524 /* EGR_ISID_DOT1P_ATTRIBUTES */ "Format for ISID_DOT1P_ATTRIBUTES.", 525 /* EGR_L2_TAG_CONTROL_PROFILE_DEL_INDEX */ "Egress L2 Tag control profile delete index", 526 /* EGR_L2_TAG_CONTROL_PROFILE_INS_INDEX */ "Egress L2 Tag control profile insert index", 527 /* EGR_L2_TAG_CONTROL_PROFILE_RW_INDEX */ "Egress L2 Tag control profile rewrite index", 528 /* EGR_L3_INTF_EARLY_PDD_OUT_BUS */ "PDD Output Bus generic format", 529 /* EGR_L3_INTF_PDD_OUT_BUS */ "PDD Output Bus generic format", 530 /* EGR_L3_NEXT_HOP_COMMON_COV_DEFS */ "defines for egr l3 next hop table coverage analysis", 531 /* EGR_L3_NEXT_HOP_EARLY_PDD_OUT_BUS */ "PDD Output Bus generic format", 532 /* EGR_L3_NEXT_HOP_PDD_OUT_BUS */ "PDD Output Bus generic format", 533 /* EGR_MPLS_PRI_MAPPING_INDEX */ "Egress EGR_MPLS_PRI_MAPPING index", 534 /* EGR_NAT_PACKET_EDIT_ACTION_PROFILE_FORMAT */ "EGR_NAT_PACKET_EDIT_ACTION_PROFILE format.", 535 /* EGR_NAT_PACKET_EDIT_INFO_FORMAT */ "EGR_NAT_PACKET_EDIT_INFO format.", 536 /* EGR_NAT_PACKET_EDIT_PDD_OUT_BUS */ "PDD Output Bus generic format", 537 /* EGR_PERQ_XMT_COUNTERS_COV_DEFS */ "defines for ep pw init counter coverage analysis", 538 /* EGR_PIPE_PKTINFO */ "Bit Definitions of EGR_PIPE_PKTINFO", 539 /* EGR_PKT_ECN_TO_EXP_MAPPING_INDEX */ "Egress PKT_ECN_TO_EXP_MAPPING index", 540 /* EGR_PKT_FLOW_SELECT_TCAM_DOP_DOP */ "EGR_PKT_FLOW_SELECT_TCAM_DOP_DOP DOP description.", 541 /* EGR_PKT_FLOW_SELECT_TCAM_INDEX_DOP_DOP */ "EGR_PKT_FLOW_SELECT_TCAM_INDEX_DOP_DOP DOP description.", 542 /* EGR_PKT_FLOW_ZONE_SELECT_FORMAT */ "Bit Definitions of Packet Flow Select TCAM Zone selects.", 543 /* EGR_PREEMPT_PKT_LEN_MEM */ "Preempt Pkt Length Memory", 544 /* EGR_QOS_CTRL_TCAM_DOP_DOP */ "EGR_QOS_CTRL_TCAM_DOP_DOP DOP description.", 545 /* EGR_SEQUENCE_NUMBER_TABLE_COV_DEFS */ "defines for ep egr_sequence_number_table coverage analysis", 546 /* EGR_SHAPE */ "Position and description of bits in EP_TO_MMU_SHAPE_Bus", 547 /* EGR_SHAPE_INFO */ "Egress Shape INFO format", 548 /* EGR_SPECIAL_PKT_HANDLING_PROFILE_ID */ "Format for EGR_SPECIAL_PKT_HANDLING_PROFILE index.", 549 /* EGR_STATS_FORMAT */ "EGR_CNTR format for part of TDBGC vector.", 550 /* EGR_TAG_STATUS */ "Tag status.", 551 /* EGR_TAP */ "Format for EGR_EVLAN TAP_TAG_ACTION.", 552 /* EGR_TUNNEL_ECN_ENCAP_TABLE_INDEX */ "Egress Tunnel ECN Encap Table index", 553 /* EGR_VC_AND_SWAP_EARLY_PDD_OUT_BUS */ "PDD Output Bus generic format", 554 /* EGR_VC_AND_SWAP_PDD_OUT_BUS */ "PDD Output Bus generic format. The following fields are reserved: FIELD_1/TUNNEL_PTR_ACTION_SET, FIELD_2/SWITCHING_CTRLS_ACTION_SET, FIELD_4/HIGIG_CONTROLS_ACITON_SET, FIELD_10 /L2_MEMBERSHIP, FIELD_11/ VPLAG_CONTROLS, FIELD_12/MTU_CHECKS, FIELD_66/FLEX_CTR_1_ACTION_SET. The following 2 fields are reserved in TD3 but should be enable in the future: FIELD_32/FLEX_CONTAINER_UPDATE action set, FIELD_6/CLASS_ID_ACTION_SET.", 555 /* EGR_VFT_PRI_MAP_INDEX */ "Egress EGR_VFT_PRI_MAP index", 556 /* EGR_VLAN_ACTION_MASK_PROFILE_FORMAT */ "Format for EGR_VLAN_ACTION_MASK_PROFILE.", 557 /* EGR_VLAN_XLATE_TUNNEL_DATA */ "Define data fields for EGR_VLAN_XLATE when used to derive fields for MiM/L2GRE/VXLAN tunnel encap", 558 /* EGR_VLAN_XLATE_TUNNEL_DATA_DOUBLE */ "Define data fields for EGR_VLAN_XLATE when used to derive fields for MiM/L2GRE/VXLAN tunnel encap", 559 /* EGR_VLAN_XLATE_XLATE_DATA */ "Define data fields for EGR_VLAN_XLATE when used as traditional vlan translation", 560 /* EGR_VLAN_XLATE_XLATE_DATA_DOUBLE */ "Define data fields for EGR_VLAN_XLATE when used as traditional vlan translation", 561 /* EGR_ZONE_DOT1P_MAPPING_TABLE_INDEX */ "Egress EGR_ZONE_1/3_DOT1P_MAPPING_TABLE_* index", 562 /* EGR_ZONE_QOS_MAPPING_TABLE_INDEX */ "Egress EGR_ZONE_1/2/3/4_QOS_MAPPING_TABLE index", 563 /* EHG_HEADER */ "Embedded Higig header sent between EP and port modules", 564 /* EH_SEG_SEL_ENCODING */ "Bit Definitions of the EH_SEG_SEL encoding", 565 /* EH_TYPE_0_FORMAT */ "EH_TYPE_0 fromat", 566 /* EH_TYPE_1_FORMAT */ "EH_TYPE_1 fromat", 567 /* EH_TYPE_2_FORMAT */ "EH_TYPE_2 fromat", 568 /* EL3_0_DOP */ "EL3_0_DOP DOP description.", 569 /* EL3_1_DOP */ "EL3_1_DOP DOP description.", 570 /* EL3_2_DOP */ "EL3_2_DOP DOP description.", 571 /* EL3_3_DOP */ "EL3_3_DOP DOP description.", 572 /* EL3_4_DOP */ "EL3_4_DOP DOP description.", 573 /* EL3_5_DOP */ "EL3_5_DOP DOP description.", 574 /* EL3_DOP */ "Position and description of bits in EL3_DOP DOP chain", 575 /* EL3_EMOP_BUFFER */ "Format for EL3 EMOP buffer.", 576 /* EL3_FC */ "Format for FCOE EOF.", 577 /* EL3_OBJECT_BUS */ "El3 internal Object Bus .", 578 /* EL3_TIMESTAMP_ACTION_SET */ "El3 Timestamp action set .", 579 /* EMC_TO_DEQ_RD_REQ_COMPLETE_INFO */ "EMC to DEQ Cell read complete", 580 /* EMC_TO_DEQ_RD_REQ_INFO */ "EMC to CI Read Request Info", 581 /* EMC_TO_ITE_WR_REQ_PKT_COMPLETE_INFO */ "EMC to ITE packet write complete", 582 /* EMC_TO_LLS_INFO */ "Position and description of bits", 583 /* ENGINE_CTRL_DOP_DOP */ "ENGINE_CTRL_DOP_DOP DOP description.", 584 /* ENQS_CT_BYP */ "Position and description of bits in the Cut-through bypass", 585 /* ENQS_PIPE */ "Position and description of bits in the ENQS pipeline", 586 /* ENQS_TO_DEQ_ASF_INFO */ "ENQS to DEQ ASF cell info", 587 /* ENQS_TO_ENQX_INFO */ "Position and description of bits sent from ENQS to ENQX.", 588 /* ENQS_TO_TOQ_CELLLINK_WDATA */ "Position and description of bits", 589 /* ENQX_TO_CTR_TX_PKT_INFO */ "ENQX to CTR TX packet info", 590 /* ENQX_TO_PQE_INFO */ "ENQX to PQE info", 591 /* ENQX_TO_TCB_DROP_TYPE */ "", 592 /* ENQX_TO_TCB_MPB_INFO */ "", 593 /* ENQX_TO_TOQ_CELLLINK_WDATA */ "Position and description of bits", 594 /* ENQX_TO_TOQ_SRCPORT_INFO */ "Position and description of bits", 595 /* ENQ_CT_DATA_DELAY_INFO */ "ENQ CT logic data delay info", 596 /* ENQ_DEF */ "enq specific defines", 597 /* ENQ_DELAY_HOLD_INFO */ "Position and description of bits in the ENQ Delay for Fragm purge INFO bus", 598 /* ENQ_EXT_PTR */ "Internal packet pointer", 599 /* ENQ_INT_PTR */ "Internal packet pointer", 600 /* ENQ_PBI_SOP_INFO */ "Position and description of bits when storing SOP info from PBI.", 601 /* ENQ_PIPE */ "internal defines for cell data passed through enq pipe this is specific to enq block", 602 /* ENQ_POST_PAC_SAE_SRCPORT_CTXT_FIFO */ "Store the EOP wr-data from MMU_ENQ_SRC_PORT_STATE_0/1/2 and read on SAE slot in post-pac stage", 603 /* ENQ_PREV_CELL_INFO */ "enq specific defines for previous cell information", 604 /* ENQ_SOP_CELLHDR */ "enq specific defines for previous cell information", 605 /* ENQ_SOP_INFO */ "enq specific defines for previous cell information", 606 /* ENQ_SRC_CTXT_FIFO */ "", 607 /* ENQ_ST7_TO_ENQOUT */ "ENQ to PQE info", 608 /* ENQ_TOP_PIPE_TO_CT_INFO */ "Position and description of bits internal of ENQ per pipe info to CT logic.", 609 /* ENQ_TO_ADM_INFO */ "ENQ to ADM per cell bus", 610 /* ENQ_TO_ADM_PIPE */ "internal defines for cell data passed through ENQ_TO_ADM_PIPE pipe this is specific to enq block", 611 /* ENQ_TO_AGING_PKT_PTR */ "ENQ to AGING pointer info", 612 /* ENQ_TO_CLINKE_INFO */ "Position and description of bits", 613 /* ENQ_TO_CLINKI_INFO */ "Position and description of bits", 614 /* ENQ_TO_CTR_INFO */ "Position and description of bits", 615 /* ENQ_TO_CTR_TX_PKT_INFO */ "ENQ to CTR TX packet info", 616 /* ENQ_TO_DEQ_ASF_INFO */ "ENQ to DEQ ASF cell info", 617 /* ENQ_TO_E2EFC_INFO_BUS */ "Position and description of bits in the ENQ to E2EFC INFO bus", 618 /* ENQ_TO_E2EFC_QEN_PURGE_INFO */ "Position and description of bits", 619 /* ENQ_TO_INTFI_INFO */ "Position and description of bits", 620 /* ENQ_TO_ITE_CTRL_INFO */ "Position and description of bits", 621 /* ENQ_TO_ITE_EMA_INFO */ "Position and description of bits", 622 /* ENQ_TO_MTRI_INC_INFO */ "Position and description of bits", 623 /* ENQ_TO_PQE_INFO */ "ENQ to PQE info", 624 /* ENQ_TO_QCN_INFO */ "ENQ to QCN packet info", 625 /* ENQ_TO_RQE_INFO */ "ENQ_TO_RQE_INFO", 626 /* ENQ_TO_RQE_INT_INFO */ "Position and description of bits", 627 /* ENQ_TO_RQE_RDDATA_INFO */ "Position and description of bits", 628 /* ENQ_TO_RQE_UC_INFO */ "Position and description of bits", 629 /* ENQ_TO_THDI_EMA_INFO */ "Position and description of bits", 630 /* ENQ_TO_THDI_EXT_INFO */ "Position and description of bits", 631 /* ENQ_TO_THDI_INT_INFO */ "Position and description of bits", 632 /* ENQ_TO_THDI_QEN_INFO */ "Position and description of bits", 633 /* ENQ_TO_THDI_QEN_PURGE_INFO */ "Position and description of bits", 634 /* ENQ_TO_THDI_RQE_INFO */ "Position and description of bits", 635 /* ENQ_TO_THDO_EMA_INFO */ "Position and description of bits", 636 /* ENQ_TO_THDO_RQEE_INFO */ "Position and description of bits", 637 /* ENQ_TO_THDO_RQEI_INFO */ "Position and description of bits", 638 /* ENQ_TO_THDO_RQEQ_INFO */ "Position and description of bits", 639 /* ENQ_TO_TOQ_CELLLINK_WDATA */ "Position and description of bits in the ENQ to TOQ SOURCE PORT INFO bus", 640 /* ENQ_TO_TOQ_SRCPORT_INFO */ "Position and description of bits in the ENQ to TOQ SOURCE PORT INFO bus", 641 /* ENQ_TO_TOQ_WCI_INFO */ "Position and description of bits", 642 /* ENQ_TO_TOQ_XQ_WR_INFO */ "Position and description of bits in the ENQ to TOQ XQ WR INFO bus", 643 /* ENQ_TO_WAMU_INFO */ "Position and description of bits in the ENQ to WAMU INFO bus", 644 /* EOP_BUFFER */ "Bit Definitions of the EOP_BUFFER", 645 /* EOP_BUFFER_B_COV_DEFS */ "defines for EOP_BUFFER_B coverage analysis", 646 /* EOP_BUFFER_MTU */ "Bit Definitions of EOP_BUFFER_MTU.", 647 /* EP2CXLP_IF */ "define for single XLPORT interface", 648 /* EPFS_0_DOP */ "EPFS_0_DOP DOP description.", 649 /* EPFS_1_DOP */ "EPFS_1_DOP DOP description.", 650 /* EPFS_DOP */ "Position and description of bits in EPFS_DOP DOP chain", 651 /* EPFS_EMOP_BUFFER */ "Format for EPFS EMOP buffer.", 652 /* EPMOD_0_DOP */ "EPMOD_0_DOP DOP description.", 653 /* EPMOD_1_DOP */ "EPMOD_1_DOP DOP description.", 654 /* EPMOD_DOP */ "Position and description of bits in EPMOD_DOP DOP chain", 655 /* EPMOD_PARITY_STATUS_BUS */ "Position and description of parity-error sigs flowing from EPMOD->EDATABUF", 656 /* EPOST_EMOP_BUFFER */ "Epost eop buffer format", 657 /* EPRG_FIELDS */ "Position and description of bits in EPRG register file", 658 /* EP_CPU_OP */ "EP CPU OP Bus Format.", 659 /* EP_CPU_OPCODES */ "Bit Definitions of the CPU Opcodes", 660 /* EP_EFPPARS_CONTAINER_BASE */ "Base format for efppars container command", 661 /* EP_EGRESS_STATS_COUNTER_COV_DEFS */ "defines for ep pw init counter coverage analysis", 662 /* EP_EGR_COUNTER_VECTOR */ "Bit Definitions of the Egress counter vector.", 663 /* EP_EGR_DROP_VECTOR */ "Bit Definitions of the Egr drop vector.", 664 /* EP_EVXLT_KEY_TYPE */ "Egress-VLAN Xlate table Key-Types", 665 /* EP_HW_CTRL */ "EP HW Ctrl Bus Format.", 666 /* EP_PARSER0_HFE_CMD_POLICY_DATA */ "", 667 /* EP_PARSER0_HFE_CONSTANTS */ "This defines constants for HFE", 668 /* EP_PARSER0_HFE_CONTROLS */ "", 669 /* EP_PARSER0_HFE_CONT_PROFILE */ "", 670 /* EP_PARSER0_HFE_IN_BUS */ "", 671 /* EP_PARSER0_HFE_MUX_CONTROLS */ "", 672 /* EP_PARSER0_HFE_MUX_IN_BUS */ "", 673 /* EP_PARSER0_HFE_MUX_OUT_BUS */ "", 674 /* EP_PARSER0_HFE_OUT_BUS */ "", 675 /* EP_PARSER0_HFE_POLICY_COMMAND_A */ "", 676 /* EP_PARSER0_HFE_POLICY_COMMAND_B */ "", 677 /* EP_PARSER0_HFE_POLICY_COMMAND_C */ "", 678 /* EP_PARSER0_HFE_POLICY_COMMAND_D */ "", 679 /* EP_PARSER0_HFE_POLICY_TABLE_DATA */ "", 680 /* EP_PARSER0_HVE_TRIGGERS */ "EP Parser0 HVE Triggers.", 681 /* EP_PARSER1_HFE_CMD_POLICY_DATA */ "", 682 /* EP_PARSER1_HFE_CONSTANTS */ "This defines constants for HFE", 683 /* EP_PARSER1_HFE_CONTROLS */ "", 684 /* EP_PARSER1_HFE_CONT_PROFILE */ "", 685 /* EP_PARSER1_HFE_IN_BUS */ "", 686 /* EP_PARSER1_HFE_MUX_CONTROLS */ "", 687 /* EP_PARSER1_HFE_MUX_IN_BUS */ "", 688 /* EP_PARSER1_HFE_MUX_OUT_BUS */ "", 689 /* EP_PARSER1_HFE_OUT_BUS */ "", 690 /* EP_PARSER1_HFE_POLICY_COMMAND_A */ "", 691 /* EP_PARSER1_HFE_POLICY_COMMAND_B */ "", 692 /* EP_PARSER1_HFE_POLICY_COMMAND_C */ "", 693 /* EP_PARSER1_HFE_POLICY_COMMAND_D */ "", 694 /* EP_PARSER1_HFE_POLICY_TABLE_DATA */ "", 695 /* EP_PARSER1_HVE_TRIGGERS */ "EP Parser0 HVE Triggers.", 696 /* EP_PARSER2_HFE_CMD_POLICY_DATA */ "", 697 /* EP_PARSER2_HFE_CONSTANTS */ "This defines constants for HFE", 698 /* EP_PARSER2_HFE_CONT_PROFILE */ "", 699 /* EP_PARSER2_HFE_MUX_CONTROLS */ "", 700 /* EP_PARSER2_HFE_MUX_IN_BUS */ "", 701 /* EP_PARSER2_HFE_MUX_OUT_BUS */ "", 702 /* EP_PARSER2_HFE_POLICY_COMMAND_A */ "", 703 /* EP_PARSER2_HFE_POLICY_COMMAND_B */ "", 704 /* EP_PARSER2_HFE_POLICY_COMMAND_C */ "", 705 /* EP_PARSER2_HFE_POLICY_COMMAND_D */ "", 706 /* EP_PARSER2_HFE_POLICY_TABLE_DATA */ "", 707 /* EP_PW_INIT_COUNTER_COV_DEFS */ "defines for ep pw init counter coverage analysis", 708 /* EP_REG */ "EP REG format", 709 /* EP_TO_CLP_IF_BUS */ "flex counters input format", 710 /* EP_TO_CM_CPU_DMA_BUS */ "EP to CMICx for the CPU DMA header fields", 711 /* EP_TO_CPU_COMPOSITES_BUS */ "Egress Pipeline to CMIC/CPU HDR format", 712 /* EP_TO_CPU_HDR */ "Egress Pipeline to CMIC HDR format", 713 /* EP_TO_EDB_CTRL_BUS */ "Ctrl Bus from EP to EDB.", 714 /* EP_TO_EDB_DATA_BUS */ "Data Bus from EP to EDB.", 715 /* EP_TO_EDB_EARLY_CTRL_BUS */ "Early Ctrl Bus from EP to EDB. These signals are sent 4 cycles ahead of the packet cell data", 716 /* EP_TO_GPORT_CTRL_BUS */ "Position and description of bits in ep_to_gp0/1/2_pkt_ctrl", 717 /* EP_TO_MMU_REDIRECTION_BUS */ "EP to MMU Redirection Bus", 718 /* EP_TO_PORT_1588_CTRL_BUS */ "Position and description of bits in ep_to_xgp0/1/2/3_pkt_ctrl", 719 /* EP_TO_QGPORT_CTRL_BUS */ "Position and description of bits in EP_TO_QGPORT_CTRL_BUS", 720 /* EP_TO_SPORT_CTRL_BUS */ "Position and description of bits in ep_to_sp_pkt_ctrl", 721 /* EP_TO_XGPORT_CTRL_BUS */ "Position and description of bits in ep_to_xgp0/1/2/3_pkt_ctrl", 722 /* EP_TO_XPORT_CTRL_BUS */ "Position and description of bits in EP_TO_XPORT_CTRL_BUS", 723 /* EP_TO_XQPORT_CTRL_BUS */ "Position and description of bits in ep_to_xp0/1/2/3_pkt_ctrl", 724 /* EP_VLAN_XLATE_1_DATA */ "Format for EP_VLAN_XLATE_1 DATA.", 725 /* EP_VLAN_XLATE_KEY */ "Format for EP_VLAN_XLATE KEY.", 726 /* ESMIF_COUNTER */ "Bit Definitions of the ESMIF counter vector", 727 /* ESMIF_DROP */ "Bit Definitions of the ESMIF drop vector", 728 /* ESM_ADM_CTRL_FIFO */ "IESMIF Admission Control FIFO Format.", 729 /* ESM_AUX1_FIFO */ "IESMIF Aux1 FIFO Format.", 730 /* ESM_COUNTER_SET */ "Position and description of bits in the esm flex counter set", 731 /* ESM_FP_CNTR_REQ */ "Position and description of bits in Update ext_fp_cntr req to ESM", 732 /* ESM_FULL_IPV6_ACL_KEY */ "FGH424 Full IPV6 ACL Key description", 733 /* ESM_IPV4_ACL144_KEY */ "IPV4_ACL144 Key description", 734 /* ESM_IPV4_ACL_7K_KEY */ "Y288 IPV4 ACL Key description", 735 /* ESM_IPV4_ACL_KEY */ "B288 IPV4 ACL Key description", 736 /* ESM_IPV6_ACL144_KEY */ "IPV6_ACL144 Key description", 737 /* ESM_KEYGEN_F10_MUX_SEL */ "Mux Select encodings for ESM Key Generation Field F10. Width of F10 is 128 bits. If the encoding is programmed other than the listed below, logic will behave as if FIELD_NOT_PRESENT is set.", 738 /* ESM_KEYGEN_F11_MUX_SEL */ "Mux Select encodings for ESM Key Generation Field F11. Width of F11 is 128 bits. If the encoding is programmed other than the listed below, logic will behave as if FIELD_NOT_PRESENT is set.", 739 /* ESM_KEYGEN_F1_MUX_SEL */ "Mux Select encodings for ESM Key Generation Field F1. Width of F1 is 128 bits. If the encoding is programmed other than the listed below, logic will behave as if FIELD_NOT_PRESENT is set.", 740 /* ESM_KEYGEN_F3_MUX_SEL */ "Mux Select encodings for ESM Key Generation Field F3. Width of F3 is 16 bits. If the encoding is programmed other than the listed below, logic will behave as if FIELD_NOT_PRESENT is set.", 741 /* ESM_KEYGEN_F4_MUX_SEL */ "Mux Select encodings for ESM Key Generation Field F4. Width of F4 is 16 bits. If the encoding is programmed other than the listed below, logic will behave as if FIELD_NOT_PRESENT is set.", 742 /* ESM_KEYGEN_F5_MUX_SEL */ "Mux Select encodings for ESM Key Generation Field F5. Width of F5 is 16 bits. If the encoding is programmed other than the listed below, logic will behave as if FIELD_NOT_PRESENT is set.", 743 /* ESM_KEYGEN_F6_MUX_SEL */ "Mux Select encodings for ESM Key Generation Field F6. Width of F6 is 32 bits. If the encoding is programmed other than the listed below, logic will behave as if FIELD_NOT_PRESENT is set.", 744 /* ESM_KEYGEN_F7_MUX_SEL */ "Mux Select encodings for ESM Key Generation Field F7. Width of F7 is 32 bits. If the encoding is programmed other than the listed below, logic will behave as if FIELD_NOT_PRESENT is set.", 745 /* ESM_KEYGEN_F8_MUX_SEL */ "Mux Select encodings for ESM Key Generation Field F8. Width of F8 is 64 bits. If the encoding is programmed other than the listed below, logic will behave as if FIELD_NOT_PRESENT is set.", 746 /* ESM_KEYGEN_F9_MUX_SEL */ "Mux Select encodings for ESM Key Generation Field F9. Width of F9 is 128 bits. If the encoding is programmed other than the listed below, logic will behave as if FIELD_NOT_PRESENT is set.", 747 /* ESM_KEYGEN_FLAGS_MUX_SEL */ "Bit Selects in FLAGS Field. Selectable width of FLAGS is 16 bits.", 748 /* ESM_L2_ACL144_KEY */ "L2_ACL144 Key description", 749 /* ESM_L2_ACL_7K_KEY */ "X274 L2 ACL Key description", 750 /* ESM_L2_ACL_KEY */ "A274 L2 ACL Key description", 751 /* ESM_L2_IPV4_ACL_KEY */ "M408 L2+IPV4 ACL Key description", 752 /* ESM_L2_IPV6_ACL_KEY */ "L432 L2+IPV6 ACL Key description", 753 /* ESM_RSP_WORD_0_ERR_INFO */ "Description of bits in ERR_INFO field of RSP_WORD_0 driven by ESM", 754 /* ESM_SEARCH_REQUEST */ "Position and description of bits in Search Request to ESM", 755 /* ESM_SEARCH_RESULTS */ "Position and description of bits in Search Results from ESM", 756 /* ESM_SHORT_IPV6_ACL_KEY */ "CDE360 Short IPV6 ACL Key description", 757 /* ESM_SVC_SET */ "Position and description of bits in the esm svc action set", 758 /* ES_TO_DEQ_PORT_DEMAND_ST */ "Position and description of bits in the ES TO DEQ Port Demand State bus", 759 /* ETAG_COMPOSITES */ "Zone l2 tag presence format.", 760 /* ETAG_HDR */ "4BYTES OF ETAG HEADER AFTER ETHERTYPE.", 761 /* ETHERTYPE */ "EtherType is a two-octet field in an Ethernet frame. It is used to indicate which protocol is encapsulated in the payload of an Ethernet Frame.", 762 /* ETH_II_DOUBLE_TAGGED_HDR */ "Ethernet 2 single tagged header specification", 763 /* ETH_II_SINGLE_TAGGED_HDR */ "Ethernet 2 single tagged header specification", 764 /* ETH_II_UNTAGGED_HDR */ "Ethernet 2 untagged specification", 765 /* ETRAP_FILTER_0_COV_DEFS */ "Elephant trap bloom filter counter", 766 /* ETRAP_FILTER_1_COV_DEFS */ "Elephant trap bloom filter counter", 767 /* ETRAP_FILTER_2_COV_DEFS */ "Elephant trap bloom filter counter", 768 /* ETRAP_FILTER_3_COV_DEFS */ "Elephant trap bloom filter counter", 769 /* ETRAP_FLOW_CNTRL_LEFT_COV_DEFS */ "Elephant trap flow control and state", 770 /* ETRAP_FLOW_CNTRL_RIGHT_COV_DEFS */ "Elephant trap flow control and state", 771 /* ETRAP_FLOW_COUNT */ "Bit Definitions of ETRAP_FLOW_COUNT format.", 772 /* ETRAP_FLOW_COUNT_LEFT_COV_DEFS */ "Elephant trap flow count", 773 /* ETRAP_FLOW_COUNT_RIGHT_COV_DEFS */ "Elephant trap flow count", 774 /* ETRAP_FLOW_CTRL */ "Bit Definitions of ETRAP_FLOW_CTRL format.", 775 /* ETRAP_FLOW_HASH */ "Bit Definitions of ETRAP_FLOW_HASH format.", 776 /* ETRAP_FLOW_HASH_L0_COV_DEFS */ "Elephant trap flow table (hash portion).", 777 /* ETRAP_FLOW_HASH_L1_COV_DEFS */ "Elephant trap flow table (hash portion).", 778 /* ETRAP_FLOW_HASH_L2_COV_DEFS */ "Elephant trap flow table (hash portion).", 779 /* ETRAP_FLOW_HASH_L3_COV_DEFS */ "Elephant trap flow table (hash portion).", 780 /* ETRAP_FLOW_HASH_L4_COV_DEFS */ "Elephant trap flow table (hash portion).", 781 /* ETRAP_FLOW_HASH_R0_COV_DEFS */ "Elephant trap flow table (hash portion).", 782 /* ETRAP_FLOW_HASH_R1_COV_DEFS */ "Elephant trap flow table (hash portion).", 783 /* ETRAP_FLOW_HASH_R2_COV_DEFS */ "Elephant trap flow table (hash portion).", 784 /* ETRAP_FLOW_HASH_R3_COV_DEFS */ "Elephant trap flow table (hash portion).", 785 /* ETRAP_FLOW_HASH_R4_COV_DEFS */ "Elephant trap flow table (hash portion).", 786 /* ETRAP_HASH_SAVE */ "Bit Definitions of ETRAP_HASH_SAVE memory. Saves SOP signals for use on EOP internally.", 787 /* ETRAP_IN */ "Bit Definitions of Etrap Input Signals.", 788 /* ETRAP_OUT */ "Results for Etrap processed packets.", 789 /* ETU_CP_MEM_ACC_REQ */ "table read/write request bus", 790 /* ETU_CP_XLAT_RESULT */ "control plane translation result format", 791 /* ETU_TX_PIPE_CTL_FIFO */ "format for etu_tx_pipe_ctl_fifo input", 792 /* EVLAN_DOP */ "Position and description of bits in EVLAN_DOP DOP chain", 793 /* EXACT_MATCH_2_DATA */ "Format for EXACT_MATCH_2 DATA.", 794 /* EXACT_MATCH_4_DATA */ "Format for EXACT_MATCH_4 DATA.", 795 /* EXACT_MATCH_CTRL */ "Exact Match signals carried from IFWD to IRSEL1", 796 /* EXACT_MATCH_DATA */ "Exact Match signals carried from the Exact Match Results to the IFP", 797 /* EXACT_MATCH_DOP */ "EXACT_MATCH_DOP DOP description.", 798 /* EXACT_MATCH_KEY */ "Format for EXACT_MATCH_2 and EXACT_MATCH_4 KEYs.", 799 /* EXACT_MATCH_KEY_DOP */ "EXACT_MATCH_KEY_DOP DOP description.", 800 /* EXACT_MATCH_KEY_SPECIAL */ "Special format for ism_lp_ctl.v module.", 801 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_DATA_FORMAT */ "format for EXACT_MATCH_LOGICAL_TABLE_SELECT data", 802 /* EXACT_MATCH_LOGICAL_TABLE_SELECT_TCAM_FORMAT */ "format for EXACT_MATCH_LOGICAL_TABLE_SELECT TCAM", 803 /* EXACT_MATCH_LOOKUP_STATUS */ "Exact Match Lookup STatus as defined the spec", 804 /* EXACT_MATCH_LTS_DOP */ "EXACT_MATCH_LTS_DOP DOP description.", 805 /* EXACT_MATCH_PDD_OUT_BUS */ "PDD Output Bus generic format", 806 /* EXACT_MATCH_POLICY */ "Exact Match Policy", 807 /* EXACT_MATCH_POLICY_MODE128 */ "Exact Match Policy", 808 /* EXACT_MATCH_POLICY_MODE160 */ "Exact Match Policy", 809 /* EXACT_MATCH_POLICY_MODE320 */ "Exact Match Policy", 810 /* EXACT_MATCH_REDIRECT_SET */ "Bit Definitions of the Redirection Field in IFP Policy Table", 811 /* EXACT_MATCH_RESULT_BUS */ "Exact Match signals carried from IFWD to IRSEL1", 812 /* EXACT_MATCH_TO_FP_KEY_SEL_BUS */ "Exact Match signals carried from Exact Match to FP Lookup", 813 /* EXPORT_FIFO_DATA */ "details of one entry of export fifo", 814 /* EXPORT_TIMER_BUS */ "Export timer bus from AGE block", 815 /* EXTENDED_VIEW_L3_OIF_ACTION_SET */ "PDD Output Bus generic format", 816 /* EXTENDED_VIEW_MACDA_ACTION_SET */ "PDD Output Bus generic format", 817 /* EXTRACTION_CTRL_ID_ACTION_SET */ "PDD Output Bus generic format", 818 /* EXT_AD_1X */ "format for ext_assoc_data - 35b", 819 /* EXT_AD_2X */ "format for ext_assoc_data - 70b", 820 /* EXT_AD_3X */ "format for ext_assoc_data - 105b", 821 /* EXT_AD_4X */ "format for ext_assoc_data - 140b", 822 /* EXT_AD_6X */ "format for ext_assoc_data - 210b", 823 /* EXT_AD_REQ_ADDR */ "ESMIF ADDR Format.", 824 /* EXT_HBIT_CMD */ "format for ext_hbit_cmd_wdata", 825 /* EXT_TCAM_REQ_WDATA */ "Request External TCAM", 826 /* EXT_TCAM_RSP_WDATA */ "TCAM RESPONSE FORMAT", 827 /* FCOE_ACTION_SET */ "PDD Output Bus generic format", 828 /* FCOE_HDR */ "FCOE header specification", 829 /* FCOE_SOF_HDR */ "FCOE SOF header specification", 830 /* FCOE_STANDARD_HDR */ "FCOE header specification", 831 /* FCOE_VFT_HDR */ "FCOE VTF header specification", 832 /* FIELD_BUS_MERGE_PROFILE_0_INDEX */ "FIELD_BUS_MERGE_PROFILE index", 833 /* FIELD_BUS_MERGE_PROFILE_INDEX */ "FIELD_BUS_MERGE_PROFILE index", 834 /* FIFO_RD_DMA_ERROR_VEC */ "Error_vec indication in CMIC FIFO RD DMA operation", 835 /* FIXED_ACTION_SET */ "PDD Output Bus generic format", 836 /* FIXED_DATA */ "Fixed Data Format.", 837 /* FLEXKEY_MEMSEL */ "Packet Fields Bus", 838 /* FLEX_ASSIGNMENT_CTRL_FORMAT */ "Flex Flow ASSIGNMENT_CTRL Format.", 839 /* FLEX_BIN_HASH_PROFILE_FORMAT */ "Flex RTAG7 hash bin profile Format.", 840 /* FLEX_CONTAINER_UPDATE_ACTION_SET */ "PDD Output Bus generic format", 841 /* FLEX_CTR_ACTION_BUS_POOL */ "flex counters action bus defines for a pool", 842 /* FLEX_CTR_ACTION_SET */ "PDD Output Bus generic format", 843 /* FLEX_CTR_COV_DEFS */ "defines for coverage analysis", 844 /* FLEX_CTR_DEFINES */ "Misc Defines for flex counter", 845 /* FLEX_CTR_FT_READ_DATA */ "flex counters bus define for a pool", 846 /* FLEX_CTR_IN_BUS */ "flex counters input format", 847 /* FLEX_CTR_OPCODE_BUS_POOL */ "flex counters opcode bus defines for a pool", 848 /* FLEX_CTR_OUTBUS */ "flex counters output format", 849 /* FLEX_CTR_SIDE_OUTBUS */ "flex counters input format", 850 /* FLEX_EDITOR_COMPOSITES_BUS */ "Field bus used for flex editor hdr construction/rewrite", 851 /* FLEX_EDITOR_COMPUTED_FIELD_BUS */ "Egress computed fields for seqence, TTL, TOS. It is only valid for SOP cell.", 852 /* FLEX_EDITOR_DELETE_COMMAND_BASE */ "", 853 /* FLEX_EDITOR_EDIT_ACTION_IN_BUS */ "Complete Input bus used for edit action block within flex editor", 854 /* FLEX_EDITOR_EDIT_ACTION_OUT_BUS */ "Complete Output bus used for edit action block within flex editor", 855 /* FLEX_EDITOR_EDIT_HDR_GEN_IN_BUS */ "Complete Input bus used for edit header generation block within flex editor", 856 /* FLEX_EDITOR_EDIT_HDR_GEN_OUT_BUS */ "Complete Output bus used for edit header generation block within flex editor", 857 /* FLEX_EDITOR_EDIT_ID_DEL_SET_BASE */ "", 858 /* FLEX_EDITOR_EDIT_ID_DEL_TABLE */ "", 859 /* FLEX_EDITOR_EDIT_ID_INS_1_TABLE */ "", 860 /* FLEX_EDITOR_EDIT_ID_INS_2_TABLE */ "", 861 /* FLEX_EDITOR_EDIT_ID_INS_SET_BASE */ "", 862 /* FLEX_EDITOR_EDIT_ID_RW_SET_BASE */ "", 863 /* FLEX_EDITOR_EDIT_ID_RW_TABLE */ "", 864 /* FLEX_EDITOR_EDIT_PKT_MOD_IN_BUS */ "Complete Input bus used for edit packet modification block within flex editor", 865 /* FLEX_EDITOR_EDIT_PKT_MOD_OUT_BUS */ "Complete Output bus used for edit packet modification block within flex editor", 866 /* FLEX_EDITOR_EH_TYPE_0_FORMAT */ "EH_TYPE_0 fromat", 867 /* FLEX_EDITOR_EH_TYPE_1_FORMAT */ "EH_TYPE_1 fromat", 868 /* FLEX_EDITOR_EH_TYPE_2_FORMAT */ "EH_TYPE_2 fromat", 869 /* FLEX_EDITOR_ENGINE_VALID */ "", 870 /* FLEX_EDITOR_ERROR_VECTOR_FORMAT */ "Error conditions in Flex editor", 871 /* FLEX_EDITOR_EXTRACTED_PKT_SET_BASE */ "", 872 /* FLEX_EDITOR_FIELD_16BIT_COMMAND_BASE */ "", 873 /* FLEX_EDITOR_FIELD_32BIT_COMMAND_BASE */ "", 874 /* FLEX_EDITOR_FIELD_BUS */ "Egress Object Bus flow from MPB to rest of egress pipeline for various process. It is only valid for SOP cell.", 875 /* FLEX_EDITOR_FIXED_HDR_L2_PROFILE_PTR_SET_BASE */ "", 876 /* FLEX_EDITOR_FIXED_HDR_L2_PROFILE_TABLE */ "", 877 /* FLEX_EDITOR_FIXED_HDR_L3_PROFILE_PTR_SET_BASE */ "", 878 /* FLEX_EDITOR_FIXED_HDR_L3_PROFILE_TABLE */ "", 879 /* FLEX_EDITOR_FIXED_HDR_LOOPBACK_PROFILE_PTR_SET_BASE */ "", 880 /* FLEX_EDITOR_FIXED_HDR_LOOPBACK_PROFILE_TABLE */ "", 881 /* FLEX_EDITOR_FIXED_HDR_NEXT_PROTO_ID_SET_BASE */ "", 882 /* FLEX_EDITOR_FIXED_HDR_NEXT_PROTO_TABLE */ "", 883 /* FLEX_EDITOR_FIXED_HDR_PROFILE_PTR_SET_BASE */ "", 884 /* FLEX_EDITOR_FIXED_HDR_SYS_PROFILE_PTR_SET_BASE */ "", 885 /* FLEX_EDITOR_FIXED_HDR_SYS_PROFILE_TABLE */ "", 886 /* FLEX_EDITOR_FIXED_HDR_TUNNEL_PROFILE_PTR_SET_BASE */ "", 887 /* FLEX_EDITOR_FIXED_HDR_TUNNEL_PROFILE_TABLE */ "", 888 /* FLEX_EDITOR_FIXED_L2_HEADER_SET_BASE */ "", 889 /* FLEX_EDITOR_FIXED_L3_HEADER_SET_BASE */ "", 890 /* FLEX_EDITOR_FIXED_SYS_HEADER_SET_BASE */ "", 891 /* FLEX_EDITOR_FIXED_TUNNEL_HEADER_SET_BASE */ "", 892 /* FLEX_EDITOR_FLEX_HDR_16BIT_FS_PROFILE_TABLE */ "", 893 /* FLEX_EDITOR_FLEX_HDR_32BIT_FS_PROFILE_TABLE */ "", 894 /* FLEX_EDITOR_FLEX_HDR_ALU_COMMAND_BASE */ "", 895 /* FLEX_EDITOR_FLEX_HDR_ALU_PROFILE_TABLE */ "", 896 /* FLEX_EDITOR_FLEX_HDR_FIELD_BUS */ "Flex header field bus after extraction in Edit Action block to Flex Header Engine.", 897 /* FLEX_EDITOR_FLEX_HDR_FIELD_SELECT_COMMAND_BASE */ "", 898 /* FLEX_EDITOR_FLEX_HDR_HC_PROFILE_TABLE */ "", 899 /* FLEX_EDITOR_FLEX_HDR_NEXT_PROTO_ID_SET_BASE */ "", 900 /* FLEX_EDITOR_FLEX_HDR_NEXT_PROTO_TABLE */ "", 901 /* FLEX_EDITOR_FLEX_HDR_OW_PROFILE_TABLE */ "", 902 /* FLEX_EDITOR_FLEX_HDR_PROFILE_PTR_SET_BASE */ "", 903 /* FLEX_EDITOR_FLEX_HDR_PROFILE_TABLE */ "", 904 /* FLEX_EDITOR_FLEX_HDR_USER_FIELD_FORMAT */ "Register formats for C code", 905 /* FLEX_EDITOR_FLEX_HEADER_SET_BASE */ "", 906 /* FLEX_EDITOR_HDR_EGR_START_SET_BASE */ "", 907 /* FLEX_EDITOR_HDR_ID_LIST_COMMAND_BASE */ "", 908 /* FLEX_EDITOR_HDR_ID_SET_BASE */ "", 909 /* FLEX_EDITOR_HDR_LIST_ARRAY_BASE */ "", 910 /* FLEX_EDITOR_HDR_SIZE_SET_BASE */ "", 911 /* FLEX_EDITOR_HG2_UNUSED_FIELDS */ "Unused hg2 header fields for transit. Used in fixed sys header construction", 912 /* FLEX_EDITOR_HG_EH_CONTROL_FORMAT */ "Register formats for C code", 913 /* FLEX_EDITOR_HIGIG_HEADER_CONFIG_FORMAT */ "Register formats for C code", 914 /* FLEX_EDITOR_INSERT_COMMAND_BASE */ "", 915 /* FLEX_EDITOR_IN_BUS */ "Complete Input bus used for flex editor block", 916 /* FLEX_EDITOR_L2_FIELD_BUS */ "L2 field bus after extraction in Edit Action block to L2 Fixed Engine", 917 /* FLEX_EDITOR_L2_TAG_BUS */ "Egress L2 Tag Bus for various TAGs. It is only valid for SOP cell.", 918 /* FLEX_EDITOR_L3_FIELD_BUS */ "L3 field bus after extraction in Edit Action block to L3 Fixed Engine", 919 /* FLEX_EDITOR_MATCH_ID_COMMAND_PROFILE_TABLE */ "", 920 /* FLEX_EDITOR_MATCH_ID_SET_BASE */ "", 921 /* FLEX_EDITOR_MATCH_ID_TABLE */ "", 922 /* FLEX_EDITOR_MHC_CHECKSUM_COMMAND_BASE */ "", 923 /* FLEX_EDITOR_MHC_CHECKSUM_FLEX_HDR_SUM_SET_BASE */ "", 924 /* FLEX_EDITOR_MHC_CHECKSUM_MASK_BITMAP_64_FORMAT */ "Register formats for C code", 925 /* FLEX_EDITOR_MHC_CHECKSUM_POSITION_SET_BASE */ "", 926 /* FLEX_EDITOR_MHC_CHECKSUM_PROFILE_PTR_SET_BASE */ "", 927 /* FLEX_EDITOR_MHC_CHECKSUM_PROFILE_SET_BASE */ "", 928 /* FLEX_EDITOR_MHC_CHECKSUM_PROFILE_TABLE */ "", 929 /* FLEX_EDITOR_MHC_CHECKSUM_RW_DELTA_SET_BASE */ "", 930 /* FLEX_EDITOR_MHC_CRC_COMMAND_BASE */ "", 931 /* FLEX_EDITOR_MHC_CRC_PROFILE_PTR_SET_BASE */ "", 932 /* FLEX_EDITOR_MHC_CRC_PROFILE_SET_BASE */ "", 933 /* FLEX_EDITOR_MHC_CRC_PROFILE_TABLE */ "", 934 /* FLEX_EDITOR_MIRROR_ENCAP_CHECKSUM_COMMAND_BASE */ "", 935 /* FLEX_EDITOR_MIRROR_ENCAP_HEADER_SET_BASE */ "", 936 /* FLEX_EDITOR_MIRROR_ENCAP_PKT_LEN_COMMAND_BASE */ "", 937 /* FLEX_EDITOR_MIRROR_ENCAP_PROFILE_1_TABLE */ "", 938 /* FLEX_EDITOR_MIRROR_ENCAP_PROFILE_2_TABLE */ "", 939 /* FLEX_EDITOR_MIRROR_ENCAP_PROFILE_3_TABLE */ "", 940 /* FLEX_EDITOR_MIRROR_FIELD_BUS */ "Mirror field bus after extraction in Edit Action block to Mirror Engine", 941 /* FLEX_EDITOR_MIRROR_PROFILE_PTR_SET_BASE */ "", 942 /* FLEX_EDITOR_MMU_PKT_LENGTH_ADJUST_FORMAT */ "Register formats for C code", 943 /* FLEX_EDITOR_OBJECT_BUS */ "Egress Object Bus flow from MPB to rest of egress pipeline for various process. It is only valid for SOP cell.", 944 /* FLEX_EDITOR_OUT_BUS */ "Complete Output bus used for flex editor block", 945 /* FLEX_EDITOR_OW_FIELD_SELECT_COMMAND_BASE */ "", 946 /* FLEX_EDITOR_PKT_LENGTH_SET_BASE */ "", 947 /* FLEX_EDITOR_PKT_LEN_ATTRIBUTE_SET_BASE */ "", 948 /* FLEX_EDITOR_PKT_LEN_COMMAND_BASE */ "", 949 /* FLEX_EDITOR_REWRITE_ALU_COMMAND_BASE */ "", 950 /* FLEX_EDITOR_REWRITE_COMMAND_BASE */ "", 951 /* FLEX_EDITOR_REWRITE_FIELD_SELECT_COMMAND_BASE */ "", 952 /* FLEX_EDITOR_RW_ALU_PROFILE_TABLE */ "", 953 /* FLEX_EDITOR_RW_FIELD_BUS */ "Rewrite field bus after extraction in Edit Action block to rewrite Engine.", 954 /* FLEX_EDITOR_RW_FS_PROFILE_TABLE */ "", 955 /* FLEX_EDITOR_RW_HC_PROFILE_TABLE */ "", 956 /* FLEX_EDITOR_RW_HEADER_SET_BASE */ "", 957 /* FLEX_EDITOR_RW_NEXT_PROTO_ID_SET_BASE */ "", 958 /* FLEX_EDITOR_RW_NEXT_PROTO_TABLE */ "", 959 /* FLEX_EDITOR_RW_PROFILE_PTR_SET_BASE */ "", 960 /* FLEX_EDITOR_RW_PROFILE_TABLE */ "", 961 /* FLEX_EDITOR_RW_USER_FIELD_FORMAT */ "Register formats for C code", 962 /* FLEX_EDITOR_SYS_FIELD_BUS */ "System field bus after extraction in Edit Action block to System Fixed Engine.", 963 /* FLEX_EDITOR_TIMESTAMP_SET_BASE */ "", 964 /* FLEX_EDITOR_TUNNEL_FIELD_BUS */ "Tunnel field bus after extraction in Edit Action block to Tunnel Fixed Engine.", 965 /* FLEX_EDITOR_TUNNEL_PIMDR1_CFG0_FORMAT */ "Register formats for C code", 966 /* FLEX_EDITOR_TUNNEL_PIMDR1_CFG1_FORMAT */ "Register formats for C code", 967 /* FLEX_EDITOR_TUNNEL_PIMDR2_CFG0_FORMAT */ "Register formats for C code", 968 /* FLEX_EDITOR_TUNNEL_PIMDR2_CFG1_FORMAT */ "Register formats for C code", 969 /* FLEX_EDITOR_USER_FIELD_32BIT_COMMAND_BASE */ "", 970 /* FLEX_EDITOR_VHLEN_SET_BASE */ "", 971 /* FLEX_EDITOR_VXLAN_CONTROL_64_FORMAT */ "Register formats for C code", 972 /* FLEX_EDITOR_ZONE_SIZE_SET_BASE */ "", 973 /* FLEX_HVE_TRIGGERS_FORMAT */ "HVE (header verfication engine) profile format.", 974 /* FLEX_IFP_KEY_SIGNALS */ "FLEX_IFP_KEY_SIGNALS", 975 /* FLEX_KEY_CAM_BIST_CONFIG_64 */ "", 976 /* FLEX_KEY_CAM_BIST_STATUS */ "", 977 /* FLEX_KEY_GEN_EXTRACT_COMMAND_BASE */ "", 978 /* FLEX_KEY_GEN_EXTRACT_COMMAND_TYPE_A_BASE */ "", 979 /* FLEX_KEY_GEN_EXTRACT_COMMAND_TYPE_B_BASE */ "", 980 /* FLEX_KEY_GEN_EXTRACT_COMMAND_TYPE_C_BASE */ "", 981 /* FLEX_KEY_GEN_MUX_CTRL */ "", 982 /* FLEX_KEY_GEN_MUX_CTRL_PLUS_MASK_TYPE_B */ "", 983 /* FLEX_KEY_GEN_MUX_CTRL_PLUS_MASK_TYPE_C */ "", 984 /* FLEX_KEY_GEN_MUX_CTRL_TYPE_A */ "", 985 /* FLEX_KEY_LOOKUP_CONTROL_SRAM */ "", 986 /* FLEX_KEY_MASK */ "", 987 /* FLEX_KEY_SER_CONTROL */ "", 988 /* FLEX_KEY_TCAM */ "", 989 /* FLEX_KEY_TCAM1 */ "", 990 /* FLEX_KEY_TM_CONTROL_64 */ "", 991 /* FLEX_KEY_TM_CONTROL_TYPE_B */ "", 992 /* FLEX_PREEMPT */ "flex preempt", 993 /* FLEX_PREEMPT_START */ "flex preempt start", 994 /* FLEX_PREEMPT_TERMINATE */ "flex preempt terminate", 995 /* FLEX_RTAG7_HASH_OBJECT_BUS_FORMAT */ "Flex RTAG7 hash object bus Format.", 996 /* FLOWSET_COV_DEFS */ "defines for flowset coverage analysis", 997 /* FLOWSET_MEMBER_COV_DEFS */ "defines for flowset_member coverage analysis", 998 /* FLOWSET_TIMESTAMP_PAGE_COV_DEFS */ "defines for flowset_timestamp_page coverage analysis", 999 /* FMT_ALPM_ASSOC_DATA */ "ALPM associated data format from shared memory", 1000 /* FMT_ALPM_ENTRY_DATA */ "ALPM associated data format from shared memory", 1001 /* FMT_SAMPLE */ "Sample format specification", 1002 /* FORWARDING_1_FLEX_KEY_GEN_IN_CONTROL_BUS */ "FlexKeyGen Input Control Bus for forwarding tables. Same format for L3_ENTRY, L2_ENTRY, and L3_DEFIP(LPM)", 1003 /* FORWARDING_1_FLEX_KEY_GEN_OUT_BUS */ "FlexKeyGen Output bus L2 ENTRY", 1004 /* FORWARDING_1_KEYS_DOP */ "FORWARDING_1_KEYS_DOP DOP description.", 1005 /* FORWARDING_1_LKUP_DOP */ "FORWARDING_1_LKUP_DOP DOP description.", 1006 /* FORWARDING_1_MISC_ATTRIBUTES_ACTION_SET */ "PDD Output Bus generic format", 1007 /* FORWARDING_1_PDD_OUT_BUS */ "PDD Output Bus generic format", 1008 /* FORWARDING_1_QOS_ACTION_SET */ "PDD Output Bus generic format", 1009 /* FORWARDING_2_FLEX_KEY_GEN_IN_CONTROL_BUS */ "FlexKeyGen Input Control Bus for forwarding tables. Same format for L3_ENTRY, L2_ENTRY, and L3_DEFIP(LPM)", 1010 /* FORWARDING_2_FLEX_KEY_GEN_OUT_BUS */ "FlexKeyGen Output bus L3 ENTRY", 1011 /* FORWARDING_2_KEY_1_DOP */ "FORWARDING_2_KEY_1_DOP DOP description.", 1012 /* FORWARDING_2_KEY_2_DOP */ "FORWARDING_2_KEY_2_DOP DOP description.", 1013 /* FORWARDING_2_LKUP_DOP */ "FORWARDING_2_LKUP_DOP DOP description.", 1014 /* FORWARDING_2_MISC_ATTRIBUTES_ACTION_SET */ "PDD Output Bus generic format", 1015 /* FORWARDING_2_PDD_OUT_BUS */ "PDD Output Bus generic format", 1016 /* FORWARDING_3_FLEX_KEY_GEN_IN_CONTROL_BUS */ "FlexKeyGen Input Control Bus for forwarding tables. Same format for L3_ENTRY, L2_ENTRY, and L3_DEFIP(LPM)", 1017 /* FORWARDING_3_FLEX_KEY_GEN_OUT_BUS */ "FlexKeyGen Output bus LPM(L3_DEFIP)", 1018 /* FORWARDING_3_KEY_0_DOP */ "FORWARDING_3_KEY_0_DOP DOP description.", 1019 /* FORWARDING_3_KEY_1_DOP */ "FORWARDING_3_KEY_1_DOP DOP description.", 1020 /* FORWARDING_3_KEY_2_DOP */ "FORWARDING_3_KEY_2_DOP DOP description.", 1021 /* FORWARDING_3_KEY_3_DOP */ "FORWARDING_3_KEY_3_DOP DOP description.", 1022 /* FORWARDING_3_LKUP_DOP */ "FORWARDING_3_LKUP_DOP DOP description.", 1023 /* FORWARDING_3_MISC_ATTRIBUTES_ACTION_SET */ "PDD Output Bus generic format", 1024 /* FORWARDING_3_PDD_OUT_BUS */ "PDD Output Bus generic format", 1025 /* FORWARDING_FLEX_KEY_GEN_IN_BUS */ "Ingress Forwarding Flex key gen input bus. It is only valid for SOP cell.", 1026 /* FORWARDING_KEYGEN_OBJECT_BUS */ "Tunnel adapt object bus portion of tunnel_adapt_flex_key_gen_in_bus. It is only valid for SOP cell.", 1027 /* FP */ "Position and description of bits in FP FIELDS", 1028 /* FP_COPY_TO_CPU_SET */ "Position and description of bits in the copy to cpu set", 1029 /* FP_COUNTER_SET */ "Position and description of bits in the counter set", 1030 /* FP_CPU_COS_SET */ "Position and description of bits in the cpu cos set", 1031 /* FP_DW */ "Position and description of bits in FP DOUBLE WIDE FIELDS", 1032 /* FP_GOA_SET */ "Position and description of bits in the goa redirect set", 1033 /* FP_HGPRXY_AUX_HDR_BITMAP */ "FP_HGPRXY AUX_HDR_BITMAP.", 1034 /* FP_L3SW_L2_FIELDS_SET */ "Position and description of bits in the l3sw_l2_fields set", 1035 /* FP_LOOKUP */ "Bit Definitions of the FP lookup vector", 1036 /* FP_LOOKUP_STATUS_VECTOR */ "Bit Definitions of the FP lookup status vector.", 1037 /* FP_METER_SET */ "Position and description of bits in the meter set", 1038 /* FP_MIRROR_SET */ "Position and description of bits in the mirror set", 1039 /* FP_MISC_1_SET */ "Position and description of bits in the misc_1 set", 1040 /* FP_MISC_2_SET */ "Position and description of bits in the misc_2 set", 1041 /* FP_MPLS_LABEL */ "", 1042 /* FP_OAM_SET */ "Position and description of bits in the oam set", 1043 /* FP_PORT_FIELD_SEL_SLICE_ENTRY_0_11 */ "IFP slice key control", 1044 /* FP_PORT_FIELD_SEL_SLICE_ENTRY_0_15 */ "IFP slice key control", 1045 /* FP_PROFILE_SET */ "Position and description of bits in the profile action set", 1046 /* FP_REDIRECT_SET */ "Position and description of bits in the redirect set", 1047 /* FP_RESOLUTION */ "FP resolution packet field values", 1048 /* FP_SHARED_METER_SET */ "Position and description of bits in the shared meter set", 1049 /* FT_CMICM_TO_IP0_EP2_X */ "Feedthrough bus from cmimc to ip0_ep2_x, through mby, mbx, ep1", 1050 /* FT_CMICM_TO_IP45_SHARED */ "Feedthrough bus from cmicm to ip45_shared", 1051 /* FT_CMICM_TO_MMU1 */ "Feedthrough bus from cmicm to mmu1", 1052 /* FT_CMICM_TO_PGW_X */ "Feedthrough bus from cmicm to pgw_cl_x", 1053 /* FT_CMICM_TO_PGW_Y */ "Feedthrough bus from cmicm to pgw_cl_y", 1054 /* FT_FIXED_ASSOCIATED_DATA */ "EXACT_MATCH Hash Table Flow Tracker Fixed Associated Data Fields", 1055 /* FT_IN_BUS */ "Input bus to flow tracker core module", 1056 /* FT_IP0_EP2_TO_CMICM */ "Feedthrough bus from ip0_ep2_x to cmicm via mbx mby", 1057 /* FT_IP0_EP2_TO_IP5 */ "Feedthrough bus from ip0_ep2 to ip5", 1058 /* FT_IP0_EP2_TO_IP1_EP0 */ "Feedthrough bus from ip0_ep2_x/y to ip1_ep0_x/y", 1059 /* FT_IP0_EP2_TO_IP45_SHARED */ "Feedthrough bus from ip0_ep2_x/y to ip45_shared", 1060 /* FT_IP0_EP2_TO_MMU0 */ "Feedthrough bus from ip0_ep2 to mmu0", 1061 /* FT_IP0_EP2_X_TO_IP0_EP2_Y */ "Feedthrough bus from ip0_ep2_x to ip0_ep2_y", 1062 /* FT_IP0_EP2_X_TO_MMU1 */ "Feedthrough bus from ip0_ep2_x to mmu1", 1063 /* FT_IP0_EP2_Y_TO_IP0_EP2_X */ "Feedthrough bus from ip0_ep2_y to ip0_ep2_x", 1064 /* FT_IP0_EP2_Y_TO_MMU1 */ "Feedthrough bus from ip0_ep2_y to mmu1", 1065 /* FT_IP0_X_TO_EP1_IP5 */ "Feedthrough bus from ip0_x to ep1_x, ip5_x, ip5_y, ep1_y", 1066 /* FT_IP1_EP0_X_TO_MMU1 */ "Feedthrough bus from ip1_ep0_x to mmu1", 1067 /* FT_IP1_EP0_Y_TO_MMU1 */ "Feedthrough bus from ip1_ep0_y to mmu1", 1068 /* FT_IP2_TO_IP0_EP2 */ "Feedthrough bus from ip2_x/y to ip0_ep2_x/y", 1069 /* FT_IP2_X_TO_CMICM */ "Feedthrough bus from ip2_x to cmicm", 1070 /* FT_IP2_X_TO_IP0_EP2_X */ "Feedthrough bus from ip2_x to ip0_ep2_x", 1071 /* FT_IP2_Y_TO_CMICM */ "Feedthrough bus from ip2_y to cmicm", 1072 /* FT_IP2_Y_TO_IP0_EP2_X */ "Feedthrough bus from ip2_y to ip0_ep2_x", 1073 /* FT_IP45_SHARED_TO_CMICM */ "Feedthrough bus from ip45_shared to cmicm", 1074 /* FT_IP45_SHARED_TO_IP0_EP2 */ "Feedthrough bus from ip45_shared to ip0_ep2", 1075 /* FT_IP45_SHARED_TO_IP1_EP0 */ "Feedthrough bus from ip45_shared to ip1_ep0", 1076 /* FT_IP5_X_TO_MMU0 */ "Feedthrough bus from ip5_x to mmu0", 1077 /* FT_IP5_Y_TO_MMU0 */ "Feedthrough bus from ip5_y to mmu0", 1078 /* FT_LEARN_DATA */ "Ingress Pipeline Learn Bus.", 1079 /* FT_LEARN_FIFO_REQ */ "Per pipeline L2 bus from ISW1[0-3] to L2_MGMT. Both Learn_bus and L2_LOOKUP / L2_MEMRD data is returned on this shared bus.", 1080 /* FT_MMU2_TO_CMICM */ "Feedthrough bus from mmu2 to cmicm", 1081 /* FT_MMU2_TO_IP45_SHARED */ "Feedthrough bus from mmu2 to ip45_shared", 1082 /* FT_MMU2_TO_PGW_CL */ "Feedthrough bus from mmu2 to pgw_cl_x/y", 1083 /* FT_OUT_BUS */ "Output bus flow tracker core module", 1084 /* FT_PGW_CL_TO_MMU2 */ "Feedthrough bus from pgw_cl_x/y to mmu2", 1085 /* FT_PGW_X_TO_CMICM */ "Feedthrough bus from pgw_cl_x to cmicm", 1086 /* FT_PGW_Y_TO_CMICM */ "Feedthrough bus from pgw_cl_y to cmicm", 1087 /* FT_SER_CONTROL */ "Flow Tracker ECC and SER control", 1088 /* FT_SESSION_COV_DEFS */ "defines for flow tracker session coverage analysis", 1089 /* FT_SM_HDR_ALL */ "Flow tracker to signature matching header", 1090 /* FT_SM_HDR_IP */ "Flow tracker to signature matching header", 1091 /* FT_TOP_REGS_TO_EP1 */ "Feedthrough bus from top_regs_otpc to ep1_x, ep1_y", 1092 /* FWD1_0_DOP */ "FWD1_0_DOP DOP description.", 1093 /* FWD1_1_DOP */ "FWD1_1_DOP DOP description.", 1094 /* FWD1_DROPS_DOP */ "FWD1_DROPS_DOP DOP description.", 1095 /* FWD1_FWD_OBJ_DOP */ "FWD1_FWD_OBJ_DOP DOP description.", 1096 /* FWD2_0_DOP */ "FWD2_0_DOP DOP description.", 1097 /* FWD2_ITAG_ISID_OR_VPNID_OR_VN_ID_DOP */ "FWD2_ITAG_ISID_OR_VPNID_OR_VN_ID_DOP DOP description.", 1098 /* FWD2_MAPPING_COMPRESSION_RESULTS_DOP */ "FWD2_MAPPING_COMPRESSION_RESULTS_DOP DOP description.", 1099 /* FWD_ATTRIBUTES_ACTION_SET */ "PDD Output Bus generic format", 1100 /* FWD_DOMAIN_ACTION_SET */ "PDD Output Bus generic format", 1101 /* FWD_DROP_VECTOR */ "Bit Definitions of the VXLT drop vector.", 1102 /* GIH */ "Bit Definitions of the Global Internal Header.", 1103 /* GIH_EP_COPY_TO_CPU */ "EP_COPY_TO_CPU specific fields in GIH header", 1104 /* GIH_FROM_CPU */ "FROM_CPU specific fields in GIH header", 1105 /* GIH_OAM_TX */ "OAM_TX specific fields in GIH header", 1106 /* GPORT_XQHDR_S_RF */ "GPORT XQ Header memory s_rf width", 1107 /* GRE_FLAGS_HDR */ "GRE header flags specification", 1108 /* GROUP_STATS_COV_DEFS */ "defines for group_stats coverage analysis", 1109 /* GROUP_STATS_ECMP_COV_DEFS */ "defines for group_stats_ecmp coverage analysis", 1110 /* HASH_CONTROL_FULL_SET */ "Hash Control.", 1111 /* HDR_UPDATE_CTRL */ "control field decoding", 1112 /* HG2_EH_CLASSID_TYPE */ "EH header ClassID source.", 1113 /* HG2_UNUSED_FIELDS */ "Unused hg2 header fields for transit", 1114 /* HGT_LAG_DLB_ACTION_SET */ "PDD Output Bus generic format", 1115 /* HGT_RH_ACTION_SET */ "PDD Output Bus generic format", 1116 /* HG_COUNTER */ "Higig counter code values", 1117 /* HG_TRUNK_DOP */ "HG_TRUNK_DOP DOP description.", 1118 /* HG_TRUNK_GROUP_RRLB_CNT_COV_DEFS */ "defines for ifp odd meter coverage analysis", 1119 /* HIGIG2 */ "Bit Definitions of the Higig2 Module Header", 1120 /* HIGIG_AUX_HDR_BITMAP */ "HIGIG AUX_HDR_BITMAP.", 1121 /* HIGIG_CHANGE_DEST_ACTION_SET */ "PDD Output Bus generic format", 1122 /* HIGIG_CONTROLS_ACTION_SET */ "PDD Output Bus generic format", 1123 /* HITREQ_BUS */ "Search Stage Hit Request Bus.", 1124 /* HITREQ_BUS_C_MODEL */ "Search Stage Hit Request Bus.", 1125 /* HITRST_BUS */ "Search Stage Hit Result Bus.", 1126 /* HITRST_BUS_C_MODEL */ "Search Stage Hit Result Bus.", 1127 /* HVE0_BUS */ "HVE0 Bus Format", 1128 /* HVE0_IN_BUS */ "HVE (header verfication engine) trigger format.", 1129 /* HVE_DOS_ATTACK_RESULTS_FORMAT */ "HVE result bus format.", 1130 /* HVE_IN_BUS */ "HVE (header verfication engine) trigger format.", 1131 /* HVE_RESULTS_FORMAT */ "HVE result bus format.", 1132 /* HVE_RESULT_BUS_1_DOP */ "HVE_RESULT_BUS_1_DOP DOP description.", 1133 /* IARB_EOP_BUS */ "IDB EOP BUS format", 1134 /* IARB_EOP_EVENT_QUEUE */ "format", 1135 /* IARB_EVENT_FIFO */ "format", 1136 /* IARB_TO_L2_MGMT_ACK */ "Ack Bus from IARB[0-3] to L2_MGMT.", 1137 /* ICFG_DOP */ "Position and description of bits in ICFG_DOP DOP chain", 1138 /* ICFG_TO_ISW2_BUS */ "Bit Definitions of ICFG_TO_ISW2_BUS.", 1139 /* ICFG_TO_ISW3_BUS */ "Bit Definitions of ICFG_TO_ISW3_BUS.", 1140 /* ICMP_TYPE */ "Specifies the format of the ICMP message.", 1141 /* IDB_CA0_CTRL */ "CA Buffer control memory format", 1142 /* IDB_CA_Q_TO_OBM_BUS */ "CA Q TO OBM status bus data format", 1143 /* IDB_CA_TO_IP_CTRL */ "CA to IP control format", 1144 /* IDB_CA_TO_OBM_BUS */ "CA TO OBM status bus data format", 1145 /* IDB_CTRL_BUS */ "format", 1146 /* IDB_EOP_BUS */ "IDB EOP BUS format", 1147 /* IDB_EOP_EVENT_QUEUE */ "format", 1148 /* IDB_OBM0_48_DATA */ "OBM Buffer data format", 1149 /* IDB_OBM0_CTRL */ "OBM Buffer control memory format", 1150 /* IDB_OBM0_DATA */ "OBM Buffer data format", 1151 /* IDB_OBM0_Q_DATA */ "OBM Buffer data format", 1152 /* IDB_OBM0_RESIDUE_CTRL */ "Active Residue (in Prebuffer) control format", 1153 /* IDB_OBM_Q_TO_CA_BUS */ "OBM Q to CA bus format", 1154 /* IDB_OBM_TO_CA_BUS */ "OBM to CA bus format", 1155 /* IDB_OBM_TO_CA_CTRL */ "OBM to CA control format", 1156 /* IDB_SOP_EVENT_FIFO */ "format", 1157 /* IDB_TO_IPOST_BUS */ "Bit Definitions of IDB_TO_IPOST_BUS.", 1158 /* IDB_TO_ISW4_BUS */ "Bit Definitions of IDB_TO_ISW4_BUS.", 1159 /* IDISC_DROP */ "Bit Definitions of the VLAN drop vector.", 1160 /* IFP_0_DOP */ "IFP_0_DOP DOP description.", 1161 /* IFP_BFD_BUS_FORMAT */ "BFD fields format", 1162 /* IFP_CHANGE_COS_OR_INT_PRI_SET */ "PDD Output Bus generic format", 1163 /* IFP_CHANGE_CPU_COS_SET */ "Position and description of bits in the copy to cpu set", 1164 /* IFP_CHANGE_DROP_PRECEDENCE_SET */ "PDD Output Bus generic format", 1165 /* IFP_CHANGE_DSCP_TOS_SET */ "PDD Output Bus generic format", 1166 /* IFP_CHANGE_ECN_SET */ "PDD Output Bus generic format", 1167 /* IFP_CHANGE_INPUT_PRIORITY_SET */ "PDD Output Bus generic format", 1168 /* IFP_CHANGE_INT_CN_SET */ "PDD Output Bus generic format", 1169 /* IFP_CHANGE_PKT_PRI_SET */ "PDD Output Bus generic format", 1170 /* IFP_COPY_TO_CPU_SET */ "Position and description of bits in the cpu cos set", 1171 /* IFP_COUNTER_MUX_DATA_STAGING */ "Position and description of bits in the counter mux data staging table added for area optimization of meter muxing logic", 1172 /* IFP_COUNTER_SET */ "Position and description of bits in the profile action set", 1173 /* IFP_COUNTER_TABLE_COV_DEFS */ "defines for ifp counter coverage analysis", 1174 /* IFP_CUT_THRU_OVERRIDE_SET */ "Position and description of bits in the profile action set", 1175 /* IFP_DELAYED_DROP_SET */ "IFP DELAYED_DROP_SET profile action set", 1176 /* IFP_DELAYED_REDIRECT_SET */ "IFP DELAYED_REDIRECT_SET profile action set", 1177 /* IFP_DLB_ALTERNATE_PATH_CONTROL_SET */ "Position and description of bits in the profile action set", 1178 /* IFP_DLB_ECMP_MONITOR_SET */ "IFP DLB_ECMP_MONITOR profile action set", 1179 /* IFP_DLB_ECMP_SET */ "Position and description of bits in the profile action set", 1180 /* IFP_DLB_HGT_LAG_SET */ "Position and description of bits in the profile action set", 1181 /* IFP_DOP */ "Position and description of bits in IFP_DOP DOP chain", 1182 /* IFP_DOUBLE_WIDE_F0 */ "Position and description of bits in FP DOUBLE WIDE FIELDS", 1183 /* IFP_DOUBLE_WIDE_F1 */ "Position and description of bits in FP DOUBLE WIDE FIELDS", 1184 /* IFP_DOUBLE_WIDE_F3 */ "Position and description of bits in FP DOUBLE WIDE FIELDS", 1185 /* IFP_DOUBLE_WIDE_F1_0 */ "Position and description of bits in FP DOUBLE WIDE FIELDS", 1186 /* IFP_DOUBLE_WIDE_F1_1 */ "Position and description of bits in FP DOUBLE WIDE FIELDS", 1187 /* IFP_DOUBLE_WIDE_F1_2 */ "Position and description of bits in FP DOUBLE WIDE FIELDS", 1188 /* IFP_DOUBLE_WIDE_F2_0 */ "Position and description of bits in FP DOUBLE WIDE FIELDS", 1189 /* IFP_DOUBLE_WIDE_F2_1 */ "Position and description of bits in FP DOUBLE WIDE FIELDS", 1190 /* IFP_DOUBLE_WIDE_F2_2 */ "Position and description of bits in FP DOUBLE WIDE FIELDS", 1191 /* IFP_DOUBLE_WIDE_F2_3 */ "Position and description of bits in FP DOUBLE WIDE FIELDS", 1192 /* IFP_DOUBLE_WIDE_F2_4 */ "Position and description of bits in FP DOUBLE WIDE FIELDS", 1193 /* IFP_DOUBLE_WIDE_F2_5 */ "Position and description of bits in FP DOUBLE WIDE FIELDS", 1194 /* IFP_DOUBLE_WIDE_F2_6 */ "Position and description of bits in FP DOUBLE WIDE FIELDS", 1195 /* IFP_DOUBLE_WIDE_F2_7 */ "Position and description of bits in FP DOUBLE WIDE FIELDS", 1196 /* IFP_DOUBLE_WIDE_F4_0 */ "Position and description of bits in FP DOUBLE WIDE FIELDS", 1197 /* IFP_DOUBLE_WIDE_F4_1 */ "Position and description of bits in FP DOUBLE WIDE FIELDS", 1198 /* IFP_DOUBLE_WIDE_IPBM_F0 */ "Position and description of bits in FP DOUBLE WIDE FIELDS", 1199 /* IFP_DROP_SET */ "Position and description of bits in the profile action set", 1200 /* IFP_DUAL_COUNTER_TABLE_COV_DEFS */ "defines for ifp dual tcam slice counter coverage analysis", 1201 /* IFP_EDIT_CTRL_ID_ACTION_SET */ "PDD Output Bus generic format", 1202 /* IFP_ELEPHANT_TRAP_SET */ "IFP ELEPHANT_TRAP_SET profile action set", 1203 /* IFP_EVEN_METER_COV_DEFS */ "defines for ifp even meter coverage analysis", 1204 /* IFP_FCOE_VSAN_SET */ "PDD Output Bus generic format", 1205 /* IFP_GREEN_TO_PID_SET */ "Position and description of bits in the profile action set", 1206 /* IFP_IGNORE_FCOE_ZONE_CHECK_SET */ "PDD Output Bus generic format", 1207 /* IFP_INBAND_TELEMETRY_SET */ "IFP INBAND_TELEMETRY profile action set", 1208 /* IFP_INSTRUMENTATION_SET */ "Position and description of bits in the profile action set", 1209 /* IFP_KEY_320B */ "320B Key Format", 1210 /* IFP_KEY_480B */ "480B Key Format", 1211 /* IFP_KEY_POST_MUX */ "Final Key to the IFP TCAM", 1212 /* IFP_KEY_SEL_LOGICAL_TABLE_ID_AND_CLASS_ID */ "IFP_KEY_SEL_LOGICAL_TABLE_ID_AND_CLASS_ID format", 1213 /* IFP_L0_BUS */ "Packet Fields Bus", 1214 /* IFP_L0_BUS_SECTION_16BIT */ "Key extractor input bus 16bit section", 1215 /* IFP_L0_BUS_SECTION_2BIT */ "Key extractor input bus 2bit section", 1216 /* IFP_L0_BUS_SECTION_32BIT */ "Key extractor input bus 32bit section", 1217 /* IFP_L0_BUS_SECTION_4BIT */ "Key extractor input bus 4bit section", 1218 /* IFP_L0_BUS_SECTION_8BIT */ "Key extractor input bus 8bit section", 1219 /* IFP_L1_BUS */ "Output of the first stage of field extraction.", 1220 /* IFP_L1_BUS_SECTION_A */ "IFP_L1_BUS_SECTION_A bit ordering", 1221 /* IFP_L1_BUS_SECTION_B */ "IFP_L1_BUS_SECTION_B bit ordering", 1222 /* IFP_L1_BUS_SECTION_C */ "IFP_L1_BUS_SECTION_C bit ordering", 1223 /* IFP_L2_BUS */ "Output of the second stage of field extraction.", 1224 /* IFP_L3SW_CHANGE_L2_SET */ "Position and description of bits in the profile action set", 1225 /* IFP_L3_BUS */ "Output of the third stage of field extraction.", 1226 /* IFP_LB_CONTROLS_SET */ "Position and description of bits in the profile action set", 1227 /* IFP_LOGICAL_TABLE_SELECT_DATA_FORMAT */ "format for IFP_LOGICAL_TABLE_SELECT data", 1228 /* IFP_LOGICAL_TABLE_SELECT_TCAM_FORMAT */ "format for IFP_LOGICAL_TABLE_SELECT TCAM", 1229 /* IFP_LOGICAL_TBL_DOP */ "IFP_LOGICAL_TBL_DOP DOP description.", 1230 /* IFP_LOOKUP_STATUS_VECTOR */ "Bit Definitions of the FP lookup status vector.", 1231 /* IFP_LOOKUP_STATUS_VECTOR_DOP */ "IFP_LOOKUP_STATUS_VECTOR_DOP DOP description.", 1232 /* IFP_LOOKUP_STATUS_VECTOR_POST */ "IFP LOOKUP STATUS VECTOR POST", 1233 /* IFP_METER_MUX_DATA_STAGING */ "Position and description of bits in the meter mux data staging table added for area optimization of meter muxing logic", 1234 /* IFP_METER_SET */ "Position and description of bits in the profile action set", 1235 /* IFP_MIRROR_OVERRIDE_SET */ "Position and description of bits in the profile action set", 1236 /* IFP_MIRROR_SET */ "Position and description of bits in the profile action set", 1237 /* IFP_MPLS_FORWARDING_LABEL_ACTION */ "MPLS Forwarding Label Action as needed by the IFP key.", 1238 /* IFP_NAT_OVERRIDE_SET */ "Position and description of bits in the profile action set", 1239 /* IFP_NAT_SET */ "Position and description of bits in the profile action set", 1240 /* IFP_ODD_METER_COV_DEFS */ "defines for ifp odd meter coverage analysis", 1241 /* IFP_PAIRING_F1 */ "Position and description of bits in FP PAIRING FIELDS", 1242 /* IFP_PAIRING_FIXED */ "Position and description of bits in FP PAIRING FIELDS", 1243 /* IFP_PAIRING_IPBM_F0 */ "Position and description of bits in FP PAIRING FIELDS", 1244 /* IFP_POLICY_PDD_OUT_BUS */ "PDD Output Bus generic format", 1245 /* IFP_POST_MUX_CONTROLS */ "Control signals for post multiplexing signals that were not available for the IFP key generation block.", 1246 /* IFP_PROFILE_SET_1 */ "Position and description of bits in the profile action set", 1247 /* IFP_PROFILE_SET_2 */ "Position and description of bits in the profile action set", 1248 /* IFP_PROFILE_SET_1_DATA_FORMAT */ "Position and description of bits in the profile action set data", 1249 /* IFP_PROFILE_SET_2_DATA_FORMAT */ "Position and description of bits in the profile action set data", 1250 /* IFP_PROTECTION_SWITCHING_DROP_OVERIDE_SET */ "PDD Output Bus generic format", 1251 /* IFP_PROTECTION_SWITCHING_SET */ "Position and description of bits in the profile action set", 1252 /* IFP_REDIRECT_SET */ "Bit Definitions of the Redirection Field in IFP Policy Table", 1253 /* IFP_RESOLUTION */ "FP resolution packet field values.", 1254 /* IFP_SECURITY_STATUS */ "Position and description of bits in FP SECURITY STATUS FIELDS", 1255 /* IFP_SFLOW_SET */ "Position and description of bits in the profile action set", 1256 /* IFP_SHARED_TO_IFP_CTR_BUS */ "control bus for ifp_shared logic to ifp, contains cmic and refresh signals", 1257 /* IFP_SHARED_TO_IFP_DATA_BUS */ "data bus for ifp_shared logic to ifp, contains normal function signals", 1258 /* IFP_SINGLE_COUNTER_TABLE_COV_DEFS */ "defines for ifp single tcam slice counter coverage analysis", 1259 /* IFP_SINGLE_WIDE_F4 */ "Position and description of bits in FP FIELDS", 1260 /* IFP_SINGLE_WIDE_F1_0 */ "Position and description of bits in FP FIELDS", 1261 /* IFP_SINGLE_WIDE_F1_1 */ "Position and description of bits in FP FIELDS", 1262 /* IFP_SINGLE_WIDE_F1_2 */ "Position and description of bits in FP FIELDS", 1263 /* IFP_SINGLE_WIDE_F1_3 */ "Position and description of bits in FP FIELDS", 1264 /* IFP_SINGLE_WIDE_F1_4 */ "Position and description of bits in FP FIELDS", 1265 /* IFP_SINGLE_WIDE_F1_5 */ "Position and description of bits in FP FIELDS", 1266 /* IFP_SINGLE_WIDE_F1_6 */ "Position and description of bits in FP FIELDS", 1267 /* IFP_SINGLE_WIDE_F1_7 */ "Position and description of bits in FP FIELDS", 1268 /* IFP_SINGLE_WIDE_F1_8 */ "Position and description of bits in FP FIELDS", 1269 /* IFP_SINGLE_WIDE_F1_9 */ "Position and description of bits in FP FIELDS", 1270 /* IFP_SINGLE_WIDE_F1_10 */ "Position and description of bits in FP FIELDS", 1271 /* IFP_SINGLE_WIDE_F1_11 */ "Position and description of bits in FP FIELDS", 1272 /* IFP_SINGLE_WIDE_F1_12 */ "Position and description of bits in FP FIELDS", 1273 /* IFP_SINGLE_WIDE_F1_13 */ "Position and description of bits in FP FIELDS", 1274 /* IFP_SINGLE_WIDE_F1_14 */ "Position and description of bits in FP FIELDS", 1275 /* IFP_SINGLE_WIDE_F1_15 */ "Position and description of bits in FP FIELDS", 1276 /* IFP_SINGLE_WIDE_F1_16 */ "Position and description of bits in FP FIELDS", 1277 /* IFP_SINGLE_WIDE_F2_0 */ "Position and description of bits in FP FIELDS", 1278 /* IFP_SINGLE_WIDE_F2_1 */ "Position and description of bits in FP FIELDS", 1279 /* IFP_SINGLE_WIDE_F2_2 */ "Position and description of bits in FP FIELDS", 1280 /* IFP_SINGLE_WIDE_F2_3 */ "Position and description of bits in FP FIELDS", 1281 /* IFP_SINGLE_WIDE_F2_4 */ "Position and description of bits in FP FIELDS", 1282 /* IFP_SINGLE_WIDE_F2_5 */ "Position and description of bits in FP FIELDS", 1283 /* IFP_SINGLE_WIDE_F2_6 */ "Position and description of bits in FP FIELDS", 1284 /* IFP_SINGLE_WIDE_F2_7 */ "Position and description of bits in FP FIELDS", 1285 /* IFP_SINGLE_WIDE_F2_8 */ "Position and description of bits in FP FIELDS", 1286 /* IFP_SINGLE_WIDE_F2_9 */ "Position and description of bits in FP FIELDS", 1287 /* IFP_SINGLE_WIDE_F2_10 */ "Position and description of bits in FP FIELDS", 1288 /* IFP_SINGLE_WIDE_F2_11 */ "Position and description of bits in FP FIELDS", 1289 /* IFP_SINGLE_WIDE_F2_12 */ "Position and description of bits in FP FIELDS", 1290 /* IFP_SINGLE_WIDE_F2_13 */ "Position and description of bits in FP FIELDS", 1291 /* IFP_SINGLE_WIDE_F2_14 */ "Position and description of bits in FP FIELDS", 1292 /* IFP_SINGLE_WIDE_F2_15 */ "Position and description of bits in FP FIELDS", 1293 /* IFP_SINGLE_WIDE_F2_16 */ "Position and description of bits in FP FIELDS", 1294 /* IFP_SINGLE_WIDE_F2_17 */ "Position and description of bits in FP FIELDS", 1295 /* IFP_SINGLE_WIDE_F2_18 */ "Position and description of bits in FP FIELDS", 1296 /* IFP_SINGLE_WIDE_F3_0 */ "Position and description of bits in FP FIELDS", 1297 /* IFP_SINGLE_WIDE_F3_1 */ "Position and description of bits in FP FIELDS", 1298 /* IFP_SINGLE_WIDE_F3_2 */ "Position and description of bits in FP FIELDS", 1299 /* IFP_SINGLE_WIDE_F3_3 */ "Position and description of bits in FP FIELDS", 1300 /* IFP_SINGLE_WIDE_F3_4 */ "Position and description of bits in FP FIELDS", 1301 /* IFP_SINGLE_WIDE_F3_5 */ "Position and description of bits in FP FIELDS", 1302 /* IFP_SINGLE_WIDE_F3_6 */ "Position and description of bits in FP FIELDS", 1303 /* IFP_SINGLE_WIDE_F3_7 */ "Position and description of bits in FP FIELDS", 1304 /* IFP_SINGLE_WIDE_F3_8 */ "Position and description of bits in FP FIELDS", 1305 /* IFP_SINGLE_WIDE_F3_9 */ "Position and description of bits in FP FIELDS", 1306 /* IFP_SINGLE_WIDE_F3_10 */ "Position and description of bits in FP FIELDS", 1307 /* IFP_SINGLE_WIDE_F3_11 */ "Position and description of bits in FP FIELDS", 1308 /* IFP_SINGLE_WIDE_F3_12 */ "Position and description of bits in FP FIELDS", 1309 /* IFP_SINGLE_WIDE_F3_13 */ "Position and description of bits in FP FIELDS", 1310 /* IFP_SINGLE_WIDE_F3_14 */ "Position and description of bits in FP FIELDS", 1311 /* IFP_SINGLE_WIDE_F3_15 */ "Position and description of bits in FP FIELDS", 1312 /* IFP_SINGLE_WIDE_F3_16 */ "Position and description of bits in FP FIELDS", 1313 /* IFP_SINGLE_WIDE_FIXED */ "Position and description of bits in FP FIELDS", 1314 /* IFP_SLICE_CONTROL_BUS */ "Ifp lookup control signals", 1315 /* IFP_SLICE_KEY_CONTROL_BUS */ "Ifp lookup control signals", 1316 /* IFP_SOURCE_CLASS_FORMAT_0 */ "Source Class Format as defined the spec", 1317 /* IFP_SOURCE_CLASS_FORMAT_1 */ "Source Class Format as defined the spec", 1318 /* IFP_SOURCE_CLASS_FORMAT_2 */ "Source Class Format as defined the spec", 1319 /* IFP_SOURCE_CLASS_FORMAT_3 */ "Source Class Format as defined the spec", 1320 /* IFP_STORM_METER_COV_DEFS */ "defines for ifp storm meter coverage analysis", 1321 /* IFP_TCAM_DOP_DOP */ "IFP_TCAM_DOP_DOP DOP description.", 1322 /* IFP_TCAM_KEY_0_DOP */ "IFP_TCAM_KEY_0_DOP DOP description.", 1323 /* IFP_TCAM_KEY_10_DOP */ "IFP_TCAM_KEY_10_DOP DOP description.", 1324 /* IFP_TCAM_KEY_11_DOP */ "IFP_TCAM_KEY_11_DOP DOP description.", 1325 /* IFP_TCAM_KEY_12_DOP */ "IFP_TCAM_KEY_12_DOP DOP description.", 1326 /* IFP_TCAM_KEY_13_DOP */ "IFP_TCAM_KEY_13_DOP DOP description.", 1327 /* IFP_TCAM_KEY_14_DOP */ "IFP_TCAM_KEY_14_DOP DOP description.", 1328 /* IFP_TCAM_KEY_15_DOP */ "IFP_TCAM_KEY_15_DOP DOP description.", 1329 /* IFP_TCAM_KEY_16_DOP */ "IFP_TCAM_KEY_16_DOP DOP description.", 1330 /* IFP_TCAM_KEY_17_DOP */ "IFP_TCAM_KEY_17_DOP DOP description.", 1331 /* IFP_TCAM_KEY_1_DOP */ "IFP_TCAM_KEY_1_DOP DOP description.", 1332 /* IFP_TCAM_KEY_2_DOP */ "IFP_TCAM_KEY_2_DOP DOP description.", 1333 /* IFP_TCAM_KEY_3_DOP */ "IFP_TCAM_KEY_3_DOP DOP description.", 1334 /* IFP_TCAM_KEY_4_DOP */ "IFP_TCAM_KEY_4_DOP DOP description.", 1335 /* IFP_TCAM_KEY_5_DOP */ "IFP_TCAM_KEY_5_DOP DOP description.", 1336 /* IFP_TCAM_KEY_6_DOP */ "IFP_TCAM_KEY_6_DOP DOP description.", 1337 /* IFP_TCAM_KEY_7_DOP */ "IFP_TCAM_KEY_7_DOP DOP description.", 1338 /* IFP_TCAM_KEY_8_DOP */ "IFP_TCAM_KEY_8_DOP DOP description.", 1339 /* IFP_TCAM_KEY_9_DOP */ "IFP_TCAM_KEY_9_DOP DOP description.", 1340 /* IFP_TIMESTAMP_INSERTION_SET */ "PDD Output Bus generic format", 1341 /* IFP_TIMESTAMP_SET */ "Position and description of bits in the profile action set", 1342 /* IFP_TO_IFP_SHARED_CTR_BUS */ "control bus for ifp to ifp_shared logic, contains cmic and refresh signals", 1343 /* IFP_TO_IFP_SHARED_DATA_BUS */ "control bus for ifp_shared logic to ifp, contains normal function signals", 1344 /* IFP_TTL_OVERRIDE_SET */ "Position and description of bits in the profile action set", 1345 /* IFP_URPF_OVERRIDE_SET */ "Position and description of bits in the profile action set", 1346 /* IFWD1_DOP */ "Position and description of bits in IFWD1_DOP DOP chain", 1347 /* IFWD2_DOP */ "Position and description of bits in IFWD2_DOP DOP chain", 1348 /* IL2LU_DATA */ "Ingress Pipeline Learn Bus.", 1349 /* IL2LU_TO_L2_MGMT_STATUS */ "Per pipeline Status bus from IL2LU[0-3] to L2_MGMT.", 1350 /* INGRESS_ASSP_HEADER */ "FPGA-ASSP Egress Inter-chip Header", 1351 /* INGRESS_COUNTER_UPDATE_VECTOR */ "Bit Definitions of the Ingress counter update vector.", 1352 /* INGRESS_DOP_TOP_FORMAT */ "Top level DOP", 1353 /* INGRESS_FIELD_BUS */ "Ingress Field Bus flow from Parser to rest of ingress pipelien for various process. It is only valid for SOP cell.", 1354 /* INGRESS_FIELD_BUS_1_L2_FIELDS_DOP */ "INGRESS_FIELD_BUS_1_L2_FIELDS_DOP DOP description.", 1355 /* INGRESS_FIELD_BUS_1_L3_FIELDS_DOP */ "INGRESS_FIELD_BUS_1_L3_FIELDS_DOP DOP description.", 1356 /* INGRESS_FIELD_BUS_1_L4_FIELDS_DOP */ "INGRESS_FIELD_BUS_1_L4_FIELDS_DOP DOP description.", 1357 /* INGRESS_FIELD_BUS_2_L2_FIELDS_DOP */ "INGRESS_FIELD_BUS_2_L2_FIELDS_DOP DOP description.", 1358 /* INGRESS_FIELD_BUS_2_L3_FIELDS_DOP */ "INGRESS_FIELD_BUS_2_L3_FIELDS_DOP DOP description.", 1359 /* INGRESS_FIELD_BUS_2_L4_FIELDS_DOP */ "INGRESS_FIELD_BUS_2_L4_FIELDS_DOP DOP description.", 1360 /* INGRESS_OBJECT_BUS */ "Ingress Object Bus flow from Parser to rest of ingress pipelien for various process. It is only valid for SOP cell.", 1361 /* ING_DISTR_MONITOR_BUS_POOL */ "Distribution monitor define for a pool", 1362 /* ING_ECN_COUNTER_COV_DEFS */ "defines for num_qcn_cnm_received coverage analysis", 1363 /* ING_ETAG_PCP_MAPPING_INDEX */ "ING_ETAG_PCP_MAPPING index", 1364 /* ING_EXP_TO_ECN_MAPPING_INDEX */ "ING_EXP_TO_ECN_MAPPING index format.", 1365 /* ING_FLEX_CTR_ADDR_DEFINE */ "flex counters memory and register offset", 1366 /* ING_FLEX_CTR_BUS */ "flex counters bus define", 1367 /* ING_FLEX_CTR_BUS_POOL */ "flex counters bus define for a pool", 1368 /* ING_FLEX_CTR_COMPRESSED_PKT_ATTR */ "compressed packet attribute", 1369 /* ING_FLEX_CTR_PKT_ATTR */ "packet attribute", 1370 /* ING_FLEX_CTR_UDF */ "flex counters udf fields definition", 1371 /* ING_FLEX_CTR_UDF_PKT_ATTR */ "flex counters bus define for a pool", 1372 /* ING_NIV_RX_FRAMES_ERROR_DROP_COV_DEFS */ "defines for num_qcn_cnm_received coverage analysis", 1373 /* ING_NIV_RX_FRAMES_FORWARDING_DROP_COV_DEFS */ "defines for num_qcn_cnm_received coverage analysis", 1374 /* ING_NIV_RX_FRAMES_VLAN_TAGGED_COV_DEFS */ "defines for num_qcn_cnm_received coverage analysis", 1375 /* ING_PW_TERM_SEQ_NUM_COV_DEFS */ "defines for pw_term_seq_num coverage analysis", 1376 /* ING_Q_BUS */ "Bit Definitions of ING_Q_BUS.", 1377 /* ING_SVM_UDF_PKT_ATTR */ "svm udf define", 1378 /* ING_TRILL_RX_ACCESS_PORT_TRILL_PKTS_DISCARDED_COV_DEFS */ "defines for num_qcn_cnm_received coverage analysis", 1379 /* ING_TRILL_RX_NETWORK_PORT_NON_TRILL_PKTS_DISCARDED_COV_DEFS */ "defines for num_qcn_cnm_received coverage analysis", 1380 /* ING_TRILL_RX_PKTS_COV_DEFS */ "defines for num_qcn_cnm_received coverage analysis", 1381 /* ING_TUNNEL_ADAPT_1_DOP */ "ING_TUNNEL_ADAPT_1_DOP DOP description.", 1382 /* ING_TUNNEL_ADAPT_1_KEY_0_DOP */ "ING_TUNNEL_ADAPT_1_KEY_0_DOP DOP description.", 1383 /* ING_TUNNEL_ADAPT_1_KEY_1_DOP */ "ING_TUNNEL_ADAPT_1_KEY_1_DOP DOP description.", 1384 /* ING_TUNNEL_ADAPT_2_DOP */ "ING_TUNNEL_ADAPT_2_DOP DOP description.", 1385 /* ING_TUNNEL_ADAPT_2_KEY_0_DOP */ "ING_TUNNEL_ADAPT_2_KEY_0_DOP DOP description.", 1386 /* ING_TUNNEL_ADAPT_2_KEY_1_DOP */ "ING_TUNNEL_ADAPT_2_KEY_1_DOP DOP description.", 1387 /* ING_TUNNEL_ADAPT_3_LKUP_DOP */ "ING_TUNNEL_ADAPT_3_LKUP_DOP DOP description.", 1388 /* ING_TUNNEL_ADAPT_4_DOP */ "ING_TUNNEL_ADAPT_4_DOP DOP description.", 1389 /* ING_TUNNEL_ADAPT_4_KEY_0_DOP */ "ING_TUNNEL_ADAPT_4_KEY_0_DOP DOP description.", 1390 /* ING_TUNNEL_ADAPT_4_KEY_1_DOP */ "ING_TUNNEL_ADAPT_4_KEY_1_DOP DOP description.", 1391 /* ING_TUNNEL_ECN_DECAP_INDEX */ "ING_TUNNEL_ECN_DECAP index", 1392 /* INLINE_FF_KEY */ "This is the INLINE_LEARN Flop memory storage format.", 1393 /* INLINE_FF_KEY_INDEX */ "This is the INLINE_LEARN Flop memory storage format.", 1394 /* INLINE_LEARN_CONTEXT_BUFFER */ "This is the context buffer used to relay on EOP .", 1395 /* INLINE_LEARN_CONTEXT_BUFFER_WO_KEY */ "This is the context buffer used to relay on EOP .", 1396 /* INLINE_LEARN_SW_INSTRUTION */ "This is the context buffer used to relay on EOP .", 1397 /* INSTR_BUFFER_IADAPT_DW0 */ "DW0 of Instrumentation Result Buffer IADAPT.", 1398 /* INSTR_BUFFER_IFWD_DW0 */ "DW0 of Instrumentation Result Buffer IFWD.", 1399 /* INSTR_BUFFER_IFWD_DW1 */ "DW1 of Instrumentation Result Buffer IFWD.", 1400 /* INSTR_BUFFER_IFWD_DW2 */ "DW2 of Instrumentation Result Buffer IFWD.", 1401 /* INSTR_BUFFER_IFWD_DW3 */ "DW3 of Instrumentation Result Buffer IFWD.", 1402 /* INSTR_BUFFER_IPARS_DW0 */ "DW0 of Instrumentation Result Buffer IPARS.", 1403 /* INSTR_BUFFER_ISW1_DW0 */ "DW0 of Instrumentation Result Buffer ISW1.", 1404 /* INSTR_BUFFER_ISW1_DW1 */ "DW1 of Instrumentation Result Buffer ISW1.", 1405 /* INSTR_BUFFER_ISW1_DW2 */ "DW2 of Instrumentation Result Buffer ISW1.", 1406 /* INSTR_BUFFER_ISW1_DW3 */ "DW3 of Instrumentation Result Buffer ISW1.", 1407 /* INSTR_BUFFER_ISW2_DW0 */ "DW0 of Instrumentation Result Buffer ISW2.", 1408 /* INSTR_BUFFER_ISW2_DW1 */ "DW1 of Instrumentation Result Buffer ISW2.", 1409 /* INSTR_BUFFER_ISW2_DW2 */ "DW2 of Instrumentation Result Buffer ISW2.", 1410 /* INSTR_BUFFER_ISW2_DW3 */ "DW3 of Instrumentation Result Buffer ISW2.", 1411 /* INSTR_BUFFER_ISW2_DW4 */ "DW4 of Instrumentation Result Buffer ISW2.", 1412 /* INSTR_BUFFER_ISW2_DW5 */ "DW5 of Instrumentation Result Buffer ISW2.", 1413 /* INSTR_BUFFER_ISW2_DW6 */ "DW6 of Instrumentation Result Buffer ISW2.", 1414 /* INSTR_BUFFER_ISW2_DW7 */ "DW7 of Instrumentation Result Buffer ISW2.", 1415 /* INSTR_BUFFER_ISW_DW0 */ "DW0 of Instrumentation Result Buffer ISW.", 1416 /* INSTR_BUFFER_ISW_DW1 */ "DW1 of Instrumentation Result Buffer ISW.", 1417 /* INSTR_BUFFER_ISW_DW2 */ "DW2 of Instrumentation Result Buffer ISW.", 1418 /* INSTR_BUFFER_ISW_DW3 */ "DW3 of Instrumentation Result Buffer ISW.", 1419 /* INSTR_BUFFER_ISW_DW4 */ "DW4 of Instrumentation Result Buffer ISW.", 1420 /* INSTR_BUFFER_ISW_DW5 */ "DW5 of Instrumentation Result Buffer ISW.", 1421 /* INSTR_BUFFER_ISW_DW6 */ "DW6 of Instrumentation Result Buffer ISW.", 1422 /* INSTR_BUFFER_IVP_DW0 */ "DW0 of Instrumentation Result Buffer IVP.", 1423 /* INSTR_BUFFER_IVP_DW1 */ "DW1 of Instrumentation Result Buffer IVP.", 1424 /* INTFI_E2ECC_PKT */ "INTFI E2ECC packet format .", 1425 /* INTFI_OOB_HCFC_PKT */ "INTFI Out of Band HCFC packet format .", 1426 /* INTFI_TO_ES_S1 */ "INTFI to ES S1 LLFC format .", 1427 /* INTFI_TO_LLS_INFO */ "INTFI to LLS interface format", 1428 /* INTFI_TO_VBS */ "INTFI to VBS FC format.", 1429 /* INTF_ACTION_SET */ "PDD Output Bus generic format", 1430 /* IPAD_BUS */ "Ingress Pipeline Arbiter Data Bus", 1431 /* IPARS1_DOP */ "Position and description of bits in IPARS1_DOP DOP chain", 1432 /* IPARS2_0_DOP */ "IPARS2_0_DOP DOP description.", 1433 /* IPARS2_DOP */ "Position and description of bits in IPARS2_DOP DOP chain", 1434 /* IPARS_EOP_BUFFER */ "Bit Definitions of IPARS_EOP_BUFFER", 1435 /* IPARS_TO_IMPLS_FCOE_FIELDS_BUS */ "Bit Definitions of the VLAN drop vector.", 1436 /* IPARS_TO_IMPLS_IP_FIELDS_BUS */ "Bit Definitions of the VLAN drop vector.", 1437 /* IPARS_TO_IMPLS_L3_FIELDS_BUS */ "Bit Definitions of the VLAN drop vector.", 1438 /* IPARS_TO_IMPLS_OAM_FIELDS_BUS */ "Bit Definitions of the VLAN drop vector.", 1439 /* IPARS_TO_IMPLS_RTAG7_FIELDS_BUS */ "Bit Definitions of the RTAG7 fields bus from Ipars to Impls.", 1440 /* IPARS_TO_ISW2_BUS */ "Bit Definitions of IPARS_TO_ISW2_BUS.", 1441 /* IPFIX_DATA_INFO */ "Position and description of bits in Session table and Export FIFO DATA_INFO section", 1442 /* IPFIX_FLOW_COV_DEFS */ "defines for flow tracker session coverage analysis", 1443 /* IPFIX_IPV4_KEY */ "Position and description of bits in L2 Type KEY for IPFIX", 1444 /* IPFIX_IPV6_LOWER_KEY */ "Position and description of bits in IPV6 LOWER KEY for IPFIX", 1445 /* IPFIX_IPV6_UPPER_KEY */ "Position and description of bits in IPV6 UPPER KEY for IPFIX", 1446 /* IPFIX_L2_KEY */ "Position and description of bits in L2 Type KEY for IPFIX", 1447 /* IPFIX_SESSION_COV_DEFS */ "defines for flow tracker session coverage analysis", 1448 /* IPFIX_SESSION_INFO_ALL */ "Position and description of bits in SESSION_INFO sestion fo the IPFIX Session Table", 1449 /* IPFIX_SESSION_INFO_FIFO */ "Position and description of bits in SESSION_INFO section fo the IPFIX FIFO Table", 1450 /* IPMC_GRP_8_S_RF */ "ipmc group table s_rf width", 1451 /* IPMC_GRP_S_RF */ "ipmc group table s_rf width", 1452 /* IPMC_VLAN_S_RF */ "ipmc vlan table s_rf width", 1453 /* IPOST_CELL_QUEUES_DATA */ "Data to be stored in the per port cell queues in Ipost. Some of them (SOP/MOP/EOPs) are also used for controls.", 1454 /* IPOST_SLOT_PIPELINE_DATA */ "Ipost slot pipeline data", 1455 /* IPRC_BUS */ "Ingress Pipeline Resource Control Bus", 1456 /* IPRC_LEARN_BUS */ "IPRC Bus Format for L2 learning", 1457 /* IPROC_INTERRUPTS */ "iProc interrups", 1458 /* IPV4_HDR */ "IPv4 header specification", 1459 /* IPV6_HDR */ "IPv6 header specification", 1460 /* IP_AXP_INFO */ "Credit or other info from IP to AXP", 1461 /* IP_IN_IP_TUNNEL_ACTION_SET */ "PDD Output Bus generic format", 1462 /* IP_OPTION_CONTROL_PROFILE_TABLE_INDEX */ "IP_OPTION_CONTROL_PROFILE_TABLE index", 1463 /* IP_PARSER0_FLEX_HVE_CONTROLS */ "", 1464 /* IP_PARSER0_FLEX_HVE_IN_BUS */ "", 1465 /* IP_PARSER0_FLEX_HVE_OUT_BUS */ "", 1466 /* IP_PARSER0_FLEX_HVE_OUT_CHECK */ "", 1467 /* IP_PARSER0_HFE_CMD_POLICY_DATA */ "", 1468 /* IP_PARSER0_HFE_CONSTANTS */ "This defines constants for HFE", 1469 /* IP_PARSER0_HFE_CONTROLS */ "", 1470 /* IP_PARSER0_HFE_CONT_PROFILE */ "", 1471 /* IP_PARSER0_HFE_IN_BUS */ "", 1472 /* IP_PARSER0_HFE_MUX_CONTROLS */ "", 1473 /* IP_PARSER0_HFE_MUX_IN_BUS */ "", 1474 /* IP_PARSER0_HFE_MUX_OUT_BUS */ "", 1475 /* IP_PARSER0_HFE_OUT_BUS */ "", 1476 /* IP_PARSER0_HFE_POLICY_COMMAND_A */ "", 1477 /* IP_PARSER0_HFE_POLICY_COMMAND_B */ "", 1478 /* IP_PARSER0_HFE_POLICY_COMMAND_C */ "", 1479 /* IP_PARSER0_HFE_POLICY_COMMAND_D */ "", 1480 /* IP_PARSER0_HFE_POLICY_TABLE_DATA */ "", 1481 /* IP_PARSER0_HME_CONSTANTS */ "This defines constants for HFE", 1482 /* IP_PARSER0_HME_IN_BUS */ "", 1483 /* IP_PARSER0_HME_LATENCY_CONTROLS */ "This is contains various configuration control which impact latency of HME and hence driven from outside of parser.", 1484 /* IP_PARSER0_HME_OUT_BUS */ "", 1485 /* IP_PARSER0_HME_PASSTHROUGH_BUS */ "This is group of signals which are needed by HFE or MICE but are not part used by HME", 1486 /* IP_PARSER0_HME_POLICY_ACTION */ "", 1487 /* IP_PARSER0_HME_STAGE_COMMON_BUS */ "", 1488 /* IP_PARSER0_HME_STAGE_IN_BUS */ "", 1489 /* IP_PARSER0_HME_STAGE_KEY_VALID_BYTES_CHECK_DATA */ "Data for HME_STAGE_KEY_VALID_BYTES_CHECK_TABLE", 1490 /* IP_PARSER0_HME_STAGE_OUT_BUS */ "", 1491 /* IP_PARSER0_HME_STAGE_OUT_ONLY_BUS */ "", 1492 /* IP_PARSER0_HME_STAGE_PIPE_BUS */ "", 1493 /* IP_PARSER0_HME_STAGE_TCAM_DATA */ "", 1494 /* IP_PARSER0_HME_STAGE_TCAM_KEY */ "", 1495 /* IP_PARSER0_HME_STAGE_TCAM_KEY_NARROW */ "Data should always be kept at MSB. This will avoid mux in key generation.", 1496 /* IP_PARSER0_HVE_CONTROLS */ "", 1497 /* IP_PARSER0_HVE_IN_BUS */ "", 1498 /* IP_PARSER0_HVE_OUT_BUS */ "", 1499 /* IP_PARSER0_HVE_RC_PROFILE */ "", 1500 /* IP_PARSER0_HVE_SCC_PROFILE */ "", 1501 /* IP_PARSER0_HVE_SCF_PROFILE */ "", 1502 /* IP_PARSER0_IN_BUS */ "", 1503 /* IP_PARSER0_MICE_IN_BUS */ "", 1504 /* IP_PARSER0_MICE_OUT_BUS */ "", 1505 /* IP_PARSER0_OUT_BUS */ "", 1506 /* IP_PARSER0_TOP_HME_OUT_BUS */ "This is group of signals which go directly out of HME goes directly out of parser", 1507 /* IP_PARSER1_FLEX_HVE_CONTROLS */ "", 1508 /* IP_PARSER1_FLEX_HVE_IN_BUS */ "", 1509 /* IP_PARSER1_FLEX_HVE_OUT_BUS */ "", 1510 /* IP_PARSER1_FLEX_HVE_OUT_CHECK */ "", 1511 /* IP_PARSER1_HFE_CMD_POLICY_DATA */ "", 1512 /* IP_PARSER1_HFE_CONSTANTS */ "This defines constants for HFE", 1513 /* IP_PARSER1_HFE_CONTROLS */ "", 1514 /* IP_PARSER1_HFE_CONT_PROFILE */ "", 1515 /* IP_PARSER1_HFE_IN_BUS */ "", 1516 /* IP_PARSER1_HFE_MUX_CONTROLS */ "", 1517 /* IP_PARSER1_HFE_MUX_IN_BUS */ "", 1518 /* IP_PARSER1_HFE_MUX_OUT_BUS */ "", 1519 /* IP_PARSER1_HFE_OUT_BUS */ "", 1520 /* IP_PARSER1_HFE_POLICY_COMMAND_A */ "", 1521 /* IP_PARSER1_HFE_POLICY_COMMAND_B */ "", 1522 /* IP_PARSER1_HFE_POLICY_COMMAND_C */ "", 1523 /* IP_PARSER1_HFE_POLICY_COMMAND_D */ "", 1524 /* IP_PARSER1_HFE_POLICY_TABLE_DATA */ "", 1525 /* IP_PARSER1_HME_CONSTANTS */ "This defines constants for HFE", 1526 /* IP_PARSER1_HME_IN_BUS */ "", 1527 /* IP_PARSER1_HME_LATENCY_CONTROLS */ "This is contains various configuration control which impact latency of HME and hence driven from outside of parser.", 1528 /* IP_PARSER1_HME_OUT_BUS */ "", 1529 /* IP_PARSER1_HME_PASSTHROUGH_BUS */ "This is group of signals which are needed by HFE or MICE but are not part used by HME", 1530 /* IP_PARSER1_HME_POLICY_ACTION */ "", 1531 /* IP_PARSER1_HME_STAGE_COMMON_BUS */ "", 1532 /* IP_PARSER1_HME_STAGE_IN_BUS */ "", 1533 /* IP_PARSER1_HME_STAGE_KEY_VALID_BYTES_CHECK_DATA */ "Data for HME_STAGE_KEY_VALID_BYTES_CHECK_TABLE", 1534 /* IP_PARSER1_HME_STAGE_OUT_BUS */ "", 1535 /* IP_PARSER1_HME_STAGE_OUT_ONLY_BUS */ "", 1536 /* IP_PARSER1_HME_STAGE_PIPE_BUS */ "", 1537 /* IP_PARSER1_HME_STAGE_TCAM_DATA */ "", 1538 /* IP_PARSER1_HME_STAGE_TCAM_KEY */ "", 1539 /* IP_PARSER1_HME_STAGE_TCAM_KEY_NARROW */ "Data should always be kept at MSB. This will avoid mux in key generation.", 1540 /* IP_PARSER1_HVE_CONTROLS */ "", 1541 /* IP_PARSER1_HVE_IN_BUS */ "", 1542 /* IP_PARSER1_HVE_OUT_BUS */ "", 1543 /* IP_PARSER1_HVE_RC_PROFILE */ "", 1544 /* IP_PARSER1_HVE_SCC_PROFILE */ "", 1545 /* IP_PARSER1_HVE_SCF_PROFILE */ "", 1546 /* IP_PARSER1_IN_BUS */ "", 1547 /* IP_PARSER1_MICE_IN_BUS */ "", 1548 /* IP_PARSER1_MICE_OUT_BUS */ "", 1549 /* IP_PARSER1_MICE_TCAM_DATA */ "", 1550 /* IP_PARSER1_MICE_TCAM_KEY */ "", 1551 /* IP_PARSER1_OUT_BUS */ "", 1552 /* IP_PARSER1_TOP_HME_OUT_BUS */ "This is group of signals which go directly out of HME goes directly out of parser", 1553 /* IP_PARSER2_FLEX_HVE_CONTROLS */ "", 1554 /* IP_PARSER2_FLEX_HVE_IN_BUS */ "", 1555 /* IP_PARSER2_FLEX_HVE_OUT_BUS */ "", 1556 /* IP_PARSER2_FLEX_HVE_OUT_CHECK */ "", 1557 /* IP_PARSER2_HFE_CMD_POLICY_DATA */ "", 1558 /* IP_PARSER2_HFE_CONSTANTS */ "This defines constants for HFE", 1559 /* IP_PARSER2_HFE_CONTROLS */ "", 1560 /* IP_PARSER2_HFE_CONT_PROFILE */ "", 1561 /* IP_PARSER2_HFE_IN_BUS */ "", 1562 /* IP_PARSER2_HFE_MUX_CONTROLS */ "", 1563 /* IP_PARSER2_HFE_MUX_IN_BUS */ "", 1564 /* IP_PARSER2_HFE_MUX_OUT_BUS */ "", 1565 /* IP_PARSER2_HFE_OUT_BUS */ "", 1566 /* IP_PARSER2_HFE_POLICY_COMMAND_A */ "", 1567 /* IP_PARSER2_HFE_POLICY_COMMAND_B */ "", 1568 /* IP_PARSER2_HFE_POLICY_COMMAND_C */ "", 1569 /* IP_PARSER2_HFE_POLICY_COMMAND_D */ "", 1570 /* IP_PARSER2_HFE_POLICY_TABLE_DATA */ "", 1571 /* IP_PARSER2_HME_CONSTANTS */ "This defines constants for HFE", 1572 /* IP_PARSER2_HME_IN_BUS */ "", 1573 /* IP_PARSER2_HME_LATENCY_CONTROLS */ "This is contains various configuration control which impact latency of HME and hence driven from outside of parser.", 1574 /* IP_PARSER2_HME_OUT_BUS */ "", 1575 /* IP_PARSER2_HME_PASSTHROUGH_BUS */ "This is group of signals which are needed by HFE or MICE but are not part used by HME", 1576 /* IP_PARSER2_HME_POLICY_ACTION */ "", 1577 /* IP_PARSER2_HME_STAGE_COMMON_BUS */ "", 1578 /* IP_PARSER2_HME_STAGE_IN_BUS */ "", 1579 /* IP_PARSER2_HME_STAGE_KEY_VALID_BYTES_CHECK_DATA */ "Data for HME_STAGE_KEY_VALID_BYTES_CHECK_TABLE", 1580 /* IP_PARSER2_HME_STAGE_OUT_BUS */ "", 1581 /* IP_PARSER2_HME_STAGE_OUT_ONLY_BUS */ "", 1582 /* IP_PARSER2_HME_STAGE_PIPE_BUS */ "", 1583 /* IP_PARSER2_HME_STAGE_TCAM_DATA */ "", 1584 /* IP_PARSER2_HME_STAGE_TCAM_KEY */ "", 1585 /* IP_PARSER2_HME_STAGE_TCAM_KEY_NARROW */ "Data should always be kept at MSB. This will avoid mux in key generation.", 1586 /* IP_PARSER2_HVE_CONTROLS */ "", 1587 /* IP_PARSER2_HVE_IN_BUS */ "", 1588 /* IP_PARSER2_HVE_OUT_BUS */ "", 1589 /* IP_PARSER2_HVE_RC_PROFILE */ "", 1590 /* IP_PARSER2_HVE_SCC_PROFILE */ "", 1591 /* IP_PARSER2_HVE_SCF_PROFILE */ "", 1592 /* IP_PARSER2_IN_BUS */ "", 1593 /* IP_PARSER2_MICE_IN_BUS */ "", 1594 /* IP_PARSER2_MICE_OUT_BUS */ "", 1595 /* IP_PARSER2_MICE_TCAM_DATA */ "", 1596 /* IP_PARSER2_MICE_TCAM_KEY */ "", 1597 /* IP_PARSER2_OUT_BUS */ "", 1598 /* IP_PARSER2_TOP_HME_OUT_BUS */ "This is group of signals which go directly out of HME goes directly out of parser", 1599 /* IP_PARSER_0_HME_STAGE_TCAM_DOP */ "IP_PARSER_0_HME_STAGE_TCAM_DOP DOP description.", 1600 /* IP_PROTOCOL */ "In the Internet Protocol version 4 (IPv4) (RFC791) there is a field called Protocol to identify the next level protocol. This is an 8 bit field. In Internet Protocol version 6 (IPv6) (RFC1883), this field is called the Next Header field.", 1601 /* IP_SBUS_META_DATA */ "ip sbus meta data is the input of ip sbus master.", 1602 /* IQ_BUS */ "Ingress Pipeline Q-Bus format - spare bits", 1603 /* IRSEL1_DOP */ "Position and description of bits in IRSEL1_DOP DOP chain", 1604 /* IRSEL1_TO_L2_MGMT_L2_BUS */ "Per pipeline L2 bus from IRSEL1[0-3] to L2_MGMT. Both Learn_bus and L2_LOOKUP / L2_MEMRD data is returned on this shared bus.", 1605 /* IRSEL2_DOP */ "Position and description of bits in IRSEL2_DOP DOP chain", 1606 /* IRSEL2_NHOP_COMMON_COV_DEFS */ "defines for Irsel2 nhop common coverage analysis", 1607 /* ISC_HG_STATS_COV_DEFS */ "defines for num_qcn_cnm_received coverage analysis", 1608 /* ISC_IP_STATS_COV_DEFS */ "defines for num_qcn_cnm_received coverage analysis", 1609 /* ISC_STATS_INST0_COV_DEFS */ "defines for num_qcn_cnm_received coverage analysis", 1610 /* ISC_STATS_INST1_COV_DEFS */ "defines for num_qcn_cnm_received coverage analysis", 1611 /* ISC_STATS_INST2_COV_DEFS */ "defines for num_qcn_cnm_received coverage analysis", 1612 /* ISC_STATS_INST3_COV_DEFS */ "defines for num_qcn_cnm_received coverage analysis", 1613 /* ISC_STATS_INST4_COV_DEFS */ "defines for num_qcn_cnm_received coverage analysis", 1614 /* ISM_ENTRY_16KBY420_2P_COV_DEFS */ "defines for l3_ecmp round-robin count coverage analysis", 1615 /* ISM_ENTRY_1BASE_2P_COV_DEFS */ "defines for Hash Table IP Search Bank rams", 1616 /* ISM_ENTRY_1BASE_4P_COV_DEFS */ "defines for Hash Table IP Search Bank rams", 1617 /* ISM_ENTRY_2BASE_2P_COV_DEFS */ "defines for Hash Table IP Search Bank rams", 1618 /* ISM_ENTRY_2BASE_4P_COV_DEFS */ "defines for Hash Table IP Search Bank rams", 1619 /* ISM_ENTRY_4BASE_2P_COV_DEFS */ "defines for Hash Table IP Search Bank rams", 1620 /* ISM_ENTRY_4BASE_4P_COV_DEFS */ "defines for Hash Table IP Search Bank rams", 1621 /* ISM_ENTRY_8KBY105_2P_COV_DEFS */ "defines for l3_ecmp round-robin count coverage analysis", 1622 /* ISM_ENTRY_8KBY140_2P_COV_DEFS */ "defines for l3_ecmp round-robin count coverage analysis", 1623 /* ISM_LEARN_BUS */ "ISM Learn Bus.", 1624 /* ISM_RSP_WORD */ "ALWAYS sent as 32 lsbs for sbus_req: INSERT, DELETE, LOOKUP.", 1625 /* ISW1_DROP */ "Bit Definitions of the ISW1 drop vector", 1626 /* ISW1_PROTOCOL_PKT */ "Ingress Pipeline Sw1 Protocol Pkt", 1627 /* ISW1_TO_L2_MGMT_L2_BUS */ "Per pipeline L2 bus from ISW1[0-3] to L2_MGMT. Both Learn_bus and L2_LOOKUP / L2_MEMRD data is returned on this shared bus.", 1628 /* ISW2_DOP */ "Position and description of bits in ISW2_DOP DOP chain", 1629 /* ISW2_TO_ICFG_BUS */ "Bit Definitions of ISW2_TO_ICFG_BUS.", 1630 /* ISW2_TO_IPARS_BUS */ "Bit Definitions of ISW2_TO_IPARS_BUS.", 1631 /* ISW3_DOP */ "Position and description of bits in ISW3_DOP DOP chain", 1632 /* ISW3_DROP */ "Bit Definitions of the ISW3 drop vector.", 1633 /* ISW3_TO_IPARS_BUS */ "Bit Definitions of ISW3_TO_IPARS_BUS.", 1634 /* ISW3_TO_ISW4_BUS */ "Position and description of bits in Isw3(DPP) to Isw4 bus. Equivalently, this is the content of DPP output event fifo", 1635 /* ISW4_CELL_QUEUES_DATA */ "Data to be stored in the per port cell queues in Isw4. Some of them (SOP/MOP/EOPs) are also used for controls.", 1636 /* ISW4_SLOT_PIPELINE_DATA */ "Isw4 slot pipeline data", 1637 /* ISW_TO_IPOST_BUS */ "Position and description of bits in Isw3(DPP) to Isw4 bus. Equivalently, this is the content of DPP output event fifo", 1638 /* ITAG_ACTION_SET */ "PDD Output Bus generic format", 1639 /* ITAG_HDR */ "4BYTES OF ETAG HEADER AFTER ETHERTYPE.", 1640 /* ITE_TO_EMC_WR_INFO */ "ITE to EMC cell write", 1641 /* ITE_TO_RQE_EXT_INFO */ "Position and description of bits", 1642 /* ITE_TO_TOQ_WCE_INFO */ "Position and description of bits", 1643 /* ITE_WORK_QUEUE_MEM */ "ITE_WORK_QUEUE Memory contents", 1644 /* IVLAN_ACTION_SET */ "PDD Output Bus generic format", 1645 /* IVP_DOP */ "Position and description of bits in IVP_DOP DOP chain", 1646 /* IVXLT1_DOP */ "Position and description of bits in IVXLT1_DOP DOP chain", 1647 /* IVXLT2_DOP */ "Position and description of bits in IVXLT2_DOP DOP chain", 1648 /* JTAG_OTP_CNTRL_FORMAT */ "JTAG_OTP_CONTROL_REG BIT ASSIGNMENT", 1649 /* JTAG_OTP_STATUS_FORMAT */ "JTAG_OTP_CONTROL_REG BIT ASSIGNMENT", 1650 /* KEY_ATTRIBUTES */ "KEY_ATTRIBUTES Table Format.", 1651 /* L2_BITMAP_DOP */ "L2_BITMAP_DOP DOP description.", 1652 /* L2_EDIT_CONTROLS_ACTION_SET */ "PDD Output Bus generic format", 1653 /* L2_ENTRY_1_DATA */ "Format for L2_ENTRY_1 DATA.", 1654 /* L2_ENTRY_2_DATA */ "Format for L2_ENTRY_2 DATA.", 1655 /* L2_ENTRY_KEY */ "Format for L2_ENTRY_1, L2_ENTRY_2 KEY.", 1656 /* L2_ENTRY_KEY_TYPE */ "L2_ENTRY Key Types", 1657 /* L2_FWD_TABLE_ATTRIBUTES */ "Bit definition for L2 Fordwarding attributes.", 1658 /* L2_GRE_HDR */ "GRE header specification", 1659 /* L2_MEMBERSHIP_CONTROLS_ACTION_SET */ "PDD Output Bus generic format", 1660 /* L2_MGMT_TO_IARB_REQ */ "Requst Bus from L2_MGMT to IARB[0-3].", 1661 /* L2_TAG_INHERIT_ACTION_FORMAT */ "L2_TAG_INHERIT_ACTION format.", 1662 /* L2_USER_ENTRY_DATA_FORMAT */ "format for L2_USER_ENTRY data", 1663 /* L2_USER_ENTRY_DOP */ "L2_USER_ENTRY_DOP DOP description.", 1664 /* L2_USER_ENTRY_KEY_TYPE */ "L2_USER_ENTRY Key Types", 1665 /* L2_USER_ENTRY_TCAM_FORMAT */ "format for L2_USER_ENTRY TCAM", 1666 /* L3MC_MAC_DA_UPDATE_ACTION_SET */ "PDD Output Bus generic format", 1667 /* L3_BITMAP_DOP */ "L3_BITMAP_DOP DOP description.", 1668 /* L3_DEFIP_ALPM_HIT_ONLY_COV_DEFS */ "defines for l3 defip alpm entry hit only coverage analysis", 1669 /* L3_DEFIP_ALPM_PIVOT_FMT1 */ "L3 Defip ALPM Pivot Associated Data FMT1. 10 bytes, 6 entries per bank.", 1670 /* L3_DEFIP_ALPM_PIVOT_FMT2 */ "L3 Defip ALPM Pivot Associated Data FMT2. 12 bytes, 5 entries per bank.", 1671 /* L3_DEFIP_ALPM_PIVOT_FMT3 */ "L3 Defip ALPM Pivot Associated Data FMT3. 15 bytes, 4 entries per bank.", 1672 /* L3_DEFIP_ALPM_PIVOT_FMT4 */ "L3 Defip ALPM Pivot Associated Data FMT4. 20 bytes, 3 entries per bank.", 1673 /* L3_DEFIP_ALPM_PIVOT_FMT5 */ "L3 Defip ALPM Pivot Associated Data FMT5. 26 bytes, 2 entries per bank.", 1674 /* L3_DEFIP_ALPM_PIVOT_FMT6 */ "L3 Defip ALPM Pivot Associated Data FMT6. 15 bytes, 4 entries per bank.", 1675 /* L3_DEFIP_ALPM_PIVOT_FMT7 */ "L3 Defip ALPM Pivot Associated Data FMT7. 20 bytes, 3 entries per bank.", 1676 /* L3_DEFIP_ALPM_PIVOT_FMT8 */ "L3 Defip ALPM Pivot Associated Data FMT8. 29 bytes, 2 entries per bank.", 1677 /* L3_DEFIP_ALPM_PIVOT_FMT1_FULL */ "L3 Defip ALPM Pivot Associated Data FMT1. 10 bytes, 6 entries per bank.", 1678 /* L3_DEFIP_ALPM_PIVOT_FMT2_FULL */ "L3 Defip ALPM Pivot Associated Data FMT2. 12 bytes, 5 entries per bank.", 1679 /* L3_DEFIP_ALPM_PIVOT_FMT3_FULL */ "L3 Defip ALPM Pivot Associated Data FMT3. 15 bytes, 4 entries per bank.", 1680 /* L3_DEFIP_ALPM_PIVOT_FMT4_FULL */ "L3 Defip ALPM Pivot Associated Data FMT4. 20 bytes, 3 entries per bank.", 1681 /* L3_DEFIP_ALPM_PIVOT_FMT5_FULL */ "L3 Defip ALPM Pivot Associated Data FMT5. 28 bytes, 2 entries per bank.", 1682 /* L3_DEFIP_ALPM_PIVOT_FMT6_FULL */ "L3 Defip ALPM Pivot Associated Data FMT6. 15 bytes, 4 entries per bank.", 1683 /* L3_DEFIP_ALPM_PIVOT_FMT7_FULL */ "L3 Defip ALPM Pivot Associated Data FMT7. 20 bytes, 3 entries per bank.", 1684 /* L3_DEFIP_ALPM_PIVOT_FMT8_FULL */ "L3 Defip ALPM Pivot Associated Data FMT8. 29 bytes, 2 entries per bank.", 1685 /* L3_DEFIP_ALPM_ROUTE_FMT1 */ "L3 Defip ALPM Route Associated Data FMT1. 9 bytes, 6 entries per bank. (L3_DEFIP_ALPM_V4)", 1686 /* L3_DEFIP_ALPM_ROUTE_FMT2 */ "L3 Defip ALPM Route Associated Data FMT1. 14 bytes, 4 entries per bank. (L3_DEFIP_ALPM_V6_64)", 1687 /* L3_DEFIP_ALPM_ROUTE_FMT3 */ "L3 Defip ALPM Route Associated Data FMT1. 27 bytes, 2 entries per bank. (L3_DEFIP_ALPM_V6_128)", 1688 /* L3_DEFIP_ALPM_ROUTE_FMT4 */ "L3 Defip ALPM Route Associated Data FMT1. 14 bytes, 4 entries per bank. (L3_DEFIP_ALPM_V4_1)", 1689 /* L3_DEFIP_ALPM_ROUTE_FMT5 */ "L3 Defip ALPM Route Associated Data FMT1. 18 bytes, 3 entries per bank. (L3_DEFIP_ALPM_V6_64_1)", 1690 /* L3_DEFIP_ALPM_ROUTE_FMT6 */ "L3 Defip ALPM Route Associated Data FMT6. 10 bytes, 6 entries per bank.", 1691 /* L3_DEFIP_ALPM_ROUTE_FMT7 */ "L3 Defip ALPM Route Associated Data FMT7. 12 bytes, 5 entries per bank.", 1692 /* L3_DEFIP_ALPM_ROUTE_FMT8 */ "L3 Defip ALPM Route Associated Data FMT8. 15 bytes, 4 entries per bank.", 1693 /* L3_DEFIP_ALPM_ROUTE_FMT9 */ "L3 Defip ALPM Route Associated Data FMT9. 19 bytes, 3 entries per bank.", 1694 /* L3_DEFIP_ALPM_ROUTE_FMT10 */ "L3 Defip ALPM Route Associated Data FMT10. 10 bytes, 6 entries per bank.", 1695 /* L3_DEFIP_ALPM_ROUTE_FMT11 */ "L3 Defip ALPM Route Associated Data FMT11. 15 bytes, 4 entries per bank.", 1696 /* L3_DEFIP_ALPM_ROUTE_FMT12 */ "L3 Defip ALPM Route Associated Data FMT12. 22 bytes, 2 entries per bank.", 1697 /* L3_DEFIP_ALPM_ROUTE_FMT13 */ "L3 Defip ALPM Route Associated Data FMT1. 3 bytes, 20 entries per bank.", 1698 /* L3_DEFIP_ALPM_ROUTE_FMT10_FULL */ "L3 Defip ALPM Route Associated Data FMT10. 10 bytes, 6 entries per bank.", 1699 /* L3_DEFIP_ALPM_ROUTE_FMT11_FULL */ "L3 Defip ALPM Route Associated Data FMT11. 15 bytes, 4 entries per bank.", 1700 /* L3_DEFIP_ALPM_ROUTE_FMT12_FULL */ "L3 Defip ALPM Route Associated Data FMT12. 22 bytes, 2 entries per bank.", 1701 /* L3_DEFIP_ALPM_ROUTE_FMT13_FULL */ "L3 Defip ALPM Route Associated Data FMT1. 3 bytes, 20 entries per bank.", 1702 /* L3_DEFIP_ALPM_ROUTE_FMT1_FULL */ "L3 Defip ALPM Route Associated Data FMT1. 9 bytes, 6 entries per bank. (L3_DEFIP_ALPM_V4)", 1703 /* L3_DEFIP_ALPM_ROUTE_FMT2_FULL */ "L3 Defip ALPM Route Associated Data FMT1. 14 bytes, 4 entries per bank. (L3_DEFIP_ALPM_V6_64)", 1704 /* L3_DEFIP_ALPM_ROUTE_FMT3_FULL */ "L3 Defip ALPM Route Associated Data FMT1. 27 bytes, 2 entries per bank. (L3_DEFIP_ALPM_V6_128)", 1705 /* L3_DEFIP_ALPM_ROUTE_FMT4_FULL */ "L3 Defip ALPM Route Associated Data FMT1. 14 bytes, 4 entries per bank. (L3_DEFIP_ALPM_V4_1)", 1706 /* L3_DEFIP_ALPM_ROUTE_FMT5_FULL */ "L3 Defip ALPM Route Associated Data FMT1. 18 bytes, 3 entries per bank. (L3_DEFIP_ALPM_V6_64_1)", 1707 /* L3_DEFIP_ALPM_ROUTE_FMT6_FULL */ "L3 Defip ALPM Route Associated Data FMT6. 10 bytes, 6 entries per bank.", 1708 /* L3_DEFIP_ALPM_ROUTE_FMT7_FULL */ "L3 Defip ALPM Route Associated Data FMT7. 12 bytes, 5 entries per bank.", 1709 /* L3_DEFIP_ALPM_ROUTE_FMT8_FULL */ "L3 Defip ALPM Route Associated Data FMT8. 15 bytes, 4 entries per bank.", 1710 /* L3_DEFIP_ALPM_ROUTE_FMT9_FULL */ "L3 Defip ALPM Route Associated Data FMT9. 19 bytes, 3 entries per bank.", 1711 /* L3_DEFIP_DATA_0_COV_DEFS */ "defines for l3_defip_data ram 0 coverage analysis, rtl bypass covers a write on Port B colliding at the same addr as a read on Port A", 1712 /* L3_DEFIP_DATA_1_COV_DEFS */ "defines for l3_defip_data ram 0 coverage analysis, rtl bypass covers a write on Port B colliding at the same addr as a read on Port A", 1713 /* L3_DEFIP_DATA_2_COV_DEFS */ "defines for l3_defip_data ram 0 coverage analysis, rtl bypass covers a write on Port B colliding at the same addr as a read on Port A", 1714 /* L3_DEFIP_DATA_3_COV_DEFS */ "defines for l3_defip_data ram 0 coverage analysis, rtl bypass covers a write on Port B colliding at the same addr as a read on Port A", 1715 /* L3_DEFIP_DATA_4_COV_DEFS */ "defines for l3_defip_data ram 0 coverage analysis, rtl bypass covers a write on Port B colliding at the same addr as a read on Port A", 1716 /* L3_DEFIP_DATA_5_COV_DEFS */ "defines for l3_defip_data ram 0 coverage analysis, rtl bypass covers a write on Port B colliding at the same addr as a read on Port A", 1717 /* L3_DEFIP_DATA_6_COV_DEFS */ "defines for l3_defip_data ram 0 coverage analysis, rtl bypass covers a write on Port B colliding at the same addr as a read on Port A", 1718 /* L3_DEFIP_DATA_7_COV_DEFS */ "defines for l3_defip_data ram 0 coverage analysis, rtl bypass covers a write on Port B colliding at the same addr as a read on Port A", 1719 /* L3_DEFIP_HIT_ONLY_COV_DEFS */ "defines for l3 defip entry hit only coverage analysis", 1720 /* L3_DEFIP_TCAM_KEY */ "L3_DEFIP_TCAM_LEVEL1 Key Format.", 1721 /* L3_ECMP_GROUP_A_RRLB_CNT_COV_DEFS */ "defines for l3_ecmp round-robin count coverage analysis", 1722 /* L3_ECMP_GROUP_B_RRLB_CNT_COV_DEFS */ "defines for l3_ecmp round-robin count coverage analysis", 1723 /* L3_ECMP_GROUP_RRLB_CNT_0_COV_DEFS */ "defines for l3_ecmp round-robin count coverage analysis", 1724 /* L3_ECMP_GROUP_RRLB_CNT_1_COV_DEFS */ "defines for l3_ecmp round-robin count coverage analysis", 1725 /* L3_ECMP_GROUP_RRLB_CNT_2_COV_DEFS */ "defines for l3_ecmp round-robin count coverage analysis", 1726 /* L3_ECMP_GROUP_RRLB_CNT_3_COV_DEFS */ "defines for l3_ecmp round-robin count coverage analysis", 1727 /* L3_ECMP_GROUP_RRLB_CNT_4_COV_DEFS */ "defines for l3_ecmp round-robin count coverage analysis", 1728 /* L3_ECMP_GROUP_RRLB_CNT_5_COV_DEFS */ "defines for l3_ecmp round-robin count coverage analysis", 1729 /* L3_ECMP_GROUP_RRLB_CNT_6_COV_DEFS */ "defines for l3_ecmp round-robin count coverage analysis", 1730 /* L3_ECMP_GROUP_RRLB_CNT_7_COV_DEFS */ "defines for l3_ecmp round-robin count coverage analysis", 1731 /* L3_ENTRY_1_DATA */ "Format for L3_ENTRY_1 DATA.", 1732 /* L3_ENTRY_2_DATA */ "Format for L3_ENTRY_2 DATA.", 1733 /* L3_ENTRY_4_DATA */ "Format for L3_ENTRY_4 DATA.", 1734 /* L3_ENTRY_HIT_ONLY_COV_DEFS */ "defines for l3 entry hit only coverage analysis", 1735 /* L3_ENTRY_KEY */ "Format for L3_ENTRY_1 KEY (keys unique to L3_ENTRY_1).", 1736 /* L3_FWD_TABLE_ATTRIBUTES */ "Bit definition for L3 Fordwarding attributes.", 1737 /* L3_GRE_HDR */ "L3 GRE header specification", 1738 /* L3_IIF_SOURCE */ "Denote the source where L3_IIF is from.", 1739 /* L3_TUNNEL_DEFAULT_VLAN_ACTION_SET */ "PDD Output Bus generic format", 1740 /* L3_TYPE */ "Description of encodings of L3_TYPE.", 1741 /* L4_PORT */ "The well known ports are assigned by IANA in the range of 0 to 1023.", 1742 /* LAG_RH_ACTION_SET */ "PDD Output Bus generic format", 1743 /* LB_MH_BASE */ "Common fields in all loopback headers", 1744 /* LB_MH_EP_REDIRECT */ "Bit Definitions of the EP Redirect Module Header", 1745 /* LB_MH_MIM */ "Bit Definitions of the MAC-in-MAC Module Header", 1746 /* LB_MH_WLAN */ "Bit Definitions of the WLAN Module Header", 1747 /* LEARN_BUS */ "Ingress Pipeline Learn Bus", 1748 /* LEARN_DATA */ "Ingress Pipeline Learn Bus.", 1749 /* LEVEL1_DATA_REQ_BUS */ "Level1 DATA Req Bus.", 1750 /* LEVEL1_DATA_RST_BUS */ "Level1 DATA Result Bus.", 1751 /* LEVEL1_REQ_BUS */ "Level1 Req Bus.", 1752 /* LEVEL1_RST_BUS */ "Level1 Result Bus.", 1753 /* LEVEL1_TCAM_REQ_BUS */ "Level1 TCAM Req Bus.", 1754 /* LEVEL1_TCAM_RST_BUS */ "Level1 TCAM Result Bus.", 1755 /* LLC_HDR */ "LLC header specification", 1756 /* LMFC_COMMON_BUS */ "Signals that are common to all interfaces", 1757 /* LMFC_COUNTER_POOL_BUS */ "Fields required to update each counter pool.", 1758 /* LMFC_EOP_BUFFER */ "EOP Context buffer.", 1759 /* LMFC_INT_CNTR_BUS */ "Bus from Interface Resolution Block to individual counter pools.", 1760 /* LMFC_IN_BUS */ "Input bus to module.", 1761 /* LMFC_OUT_BUS */ "Module output Bus.", 1762 /* LMFC_PARITY_STATUS_BUS */ "Parity Status Bus.", 1763 /* LMFC_SAMPLE_DATA */ "Bus format for read data from each pool.", 1764 /* LMFC_SRC_INTF_BUS */ "Interface bus for various sources: TX/IFP based MEPs/Native MEPs", 1765 /* LMFC_SRC_INTF_COMMON_BUS */ "Fields in this bus are applicable to all counter pools.", 1766 /* LOOPBACK_MH */ "Bit Definitions of the Loopback Module Header", 1767 /* LPM_IN_BUS */ "LPM core input bus format.", 1768 /* LPM_IN_BUS_2 */ "LPM core input bus format.", 1769 /* LPM_IP_BUS_L1L2_TO_L3 */ "L3 Defip ALPM Route Associated Data FMT7. 12 bytes, 5 entries per bank.", 1770 /* LPM_IP_CONTROL_FULL_SET */ "LPM IP CONTROL Full Set.", 1771 /* LPM_OUT_BUS */ "LPM core output bus format.", 1772 /* LP_HEADER_ETH_MODE */ "", 1773 /* LP_HEADER_TCI_LENGTH_MODE */ "", 1774 /* MAC_BLOCK_ACTION_SET */ "PDD Output Bus generic format", 1775 /* MAC_HDR */ "Ethernet MAC specification", 1776 /* MAC_IP_BIND_ACTION_SET */ "PDD Output Bus generic format", 1777 /* MAC_RRSV */ "Recieved runt packet status vector", 1778 /* MAC_RSV */ "Recieved packet status vector", 1779 /* MAC_RSV_PFC */ "Recieved packet PFC status vector", 1780 /* MAC_TSV */ "Transmit packet status vector", 1781 /* MATCH_ID_DOP */ "MATCH_ID_DOP DOP description.", 1782 /* MATCH_ID_DOP_DOP */ "MATCH_ID_DOP_DOP DOP description.", 1783 /* MA_STATE_COV_DEFS */ "defines for flex_ctr coverage analysis", 1784 /* MB_TCB_TO_DEQ_ECC_INFO */ "Position and description of bits", 1785 /* MB_TO_DQX_HDRMISC_INFO */ "Position and description of bits in the MB to DQX HDRMISC INFO bus.", 1786 /* MCQ_QDB */ "Position and description of bits in the MCQ QDB register", 1787 /* MC_INDICES_DOP */ "MC_INDICES_DOP DOP description.", 1788 /* MEMADDR */ "Memory Address Format.", 1789 /* MEMADR_EGR_FLEX_PREEMPT_LOOKUP */ "Address to physical memory EGR_FLEX_PREEMPT_LOOKUP", 1790 /* MEMADR_EGR_FLEX_PREEMPT_XFR_COUNT */ "", 1791 /* MIB_MEMORY_ROW0 */ "Row 0 of PM8x50 MIB memory. All 8 ports have the same MIB format", 1792 /* MIB_MEMORY_ROW1 */ "Row 1 of PM8x50 MIB memory. All 8 ports have the same MIB format", 1793 /* MIB_MEMORY_ROW2 */ "Row 2 of PM8x50 MIB memory. All 8 ports have the same MIB format", 1794 /* MIB_MEMORY_ROW3 */ "Row 3 of PM8x50 MIB memory. All 8 ports have the same MIB format", 1795 /* MIB_MEMORY_ROW4 */ "Row 4 of PM8x50 MIB memory. All 8 ports have the same MIB format", 1796 /* MIB_MEMORY_ROW5 */ "Row 5 of PM8x50 MIB memory. All 8 ports have the same MIB format", 1797 /* MIB_MEMORY_ROW6 */ "Row 6 of PM8x50 MIB memory. All 8 ports have the same MIB format", 1798 /* MIB_MEMORY_ROW7 */ "Row 7 of PM8x50 MIB memory. All 8 ports have the same MIB format", 1799 /* MIB_MEMORY_ROW8 */ "Row 8 of PM8x50 MIB memory. All 8 ports have the same MIB format", 1800 /* MIB_MEMORY_ROW9 */ "Row 9 of PM8x50 MIB memory. All 8 ports have the same MIB format", 1801 /* MIB_MEMORY_ROW10 */ "Row 10 of PM8x50 MIB memory. All 8 ports have the same MIB format", 1802 /* MIB_MEMORY_ROW11 */ "Row 11 of PM8x50 MIB memory. All 8 ports have the same MIB format", 1803 /* MIB_MEMORY_ROW12 */ "Row 12 of PM8x50 MIB memory. All 8 ports have the same MIB format", 1804 /* MIB_MEMORY_ROW13 */ "Row 13 of PM8x50 MIB memory. All 8 ports have the same MIB format", 1805 /* MIB_MEMORY_ROW14 */ "Row 14 of PM8x50 MIB memory. All 8 ports have the same MIB format", 1806 /* MIB_MEMORY_ROW15 */ "Row 15 of PM8x50 MIB memory. All 8 ports have the same MIB format", 1807 /* MIM_TUNNEL_TERM_ACTION_SET */ "PDD Output Bus generic format", 1808 /* MIRROR_DOP */ "MIRROR_DOP DOP description.", 1809 /* MMU_CBPPACKETHEADER */ "Position and description of bits in CBP Packet Header", 1810 /* MMU_CCPHEADER */ "Position and description of bits in CCP Entry", 1811 /* MMU_CCP_TO_CFAP_CELL_INFO */ "Info bus for the cell pointers returns sent by CCP to CFAP.", 1812 /* MMU_CELLHDR_2_CRRU */ "Position and description of bits in bus between crru and cbp rd ctrl", 1813 /* MMU_CFAP_MSBUS */ "Position and description of bits in the 96-bit MS-Bus", 1814 /* MMU_CFAP_TO_CRB_ENQ_INFO */ "Cell pointer for the enqueue cell. There are 4 instances of this interface, one for each enqueue pipe", 1815 /* MMU_CFAP_TO_MB_CELL_INFO */ "Cell pointer for the enqueue cell. There are 4 instances of this interface, one for each enqueue pipe", 1816 /* MMU_CFAP_TO_THDI_REL_INFO */ "Cell release information needed by the THDI to return resource allocation databasse.\nUp to 12 cells per transfer, This format is instantiated 12 times", 1817 /* MMU_CFAP_TO_THDO_DEQCHK_INFO */ "CQE dequeue interface from CFAP to THDO, 6 instances of this interface", 1818 /* MMU_CLSCH_TO_PKSCH_PICK_INFO */ "Port pick and related cell information from the prefetch", 1819 /* MMU_CLSCH_TO_SHP_DEQ_INFO */ "Port pick and related cell information.", 1820 /* MMU_CMICXQHEADER */ "Position and description of bits in XQ write Header", 1821 /* MMU_COEFC_INDEX */ "Position and description of bits in the ENQ_TO_INTFI COE-FC index bus", 1822 /* MMU_CPATH_TO_DPATH */ "Position and description of bits in CBP Packet Header", 1823 /* MMU_CPUCRRUHEADER */ "Position and description of bits in CPU CRRU Entry", 1824 /* MMU_CPUHGCRRUHEADER */ "Position and description of bits in CPU HG CRRUDEST_PORT Entry", 1825 /* MMU_CPUHGPPPHEADER */ "Position and description of bits in CPU HG PPP Entry", 1826 /* MMU_CPUHGXQHEADER */ "Position and description of bits in CPU HG XQ Entry", 1827 /* MMU_CPUPPPHEADER */ "Position and description of bits in CPU PPP Entry", 1828 /* MMU_CPUXQHEADER */ "Position and description of bits in CPU XQ Entry", 1829 /* MMU_CRB_TO_CFAP_ENQ_INFO */ "Interface from CRB to CFAP for enqueue cells received from IP that need cell pointer.\nCRB has 4 instances of this interface. One for every input pipe", 1830 /* MMU_CRB_TO_EBCTM_ENQ_CT_REQ_INFO */ "CRB to EBCTM Enqueue cell info for CT Request", 1831 /* MMU_CRB_TO_EBCTM_RQE_CT_REQ_INFO */ "CRB to EBCTM dummy CT request for cells received from RQE", 1832 /* MMU_CRB_TO_RL_ENQ_CT_CELL_INFO */ "CRB to RL CT Cell info used by RL to dequeue a CT cell from MB", 1833 /* MMU_CRB_TO_RL_MULTI_COPY_INFO */ "CRB to RL multi copy info used by RL to send to the CCP.", 1834 /* MMU_CRB_TO_RQE_PKTHDR_INFO */ "Multicast packet header information from IP via CRB to the RQE.\nRQE uses this information to lookup the ICC value and returns this back to the CRB so that it can be stored\nwith SAF packets out to the SCB. RQE stores this information in the RQE info table. The RQE returns the table index to the CRB.\nIf THDR drops the packet, the RQE will return the index to the RQE free pool.\nThis information is valid only on SOP and EOP cells of a packet.\nCRB has 4 instances of this interface. One for every inp ...", 1835 /* MMU_CRB_TO_SCB_IP_INFO */ "CRB to SCB unicast interface", 1836 /* MMU_CRB_TO_SCB_RQE_CELL_INFO */ "Interface from CRB to SCB capturing the cell infromation from RQE after replication.\nThere are 4 instances of this interface as RQE can transfer maximum of 4 cells per cycle.", 1837 /* MMU_CRB_TO_SCB_RQE_PKT_INFO */ "Interface from CRB to SCB capturing the packet infromation from RQE after replication.\nThere is 1 instance of this interface.", 1838 /* MMU_CRB_TO_THDI_ENQ_INFO */ "CRB to THDI enqueue cell information received from IP", 1839 /* MMU_CRB_TO_THDR_ENQ_CELL_INFO */ "Interface from CRB to THDR used by THDR to make a drop/accept decision. The interface is valid only if the cell is a Multicast/Mirror/Copy-to-CPU.\nCRB has 4 instances of this interface. One for every input pipe", 1840 /* MMU_CRRUHEADER */ "Position and description of bits in CRRU Entry", 1841 /* MMU_CTR_TO_RQE_DATA */ "MMU_CTR_TO_RQE_DATA", 1842 /* MMU_DPATH_TO_CPATH */ "Position and description of bits in CBP Packet Header", 1843 /* MMU_EBCFP_TO_EBCR_CELL_INFO */ "Supplies cell pointer and control information with valid signal to EBCR", 1844 /* MMU_EBCFP_TO_EBMB_CELL_INFO */ "Supplies cell pointer, cell size encoding and CCBE with valid signal to EBMB", 1845 /* MMU_EBCFP_TO_EBMB_DEQ_CELL_INFO */ "Supplies deque cell pointer, device/MMU port number, encoded cell size, port in/out-of-profile status with valid signal to EBMB", 1846 /* MMU_EBCR_TO_EBTOQ_ENQ_CELL_INFO */ "Position and description of the bits in the EBCR to EBTOQ enq interface", 1847 /* MMU_EBCTM_STG1_BUS_FORMAT */ "Position and description of bits in the EBCTM stage 1 to stage 2 bus.", 1848 /* MMU_EBCTM_STG2_BUS_FORMAT */ "Position and description of bits in the EBCTM stage 2 to stage 3 bus.", 1849 /* MMU_EBCTM_STG5_BUS_FORMAT */ "Position and description of bits in the EBCTM stage 5 to stage 6 bus.", 1850 /* MMU_EBCTM_STG6_BUS_FORMAT */ "Position and description of bits in the EBCTM stage 6 to stage 7 bus.", 1851 /* MMU_EBCTM_TO_CRB_ENQ_CT_DECISION_INFO */ "Position and description of bits in the EBCTM to CRB CT decision for unicast CT requests. This is a per IP interface. EBCTM has 8 sets of the given interface.", 1852 /* MMU_EBCTM_TO_CRB_RQE_CT_DECISION_INFO */ "Position and description of bits in the EBCTM to CRB cell tag information for multicast CT requests. This is a per RQE interface. EBCTM has 2 sets of the given interface.", 1853 /* MMU_EBCTM_TO_EBPCC_CT_FSM_STATE */ "Position and description of bits in the EBCTM to EBPCC CT FSM state. This is a per front panel port. EBCTM has 18 sets of the given interface.", 1854 /* MMU_EBCTM_TO_EBQS_CT_FSM_STATE_INFO */ "EBCTM to EBQS CT FSM state information. This is a per port interface. EBCTM has 18 sets of the given interface.", 1855 /* MMU_EBCTM_TO_PTSCH_PRETCT_INFO */ "Position and description of bits in the EBCTM to PTSCH PreTCT info bus. EBCTM has 1 set of the given interface.", 1856 /* MMU_EBCTM_TO_RL_ENQ_CT_DECISION_INFO */ "Position and description of bits in the EBCTM to RL CT decision for unicast CT requests. This is a per IP interface. EBCTM has 8 sets of the given interface.", 1857 /* MMU_EBMB_TO_EBPTS_DEQ_INFO */ "Dequeue info for EBPTS shaper", 1858 /* MMU_EBMB_TO_EP_CELL_DATA */ "EBMB to EP cell data format", 1859 /* MMU_EBPCC_TO_EBCTM_TCT_INFO */ "EBPCC to EBCTM information bus", 1860 /* MMU_EBPCC_TO_PTSCH_DEQ_INC_INFO */ "Credit increment information for EB dequeue", 1861 /* MMU_EBPCC_TO_PTSCH_PFC_CREDIT_INFO */ "Position and description of the credit increment decrement related information for a port that gets PFC XOFF/XON. 1 set of this interface.", 1862 /* MMU_EBPCC_TO_PTSCH_PFC_ENQ_INC_INFO */ "Credit increment information for cases where the PTSCH continues to send the cells for queues that is in XOFF", 1863 /* MMU_EBPCC_TO_QSCH_QUEUE_XOFF_INFO */ "XOFF information per Scheduler Queue. The port cycles through in a TDM manner.", 1864 /* MMU_EBPR_TO_EBCFP_CELL_INFO */ "Position and description of the bits in the EBPR to EBCFP cell info interface", 1865 /* MMU_EBPTS_TO_EBQS_PICK_INFO */ "Port pick and related cell information from the prefetch", 1866 /* MMU_EBPTS_TO_EBQS_PORT_CREDITS_AVLBL */ "Port pick and related cell information from the prefetch", 1867 /* MMU_EBP_TO_EBMB_CELL_DATA */ "EBP to EBMB cell data format", 1868 /* MMU_EBP_TO_EBMB_SLICE_DATA */ "EBP to EBMB cell data interface format, per slice", 1869 /* MMU_EBQS_ADV_PICK_INFO */ "EBQS advance pick info.", 1870 /* MMU_EBQS_ENQ_TO_PORT_INFO */ "EBQS enqueue module to per port module info bus.", 1871 /* MMU_EBQS_TO_EBPCC_PFC_XOFF_STATE_PORT */ "Per EBQueue PFC XOFF state information from EBQS to EBPCC.", 1872 /* MMU_EBQS_TO_EBPTS_PREFETCH_INFO */ "Per port cell prefetch info from EBQS to EBPortSCH.", 1873 /* MMU_EBQS_TO_EBTOQ_DEQ_CELL_INFO */ "Dequeue cell info from EBQS to EBTOQ.", 1874 /* MMU_EBTOQ_TO_EBCFP_DEQ_CELL_INFO */ "EBTOQ to EBCFP interface for dequeue", 1875 /* MMU_EBTOQ_TO_EBCTM_DEQ_CELL_INFO */ "EBTOQ to EBCTM cell info for enqueue and dequeue in EBTOQ. There are 3 instances of this interface - 2 for Enqueue, 1 for dequeue.", 1876 /* MMU_EBTOQ_TO_EBCTM_ENQ_CELL_INFO */ "EBTOQ to EBCTM cell info for enqueue and dequeue in EBTOQ. There are 3 instances of this interface - 2 for Enqueue, 1 for dequeue.", 1877 /* MMU_EBTOQ_TO_EBPCC_DEQ_CELL_INFO */ "Enqueue, dequeue indication from EBTOQ to EBPCC. There are 3 instances of this interface - 2 for enqueue, 1 for dequeue", 1878 /* MMU_EBTOQ_TO_EBPCC_ENQ_CELL_INFO */ "Enqueue, dequeue indication from EBTOQ to EBPCC. There are 3 instances of this interface - 2 for enqueue, 1 for dequeue", 1879 /* MMU_EBTOQ_TO_EBQS_DEQ_CELL_INFO */ "Indicates if 10th cell in the virtual EBQueue is an EOP.", 1880 /* MMU_EBTOQ_TO_EBQS_ENQ_CELL_INFO */ "Enqueue cell info from EBTOQ to EBQS. There are 2 such interfaces to support 2 Enqueues per cycle", 1881 /* MMU_EB_MIN_DEQUEUE_DELAY */ "The minimum dequeue delay in EB. Used to determine the number of additional dequeue staging\n flops to be added in EBCFP to prevent dequeue request to EBMB before cell enqueue.", 1882 /* MMU_ENQ_RQE_DATA */ "Position and description of bits in the DQS to TOQ INFO", 1883 /* MMU_ENQ_SOP_STORE_0 */ "Internal packet pointer", 1884 /* MMU_ENQ_SOP_STORE_1 */ "Internal packet pointer", 1885 /* MMU_ENQ_SOP_STORE_2 */ "Internal packet pointer", 1886 /* MMU_ENQ_TO_RQE_DATA */ "MMU_ENQ_TO_RQE_DATA", 1887 /* MMU_ES_TO_RQE_DATA */ "MMU_ES_TO_RQE_DATA", 1888 /* MMU_EXT_MC_QUEUE_LIST */ "MMU_EXT_MC_QUEUE_LIST0,1,4 memory format", 1889 /* MMU_HGCRRUHEADER_EXT */ "Position and description of bits in HG CRRUDEST_PORT Entry", 1890 /* MMU_HGPPPHEADER */ "Position and description of bits in HG PPP Entry", 1891 /* MMU_HGPPPHEADER_EXT */ "Position and description of bits in HG PPP Entry", 1892 /* MMU_HGXQHEADER */ "Position and description of bits in HG XQ Entry", 1893 /* MMU_HGXQHEADER_EXT */ "Position and description of bits in HG XQ Entry", 1894 /* MMU_IDMHEADER */ "Position and description of bits in IDM Header", 1895 /* MMU_INTFI_TO_EBCFP_QUEUES_PURGE_INFO */ "Per-port - 12 MMU Queues' purge bitmap + 9 EB Groups'/Queues' purge bitmap", 1896 /* MMU_INTFI_TO_EBCTM_PORT_FC_INFO */ "Per-port XOFF status", 1897 /* MMU_INTFI_TO_EBPCC_QUEUES_FC_INFO */ "Per-port - 12 MMU Queues' XOFF status bitmap + 9 EB Groups'/Queues' XOFF status bitmap", 1898 /* MMU_INTFI_TO_EBQS_EB_QUEUES_FC_INFO */ "Per-port 9 EB PFC Queues'/Groups' XOFF status bitmap.", 1899 /* MMU_IPMCGROUPTABLE */ "Position and description of bits in IPMC Group Table", 1900 /* MMU_IPMCHEADER */ "Position and description of bits in IPMC Header Entry", 1901 /* MMU_IPMCVLANTABLE */ "Position and description of bits in IPMC VLAN Table", 1902 /* MMU_IPMC_GRP_TBL_ALL */ "Aggregate IPMC group table", 1903 /* MMU_ITE_CTRL_0 */ "ITE_WORK_QUEUE Memory contents", 1904 /* MMU_ITE_WORK_QUEUE */ "ITE_WORK_QUEUE Memory contents", 1905 /* MMU_MB_BANK_ADDR */ "Position and description of bits", 1906 /* MMU_MB_REMOTE_IF */ "Internal MB interface (remote_if)", 1907 /* MMU_MB_TO_EBP_EB_INFO */ "EB number sent from MB to EBP ahead of the data", 1908 /* MMU_MB_TO_EBP_SLICE_DATA */ "Payload slice data sent from MB to EBP", 1909 /* MMU_MEM_ADDR */ "Position and description of bits", 1910 /* MMU_MTRO_TO_QSCH_EP_SHAPE_BUS_INFO */ "Translated EP shape bus info", 1911 /* MMU_MTRO_TO_QSCH_L0_PROFILING_UPDATE_INFO */ "MIN and MAX profiling status change information for COS, from MTRO to QSCH. Three parallel buses to convey up to three profiling changes per cycle due to the three update events: TOQ dequeuing response, EP-Shape-Bus return, and bucket refreshing.", 1912 /* MMU_MTRO_TO_QSCH_L1_PROFILING_UPDATE_INFO */ "MIN and MAX profiling status change information for QUEUE, from MTRO to QSCH. Three parallel buses to convey up to three profiling changes per cycle due to the three update events: TOQ dequeuing response, EP-Shape-Bus return, and bucket refreshing.", 1913 /* MMU_MTRO_TO_QSCH_PORT_PROFILING_UPDATE_INFO */ "Port MAX profiling status changes information from MTRO to QSCH. Three parallel buses to convey up to three profiling changes per cycle due to the three update events: TOQ dequeuing response, EP-Shape-Bus return, and bucket refreshing.", 1914 /* MMU_NCPHEADER */ "Position and description of bits in NCP Entry", 1915 /* MMU_OQS_TO_TOQ_CELL_INFO */ "Cell information from OQS to TOQ. There are 6 instances of this interface.", 1916 /* MMU_PKTHEADER1_ALL */ "Aggregate Packet Header 1 table", 1917 /* MMU_PPPHEADER */ "Position and description of bits in PPP to CDU bus", 1918 /* MMU_PPSCH_TO_PTSCH_PICK_INFO */ "Pipe scheduler pick feedback to port scheduler", 1919 /* MMU_PPSCH_TO_QSCH_PICK_INFO */ "Pipe scheduler pick feedback to queue scheduler", 1920 /* MMU_PPSCH_TO_QSCH_Q_MAP_INFO */ "Interface for updating Scheduler Q num to MMU Q num mapping table", 1921 /* MMU_PPSCH_TO_TOQ_DEQ_INFO */ "Dequeue pick information from pipe scheduler to TOQ", 1922 /* MMU_PTSCH_TO_PPSCH_PICK_INFO */ "Port pick for the pipe plus VOQ picks and info, including the primary and secondary picks for that Port as indicated by the Queue Scheduler", 1923 /* MMU_QSCH_TO_PTSCH_PORT_DEQ_STATE */ "indcate to PTSCH a port dequeuing states which include: one is that the port is ready to be dequeued, and one is that the port has at least two more dequeues available at this time", 1924 /* MMU_QSCH_TO_PTSCH_QUEUE_PICK_INFO */ "per port VOQ picks and info, including the primary and secondary picks", 1925 /* MMU_QSCH_TO_THDO_VOQ_FAIRNESS_INFO */ "QSCH will periodically request the average arrival rate count of each VOQ from THDO by sending to it the MMU queue number. The MMU queue number is sent one per cycle and is in the form of {pipe number, port number, and MMU queue number local to the port}", 1926 /* MMU_QSTRUCT_EOP_BLOCK */ "EOP_BLOCK DATABASE", 1927 /* MMU_QSTRUCT_QBLOCK_NEXT */ "QBLOCK_NEXT DATABASE", 1928 /* MMU_QSTRUCT_QENTRY */ "QENTRY DATABASE", 1929 /* MMU_REG_ADDR */ "Position and description of bits", 1930 /* MMU_RL_TO_CCP_CELL_INFO */ "normal read requests notifications from RL to CCP", 1931 /* MMU_RL_TO_CCP_RQE_INFO */ "RQE copy count updates sent through RL to CCP", 1932 /* MMU_RL_TO_CFAP_CELL_INFO */ "RL to CFAP", 1933 /* MMU_RL_TO_EBCFP_CTRL_DELAY */ "RL to EBCFP control delay.", 1934 /* MMU_RL_TO_EBMB_DATA_DELAY */ "RL to EBMB data path delay.", 1935 /* MMU_RL_TO_EBPR_CCBE_INFO */ "CCBE + other params passed to EBP", 1936 /* MMU_RL_TO_MB_CELL_INFO */ "CCBE + other params passed to EBP", 1937 /* MMU_RL_TO_PPSCH_CREDIT_RTN_INFO */ "Credit return from RL to Pipe Sch (2 lines per EB)", 1938 /* MMU_RL_TO_RQE_CREDIT_RTN_INFO */ "Credit return from RL to RQE", 1939 /* MMU_RQE_CELLQ_FIELD */ "RQE Cell Queue Memory Fields for each of the 8 cells", 1940 /* MMU_RQE_INFOTBL_FP_INIT_STATE */ "RQE info table free pool init state encodings", 1941 /* MMU_RQE_META_DATA_IN */ "META_DATA_IN Format", 1942 /* MMU_RQE_META_DATA_OUT */ "META_DATA_OUT Format", 1943 /* MMU_RQE_NEW_BM */ "MMU_RQE_BMP_FMT", 1944 /* MMU_RQE_PIPE_OUT_DATA */ "Position and description of bits in the DQS to PIPE_OUT INFO", 1945 /* MMU_RQE_PKTQ_FIELD */ "RQE Packet Queue Memory Fields for each of the 8 cells", 1946 /* MMU_RQE_REPENG_DATA */ "Data-Bus format for input to metadata_gen", 1947 /* MMU_RQE_TOQ_DATA */ "Position and description of bits in the DQS to TOQ INFO", 1948 /* MMU_RQE_TO_CRB_CELL_INFO */ "Cell information on replicated packet out to CRB from RQE. There are 4 instances of this interface.\nUp to 4 cells per transfer and max 1 packet per transfer from the RQE to the CRB.\nRQE can be flow controlled by a cell credit mechanism. For every cell transfer, the RQE decrements a credit count and\nget return credits back from the SCB. Credit count is configurable upon initialization in the RQE\nSent for every cell of packet, at SOP sent at same time as MMU_RQE_TO_CRB_PKT_INFO", 1949 /* MMU_RQE_TO_CRB_ICC_INFO */ "When CRB sends MMU_CRB_TO_RQE_PKTHDR_INFO, RQE needs to return an index to where this information\ngot stored in the RQE Info table, CRB sends this index to the downstream pipeline to THDR and SCB\nRQE Initial Copy Count value to be sent with each packet on the CRB to the SCB\n(CT path does not need this). This interface is instantiated 4 times for each input pipe\nThe CRB always sends information to the RQE for SOP and EOP of the packet. RQE sees SOP and source port\ninformation from the CRB for thi ...", 1950 /* MMU_RQE_TO_CRB_PKT_INFO */ "Packet information on replicated packet out to CRB from RQE. There is 1 instances of this interface.\nUp to 4 cells per transfer and max 1 packet per transfer from the RQE to the CRB.\nRQE can be flow controlled by a cell credit mechanism. For every cell transfer, the RQE decrements a credit count and\nget return credits back from the SCB. Credit count is configurable upon initialization in the RQE\nOnly sent once per packet, SOP if multiples", 1951 /* MMU_RQE_TO_CTR_DATA */ "MMU_RQE_TO_CTR_DATA", 1952 /* MMU_RQE_TO_ENQ_DATA */ "MMU_RQE_TO_ENQ_DATA", 1953 /* MMU_RQE_TO_EPRG_DATA */ "MMU_RQE_TO_EPRG_DATA", 1954 /* MMU_RQE_TO_PORTCNT_DATA */ "MMU_RQE_TO_PORTCNT_DATA", 1955 /* MMU_RQE_TO_RL_COPYCNT_INFO */ "Info bus for the copy count information transfers from RQE to RL for each cell.\nThere are 4 instances of this interface.\nUp to 4 cells per transfer and max 1 packet per transfer from the RQE to the RL.\nRQE can be flow controlled by a cell credit mechanism. For every cell transfer, the RQE decrements a cell credit count and\nget return cell credits back from the RL. Credit count is configurable upon initialization", 1956 /* MMU_RQE_TO_THDO_ENQCHK_PKT_INFO */ "Packet copy information for output queue threshold check from RQE to THDO", 1957 /* MMU_RQE_TO_THDR_DATA */ "MMU_RQE_TO_THDR_DATA", 1958 /* MMU_RQE_TO_THDR_QUE_RELEASE */ "RQE queue release information from RQE to THDR, only done once per packet and not every cell", 1959 /* MMU_RQE_WF_DATA */ "Position and description of bits in the DQS to TOQ INFO", 1960 /* MMU_SBUS_SB_INFO */ "Position and description of bits in the sbus input to a module.", 1961 /* MMU_SCB_SOPSS_DATA */ "SOP Supplemental Storage Data Format", 1962 /* MMU_SCB_TO_CRB_CREDIT_RET */ "Cell credit return from SCB to CRB.\nUp to 6 cell credit returns from the SCB to the CRB per clock.", 1963 /* MMU_SCB_TO_OQS_CELL_INFO */ "Cell information from SCB to OQS. There are 6 instances of this interface.", 1964 /* MMU_SCB_TO_RQE_CELL_CREDIT_RTN */ "Cell credit return from SCB to RQE.\nUp to 4 cells per transfer from RQE and max 1 packet per transfer from the RQE to the SCB.\nRQE can be flow controlled by a cell credit mechanism. For every cell transfer, the RQE decrements a credit count and\nget return credits back from the SCB. Credit count is configurable upon initialization in the RQE\nAll values are valid for every cell even if it is a packet property", 1965 /* MMU_SCB_TO_RQE_CELL_INFO */ "Cell information from TOQ/SCB to RQE. There are 6 instances of this interface on TOQ/SCB to RQE.\nWith these 2 interfaces, RQE can receive 12 cells per cycle and up to 12 packets per cycle for SEOP packets.\nRQE can not flow control these interfaces", 1966 /* MMU_SER_STATUS_BUS */ "Position and description of bits in the MMU memory SER status bus", 1967 /* MMU_SHAPE_PASSTHRU_INFO */ "Fields that MMU needs on SHAPE bus that are passthru in EP", 1968 /* MMU_THDI_PACKET_TYPE */ "Packet Type Encodings from THDI.", 1969 /* MMU_THDI_SPAP */ "THDI SPAP Encodings.", 1970 /* MMU_THDI_TO_CRB_ENQ_INFO */ "Position and description of bits sent from THDI to CRB.", 1971 /* MMU_THDI_TO_INTFO_OOBFC_INFO */ "Position and description of bits sent from THDI to INTFO for OOBFC.", 1972 /* MMU_THDI_TO_INTFO_PFC_INFO */ "Position and description of bits sent from THDI to INTFO for PFC.", 1973 /* MMU_THDI_TO_THDO_LOSSLESS_SP_INFO */ "Position and description of bits sent from THDI to THDO.", 1974 /* MMU_THDI_TYPE */ "THDI Type Encodings.", 1975 /* MMU_THDO_TO_EBCTM_INFO */ "Position and description of bits in THDO to EBCTM interface", 1976 /* MMU_THDO_TO_INTFO_FC_INFO */ "Position and description of bits in THDO to INTFO_FC interface", 1977 /* MMU_THDO_TO_IP_DLB_INFO */ "Position and description of bits in THDO to IP_DLB interface.", 1978 /* MMU_THDO_TO_QSCH_VOQ_FAIRNESS_INFO */ "THDO responds to a VOQ fairness request by sending back to QSCH the average arrival rate count, accompanying with the {pipe number, port number, and MMU queue number local to the port} of the queue for reference", 1979 /* MMU_THDO_TO_RQE_ENQCHK_PKT_INFO */ "Position and description of bits in THDO to RQE ENQCHK_PKT interface", 1980 /* MMU_THDO_TO_TOQ_ENQCHK_INFO */ "Position and description of bits in THDO to TOQ ENQCHK interface", 1981 /* MMU_THDO_TO_WRED_ENQ_ACCEPT_INFO */ "Position and description of bits in THDO to WRED_ENQ_ACCEPT interface", 1982 /* MMU_THDO_TO_WRED_PORTSP_LEN_STATUS_INFO */ "Position and description of bits in THDO_TO_WRED_PORTSP_LEN_STATUS_INFO interface", 1983 /* MMU_THDO_TO_WRED_QLEN_STATUS_INFO */ "Position and description of bits in THDO_TO_WRED_QLEN_STATUS_INFO interface", 1984 /* MMU_THDO_TO_WRED_Q_MIN_STATE_INFO */ "Position and description of bits in MMU_THDO_TO_WRED_Q_MIN_STATE_INFO interface", 1985 /* MMU_THDO_TO_WRED_SP_LEN_STATUS_INFO */ "Position and description of bits in THDO_TO_WRED_PORTSP_LEN_STATUS_INFO interface", 1986 /* MMU_THDR_TO_CRB_ACCEPT_INFO */ "Multicast packet thresholding checking result from THDR to CRB, for every EOP of SAF packet and every CT cell.\nTHDR has 4 instances of this interface, one for every input pipe.", 1987 /* MMU_THDR_TO_INTFO_DROP_STATUS */ "RQE Replication Fifo service pool congestion status, this is used for OOBFC message generation", 1988 /* MMU_THDR_TO_RQE_ACCEPT_INFO */ "Multicast packet thresholding checking result from THDR to RQE, for every EOP of SAF packet and every SOP of CT packet.\nTHDR also needs to stage RQE INFO Index received from CRB and send it to RQE with an accept decision.\nTHDR has 4 instances of this interface, one for every input pipe.", 1989 /* MMU_THDR_TO_THDI_ACCEPT_INFO */ "Multicast packet thresholding checking result from THDR to THDI, for every EOP of SAF packet and every CT cell.\nTHDR has 4 instances of this interface, one for every input pipe.", 1990 /* MMU_TOQ_CQE */ "CQE info Details", 1991 /* MMU_TOQ_EOPE_TBL */ "TOQ EOPE Database, overlayed on MEM0 : Holds EOPE state for external buffer usage tracking. CPU read only", 1992 /* MMU_TOQ_TO_CFAP_ENQRETURN_INFO */ "Bus information TOQ2CFAP", 1993 /* MMU_TOQ_TO_MTRO_DEQ_RESP_INFO */ "TOQ dequeue information to QSCH and MTRO, two dequeues per cycles", 1994 /* MMU_TOQ_TO_QSCH_DEQ_RESP_INFO */ "TOQ dequeue information to QSCH and MTRO, two dequeues per cycles", 1995 /* MMU_TOQ_TO_QSCH_UPDATE_INFO */ "TOQ to QSCH enqueue or dequeue update information for a queue", 1996 /* MMU_TOQ_TO_RL_INFO */ "", 1997 /* MMU_TOQ_TO_RQE_CELL_INFO */ "Cell information from TOQ/SCB to RQE. There are 6 instances of this interface on TOQ/SCB to RQE.\nWith these 2 interfaces, RQE can receive 12 cells per cycle and up to 12 packets per cycle for SEOP packets.\nRQE can not flow control these interfaces", 1998 /* MMU_TOQ_TO_THDO_DEQ_INFO */ "", 1999 /* MMU_TOQ_TO_THDO_ENQCHK_INFO */ "", 2000 /* MMU_TOQ_TO_WRED_DEQ_INFO */ "", 2001 /* MMU_TO_IP_HOL_COS */ "MMU-INTF to IP HOL status COS", 2002 /* MMU_TO_IP_HOL_STATUS */ "MMU-INTF to IP HOL status report", 2003 /* MMU_TO_IP_HOL_STATUS_EXT8 */ "MMU-INTF to IP HOL extended status report for COS_8 to COS_15", 2004 /* MMU_TO_IP_HOL_STATUS_EXT16 */ "MMU-INTF to IP HOL extended status report for COS_16 to COS_23", 2005 /* MMU_TO_IP_IBP_PRI */ "MMU-INTF to IP IBP status priority", 2006 /* MMU_TO_IP_IBP_STATUS */ "MMU-INTF to IP IBP status report", 2007 /* MMU_TO_IP_OAM_LM_BUS */ "Description of fields on the MMU_TO_IP_OAM_LM_BUS Bus from MMU to IP.", 2008 /* MMU_TO_XGP_BKP */ "MMU-INTF to XGP back-pressure (BKP) status", 2009 /* MMU_TO_XGP_E2E_BUS */ "MMU-INTF to XGP E2E data bus", 2010 /* MMU_TO_XP_E2E_BUS */ "MMU-INTF to XP E2E data bus", 2011 /* MMU_TO_XQP_E2E_BUS */ "MMU-INTF to XQP E2E data bus", 2012 /* MMU_WRED_TO_THDO_ENQ_ACCEPT_INFO */ "Position and description of bits in THDO to INTFO_FC interface", 2013 /* MMU_WRED_TO_TOQ_DEQ_FEEDBACK */ "Position and description of bits in WRED to TOQ DEQ FEEDBACK interface", 2014 /* MMU_XQHEADER */ "Position and description of bits in XQ Entry", 2015 /* MMU_XQ_HDR_ONLY_CPU */ "Position and description of bits in XQ write Header", 2016 /* MMU_XQ_HDR_ONLY_GPORT */ "Position and description of bits in XQ write Header", 2017 /* MMU_XQ_HDR_ONLY_XPORT */ "Position and description of bits in XQ write Header", 2018 /* MODULE_HEADER */ "Bit Definitions of the Internal Module Header", 2019 /* MODULE_HEADER_SHIFT */ "HG+ format shifted by 32", 2020 /* MPB */ "Position and description of bits in MMU Passthru Bus (carried from Ip to EP thru MMU).", 2021 /* MPB_BASE_FORWARD_FORMAT */ "Base Forwarding Format in MMU Passthru Bus (carried from Ip to EP thru MMU).", 2022 /* MPB_CLASSID_FORMAT */ "CLASSID FORMAT in MMU Passthru Bus (carried from Ip to EP thru MMU).", 2023 /* MPB_COPY_TO_CPU_FORMAT */ "COPY_TO_CPU FORMAT in MMU Passthru Bus (carried from Ip to EP thru MMU).", 2024 /* MPB_ENTROPY_FORMAT */ "ENTROPY FORMAT in MMU Passthru Bus (carried from Ip to EP thru MMU).", 2025 /* MPB_FORWARD_EXT_FORMAT */ "Forwarding Extension Format in MMU Passthru Bus (carried from Ip to EP thru MMU).", 2026 /* MPB_FP_HGPRXY_DATA_DECODER_OUT_BUS */ "Data Decoder Output Bus generic format", 2027 /* MPB_HG2_EXT_FORMAT */ "Reserved, HG2_EXT FORMAT in MMU Passthru Bus (carried from Ip to EP thru MMU).", 2028 /* MPB_HIGIG_DATA_DECODER_OUT_BUS */ "Data Decoder Output Bus generic format", 2029 /* MPB_ING_EDIT_EXTRACT_CTRL_ID_FORMAT */ "INGRESS_EDIT_CONTROL_ID and EXTRACTION_CTRL_ID FORMAT in MMU Passthru Bus (carried from Ip to EP thru MMU).", 2030 /* MPB_L2_ETAG_FORMAT */ "Flexible Action Bitmap in MMU Passthru Bus (carried from Ip to EP thru MMU).", 2031 /* MPB_L2_EXT_FORMAT */ "Flexible Action Bitmap in MMU Passthru Bus (carried from Ip to EP thru MMU).", 2032 /* MPB_L2_ITAG_FORMAT */ "Flexible Action Bitmap in MMU Passthru Bus (carried from Ip to EP thru MMU).", 2033 /* MPB_L2_SVP_FORMAT */ "SVP FORMAT in MMU Passthru Bus (carried from Ip to EP thru MMU).", 2034 /* MPB_L2_VFI_FORMAT */ "VFI FORMAT in MMU Passthru Bus (carried from Ip to EP thru MMU).", 2035 /* MPB_L3_IIF_FORMAT */ "L3_IIF FORMAT in MMU Passthru Bus (carried from Ip to EP thru MMU).", 2036 /* MPB_L3_VRF_FORMAT */ "VRF FORMAT in MMU Passthru Bus (carried from Ip to EP thru MMU).", 2037 /* MPB_MIRROR_FORMAT */ "MIRROR_FORMAT in MMU Passthru Bus (carried from Ip to EP thru MMU).", 2038 /* MPB_NAT_FORMAT */ "NAT FORMAT in MMU Passthru Bus (carried from Ip to EP thru MMU).", 2039 /* MPB_NEXT_HOP_DATA_FORMAT */ "NEXT_HOP_DATA format in MMU Passthru Bus (carried from Ip to EP thru MMU).", 2040 /* MPB_OPAQUE_OBJECT_FORMAT */ "OPAQUE_OBJECT FORMAT for 1 object in MMU Passthru Bus (carried from Ip to EP thru MMU).", 2041 /* MPB_QOS_FORMAT */ "QOS FORMAT in MMU Passthru Bus (carried from Ip to EP thru MMU).", 2042 /* MPB_QUEUE_TAG_FORMAT */ "QUEUE_TAG FORMAT in MMU Passthru Bus (carried from Ip to EP thru MMU).", 2043 /* MPB_TIMESTAMP_FORMAT */ "TIMESTAMP FORMAT in MMU Passthru Bus (carried from Ip to EP thru MMU).", 2044 /* MPLS_ACTION */ "PDD Output Bus generic format", 2045 /* MPLS_ACTION_SET */ "PDD Output Bus generic format", 2046 /* MPLS_CONTROL_SIGNALS_DOP */ "MPLS_CONTROL_SIGNALS_DOP DOP description.", 2047 /* MPLS_CW_ACTION_SET */ "PDD Output Bus generic format", 2048 /* MPLS_DROP */ "Bit Definitions of the MPLS drop vector", 2049 /* MPLS_ENTRY_1_DATA */ "Format for MPLS_ENTRY_1 DATA.", 2050 /* MPLS_ENTRY_2_DATA */ "Format for MPLS_ENTRY_2 DATA.", 2051 /* MPLS_ENTRY_ACTION_SET */ "PDD Output Bus generic format", 2052 /* MPLS_ENTRY_COV_DEFS */ "defines for MPLS_ENTRY coverage analysis. Port A is packet read access only. Port B is used for both packet read access and sbus read/write", 2053 /* MPLS_ENTRY_KEY */ "Format for MPLS_ENTRY_1, MPLS_ENTRY_2 KEY.", 2054 /* MPLS_HDR */ "MPLS header specification", 2055 /* MPLS_PW_TERM_CTR_ACTION_SET */ "PDD Output Bus generic format", 2056 /* MPLS_RESERVED_LABEL */ "Reserved MPLS labels.", 2057 /* MSBUS_32 */ "Position and description of bits in the 32-bit MS-Bus", 2058 /* MSBUS_96 */ "Position and description of bits in the 96-bit MS-Bus", 2059 /* MSBUS_128 */ "Position and description of bits in the 128-bit MS-Bus", 2060 /* MSBUS_160 */ "Position and description of bits in the 160-bit MS-Bus", 2061 /* MSBUS_192 */ "Position and description of bits in the 192-bit MS-Bus", 2062 /* MSBUS_256 */ "Position and description of bits in the 256-bit MS-Bus", 2063 /* MSBUS_288 */ "Position and description of bits in the 256-bit MS-Bus", 2064 /* MSBUS_448 */ "Position and description of bits in the 448-bit MS-Bus", 2065 /* MSBUS_96_REDUCED */ "Position and description of bits in the 36-bit MS-Bus, used by THDI", 2066 /* MS_TO_IARB_IF */ "ISEC to IARB with Overlay Fields Specified", 2067 /* MS_TO_PE_IF */ "MACSEC to PREENQUEUE PIPELINE Control Word Format", 2068 /* MTRO_BUCKET_RF_FIELDS */ "Position and description of bits in the MTRO register file", 2069 /* MTRO_CONFIG_RF_FIELDS */ "Position and description of bits in the MTRO register file", 2070 /* MTRO_CPU_METER_RF_FIELDS */ "Position and description of bits in MTRO Packet Meter register file", 2071 /* MTRO_PD_FIELDS */ "Position and description of bits in MTRO register file", 2072 /* MTRO_PKT_METER_RF_FIELDS */ "Position and description of bits in MTRO Packet Meter register file", 2073 /* MTRO_RF_FIELDS */ "Position and description of bits in the MTRO register file", 2074 /* MTU_CONTROLS_ACTION_SET */ "PDD Output Bus generic format", 2075 /* MXE_TABLE_KEY */ "", 2076 /* MY_STATION_DATA_FORMAT */ "format for MY_STATION data", 2077 /* MY_STATION_TCAM_FORMAT */ "format for MY_STATION TCAM", 2078 /* MY_STATION_TCAM_VAL_DOP */ "MY_STATION_TCAM_VAL_DOP DOP description.", 2079 /* NAT_ACTION_SET */ "PDD Output Bus generic format", 2080 /* NAT_CPU_OPCODE_ENCODING */ "Bit Definitions of the NAT CPU Opcode encoding", 2081 /* NETWORK_HVE_OUTPUT_BUS */ "NETWORK HVE (header verfication engine) output bus format.", 2082 /* NETWORK_HVE_TRIGGERS_FORMAT */ "NETWORK HVE (header verfication engine) trigger format for HVE1/2.", 2083 /* NEXT_PTR_ACTION_SET */ "PDD Output Bus generic format", 2084 /* NIV_CPU_OPCODE_ENCODING */ "Bit Definitions of the NIV CPU Opcode encoding", 2085 /* NLF_CPU_OPCODES */ "Bit Definitions of the CPU Opcodes", 2086 /* NUM_QCN_CNM_RECEIVED_COV_DEFS */ "defines for num_qcn_cnm_received coverage analysis", 2087 /* NVOQFC_DATA */ "Width of one NVOQFC data.", 2088 /* OAM_LM_COUNTERS_COV_DEFS */ "defines for pw_term_seq_num coverage analysis", 2089 /* OAM_LPR_CNTR_ACTION_BUS */ "", 2090 /* OAM_LPR_INTF_CONTROL_INFO */ "", 2091 /* OAM_LPR_INTF_LOOKUP_CNTR_DATA */ "", 2092 /* OAM_LPR_INTF_LOOKUP_DATA */ "Lookup result of MP group table", 2093 /* OAM_LPR_IN_BUS */ "Input bus to module containing all packet attributes.", 2094 /* OAM_LPR_KEY */ "key: .Matching Key = {SVID[11:0], CVID[11:0], GLP[15:0], KEY_TYPE[3:0]}\nHashing Key = {SVID[11:0], CVID[11:0], GLP[15:0], KEY_TYPE[3:0]}\nWhen scope of MPLS Label is per-platform, then a fixed SGLP (ex. 0xFFFF) should be used instead of actual SGLP for lookup Key.", 2095 /* OAM_LPR_KEY_TYPE */ "OAM KEY Type", 2096 /* OAM_LPR_KEY_TYPE_SRC */ "key_types and valid from various source tables", 2097 /* OAM_LPR_KEY_TYPE_SRC_ATR */ "Encoding for KEY_TYPE_SRC_ATR", 2098 /* OAM_LPR_KEY_TYPE_SRC_BUS */ "key_types and valid from various source tables", 2099 /* OAM_LPR_OAM_ACTION */ "bus is used between different process_intf_lookup_results module", 2100 /* OAM_LPR_OAM_DROP_VECTOR */ "OAM_DROP_VECTOR connection for Ingress and Egress(defined as overlay)", 2101 /* OAM_LPR_OAM_PKT_INFO_BUS */ "", 2102 /* OAM_LPR_OUT_BUS */ "All packet related output signals", 2103 /* OAM_LPR_PAR_ERR_INTR */ "bus is used for parity error interrupts generated in OAM LPR block", 2104 /* OAM_LPR_PKT_AND_CTRL_BUS */ "Various packet and control fields", 2105 /* OAM_LPR_PKT_INFO */ "used to pass packet's relevant information to process_intf_lookup_results module", 2106 /* OAM_LPR_S_INTF_PASSIVE_DROP_VECTOR */ "S_INTF_PASSIVE_DROP_VECTOR connection for Ingress and Egress(defined as overlay)", 2107 /* OAM_OPCODE */ "OpCodes indicate the OAM message type, Continuity Check, Loopback, etc. OpCodes 0 - 31 are assigned by IEEE 802.1. Continuity Check, Loopback, and Link Trace use OpCodes in this range, and the OpCode assignments are the same for Y.1711 and 802.1ag", 2108 /* OAM_TLV_DATA */ "TLVs are type, length, and value, encoded parameters that are included in the OAM message body. For each TLV, there is a one octet type field, followed by a two octet length field and an N octet value field. The End TLV has a Type field equal to 0 and the Length and Value fields are not used.", 2109 /* OAM_TLV_TYPE */ "TLVs are type, length, and value, encoded parameters that are included in the OAM message body. For each TLV, there is a one octet type field, followed by a two octet length field and an N octet value field. The End TLV has a Type field equal to 0 and the Length and Value fields are not used.", 2110 /* OLP_RX_HEADER */ "Bit Definitions of OLP_RX_HEADER. This header is constructed when a OAM/BHH/BFD pdu is transmitted TO the OLP.", 2111 /* OLP_TX_HEADER */ "Bit Definitions of OLP_TX_HEADER. This header is always constructed by OLP device when an OAM/BHH/BFD PDU is transmitted to the KT2.", 2112 /* OPAQUE_FIELDS_DOP */ "OPAQUE_FIELDS_DOP DOP description.", 2113 /* OPAQUE_OBJECT_ID_AND_VALUE_FORMAT */ "OPAQUE OBJECT ID and VALUE.", 2114 /* OQS_EXEC_CTRL_INFO */ "", 2115 /* OQS_TRANSFER_CTRL_INFO */ "", 2116 /* OTAG_ACTION_SET */ "PDD Output Bus generic format", 2117 /* OTP_FORMAT */ "OTP Field format", 2118 /* OVLAN_ACTION_SET */ "PDD Output Bus generic format", 2119 /* OVQ_TO_TOQ_INFO */ "Position and description of bits in the OVQ to TOQ to INFO bus", 2120 /* PACKED_SOBMH */ "This is the packed SOBMH usd internally after the overlay bus is not needed anymore.", 2121 /* PBE */ "Position and description of bits in PBI Bus From Ingress pipeline to MMU", 2122 /* PBE_POINTERS */ "PBE Pointers.", 2123 /* PBI */ "Position and description of bits in PBI Bus From Ingress pipeline to MMU", 2124 /* PDD_IN_BUS */ "PDD Input Bus generic format", 2125 /* PDD_OUT_BUS */ "PDD Output Bus generic format", 2126 /* PD_TO_MS_IF */ "Position and description of bits in EP_TO_MS_CONTROL_WORD", 2127 /* PD_TO_PORT_IF */ "PD to PORT Interface", 2128 /* PE_DROP */ "Bit Definitions of the pre-enqueue pipeline drop vector", 2129 /* PFAP_S_RF */ "pfap memory s_rf width", 2130 /* PGW_OBM_DATA */ "OBM Buffer data format", 2131 /* PG_TO_IP_CONTROL_WORD */ "Port Group to IP Control Word", 2132 /* PHB2_COS_MAP_INDEX */ "PHB2_COS_MAP index", 2133 /* PHB_MAPPING_TBL_INDEX */ "PHB_MAPPING_TBL index", 2134 /* PIM_BIDIR_ACTION_SET */ "PDD Output Bus generic format", 2135 /* PIM_SM_ACTION_SET */ "PDD Output Bus generic format", 2136 /* PIPE_DATA_OUT_INFO */ "PIPE_DATA_OUT_INFO", 2137 /* PKTHDR0_MEM0_S_RF */ "pkthdr0 memory s_rf width", 2138 /* PKTHDR0_MEM1_S_RF */ "pkthdr0 memory s_rf width", 2139 /* PKTHDR0_MEM2_S_RF */ "pkthdr0 memory s_rf width", 2140 /* PKTHDR0_MEM3_S_RF */ "pkthdr0 memory s_rf width", 2141 /* PKTHDR0_S_RF */ "pkthdr0 memory s_rf width", 2142 /* PKTHDR1_S_RF */ "pkthdr1 memory s_rf width", 2143 /* PKTHDR2_S_RF */ "pkthdr2 memory s_rf width", 2144 /* PKTHDR_CPU0_S_RF */ "pkthdr_cpu memory s_rf width", 2145 /* PKTHDR_CPU1_S_RF */ "pkthdr_cpu memory s_rf width", 2146 /* PKTHDR_CPU_S_RF */ "pkthdr_cpu memory s_rf width", 2147 /* PKTHDR_EXT_S_RF */ "pkthdr ext memory s_rf width", 2148 /* PKTLENGTH_S_RF */ "packet length memory s_rf width", 2149 /* PKTLINK54_S_RF */ "pktlink 54 memory s_rf width", 2150 /* PKTLINK_S_RF */ "pktlink memory s_rf width", 2151 /* PKT_ECN_TO_INT_CN_MAPPING_INDEX */ "PACKET_ECN_TO_INT_CN_MAPPING index", 2152 /* PKT_FLOW_ID_0_FORMAT */ "Packet Flow ID 0 Format.", 2153 /* PKT_FLOW_ID_1_FORMAT */ "Packet Flow ID 1 Format.", 2154 /* PKT_FLOW_ID_2_FORMAT */ "Packet Flow ID 2 Format.", 2155 /* PKT_FLOW_SELECT_CTRL_ID_1_FORMAT */ "Packet Flow Select Control ID 1 Format.", 2156 /* PKT_FLOW_SELECT_TCAM_0_DOP */ "PKT_FLOW_SELECT_TCAM_0_DOP DOP description.", 2157 /* PKT_FLOW_SELECT_TCAM_1_DOP_DOP */ "PKT_FLOW_SELECT_TCAM_1_DOP_DOP DOP description.", 2158 /* PKT_FLOW_SELECT_TCAM_1_MY_STATION_2_DOP */ "PKT_FLOW_SELECT_TCAM_1_MY_STATION_2_DOP DOP description.", 2159 /* PKT_FORWARDING_TYPE */ "Forwarding Type of Packet", 2160 /* PKT_PROC_DROP_VECTOR */ "Ifp Drop Vector", 2161 /* PM_TO_EDB_TO_PM_PORT_MODE */ "Port Mode from PM to EDB.", 2162 /* PORT_AVG_QUALITY_MEASURE_COV_DEFS */ "defines for port_avg_quality_measure coverage analysis", 2163 /* PORT_DEMAND_STATE */ "Port demand state serial bus from MMU/TDM to EP/EDB", 2164 /* PORT_FC_BEAT_1 */ "E2E Message Control Word Beat 1", 2165 /* PORT_FC_BEAT_2 */ "E2E Message Control Word Beat 2", 2166 /* PORT_FC_MSGTYPE */ "E2E Message Control Word Message Type", 2167 /* PORT_META_DATA_IN_INFO */ "PORT_META_DATA_IN_INFO", 2168 /* PORT_META_DATA_OUT_INFO */ "PORT_META_DATA_IN_INFO", 2169 /* PORT_TO_IP_CONTROL_WORD */ "GPORT/XPORT to IP Control Word Format", 2170 /* PORT_TO_PE_IF */ "PORT to PE Interface", 2171 /* PORT_WRED_CELL_THD_0_FIELDS */ "Position and description of bits in PORT WRED CELL Threshold Green & Yellow\nMemory", 2172 /* PORT_WRED_CELL_THD_1_FIELDS */ "Position and description of bits in PORT WRED CELL Threshold Red & non-tcp\nMemory", 2173 /* PORT_WRED_CFG_CELL_FIELDS */ "Position and description of bits in Port WRED Average QSize and Config\nRegisters for Cell\nWhen do register read/write test to this register,\nplease DO reset\n MISCCONFIG.REFRESH_EN = 0\n MISCCONFIG.PARITY_GEN_EN = 0\n MISCCONFIG.PARITY_CHK_EN = 0\nThis is to prevent data being overwrite by internal refresh\nprocess.", 2174 /* PORT_WRED_CFG_PACKET_FIELDS */ "Position and description of bits in Port WRED Average QSize and Config\nRegisters for Packet\nWhen do register read/write test to this register,\nplease DO reset\n MISCCONFIG.REFRESH_EN = 0\n MISCCONFIG.PARITY_GEN_EN = 0\n MISCCONFIG.PARITY_CHK_EN = 0\nThis is to prevent data being overwrite by internal refresh\nprocess.", 2175 /* PORT_WRED_PACKET_THD_0_FIELDS */ "Position and description of bits in PORT WRED PACKET Threshold Green & Yellow\nMemory", 2176 /* PORT_WRED_PACKET_THD_1_FIELDS */ "Position and description of bits in PORT_WRED PACKET Threshold Red & non-tcp\nMemory", 2177 /* PPD3_DATA_CONTAINER */ "PPD3 data container", 2178 /* PQE_REG_DATA */ "purge queue register data width", 2179 /* PQE_S_RF */ "purge queue memory s_rf width", 2180 /* PQE_TO_E2EFC_INFO_BUS */ "Position and description of bits in the PQE to E2EFC INFO bus", 2181 /* PQE_TO_THDI_INFO */ "Position and description of bits in the PQE to THDO INFO bus", 2182 /* PQE_TO_THDO4_INFO */ "Position and description of bits in the PQE to THDO INFO bus", 2183 /* PQE_TO_THDO_INFO */ "Position and description of bits in the PQE to THDO INFO bus", 2184 /* PRE_COUNTER_UPDATE_VECTOR */ "Bit Definitions of the Pre counter update vector.", 2185 /* PROTECTION_ACTION_SET */ "PDD Output Bus generic format", 2186 /* PROTECTION_GROUP_ACTION_SET */ "PDD Output Bus generic format", 2187 /* PROTECTION_NHI_ACTION_SET */ "PDD Output Bus generic format", 2188 /* PTP_1588_SIGNALS_TO_PM */ "Passthrough signals from EP to PM through EDB.", 2189 /* PTP_HDR */ "1588 PTP header first 16B field define", 2190 /* PWCW_HDR */ "Pseudowire Control Word and ACH header specification", 2191 /* QCN_DESCP_INFO */ "Position and description of bits in the QCN Descriptor", 2192 /* QCN_TO_TOQ_INFO */ "Position and description of bits in the TOQ to QCN INFO bus", 2193 /* QGPORT_TO_IP_CONTROL_WORD */ "GPORT/XPORT to IP Control Word Format", 2194 /* QID_ENQ_RQE_STORE_INFO */ "Position and description of bits", 2195 /* QOS_ACTION_SET */ "PDD Output Bus generic format", 2196 /* QOS_A_ACTION_SET */ "PDD Output Bus generic format", 2197 /* QOS_B_ACTION_SET */ "PDD Output Bus generic format", 2198 /* QTAG_ACTION_SET */ "PDD Output Bus generic format", 2199 /* RDBGC_TRIGGERS */ "Bit Definitions of the counter vector (used by RDBGC[0-8]_SELECT registers)", 2200 /* RDEHDR_S_RF */ "rdeheader memory s_rf width", 2201 /* RDE_ADM_TO_TXQ_INFO */ "", 2202 /* RDE_COSPCP_S_RF */ "rde cospcp table memory s_rf width", 2203 /* RDE_DESCP_S_RF */ "rde descp memory s_rf width", 2204 /* RDE_FIFO_TO_ADM_REAL_PIPE_INFO */ "Send DEQ_REAL_CELL_FIFO and EP_TO_MMU_REDIRECTION_BUS (non-paasthru) data", 2205 /* RDE_FIFO_TO_ADM_REL_PIPE_INFO */ "", 2206 /* RDE_FLST_S_RF */ "rde free list memory s_rf width", 2207 /* RDE_HEADER_INFO */ "Position and description of bits in the REDIRECT HEADER", 2208 /* RDE_PLNK_S_RF */ "rde pkt link memory s_rf width", 2209 /* RDE_PRCP_S_RF */ "rde prcp memory s_rf width", 2210 /* RDE_TO_CCP_INFO */ "RDE to DEQ info bus", 2211 /* RDE_TO_DEQ_INFO */ "RDE to DEQ info bus", 2212 /* RDE_TO_THDO_RDEE_INFO */ "RDE to THDO RDEE Enqueue Bus", 2213 /* RDE_TO_THDO_RDEE_REL_INFO */ "RDE to THDO RDEE Enqueue Bus", 2214 /* RDE_TO_THDO_RDEI_INFO */ "RDE to THDO RDEI Enqueue Bus", 2215 /* RDE_TO_THDO_RDEI_REL_INFO */ "RDE to THDO RDEI Enqueue Bus", 2216 /* RDE_TO_THDO_RDEQ_DEQ_INFO */ "RDE to THDO RDEQ Dequeue Bus", 2217 /* RDE_TO_THDO_RDEQ_INFO */ "RDE to THDO RDEQ Enqueue Bus", 2218 /* RDE_TO_TOQ_FIFO_MEM */ "RDE to TOQ 2 ENQ to 1 ENQ conversion FIFO.", 2219 /* RDE_TO_TOQ_INFO */ "Position and description of bits in the REDIRECT to TOQ bus", 2220 /* RDE_TXQ_WR_FIFO_INFO */ "RQE QMGR WR_FIFO data format", 2221 /* REDIRECT_TO_CCP_INFO */ "Position and description of bits in the REDIRECT to CCP INFO bus", 2222 /* REDIRECT_TO_THDI_INFO */ "Position and description of bits in the REDIRECT to THDI INFO bus", 2223 /* REDIRECT_TO_THDO3_INFO */ "Position and description of bits in the REDIRECT to THDO INFO bus", 2224 /* REDIRECT_TO_THDO_INFO */ "Position and description of bits in the REDIRECT to THDO INFO bus", 2225 /* REFRESH_BITMAP */ "Ingress Pipeline Resource Control Bus.", 2226 /* REGADDR */ "Register Address Format.", 2227 /* REMAP_TABLE */ "Remapping table (key+1).", 2228 /* REMAP_TABLE_ECC */ "Remapping table (key+1).", 2229 /* REQ_BUS_CP */ "Requst Bus for CB.", 2230 /* REQ_BUS_EXT_AD */ "ESMIF Request.", 2231 /* REQ_BUS_HITBIT */ "HITBIT Update Request Interface.", 2232 /* REQ_BUS_MAC_LIMIT */ "Mac Limit Request for SOPs.", 2233 /* REQ_BUS_MAC_LIMIT_CP */ "Requst Bus for Mac Limit Resource Block.", 2234 /* REQ_BUS_MOD_FIFO_CP */ "Requst Bus for Mac Limit Resource Block.", 2235 /* REQ_BUS_PIPE_TBL0 */ "Key Search Requst Bus for TBL0 (Ivxlt VLAN_XLATE request).", 2236 /* REQ_BUS_PIPE_TBL1 */ "Key Search Requst Bus for TBL1 (Il2lu request).", 2237 /* REQ_BUS_PIPE_TBL2 */ "Key Search Requst Bus for TBL2 (Il3lu request).", 2238 /* REQ_BUS_PIPE_TBL3 */ "Key Search Requst Bus for TBL3 (Evxlt request).", 2239 /* REQ_BUS_PIPE_TBL4 */ "Key Search Requst Bus for TBL4 (Ivxlt MPLS_ENTRY request).", 2240 /* REQ_BUS_PIPE_TBL2_LOGICAL */ "Key Search Requst Bus for TBL2 (Il3lu request), logical view for Arch. RTL does not use this format.", 2241 /* REQ_DATA_EXT_AD_CP */ "ETU Control Plane Request. This is a 35-bit bus (req_data_ext_ad_cp), multi-clock pulse req_ext_ad_cp controls number of beats. Bits 34:0 are sent first, followed by bits 69:35, etc.", 2242 /* REQ_DATA_EXT_L2 */ "ETU External L2 Interface. This is a 35-bit bus (req_data_ext_l2), multi-clock pulse req_ext_l2 controls number of beats. Bits 34:0 are sent first, followed by bits 69:35, etc.", 2243 /* RESPONSIVE_PROTOCOL_MATCH_INDEX */ "RESPONSIVE_PROTOCOL_MATCH index", 2244 /* RIL_TO_DQS_INFO */ "Position and description of bits in the RIL to DQS INFO", 2245 /* RMEP_COV_DEFS */ "defines for flex_ctr coverage analysis", 2246 /* RQE_QCON_FIFO_INFO */ "RQE QCON FIFO", 2247 /* RQE_QID_TO_QCONFLICT_PKT_INFO_LANE */ "Packet details from QID to QCONFLICT in RQE", 2248 /* RQE_QID_TO_QCONFLICT_PKT_INFO_SHARED */ "Packet details from QID to QCONFLICT in RQE", 2249 /* RQE_QMGR_TO_QID_PKT_INFO */ "Packet details from QMGR to QID in RQE", 2250 /* RQE_QMGR_WR_FIFO_INFO */ "RQE QMGR WR_FIFO data format", 2251 /* RQE_TO_E2EFC_QEN_INFO */ "RQE to E2EFC.QENTRY interface format", 2252 /* RQE_TO_E2EFC_RQE_INFO */ "RQE to E2EFC.RQE interface format", 2253 /* RQE_TO_THDIQEN_INFO */ "RQE to THDI.QENTRY interface format", 2254 /* RQE_TO_THDIRQE_INFO */ "RQE to THDI.RQE interface format", 2255 /* RQE_TO_THDM */ "RQE to THDM interface definition.", 2256 /* RQE_TO_THDO_DEQ_INFO */ "Cell dequeue info from RQE to THDO", 2257 /* RQE_TO_THDO_INFO */ "RQE to THDO interface format", 2258 /* RQE_TO_THDO_LANE_INFO */ "RQE to THDO per lane signals", 2259 /* RQE_TO_THDO_RDEE_INFO */ "RQE to THDO RDEE Dequeue Bus", 2260 /* RQE_TO_THDO_RDEI_INFO */ "RQE to THDO RDEI Dequeue Bus", 2261 /* RQE_TO_THDO_REPL_INFO */ "MC packet info from RQE to THDO", 2262 /* RQE_TO_THDO_RQEE_DEQ_INFO */ "Cell dequeue info from RQE to THDO RQEE", 2263 /* RQE_TO_THDO_RQEE_INFO */ "Cell dequeue info from RQE to THDO RQEE", 2264 /* RQE_TO_THDO_RQEI_DEQ_INFO */ "Cell dequeue info from RQE to THDO RQEI", 2265 /* RQE_TO_THDO_RQEI_INFO */ "Cell dequeue info from RQE to THDO RQEI", 2266 /* RQE_TO_THDO_RQEQ_INFO */ "Cell dequeue info from RQE to THDO RQEI", 2267 /* RQE_TO_THDO_UC_ENQ_INFO */ "Unicast ENQ signals from RQE to THDO", 2268 /* RQE_TO_TOQ_PKT_INFO */ "Packet details from RQE to TOQ", 2269 /* RQE_TO_WRED_LANE_INFO */ "RQE to WRED ENQ info", 2270 /* RQE_WF_ENTRY_INFO */ "RQE_WF_ENTRY_INFO", 2271 /* RSEL1_0_DOP */ "RSEL1_0_DOP DOP description.", 2272 /* RSEL1_1_DOP */ "RSEL1_1_DOP DOP description.", 2273 /* RSEL1_2_DOP */ "RSEL1_2_DOP DOP description.", 2274 /* RSEL1_3_DOP */ "RSEL1_3_DOP DOP description.", 2275 /* RSEL1_FIRST_DVP_NHI_DOP */ "RSEL1_FIRST_DVP_NHI_DOP DOP description.", 2276 /* RSEL1_FIRST_ECMP_DOP */ "RSEL1_FIRST_ECMP_DOP DOP description.", 2277 /* RSEL1_SECOND_DVP_NHI_DOP */ "RSEL1_SECOND_DVP_NHI_DOP DOP description.", 2278 /* RSEL1_SECOND_ECMP_DOP */ "RSEL1_SECOND_ECMP_DOP DOP description.", 2279 /* RSEL2_0_DOP */ "RSEL2_0_DOP DOP description.", 2280 /* RSEL2_1_DOP */ "RSEL2_1_DOP DOP description.", 2281 /* RSEL2_2_DOP */ "RSEL2_2_DOP DOP description.", 2282 /* RSEL2_3_DOP */ "RSEL2_3_DOP DOP description.", 2283 /* RSEL2_DROP_VECTOR */ "Bit Definitions of the RSEL2 drop vector.", 2284 /* RSEL2_FIRST_DVP_NHI_DOP */ "RSEL2_FIRST_DVP_NHI_DOP DOP description.", 2285 /* RSEL2_FIRST_ECMP_DOP */ "RSEL2_FIRST_ECMP_DOP DOP description.", 2286 /* RSEL2_SECOND_DVP_NHI_DOP */ "RSEL2_SECOND_DVP_NHI_DOP DOP description.", 2287 /* RSEL2_SECOND_ECMP_DOP */ "RSEL2_SECOND_ECMP_DOP DOP description.", 2288 /* RSEL_DROP_VECTOR */ "Bit Definitions of the RSEL drop vector.", 2289 /* RSP_WORD */ "ALWAYS sent as 32 lsbs for sbus_req: INSERT, DELETE, LOOKUP.", 2290 /* RSP_WORD_0 */ "ALWAYS sent as 32 lsbs for all entries in EXT_L2_MOD_FIFO and\n for sbus_req: INSERT, DELETE, LOOKUP.\n Sent for READ, WRITE sbus_req ONLY for off-chip tables", 2291 /* RSP_WORD_1 */ "Response word 1, additional information about failures is encoded here", 2292 /* RSP_WORD_2 */ "Response word 2, additional information about failures is encoded here", 2293 /* RTAG7_HASH_VALUES_DOP */ "RTAG7_HASH_VALUES_DOP DOP description.", 2294 /* RTS_INTERRUPTS */ "iProc interrups", 2295 /* RXDP_ASM */ "IL-LA MAC RX LBUS interface", 2296 /* RXDP_LBUS */ "IL-LA MAC RX LBUS interface", 2297 /* RXDP_RSP_CW_FMT */ "Control signals for ILA-MAC RX LBUS", 2298 /* RXLP_DEBUG_TRIGGERS */ "Events counted on per-stream basis", 2299 /* S0 */ "Phase 0 of S-bus message", 2300 /* SBUSDMA_ERROR_VEC */ "Error_vec indication in CMIC SBUSDMA operation", 2301 /* SBUS_TCAM_LOOKUP_RSP_WORD */ "SBUS TCAM LOOKUP Response word", 2302 /* SD_TAG_ACTION_SET */ "PDD Output Bus generic format", 2303 /* SD_TAG_DATA_FORMAT */ "Define data fields for SD_TAG", 2304 /* SD_TAG_DATA_FORMAT_DOUBLE */ "Define data fields for SD_TAG", 2305 /* SEQUENCE_NUMBER_ACTION_SET */ "PDD Output Bus generic format", 2306 /* SER_STATUS_BUS */ "SER Status Bus Format.", 2307 /* SFLOW_ING_DATA_SOURCE_COV_DEFS */ "defines for sflow_ing_data_source coverage analysis", 2308 /* SFLOW_ING_FLEX_DATA_SOURCE_COV_DEFS */ "defines for sflow_ing_flex_data_source coverage analysis", 2309 /* SGLP_ACTION_SET */ "PDD Output Bus generic format", 2310 /* SGPP_SUBPORT_ID_SGPP_MAP_DOP */ "SGPP_SUBPORT_ID_SGPP_MAP_DOP DOP description.", 2311 /* SHARED_BANKS_CONTROL */ "UFT or UAT Banks Hash Control.", 2312 /* SM_RES_HDR */ "Signature match engine results header", 2313 /* SNAP_HDR */ "8B SNAP-LLC header specification", 2314 /* SNAT_NAT_INDICES_DOP */ "SNAT_NAT_INDICES_DOP DOP description.", 2315 /* SOBMH */ "Bit Definitions of the Internal Stream of Bytes Module Header", 2316 /* SOP_CONTROL */ "SOP_CONTROL, formed by ENQ from MPB fields and written with payload to CBP", 2317 /* SOP_CONTROL_1 */ "SOP_CONTROL_1, formed by ENQ from MPB fields and written with payload to CBP", 2318 /* SPECIAL_LABEL_PUSH_TYPE_FORMAT */ "MPLS special label format", 2319 /* SS_BANK_WR_INTF */ "This is the WR interface for BANK's PORT B .", 2320 /* SS_BASE_VALID_OUT */ "Format used to align a raw key to base_0_key, base_1_key, base_2_key and base_3_key.", 2321 /* SS_ECC_ENTRY_BUS */ "Format used to align a raw key to base_0_key, base_1_key, base_2_key and base_3_key.", 2322 /* SS_LOGICAL_BKT_IDX_BUS */ "Format used to align a raw key to base_0_key, base_1_key, base_2_key and base_3_key.", 2323 /* SS_REQ_BUS */ "Search Stage Request Bus.", 2324 /* SS_REQ_BUS0 */ "Search Stage Request Bus (VLAN_XLATE).", 2325 /* SS_REQ_BUS1 */ "Search Stage Request Bus (L2_ENTRY).", 2326 /* SS_REQ_BUS2 */ "Search Stage Request Bus (L3_ENTRY).", 2327 /* SS_REQ_BUS3 */ "Search Stage Request Bus (EP_VLAN_XLATE).", 2328 /* SS_REQ_BUS4 */ "Search Stage Request Bus (ISM).", 2329 /* SS_REQ_BUS5 */ "Search Stage Request Bus (ISM).", 2330 /* SS_REQ_BUS6 */ "Search Stage Request Bus (MPLS_ENTRY).", 2331 /* SS_REQ_BUS0_C_MODEL */ "Search Stage Request Bus (VLAN_XLATE).", 2332 /* SS_REQ_BUS1_C_MODEL */ "Search Stage Request Bus (L2_ENTRY).", 2333 /* SS_REQ_BUS2_C_MODEL */ "Search Stage Request Bus (L3_ENTRY).", 2334 /* SS_REQ_BUS3_C_MODEL */ "Search Stage Request Bus (EP_VLAN_XLATE).", 2335 /* SS_REQ_BUS4_C_MODEL */ "Search Stage Request Bus (ISM).", 2336 /* SS_REQ_BUS5_C_MODEL */ "Search Stage Request Bus (ISM).", 2337 /* SS_REQ_BUS6_C_MODEL */ "Search Stage Request Bus (MPLS_ENTRY).", 2338 /* SS_REQ_BUS_C_MODEL */ "Search Stage Request Bus.", 2339 /* SS_REQ_BUS_FPEM */ "Search Stage Request Bus (FPEM).", 2340 /* SS_REQ_BUS_IL2LU */ "Search Stage Request Bus (IL2LU).", 2341 /* SS_REQ_BUS_IL3LU */ "Search Stage Request Bus (IL3LU).", 2342 /* SS_REQ_BUS_ILPM */ "Search Stage Request Bus (ILPM).", 2343 /* SS_REQ_BUS_IVLAN */ "Search Stage Request Bus (IVLAN).", 2344 /* SS_REQ_BUS_LPM */ "Search Stage Request Bus.", 2345 /* SS_RST_BUS */ "Search Stage Result Bus.", 2346 /* SS_RST_BUS0 */ "Search Stage Result Bus (VLAN_XLATE).", 2347 /* SS_RST_BUS1 */ "Search Stage Result Bus (L2_ENTRY).", 2348 /* SS_RST_BUS2 */ "Search Stage Result Bus (L3_ENTRY).", 2349 /* SS_RST_BUS3 */ "Search Stage Result Bus (EP_VLAN_XLATE).", 2350 /* SS_RST_BUS4 */ "Search Stage Result Bus (ISM).", 2351 /* SS_RST_BUS5 */ "Search Stage Result Bus (ISM).", 2352 /* SS_RST_BUS6 */ "Search Stage Result Bus (MPLS_ENTRY).", 2353 /* SS_RST_BUS0_C_MODEL */ "Search Stage Result Bus (VLAN_XLATE).", 2354 /* SS_RST_BUS1_C_MODEL */ "Search Stage Result Bus (L2_ENTRY).", 2355 /* SS_RST_BUS2_C_MODEL */ "Search Stage Result Bus (L3_ENTRY).", 2356 /* SS_RST_BUS3_C_MODEL */ "Search Stage Result Bus (EP_VLAN_XLATE).", 2357 /* SS_RST_BUS4_C_MODEL */ "Search Stage Result Bus (ISM).", 2358 /* SS_RST_BUS5_C_MODEL */ "Search Stage Result Bus (ISM).", 2359 /* SS_RST_BUS6_C_MODEL */ "Search Stage Result Bus (MPLS_ENTRY).", 2360 /* SS_RST_BUS_C_MODEL */ "Search Stage Result Bus.", 2361 /* SS_RST_BUS_IN */ "Search Stage Result Bus.", 2362 /* SS_RST_BUS_IN_DATA_FPEM */ "Search Stage Result Bus (FPEM).", 2363 /* SS_RST_BUS_IN_DATA_IL2LU */ "Search Stage Result Bus (IL2LU).", 2364 /* SS_RST_BUS_IN_DATA_IL3LU */ "Search Stage Result Bus (IL3LU).", 2365 /* SS_RST_BUS_IN_DATA_ILPM */ "Search Stage Result Bus (ILPM).", 2366 /* SS_RST_BUS_IN_DATA_IVLAN */ "Search Stage Result Bus (IVLAN).", 2367 /* SS_RST_BUS_IN_FPEM */ "Search Stage Result Bus (FPEM).", 2368 /* SS_RST_BUS_IN_IL2LU */ "Search Stage Result Bus (IL2LU).", 2369 /* SS_RST_BUS_IN_IL3LU */ "Search Stage Result Bus (IL3LU).", 2370 /* SS_RST_BUS_IN_ILPM */ "Search Stage Result Bus (ILPM).", 2371 /* SS_RST_BUS_IN_IVLAN */ "Search Stage Result Bus (IVLAN).", 2372 /* SS_RST_BUS_OUT */ "Search Stage Result Bus.", 2373 /* SS_RST_BUS_OUT_FPEM */ "Search Stage Result Bus (FPEM).", 2374 /* SS_RST_BUS_OUT_IL2LU */ "Search Stage Result Bus (IL2LU).", 2375 /* SS_RST_BUS_OUT_IL3LU */ "Search Stage Result Bus (IL3LU).", 2376 /* SS_RST_BUS_OUT_ILPM */ "Search Stage Result Bus (ILPM).", 2377 /* SS_RST_BUS_OUT_IVLAN */ "Search Stage Result Bus (IVLAN).", 2378 /* SS_RST_BUS_OUT_LPM */ "Search Stage Result Bus, LPM optimized.", 2379 /* SS_RST_BUS_OUT_SEARCH_FPEM */ "Search Stage Result Bus (FPEM), optimized for key search only lanes.", 2380 /* SS_RST_BUS_OUT_SEARCH_IL2LU */ "Search Stage Result Bus (IL2LU), optimized for key search only lanes.", 2381 /* SS_RST_BUS_OUT_SEARCH_IL3LU */ "Search Stage Result Bus (IL3LU), optimized for key search only lanes.", 2382 /* SS_RST_BUS_OUT_SEARCH_ILPM */ "Search Stage Result Bus (ILPM), optimized for key search only lanes.", 2383 /* SS_RST_BUS_OUT_SEARCH_IVLAN */ "Search Stage Result Bus (IVLAN), optimized for key search only lanes.", 2384 /* STUB_TO_SWITCH_SCH */ "Data portion of Switch to Stub SCH header", 2385 /* SUBNET_PROTOCOL_DOP */ "SUBNET_PROTOCOL_DOP DOP description.", 2386 /* SVM_ACTIONS */ "SVM action format", 2387 /* SVM_COMPRESSED_PKT_ATTR */ "compressed packet attribute", 2388 /* SVM_CTR_UDF */ "SVM udf fields definition", 2389 /* SVM_IN_BUS */ "SVM input format", 2390 /* SVM_METER_INDEX_EOP_BUFFER */ "Input bus for meter index generator", 2391 /* SVM_METER_INFO_FROM_SOURCE */ "Meter info from source table", 2392 /* SVM_METER_TABLE_COV_DEFS */ "defines for svm coverage analysis", 2393 /* SVM_MTR_PIPE_CTRL_BUS */ "Bus for carrying meter parameters across the meter pipeline", 2394 /* SVM_MTR_PIPE_DATA_BUS */ "Bus for carrying meter data across the meter pipeline", 2395 /* SVM_OUT_BUS */ "SVM output format", 2396 /* SVM_PKT_ATTR */ "packet attribute", 2397 /* SVM_UPDATE_BITMAP_EOP_BUFFER */ "EOP buffer to store update bitmaps and other info", 2398 /* SVP_ACTION_SET */ "PDD Output Bus generic format", 2399 /* SVP_SOURCE */ "Denote the source where SVP is from.", 2400 /* SW2_0_DOP */ "SW2_0_DOP DOP description.", 2401 /* SW2_1_DOP */ "SW2_1_DOP DOP description.", 2402 /* SW2_EOP_BUFFER */ "Bit Definitions of SW2_EOP_BUFFER", 2403 /* SW2_EOP_BUFFER_A */ "Bit Definitions of SW2_EOP_BUFFER_A", 2404 /* SW2_EOP_BUFFER_B */ "Bit Definitions of SW2_EOP_BUFFER_B", 2405 /* SW2_EOP_BUFFER_C */ "Bit Definitions of SW2_EOP_BUFFER_C", 2406 /* SW3_0_DOP */ "SW3_0_DOP DOP description.", 2407 /* SW3_EOP_BUFFER_A */ "Bit Definitions of SW3_EOP_BUFFER_A.", 2408 /* SW3_EOP_BUFFER_B */ "Bit Definitions of SW3_EOP_BUFFER_B.", 2409 /* SWITCHING_CTRLS_ACTION_SET */ "PDD Output Bus generic format", 2410 /* SWITCH_TO_STUB_SCH */ "Data portion of Switch to Stub SCH header", 2411 /* SW_COUNTER_UPDATE_VECTOR */ "Bit Definitions of the sw counter update vector.", 2412 /* SW_EOP_BUFFER_B */ "Bit Definitions of SW_EOP_BUFFER_B.", 2413 /* SYSTEM_HVE_OUTPUT_BUS */ "SYSTEM HVE (header verfication engine) output bus format.", 2414 /* SYSTEM_HVE_TRIGGERS_FORMAT */ "SYSTEM HVE (header verfication engine) trigger format for HVE0.", 2415 /* TABLE_MANAGEMENT_ACTION_SET */ "PDD Output Bus generic format", 2416 /* TAF_GATE_STATUS */ "8-bits interface from TAF Gate Control Generator maps to Isw1 Qci parameters.", 2417 /* TAG_ACTION */ "TAG Action Encoding.", 2418 /* TAG_ACTION_PROFILE_ACTION_SET */ "PDD Output Bus generic format", 2419 /* TAG_ACTION_SET */ "PDD Output Bus generic format", 2420 /* TAP_CNTRL_MOTP */ "tap control interface for motp", 2421 /* TAP_STATUS_MOTP */ "tap control status for motp", 2422 /* TCACHE_LMGR_STATE */ "Format TCACHE Location manager Allocation Structure", 2423 /* TCAM_RSP_CTB_WR_CMP */ "DW0 and DW1 of TCAM context buffer write and compare 1 & 2 response format", 2424 /* TCP_ACK */ "Tcp ACK flag", 2425 /* TCP_FIN */ "Tcp FIN flag", 2426 /* TCP_FLAGS */ "Tcp header flags", 2427 /* TCP_HDR */ "TCP header specification", 2428 /* TCP_PSH */ "Tcp PSH flag", 2429 /* TCP_RST */ "Tcp RST flag", 2430 /* TCP_SYN */ "Tcp SYN flag", 2431 /* TCP_UDP_SCTP */ "TCP, UDP, SCTP common field define", 2432 /* TCP_URG */ "Tcp URG flag", 2433 /* TDBGC_TRIGGERS */ "Bit Definitions of the counter vector (used by TDBGC[0-11]_SELECT registers)", 2434 /* THDIEMA_THDI_PORT_PG_BST */ "This memory contains shadow copies, or maximum values of selected counters that are updated in the Per Port per PG memory array. Every cycle, up to two entries will be updated, or a single entry will be updated via a RMW (depending on chip wide configuration).\nMemory address = port_num[0..62] * 8 + pg[0..7].\nEach Entry contains:\n* ing_ptpg_bst_par: Even parity across the row\n* Ing_PG_BST_Stat_Shared: Cells occupied in the shared space for this Port PG\n* Ing_PG_BST_Threshold_Profile_Shared: Which ...", 2435 /* THDIEMA_THDI_PORT_SP_BST */ "This memory contains the counters and configuration that needs to be stored on a per port per service pool basis. Every cycle, up to two entries will be updated via a RMW operation.\nMemory address = port_num[0..62] * 4 + sp[0..3].\nEach Entry contains:\n* ing_ptsp_bst_par: Even Parity across bits 17:0\n* Ing_Port_SP_BST_Stat: Number of cells currently in use for this Port SP\n* Ing_Port_SP_BST_Threshold_Profile: Which of the eight compare profiles should be used to force a trigger.", 2436 /* THDIEXT_THDI_PORT_PG_BST */ "This memory contains shadow copies, or maximum values of selected counters that are updated in the Per Port per PG memory array. Every cycle, up to two entries will be updated, or a single entry will be updated via a RMW (depending on chip wide configuration).\nMemory address = port_num[0..62] * 8 + pg[0..7].\nEach Entry contains:\n* ing_ptpg_bst_par: Even parity across the row\n* Ing_PG_BST_Stat_Shared: Cells occupied in the shared space for this Port PG\n* Ing_PG_BST_Threshold_Profile_Shared: Which ...", 2437 /* THDIEXT_THDI_PORT_SP_BST */ "This memory contains the counters and configuration that needs to be stored on a per port per service pool basis. Every cycle, up to two entries will be updated via a RMW operation.\nMemory address = port_num[0..62] * 4 + sp[0..3].\nEach Entry contains:\n* ing_ptsp_bst_par: Even Parity across bits 17:0\n* Ing_Port_SP_BST_Stat: Number of cells currently in use for this Port SP\n* Ing_Port_SP_BST_Threshold_Profile: Which of the eight compare profiles should be used to force a trigger.", 2438 /* THDIQEN_THDI_PORT_PG_BST */ "This memory contains shadow copies, or maximum values of selected counters that are updated in the Per Port per PG memory array. Every cycle, up to two entries will be updated, or a single entry will be updated via a RMW (depending on chip wide configuration).\nMemory address = port_num[0..62] * 8 + pg[0..7].\nEach Entry contains:\n* ing_ptpg_bst_par: Even parity across the row\n* Ing_PG_BST_Stat_Shared: Cells occupied in the shared space for this Port PG\n* Ing_PG_BST_Threshold_Profile_Shared: Which ...", 2439 /* THDIQEN_THDI_PORT_SP_BST */ "This memory contains the counters and configuration that needs to be stored on a per port per service pool basis. Every cycle, up to two entries will be updated via a RMW operation.\nMemory address = port_num[0..62] * 4 + sp[0..3].\nEach Entry contains:\n* ing_ptsp_bst_par: Even Parity across bits 17:0\n* Ing_Port_SP_BST_Stat: Number of cells currently in use for this Port SP\n* Ing_Port_SP_BST_Threshold_Profile: Which of the eight compare profiles should be used to force a trigger.", 2440 /* THDIRQE_THDI_PORT_PG_BST */ "This memory contains shadow copies, or maximum values of selected counters that are updated in the Per Port per PG memory array. Every cycle, up to two entries will be updated, or a single entry will be updated via a RMW (depending on chip wide configuration).\nMemory address = port_num[0..62] * 8 + pg[0..7].\nEach Entry contains:\n* ing_ptpg_bst_par: Even parity across the row\n* Ing_PG_BST_Stat_Shared: Cells occupied in the shared space for this Port PG\n* Ing_PG_BST_Threshold_Profile_Shared: Which ...", 2441 /* THDIRQE_THDI_PORT_SP_BST */ "This memory contains the counters and configuration that needs to be stored on a per port per service pool basis. Every cycle, up to two entries will be updated via a RMW operation.\nMemory address = port_num[0..62] * 4 + sp[0..3].\nEach Entry contains:\n* ing_ptsp_bst_par: Even Parity across bits 17:0\n* Ing_Port_SP_BST_Stat: Number of cells currently in use for this Port SP\n* Ing_Port_SP_BST_Threshold_Profile: Which of the eight compare profiles should be used to force a trigger.", 2442 /* THDI_PORT_PG_BST */ "This memory contains shadow copies, or maximum values of selected counters that are updated in the Per Port per PG memory array. Every cycle, up to two entries will be updated, or a single entry will be updated via a RMW (depending on chip wide configuration).\nMemory address = port_num[0..62] * 8 + pg[0..7].\nEach Entry contains:\n* ing_ptpg_bst_par: Even parity across the row\n* Ing_PG_BST_Stat_Shared: Cells occupied in the shared space for this Port PG\n* Ing_PG_BST_Threshold_Profile_Shared: Which ...", 2443 /* THDI_PORT_SP_BST */ "This memory contains the counters and configuration that needs to be stored on a per port per service pool basis. Every cycle, up to two entries will be updated via a RMW operation.\nMemory address = port_num[0..62] * 4 + sp[0..3].\nEach Entry contains:\n* ing_ptsp_bst_par: Even Parity across bits 17:0\n* Ing_Port_SP_BST_Stat: Number of cells currently in use for this Port SP\n* Ing_Port_SP_BST_Threshold_Profile: Which of the eight compare profiles should be used to force a trigger.", 2444 /* THDI_TO_CFG_INFO */ "THDI to CFG interface format", 2445 /* THDI_TO_OOBFC_INFO */ "Position and description of bits in the THDI to OOBFC bus", 2446 /* THDI_TO_REDIRECT_INFO */ "Position and description of bits in the THDI to REDIRECT INFO bus", 2447 /* THDI_TO_WAMU */ "Position and description of bits in the THDI to WAMU bus", 2448 /* THDM_STAGE_SIG */ "THDM DB stage sig definition.", 2449 /* THDM_THDU_PIPE_SIG */ "Internal pipeline signals for THDU updates, merge enq and deq events.", 2450 /* THDM_THDU_SP_PIPE_SIG */ "Internal pipeline signals for THDU updates for SP, merge enq and deq events.", 2451 /* THDM_TO_RQE */ "THDM_TO_RQE interface definition.", 2452 /* THDO_MIRROR_INFO */ "Position and description of bits in the per-source-port mirror information stored in THDO", 2453 /* THDO_OPN_INFL_CNT_INFO */ "THDO in-flight counter format", 2454 /* THDO_QUEUE_INFL_CNT_INFO */ "THDO in-flight counter format", 2455 /* THDO_TO_CTR_ENQ_INFO */ "Format TCACHE Location manager Allocation Structure", 2456 /* THDO_TO_INTFO_OOBFC */ "Position and description of bits in the per-source-port mirror information stored in THDO", 2457 /* THDO_TO_REDIRECT_INFO */ "Position and description of bits in the THDO to REDIRECT INFO bus", 2458 /* THDO_TO_RQE_INFO */ "THDO to RQE interface format", 2459 /* THDO_TO_WAMU */ "Position and description of bits in the THDO to WAMU bus", 2460 /* THDU_TO_THDM_DEQ */ "Position and description from THDO UC and THDO MC for dequeue event.", 2461 /* THDU_TO_THDM_ENQ */ "Position and description from THDO UC and THDO MC for enqueue event.", 2462 /* TIMESTAMP_RECORD */ "Metadata record format for inserting at the tail\n of data packets", 2463 /* TOQ_CELL_DESCRIPTOR_INFO */ "", 2464 /* TOQ_CFG_CONFIG */ "Position and description of bits in the TOQ PORT COSQ INFO bus, selected by es_to_toq_queue.", 2465 /* TOQ_COMMON_DEQ_CTRL */ "", 2466 /* TOQ_COS_Q_INFO */ "Position and description of bits in the TOQ COS Q INFO bus", 2467 /* TOQ_CPU_PORT_COSQ_INFO */ "Position and description of bits in the TOQ CPU PORT COSQ INFO bus", 2468 /* TOQ_CPU_PORT_COSQ_PKT_RD_PTR */ "Position and description of bits in the TOQ PORT COSQ PKT RD_PTR bus", 2469 /* TOQ_CPU_PORT_COSQ_STATE */ "Position and description of bits in the TOQ PORT COSQ STATE bus", 2470 /* TOQ_CQEBN_CACHE_ENTRY */ "", 2471 /* TOQ_DATA_OUT_INFO */ "TOQ_DATA_OUT_INFO", 2472 /* TOQ_EXEC_DEQ_CTRL */ "", 2473 /* TOQ_EXEC_ENQ_CTRL */ "", 2474 /* TOQ_MCFIFO_CHANNEL */ "Format of the data entering TOQ pipeline Stage 0", 2475 /* TOQ_MCFIFO_ENTRY */ "Format of the data entering TOQ pipeline Stage 0", 2476 /* TOQ_NEW_1CELL_INFO */ "Position and description of bits in the TOQ NEW 1CELL INFO bus", 2477 /* TOQ_NEW_CELL_INFO */ "Position and description of bits in the TOQ NEW CELL INFO bus", 2478 /* TOQ_NEW_PGQ_INFO */ "Position and description of bits in the TOQ NEW TOQ INFO bus", 2479 /* TOQ_NEW_PKTHDR1_INFO */ "Position and description of bits in the TOQ NEW PKTHDR1 INFO bus", 2480 /* TOQ_NEW_SAVED_INFO */ "Position and description of bits in the TOQ NEW SAVED INFO bus", 2481 /* TOQ_NEW_TOQ2_INFO */ "Position and description of bits in the TOQ NEW TOQ 2 INFO bus", 2482 /* TOQ_NEW_TOQ_INFO */ "Position and description of bits in the TOQ NEW TOQ INFO bus", 2483 /* TOQ_PKTHDR1_INFO */ "Position and description of bits in the TOQ NEW CELL INFO bus", 2484 /* TOQ_PORT_COSQ_INFO */ "Position and description of bits in the TOQ PORT COSQ INFO bus", 2485 /* TOQ_PORT_COSQ_PKT_RD_PTR */ "Position and description of bits in the TOQ PORT COSQ PKT RD PTR bus", 2486 /* TOQ_PORT_COSQ_STATE */ "Position and description of bits in the TOQ PORT COSQ STATE bus", 2487 /* TOQ_PORT_SEL_COSQ_INFO */ "Position and description of bits in the TOQ PORT COSQ INFO bus, selected by es_to_toq_queue.", 2488 /* TOQ_PSTAGE0_INFO */ "Format of the data entering TOQ pipeline Stage 0", 2489 /* TOQ_PSTAGE1_DEQ_INFO */ "Format of the data entering TOQ pipeline Stage 1, pipeline 1 that can be either DEQ or ENQ operation", 2490 /* TOQ_PSTAGE1_ENQ_INFO */ "Format of the data entering TOQ pipeline Stage 1 for ENQ operations", 2491 /* TOQ_PURGE_Q_INFO */ "Position and description of bits in the TOQ PURGE Q INFO bus", 2492 /* TOQ_REPPKT_INFO */ "Position and description of bits in the TOQ REPLICATE PACKET INFO bus", 2493 /* TOQ_RQE_CHANNEL_INFO */ "Individual channel ENQ format for RQE_FIFO", 2494 /* TOQ_RQE_FIFO */ "Definition of RQE_FIFO data bus, carrying 8 x ENQ info channels", 2495 /* TOQ_RQE_FIFO_MEM_DATA */ "FORMAT OF THE DATA TO BE STORED IN EACH OF 4 RQE FIFOs", 2496 /* TOQ_SHARE_Q_INFO */ "Position and description of bits in the TOQ SHARED Q INFO bus", 2497 /* TOQ_SV2_PKTHDR1 */ "Position and description of bits in the TOQ NEW TOQ 2 INFO bus", 2498 /* TOQ_TCACHE_STATUS_INFO_0 */ "Format of the TCACHE INFO_0 Status Bus", 2499 /* TOQ_TCT_EB_STATE */ "", 2500 /* TOQ_TO_DEQ_CELL_INFO */ "Position and description of bits in the TOQ to DEQ CELL INFO bus", 2501 /* TOQ_TO_DEQ_RDE_INFO */ "Position and description of bits in the TOQ RDE Q INFO bus", 2502 /* TOQ_TO_DEQ_REP_INFO */ "Position and description of bits in the TOQ to DEQ REP INFO bus", 2503 /* TOQ_TO_DEQ_WLP_INFO */ "Position and description of bits in the TOQ WLP Q INFO bus", 2504 /* TOQ_TO_DQS_CELL_INFO */ "Position and description of bits in the TOQ to DEQ CELL INFO bus", 2505 /* TOQ_TO_DQS_REP_INFO */ "Position and description of bits in the TOQ to DEQ REP INFO bus", 2506 /* TOQ_TO_RDE */ "Position and description of bits in the TOQ to RDE bus", 2507 /* TOQ_TO_THDM */ "RQE to THDM interface definition.", 2508 /* TOQ_WLP_SAVED_INFO */ "Position and description of bits in the TOQ NEW SAVED INFO bus", 2509 /* TRILL */ "", 2510 /* TRILL_CPU_OPCODE_ENCODING */ "Bit Definitions of the TRILL CPU Opcode encoding", 2511 /* TRILL_HDR */ "TRILL header specification", 2512 /* TRUNK_GROUP_RRLB_CNT_COV_DEFS */ "defines for trunk_group_rrlb_cnt coverage analysis", 2513 /* TTL_B */ "TTL .", 2514 /* TTL_B_ACTION_SET */ "PDD Output Bus generic format", 2515 /* TUNNEL_ADAPT_1_FIXED_KEY_TABLE_ATTRS_INDEX */ "TUNNEL_ADAPT_1_FIXED_KEY_TABLE_ATTRS index", 2516 /* TUNNEL_ADAPT_1_FLEX_KEY_GEN_IN_CONTROL_BUS */ "FlexKeyGen Input Control Bus1 for VXLT_1", 2517 /* TUNNEL_ADAPT_1_FLEX_KEY_GEN_OUT_BUS */ "FlexKeyGen Output bus VXLT_1", 2518 /* TUNNEL_ADAPT_1_PDD_OUT_BUS */ "PDD Output Bus generic format", 2519 /* TUNNEL_ADAPT_2_FIXED_KEY_TABLE_ATTRS_INDEX */ "TUNNEL_ADAPT_2_FIXED_KEY_TABLE_ATTRS index", 2520 /* TUNNEL_ADAPT_2_FLEX_KEY_GEN_IN_CONTROL_BUS */ "FlexKeyGen Input Control Bus2 for MPLS_ENTRY", 2521 /* TUNNEL_ADAPT_2_FLEX_KEY_GEN_OUT_BUS */ "FlexKeyGen Output bus MPLS_ENTRY", 2522 /* TUNNEL_ADAPT_2_PDD_OUT_BUS */ "PDD Output Bus generic format", 2523 /* TUNNEL_ADAPT_3_FIXED_KEY_TABLE_ATTRS_INDEX */ "TUNNEL_ADAPT_3_FIXED_KEY_TABLE_ATTRS index", 2524 /* TUNNEL_ADAPT_3_FLEX_KEY_GEN_IN_CONTROL_BUS */ "FlexKeyGen Input Control Bus2 for L3_TUNNEL", 2525 /* TUNNEL_ADAPT_3_FLEX_KEY_GEN_OUT_BUS */ "FlexKeyGen Output bus L3 TUNNEL", 2526 /* TUNNEL_ADAPT_3_PDD_OUT_BUS */ "PDD Output Bus generic format", 2527 /* TUNNEL_ADAPT_4_FLEX_KEY_GEN_IN_CONTROL_BUS */ "FlexKeyGen Input Control Bus for VXLT_2 keygen TCAM lookups", 2528 /* TUNNEL_ADAPT_4_FLEX_KEY_GEN_OUT_BUS */ "FlexKeyGen Output bus VXLT_2", 2529 /* TUNNEL_ADAPT_4_PDD_OUT_BUS */ "PDD Output Bus generic format", 2530 /* TUNNEL_ADAPT_ATTRIBUTES_ACTION_SET */ "PDD Output Bus generic format", 2531 /* TUNNEL_ADAPT_FLEX_KEY_GEN_IN_BUS */ "Ingress Flex key gen input bus. It is only valid for SOP cell.", 2532 /* TUNNEL_ADAPT_KEYGEN_OBJECT_BUS */ "Tunnel adapt object bus portion of tunnel_adapt_flex_key_gen_in_bus. It is only valid for SOP cell.", 2533 /* TUNNEL_ADAPT_MISC_ACTION_SET */ "PDD Output Bus generic format", 2534 /* TUNNEL_ADAPT_PHB_CTRL_ID_FORMAT */ "TUNNEL_ADAPT_PHB_CTRL_ID format", 2535 /* TUNNEL_PROC_DROP_VECTOR */ "Bit Definitions of the VXLAN / MPLS drop vector.", 2536 /* TUNNEL_PTR_ACTION_SET */ "PDD Output Bus generic format", 2537 /* TUNNEL_TERM_ACTION_SET */ "PDD Output Bus generic format", 2538 /* TUNNEL_TYPE_LOOPBACK_TYPE */ "Description of encodings of TUNNEL_TYPE_LOOPBACK_TYPE.", 2539 /* TXDP_S0_BUS */ "Request External TCAM", 2540 /* TXDP_S2_BUS */ "Combined view of Request External TCAM", 2541 /* TXDP_S2_CW_FMT */ "TXDP stage 2 CW format", 2542 /* TXDP_S3_BUS */ "Tx datapath Stage 3 data bus format", 2543 /* TXDP_S3_CW_BUS */ "Tx datapath Stage 3 control bus format", 2544 /* TXDP_S3_CW_FMT */ "Tx datapath Stage 3 control bus format", 2545 /* TXDP_S3_DW_BUS */ "Tx datapath Stage 3 data bus format", 2546 /* TXDP_S4_BUS */ "Tx datapath Stage 4 data bus format", 2547 /* TXLP_ALGN_TO_BUFFER_CTRL */ "Position and description of bits in Aligner-2-Buffer control-signals", 2548 /* TXLP_ALGN_TO_BUFFER_PASSTHRU_CTRL */ "Position and description of bits in Aligner-2-Buffer Passthru control-signals", 2549 /* TXLP_BUFFER_TO_PORT_CTRL */ "Position and description of bits in Buffer-2-Port control-signals", 2550 /* TXLP_TO_EDB_BUS */ "The signals needed to be sent to EDATABUF for SHAPEing related updates.", 2551 /* TXLP_TO_PORT_CTRL_BUS */ "Position and description of bits in txlp_to_port_ctrl", 2552 /* TXLP_TRIGGERS */ "The Triggers/Events in the TXLP pipeline that can be counted.", 2553 /* UDF_BASE_OFFSET_ENCODING */ "UDF Base Offset Encoding", 2554 /* UDF_TCAM_KEY */ "Bit Definitions of UDF_TCAM_KEY.", 2555 /* UDP_HDR */ "IPv4 header specification", 2556 /* VFI_SOURCE */ "Denote the source where VFI is from.", 2557 /* VFP_DOUBLE_WIDE_F1 */ "Position and description of bits in VFP DOUBLE WIDE F1 FIELDS", 2558 /* VFP_DOUBLE_WIDE_F3 */ "Position and description of bits in VFP DOUBLE WIDE F3 FIELDS", 2559 /* VFP_DOUBLE_WIDE_F2_0 */ "Position and description of bits in VFP DOUBLE WIDE F2_0 FIELDS", 2560 /* VFP_DOUBLE_WIDE_F2_1 */ "Position and description of bits in VFP DOUBLE WIDE F2_1 FIELDS", 2561 /* VFP_DOUBLE_WIDE_F2_2 */ "Position and description of bits in VFP DOUBLE WIDE F2_2 FIELDS", 2562 /* VFP_DOUBLE_WIDE_F2_3 */ "Position and description of bits in VFP DOUBLE WIDE F2_3 FIELDS", 2563 /* VFP_F1 */ "Position and description of bits in VFP F1 FIELDS", 2564 /* VFP_F2_0 */ "Position and description of bits in VFP F2 0 FIELDS", 2565 /* VFP_F2_1 */ "Position and description of bits in VFP F2 1 FIELDS", 2566 /* VFP_F2_2 */ "Position and description of bits in VFP F2 2 FIELDS", 2567 /* VFP_F2_3 */ "Position and description of bits in VFP F2 3 FIELDS", 2568 /* VFP_F2_4 */ "Position and description of bits in VFP F2 4 FIELDS", 2569 /* VFP_F2_5 */ "Position and description of bits in VFP F2 5 FIELDS", 2570 /* VFP_F2_6 */ "Position and description of bits in VFP F2 6 FIELDS", 2571 /* VFP_F2_7 */ "Position and description of bits in VFP F2 7 FIELDS", 2572 /* VFP_F2_8 */ "Position and description of bits in VFP F2 8 FIELDS", 2573 /* VFP_F2_9 */ "Position and description of bits in VFP F2 8 FIELDS", 2574 /* VFP_F2_10 */ "Position and description of bits in VFP F2 10 FIELDS", 2575 /* VFP_F3_0 */ "Position and description of bits in VFP F3 0 FIELDS", 2576 /* VFP_F3_1 */ "Position and description of bits in VFP F3 1 FIELDS", 2577 /* VFP_F3_2 */ "Position and description of bits in VFP F3 2 FIELDS", 2578 /* VFP_F3_3 */ "Position and description of bits in VFP F3 3 FIELDS", 2579 /* VFP_F3_4 */ "Position and description of bits in VFP F3 4 FIELDS", 2580 /* VFP_F3_5 */ "Position and description of bits in VFP F3 5 FIELDS", 2581 /* VFP_F3_6 */ "Position and description of bits in VFP F3 6 FIELDS", 2582 /* VFP_KEY_0_DOP */ "VFP_KEY_0_DOP DOP description.", 2583 /* VFP_KEY_1_DOP */ "VFP_KEY_1_DOP DOP description.", 2584 /* VFP_KEY_2_DOP */ "VFP_KEY_2_DOP DOP description.", 2585 /* VFP_KEY_3_DOP */ "VFP_KEY_3_DOP DOP description.", 2586 /* VFP_KEY_4_DOP */ "VFP_KEY_4_DOP DOP description.", 2587 /* VFP_KEY_5_DOP */ "VFP_KEY_5_DOP DOP description.", 2588 /* VFP_KEY_6_DOP */ "VFP_KEY_6_DOP DOP description.", 2589 /* VFP_KEY_7_DOP */ "VFP_KEY_7_DOP DOP description.", 2590 /* VFP_TCAM_DOP */ "VFP_TCAM_DOP DOP description.", 2591 /* VLAN_0 */ "vlan_0 table", 2592 /* VLAN_1 */ "vlan_1 table", 2593 /* VLAN_DROP */ "Bit Definitions of the VLAN drop vector", 2594 /* VLAN_DROP_VECTOR */ "Bit Definitions of the VLAN drop vector.", 2595 /* VLAN_HDR */ "inner/outer vlan shim specification", 2596 /* VLAN_TAG_COMPOSITES */ "Zone l2 tag presence format.", 2597 /* VLAN_TAG_HDR */ "2BYTES OF VLAN TAG HEADER EXCLUDING ETHERTYPE.", 2598 /* VLAN_XLATE_1_DATA */ "Format for VLAN_XLATE_1 DATA.", 2599 /* VLAN_XLATE_2_DATA */ "Format for VLAN_XLATE_2 DATA.", 2600 /* VLAN_XLATE_KEY */ "Format for VLAN_XLATE_1, VLAN_XLATE_2 KEY.", 2601 /* VNTAG_ETAG_ACTION_SET */ "PDD Output Bus generic format", 2602 /* VNTAG_ETAG_ASSIGN_ACTION_SET */ "PDD Output Bus generic format", 2603 /* VNTAG_HDR */ "4BYTES OF VNTAG HEADER AFTER ETHERTYPE.", 2604 /* VPLAG_CONTROLS_ACTION_SET */ "PDD Output Bus generic format", 2605 /* VSAN_ACTION_SET */ "PDD Output Bus generic format", 2606 /* VXLAN_HDR */ "VXLAN header specification", 2607 /* VXLT2_ASSIGNED_TAGS_L3_TYPE_DOP */ "VXLT2_ASSIGNED_TAGS_L3_TYPE_DOP DOP description.", 2608 /* VXLT_ACTION_SET */ "PDD Output Bus generic format", 2609 /* VXLT_CTRL_ID_SEL_ENCODING_FORMAT */ "EGR_PKT_FLOW_SELECT_TCAM_DATA_ONLY.ADAPTATION_*_VXLT_CTRL_ID_SEL_A/B encoding format.", 2610 /* VXLT_DROP_VECTOR */ "Bit Definitions of the VXLT drop vector.", 2611 /* WAMU_CNTX_TB */ "Position and description of bits in the WAMU Context Table and Table parameter", 2612 /* WAMU_PURGE */ "wamu context table purge fifo foramt", 2613 /* WAMU_S_RF */ "wamu context table memory s_rf width", 2614 /* WAMU_TO_TOQ_INFO */ "Position and description of bits in the WAMU to TOQ INFO bus", 2615 /* WESP_HDR */ "Wrapped ESP header specification", 2616 /* WRED_CELL_THD_0_FIELDS */ "Position and description of bits in WRED CELL Threshold Green & Yellow\nMemory", 2617 /* WRED_CELL_THD_1_FIELDS */ "Position and description of bits in WRED CELL Threshold Red & non-tcp\nMemory", 2618 /* WRED_CFG_CELL_FIELDS */ "Position and description of bits in WRED Average QSize and Config\nRegisters for Cell\nWhen do register read/write test to this register,\nplease DO reset\n MISCCONFIG.REFRESH_EN = 0\n MISCCONFIG.PARITY_GEN_EN = 0\n MISCCONFIG.PARITY_CHK_EN = 0\nThis is to prevent data being overwrite by internal refresh\nprocess.", 2619 /* WRED_CFG_PACKET_FIELDS */ "Position and description of bits in WRED Average QSize and Config\nRegisters for Packet\nWhen do register read/write test to this register,\nplease DO reset\n MISCCONFIG.REFRESH_EN = 0\n MISCCONFIG.PARITY_GEN_EN = 0\n MISCCONFIG.PARITY_CHK_EN = 0\nThis is to prevent data being overwrite by internal refresh\nprocess.", 2620 /* WRED_CFG_S_RF */ "WRED CFG memory s_rf width", 2621 /* WRED_PACKET_THD_0_FIELDS */ "Position and description of bits in WRED PACKET Threshold Green & Yellow\nMemory", 2622 /* WRED_PACKET_THD_1_FIELDS */ "Position and description of bits in WRED PACKET Threshold Red & non-tcp\nMemory", 2623 /* WRED_S_RF */ "wred memory s_rf width", 2624 /* WRED_THD_S_RF */ "WRED CFG memory s_rf width", 2625 /* WRED_TO_DEQ_STATUS_INFO */ "WRED to DEQ interface format", 2626 /* XGPORT_TO_EP_PORT_MODE_BUS */ "Bus from XGPORT to EP specifying the mode of operation of XGPORT", 2627 /* XGPORT_TO_IP_CONTROL_WORD */ "GPORT/XPORT to IP Control Word Format", 2628 /* XGPORT_TO_IP_CTRL_BUS */ "Position and description of bits in xgp_to_ip_pkt_ctrl", 2629 /* XPE_ENQ_TO_PQE_INFO */ "PQE format of ENQ to PQE info", 2630 /* XPORT_XQHDR_S_RF */ "XPORT XQ Header memory s_rf width", 2631 /* XPPORT_TO_IP_CONTROL_WORD */ "GPORT/XPORT to IP Control Word Format", 2632 /* XQFREE_S_RF */ "XQ free pointer memory s_rf width", 2633 /* XQNEXT_S_RF */ "XQ next pointer memory s_rf width", 2634 /* XQPORT_TO_EP_PORT_MODE_BUS */ "Bus from XQPORT to EP specifying the mode of operation of XQPORT", 2635 /* ZONE_ID_DOP_DOP */ "ZONE_ID_DOP_DOP DOP description.", 2636 /* ZONE_L2_TAGS_ACTIONS */ "Zone l2 tag modification actions format.", 2637 /* ZONE_L2_TAGS_BUS */ "Zone l2 tags.", 2638 /* ZONE_L2_TAGS_STATUS */ "Zone l2 tag presence format.", 2639 /* ZONE_L2_TAGS_VALUES */ "Zone l2 tags values bus.", 2640 /* ZONE_OBJECTS */ "Zone objects bus format.", 2641 /* ZONE_PRUNING_OBJECTS */ "Zone pruning objects bus format.",