allformats_d.i (491681B)
1 /* 2 * DO NOT EDIT THIS FILE! 3 * This file is auto-generated from the registers file. 4 * Edits to this file will be lost when it is regenerated. 5 * 6 * 7 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 8 * 9 * Copyright 2007-2020 Broadcom Inc. All rights reserved. 10 * 11 * File: allformats_d.i 12 * Purpose: Independent format descriptions. 13 */ 14 15 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 16 defined(BCM_56870_A0) 17 { /* SOC_FORMAT_INT_DELETE_TAG_ACTION_SETfmt */ 18 /* format DELETE_TAG_ACTION_SETfmt */ 19 /* nFields */ 3, 20 /* *fields */ soc_DELETE_TAG_ACTION_SETfmt_fields, 21 /* bits */ 3, 22 /* flags */ 0, 23 }, 24 #endif /* chips */ 25 26 #if defined(BCM_56725_A0) || defined(BCM_56820_A0) 27 { /* SOC_FORMAT_INT_DEQ0_TO_CCP_INFO_BUSfmt */ 28 /* format DEQ0_TO_CCP_INFO_BUSfmt */ 29 /* nFields */ 7, 30 /* *fields */ soc_DEQ0_TO_CCP_INFO_BUSfmt_fields, 31 /* bits */ 39, 32 /* flags */ 0, 33 }, 34 #endif /* chips */ 35 36 #if defined(BCM_88732_A0) 37 { /* SOC_FORMAT_INT_DEQ0_TO_CCP_INFO_BUS_BCM88732_A0fmt */ 38 /* format DEQ0_TO_CCP_INFO_BUSfmt */ 39 /* nFields */ 6, 40 /* *fields */ soc_DEQ0_TO_CCP_INFO_BUS_BCM88732_A0fmt_fields, 41 /* bits */ 40, 42 /* flags */ 0, 43 }, 44 #endif /* chips */ 45 46 #if defined(BCM_56725_A0) || defined(BCM_56820_A0) 47 { /* SOC_FORMAT_INT_DEQ0_TO_CTR_INFOfmt */ 48 /* format DEQ0_TO_CTR_INFOfmt */ 49 /* nFields */ 4, 50 /* *fields */ soc_DEQ0_TO_CTR_INFOfmt_fields, 51 /* bits */ 19, 52 /* flags */ 0, 53 }, 54 #endif /* chips */ 55 56 #if defined(BCM_88732_A0) 57 { /* SOC_FORMAT_INT_DEQ0_TO_CTR_INFO_BCM88732_A0fmt */ 58 /* format DEQ0_TO_CTR_INFOfmt */ 59 /* nFields */ 7, 60 /* *fields */ soc_DEQ0_TO_CTR_INFO_BCM88732_A0fmt_fields, 61 /* bits */ 23, 62 /* flags */ 0, 63 }, 64 #endif /* chips */ 65 66 #if defined(BCM_56820_A0) 67 { /* SOC_FORMAT_INT_DEQ1_TO_CCP_INFO_BUSfmt */ 68 /* format DEQ1_TO_CCP_INFO_BUSfmt */ 69 /* nFields */ 7, 70 /* *fields */ soc_DEQ_TO_CCP_INFO_BUSfmt_fields, 71 /* bits */ 38, 72 /* flags */ 0, 73 }, 74 #endif /* chips */ 75 76 #if defined(BCM_56725_A0) 77 { /* SOC_FORMAT_INT_DEQ1_TO_CCP_INFO_BUS_BCM56725_A0fmt */ 78 /* format DEQ1_TO_CCP_INFO_BUSfmt */ 79 /* nFields */ 7, 80 /* *fields */ soc_DEQ_TO_CCP_INFO_BUSfmt_fields, 81 /* bits */ 38, 82 /* flags */ 0, 83 }, 84 #endif /* chips */ 85 86 #if defined(BCM_56820_A0) 87 { /* SOC_FORMAT_INT_DEQ1_TO_CTR_INFOfmt */ 88 /* format DEQ1_TO_CTR_INFOfmt */ 89 /* nFields */ 4, 90 /* *fields */ soc_DEQ_TO_CTR_INFOfmt_fields, 91 /* bits */ 18, 92 /* flags */ 0, 93 }, 94 #endif /* chips */ 95 96 #if defined(BCM_56725_A0) 97 { /* SOC_FORMAT_INT_DEQ1_TO_CTR_INFO_BCM56725_A0fmt */ 98 /* format DEQ1_TO_CTR_INFOfmt */ 99 /* nFields */ 4, 100 /* *fields */ soc_DEQ_TO_CTR_INFOfmt_fields, 101 /* bits */ 18, 102 /* flags */ 0, 103 }, 104 #endif /* chips */ 105 106 #if defined(BCM_56820_A0) 107 { /* SOC_FORMAT_INT_DEQ_DEFfmt */ 108 /* format DEQ_DEFfmt */ 109 /* nFields */ 1, 110 /* *fields */ soc_ENQ_DEFfmt_fields, 111 /* bits */ 14, 112 /* flags */ 0, 113 }, 114 #endif /* chips */ 115 116 #if defined(BCM_56725_A0) 117 { /* SOC_FORMAT_INT_DEQ_DEF_BCM56725_A0fmt */ 118 /* format DEQ_DEFfmt */ 119 /* nFields */ 1, 120 /* *fields */ soc_ENQ_DEFfmt_fields, 121 /* bits */ 14, 122 /* flags */ 0, 123 }, 124 #endif /* chips */ 125 126 #if defined(BCM_88732_A0) 127 { /* SOC_FORMAT_INT_DEQ_DEF_BCM88732_A0fmt */ 128 /* format DEQ_DEFfmt */ 129 /* nFields */ 1, 130 /* *fields */ soc_ENQ_DEFfmt_fields, 131 /* bits */ 14, 132 /* flags */ 0, 133 }, 134 #endif /* chips */ 135 136 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \ 137 defined(BCM_56450_B1) 138 { /* SOC_FORMAT_INT_DEQ_NON_CCBE_CONTROL_INFOfmt */ 139 /* format DEQ_NON_CCBE_CONTROL_INFOfmt */ 140 /* nFields */ 25, 141 /* *fields */ soc_DEQ_NON_CCBE_CONTROL_INFOfmt_fields, 142 /* bits */ 87, 143 /* flags */ 0, 144 }, 145 #endif /* chips */ 146 147 #if defined(BCM_56260_A0) 148 { /* SOC_FORMAT_INT_DEQ_NON_CCBE_CONTROL_INFO_BCM56260_A0fmt */ 149 /* format DEQ_NON_CCBE_CONTROL_INFOfmt */ 150 /* nFields */ 25, 151 /* *fields */ soc_DEQ_NON_CCBE_CONTROL_INFO_BCM56260_A0fmt_fields, 152 /* bits */ 79, 153 /* flags */ 0, 154 }, 155 #endif /* chips */ 156 157 #if defined(BCM_56260_B0) 158 { /* SOC_FORMAT_INT_DEQ_NON_CCBE_CONTROL_INFO_BCM56260_B0fmt */ 159 /* format DEQ_NON_CCBE_CONTROL_INFOfmt */ 160 /* nFields */ 25, 161 /* *fields */ soc_DEQ_NON_CCBE_CONTROL_INFO_BCM56260_A0fmt_fields, 162 /* bits */ 79, 163 /* flags */ 0, 164 }, 165 #endif /* chips */ 166 167 #if defined(BCM_56270_A0) 168 { /* SOC_FORMAT_INT_DEQ_NON_CCBE_CONTROL_INFO_BCM56270_A0fmt */ 169 /* format DEQ_NON_CCBE_CONTROL_INFOfmt */ 170 /* nFields */ 20, 171 /* *fields */ soc_DEQ_NON_CCBE_CONTROL_INFO_BCM56270_A0fmt_fields, 172 /* bits */ 58, 173 /* flags */ 0, 174 }, 175 #endif /* chips */ 176 177 #if defined(BCM_56340_A0) || defined(BCM_56640_A0) 178 { /* SOC_FORMAT_INT_DEQ_RDTBL_TO_CDU_FT_INFOfmt */ 179 /* format DEQ_RDTBL_TO_CDU_FT_INFOfmt */ 180 /* nFields */ 4, 181 /* *fields */ soc_DEQ_RDTBL_TO_CDU_FT_INFOfmt_fields, 182 /* bits */ 7, 183 /* flags */ 0, 184 }, 185 #endif /* chips */ 186 187 #if defined(BCM_56440_A0) 188 { /* SOC_FORMAT_INT_DEQ_TO_CCPE_INFOfmt */ 189 /* format DEQ_TO_CCPE_INFOfmt */ 190 /* nFields */ 15, 191 /* *fields */ soc_DEQ_TO_CCPE_INFOfmt_fields, 192 /* bits */ 72, 193 /* flags */ 0, 194 }, 195 #endif /* chips */ 196 197 #if defined(BCM_56260_A0) 198 { /* SOC_FORMAT_INT_DEQ_TO_CCPE_INFO_BCM56260_A0fmt */ 199 /* format DEQ_TO_CCPE_INFOfmt */ 200 /* nFields */ 15, 201 /* *fields */ soc_DEQ_TO_CCPE_INFO_BCM56260_A0fmt_fields, 202 /* bits */ 72, 203 /* flags */ 0, 204 }, 205 #endif /* chips */ 206 207 #if defined(BCM_56260_B0) 208 { /* SOC_FORMAT_INT_DEQ_TO_CCPE_INFO_BCM56260_B0fmt */ 209 /* format DEQ_TO_CCPE_INFOfmt */ 210 /* nFields */ 15, 211 /* *fields */ soc_DEQ_TO_CCPE_INFO_BCM56260_A0fmt_fields, 212 /* bits */ 72, 213 /* flags */ 0, 214 }, 215 #endif /* chips */ 216 217 #if defined(BCM_56270_A0) 218 { /* SOC_FORMAT_INT_DEQ_TO_CCPE_INFO_BCM56270_A0fmt */ 219 /* format DEQ_TO_CCPE_INFOfmt */ 220 /* nFields */ 15, 221 /* *fields */ soc_DEQ_TO_CCPE_INFO_BCM56260_A0fmt_fields, 222 /* bits */ 72, 223 /* flags */ 0, 224 }, 225 #endif /* chips */ 226 227 #if defined(BCM_56440_B0) 228 { /* SOC_FORMAT_INT_DEQ_TO_CCPE_INFO_BCM56440_B0fmt */ 229 /* format DEQ_TO_CCPE_INFOfmt */ 230 /* nFields */ 15, 231 /* *fields */ soc_DEQ_TO_CCPE_INFOfmt_fields, 232 /* bits */ 72, 233 /* flags */ 0, 234 }, 235 #endif /* chips */ 236 237 #if defined(BCM_56450_A0) 238 { /* SOC_FORMAT_INT_DEQ_TO_CCPE_INFO_BCM56450_A0fmt */ 239 /* format DEQ_TO_CCPE_INFOfmt */ 240 /* nFields */ 15, 241 /* *fields */ soc_DEQ_TO_CCPE_INFO_BCM56450_A0fmt_fields, 242 /* bits */ 72, 243 /* flags */ 0, 244 }, 245 #endif /* chips */ 246 247 #if defined(BCM_56450_B0) 248 { /* SOC_FORMAT_INT_DEQ_TO_CCPE_INFO_BCM56450_B0fmt */ 249 /* format DEQ_TO_CCPE_INFOfmt */ 250 /* nFields */ 15, 251 /* *fields */ soc_DEQ_TO_CCPE_INFO_BCM56450_A0fmt_fields, 252 /* bits */ 72, 253 /* flags */ 0, 254 }, 255 #endif /* chips */ 256 257 #if defined(BCM_56450_B1) 258 { /* SOC_FORMAT_INT_DEQ_TO_CCPE_INFO_BCM56450_B1fmt */ 259 /* format DEQ_TO_CCPE_INFOfmt */ 260 /* nFields */ 15, 261 /* *fields */ soc_DEQ_TO_CCPE_INFO_BCM56450_A0fmt_fields, 262 /* bits */ 72, 263 /* flags */ 0, 264 }, 265 #endif /* chips */ 266 267 #if defined(BCM_56440_A0) 268 { /* SOC_FORMAT_INT_DEQ_TO_CCPI_INFOfmt */ 269 /* format DEQ_TO_CCPI_INFOfmt */ 270 /* nFields */ 15, 271 /* *fields */ soc_DEQ_TO_CCPI_INFOfmt_fields, 272 /* bits */ 68, 273 /* flags */ 0, 274 }, 275 #endif /* chips */ 276 277 #if defined(BCM_56260_A0) 278 { /* SOC_FORMAT_INT_DEQ_TO_CCPI_INFO_BCM56260_A0fmt */ 279 /* format DEQ_TO_CCPI_INFOfmt */ 280 /* nFields */ 15, 281 /* *fields */ soc_DEQ_TO_CCPI_INFO_BCM56260_A0fmt_fields, 282 /* bits */ 68, 283 /* flags */ 0, 284 }, 285 #endif /* chips */ 286 287 #if defined(BCM_56260_B0) 288 { /* SOC_FORMAT_INT_DEQ_TO_CCPI_INFO_BCM56260_B0fmt */ 289 /* format DEQ_TO_CCPI_INFOfmt */ 290 /* nFields */ 15, 291 /* *fields */ soc_DEQ_TO_CCPI_INFO_BCM56260_A0fmt_fields, 292 /* bits */ 68, 293 /* flags */ 0, 294 }, 295 #endif /* chips */ 296 297 #if defined(BCM_56270_A0) 298 { /* SOC_FORMAT_INT_DEQ_TO_CCPI_INFO_BCM56270_A0fmt */ 299 /* format DEQ_TO_CCPI_INFOfmt */ 300 /* nFields */ 15, 301 /* *fields */ soc_DEQ_TO_CCPI_INFO_BCM56260_A0fmt_fields, 302 /* bits */ 68, 303 /* flags */ 0, 304 }, 305 #endif /* chips */ 306 307 #if defined(BCM_56440_B0) 308 { /* SOC_FORMAT_INT_DEQ_TO_CCPI_INFO_BCM56440_B0fmt */ 309 /* format DEQ_TO_CCPI_INFOfmt */ 310 /* nFields */ 15, 311 /* *fields */ soc_DEQ_TO_CCPI_INFOfmt_fields, 312 /* bits */ 68, 313 /* flags */ 0, 314 }, 315 #endif /* chips */ 316 317 #if defined(BCM_56450_A0) 318 { /* SOC_FORMAT_INT_DEQ_TO_CCPI_INFO_BCM56450_A0fmt */ 319 /* format DEQ_TO_CCPI_INFOfmt */ 320 /* nFields */ 15, 321 /* *fields */ soc_DEQ_TO_CCPI_INFO_BCM56450_A0fmt_fields, 322 /* bits */ 68, 323 /* flags */ 0, 324 }, 325 #endif /* chips */ 326 327 #if defined(BCM_56450_B0) 328 { /* SOC_FORMAT_INT_DEQ_TO_CCPI_INFO_BCM56450_B0fmt */ 329 /* format DEQ_TO_CCPI_INFOfmt */ 330 /* nFields */ 15, 331 /* *fields */ soc_DEQ_TO_CCPI_INFO_BCM56450_A0fmt_fields, 332 /* bits */ 68, 333 /* flags */ 0, 334 }, 335 #endif /* chips */ 336 337 #if defined(BCM_56450_B1) 338 { /* SOC_FORMAT_INT_DEQ_TO_CCPI_INFO_BCM56450_B1fmt */ 339 /* format DEQ_TO_CCPI_INFOfmt */ 340 /* nFields */ 15, 341 /* *fields */ soc_DEQ_TO_CCPI_INFO_BCM56450_A0fmt_fields, 342 /* bits */ 68, 343 /* flags */ 0, 344 }, 345 #endif /* chips */ 346 347 #if defined(BCM_56800_A0) 348 { /* SOC_FORMAT_INT_DEQ_TO_CCP_INFO_BUSfmt */ 349 /* format DEQ_TO_CCP_INFO_BUSfmt */ 350 /* nFields */ 7, 351 /* *fields */ soc_DEQ_TO_CCP_INFO_BUSfmt_fields, 352 /* bits */ 38, 353 /* flags */ 0, 354 }, 355 #endif /* chips */ 356 357 #if defined(BCM_56334_A0) 358 { /* SOC_FORMAT_INT_DEQ_TO_CCP_INFO_BUS_BCM56334_A0fmt */ 359 /* format DEQ_TO_CCP_INFO_BUSfmt */ 360 /* nFields */ 15, 361 /* *fields */ soc_DEQ_TO_CCP_INFO_BUS_BCM56334_A0fmt_fields, 362 /* bits */ 75, 363 /* flags */ 0, 364 }, 365 #endif /* chips */ 366 367 #if defined(BCM_56334_B0) 368 { /* SOC_FORMAT_INT_DEQ_TO_CCP_INFO_BUS_BCM56334_B0fmt */ 369 /* format DEQ_TO_CCP_INFO_BUSfmt */ 370 /* nFields */ 15, 371 /* *fields */ soc_DEQ_TO_CCP_INFO_BUS_BCM56334_A0fmt_fields, 372 /* bits */ 75, 373 /* flags */ 0, 374 }, 375 #endif /* chips */ 376 377 #if defined(BCM_56524_A0) 378 { /* SOC_FORMAT_INT_DEQ_TO_CCP_INFO_BUS_BCM56524_A0fmt */ 379 /* format DEQ_TO_CCP_INFO_BUSfmt */ 380 /* nFields */ 18, 381 /* *fields */ soc_DEQ_TO_CCP_INFO_BUS_BCM56634_A0fmt_fields, 382 /* bits */ 82, 383 /* flags */ 0, 384 }, 385 #endif /* chips */ 386 387 #if defined(BCM_56524_B0) 388 { /* SOC_FORMAT_INT_DEQ_TO_CCP_INFO_BUS_BCM56524_B0fmt */ 389 /* format DEQ_TO_CCP_INFO_BUSfmt */ 390 /* nFields */ 18, 391 /* *fields */ soc_DEQ_TO_CCP_INFO_BUS_BCM56634_A0fmt_fields, 392 /* bits */ 82, 393 /* flags */ 0, 394 }, 395 #endif /* chips */ 396 397 #if defined(BCM_56560_A0) 398 { /* SOC_FORMAT_INT_DEQ_TO_CCP_INFO_BUS_BCM56560_A0fmt */ 399 /* format DEQ_TO_CCP_INFO_BUSfmt */ 400 /* nFields */ 22, 401 /* *fields */ soc_DEQ_TO_CCP_INFO_BUS_BCM56560_A0fmt_fields, 402 /* bits */ 79, 403 /* flags */ 0, 404 }, 405 #endif /* chips */ 406 407 #if defined(BCM_56560_B0) 408 { /* SOC_FORMAT_INT_DEQ_TO_CCP_INFO_BUS_BCM56560_B0fmt */ 409 /* format DEQ_TO_CCP_INFO_BUSfmt */ 410 /* nFields */ 22, 411 /* *fields */ soc_DEQ_TO_CCP_INFO_BUS_BCM56560_A0fmt_fields, 412 /* bits */ 79, 413 /* flags */ 0, 414 }, 415 #endif /* chips */ 416 417 #if defined(BCM_56624_A0) 418 { /* SOC_FORMAT_INT_DEQ_TO_CCP_INFO_BUS_BCM56624_A0fmt */ 419 /* format DEQ_TO_CCP_INFO_BUSfmt */ 420 /* nFields */ 15, 421 /* *fields */ soc_DEQ_TO_CCP_INFO_BUS_BCM56624_A0fmt_fields, 422 /* bits */ 77, 423 /* flags */ 0, 424 }, 425 #endif /* chips */ 426 427 #if defined(BCM_56624_B0) 428 { /* SOC_FORMAT_INT_DEQ_TO_CCP_INFO_BUS_BCM56624_B0fmt */ 429 /* format DEQ_TO_CCP_INFO_BUSfmt */ 430 /* nFields */ 15, 431 /* *fields */ soc_DEQ_TO_CCP_INFO_BUS_BCM56624_A0fmt_fields, 432 /* bits */ 77, 433 /* flags */ 0, 434 }, 435 #endif /* chips */ 436 437 #if defined(BCM_56634_A0) 438 { /* SOC_FORMAT_INT_DEQ_TO_CCP_INFO_BUS_BCM56634_A0fmt */ 439 /* format DEQ_TO_CCP_INFO_BUSfmt */ 440 /* nFields */ 18, 441 /* *fields */ soc_DEQ_TO_CCP_INFO_BUS_BCM56634_A0fmt_fields, 442 /* bits */ 82, 443 /* flags */ 0, 444 }, 445 #endif /* chips */ 446 447 #if defined(BCM_56634_B0) 448 { /* SOC_FORMAT_INT_DEQ_TO_CCP_INFO_BUS_BCM56634_B0fmt */ 449 /* format DEQ_TO_CCP_INFO_BUSfmt */ 450 /* nFields */ 18, 451 /* *fields */ soc_DEQ_TO_CCP_INFO_BUS_BCM56634_A0fmt_fields, 452 /* bits */ 82, 453 /* flags */ 0, 454 }, 455 #endif /* chips */ 456 457 #if defined(BCM_56670_A0) 458 { /* SOC_FORMAT_INT_DEQ_TO_CCP_INFO_BUS_BCM56670_A0fmt */ 459 /* format DEQ_TO_CCP_INFO_BUSfmt */ 460 /* nFields */ 23, 461 /* *fields */ soc_DEQ_TO_CCP_INFO_BUS_BCM56670_A0fmt_fields, 462 /* bits */ 75, 463 /* flags */ 0, 464 }, 465 #endif /* chips */ 466 467 #if defined(BCM_56670_B0) 468 { /* SOC_FORMAT_INT_DEQ_TO_CCP_INFO_BUS_BCM56670_B0fmt */ 469 /* format DEQ_TO_CCP_INFO_BUSfmt */ 470 /* nFields */ 23, 471 /* *fields */ soc_DEQ_TO_CCP_INFO_BUS_BCM56670_A0fmt_fields, 472 /* bits */ 75, 473 /* flags */ 0, 474 }, 475 #endif /* chips */ 476 477 #if defined(BCM_56680_A0) 478 { /* SOC_FORMAT_INT_DEQ_TO_CCP_INFO_BUS_BCM56680_A0fmt */ 479 /* format DEQ_TO_CCP_INFO_BUSfmt */ 480 /* nFields */ 15, 481 /* *fields */ soc_DEQ_TO_CCP_INFO_BUS_BCM56624_A0fmt_fields, 482 /* bits */ 77, 483 /* flags */ 0, 484 }, 485 #endif /* chips */ 486 487 #if defined(BCM_56680_B0) 488 { /* SOC_FORMAT_INT_DEQ_TO_CCP_INFO_BUS_BCM56680_B0fmt */ 489 /* format DEQ_TO_CCP_INFO_BUSfmt */ 490 /* nFields */ 15, 491 /* *fields */ soc_DEQ_TO_CCP_INFO_BUS_BCM56624_A0fmt_fields, 492 /* bits */ 77, 493 /* flags */ 0, 494 }, 495 #endif /* chips */ 496 497 #if defined(BCM_56685_A0) 498 { /* SOC_FORMAT_INT_DEQ_TO_CCP_INFO_BUS_BCM56685_A0fmt */ 499 /* format DEQ_TO_CCP_INFO_BUSfmt */ 500 /* nFields */ 18, 501 /* *fields */ soc_DEQ_TO_CCP_INFO_BUS_BCM56634_A0fmt_fields, 502 /* bits */ 82, 503 /* flags */ 0, 504 }, 505 #endif /* chips */ 506 507 #if defined(BCM_56685_B0) 508 { /* SOC_FORMAT_INT_DEQ_TO_CCP_INFO_BUS_BCM56685_B0fmt */ 509 /* format DEQ_TO_CCP_INFO_BUSfmt */ 510 /* nFields */ 18, 511 /* *fields */ soc_DEQ_TO_CCP_INFO_BUS_BCM56634_A0fmt_fields, 512 /* bits */ 82, 513 /* flags */ 0, 514 }, 515 #endif /* chips */ 516 517 #if defined(BCM_56840_A0) 518 { /* SOC_FORMAT_INT_DEQ_TO_CCP_INFO_BUS_BCM56840_A0fmt */ 519 /* format DEQ_TO_CCP_INFO_BUSfmt */ 520 /* nFields */ 12, 521 /* *fields */ soc_DEQ_TO_CCP_INFO_BUS_BCM56840_A0fmt_fields, 522 /* bits */ 61, 523 /* flags */ 0, 524 }, 525 #endif /* chips */ 526 527 #if defined(BCM_56840_B0) 528 { /* SOC_FORMAT_INT_DEQ_TO_CCP_INFO_BUS_BCM56840_B0fmt */ 529 /* format DEQ_TO_CCP_INFO_BUSfmt */ 530 /* nFields */ 12, 531 /* *fields */ soc_DEQ_TO_CCP_INFO_BUS_BCM56840_A0fmt_fields, 532 /* bits */ 61, 533 /* flags */ 0, 534 }, 535 #endif /* chips */ 536 537 #if defined(BCM_56850_A0) 538 { /* SOC_FORMAT_INT_DEQ_TO_CCP_INFO_BUS_BCM56850_A0fmt */ 539 /* format DEQ_TO_CCP_INFO_BUSfmt */ 540 /* nFields */ 22, 541 /* *fields */ soc_DEQ_TO_CCP_INFO_BUS_BCM56850_A0fmt_fields, 542 /* bits */ 77, 543 /* flags */ 0, 544 }, 545 #endif /* chips */ 546 547 #if defined(BCM_56860_A0) 548 { /* SOC_FORMAT_INT_DEQ_TO_CCP_INFO_BUS_BCM56860_A0fmt */ 549 /* format DEQ_TO_CCP_INFO_BUSfmt */ 550 /* nFields */ 22, 551 /* *fields */ soc_DEQ_TO_CCP_INFO_BUS_BCM56850_A0fmt_fields, 552 /* bits */ 77, 553 /* flags */ 0, 554 }, 555 #endif /* chips */ 556 557 #if defined(BCM_56440_A0) 558 { /* SOC_FORMAT_INT_DEQ_TO_CTR_DEQ_INFOfmt */ 559 /* format DEQ_TO_CTR_DEQ_INFOfmt */ 560 /* nFields */ 4, 561 /* *fields */ soc_DEQ_TO_CTR_DEQ_INFOfmt_fields, 562 /* bits */ 34, 563 /* flags */ 0, 564 }, 565 #endif /* chips */ 566 567 #if defined(BCM_56260_A0) 568 { /* SOC_FORMAT_INT_DEQ_TO_CTR_DEQ_INFO_BCM56260_A0fmt */ 569 /* format DEQ_TO_CTR_DEQ_INFOfmt */ 570 /* nFields */ 4, 571 /* *fields */ soc_DEQ_TO_CTR_DEQ_INFO_BCM56260_A0fmt_fields, 572 /* bits */ 33, 573 /* flags */ 0, 574 }, 575 #endif /* chips */ 576 577 #if defined(BCM_56260_B0) 578 { /* SOC_FORMAT_INT_DEQ_TO_CTR_DEQ_INFO_BCM56260_B0fmt */ 579 /* format DEQ_TO_CTR_DEQ_INFOfmt */ 580 /* nFields */ 4, 581 /* *fields */ soc_DEQ_TO_CTR_DEQ_INFO_BCM56260_A0fmt_fields, 582 /* bits */ 33, 583 /* flags */ 0, 584 }, 585 #endif /* chips */ 586 587 #if defined(BCM_56270_A0) 588 { /* SOC_FORMAT_INT_DEQ_TO_CTR_DEQ_INFO_BCM56270_A0fmt */ 589 /* format DEQ_TO_CTR_DEQ_INFOfmt */ 590 /* nFields */ 4, 591 /* *fields */ soc_DEQ_TO_CTR_DEQ_INFO_BCM56270_A0fmt_fields, 592 /* bits */ 32, 593 /* flags */ 0, 594 }, 595 #endif /* chips */ 596 597 #if defined(BCM_56440_B0) 598 { /* SOC_FORMAT_INT_DEQ_TO_CTR_DEQ_INFO_BCM56440_B0fmt */ 599 /* format DEQ_TO_CTR_DEQ_INFOfmt */ 600 /* nFields */ 4, 601 /* *fields */ soc_DEQ_TO_CTR_DEQ_INFOfmt_fields, 602 /* bits */ 34, 603 /* flags */ 0, 604 }, 605 #endif /* chips */ 606 607 #if defined(BCM_56450_A0) 608 { /* SOC_FORMAT_INT_DEQ_TO_CTR_DEQ_INFO_BCM56450_A0fmt */ 609 /* format DEQ_TO_CTR_DEQ_INFOfmt */ 610 /* nFields */ 4, 611 /* *fields */ soc_DEQ_TO_CTR_DEQ_INFO_BCM56450_A0fmt_fields, 612 /* bits */ 37, 613 /* flags */ 0, 614 }, 615 #endif /* chips */ 616 617 #if defined(BCM_56450_B0) 618 { /* SOC_FORMAT_INT_DEQ_TO_CTR_DEQ_INFO_BCM56450_B0fmt */ 619 /* format DEQ_TO_CTR_DEQ_INFOfmt */ 620 /* nFields */ 4, 621 /* *fields */ soc_DEQ_TO_CTR_DEQ_INFO_BCM56450_A0fmt_fields, 622 /* bits */ 37, 623 /* flags */ 0, 624 }, 625 #endif /* chips */ 626 627 #if defined(BCM_56450_B1) 628 { /* SOC_FORMAT_INT_DEQ_TO_CTR_DEQ_INFO_BCM56450_B1fmt */ 629 /* format DEQ_TO_CTR_DEQ_INFOfmt */ 630 /* nFields */ 4, 631 /* *fields */ soc_DEQ_TO_CTR_DEQ_INFO_BCM56450_A0fmt_fields, 632 /* bits */ 37, 633 /* flags */ 0, 634 }, 635 #endif /* chips */ 636 637 #if defined(BCM_56800_A0) 638 { /* SOC_FORMAT_INT_DEQ_TO_CTR_INFOfmt */ 639 /* format DEQ_TO_CTR_INFOfmt */ 640 /* nFields */ 4, 641 /* *fields */ soc_DEQ_TO_CTR_INFOfmt_fields, 642 /* bits */ 18, 643 /* flags */ 0, 644 }, 645 #endif /* chips */ 646 647 #if defined(BCM_56334_A0) 648 { /* SOC_FORMAT_INT_DEQ_TO_CTR_INFO_BCM56334_A0fmt */ 649 /* format DEQ_TO_CTR_INFOfmt */ 650 /* nFields */ 4, 651 /* *fields */ soc_DEQ_TO_CTR_INFO_BCM56624_A0fmt_fields, 652 /* bits */ 22, 653 /* flags */ 0, 654 }, 655 #endif /* chips */ 656 657 #if defined(BCM_56334_B0) 658 { /* SOC_FORMAT_INT_DEQ_TO_CTR_INFO_BCM56334_B0fmt */ 659 /* format DEQ_TO_CTR_INFOfmt */ 660 /* nFields */ 4, 661 /* *fields */ soc_DEQ_TO_CTR_INFO_BCM56624_A0fmt_fields, 662 /* bits */ 22, 663 /* flags */ 0, 664 }, 665 #endif /* chips */ 666 667 #if defined(BCM_56340_A0) 668 { /* SOC_FORMAT_INT_DEQ_TO_CTR_INFO_BCM56340_A0fmt */ 669 /* format DEQ_TO_CTR_INFOfmt */ 670 /* nFields */ 6, 671 /* *fields */ soc_DEQ_TO_CTR_INFO_BCM56640_A0fmt_fields, 672 /* bits */ 28, 673 /* flags */ 0, 674 }, 675 #endif /* chips */ 676 677 #if defined(BCM_56440_A0) 678 { /* SOC_FORMAT_INT_DEQ_TO_CTR_INFO_BCM56440_A0fmt */ 679 /* format DEQ_TO_CTR_INFOfmt */ 680 /* nFields */ 6, 681 /* *fields */ soc_DEQ_TO_CTR_INFO_BCM56840_A0fmt_fields, 682 /* bits */ 27, 683 /* flags */ 0, 684 }, 685 #endif /* chips */ 686 687 #if defined(BCM_56440_B0) 688 { /* SOC_FORMAT_INT_DEQ_TO_CTR_INFO_BCM56440_B0fmt */ 689 /* format DEQ_TO_CTR_INFOfmt */ 690 /* nFields */ 6, 691 /* *fields */ soc_DEQ_TO_CTR_INFO_BCM56840_A0fmt_fields, 692 /* bits */ 27, 693 /* flags */ 0, 694 }, 695 #endif /* chips */ 696 697 #if defined(BCM_56450_A0) 698 { /* SOC_FORMAT_INT_DEQ_TO_CTR_INFO_BCM56450_A0fmt */ 699 /* format DEQ_TO_CTR_INFOfmt */ 700 /* nFields */ 6, 701 /* *fields */ soc_DEQ_TO_CTR_INFO_BCM56450_A0fmt_fields, 702 /* bits */ 27, 703 /* flags */ 0, 704 }, 705 #endif /* chips */ 706 707 #if defined(BCM_56450_B0) 708 { /* SOC_FORMAT_INT_DEQ_TO_CTR_INFO_BCM56450_B0fmt */ 709 /* format DEQ_TO_CTR_INFOfmt */ 710 /* nFields */ 6, 711 /* *fields */ soc_DEQ_TO_CTR_INFO_BCM56450_A0fmt_fields, 712 /* bits */ 27, 713 /* flags */ 0, 714 }, 715 #endif /* chips */ 716 717 #if defined(BCM_56450_B1) 718 { /* SOC_FORMAT_INT_DEQ_TO_CTR_INFO_BCM56450_B1fmt */ 719 /* format DEQ_TO_CTR_INFOfmt */ 720 /* nFields */ 6, 721 /* *fields */ soc_DEQ_TO_CTR_INFO_BCM56450_A0fmt_fields, 722 /* bits */ 27, 723 /* flags */ 0, 724 }, 725 #endif /* chips */ 726 727 #if defined(BCM_56524_A0) 728 { /* SOC_FORMAT_INT_DEQ_TO_CTR_INFO_BCM56524_A0fmt */ 729 /* format DEQ_TO_CTR_INFOfmt */ 730 /* nFields */ 4, 731 /* *fields */ soc_DEQ_TO_CTR_INFO_BCM56624_A0fmt_fields, 732 /* bits */ 22, 733 /* flags */ 0, 734 }, 735 #endif /* chips */ 736 737 #if defined(BCM_56524_B0) 738 { /* SOC_FORMAT_INT_DEQ_TO_CTR_INFO_BCM56524_B0fmt */ 739 /* format DEQ_TO_CTR_INFOfmt */ 740 /* nFields */ 4, 741 /* *fields */ soc_DEQ_TO_CTR_INFO_BCM56624_A0fmt_fields, 742 /* bits */ 22, 743 /* flags */ 0, 744 }, 745 #endif /* chips */ 746 747 #if defined(BCM_56560_A0) 748 { /* SOC_FORMAT_INT_DEQ_TO_CTR_INFO_BCM56560_A0fmt */ 749 /* format DEQ_TO_CTR_INFOfmt */ 750 /* nFields */ 6, 751 /* *fields */ soc_DEQ_TO_CTR_INFO_BCM56560_A0fmt_fields, 752 /* bits */ 34, 753 /* flags */ 0, 754 }, 755 #endif /* chips */ 756 757 #if defined(BCM_56560_B0) 758 { /* SOC_FORMAT_INT_DEQ_TO_CTR_INFO_BCM56560_B0fmt */ 759 /* format DEQ_TO_CTR_INFOfmt */ 760 /* nFields */ 6, 761 /* *fields */ soc_DEQ_TO_CTR_INFO_BCM56560_A0fmt_fields, 762 /* bits */ 34, 763 /* flags */ 0, 764 }, 765 #endif /* chips */ 766 767 #if defined(BCM_56624_A0) 768 { /* SOC_FORMAT_INT_DEQ_TO_CTR_INFO_BCM56624_A0fmt */ 769 /* format DEQ_TO_CTR_INFOfmt */ 770 /* nFields */ 4, 771 /* *fields */ soc_DEQ_TO_CTR_INFO_BCM56624_A0fmt_fields, 772 /* bits */ 22, 773 /* flags */ 0, 774 }, 775 #endif /* chips */ 776 777 #if defined(BCM_56624_B0) 778 { /* SOC_FORMAT_INT_DEQ_TO_CTR_INFO_BCM56624_B0fmt */ 779 /* format DEQ_TO_CTR_INFOfmt */ 780 /* nFields */ 4, 781 /* *fields */ soc_DEQ_TO_CTR_INFO_BCM56624_A0fmt_fields, 782 /* bits */ 22, 783 /* flags */ 0, 784 }, 785 #endif /* chips */ 786 787 #if defined(BCM_56634_A0) 788 { /* SOC_FORMAT_INT_DEQ_TO_CTR_INFO_BCM56634_A0fmt */ 789 /* format DEQ_TO_CTR_INFOfmt */ 790 /* nFields */ 4, 791 /* *fields */ soc_DEQ_TO_CTR_INFO_BCM56624_A0fmt_fields, 792 /* bits */ 22, 793 /* flags */ 0, 794 }, 795 #endif /* chips */ 796 797 #if defined(BCM_56634_B0) 798 { /* SOC_FORMAT_INT_DEQ_TO_CTR_INFO_BCM56634_B0fmt */ 799 /* format DEQ_TO_CTR_INFOfmt */ 800 /* nFields */ 4, 801 /* *fields */ soc_DEQ_TO_CTR_INFO_BCM56624_A0fmt_fields, 802 /* bits */ 22, 803 /* flags */ 0, 804 }, 805 #endif /* chips */ 806 807 #if defined(BCM_56640_A0) 808 { /* SOC_FORMAT_INT_DEQ_TO_CTR_INFO_BCM56640_A0fmt */ 809 /* format DEQ_TO_CTR_INFOfmt */ 810 /* nFields */ 6, 811 /* *fields */ soc_DEQ_TO_CTR_INFO_BCM56640_A0fmt_fields, 812 /* bits */ 28, 813 /* flags */ 0, 814 }, 815 #endif /* chips */ 816 817 #if defined(BCM_56670_A0) 818 { /* SOC_FORMAT_INT_DEQ_TO_CTR_INFO_BCM56670_A0fmt */ 819 /* format DEQ_TO_CTR_INFOfmt */ 820 /* nFields */ 7, 821 /* *fields */ soc_DEQ_TO_CTR_INFO_BCM56670_A0fmt_fields, 822 /* bits */ 31, 823 /* flags */ 0, 824 }, 825 #endif /* chips */ 826 827 #if defined(BCM_56670_B0) 828 { /* SOC_FORMAT_INT_DEQ_TO_CTR_INFO_BCM56670_B0fmt */ 829 /* format DEQ_TO_CTR_INFOfmt */ 830 /* nFields */ 7, 831 /* *fields */ soc_DEQ_TO_CTR_INFO_BCM56670_A0fmt_fields, 832 /* bits */ 31, 833 /* flags */ 0, 834 }, 835 #endif /* chips */ 836 837 #if defined(BCM_56680_A0) 838 { /* SOC_FORMAT_INT_DEQ_TO_CTR_INFO_BCM56680_A0fmt */ 839 /* format DEQ_TO_CTR_INFOfmt */ 840 /* nFields */ 4, 841 /* *fields */ soc_DEQ_TO_CTR_INFO_BCM56624_A0fmt_fields, 842 /* bits */ 22, 843 /* flags */ 0, 844 }, 845 #endif /* chips */ 846 847 #if defined(BCM_56680_B0) 848 { /* SOC_FORMAT_INT_DEQ_TO_CTR_INFO_BCM56680_B0fmt */ 849 /* format DEQ_TO_CTR_INFOfmt */ 850 /* nFields */ 4, 851 /* *fields */ soc_DEQ_TO_CTR_INFO_BCM56624_A0fmt_fields, 852 /* bits */ 22, 853 /* flags */ 0, 854 }, 855 #endif /* chips */ 856 857 #if defined(BCM_56685_A0) 858 { /* SOC_FORMAT_INT_DEQ_TO_CTR_INFO_BCM56685_A0fmt */ 859 /* format DEQ_TO_CTR_INFOfmt */ 860 /* nFields */ 4, 861 /* *fields */ soc_DEQ_TO_CTR_INFO_BCM56624_A0fmt_fields, 862 /* bits */ 22, 863 /* flags */ 0, 864 }, 865 #endif /* chips */ 866 867 #if defined(BCM_56685_B0) 868 { /* SOC_FORMAT_INT_DEQ_TO_CTR_INFO_BCM56685_B0fmt */ 869 /* format DEQ_TO_CTR_INFOfmt */ 870 /* nFields */ 4, 871 /* *fields */ soc_DEQ_TO_CTR_INFO_BCM56624_A0fmt_fields, 872 /* bits */ 22, 873 /* flags */ 0, 874 }, 875 #endif /* chips */ 876 877 #if defined(BCM_56840_A0) 878 { /* SOC_FORMAT_INT_DEQ_TO_CTR_INFO_BCM56840_A0fmt */ 879 /* format DEQ_TO_CTR_INFOfmt */ 880 /* nFields */ 6, 881 /* *fields */ soc_DEQ_TO_CTR_INFO_BCM56840_A0fmt_fields, 882 /* bits */ 27, 883 /* flags */ 0, 884 }, 885 #endif /* chips */ 886 887 #if defined(BCM_56840_B0) 888 { /* SOC_FORMAT_INT_DEQ_TO_CTR_INFO_BCM56840_B0fmt */ 889 /* format DEQ_TO_CTR_INFOfmt */ 890 /* nFields */ 6, 891 /* *fields */ soc_DEQ_TO_CTR_INFO_BCM56840_A0fmt_fields, 892 /* bits */ 27, 893 /* flags */ 0, 894 }, 895 #endif /* chips */ 896 897 #if defined(BCM_56850_A0) 898 { /* SOC_FORMAT_INT_DEQ_TO_CTR_INFO_BCM56850_A0fmt */ 899 /* format DEQ_TO_CTR_INFOfmt */ 900 /* nFields */ 6, 901 /* *fields */ soc_DEQ_TO_CTR_INFO_BCM56850_A0fmt_fields, 902 /* bits */ 31, 903 /* flags */ 0, 904 }, 905 #endif /* chips */ 906 907 #if defined(BCM_56860_A0) 908 { /* SOC_FORMAT_INT_DEQ_TO_CTR_INFO_BCM56860_A0fmt */ 909 /* format DEQ_TO_CTR_INFOfmt */ 910 /* nFields */ 6, 911 /* *fields */ soc_DEQ_TO_CTR_INFO_BCM56850_A0fmt_fields, 912 /* bits */ 31, 913 /* flags */ 0, 914 }, 915 #endif /* chips */ 916 917 #if defined(BCM_56440_A0) 918 { /* SOC_FORMAT_INT_DEQ_TO_EMC_RD_REQ_INFOfmt */ 919 /* format DEQ_TO_EMC_RD_REQ_INFOfmt */ 920 /* nFields */ 6, 921 /* *fields */ soc_DEQ_TO_EMC_RD_REQ_INFOfmt_fields, 922 /* bits */ 31, 923 /* flags */ 0, 924 }, 925 #endif /* chips */ 926 927 #if defined(BCM_56260_A0) 928 { /* SOC_FORMAT_INT_DEQ_TO_EMC_RD_REQ_INFO_BCM56260_A0fmt */ 929 /* format DEQ_TO_EMC_RD_REQ_INFOfmt */ 930 /* nFields */ 6, 931 /* *fields */ soc_DEQ_TO_EMC_RD_REQ_INFO_BCM56260_A0fmt_fields, 932 /* bits */ 29, 933 /* flags */ 0, 934 }, 935 #endif /* chips */ 936 937 #if defined(BCM_56260_B0) 938 { /* SOC_FORMAT_INT_DEQ_TO_EMC_RD_REQ_INFO_BCM56260_B0fmt */ 939 /* format DEQ_TO_EMC_RD_REQ_INFOfmt */ 940 /* nFields */ 6, 941 /* *fields */ soc_DEQ_TO_EMC_RD_REQ_INFO_BCM56260_A0fmt_fields, 942 /* bits */ 29, 943 /* flags */ 0, 944 }, 945 #endif /* chips */ 946 947 #if defined(BCM_56440_B0) 948 { /* SOC_FORMAT_INT_DEQ_TO_EMC_RD_REQ_INFO_BCM56440_B0fmt */ 949 /* format DEQ_TO_EMC_RD_REQ_INFOfmt */ 950 /* nFields */ 6, 951 /* *fields */ soc_DEQ_TO_EMC_RD_REQ_INFOfmt_fields, 952 /* bits */ 31, 953 /* flags */ 0, 954 }, 955 #endif /* chips */ 956 957 #if defined(BCM_56450_A0) 958 { /* SOC_FORMAT_INT_DEQ_TO_EMC_RD_REQ_INFO_BCM56450_A0fmt */ 959 /* format DEQ_TO_EMC_RD_REQ_INFOfmt */ 960 /* nFields */ 6, 961 /* *fields */ soc_DEQ_TO_EMC_RD_REQ_INFO_BCM56450_A0fmt_fields, 962 /* bits */ 37, 963 /* flags */ 0, 964 }, 965 #endif /* chips */ 966 967 #if defined(BCM_56450_B0) 968 { /* SOC_FORMAT_INT_DEQ_TO_EMC_RD_REQ_INFO_BCM56450_B0fmt */ 969 /* format DEQ_TO_EMC_RD_REQ_INFOfmt */ 970 /* nFields */ 6, 971 /* *fields */ soc_DEQ_TO_EMC_RD_REQ_INFO_BCM56450_A0fmt_fields, 972 /* bits */ 37, 973 /* flags */ 0, 974 }, 975 #endif /* chips */ 976 977 #if defined(BCM_56450_B1) 978 { /* SOC_FORMAT_INT_DEQ_TO_EMC_RD_REQ_INFO_BCM56450_B1fmt */ 979 /* format DEQ_TO_EMC_RD_REQ_INFOfmt */ 980 /* nFields */ 6, 981 /* *fields */ soc_DEQ_TO_EMC_RD_REQ_INFO_BCM56450_A0fmt_fields, 982 /* bits */ 37, 983 /* flags */ 0, 984 }, 985 #endif /* chips */ 986 987 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) 988 { /* SOC_FORMAT_INT_DEQ_TO_LLS_SHAPE_BUS_INFOfmt */ 989 /* format DEQ_TO_LLS_SHAPE_BUS_INFOfmt */ 990 /* nFields */ 6, 991 /* *fields */ soc_DEQ_TO_LLS_SHAPE_BUS_INFOfmt_fields, 992 /* bits */ 53, 993 /* flags */ 0, 994 }, 995 #endif /* chips */ 996 997 #if defined(BCM_56260_A0) 998 { /* SOC_FORMAT_INT_DEQ_TO_LLS_SHAPE_BUS_INFO_BCM56260_A0fmt */ 999 /* format DEQ_TO_LLS_SHAPE_BUS_INFOfmt */ 1000 /* nFields */ 6, 1001 /* *fields */ soc_DEQ_TO_LLS_SHAPE_BUS_INFO_BCM56260_A0fmt_fields, 1002 /* bits */ 53, 1003 /* flags */ 0, 1004 }, 1005 #endif /* chips */ 1006 1007 #if defined(BCM_56260_B0) 1008 { /* SOC_FORMAT_INT_DEQ_TO_LLS_SHAPE_BUS_INFO_BCM56260_B0fmt */ 1009 /* format DEQ_TO_LLS_SHAPE_BUS_INFOfmt */ 1010 /* nFields */ 6, 1011 /* *fields */ soc_DEQ_TO_LLS_SHAPE_BUS_INFO_BCM56260_A0fmt_fields, 1012 /* bits */ 53, 1013 /* flags */ 0, 1014 }, 1015 #endif /* chips */ 1016 1017 #if defined(BCM_56270_A0) 1018 { /* SOC_FORMAT_INT_DEQ_TO_LLS_SHAPE_BUS_INFO_BCM56270_A0fmt */ 1019 /* format DEQ_TO_LLS_SHAPE_BUS_INFOfmt */ 1020 /* nFields */ 6, 1021 /* *fields */ soc_DEQ_TO_LLS_SHAPE_BUS_INFO_BCM56260_A0fmt_fields, 1022 /* bits */ 53, 1023 /* flags */ 0, 1024 }, 1025 #endif /* chips */ 1026 1027 #if defined(BCM_56450_A0) 1028 { /* SOC_FORMAT_INT_DEQ_TO_LLS_SHAPE_BUS_INFO_BCM56450_A0fmt */ 1029 /* format DEQ_TO_LLS_SHAPE_BUS_INFOfmt */ 1030 /* nFields */ 6, 1031 /* *fields */ soc_DEQ_TO_LLS_SHAPE_BUS_INFO_BCM56450_A0fmt_fields, 1032 /* bits */ 53, 1033 /* flags */ 0, 1034 }, 1035 #endif /* chips */ 1036 1037 #if defined(BCM_56450_B0) 1038 { /* SOC_FORMAT_INT_DEQ_TO_LLS_SHAPE_BUS_INFO_BCM56450_B0fmt */ 1039 /* format DEQ_TO_LLS_SHAPE_BUS_INFOfmt */ 1040 /* nFields */ 6, 1041 /* *fields */ soc_DEQ_TO_LLS_SHAPE_BUS_INFO_BCM56450_A0fmt_fields, 1042 /* bits */ 53, 1043 /* flags */ 0, 1044 }, 1045 #endif /* chips */ 1046 1047 #if defined(BCM_56450_B1) 1048 { /* SOC_FORMAT_INT_DEQ_TO_LLS_SHAPE_BUS_INFO_BCM56450_B1fmt */ 1049 /* format DEQ_TO_LLS_SHAPE_BUS_INFOfmt */ 1050 /* nFields */ 6, 1051 /* *fields */ soc_DEQ_TO_LLS_SHAPE_BUS_INFO_BCM56450_A0fmt_fields, 1052 /* bits */ 53, 1053 /* flags */ 0, 1054 }, 1055 #endif /* chips */ 1056 1057 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \ 1058 defined(BCM_56450_B1) 1059 { /* SOC_FORMAT_INT_DEQ_TO_RDE_CELL_INFOfmt */ 1060 /* format DEQ_TO_RDE_CELL_INFOfmt */ 1061 /* nFields */ 32, 1062 /* *fields */ soc_DEQ_TO_RDE_CELL_INFOfmt_fields, 1063 /* bits */ 131, 1064 /* flags */ 0, 1065 }, 1066 #endif /* chips */ 1067 1068 #if defined(BCM_56260_A0) 1069 { /* SOC_FORMAT_INT_DEQ_TO_RDE_CELL_INFO_BCM56260_A0fmt */ 1070 /* format DEQ_TO_RDE_CELL_INFOfmt */ 1071 /* nFields */ 32, 1072 /* *fields */ soc_DEQ_TO_RDE_CELL_INFO_BCM56260_A0fmt_fields, 1073 /* bits */ 120, 1074 /* flags */ 0, 1075 }, 1076 #endif /* chips */ 1077 1078 #if defined(BCM_56260_B0) 1079 { /* SOC_FORMAT_INT_DEQ_TO_RDE_CELL_INFO_BCM56260_B0fmt */ 1080 /* format DEQ_TO_RDE_CELL_INFOfmt */ 1081 /* nFields */ 32, 1082 /* *fields */ soc_DEQ_TO_RDE_CELL_INFO_BCM56260_A0fmt_fields, 1083 /* bits */ 120, 1084 /* flags */ 0, 1085 }, 1086 #endif /* chips */ 1087 1088 #if defined(BCM_56270_A0) 1089 { /* SOC_FORMAT_INT_DEQ_TO_RDE_CELL_INFO_BCM56270_A0fmt */ 1090 /* format DEQ_TO_RDE_CELL_INFOfmt */ 1091 /* nFields */ 26, 1092 /* *fields */ soc_DEQ_TO_RDE_CELL_INFO_BCM56270_A0fmt_fields, 1093 /* bits */ 99, 1094 /* flags */ 0, 1095 }, 1096 #endif /* chips */ 1097 1098 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \ 1099 defined(BCM_56450_B1) 1100 { /* SOC_FORMAT_INT_DEQ_TO_RDE_HDR_RD_INFOfmt */ 1101 /* format DEQ_TO_RDE_HDR_RD_INFOfmt */ 1102 /* nFields */ 3, 1103 /* *fields */ soc_DEQ_TO_RDE_HDR_RD_INFOfmt_fields, 1104 /* bits */ 15, 1105 /* flags */ 0, 1106 }, 1107 #endif /* chips */ 1108 1109 #if defined(BCM_56260_A0) 1110 { /* SOC_FORMAT_INT_DEQ_TO_RDE_HDR_RD_INFO_BCM56260_A0fmt */ 1111 /* format DEQ_TO_RDE_HDR_RD_INFOfmt */ 1112 /* nFields */ 3, 1113 /* *fields */ soc_DEQ_TO_RDE_HDR_RD_INFO_BCM56260_A0fmt_fields, 1114 /* bits */ 14, 1115 /* flags */ 0, 1116 }, 1117 #endif /* chips */ 1118 1119 #if defined(BCM_56260_B0) 1120 { /* SOC_FORMAT_INT_DEQ_TO_RDE_HDR_RD_INFO_BCM56260_B0fmt */ 1121 /* format DEQ_TO_RDE_HDR_RD_INFOfmt */ 1122 /* nFields */ 3, 1123 /* *fields */ soc_DEQ_TO_RDE_HDR_RD_INFO_BCM56260_A0fmt_fields, 1124 /* bits */ 14, 1125 /* flags */ 0, 1126 }, 1127 #endif /* chips */ 1128 1129 #if defined(BCM_56270_A0) 1130 { /* SOC_FORMAT_INT_DEQ_TO_RDE_HDR_RD_INFO_BCM56270_A0fmt */ 1131 /* format DEQ_TO_RDE_HDR_RD_INFOfmt */ 1132 /* nFields */ 3, 1133 /* *fields */ soc_DEQ_TO_RDE_HDR_RD_INFO_BCM56260_A0fmt_fields, 1134 /* bits */ 14, 1135 /* flags */ 0, 1136 }, 1137 #endif /* chips */ 1138 1139 #if defined(BCM_56634_A0) 1140 { /* SOC_FORMAT_INT_DEQ_TO_RDE_INFOfmt */ 1141 /* format DEQ_TO_RDE_INFOfmt */ 1142 /* nFields */ 2, 1143 /* *fields */ soc_DEQ_TO_RDE_INFOfmt_fields, 1144 /* bits */ 11, 1145 /* flags */ 0, 1146 }, 1147 #endif /* chips */ 1148 1149 #if defined(BCM_56524_A0) 1150 { /* SOC_FORMAT_INT_DEQ_TO_RDE_INFO_BCM56524_A0fmt */ 1151 /* format DEQ_TO_RDE_INFOfmt */ 1152 /* nFields */ 2, 1153 /* *fields */ soc_DEQ_TO_RDE_INFOfmt_fields, 1154 /* bits */ 11, 1155 /* flags */ 0, 1156 }, 1157 #endif /* chips */ 1158 1159 #if defined(BCM_56524_B0) 1160 { /* SOC_FORMAT_INT_DEQ_TO_RDE_INFO_BCM56524_B0fmt */ 1161 /* format DEQ_TO_RDE_INFOfmt */ 1162 /* nFields */ 2, 1163 /* *fields */ soc_DEQ_TO_RDE_INFOfmt_fields, 1164 /* bits */ 11, 1165 /* flags */ 0, 1166 }, 1167 #endif /* chips */ 1168 1169 #if defined(BCM_56634_B0) 1170 { /* SOC_FORMAT_INT_DEQ_TO_RDE_INFO_BCM56634_B0fmt */ 1171 /* format DEQ_TO_RDE_INFOfmt */ 1172 /* nFields */ 2, 1173 /* *fields */ soc_DEQ_TO_RDE_INFOfmt_fields, 1174 /* bits */ 11, 1175 /* flags */ 0, 1176 }, 1177 #endif /* chips */ 1178 1179 #if defined(BCM_56685_A0) 1180 { /* SOC_FORMAT_INT_DEQ_TO_RDE_INFO_BCM56685_A0fmt */ 1181 /* format DEQ_TO_RDE_INFOfmt */ 1182 /* nFields */ 2, 1183 /* *fields */ soc_DEQ_TO_RDE_INFOfmt_fields, 1184 /* bits */ 11, 1185 /* flags */ 0, 1186 }, 1187 #endif /* chips */ 1188 1189 #if defined(BCM_56685_B0) 1190 { /* SOC_FORMAT_INT_DEQ_TO_RDE_INFO_BCM56685_B0fmt */ 1191 /* format DEQ_TO_RDE_INFOfmt */ 1192 /* nFields */ 2, 1193 /* *fields */ soc_DEQ_TO_RDE_INFOfmt_fields, 1194 /* bits */ 11, 1195 /* flags */ 0, 1196 }, 1197 #endif /* chips */ 1198 1199 #if defined(BCM_56340_A0) || defined(BCM_56640_A0) 1200 { /* SOC_FORMAT_INT_DEQ_TO_RDE_INFO_BUS0fmt */ 1201 /* format DEQ_TO_RDE_INFO_BUS0fmt */ 1202 /* nFields */ 2, 1203 /* *fields */ soc_DEQ_TO_RDE_INFO_BUS0fmt_fields, 1204 /* bits */ 17, 1205 /* flags */ 0, 1206 }, 1207 #endif /* chips */ 1208 1209 #if defined(BCM_56340_A0) || defined(BCM_56640_A0) 1210 { /* SOC_FORMAT_INT_DEQ_TO_RDE_INFO_BUS1fmt */ 1211 /* format DEQ_TO_RDE_INFO_BUS1fmt */ 1212 /* nFields */ 27, 1213 /* *fields */ soc_DEQ_TO_RDE_INFO_BUS1fmt_fields, 1214 /* bits */ 105, 1215 /* flags */ 0, 1216 }, 1217 #endif /* chips */ 1218 1219 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \ 1220 defined(BCM_56450_B1) 1221 { /* SOC_FORMAT_INT_DEQ_TO_RDE_PQE_CELL_INFOfmt */ 1222 /* format DEQ_TO_RDE_PQE_CELL_INFOfmt */ 1223 /* nFields */ 23, 1224 /* *fields */ soc_DEQ_TO_RDE_PQE_CELL_INFOfmt_fields, 1225 /* bits */ 84, 1226 /* flags */ 0, 1227 }, 1228 #endif /* chips */ 1229 1230 #if defined(BCM_56260_A0) 1231 { /* SOC_FORMAT_INT_DEQ_TO_RDE_PQE_CELL_INFO_BCM56260_A0fmt */ 1232 /* format DEQ_TO_RDE_PQE_CELL_INFOfmt */ 1233 /* nFields */ 23, 1234 /* *fields */ soc_DEQ_TO_RDE_PQE_CELL_INFO_BCM56260_A0fmt_fields, 1235 /* bits */ 79, 1236 /* flags */ 0, 1237 }, 1238 #endif /* chips */ 1239 1240 #if defined(BCM_56260_B0) 1241 { /* SOC_FORMAT_INT_DEQ_TO_RDE_PQE_CELL_INFO_BCM56260_B0fmt */ 1242 /* format DEQ_TO_RDE_PQE_CELL_INFOfmt */ 1243 /* nFields */ 23, 1244 /* *fields */ soc_DEQ_TO_RDE_PQE_CELL_INFO_BCM56260_A0fmt_fields, 1245 /* bits */ 79, 1246 /* flags */ 0, 1247 }, 1248 #endif /* chips */ 1249 1250 #if defined(BCM_56270_A0) 1251 { /* SOC_FORMAT_INT_DEQ_TO_RDE_PQE_CELL_INFO_BCM56270_A0fmt */ 1252 /* format DEQ_TO_RDE_PQE_CELL_INFOfmt */ 1253 /* nFields */ 20, 1254 /* *fields */ soc_DEQ_TO_RDE_PQE_CELL_INFO_BCM56270_A0fmt_fields, 1255 /* bits */ 72, 1256 /* flags */ 0, 1257 }, 1258 #endif /* chips */ 1259 1260 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \ 1261 defined(BCM_56450_B1) 1262 { /* SOC_FORMAT_INT_DEQ_TO_RDE_REDIR_INFOfmt */ 1263 /* format DEQ_TO_RDE_REDIR_INFOfmt */ 1264 /* nFields */ 8, 1265 /* *fields */ soc_DEQ_TO_RDE_REDIR_INFOfmt_fields, 1266 /* bits */ 12, 1267 /* flags */ 0, 1268 }, 1269 #endif /* chips */ 1270 1271 #if defined(BCM_56260_A0) 1272 { /* SOC_FORMAT_INT_DEQ_TO_RDE_REDIR_INFO_BCM56260_A0fmt */ 1273 /* format DEQ_TO_RDE_REDIR_INFOfmt */ 1274 /* nFields */ 8, 1275 /* *fields */ soc_DEQ_TO_RDE_REDIR_INFO_BCM56260_A0fmt_fields, 1276 /* bits */ 12, 1277 /* flags */ 0, 1278 }, 1279 #endif /* chips */ 1280 1281 #if defined(BCM_56260_B0) 1282 { /* SOC_FORMAT_INT_DEQ_TO_RDE_REDIR_INFO_BCM56260_B0fmt */ 1283 /* format DEQ_TO_RDE_REDIR_INFOfmt */ 1284 /* nFields */ 8, 1285 /* *fields */ soc_DEQ_TO_RDE_REDIR_INFO_BCM56260_A0fmt_fields, 1286 /* bits */ 12, 1287 /* flags */ 0, 1288 }, 1289 #endif /* chips */ 1290 1291 #if defined(BCM_56270_A0) 1292 { /* SOC_FORMAT_INT_DEQ_TO_RDE_REDIR_INFO_BCM56270_A0fmt */ 1293 /* format DEQ_TO_RDE_REDIR_INFOfmt */ 1294 /* nFields */ 8, 1295 /* *fields */ soc_DEQ_TO_RDE_REDIR_INFO_BCM56260_A0fmt_fields, 1296 /* bits */ 12, 1297 /* flags */ 0, 1298 }, 1299 #endif /* chips */ 1300 1301 #if defined(BCM_56340_A0) || defined(BCM_56640_A0) 1302 { /* SOC_FORMAT_INT_DEQ_TO_SQS_INFOfmt */ 1303 /* format DEQ_TO_SQS_INFOfmt */ 1304 /* nFields */ 5, 1305 /* *fields */ soc_DEQ_TO_SQS_INFOfmt_fields, 1306 /* bits */ 15, 1307 /* flags */ 0, 1308 }, 1309 #endif /* chips */ 1310 1311 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) 1312 { /* SOC_FORMAT_INT_DEQ_TO_TOQ_CREDIT_VECTOR_INFOfmt */ 1313 /* format DEQ_TO_TOQ_CREDIT_VECTOR_INFOfmt */ 1314 /* nFields */ 1, 1315 /* *fields */ soc_DEQ_TO_TOQ_CREDIT_VECTOR_INFOfmt_fields, 1316 /* bits */ 36, 1317 /* flags */ 0, 1318 }, 1319 #endif /* chips */ 1320 1321 #if defined(BCM_56450_A0) 1322 { /* SOC_FORMAT_INT_DEQ_TO_TOQ_CREDIT_VECTOR_INFO_BCM56450_A0fmt */ 1323 /* format DEQ_TO_TOQ_CREDIT_VECTOR_INFOfmt */ 1324 /* nFields */ 1, 1325 /* *fields */ soc_DEQ_TO_TOQ_CREDIT_VECTOR_INFO_BCM56450_A0fmt_fields, 1326 /* bits */ 42, 1327 /* flags */ 0, 1328 }, 1329 #endif /* chips */ 1330 1331 #if defined(BCM_56450_B0) 1332 { /* SOC_FORMAT_INT_DEQ_TO_TOQ_CREDIT_VECTOR_INFO_BCM56450_B0fmt */ 1333 /* format DEQ_TO_TOQ_CREDIT_VECTOR_INFOfmt */ 1334 /* nFields */ 1, 1335 /* *fields */ soc_DEQ_TO_TOQ_CREDIT_VECTOR_INFO_BCM56450_A0fmt_fields, 1336 /* bits */ 42, 1337 /* flags */ 0, 1338 }, 1339 #endif /* chips */ 1340 1341 #if defined(BCM_56450_B1) 1342 { /* SOC_FORMAT_INT_DEQ_TO_TOQ_CREDIT_VECTOR_INFO_BCM56450_B1fmt */ 1343 /* format DEQ_TO_TOQ_CREDIT_VECTOR_INFOfmt */ 1344 /* nFields */ 1, 1345 /* *fields */ soc_DEQ_TO_TOQ_CREDIT_VECTOR_INFO_BCM56450_A0fmt_fields, 1346 /* bits */ 42, 1347 /* flags */ 0, 1348 }, 1349 #endif /* chips */ 1350 1351 #if defined(BCM_56850_A0) || defined(BCM_56860_A0) 1352 { /* SOC_FORMAT_INT_DEQ_TO_TOQ_INFOfmt */ 1353 /* format DEQ_TO_TOQ_INFOfmt */ 1354 /* nFields */ 4, 1355 /* *fields */ soc_DEQ_TO_TOQ_INFOfmt_fields, 1356 /* bits */ 32, 1357 /* flags */ 0, 1358 }, 1359 #endif /* chips */ 1360 1361 #if defined(BCM_56560_A0) 1362 { /* SOC_FORMAT_INT_DEQ_TO_TOQ_INFO_BCM56560_A0fmt */ 1363 /* format DEQ_TO_TOQ_INFOfmt */ 1364 /* nFields */ 4, 1365 /* *fields */ soc_DEQ_TO_TOQ_INFO_BCM56560_A0fmt_fields, 1366 /* bits */ 35, 1367 /* flags */ 0, 1368 }, 1369 #endif /* chips */ 1370 1371 #if defined(BCM_56560_B0) 1372 { /* SOC_FORMAT_INT_DEQ_TO_TOQ_INFO_BCM56560_B0fmt */ 1373 /* format DEQ_TO_TOQ_INFOfmt */ 1374 /* nFields */ 4, 1375 /* *fields */ soc_DEQ_TO_TOQ_INFO_BCM56560_A0fmt_fields, 1376 /* bits */ 35, 1377 /* flags */ 0, 1378 }, 1379 #endif /* chips */ 1380 1381 #if defined(BCM_56670_A0) 1382 { /* SOC_FORMAT_INT_DEQ_TO_TOQ_INFO_BCM56670_A0fmt */ 1383 /* format DEQ_TO_TOQ_INFOfmt */ 1384 /* nFields */ 4, 1385 /* *fields */ soc_DEQ_TO_TOQ_INFO_BCM56670_A0fmt_fields, 1386 /* bits */ 30, 1387 /* flags */ 0, 1388 }, 1389 #endif /* chips */ 1390 1391 #if defined(BCM_56670_B0) 1392 { /* SOC_FORMAT_INT_DEQ_TO_TOQ_INFO_BCM56670_B0fmt */ 1393 /* format DEQ_TO_TOQ_INFOfmt */ 1394 /* nFields */ 4, 1395 /* *fields */ soc_DEQ_TO_TOQ_INFO_BCM56670_A0fmt_fields, 1396 /* bits */ 30, 1397 /* flags */ 0, 1398 }, 1399 #endif /* chips */ 1400 1401 #if defined(BCM_56800_A0) 1402 { /* SOC_FORMAT_INT_DEQ_TO_TOQ_REG_INFOfmt */ 1403 /* format DEQ_TO_TOQ_REG_INFOfmt */ 1404 /* nFields */ 3, 1405 /* *fields */ soc_DEQ_TO_TOQ_REG_INFOfmt_fields, 1406 /* bits */ 12, 1407 /* flags */ 0, 1408 }, 1409 #endif /* chips */ 1410 1411 #if defined(BCM_56334_A0) 1412 { /* SOC_FORMAT_INT_DEQ_TO_TOQ_REG_INFO_BCM56334_A0fmt */ 1413 /* format DEQ_TO_TOQ_REG_INFOfmt */ 1414 /* nFields */ 7, 1415 /* *fields */ soc_DEQ_TO_TOQ_REG_INFO_BCM56624_A0fmt_fields, 1416 /* bits */ 39, 1417 /* flags */ 0, 1418 }, 1419 #endif /* chips */ 1420 1421 #if defined(BCM_56334_B0) 1422 { /* SOC_FORMAT_INT_DEQ_TO_TOQ_REG_INFO_BCM56334_B0fmt */ 1423 /* format DEQ_TO_TOQ_REG_INFOfmt */ 1424 /* nFields */ 7, 1425 /* *fields */ soc_DEQ_TO_TOQ_REG_INFO_BCM56624_A0fmt_fields, 1426 /* bits */ 39, 1427 /* flags */ 0, 1428 }, 1429 #endif /* chips */ 1430 1431 #if defined(BCM_56524_A0) 1432 { /* SOC_FORMAT_INT_DEQ_TO_TOQ_REG_INFO_BCM56524_A0fmt */ 1433 /* format DEQ_TO_TOQ_REG_INFOfmt */ 1434 /* nFields */ 7, 1435 /* *fields */ soc_DEQ_TO_TOQ_REG_INFO_BCM56624_A0fmt_fields, 1436 /* bits */ 39, 1437 /* flags */ 0, 1438 }, 1439 #endif /* chips */ 1440 1441 #if defined(BCM_56524_B0) 1442 { /* SOC_FORMAT_INT_DEQ_TO_TOQ_REG_INFO_BCM56524_B0fmt */ 1443 /* format DEQ_TO_TOQ_REG_INFOfmt */ 1444 /* nFields */ 7, 1445 /* *fields */ soc_DEQ_TO_TOQ_REG_INFO_BCM56624_A0fmt_fields, 1446 /* bits */ 39, 1447 /* flags */ 0, 1448 }, 1449 #endif /* chips */ 1450 1451 #if defined(BCM_56624_A0) 1452 { /* SOC_FORMAT_INT_DEQ_TO_TOQ_REG_INFO_BCM56624_A0fmt */ 1453 /* format DEQ_TO_TOQ_REG_INFOfmt */ 1454 /* nFields */ 7, 1455 /* *fields */ soc_DEQ_TO_TOQ_REG_INFO_BCM56624_A0fmt_fields, 1456 /* bits */ 39, 1457 /* flags */ 0, 1458 }, 1459 #endif /* chips */ 1460 1461 #if defined(BCM_56624_B0) 1462 { /* SOC_FORMAT_INT_DEQ_TO_TOQ_REG_INFO_BCM56624_B0fmt */ 1463 /* format DEQ_TO_TOQ_REG_INFOfmt */ 1464 /* nFields */ 7, 1465 /* *fields */ soc_DEQ_TO_TOQ_REG_INFO_BCM56624_A0fmt_fields, 1466 /* bits */ 39, 1467 /* flags */ 0, 1468 }, 1469 #endif /* chips */ 1470 1471 #if defined(BCM_56634_A0) 1472 { /* SOC_FORMAT_INT_DEQ_TO_TOQ_REG_INFO_BCM56634_A0fmt */ 1473 /* format DEQ_TO_TOQ_REG_INFOfmt */ 1474 /* nFields */ 7, 1475 /* *fields */ soc_DEQ_TO_TOQ_REG_INFO_BCM56624_A0fmt_fields, 1476 /* bits */ 39, 1477 /* flags */ 0, 1478 }, 1479 #endif /* chips */ 1480 1481 #if defined(BCM_56634_B0) 1482 { /* SOC_FORMAT_INT_DEQ_TO_TOQ_REG_INFO_BCM56634_B0fmt */ 1483 /* format DEQ_TO_TOQ_REG_INFOfmt */ 1484 /* nFields */ 7, 1485 /* *fields */ soc_DEQ_TO_TOQ_REG_INFO_BCM56624_A0fmt_fields, 1486 /* bits */ 39, 1487 /* flags */ 0, 1488 }, 1489 #endif /* chips */ 1490 1491 #if defined(BCM_56680_A0) 1492 { /* SOC_FORMAT_INT_DEQ_TO_TOQ_REG_INFO_BCM56680_A0fmt */ 1493 /* format DEQ_TO_TOQ_REG_INFOfmt */ 1494 /* nFields */ 7, 1495 /* *fields */ soc_DEQ_TO_TOQ_REG_INFO_BCM56624_A0fmt_fields, 1496 /* bits */ 39, 1497 /* flags */ 0, 1498 }, 1499 #endif /* chips */ 1500 1501 #if defined(BCM_56680_B0) 1502 { /* SOC_FORMAT_INT_DEQ_TO_TOQ_REG_INFO_BCM56680_B0fmt */ 1503 /* format DEQ_TO_TOQ_REG_INFOfmt */ 1504 /* nFields */ 7, 1505 /* *fields */ soc_DEQ_TO_TOQ_REG_INFO_BCM56624_A0fmt_fields, 1506 /* bits */ 39, 1507 /* flags */ 0, 1508 }, 1509 #endif /* chips */ 1510 1511 #if defined(BCM_56685_A0) 1512 { /* SOC_FORMAT_INT_DEQ_TO_TOQ_REG_INFO_BCM56685_A0fmt */ 1513 /* format DEQ_TO_TOQ_REG_INFOfmt */ 1514 /* nFields */ 7, 1515 /* *fields */ soc_DEQ_TO_TOQ_REG_INFO_BCM56624_A0fmt_fields, 1516 /* bits */ 39, 1517 /* flags */ 0, 1518 }, 1519 #endif /* chips */ 1520 1521 #if defined(BCM_56685_B0) 1522 { /* SOC_FORMAT_INT_DEQ_TO_TOQ_REG_INFO_BCM56685_B0fmt */ 1523 /* format DEQ_TO_TOQ_REG_INFOfmt */ 1524 /* nFields */ 7, 1525 /* *fields */ soc_DEQ_TO_TOQ_REG_INFO_BCM56624_A0fmt_fields, 1526 /* bits */ 39, 1527 /* flags */ 0, 1528 }, 1529 #endif /* chips */ 1530 1531 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) 1532 { /* SOC_FORMAT_INT_DEQ_TO_WRED_INFOfmt */ 1533 /* format DEQ_TO_WRED_INFOfmt */ 1534 /* nFields */ 2, 1535 /* *fields */ soc_DEQ_TO_WRED_INFOfmt_fields, 1536 /* bits */ 13, 1537 /* flags */ 0, 1538 }, 1539 #endif /* chips */ 1540 1541 #if defined(BCM_56260_A0) 1542 { /* SOC_FORMAT_INT_DEQ_TO_WRED_INFO_BCM56260_A0fmt */ 1543 /* format DEQ_TO_WRED_INFOfmt */ 1544 /* nFields */ 3, 1545 /* *fields */ soc_DEQ_TO_WRED_INFO_BCM56260_A0fmt_fields, 1546 /* bits */ 12, 1547 /* flags */ 0, 1548 }, 1549 #endif /* chips */ 1550 1551 #if defined(BCM_56260_B0) 1552 { /* SOC_FORMAT_INT_DEQ_TO_WRED_INFO_BCM56260_B0fmt */ 1553 /* format DEQ_TO_WRED_INFOfmt */ 1554 /* nFields */ 3, 1555 /* *fields */ soc_DEQ_TO_WRED_INFO_BCM56260_A0fmt_fields, 1556 /* bits */ 12, 1557 /* flags */ 0, 1558 }, 1559 #endif /* chips */ 1560 1561 #if defined(BCM_56270_A0) 1562 { /* SOC_FORMAT_INT_DEQ_TO_WRED_INFO_BCM56270_A0fmt */ 1563 /* format DEQ_TO_WRED_INFOfmt */ 1564 /* nFields */ 2, 1565 /* *fields */ soc_DEQ_TO_WRED_INFO_BCM56270_A0fmt_fields, 1566 /* bits */ 10, 1567 /* flags */ 0, 1568 }, 1569 #endif /* chips */ 1570 1571 #if defined(BCM_56450_A0) 1572 { /* SOC_FORMAT_INT_DEQ_TO_WRED_INFO_BCM56450_A0fmt */ 1573 /* format DEQ_TO_WRED_INFOfmt */ 1574 /* nFields */ 3, 1575 /* *fields */ soc_DEQ_TO_WRED_INFO_BCM56450_A0fmt_fields, 1576 /* bits */ 14, 1577 /* flags */ 0, 1578 }, 1579 #endif /* chips */ 1580 1581 #if defined(BCM_56450_B0) 1582 { /* SOC_FORMAT_INT_DEQ_TO_WRED_INFO_BCM56450_B0fmt */ 1583 /* format DEQ_TO_WRED_INFOfmt */ 1584 /* nFields */ 3, 1585 /* *fields */ soc_DEQ_TO_WRED_INFO_BCM56450_A0fmt_fields, 1586 /* bits */ 14, 1587 /* flags */ 0, 1588 }, 1589 #endif /* chips */ 1590 1591 #if defined(BCM_56450_B1) 1592 { /* SOC_FORMAT_INT_DEQ_TO_WRED_INFO_BCM56450_B1fmt */ 1593 /* format DEQ_TO_WRED_INFOfmt */ 1594 /* nFields */ 3, 1595 /* *fields */ soc_DEQ_TO_WRED_INFO_BCM56450_A0fmt_fields, 1596 /* bits */ 14, 1597 /* flags */ 0, 1598 }, 1599 #endif /* chips */ 1600 1601 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \ 1602 defined(BCM_56142_A0) || defined(BCM_56224_A0) || \ 1603 defined(BCM_56224_B0) || defined(BCM_56314_A0) || \ 1604 defined(BCM_56334_A0) || defined(BCM_56334_B0) || \ 1605 defined(BCM_56440_A0) || defined(BCM_56440_B0) || \ 1606 defined(BCM_56504_A0) || defined(BCM_56624_A0) || \ 1607 defined(BCM_56624_B0) || defined(BCM_56634_A0) || \ 1608 defined(BCM_56680_A0) || defined(BCM_56680_B0) || \ 1609 defined(BCM_56685_A0) || defined(BCM_56685_B0) || \ 1610 defined(BCM_56725_A0) || defined(BCM_56820_A0) || \ 1611 defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 1612 defined(BCM_88732_A0) 1613 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_00fmt */ 1614 /* format DESCRIPTOR_RX_00fmt */ 1615 /* nFields */ 1, 1616 /* *fields */ soc_DESCRIPTOR_RX_00fmt_fields, 1617 /* bits */ 32, 1618 /* flags */ 0, 1619 }, 1620 #endif /* chips */ 1621 1622 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \ 1623 defined(BCM_56142_A0) || defined(BCM_56224_A0) || \ 1624 defined(BCM_56224_B0) || defined(BCM_56314_A0) || \ 1625 defined(BCM_56334_A0) || defined(BCM_56334_B0) || \ 1626 defined(BCM_56440_A0) || defined(BCM_56440_B0) || \ 1627 defined(BCM_56504_A0) || defined(BCM_56504_B0) || \ 1628 defined(BCM_56514_A0) || defined(BCM_56524_A0) || \ 1629 defined(BCM_56524_B0) || defined(BCM_56624_A0) || \ 1630 defined(BCM_56624_B0) || defined(BCM_56634_A0) || \ 1631 defined(BCM_56634_B0) || defined(BCM_56680_A0) || \ 1632 defined(BCM_56680_B0) || defined(BCM_56685_A0) || \ 1633 defined(BCM_56685_B0) || defined(BCM_56725_A0) || \ 1634 defined(BCM_56820_A0) || defined(BCM_56840_A0) || \ 1635 defined(BCM_56840_B0) || defined(BCM_88732_A0) 1636 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_01fmt */ 1637 /* format DESCRIPTOR_RX_01fmt */ 1638 /* nFields */ 4, 1639 /* *fields */ soc_DESCRIPTOR_RX_01fmt_fields, 1640 /* bits */ 19, 1641 /* flags */ 0, 1642 }, 1643 #endif /* chips */ 1644 1645 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \ 1646 defined(BCM_56224_A0) || defined(BCM_56224_B0) || \ 1647 defined(BCM_56314_A0) || defined(BCM_56504_A0) || \ 1648 defined(BCM_56504_B0) || defined(BCM_56514_A0) 1649 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_02fmt */ 1650 /* format DESCRIPTOR_RX_02fmt */ 1651 /* nFields */ 1, 1652 /* *fields */ soc_DESCRIPTOR_RX_02fmt_fields, 1653 /* bits */ 32, 1654 /* flags */ 0, 1655 }, 1656 #endif /* chips */ 1657 1658 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \ 1659 defined(BCM_56224_A0) || defined(BCM_56224_B0) || \ 1660 defined(BCM_56314_A0) || defined(BCM_56504_A0) || \ 1661 defined(BCM_56514_A0) 1662 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_03fmt */ 1663 /* format DESCRIPTOR_RX_03fmt */ 1664 /* nFields */ 1, 1665 /* *fields */ soc_DESCRIPTOR_RX_03fmt_fields, 1666 /* bits */ 32, 1667 /* flags */ 0, 1668 }, 1669 #endif /* chips */ 1670 1671 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \ 1672 defined(BCM_56224_A0) || defined(BCM_56224_B0) || \ 1673 defined(BCM_56314_A0) || defined(BCM_56504_A0) || \ 1674 defined(BCM_56514_A0) 1675 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_04fmt */ 1676 /* format DESCRIPTOR_RX_04fmt */ 1677 /* nFields */ 1, 1678 /* *fields */ soc_DESCRIPTOR_RX_04fmt_fields, 1679 /* bits */ 32, 1680 /* flags */ 0, 1681 }, 1682 #endif /* chips */ 1683 1684 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \ 1685 defined(BCM_56224_A0) || defined(BCM_56224_B0) || \ 1686 defined(BCM_56314_A0) || defined(BCM_56504_A0) || \ 1687 defined(BCM_56504_B0) || defined(BCM_56514_A0) 1688 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_05fmt */ 1689 /* format DESCRIPTOR_RX_05fmt */ 1690 /* nFields */ 1, 1691 /* *fields */ soc_DESCRIPTOR_RX_05fmt_fields, 1692 /* bits */ 32, 1693 /* flags */ 0, 1694 }, 1695 #endif /* chips */ 1696 1697 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \ 1698 defined(BCM_56224_A0) || defined(BCM_56224_B0) || \ 1699 defined(BCM_56314_A0) || defined(BCM_56504_A0) || \ 1700 defined(BCM_56504_B0) || defined(BCM_56514_A0) 1701 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_06fmt */ 1702 /* format DESCRIPTOR_RX_06fmt */ 1703 /* nFields */ 1, 1704 /* *fields */ soc_DESCRIPTOR_RX_06fmt_fields, 1705 /* bits */ 32, 1706 /* flags */ 0, 1707 }, 1708 #endif /* chips */ 1709 1710 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \ 1711 defined(BCM_56224_A0) || defined(BCM_56224_B0) || \ 1712 defined(BCM_56314_A0) || defined(BCM_56504_A0) || \ 1713 defined(BCM_56504_B0) || defined(BCM_56514_A0) || \ 1714 defined(BCM_56800_A0) 1715 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_07fmt */ 1716 /* format DESCRIPTOR_RX_07fmt */ 1717 /* nFields */ 1, 1718 /* *fields */ soc_DESCRIPTOR_RX_07fmt_fields, 1719 /* bits */ 32, 1720 /* flags */ 0, 1721 }, 1722 #endif /* chips */ 1723 1724 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \ 1725 defined(BCM_56224_A0) || defined(BCM_56224_B0) || \ 1726 defined(BCM_56314_A0) || defined(BCM_56504_A0) || \ 1727 defined(BCM_56504_B0) || defined(BCM_56514_A0) || \ 1728 defined(BCM_56800_A0) 1729 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_08fmt */ 1730 /* format DESCRIPTOR_RX_08fmt */ 1731 /* nFields */ 1, 1732 /* *fields */ soc_DESCRIPTOR_RX_08fmt_fields, 1733 /* bits */ 32, 1734 /* flags */ 0, 1735 }, 1736 #endif /* chips */ 1737 1738 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \ 1739 defined(BCM_56224_A0) || defined(BCM_56224_B0) || \ 1740 defined(BCM_56314_A0) || defined(BCM_56504_A0) || \ 1741 defined(BCM_56504_B0) || defined(BCM_56514_A0) || \ 1742 defined(BCM_56800_A0) 1743 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_09fmt */ 1744 /* format DESCRIPTOR_RX_09fmt */ 1745 /* nFields */ 1, 1746 /* *fields */ soc_DESCRIPTOR_RX_09fmt_fields, 1747 /* bits */ 32, 1748 /* flags */ 0, 1749 }, 1750 #endif /* chips */ 1751 1752 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \ 1753 defined(BCM_56224_A0) || defined(BCM_56224_B0) || \ 1754 defined(BCM_56314_A0) || defined(BCM_56504_A0) || \ 1755 defined(BCM_56504_B0) || defined(BCM_56514_A0) || \ 1756 defined(BCM_56800_A0) 1757 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_10fmt */ 1758 /* format DESCRIPTOR_RX_10fmt */ 1759 /* nFields */ 5, 1760 /* *fields */ soc_DESCRIPTOR_RX_10fmt_fields, 1761 /* bits */ 32, 1762 /* flags */ 0, 1763 }, 1764 #endif /* chips */ 1765 1766 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \ 1767 defined(BCM_56334_B0) || defined(BCM_56440_A0) || \ 1768 defined(BCM_56440_B0) || defined(BCM_56524_A0) || \ 1769 defined(BCM_56524_B0) || defined(BCM_56624_A0) || \ 1770 defined(BCM_56624_B0) || defined(BCM_56634_A0) || \ 1771 defined(BCM_56634_B0) || defined(BCM_56680_A0) || \ 1772 defined(BCM_56680_B0) || defined(BCM_56685_A0) || \ 1773 defined(BCM_56685_B0) || defined(BCM_56725_A0) || \ 1774 defined(BCM_56820_A0) || defined(BCM_56840_A0) || \ 1775 defined(BCM_56840_B0) || defined(BCM_88732_A0) 1776 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_11fmt */ 1777 /* format DESCRIPTOR_RX_11fmt */ 1778 /* nFields */ 1, 1779 /* *fields */ soc_DESCRIPTOR_RX_11fmt_fields, 1780 /* bits */ 32, 1781 /* flags */ 0, 1782 }, 1783 #endif /* chips */ 1784 1785 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \ 1786 defined(BCM_56334_B0) || defined(BCM_56440_A0) || \ 1787 defined(BCM_56440_B0) || defined(BCM_56524_A0) || \ 1788 defined(BCM_56524_B0) || defined(BCM_56624_A0) || \ 1789 defined(BCM_56624_B0) || defined(BCM_56634_A0) || \ 1790 defined(BCM_56634_B0) || defined(BCM_56680_A0) || \ 1791 defined(BCM_56680_B0) || defined(BCM_56685_A0) || \ 1792 defined(BCM_56685_B0) || defined(BCM_56725_A0) || \ 1793 defined(BCM_56820_A0) || defined(BCM_56840_A0) || \ 1794 defined(BCM_56840_B0) || defined(BCM_88732_A0) 1795 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_12fmt */ 1796 /* format DESCRIPTOR_RX_12fmt */ 1797 /* nFields */ 1, 1798 /* *fields */ soc_DESCRIPTOR_RX_12fmt_fields, 1799 /* bits */ 32, 1800 /* flags */ 0, 1801 }, 1802 #endif /* chips */ 1803 1804 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \ 1805 defined(BCM_56334_B0) || defined(BCM_56440_A0) || \ 1806 defined(BCM_56440_B0) || defined(BCM_56524_A0) || \ 1807 defined(BCM_56524_B0) || defined(BCM_56624_A0) || \ 1808 defined(BCM_56624_B0) || defined(BCM_56634_A0) || \ 1809 defined(BCM_56634_B0) || defined(BCM_56680_A0) || \ 1810 defined(BCM_56680_B0) || defined(BCM_56685_A0) || \ 1811 defined(BCM_56685_B0) || defined(BCM_56725_A0) || \ 1812 defined(BCM_56820_A0) || defined(BCM_56840_A0) || \ 1813 defined(BCM_56840_B0) || defined(BCM_88732_A0) 1814 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_13fmt */ 1815 /* format DESCRIPTOR_RX_13fmt */ 1816 /* nFields */ 1, 1817 /* *fields */ soc_DESCRIPTOR_RX_13fmt_fields, 1818 /* bits */ 32, 1819 /* flags */ 0, 1820 }, 1821 #endif /* chips */ 1822 1823 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \ 1824 defined(BCM_56334_B0) || defined(BCM_56440_A0) || \ 1825 defined(BCM_56440_B0) || defined(BCM_56524_A0) || \ 1826 defined(BCM_56524_B0) || defined(BCM_56624_A0) || \ 1827 defined(BCM_56624_B0) || defined(BCM_56634_A0) || \ 1828 defined(BCM_56634_B0) || defined(BCM_56680_A0) || \ 1829 defined(BCM_56680_B0) || defined(BCM_56685_A0) || \ 1830 defined(BCM_56685_B0) || defined(BCM_56725_A0) || \ 1831 defined(BCM_56820_A0) || defined(BCM_56840_A0) || \ 1832 defined(BCM_56840_B0) || defined(BCM_88732_A0) 1833 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_14fmt */ 1834 /* format DESCRIPTOR_RX_14fmt */ 1835 /* nFields */ 1, 1836 /* *fields */ soc_DESCRIPTOR_RX_14fmt_fields, 1837 /* bits */ 32, 1838 /* flags */ 0, 1839 }, 1840 #endif /* chips */ 1841 1842 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \ 1843 defined(BCM_56334_B0) || defined(BCM_56524_A0) || \ 1844 defined(BCM_56524_B0) || defined(BCM_56624_A0) || \ 1845 defined(BCM_56624_B0) || defined(BCM_56634_A0) || \ 1846 defined(BCM_56634_B0) || defined(BCM_56680_A0) || \ 1847 defined(BCM_56680_B0) || defined(BCM_56685_A0) || \ 1848 defined(BCM_56685_B0) || defined(BCM_56725_A0) || \ 1849 defined(BCM_56820_A0) || defined(BCM_56840_A0) || \ 1850 defined(BCM_56840_B0) || defined(BCM_88732_A0) 1851 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_15fmt */ 1852 /* format DESCRIPTOR_RX_15fmt */ 1853 /* nFields */ 5, 1854 /* *fields */ soc_DESCRIPTOR_RX_15fmt_fields, 1855 /* bits */ 32, 1856 /* flags */ 0, 1857 }, 1858 #endif /* chips */ 1859 1860 #if defined(BCM_53400_A0) 1861 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_00_BCM53400_A0fmt */ 1862 /* format DESCRIPTOR_RX_00fmt */ 1863 /* nFields */ 1, 1864 /* *fields */ soc_DESCRIPTOR_RX_00_BCM53400_A0fmt_fields, 1865 /* bits */ 32, 1866 /* flags */ 0, 1867 }, 1868 #endif /* chips */ 1869 1870 #if defined(BCM_53540_A0) 1871 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_00_BCM53540_A0fmt */ 1872 /* format DESCRIPTOR_RX_00fmt */ 1873 /* nFields */ 1, 1874 /* *fields */ soc_DESCRIPTOR_RX_00_BCM53400_A0fmt_fields, 1875 /* bits */ 32, 1876 /* flags */ 0, 1877 }, 1878 #endif /* chips */ 1879 1880 #if defined(BCM_53570_A0) 1881 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_00_BCM53570_A0fmt */ 1882 /* format DESCRIPTOR_RX_00fmt */ 1883 /* nFields */ 1, 1884 /* *fields */ soc_DESCRIPTOR_RX_00_BCM53400_A0fmt_fields, 1885 /* bits */ 32, 1886 /* flags */ 0, 1887 }, 1888 #endif /* chips */ 1889 1890 #if defined(BCM_53570_B0) 1891 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_00_BCM53570_B0fmt */ 1892 /* format DESCRIPTOR_RX_00fmt */ 1893 /* nFields */ 1, 1894 /* *fields */ soc_DESCRIPTOR_RX_00_BCM53400_A0fmt_fields, 1895 /* bits */ 32, 1896 /* flags */ 0, 1897 }, 1898 #endif /* chips */ 1899 1900 #if defined(BCM_56150_A0) 1901 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_00_BCM56150_A0fmt */ 1902 /* format DESCRIPTOR_RX_00fmt */ 1903 /* nFields */ 1, 1904 /* *fields */ soc_DESCRIPTOR_RX_00_BCM56640_A0fmt_fields, 1905 /* bits */ 32, 1906 /* flags */ 0, 1907 }, 1908 #endif /* chips */ 1909 1910 #if defined(BCM_56160_A0) 1911 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_00_BCM56160_A0fmt */ 1912 /* format DESCRIPTOR_RX_00fmt */ 1913 /* nFields */ 1, 1914 /* *fields */ soc_DESCRIPTOR_RX_00_BCM53400_A0fmt_fields, 1915 /* bits */ 32, 1916 /* flags */ 0, 1917 }, 1918 #endif /* chips */ 1919 1920 #if defined(BCM_56260_A0) 1921 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_00_BCM56260_A0fmt */ 1922 /* format DESCRIPTOR_RX_00fmt */ 1923 /* nFields */ 1, 1924 /* *fields */ soc_DESCRIPTOR_RX_00_BCM53400_A0fmt_fields, 1925 /* bits */ 32, 1926 /* flags */ 0, 1927 }, 1928 #endif /* chips */ 1929 1930 #if defined(BCM_56260_B0) 1931 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_00_BCM56260_B0fmt */ 1932 /* format DESCRIPTOR_RX_00fmt */ 1933 /* nFields */ 1, 1934 /* *fields */ soc_DESCRIPTOR_RX_00_BCM53400_A0fmt_fields, 1935 /* bits */ 32, 1936 /* flags */ 0, 1937 }, 1938 #endif /* chips */ 1939 1940 #if defined(BCM_56270_A0) 1941 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_00_BCM56270_A0fmt */ 1942 /* format DESCRIPTOR_RX_00fmt */ 1943 /* nFields */ 1, 1944 /* *fields */ soc_DESCRIPTOR_RX_00_BCM53400_A0fmt_fields, 1945 /* bits */ 32, 1946 /* flags */ 0, 1947 }, 1948 #endif /* chips */ 1949 1950 #if defined(BCM_56340_A0) 1951 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_00_BCM56340_A0fmt */ 1952 /* format DESCRIPTOR_RX_00fmt */ 1953 /* nFields */ 1, 1954 /* *fields */ soc_DESCRIPTOR_RX_00_BCM56640_A0fmt_fields, 1955 /* bits */ 32, 1956 /* flags */ 0, 1957 }, 1958 #endif /* chips */ 1959 1960 #if defined(BCM_56370_A0) 1961 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_00_BCM56370_A0fmt */ 1962 /* format DESCRIPTOR_RX_00fmt */ 1963 /* nFields */ 1, 1964 /* *fields */ soc_DESCRIPTOR_RX_00_BCM53400_A0fmt_fields, 1965 /* bits */ 32, 1966 /* flags */ 0, 1967 }, 1968 #endif /* chips */ 1969 1970 #if defined(BCM_56450_A0) 1971 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_00_BCM56450_A0fmt */ 1972 /* format DESCRIPTOR_RX_00fmt */ 1973 /* nFields */ 1, 1974 /* *fields */ soc_DESCRIPTOR_RX_00_BCM56640_A0fmt_fields, 1975 /* bits */ 32, 1976 /* flags */ 0, 1977 }, 1978 #endif /* chips */ 1979 1980 #if defined(BCM_56450_B0) 1981 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_00_BCM56450_B0fmt */ 1982 /* format DESCRIPTOR_RX_00fmt */ 1983 /* nFields */ 1, 1984 /* *fields */ soc_DESCRIPTOR_RX_00_BCM56640_A0fmt_fields, 1985 /* bits */ 32, 1986 /* flags */ 0, 1987 }, 1988 #endif /* chips */ 1989 1990 #if defined(BCM_56450_B1) 1991 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_00_BCM56450_B1fmt */ 1992 /* format DESCRIPTOR_RX_00fmt */ 1993 /* nFields */ 1, 1994 /* *fields */ soc_DESCRIPTOR_RX_00_BCM56640_A0fmt_fields, 1995 /* bits */ 32, 1996 /* flags */ 0, 1997 }, 1998 #endif /* chips */ 1999 2000 #if defined(BCM_56504_B0) 2001 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_00_BCM56504_B0fmt */ 2002 /* format DESCRIPTOR_RX_00fmt */ 2003 /* nFields */ 1, 2004 /* *fields */ soc_DESCRIPTOR_RX_00fmt_fields, 2005 /* bits */ 32, 2006 /* flags */ 0, 2007 }, 2008 #endif /* chips */ 2009 2010 #if defined(BCM_56514_A0) 2011 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_00_BCM56514_A0fmt */ 2012 /* format DESCRIPTOR_RX_00fmt */ 2013 /* nFields */ 1, 2014 /* *fields */ soc_DESCRIPTOR_RX_00fmt_fields, 2015 /* bits */ 32, 2016 /* flags */ 0, 2017 }, 2018 #endif /* chips */ 2019 2020 #if defined(BCM_56524_A0) 2021 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_00_BCM56524_A0fmt */ 2022 /* format DESCRIPTOR_RX_00fmt */ 2023 /* nFields */ 1, 2024 /* *fields */ soc_DESCRIPTOR_RX_00fmt_fields, 2025 /* bits */ 32, 2026 /* flags */ 0, 2027 }, 2028 #endif /* chips */ 2029 2030 #if defined(BCM_56524_B0) 2031 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_00_BCM56524_B0fmt */ 2032 /* format DESCRIPTOR_RX_00fmt */ 2033 /* nFields */ 1, 2034 /* *fields */ soc_DESCRIPTOR_RX_00fmt_fields, 2035 /* bits */ 32, 2036 /* flags */ 0, 2037 }, 2038 #endif /* chips */ 2039 2040 #if defined(BCM_56560_A0) 2041 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_00_BCM56560_A0fmt */ 2042 /* format DESCRIPTOR_RX_00fmt */ 2043 /* nFields */ 1, 2044 /* *fields */ soc_DESCRIPTOR_RX_00_BCM53400_A0fmt_fields, 2045 /* bits */ 32, 2046 /* flags */ 0, 2047 }, 2048 #endif /* chips */ 2049 2050 #if defined(BCM_56560_B0) 2051 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_00_BCM56560_B0fmt */ 2052 /* format DESCRIPTOR_RX_00fmt */ 2053 /* nFields */ 1, 2054 /* *fields */ soc_DESCRIPTOR_RX_00_BCM53400_A0fmt_fields, 2055 /* bits */ 32, 2056 /* flags */ 0, 2057 }, 2058 #endif /* chips */ 2059 2060 #if defined(BCM_56634_B0) 2061 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_00_BCM56634_B0fmt */ 2062 /* format DESCRIPTOR_RX_00fmt */ 2063 /* nFields */ 1, 2064 /* *fields */ soc_DESCRIPTOR_RX_00fmt_fields, 2065 /* bits */ 32, 2066 /* flags */ 0, 2067 }, 2068 #endif /* chips */ 2069 2070 #if defined(BCM_56640_A0) 2071 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_00_BCM56640_A0fmt */ 2072 /* format DESCRIPTOR_RX_00fmt */ 2073 /* nFields */ 1, 2074 /* *fields */ soc_DESCRIPTOR_RX_00_BCM56640_A0fmt_fields, 2075 /* bits */ 32, 2076 /* flags */ 0, 2077 }, 2078 #endif /* chips */ 2079 2080 #if defined(BCM_56670_A0) 2081 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_00_BCM56670_A0fmt */ 2082 /* format DESCRIPTOR_RX_00fmt */ 2083 /* nFields */ 1, 2084 /* *fields */ soc_DESCRIPTOR_RX_00_BCM53400_A0fmt_fields, 2085 /* bits */ 32, 2086 /* flags */ 0, 2087 }, 2088 #endif /* chips */ 2089 2090 #if defined(BCM_56670_B0) 2091 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_00_BCM56670_B0fmt */ 2092 /* format DESCRIPTOR_RX_00fmt */ 2093 /* nFields */ 1, 2094 /* *fields */ soc_DESCRIPTOR_RX_00_BCM53400_A0fmt_fields, 2095 /* bits */ 32, 2096 /* flags */ 0, 2097 }, 2098 #endif /* chips */ 2099 2100 #if defined(BCM_56770_A0) 2101 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_00_BCM56770_A0fmt */ 2102 /* format DESCRIPTOR_RX_00fmt */ 2103 /* nFields */ 1, 2104 /* *fields */ soc_DESCRIPTOR_RX_00_BCM53400_A0fmt_fields, 2105 /* bits */ 32, 2106 /* flags */ 0, 2107 }, 2108 #endif /* chips */ 2109 2110 #if defined(BCM_56800_A0) 2111 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_00_BCM56800_A0fmt */ 2112 /* format DESCRIPTOR_RX_00fmt */ 2113 /* nFields */ 1, 2114 /* *fields */ soc_DESCRIPTOR_RX_00fmt_fields, 2115 /* bits */ 32, 2116 /* flags */ 0, 2117 }, 2118 #endif /* chips */ 2119 2120 #if defined(BCM_56850_A0) 2121 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_00_BCM56850_A0fmt */ 2122 /* format DESCRIPTOR_RX_00fmt */ 2123 /* nFields */ 1, 2124 /* *fields */ soc_DESCRIPTOR_RX_00_BCM56640_A0fmt_fields, 2125 /* bits */ 32, 2126 /* flags */ 0, 2127 }, 2128 #endif /* chips */ 2129 2130 #if defined(BCM_56860_A0) 2131 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_00_BCM56860_A0fmt */ 2132 /* format DESCRIPTOR_RX_00fmt */ 2133 /* nFields */ 1, 2134 /* *fields */ soc_DESCRIPTOR_RX_00_BCM56640_A0fmt_fields, 2135 /* bits */ 32, 2136 /* flags */ 0, 2137 }, 2138 #endif /* chips */ 2139 2140 #if defined(BCM_56870_A0) 2141 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_00_BCM56870_A0fmt */ 2142 /* format DESCRIPTOR_RX_00fmt */ 2143 /* nFields */ 1, 2144 /* *fields */ soc_DESCRIPTOR_RX_00_BCM53400_A0fmt_fields, 2145 /* bits */ 32, 2146 /* flags */ 0, 2147 }, 2148 #endif /* chips */ 2149 2150 #if defined(BCM_56960_A0) 2151 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_00_BCM56960_A0fmt */ 2152 /* format DESCRIPTOR_RX_00fmt */ 2153 /* nFields */ 1, 2154 /* *fields */ soc_DESCRIPTOR_RX_00_BCM53400_A0fmt_fields, 2155 /* bits */ 32, 2156 /* flags */ 0, 2157 }, 2158 #endif /* chips */ 2159 2160 #if defined(BCM_56965_A0) 2161 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_00_BCM56965_A0fmt */ 2162 /* format DESCRIPTOR_RX_00fmt */ 2163 /* nFields */ 1, 2164 /* *fields */ soc_DESCRIPTOR_RX_00_BCM53400_A0fmt_fields, 2165 /* bits */ 32, 2166 /* flags */ 0, 2167 }, 2168 #endif /* chips */ 2169 2170 #if defined(BCM_56970_A0) 2171 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_00_BCM56970_A0fmt */ 2172 /* format DESCRIPTOR_RX_00fmt */ 2173 /* nFields */ 1, 2174 /* *fields */ soc_DESCRIPTOR_RX_00_BCM53400_A0fmt_fields, 2175 /* bits */ 32, 2176 /* flags */ 0, 2177 }, 2178 #endif /* chips */ 2179 2180 #if defined(BCM_56980_A0) 2181 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_00_BCM56980_A0fmt */ 2182 /* format DESCRIPTOR_RX_00fmt */ 2183 /* nFields */ 1, 2184 /* *fields */ soc_DESCRIPTOR_RX_00_BCM53400_A0fmt_fields, 2185 /* bits */ 32, 2186 /* flags */ 0, 2187 }, 2188 #endif /* chips */ 2189 2190 #if defined(BCM_56980_B0) 2191 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_00_BCM56980_B0fmt */ 2192 /* format DESCRIPTOR_RX_00fmt */ 2193 /* nFields */ 1, 2194 /* *fields */ soc_DESCRIPTOR_RX_00_BCM53400_A0fmt_fields, 2195 /* bits */ 32, 2196 /* flags */ 0, 2197 }, 2198 #endif /* chips */ 2199 2200 #if defined(BCM_53400_A0) 2201 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_01_BCM53400_A0fmt */ 2202 /* format DESCRIPTOR_RX_01fmt */ 2203 /* nFields */ 5, 2204 /* *fields */ soc_DESCRIPTOR_RX_01_BCM53400_A0fmt_fields, 2205 /* bits */ 25, 2206 /* flags */ 0, 2207 }, 2208 #endif /* chips */ 2209 2210 #if defined(BCM_53540_A0) 2211 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_01_BCM53540_A0fmt */ 2212 /* format DESCRIPTOR_RX_01fmt */ 2213 /* nFields */ 5, 2214 /* *fields */ soc_DESCRIPTOR_RX_01_BCM53400_A0fmt_fields, 2215 /* bits */ 25, 2216 /* flags */ 0, 2217 }, 2218 #endif /* chips */ 2219 2220 #if defined(BCM_53570_A0) 2221 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_01_BCM53570_A0fmt */ 2222 /* format DESCRIPTOR_RX_01fmt */ 2223 /* nFields */ 5, 2224 /* *fields */ soc_DESCRIPTOR_RX_01_BCM53400_A0fmt_fields, 2225 /* bits */ 25, 2226 /* flags */ 0, 2227 }, 2228 #endif /* chips */ 2229 2230 #if defined(BCM_53570_B0) 2231 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_01_BCM53570_B0fmt */ 2232 /* format DESCRIPTOR_RX_01fmt */ 2233 /* nFields */ 5, 2234 /* *fields */ soc_DESCRIPTOR_RX_01_BCM53400_A0fmt_fields, 2235 /* bits */ 25, 2236 /* flags */ 0, 2237 }, 2238 #endif /* chips */ 2239 2240 #if defined(BCM_56150_A0) 2241 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_01_BCM56150_A0fmt */ 2242 /* format DESCRIPTOR_RX_01fmt */ 2243 /* nFields */ 4, 2244 /* *fields */ soc_DESCRIPTOR_RX_01_BCM56640_A0fmt_fields, 2245 /* bits */ 19, 2246 /* flags */ 0, 2247 }, 2248 #endif /* chips */ 2249 2250 #if defined(BCM_56160_A0) 2251 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_01_BCM56160_A0fmt */ 2252 /* format DESCRIPTOR_RX_01fmt */ 2253 /* nFields */ 5, 2254 /* *fields */ soc_DESCRIPTOR_RX_01_BCM53400_A0fmt_fields, 2255 /* bits */ 25, 2256 /* flags */ 0, 2257 }, 2258 #endif /* chips */ 2259 2260 #if defined(BCM_56260_A0) 2261 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_01_BCM56260_A0fmt */ 2262 /* format DESCRIPTOR_RX_01fmt */ 2263 /* nFields */ 5, 2264 /* *fields */ soc_DESCRIPTOR_RX_01_BCM53400_A0fmt_fields, 2265 /* bits */ 25, 2266 /* flags */ 0, 2267 }, 2268 #endif /* chips */ 2269 2270 #if defined(BCM_56260_B0) 2271 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_01_BCM56260_B0fmt */ 2272 /* format DESCRIPTOR_RX_01fmt */ 2273 /* nFields */ 5, 2274 /* *fields */ soc_DESCRIPTOR_RX_01_BCM53400_A0fmt_fields, 2275 /* bits */ 25, 2276 /* flags */ 0, 2277 }, 2278 #endif /* chips */ 2279 2280 #if defined(BCM_56270_A0) 2281 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_01_BCM56270_A0fmt */ 2282 /* format DESCRIPTOR_RX_01fmt */ 2283 /* nFields */ 5, 2284 /* *fields */ soc_DESCRIPTOR_RX_01_BCM53400_A0fmt_fields, 2285 /* bits */ 25, 2286 /* flags */ 0, 2287 }, 2288 #endif /* chips */ 2289 2290 #if defined(BCM_56340_A0) 2291 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_01_BCM56340_A0fmt */ 2292 /* format DESCRIPTOR_RX_01fmt */ 2293 /* nFields */ 4, 2294 /* *fields */ soc_DESCRIPTOR_RX_01_BCM56640_A0fmt_fields, 2295 /* bits */ 19, 2296 /* flags */ 0, 2297 }, 2298 #endif /* chips */ 2299 2300 #if defined(BCM_56370_A0) 2301 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_01_BCM56370_A0fmt */ 2302 /* format DESCRIPTOR_RX_01fmt */ 2303 /* nFields */ 1, 2304 /* *fields */ soc_DESCRIPTOR_RX_01_BCM56870_A0fmt_fields, 2305 /* bits */ 32, 2306 /* flags */ 0, 2307 }, 2308 #endif /* chips */ 2309 2310 #if defined(BCM_56450_A0) 2311 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_01_BCM56450_A0fmt */ 2312 /* format DESCRIPTOR_RX_01fmt */ 2313 /* nFields */ 4, 2314 /* *fields */ soc_DESCRIPTOR_RX_01_BCM56640_A0fmt_fields, 2315 /* bits */ 19, 2316 /* flags */ 0, 2317 }, 2318 #endif /* chips */ 2319 2320 #if defined(BCM_56450_B0) 2321 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_01_BCM56450_B0fmt */ 2322 /* format DESCRIPTOR_RX_01fmt */ 2323 /* nFields */ 4, 2324 /* *fields */ soc_DESCRIPTOR_RX_01_BCM56640_A0fmt_fields, 2325 /* bits */ 19, 2326 /* flags */ 0, 2327 }, 2328 #endif /* chips */ 2329 2330 #if defined(BCM_56450_B1) 2331 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_01_BCM56450_B1fmt */ 2332 /* format DESCRIPTOR_RX_01fmt */ 2333 /* nFields */ 4, 2334 /* *fields */ soc_DESCRIPTOR_RX_01_BCM56640_A0fmt_fields, 2335 /* bits */ 19, 2336 /* flags */ 0, 2337 }, 2338 #endif /* chips */ 2339 2340 #if defined(BCM_56560_A0) 2341 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_01_BCM56560_A0fmt */ 2342 /* format DESCRIPTOR_RX_01fmt */ 2343 /* nFields */ 5, 2344 /* *fields */ soc_DESCRIPTOR_RX_01_BCM53400_A0fmt_fields, 2345 /* bits */ 25, 2346 /* flags */ 0, 2347 }, 2348 #endif /* chips */ 2349 2350 #if defined(BCM_56560_B0) 2351 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_01_BCM56560_B0fmt */ 2352 /* format DESCRIPTOR_RX_01fmt */ 2353 /* nFields */ 5, 2354 /* *fields */ soc_DESCRIPTOR_RX_01_BCM53400_A0fmt_fields, 2355 /* bits */ 25, 2356 /* flags */ 0, 2357 }, 2358 #endif /* chips */ 2359 2360 #if defined(BCM_56640_A0) 2361 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_01_BCM56640_A0fmt */ 2362 /* format DESCRIPTOR_RX_01fmt */ 2363 /* nFields */ 4, 2364 /* *fields */ soc_DESCRIPTOR_RX_01_BCM56640_A0fmt_fields, 2365 /* bits */ 19, 2366 /* flags */ 0, 2367 }, 2368 #endif /* chips */ 2369 2370 #if defined(BCM_56670_A0) 2371 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_01_BCM56670_A0fmt */ 2372 /* format DESCRIPTOR_RX_01fmt */ 2373 /* nFields */ 5, 2374 /* *fields */ soc_DESCRIPTOR_RX_01_BCM53400_A0fmt_fields, 2375 /* bits */ 25, 2376 /* flags */ 0, 2377 }, 2378 #endif /* chips */ 2379 2380 #if defined(BCM_56670_B0) 2381 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_01_BCM56670_B0fmt */ 2382 /* format DESCRIPTOR_RX_01fmt */ 2383 /* nFields */ 5, 2384 /* *fields */ soc_DESCRIPTOR_RX_01_BCM53400_A0fmt_fields, 2385 /* bits */ 25, 2386 /* flags */ 0, 2387 }, 2388 #endif /* chips */ 2389 2390 #if defined(BCM_56770_A0) 2391 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_01_BCM56770_A0fmt */ 2392 /* format DESCRIPTOR_RX_01fmt */ 2393 /* nFields */ 1, 2394 /* *fields */ soc_DESCRIPTOR_RX_01_BCM56870_A0fmt_fields, 2395 /* bits */ 32, 2396 /* flags */ 0, 2397 }, 2398 #endif /* chips */ 2399 2400 #if defined(BCM_56800_A0) 2401 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_01_BCM56800_A0fmt */ 2402 /* format DESCRIPTOR_RX_01fmt */ 2403 /* nFields */ 4, 2404 /* *fields */ soc_DESCRIPTOR_RX_01fmt_fields, 2405 /* bits */ 19, 2406 /* flags */ 0, 2407 }, 2408 #endif /* chips */ 2409 2410 #if defined(BCM_56850_A0) 2411 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_01_BCM56850_A0fmt */ 2412 /* format DESCRIPTOR_RX_01fmt */ 2413 /* nFields */ 4, 2414 /* *fields */ soc_DESCRIPTOR_RX_01_BCM56640_A0fmt_fields, 2415 /* bits */ 19, 2416 /* flags */ 0, 2417 }, 2418 #endif /* chips */ 2419 2420 #if defined(BCM_56860_A0) 2421 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_01_BCM56860_A0fmt */ 2422 /* format DESCRIPTOR_RX_01fmt */ 2423 /* nFields */ 4, 2424 /* *fields */ soc_DESCRIPTOR_RX_01_BCM56640_A0fmt_fields, 2425 /* bits */ 19, 2426 /* flags */ 0, 2427 }, 2428 #endif /* chips */ 2429 2430 #if defined(BCM_56870_A0) 2431 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_01_BCM56870_A0fmt */ 2432 /* format DESCRIPTOR_RX_01fmt */ 2433 /* nFields */ 1, 2434 /* *fields */ soc_DESCRIPTOR_RX_01_BCM56870_A0fmt_fields, 2435 /* bits */ 32, 2436 /* flags */ 0, 2437 }, 2438 #endif /* chips */ 2439 2440 #if defined(BCM_56960_A0) 2441 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_01_BCM56960_A0fmt */ 2442 /* format DESCRIPTOR_RX_01fmt */ 2443 /* nFields */ 5, 2444 /* *fields */ soc_DESCRIPTOR_RX_01_BCM53400_A0fmt_fields, 2445 /* bits */ 25, 2446 /* flags */ 0, 2447 }, 2448 #endif /* chips */ 2449 2450 #if defined(BCM_56965_A0) 2451 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_01_BCM56965_A0fmt */ 2452 /* format DESCRIPTOR_RX_01fmt */ 2453 /* nFields */ 5, 2454 /* *fields */ soc_DESCRIPTOR_RX_01_BCM53400_A0fmt_fields, 2455 /* bits */ 25, 2456 /* flags */ 0, 2457 }, 2458 #endif /* chips */ 2459 2460 #if defined(BCM_56970_A0) 2461 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_01_BCM56970_A0fmt */ 2462 /* format DESCRIPTOR_RX_01fmt */ 2463 /* nFields */ 5, 2464 /* *fields */ soc_DESCRIPTOR_RX_01_BCM53400_A0fmt_fields, 2465 /* bits */ 25, 2466 /* flags */ 0, 2467 }, 2468 #endif /* chips */ 2469 2470 #if defined(BCM_56980_A0) 2471 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_01_BCM56980_A0fmt */ 2472 /* format DESCRIPTOR_RX_01fmt */ 2473 /* nFields */ 1, 2474 /* *fields */ soc_DESCRIPTOR_RX_01_BCM56870_A0fmt_fields, 2475 /* bits */ 32, 2476 /* flags */ 0, 2477 }, 2478 #endif /* chips */ 2479 2480 #if defined(BCM_56980_B0) 2481 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_01_BCM56980_B0fmt */ 2482 /* format DESCRIPTOR_RX_01fmt */ 2483 /* nFields */ 1, 2484 /* *fields */ soc_DESCRIPTOR_RX_01_BCM56870_A0fmt_fields, 2485 /* bits */ 32, 2486 /* flags */ 0, 2487 }, 2488 #endif /* chips */ 2489 2490 #if defined(BCM_53400_A0) 2491 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_02_BCM53400_A0fmt */ 2492 /* format DESCRIPTOR_RX_02fmt */ 2493 /* nFields */ 1, 2494 /* *fields */ soc_DESCRIPTOR_RX_02_BCM53400_A0fmt_fields, 2495 /* bits */ 32, 2496 /* flags */ 0, 2497 }, 2498 #endif /* chips */ 2499 2500 #if defined(BCM_53540_A0) 2501 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_02_BCM53540_A0fmt */ 2502 /* format DESCRIPTOR_RX_02fmt */ 2503 /* nFields */ 1, 2504 /* *fields */ soc_DESCRIPTOR_RX_02_BCM53400_A0fmt_fields, 2505 /* bits */ 32, 2506 /* flags */ 0, 2507 }, 2508 #endif /* chips */ 2509 2510 #if defined(BCM_53570_A0) 2511 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_02_BCM53570_A0fmt */ 2512 /* format DESCRIPTOR_RX_02fmt */ 2513 /* nFields */ 1, 2514 /* *fields */ soc_DESCRIPTOR_RX_02_BCM53400_A0fmt_fields, 2515 /* bits */ 32, 2516 /* flags */ 0, 2517 }, 2518 #endif /* chips */ 2519 2520 #if defined(BCM_53570_B0) 2521 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_02_BCM53570_B0fmt */ 2522 /* format DESCRIPTOR_RX_02fmt */ 2523 /* nFields */ 1, 2524 /* *fields */ soc_DESCRIPTOR_RX_02_BCM53400_A0fmt_fields, 2525 /* bits */ 32, 2526 /* flags */ 0, 2527 }, 2528 #endif /* chips */ 2529 2530 #if defined(BCM_56142_A0) 2531 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_02_BCM56142_A0fmt */ 2532 /* format DESCRIPTOR_RX_02fmt */ 2533 /* nFields */ 1, 2534 /* *fields */ soc_DESCRIPTOR_RX_02_BCM56624_A0fmt_fields, 2535 /* bits */ 32, 2536 /* flags */ 0, 2537 }, 2538 #endif /* chips */ 2539 2540 #if defined(BCM_56150_A0) 2541 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_02_BCM56150_A0fmt */ 2542 /* format DESCRIPTOR_RX_02fmt */ 2543 /* nFields */ 1, 2544 /* *fields */ soc_DESCRIPTOR_RX_02_BCM56640_A0fmt_fields, 2545 /* bits */ 32, 2546 /* flags */ 0, 2547 }, 2548 #endif /* chips */ 2549 2550 #if defined(BCM_56160_A0) 2551 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_02_BCM56160_A0fmt */ 2552 /* format DESCRIPTOR_RX_02fmt */ 2553 /* nFields */ 1, 2554 /* *fields */ soc_DESCRIPTOR_RX_02_BCM53400_A0fmt_fields, 2555 /* bits */ 32, 2556 /* flags */ 0, 2557 }, 2558 #endif /* chips */ 2559 2560 #if defined(BCM_56260_A0) 2561 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_02_BCM56260_A0fmt */ 2562 /* format DESCRIPTOR_RX_02fmt */ 2563 /* nFields */ 1, 2564 /* *fields */ soc_DESCRIPTOR_RX_02_BCM53400_A0fmt_fields, 2565 /* bits */ 32, 2566 /* flags */ 0, 2567 }, 2568 #endif /* chips */ 2569 2570 #if defined(BCM_56260_B0) 2571 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_02_BCM56260_B0fmt */ 2572 /* format DESCRIPTOR_RX_02fmt */ 2573 /* nFields */ 1, 2574 /* *fields */ soc_DESCRIPTOR_RX_02_BCM53400_A0fmt_fields, 2575 /* bits */ 32, 2576 /* flags */ 0, 2577 }, 2578 #endif /* chips */ 2579 2580 #if defined(BCM_56270_A0) 2581 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_02_BCM56270_A0fmt */ 2582 /* format DESCRIPTOR_RX_02fmt */ 2583 /* nFields */ 1, 2584 /* *fields */ soc_DESCRIPTOR_RX_02_BCM53400_A0fmt_fields, 2585 /* bits */ 32, 2586 /* flags */ 0, 2587 }, 2588 #endif /* chips */ 2589 2590 #if defined(BCM_56334_A0) 2591 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_02_BCM56334_A0fmt */ 2592 /* format DESCRIPTOR_RX_02fmt */ 2593 /* nFields */ 1, 2594 /* *fields */ soc_DESCRIPTOR_RX_02_BCM56624_A0fmt_fields, 2595 /* bits */ 32, 2596 /* flags */ 0, 2597 }, 2598 #endif /* chips */ 2599 2600 #if defined(BCM_56334_B0) 2601 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_02_BCM56334_B0fmt */ 2602 /* format DESCRIPTOR_RX_02fmt */ 2603 /* nFields */ 1, 2604 /* *fields */ soc_DESCRIPTOR_RX_02_BCM56624_A0fmt_fields, 2605 /* bits */ 32, 2606 /* flags */ 0, 2607 }, 2608 #endif /* chips */ 2609 2610 #if defined(BCM_56340_A0) 2611 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_02_BCM56340_A0fmt */ 2612 /* format DESCRIPTOR_RX_02fmt */ 2613 /* nFields */ 1, 2614 /* *fields */ soc_DESCRIPTOR_RX_02_BCM56640_A0fmt_fields, 2615 /* bits */ 32, 2616 /* flags */ 0, 2617 }, 2618 #endif /* chips */ 2619 2620 #if defined(BCM_56370_A0) 2621 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_02_BCM56370_A0fmt */ 2622 /* format DESCRIPTOR_RX_02fmt */ 2623 /* nFields */ 7, 2624 /* *fields */ soc_DESCRIPTOR_RX_02_BCM56870_A0fmt_fields, 2625 /* bits */ 30, 2626 /* flags */ 0, 2627 }, 2628 #endif /* chips */ 2629 2630 #if defined(BCM_56440_A0) 2631 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_02_BCM56440_A0fmt */ 2632 /* format DESCRIPTOR_RX_02fmt */ 2633 /* nFields */ 1, 2634 /* *fields */ soc_DESCRIPTOR_RX_02_BCM56624_A0fmt_fields, 2635 /* bits */ 32, 2636 /* flags */ 0, 2637 }, 2638 #endif /* chips */ 2639 2640 #if defined(BCM_56440_B0) 2641 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_02_BCM56440_B0fmt */ 2642 /* format DESCRIPTOR_RX_02fmt */ 2643 /* nFields */ 1, 2644 /* *fields */ soc_DESCRIPTOR_RX_02_BCM56624_A0fmt_fields, 2645 /* bits */ 32, 2646 /* flags */ 0, 2647 }, 2648 #endif /* chips */ 2649 2650 #if defined(BCM_56450_A0) 2651 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_02_BCM56450_A0fmt */ 2652 /* format DESCRIPTOR_RX_02fmt */ 2653 /* nFields */ 1, 2654 /* *fields */ soc_DESCRIPTOR_RX_02_BCM56640_A0fmt_fields, 2655 /* bits */ 32, 2656 /* flags */ 0, 2657 }, 2658 #endif /* chips */ 2659 2660 #if defined(BCM_56450_B0) 2661 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_02_BCM56450_B0fmt */ 2662 /* format DESCRIPTOR_RX_02fmt */ 2663 /* nFields */ 1, 2664 /* *fields */ soc_DESCRIPTOR_RX_02_BCM56640_A0fmt_fields, 2665 /* bits */ 32, 2666 /* flags */ 0, 2667 }, 2668 #endif /* chips */ 2669 2670 #if defined(BCM_56450_B1) 2671 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_02_BCM56450_B1fmt */ 2672 /* format DESCRIPTOR_RX_02fmt */ 2673 /* nFields */ 1, 2674 /* *fields */ soc_DESCRIPTOR_RX_02_BCM56640_A0fmt_fields, 2675 /* bits */ 32, 2676 /* flags */ 0, 2677 }, 2678 #endif /* chips */ 2679 2680 #if defined(BCM_56524_A0) 2681 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_02_BCM56524_A0fmt */ 2682 /* format DESCRIPTOR_RX_02fmt */ 2683 /* nFields */ 1, 2684 /* *fields */ soc_DESCRIPTOR_RX_02_BCM56624_A0fmt_fields, 2685 /* bits */ 32, 2686 /* flags */ 0, 2687 }, 2688 #endif /* chips */ 2689 2690 #if defined(BCM_56524_B0) 2691 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_02_BCM56524_B0fmt */ 2692 /* format DESCRIPTOR_RX_02fmt */ 2693 /* nFields */ 1, 2694 /* *fields */ soc_DESCRIPTOR_RX_02_BCM56624_A0fmt_fields, 2695 /* bits */ 32, 2696 /* flags */ 0, 2697 }, 2698 #endif /* chips */ 2699 2700 #if defined(BCM_56560_A0) 2701 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_02_BCM56560_A0fmt */ 2702 /* format DESCRIPTOR_RX_02fmt */ 2703 /* nFields */ 1, 2704 /* *fields */ soc_DESCRIPTOR_RX_02_BCM53400_A0fmt_fields, 2705 /* bits */ 32, 2706 /* flags */ 0, 2707 }, 2708 #endif /* chips */ 2709 2710 #if defined(BCM_56560_B0) 2711 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_02_BCM56560_B0fmt */ 2712 /* format DESCRIPTOR_RX_02fmt */ 2713 /* nFields */ 1, 2714 /* *fields */ soc_DESCRIPTOR_RX_02_BCM53400_A0fmt_fields, 2715 /* bits */ 32, 2716 /* flags */ 0, 2717 }, 2718 #endif /* chips */ 2719 2720 #if defined(BCM_56624_A0) 2721 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_02_BCM56624_A0fmt */ 2722 /* format DESCRIPTOR_RX_02fmt */ 2723 /* nFields */ 1, 2724 /* *fields */ soc_DESCRIPTOR_RX_02_BCM56624_A0fmt_fields, 2725 /* bits */ 32, 2726 /* flags */ 0, 2727 }, 2728 #endif /* chips */ 2729 2730 #if defined(BCM_56624_B0) 2731 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_02_BCM56624_B0fmt */ 2732 /* format DESCRIPTOR_RX_02fmt */ 2733 /* nFields */ 1, 2734 /* *fields */ soc_DESCRIPTOR_RX_02_BCM56624_A0fmt_fields, 2735 /* bits */ 32, 2736 /* flags */ 0, 2737 }, 2738 #endif /* chips */ 2739 2740 #if defined(BCM_56634_A0) 2741 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_02_BCM56634_A0fmt */ 2742 /* format DESCRIPTOR_RX_02fmt */ 2743 /* nFields */ 1, 2744 /* *fields */ soc_DESCRIPTOR_RX_02_BCM56624_A0fmt_fields, 2745 /* bits */ 32, 2746 /* flags */ 0, 2747 }, 2748 #endif /* chips */ 2749 2750 #if defined(BCM_56634_B0) 2751 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_02_BCM56634_B0fmt */ 2752 /* format DESCRIPTOR_RX_02fmt */ 2753 /* nFields */ 1, 2754 /* *fields */ soc_DESCRIPTOR_RX_02_BCM56624_A0fmt_fields, 2755 /* bits */ 32, 2756 /* flags */ 0, 2757 }, 2758 #endif /* chips */ 2759 2760 #if defined(BCM_56640_A0) 2761 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_02_BCM56640_A0fmt */ 2762 /* format DESCRIPTOR_RX_02fmt */ 2763 /* nFields */ 1, 2764 /* *fields */ soc_DESCRIPTOR_RX_02_BCM56640_A0fmt_fields, 2765 /* bits */ 32, 2766 /* flags */ 0, 2767 }, 2768 #endif /* chips */ 2769 2770 #if defined(BCM_56670_A0) 2771 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_02_BCM56670_A0fmt */ 2772 /* format DESCRIPTOR_RX_02fmt */ 2773 /* nFields */ 1, 2774 /* *fields */ soc_DESCRIPTOR_RX_02_BCM53400_A0fmt_fields, 2775 /* bits */ 32, 2776 /* flags */ 0, 2777 }, 2778 #endif /* chips */ 2779 2780 #if defined(BCM_56670_B0) 2781 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_02_BCM56670_B0fmt */ 2782 /* format DESCRIPTOR_RX_02fmt */ 2783 /* nFields */ 1, 2784 /* *fields */ soc_DESCRIPTOR_RX_02_BCM53400_A0fmt_fields, 2785 /* bits */ 32, 2786 /* flags */ 0, 2787 }, 2788 #endif /* chips */ 2789 2790 #if defined(BCM_56680_A0) 2791 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_02_BCM56680_A0fmt */ 2792 /* format DESCRIPTOR_RX_02fmt */ 2793 /* nFields */ 1, 2794 /* *fields */ soc_DESCRIPTOR_RX_02_BCM56624_A0fmt_fields, 2795 /* bits */ 32, 2796 /* flags */ 0, 2797 }, 2798 #endif /* chips */ 2799 2800 #if defined(BCM_56680_B0) 2801 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_02_BCM56680_B0fmt */ 2802 /* format DESCRIPTOR_RX_02fmt */ 2803 /* nFields */ 1, 2804 /* *fields */ soc_DESCRIPTOR_RX_02_BCM56624_A0fmt_fields, 2805 /* bits */ 32, 2806 /* flags */ 0, 2807 }, 2808 #endif /* chips */ 2809 2810 #if defined(BCM_56685_A0) 2811 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_02_BCM56685_A0fmt */ 2812 /* format DESCRIPTOR_RX_02fmt */ 2813 /* nFields */ 1, 2814 /* *fields */ soc_DESCRIPTOR_RX_02_BCM56624_A0fmt_fields, 2815 /* bits */ 32, 2816 /* flags */ 0, 2817 }, 2818 #endif /* chips */ 2819 2820 #if defined(BCM_56685_B0) 2821 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_02_BCM56685_B0fmt */ 2822 /* format DESCRIPTOR_RX_02fmt */ 2823 /* nFields */ 1, 2824 /* *fields */ soc_DESCRIPTOR_RX_02_BCM56624_A0fmt_fields, 2825 /* bits */ 32, 2826 /* flags */ 0, 2827 }, 2828 #endif /* chips */ 2829 2830 #if defined(BCM_56725_A0) 2831 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_02_BCM56725_A0fmt */ 2832 /* format DESCRIPTOR_RX_02fmt */ 2833 /* nFields */ 1, 2834 /* *fields */ soc_DESCRIPTOR_RX_02_BCM56624_A0fmt_fields, 2835 /* bits */ 32, 2836 /* flags */ 0, 2837 }, 2838 #endif /* chips */ 2839 2840 #if defined(BCM_56770_A0) 2841 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_02_BCM56770_A0fmt */ 2842 /* format DESCRIPTOR_RX_02fmt */ 2843 /* nFields */ 7, 2844 /* *fields */ soc_DESCRIPTOR_RX_02_BCM56870_A0fmt_fields, 2845 /* bits */ 30, 2846 /* flags */ 0, 2847 }, 2848 #endif /* chips */ 2849 2850 #if defined(BCM_56800_A0) 2851 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_02_BCM56800_A0fmt */ 2852 /* format DESCRIPTOR_RX_02fmt */ 2853 /* nFields */ 1, 2854 /* *fields */ soc_DESCRIPTOR_RX_02fmt_fields, 2855 /* bits */ 32, 2856 /* flags */ 0, 2857 }, 2858 #endif /* chips */ 2859 2860 #if defined(BCM_56820_A0) 2861 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_02_BCM56820_A0fmt */ 2862 /* format DESCRIPTOR_RX_02fmt */ 2863 /* nFields */ 1, 2864 /* *fields */ soc_DESCRIPTOR_RX_02_BCM56624_A0fmt_fields, 2865 /* bits */ 32, 2866 /* flags */ 0, 2867 }, 2868 #endif /* chips */ 2869 2870 #if defined(BCM_56840_A0) 2871 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_02_BCM56840_A0fmt */ 2872 /* format DESCRIPTOR_RX_02fmt */ 2873 /* nFields */ 1, 2874 /* *fields */ soc_DESCRIPTOR_RX_02_BCM56624_A0fmt_fields, 2875 /* bits */ 32, 2876 /* flags */ 0, 2877 }, 2878 #endif /* chips */ 2879 2880 #if defined(BCM_56840_B0) 2881 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_02_BCM56840_B0fmt */ 2882 /* format DESCRIPTOR_RX_02fmt */ 2883 /* nFields */ 1, 2884 /* *fields */ soc_DESCRIPTOR_RX_02_BCM56624_A0fmt_fields, 2885 /* bits */ 32, 2886 /* flags */ 0, 2887 }, 2888 #endif /* chips */ 2889 2890 #if defined(BCM_56850_A0) 2891 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_02_BCM56850_A0fmt */ 2892 /* format DESCRIPTOR_RX_02fmt */ 2893 /* nFields */ 1, 2894 /* *fields */ soc_DESCRIPTOR_RX_02_BCM56640_A0fmt_fields, 2895 /* bits */ 32, 2896 /* flags */ 0, 2897 }, 2898 #endif /* chips */ 2899 2900 #if defined(BCM_56860_A0) 2901 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_02_BCM56860_A0fmt */ 2902 /* format DESCRIPTOR_RX_02fmt */ 2903 /* nFields */ 1, 2904 /* *fields */ soc_DESCRIPTOR_RX_02_BCM56640_A0fmt_fields, 2905 /* bits */ 32, 2906 /* flags */ 0, 2907 }, 2908 #endif /* chips */ 2909 2910 #if defined(BCM_56870_A0) 2911 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_02_BCM56870_A0fmt */ 2912 /* format DESCRIPTOR_RX_02fmt */ 2913 /* nFields */ 7, 2914 /* *fields */ soc_DESCRIPTOR_RX_02_BCM56870_A0fmt_fields, 2915 /* bits */ 30, 2916 /* flags */ 0, 2917 }, 2918 #endif /* chips */ 2919 2920 #if defined(BCM_56960_A0) 2921 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_02_BCM56960_A0fmt */ 2922 /* format DESCRIPTOR_RX_02fmt */ 2923 /* nFields */ 1, 2924 /* *fields */ soc_DESCRIPTOR_RX_02_BCM53400_A0fmt_fields, 2925 /* bits */ 32, 2926 /* flags */ 0, 2927 }, 2928 #endif /* chips */ 2929 2930 #if defined(BCM_56965_A0) 2931 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_02_BCM56965_A0fmt */ 2932 /* format DESCRIPTOR_RX_02fmt */ 2933 /* nFields */ 1, 2934 /* *fields */ soc_DESCRIPTOR_RX_02_BCM53400_A0fmt_fields, 2935 /* bits */ 32, 2936 /* flags */ 0, 2937 }, 2938 #endif /* chips */ 2939 2940 #if defined(BCM_56970_A0) 2941 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_02_BCM56970_A0fmt */ 2942 /* format DESCRIPTOR_RX_02fmt */ 2943 /* nFields */ 1, 2944 /* *fields */ soc_DESCRIPTOR_RX_02_BCM53400_A0fmt_fields, 2945 /* bits */ 32, 2946 /* flags */ 0, 2947 }, 2948 #endif /* chips */ 2949 2950 #if defined(BCM_56980_A0) 2951 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_02_BCM56980_A0fmt */ 2952 /* format DESCRIPTOR_RX_02fmt */ 2953 /* nFields */ 7, 2954 /* *fields */ soc_DESCRIPTOR_RX_02_BCM56870_A0fmt_fields, 2955 /* bits */ 30, 2956 /* flags */ 0, 2957 }, 2958 #endif /* chips */ 2959 2960 #if defined(BCM_56980_B0) 2961 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_02_BCM56980_B0fmt */ 2962 /* format DESCRIPTOR_RX_02fmt */ 2963 /* nFields */ 7, 2964 /* *fields */ soc_DESCRIPTOR_RX_02_BCM56870_A0fmt_fields, 2965 /* bits */ 30, 2966 /* flags */ 0, 2967 }, 2968 #endif /* chips */ 2969 2970 #if defined(BCM_88732_A0) 2971 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_02_BCM88732_A0fmt */ 2972 /* format DESCRIPTOR_RX_02fmt */ 2973 /* nFields */ 1, 2974 /* *fields */ soc_DESCRIPTOR_RX_02_BCM56624_A0fmt_fields, 2975 /* bits */ 32, 2976 /* flags */ 0, 2977 }, 2978 #endif /* chips */ 2979 2980 #if defined(BCM_53400_A0) 2981 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_03_BCM53400_A0fmt */ 2982 /* format DESCRIPTOR_RX_03fmt */ 2983 /* nFields */ 1, 2984 /* *fields */ soc_DESCRIPTOR_RX_03_BCM53400_A0fmt_fields, 2985 /* bits */ 32, 2986 /* flags */ 0, 2987 }, 2988 #endif /* chips */ 2989 2990 #if defined(BCM_53540_A0) 2991 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_03_BCM53540_A0fmt */ 2992 /* format DESCRIPTOR_RX_03fmt */ 2993 /* nFields */ 1, 2994 /* *fields */ soc_DESCRIPTOR_RX_03_BCM53400_A0fmt_fields, 2995 /* bits */ 32, 2996 /* flags */ 0, 2997 }, 2998 #endif /* chips */ 2999 3000 #if defined(BCM_53570_A0) 3001 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_03_BCM53570_A0fmt */ 3002 /* format DESCRIPTOR_RX_03fmt */ 3003 /* nFields */ 1, 3004 /* *fields */ soc_DESCRIPTOR_RX_03_BCM53400_A0fmt_fields, 3005 /* bits */ 32, 3006 /* flags */ 0, 3007 }, 3008 #endif /* chips */ 3009 3010 #if defined(BCM_53570_B0) 3011 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_03_BCM53570_B0fmt */ 3012 /* format DESCRIPTOR_RX_03fmt */ 3013 /* nFields */ 1, 3014 /* *fields */ soc_DESCRIPTOR_RX_03_BCM53400_A0fmt_fields, 3015 /* bits */ 32, 3016 /* flags */ 0, 3017 }, 3018 #endif /* chips */ 3019 3020 #if defined(BCM_56142_A0) 3021 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_03_BCM56142_A0fmt */ 3022 /* format DESCRIPTOR_RX_03fmt */ 3023 /* nFields */ 1, 3024 /* *fields */ soc_DESCRIPTOR_RX_03_BCM56624_A0fmt_fields, 3025 /* bits */ 32, 3026 /* flags */ 0, 3027 }, 3028 #endif /* chips */ 3029 3030 #if defined(BCM_56150_A0) 3031 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_03_BCM56150_A0fmt */ 3032 /* format DESCRIPTOR_RX_03fmt */ 3033 /* nFields */ 1, 3034 /* *fields */ soc_DESCRIPTOR_RX_03_BCM56640_A0fmt_fields, 3035 /* bits */ 32, 3036 /* flags */ 0, 3037 }, 3038 #endif /* chips */ 3039 3040 #if defined(BCM_56160_A0) 3041 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_03_BCM56160_A0fmt */ 3042 /* format DESCRIPTOR_RX_03fmt */ 3043 /* nFields */ 1, 3044 /* *fields */ soc_DESCRIPTOR_RX_03_BCM53400_A0fmt_fields, 3045 /* bits */ 32, 3046 /* flags */ 0, 3047 }, 3048 #endif /* chips */ 3049 3050 #if defined(BCM_56260_A0) 3051 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_03_BCM56260_A0fmt */ 3052 /* format DESCRIPTOR_RX_03fmt */ 3053 /* nFields */ 1, 3054 /* *fields */ soc_DESCRIPTOR_RX_03_BCM53400_A0fmt_fields, 3055 /* bits */ 32, 3056 /* flags */ 0, 3057 }, 3058 #endif /* chips */ 3059 3060 #if defined(BCM_56260_B0) 3061 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_03_BCM56260_B0fmt */ 3062 /* format DESCRIPTOR_RX_03fmt */ 3063 /* nFields */ 1, 3064 /* *fields */ soc_DESCRIPTOR_RX_03_BCM53400_A0fmt_fields, 3065 /* bits */ 32, 3066 /* flags */ 0, 3067 }, 3068 #endif /* chips */ 3069 3070 #if defined(BCM_56270_A0) 3071 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_03_BCM56270_A0fmt */ 3072 /* format DESCRIPTOR_RX_03fmt */ 3073 /* nFields */ 1, 3074 /* *fields */ soc_DESCRIPTOR_RX_03_BCM53400_A0fmt_fields, 3075 /* bits */ 32, 3076 /* flags */ 0, 3077 }, 3078 #endif /* chips */ 3079 3080 #if defined(BCM_56334_A0) 3081 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_03_BCM56334_A0fmt */ 3082 /* format DESCRIPTOR_RX_03fmt */ 3083 /* nFields */ 1, 3084 /* *fields */ soc_DESCRIPTOR_RX_03_BCM56624_A0fmt_fields, 3085 /* bits */ 32, 3086 /* flags */ 0, 3087 }, 3088 #endif /* chips */ 3089 3090 #if defined(BCM_56334_B0) 3091 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_03_BCM56334_B0fmt */ 3092 /* format DESCRIPTOR_RX_03fmt */ 3093 /* nFields */ 1, 3094 /* *fields */ soc_DESCRIPTOR_RX_03_BCM56624_A0fmt_fields, 3095 /* bits */ 32, 3096 /* flags */ 0, 3097 }, 3098 #endif /* chips */ 3099 3100 #if defined(BCM_56340_A0) 3101 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_03_BCM56340_A0fmt */ 3102 /* format DESCRIPTOR_RX_03fmt */ 3103 /* nFields */ 1, 3104 /* *fields */ soc_DESCRIPTOR_RX_03_BCM56640_A0fmt_fields, 3105 /* bits */ 32, 3106 /* flags */ 0, 3107 }, 3108 #endif /* chips */ 3109 3110 #if defined(BCM_56370_A0) 3111 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_03_BCM56370_A0fmt */ 3112 /* format DESCRIPTOR_RX_03fmt */ 3113 /* nFields */ 6, 3114 /* *fields */ soc_DESCRIPTOR_RX_03_BCM56870_A0fmt_fields, 3115 /* bits */ 32, 3116 /* flags */ 0, 3117 }, 3118 #endif /* chips */ 3119 3120 #if defined(BCM_56440_A0) 3121 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_03_BCM56440_A0fmt */ 3122 /* format DESCRIPTOR_RX_03fmt */ 3123 /* nFields */ 1, 3124 /* *fields */ soc_DESCRIPTOR_RX_03_BCM56624_A0fmt_fields, 3125 /* bits */ 32, 3126 /* flags */ 0, 3127 }, 3128 #endif /* chips */ 3129 3130 #if defined(BCM_56440_B0) 3131 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_03_BCM56440_B0fmt */ 3132 /* format DESCRIPTOR_RX_03fmt */ 3133 /* nFields */ 1, 3134 /* *fields */ soc_DESCRIPTOR_RX_03_BCM56624_A0fmt_fields, 3135 /* bits */ 32, 3136 /* flags */ 0, 3137 }, 3138 #endif /* chips */ 3139 3140 #if defined(BCM_56450_A0) 3141 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_03_BCM56450_A0fmt */ 3142 /* format DESCRIPTOR_RX_03fmt */ 3143 /* nFields */ 1, 3144 /* *fields */ soc_DESCRIPTOR_RX_03_BCM56640_A0fmt_fields, 3145 /* bits */ 32, 3146 /* flags */ 0, 3147 }, 3148 #endif /* chips */ 3149 3150 #if defined(BCM_56450_B0) 3151 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_03_BCM56450_B0fmt */ 3152 /* format DESCRIPTOR_RX_03fmt */ 3153 /* nFields */ 1, 3154 /* *fields */ soc_DESCRIPTOR_RX_03_BCM56640_A0fmt_fields, 3155 /* bits */ 32, 3156 /* flags */ 0, 3157 }, 3158 #endif /* chips */ 3159 3160 #if defined(BCM_56450_B1) 3161 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_03_BCM56450_B1fmt */ 3162 /* format DESCRIPTOR_RX_03fmt */ 3163 /* nFields */ 1, 3164 /* *fields */ soc_DESCRIPTOR_RX_03_BCM56640_A0fmt_fields, 3165 /* bits */ 32, 3166 /* flags */ 0, 3167 }, 3168 #endif /* chips */ 3169 3170 #if defined(BCM_56504_B0) 3171 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_03_BCM56504_B0fmt */ 3172 /* format DESCRIPTOR_RX_03fmt */ 3173 /* nFields */ 1, 3174 /* *fields */ soc_DESCRIPTOR_RX_03fmt_fields, 3175 /* bits */ 32, 3176 /* flags */ 0, 3177 }, 3178 #endif /* chips */ 3179 3180 #if defined(BCM_56524_A0) 3181 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_03_BCM56524_A0fmt */ 3182 /* format DESCRIPTOR_RX_03fmt */ 3183 /* nFields */ 1, 3184 /* *fields */ soc_DESCRIPTOR_RX_03_BCM56624_A0fmt_fields, 3185 /* bits */ 32, 3186 /* flags */ 0, 3187 }, 3188 #endif /* chips */ 3189 3190 #if defined(BCM_56524_B0) 3191 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_03_BCM56524_B0fmt */ 3192 /* format DESCRIPTOR_RX_03fmt */ 3193 /* nFields */ 1, 3194 /* *fields */ soc_DESCRIPTOR_RX_03_BCM56624_A0fmt_fields, 3195 /* bits */ 32, 3196 /* flags */ 0, 3197 }, 3198 #endif /* chips */ 3199 3200 #if defined(BCM_56560_A0) 3201 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_03_BCM56560_A0fmt */ 3202 /* format DESCRIPTOR_RX_03fmt */ 3203 /* nFields */ 1, 3204 /* *fields */ soc_DESCRIPTOR_RX_03_BCM53400_A0fmt_fields, 3205 /* bits */ 32, 3206 /* flags */ 0, 3207 }, 3208 #endif /* chips */ 3209 3210 #if defined(BCM_56560_B0) 3211 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_03_BCM56560_B0fmt */ 3212 /* format DESCRIPTOR_RX_03fmt */ 3213 /* nFields */ 1, 3214 /* *fields */ soc_DESCRIPTOR_RX_03_BCM53400_A0fmt_fields, 3215 /* bits */ 32, 3216 /* flags */ 0, 3217 }, 3218 #endif /* chips */ 3219 3220 #if defined(BCM_56624_A0) 3221 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_03_BCM56624_A0fmt */ 3222 /* format DESCRIPTOR_RX_03fmt */ 3223 /* nFields */ 1, 3224 /* *fields */ soc_DESCRIPTOR_RX_03_BCM56624_A0fmt_fields, 3225 /* bits */ 32, 3226 /* flags */ 0, 3227 }, 3228 #endif /* chips */ 3229 3230 #if defined(BCM_56624_B0) 3231 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_03_BCM56624_B0fmt */ 3232 /* format DESCRIPTOR_RX_03fmt */ 3233 /* nFields */ 1, 3234 /* *fields */ soc_DESCRIPTOR_RX_03_BCM56624_A0fmt_fields, 3235 /* bits */ 32, 3236 /* flags */ 0, 3237 }, 3238 #endif /* chips */ 3239 3240 #if defined(BCM_56634_A0) 3241 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_03_BCM56634_A0fmt */ 3242 /* format DESCRIPTOR_RX_03fmt */ 3243 /* nFields */ 1, 3244 /* *fields */ soc_DESCRIPTOR_RX_03_BCM56624_A0fmt_fields, 3245 /* bits */ 32, 3246 /* flags */ 0, 3247 }, 3248 #endif /* chips */ 3249 3250 #if defined(BCM_56634_B0) 3251 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_03_BCM56634_B0fmt */ 3252 /* format DESCRIPTOR_RX_03fmt */ 3253 /* nFields */ 1, 3254 /* *fields */ soc_DESCRIPTOR_RX_03_BCM56624_A0fmt_fields, 3255 /* bits */ 32, 3256 /* flags */ 0, 3257 }, 3258 #endif /* chips */ 3259 3260 #if defined(BCM_56640_A0) 3261 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_03_BCM56640_A0fmt */ 3262 /* format DESCRIPTOR_RX_03fmt */ 3263 /* nFields */ 1, 3264 /* *fields */ soc_DESCRIPTOR_RX_03_BCM56640_A0fmt_fields, 3265 /* bits */ 32, 3266 /* flags */ 0, 3267 }, 3268 #endif /* chips */ 3269 3270 #if defined(BCM_56670_A0) 3271 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_03_BCM56670_A0fmt */ 3272 /* format DESCRIPTOR_RX_03fmt */ 3273 /* nFields */ 1, 3274 /* *fields */ soc_DESCRIPTOR_RX_03_BCM53400_A0fmt_fields, 3275 /* bits */ 32, 3276 /* flags */ 0, 3277 }, 3278 #endif /* chips */ 3279 3280 #if defined(BCM_56670_B0) 3281 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_03_BCM56670_B0fmt */ 3282 /* format DESCRIPTOR_RX_03fmt */ 3283 /* nFields */ 1, 3284 /* *fields */ soc_DESCRIPTOR_RX_03_BCM53400_A0fmt_fields, 3285 /* bits */ 32, 3286 /* flags */ 0, 3287 }, 3288 #endif /* chips */ 3289 3290 #if defined(BCM_56680_A0) 3291 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_03_BCM56680_A0fmt */ 3292 /* format DESCRIPTOR_RX_03fmt */ 3293 /* nFields */ 1, 3294 /* *fields */ soc_DESCRIPTOR_RX_03_BCM56624_A0fmt_fields, 3295 /* bits */ 32, 3296 /* flags */ 0, 3297 }, 3298 #endif /* chips */ 3299 3300 #if defined(BCM_56680_B0) 3301 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_03_BCM56680_B0fmt */ 3302 /* format DESCRIPTOR_RX_03fmt */ 3303 /* nFields */ 1, 3304 /* *fields */ soc_DESCRIPTOR_RX_03_BCM56624_A0fmt_fields, 3305 /* bits */ 32, 3306 /* flags */ 0, 3307 }, 3308 #endif /* chips */ 3309 3310 #if defined(BCM_56685_A0) 3311 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_03_BCM56685_A0fmt */ 3312 /* format DESCRIPTOR_RX_03fmt */ 3313 /* nFields */ 1, 3314 /* *fields */ soc_DESCRIPTOR_RX_03_BCM56624_A0fmt_fields, 3315 /* bits */ 32, 3316 /* flags */ 0, 3317 }, 3318 #endif /* chips */ 3319 3320 #if defined(BCM_56685_B0) 3321 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_03_BCM56685_B0fmt */ 3322 /* format DESCRIPTOR_RX_03fmt */ 3323 /* nFields */ 1, 3324 /* *fields */ soc_DESCRIPTOR_RX_03_BCM56624_A0fmt_fields, 3325 /* bits */ 32, 3326 /* flags */ 0, 3327 }, 3328 #endif /* chips */ 3329 3330 #if defined(BCM_56725_A0) 3331 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_03_BCM56725_A0fmt */ 3332 /* format DESCRIPTOR_RX_03fmt */ 3333 /* nFields */ 1, 3334 /* *fields */ soc_DESCRIPTOR_RX_03_BCM56624_A0fmt_fields, 3335 /* bits */ 32, 3336 /* flags */ 0, 3337 }, 3338 #endif /* chips */ 3339 3340 #if defined(BCM_56770_A0) 3341 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_03_BCM56770_A0fmt */ 3342 /* format DESCRIPTOR_RX_03fmt */ 3343 /* nFields */ 6, 3344 /* *fields */ soc_DESCRIPTOR_RX_03_BCM56870_A0fmt_fields, 3345 /* bits */ 32, 3346 /* flags */ 0, 3347 }, 3348 #endif /* chips */ 3349 3350 #if defined(BCM_56800_A0) 3351 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_03_BCM56800_A0fmt */ 3352 /* format DESCRIPTOR_RX_03fmt */ 3353 /* nFields */ 1, 3354 /* *fields */ soc_DESCRIPTOR_RX_03fmt_fields, 3355 /* bits */ 32, 3356 /* flags */ 0, 3357 }, 3358 #endif /* chips */ 3359 3360 #if defined(BCM_56820_A0) 3361 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_03_BCM56820_A0fmt */ 3362 /* format DESCRIPTOR_RX_03fmt */ 3363 /* nFields */ 1, 3364 /* *fields */ soc_DESCRIPTOR_RX_03_BCM56624_A0fmt_fields, 3365 /* bits */ 32, 3366 /* flags */ 0, 3367 }, 3368 #endif /* chips */ 3369 3370 #if defined(BCM_56840_A0) 3371 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_03_BCM56840_A0fmt */ 3372 /* format DESCRIPTOR_RX_03fmt */ 3373 /* nFields */ 1, 3374 /* *fields */ soc_DESCRIPTOR_RX_03_BCM56624_A0fmt_fields, 3375 /* bits */ 32, 3376 /* flags */ 0, 3377 }, 3378 #endif /* chips */ 3379 3380 #if defined(BCM_56840_B0) 3381 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_03_BCM56840_B0fmt */ 3382 /* format DESCRIPTOR_RX_03fmt */ 3383 /* nFields */ 1, 3384 /* *fields */ soc_DESCRIPTOR_RX_03_BCM56624_A0fmt_fields, 3385 /* bits */ 32, 3386 /* flags */ 0, 3387 }, 3388 #endif /* chips */ 3389 3390 #if defined(BCM_56850_A0) 3391 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_03_BCM56850_A0fmt */ 3392 /* format DESCRIPTOR_RX_03fmt */ 3393 /* nFields */ 1, 3394 /* *fields */ soc_DESCRIPTOR_RX_03_BCM56640_A0fmt_fields, 3395 /* bits */ 32, 3396 /* flags */ 0, 3397 }, 3398 #endif /* chips */ 3399 3400 #if defined(BCM_56860_A0) 3401 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_03_BCM56860_A0fmt */ 3402 /* format DESCRIPTOR_RX_03fmt */ 3403 /* nFields */ 1, 3404 /* *fields */ soc_DESCRIPTOR_RX_03_BCM56640_A0fmt_fields, 3405 /* bits */ 32, 3406 /* flags */ 0, 3407 }, 3408 #endif /* chips */ 3409 3410 #if defined(BCM_56870_A0) 3411 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_03_BCM56870_A0fmt */ 3412 /* format DESCRIPTOR_RX_03fmt */ 3413 /* nFields */ 6, 3414 /* *fields */ soc_DESCRIPTOR_RX_03_BCM56870_A0fmt_fields, 3415 /* bits */ 32, 3416 /* flags */ 0, 3417 }, 3418 #endif /* chips */ 3419 3420 #if defined(BCM_56960_A0) 3421 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_03_BCM56960_A0fmt */ 3422 /* format DESCRIPTOR_RX_03fmt */ 3423 /* nFields */ 1, 3424 /* *fields */ soc_DESCRIPTOR_RX_03_BCM53400_A0fmt_fields, 3425 /* bits */ 32, 3426 /* flags */ 0, 3427 }, 3428 #endif /* chips */ 3429 3430 #if defined(BCM_56965_A0) 3431 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_03_BCM56965_A0fmt */ 3432 /* format DESCRIPTOR_RX_03fmt */ 3433 /* nFields */ 1, 3434 /* *fields */ soc_DESCRIPTOR_RX_03_BCM53400_A0fmt_fields, 3435 /* bits */ 32, 3436 /* flags */ 0, 3437 }, 3438 #endif /* chips */ 3439 3440 #if defined(BCM_56970_A0) 3441 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_03_BCM56970_A0fmt */ 3442 /* format DESCRIPTOR_RX_03fmt */ 3443 /* nFields */ 1, 3444 /* *fields */ soc_DESCRIPTOR_RX_03_BCM53400_A0fmt_fields, 3445 /* bits */ 32, 3446 /* flags */ 0, 3447 }, 3448 #endif /* chips */ 3449 3450 #if defined(BCM_56980_A0) 3451 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_03_BCM56980_A0fmt */ 3452 /* format DESCRIPTOR_RX_03fmt */ 3453 /* nFields */ 6, 3454 /* *fields */ soc_DESCRIPTOR_RX_03_BCM56870_A0fmt_fields, 3455 /* bits */ 32, 3456 /* flags */ 0, 3457 }, 3458 #endif /* chips */ 3459 3460 #if defined(BCM_56980_B0) 3461 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_03_BCM56980_B0fmt */ 3462 /* format DESCRIPTOR_RX_03fmt */ 3463 /* nFields */ 6, 3464 /* *fields */ soc_DESCRIPTOR_RX_03_BCM56870_A0fmt_fields, 3465 /* bits */ 32, 3466 /* flags */ 0, 3467 }, 3468 #endif /* chips */ 3469 3470 #if defined(BCM_88732_A0) 3471 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_03_BCM88732_A0fmt */ 3472 /* format DESCRIPTOR_RX_03fmt */ 3473 /* nFields */ 1, 3474 /* *fields */ soc_DESCRIPTOR_RX_03_BCM56624_A0fmt_fields, 3475 /* bits */ 32, 3476 /* flags */ 0, 3477 }, 3478 #endif /* chips */ 3479 3480 #if defined(BCM_53400_A0) 3481 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_04_BCM53400_A0fmt */ 3482 /* format DESCRIPTOR_RX_04fmt */ 3483 /* nFields */ 1, 3484 /* *fields */ soc_DESCRIPTOR_RX_04_BCM53400_A0fmt_fields, 3485 /* bits */ 32, 3486 /* flags */ 0, 3487 }, 3488 #endif /* chips */ 3489 3490 #if defined(BCM_53540_A0) 3491 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_04_BCM53540_A0fmt */ 3492 /* format DESCRIPTOR_RX_04fmt */ 3493 /* nFields */ 1, 3494 /* *fields */ soc_DESCRIPTOR_RX_04_BCM53400_A0fmt_fields, 3495 /* bits */ 32, 3496 /* flags */ 0, 3497 }, 3498 #endif /* chips */ 3499 3500 #if defined(BCM_53570_A0) 3501 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_04_BCM53570_A0fmt */ 3502 /* format DESCRIPTOR_RX_04fmt */ 3503 /* nFields */ 1, 3504 /* *fields */ soc_DESCRIPTOR_RX_04_BCM53400_A0fmt_fields, 3505 /* bits */ 32, 3506 /* flags */ 0, 3507 }, 3508 #endif /* chips */ 3509 3510 #if defined(BCM_53570_B0) 3511 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_04_BCM53570_B0fmt */ 3512 /* format DESCRIPTOR_RX_04fmt */ 3513 /* nFields */ 1, 3514 /* *fields */ soc_DESCRIPTOR_RX_04_BCM53400_A0fmt_fields, 3515 /* bits */ 32, 3516 /* flags */ 0, 3517 }, 3518 #endif /* chips */ 3519 3520 #if defined(BCM_56142_A0) 3521 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_04_BCM56142_A0fmt */ 3522 /* format DESCRIPTOR_RX_04fmt */ 3523 /* nFields */ 1, 3524 /* *fields */ soc_DESCRIPTOR_RX_04_BCM56624_A0fmt_fields, 3525 /* bits */ 32, 3526 /* flags */ 0, 3527 }, 3528 #endif /* chips */ 3529 3530 #if defined(BCM_56150_A0) 3531 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_04_BCM56150_A0fmt */ 3532 /* format DESCRIPTOR_RX_04fmt */ 3533 /* nFields */ 1, 3534 /* *fields */ soc_DESCRIPTOR_RX_04_BCM56640_A0fmt_fields, 3535 /* bits */ 32, 3536 /* flags */ 0, 3537 }, 3538 #endif /* chips */ 3539 3540 #if defined(BCM_56160_A0) 3541 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_04_BCM56160_A0fmt */ 3542 /* format DESCRIPTOR_RX_04fmt */ 3543 /* nFields */ 1, 3544 /* *fields */ soc_DESCRIPTOR_RX_04_BCM53400_A0fmt_fields, 3545 /* bits */ 32, 3546 /* flags */ 0, 3547 }, 3548 #endif /* chips */ 3549 3550 #if defined(BCM_56260_A0) 3551 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_04_BCM56260_A0fmt */ 3552 /* format DESCRIPTOR_RX_04fmt */ 3553 /* nFields */ 1, 3554 /* *fields */ soc_DESCRIPTOR_RX_04_BCM53400_A0fmt_fields, 3555 /* bits */ 32, 3556 /* flags */ 0, 3557 }, 3558 #endif /* chips */ 3559 3560 #if defined(BCM_56260_B0) 3561 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_04_BCM56260_B0fmt */ 3562 /* format DESCRIPTOR_RX_04fmt */ 3563 /* nFields */ 1, 3564 /* *fields */ soc_DESCRIPTOR_RX_04_BCM53400_A0fmt_fields, 3565 /* bits */ 32, 3566 /* flags */ 0, 3567 }, 3568 #endif /* chips */ 3569 3570 #if defined(BCM_56270_A0) 3571 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_04_BCM56270_A0fmt */ 3572 /* format DESCRIPTOR_RX_04fmt */ 3573 /* nFields */ 1, 3574 /* *fields */ soc_DESCRIPTOR_RX_04_BCM53400_A0fmt_fields, 3575 /* bits */ 32, 3576 /* flags */ 0, 3577 }, 3578 #endif /* chips */ 3579 3580 #if defined(BCM_56334_A0) 3581 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_04_BCM56334_A0fmt */ 3582 /* format DESCRIPTOR_RX_04fmt */ 3583 /* nFields */ 1, 3584 /* *fields */ soc_DESCRIPTOR_RX_04_BCM56624_A0fmt_fields, 3585 /* bits */ 32, 3586 /* flags */ 0, 3587 }, 3588 #endif /* chips */ 3589 3590 #if defined(BCM_56334_B0) 3591 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_04_BCM56334_B0fmt */ 3592 /* format DESCRIPTOR_RX_04fmt */ 3593 /* nFields */ 1, 3594 /* *fields */ soc_DESCRIPTOR_RX_04_BCM56624_A0fmt_fields, 3595 /* bits */ 32, 3596 /* flags */ 0, 3597 }, 3598 #endif /* chips */ 3599 3600 #if defined(BCM_56340_A0) 3601 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_04_BCM56340_A0fmt */ 3602 /* format DESCRIPTOR_RX_04fmt */ 3603 /* nFields */ 1, 3604 /* *fields */ soc_DESCRIPTOR_RX_04_BCM56640_A0fmt_fields, 3605 /* bits */ 32, 3606 /* flags */ 0, 3607 }, 3608 #endif /* chips */ 3609 3610 #if defined(BCM_56440_A0) 3611 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_04_BCM56440_A0fmt */ 3612 /* format DESCRIPTOR_RX_04fmt */ 3613 /* nFields */ 1, 3614 /* *fields */ soc_DESCRIPTOR_RX_04_BCM56624_A0fmt_fields, 3615 /* bits */ 32, 3616 /* flags */ 0, 3617 }, 3618 #endif /* chips */ 3619 3620 #if defined(BCM_56440_B0) 3621 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_04_BCM56440_B0fmt */ 3622 /* format DESCRIPTOR_RX_04fmt */ 3623 /* nFields */ 1, 3624 /* *fields */ soc_DESCRIPTOR_RX_04_BCM56624_A0fmt_fields, 3625 /* bits */ 32, 3626 /* flags */ 0, 3627 }, 3628 #endif /* chips */ 3629 3630 #if defined(BCM_56450_A0) 3631 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_04_BCM56450_A0fmt */ 3632 /* format DESCRIPTOR_RX_04fmt */ 3633 /* nFields */ 1, 3634 /* *fields */ soc_DESCRIPTOR_RX_04_BCM56640_A0fmt_fields, 3635 /* bits */ 32, 3636 /* flags */ 0, 3637 }, 3638 #endif /* chips */ 3639 3640 #if defined(BCM_56450_B0) 3641 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_04_BCM56450_B0fmt */ 3642 /* format DESCRIPTOR_RX_04fmt */ 3643 /* nFields */ 1, 3644 /* *fields */ soc_DESCRIPTOR_RX_04_BCM56640_A0fmt_fields, 3645 /* bits */ 32, 3646 /* flags */ 0, 3647 }, 3648 #endif /* chips */ 3649 3650 #if defined(BCM_56450_B1) 3651 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_04_BCM56450_B1fmt */ 3652 /* format DESCRIPTOR_RX_04fmt */ 3653 /* nFields */ 1, 3654 /* *fields */ soc_DESCRIPTOR_RX_04_BCM56640_A0fmt_fields, 3655 /* bits */ 32, 3656 /* flags */ 0, 3657 }, 3658 #endif /* chips */ 3659 3660 #if defined(BCM_56504_B0) 3661 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_04_BCM56504_B0fmt */ 3662 /* format DESCRIPTOR_RX_04fmt */ 3663 /* nFields */ 1, 3664 /* *fields */ soc_DESCRIPTOR_RX_04fmt_fields, 3665 /* bits */ 32, 3666 /* flags */ 0, 3667 }, 3668 #endif /* chips */ 3669 3670 #if defined(BCM_56524_A0) 3671 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_04_BCM56524_A0fmt */ 3672 /* format DESCRIPTOR_RX_04fmt */ 3673 /* nFields */ 1, 3674 /* *fields */ soc_DESCRIPTOR_RX_04_BCM56624_A0fmt_fields, 3675 /* bits */ 32, 3676 /* flags */ 0, 3677 }, 3678 #endif /* chips */ 3679 3680 #if defined(BCM_56524_B0) 3681 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_04_BCM56524_B0fmt */ 3682 /* format DESCRIPTOR_RX_04fmt */ 3683 /* nFields */ 1, 3684 /* *fields */ soc_DESCRIPTOR_RX_04_BCM56624_A0fmt_fields, 3685 /* bits */ 32, 3686 /* flags */ 0, 3687 }, 3688 #endif /* chips */ 3689 3690 #if defined(BCM_56560_A0) 3691 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_04_BCM56560_A0fmt */ 3692 /* format DESCRIPTOR_RX_04fmt */ 3693 /* nFields */ 1, 3694 /* *fields */ soc_DESCRIPTOR_RX_04_BCM53400_A0fmt_fields, 3695 /* bits */ 32, 3696 /* flags */ 0, 3697 }, 3698 #endif /* chips */ 3699 3700 #if defined(BCM_56560_B0) 3701 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_04_BCM56560_B0fmt */ 3702 /* format DESCRIPTOR_RX_04fmt */ 3703 /* nFields */ 1, 3704 /* *fields */ soc_DESCRIPTOR_RX_04_BCM53400_A0fmt_fields, 3705 /* bits */ 32, 3706 /* flags */ 0, 3707 }, 3708 #endif /* chips */ 3709 3710 #if defined(BCM_56624_A0) 3711 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_04_BCM56624_A0fmt */ 3712 /* format DESCRIPTOR_RX_04fmt */ 3713 /* nFields */ 1, 3714 /* *fields */ soc_DESCRIPTOR_RX_04_BCM56624_A0fmt_fields, 3715 /* bits */ 32, 3716 /* flags */ 0, 3717 }, 3718 #endif /* chips */ 3719 3720 #if defined(BCM_56624_B0) 3721 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_04_BCM56624_B0fmt */ 3722 /* format DESCRIPTOR_RX_04fmt */ 3723 /* nFields */ 1, 3724 /* *fields */ soc_DESCRIPTOR_RX_04_BCM56624_A0fmt_fields, 3725 /* bits */ 32, 3726 /* flags */ 0, 3727 }, 3728 #endif /* chips */ 3729 3730 #if defined(BCM_56634_A0) 3731 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_04_BCM56634_A0fmt */ 3732 /* format DESCRIPTOR_RX_04fmt */ 3733 /* nFields */ 1, 3734 /* *fields */ soc_DESCRIPTOR_RX_04_BCM56624_A0fmt_fields, 3735 /* bits */ 32, 3736 /* flags */ 0, 3737 }, 3738 #endif /* chips */ 3739 3740 #if defined(BCM_56634_B0) 3741 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_04_BCM56634_B0fmt */ 3742 /* format DESCRIPTOR_RX_04fmt */ 3743 /* nFields */ 1, 3744 /* *fields */ soc_DESCRIPTOR_RX_04_BCM56624_A0fmt_fields, 3745 /* bits */ 32, 3746 /* flags */ 0, 3747 }, 3748 #endif /* chips */ 3749 3750 #if defined(BCM_56640_A0) 3751 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_04_BCM56640_A0fmt */ 3752 /* format DESCRIPTOR_RX_04fmt */ 3753 /* nFields */ 1, 3754 /* *fields */ soc_DESCRIPTOR_RX_04_BCM56640_A0fmt_fields, 3755 /* bits */ 32, 3756 /* flags */ 0, 3757 }, 3758 #endif /* chips */ 3759 3760 #if defined(BCM_56670_A0) 3761 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_04_BCM56670_A0fmt */ 3762 /* format DESCRIPTOR_RX_04fmt */ 3763 /* nFields */ 1, 3764 /* *fields */ soc_DESCRIPTOR_RX_04_BCM53400_A0fmt_fields, 3765 /* bits */ 32, 3766 /* flags */ 0, 3767 }, 3768 #endif /* chips */ 3769 3770 #if defined(BCM_56670_B0) 3771 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_04_BCM56670_B0fmt */ 3772 /* format DESCRIPTOR_RX_04fmt */ 3773 /* nFields */ 1, 3774 /* *fields */ soc_DESCRIPTOR_RX_04_BCM53400_A0fmt_fields, 3775 /* bits */ 32, 3776 /* flags */ 0, 3777 }, 3778 #endif /* chips */ 3779 3780 #if defined(BCM_56680_A0) 3781 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_04_BCM56680_A0fmt */ 3782 /* format DESCRIPTOR_RX_04fmt */ 3783 /* nFields */ 1, 3784 /* *fields */ soc_DESCRIPTOR_RX_04_BCM56624_A0fmt_fields, 3785 /* bits */ 32, 3786 /* flags */ 0, 3787 }, 3788 #endif /* chips */ 3789 3790 #if defined(BCM_56680_B0) 3791 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_04_BCM56680_B0fmt */ 3792 /* format DESCRIPTOR_RX_04fmt */ 3793 /* nFields */ 1, 3794 /* *fields */ soc_DESCRIPTOR_RX_04_BCM56624_A0fmt_fields, 3795 /* bits */ 32, 3796 /* flags */ 0, 3797 }, 3798 #endif /* chips */ 3799 3800 #if defined(BCM_56685_A0) 3801 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_04_BCM56685_A0fmt */ 3802 /* format DESCRIPTOR_RX_04fmt */ 3803 /* nFields */ 1, 3804 /* *fields */ soc_DESCRIPTOR_RX_04_BCM56624_A0fmt_fields, 3805 /* bits */ 32, 3806 /* flags */ 0, 3807 }, 3808 #endif /* chips */ 3809 3810 #if defined(BCM_56685_B0) 3811 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_04_BCM56685_B0fmt */ 3812 /* format DESCRIPTOR_RX_04fmt */ 3813 /* nFields */ 1, 3814 /* *fields */ soc_DESCRIPTOR_RX_04_BCM56624_A0fmt_fields, 3815 /* bits */ 32, 3816 /* flags */ 0, 3817 }, 3818 #endif /* chips */ 3819 3820 #if defined(BCM_56725_A0) 3821 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_04_BCM56725_A0fmt */ 3822 /* format DESCRIPTOR_RX_04fmt */ 3823 /* nFields */ 1, 3824 /* *fields */ soc_DESCRIPTOR_RX_04_BCM56624_A0fmt_fields, 3825 /* bits */ 32, 3826 /* flags */ 0, 3827 }, 3828 #endif /* chips */ 3829 3830 #if defined(BCM_56800_A0) 3831 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_04_BCM56800_A0fmt */ 3832 /* format DESCRIPTOR_RX_04fmt */ 3833 /* nFields */ 1, 3834 /* *fields */ soc_DESCRIPTOR_RX_04fmt_fields, 3835 /* bits */ 32, 3836 /* flags */ 0, 3837 }, 3838 #endif /* chips */ 3839 3840 #if defined(BCM_56820_A0) 3841 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_04_BCM56820_A0fmt */ 3842 /* format DESCRIPTOR_RX_04fmt */ 3843 /* nFields */ 1, 3844 /* *fields */ soc_DESCRIPTOR_RX_04_BCM56624_A0fmt_fields, 3845 /* bits */ 32, 3846 /* flags */ 0, 3847 }, 3848 #endif /* chips */ 3849 3850 #if defined(BCM_56840_A0) 3851 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_04_BCM56840_A0fmt */ 3852 /* format DESCRIPTOR_RX_04fmt */ 3853 /* nFields */ 1, 3854 /* *fields */ soc_DESCRIPTOR_RX_04_BCM56624_A0fmt_fields, 3855 /* bits */ 32, 3856 /* flags */ 0, 3857 }, 3858 #endif /* chips */ 3859 3860 #if defined(BCM_56840_B0) 3861 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_04_BCM56840_B0fmt */ 3862 /* format DESCRIPTOR_RX_04fmt */ 3863 /* nFields */ 1, 3864 /* *fields */ soc_DESCRIPTOR_RX_04_BCM56624_A0fmt_fields, 3865 /* bits */ 32, 3866 /* flags */ 0, 3867 }, 3868 #endif /* chips */ 3869 3870 #if defined(BCM_56850_A0) 3871 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_04_BCM56850_A0fmt */ 3872 /* format DESCRIPTOR_RX_04fmt */ 3873 /* nFields */ 1, 3874 /* *fields */ soc_DESCRIPTOR_RX_04_BCM56640_A0fmt_fields, 3875 /* bits */ 32, 3876 /* flags */ 0, 3877 }, 3878 #endif /* chips */ 3879 3880 #if defined(BCM_56860_A0) 3881 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_04_BCM56860_A0fmt */ 3882 /* format DESCRIPTOR_RX_04fmt */ 3883 /* nFields */ 1, 3884 /* *fields */ soc_DESCRIPTOR_RX_04_BCM56640_A0fmt_fields, 3885 /* bits */ 32, 3886 /* flags */ 0, 3887 }, 3888 #endif /* chips */ 3889 3890 #if defined(BCM_56960_A0) 3891 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_04_BCM56960_A0fmt */ 3892 /* format DESCRIPTOR_RX_04fmt */ 3893 /* nFields */ 1, 3894 /* *fields */ soc_DESCRIPTOR_RX_04_BCM53400_A0fmt_fields, 3895 /* bits */ 32, 3896 /* flags */ 0, 3897 }, 3898 #endif /* chips */ 3899 3900 #if defined(BCM_56965_A0) 3901 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_04_BCM56965_A0fmt */ 3902 /* format DESCRIPTOR_RX_04fmt */ 3903 /* nFields */ 1, 3904 /* *fields */ soc_DESCRIPTOR_RX_04_BCM53400_A0fmt_fields, 3905 /* bits */ 32, 3906 /* flags */ 0, 3907 }, 3908 #endif /* chips */ 3909 3910 #if defined(BCM_56970_A0) 3911 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_04_BCM56970_A0fmt */ 3912 /* format DESCRIPTOR_RX_04fmt */ 3913 /* nFields */ 1, 3914 /* *fields */ soc_DESCRIPTOR_RX_04_BCM53400_A0fmt_fields, 3915 /* bits */ 32, 3916 /* flags */ 0, 3917 }, 3918 #endif /* chips */ 3919 3920 #if defined(BCM_88732_A0) 3921 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_04_BCM88732_A0fmt */ 3922 /* format DESCRIPTOR_RX_04fmt */ 3923 /* nFields */ 1, 3924 /* *fields */ soc_DESCRIPTOR_RX_04_BCM56624_A0fmt_fields, 3925 /* bits */ 32, 3926 /* flags */ 0, 3927 }, 3928 #endif /* chips */ 3929 3930 #if defined(BCM_53400_A0) 3931 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_05_BCM53400_A0fmt */ 3932 /* format DESCRIPTOR_RX_05fmt */ 3933 /* nFields */ 1, 3934 /* *fields */ soc_DESCRIPTOR_RX_05_BCM53400_A0fmt_fields, 3935 /* bits */ 32, 3936 /* flags */ 0, 3937 }, 3938 #endif /* chips */ 3939 3940 #if defined(BCM_53540_A0) 3941 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_05_BCM53540_A0fmt */ 3942 /* format DESCRIPTOR_RX_05fmt */ 3943 /* nFields */ 1, 3944 /* *fields */ soc_DESCRIPTOR_RX_05_BCM53400_A0fmt_fields, 3945 /* bits */ 32, 3946 /* flags */ 0, 3947 }, 3948 #endif /* chips */ 3949 3950 #if defined(BCM_53570_A0) 3951 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_05_BCM53570_A0fmt */ 3952 /* format DESCRIPTOR_RX_05fmt */ 3953 /* nFields */ 1, 3954 /* *fields */ soc_DESCRIPTOR_RX_05_BCM53400_A0fmt_fields, 3955 /* bits */ 32, 3956 /* flags */ 0, 3957 }, 3958 #endif /* chips */ 3959 3960 #if defined(BCM_53570_B0) 3961 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_05_BCM53570_B0fmt */ 3962 /* format DESCRIPTOR_RX_05fmt */ 3963 /* nFields */ 1, 3964 /* *fields */ soc_DESCRIPTOR_RX_05_BCM53400_A0fmt_fields, 3965 /* bits */ 32, 3966 /* flags */ 0, 3967 }, 3968 #endif /* chips */ 3969 3970 #if defined(BCM_56142_A0) 3971 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_05_BCM56142_A0fmt */ 3972 /* format DESCRIPTOR_RX_05fmt */ 3973 /* nFields */ 1, 3974 /* *fields */ soc_DESCRIPTOR_RX_05_BCM56624_A0fmt_fields, 3975 /* bits */ 32, 3976 /* flags */ 0, 3977 }, 3978 #endif /* chips */ 3979 3980 #if defined(BCM_56150_A0) 3981 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_05_BCM56150_A0fmt */ 3982 /* format DESCRIPTOR_RX_05fmt */ 3983 /* nFields */ 1, 3984 /* *fields */ soc_DESCRIPTOR_RX_05_BCM56640_A0fmt_fields, 3985 /* bits */ 32, 3986 /* flags */ 0, 3987 }, 3988 #endif /* chips */ 3989 3990 #if defined(BCM_56160_A0) 3991 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_05_BCM56160_A0fmt */ 3992 /* format DESCRIPTOR_RX_05fmt */ 3993 /* nFields */ 1, 3994 /* *fields */ soc_DESCRIPTOR_RX_05_BCM53400_A0fmt_fields, 3995 /* bits */ 32, 3996 /* flags */ 0, 3997 }, 3998 #endif /* chips */ 3999 4000 #if defined(BCM_56260_A0) 4001 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_05_BCM56260_A0fmt */ 4002 /* format DESCRIPTOR_RX_05fmt */ 4003 /* nFields */ 1, 4004 /* *fields */ soc_DESCRIPTOR_RX_05_BCM53400_A0fmt_fields, 4005 /* bits */ 32, 4006 /* flags */ 0, 4007 }, 4008 #endif /* chips */ 4009 4010 #if defined(BCM_56260_B0) 4011 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_05_BCM56260_B0fmt */ 4012 /* format DESCRIPTOR_RX_05fmt */ 4013 /* nFields */ 1, 4014 /* *fields */ soc_DESCRIPTOR_RX_05_BCM53400_A0fmt_fields, 4015 /* bits */ 32, 4016 /* flags */ 0, 4017 }, 4018 #endif /* chips */ 4019 4020 #if defined(BCM_56270_A0) 4021 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_05_BCM56270_A0fmt */ 4022 /* format DESCRIPTOR_RX_05fmt */ 4023 /* nFields */ 1, 4024 /* *fields */ soc_DESCRIPTOR_RX_05_BCM53400_A0fmt_fields, 4025 /* bits */ 32, 4026 /* flags */ 0, 4027 }, 4028 #endif /* chips */ 4029 4030 #if defined(BCM_56334_A0) 4031 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_05_BCM56334_A0fmt */ 4032 /* format DESCRIPTOR_RX_05fmt */ 4033 /* nFields */ 1, 4034 /* *fields */ soc_DESCRIPTOR_RX_05_BCM56624_A0fmt_fields, 4035 /* bits */ 32, 4036 /* flags */ 0, 4037 }, 4038 #endif /* chips */ 4039 4040 #if defined(BCM_56334_B0) 4041 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_05_BCM56334_B0fmt */ 4042 /* format DESCRIPTOR_RX_05fmt */ 4043 /* nFields */ 1, 4044 /* *fields */ soc_DESCRIPTOR_RX_05_BCM56624_A0fmt_fields, 4045 /* bits */ 32, 4046 /* flags */ 0, 4047 }, 4048 #endif /* chips */ 4049 4050 #if defined(BCM_56340_A0) 4051 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_05_BCM56340_A0fmt */ 4052 /* format DESCRIPTOR_RX_05fmt */ 4053 /* nFields */ 1, 4054 /* *fields */ soc_DESCRIPTOR_RX_05_BCM56640_A0fmt_fields, 4055 /* bits */ 32, 4056 /* flags */ 0, 4057 }, 4058 #endif /* chips */ 4059 4060 #if defined(BCM_56440_A0) 4061 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_05_BCM56440_A0fmt */ 4062 /* format DESCRIPTOR_RX_05fmt */ 4063 /* nFields */ 1, 4064 /* *fields */ soc_DESCRIPTOR_RX_05_BCM56624_A0fmt_fields, 4065 /* bits */ 32, 4066 /* flags */ 0, 4067 }, 4068 #endif /* chips */ 4069 4070 #if defined(BCM_56440_B0) 4071 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_05_BCM56440_B0fmt */ 4072 /* format DESCRIPTOR_RX_05fmt */ 4073 /* nFields */ 1, 4074 /* *fields */ soc_DESCRIPTOR_RX_05_BCM56624_A0fmt_fields, 4075 /* bits */ 32, 4076 /* flags */ 0, 4077 }, 4078 #endif /* chips */ 4079 4080 #if defined(BCM_56450_A0) 4081 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_05_BCM56450_A0fmt */ 4082 /* format DESCRIPTOR_RX_05fmt */ 4083 /* nFields */ 1, 4084 /* *fields */ soc_DESCRIPTOR_RX_05_BCM56640_A0fmt_fields, 4085 /* bits */ 32, 4086 /* flags */ 0, 4087 }, 4088 #endif /* chips */ 4089 4090 #if defined(BCM_56450_B0) 4091 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_05_BCM56450_B0fmt */ 4092 /* format DESCRIPTOR_RX_05fmt */ 4093 /* nFields */ 1, 4094 /* *fields */ soc_DESCRIPTOR_RX_05_BCM56640_A0fmt_fields, 4095 /* bits */ 32, 4096 /* flags */ 0, 4097 }, 4098 #endif /* chips */ 4099 4100 #if defined(BCM_56450_B1) 4101 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_05_BCM56450_B1fmt */ 4102 /* format DESCRIPTOR_RX_05fmt */ 4103 /* nFields */ 1, 4104 /* *fields */ soc_DESCRIPTOR_RX_05_BCM56640_A0fmt_fields, 4105 /* bits */ 32, 4106 /* flags */ 0, 4107 }, 4108 #endif /* chips */ 4109 4110 #if defined(BCM_56524_A0) 4111 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_05_BCM56524_A0fmt */ 4112 /* format DESCRIPTOR_RX_05fmt */ 4113 /* nFields */ 1, 4114 /* *fields */ soc_DESCRIPTOR_RX_05_BCM56624_A0fmt_fields, 4115 /* bits */ 32, 4116 /* flags */ 0, 4117 }, 4118 #endif /* chips */ 4119 4120 #if defined(BCM_56524_B0) 4121 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_05_BCM56524_B0fmt */ 4122 /* format DESCRIPTOR_RX_05fmt */ 4123 /* nFields */ 1, 4124 /* *fields */ soc_DESCRIPTOR_RX_05_BCM56624_A0fmt_fields, 4125 /* bits */ 32, 4126 /* flags */ 0, 4127 }, 4128 #endif /* chips */ 4129 4130 #if defined(BCM_56560_A0) 4131 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_05_BCM56560_A0fmt */ 4132 /* format DESCRIPTOR_RX_05fmt */ 4133 /* nFields */ 1, 4134 /* *fields */ soc_DESCRIPTOR_RX_05_BCM53400_A0fmt_fields, 4135 /* bits */ 32, 4136 /* flags */ 0, 4137 }, 4138 #endif /* chips */ 4139 4140 #if defined(BCM_56560_B0) 4141 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_05_BCM56560_B0fmt */ 4142 /* format DESCRIPTOR_RX_05fmt */ 4143 /* nFields */ 1, 4144 /* *fields */ soc_DESCRIPTOR_RX_05_BCM53400_A0fmt_fields, 4145 /* bits */ 32, 4146 /* flags */ 0, 4147 }, 4148 #endif /* chips */ 4149 4150 #if defined(BCM_56624_A0) 4151 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_05_BCM56624_A0fmt */ 4152 /* format DESCRIPTOR_RX_05fmt */ 4153 /* nFields */ 1, 4154 /* *fields */ soc_DESCRIPTOR_RX_05_BCM56624_A0fmt_fields, 4155 /* bits */ 32, 4156 /* flags */ 0, 4157 }, 4158 #endif /* chips */ 4159 4160 #if defined(BCM_56624_B0) 4161 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_05_BCM56624_B0fmt */ 4162 /* format DESCRIPTOR_RX_05fmt */ 4163 /* nFields */ 1, 4164 /* *fields */ soc_DESCRIPTOR_RX_05_BCM56624_A0fmt_fields, 4165 /* bits */ 32, 4166 /* flags */ 0, 4167 }, 4168 #endif /* chips */ 4169 4170 #if defined(BCM_56634_A0) 4171 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_05_BCM56634_A0fmt */ 4172 /* format DESCRIPTOR_RX_05fmt */ 4173 /* nFields */ 1, 4174 /* *fields */ soc_DESCRIPTOR_RX_05_BCM56624_A0fmt_fields, 4175 /* bits */ 32, 4176 /* flags */ 0, 4177 }, 4178 #endif /* chips */ 4179 4180 #if defined(BCM_56634_B0) 4181 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_05_BCM56634_B0fmt */ 4182 /* format DESCRIPTOR_RX_05fmt */ 4183 /* nFields */ 1, 4184 /* *fields */ soc_DESCRIPTOR_RX_05_BCM56624_A0fmt_fields, 4185 /* bits */ 32, 4186 /* flags */ 0, 4187 }, 4188 #endif /* chips */ 4189 4190 #if defined(BCM_56640_A0) 4191 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_05_BCM56640_A0fmt */ 4192 /* format DESCRIPTOR_RX_05fmt */ 4193 /* nFields */ 1, 4194 /* *fields */ soc_DESCRIPTOR_RX_05_BCM56640_A0fmt_fields, 4195 /* bits */ 32, 4196 /* flags */ 0, 4197 }, 4198 #endif /* chips */ 4199 4200 #if defined(BCM_56670_A0) 4201 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_05_BCM56670_A0fmt */ 4202 /* format DESCRIPTOR_RX_05fmt */ 4203 /* nFields */ 1, 4204 /* *fields */ soc_DESCRIPTOR_RX_05_BCM53400_A0fmt_fields, 4205 /* bits */ 32, 4206 /* flags */ 0, 4207 }, 4208 #endif /* chips */ 4209 4210 #if defined(BCM_56670_B0) 4211 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_05_BCM56670_B0fmt */ 4212 /* format DESCRIPTOR_RX_05fmt */ 4213 /* nFields */ 1, 4214 /* *fields */ soc_DESCRIPTOR_RX_05_BCM53400_A0fmt_fields, 4215 /* bits */ 32, 4216 /* flags */ 0, 4217 }, 4218 #endif /* chips */ 4219 4220 #if defined(BCM_56680_A0) 4221 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_05_BCM56680_A0fmt */ 4222 /* format DESCRIPTOR_RX_05fmt */ 4223 /* nFields */ 1, 4224 /* *fields */ soc_DESCRIPTOR_RX_05_BCM56624_A0fmt_fields, 4225 /* bits */ 32, 4226 /* flags */ 0, 4227 }, 4228 #endif /* chips */ 4229 4230 #if defined(BCM_56680_B0) 4231 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_05_BCM56680_B0fmt */ 4232 /* format DESCRIPTOR_RX_05fmt */ 4233 /* nFields */ 1, 4234 /* *fields */ soc_DESCRIPTOR_RX_05_BCM56624_A0fmt_fields, 4235 /* bits */ 32, 4236 /* flags */ 0, 4237 }, 4238 #endif /* chips */ 4239 4240 #if defined(BCM_56685_A0) 4241 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_05_BCM56685_A0fmt */ 4242 /* format DESCRIPTOR_RX_05fmt */ 4243 /* nFields */ 1, 4244 /* *fields */ soc_DESCRIPTOR_RX_05_BCM56624_A0fmt_fields, 4245 /* bits */ 32, 4246 /* flags */ 0, 4247 }, 4248 #endif /* chips */ 4249 4250 #if defined(BCM_56685_B0) 4251 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_05_BCM56685_B0fmt */ 4252 /* format DESCRIPTOR_RX_05fmt */ 4253 /* nFields */ 1, 4254 /* *fields */ soc_DESCRIPTOR_RX_05_BCM56624_A0fmt_fields, 4255 /* bits */ 32, 4256 /* flags */ 0, 4257 }, 4258 #endif /* chips */ 4259 4260 #if defined(BCM_56725_A0) 4261 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_05_BCM56725_A0fmt */ 4262 /* format DESCRIPTOR_RX_05fmt */ 4263 /* nFields */ 1, 4264 /* *fields */ soc_DESCRIPTOR_RX_05_BCM56624_A0fmt_fields, 4265 /* bits */ 32, 4266 /* flags */ 0, 4267 }, 4268 #endif /* chips */ 4269 4270 #if defined(BCM_56800_A0) 4271 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_05_BCM56800_A0fmt */ 4272 /* format DESCRIPTOR_RX_05fmt */ 4273 /* nFields */ 1, 4274 /* *fields */ soc_DESCRIPTOR_RX_05fmt_fields, 4275 /* bits */ 32, 4276 /* flags */ 0, 4277 }, 4278 #endif /* chips */ 4279 4280 #if defined(BCM_56820_A0) 4281 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_05_BCM56820_A0fmt */ 4282 /* format DESCRIPTOR_RX_05fmt */ 4283 /* nFields */ 1, 4284 /* *fields */ soc_DESCRIPTOR_RX_05_BCM56624_A0fmt_fields, 4285 /* bits */ 32, 4286 /* flags */ 0, 4287 }, 4288 #endif /* chips */ 4289 4290 #if defined(BCM_56840_A0) 4291 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_05_BCM56840_A0fmt */ 4292 /* format DESCRIPTOR_RX_05fmt */ 4293 /* nFields */ 1, 4294 /* *fields */ soc_DESCRIPTOR_RX_05_BCM56624_A0fmt_fields, 4295 /* bits */ 32, 4296 /* flags */ 0, 4297 }, 4298 #endif /* chips */ 4299 4300 #if defined(BCM_56840_B0) 4301 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_05_BCM56840_B0fmt */ 4302 /* format DESCRIPTOR_RX_05fmt */ 4303 /* nFields */ 1, 4304 /* *fields */ soc_DESCRIPTOR_RX_05_BCM56624_A0fmt_fields, 4305 /* bits */ 32, 4306 /* flags */ 0, 4307 }, 4308 #endif /* chips */ 4309 4310 #if defined(BCM_56850_A0) 4311 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_05_BCM56850_A0fmt */ 4312 /* format DESCRIPTOR_RX_05fmt */ 4313 /* nFields */ 1, 4314 /* *fields */ soc_DESCRIPTOR_RX_05_BCM56640_A0fmt_fields, 4315 /* bits */ 32, 4316 /* flags */ 0, 4317 }, 4318 #endif /* chips */ 4319 4320 #if defined(BCM_56860_A0) 4321 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_05_BCM56860_A0fmt */ 4322 /* format DESCRIPTOR_RX_05fmt */ 4323 /* nFields */ 1, 4324 /* *fields */ soc_DESCRIPTOR_RX_05_BCM56640_A0fmt_fields, 4325 /* bits */ 32, 4326 /* flags */ 0, 4327 }, 4328 #endif /* chips */ 4329 4330 #if defined(BCM_56960_A0) 4331 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_05_BCM56960_A0fmt */ 4332 /* format DESCRIPTOR_RX_05fmt */ 4333 /* nFields */ 1, 4334 /* *fields */ soc_DESCRIPTOR_RX_05_BCM53400_A0fmt_fields, 4335 /* bits */ 32, 4336 /* flags */ 0, 4337 }, 4338 #endif /* chips */ 4339 4340 #if defined(BCM_56965_A0) 4341 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_05_BCM56965_A0fmt */ 4342 /* format DESCRIPTOR_RX_05fmt */ 4343 /* nFields */ 1, 4344 /* *fields */ soc_DESCRIPTOR_RX_05_BCM53400_A0fmt_fields, 4345 /* bits */ 32, 4346 /* flags */ 0, 4347 }, 4348 #endif /* chips */ 4349 4350 #if defined(BCM_56970_A0) 4351 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_05_BCM56970_A0fmt */ 4352 /* format DESCRIPTOR_RX_05fmt */ 4353 /* nFields */ 1, 4354 /* *fields */ soc_DESCRIPTOR_RX_05_BCM53400_A0fmt_fields, 4355 /* bits */ 32, 4356 /* flags */ 0, 4357 }, 4358 #endif /* chips */ 4359 4360 #if defined(BCM_88732_A0) 4361 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_05_BCM88732_A0fmt */ 4362 /* format DESCRIPTOR_RX_05fmt */ 4363 /* nFields */ 1, 4364 /* *fields */ soc_DESCRIPTOR_RX_05_BCM56624_A0fmt_fields, 4365 /* bits */ 32, 4366 /* flags */ 0, 4367 }, 4368 #endif /* chips */ 4369 4370 #if defined(BCM_53400_A0) 4371 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_06_BCM53400_A0fmt */ 4372 /* format DESCRIPTOR_RX_06fmt */ 4373 /* nFields */ 1, 4374 /* *fields */ soc_DESCRIPTOR_RX_06_BCM53400_A0fmt_fields, 4375 /* bits */ 32, 4376 /* flags */ 0, 4377 }, 4378 #endif /* chips */ 4379 4380 #if defined(BCM_53540_A0) 4381 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_06_BCM53540_A0fmt */ 4382 /* format DESCRIPTOR_RX_06fmt */ 4383 /* nFields */ 1, 4384 /* *fields */ soc_DESCRIPTOR_RX_06_BCM53400_A0fmt_fields, 4385 /* bits */ 32, 4386 /* flags */ 0, 4387 }, 4388 #endif /* chips */ 4389 4390 #if defined(BCM_53570_A0) 4391 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_06_BCM53570_A0fmt */ 4392 /* format DESCRIPTOR_RX_06fmt */ 4393 /* nFields */ 1, 4394 /* *fields */ soc_DESCRIPTOR_RX_06_BCM53400_A0fmt_fields, 4395 /* bits */ 32, 4396 /* flags */ 0, 4397 }, 4398 #endif /* chips */ 4399 4400 #if defined(BCM_53570_B0) 4401 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_06_BCM53570_B0fmt */ 4402 /* format DESCRIPTOR_RX_06fmt */ 4403 /* nFields */ 1, 4404 /* *fields */ soc_DESCRIPTOR_RX_06_BCM53400_A0fmt_fields, 4405 /* bits */ 32, 4406 /* flags */ 0, 4407 }, 4408 #endif /* chips */ 4409 4410 #if defined(BCM_56142_A0) 4411 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_06_BCM56142_A0fmt */ 4412 /* format DESCRIPTOR_RX_06fmt */ 4413 /* nFields */ 1, 4414 /* *fields */ soc_DESCRIPTOR_RX_06_BCM56624_A0fmt_fields, 4415 /* bits */ 32, 4416 /* flags */ 0, 4417 }, 4418 #endif /* chips */ 4419 4420 #if defined(BCM_56150_A0) 4421 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_06_BCM56150_A0fmt */ 4422 /* format DESCRIPTOR_RX_06fmt */ 4423 /* nFields */ 1, 4424 /* *fields */ soc_DESCRIPTOR_RX_06_BCM56640_A0fmt_fields, 4425 /* bits */ 32, 4426 /* flags */ 0, 4427 }, 4428 #endif /* chips */ 4429 4430 #if defined(BCM_56160_A0) 4431 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_06_BCM56160_A0fmt */ 4432 /* format DESCRIPTOR_RX_06fmt */ 4433 /* nFields */ 1, 4434 /* *fields */ soc_DESCRIPTOR_RX_06_BCM53400_A0fmt_fields, 4435 /* bits */ 32, 4436 /* flags */ 0, 4437 }, 4438 #endif /* chips */ 4439 4440 #if defined(BCM_56260_A0) 4441 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_06_BCM56260_A0fmt */ 4442 /* format DESCRIPTOR_RX_06fmt */ 4443 /* nFields */ 1, 4444 /* *fields */ soc_DESCRIPTOR_RX_06_BCM53400_A0fmt_fields, 4445 /* bits */ 32, 4446 /* flags */ 0, 4447 }, 4448 #endif /* chips */ 4449 4450 #if defined(BCM_56260_B0) 4451 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_06_BCM56260_B0fmt */ 4452 /* format DESCRIPTOR_RX_06fmt */ 4453 /* nFields */ 1, 4454 /* *fields */ soc_DESCRIPTOR_RX_06_BCM53400_A0fmt_fields, 4455 /* bits */ 32, 4456 /* flags */ 0, 4457 }, 4458 #endif /* chips */ 4459 4460 #if defined(BCM_56270_A0) 4461 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_06_BCM56270_A0fmt */ 4462 /* format DESCRIPTOR_RX_06fmt */ 4463 /* nFields */ 1, 4464 /* *fields */ soc_DESCRIPTOR_RX_06_BCM53400_A0fmt_fields, 4465 /* bits */ 32, 4466 /* flags */ 0, 4467 }, 4468 #endif /* chips */ 4469 4470 #if defined(BCM_56334_A0) 4471 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_06_BCM56334_A0fmt */ 4472 /* format DESCRIPTOR_RX_06fmt */ 4473 /* nFields */ 1, 4474 /* *fields */ soc_DESCRIPTOR_RX_06_BCM56624_A0fmt_fields, 4475 /* bits */ 32, 4476 /* flags */ 0, 4477 }, 4478 #endif /* chips */ 4479 4480 #if defined(BCM_56334_B0) 4481 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_06_BCM56334_B0fmt */ 4482 /* format DESCRIPTOR_RX_06fmt */ 4483 /* nFields */ 1, 4484 /* *fields */ soc_DESCRIPTOR_RX_06_BCM56624_A0fmt_fields, 4485 /* bits */ 32, 4486 /* flags */ 0, 4487 }, 4488 #endif /* chips */ 4489 4490 #if defined(BCM_56340_A0) 4491 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_06_BCM56340_A0fmt */ 4492 /* format DESCRIPTOR_RX_06fmt */ 4493 /* nFields */ 1, 4494 /* *fields */ soc_DESCRIPTOR_RX_06_BCM56640_A0fmt_fields, 4495 /* bits */ 32, 4496 /* flags */ 0, 4497 }, 4498 #endif /* chips */ 4499 4500 #if defined(BCM_56440_A0) 4501 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_06_BCM56440_A0fmt */ 4502 /* format DESCRIPTOR_RX_06fmt */ 4503 /* nFields */ 1, 4504 /* *fields */ soc_DESCRIPTOR_RX_06_BCM56624_A0fmt_fields, 4505 /* bits */ 32, 4506 /* flags */ 0, 4507 }, 4508 #endif /* chips */ 4509 4510 #if defined(BCM_56440_B0) 4511 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_06_BCM56440_B0fmt */ 4512 /* format DESCRIPTOR_RX_06fmt */ 4513 /* nFields */ 1, 4514 /* *fields */ soc_DESCRIPTOR_RX_06_BCM56624_A0fmt_fields, 4515 /* bits */ 32, 4516 /* flags */ 0, 4517 }, 4518 #endif /* chips */ 4519 4520 #if defined(BCM_56450_A0) 4521 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_06_BCM56450_A0fmt */ 4522 /* format DESCRIPTOR_RX_06fmt */ 4523 /* nFields */ 1, 4524 /* *fields */ soc_DESCRIPTOR_RX_06_BCM56640_A0fmt_fields, 4525 /* bits */ 32, 4526 /* flags */ 0, 4527 }, 4528 #endif /* chips */ 4529 4530 #if defined(BCM_56450_B0) 4531 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_06_BCM56450_B0fmt */ 4532 /* format DESCRIPTOR_RX_06fmt */ 4533 /* nFields */ 1, 4534 /* *fields */ soc_DESCRIPTOR_RX_06_BCM56640_A0fmt_fields, 4535 /* bits */ 32, 4536 /* flags */ 0, 4537 }, 4538 #endif /* chips */ 4539 4540 #if defined(BCM_56450_B1) 4541 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_06_BCM56450_B1fmt */ 4542 /* format DESCRIPTOR_RX_06fmt */ 4543 /* nFields */ 1, 4544 /* *fields */ soc_DESCRIPTOR_RX_06_BCM56640_A0fmt_fields, 4545 /* bits */ 32, 4546 /* flags */ 0, 4547 }, 4548 #endif /* chips */ 4549 4550 #if defined(BCM_56524_A0) 4551 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_06_BCM56524_A0fmt */ 4552 /* format DESCRIPTOR_RX_06fmt */ 4553 /* nFields */ 1, 4554 /* *fields */ soc_DESCRIPTOR_RX_06_BCM56624_A0fmt_fields, 4555 /* bits */ 32, 4556 /* flags */ 0, 4557 }, 4558 #endif /* chips */ 4559 4560 #if defined(BCM_56524_B0) 4561 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_06_BCM56524_B0fmt */ 4562 /* format DESCRIPTOR_RX_06fmt */ 4563 /* nFields */ 1, 4564 /* *fields */ soc_DESCRIPTOR_RX_06_BCM56624_A0fmt_fields, 4565 /* bits */ 32, 4566 /* flags */ 0, 4567 }, 4568 #endif /* chips */ 4569 4570 #if defined(BCM_56560_A0) 4571 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_06_BCM56560_A0fmt */ 4572 /* format DESCRIPTOR_RX_06fmt */ 4573 /* nFields */ 1, 4574 /* *fields */ soc_DESCRIPTOR_RX_06_BCM53400_A0fmt_fields, 4575 /* bits */ 32, 4576 /* flags */ 0, 4577 }, 4578 #endif /* chips */ 4579 4580 #if defined(BCM_56560_B0) 4581 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_06_BCM56560_B0fmt */ 4582 /* format DESCRIPTOR_RX_06fmt */ 4583 /* nFields */ 1, 4584 /* *fields */ soc_DESCRIPTOR_RX_06_BCM53400_A0fmt_fields, 4585 /* bits */ 32, 4586 /* flags */ 0, 4587 }, 4588 #endif /* chips */ 4589 4590 #if defined(BCM_56624_A0) 4591 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_06_BCM56624_A0fmt */ 4592 /* format DESCRIPTOR_RX_06fmt */ 4593 /* nFields */ 1, 4594 /* *fields */ soc_DESCRIPTOR_RX_06_BCM56624_A0fmt_fields, 4595 /* bits */ 32, 4596 /* flags */ 0, 4597 }, 4598 #endif /* chips */ 4599 4600 #if defined(BCM_56624_B0) 4601 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_06_BCM56624_B0fmt */ 4602 /* format DESCRIPTOR_RX_06fmt */ 4603 /* nFields */ 1, 4604 /* *fields */ soc_DESCRIPTOR_RX_06_BCM56624_A0fmt_fields, 4605 /* bits */ 32, 4606 /* flags */ 0, 4607 }, 4608 #endif /* chips */ 4609 4610 #if defined(BCM_56634_A0) 4611 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_06_BCM56634_A0fmt */ 4612 /* format DESCRIPTOR_RX_06fmt */ 4613 /* nFields */ 1, 4614 /* *fields */ soc_DESCRIPTOR_RX_06_BCM56624_A0fmt_fields, 4615 /* bits */ 32, 4616 /* flags */ 0, 4617 }, 4618 #endif /* chips */ 4619 4620 #if defined(BCM_56634_B0) 4621 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_06_BCM56634_B0fmt */ 4622 /* format DESCRIPTOR_RX_06fmt */ 4623 /* nFields */ 1, 4624 /* *fields */ soc_DESCRIPTOR_RX_06_BCM56624_A0fmt_fields, 4625 /* bits */ 32, 4626 /* flags */ 0, 4627 }, 4628 #endif /* chips */ 4629 4630 #if defined(BCM_56640_A0) 4631 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_06_BCM56640_A0fmt */ 4632 /* format DESCRIPTOR_RX_06fmt */ 4633 /* nFields */ 1, 4634 /* *fields */ soc_DESCRIPTOR_RX_06_BCM56640_A0fmt_fields, 4635 /* bits */ 32, 4636 /* flags */ 0, 4637 }, 4638 #endif /* chips */ 4639 4640 #if defined(BCM_56670_A0) 4641 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_06_BCM56670_A0fmt */ 4642 /* format DESCRIPTOR_RX_06fmt */ 4643 /* nFields */ 1, 4644 /* *fields */ soc_DESCRIPTOR_RX_06_BCM53400_A0fmt_fields, 4645 /* bits */ 32, 4646 /* flags */ 0, 4647 }, 4648 #endif /* chips */ 4649 4650 #if defined(BCM_56670_B0) 4651 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_06_BCM56670_B0fmt */ 4652 /* format DESCRIPTOR_RX_06fmt */ 4653 /* nFields */ 1, 4654 /* *fields */ soc_DESCRIPTOR_RX_06_BCM53400_A0fmt_fields, 4655 /* bits */ 32, 4656 /* flags */ 0, 4657 }, 4658 #endif /* chips */ 4659 4660 #if defined(BCM_56680_A0) 4661 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_06_BCM56680_A0fmt */ 4662 /* format DESCRIPTOR_RX_06fmt */ 4663 /* nFields */ 1, 4664 /* *fields */ soc_DESCRIPTOR_RX_06_BCM56624_A0fmt_fields, 4665 /* bits */ 32, 4666 /* flags */ 0, 4667 }, 4668 #endif /* chips */ 4669 4670 #if defined(BCM_56680_B0) 4671 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_06_BCM56680_B0fmt */ 4672 /* format DESCRIPTOR_RX_06fmt */ 4673 /* nFields */ 1, 4674 /* *fields */ soc_DESCRIPTOR_RX_06_BCM56624_A0fmt_fields, 4675 /* bits */ 32, 4676 /* flags */ 0, 4677 }, 4678 #endif /* chips */ 4679 4680 #if defined(BCM_56685_A0) 4681 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_06_BCM56685_A0fmt */ 4682 /* format DESCRIPTOR_RX_06fmt */ 4683 /* nFields */ 1, 4684 /* *fields */ soc_DESCRIPTOR_RX_06_BCM56624_A0fmt_fields, 4685 /* bits */ 32, 4686 /* flags */ 0, 4687 }, 4688 #endif /* chips */ 4689 4690 #if defined(BCM_56685_B0) 4691 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_06_BCM56685_B0fmt */ 4692 /* format DESCRIPTOR_RX_06fmt */ 4693 /* nFields */ 1, 4694 /* *fields */ soc_DESCRIPTOR_RX_06_BCM56624_A0fmt_fields, 4695 /* bits */ 32, 4696 /* flags */ 0, 4697 }, 4698 #endif /* chips */ 4699 4700 #if defined(BCM_56725_A0) 4701 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_06_BCM56725_A0fmt */ 4702 /* format DESCRIPTOR_RX_06fmt */ 4703 /* nFields */ 1, 4704 /* *fields */ soc_DESCRIPTOR_RX_06_BCM56624_A0fmt_fields, 4705 /* bits */ 32, 4706 /* flags */ 0, 4707 }, 4708 #endif /* chips */ 4709 4710 #if defined(BCM_56800_A0) 4711 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_06_BCM56800_A0fmt */ 4712 /* format DESCRIPTOR_RX_06fmt */ 4713 /* nFields */ 1, 4714 /* *fields */ soc_DESCRIPTOR_RX_06fmt_fields, 4715 /* bits */ 32, 4716 /* flags */ 0, 4717 }, 4718 #endif /* chips */ 4719 4720 #if defined(BCM_56820_A0) 4721 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_06_BCM56820_A0fmt */ 4722 /* format DESCRIPTOR_RX_06fmt */ 4723 /* nFields */ 1, 4724 /* *fields */ soc_DESCRIPTOR_RX_06_BCM56624_A0fmt_fields, 4725 /* bits */ 32, 4726 /* flags */ 0, 4727 }, 4728 #endif /* chips */ 4729 4730 #if defined(BCM_56840_A0) 4731 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_06_BCM56840_A0fmt */ 4732 /* format DESCRIPTOR_RX_06fmt */ 4733 /* nFields */ 1, 4734 /* *fields */ soc_DESCRIPTOR_RX_06_BCM56624_A0fmt_fields, 4735 /* bits */ 32, 4736 /* flags */ 0, 4737 }, 4738 #endif /* chips */ 4739 4740 #if defined(BCM_56840_B0) 4741 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_06_BCM56840_B0fmt */ 4742 /* format DESCRIPTOR_RX_06fmt */ 4743 /* nFields */ 1, 4744 /* *fields */ soc_DESCRIPTOR_RX_06_BCM56624_A0fmt_fields, 4745 /* bits */ 32, 4746 /* flags */ 0, 4747 }, 4748 #endif /* chips */ 4749 4750 #if defined(BCM_56850_A0) 4751 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_06_BCM56850_A0fmt */ 4752 /* format DESCRIPTOR_RX_06fmt */ 4753 /* nFields */ 1, 4754 /* *fields */ soc_DESCRIPTOR_RX_06_BCM56640_A0fmt_fields, 4755 /* bits */ 32, 4756 /* flags */ 0, 4757 }, 4758 #endif /* chips */ 4759 4760 #if defined(BCM_56860_A0) 4761 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_06_BCM56860_A0fmt */ 4762 /* format DESCRIPTOR_RX_06fmt */ 4763 /* nFields */ 1, 4764 /* *fields */ soc_DESCRIPTOR_RX_06_BCM56640_A0fmt_fields, 4765 /* bits */ 32, 4766 /* flags */ 0, 4767 }, 4768 #endif /* chips */ 4769 4770 #if defined(BCM_56960_A0) 4771 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_06_BCM56960_A0fmt */ 4772 /* format DESCRIPTOR_RX_06fmt */ 4773 /* nFields */ 1, 4774 /* *fields */ soc_DESCRIPTOR_RX_06_BCM53400_A0fmt_fields, 4775 /* bits */ 32, 4776 /* flags */ 0, 4777 }, 4778 #endif /* chips */ 4779 4780 #if defined(BCM_56965_A0) 4781 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_06_BCM56965_A0fmt */ 4782 /* format DESCRIPTOR_RX_06fmt */ 4783 /* nFields */ 1, 4784 /* *fields */ soc_DESCRIPTOR_RX_06_BCM53400_A0fmt_fields, 4785 /* bits */ 32, 4786 /* flags */ 0, 4787 }, 4788 #endif /* chips */ 4789 4790 #if defined(BCM_56970_A0) 4791 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_06_BCM56970_A0fmt */ 4792 /* format DESCRIPTOR_RX_06fmt */ 4793 /* nFields */ 1, 4794 /* *fields */ soc_DESCRIPTOR_RX_06_BCM53400_A0fmt_fields, 4795 /* bits */ 32, 4796 /* flags */ 0, 4797 }, 4798 #endif /* chips */ 4799 4800 #if defined(BCM_88732_A0) 4801 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_06_BCM88732_A0fmt */ 4802 /* format DESCRIPTOR_RX_06fmt */ 4803 /* nFields */ 1, 4804 /* *fields */ soc_DESCRIPTOR_RX_06_BCM56624_A0fmt_fields, 4805 /* bits */ 32, 4806 /* flags */ 0, 4807 }, 4808 #endif /* chips */ 4809 4810 #if defined(BCM_53400_A0) 4811 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_07_BCM53400_A0fmt */ 4812 /* format DESCRIPTOR_RX_07fmt */ 4813 /* nFields */ 1, 4814 /* *fields */ soc_DESCRIPTOR_RX_07_BCM53400_A0fmt_fields, 4815 /* bits */ 32, 4816 /* flags */ 0, 4817 }, 4818 #endif /* chips */ 4819 4820 #if defined(BCM_53540_A0) 4821 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_07_BCM53540_A0fmt */ 4822 /* format DESCRIPTOR_RX_07fmt */ 4823 /* nFields */ 1, 4824 /* *fields */ soc_DESCRIPTOR_RX_07_BCM53400_A0fmt_fields, 4825 /* bits */ 32, 4826 /* flags */ 0, 4827 }, 4828 #endif /* chips */ 4829 4830 #if defined(BCM_53570_A0) 4831 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_07_BCM53570_A0fmt */ 4832 /* format DESCRIPTOR_RX_07fmt */ 4833 /* nFields */ 1, 4834 /* *fields */ soc_DESCRIPTOR_RX_07_BCM53400_A0fmt_fields, 4835 /* bits */ 32, 4836 /* flags */ 0, 4837 }, 4838 #endif /* chips */ 4839 4840 #if defined(BCM_53570_B0) 4841 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_07_BCM53570_B0fmt */ 4842 /* format DESCRIPTOR_RX_07fmt */ 4843 /* nFields */ 1, 4844 /* *fields */ soc_DESCRIPTOR_RX_07_BCM53400_A0fmt_fields, 4845 /* bits */ 32, 4846 /* flags */ 0, 4847 }, 4848 #endif /* chips */ 4849 4850 #if defined(BCM_56142_A0) 4851 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_07_BCM56142_A0fmt */ 4852 /* format DESCRIPTOR_RX_07fmt */ 4853 /* nFields */ 1, 4854 /* *fields */ soc_DESCRIPTOR_RX_07_BCM56624_A0fmt_fields, 4855 /* bits */ 32, 4856 /* flags */ 0, 4857 }, 4858 #endif /* chips */ 4859 4860 #if defined(BCM_56150_A0) 4861 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_07_BCM56150_A0fmt */ 4862 /* format DESCRIPTOR_RX_07fmt */ 4863 /* nFields */ 1, 4864 /* *fields */ soc_DESCRIPTOR_RX_07_BCM56640_A0fmt_fields, 4865 /* bits */ 32, 4866 /* flags */ 0, 4867 }, 4868 #endif /* chips */ 4869 4870 #if defined(BCM_56160_A0) 4871 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_07_BCM56160_A0fmt */ 4872 /* format DESCRIPTOR_RX_07fmt */ 4873 /* nFields */ 1, 4874 /* *fields */ soc_DESCRIPTOR_RX_07_BCM53400_A0fmt_fields, 4875 /* bits */ 32, 4876 /* flags */ 0, 4877 }, 4878 #endif /* chips */ 4879 4880 #if defined(BCM_56260_A0) 4881 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_07_BCM56260_A0fmt */ 4882 /* format DESCRIPTOR_RX_07fmt */ 4883 /* nFields */ 1, 4884 /* *fields */ soc_DESCRIPTOR_RX_07_BCM53400_A0fmt_fields, 4885 /* bits */ 32, 4886 /* flags */ 0, 4887 }, 4888 #endif /* chips */ 4889 4890 #if defined(BCM_56260_B0) 4891 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_07_BCM56260_B0fmt */ 4892 /* format DESCRIPTOR_RX_07fmt */ 4893 /* nFields */ 1, 4894 /* *fields */ soc_DESCRIPTOR_RX_07_BCM53400_A0fmt_fields, 4895 /* bits */ 32, 4896 /* flags */ 0, 4897 }, 4898 #endif /* chips */ 4899 4900 #if defined(BCM_56270_A0) 4901 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_07_BCM56270_A0fmt */ 4902 /* format DESCRIPTOR_RX_07fmt */ 4903 /* nFields */ 1, 4904 /* *fields */ soc_DESCRIPTOR_RX_07_BCM53400_A0fmt_fields, 4905 /* bits */ 32, 4906 /* flags */ 0, 4907 }, 4908 #endif /* chips */ 4909 4910 #if defined(BCM_56334_A0) 4911 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_07_BCM56334_A0fmt */ 4912 /* format DESCRIPTOR_RX_07fmt */ 4913 /* nFields */ 1, 4914 /* *fields */ soc_DESCRIPTOR_RX_07_BCM56624_A0fmt_fields, 4915 /* bits */ 32, 4916 /* flags */ 0, 4917 }, 4918 #endif /* chips */ 4919 4920 #if defined(BCM_56334_B0) 4921 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_07_BCM56334_B0fmt */ 4922 /* format DESCRIPTOR_RX_07fmt */ 4923 /* nFields */ 1, 4924 /* *fields */ soc_DESCRIPTOR_RX_07_BCM56624_A0fmt_fields, 4925 /* bits */ 32, 4926 /* flags */ 0, 4927 }, 4928 #endif /* chips */ 4929 4930 #if defined(BCM_56340_A0) 4931 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_07_BCM56340_A0fmt */ 4932 /* format DESCRIPTOR_RX_07fmt */ 4933 /* nFields */ 1, 4934 /* *fields */ soc_DESCRIPTOR_RX_07_BCM56640_A0fmt_fields, 4935 /* bits */ 32, 4936 /* flags */ 0, 4937 }, 4938 #endif /* chips */ 4939 4940 #if defined(BCM_56440_A0) 4941 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_07_BCM56440_A0fmt */ 4942 /* format DESCRIPTOR_RX_07fmt */ 4943 /* nFields */ 1, 4944 /* *fields */ soc_DESCRIPTOR_RX_07_BCM56624_A0fmt_fields, 4945 /* bits */ 32, 4946 /* flags */ 0, 4947 }, 4948 #endif /* chips */ 4949 4950 #if defined(BCM_56440_B0) 4951 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_07_BCM56440_B0fmt */ 4952 /* format DESCRIPTOR_RX_07fmt */ 4953 /* nFields */ 1, 4954 /* *fields */ soc_DESCRIPTOR_RX_07_BCM56624_A0fmt_fields, 4955 /* bits */ 32, 4956 /* flags */ 0, 4957 }, 4958 #endif /* chips */ 4959 4960 #if defined(BCM_56450_A0) 4961 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_07_BCM56450_A0fmt */ 4962 /* format DESCRIPTOR_RX_07fmt */ 4963 /* nFields */ 1, 4964 /* *fields */ soc_DESCRIPTOR_RX_07_BCM56640_A0fmt_fields, 4965 /* bits */ 32, 4966 /* flags */ 0, 4967 }, 4968 #endif /* chips */ 4969 4970 #if defined(BCM_56450_B0) 4971 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_07_BCM56450_B0fmt */ 4972 /* format DESCRIPTOR_RX_07fmt */ 4973 /* nFields */ 1, 4974 /* *fields */ soc_DESCRIPTOR_RX_07_BCM56640_A0fmt_fields, 4975 /* bits */ 32, 4976 /* flags */ 0, 4977 }, 4978 #endif /* chips */ 4979 4980 #if defined(BCM_56450_B1) 4981 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_07_BCM56450_B1fmt */ 4982 /* format DESCRIPTOR_RX_07fmt */ 4983 /* nFields */ 1, 4984 /* *fields */ soc_DESCRIPTOR_RX_07_BCM56640_A0fmt_fields, 4985 /* bits */ 32, 4986 /* flags */ 0, 4987 }, 4988 #endif /* chips */ 4989 4990 #if defined(BCM_56524_A0) 4991 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_07_BCM56524_A0fmt */ 4992 /* format DESCRIPTOR_RX_07fmt */ 4993 /* nFields */ 1, 4994 /* *fields */ soc_DESCRIPTOR_RX_07_BCM56624_A0fmt_fields, 4995 /* bits */ 32, 4996 /* flags */ 0, 4997 }, 4998 #endif /* chips */ 4999 5000 #if defined(BCM_56524_B0) 5001 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_07_BCM56524_B0fmt */ 5002 /* format DESCRIPTOR_RX_07fmt */ 5003 /* nFields */ 1, 5004 /* *fields */ soc_DESCRIPTOR_RX_07_BCM56624_A0fmt_fields, 5005 /* bits */ 32, 5006 /* flags */ 0, 5007 }, 5008 #endif /* chips */ 5009 5010 #if defined(BCM_56560_A0) 5011 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_07_BCM56560_A0fmt */ 5012 /* format DESCRIPTOR_RX_07fmt */ 5013 /* nFields */ 1, 5014 /* *fields */ soc_DESCRIPTOR_RX_07_BCM53400_A0fmt_fields, 5015 /* bits */ 32, 5016 /* flags */ 0, 5017 }, 5018 #endif /* chips */ 5019 5020 #if defined(BCM_56560_B0) 5021 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_07_BCM56560_B0fmt */ 5022 /* format DESCRIPTOR_RX_07fmt */ 5023 /* nFields */ 1, 5024 /* *fields */ soc_DESCRIPTOR_RX_07_BCM53400_A0fmt_fields, 5025 /* bits */ 32, 5026 /* flags */ 0, 5027 }, 5028 #endif /* chips */ 5029 5030 #if defined(BCM_56624_A0) 5031 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_07_BCM56624_A0fmt */ 5032 /* format DESCRIPTOR_RX_07fmt */ 5033 /* nFields */ 1, 5034 /* *fields */ soc_DESCRIPTOR_RX_07_BCM56624_A0fmt_fields, 5035 /* bits */ 32, 5036 /* flags */ 0, 5037 }, 5038 #endif /* chips */ 5039 5040 #if defined(BCM_56624_B0) 5041 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_07_BCM56624_B0fmt */ 5042 /* format DESCRIPTOR_RX_07fmt */ 5043 /* nFields */ 1, 5044 /* *fields */ soc_DESCRIPTOR_RX_07_BCM56624_A0fmt_fields, 5045 /* bits */ 32, 5046 /* flags */ 0, 5047 }, 5048 #endif /* chips */ 5049 5050 #if defined(BCM_56634_A0) 5051 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_07_BCM56634_A0fmt */ 5052 /* format DESCRIPTOR_RX_07fmt */ 5053 /* nFields */ 1, 5054 /* *fields */ soc_DESCRIPTOR_RX_07_BCM56624_A0fmt_fields, 5055 /* bits */ 32, 5056 /* flags */ 0, 5057 }, 5058 #endif /* chips */ 5059 5060 #if defined(BCM_56634_B0) 5061 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_07_BCM56634_B0fmt */ 5062 /* format DESCRIPTOR_RX_07fmt */ 5063 /* nFields */ 1, 5064 /* *fields */ soc_DESCRIPTOR_RX_07_BCM56624_A0fmt_fields, 5065 /* bits */ 32, 5066 /* flags */ 0, 5067 }, 5068 #endif /* chips */ 5069 5070 #if defined(BCM_56640_A0) 5071 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_07_BCM56640_A0fmt */ 5072 /* format DESCRIPTOR_RX_07fmt */ 5073 /* nFields */ 1, 5074 /* *fields */ soc_DESCRIPTOR_RX_07_BCM56640_A0fmt_fields, 5075 /* bits */ 32, 5076 /* flags */ 0, 5077 }, 5078 #endif /* chips */ 5079 5080 #if defined(BCM_56670_A0) 5081 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_07_BCM56670_A0fmt */ 5082 /* format DESCRIPTOR_RX_07fmt */ 5083 /* nFields */ 1, 5084 /* *fields */ soc_DESCRIPTOR_RX_07_BCM53400_A0fmt_fields, 5085 /* bits */ 32, 5086 /* flags */ 0, 5087 }, 5088 #endif /* chips */ 5089 5090 #if defined(BCM_56670_B0) 5091 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_07_BCM56670_B0fmt */ 5092 /* format DESCRIPTOR_RX_07fmt */ 5093 /* nFields */ 1, 5094 /* *fields */ soc_DESCRIPTOR_RX_07_BCM53400_A0fmt_fields, 5095 /* bits */ 32, 5096 /* flags */ 0, 5097 }, 5098 #endif /* chips */ 5099 5100 #if defined(BCM_56680_A0) 5101 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_07_BCM56680_A0fmt */ 5102 /* format DESCRIPTOR_RX_07fmt */ 5103 /* nFields */ 1, 5104 /* *fields */ soc_DESCRIPTOR_RX_07_BCM56624_A0fmt_fields, 5105 /* bits */ 32, 5106 /* flags */ 0, 5107 }, 5108 #endif /* chips */ 5109 5110 #if defined(BCM_56680_B0) 5111 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_07_BCM56680_B0fmt */ 5112 /* format DESCRIPTOR_RX_07fmt */ 5113 /* nFields */ 1, 5114 /* *fields */ soc_DESCRIPTOR_RX_07_BCM56624_A0fmt_fields, 5115 /* bits */ 32, 5116 /* flags */ 0, 5117 }, 5118 #endif /* chips */ 5119 5120 #if defined(BCM_56685_A0) 5121 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_07_BCM56685_A0fmt */ 5122 /* format DESCRIPTOR_RX_07fmt */ 5123 /* nFields */ 1, 5124 /* *fields */ soc_DESCRIPTOR_RX_07_BCM56624_A0fmt_fields, 5125 /* bits */ 32, 5126 /* flags */ 0, 5127 }, 5128 #endif /* chips */ 5129 5130 #if defined(BCM_56685_B0) 5131 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_07_BCM56685_B0fmt */ 5132 /* format DESCRIPTOR_RX_07fmt */ 5133 /* nFields */ 1, 5134 /* *fields */ soc_DESCRIPTOR_RX_07_BCM56624_A0fmt_fields, 5135 /* bits */ 32, 5136 /* flags */ 0, 5137 }, 5138 #endif /* chips */ 5139 5140 #if defined(BCM_56725_A0) 5141 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_07_BCM56725_A0fmt */ 5142 /* format DESCRIPTOR_RX_07fmt */ 5143 /* nFields */ 1, 5144 /* *fields */ soc_DESCRIPTOR_RX_07_BCM56624_A0fmt_fields, 5145 /* bits */ 32, 5146 /* flags */ 0, 5147 }, 5148 #endif /* chips */ 5149 5150 #if defined(BCM_56820_A0) 5151 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_07_BCM56820_A0fmt */ 5152 /* format DESCRIPTOR_RX_07fmt */ 5153 /* nFields */ 1, 5154 /* *fields */ soc_DESCRIPTOR_RX_07_BCM56624_A0fmt_fields, 5155 /* bits */ 32, 5156 /* flags */ 0, 5157 }, 5158 #endif /* chips */ 5159 5160 #if defined(BCM_56840_A0) 5161 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_07_BCM56840_A0fmt */ 5162 /* format DESCRIPTOR_RX_07fmt */ 5163 /* nFields */ 1, 5164 /* *fields */ soc_DESCRIPTOR_RX_07_BCM56624_A0fmt_fields, 5165 /* bits */ 32, 5166 /* flags */ 0, 5167 }, 5168 #endif /* chips */ 5169 5170 #if defined(BCM_56840_B0) 5171 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_07_BCM56840_B0fmt */ 5172 /* format DESCRIPTOR_RX_07fmt */ 5173 /* nFields */ 1, 5174 /* *fields */ soc_DESCRIPTOR_RX_07_BCM56624_A0fmt_fields, 5175 /* bits */ 32, 5176 /* flags */ 0, 5177 }, 5178 #endif /* chips */ 5179 5180 #if defined(BCM_56850_A0) 5181 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_07_BCM56850_A0fmt */ 5182 /* format DESCRIPTOR_RX_07fmt */ 5183 /* nFields */ 1, 5184 /* *fields */ soc_DESCRIPTOR_RX_07_BCM56640_A0fmt_fields, 5185 /* bits */ 32, 5186 /* flags */ 0, 5187 }, 5188 #endif /* chips */ 5189 5190 #if defined(BCM_56860_A0) 5191 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_07_BCM56860_A0fmt */ 5192 /* format DESCRIPTOR_RX_07fmt */ 5193 /* nFields */ 1, 5194 /* *fields */ soc_DESCRIPTOR_RX_07_BCM56640_A0fmt_fields, 5195 /* bits */ 32, 5196 /* flags */ 0, 5197 }, 5198 #endif /* chips */ 5199 5200 #if defined(BCM_56960_A0) 5201 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_07_BCM56960_A0fmt */ 5202 /* format DESCRIPTOR_RX_07fmt */ 5203 /* nFields */ 1, 5204 /* *fields */ soc_DESCRIPTOR_RX_07_BCM53400_A0fmt_fields, 5205 /* bits */ 32, 5206 /* flags */ 0, 5207 }, 5208 #endif /* chips */ 5209 5210 #if defined(BCM_56965_A0) 5211 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_07_BCM56965_A0fmt */ 5212 /* format DESCRIPTOR_RX_07fmt */ 5213 /* nFields */ 1, 5214 /* *fields */ soc_DESCRIPTOR_RX_07_BCM53400_A0fmt_fields, 5215 /* bits */ 32, 5216 /* flags */ 0, 5217 }, 5218 #endif /* chips */ 5219 5220 #if defined(BCM_56970_A0) 5221 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_07_BCM56970_A0fmt */ 5222 /* format DESCRIPTOR_RX_07fmt */ 5223 /* nFields */ 1, 5224 /* *fields */ soc_DESCRIPTOR_RX_07_BCM53400_A0fmt_fields, 5225 /* bits */ 32, 5226 /* flags */ 0, 5227 }, 5228 #endif /* chips */ 5229 5230 #if defined(BCM_88732_A0) 5231 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_07_BCM88732_A0fmt */ 5232 /* format DESCRIPTOR_RX_07fmt */ 5233 /* nFields */ 1, 5234 /* *fields */ soc_DESCRIPTOR_RX_07_BCM56624_A0fmt_fields, 5235 /* bits */ 32, 5236 /* flags */ 0, 5237 }, 5238 #endif /* chips */ 5239 5240 #if defined(BCM_53400_A0) 5241 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_08_BCM53400_A0fmt */ 5242 /* format DESCRIPTOR_RX_08fmt */ 5243 /* nFields */ 1, 5244 /* *fields */ soc_DESCRIPTOR_RX_08_BCM53400_A0fmt_fields, 5245 /* bits */ 32, 5246 /* flags */ 0, 5247 }, 5248 #endif /* chips */ 5249 5250 #if defined(BCM_53540_A0) 5251 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_08_BCM53540_A0fmt */ 5252 /* format DESCRIPTOR_RX_08fmt */ 5253 /* nFields */ 1, 5254 /* *fields */ soc_DESCRIPTOR_RX_08_BCM53400_A0fmt_fields, 5255 /* bits */ 32, 5256 /* flags */ 0, 5257 }, 5258 #endif /* chips */ 5259 5260 #if defined(BCM_53570_A0) 5261 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_08_BCM53570_A0fmt */ 5262 /* format DESCRIPTOR_RX_08fmt */ 5263 /* nFields */ 1, 5264 /* *fields */ soc_DESCRIPTOR_RX_08_BCM53400_A0fmt_fields, 5265 /* bits */ 32, 5266 /* flags */ 0, 5267 }, 5268 #endif /* chips */ 5269 5270 #if defined(BCM_53570_B0) 5271 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_08_BCM53570_B0fmt */ 5272 /* format DESCRIPTOR_RX_08fmt */ 5273 /* nFields */ 1, 5274 /* *fields */ soc_DESCRIPTOR_RX_08_BCM53400_A0fmt_fields, 5275 /* bits */ 32, 5276 /* flags */ 0, 5277 }, 5278 #endif /* chips */ 5279 5280 #if defined(BCM_56142_A0) 5281 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_08_BCM56142_A0fmt */ 5282 /* format DESCRIPTOR_RX_08fmt */ 5283 /* nFields */ 1, 5284 /* *fields */ soc_DESCRIPTOR_RX_08_BCM56624_A0fmt_fields, 5285 /* bits */ 32, 5286 /* flags */ 0, 5287 }, 5288 #endif /* chips */ 5289 5290 #if defined(BCM_56150_A0) 5291 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_08_BCM56150_A0fmt */ 5292 /* format DESCRIPTOR_RX_08fmt */ 5293 /* nFields */ 1, 5294 /* *fields */ soc_DESCRIPTOR_RX_08_BCM56640_A0fmt_fields, 5295 /* bits */ 32, 5296 /* flags */ 0, 5297 }, 5298 #endif /* chips */ 5299 5300 #if defined(BCM_56160_A0) 5301 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_08_BCM56160_A0fmt */ 5302 /* format DESCRIPTOR_RX_08fmt */ 5303 /* nFields */ 1, 5304 /* *fields */ soc_DESCRIPTOR_RX_08_BCM53400_A0fmt_fields, 5305 /* bits */ 32, 5306 /* flags */ 0, 5307 }, 5308 #endif /* chips */ 5309 5310 #if defined(BCM_56260_A0) 5311 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_08_BCM56260_A0fmt */ 5312 /* format DESCRIPTOR_RX_08fmt */ 5313 /* nFields */ 1, 5314 /* *fields */ soc_DESCRIPTOR_RX_08_BCM53400_A0fmt_fields, 5315 /* bits */ 32, 5316 /* flags */ 0, 5317 }, 5318 #endif /* chips */ 5319 5320 #if defined(BCM_56260_B0) 5321 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_08_BCM56260_B0fmt */ 5322 /* format DESCRIPTOR_RX_08fmt */ 5323 /* nFields */ 1, 5324 /* *fields */ soc_DESCRIPTOR_RX_08_BCM53400_A0fmt_fields, 5325 /* bits */ 32, 5326 /* flags */ 0, 5327 }, 5328 #endif /* chips */ 5329 5330 #if defined(BCM_56270_A0) 5331 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_08_BCM56270_A0fmt */ 5332 /* format DESCRIPTOR_RX_08fmt */ 5333 /* nFields */ 1, 5334 /* *fields */ soc_DESCRIPTOR_RX_08_BCM53400_A0fmt_fields, 5335 /* bits */ 32, 5336 /* flags */ 0, 5337 }, 5338 #endif /* chips */ 5339 5340 #if defined(BCM_56334_A0) 5341 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_08_BCM56334_A0fmt */ 5342 /* format DESCRIPTOR_RX_08fmt */ 5343 /* nFields */ 1, 5344 /* *fields */ soc_DESCRIPTOR_RX_08_BCM56624_A0fmt_fields, 5345 /* bits */ 32, 5346 /* flags */ 0, 5347 }, 5348 #endif /* chips */ 5349 5350 #if defined(BCM_56334_B0) 5351 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_08_BCM56334_B0fmt */ 5352 /* format DESCRIPTOR_RX_08fmt */ 5353 /* nFields */ 1, 5354 /* *fields */ soc_DESCRIPTOR_RX_08_BCM56624_A0fmt_fields, 5355 /* bits */ 32, 5356 /* flags */ 0, 5357 }, 5358 #endif /* chips */ 5359 5360 #if defined(BCM_56340_A0) 5361 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_08_BCM56340_A0fmt */ 5362 /* format DESCRIPTOR_RX_08fmt */ 5363 /* nFields */ 1, 5364 /* *fields */ soc_DESCRIPTOR_RX_08_BCM56640_A0fmt_fields, 5365 /* bits */ 32, 5366 /* flags */ 0, 5367 }, 5368 #endif /* chips */ 5369 5370 #if defined(BCM_56440_A0) 5371 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_08_BCM56440_A0fmt */ 5372 /* format DESCRIPTOR_RX_08fmt */ 5373 /* nFields */ 1, 5374 /* *fields */ soc_DESCRIPTOR_RX_08_BCM56624_A0fmt_fields, 5375 /* bits */ 32, 5376 /* flags */ 0, 5377 }, 5378 #endif /* chips */ 5379 5380 #if defined(BCM_56440_B0) 5381 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_08_BCM56440_B0fmt */ 5382 /* format DESCRIPTOR_RX_08fmt */ 5383 /* nFields */ 1, 5384 /* *fields */ soc_DESCRIPTOR_RX_08_BCM56624_A0fmt_fields, 5385 /* bits */ 32, 5386 /* flags */ 0, 5387 }, 5388 #endif /* chips */ 5389 5390 #if defined(BCM_56450_A0) 5391 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_08_BCM56450_A0fmt */ 5392 /* format DESCRIPTOR_RX_08fmt */ 5393 /* nFields */ 1, 5394 /* *fields */ soc_DESCRIPTOR_RX_08_BCM56640_A0fmt_fields, 5395 /* bits */ 32, 5396 /* flags */ 0, 5397 }, 5398 #endif /* chips */ 5399 5400 #if defined(BCM_56450_B0) 5401 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_08_BCM56450_B0fmt */ 5402 /* format DESCRIPTOR_RX_08fmt */ 5403 /* nFields */ 1, 5404 /* *fields */ soc_DESCRIPTOR_RX_08_BCM56640_A0fmt_fields, 5405 /* bits */ 32, 5406 /* flags */ 0, 5407 }, 5408 #endif /* chips */ 5409 5410 #if defined(BCM_56450_B1) 5411 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_08_BCM56450_B1fmt */ 5412 /* format DESCRIPTOR_RX_08fmt */ 5413 /* nFields */ 1, 5414 /* *fields */ soc_DESCRIPTOR_RX_08_BCM56640_A0fmt_fields, 5415 /* bits */ 32, 5416 /* flags */ 0, 5417 }, 5418 #endif /* chips */ 5419 5420 #if defined(BCM_56524_A0) 5421 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_08_BCM56524_A0fmt */ 5422 /* format DESCRIPTOR_RX_08fmt */ 5423 /* nFields */ 1, 5424 /* *fields */ soc_DESCRIPTOR_RX_08_BCM56624_A0fmt_fields, 5425 /* bits */ 32, 5426 /* flags */ 0, 5427 }, 5428 #endif /* chips */ 5429 5430 #if defined(BCM_56524_B0) 5431 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_08_BCM56524_B0fmt */ 5432 /* format DESCRIPTOR_RX_08fmt */ 5433 /* nFields */ 1, 5434 /* *fields */ soc_DESCRIPTOR_RX_08_BCM56624_A0fmt_fields, 5435 /* bits */ 32, 5436 /* flags */ 0, 5437 }, 5438 #endif /* chips */ 5439 5440 #if defined(BCM_56560_A0) 5441 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_08_BCM56560_A0fmt */ 5442 /* format DESCRIPTOR_RX_08fmt */ 5443 /* nFields */ 1, 5444 /* *fields */ soc_DESCRIPTOR_RX_08_BCM53400_A0fmt_fields, 5445 /* bits */ 32, 5446 /* flags */ 0, 5447 }, 5448 #endif /* chips */ 5449 5450 #if defined(BCM_56560_B0) 5451 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_08_BCM56560_B0fmt */ 5452 /* format DESCRIPTOR_RX_08fmt */ 5453 /* nFields */ 1, 5454 /* *fields */ soc_DESCRIPTOR_RX_08_BCM53400_A0fmt_fields, 5455 /* bits */ 32, 5456 /* flags */ 0, 5457 }, 5458 #endif /* chips */ 5459 5460 #if defined(BCM_56624_A0) 5461 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_08_BCM56624_A0fmt */ 5462 /* format DESCRIPTOR_RX_08fmt */ 5463 /* nFields */ 1, 5464 /* *fields */ soc_DESCRIPTOR_RX_08_BCM56624_A0fmt_fields, 5465 /* bits */ 32, 5466 /* flags */ 0, 5467 }, 5468 #endif /* chips */ 5469 5470 #if defined(BCM_56624_B0) 5471 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_08_BCM56624_B0fmt */ 5472 /* format DESCRIPTOR_RX_08fmt */ 5473 /* nFields */ 1, 5474 /* *fields */ soc_DESCRIPTOR_RX_08_BCM56624_A0fmt_fields, 5475 /* bits */ 32, 5476 /* flags */ 0, 5477 }, 5478 #endif /* chips */ 5479 5480 #if defined(BCM_56634_A0) 5481 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_08_BCM56634_A0fmt */ 5482 /* format DESCRIPTOR_RX_08fmt */ 5483 /* nFields */ 1, 5484 /* *fields */ soc_DESCRIPTOR_RX_08_BCM56624_A0fmt_fields, 5485 /* bits */ 32, 5486 /* flags */ 0, 5487 }, 5488 #endif /* chips */ 5489 5490 #if defined(BCM_56634_B0) 5491 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_08_BCM56634_B0fmt */ 5492 /* format DESCRIPTOR_RX_08fmt */ 5493 /* nFields */ 1, 5494 /* *fields */ soc_DESCRIPTOR_RX_08_BCM56624_A0fmt_fields, 5495 /* bits */ 32, 5496 /* flags */ 0, 5497 }, 5498 #endif /* chips */ 5499 5500 #if defined(BCM_56640_A0) 5501 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_08_BCM56640_A0fmt */ 5502 /* format DESCRIPTOR_RX_08fmt */ 5503 /* nFields */ 1, 5504 /* *fields */ soc_DESCRIPTOR_RX_08_BCM56640_A0fmt_fields, 5505 /* bits */ 32, 5506 /* flags */ 0, 5507 }, 5508 #endif /* chips */ 5509 5510 #if defined(BCM_56670_A0) 5511 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_08_BCM56670_A0fmt */ 5512 /* format DESCRIPTOR_RX_08fmt */ 5513 /* nFields */ 1, 5514 /* *fields */ soc_DESCRIPTOR_RX_08_BCM53400_A0fmt_fields, 5515 /* bits */ 32, 5516 /* flags */ 0, 5517 }, 5518 #endif /* chips */ 5519 5520 #if defined(BCM_56670_B0) 5521 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_08_BCM56670_B0fmt */ 5522 /* format DESCRIPTOR_RX_08fmt */ 5523 /* nFields */ 1, 5524 /* *fields */ soc_DESCRIPTOR_RX_08_BCM53400_A0fmt_fields, 5525 /* bits */ 32, 5526 /* flags */ 0, 5527 }, 5528 #endif /* chips */ 5529 5530 #if defined(BCM_56680_A0) 5531 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_08_BCM56680_A0fmt */ 5532 /* format DESCRIPTOR_RX_08fmt */ 5533 /* nFields */ 1, 5534 /* *fields */ soc_DESCRIPTOR_RX_08_BCM56624_A0fmt_fields, 5535 /* bits */ 32, 5536 /* flags */ 0, 5537 }, 5538 #endif /* chips */ 5539 5540 #if defined(BCM_56680_B0) 5541 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_08_BCM56680_B0fmt */ 5542 /* format DESCRIPTOR_RX_08fmt */ 5543 /* nFields */ 1, 5544 /* *fields */ soc_DESCRIPTOR_RX_08_BCM56624_A0fmt_fields, 5545 /* bits */ 32, 5546 /* flags */ 0, 5547 }, 5548 #endif /* chips */ 5549 5550 #if defined(BCM_56685_A0) 5551 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_08_BCM56685_A0fmt */ 5552 /* format DESCRIPTOR_RX_08fmt */ 5553 /* nFields */ 1, 5554 /* *fields */ soc_DESCRIPTOR_RX_08_BCM56624_A0fmt_fields, 5555 /* bits */ 32, 5556 /* flags */ 0, 5557 }, 5558 #endif /* chips */ 5559 5560 #if defined(BCM_56685_B0) 5561 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_08_BCM56685_B0fmt */ 5562 /* format DESCRIPTOR_RX_08fmt */ 5563 /* nFields */ 1, 5564 /* *fields */ soc_DESCRIPTOR_RX_08_BCM56624_A0fmt_fields, 5565 /* bits */ 32, 5566 /* flags */ 0, 5567 }, 5568 #endif /* chips */ 5569 5570 #if defined(BCM_56725_A0) 5571 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_08_BCM56725_A0fmt */ 5572 /* format DESCRIPTOR_RX_08fmt */ 5573 /* nFields */ 1, 5574 /* *fields */ soc_DESCRIPTOR_RX_08_BCM56624_A0fmt_fields, 5575 /* bits */ 32, 5576 /* flags */ 0, 5577 }, 5578 #endif /* chips */ 5579 5580 #if defined(BCM_56820_A0) 5581 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_08_BCM56820_A0fmt */ 5582 /* format DESCRIPTOR_RX_08fmt */ 5583 /* nFields */ 1, 5584 /* *fields */ soc_DESCRIPTOR_RX_08_BCM56624_A0fmt_fields, 5585 /* bits */ 32, 5586 /* flags */ 0, 5587 }, 5588 #endif /* chips */ 5589 5590 #if defined(BCM_56840_A0) 5591 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_08_BCM56840_A0fmt */ 5592 /* format DESCRIPTOR_RX_08fmt */ 5593 /* nFields */ 1, 5594 /* *fields */ soc_DESCRIPTOR_RX_08_BCM56624_A0fmt_fields, 5595 /* bits */ 32, 5596 /* flags */ 0, 5597 }, 5598 #endif /* chips */ 5599 5600 #if defined(BCM_56840_B0) 5601 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_08_BCM56840_B0fmt */ 5602 /* format DESCRIPTOR_RX_08fmt */ 5603 /* nFields */ 1, 5604 /* *fields */ soc_DESCRIPTOR_RX_08_BCM56624_A0fmt_fields, 5605 /* bits */ 32, 5606 /* flags */ 0, 5607 }, 5608 #endif /* chips */ 5609 5610 #if defined(BCM_56850_A0) 5611 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_08_BCM56850_A0fmt */ 5612 /* format DESCRIPTOR_RX_08fmt */ 5613 /* nFields */ 1, 5614 /* *fields */ soc_DESCRIPTOR_RX_08_BCM56640_A0fmt_fields, 5615 /* bits */ 32, 5616 /* flags */ 0, 5617 }, 5618 #endif /* chips */ 5619 5620 #if defined(BCM_56860_A0) 5621 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_08_BCM56860_A0fmt */ 5622 /* format DESCRIPTOR_RX_08fmt */ 5623 /* nFields */ 1, 5624 /* *fields */ soc_DESCRIPTOR_RX_08_BCM56640_A0fmt_fields, 5625 /* bits */ 32, 5626 /* flags */ 0, 5627 }, 5628 #endif /* chips */ 5629 5630 #if defined(BCM_56960_A0) 5631 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_08_BCM56960_A0fmt */ 5632 /* format DESCRIPTOR_RX_08fmt */ 5633 /* nFields */ 1, 5634 /* *fields */ soc_DESCRIPTOR_RX_08_BCM53400_A0fmt_fields, 5635 /* bits */ 32, 5636 /* flags */ 0, 5637 }, 5638 #endif /* chips */ 5639 5640 #if defined(BCM_56965_A0) 5641 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_08_BCM56965_A0fmt */ 5642 /* format DESCRIPTOR_RX_08fmt */ 5643 /* nFields */ 1, 5644 /* *fields */ soc_DESCRIPTOR_RX_08_BCM53400_A0fmt_fields, 5645 /* bits */ 32, 5646 /* flags */ 0, 5647 }, 5648 #endif /* chips */ 5649 5650 #if defined(BCM_56970_A0) 5651 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_08_BCM56970_A0fmt */ 5652 /* format DESCRIPTOR_RX_08fmt */ 5653 /* nFields */ 1, 5654 /* *fields */ soc_DESCRIPTOR_RX_08_BCM53400_A0fmt_fields, 5655 /* bits */ 32, 5656 /* flags */ 0, 5657 }, 5658 #endif /* chips */ 5659 5660 #if defined(BCM_88732_A0) 5661 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_08_BCM88732_A0fmt */ 5662 /* format DESCRIPTOR_RX_08fmt */ 5663 /* nFields */ 1, 5664 /* *fields */ soc_DESCRIPTOR_RX_08_BCM56624_A0fmt_fields, 5665 /* bits */ 32, 5666 /* flags */ 0, 5667 }, 5668 #endif /* chips */ 5669 5670 #if defined(BCM_53400_A0) 5671 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_09_BCM53400_A0fmt */ 5672 /* format DESCRIPTOR_RX_09fmt */ 5673 /* nFields */ 1, 5674 /* *fields */ soc_DESCRIPTOR_RX_09_BCM53400_A0fmt_fields, 5675 /* bits */ 32, 5676 /* flags */ 0, 5677 }, 5678 #endif /* chips */ 5679 5680 #if defined(BCM_53540_A0) 5681 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_09_BCM53540_A0fmt */ 5682 /* format DESCRIPTOR_RX_09fmt */ 5683 /* nFields */ 1, 5684 /* *fields */ soc_DESCRIPTOR_RX_09_BCM53400_A0fmt_fields, 5685 /* bits */ 32, 5686 /* flags */ 0, 5687 }, 5688 #endif /* chips */ 5689 5690 #if defined(BCM_53570_A0) 5691 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_09_BCM53570_A0fmt */ 5692 /* format DESCRIPTOR_RX_09fmt */ 5693 /* nFields */ 1, 5694 /* *fields */ soc_DESCRIPTOR_RX_09_BCM53400_A0fmt_fields, 5695 /* bits */ 32, 5696 /* flags */ 0, 5697 }, 5698 #endif /* chips */ 5699 5700 #if defined(BCM_53570_B0) 5701 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_09_BCM53570_B0fmt */ 5702 /* format DESCRIPTOR_RX_09fmt */ 5703 /* nFields */ 1, 5704 /* *fields */ soc_DESCRIPTOR_RX_09_BCM53400_A0fmt_fields, 5705 /* bits */ 32, 5706 /* flags */ 0, 5707 }, 5708 #endif /* chips */ 5709 5710 #if defined(BCM_56142_A0) 5711 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_09_BCM56142_A0fmt */ 5712 /* format DESCRIPTOR_RX_09fmt */ 5713 /* nFields */ 1, 5714 /* *fields */ soc_DESCRIPTOR_RX_09_BCM56624_A0fmt_fields, 5715 /* bits */ 32, 5716 /* flags */ 0, 5717 }, 5718 #endif /* chips */ 5719 5720 #if defined(BCM_56150_A0) 5721 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_09_BCM56150_A0fmt */ 5722 /* format DESCRIPTOR_RX_09fmt */ 5723 /* nFields */ 1, 5724 /* *fields */ soc_DESCRIPTOR_RX_09_BCM56640_A0fmt_fields, 5725 /* bits */ 32, 5726 /* flags */ 0, 5727 }, 5728 #endif /* chips */ 5729 5730 #if defined(BCM_56160_A0) 5731 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_09_BCM56160_A0fmt */ 5732 /* format DESCRIPTOR_RX_09fmt */ 5733 /* nFields */ 1, 5734 /* *fields */ soc_DESCRIPTOR_RX_09_BCM53400_A0fmt_fields, 5735 /* bits */ 32, 5736 /* flags */ 0, 5737 }, 5738 #endif /* chips */ 5739 5740 #if defined(BCM_56260_A0) 5741 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_09_BCM56260_A0fmt */ 5742 /* format DESCRIPTOR_RX_09fmt */ 5743 /* nFields */ 1, 5744 /* *fields */ soc_DESCRIPTOR_RX_09_BCM53400_A0fmt_fields, 5745 /* bits */ 32, 5746 /* flags */ 0, 5747 }, 5748 #endif /* chips */ 5749 5750 #if defined(BCM_56260_B0) 5751 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_09_BCM56260_B0fmt */ 5752 /* format DESCRIPTOR_RX_09fmt */ 5753 /* nFields */ 1, 5754 /* *fields */ soc_DESCRIPTOR_RX_09_BCM53400_A0fmt_fields, 5755 /* bits */ 32, 5756 /* flags */ 0, 5757 }, 5758 #endif /* chips */ 5759 5760 #if defined(BCM_56270_A0) 5761 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_09_BCM56270_A0fmt */ 5762 /* format DESCRIPTOR_RX_09fmt */ 5763 /* nFields */ 1, 5764 /* *fields */ soc_DESCRIPTOR_RX_09_BCM53400_A0fmt_fields, 5765 /* bits */ 32, 5766 /* flags */ 0, 5767 }, 5768 #endif /* chips */ 5769 5770 #if defined(BCM_56334_A0) 5771 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_09_BCM56334_A0fmt */ 5772 /* format DESCRIPTOR_RX_09fmt */ 5773 /* nFields */ 1, 5774 /* *fields */ soc_DESCRIPTOR_RX_09_BCM56624_A0fmt_fields, 5775 /* bits */ 32, 5776 /* flags */ 0, 5777 }, 5778 #endif /* chips */ 5779 5780 #if defined(BCM_56334_B0) 5781 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_09_BCM56334_B0fmt */ 5782 /* format DESCRIPTOR_RX_09fmt */ 5783 /* nFields */ 1, 5784 /* *fields */ soc_DESCRIPTOR_RX_09_BCM56624_A0fmt_fields, 5785 /* bits */ 32, 5786 /* flags */ 0, 5787 }, 5788 #endif /* chips */ 5789 5790 #if defined(BCM_56340_A0) 5791 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_09_BCM56340_A0fmt */ 5792 /* format DESCRIPTOR_RX_09fmt */ 5793 /* nFields */ 1, 5794 /* *fields */ soc_DESCRIPTOR_RX_09_BCM56640_A0fmt_fields, 5795 /* bits */ 32, 5796 /* flags */ 0, 5797 }, 5798 #endif /* chips */ 5799 5800 #if defined(BCM_56440_A0) 5801 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_09_BCM56440_A0fmt */ 5802 /* format DESCRIPTOR_RX_09fmt */ 5803 /* nFields */ 1, 5804 /* *fields */ soc_DESCRIPTOR_RX_09_BCM56624_A0fmt_fields, 5805 /* bits */ 32, 5806 /* flags */ 0, 5807 }, 5808 #endif /* chips */ 5809 5810 #if defined(BCM_56440_B0) 5811 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_09_BCM56440_B0fmt */ 5812 /* format DESCRIPTOR_RX_09fmt */ 5813 /* nFields */ 1, 5814 /* *fields */ soc_DESCRIPTOR_RX_09_BCM56624_A0fmt_fields, 5815 /* bits */ 32, 5816 /* flags */ 0, 5817 }, 5818 #endif /* chips */ 5819 5820 #if defined(BCM_56450_A0) 5821 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_09_BCM56450_A0fmt */ 5822 /* format DESCRIPTOR_RX_09fmt */ 5823 /* nFields */ 1, 5824 /* *fields */ soc_DESCRIPTOR_RX_09_BCM56640_A0fmt_fields, 5825 /* bits */ 32, 5826 /* flags */ 0, 5827 }, 5828 #endif /* chips */ 5829 5830 #if defined(BCM_56450_B0) 5831 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_09_BCM56450_B0fmt */ 5832 /* format DESCRIPTOR_RX_09fmt */ 5833 /* nFields */ 1, 5834 /* *fields */ soc_DESCRIPTOR_RX_09_BCM56640_A0fmt_fields, 5835 /* bits */ 32, 5836 /* flags */ 0, 5837 }, 5838 #endif /* chips */ 5839 5840 #if defined(BCM_56450_B1) 5841 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_09_BCM56450_B1fmt */ 5842 /* format DESCRIPTOR_RX_09fmt */ 5843 /* nFields */ 1, 5844 /* *fields */ soc_DESCRIPTOR_RX_09_BCM56640_A0fmt_fields, 5845 /* bits */ 32, 5846 /* flags */ 0, 5847 }, 5848 #endif /* chips */ 5849 5850 #if defined(BCM_56524_A0) 5851 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_09_BCM56524_A0fmt */ 5852 /* format DESCRIPTOR_RX_09fmt */ 5853 /* nFields */ 1, 5854 /* *fields */ soc_DESCRIPTOR_RX_09_BCM56624_A0fmt_fields, 5855 /* bits */ 32, 5856 /* flags */ 0, 5857 }, 5858 #endif /* chips */ 5859 5860 #if defined(BCM_56524_B0) 5861 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_09_BCM56524_B0fmt */ 5862 /* format DESCRIPTOR_RX_09fmt */ 5863 /* nFields */ 1, 5864 /* *fields */ soc_DESCRIPTOR_RX_09_BCM56624_A0fmt_fields, 5865 /* bits */ 32, 5866 /* flags */ 0, 5867 }, 5868 #endif /* chips */ 5869 5870 #if defined(BCM_56560_A0) 5871 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_09_BCM56560_A0fmt */ 5872 /* format DESCRIPTOR_RX_09fmt */ 5873 /* nFields */ 1, 5874 /* *fields */ soc_DESCRIPTOR_RX_09_BCM53400_A0fmt_fields, 5875 /* bits */ 32, 5876 /* flags */ 0, 5877 }, 5878 #endif /* chips */ 5879 5880 #if defined(BCM_56560_B0) 5881 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_09_BCM56560_B0fmt */ 5882 /* format DESCRIPTOR_RX_09fmt */ 5883 /* nFields */ 1, 5884 /* *fields */ soc_DESCRIPTOR_RX_09_BCM53400_A0fmt_fields, 5885 /* bits */ 32, 5886 /* flags */ 0, 5887 }, 5888 #endif /* chips */ 5889 5890 #if defined(BCM_56624_A0) 5891 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_09_BCM56624_A0fmt */ 5892 /* format DESCRIPTOR_RX_09fmt */ 5893 /* nFields */ 1, 5894 /* *fields */ soc_DESCRIPTOR_RX_09_BCM56624_A0fmt_fields, 5895 /* bits */ 32, 5896 /* flags */ 0, 5897 }, 5898 #endif /* chips */ 5899 5900 #if defined(BCM_56624_B0) 5901 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_09_BCM56624_B0fmt */ 5902 /* format DESCRIPTOR_RX_09fmt */ 5903 /* nFields */ 1, 5904 /* *fields */ soc_DESCRIPTOR_RX_09_BCM56624_A0fmt_fields, 5905 /* bits */ 32, 5906 /* flags */ 0, 5907 }, 5908 #endif /* chips */ 5909 5910 #if defined(BCM_56634_A0) 5911 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_09_BCM56634_A0fmt */ 5912 /* format DESCRIPTOR_RX_09fmt */ 5913 /* nFields */ 1, 5914 /* *fields */ soc_DESCRIPTOR_RX_09_BCM56624_A0fmt_fields, 5915 /* bits */ 32, 5916 /* flags */ 0, 5917 }, 5918 #endif /* chips */ 5919 5920 #if defined(BCM_56634_B0) 5921 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_09_BCM56634_B0fmt */ 5922 /* format DESCRIPTOR_RX_09fmt */ 5923 /* nFields */ 1, 5924 /* *fields */ soc_DESCRIPTOR_RX_09_BCM56624_A0fmt_fields, 5925 /* bits */ 32, 5926 /* flags */ 0, 5927 }, 5928 #endif /* chips */ 5929 5930 #if defined(BCM_56640_A0) 5931 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_09_BCM56640_A0fmt */ 5932 /* format DESCRIPTOR_RX_09fmt */ 5933 /* nFields */ 1, 5934 /* *fields */ soc_DESCRIPTOR_RX_09_BCM56640_A0fmt_fields, 5935 /* bits */ 32, 5936 /* flags */ 0, 5937 }, 5938 #endif /* chips */ 5939 5940 #if defined(BCM_56670_A0) 5941 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_09_BCM56670_A0fmt */ 5942 /* format DESCRIPTOR_RX_09fmt */ 5943 /* nFields */ 1, 5944 /* *fields */ soc_DESCRIPTOR_RX_09_BCM53400_A0fmt_fields, 5945 /* bits */ 32, 5946 /* flags */ 0, 5947 }, 5948 #endif /* chips */ 5949 5950 #if defined(BCM_56670_B0) 5951 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_09_BCM56670_B0fmt */ 5952 /* format DESCRIPTOR_RX_09fmt */ 5953 /* nFields */ 1, 5954 /* *fields */ soc_DESCRIPTOR_RX_09_BCM53400_A0fmt_fields, 5955 /* bits */ 32, 5956 /* flags */ 0, 5957 }, 5958 #endif /* chips */ 5959 5960 #if defined(BCM_56680_A0) 5961 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_09_BCM56680_A0fmt */ 5962 /* format DESCRIPTOR_RX_09fmt */ 5963 /* nFields */ 1, 5964 /* *fields */ soc_DESCRIPTOR_RX_09_BCM56624_A0fmt_fields, 5965 /* bits */ 32, 5966 /* flags */ 0, 5967 }, 5968 #endif /* chips */ 5969 5970 #if defined(BCM_56680_B0) 5971 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_09_BCM56680_B0fmt */ 5972 /* format DESCRIPTOR_RX_09fmt */ 5973 /* nFields */ 1, 5974 /* *fields */ soc_DESCRIPTOR_RX_09_BCM56624_A0fmt_fields, 5975 /* bits */ 32, 5976 /* flags */ 0, 5977 }, 5978 #endif /* chips */ 5979 5980 #if defined(BCM_56685_A0) 5981 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_09_BCM56685_A0fmt */ 5982 /* format DESCRIPTOR_RX_09fmt */ 5983 /* nFields */ 1, 5984 /* *fields */ soc_DESCRIPTOR_RX_09_BCM56624_A0fmt_fields, 5985 /* bits */ 32, 5986 /* flags */ 0, 5987 }, 5988 #endif /* chips */ 5989 5990 #if defined(BCM_56685_B0) 5991 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_09_BCM56685_B0fmt */ 5992 /* format DESCRIPTOR_RX_09fmt */ 5993 /* nFields */ 1, 5994 /* *fields */ soc_DESCRIPTOR_RX_09_BCM56624_A0fmt_fields, 5995 /* bits */ 32, 5996 /* flags */ 0, 5997 }, 5998 #endif /* chips */ 5999 6000 #if defined(BCM_56725_A0) 6001 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_09_BCM56725_A0fmt */ 6002 /* format DESCRIPTOR_RX_09fmt */ 6003 /* nFields */ 1, 6004 /* *fields */ soc_DESCRIPTOR_RX_09_BCM56624_A0fmt_fields, 6005 /* bits */ 32, 6006 /* flags */ 0, 6007 }, 6008 #endif /* chips */ 6009 6010 #if defined(BCM_56820_A0) 6011 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_09_BCM56820_A0fmt */ 6012 /* format DESCRIPTOR_RX_09fmt */ 6013 /* nFields */ 1, 6014 /* *fields */ soc_DESCRIPTOR_RX_09_BCM56624_A0fmt_fields, 6015 /* bits */ 32, 6016 /* flags */ 0, 6017 }, 6018 #endif /* chips */ 6019 6020 #if defined(BCM_56840_A0) 6021 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_09_BCM56840_A0fmt */ 6022 /* format DESCRIPTOR_RX_09fmt */ 6023 /* nFields */ 1, 6024 /* *fields */ soc_DESCRIPTOR_RX_09_BCM56624_A0fmt_fields, 6025 /* bits */ 32, 6026 /* flags */ 0, 6027 }, 6028 #endif /* chips */ 6029 6030 #if defined(BCM_56840_B0) 6031 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_09_BCM56840_B0fmt */ 6032 /* format DESCRIPTOR_RX_09fmt */ 6033 /* nFields */ 1, 6034 /* *fields */ soc_DESCRIPTOR_RX_09_BCM56624_A0fmt_fields, 6035 /* bits */ 32, 6036 /* flags */ 0, 6037 }, 6038 #endif /* chips */ 6039 6040 #if defined(BCM_56850_A0) 6041 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_09_BCM56850_A0fmt */ 6042 /* format DESCRIPTOR_RX_09fmt */ 6043 /* nFields */ 1, 6044 /* *fields */ soc_DESCRIPTOR_RX_09_BCM56640_A0fmt_fields, 6045 /* bits */ 32, 6046 /* flags */ 0, 6047 }, 6048 #endif /* chips */ 6049 6050 #if defined(BCM_56860_A0) 6051 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_09_BCM56860_A0fmt */ 6052 /* format DESCRIPTOR_RX_09fmt */ 6053 /* nFields */ 1, 6054 /* *fields */ soc_DESCRIPTOR_RX_09_BCM56640_A0fmt_fields, 6055 /* bits */ 32, 6056 /* flags */ 0, 6057 }, 6058 #endif /* chips */ 6059 6060 #if defined(BCM_56960_A0) 6061 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_09_BCM56960_A0fmt */ 6062 /* format DESCRIPTOR_RX_09fmt */ 6063 /* nFields */ 1, 6064 /* *fields */ soc_DESCRIPTOR_RX_09_BCM53400_A0fmt_fields, 6065 /* bits */ 32, 6066 /* flags */ 0, 6067 }, 6068 #endif /* chips */ 6069 6070 #if defined(BCM_56965_A0) 6071 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_09_BCM56965_A0fmt */ 6072 /* format DESCRIPTOR_RX_09fmt */ 6073 /* nFields */ 1, 6074 /* *fields */ soc_DESCRIPTOR_RX_09_BCM53400_A0fmt_fields, 6075 /* bits */ 32, 6076 /* flags */ 0, 6077 }, 6078 #endif /* chips */ 6079 6080 #if defined(BCM_56970_A0) 6081 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_09_BCM56970_A0fmt */ 6082 /* format DESCRIPTOR_RX_09fmt */ 6083 /* nFields */ 1, 6084 /* *fields */ soc_DESCRIPTOR_RX_09_BCM53400_A0fmt_fields, 6085 /* bits */ 32, 6086 /* flags */ 0, 6087 }, 6088 #endif /* chips */ 6089 6090 #if defined(BCM_88732_A0) 6091 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_09_BCM88732_A0fmt */ 6092 /* format DESCRIPTOR_RX_09fmt */ 6093 /* nFields */ 1, 6094 /* *fields */ soc_DESCRIPTOR_RX_09_BCM56624_A0fmt_fields, 6095 /* bits */ 32, 6096 /* flags */ 0, 6097 }, 6098 #endif /* chips */ 6099 6100 #if defined(BCM_53400_A0) 6101 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_10_BCM53400_A0fmt */ 6102 /* format DESCRIPTOR_RX_10fmt */ 6103 /* nFields */ 1, 6104 /* *fields */ soc_DESCRIPTOR_RX_10_BCM53400_A0fmt_fields, 6105 /* bits */ 32, 6106 /* flags */ 0, 6107 }, 6108 #endif /* chips */ 6109 6110 #if defined(BCM_53540_A0) 6111 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_10_BCM53540_A0fmt */ 6112 /* format DESCRIPTOR_RX_10fmt */ 6113 /* nFields */ 1, 6114 /* *fields */ soc_DESCRIPTOR_RX_10_BCM53400_A0fmt_fields, 6115 /* bits */ 32, 6116 /* flags */ 0, 6117 }, 6118 #endif /* chips */ 6119 6120 #if defined(BCM_53570_A0) 6121 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_10_BCM53570_A0fmt */ 6122 /* format DESCRIPTOR_RX_10fmt */ 6123 /* nFields */ 1, 6124 /* *fields */ soc_DESCRIPTOR_RX_10_BCM53400_A0fmt_fields, 6125 /* bits */ 32, 6126 /* flags */ 0, 6127 }, 6128 #endif /* chips */ 6129 6130 #if defined(BCM_53570_B0) 6131 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_10_BCM53570_B0fmt */ 6132 /* format DESCRIPTOR_RX_10fmt */ 6133 /* nFields */ 1, 6134 /* *fields */ soc_DESCRIPTOR_RX_10_BCM53400_A0fmt_fields, 6135 /* bits */ 32, 6136 /* flags */ 0, 6137 }, 6138 #endif /* chips */ 6139 6140 #if defined(BCM_56142_A0) 6141 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_10_BCM56142_A0fmt */ 6142 /* format DESCRIPTOR_RX_10fmt */ 6143 /* nFields */ 1, 6144 /* *fields */ soc_DESCRIPTOR_RX_10_BCM56624_A0fmt_fields, 6145 /* bits */ 32, 6146 /* flags */ 0, 6147 }, 6148 #endif /* chips */ 6149 6150 #if defined(BCM_56150_A0) 6151 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_10_BCM56150_A0fmt */ 6152 /* format DESCRIPTOR_RX_10fmt */ 6153 /* nFields */ 1, 6154 /* *fields */ soc_DESCRIPTOR_RX_10_BCM56640_A0fmt_fields, 6155 /* bits */ 32, 6156 /* flags */ 0, 6157 }, 6158 #endif /* chips */ 6159 6160 #if defined(BCM_56160_A0) 6161 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_10_BCM56160_A0fmt */ 6162 /* format DESCRIPTOR_RX_10fmt */ 6163 /* nFields */ 1, 6164 /* *fields */ soc_DESCRIPTOR_RX_10_BCM53400_A0fmt_fields, 6165 /* bits */ 32, 6166 /* flags */ 0, 6167 }, 6168 #endif /* chips */ 6169 6170 #if defined(BCM_56260_A0) 6171 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_10_BCM56260_A0fmt */ 6172 /* format DESCRIPTOR_RX_10fmt */ 6173 /* nFields */ 1, 6174 /* *fields */ soc_DESCRIPTOR_RX_10_BCM53400_A0fmt_fields, 6175 /* bits */ 32, 6176 /* flags */ 0, 6177 }, 6178 #endif /* chips */ 6179 6180 #if defined(BCM_56260_B0) 6181 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_10_BCM56260_B0fmt */ 6182 /* format DESCRIPTOR_RX_10fmt */ 6183 /* nFields */ 1, 6184 /* *fields */ soc_DESCRIPTOR_RX_10_BCM53400_A0fmt_fields, 6185 /* bits */ 32, 6186 /* flags */ 0, 6187 }, 6188 #endif /* chips */ 6189 6190 #if defined(BCM_56270_A0) 6191 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_10_BCM56270_A0fmt */ 6192 /* format DESCRIPTOR_RX_10fmt */ 6193 /* nFields */ 1, 6194 /* *fields */ soc_DESCRIPTOR_RX_10_BCM53400_A0fmt_fields, 6195 /* bits */ 32, 6196 /* flags */ 0, 6197 }, 6198 #endif /* chips */ 6199 6200 #if defined(BCM_56334_A0) 6201 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_10_BCM56334_A0fmt */ 6202 /* format DESCRIPTOR_RX_10fmt */ 6203 /* nFields */ 1, 6204 /* *fields */ soc_DESCRIPTOR_RX_10_BCM56624_A0fmt_fields, 6205 /* bits */ 32, 6206 /* flags */ 0, 6207 }, 6208 #endif /* chips */ 6209 6210 #if defined(BCM_56334_B0) 6211 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_10_BCM56334_B0fmt */ 6212 /* format DESCRIPTOR_RX_10fmt */ 6213 /* nFields */ 1, 6214 /* *fields */ soc_DESCRIPTOR_RX_10_BCM56624_A0fmt_fields, 6215 /* bits */ 32, 6216 /* flags */ 0, 6217 }, 6218 #endif /* chips */ 6219 6220 #if defined(BCM_56340_A0) 6221 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_10_BCM56340_A0fmt */ 6222 /* format DESCRIPTOR_RX_10fmt */ 6223 /* nFields */ 1, 6224 /* *fields */ soc_DESCRIPTOR_RX_10_BCM56640_A0fmt_fields, 6225 /* bits */ 32, 6226 /* flags */ 0, 6227 }, 6228 #endif /* chips */ 6229 6230 #if defined(BCM_56440_A0) 6231 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_10_BCM56440_A0fmt */ 6232 /* format DESCRIPTOR_RX_10fmt */ 6233 /* nFields */ 1, 6234 /* *fields */ soc_DESCRIPTOR_RX_10_BCM56624_A0fmt_fields, 6235 /* bits */ 32, 6236 /* flags */ 0, 6237 }, 6238 #endif /* chips */ 6239 6240 #if defined(BCM_56440_B0) 6241 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_10_BCM56440_B0fmt */ 6242 /* format DESCRIPTOR_RX_10fmt */ 6243 /* nFields */ 1, 6244 /* *fields */ soc_DESCRIPTOR_RX_10_BCM56624_A0fmt_fields, 6245 /* bits */ 32, 6246 /* flags */ 0, 6247 }, 6248 #endif /* chips */ 6249 6250 #if defined(BCM_56450_A0) 6251 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_10_BCM56450_A0fmt */ 6252 /* format DESCRIPTOR_RX_10fmt */ 6253 /* nFields */ 1, 6254 /* *fields */ soc_DESCRIPTOR_RX_10_BCM56640_A0fmt_fields, 6255 /* bits */ 32, 6256 /* flags */ 0, 6257 }, 6258 #endif /* chips */ 6259 6260 #if defined(BCM_56450_B0) 6261 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_10_BCM56450_B0fmt */ 6262 /* format DESCRIPTOR_RX_10fmt */ 6263 /* nFields */ 1, 6264 /* *fields */ soc_DESCRIPTOR_RX_10_BCM56640_A0fmt_fields, 6265 /* bits */ 32, 6266 /* flags */ 0, 6267 }, 6268 #endif /* chips */ 6269 6270 #if defined(BCM_56450_B1) 6271 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_10_BCM56450_B1fmt */ 6272 /* format DESCRIPTOR_RX_10fmt */ 6273 /* nFields */ 1, 6274 /* *fields */ soc_DESCRIPTOR_RX_10_BCM56640_A0fmt_fields, 6275 /* bits */ 32, 6276 /* flags */ 0, 6277 }, 6278 #endif /* chips */ 6279 6280 #if defined(BCM_56524_A0) 6281 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_10_BCM56524_A0fmt */ 6282 /* format DESCRIPTOR_RX_10fmt */ 6283 /* nFields */ 1, 6284 /* *fields */ soc_DESCRIPTOR_RX_10_BCM56624_A0fmt_fields, 6285 /* bits */ 32, 6286 /* flags */ 0, 6287 }, 6288 #endif /* chips */ 6289 6290 #if defined(BCM_56524_B0) 6291 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_10_BCM56524_B0fmt */ 6292 /* format DESCRIPTOR_RX_10fmt */ 6293 /* nFields */ 1, 6294 /* *fields */ soc_DESCRIPTOR_RX_10_BCM56624_A0fmt_fields, 6295 /* bits */ 32, 6296 /* flags */ 0, 6297 }, 6298 #endif /* chips */ 6299 6300 #if defined(BCM_56560_A0) 6301 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_10_BCM56560_A0fmt */ 6302 /* format DESCRIPTOR_RX_10fmt */ 6303 /* nFields */ 1, 6304 /* *fields */ soc_DESCRIPTOR_RX_10_BCM53400_A0fmt_fields, 6305 /* bits */ 32, 6306 /* flags */ 0, 6307 }, 6308 #endif /* chips */ 6309 6310 #if defined(BCM_56560_B0) 6311 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_10_BCM56560_B0fmt */ 6312 /* format DESCRIPTOR_RX_10fmt */ 6313 /* nFields */ 1, 6314 /* *fields */ soc_DESCRIPTOR_RX_10_BCM53400_A0fmt_fields, 6315 /* bits */ 32, 6316 /* flags */ 0, 6317 }, 6318 #endif /* chips */ 6319 6320 #if defined(BCM_56624_A0) 6321 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_10_BCM56624_A0fmt */ 6322 /* format DESCRIPTOR_RX_10fmt */ 6323 /* nFields */ 1, 6324 /* *fields */ soc_DESCRIPTOR_RX_10_BCM56624_A0fmt_fields, 6325 /* bits */ 32, 6326 /* flags */ 0, 6327 }, 6328 #endif /* chips */ 6329 6330 #if defined(BCM_56624_B0) 6331 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_10_BCM56624_B0fmt */ 6332 /* format DESCRIPTOR_RX_10fmt */ 6333 /* nFields */ 1, 6334 /* *fields */ soc_DESCRIPTOR_RX_10_BCM56624_A0fmt_fields, 6335 /* bits */ 32, 6336 /* flags */ 0, 6337 }, 6338 #endif /* chips */ 6339 6340 #if defined(BCM_56634_A0) 6341 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_10_BCM56634_A0fmt */ 6342 /* format DESCRIPTOR_RX_10fmt */ 6343 /* nFields */ 1, 6344 /* *fields */ soc_DESCRIPTOR_RX_10_BCM56624_A0fmt_fields, 6345 /* bits */ 32, 6346 /* flags */ 0, 6347 }, 6348 #endif /* chips */ 6349 6350 #if defined(BCM_56634_B0) 6351 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_10_BCM56634_B0fmt */ 6352 /* format DESCRIPTOR_RX_10fmt */ 6353 /* nFields */ 1, 6354 /* *fields */ soc_DESCRIPTOR_RX_10_BCM56624_A0fmt_fields, 6355 /* bits */ 32, 6356 /* flags */ 0, 6357 }, 6358 #endif /* chips */ 6359 6360 #if defined(BCM_56640_A0) 6361 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_10_BCM56640_A0fmt */ 6362 /* format DESCRIPTOR_RX_10fmt */ 6363 /* nFields */ 1, 6364 /* *fields */ soc_DESCRIPTOR_RX_10_BCM56640_A0fmt_fields, 6365 /* bits */ 32, 6366 /* flags */ 0, 6367 }, 6368 #endif /* chips */ 6369 6370 #if defined(BCM_56670_A0) 6371 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_10_BCM56670_A0fmt */ 6372 /* format DESCRIPTOR_RX_10fmt */ 6373 /* nFields */ 1, 6374 /* *fields */ soc_DESCRIPTOR_RX_10_BCM53400_A0fmt_fields, 6375 /* bits */ 32, 6376 /* flags */ 0, 6377 }, 6378 #endif /* chips */ 6379 6380 #if defined(BCM_56670_B0) 6381 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_10_BCM56670_B0fmt */ 6382 /* format DESCRIPTOR_RX_10fmt */ 6383 /* nFields */ 1, 6384 /* *fields */ soc_DESCRIPTOR_RX_10_BCM53400_A0fmt_fields, 6385 /* bits */ 32, 6386 /* flags */ 0, 6387 }, 6388 #endif /* chips */ 6389 6390 #if defined(BCM_56680_A0) 6391 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_10_BCM56680_A0fmt */ 6392 /* format DESCRIPTOR_RX_10fmt */ 6393 /* nFields */ 1, 6394 /* *fields */ soc_DESCRIPTOR_RX_10_BCM56624_A0fmt_fields, 6395 /* bits */ 32, 6396 /* flags */ 0, 6397 }, 6398 #endif /* chips */ 6399 6400 #if defined(BCM_56680_B0) 6401 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_10_BCM56680_B0fmt */ 6402 /* format DESCRIPTOR_RX_10fmt */ 6403 /* nFields */ 1, 6404 /* *fields */ soc_DESCRIPTOR_RX_10_BCM56624_A0fmt_fields, 6405 /* bits */ 32, 6406 /* flags */ 0, 6407 }, 6408 #endif /* chips */ 6409 6410 #if defined(BCM_56685_A0) 6411 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_10_BCM56685_A0fmt */ 6412 /* format DESCRIPTOR_RX_10fmt */ 6413 /* nFields */ 1, 6414 /* *fields */ soc_DESCRIPTOR_RX_10_BCM56624_A0fmt_fields, 6415 /* bits */ 32, 6416 /* flags */ 0, 6417 }, 6418 #endif /* chips */ 6419 6420 #if defined(BCM_56685_B0) 6421 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_10_BCM56685_B0fmt */ 6422 /* format DESCRIPTOR_RX_10fmt */ 6423 /* nFields */ 1, 6424 /* *fields */ soc_DESCRIPTOR_RX_10_BCM56624_A0fmt_fields, 6425 /* bits */ 32, 6426 /* flags */ 0, 6427 }, 6428 #endif /* chips */ 6429 6430 #if defined(BCM_56725_A0) 6431 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_10_BCM56725_A0fmt */ 6432 /* format DESCRIPTOR_RX_10fmt */ 6433 /* nFields */ 1, 6434 /* *fields */ soc_DESCRIPTOR_RX_10_BCM56624_A0fmt_fields, 6435 /* bits */ 32, 6436 /* flags */ 0, 6437 }, 6438 #endif /* chips */ 6439 6440 #if defined(BCM_56820_A0) 6441 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_10_BCM56820_A0fmt */ 6442 /* format DESCRIPTOR_RX_10fmt */ 6443 /* nFields */ 1, 6444 /* *fields */ soc_DESCRIPTOR_RX_10_BCM56624_A0fmt_fields, 6445 /* bits */ 32, 6446 /* flags */ 0, 6447 }, 6448 #endif /* chips */ 6449 6450 #if defined(BCM_56840_A0) 6451 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_10_BCM56840_A0fmt */ 6452 /* format DESCRIPTOR_RX_10fmt */ 6453 /* nFields */ 1, 6454 /* *fields */ soc_DESCRIPTOR_RX_10_BCM56624_A0fmt_fields, 6455 /* bits */ 32, 6456 /* flags */ 0, 6457 }, 6458 #endif /* chips */ 6459 6460 #if defined(BCM_56840_B0) 6461 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_10_BCM56840_B0fmt */ 6462 /* format DESCRIPTOR_RX_10fmt */ 6463 /* nFields */ 1, 6464 /* *fields */ soc_DESCRIPTOR_RX_10_BCM56624_A0fmt_fields, 6465 /* bits */ 32, 6466 /* flags */ 0, 6467 }, 6468 #endif /* chips */ 6469 6470 #if defined(BCM_56850_A0) 6471 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_10_BCM56850_A0fmt */ 6472 /* format DESCRIPTOR_RX_10fmt */ 6473 /* nFields */ 1, 6474 /* *fields */ soc_DESCRIPTOR_RX_10_BCM56640_A0fmt_fields, 6475 /* bits */ 32, 6476 /* flags */ 0, 6477 }, 6478 #endif /* chips */ 6479 6480 #if defined(BCM_56860_A0) 6481 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_10_BCM56860_A0fmt */ 6482 /* format DESCRIPTOR_RX_10fmt */ 6483 /* nFields */ 1, 6484 /* *fields */ soc_DESCRIPTOR_RX_10_BCM56640_A0fmt_fields, 6485 /* bits */ 32, 6486 /* flags */ 0, 6487 }, 6488 #endif /* chips */ 6489 6490 #if defined(BCM_56960_A0) 6491 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_10_BCM56960_A0fmt */ 6492 /* format DESCRIPTOR_RX_10fmt */ 6493 /* nFields */ 1, 6494 /* *fields */ soc_DESCRIPTOR_RX_10_BCM53400_A0fmt_fields, 6495 /* bits */ 32, 6496 /* flags */ 0, 6497 }, 6498 #endif /* chips */ 6499 6500 #if defined(BCM_56965_A0) 6501 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_10_BCM56965_A0fmt */ 6502 /* format DESCRIPTOR_RX_10fmt */ 6503 /* nFields */ 1, 6504 /* *fields */ soc_DESCRIPTOR_RX_10_BCM53400_A0fmt_fields, 6505 /* bits */ 32, 6506 /* flags */ 0, 6507 }, 6508 #endif /* chips */ 6509 6510 #if defined(BCM_56970_A0) 6511 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_10_BCM56970_A0fmt */ 6512 /* format DESCRIPTOR_RX_10fmt */ 6513 /* nFields */ 1, 6514 /* *fields */ soc_DESCRIPTOR_RX_10_BCM53400_A0fmt_fields, 6515 /* bits */ 32, 6516 /* flags */ 0, 6517 }, 6518 #endif /* chips */ 6519 6520 #if defined(BCM_88732_A0) 6521 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_10_BCM88732_A0fmt */ 6522 /* format DESCRIPTOR_RX_10fmt */ 6523 /* nFields */ 1, 6524 /* *fields */ soc_DESCRIPTOR_RX_10_BCM56624_A0fmt_fields, 6525 /* bits */ 32, 6526 /* flags */ 0, 6527 }, 6528 #endif /* chips */ 6529 6530 #if defined(BCM_53400_A0) 6531 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_11_BCM53400_A0fmt */ 6532 /* format DESCRIPTOR_RX_11fmt */ 6533 /* nFields */ 1, 6534 /* *fields */ soc_DESCRIPTOR_RX_11_BCM53400_A0fmt_fields, 6535 /* bits */ 32, 6536 /* flags */ 0, 6537 }, 6538 #endif /* chips */ 6539 6540 #if defined(BCM_53540_A0) 6541 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_11_BCM53540_A0fmt */ 6542 /* format DESCRIPTOR_RX_11fmt */ 6543 /* nFields */ 1, 6544 /* *fields */ soc_DESCRIPTOR_RX_11_BCM53400_A0fmt_fields, 6545 /* bits */ 32, 6546 /* flags */ 0, 6547 }, 6548 #endif /* chips */ 6549 6550 #if defined(BCM_53570_A0) 6551 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_11_BCM53570_A0fmt */ 6552 /* format DESCRIPTOR_RX_11fmt */ 6553 /* nFields */ 1, 6554 /* *fields */ soc_DESCRIPTOR_RX_11_BCM53400_A0fmt_fields, 6555 /* bits */ 32, 6556 /* flags */ 0, 6557 }, 6558 #endif /* chips */ 6559 6560 #if defined(BCM_53570_B0) 6561 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_11_BCM53570_B0fmt */ 6562 /* format DESCRIPTOR_RX_11fmt */ 6563 /* nFields */ 1, 6564 /* *fields */ soc_DESCRIPTOR_RX_11_BCM53400_A0fmt_fields, 6565 /* bits */ 32, 6566 /* flags */ 0, 6567 }, 6568 #endif /* chips */ 6569 6570 #if defined(BCM_56150_A0) 6571 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_11_BCM56150_A0fmt */ 6572 /* format DESCRIPTOR_RX_11fmt */ 6573 /* nFields */ 1, 6574 /* *fields */ soc_DESCRIPTOR_RX_11_BCM56640_A0fmt_fields, 6575 /* bits */ 32, 6576 /* flags */ 0, 6577 }, 6578 #endif /* chips */ 6579 6580 #if defined(BCM_56160_A0) 6581 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_11_BCM56160_A0fmt */ 6582 /* format DESCRIPTOR_RX_11fmt */ 6583 /* nFields */ 1, 6584 /* *fields */ soc_DESCRIPTOR_RX_11_BCM53400_A0fmt_fields, 6585 /* bits */ 32, 6586 /* flags */ 0, 6587 }, 6588 #endif /* chips */ 6589 6590 #if defined(BCM_56260_A0) 6591 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_11_BCM56260_A0fmt */ 6592 /* format DESCRIPTOR_RX_11fmt */ 6593 /* nFields */ 1, 6594 /* *fields */ soc_DESCRIPTOR_RX_11_BCM53400_A0fmt_fields, 6595 /* bits */ 32, 6596 /* flags */ 0, 6597 }, 6598 #endif /* chips */ 6599 6600 #if defined(BCM_56260_B0) 6601 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_11_BCM56260_B0fmt */ 6602 /* format DESCRIPTOR_RX_11fmt */ 6603 /* nFields */ 1, 6604 /* *fields */ soc_DESCRIPTOR_RX_11_BCM53400_A0fmt_fields, 6605 /* bits */ 32, 6606 /* flags */ 0, 6607 }, 6608 #endif /* chips */ 6609 6610 #if defined(BCM_56270_A0) 6611 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_11_BCM56270_A0fmt */ 6612 /* format DESCRIPTOR_RX_11fmt */ 6613 /* nFields */ 1, 6614 /* *fields */ soc_DESCRIPTOR_RX_11_BCM53400_A0fmt_fields, 6615 /* bits */ 32, 6616 /* flags */ 0, 6617 }, 6618 #endif /* chips */ 6619 6620 #if defined(BCM_56340_A0) 6621 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_11_BCM56340_A0fmt */ 6622 /* format DESCRIPTOR_RX_11fmt */ 6623 /* nFields */ 1, 6624 /* *fields */ soc_DESCRIPTOR_RX_11_BCM56640_A0fmt_fields, 6625 /* bits */ 32, 6626 /* flags */ 0, 6627 }, 6628 #endif /* chips */ 6629 6630 #if defined(BCM_56450_A0) 6631 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_11_BCM56450_A0fmt */ 6632 /* format DESCRIPTOR_RX_11fmt */ 6633 /* nFields */ 1, 6634 /* *fields */ soc_DESCRIPTOR_RX_11_BCM56640_A0fmt_fields, 6635 /* bits */ 32, 6636 /* flags */ 0, 6637 }, 6638 #endif /* chips */ 6639 6640 #if defined(BCM_56450_B0) 6641 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_11_BCM56450_B0fmt */ 6642 /* format DESCRIPTOR_RX_11fmt */ 6643 /* nFields */ 1, 6644 /* *fields */ soc_DESCRIPTOR_RX_11_BCM56640_A0fmt_fields, 6645 /* bits */ 32, 6646 /* flags */ 0, 6647 }, 6648 #endif /* chips */ 6649 6650 #if defined(BCM_56450_B1) 6651 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_11_BCM56450_B1fmt */ 6652 /* format DESCRIPTOR_RX_11fmt */ 6653 /* nFields */ 1, 6654 /* *fields */ soc_DESCRIPTOR_RX_11_BCM56640_A0fmt_fields, 6655 /* bits */ 32, 6656 /* flags */ 0, 6657 }, 6658 #endif /* chips */ 6659 6660 #if defined(BCM_56560_A0) 6661 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_11_BCM56560_A0fmt */ 6662 /* format DESCRIPTOR_RX_11fmt */ 6663 /* nFields */ 1, 6664 /* *fields */ soc_DESCRIPTOR_RX_11_BCM53400_A0fmt_fields, 6665 /* bits */ 32, 6666 /* flags */ 0, 6667 }, 6668 #endif /* chips */ 6669 6670 #if defined(BCM_56560_B0) 6671 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_11_BCM56560_B0fmt */ 6672 /* format DESCRIPTOR_RX_11fmt */ 6673 /* nFields */ 1, 6674 /* *fields */ soc_DESCRIPTOR_RX_11_BCM53400_A0fmt_fields, 6675 /* bits */ 32, 6676 /* flags */ 0, 6677 }, 6678 #endif /* chips */ 6679 6680 #if defined(BCM_56640_A0) 6681 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_11_BCM56640_A0fmt */ 6682 /* format DESCRIPTOR_RX_11fmt */ 6683 /* nFields */ 1, 6684 /* *fields */ soc_DESCRIPTOR_RX_11_BCM56640_A0fmt_fields, 6685 /* bits */ 32, 6686 /* flags */ 0, 6687 }, 6688 #endif /* chips */ 6689 6690 #if defined(BCM_56670_A0) 6691 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_11_BCM56670_A0fmt */ 6692 /* format DESCRIPTOR_RX_11fmt */ 6693 /* nFields */ 1, 6694 /* *fields */ soc_DESCRIPTOR_RX_11_BCM53400_A0fmt_fields, 6695 /* bits */ 32, 6696 /* flags */ 0, 6697 }, 6698 #endif /* chips */ 6699 6700 #if defined(BCM_56670_B0) 6701 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_11_BCM56670_B0fmt */ 6702 /* format DESCRIPTOR_RX_11fmt */ 6703 /* nFields */ 1, 6704 /* *fields */ soc_DESCRIPTOR_RX_11_BCM53400_A0fmt_fields, 6705 /* bits */ 32, 6706 /* flags */ 0, 6707 }, 6708 #endif /* chips */ 6709 6710 #if defined(BCM_56850_A0) 6711 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_11_BCM56850_A0fmt */ 6712 /* format DESCRIPTOR_RX_11fmt */ 6713 /* nFields */ 1, 6714 /* *fields */ soc_DESCRIPTOR_RX_11_BCM56640_A0fmt_fields, 6715 /* bits */ 32, 6716 /* flags */ 0, 6717 }, 6718 #endif /* chips */ 6719 6720 #if defined(BCM_56860_A0) 6721 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_11_BCM56860_A0fmt */ 6722 /* format DESCRIPTOR_RX_11fmt */ 6723 /* nFields */ 1, 6724 /* *fields */ soc_DESCRIPTOR_RX_11_BCM56640_A0fmt_fields, 6725 /* bits */ 32, 6726 /* flags */ 0, 6727 }, 6728 #endif /* chips */ 6729 6730 #if defined(BCM_56960_A0) 6731 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_11_BCM56960_A0fmt */ 6732 /* format DESCRIPTOR_RX_11fmt */ 6733 /* nFields */ 1, 6734 /* *fields */ soc_DESCRIPTOR_RX_11_BCM53400_A0fmt_fields, 6735 /* bits */ 32, 6736 /* flags */ 0, 6737 }, 6738 #endif /* chips */ 6739 6740 #if defined(BCM_56965_A0) 6741 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_11_BCM56965_A0fmt */ 6742 /* format DESCRIPTOR_RX_11fmt */ 6743 /* nFields */ 1, 6744 /* *fields */ soc_DESCRIPTOR_RX_11_BCM53400_A0fmt_fields, 6745 /* bits */ 32, 6746 /* flags */ 0, 6747 }, 6748 #endif /* chips */ 6749 6750 #if defined(BCM_56970_A0) 6751 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_11_BCM56970_A0fmt */ 6752 /* format DESCRIPTOR_RX_11fmt */ 6753 /* nFields */ 1, 6754 /* *fields */ soc_DESCRIPTOR_RX_11_BCM53400_A0fmt_fields, 6755 /* bits */ 32, 6756 /* flags */ 0, 6757 }, 6758 #endif /* chips */ 6759 6760 #if defined(BCM_53400_A0) 6761 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_12_BCM53400_A0fmt */ 6762 /* format DESCRIPTOR_RX_12fmt */ 6763 /* nFields */ 1, 6764 /* *fields */ soc_DESCRIPTOR_RX_12_BCM53400_A0fmt_fields, 6765 /* bits */ 32, 6766 /* flags */ 0, 6767 }, 6768 #endif /* chips */ 6769 6770 #if defined(BCM_53540_A0) 6771 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_12_BCM53540_A0fmt */ 6772 /* format DESCRIPTOR_RX_12fmt */ 6773 /* nFields */ 1, 6774 /* *fields */ soc_DESCRIPTOR_RX_12_BCM53400_A0fmt_fields, 6775 /* bits */ 32, 6776 /* flags */ 0, 6777 }, 6778 #endif /* chips */ 6779 6780 #if defined(BCM_53570_A0) 6781 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_12_BCM53570_A0fmt */ 6782 /* format DESCRIPTOR_RX_12fmt */ 6783 /* nFields */ 1, 6784 /* *fields */ soc_DESCRIPTOR_RX_12_BCM53400_A0fmt_fields, 6785 /* bits */ 32, 6786 /* flags */ 0, 6787 }, 6788 #endif /* chips */ 6789 6790 #if defined(BCM_53570_B0) 6791 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_12_BCM53570_B0fmt */ 6792 /* format DESCRIPTOR_RX_12fmt */ 6793 /* nFields */ 1, 6794 /* *fields */ soc_DESCRIPTOR_RX_12_BCM53400_A0fmt_fields, 6795 /* bits */ 32, 6796 /* flags */ 0, 6797 }, 6798 #endif /* chips */ 6799 6800 #if defined(BCM_56150_A0) 6801 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_12_BCM56150_A0fmt */ 6802 /* format DESCRIPTOR_RX_12fmt */ 6803 /* nFields */ 1, 6804 /* *fields */ soc_DESCRIPTOR_RX_12_BCM56640_A0fmt_fields, 6805 /* bits */ 32, 6806 /* flags */ 0, 6807 }, 6808 #endif /* chips */ 6809 6810 #if defined(BCM_56160_A0) 6811 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_12_BCM56160_A0fmt */ 6812 /* format DESCRIPTOR_RX_12fmt */ 6813 /* nFields */ 1, 6814 /* *fields */ soc_DESCRIPTOR_RX_12_BCM53400_A0fmt_fields, 6815 /* bits */ 32, 6816 /* flags */ 0, 6817 }, 6818 #endif /* chips */ 6819 6820 #if defined(BCM_56260_A0) 6821 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_12_BCM56260_A0fmt */ 6822 /* format DESCRIPTOR_RX_12fmt */ 6823 /* nFields */ 1, 6824 /* *fields */ soc_DESCRIPTOR_RX_12_BCM53400_A0fmt_fields, 6825 /* bits */ 32, 6826 /* flags */ 0, 6827 }, 6828 #endif /* chips */ 6829 6830 #if defined(BCM_56260_B0) 6831 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_12_BCM56260_B0fmt */ 6832 /* format DESCRIPTOR_RX_12fmt */ 6833 /* nFields */ 1, 6834 /* *fields */ soc_DESCRIPTOR_RX_12_BCM53400_A0fmt_fields, 6835 /* bits */ 32, 6836 /* flags */ 0, 6837 }, 6838 #endif /* chips */ 6839 6840 #if defined(BCM_56270_A0) 6841 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_12_BCM56270_A0fmt */ 6842 /* format DESCRIPTOR_RX_12fmt */ 6843 /* nFields */ 1, 6844 /* *fields */ soc_DESCRIPTOR_RX_12_BCM53400_A0fmt_fields, 6845 /* bits */ 32, 6846 /* flags */ 0, 6847 }, 6848 #endif /* chips */ 6849 6850 #if defined(BCM_56340_A0) 6851 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_12_BCM56340_A0fmt */ 6852 /* format DESCRIPTOR_RX_12fmt */ 6853 /* nFields */ 1, 6854 /* *fields */ soc_DESCRIPTOR_RX_12_BCM56640_A0fmt_fields, 6855 /* bits */ 32, 6856 /* flags */ 0, 6857 }, 6858 #endif /* chips */ 6859 6860 #if defined(BCM_56450_A0) 6861 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_12_BCM56450_A0fmt */ 6862 /* format DESCRIPTOR_RX_12fmt */ 6863 /* nFields */ 1, 6864 /* *fields */ soc_DESCRIPTOR_RX_12_BCM56640_A0fmt_fields, 6865 /* bits */ 32, 6866 /* flags */ 0, 6867 }, 6868 #endif /* chips */ 6869 6870 #if defined(BCM_56450_B0) 6871 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_12_BCM56450_B0fmt */ 6872 /* format DESCRIPTOR_RX_12fmt */ 6873 /* nFields */ 1, 6874 /* *fields */ soc_DESCRIPTOR_RX_12_BCM56640_A0fmt_fields, 6875 /* bits */ 32, 6876 /* flags */ 0, 6877 }, 6878 #endif /* chips */ 6879 6880 #if defined(BCM_56450_B1) 6881 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_12_BCM56450_B1fmt */ 6882 /* format DESCRIPTOR_RX_12fmt */ 6883 /* nFields */ 1, 6884 /* *fields */ soc_DESCRIPTOR_RX_12_BCM56640_A0fmt_fields, 6885 /* bits */ 32, 6886 /* flags */ 0, 6887 }, 6888 #endif /* chips */ 6889 6890 #if defined(BCM_56560_A0) 6891 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_12_BCM56560_A0fmt */ 6892 /* format DESCRIPTOR_RX_12fmt */ 6893 /* nFields */ 1, 6894 /* *fields */ soc_DESCRIPTOR_RX_12_BCM53400_A0fmt_fields, 6895 /* bits */ 32, 6896 /* flags */ 0, 6897 }, 6898 #endif /* chips */ 6899 6900 #if defined(BCM_56560_B0) 6901 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_12_BCM56560_B0fmt */ 6902 /* format DESCRIPTOR_RX_12fmt */ 6903 /* nFields */ 1, 6904 /* *fields */ soc_DESCRIPTOR_RX_12_BCM53400_A0fmt_fields, 6905 /* bits */ 32, 6906 /* flags */ 0, 6907 }, 6908 #endif /* chips */ 6909 6910 #if defined(BCM_56640_A0) 6911 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_12_BCM56640_A0fmt */ 6912 /* format DESCRIPTOR_RX_12fmt */ 6913 /* nFields */ 1, 6914 /* *fields */ soc_DESCRIPTOR_RX_12_BCM56640_A0fmt_fields, 6915 /* bits */ 32, 6916 /* flags */ 0, 6917 }, 6918 #endif /* chips */ 6919 6920 #if defined(BCM_56670_A0) 6921 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_12_BCM56670_A0fmt */ 6922 /* format DESCRIPTOR_RX_12fmt */ 6923 /* nFields */ 1, 6924 /* *fields */ soc_DESCRIPTOR_RX_12_BCM53400_A0fmt_fields, 6925 /* bits */ 32, 6926 /* flags */ 0, 6927 }, 6928 #endif /* chips */ 6929 6930 #if defined(BCM_56670_B0) 6931 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_12_BCM56670_B0fmt */ 6932 /* format DESCRIPTOR_RX_12fmt */ 6933 /* nFields */ 1, 6934 /* *fields */ soc_DESCRIPTOR_RX_12_BCM53400_A0fmt_fields, 6935 /* bits */ 32, 6936 /* flags */ 0, 6937 }, 6938 #endif /* chips */ 6939 6940 #if defined(BCM_56850_A0) 6941 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_12_BCM56850_A0fmt */ 6942 /* format DESCRIPTOR_RX_12fmt */ 6943 /* nFields */ 1, 6944 /* *fields */ soc_DESCRIPTOR_RX_12_BCM56640_A0fmt_fields, 6945 /* bits */ 32, 6946 /* flags */ 0, 6947 }, 6948 #endif /* chips */ 6949 6950 #if defined(BCM_56860_A0) 6951 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_12_BCM56860_A0fmt */ 6952 /* format DESCRIPTOR_RX_12fmt */ 6953 /* nFields */ 1, 6954 /* *fields */ soc_DESCRIPTOR_RX_12_BCM56640_A0fmt_fields, 6955 /* bits */ 32, 6956 /* flags */ 0, 6957 }, 6958 #endif /* chips */ 6959 6960 #if defined(BCM_56960_A0) 6961 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_12_BCM56960_A0fmt */ 6962 /* format DESCRIPTOR_RX_12fmt */ 6963 /* nFields */ 1, 6964 /* *fields */ soc_DESCRIPTOR_RX_12_BCM53400_A0fmt_fields, 6965 /* bits */ 32, 6966 /* flags */ 0, 6967 }, 6968 #endif /* chips */ 6969 6970 #if defined(BCM_56965_A0) 6971 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_12_BCM56965_A0fmt */ 6972 /* format DESCRIPTOR_RX_12fmt */ 6973 /* nFields */ 1, 6974 /* *fields */ soc_DESCRIPTOR_RX_12_BCM53400_A0fmt_fields, 6975 /* bits */ 32, 6976 /* flags */ 0, 6977 }, 6978 #endif /* chips */ 6979 6980 #if defined(BCM_56970_A0) 6981 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_12_BCM56970_A0fmt */ 6982 /* format DESCRIPTOR_RX_12fmt */ 6983 /* nFields */ 1, 6984 /* *fields */ soc_DESCRIPTOR_RX_12_BCM53400_A0fmt_fields, 6985 /* bits */ 32, 6986 /* flags */ 0, 6987 }, 6988 #endif /* chips */ 6989 6990 #if defined(BCM_53400_A0) 6991 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_13_BCM53400_A0fmt */ 6992 /* format DESCRIPTOR_RX_13fmt */ 6993 /* nFields */ 1, 6994 /* *fields */ soc_DESCRIPTOR_RX_13_BCM53400_A0fmt_fields, 6995 /* bits */ 32, 6996 /* flags */ 0, 6997 }, 6998 #endif /* chips */ 6999 7000 #if defined(BCM_53540_A0) 7001 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_13_BCM53540_A0fmt */ 7002 /* format DESCRIPTOR_RX_13fmt */ 7003 /* nFields */ 1, 7004 /* *fields */ soc_DESCRIPTOR_RX_13_BCM53400_A0fmt_fields, 7005 /* bits */ 32, 7006 /* flags */ 0, 7007 }, 7008 #endif /* chips */ 7009 7010 #if defined(BCM_53570_A0) 7011 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_13_BCM53570_A0fmt */ 7012 /* format DESCRIPTOR_RX_13fmt */ 7013 /* nFields */ 1, 7014 /* *fields */ soc_DESCRIPTOR_RX_13_BCM53400_A0fmt_fields, 7015 /* bits */ 32, 7016 /* flags */ 0, 7017 }, 7018 #endif /* chips */ 7019 7020 #if defined(BCM_53570_B0) 7021 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_13_BCM53570_B0fmt */ 7022 /* format DESCRIPTOR_RX_13fmt */ 7023 /* nFields */ 1, 7024 /* *fields */ soc_DESCRIPTOR_RX_13_BCM53400_A0fmt_fields, 7025 /* bits */ 32, 7026 /* flags */ 0, 7027 }, 7028 #endif /* chips */ 7029 7030 #if defined(BCM_56150_A0) 7031 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_13_BCM56150_A0fmt */ 7032 /* format DESCRIPTOR_RX_13fmt */ 7033 /* nFields */ 1, 7034 /* *fields */ soc_DESCRIPTOR_RX_13_BCM56640_A0fmt_fields, 7035 /* bits */ 32, 7036 /* flags */ 0, 7037 }, 7038 #endif /* chips */ 7039 7040 #if defined(BCM_56160_A0) 7041 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_13_BCM56160_A0fmt */ 7042 /* format DESCRIPTOR_RX_13fmt */ 7043 /* nFields */ 1, 7044 /* *fields */ soc_DESCRIPTOR_RX_13_BCM53400_A0fmt_fields, 7045 /* bits */ 32, 7046 /* flags */ 0, 7047 }, 7048 #endif /* chips */ 7049 7050 #if defined(BCM_56260_A0) 7051 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_13_BCM56260_A0fmt */ 7052 /* format DESCRIPTOR_RX_13fmt */ 7053 /* nFields */ 1, 7054 /* *fields */ soc_DESCRIPTOR_RX_13_BCM53400_A0fmt_fields, 7055 /* bits */ 32, 7056 /* flags */ 0, 7057 }, 7058 #endif /* chips */ 7059 7060 #if defined(BCM_56260_B0) 7061 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_13_BCM56260_B0fmt */ 7062 /* format DESCRIPTOR_RX_13fmt */ 7063 /* nFields */ 1, 7064 /* *fields */ soc_DESCRIPTOR_RX_13_BCM53400_A0fmt_fields, 7065 /* bits */ 32, 7066 /* flags */ 0, 7067 }, 7068 #endif /* chips */ 7069 7070 #if defined(BCM_56270_A0) 7071 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_13_BCM56270_A0fmt */ 7072 /* format DESCRIPTOR_RX_13fmt */ 7073 /* nFields */ 1, 7074 /* *fields */ soc_DESCRIPTOR_RX_13_BCM53400_A0fmt_fields, 7075 /* bits */ 32, 7076 /* flags */ 0, 7077 }, 7078 #endif /* chips */ 7079 7080 #if defined(BCM_56340_A0) 7081 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_13_BCM56340_A0fmt */ 7082 /* format DESCRIPTOR_RX_13fmt */ 7083 /* nFields */ 1, 7084 /* *fields */ soc_DESCRIPTOR_RX_13_BCM56640_A0fmt_fields, 7085 /* bits */ 32, 7086 /* flags */ 0, 7087 }, 7088 #endif /* chips */ 7089 7090 #if defined(BCM_56450_A0) 7091 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_13_BCM56450_A0fmt */ 7092 /* format DESCRIPTOR_RX_13fmt */ 7093 /* nFields */ 1, 7094 /* *fields */ soc_DESCRIPTOR_RX_13_BCM56640_A0fmt_fields, 7095 /* bits */ 32, 7096 /* flags */ 0, 7097 }, 7098 #endif /* chips */ 7099 7100 #if defined(BCM_56450_B0) 7101 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_13_BCM56450_B0fmt */ 7102 /* format DESCRIPTOR_RX_13fmt */ 7103 /* nFields */ 1, 7104 /* *fields */ soc_DESCRIPTOR_RX_13_BCM56640_A0fmt_fields, 7105 /* bits */ 32, 7106 /* flags */ 0, 7107 }, 7108 #endif /* chips */ 7109 7110 #if defined(BCM_56450_B1) 7111 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_13_BCM56450_B1fmt */ 7112 /* format DESCRIPTOR_RX_13fmt */ 7113 /* nFields */ 1, 7114 /* *fields */ soc_DESCRIPTOR_RX_13_BCM56640_A0fmt_fields, 7115 /* bits */ 32, 7116 /* flags */ 0, 7117 }, 7118 #endif /* chips */ 7119 7120 #if defined(BCM_56560_A0) 7121 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_13_BCM56560_A0fmt */ 7122 /* format DESCRIPTOR_RX_13fmt */ 7123 /* nFields */ 1, 7124 /* *fields */ soc_DESCRIPTOR_RX_13_BCM53400_A0fmt_fields, 7125 /* bits */ 32, 7126 /* flags */ 0, 7127 }, 7128 #endif /* chips */ 7129 7130 #if defined(BCM_56560_B0) 7131 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_13_BCM56560_B0fmt */ 7132 /* format DESCRIPTOR_RX_13fmt */ 7133 /* nFields */ 1, 7134 /* *fields */ soc_DESCRIPTOR_RX_13_BCM53400_A0fmt_fields, 7135 /* bits */ 32, 7136 /* flags */ 0, 7137 }, 7138 #endif /* chips */ 7139 7140 #if defined(BCM_56640_A0) 7141 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_13_BCM56640_A0fmt */ 7142 /* format DESCRIPTOR_RX_13fmt */ 7143 /* nFields */ 1, 7144 /* *fields */ soc_DESCRIPTOR_RX_13_BCM56640_A0fmt_fields, 7145 /* bits */ 32, 7146 /* flags */ 0, 7147 }, 7148 #endif /* chips */ 7149 7150 #if defined(BCM_56670_A0) 7151 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_13_BCM56670_A0fmt */ 7152 /* format DESCRIPTOR_RX_13fmt */ 7153 /* nFields */ 1, 7154 /* *fields */ soc_DESCRIPTOR_RX_13_BCM53400_A0fmt_fields, 7155 /* bits */ 32, 7156 /* flags */ 0, 7157 }, 7158 #endif /* chips */ 7159 7160 #if defined(BCM_56670_B0) 7161 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_13_BCM56670_B0fmt */ 7162 /* format DESCRIPTOR_RX_13fmt */ 7163 /* nFields */ 1, 7164 /* *fields */ soc_DESCRIPTOR_RX_13_BCM53400_A0fmt_fields, 7165 /* bits */ 32, 7166 /* flags */ 0, 7167 }, 7168 #endif /* chips */ 7169 7170 #if defined(BCM_56850_A0) 7171 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_13_BCM56850_A0fmt */ 7172 /* format DESCRIPTOR_RX_13fmt */ 7173 /* nFields */ 1, 7174 /* *fields */ soc_DESCRIPTOR_RX_13_BCM56640_A0fmt_fields, 7175 /* bits */ 32, 7176 /* flags */ 0, 7177 }, 7178 #endif /* chips */ 7179 7180 #if defined(BCM_56860_A0) 7181 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_13_BCM56860_A0fmt */ 7182 /* format DESCRIPTOR_RX_13fmt */ 7183 /* nFields */ 1, 7184 /* *fields */ soc_DESCRIPTOR_RX_13_BCM56640_A0fmt_fields, 7185 /* bits */ 32, 7186 /* flags */ 0, 7187 }, 7188 #endif /* chips */ 7189 7190 #if defined(BCM_56960_A0) 7191 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_13_BCM56960_A0fmt */ 7192 /* format DESCRIPTOR_RX_13fmt */ 7193 /* nFields */ 1, 7194 /* *fields */ soc_DESCRIPTOR_RX_13_BCM53400_A0fmt_fields, 7195 /* bits */ 32, 7196 /* flags */ 0, 7197 }, 7198 #endif /* chips */ 7199 7200 #if defined(BCM_56965_A0) 7201 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_13_BCM56965_A0fmt */ 7202 /* format DESCRIPTOR_RX_13fmt */ 7203 /* nFields */ 1, 7204 /* *fields */ soc_DESCRIPTOR_RX_13_BCM53400_A0fmt_fields, 7205 /* bits */ 32, 7206 /* flags */ 0, 7207 }, 7208 #endif /* chips */ 7209 7210 #if defined(BCM_56970_A0) 7211 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_13_BCM56970_A0fmt */ 7212 /* format DESCRIPTOR_RX_13fmt */ 7213 /* nFields */ 1, 7214 /* *fields */ soc_DESCRIPTOR_RX_13_BCM53400_A0fmt_fields, 7215 /* bits */ 32, 7216 /* flags */ 0, 7217 }, 7218 #endif /* chips */ 7219 7220 #if defined(BCM_53400_A0) 7221 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_14_BCM53400_A0fmt */ 7222 /* format DESCRIPTOR_RX_14fmt */ 7223 /* nFields */ 1, 7224 /* *fields */ soc_DESCRIPTOR_RX_14_BCM53400_A0fmt_fields, 7225 /* bits */ 32, 7226 /* flags */ 0, 7227 }, 7228 #endif /* chips */ 7229 7230 #if defined(BCM_53540_A0) 7231 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_14_BCM53540_A0fmt */ 7232 /* format DESCRIPTOR_RX_14fmt */ 7233 /* nFields */ 1, 7234 /* *fields */ soc_DESCRIPTOR_RX_14_BCM53400_A0fmt_fields, 7235 /* bits */ 32, 7236 /* flags */ 0, 7237 }, 7238 #endif /* chips */ 7239 7240 #if defined(BCM_53570_A0) 7241 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_14_BCM53570_A0fmt */ 7242 /* format DESCRIPTOR_RX_14fmt */ 7243 /* nFields */ 1, 7244 /* *fields */ soc_DESCRIPTOR_RX_14_BCM53400_A0fmt_fields, 7245 /* bits */ 32, 7246 /* flags */ 0, 7247 }, 7248 #endif /* chips */ 7249 7250 #if defined(BCM_53570_B0) 7251 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_14_BCM53570_B0fmt */ 7252 /* format DESCRIPTOR_RX_14fmt */ 7253 /* nFields */ 1, 7254 /* *fields */ soc_DESCRIPTOR_RX_14_BCM53400_A0fmt_fields, 7255 /* bits */ 32, 7256 /* flags */ 0, 7257 }, 7258 #endif /* chips */ 7259 7260 #if defined(BCM_56150_A0) 7261 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_14_BCM56150_A0fmt */ 7262 /* format DESCRIPTOR_RX_14fmt */ 7263 /* nFields */ 1, 7264 /* *fields */ soc_DESCRIPTOR_RX_14_BCM56640_A0fmt_fields, 7265 /* bits */ 32, 7266 /* flags */ 0, 7267 }, 7268 #endif /* chips */ 7269 7270 #if defined(BCM_56160_A0) 7271 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_14_BCM56160_A0fmt */ 7272 /* format DESCRIPTOR_RX_14fmt */ 7273 /* nFields */ 1, 7274 /* *fields */ soc_DESCRIPTOR_RX_14_BCM53400_A0fmt_fields, 7275 /* bits */ 32, 7276 /* flags */ 0, 7277 }, 7278 #endif /* chips */ 7279 7280 #if defined(BCM_56260_A0) 7281 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_14_BCM56260_A0fmt */ 7282 /* format DESCRIPTOR_RX_14fmt */ 7283 /* nFields */ 1, 7284 /* *fields */ soc_DESCRIPTOR_RX_14_BCM53400_A0fmt_fields, 7285 /* bits */ 32, 7286 /* flags */ 0, 7287 }, 7288 #endif /* chips */ 7289 7290 #if defined(BCM_56260_B0) 7291 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_14_BCM56260_B0fmt */ 7292 /* format DESCRIPTOR_RX_14fmt */ 7293 /* nFields */ 1, 7294 /* *fields */ soc_DESCRIPTOR_RX_14_BCM53400_A0fmt_fields, 7295 /* bits */ 32, 7296 /* flags */ 0, 7297 }, 7298 #endif /* chips */ 7299 7300 #if defined(BCM_56270_A0) 7301 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_14_BCM56270_A0fmt */ 7302 /* format DESCRIPTOR_RX_14fmt */ 7303 /* nFields */ 1, 7304 /* *fields */ soc_DESCRIPTOR_RX_14_BCM53400_A0fmt_fields, 7305 /* bits */ 32, 7306 /* flags */ 0, 7307 }, 7308 #endif /* chips */ 7309 7310 #if defined(BCM_56340_A0) 7311 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_14_BCM56340_A0fmt */ 7312 /* format DESCRIPTOR_RX_14fmt */ 7313 /* nFields */ 1, 7314 /* *fields */ soc_DESCRIPTOR_RX_14_BCM56640_A0fmt_fields, 7315 /* bits */ 32, 7316 /* flags */ 0, 7317 }, 7318 #endif /* chips */ 7319 7320 #if defined(BCM_56450_A0) 7321 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_14_BCM56450_A0fmt */ 7322 /* format DESCRIPTOR_RX_14fmt */ 7323 /* nFields */ 1, 7324 /* *fields */ soc_DESCRIPTOR_RX_14_BCM56640_A0fmt_fields, 7325 /* bits */ 32, 7326 /* flags */ 0, 7327 }, 7328 #endif /* chips */ 7329 7330 #if defined(BCM_56450_B0) 7331 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_14_BCM56450_B0fmt */ 7332 /* format DESCRIPTOR_RX_14fmt */ 7333 /* nFields */ 1, 7334 /* *fields */ soc_DESCRIPTOR_RX_14_BCM56640_A0fmt_fields, 7335 /* bits */ 32, 7336 /* flags */ 0, 7337 }, 7338 #endif /* chips */ 7339 7340 #if defined(BCM_56450_B1) 7341 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_14_BCM56450_B1fmt */ 7342 /* format DESCRIPTOR_RX_14fmt */ 7343 /* nFields */ 1, 7344 /* *fields */ soc_DESCRIPTOR_RX_14_BCM56640_A0fmt_fields, 7345 /* bits */ 32, 7346 /* flags */ 0, 7347 }, 7348 #endif /* chips */ 7349 7350 #if defined(BCM_56560_A0) 7351 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_14_BCM56560_A0fmt */ 7352 /* format DESCRIPTOR_RX_14fmt */ 7353 /* nFields */ 1, 7354 /* *fields */ soc_DESCRIPTOR_RX_14_BCM53400_A0fmt_fields, 7355 /* bits */ 32, 7356 /* flags */ 0, 7357 }, 7358 #endif /* chips */ 7359 7360 #if defined(BCM_56560_B0) 7361 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_14_BCM56560_B0fmt */ 7362 /* format DESCRIPTOR_RX_14fmt */ 7363 /* nFields */ 1, 7364 /* *fields */ soc_DESCRIPTOR_RX_14_BCM53400_A0fmt_fields, 7365 /* bits */ 32, 7366 /* flags */ 0, 7367 }, 7368 #endif /* chips */ 7369 7370 #if defined(BCM_56640_A0) 7371 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_14_BCM56640_A0fmt */ 7372 /* format DESCRIPTOR_RX_14fmt */ 7373 /* nFields */ 1, 7374 /* *fields */ soc_DESCRIPTOR_RX_14_BCM56640_A0fmt_fields, 7375 /* bits */ 32, 7376 /* flags */ 0, 7377 }, 7378 #endif /* chips */ 7379 7380 #if defined(BCM_56670_A0) 7381 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_14_BCM56670_A0fmt */ 7382 /* format DESCRIPTOR_RX_14fmt */ 7383 /* nFields */ 1, 7384 /* *fields */ soc_DESCRIPTOR_RX_14_BCM53400_A0fmt_fields, 7385 /* bits */ 32, 7386 /* flags */ 0, 7387 }, 7388 #endif /* chips */ 7389 7390 #if defined(BCM_56670_B0) 7391 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_14_BCM56670_B0fmt */ 7392 /* format DESCRIPTOR_RX_14fmt */ 7393 /* nFields */ 1, 7394 /* *fields */ soc_DESCRIPTOR_RX_14_BCM53400_A0fmt_fields, 7395 /* bits */ 32, 7396 /* flags */ 0, 7397 }, 7398 #endif /* chips */ 7399 7400 #if defined(BCM_56850_A0) 7401 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_14_BCM56850_A0fmt */ 7402 /* format DESCRIPTOR_RX_14fmt */ 7403 /* nFields */ 1, 7404 /* *fields */ soc_DESCRIPTOR_RX_14_BCM56640_A0fmt_fields, 7405 /* bits */ 32, 7406 /* flags */ 0, 7407 }, 7408 #endif /* chips */ 7409 7410 #if defined(BCM_56860_A0) 7411 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_14_BCM56860_A0fmt */ 7412 /* format DESCRIPTOR_RX_14fmt */ 7413 /* nFields */ 1, 7414 /* *fields */ soc_DESCRIPTOR_RX_14_BCM56640_A0fmt_fields, 7415 /* bits */ 32, 7416 /* flags */ 0, 7417 }, 7418 #endif /* chips */ 7419 7420 #if defined(BCM_56960_A0) 7421 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_14_BCM56960_A0fmt */ 7422 /* format DESCRIPTOR_RX_14fmt */ 7423 /* nFields */ 1, 7424 /* *fields */ soc_DESCRIPTOR_RX_14_BCM53400_A0fmt_fields, 7425 /* bits */ 32, 7426 /* flags */ 0, 7427 }, 7428 #endif /* chips */ 7429 7430 #if defined(BCM_56965_A0) 7431 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_14_BCM56965_A0fmt */ 7432 /* format DESCRIPTOR_RX_14fmt */ 7433 /* nFields */ 1, 7434 /* *fields */ soc_DESCRIPTOR_RX_14_BCM53400_A0fmt_fields, 7435 /* bits */ 32, 7436 /* flags */ 0, 7437 }, 7438 #endif /* chips */ 7439 7440 #if defined(BCM_56970_A0) 7441 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_14_BCM56970_A0fmt */ 7442 /* format DESCRIPTOR_RX_14fmt */ 7443 /* nFields */ 1, 7444 /* *fields */ soc_DESCRIPTOR_RX_14_BCM53400_A0fmt_fields, 7445 /* bits */ 32, 7446 /* flags */ 0, 7447 }, 7448 #endif /* chips */ 7449 7450 #if defined(BCM_53400_A0) 7451 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_15_BCM53400_A0fmt */ 7452 /* format DESCRIPTOR_RX_15fmt */ 7453 /* nFields */ 7, 7454 /* *fields */ soc_DESCRIPTOR_RX_15_BCM53400_A0fmt_fields, 7455 /* bits */ 32, 7456 /* flags */ 0, 7457 }, 7458 #endif /* chips */ 7459 7460 #if defined(BCM_53540_A0) 7461 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_15_BCM53540_A0fmt */ 7462 /* format DESCRIPTOR_RX_15fmt */ 7463 /* nFields */ 7, 7464 /* *fields */ soc_DESCRIPTOR_RX_15_BCM53400_A0fmt_fields, 7465 /* bits */ 32, 7466 /* flags */ 0, 7467 }, 7468 #endif /* chips */ 7469 7470 #if defined(BCM_53570_A0) 7471 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_15_BCM53570_A0fmt */ 7472 /* format DESCRIPTOR_RX_15fmt */ 7473 /* nFields */ 7, 7474 /* *fields */ soc_DESCRIPTOR_RX_15_BCM53400_A0fmt_fields, 7475 /* bits */ 32, 7476 /* flags */ 0, 7477 }, 7478 #endif /* chips */ 7479 7480 #if defined(BCM_53570_B0) 7481 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_15_BCM53570_B0fmt */ 7482 /* format DESCRIPTOR_RX_15fmt */ 7483 /* nFields */ 7, 7484 /* *fields */ soc_DESCRIPTOR_RX_15_BCM53400_A0fmt_fields, 7485 /* bits */ 32, 7486 /* flags */ 0, 7487 }, 7488 #endif /* chips */ 7489 7490 #if defined(BCM_56150_A0) 7491 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_15_BCM56150_A0fmt */ 7492 /* format DESCRIPTOR_RX_15fmt */ 7493 /* nFields */ 7, 7494 /* *fields */ soc_DESCRIPTOR_RX_15_BCM56640_A0fmt_fields, 7495 /* bits */ 32, 7496 /* flags */ 0, 7497 }, 7498 #endif /* chips */ 7499 7500 #if defined(BCM_56160_A0) 7501 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_15_BCM56160_A0fmt */ 7502 /* format DESCRIPTOR_RX_15fmt */ 7503 /* nFields */ 7, 7504 /* *fields */ soc_DESCRIPTOR_RX_15_BCM53400_A0fmt_fields, 7505 /* bits */ 32, 7506 /* flags */ 0, 7507 }, 7508 #endif /* chips */ 7509 7510 #if defined(BCM_56260_A0) 7511 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_15_BCM56260_A0fmt */ 7512 /* format DESCRIPTOR_RX_15fmt */ 7513 /* nFields */ 7, 7514 /* *fields */ soc_DESCRIPTOR_RX_15_BCM53400_A0fmt_fields, 7515 /* bits */ 32, 7516 /* flags */ 0, 7517 }, 7518 #endif /* chips */ 7519 7520 #if defined(BCM_56260_B0) 7521 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_15_BCM56260_B0fmt */ 7522 /* format DESCRIPTOR_RX_15fmt */ 7523 /* nFields */ 7, 7524 /* *fields */ soc_DESCRIPTOR_RX_15_BCM53400_A0fmt_fields, 7525 /* bits */ 32, 7526 /* flags */ 0, 7527 }, 7528 #endif /* chips */ 7529 7530 #if defined(BCM_56270_A0) 7531 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_15_BCM56270_A0fmt */ 7532 /* format DESCRIPTOR_RX_15fmt */ 7533 /* nFields */ 7, 7534 /* *fields */ soc_DESCRIPTOR_RX_15_BCM53400_A0fmt_fields, 7535 /* bits */ 32, 7536 /* flags */ 0, 7537 }, 7538 #endif /* chips */ 7539 7540 #if defined(BCM_56340_A0) 7541 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_15_BCM56340_A0fmt */ 7542 /* format DESCRIPTOR_RX_15fmt */ 7543 /* nFields */ 7, 7544 /* *fields */ soc_DESCRIPTOR_RX_15_BCM56640_A0fmt_fields, 7545 /* bits */ 32, 7546 /* flags */ 0, 7547 }, 7548 #endif /* chips */ 7549 7550 #if defined(BCM_56440_A0) 7551 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_15_BCM56440_A0fmt */ 7552 /* format DESCRIPTOR_RX_15fmt */ 7553 /* nFields */ 7, 7554 /* *fields */ soc_DESCRIPTOR_RX_15_BCM56440_A0fmt_fields, 7555 /* bits */ 32, 7556 /* flags */ 0, 7557 }, 7558 #endif /* chips */ 7559 7560 #if defined(BCM_56440_B0) 7561 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_15_BCM56440_B0fmt */ 7562 /* format DESCRIPTOR_RX_15fmt */ 7563 /* nFields */ 7, 7564 /* *fields */ soc_DESCRIPTOR_RX_15_BCM56440_A0fmt_fields, 7565 /* bits */ 32, 7566 /* flags */ 0, 7567 }, 7568 #endif /* chips */ 7569 7570 #if defined(BCM_56450_A0) 7571 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_15_BCM56450_A0fmt */ 7572 /* format DESCRIPTOR_RX_15fmt */ 7573 /* nFields */ 7, 7574 /* *fields */ soc_DESCRIPTOR_RX_15_BCM56640_A0fmt_fields, 7575 /* bits */ 32, 7576 /* flags */ 0, 7577 }, 7578 #endif /* chips */ 7579 7580 #if defined(BCM_56450_B0) 7581 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_15_BCM56450_B0fmt */ 7582 /* format DESCRIPTOR_RX_15fmt */ 7583 /* nFields */ 7, 7584 /* *fields */ soc_DESCRIPTOR_RX_15_BCM56640_A0fmt_fields, 7585 /* bits */ 32, 7586 /* flags */ 0, 7587 }, 7588 #endif /* chips */ 7589 7590 #if defined(BCM_56450_B1) 7591 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_15_BCM56450_B1fmt */ 7592 /* format DESCRIPTOR_RX_15fmt */ 7593 /* nFields */ 7, 7594 /* *fields */ soc_DESCRIPTOR_RX_15_BCM56640_A0fmt_fields, 7595 /* bits */ 32, 7596 /* flags */ 0, 7597 }, 7598 #endif /* chips */ 7599 7600 #if defined(BCM_56560_A0) 7601 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_15_BCM56560_A0fmt */ 7602 /* format DESCRIPTOR_RX_15fmt */ 7603 /* nFields */ 7, 7604 /* *fields */ soc_DESCRIPTOR_RX_15_BCM53400_A0fmt_fields, 7605 /* bits */ 32, 7606 /* flags */ 0, 7607 }, 7608 #endif /* chips */ 7609 7610 #if defined(BCM_56560_B0) 7611 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_15_BCM56560_B0fmt */ 7612 /* format DESCRIPTOR_RX_15fmt */ 7613 /* nFields */ 7, 7614 /* *fields */ soc_DESCRIPTOR_RX_15_BCM53400_A0fmt_fields, 7615 /* bits */ 32, 7616 /* flags */ 0, 7617 }, 7618 #endif /* chips */ 7619 7620 #if defined(BCM_56640_A0) 7621 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_15_BCM56640_A0fmt */ 7622 /* format DESCRIPTOR_RX_15fmt */ 7623 /* nFields */ 7, 7624 /* *fields */ soc_DESCRIPTOR_RX_15_BCM56640_A0fmt_fields, 7625 /* bits */ 32, 7626 /* flags */ 0, 7627 }, 7628 #endif /* chips */ 7629 7630 #if defined(BCM_56670_A0) 7631 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_15_BCM56670_A0fmt */ 7632 /* format DESCRIPTOR_RX_15fmt */ 7633 /* nFields */ 7, 7634 /* *fields */ soc_DESCRIPTOR_RX_15_BCM53400_A0fmt_fields, 7635 /* bits */ 32, 7636 /* flags */ 0, 7637 }, 7638 #endif /* chips */ 7639 7640 #if defined(BCM_56670_B0) 7641 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_15_BCM56670_B0fmt */ 7642 /* format DESCRIPTOR_RX_15fmt */ 7643 /* nFields */ 7, 7644 /* *fields */ soc_DESCRIPTOR_RX_15_BCM53400_A0fmt_fields, 7645 /* bits */ 32, 7646 /* flags */ 0, 7647 }, 7648 #endif /* chips */ 7649 7650 #if defined(BCM_56850_A0) 7651 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_15_BCM56850_A0fmt */ 7652 /* format DESCRIPTOR_RX_15fmt */ 7653 /* nFields */ 7, 7654 /* *fields */ soc_DESCRIPTOR_RX_15_BCM56640_A0fmt_fields, 7655 /* bits */ 32, 7656 /* flags */ 0, 7657 }, 7658 #endif /* chips */ 7659 7660 #if defined(BCM_56860_A0) 7661 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_15_BCM56860_A0fmt */ 7662 /* format DESCRIPTOR_RX_15fmt */ 7663 /* nFields */ 7, 7664 /* *fields */ soc_DESCRIPTOR_RX_15_BCM56640_A0fmt_fields, 7665 /* bits */ 32, 7666 /* flags */ 0, 7667 }, 7668 #endif /* chips */ 7669 7670 #if defined(BCM_56960_A0) 7671 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_15_BCM56960_A0fmt */ 7672 /* format DESCRIPTOR_RX_15fmt */ 7673 /* nFields */ 7, 7674 /* *fields */ soc_DESCRIPTOR_RX_15_BCM53400_A0fmt_fields, 7675 /* bits */ 32, 7676 /* flags */ 0, 7677 }, 7678 #endif /* chips */ 7679 7680 #if defined(BCM_56965_A0) 7681 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_15_BCM56965_A0fmt */ 7682 /* format DESCRIPTOR_RX_15fmt */ 7683 /* nFields */ 7, 7684 /* *fields */ soc_DESCRIPTOR_RX_15_BCM53400_A0fmt_fields, 7685 /* bits */ 32, 7686 /* flags */ 0, 7687 }, 7688 #endif /* chips */ 7689 7690 #if defined(BCM_56970_A0) 7691 { /* SOC_FORMAT_INT_DESCRIPTOR_RX_15_BCM56970_A0fmt */ 7692 /* format DESCRIPTOR_RX_15fmt */ 7693 /* nFields */ 7, 7694 /* *fields */ soc_DESCRIPTOR_RX_15_BCM53400_A0fmt_fields, 7695 /* bits */ 32, 7696 /* flags */ 0, 7697 }, 7698 #endif /* chips */ 7699 7700 #if defined(BCM_56504_A0) 7701 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_00fmt */ 7702 /* format DESCRIPTOR_TX_00fmt */ 7703 /* nFields */ 1, 7704 /* *fields */ soc_DESCRIPTOR_RX_00fmt_fields, 7705 /* bits */ 32, 7706 /* flags */ 0, 7707 }, 7708 #endif /* chips */ 7709 7710 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \ 7711 defined(BCM_56142_A0) || defined(BCM_56224_A0) || \ 7712 defined(BCM_56224_B0) || defined(BCM_56314_A0) || \ 7713 defined(BCM_56334_A0) || defined(BCM_56334_B0) || \ 7714 defined(BCM_56440_A0) || defined(BCM_56440_B0) || \ 7715 defined(BCM_56504_A0) || defined(BCM_56504_B0) || \ 7716 defined(BCM_56514_A0) || defined(BCM_56524_A0) || \ 7717 defined(BCM_56524_B0) || defined(BCM_56624_A0) || \ 7718 defined(BCM_56624_B0) || defined(BCM_56634_A0) || \ 7719 defined(BCM_56634_B0) || defined(BCM_56680_A0) || \ 7720 defined(BCM_56680_B0) || defined(BCM_56685_A0) || \ 7721 defined(BCM_56685_B0) || defined(BCM_56725_A0) || \ 7722 defined(BCM_56820_A0) || defined(BCM_56840_A0) || \ 7723 defined(BCM_56840_B0) || defined(BCM_88732_A0) 7724 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_01fmt */ 7725 /* format DESCRIPTOR_TX_01fmt */ 7726 /* nFields */ 8, 7727 /* *fields */ soc_DESCRIPTOR_TX_01fmt_fields, 7728 /* bits */ 23, 7729 /* flags */ 0, 7730 }, 7731 #endif /* chips */ 7732 7733 #if defined(BCM_56504_A0) 7734 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_02fmt */ 7735 /* format DESCRIPTOR_TX_02fmt */ 7736 /* nFields */ 1, 7737 /* *fields */ soc_DESCRIPTOR_RX_02fmt_fields, 7738 /* bits */ 32, 7739 /* flags */ 0, 7740 }, 7741 #endif /* chips */ 7742 7743 #if defined(BCM_56504_A0) 7744 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_03fmt */ 7745 /* format DESCRIPTOR_TX_03fmt */ 7746 /* nFields */ 1, 7747 /* *fields */ soc_DESCRIPTOR_RX_03fmt_fields, 7748 /* bits */ 32, 7749 /* flags */ 0, 7750 }, 7751 #endif /* chips */ 7752 7753 #if defined(BCM_56504_A0) 7754 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_04fmt */ 7755 /* format DESCRIPTOR_TX_04fmt */ 7756 /* nFields */ 1, 7757 /* *fields */ soc_DESCRIPTOR_RX_04fmt_fields, 7758 /* bits */ 32, 7759 /* flags */ 0, 7760 }, 7761 #endif /* chips */ 7762 7763 #if defined(BCM_56314_A0) || defined(BCM_56504_A0) || \ 7764 defined(BCM_56504_B0) || defined(BCM_56514_A0) 7765 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_05fmt */ 7766 /* format DESCRIPTOR_TX_05fmt */ 7767 /* nFields */ 1, 7768 /* *fields */ soc_DESCRIPTOR_TX_05fmt_fields, 7769 /* bits */ 32, 7770 /* flags */ 0, 7771 }, 7772 #endif /* chips */ 7773 7774 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \ 7775 defined(BCM_56142_A0) || defined(BCM_56224_A0) || \ 7776 defined(BCM_56224_B0) || defined(BCM_56314_A0) || \ 7777 defined(BCM_56334_A0) || defined(BCM_56334_B0) || \ 7778 defined(BCM_56440_A0) || defined(BCM_56440_B0) || \ 7779 defined(BCM_56504_A0) || defined(BCM_56504_B0) || \ 7780 defined(BCM_56514_A0) || defined(BCM_56524_A0) || \ 7781 defined(BCM_56524_B0) || defined(BCM_56624_A0) || \ 7782 defined(BCM_56624_B0) || defined(BCM_56634_A0) || \ 7783 defined(BCM_56634_B0) || defined(BCM_56680_A0) || \ 7784 defined(BCM_56680_B0) || defined(BCM_56685_B0) || \ 7785 defined(BCM_56725_A0) || defined(BCM_56820_A0) || \ 7786 defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 7787 defined(BCM_88732_A0) 7788 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_06fmt */ 7789 /* format DESCRIPTOR_TX_06fmt */ 7790 /* nFields */ 1, 7791 /* *fields */ soc_DESCRIPTOR_TX_06fmt_fields, 7792 /* bits */ 32, 7793 /* flags */ 0, 7794 }, 7795 #endif /* chips */ 7796 7797 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \ 7798 defined(BCM_56142_A0) || defined(BCM_56224_A0) || \ 7799 defined(BCM_56224_B0) || defined(BCM_56314_A0) || \ 7800 defined(BCM_56334_A0) || defined(BCM_56334_B0) || \ 7801 defined(BCM_56440_A0) || defined(BCM_56440_B0) || \ 7802 defined(BCM_56504_A0) || defined(BCM_56504_B0) || \ 7803 defined(BCM_56514_A0) || defined(BCM_56524_A0) || \ 7804 defined(BCM_56524_B0) || defined(BCM_56624_A0) || \ 7805 defined(BCM_56624_B0) || defined(BCM_56634_A0) || \ 7806 defined(BCM_56634_B0) || defined(BCM_56680_A0) || \ 7807 defined(BCM_56680_B0) || defined(BCM_56685_B0) || \ 7808 defined(BCM_56725_A0) || defined(BCM_56820_A0) || \ 7809 defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 7810 defined(BCM_88732_A0) 7811 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_07fmt */ 7812 /* format DESCRIPTOR_TX_07fmt */ 7813 /* nFields */ 1, 7814 /* *fields */ soc_DESCRIPTOR_TX_07fmt_fields, 7815 /* bits */ 32, 7816 /* flags */ 0, 7817 }, 7818 #endif /* chips */ 7819 7820 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \ 7821 defined(BCM_56142_A0) || defined(BCM_56224_A0) || \ 7822 defined(BCM_56224_B0) || defined(BCM_56314_A0) || \ 7823 defined(BCM_56334_A0) || defined(BCM_56334_B0) || \ 7824 defined(BCM_56440_A0) || defined(BCM_56440_B0) || \ 7825 defined(BCM_56504_A0) || defined(BCM_56504_B0) || \ 7826 defined(BCM_56514_A0) || defined(BCM_56524_A0) || \ 7827 defined(BCM_56524_B0) || defined(BCM_56624_A0) || \ 7828 defined(BCM_56624_B0) || defined(BCM_56634_A0) || \ 7829 defined(BCM_56634_B0) || defined(BCM_56680_A0) || \ 7830 defined(BCM_56680_B0) || defined(BCM_56685_A0) || \ 7831 defined(BCM_56685_B0) || defined(BCM_56725_A0) || \ 7832 defined(BCM_56800_A0) || defined(BCM_56820_A0) || \ 7833 defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 7834 defined(BCM_88732_A0) 7835 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_08fmt */ 7836 /* format DESCRIPTOR_TX_08fmt */ 7837 /* nFields */ 1, 7838 /* *fields */ soc_DESCRIPTOR_TX_08fmt_fields, 7839 /* bits */ 32, 7840 /* flags */ 0, 7841 }, 7842 #endif /* chips */ 7843 7844 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \ 7845 defined(BCM_56142_A0) || defined(BCM_56224_A0) || \ 7846 defined(BCM_56224_B0) || defined(BCM_56314_A0) || \ 7847 defined(BCM_56334_A0) || defined(BCM_56334_B0) || \ 7848 defined(BCM_56440_A0) || defined(BCM_56440_B0) || \ 7849 defined(BCM_56504_A0) || defined(BCM_56504_B0) || \ 7850 defined(BCM_56514_A0) || defined(BCM_56524_A0) || \ 7851 defined(BCM_56524_B0) || defined(BCM_56624_A0) || \ 7852 defined(BCM_56624_B0) || defined(BCM_56634_A0) || \ 7853 defined(BCM_56634_B0) || defined(BCM_56680_A0) || \ 7854 defined(BCM_56680_B0) || defined(BCM_56685_A0) || \ 7855 defined(BCM_56685_B0) || defined(BCM_56725_A0) || \ 7856 defined(BCM_56800_A0) || defined(BCM_56820_A0) || \ 7857 defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 7858 defined(BCM_88732_A0) 7859 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_09fmt */ 7860 /* format DESCRIPTOR_TX_09fmt */ 7861 /* nFields */ 1, 7862 /* *fields */ soc_DESCRIPTOR_TX_09fmt_fields, 7863 /* bits */ 32, 7864 /* flags */ 0, 7865 }, 7866 #endif /* chips */ 7867 7868 #if defined(BCM_53314_A0) || defined(BCM_53324_A0) || \ 7869 defined(BCM_56224_A0) || defined(BCM_56224_B0) || \ 7870 defined(BCM_56314_A0) || defined(BCM_56504_A0) || \ 7871 defined(BCM_56504_B0) || defined(BCM_56514_A0) || \ 7872 defined(BCM_56800_A0) 7873 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_10fmt */ 7874 /* format DESCRIPTOR_TX_10fmt */ 7875 /* nFields */ 2, 7876 /* *fields */ soc_DESCRIPTOR_TX_10fmt_fields, 7877 /* bits */ 32, 7878 /* flags */ 0, 7879 }, 7880 #endif /* chips */ 7881 7882 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \ 7883 defined(BCM_56334_B0) || defined(BCM_56440_A0) || \ 7884 defined(BCM_56440_B0) || defined(BCM_56524_A0) || \ 7885 defined(BCM_56524_B0) || defined(BCM_56624_A0) || \ 7886 defined(BCM_56624_B0) || defined(BCM_56634_A0) || \ 7887 defined(BCM_56634_B0) || defined(BCM_56680_A0) || \ 7888 defined(BCM_56680_B0) || defined(BCM_56685_A0) || \ 7889 defined(BCM_56685_B0) || defined(BCM_56725_A0) || \ 7890 defined(BCM_56820_A0) || defined(BCM_56840_A0) || \ 7891 defined(BCM_56840_B0) 7892 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_11fmt */ 7893 /* format DESCRIPTOR_TX_11fmt */ 7894 /* nFields */ 1, 7895 /* *fields */ soc_DESCRIPTOR_TX_11fmt_fields, 7896 /* bits */ 32, 7897 /* flags */ 0, 7898 }, 7899 #endif /* chips */ 7900 7901 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \ 7902 defined(BCM_56334_B0) || defined(BCM_56440_A0) || \ 7903 defined(BCM_56440_B0) || defined(BCM_56524_A0) || \ 7904 defined(BCM_56524_B0) || defined(BCM_56624_A0) || \ 7905 defined(BCM_56624_B0) || defined(BCM_56634_A0) || \ 7906 defined(BCM_56634_B0) || defined(BCM_56680_A0) || \ 7907 defined(BCM_56680_B0) || defined(BCM_56685_A0) || \ 7908 defined(BCM_56685_B0) || defined(BCM_56725_A0) || \ 7909 defined(BCM_56820_A0) || defined(BCM_56840_A0) || \ 7910 defined(BCM_56840_B0) 7911 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_12fmt */ 7912 /* format DESCRIPTOR_TX_12fmt */ 7913 /* nFields */ 1, 7914 /* *fields */ soc_DESCRIPTOR_TX_12fmt_fields, 7915 /* bits */ 32, 7916 /* flags */ 0, 7917 }, 7918 #endif /* chips */ 7919 7920 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \ 7921 defined(BCM_56334_B0) || defined(BCM_56440_A0) || \ 7922 defined(BCM_56440_B0) || defined(BCM_56524_A0) || \ 7923 defined(BCM_56524_B0) || defined(BCM_56624_A0) || \ 7924 defined(BCM_56624_B0) || defined(BCM_56634_A0) || \ 7925 defined(BCM_56634_B0) || defined(BCM_56680_A0) || \ 7926 defined(BCM_56680_B0) || defined(BCM_56685_A0) || \ 7927 defined(BCM_56685_B0) || defined(BCM_56725_A0) || \ 7928 defined(BCM_56820_A0) || defined(BCM_56840_A0) || \ 7929 defined(BCM_56840_B0) || defined(BCM_88732_A0) 7930 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_13fmt */ 7931 /* format DESCRIPTOR_TX_13fmt */ 7932 /* nFields */ 1, 7933 /* *fields */ soc_DESCRIPTOR_TX_13fmt_fields, 7934 /* bits */ 32, 7935 /* flags */ 0, 7936 }, 7937 #endif /* chips */ 7938 7939 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \ 7940 defined(BCM_56334_B0) || defined(BCM_56440_A0) || \ 7941 defined(BCM_56440_B0) || defined(BCM_56524_A0) || \ 7942 defined(BCM_56524_B0) || defined(BCM_56624_A0) || \ 7943 defined(BCM_56624_B0) || defined(BCM_56634_A0) || \ 7944 defined(BCM_56634_B0) || defined(BCM_56680_A0) || \ 7945 defined(BCM_56680_B0) || defined(BCM_56685_A0) || \ 7946 defined(BCM_56685_B0) || defined(BCM_56725_A0) || \ 7947 defined(BCM_56820_A0) || defined(BCM_56840_A0) || \ 7948 defined(BCM_56840_B0) || defined(BCM_88732_A0) 7949 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_14fmt */ 7950 /* format DESCRIPTOR_TX_14fmt */ 7951 /* nFields */ 1, 7952 /* *fields */ soc_DESCRIPTOR_TX_14fmt_fields, 7953 /* bits */ 32, 7954 /* flags */ 0, 7955 }, 7956 #endif /* chips */ 7957 7958 #if defined(BCM_56142_A0) || defined(BCM_56334_A0) || \ 7959 defined(BCM_56334_B0) || defined(BCM_56440_A0) || \ 7960 defined(BCM_56440_B0) || defined(BCM_56524_A0) || \ 7961 defined(BCM_56524_B0) || defined(BCM_56624_A0) || \ 7962 defined(BCM_56624_B0) || defined(BCM_56634_A0) || \ 7963 defined(BCM_56634_B0) || defined(BCM_56680_A0) || \ 7964 defined(BCM_56680_B0) || defined(BCM_56685_A0) || \ 7965 defined(BCM_56685_B0) || defined(BCM_56725_A0) || \ 7966 defined(BCM_56820_A0) || defined(BCM_56840_A0) || \ 7967 defined(BCM_56840_B0) || defined(BCM_88732_A0) 7968 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_15fmt */ 7969 /* format DESCRIPTOR_TX_15fmt */ 7970 /* nFields */ 2, 7971 /* *fields */ soc_DESCRIPTOR_TX_15fmt_fields, 7972 /* bits */ 32, 7973 /* flags */ 0, 7974 }, 7975 #endif /* chips */ 7976 7977 #if defined(BCM_53314_A0) 7978 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_00_BCM53314_A0fmt */ 7979 /* format DESCRIPTOR_TX_00fmt */ 7980 /* nFields */ 1, 7981 /* *fields */ soc_DESCRIPTOR_RX_00fmt_fields, 7982 /* bits */ 32, 7983 /* flags */ 0, 7984 }, 7985 #endif /* chips */ 7986 7987 #if defined(BCM_53324_A0) 7988 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_00_BCM53324_A0fmt */ 7989 /* format DESCRIPTOR_TX_00fmt */ 7990 /* nFields */ 1, 7991 /* *fields */ soc_DESCRIPTOR_RX_00fmt_fields, 7992 /* bits */ 32, 7993 /* flags */ 0, 7994 }, 7995 #endif /* chips */ 7996 7997 #if defined(BCM_53400_A0) 7998 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_00_BCM53400_A0fmt */ 7999 /* format DESCRIPTOR_TX_00fmt */ 8000 /* nFields */ 1, 8001 /* *fields */ soc_DESCRIPTOR_RX_00_BCM53400_A0fmt_fields, 8002 /* bits */ 32, 8003 /* flags */ 0, 8004 }, 8005 #endif /* chips */ 8006 8007 #if defined(BCM_53540_A0) 8008 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_00_BCM53540_A0fmt */ 8009 /* format DESCRIPTOR_TX_00fmt */ 8010 /* nFields */ 1, 8011 /* *fields */ soc_DESCRIPTOR_RX_00_BCM53400_A0fmt_fields, 8012 /* bits */ 32, 8013 /* flags */ 0, 8014 }, 8015 #endif /* chips */ 8016 8017 #if defined(BCM_53570_A0) 8018 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_00_BCM53570_A0fmt */ 8019 /* format DESCRIPTOR_TX_00fmt */ 8020 /* nFields */ 1, 8021 /* *fields */ soc_DESCRIPTOR_RX_00_BCM53400_A0fmt_fields, 8022 /* bits */ 32, 8023 /* flags */ 0, 8024 }, 8025 #endif /* chips */ 8026 8027 #if defined(BCM_53570_B0) 8028 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_00_BCM53570_B0fmt */ 8029 /* format DESCRIPTOR_TX_00fmt */ 8030 /* nFields */ 1, 8031 /* *fields */ soc_DESCRIPTOR_RX_00_BCM53400_A0fmt_fields, 8032 /* bits */ 32, 8033 /* flags */ 0, 8034 }, 8035 #endif /* chips */ 8036 8037 #if defined(BCM_56142_A0) 8038 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_00_BCM56142_A0fmt */ 8039 /* format DESCRIPTOR_TX_00fmt */ 8040 /* nFields */ 1, 8041 /* *fields */ soc_DESCRIPTOR_RX_00fmt_fields, 8042 /* bits */ 32, 8043 /* flags */ 0, 8044 }, 8045 #endif /* chips */ 8046 8047 #if defined(BCM_56150_A0) 8048 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_00_BCM56150_A0fmt */ 8049 /* format DESCRIPTOR_TX_00fmt */ 8050 /* nFields */ 1, 8051 /* *fields */ soc_DESCRIPTOR_RX_00_BCM56640_A0fmt_fields, 8052 /* bits */ 32, 8053 /* flags */ 0, 8054 }, 8055 #endif /* chips */ 8056 8057 #if defined(BCM_56160_A0) 8058 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_00_BCM56160_A0fmt */ 8059 /* format DESCRIPTOR_TX_00fmt */ 8060 /* nFields */ 1, 8061 /* *fields */ soc_DESCRIPTOR_RX_00_BCM53400_A0fmt_fields, 8062 /* bits */ 32, 8063 /* flags */ 0, 8064 }, 8065 #endif /* chips */ 8066 8067 #if defined(BCM_56224_A0) 8068 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_00_BCM56224_A0fmt */ 8069 /* format DESCRIPTOR_TX_00fmt */ 8070 /* nFields */ 1, 8071 /* *fields */ soc_DESCRIPTOR_RX_00fmt_fields, 8072 /* bits */ 32, 8073 /* flags */ 0, 8074 }, 8075 #endif /* chips */ 8076 8077 #if defined(BCM_56224_B0) 8078 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_00_BCM56224_B0fmt */ 8079 /* format DESCRIPTOR_TX_00fmt */ 8080 /* nFields */ 1, 8081 /* *fields */ soc_DESCRIPTOR_RX_00fmt_fields, 8082 /* bits */ 32, 8083 /* flags */ 0, 8084 }, 8085 #endif /* chips */ 8086 8087 #if defined(BCM_56260_A0) 8088 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_00_BCM56260_A0fmt */ 8089 /* format DESCRIPTOR_TX_00fmt */ 8090 /* nFields */ 1, 8091 /* *fields */ soc_DESCRIPTOR_RX_00_BCM53400_A0fmt_fields, 8092 /* bits */ 32, 8093 /* flags */ 0, 8094 }, 8095 #endif /* chips */ 8096 8097 #if defined(BCM_56260_B0) 8098 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_00_BCM56260_B0fmt */ 8099 /* format DESCRIPTOR_TX_00fmt */ 8100 /* nFields */ 1, 8101 /* *fields */ soc_DESCRIPTOR_RX_00_BCM53400_A0fmt_fields, 8102 /* bits */ 32, 8103 /* flags */ 0, 8104 }, 8105 #endif /* chips */ 8106 8107 #if defined(BCM_56270_A0) 8108 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_00_BCM56270_A0fmt */ 8109 /* format DESCRIPTOR_TX_00fmt */ 8110 /* nFields */ 1, 8111 /* *fields */ soc_DESCRIPTOR_RX_00_BCM53400_A0fmt_fields, 8112 /* bits */ 32, 8113 /* flags */ 0, 8114 }, 8115 #endif /* chips */ 8116 8117 #if defined(BCM_56314_A0) 8118 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_00_BCM56314_A0fmt */ 8119 /* format DESCRIPTOR_TX_00fmt */ 8120 /* nFields */ 1, 8121 /* *fields */ soc_DESCRIPTOR_RX_00fmt_fields, 8122 /* bits */ 32, 8123 /* flags */ 0, 8124 }, 8125 #endif /* chips */ 8126 8127 #if defined(BCM_56334_A0) 8128 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_00_BCM56334_A0fmt */ 8129 /* format DESCRIPTOR_TX_00fmt */ 8130 /* nFields */ 1, 8131 /* *fields */ soc_DESCRIPTOR_RX_00fmt_fields, 8132 /* bits */ 32, 8133 /* flags */ 0, 8134 }, 8135 #endif /* chips */ 8136 8137 #if defined(BCM_56334_B0) 8138 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_00_BCM56334_B0fmt */ 8139 /* format DESCRIPTOR_TX_00fmt */ 8140 /* nFields */ 1, 8141 /* *fields */ soc_DESCRIPTOR_RX_00fmt_fields, 8142 /* bits */ 32, 8143 /* flags */ 0, 8144 }, 8145 #endif /* chips */ 8146 8147 #if defined(BCM_56340_A0) 8148 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_00_BCM56340_A0fmt */ 8149 /* format DESCRIPTOR_TX_00fmt */ 8150 /* nFields */ 1, 8151 /* *fields */ soc_DESCRIPTOR_RX_00_BCM56640_A0fmt_fields, 8152 /* bits */ 32, 8153 /* flags */ 0, 8154 }, 8155 #endif /* chips */ 8156 8157 #if defined(BCM_56370_A0) 8158 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_00_BCM56370_A0fmt */ 8159 /* format DESCRIPTOR_TX_00fmt */ 8160 /* nFields */ 1, 8161 /* *fields */ soc_DESCRIPTOR_RX_00_BCM53400_A0fmt_fields, 8162 /* bits */ 32, 8163 /* flags */ 0, 8164 }, 8165 #endif /* chips */ 8166 8167 #if defined(BCM_56440_A0) 8168 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_00_BCM56440_A0fmt */ 8169 /* format DESCRIPTOR_TX_00fmt */ 8170 /* nFields */ 1, 8171 /* *fields */ soc_DESCRIPTOR_RX_00fmt_fields, 8172 /* bits */ 32, 8173 /* flags */ 0, 8174 }, 8175 #endif /* chips */ 8176 8177 #if defined(BCM_56440_B0) 8178 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_00_BCM56440_B0fmt */ 8179 /* format DESCRIPTOR_TX_00fmt */ 8180 /* nFields */ 1, 8181 /* *fields */ soc_DESCRIPTOR_RX_00fmt_fields, 8182 /* bits */ 32, 8183 /* flags */ 0, 8184 }, 8185 #endif /* chips */ 8186 8187 #if defined(BCM_56450_A0) 8188 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_00_BCM56450_A0fmt */ 8189 /* format DESCRIPTOR_TX_00fmt */ 8190 /* nFields */ 1, 8191 /* *fields */ soc_DESCRIPTOR_RX_00_BCM56640_A0fmt_fields, 8192 /* bits */ 32, 8193 /* flags */ 0, 8194 }, 8195 #endif /* chips */ 8196 8197 #if defined(BCM_56450_B0) 8198 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_00_BCM56450_B0fmt */ 8199 /* format DESCRIPTOR_TX_00fmt */ 8200 /* nFields */ 1, 8201 /* *fields */ soc_DESCRIPTOR_RX_00_BCM56640_A0fmt_fields, 8202 /* bits */ 32, 8203 /* flags */ 0, 8204 }, 8205 #endif /* chips */ 8206 8207 #if defined(BCM_56450_B1) 8208 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_00_BCM56450_B1fmt */ 8209 /* format DESCRIPTOR_TX_00fmt */ 8210 /* nFields */ 1, 8211 /* *fields */ soc_DESCRIPTOR_RX_00_BCM56640_A0fmt_fields, 8212 /* bits */ 32, 8213 /* flags */ 0, 8214 }, 8215 #endif /* chips */ 8216 8217 #if defined(BCM_56504_B0) 8218 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_00_BCM56504_B0fmt */ 8219 /* format DESCRIPTOR_TX_00fmt */ 8220 /* nFields */ 1, 8221 /* *fields */ soc_DESCRIPTOR_RX_00fmt_fields, 8222 /* bits */ 32, 8223 /* flags */ 0, 8224 }, 8225 #endif /* chips */ 8226 8227 #if defined(BCM_56514_A0) 8228 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_00_BCM56514_A0fmt */ 8229 /* format DESCRIPTOR_TX_00fmt */ 8230 /* nFields */ 1, 8231 /* *fields */ soc_DESCRIPTOR_RX_00fmt_fields, 8232 /* bits */ 32, 8233 /* flags */ 0, 8234 }, 8235 #endif /* chips */ 8236 8237 #if defined(BCM_56524_A0) 8238 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_00_BCM56524_A0fmt */ 8239 /* format DESCRIPTOR_TX_00fmt */ 8240 /* nFields */ 1, 8241 /* *fields */ soc_DESCRIPTOR_RX_00fmt_fields, 8242 /* bits */ 32, 8243 /* flags */ 0, 8244 }, 8245 #endif /* chips */ 8246 8247 #if defined(BCM_56524_B0) 8248 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_00_BCM56524_B0fmt */ 8249 /* format DESCRIPTOR_TX_00fmt */ 8250 /* nFields */ 1, 8251 /* *fields */ soc_DESCRIPTOR_RX_00fmt_fields, 8252 /* bits */ 32, 8253 /* flags */ 0, 8254 }, 8255 #endif /* chips */ 8256 8257 #if defined(BCM_56560_A0) 8258 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_00_BCM56560_A0fmt */ 8259 /* format DESCRIPTOR_TX_00fmt */ 8260 /* nFields */ 1, 8261 /* *fields */ soc_DESCRIPTOR_RX_00_BCM53400_A0fmt_fields, 8262 /* bits */ 32, 8263 /* flags */ 0, 8264 }, 8265 #endif /* chips */ 8266 8267 #if defined(BCM_56560_B0) 8268 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_00_BCM56560_B0fmt */ 8269 /* format DESCRIPTOR_TX_00fmt */ 8270 /* nFields */ 1, 8271 /* *fields */ soc_DESCRIPTOR_RX_00_BCM53400_A0fmt_fields, 8272 /* bits */ 32, 8273 /* flags */ 0, 8274 }, 8275 #endif /* chips */ 8276 8277 #if defined(BCM_56624_A0) 8278 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_00_BCM56624_A0fmt */ 8279 /* format DESCRIPTOR_TX_00fmt */ 8280 /* nFields */ 1, 8281 /* *fields */ soc_DESCRIPTOR_RX_00fmt_fields, 8282 /* bits */ 32, 8283 /* flags */ 0, 8284 }, 8285 #endif /* chips */ 8286 8287 #if defined(BCM_56624_B0) 8288 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_00_BCM56624_B0fmt */ 8289 /* format DESCRIPTOR_TX_00fmt */ 8290 /* nFields */ 1, 8291 /* *fields */ soc_DESCRIPTOR_RX_00fmt_fields, 8292 /* bits */ 32, 8293 /* flags */ 0, 8294 }, 8295 #endif /* chips */ 8296 8297 #if defined(BCM_56634_A0) 8298 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_00_BCM56634_A0fmt */ 8299 /* format DESCRIPTOR_TX_00fmt */ 8300 /* nFields */ 1, 8301 /* *fields */ soc_DESCRIPTOR_RX_00fmt_fields, 8302 /* bits */ 32, 8303 /* flags */ 0, 8304 }, 8305 #endif /* chips */ 8306 8307 #if defined(BCM_56634_B0) 8308 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_00_BCM56634_B0fmt */ 8309 /* format DESCRIPTOR_TX_00fmt */ 8310 /* nFields */ 1, 8311 /* *fields */ soc_DESCRIPTOR_RX_00fmt_fields, 8312 /* bits */ 32, 8313 /* flags */ 0, 8314 }, 8315 #endif /* chips */ 8316 8317 #if defined(BCM_56640_A0) 8318 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_00_BCM56640_A0fmt */ 8319 /* format DESCRIPTOR_TX_00fmt */ 8320 /* nFields */ 1, 8321 /* *fields */ soc_DESCRIPTOR_RX_00_BCM56640_A0fmt_fields, 8322 /* bits */ 32, 8323 /* flags */ 0, 8324 }, 8325 #endif /* chips */ 8326 8327 #if defined(BCM_56670_A0) 8328 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_00_BCM56670_A0fmt */ 8329 /* format DESCRIPTOR_TX_00fmt */ 8330 /* nFields */ 1, 8331 /* *fields */ soc_DESCRIPTOR_RX_00_BCM53400_A0fmt_fields, 8332 /* bits */ 32, 8333 /* flags */ 0, 8334 }, 8335 #endif /* chips */ 8336 8337 #if defined(BCM_56670_B0) 8338 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_00_BCM56670_B0fmt */ 8339 /* format DESCRIPTOR_TX_00fmt */ 8340 /* nFields */ 1, 8341 /* *fields */ soc_DESCRIPTOR_RX_00_BCM53400_A0fmt_fields, 8342 /* bits */ 32, 8343 /* flags */ 0, 8344 }, 8345 #endif /* chips */ 8346 8347 #if defined(BCM_56680_A0) 8348 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_00_BCM56680_A0fmt */ 8349 /* format DESCRIPTOR_TX_00fmt */ 8350 /* nFields */ 1, 8351 /* *fields */ soc_DESCRIPTOR_RX_00fmt_fields, 8352 /* bits */ 32, 8353 /* flags */ 0, 8354 }, 8355 #endif /* chips */ 8356 8357 #if defined(BCM_56680_B0) 8358 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_00_BCM56680_B0fmt */ 8359 /* format DESCRIPTOR_TX_00fmt */ 8360 /* nFields */ 1, 8361 /* *fields */ soc_DESCRIPTOR_RX_00fmt_fields, 8362 /* bits */ 32, 8363 /* flags */ 0, 8364 }, 8365 #endif /* chips */ 8366 8367 #if defined(BCM_56685_A0) 8368 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_00_BCM56685_A0fmt */ 8369 /* format DESCRIPTOR_TX_00fmt */ 8370 /* nFields */ 1, 8371 /* *fields */ soc_DESCRIPTOR_RX_00fmt_fields, 8372 /* bits */ 32, 8373 /* flags */ 0, 8374 }, 8375 #endif /* chips */ 8376 8377 #if defined(BCM_56685_B0) 8378 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_00_BCM56685_B0fmt */ 8379 /* format DESCRIPTOR_TX_00fmt */ 8380 /* nFields */ 1, 8381 /* *fields */ soc_DESCRIPTOR_RX_00fmt_fields, 8382 /* bits */ 32, 8383 /* flags */ 0, 8384 }, 8385 #endif /* chips */ 8386 8387 #if defined(BCM_56725_A0) 8388 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_00_BCM56725_A0fmt */ 8389 /* format DESCRIPTOR_TX_00fmt */ 8390 /* nFields */ 1, 8391 /* *fields */ soc_DESCRIPTOR_RX_00fmt_fields, 8392 /* bits */ 32, 8393 /* flags */ 0, 8394 }, 8395 #endif /* chips */ 8396 8397 #if defined(BCM_56770_A0) 8398 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_00_BCM56770_A0fmt */ 8399 /* format DESCRIPTOR_TX_00fmt */ 8400 /* nFields */ 1, 8401 /* *fields */ soc_DESCRIPTOR_RX_00_BCM53400_A0fmt_fields, 8402 /* bits */ 32, 8403 /* flags */ 0, 8404 }, 8405 #endif /* chips */ 8406 8407 #if defined(BCM_56800_A0) 8408 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_00_BCM56800_A0fmt */ 8409 /* format DESCRIPTOR_TX_00fmt */ 8410 /* nFields */ 1, 8411 /* *fields */ soc_DESCRIPTOR_RX_00fmt_fields, 8412 /* bits */ 32, 8413 /* flags */ 0, 8414 }, 8415 #endif /* chips */ 8416 8417 #if defined(BCM_56820_A0) 8418 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_00_BCM56820_A0fmt */ 8419 /* format DESCRIPTOR_TX_00fmt */ 8420 /* nFields */ 1, 8421 /* *fields */ soc_DESCRIPTOR_RX_00fmt_fields, 8422 /* bits */ 32, 8423 /* flags */ 0, 8424 }, 8425 #endif /* chips */ 8426 8427 #if defined(BCM_56840_A0) 8428 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_00_BCM56840_A0fmt */ 8429 /* format DESCRIPTOR_TX_00fmt */ 8430 /* nFields */ 1, 8431 /* *fields */ soc_DESCRIPTOR_RX_00fmt_fields, 8432 /* bits */ 32, 8433 /* flags */ 0, 8434 }, 8435 #endif /* chips */ 8436 8437 #if defined(BCM_56840_B0) 8438 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_00_BCM56840_B0fmt */ 8439 /* format DESCRIPTOR_TX_00fmt */ 8440 /* nFields */ 1, 8441 /* *fields */ soc_DESCRIPTOR_RX_00fmt_fields, 8442 /* bits */ 32, 8443 /* flags */ 0, 8444 }, 8445 #endif /* chips */ 8446 8447 #if defined(BCM_56850_A0) 8448 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_00_BCM56850_A0fmt */ 8449 /* format DESCRIPTOR_TX_00fmt */ 8450 /* nFields */ 1, 8451 /* *fields */ soc_DESCRIPTOR_RX_00_BCM56640_A0fmt_fields, 8452 /* bits */ 32, 8453 /* flags */ 0, 8454 }, 8455 #endif /* chips */ 8456 8457 #if defined(BCM_56860_A0) 8458 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_00_BCM56860_A0fmt */ 8459 /* format DESCRIPTOR_TX_00fmt */ 8460 /* nFields */ 1, 8461 /* *fields */ soc_DESCRIPTOR_RX_00_BCM56640_A0fmt_fields, 8462 /* bits */ 32, 8463 /* flags */ 0, 8464 }, 8465 #endif /* chips */ 8466 8467 #if defined(BCM_56870_A0) 8468 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_00_BCM56870_A0fmt */ 8469 /* format DESCRIPTOR_TX_00fmt */ 8470 /* nFields */ 1, 8471 /* *fields */ soc_DESCRIPTOR_RX_00_BCM53400_A0fmt_fields, 8472 /* bits */ 32, 8473 /* flags */ 0, 8474 }, 8475 #endif /* chips */ 8476 8477 #if defined(BCM_56960_A0) 8478 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_00_BCM56960_A0fmt */ 8479 /* format DESCRIPTOR_TX_00fmt */ 8480 /* nFields */ 1, 8481 /* *fields */ soc_DESCRIPTOR_RX_00_BCM53400_A0fmt_fields, 8482 /* bits */ 32, 8483 /* flags */ 0, 8484 }, 8485 #endif /* chips */ 8486 8487 #if defined(BCM_56965_A0) 8488 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_00_BCM56965_A0fmt */ 8489 /* format DESCRIPTOR_TX_00fmt */ 8490 /* nFields */ 1, 8491 /* *fields */ soc_DESCRIPTOR_RX_00_BCM53400_A0fmt_fields, 8492 /* bits */ 32, 8493 /* flags */ 0, 8494 }, 8495 #endif /* chips */ 8496 8497 #if defined(BCM_56970_A0) 8498 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_00_BCM56970_A0fmt */ 8499 /* format DESCRIPTOR_TX_00fmt */ 8500 /* nFields */ 1, 8501 /* *fields */ soc_DESCRIPTOR_RX_00_BCM53400_A0fmt_fields, 8502 /* bits */ 32, 8503 /* flags */ 0, 8504 }, 8505 #endif /* chips */ 8506 8507 #if defined(BCM_56980_A0) 8508 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_00_BCM56980_A0fmt */ 8509 /* format DESCRIPTOR_TX_00fmt */ 8510 /* nFields */ 1, 8511 /* *fields */ soc_DESCRIPTOR_RX_00_BCM53400_A0fmt_fields, 8512 /* bits */ 32, 8513 /* flags */ 0, 8514 }, 8515 #endif /* chips */ 8516 8517 #if defined(BCM_56980_B0) 8518 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_00_BCM56980_B0fmt */ 8519 /* format DESCRIPTOR_TX_00fmt */ 8520 /* nFields */ 1, 8521 /* *fields */ soc_DESCRIPTOR_RX_00_BCM53400_A0fmt_fields, 8522 /* bits */ 32, 8523 /* flags */ 0, 8524 }, 8525 #endif /* chips */ 8526 8527 #if defined(BCM_88732_A0) 8528 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_00_BCM88732_A0fmt */ 8529 /* format DESCRIPTOR_TX_00fmt */ 8530 /* nFields */ 1, 8531 /* *fields */ soc_DESCRIPTOR_RX_00fmt_fields, 8532 /* bits */ 32, 8533 /* flags */ 0, 8534 }, 8535 #endif /* chips */ 8536 8537 #if defined(BCM_53400_A0) 8538 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_01_BCM53400_A0fmt */ 8539 /* format DESCRIPTOR_TX_01fmt */ 8540 /* nFields */ 9, 8541 /* *fields */ soc_DESCRIPTOR_TX_01_BCM53400_A0fmt_fields, 8542 /* bits */ 25, 8543 /* flags */ 0, 8544 }, 8545 #endif /* chips */ 8546 8547 #if defined(BCM_53540_A0) 8548 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_01_BCM53540_A0fmt */ 8549 /* format DESCRIPTOR_TX_01fmt */ 8550 /* nFields */ 9, 8551 /* *fields */ soc_DESCRIPTOR_TX_01_BCM53400_A0fmt_fields, 8552 /* bits */ 25, 8553 /* flags */ 0, 8554 }, 8555 #endif /* chips */ 8556 8557 #if defined(BCM_53570_A0) 8558 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_01_BCM53570_A0fmt */ 8559 /* format DESCRIPTOR_TX_01fmt */ 8560 /* nFields */ 9, 8561 /* *fields */ soc_DESCRIPTOR_TX_01_BCM53400_A0fmt_fields, 8562 /* bits */ 25, 8563 /* flags */ 0, 8564 }, 8565 #endif /* chips */ 8566 8567 #if defined(BCM_53570_B0) 8568 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_01_BCM53570_B0fmt */ 8569 /* format DESCRIPTOR_TX_01fmt */ 8570 /* nFields */ 9, 8571 /* *fields */ soc_DESCRIPTOR_TX_01_BCM53400_A0fmt_fields, 8572 /* bits */ 25, 8573 /* flags */ 0, 8574 }, 8575 #endif /* chips */ 8576 8577 #if defined(BCM_56150_A0) 8578 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_01_BCM56150_A0fmt */ 8579 /* format DESCRIPTOR_TX_01fmt */ 8580 /* nFields */ 8, 8581 /* *fields */ soc_DESCRIPTOR_TX_01_BCM56640_A0fmt_fields, 8582 /* bits */ 23, 8583 /* flags */ 0, 8584 }, 8585 #endif /* chips */ 8586 8587 #if defined(BCM_56160_A0) 8588 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_01_BCM56160_A0fmt */ 8589 /* format DESCRIPTOR_TX_01fmt */ 8590 /* nFields */ 9, 8591 /* *fields */ soc_DESCRIPTOR_TX_01_BCM53400_A0fmt_fields, 8592 /* bits */ 25, 8593 /* flags */ 0, 8594 }, 8595 #endif /* chips */ 8596 8597 #if defined(BCM_56260_A0) 8598 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_01_BCM56260_A0fmt */ 8599 /* format DESCRIPTOR_TX_01fmt */ 8600 /* nFields */ 9, 8601 /* *fields */ soc_DESCRIPTOR_TX_01_BCM53400_A0fmt_fields, 8602 /* bits */ 25, 8603 /* flags */ 0, 8604 }, 8605 #endif /* chips */ 8606 8607 #if defined(BCM_56260_B0) 8608 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_01_BCM56260_B0fmt */ 8609 /* format DESCRIPTOR_TX_01fmt */ 8610 /* nFields */ 9, 8611 /* *fields */ soc_DESCRIPTOR_TX_01_BCM53400_A0fmt_fields, 8612 /* bits */ 25, 8613 /* flags */ 0, 8614 }, 8615 #endif /* chips */ 8616 8617 #if defined(BCM_56270_A0) 8618 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_01_BCM56270_A0fmt */ 8619 /* format DESCRIPTOR_TX_01fmt */ 8620 /* nFields */ 9, 8621 /* *fields */ soc_DESCRIPTOR_TX_01_BCM53400_A0fmt_fields, 8622 /* bits */ 25, 8623 /* flags */ 0, 8624 }, 8625 #endif /* chips */ 8626 8627 #if defined(BCM_56340_A0) 8628 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_01_BCM56340_A0fmt */ 8629 /* format DESCRIPTOR_TX_01fmt */ 8630 /* nFields */ 8, 8631 /* *fields */ soc_DESCRIPTOR_TX_01_BCM56640_A0fmt_fields, 8632 /* bits */ 23, 8633 /* flags */ 0, 8634 }, 8635 #endif /* chips */ 8636 8637 #if defined(BCM_56370_A0) 8638 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_01_BCM56370_A0fmt */ 8639 /* format DESCRIPTOR_TX_01fmt */ 8640 /* nFields */ 1, 8641 /* *fields */ soc_DESCRIPTOR_RX_01_BCM56870_A0fmt_fields, 8642 /* bits */ 32, 8643 /* flags */ 0, 8644 }, 8645 #endif /* chips */ 8646 8647 #if defined(BCM_56450_A0) 8648 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_01_BCM56450_A0fmt */ 8649 /* format DESCRIPTOR_TX_01fmt */ 8650 /* nFields */ 8, 8651 /* *fields */ soc_DESCRIPTOR_TX_01_BCM56640_A0fmt_fields, 8652 /* bits */ 23, 8653 /* flags */ 0, 8654 }, 8655 #endif /* chips */ 8656 8657 #if defined(BCM_56450_B0) 8658 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_01_BCM56450_B0fmt */ 8659 /* format DESCRIPTOR_TX_01fmt */ 8660 /* nFields */ 8, 8661 /* *fields */ soc_DESCRIPTOR_TX_01_BCM56640_A0fmt_fields, 8662 /* bits */ 23, 8663 /* flags */ 0, 8664 }, 8665 #endif /* chips */ 8666 8667 #if defined(BCM_56450_B1) 8668 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_01_BCM56450_B1fmt */ 8669 /* format DESCRIPTOR_TX_01fmt */ 8670 /* nFields */ 8, 8671 /* *fields */ soc_DESCRIPTOR_TX_01_BCM56640_A0fmt_fields, 8672 /* bits */ 23, 8673 /* flags */ 0, 8674 }, 8675 #endif /* chips */ 8676 8677 #if defined(BCM_56560_A0) 8678 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_01_BCM56560_A0fmt */ 8679 /* format DESCRIPTOR_TX_01fmt */ 8680 /* nFields */ 9, 8681 /* *fields */ soc_DESCRIPTOR_TX_01_BCM53400_A0fmt_fields, 8682 /* bits */ 25, 8683 /* flags */ 0, 8684 }, 8685 #endif /* chips */ 8686 8687 #if defined(BCM_56560_B0) 8688 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_01_BCM56560_B0fmt */ 8689 /* format DESCRIPTOR_TX_01fmt */ 8690 /* nFields */ 9, 8691 /* *fields */ soc_DESCRIPTOR_TX_01_BCM53400_A0fmt_fields, 8692 /* bits */ 25, 8693 /* flags */ 0, 8694 }, 8695 #endif /* chips */ 8696 8697 #if defined(BCM_56640_A0) 8698 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_01_BCM56640_A0fmt */ 8699 /* format DESCRIPTOR_TX_01fmt */ 8700 /* nFields */ 8, 8701 /* *fields */ soc_DESCRIPTOR_TX_01_BCM56640_A0fmt_fields, 8702 /* bits */ 23, 8703 /* flags */ 0, 8704 }, 8705 #endif /* chips */ 8706 8707 #if defined(BCM_56670_A0) 8708 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_01_BCM56670_A0fmt */ 8709 /* format DESCRIPTOR_TX_01fmt */ 8710 /* nFields */ 9, 8711 /* *fields */ soc_DESCRIPTOR_TX_01_BCM53400_A0fmt_fields, 8712 /* bits */ 25, 8713 /* flags */ 0, 8714 }, 8715 #endif /* chips */ 8716 8717 #if defined(BCM_56670_B0) 8718 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_01_BCM56670_B0fmt */ 8719 /* format DESCRIPTOR_TX_01fmt */ 8720 /* nFields */ 9, 8721 /* *fields */ soc_DESCRIPTOR_TX_01_BCM53400_A0fmt_fields, 8722 /* bits */ 25, 8723 /* flags */ 0, 8724 }, 8725 #endif /* chips */ 8726 8727 #if defined(BCM_56770_A0) 8728 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_01_BCM56770_A0fmt */ 8729 /* format DESCRIPTOR_TX_01fmt */ 8730 /* nFields */ 1, 8731 /* *fields */ soc_DESCRIPTOR_RX_01_BCM56870_A0fmt_fields, 8732 /* bits */ 32, 8733 /* flags */ 0, 8734 }, 8735 #endif /* chips */ 8736 8737 #if defined(BCM_56800_A0) 8738 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_01_BCM56800_A0fmt */ 8739 /* format DESCRIPTOR_TX_01fmt */ 8740 /* nFields */ 8, 8741 /* *fields */ soc_DESCRIPTOR_TX_01_BCM56800_A0fmt_fields, 8742 /* bits */ 23, 8743 /* flags */ 0, 8744 }, 8745 #endif /* chips */ 8746 8747 #if defined(BCM_56850_A0) 8748 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_01_BCM56850_A0fmt */ 8749 /* format DESCRIPTOR_TX_01fmt */ 8750 /* nFields */ 8, 8751 /* *fields */ soc_DESCRIPTOR_TX_01_BCM56640_A0fmt_fields, 8752 /* bits */ 23, 8753 /* flags */ 0, 8754 }, 8755 #endif /* chips */ 8756 8757 #if defined(BCM_56860_A0) 8758 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_01_BCM56860_A0fmt */ 8759 /* format DESCRIPTOR_TX_01fmt */ 8760 /* nFields */ 8, 8761 /* *fields */ soc_DESCRIPTOR_TX_01_BCM56640_A0fmt_fields, 8762 /* bits */ 23, 8763 /* flags */ 0, 8764 }, 8765 #endif /* chips */ 8766 8767 #if defined(BCM_56870_A0) 8768 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_01_BCM56870_A0fmt */ 8769 /* format DESCRIPTOR_TX_01fmt */ 8770 /* nFields */ 1, 8771 /* *fields */ soc_DESCRIPTOR_RX_01_BCM56870_A0fmt_fields, 8772 /* bits */ 32, 8773 /* flags */ 0, 8774 }, 8775 #endif /* chips */ 8776 8777 #if defined(BCM_56960_A0) 8778 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_01_BCM56960_A0fmt */ 8779 /* format DESCRIPTOR_TX_01fmt */ 8780 /* nFields */ 9, 8781 /* *fields */ soc_DESCRIPTOR_TX_01_BCM53400_A0fmt_fields, 8782 /* bits */ 25, 8783 /* flags */ 0, 8784 }, 8785 #endif /* chips */ 8786 8787 #if defined(BCM_56965_A0) 8788 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_01_BCM56965_A0fmt */ 8789 /* format DESCRIPTOR_TX_01fmt */ 8790 /* nFields */ 9, 8791 /* *fields */ soc_DESCRIPTOR_TX_01_BCM53400_A0fmt_fields, 8792 /* bits */ 25, 8793 /* flags */ 0, 8794 }, 8795 #endif /* chips */ 8796 8797 #if defined(BCM_56970_A0) 8798 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_01_BCM56970_A0fmt */ 8799 /* format DESCRIPTOR_TX_01fmt */ 8800 /* nFields */ 9, 8801 /* *fields */ soc_DESCRIPTOR_TX_01_BCM53400_A0fmt_fields, 8802 /* bits */ 25, 8803 /* flags */ 0, 8804 }, 8805 #endif /* chips */ 8806 8807 #if defined(BCM_56980_A0) 8808 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_01_BCM56980_A0fmt */ 8809 /* format DESCRIPTOR_TX_01fmt */ 8810 /* nFields */ 1, 8811 /* *fields */ soc_DESCRIPTOR_RX_01_BCM56870_A0fmt_fields, 8812 /* bits */ 32, 8813 /* flags */ 0, 8814 }, 8815 #endif /* chips */ 8816 8817 #if defined(BCM_56980_B0) 8818 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_01_BCM56980_B0fmt */ 8819 /* format DESCRIPTOR_TX_01fmt */ 8820 /* nFields */ 1, 8821 /* *fields */ soc_DESCRIPTOR_RX_01_BCM56870_A0fmt_fields, 8822 /* bits */ 32, 8823 /* flags */ 0, 8824 }, 8825 #endif /* chips */ 8826 8827 #if defined(BCM_53314_A0) 8828 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_02_BCM53314_A0fmt */ 8829 /* format DESCRIPTOR_TX_02fmt */ 8830 /* nFields */ 1, 8831 /* *fields */ soc_DESCRIPTOR_TX_02fmt_fields, 8832 /* bits */ 32, 8833 /* flags */ 0, 8834 }, 8835 #endif /* chips */ 8836 8837 #if defined(BCM_53324_A0) 8838 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_02_BCM53324_A0fmt */ 8839 /* format DESCRIPTOR_TX_02fmt */ 8840 /* nFields */ 1, 8841 /* *fields */ soc_DESCRIPTOR_TX_02fmt_fields, 8842 /* bits */ 32, 8843 /* flags */ 0, 8844 }, 8845 #endif /* chips */ 8846 8847 #if defined(BCM_53400_A0) 8848 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_02_BCM53400_A0fmt */ 8849 /* format DESCRIPTOR_TX_02fmt */ 8850 /* nFields */ 1, 8851 /* *fields */ soc_DESCRIPTOR_TX_02_BCM53400_A0fmt_fields, 8852 /* bits */ 32, 8853 /* flags */ 0, 8854 }, 8855 #endif /* chips */ 8856 8857 #if defined(BCM_53540_A0) 8858 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_02_BCM53540_A0fmt */ 8859 /* format DESCRIPTOR_TX_02fmt */ 8860 /* nFields */ 1, 8861 /* *fields */ soc_DESCRIPTOR_TX_02_BCM53400_A0fmt_fields, 8862 /* bits */ 32, 8863 /* flags */ 0, 8864 }, 8865 #endif /* chips */ 8866 8867 #if defined(BCM_53570_A0) 8868 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_02_BCM53570_A0fmt */ 8869 /* format DESCRIPTOR_TX_02fmt */ 8870 /* nFields */ 1, 8871 /* *fields */ soc_DESCRIPTOR_TX_02_BCM53400_A0fmt_fields, 8872 /* bits */ 32, 8873 /* flags */ 0, 8874 }, 8875 #endif /* chips */ 8876 8877 #if defined(BCM_53570_B0) 8878 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_02_BCM53570_B0fmt */ 8879 /* format DESCRIPTOR_TX_02fmt */ 8880 /* nFields */ 1, 8881 /* *fields */ soc_DESCRIPTOR_TX_02_BCM53400_A0fmt_fields, 8882 /* bits */ 32, 8883 /* flags */ 0, 8884 }, 8885 #endif /* chips */ 8886 8887 #if defined(BCM_56142_A0) 8888 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_02_BCM56142_A0fmt */ 8889 /* format DESCRIPTOR_TX_02fmt */ 8890 /* nFields */ 1, 8891 /* *fields */ soc_DESCRIPTOR_TX_02fmt_fields, 8892 /* bits */ 32, 8893 /* flags */ 0, 8894 }, 8895 #endif /* chips */ 8896 8897 #if defined(BCM_56150_A0) 8898 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_02_BCM56150_A0fmt */ 8899 /* format DESCRIPTOR_TX_02fmt */ 8900 /* nFields */ 1, 8901 /* *fields */ soc_DESCRIPTOR_TX_02_BCM56640_A0fmt_fields, 8902 /* bits */ 32, 8903 /* flags */ 0, 8904 }, 8905 #endif /* chips */ 8906 8907 #if defined(BCM_56160_A0) 8908 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_02_BCM56160_A0fmt */ 8909 /* format DESCRIPTOR_TX_02fmt */ 8910 /* nFields */ 1, 8911 /* *fields */ soc_DESCRIPTOR_TX_02_BCM53400_A0fmt_fields, 8912 /* bits */ 32, 8913 /* flags */ 0, 8914 }, 8915 #endif /* chips */ 8916 8917 #if defined(BCM_56224_A0) 8918 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_02_BCM56224_A0fmt */ 8919 /* format DESCRIPTOR_TX_02fmt */ 8920 /* nFields */ 1, 8921 /* *fields */ soc_DESCRIPTOR_TX_02fmt_fields, 8922 /* bits */ 32, 8923 /* flags */ 0, 8924 }, 8925 #endif /* chips */ 8926 8927 #if defined(BCM_56224_B0) 8928 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_02_BCM56224_B0fmt */ 8929 /* format DESCRIPTOR_TX_02fmt */ 8930 /* nFields */ 1, 8931 /* *fields */ soc_DESCRIPTOR_TX_02fmt_fields, 8932 /* bits */ 32, 8933 /* flags */ 0, 8934 }, 8935 #endif /* chips */ 8936 8937 #if defined(BCM_56260_A0) 8938 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_02_BCM56260_A0fmt */ 8939 /* format DESCRIPTOR_TX_02fmt */ 8940 /* nFields */ 1, 8941 /* *fields */ soc_DESCRIPTOR_TX_02_BCM53400_A0fmt_fields, 8942 /* bits */ 32, 8943 /* flags */ 0, 8944 }, 8945 #endif /* chips */ 8946 8947 #if defined(BCM_56260_B0) 8948 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_02_BCM56260_B0fmt */ 8949 /* format DESCRIPTOR_TX_02fmt */ 8950 /* nFields */ 1, 8951 /* *fields */ soc_DESCRIPTOR_TX_02_BCM53400_A0fmt_fields, 8952 /* bits */ 32, 8953 /* flags */ 0, 8954 }, 8955 #endif /* chips */ 8956 8957 #if defined(BCM_56270_A0) 8958 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_02_BCM56270_A0fmt */ 8959 /* format DESCRIPTOR_TX_02fmt */ 8960 /* nFields */ 1, 8961 /* *fields */ soc_DESCRIPTOR_TX_02_BCM53400_A0fmt_fields, 8962 /* bits */ 32, 8963 /* flags */ 0, 8964 }, 8965 #endif /* chips */ 8966 8967 #if defined(BCM_56314_A0) 8968 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_02_BCM56314_A0fmt */ 8969 /* format DESCRIPTOR_TX_02fmt */ 8970 /* nFields */ 1, 8971 /* *fields */ soc_DESCRIPTOR_RX_02fmt_fields, 8972 /* bits */ 32, 8973 /* flags */ 0, 8974 }, 8975 #endif /* chips */ 8976 8977 #if defined(BCM_56334_A0) 8978 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_02_BCM56334_A0fmt */ 8979 /* format DESCRIPTOR_TX_02fmt */ 8980 /* nFields */ 1, 8981 /* *fields */ soc_DESCRIPTOR_TX_02fmt_fields, 8982 /* bits */ 32, 8983 /* flags */ 0, 8984 }, 8985 #endif /* chips */ 8986 8987 #if defined(BCM_56334_B0) 8988 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_02_BCM56334_B0fmt */ 8989 /* format DESCRIPTOR_TX_02fmt */ 8990 /* nFields */ 1, 8991 /* *fields */ soc_DESCRIPTOR_TX_02fmt_fields, 8992 /* bits */ 32, 8993 /* flags */ 0, 8994 }, 8995 #endif /* chips */ 8996 8997 #if defined(BCM_56340_A0) 8998 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_02_BCM56340_A0fmt */ 8999 /* format DESCRIPTOR_TX_02fmt */ 9000 /* nFields */ 1, 9001 /* *fields */ soc_DESCRIPTOR_TX_02_BCM56640_A0fmt_fields, 9002 /* bits */ 32, 9003 /* flags */ 0, 9004 }, 9005 #endif /* chips */ 9006 9007 #if defined(BCM_56370_A0) 9008 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_02_BCM56370_A0fmt */ 9009 /* format DESCRIPTOR_TX_02fmt */ 9010 /* nFields */ 9, 9011 /* *fields */ soc_DESCRIPTOR_TX_02_BCM56870_A0fmt_fields, 9012 /* bits */ 30, 9013 /* flags */ 0, 9014 }, 9015 #endif /* chips */ 9016 9017 #if defined(BCM_56440_A0) 9018 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_02_BCM56440_A0fmt */ 9019 /* format DESCRIPTOR_TX_02fmt */ 9020 /* nFields */ 1, 9021 /* *fields */ soc_DESCRIPTOR_TX_02fmt_fields, 9022 /* bits */ 32, 9023 /* flags */ 0, 9024 }, 9025 #endif /* chips */ 9026 9027 #if defined(BCM_56440_B0) 9028 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_02_BCM56440_B0fmt */ 9029 /* format DESCRIPTOR_TX_02fmt */ 9030 /* nFields */ 1, 9031 /* *fields */ soc_DESCRIPTOR_TX_02fmt_fields, 9032 /* bits */ 32, 9033 /* flags */ 0, 9034 }, 9035 #endif /* chips */ 9036 9037 #if defined(BCM_56450_A0) 9038 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_02_BCM56450_A0fmt */ 9039 /* format DESCRIPTOR_TX_02fmt */ 9040 /* nFields */ 1, 9041 /* *fields */ soc_DESCRIPTOR_TX_02_BCM56640_A0fmt_fields, 9042 /* bits */ 32, 9043 /* flags */ 0, 9044 }, 9045 #endif /* chips */ 9046 9047 #if defined(BCM_56450_B0) 9048 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_02_BCM56450_B0fmt */ 9049 /* format DESCRIPTOR_TX_02fmt */ 9050 /* nFields */ 1, 9051 /* *fields */ soc_DESCRIPTOR_TX_02_BCM56640_A0fmt_fields, 9052 /* bits */ 32, 9053 /* flags */ 0, 9054 }, 9055 #endif /* chips */ 9056 9057 #if defined(BCM_56450_B1) 9058 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_02_BCM56450_B1fmt */ 9059 /* format DESCRIPTOR_TX_02fmt */ 9060 /* nFields */ 1, 9061 /* *fields */ soc_DESCRIPTOR_TX_02_BCM56640_A0fmt_fields, 9062 /* bits */ 32, 9063 /* flags */ 0, 9064 }, 9065 #endif /* chips */ 9066 9067 #if defined(BCM_56504_B0) 9068 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_02_BCM56504_B0fmt */ 9069 /* format DESCRIPTOR_TX_02fmt */ 9070 /* nFields */ 1, 9071 /* *fields */ soc_DESCRIPTOR_RX_02fmt_fields, 9072 /* bits */ 32, 9073 /* flags */ 0, 9074 }, 9075 #endif /* chips */ 9076 9077 #if defined(BCM_56514_A0) 9078 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_02_BCM56514_A0fmt */ 9079 /* format DESCRIPTOR_TX_02fmt */ 9080 /* nFields */ 1, 9081 /* *fields */ soc_DESCRIPTOR_RX_02fmt_fields, 9082 /* bits */ 32, 9083 /* flags */ 0, 9084 }, 9085 #endif /* chips */ 9086 9087 #if defined(BCM_56524_A0) 9088 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_02_BCM56524_A0fmt */ 9089 /* format DESCRIPTOR_TX_02fmt */ 9090 /* nFields */ 1, 9091 /* *fields */ soc_DESCRIPTOR_TX_02fmt_fields, 9092 /* bits */ 32, 9093 /* flags */ 0, 9094 }, 9095 #endif /* chips */ 9096 9097 #if defined(BCM_56524_B0) 9098 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_02_BCM56524_B0fmt */ 9099 /* format DESCRIPTOR_TX_02fmt */ 9100 /* nFields */ 1, 9101 /* *fields */ soc_DESCRIPTOR_TX_02fmt_fields, 9102 /* bits */ 32, 9103 /* flags */ 0, 9104 }, 9105 #endif /* chips */ 9106 9107 #if defined(BCM_56560_A0) 9108 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_02_BCM56560_A0fmt */ 9109 /* format DESCRIPTOR_TX_02fmt */ 9110 /* nFields */ 1, 9111 /* *fields */ soc_DESCRIPTOR_TX_02_BCM53400_A0fmt_fields, 9112 /* bits */ 32, 9113 /* flags */ 0, 9114 }, 9115 #endif /* chips */ 9116 9117 #if defined(BCM_56560_B0) 9118 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_02_BCM56560_B0fmt */ 9119 /* format DESCRIPTOR_TX_02fmt */ 9120 /* nFields */ 1, 9121 /* *fields */ soc_DESCRIPTOR_TX_02_BCM53400_A0fmt_fields, 9122 /* bits */ 32, 9123 /* flags */ 0, 9124 }, 9125 #endif /* chips */ 9126 9127 #if defined(BCM_56624_A0) 9128 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_02_BCM56624_A0fmt */ 9129 /* format DESCRIPTOR_TX_02fmt */ 9130 /* nFields */ 1, 9131 /* *fields */ soc_DESCRIPTOR_TX_02fmt_fields, 9132 /* bits */ 32, 9133 /* flags */ 0, 9134 }, 9135 #endif /* chips */ 9136 9137 #if defined(BCM_56624_B0) 9138 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_02_BCM56624_B0fmt */ 9139 /* format DESCRIPTOR_TX_02fmt */ 9140 /* nFields */ 1, 9141 /* *fields */ soc_DESCRIPTOR_TX_02fmt_fields, 9142 /* bits */ 32, 9143 /* flags */ 0, 9144 }, 9145 #endif /* chips */ 9146 9147 #if defined(BCM_56634_A0) 9148 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_02_BCM56634_A0fmt */ 9149 /* format DESCRIPTOR_TX_02fmt */ 9150 /* nFields */ 1, 9151 /* *fields */ soc_DESCRIPTOR_TX_02fmt_fields, 9152 /* bits */ 32, 9153 /* flags */ 0, 9154 }, 9155 #endif /* chips */ 9156 9157 #if defined(BCM_56634_B0) 9158 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_02_BCM56634_B0fmt */ 9159 /* format DESCRIPTOR_TX_02fmt */ 9160 /* nFields */ 1, 9161 /* *fields */ soc_DESCRIPTOR_TX_02fmt_fields, 9162 /* bits */ 32, 9163 /* flags */ 0, 9164 }, 9165 #endif /* chips */ 9166 9167 #if defined(BCM_56640_A0) 9168 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_02_BCM56640_A0fmt */ 9169 /* format DESCRIPTOR_TX_02fmt */ 9170 /* nFields */ 1, 9171 /* *fields */ soc_DESCRIPTOR_TX_02_BCM56640_A0fmt_fields, 9172 /* bits */ 32, 9173 /* flags */ 0, 9174 }, 9175 #endif /* chips */ 9176 9177 #if defined(BCM_56670_A0) 9178 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_02_BCM56670_A0fmt */ 9179 /* format DESCRIPTOR_TX_02fmt */ 9180 /* nFields */ 1, 9181 /* *fields */ soc_DESCRIPTOR_TX_02_BCM53400_A0fmt_fields, 9182 /* bits */ 32, 9183 /* flags */ 0, 9184 }, 9185 #endif /* chips */ 9186 9187 #if defined(BCM_56670_B0) 9188 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_02_BCM56670_B0fmt */ 9189 /* format DESCRIPTOR_TX_02fmt */ 9190 /* nFields */ 1, 9191 /* *fields */ soc_DESCRIPTOR_TX_02_BCM53400_A0fmt_fields, 9192 /* bits */ 32, 9193 /* flags */ 0, 9194 }, 9195 #endif /* chips */ 9196 9197 #if defined(BCM_56680_A0) 9198 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_02_BCM56680_A0fmt */ 9199 /* format DESCRIPTOR_TX_02fmt */ 9200 /* nFields */ 1, 9201 /* *fields */ soc_DESCRIPTOR_TX_02fmt_fields, 9202 /* bits */ 32, 9203 /* flags */ 0, 9204 }, 9205 #endif /* chips */ 9206 9207 #if defined(BCM_56680_B0) 9208 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_02_BCM56680_B0fmt */ 9209 /* format DESCRIPTOR_TX_02fmt */ 9210 /* nFields */ 1, 9211 /* *fields */ soc_DESCRIPTOR_TX_02fmt_fields, 9212 /* bits */ 32, 9213 /* flags */ 0, 9214 }, 9215 #endif /* chips */ 9216 9217 #if defined(BCM_56685_A0) 9218 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_02_BCM56685_A0fmt */ 9219 /* format DESCRIPTOR_TX_02fmt */ 9220 /* nFields */ 1, 9221 /* *fields */ soc_DESCRIPTOR_TX_02fmt_fields, 9222 /* bits */ 32, 9223 /* flags */ 0, 9224 }, 9225 #endif /* chips */ 9226 9227 #if defined(BCM_56685_B0) 9228 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_02_BCM56685_B0fmt */ 9229 /* format DESCRIPTOR_TX_02fmt */ 9230 /* nFields */ 1, 9231 /* *fields */ soc_DESCRIPTOR_TX_02fmt_fields, 9232 /* bits */ 32, 9233 /* flags */ 0, 9234 }, 9235 #endif /* chips */ 9236 9237 #if defined(BCM_56725_A0) 9238 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_02_BCM56725_A0fmt */ 9239 /* format DESCRIPTOR_TX_02fmt */ 9240 /* nFields */ 1, 9241 /* *fields */ soc_DESCRIPTOR_TX_02fmt_fields, 9242 /* bits */ 32, 9243 /* flags */ 0, 9244 }, 9245 #endif /* chips */ 9246 9247 #if defined(BCM_56770_A0) 9248 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_02_BCM56770_A0fmt */ 9249 /* format DESCRIPTOR_TX_02fmt */ 9250 /* nFields */ 9, 9251 /* *fields */ soc_DESCRIPTOR_TX_02_BCM56870_A0fmt_fields, 9252 /* bits */ 30, 9253 /* flags */ 0, 9254 }, 9255 #endif /* chips */ 9256 9257 #if defined(BCM_56800_A0) 9258 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_02_BCM56800_A0fmt */ 9259 /* format DESCRIPTOR_TX_02fmt */ 9260 /* nFields */ 1, 9261 /* *fields */ soc_DESCRIPTOR_TX_02fmt_fields, 9262 /* bits */ 32, 9263 /* flags */ 0, 9264 }, 9265 #endif /* chips */ 9266 9267 #if defined(BCM_56820_A0) 9268 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_02_BCM56820_A0fmt */ 9269 /* format DESCRIPTOR_TX_02fmt */ 9270 /* nFields */ 1, 9271 /* *fields */ soc_DESCRIPTOR_TX_02fmt_fields, 9272 /* bits */ 32, 9273 /* flags */ 0, 9274 }, 9275 #endif /* chips */ 9276 9277 #if defined(BCM_56840_A0) 9278 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_02_BCM56840_A0fmt */ 9279 /* format DESCRIPTOR_TX_02fmt */ 9280 /* nFields */ 1, 9281 /* *fields */ soc_DESCRIPTOR_TX_02fmt_fields, 9282 /* bits */ 32, 9283 /* flags */ 0, 9284 }, 9285 #endif /* chips */ 9286 9287 #if defined(BCM_56840_B0) 9288 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_02_BCM56840_B0fmt */ 9289 /* format DESCRIPTOR_TX_02fmt */ 9290 /* nFields */ 1, 9291 /* *fields */ soc_DESCRIPTOR_TX_02fmt_fields, 9292 /* bits */ 32, 9293 /* flags */ 0, 9294 }, 9295 #endif /* chips */ 9296 9297 #if defined(BCM_56850_A0) 9298 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_02_BCM56850_A0fmt */ 9299 /* format DESCRIPTOR_TX_02fmt */ 9300 /* nFields */ 1, 9301 /* *fields */ soc_DESCRIPTOR_TX_02_BCM56640_A0fmt_fields, 9302 /* bits */ 32, 9303 /* flags */ 0, 9304 }, 9305 #endif /* chips */ 9306 9307 #if defined(BCM_56860_A0) 9308 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_02_BCM56860_A0fmt */ 9309 /* format DESCRIPTOR_TX_02fmt */ 9310 /* nFields */ 1, 9311 /* *fields */ soc_DESCRIPTOR_TX_02_BCM56640_A0fmt_fields, 9312 /* bits */ 32, 9313 /* flags */ 0, 9314 }, 9315 #endif /* chips */ 9316 9317 #if defined(BCM_56870_A0) 9318 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_02_BCM56870_A0fmt */ 9319 /* format DESCRIPTOR_TX_02fmt */ 9320 /* nFields */ 9, 9321 /* *fields */ soc_DESCRIPTOR_TX_02_BCM56870_A0fmt_fields, 9322 /* bits */ 30, 9323 /* flags */ 0, 9324 }, 9325 #endif /* chips */ 9326 9327 #if defined(BCM_56960_A0) 9328 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_02_BCM56960_A0fmt */ 9329 /* format DESCRIPTOR_TX_02fmt */ 9330 /* nFields */ 1, 9331 /* *fields */ soc_DESCRIPTOR_TX_02_BCM53400_A0fmt_fields, 9332 /* bits */ 32, 9333 /* flags */ 0, 9334 }, 9335 #endif /* chips */ 9336 9337 #if defined(BCM_56965_A0) 9338 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_02_BCM56965_A0fmt */ 9339 /* format DESCRIPTOR_TX_02fmt */ 9340 /* nFields */ 1, 9341 /* *fields */ soc_DESCRIPTOR_TX_02_BCM53400_A0fmt_fields, 9342 /* bits */ 32, 9343 /* flags */ 0, 9344 }, 9345 #endif /* chips */ 9346 9347 #if defined(BCM_56970_A0) 9348 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_02_BCM56970_A0fmt */ 9349 /* format DESCRIPTOR_TX_02fmt */ 9350 /* nFields */ 1, 9351 /* *fields */ soc_DESCRIPTOR_TX_02_BCM53400_A0fmt_fields, 9352 /* bits */ 32, 9353 /* flags */ 0, 9354 }, 9355 #endif /* chips */ 9356 9357 #if defined(BCM_56980_A0) 9358 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_02_BCM56980_A0fmt */ 9359 /* format DESCRIPTOR_TX_02fmt */ 9360 /* nFields */ 9, 9361 /* *fields */ soc_DESCRIPTOR_TX_02_BCM56870_A0fmt_fields, 9362 /* bits */ 30, 9363 /* flags */ 0, 9364 }, 9365 #endif /* chips */ 9366 9367 #if defined(BCM_56980_B0) 9368 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_02_BCM56980_B0fmt */ 9369 /* format DESCRIPTOR_TX_02fmt */ 9370 /* nFields */ 9, 9371 /* *fields */ soc_DESCRIPTOR_TX_02_BCM56870_A0fmt_fields, 9372 /* bits */ 30, 9373 /* flags */ 0, 9374 }, 9375 #endif /* chips */ 9376 9377 #if defined(BCM_88732_A0) 9378 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_02_BCM88732_A0fmt */ 9379 /* format DESCRIPTOR_TX_02fmt */ 9380 /* nFields */ 1, 9381 /* *fields */ soc_DESCRIPTOR_TX_02fmt_fields, 9382 /* bits */ 32, 9383 /* flags */ 0, 9384 }, 9385 #endif /* chips */ 9386 9387 #if defined(BCM_53314_A0) 9388 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_03_BCM53314_A0fmt */ 9389 /* format DESCRIPTOR_TX_03fmt */ 9390 /* nFields */ 1, 9391 /* *fields */ soc_DESCRIPTOR_TX_03fmt_fields, 9392 /* bits */ 32, 9393 /* flags */ 0, 9394 }, 9395 #endif /* chips */ 9396 9397 #if defined(BCM_53324_A0) 9398 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_03_BCM53324_A0fmt */ 9399 /* format DESCRIPTOR_TX_03fmt */ 9400 /* nFields */ 1, 9401 /* *fields */ soc_DESCRIPTOR_TX_03fmt_fields, 9402 /* bits */ 32, 9403 /* flags */ 0, 9404 }, 9405 #endif /* chips */ 9406 9407 #if defined(BCM_53400_A0) 9408 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_03_BCM53400_A0fmt */ 9409 /* format DESCRIPTOR_TX_03fmt */ 9410 /* nFields */ 1, 9411 /* *fields */ soc_DESCRIPTOR_TX_03_BCM53400_A0fmt_fields, 9412 /* bits */ 32, 9413 /* flags */ 0, 9414 }, 9415 #endif /* chips */ 9416 9417 #if defined(BCM_53540_A0) 9418 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_03_BCM53540_A0fmt */ 9419 /* format DESCRIPTOR_TX_03fmt */ 9420 /* nFields */ 1, 9421 /* *fields */ soc_DESCRIPTOR_TX_03_BCM53400_A0fmt_fields, 9422 /* bits */ 32, 9423 /* flags */ 0, 9424 }, 9425 #endif /* chips */ 9426 9427 #if defined(BCM_53570_A0) 9428 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_03_BCM53570_A0fmt */ 9429 /* format DESCRIPTOR_TX_03fmt */ 9430 /* nFields */ 1, 9431 /* *fields */ soc_DESCRIPTOR_TX_03_BCM53400_A0fmt_fields, 9432 /* bits */ 32, 9433 /* flags */ 0, 9434 }, 9435 #endif /* chips */ 9436 9437 #if defined(BCM_53570_B0) 9438 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_03_BCM53570_B0fmt */ 9439 /* format DESCRIPTOR_TX_03fmt */ 9440 /* nFields */ 1, 9441 /* *fields */ soc_DESCRIPTOR_TX_03_BCM53400_A0fmt_fields, 9442 /* bits */ 32, 9443 /* flags */ 0, 9444 }, 9445 #endif /* chips */ 9446 9447 #if defined(BCM_56142_A0) 9448 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_03_BCM56142_A0fmt */ 9449 /* format DESCRIPTOR_TX_03fmt */ 9450 /* nFields */ 1, 9451 /* *fields */ soc_DESCRIPTOR_TX_03fmt_fields, 9452 /* bits */ 32, 9453 /* flags */ 0, 9454 }, 9455 #endif /* chips */ 9456 9457 #if defined(BCM_56150_A0) 9458 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_03_BCM56150_A0fmt */ 9459 /* format DESCRIPTOR_TX_03fmt */ 9460 /* nFields */ 1, 9461 /* *fields */ soc_DESCRIPTOR_TX_03_BCM56640_A0fmt_fields, 9462 /* bits */ 32, 9463 /* flags */ 0, 9464 }, 9465 #endif /* chips */ 9466 9467 #if defined(BCM_56160_A0) 9468 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_03_BCM56160_A0fmt */ 9469 /* format DESCRIPTOR_TX_03fmt */ 9470 /* nFields */ 1, 9471 /* *fields */ soc_DESCRIPTOR_TX_03_BCM53400_A0fmt_fields, 9472 /* bits */ 32, 9473 /* flags */ 0, 9474 }, 9475 #endif /* chips */ 9476 9477 #if defined(BCM_56224_A0) 9478 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_03_BCM56224_A0fmt */ 9479 /* format DESCRIPTOR_TX_03fmt */ 9480 /* nFields */ 1, 9481 /* *fields */ soc_DESCRIPTOR_TX_03fmt_fields, 9482 /* bits */ 32, 9483 /* flags */ 0, 9484 }, 9485 #endif /* chips */ 9486 9487 #if defined(BCM_56224_B0) 9488 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_03_BCM56224_B0fmt */ 9489 /* format DESCRIPTOR_TX_03fmt */ 9490 /* nFields */ 1, 9491 /* *fields */ soc_DESCRIPTOR_TX_03fmt_fields, 9492 /* bits */ 32, 9493 /* flags */ 0, 9494 }, 9495 #endif /* chips */ 9496 9497 #if defined(BCM_56260_A0) 9498 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_03_BCM56260_A0fmt */ 9499 /* format DESCRIPTOR_TX_03fmt */ 9500 /* nFields */ 1, 9501 /* *fields */ soc_DESCRIPTOR_TX_03_BCM53400_A0fmt_fields, 9502 /* bits */ 32, 9503 /* flags */ 0, 9504 }, 9505 #endif /* chips */ 9506 9507 #if defined(BCM_56260_B0) 9508 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_03_BCM56260_B0fmt */ 9509 /* format DESCRIPTOR_TX_03fmt */ 9510 /* nFields */ 1, 9511 /* *fields */ soc_DESCRIPTOR_TX_03_BCM53400_A0fmt_fields, 9512 /* bits */ 32, 9513 /* flags */ 0, 9514 }, 9515 #endif /* chips */ 9516 9517 #if defined(BCM_56270_A0) 9518 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_03_BCM56270_A0fmt */ 9519 /* format DESCRIPTOR_TX_03fmt */ 9520 /* nFields */ 1, 9521 /* *fields */ soc_DESCRIPTOR_TX_03_BCM53400_A0fmt_fields, 9522 /* bits */ 32, 9523 /* flags */ 0, 9524 }, 9525 #endif /* chips */ 9526 9527 #if defined(BCM_56314_A0) 9528 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_03_BCM56314_A0fmt */ 9529 /* format DESCRIPTOR_TX_03fmt */ 9530 /* nFields */ 1, 9531 /* *fields */ soc_DESCRIPTOR_RX_03fmt_fields, 9532 /* bits */ 32, 9533 /* flags */ 0, 9534 }, 9535 #endif /* chips */ 9536 9537 #if defined(BCM_56334_A0) 9538 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_03_BCM56334_A0fmt */ 9539 /* format DESCRIPTOR_TX_03fmt */ 9540 /* nFields */ 1, 9541 /* *fields */ soc_DESCRIPTOR_TX_03fmt_fields, 9542 /* bits */ 32, 9543 /* flags */ 0, 9544 }, 9545 #endif /* chips */ 9546 9547 #if defined(BCM_56334_B0) 9548 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_03_BCM56334_B0fmt */ 9549 /* format DESCRIPTOR_TX_03fmt */ 9550 /* nFields */ 1, 9551 /* *fields */ soc_DESCRIPTOR_TX_03fmt_fields, 9552 /* bits */ 32, 9553 /* flags */ 0, 9554 }, 9555 #endif /* chips */ 9556 9557 #if defined(BCM_56340_A0) 9558 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_03_BCM56340_A0fmt */ 9559 /* format DESCRIPTOR_TX_03fmt */ 9560 /* nFields */ 1, 9561 /* *fields */ soc_DESCRIPTOR_TX_03_BCM56640_A0fmt_fields, 9562 /* bits */ 32, 9563 /* flags */ 0, 9564 }, 9565 #endif /* chips */ 9566 9567 #if defined(BCM_56370_A0) 9568 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_03_BCM56370_A0fmt */ 9569 /* format DESCRIPTOR_TX_03fmt */ 9570 /* nFields */ 2, 9571 /* *fields */ soc_DESCRIPTOR_TX_03_BCM56870_A0fmt_fields, 9572 /* bits */ 32, 9573 /* flags */ 0, 9574 }, 9575 #endif /* chips */ 9576 9577 #if defined(BCM_56440_A0) 9578 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_03_BCM56440_A0fmt */ 9579 /* format DESCRIPTOR_TX_03fmt */ 9580 /* nFields */ 1, 9581 /* *fields */ soc_DESCRIPTOR_TX_03fmt_fields, 9582 /* bits */ 32, 9583 /* flags */ 0, 9584 }, 9585 #endif /* chips */ 9586 9587 #if defined(BCM_56440_B0) 9588 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_03_BCM56440_B0fmt */ 9589 /* format DESCRIPTOR_TX_03fmt */ 9590 /* nFields */ 1, 9591 /* *fields */ soc_DESCRIPTOR_TX_03fmt_fields, 9592 /* bits */ 32, 9593 /* flags */ 0, 9594 }, 9595 #endif /* chips */ 9596 9597 #if defined(BCM_56450_A0) 9598 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_03_BCM56450_A0fmt */ 9599 /* format DESCRIPTOR_TX_03fmt */ 9600 /* nFields */ 1, 9601 /* *fields */ soc_DESCRIPTOR_TX_03_BCM56640_A0fmt_fields, 9602 /* bits */ 32, 9603 /* flags */ 0, 9604 }, 9605 #endif /* chips */ 9606 9607 #if defined(BCM_56450_B0) 9608 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_03_BCM56450_B0fmt */ 9609 /* format DESCRIPTOR_TX_03fmt */ 9610 /* nFields */ 1, 9611 /* *fields */ soc_DESCRIPTOR_TX_03_BCM56640_A0fmt_fields, 9612 /* bits */ 32, 9613 /* flags */ 0, 9614 }, 9615 #endif /* chips */ 9616 9617 #if defined(BCM_56450_B1) 9618 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_03_BCM56450_B1fmt */ 9619 /* format DESCRIPTOR_TX_03fmt */ 9620 /* nFields */ 1, 9621 /* *fields */ soc_DESCRIPTOR_TX_03_BCM56640_A0fmt_fields, 9622 /* bits */ 32, 9623 /* flags */ 0, 9624 }, 9625 #endif /* chips */ 9626 9627 #if defined(BCM_56504_B0) 9628 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_03_BCM56504_B0fmt */ 9629 /* format DESCRIPTOR_TX_03fmt */ 9630 /* nFields */ 1, 9631 /* *fields */ soc_DESCRIPTOR_RX_03fmt_fields, 9632 /* bits */ 32, 9633 /* flags */ 0, 9634 }, 9635 #endif /* chips */ 9636 9637 #if defined(BCM_56514_A0) 9638 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_03_BCM56514_A0fmt */ 9639 /* format DESCRIPTOR_TX_03fmt */ 9640 /* nFields */ 1, 9641 /* *fields */ soc_DESCRIPTOR_RX_03fmt_fields, 9642 /* bits */ 32, 9643 /* flags */ 0, 9644 }, 9645 #endif /* chips */ 9646 9647 #if defined(BCM_56524_A0) 9648 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_03_BCM56524_A0fmt */ 9649 /* format DESCRIPTOR_TX_03fmt */ 9650 /* nFields */ 1, 9651 /* *fields */ soc_DESCRIPTOR_TX_03fmt_fields, 9652 /* bits */ 32, 9653 /* flags */ 0, 9654 }, 9655 #endif /* chips */ 9656 9657 #if defined(BCM_56524_B0) 9658 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_03_BCM56524_B0fmt */ 9659 /* format DESCRIPTOR_TX_03fmt */ 9660 /* nFields */ 1, 9661 /* *fields */ soc_DESCRIPTOR_TX_03fmt_fields, 9662 /* bits */ 32, 9663 /* flags */ 0, 9664 }, 9665 #endif /* chips */ 9666 9667 #if defined(BCM_56560_A0) 9668 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_03_BCM56560_A0fmt */ 9669 /* format DESCRIPTOR_TX_03fmt */ 9670 /* nFields */ 1, 9671 /* *fields */ soc_DESCRIPTOR_TX_03_BCM53400_A0fmt_fields, 9672 /* bits */ 32, 9673 /* flags */ 0, 9674 }, 9675 #endif /* chips */ 9676 9677 #if defined(BCM_56560_B0) 9678 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_03_BCM56560_B0fmt */ 9679 /* format DESCRIPTOR_TX_03fmt */ 9680 /* nFields */ 1, 9681 /* *fields */ soc_DESCRIPTOR_TX_03_BCM53400_A0fmt_fields, 9682 /* bits */ 32, 9683 /* flags */ 0, 9684 }, 9685 #endif /* chips */ 9686 9687 #if defined(BCM_56624_A0) 9688 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_03_BCM56624_A0fmt */ 9689 /* format DESCRIPTOR_TX_03fmt */ 9690 /* nFields */ 1, 9691 /* *fields */ soc_DESCRIPTOR_TX_03fmt_fields, 9692 /* bits */ 32, 9693 /* flags */ 0, 9694 }, 9695 #endif /* chips */ 9696 9697 #if defined(BCM_56624_B0) 9698 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_03_BCM56624_B0fmt */ 9699 /* format DESCRIPTOR_TX_03fmt */ 9700 /* nFields */ 1, 9701 /* *fields */ soc_DESCRIPTOR_TX_03fmt_fields, 9702 /* bits */ 32, 9703 /* flags */ 0, 9704 }, 9705 #endif /* chips */ 9706 9707 #if defined(BCM_56634_A0) 9708 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_03_BCM56634_A0fmt */ 9709 /* format DESCRIPTOR_TX_03fmt */ 9710 /* nFields */ 1, 9711 /* *fields */ soc_DESCRIPTOR_TX_03fmt_fields, 9712 /* bits */ 32, 9713 /* flags */ 0, 9714 }, 9715 #endif /* chips */ 9716 9717 #if defined(BCM_56634_B0) 9718 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_03_BCM56634_B0fmt */ 9719 /* format DESCRIPTOR_TX_03fmt */ 9720 /* nFields */ 1, 9721 /* *fields */ soc_DESCRIPTOR_TX_03fmt_fields, 9722 /* bits */ 32, 9723 /* flags */ 0, 9724 }, 9725 #endif /* chips */ 9726 9727 #if defined(BCM_56640_A0) 9728 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_03_BCM56640_A0fmt */ 9729 /* format DESCRIPTOR_TX_03fmt */ 9730 /* nFields */ 1, 9731 /* *fields */ soc_DESCRIPTOR_TX_03_BCM56640_A0fmt_fields, 9732 /* bits */ 32, 9733 /* flags */ 0, 9734 }, 9735 #endif /* chips */ 9736 9737 #if defined(BCM_56670_A0) 9738 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_03_BCM56670_A0fmt */ 9739 /* format DESCRIPTOR_TX_03fmt */ 9740 /* nFields */ 1, 9741 /* *fields */ soc_DESCRIPTOR_TX_03_BCM53400_A0fmt_fields, 9742 /* bits */ 32, 9743 /* flags */ 0, 9744 }, 9745 #endif /* chips */ 9746 9747 #if defined(BCM_56670_B0) 9748 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_03_BCM56670_B0fmt */ 9749 /* format DESCRIPTOR_TX_03fmt */ 9750 /* nFields */ 1, 9751 /* *fields */ soc_DESCRIPTOR_TX_03_BCM53400_A0fmt_fields, 9752 /* bits */ 32, 9753 /* flags */ 0, 9754 }, 9755 #endif /* chips */ 9756 9757 #if defined(BCM_56680_A0) 9758 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_03_BCM56680_A0fmt */ 9759 /* format DESCRIPTOR_TX_03fmt */ 9760 /* nFields */ 1, 9761 /* *fields */ soc_DESCRIPTOR_TX_03fmt_fields, 9762 /* bits */ 32, 9763 /* flags */ 0, 9764 }, 9765 #endif /* chips */ 9766 9767 #if defined(BCM_56680_B0) 9768 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_03_BCM56680_B0fmt */ 9769 /* format DESCRIPTOR_TX_03fmt */ 9770 /* nFields */ 1, 9771 /* *fields */ soc_DESCRIPTOR_TX_03fmt_fields, 9772 /* bits */ 32, 9773 /* flags */ 0, 9774 }, 9775 #endif /* chips */ 9776 9777 #if defined(BCM_56685_A0) 9778 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_03_BCM56685_A0fmt */ 9779 /* format DESCRIPTOR_TX_03fmt */ 9780 /* nFields */ 1, 9781 /* *fields */ soc_DESCRIPTOR_TX_03fmt_fields, 9782 /* bits */ 32, 9783 /* flags */ 0, 9784 }, 9785 #endif /* chips */ 9786 9787 #if defined(BCM_56685_B0) 9788 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_03_BCM56685_B0fmt */ 9789 /* format DESCRIPTOR_TX_03fmt */ 9790 /* nFields */ 1, 9791 /* *fields */ soc_DESCRIPTOR_TX_03fmt_fields, 9792 /* bits */ 32, 9793 /* flags */ 0, 9794 }, 9795 #endif /* chips */ 9796 9797 #if defined(BCM_56725_A0) 9798 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_03_BCM56725_A0fmt */ 9799 /* format DESCRIPTOR_TX_03fmt */ 9800 /* nFields */ 1, 9801 /* *fields */ soc_DESCRIPTOR_TX_03fmt_fields, 9802 /* bits */ 32, 9803 /* flags */ 0, 9804 }, 9805 #endif /* chips */ 9806 9807 #if defined(BCM_56770_A0) 9808 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_03_BCM56770_A0fmt */ 9809 /* format DESCRIPTOR_TX_03fmt */ 9810 /* nFields */ 2, 9811 /* *fields */ soc_DESCRIPTOR_TX_03_BCM56870_A0fmt_fields, 9812 /* bits */ 32, 9813 /* flags */ 0, 9814 }, 9815 #endif /* chips */ 9816 9817 #if defined(BCM_56800_A0) 9818 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_03_BCM56800_A0fmt */ 9819 /* format DESCRIPTOR_TX_03fmt */ 9820 /* nFields */ 1, 9821 /* *fields */ soc_DESCRIPTOR_TX_03fmt_fields, 9822 /* bits */ 32, 9823 /* flags */ 0, 9824 }, 9825 #endif /* chips */ 9826 9827 #if defined(BCM_56820_A0) 9828 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_03_BCM56820_A0fmt */ 9829 /* format DESCRIPTOR_TX_03fmt */ 9830 /* nFields */ 1, 9831 /* *fields */ soc_DESCRIPTOR_TX_03fmt_fields, 9832 /* bits */ 32, 9833 /* flags */ 0, 9834 }, 9835 #endif /* chips */ 9836 9837 #if defined(BCM_56840_A0) 9838 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_03_BCM56840_A0fmt */ 9839 /* format DESCRIPTOR_TX_03fmt */ 9840 /* nFields */ 1, 9841 /* *fields */ soc_DESCRIPTOR_TX_03fmt_fields, 9842 /* bits */ 32, 9843 /* flags */ 0, 9844 }, 9845 #endif /* chips */ 9846 9847 #if defined(BCM_56840_B0) 9848 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_03_BCM56840_B0fmt */ 9849 /* format DESCRIPTOR_TX_03fmt */ 9850 /* nFields */ 1, 9851 /* *fields */ soc_DESCRIPTOR_TX_03fmt_fields, 9852 /* bits */ 32, 9853 /* flags */ 0, 9854 }, 9855 #endif /* chips */ 9856 9857 #if defined(BCM_56850_A0) 9858 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_03_BCM56850_A0fmt */ 9859 /* format DESCRIPTOR_TX_03fmt */ 9860 /* nFields */ 1, 9861 /* *fields */ soc_DESCRIPTOR_TX_03_BCM56640_A0fmt_fields, 9862 /* bits */ 32, 9863 /* flags */ 0, 9864 }, 9865 #endif /* chips */ 9866 9867 #if defined(BCM_56860_A0) 9868 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_03_BCM56860_A0fmt */ 9869 /* format DESCRIPTOR_TX_03fmt */ 9870 /* nFields */ 1, 9871 /* *fields */ soc_DESCRIPTOR_TX_03_BCM56640_A0fmt_fields, 9872 /* bits */ 32, 9873 /* flags */ 0, 9874 }, 9875 #endif /* chips */ 9876 9877 #if defined(BCM_56870_A0) 9878 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_03_BCM56870_A0fmt */ 9879 /* format DESCRIPTOR_TX_03fmt */ 9880 /* nFields */ 2, 9881 /* *fields */ soc_DESCRIPTOR_TX_03_BCM56870_A0fmt_fields, 9882 /* bits */ 32, 9883 /* flags */ 0, 9884 }, 9885 #endif /* chips */ 9886 9887 #if defined(BCM_56960_A0) 9888 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_03_BCM56960_A0fmt */ 9889 /* format DESCRIPTOR_TX_03fmt */ 9890 /* nFields */ 1, 9891 /* *fields */ soc_DESCRIPTOR_TX_03_BCM53400_A0fmt_fields, 9892 /* bits */ 32, 9893 /* flags */ 0, 9894 }, 9895 #endif /* chips */ 9896 9897 #if defined(BCM_56965_A0) 9898 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_03_BCM56965_A0fmt */ 9899 /* format DESCRIPTOR_TX_03fmt */ 9900 /* nFields */ 1, 9901 /* *fields */ soc_DESCRIPTOR_TX_03_BCM53400_A0fmt_fields, 9902 /* bits */ 32, 9903 /* flags */ 0, 9904 }, 9905 #endif /* chips */ 9906 9907 #if defined(BCM_56970_A0) 9908 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_03_BCM56970_A0fmt */ 9909 /* format DESCRIPTOR_TX_03fmt */ 9910 /* nFields */ 1, 9911 /* *fields */ soc_DESCRIPTOR_TX_03_BCM53400_A0fmt_fields, 9912 /* bits */ 32, 9913 /* flags */ 0, 9914 }, 9915 #endif /* chips */ 9916 9917 #if defined(BCM_56980_A0) 9918 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_03_BCM56980_A0fmt */ 9919 /* format DESCRIPTOR_TX_03fmt */ 9920 /* nFields */ 2, 9921 /* *fields */ soc_DESCRIPTOR_TX_03_BCM56870_A0fmt_fields, 9922 /* bits */ 32, 9923 /* flags */ 0, 9924 }, 9925 #endif /* chips */ 9926 9927 #if defined(BCM_56980_B0) 9928 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_03_BCM56980_B0fmt */ 9929 /* format DESCRIPTOR_TX_03fmt */ 9930 /* nFields */ 2, 9931 /* *fields */ soc_DESCRIPTOR_TX_03_BCM56870_A0fmt_fields, 9932 /* bits */ 32, 9933 /* flags */ 0, 9934 }, 9935 #endif /* chips */ 9936 9937 #if defined(BCM_88732_A0) 9938 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_03_BCM88732_A0fmt */ 9939 /* format DESCRIPTOR_TX_03fmt */ 9940 /* nFields */ 1, 9941 /* *fields */ soc_DESCRIPTOR_TX_03fmt_fields, 9942 /* bits */ 32, 9943 /* flags */ 0, 9944 }, 9945 #endif /* chips */ 9946 9947 #if defined(BCM_53314_A0) 9948 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_04_BCM53314_A0fmt */ 9949 /* format DESCRIPTOR_TX_04fmt */ 9950 /* nFields */ 1, 9951 /* *fields */ soc_DESCRIPTOR_TX_04fmt_fields, 9952 /* bits */ 32, 9953 /* flags */ 0, 9954 }, 9955 #endif /* chips */ 9956 9957 #if defined(BCM_53324_A0) 9958 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_04_BCM53324_A0fmt */ 9959 /* format DESCRIPTOR_TX_04fmt */ 9960 /* nFields */ 1, 9961 /* *fields */ soc_DESCRIPTOR_TX_04fmt_fields, 9962 /* bits */ 32, 9963 /* flags */ 0, 9964 }, 9965 #endif /* chips */ 9966 9967 #if defined(BCM_53400_A0) 9968 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_04_BCM53400_A0fmt */ 9969 /* format DESCRIPTOR_TX_04fmt */ 9970 /* nFields */ 1, 9971 /* *fields */ soc_DESCRIPTOR_TX_04_BCM53400_A0fmt_fields, 9972 /* bits */ 32, 9973 /* flags */ 0, 9974 }, 9975 #endif /* chips */ 9976 9977 #if defined(BCM_53540_A0) 9978 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_04_BCM53540_A0fmt */ 9979 /* format DESCRIPTOR_TX_04fmt */ 9980 /* nFields */ 1, 9981 /* *fields */ soc_DESCRIPTOR_TX_04_BCM53400_A0fmt_fields, 9982 /* bits */ 32, 9983 /* flags */ 0, 9984 }, 9985 #endif /* chips */ 9986 9987 #if defined(BCM_53570_A0) 9988 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_04_BCM53570_A0fmt */ 9989 /* format DESCRIPTOR_TX_04fmt */ 9990 /* nFields */ 1, 9991 /* *fields */ soc_DESCRIPTOR_TX_04_BCM53400_A0fmt_fields, 9992 /* bits */ 32, 9993 /* flags */ 0, 9994 }, 9995 #endif /* chips */ 9996 9997 #if defined(BCM_53570_B0) 9998 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_04_BCM53570_B0fmt */ 9999 /* format DESCRIPTOR_TX_04fmt */ 10000 /* nFields */ 1, 10001 /* *fields */ soc_DESCRIPTOR_TX_04_BCM53400_A0fmt_fields, 10002 /* bits */ 32, 10003 /* flags */ 0, 10004 }, 10005 #endif /* chips */ 10006 10007 #if defined(BCM_56142_A0) 10008 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_04_BCM56142_A0fmt */ 10009 /* format DESCRIPTOR_TX_04fmt */ 10010 /* nFields */ 1, 10011 /* *fields */ soc_DESCRIPTOR_TX_04fmt_fields, 10012 /* bits */ 32, 10013 /* flags */ 0, 10014 }, 10015 #endif /* chips */ 10016 10017 #if defined(BCM_56150_A0) 10018 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_04_BCM56150_A0fmt */ 10019 /* format DESCRIPTOR_TX_04fmt */ 10020 /* nFields */ 1, 10021 /* *fields */ soc_DESCRIPTOR_TX_04_BCM56640_A0fmt_fields, 10022 /* bits */ 32, 10023 /* flags */ 0, 10024 }, 10025 #endif /* chips */ 10026 10027 #if defined(BCM_56160_A0) 10028 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_04_BCM56160_A0fmt */ 10029 /* format DESCRIPTOR_TX_04fmt */ 10030 /* nFields */ 1, 10031 /* *fields */ soc_DESCRIPTOR_TX_04_BCM53400_A0fmt_fields, 10032 /* bits */ 32, 10033 /* flags */ 0, 10034 }, 10035 #endif /* chips */ 10036 10037 #if defined(BCM_56224_A0) 10038 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_04_BCM56224_A0fmt */ 10039 /* format DESCRIPTOR_TX_04fmt */ 10040 /* nFields */ 1, 10041 /* *fields */ soc_DESCRIPTOR_TX_04fmt_fields, 10042 /* bits */ 32, 10043 /* flags */ 0, 10044 }, 10045 #endif /* chips */ 10046 10047 #if defined(BCM_56224_B0) 10048 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_04_BCM56224_B0fmt */ 10049 /* format DESCRIPTOR_TX_04fmt */ 10050 /* nFields */ 1, 10051 /* *fields */ soc_DESCRIPTOR_TX_04fmt_fields, 10052 /* bits */ 32, 10053 /* flags */ 0, 10054 }, 10055 #endif /* chips */ 10056 10057 #if defined(BCM_56260_A0) 10058 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_04_BCM56260_A0fmt */ 10059 /* format DESCRIPTOR_TX_04fmt */ 10060 /* nFields */ 1, 10061 /* *fields */ soc_DESCRIPTOR_TX_04_BCM53400_A0fmt_fields, 10062 /* bits */ 32, 10063 /* flags */ 0, 10064 }, 10065 #endif /* chips */ 10066 10067 #if defined(BCM_56260_B0) 10068 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_04_BCM56260_B0fmt */ 10069 /* format DESCRIPTOR_TX_04fmt */ 10070 /* nFields */ 1, 10071 /* *fields */ soc_DESCRIPTOR_TX_04_BCM53400_A0fmt_fields, 10072 /* bits */ 32, 10073 /* flags */ 0, 10074 }, 10075 #endif /* chips */ 10076 10077 #if defined(BCM_56270_A0) 10078 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_04_BCM56270_A0fmt */ 10079 /* format DESCRIPTOR_TX_04fmt */ 10080 /* nFields */ 1, 10081 /* *fields */ soc_DESCRIPTOR_TX_04_BCM53400_A0fmt_fields, 10082 /* bits */ 32, 10083 /* flags */ 0, 10084 }, 10085 #endif /* chips */ 10086 10087 #if defined(BCM_56314_A0) 10088 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_04_BCM56314_A0fmt */ 10089 /* format DESCRIPTOR_TX_04fmt */ 10090 /* nFields */ 1, 10091 /* *fields */ soc_DESCRIPTOR_RX_04fmt_fields, 10092 /* bits */ 32, 10093 /* flags */ 0, 10094 }, 10095 #endif /* chips */ 10096 10097 #if defined(BCM_56334_A0) 10098 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_04_BCM56334_A0fmt */ 10099 /* format DESCRIPTOR_TX_04fmt */ 10100 /* nFields */ 1, 10101 /* *fields */ soc_DESCRIPTOR_TX_04fmt_fields, 10102 /* bits */ 32, 10103 /* flags */ 0, 10104 }, 10105 #endif /* chips */ 10106 10107 #if defined(BCM_56334_B0) 10108 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_04_BCM56334_B0fmt */ 10109 /* format DESCRIPTOR_TX_04fmt */ 10110 /* nFields */ 1, 10111 /* *fields */ soc_DESCRIPTOR_TX_04fmt_fields, 10112 /* bits */ 32, 10113 /* flags */ 0, 10114 }, 10115 #endif /* chips */ 10116 10117 #if defined(BCM_56340_A0) 10118 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_04_BCM56340_A0fmt */ 10119 /* format DESCRIPTOR_TX_04fmt */ 10120 /* nFields */ 1, 10121 /* *fields */ soc_DESCRIPTOR_TX_04_BCM56640_A0fmt_fields, 10122 /* bits */ 32, 10123 /* flags */ 0, 10124 }, 10125 #endif /* chips */ 10126 10127 #if defined(BCM_56440_A0) 10128 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_04_BCM56440_A0fmt */ 10129 /* format DESCRIPTOR_TX_04fmt */ 10130 /* nFields */ 1, 10131 /* *fields */ soc_DESCRIPTOR_TX_04fmt_fields, 10132 /* bits */ 32, 10133 /* flags */ 0, 10134 }, 10135 #endif /* chips */ 10136 10137 #if defined(BCM_56440_B0) 10138 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_04_BCM56440_B0fmt */ 10139 /* format DESCRIPTOR_TX_04fmt */ 10140 /* nFields */ 1, 10141 /* *fields */ soc_DESCRIPTOR_TX_04fmt_fields, 10142 /* bits */ 32, 10143 /* flags */ 0, 10144 }, 10145 #endif /* chips */ 10146 10147 #if defined(BCM_56450_A0) 10148 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_04_BCM56450_A0fmt */ 10149 /* format DESCRIPTOR_TX_04fmt */ 10150 /* nFields */ 1, 10151 /* *fields */ soc_DESCRIPTOR_TX_04_BCM56640_A0fmt_fields, 10152 /* bits */ 32, 10153 /* flags */ 0, 10154 }, 10155 #endif /* chips */ 10156 10157 #if defined(BCM_56450_B0) 10158 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_04_BCM56450_B0fmt */ 10159 /* format DESCRIPTOR_TX_04fmt */ 10160 /* nFields */ 1, 10161 /* *fields */ soc_DESCRIPTOR_TX_04_BCM56640_A0fmt_fields, 10162 /* bits */ 32, 10163 /* flags */ 0, 10164 }, 10165 #endif /* chips */ 10166 10167 #if defined(BCM_56450_B1) 10168 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_04_BCM56450_B1fmt */ 10169 /* format DESCRIPTOR_TX_04fmt */ 10170 /* nFields */ 1, 10171 /* *fields */ soc_DESCRIPTOR_TX_04_BCM56640_A0fmt_fields, 10172 /* bits */ 32, 10173 /* flags */ 0, 10174 }, 10175 #endif /* chips */ 10176 10177 #if defined(BCM_56504_B0) 10178 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_04_BCM56504_B0fmt */ 10179 /* format DESCRIPTOR_TX_04fmt */ 10180 /* nFields */ 1, 10181 /* *fields */ soc_DESCRIPTOR_RX_04fmt_fields, 10182 /* bits */ 32, 10183 /* flags */ 0, 10184 }, 10185 #endif /* chips */ 10186 10187 #if defined(BCM_56514_A0) 10188 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_04_BCM56514_A0fmt */ 10189 /* format DESCRIPTOR_TX_04fmt */ 10190 /* nFields */ 1, 10191 /* *fields */ soc_DESCRIPTOR_RX_04fmt_fields, 10192 /* bits */ 32, 10193 /* flags */ 0, 10194 }, 10195 #endif /* chips */ 10196 10197 #if defined(BCM_56524_A0) 10198 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_04_BCM56524_A0fmt */ 10199 /* format DESCRIPTOR_TX_04fmt */ 10200 /* nFields */ 1, 10201 /* *fields */ soc_DESCRIPTOR_TX_04fmt_fields, 10202 /* bits */ 32, 10203 /* flags */ 0, 10204 }, 10205 #endif /* chips */ 10206 10207 #if defined(BCM_56524_B0) 10208 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_04_BCM56524_B0fmt */ 10209 /* format DESCRIPTOR_TX_04fmt */ 10210 /* nFields */ 1, 10211 /* *fields */ soc_DESCRIPTOR_TX_04fmt_fields, 10212 /* bits */ 32, 10213 /* flags */ 0, 10214 }, 10215 #endif /* chips */ 10216 10217 #if defined(BCM_56560_A0) 10218 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_04_BCM56560_A0fmt */ 10219 /* format DESCRIPTOR_TX_04fmt */ 10220 /* nFields */ 1, 10221 /* *fields */ soc_DESCRIPTOR_TX_04_BCM53400_A0fmt_fields, 10222 /* bits */ 32, 10223 /* flags */ 0, 10224 }, 10225 #endif /* chips */ 10226 10227 #if defined(BCM_56560_B0) 10228 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_04_BCM56560_B0fmt */ 10229 /* format DESCRIPTOR_TX_04fmt */ 10230 /* nFields */ 1, 10231 /* *fields */ soc_DESCRIPTOR_TX_04_BCM53400_A0fmt_fields, 10232 /* bits */ 32, 10233 /* flags */ 0, 10234 }, 10235 #endif /* chips */ 10236 10237 #if defined(BCM_56624_A0) 10238 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_04_BCM56624_A0fmt */ 10239 /* format DESCRIPTOR_TX_04fmt */ 10240 /* nFields */ 1, 10241 /* *fields */ soc_DESCRIPTOR_TX_04fmt_fields, 10242 /* bits */ 32, 10243 /* flags */ 0, 10244 }, 10245 #endif /* chips */ 10246 10247 #if defined(BCM_56624_B0) 10248 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_04_BCM56624_B0fmt */ 10249 /* format DESCRIPTOR_TX_04fmt */ 10250 /* nFields */ 1, 10251 /* *fields */ soc_DESCRIPTOR_TX_04fmt_fields, 10252 /* bits */ 32, 10253 /* flags */ 0, 10254 }, 10255 #endif /* chips */ 10256 10257 #if defined(BCM_56634_A0) 10258 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_04_BCM56634_A0fmt */ 10259 /* format DESCRIPTOR_TX_04fmt */ 10260 /* nFields */ 1, 10261 /* *fields */ soc_DESCRIPTOR_TX_04fmt_fields, 10262 /* bits */ 32, 10263 /* flags */ 0, 10264 }, 10265 #endif /* chips */ 10266 10267 #if defined(BCM_56634_B0) 10268 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_04_BCM56634_B0fmt */ 10269 /* format DESCRIPTOR_TX_04fmt */ 10270 /* nFields */ 1, 10271 /* *fields */ soc_DESCRIPTOR_TX_04fmt_fields, 10272 /* bits */ 32, 10273 /* flags */ 0, 10274 }, 10275 #endif /* chips */ 10276 10277 #if defined(BCM_56640_A0) 10278 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_04_BCM56640_A0fmt */ 10279 /* format DESCRIPTOR_TX_04fmt */ 10280 /* nFields */ 1, 10281 /* *fields */ soc_DESCRIPTOR_TX_04_BCM56640_A0fmt_fields, 10282 /* bits */ 32, 10283 /* flags */ 0, 10284 }, 10285 #endif /* chips */ 10286 10287 #if defined(BCM_56670_A0) 10288 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_04_BCM56670_A0fmt */ 10289 /* format DESCRIPTOR_TX_04fmt */ 10290 /* nFields */ 1, 10291 /* *fields */ soc_DESCRIPTOR_TX_04_BCM53400_A0fmt_fields, 10292 /* bits */ 32, 10293 /* flags */ 0, 10294 }, 10295 #endif /* chips */ 10296 10297 #if defined(BCM_56670_B0) 10298 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_04_BCM56670_B0fmt */ 10299 /* format DESCRIPTOR_TX_04fmt */ 10300 /* nFields */ 1, 10301 /* *fields */ soc_DESCRIPTOR_TX_04_BCM53400_A0fmt_fields, 10302 /* bits */ 32, 10303 /* flags */ 0, 10304 }, 10305 #endif /* chips */ 10306 10307 #if defined(BCM_56680_A0) 10308 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_04_BCM56680_A0fmt */ 10309 /* format DESCRIPTOR_TX_04fmt */ 10310 /* nFields */ 1, 10311 /* *fields */ soc_DESCRIPTOR_TX_04fmt_fields, 10312 /* bits */ 32, 10313 /* flags */ 0, 10314 }, 10315 #endif /* chips */ 10316 10317 #if defined(BCM_56680_B0) 10318 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_04_BCM56680_B0fmt */ 10319 /* format DESCRIPTOR_TX_04fmt */ 10320 /* nFields */ 1, 10321 /* *fields */ soc_DESCRIPTOR_TX_04fmt_fields, 10322 /* bits */ 32, 10323 /* flags */ 0, 10324 }, 10325 #endif /* chips */ 10326 10327 #if defined(BCM_56685_A0) 10328 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_04_BCM56685_A0fmt */ 10329 /* format DESCRIPTOR_TX_04fmt */ 10330 /* nFields */ 1, 10331 /* *fields */ soc_DESCRIPTOR_TX_04fmt_fields, 10332 /* bits */ 32, 10333 /* flags */ 0, 10334 }, 10335 #endif /* chips */ 10336 10337 #if defined(BCM_56685_B0) 10338 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_04_BCM56685_B0fmt */ 10339 /* format DESCRIPTOR_TX_04fmt */ 10340 /* nFields */ 1, 10341 /* *fields */ soc_DESCRIPTOR_TX_04fmt_fields, 10342 /* bits */ 32, 10343 /* flags */ 0, 10344 }, 10345 #endif /* chips */ 10346 10347 #if defined(BCM_56725_A0) 10348 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_04_BCM56725_A0fmt */ 10349 /* format DESCRIPTOR_TX_04fmt */ 10350 /* nFields */ 1, 10351 /* *fields */ soc_DESCRIPTOR_TX_04fmt_fields, 10352 /* bits */ 32, 10353 /* flags */ 0, 10354 }, 10355 #endif /* chips */ 10356 10357 #if defined(BCM_56800_A0) 10358 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_04_BCM56800_A0fmt */ 10359 /* format DESCRIPTOR_TX_04fmt */ 10360 /* nFields */ 1, 10361 /* *fields */ soc_DESCRIPTOR_TX_04fmt_fields, 10362 /* bits */ 32, 10363 /* flags */ 0, 10364 }, 10365 #endif /* chips */ 10366 10367 #if defined(BCM_56820_A0) 10368 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_04_BCM56820_A0fmt */ 10369 /* format DESCRIPTOR_TX_04fmt */ 10370 /* nFields */ 1, 10371 /* *fields */ soc_DESCRIPTOR_TX_04fmt_fields, 10372 /* bits */ 32, 10373 /* flags */ 0, 10374 }, 10375 #endif /* chips */ 10376 10377 #if defined(BCM_56840_A0) 10378 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_04_BCM56840_A0fmt */ 10379 /* format DESCRIPTOR_TX_04fmt */ 10380 /* nFields */ 1, 10381 /* *fields */ soc_DESCRIPTOR_TX_04fmt_fields, 10382 /* bits */ 32, 10383 /* flags */ 0, 10384 }, 10385 #endif /* chips */ 10386 10387 #if defined(BCM_56840_B0) 10388 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_04_BCM56840_B0fmt */ 10389 /* format DESCRIPTOR_TX_04fmt */ 10390 /* nFields */ 1, 10391 /* *fields */ soc_DESCRIPTOR_TX_04fmt_fields, 10392 /* bits */ 32, 10393 /* flags */ 0, 10394 }, 10395 #endif /* chips */ 10396 10397 #if defined(BCM_56850_A0) 10398 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_04_BCM56850_A0fmt */ 10399 /* format DESCRIPTOR_TX_04fmt */ 10400 /* nFields */ 1, 10401 /* *fields */ soc_DESCRIPTOR_TX_04_BCM56640_A0fmt_fields, 10402 /* bits */ 32, 10403 /* flags */ 0, 10404 }, 10405 #endif /* chips */ 10406 10407 #if defined(BCM_56860_A0) 10408 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_04_BCM56860_A0fmt */ 10409 /* format DESCRIPTOR_TX_04fmt */ 10410 /* nFields */ 1, 10411 /* *fields */ soc_DESCRIPTOR_TX_04_BCM56640_A0fmt_fields, 10412 /* bits */ 32, 10413 /* flags */ 0, 10414 }, 10415 #endif /* chips */ 10416 10417 #if defined(BCM_56960_A0) 10418 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_04_BCM56960_A0fmt */ 10419 /* format DESCRIPTOR_TX_04fmt */ 10420 /* nFields */ 1, 10421 /* *fields */ soc_DESCRIPTOR_TX_04_BCM53400_A0fmt_fields, 10422 /* bits */ 32, 10423 /* flags */ 0, 10424 }, 10425 #endif /* chips */ 10426 10427 #if defined(BCM_56965_A0) 10428 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_04_BCM56965_A0fmt */ 10429 /* format DESCRIPTOR_TX_04fmt */ 10430 /* nFields */ 1, 10431 /* *fields */ soc_DESCRIPTOR_TX_04_BCM53400_A0fmt_fields, 10432 /* bits */ 32, 10433 /* flags */ 0, 10434 }, 10435 #endif /* chips */ 10436 10437 #if defined(BCM_56970_A0) 10438 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_04_BCM56970_A0fmt */ 10439 /* format DESCRIPTOR_TX_04fmt */ 10440 /* nFields */ 1, 10441 /* *fields */ soc_DESCRIPTOR_TX_04_BCM53400_A0fmt_fields, 10442 /* bits */ 32, 10443 /* flags */ 0, 10444 }, 10445 #endif /* chips */ 10446 10447 #if defined(BCM_88732_A0) 10448 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_04_BCM88732_A0fmt */ 10449 /* format DESCRIPTOR_TX_04fmt */ 10450 /* nFields */ 1, 10451 /* *fields */ soc_DESCRIPTOR_TX_04fmt_fields, 10452 /* bits */ 32, 10453 /* flags */ 0, 10454 }, 10455 #endif /* chips */ 10456 10457 #if defined(BCM_53314_A0) 10458 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_05_BCM53314_A0fmt */ 10459 /* format DESCRIPTOR_TX_05fmt */ 10460 /* nFields */ 1, 10461 /* *fields */ soc_DESCRIPTOR_TX_05_BCM56800_A0fmt_fields, 10462 /* bits */ 32, 10463 /* flags */ 0, 10464 }, 10465 #endif /* chips */ 10466 10467 #if defined(BCM_53324_A0) 10468 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_05_BCM53324_A0fmt */ 10469 /* format DESCRIPTOR_TX_05fmt */ 10470 /* nFields */ 1, 10471 /* *fields */ soc_DESCRIPTOR_TX_05_BCM56800_A0fmt_fields, 10472 /* bits */ 32, 10473 /* flags */ 0, 10474 }, 10475 #endif /* chips */ 10476 10477 #if defined(BCM_53400_A0) 10478 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_05_BCM53400_A0fmt */ 10479 /* format DESCRIPTOR_TX_05fmt */ 10480 /* nFields */ 1, 10481 /* *fields */ soc_DESCRIPTOR_TX_05_BCM53400_A0fmt_fields, 10482 /* bits */ 32, 10483 /* flags */ 0, 10484 }, 10485 #endif /* chips */ 10486 10487 #if defined(BCM_53540_A0) 10488 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_05_BCM53540_A0fmt */ 10489 /* format DESCRIPTOR_TX_05fmt */ 10490 /* nFields */ 1, 10491 /* *fields */ soc_DESCRIPTOR_TX_05_BCM53400_A0fmt_fields, 10492 /* bits */ 32, 10493 /* flags */ 0, 10494 }, 10495 #endif /* chips */ 10496 10497 #if defined(BCM_53570_A0) 10498 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_05_BCM53570_A0fmt */ 10499 /* format DESCRIPTOR_TX_05fmt */ 10500 /* nFields */ 1, 10501 /* *fields */ soc_DESCRIPTOR_TX_05_BCM53400_A0fmt_fields, 10502 /* bits */ 32, 10503 /* flags */ 0, 10504 }, 10505 #endif /* chips */ 10506 10507 #if defined(BCM_53570_B0) 10508 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_05_BCM53570_B0fmt */ 10509 /* format DESCRIPTOR_TX_05fmt */ 10510 /* nFields */ 1, 10511 /* *fields */ soc_DESCRIPTOR_TX_05_BCM53400_A0fmt_fields, 10512 /* bits */ 32, 10513 /* flags */ 0, 10514 }, 10515 #endif /* chips */ 10516 10517 #if defined(BCM_56142_A0) 10518 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_05_BCM56142_A0fmt */ 10519 /* format DESCRIPTOR_TX_05fmt */ 10520 /* nFields */ 1, 10521 /* *fields */ soc_DESCRIPTOR_TX_05_BCM56800_A0fmt_fields, 10522 /* bits */ 32, 10523 /* flags */ 0, 10524 }, 10525 #endif /* chips */ 10526 10527 #if defined(BCM_56150_A0) 10528 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_05_BCM56150_A0fmt */ 10529 /* format DESCRIPTOR_TX_05fmt */ 10530 /* nFields */ 1, 10531 /* *fields */ soc_DESCRIPTOR_TX_05_BCM56640_A0fmt_fields, 10532 /* bits */ 32, 10533 /* flags */ 0, 10534 }, 10535 #endif /* chips */ 10536 10537 #if defined(BCM_56160_A0) 10538 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_05_BCM56160_A0fmt */ 10539 /* format DESCRIPTOR_TX_05fmt */ 10540 /* nFields */ 1, 10541 /* *fields */ soc_DESCRIPTOR_TX_05_BCM53400_A0fmt_fields, 10542 /* bits */ 32, 10543 /* flags */ 0, 10544 }, 10545 #endif /* chips */ 10546 10547 #if defined(BCM_56224_A0) 10548 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_05_BCM56224_A0fmt */ 10549 /* format DESCRIPTOR_TX_05fmt */ 10550 /* nFields */ 1, 10551 /* *fields */ soc_DESCRIPTOR_TX_05_BCM56800_A0fmt_fields, 10552 /* bits */ 32, 10553 /* flags */ 0, 10554 }, 10555 #endif /* chips */ 10556 10557 #if defined(BCM_56224_B0) 10558 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_05_BCM56224_B0fmt */ 10559 /* format DESCRIPTOR_TX_05fmt */ 10560 /* nFields */ 1, 10561 /* *fields */ soc_DESCRIPTOR_TX_05_BCM56800_A0fmt_fields, 10562 /* bits */ 32, 10563 /* flags */ 0, 10564 }, 10565 #endif /* chips */ 10566 10567 #if defined(BCM_56260_A0) 10568 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_05_BCM56260_A0fmt */ 10569 /* format DESCRIPTOR_TX_05fmt */ 10570 /* nFields */ 1, 10571 /* *fields */ soc_DESCRIPTOR_TX_05_BCM53400_A0fmt_fields, 10572 /* bits */ 32, 10573 /* flags */ 0, 10574 }, 10575 #endif /* chips */ 10576 10577 #if defined(BCM_56260_B0) 10578 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_05_BCM56260_B0fmt */ 10579 /* format DESCRIPTOR_TX_05fmt */ 10580 /* nFields */ 1, 10581 /* *fields */ soc_DESCRIPTOR_TX_05_BCM53400_A0fmt_fields, 10582 /* bits */ 32, 10583 /* flags */ 0, 10584 }, 10585 #endif /* chips */ 10586 10587 #if defined(BCM_56270_A0) 10588 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_05_BCM56270_A0fmt */ 10589 /* format DESCRIPTOR_TX_05fmt */ 10590 /* nFields */ 1, 10591 /* *fields */ soc_DESCRIPTOR_TX_05_BCM53400_A0fmt_fields, 10592 /* bits */ 32, 10593 /* flags */ 0, 10594 }, 10595 #endif /* chips */ 10596 10597 #if defined(BCM_56334_A0) 10598 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_05_BCM56334_A0fmt */ 10599 /* format DESCRIPTOR_TX_05fmt */ 10600 /* nFields */ 1, 10601 /* *fields */ soc_DESCRIPTOR_TX_05_BCM56800_A0fmt_fields, 10602 /* bits */ 32, 10603 /* flags */ 0, 10604 }, 10605 #endif /* chips */ 10606 10607 #if defined(BCM_56334_B0) 10608 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_05_BCM56334_B0fmt */ 10609 /* format DESCRIPTOR_TX_05fmt */ 10610 /* nFields */ 1, 10611 /* *fields */ soc_DESCRIPTOR_TX_05_BCM56800_A0fmt_fields, 10612 /* bits */ 32, 10613 /* flags */ 0, 10614 }, 10615 #endif /* chips */ 10616 10617 #if defined(BCM_56340_A0) 10618 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_05_BCM56340_A0fmt */ 10619 /* format DESCRIPTOR_TX_05fmt */ 10620 /* nFields */ 1, 10621 /* *fields */ soc_DESCRIPTOR_TX_05_BCM56640_A0fmt_fields, 10622 /* bits */ 32, 10623 /* flags */ 0, 10624 }, 10625 #endif /* chips */ 10626 10627 #if defined(BCM_56440_A0) 10628 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_05_BCM56440_A0fmt */ 10629 /* format DESCRIPTOR_TX_05fmt */ 10630 /* nFields */ 1, 10631 /* *fields */ soc_DESCRIPTOR_TX_05_BCM56800_A0fmt_fields, 10632 /* bits */ 32, 10633 /* flags */ 0, 10634 }, 10635 #endif /* chips */ 10636 10637 #if defined(BCM_56440_B0) 10638 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_05_BCM56440_B0fmt */ 10639 /* format DESCRIPTOR_TX_05fmt */ 10640 /* nFields */ 1, 10641 /* *fields */ soc_DESCRIPTOR_TX_05_BCM56800_A0fmt_fields, 10642 /* bits */ 32, 10643 /* flags */ 0, 10644 }, 10645 #endif /* chips */ 10646 10647 #if defined(BCM_56450_A0) 10648 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_05_BCM56450_A0fmt */ 10649 /* format DESCRIPTOR_TX_05fmt */ 10650 /* nFields */ 1, 10651 /* *fields */ soc_DESCRIPTOR_TX_05_BCM56640_A0fmt_fields, 10652 /* bits */ 32, 10653 /* flags */ 0, 10654 }, 10655 #endif /* chips */ 10656 10657 #if defined(BCM_56450_B0) 10658 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_05_BCM56450_B0fmt */ 10659 /* format DESCRIPTOR_TX_05fmt */ 10660 /* nFields */ 1, 10661 /* *fields */ soc_DESCRIPTOR_TX_05_BCM56640_A0fmt_fields, 10662 /* bits */ 32, 10663 /* flags */ 0, 10664 }, 10665 #endif /* chips */ 10666 10667 #if defined(BCM_56450_B1) 10668 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_05_BCM56450_B1fmt */ 10669 /* format DESCRIPTOR_TX_05fmt */ 10670 /* nFields */ 1, 10671 /* *fields */ soc_DESCRIPTOR_TX_05_BCM56640_A0fmt_fields, 10672 /* bits */ 32, 10673 /* flags */ 0, 10674 }, 10675 #endif /* chips */ 10676 10677 #if defined(BCM_56524_A0) 10678 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_05_BCM56524_A0fmt */ 10679 /* format DESCRIPTOR_TX_05fmt */ 10680 /* nFields */ 1, 10681 /* *fields */ soc_DESCRIPTOR_TX_05_BCM56800_A0fmt_fields, 10682 /* bits */ 32, 10683 /* flags */ 0, 10684 }, 10685 #endif /* chips */ 10686 10687 #if defined(BCM_56524_B0) 10688 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_05_BCM56524_B0fmt */ 10689 /* format DESCRIPTOR_TX_05fmt */ 10690 /* nFields */ 1, 10691 /* *fields */ soc_DESCRIPTOR_TX_05_BCM56800_A0fmt_fields, 10692 /* bits */ 32, 10693 /* flags */ 0, 10694 }, 10695 #endif /* chips */ 10696 10697 #if defined(BCM_56560_A0) 10698 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_05_BCM56560_A0fmt */ 10699 /* format DESCRIPTOR_TX_05fmt */ 10700 /* nFields */ 1, 10701 /* *fields */ soc_DESCRIPTOR_TX_05_BCM53400_A0fmt_fields, 10702 /* bits */ 32, 10703 /* flags */ 0, 10704 }, 10705 #endif /* chips */ 10706 10707 #if defined(BCM_56560_B0) 10708 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_05_BCM56560_B0fmt */ 10709 /* format DESCRIPTOR_TX_05fmt */ 10710 /* nFields */ 1, 10711 /* *fields */ soc_DESCRIPTOR_TX_05_BCM53400_A0fmt_fields, 10712 /* bits */ 32, 10713 /* flags */ 0, 10714 }, 10715 #endif /* chips */ 10716 10717 #if defined(BCM_56624_A0) 10718 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_05_BCM56624_A0fmt */ 10719 /* format DESCRIPTOR_TX_05fmt */ 10720 /* nFields */ 1, 10721 /* *fields */ soc_DESCRIPTOR_TX_05_BCM56800_A0fmt_fields, 10722 /* bits */ 32, 10723 /* flags */ 0, 10724 }, 10725 #endif /* chips */ 10726 10727 #if defined(BCM_56624_B0) 10728 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_05_BCM56624_B0fmt */ 10729 /* format DESCRIPTOR_TX_05fmt */ 10730 /* nFields */ 1, 10731 /* *fields */ soc_DESCRIPTOR_TX_05_BCM56800_A0fmt_fields, 10732 /* bits */ 32, 10733 /* flags */ 0, 10734 }, 10735 #endif /* chips */ 10736 10737 #if defined(BCM_56634_A0) 10738 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_05_BCM56634_A0fmt */ 10739 /* format DESCRIPTOR_TX_05fmt */ 10740 /* nFields */ 1, 10741 /* *fields */ soc_DESCRIPTOR_TX_05_BCM56800_A0fmt_fields, 10742 /* bits */ 32, 10743 /* flags */ 0, 10744 }, 10745 #endif /* chips */ 10746 10747 #if defined(BCM_56634_B0) 10748 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_05_BCM56634_B0fmt */ 10749 /* format DESCRIPTOR_TX_05fmt */ 10750 /* nFields */ 1, 10751 /* *fields */ soc_DESCRIPTOR_TX_05_BCM56800_A0fmt_fields, 10752 /* bits */ 32, 10753 /* flags */ 0, 10754 }, 10755 #endif /* chips */ 10756 10757 #if defined(BCM_56640_A0) 10758 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_05_BCM56640_A0fmt */ 10759 /* format DESCRIPTOR_TX_05fmt */ 10760 /* nFields */ 1, 10761 /* *fields */ soc_DESCRIPTOR_TX_05_BCM56640_A0fmt_fields, 10762 /* bits */ 32, 10763 /* flags */ 0, 10764 }, 10765 #endif /* chips */ 10766 10767 #if defined(BCM_56670_A0) 10768 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_05_BCM56670_A0fmt */ 10769 /* format DESCRIPTOR_TX_05fmt */ 10770 /* nFields */ 1, 10771 /* *fields */ soc_DESCRIPTOR_TX_05_BCM53400_A0fmt_fields, 10772 /* bits */ 32, 10773 /* flags */ 0, 10774 }, 10775 #endif /* chips */ 10776 10777 #if defined(BCM_56670_B0) 10778 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_05_BCM56670_B0fmt */ 10779 /* format DESCRIPTOR_TX_05fmt */ 10780 /* nFields */ 1, 10781 /* *fields */ soc_DESCRIPTOR_TX_05_BCM53400_A0fmt_fields, 10782 /* bits */ 32, 10783 /* flags */ 0, 10784 }, 10785 #endif /* chips */ 10786 10787 #if defined(BCM_56680_A0) 10788 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_05_BCM56680_A0fmt */ 10789 /* format DESCRIPTOR_TX_05fmt */ 10790 /* nFields */ 1, 10791 /* *fields */ soc_DESCRIPTOR_TX_05_BCM56800_A0fmt_fields, 10792 /* bits */ 32, 10793 /* flags */ 0, 10794 }, 10795 #endif /* chips */ 10796 10797 #if defined(BCM_56680_B0) 10798 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_05_BCM56680_B0fmt */ 10799 /* format DESCRIPTOR_TX_05fmt */ 10800 /* nFields */ 1, 10801 /* *fields */ soc_DESCRIPTOR_TX_05_BCM56800_A0fmt_fields, 10802 /* bits */ 32, 10803 /* flags */ 0, 10804 }, 10805 #endif /* chips */ 10806 10807 #if defined(BCM_56685_A0) 10808 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_05_BCM56685_A0fmt */ 10809 /* format DESCRIPTOR_TX_05fmt */ 10810 /* nFields */ 1, 10811 /* *fields */ soc_DESCRIPTOR_TX_05_BCM56800_A0fmt_fields, 10812 /* bits */ 32, 10813 /* flags */ 0, 10814 }, 10815 #endif /* chips */ 10816 10817 #if defined(BCM_56685_B0) 10818 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_05_BCM56685_B0fmt */ 10819 /* format DESCRIPTOR_TX_05fmt */ 10820 /* nFields */ 1, 10821 /* *fields */ soc_DESCRIPTOR_TX_05_BCM56800_A0fmt_fields, 10822 /* bits */ 32, 10823 /* flags */ 0, 10824 }, 10825 #endif /* chips */ 10826 10827 #if defined(BCM_56725_A0) 10828 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_05_BCM56725_A0fmt */ 10829 /* format DESCRIPTOR_TX_05fmt */ 10830 /* nFields */ 1, 10831 /* *fields */ soc_DESCRIPTOR_TX_05_BCM56800_A0fmt_fields, 10832 /* bits */ 32, 10833 /* flags */ 0, 10834 }, 10835 #endif /* chips */ 10836 10837 #if defined(BCM_56800_A0) 10838 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_05_BCM56800_A0fmt */ 10839 /* format DESCRIPTOR_TX_05fmt */ 10840 /* nFields */ 1, 10841 /* *fields */ soc_DESCRIPTOR_TX_05_BCM56800_A0fmt_fields, 10842 /* bits */ 32, 10843 /* flags */ 0, 10844 }, 10845 #endif /* chips */ 10846 10847 #if defined(BCM_56820_A0) 10848 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_05_BCM56820_A0fmt */ 10849 /* format DESCRIPTOR_TX_05fmt */ 10850 /* nFields */ 1, 10851 /* *fields */ soc_DESCRIPTOR_TX_05_BCM56800_A0fmt_fields, 10852 /* bits */ 32, 10853 /* flags */ 0, 10854 }, 10855 #endif /* chips */ 10856 10857 #if defined(BCM_56840_A0) 10858 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_05_BCM56840_A0fmt */ 10859 /* format DESCRIPTOR_TX_05fmt */ 10860 /* nFields */ 1, 10861 /* *fields */ soc_DESCRIPTOR_TX_05_BCM56800_A0fmt_fields, 10862 /* bits */ 32, 10863 /* flags */ 0, 10864 }, 10865 #endif /* chips */ 10866 10867 #if defined(BCM_56840_B0) 10868 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_05_BCM56840_B0fmt */ 10869 /* format DESCRIPTOR_TX_05fmt */ 10870 /* nFields */ 1, 10871 /* *fields */ soc_DESCRIPTOR_TX_05_BCM56800_A0fmt_fields, 10872 /* bits */ 32, 10873 /* flags */ 0, 10874 }, 10875 #endif /* chips */ 10876 10877 #if defined(BCM_56850_A0) 10878 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_05_BCM56850_A0fmt */ 10879 /* format DESCRIPTOR_TX_05fmt */ 10880 /* nFields */ 1, 10881 /* *fields */ soc_DESCRIPTOR_TX_05_BCM56640_A0fmt_fields, 10882 /* bits */ 32, 10883 /* flags */ 0, 10884 }, 10885 #endif /* chips */ 10886 10887 #if defined(BCM_56860_A0) 10888 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_05_BCM56860_A0fmt */ 10889 /* format DESCRIPTOR_TX_05fmt */ 10890 /* nFields */ 1, 10891 /* *fields */ soc_DESCRIPTOR_TX_05_BCM56640_A0fmt_fields, 10892 /* bits */ 32, 10893 /* flags */ 0, 10894 }, 10895 #endif /* chips */ 10896 10897 #if defined(BCM_56960_A0) 10898 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_05_BCM56960_A0fmt */ 10899 /* format DESCRIPTOR_TX_05fmt */ 10900 /* nFields */ 1, 10901 /* *fields */ soc_DESCRIPTOR_TX_05_BCM53400_A0fmt_fields, 10902 /* bits */ 32, 10903 /* flags */ 0, 10904 }, 10905 #endif /* chips */ 10906 10907 #if defined(BCM_56965_A0) 10908 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_05_BCM56965_A0fmt */ 10909 /* format DESCRIPTOR_TX_05fmt */ 10910 /* nFields */ 1, 10911 /* *fields */ soc_DESCRIPTOR_TX_05_BCM53400_A0fmt_fields, 10912 /* bits */ 32, 10913 /* flags */ 0, 10914 }, 10915 #endif /* chips */ 10916 10917 #if defined(BCM_56970_A0) 10918 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_05_BCM56970_A0fmt */ 10919 /* format DESCRIPTOR_TX_05fmt */ 10920 /* nFields */ 1, 10921 /* *fields */ soc_DESCRIPTOR_TX_05_BCM53400_A0fmt_fields, 10922 /* bits */ 32, 10923 /* flags */ 0, 10924 }, 10925 #endif /* chips */ 10926 10927 #if defined(BCM_88732_A0) 10928 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_05_BCM88732_A0fmt */ 10929 /* format DESCRIPTOR_TX_05fmt */ 10930 /* nFields */ 1, 10931 /* *fields */ soc_DESCRIPTOR_TX_05_BCM56800_A0fmt_fields, 10932 /* bits */ 32, 10933 /* flags */ 0, 10934 }, 10935 #endif /* chips */ 10936 10937 #if defined(BCM_53400_A0) 10938 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_06_BCM53400_A0fmt */ 10939 /* format DESCRIPTOR_TX_06fmt */ 10940 /* nFields */ 1, 10941 /* *fields */ soc_DESCRIPTOR_TX_06_BCM53400_A0fmt_fields, 10942 /* bits */ 32, 10943 /* flags */ 0, 10944 }, 10945 #endif /* chips */ 10946 10947 #if defined(BCM_53540_A0) 10948 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_06_BCM53540_A0fmt */ 10949 /* format DESCRIPTOR_TX_06fmt */ 10950 /* nFields */ 1, 10951 /* *fields */ soc_DESCRIPTOR_TX_06_BCM53400_A0fmt_fields, 10952 /* bits */ 32, 10953 /* flags */ 0, 10954 }, 10955 #endif /* chips */ 10956 10957 #if defined(BCM_53570_A0) 10958 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_06_BCM53570_A0fmt */ 10959 /* format DESCRIPTOR_TX_06fmt */ 10960 /* nFields */ 1, 10961 /* *fields */ soc_DESCRIPTOR_TX_06_BCM53400_A0fmt_fields, 10962 /* bits */ 32, 10963 /* flags */ 0, 10964 }, 10965 #endif /* chips */ 10966 10967 #if defined(BCM_53570_B0) 10968 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_06_BCM53570_B0fmt */ 10969 /* format DESCRIPTOR_TX_06fmt */ 10970 /* nFields */ 1, 10971 /* *fields */ soc_DESCRIPTOR_TX_06_BCM53400_A0fmt_fields, 10972 /* bits */ 32, 10973 /* flags */ 0, 10974 }, 10975 #endif /* chips */ 10976 10977 #if defined(BCM_56150_A0) 10978 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_06_BCM56150_A0fmt */ 10979 /* format DESCRIPTOR_TX_06fmt */ 10980 /* nFields */ 1, 10981 /* *fields */ soc_DESCRIPTOR_TX_06_BCM56640_A0fmt_fields, 10982 /* bits */ 32, 10983 /* flags */ 0, 10984 }, 10985 #endif /* chips */ 10986 10987 #if defined(BCM_56160_A0) 10988 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_06_BCM56160_A0fmt */ 10989 /* format DESCRIPTOR_TX_06fmt */ 10990 /* nFields */ 1, 10991 /* *fields */ soc_DESCRIPTOR_TX_06_BCM53400_A0fmt_fields, 10992 /* bits */ 32, 10993 /* flags */ 0, 10994 }, 10995 #endif /* chips */ 10996 10997 #if defined(BCM_56260_A0) 10998 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_06_BCM56260_A0fmt */ 10999 /* format DESCRIPTOR_TX_06fmt */ 11000 /* nFields */ 1, 11001 /* *fields */ soc_DESCRIPTOR_TX_06_BCM53400_A0fmt_fields, 11002 /* bits */ 32, 11003 /* flags */ 0, 11004 }, 11005 #endif /* chips */ 11006 11007 #if defined(BCM_56260_B0) 11008 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_06_BCM56260_B0fmt */ 11009 /* format DESCRIPTOR_TX_06fmt */ 11010 /* nFields */ 1, 11011 /* *fields */ soc_DESCRIPTOR_TX_06_BCM53400_A0fmt_fields, 11012 /* bits */ 32, 11013 /* flags */ 0, 11014 }, 11015 #endif /* chips */ 11016 11017 #if defined(BCM_56270_A0) 11018 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_06_BCM56270_A0fmt */ 11019 /* format DESCRIPTOR_TX_06fmt */ 11020 /* nFields */ 1, 11021 /* *fields */ soc_DESCRIPTOR_TX_06_BCM53400_A0fmt_fields, 11022 /* bits */ 32, 11023 /* flags */ 0, 11024 }, 11025 #endif /* chips */ 11026 11027 #if defined(BCM_56340_A0) 11028 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_06_BCM56340_A0fmt */ 11029 /* format DESCRIPTOR_TX_06fmt */ 11030 /* nFields */ 1, 11031 /* *fields */ soc_DESCRIPTOR_TX_06_BCM56640_A0fmt_fields, 11032 /* bits */ 32, 11033 /* flags */ 0, 11034 }, 11035 #endif /* chips */ 11036 11037 #if defined(BCM_56450_A0) 11038 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_06_BCM56450_A0fmt */ 11039 /* format DESCRIPTOR_TX_06fmt */ 11040 /* nFields */ 1, 11041 /* *fields */ soc_DESCRIPTOR_TX_06_BCM56640_A0fmt_fields, 11042 /* bits */ 32, 11043 /* flags */ 0, 11044 }, 11045 #endif /* chips */ 11046 11047 #if defined(BCM_56450_B0) 11048 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_06_BCM56450_B0fmt */ 11049 /* format DESCRIPTOR_TX_06fmt */ 11050 /* nFields */ 1, 11051 /* *fields */ soc_DESCRIPTOR_TX_06_BCM56640_A0fmt_fields, 11052 /* bits */ 32, 11053 /* flags */ 0, 11054 }, 11055 #endif /* chips */ 11056 11057 #if defined(BCM_56450_B1) 11058 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_06_BCM56450_B1fmt */ 11059 /* format DESCRIPTOR_TX_06fmt */ 11060 /* nFields */ 1, 11061 /* *fields */ soc_DESCRIPTOR_TX_06_BCM56640_A0fmt_fields, 11062 /* bits */ 32, 11063 /* flags */ 0, 11064 }, 11065 #endif /* chips */ 11066 11067 #if defined(BCM_56560_A0) 11068 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_06_BCM56560_A0fmt */ 11069 /* format DESCRIPTOR_TX_06fmt */ 11070 /* nFields */ 1, 11071 /* *fields */ soc_DESCRIPTOR_TX_06_BCM53400_A0fmt_fields, 11072 /* bits */ 32, 11073 /* flags */ 0, 11074 }, 11075 #endif /* chips */ 11076 11077 #if defined(BCM_56560_B0) 11078 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_06_BCM56560_B0fmt */ 11079 /* format DESCRIPTOR_TX_06fmt */ 11080 /* nFields */ 1, 11081 /* *fields */ soc_DESCRIPTOR_TX_06_BCM53400_A0fmt_fields, 11082 /* bits */ 32, 11083 /* flags */ 0, 11084 }, 11085 #endif /* chips */ 11086 11087 #if defined(BCM_56640_A0) 11088 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_06_BCM56640_A0fmt */ 11089 /* format DESCRIPTOR_TX_06fmt */ 11090 /* nFields */ 1, 11091 /* *fields */ soc_DESCRIPTOR_TX_06_BCM56640_A0fmt_fields, 11092 /* bits */ 32, 11093 /* flags */ 0, 11094 }, 11095 #endif /* chips */ 11096 11097 #if defined(BCM_56670_A0) 11098 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_06_BCM56670_A0fmt */ 11099 /* format DESCRIPTOR_TX_06fmt */ 11100 /* nFields */ 1, 11101 /* *fields */ soc_DESCRIPTOR_TX_06_BCM53400_A0fmt_fields, 11102 /* bits */ 32, 11103 /* flags */ 0, 11104 }, 11105 #endif /* chips */ 11106 11107 #if defined(BCM_56670_B0) 11108 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_06_BCM56670_B0fmt */ 11109 /* format DESCRIPTOR_TX_06fmt */ 11110 /* nFields */ 1, 11111 /* *fields */ soc_DESCRIPTOR_TX_06_BCM53400_A0fmt_fields, 11112 /* bits */ 32, 11113 /* flags */ 0, 11114 }, 11115 #endif /* chips */ 11116 11117 #if defined(BCM_56685_A0) 11118 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_06_BCM56685_A0fmt */ 11119 /* format DESCRIPTOR_TX_06fmt */ 11120 /* nFields */ 1, 11121 /* *fields */ soc_DESCRIPTOR_TX_06fmt_fields, 11122 /* bits */ 32, 11123 /* flags */ 0, 11124 }, 11125 #endif /* chips */ 11126 11127 #if defined(BCM_56800_A0) 11128 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_06_BCM56800_A0fmt */ 11129 /* format DESCRIPTOR_TX_06fmt */ 11130 /* nFields */ 1, 11131 /* *fields */ soc_DESCRIPTOR_TX_06fmt_fields, 11132 /* bits */ 32, 11133 /* flags */ 0, 11134 }, 11135 #endif /* chips */ 11136 11137 #if defined(BCM_56850_A0) 11138 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_06_BCM56850_A0fmt */ 11139 /* format DESCRIPTOR_TX_06fmt */ 11140 /* nFields */ 1, 11141 /* *fields */ soc_DESCRIPTOR_TX_06_BCM56640_A0fmt_fields, 11142 /* bits */ 32, 11143 /* flags */ 0, 11144 }, 11145 #endif /* chips */ 11146 11147 #if defined(BCM_56860_A0) 11148 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_06_BCM56860_A0fmt */ 11149 /* format DESCRIPTOR_TX_06fmt */ 11150 /* nFields */ 1, 11151 /* *fields */ soc_DESCRIPTOR_TX_06_BCM56640_A0fmt_fields, 11152 /* bits */ 32, 11153 /* flags */ 0, 11154 }, 11155 #endif /* chips */ 11156 11157 #if defined(BCM_56960_A0) 11158 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_06_BCM56960_A0fmt */ 11159 /* format DESCRIPTOR_TX_06fmt */ 11160 /* nFields */ 1, 11161 /* *fields */ soc_DESCRIPTOR_TX_06_BCM53400_A0fmt_fields, 11162 /* bits */ 32, 11163 /* flags */ 0, 11164 }, 11165 #endif /* chips */ 11166 11167 #if defined(BCM_56965_A0) 11168 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_06_BCM56965_A0fmt */ 11169 /* format DESCRIPTOR_TX_06fmt */ 11170 /* nFields */ 1, 11171 /* *fields */ soc_DESCRIPTOR_TX_06_BCM53400_A0fmt_fields, 11172 /* bits */ 32, 11173 /* flags */ 0, 11174 }, 11175 #endif /* chips */ 11176 11177 #if defined(BCM_56970_A0) 11178 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_06_BCM56970_A0fmt */ 11179 /* format DESCRIPTOR_TX_06fmt */ 11180 /* nFields */ 1, 11181 /* *fields */ soc_DESCRIPTOR_TX_06_BCM53400_A0fmt_fields, 11182 /* bits */ 32, 11183 /* flags */ 0, 11184 }, 11185 #endif /* chips */ 11186 11187 #if defined(BCM_53400_A0) 11188 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_07_BCM53400_A0fmt */ 11189 /* format DESCRIPTOR_TX_07fmt */ 11190 /* nFields */ 1, 11191 /* *fields */ soc_DESCRIPTOR_TX_07_BCM53400_A0fmt_fields, 11192 /* bits */ 32, 11193 /* flags */ 0, 11194 }, 11195 #endif /* chips */ 11196 11197 #if defined(BCM_53540_A0) 11198 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_07_BCM53540_A0fmt */ 11199 /* format DESCRIPTOR_TX_07fmt */ 11200 /* nFields */ 1, 11201 /* *fields */ soc_DESCRIPTOR_TX_07_BCM53400_A0fmt_fields, 11202 /* bits */ 32, 11203 /* flags */ 0, 11204 }, 11205 #endif /* chips */ 11206 11207 #if defined(BCM_53570_A0) 11208 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_07_BCM53570_A0fmt */ 11209 /* format DESCRIPTOR_TX_07fmt */ 11210 /* nFields */ 1, 11211 /* *fields */ soc_DESCRIPTOR_TX_07_BCM53400_A0fmt_fields, 11212 /* bits */ 32, 11213 /* flags */ 0, 11214 }, 11215 #endif /* chips */ 11216 11217 #if defined(BCM_53570_B0) 11218 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_07_BCM53570_B0fmt */ 11219 /* format DESCRIPTOR_TX_07fmt */ 11220 /* nFields */ 1, 11221 /* *fields */ soc_DESCRIPTOR_TX_07_BCM53400_A0fmt_fields, 11222 /* bits */ 32, 11223 /* flags */ 0, 11224 }, 11225 #endif /* chips */ 11226 11227 #if defined(BCM_56150_A0) 11228 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_07_BCM56150_A0fmt */ 11229 /* format DESCRIPTOR_TX_07fmt */ 11230 /* nFields */ 1, 11231 /* *fields */ soc_DESCRIPTOR_TX_07_BCM56640_A0fmt_fields, 11232 /* bits */ 32, 11233 /* flags */ 0, 11234 }, 11235 #endif /* chips */ 11236 11237 #if defined(BCM_56160_A0) 11238 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_07_BCM56160_A0fmt */ 11239 /* format DESCRIPTOR_TX_07fmt */ 11240 /* nFields */ 1, 11241 /* *fields */ soc_DESCRIPTOR_TX_07_BCM53400_A0fmt_fields, 11242 /* bits */ 32, 11243 /* flags */ 0, 11244 }, 11245 #endif /* chips */ 11246 11247 #if defined(BCM_56260_A0) 11248 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_07_BCM56260_A0fmt */ 11249 /* format DESCRIPTOR_TX_07fmt */ 11250 /* nFields */ 1, 11251 /* *fields */ soc_DESCRIPTOR_TX_07_BCM53400_A0fmt_fields, 11252 /* bits */ 32, 11253 /* flags */ 0, 11254 }, 11255 #endif /* chips */ 11256 11257 #if defined(BCM_56260_B0) 11258 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_07_BCM56260_B0fmt */ 11259 /* format DESCRIPTOR_TX_07fmt */ 11260 /* nFields */ 1, 11261 /* *fields */ soc_DESCRIPTOR_TX_07_BCM53400_A0fmt_fields, 11262 /* bits */ 32, 11263 /* flags */ 0, 11264 }, 11265 #endif /* chips */ 11266 11267 #if defined(BCM_56270_A0) 11268 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_07_BCM56270_A0fmt */ 11269 /* format DESCRIPTOR_TX_07fmt */ 11270 /* nFields */ 1, 11271 /* *fields */ soc_DESCRIPTOR_TX_07_BCM53400_A0fmt_fields, 11272 /* bits */ 32, 11273 /* flags */ 0, 11274 }, 11275 #endif /* chips */ 11276 11277 #if defined(BCM_56340_A0) 11278 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_07_BCM56340_A0fmt */ 11279 /* format DESCRIPTOR_TX_07fmt */ 11280 /* nFields */ 1, 11281 /* *fields */ soc_DESCRIPTOR_TX_07_BCM56640_A0fmt_fields, 11282 /* bits */ 32, 11283 /* flags */ 0, 11284 }, 11285 #endif /* chips */ 11286 11287 #if defined(BCM_56450_A0) 11288 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_07_BCM56450_A0fmt */ 11289 /* format DESCRIPTOR_TX_07fmt */ 11290 /* nFields */ 1, 11291 /* *fields */ soc_DESCRIPTOR_TX_07_BCM56640_A0fmt_fields, 11292 /* bits */ 32, 11293 /* flags */ 0, 11294 }, 11295 #endif /* chips */ 11296 11297 #if defined(BCM_56450_B0) 11298 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_07_BCM56450_B0fmt */ 11299 /* format DESCRIPTOR_TX_07fmt */ 11300 /* nFields */ 1, 11301 /* *fields */ soc_DESCRIPTOR_TX_07_BCM56640_A0fmt_fields, 11302 /* bits */ 32, 11303 /* flags */ 0, 11304 }, 11305 #endif /* chips */ 11306 11307 #if defined(BCM_56450_B1) 11308 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_07_BCM56450_B1fmt */ 11309 /* format DESCRIPTOR_TX_07fmt */ 11310 /* nFields */ 1, 11311 /* *fields */ soc_DESCRIPTOR_TX_07_BCM56640_A0fmt_fields, 11312 /* bits */ 32, 11313 /* flags */ 0, 11314 }, 11315 #endif /* chips */ 11316 11317 #if defined(BCM_56560_A0) 11318 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_07_BCM56560_A0fmt */ 11319 /* format DESCRIPTOR_TX_07fmt */ 11320 /* nFields */ 1, 11321 /* *fields */ soc_DESCRIPTOR_TX_07_BCM53400_A0fmt_fields, 11322 /* bits */ 32, 11323 /* flags */ 0, 11324 }, 11325 #endif /* chips */ 11326 11327 #if defined(BCM_56560_B0) 11328 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_07_BCM56560_B0fmt */ 11329 /* format DESCRIPTOR_TX_07fmt */ 11330 /* nFields */ 1, 11331 /* *fields */ soc_DESCRIPTOR_TX_07_BCM53400_A0fmt_fields, 11332 /* bits */ 32, 11333 /* flags */ 0, 11334 }, 11335 #endif /* chips */ 11336 11337 #if defined(BCM_56640_A0) 11338 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_07_BCM56640_A0fmt */ 11339 /* format DESCRIPTOR_TX_07fmt */ 11340 /* nFields */ 1, 11341 /* *fields */ soc_DESCRIPTOR_TX_07_BCM56640_A0fmt_fields, 11342 /* bits */ 32, 11343 /* flags */ 0, 11344 }, 11345 #endif /* chips */ 11346 11347 #if defined(BCM_56670_A0) 11348 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_07_BCM56670_A0fmt */ 11349 /* format DESCRIPTOR_TX_07fmt */ 11350 /* nFields */ 1, 11351 /* *fields */ soc_DESCRIPTOR_TX_07_BCM53400_A0fmt_fields, 11352 /* bits */ 32, 11353 /* flags */ 0, 11354 }, 11355 #endif /* chips */ 11356 11357 #if defined(BCM_56670_B0) 11358 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_07_BCM56670_B0fmt */ 11359 /* format DESCRIPTOR_TX_07fmt */ 11360 /* nFields */ 1, 11361 /* *fields */ soc_DESCRIPTOR_TX_07_BCM53400_A0fmt_fields, 11362 /* bits */ 32, 11363 /* flags */ 0, 11364 }, 11365 #endif /* chips */ 11366 11367 #if defined(BCM_56685_A0) 11368 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_07_BCM56685_A0fmt */ 11369 /* format DESCRIPTOR_TX_07fmt */ 11370 /* nFields */ 1, 11371 /* *fields */ soc_DESCRIPTOR_TX_07fmt_fields, 11372 /* bits */ 32, 11373 /* flags */ 0, 11374 }, 11375 #endif /* chips */ 11376 11377 #if defined(BCM_56800_A0) 11378 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_07_BCM56800_A0fmt */ 11379 /* format DESCRIPTOR_TX_07fmt */ 11380 /* nFields */ 1, 11381 /* *fields */ soc_DESCRIPTOR_TX_07fmt_fields, 11382 /* bits */ 32, 11383 /* flags */ 0, 11384 }, 11385 #endif /* chips */ 11386 11387 #if defined(BCM_56850_A0) 11388 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_07_BCM56850_A0fmt */ 11389 /* format DESCRIPTOR_TX_07fmt */ 11390 /* nFields */ 1, 11391 /* *fields */ soc_DESCRIPTOR_TX_07_BCM56640_A0fmt_fields, 11392 /* bits */ 32, 11393 /* flags */ 0, 11394 }, 11395 #endif /* chips */ 11396 11397 #if defined(BCM_56860_A0) 11398 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_07_BCM56860_A0fmt */ 11399 /* format DESCRIPTOR_TX_07fmt */ 11400 /* nFields */ 1, 11401 /* *fields */ soc_DESCRIPTOR_TX_07_BCM56640_A0fmt_fields, 11402 /* bits */ 32, 11403 /* flags */ 0, 11404 }, 11405 #endif /* chips */ 11406 11407 #if defined(BCM_56960_A0) 11408 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_07_BCM56960_A0fmt */ 11409 /* format DESCRIPTOR_TX_07fmt */ 11410 /* nFields */ 1, 11411 /* *fields */ soc_DESCRIPTOR_TX_07_BCM53400_A0fmt_fields, 11412 /* bits */ 32, 11413 /* flags */ 0, 11414 }, 11415 #endif /* chips */ 11416 11417 #if defined(BCM_56965_A0) 11418 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_07_BCM56965_A0fmt */ 11419 /* format DESCRIPTOR_TX_07fmt */ 11420 /* nFields */ 1, 11421 /* *fields */ soc_DESCRIPTOR_TX_07_BCM53400_A0fmt_fields, 11422 /* bits */ 32, 11423 /* flags */ 0, 11424 }, 11425 #endif /* chips */ 11426 11427 #if defined(BCM_56970_A0) 11428 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_07_BCM56970_A0fmt */ 11429 /* format DESCRIPTOR_TX_07fmt */ 11430 /* nFields */ 1, 11431 /* *fields */ soc_DESCRIPTOR_TX_07_BCM53400_A0fmt_fields, 11432 /* bits */ 32, 11433 /* flags */ 0, 11434 }, 11435 #endif /* chips */ 11436 11437 #if defined(BCM_53400_A0) 11438 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_08_BCM53400_A0fmt */ 11439 /* format DESCRIPTOR_TX_08fmt */ 11440 /* nFields */ 1, 11441 /* *fields */ soc_DESCRIPTOR_TX_08_BCM53400_A0fmt_fields, 11442 /* bits */ 32, 11443 /* flags */ 0, 11444 }, 11445 #endif /* chips */ 11446 11447 #if defined(BCM_53540_A0) 11448 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_08_BCM53540_A0fmt */ 11449 /* format DESCRIPTOR_TX_08fmt */ 11450 /* nFields */ 1, 11451 /* *fields */ soc_DESCRIPTOR_TX_08_BCM53400_A0fmt_fields, 11452 /* bits */ 32, 11453 /* flags */ 0, 11454 }, 11455 #endif /* chips */ 11456 11457 #if defined(BCM_53570_A0) 11458 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_08_BCM53570_A0fmt */ 11459 /* format DESCRIPTOR_TX_08fmt */ 11460 /* nFields */ 1, 11461 /* *fields */ soc_DESCRIPTOR_TX_08_BCM53400_A0fmt_fields, 11462 /* bits */ 32, 11463 /* flags */ 0, 11464 }, 11465 #endif /* chips */ 11466 11467 #if defined(BCM_53570_B0) 11468 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_08_BCM53570_B0fmt */ 11469 /* format DESCRIPTOR_TX_08fmt */ 11470 /* nFields */ 1, 11471 /* *fields */ soc_DESCRIPTOR_TX_08_BCM53400_A0fmt_fields, 11472 /* bits */ 32, 11473 /* flags */ 0, 11474 }, 11475 #endif /* chips */ 11476 11477 #if defined(BCM_56150_A0) 11478 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_08_BCM56150_A0fmt */ 11479 /* format DESCRIPTOR_TX_08fmt */ 11480 /* nFields */ 1, 11481 /* *fields */ soc_DESCRIPTOR_TX_08_BCM56640_A0fmt_fields, 11482 /* bits */ 32, 11483 /* flags */ 0, 11484 }, 11485 #endif /* chips */ 11486 11487 #if defined(BCM_56160_A0) 11488 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_08_BCM56160_A0fmt */ 11489 /* format DESCRIPTOR_TX_08fmt */ 11490 /* nFields */ 1, 11491 /* *fields */ soc_DESCRIPTOR_TX_08_BCM53400_A0fmt_fields, 11492 /* bits */ 32, 11493 /* flags */ 0, 11494 }, 11495 #endif /* chips */ 11496 11497 #if defined(BCM_56260_A0) 11498 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_08_BCM56260_A0fmt */ 11499 /* format DESCRIPTOR_TX_08fmt */ 11500 /* nFields */ 1, 11501 /* *fields */ soc_DESCRIPTOR_TX_08_BCM53400_A0fmt_fields, 11502 /* bits */ 32, 11503 /* flags */ 0, 11504 }, 11505 #endif /* chips */ 11506 11507 #if defined(BCM_56260_B0) 11508 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_08_BCM56260_B0fmt */ 11509 /* format DESCRIPTOR_TX_08fmt */ 11510 /* nFields */ 1, 11511 /* *fields */ soc_DESCRIPTOR_TX_08_BCM53400_A0fmt_fields, 11512 /* bits */ 32, 11513 /* flags */ 0, 11514 }, 11515 #endif /* chips */ 11516 11517 #if defined(BCM_56270_A0) 11518 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_08_BCM56270_A0fmt */ 11519 /* format DESCRIPTOR_TX_08fmt */ 11520 /* nFields */ 1, 11521 /* *fields */ soc_DESCRIPTOR_TX_08_BCM53400_A0fmt_fields, 11522 /* bits */ 32, 11523 /* flags */ 0, 11524 }, 11525 #endif /* chips */ 11526 11527 #if defined(BCM_56340_A0) 11528 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_08_BCM56340_A0fmt */ 11529 /* format DESCRIPTOR_TX_08fmt */ 11530 /* nFields */ 1, 11531 /* *fields */ soc_DESCRIPTOR_TX_08_BCM56640_A0fmt_fields, 11532 /* bits */ 32, 11533 /* flags */ 0, 11534 }, 11535 #endif /* chips */ 11536 11537 #if defined(BCM_56450_A0) 11538 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_08_BCM56450_A0fmt */ 11539 /* format DESCRIPTOR_TX_08fmt */ 11540 /* nFields */ 1, 11541 /* *fields */ soc_DESCRIPTOR_TX_08_BCM56640_A0fmt_fields, 11542 /* bits */ 32, 11543 /* flags */ 0, 11544 }, 11545 #endif /* chips */ 11546 11547 #if defined(BCM_56450_B0) 11548 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_08_BCM56450_B0fmt */ 11549 /* format DESCRIPTOR_TX_08fmt */ 11550 /* nFields */ 1, 11551 /* *fields */ soc_DESCRIPTOR_TX_08_BCM56640_A0fmt_fields, 11552 /* bits */ 32, 11553 /* flags */ 0, 11554 }, 11555 #endif /* chips */ 11556 11557 #if defined(BCM_56450_B1) 11558 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_08_BCM56450_B1fmt */ 11559 /* format DESCRIPTOR_TX_08fmt */ 11560 /* nFields */ 1, 11561 /* *fields */ soc_DESCRIPTOR_TX_08_BCM56640_A0fmt_fields, 11562 /* bits */ 32, 11563 /* flags */ 0, 11564 }, 11565 #endif /* chips */ 11566 11567 #if defined(BCM_56560_A0) 11568 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_08_BCM56560_A0fmt */ 11569 /* format DESCRIPTOR_TX_08fmt */ 11570 /* nFields */ 1, 11571 /* *fields */ soc_DESCRIPTOR_TX_08_BCM53400_A0fmt_fields, 11572 /* bits */ 32, 11573 /* flags */ 0, 11574 }, 11575 #endif /* chips */ 11576 11577 #if defined(BCM_56560_B0) 11578 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_08_BCM56560_B0fmt */ 11579 /* format DESCRIPTOR_TX_08fmt */ 11580 /* nFields */ 1, 11581 /* *fields */ soc_DESCRIPTOR_TX_08_BCM53400_A0fmt_fields, 11582 /* bits */ 32, 11583 /* flags */ 0, 11584 }, 11585 #endif /* chips */ 11586 11587 #if defined(BCM_56640_A0) 11588 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_08_BCM56640_A0fmt */ 11589 /* format DESCRIPTOR_TX_08fmt */ 11590 /* nFields */ 1, 11591 /* *fields */ soc_DESCRIPTOR_TX_08_BCM56640_A0fmt_fields, 11592 /* bits */ 32, 11593 /* flags */ 0, 11594 }, 11595 #endif /* chips */ 11596 11597 #if defined(BCM_56670_A0) 11598 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_08_BCM56670_A0fmt */ 11599 /* format DESCRIPTOR_TX_08fmt */ 11600 /* nFields */ 1, 11601 /* *fields */ soc_DESCRIPTOR_TX_08_BCM53400_A0fmt_fields, 11602 /* bits */ 32, 11603 /* flags */ 0, 11604 }, 11605 #endif /* chips */ 11606 11607 #if defined(BCM_56670_B0) 11608 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_08_BCM56670_B0fmt */ 11609 /* format DESCRIPTOR_TX_08fmt */ 11610 /* nFields */ 1, 11611 /* *fields */ soc_DESCRIPTOR_TX_08_BCM53400_A0fmt_fields, 11612 /* bits */ 32, 11613 /* flags */ 0, 11614 }, 11615 #endif /* chips */ 11616 11617 #if defined(BCM_56850_A0) 11618 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_08_BCM56850_A0fmt */ 11619 /* format DESCRIPTOR_TX_08fmt */ 11620 /* nFields */ 1, 11621 /* *fields */ soc_DESCRIPTOR_TX_08_BCM56640_A0fmt_fields, 11622 /* bits */ 32, 11623 /* flags */ 0, 11624 }, 11625 #endif /* chips */ 11626 11627 #if defined(BCM_56860_A0) 11628 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_08_BCM56860_A0fmt */ 11629 /* format DESCRIPTOR_TX_08fmt */ 11630 /* nFields */ 1, 11631 /* *fields */ soc_DESCRIPTOR_TX_08_BCM56640_A0fmt_fields, 11632 /* bits */ 32, 11633 /* flags */ 0, 11634 }, 11635 #endif /* chips */ 11636 11637 #if defined(BCM_56960_A0) 11638 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_08_BCM56960_A0fmt */ 11639 /* format DESCRIPTOR_TX_08fmt */ 11640 /* nFields */ 1, 11641 /* *fields */ soc_DESCRIPTOR_TX_08_BCM53400_A0fmt_fields, 11642 /* bits */ 32, 11643 /* flags */ 0, 11644 }, 11645 #endif /* chips */ 11646 11647 #if defined(BCM_56965_A0) 11648 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_08_BCM56965_A0fmt */ 11649 /* format DESCRIPTOR_TX_08fmt */ 11650 /* nFields */ 1, 11651 /* *fields */ soc_DESCRIPTOR_TX_08_BCM53400_A0fmt_fields, 11652 /* bits */ 32, 11653 /* flags */ 0, 11654 }, 11655 #endif /* chips */ 11656 11657 #if defined(BCM_56970_A0) 11658 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_08_BCM56970_A0fmt */ 11659 /* format DESCRIPTOR_TX_08fmt */ 11660 /* nFields */ 1, 11661 /* *fields */ soc_DESCRIPTOR_TX_08_BCM53400_A0fmt_fields, 11662 /* bits */ 32, 11663 /* flags */ 0, 11664 }, 11665 #endif /* chips */ 11666 11667 #if defined(BCM_53400_A0) 11668 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_09_BCM53400_A0fmt */ 11669 /* format DESCRIPTOR_TX_09fmt */ 11670 /* nFields */ 1, 11671 /* *fields */ soc_DESCRIPTOR_TX_09_BCM53400_A0fmt_fields, 11672 /* bits */ 32, 11673 /* flags */ 0, 11674 }, 11675 #endif /* chips */ 11676 11677 #if defined(BCM_53540_A0) 11678 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_09_BCM53540_A0fmt */ 11679 /* format DESCRIPTOR_TX_09fmt */ 11680 /* nFields */ 1, 11681 /* *fields */ soc_DESCRIPTOR_TX_09_BCM53400_A0fmt_fields, 11682 /* bits */ 32, 11683 /* flags */ 0, 11684 }, 11685 #endif /* chips */ 11686 11687 #if defined(BCM_53570_A0) 11688 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_09_BCM53570_A0fmt */ 11689 /* format DESCRIPTOR_TX_09fmt */ 11690 /* nFields */ 1, 11691 /* *fields */ soc_DESCRIPTOR_TX_09_BCM53400_A0fmt_fields, 11692 /* bits */ 32, 11693 /* flags */ 0, 11694 }, 11695 #endif /* chips */ 11696 11697 #if defined(BCM_53570_B0) 11698 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_09_BCM53570_B0fmt */ 11699 /* format DESCRIPTOR_TX_09fmt */ 11700 /* nFields */ 1, 11701 /* *fields */ soc_DESCRIPTOR_TX_09_BCM53400_A0fmt_fields, 11702 /* bits */ 32, 11703 /* flags */ 0, 11704 }, 11705 #endif /* chips */ 11706 11707 #if defined(BCM_56150_A0) 11708 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_09_BCM56150_A0fmt */ 11709 /* format DESCRIPTOR_TX_09fmt */ 11710 /* nFields */ 1, 11711 /* *fields */ soc_DESCRIPTOR_TX_09_BCM56640_A0fmt_fields, 11712 /* bits */ 32, 11713 /* flags */ 0, 11714 }, 11715 #endif /* chips */ 11716 11717 #if defined(BCM_56160_A0) 11718 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_09_BCM56160_A0fmt */ 11719 /* format DESCRIPTOR_TX_09fmt */ 11720 /* nFields */ 1, 11721 /* *fields */ soc_DESCRIPTOR_TX_09_BCM53400_A0fmt_fields, 11722 /* bits */ 32, 11723 /* flags */ 0, 11724 }, 11725 #endif /* chips */ 11726 11727 #if defined(BCM_56260_A0) 11728 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_09_BCM56260_A0fmt */ 11729 /* format DESCRIPTOR_TX_09fmt */ 11730 /* nFields */ 1, 11731 /* *fields */ soc_DESCRIPTOR_TX_09_BCM53400_A0fmt_fields, 11732 /* bits */ 32, 11733 /* flags */ 0, 11734 }, 11735 #endif /* chips */ 11736 11737 #if defined(BCM_56260_B0) 11738 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_09_BCM56260_B0fmt */ 11739 /* format DESCRIPTOR_TX_09fmt */ 11740 /* nFields */ 1, 11741 /* *fields */ soc_DESCRIPTOR_TX_09_BCM53400_A0fmt_fields, 11742 /* bits */ 32, 11743 /* flags */ 0, 11744 }, 11745 #endif /* chips */ 11746 11747 #if defined(BCM_56270_A0) 11748 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_09_BCM56270_A0fmt */ 11749 /* format DESCRIPTOR_TX_09fmt */ 11750 /* nFields */ 1, 11751 /* *fields */ soc_DESCRIPTOR_TX_09_BCM53400_A0fmt_fields, 11752 /* bits */ 32, 11753 /* flags */ 0, 11754 }, 11755 #endif /* chips */ 11756 11757 #if defined(BCM_56340_A0) 11758 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_09_BCM56340_A0fmt */ 11759 /* format DESCRIPTOR_TX_09fmt */ 11760 /* nFields */ 1, 11761 /* *fields */ soc_DESCRIPTOR_TX_09_BCM56640_A0fmt_fields, 11762 /* bits */ 32, 11763 /* flags */ 0, 11764 }, 11765 #endif /* chips */ 11766 11767 #if defined(BCM_56450_A0) 11768 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_09_BCM56450_A0fmt */ 11769 /* format DESCRIPTOR_TX_09fmt */ 11770 /* nFields */ 1, 11771 /* *fields */ soc_DESCRIPTOR_TX_09_BCM56640_A0fmt_fields, 11772 /* bits */ 32, 11773 /* flags */ 0, 11774 }, 11775 #endif /* chips */ 11776 11777 #if defined(BCM_56450_B0) 11778 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_09_BCM56450_B0fmt */ 11779 /* format DESCRIPTOR_TX_09fmt */ 11780 /* nFields */ 1, 11781 /* *fields */ soc_DESCRIPTOR_TX_09_BCM56640_A0fmt_fields, 11782 /* bits */ 32, 11783 /* flags */ 0, 11784 }, 11785 #endif /* chips */ 11786 11787 #if defined(BCM_56450_B1) 11788 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_09_BCM56450_B1fmt */ 11789 /* format DESCRIPTOR_TX_09fmt */ 11790 /* nFields */ 1, 11791 /* *fields */ soc_DESCRIPTOR_TX_09_BCM56640_A0fmt_fields, 11792 /* bits */ 32, 11793 /* flags */ 0, 11794 }, 11795 #endif /* chips */ 11796 11797 #if defined(BCM_56560_A0) 11798 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_09_BCM56560_A0fmt */ 11799 /* format DESCRIPTOR_TX_09fmt */ 11800 /* nFields */ 1, 11801 /* *fields */ soc_DESCRIPTOR_TX_09_BCM53400_A0fmt_fields, 11802 /* bits */ 32, 11803 /* flags */ 0, 11804 }, 11805 #endif /* chips */ 11806 11807 #if defined(BCM_56560_B0) 11808 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_09_BCM56560_B0fmt */ 11809 /* format DESCRIPTOR_TX_09fmt */ 11810 /* nFields */ 1, 11811 /* *fields */ soc_DESCRIPTOR_TX_09_BCM53400_A0fmt_fields, 11812 /* bits */ 32, 11813 /* flags */ 0, 11814 }, 11815 #endif /* chips */ 11816 11817 #if defined(BCM_56640_A0) 11818 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_09_BCM56640_A0fmt */ 11819 /* format DESCRIPTOR_TX_09fmt */ 11820 /* nFields */ 1, 11821 /* *fields */ soc_DESCRIPTOR_TX_09_BCM56640_A0fmt_fields, 11822 /* bits */ 32, 11823 /* flags */ 0, 11824 }, 11825 #endif /* chips */ 11826 11827 #if defined(BCM_56670_A0) 11828 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_09_BCM56670_A0fmt */ 11829 /* format DESCRIPTOR_TX_09fmt */ 11830 /* nFields */ 1, 11831 /* *fields */ soc_DESCRIPTOR_TX_09_BCM53400_A0fmt_fields, 11832 /* bits */ 32, 11833 /* flags */ 0, 11834 }, 11835 #endif /* chips */ 11836 11837 #if defined(BCM_56670_B0) 11838 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_09_BCM56670_B0fmt */ 11839 /* format DESCRIPTOR_TX_09fmt */ 11840 /* nFields */ 1, 11841 /* *fields */ soc_DESCRIPTOR_TX_09_BCM53400_A0fmt_fields, 11842 /* bits */ 32, 11843 /* flags */ 0, 11844 }, 11845 #endif /* chips */ 11846 11847 #if defined(BCM_56850_A0) 11848 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_09_BCM56850_A0fmt */ 11849 /* format DESCRIPTOR_TX_09fmt */ 11850 /* nFields */ 1, 11851 /* *fields */ soc_DESCRIPTOR_TX_09_BCM56640_A0fmt_fields, 11852 /* bits */ 32, 11853 /* flags */ 0, 11854 }, 11855 #endif /* chips */ 11856 11857 #if defined(BCM_56860_A0) 11858 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_09_BCM56860_A0fmt */ 11859 /* format DESCRIPTOR_TX_09fmt */ 11860 /* nFields */ 1, 11861 /* *fields */ soc_DESCRIPTOR_TX_09_BCM56640_A0fmt_fields, 11862 /* bits */ 32, 11863 /* flags */ 0, 11864 }, 11865 #endif /* chips */ 11866 11867 #if defined(BCM_56960_A0) 11868 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_09_BCM56960_A0fmt */ 11869 /* format DESCRIPTOR_TX_09fmt */ 11870 /* nFields */ 1, 11871 /* *fields */ soc_DESCRIPTOR_TX_09_BCM53400_A0fmt_fields, 11872 /* bits */ 32, 11873 /* flags */ 0, 11874 }, 11875 #endif /* chips */ 11876 11877 #if defined(BCM_56965_A0) 11878 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_09_BCM56965_A0fmt */ 11879 /* format DESCRIPTOR_TX_09fmt */ 11880 /* nFields */ 1, 11881 /* *fields */ soc_DESCRIPTOR_TX_09_BCM53400_A0fmt_fields, 11882 /* bits */ 32, 11883 /* flags */ 0, 11884 }, 11885 #endif /* chips */ 11886 11887 #if defined(BCM_56970_A0) 11888 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_09_BCM56970_A0fmt */ 11889 /* format DESCRIPTOR_TX_09fmt */ 11890 /* nFields */ 1, 11891 /* *fields */ soc_DESCRIPTOR_TX_09_BCM53400_A0fmt_fields, 11892 /* bits */ 32, 11893 /* flags */ 0, 11894 }, 11895 #endif /* chips */ 11896 11897 #if defined(BCM_53400_A0) 11898 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_10_BCM53400_A0fmt */ 11899 /* format DESCRIPTOR_TX_10fmt */ 11900 /* nFields */ 1, 11901 /* *fields */ soc_DESCRIPTOR_TX_10_BCM53400_A0fmt_fields, 11902 /* bits */ 32, 11903 /* flags */ 0, 11904 }, 11905 #endif /* chips */ 11906 11907 #if defined(BCM_53540_A0) 11908 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_10_BCM53540_A0fmt */ 11909 /* format DESCRIPTOR_TX_10fmt */ 11910 /* nFields */ 1, 11911 /* *fields */ soc_DESCRIPTOR_TX_10_BCM53400_A0fmt_fields, 11912 /* bits */ 32, 11913 /* flags */ 0, 11914 }, 11915 #endif /* chips */ 11916 11917 #if defined(BCM_53570_A0) 11918 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_10_BCM53570_A0fmt */ 11919 /* format DESCRIPTOR_TX_10fmt */ 11920 /* nFields */ 1, 11921 /* *fields */ soc_DESCRIPTOR_TX_10_BCM53400_A0fmt_fields, 11922 /* bits */ 32, 11923 /* flags */ 0, 11924 }, 11925 #endif /* chips */ 11926 11927 #if defined(BCM_53570_B0) 11928 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_10_BCM53570_B0fmt */ 11929 /* format DESCRIPTOR_TX_10fmt */ 11930 /* nFields */ 1, 11931 /* *fields */ soc_DESCRIPTOR_TX_10_BCM53400_A0fmt_fields, 11932 /* bits */ 32, 11933 /* flags */ 0, 11934 }, 11935 #endif /* chips */ 11936 11937 #if defined(BCM_56142_A0) 11938 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_10_BCM56142_A0fmt */ 11939 /* format DESCRIPTOR_TX_10fmt */ 11940 /* nFields */ 1, 11941 /* *fields */ soc_DESCRIPTOR_TX_10_BCM56624_A0fmt_fields, 11942 /* bits */ 32, 11943 /* flags */ 0, 11944 }, 11945 #endif /* chips */ 11946 11947 #if defined(BCM_56150_A0) 11948 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_10_BCM56150_A0fmt */ 11949 /* format DESCRIPTOR_TX_10fmt */ 11950 /* nFields */ 1, 11951 /* *fields */ soc_DESCRIPTOR_TX_10_BCM56640_A0fmt_fields, 11952 /* bits */ 32, 11953 /* flags */ 0, 11954 }, 11955 #endif /* chips */ 11956 11957 #if defined(BCM_56160_A0) 11958 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_10_BCM56160_A0fmt */ 11959 /* format DESCRIPTOR_TX_10fmt */ 11960 /* nFields */ 1, 11961 /* *fields */ soc_DESCRIPTOR_TX_10_BCM53400_A0fmt_fields, 11962 /* bits */ 32, 11963 /* flags */ 0, 11964 }, 11965 #endif /* chips */ 11966 11967 #if defined(BCM_56260_A0) 11968 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_10_BCM56260_A0fmt */ 11969 /* format DESCRIPTOR_TX_10fmt */ 11970 /* nFields */ 1, 11971 /* *fields */ soc_DESCRIPTOR_TX_10_BCM53400_A0fmt_fields, 11972 /* bits */ 32, 11973 /* flags */ 0, 11974 }, 11975 #endif /* chips */ 11976 11977 #if defined(BCM_56260_B0) 11978 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_10_BCM56260_B0fmt */ 11979 /* format DESCRIPTOR_TX_10fmt */ 11980 /* nFields */ 1, 11981 /* *fields */ soc_DESCRIPTOR_TX_10_BCM53400_A0fmt_fields, 11982 /* bits */ 32, 11983 /* flags */ 0, 11984 }, 11985 #endif /* chips */ 11986 11987 #if defined(BCM_56270_A0) 11988 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_10_BCM56270_A0fmt */ 11989 /* format DESCRIPTOR_TX_10fmt */ 11990 /* nFields */ 1, 11991 /* *fields */ soc_DESCRIPTOR_TX_10_BCM53400_A0fmt_fields, 11992 /* bits */ 32, 11993 /* flags */ 0, 11994 }, 11995 #endif /* chips */ 11996 11997 #if defined(BCM_56334_A0) 11998 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_10_BCM56334_A0fmt */ 11999 /* format DESCRIPTOR_TX_10fmt */ 12000 /* nFields */ 1, 12001 /* *fields */ soc_DESCRIPTOR_TX_10_BCM56624_A0fmt_fields, 12002 /* bits */ 32, 12003 /* flags */ 0, 12004 }, 12005 #endif /* chips */ 12006 12007 #if defined(BCM_56334_B0) 12008 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_10_BCM56334_B0fmt */ 12009 /* format DESCRIPTOR_TX_10fmt */ 12010 /* nFields */ 1, 12011 /* *fields */ soc_DESCRIPTOR_TX_10_BCM56624_A0fmt_fields, 12012 /* bits */ 32, 12013 /* flags */ 0, 12014 }, 12015 #endif /* chips */ 12016 12017 #if defined(BCM_56340_A0) 12018 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_10_BCM56340_A0fmt */ 12019 /* format DESCRIPTOR_TX_10fmt */ 12020 /* nFields */ 1, 12021 /* *fields */ soc_DESCRIPTOR_TX_10_BCM56640_A0fmt_fields, 12022 /* bits */ 32, 12023 /* flags */ 0, 12024 }, 12025 #endif /* chips */ 12026 12027 #if defined(BCM_56440_A0) 12028 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_10_BCM56440_A0fmt */ 12029 /* format DESCRIPTOR_TX_10fmt */ 12030 /* nFields */ 1, 12031 /* *fields */ soc_DESCRIPTOR_TX_10_BCM56624_A0fmt_fields, 12032 /* bits */ 32, 12033 /* flags */ 0, 12034 }, 12035 #endif /* chips */ 12036 12037 #if defined(BCM_56440_B0) 12038 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_10_BCM56440_B0fmt */ 12039 /* format DESCRIPTOR_TX_10fmt */ 12040 /* nFields */ 1, 12041 /* *fields */ soc_DESCRIPTOR_TX_10_BCM56624_A0fmt_fields, 12042 /* bits */ 32, 12043 /* flags */ 0, 12044 }, 12045 #endif /* chips */ 12046 12047 #if defined(BCM_56450_A0) 12048 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_10_BCM56450_A0fmt */ 12049 /* format DESCRIPTOR_TX_10fmt */ 12050 /* nFields */ 1, 12051 /* *fields */ soc_DESCRIPTOR_TX_10_BCM56640_A0fmt_fields, 12052 /* bits */ 32, 12053 /* flags */ 0, 12054 }, 12055 #endif /* chips */ 12056 12057 #if defined(BCM_56450_B0) 12058 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_10_BCM56450_B0fmt */ 12059 /* format DESCRIPTOR_TX_10fmt */ 12060 /* nFields */ 1, 12061 /* *fields */ soc_DESCRIPTOR_TX_10_BCM56640_A0fmt_fields, 12062 /* bits */ 32, 12063 /* flags */ 0, 12064 }, 12065 #endif /* chips */ 12066 12067 #if defined(BCM_56450_B1) 12068 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_10_BCM56450_B1fmt */ 12069 /* format DESCRIPTOR_TX_10fmt */ 12070 /* nFields */ 1, 12071 /* *fields */ soc_DESCRIPTOR_TX_10_BCM56640_A0fmt_fields, 12072 /* bits */ 32, 12073 /* flags */ 0, 12074 }, 12075 #endif /* chips */ 12076 12077 #if defined(BCM_56524_A0) 12078 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_10_BCM56524_A0fmt */ 12079 /* format DESCRIPTOR_TX_10fmt */ 12080 /* nFields */ 1, 12081 /* *fields */ soc_DESCRIPTOR_TX_10_BCM56624_A0fmt_fields, 12082 /* bits */ 32, 12083 /* flags */ 0, 12084 }, 12085 #endif /* chips */ 12086 12087 #if defined(BCM_56524_B0) 12088 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_10_BCM56524_B0fmt */ 12089 /* format DESCRIPTOR_TX_10fmt */ 12090 /* nFields */ 1, 12091 /* *fields */ soc_DESCRIPTOR_TX_10_BCM56624_A0fmt_fields, 12092 /* bits */ 32, 12093 /* flags */ 0, 12094 }, 12095 #endif /* chips */ 12096 12097 #if defined(BCM_56560_A0) 12098 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_10_BCM56560_A0fmt */ 12099 /* format DESCRIPTOR_TX_10fmt */ 12100 /* nFields */ 1, 12101 /* *fields */ soc_DESCRIPTOR_TX_10_BCM53400_A0fmt_fields, 12102 /* bits */ 32, 12103 /* flags */ 0, 12104 }, 12105 #endif /* chips */ 12106 12107 #if defined(BCM_56560_B0) 12108 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_10_BCM56560_B0fmt */ 12109 /* format DESCRIPTOR_TX_10fmt */ 12110 /* nFields */ 1, 12111 /* *fields */ soc_DESCRIPTOR_TX_10_BCM53400_A0fmt_fields, 12112 /* bits */ 32, 12113 /* flags */ 0, 12114 }, 12115 #endif /* chips */ 12116 12117 #if defined(BCM_56624_A0) 12118 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_10_BCM56624_A0fmt */ 12119 /* format DESCRIPTOR_TX_10fmt */ 12120 /* nFields */ 1, 12121 /* *fields */ soc_DESCRIPTOR_TX_10_BCM56624_A0fmt_fields, 12122 /* bits */ 32, 12123 /* flags */ 0, 12124 }, 12125 #endif /* chips */ 12126 12127 #if defined(BCM_56624_B0) 12128 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_10_BCM56624_B0fmt */ 12129 /* format DESCRIPTOR_TX_10fmt */ 12130 /* nFields */ 1, 12131 /* *fields */ soc_DESCRIPTOR_TX_10_BCM56624_A0fmt_fields, 12132 /* bits */ 32, 12133 /* flags */ 0, 12134 }, 12135 #endif /* chips */ 12136 12137 #if defined(BCM_56634_A0) 12138 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_10_BCM56634_A0fmt */ 12139 /* format DESCRIPTOR_TX_10fmt */ 12140 /* nFields */ 1, 12141 /* *fields */ soc_DESCRIPTOR_TX_10_BCM56624_A0fmt_fields, 12142 /* bits */ 32, 12143 /* flags */ 0, 12144 }, 12145 #endif /* chips */ 12146 12147 #if defined(BCM_56634_B0) 12148 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_10_BCM56634_B0fmt */ 12149 /* format DESCRIPTOR_TX_10fmt */ 12150 /* nFields */ 1, 12151 /* *fields */ soc_DESCRIPTOR_TX_10_BCM56624_A0fmt_fields, 12152 /* bits */ 32, 12153 /* flags */ 0, 12154 }, 12155 #endif /* chips */ 12156 12157 #if defined(BCM_56640_A0) 12158 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_10_BCM56640_A0fmt */ 12159 /* format DESCRIPTOR_TX_10fmt */ 12160 /* nFields */ 1, 12161 /* *fields */ soc_DESCRIPTOR_TX_10_BCM56640_A0fmt_fields, 12162 /* bits */ 32, 12163 /* flags */ 0, 12164 }, 12165 #endif /* chips */ 12166 12167 #if defined(BCM_56670_A0) 12168 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_10_BCM56670_A0fmt */ 12169 /* format DESCRIPTOR_TX_10fmt */ 12170 /* nFields */ 1, 12171 /* *fields */ soc_DESCRIPTOR_TX_10_BCM53400_A0fmt_fields, 12172 /* bits */ 32, 12173 /* flags */ 0, 12174 }, 12175 #endif /* chips */ 12176 12177 #if defined(BCM_56670_B0) 12178 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_10_BCM56670_B0fmt */ 12179 /* format DESCRIPTOR_TX_10fmt */ 12180 /* nFields */ 1, 12181 /* *fields */ soc_DESCRIPTOR_TX_10_BCM53400_A0fmt_fields, 12182 /* bits */ 32, 12183 /* flags */ 0, 12184 }, 12185 #endif /* chips */ 12186 12187 #if defined(BCM_56680_A0) 12188 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_10_BCM56680_A0fmt */ 12189 /* format DESCRIPTOR_TX_10fmt */ 12190 /* nFields */ 1, 12191 /* *fields */ soc_DESCRIPTOR_TX_10_BCM56624_A0fmt_fields, 12192 /* bits */ 32, 12193 /* flags */ 0, 12194 }, 12195 #endif /* chips */ 12196 12197 #if defined(BCM_56680_B0) 12198 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_10_BCM56680_B0fmt */ 12199 /* format DESCRIPTOR_TX_10fmt */ 12200 /* nFields */ 1, 12201 /* *fields */ soc_DESCRIPTOR_TX_10_BCM56624_A0fmt_fields, 12202 /* bits */ 32, 12203 /* flags */ 0, 12204 }, 12205 #endif /* chips */ 12206 12207 #if defined(BCM_56685_A0) 12208 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_10_BCM56685_A0fmt */ 12209 /* format DESCRIPTOR_TX_10fmt */ 12210 /* nFields */ 1, 12211 /* *fields */ soc_DESCRIPTOR_TX_10_BCM56624_A0fmt_fields, 12212 /* bits */ 32, 12213 /* flags */ 0, 12214 }, 12215 #endif /* chips */ 12216 12217 #if defined(BCM_56685_B0) 12218 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_10_BCM56685_B0fmt */ 12219 /* format DESCRIPTOR_TX_10fmt */ 12220 /* nFields */ 1, 12221 /* *fields */ soc_DESCRIPTOR_TX_10_BCM56624_A0fmt_fields, 12222 /* bits */ 32, 12223 /* flags */ 0, 12224 }, 12225 #endif /* chips */ 12226 12227 #if defined(BCM_56725_A0) 12228 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_10_BCM56725_A0fmt */ 12229 /* format DESCRIPTOR_TX_10fmt */ 12230 /* nFields */ 1, 12231 /* *fields */ soc_DESCRIPTOR_TX_10_BCM56624_A0fmt_fields, 12232 /* bits */ 32, 12233 /* flags */ 0, 12234 }, 12235 #endif /* chips */ 12236 12237 #if defined(BCM_56820_A0) 12238 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_10_BCM56820_A0fmt */ 12239 /* format DESCRIPTOR_TX_10fmt */ 12240 /* nFields */ 1, 12241 /* *fields */ soc_DESCRIPTOR_TX_10_BCM56624_A0fmt_fields, 12242 /* bits */ 32, 12243 /* flags */ 0, 12244 }, 12245 #endif /* chips */ 12246 12247 #if defined(BCM_56840_A0) 12248 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_10_BCM56840_A0fmt */ 12249 /* format DESCRIPTOR_TX_10fmt */ 12250 /* nFields */ 1, 12251 /* *fields */ soc_DESCRIPTOR_TX_10_BCM56624_A0fmt_fields, 12252 /* bits */ 32, 12253 /* flags */ 0, 12254 }, 12255 #endif /* chips */ 12256 12257 #if defined(BCM_56840_B0) 12258 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_10_BCM56840_B0fmt */ 12259 /* format DESCRIPTOR_TX_10fmt */ 12260 /* nFields */ 1, 12261 /* *fields */ soc_DESCRIPTOR_TX_10_BCM56624_A0fmt_fields, 12262 /* bits */ 32, 12263 /* flags */ 0, 12264 }, 12265 #endif /* chips */ 12266 12267 #if defined(BCM_56850_A0) 12268 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_10_BCM56850_A0fmt */ 12269 /* format DESCRIPTOR_TX_10fmt */ 12270 /* nFields */ 1, 12271 /* *fields */ soc_DESCRIPTOR_TX_10_BCM56640_A0fmt_fields, 12272 /* bits */ 32, 12273 /* flags */ 0, 12274 }, 12275 #endif /* chips */ 12276 12277 #if defined(BCM_56860_A0) 12278 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_10_BCM56860_A0fmt */ 12279 /* format DESCRIPTOR_TX_10fmt */ 12280 /* nFields */ 1, 12281 /* *fields */ soc_DESCRIPTOR_TX_10_BCM56640_A0fmt_fields, 12282 /* bits */ 32, 12283 /* flags */ 0, 12284 }, 12285 #endif /* chips */ 12286 12287 #if defined(BCM_56960_A0) 12288 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_10_BCM56960_A0fmt */ 12289 /* format DESCRIPTOR_TX_10fmt */ 12290 /* nFields */ 1, 12291 /* *fields */ soc_DESCRIPTOR_TX_10_BCM53400_A0fmt_fields, 12292 /* bits */ 32, 12293 /* flags */ 0, 12294 }, 12295 #endif /* chips */ 12296 12297 #if defined(BCM_56965_A0) 12298 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_10_BCM56965_A0fmt */ 12299 /* format DESCRIPTOR_TX_10fmt */ 12300 /* nFields */ 1, 12301 /* *fields */ soc_DESCRIPTOR_TX_10_BCM53400_A0fmt_fields, 12302 /* bits */ 32, 12303 /* flags */ 0, 12304 }, 12305 #endif /* chips */ 12306 12307 #if defined(BCM_56970_A0) 12308 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_10_BCM56970_A0fmt */ 12309 /* format DESCRIPTOR_TX_10fmt */ 12310 /* nFields */ 1, 12311 /* *fields */ soc_DESCRIPTOR_TX_10_BCM53400_A0fmt_fields, 12312 /* bits */ 32, 12313 /* flags */ 0, 12314 }, 12315 #endif /* chips */ 12316 12317 #if defined(BCM_88732_A0) 12318 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_10_BCM88732_A0fmt */ 12319 /* format DESCRIPTOR_TX_10fmt */ 12320 /* nFields */ 1, 12321 /* *fields */ soc_DESCRIPTOR_TX_10_BCM56624_A0fmt_fields, 12322 /* bits */ 32, 12323 /* flags */ 0, 12324 }, 12325 #endif /* chips */ 12326 12327 #if defined(BCM_53400_A0) 12328 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_11_BCM53400_A0fmt */ 12329 /* format DESCRIPTOR_TX_11fmt */ 12330 /* nFields */ 1, 12331 /* *fields */ soc_DESCRIPTOR_TX_11_BCM53400_A0fmt_fields, 12332 /* bits */ 32, 12333 /* flags */ 0, 12334 }, 12335 #endif /* chips */ 12336 12337 #if defined(BCM_53540_A0) 12338 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_11_BCM53540_A0fmt */ 12339 /* format DESCRIPTOR_TX_11fmt */ 12340 /* nFields */ 1, 12341 /* *fields */ soc_DESCRIPTOR_TX_11_BCM53400_A0fmt_fields, 12342 /* bits */ 32, 12343 /* flags */ 0, 12344 }, 12345 #endif /* chips */ 12346 12347 #if defined(BCM_53570_A0) 12348 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_11_BCM53570_A0fmt */ 12349 /* format DESCRIPTOR_TX_11fmt */ 12350 /* nFields */ 1, 12351 /* *fields */ soc_DESCRIPTOR_TX_11_BCM53400_A0fmt_fields, 12352 /* bits */ 32, 12353 /* flags */ 0, 12354 }, 12355 #endif /* chips */ 12356 12357 #if defined(BCM_53570_B0) 12358 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_11_BCM53570_B0fmt */ 12359 /* format DESCRIPTOR_TX_11fmt */ 12360 /* nFields */ 1, 12361 /* *fields */ soc_DESCRIPTOR_TX_11_BCM53400_A0fmt_fields, 12362 /* bits */ 32, 12363 /* flags */ 0, 12364 }, 12365 #endif /* chips */ 12366 12367 #if defined(BCM_56150_A0) 12368 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_11_BCM56150_A0fmt */ 12369 /* format DESCRIPTOR_TX_11fmt */ 12370 /* nFields */ 1, 12371 /* *fields */ soc_DESCRIPTOR_TX_11_BCM56640_A0fmt_fields, 12372 /* bits */ 32, 12373 /* flags */ 0, 12374 }, 12375 #endif /* chips */ 12376 12377 #if defined(BCM_56160_A0) 12378 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_11_BCM56160_A0fmt */ 12379 /* format DESCRIPTOR_TX_11fmt */ 12380 /* nFields */ 1, 12381 /* *fields */ soc_DESCRIPTOR_TX_11_BCM53400_A0fmt_fields, 12382 /* bits */ 32, 12383 /* flags */ 0, 12384 }, 12385 #endif /* chips */ 12386 12387 #if defined(BCM_56260_A0) 12388 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_11_BCM56260_A0fmt */ 12389 /* format DESCRIPTOR_TX_11fmt */ 12390 /* nFields */ 1, 12391 /* *fields */ soc_DESCRIPTOR_TX_11_BCM53400_A0fmt_fields, 12392 /* bits */ 32, 12393 /* flags */ 0, 12394 }, 12395 #endif /* chips */ 12396 12397 #if defined(BCM_56260_B0) 12398 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_11_BCM56260_B0fmt */ 12399 /* format DESCRIPTOR_TX_11fmt */ 12400 /* nFields */ 1, 12401 /* *fields */ soc_DESCRIPTOR_TX_11_BCM53400_A0fmt_fields, 12402 /* bits */ 32, 12403 /* flags */ 0, 12404 }, 12405 #endif /* chips */ 12406 12407 #if defined(BCM_56270_A0) 12408 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_11_BCM56270_A0fmt */ 12409 /* format DESCRIPTOR_TX_11fmt */ 12410 /* nFields */ 1, 12411 /* *fields */ soc_DESCRIPTOR_TX_11_BCM53400_A0fmt_fields, 12412 /* bits */ 32, 12413 /* flags */ 0, 12414 }, 12415 #endif /* chips */ 12416 12417 #if defined(BCM_56340_A0) 12418 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_11_BCM56340_A0fmt */ 12419 /* format DESCRIPTOR_TX_11fmt */ 12420 /* nFields */ 1, 12421 /* *fields */ soc_DESCRIPTOR_TX_11_BCM56640_A0fmt_fields, 12422 /* bits */ 32, 12423 /* flags */ 0, 12424 }, 12425 #endif /* chips */ 12426 12427 #if defined(BCM_56450_A0) 12428 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_11_BCM56450_A0fmt */ 12429 /* format DESCRIPTOR_TX_11fmt */ 12430 /* nFields */ 1, 12431 /* *fields */ soc_DESCRIPTOR_TX_11_BCM56640_A0fmt_fields, 12432 /* bits */ 32, 12433 /* flags */ 0, 12434 }, 12435 #endif /* chips */ 12436 12437 #if defined(BCM_56450_B0) 12438 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_11_BCM56450_B0fmt */ 12439 /* format DESCRIPTOR_TX_11fmt */ 12440 /* nFields */ 1, 12441 /* *fields */ soc_DESCRIPTOR_TX_11_BCM56640_A0fmt_fields, 12442 /* bits */ 32, 12443 /* flags */ 0, 12444 }, 12445 #endif /* chips */ 12446 12447 #if defined(BCM_56450_B1) 12448 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_11_BCM56450_B1fmt */ 12449 /* format DESCRIPTOR_TX_11fmt */ 12450 /* nFields */ 1, 12451 /* *fields */ soc_DESCRIPTOR_TX_11_BCM56640_A0fmt_fields, 12452 /* bits */ 32, 12453 /* flags */ 0, 12454 }, 12455 #endif /* chips */ 12456 12457 #if defined(BCM_56560_A0) 12458 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_11_BCM56560_A0fmt */ 12459 /* format DESCRIPTOR_TX_11fmt */ 12460 /* nFields */ 1, 12461 /* *fields */ soc_DESCRIPTOR_TX_11_BCM53400_A0fmt_fields, 12462 /* bits */ 32, 12463 /* flags */ 0, 12464 }, 12465 #endif /* chips */ 12466 12467 #if defined(BCM_56560_B0) 12468 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_11_BCM56560_B0fmt */ 12469 /* format DESCRIPTOR_TX_11fmt */ 12470 /* nFields */ 1, 12471 /* *fields */ soc_DESCRIPTOR_TX_11_BCM53400_A0fmt_fields, 12472 /* bits */ 32, 12473 /* flags */ 0, 12474 }, 12475 #endif /* chips */ 12476 12477 #if defined(BCM_56640_A0) 12478 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_11_BCM56640_A0fmt */ 12479 /* format DESCRIPTOR_TX_11fmt */ 12480 /* nFields */ 1, 12481 /* *fields */ soc_DESCRIPTOR_TX_11_BCM56640_A0fmt_fields, 12482 /* bits */ 32, 12483 /* flags */ 0, 12484 }, 12485 #endif /* chips */ 12486 12487 #if defined(BCM_56670_A0) 12488 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_11_BCM56670_A0fmt */ 12489 /* format DESCRIPTOR_TX_11fmt */ 12490 /* nFields */ 1, 12491 /* *fields */ soc_DESCRIPTOR_TX_11_BCM53400_A0fmt_fields, 12492 /* bits */ 32, 12493 /* flags */ 0, 12494 }, 12495 #endif /* chips */ 12496 12497 #if defined(BCM_56670_B0) 12498 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_11_BCM56670_B0fmt */ 12499 /* format DESCRIPTOR_TX_11fmt */ 12500 /* nFields */ 1, 12501 /* *fields */ soc_DESCRIPTOR_TX_11_BCM53400_A0fmt_fields, 12502 /* bits */ 32, 12503 /* flags */ 0, 12504 }, 12505 #endif /* chips */ 12506 12507 #if defined(BCM_56850_A0) 12508 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_11_BCM56850_A0fmt */ 12509 /* format DESCRIPTOR_TX_11fmt */ 12510 /* nFields */ 1, 12511 /* *fields */ soc_DESCRIPTOR_TX_11_BCM56640_A0fmt_fields, 12512 /* bits */ 32, 12513 /* flags */ 0, 12514 }, 12515 #endif /* chips */ 12516 12517 #if defined(BCM_56860_A0) 12518 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_11_BCM56860_A0fmt */ 12519 /* format DESCRIPTOR_TX_11fmt */ 12520 /* nFields */ 1, 12521 /* *fields */ soc_DESCRIPTOR_TX_11_BCM56640_A0fmt_fields, 12522 /* bits */ 32, 12523 /* flags */ 0, 12524 }, 12525 #endif /* chips */ 12526 12527 #if defined(BCM_56960_A0) 12528 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_11_BCM56960_A0fmt */ 12529 /* format DESCRIPTOR_TX_11fmt */ 12530 /* nFields */ 1, 12531 /* *fields */ soc_DESCRIPTOR_TX_11_BCM53400_A0fmt_fields, 12532 /* bits */ 32, 12533 /* flags */ 0, 12534 }, 12535 #endif /* chips */ 12536 12537 #if defined(BCM_56965_A0) 12538 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_11_BCM56965_A0fmt */ 12539 /* format DESCRIPTOR_TX_11fmt */ 12540 /* nFields */ 1, 12541 /* *fields */ soc_DESCRIPTOR_TX_11_BCM53400_A0fmt_fields, 12542 /* bits */ 32, 12543 /* flags */ 0, 12544 }, 12545 #endif /* chips */ 12546 12547 #if defined(BCM_56970_A0) 12548 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_11_BCM56970_A0fmt */ 12549 /* format DESCRIPTOR_TX_11fmt */ 12550 /* nFields */ 1, 12551 /* *fields */ soc_DESCRIPTOR_TX_11_BCM53400_A0fmt_fields, 12552 /* bits */ 32, 12553 /* flags */ 0, 12554 }, 12555 #endif /* chips */ 12556 12557 #if defined(BCM_88732_A0) 12558 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_11_BCM88732_A0fmt */ 12559 /* format DESCRIPTOR_TX_11fmt */ 12560 /* nFields */ 1, 12561 /* *fields */ soc_DESCRIPTOR_TX_11fmt_fields, 12562 /* bits */ 32, 12563 /* flags */ 0, 12564 }, 12565 #endif /* chips */ 12566 12567 #if defined(BCM_53400_A0) 12568 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_12_BCM53400_A0fmt */ 12569 /* format DESCRIPTOR_TX_12fmt */ 12570 /* nFields */ 1, 12571 /* *fields */ soc_DESCRIPTOR_TX_12_BCM53400_A0fmt_fields, 12572 /* bits */ 32, 12573 /* flags */ 0, 12574 }, 12575 #endif /* chips */ 12576 12577 #if defined(BCM_53540_A0) 12578 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_12_BCM53540_A0fmt */ 12579 /* format DESCRIPTOR_TX_12fmt */ 12580 /* nFields */ 1, 12581 /* *fields */ soc_DESCRIPTOR_TX_12_BCM53400_A0fmt_fields, 12582 /* bits */ 32, 12583 /* flags */ 0, 12584 }, 12585 #endif /* chips */ 12586 12587 #if defined(BCM_53570_A0) 12588 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_12_BCM53570_A0fmt */ 12589 /* format DESCRIPTOR_TX_12fmt */ 12590 /* nFields */ 1, 12591 /* *fields */ soc_DESCRIPTOR_TX_12_BCM53400_A0fmt_fields, 12592 /* bits */ 32, 12593 /* flags */ 0, 12594 }, 12595 #endif /* chips */ 12596 12597 #if defined(BCM_53570_B0) 12598 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_12_BCM53570_B0fmt */ 12599 /* format DESCRIPTOR_TX_12fmt */ 12600 /* nFields */ 1, 12601 /* *fields */ soc_DESCRIPTOR_TX_12_BCM53400_A0fmt_fields, 12602 /* bits */ 32, 12603 /* flags */ 0, 12604 }, 12605 #endif /* chips */ 12606 12607 #if defined(BCM_56150_A0) 12608 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_12_BCM56150_A0fmt */ 12609 /* format DESCRIPTOR_TX_12fmt */ 12610 /* nFields */ 1, 12611 /* *fields */ soc_DESCRIPTOR_TX_12_BCM56640_A0fmt_fields, 12612 /* bits */ 32, 12613 /* flags */ 0, 12614 }, 12615 #endif /* chips */ 12616 12617 #if defined(BCM_56160_A0) 12618 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_12_BCM56160_A0fmt */ 12619 /* format DESCRIPTOR_TX_12fmt */ 12620 /* nFields */ 1, 12621 /* *fields */ soc_DESCRIPTOR_TX_12_BCM53400_A0fmt_fields, 12622 /* bits */ 32, 12623 /* flags */ 0, 12624 }, 12625 #endif /* chips */ 12626 12627 #if defined(BCM_56260_A0) 12628 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_12_BCM56260_A0fmt */ 12629 /* format DESCRIPTOR_TX_12fmt */ 12630 /* nFields */ 1, 12631 /* *fields */ soc_DESCRIPTOR_TX_12_BCM53400_A0fmt_fields, 12632 /* bits */ 32, 12633 /* flags */ 0, 12634 }, 12635 #endif /* chips */ 12636 12637 #if defined(BCM_56260_B0) 12638 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_12_BCM56260_B0fmt */ 12639 /* format DESCRIPTOR_TX_12fmt */ 12640 /* nFields */ 1, 12641 /* *fields */ soc_DESCRIPTOR_TX_12_BCM53400_A0fmt_fields, 12642 /* bits */ 32, 12643 /* flags */ 0, 12644 }, 12645 #endif /* chips */ 12646 12647 #if defined(BCM_56270_A0) 12648 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_12_BCM56270_A0fmt */ 12649 /* format DESCRIPTOR_TX_12fmt */ 12650 /* nFields */ 1, 12651 /* *fields */ soc_DESCRIPTOR_TX_12_BCM53400_A0fmt_fields, 12652 /* bits */ 32, 12653 /* flags */ 0, 12654 }, 12655 #endif /* chips */ 12656 12657 #if defined(BCM_56340_A0) 12658 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_12_BCM56340_A0fmt */ 12659 /* format DESCRIPTOR_TX_12fmt */ 12660 /* nFields */ 1, 12661 /* *fields */ soc_DESCRIPTOR_TX_12_BCM56640_A0fmt_fields, 12662 /* bits */ 32, 12663 /* flags */ 0, 12664 }, 12665 #endif /* chips */ 12666 12667 #if defined(BCM_56450_A0) 12668 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_12_BCM56450_A0fmt */ 12669 /* format DESCRIPTOR_TX_12fmt */ 12670 /* nFields */ 1, 12671 /* *fields */ soc_DESCRIPTOR_TX_12_BCM56640_A0fmt_fields, 12672 /* bits */ 32, 12673 /* flags */ 0, 12674 }, 12675 #endif /* chips */ 12676 12677 #if defined(BCM_56450_B0) 12678 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_12_BCM56450_B0fmt */ 12679 /* format DESCRIPTOR_TX_12fmt */ 12680 /* nFields */ 1, 12681 /* *fields */ soc_DESCRIPTOR_TX_12_BCM56640_A0fmt_fields, 12682 /* bits */ 32, 12683 /* flags */ 0, 12684 }, 12685 #endif /* chips */ 12686 12687 #if defined(BCM_56450_B1) 12688 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_12_BCM56450_B1fmt */ 12689 /* format DESCRIPTOR_TX_12fmt */ 12690 /* nFields */ 1, 12691 /* *fields */ soc_DESCRIPTOR_TX_12_BCM56640_A0fmt_fields, 12692 /* bits */ 32, 12693 /* flags */ 0, 12694 }, 12695 #endif /* chips */ 12696 12697 #if defined(BCM_56560_A0) 12698 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_12_BCM56560_A0fmt */ 12699 /* format DESCRIPTOR_TX_12fmt */ 12700 /* nFields */ 1, 12701 /* *fields */ soc_DESCRIPTOR_TX_12_BCM53400_A0fmt_fields, 12702 /* bits */ 32, 12703 /* flags */ 0, 12704 }, 12705 #endif /* chips */ 12706 12707 #if defined(BCM_56560_B0) 12708 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_12_BCM56560_B0fmt */ 12709 /* format DESCRIPTOR_TX_12fmt */ 12710 /* nFields */ 1, 12711 /* *fields */ soc_DESCRIPTOR_TX_12_BCM53400_A0fmt_fields, 12712 /* bits */ 32, 12713 /* flags */ 0, 12714 }, 12715 #endif /* chips */ 12716 12717 #if defined(BCM_56640_A0) 12718 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_12_BCM56640_A0fmt */ 12719 /* format DESCRIPTOR_TX_12fmt */ 12720 /* nFields */ 1, 12721 /* *fields */ soc_DESCRIPTOR_TX_12_BCM56640_A0fmt_fields, 12722 /* bits */ 32, 12723 /* flags */ 0, 12724 }, 12725 #endif /* chips */ 12726 12727 #if defined(BCM_56670_A0) 12728 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_12_BCM56670_A0fmt */ 12729 /* format DESCRIPTOR_TX_12fmt */ 12730 /* nFields */ 1, 12731 /* *fields */ soc_DESCRIPTOR_TX_12_BCM53400_A0fmt_fields, 12732 /* bits */ 32, 12733 /* flags */ 0, 12734 }, 12735 #endif /* chips */ 12736 12737 #if defined(BCM_56670_B0) 12738 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_12_BCM56670_B0fmt */ 12739 /* format DESCRIPTOR_TX_12fmt */ 12740 /* nFields */ 1, 12741 /* *fields */ soc_DESCRIPTOR_TX_12_BCM53400_A0fmt_fields, 12742 /* bits */ 32, 12743 /* flags */ 0, 12744 }, 12745 #endif /* chips */ 12746 12747 #if defined(BCM_56850_A0) 12748 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_12_BCM56850_A0fmt */ 12749 /* format DESCRIPTOR_TX_12fmt */ 12750 /* nFields */ 1, 12751 /* *fields */ soc_DESCRIPTOR_TX_12_BCM56640_A0fmt_fields, 12752 /* bits */ 32, 12753 /* flags */ 0, 12754 }, 12755 #endif /* chips */ 12756 12757 #if defined(BCM_56860_A0) 12758 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_12_BCM56860_A0fmt */ 12759 /* format DESCRIPTOR_TX_12fmt */ 12760 /* nFields */ 1, 12761 /* *fields */ soc_DESCRIPTOR_TX_12_BCM56640_A0fmt_fields, 12762 /* bits */ 32, 12763 /* flags */ 0, 12764 }, 12765 #endif /* chips */ 12766 12767 #if defined(BCM_56960_A0) 12768 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_12_BCM56960_A0fmt */ 12769 /* format DESCRIPTOR_TX_12fmt */ 12770 /* nFields */ 1, 12771 /* *fields */ soc_DESCRIPTOR_TX_12_BCM53400_A0fmt_fields, 12772 /* bits */ 32, 12773 /* flags */ 0, 12774 }, 12775 #endif /* chips */ 12776 12777 #if defined(BCM_56965_A0) 12778 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_12_BCM56965_A0fmt */ 12779 /* format DESCRIPTOR_TX_12fmt */ 12780 /* nFields */ 1, 12781 /* *fields */ soc_DESCRIPTOR_TX_12_BCM53400_A0fmt_fields, 12782 /* bits */ 32, 12783 /* flags */ 0, 12784 }, 12785 #endif /* chips */ 12786 12787 #if defined(BCM_56970_A0) 12788 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_12_BCM56970_A0fmt */ 12789 /* format DESCRIPTOR_TX_12fmt */ 12790 /* nFields */ 1, 12791 /* *fields */ soc_DESCRIPTOR_TX_12_BCM53400_A0fmt_fields, 12792 /* bits */ 32, 12793 /* flags */ 0, 12794 }, 12795 #endif /* chips */ 12796 12797 #if defined(BCM_88732_A0) 12798 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_12_BCM88732_A0fmt */ 12799 /* format DESCRIPTOR_TX_12fmt */ 12800 /* nFields */ 1, 12801 /* *fields */ soc_DESCRIPTOR_TX_12fmt_fields, 12802 /* bits */ 32, 12803 /* flags */ 0, 12804 }, 12805 #endif /* chips */ 12806 12807 #if defined(BCM_53400_A0) 12808 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_13_BCM53400_A0fmt */ 12809 /* format DESCRIPTOR_TX_13fmt */ 12810 /* nFields */ 1, 12811 /* *fields */ soc_DESCRIPTOR_TX_13_BCM53400_A0fmt_fields, 12812 /* bits */ 32, 12813 /* flags */ 0, 12814 }, 12815 #endif /* chips */ 12816 12817 #if defined(BCM_53540_A0) 12818 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_13_BCM53540_A0fmt */ 12819 /* format DESCRIPTOR_TX_13fmt */ 12820 /* nFields */ 1, 12821 /* *fields */ soc_DESCRIPTOR_TX_13_BCM53400_A0fmt_fields, 12822 /* bits */ 32, 12823 /* flags */ 0, 12824 }, 12825 #endif /* chips */ 12826 12827 #if defined(BCM_53570_A0) 12828 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_13_BCM53570_A0fmt */ 12829 /* format DESCRIPTOR_TX_13fmt */ 12830 /* nFields */ 1, 12831 /* *fields */ soc_DESCRIPTOR_TX_13_BCM53400_A0fmt_fields, 12832 /* bits */ 32, 12833 /* flags */ 0, 12834 }, 12835 #endif /* chips */ 12836 12837 #if defined(BCM_53570_B0) 12838 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_13_BCM53570_B0fmt */ 12839 /* format DESCRIPTOR_TX_13fmt */ 12840 /* nFields */ 1, 12841 /* *fields */ soc_DESCRIPTOR_TX_13_BCM53400_A0fmt_fields, 12842 /* bits */ 32, 12843 /* flags */ 0, 12844 }, 12845 #endif /* chips */ 12846 12847 #if defined(BCM_56150_A0) 12848 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_13_BCM56150_A0fmt */ 12849 /* format DESCRIPTOR_TX_13fmt */ 12850 /* nFields */ 1, 12851 /* *fields */ soc_DESCRIPTOR_TX_13_BCM56640_A0fmt_fields, 12852 /* bits */ 32, 12853 /* flags */ 0, 12854 }, 12855 #endif /* chips */ 12856 12857 #if defined(BCM_56160_A0) 12858 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_13_BCM56160_A0fmt */ 12859 /* format DESCRIPTOR_TX_13fmt */ 12860 /* nFields */ 1, 12861 /* *fields */ soc_DESCRIPTOR_TX_13_BCM53400_A0fmt_fields, 12862 /* bits */ 32, 12863 /* flags */ 0, 12864 }, 12865 #endif /* chips */ 12866 12867 #if defined(BCM_56260_A0) 12868 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_13_BCM56260_A0fmt */ 12869 /* format DESCRIPTOR_TX_13fmt */ 12870 /* nFields */ 1, 12871 /* *fields */ soc_DESCRIPTOR_TX_13_BCM53400_A0fmt_fields, 12872 /* bits */ 32, 12873 /* flags */ 0, 12874 }, 12875 #endif /* chips */ 12876 12877 #if defined(BCM_56260_B0) 12878 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_13_BCM56260_B0fmt */ 12879 /* format DESCRIPTOR_TX_13fmt */ 12880 /* nFields */ 1, 12881 /* *fields */ soc_DESCRIPTOR_TX_13_BCM53400_A0fmt_fields, 12882 /* bits */ 32, 12883 /* flags */ 0, 12884 }, 12885 #endif /* chips */ 12886 12887 #if defined(BCM_56270_A0) 12888 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_13_BCM56270_A0fmt */ 12889 /* format DESCRIPTOR_TX_13fmt */ 12890 /* nFields */ 1, 12891 /* *fields */ soc_DESCRIPTOR_TX_13_BCM53400_A0fmt_fields, 12892 /* bits */ 32, 12893 /* flags */ 0, 12894 }, 12895 #endif /* chips */ 12896 12897 #if defined(BCM_56340_A0) 12898 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_13_BCM56340_A0fmt */ 12899 /* format DESCRIPTOR_TX_13fmt */ 12900 /* nFields */ 1, 12901 /* *fields */ soc_DESCRIPTOR_TX_13_BCM56640_A0fmt_fields, 12902 /* bits */ 32, 12903 /* flags */ 0, 12904 }, 12905 #endif /* chips */ 12906 12907 #if defined(BCM_56450_A0) 12908 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_13_BCM56450_A0fmt */ 12909 /* format DESCRIPTOR_TX_13fmt */ 12910 /* nFields */ 1, 12911 /* *fields */ soc_DESCRIPTOR_TX_13_BCM56640_A0fmt_fields, 12912 /* bits */ 32, 12913 /* flags */ 0, 12914 }, 12915 #endif /* chips */ 12916 12917 #if defined(BCM_56450_B0) 12918 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_13_BCM56450_B0fmt */ 12919 /* format DESCRIPTOR_TX_13fmt */ 12920 /* nFields */ 1, 12921 /* *fields */ soc_DESCRIPTOR_TX_13_BCM56640_A0fmt_fields, 12922 /* bits */ 32, 12923 /* flags */ 0, 12924 }, 12925 #endif /* chips */ 12926 12927 #if defined(BCM_56450_B1) 12928 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_13_BCM56450_B1fmt */ 12929 /* format DESCRIPTOR_TX_13fmt */ 12930 /* nFields */ 1, 12931 /* *fields */ soc_DESCRIPTOR_TX_13_BCM56640_A0fmt_fields, 12932 /* bits */ 32, 12933 /* flags */ 0, 12934 }, 12935 #endif /* chips */ 12936 12937 #if defined(BCM_56560_A0) 12938 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_13_BCM56560_A0fmt */ 12939 /* format DESCRIPTOR_TX_13fmt */ 12940 /* nFields */ 1, 12941 /* *fields */ soc_DESCRIPTOR_TX_13_BCM53400_A0fmt_fields, 12942 /* bits */ 32, 12943 /* flags */ 0, 12944 }, 12945 #endif /* chips */ 12946 12947 #if defined(BCM_56560_B0) 12948 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_13_BCM56560_B0fmt */ 12949 /* format DESCRIPTOR_TX_13fmt */ 12950 /* nFields */ 1, 12951 /* *fields */ soc_DESCRIPTOR_TX_13_BCM53400_A0fmt_fields, 12952 /* bits */ 32, 12953 /* flags */ 0, 12954 }, 12955 #endif /* chips */ 12956 12957 #if defined(BCM_56640_A0) 12958 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_13_BCM56640_A0fmt */ 12959 /* format DESCRIPTOR_TX_13fmt */ 12960 /* nFields */ 1, 12961 /* *fields */ soc_DESCRIPTOR_TX_13_BCM56640_A0fmt_fields, 12962 /* bits */ 32, 12963 /* flags */ 0, 12964 }, 12965 #endif /* chips */ 12966 12967 #if defined(BCM_56670_A0) 12968 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_13_BCM56670_A0fmt */ 12969 /* format DESCRIPTOR_TX_13fmt */ 12970 /* nFields */ 1, 12971 /* *fields */ soc_DESCRIPTOR_TX_13_BCM53400_A0fmt_fields, 12972 /* bits */ 32, 12973 /* flags */ 0, 12974 }, 12975 #endif /* chips */ 12976 12977 #if defined(BCM_56670_B0) 12978 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_13_BCM56670_B0fmt */ 12979 /* format DESCRIPTOR_TX_13fmt */ 12980 /* nFields */ 1, 12981 /* *fields */ soc_DESCRIPTOR_TX_13_BCM53400_A0fmt_fields, 12982 /* bits */ 32, 12983 /* flags */ 0, 12984 }, 12985 #endif /* chips */ 12986 12987 #if defined(BCM_56850_A0) 12988 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_13_BCM56850_A0fmt */ 12989 /* format DESCRIPTOR_TX_13fmt */ 12990 /* nFields */ 1, 12991 /* *fields */ soc_DESCRIPTOR_TX_13_BCM56640_A0fmt_fields, 12992 /* bits */ 32, 12993 /* flags */ 0, 12994 }, 12995 #endif /* chips */ 12996 12997 #if defined(BCM_56860_A0) 12998 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_13_BCM56860_A0fmt */ 12999 /* format DESCRIPTOR_TX_13fmt */ 13000 /* nFields */ 1, 13001 /* *fields */ soc_DESCRIPTOR_TX_13_BCM56640_A0fmt_fields, 13002 /* bits */ 32, 13003 /* flags */ 0, 13004 }, 13005 #endif /* chips */ 13006 13007 #if defined(BCM_56960_A0) 13008 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_13_BCM56960_A0fmt */ 13009 /* format DESCRIPTOR_TX_13fmt */ 13010 /* nFields */ 1, 13011 /* *fields */ soc_DESCRIPTOR_TX_13_BCM53400_A0fmt_fields, 13012 /* bits */ 32, 13013 /* flags */ 0, 13014 }, 13015 #endif /* chips */ 13016 13017 #if defined(BCM_56965_A0) 13018 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_13_BCM56965_A0fmt */ 13019 /* format DESCRIPTOR_TX_13fmt */ 13020 /* nFields */ 1, 13021 /* *fields */ soc_DESCRIPTOR_TX_13_BCM53400_A0fmt_fields, 13022 /* bits */ 32, 13023 /* flags */ 0, 13024 }, 13025 #endif /* chips */ 13026 13027 #if defined(BCM_56970_A0) 13028 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_13_BCM56970_A0fmt */ 13029 /* format DESCRIPTOR_TX_13fmt */ 13030 /* nFields */ 1, 13031 /* *fields */ soc_DESCRIPTOR_TX_13_BCM53400_A0fmt_fields, 13032 /* bits */ 32, 13033 /* flags */ 0, 13034 }, 13035 #endif /* chips */ 13036 13037 #if defined(BCM_53400_A0) 13038 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_14_BCM53400_A0fmt */ 13039 /* format DESCRIPTOR_TX_14fmt */ 13040 /* nFields */ 1, 13041 /* *fields */ soc_DESCRIPTOR_TX_14_BCM53400_A0fmt_fields, 13042 /* bits */ 32, 13043 /* flags */ 0, 13044 }, 13045 #endif /* chips */ 13046 13047 #if defined(BCM_53540_A0) 13048 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_14_BCM53540_A0fmt */ 13049 /* format DESCRIPTOR_TX_14fmt */ 13050 /* nFields */ 1, 13051 /* *fields */ soc_DESCRIPTOR_TX_14_BCM53400_A0fmt_fields, 13052 /* bits */ 32, 13053 /* flags */ 0, 13054 }, 13055 #endif /* chips */ 13056 13057 #if defined(BCM_53570_A0) 13058 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_14_BCM53570_A0fmt */ 13059 /* format DESCRIPTOR_TX_14fmt */ 13060 /* nFields */ 1, 13061 /* *fields */ soc_DESCRIPTOR_TX_14_BCM53400_A0fmt_fields, 13062 /* bits */ 32, 13063 /* flags */ 0, 13064 }, 13065 #endif /* chips */ 13066 13067 #if defined(BCM_53570_B0) 13068 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_14_BCM53570_B0fmt */ 13069 /* format DESCRIPTOR_TX_14fmt */ 13070 /* nFields */ 1, 13071 /* *fields */ soc_DESCRIPTOR_TX_14_BCM53400_A0fmt_fields, 13072 /* bits */ 32, 13073 /* flags */ 0, 13074 }, 13075 #endif /* chips */ 13076 13077 #if defined(BCM_56150_A0) 13078 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_14_BCM56150_A0fmt */ 13079 /* format DESCRIPTOR_TX_14fmt */ 13080 /* nFields */ 1, 13081 /* *fields */ soc_DESCRIPTOR_TX_14_BCM56640_A0fmt_fields, 13082 /* bits */ 32, 13083 /* flags */ 0, 13084 }, 13085 #endif /* chips */ 13086 13087 #if defined(BCM_56160_A0) 13088 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_14_BCM56160_A0fmt */ 13089 /* format DESCRIPTOR_TX_14fmt */ 13090 /* nFields */ 1, 13091 /* *fields */ soc_DESCRIPTOR_TX_14_BCM53400_A0fmt_fields, 13092 /* bits */ 32, 13093 /* flags */ 0, 13094 }, 13095 #endif /* chips */ 13096 13097 #if defined(BCM_56260_A0) 13098 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_14_BCM56260_A0fmt */ 13099 /* format DESCRIPTOR_TX_14fmt */ 13100 /* nFields */ 1, 13101 /* *fields */ soc_DESCRIPTOR_TX_14_BCM53400_A0fmt_fields, 13102 /* bits */ 32, 13103 /* flags */ 0, 13104 }, 13105 #endif /* chips */ 13106 13107 #if defined(BCM_56260_B0) 13108 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_14_BCM56260_B0fmt */ 13109 /* format DESCRIPTOR_TX_14fmt */ 13110 /* nFields */ 1, 13111 /* *fields */ soc_DESCRIPTOR_TX_14_BCM53400_A0fmt_fields, 13112 /* bits */ 32, 13113 /* flags */ 0, 13114 }, 13115 #endif /* chips */ 13116 13117 #if defined(BCM_56270_A0) 13118 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_14_BCM56270_A0fmt */ 13119 /* format DESCRIPTOR_TX_14fmt */ 13120 /* nFields */ 1, 13121 /* *fields */ soc_DESCRIPTOR_TX_14_BCM53400_A0fmt_fields, 13122 /* bits */ 32, 13123 /* flags */ 0, 13124 }, 13125 #endif /* chips */ 13126 13127 #if defined(BCM_56340_A0) 13128 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_14_BCM56340_A0fmt */ 13129 /* format DESCRIPTOR_TX_14fmt */ 13130 /* nFields */ 1, 13131 /* *fields */ soc_DESCRIPTOR_TX_14_BCM56640_A0fmt_fields, 13132 /* bits */ 32, 13133 /* flags */ 0, 13134 }, 13135 #endif /* chips */ 13136 13137 #if defined(BCM_56450_A0) 13138 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_14_BCM56450_A0fmt */ 13139 /* format DESCRIPTOR_TX_14fmt */ 13140 /* nFields */ 1, 13141 /* *fields */ soc_DESCRIPTOR_TX_14_BCM56640_A0fmt_fields, 13142 /* bits */ 32, 13143 /* flags */ 0, 13144 }, 13145 #endif /* chips */ 13146 13147 #if defined(BCM_56450_B0) 13148 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_14_BCM56450_B0fmt */ 13149 /* format DESCRIPTOR_TX_14fmt */ 13150 /* nFields */ 1, 13151 /* *fields */ soc_DESCRIPTOR_TX_14_BCM56640_A0fmt_fields, 13152 /* bits */ 32, 13153 /* flags */ 0, 13154 }, 13155 #endif /* chips */ 13156 13157 #if defined(BCM_56450_B1) 13158 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_14_BCM56450_B1fmt */ 13159 /* format DESCRIPTOR_TX_14fmt */ 13160 /* nFields */ 1, 13161 /* *fields */ soc_DESCRIPTOR_TX_14_BCM56640_A0fmt_fields, 13162 /* bits */ 32, 13163 /* flags */ 0, 13164 }, 13165 #endif /* chips */ 13166 13167 #if defined(BCM_56560_A0) 13168 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_14_BCM56560_A0fmt */ 13169 /* format DESCRIPTOR_TX_14fmt */ 13170 /* nFields */ 1, 13171 /* *fields */ soc_DESCRIPTOR_TX_14_BCM53400_A0fmt_fields, 13172 /* bits */ 32, 13173 /* flags */ 0, 13174 }, 13175 #endif /* chips */ 13176 13177 #if defined(BCM_56560_B0) 13178 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_14_BCM56560_B0fmt */ 13179 /* format DESCRIPTOR_TX_14fmt */ 13180 /* nFields */ 1, 13181 /* *fields */ soc_DESCRIPTOR_TX_14_BCM53400_A0fmt_fields, 13182 /* bits */ 32, 13183 /* flags */ 0, 13184 }, 13185 #endif /* chips */ 13186 13187 #if defined(BCM_56640_A0) 13188 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_14_BCM56640_A0fmt */ 13189 /* format DESCRIPTOR_TX_14fmt */ 13190 /* nFields */ 1, 13191 /* *fields */ soc_DESCRIPTOR_TX_14_BCM56640_A0fmt_fields, 13192 /* bits */ 32, 13193 /* flags */ 0, 13194 }, 13195 #endif /* chips */ 13196 13197 #if defined(BCM_56670_A0) 13198 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_14_BCM56670_A0fmt */ 13199 /* format DESCRIPTOR_TX_14fmt */ 13200 /* nFields */ 1, 13201 /* *fields */ soc_DESCRIPTOR_TX_14_BCM53400_A0fmt_fields, 13202 /* bits */ 32, 13203 /* flags */ 0, 13204 }, 13205 #endif /* chips */ 13206 13207 #if defined(BCM_56670_B0) 13208 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_14_BCM56670_B0fmt */ 13209 /* format DESCRIPTOR_TX_14fmt */ 13210 /* nFields */ 1, 13211 /* *fields */ soc_DESCRIPTOR_TX_14_BCM53400_A0fmt_fields, 13212 /* bits */ 32, 13213 /* flags */ 0, 13214 }, 13215 #endif /* chips */ 13216 13217 #if defined(BCM_56850_A0) 13218 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_14_BCM56850_A0fmt */ 13219 /* format DESCRIPTOR_TX_14fmt */ 13220 /* nFields */ 1, 13221 /* *fields */ soc_DESCRIPTOR_TX_14_BCM56640_A0fmt_fields, 13222 /* bits */ 32, 13223 /* flags */ 0, 13224 }, 13225 #endif /* chips */ 13226 13227 #if defined(BCM_56860_A0) 13228 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_14_BCM56860_A0fmt */ 13229 /* format DESCRIPTOR_TX_14fmt */ 13230 /* nFields */ 1, 13231 /* *fields */ soc_DESCRIPTOR_TX_14_BCM56640_A0fmt_fields, 13232 /* bits */ 32, 13233 /* flags */ 0, 13234 }, 13235 #endif /* chips */ 13236 13237 #if defined(BCM_56960_A0) 13238 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_14_BCM56960_A0fmt */ 13239 /* format DESCRIPTOR_TX_14fmt */ 13240 /* nFields */ 1, 13241 /* *fields */ soc_DESCRIPTOR_TX_14_BCM53400_A0fmt_fields, 13242 /* bits */ 32, 13243 /* flags */ 0, 13244 }, 13245 #endif /* chips */ 13246 13247 #if defined(BCM_56965_A0) 13248 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_14_BCM56965_A0fmt */ 13249 /* format DESCRIPTOR_TX_14fmt */ 13250 /* nFields */ 1, 13251 /* *fields */ soc_DESCRIPTOR_TX_14_BCM53400_A0fmt_fields, 13252 /* bits */ 32, 13253 /* flags */ 0, 13254 }, 13255 #endif /* chips */ 13256 13257 #if defined(BCM_56970_A0) 13258 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_14_BCM56970_A0fmt */ 13259 /* format DESCRIPTOR_TX_14fmt */ 13260 /* nFields */ 1, 13261 /* *fields */ soc_DESCRIPTOR_TX_14_BCM53400_A0fmt_fields, 13262 /* bits */ 32, 13263 /* flags */ 0, 13264 }, 13265 #endif /* chips */ 13266 13267 #if defined(BCM_53400_A0) 13268 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_15_BCM53400_A0fmt */ 13269 /* format DESCRIPTOR_TX_15fmt */ 13270 /* nFields */ 2, 13271 /* *fields */ soc_DESCRIPTOR_TX_15_BCM53400_A0fmt_fields, 13272 /* bits */ 32, 13273 /* flags */ 0, 13274 }, 13275 #endif /* chips */ 13276 13277 #if defined(BCM_53540_A0) 13278 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_15_BCM53540_A0fmt */ 13279 /* format DESCRIPTOR_TX_15fmt */ 13280 /* nFields */ 2, 13281 /* *fields */ soc_DESCRIPTOR_TX_15_BCM53400_A0fmt_fields, 13282 /* bits */ 32, 13283 /* flags */ 0, 13284 }, 13285 #endif /* chips */ 13286 13287 #if defined(BCM_53570_A0) 13288 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_15_BCM53570_A0fmt */ 13289 /* format DESCRIPTOR_TX_15fmt */ 13290 /* nFields */ 2, 13291 /* *fields */ soc_DESCRIPTOR_TX_15_BCM53400_A0fmt_fields, 13292 /* bits */ 32, 13293 /* flags */ 0, 13294 }, 13295 #endif /* chips */ 13296 13297 #if defined(BCM_53570_B0) 13298 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_15_BCM53570_B0fmt */ 13299 /* format DESCRIPTOR_TX_15fmt */ 13300 /* nFields */ 2, 13301 /* *fields */ soc_DESCRIPTOR_TX_15_BCM53400_A0fmt_fields, 13302 /* bits */ 32, 13303 /* flags */ 0, 13304 }, 13305 #endif /* chips */ 13306 13307 #if defined(BCM_56150_A0) 13308 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_15_BCM56150_A0fmt */ 13309 /* format DESCRIPTOR_TX_15fmt */ 13310 /* nFields */ 2, 13311 /* *fields */ soc_DESCRIPTOR_TX_15_BCM56640_A0fmt_fields, 13312 /* bits */ 32, 13313 /* flags */ 0, 13314 }, 13315 #endif /* chips */ 13316 13317 #if defined(BCM_56160_A0) 13318 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_15_BCM56160_A0fmt */ 13319 /* format DESCRIPTOR_TX_15fmt */ 13320 /* nFields */ 2, 13321 /* *fields */ soc_DESCRIPTOR_TX_15_BCM53400_A0fmt_fields, 13322 /* bits */ 32, 13323 /* flags */ 0, 13324 }, 13325 #endif /* chips */ 13326 13327 #if defined(BCM_56260_A0) 13328 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_15_BCM56260_A0fmt */ 13329 /* format DESCRIPTOR_TX_15fmt */ 13330 /* nFields */ 2, 13331 /* *fields */ soc_DESCRIPTOR_TX_15_BCM53400_A0fmt_fields, 13332 /* bits */ 32, 13333 /* flags */ 0, 13334 }, 13335 #endif /* chips */ 13336 13337 #if defined(BCM_56260_B0) 13338 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_15_BCM56260_B0fmt */ 13339 /* format DESCRIPTOR_TX_15fmt */ 13340 /* nFields */ 2, 13341 /* *fields */ soc_DESCRIPTOR_TX_15_BCM53400_A0fmt_fields, 13342 /* bits */ 32, 13343 /* flags */ 0, 13344 }, 13345 #endif /* chips */ 13346 13347 #if defined(BCM_56270_A0) 13348 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_15_BCM56270_A0fmt */ 13349 /* format DESCRIPTOR_TX_15fmt */ 13350 /* nFields */ 2, 13351 /* *fields */ soc_DESCRIPTOR_TX_15_BCM53400_A0fmt_fields, 13352 /* bits */ 32, 13353 /* flags */ 0, 13354 }, 13355 #endif /* chips */ 13356 13357 #if defined(BCM_56340_A0) 13358 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_15_BCM56340_A0fmt */ 13359 /* format DESCRIPTOR_TX_15fmt */ 13360 /* nFields */ 2, 13361 /* *fields */ soc_DESCRIPTOR_TX_15_BCM56640_A0fmt_fields, 13362 /* bits */ 32, 13363 /* flags */ 0, 13364 }, 13365 #endif /* chips */ 13366 13367 #if defined(BCM_56450_A0) 13368 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_15_BCM56450_A0fmt */ 13369 /* format DESCRIPTOR_TX_15fmt */ 13370 /* nFields */ 2, 13371 /* *fields */ soc_DESCRIPTOR_TX_15_BCM56640_A0fmt_fields, 13372 /* bits */ 32, 13373 /* flags */ 0, 13374 }, 13375 #endif /* chips */ 13376 13377 #if defined(BCM_56450_B0) 13378 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_15_BCM56450_B0fmt */ 13379 /* format DESCRIPTOR_TX_15fmt */ 13380 /* nFields */ 2, 13381 /* *fields */ soc_DESCRIPTOR_TX_15_BCM56640_A0fmt_fields, 13382 /* bits */ 32, 13383 /* flags */ 0, 13384 }, 13385 #endif /* chips */ 13386 13387 #if defined(BCM_56450_B1) 13388 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_15_BCM56450_B1fmt */ 13389 /* format DESCRIPTOR_TX_15fmt */ 13390 /* nFields */ 2, 13391 /* *fields */ soc_DESCRIPTOR_TX_15_BCM56640_A0fmt_fields, 13392 /* bits */ 32, 13393 /* flags */ 0, 13394 }, 13395 #endif /* chips */ 13396 13397 #if defined(BCM_56560_A0) 13398 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_15_BCM56560_A0fmt */ 13399 /* format DESCRIPTOR_TX_15fmt */ 13400 /* nFields */ 2, 13401 /* *fields */ soc_DESCRIPTOR_TX_15_BCM53400_A0fmt_fields, 13402 /* bits */ 32, 13403 /* flags */ 0, 13404 }, 13405 #endif /* chips */ 13406 13407 #if defined(BCM_56560_B0) 13408 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_15_BCM56560_B0fmt */ 13409 /* format DESCRIPTOR_TX_15fmt */ 13410 /* nFields */ 2, 13411 /* *fields */ soc_DESCRIPTOR_TX_15_BCM53400_A0fmt_fields, 13412 /* bits */ 32, 13413 /* flags */ 0, 13414 }, 13415 #endif /* chips */ 13416 13417 #if defined(BCM_56640_A0) 13418 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_15_BCM56640_A0fmt */ 13419 /* format DESCRIPTOR_TX_15fmt */ 13420 /* nFields */ 2, 13421 /* *fields */ soc_DESCRIPTOR_TX_15_BCM56640_A0fmt_fields, 13422 /* bits */ 32, 13423 /* flags */ 0, 13424 }, 13425 #endif /* chips */ 13426 13427 #if defined(BCM_56670_A0) 13428 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_15_BCM56670_A0fmt */ 13429 /* format DESCRIPTOR_TX_15fmt */ 13430 /* nFields */ 2, 13431 /* *fields */ soc_DESCRIPTOR_TX_15_BCM53400_A0fmt_fields, 13432 /* bits */ 32, 13433 /* flags */ 0, 13434 }, 13435 #endif /* chips */ 13436 13437 #if defined(BCM_56670_B0) 13438 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_15_BCM56670_B0fmt */ 13439 /* format DESCRIPTOR_TX_15fmt */ 13440 /* nFields */ 2, 13441 /* *fields */ soc_DESCRIPTOR_TX_15_BCM53400_A0fmt_fields, 13442 /* bits */ 32, 13443 /* flags */ 0, 13444 }, 13445 #endif /* chips */ 13446 13447 #if defined(BCM_56850_A0) 13448 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_15_BCM56850_A0fmt */ 13449 /* format DESCRIPTOR_TX_15fmt */ 13450 /* nFields */ 2, 13451 /* *fields */ soc_DESCRIPTOR_TX_15_BCM56640_A0fmt_fields, 13452 /* bits */ 32, 13453 /* flags */ 0, 13454 }, 13455 #endif /* chips */ 13456 13457 #if defined(BCM_56860_A0) 13458 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_15_BCM56860_A0fmt */ 13459 /* format DESCRIPTOR_TX_15fmt */ 13460 /* nFields */ 2, 13461 /* *fields */ soc_DESCRIPTOR_TX_15_BCM56640_A0fmt_fields, 13462 /* bits */ 32, 13463 /* flags */ 0, 13464 }, 13465 #endif /* chips */ 13466 13467 #if defined(BCM_56960_A0) 13468 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_15_BCM56960_A0fmt */ 13469 /* format DESCRIPTOR_TX_15fmt */ 13470 /* nFields */ 2, 13471 /* *fields */ soc_DESCRIPTOR_TX_15_BCM53400_A0fmt_fields, 13472 /* bits */ 32, 13473 /* flags */ 0, 13474 }, 13475 #endif /* chips */ 13476 13477 #if defined(BCM_56965_A0) 13478 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_15_BCM56965_A0fmt */ 13479 /* format DESCRIPTOR_TX_15fmt */ 13480 /* nFields */ 2, 13481 /* *fields */ soc_DESCRIPTOR_TX_15_BCM53400_A0fmt_fields, 13482 /* bits */ 32, 13483 /* flags */ 0, 13484 }, 13485 #endif /* chips */ 13486 13487 #if defined(BCM_56970_A0) 13488 { /* SOC_FORMAT_INT_DESCRIPTOR_TX_15_BCM56970_A0fmt */ 13489 /* format DESCRIPTOR_TX_15fmt */ 13490 /* nFields */ 2, 13491 /* *fields */ soc_DESCRIPTOR_TX_15_BCM53400_A0fmt_fields, 13492 /* bits */ 32, 13493 /* flags */ 0, 13494 }, 13495 #endif /* chips */ 13496 13497 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) 13498 { /* SOC_FORMAT_INT_DESTINATION_FORMATfmt */ 13499 /* format DESTINATION_FORMATfmt */ 13500 /* nFields */ 17, 13501 /* *fields */ soc_DESTINATION_FORMATfmt_fields, 13502 /* bits */ 18, 13503 /* flags */ 0, 13504 }, 13505 #endif /* chips */ 13506 13507 #if defined(BCM_56370_A0) 13508 { /* SOC_FORMAT_INT_DESTINATION_FORMAT_BCM56370_A0fmt */ 13509 /* format DESTINATION_FORMATfmt */ 13510 /* nFields */ 18, 13511 /* *fields */ soc_DESTINATION_FORMAT_BCM56370_A0fmt_fields, 13512 /* bits */ 18, 13513 /* flags */ 0, 13514 }, 13515 #endif /* chips */ 13516 13517 #if defined(BCM_56860_A0) 13518 { /* SOC_FORMAT_INT_DESTINATION_MY_STATIONfmt */ 13519 /* format DESTINATION_MY_STATIONfmt */ 13520 /* nFields */ 10, 13521 /* *fields */ soc_DESTINATION_MY_STATIONfmt_fields, 13522 /* bits */ 10, 13523 /* flags */ 0, 13524 }, 13525 #endif /* chips */ 13526 13527 #if defined(BCM_56560_A0) 13528 { /* SOC_FORMAT_INT_DESTINATION_MY_STATION_BCM56560_A0fmt */ 13529 /* format DESTINATION_MY_STATIONfmt */ 13530 /* nFields */ 10, 13531 /* *fields */ soc_DESTINATION_MY_STATION_BCM56560_A0fmt_fields, 13532 /* bits */ 10, 13533 /* flags */ 0, 13534 }, 13535 #endif /* chips */ 13536 13537 #if defined(BCM_56560_B0) 13538 { /* SOC_FORMAT_INT_DESTINATION_MY_STATION_BCM56560_B0fmt */ 13539 /* format DESTINATION_MY_STATIONfmt */ 13540 /* nFields */ 10, 13541 /* *fields */ soc_DESTINATION_MY_STATION_BCM56560_A0fmt_fields, 13542 /* bits */ 10, 13543 /* flags */ 0, 13544 }, 13545 #endif /* chips */ 13546 13547 #if defined(BCM_56670_A0) 13548 { /* SOC_FORMAT_INT_DESTINATION_MY_STATION_BCM56670_A0fmt */ 13549 /* format DESTINATION_MY_STATIONfmt */ 13550 /* nFields */ 10, 13551 /* *fields */ soc_DESTINATION_MY_STATION_BCM56560_A0fmt_fields, 13552 /* bits */ 10, 13553 /* flags */ 0, 13554 }, 13555 #endif /* chips */ 13556 13557 #if defined(BCM_56670_B0) 13558 { /* SOC_FORMAT_INT_DESTINATION_MY_STATION_BCM56670_B0fmt */ 13559 /* format DESTINATION_MY_STATIONfmt */ 13560 /* nFields */ 10, 13561 /* *fields */ soc_DESTINATION_MY_STATION_BCM56560_A0fmt_fields, 13562 /* bits */ 10, 13563 /* flags */ 0, 13564 }, 13565 #endif /* chips */ 13566 13567 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 13568 defined(BCM_56870_A0) 13569 { /* SOC_FORMAT_INT_DISCARD_PROC_DROP_VECTORfmt */ 13570 /* format DISCARD_PROC_DROP_VECTORfmt */ 13571 /* nFields */ 15, 13572 /* *fields */ soc_DISCARD_PROC_DROP_VECTORfmt_fields, 13573 /* bits */ 16, 13574 /* flags */ 0, 13575 }, 13576 #endif /* chips */ 13577 13578 #if defined(BCM_56980_A0) 13579 { /* SOC_FORMAT_INT_DISCARD_PROC_DROP_VECTOR_BCM56980_A0fmt */ 13580 /* format DISCARD_PROC_DROP_VECTORfmt */ 13581 /* nFields */ 8, 13582 /* *fields */ soc_DISCARD_PROC_DROP_VECTOR_BCM56980_A0fmt_fields, 13583 /* bits */ 8, 13584 /* flags */ 0, 13585 }, 13586 #endif /* chips */ 13587 13588 #if defined(BCM_56980_B0) 13589 { /* SOC_FORMAT_INT_DISCARD_PROC_DROP_VECTOR_BCM56980_B0fmt */ 13590 /* format DISCARD_PROC_DROP_VECTORfmt */ 13591 /* nFields */ 8, 13592 /* *fields */ soc_DISCARD_PROC_DROP_VECTOR_BCM56980_A0fmt_fields, 13593 /* bits */ 8, 13594 /* flags */ 0, 13595 }, 13596 #endif /* chips */ 13597 13598 #if defined(BCM_56340_A0) || defined(BCM_56640_A0) || \ 13599 defined(BCM_56850_A0) || defined(BCM_56860_A0) 13600 { /* SOC_FORMAT_INT_DLB_ECMP_FLOWSET_COV_DEFSfmt */ 13601 /* format DLB_ECMP_FLOWSET_COV_DEFSfmt */ 13602 /* nFields */ 4, 13603 /* *fields */ soc_DLB_ECMP_FLOWSET_COV_DEFSfmt_fields, 13604 /* bits */ 19, 13605 /* flags */ 0, 13606 }, 13607 #endif /* chips */ 13608 13609 #if defined(BCM_56560_A0) 13610 { /* SOC_FORMAT_INT_DLB_ECMP_FLOWSET_COV_DEFS_BCM56560_A0fmt */ 13611 /* format DLB_ECMP_FLOWSET_COV_DEFSfmt */ 13612 /* nFields */ 4, 13613 /* *fields */ soc_DLB_ECMP_FLOWSET_COV_DEFS_BCM56560_A0fmt_fields, 13614 /* bits */ 19, 13615 /* flags */ 0, 13616 }, 13617 #endif /* chips */ 13618 13619 #if defined(BCM_56560_B0) 13620 { /* SOC_FORMAT_INT_DLB_ECMP_FLOWSET_COV_DEFS_BCM56560_B0fmt */ 13621 /* format DLB_ECMP_FLOWSET_COV_DEFSfmt */ 13622 /* nFields */ 4, 13623 /* *fields */ soc_DLB_ECMP_FLOWSET_COV_DEFS_BCM56560_A0fmt_fields, 13624 /* bits */ 19, 13625 /* flags */ 0, 13626 }, 13627 #endif /* chips */ 13628 13629 #if defined(BCM_56670_A0) 13630 { /* SOC_FORMAT_INT_DLB_ECMP_FLOWSET_COV_DEFS_BCM56670_A0fmt */ 13631 /* format DLB_ECMP_FLOWSET_COV_DEFSfmt */ 13632 /* nFields */ 4, 13633 /* *fields */ soc_DLB_ECMP_FLOWSET_COV_DEFS_BCM56560_A0fmt_fields, 13634 /* bits */ 19, 13635 /* flags */ 0, 13636 }, 13637 #endif /* chips */ 13638 13639 #if defined(BCM_56670_B0) 13640 { /* SOC_FORMAT_INT_DLB_ECMP_FLOWSET_COV_DEFS_BCM56670_B0fmt */ 13641 /* format DLB_ECMP_FLOWSET_COV_DEFSfmt */ 13642 /* nFields */ 4, 13643 /* *fields */ soc_DLB_ECMP_FLOWSET_COV_DEFS_BCM56560_A0fmt_fields, 13644 /* bits */ 19, 13645 /* flags */ 0, 13646 }, 13647 #endif /* chips */ 13648 13649 #if defined(BCM_56340_A0) || defined(BCM_56640_A0) || \ 13650 defined(BCM_56850_A0) || defined(BCM_56860_A0) 13651 { /* SOC_FORMAT_INT_DLB_ECMP_FLOWSET_TIMESTAMP_PAGE_COV_DEFSfmt */ 13652 /* format DLB_ECMP_FLOWSET_TIMESTAMP_PAGE_COV_DEFSfmt */ 13653 /* nFields */ 5, 13654 /* *fields */ soc_DLB_ECMP_FLOWSET_TIMESTAMP_PAGE_COV_DEFSfmt_fields, 13655 /* bits */ 15, 13656 /* flags */ 0, 13657 }, 13658 #endif /* chips */ 13659 13660 #if defined(BCM_56560_A0) 13661 { /* SOC_FORMAT_INT_DLB_ECMP_FLOWSET_TIMESTAMP_PAGE_COV_DEFS_BCM56560_A0fmt */ 13662 /* format DLB_ECMP_FLOWSET_TIMESTAMP_PAGE_COV_DEFSfmt */ 13663 /* nFields */ 5, 13664 /* *fields */ soc_DLB_ECMP_FLOWSET_TIMESTAMP_PAGE_COV_DEFS_BCM56560_A0fmt_fields, 13665 /* bits */ 15, 13666 /* flags */ 0, 13667 }, 13668 #endif /* chips */ 13669 13670 #if defined(BCM_56560_B0) 13671 { /* SOC_FORMAT_INT_DLB_ECMP_FLOWSET_TIMESTAMP_PAGE_COV_DEFS_BCM56560_B0fmt */ 13672 /* format DLB_ECMP_FLOWSET_TIMESTAMP_PAGE_COV_DEFSfmt */ 13673 /* nFields */ 5, 13674 /* *fields */ soc_DLB_ECMP_FLOWSET_TIMESTAMP_PAGE_COV_DEFS_BCM56560_A0fmt_fields, 13675 /* bits */ 15, 13676 /* flags */ 0, 13677 }, 13678 #endif /* chips */ 13679 13680 #if defined(BCM_56670_A0) 13681 { /* SOC_FORMAT_INT_DLB_ECMP_FLOWSET_TIMESTAMP_PAGE_COV_DEFS_BCM56670_A0fmt */ 13682 /* format DLB_ECMP_FLOWSET_TIMESTAMP_PAGE_COV_DEFSfmt */ 13683 /* nFields */ 5, 13684 /* *fields */ soc_DLB_ECMP_FLOWSET_TIMESTAMP_PAGE_COV_DEFS_BCM56560_A0fmt_fields, 13685 /* bits */ 15, 13686 /* flags */ 0, 13687 }, 13688 #endif /* chips */ 13689 13690 #if defined(BCM_56670_B0) 13691 { /* SOC_FORMAT_INT_DLB_ECMP_FLOWSET_TIMESTAMP_PAGE_COV_DEFS_BCM56670_B0fmt */ 13692 /* format DLB_ECMP_FLOWSET_TIMESTAMP_PAGE_COV_DEFSfmt */ 13693 /* nFields */ 5, 13694 /* *fields */ soc_DLB_ECMP_FLOWSET_TIMESTAMP_PAGE_COV_DEFS_BCM56560_A0fmt_fields, 13695 /* bits */ 15, 13696 /* flags */ 0, 13697 }, 13698 #endif /* chips */ 13699 13700 #if defined(BCM_56640_A0) 13701 { /* SOC_FORMAT_INT_DLB_HGT_FLOWSET_COV_DEFSfmt */ 13702 /* format DLB_HGT_FLOWSET_COV_DEFSfmt */ 13703 /* nFields */ 4, 13704 /* *fields */ soc_DLB_ECMP_FLOWSET_COV_DEFSfmt_fields, 13705 /* bits */ 19, 13706 /* flags */ 0, 13707 }, 13708 #endif /* chips */ 13709 13710 #if defined(BCM_56340_A0) 13711 { /* SOC_FORMAT_INT_DLB_HGT_FLOWSET_COV_DEFS_BCM56340_A0fmt */ 13712 /* format DLB_HGT_FLOWSET_COV_DEFSfmt */ 13713 /* nFields */ 4, 13714 /* *fields */ soc_DLB_ECMP_FLOWSET_COV_DEFSfmt_fields, 13715 /* bits */ 19, 13716 /* flags */ 0, 13717 }, 13718 #endif /* chips */ 13719 13720 #if defined(BCM_56560_A0) 13721 { /* SOC_FORMAT_INT_DLB_HGT_FLOWSET_COV_DEFS_BCM56560_A0fmt */ 13722 /* format DLB_HGT_FLOWSET_COV_DEFSfmt */ 13723 /* nFields */ 5, 13724 /* *fields */ soc_DLB_HGT_FLOWSET_COV_DEFS_BCM56560_A0fmt_fields, 13725 /* bits */ 20, 13726 /* flags */ 0, 13727 }, 13728 #endif /* chips */ 13729 13730 #if defined(BCM_56560_B0) 13731 { /* SOC_FORMAT_INT_DLB_HGT_FLOWSET_COV_DEFS_BCM56560_B0fmt */ 13732 /* format DLB_HGT_FLOWSET_COV_DEFSfmt */ 13733 /* nFields */ 5, 13734 /* *fields */ soc_DLB_HGT_FLOWSET_COV_DEFS_BCM56560_A0fmt_fields, 13735 /* bits */ 20, 13736 /* flags */ 0, 13737 }, 13738 #endif /* chips */ 13739 13740 #if defined(BCM_56670_A0) 13741 { /* SOC_FORMAT_INT_DLB_HGT_FLOWSET_COV_DEFS_BCM56670_A0fmt */ 13742 /* format DLB_HGT_FLOWSET_COV_DEFSfmt */ 13743 /* nFields */ 5, 13744 /* *fields */ soc_DLB_HGT_FLOWSET_COV_DEFS_BCM56560_A0fmt_fields, 13745 /* bits */ 20, 13746 /* flags */ 0, 13747 }, 13748 #endif /* chips */ 13749 13750 #if defined(BCM_56670_B0) 13751 { /* SOC_FORMAT_INT_DLB_HGT_FLOWSET_COV_DEFS_BCM56670_B0fmt */ 13752 /* format DLB_HGT_FLOWSET_COV_DEFSfmt */ 13753 /* nFields */ 5, 13754 /* *fields */ soc_DLB_HGT_FLOWSET_COV_DEFS_BCM56560_A0fmt_fields, 13755 /* bits */ 20, 13756 /* flags */ 0, 13757 }, 13758 #endif /* chips */ 13759 13760 #if defined(BCM_56850_A0) 13761 { /* SOC_FORMAT_INT_DLB_HGT_FLOWSET_COV_DEFS_BCM56850_A0fmt */ 13762 /* format DLB_HGT_FLOWSET_COV_DEFSfmt */ 13763 /* nFields */ 4, 13764 /* *fields */ soc_DLB_ECMP_FLOWSET_COV_DEFSfmt_fields, 13765 /* bits */ 19, 13766 /* flags */ 0, 13767 }, 13768 #endif /* chips */ 13769 13770 #if defined(BCM_56860_A0) 13771 { /* SOC_FORMAT_INT_DLB_HGT_FLOWSET_COV_DEFS_BCM56860_A0fmt */ 13772 /* format DLB_HGT_FLOWSET_COV_DEFSfmt */ 13773 /* nFields */ 5, 13774 /* *fields */ soc_DLB_HGT_FLOWSET_COV_DEFSfmt_fields, 13775 /* bits */ 20, 13776 /* flags */ 0, 13777 }, 13778 #endif /* chips */ 13779 13780 #if defined(BCM_56640_A0) 13781 { /* SOC_FORMAT_INT_DLB_HGT_FLOWSET_TIMESTAMP_PAGE_COV_DEFSfmt */ 13782 /* format DLB_HGT_FLOWSET_TIMESTAMP_PAGE_COV_DEFSfmt */ 13783 /* nFields */ 5, 13784 /* *fields */ soc_DLB_ECMP_FLOWSET_TIMESTAMP_PAGE_COV_DEFSfmt_fields, 13785 /* bits */ 15, 13786 /* flags */ 0, 13787 }, 13788 #endif /* chips */ 13789 13790 #if defined(BCM_56340_A0) 13791 { /* SOC_FORMAT_INT_DLB_HGT_FLOWSET_TIMESTAMP_PAGE_COV_DEFS_BCM56340_A0fmt */ 13792 /* format DLB_HGT_FLOWSET_TIMESTAMP_PAGE_COV_DEFSfmt */ 13793 /* nFields */ 5, 13794 /* *fields */ soc_DLB_ECMP_FLOWSET_TIMESTAMP_PAGE_COV_DEFSfmt_fields, 13795 /* bits */ 15, 13796 /* flags */ 0, 13797 }, 13798 #endif /* chips */ 13799 13800 #if defined(BCM_56560_A0) 13801 { /* SOC_FORMAT_INT_DLB_HGT_FLOWSET_TIMESTAMP_PAGE_COV_DEFS_BCM56560_A0fmt */ 13802 /* format DLB_HGT_FLOWSET_TIMESTAMP_PAGE_COV_DEFSfmt */ 13803 /* nFields */ 5, 13804 /* *fields */ soc_DLB_ECMP_FLOWSET_TIMESTAMP_PAGE_COV_DEFS_BCM56560_A0fmt_fields, 13805 /* bits */ 15, 13806 /* flags */ 0, 13807 }, 13808 #endif /* chips */ 13809 13810 #if defined(BCM_56560_B0) 13811 { /* SOC_FORMAT_INT_DLB_HGT_FLOWSET_TIMESTAMP_PAGE_COV_DEFS_BCM56560_B0fmt */ 13812 /* format DLB_HGT_FLOWSET_TIMESTAMP_PAGE_COV_DEFSfmt */ 13813 /* nFields */ 5, 13814 /* *fields */ soc_DLB_ECMP_FLOWSET_TIMESTAMP_PAGE_COV_DEFS_BCM56560_A0fmt_fields, 13815 /* bits */ 15, 13816 /* flags */ 0, 13817 }, 13818 #endif /* chips */ 13819 13820 #if defined(BCM_56670_A0) 13821 { /* SOC_FORMAT_INT_DLB_HGT_FLOWSET_TIMESTAMP_PAGE_COV_DEFS_BCM56670_A0fmt */ 13822 /* format DLB_HGT_FLOWSET_TIMESTAMP_PAGE_COV_DEFSfmt */ 13823 /* nFields */ 5, 13824 /* *fields */ soc_DLB_ECMP_FLOWSET_TIMESTAMP_PAGE_COV_DEFS_BCM56560_A0fmt_fields, 13825 /* bits */ 15, 13826 /* flags */ 0, 13827 }, 13828 #endif /* chips */ 13829 13830 #if defined(BCM_56670_B0) 13831 { /* SOC_FORMAT_INT_DLB_HGT_FLOWSET_TIMESTAMP_PAGE_COV_DEFS_BCM56670_B0fmt */ 13832 /* format DLB_HGT_FLOWSET_TIMESTAMP_PAGE_COV_DEFSfmt */ 13833 /* nFields */ 5, 13834 /* *fields */ soc_DLB_ECMP_FLOWSET_TIMESTAMP_PAGE_COV_DEFS_BCM56560_A0fmt_fields, 13835 /* bits */ 15, 13836 /* flags */ 0, 13837 }, 13838 #endif /* chips */ 13839 13840 #if defined(BCM_56850_A0) 13841 { /* SOC_FORMAT_INT_DLB_HGT_FLOWSET_TIMESTAMP_PAGE_COV_DEFS_BCM56850_A0fmt */ 13842 /* format DLB_HGT_FLOWSET_TIMESTAMP_PAGE_COV_DEFSfmt */ 13843 /* nFields */ 5, 13844 /* *fields */ soc_DLB_ECMP_FLOWSET_TIMESTAMP_PAGE_COV_DEFSfmt_fields, 13845 /* bits */ 15, 13846 /* flags */ 0, 13847 }, 13848 #endif /* chips */ 13849 13850 #if defined(BCM_56860_A0) 13851 { /* SOC_FORMAT_INT_DLB_HGT_FLOWSET_TIMESTAMP_PAGE_COV_DEFS_BCM56860_A0fmt */ 13852 /* format DLB_HGT_FLOWSET_TIMESTAMP_PAGE_COV_DEFSfmt */ 13853 /* nFields */ 5, 13854 /* *fields */ soc_DLB_ECMP_FLOWSET_TIMESTAMP_PAGE_COV_DEFSfmt_fields, 13855 /* bits */ 15, 13856 /* flags */ 0, 13857 }, 13858 #endif /* chips */ 13859 13860 #if defined(BCM_56840_A0) 13861 { /* SOC_FORMAT_INT_DLB_HGT_PORT_LOADING_BUSfmt */ 13862 /* format DLB_HGT_PORT_LOADING_BUSfmt */ 13863 /* nFields */ 3, 13864 /* *fields */ soc_DLB_HGT_PORT_LOADING_BUSfmt_fields, 13865 /* bits */ 16, 13866 /* flags */ 0, 13867 }, 13868 #endif /* chips */ 13869 13870 #if defined(BCM_56260_A0) 13871 { /* SOC_FORMAT_INT_DLB_HGT_PORT_LOADING_BUS_BCM56260_A0fmt */ 13872 /* format DLB_HGT_PORT_LOADING_BUSfmt */ 13873 /* nFields */ 3, 13874 /* *fields */ soc_DLB_HGT_PORT_LOADING_BUS_BCM56260_A0fmt_fields, 13875 /* bits */ 16, 13876 /* flags */ 0, 13877 }, 13878 #endif /* chips */ 13879 13880 #if defined(BCM_56260_B0) 13881 { /* SOC_FORMAT_INT_DLB_HGT_PORT_LOADING_BUS_BCM56260_B0fmt */ 13882 /* format DLB_HGT_PORT_LOADING_BUSfmt */ 13883 /* nFields */ 3, 13884 /* *fields */ soc_DLB_HGT_PORT_LOADING_BUS_BCM56260_A0fmt_fields, 13885 /* bits */ 16, 13886 /* flags */ 0, 13887 }, 13888 #endif /* chips */ 13889 13890 #if defined(BCM_56270_A0) 13891 { /* SOC_FORMAT_INT_DLB_HGT_PORT_LOADING_BUS_BCM56270_A0fmt */ 13892 /* format DLB_HGT_PORT_LOADING_BUSfmt */ 13893 /* nFields */ 3, 13894 /* *fields */ soc_DLB_HGT_PORT_LOADING_BUS_BCM56260_A0fmt_fields, 13895 /* bits */ 16, 13896 /* flags */ 0, 13897 }, 13898 #endif /* chips */ 13899 13900 #if defined(BCM_56340_A0) 13901 { /* SOC_FORMAT_INT_DLB_HGT_PORT_LOADING_BUS_BCM56340_A0fmt */ 13902 /* format DLB_HGT_PORT_LOADING_BUSfmt */ 13903 /* nFields */ 4, 13904 /* *fields */ soc_DLB_HGT_PORT_LOADING_BUS_BCM56640_A0fmt_fields, 13905 /* bits */ 17, 13906 /* flags */ 0, 13907 }, 13908 #endif /* chips */ 13909 13910 #if defined(BCM_56370_A0) 13911 { /* SOC_FORMAT_INT_DLB_HGT_PORT_LOADING_BUS_BCM56370_A0fmt */ 13912 /* format DLB_HGT_PORT_LOADING_BUSfmt */ 13913 /* nFields */ 4, 13914 /* *fields */ soc_DLB_HGT_PORT_LOADING_BUS_BCM56370_A0fmt_fields, 13915 /* bits */ 18, 13916 /* flags */ 0, 13917 }, 13918 #endif /* chips */ 13919 13920 #if defined(BCM_56440_A0) 13921 { /* SOC_FORMAT_INT_DLB_HGT_PORT_LOADING_BUS_BCM56440_A0fmt */ 13922 /* format DLB_HGT_PORT_LOADING_BUSfmt */ 13923 /* nFields */ 3, 13924 /* *fields */ soc_DLB_HGT_PORT_LOADING_BUS_BCM56440_A0fmt_fields, 13925 /* bits */ 16, 13926 /* flags */ 0, 13927 }, 13928 #endif /* chips */ 13929 13930 #if defined(BCM_56440_B0) 13931 { /* SOC_FORMAT_INT_DLB_HGT_PORT_LOADING_BUS_BCM56440_B0fmt */ 13932 /* format DLB_HGT_PORT_LOADING_BUSfmt */ 13933 /* nFields */ 3, 13934 /* *fields */ soc_DLB_HGT_PORT_LOADING_BUS_BCM56440_A0fmt_fields, 13935 /* bits */ 16, 13936 /* flags */ 0, 13937 }, 13938 #endif /* chips */ 13939 13940 #if defined(BCM_56450_A0) 13941 { /* SOC_FORMAT_INT_DLB_HGT_PORT_LOADING_BUS_BCM56450_A0fmt */ 13942 /* format DLB_HGT_PORT_LOADING_BUSfmt */ 13943 /* nFields */ 3, 13944 /* *fields */ soc_DLB_HGT_PORT_LOADING_BUS_BCM56450_A0fmt_fields, 13945 /* bits */ 16, 13946 /* flags */ 0, 13947 }, 13948 #endif /* chips */ 13949 13950 #if defined(BCM_56450_B0) 13951 { /* SOC_FORMAT_INT_DLB_HGT_PORT_LOADING_BUS_BCM56450_B0fmt */ 13952 /* format DLB_HGT_PORT_LOADING_BUSfmt */ 13953 /* nFields */ 3, 13954 /* *fields */ soc_DLB_HGT_PORT_LOADING_BUS_BCM56450_A0fmt_fields, 13955 /* bits */ 16, 13956 /* flags */ 0, 13957 }, 13958 #endif /* chips */ 13959 13960 #if defined(BCM_56450_B1) 13961 { /* SOC_FORMAT_INT_DLB_HGT_PORT_LOADING_BUS_BCM56450_B1fmt */ 13962 /* format DLB_HGT_PORT_LOADING_BUSfmt */ 13963 /* nFields */ 3, 13964 /* *fields */ soc_DLB_HGT_PORT_LOADING_BUS_BCM56450_A0fmt_fields, 13965 /* bits */ 16, 13966 /* flags */ 0, 13967 }, 13968 #endif /* chips */ 13969 13970 #if defined(BCM_56560_A0) 13971 { /* SOC_FORMAT_INT_DLB_HGT_PORT_LOADING_BUS_BCM56560_A0fmt */ 13972 /* format DLB_HGT_PORT_LOADING_BUSfmt */ 13973 /* nFields */ 3, 13974 /* *fields */ soc_DLB_HGT_PORT_LOADING_BUS_BCM56560_A0fmt_fields, 13975 /* bits */ 17, 13976 /* flags */ 0, 13977 }, 13978 #endif /* chips */ 13979 13980 #if defined(BCM_56560_B0) 13981 { /* SOC_FORMAT_INT_DLB_HGT_PORT_LOADING_BUS_BCM56560_B0fmt */ 13982 /* format DLB_HGT_PORT_LOADING_BUSfmt */ 13983 /* nFields */ 3, 13984 /* *fields */ soc_DLB_HGT_PORT_LOADING_BUS_BCM56560_A0fmt_fields, 13985 /* bits */ 17, 13986 /* flags */ 0, 13987 }, 13988 #endif /* chips */ 13989 13990 #if defined(BCM_56640_A0) 13991 { /* SOC_FORMAT_INT_DLB_HGT_PORT_LOADING_BUS_BCM56640_A0fmt */ 13992 /* format DLB_HGT_PORT_LOADING_BUSfmt */ 13993 /* nFields */ 4, 13994 /* *fields */ soc_DLB_HGT_PORT_LOADING_BUS_BCM56640_A0fmt_fields, 13995 /* bits */ 17, 13996 /* flags */ 0, 13997 }, 13998 #endif /* chips */ 13999 14000 #if defined(BCM_56670_A0) 14001 { /* SOC_FORMAT_INT_DLB_HGT_PORT_LOADING_BUS_BCM56670_A0fmt */ 14002 /* format DLB_HGT_PORT_LOADING_BUSfmt */ 14003 /* nFields */ 3, 14004 /* *fields */ soc_DLB_HGT_PORT_LOADING_BUS_BCM56560_A0fmt_fields, 14005 /* bits */ 17, 14006 /* flags */ 0, 14007 }, 14008 #endif /* chips */ 14009 14010 #if defined(BCM_56670_B0) 14011 { /* SOC_FORMAT_INT_DLB_HGT_PORT_LOADING_BUS_BCM56670_B0fmt */ 14012 /* format DLB_HGT_PORT_LOADING_BUSfmt */ 14013 /* nFields */ 3, 14014 /* *fields */ soc_DLB_HGT_PORT_LOADING_BUS_BCM56560_A0fmt_fields, 14015 /* bits */ 17, 14016 /* flags */ 0, 14017 }, 14018 #endif /* chips */ 14019 14020 #if defined(BCM_56770_A0) 14021 { /* SOC_FORMAT_INT_DLB_HGT_PORT_LOADING_BUS_BCM56770_A0fmt */ 14022 /* format DLB_HGT_PORT_LOADING_BUSfmt */ 14023 /* nFields */ 3, 14024 /* *fields */ soc_DLB_PORT_LOADING_BUSfmt_fields, 14025 /* bits */ 18, 14026 /* flags */ 0, 14027 }, 14028 #endif /* chips */ 14029 14030 #if defined(BCM_56840_B0) 14031 { /* SOC_FORMAT_INT_DLB_HGT_PORT_LOADING_BUS_BCM56840_B0fmt */ 14032 /* format DLB_HGT_PORT_LOADING_BUSfmt */ 14033 /* nFields */ 3, 14034 /* *fields */ soc_DLB_HGT_PORT_LOADING_BUSfmt_fields, 14035 /* bits */ 16, 14036 /* flags */ 0, 14037 }, 14038 #endif /* chips */ 14039 14040 #if defined(BCM_56850_A0) 14041 { /* SOC_FORMAT_INT_DLB_HGT_PORT_LOADING_BUS_BCM56850_A0fmt */ 14042 /* format DLB_HGT_PORT_LOADING_BUSfmt */ 14043 /* nFields */ 3, 14044 /* *fields */ soc_DLB_HGT_PORT_LOADING_BUS_BCM56850_A0fmt_fields, 14045 /* bits */ 16, 14046 /* flags */ 0, 14047 }, 14048 #endif /* chips */ 14049 14050 #if defined(BCM_56860_A0) 14051 { /* SOC_FORMAT_INT_DLB_HGT_PORT_LOADING_BUS_BCM56860_A0fmt */ 14052 /* format DLB_HGT_PORT_LOADING_BUSfmt */ 14053 /* nFields */ 3, 14054 /* *fields */ soc_DLB_HGT_PORT_LOADING_BUS_BCM56850_A0fmt_fields, 14055 /* bits */ 16, 14056 /* flags */ 0, 14057 }, 14058 #endif /* chips */ 14059 14060 #if defined(BCM_56870_A0) 14061 { /* SOC_FORMAT_INT_DLB_HGT_PORT_LOADING_BUS_BCM56870_A0fmt */ 14062 /* format DLB_HGT_PORT_LOADING_BUSfmt */ 14063 /* nFields */ 3, 14064 /* *fields */ soc_DLB_PORT_LOADING_BUSfmt_fields, 14065 /* bits */ 18, 14066 /* flags */ 0, 14067 }, 14068 #endif /* chips */ 14069 14070 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) || \ 14071 defined(BCM_56840_A0) 14072 { /* SOC_FORMAT_INT_DLB_HGT_PORT_QSIZE_BUSfmt */ 14073 /* format DLB_HGT_PORT_QSIZE_BUSfmt */ 14074 /* nFields */ 3, 14075 /* *fields */ soc_DLB_HGT_PORT_QSIZE_BUSfmt_fields, 14076 /* bits */ 24, 14077 /* flags */ 0, 14078 }, 14079 #endif /* chips */ 14080 14081 #if defined(BCM_56260_A0) 14082 { /* SOC_FORMAT_INT_DLB_HGT_PORT_QSIZE_BUS_BCM56260_A0fmt */ 14083 /* format DLB_HGT_PORT_QSIZE_BUSfmt */ 14084 /* nFields */ 3, 14085 /* *fields */ soc_DLB_HGT_PORT_QSIZE_BUS_BCM56260_A0fmt_fields, 14086 /* bits */ 14, 14087 /* flags */ 0, 14088 }, 14089 #endif /* chips */ 14090 14091 #if defined(BCM_56260_B0) 14092 { /* SOC_FORMAT_INT_DLB_HGT_PORT_QSIZE_BUS_BCM56260_B0fmt */ 14093 /* format DLB_HGT_PORT_QSIZE_BUSfmt */ 14094 /* nFields */ 3, 14095 /* *fields */ soc_DLB_HGT_PORT_QSIZE_BUS_BCM56260_A0fmt_fields, 14096 /* bits */ 14, 14097 /* flags */ 0, 14098 }, 14099 #endif /* chips */ 14100 14101 #if defined(BCM_56270_A0) 14102 { /* SOC_FORMAT_INT_DLB_HGT_PORT_QSIZE_BUS_BCM56270_A0fmt */ 14103 /* format DLB_HGT_PORT_QSIZE_BUSfmt */ 14104 /* nFields */ 3, 14105 /* *fields */ soc_DLB_HGT_PORT_QSIZE_BUS_BCM56260_A0fmt_fields, 14106 /* bits */ 14, 14107 /* flags */ 0, 14108 }, 14109 #endif /* chips */ 14110 14111 #if defined(BCM_56340_A0) 14112 { /* SOC_FORMAT_INT_DLB_HGT_PORT_QSIZE_BUS_BCM56340_A0fmt */ 14113 /* format DLB_HGT_PORT_QSIZE_BUSfmt */ 14114 /* nFields */ 3, 14115 /* *fields */ soc_DLB_HGT_PORT_QSIZE_BUS_BCM56640_A0fmt_fields, 14116 /* bits */ 24, 14117 /* flags */ 0, 14118 }, 14119 #endif /* chips */ 14120 14121 #if defined(BCM_56370_A0) 14122 { /* SOC_FORMAT_INT_DLB_HGT_PORT_QSIZE_BUS_BCM56370_A0fmt */ 14123 /* format DLB_HGT_PORT_QSIZE_BUSfmt */ 14124 /* nFields */ 3, 14125 /* *fields */ soc_DLB_HGT_PORT_QSIZE_BUS_BCM56560_A0fmt_fields, 14126 /* bits */ 25, 14127 /* flags */ 0, 14128 }, 14129 #endif /* chips */ 14130 14131 #if defined(BCM_56450_A0) 14132 { /* SOC_FORMAT_INT_DLB_HGT_PORT_QSIZE_BUS_BCM56450_A0fmt */ 14133 /* format DLB_HGT_PORT_QSIZE_BUSfmt */ 14134 /* nFields */ 3, 14135 /* *fields */ soc_DLB_HGT_PORT_QSIZE_BUS_BCM56640_A0fmt_fields, 14136 /* bits */ 24, 14137 /* flags */ 0, 14138 }, 14139 #endif /* chips */ 14140 14141 #if defined(BCM_56450_B0) 14142 { /* SOC_FORMAT_INT_DLB_HGT_PORT_QSIZE_BUS_BCM56450_B0fmt */ 14143 /* format DLB_HGT_PORT_QSIZE_BUSfmt */ 14144 /* nFields */ 3, 14145 /* *fields */ soc_DLB_HGT_PORT_QSIZE_BUS_BCM56640_A0fmt_fields, 14146 /* bits */ 24, 14147 /* flags */ 0, 14148 }, 14149 #endif /* chips */ 14150 14151 #if defined(BCM_56450_B1) 14152 { /* SOC_FORMAT_INT_DLB_HGT_PORT_QSIZE_BUS_BCM56450_B1fmt */ 14153 /* format DLB_HGT_PORT_QSIZE_BUSfmt */ 14154 /* nFields */ 3, 14155 /* *fields */ soc_DLB_HGT_PORT_QSIZE_BUS_BCM56640_A0fmt_fields, 14156 /* bits */ 24, 14157 /* flags */ 0, 14158 }, 14159 #endif /* chips */ 14160 14161 #if defined(BCM_56560_A0) 14162 { /* SOC_FORMAT_INT_DLB_HGT_PORT_QSIZE_BUS_BCM56560_A0fmt */ 14163 /* format DLB_HGT_PORT_QSIZE_BUSfmt */ 14164 /* nFields */ 3, 14165 /* *fields */ soc_DLB_HGT_PORT_QSIZE_BUS_BCM56560_A0fmt_fields, 14166 /* bits */ 25, 14167 /* flags */ 0, 14168 }, 14169 #endif /* chips */ 14170 14171 #if defined(BCM_56560_B0) 14172 { /* SOC_FORMAT_INT_DLB_HGT_PORT_QSIZE_BUS_BCM56560_B0fmt */ 14173 /* format DLB_HGT_PORT_QSIZE_BUSfmt */ 14174 /* nFields */ 3, 14175 /* *fields */ soc_DLB_HGT_PORT_QSIZE_BUS_BCM56560_A0fmt_fields, 14176 /* bits */ 25, 14177 /* flags */ 0, 14178 }, 14179 #endif /* chips */ 14180 14181 #if defined(BCM_56640_A0) 14182 { /* SOC_FORMAT_INT_DLB_HGT_PORT_QSIZE_BUS_BCM56640_A0fmt */ 14183 /* format DLB_HGT_PORT_QSIZE_BUSfmt */ 14184 /* nFields */ 3, 14185 /* *fields */ soc_DLB_HGT_PORT_QSIZE_BUS_BCM56640_A0fmt_fields, 14186 /* bits */ 24, 14187 /* flags */ 0, 14188 }, 14189 #endif /* chips */ 14190 14191 #if defined(BCM_56670_A0) 14192 { /* SOC_FORMAT_INT_DLB_HGT_PORT_QSIZE_BUS_BCM56670_A0fmt */ 14193 /* format DLB_HGT_PORT_QSIZE_BUSfmt */ 14194 /* nFields */ 3, 14195 /* *fields */ soc_DLB_HGT_PORT_QSIZE_BUS_BCM56560_A0fmt_fields, 14196 /* bits */ 25, 14197 /* flags */ 0, 14198 }, 14199 #endif /* chips */ 14200 14201 #if defined(BCM_56670_B0) 14202 { /* SOC_FORMAT_INT_DLB_HGT_PORT_QSIZE_BUS_BCM56670_B0fmt */ 14203 /* format DLB_HGT_PORT_QSIZE_BUSfmt */ 14204 /* nFields */ 3, 14205 /* *fields */ soc_DLB_HGT_PORT_QSIZE_BUS_BCM56560_A0fmt_fields, 14206 /* bits */ 25, 14207 /* flags */ 0, 14208 }, 14209 #endif /* chips */ 14210 14211 #if defined(BCM_56770_A0) 14212 { /* SOC_FORMAT_INT_DLB_HGT_PORT_QSIZE_BUS_BCM56770_A0fmt */ 14213 /* format DLB_HGT_PORT_QSIZE_BUSfmt */ 14214 /* nFields */ 3, 14215 /* *fields */ soc_DLB_HGT_PORT_QSIZE_BUS_BCM56560_A0fmt_fields, 14216 /* bits */ 25, 14217 /* flags */ 0, 14218 }, 14219 #endif /* chips */ 14220 14221 #if defined(BCM_56840_B0) 14222 { /* SOC_FORMAT_INT_DLB_HGT_PORT_QSIZE_BUS_BCM56840_B0fmt */ 14223 /* format DLB_HGT_PORT_QSIZE_BUSfmt */ 14224 /* nFields */ 3, 14225 /* *fields */ soc_DLB_HGT_PORT_QSIZE_BUSfmt_fields, 14226 /* bits */ 24, 14227 /* flags */ 0, 14228 }, 14229 #endif /* chips */ 14230 14231 #if defined(BCM_56850_A0) 14232 { /* SOC_FORMAT_INT_DLB_HGT_PORT_QSIZE_BUS_BCM56850_A0fmt */ 14233 /* format DLB_HGT_PORT_QSIZE_BUSfmt */ 14234 /* nFields */ 3, 14235 /* *fields */ soc_DLB_HGT_PORT_QSIZE_BUS_BCM56640_A0fmt_fields, 14236 /* bits */ 24, 14237 /* flags */ 0, 14238 }, 14239 #endif /* chips */ 14240 14241 #if defined(BCM_56860_A0) 14242 { /* SOC_FORMAT_INT_DLB_HGT_PORT_QSIZE_BUS_BCM56860_A0fmt */ 14243 /* format DLB_HGT_PORT_QSIZE_BUSfmt */ 14244 /* nFields */ 3, 14245 /* *fields */ soc_DLB_HGT_PORT_QSIZE_BUS_BCM56860_A0fmt_fields, 14246 /* bits */ 25, 14247 /* flags */ 0, 14248 }, 14249 #endif /* chips */ 14250 14251 #if defined(BCM_56870_A0) 14252 { /* SOC_FORMAT_INT_DLB_HGT_PORT_QSIZE_BUS_BCM56870_A0fmt */ 14253 /* format DLB_HGT_PORT_QSIZE_BUSfmt */ 14254 /* nFields */ 3, 14255 /* *fields */ soc_DLB_HGT_PORT_QSIZE_BUS_BCM56560_A0fmt_fields, 14256 /* bits */ 25, 14257 /* flags */ 0, 14258 }, 14259 #endif /* chips */ 14260 14261 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 14262 { /* SOC_FORMAT_INT_DLB_IP_LOADING_BUSfmt */ 14263 /* format DLB_IP_LOADING_BUSfmt */ 14264 /* nFields */ 4, 14265 /* *fields */ soc_DLB_IP_LOADING_BUSfmt_fields, 14266 /* bits */ 8, 14267 /* flags */ 0, 14268 }, 14269 #endif /* chips */ 14270 14271 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 14272 { /* SOC_FORMAT_INT_DLB_ITM_PORT_QSIZE_BUSfmt */ 14273 /* format DLB_ITM_PORT_QSIZE_BUSfmt */ 14274 /* nFields */ 3, 14275 /* *fields */ soc_DLB_ITM_PORT_QSIZE_BUSfmt_fields, 14276 /* bits */ 27, 14277 /* flags */ 0, 14278 }, 14279 #endif /* chips */ 14280 14281 #if defined(BCM_56640_A0) 14282 { /* SOC_FORMAT_INT_DLB_LAG_FLOWSET_COV_DEFSfmt */ 14283 /* format DLB_LAG_FLOWSET_COV_DEFSfmt */ 14284 /* nFields */ 4, 14285 /* *fields */ soc_DLB_ECMP_FLOWSET_COV_DEFSfmt_fields, 14286 /* bits */ 19, 14287 /* flags */ 0, 14288 }, 14289 #endif /* chips */ 14290 14291 #if defined(BCM_56340_A0) 14292 { /* SOC_FORMAT_INT_DLB_LAG_FLOWSET_COV_DEFS_BCM56340_A0fmt */ 14293 /* format DLB_LAG_FLOWSET_COV_DEFSfmt */ 14294 /* nFields */ 4, 14295 /* *fields */ soc_DLB_ECMP_FLOWSET_COV_DEFSfmt_fields, 14296 /* bits */ 19, 14297 /* flags */ 0, 14298 }, 14299 #endif /* chips */ 14300 14301 #if defined(BCM_56560_A0) 14302 { /* SOC_FORMAT_INT_DLB_LAG_FLOWSET_COV_DEFS_BCM56560_A0fmt */ 14303 /* format DLB_LAG_FLOWSET_COV_DEFSfmt */ 14304 /* nFields */ 4, 14305 /* *fields */ soc_DLB_ECMP_FLOWSET_COV_DEFS_BCM56560_A0fmt_fields, 14306 /* bits */ 19, 14307 /* flags */ 0, 14308 }, 14309 #endif /* chips */ 14310 14311 #if defined(BCM_56560_B0) 14312 { /* SOC_FORMAT_INT_DLB_LAG_FLOWSET_COV_DEFS_BCM56560_B0fmt */ 14313 /* format DLB_LAG_FLOWSET_COV_DEFSfmt */ 14314 /* nFields */ 4, 14315 /* *fields */ soc_DLB_ECMP_FLOWSET_COV_DEFS_BCM56560_A0fmt_fields, 14316 /* bits */ 19, 14317 /* flags */ 0, 14318 }, 14319 #endif /* chips */ 14320 14321 #if defined(BCM_56670_A0) 14322 { /* SOC_FORMAT_INT_DLB_LAG_FLOWSET_COV_DEFS_BCM56670_A0fmt */ 14323 /* format DLB_LAG_FLOWSET_COV_DEFSfmt */ 14324 /* nFields */ 4, 14325 /* *fields */ soc_DLB_ECMP_FLOWSET_COV_DEFS_BCM56560_A0fmt_fields, 14326 /* bits */ 19, 14327 /* flags */ 0, 14328 }, 14329 #endif /* chips */ 14330 14331 #if defined(BCM_56670_B0) 14332 { /* SOC_FORMAT_INT_DLB_LAG_FLOWSET_COV_DEFS_BCM56670_B0fmt */ 14333 /* format DLB_LAG_FLOWSET_COV_DEFSfmt */ 14334 /* nFields */ 4, 14335 /* *fields */ soc_DLB_ECMP_FLOWSET_COV_DEFS_BCM56560_A0fmt_fields, 14336 /* bits */ 19, 14337 /* flags */ 0, 14338 }, 14339 #endif /* chips */ 14340 14341 #if defined(BCM_56850_A0) 14342 { /* SOC_FORMAT_INT_DLB_LAG_FLOWSET_COV_DEFS_BCM56850_A0fmt */ 14343 /* format DLB_LAG_FLOWSET_COV_DEFSfmt */ 14344 /* nFields */ 4, 14345 /* *fields */ soc_DLB_ECMP_FLOWSET_COV_DEFSfmt_fields, 14346 /* bits */ 19, 14347 /* flags */ 0, 14348 }, 14349 #endif /* chips */ 14350 14351 #if defined(BCM_56860_A0) 14352 { /* SOC_FORMAT_INT_DLB_LAG_FLOWSET_COV_DEFS_BCM56860_A0fmt */ 14353 /* format DLB_LAG_FLOWSET_COV_DEFSfmt */ 14354 /* nFields */ 4, 14355 /* *fields */ soc_DLB_ECMP_FLOWSET_COV_DEFSfmt_fields, 14356 /* bits */ 19, 14357 /* flags */ 0, 14358 }, 14359 #endif /* chips */ 14360 14361 #if defined(BCM_56640_A0) 14362 { /* SOC_FORMAT_INT_DLB_LAG_FLOWSET_TIMESTAMP_PAGE_COV_DEFSfmt */ 14363 /* format DLB_LAG_FLOWSET_TIMESTAMP_PAGE_COV_DEFSfmt */ 14364 /* nFields */ 5, 14365 /* *fields */ soc_DLB_ECMP_FLOWSET_TIMESTAMP_PAGE_COV_DEFSfmt_fields, 14366 /* bits */ 15, 14367 /* flags */ 0, 14368 }, 14369 #endif /* chips */ 14370 14371 #if defined(BCM_56340_A0) 14372 { /* SOC_FORMAT_INT_DLB_LAG_FLOWSET_TIMESTAMP_PAGE_COV_DEFS_BCM56340_A0fmt */ 14373 /* format DLB_LAG_FLOWSET_TIMESTAMP_PAGE_COV_DEFSfmt */ 14374 /* nFields */ 5, 14375 /* *fields */ soc_DLB_ECMP_FLOWSET_TIMESTAMP_PAGE_COV_DEFSfmt_fields, 14376 /* bits */ 15, 14377 /* flags */ 0, 14378 }, 14379 #endif /* chips */ 14380 14381 #if defined(BCM_56560_A0) 14382 { /* SOC_FORMAT_INT_DLB_LAG_FLOWSET_TIMESTAMP_PAGE_COV_DEFS_BCM56560_A0fmt */ 14383 /* format DLB_LAG_FLOWSET_TIMESTAMP_PAGE_COV_DEFSfmt */ 14384 /* nFields */ 5, 14385 /* *fields */ soc_DLB_ECMP_FLOWSET_TIMESTAMP_PAGE_COV_DEFS_BCM56560_A0fmt_fields, 14386 /* bits */ 15, 14387 /* flags */ 0, 14388 }, 14389 #endif /* chips */ 14390 14391 #if defined(BCM_56560_B0) 14392 { /* SOC_FORMAT_INT_DLB_LAG_FLOWSET_TIMESTAMP_PAGE_COV_DEFS_BCM56560_B0fmt */ 14393 /* format DLB_LAG_FLOWSET_TIMESTAMP_PAGE_COV_DEFSfmt */ 14394 /* nFields */ 5, 14395 /* *fields */ soc_DLB_ECMP_FLOWSET_TIMESTAMP_PAGE_COV_DEFS_BCM56560_A0fmt_fields, 14396 /* bits */ 15, 14397 /* flags */ 0, 14398 }, 14399 #endif /* chips */ 14400 14401 #if defined(BCM_56670_A0) 14402 { /* SOC_FORMAT_INT_DLB_LAG_FLOWSET_TIMESTAMP_PAGE_COV_DEFS_BCM56670_A0fmt */ 14403 /* format DLB_LAG_FLOWSET_TIMESTAMP_PAGE_COV_DEFSfmt */ 14404 /* nFields */ 5, 14405 /* *fields */ soc_DLB_ECMP_FLOWSET_TIMESTAMP_PAGE_COV_DEFS_BCM56560_A0fmt_fields, 14406 /* bits */ 15, 14407 /* flags */ 0, 14408 }, 14409 #endif /* chips */ 14410 14411 #if defined(BCM_56670_B0) 14412 { /* SOC_FORMAT_INT_DLB_LAG_FLOWSET_TIMESTAMP_PAGE_COV_DEFS_BCM56670_B0fmt */ 14413 /* format DLB_LAG_FLOWSET_TIMESTAMP_PAGE_COV_DEFSfmt */ 14414 /* nFields */ 5, 14415 /* *fields */ soc_DLB_ECMP_FLOWSET_TIMESTAMP_PAGE_COV_DEFS_BCM56560_A0fmt_fields, 14416 /* bits */ 15, 14417 /* flags */ 0, 14418 }, 14419 #endif /* chips */ 14420 14421 #if defined(BCM_56850_A0) 14422 { /* SOC_FORMAT_INT_DLB_LAG_FLOWSET_TIMESTAMP_PAGE_COV_DEFS_BCM56850_A0fmt */ 14423 /* format DLB_LAG_FLOWSET_TIMESTAMP_PAGE_COV_DEFSfmt */ 14424 /* nFields */ 5, 14425 /* *fields */ soc_DLB_ECMP_FLOWSET_TIMESTAMP_PAGE_COV_DEFSfmt_fields, 14426 /* bits */ 15, 14427 /* flags */ 0, 14428 }, 14429 #endif /* chips */ 14430 14431 #if defined(BCM_56860_A0) 14432 { /* SOC_FORMAT_INT_DLB_LAG_FLOWSET_TIMESTAMP_PAGE_COV_DEFS_BCM56860_A0fmt */ 14433 /* format DLB_LAG_FLOWSET_TIMESTAMP_PAGE_COV_DEFSfmt */ 14434 /* nFields */ 5, 14435 /* *fields */ soc_DLB_ECMP_FLOWSET_TIMESTAMP_PAGE_COV_DEFSfmt_fields, 14436 /* bits */ 15, 14437 /* flags */ 0, 14438 }, 14439 #endif /* chips */ 14440 14441 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 14442 defined(BCM_56870_A0) || defined(BCM_56970_A0) 14443 { /* SOC_FORMAT_INT_DLB_PORT_LOADING_BUSfmt */ 14444 /* format DLB_PORT_LOADING_BUSfmt */ 14445 /* nFields */ 3, 14446 /* *fields */ soc_DLB_PORT_LOADING_BUSfmt_fields, 14447 /* bits */ 18, 14448 /* flags */ 0, 14449 }, 14450 #endif /* chips */ 14451 14452 #if defined(BCM_56980_A0) 14453 { /* SOC_FORMAT_INT_DLB_PORT_LOADING_BUS_BCM56980_A0fmt */ 14454 /* format DLB_PORT_LOADING_BUSfmt */ 14455 /* nFields */ 3, 14456 /* *fields */ soc_DLB_PORT_LOADING_BUS_BCM56980_A0fmt_fields, 14457 /* bits */ 18, 14458 /* flags */ 0, 14459 }, 14460 #endif /* chips */ 14461 14462 #if defined(BCM_56980_B0) 14463 { /* SOC_FORMAT_INT_DLB_PORT_LOADING_BUS_BCM56980_B0fmt */ 14464 /* format DLB_PORT_LOADING_BUSfmt */ 14465 /* nFields */ 3, 14466 /* *fields */ soc_DLB_PORT_LOADING_BUS_BCM56980_A0fmt_fields, 14467 /* bits */ 18, 14468 /* flags */ 0, 14469 }, 14470 #endif /* chips */ 14471 14472 #if defined(BCM_56340_A0) || defined(BCM_56640_A0) 14473 { /* SOC_FORMAT_INT_DLB_VIRTUAL_ACCOUNTING_LOADING_BUSfmt */ 14474 /* format DLB_VIRTUAL_ACCOUNTING_LOADING_BUSfmt */ 14475 /* nFields */ 3, 14476 /* *fields */ soc_DLB_VIRTUAL_ACCOUNTING_LOADING_BUSfmt_fields, 14477 /* bits */ 17, 14478 /* flags */ 0, 14479 }, 14480 #endif /* chips */ 14481 14482 #if defined(BCM_56970_A0) 14483 { /* SOC_FORMAT_INT_DLB_XPE_PORT_QSIZE_BUSfmt */ 14484 /* format DLB_XPE_PORT_QSIZE_BUSfmt */ 14485 /* nFields */ 3, 14486 /* *fields */ soc_DLB_XPE_PORT_QSIZE_BUSfmt_fields, 14487 /* bits */ 25, 14488 /* flags */ 0, 14489 }, 14490 #endif /* chips */ 14491 14492 #if defined(BCM_56370_A0) 14493 { /* SOC_FORMAT_INT_DLB_XPE_PORT_QSIZE_BUS_BCM56370_A0fmt */ 14494 /* format DLB_XPE_PORT_QSIZE_BUSfmt */ 14495 /* nFields */ 3, 14496 /* *fields */ soc_DLB_XPE_PORT_QSIZE_BUS_BCM56870_A0fmt_fields, 14497 /* bits */ 27, 14498 /* flags */ 0, 14499 }, 14500 #endif /* chips */ 14501 14502 #if defined(BCM_56770_A0) 14503 { /* SOC_FORMAT_INT_DLB_XPE_PORT_QSIZE_BUS_BCM56770_A0fmt */ 14504 /* format DLB_XPE_PORT_QSIZE_BUSfmt */ 14505 /* nFields */ 3, 14506 /* *fields */ soc_DLB_XPE_PORT_QSIZE_BUS_BCM56870_A0fmt_fields, 14507 /* bits */ 27, 14508 /* flags */ 0, 14509 }, 14510 #endif /* chips */ 14511 14512 #if defined(BCM_56870_A0) 14513 { /* SOC_FORMAT_INT_DLB_XPE_PORT_QSIZE_BUS_BCM56870_A0fmt */ 14514 /* format DLB_XPE_PORT_QSIZE_BUSfmt */ 14515 /* nFields */ 3, 14516 /* *fields */ soc_DLB_XPE_PORT_QSIZE_BUS_BCM56870_A0fmt_fields, 14517 /* bits */ 27, 14518 /* flags */ 0, 14519 }, 14520 #endif /* chips */ 14521 14522 #if defined(BCM_56340_A0) || defined(BCM_56450_A0) || \ 14523 defined(BCM_56450_B0) || defined(BCM_56450_B1) || \ 14524 defined(BCM_56640_A0) || defined(BCM_56850_A0) || \ 14525 defined(BCM_56860_A0) 14526 { /* SOC_FORMAT_INT_DM_TIMESTAMPfmt */ 14527 /* format DM_TIMESTAMPfmt */ 14528 /* nFields */ 6, 14529 /* *fields */ soc_DM_TIMESTAMPfmt_fields, 14530 /* bits */ 128, 14531 /* flags */ 0, 14532 }, 14533 #endif /* chips */ 14534 14535 #if defined(BCM_56260_A0) 14536 { /* SOC_FORMAT_INT_DM_TIMESTAMP_BCM56260_A0fmt */ 14537 /* format DM_TIMESTAMPfmt */ 14538 /* nFields */ 6, 14539 /* *fields */ soc_DM_TIMESTAMP_BCM56960_A0fmt_fields, 14540 /* bits */ 128, 14541 /* flags */ 0, 14542 }, 14543 #endif /* chips */ 14544 14545 #if defined(BCM_56260_B0) 14546 { /* SOC_FORMAT_INT_DM_TIMESTAMP_BCM56260_B0fmt */ 14547 /* format DM_TIMESTAMPfmt */ 14548 /* nFields */ 6, 14549 /* *fields */ soc_DM_TIMESTAMP_BCM56960_A0fmt_fields, 14550 /* bits */ 128, 14551 /* flags */ 0, 14552 }, 14553 #endif /* chips */ 14554 14555 #if defined(BCM_56270_A0) 14556 { /* SOC_FORMAT_INT_DM_TIMESTAMP_BCM56270_A0fmt */ 14557 /* format DM_TIMESTAMPfmt */ 14558 /* nFields */ 6, 14559 /* *fields */ soc_DM_TIMESTAMP_BCM56960_A0fmt_fields, 14560 /* bits */ 128, 14561 /* flags */ 0, 14562 }, 14563 #endif /* chips */ 14564 14565 #if defined(BCM_56370_A0) 14566 { /* SOC_FORMAT_INT_DM_TIMESTAMP_BCM56370_A0fmt */ 14567 /* format DM_TIMESTAMPfmt */ 14568 /* nFields */ 6, 14569 /* *fields */ soc_DM_TIMESTAMP_BCM56960_A0fmt_fields, 14570 /* bits */ 128, 14571 /* flags */ 0, 14572 }, 14573 #endif /* chips */ 14574 14575 #if defined(BCM_56560_A0) 14576 { /* SOC_FORMAT_INT_DM_TIMESTAMP_BCM56560_A0fmt */ 14577 /* format DM_TIMESTAMPfmt */ 14578 /* nFields */ 6, 14579 /* *fields */ soc_DM_TIMESTAMP_BCM56960_A0fmt_fields, 14580 /* bits */ 128, 14581 /* flags */ 0, 14582 }, 14583 #endif /* chips */ 14584 14585 #if defined(BCM_56560_B0) 14586 { /* SOC_FORMAT_INT_DM_TIMESTAMP_BCM56560_B0fmt */ 14587 /* format DM_TIMESTAMPfmt */ 14588 /* nFields */ 6, 14589 /* *fields */ soc_DM_TIMESTAMP_BCM56960_A0fmt_fields, 14590 /* bits */ 128, 14591 /* flags */ 0, 14592 }, 14593 #endif /* chips */ 14594 14595 #if defined(BCM_56670_A0) 14596 { /* SOC_FORMAT_INT_DM_TIMESTAMP_BCM56670_A0fmt */ 14597 /* format DM_TIMESTAMPfmt */ 14598 /* nFields */ 6, 14599 /* *fields */ soc_DM_TIMESTAMP_BCM56960_A0fmt_fields, 14600 /* bits */ 128, 14601 /* flags */ 0, 14602 }, 14603 #endif /* chips */ 14604 14605 #if defined(BCM_56670_B0) 14606 { /* SOC_FORMAT_INT_DM_TIMESTAMP_BCM56670_B0fmt */ 14607 /* format DM_TIMESTAMPfmt */ 14608 /* nFields */ 6, 14609 /* *fields */ soc_DM_TIMESTAMP_BCM56960_A0fmt_fields, 14610 /* bits */ 128, 14611 /* flags */ 0, 14612 }, 14613 #endif /* chips */ 14614 14615 #if defined(BCM_56770_A0) 14616 { /* SOC_FORMAT_INT_DM_TIMESTAMP_BCM56770_A0fmt */ 14617 /* format DM_TIMESTAMPfmt */ 14618 /* nFields */ 6, 14619 /* *fields */ soc_DM_TIMESTAMP_BCM56960_A0fmt_fields, 14620 /* bits */ 128, 14621 /* flags */ 0, 14622 }, 14623 #endif /* chips */ 14624 14625 #if defined(BCM_56870_A0) 14626 { /* SOC_FORMAT_INT_DM_TIMESTAMP_BCM56870_A0fmt */ 14627 /* format DM_TIMESTAMPfmt */ 14628 /* nFields */ 6, 14629 /* *fields */ soc_DM_TIMESTAMP_BCM56960_A0fmt_fields, 14630 /* bits */ 128, 14631 /* flags */ 0, 14632 }, 14633 #endif /* chips */ 14634 14635 #if defined(BCM_56960_A0) 14636 { /* SOC_FORMAT_INT_DM_TIMESTAMP_BCM56960_A0fmt */ 14637 /* format DM_TIMESTAMPfmt */ 14638 /* nFields */ 6, 14639 /* *fields */ soc_DM_TIMESTAMP_BCM56960_A0fmt_fields, 14640 /* bits */ 128, 14641 /* flags */ 0, 14642 }, 14643 #endif /* chips */ 14644 14645 #if defined(BCM_56965_A0) 14646 { /* SOC_FORMAT_INT_DM_TIMESTAMP_BCM56965_A0fmt */ 14647 /* format DM_TIMESTAMPfmt */ 14648 /* nFields */ 6, 14649 /* *fields */ soc_DM_TIMESTAMP_BCM56960_A0fmt_fields, 14650 /* bits */ 128, 14651 /* flags */ 0, 14652 }, 14653 #endif /* chips */ 14654 14655 #if defined(BCM_56970_A0) 14656 { /* SOC_FORMAT_INT_DM_TIMESTAMP_BCM56970_A0fmt */ 14657 /* format DM_TIMESTAMPfmt */ 14658 /* nFields */ 6, 14659 /* *fields */ soc_DM_TIMESTAMP_BCM56960_A0fmt_fields, 14660 /* bits */ 128, 14661 /* flags */ 0, 14662 }, 14663 #endif /* chips */ 14664 14665 #if defined(BCM_56980_A0) 14666 { /* SOC_FORMAT_INT_DM_TIMESTAMP_BCM56980_A0fmt */ 14667 /* format DM_TIMESTAMPfmt */ 14668 /* nFields */ 6, 14669 /* *fields */ soc_DM_TIMESTAMP_BCM56960_A0fmt_fields, 14670 /* bits */ 128, 14671 /* flags */ 0, 14672 }, 14673 #endif /* chips */ 14674 14675 #if defined(BCM_56980_B0) 14676 { /* SOC_FORMAT_INT_DM_TIMESTAMP_BCM56980_B0fmt */ 14677 /* format DM_TIMESTAMPfmt */ 14678 /* nFields */ 6, 14679 /* *fields */ soc_DM_TIMESTAMP_BCM56960_A0fmt_fields, 14680 /* bits */ 128, 14681 /* flags */ 0, 14682 }, 14683 #endif /* chips */ 14684 14685 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 14686 defined(BCM_56870_A0) 14687 { /* SOC_FORMAT_INT_DOP_BUSfmt */ 14688 /* format DOP_BUSfmt */ 14689 /* nFields */ 4, 14690 /* *fields */ soc_DOP_BUSfmt_fields, 14691 /* bits */ 40, 14692 /* flags */ 0, 14693 }, 14694 #endif /* chips */ 14695 14696 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 14697 defined(BCM_56870_A0) 14698 { /* SOC_FORMAT_INT_DOP_COLLECTION_RESP_WORDfmt */ 14699 /* format DOP_COLLECTION_RESP_WORDfmt */ 14700 /* nFields */ 4, 14701 /* *fields */ soc_DOP_COLLECTION_RESP_WORDfmt_fields, 14702 /* bits */ 32, 14703 /* flags */ 0, 14704 }, 14705 #endif /* chips */ 14706 14707 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 14708 defined(BCM_56870_A0) 14709 { /* SOC_FORMAT_INT_DOP_DATA_BUSfmt */ 14710 /* format DOP_DATA_BUSfmt */ 14711 /* nFields */ 5, 14712 /* *fields */ soc_DOP_DATA_BUSfmt_fields, 14713 /* bits */ 32, 14714 /* flags */ 0, 14715 }, 14716 #endif /* chips */ 14717 14718 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) 14719 { /* SOC_FORMAT_INT_DQS_TO_DQX_CELL_INFOfmt */ 14720 /* format DQS_TO_DQX_CELL_INFOfmt */ 14721 /* nFields */ 16, 14722 /* *fields */ soc_DQS_TO_DQX_CELL_INFOfmt_fields, 14723 /* bits */ 73, 14724 /* flags */ 0, 14725 }, 14726 #endif /* chips */ 14727 14728 #if defined(BCM_56370_A0) 14729 { /* SOC_FORMAT_INT_DQS_TO_DQX_CELL_INFO_BCM56370_A0fmt */ 14730 /* format DQS_TO_DQX_CELL_INFOfmt */ 14731 /* nFields */ 18, 14732 /* *fields */ soc_DQS_TO_DQX_CELL_INFO_BCM56370_A0fmt_fields, 14733 /* bits */ 85, 14734 /* flags */ 0, 14735 }, 14736 #endif /* chips */ 14737 14738 #if defined(BCM_56770_A0) 14739 { /* SOC_FORMAT_INT_DQS_TO_DQX_CELL_INFO_BCM56770_A0fmt */ 14740 /* format DQS_TO_DQX_CELL_INFOfmt */ 14741 /* nFields */ 16, 14742 /* *fields */ soc_DQS_TO_DQX_CELL_INFO_BCM56870_A0fmt_fields, 14743 /* bits */ 79, 14744 /* flags */ 0, 14745 }, 14746 #endif /* chips */ 14747 14748 #if defined(BCM_56870_A0) 14749 { /* SOC_FORMAT_INT_DQS_TO_DQX_CELL_INFO_BCM56870_A0fmt */ 14750 /* format DQS_TO_DQX_CELL_INFOfmt */ 14751 /* nFields */ 16, 14752 /* *fields */ soc_DQS_TO_DQX_CELL_INFO_BCM56870_A0fmt_fields, 14753 /* bits */ 79, 14754 /* flags */ 0, 14755 }, 14756 #endif /* chips */ 14757 14758 #if defined(BCM_56970_A0) 14759 { /* SOC_FORMAT_INT_DQS_TO_DQX_CELL_INFO_BCM56970_A0fmt */ 14760 /* format DQS_TO_DQX_CELL_INFOfmt */ 14761 /* nFields */ 16, 14762 /* *fields */ soc_DQS_TO_DQX_CELL_INFO_BCM56970_A0fmt_fields, 14763 /* bits */ 74, 14764 /* flags */ 0, 14765 }, 14766 #endif /* chips */ 14767 14768 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 14769 defined(BCM_56870_A0) || defined(BCM_56960_A0) || \ 14770 defined(BCM_56965_A0) || defined(BCM_56970_A0) 14771 { /* SOC_FORMAT_INT_DQS_TO_DQX_REP_INFOfmt */ 14772 /* format DQS_TO_DQX_REP_INFOfmt */ 14773 /* nFields */ 10, 14774 /* *fields */ soc_DQS_TO_DQX_REP_INFOfmt_fields, 14775 /* bits */ 25, 14776 /* flags */ 0, 14777 }, 14778 #endif /* chips */ 14779 14780 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) 14781 { /* SOC_FORMAT_INT_DQS_TO_RIL_INFOfmt */ 14782 /* format DQS_TO_RIL_INFOfmt */ 14783 /* nFields */ 13, 14784 /* *fields */ soc_DQS_TO_RIL_INFOfmt_fields, 14785 /* bits */ 52, 14786 /* flags */ 0, 14787 }, 14788 #endif /* chips */ 14789 14790 #if defined(BCM_56370_A0) 14791 { /* SOC_FORMAT_INT_DQS_TO_RIL_INFO_BCM56370_A0fmt */ 14792 /* format DQS_TO_RIL_INFOfmt */ 14793 /* nFields */ 13, 14794 /* *fields */ soc_DQS_TO_RIL_INFO_BCM56370_A0fmt_fields, 14795 /* bits */ 57, 14796 /* flags */ 0, 14797 }, 14798 #endif /* chips */ 14799 14800 #if defined(BCM_56770_A0) 14801 { /* SOC_FORMAT_INT_DQS_TO_RIL_INFO_BCM56770_A0fmt */ 14802 /* format DQS_TO_RIL_INFOfmt */ 14803 /* nFields */ 13, 14804 /* *fields */ soc_DQS_TO_RIL_INFO_BCM56870_A0fmt_fields, 14805 /* bits */ 59, 14806 /* flags */ 0, 14807 }, 14808 #endif /* chips */ 14809 14810 #if defined(BCM_56870_A0) 14811 { /* SOC_FORMAT_INT_DQS_TO_RIL_INFO_BCM56870_A0fmt */ 14812 /* format DQS_TO_RIL_INFOfmt */ 14813 /* nFields */ 13, 14814 /* *fields */ soc_DQS_TO_RIL_INFO_BCM56870_A0fmt_fields, 14815 /* bits */ 59, 14816 /* flags */ 0, 14817 }, 14818 #endif /* chips */ 14819 14820 #if defined(BCM_56970_A0) 14821 { /* SOC_FORMAT_INT_DQS_TO_RIL_INFO_BCM56970_A0fmt */ 14822 /* format DQS_TO_RIL_INFOfmt */ 14823 /* nFields */ 13, 14824 /* *fields */ soc_DQS_TO_RIL_INFO_BCM56970_A0fmt_fields, 14825 /* bits */ 53, 14826 /* flags */ 0, 14827 }, 14828 #endif /* chips */ 14829 14830 #if defined(BCM_56960_A0) 14831 { /* SOC_FORMAT_INT_DQS_TO_TOQ_INFOfmt */ 14832 /* format DQS_TO_TOQ_INFOfmt */ 14833 /* nFields */ 5, 14834 /* *fields */ soc_DQS_TO_TOQ_INFOfmt_fields, 14835 /* bits */ 34, 14836 /* flags */ 0, 14837 }, 14838 #endif /* chips */ 14839 14840 #if defined(BCM_56370_A0) 14841 { /* SOC_FORMAT_INT_DQS_TO_TOQ_INFO_BCM56370_A0fmt */ 14842 /* format DQS_TO_TOQ_INFOfmt */ 14843 /* nFields */ 4, 14844 /* *fields */ soc_DQS_TO_TOQ_INFO_BCM56870_A0fmt_fields, 14845 /* bits */ 22, 14846 /* flags */ 0, 14847 }, 14848 #endif /* chips */ 14849 14850 #if defined(BCM_56770_A0) 14851 { /* SOC_FORMAT_INT_DQS_TO_TOQ_INFO_BCM56770_A0fmt */ 14852 /* format DQS_TO_TOQ_INFOfmt */ 14853 /* nFields */ 4, 14854 /* *fields */ soc_DQS_TO_TOQ_INFO_BCM56870_A0fmt_fields, 14855 /* bits */ 22, 14856 /* flags */ 0, 14857 }, 14858 #endif /* chips */ 14859 14860 #if defined(BCM_56870_A0) 14861 { /* SOC_FORMAT_INT_DQS_TO_TOQ_INFO_BCM56870_A0fmt */ 14862 /* format DQS_TO_TOQ_INFOfmt */ 14863 /* nFields */ 4, 14864 /* *fields */ soc_DQS_TO_TOQ_INFO_BCM56870_A0fmt_fields, 14865 /* bits */ 22, 14866 /* flags */ 0, 14867 }, 14868 #endif /* chips */ 14869 14870 #if defined(BCM_56965_A0) 14871 { /* SOC_FORMAT_INT_DQS_TO_TOQ_INFO_BCM56965_A0fmt */ 14872 /* format DQS_TO_TOQ_INFOfmt */ 14873 /* nFields */ 4, 14874 /* *fields */ soc_DQS_TO_TOQ_INFO_BCM56965_A0fmt_fields, 14875 /* bits */ 19, 14876 /* flags */ 0, 14877 }, 14878 #endif /* chips */ 14879 14880 #if defined(BCM_56970_A0) 14881 { /* SOC_FORMAT_INT_DQS_TO_TOQ_INFO_BCM56970_A0fmt */ 14882 /* format DQS_TO_TOQ_INFOfmt */ 14883 /* nFields */ 4, 14884 /* *fields */ soc_DQS_TO_TOQ_INFO_BCM56965_A0fmt_fields, 14885 /* bits */ 19, 14886 /* flags */ 0, 14887 }, 14888 #endif /* chips */ 14889 14890 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) 14891 { /* SOC_FORMAT_INT_DQX_TO_CCP_INFO_BUSfmt */ 14892 /* format DQX_TO_CCP_INFO_BUSfmt */ 14893 /* nFields */ 22, 14894 /* *fields */ soc_DQX_TO_CCP_INFO_BUSfmt_fields, 14895 /* bits */ 72, 14896 /* flags */ 0, 14897 }, 14898 #endif /* chips */ 14899 14900 #if defined(BCM_56370_A0) 14901 { /* SOC_FORMAT_INT_DQX_TO_CCP_INFO_BUS_BCM56370_A0fmt */ 14902 /* format DQX_TO_CCP_INFO_BUSfmt */ 14903 /* nFields */ 22, 14904 /* *fields */ soc_DQX_TO_CCP_INFO_BUS_BCM56370_A0fmt_fields, 14905 /* bits */ 78, 14906 /* flags */ 0, 14907 }, 14908 #endif /* chips */ 14909 14910 #if defined(BCM_56770_A0) 14911 { /* SOC_FORMAT_INT_DQX_TO_CCP_INFO_BUS_BCM56770_A0fmt */ 14912 /* format DQX_TO_CCP_INFO_BUSfmt */ 14913 /* nFields */ 22, 14914 /* *fields */ soc_DQX_TO_CCP_INFO_BUS_BCM56870_A0fmt_fields, 14915 /* bits */ 79, 14916 /* flags */ 0, 14917 }, 14918 #endif /* chips */ 14919 14920 #if defined(BCM_56870_A0) 14921 { /* SOC_FORMAT_INT_DQX_TO_CCP_INFO_BUS_BCM56870_A0fmt */ 14922 /* format DQX_TO_CCP_INFO_BUSfmt */ 14923 /* nFields */ 22, 14924 /* *fields */ soc_DQX_TO_CCP_INFO_BUS_BCM56870_A0fmt_fields, 14925 /* bits */ 79, 14926 /* flags */ 0, 14927 }, 14928 #endif /* chips */ 14929 14930 #if defined(BCM_56970_A0) 14931 { /* SOC_FORMAT_INT_DQX_TO_CCP_INFO_BUS_BCM56970_A0fmt */ 14932 /* format DQX_TO_CCP_INFO_BUSfmt */ 14933 /* nFields */ 22, 14934 /* *fields */ soc_DQX_TO_CCP_INFO_BUS_BCM56970_A0fmt_fields, 14935 /* bits */ 73, 14936 /* flags */ 0, 14937 }, 14938 #endif /* chips */ 14939 14940 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) || \ 14941 defined(BCM_56970_A0) 14942 { /* SOC_FORMAT_INT_DQX_TO_CTR_INFOfmt */ 14943 /* format DQX_TO_CTR_INFOfmt */ 14944 /* nFields */ 6, 14945 /* *fields */ soc_DQX_TO_CTR_INFOfmt_fields, 14946 /* bits */ 28, 14947 /* flags */ 0, 14948 }, 14949 #endif /* chips */ 14950 14951 #if defined(BCM_56370_A0) 14952 { /* SOC_FORMAT_INT_DQX_TO_CTR_INFO_BCM56370_A0fmt */ 14953 /* format DQX_TO_CTR_INFOfmt */ 14954 /* nFields */ 6, 14955 /* *fields */ soc_DQX_TO_CTR_INFO_BCM56370_A0fmt_fields, 14956 /* bits */ 31, 14957 /* flags */ 0, 14958 }, 14959 #endif /* chips */ 14960 14961 #if defined(BCM_56770_A0) 14962 { /* SOC_FORMAT_INT_DQX_TO_CTR_INFO_BCM56770_A0fmt */ 14963 /* format DQX_TO_CTR_INFOfmt */ 14964 /* nFields */ 6, 14965 /* *fields */ soc_DQX_TO_CTR_INFO_BCM56870_A0fmt_fields, 14966 /* bits */ 31, 14967 /* flags */ 0, 14968 }, 14969 #endif /* chips */ 14970 14971 #if defined(BCM_56870_A0) 14972 { /* SOC_FORMAT_INT_DQX_TO_CTR_INFO_BCM56870_A0fmt */ 14973 /* format DQX_TO_CTR_INFOfmt */ 14974 /* nFields */ 6, 14975 /* *fields */ soc_DQX_TO_CTR_INFO_BCM56870_A0fmt_fields, 14976 /* bits */ 31, 14977 /* flags */ 0, 14978 }, 14979 #endif /* chips */ 14980 14981 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) 14982 { /* SOC_FORMAT_INT_DROP_VECTOR_1_DOPfmt */ 14983 /* format DROP_VECTOR_1_DOPfmt */ 14984 /* nFields */ 2, 14985 /* *fields */ soc_DROP_VECTOR_1_DOPfmt_fields, 14986 /* bits */ 64, 14987 /* flags */ 0, 14988 }, 14989 #endif /* chips */ 14990 14991 #if defined(BCM_56370_A0) 14992 { /* SOC_FORMAT_INT_DROP_VECTOR_1_DOP_BCM56370_A0fmt */ 14993 /* format DROP_VECTOR_1_DOPfmt */ 14994 /* nFields */ 3, 14995 /* *fields */ soc_DROP_VECTOR_1_DOP_BCM56370_A0fmt_fields, 14996 /* bits */ 96, 14997 /* flags */ 0, 14998 }, 14999 #endif /* chips */ 15000 15001 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 15002 defined(BCM_56870_A0) 15003 { /* SOC_FORMAT_INT_DVP_SWITCHING_CTRLS_ACTION_SETfmt */ 15004 /* format DVP_SWITCHING_CTRLS_ACTION_SETfmt */ 15005 /* nFields */ 8, 15006 /* *fields */ soc_DVP_SWITCHING_CTRLS_ACTION_SETfmt_fields, 15007 /* bits */ 10, 15008 /* flags */ 0, 15009 }, 15010 #endif /* chips */ 15011