allformats_c.i (486613B)
1 /* 2 * DO NOT EDIT THIS FILE! 3 * This file is auto-generated from the registers file. 4 * Edits to this file will be lost when it is regenerated. 5 * 6 * 7 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 8 * 9 * Copyright 2007-2020 Broadcom Inc. All rights reserved. 10 * 11 * File: allformats_c.i 12 * Purpose: Independent format descriptions. 13 */ 14 15 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 16 defined(BCM_56870_A0) 17 { /* SOC_FORMAT_INT_CAM_BIST_CONFIG_64_FORMATfmt */ 18 /* format CAM_BIST_CONFIG_64_FORMATfmt */ 19 /* nFields */ 6, 20 /* *fields */ soc_CAM_BIST_CONFIG_64_FORMATfmt_fields, 21 /* bits */ 37, 22 /* flags */ 0, 23 }, 24 #endif /* chips */ 25 26 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \ 27 defined(BCM_56450_A0) || defined(BCM_56450_B0) || \ 28 defined(BCM_56450_B1) || defined(BCM_56640_A0) || \ 29 defined(BCM_56850_A0) || defined(BCM_56860_A0) 30 { /* SOC_FORMAT_INT_CAPWAP_RADIOMAC_HDRfmt */ 31 /* format CAPWAP_RADIOMAC_HDRfmt */ 32 /* nFields */ 3, 33 /* *fields */ soc_CAPWAP_RADIOMAC_HDRfmt_fields, 34 /* bits */ 64, 35 /* flags */ 0, 36 }, 37 #endif /* chips */ 38 39 #if defined(BCM_53400_A0) 40 { /* SOC_FORMAT_INT_CAPWAP_RADIOMAC_HDR_BCM53400_A0fmt */ 41 /* format CAPWAP_RADIOMAC_HDRfmt */ 42 /* nFields */ 3, 43 /* *fields */ soc_CAPWAP_RADIOMAC_HDR_BCM53400_A0fmt_fields, 44 /* bits */ 64, 45 /* flags */ 0, 46 }, 47 #endif /* chips */ 48 49 #if defined(BCM_53540_A0) 50 { /* SOC_FORMAT_INT_CAPWAP_RADIOMAC_HDR_BCM53540_A0fmt */ 51 /* format CAPWAP_RADIOMAC_HDRfmt */ 52 /* nFields */ 3, 53 /* *fields */ soc_CAPWAP_RADIOMAC_HDR_BCM53400_A0fmt_fields, 54 /* bits */ 64, 55 /* flags */ 0, 56 }, 57 #endif /* chips */ 58 59 #if defined(BCM_53570_A0) 60 { /* SOC_FORMAT_INT_CAPWAP_RADIOMAC_HDR_BCM53570_A0fmt */ 61 /* format CAPWAP_RADIOMAC_HDRfmt */ 62 /* nFields */ 3, 63 /* *fields */ soc_CAPWAP_RADIOMAC_HDR_BCM53400_A0fmt_fields, 64 /* bits */ 64, 65 /* flags */ 0, 66 }, 67 #endif /* chips */ 68 69 #if defined(BCM_53570_B0) 70 { /* SOC_FORMAT_INT_CAPWAP_RADIOMAC_HDR_BCM53570_B0fmt */ 71 /* format CAPWAP_RADIOMAC_HDRfmt */ 72 /* nFields */ 3, 73 /* *fields */ soc_CAPWAP_RADIOMAC_HDR_BCM53400_A0fmt_fields, 74 /* bits */ 64, 75 /* flags */ 0, 76 }, 77 #endif /* chips */ 78 79 #if defined(BCM_56160_A0) 80 { /* SOC_FORMAT_INT_CAPWAP_RADIOMAC_HDR_BCM56160_A0fmt */ 81 /* format CAPWAP_RADIOMAC_HDRfmt */ 82 /* nFields */ 3, 83 /* *fields */ soc_CAPWAP_RADIOMAC_HDR_BCM53400_A0fmt_fields, 84 /* bits */ 64, 85 /* flags */ 0, 86 }, 87 #endif /* chips */ 88 89 #if defined(BCM_56260_A0) 90 { /* SOC_FORMAT_INT_CAPWAP_RADIOMAC_HDR_BCM56260_A0fmt */ 91 /* format CAPWAP_RADIOMAC_HDRfmt */ 92 /* nFields */ 3, 93 /* *fields */ soc_CAPWAP_RADIOMAC_HDR_BCM53400_A0fmt_fields, 94 /* bits */ 64, 95 /* flags */ 0, 96 }, 97 #endif /* chips */ 98 99 #if defined(BCM_56260_B0) 100 { /* SOC_FORMAT_INT_CAPWAP_RADIOMAC_HDR_BCM56260_B0fmt */ 101 /* format CAPWAP_RADIOMAC_HDRfmt */ 102 /* nFields */ 3, 103 /* *fields */ soc_CAPWAP_RADIOMAC_HDR_BCM53400_A0fmt_fields, 104 /* bits */ 64, 105 /* flags */ 0, 106 }, 107 #endif /* chips */ 108 109 #if defined(BCM_56270_A0) 110 { /* SOC_FORMAT_INT_CAPWAP_RADIOMAC_HDR_BCM56270_A0fmt */ 111 /* format CAPWAP_RADIOMAC_HDRfmt */ 112 /* nFields */ 3, 113 /* *fields */ soc_CAPWAP_RADIOMAC_HDR_BCM53400_A0fmt_fields, 114 /* bits */ 64, 115 /* flags */ 0, 116 }, 117 #endif /* chips */ 118 119 #if defined(BCM_56370_A0) 120 { /* SOC_FORMAT_INT_CAPWAP_RADIOMAC_HDR_BCM56370_A0fmt */ 121 /* format CAPWAP_RADIOMAC_HDRfmt */ 122 /* nFields */ 3, 123 /* *fields */ soc_CAPWAP_RADIOMAC_HDR_BCM56870_A0fmt_fields, 124 /* bits */ 64, 125 /* flags */ 0, 126 }, 127 #endif /* chips */ 128 129 #if defined(BCM_56560_A0) 130 { /* SOC_FORMAT_INT_CAPWAP_RADIOMAC_HDR_BCM56560_A0fmt */ 131 /* format CAPWAP_RADIOMAC_HDRfmt */ 132 /* nFields */ 3, 133 /* *fields */ soc_CAPWAP_RADIOMAC_HDR_BCM53400_A0fmt_fields, 134 /* bits */ 64, 135 /* flags */ 0, 136 }, 137 #endif /* chips */ 138 139 #if defined(BCM_56560_B0) 140 { /* SOC_FORMAT_INT_CAPWAP_RADIOMAC_HDR_BCM56560_B0fmt */ 141 /* format CAPWAP_RADIOMAC_HDRfmt */ 142 /* nFields */ 3, 143 /* *fields */ soc_CAPWAP_RADIOMAC_HDR_BCM53400_A0fmt_fields, 144 /* bits */ 64, 145 /* flags */ 0, 146 }, 147 #endif /* chips */ 148 149 #if defined(BCM_56670_A0) 150 { /* SOC_FORMAT_INT_CAPWAP_RADIOMAC_HDR_BCM56670_A0fmt */ 151 /* format CAPWAP_RADIOMAC_HDRfmt */ 152 /* nFields */ 3, 153 /* *fields */ soc_CAPWAP_RADIOMAC_HDR_BCM53400_A0fmt_fields, 154 /* bits */ 64, 155 /* flags */ 0, 156 }, 157 #endif /* chips */ 158 159 #if defined(BCM_56670_B0) 160 { /* SOC_FORMAT_INT_CAPWAP_RADIOMAC_HDR_BCM56670_B0fmt */ 161 /* format CAPWAP_RADIOMAC_HDRfmt */ 162 /* nFields */ 3, 163 /* *fields */ soc_CAPWAP_RADIOMAC_HDR_BCM53400_A0fmt_fields, 164 /* bits */ 64, 165 /* flags */ 0, 166 }, 167 #endif /* chips */ 168 169 #if defined(BCM_56770_A0) 170 { /* SOC_FORMAT_INT_CAPWAP_RADIOMAC_HDR_BCM56770_A0fmt */ 171 /* format CAPWAP_RADIOMAC_HDRfmt */ 172 /* nFields */ 3, 173 /* *fields */ soc_CAPWAP_RADIOMAC_HDR_BCM56870_A0fmt_fields, 174 /* bits */ 64, 175 /* flags */ 0, 176 }, 177 #endif /* chips */ 178 179 #if defined(BCM_56870_A0) 180 { /* SOC_FORMAT_INT_CAPWAP_RADIOMAC_HDR_BCM56870_A0fmt */ 181 /* format CAPWAP_RADIOMAC_HDRfmt */ 182 /* nFields */ 3, 183 /* *fields */ soc_CAPWAP_RADIOMAC_HDR_BCM56870_A0fmt_fields, 184 /* bits */ 64, 185 /* flags */ 0, 186 }, 187 #endif /* chips */ 188 189 #if defined(BCM_56960_A0) 190 { /* SOC_FORMAT_INT_CAPWAP_RADIOMAC_HDR_BCM56960_A0fmt */ 191 /* format CAPWAP_RADIOMAC_HDRfmt */ 192 /* nFields */ 3, 193 /* *fields */ soc_CAPWAP_RADIOMAC_HDR_BCM53400_A0fmt_fields, 194 /* bits */ 64, 195 /* flags */ 0, 196 }, 197 #endif /* chips */ 198 199 #if defined(BCM_56965_A0) 200 { /* SOC_FORMAT_INT_CAPWAP_RADIOMAC_HDR_BCM56965_A0fmt */ 201 /* format CAPWAP_RADIOMAC_HDRfmt */ 202 /* nFields */ 3, 203 /* *fields */ soc_CAPWAP_RADIOMAC_HDR_BCM53400_A0fmt_fields, 204 /* bits */ 64, 205 /* flags */ 0, 206 }, 207 #endif /* chips */ 208 209 #if defined(BCM_56970_A0) 210 { /* SOC_FORMAT_INT_CAPWAP_RADIOMAC_HDR_BCM56970_A0fmt */ 211 /* format CAPWAP_RADIOMAC_HDRfmt */ 212 /* nFields */ 3, 213 /* *fields */ soc_CAPWAP_RADIOMAC_HDR_BCM53400_A0fmt_fields, 214 /* bits */ 64, 215 /* flags */ 0, 216 }, 217 #endif /* chips */ 218 219 #if defined(BCM_56980_A0) 220 { /* SOC_FORMAT_INT_CAPWAP_RADIOMAC_HDR_BCM56980_A0fmt */ 221 /* format CAPWAP_RADIOMAC_HDRfmt */ 222 /* nFields */ 3, 223 /* *fields */ soc_CAPWAP_RADIOMAC_HDR_BCM53400_A0fmt_fields, 224 /* bits */ 64, 225 /* flags */ 0, 226 }, 227 #endif /* chips */ 228 229 #if defined(BCM_56980_B0) 230 { /* SOC_FORMAT_INT_CAPWAP_RADIOMAC_HDR_BCM56980_B0fmt */ 231 /* format CAPWAP_RADIOMAC_HDRfmt */ 232 /* nFields */ 3, 233 /* *fields */ soc_CAPWAP_RADIOMAC_HDR_BCM53400_A0fmt_fields, 234 /* bits */ 64, 235 /* flags */ 0, 236 }, 237 #endif /* chips */ 238 239 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \ 240 defined(BCM_56450_A0) || defined(BCM_56450_B0) || \ 241 defined(BCM_56450_B1) || defined(BCM_56640_A0) || \ 242 defined(BCM_56850_A0) || defined(BCM_56860_A0) 243 { /* SOC_FORMAT_INT_CAPWAP_SHIM_BASE_HDRfmt */ 244 /* format CAPWAP_SHIM_BASE_HDRfmt */ 245 /* nFields */ 17, 246 /* *fields */ soc_CAPWAP_SHIM_BASE_HDRfmt_fields, 247 /* bits */ 64, 248 /* flags */ 0, 249 }, 250 #endif /* chips */ 251 252 #if defined(BCM_53400_A0) 253 { /* SOC_FORMAT_INT_CAPWAP_SHIM_BASE_HDR_BCM53400_A0fmt */ 254 /* format CAPWAP_SHIM_BASE_HDRfmt */ 255 /* nFields */ 17, 256 /* *fields */ soc_CAPWAP_SHIM_BASE_HDR_BCM53400_A0fmt_fields, 257 /* bits */ 64, 258 /* flags */ 0, 259 }, 260 #endif /* chips */ 261 262 #if defined(BCM_53540_A0) 263 { /* SOC_FORMAT_INT_CAPWAP_SHIM_BASE_HDR_BCM53540_A0fmt */ 264 /* format CAPWAP_SHIM_BASE_HDRfmt */ 265 /* nFields */ 17, 266 /* *fields */ soc_CAPWAP_SHIM_BASE_HDR_BCM53400_A0fmt_fields, 267 /* bits */ 64, 268 /* flags */ 0, 269 }, 270 #endif /* chips */ 271 272 #if defined(BCM_53570_A0) 273 { /* SOC_FORMAT_INT_CAPWAP_SHIM_BASE_HDR_BCM53570_A0fmt */ 274 /* format CAPWAP_SHIM_BASE_HDRfmt */ 275 /* nFields */ 17, 276 /* *fields */ soc_CAPWAP_SHIM_BASE_HDR_BCM53400_A0fmt_fields, 277 /* bits */ 64, 278 /* flags */ 0, 279 }, 280 #endif /* chips */ 281 282 #if defined(BCM_53570_B0) 283 { /* SOC_FORMAT_INT_CAPWAP_SHIM_BASE_HDR_BCM53570_B0fmt */ 284 /* format CAPWAP_SHIM_BASE_HDRfmt */ 285 /* nFields */ 17, 286 /* *fields */ soc_CAPWAP_SHIM_BASE_HDR_BCM53400_A0fmt_fields, 287 /* bits */ 64, 288 /* flags */ 0, 289 }, 290 #endif /* chips */ 291 292 #if defined(BCM_56160_A0) 293 { /* SOC_FORMAT_INT_CAPWAP_SHIM_BASE_HDR_BCM56160_A0fmt */ 294 /* format CAPWAP_SHIM_BASE_HDRfmt */ 295 /* nFields */ 17, 296 /* *fields */ soc_CAPWAP_SHIM_BASE_HDR_BCM53400_A0fmt_fields, 297 /* bits */ 64, 298 /* flags */ 0, 299 }, 300 #endif /* chips */ 301 302 #if defined(BCM_56260_A0) 303 { /* SOC_FORMAT_INT_CAPWAP_SHIM_BASE_HDR_BCM56260_A0fmt */ 304 /* format CAPWAP_SHIM_BASE_HDRfmt */ 305 /* nFields */ 17, 306 /* *fields */ soc_CAPWAP_SHIM_BASE_HDR_BCM53400_A0fmt_fields, 307 /* bits */ 64, 308 /* flags */ 0, 309 }, 310 #endif /* chips */ 311 312 #if defined(BCM_56260_B0) 313 { /* SOC_FORMAT_INT_CAPWAP_SHIM_BASE_HDR_BCM56260_B0fmt */ 314 /* format CAPWAP_SHIM_BASE_HDRfmt */ 315 /* nFields */ 17, 316 /* *fields */ soc_CAPWAP_SHIM_BASE_HDR_BCM53400_A0fmt_fields, 317 /* bits */ 64, 318 /* flags */ 0, 319 }, 320 #endif /* chips */ 321 322 #if defined(BCM_56270_A0) 323 { /* SOC_FORMAT_INT_CAPWAP_SHIM_BASE_HDR_BCM56270_A0fmt */ 324 /* format CAPWAP_SHIM_BASE_HDRfmt */ 325 /* nFields */ 17, 326 /* *fields */ soc_CAPWAP_SHIM_BASE_HDR_BCM53400_A0fmt_fields, 327 /* bits */ 64, 328 /* flags */ 0, 329 }, 330 #endif /* chips */ 331 332 #if defined(BCM_56370_A0) 333 { /* SOC_FORMAT_INT_CAPWAP_SHIM_BASE_HDR_BCM56370_A0fmt */ 334 /* format CAPWAP_SHIM_BASE_HDRfmt */ 335 /* nFields */ 17, 336 /* *fields */ soc_CAPWAP_SHIM_BASE_HDR_BCM56870_A0fmt_fields, 337 /* bits */ 64, 338 /* flags */ 0, 339 }, 340 #endif /* chips */ 341 342 #if defined(BCM_56560_A0) 343 { /* SOC_FORMAT_INT_CAPWAP_SHIM_BASE_HDR_BCM56560_A0fmt */ 344 /* format CAPWAP_SHIM_BASE_HDRfmt */ 345 /* nFields */ 17, 346 /* *fields */ soc_CAPWAP_SHIM_BASE_HDR_BCM53400_A0fmt_fields, 347 /* bits */ 64, 348 /* flags */ 0, 349 }, 350 #endif /* chips */ 351 352 #if defined(BCM_56560_B0) 353 { /* SOC_FORMAT_INT_CAPWAP_SHIM_BASE_HDR_BCM56560_B0fmt */ 354 /* format CAPWAP_SHIM_BASE_HDRfmt */ 355 /* nFields */ 17, 356 /* *fields */ soc_CAPWAP_SHIM_BASE_HDR_BCM53400_A0fmt_fields, 357 /* bits */ 64, 358 /* flags */ 0, 359 }, 360 #endif /* chips */ 361 362 #if defined(BCM_56670_A0) 363 { /* SOC_FORMAT_INT_CAPWAP_SHIM_BASE_HDR_BCM56670_A0fmt */ 364 /* format CAPWAP_SHIM_BASE_HDRfmt */ 365 /* nFields */ 17, 366 /* *fields */ soc_CAPWAP_SHIM_BASE_HDR_BCM53400_A0fmt_fields, 367 /* bits */ 64, 368 /* flags */ 0, 369 }, 370 #endif /* chips */ 371 372 #if defined(BCM_56670_B0) 373 { /* SOC_FORMAT_INT_CAPWAP_SHIM_BASE_HDR_BCM56670_B0fmt */ 374 /* format CAPWAP_SHIM_BASE_HDRfmt */ 375 /* nFields */ 17, 376 /* *fields */ soc_CAPWAP_SHIM_BASE_HDR_BCM53400_A0fmt_fields, 377 /* bits */ 64, 378 /* flags */ 0, 379 }, 380 #endif /* chips */ 381 382 #if defined(BCM_56770_A0) 383 { /* SOC_FORMAT_INT_CAPWAP_SHIM_BASE_HDR_BCM56770_A0fmt */ 384 /* format CAPWAP_SHIM_BASE_HDRfmt */ 385 /* nFields */ 17, 386 /* *fields */ soc_CAPWAP_SHIM_BASE_HDR_BCM56870_A0fmt_fields, 387 /* bits */ 64, 388 /* flags */ 0, 389 }, 390 #endif /* chips */ 391 392 #if defined(BCM_56870_A0) 393 { /* SOC_FORMAT_INT_CAPWAP_SHIM_BASE_HDR_BCM56870_A0fmt */ 394 /* format CAPWAP_SHIM_BASE_HDRfmt */ 395 /* nFields */ 17, 396 /* *fields */ soc_CAPWAP_SHIM_BASE_HDR_BCM56870_A0fmt_fields, 397 /* bits */ 64, 398 /* flags */ 0, 399 }, 400 #endif /* chips */ 401 402 #if defined(BCM_56960_A0) 403 { /* SOC_FORMAT_INT_CAPWAP_SHIM_BASE_HDR_BCM56960_A0fmt */ 404 /* format CAPWAP_SHIM_BASE_HDRfmt */ 405 /* nFields */ 17, 406 /* *fields */ soc_CAPWAP_SHIM_BASE_HDR_BCM53400_A0fmt_fields, 407 /* bits */ 64, 408 /* flags */ 0, 409 }, 410 #endif /* chips */ 411 412 #if defined(BCM_56965_A0) 413 { /* SOC_FORMAT_INT_CAPWAP_SHIM_BASE_HDR_BCM56965_A0fmt */ 414 /* format CAPWAP_SHIM_BASE_HDRfmt */ 415 /* nFields */ 17, 416 /* *fields */ soc_CAPWAP_SHIM_BASE_HDR_BCM53400_A0fmt_fields, 417 /* bits */ 64, 418 /* flags */ 0, 419 }, 420 #endif /* chips */ 421 422 #if defined(BCM_56970_A0) 423 { /* SOC_FORMAT_INT_CAPWAP_SHIM_BASE_HDR_BCM56970_A0fmt */ 424 /* format CAPWAP_SHIM_BASE_HDRfmt */ 425 /* nFields */ 17, 426 /* *fields */ soc_CAPWAP_SHIM_BASE_HDR_BCM53400_A0fmt_fields, 427 /* bits */ 64, 428 /* flags */ 0, 429 }, 430 #endif /* chips */ 431 432 #if defined(BCM_56980_A0) 433 { /* SOC_FORMAT_INT_CAPWAP_SHIM_BASE_HDR_BCM56980_A0fmt */ 434 /* format CAPWAP_SHIM_BASE_HDRfmt */ 435 /* nFields */ 17, 436 /* *fields */ soc_CAPWAP_SHIM_BASE_HDR_BCM53400_A0fmt_fields, 437 /* bits */ 64, 438 /* flags */ 0, 439 }, 440 #endif /* chips */ 441 442 #if defined(BCM_56980_B0) 443 { /* SOC_FORMAT_INT_CAPWAP_SHIM_BASE_HDR_BCM56980_B0fmt */ 444 /* format CAPWAP_SHIM_BASE_HDRfmt */ 445 /* nFields */ 17, 446 /* *fields */ soc_CAPWAP_SHIM_BASE_HDR_BCM53400_A0fmt_fields, 447 /* bits */ 64, 448 /* flags */ 0, 449 }, 450 #endif /* chips */ 451 452 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \ 453 defined(BCM_56450_A0) || defined(BCM_56450_B0) || \ 454 defined(BCM_56450_B1) || defined(BCM_56640_A0) || \ 455 defined(BCM_56850_A0) || defined(BCM_56860_A0) 456 { /* SOC_FORMAT_INT_CAPWAP_WIRELESS_SPECIFIC_HDRfmt */ 457 /* format CAPWAP_WIRELESS_SPECIFIC_HDRfmt */ 458 /* nFields */ 3, 459 /* *fields */ soc_CAPWAP_WIRELESS_SPECIFIC_HDRfmt_fields, 460 /* bits */ 64, 461 /* flags */ 0, 462 }, 463 #endif /* chips */ 464 465 #if defined(BCM_53400_A0) 466 { /* SOC_FORMAT_INT_CAPWAP_WIRELESS_SPECIFIC_HDR_BCM53400_A0fmt */ 467 /* format CAPWAP_WIRELESS_SPECIFIC_HDRfmt */ 468 /* nFields */ 3, 469 /* *fields */ soc_CAPWAP_WIRELESS_SPECIFIC_HDR_BCM53400_A0fmt_fields, 470 /* bits */ 64, 471 /* flags */ 0, 472 }, 473 #endif /* chips */ 474 475 #if defined(BCM_53540_A0) 476 { /* SOC_FORMAT_INT_CAPWAP_WIRELESS_SPECIFIC_HDR_BCM53540_A0fmt */ 477 /* format CAPWAP_WIRELESS_SPECIFIC_HDRfmt */ 478 /* nFields */ 3, 479 /* *fields */ soc_CAPWAP_WIRELESS_SPECIFIC_HDR_BCM53400_A0fmt_fields, 480 /* bits */ 64, 481 /* flags */ 0, 482 }, 483 #endif /* chips */ 484 485 #if defined(BCM_53570_A0) 486 { /* SOC_FORMAT_INT_CAPWAP_WIRELESS_SPECIFIC_HDR_BCM53570_A0fmt */ 487 /* format CAPWAP_WIRELESS_SPECIFIC_HDRfmt */ 488 /* nFields */ 3, 489 /* *fields */ soc_CAPWAP_WIRELESS_SPECIFIC_HDR_BCM53400_A0fmt_fields, 490 /* bits */ 64, 491 /* flags */ 0, 492 }, 493 #endif /* chips */ 494 495 #if defined(BCM_53570_B0) 496 { /* SOC_FORMAT_INT_CAPWAP_WIRELESS_SPECIFIC_HDR_BCM53570_B0fmt */ 497 /* format CAPWAP_WIRELESS_SPECIFIC_HDRfmt */ 498 /* nFields */ 3, 499 /* *fields */ soc_CAPWAP_WIRELESS_SPECIFIC_HDR_BCM53400_A0fmt_fields, 500 /* bits */ 64, 501 /* flags */ 0, 502 }, 503 #endif /* chips */ 504 505 #if defined(BCM_56160_A0) 506 { /* SOC_FORMAT_INT_CAPWAP_WIRELESS_SPECIFIC_HDR_BCM56160_A0fmt */ 507 /* format CAPWAP_WIRELESS_SPECIFIC_HDRfmt */ 508 /* nFields */ 3, 509 /* *fields */ soc_CAPWAP_WIRELESS_SPECIFIC_HDR_BCM53400_A0fmt_fields, 510 /* bits */ 64, 511 /* flags */ 0, 512 }, 513 #endif /* chips */ 514 515 #if defined(BCM_56260_A0) 516 { /* SOC_FORMAT_INT_CAPWAP_WIRELESS_SPECIFIC_HDR_BCM56260_A0fmt */ 517 /* format CAPWAP_WIRELESS_SPECIFIC_HDRfmt */ 518 /* nFields */ 3, 519 /* *fields */ soc_CAPWAP_WIRELESS_SPECIFIC_HDR_BCM53400_A0fmt_fields, 520 /* bits */ 64, 521 /* flags */ 0, 522 }, 523 #endif /* chips */ 524 525 #if defined(BCM_56260_B0) 526 { /* SOC_FORMAT_INT_CAPWAP_WIRELESS_SPECIFIC_HDR_BCM56260_B0fmt */ 527 /* format CAPWAP_WIRELESS_SPECIFIC_HDRfmt */ 528 /* nFields */ 3, 529 /* *fields */ soc_CAPWAP_WIRELESS_SPECIFIC_HDR_BCM53400_A0fmt_fields, 530 /* bits */ 64, 531 /* flags */ 0, 532 }, 533 #endif /* chips */ 534 535 #if defined(BCM_56270_A0) 536 { /* SOC_FORMAT_INT_CAPWAP_WIRELESS_SPECIFIC_HDR_BCM56270_A0fmt */ 537 /* format CAPWAP_WIRELESS_SPECIFIC_HDRfmt */ 538 /* nFields */ 3, 539 /* *fields */ soc_CAPWAP_WIRELESS_SPECIFIC_HDR_BCM53400_A0fmt_fields, 540 /* bits */ 64, 541 /* flags */ 0, 542 }, 543 #endif /* chips */ 544 545 #if defined(BCM_56370_A0) 546 { /* SOC_FORMAT_INT_CAPWAP_WIRELESS_SPECIFIC_HDR_BCM56370_A0fmt */ 547 /* format CAPWAP_WIRELESS_SPECIFIC_HDRfmt */ 548 /* nFields */ 3, 549 /* *fields */ soc_CAPWAP_WIRELESS_SPECIFIC_HDR_BCM56870_A0fmt_fields, 550 /* bits */ 64, 551 /* flags */ 0, 552 }, 553 #endif /* chips */ 554 555 #if defined(BCM_56560_A0) 556 { /* SOC_FORMAT_INT_CAPWAP_WIRELESS_SPECIFIC_HDR_BCM56560_A0fmt */ 557 /* format CAPWAP_WIRELESS_SPECIFIC_HDRfmt */ 558 /* nFields */ 3, 559 /* *fields */ soc_CAPWAP_WIRELESS_SPECIFIC_HDR_BCM53400_A0fmt_fields, 560 /* bits */ 64, 561 /* flags */ 0, 562 }, 563 #endif /* chips */ 564 565 #if defined(BCM_56560_B0) 566 { /* SOC_FORMAT_INT_CAPWAP_WIRELESS_SPECIFIC_HDR_BCM56560_B0fmt */ 567 /* format CAPWAP_WIRELESS_SPECIFIC_HDRfmt */ 568 /* nFields */ 3, 569 /* *fields */ soc_CAPWAP_WIRELESS_SPECIFIC_HDR_BCM53400_A0fmt_fields, 570 /* bits */ 64, 571 /* flags */ 0, 572 }, 573 #endif /* chips */ 574 575 #if defined(BCM_56670_A0) 576 { /* SOC_FORMAT_INT_CAPWAP_WIRELESS_SPECIFIC_HDR_BCM56670_A0fmt */ 577 /* format CAPWAP_WIRELESS_SPECIFIC_HDRfmt */ 578 /* nFields */ 3, 579 /* *fields */ soc_CAPWAP_WIRELESS_SPECIFIC_HDR_BCM53400_A0fmt_fields, 580 /* bits */ 64, 581 /* flags */ 0, 582 }, 583 #endif /* chips */ 584 585 #if defined(BCM_56670_B0) 586 { /* SOC_FORMAT_INT_CAPWAP_WIRELESS_SPECIFIC_HDR_BCM56670_B0fmt */ 587 /* format CAPWAP_WIRELESS_SPECIFIC_HDRfmt */ 588 /* nFields */ 3, 589 /* *fields */ soc_CAPWAP_WIRELESS_SPECIFIC_HDR_BCM53400_A0fmt_fields, 590 /* bits */ 64, 591 /* flags */ 0, 592 }, 593 #endif /* chips */ 594 595 #if defined(BCM_56770_A0) 596 { /* SOC_FORMAT_INT_CAPWAP_WIRELESS_SPECIFIC_HDR_BCM56770_A0fmt */ 597 /* format CAPWAP_WIRELESS_SPECIFIC_HDRfmt */ 598 /* nFields */ 3, 599 /* *fields */ soc_CAPWAP_WIRELESS_SPECIFIC_HDR_BCM56870_A0fmt_fields, 600 /* bits */ 64, 601 /* flags */ 0, 602 }, 603 #endif /* chips */ 604 605 #if defined(BCM_56870_A0) 606 { /* SOC_FORMAT_INT_CAPWAP_WIRELESS_SPECIFIC_HDR_BCM56870_A0fmt */ 607 /* format CAPWAP_WIRELESS_SPECIFIC_HDRfmt */ 608 /* nFields */ 3, 609 /* *fields */ soc_CAPWAP_WIRELESS_SPECIFIC_HDR_BCM56870_A0fmt_fields, 610 /* bits */ 64, 611 /* flags */ 0, 612 }, 613 #endif /* chips */ 614 615 #if defined(BCM_56960_A0) 616 { /* SOC_FORMAT_INT_CAPWAP_WIRELESS_SPECIFIC_HDR_BCM56960_A0fmt */ 617 /* format CAPWAP_WIRELESS_SPECIFIC_HDRfmt */ 618 /* nFields */ 3, 619 /* *fields */ soc_CAPWAP_WIRELESS_SPECIFIC_HDR_BCM53400_A0fmt_fields, 620 /* bits */ 64, 621 /* flags */ 0, 622 }, 623 #endif /* chips */ 624 625 #if defined(BCM_56965_A0) 626 { /* SOC_FORMAT_INT_CAPWAP_WIRELESS_SPECIFIC_HDR_BCM56965_A0fmt */ 627 /* format CAPWAP_WIRELESS_SPECIFIC_HDRfmt */ 628 /* nFields */ 3, 629 /* *fields */ soc_CAPWAP_WIRELESS_SPECIFIC_HDR_BCM53400_A0fmt_fields, 630 /* bits */ 64, 631 /* flags */ 0, 632 }, 633 #endif /* chips */ 634 635 #if defined(BCM_56970_A0) 636 { /* SOC_FORMAT_INT_CAPWAP_WIRELESS_SPECIFIC_HDR_BCM56970_A0fmt */ 637 /* format CAPWAP_WIRELESS_SPECIFIC_HDRfmt */ 638 /* nFields */ 3, 639 /* *fields */ soc_CAPWAP_WIRELESS_SPECIFIC_HDR_BCM53400_A0fmt_fields, 640 /* bits */ 64, 641 /* flags */ 0, 642 }, 643 #endif /* chips */ 644 645 #if defined(BCM_56980_A0) 646 { /* SOC_FORMAT_INT_CAPWAP_WIRELESS_SPECIFIC_HDR_BCM56980_A0fmt */ 647 /* format CAPWAP_WIRELESS_SPECIFIC_HDRfmt */ 648 /* nFields */ 3, 649 /* *fields */ soc_CAPWAP_WIRELESS_SPECIFIC_HDR_BCM53400_A0fmt_fields, 650 /* bits */ 64, 651 /* flags */ 0, 652 }, 653 #endif /* chips */ 654 655 #if defined(BCM_56980_B0) 656 { /* SOC_FORMAT_INT_CAPWAP_WIRELESS_SPECIFIC_HDR_BCM56980_B0fmt */ 657 /* format CAPWAP_WIRELESS_SPECIFIC_HDRfmt */ 658 /* nFields */ 3, 659 /* *fields */ soc_CAPWAP_WIRELESS_SPECIFIC_HDR_BCM53400_A0fmt_fields, 660 /* bits */ 64, 661 /* flags */ 0, 662 }, 663 #endif /* chips */ 664 665 #if defined(BCM_56725_A0) || defined(BCM_56820_A0) || \ 666 defined(BCM_88732_A0) 667 { /* SOC_FORMAT_INT_CBP2M_COSQfmt */ 668 /* format CBP2M_COSQfmt */ 669 /* nFields */ 1, 670 /* *fields */ soc_CBP2M_COSQfmt_fields, 671 /* bits */ 10, 672 /* flags */ 0, 673 }, 674 #endif /* chips */ 675 676 #if defined(BCM_56725_A0) || defined(BCM_56820_A0) 677 { /* SOC_FORMAT_INT_CBP2M_COSQ_CPU_PORTfmt */ 678 /* format CBP2M_COSQ_CPU_PORTfmt */ 679 /* nFields */ 1, 680 /* *fields */ soc_CBP2M_COSQ_CPU_PORTfmt_fields, 681 /* bits */ 32, 682 /* flags */ 0, 683 }, 684 #endif /* chips */ 685 686 #if defined(BCM_88732_A0) 687 { /* SOC_FORMAT_INT_CBP2M_COSQ_CPU_PORT_BCM88732_A0fmt */ 688 /* format CBP2M_COSQ_CPU_PORTfmt */ 689 /* nFields */ 1, 690 /* *fields */ soc_CBP2M_COSQfmt_fields, 691 /* bits */ 10, 692 /* flags */ 0, 693 }, 694 #endif /* chips */ 695 696 #if defined(BCM_56725_A0) || defined(BCM_56820_A0) 697 { /* SOC_FORMAT_INT_CBP2M_EPORTS_S0fmt */ 698 /* format CBP2M_EPORTS_S0fmt */ 699 /* nFields */ 1, 700 /* *fields */ soc_CBP2M_EPORTS_S0fmt_fields, 701 /* bits */ 13, 702 /* flags */ 0, 703 }, 704 #endif /* chips */ 705 706 #if defined(BCM_88732_A0) 707 { /* SOC_FORMAT_INT_CBP2M_EPORTS_S0_BCM88732_A0fmt */ 708 /* format CBP2M_EPORTS_S0fmt */ 709 /* nFields */ 1, 710 /* *fields */ soc_CBP2M_EPORTS_S0_BCM88732_A0fmt_fields, 711 /* bits */ 17, 712 /* flags */ 0, 713 }, 714 #endif /* chips */ 715 716 #if defined(BCM_56725_A0) || defined(BCM_56820_A0) 717 { /* SOC_FORMAT_INT_CBP2M_MEMfmt */ 718 /* format CBP2M_MEMfmt */ 719 /* nFields */ 1, 720 /* *fields */ soc_CBP2M_MEMfmt_fields, 721 /* bits */ 14, 722 /* flags */ 0, 723 }, 724 #endif /* chips */ 725 726 #if defined(BCM_88732_A0) 727 { /* SOC_FORMAT_INT_CBP2M_MEM_BCM88732_A0fmt */ 728 /* format CBP2M_MEMfmt */ 729 /* nFields */ 1, 730 /* *fields */ soc_CBP2M_MEM_BCM88732_A0fmt_fields, 731 /* bits */ 17, 732 /* flags */ 0, 733 }, 734 #endif /* chips */ 735 736 #if defined(BCM_56725_A0) || defined(BCM_56820_A0) 737 { /* SOC_FORMAT_INT_CBP2M_PORTSfmt */ 738 /* format CBP2M_PORTSfmt */ 739 /* nFields */ 1, 740 /* *fields */ soc_CBP2M_PORTSfmt_fields, 741 /* bits */ 29, 742 /* flags */ 0, 743 }, 744 #endif /* chips */ 745 746 #if defined(BCM_88732_A0) 747 { /* SOC_FORMAT_INT_CBP2M_PORTS_BCM88732_A0fmt */ 748 /* format CBP2M_PORTSfmt */ 749 /* nFields */ 1, 750 /* *fields */ soc_CBP2M_MEM_BCM88732_A0fmt_fields, 751 /* bits */ 17, 752 /* flags */ 0, 753 }, 754 #endif /* chips */ 755 756 #if defined(BCM_56725_A0) || defined(BCM_56820_A0) 757 { /* SOC_FORMAT_INT_CBP2M_PORTS_REL_S1fmt */ 758 /* format CBP2M_PORTS_REL_S1fmt */ 759 /* nFields */ 1, 760 /* *fields */ soc_CBP2M_PORTS_REL_S1fmt_fields, 761 /* bits */ 16, 762 /* flags */ 0, 763 }, 764 #endif /* chips */ 765 766 #if defined(BCM_56725_A0) || defined(BCM_56820_A0) 767 { /* SOC_FORMAT_INT_CBP2M_PORTS_S0fmt */ 768 /* format CBP2M_PORTS_S0fmt */ 769 /* nFields */ 1, 770 /* *fields */ soc_CBP2M_PORTS_S0fmt_fields, 771 /* bits */ 13, 772 /* flags */ 0, 773 }, 774 #endif /* chips */ 775 776 #if defined(BCM_56725_A0) || defined(BCM_56820_A0) 777 { /* SOC_FORMAT_INT_CBP2M_PORTS_S1fmt */ 778 /* format CBP2M_PORTS_S1fmt */ 779 /* nFields */ 1, 780 /* *fields */ soc_CBP2M_PORTS_S1fmt_fields, 781 /* bits */ 29, 782 /* flags */ 0, 783 }, 784 #endif /* chips */ 785 786 #if defined(BCM_88732_A0) 787 { /* SOC_FORMAT_INT_CBP2M_PORTS_S0_BCM88732_A0fmt */ 788 /* format CBP2M_PORTS_S0fmt */ 789 /* nFields */ 1, 790 /* *fields */ soc_CBP2M_MEM_BCM88732_A0fmt_fields, 791 /* bits */ 17, 792 /* flags */ 0, 793 }, 794 #endif /* chips */ 795 796 #if defined(BCM_56725_A0) || defined(BCM_56820_A0) || \ 797 defined(BCM_88732_A0) 798 { /* SOC_FORMAT_INT_CBP2M_Qfmt */ 799 /* format CBP2M_Qfmt */ 800 /* nFields */ 1, 801 /* *fields */ soc_CBP2M_Qfmt_fields, 802 /* bits */ 11, 803 /* flags */ 0, 804 }, 805 #endif /* chips */ 806 807 #if defined(BCM_56725_A0) || defined(BCM_56820_A0) 808 { /* SOC_FORMAT_INT_CBP2M_Q_CPU_PORTfmt */ 809 /* format CBP2M_Q_CPU_PORTfmt */ 810 /* nFields */ 1, 811 /* *fields */ soc_CBP2M_Q_CPU_PORTfmt_fields, 812 /* bits */ 33, 813 /* flags */ 0, 814 }, 815 #endif /* chips */ 816 817 #if defined(BCM_88732_A0) 818 { /* SOC_FORMAT_INT_CBP2M_Q_CPU_PORT_BCM88732_A0fmt */ 819 /* format CBP2M_Q_CPU_PORTfmt */ 820 /* nFields */ 1, 821 /* *fields */ soc_CBP2M_Qfmt_fields, 822 /* bits */ 11, 823 /* flags */ 0, 824 }, 825 #endif /* chips */ 826 827 #if defined(BCM_56725_A0) || defined(BCM_56820_A0) 828 { /* SOC_FORMAT_INT_CBP2M_SAVED_SOP_INFO_S0fmt */ 829 /* format CBP2M_SAVED_SOP_INFO_S0fmt */ 830 /* nFields */ 1, 831 /* *fields */ soc_CBP2M_SAVED_SOP_INFO_S0fmt_fields, 832 /* bits */ 42, 833 /* flags */ 0, 834 }, 835 #endif /* chips */ 836 837 #if defined(BCM_56725_A0) || defined(BCM_56820_A0) 838 { /* SOC_FORMAT_INT_CBP2M_SAVED_SOP_INFO_S1fmt */ 839 /* format CBP2M_SAVED_SOP_INFO_S1fmt */ 840 /* nFields */ 1, 841 /* *fields */ soc_CBP2M_SAVED_SOP_INFO_S1fmt_fields, 842 /* bits */ 41, 843 /* flags */ 0, 844 }, 845 #endif /* chips */ 846 847 #if defined(BCM_88732_A0) 848 { /* SOC_FORMAT_INT_CBP2M_SAVED_SOP_INFO_S0_BCM88732_A0fmt */ 849 /* format CBP2M_SAVED_SOP_INFO_S0fmt */ 850 /* nFields */ 1, 851 /* *fields */ soc_CBP2M_SAVED_SOP_INFO_S0_BCM88732_A0fmt_fields, 852 /* bits */ 43, 853 /* flags */ 0, 854 }, 855 #endif /* chips */ 856 857 #if defined(BCM_56840_A0) 858 { /* SOC_FORMAT_INT_CCBEfmt */ 859 /* format CCBEfmt */ 860 /* nFields */ 32, 861 /* *fields */ soc_CCBEfmt_fields, 862 /* bits */ 163, 863 /* flags */ 0, 864 }, 865 #endif /* chips */ 866 867 #if defined(BCM_56260_A0) 868 { /* SOC_FORMAT_INT_CCBE_BCM56260_A0fmt */ 869 /* format CCBEfmt */ 870 /* nFields */ 46, 871 /* *fields */ soc_CCBE_BCM56260_A0fmt_fields, 872 /* bits */ 353, 873 /* flags */ 0, 874 }, 875 #endif /* chips */ 876 877 #if defined(BCM_56260_B0) 878 { /* SOC_FORMAT_INT_CCBE_BCM56260_B0fmt */ 879 /* format CCBEfmt */ 880 /* nFields */ 46, 881 /* *fields */ soc_CCBE_BCM56260_A0fmt_fields, 882 /* bits */ 353, 883 /* flags */ 0, 884 }, 885 #endif /* chips */ 886 887 #if defined(BCM_56270_A0) 888 { /* SOC_FORMAT_INT_CCBE_BCM56270_A0fmt */ 889 /* format CCBEfmt */ 890 /* nFields */ 48, 891 /* *fields */ soc_CCBE_BCM56270_A0fmt_fields, 892 /* bits */ 353, 893 /* flags */ 0, 894 }, 895 #endif /* chips */ 896 897 #if defined(BCM_56340_A0) 898 { /* SOC_FORMAT_INT_CCBE_BCM56340_A0fmt */ 899 /* format CCBEfmt */ 900 /* nFields */ 50, 901 /* *fields */ soc_CCBE_BCM56340_A0fmt_fields, 902 /* bits */ 309, 903 /* flags */ 0, 904 }, 905 #endif /* chips */ 906 907 #if defined(BCM_56370_A0) 908 { /* SOC_FORMAT_INT_CCBE_BCM56370_A0fmt */ 909 /* format CCBEfmt */ 910 /* nFields */ 23, 911 /* *fields */ soc_CCBE_BCM56370_A0fmt_fields, 912 /* bits */ 101, 913 /* flags */ 0, 914 }, 915 #endif /* chips */ 916 917 #if defined(BCM_56440_A0) 918 { /* SOC_FORMAT_INT_CCBE_BCM56440_A0fmt */ 919 /* format CCBEfmt */ 920 /* nFields */ 23, 921 /* *fields */ soc_CCBE_BCM56440_A0fmt_fields, 922 /* bits */ 109, 923 /* flags */ 0, 924 }, 925 #endif /* chips */ 926 927 #if defined(BCM_56440_B0) 928 { /* SOC_FORMAT_INT_CCBE_BCM56440_B0fmt */ 929 /* format CCBEfmt */ 930 /* nFields */ 23, 931 /* *fields */ soc_CCBE_BCM56440_A0fmt_fields, 932 /* bits */ 109, 933 /* flags */ 0, 934 }, 935 #endif /* chips */ 936 937 #if defined(BCM_56450_A0) 938 { /* SOC_FORMAT_INT_CCBE_BCM56450_A0fmt */ 939 /* format CCBEfmt */ 940 /* nFields */ 47, 941 /* *fields */ soc_CCBE_BCM56450_A0fmt_fields, 942 /* bits */ 353, 943 /* flags */ 0, 944 }, 945 #endif /* chips */ 946 947 #if defined(BCM_56450_B0) 948 { /* SOC_FORMAT_INT_CCBE_BCM56450_B0fmt */ 949 /* format CCBEfmt */ 950 /* nFields */ 47, 951 /* *fields */ soc_CCBE_BCM56450_A0fmt_fields, 952 /* bits */ 353, 953 /* flags */ 0, 954 }, 955 #endif /* chips */ 956 957 #if defined(BCM_56450_B1) 958 { /* SOC_FORMAT_INT_CCBE_BCM56450_B1fmt */ 959 /* format CCBEfmt */ 960 /* nFields */ 47, 961 /* *fields */ soc_CCBE_BCM56450_A0fmt_fields, 962 /* bits */ 353, 963 /* flags */ 0, 964 }, 965 #endif /* chips */ 966 967 #if defined(BCM_56560_A0) 968 { /* SOC_FORMAT_INT_CCBE_BCM56560_A0fmt */ 969 /* format CCBEfmt */ 970 /* nFields */ 33, 971 /* *fields */ soc_CCBE_BCM56560_A0fmt_fields, 972 /* bits */ 200, 973 /* flags */ 0, 974 }, 975 #endif /* chips */ 976 977 #if defined(BCM_56560_B0) 978 { /* SOC_FORMAT_INT_CCBE_BCM56560_B0fmt */ 979 /* format CCBEfmt */ 980 /* nFields */ 33, 981 /* *fields */ soc_CCBE_BCM56560_A0fmt_fields, 982 /* bits */ 200, 983 /* flags */ 0, 984 }, 985 #endif /* chips */ 986 987 #if defined(BCM_56640_A0) 988 { /* SOC_FORMAT_INT_CCBE_BCM56640_A0fmt */ 989 /* format CCBEfmt */ 990 /* nFields */ 49, 991 /* *fields */ soc_CCBE_BCM56640_A0fmt_fields, 992 /* bits */ 309, 993 /* flags */ 0, 994 }, 995 #endif /* chips */ 996 997 #if defined(BCM_56670_A0) 998 { /* SOC_FORMAT_INT_CCBE_BCM56670_A0fmt */ 999 /* format CCBEfmt */ 1000 /* nFields */ 35, 1001 /* *fields */ soc_CCBE_BCM56670_A0fmt_fields, 1002 /* bits */ 200, 1003 /* flags */ 0, 1004 }, 1005 #endif /* chips */ 1006 1007 #if defined(BCM_56670_B0) 1008 { /* SOC_FORMAT_INT_CCBE_BCM56670_B0fmt */ 1009 /* format CCBEfmt */ 1010 /* nFields */ 35, 1011 /* *fields */ soc_CCBE_BCM56670_A0fmt_fields, 1012 /* bits */ 200, 1013 /* flags */ 0, 1014 }, 1015 #endif /* chips */ 1016 1017 #if defined(BCM_56770_A0) 1018 { /* SOC_FORMAT_INT_CCBE_BCM56770_A0fmt */ 1019 /* format CCBEfmt */ 1020 /* nFields */ 22, 1021 /* *fields */ soc_CCBE_BCM56870_A0fmt_fields, 1022 /* bits */ 105, 1023 /* flags */ 0, 1024 }, 1025 #endif /* chips */ 1026 1027 #if defined(BCM_56840_B0) 1028 { /* SOC_FORMAT_INT_CCBE_BCM56840_B0fmt */ 1029 /* format CCBEfmt */ 1030 /* nFields */ 32, 1031 /* *fields */ soc_CCBE_BCM56840_B0fmt_fields, 1032 /* bits */ 163, 1033 /* flags */ 0, 1034 }, 1035 #endif /* chips */ 1036 1037 #if defined(BCM_56850_A0) 1038 { /* SOC_FORMAT_INT_CCBE_BCM56850_A0fmt */ 1039 /* format CCBEfmt */ 1040 /* nFields */ 38, 1041 /* *fields */ soc_CCBE_BCM56850_A0fmt_fields, 1042 /* bits */ 181, 1043 /* flags */ 0, 1044 }, 1045 #endif /* chips */ 1046 1047 #if defined(BCM_56860_A0) 1048 { /* SOC_FORMAT_INT_CCBE_BCM56860_A0fmt */ 1049 /* format CCBEfmt */ 1050 /* nFields */ 41, 1051 /* *fields */ soc_CCBE_BCM56860_A0fmt_fields, 1052 /* bits */ 187, 1053 /* flags */ 0, 1054 }, 1055 #endif /* chips */ 1056 1057 #if defined(BCM_56870_A0) 1058 { /* SOC_FORMAT_INT_CCBE_BCM56870_A0fmt */ 1059 /* format CCBEfmt */ 1060 /* nFields */ 22, 1061 /* *fields */ soc_CCBE_BCM56870_A0fmt_fields, 1062 /* bits */ 105, 1063 /* flags */ 0, 1064 }, 1065 #endif /* chips */ 1066 1067 #if defined(BCM_56960_A0) 1068 { /* SOC_FORMAT_INT_CCBE_BCM56960_A0fmt */ 1069 /* format CCBEfmt */ 1070 /* nFields */ 22, 1071 /* *fields */ soc_CCBE_BCM56960_A0fmt_fields, 1072 /* bits */ 101, 1073 /* flags */ 0, 1074 }, 1075 #endif /* chips */ 1076 1077 #if defined(BCM_56965_A0) 1078 { /* SOC_FORMAT_INT_CCBE_BCM56965_A0fmt */ 1079 /* format CCBEfmt */ 1080 /* nFields */ 22, 1081 /* *fields */ soc_CCBE_BCM56960_A0fmt_fields, 1082 /* bits */ 101, 1083 /* flags */ 0, 1084 }, 1085 #endif /* chips */ 1086 1087 #if defined(BCM_56970_A0) 1088 { /* SOC_FORMAT_INT_CCBE_BCM56970_A0fmt */ 1089 /* format CCBEfmt */ 1090 /* nFields */ 24, 1091 /* *fields */ soc_CCBE_BCM56970_A0fmt_fields, 1092 /* bits */ 107, 1093 /* flags */ 0, 1094 }, 1095 #endif /* chips */ 1096 1097 #if defined(BCM_56980_A0) 1098 { /* SOC_FORMAT_INT_CCBE_BCM56980_A0fmt */ 1099 /* format CCBEfmt */ 1100 /* nFields */ 22, 1101 /* *fields */ soc_CCBE_BCM56980_A0fmt_fields, 1102 /* bits */ 93, 1103 /* flags */ 0, 1104 }, 1105 #endif /* chips */ 1106 1107 #if defined(BCM_56980_B0) 1108 { /* SOC_FORMAT_INT_CCBE_BCM56980_B0fmt */ 1109 /* format CCBEfmt */ 1110 /* nFields */ 22, 1111 /* *fields */ soc_CCBE_BCM56980_A0fmt_fields, 1112 /* bits */ 93, 1113 /* flags */ 0, 1114 }, 1115 #endif /* chips */ 1116 1117 #if defined(BCM_56840_A0) 1118 { /* SOC_FORMAT_INT_CCBIfmt */ 1119 /* format CCBIfmt */ 1120 /* nFields */ 31, 1121 /* *fields */ soc_CCBIfmt_fields, 1122 /* bits */ 296, 1123 /* flags */ 0, 1124 }, 1125 #endif /* chips */ 1126 1127 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) || \ 1128 defined(BCM_56970_A0) 1129 { /* SOC_FORMAT_INT_CCBI_Afmt */ 1130 /* format CCBI_Afmt */ 1131 /* nFields */ 4, 1132 /* *fields */ soc_CCBI_Afmt_fields, 1133 /* bits */ 11, 1134 /* flags */ 0, 1135 }, 1136 #endif /* chips */ 1137 1138 #if defined(BCM_56370_A0) 1139 { /* SOC_FORMAT_INT_CCBI_A_BCM56370_A0fmt */ 1140 /* format CCBI_Afmt */ 1141 /* nFields */ 5, 1142 /* *fields */ soc_CCBI_A_BCM56370_A0fmt_fields, 1143 /* bits */ 10, 1144 /* flags */ 0, 1145 }, 1146 #endif /* chips */ 1147 1148 #if defined(BCM_56770_A0) 1149 { /* SOC_FORMAT_INT_CCBI_A_BCM56770_A0fmt */ 1150 /* format CCBI_Afmt */ 1151 /* nFields */ 5, 1152 /* *fields */ soc_CCBI_A_BCM56870_A0fmt_fields, 1153 /* bits */ 11, 1154 /* flags */ 0, 1155 }, 1156 #endif /* chips */ 1157 1158 #if defined(BCM_56870_A0) 1159 { /* SOC_FORMAT_INT_CCBI_A_BCM56870_A0fmt */ 1160 /* format CCBI_Afmt */ 1161 /* nFields */ 5, 1162 /* *fields */ soc_CCBI_A_BCM56870_A0fmt_fields, 1163 /* bits */ 11, 1164 /* flags */ 0, 1165 }, 1166 #endif /* chips */ 1167 1168 #if defined(BCM_56980_A0) 1169 { /* SOC_FORMAT_INT_CCBI_A_BCM56980_A0fmt */ 1170 /* format CCBI_Afmt */ 1171 /* nFields */ 4, 1172 /* *fields */ soc_CCBI_A_BCM56980_A0fmt_fields, 1173 /* bits */ 11, 1174 /* flags */ 0, 1175 }, 1176 #endif /* chips */ 1177 1178 #if defined(BCM_56980_B0) 1179 { /* SOC_FORMAT_INT_CCBI_A_BCM56980_B0fmt */ 1180 /* format CCBI_Afmt */ 1181 /* nFields */ 4, 1182 /* *fields */ soc_CCBI_A_BCM56980_A0fmt_fields, 1183 /* bits */ 11, 1184 /* flags */ 0, 1185 }, 1186 #endif /* chips */ 1187 1188 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) 1189 { /* SOC_FORMAT_INT_CCBI_Bfmt */ 1190 /* format CCBI_Bfmt */ 1191 /* nFields */ 29, 1192 /* *fields */ soc_CCBI_Bfmt_fields, 1193 /* bits */ 412, 1194 /* flags */ 0, 1195 }, 1196 #endif /* chips */ 1197 1198 #if defined(BCM_56260_A0) 1199 { /* SOC_FORMAT_INT_CCBI_BCM56260_A0fmt */ 1200 /* format CCBIfmt */ 1201 /* nFields */ 43, 1202 /* *fields */ soc_CCBI_BCM56260_A0fmt_fields, 1203 /* bits */ 412, 1204 /* flags */ 0, 1205 }, 1206 #endif /* chips */ 1207 1208 #if defined(BCM_56260_B0) 1209 { /* SOC_FORMAT_INT_CCBI_BCM56260_B0fmt */ 1210 /* format CCBIfmt */ 1211 /* nFields */ 43, 1212 /* *fields */ soc_CCBI_BCM56260_A0fmt_fields, 1213 /* bits */ 412, 1214 /* flags */ 0, 1215 }, 1216 #endif /* chips */ 1217 1218 #if defined(BCM_56270_A0) 1219 { /* SOC_FORMAT_INT_CCBI_BCM56270_A0fmt */ 1220 /* format CCBIfmt */ 1221 /* nFields */ 43, 1222 /* *fields */ soc_CCBI_BCM56270_A0fmt_fields, 1223 /* bits */ 259, 1224 /* flags */ 0, 1225 }, 1226 #endif /* chips */ 1227 1228 #if defined(BCM_56340_A0) 1229 { /* SOC_FORMAT_INT_CCBI_BCM56340_A0fmt */ 1230 /* format CCBIfmt */ 1231 /* nFields */ 46, 1232 /* *fields */ soc_CCBI_BCM56340_A0fmt_fields, 1233 /* bits */ 310, 1234 /* flags */ 0, 1235 }, 1236 #endif /* chips */ 1237 1238 #if defined(BCM_56370_A0) 1239 { /* SOC_FORMAT_INT_CCBI_BCM56370_A0fmt */ 1240 /* format CCBIfmt */ 1241 /* nFields */ 43, 1242 /* *fields */ soc_CCBI_BCM56370_A0fmt_fields, 1243 /* bits */ 463, 1244 /* flags */ 0, 1245 }, 1246 #endif /* chips */ 1247 1248 #if defined(BCM_56440_A0) 1249 { /* SOC_FORMAT_INT_CCBI_BCM56440_A0fmt */ 1250 /* format CCBIfmt */ 1251 /* nFields */ 33, 1252 /* *fields */ soc_CCBI_BCM56440_A0fmt_fields, 1253 /* bits */ 223, 1254 /* flags */ 0, 1255 }, 1256 #endif /* chips */ 1257 1258 #if defined(BCM_56440_B0) 1259 { /* SOC_FORMAT_INT_CCBI_BCM56440_B0fmt */ 1260 /* format CCBIfmt */ 1261 /* nFields */ 33, 1262 /* *fields */ soc_CCBI_BCM56440_A0fmt_fields, 1263 /* bits */ 223, 1264 /* flags */ 0, 1265 }, 1266 #endif /* chips */ 1267 1268 #if defined(BCM_56450_A0) 1269 { /* SOC_FORMAT_INT_CCBI_BCM56450_A0fmt */ 1270 /* format CCBIfmt */ 1271 /* nFields */ 41, 1272 /* *fields */ soc_CCBI_BCM56450_A0fmt_fields, 1273 /* bits */ 563, 1274 /* flags */ 0, 1275 }, 1276 #endif /* chips */ 1277 1278 #if defined(BCM_56450_B0) 1279 { /* SOC_FORMAT_INT_CCBI_BCM56450_B0fmt */ 1280 /* format CCBIfmt */ 1281 /* nFields */ 41, 1282 /* *fields */ soc_CCBI_BCM56450_A0fmt_fields, 1283 /* bits */ 563, 1284 /* flags */ 0, 1285 }, 1286 #endif /* chips */ 1287 1288 #if defined(BCM_56450_B1) 1289 { /* SOC_FORMAT_INT_CCBI_BCM56450_B1fmt */ 1290 /* format CCBIfmt */ 1291 /* nFields */ 41, 1292 /* *fields */ soc_CCBI_BCM56450_A0fmt_fields, 1293 /* bits */ 563, 1294 /* flags */ 0, 1295 }, 1296 #endif /* chips */ 1297 1298 #if defined(BCM_56560_A0) 1299 { /* SOC_FORMAT_INT_CCBI_BCM56560_A0fmt */ 1300 /* format CCBIfmt */ 1301 /* nFields */ 45, 1302 /* *fields */ soc_CCBI_BCM56560_A0fmt_fields, 1303 /* bits */ 416, 1304 /* flags */ 0, 1305 }, 1306 #endif /* chips */ 1307 1308 #if defined(BCM_56560_B0) 1309 { /* SOC_FORMAT_INT_CCBI_BCM56560_B0fmt */ 1310 /* format CCBIfmt */ 1311 /* nFields */ 45, 1312 /* *fields */ soc_CCBI_BCM56560_A0fmt_fields, 1313 /* bits */ 416, 1314 /* flags */ 0, 1315 }, 1316 #endif /* chips */ 1317 1318 #if defined(BCM_56640_A0) 1319 { /* SOC_FORMAT_INT_CCBI_BCM56640_A0fmt */ 1320 /* format CCBIfmt */ 1321 /* nFields */ 45, 1322 /* *fields */ soc_CCBI_BCM56640_A0fmt_fields, 1323 /* bits */ 310, 1324 /* flags */ 0, 1325 }, 1326 #endif /* chips */ 1327 1328 #if defined(BCM_56670_A0) 1329 { /* SOC_FORMAT_INT_CCBI_BCM56670_A0fmt */ 1330 /* format CCBIfmt */ 1331 /* nFields */ 46, 1332 /* *fields */ soc_CCBI_BCM56670_A0fmt_fields, 1333 /* bits */ 380, 1334 /* flags */ 0, 1335 }, 1336 #endif /* chips */ 1337 1338 #if defined(BCM_56670_B0) 1339 { /* SOC_FORMAT_INT_CCBI_BCM56670_B0fmt */ 1340 /* format CCBIfmt */ 1341 /* nFields */ 46, 1342 /* *fields */ soc_CCBI_BCM56670_A0fmt_fields, 1343 /* bits */ 380, 1344 /* flags */ 0, 1345 }, 1346 #endif /* chips */ 1347 1348 #if defined(BCM_56770_A0) 1349 { /* SOC_FORMAT_INT_CCBI_BCM56770_A0fmt */ 1350 /* format CCBIfmt */ 1351 /* nFields */ 41, 1352 /* *fields */ soc_CCBI_BCM56870_A0fmt_fields, 1353 /* bits */ 464, 1354 /* flags */ 0, 1355 }, 1356 #endif /* chips */ 1357 1358 #if defined(BCM_56840_B0) 1359 { /* SOC_FORMAT_INT_CCBI_BCM56840_B0fmt */ 1360 /* format CCBIfmt */ 1361 /* nFields */ 31, 1362 /* *fields */ soc_CCBIfmt_fields, 1363 /* bits */ 296, 1364 /* flags */ 0, 1365 }, 1366 #endif /* chips */ 1367 1368 #if defined(BCM_56850_A0) 1369 { /* SOC_FORMAT_INT_CCBI_BCM56850_A0fmt */ 1370 /* format CCBIfmt */ 1371 /* nFields */ 41, 1372 /* *fields */ soc_CCBI_BCM56850_A0fmt_fields, 1373 /* bits */ 488, 1374 /* flags */ 0, 1375 }, 1376 #endif /* chips */ 1377 1378 #if defined(BCM_56860_A0) 1379 { /* SOC_FORMAT_INT_CCBI_BCM56860_A0fmt */ 1380 /* format CCBIfmt */ 1381 /* nFields */ 44, 1382 /* *fields */ soc_CCBI_BCM56860_A0fmt_fields, 1383 /* bits */ 506, 1384 /* flags */ 0, 1385 }, 1386 #endif /* chips */ 1387 1388 #if defined(BCM_56870_A0) 1389 { /* SOC_FORMAT_INT_CCBI_BCM56870_A0fmt */ 1390 /* format CCBIfmt */ 1391 /* nFields */ 41, 1392 /* *fields */ soc_CCBI_BCM56870_A0fmt_fields, 1393 /* bits */ 464, 1394 /* flags */ 0, 1395 }, 1396 #endif /* chips */ 1397 1398 #if defined(BCM_56960_A0) 1399 { /* SOC_FORMAT_INT_CCBI_BCM56960_A0fmt */ 1400 /* format CCBIfmt */ 1401 /* nFields */ 35, 1402 /* *fields */ soc_CCBI_BCM56960_A0fmt_fields, 1403 /* bits */ 423, 1404 /* flags */ 0, 1405 }, 1406 #endif /* chips */ 1407 1408 #if defined(BCM_56965_A0) 1409 { /* SOC_FORMAT_INT_CCBI_BCM56965_A0fmt */ 1410 /* format CCBIfmt */ 1411 /* nFields */ 35, 1412 /* *fields */ soc_CCBI_BCM56960_A0fmt_fields, 1413 /* bits */ 423, 1414 /* flags */ 0, 1415 }, 1416 #endif /* chips */ 1417 1418 #if defined(BCM_56970_A0) 1419 { /* SOC_FORMAT_INT_CCBI_BCM56970_A0fmt */ 1420 /* format CCBIfmt */ 1421 /* nFields */ 39, 1422 /* *fields */ soc_CCBI_BCM56970_A0fmt_fields, 1423 /* bits */ 463, 1424 /* flags */ 0, 1425 }, 1426 #endif /* chips */ 1427 1428 #if defined(BCM_56980_A0) 1429 { /* SOC_FORMAT_INT_CCBI_BCM56980_A0fmt */ 1430 /* format CCBIfmt */ 1431 /* nFields */ 2, 1432 /* *fields */ soc_CCBI_BCM56980_A0fmt_fields, 1433 /* bits */ 446, 1434 /* flags */ 0, 1435 }, 1436 #endif /* chips */ 1437 1438 #if defined(BCM_56980_B0) 1439 { /* SOC_FORMAT_INT_CCBI_BCM56980_B0fmt */ 1440 /* format CCBIfmt */ 1441 /* nFields */ 2, 1442 /* *fields */ soc_CCBI_BCM56980_A0fmt_fields, 1443 /* bits */ 446, 1444 /* flags */ 0, 1445 }, 1446 #endif /* chips */ 1447 1448 #if defined(BCM_56370_A0) 1449 { /* SOC_FORMAT_INT_CCBI_B_BCM56370_A0fmt */ 1450 /* format CCBI_Bfmt */ 1451 /* nFields */ 35, 1452 /* *fields */ soc_CCBI_B_BCM56370_A0fmt_fields, 1453 /* bits */ 442, 1454 /* flags */ 0, 1455 }, 1456 #endif /* chips */ 1457 1458 #if defined(BCM_56770_A0) 1459 { /* SOC_FORMAT_INT_CCBI_B_BCM56770_A0fmt */ 1460 /* format CCBI_Bfmt */ 1461 /* nFields */ 33, 1462 /* *fields */ soc_CCBI_B_BCM56870_A0fmt_fields, 1463 /* bits */ 442, 1464 /* flags */ 0, 1465 }, 1466 #endif /* chips */ 1467 1468 #if defined(BCM_56870_A0) 1469 { /* SOC_FORMAT_INT_CCBI_B_BCM56870_A0fmt */ 1470 /* format CCBI_Bfmt */ 1471 /* nFields */ 33, 1472 /* *fields */ soc_CCBI_B_BCM56870_A0fmt_fields, 1473 /* bits */ 442, 1474 /* flags */ 0, 1475 }, 1476 #endif /* chips */ 1477 1478 #if defined(BCM_56970_A0) 1479 { /* SOC_FORMAT_INT_CCBI_B_BCM56970_A0fmt */ 1480 /* format CCBI_Bfmt */ 1481 /* nFields */ 33, 1482 /* *fields */ soc_CCBI_B_BCM56970_A0fmt_fields, 1483 /* bits */ 452, 1484 /* flags */ 0, 1485 }, 1486 #endif /* chips */ 1487 1488 #if defined(BCM_56980_A0) 1489 { /* SOC_FORMAT_INT_CCBI_B_BCM56980_A0fmt */ 1490 /* format CCBI_Bfmt */ 1491 /* nFields */ 29, 1492 /* *fields */ soc_CCBI_B_BCM56980_A0fmt_fields, 1493 /* bits */ 435, 1494 /* flags */ 0, 1495 }, 1496 #endif /* chips */ 1497 1498 #if defined(BCM_56980_B0) 1499 { /* SOC_FORMAT_INT_CCBI_B_BCM56980_B0fmt */ 1500 /* format CCBI_Bfmt */ 1501 /* nFields */ 29, 1502 /* *fields */ soc_CCBI_B_BCM56980_A0fmt_fields, 1503 /* bits */ 435, 1504 /* flags */ 0, 1505 }, 1506 #endif /* chips */ 1507 1508 #if defined(BCM_56970_A0) 1509 { /* SOC_FORMAT_INT_CCBI_Cfmt */ 1510 /* format CCBI_Cfmt */ 1511 /* nFields */ 3, 1512 /* *fields */ soc_CCBI_Cfmt_fields, 1513 /* bits */ 10, 1514 /* flags */ 0, 1515 }, 1516 #endif /* chips */ 1517 1518 #if defined(BCM_56370_A0) 1519 { /* SOC_FORMAT_INT_CCBI_C_BCM56370_A0fmt */ 1520 /* format CCBI_Cfmt */ 1521 /* nFields */ 3, 1522 /* *fields */ soc_CCBI_C_BCM56870_A0fmt_fields, 1523 /* bits */ 11, 1524 /* flags */ 0, 1525 }, 1526 #endif /* chips */ 1527 1528 #if defined(BCM_56770_A0) 1529 { /* SOC_FORMAT_INT_CCBI_C_BCM56770_A0fmt */ 1530 /* format CCBI_Cfmt */ 1531 /* nFields */ 3, 1532 /* *fields */ soc_CCBI_C_BCM56870_A0fmt_fields, 1533 /* bits */ 11, 1534 /* flags */ 0, 1535 }, 1536 #endif /* chips */ 1537 1538 #if defined(BCM_56870_A0) 1539 { /* SOC_FORMAT_INT_CCBI_C_BCM56870_A0fmt */ 1540 /* format CCBI_Cfmt */ 1541 /* nFields */ 3, 1542 /* *fields */ soc_CCBI_C_BCM56870_A0fmt_fields, 1543 /* bits */ 11, 1544 /* flags */ 0, 1545 }, 1546 #endif /* chips */ 1547 1548 #if defined(BCM_56980_A0) 1549 { /* SOC_FORMAT_INT_CCBI_C_BCM56980_A0fmt */ 1550 /* format CCBI_Cfmt */ 1551 /* nFields */ 3, 1552 /* *fields */ soc_CCBI_C_BCM56980_A0fmt_fields, 1553 /* bits */ 10, 1554 /* flags */ 0, 1555 }, 1556 #endif /* chips */ 1557 1558 #if defined(BCM_56980_B0) 1559 { /* SOC_FORMAT_INT_CCBI_C_BCM56980_B0fmt */ 1560 /* format CCBI_Cfmt */ 1561 /* nFields */ 3, 1562 /* *fields */ soc_CCBI_C_BCM56980_A0fmt_fields, 1563 /* bits */ 10, 1564 /* flags */ 0, 1565 }, 1566 #endif /* chips */ 1567 1568 #if defined(BCM_56340_A0) || defined(BCM_56640_A0) 1569 { /* SOC_FORMAT_INT_CCP_RESEQfmt */ 1570 /* format CCP_RESEQfmt */ 1571 /* nFields */ 3, 1572 /* *fields */ soc_CCP_RESEQfmt_fields, 1573 /* bits */ 17, 1574 /* flags */ 0, 1575 }, 1576 #endif /* chips */ 1577 1578 #if defined(BCM_56800_A0) 1579 { /* SOC_FORMAT_INT_CCP_S_RFfmt */ 1580 /* format CCP_S_RFfmt */ 1581 /* nFields */ 1, 1582 /* *fields */ soc_CCP_S_RFfmt_fields, 1583 /* bits */ 56, 1584 /* flags */ 0, 1585 }, 1586 #endif /* chips */ 1587 1588 #if defined(BCM_56142_A0) 1589 { /* SOC_FORMAT_INT_CCP_S_RF_BCM56142_A0fmt */ 1590 /* format CCP_S_RFfmt */ 1591 /* nFields */ 1, 1592 /* *fields */ soc_CCP_S_RF_BCM56142_A0fmt_fields, 1593 /* bits */ 36, 1594 /* flags */ 0, 1595 }, 1596 #endif /* chips */ 1597 1598 #if defined(BCM_56260_A0) 1599 { /* SOC_FORMAT_INT_CCP_S_RF_BCM56260_A0fmt */ 1600 /* format CCP_S_RFfmt */ 1601 /* nFields */ 1, 1602 /* *fields */ soc_CCP_S_RF_BCM56260_A0fmt_fields, 1603 /* bits */ 112, 1604 /* flags */ 0, 1605 }, 1606 #endif /* chips */ 1607 1608 #if defined(BCM_56260_B0) 1609 { /* SOC_FORMAT_INT_CCP_S_RF_BCM56260_B0fmt */ 1610 /* format CCP_S_RFfmt */ 1611 /* nFields */ 1, 1612 /* *fields */ soc_CCP_S_RF_BCM56260_A0fmt_fields, 1613 /* bits */ 112, 1614 /* flags */ 0, 1615 }, 1616 #endif /* chips */ 1617 1618 #if defined(BCM_56270_A0) 1619 { /* SOC_FORMAT_INT_CCP_S_RF_BCM56270_A0fmt */ 1620 /* format CCP_S_RFfmt */ 1621 /* nFields */ 1, 1622 /* *fields */ soc_CCP_S_RF_BCM56260_A0fmt_fields, 1623 /* bits */ 112, 1624 /* flags */ 0, 1625 }, 1626 #endif /* chips */ 1627 1628 #if defined(BCM_56334_A0) 1629 { /* SOC_FORMAT_INT_CCP_S_RF_BCM56334_A0fmt */ 1630 /* format CCP_S_RFfmt */ 1631 /* nFields */ 1, 1632 /* *fields */ soc_CCP_S_RF_BCM56334_A0fmt_fields, 1633 /* bits */ 18, 1634 /* flags */ 0, 1635 }, 1636 #endif /* chips */ 1637 1638 #if defined(BCM_56334_B0) 1639 { /* SOC_FORMAT_INT_CCP_S_RF_BCM56334_B0fmt */ 1640 /* format CCP_S_RFfmt */ 1641 /* nFields */ 1, 1642 /* *fields */ soc_CCP_S_RF_BCM56334_A0fmt_fields, 1643 /* bits */ 18, 1644 /* flags */ 0, 1645 }, 1646 #endif /* chips */ 1647 1648 #if defined(BCM_56340_A0) 1649 { /* SOC_FORMAT_INT_CCP_S_RF_BCM56340_A0fmt */ 1650 /* format CCP_S_RFfmt */ 1651 /* nFields */ 1, 1652 /* *fields */ soc_CCP_S_RF_BCM56640_A0fmt_fields, 1653 /* bits */ 112, 1654 /* flags */ 0, 1655 }, 1656 #endif /* chips */ 1657 1658 #if defined(BCM_56440_A0) 1659 { /* SOC_FORMAT_INT_CCP_S_RF_BCM56440_A0fmt */ 1660 /* format CCP_S_RFfmt */ 1661 /* nFields */ 1, 1662 /* *fields */ soc_CCP_S_RF_BCM56634_A0fmt_fields, 1663 /* bits */ 112, 1664 /* flags */ 0, 1665 }, 1666 #endif /* chips */ 1667 1668 #if defined(BCM_56440_B0) 1669 { /* SOC_FORMAT_INT_CCP_S_RF_BCM56440_B0fmt */ 1670 /* format CCP_S_RFfmt */ 1671 /* nFields */ 1, 1672 /* *fields */ soc_CCP_S_RF_BCM56634_A0fmt_fields, 1673 /* bits */ 112, 1674 /* flags */ 0, 1675 }, 1676 #endif /* chips */ 1677 1678 #if defined(BCM_56450_A0) 1679 { /* SOC_FORMAT_INT_CCP_S_RF_BCM56450_A0fmt */ 1680 /* format CCP_S_RFfmt */ 1681 /* nFields */ 1, 1682 /* *fields */ soc_CCP_S_RF_BCM56640_A0fmt_fields, 1683 /* bits */ 112, 1684 /* flags */ 0, 1685 }, 1686 #endif /* chips */ 1687 1688 #if defined(BCM_56450_B0) 1689 { /* SOC_FORMAT_INT_CCP_S_RF_BCM56450_B0fmt */ 1690 /* format CCP_S_RFfmt */ 1691 /* nFields */ 1, 1692 /* *fields */ soc_CCP_S_RF_BCM56640_A0fmt_fields, 1693 /* bits */ 112, 1694 /* flags */ 0, 1695 }, 1696 #endif /* chips */ 1697 1698 #if defined(BCM_56450_B1) 1699 { /* SOC_FORMAT_INT_CCP_S_RF_BCM56450_B1fmt */ 1700 /* format CCP_S_RFfmt */ 1701 /* nFields */ 1, 1702 /* *fields */ soc_CCP_S_RF_BCM56640_A0fmt_fields, 1703 /* bits */ 112, 1704 /* flags */ 0, 1705 }, 1706 #endif /* chips */ 1707 1708 #if defined(BCM_56524_A0) 1709 { /* SOC_FORMAT_INT_CCP_S_RF_BCM56524_A0fmt */ 1710 /* format CCP_S_RFfmt */ 1711 /* nFields */ 1, 1712 /* *fields */ soc_CCP_S_RF_BCM56634_A0fmt_fields, 1713 /* bits */ 112, 1714 /* flags */ 0, 1715 }, 1716 #endif /* chips */ 1717 1718 #if defined(BCM_56524_B0) 1719 { /* SOC_FORMAT_INT_CCP_S_RF_BCM56524_B0fmt */ 1720 /* format CCP_S_RFfmt */ 1721 /* nFields */ 1, 1722 /* *fields */ soc_CCP_S_RF_BCM56634_A0fmt_fields, 1723 /* bits */ 112, 1724 /* flags */ 0, 1725 }, 1726 #endif /* chips */ 1727 1728 #if defined(BCM_56624_A0) 1729 { /* SOC_FORMAT_INT_CCP_S_RF_BCM56624_A0fmt */ 1730 /* format CCP_S_RFfmt */ 1731 /* nFields */ 1, 1732 /* *fields */ soc_CCP_S_RF_BCM56624_A0fmt_fields, 1733 /* bits */ 64, 1734 /* flags */ 0, 1735 }, 1736 #endif /* chips */ 1737 1738 #if defined(BCM_56624_B0) 1739 { /* SOC_FORMAT_INT_CCP_S_RF_BCM56624_B0fmt */ 1740 /* format CCP_S_RFfmt */ 1741 /* nFields */ 1, 1742 /* *fields */ soc_CCP_S_RF_BCM56624_A0fmt_fields, 1743 /* bits */ 64, 1744 /* flags */ 0, 1745 }, 1746 #endif /* chips */ 1747 1748 #if defined(BCM_56634_A0) 1749 { /* SOC_FORMAT_INT_CCP_S_RF_BCM56634_A0fmt */ 1750 /* format CCP_S_RFfmt */ 1751 /* nFields */ 1, 1752 /* *fields */ soc_CCP_S_RF_BCM56634_A0fmt_fields, 1753 /* bits */ 112, 1754 /* flags */ 0, 1755 }, 1756 #endif /* chips */ 1757 1758 #if defined(BCM_56634_B0) 1759 { /* SOC_FORMAT_INT_CCP_S_RF_BCM56634_B0fmt */ 1760 /* format CCP_S_RFfmt */ 1761 /* nFields */ 1, 1762 /* *fields */ soc_CCP_S_RF_BCM56634_A0fmt_fields, 1763 /* bits */ 112, 1764 /* flags */ 0, 1765 }, 1766 #endif /* chips */ 1767 1768 #if defined(BCM_56640_A0) 1769 { /* SOC_FORMAT_INT_CCP_S_RF_BCM56640_A0fmt */ 1770 /* format CCP_S_RFfmt */ 1771 /* nFields */ 1, 1772 /* *fields */ soc_CCP_S_RF_BCM56640_A0fmt_fields, 1773 /* bits */ 112, 1774 /* flags */ 0, 1775 }, 1776 #endif /* chips */ 1777 1778 #if defined(BCM_56680_A0) 1779 { /* SOC_FORMAT_INT_CCP_S_RF_BCM56680_A0fmt */ 1780 /* format CCP_S_RFfmt */ 1781 /* nFields */ 1, 1782 /* *fields */ soc_CCP_S_RF_BCM56624_A0fmt_fields, 1783 /* bits */ 64, 1784 /* flags */ 0, 1785 }, 1786 #endif /* chips */ 1787 1788 #if defined(BCM_56680_B0) 1789 { /* SOC_FORMAT_INT_CCP_S_RF_BCM56680_B0fmt */ 1790 /* format CCP_S_RFfmt */ 1791 /* nFields */ 1, 1792 /* *fields */ soc_CCP_S_RF_BCM56624_A0fmt_fields, 1793 /* bits */ 64, 1794 /* flags */ 0, 1795 }, 1796 #endif /* chips */ 1797 1798 #if defined(BCM_56685_A0) 1799 { /* SOC_FORMAT_INT_CCP_S_RF_BCM56685_A0fmt */ 1800 /* format CCP_S_RFfmt */ 1801 /* nFields */ 1, 1802 /* *fields */ soc_CCP_S_RF_BCM56634_A0fmt_fields, 1803 /* bits */ 112, 1804 /* flags */ 0, 1805 }, 1806 #endif /* chips */ 1807 1808 #if defined(BCM_56685_B0) 1809 { /* SOC_FORMAT_INT_CCP_S_RF_BCM56685_B0fmt */ 1810 /* format CCP_S_RFfmt */ 1811 /* nFields */ 1, 1812 /* *fields */ soc_CCP_S_RF_BCM56634_A0fmt_fields, 1813 /* bits */ 112, 1814 /* flags */ 0, 1815 }, 1816 #endif /* chips */ 1817 1818 #if defined(BCM_56725_A0) 1819 { /* SOC_FORMAT_INT_CCP_S_RF_BCM56725_A0fmt */ 1820 /* format CCP_S_RFfmt */ 1821 /* nFields */ 1, 1822 /* *fields */ soc_CCP_S_RF_BCM56820_A0fmt_fields, 1823 /* bits */ 28, 1824 /* flags */ 0, 1825 }, 1826 #endif /* chips */ 1827 1828 #if defined(BCM_56820_A0) 1829 { /* SOC_FORMAT_INT_CCP_S_RF_BCM56820_A0fmt */ 1830 /* format CCP_S_RFfmt */ 1831 /* nFields */ 1, 1832 /* *fields */ soc_CCP_S_RF_BCM56820_A0fmt_fields, 1833 /* bits */ 28, 1834 /* flags */ 0, 1835 }, 1836 #endif /* chips */ 1837 1838 #if defined(BCM_56840_A0) 1839 { /* SOC_FORMAT_INT_CCP_S_RF_BCM56840_A0fmt */ 1840 /* format CCP_S_RFfmt */ 1841 /* nFields */ 1, 1842 /* *fields */ soc_CCP_S_RF_BCM56634_A0fmt_fields, 1843 /* bits */ 112, 1844 /* flags */ 0, 1845 }, 1846 #endif /* chips */ 1847 1848 #if defined(BCM_56840_B0) 1849 { /* SOC_FORMAT_INT_CCP_S_RF_BCM56840_B0fmt */ 1850 /* format CCP_S_RFfmt */ 1851 /* nFields */ 1, 1852 /* *fields */ soc_CCP_S_RF_BCM56634_A0fmt_fields, 1853 /* bits */ 112, 1854 /* flags */ 0, 1855 }, 1856 #endif /* chips */ 1857 1858 #if defined(BCM_56850_A0) || defined(BCM_56860_A0) 1859 { /* SOC_FORMAT_INT_CCP_TO_ENQ_INFO_BUSfmt */ 1860 /* format CCP_TO_ENQ_INFO_BUSfmt */ 1861 /* nFields */ 1, 1862 /* *fields */ soc_CCP_TO_ENQ_INFO_BUSfmt_fields, 1863 /* bits */ 7, 1864 /* flags */ 0, 1865 }, 1866 #endif /* chips */ 1867 1868 #if defined(BCM_56370_A0) 1869 { /* SOC_FORMAT_INT_CCP_TO_ENQ_INFO_BUS_BCM56370_A0fmt */ 1870 /* format CCP_TO_ENQ_INFO_BUSfmt */ 1871 /* nFields */ 1, 1872 /* *fields */ soc_CCP_TO_ENQ_INFO_BUS_BCM56560_A0fmt_fields, 1873 /* bits */ 7, 1874 /* flags */ 0, 1875 }, 1876 #endif /* chips */ 1877 1878 #if defined(BCM_56560_A0) 1879 { /* SOC_FORMAT_INT_CCP_TO_ENQ_INFO_BUS_BCM56560_A0fmt */ 1880 /* format CCP_TO_ENQ_INFO_BUSfmt */ 1881 /* nFields */ 1, 1882 /* *fields */ soc_CCP_TO_ENQ_INFO_BUS_BCM56560_A0fmt_fields, 1883 /* bits */ 7, 1884 /* flags */ 0, 1885 }, 1886 #endif /* chips */ 1887 1888 #if defined(BCM_56560_B0) 1889 { /* SOC_FORMAT_INT_CCP_TO_ENQ_INFO_BUS_BCM56560_B0fmt */ 1890 /* format CCP_TO_ENQ_INFO_BUSfmt */ 1891 /* nFields */ 1, 1892 /* *fields */ soc_CCP_TO_ENQ_INFO_BUS_BCM56560_A0fmt_fields, 1893 /* bits */ 7, 1894 /* flags */ 0, 1895 }, 1896 #endif /* chips */ 1897 1898 #if defined(BCM_56670_A0) 1899 { /* SOC_FORMAT_INT_CCP_TO_ENQ_INFO_BUS_BCM56670_A0fmt */ 1900 /* format CCP_TO_ENQ_INFO_BUSfmt */ 1901 /* nFields */ 1, 1902 /* *fields */ soc_CCP_TO_ENQ_INFO_BUS_BCM56560_A0fmt_fields, 1903 /* bits */ 7, 1904 /* flags */ 0, 1905 }, 1906 #endif /* chips */ 1907 1908 #if defined(BCM_56670_B0) 1909 { /* SOC_FORMAT_INT_CCP_TO_ENQ_INFO_BUS_BCM56670_B0fmt */ 1910 /* format CCP_TO_ENQ_INFO_BUSfmt */ 1911 /* nFields */ 1, 1912 /* *fields */ soc_CCP_TO_ENQ_INFO_BUS_BCM56560_A0fmt_fields, 1913 /* bits */ 7, 1914 /* flags */ 0, 1915 }, 1916 #endif /* chips */ 1917 1918 #if defined(BCM_56770_A0) 1919 { /* SOC_FORMAT_INT_CCP_TO_ENQ_INFO_BUS_BCM56770_A0fmt */ 1920 /* format CCP_TO_ENQ_INFO_BUSfmt */ 1921 /* nFields */ 1, 1922 /* *fields */ soc_CCP_TO_ENQ_INFO_BUS_BCM56560_A0fmt_fields, 1923 /* bits */ 7, 1924 /* flags */ 0, 1925 }, 1926 #endif /* chips */ 1927 1928 #if defined(BCM_56870_A0) 1929 { /* SOC_FORMAT_INT_CCP_TO_ENQ_INFO_BUS_BCM56870_A0fmt */ 1930 /* format CCP_TO_ENQ_INFO_BUSfmt */ 1931 /* nFields */ 1, 1932 /* *fields */ soc_CCP_TO_ENQ_INFO_BUS_BCM56560_A0fmt_fields, 1933 /* bits */ 7, 1934 /* flags */ 0, 1935 }, 1936 #endif /* chips */ 1937 1938 #if defined(BCM_56960_A0) 1939 { /* SOC_FORMAT_INT_CCP_TO_ENQ_INFO_BUS_BCM56960_A0fmt */ 1940 /* format CCP_TO_ENQ_INFO_BUSfmt */ 1941 /* nFields */ 1, 1942 /* *fields */ soc_CCP_TO_ENQ_INFO_BUS_BCM56960_A0fmt_fields, 1943 /* bits */ 6, 1944 /* flags */ 0, 1945 }, 1946 #endif /* chips */ 1947 1948 #if defined(BCM_56965_A0) 1949 { /* SOC_FORMAT_INT_CCP_TO_ENQ_INFO_BUS_BCM56965_A0fmt */ 1950 /* format CCP_TO_ENQ_INFO_BUSfmt */ 1951 /* nFields */ 1, 1952 /* *fields */ soc_CCP_TO_ENQ_INFO_BUS_BCM56960_A0fmt_fields, 1953 /* bits */ 6, 1954 /* flags */ 0, 1955 }, 1956 #endif /* chips */ 1957 1958 #if defined(BCM_56970_A0) 1959 { /* SOC_FORMAT_INT_CCP_TO_ENQ_INFO_BUS_BCM56970_A0fmt */ 1960 /* format CCP_TO_ENQ_INFO_BUSfmt */ 1961 /* nFields */ 1, 1962 /* *fields */ soc_CCP_TO_ENQ_INFO_BUS_BCM56960_A0fmt_fields, 1963 /* bits */ 6, 1964 /* flags */ 0, 1965 }, 1966 #endif /* chips */ 1967 1968 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) 1969 { /* SOC_FORMAT_INT_CCP_TO_RQE_INFOfmt */ 1970 /* format CCP_TO_RQE_INFOfmt */ 1971 /* nFields */ 7, 1972 /* *fields */ soc_CCP_TO_RQE_INFOfmt_fields, 1973 /* bits */ 18, 1974 /* flags */ 0, 1975 }, 1976 #endif /* chips */ 1977 1978 #if defined(BCM_56260_A0) 1979 { /* SOC_FORMAT_INT_CCP_TO_RQE_INFO_BCM56260_A0fmt */ 1980 /* format CCP_TO_RQE_INFOfmt */ 1981 /* nFields */ 9, 1982 /* *fields */ soc_CCP_TO_RQE_INFO_BCM56260_A0fmt_fields, 1983 /* bits */ 18, 1984 /* flags */ 0, 1985 }, 1986 #endif /* chips */ 1987 1988 #if defined(BCM_56260_B0) 1989 { /* SOC_FORMAT_INT_CCP_TO_RQE_INFO_BCM56260_B0fmt */ 1990 /* format CCP_TO_RQE_INFOfmt */ 1991 /* nFields */ 9, 1992 /* *fields */ soc_CCP_TO_RQE_INFO_BCM56260_A0fmt_fields, 1993 /* bits */ 18, 1994 /* flags */ 0, 1995 }, 1996 #endif /* chips */ 1997 1998 #if defined(BCM_56270_A0) 1999 { /* SOC_FORMAT_INT_CCP_TO_RQE_INFO_BCM56270_A0fmt */ 2000 /* format CCP_TO_RQE_INFOfmt */ 2001 /* nFields */ 9, 2002 /* *fields */ soc_CCP_TO_RQE_INFO_BCM56270_A0fmt_fields, 2003 /* bits */ 17, 2004 /* flags */ 0, 2005 }, 2006 #endif /* chips */ 2007 2008 #if defined(BCM_56450_A0) 2009 { /* SOC_FORMAT_INT_CCP_TO_RQE_INFO_BCM56450_A0fmt */ 2010 /* format CCP_TO_RQE_INFOfmt */ 2011 /* nFields */ 9, 2012 /* *fields */ soc_CCP_TO_RQE_INFO_BCM56450_A0fmt_fields, 2013 /* bits */ 20, 2014 /* flags */ 0, 2015 }, 2016 #endif /* chips */ 2017 2018 #if defined(BCM_56450_B0) 2019 { /* SOC_FORMAT_INT_CCP_TO_RQE_INFO_BCM56450_B0fmt */ 2020 /* format CCP_TO_RQE_INFOfmt */ 2021 /* nFields */ 9, 2022 /* *fields */ soc_CCP_TO_RQE_INFO_BCM56450_A0fmt_fields, 2023 /* bits */ 20, 2024 /* flags */ 0, 2025 }, 2026 #endif /* chips */ 2027 2028 #if defined(BCM_56450_B1) 2029 { /* SOC_FORMAT_INT_CCP_TO_RQE_INFO_BCM56450_B1fmt */ 2030 /* format CCP_TO_RQE_INFOfmt */ 2031 /* nFields */ 9, 2032 /* *fields */ soc_CCP_TO_RQE_INFO_BCM56450_A0fmt_fields, 2033 /* bits */ 20, 2034 /* flags */ 0, 2035 }, 2036 #endif /* chips */ 2037 2038 #if defined(BCM_56725_A0) || defined(BCM_56820_A0) 2039 { /* SOC_FORMAT_INT_CCP_TO_THD0_INFO_BUSfmt */ 2040 /* format CCP_TO_THD0_INFO_BUSfmt */ 2041 /* nFields */ 7, 2042 /* *fields */ soc_CCP_TO_THD0_INFO_BUSfmt_fields, 2043 /* bits */ 23, 2044 /* flags */ 0, 2045 }, 2046 #endif /* chips */ 2047 2048 #if defined(BCM_56820_A0) 2049 { /* SOC_FORMAT_INT_CCP_TO_THD1_INFO_BUSfmt */ 2050 /* format CCP_TO_THD1_INFO_BUSfmt */ 2051 /* nFields */ 7, 2052 /* *fields */ soc_CCP_TO_THD_INFO_BUSfmt_fields, 2053 /* bits */ 21, 2054 /* flags */ 0, 2055 }, 2056 #endif /* chips */ 2057 2058 #if defined(BCM_56725_A0) 2059 { /* SOC_FORMAT_INT_CCP_TO_THD1_INFO_BUS_BCM56725_A0fmt */ 2060 /* format CCP_TO_THD1_INFO_BUSfmt */ 2061 /* nFields */ 7, 2062 /* *fields */ soc_CCP_TO_THD_INFO_BUSfmt_fields, 2063 /* bits */ 21, 2064 /* flags */ 0, 2065 }, 2066 #endif /* chips */ 2067 2068 #if defined(BCM_56340_A0) || defined(BCM_56640_A0) 2069 { /* SOC_FORMAT_INT_CCP_TO_THDI_INFO_BUSfmt */ 2070 /* format CCP_TO_THDI_INFO_BUSfmt */ 2071 /* nFields */ 6, 2072 /* *fields */ soc_CCP_TO_THDI_INFO_BUSfmt_fields, 2073 /* bits */ 14, 2074 /* flags */ 0, 2075 }, 2076 #endif /* chips */ 2077 2078 #if defined(BCM_56370_A0) 2079 { /* SOC_FORMAT_INT_CCP_TO_THDI_INFO_BUS_BCM56370_A0fmt */ 2080 /* format CCP_TO_THDI_INFO_BUSfmt */ 2081 /* nFields */ 5, 2082 /* *fields */ soc_CCP_TO_THDI_INFO_BUS_BCM56870_A0fmt_fields, 2083 /* bits */ 15, 2084 /* flags */ 0, 2085 }, 2086 #endif /* chips */ 2087 2088 #if defined(BCM_56560_A0) 2089 { /* SOC_FORMAT_INT_CCP_TO_THDI_INFO_BUS_BCM56560_A0fmt */ 2090 /* format CCP_TO_THDI_INFO_BUSfmt */ 2091 /* nFields */ 5, 2092 /* *fields */ soc_CCP_TO_THDI_INFO_BUS_BCM56960_A0fmt_fields, 2093 /* bits */ 14, 2094 /* flags */ 0, 2095 }, 2096 #endif /* chips */ 2097 2098 #if defined(BCM_56560_B0) 2099 { /* SOC_FORMAT_INT_CCP_TO_THDI_INFO_BUS_BCM56560_B0fmt */ 2100 /* format CCP_TO_THDI_INFO_BUSfmt */ 2101 /* nFields */ 5, 2102 /* *fields */ soc_CCP_TO_THDI_INFO_BUS_BCM56960_A0fmt_fields, 2103 /* bits */ 14, 2104 /* flags */ 0, 2105 }, 2106 #endif /* chips */ 2107 2108 #if defined(BCM_56670_A0) 2109 { /* SOC_FORMAT_INT_CCP_TO_THDI_INFO_BUS_BCM56670_A0fmt */ 2110 /* format CCP_TO_THDI_INFO_BUSfmt */ 2111 /* nFields */ 5, 2112 /* *fields */ soc_CCP_TO_THDI_INFO_BUS_BCM56960_A0fmt_fields, 2113 /* bits */ 14, 2114 /* flags */ 0, 2115 }, 2116 #endif /* chips */ 2117 2118 #if defined(BCM_56670_B0) 2119 { /* SOC_FORMAT_INT_CCP_TO_THDI_INFO_BUS_BCM56670_B0fmt */ 2120 /* format CCP_TO_THDI_INFO_BUSfmt */ 2121 /* nFields */ 5, 2122 /* *fields */ soc_CCP_TO_THDI_INFO_BUS_BCM56960_A0fmt_fields, 2123 /* bits */ 14, 2124 /* flags */ 0, 2125 }, 2126 #endif /* chips */ 2127 2128 #if defined(BCM_56770_A0) 2129 { /* SOC_FORMAT_INT_CCP_TO_THDI_INFO_BUS_BCM56770_A0fmt */ 2130 /* format CCP_TO_THDI_INFO_BUSfmt */ 2131 /* nFields */ 5, 2132 /* *fields */ soc_CCP_TO_THDI_INFO_BUS_BCM56870_A0fmt_fields, 2133 /* bits */ 15, 2134 /* flags */ 0, 2135 }, 2136 #endif /* chips */ 2137 2138 #if defined(BCM_56850_A0) 2139 { /* SOC_FORMAT_INT_CCP_TO_THDI_INFO_BUS_BCM56850_A0fmt */ 2140 /* format CCP_TO_THDI_INFO_BUSfmt */ 2141 /* nFields */ 5, 2142 /* *fields */ soc_CCP_TO_THDI_INFO_BUS_BCM56850_A0fmt_fields, 2143 /* bits */ 14, 2144 /* flags */ 0, 2145 }, 2146 #endif /* chips */ 2147 2148 #if defined(BCM_56860_A0) 2149 { /* SOC_FORMAT_INT_CCP_TO_THDI_INFO_BUS_BCM56860_A0fmt */ 2150 /* format CCP_TO_THDI_INFO_BUSfmt */ 2151 /* nFields */ 5, 2152 /* *fields */ soc_CCP_TO_THDI_INFO_BUS_BCM56850_A0fmt_fields, 2153 /* bits */ 14, 2154 /* flags */ 0, 2155 }, 2156 #endif /* chips */ 2157 2158 #if defined(BCM_56870_A0) 2159 { /* SOC_FORMAT_INT_CCP_TO_THDI_INFO_BUS_BCM56870_A0fmt */ 2160 /* format CCP_TO_THDI_INFO_BUSfmt */ 2161 /* nFields */ 5, 2162 /* *fields */ soc_CCP_TO_THDI_INFO_BUS_BCM56870_A0fmt_fields, 2163 /* bits */ 15, 2164 /* flags */ 0, 2165 }, 2166 #endif /* chips */ 2167 2168 #if defined(BCM_56960_A0) 2169 { /* SOC_FORMAT_INT_CCP_TO_THDI_INFO_BUS_BCM56960_A0fmt */ 2170 /* format CCP_TO_THDI_INFO_BUSfmt */ 2171 /* nFields */ 5, 2172 /* *fields */ soc_CCP_TO_THDI_INFO_BUS_BCM56960_A0fmt_fields, 2173 /* bits */ 14, 2174 /* flags */ 0, 2175 }, 2176 #endif /* chips */ 2177 2178 #if defined(BCM_56965_A0) 2179 { /* SOC_FORMAT_INT_CCP_TO_THDI_INFO_BUS_BCM56965_A0fmt */ 2180 /* format CCP_TO_THDI_INFO_BUSfmt */ 2181 /* nFields */ 5, 2182 /* *fields */ soc_CCP_TO_THDI_INFO_BUS_BCM56960_A0fmt_fields, 2183 /* bits */ 14, 2184 /* flags */ 0, 2185 }, 2186 #endif /* chips */ 2187 2188 #if defined(BCM_56970_A0) 2189 { /* SOC_FORMAT_INT_CCP_TO_THDI_INFO_BUS_BCM56970_A0fmt */ 2190 /* format CCP_TO_THDI_INFO_BUSfmt */ 2191 /* nFields */ 5, 2192 /* *fields */ soc_CCP_TO_THDI_INFO_BUS_BCM56960_A0fmt_fields, 2193 /* bits */ 14, 2194 /* flags */ 0, 2195 }, 2196 #endif /* chips */ 2197 2198 #if defined(BCM_56850_A0) || defined(BCM_56860_A0) 2199 { /* SOC_FORMAT_INT_CCP_TO_THDMfmt */ 2200 /* format CCP_TO_THDMfmt */ 2201 /* nFields */ 6, 2202 /* *fields */ soc_CCP_TO_THDMfmt_fields, 2203 /* bits */ 25, 2204 /* flags */ 0, 2205 }, 2206 #endif /* chips */ 2207 2208 #if defined(BCM_56370_A0) 2209 { /* SOC_FORMAT_INT_CCP_TO_THDM_BCM56370_A0fmt */ 2210 /* format CCP_TO_THDMfmt */ 2211 /* nFields */ 7, 2212 /* *fields */ soc_CCP_TO_THDM_BCM56370_A0fmt_fields, 2213 /* bits */ 27, 2214 /* flags */ 0, 2215 }, 2216 #endif /* chips */ 2217 2218 #if defined(BCM_56560_A0) 2219 { /* SOC_FORMAT_INT_CCP_TO_THDM_BCM56560_A0fmt */ 2220 /* format CCP_TO_THDMfmt */ 2221 /* nFields */ 6, 2222 /* *fields */ soc_CCP_TO_THDM_BCM56560_A0fmt_fields, 2223 /* bits */ 29, 2224 /* flags */ 0, 2225 }, 2226 #endif /* chips */ 2227 2228 #if defined(BCM_56560_B0) 2229 { /* SOC_FORMAT_INT_CCP_TO_THDM_BCM56560_B0fmt */ 2230 /* format CCP_TO_THDMfmt */ 2231 /* nFields */ 6, 2232 /* *fields */ soc_CCP_TO_THDM_BCM56560_A0fmt_fields, 2233 /* bits */ 29, 2234 /* flags */ 0, 2235 }, 2236 #endif /* chips */ 2237 2238 #if defined(BCM_56670_A0) 2239 { /* SOC_FORMAT_INT_CCP_TO_THDM_BCM56670_A0fmt */ 2240 /* format CCP_TO_THDMfmt */ 2241 /* nFields */ 6, 2242 /* *fields */ soc_CCP_TO_THDM_BCM56670_A0fmt_fields, 2243 /* bits */ 25, 2244 /* flags */ 0, 2245 }, 2246 #endif /* chips */ 2247 2248 #if defined(BCM_56670_B0) 2249 { /* SOC_FORMAT_INT_CCP_TO_THDM_BCM56670_B0fmt */ 2250 /* format CCP_TO_THDMfmt */ 2251 /* nFields */ 6, 2252 /* *fields */ soc_CCP_TO_THDM_BCM56670_A0fmt_fields, 2253 /* bits */ 25, 2254 /* flags */ 0, 2255 }, 2256 #endif /* chips */ 2257 2258 #if defined(BCM_56770_A0) 2259 { /* SOC_FORMAT_INT_CCP_TO_THDM_BCM56770_A0fmt */ 2260 /* format CCP_TO_THDMfmt */ 2261 /* nFields */ 7, 2262 /* *fields */ soc_CCP_TO_THDM_BCM56870_A0fmt_fields, 2263 /* bits */ 27, 2264 /* flags */ 0, 2265 }, 2266 #endif /* chips */ 2267 2268 #if defined(BCM_56870_A0) 2269 { /* SOC_FORMAT_INT_CCP_TO_THDM_BCM56870_A0fmt */ 2270 /* format CCP_TO_THDMfmt */ 2271 /* nFields */ 7, 2272 /* *fields */ soc_CCP_TO_THDM_BCM56870_A0fmt_fields, 2273 /* bits */ 27, 2274 /* flags */ 0, 2275 }, 2276 #endif /* chips */ 2277 2278 #if defined(BCM_56960_A0) 2279 { /* SOC_FORMAT_INT_CCP_TO_THDM_BCM56960_A0fmt */ 2280 /* format CCP_TO_THDMfmt */ 2281 /* nFields */ 7, 2282 /* *fields */ soc_CCP_TO_THDM_BCM56960_A0fmt_fields, 2283 /* bits */ 25, 2284 /* flags */ 0, 2285 }, 2286 #endif /* chips */ 2287 2288 #if defined(BCM_56965_A0) 2289 { /* SOC_FORMAT_INT_CCP_TO_THDM_BCM56965_A0fmt */ 2290 /* format CCP_TO_THDMfmt */ 2291 /* nFields */ 7, 2292 /* *fields */ soc_CCP_TO_THDM_BCM56960_A0fmt_fields, 2293 /* bits */ 25, 2294 /* flags */ 0, 2295 }, 2296 #endif /* chips */ 2297 2298 #if defined(BCM_56970_A0) 2299 { /* SOC_FORMAT_INT_CCP_TO_THDM_BCM56970_A0fmt */ 2300 /* format CCP_TO_THDMfmt */ 2301 /* nFields */ 7, 2302 /* *fields */ soc_CCP_TO_THDM_BCM56960_A0fmt_fields, 2303 /* bits */ 25, 2304 /* flags */ 0, 2305 }, 2306 #endif /* chips */ 2307 2308 #if defined(BCM_56340_A0) || defined(BCM_56640_A0) 2309 { /* SOC_FORMAT_INT_CCP_TO_THDO_INFO_BUSfmt */ 2310 /* format CCP_TO_THDO_INFO_BUSfmt */ 2311 /* nFields */ 7, 2312 /* *fields */ soc_CCP_TO_THDO_INFO_BUSfmt_fields, 2313 /* bits */ 35, 2314 /* flags */ 0, 2315 }, 2316 #endif /* chips */ 2317 2318 #if defined(BCM_56370_A0) 2319 { /* SOC_FORMAT_INT_CCP_TO_THDO_INFO_BUS_BCM56370_A0fmt */ 2320 /* format CCP_TO_THDO_INFO_BUSfmt */ 2321 /* nFields */ 7, 2322 /* *fields */ soc_CCP_TO_THDO_INFO_BUS_BCM56370_A0fmt_fields, 2323 /* bits */ 32, 2324 /* flags */ 0, 2325 }, 2326 #endif /* chips */ 2327 2328 #if defined(BCM_56560_A0) 2329 { /* SOC_FORMAT_INT_CCP_TO_THDO_INFO_BUS_BCM56560_A0fmt */ 2330 /* format CCP_TO_THDO_INFO_BUSfmt */ 2331 /* nFields */ 8, 2332 /* *fields */ soc_CCP_TO_THDO_INFO_BUS_BCM56560_A0fmt_fields, 2333 /* bits */ 42, 2334 /* flags */ 0, 2335 }, 2336 #endif /* chips */ 2337 2338 #if defined(BCM_56560_B0) 2339 { /* SOC_FORMAT_INT_CCP_TO_THDO_INFO_BUS_BCM56560_B0fmt */ 2340 /* format CCP_TO_THDO_INFO_BUSfmt */ 2341 /* nFields */ 8, 2342 /* *fields */ soc_CCP_TO_THDO_INFO_BUS_BCM56560_A0fmt_fields, 2343 /* bits */ 42, 2344 /* flags */ 0, 2345 }, 2346 #endif /* chips */ 2347 2348 #if defined(BCM_56670_A0) 2349 { /* SOC_FORMAT_INT_CCP_TO_THDO_INFO_BUS_BCM56670_A0fmt */ 2350 /* format CCP_TO_THDO_INFO_BUSfmt */ 2351 /* nFields */ 8, 2352 /* *fields */ soc_CCP_TO_THDO_INFO_BUS_BCM56670_A0fmt_fields, 2353 /* bits */ 38, 2354 /* flags */ 0, 2355 }, 2356 #endif /* chips */ 2357 2358 #if defined(BCM_56670_B0) 2359 { /* SOC_FORMAT_INT_CCP_TO_THDO_INFO_BUS_BCM56670_B0fmt */ 2360 /* format CCP_TO_THDO_INFO_BUSfmt */ 2361 /* nFields */ 8, 2362 /* *fields */ soc_CCP_TO_THDO_INFO_BUS_BCM56670_A0fmt_fields, 2363 /* bits */ 38, 2364 /* flags */ 0, 2365 }, 2366 #endif /* chips */ 2367 2368 #if defined(BCM_56770_A0) 2369 { /* SOC_FORMAT_INT_CCP_TO_THDO_INFO_BUS_BCM56770_A0fmt */ 2370 /* format CCP_TO_THDO_INFO_BUSfmt */ 2371 /* nFields */ 7, 2372 /* *fields */ soc_CCP_TO_THDO_INFO_BUS_BCM56870_A0fmt_fields, 2373 /* bits */ 31, 2374 /* flags */ 0, 2375 }, 2376 #endif /* chips */ 2377 2378 #if defined(BCM_56850_A0) 2379 { /* SOC_FORMAT_INT_CCP_TO_THDO_INFO_BUS_BCM56850_A0fmt */ 2380 /* format CCP_TO_THDO_INFO_BUSfmt */ 2381 /* nFields */ 8, 2382 /* *fields */ soc_CCP_TO_THDO_INFO_BUS_BCM56850_A0fmt_fields, 2383 /* bits */ 39, 2384 /* flags */ 0, 2385 }, 2386 #endif /* chips */ 2387 2388 #if defined(BCM_56860_A0) 2389 { /* SOC_FORMAT_INT_CCP_TO_THDO_INFO_BUS_BCM56860_A0fmt */ 2390 /* format CCP_TO_THDO_INFO_BUSfmt */ 2391 /* nFields */ 8, 2392 /* *fields */ soc_CCP_TO_THDO_INFO_BUS_BCM56850_A0fmt_fields, 2393 /* bits */ 39, 2394 /* flags */ 0, 2395 }, 2396 #endif /* chips */ 2397 2398 #if defined(BCM_56870_A0) 2399 { /* SOC_FORMAT_INT_CCP_TO_THDO_INFO_BUS_BCM56870_A0fmt */ 2400 /* format CCP_TO_THDO_INFO_BUSfmt */ 2401 /* nFields */ 7, 2402 /* *fields */ soc_CCP_TO_THDO_INFO_BUS_BCM56870_A0fmt_fields, 2403 /* bits */ 31, 2404 /* flags */ 0, 2405 }, 2406 #endif /* chips */ 2407 2408 #if defined(BCM_56960_A0) 2409 { /* SOC_FORMAT_INT_CCP_TO_THDO_INFO_BUS_BCM56960_A0fmt */ 2410 /* format CCP_TO_THDO_INFO_BUSfmt */ 2411 /* nFields */ 7, 2412 /* *fields */ soc_CCP_TO_THDO_INFO_BUS_BCM56960_A0fmt_fields, 2413 /* bits */ 29, 2414 /* flags */ 0, 2415 }, 2416 #endif /* chips */ 2417 2418 #if defined(BCM_56965_A0) 2419 { /* SOC_FORMAT_INT_CCP_TO_THDO_INFO_BUS_BCM56965_A0fmt */ 2420 /* format CCP_TO_THDO_INFO_BUSfmt */ 2421 /* nFields */ 7, 2422 /* *fields */ soc_CCP_TO_THDO_INFO_BUS_BCM56960_A0fmt_fields, 2423 /* bits */ 29, 2424 /* flags */ 0, 2425 }, 2426 #endif /* chips */ 2427 2428 #if defined(BCM_56970_A0) 2429 { /* SOC_FORMAT_INT_CCP_TO_THDO_INFO_BUS_BCM56970_A0fmt */ 2430 /* format CCP_TO_THDO_INFO_BUSfmt */ 2431 /* nFields */ 7, 2432 /* *fields */ soc_CCP_TO_THDO_INFO_BUS_BCM56960_A0fmt_fields, 2433 /* bits */ 29, 2434 /* flags */ 0, 2435 }, 2436 #endif /* chips */ 2437 2438 #if defined(BCM_56800_A0) 2439 { /* SOC_FORMAT_INT_CCP_TO_THD_INFO_BUSfmt */ 2440 /* format CCP_TO_THD_INFO_BUSfmt */ 2441 /* nFields */ 7, 2442 /* *fields */ soc_CCP_TO_THD_INFO_BUSfmt_fields, 2443 /* bits */ 21, 2444 /* flags */ 0, 2445 }, 2446 #endif /* chips */ 2447 2448 #if defined(BCM_56260_A0) 2449 { /* SOC_FORMAT_INT_CCP_TO_THD_INFO_BUS_BCM56260_A0fmt */ 2450 /* format CCP_TO_THD_INFO_BUSfmt */ 2451 /* nFields */ 11, 2452 /* *fields */ soc_CCP_TO_THD_INFO_BUS_BCM56260_A0fmt_fields, 2453 /* bits */ 34, 2454 /* flags */ 0, 2455 }, 2456 #endif /* chips */ 2457 2458 #if defined(BCM_56260_B0) 2459 { /* SOC_FORMAT_INT_CCP_TO_THD_INFO_BUS_BCM56260_B0fmt */ 2460 /* format CCP_TO_THD_INFO_BUSfmt */ 2461 /* nFields */ 11, 2462 /* *fields */ soc_CCP_TO_THD_INFO_BUS_BCM56260_A0fmt_fields, 2463 /* bits */ 34, 2464 /* flags */ 0, 2465 }, 2466 #endif /* chips */ 2467 2468 #if defined(BCM_56270_A0) 2469 { /* SOC_FORMAT_INT_CCP_TO_THD_INFO_BUS_BCM56270_A0fmt */ 2470 /* format CCP_TO_THD_INFO_BUSfmt */ 2471 /* nFields */ 11, 2472 /* *fields */ soc_CCP_TO_THD_INFO_BUS_BCM56260_A0fmt_fields, 2473 /* bits */ 34, 2474 /* flags */ 0, 2475 }, 2476 #endif /* chips */ 2477 2478 #if defined(BCM_56334_A0) 2479 { /* SOC_FORMAT_INT_CCP_TO_THD_INFO_BUS_BCM56334_A0fmt */ 2480 /* format CCP_TO_THD_INFO_BUSfmt */ 2481 /* nFields */ 12, 2482 /* *fields */ soc_CCP_TO_THD_INFO_BUS_BCM56624_A0fmt_fields, 2483 /* bits */ 44, 2484 /* flags */ 0, 2485 }, 2486 #endif /* chips */ 2487 2488 #if defined(BCM_56334_B0) 2489 { /* SOC_FORMAT_INT_CCP_TO_THD_INFO_BUS_BCM56334_B0fmt */ 2490 /* format CCP_TO_THD_INFO_BUSfmt */ 2491 /* nFields */ 12, 2492 /* *fields */ soc_CCP_TO_THD_INFO_BUS_BCM56624_A0fmt_fields, 2493 /* bits */ 44, 2494 /* flags */ 0, 2495 }, 2496 #endif /* chips */ 2497 2498 #if defined(BCM_56440_A0) 2499 { /* SOC_FORMAT_INT_CCP_TO_THD_INFO_BUS_BCM56440_A0fmt */ 2500 /* format CCP_TO_THD_INFO_BUSfmt */ 2501 /* nFields */ 11, 2502 /* *fields */ soc_CCP_TO_THD_INFO_BUS_BCM56840_A0fmt_fields, 2503 /* bits */ 38, 2504 /* flags */ 0, 2505 }, 2506 #endif /* chips */ 2507 2508 #if defined(BCM_56440_B0) 2509 { /* SOC_FORMAT_INT_CCP_TO_THD_INFO_BUS_BCM56440_B0fmt */ 2510 /* format CCP_TO_THD_INFO_BUSfmt */ 2511 /* nFields */ 11, 2512 /* *fields */ soc_CCP_TO_THD_INFO_BUS_BCM56840_A0fmt_fields, 2513 /* bits */ 38, 2514 /* flags */ 0, 2515 }, 2516 #endif /* chips */ 2517 2518 #if defined(BCM_56450_A0) 2519 { /* SOC_FORMAT_INT_CCP_TO_THD_INFO_BUS_BCM56450_A0fmt */ 2520 /* format CCP_TO_THD_INFO_BUSfmt */ 2521 /* nFields */ 11, 2522 /* *fields */ soc_CCP_TO_THD_INFO_BUS_BCM56450_A0fmt_fields, 2523 /* bits */ 38, 2524 /* flags */ 0, 2525 }, 2526 #endif /* chips */ 2527 2528 #if defined(BCM_56450_B0) 2529 { /* SOC_FORMAT_INT_CCP_TO_THD_INFO_BUS_BCM56450_B0fmt */ 2530 /* format CCP_TO_THD_INFO_BUSfmt */ 2531 /* nFields */ 11, 2532 /* *fields */ soc_CCP_TO_THD_INFO_BUS_BCM56450_A0fmt_fields, 2533 /* bits */ 38, 2534 /* flags */ 0, 2535 }, 2536 #endif /* chips */ 2537 2538 #if defined(BCM_56450_B1) 2539 { /* SOC_FORMAT_INT_CCP_TO_THD_INFO_BUS_BCM56450_B1fmt */ 2540 /* format CCP_TO_THD_INFO_BUSfmt */ 2541 /* nFields */ 11, 2542 /* *fields */ soc_CCP_TO_THD_INFO_BUS_BCM56450_A0fmt_fields, 2543 /* bits */ 38, 2544 /* flags */ 0, 2545 }, 2546 #endif /* chips */ 2547 2548 #if defined(BCM_56524_A0) 2549 { /* SOC_FORMAT_INT_CCP_TO_THD_INFO_BUS_BCM56524_A0fmt */ 2550 /* format CCP_TO_THD_INFO_BUSfmt */ 2551 /* nFields */ 12, 2552 /* *fields */ soc_CCP_TO_THD_INFO_BUS_BCM56624_A0fmt_fields, 2553 /* bits */ 44, 2554 /* flags */ 0, 2555 }, 2556 #endif /* chips */ 2557 2558 #if defined(BCM_56524_B0) 2559 { /* SOC_FORMAT_INT_CCP_TO_THD_INFO_BUS_BCM56524_B0fmt */ 2560 /* format CCP_TO_THD_INFO_BUSfmt */ 2561 /* nFields */ 12, 2562 /* *fields */ soc_CCP_TO_THD_INFO_BUS_BCM56624_A0fmt_fields, 2563 /* bits */ 44, 2564 /* flags */ 0, 2565 }, 2566 #endif /* chips */ 2567 2568 #if defined(BCM_56624_A0) 2569 { /* SOC_FORMAT_INT_CCP_TO_THD_INFO_BUS_BCM56624_A0fmt */ 2570 /* format CCP_TO_THD_INFO_BUSfmt */ 2571 /* nFields */ 12, 2572 /* *fields */ soc_CCP_TO_THD_INFO_BUS_BCM56624_A0fmt_fields, 2573 /* bits */ 44, 2574 /* flags */ 0, 2575 }, 2576 #endif /* chips */ 2577 2578 #if defined(BCM_56624_B0) 2579 { /* SOC_FORMAT_INT_CCP_TO_THD_INFO_BUS_BCM56624_B0fmt */ 2580 /* format CCP_TO_THD_INFO_BUSfmt */ 2581 /* nFields */ 12, 2582 /* *fields */ soc_CCP_TO_THD_INFO_BUS_BCM56624_A0fmt_fields, 2583 /* bits */ 44, 2584 /* flags */ 0, 2585 }, 2586 #endif /* chips */ 2587 2588 #if defined(BCM_56634_A0) 2589 { /* SOC_FORMAT_INT_CCP_TO_THD_INFO_BUS_BCM56634_A0fmt */ 2590 /* format CCP_TO_THD_INFO_BUSfmt */ 2591 /* nFields */ 12, 2592 /* *fields */ soc_CCP_TO_THD_INFO_BUS_BCM56624_A0fmt_fields, 2593 /* bits */ 44, 2594 /* flags */ 0, 2595 }, 2596 #endif /* chips */ 2597 2598 #if defined(BCM_56634_B0) 2599 { /* SOC_FORMAT_INT_CCP_TO_THD_INFO_BUS_BCM56634_B0fmt */ 2600 /* format CCP_TO_THD_INFO_BUSfmt */ 2601 /* nFields */ 12, 2602 /* *fields */ soc_CCP_TO_THD_INFO_BUS_BCM56624_A0fmt_fields, 2603 /* bits */ 44, 2604 /* flags */ 0, 2605 }, 2606 #endif /* chips */ 2607 2608 #if defined(BCM_56680_A0) 2609 { /* SOC_FORMAT_INT_CCP_TO_THD_INFO_BUS_BCM56680_A0fmt */ 2610 /* format CCP_TO_THD_INFO_BUSfmt */ 2611 /* nFields */ 12, 2612 /* *fields */ soc_CCP_TO_THD_INFO_BUS_BCM56624_A0fmt_fields, 2613 /* bits */ 44, 2614 /* flags */ 0, 2615 }, 2616 #endif /* chips */ 2617 2618 #if defined(BCM_56680_B0) 2619 { /* SOC_FORMAT_INT_CCP_TO_THD_INFO_BUS_BCM56680_B0fmt */ 2620 /* format CCP_TO_THD_INFO_BUSfmt */ 2621 /* nFields */ 12, 2622 /* *fields */ soc_CCP_TO_THD_INFO_BUS_BCM56624_A0fmt_fields, 2623 /* bits */ 44, 2624 /* flags */ 0, 2625 }, 2626 #endif /* chips */ 2627 2628 #if defined(BCM_56685_A0) 2629 { /* SOC_FORMAT_INT_CCP_TO_THD_INFO_BUS_BCM56685_A0fmt */ 2630 /* format CCP_TO_THD_INFO_BUSfmt */ 2631 /* nFields */ 12, 2632 /* *fields */ soc_CCP_TO_THD_INFO_BUS_BCM56624_A0fmt_fields, 2633 /* bits */ 44, 2634 /* flags */ 0, 2635 }, 2636 #endif /* chips */ 2637 2638 #if defined(BCM_56685_B0) 2639 { /* SOC_FORMAT_INT_CCP_TO_THD_INFO_BUS_BCM56685_B0fmt */ 2640 /* format CCP_TO_THD_INFO_BUSfmt */ 2641 /* nFields */ 12, 2642 /* *fields */ soc_CCP_TO_THD_INFO_BUS_BCM56624_A0fmt_fields, 2643 /* bits */ 44, 2644 /* flags */ 0, 2645 }, 2646 #endif /* chips */ 2647 2648 #if defined(BCM_56840_A0) 2649 { /* SOC_FORMAT_INT_CCP_TO_THD_INFO_BUS_BCM56840_A0fmt */ 2650 /* format CCP_TO_THD_INFO_BUSfmt */ 2651 /* nFields */ 11, 2652 /* *fields */ soc_CCP_TO_THD_INFO_BUS_BCM56840_A0fmt_fields, 2653 /* bits */ 38, 2654 /* flags */ 0, 2655 }, 2656 #endif /* chips */ 2657 2658 #if defined(BCM_56840_B0) 2659 { /* SOC_FORMAT_INT_CCP_TO_THD_INFO_BUS_BCM56840_B0fmt */ 2660 /* format CCP_TO_THD_INFO_BUSfmt */ 2661 /* nFields */ 11, 2662 /* *fields */ soc_CCP_TO_THD_INFO_BUS_BCM56840_A0fmt_fields, 2663 /* bits */ 38, 2664 /* flags */ 0, 2665 }, 2666 #endif /* chips */ 2667 2668 #if defined(BCM_56850_A0) || defined(BCM_56860_A0) 2669 { /* SOC_FORMAT_INT_CCP_UPDATE_META_DATAfmt */ 2670 /* format CCP_UPDATE_META_DATAfmt */ 2671 /* nFields */ 10, 2672 /* *fields */ soc_CCP_UPDATE_META_DATAfmt_fields, 2673 /* bits */ 16, 2674 /* flags */ 0, 2675 }, 2676 #endif /* chips */ 2677 2678 #if defined(BCM_56370_A0) 2679 { /* SOC_FORMAT_INT_CCP_UPDATE_META_DATA_BCM56370_A0fmt */ 2680 /* format CCP_UPDATE_META_DATAfmt */ 2681 /* nFields */ 10, 2682 /* *fields */ soc_CCP_UPDATE_META_DATA_BCM56870_A0fmt_fields, 2683 /* bits */ 17, 2684 /* flags */ 0, 2685 }, 2686 #endif /* chips */ 2687 2688 #if defined(BCM_56560_A0) 2689 { /* SOC_FORMAT_INT_CCP_UPDATE_META_DATA_BCM56560_A0fmt */ 2690 /* format CCP_UPDATE_META_DATAfmt */ 2691 /* nFields */ 10, 2692 /* *fields */ soc_CCP_UPDATE_META_DATA_BCM56960_A0fmt_fields, 2693 /* bits */ 16, 2694 /* flags */ 0, 2695 }, 2696 #endif /* chips */ 2697 2698 #if defined(BCM_56560_B0) 2699 { /* SOC_FORMAT_INT_CCP_UPDATE_META_DATA_BCM56560_B0fmt */ 2700 /* format CCP_UPDATE_META_DATAfmt */ 2701 /* nFields */ 10, 2702 /* *fields */ soc_CCP_UPDATE_META_DATA_BCM56960_A0fmt_fields, 2703 /* bits */ 16, 2704 /* flags */ 0, 2705 }, 2706 #endif /* chips */ 2707 2708 #if defined(BCM_56670_A0) 2709 { /* SOC_FORMAT_INT_CCP_UPDATE_META_DATA_BCM56670_A0fmt */ 2710 /* format CCP_UPDATE_META_DATAfmt */ 2711 /* nFields */ 10, 2712 /* *fields */ soc_CCP_UPDATE_META_DATA_BCM56960_A0fmt_fields, 2713 /* bits */ 16, 2714 /* flags */ 0, 2715 }, 2716 #endif /* chips */ 2717 2718 #if defined(BCM_56670_B0) 2719 { /* SOC_FORMAT_INT_CCP_UPDATE_META_DATA_BCM56670_B0fmt */ 2720 /* format CCP_UPDATE_META_DATAfmt */ 2721 /* nFields */ 10, 2722 /* *fields */ soc_CCP_UPDATE_META_DATA_BCM56960_A0fmt_fields, 2723 /* bits */ 16, 2724 /* flags */ 0, 2725 }, 2726 #endif /* chips */ 2727 2728 #if defined(BCM_56770_A0) 2729 { /* SOC_FORMAT_INT_CCP_UPDATE_META_DATA_BCM56770_A0fmt */ 2730 /* format CCP_UPDATE_META_DATAfmt */ 2731 /* nFields */ 10, 2732 /* *fields */ soc_CCP_UPDATE_META_DATA_BCM56870_A0fmt_fields, 2733 /* bits */ 17, 2734 /* flags */ 0, 2735 }, 2736 #endif /* chips */ 2737 2738 #if defined(BCM_56870_A0) 2739 { /* SOC_FORMAT_INT_CCP_UPDATE_META_DATA_BCM56870_A0fmt */ 2740 /* format CCP_UPDATE_META_DATAfmt */ 2741 /* nFields */ 10, 2742 /* *fields */ soc_CCP_UPDATE_META_DATA_BCM56870_A0fmt_fields, 2743 /* bits */ 17, 2744 /* flags */ 0, 2745 }, 2746 #endif /* chips */ 2747 2748 #if defined(BCM_56960_A0) 2749 { /* SOC_FORMAT_INT_CCP_UPDATE_META_DATA_BCM56960_A0fmt */ 2750 /* format CCP_UPDATE_META_DATAfmt */ 2751 /* nFields */ 10, 2752 /* *fields */ soc_CCP_UPDATE_META_DATA_BCM56960_A0fmt_fields, 2753 /* bits */ 16, 2754 /* flags */ 0, 2755 }, 2756 #endif /* chips */ 2757 2758 #if defined(BCM_56965_A0) 2759 { /* SOC_FORMAT_INT_CCP_UPDATE_META_DATA_BCM56965_A0fmt */ 2760 /* format CCP_UPDATE_META_DATAfmt */ 2761 /* nFields */ 10, 2762 /* *fields */ soc_CCP_UPDATE_META_DATA_BCM56960_A0fmt_fields, 2763 /* bits */ 16, 2764 /* flags */ 0, 2765 }, 2766 #endif /* chips */ 2767 2768 #if defined(BCM_56970_A0) 2769 { /* SOC_FORMAT_INT_CCP_UPDATE_META_DATA_BCM56970_A0fmt */ 2770 /* format CCP_UPDATE_META_DATAfmt */ 2771 /* nFields */ 10, 2772 /* *fields */ soc_CCP_UPDATE_META_DATA_BCM56960_A0fmt_fields, 2773 /* bits */ 16, 2774 /* flags */ 0, 2775 }, 2776 #endif /* chips */ 2777 2778 #if defined(BCM_56800_A0) 2779 { /* SOC_FORMAT_INT_CELLCHK_S_RFfmt */ 2780 /* format CELLCHK_S_RFfmt */ 2781 /* nFields */ 1, 2782 /* *fields */ soc_CELLCHK_S_RFfmt_fields, 2783 /* bits */ 84, 2784 /* flags */ 0, 2785 }, 2786 #endif /* chips */ 2787 2788 #if defined(BCM_56260_A0) 2789 { /* SOC_FORMAT_INT_CELLCHK_S_RF_BCM56260_A0fmt */ 2790 /* format CELLCHK_S_RFfmt */ 2791 /* nFields */ 1, 2792 /* *fields */ soc_CELLCHK_S_RF_BCM56960_A0fmt_fields, 2793 /* bits */ 112, 2794 /* flags */ 0, 2795 }, 2796 #endif /* chips */ 2797 2798 #if defined(BCM_56260_B0) 2799 { /* SOC_FORMAT_INT_CELLCHK_S_RF_BCM56260_B0fmt */ 2800 /* format CELLCHK_S_RFfmt */ 2801 /* nFields */ 1, 2802 /* *fields */ soc_CELLCHK_S_RF_BCM56960_A0fmt_fields, 2803 /* bits */ 112, 2804 /* flags */ 0, 2805 }, 2806 #endif /* chips */ 2807 2808 #if defined(BCM_56270_A0) 2809 { /* SOC_FORMAT_INT_CELLCHK_S_RF_BCM56270_A0fmt */ 2810 /* format CELLCHK_S_RFfmt */ 2811 /* nFields */ 1, 2812 /* *fields */ soc_CELLCHK_S_RF_BCM56960_A0fmt_fields, 2813 /* bits */ 112, 2814 /* flags */ 0, 2815 }, 2816 #endif /* chips */ 2817 2818 #if defined(BCM_56334_A0) 2819 { /* SOC_FORMAT_INT_CELLCHK_S_RF_BCM56334_A0fmt */ 2820 /* format CELLCHK_S_RFfmt */ 2821 /* nFields */ 1, 2822 /* *fields */ soc_CELLCHK_S_RF_BCM56334_A0fmt_fields, 2823 /* bits */ 36, 2824 /* flags */ 0, 2825 }, 2826 #endif /* chips */ 2827 2828 #if defined(BCM_56334_B0) 2829 { /* SOC_FORMAT_INT_CELLCHK_S_RF_BCM56334_B0fmt */ 2830 /* format CELLCHK_S_RFfmt */ 2831 /* nFields */ 1, 2832 /* *fields */ soc_CELLCHK_S_RF_BCM56334_A0fmt_fields, 2833 /* bits */ 36, 2834 /* flags */ 0, 2835 }, 2836 #endif /* chips */ 2837 2838 #if defined(BCM_56340_A0) 2839 { /* SOC_FORMAT_INT_CELLCHK_S_RF_BCM56340_A0fmt */ 2840 /* format CELLCHK_S_RFfmt */ 2841 /* nFields */ 1, 2842 /* *fields */ soc_CELLCHK_S_RF_BCM56640_A0fmt_fields, 2843 /* bits */ 112, 2844 /* flags */ 0, 2845 }, 2846 #endif /* chips */ 2847 2848 #if defined(BCM_56440_A0) 2849 { /* SOC_FORMAT_INT_CELLCHK_S_RF_BCM56440_A0fmt */ 2850 /* format CELLCHK_S_RFfmt */ 2851 /* nFields */ 1, 2852 /* *fields */ soc_CELLCHK_S_RF_BCM56624_A0fmt_fields, 2853 /* bits */ 112, 2854 /* flags */ 0, 2855 }, 2856 #endif /* chips */ 2857 2858 #if defined(BCM_56440_B0) 2859 { /* SOC_FORMAT_INT_CELLCHK_S_RF_BCM56440_B0fmt */ 2860 /* format CELLCHK_S_RFfmt */ 2861 /* nFields */ 1, 2862 /* *fields */ soc_CELLCHK_S_RF_BCM56624_A0fmt_fields, 2863 /* bits */ 112, 2864 /* flags */ 0, 2865 }, 2866 #endif /* chips */ 2867 2868 #if defined(BCM_56450_A0) 2869 { /* SOC_FORMAT_INT_CELLCHK_S_RF_BCM56450_A0fmt */ 2870 /* format CELLCHK_S_RFfmt */ 2871 /* nFields */ 1, 2872 /* *fields */ soc_CELLCHK_S_RF_BCM56640_A0fmt_fields, 2873 /* bits */ 112, 2874 /* flags */ 0, 2875 }, 2876 #endif /* chips */ 2877 2878 #if defined(BCM_56450_B0) 2879 { /* SOC_FORMAT_INT_CELLCHK_S_RF_BCM56450_B0fmt */ 2880 /* format CELLCHK_S_RFfmt */ 2881 /* nFields */ 1, 2882 /* *fields */ soc_CELLCHK_S_RF_BCM56640_A0fmt_fields, 2883 /* bits */ 112, 2884 /* flags */ 0, 2885 }, 2886 #endif /* chips */ 2887 2888 #if defined(BCM_56450_B1) 2889 { /* SOC_FORMAT_INT_CELLCHK_S_RF_BCM56450_B1fmt */ 2890 /* format CELLCHK_S_RFfmt */ 2891 /* nFields */ 1, 2892 /* *fields */ soc_CELLCHK_S_RF_BCM56640_A0fmt_fields, 2893 /* bits */ 112, 2894 /* flags */ 0, 2895 }, 2896 #endif /* chips */ 2897 2898 #if defined(BCM_56524_A0) 2899 { /* SOC_FORMAT_INT_CELLCHK_S_RF_BCM56524_A0fmt */ 2900 /* format CELLCHK_S_RFfmt */ 2901 /* nFields */ 1, 2902 /* *fields */ soc_CELLCHK_S_RF_BCM56624_A0fmt_fields, 2903 /* bits */ 112, 2904 /* flags */ 0, 2905 }, 2906 #endif /* chips */ 2907 2908 #if defined(BCM_56524_B0) 2909 { /* SOC_FORMAT_INT_CELLCHK_S_RF_BCM56524_B0fmt */ 2910 /* format CELLCHK_S_RFfmt */ 2911 /* nFields */ 1, 2912 /* *fields */ soc_CELLCHK_S_RF_BCM56624_A0fmt_fields, 2913 /* bits */ 112, 2914 /* flags */ 0, 2915 }, 2916 #endif /* chips */ 2917 2918 #if defined(BCM_56560_A0) 2919 { /* SOC_FORMAT_INT_CELLCHK_S_RF_BCM56560_A0fmt */ 2920 /* format CELLCHK_S_RFfmt */ 2921 /* nFields */ 1, 2922 /* *fields */ soc_CELLCHK_S_RF_BCM56960_A0fmt_fields, 2923 /* bits */ 112, 2924 /* flags */ 0, 2925 }, 2926 #endif /* chips */ 2927 2928 #if defined(BCM_56560_B0) 2929 { /* SOC_FORMAT_INT_CELLCHK_S_RF_BCM56560_B0fmt */ 2930 /* format CELLCHK_S_RFfmt */ 2931 /* nFields */ 1, 2932 /* *fields */ soc_CELLCHK_S_RF_BCM56960_A0fmt_fields, 2933 /* bits */ 112, 2934 /* flags */ 0, 2935 }, 2936 #endif /* chips */ 2937 2938 #if defined(BCM_56624_A0) 2939 { /* SOC_FORMAT_INT_CELLCHK_S_RF_BCM56624_A0fmt */ 2940 /* format CELLCHK_S_RFfmt */ 2941 /* nFields */ 1, 2942 /* *fields */ soc_CELLCHK_S_RF_BCM56624_A0fmt_fields, 2943 /* bits */ 112, 2944 /* flags */ 0, 2945 }, 2946 #endif /* chips */ 2947 2948 #if defined(BCM_56624_B0) 2949 { /* SOC_FORMAT_INT_CELLCHK_S_RF_BCM56624_B0fmt */ 2950 /* format CELLCHK_S_RFfmt */ 2951 /* nFields */ 1, 2952 /* *fields */ soc_CELLCHK_S_RF_BCM56624_A0fmt_fields, 2953 /* bits */ 112, 2954 /* flags */ 0, 2955 }, 2956 #endif /* chips */ 2957 2958 #if defined(BCM_56634_A0) 2959 { /* SOC_FORMAT_INT_CELLCHK_S_RF_BCM56634_A0fmt */ 2960 /* format CELLCHK_S_RFfmt */ 2961 /* nFields */ 1, 2962 /* *fields */ soc_CELLCHK_S_RF_BCM56624_A0fmt_fields, 2963 /* bits */ 112, 2964 /* flags */ 0, 2965 }, 2966 #endif /* chips */ 2967 2968 #if defined(BCM_56634_B0) 2969 { /* SOC_FORMAT_INT_CELLCHK_S_RF_BCM56634_B0fmt */ 2970 /* format CELLCHK_S_RFfmt */ 2971 /* nFields */ 1, 2972 /* *fields */ soc_CELLCHK_S_RF_BCM56624_A0fmt_fields, 2973 /* bits */ 112, 2974 /* flags */ 0, 2975 }, 2976 #endif /* chips */ 2977 2978 #if defined(BCM_56640_A0) 2979 { /* SOC_FORMAT_INT_CELLCHK_S_RF_BCM56640_A0fmt */ 2980 /* format CELLCHK_S_RFfmt */ 2981 /* nFields */ 1, 2982 /* *fields */ soc_CELLCHK_S_RF_BCM56640_A0fmt_fields, 2983 /* bits */ 112, 2984 /* flags */ 0, 2985 }, 2986 #endif /* chips */ 2987 2988 #if defined(BCM_56670_A0) 2989 { /* SOC_FORMAT_INT_CELLCHK_S_RF_BCM56670_A0fmt */ 2990 /* format CELLCHK_S_RFfmt */ 2991 /* nFields */ 1, 2992 /* *fields */ soc_CELLCHK_S_RF_BCM56960_A0fmt_fields, 2993 /* bits */ 112, 2994 /* flags */ 0, 2995 }, 2996 #endif /* chips */ 2997 2998 #if defined(BCM_56670_B0) 2999 { /* SOC_FORMAT_INT_CELLCHK_S_RF_BCM56670_B0fmt */ 3000 /* format CELLCHK_S_RFfmt */ 3001 /* nFields */ 1, 3002 /* *fields */ soc_CELLCHK_S_RF_BCM56960_A0fmt_fields, 3003 /* bits */ 112, 3004 /* flags */ 0, 3005 }, 3006 #endif /* chips */ 3007 3008 #if defined(BCM_56680_A0) 3009 { /* SOC_FORMAT_INT_CELLCHK_S_RF_BCM56680_A0fmt */ 3010 /* format CELLCHK_S_RFfmt */ 3011 /* nFields */ 1, 3012 /* *fields */ soc_CELLCHK_S_RF_BCM56624_A0fmt_fields, 3013 /* bits */ 112, 3014 /* flags */ 0, 3015 }, 3016 #endif /* chips */ 3017 3018 #if defined(BCM_56680_B0) 3019 { /* SOC_FORMAT_INT_CELLCHK_S_RF_BCM56680_B0fmt */ 3020 /* format CELLCHK_S_RFfmt */ 3021 /* nFields */ 1, 3022 /* *fields */ soc_CELLCHK_S_RF_BCM56624_A0fmt_fields, 3023 /* bits */ 112, 3024 /* flags */ 0, 3025 }, 3026 #endif /* chips */ 3027 3028 #if defined(BCM_56685_A0) 3029 { /* SOC_FORMAT_INT_CELLCHK_S_RF_BCM56685_A0fmt */ 3030 /* format CELLCHK_S_RFfmt */ 3031 /* nFields */ 1, 3032 /* *fields */ soc_CELLCHK_S_RF_BCM56624_A0fmt_fields, 3033 /* bits */ 112, 3034 /* flags */ 0, 3035 }, 3036 #endif /* chips */ 3037 3038 #if defined(BCM_56685_B0) 3039 { /* SOC_FORMAT_INT_CELLCHK_S_RF_BCM56685_B0fmt */ 3040 /* format CELLCHK_S_RFfmt */ 3041 /* nFields */ 1, 3042 /* *fields */ soc_CELLCHK_S_RF_BCM56624_A0fmt_fields, 3043 /* bits */ 112, 3044 /* flags */ 0, 3045 }, 3046 #endif /* chips */ 3047 3048 #if defined(BCM_56725_A0) 3049 { /* SOC_FORMAT_INT_CELLCHK_S_RF_BCM56725_A0fmt */ 3050 /* format CELLCHK_S_RFfmt */ 3051 /* nFields */ 1, 3052 /* *fields */ soc_CELLCHK_S_RF_BCM56820_A0fmt_fields, 3053 /* bits */ 56, 3054 /* flags */ 0, 3055 }, 3056 #endif /* chips */ 3057 3058 #if defined(BCM_56820_A0) 3059 { /* SOC_FORMAT_INT_CELLCHK_S_RF_BCM56820_A0fmt */ 3060 /* format CELLCHK_S_RFfmt */ 3061 /* nFields */ 1, 3062 /* *fields */ soc_CELLCHK_S_RF_BCM56820_A0fmt_fields, 3063 /* bits */ 56, 3064 /* flags */ 0, 3065 }, 3066 #endif /* chips */ 3067 3068 #if defined(BCM_56840_A0) 3069 { /* SOC_FORMAT_INT_CELLCHK_S_RF_BCM56840_A0fmt */ 3070 /* format CELLCHK_S_RFfmt */ 3071 /* nFields */ 1, 3072 /* *fields */ soc_CELLCHK_S_RF_BCM56624_A0fmt_fields, 3073 /* bits */ 112, 3074 /* flags */ 0, 3075 }, 3076 #endif /* chips */ 3077 3078 #if defined(BCM_56840_B0) 3079 { /* SOC_FORMAT_INT_CELLCHK_S_RF_BCM56840_B0fmt */ 3080 /* format CELLCHK_S_RFfmt */ 3081 /* nFields */ 1, 3082 /* *fields */ soc_CELLCHK_S_RF_BCM56624_A0fmt_fields, 3083 /* bits */ 112, 3084 /* flags */ 0, 3085 }, 3086 #endif /* chips */ 3087 3088 #if defined(BCM_56850_A0) 3089 { /* SOC_FORMAT_INT_CELLCHK_S_RF_BCM56850_A0fmt */ 3090 /* format CELLCHK_S_RFfmt */ 3091 /* nFields */ 1, 3092 /* *fields */ soc_CELLCHK_S_RF_BCM56640_A0fmt_fields, 3093 /* bits */ 112, 3094 /* flags */ 0, 3095 }, 3096 #endif /* chips */ 3097 3098 #if defined(BCM_56860_A0) 3099 { /* SOC_FORMAT_INT_CELLCHK_S_RF_BCM56860_A0fmt */ 3100 /* format CELLCHK_S_RFfmt */ 3101 /* nFields */ 1, 3102 /* *fields */ soc_CELLCHK_S_RF_BCM56640_A0fmt_fields, 3103 /* bits */ 112, 3104 /* flags */ 0, 3105 }, 3106 #endif /* chips */ 3107 3108 #if defined(BCM_56960_A0) 3109 { /* SOC_FORMAT_INT_CELLCHK_S_RF_BCM56960_A0fmt */ 3110 /* format CELLCHK_S_RFfmt */ 3111 /* nFields */ 1, 3112 /* *fields */ soc_CELLCHK_S_RF_BCM56960_A0fmt_fields, 3113 /* bits */ 112, 3114 /* flags */ 0, 3115 }, 3116 #endif /* chips */ 3117 3118 #if defined(BCM_56965_A0) 3119 { /* SOC_FORMAT_INT_CELLCHK_S_RF_BCM56965_A0fmt */ 3120 /* format CELLCHK_S_RFfmt */ 3121 /* nFields */ 1, 3122 /* *fields */ soc_CELLCHK_S_RF_BCM56960_A0fmt_fields, 3123 /* bits */ 112, 3124 /* flags */ 0, 3125 }, 3126 #endif /* chips */ 3127 3128 #if defined(BCM_56970_A0) 3129 { /* SOC_FORMAT_INT_CELLCHK_S_RF_BCM56970_A0fmt */ 3130 /* format CELLCHK_S_RFfmt */ 3131 /* nFields */ 1, 3132 /* *fields */ soc_CELLCHK_S_RF_BCM56960_A0fmt_fields, 3133 /* bits */ 112, 3134 /* flags */ 0, 3135 }, 3136 #endif /* chips */ 3137 3138 #if defined(BCM_88732_A0) 3139 { /* SOC_FORMAT_INT_CELLCHK_S_RF_BCM88732_A0fmt */ 3140 /* format CELLCHK_S_RFfmt */ 3141 /* nFields */ 1, 3142 /* *fields */ soc_CELLCHK_S_RF_BCM88732_A0fmt_fields, 3143 /* bits */ 128, 3144 /* flags */ 0, 3145 }, 3146 #endif /* chips */ 3147 3148 #if defined(BCM_56800_A0) 3149 { /* SOC_FORMAT_INT_CELLDATA_S_RFfmt */ 3150 /* format CELLDATA_S_RFfmt */ 3151 /* nFields */ 1, 3152 /* *fields */ soc_CELLDATA_S_RFfmt_fields, 3153 /* bits */ 84, 3154 /* flags */ 0, 3155 }, 3156 #endif /* chips */ 3157 3158 #if defined(BCM_56142_A0) 3159 { /* SOC_FORMAT_INT_CELLDATA_S_RF_BCM56142_A0fmt */ 3160 /* format CELLDATA_S_RFfmt */ 3161 /* nFields */ 1, 3162 /* *fields */ soc_CELLDATA_S_RF_BCM56142_A0fmt_fields, 3163 /* bits */ 54, 3164 /* flags */ 0, 3165 }, 3166 #endif /* chips */ 3167 3168 #if defined(BCM_56260_A0) 3169 { /* SOC_FORMAT_INT_CELLDATA_S_RF_BCM56260_A0fmt */ 3170 /* format CELLDATA_S_RFfmt */ 3171 /* nFields */ 1, 3172 /* *fields */ soc_CELLDATA_S_RF_BCM56960_A0fmt_fields, 3173 /* bits */ 112, 3174 /* flags */ 0, 3175 }, 3176 #endif /* chips */ 3177 3178 #if defined(BCM_56260_B0) 3179 { /* SOC_FORMAT_INT_CELLDATA_S_RF_BCM56260_B0fmt */ 3180 /* format CELLDATA_S_RFfmt */ 3181 /* nFields */ 1, 3182 /* *fields */ soc_CELLDATA_S_RF_BCM56960_A0fmt_fields, 3183 /* bits */ 112, 3184 /* flags */ 0, 3185 }, 3186 #endif /* chips */ 3187 3188 #if defined(BCM_56270_A0) 3189 { /* SOC_FORMAT_INT_CELLDATA_S_RF_BCM56270_A0fmt */ 3190 /* format CELLDATA_S_RFfmt */ 3191 /* nFields */ 1, 3192 /* *fields */ soc_CELLDATA_S_RF_BCM56960_A0fmt_fields, 3193 /* bits */ 112, 3194 /* flags */ 0, 3195 }, 3196 #endif /* chips */ 3197 3198 #if defined(BCM_56334_A0) 3199 { /* SOC_FORMAT_INT_CELLDATA_S_RF_BCM56334_A0fmt */ 3200 /* format CELLDATA_S_RFfmt */ 3201 /* nFields */ 1, 3202 /* *fields */ soc_CELLDATA_S_RF_BCM56334_A0fmt_fields, 3203 /* bits */ 72, 3204 /* flags */ 0, 3205 }, 3206 #endif /* chips */ 3207 3208 #if defined(BCM_56334_B0) 3209 { /* SOC_FORMAT_INT_CELLDATA_S_RF_BCM56334_B0fmt */ 3210 /* format CELLDATA_S_RFfmt */ 3211 /* nFields */ 1, 3212 /* *fields */ soc_CELLDATA_S_RF_BCM56334_A0fmt_fields, 3213 /* bits */ 72, 3214 /* flags */ 0, 3215 }, 3216 #endif /* chips */ 3217 3218 #if defined(BCM_56340_A0) 3219 { /* SOC_FORMAT_INT_CELLDATA_S_RF_BCM56340_A0fmt */ 3220 /* format CELLDATA_S_RFfmt */ 3221 /* nFields */ 1, 3222 /* *fields */ soc_CELLDATA_S_RF_BCM56640_A0fmt_fields, 3223 /* bits */ 112, 3224 /* flags */ 0, 3225 }, 3226 #endif /* chips */ 3227 3228 #if defined(BCM_56440_A0) 3229 { /* SOC_FORMAT_INT_CELLDATA_S_RF_BCM56440_A0fmt */ 3230 /* format CELLDATA_S_RFfmt */ 3231 /* nFields */ 1, 3232 /* *fields */ soc_CELLDATA_S_RF_BCM56624_A0fmt_fields, 3233 /* bits */ 112, 3234 /* flags */ 0, 3235 }, 3236 #endif /* chips */ 3237 3238 #if defined(BCM_56440_B0) 3239 { /* SOC_FORMAT_INT_CELLDATA_S_RF_BCM56440_B0fmt */ 3240 /* format CELLDATA_S_RFfmt */ 3241 /* nFields */ 1, 3242 /* *fields */ soc_CELLDATA_S_RF_BCM56624_A0fmt_fields, 3243 /* bits */ 112, 3244 /* flags */ 0, 3245 }, 3246 #endif /* chips */ 3247 3248 #if defined(BCM_56450_A0) 3249 { /* SOC_FORMAT_INT_CELLDATA_S_RF_BCM56450_A0fmt */ 3250 /* format CELLDATA_S_RFfmt */ 3251 /* nFields */ 1, 3252 /* *fields */ soc_CELLDATA_S_RF_BCM56640_A0fmt_fields, 3253 /* bits */ 112, 3254 /* flags */ 0, 3255 }, 3256 #endif /* chips */ 3257 3258 #if defined(BCM_56450_B0) 3259 { /* SOC_FORMAT_INT_CELLDATA_S_RF_BCM56450_B0fmt */ 3260 /* format CELLDATA_S_RFfmt */ 3261 /* nFields */ 1, 3262 /* *fields */ soc_CELLDATA_S_RF_BCM56640_A0fmt_fields, 3263 /* bits */ 112, 3264 /* flags */ 0, 3265 }, 3266 #endif /* chips */ 3267 3268 #if defined(BCM_56450_B1) 3269 { /* SOC_FORMAT_INT_CELLDATA_S_RF_BCM56450_B1fmt */ 3270 /* format CELLDATA_S_RFfmt */ 3271 /* nFields */ 1, 3272 /* *fields */ soc_CELLDATA_S_RF_BCM56640_A0fmt_fields, 3273 /* bits */ 112, 3274 /* flags */ 0, 3275 }, 3276 #endif /* chips */ 3277 3278 #if defined(BCM_56524_A0) 3279 { /* SOC_FORMAT_INT_CELLDATA_S_RF_BCM56524_A0fmt */ 3280 /* format CELLDATA_S_RFfmt */ 3281 /* nFields */ 1, 3282 /* *fields */ soc_CELLDATA_S_RF_BCM56624_A0fmt_fields, 3283 /* bits */ 112, 3284 /* flags */ 0, 3285 }, 3286 #endif /* chips */ 3287 3288 #if defined(BCM_56524_B0) 3289 { /* SOC_FORMAT_INT_CELLDATA_S_RF_BCM56524_B0fmt */ 3290 /* format CELLDATA_S_RFfmt */ 3291 /* nFields */ 1, 3292 /* *fields */ soc_CELLDATA_S_RF_BCM56624_A0fmt_fields, 3293 /* bits */ 112, 3294 /* flags */ 0, 3295 }, 3296 #endif /* chips */ 3297 3298 #if defined(BCM_56560_A0) 3299 { /* SOC_FORMAT_INT_CELLDATA_S_RF_BCM56560_A0fmt */ 3300 /* format CELLDATA_S_RFfmt */ 3301 /* nFields */ 1, 3302 /* *fields */ soc_CELLDATA_S_RF_BCM56960_A0fmt_fields, 3303 /* bits */ 112, 3304 /* flags */ 0, 3305 }, 3306 #endif /* chips */ 3307 3308 #if defined(BCM_56560_B0) 3309 { /* SOC_FORMAT_INT_CELLDATA_S_RF_BCM56560_B0fmt */ 3310 /* format CELLDATA_S_RFfmt */ 3311 /* nFields */ 1, 3312 /* *fields */ soc_CELLDATA_S_RF_BCM56960_A0fmt_fields, 3313 /* bits */ 112, 3314 /* flags */ 0, 3315 }, 3316 #endif /* chips */ 3317 3318 #if defined(BCM_56624_A0) 3319 { /* SOC_FORMAT_INT_CELLDATA_S_RF_BCM56624_A0fmt */ 3320 /* format CELLDATA_S_RFfmt */ 3321 /* nFields */ 1, 3322 /* *fields */ soc_CELLDATA_S_RF_BCM56624_A0fmt_fields, 3323 /* bits */ 112, 3324 /* flags */ 0, 3325 }, 3326 #endif /* chips */ 3327 3328 #if defined(BCM_56624_B0) 3329 { /* SOC_FORMAT_INT_CELLDATA_S_RF_BCM56624_B0fmt */ 3330 /* format CELLDATA_S_RFfmt */ 3331 /* nFields */ 1, 3332 /* *fields */ soc_CELLDATA_S_RF_BCM56624_A0fmt_fields, 3333 /* bits */ 112, 3334 /* flags */ 0, 3335 }, 3336 #endif /* chips */ 3337 3338 #if defined(BCM_56634_A0) 3339 { /* SOC_FORMAT_INT_CELLDATA_S_RF_BCM56634_A0fmt */ 3340 /* format CELLDATA_S_RFfmt */ 3341 /* nFields */ 1, 3342 /* *fields */ soc_CELLDATA_S_RF_BCM56624_A0fmt_fields, 3343 /* bits */ 112, 3344 /* flags */ 0, 3345 }, 3346 #endif /* chips */ 3347 3348 #if defined(BCM_56634_B0) 3349 { /* SOC_FORMAT_INT_CELLDATA_S_RF_BCM56634_B0fmt */ 3350 /* format CELLDATA_S_RFfmt */ 3351 /* nFields */ 1, 3352 /* *fields */ soc_CELLDATA_S_RF_BCM56624_A0fmt_fields, 3353 /* bits */ 112, 3354 /* flags */ 0, 3355 }, 3356 #endif /* chips */ 3357 3358 #if defined(BCM_56640_A0) 3359 { /* SOC_FORMAT_INT_CELLDATA_S_RF_BCM56640_A0fmt */ 3360 /* format CELLDATA_S_RFfmt */ 3361 /* nFields */ 1, 3362 /* *fields */ soc_CELLDATA_S_RF_BCM56640_A0fmt_fields, 3363 /* bits */ 112, 3364 /* flags */ 0, 3365 }, 3366 #endif /* chips */ 3367 3368 #if defined(BCM_56670_A0) 3369 { /* SOC_FORMAT_INT_CELLDATA_S_RF_BCM56670_A0fmt */ 3370 /* format CELLDATA_S_RFfmt */ 3371 /* nFields */ 1, 3372 /* *fields */ soc_CELLDATA_S_RF_BCM56960_A0fmt_fields, 3373 /* bits */ 112, 3374 /* flags */ 0, 3375 }, 3376 #endif /* chips */ 3377 3378 #if defined(BCM_56670_B0) 3379 { /* SOC_FORMAT_INT_CELLDATA_S_RF_BCM56670_B0fmt */ 3380 /* format CELLDATA_S_RFfmt */ 3381 /* nFields */ 1, 3382 /* *fields */ soc_CELLDATA_S_RF_BCM56960_A0fmt_fields, 3383 /* bits */ 112, 3384 /* flags */ 0, 3385 }, 3386 #endif /* chips */ 3387 3388 #if defined(BCM_56680_A0) 3389 { /* SOC_FORMAT_INT_CELLDATA_S_RF_BCM56680_A0fmt */ 3390 /* format CELLDATA_S_RFfmt */ 3391 /* nFields */ 1, 3392 /* *fields */ soc_CELLDATA_S_RF_BCM56624_A0fmt_fields, 3393 /* bits */ 112, 3394 /* flags */ 0, 3395 }, 3396 #endif /* chips */ 3397 3398 #if defined(BCM_56680_B0) 3399 { /* SOC_FORMAT_INT_CELLDATA_S_RF_BCM56680_B0fmt */ 3400 /* format CELLDATA_S_RFfmt */ 3401 /* nFields */ 1, 3402 /* *fields */ soc_CELLDATA_S_RF_BCM56624_A0fmt_fields, 3403 /* bits */ 112, 3404 /* flags */ 0, 3405 }, 3406 #endif /* chips */ 3407 3408 #if defined(BCM_56685_A0) 3409 { /* SOC_FORMAT_INT_CELLDATA_S_RF_BCM56685_A0fmt */ 3410 /* format CELLDATA_S_RFfmt */ 3411 /* nFields */ 1, 3412 /* *fields */ soc_CELLDATA_S_RF_BCM56624_A0fmt_fields, 3413 /* bits */ 112, 3414 /* flags */ 0, 3415 }, 3416 #endif /* chips */ 3417 3418 #if defined(BCM_56685_B0) 3419 { /* SOC_FORMAT_INT_CELLDATA_S_RF_BCM56685_B0fmt */ 3420 /* format CELLDATA_S_RFfmt */ 3421 /* nFields */ 1, 3422 /* *fields */ soc_CELLDATA_S_RF_BCM56624_A0fmt_fields, 3423 /* bits */ 112, 3424 /* flags */ 0, 3425 }, 3426 #endif /* chips */ 3427 3428 #if defined(BCM_56725_A0) 3429 { /* SOC_FORMAT_INT_CELLDATA_S_RF_BCM56725_A0fmt */ 3430 /* format CELLDATA_S_RFfmt */ 3431 /* nFields */ 1, 3432 /* *fields */ soc_CELLDATA_S_RF_BCM56624_A0fmt_fields, 3433 /* bits */ 112, 3434 /* flags */ 0, 3435 }, 3436 #endif /* chips */ 3437 3438 #if defined(BCM_56820_A0) 3439 { /* SOC_FORMAT_INT_CELLDATA_S_RF_BCM56820_A0fmt */ 3440 /* format CELLDATA_S_RFfmt */ 3441 /* nFields */ 1, 3442 /* *fields */ soc_CELLDATA_S_RF_BCM56624_A0fmt_fields, 3443 /* bits */ 112, 3444 /* flags */ 0, 3445 }, 3446 #endif /* chips */ 3447 3448 #if defined(BCM_56840_A0) 3449 { /* SOC_FORMAT_INT_CELLDATA_S_RF_BCM56840_A0fmt */ 3450 /* format CELLDATA_S_RFfmt */ 3451 /* nFields */ 1, 3452 /* *fields */ soc_CELLDATA_S_RF_BCM56624_A0fmt_fields, 3453 /* bits */ 112, 3454 /* flags */ 0, 3455 }, 3456 #endif /* chips */ 3457 3458 #if defined(BCM_56840_B0) 3459 { /* SOC_FORMAT_INT_CELLDATA_S_RF_BCM56840_B0fmt */ 3460 /* format CELLDATA_S_RFfmt */ 3461 /* nFields */ 1, 3462 /* *fields */ soc_CELLDATA_S_RF_BCM56624_A0fmt_fields, 3463 /* bits */ 112, 3464 /* flags */ 0, 3465 }, 3466 #endif /* chips */ 3467 3468 #if defined(BCM_56850_A0) 3469 { /* SOC_FORMAT_INT_CELLDATA_S_RF_BCM56850_A0fmt */ 3470 /* format CELLDATA_S_RFfmt */ 3471 /* nFields */ 1, 3472 /* *fields */ soc_CELLDATA_S_RF_BCM56640_A0fmt_fields, 3473 /* bits */ 112, 3474 /* flags */ 0, 3475 }, 3476 #endif /* chips */ 3477 3478 #if defined(BCM_56860_A0) 3479 { /* SOC_FORMAT_INT_CELLDATA_S_RF_BCM56860_A0fmt */ 3480 /* format CELLDATA_S_RFfmt */ 3481 /* nFields */ 1, 3482 /* *fields */ soc_CELLDATA_S_RF_BCM56640_A0fmt_fields, 3483 /* bits */ 112, 3484 /* flags */ 0, 3485 }, 3486 #endif /* chips */ 3487 3488 #if defined(BCM_56960_A0) 3489 { /* SOC_FORMAT_INT_CELLDATA_S_RF_BCM56960_A0fmt */ 3490 /* format CELLDATA_S_RFfmt */ 3491 /* nFields */ 1, 3492 /* *fields */ soc_CELLDATA_S_RF_BCM56960_A0fmt_fields, 3493 /* bits */ 112, 3494 /* flags */ 0, 3495 }, 3496 #endif /* chips */ 3497 3498 #if defined(BCM_56965_A0) 3499 { /* SOC_FORMAT_INT_CELLDATA_S_RF_BCM56965_A0fmt */ 3500 /* format CELLDATA_S_RFfmt */ 3501 /* nFields */ 1, 3502 /* *fields */ soc_CELLDATA_S_RF_BCM56960_A0fmt_fields, 3503 /* bits */ 112, 3504 /* flags */ 0, 3505 }, 3506 #endif /* chips */ 3507 3508 #if defined(BCM_56970_A0) 3509 { /* SOC_FORMAT_INT_CELLDATA_S_RF_BCM56970_A0fmt */ 3510 /* format CELLDATA_S_RFfmt */ 3511 /* nFields */ 1, 3512 /* *fields */ soc_CELLDATA_S_RF_BCM56960_A0fmt_fields, 3513 /* bits */ 112, 3514 /* flags */ 0, 3515 }, 3516 #endif /* chips */ 3517 3518 #if defined(BCM_88732_A0) 3519 { /* SOC_FORMAT_INT_CELLDATA_S_RF_BCM88732_A0fmt */ 3520 /* format CELLDATA_S_RFfmt */ 3521 /* nFields */ 1, 3522 /* *fields */ soc_CELLDATA_S_RF_BCM88732_A0fmt_fields, 3523 /* bits */ 128, 3524 /* flags */ 0, 3525 }, 3526 #endif /* chips */ 3527 3528 #if defined(BCM_56800_A0) 3529 { /* SOC_FORMAT_INT_CELLHDR_S_RFfmt */ 3530 /* format CELLHDR_S_RFfmt */ 3531 /* nFields */ 1, 3532 /* *fields */ soc_CELLHDR_S_RFfmt_fields, 3533 /* bits */ 84, 3534 /* flags */ 0, 3535 }, 3536 #endif /* chips */ 3537 3538 #if defined(BCM_56142_A0) 3539 { /* SOC_FORMAT_INT_CELLHDR_S_RF_BCM56142_A0fmt */ 3540 /* format CELLHDR_S_RFfmt */ 3541 /* nFields */ 1, 3542 /* *fields */ soc_CELLDATA_S_RF_BCM56142_A0fmt_fields, 3543 /* bits */ 54, 3544 /* flags */ 0, 3545 }, 3546 #endif /* chips */ 3547 3548 #if defined(BCM_56334_A0) 3549 { /* SOC_FORMAT_INT_CELLHDR_S_RF_BCM56334_A0fmt */ 3550 /* format CELLHDR_S_RFfmt */ 3551 /* nFields */ 1, 3552 /* *fields */ soc_CELLHDR_S_RF_BCM56334_A0fmt_fields, 3553 /* bits */ 36, 3554 /* flags */ 0, 3555 }, 3556 #endif /* chips */ 3557 3558 #if defined(BCM_56334_B0) 3559 { /* SOC_FORMAT_INT_CELLHDR_S_RF_BCM56334_B0fmt */ 3560 /* format CELLHDR_S_RFfmt */ 3561 /* nFields */ 1, 3562 /* *fields */ soc_CELLHDR_S_RF_BCM56334_A0fmt_fields, 3563 /* bits */ 36, 3564 /* flags */ 0, 3565 }, 3566 #endif /* chips */ 3567 3568 #if defined(BCM_56524_A0) 3569 { /* SOC_FORMAT_INT_CELLHDR_S_RF_BCM56524_A0fmt */ 3570 /* format CELLHDR_S_RFfmt */ 3571 /* nFields */ 1, 3572 /* *fields */ soc_CELLHDR_S_RF_BCM56624_A0fmt_fields, 3573 /* bits */ 112, 3574 /* flags */ 0, 3575 }, 3576 #endif /* chips */ 3577 3578 #if defined(BCM_56524_B0) 3579 { /* SOC_FORMAT_INT_CELLHDR_S_RF_BCM56524_B0fmt */ 3580 /* format CELLHDR_S_RFfmt */ 3581 /* nFields */ 1, 3582 /* *fields */ soc_CELLHDR_S_RF_BCM56624_A0fmt_fields, 3583 /* bits */ 112, 3584 /* flags */ 0, 3585 }, 3586 #endif /* chips */ 3587 3588 #if defined(BCM_56624_A0) 3589 { /* SOC_FORMAT_INT_CELLHDR_S_RF_BCM56624_A0fmt */ 3590 /* format CELLHDR_S_RFfmt */ 3591 /* nFields */ 1, 3592 /* *fields */ soc_CELLHDR_S_RF_BCM56624_A0fmt_fields, 3593 /* bits */ 112, 3594 /* flags */ 0, 3595 }, 3596 #endif /* chips */ 3597 3598 #if defined(BCM_56624_B0) 3599 { /* SOC_FORMAT_INT_CELLHDR_S_RF_BCM56624_B0fmt */ 3600 /* format CELLHDR_S_RFfmt */ 3601 /* nFields */ 1, 3602 /* *fields */ soc_CELLHDR_S_RF_BCM56624_A0fmt_fields, 3603 /* bits */ 112, 3604 /* flags */ 0, 3605 }, 3606 #endif /* chips */ 3607 3608 #if defined(BCM_56634_A0) 3609 { /* SOC_FORMAT_INT_CELLHDR_S_RF_BCM56634_A0fmt */ 3610 /* format CELLHDR_S_RFfmt */ 3611 /* nFields */ 1, 3612 /* *fields */ soc_CELLHDR_S_RF_BCM56624_A0fmt_fields, 3613 /* bits */ 112, 3614 /* flags */ 0, 3615 }, 3616 #endif /* chips */ 3617 3618 #if defined(BCM_56634_B0) 3619 { /* SOC_FORMAT_INT_CELLHDR_S_RF_BCM56634_B0fmt */ 3620 /* format CELLHDR_S_RFfmt */ 3621 /* nFields */ 1, 3622 /* *fields */ soc_CELLHDR_S_RF_BCM56624_A0fmt_fields, 3623 /* bits */ 112, 3624 /* flags */ 0, 3625 }, 3626 #endif /* chips */ 3627 3628 #if defined(BCM_56680_A0) 3629 { /* SOC_FORMAT_INT_CELLHDR_S_RF_BCM56680_A0fmt */ 3630 /* format CELLHDR_S_RFfmt */ 3631 /* nFields */ 1, 3632 /* *fields */ soc_CELLHDR_S_RF_BCM56624_A0fmt_fields, 3633 /* bits */ 112, 3634 /* flags */ 0, 3635 }, 3636 #endif /* chips */ 3637 3638 #if defined(BCM_56680_B0) 3639 { /* SOC_FORMAT_INT_CELLHDR_S_RF_BCM56680_B0fmt */ 3640 /* format CELLHDR_S_RFfmt */ 3641 /* nFields */ 1, 3642 /* *fields */ soc_CELLHDR_S_RF_BCM56624_A0fmt_fields, 3643 /* bits */ 112, 3644 /* flags */ 0, 3645 }, 3646 #endif /* chips */ 3647 3648 #if defined(BCM_56685_A0) 3649 { /* SOC_FORMAT_INT_CELLHDR_S_RF_BCM56685_A0fmt */ 3650 /* format CELLHDR_S_RFfmt */ 3651 /* nFields */ 1, 3652 /* *fields */ soc_CELLHDR_S_RF_BCM56624_A0fmt_fields, 3653 /* bits */ 112, 3654 /* flags */ 0, 3655 }, 3656 #endif /* chips */ 3657 3658 #if defined(BCM_56685_B0) 3659 { /* SOC_FORMAT_INT_CELLHDR_S_RF_BCM56685_B0fmt */ 3660 /* format CELLHDR_S_RFfmt */ 3661 /* nFields */ 1, 3662 /* *fields */ soc_CELLHDR_S_RF_BCM56624_A0fmt_fields, 3663 /* bits */ 112, 3664 /* flags */ 0, 3665 }, 3666 #endif /* chips */ 3667 3668 #if defined(BCM_56725_A0) 3669 { /* SOC_FORMAT_INT_CELLHDR_S_RF_BCM56725_A0fmt */ 3670 /* format CELLHDR_S_RFfmt */ 3671 /* nFields */ 1, 3672 /* *fields */ soc_CELLHDR_S_RF_BCM56820_A0fmt_fields, 3673 /* bits */ 56, 3674 /* flags */ 0, 3675 }, 3676 #endif /* chips */ 3677 3678 #if defined(BCM_56820_A0) 3679 { /* SOC_FORMAT_INT_CELLHDR_S_RF_BCM56820_A0fmt */ 3680 /* format CELLHDR_S_RFfmt */ 3681 /* nFields */ 1, 3682 /* *fields */ soc_CELLHDR_S_RF_BCM56820_A0fmt_fields, 3683 /* bits */ 56, 3684 /* flags */ 0, 3685 }, 3686 #endif /* chips */ 3687 3688 #if defined(BCM_56800_A0) 3689 { /* SOC_FORMAT_INT_CELLLINK_S_RFfmt */ 3690 /* format CELLLINK_S_RFfmt */ 3691 /* nFields */ 1, 3692 /* *fields */ soc_CELLLINK_S_RFfmt_fields, 3693 /* bits */ 84, 3694 /* flags */ 0, 3695 }, 3696 #endif /* chips */ 3697 3698 #if defined(BCM_56260_A0) 3699 { /* SOC_FORMAT_INT_CELLLINK_S_RF_BCM56260_A0fmt */ 3700 /* format CELLLINK_S_RFfmt */ 3701 /* nFields */ 1, 3702 /* *fields */ soc_CELLLINK_S_RF_BCM56960_A0fmt_fields, 3703 /* bits */ 112, 3704 /* flags */ 0, 3705 }, 3706 #endif /* chips */ 3707 3708 #if defined(BCM_56260_B0) 3709 { /* SOC_FORMAT_INT_CELLLINK_S_RF_BCM56260_B0fmt */ 3710 /* format CELLLINK_S_RFfmt */ 3711 /* nFields */ 1, 3712 /* *fields */ soc_CELLLINK_S_RF_BCM56960_A0fmt_fields, 3713 /* bits */ 112, 3714 /* flags */ 0, 3715 }, 3716 #endif /* chips */ 3717 3718 #if defined(BCM_56270_A0) 3719 { /* SOC_FORMAT_INT_CELLLINK_S_RF_BCM56270_A0fmt */ 3720 /* format CELLLINK_S_RFfmt */ 3721 /* nFields */ 1, 3722 /* *fields */ soc_CELLLINK_S_RF_BCM56960_A0fmt_fields, 3723 /* bits */ 112, 3724 /* flags */ 0, 3725 }, 3726 #endif /* chips */ 3727 3728 #if defined(BCM_56334_A0) 3729 { /* SOC_FORMAT_INT_CELLLINK_S_RF_BCM56334_A0fmt */ 3730 /* format CELLLINK_S_RFfmt */ 3731 /* nFields */ 1, 3732 /* *fields */ soc_CELLLINK_S_RF_BCM56334_A0fmt_fields, 3733 /* bits */ 72, 3734 /* flags */ 0, 3735 }, 3736 #endif /* chips */ 3737 3738 #if defined(BCM_56334_B0) 3739 { /* SOC_FORMAT_INT_CELLLINK_S_RF_BCM56334_B0fmt */ 3740 /* format CELLLINK_S_RFfmt */ 3741 /* nFields */ 1, 3742 /* *fields */ soc_CELLLINK_S_RF_BCM56334_A0fmt_fields, 3743 /* bits */ 72, 3744 /* flags */ 0, 3745 }, 3746 #endif /* chips */ 3747 3748 #if defined(BCM_56340_A0) 3749 { /* SOC_FORMAT_INT_CELLLINK_S_RF_BCM56340_A0fmt */ 3750 /* format CELLLINK_S_RFfmt */ 3751 /* nFields */ 1, 3752 /* *fields */ soc_CELLLINK_S_RF_BCM56640_A0fmt_fields, 3753 /* bits */ 112, 3754 /* flags */ 0, 3755 }, 3756 #endif /* chips */ 3757 3758 #if defined(BCM_56440_A0) 3759 { /* SOC_FORMAT_INT_CELLLINK_S_RF_BCM56440_A0fmt */ 3760 /* format CELLLINK_S_RFfmt */ 3761 /* nFields */ 1, 3762 /* *fields */ soc_CELLLINK_S_RF_BCM56624_A0fmt_fields, 3763 /* bits */ 112, 3764 /* flags */ 0, 3765 }, 3766 #endif /* chips */ 3767 3768 #if defined(BCM_56440_B0) 3769 { /* SOC_FORMAT_INT_CELLLINK_S_RF_BCM56440_B0fmt */ 3770 /* format CELLLINK_S_RFfmt */ 3771 /* nFields */ 1, 3772 /* *fields */ soc_CELLLINK_S_RF_BCM56624_A0fmt_fields, 3773 /* bits */ 112, 3774 /* flags */ 0, 3775 }, 3776 #endif /* chips */ 3777 3778 #if defined(BCM_56450_A0) 3779 { /* SOC_FORMAT_INT_CELLLINK_S_RF_BCM56450_A0fmt */ 3780 /* format CELLLINK_S_RFfmt */ 3781 /* nFields */ 1, 3782 /* *fields */ soc_CELLLINK_S_RF_BCM56640_A0fmt_fields, 3783 /* bits */ 112, 3784 /* flags */ 0, 3785 }, 3786 #endif /* chips */ 3787 3788 #if defined(BCM_56450_B0) 3789 { /* SOC_FORMAT_INT_CELLLINK_S_RF_BCM56450_B0fmt */ 3790 /* format CELLLINK_S_RFfmt */ 3791 /* nFields */ 1, 3792 /* *fields */ soc_CELLLINK_S_RF_BCM56640_A0fmt_fields, 3793 /* bits */ 112, 3794 /* flags */ 0, 3795 }, 3796 #endif /* chips */ 3797 3798 #if defined(BCM_56450_B1) 3799 { /* SOC_FORMAT_INT_CELLLINK_S_RF_BCM56450_B1fmt */ 3800 /* format CELLLINK_S_RFfmt */ 3801 /* nFields */ 1, 3802 /* *fields */ soc_CELLLINK_S_RF_BCM56640_A0fmt_fields, 3803 /* bits */ 112, 3804 /* flags */ 0, 3805 }, 3806 #endif /* chips */ 3807 3808 #if defined(BCM_56524_A0) 3809 { /* SOC_FORMAT_INT_CELLLINK_S_RF_BCM56524_A0fmt */ 3810 /* format CELLLINK_S_RFfmt */ 3811 /* nFields */ 1, 3812 /* *fields */ soc_CELLLINK_S_RF_BCM56624_A0fmt_fields, 3813 /* bits */ 112, 3814 /* flags */ 0, 3815 }, 3816 #endif /* chips */ 3817 3818 #if defined(BCM_56524_B0) 3819 { /* SOC_FORMAT_INT_CELLLINK_S_RF_BCM56524_B0fmt */ 3820 /* format CELLLINK_S_RFfmt */ 3821 /* nFields */ 1, 3822 /* *fields */ soc_CELLLINK_S_RF_BCM56624_A0fmt_fields, 3823 /* bits */ 112, 3824 /* flags */ 0, 3825 }, 3826 #endif /* chips */ 3827 3828 #if defined(BCM_56560_A0) 3829 { /* SOC_FORMAT_INT_CELLLINK_S_RF_BCM56560_A0fmt */ 3830 /* format CELLLINK_S_RFfmt */ 3831 /* nFields */ 1, 3832 /* *fields */ soc_CELLLINK_S_RF_BCM56960_A0fmt_fields, 3833 /* bits */ 112, 3834 /* flags */ 0, 3835 }, 3836 #endif /* chips */ 3837 3838 #if defined(BCM_56560_B0) 3839 { /* SOC_FORMAT_INT_CELLLINK_S_RF_BCM56560_B0fmt */ 3840 /* format CELLLINK_S_RFfmt */ 3841 /* nFields */ 1, 3842 /* *fields */ soc_CELLLINK_S_RF_BCM56960_A0fmt_fields, 3843 /* bits */ 112, 3844 /* flags */ 0, 3845 }, 3846 #endif /* chips */ 3847 3848 #if defined(BCM_56624_A0) 3849 { /* SOC_FORMAT_INT_CELLLINK_S_RF_BCM56624_A0fmt */ 3850 /* format CELLLINK_S_RFfmt */ 3851 /* nFields */ 1, 3852 /* *fields */ soc_CELLLINK_S_RF_BCM56624_A0fmt_fields, 3853 /* bits */ 112, 3854 /* flags */ 0, 3855 }, 3856 #endif /* chips */ 3857 3858 #if defined(BCM_56624_B0) 3859 { /* SOC_FORMAT_INT_CELLLINK_S_RF_BCM56624_B0fmt */ 3860 /* format CELLLINK_S_RFfmt */ 3861 /* nFields */ 1, 3862 /* *fields */ soc_CELLLINK_S_RF_BCM56624_A0fmt_fields, 3863 /* bits */ 112, 3864 /* flags */ 0, 3865 }, 3866 #endif /* chips */ 3867 3868 #if defined(BCM_56634_A0) 3869 { /* SOC_FORMAT_INT_CELLLINK_S_RF_BCM56634_A0fmt */ 3870 /* format CELLLINK_S_RFfmt */ 3871 /* nFields */ 1, 3872 /* *fields */ soc_CELLLINK_S_RF_BCM56624_A0fmt_fields, 3873 /* bits */ 112, 3874 /* flags */ 0, 3875 }, 3876 #endif /* chips */ 3877 3878 #if defined(BCM_56634_B0) 3879 { /* SOC_FORMAT_INT_CELLLINK_S_RF_BCM56634_B0fmt */ 3880 /* format CELLLINK_S_RFfmt */ 3881 /* nFields */ 1, 3882 /* *fields */ soc_CELLLINK_S_RF_BCM56624_A0fmt_fields, 3883 /* bits */ 112, 3884 /* flags */ 0, 3885 }, 3886 #endif /* chips */ 3887 3888 #if defined(BCM_56640_A0) 3889 { /* SOC_FORMAT_INT_CELLLINK_S_RF_BCM56640_A0fmt */ 3890 /* format CELLLINK_S_RFfmt */ 3891 /* nFields */ 1, 3892 /* *fields */ soc_CELLLINK_S_RF_BCM56640_A0fmt_fields, 3893 /* bits */ 112, 3894 /* flags */ 0, 3895 }, 3896 #endif /* chips */ 3897 3898 #if defined(BCM_56670_A0) 3899 { /* SOC_FORMAT_INT_CELLLINK_S_RF_BCM56670_A0fmt */ 3900 /* format CELLLINK_S_RFfmt */ 3901 /* nFields */ 1, 3902 /* *fields */ soc_CELLLINK_S_RF_BCM56960_A0fmt_fields, 3903 /* bits */ 112, 3904 /* flags */ 0, 3905 }, 3906 #endif /* chips */ 3907 3908 #if defined(BCM_56670_B0) 3909 { /* SOC_FORMAT_INT_CELLLINK_S_RF_BCM56670_B0fmt */ 3910 /* format CELLLINK_S_RFfmt */ 3911 /* nFields */ 1, 3912 /* *fields */ soc_CELLLINK_S_RF_BCM56960_A0fmt_fields, 3913 /* bits */ 112, 3914 /* flags */ 0, 3915 }, 3916 #endif /* chips */ 3917 3918 #if defined(BCM_56680_A0) 3919 { /* SOC_FORMAT_INT_CELLLINK_S_RF_BCM56680_A0fmt */ 3920 /* format CELLLINK_S_RFfmt */ 3921 /* nFields */ 1, 3922 /* *fields */ soc_CELLLINK_S_RF_BCM56624_A0fmt_fields, 3923 /* bits */ 112, 3924 /* flags */ 0, 3925 }, 3926 #endif /* chips */ 3927 3928 #if defined(BCM_56680_B0) 3929 { /* SOC_FORMAT_INT_CELLLINK_S_RF_BCM56680_B0fmt */ 3930 /* format CELLLINK_S_RFfmt */ 3931 /* nFields */ 1, 3932 /* *fields */ soc_CELLLINK_S_RF_BCM56624_A0fmt_fields, 3933 /* bits */ 112, 3934 /* flags */ 0, 3935 }, 3936 #endif /* chips */ 3937 3938 #if defined(BCM_56685_A0) 3939 { /* SOC_FORMAT_INT_CELLLINK_S_RF_BCM56685_A0fmt */ 3940 /* format CELLLINK_S_RFfmt */ 3941 /* nFields */ 1, 3942 /* *fields */ soc_CELLLINK_S_RF_BCM56624_A0fmt_fields, 3943 /* bits */ 112, 3944 /* flags */ 0, 3945 }, 3946 #endif /* chips */ 3947 3948 #if defined(BCM_56685_B0) 3949 { /* SOC_FORMAT_INT_CELLLINK_S_RF_BCM56685_B0fmt */ 3950 /* format CELLLINK_S_RFfmt */ 3951 /* nFields */ 1, 3952 /* *fields */ soc_CELLLINK_S_RF_BCM56624_A0fmt_fields, 3953 /* bits */ 112, 3954 /* flags */ 0, 3955 }, 3956 #endif /* chips */ 3957 3958 #if defined(BCM_56725_A0) 3959 { /* SOC_FORMAT_INT_CELLLINK_S_RF_BCM56725_A0fmt */ 3960 /* format CELLLINK_S_RFfmt */ 3961 /* nFields */ 1, 3962 /* *fields */ soc_CELLLINK_S_RF_BCM56624_A0fmt_fields, 3963 /* bits */ 112, 3964 /* flags */ 0, 3965 }, 3966 #endif /* chips */ 3967 3968 #if defined(BCM_56820_A0) 3969 { /* SOC_FORMAT_INT_CELLLINK_S_RF_BCM56820_A0fmt */ 3970 /* format CELLLINK_S_RFfmt */ 3971 /* nFields */ 1, 3972 /* *fields */ soc_CELLLINK_S_RF_BCM56624_A0fmt_fields, 3973 /* bits */ 112, 3974 /* flags */ 0, 3975 }, 3976 #endif /* chips */ 3977 3978 #if defined(BCM_56840_A0) 3979 { /* SOC_FORMAT_INT_CELLLINK_S_RF_BCM56840_A0fmt */ 3980 /* format CELLLINK_S_RFfmt */ 3981 /* nFields */ 1, 3982 /* *fields */ soc_CELLLINK_S_RF_BCM56624_A0fmt_fields, 3983 /* bits */ 112, 3984 /* flags */ 0, 3985 }, 3986 #endif /* chips */ 3987 3988 #if defined(BCM_56840_B0) 3989 { /* SOC_FORMAT_INT_CELLLINK_S_RF_BCM56840_B0fmt */ 3990 /* format CELLLINK_S_RFfmt */ 3991 /* nFields */ 1, 3992 /* *fields */ soc_CELLLINK_S_RF_BCM56624_A0fmt_fields, 3993 /* bits */ 112, 3994 /* flags */ 0, 3995 }, 3996 #endif /* chips */ 3997 3998 #if defined(BCM_56850_A0) 3999 { /* SOC_FORMAT_INT_CELLLINK_S_RF_BCM56850_A0fmt */ 4000 /* format CELLLINK_S_RFfmt */ 4001 /* nFields */ 1, 4002 /* *fields */ soc_CELLLINK_S_RF_BCM56640_A0fmt_fields, 4003 /* bits */ 112, 4004 /* flags */ 0, 4005 }, 4006 #endif /* chips */ 4007 4008 #if defined(BCM_56860_A0) 4009 { /* SOC_FORMAT_INT_CELLLINK_S_RF_BCM56860_A0fmt */ 4010 /* format CELLLINK_S_RFfmt */ 4011 /* nFields */ 1, 4012 /* *fields */ soc_CELLLINK_S_RF_BCM56640_A0fmt_fields, 4013 /* bits */ 112, 4014 /* flags */ 0, 4015 }, 4016 #endif /* chips */ 4017 4018 #if defined(BCM_56960_A0) 4019 { /* SOC_FORMAT_INT_CELLLINK_S_RF_BCM56960_A0fmt */ 4020 /* format CELLLINK_S_RFfmt */ 4021 /* nFields */ 1, 4022 /* *fields */ soc_CELLLINK_S_RF_BCM56960_A0fmt_fields, 4023 /* bits */ 112, 4024 /* flags */ 0, 4025 }, 4026 #endif /* chips */ 4027 4028 #if defined(BCM_56965_A0) 4029 { /* SOC_FORMAT_INT_CELLLINK_S_RF_BCM56965_A0fmt */ 4030 /* format CELLLINK_S_RFfmt */ 4031 /* nFields */ 1, 4032 /* *fields */ soc_CELLLINK_S_RF_BCM56960_A0fmt_fields, 4033 /* bits */ 112, 4034 /* flags */ 0, 4035 }, 4036 #endif /* chips */ 4037 4038 #if defined(BCM_56970_A0) 4039 { /* SOC_FORMAT_INT_CELLLINK_S_RF_BCM56970_A0fmt */ 4040 /* format CELLLINK_S_RFfmt */ 4041 /* nFields */ 1, 4042 /* *fields */ soc_CELLLINK_S_RF_BCM56960_A0fmt_fields, 4043 /* bits */ 112, 4044 /* flags */ 0, 4045 }, 4046 #endif /* chips */ 4047 4048 #if defined(BCM_88732_A0) 4049 { /* SOC_FORMAT_INT_CELLLINK_S_RF_BCM88732_A0fmt */ 4050 /* format CELLLINK_S_RFfmt */ 4051 /* nFields */ 1, 4052 /* *fields */ soc_CELLLINK_S_RF_BCM56334_A0fmt_fields, 4053 /* bits */ 72, 4054 /* flags */ 0, 4055 }, 4056 #endif /* chips */ 4057 4058 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) || \ 4059 defined(BCM_56970_A0) 4060 { /* SOC_FORMAT_INT_CEV_CHAIN_IDfmt */ 4061 /* format CEV_CHAIN_IDfmt */ 4062 /* nFields */ 2, 4063 /* *fields */ soc_CEV_CHAIN_IDfmt_fields, 4064 /* bits */ 8, 4065 /* flags */ 0, 4066 }, 4067 #endif /* chips */ 4068 4069 #if defined(BCM_56370_A0) 4070 { /* SOC_FORMAT_INT_CEV_CHAIN_ID_BCM56370_A0fmt */ 4071 /* format CEV_CHAIN_IDfmt */ 4072 /* nFields */ 2, 4073 /* *fields */ soc_CEV_CHAIN_ID_BCM56870_A0fmt_fields, 4074 /* bits */ 7, 4075 /* flags */ 0, 4076 }, 4077 #endif /* chips */ 4078 4079 #if defined(BCM_56770_A0) 4080 { /* SOC_FORMAT_INT_CEV_CHAIN_ID_BCM56770_A0fmt */ 4081 /* format CEV_CHAIN_IDfmt */ 4082 /* nFields */ 2, 4083 /* *fields */ soc_CEV_CHAIN_ID_BCM56870_A0fmt_fields, 4084 /* bits */ 7, 4085 /* flags */ 0, 4086 }, 4087 #endif /* chips */ 4088 4089 #if defined(BCM_56870_A0) 4090 { /* SOC_FORMAT_INT_CEV_CHAIN_ID_BCM56870_A0fmt */ 4091 /* format CEV_CHAIN_IDfmt */ 4092 /* nFields */ 2, 4093 /* *fields */ soc_CEV_CHAIN_ID_BCM56870_A0fmt_fields, 4094 /* bits */ 7, 4095 /* flags */ 0, 4096 }, 4097 #endif /* chips */ 4098 4099 #if defined(BCM_56800_A0) 4100 { /* SOC_FORMAT_INT_CFAP_S_RFfmt */ 4101 /* format CFAP_S_RFfmt */ 4102 /* nFields */ 1, 4103 /* *fields */ soc_CFAP_S_RFfmt_fields, 4104 /* bits */ 64, 4105 /* flags */ 0, 4106 }, 4107 #endif /* chips */ 4108 4109 #if defined(BCM_56142_A0) 4110 { /* SOC_FORMAT_INT_CFAP_S_RF_BCM56142_A0fmt */ 4111 /* format CFAP_S_RFfmt */ 4112 /* nFields */ 1, 4113 /* *fields */ soc_CELLDATA_S_RF_BCM56142_A0fmt_fields, 4114 /* bits */ 54, 4115 /* flags */ 0, 4116 }, 4117 #endif /* chips */ 4118 4119 #if defined(BCM_56260_A0) 4120 { /* SOC_FORMAT_INT_CFAP_S_RF_BCM56260_A0fmt */ 4121 /* format CFAP_S_RFfmt */ 4122 /* nFields */ 1, 4123 /* *fields */ soc_CFAP_S_RF_BCM56960_A0fmt_fields, 4124 /* bits */ 36, 4125 /* flags */ 0, 4126 }, 4127 #endif /* chips */ 4128 4129 #if defined(BCM_56260_B0) 4130 { /* SOC_FORMAT_INT_CFAP_S_RF_BCM56260_B0fmt */ 4131 /* format CFAP_S_RFfmt */ 4132 /* nFields */ 1, 4133 /* *fields */ soc_CFAP_S_RF_BCM56960_A0fmt_fields, 4134 /* bits */ 36, 4135 /* flags */ 0, 4136 }, 4137 #endif /* chips */ 4138 4139 #if defined(BCM_56270_A0) 4140 { /* SOC_FORMAT_INT_CFAP_S_RF_BCM56270_A0fmt */ 4141 /* format CFAP_S_RFfmt */ 4142 /* nFields */ 1, 4143 /* *fields */ soc_CFAP_S_RF_BCM56960_A0fmt_fields, 4144 /* bits */ 36, 4145 /* flags */ 0, 4146 }, 4147 #endif /* chips */ 4148 4149 #if defined(BCM_56334_A0) 4150 { /* SOC_FORMAT_INT_CFAP_S_RF_BCM56334_A0fmt */ 4151 /* format CFAP_S_RFfmt */ 4152 /* nFields */ 1, 4153 /* *fields */ soc_CFAP_S_RF_BCM56820_A0fmt_fields, 4154 /* bits */ 18, 4155 /* flags */ 0, 4156 }, 4157 #endif /* chips */ 4158 4159 #if defined(BCM_56334_B0) 4160 { /* SOC_FORMAT_INT_CFAP_S_RF_BCM56334_B0fmt */ 4161 /* format CFAP_S_RFfmt */ 4162 /* nFields */ 1, 4163 /* *fields */ soc_CFAP_S_RF_BCM56820_A0fmt_fields, 4164 /* bits */ 18, 4165 /* flags */ 0, 4166 }, 4167 #endif /* chips */ 4168 4169 #if defined(BCM_56340_A0) 4170 { /* SOC_FORMAT_INT_CFAP_S_RF_BCM56340_A0fmt */ 4171 /* format CFAP_S_RFfmt */ 4172 /* nFields */ 1, 4173 /* *fields */ soc_CFAP_S_RF_BCM56640_A0fmt_fields, 4174 /* bits */ 36, 4175 /* flags */ 0, 4176 }, 4177 #endif /* chips */ 4178 4179 #if defined(BCM_56440_A0) 4180 { /* SOC_FORMAT_INT_CFAP_S_RF_BCM56440_A0fmt */ 4181 /* format CFAP_S_RFfmt */ 4182 /* nFields */ 1, 4183 /* *fields */ soc_CFAP_S_RF_BCM56624_A0fmt_fields, 4184 /* bits */ 36, 4185 /* flags */ 0, 4186 }, 4187 #endif /* chips */ 4188 4189 #if defined(BCM_56440_B0) 4190 { /* SOC_FORMAT_INT_CFAP_S_RF_BCM56440_B0fmt */ 4191 /* format CFAP_S_RFfmt */ 4192 /* nFields */ 1, 4193 /* *fields */ soc_CFAP_S_RF_BCM56624_A0fmt_fields, 4194 /* bits */ 36, 4195 /* flags */ 0, 4196 }, 4197 #endif /* chips */ 4198 4199 #if defined(BCM_56450_A0) 4200 { /* SOC_FORMAT_INT_CFAP_S_RF_BCM56450_A0fmt */ 4201 /* format CFAP_S_RFfmt */ 4202 /* nFields */ 1, 4203 /* *fields */ soc_CFAP_S_RF_BCM56640_A0fmt_fields, 4204 /* bits */ 36, 4205 /* flags */ 0, 4206 }, 4207 #endif /* chips */ 4208 4209 #if defined(BCM_56450_B0) 4210 { /* SOC_FORMAT_INT_CFAP_S_RF_BCM56450_B0fmt */ 4211 /* format CFAP_S_RFfmt */ 4212 /* nFields */ 1, 4213 /* *fields */ soc_CFAP_S_RF_BCM56640_A0fmt_fields, 4214 /* bits */ 36, 4215 /* flags */ 0, 4216 }, 4217 #endif /* chips */ 4218 4219 #if defined(BCM_56450_B1) 4220 { /* SOC_FORMAT_INT_CFAP_S_RF_BCM56450_B1fmt */ 4221 /* format CFAP_S_RFfmt */ 4222 /* nFields */ 1, 4223 /* *fields */ soc_CFAP_S_RF_BCM56640_A0fmt_fields, 4224 /* bits */ 36, 4225 /* flags */ 0, 4226 }, 4227 #endif /* chips */ 4228 4229 #if defined(BCM_56524_A0) 4230 { /* SOC_FORMAT_INT_CFAP_S_RF_BCM56524_A0fmt */ 4231 /* format CFAP_S_RFfmt */ 4232 /* nFields */ 1, 4233 /* *fields */ soc_CFAP_S_RF_BCM56624_A0fmt_fields, 4234 /* bits */ 36, 4235 /* flags */ 0, 4236 }, 4237 #endif /* chips */ 4238 4239 #if defined(BCM_56524_B0) 4240 { /* SOC_FORMAT_INT_CFAP_S_RF_BCM56524_B0fmt */ 4241 /* format CFAP_S_RFfmt */ 4242 /* nFields */ 1, 4243 /* *fields */ soc_CFAP_S_RF_BCM56624_A0fmt_fields, 4244 /* bits */ 36, 4245 /* flags */ 0, 4246 }, 4247 #endif /* chips */ 4248 4249 #if defined(BCM_56560_A0) 4250 { /* SOC_FORMAT_INT_CFAP_S_RF_BCM56560_A0fmt */ 4251 /* format CFAP_S_RFfmt */ 4252 /* nFields */ 1, 4253 /* *fields */ soc_CFAP_S_RF_BCM56960_A0fmt_fields, 4254 /* bits */ 36, 4255 /* flags */ 0, 4256 }, 4257 #endif /* chips */ 4258 4259 #if defined(BCM_56560_B0) 4260 { /* SOC_FORMAT_INT_CFAP_S_RF_BCM56560_B0fmt */ 4261 /* format CFAP_S_RFfmt */ 4262 /* nFields */ 1, 4263 /* *fields */ soc_CFAP_S_RF_BCM56960_A0fmt_fields, 4264 /* bits */ 36, 4265 /* flags */ 0, 4266 }, 4267 #endif /* chips */ 4268 4269 #if defined(BCM_56624_A0) 4270 { /* SOC_FORMAT_INT_CFAP_S_RF_BCM56624_A0fmt */ 4271 /* format CFAP_S_RFfmt */ 4272 /* nFields */ 1, 4273 /* *fields */ soc_CFAP_S_RF_BCM56624_A0fmt_fields, 4274 /* bits */ 36, 4275 /* flags */ 0, 4276 }, 4277 #endif /* chips */ 4278 4279 #if defined(BCM_56624_B0) 4280 { /* SOC_FORMAT_INT_CFAP_S_RF_BCM56624_B0fmt */ 4281 /* format CFAP_S_RFfmt */ 4282 /* nFields */ 1, 4283 /* *fields */ soc_CFAP_S_RF_BCM56624_A0fmt_fields, 4284 /* bits */ 36, 4285 /* flags */ 0, 4286 }, 4287 #endif /* chips */ 4288 4289 #if defined(BCM_56634_A0) 4290 { /* SOC_FORMAT_INT_CFAP_S_RF_BCM56634_A0fmt */ 4291 /* format CFAP_S_RFfmt */ 4292 /* nFields */ 1, 4293 /* *fields */ soc_CFAP_S_RF_BCM56624_A0fmt_fields, 4294 /* bits */ 36, 4295 /* flags */ 0, 4296 }, 4297 #endif /* chips */ 4298 4299 #if defined(BCM_56634_B0) 4300 { /* SOC_FORMAT_INT_CFAP_S_RF_BCM56634_B0fmt */ 4301 /* format CFAP_S_RFfmt */ 4302 /* nFields */ 1, 4303 /* *fields */ soc_CFAP_S_RF_BCM56624_A0fmt_fields, 4304 /* bits */ 36, 4305 /* flags */ 0, 4306 }, 4307 #endif /* chips */ 4308 4309 #if defined(BCM_56640_A0) 4310 { /* SOC_FORMAT_INT_CFAP_S_RF_BCM56640_A0fmt */ 4311 /* format CFAP_S_RFfmt */ 4312 /* nFields */ 1, 4313 /* *fields */ soc_CFAP_S_RF_BCM56640_A0fmt_fields, 4314 /* bits */ 36, 4315 /* flags */ 0, 4316 }, 4317 #endif /* chips */ 4318 4319 #if defined(BCM_56670_A0) 4320 { /* SOC_FORMAT_INT_CFAP_S_RF_BCM56670_A0fmt */ 4321 /* format CFAP_S_RFfmt */ 4322 /* nFields */ 1, 4323 /* *fields */ soc_CFAP_S_RF_BCM56960_A0fmt_fields, 4324 /* bits */ 36, 4325 /* flags */ 0, 4326 }, 4327 #endif /* chips */ 4328 4329 #if defined(BCM_56670_B0) 4330 { /* SOC_FORMAT_INT_CFAP_S_RF_BCM56670_B0fmt */ 4331 /* format CFAP_S_RFfmt */ 4332 /* nFields */ 1, 4333 /* *fields */ soc_CFAP_S_RF_BCM56960_A0fmt_fields, 4334 /* bits */ 36, 4335 /* flags */ 0, 4336 }, 4337 #endif /* chips */ 4338 4339 #if defined(BCM_56680_A0) 4340 { /* SOC_FORMAT_INT_CFAP_S_RF_BCM56680_A0fmt */ 4341 /* format CFAP_S_RFfmt */ 4342 /* nFields */ 1, 4343 /* *fields */ soc_CFAP_S_RF_BCM56624_A0fmt_fields, 4344 /* bits */ 36, 4345 /* flags */ 0, 4346 }, 4347 #endif /* chips */ 4348 4349 #if defined(BCM_56680_B0) 4350 { /* SOC_FORMAT_INT_CFAP_S_RF_BCM56680_B0fmt */ 4351 /* format CFAP_S_RFfmt */ 4352 /* nFields */ 1, 4353 /* *fields */ soc_CFAP_S_RF_BCM56624_A0fmt_fields, 4354 /* bits */ 36, 4355 /* flags */ 0, 4356 }, 4357 #endif /* chips */ 4358 4359 #if defined(BCM_56685_A0) 4360 { /* SOC_FORMAT_INT_CFAP_S_RF_BCM56685_A0fmt */ 4361 /* format CFAP_S_RFfmt */ 4362 /* nFields */ 1, 4363 /* *fields */ soc_CFAP_S_RF_BCM56624_A0fmt_fields, 4364 /* bits */ 36, 4365 /* flags */ 0, 4366 }, 4367 #endif /* chips */ 4368 4369 #if defined(BCM_56685_B0) 4370 { /* SOC_FORMAT_INT_CFAP_S_RF_BCM56685_B0fmt */ 4371 /* format CFAP_S_RFfmt */ 4372 /* nFields */ 1, 4373 /* *fields */ soc_CFAP_S_RF_BCM56624_A0fmt_fields, 4374 /* bits */ 36, 4375 /* flags */ 0, 4376 }, 4377 #endif /* chips */ 4378 4379 #if defined(BCM_56725_A0) 4380 { /* SOC_FORMAT_INT_CFAP_S_RF_BCM56725_A0fmt */ 4381 /* format CFAP_S_RFfmt */ 4382 /* nFields */ 1, 4383 /* *fields */ soc_CFAP_S_RF_BCM56820_A0fmt_fields, 4384 /* bits */ 18, 4385 /* flags */ 0, 4386 }, 4387 #endif /* chips */ 4388 4389 #if defined(BCM_56820_A0) 4390 { /* SOC_FORMAT_INT_CFAP_S_RF_BCM56820_A0fmt */ 4391 /* format CFAP_S_RFfmt */ 4392 /* nFields */ 1, 4393 /* *fields */ soc_CFAP_S_RF_BCM56820_A0fmt_fields, 4394 /* bits */ 18, 4395 /* flags */ 0, 4396 }, 4397 #endif /* chips */ 4398 4399 #if defined(BCM_56840_A0) 4400 { /* SOC_FORMAT_INT_CFAP_S_RF_BCM56840_A0fmt */ 4401 /* format CFAP_S_RFfmt */ 4402 /* nFields */ 1, 4403 /* *fields */ soc_CFAP_S_RF_BCM56624_A0fmt_fields, 4404 /* bits */ 36, 4405 /* flags */ 0, 4406 }, 4407 #endif /* chips */ 4408 4409 #if defined(BCM_56840_B0) 4410 { /* SOC_FORMAT_INT_CFAP_S_RF_BCM56840_B0fmt */ 4411 /* format CFAP_S_RFfmt */ 4412 /* nFields */ 1, 4413 /* *fields */ soc_CFAP_S_RF_BCM56624_A0fmt_fields, 4414 /* bits */ 36, 4415 /* flags */ 0, 4416 }, 4417 #endif /* chips */ 4418 4419 #if defined(BCM_56850_A0) 4420 { /* SOC_FORMAT_INT_CFAP_S_RF_BCM56850_A0fmt */ 4421 /* format CFAP_S_RFfmt */ 4422 /* nFields */ 1, 4423 /* *fields */ soc_CFAP_S_RF_BCM56640_A0fmt_fields, 4424 /* bits */ 36, 4425 /* flags */ 0, 4426 }, 4427 #endif /* chips */ 4428 4429 #if defined(BCM_56860_A0) 4430 { /* SOC_FORMAT_INT_CFAP_S_RF_BCM56860_A0fmt */ 4431 /* format CFAP_S_RFfmt */ 4432 /* nFields */ 1, 4433 /* *fields */ soc_CFAP_S_RF_BCM56640_A0fmt_fields, 4434 /* bits */ 36, 4435 /* flags */ 0, 4436 }, 4437 #endif /* chips */ 4438 4439 #if defined(BCM_56960_A0) 4440 { /* SOC_FORMAT_INT_CFAP_S_RF_BCM56960_A0fmt */ 4441 /* format CFAP_S_RFfmt */ 4442 /* nFields */ 1, 4443 /* *fields */ soc_CFAP_S_RF_BCM56960_A0fmt_fields, 4444 /* bits */ 36, 4445 /* flags */ 0, 4446 }, 4447 #endif /* chips */ 4448 4449 #if defined(BCM_56965_A0) 4450 { /* SOC_FORMAT_INT_CFAP_S_RF_BCM56965_A0fmt */ 4451 /* format CFAP_S_RFfmt */ 4452 /* nFields */ 1, 4453 /* *fields */ soc_CFAP_S_RF_BCM56960_A0fmt_fields, 4454 /* bits */ 36, 4455 /* flags */ 0, 4456 }, 4457 #endif /* chips */ 4458 4459 #if defined(BCM_56970_A0) 4460 { /* SOC_FORMAT_INT_CFAP_S_RF_BCM56970_A0fmt */ 4461 /* format CFAP_S_RFfmt */ 4462 /* nFields */ 1, 4463 /* *fields */ soc_CFAP_S_RF_BCM56960_A0fmt_fields, 4464 /* bits */ 36, 4465 /* flags */ 0, 4466 }, 4467 #endif /* chips */ 4468 4469 #if defined(BCM_88732_A0) 4470 { /* SOC_FORMAT_INT_CFAP_S_RF_BCM88732_A0fmt */ 4471 /* format CFAP_S_RFfmt */ 4472 /* nFields */ 1, 4473 /* *fields */ soc_CFAP_S_RF_BCM88732_A0fmt_fields, 4474 /* bits */ 54, 4475 /* flags */ 0, 4476 }, 4477 #endif /* chips */ 4478 4479 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) 4480 { /* SOC_FORMAT_INT_CFG_EOP_BUFFERfmt */ 4481 /* format CFG_EOP_BUFFERfmt */ 4482 /* nFields */ 3, 4483 /* *fields */ soc_CFG_EOP_BUFFERfmt_fields, 4484 /* bits */ 9, 4485 /* flags */ 0, 4486 }, 4487 #endif /* chips */ 4488 4489 #if defined(BCM_56370_A0) 4490 { /* SOC_FORMAT_INT_CFG_EOP_BUFFER_BCM56370_A0fmt */ 4491 /* format CFG_EOP_BUFFERfmt */ 4492 /* nFields */ 4, 4493 /* *fields */ soc_CFG_EOP_BUFFER_BCM56370_A0fmt_fields, 4494 /* bits */ 9, 4495 /* flags */ 0, 4496 }, 4497 #endif /* chips */ 4498 4499 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) 4500 { /* SOC_FORMAT_INT_CFG_TO_CTR_REG_INFOfmt */ 4501 /* format CFG_TO_CTR_REG_INFOfmt */ 4502 /* nFields */ 1, 4503 /* *fields */ soc_CFG_TO_CTR_REG_INFOfmt_fields, 4504 /* bits */ 1, 4505 /* flags */ 0, 4506 }, 4507 #endif /* chips */ 4508 4509 #if defined(BCM_56260_A0) 4510 { /* SOC_FORMAT_INT_CFG_TO_CTR_REG_INFO_BCM56260_A0fmt */ 4511 /* format CFG_TO_CTR_REG_INFOfmt */ 4512 /* nFields */ 1, 4513 /* *fields */ soc_CFG_TO_CTR_REG_INFO_BCM56260_A0fmt_fields, 4514 /* bits */ 1, 4515 /* flags */ 0, 4516 }, 4517 #endif /* chips */ 4518 4519 #if defined(BCM_56260_B0) 4520 { /* SOC_FORMAT_INT_CFG_TO_CTR_REG_INFO_BCM56260_B0fmt */ 4521 /* format CFG_TO_CTR_REG_INFOfmt */ 4522 /* nFields */ 1, 4523 /* *fields */ soc_CFG_TO_CTR_REG_INFO_BCM56260_A0fmt_fields, 4524 /* bits */ 1, 4525 /* flags */ 0, 4526 }, 4527 #endif /* chips */ 4528 4529 #if defined(BCM_56270_A0) 4530 { /* SOC_FORMAT_INT_CFG_TO_CTR_REG_INFO_BCM56270_A0fmt */ 4531 /* format CFG_TO_CTR_REG_INFOfmt */ 4532 /* nFields */ 1, 4533 /* *fields */ soc_CFG_TO_CTR_REG_INFO_BCM56260_A0fmt_fields, 4534 /* bits */ 1, 4535 /* flags */ 0, 4536 }, 4537 #endif /* chips */ 4538 4539 #if defined(BCM_56450_A0) 4540 { /* SOC_FORMAT_INT_CFG_TO_CTR_REG_INFO_BCM56450_A0fmt */ 4541 /* format CFG_TO_CTR_REG_INFOfmt */ 4542 /* nFields */ 1, 4543 /* *fields */ soc_CFG_TO_CTR_REG_INFO_BCM56450_A0fmt_fields, 4544 /* bits */ 1, 4545 /* flags */ 0, 4546 }, 4547 #endif /* chips */ 4548 4549 #if defined(BCM_56450_B0) 4550 { /* SOC_FORMAT_INT_CFG_TO_CTR_REG_INFO_BCM56450_B0fmt */ 4551 /* format CFG_TO_CTR_REG_INFOfmt */ 4552 /* nFields */ 1, 4553 /* *fields */ soc_CFG_TO_CTR_REG_INFO_BCM56450_A0fmt_fields, 4554 /* bits */ 1, 4555 /* flags */ 0, 4556 }, 4557 #endif /* chips */ 4558 4559 #if defined(BCM_56450_B1) 4560 { /* SOC_FORMAT_INT_CFG_TO_CTR_REG_INFO_BCM56450_B1fmt */ 4561 /* format CFG_TO_CTR_REG_INFOfmt */ 4562 /* nFields */ 1, 4563 /* *fields */ soc_CFG_TO_CTR_REG_INFO_BCM56450_A0fmt_fields, 4564 /* bits */ 1, 4565 /* flags */ 0, 4566 }, 4567 #endif /* chips */ 4568 4569 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) 4570 { /* SOC_FORMAT_INT_CFG_TO_ENQ_REG_INFOfmt */ 4571 /* format CFG_TO_ENQ_REG_INFOfmt */ 4572 /* nFields */ 1, 4573 /* *fields */ soc_CFG_TO_ENQ_REG_INFOfmt_fields, 4574 /* bits */ 36, 4575 /* flags */ 0, 4576 }, 4577 #endif /* chips */ 4578 4579 #if defined(BCM_56260_A0) 4580 { /* SOC_FORMAT_INT_CFG_TO_ENQ_REG_INFO_BCM56260_A0fmt */ 4581 /* format CFG_TO_ENQ_REG_INFOfmt */ 4582 /* nFields */ 1, 4583 /* *fields */ soc_CFG_TO_ENQ_REG_INFO_BCM56260_A0fmt_fields, 4584 /* bits */ 36, 4585 /* flags */ 0, 4586 }, 4587 #endif /* chips */ 4588 4589 #if defined(BCM_56260_B0) 4590 { /* SOC_FORMAT_INT_CFG_TO_ENQ_REG_INFO_BCM56260_B0fmt */ 4591 /* format CFG_TO_ENQ_REG_INFOfmt */ 4592 /* nFields */ 1, 4593 /* *fields */ soc_CFG_TO_ENQ_REG_INFO_BCM56260_A0fmt_fields, 4594 /* bits */ 36, 4595 /* flags */ 0, 4596 }, 4597 #endif /* chips */ 4598 4599 #if defined(BCM_56270_A0) 4600 { /* SOC_FORMAT_INT_CFG_TO_ENQ_REG_INFO_BCM56270_A0fmt */ 4601 /* format CFG_TO_ENQ_REG_INFOfmt */ 4602 /* nFields */ 1, 4603 /* *fields */ soc_CFG_TO_ENQ_REG_INFO_BCM56260_A0fmt_fields, 4604 /* bits */ 36, 4605 /* flags */ 0, 4606 }, 4607 #endif /* chips */ 4608 4609 #if defined(BCM_56450_A0) 4610 { /* SOC_FORMAT_INT_CFG_TO_ENQ_REG_INFO_BCM56450_A0fmt */ 4611 /* format CFG_TO_ENQ_REG_INFOfmt */ 4612 /* nFields */ 1, 4613 /* *fields */ soc_CFG_TO_ENQ_REG_INFO_BCM56450_A0fmt_fields, 4614 /* bits */ 36, 4615 /* flags */ 0, 4616 }, 4617 #endif /* chips */ 4618 4619 #if defined(BCM_56450_B0) 4620 { /* SOC_FORMAT_INT_CFG_TO_ENQ_REG_INFO_BCM56450_B0fmt */ 4621 /* format CFG_TO_ENQ_REG_INFOfmt */ 4622 /* nFields */ 1, 4623 /* *fields */ soc_CFG_TO_ENQ_REG_INFO_BCM56450_A0fmt_fields, 4624 /* bits */ 36, 4625 /* flags */ 0, 4626 }, 4627 #endif /* chips */ 4628 4629 #if defined(BCM_56450_B1) 4630 { /* SOC_FORMAT_INT_CFG_TO_ENQ_REG_INFO_BCM56450_B1fmt */ 4631 /* format CFG_TO_ENQ_REG_INFOfmt */ 4632 /* nFields */ 1, 4633 /* *fields */ soc_CFG_TO_ENQ_REG_INFO_BCM56450_A0fmt_fields, 4634 /* bits */ 36, 4635 /* flags */ 0, 4636 }, 4637 #endif /* chips */ 4638 4639 #if defined(BCM_56624_A0) || defined(BCM_56680_A0) || \ 4640 defined(BCM_56680_B0) 4641 { /* SOC_FORMAT_INT_CHIP_CONFIG_OTPfmt */ 4642 /* format CHIP_CONFIG_OTPfmt */ 4643 /* nFields */ 39, 4644 /* *fields */ soc_CHIP_CONFIG_OTPfmt_fields, 4645 /* bits */ 126, 4646 /* flags */ 0, 4647 }, 4648 #endif /* chips */ 4649 4650 #if defined(BCM_53314_A0) 4651 { /* SOC_FORMAT_INT_CHIP_CONFIG_OTP_BCM53314_A0fmt */ 4652 /* format CHIP_CONFIG_OTPfmt */ 4653 /* nFields */ 32, 4654 /* *fields */ soc_CHIP_CONFIG_OTP_BCM53314_A0fmt_fields, 4655 /* bits */ 126, 4656 /* flags */ 0, 4657 }, 4658 #endif /* chips */ 4659 4660 #if defined(BCM_53324_A0) 4661 { /* SOC_FORMAT_INT_CHIP_CONFIG_OTP_BCM53324_A0fmt */ 4662 /* format CHIP_CONFIG_OTPfmt */ 4663 /* nFields */ 32, 4664 /* *fields */ soc_CHIP_CONFIG_OTP_BCM53314_A0fmt_fields, 4665 /* bits */ 126, 4666 /* flags */ 0, 4667 }, 4668 #endif /* chips */ 4669 4670 #if defined(BCM_53400_A0) 4671 { /* SOC_FORMAT_INT_CHIP_CONFIG_OTP_BCM53400_A0fmt */ 4672 /* format CHIP_CONFIG_OTPfmt */ 4673 /* nFields */ 68, 4674 /* *fields */ soc_CHIP_CONFIG_OTP_BCM53400_A0fmt_fields, 4675 /* bits */ 512, 4676 /* flags */ 0, 4677 }, 4678 #endif /* chips */ 4679 4680 #if defined(BCM_53540_A0) 4681 { /* SOC_FORMAT_INT_CHIP_CONFIG_OTP_BCM53540_A0fmt */ 4682 /* format CHIP_CONFIG_OTPfmt */ 4683 /* nFields */ 77, 4684 /* *fields */ soc_CHIP_CONFIG_OTP_BCM53540_A0fmt_fields, 4685 /* bits */ 512, 4686 /* flags */ 0, 4687 }, 4688 #endif /* chips */ 4689 4690 #if defined(BCM_53570_A0) 4691 { /* SOC_FORMAT_INT_CHIP_CONFIG_OTP_BCM53570_A0fmt */ 4692 /* format CHIP_CONFIG_OTPfmt */ 4693 /* nFields */ 91, 4694 /* *fields */ soc_CHIP_CONFIG_OTP_BCM53570_A0fmt_fields, 4695 /* bits */ 512, 4696 /* flags */ 0, 4697 }, 4698 #endif /* chips */ 4699 4700 #if defined(BCM_53570_B0) 4701 { /* SOC_FORMAT_INT_CHIP_CONFIG_OTP_BCM53570_B0fmt */ 4702 /* format CHIP_CONFIG_OTPfmt */ 4703 /* nFields */ 92, 4704 /* *fields */ soc_CHIP_CONFIG_OTP_BCM53570_B0fmt_fields, 4705 /* bits */ 512, 4706 /* flags */ 0, 4707 }, 4708 #endif /* chips */ 4709 4710 #if defined(BCM_56142_A0) 4711 { /* SOC_FORMAT_INT_CHIP_CONFIG_OTP_BCM56142_A0fmt */ 4712 /* format CHIP_CONFIG_OTPfmt */ 4713 /* nFields */ 19, 4714 /* *fields */ soc_CHIP_CONFIG_OTP_BCM56142_A0fmt_fields, 4715 /* bits */ 254, 4716 /* flags */ 0, 4717 }, 4718 #endif /* chips */ 4719 4720 #if defined(BCM_56150_A0) 4721 { /* SOC_FORMAT_INT_CHIP_CONFIG_OTP_BCM56150_A0fmt */ 4722 /* format CHIP_CONFIG_OTPfmt */ 4723 /* nFields */ 74, 4724 /* *fields */ soc_CHIP_CONFIG_OTP_BCM56150_A0fmt_fields, 4725 /* bits */ 448, 4726 /* flags */ 0, 4727 }, 4728 #endif /* chips */ 4729 4730 #if defined(BCM_56160_A0) 4731 { /* SOC_FORMAT_INT_CHIP_CONFIG_OTP_BCM56160_A0fmt */ 4732 /* format CHIP_CONFIG_OTPfmt */ 4733 /* nFields */ 89, 4734 /* *fields */ soc_CHIP_CONFIG_OTP_BCM56160_A0fmt_fields, 4735 /* bits */ 512, 4736 /* flags */ 0, 4737 }, 4738 #endif /* chips */ 4739 4740 #if defined(BCM_56260_A0) 4741 { /* SOC_FORMAT_INT_CHIP_CONFIG_OTP_BCM56260_A0fmt */ 4742 /* format CHIP_CONFIG_OTPfmt */ 4743 /* nFields */ 73, 4744 /* *fields */ soc_CHIP_CONFIG_OTP_BCM56260_A0fmt_fields, 4745 /* bits */ 448, 4746 /* flags */ 0, 4747 }, 4748 #endif /* chips */ 4749 4750 #if defined(BCM_56260_B0) 4751 { /* SOC_FORMAT_INT_CHIP_CONFIG_OTP_BCM56260_B0fmt */ 4752 /* format CHIP_CONFIG_OTPfmt */ 4753 /* nFields */ 73, 4754 /* *fields */ soc_CHIP_CONFIG_OTP_BCM56260_A0fmt_fields, 4755 /* bits */ 448, 4756 /* flags */ 0, 4757 }, 4758 #endif /* chips */ 4759 4760 #if defined(BCM_56270_A0) 4761 { /* SOC_FORMAT_INT_CHIP_CONFIG_OTP_BCM56270_A0fmt */ 4762 /* format CHIP_CONFIG_OTPfmt */ 4763 /* nFields */ 72, 4764 /* *fields */ soc_CHIP_CONFIG_OTP_BCM56270_A0fmt_fields, 4765 /* bits */ 448, 4766 /* flags */ 0, 4767 }, 4768 #endif /* chips */ 4769 4770 #if defined(BCM_56334_A0) 4771 { /* SOC_FORMAT_INT_CHIP_CONFIG_OTP_BCM56334_A0fmt */ 4772 /* format CHIP_CONFIG_OTPfmt */ 4773 /* nFields */ 21, 4774 /* *fields */ soc_CHIP_CONFIG_OTP_BCM56334_A0fmt_fields, 4775 /* bits */ 254, 4776 /* flags */ 0, 4777 }, 4778 #endif /* chips */ 4779 4780 #if defined(BCM_56334_B0) 4781 { /* SOC_FORMAT_INT_CHIP_CONFIG_OTP_BCM56334_B0fmt */ 4782 /* format CHIP_CONFIG_OTPfmt */ 4783 /* nFields */ 21, 4784 /* *fields */ soc_CHIP_CONFIG_OTP_BCM56334_A0fmt_fields, 4785 /* bits */ 254, 4786 /* flags */ 0, 4787 }, 4788 #endif /* chips */ 4789 4790 #if defined(BCM_56340_A0) 4791 { /* SOC_FORMAT_INT_CHIP_CONFIG_OTP_BCM56340_A0fmt */ 4792 /* format CHIP_CONFIG_OTPfmt */ 4793 /* nFields */ 65, 4794 /* *fields */ soc_CHIP_CONFIG_OTP_BCM56340_A0fmt_fields, 4795 /* bits */ 448, 4796 /* flags */ 0, 4797 }, 4798 #endif /* chips */ 4799 4800 #if defined(BCM_56370_A0) 4801 { /* SOC_FORMAT_INT_CHIP_CONFIG_OTP_BCM56370_A0fmt */ 4802 /* format CHIP_CONFIG_OTPfmt */ 4803 /* nFields */ 84, 4804 /* *fields */ soc_CHIP_CONFIG_OTP_BCM56370_A0fmt_fields, 4805 /* bits */ 896, 4806 /* flags */ 0, 4807 }, 4808 #endif /* chips */ 4809 4810 #if defined(BCM_56440_A0) 4811 { /* SOC_FORMAT_INT_CHIP_CONFIG_OTP_BCM56440_A0fmt */ 4812 /* format CHIP_CONFIG_OTPfmt */ 4813 /* nFields */ 53, 4814 /* *fields */ soc_CHIP_CONFIG_OTP_BCM56440_A0fmt_fields, 4815 /* bits */ 448, 4816 /* flags */ 0, 4817 }, 4818 #endif /* chips */ 4819 4820 #if defined(BCM_56440_B0) 4821 { /* SOC_FORMAT_INT_CHIP_CONFIG_OTP_BCM56440_B0fmt */ 4822 /* format CHIP_CONFIG_OTPfmt */ 4823 /* nFields */ 53, 4824 /* *fields */ soc_CHIP_CONFIG_OTP_BCM56440_A0fmt_fields, 4825 /* bits */ 448, 4826 /* flags */ 0, 4827 }, 4828 #endif /* chips */ 4829 4830 #if defined(BCM_56450_A0) 4831 { /* SOC_FORMAT_INT_CHIP_CONFIG_OTP_BCM56450_A0fmt */ 4832 /* format CHIP_CONFIG_OTPfmt */ 4833 /* nFields */ 74, 4834 /* *fields */ soc_CHIP_CONFIG_OTP_BCM56450_A0fmt_fields, 4835 /* bits */ 448, 4836 /* flags */ 0, 4837 }, 4838 #endif /* chips */ 4839 4840 #if defined(BCM_56450_B0) 4841 { /* SOC_FORMAT_INT_CHIP_CONFIG_OTP_BCM56450_B0fmt */ 4842 /* format CHIP_CONFIG_OTPfmt */ 4843 /* nFields */ 76, 4844 /* *fields */ soc_CHIP_CONFIG_OTP_BCM56450_B0fmt_fields, 4845 /* bits */ 448, 4846 /* flags */ 0, 4847 }, 4848 #endif /* chips */ 4849 4850 #if defined(BCM_56450_B1) 4851 { /* SOC_FORMAT_INT_CHIP_CONFIG_OTP_BCM56450_B1fmt */ 4852 /* format CHIP_CONFIG_OTPfmt */ 4853 /* nFields */ 76, 4854 /* *fields */ soc_CHIP_CONFIG_OTP_BCM56450_B0fmt_fields, 4855 /* bits */ 448, 4856 /* flags */ 0, 4857 }, 4858 #endif /* chips */ 4859 4860 #if defined(BCM_56524_A0) 4861 { /* SOC_FORMAT_INT_CHIP_CONFIG_OTP_BCM56524_A0fmt */ 4862 /* format CHIP_CONFIG_OTPfmt */ 4863 /* nFields */ 61, 4864 /* *fields */ soc_CHIP_CONFIG_OTP_BCM56634_A0fmt_fields, 4865 /* bits */ 254, 4866 /* flags */ 0, 4867 }, 4868 #endif /* chips */ 4869 4870 #if defined(BCM_56524_B0) 4871 { /* SOC_FORMAT_INT_CHIP_CONFIG_OTP_BCM56524_B0fmt */ 4872 /* format CHIP_CONFIG_OTPfmt */ 4873 /* nFields */ 67, 4874 /* *fields */ soc_CHIP_CONFIG_OTP_BCM56634_B0fmt_fields, 4875 /* bits */ 254, 4876 /* flags */ 0, 4877 }, 4878 #endif /* chips */ 4879 4880 #if defined(BCM_56560_A0) 4881 { /* SOC_FORMAT_INT_CHIP_CONFIG_OTP_BCM56560_A0fmt */ 4882 /* format CHIP_CONFIG_OTPfmt */ 4883 /* nFields */ 101, 4884 /* *fields */ soc_CHIP_CONFIG_OTP_BCM56560_A0fmt_fields, 4885 /* bits */ 448, 4886 /* flags */ 0, 4887 }, 4888 #endif /* chips */ 4889 4890 #if defined(BCM_56560_B0) 4891 { /* SOC_FORMAT_INT_CHIP_CONFIG_OTP_BCM56560_B0fmt */ 4892 /* format CHIP_CONFIG_OTPfmt */ 4893 /* nFields */ 101, 4894 /* *fields */ soc_CHIP_CONFIG_OTP_BCM56560_A0fmt_fields, 4895 /* bits */ 448, 4896 /* flags */ 0, 4897 }, 4898 #endif /* chips */ 4899 4900 #if defined(BCM_56624_B0) 4901 { /* SOC_FORMAT_INT_CHIP_CONFIG_OTP_BCM56624_B0fmt */ 4902 /* format CHIP_CONFIG_OTPfmt */ 4903 /* nFields */ 40, 4904 /* *fields */ soc_CHIP_CONFIG_OTP_BCM56624_B0fmt_fields, 4905 /* bits */ 126, 4906 /* flags */ 0, 4907 }, 4908 #endif /* chips */ 4909 4910 #if defined(BCM_56634_A0) 4911 { /* SOC_FORMAT_INT_CHIP_CONFIG_OTP_BCM56634_A0fmt */ 4912 /* format CHIP_CONFIG_OTPfmt */ 4913 /* nFields */ 61, 4914 /* *fields */ soc_CHIP_CONFIG_OTP_BCM56634_A0fmt_fields, 4915 /* bits */ 254, 4916 /* flags */ 0, 4917 }, 4918 #endif /* chips */ 4919 4920 #if defined(BCM_56634_B0) 4921 { /* SOC_FORMAT_INT_CHIP_CONFIG_OTP_BCM56634_B0fmt */ 4922 /* format CHIP_CONFIG_OTPfmt */ 4923 /* nFields */ 67, 4924 /* *fields */ soc_CHIP_CONFIG_OTP_BCM56634_B0fmt_fields, 4925 /* bits */ 254, 4926 /* flags */ 0, 4927 }, 4928 #endif /* chips */ 4929 4930 #if defined(BCM_56640_A0) 4931 { /* SOC_FORMAT_INT_CHIP_CONFIG_OTP_BCM56640_A0fmt */ 4932 /* format CHIP_CONFIG_OTPfmt */ 4933 /* nFields */ 94, 4934 /* *fields */ soc_CHIP_CONFIG_OTP_BCM56640_A0fmt_fields, 4935 /* bits */ 448, 4936 /* flags */ 0, 4937 }, 4938 #endif /* chips */ 4939 4940 #if defined(BCM_56670_A0) 4941 { /* SOC_FORMAT_INT_CHIP_CONFIG_OTP_BCM56670_A0fmt */ 4942 /* format CHIP_CONFIG_OTPfmt */ 4943 /* nFields */ 64, 4944 /* *fields */ soc_CHIP_CONFIG_OTP_BCM56670_A0fmt_fields, 4945 /* bits */ 448, 4946 /* flags */ 0, 4947 }, 4948 #endif /* chips */ 4949 4950 #if defined(BCM_56670_B0) 4951 { /* SOC_FORMAT_INT_CHIP_CONFIG_OTP_BCM56670_B0fmt */ 4952 /* format CHIP_CONFIG_OTPfmt */ 4953 /* nFields */ 64, 4954 /* *fields */ soc_CHIP_CONFIG_OTP_BCM56670_B0fmt_fields, 4955 /* bits */ 448, 4956 /* flags */ 0, 4957 }, 4958 #endif /* chips */ 4959 4960 #if defined(BCM_56685_A0) 4961 { /* SOC_FORMAT_INT_CHIP_CONFIG_OTP_BCM56685_A0fmt */ 4962 /* format CHIP_CONFIG_OTPfmt */ 4963 /* nFields */ 61, 4964 /* *fields */ soc_CHIP_CONFIG_OTP_BCM56634_A0fmt_fields, 4965 /* bits */ 254, 4966 /* flags */ 0, 4967 }, 4968 #endif /* chips */ 4969 4970 #if defined(BCM_56685_B0) 4971 { /* SOC_FORMAT_INT_CHIP_CONFIG_OTP_BCM56685_B0fmt */ 4972 /* format CHIP_CONFIG_OTPfmt */ 4973 /* nFields */ 67, 4974 /* *fields */ soc_CHIP_CONFIG_OTP_BCM56634_B0fmt_fields, 4975 /* bits */ 254, 4976 /* flags */ 0, 4977 }, 4978 #endif /* chips */ 4979 4980 #if defined(BCM_56725_A0) 4981 { /* SOC_FORMAT_INT_CHIP_CONFIG_OTP_BCM56725_A0fmt */ 4982 /* format CHIP_CONFIG_OTPfmt */ 4983 /* nFields */ 21, 4984 /* *fields */ soc_CHIP_CONFIG_OTP_BCM56820_A0fmt_fields, 4985 /* bits */ 126, 4986 /* flags */ 0, 4987 }, 4988 #endif /* chips */ 4989 4990 #if defined(BCM_56770_A0) 4991 { /* SOC_FORMAT_INT_CHIP_CONFIG_OTP_BCM56770_A0fmt */ 4992 /* format CHIP_CONFIG_OTPfmt */ 4993 /* nFields */ 95, 4994 /* *fields */ soc_CHIP_CONFIG_OTP_BCM56770_A0fmt_fields, 4995 /* bits */ 896, 4996 /* flags */ 0, 4997 }, 4998 #endif /* chips */ 4999 5000 #if defined(BCM_56820_A0) 5001 { /* SOC_FORMAT_INT_CHIP_CONFIG_OTP_BCM56820_A0fmt */ 5002 /* format CHIP_CONFIG_OTPfmt */ 5003 /* nFields */ 21, 5004 /* *fields */ soc_CHIP_CONFIG_OTP_BCM56820_A0fmt_fields, 5005 /* bits */ 126, 5006 /* flags */ 0, 5007 }, 5008 #endif /* chips */ 5009 5010 #if defined(BCM_56840_A0) 5011 { /* SOC_FORMAT_INT_CHIP_CONFIG_OTP_BCM56840_A0fmt */ 5012 /* format CHIP_CONFIG_OTPfmt */ 5013 /* nFields */ 48, 5014 /* *fields */ soc_CHIP_CONFIG_OTP_BCM56840_A0fmt_fields, 5015 /* bits */ 448, 5016 /* flags */ 0, 5017 }, 5018 #endif /* chips */ 5019 5020 #if defined(BCM_56840_B0) 5021 { /* SOC_FORMAT_INT_CHIP_CONFIG_OTP_BCM56840_B0fmt */ 5022 /* format CHIP_CONFIG_OTPfmt */ 5023 /* nFields */ 49, 5024 /* *fields */ soc_CHIP_CONFIG_OTP_BCM56840_B0fmt_fields, 5025 /* bits */ 448, 5026 /* flags */ 0, 5027 }, 5028 #endif /* chips */ 5029 5030 #if defined(BCM_56850_A0) 5031 { /* SOC_FORMAT_INT_CHIP_CONFIG_OTP_BCM56850_A0fmt */ 5032 /* format CHIP_CONFIG_OTPfmt */ 5033 /* nFields */ 82, 5034 /* *fields */ soc_CHIP_CONFIG_OTP_BCM56850_A0fmt_fields, 5035 /* bits */ 448, 5036 /* flags */ 0, 5037 }, 5038 #endif /* chips */ 5039 5040 #if defined(BCM_56860_A0) 5041 { /* SOC_FORMAT_INT_CHIP_CONFIG_OTP_BCM56860_A0fmt */ 5042 /* format CHIP_CONFIG_OTPfmt */ 5043 /* nFields */ 96, 5044 /* *fields */ soc_CHIP_CONFIG_OTP_BCM56860_A0fmt_fields, 5045 /* bits */ 448, 5046 /* flags */ 0, 5047 }, 5048 #endif /* chips */ 5049 5050 #if defined(BCM_56870_A0) 5051 { /* SOC_FORMAT_INT_CHIP_CONFIG_OTP_BCM56870_A0fmt */ 5052 /* format CHIP_CONFIG_OTPfmt */ 5053 /* nFields */ 95, 5054 /* *fields */ soc_CHIP_CONFIG_OTP_BCM56870_A0fmt_fields, 5055 /* bits */ 896, 5056 /* flags */ 0, 5057 }, 5058 #endif /* chips */ 5059 5060 #if defined(BCM_56960_A0) 5061 { /* SOC_FORMAT_INT_CHIP_CONFIG_OTP_BCM56960_A0fmt */ 5062 /* format CHIP_CONFIG_OTPfmt */ 5063 /* nFields */ 72, 5064 /* *fields */ soc_CHIP_CONFIG_OTP_BCM56960_A0fmt_fields, 5065 /* bits */ 448, 5066 /* flags */ 0, 5067 }, 5068 #endif /* chips */ 5069 5070 #if defined(BCM_56965_A0) 5071 { /* SOC_FORMAT_INT_CHIP_CONFIG_OTP_BCM56965_A0fmt */ 5072 /* format CHIP_CONFIG_OTPfmt */ 5073 /* nFields */ 72, 5074 /* *fields */ soc_CHIP_CONFIG_OTP_BCM56965_A0fmt_fields, 5075 /* bits */ 448, 5076 /* flags */ 0, 5077 }, 5078 #endif /* chips */ 5079 5080 #if defined(BCM_56970_A0) 5081 { /* SOC_FORMAT_INT_CHIP_CONFIG_OTP_BCM56970_A0fmt */ 5082 /* format CHIP_CONFIG_OTPfmt */ 5083 /* nFields */ 77, 5084 /* *fields */ soc_CHIP_CONFIG_OTP_BCM56970_A0fmt_fields, 5085 /* bits */ 896, 5086 /* flags */ 0, 5087 }, 5088 #endif /* chips */ 5089 5090 #if defined(BCM_56980_A0) 5091 { /* SOC_FORMAT_INT_CHIP_CONFIG_OTP_BCM56980_A0fmt */ 5092 /* format CHIP_CONFIG_OTPfmt */ 5093 /* nFields */ 64, 5094 /* *fields */ soc_CHIP_CONFIG_OTP_BCM56980_A0fmt_fields, 5095 /* bits */ 896, 5096 /* flags */ 0, 5097 }, 5098 #endif /* chips */ 5099 5100 #if defined(BCM_56980_B0) 5101 { /* SOC_FORMAT_INT_CHIP_CONFIG_OTP_BCM56980_B0fmt */ 5102 /* format CHIP_CONFIG_OTPfmt */ 5103 /* nFields */ 64, 5104 /* *fields */ soc_CHIP_CONFIG_OTP_BCM56980_A0fmt_fields, 5105 /* bits */ 896, 5106 /* flags */ 0, 5107 }, 5108 #endif /* chips */ 5109 5110 #if defined(BCM_88732_A0) 5111 { /* SOC_FORMAT_INT_CHIP_CONFIG_OTP_BCM88732_A0fmt */ 5112 /* format CHIP_CONFIG_OTPfmt */ 5113 /* nFields */ 26, 5114 /* *fields */ soc_CHIP_CONFIG_OTP_BCM88732_A0fmt_fields, 5115 /* bits */ 448, 5116 /* flags */ 0, 5117 }, 5118 #endif /* chips */ 5119 5120 #if defined(BCM_56820_A0) 5121 { /* SOC_FORMAT_INT_CHIP_FUNCTIONAL_INTRfmt */ 5122 /* format CHIP_FUNCTIONAL_INTRfmt */ 5123 /* nFields */ 3, 5124 /* *fields */ soc_CHIP_FUNCTIONAL_INTRfmt_fields, 5125 /* bits */ 8, 5126 /* flags */ 0, 5127 }, 5128 #endif /* chips */ 5129 5130 #if defined(BCM_56725_A0) 5131 { /* SOC_FORMAT_INT_CHIP_FUNCTIONAL_INTR_BCM56725_A0fmt */ 5132 /* format CHIP_FUNCTIONAL_INTRfmt */ 5133 /* nFields */ 3, 5134 /* *fields */ soc_CHIP_FUNCTIONAL_INTRfmt_fields, 5135 /* bits */ 8, 5136 /* flags */ 0, 5137 }, 5138 #endif /* chips */ 5139 5140 #if defined(BCM_88732_A0) 5141 { /* SOC_FORMAT_INT_CHIP_FUNCTIONAL_INTR_BCM88732_A0fmt */ 5142 /* format CHIP_FUNCTIONAL_INTRfmt */ 5143 /* nFields */ 1, 5144 /* *fields */ soc_CHIP_FUNCTIONAL_INTR_BCM88732_A0fmt_fields, 5145 /* bits */ 8, 5146 /* flags */ 0, 5147 }, 5148 #endif /* chips */ 5149 5150 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 5151 { /* SOC_FORMAT_INT_CHIP_LP_INTRfmt */ 5152 /* format CHIP_LP_INTRfmt */ 5153 /* nFields */ 113, 5154 /* *fields */ soc_CHIP_LP_INTRfmt_fields, 5155 /* bits */ 128, 5156 /* flags */ 0, 5157 }, 5158 #endif /* chips */ 5159 5160 #if defined(BCM_56820_A0) 5161 { /* SOC_FORMAT_INT_CHIP_PARITY_INTRfmt */ 5162 /* format CHIP_PARITY_INTRfmt */ 5163 /* nFields */ 13, 5164 /* *fields */ soc_CHIP_PARITY_INTRfmt_fields, 5165 /* bits */ 32, 5166 /* flags */ 0, 5167 }, 5168 #endif /* chips */ 5169 5170 #if defined(BCM_56725_A0) 5171 { /* SOC_FORMAT_INT_CHIP_PARITY_INTR_BCM56725_A0fmt */ 5172 /* format CHIP_PARITY_INTRfmt */ 5173 /* nFields */ 13, 5174 /* *fields */ soc_CHIP_PARITY_INTRfmt_fields, 5175 /* bits */ 32, 5176 /* flags */ 0, 5177 }, 5178 #endif /* chips */ 5179 5180 #if defined(BCM_88732_A0) 5181 { /* SOC_FORMAT_INT_CHIP_PARITY_INTR_BCM88732_A0fmt */ 5182 /* format CHIP_PARITY_INTRfmt */ 5183 /* nFields */ 2, 5184 /* *fields */ soc_CHIP_PARITY_INTR_BCM88732_A0fmt_fields, 5185 /* bits */ 32, 5186 /* flags */ 0, 5187 }, 5188 #endif /* chips */ 5189 5190 #if defined(BCM_56150_A0) || defined(BCM_56340_A0) || \ 5191 defined(BCM_56450_A0) || defined(BCM_56450_B0) || \ 5192 defined(BCM_56450_B1) 5193 { /* SOC_FORMAT_INT_CMICD_TO_GIC_INTERUPTSfmt */ 5194 /* format CMICD_TO_GIC_INTERUPTSfmt */ 5195 /* nFields */ 55, 5196 /* *fields */ soc_CMICD_TO_GIC_INTERUPTSfmt_fields, 5197 /* bits */ 64, 5198 /* flags */ 0, 5199 }, 5200 #endif /* chips */ 5201 5202 #if defined(BCM_53400_A0) 5203 { /* SOC_FORMAT_INT_CMICD_TO_GIC_INTERUPTS_BCM53400_A0fmt */ 5204 /* format CMICD_TO_GIC_INTERUPTSfmt */ 5205 /* nFields */ 55, 5206 /* *fields */ soc_CMICD_TO_GIC_INTERUPTS_BCM53400_A0fmt_fields, 5207 /* bits */ 64, 5208 /* flags */ 0, 5209 }, 5210 #endif /* chips */ 5211 5212 #if defined(BCM_53540_A0) 5213 { /* SOC_FORMAT_INT_CMICD_TO_GIC_INTERUPTS_BCM53540_A0fmt */ 5214 /* format CMICD_TO_GIC_INTERUPTSfmt */ 5215 /* nFields */ 55, 5216 /* *fields */ soc_CMICD_TO_GIC_INTERUPTS_BCM53400_A0fmt_fields, 5217 /* bits */ 64, 5218 /* flags */ 0, 5219 }, 5220 #endif /* chips */ 5221 5222 #if defined(BCM_53570_A0) 5223 { /* SOC_FORMAT_INT_CMICD_TO_GIC_INTERUPTS_BCM53570_A0fmt */ 5224 /* format CMICD_TO_GIC_INTERUPTSfmt */ 5225 /* nFields */ 55, 5226 /* *fields */ soc_CMICD_TO_GIC_INTERUPTS_BCM53400_A0fmt_fields, 5227 /* bits */ 64, 5228 /* flags */ 0, 5229 }, 5230 #endif /* chips */ 5231 5232 #if defined(BCM_53570_B0) 5233 { /* SOC_FORMAT_INT_CMICD_TO_GIC_INTERUPTS_BCM53570_B0fmt */ 5234 /* format CMICD_TO_GIC_INTERUPTSfmt */ 5235 /* nFields */ 55, 5236 /* *fields */ soc_CMICD_TO_GIC_INTERUPTS_BCM53400_A0fmt_fields, 5237 /* bits */ 64, 5238 /* flags */ 0, 5239 }, 5240 #endif /* chips */ 5241 5242 #if defined(BCM_56160_A0) 5243 { /* SOC_FORMAT_INT_CMICD_TO_GIC_INTERUPTS_BCM56160_A0fmt */ 5244 /* format CMICD_TO_GIC_INTERUPTSfmt */ 5245 /* nFields */ 55, 5246 /* *fields */ soc_CMICD_TO_GIC_INTERUPTS_BCM53400_A0fmt_fields, 5247 /* bits */ 64, 5248 /* flags */ 0, 5249 }, 5250 #endif /* chips */ 5251 5252 #if defined(BCM_56260_A0) 5253 { /* SOC_FORMAT_INT_CMICD_TO_GIC_INTERUPTS_BCM56260_A0fmt */ 5254 /* format CMICD_TO_GIC_INTERUPTSfmt */ 5255 /* nFields */ 55, 5256 /* *fields */ soc_CMICD_TO_GIC_INTERUPTS_BCM53400_A0fmt_fields, 5257 /* bits */ 64, 5258 /* flags */ 0, 5259 }, 5260 #endif /* chips */ 5261 5262 #if defined(BCM_56260_B0) 5263 { /* SOC_FORMAT_INT_CMICD_TO_GIC_INTERUPTS_BCM56260_B0fmt */ 5264 /* format CMICD_TO_GIC_INTERUPTSfmt */ 5265 /* nFields */ 55, 5266 /* *fields */ soc_CMICD_TO_GIC_INTERUPTS_BCM53400_A0fmt_fields, 5267 /* bits */ 64, 5268 /* flags */ 0, 5269 }, 5270 #endif /* chips */ 5271 5272 #if defined(BCM_56270_A0) 5273 { /* SOC_FORMAT_INT_CMICD_TO_GIC_INTERUPTS_BCM56270_A0fmt */ 5274 /* format CMICD_TO_GIC_INTERUPTSfmt */ 5275 /* nFields */ 55, 5276 /* *fields */ soc_CMICD_TO_GIC_INTERUPTS_BCM53400_A0fmt_fields, 5277 /* bits */ 64, 5278 /* flags */ 0, 5279 }, 5280 #endif /* chips */ 5281 5282 #if defined(BCM_56560_A0) 5283 { /* SOC_FORMAT_INT_CMICD_TO_GIC_INTERUPTS_BCM56560_A0fmt */ 5284 /* format CMICD_TO_GIC_INTERUPTSfmt */ 5285 /* nFields */ 55, 5286 /* *fields */ soc_CMICD_TO_GIC_INTERUPTS_BCM53400_A0fmt_fields, 5287 /* bits */ 64, 5288 /* flags */ 0, 5289 }, 5290 #endif /* chips */ 5291 5292 #if defined(BCM_56560_B0) 5293 { /* SOC_FORMAT_INT_CMICD_TO_GIC_INTERUPTS_BCM56560_B0fmt */ 5294 /* format CMICD_TO_GIC_INTERUPTSfmt */ 5295 /* nFields */ 55, 5296 /* *fields */ soc_CMICD_TO_GIC_INTERUPTS_BCM53400_A0fmt_fields, 5297 /* bits */ 64, 5298 /* flags */ 0, 5299 }, 5300 #endif /* chips */ 5301 5302 #if defined(BCM_56670_A0) 5303 { /* SOC_FORMAT_INT_CMICD_TO_GIC_INTERUPTS_BCM56670_A0fmt */ 5304 /* format CMICD_TO_GIC_INTERUPTSfmt */ 5305 /* nFields */ 55, 5306 /* *fields */ soc_CMICD_TO_GIC_INTERUPTS_BCM53400_A0fmt_fields, 5307 /* bits */ 64, 5308 /* flags */ 0, 5309 }, 5310 #endif /* chips */ 5311 5312 #if defined(BCM_56670_B0) 5313 { /* SOC_FORMAT_INT_CMICD_TO_GIC_INTERUPTS_BCM56670_B0fmt */ 5314 /* format CMICD_TO_GIC_INTERUPTSfmt */ 5315 /* nFields */ 55, 5316 /* *fields */ soc_CMICD_TO_GIC_INTERUPTS_BCM53400_A0fmt_fields, 5317 /* bits */ 64, 5318 /* flags */ 0, 5319 }, 5320 #endif /* chips */ 5321 5322 #if defined(BCM_56960_A0) 5323 { /* SOC_FORMAT_INT_CMICD_TO_GIC_INTERUPTS_BCM56960_A0fmt */ 5324 /* format CMICD_TO_GIC_INTERUPTSfmt */ 5325 /* nFields */ 55, 5326 /* *fields */ soc_CMICD_TO_GIC_INTERUPTS_BCM53400_A0fmt_fields, 5327 /* bits */ 64, 5328 /* flags */ 0, 5329 }, 5330 #endif /* chips */ 5331 5332 #if defined(BCM_56965_A0) 5333 { /* SOC_FORMAT_INT_CMICD_TO_GIC_INTERUPTS_BCM56965_A0fmt */ 5334 /* format CMICD_TO_GIC_INTERUPTSfmt */ 5335 /* nFields */ 55, 5336 /* *fields */ soc_CMICD_TO_GIC_INTERUPTS_BCM53400_A0fmt_fields, 5337 /* bits */ 64, 5338 /* flags */ 0, 5339 }, 5340 #endif /* chips */ 5341 5342 #if defined(BCM_56970_A0) 5343 { /* SOC_FORMAT_INT_CMICD_TO_GIC_INTERUPTS_BCM56970_A0fmt */ 5344 /* format CMICD_TO_GIC_INTERUPTSfmt */ 5345 /* nFields */ 55, 5346 /* *fields */ soc_CMICD_TO_GIC_INTERUPTS_BCM53400_A0fmt_fields, 5347 /* bits */ 64, 5348 /* flags */ 0, 5349 }, 5350 #endif /* chips */ 5351 5352 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) 5353 { /* SOC_FORMAT_INT_CMIC_CMC_IRQ_STAT3fmt */ 5354 /* format CMIC_CMC_IRQ_STAT3fmt */ 5355 /* nFields */ 27, 5356 /* *fields */ soc_CMIC_CMC_IRQ_STAT3fmt_fields, 5357 /* bits */ 32, 5358 /* flags */ 0, 5359 }, 5360 #endif /* chips */ 5361 5362 #if defined(BCM_56870_A0) || defined(BCM_56960_A0) || \ 5363 defined(BCM_56965_A0) || defined(BCM_56970_A0) 5364 { /* SOC_FORMAT_INT_CMIC_CMC_IRQ_STAT4fmt */ 5365 /* format CMIC_CMC_IRQ_STAT4fmt */ 5366 /* nFields */ 32, 5367 /* *fields */ soc_CMIC_CMC_IRQ_STAT4fmt_fields, 5368 /* bits */ 32, 5369 /* flags */ 0, 5370 }, 5371 #endif /* chips */ 5372 5373 #if defined(BCM_56870_A0) || defined(BCM_56960_A0) || \ 5374 defined(BCM_56965_A0) 5375 { /* SOC_FORMAT_INT_CMIC_CMC_IRQ_STAT5fmt */ 5376 /* format CMIC_CMC_IRQ_STAT5fmt */ 5377 /* nFields */ 2, 5378 /* *fields */ soc_CMIC_CMC_IRQ_STAT5fmt_fields, 5379 /* bits */ 32, 5380 /* flags */ 0, 5381 }, 5382 #endif /* chips */ 5383 5384 #if defined(BCM_56370_A0) || defined(BCM_56560_A0) || \ 5385 defined(BCM_56560_B0) || defined(BCM_56670_A0) || \ 5386 defined(BCM_56670_B0) || defined(BCM_56770_A0) || \ 5387 defined(BCM_56870_A0) || defined(BCM_56960_A0) || \ 5388 defined(BCM_56965_A0) 5389 { /* SOC_FORMAT_INT_CMIC_CMC_IRQ_STAT6fmt */ 5390 /* format CMIC_CMC_IRQ_STAT6fmt */ 5391 /* nFields */ 1, 5392 /* *fields */ soc_CMIC_CMC_IRQ_STAT6fmt_fields, 5393 /* bits */ 32, 5394 /* flags */ 0, 5395 }, 5396 #endif /* chips */ 5397 5398 #if defined(BCM_56370_A0) 5399 { /* SOC_FORMAT_INT_CMIC_CMC_IRQ_STAT3_BCM56370_A0fmt */ 5400 /* format CMIC_CMC_IRQ_STAT3fmt */ 5401 /* nFields */ 22, 5402 /* *fields */ soc_CMIC_CMC_IRQ_STAT3_BCM56370_A0fmt_fields, 5403 /* bits */ 32, 5404 /* flags */ 0, 5405 }, 5406 #endif /* chips */ 5407 5408 #if defined(BCM_56560_A0) 5409 { /* SOC_FORMAT_INT_CMIC_CMC_IRQ_STAT3_BCM56560_A0fmt */ 5410 /* format CMIC_CMC_IRQ_STAT3fmt */ 5411 /* nFields */ 16, 5412 /* *fields */ soc_CMIC_CMC_IRQ_STAT3_BCM56560_A0fmt_fields, 5413 /* bits */ 32, 5414 /* flags */ 0, 5415 }, 5416 #endif /* chips */ 5417 5418 #if defined(BCM_56560_B0) 5419 { /* SOC_FORMAT_INT_CMIC_CMC_IRQ_STAT3_BCM56560_B0fmt */ 5420 /* format CMIC_CMC_IRQ_STAT3fmt */ 5421 /* nFields */ 16, 5422 /* *fields */ soc_CMIC_CMC_IRQ_STAT3_BCM56560_A0fmt_fields, 5423 /* bits */ 32, 5424 /* flags */ 0, 5425 }, 5426 #endif /* chips */ 5427 5428 #if defined(BCM_56670_A0) 5429 { /* SOC_FORMAT_INT_CMIC_CMC_IRQ_STAT3_BCM56670_A0fmt */ 5430 /* format CMIC_CMC_IRQ_STAT3fmt */ 5431 /* nFields */ 15, 5432 /* *fields */ soc_CMIC_CMC_IRQ_STAT3_BCM56670_A0fmt_fields, 5433 /* bits */ 32, 5434 /* flags */ 0, 5435 }, 5436 #endif /* chips */ 5437 5438 #if defined(BCM_56670_B0) 5439 { /* SOC_FORMAT_INT_CMIC_CMC_IRQ_STAT3_BCM56670_B0fmt */ 5440 /* format CMIC_CMC_IRQ_STAT3fmt */ 5441 /* nFields */ 15, 5442 /* *fields */ soc_CMIC_CMC_IRQ_STAT3_BCM56670_A0fmt_fields, 5443 /* bits */ 32, 5444 /* flags */ 0, 5445 }, 5446 #endif /* chips */ 5447 5448 #if defined(BCM_56770_A0) 5449 { /* SOC_FORMAT_INT_CMIC_CMC_IRQ_STAT3_BCM56770_A0fmt */ 5450 /* format CMIC_CMC_IRQ_STAT3fmt */ 5451 /* nFields */ 21, 5452 /* *fields */ soc_CMIC_CMC_IRQ_STAT3_BCM56770_A0fmt_fields, 5453 /* bits */ 32, 5454 /* flags */ 0, 5455 }, 5456 #endif /* chips */ 5457 5458 #if defined(BCM_56870_A0) 5459 { /* SOC_FORMAT_INT_CMIC_CMC_IRQ_STAT3_BCM56870_A0fmt */ 5460 /* format CMIC_CMC_IRQ_STAT3fmt */ 5461 /* nFields */ 25, 5462 /* *fields */ soc_CMIC_CMC_IRQ_STAT3_BCM56870_A0fmt_fields, 5463 /* bits */ 32, 5464 /* flags */ 0, 5465 }, 5466 #endif /* chips */ 5467 5468 #if defined(BCM_56970_A0) 5469 { /* SOC_FORMAT_INT_CMIC_CMC_IRQ_STAT3_BCM56970_A0fmt */ 5470 /* format CMIC_CMC_IRQ_STAT3fmt */ 5471 /* nFields */ 31, 5472 /* *fields */ soc_CMIC_CMC_IRQ_STAT3_BCM56970_A0fmt_fields, 5473 /* bits */ 32, 5474 /* flags */ 0, 5475 }, 5476 #endif /* chips */ 5477 5478 #if defined(BCM_56370_A0) 5479 { /* SOC_FORMAT_INT_CMIC_CMC_IRQ_STAT4_BCM56370_A0fmt */ 5480 /* format CMIC_CMC_IRQ_STAT4fmt */ 5481 /* nFields */ 12, 5482 /* *fields */ soc_CMIC_CMC_IRQ_STAT4_BCM56370_A0fmt_fields, 5483 /* bits */ 32, 5484 /* flags */ 0, 5485 }, 5486 #endif /* chips */ 5487 5488 #if defined(BCM_56560_A0) 5489 { /* SOC_FORMAT_INT_CMIC_CMC_IRQ_STAT4_BCM56560_A0fmt */ 5490 /* format CMIC_CMC_IRQ_STAT4fmt */ 5491 /* nFields */ 15, 5492 /* *fields */ soc_CMIC_CMC_IRQ_STAT4_BCM56560_A0fmt_fields, 5493 /* bits */ 32, 5494 /* flags */ 0, 5495 }, 5496 #endif /* chips */ 5497 5498 #if defined(BCM_56560_B0) 5499 { /* SOC_FORMAT_INT_CMIC_CMC_IRQ_STAT4_BCM56560_B0fmt */ 5500 /* format CMIC_CMC_IRQ_STAT4fmt */ 5501 /* nFields */ 15, 5502 /* *fields */ soc_CMIC_CMC_IRQ_STAT4_BCM56560_A0fmt_fields, 5503 /* bits */ 32, 5504 /* flags */ 0, 5505 }, 5506 #endif /* chips */ 5507 5508 #if defined(BCM_56670_A0) 5509 { /* SOC_FORMAT_INT_CMIC_CMC_IRQ_STAT4_BCM56670_A0fmt */ 5510 /* format CMIC_CMC_IRQ_STAT4fmt */ 5511 /* nFields */ 24, 5512 /* *fields */ soc_CMIC_CMC_IRQ_STAT4_BCM56670_A0fmt_fields, 5513 /* bits */ 32, 5514 /* flags */ 0, 5515 }, 5516 #endif /* chips */ 5517 5518 #if defined(BCM_56670_B0) 5519 { /* SOC_FORMAT_INT_CMIC_CMC_IRQ_STAT4_BCM56670_B0fmt */ 5520 /* format CMIC_CMC_IRQ_STAT4fmt */ 5521 /* nFields */ 24, 5522 /* *fields */ soc_CMIC_CMC_IRQ_STAT4_BCM56670_A0fmt_fields, 5523 /* bits */ 32, 5524 /* flags */ 0, 5525 }, 5526 #endif /* chips */ 5527 5528 #if defined(BCM_56770_A0) 5529 { /* SOC_FORMAT_INT_CMIC_CMC_IRQ_STAT4_BCM56770_A0fmt */ 5530 /* format CMIC_CMC_IRQ_STAT4fmt */ 5531 /* nFields */ 22, 5532 /* *fields */ soc_CMIC_CMC_IRQ_STAT4_BCM56770_A0fmt_fields, 5533 /* bits */ 32, 5534 /* flags */ 0, 5535 }, 5536 #endif /* chips */ 5537 5538 #if defined(BCM_56370_A0) 5539 { /* SOC_FORMAT_INT_CMIC_CMC_IRQ_STAT5_BCM56370_A0fmt */ 5540 /* format CMIC_CMC_IRQ_STAT5fmt */ 5541 /* nFields */ 1, 5542 /* *fields */ soc_CMIC_CMC_IRQ_STAT6fmt_fields, 5543 /* bits */ 32, 5544 /* flags */ 0, 5545 }, 5546 #endif /* chips */ 5547 5548 #if defined(BCM_56560_A0) 5549 { /* SOC_FORMAT_INT_CMIC_CMC_IRQ_STAT5_BCM56560_A0fmt */ 5550 /* format CMIC_CMC_IRQ_STAT5fmt */ 5551 /* nFields */ 1, 5552 /* *fields */ soc_CMIC_CMC_IRQ_STAT6fmt_fields, 5553 /* bits */ 32, 5554 /* flags */ 0, 5555 }, 5556 #endif /* chips */ 5557 5558 #if defined(BCM_56560_B0) 5559 { /* SOC_FORMAT_INT_CMIC_CMC_IRQ_STAT5_BCM56560_B0fmt */ 5560 /* format CMIC_CMC_IRQ_STAT5fmt */ 5561 /* nFields */ 1, 5562 /* *fields */ soc_CMIC_CMC_IRQ_STAT6fmt_fields, 5563 /* bits */ 32, 5564 /* flags */ 0, 5565 }, 5566 #endif /* chips */ 5567 5568 #if defined(BCM_56670_A0) 5569 { /* SOC_FORMAT_INT_CMIC_CMC_IRQ_STAT5_BCM56670_A0fmt */ 5570 /* format CMIC_CMC_IRQ_STAT5fmt */ 5571 /* nFields */ 1, 5572 /* *fields */ soc_CMIC_CMC_IRQ_STAT6fmt_fields, 5573 /* bits */ 32, 5574 /* flags */ 0, 5575 }, 5576 #endif /* chips */ 5577 5578 #if defined(BCM_56670_B0) 5579 { /* SOC_FORMAT_INT_CMIC_CMC_IRQ_STAT5_BCM56670_B0fmt */ 5580 /* format CMIC_CMC_IRQ_STAT5fmt */ 5581 /* nFields */ 1, 5582 /* *fields */ soc_CMIC_CMC_IRQ_STAT6fmt_fields, 5583 /* bits */ 32, 5584 /* flags */ 0, 5585 }, 5586 #endif /* chips */ 5587 5588 #if defined(BCM_56770_A0) 5589 { /* SOC_FORMAT_INT_CMIC_CMC_IRQ_STAT5_BCM56770_A0fmt */ 5590 /* format CMIC_CMC_IRQ_STAT5fmt */ 5591 /* nFields */ 1, 5592 /* *fields */ soc_CMIC_CMC_IRQ_STAT6fmt_fields, 5593 /* bits */ 32, 5594 /* flags */ 0, 5595 }, 5596 #endif /* chips */ 5597 5598 #if defined(BCM_56970_A0) 5599 { /* SOC_FORMAT_INT_CMIC_CMC_IRQ_STAT5_BCM56970_A0fmt */ 5600 /* format CMIC_CMC_IRQ_STAT5fmt */ 5601 /* nFields */ 2, 5602 /* *fields */ soc_CMIC_CMC_IRQ_STAT5_BCM56970_A0fmt_fields, 5603 /* bits */ 32, 5604 /* flags */ 0, 5605 }, 5606 #endif /* chips */ 5607 5608 #if defined(BCM_56970_A0) 5609 { /* SOC_FORMAT_INT_CMIC_CMC_IRQ_STAT6_BCM56970_A0fmt */ 5610 /* format CMIC_CMC_IRQ_STAT6fmt */ 5611 /* nFields */ 32, 5612 /* *fields */ soc_CMIC_CMC_IRQ_STAT6_BCM56970_A0fmt_fields, 5613 /* bits */ 32, 5614 /* flags */ 0, 5615 }, 5616 #endif /* chips */ 5617 5618 #if defined(BCM_56840_A0) 5619 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_0fmt */ 5620 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_0fmt */ 5621 /* nFields */ 13, 5622 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_0fmt_fields, 5623 /* bits */ 32, 5624 /* flags */ 0, 5625 }, 5626 #endif /* chips */ 5627 5628 #if defined(BCM_56840_A0) || defined(BCM_56840_B0) 5629 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_1fmt */ 5630 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_1fmt */ 5631 /* nFields */ 5, 5632 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_1fmt_fields, 5633 /* bits */ 32, 5634 /* flags */ 0, 5635 }, 5636 #endif /* chips */ 5637 5638 #if defined(BCM_56840_A0) 5639 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_2fmt */ 5640 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_2fmt */ 5641 /* nFields */ 7, 5642 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_2fmt_fields, 5643 /* bits */ 32, 5644 /* flags */ 0, 5645 }, 5646 #endif /* chips */ 5647 5648 #if defined(BCM_56840_A0) 5649 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3fmt */ 5650 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3fmt */ 5651 /* nFields */ 8, 5652 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3fmt_fields, 5653 /* bits */ 32, 5654 /* flags */ 0, 5655 }, 5656 #endif /* chips */ 5657 5658 #if defined(BCM_56840_A0) 5659 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_4fmt */ 5660 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_4fmt */ 5661 /* nFields */ 6, 5662 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_4fmt_fields, 5663 /* bits */ 32, 5664 /* flags */ 0, 5665 }, 5666 #endif /* chips */ 5667 5668 #if defined(BCM_56260_A0) 5669 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_0_BCM56260_A0fmt */ 5670 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_0fmt */ 5671 /* nFields */ 13, 5672 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_0_BCM56260_A0fmt_fields, 5673 /* bits */ 32, 5674 /* flags */ 0, 5675 }, 5676 #endif /* chips */ 5677 5678 #if defined(BCM_56260_B0) 5679 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_0_BCM56260_B0fmt */ 5680 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_0fmt */ 5681 /* nFields */ 13, 5682 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_0_BCM56260_A0fmt_fields, 5683 /* bits */ 32, 5684 /* flags */ 0, 5685 }, 5686 #endif /* chips */ 5687 5688 #if defined(BCM_56270_A0) 5689 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_0_BCM56270_A0fmt */ 5690 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_0fmt */ 5691 /* nFields */ 13, 5692 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_0_BCM56260_A0fmt_fields, 5693 /* bits */ 32, 5694 /* flags */ 0, 5695 }, 5696 #endif /* chips */ 5697 5698 #if defined(BCM_56340_A0) 5699 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_0_BCM56340_A0fmt */ 5700 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_0fmt */ 5701 /* nFields */ 13, 5702 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_0_BCM56640_A0fmt_fields, 5703 /* bits */ 32, 5704 /* flags */ 0, 5705 }, 5706 #endif /* chips */ 5707 5708 #if defined(BCM_56370_A0) 5709 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_0_BCM56370_A0fmt */ 5710 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_0fmt */ 5711 /* nFields */ 15, 5712 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_0_BCM56960_A0fmt_fields, 5713 /* bits */ 32, 5714 /* flags */ 0, 5715 }, 5716 #endif /* chips */ 5717 5718 #if defined(BCM_56450_A0) 5719 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_0_BCM56450_A0fmt */ 5720 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_0fmt */ 5721 /* nFields */ 13, 5722 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_0_BCM56640_A0fmt_fields, 5723 /* bits */ 32, 5724 /* flags */ 0, 5725 }, 5726 #endif /* chips */ 5727 5728 #if defined(BCM_56450_B0) 5729 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_0_BCM56450_B0fmt */ 5730 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_0fmt */ 5731 /* nFields */ 13, 5732 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_0_BCM56640_A0fmt_fields, 5733 /* bits */ 32, 5734 /* flags */ 0, 5735 }, 5736 #endif /* chips */ 5737 5738 #if defined(BCM_56450_B1) 5739 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_0_BCM56450_B1fmt */ 5740 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_0fmt */ 5741 /* nFields */ 13, 5742 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_0_BCM56640_A0fmt_fields, 5743 /* bits */ 32, 5744 /* flags */ 0, 5745 }, 5746 #endif /* chips */ 5747 5748 #if defined(BCM_56640_A0) 5749 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_0_BCM56640_A0fmt */ 5750 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_0fmt */ 5751 /* nFields */ 13, 5752 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_0_BCM56640_A0fmt_fields, 5753 /* bits */ 32, 5754 /* flags */ 0, 5755 }, 5756 #endif /* chips */ 5757 5758 #if defined(BCM_56770_A0) 5759 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_0_BCM56770_A0fmt */ 5760 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_0fmt */ 5761 /* nFields */ 15, 5762 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_0_BCM56960_A0fmt_fields, 5763 /* bits */ 32, 5764 /* flags */ 0, 5765 }, 5766 #endif /* chips */ 5767 5768 #if defined(BCM_56840_B0) 5769 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_0_BCM56840_B0fmt */ 5770 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_0fmt */ 5771 /* nFields */ 15, 5772 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_0_BCM56840_B0fmt_fields, 5773 /* bits */ 32, 5774 /* flags */ 0, 5775 }, 5776 #endif /* chips */ 5777 5778 #if defined(BCM_56850_A0) 5779 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_0_BCM56850_A0fmt */ 5780 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_0fmt */ 5781 /* nFields */ 15, 5782 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_0_BCM56850_A0fmt_fields, 5783 /* bits */ 32, 5784 /* flags */ 0, 5785 }, 5786 #endif /* chips */ 5787 5788 #if defined(BCM_56860_A0) 5789 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_0_BCM56860_A0fmt */ 5790 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_0fmt */ 5791 /* nFields */ 15, 5792 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_0_BCM56850_A0fmt_fields, 5793 /* bits */ 32, 5794 /* flags */ 0, 5795 }, 5796 #endif /* chips */ 5797 5798 #if defined(BCM_56870_A0) 5799 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_0_BCM56870_A0fmt */ 5800 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_0fmt */ 5801 /* nFields */ 15, 5802 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_0_BCM56960_A0fmt_fields, 5803 /* bits */ 32, 5804 /* flags */ 0, 5805 }, 5806 #endif /* chips */ 5807 5808 #if defined(BCM_56960_A0) 5809 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_0_BCM56960_A0fmt */ 5810 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_0fmt */ 5811 /* nFields */ 15, 5812 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_0_BCM56960_A0fmt_fields, 5813 /* bits */ 32, 5814 /* flags */ 0, 5815 }, 5816 #endif /* chips */ 5817 5818 #if defined(BCM_56965_A0) 5819 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_0_BCM56965_A0fmt */ 5820 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_0fmt */ 5821 /* nFields */ 15, 5822 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_0_BCM56960_A0fmt_fields, 5823 /* bits */ 32, 5824 /* flags */ 0, 5825 }, 5826 #endif /* chips */ 5827 5828 #if defined(BCM_56970_A0) 5829 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_0_BCM56970_A0fmt */ 5830 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_0fmt */ 5831 /* nFields */ 15, 5832 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_0_BCM56960_A0fmt_fields, 5833 /* bits */ 32, 5834 /* flags */ 0, 5835 }, 5836 #endif /* chips */ 5837 5838 #if defined(BCM_88732_A0) 5839 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_0_BCM88732_A0fmt */ 5840 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_0fmt */ 5841 /* nFields */ 4, 5842 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_0_BCM88732_A0fmt_fields, 5843 /* bits */ 32, 5844 /* flags */ 0, 5845 }, 5846 #endif /* chips */ 5847 5848 #if defined(BCM_56260_A0) 5849 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_1_BCM56260_A0fmt */ 5850 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_1fmt */ 5851 /* nFields */ 5, 5852 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_1_BCM56960_A0fmt_fields, 5853 /* bits */ 32, 5854 /* flags */ 0, 5855 }, 5856 #endif /* chips */ 5857 5858 #if defined(BCM_56260_B0) 5859 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_1_BCM56260_B0fmt */ 5860 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_1fmt */ 5861 /* nFields */ 5, 5862 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_1_BCM56960_A0fmt_fields, 5863 /* bits */ 32, 5864 /* flags */ 0, 5865 }, 5866 #endif /* chips */ 5867 5868 #if defined(BCM_56270_A0) 5869 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_1_BCM56270_A0fmt */ 5870 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_1fmt */ 5871 /* nFields */ 5, 5872 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_1_BCM56960_A0fmt_fields, 5873 /* bits */ 32, 5874 /* flags */ 0, 5875 }, 5876 #endif /* chips */ 5877 5878 #if defined(BCM_56340_A0) 5879 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_1_BCM56340_A0fmt */ 5880 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_1fmt */ 5881 /* nFields */ 5, 5882 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_1_BCM56640_A0fmt_fields, 5883 /* bits */ 32, 5884 /* flags */ 0, 5885 }, 5886 #endif /* chips */ 5887 5888 #if defined(BCM_56370_A0) 5889 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_1_BCM56370_A0fmt */ 5890 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_1fmt */ 5891 /* nFields */ 5, 5892 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_1_BCM56960_A0fmt_fields, 5893 /* bits */ 32, 5894 /* flags */ 0, 5895 }, 5896 #endif /* chips */ 5897 5898 #if defined(BCM_56450_A0) 5899 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_1_BCM56450_A0fmt */ 5900 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_1fmt */ 5901 /* nFields */ 5, 5902 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_1_BCM56640_A0fmt_fields, 5903 /* bits */ 32, 5904 /* flags */ 0, 5905 }, 5906 #endif /* chips */ 5907 5908 #if defined(BCM_56450_B0) 5909 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_1_BCM56450_B0fmt */ 5910 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_1fmt */ 5911 /* nFields */ 5, 5912 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_1_BCM56640_A0fmt_fields, 5913 /* bits */ 32, 5914 /* flags */ 0, 5915 }, 5916 #endif /* chips */ 5917 5918 #if defined(BCM_56450_B1) 5919 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_1_BCM56450_B1fmt */ 5920 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_1fmt */ 5921 /* nFields */ 5, 5922 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_1_BCM56640_A0fmt_fields, 5923 /* bits */ 32, 5924 /* flags */ 0, 5925 }, 5926 #endif /* chips */ 5927 5928 #if defined(BCM_56640_A0) 5929 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_1_BCM56640_A0fmt */ 5930 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_1fmt */ 5931 /* nFields */ 5, 5932 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_1_BCM56640_A0fmt_fields, 5933 /* bits */ 32, 5934 /* flags */ 0, 5935 }, 5936 #endif /* chips */ 5937 5938 #if defined(BCM_56770_A0) 5939 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_1_BCM56770_A0fmt */ 5940 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_1fmt */ 5941 /* nFields */ 5, 5942 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_1_BCM56960_A0fmt_fields, 5943 /* bits */ 32, 5944 /* flags */ 0, 5945 }, 5946 #endif /* chips */ 5947 5948 #if defined(BCM_56850_A0) 5949 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_1_BCM56850_A0fmt */ 5950 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_1fmt */ 5951 /* nFields */ 5, 5952 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_1_BCM56640_A0fmt_fields, 5953 /* bits */ 32, 5954 /* flags */ 0, 5955 }, 5956 #endif /* chips */ 5957 5958 #if defined(BCM_56860_A0) 5959 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_1_BCM56860_A0fmt */ 5960 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_1fmt */ 5961 /* nFields */ 5, 5962 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_1_BCM56640_A0fmt_fields, 5963 /* bits */ 32, 5964 /* flags */ 0, 5965 }, 5966 #endif /* chips */ 5967 5968 #if defined(BCM_56870_A0) 5969 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_1_BCM56870_A0fmt */ 5970 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_1fmt */ 5971 /* nFields */ 5, 5972 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_1_BCM56960_A0fmt_fields, 5973 /* bits */ 32, 5974 /* flags */ 0, 5975 }, 5976 #endif /* chips */ 5977 5978 #if defined(BCM_56960_A0) 5979 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_1_BCM56960_A0fmt */ 5980 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_1fmt */ 5981 /* nFields */ 5, 5982 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_1_BCM56960_A0fmt_fields, 5983 /* bits */ 32, 5984 /* flags */ 0, 5985 }, 5986 #endif /* chips */ 5987 5988 #if defined(BCM_56965_A0) 5989 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_1_BCM56965_A0fmt */ 5990 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_1fmt */ 5991 /* nFields */ 5, 5992 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_1_BCM56960_A0fmt_fields, 5993 /* bits */ 32, 5994 /* flags */ 0, 5995 }, 5996 #endif /* chips */ 5997 5998 #if defined(BCM_56970_A0) 5999 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_1_BCM56970_A0fmt */ 6000 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_1fmt */ 6001 /* nFields */ 5, 6002 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_1_BCM56960_A0fmt_fields, 6003 /* bits */ 32, 6004 /* flags */ 0, 6005 }, 6006 #endif /* chips */ 6007 6008 #if defined(BCM_88732_A0) 6009 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_1_BCM88732_A0fmt */ 6010 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_1fmt */ 6011 /* nFields */ 7, 6012 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_1_BCM88732_A0fmt_fields, 6013 /* bits */ 32, 6014 /* flags */ 0, 6015 }, 6016 #endif /* chips */ 6017 6018 #if defined(BCM_56260_A0) 6019 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_2_BCM56260_A0fmt */ 6020 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_2fmt */ 6021 /* nFields */ 7, 6022 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_2_BCM56960_A0fmt_fields, 6023 /* bits */ 32, 6024 /* flags */ 0, 6025 }, 6026 #endif /* chips */ 6027 6028 #if defined(BCM_56260_B0) 6029 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_2_BCM56260_B0fmt */ 6030 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_2fmt */ 6031 /* nFields */ 7, 6032 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_2_BCM56960_A0fmt_fields, 6033 /* bits */ 32, 6034 /* flags */ 0, 6035 }, 6036 #endif /* chips */ 6037 6038 #if defined(BCM_56270_A0) 6039 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_2_BCM56270_A0fmt */ 6040 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_2fmt */ 6041 /* nFields */ 7, 6042 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_2_BCM56960_A0fmt_fields, 6043 /* bits */ 32, 6044 /* flags */ 0, 6045 }, 6046 #endif /* chips */ 6047 6048 #if defined(BCM_56340_A0) 6049 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_2_BCM56340_A0fmt */ 6050 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_2fmt */ 6051 /* nFields */ 7, 6052 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_2_BCM56640_A0fmt_fields, 6053 /* bits */ 32, 6054 /* flags */ 0, 6055 }, 6056 #endif /* chips */ 6057 6058 #if defined(BCM_56370_A0) 6059 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_2_BCM56370_A0fmt */ 6060 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_2fmt */ 6061 /* nFields */ 7, 6062 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_2_BCM56960_A0fmt_fields, 6063 /* bits */ 32, 6064 /* flags */ 0, 6065 }, 6066 #endif /* chips */ 6067 6068 #if defined(BCM_56450_A0) 6069 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_2_BCM56450_A0fmt */ 6070 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_2fmt */ 6071 /* nFields */ 7, 6072 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_2_BCM56640_A0fmt_fields, 6073 /* bits */ 32, 6074 /* flags */ 0, 6075 }, 6076 #endif /* chips */ 6077 6078 #if defined(BCM_56450_B0) 6079 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_2_BCM56450_B0fmt */ 6080 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_2fmt */ 6081 /* nFields */ 7, 6082 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_2_BCM56640_A0fmt_fields, 6083 /* bits */ 32, 6084 /* flags */ 0, 6085 }, 6086 #endif /* chips */ 6087 6088 #if defined(BCM_56450_B1) 6089 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_2_BCM56450_B1fmt */ 6090 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_2fmt */ 6091 /* nFields */ 7, 6092 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_2_BCM56640_A0fmt_fields, 6093 /* bits */ 32, 6094 /* flags */ 0, 6095 }, 6096 #endif /* chips */ 6097 6098 #if defined(BCM_56640_A0) 6099 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_2_BCM56640_A0fmt */ 6100 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_2fmt */ 6101 /* nFields */ 7, 6102 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_2_BCM56640_A0fmt_fields, 6103 /* bits */ 32, 6104 /* flags */ 0, 6105 }, 6106 #endif /* chips */ 6107 6108 #if defined(BCM_56770_A0) 6109 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_2_BCM56770_A0fmt */ 6110 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_2fmt */ 6111 /* nFields */ 7, 6112 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_2_BCM56960_A0fmt_fields, 6113 /* bits */ 32, 6114 /* flags */ 0, 6115 }, 6116 #endif /* chips */ 6117 6118 #if defined(BCM_56840_B0) 6119 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_2_BCM56840_B0fmt */ 6120 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_2fmt */ 6121 /* nFields */ 7, 6122 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_2fmt_fields, 6123 /* bits */ 32, 6124 /* flags */ 0, 6125 }, 6126 #endif /* chips */ 6127 6128 #if defined(BCM_56850_A0) 6129 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_2_BCM56850_A0fmt */ 6130 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_2fmt */ 6131 /* nFields */ 7, 6132 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_2_BCM56640_A0fmt_fields, 6133 /* bits */ 32, 6134 /* flags */ 0, 6135 }, 6136 #endif /* chips */ 6137 6138 #if defined(BCM_56860_A0) 6139 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_2_BCM56860_A0fmt */ 6140 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_2fmt */ 6141 /* nFields */ 7, 6142 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_2_BCM56640_A0fmt_fields, 6143 /* bits */ 32, 6144 /* flags */ 0, 6145 }, 6146 #endif /* chips */ 6147 6148 #if defined(BCM_56870_A0) 6149 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_2_BCM56870_A0fmt */ 6150 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_2fmt */ 6151 /* nFields */ 7, 6152 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_2_BCM56960_A0fmt_fields, 6153 /* bits */ 32, 6154 /* flags */ 0, 6155 }, 6156 #endif /* chips */ 6157 6158 #if defined(BCM_56960_A0) 6159 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_2_BCM56960_A0fmt */ 6160 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_2fmt */ 6161 /* nFields */ 7, 6162 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_2_BCM56960_A0fmt_fields, 6163 /* bits */ 32, 6164 /* flags */ 0, 6165 }, 6166 #endif /* chips */ 6167 6168 #if defined(BCM_56965_A0) 6169 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_2_BCM56965_A0fmt */ 6170 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_2fmt */ 6171 /* nFields */ 7, 6172 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_2_BCM56960_A0fmt_fields, 6173 /* bits */ 32, 6174 /* flags */ 0, 6175 }, 6176 #endif /* chips */ 6177 6178 #if defined(BCM_56970_A0) 6179 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_2_BCM56970_A0fmt */ 6180 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_2fmt */ 6181 /* nFields */ 7, 6182 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_2_BCM56960_A0fmt_fields, 6183 /* bits */ 32, 6184 /* flags */ 0, 6185 }, 6186 #endif /* chips */ 6187 6188 #if defined(BCM_88732_A0) 6189 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_2_BCM88732_A0fmt */ 6190 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_2fmt */ 6191 /* nFields */ 6, 6192 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_2_BCM88732_A0fmt_fields, 6193 /* bits */ 32, 6194 /* flags */ 0, 6195 }, 6196 #endif /* chips */ 6197 6198 #if defined(BCM_56260_A0) 6199 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3_BCM56260_A0fmt */ 6200 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3fmt */ 6201 /* nFields */ 8, 6202 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3_BCM56960_A0fmt_fields, 6203 /* bits */ 32, 6204 /* flags */ 0, 6205 }, 6206 #endif /* chips */ 6207 6208 #if defined(BCM_56260_B0) 6209 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3_BCM56260_B0fmt */ 6210 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3fmt */ 6211 /* nFields */ 8, 6212 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3_BCM56960_A0fmt_fields, 6213 /* bits */ 32, 6214 /* flags */ 0, 6215 }, 6216 #endif /* chips */ 6217 6218 #if defined(BCM_56270_A0) 6219 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3_BCM56270_A0fmt */ 6220 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3fmt */ 6221 /* nFields */ 8, 6222 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3_BCM56960_A0fmt_fields, 6223 /* bits */ 32, 6224 /* flags */ 0, 6225 }, 6226 #endif /* chips */ 6227 6228 #if defined(BCM_56340_A0) 6229 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3_BCM56340_A0fmt */ 6230 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3fmt */ 6231 /* nFields */ 8, 6232 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3_BCM56640_A0fmt_fields, 6233 /* bits */ 32, 6234 /* flags */ 0, 6235 }, 6236 #endif /* chips */ 6237 6238 #if defined(BCM_56370_A0) 6239 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3_BCM56370_A0fmt */ 6240 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3fmt */ 6241 /* nFields */ 8, 6242 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3_BCM56960_A0fmt_fields, 6243 /* bits */ 32, 6244 /* flags */ 0, 6245 }, 6246 #endif /* chips */ 6247 6248 #if defined(BCM_56450_A0) 6249 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3_BCM56450_A0fmt */ 6250 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3fmt */ 6251 /* nFields */ 8, 6252 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3_BCM56640_A0fmt_fields, 6253 /* bits */ 32, 6254 /* flags */ 0, 6255 }, 6256 #endif /* chips */ 6257 6258 #if defined(BCM_56450_B0) 6259 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3_BCM56450_B0fmt */ 6260 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3fmt */ 6261 /* nFields */ 8, 6262 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3_BCM56640_A0fmt_fields, 6263 /* bits */ 32, 6264 /* flags */ 0, 6265 }, 6266 #endif /* chips */ 6267 6268 #if defined(BCM_56450_B1) 6269 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3_BCM56450_B1fmt */ 6270 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3fmt */ 6271 /* nFields */ 8, 6272 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3_BCM56640_A0fmt_fields, 6273 /* bits */ 32, 6274 /* flags */ 0, 6275 }, 6276 #endif /* chips */ 6277 6278 #if defined(BCM_56640_A0) 6279 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3_BCM56640_A0fmt */ 6280 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3fmt */ 6281 /* nFields */ 8, 6282 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3_BCM56640_A0fmt_fields, 6283 /* bits */ 32, 6284 /* flags */ 0, 6285 }, 6286 #endif /* chips */ 6287 6288 #if defined(BCM_56770_A0) 6289 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3_BCM56770_A0fmt */ 6290 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3fmt */ 6291 /* nFields */ 8, 6292 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3_BCM56960_A0fmt_fields, 6293 /* bits */ 32, 6294 /* flags */ 0, 6295 }, 6296 #endif /* chips */ 6297 6298 #if defined(BCM_56840_B0) 6299 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3_BCM56840_B0fmt */ 6300 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3fmt */ 6301 /* nFields */ 8, 6302 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3fmt_fields, 6303 /* bits */ 32, 6304 /* flags */ 0, 6305 }, 6306 #endif /* chips */ 6307 6308 #if defined(BCM_56850_A0) 6309 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3_BCM56850_A0fmt */ 6310 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3fmt */ 6311 /* nFields */ 8, 6312 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3_BCM56640_A0fmt_fields, 6313 /* bits */ 32, 6314 /* flags */ 0, 6315 }, 6316 #endif /* chips */ 6317 6318 #if defined(BCM_56860_A0) 6319 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3_BCM56860_A0fmt */ 6320 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3fmt */ 6321 /* nFields */ 8, 6322 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3_BCM56640_A0fmt_fields, 6323 /* bits */ 32, 6324 /* flags */ 0, 6325 }, 6326 #endif /* chips */ 6327 6328 #if defined(BCM_56870_A0) 6329 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3_BCM56870_A0fmt */ 6330 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3fmt */ 6331 /* nFields */ 8, 6332 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3_BCM56960_A0fmt_fields, 6333 /* bits */ 32, 6334 /* flags */ 0, 6335 }, 6336 #endif /* chips */ 6337 6338 #if defined(BCM_56960_A0) 6339 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3_BCM56960_A0fmt */ 6340 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3fmt */ 6341 /* nFields */ 8, 6342 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3_BCM56960_A0fmt_fields, 6343 /* bits */ 32, 6344 /* flags */ 0, 6345 }, 6346 #endif /* chips */ 6347 6348 #if defined(BCM_56965_A0) 6349 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3_BCM56965_A0fmt */ 6350 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3fmt */ 6351 /* nFields */ 8, 6352 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3_BCM56960_A0fmt_fields, 6353 /* bits */ 32, 6354 /* flags */ 0, 6355 }, 6356 #endif /* chips */ 6357 6358 #if defined(BCM_56970_A0) 6359 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3_BCM56970_A0fmt */ 6360 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3fmt */ 6361 /* nFields */ 8, 6362 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3_BCM56960_A0fmt_fields, 6363 /* bits */ 32, 6364 /* flags */ 0, 6365 }, 6366 #endif /* chips */ 6367 6368 #if defined(BCM_88732_A0) 6369 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3_BCM88732_A0fmt */ 6370 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3fmt */ 6371 /* nFields */ 5, 6372 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_3_BCM88732_A0fmt_fields, 6373 /* bits */ 32, 6374 /* flags */ 0, 6375 }, 6376 #endif /* chips */ 6377 6378 #if defined(BCM_56260_A0) 6379 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_4_BCM56260_A0fmt */ 6380 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_4fmt */ 6381 /* nFields */ 6, 6382 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_4_BCM56960_A0fmt_fields, 6383 /* bits */ 32, 6384 /* flags */ 0, 6385 }, 6386 #endif /* chips */ 6387 6388 #if defined(BCM_56260_B0) 6389 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_4_BCM56260_B0fmt */ 6390 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_4fmt */ 6391 /* nFields */ 6, 6392 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_4_BCM56960_A0fmt_fields, 6393 /* bits */ 32, 6394 /* flags */ 0, 6395 }, 6396 #endif /* chips */ 6397 6398 #if defined(BCM_56270_A0) 6399 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_4_BCM56270_A0fmt */ 6400 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_4fmt */ 6401 /* nFields */ 6, 6402 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_4_BCM56960_A0fmt_fields, 6403 /* bits */ 32, 6404 /* flags */ 0, 6405 }, 6406 #endif /* chips */ 6407 6408 #if defined(BCM_56340_A0) 6409 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_4_BCM56340_A0fmt */ 6410 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_4fmt */ 6411 /* nFields */ 6, 6412 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_4_BCM56640_A0fmt_fields, 6413 /* bits */ 32, 6414 /* flags */ 0, 6415 }, 6416 #endif /* chips */ 6417 6418 #if defined(BCM_56370_A0) 6419 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_4_BCM56370_A0fmt */ 6420 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_4fmt */ 6421 /* nFields */ 6, 6422 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_4_BCM56960_A0fmt_fields, 6423 /* bits */ 32, 6424 /* flags */ 0, 6425 }, 6426 #endif /* chips */ 6427 6428 #if defined(BCM_56450_A0) 6429 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_4_BCM56450_A0fmt */ 6430 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_4fmt */ 6431 /* nFields */ 6, 6432 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_4_BCM56640_A0fmt_fields, 6433 /* bits */ 32, 6434 /* flags */ 0, 6435 }, 6436 #endif /* chips */ 6437 6438 #if defined(BCM_56450_B0) 6439 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_4_BCM56450_B0fmt */ 6440 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_4fmt */ 6441 /* nFields */ 6, 6442 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_4_BCM56640_A0fmt_fields, 6443 /* bits */ 32, 6444 /* flags */ 0, 6445 }, 6446 #endif /* chips */ 6447 6448 #if defined(BCM_56450_B1) 6449 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_4_BCM56450_B1fmt */ 6450 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_4fmt */ 6451 /* nFields */ 6, 6452 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_4_BCM56640_A0fmt_fields, 6453 /* bits */ 32, 6454 /* flags */ 0, 6455 }, 6456 #endif /* chips */ 6457 6458 #if defined(BCM_56640_A0) 6459 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_4_BCM56640_A0fmt */ 6460 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_4fmt */ 6461 /* nFields */ 6, 6462 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_4_BCM56640_A0fmt_fields, 6463 /* bits */ 32, 6464 /* flags */ 0, 6465 }, 6466 #endif /* chips */ 6467 6468 #if defined(BCM_56770_A0) 6469 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_4_BCM56770_A0fmt */ 6470 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_4fmt */ 6471 /* nFields */ 6, 6472 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_4_BCM56960_A0fmt_fields, 6473 /* bits */ 32, 6474 /* flags */ 0, 6475 }, 6476 #endif /* chips */ 6477 6478 #if defined(BCM_56840_B0) 6479 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_4_BCM56840_B0fmt */ 6480 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_4fmt */ 6481 /* nFields */ 6, 6482 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_4fmt_fields, 6483 /* bits */ 32, 6484 /* flags */ 0, 6485 }, 6486 #endif /* chips */ 6487 6488 #if defined(BCM_56850_A0) 6489 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_4_BCM56850_A0fmt */ 6490 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_4fmt */ 6491 /* nFields */ 6, 6492 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_4_BCM56640_A0fmt_fields, 6493 /* bits */ 32, 6494 /* flags */ 0, 6495 }, 6496 #endif /* chips */ 6497 6498 #if defined(BCM_56860_A0) 6499 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_4_BCM56860_A0fmt */ 6500 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_4fmt */ 6501 /* nFields */ 6, 6502 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_4_BCM56640_A0fmt_fields, 6503 /* bits */ 32, 6504 /* flags */ 0, 6505 }, 6506 #endif /* chips */ 6507 6508 #if defined(BCM_56870_A0) 6509 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_4_BCM56870_A0fmt */ 6510 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_4fmt */ 6511 /* nFields */ 6, 6512 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_4_BCM56960_A0fmt_fields, 6513 /* bits */ 32, 6514 /* flags */ 0, 6515 }, 6516 #endif /* chips */ 6517 6518 #if defined(BCM_56960_A0) 6519 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_4_BCM56960_A0fmt */ 6520 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_4fmt */ 6521 /* nFields */ 6, 6522 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_4_BCM56960_A0fmt_fields, 6523 /* bits */ 32, 6524 /* flags */ 0, 6525 }, 6526 #endif /* chips */ 6527 6528 #if defined(BCM_56965_A0) 6529 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_4_BCM56965_A0fmt */ 6530 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_4fmt */ 6531 /* nFields */ 6, 6532 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_4_BCM56960_A0fmt_fields, 6533 /* bits */ 32, 6534 /* flags */ 0, 6535 }, 6536 #endif /* chips */ 6537 6538 #if defined(BCM_56970_A0) 6539 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_4_BCM56970_A0fmt */ 6540 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_4fmt */ 6541 /* nFields */ 6, 6542 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_4_BCM56960_A0fmt_fields, 6543 /* bits */ 32, 6544 /* flags */ 0, 6545 }, 6546 #endif /* chips */ 6547 6548 #if defined(BCM_88732_A0) 6549 { /* SOC_FORMAT_INT_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_4_BCM88732_A0fmt */ 6550 /* format CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_4fmt */ 6551 /* nFields */ 11, 6552 /* *fields */ soc_CMIC_CORE_PLL0_CTRL_STATUS_REGISTER_4_BCM88732_A0fmt_fields, 6553 /* bits */ 32, 6554 /* flags */ 0, 6555 }, 6556 #endif /* chips */ 6557 6558 #if defined(BCM_56840_A0) || defined(BCM_56840_B0) 6559 { /* SOC_FORMAT_INT_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_0fmt */ 6560 /* format CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_0fmt */ 6561 /* nFields */ 3, 6562 /* *fields */ soc_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_0fmt_fields, 6563 /* bits */ 32, 6564 /* flags */ 0, 6565 }, 6566 #endif /* chips */ 6567 6568 #if defined(BCM_56840_A0) || defined(BCM_56840_B0) 6569 { /* SOC_FORMAT_INT_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_1fmt */ 6570 /* format CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_1fmt */ 6571 /* nFields */ 3, 6572 /* *fields */ soc_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_1fmt_fields, 6573 /* bits */ 32, 6574 /* flags */ 0, 6575 }, 6576 #endif /* chips */ 6577 6578 #if defined(BCM_56840_A0) || defined(BCM_56840_B0) 6579 { /* SOC_FORMAT_INT_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_2fmt */ 6580 /* format CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_2fmt */ 6581 /* nFields */ 3, 6582 /* *fields */ soc_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_2fmt_fields, 6583 /* bits */ 32, 6584 /* flags */ 0, 6585 }, 6586 #endif /* chips */ 6587 6588 #if defined(BCM_56260_A0) 6589 { /* SOC_FORMAT_INT_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_0_BCM56260_A0fmt */ 6590 /* format CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_0fmt */ 6591 /* nFields */ 3, 6592 /* *fields */ soc_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_0_BCM56960_A0fmt_fields, 6593 /* bits */ 32, 6594 /* flags */ 0, 6595 }, 6596 #endif /* chips */ 6597 6598 #if defined(BCM_56260_B0) 6599 { /* SOC_FORMAT_INT_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_0_BCM56260_B0fmt */ 6600 /* format CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_0fmt */ 6601 /* nFields */ 3, 6602 /* *fields */ soc_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_0_BCM56960_A0fmt_fields, 6603 /* bits */ 32, 6604 /* flags */ 0, 6605 }, 6606 #endif /* chips */ 6607 6608 #if defined(BCM_56270_A0) 6609 { /* SOC_FORMAT_INT_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_0_BCM56270_A0fmt */ 6610 /* format CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_0fmt */ 6611 /* nFields */ 3, 6612 /* *fields */ soc_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_0_BCM56960_A0fmt_fields, 6613 /* bits */ 32, 6614 /* flags */ 0, 6615 }, 6616 #endif /* chips */ 6617 6618 #if defined(BCM_56340_A0) 6619 { /* SOC_FORMAT_INT_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_0_BCM56340_A0fmt */ 6620 /* format CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_0fmt */ 6621 /* nFields */ 3, 6622 /* *fields */ soc_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_0_BCM56640_A0fmt_fields, 6623 /* bits */ 32, 6624 /* flags */ 0, 6625 }, 6626 #endif /* chips */ 6627 6628 #if defined(BCM_56370_A0) 6629 { /* SOC_FORMAT_INT_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_0_BCM56370_A0fmt */ 6630 /* format CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_0fmt */ 6631 /* nFields */ 3, 6632 /* *fields */ soc_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_0_BCM56960_A0fmt_fields, 6633 /* bits */ 32, 6634 /* flags */ 0, 6635 }, 6636 #endif /* chips */ 6637 6638 #if defined(BCM_56450_A0) 6639 { /* SOC_FORMAT_INT_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_0_BCM56450_A0fmt */ 6640 /* format CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_0fmt */ 6641 /* nFields */ 3, 6642 /* *fields */ soc_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_0_BCM56640_A0fmt_fields, 6643 /* bits */ 32, 6644 /* flags */ 0, 6645 }, 6646 #endif /* chips */ 6647 6648 #if defined(BCM_56450_B0) 6649 { /* SOC_FORMAT_INT_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_0_BCM56450_B0fmt */ 6650 /* format CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_0fmt */ 6651 /* nFields */ 3, 6652 /* *fields */ soc_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_0_BCM56640_A0fmt_fields, 6653 /* bits */ 32, 6654 /* flags */ 0, 6655 }, 6656 #endif /* chips */ 6657 6658 #if defined(BCM_56450_B1) 6659 { /* SOC_FORMAT_INT_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_0_BCM56450_B1fmt */ 6660 /* format CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_0fmt */ 6661 /* nFields */ 3, 6662 /* *fields */ soc_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_0_BCM56640_A0fmt_fields, 6663 /* bits */ 32, 6664 /* flags */ 0, 6665 }, 6666 #endif /* chips */ 6667 6668 #if defined(BCM_56640_A0) 6669 { /* SOC_FORMAT_INT_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_0_BCM56640_A0fmt */ 6670 /* format CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_0fmt */ 6671 /* nFields */ 3, 6672 /* *fields */ soc_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_0_BCM56640_A0fmt_fields, 6673 /* bits */ 32, 6674 /* flags */ 0, 6675 }, 6676 #endif /* chips */ 6677 6678 #if defined(BCM_56770_A0) 6679 { /* SOC_FORMAT_INT_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_0_BCM56770_A0fmt */ 6680 /* format CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_0fmt */ 6681 /* nFields */ 3, 6682 /* *fields */ soc_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_0_BCM56960_A0fmt_fields, 6683 /* bits */ 32, 6684 /* flags */ 0, 6685 }, 6686 #endif /* chips */ 6687 6688 #if defined(BCM_56850_A0) 6689 { /* SOC_FORMAT_INT_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_0_BCM56850_A0fmt */ 6690 /* format CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_0fmt */ 6691 /* nFields */ 3, 6692 /* *fields */ soc_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_0_BCM56640_A0fmt_fields, 6693 /* bits */ 32, 6694 /* flags */ 0, 6695 }, 6696 #endif /* chips */ 6697 6698 #if defined(BCM_56860_A0) 6699 { /* SOC_FORMAT_INT_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_0_BCM56860_A0fmt */ 6700 /* format CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_0fmt */ 6701 /* nFields */ 3, 6702 /* *fields */ soc_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_0_BCM56640_A0fmt_fields, 6703 /* bits */ 32, 6704 /* flags */ 0, 6705 }, 6706 #endif /* chips */ 6707 6708 #if defined(BCM_56870_A0) 6709 { /* SOC_FORMAT_INT_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_0_BCM56870_A0fmt */ 6710 /* format CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_0fmt */ 6711 /* nFields */ 3, 6712 /* *fields */ soc_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_0_BCM56960_A0fmt_fields, 6713 /* bits */ 32, 6714 /* flags */ 0, 6715 }, 6716 #endif /* chips */ 6717 6718 #if defined(BCM_56960_A0) 6719 { /* SOC_FORMAT_INT_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_0_BCM56960_A0fmt */ 6720 /* format CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_0fmt */ 6721 /* nFields */ 3, 6722 /* *fields */ soc_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_0_BCM56960_A0fmt_fields, 6723 /* bits */ 32, 6724 /* flags */ 0, 6725 }, 6726 #endif /* chips */ 6727 6728 #if defined(BCM_56965_A0) 6729 { /* SOC_FORMAT_INT_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_0_BCM56965_A0fmt */ 6730 /* format CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_0fmt */ 6731 /* nFields */ 3, 6732 /* *fields */ soc_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_0_BCM56960_A0fmt_fields, 6733 /* bits */ 32, 6734 /* flags */ 0, 6735 }, 6736 #endif /* chips */ 6737 6738 #if defined(BCM_56970_A0) 6739 { /* SOC_FORMAT_INT_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_0_BCM56970_A0fmt */ 6740 /* format CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_0fmt */ 6741 /* nFields */ 3, 6742 /* *fields */ soc_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_0_BCM56960_A0fmt_fields, 6743 /* bits */ 32, 6744 /* flags */ 0, 6745 }, 6746 #endif /* chips */ 6747 6748 #if defined(BCM_88732_A0) 6749 { /* SOC_FORMAT_INT_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_0_BCM88732_A0fmt */ 6750 /* format CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_0fmt */ 6751 /* nFields */ 10, 6752 /* *fields */ soc_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_0_BCM88732_A0fmt_fields, 6753 /* bits */ 32, 6754 /* flags */ 0, 6755 }, 6756 #endif /* chips */ 6757 6758 #if defined(BCM_56260_A0) 6759 { /* SOC_FORMAT_INT_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_1_BCM56260_A0fmt */ 6760 /* format CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_1fmt */ 6761 /* nFields */ 3, 6762 /* *fields */ soc_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_1_BCM56960_A0fmt_fields, 6763 /* bits */ 32, 6764 /* flags */ 0, 6765 }, 6766 #endif /* chips */ 6767 6768 #if defined(BCM_56260_B0) 6769 { /* SOC_FORMAT_INT_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_1_BCM56260_B0fmt */ 6770 /* format CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_1fmt */ 6771 /* nFields */ 3, 6772 /* *fields */ soc_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_1_BCM56960_A0fmt_fields, 6773 /* bits */ 32, 6774 /* flags */ 0, 6775 }, 6776 #endif /* chips */ 6777 6778 #if defined(BCM_56270_A0) 6779 { /* SOC_FORMAT_INT_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_1_BCM56270_A0fmt */ 6780 /* format CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_1fmt */ 6781 /* nFields */ 3, 6782 /* *fields */ soc_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_1_BCM56960_A0fmt_fields, 6783 /* bits */ 32, 6784 /* flags */ 0, 6785 }, 6786 #endif /* chips */ 6787 6788 #if defined(BCM_56340_A0) 6789 { /* SOC_FORMAT_INT_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_1_BCM56340_A0fmt */ 6790 /* format CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_1fmt */ 6791 /* nFields */ 3, 6792 /* *fields */ soc_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_1_BCM56640_A0fmt_fields, 6793 /* bits */ 32, 6794 /* flags */ 0, 6795 }, 6796 #endif /* chips */ 6797 6798 #if defined(BCM_56370_A0) 6799 { /* SOC_FORMAT_INT_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_1_BCM56370_A0fmt */ 6800 /* format CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_1fmt */ 6801 /* nFields */ 3, 6802 /* *fields */ soc_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_1_BCM56960_A0fmt_fields, 6803 /* bits */ 32, 6804 /* flags */ 0, 6805 }, 6806 #endif /* chips */ 6807 6808 #if defined(BCM_56450_A0) 6809 { /* SOC_FORMAT_INT_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_1_BCM56450_A0fmt */ 6810 /* format CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_1fmt */ 6811 /* nFields */ 3, 6812 /* *fields */ soc_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_1_BCM56640_A0fmt_fields, 6813 /* bits */ 32, 6814 /* flags */ 0, 6815 }, 6816 #endif /* chips */ 6817 6818 #if defined(BCM_56450_B0) 6819 { /* SOC_FORMAT_INT_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_1_BCM56450_B0fmt */ 6820 /* format CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_1fmt */ 6821 /* nFields */ 3, 6822 /* *fields */ soc_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_1_BCM56640_A0fmt_fields, 6823 /* bits */ 32, 6824 /* flags */ 0, 6825 }, 6826 #endif /* chips */ 6827 6828 #if defined(BCM_56450_B1) 6829 { /* SOC_FORMAT_INT_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_1_BCM56450_B1fmt */ 6830 /* format CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_1fmt */ 6831 /* nFields */ 3, 6832 /* *fields */ soc_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_1_BCM56640_A0fmt_fields, 6833 /* bits */ 32, 6834 /* flags */ 0, 6835 }, 6836 #endif /* chips */ 6837 6838 #if defined(BCM_56640_A0) 6839 { /* SOC_FORMAT_INT_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_1_BCM56640_A0fmt */ 6840 /* format CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_1fmt */ 6841 /* nFields */ 3, 6842 /* *fields */ soc_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_1_BCM56640_A0fmt_fields, 6843 /* bits */ 32, 6844 /* flags */ 0, 6845 }, 6846 #endif /* chips */ 6847 6848 #if defined(BCM_56770_A0) 6849 { /* SOC_FORMAT_INT_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_1_BCM56770_A0fmt */ 6850 /* format CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_1fmt */ 6851 /* nFields */ 3, 6852 /* *fields */ soc_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_1_BCM56960_A0fmt_fields, 6853 /* bits */ 32, 6854 /* flags */ 0, 6855 }, 6856 #endif /* chips */ 6857 6858 #if defined(BCM_56850_A0) 6859 { /* SOC_FORMAT_INT_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_1_BCM56850_A0fmt */ 6860 /* format CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_1fmt */ 6861 /* nFields */ 3, 6862 /* *fields */ soc_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_1_BCM56640_A0fmt_fields, 6863 /* bits */ 32, 6864 /* flags */ 0, 6865 }, 6866 #endif /* chips */ 6867 6868 #if defined(BCM_56860_A0) 6869 { /* SOC_FORMAT_INT_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_1_BCM56860_A0fmt */ 6870 /* format CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_1fmt */ 6871 /* nFields */ 3, 6872 /* *fields */ soc_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_1_BCM56640_A0fmt_fields, 6873 /* bits */ 32, 6874 /* flags */ 0, 6875 }, 6876 #endif /* chips */ 6877 6878 #if defined(BCM_56870_A0) 6879 { /* SOC_FORMAT_INT_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_1_BCM56870_A0fmt */ 6880 /* format CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_1fmt */ 6881 /* nFields */ 3, 6882 /* *fields */ soc_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_1_BCM56960_A0fmt_fields, 6883 /* bits */ 32, 6884 /* flags */ 0, 6885 }, 6886 #endif /* chips */ 6887 6888 #if defined(BCM_56960_A0) 6889 { /* SOC_FORMAT_INT_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_1_BCM56960_A0fmt */ 6890 /* format CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_1fmt */ 6891 /* nFields */ 3, 6892 /* *fields */ soc_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_1_BCM56960_A0fmt_fields, 6893 /* bits */ 32, 6894 /* flags */ 0, 6895 }, 6896 #endif /* chips */ 6897 6898 #if defined(BCM_56965_A0) 6899 { /* SOC_FORMAT_INT_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_1_BCM56965_A0fmt */ 6900 /* format CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_1fmt */ 6901 /* nFields */ 3, 6902 /* *fields */ soc_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_1_BCM56960_A0fmt_fields, 6903 /* bits */ 32, 6904 /* flags */ 0, 6905 }, 6906 #endif /* chips */ 6907 6908 #if defined(BCM_56970_A0) 6909 { /* SOC_FORMAT_INT_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_1_BCM56970_A0fmt */ 6910 /* format CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_1fmt */ 6911 /* nFields */ 3, 6912 /* *fields */ soc_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_1_BCM56960_A0fmt_fields, 6913 /* bits */ 32, 6914 /* flags */ 0, 6915 }, 6916 #endif /* chips */ 6917 6918 #if defined(BCM_88732_A0) 6919 { /* SOC_FORMAT_INT_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_1_BCM88732_A0fmt */ 6920 /* format CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_1fmt */ 6921 /* nFields */ 19, 6922 /* *fields */ soc_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_1_BCM88732_A0fmt_fields, 6923 /* bits */ 32, 6924 /* flags */ 0, 6925 }, 6926 #endif /* chips */ 6927 6928 #if defined(BCM_56260_A0) 6929 { /* SOC_FORMAT_INT_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_2_BCM56260_A0fmt */ 6930 /* format CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_2fmt */ 6931 /* nFields */ 3, 6932 /* *fields */ soc_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_2_BCM56960_A0fmt_fields, 6933 /* bits */ 32, 6934 /* flags */ 0, 6935 }, 6936 #endif /* chips */ 6937 6938 #if defined(BCM_56260_B0) 6939 { /* SOC_FORMAT_INT_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_2_BCM56260_B0fmt */ 6940 /* format CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_2fmt */ 6941 /* nFields */ 3, 6942 /* *fields */ soc_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_2_BCM56960_A0fmt_fields, 6943 /* bits */ 32, 6944 /* flags */ 0, 6945 }, 6946 #endif /* chips */ 6947 6948 #if defined(BCM_56270_A0) 6949 { /* SOC_FORMAT_INT_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_2_BCM56270_A0fmt */ 6950 /* format CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_2fmt */ 6951 /* nFields */ 3, 6952 /* *fields */ soc_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_2_BCM56960_A0fmt_fields, 6953 /* bits */ 32, 6954 /* flags */ 0, 6955 }, 6956 #endif /* chips */ 6957 6958 #if defined(BCM_56340_A0) 6959 { /* SOC_FORMAT_INT_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_2_BCM56340_A0fmt */ 6960 /* format CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_2fmt */ 6961 /* nFields */ 3, 6962 /* *fields */ soc_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_2_BCM56640_A0fmt_fields, 6963 /* bits */ 32, 6964 /* flags */ 0, 6965 }, 6966 #endif /* chips */ 6967 6968 #if defined(BCM_56370_A0) 6969 { /* SOC_FORMAT_INT_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_2_BCM56370_A0fmt */ 6970 /* format CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_2fmt */ 6971 /* nFields */ 3, 6972 /* *fields */ soc_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_2_BCM56960_A0fmt_fields, 6973 /* bits */ 32, 6974 /* flags */ 0, 6975 }, 6976 #endif /* chips */ 6977 6978 #if defined(BCM_56450_A0) 6979 { /* SOC_FORMAT_INT_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_2_BCM56450_A0fmt */ 6980 /* format CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_2fmt */ 6981 /* nFields */ 3, 6982 /* *fields */ soc_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_2_BCM56640_A0fmt_fields, 6983 /* bits */ 32, 6984 /* flags */ 0, 6985 }, 6986 #endif /* chips */ 6987 6988 #if defined(BCM_56450_B0) 6989 { /* SOC_FORMAT_INT_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_2_BCM56450_B0fmt */ 6990 /* format CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_2fmt */ 6991 /* nFields */ 3, 6992 /* *fields */ soc_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_2_BCM56640_A0fmt_fields, 6993 /* bits */ 32, 6994 /* flags */ 0, 6995 }, 6996 #endif /* chips */ 6997 6998 #if defined(BCM_56450_B1) 6999 { /* SOC_FORMAT_INT_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_2_BCM56450_B1fmt */ 7000 /* format CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_2fmt */ 7001 /* nFields */ 3, 7002 /* *fields */ soc_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_2_BCM56640_A0fmt_fields, 7003 /* bits */ 32, 7004 /* flags */ 0, 7005 }, 7006 #endif /* chips */ 7007 7008 #if defined(BCM_56640_A0) 7009 { /* SOC_FORMAT_INT_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_2_BCM56640_A0fmt */ 7010 /* format CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_2fmt */ 7011 /* nFields */ 3, 7012 /* *fields */ soc_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_2_BCM56640_A0fmt_fields, 7013 /* bits */ 32, 7014 /* flags */ 0, 7015 }, 7016 #endif /* chips */ 7017 7018 #if defined(BCM_56770_A0) 7019 { /* SOC_FORMAT_INT_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_2_BCM56770_A0fmt */ 7020 /* format CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_2fmt */ 7021 /* nFields */ 3, 7022 /* *fields */ soc_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_2_BCM56960_A0fmt_fields, 7023 /* bits */ 32, 7024 /* flags */ 0, 7025 }, 7026 #endif /* chips */ 7027 7028 #if defined(BCM_56850_A0) 7029 { /* SOC_FORMAT_INT_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_2_BCM56850_A0fmt */ 7030 /* format CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_2fmt */ 7031 /* nFields */ 3, 7032 /* *fields */ soc_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_2_BCM56640_A0fmt_fields, 7033 /* bits */ 32, 7034 /* flags */ 0, 7035 }, 7036 #endif /* chips */ 7037 7038 #if defined(BCM_56860_A0) 7039 { /* SOC_FORMAT_INT_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_2_BCM56860_A0fmt */ 7040 /* format CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_2fmt */ 7041 /* nFields */ 3, 7042 /* *fields */ soc_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_2_BCM56640_A0fmt_fields, 7043 /* bits */ 32, 7044 /* flags */ 0, 7045 }, 7046 #endif /* chips */ 7047 7048 #if defined(BCM_56870_A0) 7049 { /* SOC_FORMAT_INT_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_2_BCM56870_A0fmt */ 7050 /* format CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_2fmt */ 7051 /* nFields */ 3, 7052 /* *fields */ soc_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_2_BCM56960_A0fmt_fields, 7053 /* bits */ 32, 7054 /* flags */ 0, 7055 }, 7056 #endif /* chips */ 7057 7058 #if defined(BCM_56960_A0) 7059 { /* SOC_FORMAT_INT_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_2_BCM56960_A0fmt */ 7060 /* format CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_2fmt */ 7061 /* nFields */ 3, 7062 /* *fields */ soc_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_2_BCM56960_A0fmt_fields, 7063 /* bits */ 32, 7064 /* flags */ 0, 7065 }, 7066 #endif /* chips */ 7067 7068 #if defined(BCM_56965_A0) 7069 { /* SOC_FORMAT_INT_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_2_BCM56965_A0fmt */ 7070 /* format CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_2fmt */ 7071 /* nFields */ 3, 7072 /* *fields */ soc_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_2_BCM56960_A0fmt_fields, 7073 /* bits */ 32, 7074 /* flags */ 0, 7075 }, 7076 #endif /* chips */ 7077 7078 #if defined(BCM_56970_A0) 7079 { /* SOC_FORMAT_INT_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_2_BCM56970_A0fmt */ 7080 /* format CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_2fmt */ 7081 /* nFields */ 3, 7082 /* *fields */ soc_CMIC_CORE_PLL1_CTRL_STATUS_REGISTER_2_BCM56960_A0fmt_fields, 7083 /* bits */ 32, 7084 /* flags */ 0, 7085 }, 7086 #endif /* chips */ 7087 7088 #if defined(BCM_56840_B0) 7089 { /* SOC_FORMAT_INT_CMIC_CORE_PLL3_CTRL_STATUS_REGISTER_2fmt */ 7090 /* format CMIC_CORE_PLL3_CTRL_STATUS_REGISTER_2fmt */ 7091 /* nFields */ 10, 7092 /* *fields */ soc_CMIC_CORE_PLL3_CTRL_STATUS_REGISTER_2fmt_fields, 7093 /* bits */ 32, 7094 /* flags */ 0, 7095 }, 7096 #endif /* chips */ 7097 7098 #if defined(BCM_56840_B0) 7099 { /* SOC_FORMAT_INT_CMIC_CORE_PLL3_CTRL_STATUS_REGISTER_3fmt */ 7100 /* format CMIC_CORE_PLL3_CTRL_STATUS_REGISTER_3fmt */ 7101 /* nFields */ 10, 7102 /* *fields */ soc_CMIC_CORE_PLL3_CTRL_STATUS_REGISTER_3fmt_fields, 7103 /* bits */ 32, 7104 /* flags */ 0, 7105 }, 7106 #endif /* chips */ 7107 7108 #if defined(BCM_56370_A0) 7109 { /* SOC_FORMAT_INT_CMIC_CORE_PLL3_CTRL_STATUS_REGISTER_2_BCM56370_A0fmt */ 7110 /* format CMIC_CORE_PLL3_CTRL_STATUS_REGISTER_2fmt */ 7111 /* nFields */ 10, 7112 /* *fields */ soc_CMIC_CORE_PLL3_CTRL_STATUS_REGISTER_2_BCM56960_A0fmt_fields, 7113 /* bits */ 32, 7114 /* flags */ 0, 7115 }, 7116 #endif /* chips */ 7117 7118 #if defined(BCM_56770_A0) 7119 { /* SOC_FORMAT_INT_CMIC_CORE_PLL3_CTRL_STATUS_REGISTER_2_BCM56770_A0fmt */ 7120 /* format CMIC_CORE_PLL3_CTRL_STATUS_REGISTER_2fmt */ 7121 /* nFields */ 10, 7122 /* *fields */ soc_CMIC_CORE_PLL3_CTRL_STATUS_REGISTER_2_BCM56960_A0fmt_fields, 7123 /* bits */ 32, 7124 /* flags */ 0, 7125 }, 7126 #endif /* chips */ 7127 7128 #if defined(BCM_56850_A0) 7129 { /* SOC_FORMAT_INT_CMIC_CORE_PLL3_CTRL_STATUS_REGISTER_2_BCM56850_A0fmt */ 7130 /* format CMIC_CORE_PLL3_CTRL_STATUS_REGISTER_2fmt */ 7131 /* nFields */ 10, 7132 /* *fields */ soc_CMIC_CORE_PLL3_CTRL_STATUS_REGISTER_2_BCM56850_A0fmt_fields, 7133 /* bits */ 32, 7134 /* flags */ 0, 7135 }, 7136 #endif /* chips */ 7137 7138 #if defined(BCM_56860_A0) 7139 { /* SOC_FORMAT_INT_CMIC_CORE_PLL3_CTRL_STATUS_REGISTER_2_BCM56860_A0fmt */ 7140 /* format CMIC_CORE_PLL3_CTRL_STATUS_REGISTER_2fmt */ 7141 /* nFields */ 10, 7142 /* *fields */ soc_CMIC_CORE_PLL3_CTRL_STATUS_REGISTER_2_BCM56850_A0fmt_fields, 7143 /* bits */ 32, 7144 /* flags */ 0, 7145 }, 7146 #endif /* chips */ 7147 7148 #if defined(BCM_56870_A0) 7149 { /* SOC_FORMAT_INT_CMIC_CORE_PLL3_CTRL_STATUS_REGISTER_2_BCM56870_A0fmt */ 7150 /* format CMIC_CORE_PLL3_CTRL_STATUS_REGISTER_2fmt */ 7151 /* nFields */ 10, 7152 /* *fields */ soc_CMIC_CORE_PLL3_CTRL_STATUS_REGISTER_2_BCM56960_A0fmt_fields, 7153 /* bits */ 32, 7154 /* flags */ 0, 7155 }, 7156 #endif /* chips */ 7157 7158 #if defined(BCM_56960_A0) 7159 { /* SOC_FORMAT_INT_CMIC_CORE_PLL3_CTRL_STATUS_REGISTER_2_BCM56960_A0fmt */ 7160 /* format CMIC_CORE_PLL3_CTRL_STATUS_REGISTER_2fmt */ 7161 /* nFields */ 10, 7162 /* *fields */ soc_CMIC_CORE_PLL3_CTRL_STATUS_REGISTER_2_BCM56960_A0fmt_fields, 7163 /* bits */ 32, 7164 /* flags */ 0, 7165 }, 7166 #endif /* chips */ 7167 7168 #if defined(BCM_56965_A0) 7169 { /* SOC_FORMAT_INT_CMIC_CORE_PLL3_CTRL_STATUS_REGISTER_2_BCM56965_A0fmt */ 7170 /* format CMIC_CORE_PLL3_CTRL_STATUS_REGISTER_2fmt */ 7171 /* nFields */ 10, 7172 /* *fields */ soc_CMIC_CORE_PLL3_CTRL_STATUS_REGISTER_2_BCM56960_A0fmt_fields, 7173 /* bits */ 32, 7174 /* flags */ 0, 7175 }, 7176 #endif /* chips */ 7177 7178 #if defined(BCM_56970_A0) 7179 { /* SOC_FORMAT_INT_CMIC_CORE_PLL3_CTRL_STATUS_REGISTER_2_BCM56970_A0fmt */ 7180 /* format CMIC_CORE_PLL3_CTRL_STATUS_REGISTER_2fmt */ 7181 /* nFields */ 10, 7182 /* *fields */ soc_CMIC_CORE_PLL3_CTRL_STATUS_REGISTER_2_BCM56960_A0fmt_fields, 7183 /* bits */ 32, 7184 /* flags */ 0, 7185 }, 7186 #endif /* chips */ 7187 7188 #if defined(BCM_56370_A0) 7189 { /* SOC_FORMAT_INT_CMIC_CORE_PLL3_CTRL_STATUS_REGISTER_3_BCM56370_A0fmt */ 7190 /* format CMIC_CORE_PLL3_CTRL_STATUS_REGISTER_3fmt */ 7191 /* nFields */ 10, 7192 /* *fields */ soc_CMIC_CORE_PLL3_CTRL_STATUS_REGISTER_3_BCM56960_A0fmt_fields, 7193 /* bits */ 32, 7194 /* flags */ 0, 7195 }, 7196 #endif /* chips */ 7197 7198 #if defined(BCM_56770_A0) 7199 { /* SOC_FORMAT_INT_CMIC_CORE_PLL3_CTRL_STATUS_REGISTER_3_BCM56770_A0fmt */ 7200 /* format CMIC_CORE_PLL3_CTRL_STATUS_REGISTER_3fmt */ 7201 /* nFields */ 10, 7202 /* *fields */ soc_CMIC_CORE_PLL3_CTRL_STATUS_REGISTER_3_BCM56960_A0fmt_fields, 7203 /* bits */ 32, 7204 /* flags */ 0, 7205 }, 7206 #endif /* chips */ 7207 7208 #if defined(BCM_56850_A0) 7209 { /* SOC_FORMAT_INT_CMIC_CORE_PLL3_CTRL_STATUS_REGISTER_3_BCM56850_A0fmt */ 7210 /* format CMIC_CORE_PLL3_CTRL_STATUS_REGISTER_3fmt */ 7211 /* nFields */ 10, 7212 /* *fields */ soc_CMIC_CORE_PLL3_CTRL_STATUS_REGISTER_3_BCM56850_A0fmt_fields, 7213 /* bits */ 32, 7214 /* flags */ 0, 7215 }, 7216 #endif /* chips */ 7217 7218 #if defined(BCM_56860_A0) 7219 { /* SOC_FORMAT_INT_CMIC_CORE_PLL3_CTRL_STATUS_REGISTER_3_BCM56860_A0fmt */ 7220 /* format CMIC_CORE_PLL3_CTRL_STATUS_REGISTER_3fmt */ 7221 /* nFields */ 10, 7222 /* *fields */ soc_CMIC_CORE_PLL3_CTRL_STATUS_REGISTER_3_BCM56850_A0fmt_fields, 7223 /* bits */ 32, 7224 /* flags */ 0, 7225 }, 7226 #endif /* chips */ 7227 7228 #if defined(BCM_56870_A0) 7229 { /* SOC_FORMAT_INT_CMIC_CORE_PLL3_CTRL_STATUS_REGISTER_3_BCM56870_A0fmt */ 7230 /* format CMIC_CORE_PLL3_CTRL_STATUS_REGISTER_3fmt */ 7231 /* nFields */ 10, 7232 /* *fields */ soc_CMIC_CORE_PLL3_CTRL_STATUS_REGISTER_3_BCM56960_A0fmt_fields, 7233 /* bits */ 32, 7234 /* flags */ 0, 7235 }, 7236 #endif /* chips */ 7237 7238 #if defined(BCM_56960_A0) 7239 { /* SOC_FORMAT_INT_CMIC_CORE_PLL3_CTRL_STATUS_REGISTER_3_BCM56960_A0fmt */ 7240 /* format CMIC_CORE_PLL3_CTRL_STATUS_REGISTER_3fmt */ 7241 /* nFields */ 10, 7242 /* *fields */ soc_CMIC_CORE_PLL3_CTRL_STATUS_REGISTER_3_BCM56960_A0fmt_fields, 7243 /* bits */ 32, 7244 /* flags */ 0, 7245 }, 7246 #endif /* chips */ 7247 7248 #if defined(BCM_56965_A0) 7249 { /* SOC_FORMAT_INT_CMIC_CORE_PLL3_CTRL_STATUS_REGISTER_3_BCM56965_A0fmt */ 7250 /* format CMIC_CORE_PLL3_CTRL_STATUS_REGISTER_3fmt */ 7251 /* nFields */ 10, 7252 /* *fields */ soc_CMIC_CORE_PLL3_CTRL_STATUS_REGISTER_3_BCM56960_A0fmt_fields, 7253 /* bits */ 32, 7254 /* flags */ 0, 7255 }, 7256 #endif /* chips */ 7257 7258 #if defined(BCM_56970_A0) 7259 { /* SOC_FORMAT_INT_CMIC_CORE_PLL3_CTRL_STATUS_REGISTER_3_BCM56970_A0fmt */ 7260 /* format CMIC_CORE_PLL3_CTRL_STATUS_REGISTER_3fmt */ 7261 /* nFields */ 10, 7262 /* *fields */ soc_CMIC_CORE_PLL3_CTRL_STATUS_REGISTER_3_BCM56960_A0fmt_fields, 7263 /* bits */ 32, 7264 /* flags */ 0, 7265 }, 7266 #endif /* chips */ 7267 7268 #if defined(BCM_56440_A0) || defined(BCM_56440_B0) 7269 { /* SOC_FORMAT_INT_CMIC_FASTRD_TO_RQE_INFOfmt */ 7270 /* format CMIC_FASTRD_TO_RQE_INFOfmt */ 7271 /* nFields */ 1, 7272 /* *fields */ soc_CMIC_FASTRD_TO_RQE_INFOfmt_fields, 7273 /* bits */ 12, 7274 /* flags */ 0, 7275 }, 7276 #endif /* chips */ 7277 7278 #if defined(BCM_56260_A0) 7279 { /* SOC_FORMAT_INT_CMIC_FASTRD_TO_RQE_INFO_BCM56260_A0fmt */ 7280 /* format CMIC_FASTRD_TO_RQE_INFOfmt */ 7281 /* nFields */ 1, 7282 /* *fields */ soc_CMIC_FASTRD_TO_RQE_INFO_BCM56260_A0fmt_fields, 7283 /* bits */ 12, 7284 /* flags */ 0, 7285 }, 7286 #endif /* chips */ 7287 7288 #if defined(BCM_56260_B0) 7289 { /* SOC_FORMAT_INT_CMIC_FASTRD_TO_RQE_INFO_BCM56260_B0fmt */ 7290 /* format CMIC_FASTRD_TO_RQE_INFOfmt */ 7291 /* nFields */ 1, 7292 /* *fields */ soc_CMIC_FASTRD_TO_RQE_INFO_BCM56260_A0fmt_fields, 7293 /* bits */ 12, 7294 /* flags */ 0, 7295 }, 7296 #endif /* chips */ 7297 7298 #if defined(BCM_56270_A0) 7299 { /* SOC_FORMAT_INT_CMIC_FASTRD_TO_RQE_INFO_BCM56270_A0fmt */ 7300 /* format CMIC_FASTRD_TO_RQE_INFOfmt */ 7301 /* nFields */ 1, 7302 /* *fields */ soc_CMIC_FASTRD_TO_RQE_INFO_BCM56260_A0fmt_fields, 7303 /* bits */ 12, 7304 /* flags */ 0, 7305 }, 7306 #endif /* chips */ 7307 7308 #if defined(BCM_56450_A0) 7309 { /* SOC_FORMAT_INT_CMIC_FASTRD_TO_RQE_INFO_BCM56450_A0fmt */ 7310 /* format CMIC_FASTRD_TO_RQE_INFOfmt */ 7311 /* nFields */ 1, 7312 /* *fields */ soc_CMIC_FASTRD_TO_RQE_INFO_BCM56450_A0fmt_fields, 7313 /* bits */ 12, 7314 /* flags */ 0, 7315 }, 7316 #endif /* chips */ 7317 7318 #if defined(BCM_56450_B0) 7319 { /* SOC_FORMAT_INT_CMIC_FASTRD_TO_RQE_INFO_BCM56450_B0fmt */ 7320 /* format CMIC_FASTRD_TO_RQE_INFOfmt */ 7321 /* nFields */ 1, 7322 /* *fields */ soc_CMIC_FASTRD_TO_RQE_INFO_BCM56450_A0fmt_fields, 7323 /* bits */ 12, 7324 /* flags */ 0, 7325 }, 7326 #endif /* chips */ 7327 7328 #if defined(BCM_56450_B1) 7329 { /* SOC_FORMAT_INT_CMIC_FASTRD_TO_RQE_INFO_BCM56450_B1fmt */ 7330 /* format CMIC_FASTRD_TO_RQE_INFOfmt */ 7331 /* nFields */ 1, 7332 /* *fields */ soc_CMIC_FASTRD_TO_RQE_INFO_BCM56450_A0fmt_fields, 7333 /* bits */ 12, 7334 /* flags */ 0, 7335 }, 7336 #endif /* chips */ 7337 7338 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \ 7339 defined(BCM_56634_B0) || defined(BCM_56680_A0) || \ 7340 defined(BCM_56680_B0) || defined(BCM_56685_A0) || \ 7341 defined(BCM_56685_B0) 7342 { /* SOC_FORMAT_INT_CMIC_FUNC_INTR_STATUSfmt */ 7343 /* format CMIC_FUNC_INTR_STATUSfmt */ 7344 /* nFields */ 8, 7345 /* *fields */ soc_CMIC_FUNC_INTR_STATUSfmt_fields, 7346 /* bits */ 8, 7347 /* flags */ 0, 7348 }, 7349 #endif /* chips */ 7350 7351 #if defined(BCM_53400_A0) 7352 { /* SOC_FORMAT_INT_CMIC_FUNC_INTR_STATUS_BCM53400_A0fmt */ 7353 /* format CMIC_FUNC_INTR_STATUSfmt */ 7354 /* nFields */ 3, 7355 /* *fields */ soc_CMIC_FUNC_INTR_STATUS_BCM53400_A0fmt_fields, 7356 /* bits */ 8, 7357 /* flags */ 0, 7358 }, 7359 #endif /* chips */ 7360 7361 #if defined(BCM_53540_A0) 7362 { /* SOC_FORMAT_INT_CMIC_FUNC_INTR_STATUS_BCM53540_A0fmt */ 7363 /* format CMIC_FUNC_INTR_STATUSfmt */ 7364 /* nFields */ 4, 7365 /* *fields */ soc_CMIC_FUNC_INTR_STATUS_BCM56160_A0fmt_fields, 7366 /* bits */ 8, 7367 /* flags */ 0, 7368 }, 7369 #endif /* chips */ 7370 7371 #if defined(BCM_53570_A0) 7372 { /* SOC_FORMAT_INT_CMIC_FUNC_INTR_STATUS_BCM53570_A0fmt */ 7373 /* format CMIC_FUNC_INTR_STATUSfmt */ 7374 /* nFields */ 5, 7375 /* *fields */ soc_CMIC_FUNC_INTR_STATUS_BCM53570_A0fmt_fields, 7376 /* bits */ 8, 7377 /* flags */ 0, 7378 }, 7379 #endif /* chips */ 7380 7381 #if defined(BCM_53570_B0) 7382 { /* SOC_FORMAT_INT_CMIC_FUNC_INTR_STATUS_BCM53570_B0fmt */ 7383 /* format CMIC_FUNC_INTR_STATUSfmt */ 7384 /* nFields */ 6, 7385 /* *fields */ soc_CMIC_FUNC_INTR_STATUS_BCM53570_B0fmt_fields, 7386 /* bits */ 8, 7387 /* flags */ 0, 7388 }, 7389 #endif /* chips */ 7390 7391 #if defined(BCM_56142_A0) 7392 { /* SOC_FORMAT_INT_CMIC_FUNC_INTR_STATUS_BCM56142_A0fmt */ 7393 /* format CMIC_FUNC_INTR_STATUSfmt */ 7394 /* nFields */ 3, 7395 /* *fields */ soc_CMIC_FUNC_INTR_STATUS_BCM56334_A0fmt_fields, 7396 /* bits */ 8, 7397 /* flags */ 0, 7398 }, 7399 #endif /* chips */ 7400 7401 #if defined(BCM_56150_A0) 7402 { /* SOC_FORMAT_INT_CMIC_FUNC_INTR_STATUS_BCM56150_A0fmt */ 7403 /* format CMIC_FUNC_INTR_STATUSfmt */ 7404 /* nFields */ 3, 7405 /* *fields */ soc_CMIC_FUNC_INTR_STATUS_BCM56450_A0fmt_fields, 7406 /* bits */ 8, 7407 /* flags */ 0, 7408 }, 7409 #endif /* chips */ 7410 7411 #if defined(BCM_56160_A0) 7412 { /* SOC_FORMAT_INT_CMIC_FUNC_INTR_STATUS_BCM56160_A0fmt */ 7413 /* format CMIC_FUNC_INTR_STATUSfmt */ 7414 /* nFields */ 4, 7415 /* *fields */ soc_CMIC_FUNC_INTR_STATUS_BCM56160_A0fmt_fields, 7416 /* bits */ 8, 7417 /* flags */ 0, 7418 }, 7419 #endif /* chips */ 7420 7421 #if defined(BCM_56334_A0) 7422 { /* SOC_FORMAT_INT_CMIC_FUNC_INTR_STATUS_BCM56334_A0fmt */ 7423 /* format CMIC_FUNC_INTR_STATUSfmt */ 7424 /* nFields */ 3, 7425 /* *fields */ soc_CMIC_FUNC_INTR_STATUS_BCM56334_A0fmt_fields, 7426 /* bits */ 8, 7427 /* flags */ 0, 7428 }, 7429 #endif /* chips */ 7430 7431 #if defined(BCM_56334_B0) 7432 { /* SOC_FORMAT_INT_CMIC_FUNC_INTR_STATUS_BCM56334_B0fmt */ 7433 /* format CMIC_FUNC_INTR_STATUSfmt */ 7434 /* nFields */ 3, 7435 /* *fields */ soc_CMIC_FUNC_INTR_STATUS_BCM56334_A0fmt_fields, 7436 /* bits */ 8, 7437 /* flags */ 0, 7438 }, 7439 #endif /* chips */ 7440 7441 #if defined(BCM_56340_A0) 7442 { /* SOC_FORMAT_INT_CMIC_FUNC_INTR_STATUS_BCM56340_A0fmt */ 7443 /* format CMIC_FUNC_INTR_STATUSfmt */ 7444 /* nFields */ 7, 7445 /* *fields */ soc_CMIC_FUNC_INTR_STATUS_BCM56340_A0fmt_fields, 7446 /* bits */ 8, 7447 /* flags */ 0, 7448 }, 7449 #endif /* chips */ 7450 7451 #if defined(BCM_56440_A0) 7452 { /* SOC_FORMAT_INT_CMIC_FUNC_INTR_STATUS_BCM56440_A0fmt */ 7453 /* format CMIC_FUNC_INTR_STATUSfmt */ 7454 /* nFields */ 4, 7455 /* *fields */ soc_CMIC_FUNC_INTR_STATUS_BCM56440_A0fmt_fields, 7456 /* bits */ 8, 7457 /* flags */ 0, 7458 }, 7459 #endif /* chips */ 7460 7461 #if defined(BCM_56440_B0) 7462 { /* SOC_FORMAT_INT_CMIC_FUNC_INTR_STATUS_BCM56440_B0fmt */ 7463 /* format CMIC_FUNC_INTR_STATUSfmt */ 7464 /* nFields */ 4, 7465 /* *fields */ soc_CMIC_FUNC_INTR_STATUS_BCM56440_A0fmt_fields, 7466 /* bits */ 8, 7467 /* flags */ 0, 7468 }, 7469 #endif /* chips */ 7470 7471 #if defined(BCM_56450_A0) 7472 { /* SOC_FORMAT_INT_CMIC_FUNC_INTR_STATUS_BCM56450_A0fmt */ 7473 /* format CMIC_FUNC_INTR_STATUSfmt */ 7474 /* nFields */ 3, 7475 /* *fields */ soc_CMIC_FUNC_INTR_STATUS_BCM56450_A0fmt_fields, 7476 /* bits */ 8, 7477 /* flags */ 0, 7478 }, 7479 #endif /* chips */ 7480 7481 #if defined(BCM_56450_B0) 7482 { /* SOC_FORMAT_INT_CMIC_FUNC_INTR_STATUS_BCM56450_B0fmt */ 7483 /* format CMIC_FUNC_INTR_STATUSfmt */ 7484 /* nFields */ 3, 7485 /* *fields */ soc_CMIC_FUNC_INTR_STATUS_BCM56450_A0fmt_fields, 7486 /* bits */ 8, 7487 /* flags */ 0, 7488 }, 7489 #endif /* chips */ 7490 7491 #if defined(BCM_56450_B1) 7492 { /* SOC_FORMAT_INT_CMIC_FUNC_INTR_STATUS_BCM56450_B1fmt */ 7493 /* format CMIC_FUNC_INTR_STATUSfmt */ 7494 /* nFields */ 3, 7495 /* *fields */ soc_CMIC_FUNC_INTR_STATUS_BCM56450_A0fmt_fields, 7496 /* bits */ 8, 7497 /* flags */ 0, 7498 }, 7499 #endif /* chips */ 7500 7501 #if defined(BCM_56524_A0) 7502 { /* SOC_FORMAT_INT_CMIC_FUNC_INTR_STATUS_BCM56524_A0fmt */ 7503 /* format CMIC_FUNC_INTR_STATUSfmt */ 7504 /* nFields */ 8, 7505 /* *fields */ soc_CMIC_FUNC_INTR_STATUSfmt_fields, 7506 /* bits */ 8, 7507 /* flags */ 0, 7508 }, 7509 #endif /* chips */ 7510 7511 #if defined(BCM_56524_B0) 7512 { /* SOC_FORMAT_INT_CMIC_FUNC_INTR_STATUS_BCM56524_B0fmt */ 7513 /* format CMIC_FUNC_INTR_STATUSfmt */ 7514 /* nFields */ 8, 7515 /* *fields */ soc_CMIC_FUNC_INTR_STATUSfmt_fields, 7516 /* bits */ 8, 7517 /* flags */ 0, 7518 }, 7519 #endif /* chips */ 7520 7521 #if defined(BCM_56634_A0) 7522 { /* SOC_FORMAT_INT_CMIC_FUNC_INTR_STATUS_BCM56634_A0fmt */ 7523 /* format CMIC_FUNC_INTR_STATUSfmt */ 7524 /* nFields */ 8, 7525 /* *fields */ soc_CMIC_FUNC_INTR_STATUSfmt_fields, 7526 /* bits */ 8, 7527 /* flags */ 0, 7528 }, 7529 #endif /* chips */ 7530 7531 #if defined(BCM_56640_A0) 7532 { /* SOC_FORMAT_INT_CMIC_FUNC_INTR_STATUS_BCM56640_A0fmt */ 7533 /* format CMIC_FUNC_INTR_STATUSfmt */ 7534 /* nFields */ 8, 7535 /* *fields */ soc_CMIC_FUNC_INTR_STATUS_BCM56640_A0fmt_fields, 7536 /* bits */ 8, 7537 /* flags */ 0, 7538 }, 7539 #endif /* chips */ 7540 7541 #if defined(BCM_56840_A0) 7542 { /* SOC_FORMAT_INT_CMIC_FUNC_INTR_STATUS_BCM56840_A0fmt */ 7543 /* format CMIC_FUNC_INTR_STATUSfmt */ 7544 /* nFields */ 2, 7545 /* *fields */ soc_CMIC_FUNC_INTR_STATUS_BCM56840_A0fmt_fields, 7546 /* bits */ 2, 7547 /* flags */ 0, 7548 }, 7549 #endif /* chips */ 7550 7551 #if defined(BCM_56840_B0) 7552 { /* SOC_FORMAT_INT_CMIC_FUNC_INTR_STATUS_BCM56840_B0fmt */ 7553 /* format CMIC_FUNC_INTR_STATUSfmt */ 7554 /* nFields */ 2, 7555 /* *fields */ soc_CMIC_FUNC_INTR_STATUS_BCM56840_A0fmt_fields, 7556 /* bits */ 2, 7557 /* flags */ 0, 7558 }, 7559 #endif /* chips */ 7560 7561 #if defined(BCM_56850_A0) 7562 { /* SOC_FORMAT_INT_CMIC_FUNC_INTR_STATUS_BCM56850_A0fmt */ 7563 /* format CMIC_FUNC_INTR_STATUSfmt */ 7564 /* nFields */ 5, 7565 /* *fields */ soc_CMIC_FUNC_INTR_STATUS_BCM56850_A0fmt_fields, 7566 /* bits */ 6, 7567 /* flags */ 0, 7568 }, 7569 #endif /* chips */ 7570 7571 #if defined(BCM_56860_A0) 7572 { /* SOC_FORMAT_INT_CMIC_FUNC_INTR_STATUS_BCM56860_A0fmt */ 7573 /* format CMIC_FUNC_INTR_STATUSfmt */ 7574 /* nFields */ 6, 7575 /* *fields */ soc_CMIC_FUNC_INTR_STATUS_BCM56860_A0fmt_fields, 7576 /* bits */ 6, 7577 /* flags */ 0, 7578 }, 7579 #endif /* chips */ 7580 7581 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 7582 defined(BCM_56870_A0) || defined(BCM_56980_A0) || \ 7583 defined(BCM_56980_B0) 7584 { /* SOC_FORMAT_INT_CMIC_INTERUPTSfmt */ 7585 /* format CMIC_INTERUPTSfmt */ 7586 /* nFields */ 106, 7587 /* *fields */ soc_CMIC_INTERUPTSfmt_fields, 7588 /* bits */ 128, 7589 /* flags */ 0, 7590 }, 7591 #endif /* chips */ 7592 7593 #if defined(BCM_56260_A0) || defined(BCM_56260_B0) 7594 { /* SOC_FORMAT_INT_CMIC_INTR_STATUSfmt */ 7595 /* format CMIC_INTR_STATUSfmt */ 7596 /* nFields */ 24, 7597 /* *fields */ soc_CMIC_INTR_STATUSfmt_fields, 7598 /* bits */ 90, 7599 /* flags */ 0, 7600 }, 7601 #endif /* chips */ 7602 7603 #if defined(BCM_56270_A0) 7604 { /* SOC_FORMAT_INT_CMIC_INTR_STATUS_BCM56270_A0fmt */ 7605 /* format CMIC_INTR_STATUSfmt */ 7606 /* nFields */ 19, 7607 /* *fields */ soc_CMIC_INTR_STATUS_BCM56270_A0fmt_fields, 7608 /* bits */ 90, 7609 /* flags */ 0, 7610 }, 7611 #endif /* chips */ 7612 7613 #if defined(BCM_88732_A0) 7614 { /* SOC_FORMAT_INT_CMIC_IRQ_STAT_1fmt */ 7615 /* format CMIC_IRQ_STAT_1fmt */ 7616 /* nFields */ 17, 7617 /* *fields */ soc_CMIC_IRQ_STAT_1fmt_fields, 7618 /* bits */ 32, 7619 /* flags */ 0, 7620 }, 7621 #endif /* chips */ 7622 7623 #if defined(BCM_56820_A0) 7624 { /* SOC_FORMAT_INT_CMIC_MISC_CONTROLfmt */ 7625 /* format CMIC_MISC_CONTROLfmt */ 7626 /* nFields */ 8, 7627 /* *fields */ soc_CMIC_MISC_CONTROLfmt_fields, 7628 /* bits */ 32, 7629 /* flags */ 0, 7630 }, 7631 #endif /* chips */ 7632 7633 #if defined(BCM_56260_A0) 7634 { /* SOC_FORMAT_INT_CMIC_MISC_CONTROL_BCM56260_A0fmt */ 7635 /* format CMIC_MISC_CONTROLfmt */ 7636 /* nFields */ 19, 7637 /* *fields */ soc_CMIC_MISC_CONTROL_BCM56260_A0fmt_fields, 7638 /* bits */ 32, 7639 /* flags */ 0, 7640 }, 7641 #endif /* chips */ 7642 7643 #if defined(BCM_56260_B0) 7644 { /* SOC_FORMAT_INT_CMIC_MISC_CONTROL_BCM56260_B0fmt */ 7645 /* format CMIC_MISC_CONTROLfmt */ 7646 /* nFields */ 19, 7647 /* *fields */ soc_CMIC_MISC_CONTROL_BCM56260_A0fmt_fields, 7648 /* bits */ 32, 7649 /* flags */ 0, 7650 }, 7651 #endif /* chips */ 7652 7653 #if defined(BCM_56270_A0) 7654 { /* SOC_FORMAT_INT_CMIC_MISC_CONTROL_BCM56270_A0fmt */ 7655 /* format CMIC_MISC_CONTROLfmt */ 7656 /* nFields */ 19, 7657 /* *fields */ soc_CMIC_MISC_CONTROL_BCM56260_A0fmt_fields, 7658 /* bits */ 32, 7659 /* flags */ 0, 7660 }, 7661 #endif /* chips */ 7662 7663 #if defined(BCM_56340_A0) 7664 { /* SOC_FORMAT_INT_CMIC_MISC_CONTROL_BCM56340_A0fmt */ 7665 /* format CMIC_MISC_CONTROLfmt */ 7666 /* nFields */ 1, 7667 /* *fields */ soc_CMIC_MISC_CONTROL_BCM56640_A0fmt_fields, 7668 /* bits */ 32, 7669 /* flags */ 0, 7670 }, 7671 #endif /* chips */ 7672 7673 #if defined(BCM_56450_A0) 7674 { /* SOC_FORMAT_INT_CMIC_MISC_CONTROL_BCM56450_A0fmt */ 7675 /* format CMIC_MISC_CONTROLfmt */ 7676 /* nFields */ 19, 7677 /* *fields */ soc_CMIC_MISC_CONTROL_BCM56450_A0fmt_fields, 7678 /* bits */ 32, 7679 /* flags */ 0, 7680 }, 7681 #endif /* chips */ 7682 7683 #if defined(BCM_56450_B0) 7684 { /* SOC_FORMAT_INT_CMIC_MISC_CONTROL_BCM56450_B0fmt */ 7685 /* format CMIC_MISC_CONTROLfmt */ 7686 /* nFields */ 19, 7687 /* *fields */ soc_CMIC_MISC_CONTROL_BCM56450_A0fmt_fields, 7688 /* bits */ 32, 7689 /* flags */ 0, 7690 }, 7691 #endif /* chips */ 7692 7693 #if defined(BCM_56450_B1) 7694 { /* SOC_FORMAT_INT_CMIC_MISC_CONTROL_BCM56450_B1fmt */ 7695 /* format CMIC_MISC_CONTROLfmt */ 7696 /* nFields */ 19, 7697 /* *fields */ soc_CMIC_MISC_CONTROL_BCM56450_A0fmt_fields, 7698 /* bits */ 32, 7699 /* flags */ 0, 7700 }, 7701 #endif /* chips */ 7702 7703 #if defined(BCM_56640_A0) 7704 { /* SOC_FORMAT_INT_CMIC_MISC_CONTROL_BCM56640_A0fmt */ 7705 /* format CMIC_MISC_CONTROLfmt */ 7706 /* nFields */ 1, 7707 /* *fields */ soc_CMIC_MISC_CONTROL_BCM56640_A0fmt_fields, 7708 /* bits */ 32, 7709 /* flags */ 0, 7710 }, 7711 #endif /* chips */ 7712 7713 #if defined(BCM_56725_A0) 7714 { /* SOC_FORMAT_INT_CMIC_MISC_CONTROL_BCM56725_A0fmt */ 7715 /* format CMIC_MISC_CONTROLfmt */ 7716 /* nFields */ 8, 7717 /* *fields */ soc_CMIC_MISC_CONTROLfmt_fields, 7718 /* bits */ 32, 7719 /* flags */ 0, 7720 }, 7721 #endif /* chips */ 7722 7723 #if defined(BCM_56840_A0) 7724 { /* SOC_FORMAT_INT_CMIC_MISC_CONTROL_BCM56840_A0fmt */ 7725 /* format CMIC_MISC_CONTROLfmt */ 7726 /* nFields */ 19, 7727 /* *fields */ soc_CMIC_MISC_CONTROL_BCM56840_A0fmt_fields, 7728 /* bits */ 32, 7729 /* flags */ 0, 7730 }, 7731 #endif /* chips */ 7732 7733 #if defined(BCM_56840_B0) 7734 { /* SOC_FORMAT_INT_CMIC_MISC_CONTROL_BCM56840_B0fmt */ 7735 /* format CMIC_MISC_CONTROLfmt */ 7736 /* nFields */ 21, 7737 /* *fields */ soc_CMIC_MISC_CONTROL_BCM56840_B0fmt_fields, 7738 /* bits */ 32, 7739 /* flags */ 0, 7740 }, 7741 #endif /* chips */ 7742 7743 #if defined(BCM_88732_A0) 7744 { /* SOC_FORMAT_INT_CMIC_MISC_CONTROL_BCM88732_A0fmt */ 7745 /* format CMIC_MISC_CONTROLfmt */ 7746 /* nFields */ 11, 7747 /* *fields */ soc_CMIC_MISC_CONTROL_BCM88732_A0fmt_fields, 7748 /* bits */ 32, 7749 /* flags */ 0, 7750 }, 7751 #endif /* chips */ 7752 7753 #if defined(BCM_56820_A0) 7754 { /* SOC_FORMAT_INT_CMIC_MISC_STATUSfmt */ 7755 /* format CMIC_MISC_STATUSfmt */ 7756 /* nFields */ 11, 7757 /* *fields */ soc_CMIC_MISC_STATUSfmt_fields, 7758 /* bits */ 32, 7759 /* flags */ 0, 7760 }, 7761 #endif /* chips */ 7762 7763 #if defined(BCM_56260_A0) 7764 { /* SOC_FORMAT_INT_CMIC_MISC_STATUS_BCM56260_A0fmt */ 7765 /* format CMIC_MISC_STATUSfmt */ 7766 /* nFields */ 14, 7767 /* *fields */ soc_CMIC_MISC_STATUS_BCM56960_A0fmt_fields, 7768 /* bits */ 32, 7769 /* flags */ 0, 7770 }, 7771 #endif /* chips */ 7772 7773 #if defined(BCM_56260_B0) 7774 { /* SOC_FORMAT_INT_CMIC_MISC_STATUS_BCM56260_B0fmt */ 7775 /* format CMIC_MISC_STATUSfmt */ 7776 /* nFields */ 14, 7777 /* *fields */ soc_CMIC_MISC_STATUS_BCM56960_A0fmt_fields, 7778 /* bits */ 32, 7779 /* flags */ 0, 7780 }, 7781 #endif /* chips */ 7782 7783 #if defined(BCM_56270_A0) 7784 { /* SOC_FORMAT_INT_CMIC_MISC_STATUS_BCM56270_A0fmt */ 7785 /* format CMIC_MISC_STATUSfmt */ 7786 /* nFields */ 14, 7787 /* *fields */ soc_CMIC_MISC_STATUS_BCM56960_A0fmt_fields, 7788 /* bits */ 32, 7789 /* flags */ 0, 7790 }, 7791 #endif /* chips */ 7792 7793 #if defined(BCM_56340_A0) 7794 { /* SOC_FORMAT_INT_CMIC_MISC_STATUS_BCM56340_A0fmt */ 7795 /* format CMIC_MISC_STATUSfmt */ 7796 /* nFields */ 1, 7797 /* *fields */ soc_CMIC_MISC_STATUS_BCM56640_A0fmt_fields, 7798 /* bits */ 32, 7799 /* flags */ 0, 7800 }, 7801 #endif /* chips */ 7802 7803 #if defined(BCM_56370_A0) 7804 { /* SOC_FORMAT_INT_CMIC_MISC_STATUS_BCM56370_A0fmt */ 7805 /* format CMIC_MISC_STATUSfmt */ 7806 /* nFields */ 14, 7807 /* *fields */ soc_CMIC_MISC_STATUS_BCM56960_A0fmt_fields, 7808 /* bits */ 32, 7809 /* flags */ 0, 7810 }, 7811 #endif /* chips */ 7812 7813 #if defined(BCM_56450_A0) 7814 { /* SOC_FORMAT_INT_CMIC_MISC_STATUS_BCM56450_A0fmt */ 7815 /* format CMIC_MISC_STATUSfmt */ 7816 /* nFields */ 14, 7817 /* *fields */ soc_CMIC_MISC_STATUS_BCM56850_A0fmt_fields, 7818 /* bits */ 32, 7819 /* flags */ 0, 7820 }, 7821 #endif /* chips */ 7822 7823 #if defined(BCM_56450_B0) 7824 { /* SOC_FORMAT_INT_CMIC_MISC_STATUS_BCM56450_B0fmt */ 7825 /* format CMIC_MISC_STATUSfmt */ 7826 /* nFields */ 14, 7827 /* *fields */ soc_CMIC_MISC_STATUS_BCM56850_A0fmt_fields, 7828 /* bits */ 32, 7829 /* flags */ 0, 7830 }, 7831 #endif /* chips */ 7832 7833 #if defined(BCM_56450_B1) 7834 { /* SOC_FORMAT_INT_CMIC_MISC_STATUS_BCM56450_B1fmt */ 7835 /* format CMIC_MISC_STATUSfmt */ 7836 /* nFields */ 14, 7837 /* *fields */ soc_CMIC_MISC_STATUS_BCM56850_A0fmt_fields, 7838 /* bits */ 32, 7839 /* flags */ 0, 7840 }, 7841 #endif /* chips */ 7842 7843 #if defined(BCM_56640_A0) 7844 { /* SOC_FORMAT_INT_CMIC_MISC_STATUS_BCM56640_A0fmt */ 7845 /* format CMIC_MISC_STATUSfmt */ 7846 /* nFields */ 1, 7847 /* *fields */ soc_CMIC_MISC_STATUS_BCM56640_A0fmt_fields, 7848 /* bits */ 32, 7849 /* flags */ 0, 7850 }, 7851 #endif /* chips */ 7852 7853 #if defined(BCM_56725_A0) 7854 { /* SOC_FORMAT_INT_CMIC_MISC_STATUS_BCM56725_A0fmt */ 7855 /* format CMIC_MISC_STATUSfmt */ 7856 /* nFields */ 11, 7857 /* *fields */ soc_CMIC_MISC_STATUSfmt_fields, 7858 /* bits */ 32, 7859 /* flags */ 0, 7860 }, 7861 #endif /* chips */ 7862 7863 #if defined(BCM_56770_A0) 7864 { /* SOC_FORMAT_INT_CMIC_MISC_STATUS_BCM56770_A0fmt */ 7865 /* format CMIC_MISC_STATUSfmt */ 7866 /* nFields */ 14, 7867 /* *fields */ soc_CMIC_MISC_STATUS_BCM56960_A0fmt_fields, 7868 /* bits */ 32, 7869 /* flags */ 0, 7870 }, 7871 #endif /* chips */ 7872 7873 #if defined(BCM_56840_A0) 7874 { /* SOC_FORMAT_INT_CMIC_MISC_STATUS_BCM56840_A0fmt */ 7875 /* format CMIC_MISC_STATUSfmt */ 7876 /* nFields */ 14, 7877 /* *fields */ soc_CMIC_MISC_STATUS_BCM56840_A0fmt_fields, 7878 /* bits */ 32, 7879 /* flags */ 0, 7880 }, 7881 #endif /* chips */ 7882 7883 #if defined(BCM_56840_B0) 7884 { /* SOC_FORMAT_INT_CMIC_MISC_STATUS_BCM56840_B0fmt */ 7885 /* format CMIC_MISC_STATUSfmt */ 7886 /* nFields */ 14, 7887 /* *fields */ soc_CMIC_MISC_STATUS_BCM56840_A0fmt_fields, 7888 /* bits */ 32, 7889 /* flags */ 0, 7890 }, 7891 #endif /* chips */ 7892 7893 #if defined(BCM_56850_A0) 7894 { /* SOC_FORMAT_INT_CMIC_MISC_STATUS_BCM56850_A0fmt */ 7895 /* format CMIC_MISC_STATUSfmt */ 7896 /* nFields */ 14, 7897 /* *fields */ soc_CMIC_MISC_STATUS_BCM56850_A0fmt_fields, 7898 /* bits */ 32, 7899 /* flags */ 0, 7900 }, 7901 #endif /* chips */ 7902 7903 #if defined(BCM_56860_A0) 7904 { /* SOC_FORMAT_INT_CMIC_MISC_STATUS_BCM56860_A0fmt */ 7905 /* format CMIC_MISC_STATUSfmt */ 7906 /* nFields */ 14, 7907 /* *fields */ soc_CMIC_MISC_STATUS_BCM56850_A0fmt_fields, 7908 /* bits */ 32, 7909 /* flags */ 0, 7910 }, 7911 #endif /* chips */ 7912 7913 #if defined(BCM_56870_A0) 7914 { /* SOC_FORMAT_INT_CMIC_MISC_STATUS_BCM56870_A0fmt */ 7915 /* format CMIC_MISC_STATUSfmt */ 7916 /* nFields */ 14, 7917 /* *fields */ soc_CMIC_MISC_STATUS_BCM56960_A0fmt_fields, 7918 /* bits */ 32, 7919 /* flags */ 0, 7920 }, 7921 #endif /* chips */ 7922 7923 #if defined(BCM_56960_A0) 7924 { /* SOC_FORMAT_INT_CMIC_MISC_STATUS_BCM56960_A0fmt */ 7925 /* format CMIC_MISC_STATUSfmt */ 7926 /* nFields */ 14, 7927 /* *fields */ soc_CMIC_MISC_STATUS_BCM56960_A0fmt_fields, 7928 /* bits */ 32, 7929 /* flags */ 0, 7930 }, 7931 #endif /* chips */ 7932 7933 #if defined(BCM_56965_A0) 7934 { /* SOC_FORMAT_INT_CMIC_MISC_STATUS_BCM56965_A0fmt */ 7935 /* format CMIC_MISC_STATUSfmt */ 7936 /* nFields */ 14, 7937 /* *fields */ soc_CMIC_MISC_STATUS_BCM56960_A0fmt_fields, 7938 /* bits */ 32, 7939 /* flags */ 0, 7940 }, 7941 #endif /* chips */ 7942 7943 #if defined(BCM_56970_A0) 7944 { /* SOC_FORMAT_INT_CMIC_MISC_STATUS_BCM56970_A0fmt */ 7945 /* format CMIC_MISC_STATUSfmt */ 7946 /* nFields */ 14, 7947 /* *fields */ soc_CMIC_MISC_STATUS_BCM56960_A0fmt_fields, 7948 /* bits */ 32, 7949 /* flags */ 0, 7950 }, 7951 #endif /* chips */ 7952 7953 #if defined(BCM_88732_A0) 7954 { /* SOC_FORMAT_INT_CMIC_MISC_STATUS_BCM88732_A0fmt */ 7955 /* format CMIC_MISC_STATUSfmt */ 7956 /* nFields */ 12, 7957 /* *fields */ soc_CMIC_MISC_STATUS_BCM88732_A0fmt_fields, 7958 /* bits */ 32, 7959 /* flags */ 0, 7960 }, 7961 #endif /* chips */ 7962 7963 #if defined(BCM_56624_A0) || defined(BCM_56624_B0) || \ 7964 defined(BCM_56680_A0) || defined(BCM_56680_B0) 7965 { /* SOC_FORMAT_INT_CMIC_PARITY_INTR_STATUSfmt */ 7966 /* format CMIC_PARITY_INTR_STATUSfmt */ 7967 /* nFields */ 8, 7968 /* *fields */ soc_CMIC_PARITY_INTR_STATUSfmt_fields, 7969 /* bits */ 32, 7970 /* flags */ 0, 7971 }, 7972 #endif /* chips */ 7973 7974 #if defined(BCM_53400_A0) 7975 { /* SOC_FORMAT_INT_CMIC_PARITY_INTR_STATUS_BCM53400_A0fmt */ 7976 /* format CMIC_PARITY_INTR_STATUSfmt */ 7977 /* nFields */ 13, 7978 /* *fields */ soc_CMIC_PARITY_INTR_STATUS_BCM53400_A0fmt_fields, 7979 /* bits */ 32, 7980 /* flags */ 0, 7981 }, 7982 #endif /* chips */ 7983 7984 #if defined(BCM_53540_A0) 7985 { /* SOC_FORMAT_INT_CMIC_PARITY_INTR_STATUS_BCM53540_A0fmt */ 7986 /* format CMIC_PARITY_INTR_STATUSfmt */ 7987 /* nFields */ 11, 7988 /* *fields */ soc_CMIC_PARITY_INTR_STATUS_BCM53540_A0fmt_fields, 7989 /* bits */ 32, 7990 /* flags */ 0, 7991 }, 7992 #endif /* chips */ 7993 7994 #if defined(BCM_53570_A0) 7995 { /* SOC_FORMAT_INT_CMIC_PARITY_INTR_STATUS_BCM53570_A0fmt */ 7996 /* format CMIC_PARITY_INTR_STATUSfmt */ 7997 /* nFields */ 22, 7998 /* *fields */ soc_CMIC_PARITY_INTR_STATUS_BCM53570_A0fmt_fields, 7999 /* bits */ 32, 8000 /* flags */ 0, 8001 }, 8002 #endif /* chips */ 8003 8004 #if defined(BCM_53570_B0) 8005 { /* SOC_FORMAT_INT_CMIC_PARITY_INTR_STATUS_BCM53570_B0fmt */ 8006 /* format CMIC_PARITY_INTR_STATUSfmt */ 8007 /* nFields */ 22, 8008 /* *fields */ soc_CMIC_PARITY_INTR_STATUS_BCM53570_A0fmt_fields, 8009 /* bits */ 32, 8010 /* flags */ 0, 8011 }, 8012 #endif /* chips */ 8013 8014 #if defined(BCM_56142_A0) 8015 { /* SOC_FORMAT_INT_CMIC_PARITY_INTR_STATUS_BCM56142_A0fmt */ 8016 /* format CMIC_PARITY_INTR_STATUSfmt */ 8017 /* nFields */ 11, 8018 /* *fields */ soc_CMIC_PARITY_INTR_STATUS_BCM56334_A0fmt_fields, 8019 /* bits */ 32, 8020 /* flags */ 0, 8021 }, 8022 #endif /* chips */ 8023 8024 #if defined(BCM_56150_A0) 8025 { /* SOC_FORMAT_INT_CMIC_PARITY_INTR_STATUS_BCM56150_A0fmt */ 8026 /* format CMIC_PARITY_INTR_STATUSfmt */ 8027 /* nFields */ 11, 8028 /* *fields */ soc_CMIC_PARITY_INTR_STATUS_BCM56150_A0fmt_fields, 8029 /* bits */ 32, 8030 /* flags */ 0, 8031 }, 8032 #endif /* chips */ 8033 8034 #if defined(BCM_56160_A0) 8035 { /* SOC_FORMAT_INT_CMIC_PARITY_INTR_STATUS_BCM56160_A0fmt */ 8036 /* format CMIC_PARITY_INTR_STATUSfmt */ 8037 /* nFields */ 11, 8038 /* *fields */ soc_CMIC_PARITY_INTR_STATUS_BCM56160_A0fmt_fields, 8039 /* bits */ 32, 8040 /* flags */ 0, 8041 }, 8042 #endif /* chips */ 8043 8044 #if defined(BCM_56334_A0) 8045 { /* SOC_FORMAT_INT_CMIC_PARITY_INTR_STATUS_BCM56334_A0fmt */ 8046 /* format CMIC_PARITY_INTR_STATUSfmt */ 8047 /* nFields */ 11, 8048 /* *fields */ soc_CMIC_PARITY_INTR_STATUS_BCM56334_A0fmt_fields, 8049 /* bits */ 32, 8050 /* flags */ 0, 8051 }, 8052 #endif /* chips */ 8053 8054 #if defined(BCM_56334_B0) 8055 { /* SOC_FORMAT_INT_CMIC_PARITY_INTR_STATUS_BCM56334_B0fmt */ 8056 /* format CMIC_PARITY_INTR_STATUSfmt */ 8057 /* nFields */ 11, 8058 /* *fields */ soc_CMIC_PARITY_INTR_STATUS_BCM56334_A0fmt_fields, 8059 /* bits */ 32, 8060 /* flags */ 0, 8061 }, 8062 #endif /* chips */ 8063 8064 #if defined(BCM_56340_A0) 8065 { /* SOC_FORMAT_INT_CMIC_PARITY_INTR_STATUS_BCM56340_A0fmt */ 8066 /* format CMIC_PARITY_INTR_STATUSfmt */ 8067 /* nFields */ 14, 8068 /* *fields */ soc_CMIC_PARITY_INTR_STATUS_BCM56340_A0fmt_fields, 8069 /* bits */ 15, 8070 /* flags */ 0, 8071 }, 8072 #endif /* chips */ 8073 8074 #if defined(BCM_56440_A0) 8075 { /* SOC_FORMAT_INT_CMIC_PARITY_INTR_STATUS_BCM56440_A0fmt */ 8076 /* format CMIC_PARITY_INTR_STATUSfmt */ 8077 /* nFields */ 12, 8078 /* *fields */ soc_CMIC_PARITY_INTR_STATUS_BCM56440_A0fmt_fields, 8079 /* bits */ 32, 8080 /* flags */ 0, 8081 }, 8082 #endif /* chips */ 8083 8084 #if defined(BCM_56440_B0) 8085 { /* SOC_FORMAT_INT_CMIC_PARITY_INTR_STATUS_BCM56440_B0fmt */ 8086 /* format CMIC_PARITY_INTR_STATUSfmt */ 8087 /* nFields */ 12, 8088 /* *fields */ soc_CMIC_PARITY_INTR_STATUS_BCM56440_A0fmt_fields, 8089 /* bits */ 32, 8090 /* flags */ 0, 8091 }, 8092 #endif /* chips */ 8093 8094 #if defined(BCM_56450_A0) 8095 { /* SOC_FORMAT_INT_CMIC_PARITY_INTR_STATUS_BCM56450_A0fmt */ 8096 /* format CMIC_PARITY_INTR_STATUSfmt */ 8097 /* nFields */ 24, 8098 /* *fields */ soc_CMIC_PARITY_INTR_STATUS_BCM56450_A0fmt_fields, 8099 /* bits */ 32, 8100 /* flags */ 0, 8101 }, 8102 #endif /* chips */ 8103 8104 #if defined(BCM_56450_B0) 8105 { /* SOC_FORMAT_INT_CMIC_PARITY_INTR_STATUS_BCM56450_B0fmt */ 8106 /* format CMIC_PARITY_INTR_STATUSfmt */ 8107 /* nFields */ 24, 8108 /* *fields */ soc_CMIC_PARITY_INTR_STATUS_BCM56450_A0fmt_fields, 8109 /* bits */ 32, 8110 /* flags */ 0, 8111 }, 8112 #endif /* chips */ 8113 8114 #if defined(BCM_56450_B1) 8115 { /* SOC_FORMAT_INT_CMIC_PARITY_INTR_STATUS_BCM56450_B1fmt */ 8116 /* format CMIC_PARITY_INTR_STATUSfmt */ 8117 /* nFields */ 24, 8118 /* *fields */ soc_CMIC_PARITY_INTR_STATUS_BCM56450_A0fmt_fields, 8119 /* bits */ 32, 8120 /* flags */ 0, 8121 }, 8122 #endif /* chips */ 8123 8124 #if defined(BCM_56524_A0) 8125 { /* SOC_FORMAT_INT_CMIC_PARITY_INTR_STATUS_BCM56524_A0fmt */ 8126 /* format CMIC_PARITY_INTR_STATUSfmt */ 8127 /* nFields */ 21, 8128 /* *fields */ soc_CMIC_PARITY_INTR_STATUS_BCM56634_A0fmt_fields, 8129 /* bits */ 32, 8130 /* flags */ 0, 8131 }, 8132 #endif /* chips */ 8133 8134 #if defined(BCM_56524_B0) 8135 { /* SOC_FORMAT_INT_CMIC_PARITY_INTR_STATUS_BCM56524_B0fmt */ 8136 /* format CMIC_PARITY_INTR_STATUSfmt */ 8137 /* nFields */ 21, 8138 /* *fields */ soc_CMIC_PARITY_INTR_STATUS_BCM56634_A0fmt_fields, 8139 /* bits */ 32, 8140 /* flags */ 0, 8141 }, 8142 #endif /* chips */ 8143 8144 #if defined(BCM_56634_A0) 8145 { /* SOC_FORMAT_INT_CMIC_PARITY_INTR_STATUS_BCM56634_A0fmt */ 8146 /* format CMIC_PARITY_INTR_STATUSfmt */ 8147 /* nFields */ 21, 8148 /* *fields */ soc_CMIC_PARITY_INTR_STATUS_BCM56634_A0fmt_fields, 8149 /* bits */ 32, 8150 /* flags */ 0, 8151 }, 8152 #endif /* chips */ 8153 8154 #if defined(BCM_56634_B0) 8155 { /* SOC_FORMAT_INT_CMIC_PARITY_INTR_STATUS_BCM56634_B0fmt */ 8156 /* format CMIC_PARITY_INTR_STATUSfmt */ 8157 /* nFields */ 21, 8158 /* *fields */ soc_CMIC_PARITY_INTR_STATUS_BCM56634_A0fmt_fields, 8159 /* bits */ 32, 8160 /* flags */ 0, 8161 }, 8162 #endif /* chips */ 8163 8164 #if defined(BCM_56640_A0) 8165 { /* SOC_FORMAT_INT_CMIC_PARITY_INTR_STATUS_BCM56640_A0fmt */ 8166 /* format CMIC_PARITY_INTR_STATUSfmt */ 8167 /* nFields */ 15, 8168 /* *fields */ soc_CMIC_PARITY_INTR_STATUS_BCM56640_A0fmt_fields, 8169 /* bits */ 15, 8170 /* flags */ 0, 8171 }, 8172 #endif /* chips */ 8173 8174 #if defined(BCM_56685_A0) 8175 { /* SOC_FORMAT_INT_CMIC_PARITY_INTR_STATUS_BCM56685_A0fmt */ 8176 /* format CMIC_PARITY_INTR_STATUSfmt */ 8177 /* nFields */ 21, 8178 /* *fields */ soc_CMIC_PARITY_INTR_STATUS_BCM56634_A0fmt_fields, 8179 /* bits */ 32, 8180 /* flags */ 0, 8181 }, 8182 #endif /* chips */ 8183 8184 #if defined(BCM_56685_B0) 8185 { /* SOC_FORMAT_INT_CMIC_PARITY_INTR_STATUS_BCM56685_B0fmt */ 8186 /* format CMIC_PARITY_INTR_STATUSfmt */ 8187 /* nFields */ 21, 8188 /* *fields */ soc_CMIC_PARITY_INTR_STATUS_BCM56634_A0fmt_fields, 8189 /* bits */ 32, 8190 /* flags */ 0, 8191 }, 8192 #endif /* chips */ 8193 8194 #if defined(BCM_56840_A0) 8195 { /* SOC_FORMAT_INT_CMIC_PARITY_INTR_STATUS_BCM56840_A0fmt */ 8196 /* format CMIC_PARITY_INTR_STATUSfmt */ 8197 /* nFields */ 22, 8198 /* *fields */ soc_CMIC_PARITY_INTR_STATUS_BCM56840_A0fmt_fields, 8199 /* bits */ 22, 8200 /* flags */ 0, 8201 }, 8202 #endif /* chips */ 8203 8204 #if defined(BCM_56840_B0) 8205 { /* SOC_FORMAT_INT_CMIC_PARITY_INTR_STATUS_BCM56840_B0fmt */ 8206 /* format CMIC_PARITY_INTR_STATUSfmt */ 8207 /* nFields */ 22, 8208 /* *fields */ soc_CMIC_PARITY_INTR_STATUS_BCM56840_A0fmt_fields, 8209 /* bits */ 22, 8210 /* flags */ 0, 8211 }, 8212 #endif /* chips */ 8213 8214 #if defined(BCM_56850_A0) 8215 { /* SOC_FORMAT_INT_CMIC_PARITY_INTR_STATUS_BCM56850_A0fmt */ 8216 /* format CMIC_PARITY_INTR_STATUSfmt */ 8217 /* nFields */ 26, 8218 /* *fields */ soc_CMIC_PARITY_INTR_STATUS_BCM56850_A0fmt_fields, 8219 /* bits */ 26, 8220 /* flags */ 0, 8221 }, 8222 #endif /* chips */ 8223 8224 #if defined(BCM_56860_A0) 8225 { /* SOC_FORMAT_INT_CMIC_PARITY_INTR_STATUS_BCM56860_A0fmt */ 8226 /* format CMIC_PARITY_INTR_STATUSfmt */ 8227 /* nFields */ 26, 8228 /* *fields */ soc_CMIC_PARITY_INTR_STATUS_BCM56850_A0fmt_fields, 8229 /* bits */ 26, 8230 /* flags */ 0, 8231 }, 8232 #endif /* chips */ 8233 8234 #if defined(BCM_56840_A0) 8235 { /* SOC_FORMAT_INT_CMIC_SOFT_RESET_REGfmt */ 8236 /* format CMIC_SOFT_RESET_REGfmt */ 8237 /* nFields */ 17, 8238 /* *fields */ soc_CMIC_SOFT_RESET_REGfmt_fields, 8239 /* bits */ 32, 8240 /* flags */ 0, 8241 }, 8242 #endif /* chips */ 8243 8244 #if defined(BCM_56840_A0) 8245 { /* SOC_FORMAT_INT_CMIC_SOFT_RESET_REG_2fmt */ 8246 /* format CMIC_SOFT_RESET_REG_2fmt */ 8247 /* nFields */ 8, 8248 /* *fields */ soc_CMIC_SOFT_RESET_REG_2fmt_fields, 8249 /* bits */ 32, 8250 /* flags */ 0, 8251 }, 8252 #endif /* chips */ 8253 8254 #if defined(BCM_56260_A0) 8255 { /* SOC_FORMAT_INT_CMIC_SOFT_RESET_REG_2_BCM56260_A0fmt */ 8256 /* format CMIC_SOFT_RESET_REG_2fmt */ 8257 /* nFields */ 8, 8258 /* *fields */ soc_CMIC_SOFT_RESET_REG_2_BCM56960_A0fmt_fields, 8259 /* bits */ 32, 8260 /* flags */ 0, 8261 }, 8262 #endif /* chips */ 8263 8264 #if defined(BCM_56260_B0) 8265 { /* SOC_FORMAT_INT_CMIC_SOFT_RESET_REG_2_BCM56260_B0fmt */ 8266 /* format CMIC_SOFT_RESET_REG_2fmt */ 8267 /* nFields */ 8, 8268 /* *fields */ soc_CMIC_SOFT_RESET_REG_2_BCM56960_A0fmt_fields, 8269 /* bits */ 32, 8270 /* flags */ 0, 8271 }, 8272 #endif /* chips */ 8273 8274 #if defined(BCM_56270_A0) 8275 { /* SOC_FORMAT_INT_CMIC_SOFT_RESET_REG_2_BCM56270_A0fmt */ 8276 /* format CMIC_SOFT_RESET_REG_2fmt */ 8277 /* nFields */ 8, 8278 /* *fields */ soc_CMIC_SOFT_RESET_REG_2_BCM56960_A0fmt_fields, 8279 /* bits */ 32, 8280 /* flags */ 0, 8281 }, 8282 #endif /* chips */ 8283 8284 #if defined(BCM_56340_A0) 8285 { /* SOC_FORMAT_INT_CMIC_SOFT_RESET_REG_2_BCM56340_A0fmt */ 8286 /* format CMIC_SOFT_RESET_REG_2fmt */ 8287 /* nFields */ 8, 8288 /* *fields */ soc_CMIC_SOFT_RESET_REG_2_BCM56640_A0fmt_fields, 8289 /* bits */ 32, 8290 /* flags */ 0, 8291 }, 8292 #endif /* chips */ 8293 8294 #if defined(BCM_56370_A0) 8295 { /* SOC_FORMAT_INT_CMIC_SOFT_RESET_REG_2_BCM56370_A0fmt */ 8296 /* format CMIC_SOFT_RESET_REG_2fmt */ 8297 /* nFields */ 8, 8298 /* *fields */ soc_CMIC_SOFT_RESET_REG_2_BCM56960_A0fmt_fields, 8299 /* bits */ 32, 8300 /* flags */ 0, 8301 }, 8302 #endif /* chips */ 8303 8304 #if defined(BCM_56450_A0) 8305 { /* SOC_FORMAT_INT_CMIC_SOFT_RESET_REG_2_BCM56450_A0fmt */ 8306 /* format CMIC_SOFT_RESET_REG_2fmt */ 8307 /* nFields */ 8, 8308 /* *fields */ soc_CMIC_SOFT_RESET_REG_2_BCM56640_A0fmt_fields, 8309 /* bits */ 32, 8310 /* flags */ 0, 8311 }, 8312 #endif /* chips */ 8313 8314 #if defined(BCM_56450_B0) 8315 { /* SOC_FORMAT_INT_CMIC_SOFT_RESET_REG_2_BCM56450_B0fmt */ 8316 /* format CMIC_SOFT_RESET_REG_2fmt */ 8317 /* nFields */ 8, 8318 /* *fields */ soc_CMIC_SOFT_RESET_REG_2_BCM56640_A0fmt_fields, 8319 /* bits */ 32, 8320 /* flags */ 0, 8321 }, 8322 #endif /* chips */ 8323 8324 #if defined(BCM_56450_B1) 8325 { /* SOC_FORMAT_INT_CMIC_SOFT_RESET_REG_2_BCM56450_B1fmt */ 8326 /* format CMIC_SOFT_RESET_REG_2fmt */ 8327 /* nFields */ 8, 8328 /* *fields */ soc_CMIC_SOFT_RESET_REG_2_BCM56640_A0fmt_fields, 8329 /* bits */ 32, 8330 /* flags */ 0, 8331 }, 8332 #endif /* chips */ 8333 8334 #if defined(BCM_56640_A0) 8335 { /* SOC_FORMAT_INT_CMIC_SOFT_RESET_REG_2_BCM56640_A0fmt */ 8336 /* format CMIC_SOFT_RESET_REG_2fmt */ 8337 /* nFields */ 8, 8338 /* *fields */ soc_CMIC_SOFT_RESET_REG_2_BCM56640_A0fmt_fields, 8339 /* bits */ 32, 8340 /* flags */ 0, 8341 }, 8342 #endif /* chips */ 8343 8344 #if defined(BCM_56770_A0) 8345 { /* SOC_FORMAT_INT_CMIC_SOFT_RESET_REG_2_BCM56770_A0fmt */ 8346 /* format CMIC_SOFT_RESET_REG_2fmt */ 8347 /* nFields */ 8, 8348 /* *fields */ soc_CMIC_SOFT_RESET_REG_2_BCM56960_A0fmt_fields, 8349 /* bits */ 32, 8350 /* flags */ 0, 8351 }, 8352 #endif /* chips */ 8353 8354 #if defined(BCM_56840_B0) 8355 { /* SOC_FORMAT_INT_CMIC_SOFT_RESET_REG_2_BCM56840_B0fmt */ 8356 /* format CMIC_SOFT_RESET_REG_2fmt */ 8357 /* nFields */ 8, 8358 /* *fields */ soc_CMIC_SOFT_RESET_REG_2fmt_fields, 8359 /* bits */ 32, 8360 /* flags */ 0, 8361 }, 8362 #endif /* chips */ 8363 8364 #if defined(BCM_56850_A0) 8365 { /* SOC_FORMAT_INT_CMIC_SOFT_RESET_REG_2_BCM56850_A0fmt */ 8366 /* format CMIC_SOFT_RESET_REG_2fmt */ 8367 /* nFields */ 8, 8368 /* *fields */ soc_CMIC_SOFT_RESET_REG_2_BCM56640_A0fmt_fields, 8369 /* bits */ 32, 8370 /* flags */ 0, 8371 }, 8372 #endif /* chips */ 8373 8374 #if defined(BCM_56860_A0) 8375 { /* SOC_FORMAT_INT_CMIC_SOFT_RESET_REG_2_BCM56860_A0fmt */ 8376 /* format CMIC_SOFT_RESET_REG_2fmt */ 8377 /* nFields */ 8, 8378 /* *fields */ soc_CMIC_SOFT_RESET_REG_2_BCM56640_A0fmt_fields, 8379 /* bits */ 32, 8380 /* flags */ 0, 8381 }, 8382 #endif /* chips */ 8383 8384 #if defined(BCM_56870_A0) 8385 { /* SOC_FORMAT_INT_CMIC_SOFT_RESET_REG_2_BCM56870_A0fmt */ 8386 /* format CMIC_SOFT_RESET_REG_2fmt */ 8387 /* nFields */ 8, 8388 /* *fields */ soc_CMIC_SOFT_RESET_REG_2_BCM56960_A0fmt_fields, 8389 /* bits */ 32, 8390 /* flags */ 0, 8391 }, 8392 #endif /* chips */ 8393 8394 #if defined(BCM_56960_A0) 8395 { /* SOC_FORMAT_INT_CMIC_SOFT_RESET_REG_2_BCM56960_A0fmt */ 8396 /* format CMIC_SOFT_RESET_REG_2fmt */ 8397 /* nFields */ 8, 8398 /* *fields */ soc_CMIC_SOFT_RESET_REG_2_BCM56960_A0fmt_fields, 8399 /* bits */ 32, 8400 /* flags */ 0, 8401 }, 8402 #endif /* chips */ 8403 8404 #if defined(BCM_56965_A0) 8405 { /* SOC_FORMAT_INT_CMIC_SOFT_RESET_REG_2_BCM56965_A0fmt */ 8406 /* format CMIC_SOFT_RESET_REG_2fmt */ 8407 /* nFields */ 8, 8408 /* *fields */ soc_CMIC_SOFT_RESET_REG_2_BCM56960_A0fmt_fields, 8409 /* bits */ 32, 8410 /* flags */ 0, 8411 }, 8412 #endif /* chips */ 8413 8414 #if defined(BCM_56970_A0) 8415 { /* SOC_FORMAT_INT_CMIC_SOFT_RESET_REG_2_BCM56970_A0fmt */ 8416 /* format CMIC_SOFT_RESET_REG_2fmt */ 8417 /* nFields */ 8, 8418 /* *fields */ soc_CMIC_SOFT_RESET_REG_2_BCM56960_A0fmt_fields, 8419 /* bits */ 32, 8420 /* flags */ 0, 8421 }, 8422 #endif /* chips */ 8423 8424 #if defined(BCM_88732_A0) 8425 { /* SOC_FORMAT_INT_CMIC_SOFT_RESET_REG_2_BCM88732_A0fmt */ 8426 /* format CMIC_SOFT_RESET_REG_2fmt */ 8427 /* nFields */ 2, 8428 /* *fields */ soc_CMIC_SOFT_RESET_REG_2_BCM88732_A0fmt_fields, 8429 /* bits */ 32, 8430 /* flags */ 0, 8431 }, 8432 #endif /* chips */ 8433 8434 #if defined(BCM_56260_A0) 8435 { /* SOC_FORMAT_INT_CMIC_SOFT_RESET_REG_BCM56260_A0fmt */ 8436 /* format CMIC_SOFT_RESET_REGfmt */ 8437 /* nFields */ 17, 8438 /* *fields */ soc_CMIC_SOFT_RESET_REG_BCM56960_A0fmt_fields, 8439 /* bits */ 32, 8440 /* flags */ 0, 8441 }, 8442 #endif /* chips */ 8443 8444 #if defined(BCM_56260_B0) 8445 { /* SOC_FORMAT_INT_CMIC_SOFT_RESET_REG_BCM56260_B0fmt */ 8446 /* format CMIC_SOFT_RESET_REGfmt */ 8447 /* nFields */ 17, 8448 /* *fields */ soc_CMIC_SOFT_RESET_REG_BCM56960_A0fmt_fields, 8449 /* bits */ 32, 8450 /* flags */ 0, 8451 }, 8452 #endif /* chips */ 8453 8454 #if defined(BCM_56270_A0) 8455 { /* SOC_FORMAT_INT_CMIC_SOFT_RESET_REG_BCM56270_A0fmt */ 8456 /* format CMIC_SOFT_RESET_REGfmt */ 8457 /* nFields */ 17, 8458 /* *fields */ soc_CMIC_SOFT_RESET_REG_BCM56960_A0fmt_fields, 8459 /* bits */ 32, 8460 /* flags */ 0, 8461 }, 8462 #endif /* chips */ 8463 8464 #if defined(BCM_56340_A0) 8465 { /* SOC_FORMAT_INT_CMIC_SOFT_RESET_REG_BCM56340_A0fmt */ 8466 /* format CMIC_SOFT_RESET_REGfmt */ 8467 /* nFields */ 17, 8468 /* *fields */ soc_CMIC_SOFT_RESET_REG_BCM56640_A0fmt_fields, 8469 /* bits */ 32, 8470 /* flags */ 0, 8471 }, 8472 #endif /* chips */ 8473 8474 #if defined(BCM_56370_A0) 8475 { /* SOC_FORMAT_INT_CMIC_SOFT_RESET_REG_BCM56370_A0fmt */ 8476 /* format CMIC_SOFT_RESET_REGfmt */ 8477 /* nFields */ 17, 8478 /* *fields */ soc_CMIC_SOFT_RESET_REG_BCM56960_A0fmt_fields, 8479 /* bits */ 32, 8480 /* flags */ 0, 8481 }, 8482 #endif /* chips */ 8483 8484 #if defined(BCM_56450_A0) 8485 { /* SOC_FORMAT_INT_CMIC_SOFT_RESET_REG_BCM56450_A0fmt */ 8486 /* format CMIC_SOFT_RESET_REGfmt */ 8487 /* nFields */ 17, 8488 /* *fields */ soc_CMIC_SOFT_RESET_REG_BCM56640_A0fmt_fields, 8489 /* bits */ 32, 8490 /* flags */ 0, 8491 }, 8492 #endif /* chips */ 8493 8494 #if defined(BCM_56450_B0) 8495 { /* SOC_FORMAT_INT_CMIC_SOFT_RESET_REG_BCM56450_B0fmt */ 8496 /* format CMIC_SOFT_RESET_REGfmt */ 8497 /* nFields */ 17, 8498 /* *fields */ soc_CMIC_SOFT_RESET_REG_BCM56640_A0fmt_fields, 8499 /* bits */ 32, 8500 /* flags */ 0, 8501 }, 8502 #endif /* chips */ 8503 8504 #if defined(BCM_56450_B1) 8505 { /* SOC_FORMAT_INT_CMIC_SOFT_RESET_REG_BCM56450_B1fmt */ 8506 /* format CMIC_SOFT_RESET_REGfmt */ 8507 /* nFields */ 17, 8508 /* *fields */ soc_CMIC_SOFT_RESET_REG_BCM56640_A0fmt_fields, 8509 /* bits */ 32, 8510 /* flags */ 0, 8511 }, 8512 #endif /* chips */ 8513 8514 #if defined(BCM_56640_A0) 8515 { /* SOC_FORMAT_INT_CMIC_SOFT_RESET_REG_BCM56640_A0fmt */ 8516 /* format CMIC_SOFT_RESET_REGfmt */ 8517 /* nFields */ 17, 8518 /* *fields */ soc_CMIC_SOFT_RESET_REG_BCM56640_A0fmt_fields, 8519 /* bits */ 32, 8520 /* flags */ 0, 8521 }, 8522 #endif /* chips */ 8523 8524 #if defined(BCM_56770_A0) 8525 { /* SOC_FORMAT_INT_CMIC_SOFT_RESET_REG_BCM56770_A0fmt */ 8526 /* format CMIC_SOFT_RESET_REGfmt */ 8527 /* nFields */ 17, 8528 /* *fields */ soc_CMIC_SOFT_RESET_REG_BCM56960_A0fmt_fields, 8529 /* bits */ 32, 8530 /* flags */ 0, 8531 }, 8532 #endif /* chips */ 8533 8534 #if defined(BCM_56840_B0) 8535 { /* SOC_FORMAT_INT_CMIC_SOFT_RESET_REG_BCM56840_B0fmt */ 8536 /* format CMIC_SOFT_RESET_REGfmt */ 8537 /* nFields */ 17, 8538 /* *fields */ soc_CMIC_SOFT_RESET_REGfmt_fields, 8539 /* bits */ 32, 8540 /* flags */ 0, 8541 }, 8542 #endif /* chips */ 8543 8544 #if defined(BCM_56850_A0) 8545 { /* SOC_FORMAT_INT_CMIC_SOFT_RESET_REG_BCM56850_A0fmt */ 8546 /* format CMIC_SOFT_RESET_REGfmt */ 8547 /* nFields */ 17, 8548 /* *fields */ soc_CMIC_SOFT_RESET_REG_BCM56640_A0fmt_fields, 8549 /* bits */ 32, 8550 /* flags */ 0, 8551 }, 8552 #endif /* chips */ 8553 8554 #if defined(BCM_56860_A0) 8555 { /* SOC_FORMAT_INT_CMIC_SOFT_RESET_REG_BCM56860_A0fmt */ 8556 /* format CMIC_SOFT_RESET_REGfmt */ 8557 /* nFields */ 17, 8558 /* *fields */ soc_CMIC_SOFT_RESET_REG_BCM56640_A0fmt_fields, 8559 /* bits */ 32, 8560 /* flags */ 0, 8561 }, 8562 #endif /* chips */ 8563 8564 #if defined(BCM_56870_A0) 8565 { /* SOC_FORMAT_INT_CMIC_SOFT_RESET_REG_BCM56870_A0fmt */ 8566 /* format CMIC_SOFT_RESET_REGfmt */ 8567 /* nFields */ 17, 8568 /* *fields */ soc_CMIC_SOFT_RESET_REG_BCM56960_A0fmt_fields, 8569 /* bits */ 32, 8570 /* flags */ 0, 8571 }, 8572 #endif /* chips */ 8573 8574 #if defined(BCM_56960_A0) 8575 { /* SOC_FORMAT_INT_CMIC_SOFT_RESET_REG_BCM56960_A0fmt */ 8576 /* format CMIC_SOFT_RESET_REGfmt */ 8577 /* nFields */ 17, 8578 /* *fields */ soc_CMIC_SOFT_RESET_REG_BCM56960_A0fmt_fields, 8579 /* bits */ 32, 8580 /* flags */ 0, 8581 }, 8582 #endif /* chips */ 8583 8584 #if defined(BCM_56965_A0) 8585 { /* SOC_FORMAT_INT_CMIC_SOFT_RESET_REG_BCM56965_A0fmt */ 8586 /* format CMIC_SOFT_RESET_REGfmt */ 8587 /* nFields */ 17, 8588 /* *fields */ soc_CMIC_SOFT_RESET_REG_BCM56960_A0fmt_fields, 8589 /* bits */ 32, 8590 /* flags */ 0, 8591 }, 8592 #endif /* chips */ 8593 8594 #if defined(BCM_56970_A0) 8595 { /* SOC_FORMAT_INT_CMIC_SOFT_RESET_REG_BCM56970_A0fmt */ 8596 /* format CMIC_SOFT_RESET_REGfmt */ 8597 /* nFields */ 17, 8598 /* *fields */ soc_CMIC_SOFT_RESET_REG_BCM56960_A0fmt_fields, 8599 /* bits */ 32, 8600 /* flags */ 0, 8601 }, 8602 #endif /* chips */ 8603 8604 #if defined(BCM_88732_A0) 8605 { /* SOC_FORMAT_INT_CMIC_SOFT_RESET_REG_BCM88732_A0fmt */ 8606 /* format CMIC_SOFT_RESET_REGfmt */ 8607 /* nFields */ 29, 8608 /* *fields */ soc_CMIC_SOFT_RESET_REG_BCM88732_A0fmt_fields, 8609 /* bits */ 32, 8610 /* flags */ 0, 8611 }, 8612 #endif /* chips */ 8613 8614 #if defined(BCM_56840_A0) 8615 { /* SOC_FORMAT_INT_CMIC_THERMAL_MON_CTRLfmt */ 8616 /* format CMIC_THERMAL_MON_CTRLfmt */ 8617 /* nFields */ 6, 8618 /* *fields */ soc_CMIC_THERMAL_MON_CTRLfmt_fields, 8619 /* bits */ 32, 8620 /* flags */ 0, 8621 }, 8622 #endif /* chips */ 8623 8624 #if defined(BCM_56260_A0) 8625 { /* SOC_FORMAT_INT_CMIC_THERMAL_MON_CTRL_BCM56260_A0fmt */ 8626 /* format CMIC_THERMAL_MON_CTRLfmt */ 8627 /* nFields */ 6, 8628 /* *fields */ soc_CMIC_THERMAL_MON_CTRL_BCM56960_A0fmt_fields, 8629 /* bits */ 32, 8630 /* flags */ 0, 8631 }, 8632 #endif /* chips */ 8633 8634 #if defined(BCM_56260_B0) 8635 { /* SOC_FORMAT_INT_CMIC_THERMAL_MON_CTRL_BCM56260_B0fmt */ 8636 /* format CMIC_THERMAL_MON_CTRLfmt */ 8637 /* nFields */ 6, 8638 /* *fields */ soc_CMIC_THERMAL_MON_CTRL_BCM56960_A0fmt_fields, 8639 /* bits */ 32, 8640 /* flags */ 0, 8641 }, 8642 #endif /* chips */ 8643 8644 #if defined(BCM_56270_A0) 8645 { /* SOC_FORMAT_INT_CMIC_THERMAL_MON_CTRL_BCM56270_A0fmt */ 8646 /* format CMIC_THERMAL_MON_CTRLfmt */ 8647 /* nFields */ 6, 8648 /* *fields */ soc_CMIC_THERMAL_MON_CTRL_BCM56960_A0fmt_fields, 8649 /* bits */ 32, 8650 /* flags */ 0, 8651 }, 8652 #endif /* chips */ 8653 8654 #if defined(BCM_56340_A0) 8655 { /* SOC_FORMAT_INT_CMIC_THERMAL_MON_CTRL_BCM56340_A0fmt */ 8656 /* format CMIC_THERMAL_MON_CTRLfmt */ 8657 /* nFields */ 6, 8658 /* *fields */ soc_CMIC_THERMAL_MON_CTRL_BCM56640_A0fmt_fields, 8659 /* bits */ 32, 8660 /* flags */ 0, 8661 }, 8662 #endif /* chips */ 8663 8664 #if defined(BCM_56370_A0) 8665 { /* SOC_FORMAT_INT_CMIC_THERMAL_MON_CTRL_BCM56370_A0fmt */ 8666 /* format CMIC_THERMAL_MON_CTRLfmt */ 8667 /* nFields */ 6, 8668 /* *fields */ soc_CMIC_THERMAL_MON_CTRL_BCM56960_A0fmt_fields, 8669 /* bits */ 32, 8670 /* flags */ 0, 8671 }, 8672 #endif /* chips */ 8673 8674 #if defined(BCM_56450_A0) 8675 { /* SOC_FORMAT_INT_CMIC_THERMAL_MON_CTRL_BCM56450_A0fmt */ 8676 /* format CMIC_THERMAL_MON_CTRLfmt */ 8677 /* nFields */ 6, 8678 /* *fields */ soc_CMIC_THERMAL_MON_CTRL_BCM56640_A0fmt_fields, 8679 /* bits */ 32, 8680 /* flags */ 0, 8681 }, 8682 #endif /* chips */ 8683 8684 #if defined(BCM_56450_B0) 8685 { /* SOC_FORMAT_INT_CMIC_THERMAL_MON_CTRL_BCM56450_B0fmt */ 8686 /* format CMIC_THERMAL_MON_CTRLfmt */ 8687 /* nFields */ 6, 8688 /* *fields */ soc_CMIC_THERMAL_MON_CTRL_BCM56640_A0fmt_fields, 8689 /* bits */ 32, 8690 /* flags */ 0, 8691 }, 8692 #endif /* chips */ 8693 8694 #if defined(BCM_56450_B1) 8695 { /* SOC_FORMAT_INT_CMIC_THERMAL_MON_CTRL_BCM56450_B1fmt */ 8696 /* format CMIC_THERMAL_MON_CTRLfmt */ 8697 /* nFields */ 6, 8698 /* *fields */ soc_CMIC_THERMAL_MON_CTRL_BCM56640_A0fmt_fields, 8699 /* bits */ 32, 8700 /* flags */ 0, 8701 }, 8702 #endif /* chips */ 8703 8704 #if defined(BCM_56640_A0) 8705 { /* SOC_FORMAT_INT_CMIC_THERMAL_MON_CTRL_BCM56640_A0fmt */ 8706 /* format CMIC_THERMAL_MON_CTRLfmt */ 8707 /* nFields */ 6, 8708 /* *fields */ soc_CMIC_THERMAL_MON_CTRL_BCM56640_A0fmt_fields, 8709 /* bits */ 32, 8710 /* flags */ 0, 8711 }, 8712 #endif /* chips */ 8713 8714 #if defined(BCM_56770_A0) 8715 { /* SOC_FORMAT_INT_CMIC_THERMAL_MON_CTRL_BCM56770_A0fmt */ 8716 /* format CMIC_THERMAL_MON_CTRLfmt */ 8717 /* nFields */ 6, 8718 /* *fields */ soc_CMIC_THERMAL_MON_CTRL_BCM56960_A0fmt_fields, 8719 /* bits */ 32, 8720 /* flags */ 0, 8721 }, 8722 #endif /* chips */ 8723 8724 #if defined(BCM_56840_B0) 8725 { /* SOC_FORMAT_INT_CMIC_THERMAL_MON_CTRL_BCM56840_B0fmt */ 8726 /* format CMIC_THERMAL_MON_CTRLfmt */ 8727 /* nFields */ 6, 8728 /* *fields */ soc_CMIC_THERMAL_MON_CTRLfmt_fields, 8729 /* bits */ 32, 8730 /* flags */ 0, 8731 }, 8732 #endif /* chips */ 8733 8734 #if defined(BCM_56850_A0) 8735 { /* SOC_FORMAT_INT_CMIC_THERMAL_MON_CTRL_BCM56850_A0fmt */ 8736 /* format CMIC_THERMAL_MON_CTRLfmt */ 8737 /* nFields */ 6, 8738 /* *fields */ soc_CMIC_THERMAL_MON_CTRL_BCM56640_A0fmt_fields, 8739 /* bits */ 32, 8740 /* flags */ 0, 8741 }, 8742 #endif /* chips */ 8743 8744 #if defined(BCM_56860_A0) 8745 { /* SOC_FORMAT_INT_CMIC_THERMAL_MON_CTRL_BCM56860_A0fmt */ 8746 /* format CMIC_THERMAL_MON_CTRLfmt */ 8747 /* nFields */ 6, 8748 /* *fields */ soc_CMIC_THERMAL_MON_CTRL_BCM56640_A0fmt_fields, 8749 /* bits */ 32, 8750 /* flags */ 0, 8751 }, 8752 #endif /* chips */ 8753 8754 #if defined(BCM_56870_A0) 8755 { /* SOC_FORMAT_INT_CMIC_THERMAL_MON_CTRL_BCM56870_A0fmt */ 8756 /* format CMIC_THERMAL_MON_CTRLfmt */ 8757 /* nFields */ 6, 8758 /* *fields */ soc_CMIC_THERMAL_MON_CTRL_BCM56960_A0fmt_fields, 8759 /* bits */ 32, 8760 /* flags */ 0, 8761 }, 8762 #endif /* chips */ 8763 8764 #if defined(BCM_56960_A0) 8765 { /* SOC_FORMAT_INT_CMIC_THERMAL_MON_CTRL_BCM56960_A0fmt */ 8766 /* format CMIC_THERMAL_MON_CTRLfmt */ 8767 /* nFields */ 6, 8768 /* *fields */ soc_CMIC_THERMAL_MON_CTRL_BCM56960_A0fmt_fields, 8769 /* bits */ 32, 8770 /* flags */ 0, 8771 }, 8772 #endif /* chips */ 8773 8774 #if defined(BCM_56965_A0) 8775 { /* SOC_FORMAT_INT_CMIC_THERMAL_MON_CTRL_BCM56965_A0fmt */ 8776 /* format CMIC_THERMAL_MON_CTRLfmt */ 8777 /* nFields */ 6, 8778 /* *fields */ soc_CMIC_THERMAL_MON_CTRL_BCM56960_A0fmt_fields, 8779 /* bits */ 32, 8780 /* flags */ 0, 8781 }, 8782 #endif /* chips */ 8783 8784 #if defined(BCM_56970_A0) 8785 { /* SOC_FORMAT_INT_CMIC_THERMAL_MON_CTRL_BCM56970_A0fmt */ 8786 /* format CMIC_THERMAL_MON_CTRLfmt */ 8787 /* nFields */ 6, 8788 /* *fields */ soc_CMIC_THERMAL_MON_CTRL_BCM56960_A0fmt_fields, 8789 /* bits */ 32, 8790 /* flags */ 0, 8791 }, 8792 #endif /* chips */ 8793 8794 #if defined(BCM_56840_A0) 8795 { /* SOC_FORMAT_INT_CMIC_XGXS0_PLL_CONTROL_1fmt */ 8796 /* format CMIC_XGXS0_PLL_CONTROL_1fmt */ 8797 /* nFields */ 4, 8798 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_1fmt_fields, 8799 /* bits */ 32, 8800 /* flags */ 0, 8801 }, 8802 #endif /* chips */ 8803 8804 #if defined(BCM_56840_A0) 8805 { /* SOC_FORMAT_INT_CMIC_XGXS0_PLL_CONTROL_2fmt */ 8806 /* format CMIC_XGXS0_PLL_CONTROL_2fmt */ 8807 /* nFields */ 7, 8808 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_2fmt_fields, 8809 /* bits */ 32, 8810 /* flags */ 0, 8811 }, 8812 #endif /* chips */ 8813 8814 #if defined(BCM_56840_A0) 8815 { /* SOC_FORMAT_INT_CMIC_XGXS0_PLL_CONTROL_3fmt */ 8816 /* format CMIC_XGXS0_PLL_CONTROL_3fmt */ 8817 /* nFields */ 6, 8818 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_3fmt_fields, 8819 /* bits */ 32, 8820 /* flags */ 0, 8821 }, 8822 #endif /* chips */ 8823 8824 #if defined(BCM_56840_A0) 8825 { /* SOC_FORMAT_INT_CMIC_XGXS0_PLL_CONTROL_4fmt */ 8826 /* format CMIC_XGXS0_PLL_CONTROL_4fmt */ 8827 /* nFields */ 16, 8828 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_4fmt_fields, 8829 /* bits */ 32, 8830 /* flags */ 0, 8831 }, 8832 #endif /* chips */ 8833 8834 #if defined(BCM_56260_A0) 8835 { /* SOC_FORMAT_INT_CMIC_XGXS0_PLL_CONTROL_1_BCM56260_A0fmt */ 8836 /* format CMIC_XGXS0_PLL_CONTROL_1fmt */ 8837 /* nFields */ 4, 8838 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_1_BCM56960_A0fmt_fields, 8839 /* bits */ 32, 8840 /* flags */ 0, 8841 }, 8842 #endif /* chips */ 8843 8844 #if defined(BCM_56260_B0) 8845 { /* SOC_FORMAT_INT_CMIC_XGXS0_PLL_CONTROL_1_BCM56260_B0fmt */ 8846 /* format CMIC_XGXS0_PLL_CONTROL_1fmt */ 8847 /* nFields */ 4, 8848 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_1_BCM56960_A0fmt_fields, 8849 /* bits */ 32, 8850 /* flags */ 0, 8851 }, 8852 #endif /* chips */ 8853 8854 #if defined(BCM_56270_A0) 8855 { /* SOC_FORMAT_INT_CMIC_XGXS0_PLL_CONTROL_1_BCM56270_A0fmt */ 8856 /* format CMIC_XGXS0_PLL_CONTROL_1fmt */ 8857 /* nFields */ 4, 8858 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_1_BCM56960_A0fmt_fields, 8859 /* bits */ 32, 8860 /* flags */ 0, 8861 }, 8862 #endif /* chips */ 8863 8864 #if defined(BCM_56340_A0) 8865 { /* SOC_FORMAT_INT_CMIC_XGXS0_PLL_CONTROL_1_BCM56340_A0fmt */ 8866 /* format CMIC_XGXS0_PLL_CONTROL_1fmt */ 8867 /* nFields */ 4, 8868 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_1_BCM56640_A0fmt_fields, 8869 /* bits */ 32, 8870 /* flags */ 0, 8871 }, 8872 #endif /* chips */ 8873 8874 #if defined(BCM_56370_A0) 8875 { /* SOC_FORMAT_INT_CMIC_XGXS0_PLL_CONTROL_1_BCM56370_A0fmt */ 8876 /* format CMIC_XGXS0_PLL_CONTROL_1fmt */ 8877 /* nFields */ 4, 8878 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_1_BCM56960_A0fmt_fields, 8879 /* bits */ 32, 8880 /* flags */ 0, 8881 }, 8882 #endif /* chips */ 8883 8884 #if defined(BCM_56450_A0) 8885 { /* SOC_FORMAT_INT_CMIC_XGXS0_PLL_CONTROL_1_BCM56450_A0fmt */ 8886 /* format CMIC_XGXS0_PLL_CONTROL_1fmt */ 8887 /* nFields */ 4, 8888 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_1_BCM56640_A0fmt_fields, 8889 /* bits */ 32, 8890 /* flags */ 0, 8891 }, 8892 #endif /* chips */ 8893 8894 #if defined(BCM_56450_B0) 8895 { /* SOC_FORMAT_INT_CMIC_XGXS0_PLL_CONTROL_1_BCM56450_B0fmt */ 8896 /* format CMIC_XGXS0_PLL_CONTROL_1fmt */ 8897 /* nFields */ 4, 8898 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_1_BCM56640_A0fmt_fields, 8899 /* bits */ 32, 8900 /* flags */ 0, 8901 }, 8902 #endif /* chips */ 8903 8904 #if defined(BCM_56450_B1) 8905 { /* SOC_FORMAT_INT_CMIC_XGXS0_PLL_CONTROL_1_BCM56450_B1fmt */ 8906 /* format CMIC_XGXS0_PLL_CONTROL_1fmt */ 8907 /* nFields */ 4, 8908 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_1_BCM56640_A0fmt_fields, 8909 /* bits */ 32, 8910 /* flags */ 0, 8911 }, 8912 #endif /* chips */ 8913 8914 #if defined(BCM_56640_A0) 8915 { /* SOC_FORMAT_INT_CMIC_XGXS0_PLL_CONTROL_1_BCM56640_A0fmt */ 8916 /* format CMIC_XGXS0_PLL_CONTROL_1fmt */ 8917 /* nFields */ 4, 8918 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_1_BCM56640_A0fmt_fields, 8919 /* bits */ 32, 8920 /* flags */ 0, 8921 }, 8922 #endif /* chips */ 8923 8924 #if defined(BCM_56770_A0) 8925 { /* SOC_FORMAT_INT_CMIC_XGXS0_PLL_CONTROL_1_BCM56770_A0fmt */ 8926 /* format CMIC_XGXS0_PLL_CONTROL_1fmt */ 8927 /* nFields */ 4, 8928 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_1_BCM56960_A0fmt_fields, 8929 /* bits */ 32, 8930 /* flags */ 0, 8931 }, 8932 #endif /* chips */ 8933 8934 #if defined(BCM_56840_B0) 8935 { /* SOC_FORMAT_INT_CMIC_XGXS0_PLL_CONTROL_1_BCM56840_B0fmt */ 8936 /* format CMIC_XGXS0_PLL_CONTROL_1fmt */ 8937 /* nFields */ 4, 8938 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_1fmt_fields, 8939 /* bits */ 32, 8940 /* flags */ 0, 8941 }, 8942 #endif /* chips */ 8943 8944 #if defined(BCM_56850_A0) 8945 { /* SOC_FORMAT_INT_CMIC_XGXS0_PLL_CONTROL_1_BCM56850_A0fmt */ 8946 /* format CMIC_XGXS0_PLL_CONTROL_1fmt */ 8947 /* nFields */ 4, 8948 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_1_BCM56640_A0fmt_fields, 8949 /* bits */ 32, 8950 /* flags */ 0, 8951 }, 8952 #endif /* chips */ 8953 8954 #if defined(BCM_56860_A0) 8955 { /* SOC_FORMAT_INT_CMIC_XGXS0_PLL_CONTROL_1_BCM56860_A0fmt */ 8956 /* format CMIC_XGXS0_PLL_CONTROL_1fmt */ 8957 /* nFields */ 4, 8958 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_1_BCM56640_A0fmt_fields, 8959 /* bits */ 32, 8960 /* flags */ 0, 8961 }, 8962 #endif /* chips */ 8963 8964 #if defined(BCM_56870_A0) 8965 { /* SOC_FORMAT_INT_CMIC_XGXS0_PLL_CONTROL_1_BCM56870_A0fmt */ 8966 /* format CMIC_XGXS0_PLL_CONTROL_1fmt */ 8967 /* nFields */ 4, 8968 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_1_BCM56960_A0fmt_fields, 8969 /* bits */ 32, 8970 /* flags */ 0, 8971 }, 8972 #endif /* chips */ 8973 8974 #if defined(BCM_56960_A0) 8975 { /* SOC_FORMAT_INT_CMIC_XGXS0_PLL_CONTROL_1_BCM56960_A0fmt */ 8976 /* format CMIC_XGXS0_PLL_CONTROL_1fmt */ 8977 /* nFields */ 4, 8978 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_1_BCM56960_A0fmt_fields, 8979 /* bits */ 32, 8980 /* flags */ 0, 8981 }, 8982 #endif /* chips */ 8983 8984 #if defined(BCM_56965_A0) 8985 { /* SOC_FORMAT_INT_CMIC_XGXS0_PLL_CONTROL_1_BCM56965_A0fmt */ 8986 /* format CMIC_XGXS0_PLL_CONTROL_1fmt */ 8987 /* nFields */ 4, 8988 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_1_BCM56960_A0fmt_fields, 8989 /* bits */ 32, 8990 /* flags */ 0, 8991 }, 8992 #endif /* chips */ 8993 8994 #if defined(BCM_56970_A0) 8995 { /* SOC_FORMAT_INT_CMIC_XGXS0_PLL_CONTROL_1_BCM56970_A0fmt */ 8996 /* format CMIC_XGXS0_PLL_CONTROL_1fmt */ 8997 /* nFields */ 4, 8998 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_1_BCM56960_A0fmt_fields, 8999 /* bits */ 32, 9000 /* flags */ 0, 9001 }, 9002 #endif /* chips */ 9003 9004 #if defined(BCM_88732_A0) 9005 { /* SOC_FORMAT_INT_CMIC_XGXS0_PLL_CONTROL_1_BCM88732_A0fmt */ 9006 /* format CMIC_XGXS0_PLL_CONTROL_1fmt */ 9007 /* nFields */ 10, 9008 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_1_BCM88732_A0fmt_fields, 9009 /* bits */ 32, 9010 /* flags */ 0, 9011 }, 9012 #endif /* chips */ 9013 9014 #if defined(BCM_56260_A0) 9015 { /* SOC_FORMAT_INT_CMIC_XGXS0_PLL_CONTROL_2_BCM56260_A0fmt */ 9016 /* format CMIC_XGXS0_PLL_CONTROL_2fmt */ 9017 /* nFields */ 7, 9018 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_2_BCM56960_A0fmt_fields, 9019 /* bits */ 32, 9020 /* flags */ 0, 9021 }, 9022 #endif /* chips */ 9023 9024 #if defined(BCM_56260_B0) 9025 { /* SOC_FORMAT_INT_CMIC_XGXS0_PLL_CONTROL_2_BCM56260_B0fmt */ 9026 /* format CMIC_XGXS0_PLL_CONTROL_2fmt */ 9027 /* nFields */ 7, 9028 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_2_BCM56960_A0fmt_fields, 9029 /* bits */ 32, 9030 /* flags */ 0, 9031 }, 9032 #endif /* chips */ 9033 9034 #if defined(BCM_56270_A0) 9035 { /* SOC_FORMAT_INT_CMIC_XGXS0_PLL_CONTROL_2_BCM56270_A0fmt */ 9036 /* format CMIC_XGXS0_PLL_CONTROL_2fmt */ 9037 /* nFields */ 7, 9038 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_2_BCM56960_A0fmt_fields, 9039 /* bits */ 32, 9040 /* flags */ 0, 9041 }, 9042 #endif /* chips */ 9043 9044 #if defined(BCM_56340_A0) 9045 { /* SOC_FORMAT_INT_CMIC_XGXS0_PLL_CONTROL_2_BCM56340_A0fmt */ 9046 /* format CMIC_XGXS0_PLL_CONTROL_2fmt */ 9047 /* nFields */ 7, 9048 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_2_BCM56640_A0fmt_fields, 9049 /* bits */ 32, 9050 /* flags */ 0, 9051 }, 9052 #endif /* chips */ 9053 9054 #if defined(BCM_56370_A0) 9055 { /* SOC_FORMAT_INT_CMIC_XGXS0_PLL_CONTROL_2_BCM56370_A0fmt */ 9056 /* format CMIC_XGXS0_PLL_CONTROL_2fmt */ 9057 /* nFields */ 7, 9058 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_2_BCM56960_A0fmt_fields, 9059 /* bits */ 32, 9060 /* flags */ 0, 9061 }, 9062 #endif /* chips */ 9063 9064 #if defined(BCM_56450_A0) 9065 { /* SOC_FORMAT_INT_CMIC_XGXS0_PLL_CONTROL_2_BCM56450_A0fmt */ 9066 /* format CMIC_XGXS0_PLL_CONTROL_2fmt */ 9067 /* nFields */ 7, 9068 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_2_BCM56640_A0fmt_fields, 9069 /* bits */ 32, 9070 /* flags */ 0, 9071 }, 9072 #endif /* chips */ 9073 9074 #if defined(BCM_56450_B0) 9075 { /* SOC_FORMAT_INT_CMIC_XGXS0_PLL_CONTROL_2_BCM56450_B0fmt */ 9076 /* format CMIC_XGXS0_PLL_CONTROL_2fmt */ 9077 /* nFields */ 7, 9078 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_2_BCM56640_A0fmt_fields, 9079 /* bits */ 32, 9080 /* flags */ 0, 9081 }, 9082 #endif /* chips */ 9083 9084 #if defined(BCM_56450_B1) 9085 { /* SOC_FORMAT_INT_CMIC_XGXS0_PLL_CONTROL_2_BCM56450_B1fmt */ 9086 /* format CMIC_XGXS0_PLL_CONTROL_2fmt */ 9087 /* nFields */ 7, 9088 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_2_BCM56640_A0fmt_fields, 9089 /* bits */ 32, 9090 /* flags */ 0, 9091 }, 9092 #endif /* chips */ 9093 9094 #if defined(BCM_56640_A0) 9095 { /* SOC_FORMAT_INT_CMIC_XGXS0_PLL_CONTROL_2_BCM56640_A0fmt */ 9096 /* format CMIC_XGXS0_PLL_CONTROL_2fmt */ 9097 /* nFields */ 7, 9098 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_2_BCM56640_A0fmt_fields, 9099 /* bits */ 32, 9100 /* flags */ 0, 9101 }, 9102 #endif /* chips */ 9103 9104 #if defined(BCM_56770_A0) 9105 { /* SOC_FORMAT_INT_CMIC_XGXS0_PLL_CONTROL_2_BCM56770_A0fmt */ 9106 /* format CMIC_XGXS0_PLL_CONTROL_2fmt */ 9107 /* nFields */ 7, 9108 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_2_BCM56960_A0fmt_fields, 9109 /* bits */ 32, 9110 /* flags */ 0, 9111 }, 9112 #endif /* chips */ 9113 9114 #if defined(BCM_56840_B0) 9115 { /* SOC_FORMAT_INT_CMIC_XGXS0_PLL_CONTROL_2_BCM56840_B0fmt */ 9116 /* format CMIC_XGXS0_PLL_CONTROL_2fmt */ 9117 /* nFields */ 7, 9118 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_2fmt_fields, 9119 /* bits */ 32, 9120 /* flags */ 0, 9121 }, 9122 #endif /* chips */ 9123 9124 #if defined(BCM_56850_A0) 9125 { /* SOC_FORMAT_INT_CMIC_XGXS0_PLL_CONTROL_2_BCM56850_A0fmt */ 9126 /* format CMIC_XGXS0_PLL_CONTROL_2fmt */ 9127 /* nFields */ 7, 9128 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_2_BCM56640_A0fmt_fields, 9129 /* bits */ 32, 9130 /* flags */ 0, 9131 }, 9132 #endif /* chips */ 9133 9134 #if defined(BCM_56860_A0) 9135 { /* SOC_FORMAT_INT_CMIC_XGXS0_PLL_CONTROL_2_BCM56860_A0fmt */ 9136 /* format CMIC_XGXS0_PLL_CONTROL_2fmt */ 9137 /* nFields */ 7, 9138 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_2_BCM56640_A0fmt_fields, 9139 /* bits */ 32, 9140 /* flags */ 0, 9141 }, 9142 #endif /* chips */ 9143 9144 #if defined(BCM_56870_A0) 9145 { /* SOC_FORMAT_INT_CMIC_XGXS0_PLL_CONTROL_2_BCM56870_A0fmt */ 9146 /* format CMIC_XGXS0_PLL_CONTROL_2fmt */ 9147 /* nFields */ 7, 9148 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_2_BCM56960_A0fmt_fields, 9149 /* bits */ 32, 9150 /* flags */ 0, 9151 }, 9152 #endif /* chips */ 9153 9154 #if defined(BCM_56960_A0) 9155 { /* SOC_FORMAT_INT_CMIC_XGXS0_PLL_CONTROL_2_BCM56960_A0fmt */ 9156 /* format CMIC_XGXS0_PLL_CONTROL_2fmt */ 9157 /* nFields */ 7, 9158 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_2_BCM56960_A0fmt_fields, 9159 /* bits */ 32, 9160 /* flags */ 0, 9161 }, 9162 #endif /* chips */ 9163 9164 #if defined(BCM_56965_A0) 9165 { /* SOC_FORMAT_INT_CMIC_XGXS0_PLL_CONTROL_2_BCM56965_A0fmt */ 9166 /* format CMIC_XGXS0_PLL_CONTROL_2fmt */ 9167 /* nFields */ 7, 9168 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_2_BCM56960_A0fmt_fields, 9169 /* bits */ 32, 9170 /* flags */ 0, 9171 }, 9172 #endif /* chips */ 9173 9174 #if defined(BCM_56970_A0) 9175 { /* SOC_FORMAT_INT_CMIC_XGXS0_PLL_CONTROL_2_BCM56970_A0fmt */ 9176 /* format CMIC_XGXS0_PLL_CONTROL_2fmt */ 9177 /* nFields */ 7, 9178 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_2_BCM56960_A0fmt_fields, 9179 /* bits */ 32, 9180 /* flags */ 0, 9181 }, 9182 #endif /* chips */ 9183 9184 #if defined(BCM_88732_A0) 9185 { /* SOC_FORMAT_INT_CMIC_XGXS0_PLL_CONTROL_2_BCM88732_A0fmt */ 9186 /* format CMIC_XGXS0_PLL_CONTROL_2fmt */ 9187 /* nFields */ 14, 9188 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_2_BCM88732_A0fmt_fields, 9189 /* bits */ 32, 9190 /* flags */ 0, 9191 }, 9192 #endif /* chips */ 9193 9194 #if defined(BCM_56260_A0) 9195 { /* SOC_FORMAT_INT_CMIC_XGXS0_PLL_CONTROL_3_BCM56260_A0fmt */ 9196 /* format CMIC_XGXS0_PLL_CONTROL_3fmt */ 9197 /* nFields */ 6, 9198 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_3_BCM56960_A0fmt_fields, 9199 /* bits */ 32, 9200 /* flags */ 0, 9201 }, 9202 #endif /* chips */ 9203 9204 #if defined(BCM_56260_B0) 9205 { /* SOC_FORMAT_INT_CMIC_XGXS0_PLL_CONTROL_3_BCM56260_B0fmt */ 9206 /* format CMIC_XGXS0_PLL_CONTROL_3fmt */ 9207 /* nFields */ 6, 9208 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_3_BCM56960_A0fmt_fields, 9209 /* bits */ 32, 9210 /* flags */ 0, 9211 }, 9212 #endif /* chips */ 9213 9214 #if defined(BCM_56270_A0) 9215 { /* SOC_FORMAT_INT_CMIC_XGXS0_PLL_CONTROL_3_BCM56270_A0fmt */ 9216 /* format CMIC_XGXS0_PLL_CONTROL_3fmt */ 9217 /* nFields */ 6, 9218 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_3_BCM56960_A0fmt_fields, 9219 /* bits */ 32, 9220 /* flags */ 0, 9221 }, 9222 #endif /* chips */ 9223 9224 #if defined(BCM_56340_A0) 9225 { /* SOC_FORMAT_INT_CMIC_XGXS0_PLL_CONTROL_3_BCM56340_A0fmt */ 9226 /* format CMIC_XGXS0_PLL_CONTROL_3fmt */ 9227 /* nFields */ 6, 9228 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_3_BCM56640_A0fmt_fields, 9229 /* bits */ 32, 9230 /* flags */ 0, 9231 }, 9232 #endif /* chips */ 9233 9234 #if defined(BCM_56370_A0) 9235 { /* SOC_FORMAT_INT_CMIC_XGXS0_PLL_CONTROL_3_BCM56370_A0fmt */ 9236 /* format CMIC_XGXS0_PLL_CONTROL_3fmt */ 9237 /* nFields */ 6, 9238 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_3_BCM56960_A0fmt_fields, 9239 /* bits */ 32, 9240 /* flags */ 0, 9241 }, 9242 #endif /* chips */ 9243 9244 #if defined(BCM_56450_A0) 9245 { /* SOC_FORMAT_INT_CMIC_XGXS0_PLL_CONTROL_3_BCM56450_A0fmt */ 9246 /* format CMIC_XGXS0_PLL_CONTROL_3fmt */ 9247 /* nFields */ 6, 9248 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_3_BCM56640_A0fmt_fields, 9249 /* bits */ 32, 9250 /* flags */ 0, 9251 }, 9252 #endif /* chips */ 9253 9254 #if defined(BCM_56450_B0) 9255 { /* SOC_FORMAT_INT_CMIC_XGXS0_PLL_CONTROL_3_BCM56450_B0fmt */ 9256 /* format CMIC_XGXS0_PLL_CONTROL_3fmt */ 9257 /* nFields */ 6, 9258 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_3_BCM56640_A0fmt_fields, 9259 /* bits */ 32, 9260 /* flags */ 0, 9261 }, 9262 #endif /* chips */ 9263 9264 #if defined(BCM_56450_B1) 9265 { /* SOC_FORMAT_INT_CMIC_XGXS0_PLL_CONTROL_3_BCM56450_B1fmt */ 9266 /* format CMIC_XGXS0_PLL_CONTROL_3fmt */ 9267 /* nFields */ 6, 9268 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_3_BCM56640_A0fmt_fields, 9269 /* bits */ 32, 9270 /* flags */ 0, 9271 }, 9272 #endif /* chips */ 9273 9274 #if defined(BCM_56640_A0) 9275 { /* SOC_FORMAT_INT_CMIC_XGXS0_PLL_CONTROL_3_BCM56640_A0fmt */ 9276 /* format CMIC_XGXS0_PLL_CONTROL_3fmt */ 9277 /* nFields */ 6, 9278 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_3_BCM56640_A0fmt_fields, 9279 /* bits */ 32, 9280 /* flags */ 0, 9281 }, 9282 #endif /* chips */ 9283 9284 #if defined(BCM_56770_A0) 9285 { /* SOC_FORMAT_INT_CMIC_XGXS0_PLL_CONTROL_3_BCM56770_A0fmt */ 9286 /* format CMIC_XGXS0_PLL_CONTROL_3fmt */ 9287 /* nFields */ 6, 9288 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_3_BCM56960_A0fmt_fields, 9289 /* bits */ 32, 9290 /* flags */ 0, 9291 }, 9292 #endif /* chips */ 9293 9294 #if defined(BCM_56840_B0) 9295 { /* SOC_FORMAT_INT_CMIC_XGXS0_PLL_CONTROL_3_BCM56840_B0fmt */ 9296 /* format CMIC_XGXS0_PLL_CONTROL_3fmt */ 9297 /* nFields */ 6, 9298 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_3fmt_fields, 9299 /* bits */ 32, 9300 /* flags */ 0, 9301 }, 9302 #endif /* chips */ 9303 9304 #if defined(BCM_56850_A0) 9305 { /* SOC_FORMAT_INT_CMIC_XGXS0_PLL_CONTROL_3_BCM56850_A0fmt */ 9306 /* format CMIC_XGXS0_PLL_CONTROL_3fmt */ 9307 /* nFields */ 6, 9308 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_3_BCM56640_A0fmt_fields, 9309 /* bits */ 32, 9310 /* flags */ 0, 9311 }, 9312 #endif /* chips */ 9313 9314 #if defined(BCM_56860_A0) 9315 { /* SOC_FORMAT_INT_CMIC_XGXS0_PLL_CONTROL_3_BCM56860_A0fmt */ 9316 /* format CMIC_XGXS0_PLL_CONTROL_3fmt */ 9317 /* nFields */ 6, 9318 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_3_BCM56640_A0fmt_fields, 9319 /* bits */ 32, 9320 /* flags */ 0, 9321 }, 9322 #endif /* chips */ 9323 9324 #if defined(BCM_56870_A0) 9325 { /* SOC_FORMAT_INT_CMIC_XGXS0_PLL_CONTROL_3_BCM56870_A0fmt */ 9326 /* format CMIC_XGXS0_PLL_CONTROL_3fmt */ 9327 /* nFields */ 6, 9328 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_3_BCM56960_A0fmt_fields, 9329 /* bits */ 32, 9330 /* flags */ 0, 9331 }, 9332 #endif /* chips */ 9333 9334 #if defined(BCM_56960_A0) 9335 { /* SOC_FORMAT_INT_CMIC_XGXS0_PLL_CONTROL_3_BCM56960_A0fmt */ 9336 /* format CMIC_XGXS0_PLL_CONTROL_3fmt */ 9337 /* nFields */ 6, 9338 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_3_BCM56960_A0fmt_fields, 9339 /* bits */ 32, 9340 /* flags */ 0, 9341 }, 9342 #endif /* chips */ 9343 9344 #if defined(BCM_56965_A0) 9345 { /* SOC_FORMAT_INT_CMIC_XGXS0_PLL_CONTROL_3_BCM56965_A0fmt */ 9346 /* format CMIC_XGXS0_PLL_CONTROL_3fmt */ 9347 /* nFields */ 6, 9348 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_3_BCM56960_A0fmt_fields, 9349 /* bits */ 32, 9350 /* flags */ 0, 9351 }, 9352 #endif /* chips */ 9353 9354 #if defined(BCM_56970_A0) 9355 { /* SOC_FORMAT_INT_CMIC_XGXS0_PLL_CONTROL_3_BCM56970_A0fmt */ 9356 /* format CMIC_XGXS0_PLL_CONTROL_3fmt */ 9357 /* nFields */ 6, 9358 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_3_BCM56960_A0fmt_fields, 9359 /* bits */ 32, 9360 /* flags */ 0, 9361 }, 9362 #endif /* chips */ 9363 9364 #if defined(BCM_88732_A0) 9365 { /* SOC_FORMAT_INT_CMIC_XGXS0_PLL_CONTROL_3_BCM88732_A0fmt */ 9366 /* format CMIC_XGXS0_PLL_CONTROL_3fmt */ 9367 /* nFields */ 4, 9368 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_3_BCM88732_A0fmt_fields, 9369 /* bits */ 32, 9370 /* flags */ 0, 9371 }, 9372 #endif /* chips */ 9373 9374 #if defined(BCM_56260_A0) 9375 { /* SOC_FORMAT_INT_CMIC_XGXS0_PLL_CONTROL_4_BCM56260_A0fmt */ 9376 /* format CMIC_XGXS0_PLL_CONTROL_4fmt */ 9377 /* nFields */ 16, 9378 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_4_BCM56960_A0fmt_fields, 9379 /* bits */ 32, 9380 /* flags */ 0, 9381 }, 9382 #endif /* chips */ 9383 9384 #if defined(BCM_56260_B0) 9385 { /* SOC_FORMAT_INT_CMIC_XGXS0_PLL_CONTROL_4_BCM56260_B0fmt */ 9386 /* format CMIC_XGXS0_PLL_CONTROL_4fmt */ 9387 /* nFields */ 16, 9388 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_4_BCM56960_A0fmt_fields, 9389 /* bits */ 32, 9390 /* flags */ 0, 9391 }, 9392 #endif /* chips */ 9393 9394 #if defined(BCM_56270_A0) 9395 { /* SOC_FORMAT_INT_CMIC_XGXS0_PLL_CONTROL_4_BCM56270_A0fmt */ 9396 /* format CMIC_XGXS0_PLL_CONTROL_4fmt */ 9397 /* nFields */ 16, 9398 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_4_BCM56960_A0fmt_fields, 9399 /* bits */ 32, 9400 /* flags */ 0, 9401 }, 9402 #endif /* chips */ 9403 9404 #if defined(BCM_56340_A0) 9405 { /* SOC_FORMAT_INT_CMIC_XGXS0_PLL_CONTROL_4_BCM56340_A0fmt */ 9406 /* format CMIC_XGXS0_PLL_CONTROL_4fmt */ 9407 /* nFields */ 16, 9408 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_4_BCM56640_A0fmt_fields, 9409 /* bits */ 32, 9410 /* flags */ 0, 9411 }, 9412 #endif /* chips */ 9413 9414 #if defined(BCM_56370_A0) 9415 { /* SOC_FORMAT_INT_CMIC_XGXS0_PLL_CONTROL_4_BCM56370_A0fmt */ 9416 /* format CMIC_XGXS0_PLL_CONTROL_4fmt */ 9417 /* nFields */ 16, 9418 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_4_BCM56960_A0fmt_fields, 9419 /* bits */ 32, 9420 /* flags */ 0, 9421 }, 9422 #endif /* chips */ 9423 9424 #if defined(BCM_56450_A0) 9425 { /* SOC_FORMAT_INT_CMIC_XGXS0_PLL_CONTROL_4_BCM56450_A0fmt */ 9426 /* format CMIC_XGXS0_PLL_CONTROL_4fmt */ 9427 /* nFields */ 16, 9428 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_4_BCM56640_A0fmt_fields, 9429 /* bits */ 32, 9430 /* flags */ 0, 9431 }, 9432 #endif /* chips */ 9433 9434 #if defined(BCM_56450_B0) 9435 { /* SOC_FORMAT_INT_CMIC_XGXS0_PLL_CONTROL_4_BCM56450_B0fmt */ 9436 /* format CMIC_XGXS0_PLL_CONTROL_4fmt */ 9437 /* nFields */ 16, 9438 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_4_BCM56640_A0fmt_fields, 9439 /* bits */ 32, 9440 /* flags */ 0, 9441 }, 9442 #endif /* chips */ 9443 9444 #if defined(BCM_56450_B1) 9445 { /* SOC_FORMAT_INT_CMIC_XGXS0_PLL_CONTROL_4_BCM56450_B1fmt */ 9446 /* format CMIC_XGXS0_PLL_CONTROL_4fmt */ 9447 /* nFields */ 16, 9448 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_4_BCM56640_A0fmt_fields, 9449 /* bits */ 32, 9450 /* flags */ 0, 9451 }, 9452 #endif /* chips */ 9453 9454 #if defined(BCM_56640_A0) 9455 { /* SOC_FORMAT_INT_CMIC_XGXS0_PLL_CONTROL_4_BCM56640_A0fmt */ 9456 /* format CMIC_XGXS0_PLL_CONTROL_4fmt */ 9457 /* nFields */ 16, 9458 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_4_BCM56640_A0fmt_fields, 9459 /* bits */ 32, 9460 /* flags */ 0, 9461 }, 9462 #endif /* chips */ 9463 9464 #if defined(BCM_56770_A0) 9465 { /* SOC_FORMAT_INT_CMIC_XGXS0_PLL_CONTROL_4_BCM56770_A0fmt */ 9466 /* format CMIC_XGXS0_PLL_CONTROL_4fmt */ 9467 /* nFields */ 16, 9468 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_4_BCM56960_A0fmt_fields, 9469 /* bits */ 32, 9470 /* flags */ 0, 9471 }, 9472 #endif /* chips */ 9473 9474 #if defined(BCM_56840_B0) 9475 { /* SOC_FORMAT_INT_CMIC_XGXS0_PLL_CONTROL_4_BCM56840_B0fmt */ 9476 /* format CMIC_XGXS0_PLL_CONTROL_4fmt */ 9477 /* nFields */ 16, 9478 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_4fmt_fields, 9479 /* bits */ 32, 9480 /* flags */ 0, 9481 }, 9482 #endif /* chips */ 9483 9484 #if defined(BCM_56850_A0) 9485 { /* SOC_FORMAT_INT_CMIC_XGXS0_PLL_CONTROL_4_BCM56850_A0fmt */ 9486 /* format CMIC_XGXS0_PLL_CONTROL_4fmt */ 9487 /* nFields */ 16, 9488 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_4_BCM56640_A0fmt_fields, 9489 /* bits */ 32, 9490 /* flags */ 0, 9491 }, 9492 #endif /* chips */ 9493 9494 #if defined(BCM_56860_A0) 9495 { /* SOC_FORMAT_INT_CMIC_XGXS0_PLL_CONTROL_4_BCM56860_A0fmt */ 9496 /* format CMIC_XGXS0_PLL_CONTROL_4fmt */ 9497 /* nFields */ 16, 9498 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_4_BCM56640_A0fmt_fields, 9499 /* bits */ 32, 9500 /* flags */ 0, 9501 }, 9502 #endif /* chips */ 9503 9504 #if defined(BCM_56870_A0) 9505 { /* SOC_FORMAT_INT_CMIC_XGXS0_PLL_CONTROL_4_BCM56870_A0fmt */ 9506 /* format CMIC_XGXS0_PLL_CONTROL_4fmt */ 9507 /* nFields */ 16, 9508 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_4_BCM56960_A0fmt_fields, 9509 /* bits */ 32, 9510 /* flags */ 0, 9511 }, 9512 #endif /* chips */ 9513 9514 #if defined(BCM_56960_A0) 9515 { /* SOC_FORMAT_INT_CMIC_XGXS0_PLL_CONTROL_4_BCM56960_A0fmt */ 9516 /* format CMIC_XGXS0_PLL_CONTROL_4fmt */ 9517 /* nFields */ 16, 9518 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_4_BCM56960_A0fmt_fields, 9519 /* bits */ 32, 9520 /* flags */ 0, 9521 }, 9522 #endif /* chips */ 9523 9524 #if defined(BCM_56965_A0) 9525 { /* SOC_FORMAT_INT_CMIC_XGXS0_PLL_CONTROL_4_BCM56965_A0fmt */ 9526 /* format CMIC_XGXS0_PLL_CONTROL_4fmt */ 9527 /* nFields */ 16, 9528 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_4_BCM56960_A0fmt_fields, 9529 /* bits */ 32, 9530 /* flags */ 0, 9531 }, 9532 #endif /* chips */ 9533 9534 #if defined(BCM_56970_A0) 9535 { /* SOC_FORMAT_INT_CMIC_XGXS0_PLL_CONTROL_4_BCM56970_A0fmt */ 9536 /* format CMIC_XGXS0_PLL_CONTROL_4fmt */ 9537 /* nFields */ 16, 9538 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_4_BCM56960_A0fmt_fields, 9539 /* bits */ 32, 9540 /* flags */ 0, 9541 }, 9542 #endif /* chips */ 9543 9544 #if defined(BCM_88732_A0) 9545 { /* SOC_FORMAT_INT_CMIC_XGXS0_PLL_CONTROL_4_BCM88732_A0fmt */ 9546 /* format CMIC_XGXS0_PLL_CONTROL_4fmt */ 9547 /* nFields */ 16, 9548 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_4_BCM88732_A0fmt_fields, 9549 /* bits */ 32, 9550 /* flags */ 0, 9551 }, 9552 #endif /* chips */ 9553 9554 #if defined(BCM_56840_A0) 9555 { /* SOC_FORMAT_INT_CMIC_XGXS1_PLL_CONTROL_1fmt */ 9556 /* format CMIC_XGXS1_PLL_CONTROL_1fmt */ 9557 /* nFields */ 4, 9558 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_1fmt_fields, 9559 /* bits */ 32, 9560 /* flags */ 0, 9561 }, 9562 #endif /* chips */ 9563 9564 #if defined(BCM_56840_A0) 9565 { /* SOC_FORMAT_INT_CMIC_XGXS1_PLL_CONTROL_2fmt */ 9566 /* format CMIC_XGXS1_PLL_CONTROL_2fmt */ 9567 /* nFields */ 7, 9568 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_2fmt_fields, 9569 /* bits */ 32, 9570 /* flags */ 0, 9571 }, 9572 #endif /* chips */ 9573 9574 #if defined(BCM_56840_A0) 9575 { /* SOC_FORMAT_INT_CMIC_XGXS1_PLL_CONTROL_3fmt */ 9576 /* format CMIC_XGXS1_PLL_CONTROL_3fmt */ 9577 /* nFields */ 6, 9578 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_3fmt_fields, 9579 /* bits */ 32, 9580 /* flags */ 0, 9581 }, 9582 #endif /* chips */ 9583 9584 #if defined(BCM_56840_A0) 9585 { /* SOC_FORMAT_INT_CMIC_XGXS1_PLL_CONTROL_4fmt */ 9586 /* format CMIC_XGXS1_PLL_CONTROL_4fmt */ 9587 /* nFields */ 16, 9588 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_4fmt_fields, 9589 /* bits */ 32, 9590 /* flags */ 0, 9591 }, 9592 #endif /* chips */ 9593 9594 #if defined(BCM_56260_A0) 9595 { /* SOC_FORMAT_INT_CMIC_XGXS1_PLL_CONTROL_1_BCM56260_A0fmt */ 9596 /* format CMIC_XGXS1_PLL_CONTROL_1fmt */ 9597 /* nFields */ 4, 9598 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_1_BCM56960_A0fmt_fields, 9599 /* bits */ 32, 9600 /* flags */ 0, 9601 }, 9602 #endif /* chips */ 9603 9604 #if defined(BCM_56260_B0) 9605 { /* SOC_FORMAT_INT_CMIC_XGXS1_PLL_CONTROL_1_BCM56260_B0fmt */ 9606 /* format CMIC_XGXS1_PLL_CONTROL_1fmt */ 9607 /* nFields */ 4, 9608 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_1_BCM56960_A0fmt_fields, 9609 /* bits */ 32, 9610 /* flags */ 0, 9611 }, 9612 #endif /* chips */ 9613 9614 #if defined(BCM_56270_A0) 9615 { /* SOC_FORMAT_INT_CMIC_XGXS1_PLL_CONTROL_1_BCM56270_A0fmt */ 9616 /* format CMIC_XGXS1_PLL_CONTROL_1fmt */ 9617 /* nFields */ 4, 9618 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_1_BCM56960_A0fmt_fields, 9619 /* bits */ 32, 9620 /* flags */ 0, 9621 }, 9622 #endif /* chips */ 9623 9624 #if defined(BCM_56340_A0) 9625 { /* SOC_FORMAT_INT_CMIC_XGXS1_PLL_CONTROL_1_BCM56340_A0fmt */ 9626 /* format CMIC_XGXS1_PLL_CONTROL_1fmt */ 9627 /* nFields */ 4, 9628 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_1_BCM56640_A0fmt_fields, 9629 /* bits */ 32, 9630 /* flags */ 0, 9631 }, 9632 #endif /* chips */ 9633 9634 #if defined(BCM_56370_A0) 9635 { /* SOC_FORMAT_INT_CMIC_XGXS1_PLL_CONTROL_1_BCM56370_A0fmt */ 9636 /* format CMIC_XGXS1_PLL_CONTROL_1fmt */ 9637 /* nFields */ 4, 9638 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_1_BCM56960_A0fmt_fields, 9639 /* bits */ 32, 9640 /* flags */ 0, 9641 }, 9642 #endif /* chips */ 9643 9644 #if defined(BCM_56450_A0) 9645 { /* SOC_FORMAT_INT_CMIC_XGXS1_PLL_CONTROL_1_BCM56450_A0fmt */ 9646 /* format CMIC_XGXS1_PLL_CONTROL_1fmt */ 9647 /* nFields */ 4, 9648 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_1_BCM56640_A0fmt_fields, 9649 /* bits */ 32, 9650 /* flags */ 0, 9651 }, 9652 #endif /* chips */ 9653 9654 #if defined(BCM_56450_B0) 9655 { /* SOC_FORMAT_INT_CMIC_XGXS1_PLL_CONTROL_1_BCM56450_B0fmt */ 9656 /* format CMIC_XGXS1_PLL_CONTROL_1fmt */ 9657 /* nFields */ 4, 9658 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_1_BCM56640_A0fmt_fields, 9659 /* bits */ 32, 9660 /* flags */ 0, 9661 }, 9662 #endif /* chips */ 9663 9664 #if defined(BCM_56450_B1) 9665 { /* SOC_FORMAT_INT_CMIC_XGXS1_PLL_CONTROL_1_BCM56450_B1fmt */ 9666 /* format CMIC_XGXS1_PLL_CONTROL_1fmt */ 9667 /* nFields */ 4, 9668 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_1_BCM56640_A0fmt_fields, 9669 /* bits */ 32, 9670 /* flags */ 0, 9671 }, 9672 #endif /* chips */ 9673 9674 #if defined(BCM_56640_A0) 9675 { /* SOC_FORMAT_INT_CMIC_XGXS1_PLL_CONTROL_1_BCM56640_A0fmt */ 9676 /* format CMIC_XGXS1_PLL_CONTROL_1fmt */ 9677 /* nFields */ 4, 9678 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_1_BCM56640_A0fmt_fields, 9679 /* bits */ 32, 9680 /* flags */ 0, 9681 }, 9682 #endif /* chips */ 9683 9684 #if defined(BCM_56770_A0) 9685 { /* SOC_FORMAT_INT_CMIC_XGXS1_PLL_CONTROL_1_BCM56770_A0fmt */ 9686 /* format CMIC_XGXS1_PLL_CONTROL_1fmt */ 9687 /* nFields */ 4, 9688 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_1_BCM56960_A0fmt_fields, 9689 /* bits */ 32, 9690 /* flags */ 0, 9691 }, 9692 #endif /* chips */ 9693 9694 #if defined(BCM_56840_B0) 9695 { /* SOC_FORMAT_INT_CMIC_XGXS1_PLL_CONTROL_1_BCM56840_B0fmt */ 9696 /* format CMIC_XGXS1_PLL_CONTROL_1fmt */ 9697 /* nFields */ 4, 9698 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_1fmt_fields, 9699 /* bits */ 32, 9700 /* flags */ 0, 9701 }, 9702 #endif /* chips */ 9703 9704 #if defined(BCM_56850_A0) 9705 { /* SOC_FORMAT_INT_CMIC_XGXS1_PLL_CONTROL_1_BCM56850_A0fmt */ 9706 /* format CMIC_XGXS1_PLL_CONTROL_1fmt */ 9707 /* nFields */ 4, 9708 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_1_BCM56640_A0fmt_fields, 9709 /* bits */ 32, 9710 /* flags */ 0, 9711 }, 9712 #endif /* chips */ 9713 9714 #if defined(BCM_56860_A0) 9715 { /* SOC_FORMAT_INT_CMIC_XGXS1_PLL_CONTROL_1_BCM56860_A0fmt */ 9716 /* format CMIC_XGXS1_PLL_CONTROL_1fmt */ 9717 /* nFields */ 4, 9718 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_1_BCM56640_A0fmt_fields, 9719 /* bits */ 32, 9720 /* flags */ 0, 9721 }, 9722 #endif /* chips */ 9723 9724 #if defined(BCM_56870_A0) 9725 { /* SOC_FORMAT_INT_CMIC_XGXS1_PLL_CONTROL_1_BCM56870_A0fmt */ 9726 /* format CMIC_XGXS1_PLL_CONTROL_1fmt */ 9727 /* nFields */ 4, 9728 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_1_BCM56960_A0fmt_fields, 9729 /* bits */ 32, 9730 /* flags */ 0, 9731 }, 9732 #endif /* chips */ 9733 9734 #if defined(BCM_56960_A0) 9735 { /* SOC_FORMAT_INT_CMIC_XGXS1_PLL_CONTROL_1_BCM56960_A0fmt */ 9736 /* format CMIC_XGXS1_PLL_CONTROL_1fmt */ 9737 /* nFields */ 4, 9738 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_1_BCM56960_A0fmt_fields, 9739 /* bits */ 32, 9740 /* flags */ 0, 9741 }, 9742 #endif /* chips */ 9743 9744 #if defined(BCM_56965_A0) 9745 { /* SOC_FORMAT_INT_CMIC_XGXS1_PLL_CONTROL_1_BCM56965_A0fmt */ 9746 /* format CMIC_XGXS1_PLL_CONTROL_1fmt */ 9747 /* nFields */ 4, 9748 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_1_BCM56960_A0fmt_fields, 9749 /* bits */ 32, 9750 /* flags */ 0, 9751 }, 9752 #endif /* chips */ 9753 9754 #if defined(BCM_56970_A0) 9755 { /* SOC_FORMAT_INT_CMIC_XGXS1_PLL_CONTROL_1_BCM56970_A0fmt */ 9756 /* format CMIC_XGXS1_PLL_CONTROL_1fmt */ 9757 /* nFields */ 4, 9758 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_1_BCM56960_A0fmt_fields, 9759 /* bits */ 32, 9760 /* flags */ 0, 9761 }, 9762 #endif /* chips */ 9763 9764 #if defined(BCM_88732_A0) 9765 { /* SOC_FORMAT_INT_CMIC_XGXS1_PLL_CONTROL_1_BCM88732_A0fmt */ 9766 /* format CMIC_XGXS1_PLL_CONTROL_1fmt */ 9767 /* nFields */ 10, 9768 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_1_BCM88732_A0fmt_fields, 9769 /* bits */ 32, 9770 /* flags */ 0, 9771 }, 9772 #endif /* chips */ 9773 9774 #if defined(BCM_56260_A0) 9775 { /* SOC_FORMAT_INT_CMIC_XGXS1_PLL_CONTROL_2_BCM56260_A0fmt */ 9776 /* format CMIC_XGXS1_PLL_CONTROL_2fmt */ 9777 /* nFields */ 7, 9778 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_2_BCM56960_A0fmt_fields, 9779 /* bits */ 32, 9780 /* flags */ 0, 9781 }, 9782 #endif /* chips */ 9783 9784 #if defined(BCM_56260_B0) 9785 { /* SOC_FORMAT_INT_CMIC_XGXS1_PLL_CONTROL_2_BCM56260_B0fmt */ 9786 /* format CMIC_XGXS1_PLL_CONTROL_2fmt */ 9787 /* nFields */ 7, 9788 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_2_BCM56960_A0fmt_fields, 9789 /* bits */ 32, 9790 /* flags */ 0, 9791 }, 9792 #endif /* chips */ 9793 9794 #if defined(BCM_56270_A0) 9795 { /* SOC_FORMAT_INT_CMIC_XGXS1_PLL_CONTROL_2_BCM56270_A0fmt */ 9796 /* format CMIC_XGXS1_PLL_CONTROL_2fmt */ 9797 /* nFields */ 7, 9798 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_2_BCM56960_A0fmt_fields, 9799 /* bits */ 32, 9800 /* flags */ 0, 9801 }, 9802 #endif /* chips */ 9803 9804 #if defined(BCM_56340_A0) 9805 { /* SOC_FORMAT_INT_CMIC_XGXS1_PLL_CONTROL_2_BCM56340_A0fmt */ 9806 /* format CMIC_XGXS1_PLL_CONTROL_2fmt */ 9807 /* nFields */ 7, 9808 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_2_BCM56640_A0fmt_fields, 9809 /* bits */ 32, 9810 /* flags */ 0, 9811 }, 9812 #endif /* chips */ 9813 9814 #if defined(BCM_56370_A0) 9815 { /* SOC_FORMAT_INT_CMIC_XGXS1_PLL_CONTROL_2_BCM56370_A0fmt */ 9816 /* format CMIC_XGXS1_PLL_CONTROL_2fmt */ 9817 /* nFields */ 7, 9818 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_2_BCM56960_A0fmt_fields, 9819 /* bits */ 32, 9820 /* flags */ 0, 9821 }, 9822 #endif /* chips */ 9823 9824 #if defined(BCM_56450_A0) 9825 { /* SOC_FORMAT_INT_CMIC_XGXS1_PLL_CONTROL_2_BCM56450_A0fmt */ 9826 /* format CMIC_XGXS1_PLL_CONTROL_2fmt */ 9827 /* nFields */ 7, 9828 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_2_BCM56640_A0fmt_fields, 9829 /* bits */ 32, 9830 /* flags */ 0, 9831 }, 9832 #endif /* chips */ 9833 9834 #if defined(BCM_56450_B0) 9835 { /* SOC_FORMAT_INT_CMIC_XGXS1_PLL_CONTROL_2_BCM56450_B0fmt */ 9836 /* format CMIC_XGXS1_PLL_CONTROL_2fmt */ 9837 /* nFields */ 7, 9838 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_2_BCM56640_A0fmt_fields, 9839 /* bits */ 32, 9840 /* flags */ 0, 9841 }, 9842 #endif /* chips */ 9843 9844 #if defined(BCM_56450_B1) 9845 { /* SOC_FORMAT_INT_CMIC_XGXS1_PLL_CONTROL_2_BCM56450_B1fmt */ 9846 /* format CMIC_XGXS1_PLL_CONTROL_2fmt */ 9847 /* nFields */ 7, 9848 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_2_BCM56640_A0fmt_fields, 9849 /* bits */ 32, 9850 /* flags */ 0, 9851 }, 9852 #endif /* chips */ 9853 9854 #if defined(BCM_56640_A0) 9855 { /* SOC_FORMAT_INT_CMIC_XGXS1_PLL_CONTROL_2_BCM56640_A0fmt */ 9856 /* format CMIC_XGXS1_PLL_CONTROL_2fmt */ 9857 /* nFields */ 7, 9858 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_2_BCM56640_A0fmt_fields, 9859 /* bits */ 32, 9860 /* flags */ 0, 9861 }, 9862 #endif /* chips */ 9863 9864 #if defined(BCM_56770_A0) 9865 { /* SOC_FORMAT_INT_CMIC_XGXS1_PLL_CONTROL_2_BCM56770_A0fmt */ 9866 /* format CMIC_XGXS1_PLL_CONTROL_2fmt */ 9867 /* nFields */ 7, 9868 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_2_BCM56960_A0fmt_fields, 9869 /* bits */ 32, 9870 /* flags */ 0, 9871 }, 9872 #endif /* chips */ 9873 9874 #if defined(BCM_56840_B0) 9875 { /* SOC_FORMAT_INT_CMIC_XGXS1_PLL_CONTROL_2_BCM56840_B0fmt */ 9876 /* format CMIC_XGXS1_PLL_CONTROL_2fmt */ 9877 /* nFields */ 7, 9878 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_2fmt_fields, 9879 /* bits */ 32, 9880 /* flags */ 0, 9881 }, 9882 #endif /* chips */ 9883 9884 #if defined(BCM_56850_A0) 9885 { /* SOC_FORMAT_INT_CMIC_XGXS1_PLL_CONTROL_2_BCM56850_A0fmt */ 9886 /* format CMIC_XGXS1_PLL_CONTROL_2fmt */ 9887 /* nFields */ 7, 9888 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_2_BCM56640_A0fmt_fields, 9889 /* bits */ 32, 9890 /* flags */ 0, 9891 }, 9892 #endif /* chips */ 9893 9894 #if defined(BCM_56860_A0) 9895 { /* SOC_FORMAT_INT_CMIC_XGXS1_PLL_CONTROL_2_BCM56860_A0fmt */ 9896 /* format CMIC_XGXS1_PLL_CONTROL_2fmt */ 9897 /* nFields */ 7, 9898 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_2_BCM56640_A0fmt_fields, 9899 /* bits */ 32, 9900 /* flags */ 0, 9901 }, 9902 #endif /* chips */ 9903 9904 #if defined(BCM_56870_A0) 9905 { /* SOC_FORMAT_INT_CMIC_XGXS1_PLL_CONTROL_2_BCM56870_A0fmt */ 9906 /* format CMIC_XGXS1_PLL_CONTROL_2fmt */ 9907 /* nFields */ 7, 9908 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_2_BCM56960_A0fmt_fields, 9909 /* bits */ 32, 9910 /* flags */ 0, 9911 }, 9912 #endif /* chips */ 9913 9914 #if defined(BCM_56960_A0) 9915 { /* SOC_FORMAT_INT_CMIC_XGXS1_PLL_CONTROL_2_BCM56960_A0fmt */ 9916 /* format CMIC_XGXS1_PLL_CONTROL_2fmt */ 9917 /* nFields */ 7, 9918 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_2_BCM56960_A0fmt_fields, 9919 /* bits */ 32, 9920 /* flags */ 0, 9921 }, 9922 #endif /* chips */ 9923 9924 #if defined(BCM_56965_A0) 9925 { /* SOC_FORMAT_INT_CMIC_XGXS1_PLL_CONTROL_2_BCM56965_A0fmt */ 9926 /* format CMIC_XGXS1_PLL_CONTROL_2fmt */ 9927 /* nFields */ 7, 9928 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_2_BCM56960_A0fmt_fields, 9929 /* bits */ 32, 9930 /* flags */ 0, 9931 }, 9932 #endif /* chips */ 9933 9934 #if defined(BCM_56970_A0) 9935 { /* SOC_FORMAT_INT_CMIC_XGXS1_PLL_CONTROL_2_BCM56970_A0fmt */ 9936 /* format CMIC_XGXS1_PLL_CONTROL_2fmt */ 9937 /* nFields */ 7, 9938 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_2_BCM56960_A0fmt_fields, 9939 /* bits */ 32, 9940 /* flags */ 0, 9941 }, 9942 #endif /* chips */ 9943 9944 #if defined(BCM_88732_A0) 9945 { /* SOC_FORMAT_INT_CMIC_XGXS1_PLL_CONTROL_2_BCM88732_A0fmt */ 9946 /* format CMIC_XGXS1_PLL_CONTROL_2fmt */ 9947 /* nFields */ 14, 9948 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_2_BCM88732_A0fmt_fields, 9949 /* bits */ 32, 9950 /* flags */ 0, 9951 }, 9952 #endif /* chips */ 9953 9954 #if defined(BCM_56260_A0) 9955 { /* SOC_FORMAT_INT_CMIC_XGXS1_PLL_CONTROL_3_BCM56260_A0fmt */ 9956 /* format CMIC_XGXS1_PLL_CONTROL_3fmt */ 9957 /* nFields */ 6, 9958 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_3_BCM56960_A0fmt_fields, 9959 /* bits */ 32, 9960 /* flags */ 0, 9961 }, 9962 #endif /* chips */ 9963 9964 #if defined(BCM_56260_B0) 9965 { /* SOC_FORMAT_INT_CMIC_XGXS1_PLL_CONTROL_3_BCM56260_B0fmt */ 9966 /* format CMIC_XGXS1_PLL_CONTROL_3fmt */ 9967 /* nFields */ 6, 9968 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_3_BCM56960_A0fmt_fields, 9969 /* bits */ 32, 9970 /* flags */ 0, 9971 }, 9972 #endif /* chips */ 9973 9974 #if defined(BCM_56270_A0) 9975 { /* SOC_FORMAT_INT_CMIC_XGXS1_PLL_CONTROL_3_BCM56270_A0fmt */ 9976 /* format CMIC_XGXS1_PLL_CONTROL_3fmt */ 9977 /* nFields */ 6, 9978 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_3_BCM56960_A0fmt_fields, 9979 /* bits */ 32, 9980 /* flags */ 0, 9981 }, 9982 #endif /* chips */ 9983 9984 #if defined(BCM_56340_A0) 9985 { /* SOC_FORMAT_INT_CMIC_XGXS1_PLL_CONTROL_3_BCM56340_A0fmt */ 9986 /* format CMIC_XGXS1_PLL_CONTROL_3fmt */ 9987 /* nFields */ 6, 9988 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_3_BCM56640_A0fmt_fields, 9989 /* bits */ 32, 9990 /* flags */ 0, 9991 }, 9992 #endif /* chips */ 9993 9994 #if defined(BCM_56370_A0) 9995 { /* SOC_FORMAT_INT_CMIC_XGXS1_PLL_CONTROL_3_BCM56370_A0fmt */ 9996 /* format CMIC_XGXS1_PLL_CONTROL_3fmt */ 9997 /* nFields */ 6, 9998 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_3_BCM56960_A0fmt_fields, 9999 /* bits */ 32, 10000 /* flags */ 0, 10001 }, 10002 #endif /* chips */ 10003 10004 #if defined(BCM_56450_A0) 10005 { /* SOC_FORMAT_INT_CMIC_XGXS1_PLL_CONTROL_3_BCM56450_A0fmt */ 10006 /* format CMIC_XGXS1_PLL_CONTROL_3fmt */ 10007 /* nFields */ 6, 10008 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_3_BCM56640_A0fmt_fields, 10009 /* bits */ 32, 10010 /* flags */ 0, 10011 }, 10012 #endif /* chips */ 10013 10014 #if defined(BCM_56450_B0) 10015 { /* SOC_FORMAT_INT_CMIC_XGXS1_PLL_CONTROL_3_BCM56450_B0fmt */ 10016 /* format CMIC_XGXS1_PLL_CONTROL_3fmt */ 10017 /* nFields */ 6, 10018 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_3_BCM56640_A0fmt_fields, 10019 /* bits */ 32, 10020 /* flags */ 0, 10021 }, 10022 #endif /* chips */ 10023 10024 #if defined(BCM_56450_B1) 10025 { /* SOC_FORMAT_INT_CMIC_XGXS1_PLL_CONTROL_3_BCM56450_B1fmt */ 10026 /* format CMIC_XGXS1_PLL_CONTROL_3fmt */ 10027 /* nFields */ 6, 10028 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_3_BCM56640_A0fmt_fields, 10029 /* bits */ 32, 10030 /* flags */ 0, 10031 }, 10032 #endif /* chips */ 10033 10034 #if defined(BCM_56640_A0) 10035 { /* SOC_FORMAT_INT_CMIC_XGXS1_PLL_CONTROL_3_BCM56640_A0fmt */ 10036 /* format CMIC_XGXS1_PLL_CONTROL_3fmt */ 10037 /* nFields */ 6, 10038 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_3_BCM56640_A0fmt_fields, 10039 /* bits */ 32, 10040 /* flags */ 0, 10041 }, 10042 #endif /* chips */ 10043 10044 #if defined(BCM_56770_A0) 10045 { /* SOC_FORMAT_INT_CMIC_XGXS1_PLL_CONTROL_3_BCM56770_A0fmt */ 10046 /* format CMIC_XGXS1_PLL_CONTROL_3fmt */ 10047 /* nFields */ 6, 10048 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_3_BCM56960_A0fmt_fields, 10049 /* bits */ 32, 10050 /* flags */ 0, 10051 }, 10052 #endif /* chips */ 10053 10054 #if defined(BCM_56840_B0) 10055 { /* SOC_FORMAT_INT_CMIC_XGXS1_PLL_CONTROL_3_BCM56840_B0fmt */ 10056 /* format CMIC_XGXS1_PLL_CONTROL_3fmt */ 10057 /* nFields */ 6, 10058 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_3fmt_fields, 10059 /* bits */ 32, 10060 /* flags */ 0, 10061 }, 10062 #endif /* chips */ 10063 10064 #if defined(BCM_56850_A0) 10065 { /* SOC_FORMAT_INT_CMIC_XGXS1_PLL_CONTROL_3_BCM56850_A0fmt */ 10066 /* format CMIC_XGXS1_PLL_CONTROL_3fmt */ 10067 /* nFields */ 6, 10068 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_3_BCM56640_A0fmt_fields, 10069 /* bits */ 32, 10070 /* flags */ 0, 10071 }, 10072 #endif /* chips */ 10073 10074 #if defined(BCM_56860_A0) 10075 { /* SOC_FORMAT_INT_CMIC_XGXS1_PLL_CONTROL_3_BCM56860_A0fmt */ 10076 /* format CMIC_XGXS1_PLL_CONTROL_3fmt */ 10077 /* nFields */ 6, 10078 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_3_BCM56640_A0fmt_fields, 10079 /* bits */ 32, 10080 /* flags */ 0, 10081 }, 10082 #endif /* chips */ 10083 10084 #if defined(BCM_56870_A0) 10085 { /* SOC_FORMAT_INT_CMIC_XGXS1_PLL_CONTROL_3_BCM56870_A0fmt */ 10086 /* format CMIC_XGXS1_PLL_CONTROL_3fmt */ 10087 /* nFields */ 6, 10088 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_3_BCM56960_A0fmt_fields, 10089 /* bits */ 32, 10090 /* flags */ 0, 10091 }, 10092 #endif /* chips */ 10093 10094 #if defined(BCM_56960_A0) 10095 { /* SOC_FORMAT_INT_CMIC_XGXS1_PLL_CONTROL_3_BCM56960_A0fmt */ 10096 /* format CMIC_XGXS1_PLL_CONTROL_3fmt */ 10097 /* nFields */ 6, 10098 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_3_BCM56960_A0fmt_fields, 10099 /* bits */ 32, 10100 /* flags */ 0, 10101 }, 10102 #endif /* chips */ 10103 10104 #if defined(BCM_56965_A0) 10105 { /* SOC_FORMAT_INT_CMIC_XGXS1_PLL_CONTROL_3_BCM56965_A0fmt */ 10106 /* format CMIC_XGXS1_PLL_CONTROL_3fmt */ 10107 /* nFields */ 6, 10108 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_3_BCM56960_A0fmt_fields, 10109 /* bits */ 32, 10110 /* flags */ 0, 10111 }, 10112 #endif /* chips */ 10113 10114 #if defined(BCM_56970_A0) 10115 { /* SOC_FORMAT_INT_CMIC_XGXS1_PLL_CONTROL_3_BCM56970_A0fmt */ 10116 /* format CMIC_XGXS1_PLL_CONTROL_3fmt */ 10117 /* nFields */ 6, 10118 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_3_BCM56960_A0fmt_fields, 10119 /* bits */ 32, 10120 /* flags */ 0, 10121 }, 10122 #endif /* chips */ 10123 10124 #if defined(BCM_88732_A0) 10125 { /* SOC_FORMAT_INT_CMIC_XGXS1_PLL_CONTROL_3_BCM88732_A0fmt */ 10126 /* format CMIC_XGXS1_PLL_CONTROL_3fmt */ 10127 /* nFields */ 4, 10128 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_3_BCM88732_A0fmt_fields, 10129 /* bits */ 32, 10130 /* flags */ 0, 10131 }, 10132 #endif /* chips */ 10133 10134 #if defined(BCM_56260_A0) 10135 { /* SOC_FORMAT_INT_CMIC_XGXS1_PLL_CONTROL_4_BCM56260_A0fmt */ 10136 /* format CMIC_XGXS1_PLL_CONTROL_4fmt */ 10137 /* nFields */ 16, 10138 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_4_BCM56960_A0fmt_fields, 10139 /* bits */ 32, 10140 /* flags */ 0, 10141 }, 10142 #endif /* chips */ 10143 10144 #if defined(BCM_56260_B0) 10145 { /* SOC_FORMAT_INT_CMIC_XGXS1_PLL_CONTROL_4_BCM56260_B0fmt */ 10146 /* format CMIC_XGXS1_PLL_CONTROL_4fmt */ 10147 /* nFields */ 16, 10148 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_4_BCM56960_A0fmt_fields, 10149 /* bits */ 32, 10150 /* flags */ 0, 10151 }, 10152 #endif /* chips */ 10153 10154 #if defined(BCM_56270_A0) 10155 { /* SOC_FORMAT_INT_CMIC_XGXS1_PLL_CONTROL_4_BCM56270_A0fmt */ 10156 /* format CMIC_XGXS1_PLL_CONTROL_4fmt */ 10157 /* nFields */ 16, 10158 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_4_BCM56960_A0fmt_fields, 10159 /* bits */ 32, 10160 /* flags */ 0, 10161 }, 10162 #endif /* chips */ 10163 10164 #if defined(BCM_56340_A0) 10165 { /* SOC_FORMAT_INT_CMIC_XGXS1_PLL_CONTROL_4_BCM56340_A0fmt */ 10166 /* format CMIC_XGXS1_PLL_CONTROL_4fmt */ 10167 /* nFields */ 16, 10168 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_4_BCM56640_A0fmt_fields, 10169 /* bits */ 32, 10170 /* flags */ 0, 10171 }, 10172 #endif /* chips */ 10173 10174 #if defined(BCM_56370_A0) 10175 { /* SOC_FORMAT_INT_CMIC_XGXS1_PLL_CONTROL_4_BCM56370_A0fmt */ 10176 /* format CMIC_XGXS1_PLL_CONTROL_4fmt */ 10177 /* nFields */ 16, 10178 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_4_BCM56960_A0fmt_fields, 10179 /* bits */ 32, 10180 /* flags */ 0, 10181 }, 10182 #endif /* chips */ 10183 10184 #if defined(BCM_56450_A0) 10185 { /* SOC_FORMAT_INT_CMIC_XGXS1_PLL_CONTROL_4_BCM56450_A0fmt */ 10186 /* format CMIC_XGXS1_PLL_CONTROL_4fmt */ 10187 /* nFields */ 16, 10188 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_4_BCM56640_A0fmt_fields, 10189 /* bits */ 32, 10190 /* flags */ 0, 10191 }, 10192 #endif /* chips */ 10193 10194 #if defined(BCM_56450_B0) 10195 { /* SOC_FORMAT_INT_CMIC_XGXS1_PLL_CONTROL_4_BCM56450_B0fmt */ 10196 /* format CMIC_XGXS1_PLL_CONTROL_4fmt */ 10197 /* nFields */ 16, 10198 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_4_BCM56640_A0fmt_fields, 10199 /* bits */ 32, 10200 /* flags */ 0, 10201 }, 10202 #endif /* chips */ 10203 10204 #if defined(BCM_56450_B1) 10205 { /* SOC_FORMAT_INT_CMIC_XGXS1_PLL_CONTROL_4_BCM56450_B1fmt */ 10206 /* format CMIC_XGXS1_PLL_CONTROL_4fmt */ 10207 /* nFields */ 16, 10208 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_4_BCM56640_A0fmt_fields, 10209 /* bits */ 32, 10210 /* flags */ 0, 10211 }, 10212 #endif /* chips */ 10213 10214 #if defined(BCM_56640_A0) 10215 { /* SOC_FORMAT_INT_CMIC_XGXS1_PLL_CONTROL_4_BCM56640_A0fmt */ 10216 /* format CMIC_XGXS1_PLL_CONTROL_4fmt */ 10217 /* nFields */ 16, 10218 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_4_BCM56640_A0fmt_fields, 10219 /* bits */ 32, 10220 /* flags */ 0, 10221 }, 10222 #endif /* chips */ 10223 10224 #if defined(BCM_56770_A0) 10225 { /* SOC_FORMAT_INT_CMIC_XGXS1_PLL_CONTROL_4_BCM56770_A0fmt */ 10226 /* format CMIC_XGXS1_PLL_CONTROL_4fmt */ 10227 /* nFields */ 16, 10228 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_4_BCM56960_A0fmt_fields, 10229 /* bits */ 32, 10230 /* flags */ 0, 10231 }, 10232 #endif /* chips */ 10233 10234 #if defined(BCM_56840_B0) 10235 { /* SOC_FORMAT_INT_CMIC_XGXS1_PLL_CONTROL_4_BCM56840_B0fmt */ 10236 /* format CMIC_XGXS1_PLL_CONTROL_4fmt */ 10237 /* nFields */ 16, 10238 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_4fmt_fields, 10239 /* bits */ 32, 10240 /* flags */ 0, 10241 }, 10242 #endif /* chips */ 10243 10244 #if defined(BCM_56850_A0) 10245 { /* SOC_FORMAT_INT_CMIC_XGXS1_PLL_CONTROL_4_BCM56850_A0fmt */ 10246 /* format CMIC_XGXS1_PLL_CONTROL_4fmt */ 10247 /* nFields */ 16, 10248 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_4_BCM56640_A0fmt_fields, 10249 /* bits */ 32, 10250 /* flags */ 0, 10251 }, 10252 #endif /* chips */ 10253 10254 #if defined(BCM_56860_A0) 10255 { /* SOC_FORMAT_INT_CMIC_XGXS1_PLL_CONTROL_4_BCM56860_A0fmt */ 10256 /* format CMIC_XGXS1_PLL_CONTROL_4fmt */ 10257 /* nFields */ 16, 10258 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_4_BCM56640_A0fmt_fields, 10259 /* bits */ 32, 10260 /* flags */ 0, 10261 }, 10262 #endif /* chips */ 10263 10264 #if defined(BCM_56870_A0) 10265 { /* SOC_FORMAT_INT_CMIC_XGXS1_PLL_CONTROL_4_BCM56870_A0fmt */ 10266 /* format CMIC_XGXS1_PLL_CONTROL_4fmt */ 10267 /* nFields */ 16, 10268 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_4_BCM56960_A0fmt_fields, 10269 /* bits */ 32, 10270 /* flags */ 0, 10271 }, 10272 #endif /* chips */ 10273 10274 #if defined(BCM_56960_A0) 10275 { /* SOC_FORMAT_INT_CMIC_XGXS1_PLL_CONTROL_4_BCM56960_A0fmt */ 10276 /* format CMIC_XGXS1_PLL_CONTROL_4fmt */ 10277 /* nFields */ 16, 10278 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_4_BCM56960_A0fmt_fields, 10279 /* bits */ 32, 10280 /* flags */ 0, 10281 }, 10282 #endif /* chips */ 10283 10284 #if defined(BCM_56965_A0) 10285 { /* SOC_FORMAT_INT_CMIC_XGXS1_PLL_CONTROL_4_BCM56965_A0fmt */ 10286 /* format CMIC_XGXS1_PLL_CONTROL_4fmt */ 10287 /* nFields */ 16, 10288 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_4_BCM56960_A0fmt_fields, 10289 /* bits */ 32, 10290 /* flags */ 0, 10291 }, 10292 #endif /* chips */ 10293 10294 #if defined(BCM_56970_A0) 10295 { /* SOC_FORMAT_INT_CMIC_XGXS1_PLL_CONTROL_4_BCM56970_A0fmt */ 10296 /* format CMIC_XGXS1_PLL_CONTROL_4fmt */ 10297 /* nFields */ 16, 10298 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_4_BCM56960_A0fmt_fields, 10299 /* bits */ 32, 10300 /* flags */ 0, 10301 }, 10302 #endif /* chips */ 10303 10304 #if defined(BCM_88732_A0) 10305 { /* SOC_FORMAT_INT_CMIC_XGXS1_PLL_CONTROL_4_BCM88732_A0fmt */ 10306 /* format CMIC_XGXS1_PLL_CONTROL_4fmt */ 10307 /* nFields */ 16, 10308 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_4_BCM88732_A0fmt_fields, 10309 /* bits */ 32, 10310 /* flags */ 0, 10311 }, 10312 #endif /* chips */ 10313 10314 #if defined(BCM_56840_A0) 10315 { /* SOC_FORMAT_INT_CMIC_XGXS2_PLL_CONTROL_1fmt */ 10316 /* format CMIC_XGXS2_PLL_CONTROL_1fmt */ 10317 /* nFields */ 4, 10318 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_1fmt_fields, 10319 /* bits */ 32, 10320 /* flags */ 0, 10321 }, 10322 #endif /* chips */ 10323 10324 #if defined(BCM_56840_A0) 10325 { /* SOC_FORMAT_INT_CMIC_XGXS2_PLL_CONTROL_2fmt */ 10326 /* format CMIC_XGXS2_PLL_CONTROL_2fmt */ 10327 /* nFields */ 7, 10328 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_2fmt_fields, 10329 /* bits */ 32, 10330 /* flags */ 0, 10331 }, 10332 #endif /* chips */ 10333 10334 #if defined(BCM_56840_A0) 10335 { /* SOC_FORMAT_INT_CMIC_XGXS2_PLL_CONTROL_3fmt */ 10336 /* format CMIC_XGXS2_PLL_CONTROL_3fmt */ 10337 /* nFields */ 6, 10338 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_3fmt_fields, 10339 /* bits */ 32, 10340 /* flags */ 0, 10341 }, 10342 #endif /* chips */ 10343 10344 #if defined(BCM_56840_A0) 10345 { /* SOC_FORMAT_INT_CMIC_XGXS2_PLL_CONTROL_4fmt */ 10346 /* format CMIC_XGXS2_PLL_CONTROL_4fmt */ 10347 /* nFields */ 16, 10348 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_4fmt_fields, 10349 /* bits */ 32, 10350 /* flags */ 0, 10351 }, 10352 #endif /* chips */ 10353 10354 #if defined(BCM_56260_A0) 10355 { /* SOC_FORMAT_INT_CMIC_XGXS2_PLL_CONTROL_1_BCM56260_A0fmt */ 10356 /* format CMIC_XGXS2_PLL_CONTROL_1fmt */ 10357 /* nFields */ 4, 10358 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_1_BCM56960_A0fmt_fields, 10359 /* bits */ 32, 10360 /* flags */ 0, 10361 }, 10362 #endif /* chips */ 10363 10364 #if defined(BCM_56260_B0) 10365 { /* SOC_FORMAT_INT_CMIC_XGXS2_PLL_CONTROL_1_BCM56260_B0fmt */ 10366 /* format CMIC_XGXS2_PLL_CONTROL_1fmt */ 10367 /* nFields */ 4, 10368 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_1_BCM56960_A0fmt_fields, 10369 /* bits */ 32, 10370 /* flags */ 0, 10371 }, 10372 #endif /* chips */ 10373 10374 #if defined(BCM_56270_A0) 10375 { /* SOC_FORMAT_INT_CMIC_XGXS2_PLL_CONTROL_1_BCM56270_A0fmt */ 10376 /* format CMIC_XGXS2_PLL_CONTROL_1fmt */ 10377 /* nFields */ 4, 10378 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_1_BCM56960_A0fmt_fields, 10379 /* bits */ 32, 10380 /* flags */ 0, 10381 }, 10382 #endif /* chips */ 10383 10384 #if defined(BCM_56340_A0) 10385 { /* SOC_FORMAT_INT_CMIC_XGXS2_PLL_CONTROL_1_BCM56340_A0fmt */ 10386 /* format CMIC_XGXS2_PLL_CONTROL_1fmt */ 10387 /* nFields */ 4, 10388 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_1_BCM56640_A0fmt_fields, 10389 /* bits */ 32, 10390 /* flags */ 0, 10391 }, 10392 #endif /* chips */ 10393 10394 #if defined(BCM_56370_A0) 10395 { /* SOC_FORMAT_INT_CMIC_XGXS2_PLL_CONTROL_1_BCM56370_A0fmt */ 10396 /* format CMIC_XGXS2_PLL_CONTROL_1fmt */ 10397 /* nFields */ 4, 10398 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_1_BCM56960_A0fmt_fields, 10399 /* bits */ 32, 10400 /* flags */ 0, 10401 }, 10402 #endif /* chips */ 10403 10404 #if defined(BCM_56450_A0) 10405 { /* SOC_FORMAT_INT_CMIC_XGXS2_PLL_CONTROL_1_BCM56450_A0fmt */ 10406 /* format CMIC_XGXS2_PLL_CONTROL_1fmt */ 10407 /* nFields */ 4, 10408 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_1_BCM56640_A0fmt_fields, 10409 /* bits */ 32, 10410 /* flags */ 0, 10411 }, 10412 #endif /* chips */ 10413 10414 #if defined(BCM_56450_B0) 10415 { /* SOC_FORMAT_INT_CMIC_XGXS2_PLL_CONTROL_1_BCM56450_B0fmt */ 10416 /* format CMIC_XGXS2_PLL_CONTROL_1fmt */ 10417 /* nFields */ 4, 10418 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_1_BCM56640_A0fmt_fields, 10419 /* bits */ 32, 10420 /* flags */ 0, 10421 }, 10422 #endif /* chips */ 10423 10424 #if defined(BCM_56450_B1) 10425 { /* SOC_FORMAT_INT_CMIC_XGXS2_PLL_CONTROL_1_BCM56450_B1fmt */ 10426 /* format CMIC_XGXS2_PLL_CONTROL_1fmt */ 10427 /* nFields */ 4, 10428 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_1_BCM56640_A0fmt_fields, 10429 /* bits */ 32, 10430 /* flags */ 0, 10431 }, 10432 #endif /* chips */ 10433 10434 #if defined(BCM_56640_A0) 10435 { /* SOC_FORMAT_INT_CMIC_XGXS2_PLL_CONTROL_1_BCM56640_A0fmt */ 10436 /* format CMIC_XGXS2_PLL_CONTROL_1fmt */ 10437 /* nFields */ 4, 10438 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_1_BCM56640_A0fmt_fields, 10439 /* bits */ 32, 10440 /* flags */ 0, 10441 }, 10442 #endif /* chips */ 10443 10444 #if defined(BCM_56770_A0) 10445 { /* SOC_FORMAT_INT_CMIC_XGXS2_PLL_CONTROL_1_BCM56770_A0fmt */ 10446 /* format CMIC_XGXS2_PLL_CONTROL_1fmt */ 10447 /* nFields */ 4, 10448 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_1_BCM56960_A0fmt_fields, 10449 /* bits */ 32, 10450 /* flags */ 0, 10451 }, 10452 #endif /* chips */ 10453 10454 #if defined(BCM_56840_B0) 10455 { /* SOC_FORMAT_INT_CMIC_XGXS2_PLL_CONTROL_1_BCM56840_B0fmt */ 10456 /* format CMIC_XGXS2_PLL_CONTROL_1fmt */ 10457 /* nFields */ 4, 10458 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_1fmt_fields, 10459 /* bits */ 32, 10460 /* flags */ 0, 10461 }, 10462 #endif /* chips */ 10463 10464 #if defined(BCM_56850_A0) 10465 { /* SOC_FORMAT_INT_CMIC_XGXS2_PLL_CONTROL_1_BCM56850_A0fmt */ 10466 /* format CMIC_XGXS2_PLL_CONTROL_1fmt */ 10467 /* nFields */ 4, 10468 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_1_BCM56640_A0fmt_fields, 10469 /* bits */ 32, 10470 /* flags */ 0, 10471 }, 10472 #endif /* chips */ 10473 10474 #if defined(BCM_56860_A0) 10475 { /* SOC_FORMAT_INT_CMIC_XGXS2_PLL_CONTROL_1_BCM56860_A0fmt */ 10476 /* format CMIC_XGXS2_PLL_CONTROL_1fmt */ 10477 /* nFields */ 4, 10478 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_1_BCM56640_A0fmt_fields, 10479 /* bits */ 32, 10480 /* flags */ 0, 10481 }, 10482 #endif /* chips */ 10483 10484 #if defined(BCM_56870_A0) 10485 { /* SOC_FORMAT_INT_CMIC_XGXS2_PLL_CONTROL_1_BCM56870_A0fmt */ 10486 /* format CMIC_XGXS2_PLL_CONTROL_1fmt */ 10487 /* nFields */ 4, 10488 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_1_BCM56960_A0fmt_fields, 10489 /* bits */ 32, 10490 /* flags */ 0, 10491 }, 10492 #endif /* chips */ 10493 10494 #if defined(BCM_56960_A0) 10495 { /* SOC_FORMAT_INT_CMIC_XGXS2_PLL_CONTROL_1_BCM56960_A0fmt */ 10496 /* format CMIC_XGXS2_PLL_CONTROL_1fmt */ 10497 /* nFields */ 4, 10498 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_1_BCM56960_A0fmt_fields, 10499 /* bits */ 32, 10500 /* flags */ 0, 10501 }, 10502 #endif /* chips */ 10503 10504 #if defined(BCM_56965_A0) 10505 { /* SOC_FORMAT_INT_CMIC_XGXS2_PLL_CONTROL_1_BCM56965_A0fmt */ 10506 /* format CMIC_XGXS2_PLL_CONTROL_1fmt */ 10507 /* nFields */ 4, 10508 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_1_BCM56960_A0fmt_fields, 10509 /* bits */ 32, 10510 /* flags */ 0, 10511 }, 10512 #endif /* chips */ 10513 10514 #if defined(BCM_56970_A0) 10515 { /* SOC_FORMAT_INT_CMIC_XGXS2_PLL_CONTROL_1_BCM56970_A0fmt */ 10516 /* format CMIC_XGXS2_PLL_CONTROL_1fmt */ 10517 /* nFields */ 4, 10518 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_1_BCM56960_A0fmt_fields, 10519 /* bits */ 32, 10520 /* flags */ 0, 10521 }, 10522 #endif /* chips */ 10523 10524 #if defined(BCM_88732_A0) 10525 { /* SOC_FORMAT_INT_CMIC_XGXS2_PLL_CONTROL_1_BCM88732_A0fmt */ 10526 /* format CMIC_XGXS2_PLL_CONTROL_1fmt */ 10527 /* nFields */ 10, 10528 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_1_BCM88732_A0fmt_fields, 10529 /* bits */ 32, 10530 /* flags */ 0, 10531 }, 10532 #endif /* chips */ 10533 10534 #if defined(BCM_56260_A0) 10535 { /* SOC_FORMAT_INT_CMIC_XGXS2_PLL_CONTROL_2_BCM56260_A0fmt */ 10536 /* format CMIC_XGXS2_PLL_CONTROL_2fmt */ 10537 /* nFields */ 7, 10538 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_2_BCM56960_A0fmt_fields, 10539 /* bits */ 32, 10540 /* flags */ 0, 10541 }, 10542 #endif /* chips */ 10543 10544 #if defined(BCM_56260_B0) 10545 { /* SOC_FORMAT_INT_CMIC_XGXS2_PLL_CONTROL_2_BCM56260_B0fmt */ 10546 /* format CMIC_XGXS2_PLL_CONTROL_2fmt */ 10547 /* nFields */ 7, 10548 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_2_BCM56960_A0fmt_fields, 10549 /* bits */ 32, 10550 /* flags */ 0, 10551 }, 10552 #endif /* chips */ 10553 10554 #if defined(BCM_56270_A0) 10555 { /* SOC_FORMAT_INT_CMIC_XGXS2_PLL_CONTROL_2_BCM56270_A0fmt */ 10556 /* format CMIC_XGXS2_PLL_CONTROL_2fmt */ 10557 /* nFields */ 7, 10558 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_2_BCM56960_A0fmt_fields, 10559 /* bits */ 32, 10560 /* flags */ 0, 10561 }, 10562 #endif /* chips */ 10563 10564 #if defined(BCM_56340_A0) 10565 { /* SOC_FORMAT_INT_CMIC_XGXS2_PLL_CONTROL_2_BCM56340_A0fmt */ 10566 /* format CMIC_XGXS2_PLL_CONTROL_2fmt */ 10567 /* nFields */ 7, 10568 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_2_BCM56640_A0fmt_fields, 10569 /* bits */ 32, 10570 /* flags */ 0, 10571 }, 10572 #endif /* chips */ 10573 10574 #if defined(BCM_56370_A0) 10575 { /* SOC_FORMAT_INT_CMIC_XGXS2_PLL_CONTROL_2_BCM56370_A0fmt */ 10576 /* format CMIC_XGXS2_PLL_CONTROL_2fmt */ 10577 /* nFields */ 7, 10578 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_2_BCM56960_A0fmt_fields, 10579 /* bits */ 32, 10580 /* flags */ 0, 10581 }, 10582 #endif /* chips */ 10583 10584 #if defined(BCM_56450_A0) 10585 { /* SOC_FORMAT_INT_CMIC_XGXS2_PLL_CONTROL_2_BCM56450_A0fmt */ 10586 /* format CMIC_XGXS2_PLL_CONTROL_2fmt */ 10587 /* nFields */ 7, 10588 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_2_BCM56640_A0fmt_fields, 10589 /* bits */ 32, 10590 /* flags */ 0, 10591 }, 10592 #endif /* chips */ 10593 10594 #if defined(BCM_56450_B0) 10595 { /* SOC_FORMAT_INT_CMIC_XGXS2_PLL_CONTROL_2_BCM56450_B0fmt */ 10596 /* format CMIC_XGXS2_PLL_CONTROL_2fmt */ 10597 /* nFields */ 7, 10598 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_2_BCM56640_A0fmt_fields, 10599 /* bits */ 32, 10600 /* flags */ 0, 10601 }, 10602 #endif /* chips */ 10603 10604 #if defined(BCM_56450_B1) 10605 { /* SOC_FORMAT_INT_CMIC_XGXS2_PLL_CONTROL_2_BCM56450_B1fmt */ 10606 /* format CMIC_XGXS2_PLL_CONTROL_2fmt */ 10607 /* nFields */ 7, 10608 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_2_BCM56640_A0fmt_fields, 10609 /* bits */ 32, 10610 /* flags */ 0, 10611 }, 10612 #endif /* chips */ 10613 10614 #if defined(BCM_56640_A0) 10615 { /* SOC_FORMAT_INT_CMIC_XGXS2_PLL_CONTROL_2_BCM56640_A0fmt */ 10616 /* format CMIC_XGXS2_PLL_CONTROL_2fmt */ 10617 /* nFields */ 7, 10618 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_2_BCM56640_A0fmt_fields, 10619 /* bits */ 32, 10620 /* flags */ 0, 10621 }, 10622 #endif /* chips */ 10623 10624 #if defined(BCM_56770_A0) 10625 { /* SOC_FORMAT_INT_CMIC_XGXS2_PLL_CONTROL_2_BCM56770_A0fmt */ 10626 /* format CMIC_XGXS2_PLL_CONTROL_2fmt */ 10627 /* nFields */ 7, 10628 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_2_BCM56960_A0fmt_fields, 10629 /* bits */ 32, 10630 /* flags */ 0, 10631 }, 10632 #endif /* chips */ 10633 10634 #if defined(BCM_56840_B0) 10635 { /* SOC_FORMAT_INT_CMIC_XGXS2_PLL_CONTROL_2_BCM56840_B0fmt */ 10636 /* format CMIC_XGXS2_PLL_CONTROL_2fmt */ 10637 /* nFields */ 7, 10638 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_2fmt_fields, 10639 /* bits */ 32, 10640 /* flags */ 0, 10641 }, 10642 #endif /* chips */ 10643 10644 #if defined(BCM_56850_A0) 10645 { /* SOC_FORMAT_INT_CMIC_XGXS2_PLL_CONTROL_2_BCM56850_A0fmt */ 10646 /* format CMIC_XGXS2_PLL_CONTROL_2fmt */ 10647 /* nFields */ 7, 10648 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_2_BCM56640_A0fmt_fields, 10649 /* bits */ 32, 10650 /* flags */ 0, 10651 }, 10652 #endif /* chips */ 10653 10654 #if defined(BCM_56860_A0) 10655 { /* SOC_FORMAT_INT_CMIC_XGXS2_PLL_CONTROL_2_BCM56860_A0fmt */ 10656 /* format CMIC_XGXS2_PLL_CONTROL_2fmt */ 10657 /* nFields */ 7, 10658 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_2_BCM56640_A0fmt_fields, 10659 /* bits */ 32, 10660 /* flags */ 0, 10661 }, 10662 #endif /* chips */ 10663 10664 #if defined(BCM_56870_A0) 10665 { /* SOC_FORMAT_INT_CMIC_XGXS2_PLL_CONTROL_2_BCM56870_A0fmt */ 10666 /* format CMIC_XGXS2_PLL_CONTROL_2fmt */ 10667 /* nFields */ 7, 10668 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_2_BCM56960_A0fmt_fields, 10669 /* bits */ 32, 10670 /* flags */ 0, 10671 }, 10672 #endif /* chips */ 10673 10674 #if defined(BCM_56960_A0) 10675 { /* SOC_FORMAT_INT_CMIC_XGXS2_PLL_CONTROL_2_BCM56960_A0fmt */ 10676 /* format CMIC_XGXS2_PLL_CONTROL_2fmt */ 10677 /* nFields */ 7, 10678 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_2_BCM56960_A0fmt_fields, 10679 /* bits */ 32, 10680 /* flags */ 0, 10681 }, 10682 #endif /* chips */ 10683 10684 #if defined(BCM_56965_A0) 10685 { /* SOC_FORMAT_INT_CMIC_XGXS2_PLL_CONTROL_2_BCM56965_A0fmt */ 10686 /* format CMIC_XGXS2_PLL_CONTROL_2fmt */ 10687 /* nFields */ 7, 10688 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_2_BCM56960_A0fmt_fields, 10689 /* bits */ 32, 10690 /* flags */ 0, 10691 }, 10692 #endif /* chips */ 10693 10694 #if defined(BCM_56970_A0) 10695 { /* SOC_FORMAT_INT_CMIC_XGXS2_PLL_CONTROL_2_BCM56970_A0fmt */ 10696 /* format CMIC_XGXS2_PLL_CONTROL_2fmt */ 10697 /* nFields */ 7, 10698 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_2_BCM56960_A0fmt_fields, 10699 /* bits */ 32, 10700 /* flags */ 0, 10701 }, 10702 #endif /* chips */ 10703 10704 #if defined(BCM_88732_A0) 10705 { /* SOC_FORMAT_INT_CMIC_XGXS2_PLL_CONTROL_2_BCM88732_A0fmt */ 10706 /* format CMIC_XGXS2_PLL_CONTROL_2fmt */ 10707 /* nFields */ 14, 10708 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_2_BCM88732_A0fmt_fields, 10709 /* bits */ 32, 10710 /* flags */ 0, 10711 }, 10712 #endif /* chips */ 10713 10714 #if defined(BCM_56260_A0) 10715 { /* SOC_FORMAT_INT_CMIC_XGXS2_PLL_CONTROL_3_BCM56260_A0fmt */ 10716 /* format CMIC_XGXS2_PLL_CONTROL_3fmt */ 10717 /* nFields */ 6, 10718 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_3_BCM56960_A0fmt_fields, 10719 /* bits */ 32, 10720 /* flags */ 0, 10721 }, 10722 #endif /* chips */ 10723 10724 #if defined(BCM_56260_B0) 10725 { /* SOC_FORMAT_INT_CMIC_XGXS2_PLL_CONTROL_3_BCM56260_B0fmt */ 10726 /* format CMIC_XGXS2_PLL_CONTROL_3fmt */ 10727 /* nFields */ 6, 10728 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_3_BCM56960_A0fmt_fields, 10729 /* bits */ 32, 10730 /* flags */ 0, 10731 }, 10732 #endif /* chips */ 10733 10734 #if defined(BCM_56270_A0) 10735 { /* SOC_FORMAT_INT_CMIC_XGXS2_PLL_CONTROL_3_BCM56270_A0fmt */ 10736 /* format CMIC_XGXS2_PLL_CONTROL_3fmt */ 10737 /* nFields */ 6, 10738 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_3_BCM56960_A0fmt_fields, 10739 /* bits */ 32, 10740 /* flags */ 0, 10741 }, 10742 #endif /* chips */ 10743 10744 #if defined(BCM_56340_A0) 10745 { /* SOC_FORMAT_INT_CMIC_XGXS2_PLL_CONTROL_3_BCM56340_A0fmt */ 10746 /* format CMIC_XGXS2_PLL_CONTROL_3fmt */ 10747 /* nFields */ 6, 10748 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_3_BCM56640_A0fmt_fields, 10749 /* bits */ 32, 10750 /* flags */ 0, 10751 }, 10752 #endif /* chips */ 10753 10754 #if defined(BCM_56370_A0) 10755 { /* SOC_FORMAT_INT_CMIC_XGXS2_PLL_CONTROL_3_BCM56370_A0fmt */ 10756 /* format CMIC_XGXS2_PLL_CONTROL_3fmt */ 10757 /* nFields */ 6, 10758 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_3_BCM56960_A0fmt_fields, 10759 /* bits */ 32, 10760 /* flags */ 0, 10761 }, 10762 #endif /* chips */ 10763 10764 #if defined(BCM_56450_A0) 10765 { /* SOC_FORMAT_INT_CMIC_XGXS2_PLL_CONTROL_3_BCM56450_A0fmt */ 10766 /* format CMIC_XGXS2_PLL_CONTROL_3fmt */ 10767 /* nFields */ 6, 10768 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_3_BCM56640_A0fmt_fields, 10769 /* bits */ 32, 10770 /* flags */ 0, 10771 }, 10772 #endif /* chips */ 10773 10774 #if defined(BCM_56450_B0) 10775 { /* SOC_FORMAT_INT_CMIC_XGXS2_PLL_CONTROL_3_BCM56450_B0fmt */ 10776 /* format CMIC_XGXS2_PLL_CONTROL_3fmt */ 10777 /* nFields */ 6, 10778 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_3_BCM56640_A0fmt_fields, 10779 /* bits */ 32, 10780 /* flags */ 0, 10781 }, 10782 #endif /* chips */ 10783 10784 #if defined(BCM_56450_B1) 10785 { /* SOC_FORMAT_INT_CMIC_XGXS2_PLL_CONTROL_3_BCM56450_B1fmt */ 10786 /* format CMIC_XGXS2_PLL_CONTROL_3fmt */ 10787 /* nFields */ 6, 10788 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_3_BCM56640_A0fmt_fields, 10789 /* bits */ 32, 10790 /* flags */ 0, 10791 }, 10792 #endif /* chips */ 10793 10794 #if defined(BCM_56640_A0) 10795 { /* SOC_FORMAT_INT_CMIC_XGXS2_PLL_CONTROL_3_BCM56640_A0fmt */ 10796 /* format CMIC_XGXS2_PLL_CONTROL_3fmt */ 10797 /* nFields */ 6, 10798 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_3_BCM56640_A0fmt_fields, 10799 /* bits */ 32, 10800 /* flags */ 0, 10801 }, 10802 #endif /* chips */ 10803 10804 #if defined(BCM_56770_A0) 10805 { /* SOC_FORMAT_INT_CMIC_XGXS2_PLL_CONTROL_3_BCM56770_A0fmt */ 10806 /* format CMIC_XGXS2_PLL_CONTROL_3fmt */ 10807 /* nFields */ 6, 10808 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_3_BCM56960_A0fmt_fields, 10809 /* bits */ 32, 10810 /* flags */ 0, 10811 }, 10812 #endif /* chips */ 10813 10814 #if defined(BCM_56840_B0) 10815 { /* SOC_FORMAT_INT_CMIC_XGXS2_PLL_CONTROL_3_BCM56840_B0fmt */ 10816 /* format CMIC_XGXS2_PLL_CONTROL_3fmt */ 10817 /* nFields */ 6, 10818 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_3fmt_fields, 10819 /* bits */ 32, 10820 /* flags */ 0, 10821 }, 10822 #endif /* chips */ 10823 10824 #if defined(BCM_56850_A0) 10825 { /* SOC_FORMAT_INT_CMIC_XGXS2_PLL_CONTROL_3_BCM56850_A0fmt */ 10826 /* format CMIC_XGXS2_PLL_CONTROL_3fmt */ 10827 /* nFields */ 6, 10828 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_3_BCM56640_A0fmt_fields, 10829 /* bits */ 32, 10830 /* flags */ 0, 10831 }, 10832 #endif /* chips */ 10833 10834 #if defined(BCM_56860_A0) 10835 { /* SOC_FORMAT_INT_CMIC_XGXS2_PLL_CONTROL_3_BCM56860_A0fmt */ 10836 /* format CMIC_XGXS2_PLL_CONTROL_3fmt */ 10837 /* nFields */ 6, 10838 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_3_BCM56640_A0fmt_fields, 10839 /* bits */ 32, 10840 /* flags */ 0, 10841 }, 10842 #endif /* chips */ 10843 10844 #if defined(BCM_56870_A0) 10845 { /* SOC_FORMAT_INT_CMIC_XGXS2_PLL_CONTROL_3_BCM56870_A0fmt */ 10846 /* format CMIC_XGXS2_PLL_CONTROL_3fmt */ 10847 /* nFields */ 6, 10848 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_3_BCM56960_A0fmt_fields, 10849 /* bits */ 32, 10850 /* flags */ 0, 10851 }, 10852 #endif /* chips */ 10853 10854 #if defined(BCM_56960_A0) 10855 { /* SOC_FORMAT_INT_CMIC_XGXS2_PLL_CONTROL_3_BCM56960_A0fmt */ 10856 /* format CMIC_XGXS2_PLL_CONTROL_3fmt */ 10857 /* nFields */ 6, 10858 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_3_BCM56960_A0fmt_fields, 10859 /* bits */ 32, 10860 /* flags */ 0, 10861 }, 10862 #endif /* chips */ 10863 10864 #if defined(BCM_56965_A0) 10865 { /* SOC_FORMAT_INT_CMIC_XGXS2_PLL_CONTROL_3_BCM56965_A0fmt */ 10866 /* format CMIC_XGXS2_PLL_CONTROL_3fmt */ 10867 /* nFields */ 6, 10868 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_3_BCM56960_A0fmt_fields, 10869 /* bits */ 32, 10870 /* flags */ 0, 10871 }, 10872 #endif /* chips */ 10873 10874 #if defined(BCM_56970_A0) 10875 { /* SOC_FORMAT_INT_CMIC_XGXS2_PLL_CONTROL_3_BCM56970_A0fmt */ 10876 /* format CMIC_XGXS2_PLL_CONTROL_3fmt */ 10877 /* nFields */ 6, 10878 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_3_BCM56960_A0fmt_fields, 10879 /* bits */ 32, 10880 /* flags */ 0, 10881 }, 10882 #endif /* chips */ 10883 10884 #if defined(BCM_88732_A0) 10885 { /* SOC_FORMAT_INT_CMIC_XGXS2_PLL_CONTROL_3_BCM88732_A0fmt */ 10886 /* format CMIC_XGXS2_PLL_CONTROL_3fmt */ 10887 /* nFields */ 4, 10888 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_3_BCM88732_A0fmt_fields, 10889 /* bits */ 32, 10890 /* flags */ 0, 10891 }, 10892 #endif /* chips */ 10893 10894 #if defined(BCM_56260_A0) 10895 { /* SOC_FORMAT_INT_CMIC_XGXS2_PLL_CONTROL_4_BCM56260_A0fmt */ 10896 /* format CMIC_XGXS2_PLL_CONTROL_4fmt */ 10897 /* nFields */ 16, 10898 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_4_BCM56960_A0fmt_fields, 10899 /* bits */ 32, 10900 /* flags */ 0, 10901 }, 10902 #endif /* chips */ 10903 10904 #if defined(BCM_56260_B0) 10905 { /* SOC_FORMAT_INT_CMIC_XGXS2_PLL_CONTROL_4_BCM56260_B0fmt */ 10906 /* format CMIC_XGXS2_PLL_CONTROL_4fmt */ 10907 /* nFields */ 16, 10908 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_4_BCM56960_A0fmt_fields, 10909 /* bits */ 32, 10910 /* flags */ 0, 10911 }, 10912 #endif /* chips */ 10913 10914 #if defined(BCM_56270_A0) 10915 { /* SOC_FORMAT_INT_CMIC_XGXS2_PLL_CONTROL_4_BCM56270_A0fmt */ 10916 /* format CMIC_XGXS2_PLL_CONTROL_4fmt */ 10917 /* nFields */ 16, 10918 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_4_BCM56960_A0fmt_fields, 10919 /* bits */ 32, 10920 /* flags */ 0, 10921 }, 10922 #endif /* chips */ 10923 10924 #if defined(BCM_56340_A0) 10925 { /* SOC_FORMAT_INT_CMIC_XGXS2_PLL_CONTROL_4_BCM56340_A0fmt */ 10926 /* format CMIC_XGXS2_PLL_CONTROL_4fmt */ 10927 /* nFields */ 16, 10928 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_4_BCM56640_A0fmt_fields, 10929 /* bits */ 32, 10930 /* flags */ 0, 10931 }, 10932 #endif /* chips */ 10933 10934 #if defined(BCM_56370_A0) 10935 { /* SOC_FORMAT_INT_CMIC_XGXS2_PLL_CONTROL_4_BCM56370_A0fmt */ 10936 /* format CMIC_XGXS2_PLL_CONTROL_4fmt */ 10937 /* nFields */ 16, 10938 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_4_BCM56960_A0fmt_fields, 10939 /* bits */ 32, 10940 /* flags */ 0, 10941 }, 10942 #endif /* chips */ 10943 10944 #if defined(BCM_56450_A0) 10945 { /* SOC_FORMAT_INT_CMIC_XGXS2_PLL_CONTROL_4_BCM56450_A0fmt */ 10946 /* format CMIC_XGXS2_PLL_CONTROL_4fmt */ 10947 /* nFields */ 16, 10948 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_4_BCM56640_A0fmt_fields, 10949 /* bits */ 32, 10950 /* flags */ 0, 10951 }, 10952 #endif /* chips */ 10953 10954 #if defined(BCM_56450_B0) 10955 { /* SOC_FORMAT_INT_CMIC_XGXS2_PLL_CONTROL_4_BCM56450_B0fmt */ 10956 /* format CMIC_XGXS2_PLL_CONTROL_4fmt */ 10957 /* nFields */ 16, 10958 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_4_BCM56640_A0fmt_fields, 10959 /* bits */ 32, 10960 /* flags */ 0, 10961 }, 10962 #endif /* chips */ 10963 10964 #if defined(BCM_56450_B1) 10965 { /* SOC_FORMAT_INT_CMIC_XGXS2_PLL_CONTROL_4_BCM56450_B1fmt */ 10966 /* format CMIC_XGXS2_PLL_CONTROL_4fmt */ 10967 /* nFields */ 16, 10968 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_4_BCM56640_A0fmt_fields, 10969 /* bits */ 32, 10970 /* flags */ 0, 10971 }, 10972 #endif /* chips */ 10973 10974 #if defined(BCM_56640_A0) 10975 { /* SOC_FORMAT_INT_CMIC_XGXS2_PLL_CONTROL_4_BCM56640_A0fmt */ 10976 /* format CMIC_XGXS2_PLL_CONTROL_4fmt */ 10977 /* nFields */ 16, 10978 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_4_BCM56640_A0fmt_fields, 10979 /* bits */ 32, 10980 /* flags */ 0, 10981 }, 10982 #endif /* chips */ 10983 10984 #if defined(BCM_56770_A0) 10985 { /* SOC_FORMAT_INT_CMIC_XGXS2_PLL_CONTROL_4_BCM56770_A0fmt */ 10986 /* format CMIC_XGXS2_PLL_CONTROL_4fmt */ 10987 /* nFields */ 16, 10988 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_4_BCM56960_A0fmt_fields, 10989 /* bits */ 32, 10990 /* flags */ 0, 10991 }, 10992 #endif /* chips */ 10993 10994 #if defined(BCM_56840_B0) 10995 { /* SOC_FORMAT_INT_CMIC_XGXS2_PLL_CONTROL_4_BCM56840_B0fmt */ 10996 /* format CMIC_XGXS2_PLL_CONTROL_4fmt */ 10997 /* nFields */ 16, 10998 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_4fmt_fields, 10999 /* bits */ 32, 11000 /* flags */ 0, 11001 }, 11002 #endif /* chips */ 11003 11004 #if defined(BCM_56850_A0) 11005 { /* SOC_FORMAT_INT_CMIC_XGXS2_PLL_CONTROL_4_BCM56850_A0fmt */ 11006 /* format CMIC_XGXS2_PLL_CONTROL_4fmt */ 11007 /* nFields */ 16, 11008 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_4_BCM56640_A0fmt_fields, 11009 /* bits */ 32, 11010 /* flags */ 0, 11011 }, 11012 #endif /* chips */ 11013 11014 #if defined(BCM_56860_A0) 11015 { /* SOC_FORMAT_INT_CMIC_XGXS2_PLL_CONTROL_4_BCM56860_A0fmt */ 11016 /* format CMIC_XGXS2_PLL_CONTROL_4fmt */ 11017 /* nFields */ 16, 11018 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_4_BCM56640_A0fmt_fields, 11019 /* bits */ 32, 11020 /* flags */ 0, 11021 }, 11022 #endif /* chips */ 11023 11024 #if defined(BCM_56870_A0) 11025 { /* SOC_FORMAT_INT_CMIC_XGXS2_PLL_CONTROL_4_BCM56870_A0fmt */ 11026 /* format CMIC_XGXS2_PLL_CONTROL_4fmt */ 11027 /* nFields */ 16, 11028 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_4_BCM56960_A0fmt_fields, 11029 /* bits */ 32, 11030 /* flags */ 0, 11031 }, 11032 #endif /* chips */ 11033 11034 #if defined(BCM_56960_A0) 11035 { /* SOC_FORMAT_INT_CMIC_XGXS2_PLL_CONTROL_4_BCM56960_A0fmt */ 11036 /* format CMIC_XGXS2_PLL_CONTROL_4fmt */ 11037 /* nFields */ 16, 11038 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_4_BCM56960_A0fmt_fields, 11039 /* bits */ 32, 11040 /* flags */ 0, 11041 }, 11042 #endif /* chips */ 11043 11044 #if defined(BCM_56965_A0) 11045 { /* SOC_FORMAT_INT_CMIC_XGXS2_PLL_CONTROL_4_BCM56965_A0fmt */ 11046 /* format CMIC_XGXS2_PLL_CONTROL_4fmt */ 11047 /* nFields */ 16, 11048 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_4_BCM56960_A0fmt_fields, 11049 /* bits */ 32, 11050 /* flags */ 0, 11051 }, 11052 #endif /* chips */ 11053 11054 #if defined(BCM_56970_A0) 11055 { /* SOC_FORMAT_INT_CMIC_XGXS2_PLL_CONTROL_4_BCM56970_A0fmt */ 11056 /* format CMIC_XGXS2_PLL_CONTROL_4fmt */ 11057 /* nFields */ 16, 11058 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_4_BCM56960_A0fmt_fields, 11059 /* bits */ 32, 11060 /* flags */ 0, 11061 }, 11062 #endif /* chips */ 11063 11064 #if defined(BCM_88732_A0) 11065 { /* SOC_FORMAT_INT_CMIC_XGXS2_PLL_CONTROL_4_BCM88732_A0fmt */ 11066 /* format CMIC_XGXS2_PLL_CONTROL_4fmt */ 11067 /* nFields */ 16, 11068 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_4_BCM88732_A0fmt_fields, 11069 /* bits */ 32, 11070 /* flags */ 0, 11071 }, 11072 #endif /* chips */ 11073 11074 #if defined(BCM_56840_A0) 11075 { /* SOC_FORMAT_INT_CMIC_XGXS3_PLL_CONTROL_1fmt */ 11076 /* format CMIC_XGXS3_PLL_CONTROL_1fmt */ 11077 /* nFields */ 4, 11078 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_1fmt_fields, 11079 /* bits */ 32, 11080 /* flags */ 0, 11081 }, 11082 #endif /* chips */ 11083 11084 #if defined(BCM_56840_A0) 11085 { /* SOC_FORMAT_INT_CMIC_XGXS3_PLL_CONTROL_2fmt */ 11086 /* format CMIC_XGXS3_PLL_CONTROL_2fmt */ 11087 /* nFields */ 7, 11088 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_2fmt_fields, 11089 /* bits */ 32, 11090 /* flags */ 0, 11091 }, 11092 #endif /* chips */ 11093 11094 #if defined(BCM_56840_A0) 11095 { /* SOC_FORMAT_INT_CMIC_XGXS3_PLL_CONTROL_3fmt */ 11096 /* format CMIC_XGXS3_PLL_CONTROL_3fmt */ 11097 /* nFields */ 6, 11098 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_3fmt_fields, 11099 /* bits */ 32, 11100 /* flags */ 0, 11101 }, 11102 #endif /* chips */ 11103 11104 #if defined(BCM_56840_A0) 11105 { /* SOC_FORMAT_INT_CMIC_XGXS3_PLL_CONTROL_4fmt */ 11106 /* format CMIC_XGXS3_PLL_CONTROL_4fmt */ 11107 /* nFields */ 16, 11108 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_4fmt_fields, 11109 /* bits */ 32, 11110 /* flags */ 0, 11111 }, 11112 #endif /* chips */ 11113 11114 #if defined(BCM_56260_A0) 11115 { /* SOC_FORMAT_INT_CMIC_XGXS3_PLL_CONTROL_1_BCM56260_A0fmt */ 11116 /* format CMIC_XGXS3_PLL_CONTROL_1fmt */ 11117 /* nFields */ 4, 11118 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_1_BCM56960_A0fmt_fields, 11119 /* bits */ 32, 11120 /* flags */ 0, 11121 }, 11122 #endif /* chips */ 11123 11124 #if defined(BCM_56260_B0) 11125 { /* SOC_FORMAT_INT_CMIC_XGXS3_PLL_CONTROL_1_BCM56260_B0fmt */ 11126 /* format CMIC_XGXS3_PLL_CONTROL_1fmt */ 11127 /* nFields */ 4, 11128 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_1_BCM56960_A0fmt_fields, 11129 /* bits */ 32, 11130 /* flags */ 0, 11131 }, 11132 #endif /* chips */ 11133 11134 #if defined(BCM_56270_A0) 11135 { /* SOC_FORMAT_INT_CMIC_XGXS3_PLL_CONTROL_1_BCM56270_A0fmt */ 11136 /* format CMIC_XGXS3_PLL_CONTROL_1fmt */ 11137 /* nFields */ 4, 11138 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_1_BCM56960_A0fmt_fields, 11139 /* bits */ 32, 11140 /* flags */ 0, 11141 }, 11142 #endif /* chips */ 11143 11144 #if defined(BCM_56340_A0) 11145 { /* SOC_FORMAT_INT_CMIC_XGXS3_PLL_CONTROL_1_BCM56340_A0fmt */ 11146 /* format CMIC_XGXS3_PLL_CONTROL_1fmt */ 11147 /* nFields */ 4, 11148 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_1_BCM56640_A0fmt_fields, 11149 /* bits */ 32, 11150 /* flags */ 0, 11151 }, 11152 #endif /* chips */ 11153 11154 #if defined(BCM_56370_A0) 11155 { /* SOC_FORMAT_INT_CMIC_XGXS3_PLL_CONTROL_1_BCM56370_A0fmt */ 11156 /* format CMIC_XGXS3_PLL_CONTROL_1fmt */ 11157 /* nFields */ 4, 11158 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_1_BCM56960_A0fmt_fields, 11159 /* bits */ 32, 11160 /* flags */ 0, 11161 }, 11162 #endif /* chips */ 11163 11164 #if defined(BCM_56450_A0) 11165 { /* SOC_FORMAT_INT_CMIC_XGXS3_PLL_CONTROL_1_BCM56450_A0fmt */ 11166 /* format CMIC_XGXS3_PLL_CONTROL_1fmt */ 11167 /* nFields */ 4, 11168 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_1_BCM56640_A0fmt_fields, 11169 /* bits */ 32, 11170 /* flags */ 0, 11171 }, 11172 #endif /* chips */ 11173 11174 #if defined(BCM_56450_B0) 11175 { /* SOC_FORMAT_INT_CMIC_XGXS3_PLL_CONTROL_1_BCM56450_B0fmt */ 11176 /* format CMIC_XGXS3_PLL_CONTROL_1fmt */ 11177 /* nFields */ 4, 11178 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_1_BCM56640_A0fmt_fields, 11179 /* bits */ 32, 11180 /* flags */ 0, 11181 }, 11182 #endif /* chips */ 11183 11184 #if defined(BCM_56450_B1) 11185 { /* SOC_FORMAT_INT_CMIC_XGXS3_PLL_CONTROL_1_BCM56450_B1fmt */ 11186 /* format CMIC_XGXS3_PLL_CONTROL_1fmt */ 11187 /* nFields */ 4, 11188 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_1_BCM56640_A0fmt_fields, 11189 /* bits */ 32, 11190 /* flags */ 0, 11191 }, 11192 #endif /* chips */ 11193 11194 #if defined(BCM_56640_A0) 11195 { /* SOC_FORMAT_INT_CMIC_XGXS3_PLL_CONTROL_1_BCM56640_A0fmt */ 11196 /* format CMIC_XGXS3_PLL_CONTROL_1fmt */ 11197 /* nFields */ 4, 11198 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_1_BCM56640_A0fmt_fields, 11199 /* bits */ 32, 11200 /* flags */ 0, 11201 }, 11202 #endif /* chips */ 11203 11204 #if defined(BCM_56770_A0) 11205 { /* SOC_FORMAT_INT_CMIC_XGXS3_PLL_CONTROL_1_BCM56770_A0fmt */ 11206 /* format CMIC_XGXS3_PLL_CONTROL_1fmt */ 11207 /* nFields */ 4, 11208 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_1_BCM56960_A0fmt_fields, 11209 /* bits */ 32, 11210 /* flags */ 0, 11211 }, 11212 #endif /* chips */ 11213 11214 #if defined(BCM_56840_B0) 11215 { /* SOC_FORMAT_INT_CMIC_XGXS3_PLL_CONTROL_1_BCM56840_B0fmt */ 11216 /* format CMIC_XGXS3_PLL_CONTROL_1fmt */ 11217 /* nFields */ 4, 11218 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_1fmt_fields, 11219 /* bits */ 32, 11220 /* flags */ 0, 11221 }, 11222 #endif /* chips */ 11223 11224 #if defined(BCM_56850_A0) 11225 { /* SOC_FORMAT_INT_CMIC_XGXS3_PLL_CONTROL_1_BCM56850_A0fmt */ 11226 /* format CMIC_XGXS3_PLL_CONTROL_1fmt */ 11227 /* nFields */ 4, 11228 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_1_BCM56640_A0fmt_fields, 11229 /* bits */ 32, 11230 /* flags */ 0, 11231 }, 11232 #endif /* chips */ 11233 11234 #if defined(BCM_56860_A0) 11235 { /* SOC_FORMAT_INT_CMIC_XGXS3_PLL_CONTROL_1_BCM56860_A0fmt */ 11236 /* format CMIC_XGXS3_PLL_CONTROL_1fmt */ 11237 /* nFields */ 4, 11238 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_1_BCM56640_A0fmt_fields, 11239 /* bits */ 32, 11240 /* flags */ 0, 11241 }, 11242 #endif /* chips */ 11243 11244 #if defined(BCM_56870_A0) 11245 { /* SOC_FORMAT_INT_CMIC_XGXS3_PLL_CONTROL_1_BCM56870_A0fmt */ 11246 /* format CMIC_XGXS3_PLL_CONTROL_1fmt */ 11247 /* nFields */ 4, 11248 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_1_BCM56960_A0fmt_fields, 11249 /* bits */ 32, 11250 /* flags */ 0, 11251 }, 11252 #endif /* chips */ 11253 11254 #if defined(BCM_56960_A0) 11255 { /* SOC_FORMAT_INT_CMIC_XGXS3_PLL_CONTROL_1_BCM56960_A0fmt */ 11256 /* format CMIC_XGXS3_PLL_CONTROL_1fmt */ 11257 /* nFields */ 4, 11258 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_1_BCM56960_A0fmt_fields, 11259 /* bits */ 32, 11260 /* flags */ 0, 11261 }, 11262 #endif /* chips */ 11263 11264 #if defined(BCM_56965_A0) 11265 { /* SOC_FORMAT_INT_CMIC_XGXS3_PLL_CONTROL_1_BCM56965_A0fmt */ 11266 /* format CMIC_XGXS3_PLL_CONTROL_1fmt */ 11267 /* nFields */ 4, 11268 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_1_BCM56960_A0fmt_fields, 11269 /* bits */ 32, 11270 /* flags */ 0, 11271 }, 11272 #endif /* chips */ 11273 11274 #if defined(BCM_56970_A0) 11275 { /* SOC_FORMAT_INT_CMIC_XGXS3_PLL_CONTROL_1_BCM56970_A0fmt */ 11276 /* format CMIC_XGXS3_PLL_CONTROL_1fmt */ 11277 /* nFields */ 4, 11278 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_1_BCM56960_A0fmt_fields, 11279 /* bits */ 32, 11280 /* flags */ 0, 11281 }, 11282 #endif /* chips */ 11283 11284 #if defined(BCM_56260_A0) 11285 { /* SOC_FORMAT_INT_CMIC_XGXS3_PLL_CONTROL_2_BCM56260_A0fmt */ 11286 /* format CMIC_XGXS3_PLL_CONTROL_2fmt */ 11287 /* nFields */ 7, 11288 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_2_BCM56960_A0fmt_fields, 11289 /* bits */ 32, 11290 /* flags */ 0, 11291 }, 11292 #endif /* chips */ 11293 11294 #if defined(BCM_56260_B0) 11295 { /* SOC_FORMAT_INT_CMIC_XGXS3_PLL_CONTROL_2_BCM56260_B0fmt */ 11296 /* format CMIC_XGXS3_PLL_CONTROL_2fmt */ 11297 /* nFields */ 7, 11298 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_2_BCM56960_A0fmt_fields, 11299 /* bits */ 32, 11300 /* flags */ 0, 11301 }, 11302 #endif /* chips */ 11303 11304 #if defined(BCM_56270_A0) 11305 { /* SOC_FORMAT_INT_CMIC_XGXS3_PLL_CONTROL_2_BCM56270_A0fmt */ 11306 /* format CMIC_XGXS3_PLL_CONTROL_2fmt */ 11307 /* nFields */ 7, 11308 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_2_BCM56960_A0fmt_fields, 11309 /* bits */ 32, 11310 /* flags */ 0, 11311 }, 11312 #endif /* chips */ 11313 11314 #if defined(BCM_56340_A0) 11315 { /* SOC_FORMAT_INT_CMIC_XGXS3_PLL_CONTROL_2_BCM56340_A0fmt */ 11316 /* format CMIC_XGXS3_PLL_CONTROL_2fmt */ 11317 /* nFields */ 7, 11318 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_2_BCM56640_A0fmt_fields, 11319 /* bits */ 32, 11320 /* flags */ 0, 11321 }, 11322 #endif /* chips */ 11323 11324 #if defined(BCM_56370_A0) 11325 { /* SOC_FORMAT_INT_CMIC_XGXS3_PLL_CONTROL_2_BCM56370_A0fmt */ 11326 /* format CMIC_XGXS3_PLL_CONTROL_2fmt */ 11327 /* nFields */ 7, 11328 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_2_BCM56960_A0fmt_fields, 11329 /* bits */ 32, 11330 /* flags */ 0, 11331 }, 11332 #endif /* chips */ 11333 11334 #if defined(BCM_56450_A0) 11335 { /* SOC_FORMAT_INT_CMIC_XGXS3_PLL_CONTROL_2_BCM56450_A0fmt */ 11336 /* format CMIC_XGXS3_PLL_CONTROL_2fmt */ 11337 /* nFields */ 7, 11338 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_2_BCM56640_A0fmt_fields, 11339 /* bits */ 32, 11340 /* flags */ 0, 11341 }, 11342 #endif /* chips */ 11343 11344 #if defined(BCM_56450_B0) 11345 { /* SOC_FORMAT_INT_CMIC_XGXS3_PLL_CONTROL_2_BCM56450_B0fmt */ 11346 /* format CMIC_XGXS3_PLL_CONTROL_2fmt */ 11347 /* nFields */ 7, 11348 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_2_BCM56640_A0fmt_fields, 11349 /* bits */ 32, 11350 /* flags */ 0, 11351 }, 11352 #endif /* chips */ 11353 11354 #if defined(BCM_56450_B1) 11355 { /* SOC_FORMAT_INT_CMIC_XGXS3_PLL_CONTROL_2_BCM56450_B1fmt */ 11356 /* format CMIC_XGXS3_PLL_CONTROL_2fmt */ 11357 /* nFields */ 7, 11358 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_2_BCM56640_A0fmt_fields, 11359 /* bits */ 32, 11360 /* flags */ 0, 11361 }, 11362 #endif /* chips */ 11363 11364 #if defined(BCM_56640_A0) 11365 { /* SOC_FORMAT_INT_CMIC_XGXS3_PLL_CONTROL_2_BCM56640_A0fmt */ 11366 /* format CMIC_XGXS3_PLL_CONTROL_2fmt */ 11367 /* nFields */ 7, 11368 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_2_BCM56640_A0fmt_fields, 11369 /* bits */ 32, 11370 /* flags */ 0, 11371 }, 11372 #endif /* chips */ 11373 11374 #if defined(BCM_56770_A0) 11375 { /* SOC_FORMAT_INT_CMIC_XGXS3_PLL_CONTROL_2_BCM56770_A0fmt */ 11376 /* format CMIC_XGXS3_PLL_CONTROL_2fmt */ 11377 /* nFields */ 7, 11378 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_2_BCM56960_A0fmt_fields, 11379 /* bits */ 32, 11380 /* flags */ 0, 11381 }, 11382 #endif /* chips */ 11383 11384 #if defined(BCM_56840_B0) 11385 { /* SOC_FORMAT_INT_CMIC_XGXS3_PLL_CONTROL_2_BCM56840_B0fmt */ 11386 /* format CMIC_XGXS3_PLL_CONTROL_2fmt */ 11387 /* nFields */ 7, 11388 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_2fmt_fields, 11389 /* bits */ 32, 11390 /* flags */ 0, 11391 }, 11392 #endif /* chips */ 11393 11394 #if defined(BCM_56850_A0) 11395 { /* SOC_FORMAT_INT_CMIC_XGXS3_PLL_CONTROL_2_BCM56850_A0fmt */ 11396 /* format CMIC_XGXS3_PLL_CONTROL_2fmt */ 11397 /* nFields */ 7, 11398 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_2_BCM56640_A0fmt_fields, 11399 /* bits */ 32, 11400 /* flags */ 0, 11401 }, 11402 #endif /* chips */ 11403 11404 #if defined(BCM_56860_A0) 11405 { /* SOC_FORMAT_INT_CMIC_XGXS3_PLL_CONTROL_2_BCM56860_A0fmt */ 11406 /* format CMIC_XGXS3_PLL_CONTROL_2fmt */ 11407 /* nFields */ 7, 11408 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_2_BCM56640_A0fmt_fields, 11409 /* bits */ 32, 11410 /* flags */ 0, 11411 }, 11412 #endif /* chips */ 11413 11414 #if defined(BCM_56870_A0) 11415 { /* SOC_FORMAT_INT_CMIC_XGXS3_PLL_CONTROL_2_BCM56870_A0fmt */ 11416 /* format CMIC_XGXS3_PLL_CONTROL_2fmt */ 11417 /* nFields */ 7, 11418 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_2_BCM56960_A0fmt_fields, 11419 /* bits */ 32, 11420 /* flags */ 0, 11421 }, 11422 #endif /* chips */ 11423 11424 #if defined(BCM_56960_A0) 11425 { /* SOC_FORMAT_INT_CMIC_XGXS3_PLL_CONTROL_2_BCM56960_A0fmt */ 11426 /* format CMIC_XGXS3_PLL_CONTROL_2fmt */ 11427 /* nFields */ 7, 11428 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_2_BCM56960_A0fmt_fields, 11429 /* bits */ 32, 11430 /* flags */ 0, 11431 }, 11432 #endif /* chips */ 11433 11434 #if defined(BCM_56965_A0) 11435 { /* SOC_FORMAT_INT_CMIC_XGXS3_PLL_CONTROL_2_BCM56965_A0fmt */ 11436 /* format CMIC_XGXS3_PLL_CONTROL_2fmt */ 11437 /* nFields */ 7, 11438 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_2_BCM56960_A0fmt_fields, 11439 /* bits */ 32, 11440 /* flags */ 0, 11441 }, 11442 #endif /* chips */ 11443 11444 #if defined(BCM_56970_A0) 11445 { /* SOC_FORMAT_INT_CMIC_XGXS3_PLL_CONTROL_2_BCM56970_A0fmt */ 11446 /* format CMIC_XGXS3_PLL_CONTROL_2fmt */ 11447 /* nFields */ 7, 11448 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_2_BCM56960_A0fmt_fields, 11449 /* bits */ 32, 11450 /* flags */ 0, 11451 }, 11452 #endif /* chips */ 11453 11454 #if defined(BCM_56260_A0) 11455 { /* SOC_FORMAT_INT_CMIC_XGXS3_PLL_CONTROL_3_BCM56260_A0fmt */ 11456 /* format CMIC_XGXS3_PLL_CONTROL_3fmt */ 11457 /* nFields */ 6, 11458 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_3_BCM56960_A0fmt_fields, 11459 /* bits */ 32, 11460 /* flags */ 0, 11461 }, 11462 #endif /* chips */ 11463 11464 #if defined(BCM_56260_B0) 11465 { /* SOC_FORMAT_INT_CMIC_XGXS3_PLL_CONTROL_3_BCM56260_B0fmt */ 11466 /* format CMIC_XGXS3_PLL_CONTROL_3fmt */ 11467 /* nFields */ 6, 11468 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_3_BCM56960_A0fmt_fields, 11469 /* bits */ 32, 11470 /* flags */ 0, 11471 }, 11472 #endif /* chips */ 11473 11474 #if defined(BCM_56270_A0) 11475 { /* SOC_FORMAT_INT_CMIC_XGXS3_PLL_CONTROL_3_BCM56270_A0fmt */ 11476 /* format CMIC_XGXS3_PLL_CONTROL_3fmt */ 11477 /* nFields */ 6, 11478 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_3_BCM56960_A0fmt_fields, 11479 /* bits */ 32, 11480 /* flags */ 0, 11481 }, 11482 #endif /* chips */ 11483 11484 #if defined(BCM_56340_A0) 11485 { /* SOC_FORMAT_INT_CMIC_XGXS3_PLL_CONTROL_3_BCM56340_A0fmt */ 11486 /* format CMIC_XGXS3_PLL_CONTROL_3fmt */ 11487 /* nFields */ 6, 11488 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_3_BCM56640_A0fmt_fields, 11489 /* bits */ 32, 11490 /* flags */ 0, 11491 }, 11492 #endif /* chips */ 11493 11494 #if defined(BCM_56370_A0) 11495 { /* SOC_FORMAT_INT_CMIC_XGXS3_PLL_CONTROL_3_BCM56370_A0fmt */ 11496 /* format CMIC_XGXS3_PLL_CONTROL_3fmt */ 11497 /* nFields */ 6, 11498 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_3_BCM56960_A0fmt_fields, 11499 /* bits */ 32, 11500 /* flags */ 0, 11501 }, 11502 #endif /* chips */ 11503 11504 #if defined(BCM_56450_A0) 11505 { /* SOC_FORMAT_INT_CMIC_XGXS3_PLL_CONTROL_3_BCM56450_A0fmt */ 11506 /* format CMIC_XGXS3_PLL_CONTROL_3fmt */ 11507 /* nFields */ 6, 11508 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_3_BCM56640_A0fmt_fields, 11509 /* bits */ 32, 11510 /* flags */ 0, 11511 }, 11512 #endif /* chips */ 11513 11514 #if defined(BCM_56450_B0) 11515 { /* SOC_FORMAT_INT_CMIC_XGXS3_PLL_CONTROL_3_BCM56450_B0fmt */ 11516 /* format CMIC_XGXS3_PLL_CONTROL_3fmt */ 11517 /* nFields */ 6, 11518 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_3_BCM56640_A0fmt_fields, 11519 /* bits */ 32, 11520 /* flags */ 0, 11521 }, 11522 #endif /* chips */ 11523 11524 #if defined(BCM_56450_B1) 11525 { /* SOC_FORMAT_INT_CMIC_XGXS3_PLL_CONTROL_3_BCM56450_B1fmt */ 11526 /* format CMIC_XGXS3_PLL_CONTROL_3fmt */ 11527 /* nFields */ 6, 11528 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_3_BCM56640_A0fmt_fields, 11529 /* bits */ 32, 11530 /* flags */ 0, 11531 }, 11532 #endif /* chips */ 11533 11534 #if defined(BCM_56640_A0) 11535 { /* SOC_FORMAT_INT_CMIC_XGXS3_PLL_CONTROL_3_BCM56640_A0fmt */ 11536 /* format CMIC_XGXS3_PLL_CONTROL_3fmt */ 11537 /* nFields */ 6, 11538 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_3_BCM56640_A0fmt_fields, 11539 /* bits */ 32, 11540 /* flags */ 0, 11541 }, 11542 #endif /* chips */ 11543 11544 #if defined(BCM_56770_A0) 11545 { /* SOC_FORMAT_INT_CMIC_XGXS3_PLL_CONTROL_3_BCM56770_A0fmt */ 11546 /* format CMIC_XGXS3_PLL_CONTROL_3fmt */ 11547 /* nFields */ 6, 11548 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_3_BCM56960_A0fmt_fields, 11549 /* bits */ 32, 11550 /* flags */ 0, 11551 }, 11552 #endif /* chips */ 11553 11554 #if defined(BCM_56840_B0) 11555 { /* SOC_FORMAT_INT_CMIC_XGXS3_PLL_CONTROL_3_BCM56840_B0fmt */ 11556 /* format CMIC_XGXS3_PLL_CONTROL_3fmt */ 11557 /* nFields */ 6, 11558 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_3fmt_fields, 11559 /* bits */ 32, 11560 /* flags */ 0, 11561 }, 11562 #endif /* chips */ 11563 11564 #if defined(BCM_56850_A0) 11565 { /* SOC_FORMAT_INT_CMIC_XGXS3_PLL_CONTROL_3_BCM56850_A0fmt */ 11566 /* format CMIC_XGXS3_PLL_CONTROL_3fmt */ 11567 /* nFields */ 6, 11568 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_3_BCM56640_A0fmt_fields, 11569 /* bits */ 32, 11570 /* flags */ 0, 11571 }, 11572 #endif /* chips */ 11573 11574 #if defined(BCM_56860_A0) 11575 { /* SOC_FORMAT_INT_CMIC_XGXS3_PLL_CONTROL_3_BCM56860_A0fmt */ 11576 /* format CMIC_XGXS3_PLL_CONTROL_3fmt */ 11577 /* nFields */ 6, 11578 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_3_BCM56640_A0fmt_fields, 11579 /* bits */ 32, 11580 /* flags */ 0, 11581 }, 11582 #endif /* chips */ 11583 11584 #if defined(BCM_56870_A0) 11585 { /* SOC_FORMAT_INT_CMIC_XGXS3_PLL_CONTROL_3_BCM56870_A0fmt */ 11586 /* format CMIC_XGXS3_PLL_CONTROL_3fmt */ 11587 /* nFields */ 6, 11588 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_3_BCM56960_A0fmt_fields, 11589 /* bits */ 32, 11590 /* flags */ 0, 11591 }, 11592 #endif /* chips */ 11593 11594 #if defined(BCM_56960_A0) 11595 { /* SOC_FORMAT_INT_CMIC_XGXS3_PLL_CONTROL_3_BCM56960_A0fmt */ 11596 /* format CMIC_XGXS3_PLL_CONTROL_3fmt */ 11597 /* nFields */ 6, 11598 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_3_BCM56960_A0fmt_fields, 11599 /* bits */ 32, 11600 /* flags */ 0, 11601 }, 11602 #endif /* chips */ 11603 11604 #if defined(BCM_56965_A0) 11605 { /* SOC_FORMAT_INT_CMIC_XGXS3_PLL_CONTROL_3_BCM56965_A0fmt */ 11606 /* format CMIC_XGXS3_PLL_CONTROL_3fmt */ 11607 /* nFields */ 6, 11608 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_3_BCM56960_A0fmt_fields, 11609 /* bits */ 32, 11610 /* flags */ 0, 11611 }, 11612 #endif /* chips */ 11613 11614 #if defined(BCM_56970_A0) 11615 { /* SOC_FORMAT_INT_CMIC_XGXS3_PLL_CONTROL_3_BCM56970_A0fmt */ 11616 /* format CMIC_XGXS3_PLL_CONTROL_3fmt */ 11617 /* nFields */ 6, 11618 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_3_BCM56960_A0fmt_fields, 11619 /* bits */ 32, 11620 /* flags */ 0, 11621 }, 11622 #endif /* chips */ 11623 11624 #if defined(BCM_56260_A0) 11625 { /* SOC_FORMAT_INT_CMIC_XGXS3_PLL_CONTROL_4_BCM56260_A0fmt */ 11626 /* format CMIC_XGXS3_PLL_CONTROL_4fmt */ 11627 /* nFields */ 16, 11628 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_4_BCM56960_A0fmt_fields, 11629 /* bits */ 32, 11630 /* flags */ 0, 11631 }, 11632 #endif /* chips */ 11633 11634 #if defined(BCM_56260_B0) 11635 { /* SOC_FORMAT_INT_CMIC_XGXS3_PLL_CONTROL_4_BCM56260_B0fmt */ 11636 /* format CMIC_XGXS3_PLL_CONTROL_4fmt */ 11637 /* nFields */ 16, 11638 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_4_BCM56960_A0fmt_fields, 11639 /* bits */ 32, 11640 /* flags */ 0, 11641 }, 11642 #endif /* chips */ 11643 11644 #if defined(BCM_56270_A0) 11645 { /* SOC_FORMAT_INT_CMIC_XGXS3_PLL_CONTROL_4_BCM56270_A0fmt */ 11646 /* format CMIC_XGXS3_PLL_CONTROL_4fmt */ 11647 /* nFields */ 16, 11648 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_4_BCM56960_A0fmt_fields, 11649 /* bits */ 32, 11650 /* flags */ 0, 11651 }, 11652 #endif /* chips */ 11653 11654 #if defined(BCM_56340_A0) 11655 { /* SOC_FORMAT_INT_CMIC_XGXS3_PLL_CONTROL_4_BCM56340_A0fmt */ 11656 /* format CMIC_XGXS3_PLL_CONTROL_4fmt */ 11657 /* nFields */ 16, 11658 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_4_BCM56640_A0fmt_fields, 11659 /* bits */ 32, 11660 /* flags */ 0, 11661 }, 11662 #endif /* chips */ 11663 11664 #if defined(BCM_56370_A0) 11665 { /* SOC_FORMAT_INT_CMIC_XGXS3_PLL_CONTROL_4_BCM56370_A0fmt */ 11666 /* format CMIC_XGXS3_PLL_CONTROL_4fmt */ 11667 /* nFields */ 16, 11668 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_4_BCM56960_A0fmt_fields, 11669 /* bits */ 32, 11670 /* flags */ 0, 11671 }, 11672 #endif /* chips */ 11673 11674 #if defined(BCM_56450_A0) 11675 { /* SOC_FORMAT_INT_CMIC_XGXS3_PLL_CONTROL_4_BCM56450_A0fmt */ 11676 /* format CMIC_XGXS3_PLL_CONTROL_4fmt */ 11677 /* nFields */ 16, 11678 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_4_BCM56640_A0fmt_fields, 11679 /* bits */ 32, 11680 /* flags */ 0, 11681 }, 11682 #endif /* chips */ 11683 11684 #if defined(BCM_56450_B0) 11685 { /* SOC_FORMAT_INT_CMIC_XGXS3_PLL_CONTROL_4_BCM56450_B0fmt */ 11686 /* format CMIC_XGXS3_PLL_CONTROL_4fmt */ 11687 /* nFields */ 16, 11688 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_4_BCM56640_A0fmt_fields, 11689 /* bits */ 32, 11690 /* flags */ 0, 11691 }, 11692 #endif /* chips */ 11693 11694 #if defined(BCM_56450_B1) 11695 { /* SOC_FORMAT_INT_CMIC_XGXS3_PLL_CONTROL_4_BCM56450_B1fmt */ 11696 /* format CMIC_XGXS3_PLL_CONTROL_4fmt */ 11697 /* nFields */ 16, 11698 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_4_BCM56640_A0fmt_fields, 11699 /* bits */ 32, 11700 /* flags */ 0, 11701 }, 11702 #endif /* chips */ 11703 11704 #if defined(BCM_56640_A0) 11705 { /* SOC_FORMAT_INT_CMIC_XGXS3_PLL_CONTROL_4_BCM56640_A0fmt */ 11706 /* format CMIC_XGXS3_PLL_CONTROL_4fmt */ 11707 /* nFields */ 16, 11708 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_4_BCM56640_A0fmt_fields, 11709 /* bits */ 32, 11710 /* flags */ 0, 11711 }, 11712 #endif /* chips */ 11713 11714 #if defined(BCM_56770_A0) 11715 { /* SOC_FORMAT_INT_CMIC_XGXS3_PLL_CONTROL_4_BCM56770_A0fmt */ 11716 /* format CMIC_XGXS3_PLL_CONTROL_4fmt */ 11717 /* nFields */ 16, 11718 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_4_BCM56960_A0fmt_fields, 11719 /* bits */ 32, 11720 /* flags */ 0, 11721 }, 11722 #endif /* chips */ 11723 11724 #if defined(BCM_56840_B0) 11725 { /* SOC_FORMAT_INT_CMIC_XGXS3_PLL_CONTROL_4_BCM56840_B0fmt */ 11726 /* format CMIC_XGXS3_PLL_CONTROL_4fmt */ 11727 /* nFields */ 16, 11728 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_4fmt_fields, 11729 /* bits */ 32, 11730 /* flags */ 0, 11731 }, 11732 #endif /* chips */ 11733 11734 #if defined(BCM_56850_A0) 11735 { /* SOC_FORMAT_INT_CMIC_XGXS3_PLL_CONTROL_4_BCM56850_A0fmt */ 11736 /* format CMIC_XGXS3_PLL_CONTROL_4fmt */ 11737 /* nFields */ 16, 11738 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_4_BCM56640_A0fmt_fields, 11739 /* bits */ 32, 11740 /* flags */ 0, 11741 }, 11742 #endif /* chips */ 11743 11744 #if defined(BCM_56860_A0) 11745 { /* SOC_FORMAT_INT_CMIC_XGXS3_PLL_CONTROL_4_BCM56860_A0fmt */ 11746 /* format CMIC_XGXS3_PLL_CONTROL_4fmt */ 11747 /* nFields */ 16, 11748 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_4_BCM56640_A0fmt_fields, 11749 /* bits */ 32, 11750 /* flags */ 0, 11751 }, 11752 #endif /* chips */ 11753 11754 #if defined(BCM_56870_A0) 11755 { /* SOC_FORMAT_INT_CMIC_XGXS3_PLL_CONTROL_4_BCM56870_A0fmt */ 11756 /* format CMIC_XGXS3_PLL_CONTROL_4fmt */ 11757 /* nFields */ 16, 11758 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_4_BCM56960_A0fmt_fields, 11759 /* bits */ 32, 11760 /* flags */ 0, 11761 }, 11762 #endif /* chips */ 11763 11764 #if defined(BCM_56960_A0) 11765 { /* SOC_FORMAT_INT_CMIC_XGXS3_PLL_CONTROL_4_BCM56960_A0fmt */ 11766 /* format CMIC_XGXS3_PLL_CONTROL_4fmt */ 11767 /* nFields */ 16, 11768 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_4_BCM56960_A0fmt_fields, 11769 /* bits */ 32, 11770 /* flags */ 0, 11771 }, 11772 #endif /* chips */ 11773 11774 #if defined(BCM_56965_A0) 11775 { /* SOC_FORMAT_INT_CMIC_XGXS3_PLL_CONTROL_4_BCM56965_A0fmt */ 11776 /* format CMIC_XGXS3_PLL_CONTROL_4fmt */ 11777 /* nFields */ 16, 11778 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_4_BCM56960_A0fmt_fields, 11779 /* bits */ 32, 11780 /* flags */ 0, 11781 }, 11782 #endif /* chips */ 11783 11784 #if defined(BCM_56970_A0) 11785 { /* SOC_FORMAT_INT_CMIC_XGXS3_PLL_CONTROL_4_BCM56970_A0fmt */ 11786 /* format CMIC_XGXS3_PLL_CONTROL_4fmt */ 11787 /* nFields */ 16, 11788 /* *fields */ soc_CMIC_XGXS0_PLL_CONTROL_4_BCM56960_A0fmt_fields, 11789 /* bits */ 32, 11790 /* flags */ 0, 11791 }, 11792 #endif /* chips */ 11793 11794 #if defined(BCM_56334_A0) || defined(BCM_56440_A0) || \ 11795 defined(BCM_56440_B0) || defined(BCM_56524_B0) || \ 11796 defined(BCM_56624_A0) || defined(BCM_56624_B0) || \ 11797 defined(BCM_56634_A0) || defined(BCM_56634_B0) || \ 11798 defined(BCM_56680_A0) || defined(BCM_56680_B0) || \ 11799 defined(BCM_56685_A0) || defined(BCM_56685_B0) || \ 11800 defined(BCM_56725_A0) || defined(BCM_56820_A0) || \ 11801 defined(BCM_56840_A0) || defined(BCM_56840_B0) || \ 11802 defined(BCM_88732_A0) 11803 { /* SOC_FORMAT_INT_CML_OFFSETfmt */ 11804 /* format CML_OFFSETfmt */ 11805 /* nFields */ 4, 11806 /* *fields */ soc_CML_OFFSETfmt_fields, 11807 /* bits */ 4, 11808 /* flags */ 0, 11809 }, 11810 #endif /* chips */ 11811 11812 #if defined(BCM_53400_A0) 11813 { /* SOC_FORMAT_INT_CML_OFFSET_BCM53400_A0fmt */ 11814 /* format CML_OFFSETfmt */ 11815 /* nFields */ 4, 11816 /* *fields */ soc_CML_OFFSET_BCM53400_A0fmt_fields, 11817 /* bits */ 4, 11818 /* flags */ 0, 11819 }, 11820 #endif /* chips */ 11821 11822 #if defined(BCM_53540_A0) 11823 { /* SOC_FORMAT_INT_CML_OFFSET_BCM53540_A0fmt */ 11824 /* format CML_OFFSETfmt */ 11825 /* nFields */ 4, 11826 /* *fields */ soc_CML_OFFSET_BCM53400_A0fmt_fields, 11827 /* bits */ 4, 11828 /* flags */ 0, 11829 }, 11830 #endif /* chips */ 11831 11832 #if defined(BCM_53570_A0) 11833 { /* SOC_FORMAT_INT_CML_OFFSET_BCM53570_A0fmt */ 11834 /* format CML_OFFSETfmt */ 11835 /* nFields */ 4, 11836 /* *fields */ soc_CML_OFFSET_BCM53400_A0fmt_fields, 11837 /* bits */ 4, 11838 /* flags */ 0, 11839 }, 11840 #endif /* chips */ 11841 11842 #if defined(BCM_53570_B0) 11843 { /* SOC_FORMAT_INT_CML_OFFSET_BCM53570_B0fmt */ 11844 /* format CML_OFFSETfmt */ 11845 /* nFields */ 4, 11846 /* *fields */ soc_CML_OFFSET_BCM53400_A0fmt_fields, 11847 /* bits */ 4, 11848 /* flags */ 0, 11849 }, 11850 #endif /* chips */ 11851 11852 #if defined(BCM_56142_A0) 11853 { /* SOC_FORMAT_INT_CML_OFFSET_BCM56142_A0fmt */ 11854 /* format CML_OFFSETfmt */ 11855 /* nFields */ 4, 11856 /* *fields */ soc_CML_OFFSETfmt_fields, 11857 /* bits */ 4, 11858 /* flags */ 0, 11859 }, 11860 #endif /* chips */ 11861 11862 #if defined(BCM_56150_A0) 11863 { /* SOC_FORMAT_INT_CML_OFFSET_BCM56150_A0fmt */ 11864 /* format CML_OFFSETfmt */ 11865 /* nFields */ 4, 11866 /* *fields */ soc_CML_OFFSET_BCM56640_A0fmt_fields, 11867 /* bits */ 4, 11868 /* flags */ 0, 11869 }, 11870 #endif /* chips */ 11871 11872 #if defined(BCM_56160_A0) 11873 { /* SOC_FORMAT_INT_CML_OFFSET_BCM56160_A0fmt */ 11874 /* format CML_OFFSETfmt */ 11875 /* nFields */ 4, 11876 /* *fields */ soc_CML_OFFSET_BCM53400_A0fmt_fields, 11877 /* bits */ 4, 11878 /* flags */ 0, 11879 }, 11880 #endif /* chips */ 11881 11882 #if defined(BCM_56260_A0) 11883 { /* SOC_FORMAT_INT_CML_OFFSET_BCM56260_A0fmt */ 11884 /* format CML_OFFSETfmt */ 11885 /* nFields */ 4, 11886 /* *fields */ soc_CML_OFFSET_BCM53400_A0fmt_fields, 11887 /* bits */ 4, 11888 /* flags */ 0, 11889 }, 11890 #endif /* chips */ 11891 11892 #if defined(BCM_56260_B0) 11893 { /* SOC_FORMAT_INT_CML_OFFSET_BCM56260_B0fmt */ 11894 /* format CML_OFFSETfmt */ 11895 /* nFields */ 4, 11896 /* *fields */ soc_CML_OFFSET_BCM53400_A0fmt_fields, 11897 /* bits */ 4, 11898 /* flags */ 0, 11899 }, 11900 #endif /* chips */ 11901 11902 #if defined(BCM_56270_A0) 11903 { /* SOC_FORMAT_INT_CML_OFFSET_BCM56270_A0fmt */ 11904 /* format CML_OFFSETfmt */ 11905 /* nFields */ 4, 11906 /* *fields */ soc_CML_OFFSET_BCM53400_A0fmt_fields, 11907 /* bits */ 4, 11908 /* flags */ 0, 11909 }, 11910 #endif /* chips */ 11911 11912 #if defined(BCM_56334_B0) 11913 { /* SOC_FORMAT_INT_CML_OFFSET_BCM56334_B0fmt */ 11914 /* format CML_OFFSETfmt */ 11915 /* nFields */ 4, 11916 /* *fields */ soc_CML_OFFSETfmt_fields, 11917 /* bits */ 4, 11918 /* flags */ 0, 11919 }, 11920 #endif /* chips */ 11921 11922 #if defined(BCM_56340_A0) 11923 { /* SOC_FORMAT_INT_CML_OFFSET_BCM56340_A0fmt */ 11924 /* format CML_OFFSETfmt */ 11925 /* nFields */ 4, 11926 /* *fields */ soc_CML_OFFSET_BCM56640_A0fmt_fields, 11927 /* bits */ 4, 11928 /* flags */ 0, 11929 }, 11930 #endif /* chips */ 11931 11932 #if defined(BCM_56370_A0) 11933 { /* SOC_FORMAT_INT_CML_OFFSET_BCM56370_A0fmt */ 11934 /* format CML_OFFSETfmt */ 11935 /* nFields */ 4, 11936 /* *fields */ soc_CML_OFFSET_BCM53400_A0fmt_fields, 11937 /* bits */ 4, 11938 /* flags */ 0, 11939 }, 11940 #endif /* chips */ 11941 11942 #if defined(BCM_56450_A0) 11943 { /* SOC_FORMAT_INT_CML_OFFSET_BCM56450_A0fmt */ 11944 /* format CML_OFFSETfmt */ 11945 /* nFields */ 4, 11946 /* *fields */ soc_CML_OFFSET_BCM56640_A0fmt_fields, 11947 /* bits */ 4, 11948 /* flags */ 0, 11949 }, 11950 #endif /* chips */ 11951 11952 #if defined(BCM_56450_B0) 11953 { /* SOC_FORMAT_INT_CML_OFFSET_BCM56450_B0fmt */ 11954 /* format CML_OFFSETfmt */ 11955 /* nFields */ 4, 11956 /* *fields */ soc_CML_OFFSET_BCM56640_A0fmt_fields, 11957 /* bits */ 4, 11958 /* flags */ 0, 11959 }, 11960 #endif /* chips */ 11961 11962 #if defined(BCM_56450_B1) 11963 { /* SOC_FORMAT_INT_CML_OFFSET_BCM56450_B1fmt */ 11964 /* format CML_OFFSETfmt */ 11965 /* nFields */ 4, 11966 /* *fields */ soc_CML_OFFSET_BCM56640_A0fmt_fields, 11967 /* bits */ 4, 11968 /* flags */ 0, 11969 }, 11970 #endif /* chips */ 11971 11972 #if defined(BCM_56524_A0) 11973 { /* SOC_FORMAT_INT_CML_OFFSET_BCM56524_A0fmt */ 11974 /* format CML_OFFSETfmt */ 11975 /* nFields */ 4, 11976 /* *fields */ soc_CML_OFFSETfmt_fields, 11977 /* bits */ 4, 11978 /* flags */ 0, 11979 }, 11980 #endif /* chips */ 11981 11982 #if defined(BCM_56560_A0) 11983 { /* SOC_FORMAT_INT_CML_OFFSET_BCM56560_A0fmt */ 11984 /* format CML_OFFSETfmt */ 11985 /* nFields */ 4, 11986 /* *fields */ soc_CML_OFFSET_BCM53400_A0fmt_fields, 11987 /* bits */ 4, 11988 /* flags */ 0, 11989 }, 11990 #endif /* chips */ 11991 11992 #if defined(BCM_56560_B0) 11993 { /* SOC_FORMAT_INT_CML_OFFSET_BCM56560_B0fmt */ 11994 /* format CML_OFFSETfmt */ 11995 /* nFields */ 4, 11996 /* *fields */ soc_CML_OFFSET_BCM53400_A0fmt_fields, 11997 /* bits */ 4, 11998 /* flags */ 0, 11999 }, 12000 #endif /* chips */ 12001 12002 #if defined(BCM_56640_A0) 12003 { /* SOC_FORMAT_INT_CML_OFFSET_BCM56640_A0fmt */ 12004 /* format CML_OFFSETfmt */ 12005 /* nFields */ 4, 12006 /* *fields */ soc_CML_OFFSET_BCM56640_A0fmt_fields, 12007 /* bits */ 4, 12008 /* flags */ 0, 12009 }, 12010 #endif /* chips */ 12011 12012 #if defined(BCM_56670_A0) 12013 { /* SOC_FORMAT_INT_CML_OFFSET_BCM56670_A0fmt */ 12014 /* format CML_OFFSETfmt */ 12015 /* nFields */ 4, 12016 /* *fields */ soc_CML_OFFSET_BCM53400_A0fmt_fields, 12017 /* bits */ 4, 12018 /* flags */ 0, 12019 }, 12020 #endif /* chips */ 12021 12022 #if defined(BCM_56670_B0) 12023 { /* SOC_FORMAT_INT_CML_OFFSET_BCM56670_B0fmt */ 12024 /* format CML_OFFSETfmt */ 12025 /* nFields */ 4, 12026 /* *fields */ soc_CML_OFFSET_BCM53400_A0fmt_fields, 12027 /* bits */ 4, 12028 /* flags */ 0, 12029 }, 12030 #endif /* chips */ 12031 12032 #if defined(BCM_56770_A0) 12033 { /* SOC_FORMAT_INT_CML_OFFSET_BCM56770_A0fmt */ 12034 /* format CML_OFFSETfmt */ 12035 /* nFields */ 4, 12036 /* *fields */ soc_CML_OFFSET_BCM53400_A0fmt_fields, 12037 /* bits */ 4, 12038 /* flags */ 0, 12039 }, 12040 #endif /* chips */ 12041 12042 #if defined(BCM_56850_A0) 12043 { /* SOC_FORMAT_INT_CML_OFFSET_BCM56850_A0fmt */ 12044 /* format CML_OFFSETfmt */ 12045 /* nFields */ 4, 12046 /* *fields */ soc_CML_OFFSET_BCM56640_A0fmt_fields, 12047 /* bits */ 4, 12048 /* flags */ 0, 12049 }, 12050 #endif /* chips */ 12051 12052 #if defined(BCM_56860_A0) 12053 { /* SOC_FORMAT_INT_CML_OFFSET_BCM56860_A0fmt */ 12054 /* format CML_OFFSETfmt */ 12055 /* nFields */ 4, 12056 /* *fields */ soc_CML_OFFSET_BCM56640_A0fmt_fields, 12057 /* bits */ 4, 12058 /* flags */ 0, 12059 }, 12060 #endif /* chips */ 12061 12062 #if defined(BCM_56870_A0) 12063 { /* SOC_FORMAT_INT_CML_OFFSET_BCM56870_A0fmt */ 12064 /* format CML_OFFSETfmt */ 12065 /* nFields */ 4, 12066 /* *fields */ soc_CML_OFFSET_BCM53400_A0fmt_fields, 12067 /* bits */ 4, 12068 /* flags */ 0, 12069 }, 12070 #endif /* chips */ 12071 12072 #if defined(BCM_56960_A0) 12073 { /* SOC_FORMAT_INT_CML_OFFSET_BCM56960_A0fmt */ 12074 /* format CML_OFFSETfmt */ 12075 /* nFields */ 4, 12076 /* *fields */ soc_CML_OFFSET_BCM53400_A0fmt_fields, 12077 /* bits */ 4, 12078 /* flags */ 0, 12079 }, 12080 #endif /* chips */ 12081 12082 #if defined(BCM_56965_A0) 12083 { /* SOC_FORMAT_INT_CML_OFFSET_BCM56965_A0fmt */ 12084 /* format CML_OFFSETfmt */ 12085 /* nFields */ 4, 12086 /* *fields */ soc_CML_OFFSET_BCM53400_A0fmt_fields, 12087 /* bits */ 4, 12088 /* flags */ 0, 12089 }, 12090 #endif /* chips */ 12091 12092 #if defined(BCM_56970_A0) 12093 { /* SOC_FORMAT_INT_CML_OFFSET_BCM56970_A0fmt */ 12094 /* format CML_OFFSETfmt */ 12095 /* nFields */ 4, 12096 /* *fields */ soc_CML_OFFSET_BCM53400_A0fmt_fields, 12097 /* bits */ 4, 12098 /* flags */ 0, 12099 }, 12100 #endif /* chips */ 12101 12102 #if defined(BCM_56980_A0) 12103 { /* SOC_FORMAT_INT_CML_OFFSET_BCM56980_A0fmt */ 12104 /* format CML_OFFSETfmt */ 12105 /* nFields */ 4, 12106 /* *fields */ soc_CML_OFFSET_BCM56980_A0fmt_fields, 12107 /* bits */ 4, 12108 /* flags */ 0, 12109 }, 12110 #endif /* chips */ 12111 12112 #if defined(BCM_56980_B0) 12113 { /* SOC_FORMAT_INT_CML_OFFSET_BCM56980_B0fmt */ 12114 /* format CML_OFFSETfmt */ 12115 /* nFields */ 4, 12116 /* *fields */ soc_CML_OFFSET_BCM56980_A0fmt_fields, 12117 /* bits */ 4, 12118 /* flags */ 0, 12119 }, 12120 #endif /* chips */ 12121 12122 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 12123 defined(BCM_56870_A0) 12124 { /* SOC_FORMAT_INT_CNTAG_ACTION_SETfmt */ 12125 /* format CNTAG_ACTION_SETfmt */ 12126 /* nFields */ 1, 12127 /* *fields */ soc_CNTAG_ACTION_SETfmt_fields, 12128 /* bits */ 8, 12129 /* flags */ 0, 12130 }, 12131 #endif /* chips */ 12132 12133 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 12134 defined(BCM_56870_A0) 12135 { /* SOC_FORMAT_INT_CNTAG_HDRfmt */ 12136 /* format CNTAG_HDRfmt */ 12137 /* nFields */ 1, 12138 /* *fields */ soc_CNTAG_HDRfmt_fields, 12139 /* bits */ 16, 12140 /* flags */ 0, 12141 }, 12142 #endif /* chips */ 12143 12144 #if defined(BCM_56340_A0) || defined(BCM_56640_A0) 12145 { /* SOC_FORMAT_INT_COMMON_HEADER_TYPESfmt */ 12146 /* format COMMON_HEADER_TYPESfmt */ 12147 /* nFields */ 1, 12148 /* *fields */ soc_COMMON_HEADER_TYPESfmt_fields, 12149 /* bits */ 6, 12150 /* flags */ 0, 12151 }, 12152 #endif /* chips */ 12153 12154 #if defined(BCM_56370_A0) 12155 { /* SOC_FORMAT_INT_COMMON_HEADER_TYPES_BCM56370_A0fmt */ 12156 /* format COMMON_HEADER_TYPESfmt */ 12157 /* nFields */ 1, 12158 /* *fields */ soc_COMMON_HEADER_TYPES_BCM56960_A0fmt_fields, 12159 /* bits */ 5, 12160 /* flags */ 0, 12161 }, 12162 #endif /* chips */ 12163 12164 #if defined(BCM_56560_A0) 12165 { /* SOC_FORMAT_INT_COMMON_HEADER_TYPES_BCM56560_A0fmt */ 12166 /* format COMMON_HEADER_TYPESfmt */ 12167 /* nFields */ 1, 12168 /* *fields */ soc_COMMON_HEADER_TYPES_BCM56560_A0fmt_fields, 12169 /* bits */ 4, 12170 /* flags */ 0, 12171 }, 12172 #endif /* chips */ 12173 12174 #if defined(BCM_56560_B0) 12175 { /* SOC_FORMAT_INT_COMMON_HEADER_TYPES_BCM56560_B0fmt */ 12176 /* format COMMON_HEADER_TYPESfmt */ 12177 /* nFields */ 1, 12178 /* *fields */ soc_COMMON_HEADER_TYPES_BCM56560_A0fmt_fields, 12179 /* bits */ 4, 12180 /* flags */ 0, 12181 }, 12182 #endif /* chips */ 12183 12184 #if defined(BCM_56670_A0) 12185 { /* SOC_FORMAT_INT_COMMON_HEADER_TYPES_BCM56670_A0fmt */ 12186 /* format COMMON_HEADER_TYPESfmt */ 12187 /* nFields */ 1, 12188 /* *fields */ soc_COMMON_HEADER_TYPES_BCM56560_A0fmt_fields, 12189 /* bits */ 4, 12190 /* flags */ 0, 12191 }, 12192 #endif /* chips */ 12193 12194 #if defined(BCM_56670_B0) 12195 { /* SOC_FORMAT_INT_COMMON_HEADER_TYPES_BCM56670_B0fmt */ 12196 /* format COMMON_HEADER_TYPESfmt */ 12197 /* nFields */ 1, 12198 /* *fields */ soc_COMMON_HEADER_TYPES_BCM56560_A0fmt_fields, 12199 /* bits */ 4, 12200 /* flags */ 0, 12201 }, 12202 #endif /* chips */ 12203 12204 #if defined(BCM_56770_A0) 12205 { /* SOC_FORMAT_INT_COMMON_HEADER_TYPES_BCM56770_A0fmt */ 12206 /* format COMMON_HEADER_TYPESfmt */ 12207 /* nFields */ 1, 12208 /* *fields */ soc_COMMON_HEADER_TYPES_BCM56960_A0fmt_fields, 12209 /* bits */ 5, 12210 /* flags */ 0, 12211 }, 12212 #endif /* chips */ 12213 12214 #if defined(BCM_56850_A0) 12215 { /* SOC_FORMAT_INT_COMMON_HEADER_TYPES_BCM56850_A0fmt */ 12216 /* format COMMON_HEADER_TYPESfmt */ 12217 /* nFields */ 1, 12218 /* *fields */ soc_COMMON_HEADER_TYPES_BCM56850_A0fmt_fields, 12219 /* bits */ 3, 12220 /* flags */ 0, 12221 }, 12222 #endif /* chips */ 12223 12224 #if defined(BCM_56860_A0) 12225 { /* SOC_FORMAT_INT_COMMON_HEADER_TYPES_BCM56860_A0fmt */ 12226 /* format COMMON_HEADER_TYPESfmt */ 12227 /* nFields */ 1, 12228 /* *fields */ soc_COMMON_HEADER_TYPES_BCM56850_A0fmt_fields, 12229 /* bits */ 3, 12230 /* flags */ 0, 12231 }, 12232 #endif /* chips */ 12233 12234 #if defined(BCM_56870_A0) 12235 { /* SOC_FORMAT_INT_COMMON_HEADER_TYPES_BCM56870_A0fmt */ 12236 /* format COMMON_HEADER_TYPESfmt */ 12237 /* nFields */ 1, 12238 /* *fields */ soc_COMMON_HEADER_TYPES_BCM56960_A0fmt_fields, 12239 /* bits */ 5, 12240 /* flags */ 0, 12241 }, 12242 #endif /* chips */ 12243 12244 #if defined(BCM_56960_A0) 12245 { /* SOC_FORMAT_INT_COMMON_HEADER_TYPES_BCM56960_A0fmt */ 12246 /* format COMMON_HEADER_TYPESfmt */ 12247 /* nFields */ 1, 12248 /* *fields */ soc_COMMON_HEADER_TYPES_BCM56960_A0fmt_fields, 12249 /* bits */ 5, 12250 /* flags */ 0, 12251 }, 12252 #endif /* chips */ 12253 12254 #if defined(BCM_56965_A0) 12255 { /* SOC_FORMAT_INT_COMMON_HEADER_TYPES_BCM56965_A0fmt */ 12256 /* format COMMON_HEADER_TYPESfmt */ 12257 /* nFields */ 1, 12258 /* *fields */ soc_COMMON_HEADER_TYPES_BCM56960_A0fmt_fields, 12259 /* bits */ 5, 12260 /* flags */ 0, 12261 }, 12262 #endif /* chips */ 12263 12264 #if defined(BCM_56970_A0) 12265 { /* SOC_FORMAT_INT_COMMON_HEADER_TYPES_BCM56970_A0fmt */ 12266 /* format COMMON_HEADER_TYPESfmt */ 12267 /* nFields */ 1, 12268 /* *fields */ soc_COMMON_HEADER_TYPES_BCM56960_A0fmt_fields, 12269 /* bits */ 5, 12270 /* flags */ 0, 12271 }, 12272 #endif /* chips */ 12273 12274 #if defined(BCM_56980_A0) 12275 { /* SOC_FORMAT_INT_COMMON_HEADER_TYPES_BCM56980_A0fmt */ 12276 /* format COMMON_HEADER_TYPESfmt */ 12277 /* nFields */ 1, 12278 /* *fields */ soc_COMMON_HEADER_TYPES_BCM56960_A0fmt_fields, 12279 /* bits */ 5, 12280 /* flags */ 0, 12281 }, 12282 #endif /* chips */ 12283 12284 #if defined(BCM_56980_B0) 12285 { /* SOC_FORMAT_INT_COMMON_HEADER_TYPES_BCM56980_B0fmt */ 12286 /* format COMMON_HEADER_TYPESfmt */ 12287 /* nFields */ 1, 12288 /* *fields */ soc_COMMON_HEADER_TYPES_BCM56960_A0fmt_fields, 12289 /* bits */ 5, 12290 /* flags */ 0, 12291 }, 12292 #endif /* chips */ 12293 12294 #if defined(BCM_56624_A0) 12295 { /* SOC_FORMAT_INT_COPYTO_CPUfmt */ 12296 /* format COPYTO_CPUfmt */ 12297 /* nFields */ 44, 12298 /* *fields */ soc_COPYTO_CPUfmt_fields, 12299 /* bits */ 44, 12300 /* flags */ 0, 12301 }, 12302 #endif /* chips */ 12303 12304 #if defined(BCM_53400_A0) 12305 { /* SOC_FORMAT_INT_COPYTO_CPU_BCM53400_A0fmt */ 12306 /* format COPYTO_CPUfmt */ 12307 /* nFields */ 54, 12308 /* *fields */ soc_COPYTO_CPU_BCM53400_A0fmt_fields, 12309 /* bits */ 56, 12310 /* flags */ 0, 12311 }, 12312 #endif /* chips */ 12313 12314 #if defined(BCM_53540_A0) 12315 { /* SOC_FORMAT_INT_COPYTO_CPU_BCM53540_A0fmt */ 12316 /* format COPYTO_CPUfmt */ 12317 /* nFields */ 54, 12318 /* *fields */ soc_COPYTO_CPU_BCM53400_A0fmt_fields, 12319 /* bits */ 56, 12320 /* flags */ 0, 12321 }, 12322 #endif /* chips */ 12323 12324 #if defined(BCM_53570_A0) 12325 { /* SOC_FORMAT_INT_COPYTO_CPU_BCM53570_A0fmt */ 12326 /* format COPYTO_CPUfmt */ 12327 /* nFields */ 59, 12328 /* *fields */ soc_COPYTO_CPU_BCM53570_A0fmt_fields, 12329 /* bits */ 65, 12330 /* flags */ 0, 12331 }, 12332 #endif /* chips */ 12333 12334 #if defined(BCM_53570_B0) 12335 { /* SOC_FORMAT_INT_COPYTO_CPU_BCM53570_B0fmt */ 12336 /* format COPYTO_CPUfmt */ 12337 /* nFields */ 59, 12338 /* *fields */ soc_COPYTO_CPU_BCM53570_A0fmt_fields, 12339 /* bits */ 65, 12340 /* flags */ 0, 12341 }, 12342 #endif /* chips */ 12343 12344 #if defined(BCM_56142_A0) 12345 { /* SOC_FORMAT_INT_COPYTO_CPU_BCM56142_A0fmt */ 12346 /* format COPYTO_CPUfmt */ 12347 /* nFields */ 51, 12348 /* *fields */ soc_COPYTO_CPU_BCM56334_A0fmt_fields, 12349 /* bits */ 56, 12350 /* flags */ 0, 12351 }, 12352 #endif /* chips */ 12353 12354 #if defined(BCM_56150_A0) 12355 { /* SOC_FORMAT_INT_COPYTO_CPU_BCM56150_A0fmt */ 12356 /* format COPYTO_CPUfmt */ 12357 /* nFields */ 54, 12358 /* *fields */ soc_COPYTO_CPU_BCM56150_A0fmt_fields, 12359 /* bits */ 56, 12360 /* flags */ 0, 12361 }, 12362 #endif /* chips */ 12363 12364 #if defined(BCM_56160_A0) 12365 { /* SOC_FORMAT_INT_COPYTO_CPU_BCM56160_A0fmt */ 12366 /* format COPYTO_CPUfmt */ 12367 /* nFields */ 54, 12368 /* *fields */ soc_COPYTO_CPU_BCM53400_A0fmt_fields, 12369 /* bits */ 56, 12370 /* flags */ 0, 12371 }, 12372 #endif /* chips */ 12373 12374 #if defined(BCM_56260_A0) 12375 { /* SOC_FORMAT_INT_COPYTO_CPU_BCM56260_A0fmt */ 12376 /* format COPYTO_CPUfmt */ 12377 /* nFields */ 78, 12378 /* *fields */ soc_COPYTO_CPU_BCM56260_A0fmt_fields, 12379 /* bits */ 76, 12380 /* flags */ 0, 12381 }, 12382 #endif /* chips */ 12383 12384 #if defined(BCM_56260_B0) 12385 { /* SOC_FORMAT_INT_COPYTO_CPU_BCM56260_B0fmt */ 12386 /* format COPYTO_CPUfmt */ 12387 /* nFields */ 78, 12388 /* *fields */ soc_COPYTO_CPU_BCM56260_A0fmt_fields, 12389 /* bits */ 76, 12390 /* flags */ 0, 12391 }, 12392 #endif /* chips */ 12393 12394 #if defined(BCM_56270_A0) 12395 { /* SOC_FORMAT_INT_COPYTO_CPU_BCM56270_A0fmt */ 12396 /* format COPYTO_CPUfmt */ 12397 /* nFields */ 78, 12398 /* *fields */ soc_COPYTO_CPU_BCM56260_A0fmt_fields, 12399 /* bits */ 76, 12400 /* flags */ 0, 12401 }, 12402 #endif /* chips */ 12403 12404 #if defined(BCM_56334_A0) 12405 { /* SOC_FORMAT_INT_COPYTO_CPU_BCM56334_A0fmt */ 12406 /* format COPYTO_CPUfmt */ 12407 /* nFields */ 51, 12408 /* *fields */ soc_COPYTO_CPU_BCM56334_A0fmt_fields, 12409 /* bits */ 56, 12410 /* flags */ 0, 12411 }, 12412 #endif /* chips */ 12413 12414 #if defined(BCM_56334_B0) 12415 { /* SOC_FORMAT_INT_COPYTO_CPU_BCM56334_B0fmt */ 12416 /* format COPYTO_CPUfmt */ 12417 /* nFields */ 51, 12418 /* *fields */ soc_COPYTO_CPU_BCM56334_A0fmt_fields, 12419 /* bits */ 56, 12420 /* flags */ 0, 12421 }, 12422 #endif /* chips */ 12423 12424 #if defined(BCM_56340_A0) 12425 { /* SOC_FORMAT_INT_COPYTO_CPU_BCM56340_A0fmt */ 12426 /* format COPYTO_CPUfmt */ 12427 /* nFields */ 93, 12428 /* *fields */ soc_COPYTO_CPU_BCM56340_A0fmt_fields, 12429 /* bits */ 101, 12430 /* flags */ 0, 12431 }, 12432 #endif /* chips */ 12433 12434 #if defined(BCM_56370_A0) 12435 { /* SOC_FORMAT_INT_COPYTO_CPU_BCM56370_A0fmt */ 12436 /* format COPYTO_CPUfmt */ 12437 /* nFields */ 94, 12438 /* *fields */ soc_COPYTO_CPU_BCM56370_A0fmt_fields, 12439 /* bits */ 102, 12440 /* flags */ 0, 12441 }, 12442 #endif /* chips */ 12443 12444 #if defined(BCM_56440_A0) 12445 { /* SOC_FORMAT_INT_COPYTO_CPU_BCM56440_A0fmt */ 12446 /* format COPYTO_CPUfmt */ 12447 /* nFields */ 61, 12448 /* *fields */ soc_COPYTO_CPU_BCM56440_A0fmt_fields, 12449 /* bits */ 62, 12450 /* flags */ 0, 12451 }, 12452 #endif /* chips */ 12453 12454 #if defined(BCM_56440_B0) 12455 { /* SOC_FORMAT_INT_COPYTO_CPU_BCM56440_B0fmt */ 12456 /* format COPYTO_CPUfmt */ 12457 /* nFields */ 61, 12458 /* *fields */ soc_COPYTO_CPU_BCM56440_A0fmt_fields, 12459 /* bits */ 62, 12460 /* flags */ 0, 12461 }, 12462 #endif /* chips */ 12463 12464 #if defined(BCM_56450_A0) 12465 { /* SOC_FORMAT_INT_COPYTO_CPU_BCM56450_A0fmt */ 12466 /* format COPYTO_CPUfmt */ 12467 /* nFields */ 73, 12468 /* *fields */ soc_COPYTO_CPU_BCM56450_A0fmt_fields, 12469 /* bits */ 74, 12470 /* flags */ 0, 12471 }, 12472 #endif /* chips */ 12473 12474 #if defined(BCM_56450_B0) 12475 { /* SOC_FORMAT_INT_COPYTO_CPU_BCM56450_B0fmt */ 12476 /* format COPYTO_CPUfmt */ 12477 /* nFields */ 73, 12478 /* *fields */ soc_COPYTO_CPU_BCM56450_A0fmt_fields, 12479 /* bits */ 74, 12480 /* flags */ 0, 12481 }, 12482 #endif /* chips */ 12483 12484 #if defined(BCM_56450_B1) 12485 { /* SOC_FORMAT_INT_COPYTO_CPU_BCM56450_B1fmt */ 12486 /* format COPYTO_CPUfmt */ 12487 /* nFields */ 73, 12488 /* *fields */ soc_COPYTO_CPU_BCM56450_A0fmt_fields, 12489 /* bits */ 74, 12490 /* flags */ 0, 12491 }, 12492 #endif /* chips */ 12493 12494 #if defined(BCM_56524_A0) 12495 { /* SOC_FORMAT_INT_COPYTO_CPU_BCM56524_A0fmt */ 12496 /* format COPYTO_CPUfmt */ 12497 /* nFields */ 58, 12498 /* *fields */ soc_COPYTO_CPU_BCM56634_A0fmt_fields, 12499 /* bits */ 58, 12500 /* flags */ 0, 12501 }, 12502 #endif /* chips */ 12503 12504 #if defined(BCM_56524_B0) 12505 { /* SOC_FORMAT_INT_COPYTO_CPU_BCM56524_B0fmt */ 12506 /* format COPYTO_CPUfmt */ 12507 /* nFields */ 58, 12508 /* *fields */ soc_COPYTO_CPU_BCM56634_A0fmt_fields, 12509 /* bits */ 58, 12510 /* flags */ 0, 12511 }, 12512 #endif /* chips */ 12513 12514 #if defined(BCM_56560_A0) 12515 { /* SOC_FORMAT_INT_COPYTO_CPU_BCM56560_A0fmt */ 12516 /* format COPYTO_CPUfmt */ 12517 /* nFields */ 81, 12518 /* *fields */ soc_COPYTO_CPU_BCM56560_A0fmt_fields, 12519 /* bits */ 83, 12520 /* flags */ 0, 12521 }, 12522 #endif /* chips */ 12523 12524 #if defined(BCM_56560_B0) 12525 { /* SOC_FORMAT_INT_COPYTO_CPU_BCM56560_B0fmt */ 12526 /* format COPYTO_CPUfmt */ 12527 /* nFields */ 81, 12528 /* *fields */ soc_COPYTO_CPU_BCM56560_A0fmt_fields, 12529 /* bits */ 83, 12530 /* flags */ 0, 12531 }, 12532 #endif /* chips */ 12533 12534 #if defined(BCM_56624_B0) 12535 { /* SOC_FORMAT_INT_COPYTO_CPU_BCM56624_B0fmt */ 12536 /* format COPYTO_CPUfmt */ 12537 /* nFields */ 45, 12538 /* *fields */ soc_COPYTO_CPU_BCM56624_B0fmt_fields, 12539 /* bits */ 45, 12540 /* flags */ 0, 12541 }, 12542 #endif /* chips */ 12543 12544 #if defined(BCM_56634_A0) 12545 { /* SOC_FORMAT_INT_COPYTO_CPU_BCM56634_A0fmt */ 12546 /* format COPYTO_CPUfmt */ 12547 /* nFields */ 58, 12548 /* *fields */ soc_COPYTO_CPU_BCM56634_A0fmt_fields, 12549 /* bits */ 58, 12550 /* flags */ 0, 12551 }, 12552 #endif /* chips */ 12553 12554 #if defined(BCM_56634_B0) 12555 { /* SOC_FORMAT_INT_COPYTO_CPU_BCM56634_B0fmt */ 12556 /* format COPYTO_CPUfmt */ 12557 /* nFields */ 58, 12558 /* *fields */ soc_COPYTO_CPU_BCM56634_A0fmt_fields, 12559 /* bits */ 58, 12560 /* flags */ 0, 12561 }, 12562 #endif /* chips */ 12563 12564 #if defined(BCM_56640_A0) 12565 { /* SOC_FORMAT_INT_COPYTO_CPU_BCM56640_A0fmt */ 12566 /* format COPYTO_CPUfmt */ 12567 /* nFields */ 93, 12568 /* *fields */ soc_COPYTO_CPU_BCM56640_A0fmt_fields, 12569 /* bits */ 101, 12570 /* flags */ 0, 12571 }, 12572 #endif /* chips */ 12573 12574 #if defined(BCM_56670_A0) 12575 { /* SOC_FORMAT_INT_COPYTO_CPU_BCM56670_A0fmt */ 12576 /* format COPYTO_CPUfmt */ 12577 /* nFields */ 81, 12578 /* *fields */ soc_COPYTO_CPU_BCM56560_A0fmt_fields, 12579 /* bits */ 83, 12580 /* flags */ 0, 12581 }, 12582 #endif /* chips */ 12583 12584 #if defined(BCM_56670_B0) 12585 { /* SOC_FORMAT_INT_COPYTO_CPU_BCM56670_B0fmt */ 12586 /* format COPYTO_CPUfmt */ 12587 /* nFields */ 81, 12588 /* *fields */ soc_COPYTO_CPU_BCM56560_A0fmt_fields, 12589 /* bits */ 83, 12590 /* flags */ 0, 12591 }, 12592 #endif /* chips */ 12593 12594 #if defined(BCM_56680_A0) 12595 { /* SOC_FORMAT_INT_COPYTO_CPU_BCM56680_A0fmt */ 12596 /* format COPYTO_CPUfmt */ 12597 /* nFields */ 44, 12598 /* *fields */ soc_COPYTO_CPUfmt_fields, 12599 /* bits */ 44, 12600 /* flags */ 0, 12601 }, 12602 #endif /* chips */ 12603 12604 #if defined(BCM_56680_B0) 12605 { /* SOC_FORMAT_INT_COPYTO_CPU_BCM56680_B0fmt */ 12606 /* format COPYTO_CPUfmt */ 12607 /* nFields */ 45, 12608 /* *fields */ soc_COPYTO_CPU_BCM56624_B0fmt_fields, 12609 /* bits */ 45, 12610 /* flags */ 0, 12611 }, 12612 #endif /* chips */ 12613 12614 #if defined(BCM_56685_A0) 12615 { /* SOC_FORMAT_INT_COPYTO_CPU_BCM56685_A0fmt */ 12616 /* format COPYTO_CPUfmt */ 12617 /* nFields */ 58, 12618 /* *fields */ soc_COPYTO_CPU_BCM56634_A0fmt_fields, 12619 /* bits */ 58, 12620 /* flags */ 0, 12621 }, 12622 #endif /* chips */ 12623 12624 #if defined(BCM_56685_B0) 12625 { /* SOC_FORMAT_INT_COPYTO_CPU_BCM56685_B0fmt */ 12626 /* format COPYTO_CPUfmt */ 12627 /* nFields */ 58, 12628 /* *fields */ soc_COPYTO_CPU_BCM56634_A0fmt_fields, 12629 /* bits */ 58, 12630 /* flags */ 0, 12631 }, 12632 #endif /* chips */ 12633 12634 #if defined(BCM_56725_A0) 12635 { /* SOC_FORMAT_INT_COPYTO_CPU_BCM56725_A0fmt */ 12636 /* format COPYTO_CPUfmt */ 12637 /* nFields */ 39, 12638 /* *fields */ soc_COPYTO_CPU_BCM56820_A0fmt_fields, 12639 /* bits */ 39, 12640 /* flags */ 0, 12641 }, 12642 #endif /* chips */ 12643 12644 #if defined(BCM_56770_A0) 12645 { /* SOC_FORMAT_INT_COPYTO_CPU_BCM56770_A0fmt */ 12646 /* format COPYTO_CPUfmt */ 12647 /* nFields */ 94, 12648 /* *fields */ soc_COPYTO_CPU_BCM56870_A0fmt_fields, 12649 /* bits */ 102, 12650 /* flags */ 0, 12651 }, 12652 #endif /* chips */ 12653 12654 #if defined(BCM_56820_A0) 12655 { /* SOC_FORMAT_INT_COPYTO_CPU_BCM56820_A0fmt */ 12656 /* format COPYTO_CPUfmt */ 12657 /* nFields */ 39, 12658 /* *fields */ soc_COPYTO_CPU_BCM56820_A0fmt_fields, 12659 /* bits */ 39, 12660 /* flags */ 0, 12661 }, 12662 #endif /* chips */ 12663 12664 #if defined(BCM_56840_A0) 12665 { /* SOC_FORMAT_INT_COPYTO_CPU_BCM56840_A0fmt */ 12666 /* format COPYTO_CPUfmt */ 12667 /* nFields */ 61, 12668 /* *fields */ soc_COPYTO_CPU_BCM56840_A0fmt_fields, 12669 /* bits */ 65, 12670 /* flags */ 0, 12671 }, 12672 #endif /* chips */ 12673 12674 #if defined(BCM_56840_B0) 12675 { /* SOC_FORMAT_INT_COPYTO_CPU_BCM56840_B0fmt */ 12676 /* format COPYTO_CPUfmt */ 12677 /* nFields */ 61, 12678 /* *fields */ soc_COPYTO_CPU_BCM56840_A0fmt_fields, 12679 /* bits */ 65, 12680 /* flags */ 0, 12681 }, 12682 #endif /* chips */ 12683 12684 #if defined(BCM_56850_A0) 12685 { /* SOC_FORMAT_INT_COPYTO_CPU_BCM56850_A0fmt */ 12686 /* format COPYTO_CPUfmt */ 12687 /* nFields */ 76, 12688 /* *fields */ soc_COPYTO_CPU_BCM56850_A0fmt_fields, 12689 /* bits */ 78, 12690 /* flags */ 0, 12691 }, 12692 #endif /* chips */ 12693 12694 #if defined(BCM_56860_A0) 12695 { /* SOC_FORMAT_INT_COPYTO_CPU_BCM56860_A0fmt */ 12696 /* format COPYTO_CPUfmt */ 12697 /* nFields */ 79, 12698 /* *fields */ soc_COPYTO_CPU_BCM56860_A0fmt_fields, 12699 /* bits */ 81, 12700 /* flags */ 0, 12701 }, 12702 #endif /* chips */ 12703 12704 #if defined(BCM_56870_A0) 12705 { /* SOC_FORMAT_INT_COPYTO_CPU_BCM56870_A0fmt */ 12706 /* format COPYTO_CPUfmt */ 12707 /* nFields */ 94, 12708 /* *fields */ soc_COPYTO_CPU_BCM56870_A0fmt_fields, 12709 /* bits */ 102, 12710 /* flags */ 0, 12711 }, 12712 #endif /* chips */ 12713 12714 #if defined(BCM_56960_A0) 12715 { /* SOC_FORMAT_INT_COPYTO_CPU_BCM56960_A0fmt */ 12716 /* format COPYTO_CPUfmt */ 12717 /* nFields */ 79, 12718 /* *fields */ soc_COPYTO_CPU_BCM56960_A0fmt_fields, 12719 /* bits */ 89, 12720 /* flags */ 0, 12721 }, 12722 #endif /* chips */ 12723 12724 #if defined(BCM_56965_A0) 12725 { /* SOC_FORMAT_INT_COPYTO_CPU_BCM56965_A0fmt */ 12726 /* format COPYTO_CPUfmt */ 12727 /* nFields */ 79, 12728 /* *fields */ soc_COPYTO_CPU_BCM56960_A0fmt_fields, 12729 /* bits */ 89, 12730 /* flags */ 0, 12731 }, 12732 #endif /* chips */ 12733 12734 #if defined(BCM_56970_A0) 12735 { /* SOC_FORMAT_INT_COPYTO_CPU_BCM56970_A0fmt */ 12736 /* format COPYTO_CPUfmt */ 12737 /* nFields */ 79, 12738 /* *fields */ soc_COPYTO_CPU_BCM56960_A0fmt_fields, 12739 /* bits */ 89, 12740 /* flags */ 0, 12741 }, 12742 #endif /* chips */ 12743 12744 #if defined(BCM_56980_A0) 12745 { /* SOC_FORMAT_INT_COPYTO_CPU_BCM56980_A0fmt */ 12746 /* format COPYTO_CPUfmt */ 12747 /* nFields */ 72, 12748 /* *fields */ soc_COPYTO_CPU_BCM56980_A0fmt_fields, 12749 /* bits */ 81, 12750 /* flags */ 0, 12751 }, 12752 #endif /* chips */ 12753 12754 #if defined(BCM_56980_B0) 12755 { /* SOC_FORMAT_INT_COPYTO_CPU_BCM56980_B0fmt */ 12756 /* format COPYTO_CPUfmt */ 12757 /* nFields */ 72, 12758 /* *fields */ soc_COPYTO_CPU_BCM56980_A0fmt_fields, 12759 /* bits */ 81, 12760 /* flags */ 0, 12761 }, 12762 #endif /* chips */ 12763 12764 #if defined(BCM_88732_A0) 12765 { /* SOC_FORMAT_INT_COPYTO_CPU_BCM88732_A0fmt */ 12766 /* format COPYTO_CPUfmt */ 12767 /* nFields */ 14, 12768 /* *fields */ soc_COPYTO_CPU_BCM88732_A0fmt_fields, 12769 /* bits */ 14, 12770 /* flags */ 0, 12771 }, 12772 #endif /* chips */ 12773 12774 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 12775 { /* SOC_FORMAT_INT_COUNTER_UPDATE_CODEfmt */ 12776 /* format COUNTER_UPDATE_CODEfmt */ 12777 /* nFields */ 1, 12778 /* *fields */ soc_COUNTER_UPDATE_CODEfmt_fields, 12779 /* bits */ 4, 12780 /* flags */ 0, 12781 }, 12782 #endif /* chips */ 12783 12784 #if defined(BCM_56770_A0) || defined(BCM_56870_A0) 12785 { /* SOC_FORMAT_INT_COUNTER_UPDATE_VECTOR_DOPfmt */ 12786 /* format COUNTER_UPDATE_VECTOR_DOPfmt */ 12787 /* nFields */ 2, 12788 /* *fields */ soc_COUNTER_UPDATE_VECTOR_DOPfmt_fields, 12789 /* bits */ 128, 12790 /* flags */ 0, 12791 }, 12792 #endif /* chips */ 12793 12794 #if defined(BCM_56370_A0) 12795 { /* SOC_FORMAT_INT_COUNTER_UPDATE_VECTOR_DOP_BCM56370_A0fmt */ 12796 /* format COUNTER_UPDATE_VECTOR_DOPfmt */ 12797 /* nFields */ 3, 12798 /* *fields */ soc_COUNTER_UPDATE_VECTOR_DOP_BCM56370_A0fmt_fields, 12799 /* bits */ 160, 12800 /* flags */ 0, 12801 }, 12802 #endif /* chips */ 12803 12804 #if defined(BCM_56340_A0) || defined(BCM_56640_A0) 12805 { /* SOC_FORMAT_INT_CPUQ_QDBfmt */ 12806 /* format CPUQ_QDBfmt */ 12807 /* nFields */ 9, 12808 /* *fields */ soc_CPUQ_QDBfmt_fields, 12809 /* bits */ 22, 12810 /* flags */ 0, 12811 }, 12812 #endif /* chips */ 12813 12814 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 12815 { /* SOC_FORMAT_INT_CPU_COS_MAP_DATA_FORMATfmt */ 12816 /* format CPU_COS_MAP_DATA_FORMATfmt */ 12817 /* nFields */ 5, 12818 /* *fields */ soc_CPU_COS_MAP_DATA_FORMATfmt_fields, 12819 /* bits */ 15, 12820 /* flags */ 0, 12821 }, 12822 #endif /* chips */ 12823 12824 #if defined(BCM_56624_A0) 12825 { /* SOC_FORMAT_INT_CPU_COS_MAP_KEYfmt */ 12826 /* format CPU_COS_MAP_KEYfmt */ 12827 /* nFields */ 48, 12828 /* *fields */ soc_CPU_COS_MAP_KEYfmt_fields, 12829 /* bits */ 67, 12830 /* flags */ 0, 12831 }, 12832 #endif /* chips */ 12833 12834 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 12835 defined(BCM_56870_A0) 12836 { /* SOC_FORMAT_INT_CPU_COS_MAP_KEY0_PROBES_DOPfmt */ 12837 /* format CPU_COS_MAP_KEY0_PROBES_DOPfmt */ 12838 /* nFields */ 4, 12839 /* *fields */ soc_CPU_COS_MAP_KEY0_PROBES_DOPfmt_fields, 12840 /* bits */ 32, 12841 /* flags */ 0, 12842 }, 12843 #endif /* chips */ 12844 12845 #if defined(BCM_53400_A0) 12846 { /* SOC_FORMAT_INT_CPU_COS_MAP_KEY_BCM53400_A0fmt */ 12847 /* format CPU_COS_MAP_KEYfmt */ 12848 /* nFields */ 58, 12849 /* *fields */ soc_CPU_COS_MAP_KEY_BCM53400_A0fmt_fields, 12850 /* bits */ 69, 12851 /* flags */ 0, 12852 }, 12853 #endif /* chips */ 12854 12855 #if defined(BCM_53540_A0) 12856 { /* SOC_FORMAT_INT_CPU_COS_MAP_KEY_BCM53540_A0fmt */ 12857 /* format CPU_COS_MAP_KEYfmt */ 12858 /* nFields */ 58, 12859 /* *fields */ soc_CPU_COS_MAP_KEY_BCM53400_A0fmt_fields, 12860 /* bits */ 69, 12861 /* flags */ 0, 12862 }, 12863 #endif /* chips */ 12864 12865 #if defined(BCM_53570_A0) 12866 { /* SOC_FORMAT_INT_CPU_COS_MAP_KEY_BCM53570_A0fmt */ 12867 /* format CPU_COS_MAP_KEYfmt */ 12868 /* nFields */ 61, 12869 /* *fields */ soc_CPU_COS_MAP_KEY_BCM53570_A0fmt_fields, 12870 /* bits */ 72, 12871 /* flags */ 0, 12872 }, 12873 #endif /* chips */ 12874 12875 #if defined(BCM_53570_B0) 12876 { /* SOC_FORMAT_INT_CPU_COS_MAP_KEY_BCM53570_B0fmt */ 12877 /* format CPU_COS_MAP_KEYfmt */ 12878 /* nFields */ 61, 12879 /* *fields */ soc_CPU_COS_MAP_KEY_BCM53570_A0fmt_fields, 12880 /* bits */ 72, 12881 /* flags */ 0, 12882 }, 12883 #endif /* chips */ 12884 12885 #if defined(BCM_56142_A0) 12886 { /* SOC_FORMAT_INT_CPU_COS_MAP_KEY_BCM56142_A0fmt */ 12887 /* format CPU_COS_MAP_KEYfmt */ 12888 /* nFields */ 54, 12889 /* *fields */ soc_CPU_COS_MAP_KEY_BCM56334_A0fmt_fields, 12890 /* bits */ 67, 12891 /* flags */ 0, 12892 }, 12893 #endif /* chips */ 12894 12895 #if defined(BCM_56150_A0) 12896 { /* SOC_FORMAT_INT_CPU_COS_MAP_KEY_BCM56150_A0fmt */ 12897 /* format CPU_COS_MAP_KEYfmt */ 12898 /* nFields */ 57, 12899 /* *fields */ soc_CPU_COS_MAP_KEY_BCM56150_A0fmt_fields, 12900 /* bits */ 69, 12901 /* flags */ 0, 12902 }, 12903 #endif /* chips */ 12904 12905 #if defined(BCM_56160_A0) 12906 { /* SOC_FORMAT_INT_CPU_COS_MAP_KEY_BCM56160_A0fmt */ 12907 /* format CPU_COS_MAP_KEYfmt */ 12908 /* nFields */ 58, 12909 /* *fields */ soc_CPU_COS_MAP_KEY_BCM53400_A0fmt_fields, 12910 /* bits */ 69, 12911 /* flags */ 0, 12912 }, 12913 #endif /* chips */ 12914 12915 #if defined(BCM_56260_A0) 12916 { /* SOC_FORMAT_INT_CPU_COS_MAP_KEY_BCM56260_A0fmt */ 12917 /* format CPU_COS_MAP_KEYfmt */ 12918 /* nFields */ 5, 12919 /* *fields */ soc_CPU_COS_MAP_KEY_BCM56260_A0fmt_fields, 12920 /* bits */ 83, 12921 /* flags */ 0, 12922 }, 12923 #endif /* chips */ 12924 12925 #if defined(BCM_56260_B0) 12926 { /* SOC_FORMAT_INT_CPU_COS_MAP_KEY_BCM56260_B0fmt */ 12927 /* format CPU_COS_MAP_KEYfmt */ 12928 /* nFields */ 5, 12929 /* *fields */ soc_CPU_COS_MAP_KEY_BCM56260_A0fmt_fields, 12930 /* bits */ 83, 12931 /* flags */ 0, 12932 }, 12933 #endif /* chips */ 12934 12935 #if defined(BCM_56270_A0) 12936 { /* SOC_FORMAT_INT_CPU_COS_MAP_KEY_BCM56270_A0fmt */ 12937 /* format CPU_COS_MAP_KEYfmt */ 12938 /* nFields */ 5, 12939 /* *fields */ soc_CPU_COS_MAP_KEY_BCM56260_A0fmt_fields, 12940 /* bits */ 83, 12941 /* flags */ 0, 12942 }, 12943 #endif /* chips */ 12944 12945 #if defined(BCM_56334_A0) 12946 { /* SOC_FORMAT_INT_CPU_COS_MAP_KEY_BCM56334_A0fmt */ 12947 /* format CPU_COS_MAP_KEYfmt */ 12948 /* nFields */ 54, 12949 /* *fields */ soc_CPU_COS_MAP_KEY_BCM56334_A0fmt_fields, 12950 /* bits */ 67, 12951 /* flags */ 0, 12952 }, 12953 #endif /* chips */ 12954 12955 #if defined(BCM_56334_B0) 12956 { /* SOC_FORMAT_INT_CPU_COS_MAP_KEY_BCM56334_B0fmt */ 12957 /* format CPU_COS_MAP_KEYfmt */ 12958 /* nFields */ 54, 12959 /* *fields */ soc_CPU_COS_MAP_KEY_BCM56334_A0fmt_fields, 12960 /* bits */ 67, 12961 /* flags */ 0, 12962 }, 12963 #endif /* chips */ 12964 12965 #if defined(BCM_56340_A0) 12966 { /* SOC_FORMAT_INT_CPU_COS_MAP_KEY_BCM56340_A0fmt */ 12967 /* format CPU_COS_MAP_KEYfmt */ 12968 /* nFields */ 5, 12969 /* *fields */ soc_CPU_COS_MAP_KEY_BCM56640_A0fmt_fields, 12970 /* bits */ 112, 12971 /* flags */ 0, 12972 }, 12973 #endif /* chips */ 12974 12975 #if defined(BCM_56370_A0) 12976 { /* SOC_FORMAT_INT_CPU_COS_MAP_KEY_BCM56370_A0fmt */ 12977 /* format CPU_COS_MAP_KEYfmt */ 12978 /* nFields */ 5, 12979 /* *fields */ soc_CPU_COS_MAP_KEY_BCM56870_A0fmt_fields, 12980 /* bits */ 144, 12981 /* flags */ 0, 12982 }, 12983 #endif /* chips */ 12984 12985 #if defined(BCM_56440_A0) 12986 { /* SOC_FORMAT_INT_CPU_COS_MAP_KEY_BCM56440_A0fmt */ 12987 /* format CPU_COS_MAP_KEYfmt */ 12988 /* nFields */ 63, 12989 /* *fields */ soc_CPU_COS_MAP_KEY_BCM56440_A0fmt_fields, 12990 /* bits */ 69, 12991 /* flags */ 0, 12992 }, 12993 #endif /* chips */ 12994 12995 #if defined(BCM_56440_B0) 12996 { /* SOC_FORMAT_INT_CPU_COS_MAP_KEY_BCM56440_B0fmt */ 12997 /* format CPU_COS_MAP_KEYfmt */ 12998 /* nFields */ 63, 12999 /* *fields */ soc_CPU_COS_MAP_KEY_BCM56440_A0fmt_fields, 13000 /* bits */ 69, 13001 /* flags */ 0, 13002 }, 13003 #endif /* chips */ 13004 13005 #if defined(BCM_56450_A0) 13006 { /* SOC_FORMAT_INT_CPU_COS_MAP_KEY_BCM56450_A0fmt */ 13007 /* format CPU_COS_MAP_KEYfmt */ 13008 /* nFields */ 5, 13009 /* *fields */ soc_CPU_COS_MAP_KEY_BCM56450_A0fmt_fields, 13010 /* bits */ 81, 13011 /* flags */ 0, 13012 }, 13013 #endif /* chips */ 13014 13015 #if defined(BCM_56450_B0) 13016 { /* SOC_FORMAT_INT_CPU_COS_MAP_KEY_BCM56450_B0fmt */ 13017 /* format CPU_COS_MAP_KEYfmt */ 13018 /* nFields */ 5, 13019 /* *fields */ soc_CPU_COS_MAP_KEY_BCM56450_A0fmt_fields, 13020 /* bits */ 81, 13021 /* flags */ 0, 13022 }, 13023 #endif /* chips */ 13024 13025 #if defined(BCM_56450_B1) 13026 { /* SOC_FORMAT_INT_CPU_COS_MAP_KEY_BCM56450_B1fmt */ 13027 /* format CPU_COS_MAP_KEYfmt */ 13028 /* nFields */ 5, 13029 /* *fields */ soc_CPU_COS_MAP_KEY_BCM56450_A0fmt_fields, 13030 /* bits */ 81, 13031 /* flags */ 0, 13032 }, 13033 #endif /* chips */ 13034 13035 #if defined(BCM_56524_A0) 13036 { /* SOC_FORMAT_INT_CPU_COS_MAP_KEY_BCM56524_A0fmt */ 13037 /* format CPU_COS_MAP_KEYfmt */ 13038 /* nFields */ 63, 13039 /* *fields */ soc_CPU_COS_MAP_KEY_BCM56634_A0fmt_fields, 13040 /* bits */ 67, 13041 /* flags */ 0, 13042 }, 13043 #endif /* chips */ 13044 13045 #if defined(BCM_56524_B0) 13046 { /* SOC_FORMAT_INT_CPU_COS_MAP_KEY_BCM56524_B0fmt */ 13047 /* format CPU_COS_MAP_KEYfmt */ 13048 /* nFields */ 63, 13049 /* *fields */ soc_CPU_COS_MAP_KEY_BCM56634_A0fmt_fields, 13050 /* bits */ 67, 13051 /* flags */ 0, 13052 }, 13053 #endif /* chips */ 13054 13055 #if defined(BCM_56560_A0) 13056 { /* SOC_FORMAT_INT_CPU_COS_MAP_KEY_BCM56560_A0fmt */ 13057 /* format CPU_COS_MAP_KEYfmt */ 13058 /* nFields */ 6, 13059 /* *fields */ soc_CPU_COS_MAP_KEY_BCM56560_A0fmt_fields, 13060 /* bits */ 144, 13061 /* flags */ 0, 13062 }, 13063 #endif /* chips */ 13064 13065 #if defined(BCM_56560_B0) 13066 { /* SOC_FORMAT_INT_CPU_COS_MAP_KEY_BCM56560_B0fmt */ 13067 /* format CPU_COS_MAP_KEYfmt */ 13068 /* nFields */ 6, 13069 /* *fields */ soc_CPU_COS_MAP_KEY_BCM56560_A0fmt_fields, 13070 /* bits */ 144, 13071 /* flags */ 0, 13072 }, 13073 #endif /* chips */ 13074 13075 #if defined(BCM_56624_B0) 13076 { /* SOC_FORMAT_INT_CPU_COS_MAP_KEY_BCM56624_B0fmt */ 13077 /* format CPU_COS_MAP_KEYfmt */ 13078 /* nFields */ 49, 13079 /* *fields */ soc_CPU_COS_MAP_KEY_BCM56624_B0fmt_fields, 13080 /* bits */ 67, 13081 /* flags */ 0, 13082 }, 13083 #endif /* chips */ 13084 13085 #if defined(BCM_56634_A0) 13086 { /* SOC_FORMAT_INT_CPU_COS_MAP_KEY_BCM56634_A0fmt */ 13087 /* format CPU_COS_MAP_KEYfmt */ 13088 /* nFields */ 63, 13089 /* *fields */ soc_CPU_COS_MAP_KEY_BCM56634_A0fmt_fields, 13090 /* bits */ 67, 13091 /* flags */ 0, 13092 }, 13093 #endif /* chips */ 13094 13095 #if defined(BCM_56634_B0) 13096 { /* SOC_FORMAT_INT_CPU_COS_MAP_KEY_BCM56634_B0fmt */ 13097 /* format CPU_COS_MAP_KEYfmt */ 13098 /* nFields */ 63, 13099 /* *fields */ soc_CPU_COS_MAP_KEY_BCM56634_A0fmt_fields, 13100 /* bits */ 67, 13101 /* flags */ 0, 13102 }, 13103 #endif /* chips */ 13104 13105 #if defined(BCM_56640_A0) 13106 { /* SOC_FORMAT_INT_CPU_COS_MAP_KEY_BCM56640_A0fmt */ 13107 /* format CPU_COS_MAP_KEYfmt */ 13108 /* nFields */ 5, 13109 /* *fields */ soc_CPU_COS_MAP_KEY_BCM56640_A0fmt_fields, 13110 /* bits */ 112, 13111 /* flags */ 0, 13112 }, 13113 #endif /* chips */ 13114 13115 #if defined(BCM_56670_A0) 13116 { /* SOC_FORMAT_INT_CPU_COS_MAP_KEY_BCM56670_A0fmt */ 13117 /* format CPU_COS_MAP_KEYfmt */ 13118 /* nFields */ 6, 13119 /* *fields */ soc_CPU_COS_MAP_KEY_BCM56560_A0fmt_fields, 13120 /* bits */ 144, 13121 /* flags */ 0, 13122 }, 13123 #endif /* chips */ 13124 13125 #if defined(BCM_56670_B0) 13126 { /* SOC_FORMAT_INT_CPU_COS_MAP_KEY_BCM56670_B0fmt */ 13127 /* format CPU_COS_MAP_KEYfmt */ 13128 /* nFields */ 6, 13129 /* *fields */ soc_CPU_COS_MAP_KEY_BCM56560_A0fmt_fields, 13130 /* bits */ 144, 13131 /* flags */ 0, 13132 }, 13133 #endif /* chips */ 13134 13135 #if defined(BCM_56680_A0) 13136 { /* SOC_FORMAT_INT_CPU_COS_MAP_KEY_BCM56680_A0fmt */ 13137 /* format CPU_COS_MAP_KEYfmt */ 13138 /* nFields */ 48, 13139 /* *fields */ soc_CPU_COS_MAP_KEYfmt_fields, 13140 /* bits */ 67, 13141 /* flags */ 0, 13142 }, 13143 #endif /* chips */ 13144 13145 #if defined(BCM_56680_B0) 13146 { /* SOC_FORMAT_INT_CPU_COS_MAP_KEY_BCM56680_B0fmt */ 13147 /* format CPU_COS_MAP_KEYfmt */ 13148 /* nFields */ 49, 13149 /* *fields */ soc_CPU_COS_MAP_KEY_BCM56624_B0fmt_fields, 13150 /* bits */ 67, 13151 /* flags */ 0, 13152 }, 13153 #endif /* chips */ 13154 13155 #if defined(BCM_56685_A0) 13156 { /* SOC_FORMAT_INT_CPU_COS_MAP_KEY_BCM56685_A0fmt */ 13157 /* format CPU_COS_MAP_KEYfmt */ 13158 /* nFields */ 63, 13159 /* *fields */ soc_CPU_COS_MAP_KEY_BCM56634_A0fmt_fields, 13160 /* bits */ 67, 13161 /* flags */ 0, 13162 }, 13163 #endif /* chips */ 13164 13165 #if defined(BCM_56685_B0) 13166 { /* SOC_FORMAT_INT_CPU_COS_MAP_KEY_BCM56685_B0fmt */ 13167 /* format CPU_COS_MAP_KEYfmt */ 13168 /* nFields */ 63, 13169 /* *fields */ soc_CPU_COS_MAP_KEY_BCM56634_A0fmt_fields, 13170 /* bits */ 67, 13171 /* flags */ 0, 13172 }, 13173 #endif /* chips */ 13174 13175 #if defined(BCM_56725_A0) 13176 { /* SOC_FORMAT_INT_CPU_COS_MAP_KEY_BCM56725_A0fmt */ 13177 /* format CPU_COS_MAP_KEYfmt */ 13178 /* nFields */ 43, 13179 /* *fields */ soc_CPU_COS_MAP_KEY_BCM56820_A0fmt_fields, 13180 /* bits */ 67, 13181 /* flags */ 0, 13182 }, 13183 #endif /* chips */ 13184 13185 #if defined(BCM_56770_A0) 13186 { /* SOC_FORMAT_INT_CPU_COS_MAP_KEY_BCM56770_A0fmt */ 13187 /* format CPU_COS_MAP_KEYfmt */ 13188 /* nFields */ 5, 13189 /* *fields */ soc_CPU_COS_MAP_KEY_BCM56870_A0fmt_fields, 13190 /* bits */ 144, 13191 /* flags */ 0, 13192 }, 13193 #endif /* chips */ 13194 13195 #if defined(BCM_56820_A0) 13196 { /* SOC_FORMAT_INT_CPU_COS_MAP_KEY_BCM56820_A0fmt */ 13197 /* format CPU_COS_MAP_KEYfmt */ 13198 /* nFields */ 43, 13199 /* *fields */ soc_CPU_COS_MAP_KEY_BCM56820_A0fmt_fields, 13200 /* bits */ 67, 13201 /* flags */ 0, 13202 }, 13203 #endif /* chips */ 13204 13205 #if defined(BCM_56840_A0) 13206 { /* SOC_FORMAT_INT_CPU_COS_MAP_KEY_BCM56840_A0fmt */ 13207 /* format CPU_COS_MAP_KEYfmt */ 13208 /* nFields */ 57, 13209 /* *fields */ soc_CPU_COS_MAP_KEY_BCM56840_A0fmt_fields, 13210 /* bits */ 67, 13211 /* flags */ 0, 13212 }, 13213 #endif /* chips */ 13214 13215 #if defined(BCM_56840_B0) 13216 { /* SOC_FORMAT_INT_CPU_COS_MAP_KEY_BCM56840_B0fmt */ 13217 /* format CPU_COS_MAP_KEYfmt */ 13218 /* nFields */ 57, 13219 /* *fields */ soc_CPU_COS_MAP_KEY_BCM56840_A0fmt_fields, 13220 /* bits */ 67, 13221 /* flags */ 0, 13222 }, 13223 #endif /* chips */ 13224 13225 #if defined(BCM_56850_A0) 13226 { /* SOC_FORMAT_INT_CPU_COS_MAP_KEY_BCM56850_A0fmt */ 13227 /* format CPU_COS_MAP_KEYfmt */ 13228 /* nFields */ 75, 13229 /* *fields */ soc_CPU_COS_MAP_KEY_BCM56850_A0fmt_fields, 13230 /* bits */ 140, 13231 /* flags */ 0, 13232 }, 13233 #endif /* chips */ 13234 13235 #if defined(BCM_56860_A0) 13236 { /* SOC_FORMAT_INT_CPU_COS_MAP_KEY_BCM56860_A0fmt */ 13237 /* format CPU_COS_MAP_KEYfmt */ 13238 /* nFields */ 6, 13239 /* *fields */ soc_CPU_COS_MAP_KEY_BCM56860_A0fmt_fields, 13240 /* bits */ 144, 13241 /* flags */ 0, 13242 }, 13243 #endif /* chips */ 13244 13245 #if defined(BCM_56870_A0) 13246 { /* SOC_FORMAT_INT_CPU_COS_MAP_KEY_BCM56870_A0fmt */ 13247 /* format CPU_COS_MAP_KEYfmt */ 13248 /* nFields */ 5, 13249 /* *fields */ soc_CPU_COS_MAP_KEY_BCM56870_A0fmt_fields, 13250 /* bits */ 144, 13251 /* flags */ 0, 13252 }, 13253 #endif /* chips */ 13254 13255 #if defined(BCM_56960_A0) 13256 { /* SOC_FORMAT_INT_CPU_COS_MAP_KEY_BCM56960_A0fmt */ 13257 /* format CPU_COS_MAP_KEYfmt */ 13258 /* nFields */ 79, 13259 /* *fields */ soc_CPU_COS_MAP_KEY_BCM56960_A0fmt_fields, 13260 /* bits */ 140, 13261 /* flags */ 0, 13262 }, 13263 #endif /* chips */ 13264 13265 #if defined(BCM_56965_A0) 13266 { /* SOC_FORMAT_INT_CPU_COS_MAP_KEY_BCM56965_A0fmt */ 13267 /* format CPU_COS_MAP_KEYfmt */ 13268 /* nFields */ 79, 13269 /* *fields */ soc_CPU_COS_MAP_KEY_BCM56960_A0fmt_fields, 13270 /* bits */ 140, 13271 /* flags */ 0, 13272 }, 13273 #endif /* chips */ 13274 13275 #if defined(BCM_56970_A0) 13276 { /* SOC_FORMAT_INT_CPU_COS_MAP_KEY_BCM56970_A0fmt */ 13277 /* format CPU_COS_MAP_KEYfmt */ 13278 /* nFields */ 79, 13279 /* *fields */ soc_CPU_COS_MAP_KEY_BCM56970_A0fmt_fields, 13280 /* bits */ 144, 13281 /* flags */ 0, 13282 }, 13283 #endif /* chips */ 13284 13285 #if defined(BCM_56980_A0) 13286 { /* SOC_FORMAT_INT_CPU_COS_MAP_KEY_BCM56980_A0fmt */ 13287 /* format CPU_COS_MAP_KEYfmt */ 13288 /* nFields */ 5, 13289 /* *fields */ soc_CPU_COS_MAP_KEY_BCM56980_A0fmt_fields, 13290 /* bits */ 100, 13291 /* flags */ 0, 13292 }, 13293 #endif /* chips */ 13294 13295 #if defined(BCM_56980_B0) 13296 { /* SOC_FORMAT_INT_CPU_COS_MAP_KEY_BCM56980_B0fmt */ 13297 /* format CPU_COS_MAP_KEYfmt */ 13298 /* nFields */ 5, 13299 /* *fields */ soc_CPU_COS_MAP_KEY_BCM56980_A0fmt_fields, 13300 /* bits */ 100, 13301 /* flags */ 0, 13302 }, 13303 #endif /* chips */ 13304 13305 #if defined(BCM_56980_A0) || defined(BCM_56980_B0) 13306 { /* SOC_FORMAT_INT_CPU_COS_MAP_TCAM_FORMATfmt */ 13307 /* format CPU_COS_MAP_TCAM_FORMATfmt */ 13308 /* nFields */ 5, 13309 /* *fields */ soc_CPU_COS_MAP_TCAM_FORMATfmt_fields, 13310 /* bits */ 209, 13311 /* flags */ 0, 13312 }, 13313 #endif /* chips */ 13314 13315 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 13316 defined(BCM_56870_A0) 13317 { /* SOC_FORMAT_INT_CPU_COS_MAP_VAL_PROBES_DOPfmt */ 13318 /* format CPU_COS_MAP_VAL_PROBES_DOPfmt */ 13319 /* nFields */ 4, 13320 /* *fields */ soc_CPU_COS_MAP_VAL_PROBES_DOPfmt_fields, 13321 /* bits */ 32, 13322 /* flags */ 0, 13323 }, 13324 #endif /* chips */ 13325 13326 #if defined(BCM_56504_A0) 13327 { /* SOC_FORMAT_INT_CPU_OPCODESfmt */ 13328 /* format CPU_OPCODESfmt */ 13329 /* nFields */ 21, 13330 /* *fields */ soc_CPU_OPCODESfmt_fields, 13331 /* bits */ 21, 13332 /* flags */ 0, 13333 }, 13334 #endif /* chips */ 13335 13336 #if defined(BCM_53314_A0) 13337 { /* SOC_FORMAT_INT_CPU_OPCODES_BCM53314_A0fmt */ 13338 /* format CPU_OPCODESfmt */ 13339 /* nFields */ 28, 13340 /* *fields */ soc_CPU_OPCODES_BCM53314_A0fmt_fields, 13341 /* bits */ 28, 13342 /* flags */ 0, 13343 }, 13344 #endif /* chips */ 13345 13346 #if defined(BCM_53324_A0) 13347 { /* SOC_FORMAT_INT_CPU_OPCODES_BCM53324_A0fmt */ 13348 /* format CPU_OPCODESfmt */ 13349 /* nFields */ 28, 13350 /* *fields */ soc_CPU_OPCODES_BCM53314_A0fmt_fields, 13351 /* bits */ 28, 13352 /* flags */ 0, 13353 }, 13354 #endif /* chips */ 13355 13356 #if defined(BCM_53400_A0) 13357 { /* SOC_FORMAT_INT_CPU_OPCODES_BCM53400_A0fmt */ 13358 /* format CPU_OPCODESfmt */ 13359 /* nFields */ 43, 13360 /* *fields */ soc_CPU_OPCODES_BCM53400_A0fmt_fields, 13361 /* bits */ 45, 13362 /* flags */ 0, 13363 }, 13364 #endif /* chips */ 13365 13366 #if defined(BCM_53540_A0) 13367 { /* SOC_FORMAT_INT_CPU_OPCODES_BCM53540_A0fmt */ 13368 /* format CPU_OPCODESfmt */ 13369 /* nFields */ 43, 13370 /* *fields */ soc_CPU_OPCODES_BCM53400_A0fmt_fields, 13371 /* bits */ 45, 13372 /* flags */ 0, 13373 }, 13374 #endif /* chips */ 13375 13376 #if defined(BCM_53570_A0) 13377 { /* SOC_FORMAT_INT_CPU_OPCODES_BCM53570_A0fmt */ 13378 /* format CPU_OPCODESfmt */ 13379 /* nFields */ 48, 13380 /* *fields */ soc_CPU_OPCODES_BCM53570_A0fmt_fields, 13381 /* bits */ 54, 13382 /* flags */ 0, 13383 }, 13384 #endif /* chips */ 13385 13386 #if defined(BCM_53570_B0) 13387 { /* SOC_FORMAT_INT_CPU_OPCODES_BCM53570_B0fmt */ 13388 /* format CPU_OPCODESfmt */ 13389 /* nFields */ 48, 13390 /* *fields */ soc_CPU_OPCODES_BCM53570_A0fmt_fields, 13391 /* bits */ 54, 13392 /* flags */ 0, 13393 }, 13394 #endif /* chips */ 13395 13396 #if defined(BCM_56142_A0) 13397 { /* SOC_FORMAT_INT_CPU_OPCODES_BCM56142_A0fmt */ 13398 /* format CPU_OPCODESfmt */ 13399 /* nFields */ 40, 13400 /* *fields */ soc_CPU_OPCODES_BCM56334_A0fmt_fields, 13401 /* bits */ 40, 13402 /* flags */ 0, 13403 }, 13404 #endif /* chips */ 13405 13406 #if defined(BCM_56150_A0) 13407 { /* SOC_FORMAT_INT_CPU_OPCODES_BCM56150_A0fmt */ 13408 /* format CPU_OPCODESfmt */ 13409 /* nFields */ 42, 13410 /* *fields */ soc_CPU_OPCODES_BCM56150_A0fmt_fields, 13411 /* bits */ 42, 13412 /* flags */ 0, 13413 }, 13414 #endif /* chips */ 13415 13416 #if defined(BCM_56160_A0) 13417 { /* SOC_FORMAT_INT_CPU_OPCODES_BCM56160_A0fmt */ 13418 /* format CPU_OPCODESfmt */ 13419 /* nFields */ 43, 13420 /* *fields */ soc_CPU_OPCODES_BCM53400_A0fmt_fields, 13421 /* bits */ 45, 13422 /* flags */ 0, 13423 }, 13424 #endif /* chips */ 13425 13426 #if defined(BCM_56224_A0) 13427 { /* SOC_FORMAT_INT_CPU_OPCODES_BCM56224_A0fmt */ 13428 /* format CPU_OPCODESfmt */ 13429 /* nFields */ 26, 13430 /* *fields */ soc_CPU_OPCODES_BCM56224_A0fmt_fields, 13431 /* bits */ 26, 13432 /* flags */ 0, 13433 }, 13434 #endif /* chips */ 13435 13436 #if defined(BCM_56224_B0) 13437 { /* SOC_FORMAT_INT_CPU_OPCODES_BCM56224_B0fmt */ 13438 /* format CPU_OPCODESfmt */ 13439 /* nFields */ 26, 13440 /* *fields */ soc_CPU_OPCODES_BCM56224_A0fmt_fields, 13441 /* bits */ 26, 13442 /* flags */ 0, 13443 }, 13444 #endif /* chips */ 13445 13446 #if defined(BCM_56260_A0) 13447 { /* SOC_FORMAT_INT_CPU_OPCODES_BCM56260_A0fmt */ 13448 /* format CPU_OPCODESfmt */ 13449 /* nFields */ 46, 13450 /* *fields */ soc_CPU_OPCODES_BCM56260_A0fmt_fields, 13451 /* bits */ 50, 13452 /* flags */ 0, 13453 }, 13454 #endif /* chips */ 13455 13456 #if defined(BCM_56260_B0) 13457 { /* SOC_FORMAT_INT_CPU_OPCODES_BCM56260_B0fmt */ 13458 /* format CPU_OPCODESfmt */ 13459 /* nFields */ 46, 13460 /* *fields */ soc_CPU_OPCODES_BCM56260_A0fmt_fields, 13461 /* bits */ 50, 13462 /* flags */ 0, 13463 }, 13464 #endif /* chips */ 13465 13466 #if defined(BCM_56270_A0) 13467 { /* SOC_FORMAT_INT_CPU_OPCODES_BCM56270_A0fmt */ 13468 /* format CPU_OPCODESfmt */ 13469 /* nFields */ 46, 13470 /* *fields */ soc_CPU_OPCODES_BCM56260_A0fmt_fields, 13471 /* bits */ 50, 13472 /* flags */ 0, 13473 }, 13474 #endif /* chips */ 13475 13476 #if defined(BCM_56314_A0) 13477 { /* SOC_FORMAT_INT_CPU_OPCODES_BCM56314_A0fmt */ 13478 /* format CPU_OPCODESfmt */ 13479 /* nFields */ 23, 13480 /* *fields */ soc_CPU_OPCODES_BCM56504_B0fmt_fields, 13481 /* bits */ 23, 13482 /* flags */ 0, 13483 }, 13484 #endif /* chips */ 13485 13486 #if defined(BCM_56334_A0) 13487 { /* SOC_FORMAT_INT_CPU_OPCODES_BCM56334_A0fmt */ 13488 /* format CPU_OPCODESfmt */ 13489 /* nFields */ 40, 13490 /* *fields */ soc_CPU_OPCODES_BCM56334_A0fmt_fields, 13491 /* bits */ 40, 13492 /* flags */ 0, 13493 }, 13494 #endif /* chips */ 13495 13496 #if defined(BCM_56334_B0) 13497 { /* SOC_FORMAT_INT_CPU_OPCODES_BCM56334_B0fmt */ 13498 /* format CPU_OPCODESfmt */ 13499 /* nFields */ 40, 13500 /* *fields */ soc_CPU_OPCODES_BCM56334_A0fmt_fields, 13501 /* bits */ 40, 13502 /* flags */ 0, 13503 }, 13504 #endif /* chips */ 13505 13506 #if defined(BCM_56340_A0) 13507 { /* SOC_FORMAT_INT_CPU_OPCODES_BCM56340_A0fmt */ 13508 /* format CPU_OPCODESfmt */ 13509 /* nFields */ 54, 13510 /* *fields */ soc_CPU_OPCODES_BCM56640_A0fmt_fields, 13511 /* bits */ 63, 13512 /* flags */ 0, 13513 }, 13514 #endif /* chips */ 13515 13516 #if defined(BCM_56370_A0) 13517 { /* SOC_FORMAT_INT_CPU_OPCODES_BCM56370_A0fmt */ 13518 /* format CPU_OPCODESfmt */ 13519 /* nFields */ 63, 13520 /* *fields */ soc_CPU_OPCODES_BCM56370_A0fmt_fields, 13521 /* bits */ 64, 13522 /* flags */ 0, 13523 }, 13524 #endif /* chips */ 13525 13526 #if defined(BCM_56440_A0) 13527 { /* SOC_FORMAT_INT_CPU_OPCODES_BCM56440_A0fmt */ 13528 /* format CPU_OPCODESfmt */ 13529 /* nFields */ 46, 13530 /* *fields */ soc_CPU_OPCODES_BCM56440_A0fmt_fields, 13531 /* bits */ 48, 13532 /* flags */ 0, 13533 }, 13534 #endif /* chips */ 13535 13536 #if defined(BCM_56440_B0) 13537 { /* SOC_FORMAT_INT_CPU_OPCODES_BCM56440_B0fmt */ 13538 /* format CPU_OPCODESfmt */ 13539 /* nFields */ 46, 13540 /* *fields */ soc_CPU_OPCODES_BCM56440_A0fmt_fields, 13541 /* bits */ 48, 13542 /* flags */ 0, 13543 }, 13544 #endif /* chips */ 13545 13546 #if defined(BCM_56450_A0) 13547 { /* SOC_FORMAT_INT_CPU_OPCODES_BCM56450_A0fmt */ 13548 /* format CPU_OPCODESfmt */ 13549 /* nFields */ 46, 13550 /* *fields */ soc_CPU_OPCODES_BCM56450_A0fmt_fields, 13551 /* bits */ 50, 13552 /* flags */ 0, 13553 }, 13554 #endif /* chips */ 13555 13556 #if defined(BCM_56450_B0) 13557 { /* SOC_FORMAT_INT_CPU_OPCODES_BCM56450_B0fmt */ 13558 /* format CPU_OPCODESfmt */ 13559 /* nFields */ 46, 13560 /* *fields */ soc_CPU_OPCODES_BCM56450_A0fmt_fields, 13561 /* bits */ 50, 13562 /* flags */ 0, 13563 }, 13564 #endif /* chips */ 13565 13566 #if defined(BCM_56450_B1) 13567 { /* SOC_FORMAT_INT_CPU_OPCODES_BCM56450_B1fmt */ 13568 /* format CPU_OPCODESfmt */ 13569 /* nFields */ 46, 13570 /* *fields */ soc_CPU_OPCODES_BCM56450_A0fmt_fields, 13571 /* bits */ 50, 13572 /* flags */ 0, 13573 }, 13574 #endif /* chips */ 13575 13576 #if defined(BCM_56504_B0) 13577 { /* SOC_FORMAT_INT_CPU_OPCODES_BCM56504_B0fmt */ 13578 /* format CPU_OPCODESfmt */ 13579 /* nFields */ 23, 13580 /* *fields */ soc_CPU_OPCODES_BCM56504_B0fmt_fields, 13581 /* bits */ 23, 13582 /* flags */ 0, 13583 }, 13584 #endif /* chips */ 13585 13586 #if defined(BCM_56514_A0) 13587 { /* SOC_FORMAT_INT_CPU_OPCODES_BCM56514_A0fmt */ 13588 /* format CPU_OPCODESfmt */ 13589 /* nFields */ 25, 13590 /* *fields */ soc_CPU_OPCODES_BCM56514_A0fmt_fields, 13591 /* bits */ 25, 13592 /* flags */ 0, 13593 }, 13594 #endif /* chips */ 13595 13596 #if defined(BCM_56524_A0) 13597 { /* SOC_FORMAT_INT_CPU_OPCODES_BCM56524_A0fmt */ 13598 /* format CPU_OPCODESfmt */ 13599 /* nFields */ 45, 13600 /* *fields */ soc_CPU_OPCODES_BCM56634_A0fmt_fields, 13601 /* bits */ 45, 13602 /* flags */ 0, 13603 }, 13604 #endif /* chips */ 13605 13606 #if defined(BCM_56524_B0) 13607 { /* SOC_FORMAT_INT_CPU_OPCODES_BCM56524_B0fmt */ 13608 /* format CPU_OPCODESfmt */ 13609 /* nFields */ 45, 13610 /* *fields */ soc_CPU_OPCODES_BCM56634_A0fmt_fields, 13611 /* bits */ 45, 13612 /* flags */ 0, 13613 }, 13614 #endif /* chips */ 13615 13616 #if defined(BCM_56560_A0) 13617 { /* SOC_FORMAT_INT_CPU_OPCODES_BCM56560_A0fmt */ 13618 /* format CPU_OPCODESfmt */ 13619 /* nFields */ 59, 13620 /* *fields */ soc_CPU_OPCODES_BCM56560_A0fmt_fields, 13621 /* bits */ 64, 13622 /* flags */ 0, 13623 }, 13624 #endif /* chips */ 13625 13626 #if defined(BCM_56560_B0) 13627 { /* SOC_FORMAT_INT_CPU_OPCODES_BCM56560_B0fmt */ 13628 /* format CPU_OPCODESfmt */ 13629 /* nFields */ 59, 13630 /* *fields */ soc_CPU_OPCODES_BCM56560_A0fmt_fields, 13631 /* bits */ 64, 13632 /* flags */ 0, 13633 }, 13634 #endif /* chips */ 13635 13636 #if defined(BCM_56624_A0) 13637 { /* SOC_FORMAT_INT_CPU_OPCODES_BCM56624_A0fmt */ 13638 /* format CPU_OPCODESfmt */ 13639 /* nFields */ 35, 13640 /* *fields */ soc_CPU_OPCODES_BCM56624_A0fmt_fields, 13641 /* bits */ 35, 13642 /* flags */ 0, 13643 }, 13644 #endif /* chips */ 13645 13646 #if defined(BCM_56624_B0) 13647 { /* SOC_FORMAT_INT_CPU_OPCODES_BCM56624_B0fmt */ 13648 /* format CPU_OPCODESfmt */ 13649 /* nFields */ 36, 13650 /* *fields */ soc_CPU_OPCODES_BCM56624_B0fmt_fields, 13651 /* bits */ 36, 13652 /* flags */ 0, 13653 }, 13654 #endif /* chips */ 13655 13656 #if defined(BCM_56634_A0) 13657 { /* SOC_FORMAT_INT_CPU_OPCODES_BCM56634_A0fmt */ 13658 /* format CPU_OPCODESfmt */ 13659 /* nFields */ 45, 13660 /* *fields */ soc_CPU_OPCODES_BCM56634_A0fmt_fields, 13661 /* bits */ 45, 13662 /* flags */ 0, 13663 }, 13664 #endif /* chips */ 13665 13666 #if defined(BCM_56634_B0) 13667 { /* SOC_FORMAT_INT_CPU_OPCODES_BCM56634_B0fmt */ 13668 /* format CPU_OPCODESfmt */ 13669 /* nFields */ 45, 13670 /* *fields */ soc_CPU_OPCODES_BCM56634_A0fmt_fields, 13671 /* bits */ 45, 13672 /* flags */ 0, 13673 }, 13674 #endif /* chips */ 13675 13676 #if defined(BCM_56640_A0) 13677 { /* SOC_FORMAT_INT_CPU_OPCODES_BCM56640_A0fmt */ 13678 /* format CPU_OPCODESfmt */ 13679 /* nFields */ 54, 13680 /* *fields */ soc_CPU_OPCODES_BCM56640_A0fmt_fields, 13681 /* bits */ 63, 13682 /* flags */ 0, 13683 }, 13684 #endif /* chips */ 13685 13686 #if defined(BCM_56670_A0) 13687 { /* SOC_FORMAT_INT_CPU_OPCODES_BCM56670_A0fmt */ 13688 /* format CPU_OPCODESfmt */ 13689 /* nFields */ 59, 13690 /* *fields */ soc_CPU_OPCODES_BCM56560_A0fmt_fields, 13691 /* bits */ 64, 13692 /* flags */ 0, 13693 }, 13694 #endif /* chips */ 13695 13696 #if defined(BCM_56670_B0) 13697 { /* SOC_FORMAT_INT_CPU_OPCODES_BCM56670_B0fmt */ 13698 /* format CPU_OPCODESfmt */ 13699 /* nFields */ 59, 13700 /* *fields */ soc_CPU_OPCODES_BCM56560_A0fmt_fields, 13701 /* bits */ 64, 13702 /* flags */ 0, 13703 }, 13704 #endif /* chips */ 13705 13706 #if defined(BCM_56680_A0) 13707 { /* SOC_FORMAT_INT_CPU_OPCODES_BCM56680_A0fmt */ 13708 /* format CPU_OPCODESfmt */ 13709 /* nFields */ 35, 13710 /* *fields */ soc_CPU_OPCODES_BCM56624_A0fmt_fields, 13711 /* bits */ 35, 13712 /* flags */ 0, 13713 }, 13714 #endif /* chips */ 13715 13716 #if defined(BCM_56680_B0) 13717 { /* SOC_FORMAT_INT_CPU_OPCODES_BCM56680_B0fmt */ 13718 /* format CPU_OPCODESfmt */ 13719 /* nFields */ 36, 13720 /* *fields */ soc_CPU_OPCODES_BCM56624_B0fmt_fields, 13721 /* bits */ 36, 13722 /* flags */ 0, 13723 }, 13724 #endif /* chips */ 13725 13726 #if defined(BCM_56685_A0) 13727 { /* SOC_FORMAT_INT_CPU_OPCODES_BCM56685_A0fmt */ 13728 /* format CPU_OPCODESfmt */ 13729 /* nFields */ 45, 13730 /* *fields */ soc_CPU_OPCODES_BCM56634_A0fmt_fields, 13731 /* bits */ 45, 13732 /* flags */ 0, 13733 }, 13734 #endif /* chips */ 13735 13736 #if defined(BCM_56685_B0) 13737 { /* SOC_FORMAT_INT_CPU_OPCODES_BCM56685_B0fmt */ 13738 /* format CPU_OPCODESfmt */ 13739 /* nFields */ 45, 13740 /* *fields */ soc_CPU_OPCODES_BCM56634_A0fmt_fields, 13741 /* bits */ 45, 13742 /* flags */ 0, 13743 }, 13744 #endif /* chips */ 13745 13746 #if defined(BCM_56725_A0) 13747 { /* SOC_FORMAT_INT_CPU_OPCODES_BCM56725_A0fmt */ 13748 /* format CPU_OPCODESfmt */ 13749 /* nFields */ 31, 13750 /* *fields */ soc_CPU_OPCODES_BCM56820_A0fmt_fields, 13751 /* bits */ 32, 13752 /* flags */ 0, 13753 }, 13754 #endif /* chips */ 13755 13756 #if defined(BCM_56770_A0) 13757 { /* SOC_FORMAT_INT_CPU_OPCODES_BCM56770_A0fmt */ 13758 /* format CPU_OPCODESfmt */ 13759 /* nFields */ 63, 13760 /* *fields */ soc_CPU_OPCODES_BCM56870_A0fmt_fields, 13761 /* bits */ 64, 13762 /* flags */ 0, 13763 }, 13764 #endif /* chips */ 13765 13766 #if defined(BCM_56800_A0) 13767 { /* SOC_FORMAT_INT_CPU_OPCODES_BCM56800_A0fmt */ 13768 /* format CPU_OPCODESfmt */ 13769 /* nFields */ 25, 13770 /* *fields */ soc_CPU_OPCODES_BCM56800_A0fmt_fields, 13771 /* bits */ 25, 13772 /* flags */ 0, 13773 }, 13774 #endif /* chips */ 13775 13776 #if defined(BCM_56820_A0) 13777 { /* SOC_FORMAT_INT_CPU_OPCODES_BCM56820_A0fmt */ 13778 /* format CPU_OPCODESfmt */ 13779 /* nFields */ 31, 13780 /* *fields */ soc_CPU_OPCODES_BCM56820_A0fmt_fields, 13781 /* bits */ 32, 13782 /* flags */ 0, 13783 }, 13784 #endif /* chips */ 13785 13786 #if defined(BCM_56840_A0) 13787 { /* SOC_FORMAT_INT_CPU_OPCODES_BCM56840_A0fmt */ 13788 /* format CPU_OPCODESfmt */ 13789 /* nFields */ 43, 13790 /* *fields */ soc_CPU_OPCODES_BCM56840_A0fmt_fields, 13791 /* bits */ 47, 13792 /* flags */ 0, 13793 }, 13794 #endif /* chips */ 13795 13796 #if defined(BCM_56840_B0) 13797 { /* SOC_FORMAT_INT_CPU_OPCODES_BCM56840_B0fmt */ 13798 /* format CPU_OPCODESfmt */ 13799 /* nFields */ 43, 13800 /* *fields */ soc_CPU_OPCODES_BCM56840_A0fmt_fields, 13801 /* bits */ 47, 13802 /* flags */ 0, 13803 }, 13804 #endif /* chips */ 13805 13806 #if defined(BCM_56850_A0) 13807 { /* SOC_FORMAT_INT_CPU_OPCODES_BCM56850_A0fmt */ 13808 /* format CPU_OPCODESfmt */ 13809 /* nFields */ 58, 13810 /* *fields */ soc_CPU_OPCODES_BCM56850_A0fmt_fields, 13811 /* bits */ 64, 13812 /* flags */ 0, 13813 }, 13814 #endif /* chips */ 13815 13816 #if defined(BCM_56860_A0) 13817 { /* SOC_FORMAT_INT_CPU_OPCODES_BCM56860_A0fmt */ 13818 /* format CPU_OPCODESfmt */ 13819 /* nFields */ 58, 13820 /* *fields */ soc_CPU_OPCODES_BCM56860_A0fmt_fields, 13821 /* bits */ 64, 13822 /* flags */ 0, 13823 }, 13824 #endif /* chips */ 13825 13826 #if defined(BCM_56870_A0) 13827 { /* SOC_FORMAT_INT_CPU_OPCODES_BCM56870_A0fmt */ 13828 /* format CPU_OPCODESfmt */ 13829 /* nFields */ 63, 13830 /* *fields */ soc_CPU_OPCODES_BCM56870_A0fmt_fields, 13831 /* bits */ 64, 13832 /* flags */ 0, 13833 }, 13834 #endif /* chips */ 13835 13836 #if defined(BCM_56960_A0) 13837 { /* SOC_FORMAT_INT_CPU_OPCODES_BCM56960_A0fmt */ 13838 /* format CPU_OPCODESfmt */ 13839 /* nFields */ 58, 13840 /* *fields */ soc_CPU_OPCODES_BCM56960_A0fmt_fields, 13841 /* bits */ 64, 13842 /* flags */ 0, 13843 }, 13844 #endif /* chips */ 13845 13846 #if defined(BCM_56965_A0) 13847 { /* SOC_FORMAT_INT_CPU_OPCODES_BCM56965_A0fmt */ 13848 /* format CPU_OPCODESfmt */ 13849 /* nFields */ 58, 13850 /* *fields */ soc_CPU_OPCODES_BCM56960_A0fmt_fields, 13851 /* bits */ 64, 13852 /* flags */ 0, 13853 }, 13854 #endif /* chips */ 13855 13856 #if defined(BCM_56970_A0) 13857 { /* SOC_FORMAT_INT_CPU_OPCODES_BCM56970_A0fmt */ 13858 /* format CPU_OPCODESfmt */ 13859 /* nFields */ 58, 13860 /* *fields */ soc_CPU_OPCODES_BCM56960_A0fmt_fields, 13861 /* bits */ 64, 13862 /* flags */ 0, 13863 }, 13864 #endif /* chips */ 13865 13866 #if defined(BCM_56980_A0) 13867 { /* SOC_FORMAT_INT_CPU_OPCODES_BCM56980_A0fmt */ 13868 /* format CPU_OPCODESfmt */ 13869 /* nFields */ 39, 13870 /* *fields */ soc_CPU_OPCODES_BCM56980_A0fmt_fields, 13871 /* bits */ 42, 13872 /* flags */ 0, 13873 }, 13874 #endif /* chips */ 13875 13876 #if defined(BCM_56980_B0) 13877 { /* SOC_FORMAT_INT_CPU_OPCODES_BCM56980_B0fmt */ 13878 /* format CPU_OPCODESfmt */ 13879 /* nFields */ 39, 13880 /* *fields */ soc_CPU_OPCODES_BCM56980_A0fmt_fields, 13881 /* bits */ 42, 13882 /* flags */ 0, 13883 }, 13884 #endif /* chips */ 13885 13886 #if defined(BCM_88732_A0) 13887 { /* SOC_FORMAT_INT_CPU_OPCODES_BCM88732_A0fmt */ 13888 /* format CPU_OPCODESfmt */ 13889 /* nFields */ 11, 13890 /* *fields */ soc_CPU_OPCODES_BCM88732_A0fmt_fields, 13891 /* bits */ 16, 13892 /* flags */ 0, 13893 }, 13894 #endif /* chips */ 13895 13896 #if defined(BCM_56340_A0) || defined(BCM_56640_A0) 13897 { /* SOC_FORMAT_INT_CPU_OPCODES_OVERLAY_TYPE_0fmt */ 13898 /* format CPU_OPCODES_OVERLAY_TYPE_0fmt */ 13899 /* nFields */ 13, 13900 /* *fields */ soc_CPU_OPCODES_OVERLAY_TYPE_0fmt_fields, 13901 /* bits */ 13, 13902 /* flags */ 0, 13903 }, 13904 #endif /* chips */ 13905 13906 #if defined(BCM_56340_A0) || defined(BCM_56640_A0) 13907 { /* SOC_FORMAT_INT_CPU_OPCODES_OVERLAY_TYPE_1fmt */ 13908 /* format CPU_OPCODES_OVERLAY_TYPE_1fmt */ 13909 /* nFields */ 13, 13910 /* *fields */ soc_CPU_OPCODES_OVERLAY_TYPE_1fmt_fields, 13911 /* bits */ 13, 13912 /* flags */ 0, 13913 }, 13914 #endif /* chips */ 13915 13916 #if defined(BCM_56450_A0) || defined(BCM_56450_B0) || \ 13917 defined(BCM_56450_B1) 13918 { /* SOC_FORMAT_INT_CPU_OPCODES_OVERLAY_TYPE_3fmt */ 13919 /* format CPU_OPCODES_OVERLAY_TYPE_3fmt */ 13920 /* nFields */ 7, 13921 /* *fields */ soc_CPU_OPCODES_OVERLAY_TYPE_3fmt_fields, 13922 /* bits */ 8, 13923 /* flags */ 0, 13924 }, 13925 #endif /* chips */ 13926 13927 #if defined(BCM_56260_A0) 13928 { /* SOC_FORMAT_INT_CPU_OPCODES_OVERLAY_TYPE_0_BCM56260_A0fmt */ 13929 /* format CPU_OPCODES_OVERLAY_TYPE_0fmt */ 13930 /* nFields */ 8, 13931 /* *fields */ soc_CPU_OPCODES_OVERLAY_TYPE_0_BCM56260_A0fmt_fields, 13932 /* bits */ 8, 13933 /* flags */ 0, 13934 }, 13935 #endif /* chips */ 13936 13937 #if defined(BCM_56260_B0) 13938 { /* SOC_FORMAT_INT_CPU_OPCODES_OVERLAY_TYPE_0_BCM56260_B0fmt */ 13939 /* format CPU_OPCODES_OVERLAY_TYPE_0fmt */ 13940 /* nFields */ 8, 13941 /* *fields */ soc_CPU_OPCODES_OVERLAY_TYPE_0_BCM56260_A0fmt_fields, 13942 /* bits */ 8, 13943 /* flags */ 0, 13944 }, 13945 #endif /* chips */ 13946 13947 #if defined(BCM_56270_A0) 13948 { /* SOC_FORMAT_INT_CPU_OPCODES_OVERLAY_TYPE_0_BCM56270_A0fmt */ 13949 /* format CPU_OPCODES_OVERLAY_TYPE_0fmt */ 13950 /* nFields */ 8, 13951 /* *fields */ soc_CPU_OPCODES_OVERLAY_TYPE_0_BCM56260_A0fmt_fields, 13952 /* bits */ 8, 13953 /* flags */ 0, 13954 }, 13955 #endif /* chips */ 13956 13957 #if defined(BCM_56450_A0) 13958 { /* SOC_FORMAT_INT_CPU_OPCODES_OVERLAY_TYPE_0_BCM56450_A0fmt */ 13959 /* format CPU_OPCODES_OVERLAY_TYPE_0fmt */ 13960 /* nFields */ 8, 13961 /* *fields */ soc_CPU_OPCODES_OVERLAY_TYPE_0_BCM56450_A0fmt_fields, 13962 /* bits */ 8, 13963 /* flags */ 0, 13964 }, 13965 #endif /* chips */ 13966 13967 #if defined(BCM_56450_B0) 13968 { /* SOC_FORMAT_INT_CPU_OPCODES_OVERLAY_TYPE_0_BCM56450_B0fmt */ 13969 /* format CPU_OPCODES_OVERLAY_TYPE_0fmt */ 13970 /* nFields */ 8, 13971 /* *fields */ soc_CPU_OPCODES_OVERLAY_TYPE_0_BCM56450_A0fmt_fields, 13972 /* bits */ 8, 13973 /* flags */ 0, 13974 }, 13975 #endif /* chips */ 13976 13977 #if defined(BCM_56450_B1) 13978 { /* SOC_FORMAT_INT_CPU_OPCODES_OVERLAY_TYPE_0_BCM56450_B1fmt */ 13979 /* format CPU_OPCODES_OVERLAY_TYPE_0fmt */ 13980 /* nFields */ 8, 13981 /* *fields */ soc_CPU_OPCODES_OVERLAY_TYPE_0_BCM56450_A0fmt_fields, 13982 /* bits */ 8, 13983 /* flags */ 0, 13984 }, 13985 #endif /* chips */ 13986 13987 #if defined(BCM_56260_A0) 13988 { /* SOC_FORMAT_INT_CPU_OPCODES_OVERLAY_TYPE_1_BCM56260_A0fmt */ 13989 /* format CPU_OPCODES_OVERLAY_TYPE_1fmt */ 13990 /* nFields */ 11, 13991 /* *fields */ soc_CPU_OPCODES_OVERLAY_TYPE_1_BCM56260_A0fmt_fields, 13992 /* bits */ 8, 13993 /* flags */ 0, 13994 }, 13995 #endif /* chips */ 13996 13997 #if defined(BCM_56260_B0) 13998 { /* SOC_FORMAT_INT_CPU_OPCODES_OVERLAY_TYPE_1_BCM56260_B0fmt */ 13999 /* format CPU_OPCODES_OVERLAY_TYPE_1fmt */ 14000 /* nFields */ 11, 14001 /* *fields */ soc_CPU_OPCODES_OVERLAY_TYPE_1_BCM56260_A0fmt_fields, 14002 /* bits */ 8, 14003 /* flags */ 0, 14004 }, 14005 #endif /* chips */ 14006 14007 #if defined(BCM_56270_A0) 14008 { /* SOC_FORMAT_INT_CPU_OPCODES_OVERLAY_TYPE_1_BCM56270_A0fmt */ 14009 /* format CPU_OPCODES_OVERLAY_TYPE_1fmt */ 14010 /* nFields */ 11, 14011 /* *fields */ soc_CPU_OPCODES_OVERLAY_TYPE_1_BCM56260_A0fmt_fields, 14012 /* bits */ 8, 14013 /* flags */ 0, 14014 }, 14015 #endif /* chips */ 14016 14017 #if defined(BCM_56450_A0) 14018 { /* SOC_FORMAT_INT_CPU_OPCODES_OVERLAY_TYPE_1_BCM56450_A0fmt */ 14019 /* format CPU_OPCODES_OVERLAY_TYPE_1fmt */ 14020 /* nFields */ 6, 14021 /* *fields */ soc_CPU_OPCODES_OVERLAY_TYPE_1_BCM56450_A0fmt_fields, 14022 /* bits */ 8, 14023 /* flags */ 0, 14024 }, 14025 #endif /* chips */ 14026 14027 #if defined(BCM_56450_B0) 14028 { /* SOC_FORMAT_INT_CPU_OPCODES_OVERLAY_TYPE_1_BCM56450_B0fmt */ 14029 /* format CPU_OPCODES_OVERLAY_TYPE_1fmt */ 14030 /* nFields */ 6, 14031 /* *fields */ soc_CPU_OPCODES_OVERLAY_TYPE_1_BCM56450_A0fmt_fields, 14032 /* bits */ 8, 14033 /* flags */ 0, 14034 }, 14035 #endif /* chips */ 14036 14037 #if defined(BCM_56450_B1) 14038 { /* SOC_FORMAT_INT_CPU_OPCODES_OVERLAY_TYPE_1_BCM56450_B1fmt */ 14039 /* format CPU_OPCODES_OVERLAY_TYPE_1fmt */ 14040 /* nFields */ 6, 14041 /* *fields */ soc_CPU_OPCODES_OVERLAY_TYPE_1_BCM56450_A0fmt_fields, 14042 /* bits */ 8, 14043 /* flags */ 0, 14044 }, 14045 #endif /* chips */ 14046 14047 #if defined(BCM_56260_A0) 14048 { /* SOC_FORMAT_INT_CPU_OPCODES_OVERLAY_TYPE_3_BCM56260_A0fmt */ 14049 /* format CPU_OPCODES_OVERLAY_TYPE_3fmt */ 14050 /* nFields */ 7, 14051 /* *fields */ soc_CPU_OPCODES_OVERLAY_TYPE_3_BCM56260_A0fmt_fields, 14052 /* bits */ 8, 14053 /* flags */ 0, 14054 }, 14055 #endif /* chips */ 14056 14057 #if defined(BCM_56260_B0) 14058 { /* SOC_FORMAT_INT_CPU_OPCODES_OVERLAY_TYPE_3_BCM56260_B0fmt */ 14059 /* format CPU_OPCODES_OVERLAY_TYPE_3fmt */ 14060 /* nFields */ 7, 14061 /* *fields */ soc_CPU_OPCODES_OVERLAY_TYPE_3_BCM56260_A0fmt_fields, 14062 /* bits */ 8, 14063 /* flags */ 0, 14064 }, 14065 #endif /* chips */ 14066 14067 #if defined(BCM_56270_A0) 14068 { /* SOC_FORMAT_INT_CPU_OPCODES_OVERLAY_TYPE_3_BCM56270_A0fmt */ 14069 /* format CPU_OPCODES_OVERLAY_TYPE_3fmt */ 14070 /* nFields */ 7, 14071 /* *fields */ soc_CPU_OPCODES_OVERLAY_TYPE_3_BCM56260_A0fmt_fields, 14072 /* bits */ 8, 14073 /* flags */ 0, 14074 }, 14075 #endif /* chips */ 14076 14077 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 14078 defined(BCM_56870_A0) 14079 { /* SOC_FORMAT_INT_CPU_OPCODE_VAL_PROBES_DOPfmt */ 14080 /* format CPU_OPCODE_VAL_PROBES_DOPfmt */ 14081 /* nFields */ 2, 14082 /* *fields */ soc_CPU_OPCODE_VAL_PROBES_DOPfmt_fields, 14083 /* bits */ 64, 14084 /* flags */ 0, 14085 }, 14086 #endif /* chips */ 14087 14088 #if defined(BCM_56524_B0) || defined(BCM_56624_B0) || \ 14089 defined(BCM_56634_A0) || defined(BCM_56680_A0) || \ 14090 defined(BCM_56685_B0) || defined(BCM_56800_A0) 14091 { /* SOC_FORMAT_INT_CPU_PROTOCOLfmt */ 14092 /* format CPU_PROTOCOLfmt */ 14093 /* nFields */ 8, 14094 /* *fields */ soc_CPU_PROTOCOLfmt_fields, 14095 /* bits */ 8, 14096 /* flags */ 0, 14097 }, 14098 #endif /* chips */ 14099 14100 #if defined(BCM_53400_A0) 14101 { /* SOC_FORMAT_INT_CPU_PROTOCOL_BCM53400_A0fmt */ 14102 /* format CPU_PROTOCOLfmt */ 14103 /* nFields */ 8, 14104 /* *fields */ soc_CPU_PROTOCOL_BCM53400_A0fmt_fields, 14105 /* bits */ 8, 14106 /* flags */ 0, 14107 }, 14108 #endif /* chips */ 14109 14110 #if defined(BCM_53540_A0) 14111 { /* SOC_FORMAT_INT_CPU_PROTOCOL_BCM53540_A0fmt */ 14112 /* format CPU_PROTOCOLfmt */ 14113 /* nFields */ 8, 14114 /* *fields */ soc_CPU_PROTOCOL_BCM53400_A0fmt_fields, 14115 /* bits */ 8, 14116 /* flags */ 0, 14117 }, 14118 #endif /* chips */ 14119 14120 #if defined(BCM_53570_A0) 14121 { /* SOC_FORMAT_INT_CPU_PROTOCOL_BCM53570_A0fmt */ 14122 /* format CPU_PROTOCOLfmt */ 14123 /* nFields */ 8, 14124 /* *fields */ soc_CPU_PROTOCOL_BCM53400_A0fmt_fields, 14125 /* bits */ 8, 14126 /* flags */ 0, 14127 }, 14128 #endif /* chips */ 14129 14130 #if defined(BCM_53570_B0) 14131 { /* SOC_FORMAT_INT_CPU_PROTOCOL_BCM53570_B0fmt */ 14132 /* format CPU_PROTOCOLfmt */ 14133 /* nFields */ 8, 14134 /* *fields */ soc_CPU_PROTOCOL_BCM53400_A0fmt_fields, 14135 /* bits */ 8, 14136 /* flags */ 0, 14137 }, 14138 #endif /* chips */ 14139 14140 #if defined(BCM_56142_A0) 14141 { /* SOC_FORMAT_INT_CPU_PROTOCOL_BCM56142_A0fmt */ 14142 /* format CPU_PROTOCOLfmt */ 14143 /* nFields */ 8, 14144 /* *fields */ soc_CPU_PROTOCOLfmt_fields, 14145 /* bits */ 8, 14146 /* flags */ 0, 14147 }, 14148 #endif /* chips */ 14149 14150 #if defined(BCM_56150_A0) 14151 { /* SOC_FORMAT_INT_CPU_PROTOCOL_BCM56150_A0fmt */ 14152 /* format CPU_PROTOCOLfmt */ 14153 /* nFields */ 8, 14154 /* *fields */ soc_CPU_PROTOCOL_BCM56640_A0fmt_fields, 14155 /* bits */ 8, 14156 /* flags */ 0, 14157 }, 14158 #endif /* chips */ 14159 14160 #if defined(BCM_56160_A0) 14161 { /* SOC_FORMAT_INT_CPU_PROTOCOL_BCM56160_A0fmt */ 14162 /* format CPU_PROTOCOLfmt */ 14163 /* nFields */ 8, 14164 /* *fields */ soc_CPU_PROTOCOL_BCM53400_A0fmt_fields, 14165 /* bits */ 8, 14166 /* flags */ 0, 14167 }, 14168 #endif /* chips */ 14169 14170 #if defined(BCM_56260_A0) 14171 { /* SOC_FORMAT_INT_CPU_PROTOCOL_BCM56260_A0fmt */ 14172 /* format CPU_PROTOCOLfmt */ 14173 /* nFields */ 8, 14174 /* *fields */ soc_CPU_PROTOCOL_BCM53400_A0fmt_fields, 14175 /* bits */ 8, 14176 /* flags */ 0, 14177 }, 14178 #endif /* chips */ 14179 14180 #if defined(BCM_56260_B0) 14181 { /* SOC_FORMAT_INT_CPU_PROTOCOL_BCM56260_B0fmt */ 14182 /* format CPU_PROTOCOLfmt */ 14183 /* nFields */ 8, 14184 /* *fields */ soc_CPU_PROTOCOL_BCM53400_A0fmt_fields, 14185 /* bits */ 8, 14186 /* flags */ 0, 14187 }, 14188 #endif /* chips */ 14189 14190 #if defined(BCM_56270_A0) 14191 { /* SOC_FORMAT_INT_CPU_PROTOCOL_BCM56270_A0fmt */ 14192 /* format CPU_PROTOCOLfmt */ 14193 /* nFields */ 8, 14194 /* *fields */ soc_CPU_PROTOCOL_BCM53400_A0fmt_fields, 14195 /* bits */ 8, 14196 /* flags */ 0, 14197 }, 14198 #endif /* chips */ 14199 14200 #if defined(BCM_56334_A0) 14201 { /* SOC_FORMAT_INT_CPU_PROTOCOL_BCM56334_A0fmt */ 14202 /* format CPU_PROTOCOLfmt */ 14203 /* nFields */ 8, 14204 /* *fields */ soc_CPU_PROTOCOLfmt_fields, 14205 /* bits */ 8, 14206 /* flags */ 0, 14207 }, 14208 #endif /* chips */ 14209 14210 #if defined(BCM_56334_B0) 14211 { /* SOC_FORMAT_INT_CPU_PROTOCOL_BCM56334_B0fmt */ 14212 /* format CPU_PROTOCOLfmt */ 14213 /* nFields */ 8, 14214 /* *fields */ soc_CPU_PROTOCOLfmt_fields, 14215 /* bits */ 8, 14216 /* flags */ 0, 14217 }, 14218 #endif /* chips */ 14219 14220 #if defined(BCM_56340_A0) 14221 { /* SOC_FORMAT_INT_CPU_PROTOCOL_BCM56340_A0fmt */ 14222 /* format CPU_PROTOCOLfmt */ 14223 /* nFields */ 8, 14224 /* *fields */ soc_CPU_PROTOCOL_BCM56640_A0fmt_fields, 14225 /* bits */ 8, 14226 /* flags */ 0, 14227 }, 14228 #endif /* chips */ 14229 14230 #if defined(BCM_56370_A0) 14231 { /* SOC_FORMAT_INT_CPU_PROTOCOL_BCM56370_A0fmt */ 14232 /* format CPU_PROTOCOLfmt */ 14233 /* nFields */ 8, 14234 /* *fields */ soc_CPU_PROTOCOL_BCM53400_A0fmt_fields, 14235 /* bits */ 8, 14236 /* flags */ 0, 14237 }, 14238 #endif /* chips */ 14239 14240 #if defined(BCM_56440_A0) 14241 { /* SOC_FORMAT_INT_CPU_PROTOCOL_BCM56440_A0fmt */ 14242 /* format CPU_PROTOCOLfmt */ 14243 /* nFields */ 8, 14244 /* *fields */ soc_CPU_PROTOCOLfmt_fields, 14245 /* bits */ 8, 14246 /* flags */ 0, 14247 }, 14248 #endif /* chips */ 14249 14250 #if defined(BCM_56440_B0) 14251 { /* SOC_FORMAT_INT_CPU_PROTOCOL_BCM56440_B0fmt */ 14252 /* format CPU_PROTOCOLfmt */ 14253 /* nFields */ 8, 14254 /* *fields */ soc_CPU_PROTOCOLfmt_fields, 14255 /* bits */ 8, 14256 /* flags */ 0, 14257 }, 14258 #endif /* chips */ 14259 14260 #if defined(BCM_56450_A0) 14261 { /* SOC_FORMAT_INT_CPU_PROTOCOL_BCM56450_A0fmt */ 14262 /* format CPU_PROTOCOLfmt */ 14263 /* nFields */ 8, 14264 /* *fields */ soc_CPU_PROTOCOL_BCM56640_A0fmt_fields, 14265 /* bits */ 8, 14266 /* flags */ 0, 14267 }, 14268 #endif /* chips */ 14269 14270 #if defined(BCM_56450_B0) 14271 { /* SOC_FORMAT_INT_CPU_PROTOCOL_BCM56450_B0fmt */ 14272 /* format CPU_PROTOCOLfmt */ 14273 /* nFields */ 8, 14274 /* *fields */ soc_CPU_PROTOCOL_BCM56640_A0fmt_fields, 14275 /* bits */ 8, 14276 /* flags */ 0, 14277 }, 14278 #endif /* chips */ 14279 14280 #if defined(BCM_56450_B1) 14281 { /* SOC_FORMAT_INT_CPU_PROTOCOL_BCM56450_B1fmt */ 14282 /* format CPU_PROTOCOLfmt */ 14283 /* nFields */ 8, 14284 /* *fields */ soc_CPU_PROTOCOL_BCM56640_A0fmt_fields, 14285 /* bits */ 8, 14286 /* flags */ 0, 14287 }, 14288 #endif /* chips */ 14289 14290 #if defined(BCM_56524_A0) 14291 { /* SOC_FORMAT_INT_CPU_PROTOCOL_BCM56524_A0fmt */ 14292 /* format CPU_PROTOCOLfmt */ 14293 /* nFields */ 8, 14294 /* *fields */ soc_CPU_PROTOCOLfmt_fields, 14295 /* bits */ 8, 14296 /* flags */ 0, 14297 }, 14298 #endif /* chips */ 14299 14300 #if defined(BCM_56560_A0) 14301 { /* SOC_FORMAT_INT_CPU_PROTOCOL_BCM56560_A0fmt */ 14302 /* format CPU_PROTOCOLfmt */ 14303 /* nFields */ 8, 14304 /* *fields */ soc_CPU_PROTOCOL_BCM53400_A0fmt_fields, 14305 /* bits */ 8, 14306 /* flags */ 0, 14307 }, 14308 #endif /* chips */ 14309 14310 #if defined(BCM_56560_B0) 14311 { /* SOC_FORMAT_INT_CPU_PROTOCOL_BCM56560_B0fmt */ 14312 /* format CPU_PROTOCOLfmt */ 14313 /* nFields */ 8, 14314 /* *fields */ soc_CPU_PROTOCOL_BCM53400_A0fmt_fields, 14315 /* bits */ 8, 14316 /* flags */ 0, 14317 }, 14318 #endif /* chips */ 14319 14320 #if defined(BCM_56624_A0) 14321 { /* SOC_FORMAT_INT_CPU_PROTOCOL_BCM56624_A0fmt */ 14322 /* format CPU_PROTOCOLfmt */ 14323 /* nFields */ 8, 14324 /* *fields */ soc_CPU_PROTOCOLfmt_fields, 14325 /* bits */ 8, 14326 /* flags */ 0, 14327 }, 14328 #endif /* chips */ 14329 14330 #if defined(BCM_56634_B0) 14331 { /* SOC_FORMAT_INT_CPU_PROTOCOL_BCM56634_B0fmt */ 14332 /* format CPU_PROTOCOLfmt */ 14333 /* nFields */ 8, 14334 /* *fields */ soc_CPU_PROTOCOLfmt_fields, 14335 /* bits */ 8, 14336 /* flags */ 0, 14337 }, 14338 #endif /* chips */ 14339 14340 #if defined(BCM_56640_A0) 14341 { /* SOC_FORMAT_INT_CPU_PROTOCOL_BCM56640_A0fmt */ 14342 /* format CPU_PROTOCOLfmt */ 14343 /* nFields */ 8, 14344 /* *fields */ soc_CPU_PROTOCOL_BCM56640_A0fmt_fields, 14345 /* bits */ 8, 14346 /* flags */ 0, 14347 }, 14348 #endif /* chips */ 14349 14350 #if defined(BCM_56670_A0) 14351 { /* SOC_FORMAT_INT_CPU_PROTOCOL_BCM56670_A0fmt */ 14352 /* format CPU_PROTOCOLfmt */ 14353 /* nFields */ 8, 14354 /* *fields */ soc_CPU_PROTOCOL_BCM53400_A0fmt_fields, 14355 /* bits */ 8, 14356 /* flags */ 0, 14357 }, 14358 #endif /* chips */ 14359 14360 #if defined(BCM_56670_B0) 14361 { /* SOC_FORMAT_INT_CPU_PROTOCOL_BCM56670_B0fmt */ 14362 /* format CPU_PROTOCOLfmt */ 14363 /* nFields */ 8, 14364 /* *fields */ soc_CPU_PROTOCOL_BCM53400_A0fmt_fields, 14365 /* bits */ 8, 14366 /* flags */ 0, 14367 }, 14368 #endif /* chips */ 14369 14370 #if defined(BCM_56680_B0) 14371 { /* SOC_FORMAT_INT_CPU_PROTOCOL_BCM56680_B0fmt */ 14372 /* format CPU_PROTOCOLfmt */ 14373 /* nFields */ 8, 14374 /* *fields */ soc_CPU_PROTOCOLfmt_fields, 14375 /* bits */ 8, 14376 /* flags */ 0, 14377 }, 14378 #endif /* chips */ 14379 14380 #if defined(BCM_56685_A0) 14381 { /* SOC_FORMAT_INT_CPU_PROTOCOL_BCM56685_A0fmt */ 14382 /* format CPU_PROTOCOLfmt */ 14383 /* nFields */ 8, 14384 /* *fields */ soc_CPU_PROTOCOLfmt_fields, 14385 /* bits */ 8, 14386 /* flags */ 0, 14387 }, 14388 #endif /* chips */ 14389 14390 #if defined(BCM_56725_A0) 14391 { /* SOC_FORMAT_INT_CPU_PROTOCOL_BCM56725_A0fmt */ 14392 /* format CPU_PROTOCOLfmt */ 14393 /* nFields */ 8, 14394 /* *fields */ soc_CPU_PROTOCOLfmt_fields, 14395 /* bits */ 8, 14396 /* flags */ 0, 14397 }, 14398 #endif /* chips */ 14399 14400 #if defined(BCM_56770_A0) 14401 { /* SOC_FORMAT_INT_CPU_PROTOCOL_BCM56770_A0fmt */ 14402 /* format CPU_PROTOCOLfmt */ 14403 /* nFields */ 8, 14404 /* *fields */ soc_CPU_PROTOCOL_BCM53400_A0fmt_fields, 14405 /* bits */ 8, 14406 /* flags */ 0, 14407 }, 14408 #endif /* chips */ 14409 14410 #if defined(BCM_56820_A0) 14411 { /* SOC_FORMAT_INT_CPU_PROTOCOL_BCM56820_A0fmt */ 14412 /* format CPU_PROTOCOLfmt */ 14413 /* nFields */ 8, 14414 /* *fields */ soc_CPU_PROTOCOLfmt_fields, 14415 /* bits */ 8, 14416 /* flags */ 0, 14417 }, 14418 #endif /* chips */ 14419 14420 #if defined(BCM_56840_A0) 14421 { /* SOC_FORMAT_INT_CPU_PROTOCOL_BCM56840_A0fmt */ 14422 /* format CPU_PROTOCOLfmt */ 14423 /* nFields */ 8, 14424 /* *fields */ soc_CPU_PROTOCOLfmt_fields, 14425 /* bits */ 8, 14426 /* flags */ 0, 14427 }, 14428 #endif /* chips */ 14429 14430 #if defined(BCM_56840_B0) 14431 { /* SOC_FORMAT_INT_CPU_PROTOCOL_BCM56840_B0fmt */ 14432 /* format CPU_PROTOCOLfmt */ 14433 /* nFields */ 8, 14434 /* *fields */ soc_CPU_PROTOCOLfmt_fields, 14435 /* bits */ 8, 14436 /* flags */ 0, 14437 }, 14438 #endif /* chips */ 14439 14440 #if defined(BCM_56850_A0) 14441 { /* SOC_FORMAT_INT_CPU_PROTOCOL_BCM56850_A0fmt */ 14442 /* format CPU_PROTOCOLfmt */ 14443 /* nFields */ 8, 14444 /* *fields */ soc_CPU_PROTOCOL_BCM56640_A0fmt_fields, 14445 /* bits */ 8, 14446 /* flags */ 0, 14447 }, 14448 #endif /* chips */ 14449 14450 #if defined(BCM_56860_A0) 14451 { /* SOC_FORMAT_INT_CPU_PROTOCOL_BCM56860_A0fmt */ 14452 /* format CPU_PROTOCOLfmt */ 14453 /* nFields */ 8, 14454 /* *fields */ soc_CPU_PROTOCOL_BCM56640_A0fmt_fields, 14455 /* bits */ 8, 14456 /* flags */ 0, 14457 }, 14458 #endif /* chips */ 14459 14460 #if defined(BCM_56870_A0) 14461 { /* SOC_FORMAT_INT_CPU_PROTOCOL_BCM56870_A0fmt */ 14462 /* format CPU_PROTOCOLfmt */ 14463 /* nFields */ 8, 14464 /* *fields */ soc_CPU_PROTOCOL_BCM53400_A0fmt_fields, 14465 /* bits */ 8, 14466 /* flags */ 0, 14467 }, 14468 #endif /* chips */ 14469 14470 #if defined(BCM_56960_A0) 14471 { /* SOC_FORMAT_INT_CPU_PROTOCOL_BCM56960_A0fmt */ 14472 /* format CPU_PROTOCOLfmt */ 14473 /* nFields */ 8, 14474 /* *fields */ soc_CPU_PROTOCOL_BCM53400_A0fmt_fields, 14475 /* bits */ 8, 14476 /* flags */ 0, 14477 }, 14478 #endif /* chips */ 14479 14480 #if defined(BCM_56965_A0) 14481 { /* SOC_FORMAT_INT_CPU_PROTOCOL_BCM56965_A0fmt */ 14482 /* format CPU_PROTOCOLfmt */ 14483 /* nFields */ 8, 14484 /* *fields */ soc_CPU_PROTOCOL_BCM53400_A0fmt_fields, 14485 /* bits */ 8, 14486 /* flags */ 0, 14487 }, 14488 #endif /* chips */ 14489 14490 #if defined(BCM_56970_A0) 14491 { /* SOC_FORMAT_INT_CPU_PROTOCOL_BCM56970_A0fmt */ 14492 /* format CPU_PROTOCOLfmt */ 14493 /* nFields */ 8, 14494 /* *fields */ soc_CPU_PROTOCOL_BCM53400_A0fmt_fields, 14495 /* bits */ 8, 14496 /* flags */ 0, 14497 }, 14498 #endif /* chips */ 14499 14500 #if defined(BCM_56980_A0) 14501 { /* SOC_FORMAT_INT_CPU_PROTOCOL_BCM56980_A0fmt */ 14502 /* format CPU_PROTOCOLfmt */ 14503 /* nFields */ 8, 14504 /* *fields */ soc_CPU_PROTOCOL_BCM53400_A0fmt_fields, 14505 /* bits */ 8, 14506 /* flags */ 0, 14507 }, 14508 #endif /* chips */ 14509 14510 #if defined(BCM_56980_B0) 14511 { /* SOC_FORMAT_INT_CPU_PROTOCOL_BCM56980_B0fmt */ 14512 /* format CPU_PROTOCOLfmt */ 14513 /* nFields */ 8, 14514 /* *fields */ soc_CPU_PROTOCOL_BCM53400_A0fmt_fields, 14515 /* bits */ 8, 14516 /* flags */ 0, 14517 }, 14518 #endif /* chips */ 14519 14520 #if defined(BCM_88732_A0) 14521 { /* SOC_FORMAT_INT_CPU_PROTOCOL_BCM88732_A0fmt */ 14522 /* format CPU_PROTOCOLfmt */ 14523 /* nFields */ 8, 14524 /* *fields */ soc_CPU_PROTOCOLfmt_fields, 14525 /* bits */ 8, 14526 /* flags */ 0, 14527 }, 14528 #endif /* chips */ 14529 14530 #if defined(BCM_56142_A0) 14531 { /* SOC_FORMAT_INT_CPU_XQHDR_S_RFfmt */ 14532 /* format CPU_XQHDR_S_RFfmt */ 14533 /* nFields */ 1, 14534 /* *fields */ soc_AGING_CTR_S_RF_BCM56142_A0fmt_fields, 14535 /* bits */ 18, 14536 /* flags */ 0, 14537 }, 14538 #endif /* chips */ 14539 14540 #if defined(BCM_56640_A0) 14541 { /* SOC_FORMAT_INT_CP_REQ_BUSfmt */ 14542 /* format CP_REQ_BUSfmt */ 14543 /* nFields */ 20, 14544 /* *fields */ soc_CP_REQ_BUSfmt_fields, 14545 /* bits */ 688, 14546 /* flags */ 0, 14547 }, 14548 #endif /* chips */ 14549 14550 #if defined(BCM_56960_A0) || defined(BCM_56965_A0) 14551 { /* SOC_FORMAT_INT_CTR_EVICTION_MESSAGEfmt */ 14552 /* format CTR_EVICTION_MESSAGEfmt */ 14553 /* nFields */ 9, 14554 /* *fields */ soc_CTR_EVICTION_MESSAGEfmt_fields, 14555 /* bits */ 83, 14556 /* flags */ 0, 14557 }, 14558 #endif /* chips */ 14559 14560 #if defined(BCM_56370_A0) 14561 { /* SOC_FORMAT_INT_CTR_EVICTION_MESSAGE_BCM56370_A0fmt */ 14562 /* format CTR_EVICTION_MESSAGEfmt */ 14563 /* nFields */ 9, 14564 /* *fields */ soc_CTR_EVICTION_MESSAGE_BCM56870_A0fmt_fields, 14565 /* bits */ 86, 14566 /* flags */ 0, 14567 }, 14568 #endif /* chips */ 14569 14570 #if defined(BCM_56770_A0) 14571 { /* SOC_FORMAT_INT_CTR_EVICTION_MESSAGE_BCM56770_A0fmt */ 14572 /* format CTR_EVICTION_MESSAGEfmt */ 14573 /* nFields */ 9, 14574 /* *fields */ soc_CTR_EVICTION_MESSAGE_BCM56870_A0fmt_fields, 14575 /* bits */ 86, 14576 /* flags */ 0, 14577 }, 14578 #endif /* chips */ 14579 14580 #if defined(BCM_56870_A0) 14581 { /* SOC_FORMAT_INT_CTR_EVICTION_MESSAGE_BCM56870_A0fmt */ 14582 /* format CTR_EVICTION_MESSAGEfmt */ 14583 /* nFields */ 9, 14584 /* *fields */ soc_CTR_EVICTION_MESSAGE_BCM56870_A0fmt_fields, 14585 /* bits */ 86, 14586 /* flags */ 0, 14587 }, 14588 #endif /* chips */ 14589 14590 #if defined(BCM_56970_A0) 14591 { /* SOC_FORMAT_INT_CTR_EVICTION_MESSAGE_BCM56970_A0fmt */ 14592 /* format CTR_EVICTION_MESSAGEfmt */ 14593 /* nFields */ 9, 14594 /* *fields */ soc_CTR_EVICTION_MESSAGE_BCM56970_A0fmt_fields, 14595 /* bits */ 87, 14596 /* flags */ 0, 14597 }, 14598 #endif /* chips */ 14599 14600 #if defined(BCM_56980_A0) 14601 { /* SOC_FORMAT_INT_CTR_EVICTION_MESSAGE_BCM56980_A0fmt */ 14602 /* format CTR_EVICTION_MESSAGEfmt */ 14603 /* nFields */ 9, 14604 /* *fields */ soc_CTR_EVICTION_MESSAGE_BCM56980_A0fmt_fields, 14605 /* bits */ 87, 14606 /* flags */ 0, 14607 }, 14608 #endif /* chips */ 14609 14610 #if defined(BCM_56980_B0) 14611 { /* SOC_FORMAT_INT_CTR_EVICTION_MESSAGE_BCM56980_B0fmt */ 14612 /* format CTR_EVICTION_MESSAGEfmt */ 14613 /* nFields */ 9, 14614 /* *fields */ soc_CTR_EVICTION_MESSAGE_BCM56980_A0fmt_fields, 14615 /* bits */ 87, 14616 /* flags */ 0, 14617 }, 14618 #endif /* chips */ 14619 14620 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 14621 defined(BCM_56870_A0) 14622 { /* SOC_FORMAT_INT_CUR_L3_INTFfmt */ 14623 /* format CUR_L3_INTFfmt */ 14624 /* nFields */ 4, 14625 /* *fields */ soc_CUR_L3_INTFfmt_fields, 14626 /* bits */ 5, 14627 /* flags */ 0, 14628 }, 14629 #endif /* chips */ 14630 14631 #if defined(BCM_56370_A0) || defined(BCM_56770_A0) || \ 14632 defined(BCM_56870_A0) 14633 { /* SOC_FORMAT_INT_CUR_NEXT_HOPfmt */ 14634 /* format CUR_NEXT_HOPfmt */ 14635 /* nFields */ 6, 14636 /* *fields */ soc_CUR_NEXT_HOPfmt_fields, 14637 /* bits */ 7, 14638 /* flags */ 0, 14639 }, 14640 #endif /* chips */ 14641