bus.c (76090B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * I2C driver for the CPU Management Interface Controller (CMIC). This 8 * module provides common I2C Bus driver routines for using the the 9 * I2C bus controller internal to the CMIC as a bus-master. (I2C 10 * bus-master driver interface). 11 * 12 * The I2C bus is a 2-wire bus originally developed by Philips 13 * Semiconductor for bi-directional data I/O between two 14 * interconnected integrated circuits (hence the name Inter-IC, IIC or 15 * I2C). The I2C bus uses the 2-wires SDA (Serial Data) and SCL 16 * (Serial Clock) and each device connected to the bus is addressable 17 * through a unique slave or device address while simple master/slave 18 * relationships exist at all times. Serial, 8-bit oriented, 19 * bi-directional data transfers can be made at up to 400Kbits/sec in 20 * fast mode, with 100Kbits/s being the norm. The number of IC's 21 * connected to this bus is limited only by a maximum bus capacitance 22 * of 400pF. For more information, see: The I2C Bus and How to Use it 23 * 24 * This driver allows access to I2C slave devices attached to the SOC 25 * (Switch on a Chip) device's SCL and SDA pins. The SDA and SCL pins 26 * are controlled by the intelligent I2C controller inside the CMIC. 27 * 28 * Known Issues 29 * 30 * Currently, slave mode is supported only in HW, as supporting dual 31 * mode (master/slave) in software is currently unimplemented. 32 * 33 * The I2C controller will automatically enter slave transmit mode if 34 * it receives it's own Slave address with the read bit 35 * set. Similarly, the I2C controller will automatically enter slave 36 * receive mode if it receives it's own slave address and the write 37 * bit, or the general call address. The implication is that you 38 * cannot have two masters with the same slave address on the same bus 39 * or using the General call address at this time. 40 */ 41 42 #include <shared/bsl.h> 43 44 #include <sal/types.h> 45 #include <sal/core/boot.h> 46 #include <shared/bsl.h> 47 #include <soc/debug.h> 48 #include <soc/error.h> 49 #include <soc/drv.h> 50 #include <soc/cmic.h> 51 #include <soc/iproc.h> 52 #include <soc/cm.h> 53 #include <soc/i2c.h> 54 #ifdef BCM_CMICM_SUPPORT 55 #include <soc/cmicm.h> 56 #endif 57 58 #define KHZ_TO_HZ(n) ((n)*1000) 59 60 #ifdef HW_DEBUG 61 #define SOC_I2C_EVENT_LOGGING 1 62 #define SOC_I2C_TIME_STAMPING 1 63 #endif 64 65 #ifdef SOC_I2C_EVENT_LOGGING 66 #define SOC_I2C_MAX_EVENTS (1024*1024) /* 1MB trace buffer */ 67 static uint8* log_ptr[SOC_MAX_NUM_DEVICES]; 68 static int log_index[SOC_MAX_NUM_DEVICES]; 69 #ifdef SOC_I2C_TIME_STAMPING 70 static sal_usecs_t* time_ptr[SOC_MAX_NUM_DEVICES]; 71 #endif 72 #endif 73 74 /* 75 * Function: soc_i2c_log_event 76 * 77 * Purpose: Add the last bus status to the event log. 78 * 79 * Parameters: 80 * unit - StrataSwitch device number or I2C bus number 81 * status - value of BUS STATUS register. 82 * 83 * Returns: 84 * none 85 * 86 * Notes: 87 * This routine is used to capture a trace of bus activity. 88 */ 89 void 90 soc_i2c_log_event(int unit, uint8 status) 91 { 92 #ifdef SOC_I2C_EVENT_LOGGING 93 int idx = log_index[unit]; 94 95 if (log_index[unit] == SOC_I2C_MAX_EVENTS) { 96 log_index[unit] = 0; 97 } 98 99 log_ptr[unit][idx] = status; 100 101 #ifdef SOC_I2C_TIME_STAMPING 102 time_ptr[unit][idx] = sal_time_usecs(); 103 #endif 104 105 log_index[unit]++; 106 #else 107 COMPILER_REFERENCE(unit); 108 COMPILER_REFERENCE(status); 109 #endif 110 } 111 112 /* 113 * Function: soc_i2c_show_log 114 * 115 * Purpose: Display the bus trace event log for the specified unit. 116 * 117 * Parameters: 118 * unit - StrataSwitch device number or I2C bus number 119 * reverse - if set, the log is show in reverse order. 120 * 121 * Returns: 122 * none 123 * 124 * Notes: 125 * This routine is used to capture a trace of bus activity. 126 */ 127 void 128 soc_i2c_show_log(int unit, int reverse) 129 { 130 #ifdef SOC_I2C_EVENT_LOGGING 131 int i; 132 133 if (reverse) { 134 for (i = log_index[unit]; i >= 0; i--) { 135 #ifdef SOC_I2C_TIME_STAMPING 136 LOG_CLI((BSL_META_U(unit, 137 "%dus: STATUS[%d]: %s (0x%x)\n"), 138 time_ptr[unit][i], 139 i, 140 soc_i2c_status_message((soc_i2c_status_t)log_ptr[unit][i]), 141 (soc_i2c_status_t)log_ptr[unit][i])); 142 #else 143 LOG_CLI((BSL_META_U(unit, 144 "STATUS[%d]: %s (0x%x)\n"), 145 i, 146 soc_i2c_status_message((soc_i2c_status_t)log_ptr[unit][i]), 147 (soc_i2c_status_t)log_ptr[unit][i])); 148 #endif 149 } 150 } else { 151 for (i = 0; i < log_index[unit]; i++) { 152 #ifdef SOC_I2C_TIME_STAMPING 153 LOG_CLI((BSL_META_U(unit, 154 "%dus: STATUS[%d]: %s (0x%x)\n"), 155 time_ptr[unit][i], 156 i, 157 soc_i2c_status_message((soc_i2c_status_t)log_ptr[unit][i]), 158 (soc_i2c_status_t)log_ptr[unit][i])); 159 #else 160 LOG_CLI((BSL_META_U(unit, 161 "STATUS[%d]: %s (0x%x)\n"), 162 i, 163 soc_i2c_status_message((soc_i2c_status_t)log_ptr[unit][i]), 164 (soc_i2c_status_t)log_ptr[unit][i])); 165 #endif 166 } 167 } 168 #else 169 LOG_CLI((BSL_META_U(unit, 170 "NOTICE: SOC_I2C_EVENT_LOGGING not compiled in.\n"))); 171 #endif 172 } 173 174 void 175 soc_i2c_clear_log(int unit) 176 { 177 #ifdef SOC_I2C_EVENT_LOGGING 178 log_index[unit] = 0; 179 #endif 180 } 181 182 /* 183 * The CMIC I2C controller register values are clocked off the 184 * I2C bus which is slow in comparison to PCI. As a result, we 185 * need a few PCI cycles of delay so that the CPU "sees" the 186 * correct I2C register value. 187 */ 188 #define SLEEP(u) \ 189 { \ 190 soc_pci_read(u, CMIC_I2C_SLAVE_ADDR); \ 191 soc_pci_read(u, CMIC_I2C_SLAVE_ADDR); \ 192 soc_pci_read(u, CMIC_I2C_SLAVE_ADDR); \ 193 soc_pci_read(u, CMIC_I2C_SLAVE_ADDR); \ 194 } 195 196 /* 197 * Get a CMIC I2C register in PCI space. 198 * Input address is relative to the base of CMIC registers. 199 * Same as soc_pci_read(), with a delay for I2C register 200 * access. 201 */ 202 uint32 203 soc_i2c_pci_read(int unit, uint32 addr) 204 { 205 SLEEP(unit); 206 return soc_pci_read(unit, addr); 207 } 208 209 /* 210 * Set a CMIC I2C register in PCI space. 211 * Input address is relative to the base of CMIC registers. 212 * Same as soc_pci_write(), with a delay for I2C register 213 * access. 214 */ 215 int 216 soc_i2c_pci_write(int unit, uint32 addr, uint32 data) 217 { 218 soc_pci_write(unit, addr, data); 219 SLEEP(unit); 220 return 0; 221 } 222 223 /* 224 * Function: soc_write_i2c_stop_bits 225 * 226 * Purpose: Generate stop condition on the I2C Bus. 227 * This also recovers from an I2C bus error. 228 * 229 * Parameters: 230 * unit - StrataSwitch device number or I2C bus number 231 * 232 * Returns: 233 * none 234 * 235 * Notes: 236 * none 237 */ 238 STATIC INLINE void 239 soc_write_i2c_stop_bits(int unit) 240 { 241 soc_i2c_bus_t *i2cbus; 242 uint32 reg; 243 244 i2cbus = I2CBUS(unit); 245 reg = soc_i2c_pci_read(unit, CMIC_I2C_CTRL); 246 reg |= (CI2CC_MM_STOP | CI2CC_AACK); 247 reg &= ~CI2CC_INT_FLAG; 248 249 /* 250 * Clear Intr from any previous phase, and initiate STOP phase. 251 * IFLG will NOT set when the STOP phase has completed. 252 */ 253 soc_i2c_pci_write(unit, CMIC_I2C_CTRL, reg); 254 255 /* If in interrupt mode, leave I2C interrupt unmasked (enabled). */ 256 if ((i2cbus->flags & SOC_I2C_MODE_INTR)) { 257 #ifdef BCM_ESW_SUPPORT 258 soc_intr_enable(unit, IRQ_I2C_INTR); 259 #endif 260 } 261 262 } 263 264 /* 265 * Function: soc_write_i2c_start_bits 266 * 267 * Purpose: Generate start condition on the I2C bus. 268 * 269 * Parameters: 270 * unit - StrataSwitch device number or I2C bus number 271 * Returns: 272 * none 273 * Notes: 274 * none 275 */ 276 STATIC INLINE void 277 soc_write_i2c_start_bits(int unit) 278 { 279 soc_i2c_bus_t *i2cbus; 280 uint32 reg; 281 282 i2cbus = I2CBUS(unit); 283 reg = soc_i2c_pci_read(unit, CMIC_I2C_CTRL); 284 285 reg |= (CI2CC_MM_START | CI2CC_AACK); 286 reg &= ~CI2CC_INT_FLAG; 287 288 /* If in interrupt mode, make sure I2C interrupt is disabled. */ 289 if ((i2cbus->flags & SOC_I2C_MODE_INTR)) { 290 #ifdef BCM_ESW_SUPPORT 291 soc_intr_disable(unit, IRQ_I2C_INTR); 292 #endif 293 } 294 295 /* 296 * Clear Intr from any previous phase, and initiate START or 297 * REPEATED_START. 298 * IFLG will set when the START/REPEATED_START phase has completed. 299 */ 300 soc_i2c_pci_write(unit, CMIC_I2C_CTRL, reg); 301 302 /* If in interrupt mode, make sure I2C interrupt is enabled. */ 303 if ((i2cbus->flags & SOC_I2C_MODE_INTR)) { 304 #ifdef BCM_ESW_SUPPORT 305 soc_intr_enable(unit, IRQ_I2C_INTR); 306 #endif 307 } 308 309 } 310 311 /* 312 * Function: soc_i2c_reset 313 * 314 * Purpose: Reset I2C Bus controller core logic. 315 * 316 * Parameters: 317 * unit - StrataSwitch I2C bus controller chip number (PCI device) 318 * Returns: 319 * none 320 * Notes: 321 */ 322 void 323 soc_i2c_reset(int unit) 324 { 325 #if defined(BCM_CMICM_SUPPORT) || defined(BCM_CMICX_SUPPORT) 326 uint32 rval; 327 #endif 328 329 #ifdef BCM_CMICM_SUPPORT 330 if(soc_feature(unit, soc_feature_cmicm)) { 331 READ_CMIC_I2CM_SMBUS_CONFIGr(unit,&rval); 332 soc_reg_field_set(unit, CMIC_I2CM_SMBUS_CONFIGr, &rval, RESETf, 1); 333 WRITE_CMIC_I2CM_SMBUS_CONFIGr(unit,rval); 334 soc_reg_field_set(unit, CMIC_I2CM_SMBUS_CONFIGr, &rval, RESETf, 0); 335 WRITE_CMIC_I2CM_SMBUS_CONFIGr(unit,rval); 336 } else 337 #endif 338 #ifdef BCM_CMICX_SUPPORT 339 if(soc_feature(unit, soc_feature_cmicx)) { 340 if (soc_feature(unit, soc_feature_use_smbus2_for_i2c)) { 341 READ_IPROCPERIPH_SMBUS2_SMBUS_CONFIGr(unit,&rval); 342 soc_reg_field_set(unit, IPROCPERIPH_SMBUS2_SMBUS_CONFIGr, &rval, RESETf, 1); 343 WRITE_IPROCPERIPH_SMBUS2_SMBUS_CONFIGr(unit,rval); 344 soc_reg_field_set(unit, IPROCPERIPH_SMBUS2_SMBUS_CONFIGr, &rval, RESETf, 0); 345 WRITE_IPROCPERIPH_SMBUS2_SMBUS_CONFIGr(unit,rval); 346 } else { 347 READ_IPROCPERIPH_SMBUS1_SMBUS_CONFIGr(unit,&rval); 348 soc_reg_field_set(unit, IPROCPERIPH_SMBUS1_SMBUS_CONFIGr, &rval, RESETf, 1); 349 WRITE_IPROCPERIPH_SMBUS1_SMBUS_CONFIGr(unit,rval); 350 soc_reg_field_set(unit, IPROCPERIPH_SMBUS1_SMBUS_CONFIGr, &rval, RESETf, 0); 351 WRITE_IPROCPERIPH_SMBUS1_SMBUS_CONFIGr(unit,rval); 352 } 353 } else 354 #endif 355 { 356 soc_i2c_pci_write(unit, CMIC_I2C_RESET, 0x000000ff); 357 sal_usleep(10000); 358 } 359 } 360 361 /* 362 * Function: soc_i2c_decode_ctrl 363 * 364 * Purpose: Pretty print encoding of control register. 365 * 366 * Parameters: 367 * ctrl - unsigned 8bit value for I2C control register 368 * (CMIC PCIM off=0x128 (CMIC_I2C_CONTROL) 369 * Returns: 370 * none 371 * Notes: 372 * Pretty-printed output of bit meanings in control register. 373 */ 374 STATIC void 375 soc_i2c_decode_ctrl(uint8 ctrl) 376 { 377 if (ctrl & CI2CC_INT_EN) { 378 LOG_CLI((BSL_META(" ie"))); 379 } 380 if (ctrl & CI2CC_BUS_EN) { 381 LOG_CLI((BSL_META(" be"))); 382 } 383 if (ctrl & CI2CC_MM_START) { 384 LOG_CLI((BSL_META(" sta"))); 385 } 386 if (ctrl & CI2CC_MM_STOP) { 387 LOG_CLI((BSL_META(" stp"))); 388 } 389 if (ctrl & CI2CC_INT_FLAG) { 390 LOG_CLI((BSL_META(" ip"))); 391 } 392 if (ctrl & CI2CC_AACK) { 393 LOG_CLI((BSL_META(" aak"))); 394 } 395 LOG_CLI((BSL_META("\n"))); 396 } 397 398 /* 399 * Function: soc_i2c_decode_op 400 * 401 * Purpose: Print CPU requested IO. 402 * 403 * Parameters: 404 * soc_i2c_op_t opcode -- CPU opcode 405 * Returns: 406 * none 407 * Notes: 408 * Pretty-printed output of meanings of last CPU initiated IO. 409 */ 410 STATIC char* 411 soc_i2c_decode_op(soc_i2c_op_t opcode) 412 { 413 switch (opcode) { 414 case SOC_I2C_IDLE: return "IDLE"; 415 case SOC_I2C_START: return "START"; 416 case SOC_I2C_REP_START: return "REP START"; 417 case SOC_I2C_TX: return "TX"; 418 case SOC_I2C_RX: return "RX"; 419 case SOC_I2C_STOP: return "STOP"; 420 case SOC_I2C_PROBE: return "PROBE"; 421 default: return "?"; 422 } 423 } 424 425 /* 426 * Function: soc_i2c_decode_flags 427 * 428 * Purpose: Decode driver flags and pretty print output. 429 * 430 * Parameters: 431 * unit - StrataSwitch device number or I2C bus number 432 * msg - message string to print after device string 433 * flags - I2C Bus driver flags value. 434 * Returns: 435 * none 436 * Notes: 437 * Pretty-printed output of meanings of current state of driver. 438 */ 439 void 440 soc_i2c_decode_flags(int unit, char *msg, uint32 flags) 441 { 442 LOG_CLI((BSL_META_U(unit, 443 "unit %d i2c: %s:"), unit, msg)); 444 if (flags == 0) { 445 LOG_CLI((BSL_META_U(unit, 446 " OFFLINE"))); 447 } 448 if (flags & SOC_I2C_MODE_PIO) { 449 LOG_CLI((BSL_META_U(unit, 450 " PIO"))); 451 } 452 if (flags & SOC_I2C_MODE_INTR) { 453 LOG_CLI((BSL_META_U(unit, 454 " INTR"))); 455 } 456 if (flags & SOC_I2C_ATTACHED) { 457 LOG_CLI((BSL_META_U(unit, 458 " ATTACHED"))); 459 } 460 LOG_CLI((BSL_META_U(unit, 461 "\n"))); 462 } 463 464 /* 465 * Function: soc_i2c_wait_for_iflg_set 466 * 467 * Purpose: Read IFLG register, if not set, then busy-wait (spin) 468 * until ihe IFLG register has been set, or if the number of retries 469 * have been exceeded, a timeout error. 470 * 471 * Parameters: 472 * unit - StrataSwitch device number or I2C bus number 473 * 474 * Returns: 475 * SOC_E_NONE - device ok 476 * SOC_E_TIMEOUT - the last operation (state) timed out. 477 * 478 * Notes: 479 * This is used for PIO mode I2C operations. 480 */ 481 int 482 soc_i2c_wait_for_iflg_set(int unit) 483 { 484 soc_i2c_bus_t *i2cbus; 485 volatile register uint32 reg; 486 uint32 retries; 487 488 i2cbus = I2CBUS(unit); 489 retries = i2cbus->pio_retries; 490 491 while (!((reg = soc_i2c_pci_read(unit, CMIC_I2C_CTRL)) & 492 CI2CC_INT_FLAG) 493 && --retries) { 494 sal_udelay(1); 495 /* SPIN */ 496 } 497 498 /* Store a statistic for PIO mode */ 499 i2cbus->iflg_polls = _i2c_abs(((int)i2cbus->pio_retries) - (int) retries); 500 return retries > 0 ? SOC_E_NONE : SOC_E_TIMEOUT; 501 } 502 503 /* Forward declaration of static routine to set bus frequency */ 504 static int soc_i2c_set_freq(int unit); 505 506 /* 507 * Function: soc_i2c_attach 508 * 509 * Purpose: I2C Bus attach routine, main entry point for I2C startup. 510 * Initialize the I2C controller configuration for the specified 511 * device. Default is to disable the device, if enable is specified, 512 * the default frequency is 100Khz. Flags currently allows selection 513 * of Interrupt driven mode, PIO mode, or force configuration. 514 * 515 * Parameters: 516 * unit - StrataSwitch device number or I2C bus number 517 * flags - bitmap (logical OR) of one or more of the following: 518 * SOC_I2C_MODE_INTR - interrupt driven mode 519 * SOC_I2C_MODE_PIO - programmed I/O mode 520 * speed_khz - Requested I2C bus speed, in kilohertz. 521 * Zero or excessively large values use default speed. 522 * < 0 uses currently programmed H/W speed, or default 523 * speed if H/W not currently programmed. 524 * 525 * Returns: 526 * SOC_E_* if negative 527 * count of found devices if positive or zero 528 * 529 * Notes: Default is Interrupt mode, if both are selected Interrupt is 530 * chosen. 531 */ 532 int 533 soc_i2c_attach(int unit, uint32 flags, int speed_khz) 534 { 535 uint32 reg; 536 soc_i2c_bus_t *i2cbus; 537 538 i2cbus = I2CBUS(unit); 539 if (i2cbus == NULL) { 540 i2cbus = sal_alloc(sizeof(*i2cbus), "i2c_bus"); 541 if (i2cbus == NULL) { 542 return SOC_E_MEMORY; 543 } 544 I2CBUS_VOID(unit) = i2cbus; 545 sal_memset(i2cbus, 0, sizeof(*i2cbus)); 546 } 547 548 if (bsl_check(bslLayerSoc, bslSourceI2c, bslSeverityNormal, unit)) { 549 soc_i2c_decode_flags(unit, "current flags", i2cbus->flags); 550 soc_i2c_decode_flags(unit, "new flags", flags); 551 } 552 553 #ifdef SOC_I2C_EVENT_LOGGING 554 if (!log_ptr[unit]) { 555 log_ptr[unit] = (uint8*)sal_alloc(SOC_I2C_MAX_EVENTS, "i2c event log"); 556 } 557 log_index[unit] = 0; 558 #ifdef SOC_I2C_TIME_STAMPING 559 if (!time_ptr[unit]) { 560 time_ptr[unit] = (sal_usecs_t*) 561 sal_alloc(SOC_I2C_MAX_EVENTS*sizeof(sal_usecs_t), 562 "i2c timestamp event log"); 563 } 564 #endif 565 #endif 566 567 568 /* If not yet done, create synchronization semaphores/mutex */ 569 if (i2cbus->i2cMutex == NULL) { 570 i2cbus->i2cMutex = sal_mutex_create("I2C Mutex"); 571 if (i2cbus->i2cMutex == NULL) { 572 return SOC_E_MEMORY; 573 } 574 } 575 576 if (i2cbus->i2cIntr == NULL) { 577 i2cbus->i2cIntr = sal_sem_create("I2C interrupt", sal_sem_BINARY, 0); 578 if (i2cbus->i2cIntr == NULL) { 579 return SOC_E_MEMORY; 580 } 581 } 582 583 /* Set semaphore timeout values */ 584 if (SAL_BOOT_QUICKTURN) { 585 i2cbus->i2cTimeout = I2C_TIMEOUT_QT; 586 } else if (SAL_BOOT_PLISIM) { 587 i2cbus->i2cTimeout = I2C_TIMEOUT_PLI; 588 } else { 589 i2cbus->i2cTimeout = I2C_TIMEOUT; 590 } 591 592 i2cbus->i2cTimeout = soc_property_get(unit, spn_I2C_TIMEOUT_USEC, 593 i2cbus->i2cTimeout); 594 595 /* Choose one or the other IO mode, default 596 * to interrupt driven 597 */ 598 if ( ((flags & SOC_I2C_MODE_INTR) != 0) == 599 ((flags & SOC_I2C_MODE_PIO) != 0) ) { 600 i2cbus->flags = SOC_I2C_MODE_INTR; 601 } else { 602 i2cbus->flags = flags & (SOC_I2C_MODE_INTR | SOC_I2C_MODE_PIO); 603 } 604 605 /* Number of PIO's (IFLG/ACK) */ 606 i2cbus->pio_retries = 1000000; 607 LOG_INFO(BSL_LS_SOC_I2C, 608 (BSL_META_U(unit, 609 "soc_i2c_attach: oldspeed=%d newspeed=%d\n"), 610 i2cbus->frequency, KHZ_TO_HZ(speed_khz))); 611 612 /* 613 * Use default speed if zero or bad value specified, 614 * or if current speed requested with unprogrammed H/W. 615 * Leave the H/W speed alone if negative speed requested 616 * and the H/W already has non-zero speed programmed. 617 * Otherwise keep requested speed. 618 */ 619 if ( ((speed_khz == 0) || (speed_khz > (SOC_IS_XGS3_SWITCH(unit) ? 250 : 2500))) || 620 ((speed_khz < 0) && (i2cbus->frequency <= 0)) ) { 621 if (SOC_IS_XGS_FABRIC(unit) || SOC_IS_XGS3_SWITCH(unit)) { 622 /* 10Gig Ethernet on board seems to cause signal 623 * integrity issue, hence, 100Khz is default on 5670. 624 */ 625 speed_khz = CMIC_I2C_SPEED_SLOW_IO; 626 } else { 627 speed_khz = CMIC_I2C_SPEED_DEFAULT; 628 } 629 } 630 #ifdef BCM_CMICM_SUPPORT 631 if(soc_feature(unit, soc_feature_cmicm)) { 632 /* I2C set to Master Mode through Override Strap */ 633 READ_CMIC_OVERRIDE_STRAPr(unit, ®); 634 soc_reg_field_set(unit, CMIC_OVERRIDE_STRAPr, ®, 635 ENABLE_OVERRIDE_I2C_MASTER_SLAVE_MODEf, 1); 636 soc_reg_field_set(unit, CMIC_OVERRIDE_STRAPr, ®, 637 I2C_MASTER_SLAVE_MODEf, 1); 638 WRITE_CMIC_OVERRIDE_STRAPr(unit, reg); 639 640 /* 1) Enable CPU access to I2C controller */ 641 READ_CMIC_I2CM_SMBUS_CONFIGr(unit,®); 642 soc_reg_field_set(unit, CMIC_I2CM_SMBUS_CONFIGr, ®, SMB_ENf, 1); 643 WRITE_CMIC_I2CM_SMBUS_CONFIGr(unit,reg); 644 /* Write to I2C register after it is enabled */ 645 if (speed_khz > 0) { 646 i2cbus->frequency = KHZ_TO_HZ(speed_khz); 647 } 648 /* 2) Program the SOC device's (7-bit) slave I2C address. */ 649 /* SOC Default Slave Address = SOC_I2C_SLAVE_BASE + PCI_ID */ 650 651 652 /* 3) Enable bus, interrupts */ 653 654 /* 4) Tell CMIC to enable SOC I2C interrupts 655 * only when in interrupt driven IO mode. 656 */ 657 658 } else 659 #endif 660 #ifdef BCM_CMICX_SUPPORT 661 if(soc_feature(unit, soc_feature_cmicx)) { 662 /* 1) Enable CPU access to I2C controller */ 663 if (soc_feature(unit, soc_feature_use_smbus2_for_i2c)) { 664 READ_IPROCPERIPH_SMBUS2_SMBUS_CONFIGr(unit,®); 665 soc_reg_field_set(unit, IPROCPERIPH_SMBUS2_SMBUS_CONFIGr, ®, SMB_ENf, 1); 666 WRITE_IPROCPERIPH_SMBUS2_SMBUS_CONFIGr(unit,reg); 667 } else { 668 READ_IPROCPERIPH_SMBUS1_SMBUS_CONFIGr(unit,®); 669 soc_reg_field_set(unit, IPROCPERIPH_SMBUS1_SMBUS_CONFIGr, ®, SMB_ENf, 1); 670 WRITE_IPROCPERIPH_SMBUS1_SMBUS_CONFIGr(unit,reg); 671 } 672 /* Write to I2C register after it is enabled */ 673 if (speed_khz > 0) { 674 i2cbus->frequency = KHZ_TO_HZ(speed_khz); 675 } 676 /* 2) Program the SOC device's (7-bit) slave I2C address. */ 677 /* SOC Default Slave Address = SOC_I2C_SLAVE_BASE + PCI_ID */ 678 679 680 /* 3) Enable bus, interrupts */ 681 682 /* 4) Tell CMIC to enable SOC I2C interrupts 683 * only when in interrupt driven IO mode. 684 */ 685 686 } else 687 #endif 688 { 689 /* 1) Enable CPU access to I2C controller */ 690 reg = soc_i2c_pci_read(unit, CMIC_CONFIG); 691 reg |= CC_I2C_EN; 692 soc_i2c_pci_write(unit, CMIC_CONFIG, reg); 693 694 /* Write to I2C register after it is enabled */ 695 if (speed_khz > 0) { 696 i2cbus->frequency = KHZ_TO_HZ(speed_khz); 697 soc_i2c_set_freq(unit); 698 } 699 700 /* 2) Program the SOC device's (7-bit) slave I2C address. */ 701 /* SOC Default Slave Address = SOC_I2C_SLAVE_BASE + PCI_ID */ 702 i2cbus->master_addr = SOC_I2C_SLAVE_BASE + unit; 703 soc_i2c_pci_write(unit, CMIC_I2C_SLAVE_ADDR, i2cbus->master_addr<<1); 704 705 /* 3) Enable bus, interrupts */ 706 reg = soc_i2c_pci_read(unit, CMIC_I2C_CTRL); 707 if (i2cbus->flags & SOC_I2C_MODE_INTR) { 708 reg |= CI2CC_INT_EN; 709 } 710 711 #ifdef CONFIG_I2C_MIXED_MODE 712 /* Allows the controller to enter slave mode when it sees 713 * either it's own or the general call address. 714 */ 715 reg |= CI2CC_BUS_EN; 716 #endif 717 soc_i2c_pci_write(unit, CMIC_I2C_CTRL, reg); 718 719 #ifdef BCM_ESW_SUPPORT 720 /* 4) Tell CMIC to enable SOC I2C interrupts 721 * only when in interrupt driven IO mode. 722 */ 723 if (i2cbus->flags & SOC_I2C_MODE_INTR) { 724 soc_intr_enable(unit, IRQ_I2C_INTR); 725 } else { 726 soc_intr_disable(unit, IRQ_I2C_INTR); 727 } 728 #endif 729 } 730 731 /* Enable smbus0 in iproc */ 732 #ifdef BCM_IPROC_SUPPORT 733 if (soc_feature(unit, soc_feature_eeprom_iproc)) { 734 /* 1) Enable CPU access to I2C controller */ 735 READ_CHIPCOMMONG_SMBUS0_SMBUS_CONFIGr(unit, ®); 736 soc_reg_field_set(unit, CHIPCOMMONG_SMBUS0_SMBUS_CONFIGr, ®, SMB_ENf, 1); 737 WRITE_CHIPCOMMONG_SMBUS0_SMBUS_CONFIGr(unit, reg); 738 } 739 #endif /* BCM_IPROC_SUPPORT */ 740 741 LOG_VERBOSE(BSL_LS_SOC_COMMON, 742 (BSL_META_U(unit, 743 "unit %d i2c 0x%03x bus: mode %s, speed %dKbps\n"), 744 unit, i2cbus->master_addr, 745 (i2cbus->flags & SOC_I2C_MODE_PIO) ? "PIO" : "INTR", 746 (i2cbus->frequency+500) / 1000 )); 747 748 /* 749 * Disable general call addresses (for now). 750 */ 751 #ifdef BCM_CMICM_SUPPORT 752 if(soc_feature(unit, soc_feature_cmicm)) { 753 754 } else 755 #endif 756 #ifdef BCM_CMICX_SUPPORT 757 if(soc_feature(unit, soc_feature_cmicx)) { 758 759 } else 760 #endif 761 { 762 soc_i2c_pci_write(unit, CMIC_I2C_SLAVE_ADDR, 763 soc_i2c_pci_read(unit, CMIC_I2C_SLAVE_ADDR) 764 & ~(0x01)); 765 } 766 767 i2cbus->flags |= SOC_I2C_ATTACHED; 768 769 /* 770 * Probe for I2C devices, update device list for detected devices ... 771 */ 772 if (flags & SOC_I2C_NO_PROBE) { 773 return SOC_E_NONE; 774 } else { 775 return soc_i2c_probe(unit); 776 } 777 778 } 779 780 /* 781 * Function: soc_i2c_detach 782 * 783 * Purpose: I2C detach routine: free resources used by I2C bus driver. 784 * 785 * Paremeters: 786 * unit - StrataSwitch device number or I2C bus number 787 * Returns: 788 * SOC_E_NONE - no error 789 * Notes: 790 * none 791 */ 792 int 793 soc_i2c_detach(int unit) 794 { 795 soc_i2c_bus_t *i2cbus; 796 797 i2cbus = I2CBUS(unit); 798 799 if (i2cbus != NULL) { 800 (void)soc_i2c_unload_devices(unit); 801 if (i2cbus->i2cIntr) { 802 sal_sem_destroy(i2cbus->i2cIntr); 803 i2cbus->i2cIntr = 0; 804 } 805 if (i2cbus->i2cMutex) { 806 sal_mutex_destroy(i2cbus->i2cMutex); 807 i2cbus->i2cMutex = 0; 808 } 809 sal_free(i2cbus); 810 I2CBUS_VOID(unit) = NULL; 811 } 812 813 return SOC_E_NONE; 814 } 815 816 /* 817 * Function: soc_i2c_next_bus_phase 818 * 819 * Purpose: Interrupt clear/next operation continue. Clear the IFLG 820 * to trigger or complete a CPU initiated transaction. If tx_ack is 821 * set, then an acknowledgement will be sent; usually tx_ack is only 822 * relevant for receive operations. 823 * 824 * Parameters: 825 * unit - StrataSwitch device number or I2C bus number 826 * tx_ack - when non-zero, ACKs will be sent, otherwise NACKs will be sent. 827 * 828 * Returns: 829 * Once the next (implied) phase has been started. Calling code 830 * must call soc_i2c_wait() to get indication of phase completion. 831 * 832 * Notes: 833 * The nature of the next bus phase depends on the current state 834 * of the I2C controller. 835 */ 836 void 837 soc_i2c_next_bus_phase(int unit, int tx_ack) 838 { 839 volatile register uint32 reg, data=0; 840 soc_i2c_bus_t *i2cbus; 841 842 i2cbus = I2CBUS(unit); 843 844 #ifdef SOC_I2C_EVENT_LOGGING 845 soc_i2c_log_event(unit, soc_i2c_stat(unit)); 846 #endif 847 848 reg = soc_i2c_pci_read(unit, CMIC_I2C_CTRL); 849 850 /* Will clear the interrupt flag when we start next phase */ 851 reg &= ~CI2CC_INT_FLAG; 852 853 /* Set remote transmit acknowledgement .. */ 854 if (tx_ack) { 855 reg |= CI2CC_AACK; 856 } else { 857 reg &= ~CI2CC_AACK; 858 } 859 860 /* Set it all in one write */ 861 soc_i2c_pci_write(unit, CMIC_I2C_CTRL, reg); 862 863 /* More debug nonsense */ 864 LOG_INFO(BSL_LS_SOC_I2C, 865 (BSL_META_U(unit, 866 "soc_i2c_next_bus_phase: (after) " 867 "ctrl=0x%x data=0x%x op=%s(%d) "), 868 reg, data, 869 soc_i2c_decode_op(i2cbus->opcode), 870 i2cbus->opcode)); 871 if (bsl_check(bslLayerSoc, bslSourceI2c, bslSeverityNormal, unit)) { 872 soc_i2c_decode_ctrl(reg); 873 } 874 875 /* If in interrupt mode, re-enable the I2C interrupt. */ 876 if (i2cbus->flags & SOC_I2C_MODE_INTR) { 877 #ifdef BCM_ESW_SUPPORT 878 soc_intr_enable(unit, IRQ_I2C_INTR); 879 #endif 880 } 881 882 } 883 884 /* 885 * Function: soc_i2c_stat 886 * 887 * Purpose: Return bus status code in enumerated type format. 888 * 889 * Parameters: 890 * unit - StrataSwitch device number or I2C bus number 891 * 892 * Returns: 893 * bus status code as enumerated type definition 894 * 895 * Notes: 896 * This routine should be used in conjunction with 897 * soc_i2c_status_message 898 */ 899 soc_i2c_status_t 900 soc_i2c_stat(int unit) 901 { 902 uint32 stat; 903 904 stat = soc_i2c_pci_read(unit, CMIC_I2C_STAT); 905 stat &= CMIC_I2C_REG_MASK; 906 return (soc_i2c_status_t) stat; 907 } 908 909 /* 910 * Function: soc_i2c_intr 911 * 912 * Purpose: ISR for I2C interrupts, we basically unblock the calling 913 * task since clearing of the IFLG invokes a particular 914 * action which is state-machine dependent and requires the 915 * data register be loaded before it is cleared. 916 * 917 * Parameters: 918 * unit - StrataSwitch device number or I2C bus number 919 * Returns: 920 * none 921 * Notes: 922 * executed from within interrupt context 923 */ 924 void 925 soc_i2c_intr(int unit) 926 { 927 soc_i2c_bus_t *i2cbus; 928 soc_i2c_status_t s; 929 930 i2cbus = I2CBUS(unit); 931 #ifdef BCM_ESW_SUPPORT 932 /* Disable interrupts so caller gets a chance to run... */ 933 soc_intr_disable(unit, IRQ_I2C_INTR); 934 #endif 935 s = soc_i2c_stat(unit); 936 937 /* 938 * Slave Processing: Trap all Slave requests for now, when the 939 * CMIC is in bus-slave mode (default power-up state), all of 940 * this processing is done by the CMIC I2C controller, when we 941 * are in master mode, and another master is accessing us on the 942 * bus, we may get confused as we are not acting as a slave. 943 * 944 * Slave Transmit Mode 945 * 946 * The I2C controller will enter into Slave mode when it 947 * receives it's own Slave Address, and a read bit after 948 * a start condition. 949 * 950 * Slave transmit mode can also be entered directly from a master 951 * mode transaction if arbitration is lost in master mode during 952 * the transmission of an address and the slave address and read 953 * bit are received. 954 * 955 * The data byte to be transmitted should then be loaded 956 * into the DATA register and the IFLG cleared. When the 957 * I2C controller has transmitted the byte and received an 958 * acknowledge, the IFLG will be set and the STAT register 959 * will contain 0xB8. Once the last byte to be transmitted 960 * has been loaded into the DATA register, the AAK bit 961 * should be cleared when the IFLG is cleared. After the 962 * last byte has been transmitted, the IFLG will be set and 963 * the STAT register will contain 0xC8. The I2C will then 964 * return to the idle state and the AAK bit must be set to 965 * one before slave mode can be entered again. If no 966 * acknowledge is received after transmitting a byte, the 967 * IFLG will be set and the STAT register will contact 968 * 0xC0. The I2C will then return to the idle state. If the 969 * STOP condition is detected after an acknowledge bit, the 970 * I2C will return to the idle state. 971 */ 972 973 if (s == SOC_I2C_SADDR_RX_RD_BIT_RX_ACK_TX || 974 s == SOC_I2C_ARB_LOST_IN_ADDR_PHASE_SADDR_RX_RD_BIT_RX_ACK_TX) { 975 LOG_VERBOSE(BSL_LS_SOC_COMMON, 976 (BSL_META_U(unit, 977 "i2c%d: slave transmit mode entered: %s\n"), 978 unit, soc_i2c_status_message(s))); 979 980 /* Terminate remote client: send NACK */ 981 soc_i2c_next_bus_phase(unit, FALSE); 982 } 983 984 /* 985 * Slave receive mode; in the slave receive mode, a number of 986 * bytes are received from a master transmitter. 987 * 988 * The I2C controller will enter into slave recieve mode when it 989 * receives its own slave address and a write bit (LSB=0) after a 990 * START condition. The I2C will then transmit an ACK bit and set 991 * the IFLG bit in the CTRL register: the STAT register will then 992 * contain the status code 0x60. The I2C will also enter slave 993 * receive mode when it receives the general call address 0x00 (if 994 * the GCE bit in the ADDR register is set). The status code will 995 * then be 0x70. 996 * 997 * Slave receive mode can also be entered directly from a master 998 * mode if arbitration is lost in master mode during the 999 * transmission of an address and the slave address and write bit 1000 * (or the general call address if bit GCE in the ADDR register is 1001 * set to one) are received. The status code in the STAT register 1002 * will then be 0x68 if the slave address was received or 0x78 if 1003 * the General Call address was received. The IFLG bit must be 1004 * cleared to zero to allow the data transfer to continue. 1005 * 1006 * If the AAK bit in the CTRL register is set to one, then after 1007 * each byte is received, an acknowledge bit (low level on SDA) is 1008 * transmitted and the IFLG bit is set: the stat register will then 1009 * contain status code 0x80 (or 0x90 if slave receive mode was 1010 * entered with the general call address). The received data byte 1011 * can be read from the DATA register and the IFLG bit must be 1012 * cleared to allow the transfer to continue. When the STOP 1013 * condition or a repeated START condition is detected after the 1014 * acknowledge bit, the the IFLG bit is set and the STAT register 1015 * will contain status code 0xA0. 1016 * 1017 * If the AAK bit is cleared to zero during a transfer, the I2C will 1018 * transmit a NACK bit (high level on SDA) after the next byte is 1019 * received, and set the IFLG bit. The STAT register will contain 1020 * status code 0x88 (or 0x98 if slave receive mode was entered with 1021 * the general call address). When the IFLG bit has been cleared to 1022 * zero, the I2C will return to the idle state. 1023 */ 1024 if (s == SOC_I2C_SADDR_RX_WR_BIT_RX_ACK_TX || 1025 s == SOC_I2C_GC_ADDR_RX_ACK_TX || 1026 s == SOC_I2C_ARB_LOST_SADDR_RX_WR_BIT_RX_ACK_TX || 1027 s == SOC_I2C_ARB_LOST_GC_ADDR_RX_ACK_TX || 1028 s == SOC_I2C_DATA_BYTE_RX_AFTER_SADDR_RX_ACK_TX || 1029 s == SOC_I2C_DATA_BYTE_RX_AFTER_SADDR_RX_ACK_TX || 1030 s == SOC_I2C_DATA_BYTE_RX_AFTER_SADDR_RX_NO_ACK_TX || 1031 s == SOC_I2C_DATA_BYTE_RX_AFTER_GC_ADDR_RX_ACK_TX || 1032 s == SOC_I2C_DATA_BYTE_RX_AFTER_GC_ADDR_RX_NO_ACK_TX || 1033 s == SOC_I2C_STOP_OR_REP_START_COND_RX_IN_SLAVE_MODE) { 1034 1035 LOG_VERBOSE(BSL_LS_SOC_COMMON, 1036 (BSL_META_U(unit, 1037 "i2c%d: slave receive mode entered: %s\n"), 1038 unit, soc_i2c_status_message(s))); 1039 1040 /* Terminate remote client: send NACK */ 1041 soc_i2c_next_bus_phase(unit, FALSE); 1042 } 1043 1044 /* Master processing, simply give back semaphore ... */ 1045 if (i2cbus && i2cbus->i2cIntr) { 1046 sal_sem_give(i2cbus->i2cIntr); 1047 } 1048 } 1049 1050 /* 1051 * Function: soc_i2c_wait 1052 * 1053 * Purpose: Wait for Interrupt Pending state. This routine is the second 1054 * half of soc_intr and in PIO mode, it blocks until the next 1055 * state of I2C bus controller is ready for processing. 1056 * 1057 * In interrupt-driven mode, we wait for the interrupt to 1058 * occur and to be unblocked from the semaphore relinquished 1059 * by the interrupt. In PIO mode, we poll some number of 1060 * times, waiting for IFLG to be set. 1061 * 1062 * Input: 1063 * unit - StrataSwitch device number or I2C bus number 1064 * 1065 * Returns: 1066 * SOC_E_NONE - the device was contacted and is ready for the 1067 * next I/O state. 1068 * SOC_E_TIMEOUT - device is not present or failure. 1069 * Notes: 1070 * Usually, we will initiate some action (e.g. START, ADDR), 1071 * and then we will load a data byte, clear the iflg, and then 1072 * soc_i2c_wait for the next state. Finally, we issue STOP 1073 * to release the bus. 1074 */ 1075 int 1076 soc_i2c_wait(int unit) 1077 { 1078 uint32 stat; 1079 int rv = SOC_E_NONE; 1080 soc_i2c_bus_t *i2cbus; 1081 1082 i2cbus = I2CBUS(unit); 1083 1084 /* Interrupt Driven IO: Wait for interrupt */ 1085 if (i2cbus->flags & SOC_I2C_MODE_INTR) { 1086 if (sal_sem_take(i2cbus->i2cIntr, i2cbus->i2cTimeout) != 0) { 1087 rv = SOC_E_TIMEOUT; 1088 } 1089 } else { 1090 /* PIO: Poll IFLG=1 */ 1091 rv = soc_i2c_wait_for_iflg_set(unit); 1092 } 1093 1094 stat = soc_i2c_pci_read(unit, CMIC_I2C_STAT); 1095 i2cbus->stat = stat; 1096 1097 LOG_INFO(BSL_LS_SOC_I2C, 1098 (BSL_META_U(unit, 1099 "soc_i2c_wait: current state=0x%x:[%s]\n"), 1100 stat, soc_i2c_status_message((soc_i2c_status_t)stat))); 1101 return rv; 1102 } 1103 1104 /* 1105 * Function: _i2c_start_helper 1106 * 1107 * Purpose: Helper routine for soc_i2c_start() and soc_i2c_rep_start(). 1108 * Issue an I2C start command and the provided bus_addr byte. 1109 * The bus_addr byte contains the appropriate read/write bit. 1110 * 1111 * Parameters: 1112 * unit - StrataSwitch device number or I2C bus number 1113 * bus_addr - I2C slave device bus address byte. Contains R/W info. 1114 * repeated - Set to generate REP_START, clear to generate START. 1115 * 1116 * Returns: SOC_E_NONE if the device was contacted and ready for I/O. 1117 * SOC_E_INTERNAL - Unexpected or internal error 1118 * SOC_E_TIMEOUT if the device is not present. 1119 * 1120 * If SOC_E_NONE is returned, the I2C bus is in a "suspended" 1121 * state, ready to be bumped to the next appropriate state 1122 * (read, write, or stop). 1123 * Otherwise, returns with the I2C bus in stopped (idle) state. 1124 * 1125 * Notes: 10-bit addressing currently not supported by H/W or S/W. 1126 */ 1127 int 1128 _i2c_start_helper(int unit, i2c_bus_addr_t bus_addr, int repeated) 1129 { 1130 int rv = SOC_E_NONE; 1131 soc_i2c_bus_t *i2cbus; 1132 soc_i2c_status_t s = soc_i2c_stat(unit); 1133 soc_i2c_status_t correct_next_stat = SOC_I2C_NO_STATUS; 1134 1135 i2cbus = I2CBUS(unit); 1136 /* 1137 * A START should happen only with a status of SOC_I2C_NO_STATUS. 1138 * A REP_START should happen with a non-idle status. 1139 */ 1140 if ( (!repeated && (s != SOC_I2C_NO_STATUS)) || 1141 (repeated && (s == SOC_I2C_NO_STATUS)) ) { 1142 LOG_VERBOSE(BSL_LS_SOC_COMMON, 1143 (BSL_META_U(unit, 1144 "unit %d i2c 0x%x: %sSTART- BAD STATUS: %s\n"), 1145 unit, bus_addr>>1, 1146 (repeated ? "REP_" : ""), 1147 soc_i2c_status_message(s))); 1148 rv = SOC_E_INTERNAL; 1149 goto done; 1150 } 1151 1152 soc_write_i2c_start_bits(unit); 1153 1154 if (repeated) { 1155 i2cbus->opcode = SOC_I2C_REP_START; 1156 correct_next_stat = SOC_I2C_REP_START_TX; 1157 } else { 1158 i2cbus->opcode = SOC_I2C_START; 1159 correct_next_stat = SOC_I2C_START_TX; 1160 } 1161 1162 if (SOC_E_NONE == soc_i2c_wait(unit)) { 1163 1164 if ((s = soc_i2c_stat(unit)) == correct_next_stat) { 1165 /* 1166 * We generated start, now send the slave's bus address byte. 1167 * (7-bit address mode only) 1168 */ 1169 soc_i2c_pci_write(unit, CMIC_I2C_DATA, bus_addr); 1170 soc_i2c_next_bus_phase(unit, 1); 1171 } else { 1172 LOG_INFO(BSL_LS_SOC_I2C, 1173 (BSL_META_U(unit, 1174 "unit %d i2c 0x%x: %sSTART unhandled state 0x%x:" 1175 " %s\n"), 1176 unit, bus_addr>>1, 1177 repeated?"REP_":"", 1178 s, 1179 soc_i2c_status_message(s))); 1180 rv = SOC_E_INTERNAL; 1181 goto done; 1182 } 1183 1184 /* 1185 * Now, wait again for an interrupt. One of four possible 1186 * interrupts should occur: 1187 * 1188 * Ready for IO: (R/W) 1189 * SOC_I2C_ADDR_WR_BIT_TX_ACK_RX - Device ready for writing 1190 * SOC_I2C_ADDR_RD_BIT_TX_ACK_RX - Device ready for reading 1191 * No Device : 1192 * SOC_I2C_ADDR_WR_BIT_TX_NO_ACK_RX - No device ready 1193 * for write 1194 * SOC_I2C_ADDR_RD_BIT_TX_NO_ACK_RX - No device ready 1195 * for read 1196 */ 1197 if ((rv = soc_i2c_wait(unit)) == SOC_E_NONE) { 1198 s = soc_i2c_stat(unit); 1199 if (s == SOC_I2C_ADDR_WR_BIT_TX_ACK_RX) { 1200 i2cbus->opcode = SOC_I2C_TX; 1201 rv = SOC_E_NONE; 1202 /* Next I2C bus phase is write-ready. */ 1203 } else if (s == SOC_I2C_ADDR_RD_BIT_TX_ACK_RX) { 1204 i2cbus->opcode = SOC_I2C_RX; 1205 rv = SOC_E_NONE; 1206 /* Next I2C bus phase is read-ready. */ 1207 } else if (s == SOC_I2C_ADDR_RD_BIT_TX_NO_ACK_RX || 1208 s == SOC_I2C_ADDR_WR_BIT_TX_NO_ACK_RX) { 1209 LOG_INFO(BSL_LS_SOC_I2C, 1210 (BSL_META_U(unit, 1211 "unit %d i2c 0x%x: no response from device: %s\n"), 1212 unit, bus_addr>>1, 1213 soc_i2c_status_message(s))); 1214 rv = SOC_E_TIMEOUT; 1215 } else{ 1216 LOG_INFO(BSL_LS_SOC_I2C, 1217 (BSL_META_U(unit, 1218 "unit %d i2c 0x%x: BUS_ADDR " 1219 "unhandled state 0x%x:" 1220 " %s\n"), 1221 unit, bus_addr>>1, 1222 s, 1223 soc_i2c_status_message(s))); 1224 rv = SOC_E_INTERNAL; 1225 } 1226 } 1227 } else { 1228 LOG_INFO(BSL_LS_SOC_I2C, 1229 (BSL_META_U(unit, 1230 "unit %d i2c 0x%x: timeout generating start condition:" 1231 " check or reset I2C bus\n"), 1232 unit, bus_addr>>1)); 1233 rv = SOC_E_TIMEOUT; 1234 } 1235 1236 done: 1237 if (rv != SOC_E_NONE) { 1238 /* Very important, if anything went wrong, 1239 * we MUST release the bus to return to idle state 1240 */ 1241 soc_i2c_stop(unit); 1242 } 1243 1244 return rv; 1245 } 1246 1247 1248 /* 1249 * Function: soc_i2c_start 1250 * 1251 * Purpose: Issue an I2C start command and the provided bus_addr byte. 1252 * The bus_addr byte contains the appropriate read/write bit. 1253 * 1254 * Parameters: 1255 * unit - StrataSwitch device number or I2C bus number 1256 * bus_addr - I2C slave device bus address byte. Contains R/W info. 1257 * 1258 * Returns: SOC_E_NONE if the device was contacted and ready for I/O. 1259 * SOC_E_INTERNAL - Unexpected or internal error 1260 * SOC_E_TIMEOUT if the device is not present. 1261 * 1262 * If SOC_E_NONE is returned, the I2C bus is in a "suspended" 1263 * state. Calling code must then progress to the next 1264 * appropriate I2C bus phase. 1265 * 1266 * See also: SOC_I2C_TX_ADDR(), SOC_I2C_RX_ADDR() 1267 * 1268 * Notes: 10-bit addressing currently not supported by H/W or S/W. 1269 */ 1270 int 1271 soc_i2c_start(int unit, i2c_bus_addr_t bus_addr) 1272 { 1273 return _i2c_start_helper(unit, bus_addr, FALSE); 1274 } 1275 1276 1277 /* 1278 * Function: soc_i2c_rep_start 1279 * 1280 * Purpose: Generate a repeated start and the specified bus_addr byte. 1281 * The bus_addr byte contains the appropriate read/write bit. 1282 * Typically, this is done in the middle of an operation in 1283 * order to delimit a new command sequence without releasing 1284 * the I2C bus. 1285 * 1286 * Parameters: 1287 * 1288 * unit - StrataSwitch device number or I2C bus number 1289 * bus_addr - I2C slave device bus address byte. Contains R/W info. 1290 * 1291 * Returns: 1292 * 1293 * SOC_E_TIMEOUT - the device cannot be contacted or is offline 1294 * SOC_E_INTERNAL - Unexpected or internal error 1295 * SOC_E_NONE - no error, device ready for IO. 1296 * 1297 * Notes: 1298 * If SOC_E_NONE is returned, the I2C bus is in a "suspended" 1299 * state. Calling code must then progress to the next 1300 * appropriate I2C bus phase. 1301 * 1302 * Notes: 10-bit addressing currently not supported by H/W or S/W. 1303 */ 1304 int 1305 soc_i2c_rep_start(int unit, i2c_bus_addr_t bus_addr) 1306 { 1307 return _i2c_start_helper(unit, bus_addr, TRUE); 1308 } 1309 1310 1311 /* 1312 * Function: soc_i2c_write_one_byte 1313 * 1314 * Purpose: Write data to the last addressed slave device. 1315 * 1316 * Parameters: 1317 * unit - StrataSwitch device number or I2C bus number 1318 * data - data byte to transmit 1319 * 1320 * Returns: 1321 * SOC_E_NONE if the device was contacted and the operation 1322 * succeeded. 1323 * SOC_E_BUSY if the device timed out or is busy. 1324 * 1325 * Notes: 1326 * Before this routine can be used, the I2C controller must 1327 * be in a write-ready state, i.e. following a START-WRITE_SADDR 1328 * phase or a previous write operation. 1329 */ 1330 int 1331 soc_i2c_write_one_byte(int unit, uint8 data) 1332 { 1333 soc_i2c_bus_t *i2cbus; 1334 1335 i2cbus = I2CBUS(unit); 1336 /* Make sure we're in a write-ready state. */ 1337 if (i2cbus->opcode != SOC_I2C_TX) { 1338 return SOC_E_INTERNAL; 1339 } 1340 1341 soc_i2c_pci_write(unit, CMIC_I2C_DATA, data); 1342 soc_i2c_next_bus_phase(unit, 1); 1343 if (SOC_E_TIMEOUT == soc_i2c_wait(unit)) { 1344 LOG_INFO(BSL_LS_SOC_I2C, 1345 (BSL_META_U(unit, 1346 "soc_i2c_write_one_byte: u=%d data=0x%x" 1347 " DEVICE TIMEOUT!\n"), 1348 unit, data)); 1349 return SOC_E_BUSY; 1350 } 1351 return SOC_E_NONE; 1352 } 1353 1354 1355 /* 1356 * Function: soc_i2c_read_bytes 1357 * 1358 * Purpose: Read bytes from the last addressed slave device. 1359 * 1360 * Parameters: 1361 * unit - StrataSwitch device number or I2C bus number 1362 * data - address to place data byte received from slave 1363 * len - (in) number of bytes to read from slave. 1364 * (out) number of bytes actually read. 1365 * ack_last_byte - 1366 * if set, an ACK will automatically be sent by the 1367 * controller for the last byte read from the slave. 1368 * If not set, a NAK is pulsed when the last byte 1369 * has been received. Set when a master would like 1370 * to signify that this block read is NOT the last 1371 * data to be read from the slave. 1372 * 1373 * Returns: 1374 * SOC_E_NONE if the device was contacted and the operation 1375 * succeeded. 1376 * SOC_E_INTERNAL - Unexpected or internal error 1377 * SOC_E_TIMEOUT if the device timed out. 1378 * 1379 * Notes: 1380 * The ack_last_byte field only affects the last byte; this 1381 * allows support for the following I2C byte read transactions: 1382 * 1383 * START Addr Rd [ACK] [Data] ACK REPSTART ... 1384 * START Addr Rd [ACK] [Data] NAK REPSTART ... 1385 * 1386 * START Addr Rd [ACK] [Data] ACK [DATA] ACK STOP 1387 * START Addr Rd [ACK] [Data] ACK [DATA] NAK STOP 1388 * 1389 * We always transmit an ACK when two or more bytes 1390 * remain to be read, i.e. the non-last byte(s). 1391 * 1392 * Before this routine can be used, the I2C controller must 1393 * be in a read-ready state, i.e. following a START-READ_SADDR 1394 * phase or a previous read operation. 1395 */ 1396 int 1397 soc_i2c_read_bytes(int unit, uint8* data, int* len, int ack_last_byte) 1398 { 1399 int ack; 1400 uint32 rx, nread, nbytes; 1401 uint8* ptr; 1402 soc_i2c_bus_t *i2cbus; 1403 soc_i2c_status_t s; 1404 1405 if (!len || (*len <= 0)) { 1406 return SOC_E_PARAM; 1407 } 1408 1409 i2cbus = I2CBUS(unit); 1410 /* Make sure we're in a read-ready state. */ 1411 if (i2cbus->opcode != SOC_I2C_RX) { 1412 return SOC_E_INTERNAL; 1413 } 1414 1415 nbytes = *len; 1416 ptr = data; 1417 1418 /* Read up to len bytes ... */ 1419 *len = 0; 1420 /* 1421 * Some sort of start condition and slave address has been sent 1422 * by the I2C controller (master) and ACK'd by the slave device, 1423 * or one or more bytes have already been read. 1424 * The I2C controller is now in a state that will perform byte 1425 * reads until a stop or repeat start is explicitly initiated. 1426 * We'll only do the requested number of byte reads here, and 1427 * leave it up to the calling code to do the stop or start. 1428 */ 1429 for (nread = 0; nread < nbytes; nread++) { 1430 /* ACK the byte we're about to read? */ 1431 if (!ack_last_byte) { 1432 ack = (nread == nbytes - 1 ? 0 : 1); 1433 } else { 1434 ack = 1; 1435 } 1436 1437 /* Initiate the next byte read. */ 1438 soc_i2c_next_bus_phase(unit, ack); 1439 1440 if (SOC_E_TIMEOUT == soc_i2c_wait(unit)) { 1441 LOG_INFO(BSL_LS_SOC_I2C, 1442 (BSL_META_U(unit, 1443 "soc_i2c_read_bytes: u=%d data=0x%x state=0x%x:[%s]\n"), 1444 unit, 0, soc_i2c_stat(unit), 1445 soc_i2c_status_message(soc_i2c_stat(unit)))); 1446 return SOC_E_TIMEOUT; 1447 } 1448 1449 /* Store the read data byte, or deal with error condition. */ 1450 if ( ((s=soc_i2c_stat(unit)) == SOC_I2C_DATA_BYTE_RX_ACK_TX) || 1451 (s == SOC_I2C_DATA_BYTE_RX_NO_ACK_TX) ) { 1452 1453 i2cbus->opcode = SOC_I2C_RX; 1454 rx = soc_i2c_pci_read(unit, CMIC_I2C_DATA); 1455 rx &= CMIC_I2C_REG_MASK; 1456 1457 *ptr++ = (uint8) rx ; 1458 *len = *len + 1; 1459 } else { 1460 return SOC_E_INTERNAL; 1461 } 1462 } /* read nbytes bytes */ 1463 1464 return SOC_E_NONE; 1465 } 1466 1467 /* 1468 * Function: soc_i2c_read_one_byte 1469 * 1470 * Purpose: Read one byte from the last addressed slave device, 1471 * with ACK/NACK control. 1472 * 1473 * Parameters: 1474 * unit - StrataSwitch device number or I2C bus number 1475 * data - address to place data byte received from slave 1476 * ack - if set, an ACK will automatically be sent by the 1477 * controller when the slave sends the data. If not 1478 * set, a NAK is pulsed when the byte has been received. 1479 * This is set when a master would like to signify 1480 * that this is NOT the last byte being read from the 1481 * slave. 1482 * 1483 * Returns: 1484 * SOC_E_NONE if the device was contacted and the operation 1485 * succeeded. 1486 * SOC_E_INTERNAL - Unexpected or internal error 1487 * SOC_E_TIMEOUT if the device timed out. 1488 * 1489 * Notes: 1490 * Before this routine can be used, the I2C controller must 1491 * be in a read-ready state, i.e. following a START-READ_SADDR 1492 * phase or a previous read operation. 1493 */ 1494 int 1495 soc_i2c_read_one_byte(int unit, uint8* data, int ack) 1496 { 1497 int nbytes = 1; 1498 1499 return soc_i2c_read_bytes(unit, data, &nbytes, ack); 1500 } 1501 1502 /* 1503 * 1504 * Function: soc_i2c_read_short 1505 * 1506 * Purpose: Read two bytes, interpret as a single short value 1507 * (LSbyte then MSbyte), with ACK/NACK control. 1508 * 1509 * Algorithm: [Read_LSbyte] [A] [Read_MSbyte] [ack_last_byte] 1510 * 1511 * Parameters: 1512 * unit - StrataSwitch device number or I2C bus number 1513 * value - 16 bit device-specific data value to read. 1514 * ack_last_byte - 1515 * if set, an ACK will automatically be sent by the 1516 * controller for the second byte read from the slave. 1517 * If not set, a NAK is pulsed when the second byte 1518 * has been received. Set when a master would like 1519 * to signify that this short read is NOT the last 1520 * data to be read from the slave. 1521 * 1522 * Returns: 1523 * 1524 * SOC_E_TIMEOUT - the device can not be contacted or is offline. 1525 * SOC_E_INTERNAL - Unexpected or internal error 1526 * SOC_E_NONE - no error, operation succeeded. 1527 * 1528 * Notes: 1529 * none 1530 */ 1531 int 1532 soc_i2c_read_short(int unit, uint16* val, int ack_last_byte) 1533 { 1534 uint8 a0, a1; 1535 uint32 rx; 1536 soc_i2c_bus_t *i2cbus; 1537 soc_i2c_status_t s; 1538 1539 i2cbus = I2CBUS(unit); 1540 /* Make sure we're in a read-ready state. */ 1541 if (i2cbus->opcode != SOC_I2C_RX) { 1542 return SOC_E_INTERNAL; 1543 } 1544 1545 a0 = a1 = 0; 1546 1547 /* Read first byte (LSbyte); always ACK first byte. */ 1548 soc_i2c_next_bus_phase(unit, 1); 1549 1550 if (SOC_E_TIMEOUT == soc_i2c_wait(unit)) { 1551 LOG_INFO(BSL_LS_SOC_I2C, 1552 (BSL_META_U(unit, 1553 "soc_i2c_read_short: u=%d data=0x%x state=0x%x:[%s]\n"), 1554 unit, 0, soc_i2c_stat(unit), 1555 soc_i2c_status_message(soc_i2c_stat(unit)))); 1556 return SOC_E_TIMEOUT; 1557 } 1558 1559 /* 1560 * Read/store the LSB, then read the MSbyte. 1561 * Else deal with any error condition. 1562 */ 1563 if ( ((s=soc_i2c_stat(unit)) == SOC_I2C_DATA_BYTE_RX_ACK_TX) || 1564 (s == SOC_I2C_DATA_BYTE_RX_NO_ACK_TX) ) { 1565 1566 rx = soc_i2c_pci_read(unit, CMIC_I2C_DATA); 1567 rx &= CMIC_I2C_REG_MASK; 1568 1569 a0 = (uint8) rx ; 1570 1571 /* Read next byte (MSbyte), setting ACK/NACK as requested. */ 1572 soc_i2c_next_bus_phase(unit, (ack_last_byte ? 1 : 0)); 1573 1574 /* Wait for next state change */ 1575 if (SOC_E_TIMEOUT == soc_i2c_wait(unit)) { 1576 LOG_INFO(BSL_LS_SOC_I2C, 1577 (BSL_META_U(unit, 1578 "soc_i2c_read_short: u=%d data=0x%x state=0x%x:[%s]\n"), 1579 unit, (uint32)a1, soc_i2c_stat(unit), 1580 soc_i2c_status_message(soc_i2c_stat(unit)))); 1581 return SOC_E_TIMEOUT; 1582 } 1583 } else { 1584 return SOC_E_INTERNAL; 1585 } 1586 1587 /* Read/store the MSB, or deal with error condition */ 1588 if ( ((s=soc_i2c_stat(unit)) == SOC_I2C_DATA_BYTE_RX_ACK_TX) || 1589 (s == SOC_I2C_DATA_BYTE_RX_NO_ACK_TX) ) { 1590 rx = soc_i2c_pci_read(unit, CMIC_I2C_DATA); 1591 rx &= CMIC_I2C_REG_MASK; 1592 1593 a1 = (uint8) rx ; 1594 } else { 1595 return SOC_E_INTERNAL; 1596 } 1597 1598 *val= (a1 << 8) | a0; 1599 1600 return SOC_E_NONE; 1601 } 1602 1603 1604 /* 1605 * Function: soc_i2c_stop 1606 * 1607 * Purpose: Generate stop condition on the I2C bus. This routine is 1608 * used to signal the end of a data transfer and releases 1609 * the bus according to the I2C protocol. 1610 * 1611 * Parameters: 1612 * unit - StrataSwitch device number or I2C bus number 1613 * Returns: 1614 * SOC_E_NONE - no error, one can always issue stop. 1615 * Notes: 1616 * none 1617 */ 1618 int 1619 soc_i2c_stop(int unit) 1620 { 1621 I2CBUS(unit)->opcode = SOC_I2C_STOP; 1622 soc_write_i2c_stop_bits(unit); 1623 return SOC_E_NONE; 1624 } 1625 1626 /* 1627 * Function: soc_i2c_ack_poll 1628 * 1629 * Purpose: Many devices will require a polling acknowledge cycle to 1630 * determine if the device is available for IO. Usually, this 1631 * means that a START condition is generated, along with a read 1632 * or write form of the slave device address, and then we wait 1633 * until the device responds with an ACK. When this occurs, we 1634 * issue a STOP, to free the bus, and return since the device 1635 * is ready for IO. 1636 * 1637 * Parameters: 1638 * unit - StrataSwitch device number or I2C bus number 1639 * bus_addr - device bus address byte, with r/w bit set for data direction. 1640 * max_polls - number of times to attempt the operation. 1641 * 1642 * Returns: 1643 * Number of Poll operations required to contact device, or 1644 * maxpolls if the device is not online or responding. 1645 * 1646 * Notes: Typically, we poll a specified IO address with the 1647 * read/write bit set to determine if the device is ready 1648 * for reading or writing. When we receive an ACK for that 1649 * function (Read/Write), the device is ready for IO. The 1650 * data direction (or function) is determined by the address 1651 * bits (see SOC_I2C_TX_ADDR/SOC_I2C_RX_ADDR) macros. 1652 */ 1653 int 1654 soc_i2c_ack_poll(int unit, i2c_bus_addr_t bus_addr, int maxpolls) 1655 { 1656 int i = maxpolls; 1657 1658 while (--i > 0 && (soc_i2c_start(unit, bus_addr) < 0)) { 1659 /* NOP */ 1660 } 1661 soc_i2c_stop(unit); 1662 return maxpolls - i; 1663 } 1664 1665 /* 1666 * Data: soc_i2c_message[] 1667 * Purpose: Human-readable status messages for the I2C bus controller. 1668 * 1669 * Notes: there is a one-one-correspondence between the order of 1670 * these message definitions here and the stat register 1671 * meaning definitions in i2c.h (do not re-order). 1672 */ 1673 STATIC struct i2c_status_info{ 1674 soc_i2c_status_t status; 1675 char *msg; 1676 } soc_i2c_message[] = { 1677 {SOC_I2C_BERR, 1678 "Bus Error"}, 1679 {SOC_I2C_START_TX, 1680 "START Condition Transmitted"}, 1681 {SOC_I2C_REP_START_TX, 1682 "Repeated START Condition Transmitted"}, 1683 {SOC_I2C_ADDR_WR_BIT_TX_ACK_RX, 1684 "Address and Write Bit Transmitted, ACK Received"}, 1685 {SOC_I2C_ADDR_WR_BIT_TX_NO_ACK_RX, 1686 "Address and Write Bit Transmitted, NO ACK received"}, 1687 {SOC_I2C_DATA_BYTE_TX_ACK_RX, 1688 "Data Byte Transmitted, ACK Received"}, 1689 {SOC_I2C_DATA_BYTE_TX_NO_ACK_RX, 1690 "Data Byte Transmitted, NO ACK Received"}, 1691 {SOC_I2C_ARB_LOST, 1692 "Arbitration Lost in Address or Data Byte"}, 1693 {SOC_I2C_ADDR_RD_BIT_TX_ACK_RX, 1694 "Address and Read Bit Transmitted, ACK Received"}, 1695 {SOC_I2C_ADDR_RD_BIT_TX_NO_ACK_RX, 1696 "Address and Read Bit Transmitted, NO ACK Received"}, 1697 {SOC_I2C_DATA_BYTE_RX_ACK_TX, 1698 "Data Byte Received, ACK Transmitted"}, 1699 {SOC_I2C_DATA_BYTE_RX_NO_ACK_TX, 1700 "Data Byte Received, NO ACK Transmitted"}, 1701 {SOC_I2C_SADDR_RX_WR_BIT_RX_ACK_TX, 1702 "Slave Address and Write Bit Received, ACK Transmitted"}, 1703 {SOC_I2C_ARB_LOST_SADDR_RX_WR_BIT_RX_ACK_TX, 1704 "Arbitration Lost in Address Phase, Slave Address and Write" 1705 " Bit Received, ACK Transmitted"}, 1706 {SOC_I2C_GC_ADDR_RX_ACK_TX, 1707 "General Call Address Received, ACK Transmitted"}, 1708 {SOC_I2C_ARB_LOST_GC_ADDR_RX_ACK_TX, 1709 "Arbitration Lost in Address Phase, General Call Address " 1710 "Received, ACK Transmitted"}, 1711 {SOC_I2C_DATA_BYTE_RX_AFTER_SADDR_RX_ACK_TX, 1712 "Data Byte Received after Slave Address Received, " 1713 "ACK Transmitted"}, 1714 {SOC_I2C_DATA_BYTE_RX_AFTER_SADDR_RX_NO_ACK_TX, 1715 "Data Byte Received after Slave Address Received, " 1716 "NO ACK Transmitted"}, 1717 {SOC_I2C_DATA_BYTE_RX_AFTER_GC_ADDR_RX_ACK_TX, 1718 "Data Byte Received after General Call Address Received," 1719 " ACK Transmitted"}, 1720 {SOC_I2C_DATA_BYTE_RX_AFTER_GC_ADDR_RX_NO_ACK_TX, 1721 "Data Byte Received after General Call Address Received," 1722 " NO ACK Transmitted"}, 1723 {SOC_I2C_STOP_OR_REP_START_COND_RX_IN_SLAVE_MODE, 1724 "STOP or Repeated START Condition Received in Slave Mode"}, 1725 {SOC_I2C_SADDR_RX_RD_BIT_RX_ACK_TX, 1726 "Slave Address and Read Bit Received, ACK Transmitted"}, 1727 {SOC_I2C_ARB_LOST_IN_ADDR_PHASE_SADDR_RX_RD_BIT_RX_ACK_TX, 1728 "Arbitration Lost in Address Phase, Slave Address and Read Bit" 1729 " Received, ACK Transmitted"}, 1730 {SOC_I2C_SM_DATA_BYTE_TX_ACK_RX, 1731 "Data Byte Transmitted in Slave Mode, ACK Received"}, 1732 {SOC_I2C_SM_DATA_BYTE_TX_NO_ACK_RX, 1733 "Data Byte Transmitted in Slave Mode, NO ACK Received"}, 1734 {SOC_I2C_SM_LAST_BYTE_TX_ACK_RX, 1735 "Last Byte Transmitted in Slave Mode, ACK Received"}, 1736 {SOC_I2C_2ND_ADDR_BYTE_TX_WR_BIT_TX_ACK_RX, 1737 "Second Address Byte and Write Bit Transmitted, ACK Received"}, 1738 {SOC_I2C_2ND_ADDR_BYTE_TX_WR_BIT_TX_NO_ACK_RX, 1739 "Second Address Byte and Write Bit Transmitted, NO ACK Received"}, 1740 {SOC_I2C_2ND_ADDR_BYTE_TX_RD_BIT_TX_ACK_RX, 1741 "Second Address Byte and Read Bit Transmitted, ACK Received"}, 1742 {SOC_I2C_2ND_ADDR_BYTE_TX_RD_BIT_TX_NO_ACK_RX, 1743 "Second Address Byte and Read Bit Transmitted, NO AC Received"}, 1744 {SOC_I2C_UNDEFINED,"ERROR: Undefined status code!"}, 1745 {SOC_I2C_NO_STATUS,"No relevant status Information (IFLG=0)"} 1746 } ; 1747 #define num_soc_i2c_messages COUNTOF(soc_i2c_message) 1748 1749 /* 1750 * Function: soc_i2c_status_message 1751 * 1752 * Purpose: This routine decodes the current I2C bus status code and 1753 * return human-readable bus status for last I2C operation 1754 * 1755 * Returns: human readable character string telling what the 1756 * current status of the I2C bus is, NULL on invalid 1757 * status code. 1758 * 1759 * Notes: 1760 * See also: soc_i2c_stat (for getting current status value). 1761 */ 1762 char * 1763 soc_i2c_status_message(soc_i2c_status_t status) 1764 { 1765 int idx = status / 8; 1766 1767 if (idx >= num_soc_i2c_messages) { 1768 return NULL; 1769 } 1770 if (status < SOC_I2C_BERR || status > SOC_I2C_NUM_STATUS_CODES) { 1771 return NULL; 1772 } 1773 if (status == soc_i2c_message[idx].status) { 1774 return soc_i2c_message[idx].msg; 1775 } 1776 return NULL; 1777 } 1778 1779 /* 1780 * Data: i2c_freq_tab 1781 * 1782 * Purpose: Frequency Table. I2C Bus controller frequencies (k0) 1783 * for all values M{0:3},N{0:2}, in_freq=50Mhz, 1784 * BUS_DIVIDER = 10 1785 * 1786 * Notes: 1787 * Algorithm for I2C bus clock frequency. 1788 * 1789 * out_freq = in_freq / ( (M_Val + 1) * 1790 * pow( 2, N_Val + 1 )) / BUS_DIVIDER; 1791 */ 1792 static struct freq_tab_s{ 1793 uint8 m; 1794 uint8 n; 1795 uint32 speed; 1796 char* name; 1797 } i2c_freq_tab[]={ 1798 { 0, 0, 2500000, "2.50MHz"}, /* 2.50MHz */ 1799 { 1, 0, 1250000, "1.25MHz"}, /* 1.25MHz */ 1800 { 0, 1, 1250000, "1.25MHz"}, /* 1.25MHz */ 1801 { 2, 0, 833333, "833.33kHz"}, /* 833.33KHz */ 1802 { 3, 0, 625000, "625.00kHz"}, /* 625.00KHz */ 1803 { 1, 1, 625000, "625.00kHz"}, /* 625.00KHz */ 1804 { 0, 2, 625000, "625.00kHz"}, /* 625.00KHz */ 1805 { 4, 0, 500000, "500.00kHz"}, /* 500.00KHz */ 1806 { 5, 0, 416666, "416.67kHz"}, /* 416.67KHz */ 1807 { 2, 1, 416666, "416.67kHz"}, /* 416.67KHz */ 1808 { 6, 0, 357142, "357.14kHz"}, /* 357.14KHz */ 1809 { 7, 0, 312500, "312.50kHz"}, /* 312.50KHz */ 1810 { 3, 1, 312500, "312.50kHz"}, /* 312.50KHz */ 1811 { 1, 2, 312500, "312.50kHz"}, /* 312.50KHz */ 1812 { 0, 3, 312500, "312.50kHz"}, /* 312.50KHz */ 1813 { 8, 0, 277777, "277.78kHz"}, /* 277.78KHz */ 1814 { 9, 0, 250000, "250.00kHz"}, /* 250.00KHz */ 1815 { 4, 1, 250000, "250.00kHz"}, /* 250.00KHz */ 1816 { 10, 0, 227272, "227.27kHz"}, /* 227.27KHz */ 1817 { 5, 1, 208333, "208.33kHz"}, /* 208.33KHz */ 1818 { 2, 2, 208333, "208.33kHz"}, /* 208.33KHz */ 1819 { 11, 0, 208333, "208.33kHz"}, /* 208.33KHz */ 1820 { 12, 0, 192307, "192.31kHz"}, /* 192.31KHz */ 1821 { 6, 1, 178571, "178.57kHz"}, /* 178.57KHz */ 1822 { 13, 0, 178571, "178.57kHz"}, /* 178.57KHz */ 1823 { 14, 0, 166666, "166.67kHz"}, /* 166.67KHz */ 1824 { 7, 1, 156250, "156.25kHz"}, /* 156.25KHz */ 1825 { 3, 2, 156250, "156.25kHz"}, /* 156.25KHz */ 1826 { 15, 0, 156250, "156.25kHz"}, /* 156.25KHz */ 1827 { 1, 3, 156250, "156.25kHz"}, /* 156.25KHz */ 1828 { 0, 4, 156250, "156.25kHz"}, /* 156.25KHz */ 1829 { 8, 1, 138888, "138.89kHz"}, /* 138.89KHz */ 1830 { 9, 1, 125000, "125.00kHz"}, /* 125.00KHz */ 1831 { 4, 2, 125000, "125.00kHz"}, /* 125.00KHz */ 1832 { 10, 1, 113636, "113.64kHz"}, /* 113.64KHz */ 1833 { 5, 2, 104166, "104.17kHz"}, /* 104.17KHz */ 1834 { 2, 3, 104166, "104.17kHz"}, /* 104.17KHz */ 1835 { 11, 1, 104166, "104.17kHz"}, /* 104.17KHz */ 1836 { 12, 1, 96153, "96.15kHz"}, /* 96.15KHz */ 1837 { 6, 2, 89285, "89.28kHz"}, /* 89.28KHz */ 1838 { 13, 1, 89285, "89.28kHz"}, /* 89.28KHz */ 1839 { 14, 1, 83333, "83.33kHz"}, /* 83.33KHz */ 1840 { 7, 2, 78125, "78.12kHz"}, /* 78.12KHz */ 1841 { 3, 3, 78125, "78.12kHz"}, /* 78.12KHz */ 1842 { 15, 1, 78125, "78.12kHz"}, /* 78.12KHz */ 1843 { 1, 4, 78125, "78.12kHz"}, /* 78.12KHz */ 1844 { 0, 5, 78125, "78.12kHz"}, /* 78.12KHz */ 1845 { 8, 2, 69444, "69.44kHz"}, /* 69.44KHz */ 1846 { 9, 2, 62500, "62.50kHz"}, /* 62.50KHz */ 1847 { 4, 3, 62500, "62.50kHz"}, /* 62.50KHz */ 1848 { 10, 2, 56818, "56.82kHz"}, /* 56.82KHz */ 1849 { 5, 3, 52083, "52.08kHz"}, /* 52.08KHz */ 1850 { 2, 4, 52083, "52.08kHz"}, /* 52.08KHz */ 1851 { 11, 2, 52083, "52.08kHz"}, /* 52.08KHz */ 1852 { 12, 2, 48076, "48.08kHz"}, /* 48.08KHz */ 1853 { 6, 3, 44642, "44.64kHz"}, /* 44.64KHz */ 1854 { 13, 2, 44642, "44.64kHz"}, /* 44.64KHz */ 1855 { 14, 2, 41666, "41.67kHz"}, /* 41.67KHz */ 1856 { 7, 3, 39062, "39.06kHz"}, /* 39.06KHz */ 1857 { 3, 4, 39062, "39.06kHz"}, /* 39.06KHz */ 1858 { 15, 2, 39062, "39.06kHz"}, /* 39.06KHz */ 1859 { 1, 5, 39062, "39.06kHz"}, /* 39.06KHz */ 1860 { 0, 6, 39062, "39.06kHz"}, /* 39.06KHz */ 1861 { 8, 3, 34722, "34.72kHz"}, /* 34.72KHz */ 1862 { 9, 3, 31250, "31.25kHz"}, /* 31.25KHz */ 1863 { 4, 4, 31250, "31.25kHz"}, /* 31.25KHz */ 1864 { 10, 3, 28409, "28.41kHz"}, /* 28.41KHz */ 1865 { 5, 4, 26041, "26.04kHz"}, /* 26.04KHz */ 1866 { 2, 5, 26041, "26.04kHz"}, /* 26.04KHz */ 1867 { 11, 3, 26041, "26.04kHz"}, /* 26.04KHz */ 1868 { 12, 3, 24038, "24.04kHz"}, /* 24.04KHz */ 1869 { 6, 4, 22321, "22.32kHz"}, /* 22.32KHz */ 1870 { 13, 3, 22321, "22.32kHz"}, /* 22.32KHz */ 1871 { 14, 3, 20833, "20.83kHz"}, /* 20.83KHz */ 1872 { 7, 4, 19531, "19.53kHz"}, /* 19.53KHz */ 1873 { 3, 5, 19531, "19.53kHz"}, /* 19.53KHz */ 1874 { 15, 3, 19531, "19.53kHz"}, /* 19.53KHz */ 1875 { 1, 6, 19531, "19.53kHz"}, /* 19.53KHz */ 1876 { 0, 7, 19531, "19.53kHz"}, /* 19.53KHz */ 1877 { 8, 4, 17361, "17.36kHz"}, /* 17.36KHz */ 1878 { 9, 4, 15625, "15.62kHz"}, /* 15.62KHz */ 1879 { 4, 5, 15625, "15.62kHz"}, /* 15.62KHz */ 1880 { 10, 4, 14204, "14.20kHz"}, /* 14.20KHz */ 1881 { 5, 5, 13020, "13.02kHz"}, /* 13.02KHz */ 1882 { 2, 6, 13020, "13.02kHz"}, /* 13.02KHz */ 1883 { 11, 4, 13020, "13.02kHz"}, /* 13.02KHz */ 1884 { 12, 4, 12019, "12.02kHz"}, /* 12.02KHz */ 1885 { 6, 5, 11160, "11.16kHz"}, /* 11.16KHz */ 1886 { 13, 4, 11160, "11.16kHz"}, /* 11.16KHz */ 1887 { 14, 4, 10416, "10.42kHz"}, /* 10.42KHz */ 1888 { 7, 5, 9765, "9.77kHz"}, /* 9.77KHz */ 1889 { 3, 6, 9765, "9.77kHz"}, /* 9.77KHz */ 1890 { 15, 4, 9765, "9.77kHz"}, /* 9.77KHz */ 1891 { 1, 7, 9765, "9.77kHz"}, /* 9.77KHz */ 1892 { 8, 5, 8680, "8.68kHz"}, /* 8.68KHz */ 1893 { 9, 5, 7812, "7.81kHz"}, /* 7.81KHz */ 1894 { 4, 6, 7812, "7.81kHz"}, /* 7.81KHz */ 1895 { 10, 5, 7102, "7.10kHz"}, /* 7.10KHz */ 1896 { 5, 6, 6510, "6.51kHz"}, /* 6.51KHz */ 1897 { 2, 7, 6510, "6.51kHz"}, /* 6.51KHz */ 1898 { 11, 5, 6510, "6.51kHz"}, /* 6.51KHz */ 1899 { 12, 5, 6009, "6.01kHz"}, /* 6.01KHz */ 1900 { 6, 6, 5580, "5.58kHz"}, /* 5.58KHz */ 1901 { 13, 5, 5580, "5.58kHz"}, /* 5.58KHz */ 1902 { 14, 5, 5208, "5.21kHz"}, /* 5.21KHz */ 1903 { 7, 6, 4882, "4.88kHz"}, /* 4.88KHz */ 1904 { 3, 7, 4882, "4.88kHz"}, /* 4.88KHz */ 1905 { 15, 5, 4882, "4.88kHz"}, /* 4.88KHz */ 1906 { 8, 6, 4340, "4.34kHz"}, /* 4.34KHz */ 1907 { 9, 6, 3906, "3.91kHz"}, /* 3.91KHz */ 1908 { 4, 7, 3906, "3.91kHz"}, /* 3.91KHz */ 1909 { 10, 6, 3551, "3.55kHz"}, /* 3.55KHz */ 1910 { 5, 7, 3255, "3.25kHz"}, /* 3.25KHz */ 1911 { 11, 6, 3255, "3.25kHz"}, /* 3.25KHz */ 1912 { 12, 6, 3004, "3.00kHz"}, /* 3.00KHz */ 1913 { 6, 7, 2790, "2.79kHz"}, /* 2.79KHz */ 1914 { 13, 6, 2790, "2.79kHz"}, /* 2.79KHz */ 1915 { 14, 6, 2604, "2.60kHz"}, /* 2.60KHz */ 1916 { 7, 7, 2441, "2.44kHz"}, /* 2.44KHz */ 1917 { 15, 6, 2441, "2.44kHz"}, /* 2.44KHz */ 1918 { 8, 7, 2170, "2.17kHz"}, /* 2.17KHz */ 1919 { 9, 7, 1953, "1.95kHz"}, /* 1.95KHz */ 1920 { 10, 7, 1775, "1.77kHz"}, /* 1.77KHz */ 1921 { 11, 7, 1627, "1.63kHz"}, /* 1.63KHz */ 1922 { 12, 7, 1502, "1.50kHz"}, /* 1.50KHz */ 1923 { 13, 7, 1395, "1.40kHz"}, /* 1.40KHz */ 1924 { 14, 7, 1302, "1.30kHz"}, /* 1.30KHz */ 1925 { 15, 7, 1220, "1.22kHz"} /* 1.22KHz */ 1926 }; 1927 #define freqtab_sz COUNTOF(i2c_freq_tab) 1928 1929 /* 1930 * Data: i2c_xgs3_freq_tab 1931 * 1932 * Purpose: Frequency Table. I2C Bus controller frequencies (k0) 1933 * for all values M{0:3},N{0:2}, in_freq=5Mhz, 1934 * BUS_DIVIDER = 10 1935 * 1936 * Notes: 1937 * Algorithm for I2C bus clock frequency. 1938 * 1939 * out_freq = in_freq / ( (M_Val + 1) * 1940 * pow( 2, N_Val + 1 )) / BUS_DIVIDER; 1941 */ 1942 static struct xgs3_freq_tab_s{ 1943 uint8 m; 1944 uint8 n; 1945 uint32 speed; 1946 char* name; 1947 } i2c_xgs3_freq_tab[]={ 1948 { 0, 0, 250000, "250.00kHz"}, /* 250.00KHz */ 1949 { 1, 0, 125000, "125.00kHz"}, /* 125.00KHz */ 1950 { 0, 1, 125000, "125.00kHz"}, /* 125.00KHz */ 1951 { 2, 0, 83333, "83.33kHz"}, /* 83.33KHz */ 1952 { 3, 0, 62500, "62.50kHz"}, /* 62.50KHz */ 1953 { 0, 2, 62500, "62.50kHz"}, /* 62.50KHz */ 1954 { 4, 0, 50000, "50.00kHz"}, /* 50.00KHz */ 1955 { 5, 0, 41667, "41.67kHz"}, /* 41.67KHz */ 1956 { 2, 1, 41667, "41.67kHz"}, /* 41.67KHz */ 1957 { 6, 0, 35714, "35.71kHz"}, /* 35.71KHz */ 1958 { 7, 0, 31250, "31.25kHz"}, /* 31.25KHz */ 1959 { 0, 3, 31250, "31.25kHz"}, /* 31.25KHz */ 1960 { 3, 1, 31250, "31.25kHz"}, /* 31.25KHz */ 1961 { 1, 2, 31250, "31.25kHz"}, /* 31.25KHz */ 1962 { 8, 0, 27778, "27.78kHz"}, /* 27.78KHz */ 1963 { 9, 0, 25000, "25.00kHz"}, /* 25.00KHz */ 1964 { 4, 1, 25000, "25.00kHz"}, /* 25.00KHz */ 1965 { 10, 0, 22727, "22.73kHz"}, /* 22.73KHz */ 1966 { 2, 2, 20833, "20.83kHz"}, /* 20.83KHz */ 1967 { 5, 1, 20833, "20.83kHz"}, /* 20.83KHz */ 1968 { 11, 0, 20833, "20.83kHz"}, /* 20.83KHz */ 1969 { 12, 0, 19231, "19.23kHz"}, /* 19.23KHz */ 1970 { 13, 0, 17857, "17.86kHz"}, /* 17.86KHz */ 1971 { 6, 1, 17857, "17.86kHz"}, /* 17.86KHz */ 1972 { 14, 0, 16667, "16.67kHz"}, /* 16.67KHz */ 1973 { 15, 0, 15625, "15.63kHz"}, /* 15.63KHz */ 1974 { 0, 4, 15625, "15.63kHz"}, /* 15.63KHz */ 1975 { 3, 2, 15625, "15.63kHz"}, /* 15.63KHz */ 1976 { 7, 1, 15625, "15.63kHz"}, /* 15.63KHz */ 1977 { 1, 3, 15625, "15.63kHz"}, /* 15.63KHz */ 1978 { 16, 0, 14706, "14.71kHz"}, /* 14.71KHz */ 1979 { 17, 0, 13889, "13.89kHz"}, /* 13.89KHz */ 1980 { 8, 1, 13889, "13.89kHz"}, /* 13.89KHz */ 1981 { 18, 0, 13158, "13.16kHz"}, /* 13.16KHz */ 1982 { 19, 0, 12500, "12.50kHz"}, /* 12.50KHz */ 1983 { 4, 2, 12500, "12.50kHz"}, /* 12.50KHz */ 1984 { 9, 1, 12500, "12.50kHz"}, /* 12.50KHz */ 1985 { 20, 0, 11905, "11.91kHz"}, /* 11.91KHz */ 1986 { 21, 0, 11364, "11.36kHz"}, /* 11.36KHz */ 1987 { 10, 1, 11364, "11.36kHz"}, /* 11.36KHz */ 1988 { 22, 0, 10870, "10.87kHz"}, /* 10.87KHz */ 1989 { 23, 0, 10417, "10.42kHz"}, /* 10.42KHz */ 1990 { 2, 3, 10417, "10.42kHz"}, /* 10.42KHz */ 1991 { 5, 2, 10417, "10.42kHz"}, /* 10.42KHz */ 1992 { 11, 1, 10417, "10.42kHz"}, /* 10.42KHz */ 1993 { 24, 0, 10000, "10.00kHz"}, /* 10.00KHz */ 1994 { 25, 0, 9615, "9.62kHz"}, /* 9.62KHz */ 1995 { 12, 1, 9615, "9.62kHz"}, /* 9.62KHz */ 1996 { 26, 0, 9259, "8.93kHz"}, /* 8.93KHz */ 1997 { 27, 0, 8929, "8.93kHz"}, /* 8.93KHz */ 1998 { 13, 1, 8929, "8.93kHz"}, /* 8.93KHz */ 1999 { 6, 2, 8929, "8.93kHz"}, /* 8.93KHz */ 2000 { 28, 0, 8621, "8.62kHz"}, /* 8.62KHz */ 2001 { 29, 0, 8333, "8.33kHz"}, /* 8.33KHz */ 2002 { 30, 0, 8065, "8.07kHz"}, /* 8.07KHz */ 2003 { 31, 0, 7813, "7.81kHz"}, /* 7.81KHz */ 2004 { 0, 5, 7813, "7.81kHz"}, /* 7.81KHz */ 2005 { 3, 3, 7813, "7.81kHz"}, /* 7.81KHz */ 2006 { 7, 2, 7813, "7.81kHz"}, /* 7.81KHz */ 2007 { 1, 4, 7813, "7.81kHz"}, /* 7.81KHz */ 2008 { 32, 0, 7576, "7.58kHz"}, /* 7.58KHz */ 2009 { 33, 0, 7353, "7.35kHz"}, /* 7.35KHz */ 2010 { 34, 0, 7143, "7.14kHz"}, /* 7.14KHz */ 2011 { 35, 0, 6944, "6.94kHz"}, /* 6.94KHz */ 2012 { 8, 2, 6944, "6.94kHz"}, /* 6.94KHz */ 2013 { 36, 0, 6757, "6.76kHz"}, /* 6.76KHz */ 2014 { 37, 0, 6579, "6.58kHz"}, /* 6.58KHz */ 2015 { 38, 0, 6410, "6.41kHz"}, /* 6.41KHz */ 2016 { 39, 0, 6250, "6.25kHz"}, /* 6.25KHz */ 2017 { 4, 3, 6250, "6.25kHz"}, /* 6.25KHz */ 2018 { 9, 2, 6250, "6.25kHz"}, /* 6.25KHz */ 2019 { 40, 0, 6098, "6.10kHz"}, /* 6.10KHz */ 2020 { 41, 0, 5952, "5.95kHz"}, /* 5.95KHz */ 2021 { 42, 0, 5814, "5.81kHz"}, /* 5.81KHz */ 2022 { 43, 0, 5682, "5.68kHz"}, /* 5.68KHz */ 2023 { 10, 2, 5682, "5.68kHz"}, /* 5.68KHz */ 2024 { 44, 0, 5556, "5.56kHz"}, /* 5.56KHz */ 2025 { 45, 0, 5435, "5.44kHz"}, /* 5.44KHz */ 2026 { 46, 0, 5319, "5.32kHz"}, /* 5.32KHz */ 2027 { 47, 0, 5208, "5.21kHz"}, /* 5.21KHz */ 2028 { 5, 3, 5208, "5.21kHz"}, /* 5.21KHz */ 2029 { 11, 2, 5208, "5.21kHz"}, /* 5.21KHz */ 2030 { 2, 4, 5208, "5.21kHz"}, /* 5.21KHz */ 2031 { 48, 0, 5102, "5.10kHz"}, /* 5.10KHz */ 2032 { 49, 0, 5000, "5.00kHz"}, /* 5.00KHz */ 2033 { 50, 0, 4902, "4.90kHz"}, /* 4.90KHz */ 2034 { 51, 0, 4808, "4.81kHz"}, /* 4.81KHz */ 2035 { 12, 2, 4808, "4.81kHz"}, /* 4.81KHz */ 2036 { 52, 0, 4717, "4.72kHz"}, /* 4.72KHz */ 2037 { 53, 0, 4630, "4.63kHz"}, /* 4.63KHz */ 2038 { 54, 0, 4545, "4.55kHz"}, /* 4.55KHz */ 2039 { 55, 0, 4464, "4.46kHz"}, /* 4.46KHz */ 2040 { 6, 3, 4464, "4.46kHz"}, /* 4.46KHz */ 2041 { 13, 2, 4464, "4.46kHz"}, /* 4.46KHz */ 2042 { 56, 0, 4386, "4.39kHz"}, /* 4.39KHz */ 2043 { 57, 0, 4310, "4.31kHz"}, /* 4.31KHz */ 2044 { 58, 0, 4237, "4.24kHz"}, /* 4.24KHz */ 2045 { 59, 0, 4167, "4.17kHz"}, /* 4.17KHz */ 2046 { 60, 0, 4098, "4.10kHz"}, /* 4.10KHz */ 2047 { 61, 0, 4032, "4.03kHz"}, /* 4.03KHz */ 2048 { 62, 0, 3968, "3.97kHz"}, /* 3.97KHz */ 2049 { 63, 0, 3906, "3.91kHz"}, /* 3.91KHz */ 2050 { 0, 6, 3906, "3.91kHz"}, /* 3.91KHz */ 2051 { 3, 4, 3906, "3.91kHz"}, /* 3.91KHz */ 2052 { 7, 3, 3906, "3.91kHz"}, /* 3.91KHz */ 2053 { 8, 3, 3472, "3.47kHz"}, /* 3.47KHz */ 2054 { 4, 4, 3125, "3.13kHz"}, /* 3.13KHz */ 2055 { 9, 3, 3125, "3.13kHz"}, /* 3.13KHz */ 2056 { 10, 3, 2841, "2.84kHz"}, /* 2.84KHz */ 2057 { 2, 5, 2604, "2.60kHz"}, /* 2.60KHz */ 2058 { 5, 4, 2604, "2.60kHz"}, /* 2.60KHz */ 2059 { 11, 3, 2604, "2.60kHz"}, /* 2.60KHz */ 2060 { 12, 3, 2404, "2.40kHz"}, /* 2.40KHz */ 2061 { 13, 3, 2232, "2.23kHz"}, /* 2.23KHz */ 2062 { 6, 4, 2232, "2.23kHz"}, /* 2.23KHz */ 2063 { 0, 7, 1953, "1.95kHz"}, /* 1.95KHz */ 2064 { 7, 4, 1953, "1.95kHz"}, /* 1.95KHz */ 2065 { 3, 5, 1953, "1.95kHz"}, /* 1.95KHz */ 2066 { 8, 4, 1736, "1.74kHz"}, /* 1.74KHz */ 2067 { 4, 5, 1563, "1.56kHz"}, /* 1.56KHz */ 2068 { 9, 4, 1563, "1.56kHz"}, /* 1.56KHz */ 2069 { 10, 4, 1420, "1.42kHz"}, /* 1.42KHz */ 2070 { 5, 5, 1302, "1.30kHz"}, /* 1.30KHz */ 2071 { 2, 6, 1302, "1.30kHz"}, /* 1.30KHz */ 2072 { 11, 4, 1302, "1.30kHz"}, /* 1.30KHz */ 2073 { 12, 4, 1202, "1.20kHz"}, /* 1.20KHz */ 2074 { 13, 4, 1116, "1.11kHz"}, /* 1.11KHz */ 2075 { 6, 5, 1116, "1.11kHz"} /* 1.11KHz */ 2076 }; 2077 #define xgs3_freqtab_sz COUNTOF(i2c_xgs3_freq_tab) 2078 2079 /* 2080 * Function: soc_i2c_set_freq 2081 * 2082 * Purpose: Set the clock control register on the I2C bus controller. 2083 * The CMIC_I2C_STAT register is a read-only register for the 2084 * bus status code of the last operation. The CMIC_I2C_CCR 2085 * register is at the same offset, but is a write-only 2086 * register, hence we must keep track of what M/N values 2087 * we are using. 2088 * 2089 * Inputs: 2090 * unit - StrataSwitch device number or I2C bus number 2091 * 2092 * Returns: 2093 * SOC_E_PARAM on bad input value, SOC_E_NONE otherwise. 2094 * 2095 * Notes: 2096 * CMIC_I2C_CCR <X,M{6:3},N{2:0}> 2097 */ 2098 static int 2099 soc_i2c_set_freq(int unit) 2100 { 2101 soc_i2c_bus_t *i2cbus; 2102 int i, size; 2103 uint32 speed; 2104 2105 i2cbus = I2CBUS(unit); 2106 speed = i2cbus->frequency; 2107 2108 if (bsl_check(bslLayerSoc, bslSourceI2c, bslSeverityNormal, unit)) { 2109 uint32 whole, decimal; 2110 char* pfx = NULL; 2111 2112 if (speed >= 1000000) { 2113 pfx = "M"; 2114 whole = speed / 1000000; 2115 decimal = ((speed%1000000)+5000)/10000; 2116 } else if (speed >= 1000) { 2117 pfx = "k"; 2118 whole = speed / 1000; 2119 decimal = ((speed%1000)+5)/10; 2120 } else { 2121 pfx = ""; 2122 whole = speed; 2123 decimal = 0; 2124 } 2125 2126 if (decimal == 100) { 2127 whole++; 2128 decimal = 0; 2129 } 2130 2131 LOG_CLI((BSL_META_U(unit, 2132 "unit %d i2c bus: attempting to set speed=%d.%02d%sHz (%d)\n"), 2133 unit, whole, decimal, pfx, speed)); 2134 } 2135 2136 size = SOC_IS_XGS3_SWITCH(unit) ? xgs3_freqtab_sz : freqtab_sz; 2137 2138 for (i = 0; i < size; i++) { 2139 if (speed >= (SOC_IS_XGS3_SWITCH(unit) ? 2140 i2c_xgs3_freq_tab[i].speed : i2c_freq_tab[i].speed)) { 2141 /* Use lower value (never exceed requested speed) */ 2142 i2cbus->m_val = SOC_IS_XGS3_SWITCH(unit) ? 2143 i2c_xgs3_freq_tab[i].m : i2c_freq_tab[i].m; 2144 i2cbus->n_val = SOC_IS_XGS3_SWITCH(unit) ? 2145 i2c_xgs3_freq_tab[i].n : i2c_freq_tab[i].n; 2146 soc_i2c_pci_write(unit, CMIC_I2C_STAT, 2147 (i2cbus->m_val << 3) | i2cbus->n_val); 2148 LOG_INFO(BSL_LS_SOC_I2C, 2149 (BSL_META_U(unit, 2150 "unit %d i2c bus: set frequency: " 2151 " just set M=%d N=%d: %s\n"), 2152 unit, i2cbus->m_val, i2cbus->n_val, 2153 SOC_IS_XGS3_SWITCH(unit) ? 2154 i2c_xgs3_freq_tab[i].name : i2c_freq_tab[i].name)); 2155 i2cbus->frequency = SOC_IS_XGS3_SWITCH(unit) ? 2156 i2c_xgs3_freq_tab[i].speed : i2c_freq_tab[i].speed; 2157 return SOC_E_NONE; 2158 } 2159 2160 } 2161 2162 /* 2163 * Here if requested speed is below the H/W's minimum. 2164 * In this case, use the hardware minimum even though 2165 * it is greater than the requested speed. 2166 */ 2167 i--; /* Last value in i2c_freq_table */ 2168 2169 i2cbus->m_val = SOC_IS_XGS3_SWITCH(unit) ? 2170 i2c_xgs3_freq_tab[i].m : i2c_freq_tab[i].m; 2171 i2cbus->n_val = SOC_IS_XGS3_SWITCH(unit) ? 2172 i2c_xgs3_freq_tab[i].n : i2c_freq_tab[i].n; 2173 soc_i2c_pci_write(unit, CMIC_I2C_STAT, 2174 (i2cbus->m_val << 3) | i2cbus->n_val); 2175 LOG_INFO(BSL_LS_SOC_I2C, 2176 (BSL_META_U(unit, 2177 "unit %d i2c bus: set frequency: " 2178 " just set M=%d N=%d: %s\n"), 2179 unit, i2cbus->m_val, i2cbus->n_val, 2180 SOC_IS_XGS3_SWITCH(unit) ? 2181 i2c_xgs3_freq_tab[i].name : i2c_freq_tab[i].name)); 2182 i2cbus->frequency = SOC_IS_XGS3_SWITCH(unit) ? 2183 i2c_xgs3_freq_tab[i].speed : i2c_freq_tab[i].speed; 2184 2185 return SOC_E_NONE; 2186 } 2187 2188 void 2189 soc_i2c_show_speeds(int unit) 2190 { 2191 int i; 2192 2193 for (i = 0; i < freqtab_sz; i++) { 2194 LOG_CLI((BSL_META_U(unit, 2195 "unit %d i2c bus: speed %s (CCR M=%d,N=%d) [%d]\n"), 2196 unit, SOC_IS_XGS3_SWITCH(unit) ? 2197 i2c_xgs3_freq_tab[i].name : i2c_freq_tab[i].name, 2198 SOC_IS_XGS3_SWITCH(unit) ? 2199 i2c_xgs3_freq_tab[i].m : i2c_freq_tab[i].m, 2200 SOC_IS_XGS3_SWITCH(unit) ? 2201 i2c_xgs3_freq_tab[i].n : i2c_freq_tab[i].n, 2202 SOC_IS_XGS3_SWITCH(unit) ? 2203 i2c_xgs3_freq_tab[i].speed : i2c_freq_tab[i].speed)); 2204 } 2205 } 2206