wolfhound2.c (269759B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: wolfhound2.c 8 * Purpose: 9 * Requires: 10 */ 11 12 #include <sal/core/boot.h> 13 #include <soc/bradley.h> 14 #include <soc/wolfhound2.h> 15 #include <soc/hurricane3.h> 16 #include <soc/drv.h> 17 #include <soc/mem.h> 18 #include <soc/hash.h> 19 #include <soc/error.h> 20 #include <soc/debug.h> 21 #include <soc/devids.h> 22 #include <soc/defs.h> 23 #include <soc/mspi.h> 24 25 #include <shared/util.h> 26 #include <shared/bsl.h> 27 28 29 #ifdef BCM_HURRICANE3_SUPPORT 30 31 #define WH2_MAX_PHY_PORTS (38) 32 33 static const int p2l_mapping_default[] = { 34 0, -1, 2, 3, 4, 5, 6, 7, 35 8, 9, 10, 11, 12, 13, -1, -1, 36 -1, -1, 14, 15, 16, 17, 18, 19, 37 20, 21, 22, 23, 24, 25, -1, -1, 38 -1, -1, 26, 27, 28, 29 39 }; 40 41 static const int port_speed_max_default[] = { 42 -1, -1, 10, 10, 10, 10, 10, 10, 43 10, 10, 10, 10, 10, 10, -1, -1, 44 -1, -1, 10, 10, 10, 10, 10, 10, 45 10, 10, 10, 10, 10, 10, -1, -1, 46 -1, -1, 25, 25, 25, 25 47 }; 48 49 static const int tdm_24p[] = { 50 2, 10, 18, 34, 3, 11, 19, 35, 51 4, 12, 20, 36, 5, 13, 21, 37, 52 6, 26, 22, 34, 7, 27, 23, 35, 53 8, 28, 24, 36, 9, 29, 25, 37, 54 0, 63 55 }; 56 57 static const int port_speed_max_op1[] = { 58 -1, -1, 10, 10, 10, 10, 10, 10, 59 10, 10, 10, 10, 10, 10, -1, -1, 60 -1, -1, 10, 10, 10, 10, 10, 10, 61 10, 10, 25, 25, 25, 25, -1, -1, 62 -1, -1, 25, 25, 25, 25 63 }; 64 65 static const int port_speed_max_op2[] = { 66 -1, -1, 10, 10, 10, 10, 10, 10, 67 10, 10, 10, 10, 10, 10, -1, -1, 68 -1, -1, 10, 10, 10, 10, 10, 10, 69 10, 10, 10, 10, 10, 10, -1, -1, 70 -1, -1, 25, 25, 25, 25 71 }; 72 73 static const int port_speed_max_op3[] = { 74 -1, -1, 10, 10, 10, 10, 10, 10, 75 10, 10, 10, 10, 10, 10, -1, -1, 76 -1, -1, 10, 10, 10, 10, 10, 10, 77 10, 10, 10, 10, 10, 10, -1, -1, 78 -1, -1, 25, 25, 25, 25 79 }; 80 81 static const int port_speed_max_op4_5_6[] = { 82 -1, -1, 10, 10, 10, 10, 10, 10, 83 10, 10, 10, 10, 10, 10, -1, -1, 84 -1, -1, 10, 10, 10, 10, 10, 10, 85 10, 10, 10, 10, 10, 10, -1, -1, 86 -1, -1, 10, 10, 10, 10 87 }; 88 89 static const int port_speed_max_op7[] = { 90 -1, -1, 10, 10, 10, 10, -1, -1, 91 -1, -1, -1, -1, -1, -1, -1, -1, 92 -1, -1, 10, 10, 10, 10, 10, 10, 93 10, 10, 25, 25, 25, 25, -1, -1, 94 -1, -1, 25, 25, 25, 25 95 }; 96 97 static const int port_speed_max_op8[] = { 98 -1, -1, 10, 10, 10, 10, -1, -1, 99 -1, -1, -1, -1, -1, -1, -1, -1, 100 -1, -1, 10, 10, 10, 10, 10, 10, 101 10, 10, 10, 10, 10, 10, -1, -1, 102 -1, -1, 25, 25, 25, 25 103 }; 104 105 static const int port_speed_max_op9[] = { 106 -1, -1, 10, 10, 10, 10, -1, -1, 107 -1, -1, -1, -1, -1, -1, -1, -1, 108 -1, -1, 10, 10, 10, 10, 10, 10, 109 10, 10, 10, 10, 10, 10, -1, -1, 110 -1, -1, 25, 25, 25, 25 111 }; 112 113 static const int port_speed_max_op10_11_12[] = { 114 -1, -1, 10, 10, 10, 10, -1, -1, 115 -1, -1, -1, -1, -1, -1, -1, -1, 116 -1, -1, 10, 10, 10, 10, 10, 10, 117 10, 10, 10, 10, 10, 10, -1, -1, 118 -1, -1, 10, 10, 10, 10 119 }; 120 121 static const int port_speed_max_op13[] = { 122 -1, -1, -1, -1, -1, -1, -1, -1, 123 -1, -1, -1, -1, -1, -1, -1, -1, 124 -1, -1, 10, 10, 10, 10, -1, -1, 125 -1, -1, 25, 25, 25, 25, -1, -1, 126 -1, -1, 25, 25, 25, 25 127 }; 128 129 static const int port_speed_max_op14[] = { 130 -1, -1, -1, -1, -1, -1, -1, -1, 131 -1, -1, -1, -1, -1, -1, -1, -1, 132 -1, -1, 10, 10, 10, 10, -1, -1, 133 -1, -1, 10, 10, 10, 10, -1, -1, 134 -1, -1, 25, 25, 25, 25 135 }; 136 137 static const int port_speed_max_op15[] = { 138 -1, -1, -1, -1, -1, -1, -1, -1, 139 -1, -1, -1, -1, -1, -1, -1, -1, 140 -1, -1, 10, 10, 10, 10, -1, -1, 141 -1, -1, 10, 10, 10, 10, -1, -1, 142 -1, -1, 25, 25, 25, 25 143 }; 144 145 static const int port_speed_max_op16_17_18[] = { 146 -1, -1, -1, -1, -1, -1, -1, -1, 147 -1, -1, -1, -1, -1, -1, -1, -1, 148 -1, -1, 10, 10, 10, 10, -1, -1, 149 -1, -1, 10, 10, 10, 10, -1, -1, 150 -1, -1, 10, 10, 10, 10 151 }; 152 153 static const int p2l_mapping_tdm_0[] = { 154 0, -1, 2, 3, 4, 5, 6, 7, 155 8, 9, 10, 11, 12, 13, -1, -1, 156 -1, -1, 14, 15, 16, 17, 18, 19, 157 20, 21, 22, 23, 24, 25, -1, -1, 158 -1, -1, 26, 27, 28, 29 159 }; 160 161 static const int tdm_0[] = { 162 2, 10, 18, 34, 3, 11, 19, 35, 163 4, 12, 20, 36, 5, 13, 21, 37, 164 6, 26, 22, 34, 7, 27, 23, 35, 165 8, 28, 24, 36, 9, 29, 25, 37, 166 0, 63 167 }; 168 169 static const int p2l_mapping_tdm_1[] = { 170 0, -1, -1, -1, -1, -1, -1, -1, 171 -1, -1, -1, -1, -1, -1, -1, -1, 172 -1, -1, 2, 3, 4, 5, -1, -1, 173 -1, -1, 6, 7, 8, 9, -1, -1, 174 -1, -1, 10, 11, 12, 13 175 }; 176 177 static const int tdm_1[] = { 178 18, 26, 34, 0, 19, 27, 35, 63, 179 20, 28, 36, 63, 21, 29, 37, 63 180 }; 181 182 static const int p2l_mapping_tdm_2[] = { 183 0, -1, 2, 3, 4, 5, 6, 7, 184 8, 9, 10, 11, 12, 13, -1, -1, 185 -1, -1, 14, 15, 16, 17, 18, 19, 186 20, 21, 22, 23, 24, 25, -1, -1, 187 -1, -1, 26, 27, 28, 29 188 }; 189 190 static const int tdm_2[] = { 191 2, 10, 18, 34, 3, 11, 19, 35, 192 4, 12, 20, 36, 5, 13, 21, 37, 193 6, 26, 22, 0, 7, 27, 23, 63, 194 8, 28, 24, 63, 9, 29, 25, 63 195 }; 196 197 static const int p2l_mapping_tdm_3[] = { 198 0, -1, 2, 3, 4, 5, 6, 7, 199 8, 9, 10, 11, 12, 13, -1, -1, 200 -1, -1, 14, 15, 16, 17, 18, 19, 201 20, 21, 22, 23, 24, 25, -1, -1, 202 -1, -1, 26, 27, 28, 29 203 }; 204 205 static const int tdm_3[] = { 206 2, 18, 26, 34, 10, 3, 27, 35, 207 19, 11, 28, 36, 4, 20, 29, 37, 208 12, 5, 26, 34, 21, 13, 27, 35, 209 6, 22, 28, 36, 7, 23, 29, 37, 210 8, 24, 0, 63, 9, 25, 63, 63 211 }; 212 213 static const int p2l_mapping_tdm_4[] = { 214 0, -1, 2, 3, 4, 5, -1, -1, 215 -1, -1, -1, -1, -1, -1, -1, -1, 216 -1, -1, 6, 7, 8, 9, 10, 11, 217 12, 13, 14, 15, 16, 17, -1, -1, 218 -1, -1, 18, 19, 20, 21 219 }; 220 221 static const int tdm_4[] = { 222 2, 18, 26, 34, 3, 19, 27, 35, 223 4, 20, 28, 36, 5, 21, 29, 37, 224 0, 22, 26, 34, 63, 23, 27, 35, 225 63, 24, 28, 36, 63, 25, 29, 37 226 }; 227 228 static const soc_port_t lport_dport_map_0[] = { 229 0, -1, 13, 12, 11, 10, 9, 8, 230 7, 6, 5, 4, 3, 2, 14, 15, 231 16, 17, 18, 19, 20, 21, 22, 23, 232 24, 25, 26, 27, 28, 29 233 }; 234 235 static const soc_port_t lport_dport_map_1[] = { 236 0, -1, -1, -1, -1, -1, -1, -1, 237 -1, -1, 5, 4, 3, 2, 6, 7, 238 8, 9, 10, 11, 12, 13, 14, 15, 239 16, 17, 18, 19, 20, 21 240 }; 241 242 static const soc_port_t lport_dport_map_2[] = { 243 0, -1, -1, -1, -1, -1, -1, -1, 244 -1, -1, 5, 4, 3, 2, 14, 15, 245 16, 17, 18, 19, 20, 21, 22, 23, 246 24, 25, 26, 27, 28, 29 247 }; 248 249 static const soc_port_t lport_dport_map_3[] = { 250 0, -1, -1, -1, -1, -1, -1, -1, 251 -1, -1, -1, -1, -1, -1, 2, 3, 252 4, 5, -1, -1, -1, -1, 6, 7, 253 8, 9, 10, 11, 12, 13 254 }; 255 256 static int matched_devid_idx[SOC_MAX_NUM_DEVICES] = {-1}; 257 258 typedef struct wh2_sku_info_s { 259 uint16 dev_id; 260 int config_option; 261 int frequency; 262 char *op_str; 263 const int *p2l_mapping; 264 const int *speed_max; 265 const int *dport_mapping; 266 const int *tdm_table; 267 int tdm_table_size; 268 uint32 qgphy_core_map; 269 uint8 qgphy5_lane; 270 uint8 sgmii_4p0_lane; 271 } wh2_sku_info_t; 272 273 274 STATIC wh2_sku_info_t wh2_sku_port_config[] = { 275 /* 53540 : 24 + 4 */ 276 {BCM53540_DEVICE_ID, 2, 78, "op2", 277 p2l_mapping_default, port_speed_max_default, lport_dport_map_0, 278 tdm_24p, 34, 0x3F, 0xF, 0 279 }, 280 {BCM53547_DEVICE_ID, 1, 104, "op1", 281 p2l_mapping_tdm_3, port_speed_max_op1, lport_dport_map_0, 282 tdm_3, 40, 0x1F, 0, 0xF 283 }, 284 {BCM53547_DEVICE_ID, 2, 104, "op2", 285 p2l_mapping_tdm_0, port_speed_max_op2, lport_dport_map_0, 286 tdm_0, 34, 0x3F, 0xF, 0 287 }, 288 {BCM53547_DEVICE_ID, 3, 104, "op3", 289 p2l_mapping_tdm_0, port_speed_max_op3, lport_dport_map_0, 290 tdm_0, 34, 0x3F, 0x3, 0xC 291 }, 292 {BCM53547_DEVICE_ID, 4, 62, "op4", 293 p2l_mapping_tdm_2, port_speed_max_op4_5_6, lport_dport_map_0, 294 tdm_2, 32, 0x3F, 0x3, 0xC 295 }, 296 {BCM53547_DEVICE_ID, 5, 62, "op5", 297 p2l_mapping_tdm_2, port_speed_max_op4_5_6, lport_dport_map_0, 298 tdm_2, 32, 0x1F, 0, 0xF 299 }, 300 {BCM53547_DEVICE_ID, 6, 62, "op6", 301 p2l_mapping_tdm_2, port_speed_max_op4_5_6, lport_dport_map_0, 302 tdm_2, 32, 0x3F, 0xF, 0 303 }, 304 {BCM53548_DEVICE_ID, 7, 104, "op7", 305 p2l_mapping_tdm_4, port_speed_max_op7, lport_dport_map_1, 306 tdm_4, 32, 0x19, 0, 0xF 307 }, 308 {BCM53548_DEVICE_ID, 8, 104, "op8", 309 p2l_mapping_tdm_0, port_speed_max_op8, lport_dport_map_2, 310 tdm_0, 34, 0x39, 0xF, 0 311 }, 312 {BCM53548_DEVICE_ID, 9, 104, "op9", 313 p2l_mapping_tdm_0, port_speed_max_op9, lport_dport_map_2, 314 tdm_0, 34, 0x39, 0x3, 0xC 315 }, 316 {BCM53548_DEVICE_ID, 10, 62, "op10", 317 p2l_mapping_tdm_2, port_speed_max_op10_11_12, lport_dport_map_2, 318 tdm_2, 32, 0x39, 0x3, 0xC 319 }, 320 {BCM53548_DEVICE_ID, 11, 62, "op11", 321 p2l_mapping_tdm_2, port_speed_max_op10_11_12, lport_dport_map_2, 322 tdm_2, 32, 0x19, 0, 0xF 323 }, 324 {BCM53548_DEVICE_ID, 12, 62, "op12", 325 p2l_mapping_tdm_2, port_speed_max_op10_11_12, lport_dport_map_2, 326 tdm_2, 32, 0x39, 0xF, 0 327 }, 328 {BCM53549_DEVICE_ID, 13, 104, "op13", 329 p2l_mapping_tdm_1, port_speed_max_op13, lport_dport_map_3, 330 tdm_1, 16, 0x8, 0, 0xF 331 }, 332 {BCM53549_DEVICE_ID, 14, 104, "op14", 333 p2l_mapping_tdm_1, port_speed_max_op14, lport_dport_map_3, 334 tdm_1, 16, 0x28, 0xF, 0 335 }, 336 {BCM53549_DEVICE_ID, 15, 104, "op15", 337 p2l_mapping_tdm_1, port_speed_max_op15, lport_dport_map_3, 338 tdm_1, 16, 0x28, 0x3, 0xC 339 }, 340 {BCM53549_DEVICE_ID, 16, 41, "op16", 341 p2l_mapping_tdm_1, port_speed_max_op16_17_18, lport_dport_map_3, 342 tdm_1, 16, 0x28, 0x3, 0xC 343 }, 344 {BCM53549_DEVICE_ID, 17, 41, "op17", 345 p2l_mapping_tdm_1, port_speed_max_op16_17_18, lport_dport_map_3, 346 tdm_1, 16, 0x8, 0, 0xF 347 }, 348 {BCM53549_DEVICE_ID, 18, 41, "op18", 349 p2l_mapping_tdm_1, port_speed_max_op16_17_18, lport_dport_map_3, 350 tdm_1, 16, 0x28, 0xF, 0 351 }, 352 {0} 353 }; 354 355 int 356 soc_wolfhound2_port_config_init(int unit, uint16 dev_id) 357 { 358 soc_info_t *si; 359 int phy_port, lport; 360 const int *p2l_mapping, *port_speed_max; 361 wh2_sku_info_t *sku_info, *matched_port_config = NULL; 362 char *option_str; 363 int valid_sku_option, i; 364 365 option_str = soc_property_get_str(unit, "init_port_config_option"); 366 367 valid_sku_option = -1; 368 matched_devid_idx[unit] = -1; 369 370 for (i = 0; wh2_sku_port_config[i].dev_id != 0; i++) { 371 sku_info = &wh2_sku_port_config[i]; 372 if (dev_id == sku_info->dev_id) { 373 if (option_str == NULL) { 374 option_str = sku_info->op_str; 375 LOG_WARN(BSL_LS_SOC_COMMON, 376 (BSL_META_U(unit, 377 "Warning: init_port_config_option is not " 378 "specified. Take %s for %s \n"), 379 option_str, soc_dev_name(unit))); 380 } 381 if (matched_devid_idx[unit] == -1) { 382 matched_devid_idx[unit] = i; 383 } 384 if (!sal_strcmp(sku_info->op_str, option_str)) { 385 valid_sku_option = i; 386 break; 387 } 388 } 389 } 390 assert(matched_devid_idx[unit] != -1); 391 392 if (valid_sku_option == -1) { 393 valid_sku_option = 394 wh2_sku_port_config[matched_devid_idx[unit]].config_option; 395 LOG_WARN(BSL_LS_SOC_COMMON, 396 (BSL_META_U(unit, 397 "Warning: option %s is not supported in %s. " 398 "Take %s\n"), 399 option_str, soc_dev_name(unit), 400 wh2_sku_port_config[matched_devid_idx[unit]].op_str)); 401 } 402 matched_devid_idx[unit] = valid_sku_option; 403 404 matched_port_config = &wh2_sku_port_config[matched_devid_idx[unit]]; 405 p2l_mapping = matched_port_config->p2l_mapping; 406 port_speed_max = matched_port_config->speed_max; 407 408 si = &SOC_INFO(unit); 409 for (phy_port = 0; phy_port < WH2_MAX_PHY_PORTS; phy_port++) { 410 if ((port_speed_max[phy_port] == -1) && (phy_port != 0)) { 411 si->port_p2l_mapping[phy_port] = -1; 412 si->port_p2m_mapping[phy_port] = -1; 413 si->max_port_p2m_mapping[phy_port] = -1; 414 si->port_num_lanes[p2l_mapping[phy_port]] = -1; 415 } else { 416 si->port_p2l_mapping[phy_port] = p2l_mapping[phy_port]; 417 si->port_p2m_mapping[phy_port] = p2l_mapping[phy_port]; 418 si->max_port_p2m_mapping[phy_port] = p2l_mapping[phy_port]; 419 lport = si->port_p2l_mapping[phy_port]; 420 si->port_speed_max[lport] = port_speed_max[phy_port] * 100; 421 si->port_num_lanes[lport] = 1; 422 } 423 } 424 si->frequency = matched_port_config->frequency; 425 return SOC_E_NONE; 426 } 427 428 int 429 soc_wolfhound2_dport_init(int unit) 430 { 431 int dport; 432 wh2_sku_info_t *matched_port_config = NULL; 433 const int *l2d_mapping; 434 435 matched_port_config = &wh2_sku_port_config[matched_devid_idx[unit]]; 436 l2d_mapping = matched_port_config->dport_mapping; 437 438 if (l2d_mapping == NULL) { 439 return SOC_E_NONE; 440 } 441 442 for (dport = 0; dport < 30; dport++) { 443 SOC_DPORT_MAP(unit)[dport] = l2d_mapping[dport]; 444 } 445 446 return SOC_E_NONE; 447 } 448 449 int 450 soc_wolfhound2_gphy_get(int unit, int port, uint8 *is_gphy) 451 { 452 wh2_sku_info_t *matched_port_config = NULL; 453 soc_info_t *si; 454 int qgphy_id, phy_port; 455 uint32 qgphy_core_map; 456 uint8 qgphy5_lane; 457 458 matched_port_config = &wh2_sku_port_config[matched_devid_idx[unit]]; 459 qgphy_core_map = matched_port_config->qgphy_core_map; 460 qgphy5_lane = matched_port_config->qgphy5_lane; 461 462 si = &SOC_INFO(unit); 463 phy_port = si->port_l2p_mapping[port]; 464 465 /* get the quad gphy id */ 466 /* 0:2-5, 1:6-9, 2:10-13, 3:18-21, 4:22-25, 5:26-29 */ 467 qgphy_id = (phy_port - 2) / 4; 468 if (phy_port >= 34) { 469 /* SGMII_4P1 => qgphy_id = -1 */ 470 qgphy_id = -1; 471 } else if (phy_port >= 18) { 472 qgphy_id--; 473 } 474 475 if (qgphy_id != -1) { 476 if (qgphy_core_map & (1 << qgphy_id)) { 477 if (qgphy_id == 5) { 478 if (qgphy5_lane & (1 << (phy_port - 2) % 4)) { 479 *is_gphy = 1; 480 } else { 481 *is_gphy = 0; 482 } 483 484 } else { 485 *is_gphy = 1; 486 } 487 } else { 488 *is_gphy = 0; 489 } 490 } else { 491 *is_gphy = 0; 492 } 493 return SOC_E_NONE; 494 } 495 496 int 497 soc_wolfhound2_features(int unit, soc_feature_t feature) 498 { 499 switch (feature) { 500 /* Wolfhound2 specific feature (different from HR3) */ 501 case soc_feature_field_multi_stage: /* no VFP, EFP in WH2 */ 502 case soc_feature_field_slice_size128: 503 case soc_feature_xlmac: 504 case soc_feature_uc: 505 case soc_feature_rcpu_priority: /* CMIC_PKT_CTRL not in regfile */ 506 case soc_feature_l3_dynamic_ecmp_group: 507 case soc_feature_e2ecc: /* no E2ECC */ 508 case soc_feature_discard_ability: /* no WRED */ 509 case soc_feature_wred_drop_counter_per_port: /* no WRED */ 510 case soc_feature_ecn_wred: /* no ECN */ 511 case soc_feature_miml: /* no MiML */ 512 case soc_feature_miml_no_l3: /* no MiML when no L3 */ 513 case soc_feature_higig_lookup: 514 case soc_feature_proxy_port_property: 515 case soc_feature_gmii_clkout: /* no SyncE in WH2 */ 516 return FALSE; 517 case soc_feature_wh2: 518 case soc_feature_gphy: /* need to consider sku later */ 519 case soc_feature_time_v3_no_bs: 520 case soc_feature_no_qt_gport: /* wh2 qt has no phy model in QT */ 521 case soc_feature_l3_no_ecmp: 522 case soc_feature_l3: 523 case soc_feature_l3_ip6: 524 case soc_feature_l3_entry_key_type: 525 case soc_feature_lpm_tcam: 526 case soc_feature_ip_mcast: 527 case soc_feature_ip_mcast_repl: 528 case soc_feature_ipmc_unicast: 529 case soc_feature_ipmc_use_configured_dest_mac: 530 case soc_feature_l3mc_use_egress_next_hop: 531 case soc_feature_l3_sgv: 532 case soc_feature_urpf: 533 case soc_feature_l3_ingress_interface: 534 case soc_feature_l3_iif_zero_invalid: 535 case soc_feature_l3_iif_under_4k: 536 case soc_feature_hg_trunking: 537 case soc_feature_hg_trunk_override: 538 case soc_feature_hg_trunk_failover: 539 case soc_feature_hg_trunk_group_members_max_4: 540 return TRUE; 541 542 default : 543 return _soc_hurricane3_features(unit, feature); 544 } 545 } 546 547 /* 548 * soc_wolfhound2_mem_config: 549 * Over-ride the default table sizes (from regsfile) for any SKUs here 550 */ 551 int 552 soc_wolfhound2_mem_config(int unit, int dev_id) 553 { 554 int rv = SOC_E_NONE; 555 soc_persist_t *sop = SOC_PERSIST(unit); 556 switch (dev_id) { 557 case BCM53540_DEVICE_ID: 558 case BCM53547_DEVICE_ID: 559 case BCM53548_DEVICE_ID: 560 case BCM53549_DEVICE_ID: 561 default: 562 /* No EFP and VFP in WH2 family */ 563 sop->memState[EFP_COUNTER_TABLEm].index_max = -1; 564 sop->memState[EFP_METER_TABLEm].index_max = -1; 565 sop->memState[EFP_POLICY_TABLEm].index_max = -1; 566 sop->memState[EFP_TCAMm].index_max = -1; 567 sop->memState[VFP_POLICY_TABLEm].index_max = -1; 568 sop->memState[VFP_TCAMm].index_max = -1; 569 SOC_CONTROL(unit)->l3_defip_max_tcams = 1; 570 SOC_CONTROL(unit)->l3_defip_tcam_size = 64; 571 /* Module ID num: 64(0 ~ 63), not 256 */ 572 sop->memState[MODPORT_MAPm].index_max = 383; 573 break; 574 } 575 if (SAL_BOOT_QUICKTURN) { 576 /* QuickTurn with limited TCAM entries */ 577 sop->memState[L2_USER_ENTRYm].index_max = 11; 578 sop->memState[L2_USER_ENTRY_ONLYm].index_max = 11; 579 sop->memState[L2_USER_ENTRY_DATA_ONLYm].index_max = 11; 580 sop->memState[CPU_COS_MAPm].index_max = 11; 581 sop->memState[CPU_COS_MAP_ONLYm].index_max = 11; 582 sop->memState[FP_GLOBAL_MASK_TCAMm].index_max = 29; 583 sop->memState[VLAN_SUBNETm].index_max = 11; 584 sop->memState[VLAN_SUBNET_ONLYm].index_max = 11; 585 sop->memState[VLAN_SUBNET_DATA_ONLYm].index_max = 11; 586 sop->memState[L3_DEFIPm].index_max = 31; 587 sop->memState[L3_DEFIP_ONLYm].index_max = 31; 588 sop->memState[L3_DEFIP_DATA_ONLYm].index_max = 31; 589 sop->memState[FP_TCAMm].index_max = 29; 590 } 591 return rv; 592 } 593 594 #define WH2_QGPHY_CORE_AMAC (5) 595 #define WH2_QGPHY_CORE_ALL (0x3F) 596 #define WH2_QGPHY_CORE_PBMP_ALL (0xFFFFFF) 597 #define WH2_QGPHY_CORE_AMAC_BIT_SHIFT (20) 598 599 static const uint32 wh2_qgphy_core_pbmp [6] = { 600 0xF, 0xF0, 0xF00, 0xF000, 0xF0000, 0xF00000 601 }; 602 603 STATIC int 604 soc_wh2_qgphy_init(int unit, uint32 qgphy_core_map, uint8 qgphy5_lane) 605 { 606 int amac = 0, i; 607 uint32 pbmp, core, core_temp, iddq_pwr, iddq_bias, rval; 608 uint32 pbmp_temp = 0; 609 int sleep_usec = 1100; 610 611 pbmp = 0; 612 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REGr(unit, &rval)); 613 core = soc_reg_field_get(unit, TOP_SOFT_RESET_REGr, rval, TOP_QGPHY_RST_Lf); 614 615 /* Check if gphy5 is up and used by AMAC */ 616 if (core & (1 << WH2_QGPHY_CORE_AMAC)) { 617 if (soc_cm_get_bus_type(unit) & SOC_AXI_DEV_TYPE) { 618 amac = 1; 619 } 620 } 621 622 /* power up the QGPHY */ 623 for (i = 0; i < 6; i++) { 624 if (qgphy_core_map & (1 << i)) { 625 pbmp_temp |= wh2_qgphy_core_pbmp[i]; 626 } 627 } 628 if (amac) { 629 pbmp_temp &= ~wh2_qgphy_core_pbmp[WH2_QGPHY_CORE_AMAC]; 630 } 631 SOC_IF_ERROR_RETURN(READ_TOP_QGPHY_CTRL_0r(unit, &rval)); 632 pbmp = soc_reg_field_get(unit, TOP_QGPHY_CTRL_0r, rval, EXT_PWRDOWNf); 633 pbmp &= ~pbmp_temp; 634 soc_reg_field_set(unit, TOP_QGPHY_CTRL_0r, &rval, EXT_PWRDOWNf, pbmp); 635 SOC_IF_ERROR_RETURN(WRITE_TOP_QGPHY_CTRL_0r(unit, rval)); 636 sal_usleep(sleep_usec); 637 638 /* Release iddq isolation */ 639 core = qgphy_core_map; 640 if ((amac) || (qgphy5_lane == 0x3)) { 641 core &= ~(1 << WH2_QGPHY_CORE_AMAC); 642 } 643 SOC_IF_ERROR_RETURN(READ_TOP_QGPHY_CTRL_2r(unit, &rval)); 644 iddq_pwr = soc_reg_field_get(unit, TOP_QGPHY_CTRL_2r, rval, 645 GPHY_IDDQ_GLOBAL_PWRf); 646 iddq_bias = soc_reg_field_get(unit, TOP_QGPHY_CTRL_2r, rval, 647 IDDQ_BIASf); 648 iddq_pwr &= ~core; 649 iddq_bias &= ~core; 650 soc_reg_field_set(unit, TOP_QGPHY_CTRL_2r, &rval, 651 GPHY_IDDQ_GLOBAL_PWRf, iddq_pwr); 652 soc_reg_field_set(unit, TOP_QGPHY_CTRL_2r, &rval, 653 IDDQ_BIASf, iddq_bias); 654 SOC_IF_ERROR_RETURN(WRITE_TOP_QGPHY_CTRL_2r(unit, rval)); 655 sal_usleep(sleep_usec); 656 657 /* Toggle reset */ 658 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REGr(unit, &rval)); 659 core_temp = soc_reg_field_get(unit, TOP_SOFT_RESET_REGr, rval, 660 TOP_QGPHY_RST_Lf); 661 core_temp |= core; 662 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, 663 TOP_QGPHY_RST_Lf, core_temp); 664 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REGr(unit, rval)); 665 sal_usleep(sleep_usec); 666 LOG_VERBOSE(BSL_LS_SOC_COMMON, 667 (BSL_META_U(unit,"QGPHY 0x%x are power up. " 668 "pwrdown bitmap %x (amac=%d)\n"), 669 core_temp, pbmp, amac)); 670 671 /* Full Quad power down */ 672 pbmp_temp = 0; 673 core_temp = WH2_QGPHY_CORE_ALL; 674 core_temp &= ~qgphy_core_map; 675 if (amac) { 676 /* Avoid power down qgphy5 when amac is using it */ 677 core_temp &= ~(1 << WH2_QGPHY_CORE_AMAC); 678 } else if (qgphy5_lane == 0x3) { 679 /* Power down qgphy 5 first then enable some bitmap later */ 680 core_temp |= (1 << WH2_QGPHY_CORE_AMAC); 681 } 682 if (core_temp) { 683 for (i = 0; i < 6; i++) { 684 if (core_temp & (1 << i)) { 685 pbmp_temp |= wh2_qgphy_core_pbmp[i]; 686 } 687 } 688 SOC_IF_ERROR_RETURN(READ_TOP_QGPHY_CTRL_0r(unit, &rval)); 689 pbmp = soc_reg_field_get(unit, TOP_QGPHY_CTRL_0r, rval, EXT_PWRDOWNf); 690 pbmp |= pbmp_temp; 691 soc_reg_field_set(unit, TOP_QGPHY_CTRL_0r, &rval, EXT_PWRDOWNf, pbmp); 692 SOC_IF_ERROR_RETURN(WRITE_TOP_QGPHY_CTRL_0r(unit, rval)); 693 sal_usleep(sleep_usec); 694 695 /* Toggle iddq isolation and reset */ 696 /* iddq_pw1 = 1, iddq_bias = 1, reset_n = 1*/ 697 SOC_IF_ERROR_RETURN(READ_TOP_QGPHY_CTRL_2r(unit, &rval)); 698 iddq_pwr = soc_reg_field_get(unit, TOP_QGPHY_CTRL_2r, rval, 699 GPHY_IDDQ_GLOBAL_PWRf); 700 iddq_bias = soc_reg_field_get(unit, TOP_QGPHY_CTRL_2r, rval, 701 IDDQ_BIASf); 702 iddq_pwr |= core_temp; 703 iddq_bias |= core_temp; 704 soc_reg_field_set(unit, TOP_QGPHY_CTRL_2r, &rval, 705 GPHY_IDDQ_GLOBAL_PWRf, iddq_pwr); 706 soc_reg_field_set(unit, TOP_QGPHY_CTRL_2r, &rval, 707 IDDQ_BIASf, iddq_pwr); 708 SOC_IF_ERROR_RETURN(WRITE_TOP_QGPHY_CTRL_2r(unit, rval)); 709 sal_usleep(sleep_usec); 710 711 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REGr(unit, &rval)); 712 core = soc_reg_field_get(unit, TOP_SOFT_RESET_REGr, rval, 713 TOP_QGPHY_RST_Lf); 714 core |= core_temp; 715 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, 716 TOP_QGPHY_RST_Lf, core); 717 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REGr(unit, rval)); 718 sal_usleep(sleep_usec); 719 720 /* iddq_pw1 = 0, iddq_bias = 0, reset_n = 0*/ 721 SOC_IF_ERROR_RETURN(READ_TOP_QGPHY_CTRL_2r(unit, &rval)); 722 iddq_pwr = soc_reg_field_get(unit, TOP_QGPHY_CTRL_2r, rval, 723 GPHY_IDDQ_GLOBAL_PWRf); 724 iddq_bias = soc_reg_field_get(unit, TOP_QGPHY_CTRL_2r, rval, 725 IDDQ_BIASf); 726 iddq_pwr &= ~core_temp; 727 iddq_bias &= ~core_temp; 728 soc_reg_field_set(unit, TOP_QGPHY_CTRL_2r, &rval, 729 GPHY_IDDQ_GLOBAL_PWRf, iddq_pwr); 730 soc_reg_field_set(unit, TOP_QGPHY_CTRL_2r, &rval, 731 IDDQ_BIASf, iddq_pwr); 732 SOC_IF_ERROR_RETURN(WRITE_TOP_QGPHY_CTRL_2r(unit, rval)); 733 sal_usleep(sleep_usec); 734 735 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REGr(unit, &rval)); 736 core = soc_reg_field_get(unit, TOP_SOFT_RESET_REGr, rval, 737 TOP_QGPHY_RST_Lf); 738 core &= ~core_temp; 739 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, 740 TOP_QGPHY_RST_Lf, core); 741 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REGr(unit, rval)); 742 sal_usleep(sleep_usec); 743 744 /* reset_n = 1, iddq_pw1 = 1, iddq_bias = 1 */ 745 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REGr(unit, &rval)); 746 core = soc_reg_field_get(unit, TOP_SOFT_RESET_REGr, rval, 747 TOP_QGPHY_RST_Lf); 748 core |= core_temp; 749 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, 750 TOP_QGPHY_RST_Lf, core); 751 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REGr(unit, rval)); 752 sal_usleep(sleep_usec); 753 754 SOC_IF_ERROR_RETURN(READ_TOP_QGPHY_CTRL_2r(unit, &rval)); 755 iddq_pwr = soc_reg_field_get(unit, TOP_QGPHY_CTRL_2r, rval, 756 GPHY_IDDQ_GLOBAL_PWRf); 757 iddq_bias = soc_reg_field_get(unit, TOP_QGPHY_CTRL_2r, rval, 758 IDDQ_BIASf); 759 iddq_pwr |= core_temp; 760 iddq_bias |= core_temp; 761 soc_reg_field_set(unit, TOP_QGPHY_CTRL_2r, &rval, 762 GPHY_IDDQ_GLOBAL_PWRf, iddq_pwr); 763 soc_reg_field_set(unit, TOP_QGPHY_CTRL_2r, &rval, 764 IDDQ_BIASf, iddq_pwr); 765 SOC_IF_ERROR_RETURN(WRITE_TOP_QGPHY_CTRL_2r(unit, rval)); 766 sal_usleep(sleep_usec); 767 LOG_VERBOSE(BSL_LS_SOC_COMMON, 768 (BSL_META_U(unit,"Disable QGPHY 0x%x " 769 "pwrdown bitmap %x\n"), 770 core_temp, pbmp)); 771 } 772 773 /* Partial power up */ 774 if (qgphy5_lane == 0x3) { 775 if (!amac) { 776 /* iddq_pw1 = 0, iddq_bias = 0*/ 777 SOC_IF_ERROR_RETURN(READ_TOP_QGPHY_CTRL_2r(unit, &rval)); 778 iddq_pwr = soc_reg_field_get(unit, TOP_QGPHY_CTRL_2r, rval, 779 GPHY_IDDQ_GLOBAL_PWRf); 780 iddq_bias = soc_reg_field_get(unit, TOP_QGPHY_CTRL_2r, rval, 781 IDDQ_BIASf); 782 iddq_pwr &= ~(1 << WH2_QGPHY_CORE_AMAC); 783 iddq_bias &= ~(1 << WH2_QGPHY_CORE_AMAC); 784 soc_reg_field_set(unit, TOP_QGPHY_CTRL_2r, &rval, 785 GPHY_IDDQ_GLOBAL_PWRf, iddq_pwr); 786 soc_reg_field_set(unit, TOP_QGPHY_CTRL_2r, &rval, 787 IDDQ_BIASf, iddq_pwr); 788 SOC_IF_ERROR_RETURN(WRITE_TOP_QGPHY_CTRL_2r(unit, rval)); 789 sal_usleep(sleep_usec); 790 } 791 /* power up qghphy lane */ 792 SOC_IF_ERROR_RETURN(READ_TOP_QGPHY_CTRL_0r(unit, &rval)); 793 pbmp = soc_reg_field_get(unit, TOP_QGPHY_CTRL_0r, rval, 794 EXT_PWRDOWNf); 795 pbmp &= ~(qgphy5_lane << WH2_QGPHY_CORE_AMAC_BIT_SHIFT); 796 soc_reg_field_set(unit, TOP_QGPHY_CTRL_0r, &rval, EXT_PWRDOWNf, pbmp); 797 SOC_IF_ERROR_RETURN(WRITE_TOP_QGPHY_CTRL_0r(unit, rval)); 798 sal_usleep(sleep_usec); 799 LOG_VERBOSE(BSL_LS_SOC_COMMON, 800 (BSL_META_U(unit, "Partial power up qgphy5 lane 0/1\n"))); 801 } 802 803 return SOC_E_NONE; 804 } 805 806 STATIC int 807 soc_wh2_gphy_pmq_init(int unit, int pmq_inst) 808 { 809 soc_reg_t reg; 810 int blk, pmq_port; 811 uint32 rval; 812 int sleep_usec = SAL_BOOT_QUICKTURN ? 500000 : 1100; 813 soc_info_t *si; 814 815 if (pmq_inst > 1) { 816 /* PMQ 0,1 control GPHY related configurations */ 817 return SOC_E_INTERNAL; 818 } 819 820 reg = GPORT_XGXS0_CTRL_REGr; 821 si = &SOC_INFO(unit); 822 blk = si->pmq_block[pmq_inst]; 823 pmq_port = blk | SOC_REG_ADDR_BLOCK_ID_MASK; 824 825 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, reg, pmq_port, 0, &rval)); 826 soc_reg_field_set(unit, reg, &rval, IDDQf, 0); 827 /* Deassert power down */ 828 soc_reg_field_set(unit, reg, &rval, PWRDWNf, 0); 829 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, reg, pmq_port, 0, rval)); 830 sal_usleep(sleep_usec); 831 832 /* Reset XGXS */ 833 soc_reg_field_set(unit, reg, &rval, RSTB_HWf, 0); 834 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, reg, pmq_port, 0, rval)); 835 sal_usleep(sleep_usec + 10000); 836 837 /* Bring XGXS out of reset */ 838 soc_reg_field_set(unit, reg, &rval, RSTB_HWf, 1); 839 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, reg, pmq_port, 0, rval)); 840 sal_usleep(sleep_usec); 841 842 /* Activate MDIO on SGMII */ 843 soc_reg_field_set(unit, reg, &rval, RSTB_REFCLKf, 1); 844 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, reg, pmq_port, 0, rval)); 845 sal_usleep(sleep_usec); 846 847 /* Activate clocks */ 848 soc_reg_field_set(unit, reg, &rval, RSTB_PLLf, 1); 849 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, reg, pmq_port, 0, rval)); 850 851 return SOC_E_NONE; 852 } 853 854 STATIC int 855 soc_wh2_sgmii_init(int unit, int sgmii_inst) 856 { 857 soc_reg_t reg; 858 int blk, pmq_port; 859 uint32 rval; 860 int sleep_usec = SAL_BOOT_QUICKTURN ? 500000 : 1100; 861 soc_info_t *si; 862 863 if (sgmii_inst == 0) { 864 /* TOP_SGMII_CTRL_REGr */ 865 reg = TOP_SGMII_CTRL_REGr; 866 pmq_port = REG_PORT_ANY; 867 } else if (sgmii_inst == 1) { 868 /* GPORT_SGMII0_CTRL_REGr in PMQ2 */ 869 reg = GPORT_SGMII0_CTRL_REGr; 870 si = &SOC_INFO(unit); 871 blk = si->pmq_block[2]; 872 pmq_port = blk | SOC_REG_ADDR_BLOCK_ID_MASK; 873 } else { 874 return SOC_E_UNAVAIL; 875 } 876 877 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, reg, pmq_port, 0, &rval)); 878 soc_reg_field_set(unit, reg, &rval, IDDQf, 0); 879 /* Deassert power down */ 880 soc_reg_field_set(unit, reg, &rval, PWRDWNf, 0); 881 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, reg, pmq_port, 0, rval)); 882 sal_usleep(sleep_usec); 883 884 /* Reset SGMII */ 885 soc_reg_field_set(unit, reg, &rval, RSTB_HWf, 0); 886 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, reg, pmq_port, 0, rval)); 887 sal_usleep(sleep_usec + 10000); 888 889 /* Bring SGMII out of reset */ 890 soc_reg_field_set(unit, reg, &rval, RSTB_HWf, 1); 891 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, reg, pmq_port, 0, rval)); 892 sal_usleep(sleep_usec); 893 894 /* Activate MDIO on SGMII */ 895 soc_reg_field_set(unit, reg, &rval, RSTB_MDIOREGSf, 1); 896 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, reg, pmq_port, 0, rval)); 897 sal_usleep(sleep_usec); 898 899 /* Activate clocks */ 900 soc_reg_field_set(unit, reg, &rval, RSTB_PLLf, 1); 901 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, reg, pmq_port, 0, rval)); 902 903 return SOC_E_NONE; 904 } 905 906 /* 907 * Function: 908 * soc_wolfhound2_port_reset 909 * Purpose: 910 * Special reset sequencing for BCM53540 911 */ 912 int 913 soc_wolfhound2_port_reset(int unit) 914 { 915 int blk; 916 917 SOC_BLOCK_ITER(unit, blk, SOC_BLK_PMQ) { 918 if (SOC_BLOCK_NUMBER(unit, blk) == 2) { 919 /* reset SGMII_4P1 */ 920 SOC_IF_ERROR_RETURN(soc_wh2_sgmii_init(unit, 1)); 921 } else { 922 SOC_IF_ERROR_RETURN( 923 soc_wh2_gphy_pmq_init(unit, SOC_BLOCK_NUMBER(unit, blk))); 924 } 925 } 926 return SOC_E_NONE; 927 } 928 929 /* 930 * Function: 931 * soc_wolfhound2_chip_reset 932 * Purpose: 933 * Special reset sequencing for BCM53540 934 */ 935 int 936 soc_wolfhound2_chip_reset(int unit) 937 { 938 uint32 to_usec, rval; 939 int option; 940 soc_info_t *si; 941 uint32 strap_sts_1, value, qgphy_core_map; 942 wh2_sku_info_t *matched_port_config = NULL; 943 uint8 qgphy5_lane, sgmii_4p0_lane; 944 945 to_usec = SAL_BOOT_QUICKTURN ? (250 * MILLISECOND_USEC) : 946 (10 * MILLISECOND_USEC); 947 948 WRITE_CMIC_SBUS_RING_MAP_0_7r(unit, 0x00000000); /* block 7 - 0 */ 949 WRITE_CMIC_SBUS_RING_MAP_8_15r(unit, 0x00430000); /* block 15 - 8 */ 950 WRITE_CMIC_SBUS_RING_MAP_16_23r(unit, 0x00005064); /* block 23 - 16 */ 951 WRITE_CMIC_SBUS_RING_MAP_24_31r(unit, 0x00000000); /* block 31 - 24 */ 952 WRITE_CMIC_SBUS_RING_MAP_32_39r(unit, 0x77772222); /* block 39 - 32 */ 953 WRITE_CMIC_SBUS_RING_MAP_40_47r(unit, 0x00000111); /* block 40 - 47 */ 954 955 WRITE_CMIC_SBUS_TIMEOUTr(unit, 0x7d0); 956 957 sal_usleep(to_usec); 958 959 960 /* Change core clock if required */ 961 si = &SOC_INFO(unit); 962 /* set core clock to 62.5MHz */ 963 if (si->frequency == 62) { 964 rval = 0x28; 965 /* set core clock to 41.67MHz */ 966 } else if (si->frequency == 41) { 967 rval = 0x3c; 968 /* set core clock to 104.17MHz */ 969 } else { 970 rval = 0x18; 971 } 972 SOC_IF_ERROR_RETURN 973 (soc_reg_field32_modify(unit, TOP_CORE_PLL_CTRL4r, 974 REG_PORT_ANY, MSTR_CH0_MDIVf, rval)); 975 976 SOC_IF_ERROR_RETURN 977 (soc_reg_field32_modify(unit, TOP_MISC_CONTROL_1r, REG_PORT_ANY, 978 CMIC_TO_CORE_PLL_LOADf, 1)); 979 980 /* Check option and strap pin status to do the proper initialization */ 981 matched_port_config = &wh2_sku_port_config[matched_devid_idx[unit]]; 982 option = matched_port_config->config_option; 983 qgphy_core_map = matched_port_config->qgphy_core_map; 984 qgphy5_lane = matched_port_config->qgphy5_lane; 985 sgmii_4p0_lane = matched_port_config->sgmii_4p0_lane; 986 #define WH2_STRAP_GPHY_SGMII_SEL_0 (1 << 0) 987 #define WH2_STRAP_GPHY_SGMII_SEL_1 (1 << 1) 988 strap_sts_1 = 0; 989 option = option % 6; 990 SOC_IF_ERROR_RETURN(READ_TOP_STRAP_STATUS_1r(unit, &strap_sts_1)); 991 /* check strap v.s. option */ 992 value = (strap_sts_1 >> 1) & 0x3; 993 if (!SAL_BOOT_SIMULATION) { 994 switch (option) { 995 case 0: 996 case 2: 997 if (value != 3) { 998 LOG_ERROR(BSL_LS_SOC_COMMON, 999 (BSL_META_U(unit, 1000 "Invalid option " 1001 "(unmatch with strap pin)"))); 1002 return SOC_E_INTERNAL; 1003 } 1004 break; 1005 case 3: 1006 case 4: 1007 if (value != 1) { 1008 LOG_ERROR(BSL_LS_SOC_COMMON, 1009 (BSL_META_U(unit, 1010 "Invalid option " 1011 "(unmatch with strap pin)"))); 1012 return SOC_E_INTERNAL; 1013 } 1014 break; 1015 case 1: 1016 case 5: 1017 if (value != 0) { 1018 LOG_ERROR(BSL_LS_SOC_COMMON, 1019 (BSL_META_U(unit, 1020 "Invalid option " 1021 "(unmatch with strap pin)"))); 1022 return SOC_E_INTERNAL; 1023 } 1024 break; 1025 } 1026 1027 if (value & WH2_STRAP_GPHY_SGMII_SEL_0) { 1028 /* front ports select GPHY */ 1029 if (!(qgphy_core_map & 0x20) || !(qgphy5_lane & 0x3)) { 1030 LOG_ERROR(BSL_LS_SOC_COMMON, 1031 (BSL_META_U(unit, 1032 "Invalid option " 1033 "(unmatch with strap pin)"))); 1034 return SOC_E_INTERNAL; 1035 } 1036 } 1037 if (value & WH2_STRAP_GPHY_SGMII_SEL_1) { 1038 /* front ports select GPHY, OOB port select SGMII */ 1039 if (!(qgphy_core_map & 0x20) || !(qgphy5_lane & 0xC)) { 1040 LOG_ERROR(BSL_LS_SOC_COMMON, 1041 (BSL_META_U(unit, 1042 "Invalid option " 1043 "(unmatch with strap pin)"))); 1044 return SOC_E_INTERNAL; 1045 } 1046 } 1047 } 1048 1049 /* re-ordering the port sequence if required*/ 1050 1051 /* Bring port block out of reset */ 1052 /* GPHY or SGMII configuration need to be considered here */ 1053 if (sgmii_4p0_lane) { 1054 SOC_IF_ERROR_RETURN(soc_wh2_sgmii_init(unit, 0)); 1055 } 1056 SOC_IF_ERROR_RETURN( 1057 soc_wh2_qgphy_init(unit, qgphy_core_map, qgphy5_lane)); 1058 1059 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REGr(unit, &rval)); 1060 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_GXP0_RST_Lf, 1); 1061 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_GXP1_RST_Lf, 1); 1062 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_GXP2_RST_Lf, 1); 1063 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REGr(unit, rval)); 1064 sal_usleep(to_usec); 1065 1066 /* Bring network sync out of reset */ 1067 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REGr(unit, &rval)); 1068 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_TS_RST_Lf, 1); 1069 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REGr(unit, rval)); 1070 sal_usleep(to_usec); 1071 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REG_2r(unit, &rval)); 1072 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, TOP_TS_PLL_RST_Lf, 1); 1073 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REG_2r(unit, rval)); 1074 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, 1075 TOP_TS_PLL_POST_RST_Lf, 1); 1076 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REG_2r(unit, rval)); 1077 1078 /* Bring IP, EP, and MMU blocks out of reset */ 1079 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REGr(unit, &rval)); 1080 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_EP_RST_Lf, 1); 1081 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_IP_RST_Lf, 1); 1082 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_MMU_RST_Lf, 1); 1083 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REGr(unit, rval)); 1084 sal_usleep(to_usec); 1085 1086 return SOC_E_NONE; 1087 } 1088 1089 #define WH2_MMU_IPMC_GROUP_MAX 30 1090 static soc_mem_t ipmc_mems[WH2_MMU_IPMC_GROUP_MAX] = { 1091 INVALIDm, INVALIDm, 1092 MMU_IPMC_GROUP_TBL2m, MMU_IPMC_GROUP_TBL3m, 1093 MMU_IPMC_GROUP_TBL4m, MMU_IPMC_GROUP_TBL5m, 1094 MMU_IPMC_GROUP_TBL6m, MMU_IPMC_GROUP_TBL7m, 1095 MMU_IPMC_GROUP_TBL8m, MMU_IPMC_GROUP_TBL9m, 1096 MMU_IPMC_GROUP_TBL10m, MMU_IPMC_GROUP_TBL11m, 1097 MMU_IPMC_GROUP_TBL12m, MMU_IPMC_GROUP_TBL13m, 1098 MMU_IPMC_GROUP_TBL14m, MMU_IPMC_GROUP_TBL15m, 1099 MMU_IPMC_GROUP_TBL16m, MMU_IPMC_GROUP_TBL17m, 1100 MMU_IPMC_GROUP_TBL18m, MMU_IPMC_GROUP_TBL19m, 1101 MMU_IPMC_GROUP_TBL20m, MMU_IPMC_GROUP_TBL21m, 1102 MMU_IPMC_GROUP_TBL22m, MMU_IPMC_GROUP_TBL23m, 1103 MMU_IPMC_GROUP_TBL24m, MMU_IPMC_GROUP_TBL25m, 1104 MMU_IPMC_GROUP_TBL26m, MMU_IPMC_GROUP_TBL27m, 1105 MMU_IPMC_GROUP_TBL28m, MMU_IPMC_GROUP_TBL29m 1106 }; 1107 1108 static int 1109 soc_wolfhound2_pipe_mem_clear(int unit) 1110 { 1111 uint32 rval; 1112 int pipe_init_usec, index; 1113 soc_timeout_t to; 1114 static const struct { 1115 soc_mem_t mem; 1116 uint32 skip_flags; /* always skip on QUICKTURN or XGSSIM */ 1117 } cam_list[] = { 1118 { CPU_COS_MAPm, BOOT_F_PLISIM }, 1119 { EFP_TCAMm, BOOT_F_PLISIM }, 1120 { FP_GLOBAL_MASK_TCAMm, BOOT_F_PLISIM }, 1121 { FP_TCAMm, BOOT_F_PLISIM }, 1122 { L2_USER_ENTRYm, BOOT_F_PLISIM }, 1123 { L2_USER_ENTRY_ONLYm, BOOT_F_PLISIM }, 1124 { L3_DEFIPm, BOOT_F_PLISIM }, 1125 { L3_DEFIP_ONLYm, BOOT_F_PLISIM }, 1126 { VFP_TCAMm, BOOT_F_PLISIM }, 1127 { VLAN_SUBNETm, 0 }, /* VLAN API needs all 0 mask */ 1128 { VLAN_SUBNET_ONLYm, 0 } 1129 }; 1130 1131 /* 1132 * Reset the IPIPE and EPIPE block 1133 */ 1134 rval = 0; 1135 SOC_IF_ERROR_RETURN(WRITE_ING_HW_RESET_CONTROL_1r(unit, rval)); 1136 soc_reg_field_set(unit, ING_HW_RESET_CONTROL_2r, &rval, RESET_ALLf, 1); 1137 soc_reg_field_set(unit, ING_HW_RESET_CONTROL_2r, &rval, VALIDf, 1); 1138 /* Set count to # entries in largest IPIPE table, L2_ENTRYm */ 1139 soc_reg_field_set(unit, ING_HW_RESET_CONTROL_2r, &rval, COUNTf, 0x4000); 1140 SOC_IF_ERROR_RETURN(WRITE_ING_HW_RESET_CONTROL_2r(unit, rval)); 1141 1142 rval = 0; 1143 SOC_IF_ERROR_RETURN(WRITE_EGR_HW_RESET_CONTROL_0r(unit, rval)); 1144 soc_reg_field_set(unit, EGR_HW_RESET_CONTROL_1r, &rval, RESET_ALLf, 1); 1145 soc_reg_field_set(unit, EGR_HW_RESET_CONTROL_1r, &rval, VALIDf, 1); 1146 /* Set count to # entries in largest EPIPE table, EGR_GPP_ATTRIBUTESm */ 1147 soc_reg_field_set(unit, EGR_HW_RESET_CONTROL_1r, &rval, COUNTf, 0x2000); 1148 SOC_IF_ERROR_RETURN(WRITE_EGR_HW_RESET_CONTROL_1r(unit, rval)); 1149 1150 /* For simulation, set timeout to 10 sec. Otherwise, timeout = 50 ms */ 1151 if (SAL_BOOT_SIMULATION) { 1152 pipe_init_usec = 10000000; 1153 } else { 1154 pipe_init_usec = 50000; 1155 } 1156 soc_timeout_init(&to, pipe_init_usec, 0); 1157 1158 /* Wait for IPIPE memory initialization done. */ 1159 do { 1160 SOC_IF_ERROR_RETURN(READ_ING_HW_RESET_CONTROL_2r(unit, &rval)); 1161 if (soc_reg_field_get(unit, ING_HW_RESET_CONTROL_2r, rval, DONEf)) { 1162 break; 1163 } 1164 if (soc_timeout_check(&to)) { 1165 LOG_WARN(BSL_LS_SOC_COMMON, 1166 (BSL_META_U(unit, "unit %d : ING_HW_RESET timeout\n"), 1167 unit)); 1168 break; 1169 } 1170 } while (TRUE); 1171 1172 /* Wait for EPIPE memory initialization done. */ 1173 do { 1174 SOC_IF_ERROR_RETURN(READ_EGR_HW_RESET_CONTROL_1r(unit, &rval)); 1175 if (soc_reg_field_get(unit, EGR_HW_RESET_CONTROL_1r, rval, DONEf)) { 1176 break; 1177 } 1178 if (soc_timeout_check(&to)) { 1179 LOG_WARN(BSL_LS_SOC_COMMON, 1180 (BSL_META_U(unit, "unit %d : EGR_HW_RESET timeout\n"), 1181 unit)); 1182 break; 1183 } 1184 } while (TRUE); 1185 1186 rval = 0; 1187 SOC_IF_ERROR_RETURN(WRITE_ING_HW_RESET_CONTROL_2r(unit, rval)); 1188 SOC_IF_ERROR_RETURN(WRITE_EGR_HW_RESET_CONTROL_1r(unit, rval)); 1189 1190 if (!SAL_BOOT_SIMULATION || SAL_BOOT_BCMSIM) { 1191 /* TCAM tables are not handled by hardware reset control */ 1192 for (index = 0; index < sizeof(cam_list) / sizeof(cam_list[0]); 1193 index++) { 1194 if (sal_boot_flags_get() & cam_list[index].skip_flags) { 1195 continue; 1196 } 1197 if (((cam_list[index].mem == EFP_TCAMm) || 1198 (cam_list[index].mem == VFP_TCAMm)) && 1199 (!soc_feature(unit, soc_feature_field_multi_stage))) { 1200 continue; 1201 } 1202 SOC_IF_ERROR_RETURN( 1203 soc_mem_clear(unit, cam_list[index].mem, COPYNO_ALL, TRUE)); 1204 } 1205 1206 /* MMU_IPMC_VLAN_TBL */ 1207 SOC_IF_ERROR_RETURN( 1208 soc_mem_clear(unit, MMU_IPMC_VLAN_TBLm, COPYNO_ALL, TRUE)); 1209 1210 /* MMU_IPMC_GROUP_TBLn : n is 2 ~ 31 in HR3 */ 1211 for (index = 0; index < WH2_MMU_IPMC_GROUP_MAX; index++) { 1212 if (ipmc_mems[index] != INVALIDm) { 1213 SOC_IF_ERROR_RETURN( 1214 soc_mem_clear(unit, ipmc_mems[index], COPYNO_ALL, TRUE)); 1215 } 1216 } 1217 } 1218 1219 return SOC_E_NONE; 1220 } 1221 1222 1223 STATIC int 1224 soc_wolfhound2_init_port_mapping(int unit) 1225 { 1226 soc_info_t *si; 1227 soc_mem_t mem; 1228 uint32 rval; 1229 ing_physical_to_logical_port_number_mapping_table_entry_t entry; 1230 int port, phy_port; 1231 int num_port, num_phy_port; 1232 1233 si = &SOC_INFO(unit); 1234 1235 /* Ingress physical to logical port mapping */ 1236 mem = ING_PHYSICAL_TO_LOGICAL_PORT_NUMBER_MAPPING_TABLEm; 1237 num_phy_port = soc_mem_index_count(unit, mem); 1238 sal_memset(&entry, 0, sizeof(entry)); 1239 for (phy_port = 0; phy_port < num_phy_port; phy_port++) { 1240 port = si->port_p2l_mapping[phy_port]; 1241 soc_mem_field32_set(unit, mem, &entry, LOGICAL_PORT_NUMBERf, 1242 port == -1 ? 0x3F : port); 1243 SOC_IF_ERROR_RETURN( 1244 soc_mem_write(unit, mem, MEM_BLOCK_ALL, phy_port, &entry)); 1245 } 1246 num_port = soc_mem_index_count(unit, PORT_TABm); 1247 1248 /* Egress logical to physical port mapping */ 1249 for (port = 0; port < num_port; port++) { 1250 phy_port = si->port_l2p_mapping[port]; 1251 rval = 0; 1252 soc_reg_field_set(unit, EGR_LOGICAL_TO_PHYSICAL_PORT_NUMBER_MAPPINGr, 1253 &rval, PHYSICAL_PORT_NUMBERf, 1254 phy_port == -1 ? 0x3F : phy_port); 1255 SOC_IF_ERROR_RETURN( 1256 WRITE_EGR_LOGICAL_TO_PHYSICAL_PORT_NUMBER_MAPPINGr(unit, port, 1257 rval)); 1258 } 1259 /* MMU logical to physical port mapping */ 1260 /*(Here, Same as Egress logical to physical port mapping) */ 1261 for (port = 0; port < num_port; port++) { 1262 phy_port = si->port_m2p_mapping[port]; 1263 if (phy_port != -1) { 1264 rval = 0; 1265 soc_reg_field_set(unit, LOG_TO_PHY_PORT_MAPPINGr, &rval, 1266 PHY_PORTf, phy_port); 1267 SOC_IF_ERROR_RETURN( 1268 WRITE_LOG_TO_PHY_PORT_MAPPINGr(unit, port, rval)); 1269 } 1270 } 1271 1272 return SOC_E_NONE; 1273 } 1274 1275 STATIC int 1276 soc_wolfhound2_pgw_ge_tdm_config(int unit) 1277 { 1278 int blk, instance, phy_port, port, bindex; 1279 uint32 rval; 1280 int ge0, ge1; 1281 soc_driver_t *d = SOC_DRIVER(unit); 1282 int num_blktype, i; 1283 soc_info_t *si = &SOC_INFO(unit); 1284 1285 /* The value of the PGW_GE TDM mode depends on the active port numbers */ 1286 num_blktype = d->port_num_blktype; 1287 SOC_BLOCK_ITER(unit, blk, SOC_BLK_PGW_GE) { 1288 /* iter pgw_ge0 ~ pgw_ge2 */ 1289 instance = SOC_BLOCK_PORT(unit, blk); 1290 ge0 = ge1 = 0; 1291 SOC_PBMP_ITER(si->block_bitmap[blk], port) { 1292 /* iter the valid port in pgw_gex */ 1293 phy_port = si->port_l2p_mapping[port]; 1294 for (i = 0; i < num_blktype; i++) { 1295 if (d->port_info[phy_port * num_blktype + i].blk == blk) { 1296 /* get index of pgw_gex */ 1297 bindex = d->port_info[phy_port * num_blktype + i].bindex; 1298 if (bindex < 8) { 1299 /* index 0-7 controlled by PGW_GE0_MODE_REG */ 1300 ge0++; 1301 } else { 1302 /* index 8-15 controlled by PGW_GE1_MODE_REG */ 1303 ge1++; 1304 } 1305 } 1306 } 1307 } 1308 SOC_IF_ERROR_RETURN(READ_PGW_GE0_MODE_REGr(unit, instance, &rval)); 1309 soc_reg_field_set(unit, PGW_GE0_MODE_REGr, &rval, GP0_TDM_MODEf, ge0); 1310 SOC_IF_ERROR_RETURN(WRITE_PGW_GE0_MODE_REGr(unit, instance, rval)); 1311 SOC_IF_ERROR_RETURN(READ_PGW_GE1_MODE_REGr(unit, instance, &rval)); 1312 soc_reg_field_set(unit, PGW_GE1_MODE_REGr, &rval, GP0_TDM_MODEf, ge1); 1313 SOC_IF_ERROR_RETURN(WRITE_PGW_GE1_MODE_REGr(unit, instance, rval)); 1314 } 1315 return SOC_E_NONE; 1316 } 1317 1318 #define wh2_get_pval(_map_, _idx_, _max_num_) \ 1319 ((_idx_ < _max_num_) ? _map_[_idx_]: 0) 1320 1321 #define WH2_PGW_COUNT_GE12P (2) 1322 #define WH2_PORTS_PER_PGW_GE12P (12) 1323 #define WH2_FIRST_PORT_PGW_GE12P0_0 (2) 1324 #define WH2_FIRST_PORT_PGW_GE12P1_0 (18) 1325 1326 #define WH2_PGW_COUNT_GE4P (1) 1327 #define WH2_PORTS_PER_PGW_GE4P (4) 1328 #define WH2_FIRST_PORT_PGW_GE4P0 (34) 1329 1330 STATIC int 1331 soc_wolfhound2_ledup_init(int unit) 1332 { 1333 int i, j, pval0, pval1, pval2, pval3, port_idx; 1334 uint32 led_remap[64] = {0}, port_cnt = 0, rval = 0; 1335 1336 struct led_remap_t { 1337 uint32 reg_addr; 1338 uint32 port0; 1339 uint32 port1; 1340 uint32 port2; 1341 uint32 port3; 1342 } ledup0_remap_r[] = { 1343 {CMIC_LEDUP0_PORT_ORDER_REMAP_0_3r, 1344 REMAP_PORT_0f, REMAP_PORT_1f, REMAP_PORT_2f, REMAP_PORT_3f}, 1345 {CMIC_LEDUP0_PORT_ORDER_REMAP_4_7r, 1346 REMAP_PORT_4f, REMAP_PORT_5f, REMAP_PORT_6f, REMAP_PORT_7f}, 1347 {CMIC_LEDUP0_PORT_ORDER_REMAP_8_11r, 1348 REMAP_PORT_8f, REMAP_PORT_9f, REMAP_PORT_10f, REMAP_PORT_11f}, 1349 {CMIC_LEDUP0_PORT_ORDER_REMAP_12_15r, 1350 REMAP_PORT_12f, REMAP_PORT_13f, REMAP_PORT_14f, REMAP_PORT_15f}, 1351 {CMIC_LEDUP0_PORT_ORDER_REMAP_16_19r, 1352 REMAP_PORT_16f, REMAP_PORT_17f, REMAP_PORT_18f, REMAP_PORT_19f}, 1353 {CMIC_LEDUP0_PORT_ORDER_REMAP_20_23r, 1354 REMAP_PORT_20f, REMAP_PORT_21f, REMAP_PORT_22f, REMAP_PORT_23f}, 1355 {CMIC_LEDUP0_PORT_ORDER_REMAP_24_27r, 1356 REMAP_PORT_24f, REMAP_PORT_25f, REMAP_PORT_26f, REMAP_PORT_27f}, 1357 {CMIC_LEDUP0_PORT_ORDER_REMAP_28_31r, 1358 REMAP_PORT_28f, REMAP_PORT_29f, REMAP_PORT_30f, REMAP_PORT_31f}, 1359 {CMIC_LEDUP0_PORT_ORDER_REMAP_32_35r, 1360 REMAP_PORT_32f, REMAP_PORT_33f, REMAP_PORT_34f, REMAP_PORT_35f}, 1361 {CMIC_LEDUP0_PORT_ORDER_REMAP_36_39r, 1362 REMAP_PORT_36f, REMAP_PORT_37f, REMAP_PORT_38f, REMAP_PORT_39f}, 1363 {CMIC_LEDUP0_PORT_ORDER_REMAP_40_43r, 1364 REMAP_PORT_40f, REMAP_PORT_41f, REMAP_PORT_42f, REMAP_PORT_43f} 1365 }; 1366 1367 /* The LED scanning out order is 1368 * PGW_GE4P(37->34) -> PGW_GE12P1(18->29) -> PGW_GE12P0(13->2) 1369 */ 1370 1371 /* PGW_GE4P(34->37) */ 1372 for (i = WH2_PGW_COUNT_GE4P - 1; i >= 0; i--) { 1373 for (j = 0; j < WH2_PORTS_PER_PGW_GE4P; j++) { 1374 led_remap[port_cnt++] = 1375 WH2_FIRST_PORT_PGW_GE4P0 + WH2_PORTS_PER_PGW_GE4P * i + j; 1376 } 1377 } 1378 1379 /* PGW_GE12P1 -> PGW_GE12P0 */ 1380 for (i = WH2_PGW_COUNT_GE12P - 1; i >= 0; i--) { 1381 for (j = 0; j < WH2_PORTS_PER_PGW_GE12P; j++) { 1382 /* Not consecutive port mapping */ 1383 if (i == 1) { 1384 led_remap[port_cnt++] = 1385 WH2_FIRST_PORT_PGW_GE12P1_0 + j; 1386 } else { 1387 led_remap[port_cnt++] = 1388 WH2_FIRST_PORT_PGW_GE12P0_0 + j; 1389 } 1390 } 1391 } 1392 1393 /* Setup CMIC_LEDUP0_PORT_ORDER_REMAP registers */ 1394 for (i = 0; i < sizeof(ledup0_remap_r) / sizeof(ledup0_remap_r[0]); i++) { 1395 port_idx = i * 4; 1396 pval0 = wh2_get_pval(led_remap, port_idx, port_cnt); 1397 pval1 = wh2_get_pval(led_remap, port_idx + 1, port_cnt); 1398 pval2 = wh2_get_pval(led_remap, port_idx + 2, port_cnt); 1399 pval3 = wh2_get_pval(led_remap, port_idx + 3, port_cnt); 1400 1401 rval = 0; 1402 soc_reg_field_set(unit, ledup0_remap_r[i].reg_addr, &rval, 1403 ledup0_remap_r[i].port0, pval0); 1404 soc_reg_field_set(unit, ledup0_remap_r[i].reg_addr, &rval, 1405 ledup0_remap_r[i].port1, pval1); 1406 soc_reg_field_set(unit, ledup0_remap_r[i].reg_addr, &rval, 1407 ledup0_remap_r[i].port2, pval2); 1408 soc_reg_field_set(unit, ledup0_remap_r[i].reg_addr, &rval, 1409 ledup0_remap_r[i].port3, pval3); 1410 1411 /* coverity[result_independent_of_operands] */ 1412 SOC_IF_ERROR_RETURN 1413 (soc_pci_write(unit, 1414 soc_reg_addr(unit, ledup0_remap_r[i].reg_addr, 1415 REG_PORT_ANY, 0),rval)); 1416 } 1417 1418 /* Initialize the LEDuP0 data ram */ 1419 rval = 0; 1420 for (i = 0; i < 256; i++) { 1421 /* coverity[result_independent_of_operands] */ 1422 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP0_DATA_RAMr(unit, i, rval)); 1423 } 1424 1425 return SOC_E_NONE; 1426 } 1427 1428 STATIC int 1429 soc_wolfhound2_misc_init(int unit) 1430 { 1431 int blk, parity_enable, port, l2_ovf_enable, l2_tbl_size; 1432 uint32 rval, fval; 1433 soc_field_t fields[3]; 1434 uint32 values[3]; 1435 uint32 entry[SOC_MAX_MEM_WORDS]; 1436 uint64 reg64; 1437 int freq, target_freq, divisor, dividend, delay; 1438 soc_info_t *si = &SOC_INFO(unit); 1439 1440 /* Stop the mem scan task before all of the parity init takes place */ 1441 SOC_IF_ERROR_RETURN(soc_generic_ser_mem_scan_stop(unit)); 1442 1443 if (!SOC_IS_RELOADING(unit) && !SOC_WARM_BOOT(unit)) { 1444 /* Clear IPIPE/EPIPE Memories */ 1445 SOC_IF_ERROR_RETURN(soc_wolfhound2_pipe_mem_clear(unit)); 1446 /* PGW_GE TDM mode */ 1447 SOC_IF_ERROR_RETURN(soc_wolfhound2_pgw_ge_tdm_config(unit)); 1448 } 1449 SOC_IF_ERROR_RETURN(soc_wolfhound2_init_port_mapping(unit)); 1450 1451 parity_enable = soc_property_get(unit, spn_PARITY_ENABLE, TRUE); 1452 soc_hr3_ser_register(unit); 1453 if (parity_enable) { 1454 SOC_IF_ERROR_RETURN(soc_hr3_tcam_ser_init(unit)); 1455 /* Enabling the packet drop when parity error occurred */ 1456 SOC_IF_ERROR_RETURN(READ_IPIPE_PERR_CONTROLr(unit, &rval)); 1457 fval = 1; 1458 soc_reg_field_set(unit, IPIPE_PERR_CONTROLr, &rval, DROPf, fval); 1459 SOC_IF_ERROR_RETURN(WRITE_IPIPE_PERR_CONTROLr(unit, rval)); 1460 SOC_IF_ERROR_RETURN(soc_hr3_ser_enable_all(unit, TRUE)); 1461 #if defined(SER_TR_TEST_SUPPORT) 1462 soc_hr3_ser_test_register(unit); 1463 #endif /* SER_TR_TEST_SUPPORT */ 1464 } else { 1465 SOC_IF_ERROR_RETURN(soc_hr3_ser_enable_all(unit, FALSE)); 1466 } 1467 1468 /* Enable L2 overflow bucket */ 1469 l2_tbl_size = soc_property_get(unit, spn_L2_TABLE_SIZE, FALSE); 1470 if (l2_tbl_size == (soc_mem_index_count(unit, L2Xm) + 1471 soc_mem_index_count(unit, L2_ENTRY_OVERFLOWm))) { 1472 /* 1473 * if l2 table size equals to l2 table size + l2 overflow table size, 1474 * it indicates the l2 overflow table is enabled. 1475 */ 1476 l2_ovf_enable = 1; 1477 } else { 1478 l2_ovf_enable = 0; 1479 } 1480 SOC_IF_ERROR_RETURN(READ_L2_LEARN_CONTROLr(unit, &rval)); 1481 soc_reg_field_set(unit, L2_LEARN_CONTROLr, &rval, 1482 OVERFLOW_BUCKET_ENABLEf, l2_ovf_enable); 1483 SOC_IF_ERROR_RETURN(WRITE_L2_LEARN_CONTROLr(unit, rval)); 1484 SOC_CONTROL_LOCK(unit); 1485 SOC_CONTROL(unit)->l2_overflow_bucket_enable = l2_ovf_enable; 1486 SOC_CONTROL_UNLOCK(unit); 1487 1488 /* Enable L2 overflow interrupt */ 1489 if (soc_property_get(unit, spn_L2_OVERFLOW_EVENT, FALSE)) { 1490 SOC_CONTROL_LOCK(unit); 1491 SOC_CONTROL(unit)->l2_overflow_enable = TRUE; 1492 SOC_CONTROL_UNLOCK(unit); 1493 SOC_IF_ERROR_RETURN(soc_hr3_l2_overflow_start(unit)); 1494 } else { 1495 SOC_CONTROL_LOCK(unit); 1496 SOC_CONTROL(unit)->l2_overflow_enable = FALSE; 1497 SOC_CONTROL_UNLOCK(unit); 1498 SOC_IF_ERROR_RETURN(soc_hr3_l2_overflow_stop(unit)); 1499 } 1500 1501 /* Port related init */ 1502 /* Enable GPORT */ 1503 rval = 0; 1504 soc_reg_field_set(unit, GPORT_CONFIGr, &rval, CLR_CNTf, 1); 1505 soc_reg_field_set(unit, GPORT_CONFIGr, &rval, GPORT_ENf, 1); 1506 SOC_BLOCK_ITER(unit, blk, SOC_BLK_GPORT) { 1507 port = SOC_BLOCK_PORT(unit, blk); 1508 SOC_IF_ERROR_RETURN(WRITE_GPORT_CONFIGr(unit, port, rval)); 1509 } 1510 soc_reg_field_set(unit, GPORT_CONFIGr, &rval, CLR_CNTf, 0); 1511 SOC_BLOCK_ITER(unit, blk, SOC_BLK_GPORT) { 1512 port = SOC_BLOCK_PORT(unit, blk); 1513 SOC_IF_ERROR_RETURN(WRITE_GPORT_CONFIGr(unit, port, rval)); 1514 } 1515 1516 /* MMU related init */ 1517 SOC_IF_ERROR_RETURN(READ_MISCCONFIGr(unit, &rval)); 1518 soc_reg_field_set(unit, MISCCONFIGr, &rval, METERING_CLK_ENf, 1); 1519 SOC_IF_ERROR_RETURN(WRITE_MISCCONFIGr(unit, rval)); 1520 1521 /* Enable dual hash on L2 and L3 tables */ 1522 fields[0] = ENABLEf; 1523 values[0] = 1; 1524 fields[1] = HASH_SELECTf; 1525 values[1] = FB_HASH_CRC32_LOWER; 1526 fields[2] = INSERT_LEAST_FULL_HALFf; 1527 values[2] = 1; 1528 SOC_IF_ERROR_RETURN( 1529 soc_reg_fields32_modify(unit, L2_AUX_HASH_CONTROLr, REG_PORT_ANY, 3, 1530 fields, values)); 1531 SOC_IF_ERROR_RETURN( 1532 soc_reg_fields32_modify(unit, L3_AUX_HASH_CONTROLr, REG_PORT_ANY, 3, 1533 fields, values)); 1534 1535 /* 1536 * Egress Enable 1537 */ 1538 sal_memset(entry, 0, sizeof(egr_enable_entry_t)); 1539 soc_mem_field32_set(unit, EGR_ENABLEm, entry, PRT_ENABLEf, 1); 1540 PBMP_ALL_ITER(unit, port) { 1541 SOC_IF_ERROR_RETURN( 1542 WRITE_EGR_ENABLEm(unit, MEM_BLOCK_ALL, 1543 SOC_INFO(unit).port_l2p_mapping[port], entry)); 1544 } 1545 1546 COMPILER_64_ZERO(reg64); 1547 soc_reg64_field32_set(unit, EPC_LINK_BMAP_64r, ®64, PORT_BITMAP_LOf, 1548 SOC_PBMP_WORD_GET(PBMP_CMIC(unit), 0)); 1549 SOC_IF_ERROR_RETURN(WRITE_EPC_LINK_BMAP_64r(unit, reg64)); 1550 1551 SOC_IF_ERROR_RETURN(READ_ING_CONFIG_64r(unit, ®64)); 1552 soc_reg64_field32_set(unit, ING_CONFIG_64r, ®64, 1553 L3SRC_HIT_ENABLEf, 1); 1554 soc_reg64_field32_set(unit, ING_CONFIG_64r, ®64, 1555 L2DST_HIT_ENABLEf, 1); 1556 soc_reg64_field32_set(unit, ING_CONFIG_64r, ®64, 1557 APPLY_EGR_MASK_ON_L2f, 1); 1558 soc_reg64_field32_set(unit, ING_CONFIG_64r, ®64, 1559 APPLY_EGR_MASK_ON_L3f, 1); 1560 soc_reg64_field32_set(unit, ING_CONFIG_64r, ®64, 1561 ARP_RARP_TO_FPf, 0x3); /* enable both ARP & RARP */ 1562 soc_reg64_field32_set(unit, ING_CONFIG_64r, ®64, 1563 ARP_VALIDATION_ENf, 1); 1564 soc_reg64_field32_set(unit, ING_CONFIG_64r, ®64, 1565 IGNORE_HG_HDR_LAG_FAILOVERf, 1); 1566 SOC_IF_ERROR_RETURN(WRITE_ING_CONFIG_64r(unit, reg64)); 1567 1568 SOC_IF_ERROR_RETURN(READ_EGR_CONFIG_1r(unit, &rval)); 1569 soc_reg_field_set(unit, EGR_CONFIG_1r, &rval, RING_MODEf, 1); 1570 SOC_IF_ERROR_RETURN(WRITE_EGR_CONFIG_1r(unit, rval)); 1571 1572 /* 1573 * The HW defaults for EGR_VLAN_CONTROL_1.VT_MISS_UNTAG == 1, which 1574 * causes the outer tag to be removed from packets that don't have 1575 * a hit in the egress vlan tranlation table. Set to 0 to disable this. 1576 */ 1577 rval = 0; 1578 soc_reg_field_set(unit, EGR_VLAN_CONTROL_1r, &rval, VT_MISS_UNTAGf, 0); 1579 1580 /* Enable pri/cfi remarking on egress ports. */ 1581 soc_reg_field_set(unit, EGR_VLAN_CONTROL_1r, &rval, REMARK_OUTER_DOT1Pf, 1582 1); 1583 PBMP_ALL_ITER(unit, port) { 1584 SOC_IF_ERROR_RETURN(WRITE_EGR_VLAN_CONTROL_1r(unit, port, rval)); 1585 } 1586 1587 /* Multicast range initialization */ 1588 SOC_IF_ERROR_RETURN( 1589 soc_hbx_higig2_mcast_sizes_set( 1590 unit, 1591 soc_property_get(unit, spn_HIGIG2_MULTICAST_VLAN_RANGE, 1592 SOC_HBX_MULTICAST_RANGE_DEFAULT), 1593 soc_property_get(unit, spn_HIGIG2_MULTICAST_L2_RANGE, 1594 SOC_HBX_MULTICAST_RANGE_DEFAULT), 1595 soc_property_get(unit, spn_HIGIG2_MULTICAST_L3_RANGE, 1596 SOC_HBX_MULTICAST_RANGE_DEFAULT))); 1597 1598 /* Setup SW2_FP_DST_ACTION_CONTROL */ 1599 fields[0] = HGTRUNK_RES_ENf; 1600 fields[1] = LAG_RES_ENf; 1601 values[0] = values[1] = 1; 1602 SOC_IF_ERROR_RETURN( 1603 soc_reg_fields32_modify(unit, SW2_FP_DST_ACTION_CONTROLr, 1604 REG_PORT_ANY, 2, fields, values)); 1605 1606 /* Directed Mirroring ON by default except for CPU port */ 1607 /* 1608 * The src_port info will be changed as egress port 1609 * if EM_SRCMOD_CHANGEf = 1 1610 */ 1611 PBMP_PORT_ITER(unit, port) { 1612 SOC_IF_ERROR_RETURN(READ_EGR_PORT_64r(unit, port, ®64)); 1613 soc_reg64_field32_set(unit, EGR_PORT_64r, ®64, EM_SRCMOD_CHANGEf, 1); 1614 SOC_IF_ERROR_RETURN(WRITE_EGR_PORT_64r(unit, port, reg64)); 1615 SOC_IF_ERROR_RETURN(READ_IEGR_PORT_64r(unit, port, ®64)); 1616 soc_reg64_field32_set(unit, IEGR_PORT_64r, ®64, 1617 EM_SRCMOD_CHANGEf, 1); 1618 SOC_IF_ERROR_RETURN(WRITE_IEGR_PORT_64r(unit, port, reg64)); 1619 } 1620 1621 SOC_IF_ERROR_RETURN(_soc_hr3_l3iif_hw_mem_init(unit, TRUE)); 1622 1623 1624 freq = si->frequency; 1625 1626 /* 1627 * Set external MDIO freq to around 10MHz 1628 * target_freq = core_clock_freq * DIVIDEND / DIVISOR / 2 1629 */ 1630 if (!SOC_WARM_BOOT(unit)) { 1631 target_freq = 10; 1632 divisor = (freq + (target_freq * 2 - 1)) / (target_freq * 2); 1633 divisor = soc_property_get(unit, spn_RATE_EXT_MDIO_DIVISOR, divisor); 1634 dividend = soc_property_get(unit, spn_RATE_EXT_MDIO_DIVIDEND, 1); 1635 1636 rval = 0; 1637 soc_reg_field_set(unit, CMIC_RATE_ADJUSTr, &rval, DIVISORf, divisor); 1638 soc_reg_field_set(unit, CMIC_RATE_ADJUSTr, &rval, DIVIDENDf, dividend); 1639 /* coverity[result_independent_of_operands] */ 1640 SOC_IF_ERROR_RETURN(WRITE_CMIC_RATE_ADJUSTr(unit, rval)); 1641 } 1642 1643 /* CMIC related */ 1644 freq = si->frequency; 1645 /* 1646 * Set internal MDIO freq to around 10MHz 1647 * Valid range is from 2.5MHz to 12.5MHz 1648 * target_freq = core_clock_freq * DIVIDEND / DIVISOR / 2 1649 * or 1650 * DIVISOR = core_clock_freq * DIVIDENT / (target_freq * 2) 1651 */ 1652 target_freq = 10; 1653 divisor = (freq + (target_freq * 2 - 1)) / (target_freq * 2); 1654 divisor = soc_property_get(unit, spn_RATE_INT_MDIO_DIVISOR, divisor); 1655 dividend = soc_property_get(unit, spn_RATE_INT_MDIO_DIVIDEND, 1); 1656 rval = 0; 1657 soc_reg_field_set (unit, CMIC_RATE_ADJUST_INT_MDIOr, &rval, DIVISORf, 1658 divisor); 1659 soc_reg_field_set (unit, CMIC_RATE_ADJUST_INT_MDIOr, &rval, DIVIDENDf, 1660 dividend); 1661 /* coverity[result_independent_of_operands] */ 1662 SOC_IF_ERROR_RETURN(WRITE_CMIC_RATE_ADJUST_INT_MDIOr(unit, rval)); 1663 1664 delay = soc_property_get(unit, spn_MDIO_OUTPUT_DELAY, -1); 1665 if (delay >= 1 && delay <= 15) { 1666 /* coverity[result_independent_of_operands] */ 1667 SOC_IF_ERROR_RETURN(READ_CMIC_MIIM_CONFIGr(unit, &rval)); 1668 soc_reg_field_set(unit, CMIC_MIIM_CONFIGr, &rval, MDIO_OUT_DELAYf, 1669 delay); 1670 /* coverity[result_independent_of_operands] */ 1671 SOC_IF_ERROR_RETURN(WRITE_CMIC_MIIM_CONFIGr(unit, rval)); 1672 } 1673 1674 /* LEDuP init */ 1675 SOC_IF_ERROR_RETURN(soc_wolfhound2_ledup_init(unit)); 1676 1677 /* MSPI init */ 1678 if (soc_mspi_init(unit) != SOC_E_NONE) { 1679 LOG_WARN(BSL_LS_SOC_COMMON, 1680 (BSL_META_U(unit, "MSPI Init Failed\n"))); 1681 } 1682 1683 /* I2C set to Master Mode through Override Strap */ 1684 /* coverity[result_independent_of_operands] */ 1685 SOC_IF_ERROR_RETURN(READ_CMIC_OVERRIDE_STRAPr(unit, &rval)); 1686 soc_reg_field_set(unit, CMIC_OVERRIDE_STRAPr, &rval, 1687 ENABLE_OVERRIDE_I2C_MASTER_SLAVE_MODEf, 1); 1688 soc_reg_field_set(unit, CMIC_OVERRIDE_STRAPr, &rval, 1689 I2C_MASTER_SLAVE_MODEf, 1); 1690 /* coverity[result_independent_of_operands] */ 1691 SOC_IF_ERROR_RETURN(WRITE_CMIC_OVERRIDE_STRAPr(unit, rval)); 1692 1693 return SOC_E_NONE; 1694 } 1695 1696 STATIC int 1697 soc_wolfhound2_tdm_init(int unit) 1698 { 1699 int tdm_size; 1700 uint32 rval; 1701 iarb_tdm_table_entry_t iarb_tdm; 1702 mmu_arb_tdm_table_entry_t mmu_arb_tdm; 1703 int i, port, phy_port; 1704 wh2_sku_info_t *matched_sku_info; 1705 const int *arr = NULL; 1706 1707 SOC_IF_ERROR_RETURN(READ_IARB_TDM_CONTROLr(unit, &rval)); 1708 soc_reg_field_set(unit, IARB_TDM_CONTROLr, &rval, DISABLEf, 1); 1709 soc_reg_field_set(unit, IARB_TDM_CONTROLr, &rval, TDM_WRAP_PTRf, 83); 1710 SOC_IF_ERROR_RETURN(WRITE_IARB_TDM_CONTROLr(unit, rval)); 1711 1712 if (matched_devid_idx[unit] == -1) { 1713 LOG_WARN(BSL_LS_SOC_COMMON, 1714 (BSL_META_U(unit, "Warning: soc_wolfhound2_port_config_init " 1715 "should be invoked first! " 1716 "Choose bcm53540 port config.\n"))); 1717 matched_devid_idx[unit] = 0; 1718 } 1719 matched_sku_info = &wh2_sku_port_config[matched_devid_idx[unit]]; 1720 1721 arr = matched_sku_info->tdm_table; 1722 tdm_size = matched_sku_info->tdm_table_size; 1723 1724 if (arr == NULL) { 1725 return SOC_E_CONFIG; 1726 } 1727 1728 for (i = 0; i < tdm_size; i++) { 1729 phy_port = arr[i]; 1730 port = (phy_port != 63) ? matched_sku_info->p2l_mapping[phy_port] : 63; 1731 sal_memset(&iarb_tdm, 0, sizeof(iarb_tdm_table_entry_t)); 1732 sal_memset(&mmu_arb_tdm, 0, sizeof(mmu_arb_tdm_table_entry_t)); 1733 1734 soc_IARB_TDM_TABLEm_field32_set(unit, &iarb_tdm, PORT_NUMf, 1735 phy_port); 1736 1737 soc_MMU_ARB_TDM_TABLEm_field32_set(unit, &mmu_arb_tdm, PORT_NUMf, 1738 (port != -1) ? port : 63); 1739 if (i == tdm_size - 1) { 1740 soc_MMU_ARB_TDM_TABLEm_field32_set(unit, &mmu_arb_tdm, WRAP_ENf, 1); 1741 } 1742 SOC_IF_ERROR_RETURN(WRITE_IARB_TDM_TABLEm(unit, SOC_BLOCK_ALL, i, 1743 &iarb_tdm)); 1744 SOC_IF_ERROR_RETURN(WRITE_MMU_ARB_TDM_TABLEm(unit, SOC_BLOCK_ALL, i, 1745 &mmu_arb_tdm)); 1746 } 1747 rval = 0; 1748 soc_reg_field_set(unit, IARB_TDM_CONTROLr, &rval, DISABLEf, 0); 1749 soc_reg_field_set(unit, IARB_TDM_CONTROLr, &rval, TDM_WRAP_PTRf, 1750 tdm_size -1); 1751 SOC_IF_ERROR_RETURN(WRITE_IARB_TDM_CONTROLr(unit, rval)); 1752 1753 return SOC_E_NONE; 1754 } 1755 1756 #define CELL_SIZE 128 1757 1758 /* Maximum device supported number of COSQ. */ 1759 #define WH2_QUEUE_MAX_NUM 8 1760 /* Default configured number of COSQ. */ 1761 #define WH2_QUEUE_DEFAULT_NUM 4 1762 1763 typedef struct soc_wh2_mmu_params_s { 1764 /*_traffic_attributes_*/ 1765 uint32 min_packet_size_traffic_attr; /* c7 */ 1766 uint32 ethernet_mtu_traffic_attr; /* c8 */ 1767 uint32 max_packet_size_traffic_attr; /* c9 */ 1768 uint32 standard_jumbo_frame_traffic_attr; /* c10 */ 1769 uint32 lossless_traffic_mtu_size_traffic_attr; /* c11 */ 1770 1771 /*_sw_config_property_*/ 1772 uint32 total_physical_memory_sw_cfg; /* c14 */ 1773 uint32 cfapfullsetpoint_sw_cfg; /* c15 */ 1774 uint32 total_cell_memory_for_admission_sw_cfg; /* c16 */ 1775 uint32 num_1g_ports_uplink_ports_sw_cfg; /* c17 configurable */ 1776 uint32 num_2p5g_ports_uplink_ports_sw_cfg; /* c18 configurable */ 1777 /* for lossy or lossles(pause) mode */ 1778 uint32 num_1g_ports_downlink_ports_sw_cfg; /* c19 configurable */ 1779 uint32 num_2p5g_ports_downlink_ports_sw_cfg; /* c20 configurable */ 1780 /* for lossy+lossless(pfc) mode */ 1781 uint32 num_lossy_downlink_ports_sw_cfg; /* c19 configurable */ 1782 uint32 num_lossless_downlink_ports_sw_cfg; /* c20 configurable */ 1783 1784 uint32 number_of_uplink_ports_sw_cfg; /* c21 */ 1785 uint32 number_of_downlink_ports_sw_cfg; /* c22 */ 1786 uint32 flow_control_enabled_sw_cfg; /* c23 lossy, lossless */ 1787 uint32 flow_control_type_sw_cfg; /* c24 pause=0, pfc=1 */ 1788 uint32 queue_port_limit_ratio_sw_cfg; /* c25 */ 1789 1790 /*_sw_config_parameter_*/ 1791 uint32 egress_queue_min_reserve_uplink_ports_lossy; /* c29 */ 1792 uint32 egress_queue_min_reserve_downlink_ports_lossy; /* c30 */ 1793 uint32 egress_queue_min_reserve_uplink_ports_lossless; /* c31 */ 1794 uint32 egress_queue_min_reserve_downlink_ports_lossless; /* c32 */ 1795 uint32 egress_queue_min_reserve_cpu_ports; /* c33 */ 1796 uint32 egress_xq_min_reserve_lossy_uplink_and_downlink_ports; /* c34 */ 1797 uint32 egress_xq_min_reserve_lossless_uplink_ports; /* c35 */ 1798 uint32 egress_xq_min_reserve_lossless_downlink_ports; /* c36 */ 1799 uint32 num_total_pri_groups; /* c37 */ 1800 uint32 num_active_pri_group_lossless; /* c38 */ 1801 uint32 num_lossless_queues; /* c39 */ 1802 uint32 num_lossy_queues; /* c40 */ 1803 uint32 mmu_xoff_pkt_threshold_uplink_ports; /* c41 */ 1804 uint32 mmu_xoff_pkt_threshold_downlink_ports; /* c42 */ 1805 uint32 mmu_xoff_cell_threshold_1g_port_uplink_ports; /* c43 */ 1806 uint32 mmu_xoff_cell_threshold_2p5g_port_uplink_ports; /* c44 */ 1807 1808 /* for lossy or lossles(pause) mode */ 1809 uint32 mmu_xoff_cell_threshold_1g_downlink_ports; /* c45 */ 1810 uint32 mmu_xoff_cell_threshold_2p5g_downlink_ports; /* c46 */ 1811 /* for lossy+lossless(pfc) mode */ 1812 uint32 mmu_xoff_cell_threshold_downlink_lossy_ports; /* c45 */ 1813 uint32 mmu_xoff_cell_threshold_downlink_lossless_ports; /* c46 */ 1814 1815 /*_device_attributes_*/ 1816 uint32 cell_size; /* c49 */ 1817 uint32 num_egress_queues_per_port; /* c50 */ 1818 uint32 num_cpu_queues; /* c51 */ 1819 uint32 num_1g_ports_uplink_ports; /* c52 */ 1820 uint32 num_2p5g_ports_uplink_ports; /* c53 */ 1821 1822 /* for lossy or lossles(pause) mode */ 1823 uint32 num_1g_ports_downlink_ports; /* c54 */ 1824 uint32 num_2p5g_ports_downlink_ports; /* c55 */ 1825 /* for lossy+lossless(pfc) mode */ 1826 uint32 num_lossy_downlink_ports; /* c54 */ 1827 uint32 num_lossless_downlink_ports; /* c55 */ 1828 1829 uint32 num_cpu_ports; /* c56 */ 1830 uint32 number_of_uplink_ports; /* c57 */ 1831 uint32 number_of_downlink_ports; /* c58 */ 1832 uint32 total_physical_memory; /* c59 */ 1833 uint32 total_cell_memory; /* c60 */ 1834 uint32 total_advertised_cell_memory; /* c61 */ 1835 uint32 numxq_per_uplink_ports; /* c62 */ 1836 uint32 numxq_per_downlink_ports_and_cpu_port; /* c63 */ 1837 uint32 the_number_of_pipelines_per_device; /* c64 */ 1838 1839 uint32 n_egress_queues_active_per_xpe; /* c66 */ 1840 uint32 n_ingress_ports_active_per_xpe; /* c67 */ 1841 1842 /*_reservations_*/ 1843 uint32 wrr_reserve; /* c70 */ 1844 uint32 reserved_for_cfap; /* c71 */ 1845 uint32 skidmarker; /* c72 */ 1846 uint32 skidmarker_option; /* c73 */ 1847 uint32 prefetch; /* c74 */ 1848 1849 /*_intermediate_results_*/ 1850 /*_general_information_*/ 1851 uint32 min_packet_size; /* c79 */ 1852 uint32 ethernet_mtu; /* c80 */ 1853 uint32 max_packet_size; /* c81 */ 1854 uint32 standard_jumbo_frame; /* c82 */ 1855 uint32 lossless_traffic_mtu_size; /* c83 */ 1856 /*_ingress_thresholds_*/ 1857 /* for lossy or lossles(pause) mode */ 1858 uint32 headroom_for_1g_port; /* c85 */ 1859 uint32 headroom_for_2p5g_port; /* c86 */ 1860 /* for lossy+lossless(pfc) mode */ 1861 /* Skipped c85 in this mode */ 1862 uint32 headroom_for_lossless_downlink_port; /* c86 */ 1863 1864 /* for lossy or lossles(pause) mode */ 1865 uint32 xoff_cell_thresholds_per_port_pg_1g_port_downlink_ports; /* c87 */ 1866 uint32 xoff_cell_thresholds_per_port_pg_2p5g_port_downlink_ports; /* c88 */ 1867 /* for lossy+lossless(pfc) mode */ 1868 uint32 xoff_cell_thresholds_per_port_pg_downlink_lossy_ports; /* c87 */ 1869 uint32 xoff_cell_thresholds_per_port_pg_downlink_lossless_ports; /* c88 */ 1870 1871 uint32 xoff_cell_threshold_1g_uplink_ports; /* c89 */ 1872 uint32 xoff_cell_threshold_2p5g_uplink_ports; /* c90 */ 1873 uint32 xoff_packet_thresholds_per_port_uplink_port; /* c91 */ 1874 uint32 xoff_packet_thresholds_per_port_downlink_port; /* c92 */ 1875 1876 /* for lossy or lossles(pause) mode */ 1877 uint32 discard_limit_per_port_pg_downlink_1g_port; /* c93 */ 1878 /* for lossy+lossless(pfc) mode */ 1879 uint32 discard_limit_per_port_pg_lossy_downlink_port; /* c93 */ 1880 1881 uint32 discard_limit_per_port_pg_downlink_2p5g_port; /* c94 */ 1882 uint32 discard_limit_per_port_pg_uplink_port; /* c95 */ 1883 /*_egress_thresholds_*/ 1884 uint32 total_reserved_cells_for_uplink_ports; /* c97 */ 1885 uint32 total_reserved_cells_for_downlink_ports; /* c98 */ 1886 uint32 total_reserved_cells_for_cpu_port; /* c99 */ 1887 uint32 total_reserved; /* c100 */ 1888 uint32 shared_space_cells; /* c101 */ 1889 uint32 reserved_xqs_per_uplink_port; /* c102 */ 1890 uint32 shared_xqs_per_uplink_port; /* c103 */ 1891 uint32 reserved_xqs_per_downlink_port; /* c104 */ 1892 uint32 shared_xqs_per_downlink_port; /* c105 */ 1893 uint32 reserved_xqs_at_cpu_port; /* c106 */ 1894 uint32 shared_xqs_at_cpu_port; /* c107 */ 1895 } soc_wh2_mmu_params_t; 1896 soc_wh2_mmu_params_t mmu_params; 1897 1898 STATIC 1899 uint32 _ceil_func(uint32 numerators , uint32 denominator) 1900 { 1901 uint32 result; 1902 if (denominator == 0) { 1903 return 0xFFFFFFFF; 1904 } 1905 result = numerators / denominator; 1906 if (numerators % denominator != 0) { 1907 result++; 1908 } 1909 return result; 1910 } 1911 1912 STATIC int 1913 soc_wolfhound2_mmu_lossy_lossless_pfc_config_helper(int unit) 1914 { 1915 uint32 val = 0; 1916 uint32 fld_val = 0; 1917 uint32 tmp = 0; 1918 int port; /* logical port id */ 1919 int pport; /* physical port id */ 1920 int speed; 1921 int cos; 1922 int i; 1923 int lossless_port = 0; 1924 uint32 ibppktsetlimit_pktsetlimit; 1925 uint32 ibppktsetlimit_resetlimitsel; 1926 uint32 mmu_fc_rx_en_mmu_fc_rx_enable; 1927 uint32 mmu_fc_tx_en_mmu_fc_tx_enable; 1928 uint32 pgcelllimit_0_2__cellsetlimit; 1929 uint32 pgcelllimit_3__cellsetlimit; 1930 uint32 pgcelllimit_4_7__cellsetlimit; 1931 uint32 pgcelllimit_0_2__cellresetlimit; 1932 uint32 pgcelllimit_3__cellresetlimit; 1933 uint32 pgcelllimit_4_7__cellresetlimit; 1934 uint32 pgdiscardsetlimit_0_2__discardsetlimit; 1935 uint32 pgdiscardsetlimit_3__discardsetlimit; 1936 uint32 pgdiscardsetlimit_4_7__discardsetlimit; 1937 uint32 holcosminxqcnt_0_2__holcosminxqcnt; 1938 uint32 holcosminxqcnt_3__holcosminxqcnt; 1939 uint32 holcosminxqcnt_4_7__holcosminxqcnt; 1940 uint32 holcospktsetlimit_0_2__pktsetlimit; 1941 uint32 holcospktsetlimit_3__pktsetlimit; 1942 uint32 holcospktsetlimit_4_7__pktsetlimit; 1943 uint32 holcospktresetlimit_0_2__pktresetlimit; 1944 uint32 holcospktresetlimit_3__pktresetlimit; 1945 uint32 holcospktresetlimit_4_7__pktresetlimit; 1946 uint32 cngcospktlimit0_0_7__cngpktsetlimit0; 1947 uint32 cngcospktlimit1_0_7__cngpktsetlimit1; 1948 uint32 cngportpktlimit0_cngportpktlimit0; 1949 uint32 cngportpktlimit1_cngportpktlimit1; 1950 uint32 dynxqcntport_dynxqcntport; 1951 uint32 dynresetlimport_dynresetlimport; 1952 uint32 lwmcoscellsetlimit_0_2__cellsetlimit; 1953 uint32 lwmcoscellsetlimit_3__cellsetlimit; 1954 uint32 lwmcoscellsetlimit_4_7__cellsetlimit; 1955 uint32 lwmcoscellsetlimit_0_2__cellresetlimit; 1956 uint32 lwmcoscellsetlimit_3__cellresetlimit; 1957 uint32 lwmcoscellsetlimit_4_7__cellresetlimit; 1958 uint32 holcoscellmaxlimit_0_2__cellmaxlimit; 1959 uint32 holcoscellmaxlimit_3__cellmaxlimit; 1960 uint32 holcoscellmaxlimit_4_7__cellmaxlimit; 1961 uint32 holcoscellmaxlimit_0_2__cellmaxresumelimit; 1962 uint32 holcoscellmaxlimit_3__cellmaxresumelimit; 1963 uint32 holcoscellmaxlimit_4_7__cellmaxresumelimit; 1964 uint32 dyncelllimit_dyncellsetlimit; 1965 uint32 dyncelllimit_dyncellresetlimit; 1966 uint32 color_drop_en_color_drop_en; 1967 uint32 shared_pool_ctrl_dynamic_cos_drop_en; 1968 uint32 shared_pool_ctrl_shared_pool_discard_en; 1969 uint32 shared_pool_ctrl_sharded_pool_xoff_en; 1970 1971 soc_pbmp_t pbmp_lossless; 1972 1973 SOC_PBMP_CLEAR(pbmp_lossless); 1974 pbmp_lossless = soc_property_get_pbmp_default(unit, spn_MMU_LOSSLESS_PBMP, 1975 pbmp_lossless); 1976 1977 SOC_IF_ERROR_RETURN(READ_CFAPFULLTHRESHOLDr(unit, &val)); 1978 /* i6 = c15 */ 1979 soc_reg_field_set(unit, CFAPFULLTHRESHOLDr, &val, 1980 CFAPFULLSETPOINTf, 1981 mmu_params.cfapfullsetpoint_sw_cfg); 1982 /* i7 = i6 - c82 */ 1983 soc_reg_field_set(unit, CFAPFULLTHRESHOLDr, &val, 1984 CFAPFULLRESETPOINTf, 1985 mmu_params.cfapfullsetpoint_sw_cfg - \ 1986 mmu_params.standard_jumbo_frame); 1987 SOC_IF_ERROR_RETURN(WRITE_CFAPFULLTHRESHOLDr(unit, val)); 1988 1989 /* i10 = c16 */ 1990 SOC_IF_ERROR_RETURN(READ_GBLLIMITSETLIMITr(unit, &val)); 1991 soc_reg_field_set(unit, GBLLIMITSETLIMITr, &val, 1992 GBLCELLSETLIMITf, 1993 mmu_params.total_cell_memory_for_admission_sw_cfg); 1994 SOC_IF_ERROR_RETURN(WRITE_GBLLIMITSETLIMITr(unit, val)); 1995 1996 /* i11 = i10 */ 1997 SOC_IF_ERROR_RETURN(READ_GBLLIMITRESETLIMITr(unit, &val)); 1998 soc_reg_field_set(unit, GBLLIMITRESETLIMITr, &val, 1999 GBLCELLRESETLIMITf, 2000 mmu_params.total_cell_memory_for_admission_sw_cfg); 2001 SOC_IF_ERROR_RETURN(WRITE_GBLLIMITRESETLIMITr(unit, val)); 2002 2003 /* Device Wide - Egress Thresholds */ 2004 val = 0; 2005 /* i15 = c101 */ 2006 soc_reg_field_set(unit, TOTALDYNCELLSETLIMITr, 2007 &val, TOTALDYNCELLSETLIMITf, 2008 mmu_params.shared_space_cells); 2009 SOC_IF_ERROR_RETURN(WRITE_TOTALDYNCELLSETLIMITr(unit, val)); 2010 val = 0; 2011 /* i16 =i15-c82*2*/ 2012 soc_reg_field_set(unit, TOTALDYNCELLRESETLIMITr, 2013 &val, TOTALDYNCELLRESETLIMITf, 2014 mmu_params.shared_space_cells - \ 2015 (mmu_params.standard_jumbo_frame * 2)); 2016 SOC_IF_ERROR_RETURN(WRITE_TOTALDYNCELLRESETLIMITr(unit, val)); 2017 2018 /* MICCONFIGr */ 2019 SOC_IF_ERROR_RETURN(READ_MISCCONFIGr(unit, &val)); 2020 soc_reg_field_set(unit, MISCCONFIGr, &val, MULTIPLE_ACCOUNTING_FIX_ENf, 1); 2021 soc_reg_field_set(unit, MISCCONFIGr, &val, CNG_DROP_ENf, 0); 2022 soc_reg_field_set(unit, MISCCONFIGr, &val, DYN_XQ_ENf, 1); 2023 soc_reg_field_set(unit, MISCCONFIGr, &val, HOL_CELL_SOP_DROP_ENf, 1); 2024 soc_reg_field_set(unit, MISCCONFIGr, &val, DYNAMIC_MEMORY_ENf, 1); 2025 soc_reg_field_set(unit, MISCCONFIGr, &val, SKIDMARKERf, 3); 2026 SOC_IF_ERROR_RETURN(WRITE_MISCCONFIGr(unit, val)); 2027 2028 PBMP_ALL_ITER(unit, port) { 2029 pport = SOC_INFO(unit).port_l2p_mapping[port]; 2030 speed = SOC_INFO(unit).port_speed_max[port]; 2031 2032 /* Settings based on port type */ 2033 if (IS_CPU_PORT(unit, port)) { 2034 val = 0; 2035 if (mmu_params.flow_control_type_sw_cfg) { 2036 /* PFC */ 2037 soc_reg_field_set(unit, PG_CTRL0r, &val, PPFC_PG_ENf, 0); 2038 soc_reg_field_set(unit, PG_CTRL0r, &val, PRI0_GRPf, 0); 2039 soc_reg_field_set(unit, PG_CTRL0r, &val, PRI1_GRPf, 1); 2040 soc_reg_field_set(unit, PG_CTRL0r, &val, PRI2_GRPf, 2); 2041 soc_reg_field_set(unit, PG_CTRL0r, &val, PRI3_GRPf, 3); 2042 soc_reg_field_set(unit, PG_CTRL0r, &val, PRI4_GRPf, 4); 2043 soc_reg_field_set(unit, PG_CTRL0r, &val, PRI5_GRPf, 5); 2044 soc_reg_field_set(unit, PG_CTRL0r, &val, PRI6_GRPf, 6); 2045 soc_reg_field_set(unit, PG_CTRL0r, &val, PRI7_GRPf, 7); 2046 } else { 2047 /* PAUSE */ 2048 soc_reg_field_set(unit, PG_CTRL0r, &val, PPFC_PG_ENf, 0); 2049 soc_reg_field_set(unit, PG_CTRL0r, &val, PRI0_GRPf, 3); 2050 soc_reg_field_set(unit, PG_CTRL0r, &val, PRI1_GRPf, 3); 2051 soc_reg_field_set(unit, PG_CTRL0r, &val, PRI2_GRPf, 3); 2052 soc_reg_field_set(unit, PG_CTRL0r, &val, PRI3_GRPf, 3); 2053 soc_reg_field_set(unit, PG_CTRL0r, &val, PRI4_GRPf, 3); 2054 soc_reg_field_set(unit, PG_CTRL0r, &val, PRI5_GRPf, 3); 2055 soc_reg_field_set(unit, PG_CTRL0r, &val, PRI6_GRPf, 3); 2056 soc_reg_field_set(unit, PG_CTRL0r, &val, PRI7_GRPf, 3); 2057 } 2058 SOC_IF_ERROR_RETURN(WRITE_PG_CTRL0r(unit, port, val)); 2059 val = 0; 2060 if (mmu_params.flow_control_type_sw_cfg) { 2061 /* PFC */ 2062 soc_reg_field_set(unit, PG_CTRL1r, &val, PRI8_GRPf, 7); 2063 soc_reg_field_set(unit, PG_CTRL1r, &val, PRI9_GRPf, 7); 2064 soc_reg_field_set(unit, PG_CTRL1r, &val, PRI10_GRPf, 7); 2065 soc_reg_field_set(unit, PG_CTRL1r, &val, PRI11_GRPf, 7); 2066 soc_reg_field_set(unit, PG_CTRL1r, &val, PRI12_GRPf, 7); 2067 soc_reg_field_set(unit, PG_CTRL1r, &val, PRI13_GRPf, 7); 2068 soc_reg_field_set(unit, PG_CTRL1r, &val, PRI14_GRPf, 7); 2069 soc_reg_field_set(unit, PG_CTRL1r, &val, PRI15_GRPf, 7); 2070 } else { 2071 /* PAUSE */ 2072 soc_reg_field_set(unit, PG_CTRL1r, &val, PRI8_GRPf, 3); 2073 soc_reg_field_set(unit, PG_CTRL1r, &val, PRI9_GRPf, 3); 2074 soc_reg_field_set(unit, PG_CTRL1r, &val, PRI10_GRPf, 3); 2075 soc_reg_field_set(unit, PG_CTRL1r, &val, PRI11_GRPf, 3); 2076 soc_reg_field_set(unit, PG_CTRL1r, &val, PRI12_GRPf, 3); 2077 soc_reg_field_set(unit, PG_CTRL1r, &val, PRI13_GRPf, 3); 2078 soc_reg_field_set(unit, PG_CTRL1r, &val, PRI14_GRPf, 3); 2079 soc_reg_field_set(unit, PG_CTRL1r, &val, PRI15_GRPf, 3); 2080 } 2081 SOC_IF_ERROR_RETURN(WRITE_PG_CTRL1r(unit, port, val)); 2082 2083 val = 0; 2084 soc_reg_field_set(unit, PG2TCr, &val, PG_BMPf, 0); 2085 for (i = 0; i < 8; i++) { 2086 SOC_IF_ERROR_RETURN(WRITE_PG2TCr(unit, port, i, val)); 2087 } 2088 2089 ibppktsetlimit_pktsetlimit = \ 2090 mmu_params.\ 2091 xoff_packet_thresholds_per_port_downlink_port; /* c92 */ 2092 ibppktsetlimit_resetlimitsel = 3; 2093 mmu_fc_rx_en_mmu_fc_rx_enable = 0; 2094 mmu_fc_tx_en_mmu_fc_tx_enable = 0; 2095 pgcelllimit_0_2__cellsetlimit = \ 2096 mmu_params.\ 2097 xoff_cell_thresholds_per_port_pg_downlink_lossy_ports; /*c87*/ 2098 pgcelllimit_3__cellsetlimit = \ 2099 mmu_params.\ 2100 xoff_cell_thresholds_per_port_pg_downlink_lossy_ports; /*c87*/ 2101 pgcelllimit_4_7__cellsetlimit = 0; 2102 pgcelllimit_0_2__cellresetlimit = \ 2103 mmu_params.\ 2104 xoff_cell_thresholds_per_port_pg_downlink_lossy_ports; /*c87*/ 2105 pgcelllimit_3__cellresetlimit = \ 2106 mmu_params.\ 2107 xoff_cell_thresholds_per_port_pg_downlink_lossy_ports; /*c87*/ 2108 pgcelllimit_4_7__cellresetlimit = 0; 2109 pgdiscardsetlimit_0_2__discardsetlimit = \ 2110 mmu_params.\ 2111 discard_limit_per_port_pg_lossy_downlink_port; /* c93 */ 2112 pgdiscardsetlimit_3__discardsetlimit = \ 2113 mmu_params.\ 2114 discard_limit_per_port_pg_lossy_downlink_port; /* c93 */ 2115 pgdiscardsetlimit_4_7__discardsetlimit = 0; 2116 2117 holcosminxqcnt_0_2__holcosminxqcnt = \ 2118 mmu_params.egress_queue_min_reserve_cpu_ports; /* c33 */ 2119 holcosminxqcnt_3__holcosminxqcnt = \ 2120 mmu_params.egress_queue_min_reserve_cpu_ports; /* c33 */ 2121 holcosminxqcnt_4_7__holcosminxqcnt = \ 2122 mmu_params.egress_queue_min_reserve_cpu_ports; /* c33 */ 2123 holcospktsetlimit_0_2__pktsetlimit = \ 2124 mmu_params.shared_xqs_at_cpu_port - \ 2125 mmu_params.skidmarker - \ 2126 mmu_params.prefetch + \ 2127 holcosminxqcnt_0_2__holcosminxqcnt; /* C107-C72-C74+Q70 */ 2128 holcospktsetlimit_3__pktsetlimit = \ 2129 mmu_params.shared_xqs_at_cpu_port - \ 2130 mmu_params.skidmarker - \ 2131 mmu_params.prefetch + \ 2132 holcosminxqcnt_3__holcosminxqcnt; /* C107-C72-C74+Q71 */ 2133 holcospktsetlimit_4_7__pktsetlimit = \ 2134 mmu_params.shared_xqs_at_cpu_port - \ 2135 mmu_params.skidmarker - \ 2136 mmu_params.prefetch + \ 2137 holcosminxqcnt_4_7__holcosminxqcnt; /* C107-C72-C74+Q72 */ 2138 holcospktresetlimit_0_2__pktresetlimit = \ 2139 holcospktsetlimit_0_2__pktsetlimit - 1; /* q73 - 1 */ 2140 holcospktresetlimit_3__pktresetlimit = \ 2141 holcospktsetlimit_3__pktsetlimit - 1; /* q74 - 1 */ 2142 holcospktresetlimit_4_7__pktresetlimit = \ 2143 holcospktsetlimit_4_7__pktsetlimit - 1; /* q75 - 1 */ 2144 cngcospktlimit0_0_7__cngpktsetlimit0 = \ 2145 mmu_params.numxq_per_downlink_ports_and_cpu_port - 1; /*c63-1*/ 2146 cngcospktlimit1_0_7__cngpktsetlimit1 = \ 2147 mmu_params.numxq_per_downlink_ports_and_cpu_port - 1; /*c63-1*/ 2148 cngportpktlimit0_cngportpktlimit0 = \ 2149 mmu_params.numxq_per_downlink_ports_and_cpu_port - 1; /*c63-1*/ 2150 cngportpktlimit1_cngportpktlimit1 = \ 2151 mmu_params.numxq_per_downlink_ports_and_cpu_port - 1; /*c63-1*/ 2152 dynxqcntport_dynxqcntport = \ 2153 mmu_params.shared_xqs_at_cpu_port - \ 2154 mmu_params.skidmarker - \ 2155 mmu_params.prefetch; /* c107-c72-c74 */ 2156 dynresetlimport_dynresetlimport = \ 2157 dynxqcntport_dynxqcntport - 2; /* q83 - 2 */ 2158 lwmcoscellsetlimit_0_2__cellsetlimit = \ 2159 mmu_params.egress_queue_min_reserve_cpu_ports; /* c33 */ 2160 lwmcoscellsetlimit_3__cellsetlimit = \ 2161 mmu_params.egress_queue_min_reserve_cpu_ports; /* c33 */ 2162 lwmcoscellsetlimit_4_7__cellsetlimit = \ 2163 mmu_params.egress_queue_min_reserve_cpu_ports; /* c33 */ 2164 lwmcoscellsetlimit_0_2__cellresetlimit = \ 2165 mmu_params.egress_queue_min_reserve_cpu_ports; /* c33 */ 2166 lwmcoscellsetlimit_3__cellresetlimit = \ 2167 mmu_params.egress_queue_min_reserve_cpu_ports; /* c33 */ 2168 lwmcoscellsetlimit_4_7__cellresetlimit = \ 2169 mmu_params.egress_queue_min_reserve_cpu_ports; /* c33 */ 2170 /* CEILING(c101*C25+Q85, 1) */ 2171 tmp = _ceil_func((mmu_params.shared_space_cells * 10 / 4), 10); 2172 holcoscellmaxlimit_0_2__cellmaxlimit = \ 2173 tmp + lwmcoscellsetlimit_0_2__cellsetlimit; 2174 /* CEILING(c101*C25+Q86, 1) */ 2175 tmp = _ceil_func((mmu_params.shared_space_cells * 10 / 4), 10); 2176 holcoscellmaxlimit_3__cellmaxlimit = \ 2177 tmp + lwmcoscellsetlimit_3__cellsetlimit; 2178 /* CEILING(c101*C25+Q87, 1) */ 2179 tmp = _ceil_func((mmu_params.shared_space_cells * 10 / 4), 10); 2180 holcoscellmaxlimit_4_7__cellmaxlimit = \ 2181 tmp + lwmcoscellsetlimit_4_7__cellsetlimit; 2182 holcoscellmaxlimit_0_2__cellmaxresumelimit = \ 2183 holcoscellmaxlimit_0_2__cellmaxlimit - \ 2184 mmu_params.ethernet_mtu; /* q91 - c83 */ 2185 holcoscellmaxlimit_3__cellmaxresumelimit = \ 2186 holcoscellmaxlimit_3__cellmaxlimit - \ 2187 mmu_params.ethernet_mtu; /* q92 - c83 */ 2188 holcoscellmaxlimit_4_7__cellmaxresumelimit = \ 2189 holcoscellmaxlimit_4_7__cellmaxlimit - \ 2190 mmu_params.ethernet_mtu; /* q93 - c83 */ 2191 dyncelllimit_dyncellsetlimit = \ 2192 mmu_params.shared_space_cells; /* c101 */ 2193 dyncelllimit_dyncellresetlimit = \ 2194 dyncelllimit_dyncellsetlimit - \ 2195 (mmu_params.ethernet_mtu * 2); /* q97-c83*2 */ 2196 color_drop_en_color_drop_en = 0; 2197 shared_pool_ctrl_dynamic_cos_drop_en = 255; 2198 shared_pool_ctrl_shared_pool_discard_en = 255; 2199 shared_pool_ctrl_sharded_pool_xoff_en = 0; 2200 } else if (pport >= 34) { /* uplink port 1G, 2.5G*/ 2201 if (SOC_PBMP_MEMBER(pbmp_lossless, port)) { 2202 /* no lossless config allowed on uplink ports */ 2203 LOG_WARN(BSL_LS_SOC_COMMON, 2204 (BSL_META_U(unit, 2205 "unit %d : MMU lossless configuration is " 2206 "not available on uplink port %d. " 2207 "No lossless setting will be applied " 2208 "to the port.\n"), 2209 unit, port)); 2210 } 2211 2212 val = 0; 2213 if (mmu_params.flow_control_type_sw_cfg) { 2214 /* PFC */ 2215 soc_reg_field_set(unit, PG_CTRL0r, &val, PPFC_PG_ENf, 0); 2216 soc_reg_field_set(unit, PG_CTRL0r, &val, PRI0_GRPf, 0); 2217 soc_reg_field_set(unit, PG_CTRL0r, &val, PRI1_GRPf, 1); 2218 soc_reg_field_set(unit, PG_CTRL0r, &val, PRI2_GRPf, 2); 2219 soc_reg_field_set(unit, PG_CTRL0r, &val, PRI3_GRPf, 3); 2220 soc_reg_field_set(unit, PG_CTRL0r, &val, PRI4_GRPf, 4); 2221 soc_reg_field_set(unit, PG_CTRL0r, &val, PRI5_GRPf, 5); 2222 soc_reg_field_set(unit, PG_CTRL0r, &val, PRI6_GRPf, 6); 2223 soc_reg_field_set(unit, PG_CTRL0r, &val, PRI7_GRPf, 7); 2224 } else { 2225 /* PAUSE */ 2226 soc_reg_field_set(unit, PG_CTRL0r, &val, PPFC_PG_ENf, 0); 2227 soc_reg_field_set(unit, PG_CTRL0r, &val, PRI0_GRPf, 3); 2228 soc_reg_field_set(unit, PG_CTRL0r, &val, PRI1_GRPf, 3); 2229 soc_reg_field_set(unit, PG_CTRL0r, &val, PRI2_GRPf, 3); 2230 soc_reg_field_set(unit, PG_CTRL0r, &val, PRI3_GRPf, 3); 2231 soc_reg_field_set(unit, PG_CTRL0r, &val, PRI4_GRPf, 3); 2232 soc_reg_field_set(unit, PG_CTRL0r, &val, PRI5_GRPf, 3); 2233 soc_reg_field_set(unit, PG_CTRL0r, &val, PRI6_GRPf, 3); 2234 soc_reg_field_set(unit, PG_CTRL0r, &val, PRI7_GRPf, 3); 2235 } 2236 SOC_IF_ERROR_RETURN(WRITE_PG_CTRL0r(unit, port, val)); 2237 val = 0; 2238 if (mmu_params.flow_control_type_sw_cfg) { 2239 /* PFC */ 2240 soc_reg_field_set(unit, PG_CTRL1r, &val, PRI8_GRPf, 7); 2241 soc_reg_field_set(unit, PG_CTRL1r, &val, PRI9_GRPf, 7); 2242 soc_reg_field_set(unit, PG_CTRL1r, &val, PRI10_GRPf, 7); 2243 soc_reg_field_set(unit, PG_CTRL1r, &val, PRI11_GRPf, 7); 2244 soc_reg_field_set(unit, PG_CTRL1r, &val, PRI12_GRPf, 7); 2245 soc_reg_field_set(unit, PG_CTRL1r, &val, PRI13_GRPf, 7); 2246 soc_reg_field_set(unit, PG_CTRL1r, &val, PRI14_GRPf, 7); 2247 soc_reg_field_set(unit, PG_CTRL1r, &val, PRI15_GRPf, 7); 2248 } else { 2249 /* PAUSE */ 2250 soc_reg_field_set(unit, PG_CTRL1r, &val, PRI8_GRPf, 3); 2251 soc_reg_field_set(unit, PG_CTRL1r, &val, PRI9_GRPf, 3); 2252 soc_reg_field_set(unit, PG_CTRL1r, &val, PRI10_GRPf, 3); 2253 soc_reg_field_set(unit, PG_CTRL1r, &val, PRI11_GRPf, 3); 2254 soc_reg_field_set(unit, PG_CTRL1r, &val, PRI12_GRPf, 3); 2255 soc_reg_field_set(unit, PG_CTRL1r, &val, PRI13_GRPf, 3); 2256 soc_reg_field_set(unit, PG_CTRL1r, &val, PRI14_GRPf, 3); 2257 soc_reg_field_set(unit, PG_CTRL1r, &val, PRI15_GRPf, 3); 2258 } 2259 SOC_IF_ERROR_RETURN(WRITE_PG_CTRL1r(unit, port, val)); 2260 val = 0; 2261 soc_reg_field_set(unit, PG2TCr, &val, PG_BMPf, 0); 2262 for (i = 0; i < 8; i++) { 2263 SOC_IF_ERROR_RETURN(WRITE_PG2TCr(unit, port, i, val)); 2264 } 2265 2266 if (speed == 10) { /* 1G */ 2267 /* c89 */ 2268 pgcelllimit_0_2__cellsetlimit = \ 2269 mmu_params.\ 2270 xoff_cell_threshold_1g_uplink_ports; 2271 /* c89 */ 2272 pgcelllimit_3__cellsetlimit = \ 2273 mmu_params.\ 2274 xoff_cell_threshold_1g_uplink_ports; 2275 pgcelllimit_4_7__cellsetlimit = 0; 2276 /* c89 */ 2277 pgcelllimit_0_2__cellresetlimit = \ 2278 mmu_params.\ 2279 xoff_cell_threshold_1g_uplink_ports; 2280 /* c89 */ 2281 pgcelllimit_3__cellresetlimit = \ 2282 mmu_params.\ 2283 xoff_cell_threshold_1g_uplink_ports; 2284 pgcelllimit_4_7__cellresetlimit = 0; 2285 } else { /* 2.5 G */ 2286 /* c90 */ 2287 pgcelllimit_0_2__cellsetlimit = \ 2288 mmu_params.\ 2289 xoff_cell_threshold_2p5g_uplink_ports; 2290 /* c90 */ 2291 pgcelllimit_3__cellsetlimit = \ 2292 mmu_params.\ 2293 xoff_cell_threshold_2p5g_uplink_ports; 2294 pgcelllimit_4_7__cellsetlimit = 0; 2295 /* c90 */ 2296 pgcelllimit_0_2__cellresetlimit = \ 2297 mmu_params.\ 2298 xoff_cell_threshold_2p5g_uplink_ports; 2299 /* c90 */ 2300 pgcelllimit_3__cellresetlimit = \ 2301 mmu_params.\ 2302 xoff_cell_threshold_2p5g_uplink_ports; 2303 pgcelllimit_4_7__cellresetlimit = 0; 2304 } 2305 /* c91 */ 2306 ibppktsetlimit_pktsetlimit = \ 2307 mmu_params.\ 2308 xoff_packet_thresholds_per_port_uplink_port; 2309 ibppktsetlimit_resetlimitsel = 3; 2310 mmu_fc_rx_en_mmu_fc_rx_enable = 0; 2311 mmu_fc_tx_en_mmu_fc_tx_enable = 0; 2312 /* c95 */ 2313 pgdiscardsetlimit_0_2__discardsetlimit = \ 2314 mmu_params.discard_limit_per_port_pg_uplink_port; 2315 /* c95 */ 2316 pgdiscardsetlimit_3__discardsetlimit = \ 2317 mmu_params.discard_limit_per_port_pg_uplink_port; 2318 pgdiscardsetlimit_4_7__discardsetlimit = 0; 2319 2320 /* c34 */ 2321 holcosminxqcnt_0_2__holcosminxqcnt = \ 2322 mmu_params.\ 2323 egress_xq_min_reserve_lossy_uplink_and_downlink_ports; 2324 /* c35 */ 2325 holcosminxqcnt_3__holcosminxqcnt = \ 2326 mmu_params.\ 2327 egress_xq_min_reserve_lossless_uplink_ports; 2328 holcosminxqcnt_4_7__holcosminxqcnt = 0; 2329 /* C103-C72-C74+C34 */ 2330 holcospktsetlimit_0_2__pktsetlimit = \ 2331 mmu_params.shared_xqs_per_uplink_port - \ 2332 mmu_params.skidmarker - \ 2333 mmu_params.prefetch + \ 2334 holcosminxqcnt_0_2__holcosminxqcnt; 2335 /* C103-C72-C74+c35 */ 2336 holcospktsetlimit_3__pktsetlimit = \ 2337 mmu_params.shared_xqs_per_uplink_port - \ 2338 mmu_params.skidmarker - \ 2339 mmu_params.prefetch + \ 2340 holcosminxqcnt_3__holcosminxqcnt; 2341 holcospktsetlimit_4_7__pktsetlimit = 0; 2342 holcospktresetlimit_0_2__pktresetlimit = \ 2343 /* m73 - 1 */ 2344 holcospktsetlimit_0_2__pktsetlimit - 1; 2345 /* m74 - 1 */ 2346 holcospktresetlimit_3__pktresetlimit = \ 2347 holcospktsetlimit_3__pktsetlimit - 1; 2348 holcospktresetlimit_4_7__pktresetlimit = 0; 2349 /* c62 - 1 */ 2350 cngcospktlimit0_0_7__cngpktsetlimit0 = \ 2351 mmu_params.numxq_per_uplink_ports - 1; 2352 /* c62 - 1 */ 2353 cngcospktlimit1_0_7__cngpktsetlimit1 = \ 2354 mmu_params.numxq_per_uplink_ports - 1; 2355 /* c62 - 1 */ 2356 cngportpktlimit0_cngportpktlimit0 = \ 2357 mmu_params.numxq_per_uplink_ports - 1; 2358 /* c62 - 1 */ 2359 cngportpktlimit1_cngportpktlimit1 = \ 2360 mmu_params.numxq_per_uplink_ports - 1; 2361 /* c103-c72-c74 */ 2362 dynxqcntport_dynxqcntport = \ 2363 mmu_params.shared_xqs_per_uplink_port - \ 2364 mmu_params.skidmarker - \ 2365 mmu_params.prefetch; 2366 /* m83 - 2 */ 2367 dynresetlimport_dynresetlimport = \ 2368 dynxqcntport_dynxqcntport - 2; 2369 /* c29 */ 2370 lwmcoscellsetlimit_0_2__cellsetlimit = \ 2371 mmu_params.egress_queue_min_reserve_uplink_ports_lossy; 2372 /* c31 */ 2373 lwmcoscellsetlimit_3__cellsetlimit = \ 2374 mmu_params.egress_queue_min_reserve_uplink_ports_lossless; 2375 lwmcoscellsetlimit_4_7__cellsetlimit = 0; 2376 /* c29 */ 2377 lwmcoscellsetlimit_0_2__cellresetlimit = \ 2378 mmu_params.egress_queue_min_reserve_uplink_ports_lossy; 2379 /* c31 */ 2380 lwmcoscellsetlimit_3__cellresetlimit = \ 2381 mmu_params.egress_queue_min_reserve_uplink_ports_lossless; 2382 lwmcoscellsetlimit_4_7__cellresetlimit = 0; 2383 /* CEILING(c101*C25+o85, 1) */ 2384 tmp = _ceil_func((mmu_params.shared_space_cells * 10 / 4), 10); 2385 holcoscellmaxlimit_0_2__cellmaxlimit = \ 2386 tmp + lwmcoscellsetlimit_0_2__cellsetlimit; 2387 /* CEILING(c101*C25+o85, 1) */ 2388 tmp = _ceil_func((mmu_params.shared_space_cells * 10 / 4), 10); 2389 holcoscellmaxlimit_3__cellmaxlimit = \ 2390 tmp + lwmcoscellsetlimit_0_2__cellsetlimit; 2391 holcoscellmaxlimit_4_7__cellmaxlimit = 0; 2392 /* o91 - c80 */ 2393 holcoscellmaxlimit_0_2__cellmaxresumelimit = \ 2394 holcoscellmaxlimit_0_2__cellmaxlimit - \ 2395 mmu_params.ethernet_mtu; 2396 /* o91 - c80 */ 2397 holcoscellmaxlimit_3__cellmaxresumelimit = \ 2398 holcoscellmaxlimit_0_2__cellmaxlimit - \ 2399 mmu_params.ethernet_mtu; 2400 holcoscellmaxlimit_4_7__cellmaxresumelimit = 0; 2401 /* c101 */ 2402 dyncelllimit_dyncellsetlimit = \ 2403 mmu_params.shared_space_cells; 2404 /* o97-c80*2 */ 2405 dyncelllimit_dyncellresetlimit = \ 2406 dyncelllimit_dyncellsetlimit - \ 2407 (mmu_params.ethernet_mtu * 2); 2408 color_drop_en_color_drop_en = 0; 2409 shared_pool_ctrl_dynamic_cos_drop_en = 255; 2410 shared_pool_ctrl_shared_pool_discard_en = 255; 2411 shared_pool_ctrl_sharded_pool_xoff_en = 0; 2412 } else { /* downlink port lossy, lossless */ 2413 lossless_port = 0; 2414 if (SOC_PBMP_MEMBER(pbmp_lossless, port)) { 2415 lossless_port = 1; 2416 } 2417 2418 val = 0; 2419 if (lossless_port) { 2420 soc_reg_field_set(unit, PG_CTRL0r, &val, PPFC_PG_ENf, 0x8); 2421 } else { 2422 soc_reg_field_set(unit, PG_CTRL0r, &val, PPFC_PG_ENf, 0); 2423 } 2424 if (mmu_params.flow_control_type_sw_cfg) { 2425 /* PFC */ 2426 soc_reg_field_set(unit, PG_CTRL0r, &val, PRI0_GRPf, 0); 2427 soc_reg_field_set(unit, PG_CTRL0r, &val, PRI1_GRPf, 1); 2428 soc_reg_field_set(unit, PG_CTRL0r, &val, PRI2_GRPf, 2); 2429 soc_reg_field_set(unit, PG_CTRL0r, &val, PRI3_GRPf, 3); 2430 soc_reg_field_set(unit, PG_CTRL0r, &val, PRI4_GRPf, 4); 2431 soc_reg_field_set(unit, PG_CTRL0r, &val, PRI5_GRPf, 5); 2432 soc_reg_field_set(unit, PG_CTRL0r, &val, PRI6_GRPf, 6); 2433 soc_reg_field_set(unit, PG_CTRL0r, &val, PRI7_GRPf, 7); 2434 } else { 2435 /* PAUSE */ 2436 soc_reg_field_set(unit, PG_CTRL0r, &val, PRI0_GRPf, 3); 2437 soc_reg_field_set(unit, PG_CTRL0r, &val, PRI1_GRPf, 3); 2438 soc_reg_field_set(unit, PG_CTRL0r, &val, PRI2_GRPf, 3); 2439 soc_reg_field_set(unit, PG_CTRL0r, &val, PRI3_GRPf, 3); 2440 soc_reg_field_set(unit, PG_CTRL0r, &val, PRI4_GRPf, 3); 2441 soc_reg_field_set(unit, PG_CTRL0r, &val, PRI5_GRPf, 3); 2442 soc_reg_field_set(unit, PG_CTRL0r, &val, PRI6_GRPf, 3); 2443 soc_reg_field_set(unit, PG_CTRL0r, &val, PRI7_GRPf, 3); 2444 } 2445 SOC_IF_ERROR_RETURN(WRITE_PG_CTRL0r(unit, port, val)); 2446 val = 0; 2447 if (mmu_params.flow_control_type_sw_cfg) { 2448 /* PFC */ 2449 soc_reg_field_set(unit, PG_CTRL1r, &val, PRI8_GRPf, 7); 2450 soc_reg_field_set(unit, PG_CTRL1r, &val, PRI9_GRPf, 7); 2451 soc_reg_field_set(unit, PG_CTRL1r, &val, PRI10_GRPf, 7); 2452 soc_reg_field_set(unit, PG_CTRL1r, &val, PRI11_GRPf, 7); 2453 soc_reg_field_set(unit, PG_CTRL1r, &val, PRI12_GRPf, 7); 2454 soc_reg_field_set(unit, PG_CTRL1r, &val, PRI13_GRPf, 7); 2455 soc_reg_field_set(unit, PG_CTRL1r, &val, PRI14_GRPf, 7); 2456 soc_reg_field_set(unit, PG_CTRL1r, &val, PRI15_GRPf, 7); 2457 } else { 2458 /* PAUSE */ 2459 soc_reg_field_set(unit, PG_CTRL1r, &val, PRI8_GRPf, 3); 2460 soc_reg_field_set(unit, PG_CTRL1r, &val, PRI9_GRPf, 3); 2461 soc_reg_field_set(unit, PG_CTRL1r, &val, PRI10_GRPf, 3); 2462 soc_reg_field_set(unit, PG_CTRL1r, &val, PRI11_GRPf, 3); 2463 soc_reg_field_set(unit, PG_CTRL1r, &val, PRI12_GRPf, 3); 2464 soc_reg_field_set(unit, PG_CTRL1r, &val, PRI13_GRPf, 3); 2465 soc_reg_field_set(unit, PG_CTRL1r, &val, PRI14_GRPf, 3); 2466 soc_reg_field_set(unit, PG_CTRL1r, &val, PRI15_GRPf, 3); 2467 } 2468 SOC_IF_ERROR_RETURN(WRITE_PG_CTRL1r(unit, port, val)); 2469 val = 0; 2470 soc_reg_field_set(unit, PG2TCr, &val, PG_BMPf, 0); 2471 for (i = 0; i < 8; i++) { 2472 SOC_IF_ERROR_RETURN(WRITE_PG2TCr(unit, port, i, val)); 2473 } 2474 if (lossless_port) { 2475 /* PG2TC(3) */ 2476 val = 0x8; 2477 SOC_IF_ERROR_RETURN(WRITE_PG2TCr(unit, port, 3, val)); 2478 } 2479 2480 if (lossless_port) { /* lossless ports */ 2481 mmu_fc_rx_en_mmu_fc_rx_enable = 0x8; 2482 mmu_fc_tx_en_mmu_fc_tx_enable = 0x8; 2483 2484 /* c87 */ 2485 pgcelllimit_0_2__cellsetlimit = \ 2486 mmu_params.\ 2487 xoff_cell_thresholds_per_port_pg_downlink_lossy_ports; 2488 /* c88 */ 2489 pgcelllimit_3__cellsetlimit = \ 2490 mmu_params.\ 2491 xoff_cell_thresholds_per_port_pg_downlink_lossless_ports; 2492 pgcelllimit_4_7__cellsetlimit = 0; 2493 /* c87 */ 2494 pgcelllimit_0_2__cellresetlimit = \ 2495 mmu_params.\ 2496 xoff_cell_thresholds_per_port_pg_downlink_lossy_ports; 2497 /* c88 */ 2498 pgcelllimit_3__cellresetlimit = \ 2499 mmu_params.\ 2500 xoff_cell_thresholds_per_port_pg_downlink_lossless_ports; 2501 pgcelllimit_4_7__cellresetlimit = 0; 2502 /* c93 */ 2503 pgdiscardsetlimit_0_2__discardsetlimit = \ 2504 mmu_params.discard_limit_per_port_pg_lossy_downlink_port; 2505 /* c94 */ 2506 pgdiscardsetlimit_3__discardsetlimit = \ 2507 mmu_params.discard_limit_per_port_pg_downlink_2p5g_port; 2508 pgdiscardsetlimit_4_7__discardsetlimit = 0; 2509 } else { /* lossy ports */ 2510 mmu_fc_rx_en_mmu_fc_rx_enable = 0; 2511 mmu_fc_tx_en_mmu_fc_tx_enable = 0; 2512 2513 /* c87 */ 2514 pgcelllimit_0_2__cellsetlimit = \ 2515 mmu_params.\ 2516 xoff_cell_thresholds_per_port_pg_downlink_lossy_ports; 2517 /* c87 */ 2518 pgcelllimit_3__cellsetlimit = \ 2519 mmu_params.\ 2520 xoff_cell_thresholds_per_port_pg_downlink_lossy_ports; 2521 pgcelllimit_4_7__cellsetlimit = 0; 2522 /* c87 */ 2523 pgcelllimit_0_2__cellresetlimit = \ 2524 mmu_params.\ 2525 xoff_cell_thresholds_per_port_pg_downlink_lossy_ports; 2526 /* c87 */ 2527 pgcelllimit_3__cellresetlimit = \ 2528 mmu_params.\ 2529 xoff_cell_thresholds_per_port_pg_downlink_lossy_ports; 2530 pgcelllimit_4_7__cellresetlimit = 0; 2531 /* c93 */ 2532 pgdiscardsetlimit_0_2__discardsetlimit = \ 2533 mmu_params.discard_limit_per_port_pg_lossy_downlink_port; 2534 /* c93 */ 2535 pgdiscardsetlimit_3__discardsetlimit = \ 2536 mmu_params.discard_limit_per_port_pg_lossy_downlink_port; 2537 pgdiscardsetlimit_4_7__discardsetlimit = 0; 2538 } 2539 /* c92 */ 2540 ibppktsetlimit_pktsetlimit = \ 2541 mmu_params.\ 2542 xoff_packet_thresholds_per_port_downlink_port; 2543 ibppktsetlimit_resetlimitsel = 3; 2544 2545 /* c34 */ 2546 holcosminxqcnt_0_2__holcosminxqcnt = \ 2547 mmu_params.\ 2548 egress_xq_min_reserve_lossy_uplink_and_downlink_ports; 2549 /* c36 */ 2550 holcosminxqcnt_3__holcosminxqcnt = \ 2551 mmu_params.\ 2552 egress_xq_min_reserve_lossless_downlink_ports; 2553 holcosminxqcnt_4_7__holcosminxqcnt = 0; 2554 /* c105-C72-C74+c34 */ 2555 holcospktsetlimit_0_2__pktsetlimit = \ 2556 mmu_params.shared_xqs_per_downlink_port - \ 2557 mmu_params.skidmarker - \ 2558 mmu_params.prefetch + \ 2559 holcosminxqcnt_0_2__holcosminxqcnt; 2560 /* c105-C72-C74+c36 */ 2561 holcospktsetlimit_3__pktsetlimit = \ 2562 mmu_params.shared_xqs_per_downlink_port - \ 2563 mmu_params.skidmarker - \ 2564 mmu_params.prefetch + \ 2565 holcosminxqcnt_3__holcosminxqcnt; 2566 holcospktsetlimit_4_7__pktsetlimit = 0; 2567 holcospktresetlimit_0_2__pktresetlimit = \ 2568 holcospktsetlimit_0_2__pktsetlimit - 1; 2569 holcospktresetlimit_3__pktresetlimit = \ 2570 holcospktsetlimit_3__pktsetlimit - 1; 2571 holcospktresetlimit_4_7__pktresetlimit = 0; 2572 /* c63 - 1 */ 2573 cngcospktlimit0_0_7__cngpktsetlimit0 = \ 2574 mmu_params.numxq_per_downlink_ports_and_cpu_port - 1; 2575 /* c63 - 1 */ 2576 cngcospktlimit1_0_7__cngpktsetlimit1 = \ 2577 mmu_params.numxq_per_downlink_ports_and_cpu_port - 1; 2578 /* c63 - 1 */ 2579 cngportpktlimit0_cngportpktlimit0 = \ 2580 mmu_params.numxq_per_downlink_ports_and_cpu_port - 1; 2581 /* c63 - 1 */ 2582 cngportpktlimit1_cngportpktlimit1 = \ 2583 mmu_params.numxq_per_downlink_ports_and_cpu_port - 1; 2584 /* c105-c72-c74 */ 2585 dynxqcntport_dynxqcntport = \ 2586 mmu_params.shared_xqs_per_downlink_port - \ 2587 mmu_params.skidmarker - \ 2588 mmu_params.prefetch; 2589 dynresetlimport_dynresetlimport = \ 2590 dynxqcntport_dynxqcntport - 2; 2591 /* c30 */ 2592 lwmcoscellsetlimit_0_2__cellsetlimit = \ 2593 mmu_params.egress_queue_min_reserve_downlink_ports_lossy; 2594 /* c32 */ 2595 lwmcoscellsetlimit_3__cellsetlimit = \ 2596 mmu_params.egress_queue_min_reserve_downlink_ports_lossless; 2597 lwmcoscellsetlimit_4_7__cellsetlimit = 0; 2598 /* c30 */ 2599 lwmcoscellsetlimit_0_2__cellresetlimit = \ 2600 mmu_params.egress_queue_min_reserve_downlink_ports_lossy; 2601 /* c32 */ 2602 lwmcoscellsetlimit_3__cellresetlimit = \ 2603 mmu_params.egress_queue_min_reserve_downlink_ports_lossless; 2604 lwmcoscellsetlimit_4_7__cellresetlimit = 0; 2605 /* CEILING(c101*C25+o85, 1) */ 2606 tmp = _ceil_func((mmu_params.shared_space_cells * 10 / 4), 10); 2607 holcoscellmaxlimit_0_2__cellmaxlimit = \ 2608 tmp + lwmcoscellsetlimit_0_2__cellsetlimit; 2609 /* CEILING(c101*C25+o85, 1) */ 2610 tmp = _ceil_func((mmu_params.shared_space_cells * 10 / 4), 10); 2611 holcoscellmaxlimit_3__cellmaxlimit = \ 2612 tmp + lwmcoscellsetlimit_0_2__cellsetlimit; 2613 holcoscellmaxlimit_4_7__cellmaxlimit = 0; 2614 /* I91-C80 */ 2615 holcoscellmaxlimit_0_2__cellmaxresumelimit = \ 2616 holcoscellmaxlimit_0_2__cellmaxlimit - \ 2617 mmu_params.ethernet_mtu; 2618 /* I91-C80 */ 2619 holcoscellmaxlimit_3__cellmaxresumelimit = \ 2620 holcoscellmaxlimit_0_2__cellmaxlimit - \ 2621 mmu_params.ethernet_mtu; 2622 holcoscellmaxlimit_4_7__cellmaxresumelimit = 0; 2623 /* c101 */ 2624 dyncelllimit_dyncellsetlimit = \ 2625 mmu_params.shared_space_cells; 2626 /* o97-c80*2 */ 2627 dyncelllimit_dyncellresetlimit = \ 2628 dyncelllimit_dyncellsetlimit - \ 2629 (mmu_params.ethernet_mtu * 2); 2630 color_drop_en_color_drop_en = 0; 2631 shared_pool_ctrl_dynamic_cos_drop_en = 255; 2632 shared_pool_ctrl_shared_pool_discard_en = 255; 2633 shared_pool_ctrl_sharded_pool_xoff_en = 0; 2634 } 2635 2636 /* Program the setting */ 2637 val = 0; 2638 /* i52 = c92 */ 2639 soc_reg_field_set(unit, IBPPKTSETLIMITr, &val, PKTSETLIMITf, 2640 ibppktsetlimit_pktsetlimit); 2641 soc_reg_field_set(unit, IBPPKTSETLIMITr, &val, RESETLIMITSELf, 2642 ibppktsetlimit_resetlimitsel); 2643 SOC_IF_ERROR_RETURN(WRITE_IBPPKTSETLIMITr(unit, port, val)); 2644 2645 val = 0; 2646 soc_reg_field_set(unit, MMU_FC_RX_ENr, &val, MMU_FC_RX_ENABLEf, 2647 mmu_fc_rx_en_mmu_fc_rx_enable); 2648 SOC_IF_ERROR_RETURN(WRITE_MMU_FC_RX_ENr(unit, port, val)); 2649 val = 0; 2650 soc_reg_field_set(unit, MMU_FC_TX_ENr, &val, MMU_FC_TX_ENABLEf, 2651 mmu_fc_tx_en_mmu_fc_tx_enable); 2652 SOC_IF_ERROR_RETURN(WRITE_MMU_FC_TX_ENr(unit, port, val)); 2653 2654 for (cos = 0; cos < WH2_QUEUE_MAX_NUM; cos++) { 2655 if ((cos >= 0) && (cos <= 2)) { 2656 fld_val = holcospktsetlimit_0_2__pktsetlimit; 2657 } else if (cos == 3) { 2658 fld_val = holcospktsetlimit_3__pktsetlimit; 2659 } else { 2660 fld_val = holcospktsetlimit_4_7__pktsetlimit; 2661 } 2662 SOC_IF_ERROR_RETURN 2663 (READ_HOLCOSPKTSETLIMITr(unit, port, cos, &val)); 2664 soc_reg_field_set(unit, HOLCOSPKTSETLIMITr, &val, 2665 PKTSETLIMITf, fld_val); 2666 SOC_IF_ERROR_RETURN 2667 (WRITE_HOLCOSPKTSETLIMITr(unit, port, cos, val)); 2668 2669 if ((cos >= 0) && (cos <= 2)) { 2670 fld_val = holcospktresetlimit_0_2__pktresetlimit; 2671 } else if (cos == 3) { 2672 fld_val = holcospktresetlimit_3__pktresetlimit; 2673 } else { 2674 fld_val = holcospktresetlimit_4_7__pktresetlimit; 2675 } 2676 SOC_IF_ERROR_RETURN 2677 (READ_HOLCOSPKTRESETLIMITr(unit, port, cos, &val)); 2678 soc_reg_field_set(unit, HOLCOSPKTRESETLIMITr, &val, 2679 PKTRESETLIMITf, fld_val); 2680 SOC_IF_ERROR_RETURN 2681 (WRITE_HOLCOSPKTRESETLIMITr(unit, port, cos, val)); 2682 2683 if ((cos >= 0) && (cos <= 2)) { 2684 fld_val = holcosminxqcnt_0_2__holcosminxqcnt; 2685 } else if (cos == 3) { 2686 fld_val = holcosminxqcnt_3__holcosminxqcnt; 2687 } else { 2688 fld_val = holcosminxqcnt_4_7__holcosminxqcnt; 2689 } 2690 val = 0; 2691 soc_reg_field_set(unit, HOLCOSMINXQCNTr, &val, 2692 HOLCOSMINXQCNTf, fld_val); 2693 SOC_IF_ERROR_RETURN 2694 (WRITE_HOLCOSMINXQCNTr(unit, port, cos, val)); 2695 2696 val = 0; 2697 if ((cos >= 0) && (cos <= 2)) { 2698 fld_val = lwmcoscellsetlimit_0_2__cellsetlimit; 2699 } else if (cos == 3) { 2700 fld_val = lwmcoscellsetlimit_3__cellsetlimit; 2701 } else { 2702 fld_val = lwmcoscellsetlimit_4_7__cellsetlimit; 2703 } 2704 soc_reg_field_set(unit, LWMCOSCELLSETLIMITr, &val, 2705 CELLSETLIMITf, fld_val); 2706 if ((cos >= 0) && (cos <= 2)) { 2707 fld_val = lwmcoscellsetlimit_0_2__cellresetlimit; 2708 } else if (cos == 3) { 2709 fld_val = lwmcoscellsetlimit_3__cellresetlimit; 2710 } else { 2711 fld_val = lwmcoscellsetlimit_4_7__cellresetlimit; 2712 } 2713 soc_reg_field_set(unit, LWMCOSCELLSETLIMITr, &val, 2714 CELLRESETLIMITf, fld_val); 2715 SOC_IF_ERROR_RETURN 2716 (WRITE_LWMCOSCELLSETLIMITr(unit, port, cos, val)); 2717 2718 val = 0; 2719 if ((cos >= 0) && (cos <= 2)) { 2720 fld_val = holcoscellmaxlimit_0_2__cellmaxlimit; 2721 } else if (cos == 3) { 2722 fld_val = holcoscellmaxlimit_3__cellmaxlimit; 2723 } else { 2724 fld_val = holcoscellmaxlimit_4_7__cellmaxlimit; 2725 } 2726 soc_reg_field_set(unit, HOLCOSCELLMAXLIMITr, &val, 2727 CELLMAXLIMITf, fld_val); 2728 if ((cos >= 0) && (cos <= 2)) { 2729 fld_val = holcoscellmaxlimit_0_2__cellmaxresumelimit; 2730 } else if (cos == 3) { 2731 fld_val = holcoscellmaxlimit_3__cellmaxresumelimit; 2732 } else { 2733 fld_val = holcoscellmaxlimit_4_7__cellmaxresumelimit; 2734 } 2735 soc_reg_field_set(unit, HOLCOSCELLMAXLIMITr, &val, 2736 CELLMAXRESUMELIMITf, fld_val); 2737 SOC_IF_ERROR_RETURN 2738 (WRITE_HOLCOSCELLMAXLIMITr(unit, port, cos, val)); 2739 2740 val = 0; 2741 if ((cos >= 0) && (cos <= 2)) { 2742 fld_val = pgcelllimit_0_2__cellsetlimit; 2743 } else if (cos == 3) { 2744 fld_val = pgcelllimit_3__cellsetlimit; 2745 } else { 2746 fld_val = pgcelllimit_4_7__cellsetlimit; 2747 } 2748 soc_reg_field_set(unit, PGCELLLIMITr, &val, 2749 CELLSETLIMITf, fld_val); 2750 if ((cos >= 0) && (cos <= 2)) { 2751 fld_val = pgcelllimit_0_2__cellresetlimit; 2752 } else if (cos == 3) { 2753 fld_val = pgcelllimit_3__cellresetlimit; 2754 } else { 2755 fld_val = pgcelllimit_4_7__cellresetlimit; 2756 } 2757 soc_reg_field_set(unit, PGCELLLIMITr, &val, 2758 CELLRESETLIMITf, fld_val); 2759 SOC_IF_ERROR_RETURN 2760 (WRITE_PGCELLLIMITr(unit, port, cos, val)); 2761 2762 val = 0; 2763 if ((cos >= 0) && (cos <= 2)) { 2764 fld_val = pgdiscardsetlimit_0_2__discardsetlimit; 2765 } else if (cos == 3) { 2766 fld_val = pgdiscardsetlimit_3__discardsetlimit; 2767 } else { 2768 fld_val = pgdiscardsetlimit_4_7__discardsetlimit; 2769 } 2770 soc_reg_field_set(unit, PGDISCARDSETLIMITr, &val, 2771 DISCARDSETLIMITf, fld_val); 2772 SOC_IF_ERROR_RETURN 2773 (WRITE_PGDISCARDSETLIMITr(unit, port, cos, val)); 2774 2775 val = 0; 2776 soc_reg_field_set(unit, CNGCOSPKTLIMIT0r, &val, 2777 CNGPKTSETLIMIT0f, 2778 cngcospktlimit0_0_7__cngpktsetlimit0); 2779 SOC_IF_ERROR_RETURN 2780 (WRITE_CNGCOSPKTLIMIT0r(unit, port, cos, val)); 2781 val = 0; 2782 soc_reg_field_set(unit, CNGCOSPKTLIMIT1r, &val, 2783 CNGPKTSETLIMIT1f, 2784 cngcospktlimit1_0_7__cngpktsetlimit1); 2785 SOC_IF_ERROR_RETURN 2786 (WRITE_CNGCOSPKTLIMIT1r(unit, port, cos, val)); 2787 } 2788 2789 val = 0; 2790 soc_reg_field_set(unit, CNGPORTPKTLIMIT0r, &val, 2791 CNGPORTPKTLIMIT0f, 2792 cngportpktlimit0_cngportpktlimit0); 2793 SOC_IF_ERROR_RETURN(WRITE_CNGPORTPKTLIMIT0r(unit, port, val)); 2794 2795 val = 0; 2796 soc_reg_field_set(unit, CNGPORTPKTLIMIT1r, &val, 2797 CNGPORTPKTLIMIT1f, 2798 cngportpktlimit1_cngportpktlimit1); 2799 SOC_IF_ERROR_RETURN(WRITE_CNGPORTPKTLIMIT1r(unit, port, val)); 2800 2801 val = 0; 2802 soc_reg_field_set(unit, DYNXQCNTPORTr, &val, 2803 DYNXQCNTPORTf, 2804 dynxqcntport_dynxqcntport); 2805 SOC_IF_ERROR_RETURN(WRITE_DYNXQCNTPORTr(unit, port, val)); 2806 2807 val = 0; 2808 soc_reg_field_set(unit, DYNRESETLIMPORTr, &val, 2809 DYNRESETLIMPORTf, 2810 dynresetlimport_dynresetlimport); 2811 SOC_IF_ERROR_RETURN(WRITE_DYNRESETLIMPORTr(unit, port, val)); 2812 2813 val = 0; 2814 soc_reg_field_set(unit, DYNCELLLIMITr, &val, 2815 DYNCELLSETLIMITf, 2816 dyncelllimit_dyncellsetlimit); 2817 soc_reg_field_set(unit, DYNCELLLIMITr, &val, 2818 DYNCELLRESETLIMITf, 2819 dyncelllimit_dyncellresetlimit); 2820 SOC_IF_ERROR_RETURN(WRITE_DYNCELLLIMITr(unit, port, val)); 2821 2822 val = 0; 2823 soc_reg_field_set(unit, COLOR_DROP_ENr, &val, 2824 COLOR_DROP_ENf, 2825 color_drop_en_color_drop_en); 2826 SOC_IF_ERROR_RETURN(WRITE_COLOR_DROP_ENr(unit, port, val)); 2827 2828 val = 0; 2829 soc_reg_field_set(unit, SHARED_POOL_CTRLr, &val, 2830 DYNAMIC_COS_DROP_ENf, 2831 shared_pool_ctrl_dynamic_cos_drop_en); 2832 soc_reg_field_set(unit, SHARED_POOL_CTRLr, &val, 2833 SHARED_POOL_DISCARD_ENf, 2834 shared_pool_ctrl_shared_pool_discard_en); 2835 soc_reg_field_set(unit, SHARED_POOL_CTRLr, &val, 2836 SHARED_POOL_XOFF_ENf, 2837 shared_pool_ctrl_sharded_pool_xoff_en); 2838 SOC_IF_ERROR_RETURN(WRITE_SHARED_POOL_CTRLr(unit, port, val)); 2839 } 2840 2841 return SOC_E_NONE; 2842 } 2843 2844 STATIC int 2845 soc_wolfhound2_mmu_lossy_lossless_pfc_init_helper(int unit) 2846 { 2847 uint32 tmp; 2848 wh2_sku_info_t *matched_port_config = NULL; 2849 int option; 2850 int downlink_port_1g; 2851 int downlink_port_2p5g; 2852 int uplink_port_1g; 2853 int uplink_port_2p5g; 2854 int lossy_downlink_ports; 2855 int lossless_downlink_ports; 2856 soc_pbmp_t pbmp_lossless; 2857 2858 SOC_PBMP_CLEAR(pbmp_lossless); 2859 pbmp_lossless = soc_property_get_pbmp_default(unit, spn_MMU_LOSSLESS_PBMP, 2860 pbmp_lossless); 2861 2862 /* 2863 * Lossless port count should between 1~4 and already validated by 2864 * soc_wolfhound2_mmu_init(). 2865 */ 2866 SOC_PBMP_COUNT(pbmp_lossless, lossless_downlink_ports); 2867 2868 matched_port_config = &wh2_sku_port_config[matched_devid_idx[unit]]; 2869 option = matched_port_config->config_option; 2870 /* MMU settings */ 2871 switch (option) { 2872 case 1: 2873 downlink_port_1g = 20; 2874 downlink_port_2p5g = 4; 2875 uplink_port_1g = 0; 2876 uplink_port_2p5g = 4; 2877 break; 2878 case 2: 2879 case 3: 2880 downlink_port_1g = 24; 2881 downlink_port_2p5g = 0; 2882 uplink_port_1g = 0; 2883 uplink_port_2p5g = 4; 2884 break; 2885 case 4: 2886 case 5: 2887 case 6: 2888 downlink_port_1g = 24; 2889 downlink_port_2p5g = 0; 2890 uplink_port_1g = 4; 2891 uplink_port_2p5g = 0; 2892 break; 2893 case 7: 2894 downlink_port_1g = 12; 2895 downlink_port_2p5g = 4; 2896 uplink_port_1g = 0; 2897 uplink_port_2p5g = 4; 2898 break; 2899 case 8: 2900 case 9: 2901 downlink_port_1g = 16; 2902 downlink_port_2p5g = 0; 2903 uplink_port_1g = 0; 2904 uplink_port_2p5g = 4; 2905 break; 2906 case 10: 2907 case 11: 2908 case 12: 2909 downlink_port_1g = 16; 2910 downlink_port_2p5g = 0; 2911 uplink_port_1g = 4; 2912 uplink_port_2p5g = 0; 2913 break; 2914 case 13: 2915 downlink_port_1g = 4; 2916 downlink_port_2p5g = 4; 2917 uplink_port_1g = 0; 2918 uplink_port_2p5g = 4; 2919 break; 2920 case 14: 2921 case 15: 2922 downlink_port_1g = 8; 2923 downlink_port_2p5g = 0; 2924 uplink_port_1g = 0; 2925 uplink_port_2p5g = 4; 2926 break; 2927 case 16: 2928 case 17: 2929 case 18: 2930 downlink_port_1g = 8; 2931 downlink_port_2p5g = 0; 2932 uplink_port_1g = 4; 2933 uplink_port_2p5g = 0; 2934 break; 2935 default: 2936 /* Default matched wh2_sku_port_config[0] */ 2937 downlink_port_1g = 20; 2938 downlink_port_2p5g = 4; 2939 uplink_port_1g = 0; 2940 uplink_port_2p5g = 4; 2941 break; 2942 } 2943 lossy_downlink_ports = (downlink_port_1g + downlink_port_2p5g) - \ 2944 lossless_downlink_ports; 2945 /* Prepare MMU settings */ 2946 /* 2947 * Traffic Attributes 2948 */ 2949 /* c7 */ 2950 mmu_params.min_packet_size_traffic_attr = 64; 2951 /* 2952 * c8 2953 * the value is 1.5 in doc, save 15 instead in sw. 2954 * any later usage should take care of this. 2955 */ 2956 mmu_params.ethernet_mtu_traffic_attr = 15; 2957 /* c9 */ 2958 mmu_params.max_packet_size_traffic_attr = 12288; 2959 /* c10 */ 2960 mmu_params.standard_jumbo_frame_traffic_attr = 9216; 2961 /* c11 */ 2962 mmu_params.lossless_traffic_mtu_size_traffic_attr = 2048; 2963 2964 /* 2965 * General Information 2966 * moved to earlier place as these are needed by others 2967 */ 2968 /* c79 = CEILING(C7/c49, 1)*/ 2969 tmp = mmu_params.min_packet_size_traffic_attr / CELL_SIZE; 2970 mmu_params.min_packet_size = _ceil_func(tmp, 1); 2971 /* c80 = CEILING(C8*1024/c49, 1)*/ 2972 tmp = (mmu_params.ethernet_mtu_traffic_attr * 1024) / CELL_SIZE; 2973 tmp /= 10; /* The value is 1.5 in MMU setting data, save as 15 in SW*/ 2974 mmu_params.ethernet_mtu = _ceil_func(tmp, 1); 2975 /* c81 = CEILING(C9/c49, 1)*/ 2976 tmp = mmu_params.max_packet_size_traffic_attr / CELL_SIZE; 2977 mmu_params.max_packet_size = _ceil_func(tmp, 1); 2978 /* c82 = CEILING(C10/c49, 1)*/ 2979 tmp = mmu_params.standard_jumbo_frame_traffic_attr / CELL_SIZE; 2980 mmu_params.standard_jumbo_frame = _ceil_func(tmp, 1); 2981 /* c83 = CEILING(C11/c49, 1)*/ 2982 tmp = mmu_params.lossless_traffic_mtu_size_traffic_attr / CELL_SIZE; 2983 mmu_params.lossless_traffic_mtu_size = _ceil_func(tmp, 1); 2984 2985 /* 2986 * Reservations 2987 * moved to earlier place as these are needed by others 2988 */ 2989 /* c70 = c80*4*/ 2990 mmu_params.wrr_reserve = mmu_params.ethernet_mtu * 4; 2991 /* c71 = (31)*2 +7+29*/ 2992 mmu_params.reserved_for_cfap = 98; 2993 /* c72 */ 2994 mmu_params.skidmarker = 7; 2995 /* c73 */ 2996 mmu_params.skidmarker_option = 3; 2997 /* c74 */ 2998 mmu_params.prefetch = 9; 2999 3000 /* 3001 * SW Config Property 3002 */ 3003 /* c14 */ 3004 mmu_params.total_physical_memory_sw_cfg = 4096; 3005 /* c15 = c14-c71 */ 3006 mmu_params.cfapfullsetpoint_sw_cfg = \ 3007 mmu_params.total_physical_memory_sw_cfg - mmu_params.reserved_for_cfap; 3008 /* c16 = c15 */ 3009 mmu_params.total_cell_memory_for_admission_sw_cfg = \ 3010 mmu_params.cfapfullsetpoint_sw_cfg; 3011 3012 /* c17 configurable */ 3013 mmu_params.num_1g_ports_uplink_ports_sw_cfg = uplink_port_1g; 3014 /* c18 configurable */ 3015 mmu_params.num_2p5g_ports_uplink_ports_sw_cfg = uplink_port_2p5g; 3016 /* c19 configurable */ 3017 mmu_params.num_lossy_downlink_ports_sw_cfg = lossy_downlink_ports; 3018 /* c20 configurable */ 3019 mmu_params.num_lossless_downlink_ports_sw_cfg = lossless_downlink_ports; 3020 /* c21 = SUM(C17:C18) */ 3021 mmu_params.number_of_uplink_ports_sw_cfg = \ 3022 mmu_params.num_1g_ports_uplink_ports_sw_cfg + \ 3023 mmu_params.num_2p5g_ports_uplink_ports_sw_cfg; 3024 /* c22 = SUM(C19:C20)*/ 3025 mmu_params.number_of_downlink_ports_sw_cfg = \ 3026 mmu_params.num_lossy_downlink_ports_sw_cfg + \ 3027 mmu_params.num_lossless_downlink_ports_sw_cfg; 3028 /* c23 lossless = 1 */ 3029 mmu_params.flow_control_enabled_sw_cfg = 1; 3030 /* c24 PFC = 1 */ 3031 mmu_params.flow_control_type_sw_cfg = 1; 3032 /* c25 = 0.25, not used */ 3033 /* mmu_params.queue_port_limit_ratio_sw_cfg = 0.25; */ 3034 3035 /* 3036 * Device Attributes 3037 * moved to earlier place as these are needed by others 3038 */ 3039 /* c49 */ 3040 mmu_params.cell_size = CELL_SIZE; 3041 /* c50 */ 3042 mmu_params.num_egress_queues_per_port = 4; 3043 /* c51 */ 3044 mmu_params.num_cpu_queues = 8; 3045 /* c52 = c17*/ 3046 mmu_params.num_1g_ports_uplink_ports = \ 3047 mmu_params.num_1g_ports_uplink_ports_sw_cfg; 3048 /* c53 = c18 */ 3049 mmu_params.num_2p5g_ports_uplink_ports = \ 3050 mmu_params.num_2p5g_ports_uplink_ports_sw_cfg; 3051 /* c54 = c19 */ 3052 mmu_params.num_lossy_downlink_ports = \ 3053 mmu_params.num_lossy_downlink_ports_sw_cfg; 3054 /* c55 = c20 */ 3055 mmu_params.num_lossless_downlink_ports = \ 3056 mmu_params.num_lossless_downlink_ports_sw_cfg; 3057 /* c56 */ 3058 mmu_params.num_cpu_ports = 1; 3059 /* c57 = c21*/ 3060 mmu_params.number_of_uplink_ports = \ 3061 mmu_params.number_of_uplink_ports_sw_cfg; 3062 /* c58 = c22 */ 3063 mmu_params.number_of_downlink_ports = \ 3064 mmu_params.number_of_downlink_ports_sw_cfg; 3065 /* c59 = c14 */ 3066 mmu_params.total_physical_memory = \ 3067 mmu_params.total_physical_memory_sw_cfg; 3068 /* c60 = c16 */ 3069 mmu_params.total_cell_memory = \ 3070 mmu_params.total_cell_memory_for_admission_sw_cfg; 3071 /* c61 = c60 */ 3072 mmu_params.total_advertised_cell_memory = \ 3073 mmu_params.total_cell_memory; 3074 /* c62 */ 3075 mmu_params.numxq_per_uplink_ports = 512; 3076 /* c63 */ 3077 mmu_params.numxq_per_downlink_ports_and_cpu_port = 512; 3078 /* c64 */ 3079 mmu_params.the_number_of_pipelines_per_device = 1; 3080 /* c66 */ 3081 mmu_params.n_egress_queues_active_per_xpe = 1; 3082 /* c67 */ 3083 mmu_params.n_ingress_ports_active_per_xpe = 1; 3084 3085 /* 3086 * SW Config Parameter : may different from lossy to lossless 3087 */ 3088 /* c46, used by (c88) */ 3089 mmu_params.mmu_xoff_cell_threshold_downlink_lossless_ports = 36; 3090 /* c88 = c46, used by (c35) */ 3091 mmu_params.xoff_cell_thresholds_per_port_pg_downlink_lossless_ports = \ 3092 mmu_params.mmu_xoff_cell_threshold_downlink_lossless_ports; 3093 /* c35 =(c88+c46)*c20, used by later (c31) */ 3094 mmu_params.egress_xq_min_reserve_lossless_uplink_ports = \ 3095 (mmu_params.xoff_cell_thresholds_per_port_pg_downlink_lossless_ports + \ 3096 mmu_params.mmu_xoff_cell_threshold_downlink_lossless_ports) * \ 3097 mmu_params.num_lossless_downlink_ports_sw_cfg; 3098 3099 /* c29 = c80 */ 3100 mmu_params.egress_queue_min_reserve_uplink_ports_lossy = \ 3101 mmu_params.ethernet_mtu; 3102 /* c30 = c80 */ 3103 mmu_params.egress_queue_min_reserve_downlink_ports_lossy = \ 3104 mmu_params.ethernet_mtu; 3105 /* c31 = c35 */ 3106 mmu_params.egress_queue_min_reserve_uplink_ports_lossless = \ 3107 mmu_params.egress_xq_min_reserve_lossless_uplink_ports; 3108 /* c32 */ 3109 mmu_params.egress_queue_min_reserve_downlink_ports_lossless = 0; 3110 /* c33 = c80 */ 3111 mmu_params.egress_queue_min_reserve_cpu_ports = \ 3112 mmu_params.ethernet_mtu; 3113 /* c34 = c80 */ 3114 mmu_params.egress_xq_min_reserve_lossy_uplink_and_downlink_ports = \ 3115 mmu_params.ethernet_mtu; 3116 /* c36 */ 3117 mmu_params.egress_xq_min_reserve_lossless_downlink_ports = 0; 3118 /* c37 */ 3119 mmu_params.num_total_pri_groups = 4; 3120 /* c38 */ 3121 mmu_params.num_active_pri_group_lossless = 1; 3122 /* c39 */ 3123 mmu_params.num_lossless_queues = 1; 3124 /* c40 */ 3125 mmu_params.num_lossy_queues = 3; 3126 /* c41 = c61 */ 3127 mmu_params.mmu_xoff_pkt_threshold_uplink_ports = \ 3128 mmu_params.total_advertised_cell_memory; 3129 /* c42 = c61 */ 3130 mmu_params.mmu_xoff_pkt_threshold_downlink_ports = \ 3131 mmu_params.total_advertised_cell_memory; 3132 /* c43 = c61 */ 3133 mmu_params.mmu_xoff_cell_threshold_1g_port_uplink_ports = \ 3134 mmu_params.total_advertised_cell_memory; 3135 /* c44 = c61 */ 3136 mmu_params.mmu_xoff_cell_threshold_2p5g_port_uplink_ports = \ 3137 mmu_params.total_advertised_cell_memory; 3138 /* c45 = c61 */ 3139 mmu_params.mmu_xoff_cell_threshold_downlink_lossy_ports = \ 3140 mmu_params.total_advertised_cell_memory; 3141 3142 /* 3143 * Ingress Thresholds : may different from lossy to lossless 3144 */ 3145 /* c86 = c46 */ 3146 mmu_params.headroom_for_lossless_downlink_port = \ 3147 mmu_params.mmu_xoff_cell_threshold_downlink_lossless_ports; 3148 /* c87 = c45 */ 3149 mmu_params.xoff_cell_thresholds_per_port_pg_downlink_lossy_ports = \ 3150 mmu_params.mmu_xoff_cell_threshold_downlink_lossy_ports; 3151 /* c89 = c43 */ 3152 mmu_params.xoff_cell_threshold_1g_uplink_ports = \ 3153 mmu_params.mmu_xoff_cell_threshold_1g_port_uplink_ports; 3154 /* c90 = c44 */ 3155 mmu_params.xoff_cell_threshold_2p5g_uplink_ports = \ 3156 mmu_params.mmu_xoff_cell_threshold_2p5g_port_uplink_ports; 3157 /* c91 = c41 */ 3158 mmu_params.xoff_packet_thresholds_per_port_uplink_port = \ 3159 mmu_params.mmu_xoff_pkt_threshold_uplink_ports; 3160 /* c92 = c42 */ 3161 mmu_params.xoff_packet_thresholds_per_port_downlink_port = \ 3162 mmu_params.mmu_xoff_pkt_threshold_downlink_ports; 3163 /* c93 = c61 */ 3164 mmu_params.discard_limit_per_port_pg_lossy_downlink_port = \ 3165 mmu_params.total_advertised_cell_memory; 3166 /* c94 = c88+c86 */ 3167 mmu_params.discard_limit_per_port_pg_downlink_2p5g_port = \ 3168 mmu_params.xoff_cell_thresholds_per_port_pg_downlink_lossless_ports + \ 3169 mmu_params.headroom_for_lossless_downlink_port; 3170 /* c95 = c61 */ 3171 mmu_params.discard_limit_per_port_pg_uplink_port = \ 3172 mmu_params.total_advertised_cell_memory; 3173 3174 /* 3175 * Egress Thresholds 3176 */ 3177 /* c97 = c29*c57*c40+c57*c31*c39 */ 3178 mmu_params.total_reserved_cells_for_uplink_ports = \ 3179 (mmu_params.egress_queue_min_reserve_uplink_ports_lossy * \ 3180 mmu_params.number_of_uplink_ports * \ 3181 mmu_params.num_lossy_queues) + \ 3182 (mmu_params.number_of_uplink_ports * \ 3183 mmu_params.egress_queue_min_reserve_uplink_ports_lossless * \ 3184 mmu_params.num_lossless_queues); 3185 /* c98 = c58*c30*(c40)+c58*c32*c39 */ 3186 mmu_params.total_reserved_cells_for_downlink_ports = \ 3187 (mmu_params.number_of_downlink_ports * \ 3188 mmu_params.egress_queue_min_reserve_downlink_ports_lossy * \ 3189 mmu_params.num_lossy_queues) + \ 3190 (mmu_params.number_of_downlink_ports * \ 3191 mmu_params.egress_queue_min_reserve_downlink_ports_lossless * \ 3192 mmu_params.num_lossless_queues); 3193 /* c99 = c56*c33*c51 */ 3194 mmu_params.total_reserved_cells_for_cpu_port = \ 3195 mmu_params.num_cpu_ports * \ 3196 mmu_params.egress_queue_min_reserve_cpu_ports * \ 3197 mmu_params.num_cpu_queues; 3198 /* c100 = SUM(c97:c99) */ 3199 mmu_params.total_reserved = \ 3200 mmu_params.total_reserved_cells_for_uplink_ports + \ 3201 mmu_params.total_reserved_cells_for_downlink_ports + \ 3202 mmu_params.total_reserved_cells_for_cpu_port; 3203 /* c101 = c61-c100 */ 3204 mmu_params.shared_space_cells = \ 3205 mmu_params.total_advertised_cell_memory - \ 3206 mmu_params.total_reserved; 3207 /* c102 = c34*c40+c35*c39 */ 3208 mmu_params.reserved_xqs_per_uplink_port = \ 3209 (mmu_params.egress_xq_min_reserve_lossy_uplink_and_downlink_ports * \ 3210 mmu_params.num_lossy_queues) + \ 3211 (mmu_params.egress_xq_min_reserve_lossless_uplink_ports * \ 3212 mmu_params.num_lossless_queues); 3213 /* c103 = c62-c102 */ 3214 mmu_params.shared_xqs_per_uplink_port = \ 3215 mmu_params.numxq_per_uplink_ports - \ 3216 mmu_params.reserved_xqs_per_uplink_port; 3217 /* c104 = c34*c40+c36*c39 */ 3218 mmu_params.reserved_xqs_per_downlink_port = \ 3219 (mmu_params.egress_xq_min_reserve_lossy_uplink_and_downlink_ports * \ 3220 mmu_params.num_lossy_queues) + \ 3221 (mmu_params.egress_xq_min_reserve_lossless_downlink_ports * \ 3222 mmu_params.num_lossless_queues); 3223 /* c105 = c63-c104 */ 3224 mmu_params.shared_xqs_per_downlink_port = \ 3225 mmu_params.numxq_per_downlink_ports_and_cpu_port - \ 3226 mmu_params.reserved_xqs_per_downlink_port; 3227 /* c106 = c33 * c51 */ 3228 mmu_params.reserved_xqs_at_cpu_port = \ 3229 mmu_params.egress_queue_min_reserve_cpu_ports * \ 3230 mmu_params.num_cpu_queues; 3231 /* c107 = c63 - c106 */ 3232 mmu_params.shared_xqs_at_cpu_port = \ 3233 mmu_params.numxq_per_downlink_ports_and_cpu_port - \ 3234 mmu_params.reserved_xqs_at_cpu_port; 3235 3236 /* Program MMU settings */ 3237 SOC_IF_ERROR_RETURN( 3238 soc_wolfhound2_mmu_lossy_lossless_pfc_config_helper(unit)); 3239 3240 return SOC_E_NONE; 3241 } 3242 3243 STATIC int 3244 soc_wolfhound2_mmu_lossy_or_lossless_config_helper(int unit, int lossless) 3245 { 3246 uint32 val = 0; 3247 uint32 fld_val = 0; 3248 uint32 tmp = 0; 3249 int port; /* logical port id */ 3250 int pport; /* physical port id */ 3251 int speed; 3252 int cos; 3253 int i; 3254 uint32 ibppktsetlimit_pktsetlimit; 3255 uint32 ibppktsetlimit_resetlimitsel; 3256 uint32 mmu_fc_rx_en_mmu_fc_rx_enable; 3257 uint32 mmu_fc_tx_en_mmu_fc_tx_enable; 3258 uint32 pgcelllimit_0_2__cellsetlimit; 3259 uint32 pgcelllimit_3__cellsetlimit; 3260 uint32 pgcelllimit_4_6__cellsetlimit; 3261 uint32 pgcelllimit_7__cellsetlimit; 3262 uint32 pgcelllimit_0_2__cellresetlimit; 3263 uint32 pgcelllimit_3__cellresetlimit; 3264 uint32 pgcelllimit_4_6__cellresetlimit; 3265 uint32 pgcelllimit_7__cellresetlimit; 3266 uint32 pgdiscardsetlimit_0_2__discardsetlimit; 3267 uint32 pgdiscardsetlimit_3__discardsetlimit; 3268 uint32 pgdiscardsetlimit_4_6__discardsetlimit; 3269 uint32 pgdiscardsetlimit_7__discardsetlimit; 3270 uint32 holcosminxqcnt_0_2__holcosminxqcnt; 3271 uint32 holcosminxqcnt_3__holcosminxqcnt; 3272 uint32 holcosminxqcnt_4_7__holcosminxqcnt; 3273 uint32 holcospktsetlimit_0_2__pktsetlimit; 3274 uint32 holcospktsetlimit_3__pktsetlimit; 3275 uint32 holcospktsetlimit_4_7__pktsetlimit; 3276 uint32 holcospktresetlimit_0_2__pktresetlimit; 3277 uint32 holcospktresetlimit_3__pktresetlimit; 3278 uint32 holcospktresetlimit_4_7__pktresetlimit; 3279 uint32 cngcospktlimit0_0_7__cngpktsetlimit0; 3280 uint32 cngcospktlimit1_0_7__cngpktsetlimit1; 3281 uint32 cngportpktlimit0_cngportpktlimit0; 3282 uint32 cngportpktlimit1_cngportpktlimit1; 3283 uint32 dynxqcntport_dynxqcntport; 3284 uint32 dynresetlimport_dynresetlimport; 3285 uint32 lwmcoscellsetlimit_0_2__cellsetlimit; 3286 uint32 lwmcoscellsetlimit_3__cellsetlimit; 3287 uint32 lwmcoscellsetlimit_4_7__cellsetlimit; 3288 uint32 lwmcoscellsetlimit_0_2__cellresetlimit; 3289 uint32 lwmcoscellsetlimit_3__cellresetlimit; 3290 uint32 lwmcoscellsetlimit_4_7__cellresetlimit; 3291 uint32 holcoscellmaxlimit_0_2__cellmaxlimit; 3292 uint32 holcoscellmaxlimit_3__cellmaxlimit; 3293 uint32 holcoscellmaxlimit_4_7__cellmaxlimit; 3294 uint32 holcoscellmaxlimit_0_2__cellmaxresumelimit; 3295 uint32 holcoscellmaxlimit_3__cellmaxresumelimit; 3296 uint32 holcoscellmaxlimit_4_7__cellmaxresumelimit; 3297 uint32 dyncelllimit_dyncellsetlimit; 3298 uint32 dyncelllimit_dyncellresetlimit; 3299 uint32 color_drop_en_color_drop_en; 3300 uint32 shared_pool_ctrl_dynamic_cos_drop_en; 3301 uint32 shared_pool_ctrl_shared_pool_discard_en; 3302 uint32 shared_pool_ctrl_sharded_pool_xoff_en; 3303 3304 SOC_IF_ERROR_RETURN(READ_CFAPFULLTHRESHOLDr(unit, &val)); 3305 /* i6 = c15 */ 3306 soc_reg_field_set(unit, CFAPFULLTHRESHOLDr, &val, 3307 CFAPFULLSETPOINTf, 3308 mmu_params.cfapfullsetpoint_sw_cfg); 3309 /* i7 = i6 - c82 */ 3310 soc_reg_field_set(unit, CFAPFULLTHRESHOLDr, &val, 3311 CFAPFULLRESETPOINTf, 3312 mmu_params.cfapfullsetpoint_sw_cfg - \ 3313 mmu_params.standard_jumbo_frame); 3314 SOC_IF_ERROR_RETURN(WRITE_CFAPFULLTHRESHOLDr(unit, val)); 3315 3316 /* i10 = c16 */ 3317 SOC_IF_ERROR_RETURN(READ_GBLLIMITSETLIMITr(unit, &val)); 3318 soc_reg_field_set(unit, GBLLIMITSETLIMITr, &val, 3319 GBLCELLSETLIMITf, 3320 mmu_params.total_cell_memory_for_admission_sw_cfg); 3321 SOC_IF_ERROR_RETURN(WRITE_GBLLIMITSETLIMITr(unit, val)); 3322 3323 /* i11 = i10 */ 3324 SOC_IF_ERROR_RETURN(READ_GBLLIMITRESETLIMITr(unit, &val)); 3325 soc_reg_field_set(unit, GBLLIMITRESETLIMITr, &val, 3326 GBLCELLRESETLIMITf, 3327 mmu_params.total_cell_memory_for_admission_sw_cfg); 3328 SOC_IF_ERROR_RETURN(WRITE_GBLLIMITRESETLIMITr(unit, val)); 3329 3330 /* Device Wide - Egress Thresholds */ 3331 val = 0; 3332 /* i15 = c101 */ 3333 soc_reg_field_set(unit, TOTALDYNCELLSETLIMITr, 3334 &val, TOTALDYNCELLSETLIMITf, 3335 mmu_params.shared_space_cells); 3336 SOC_IF_ERROR_RETURN(WRITE_TOTALDYNCELLSETLIMITr(unit, val)); 3337 val = 0; 3338 /* i16 =i15-c82*2*/ 3339 soc_reg_field_set(unit, TOTALDYNCELLRESETLIMITr, 3340 &val, TOTALDYNCELLRESETLIMITf, 3341 mmu_params.shared_space_cells - \ 3342 (mmu_params.standard_jumbo_frame * 2)); 3343 SOC_IF_ERROR_RETURN(WRITE_TOTALDYNCELLRESETLIMITr(unit, val)); 3344 3345 /* MICCONFIGr */ 3346 SOC_IF_ERROR_RETURN(READ_MISCCONFIGr(unit, &val)); 3347 soc_reg_field_set(unit, MISCCONFIGr, &val, MULTIPLE_ACCOUNTING_FIX_ENf, 1); 3348 soc_reg_field_set(unit, MISCCONFIGr, &val, CNG_DROP_ENf, 0); 3349 soc_reg_field_set(unit, MISCCONFIGr, &val, DYN_XQ_ENf, 1); 3350 soc_reg_field_set(unit, MISCCONFIGr, &val, HOL_CELL_SOP_DROP_ENf, 1); 3351 soc_reg_field_set(unit, MISCCONFIGr, &val, DYNAMIC_MEMORY_ENf, 1); 3352 soc_reg_field_set(unit, MISCCONFIGr, &val, SKIDMARKERf, 3); 3353 SOC_IF_ERROR_RETURN(WRITE_MISCCONFIGr(unit, val)); 3354 3355 PBMP_ALL_ITER(unit, port) { 3356 pport = SOC_INFO(unit).port_l2p_mapping[port]; 3357 speed = SOC_INFO(unit).port_speed_max[port]; 3358 3359 val = 0; 3360 if (lossless) { 3361 if (IS_CPU_PORT(unit, port)) { 3362 soc_reg_field_set(unit, PG_CTRL0r, &val, PPFC_PG_ENf, 0); 3363 } else { 3364 soc_reg_field_set(unit, PG_CTRL0r, &val, PPFC_PG_ENf, 0x80); 3365 } 3366 } else { 3367 soc_reg_field_set(unit, PG_CTRL0r, &val, PPFC_PG_ENf, 0); 3368 } 3369 soc_reg_field_set(unit, PG_CTRL0r, &val, PRI0_GRPf, 7); 3370 soc_reg_field_set(unit, PG_CTRL0r, &val, PRI1_GRPf, 7); 3371 soc_reg_field_set(unit, PG_CTRL0r, &val, PRI2_GRPf, 7); 3372 soc_reg_field_set(unit, PG_CTRL0r, &val, PRI3_GRPf, 7); 3373 soc_reg_field_set(unit, PG_CTRL0r, &val, PRI4_GRPf, 7); 3374 soc_reg_field_set(unit, PG_CTRL0r, &val, PRI5_GRPf, 7); 3375 soc_reg_field_set(unit, PG_CTRL0r, &val, PRI6_GRPf, 7); 3376 soc_reg_field_set(unit, PG_CTRL0r, &val, PRI7_GRPf, 7); 3377 SOC_IF_ERROR_RETURN(WRITE_PG_CTRL0r(unit, port, val)); 3378 val = 0; 3379 soc_reg_field_set(unit, PG_CTRL1r, &val, PRI8_GRPf, 7); 3380 soc_reg_field_set(unit, PG_CTRL1r, &val, PRI9_GRPf, 7); 3381 soc_reg_field_set(unit, PG_CTRL1r, &val, PRI10_GRPf, 7); 3382 soc_reg_field_set(unit, PG_CTRL1r, &val, PRI11_GRPf, 7); 3383 soc_reg_field_set(unit, PG_CTRL1r, &val, PRI12_GRPf, 7); 3384 soc_reg_field_set(unit, PG_CTRL1r, &val, PRI13_GRPf, 7); 3385 soc_reg_field_set(unit, PG_CTRL1r, &val, PRI14_GRPf, 7); 3386 soc_reg_field_set(unit, PG_CTRL1r, &val, PRI15_GRPf, 7); 3387 SOC_IF_ERROR_RETURN(WRITE_PG_CTRL1r(unit, port, val)); 3388 val = 0; 3389 soc_reg_field_set(unit, PG2TCr, &val, PG_BMPf, 0); 3390 for (i = 0; i < 8; i++) { 3391 SOC_IF_ERROR_RETURN(WRITE_PG2TCr(unit, port, i, val)); 3392 } 3393 3394 /* Settings based on port type */ 3395 if (IS_CPU_PORT(unit, port)) { 3396 ibppktsetlimit_pktsetlimit = \ 3397 mmu_params.\ 3398 xoff_packet_thresholds_per_port_downlink_port; /* c92 */ 3399 ibppktsetlimit_resetlimitsel = 3; 3400 mmu_fc_rx_en_mmu_fc_rx_enable = 0; 3401 mmu_fc_tx_en_mmu_fc_tx_enable = 0; 3402 if (lossless) { 3403 /* c93 */ 3404 pgcelllimit_0_2__cellsetlimit = \ 3405 mmu_params.discard_limit_per_port_pg_downlink_1g_port; 3406 /* c93 */ 3407 pgcelllimit_3__cellsetlimit = \ 3408 mmu_params.discard_limit_per_port_pg_downlink_1g_port; 3409 /* c93 */ 3410 pgcelllimit_4_6__cellsetlimit = \ 3411 mmu_params.discard_limit_per_port_pg_downlink_1g_port; 3412 /* c87 */ 3413 pgcelllimit_7__cellsetlimit = \ 3414 mmu_params.\ 3415 xoff_cell_thresholds_per_port_pg_1g_port_downlink_ports; 3416 /* c93 */ 3417 pgcelllimit_0_2__cellresetlimit = \ 3418 mmu_params.discard_limit_per_port_pg_downlink_1g_port; 3419 /* c93 */ 3420 pgcelllimit_3__cellresetlimit = \ 3421 mmu_params.discard_limit_per_port_pg_downlink_1g_port; 3422 /* c93 */ 3423 pgcelllimit_4_6__cellresetlimit = \ 3424 mmu_params.discard_limit_per_port_pg_downlink_1g_port; 3425 /* c87 */ 3426 pgcelllimit_7__cellresetlimit = \ 3427 mmu_params.\ 3428 xoff_cell_thresholds_per_port_pg_1g_port_downlink_ports; 3429 } else { 3430 /* c87 */ 3431 pgcelllimit_0_2__cellsetlimit = \ 3432 mmu_params.\ 3433 xoff_cell_thresholds_per_port_pg_1g_port_downlink_ports; 3434 /* c87 */ 3435 pgcelllimit_3__cellsetlimit = \ 3436 mmu_params.\ 3437 xoff_cell_thresholds_per_port_pg_1g_port_downlink_ports; 3438 /* c87 */ 3439 pgcelllimit_4_6__cellsetlimit = \ 3440 mmu_params.\ 3441 xoff_cell_thresholds_per_port_pg_1g_port_downlink_ports; 3442 /* c87 */ 3443 pgcelllimit_7__cellsetlimit = \ 3444 mmu_params.\ 3445 xoff_cell_thresholds_per_port_pg_1g_port_downlink_ports; 3446 /* c87 */ 3447 pgcelllimit_0_2__cellresetlimit = \ 3448 mmu_params.\ 3449 xoff_cell_thresholds_per_port_pg_1g_port_downlink_ports; 3450 /* c87 */ 3451 pgcelllimit_3__cellresetlimit = \ 3452 mmu_params.\ 3453 xoff_cell_thresholds_per_port_pg_1g_port_downlink_ports; 3454 /* c87 */ 3455 pgcelllimit_4_6__cellresetlimit = \ 3456 mmu_params.\ 3457 xoff_cell_thresholds_per_port_pg_1g_port_downlink_ports; 3458 /* c87 */ 3459 pgcelllimit_7__cellresetlimit = \ 3460 mmu_params.\ 3461 xoff_cell_thresholds_per_port_pg_1g_port_downlink_ports; 3462 } 3463 pgdiscardsetlimit_0_2__discardsetlimit = \ 3464 mmu_params.discard_limit_per_port_pg_downlink_1g_port; /* c93 */ 3465 pgdiscardsetlimit_3__discardsetlimit = \ 3466 mmu_params.discard_limit_per_port_pg_downlink_1g_port; /* c93 */ 3467 pgdiscardsetlimit_4_6__discardsetlimit = \ 3468 mmu_params.discard_limit_per_port_pg_downlink_1g_port; /* c93 */ 3469 pgdiscardsetlimit_7__discardsetlimit = \ 3470 mmu_params.discard_limit_per_port_pg_downlink_1g_port; /* c93 */ 3471 3472 holcosminxqcnt_0_2__holcosminxqcnt = \ 3473 mmu_params.egress_queue_min_reserve_cpu_ports; /* c33 */ 3474 holcosminxqcnt_3__holcosminxqcnt = \ 3475 mmu_params.egress_queue_min_reserve_cpu_ports; /* c33 */ 3476 holcosminxqcnt_4_7__holcosminxqcnt = \ 3477 mmu_params.egress_queue_min_reserve_cpu_ports; /* c33 */ 3478 holcospktsetlimit_0_2__pktsetlimit = \ 3479 mmu_params.shared_xqs_at_cpu_port - \ 3480 mmu_params.skidmarker - \ 3481 mmu_params.prefetch + \ 3482 holcosminxqcnt_0_2__holcosminxqcnt; /* C107-C72-C74+Q70 */ 3483 holcospktsetlimit_3__pktsetlimit = \ 3484 mmu_params.shared_xqs_at_cpu_port - \ 3485 mmu_params.skidmarker - \ 3486 mmu_params.prefetch + \ 3487 holcosminxqcnt_3__holcosminxqcnt; /* C107-C72-C74+Q71 */ 3488 holcospktsetlimit_4_7__pktsetlimit = \ 3489 mmu_params.shared_xqs_at_cpu_port - \ 3490 mmu_params.skidmarker - \ 3491 mmu_params.prefetch + \ 3492 holcosminxqcnt_4_7__holcosminxqcnt; /* C107-C72-C74+Q72 */ 3493 holcospktresetlimit_0_2__pktresetlimit = \ 3494 holcospktsetlimit_0_2__pktsetlimit - 1; /* q73 - 1 */ 3495 holcospktresetlimit_3__pktresetlimit = \ 3496 holcospktsetlimit_3__pktsetlimit - 1; /* q74 - 1 */ 3497 holcospktresetlimit_4_7__pktresetlimit = \ 3498 holcospktsetlimit_4_7__pktsetlimit - 1; /* q75 - 1 */ 3499 cngcospktlimit0_0_7__cngpktsetlimit0 = \ 3500 mmu_params.numxq_per_downlink_ports_and_cpu_port - 1; /*c63-1*/ 3501 cngcospktlimit1_0_7__cngpktsetlimit1 = \ 3502 mmu_params.numxq_per_downlink_ports_and_cpu_port - 1; /*c63-1*/ 3503 cngportpktlimit0_cngportpktlimit0 = \ 3504 mmu_params.numxq_per_downlink_ports_and_cpu_port - 1; /*c63-1*/ 3505 cngportpktlimit1_cngportpktlimit1 = \ 3506 mmu_params.numxq_per_downlink_ports_and_cpu_port - 1; /*c63-1*/ 3507 dynxqcntport_dynxqcntport = \ 3508 mmu_params.shared_xqs_at_cpu_port - \ 3509 mmu_params.skidmarker - \ 3510 mmu_params.prefetch; /* c107-c72-c74 */ 3511 dynresetlimport_dynresetlimport = \ 3512 dynxqcntport_dynxqcntport - 2; /* q83 - 2 */ 3513 lwmcoscellsetlimit_0_2__cellsetlimit = \ 3514 mmu_params.egress_queue_min_reserve_cpu_ports; /* c33 */ 3515 lwmcoscellsetlimit_3__cellsetlimit = \ 3516 mmu_params.egress_queue_min_reserve_cpu_ports; /* c33 */ 3517 lwmcoscellsetlimit_4_7__cellsetlimit = \ 3518 mmu_params.egress_queue_min_reserve_cpu_ports; /* c33 */ 3519 lwmcoscellsetlimit_0_2__cellresetlimit = \ 3520 mmu_params.egress_queue_min_reserve_cpu_ports; /* c33 */ 3521 lwmcoscellsetlimit_3__cellresetlimit = \ 3522 mmu_params.egress_queue_min_reserve_cpu_ports; /* c33 */ 3523 lwmcoscellsetlimit_4_7__cellresetlimit = \ 3524 mmu_params.egress_queue_min_reserve_cpu_ports; /* c33 */ 3525 /* CEILING(c101*C25+Q85, 1) */ 3526 tmp = _ceil_func((mmu_params.shared_space_cells * 10 / 4), 10); 3527 holcoscellmaxlimit_0_2__cellmaxlimit = \ 3528 tmp + lwmcoscellsetlimit_0_2__cellsetlimit; 3529 /* CEILING(c101*C25+Q86, 1) */ 3530 tmp = _ceil_func((mmu_params.shared_space_cells * 10 / 4), 10); 3531 holcoscellmaxlimit_3__cellmaxlimit = \ 3532 tmp + lwmcoscellsetlimit_3__cellsetlimit; 3533 /* CEILING(c101*C25+Q87, 1) */ 3534 tmp = _ceil_func((mmu_params.shared_space_cells * 10 / 4), 10); 3535 holcoscellmaxlimit_4_7__cellmaxlimit = \ 3536 tmp + lwmcoscellsetlimit_4_7__cellsetlimit; 3537 holcoscellmaxlimit_0_2__cellmaxresumelimit = \ 3538 holcoscellmaxlimit_0_2__cellmaxlimit - \ 3539 mmu_params.ethernet_mtu; /* q91 - c80 */ 3540 holcoscellmaxlimit_3__cellmaxresumelimit = \ 3541 holcoscellmaxlimit_3__cellmaxlimit - \ 3542 mmu_params.ethernet_mtu; /* q92 - c80 */ 3543 holcoscellmaxlimit_4_7__cellmaxresumelimit = \ 3544 holcoscellmaxlimit_4_7__cellmaxlimit - \ 3545 mmu_params.ethernet_mtu; /* q93 - c80 */ 3546 dyncelllimit_dyncellsetlimit = \ 3547 mmu_params.shared_space_cells; /* c101 */ 3548 dyncelllimit_dyncellresetlimit = \ 3549 dyncelllimit_dyncellsetlimit - \ 3550 (mmu_params.ethernet_mtu * 2); /* q97-c80*2 */ 3551 color_drop_en_color_drop_en = 0; 3552 shared_pool_ctrl_dynamic_cos_drop_en = 255; 3553 shared_pool_ctrl_shared_pool_discard_en = 255; 3554 shared_pool_ctrl_sharded_pool_xoff_en = 0; 3555 } else if (pport >= 34) { /* uplink port 1G, 2.5G */ 3556 if (lossless) { 3557 SOC_IF_ERROR_RETURN(WRITE_PG2TCr(unit, port, 7, 0x80)); 3558 } 3559 3560 if (lossless) { 3561 if (speed == 10) { /* 1G */ 3562 /* c95 */ 3563 pgcelllimit_0_2__cellsetlimit = \ 3564 mmu_params.discard_limit_per_port_pg_uplink_port; 3565 /* c95 */ 3566 pgcelllimit_3__cellsetlimit = \ 3567 mmu_params.discard_limit_per_port_pg_uplink_port; 3568 /* c95 */ 3569 pgcelllimit_4_6__cellsetlimit = \ 3570 mmu_params.discard_limit_per_port_pg_uplink_port; 3571 /* c89 */ 3572 pgcelllimit_7__cellsetlimit = \ 3573 mmu_params.\ 3574 xoff_cell_threshold_1g_uplink_ports; 3575 /* c95 */ 3576 pgcelllimit_0_2__cellresetlimit = \ 3577 mmu_params.discard_limit_per_port_pg_uplink_port; 3578 /* c95 */ 3579 pgcelllimit_3__cellresetlimit = \ 3580 mmu_params.discard_limit_per_port_pg_uplink_port; 3581 /* c95 */ 3582 pgcelllimit_4_6__cellresetlimit = \ 3583 mmu_params.discard_limit_per_port_pg_uplink_port; 3584 /* c89 */ 3585 pgcelllimit_7__cellresetlimit = \ 3586 mmu_params.\ 3587 xoff_cell_threshold_1g_uplink_ports; 3588 } else { /* 2.5 G */ 3589 /* c95 */ 3590 pgcelllimit_0_2__cellsetlimit = \ 3591 mmu_params.discard_limit_per_port_pg_uplink_port; 3592 /* c95 */ 3593 pgcelllimit_3__cellsetlimit = \ 3594 mmu_params.discard_limit_per_port_pg_uplink_port; 3595 /* c95 */ 3596 pgcelllimit_4_6__cellsetlimit = \ 3597 mmu_params.discard_limit_per_port_pg_uplink_port; 3598 /* c90 */ 3599 pgcelllimit_7__cellsetlimit = \ 3600 mmu_params.\ 3601 xoff_cell_threshold_2p5g_uplink_ports; 3602 /* c95 */ 3603 pgcelllimit_0_2__cellresetlimit = \ 3604 mmu_params.discard_limit_per_port_pg_uplink_port; 3605 /* c95 */ 3606 pgcelllimit_3__cellresetlimit = \ 3607 mmu_params.discard_limit_per_port_pg_uplink_port; 3608 /* c95 */ 3609 pgcelllimit_4_6__cellresetlimit = \ 3610 mmu_params.discard_limit_per_port_pg_uplink_port; 3611 /* c90 */ 3612 pgcelllimit_7__cellresetlimit = \ 3613 mmu_params.\ 3614 xoff_cell_threshold_2p5g_uplink_ports; 3615 } 3616 } else { 3617 if (speed == 10) { /* 1G */ 3618 /* c89 */ 3619 pgcelllimit_0_2__cellsetlimit = \ 3620 mmu_params.\ 3621 xoff_cell_threshold_1g_uplink_ports; 3622 /* c89 */ 3623 pgcelllimit_3__cellsetlimit = \ 3624 mmu_params.\ 3625 xoff_cell_threshold_1g_uplink_ports; 3626 /* c89 */ 3627 pgcelllimit_4_6__cellsetlimit = \ 3628 mmu_params.\ 3629 xoff_cell_threshold_1g_uplink_ports; 3630 /* c89 */ 3631 pgcelllimit_7__cellsetlimit = \ 3632 mmu_params.\ 3633 xoff_cell_threshold_1g_uplink_ports; 3634 /* c89 */ 3635 pgcelllimit_0_2__cellresetlimit = \ 3636 mmu_params.\ 3637 xoff_cell_threshold_1g_uplink_ports; 3638 /* c89 */ 3639 pgcelllimit_3__cellresetlimit = \ 3640 mmu_params.\ 3641 xoff_cell_threshold_1g_uplink_ports; 3642 /* c89 */ 3643 pgcelllimit_4_6__cellresetlimit = \ 3644 mmu_params.\ 3645 xoff_cell_threshold_1g_uplink_ports; 3646 /* c89 */ 3647 pgcelllimit_7__cellresetlimit = \ 3648 mmu_params.\ 3649 xoff_cell_threshold_1g_uplink_ports; 3650 } else { /* 2.5 G */ 3651 /* c90 */ 3652 pgcelllimit_0_2__cellsetlimit = \ 3653 mmu_params.\ 3654 xoff_cell_threshold_2p5g_uplink_ports; 3655 /* c90 */ 3656 pgcelllimit_3__cellsetlimit = \ 3657 mmu_params.\ 3658 xoff_cell_threshold_2p5g_uplink_ports; 3659 /* c90 */ 3660 pgcelllimit_4_6__cellsetlimit = \ 3661 mmu_params.\ 3662 xoff_cell_threshold_2p5g_uplink_ports; 3663 /* c90 */ 3664 pgcelllimit_7__cellsetlimit = \ 3665 mmu_params.\ 3666 xoff_cell_threshold_2p5g_uplink_ports; 3667 /* c90 */ 3668 pgcelllimit_0_2__cellresetlimit = \ 3669 mmu_params.\ 3670 xoff_cell_threshold_2p5g_uplink_ports; 3671 /* c90 */ 3672 pgcelllimit_3__cellresetlimit = \ 3673 mmu_params.\ 3674 xoff_cell_threshold_2p5g_uplink_ports; 3675 /* c90 */ 3676 pgcelllimit_4_6__cellresetlimit = \ 3677 mmu_params.\ 3678 xoff_cell_threshold_2p5g_uplink_ports; 3679 /* c90 */ 3680 pgcelllimit_7__cellresetlimit = \ 3681 mmu_params.\ 3682 xoff_cell_threshold_2p5g_uplink_ports; 3683 } 3684 } 3685 /* c91 */ 3686 ibppktsetlimit_pktsetlimit = \ 3687 mmu_params.\ 3688 xoff_packet_thresholds_per_port_uplink_port; 3689 ibppktsetlimit_resetlimitsel = 3; 3690 mmu_fc_rx_en_mmu_fc_rx_enable = 0; 3691 if (lossless) { 3692 mmu_fc_tx_en_mmu_fc_tx_enable = 0x80; 3693 } else { 3694 mmu_fc_tx_en_mmu_fc_tx_enable = 0; 3695 } 3696 /* c95 */ 3697 pgdiscardsetlimit_0_2__discardsetlimit = \ 3698 mmu_params.discard_limit_per_port_pg_uplink_port; 3699 /* c95 */ 3700 pgdiscardsetlimit_3__discardsetlimit = \ 3701 mmu_params.discard_limit_per_port_pg_uplink_port; 3702 /* c95 */ 3703 pgdiscardsetlimit_4_6__discardsetlimit = \ 3704 mmu_params.discard_limit_per_port_pg_uplink_port; 3705 /* c95 */ 3706 pgdiscardsetlimit_7__discardsetlimit = \ 3707 mmu_params.discard_limit_per_port_pg_uplink_port; 3708 3709 if (lossless) { 3710 /* c36 */ 3711 holcosminxqcnt_0_2__holcosminxqcnt = \ 3712 mmu_params.egress_xq_min_reserve_lossless_downlink_ports; 3713 /* c36 */ 3714 holcosminxqcnt_3__holcosminxqcnt = \ 3715 mmu_params.egress_xq_min_reserve_lossless_downlink_ports; 3716 holcosminxqcnt_4_7__holcosminxqcnt = 0; 3717 /* C103-C72-C74+M70 */ 3718 holcospktsetlimit_0_2__pktsetlimit = \ 3719 mmu_params.shared_xqs_per_uplink_port - \ 3720 mmu_params.skidmarker - \ 3721 mmu_params.prefetch + \ 3722 holcosminxqcnt_0_2__holcosminxqcnt; 3723 /* C103-C72-C74+M71 */ 3724 holcospktsetlimit_3__pktsetlimit = \ 3725 mmu_params.shared_xqs_per_uplink_port - \ 3726 mmu_params.skidmarker - \ 3727 mmu_params.prefetch + \ 3728 holcosminxqcnt_3__holcosminxqcnt; 3729 holcospktsetlimit_4_7__pktsetlimit = 0; 3730 } else { 3731 /* c34 */ 3732 holcosminxqcnt_0_2__holcosminxqcnt = \ 3733 mmu_params.\ 3734 egress_xq_min_reserve_lossy_uplink_and_downlink_ports; 3735 /* c34 */ 3736 holcosminxqcnt_3__holcosminxqcnt = \ 3737 mmu_params.\ 3738 egress_xq_min_reserve_lossy_uplink_and_downlink_ports; 3739 holcosminxqcnt_4_7__holcosminxqcnt = 0; 3740 /* C103-C72-C74+C34 */ 3741 holcospktsetlimit_0_2__pktsetlimit = \ 3742 mmu_params.shared_xqs_per_uplink_port - \ 3743 mmu_params.skidmarker - \ 3744 mmu_params.prefetch + \ 3745 mmu_params.\ 3746 egress_xq_min_reserve_lossy_uplink_and_downlink_ports; 3747 /* C103-C72-C74+C34 */ 3748 holcospktsetlimit_3__pktsetlimit = \ 3749 mmu_params.shared_xqs_per_uplink_port - \ 3750 mmu_params.skidmarker - \ 3751 mmu_params.prefetch + \ 3752 mmu_params.\ 3753 egress_xq_min_reserve_lossy_uplink_and_downlink_ports; 3754 holcospktsetlimit_4_7__pktsetlimit = 0; 3755 } 3756 /* m73 - 1 */ 3757 holcospktresetlimit_0_2__pktresetlimit = \ 3758 holcospktsetlimit_0_2__pktsetlimit - 1; 3759 /* m74 - 1 */ 3760 holcospktresetlimit_3__pktresetlimit = \ 3761 holcospktsetlimit_3__pktsetlimit - 1; 3762 holcospktresetlimit_4_7__pktresetlimit = 0; 3763 /* c62 - 1 */ 3764 cngcospktlimit0_0_7__cngpktsetlimit0 = \ 3765 mmu_params.numxq_per_uplink_ports - 1; 3766 /* c62 - 1 */ 3767 cngcospktlimit1_0_7__cngpktsetlimit1 = \ 3768 mmu_params.numxq_per_uplink_ports - 1; 3769 /* c62 - 1 */ 3770 cngportpktlimit0_cngportpktlimit0 = \ 3771 mmu_params.numxq_per_uplink_ports - 1; 3772 /* c62 - 1 */ 3773 cngportpktlimit1_cngportpktlimit1 = \ 3774 mmu_params.numxq_per_uplink_ports - 1; 3775 /* c103-c72-c74 */ 3776 dynxqcntport_dynxqcntport = \ 3777 mmu_params.shared_xqs_per_uplink_port - \ 3778 mmu_params.skidmarker - \ 3779 mmu_params.prefetch; 3780 /* m83 - 2 */ 3781 dynresetlimport_dynresetlimport = \ 3782 dynxqcntport_dynxqcntport - 2; 3783 if (lossless) { 3784 /* c31 */ 3785 lwmcoscellsetlimit_0_2__cellsetlimit = \ 3786 mmu_params.egress_queue_min_reserve_uplink_ports_lossless; 3787 /* c31 */ 3788 lwmcoscellsetlimit_3__cellsetlimit = \ 3789 mmu_params.egress_queue_min_reserve_uplink_ports_lossless; 3790 lwmcoscellsetlimit_4_7__cellsetlimit = 0; 3791 /* c31 */ 3792 lwmcoscellsetlimit_0_2__cellresetlimit = \ 3793 mmu_params.egress_queue_min_reserve_uplink_ports_lossless; 3794 /* c31 */ 3795 lwmcoscellsetlimit_3__cellresetlimit = \ 3796 mmu_params.egress_queue_min_reserve_uplink_ports_lossless; 3797 lwmcoscellsetlimit_4_7__cellresetlimit = 0; 3798 /* CEILING((C87+C85)*C54+(C88+C86)*C55+(C89+C85)*C53+(C90+C86)*C52+I85,1) */ 3799 tmp = (mmu_params.\ 3800 xoff_cell_thresholds_per_port_pg_1g_port_downlink_ports + 3801 mmu_params.headroom_for_1g_port) * \ 3802 mmu_params.num_1g_ports_downlink_ports + \ 3803 (mmu_params.\ 3804 xoff_cell_thresholds_per_port_pg_2p5g_port_downlink_ports + 3805 mmu_params.headroom_for_2p5g_port) * \ 3806 mmu_params.num_2p5g_ports_downlink_ports + \ 3807 (mmu_params.\ 3808 xoff_cell_threshold_1g_uplink_ports + \ 3809 mmu_params.headroom_for_1g_port) * \ 3810 mmu_params.num_2p5g_ports_uplink_ports + \ 3811 (mmu_params.xoff_cell_threshold_2p5g_uplink_ports + \ 3812 mmu_params.headroom_for_2p5g_port) * \ 3813 mmu_params.num_1g_ports_uplink_ports + \ 3814 lwmcoscellsetlimit_0_2__cellsetlimit; 3815 holcoscellmaxlimit_0_2__cellmaxlimit = _ceil_func(tmp, 1); 3816 /* CEILING((C87+C85)*C54+(C88+C86)*C55+(C89+C85)*C53+(C90+C86)*C52+I86, 1) */ 3817 tmp = (mmu_params.\ 3818 xoff_cell_thresholds_per_port_pg_1g_port_downlink_ports + 3819 mmu_params.headroom_for_1g_port) * \ 3820 mmu_params.num_1g_ports_downlink_ports + \ 3821 (mmu_params.\ 3822 xoff_cell_thresholds_per_port_pg_2p5g_port_downlink_ports + 3823 mmu_params.headroom_for_2p5g_port) * \ 3824 mmu_params.num_2p5g_ports_downlink_ports + \ 3825 (mmu_params.\ 3826 xoff_cell_threshold_1g_uplink_ports + \ 3827 mmu_params.headroom_for_1g_port) * \ 3828 mmu_params.num_2p5g_ports_uplink_ports + \ 3829 (mmu_params.xoff_cell_threshold_2p5g_uplink_ports + \ 3830 mmu_params.headroom_for_2p5g_port) * \ 3831 mmu_params.num_1g_ports_uplink_ports + \ 3832 lwmcoscellsetlimit_3__cellsetlimit; 3833 holcoscellmaxlimit_3__cellmaxlimit = _ceil_func(tmp, 1);; 3834 holcoscellmaxlimit_4_7__cellmaxlimit = 0; 3835 } else { 3836 /* c29 */ 3837 lwmcoscellsetlimit_0_2__cellsetlimit = \ 3838 mmu_params.egress_queue_min_reserve_uplink_ports_lossy; 3839 /* c29 */ 3840 lwmcoscellsetlimit_3__cellsetlimit = \ 3841 mmu_params.egress_queue_min_reserve_uplink_ports_lossy; 3842 lwmcoscellsetlimit_4_7__cellsetlimit = 0; 3843 /* c29 */ 3844 lwmcoscellsetlimit_0_2__cellresetlimit = \ 3845 mmu_params.egress_queue_min_reserve_uplink_ports_lossy; 3846 /* c29 */ 3847 lwmcoscellsetlimit_3__cellresetlimit = \ 3848 mmu_params.egress_queue_min_reserve_uplink_ports_lossy; 3849 lwmcoscellsetlimit_4_7__cellresetlimit = 0; 3850 /* CEILING(c101*C25+o85, 1) */ 3851 tmp = _ceil_func((mmu_params.shared_space_cells * 10 / 4), 10); 3852 holcoscellmaxlimit_0_2__cellmaxlimit = \ 3853 tmp + lwmcoscellsetlimit_0_2__cellsetlimit; 3854 /* CEILING(c101*C25+o86, 1) */ 3855 tmp = _ceil_func((mmu_params.shared_space_cells * 10 / 4), 10); 3856 holcoscellmaxlimit_3__cellmaxlimit = \ 3857 tmp + lwmcoscellsetlimit_3__cellsetlimit; 3858 holcoscellmaxlimit_4_7__cellmaxlimit = 0; 3859 } 3860 /* o91 - c80 */ 3861 holcoscellmaxlimit_0_2__cellmaxresumelimit = \ 3862 holcoscellmaxlimit_0_2__cellmaxlimit - \ 3863 mmu_params.ethernet_mtu; 3864 /* o92 - c80 */ 3865 holcoscellmaxlimit_3__cellmaxresumelimit = \ 3866 holcoscellmaxlimit_3__cellmaxlimit - \ 3867 mmu_params.ethernet_mtu; 3868 holcoscellmaxlimit_4_7__cellmaxresumelimit = 0; 3869 /* c101 */ 3870 dyncelllimit_dyncellsetlimit = \ 3871 mmu_params.shared_space_cells; 3872 /* o97-c80*2 */ 3873 dyncelllimit_dyncellresetlimit = \ 3874 dyncelllimit_dyncellsetlimit - \ 3875 (mmu_params.ethernet_mtu * 2); 3876 color_drop_en_color_drop_en = 0; 3877 shared_pool_ctrl_dynamic_cos_drop_en = 255; 3878 shared_pool_ctrl_shared_pool_discard_en = 255; 3879 shared_pool_ctrl_sharded_pool_xoff_en = 0; 3880 } else { /* downlink port 1G, 2.5G */ 3881 if (lossless) { 3882 SOC_IF_ERROR_RETURN(WRITE_PG2TCr(unit, port, 7, 0x80)); 3883 } 3884 3885 if (lossless) { 3886 if (speed == 10) { /* 1G */ 3887 /* c93 */ 3888 pgcelllimit_0_2__cellsetlimit = \ 3889 mmu_params.discard_limit_per_port_pg_downlink_1g_port; 3890 /* c93 */ 3891 pgcelllimit_3__cellsetlimit = \ 3892 mmu_params.discard_limit_per_port_pg_downlink_1g_port; 3893 /* c93 */ 3894 pgcelllimit_4_6__cellsetlimit = \ 3895 mmu_params.discard_limit_per_port_pg_downlink_1g_port; 3896 /* c87 */ 3897 pgcelllimit_7__cellsetlimit = \ 3898 mmu_params.\ 3899 xoff_cell_thresholds_per_port_pg_1g_port_downlink_ports; 3900 /* c93 */ 3901 pgcelllimit_0_2__cellresetlimit = \ 3902 mmu_params.discard_limit_per_port_pg_downlink_1g_port; 3903 /* c93 */ 3904 pgcelllimit_3__cellresetlimit = \ 3905 mmu_params.discard_limit_per_port_pg_downlink_1g_port; 3906 /* c93 */ 3907 pgcelllimit_4_6__cellresetlimit = \ 3908 mmu_params.discard_limit_per_port_pg_downlink_1g_port; 3909 /* c87 */ 3910 pgcelllimit_7__cellresetlimit = \ 3911 mmu_params.\ 3912 xoff_cell_thresholds_per_port_pg_1g_port_downlink_ports; 3913 /* c93 */ 3914 pgdiscardsetlimit_0_2__discardsetlimit = \ 3915 mmu_params.discard_limit_per_port_pg_downlink_1g_port; 3916 /* c93 */ 3917 pgdiscardsetlimit_3__discardsetlimit = \ 3918 mmu_params.discard_limit_per_port_pg_downlink_1g_port; 3919 /* c93 */ 3920 pgdiscardsetlimit_4_6__discardsetlimit = \ 3921 mmu_params.discard_limit_per_port_pg_downlink_1g_port; 3922 /* c93 */ 3923 pgdiscardsetlimit_7__discardsetlimit = \ 3924 mmu_params.discard_limit_per_port_pg_downlink_1g_port; 3925 } else { /* 2.5 G */ 3926 /* c94 */ 3927 pgcelllimit_0_2__cellsetlimit = \ 3928 mmu_params.discard_limit_per_port_pg_downlink_2p5g_port; 3929 /* c94 */ 3930 pgcelllimit_3__cellsetlimit = \ 3931 mmu_params.discard_limit_per_port_pg_downlink_2p5g_port; 3932 /* c94 */ 3933 pgcelllimit_4_6__cellsetlimit = \ 3934 mmu_params.discard_limit_per_port_pg_downlink_2p5g_port; 3935 /* c88 */ 3936 pgcelllimit_7__cellsetlimit = \ 3937 mmu_params.\ 3938 xoff_cell_thresholds_per_port_pg_2p5g_port_downlink_ports; 3939 /* c94 */ 3940 pgcelllimit_0_2__cellresetlimit = \ 3941 mmu_params.discard_limit_per_port_pg_downlink_2p5g_port; 3942 /* c94 */ 3943 pgcelllimit_3__cellresetlimit = \ 3944 mmu_params.discard_limit_per_port_pg_downlink_2p5g_port; 3945 /* c94 */ 3946 pgcelllimit_4_6__cellresetlimit = \ 3947 mmu_params.discard_limit_per_port_pg_downlink_2p5g_port; 3948 /* c88 */ 3949 pgcelllimit_7__cellresetlimit = \ 3950 mmu_params.\ 3951 xoff_cell_thresholds_per_port_pg_2p5g_port_downlink_ports; 3952 /* c94 */ 3953 pgdiscardsetlimit_0_2__discardsetlimit = \ 3954 mmu_params.discard_limit_per_port_pg_downlink_2p5g_port; 3955 /* c94 */ 3956 pgdiscardsetlimit_3__discardsetlimit = \ 3957 mmu_params.discard_limit_per_port_pg_downlink_2p5g_port; 3958 /* c94 */ 3959 pgdiscardsetlimit_4_6__discardsetlimit = \ 3960 mmu_params.discard_limit_per_port_pg_downlink_2p5g_port; 3961 /* c94 */ 3962 pgdiscardsetlimit_7__discardsetlimit = \ 3963 mmu_params.discard_limit_per_port_pg_downlink_2p5g_port; 3964 } 3965 } else { 3966 if (speed == 10) { /* 1G */ 3967 /* c87 */ 3968 pgcelllimit_0_2__cellsetlimit = \ 3969 mmu_params.\ 3970 xoff_cell_thresholds_per_port_pg_1g_port_downlink_ports; 3971 /* c87 */ 3972 pgcelllimit_3__cellsetlimit = \ 3973 mmu_params.\ 3974 xoff_cell_thresholds_per_port_pg_1g_port_downlink_ports; 3975 /* c87 */ 3976 pgcelllimit_4_6__cellsetlimit = \ 3977 mmu_params.\ 3978 xoff_cell_thresholds_per_port_pg_1g_port_downlink_ports; 3979 /* c87 */ 3980 pgcelllimit_7__cellsetlimit = \ 3981 mmu_params.\ 3982 xoff_cell_thresholds_per_port_pg_1g_port_downlink_ports; 3983 /* c87 */ 3984 pgcelllimit_0_2__cellresetlimit = \ 3985 mmu_params.\ 3986 xoff_cell_thresholds_per_port_pg_1g_port_downlink_ports; 3987 /* c87 */ 3988 pgcelllimit_3__cellresetlimit = \ 3989 mmu_params.\ 3990 xoff_cell_thresholds_per_port_pg_1g_port_downlink_ports; 3991 /* c87 */ 3992 pgcelllimit_4_6__cellresetlimit = \ 3993 mmu_params.\ 3994 xoff_cell_thresholds_per_port_pg_1g_port_downlink_ports; 3995 /* c87 */ 3996 pgcelllimit_7__cellresetlimit = \ 3997 mmu_params.\ 3998 xoff_cell_thresholds_per_port_pg_1g_port_downlink_ports; 3999 /* c93 */ 4000 pgdiscardsetlimit_0_2__discardsetlimit = \ 4001 mmu_params.discard_limit_per_port_pg_downlink_1g_port; 4002 /* c93 */ 4003 pgdiscardsetlimit_3__discardsetlimit = \ 4004 mmu_params.discard_limit_per_port_pg_downlink_1g_port; 4005 /* c93 */ 4006 pgdiscardsetlimit_4_6__discardsetlimit = \ 4007 mmu_params.discard_limit_per_port_pg_downlink_1g_port; 4008 /* c93 */ 4009 pgdiscardsetlimit_7__discardsetlimit = \ 4010 mmu_params.discard_limit_per_port_pg_downlink_1g_port; 4011 } else { /* 2.5 G */ 4012 /* c88 */ 4013 pgcelllimit_0_2__cellsetlimit = \ 4014 mmu_params.\ 4015 xoff_cell_thresholds_per_port_pg_2p5g_port_downlink_ports; 4016 /* c88 */ 4017 pgcelllimit_3__cellsetlimit = \ 4018 mmu_params.\ 4019 xoff_cell_thresholds_per_port_pg_2p5g_port_downlink_ports; 4020 /* c88 */ 4021 pgcelllimit_4_6__cellsetlimit = \ 4022 mmu_params.\ 4023 xoff_cell_thresholds_per_port_pg_2p5g_port_downlink_ports; 4024 /* c88 */ 4025 pgcelllimit_7__cellsetlimit = \ 4026 mmu_params.\ 4027 xoff_cell_thresholds_per_port_pg_2p5g_port_downlink_ports; 4028 /* c88 */ 4029 pgcelllimit_0_2__cellresetlimit = \ 4030 mmu_params.\ 4031 xoff_cell_thresholds_per_port_pg_2p5g_port_downlink_ports; 4032 /* c88 */ 4033 pgcelllimit_3__cellresetlimit = \ 4034 mmu_params.\ 4035 xoff_cell_thresholds_per_port_pg_2p5g_port_downlink_ports; 4036 /* c88 */ 4037 pgcelllimit_4_6__cellresetlimit = \ 4038 mmu_params.\ 4039 xoff_cell_thresholds_per_port_pg_2p5g_port_downlink_ports; 4040 /* c88 */ 4041 pgcelllimit_7__cellresetlimit = \ 4042 mmu_params.\ 4043 xoff_cell_thresholds_per_port_pg_2p5g_port_downlink_ports; 4044 /* c94 */ 4045 pgdiscardsetlimit_0_2__discardsetlimit = \ 4046 mmu_params.discard_limit_per_port_pg_downlink_2p5g_port; 4047 /* c94 */ 4048 pgdiscardsetlimit_3__discardsetlimit = \ 4049 mmu_params.discard_limit_per_port_pg_downlink_2p5g_port; 4050 /* c94 */ 4051 pgdiscardsetlimit_4_6__discardsetlimit = \ 4052 mmu_params.discard_limit_per_port_pg_downlink_2p5g_port; 4053 /* c94 */ 4054 pgdiscardsetlimit_7__discardsetlimit = \ 4055 mmu_params.discard_limit_per_port_pg_downlink_2p5g_port; 4056 } 4057 } 4058 /* c92 */ 4059 ibppktsetlimit_pktsetlimit = \ 4060 mmu_params.\ 4061 xoff_packet_thresholds_per_port_downlink_port; 4062 ibppktsetlimit_resetlimitsel = 3; 4063 mmu_fc_rx_en_mmu_fc_rx_enable = 0; 4064 if (lossless) { 4065 mmu_fc_tx_en_mmu_fc_tx_enable = 0x80; 4066 } else { 4067 mmu_fc_tx_en_mmu_fc_tx_enable = 0; 4068 } 4069 4070 if (lossless) { 4071 /* c35 */ 4072 holcosminxqcnt_0_2__holcosminxqcnt = \ 4073 mmu_params.egress_xq_min_reserve_lossless_uplink_ports; 4074 /* c35 */ 4075 holcosminxqcnt_3__holcosminxqcnt = \ 4076 mmu_params.egress_xq_min_reserve_lossless_uplink_ports; 4077 holcosminxqcnt_4_7__holcosminxqcnt = 0; 4078 /* C105-C72-C74+I70 */ 4079 holcospktsetlimit_0_2__pktsetlimit = \ 4080 mmu_params.shared_xqs_per_downlink_port - \ 4081 mmu_params.skidmarker - \ 4082 mmu_params.prefetch + \ 4083 holcosminxqcnt_0_2__holcosminxqcnt; 4084 /* C105-C72-C74+I71 */ 4085 holcospktsetlimit_3__pktsetlimit = \ 4086 mmu_params.shared_xqs_per_downlink_port - \ 4087 mmu_params.skidmarker - \ 4088 mmu_params.prefetch + \ 4089 holcosminxqcnt_3__holcosminxqcnt; 4090 holcospktsetlimit_4_7__pktsetlimit = 0; 4091 } else { 4092 /* c34 */ 4093 holcosminxqcnt_0_2__holcosminxqcnt = \ 4094 mmu_params.\ 4095 egress_xq_min_reserve_lossy_uplink_and_downlink_ports; 4096 /* c34 */ 4097 holcosminxqcnt_3__holcosminxqcnt = \ 4098 mmu_params.\ 4099 egress_xq_min_reserve_lossy_uplink_and_downlink_ports; 4100 holcosminxqcnt_4_7__holcosminxqcnt = 0; 4101 /* C105-C72-C74+C34 */ 4102 holcospktsetlimit_0_2__pktsetlimit = \ 4103 mmu_params.shared_xqs_per_downlink_port - \ 4104 mmu_params.skidmarker - \ 4105 mmu_params.prefetch + \ 4106 holcosminxqcnt_0_2__holcosminxqcnt; 4107 /* C105-C72-C74+C34 */ 4108 holcospktsetlimit_3__pktsetlimit = \ 4109 mmu_params.shared_xqs_per_downlink_port - \ 4110 mmu_params.skidmarker - \ 4111 mmu_params.prefetch + \ 4112 holcosminxqcnt_0_2__holcosminxqcnt; 4113 holcospktsetlimit_4_7__pktsetlimit = 0; 4114 } 4115 holcospktresetlimit_0_2__pktresetlimit = \ 4116 holcospktsetlimit_0_2__pktsetlimit - 1; 4117 holcospktresetlimit_3__pktresetlimit = \ 4118 holcospktsetlimit_3__pktsetlimit - 1; 4119 holcospktresetlimit_4_7__pktresetlimit = 0; 4120 /* c63 - 1 */ 4121 cngcospktlimit0_0_7__cngpktsetlimit0 = \ 4122 mmu_params.numxq_per_downlink_ports_and_cpu_port - 1; 4123 /* c63 - 1 */ 4124 cngcospktlimit1_0_7__cngpktsetlimit1 = \ 4125 mmu_params.numxq_per_downlink_ports_and_cpu_port - 1; 4126 /* c63 - 1 */ 4127 cngportpktlimit0_cngportpktlimit0 = \ 4128 mmu_params.numxq_per_downlink_ports_and_cpu_port - 1; 4129 /* c63 - 1 */ 4130 cngportpktlimit1_cngportpktlimit1 = \ 4131 mmu_params.numxq_per_downlink_ports_and_cpu_port - 1; 4132 /* c105-c72-c74 */ 4133 dynxqcntport_dynxqcntport = \ 4134 mmu_params.shared_xqs_per_downlink_port - \ 4135 mmu_params.skidmarker - \ 4136 mmu_params.prefetch; 4137 /* I83-2 */ 4138 dynresetlimport_dynresetlimport = \ 4139 dynxqcntport_dynxqcntport - 2; 4140 if (lossless) { 4141 /* c32 */ 4142 lwmcoscellsetlimit_0_2__cellsetlimit = \ 4143 mmu_params.egress_queue_min_reserve_downlink_ports_lossless; 4144 /* c32 */ 4145 lwmcoscellsetlimit_3__cellsetlimit = \ 4146 mmu_params.egress_queue_min_reserve_downlink_ports_lossless; 4147 lwmcoscellsetlimit_4_7__cellsetlimit = 0; 4148 /* c32 */ 4149 lwmcoscellsetlimit_0_2__cellresetlimit = \ 4150 mmu_params.egress_queue_min_reserve_downlink_ports_lossless; 4151 /* c32 */ 4152 lwmcoscellsetlimit_3__cellresetlimit = \ 4153 mmu_params.egress_queue_min_reserve_downlink_ports_lossless; 4154 lwmcoscellsetlimit_4_7__cellresetlimit = 0; 4155 /* CEILING((C87+C85)*C54+(C88+C86)*C55+(C89+C85)*C53+(C90+C86)*C52+I85, 1) */ 4156 tmp = (mmu_params.\ 4157 xoff_cell_thresholds_per_port_pg_1g_port_downlink_ports + 4158 mmu_params.headroom_for_1g_port) * \ 4159 mmu_params.num_1g_ports_downlink_ports + \ 4160 (mmu_params.\ 4161 xoff_cell_thresholds_per_port_pg_2p5g_port_downlink_ports + 4162 mmu_params.headroom_for_2p5g_port) * \ 4163 mmu_params.num_2p5g_ports_downlink_ports + \ 4164 (mmu_params.\ 4165 xoff_cell_threshold_1g_uplink_ports + \ 4166 mmu_params.headroom_for_1g_port) * \ 4167 mmu_params.num_2p5g_ports_uplink_ports + \ 4168 (mmu_params.xoff_cell_threshold_2p5g_uplink_ports + \ 4169 mmu_params.headroom_for_2p5g_port) * \ 4170 mmu_params.num_1g_ports_uplink_ports + \ 4171 lwmcoscellsetlimit_0_2__cellsetlimit; 4172 holcoscellmaxlimit_0_2__cellmaxlimit = _ceil_func(tmp, 1); 4173 /* CEILING((C87+C85)*C54+(C88+C86)*C55+(C89+C85)*C53+(C90+C86)*C52+I86, 1) */ 4174 tmp = (mmu_params.\ 4175 xoff_cell_thresholds_per_port_pg_1g_port_downlink_ports + 4176 mmu_params.headroom_for_1g_port) * \ 4177 mmu_params.num_1g_ports_downlink_ports + \ 4178 (mmu_params.\ 4179 xoff_cell_thresholds_per_port_pg_2p5g_port_downlink_ports + 4180 mmu_params.headroom_for_2p5g_port) * \ 4181 mmu_params.num_2p5g_ports_downlink_ports + \ 4182 (mmu_params.\ 4183 xoff_cell_threshold_1g_uplink_ports + \ 4184 mmu_params.headroom_for_1g_port) * \ 4185 mmu_params.num_2p5g_ports_uplink_ports + \ 4186 (mmu_params.xoff_cell_threshold_2p5g_uplink_ports + \ 4187 mmu_params.headroom_for_2p5g_port) * \ 4188 mmu_params.num_1g_ports_uplink_ports + \ 4189 lwmcoscellsetlimit_3__cellsetlimit; 4190 holcoscellmaxlimit_3__cellmaxlimit = _ceil_func(tmp, 1); 4191 holcoscellmaxlimit_4_7__cellmaxlimit = 0; 4192 } else { 4193 /* c30 */ 4194 lwmcoscellsetlimit_0_2__cellsetlimit = \ 4195 mmu_params.egress_queue_min_reserve_downlink_ports_lossy; 4196 /* c30 */ 4197 lwmcoscellsetlimit_3__cellsetlimit = \ 4198 mmu_params.egress_queue_min_reserve_downlink_ports_lossy; 4199 lwmcoscellsetlimit_4_7__cellsetlimit = 0; 4200 /* c30 */ 4201 lwmcoscellsetlimit_0_2__cellresetlimit = \ 4202 mmu_params.egress_queue_min_reserve_downlink_ports_lossy; 4203 /* c30 */ 4204 lwmcoscellsetlimit_3__cellresetlimit = \ 4205 mmu_params.egress_queue_min_reserve_downlink_ports_lossy; 4206 lwmcoscellsetlimit_4_7__cellresetlimit = 0; 4207 /* CEILING(c101*C25+o85, 1) */ 4208 tmp = _ceil_func((mmu_params.shared_space_cells * 10 / 4), 10); 4209 holcoscellmaxlimit_0_2__cellmaxlimit = \ 4210 tmp + lwmcoscellsetlimit_0_2__cellsetlimit; 4211 /* CEILING(c101*C25+o87, 1) */ 4212 tmp = _ceil_func((mmu_params.shared_space_cells * 10 / 4), 10); 4213 holcoscellmaxlimit_3__cellmaxlimit = \ 4214 tmp + lwmcoscellsetlimit_3__cellsetlimit; 4215 holcoscellmaxlimit_4_7__cellmaxlimit = 0; 4216 } 4217 /* I91-C80 */ 4218 holcoscellmaxlimit_0_2__cellmaxresumelimit = \ 4219 holcoscellmaxlimit_0_2__cellmaxlimit - \ 4220 mmu_params.ethernet_mtu; 4221 /* I92-C80 */ 4222 holcoscellmaxlimit_3__cellmaxresumelimit = \ 4223 holcoscellmaxlimit_3__cellmaxlimit - \ 4224 mmu_params.ethernet_mtu; 4225 holcoscellmaxlimit_4_7__cellmaxresumelimit = 0; 4226 /* c101 */ 4227 dyncelllimit_dyncellsetlimit = \ 4228 mmu_params.shared_space_cells; 4229 /* o97-c80*2 */ 4230 dyncelllimit_dyncellresetlimit = \ 4231 dyncelllimit_dyncellsetlimit - \ 4232 (mmu_params.ethernet_mtu * 2); 4233 color_drop_en_color_drop_en = 0; 4234 shared_pool_ctrl_dynamic_cos_drop_en = 255; 4235 shared_pool_ctrl_shared_pool_discard_en = 255; 4236 shared_pool_ctrl_sharded_pool_xoff_en = 0; 4237 } 4238 4239 /* Program the setting */ 4240 val = 0; 4241 /* i52 = c92 */ 4242 soc_reg_field_set(unit, IBPPKTSETLIMITr, &val, PKTSETLIMITf, 4243 ibppktsetlimit_pktsetlimit); 4244 soc_reg_field_set(unit, IBPPKTSETLIMITr, &val, RESETLIMITSELf, 4245 ibppktsetlimit_resetlimitsel); 4246 SOC_IF_ERROR_RETURN(WRITE_IBPPKTSETLIMITr(unit, port, val)); 4247 4248 val = 0; 4249 soc_reg_field_set(unit, MMU_FC_RX_ENr, &val, MMU_FC_RX_ENABLEf, 4250 mmu_fc_rx_en_mmu_fc_rx_enable); 4251 SOC_IF_ERROR_RETURN(WRITE_MMU_FC_RX_ENr(unit, port, val)); 4252 val = 0; 4253 soc_reg_field_set(unit, MMU_FC_TX_ENr, &val, MMU_FC_TX_ENABLEf, 4254 mmu_fc_tx_en_mmu_fc_tx_enable); 4255 SOC_IF_ERROR_RETURN(WRITE_MMU_FC_TX_ENr(unit, port, val)); 4256 4257 for (cos = 0; cos < WH2_QUEUE_MAX_NUM; cos++) { 4258 if ((cos >= 0) && (cos <= 2)) { 4259 fld_val = holcospktsetlimit_0_2__pktsetlimit; 4260 } else if (cos == 3) { 4261 fld_val = holcospktsetlimit_3__pktsetlimit; 4262 } else { 4263 fld_val = holcospktsetlimit_4_7__pktsetlimit; 4264 } 4265 SOC_IF_ERROR_RETURN 4266 (READ_HOLCOSPKTSETLIMITr(unit, port, cos, &val)); 4267 soc_reg_field_set(unit, HOLCOSPKTSETLIMITr, &val, 4268 PKTSETLIMITf, fld_val); 4269 SOC_IF_ERROR_RETURN 4270 (WRITE_HOLCOSPKTSETLIMITr(unit, port, cos, val)); 4271 4272 if ((cos >= 0) && (cos <= 2)) { 4273 fld_val = holcospktresetlimit_0_2__pktresetlimit; 4274 } else if (cos == 3) { 4275 fld_val = holcospktresetlimit_3__pktresetlimit; 4276 } else { 4277 fld_val = holcospktresetlimit_4_7__pktresetlimit; 4278 } 4279 SOC_IF_ERROR_RETURN 4280 (READ_HOLCOSPKTRESETLIMITr(unit, port, cos, &val)); 4281 soc_reg_field_set(unit, HOLCOSPKTRESETLIMITr, &val, 4282 PKTRESETLIMITf, fld_val); 4283 SOC_IF_ERROR_RETURN 4284 (WRITE_HOLCOSPKTRESETLIMITr(unit, port, cos, val)); 4285 4286 if ((cos >= 0) && (cos <= 2)) { 4287 fld_val = holcosminxqcnt_0_2__holcosminxqcnt; 4288 } else if (cos == 3) { 4289 fld_val = holcosminxqcnt_3__holcosminxqcnt; 4290 } else { 4291 fld_val = holcosminxqcnt_4_7__holcosminxqcnt; 4292 } 4293 val = 0; 4294 soc_reg_field_set(unit, HOLCOSMINXQCNTr, &val, 4295 HOLCOSMINXQCNTf, fld_val); 4296 SOC_IF_ERROR_RETURN 4297 (WRITE_HOLCOSMINXQCNTr(unit, port, cos, val)); 4298 4299 val = 0; 4300 if ((cos >= 0) && (cos <= 2)) { 4301 fld_val = lwmcoscellsetlimit_0_2__cellsetlimit; 4302 } else if (cos == 3) { 4303 fld_val = lwmcoscellsetlimit_3__cellsetlimit; 4304 } else { 4305 fld_val = lwmcoscellsetlimit_4_7__cellsetlimit; 4306 } 4307 soc_reg_field_set(unit, LWMCOSCELLSETLIMITr, &val, 4308 CELLSETLIMITf, fld_val); 4309 if ((cos >= 0) && (cos <= 2)) { 4310 fld_val = lwmcoscellsetlimit_0_2__cellresetlimit; 4311 } else if (cos == 3) { 4312 fld_val = lwmcoscellsetlimit_3__cellresetlimit; 4313 } else { 4314 fld_val = lwmcoscellsetlimit_4_7__cellresetlimit; 4315 } 4316 soc_reg_field_set(unit, LWMCOSCELLSETLIMITr, &val, 4317 CELLRESETLIMITf, fld_val); 4318 SOC_IF_ERROR_RETURN 4319 (WRITE_LWMCOSCELLSETLIMITr(unit, port, cos, val)); 4320 4321 val = 0; 4322 if ((cos >= 0) && (cos <= 2)) { 4323 fld_val = holcoscellmaxlimit_0_2__cellmaxlimit; 4324 } else if (cos == 3) { 4325 fld_val = holcoscellmaxlimit_3__cellmaxlimit; 4326 } else { 4327 fld_val = holcoscellmaxlimit_4_7__cellmaxlimit; 4328 } 4329 soc_reg_field_set(unit, HOLCOSCELLMAXLIMITr, &val, 4330 CELLMAXLIMITf, fld_val); 4331 if ((cos >= 0) && (cos <= 2)) { 4332 fld_val = holcoscellmaxlimit_0_2__cellmaxresumelimit; 4333 } else if (cos == 3) { 4334 fld_val = holcoscellmaxlimit_3__cellmaxresumelimit; 4335 } else { 4336 fld_val = holcoscellmaxlimit_4_7__cellmaxresumelimit; 4337 } 4338 soc_reg_field_set(unit, HOLCOSCELLMAXLIMITr, &val, 4339 CELLMAXRESUMELIMITf, fld_val); 4340 SOC_IF_ERROR_RETURN 4341 (WRITE_HOLCOSCELLMAXLIMITr(unit, port, cos, val)); 4342 4343 val = 0; 4344 if ((cos >= 0) && (cos <= 2)) { 4345 fld_val = pgcelllimit_0_2__cellsetlimit; 4346 } else if (cos == 3) { 4347 fld_val = pgcelllimit_3__cellsetlimit; 4348 } else if ((cos >= 4) && (cos <= 6)) { 4349 fld_val = pgcelllimit_4_6__cellsetlimit; 4350 } else { 4351 fld_val = pgcelllimit_7__cellsetlimit; 4352 } 4353 soc_reg_field_set(unit, PGCELLLIMITr, &val, 4354 CELLSETLIMITf, fld_val); 4355 if ((cos >= 0) && (cos <= 2)) { 4356 fld_val = pgcelllimit_0_2__cellresetlimit; 4357 } else if (cos == 3) { 4358 fld_val = pgcelllimit_3__cellresetlimit; 4359 } else if ((cos >= 4) && (cos <= 6)) { 4360 fld_val = pgcelllimit_4_6__cellresetlimit; 4361 } else { 4362 fld_val = pgcelllimit_7__cellresetlimit; 4363 } 4364 soc_reg_field_set(unit, PGCELLLIMITr, &val, 4365 CELLRESETLIMITf, fld_val); 4366 SOC_IF_ERROR_RETURN 4367 (WRITE_PGCELLLIMITr(unit, port, cos, val)); 4368 4369 val = 0; 4370 if ((cos >= 0) && (cos <= 2)) { 4371 fld_val = pgdiscardsetlimit_0_2__discardsetlimit; 4372 } else if (cos == 3) { 4373 fld_val = pgdiscardsetlimit_3__discardsetlimit; 4374 } else if ((cos >= 4) && (cos <= 6)) { 4375 fld_val = pgdiscardsetlimit_4_6__discardsetlimit; 4376 } else { 4377 fld_val = pgdiscardsetlimit_7__discardsetlimit; 4378 } 4379 soc_reg_field_set(unit, PGDISCARDSETLIMITr, &val, 4380 DISCARDSETLIMITf, fld_val); 4381 SOC_IF_ERROR_RETURN 4382 (WRITE_PGDISCARDSETLIMITr(unit, port, cos, val)); 4383 4384 val = 0; 4385 soc_reg_field_set(unit, CNGCOSPKTLIMIT0r, &val, 4386 CNGPKTSETLIMIT0f, 4387 cngcospktlimit0_0_7__cngpktsetlimit0); 4388 SOC_IF_ERROR_RETURN 4389 (WRITE_CNGCOSPKTLIMIT0r(unit, port, cos, val)); 4390 val = 0; 4391 soc_reg_field_set(unit, CNGCOSPKTLIMIT1r, &val, 4392 CNGPKTSETLIMIT1f, 4393 cngcospktlimit1_0_7__cngpktsetlimit1); 4394 SOC_IF_ERROR_RETURN 4395 (WRITE_CNGCOSPKTLIMIT1r(unit, port, cos, val)); 4396 } 4397 4398 val = 0; 4399 soc_reg_field_set(unit, CNGPORTPKTLIMIT0r, &val, 4400 CNGPORTPKTLIMIT0f, 4401 cngportpktlimit0_cngportpktlimit0); 4402 SOC_IF_ERROR_RETURN(WRITE_CNGPORTPKTLIMIT0r(unit, port, val)); 4403 4404 val = 0; 4405 soc_reg_field_set(unit, CNGPORTPKTLIMIT1r, &val, 4406 CNGPORTPKTLIMIT1f, 4407 cngportpktlimit1_cngportpktlimit1); 4408 SOC_IF_ERROR_RETURN(WRITE_CNGPORTPKTLIMIT1r(unit, port, val)); 4409 4410 val = 0; 4411 soc_reg_field_set(unit, DYNXQCNTPORTr, &val, 4412 DYNXQCNTPORTf, 4413 dynxqcntport_dynxqcntport); 4414 SOC_IF_ERROR_RETURN(WRITE_DYNXQCNTPORTr(unit, port, val)); 4415 4416 val = 0; 4417 soc_reg_field_set(unit, DYNRESETLIMPORTr, &val, 4418 DYNRESETLIMPORTf, 4419 dynresetlimport_dynresetlimport); 4420 SOC_IF_ERROR_RETURN(WRITE_DYNRESETLIMPORTr(unit, port, val)); 4421 4422 val = 0; 4423 soc_reg_field_set(unit, DYNCELLLIMITr, &val, 4424 DYNCELLSETLIMITf, 4425 dyncelllimit_dyncellsetlimit); 4426 soc_reg_field_set(unit, DYNCELLLIMITr, &val, 4427 DYNCELLRESETLIMITf, 4428 dyncelllimit_dyncellresetlimit); 4429 SOC_IF_ERROR_RETURN(WRITE_DYNCELLLIMITr(unit, port, val)); 4430 4431 val = 0; 4432 soc_reg_field_set(unit, COLOR_DROP_ENr, &val, 4433 COLOR_DROP_ENf, 4434 color_drop_en_color_drop_en); 4435 SOC_IF_ERROR_RETURN(WRITE_COLOR_DROP_ENr(unit, port, val)); 4436 4437 val = 0; 4438 soc_reg_field_set(unit, SHARED_POOL_CTRLr, &val, 4439 DYNAMIC_COS_DROP_ENf, 4440 shared_pool_ctrl_dynamic_cos_drop_en); 4441 soc_reg_field_set(unit, SHARED_POOL_CTRLr, &val, 4442 SHARED_POOL_DISCARD_ENf, 4443 shared_pool_ctrl_shared_pool_discard_en); 4444 soc_reg_field_set(unit, SHARED_POOL_CTRLr, &val, 4445 SHARED_POOL_XOFF_ENf, 4446 shared_pool_ctrl_sharded_pool_xoff_en); 4447 SOC_IF_ERROR_RETURN(WRITE_SHARED_POOL_CTRLr(unit, port, val)); 4448 } 4449 4450 return SOC_E_NONE; 4451 } 4452 4453 STATIC int 4454 soc_wolfhound2_mmu_lossy_or_lossless_init_helper(int unit, int lossless) 4455 { 4456 uint32 tmp; 4457 wh2_sku_info_t *matched_port_config = NULL; 4458 int option; 4459 int downlink_port_1g; 4460 int downlink_port_2p5g; 4461 int uplink_port_1g; 4462 int uplink_port_2p5g; 4463 4464 matched_port_config = &wh2_sku_port_config[matched_devid_idx[unit]]; 4465 option = matched_port_config->config_option; 4466 /* MMU settings */ 4467 switch (option) { 4468 case 1: 4469 downlink_port_1g = 20; 4470 downlink_port_2p5g = 4; 4471 uplink_port_1g = 0; 4472 uplink_port_2p5g = 4; 4473 break; 4474 case 2: 4475 case 3: 4476 downlink_port_1g = 24; 4477 downlink_port_2p5g = 0; 4478 uplink_port_1g = 0; 4479 uplink_port_2p5g = 4; 4480 break; 4481 case 4: 4482 case 5: 4483 case 6: 4484 downlink_port_1g = 24; 4485 downlink_port_2p5g = 0; 4486 uplink_port_1g = 4; 4487 uplink_port_2p5g = 0; 4488 break; 4489 case 7: 4490 downlink_port_1g = 12; 4491 downlink_port_2p5g = 4; 4492 uplink_port_1g = 0; 4493 uplink_port_2p5g = 4; 4494 break; 4495 case 8: 4496 case 9: 4497 downlink_port_1g = 16; 4498 downlink_port_2p5g = 0; 4499 uplink_port_1g = 0; 4500 uplink_port_2p5g = 4; 4501 break; 4502 case 10: 4503 case 11: 4504 case 12: 4505 downlink_port_1g = 16; 4506 downlink_port_2p5g = 0; 4507 uplink_port_1g = 4; 4508 uplink_port_2p5g = 0; 4509 break; 4510 case 13: 4511 downlink_port_1g = 4; 4512 downlink_port_2p5g = 4; 4513 uplink_port_1g = 0; 4514 uplink_port_2p5g = 4; 4515 break; 4516 case 14: 4517 case 15: 4518 downlink_port_1g = 8; 4519 downlink_port_2p5g = 0; 4520 uplink_port_1g = 0; 4521 uplink_port_2p5g = 4; 4522 break; 4523 case 16: 4524 case 17: 4525 case 18: 4526 downlink_port_1g = 8; 4527 downlink_port_2p5g = 0; 4528 uplink_port_1g = 4; 4529 uplink_port_2p5g = 0; 4530 break; 4531 default: 4532 /* Default matched wh2_sku_port_config[0] */ 4533 downlink_port_1g = 20; 4534 downlink_port_2p5g = 4; 4535 uplink_port_1g = 0; 4536 uplink_port_2p5g = 4; 4537 break; 4538 } 4539 4540 /* Prepare MMU settings */ 4541 /* 4542 * Traffic Attributes 4543 */ 4544 /* c7 */ 4545 mmu_params.min_packet_size_traffic_attr = 64; 4546 /* 4547 * c8 4548 * the value is 1.5 in doc, save 15 instead in sw. 4549 * any later usage should take care of this. 4550 */ 4551 mmu_params.ethernet_mtu_traffic_attr = 15; 4552 /* c9 */ 4553 mmu_params.max_packet_size_traffic_attr = 12288; 4554 /* c10 */ 4555 mmu_params.standard_jumbo_frame_traffic_attr = 9216; 4556 /* c11 */ 4557 mmu_params.lossless_traffic_mtu_size_traffic_attr = 2048; 4558 4559 /* 4560 * General Information 4561 * moved to earlier place as these are needed by others 4562 */ 4563 /* c79 = CEILING(C7/c49, 1)*/ 4564 tmp = mmu_params.min_packet_size_traffic_attr / CELL_SIZE; 4565 mmu_params.min_packet_size = _ceil_func(tmp, 1); 4566 /* c80 = CEILING(C8*1024/c49, 1)*/ 4567 tmp = (mmu_params.ethernet_mtu_traffic_attr * 1024) / CELL_SIZE; 4568 tmp /= 10; /* The value is 1.5 in MMU setting data, save as 15 in SW */ 4569 mmu_params.ethernet_mtu = _ceil_func(tmp, 1); 4570 /* c81 = CEILING(C9/c49, 1)*/ 4571 tmp = mmu_params.max_packet_size_traffic_attr / CELL_SIZE; 4572 mmu_params.max_packet_size = _ceil_func(tmp, 1); 4573 /* c82 = CEILING(C10/c49, 1)*/ 4574 tmp = mmu_params.standard_jumbo_frame_traffic_attr / CELL_SIZE; 4575 mmu_params.standard_jumbo_frame = _ceil_func(tmp, 1); 4576 /* c83 = CEILING(C11/c49, 1)*/ 4577 tmp = mmu_params.lossless_traffic_mtu_size_traffic_attr / CELL_SIZE; 4578 mmu_params.lossless_traffic_mtu_size = _ceil_func(tmp, 1); 4579 4580 /* 4581 * Reservations 4582 * moved to earlier place as these are needed by others 4583 */ 4584 /* c70 = c80*4*/ 4585 mmu_params.wrr_reserve = mmu_params.ethernet_mtu * 4; 4586 /* c71 = (31)*2 +7+29*/ 4587 mmu_params.reserved_for_cfap = 98; 4588 /* c72 */ 4589 mmu_params.skidmarker = 7; 4590 /* c73 */ 4591 mmu_params.skidmarker_option = 3; 4592 /* c74 */ 4593 mmu_params.prefetch = 9; 4594 4595 /* 4596 * SW Config Property 4597 */ 4598 /* c14 */ 4599 mmu_params.total_physical_memory_sw_cfg = 4096; 4600 /* c15 = c14-c71 */ 4601 mmu_params.cfapfullsetpoint_sw_cfg = \ 4602 mmu_params.total_physical_memory_sw_cfg - mmu_params.reserved_for_cfap; 4603 /* c16 = c15 */ 4604 mmu_params.total_cell_memory_for_admission_sw_cfg = \ 4605 mmu_params.cfapfullsetpoint_sw_cfg; 4606 4607 /* c17 configurable */ 4608 mmu_params.num_1g_ports_uplink_ports_sw_cfg = uplink_port_1g; 4609 /* c18 configurable */ 4610 mmu_params.num_2p5g_ports_uplink_ports_sw_cfg = uplink_port_2p5g; 4611 /* c19 configurable */ 4612 mmu_params.num_1g_ports_downlink_ports_sw_cfg = downlink_port_1g; 4613 /* c20 configurable */ 4614 mmu_params.num_2p5g_ports_downlink_ports_sw_cfg = downlink_port_2p5g; 4615 /* c21 = SUM(C17:C18) */ 4616 mmu_params.number_of_uplink_ports_sw_cfg = \ 4617 mmu_params.num_1g_ports_uplink_ports_sw_cfg + \ 4618 mmu_params.num_2p5g_ports_uplink_ports_sw_cfg; 4619 /* c22 = SUM(C19:C20)*/ 4620 mmu_params.number_of_downlink_ports_sw_cfg = \ 4621 mmu_params.num_1g_ports_downlink_ports_sw_cfg + \ 4622 mmu_params.num_2p5g_ports_downlink_ports_sw_cfg; 4623 /* c23 lossless */ 4624 if (lossless) { 4625 mmu_params.flow_control_enabled_sw_cfg = 1; 4626 } else { 4627 mmu_params.flow_control_enabled_sw_cfg = 0; 4628 } 4629 /* c24 PFC = 0 */ 4630 mmu_params.flow_control_type_sw_cfg = 0; 4631 /* c25 = 0.25, not used */ 4632 /* mmu_params.queue_port_limit_ratio_sw_cfg = 0.25; */ 4633 4634 /* 4635 * Device Attributes 4636 * moved to earlier place as these are needed by others 4637 */ 4638 /* c49 */ 4639 mmu_params.cell_size = CELL_SIZE; 4640 /* c50 */ 4641 mmu_params.num_egress_queues_per_port = 4; 4642 /* c51 */ 4643 mmu_params.num_cpu_queues = 8; 4644 /* c52 = c17*/ 4645 mmu_params.num_1g_ports_uplink_ports = \ 4646 mmu_params.num_1g_ports_uplink_ports_sw_cfg; 4647 /* c53 = c18 */ 4648 mmu_params.num_2p5g_ports_uplink_ports = \ 4649 mmu_params.num_2p5g_ports_uplink_ports_sw_cfg; 4650 /* c54 = c19 */ 4651 mmu_params.num_1g_ports_downlink_ports = \ 4652 mmu_params.num_1g_ports_downlink_ports_sw_cfg; 4653 /* c55 = c20 */ 4654 mmu_params.num_2p5g_ports_downlink_ports = \ 4655 mmu_params.num_2p5g_ports_downlink_ports_sw_cfg; 4656 /* c56 */ 4657 mmu_params.num_cpu_ports = 1; 4658 /* c57 = c21*/ 4659 mmu_params.number_of_uplink_ports = \ 4660 mmu_params.number_of_uplink_ports_sw_cfg; 4661 /* c58 = c22 */ 4662 mmu_params.number_of_downlink_ports = \ 4663 mmu_params.number_of_downlink_ports_sw_cfg; 4664 /* c59 = c14 */ 4665 mmu_params.total_physical_memory = \ 4666 mmu_params.total_physical_memory_sw_cfg; 4667 /* c60 = c16 */ 4668 mmu_params.total_cell_memory = \ 4669 mmu_params.total_cell_memory_for_admission_sw_cfg; 4670 /* c61 = c60 */ 4671 mmu_params.total_advertised_cell_memory = \ 4672 mmu_params.total_cell_memory; 4673 /* c62 */ 4674 mmu_params.numxq_per_uplink_ports = 512; 4675 /* c63 */ 4676 mmu_params.numxq_per_downlink_ports_and_cpu_port = 512; 4677 /* c64 */ 4678 mmu_params.the_number_of_pipelines_per_device = 1; 4679 /* c66 */ 4680 mmu_params.n_egress_queues_active_per_xpe = 1; 4681 /* c67 */ 4682 mmu_params.n_ingress_ports_active_per_xpe = 1; 4683 4684 /* 4685 * SW Config Parameter : may different from lossy to lossless 4686 */ 4687 if (lossless) { 4688 /* c29 */ 4689 mmu_params.egress_queue_min_reserve_uplink_ports_lossy = 0; 4690 /* c30 */ 4691 mmu_params.egress_queue_min_reserve_downlink_ports_lossy = 0; 4692 /* c31 */ 4693 mmu_params.egress_queue_min_reserve_uplink_ports_lossless = 12; 4694 /* c32 */ 4695 mmu_params.egress_queue_min_reserve_downlink_ports_lossless = 12; 4696 } else { 4697 /* c29 = c80 */ 4698 mmu_params.egress_queue_min_reserve_uplink_ports_lossy = \ 4699 mmu_params.ethernet_mtu; 4700 /* c30 = c80 */ 4701 mmu_params.egress_queue_min_reserve_downlink_ports_lossy = \ 4702 mmu_params.ethernet_mtu; 4703 /* c31 */ 4704 mmu_params.egress_queue_min_reserve_uplink_ports_lossless = 0; 4705 /* c32 */ 4706 mmu_params.egress_queue_min_reserve_downlink_ports_lossless = 0; 4707 } 4708 /* c33 = c80 */ 4709 mmu_params.egress_queue_min_reserve_cpu_ports = \ 4710 mmu_params.ethernet_mtu; 4711 if (lossless) { 4712 /* c34 */ 4713 mmu_params.egress_xq_min_reserve_lossy_uplink_and_downlink_ports = 0; 4714 /* c35 */ 4715 mmu_params.egress_xq_min_reserve_lossless_uplink_ports = 12; 4716 /* c36 */ 4717 mmu_params.egress_xq_min_reserve_lossless_downlink_ports = 12; 4718 } else { 4719 /* c34 = c80 */ 4720 mmu_params.egress_xq_min_reserve_lossy_uplink_and_downlink_ports = \ 4721 mmu_params.ethernet_mtu; 4722 /* c35 */ 4723 mmu_params.egress_xq_min_reserve_lossless_uplink_ports = 0; 4724 /* c36 */ 4725 mmu_params.egress_xq_min_reserve_lossless_downlink_ports = 0; 4726 } 4727 /* c37 */ 4728 mmu_params.num_total_pri_groups = 4; 4729 if (lossless) { 4730 /* c38 */ 4731 mmu_params.num_active_pri_group_lossless = 1; 4732 /* c39 */ 4733 mmu_params.num_lossless_queues = 4; 4734 /* c40 */ 4735 mmu_params.num_lossy_queues = 0; 4736 /* c41 = c61 */ 4737 mmu_params.mmu_xoff_pkt_threshold_uplink_ports = 12; 4738 /* c42 = c61 */ 4739 mmu_params.mmu_xoff_pkt_threshold_downlink_ports = 12; 4740 /* c43 = c61 */ 4741 mmu_params.mmu_xoff_cell_threshold_1g_port_uplink_ports = 36; 4742 /* c44 = c61 */ 4743 mmu_params.mmu_xoff_cell_threshold_2p5g_port_uplink_ports = 36; 4744 /* c45 = c61 */ 4745 mmu_params.mmu_xoff_cell_threshold_1g_downlink_ports = 36; 4746 /* c46 = c61 */ 4747 mmu_params.mmu_xoff_cell_threshold_2p5g_downlink_ports = 36; 4748 } else { 4749 /* c38 */ 4750 mmu_params.num_active_pri_group_lossless = 0; 4751 /* c39 */ 4752 mmu_params.num_lossless_queues = 0; 4753 /* c40 */ 4754 mmu_params.num_lossy_queues = 4; 4755 /* c41 = c61 */ 4756 mmu_params.mmu_xoff_pkt_threshold_uplink_ports = \ 4757 mmu_params.total_advertised_cell_memory; 4758 /* c42 = c61 */ 4759 mmu_params.mmu_xoff_pkt_threshold_downlink_ports = \ 4760 mmu_params.total_advertised_cell_memory; 4761 /* c43 = c61 */ 4762 mmu_params.mmu_xoff_cell_threshold_1g_port_uplink_ports = \ 4763 mmu_params.total_advertised_cell_memory; 4764 /* c44 = c61 */ 4765 mmu_params.mmu_xoff_cell_threshold_2p5g_port_uplink_ports = \ 4766 mmu_params.total_advertised_cell_memory; 4767 /* c45 = c61 */ 4768 mmu_params.mmu_xoff_cell_threshold_1g_downlink_ports = \ 4769 mmu_params.total_advertised_cell_memory; 4770 /* c46 = c61 */ 4771 mmu_params.mmu_xoff_cell_threshold_2p5g_downlink_ports = \ 4772 mmu_params.total_advertised_cell_memory; 4773 } 4774 4775 /* 4776 * Ingress Thresholds : may different from lossy to lossless 4777 */ 4778 if (lossless) { 4779 /* c85 */ 4780 mmu_params.headroom_for_1g_port = 36; 4781 /* c86 */ 4782 mmu_params.headroom_for_2p5g_port = 36; 4783 } else { 4784 /* c85 */ 4785 mmu_params.headroom_for_1g_port = 0; 4786 /* c86 */ 4787 mmu_params.headroom_for_2p5g_port = 0; 4788 } 4789 /* c87 = c45 */ 4790 mmu_params.xoff_cell_thresholds_per_port_pg_1g_port_downlink_ports = \ 4791 mmu_params.mmu_xoff_cell_threshold_1g_downlink_ports; 4792 /* c88 = c46 */ 4793 mmu_params.xoff_cell_thresholds_per_port_pg_2p5g_port_downlink_ports = \ 4794 mmu_params.mmu_xoff_cell_threshold_2p5g_downlink_ports; 4795 /* c89 = c43 */ 4796 mmu_params.xoff_cell_threshold_1g_uplink_ports = \ 4797 mmu_params.mmu_xoff_cell_threshold_1g_port_uplink_ports; 4798 /* c90 = c44 */ 4799 mmu_params.xoff_cell_threshold_2p5g_uplink_ports = \ 4800 mmu_params.mmu_xoff_cell_threshold_2p5g_port_uplink_ports; 4801 /* c91 = c41 */ 4802 mmu_params.xoff_packet_thresholds_per_port_uplink_port = \ 4803 mmu_params.mmu_xoff_pkt_threshold_uplink_ports; 4804 /* c92 = c42 */ 4805 mmu_params.xoff_packet_thresholds_per_port_downlink_port = \ 4806 mmu_params.mmu_xoff_pkt_threshold_downlink_ports; 4807 if (lossless) { 4808 /* c93 = c61 */ 4809 mmu_params.discard_limit_per_port_pg_downlink_1g_port = \ 4810 mmu_params.total_advertised_cell_memory; 4811 /* c94 = c61 */ 4812 mmu_params.discard_limit_per_port_pg_downlink_2p5g_port = \ 4813 mmu_params.total_advertised_cell_memory; 4814 } else { 4815 /* c93 = c87+c85 */ 4816 mmu_params.discard_limit_per_port_pg_downlink_1g_port = \ 4817 mmu_params.xoff_cell_thresholds_per_port_pg_1g_port_downlink_ports + \ 4818 mmu_params.headroom_for_1g_port; 4819 /* c94 = c88+c86 */ 4820 mmu_params.discard_limit_per_port_pg_downlink_2p5g_port = \ 4821 mmu_params.xoff_cell_thresholds_per_port_pg_2p5g_port_downlink_ports + \ 4822 mmu_params.headroom_for_lossless_downlink_port; 4823 } 4824 /* c95 = c61 */ 4825 mmu_params.discard_limit_per_port_pg_uplink_port = \ 4826 mmu_params.total_advertised_cell_memory; 4827 4828 /* 4829 * Egress Thresholds 4830 */ 4831 /* c97 = c29*c57*c40+c57*c31*c39 */ 4832 mmu_params.total_reserved_cells_for_uplink_ports = \ 4833 (mmu_params.egress_queue_min_reserve_uplink_ports_lossy * \ 4834 mmu_params.number_of_uplink_ports * \ 4835 mmu_params.num_lossy_queues) + \ 4836 (mmu_params.number_of_uplink_ports * \ 4837 mmu_params.egress_queue_min_reserve_uplink_ports_lossless * \ 4838 mmu_params.num_lossless_queues); 4839 /* c98 = c58*c30*(c40)+c58*c32*c39 */ 4840 mmu_params.total_reserved_cells_for_downlink_ports = \ 4841 (mmu_params.number_of_downlink_ports * \ 4842 mmu_params.egress_queue_min_reserve_downlink_ports_lossy * \ 4843 mmu_params.num_lossy_queues) + \ 4844 (mmu_params.number_of_downlink_ports * \ 4845 mmu_params.egress_queue_min_reserve_downlink_ports_lossless * \ 4846 mmu_params.num_lossless_queues); 4847 /* c99 = c56*c33*c51 */ 4848 mmu_params.total_reserved_cells_for_cpu_port = \ 4849 mmu_params.num_cpu_ports * \ 4850 mmu_params.egress_queue_min_reserve_cpu_ports * \ 4851 mmu_params.num_cpu_queues; 4852 /* c100 = SUM(c97:c99) */ 4853 mmu_params.total_reserved = \ 4854 mmu_params.total_reserved_cells_for_uplink_ports + \ 4855 mmu_params.total_reserved_cells_for_downlink_ports + \ 4856 mmu_params.total_reserved_cells_for_cpu_port; 4857 /* c101 = c61-c100 */ 4858 mmu_params.shared_space_cells = \ 4859 mmu_params.total_advertised_cell_memory - \ 4860 mmu_params.total_reserved; 4861 /* c102 = c34*c40+c35*c39 */ 4862 mmu_params.reserved_xqs_per_uplink_port = \ 4863 (mmu_params.egress_xq_min_reserve_lossy_uplink_and_downlink_ports * \ 4864 mmu_params.num_lossy_queues) + \ 4865 (mmu_params.egress_xq_min_reserve_lossless_uplink_ports * \ 4866 mmu_params.num_lossless_queues); 4867 /* c103 = c62-c102 */ 4868 mmu_params.shared_xqs_per_uplink_port = \ 4869 mmu_params.numxq_per_uplink_ports - \ 4870 mmu_params.reserved_xqs_per_uplink_port; 4871 /* c104 = c34*c40+c36*c39 */ 4872 mmu_params.reserved_xqs_per_downlink_port = \ 4873 (mmu_params.egress_xq_min_reserve_lossy_uplink_and_downlink_ports * \ 4874 mmu_params.num_lossy_queues) + \ 4875 (mmu_params.egress_xq_min_reserve_lossless_downlink_ports * \ 4876 mmu_params.num_lossless_queues); 4877 /* c105 = c63-c104 */ 4878 mmu_params.shared_xqs_per_downlink_port = \ 4879 mmu_params.numxq_per_downlink_ports_and_cpu_port - \ 4880 mmu_params.reserved_xqs_per_downlink_port; 4881 /* c106 = c33 * c51 */ 4882 mmu_params.reserved_xqs_at_cpu_port = \ 4883 mmu_params.egress_queue_min_reserve_cpu_ports * \ 4884 mmu_params.num_cpu_queues; 4885 /* c107 = c63 - c106 */ 4886 mmu_params.shared_xqs_at_cpu_port = \ 4887 mmu_params.numxq_per_downlink_ports_and_cpu_port - \ 4888 mmu_params.reserved_xqs_at_cpu_port; 4889 4890 /* Program MMU settings */ 4891 SOC_IF_ERROR_RETURN( 4892 soc_wolfhound2_mmu_lossy_or_lossless_config_helper(unit, lossless)); 4893 4894 return SOC_E_NONE; 4895 } 4896 4897 STATIC int 4898 soc_wolfhound2_mmu_8_cosq_config_helper(int unit, int lossless) 4899 { 4900 uint32 val = 0; 4901 uint32 fld_val = 0; 4902 uint32 tmp = 0; 4903 int port; /* logical port id */ 4904 int pport; /* physical port id */ 4905 int speed; 4906 int cos; 4907 int i; 4908 uint32 ibppktsetlimit_pktsetlimit; 4909 uint32 ibppktsetlimit_resetlimitsel; 4910 uint32 mmu_fc_rx_en_mmu_fc_rx_enable; 4911 uint32 mmu_fc_tx_en_mmu_fc_tx_enable; 4912 uint32 pgcelllimit_0_2__cellsetlimit; 4913 uint32 pgcelllimit_3__cellsetlimit; 4914 uint32 pgcelllimit_4_6__cellsetlimit; 4915 uint32 pgcelllimit_7__cellsetlimit; 4916 uint32 pgcelllimit_0_2__cellresetlimit; 4917 uint32 pgcelllimit_3__cellresetlimit; 4918 uint32 pgcelllimit_4_6__cellresetlimit; 4919 uint32 pgcelllimit_7__cellresetlimit; 4920 uint32 pgdiscardsetlimit_0_2__discardsetlimit; 4921 uint32 pgdiscardsetlimit_3__discardsetlimit; 4922 uint32 pgdiscardsetlimit_4_6__discardsetlimit; 4923 uint32 pgdiscardsetlimit_7__discardsetlimit; 4924 uint32 holcosminxqcnt_0_2__holcosminxqcnt; 4925 uint32 holcosminxqcnt_3__holcosminxqcnt; 4926 uint32 holcosminxqcnt_4_7__holcosminxqcnt; 4927 uint32 holcospktsetlimit_0_2__pktsetlimit; 4928 uint32 holcospktsetlimit_3__pktsetlimit; 4929 uint32 holcospktsetlimit_4_7__pktsetlimit; 4930 uint32 holcospktresetlimit_0_2__pktresetlimit; 4931 uint32 holcospktresetlimit_3__pktresetlimit; 4932 uint32 holcospktresetlimit_4_7__pktresetlimit; 4933 uint32 cngcospktlimit0_0_7__cngpktsetlimit0; 4934 uint32 cngcospktlimit1_0_7__cngpktsetlimit1; 4935 uint32 cngportpktlimit0_cngportpktlimit0; 4936 uint32 cngportpktlimit1_cngportpktlimit1; 4937 uint32 dynxqcntport_dynxqcntport; 4938 uint32 dynresetlimport_dynresetlimport; 4939 uint32 lwmcoscellsetlimit_0_2__cellsetlimit; 4940 uint32 lwmcoscellsetlimit_3__cellsetlimit; 4941 uint32 lwmcoscellsetlimit_4_7__cellsetlimit; 4942 uint32 lwmcoscellsetlimit_0_2__cellresetlimit; 4943 uint32 lwmcoscellsetlimit_3__cellresetlimit; 4944 uint32 lwmcoscellsetlimit_4_7__cellresetlimit; 4945 uint32 holcoscellmaxlimit_0_2__cellmaxlimit; 4946 uint32 holcoscellmaxlimit_3__cellmaxlimit; 4947 uint32 holcoscellmaxlimit_4_7__cellmaxlimit; 4948 uint32 holcoscellmaxlimit_0_2__cellmaxresumelimit; 4949 uint32 holcoscellmaxlimit_3__cellmaxresumelimit; 4950 uint32 holcoscellmaxlimit_4_7__cellmaxresumelimit; 4951 uint32 dyncelllimit_dyncellsetlimit; 4952 uint32 dyncelllimit_dyncellresetlimit; 4953 uint32 color_drop_en_color_drop_en; 4954 uint32 shared_pool_ctrl_dynamic_cos_drop_en; 4955 uint32 shared_pool_ctrl_shared_pool_discard_en; 4956 uint32 shared_pool_ctrl_sharded_pool_xoff_en; 4957 4958 SOC_IF_ERROR_RETURN(READ_CFAPFULLTHRESHOLDr(unit, &val)); 4959 /* i6 = c15 */ 4960 soc_reg_field_set(unit, CFAPFULLTHRESHOLDr, &val, 4961 CFAPFULLSETPOINTf, 4962 mmu_params.cfapfullsetpoint_sw_cfg); 4963 /* i7 = i6 - c82 */ 4964 soc_reg_field_set(unit, CFAPFULLTHRESHOLDr, &val, 4965 CFAPFULLRESETPOINTf, 4966 mmu_params.cfapfullsetpoint_sw_cfg - \ 4967 mmu_params.standard_jumbo_frame); 4968 SOC_IF_ERROR_RETURN(WRITE_CFAPFULLTHRESHOLDr(unit, val)); 4969 4970 /* i10 = c16 */ 4971 SOC_IF_ERROR_RETURN(READ_GBLLIMITSETLIMITr(unit, &val)); 4972 soc_reg_field_set(unit, GBLLIMITSETLIMITr, &val, 4973 GBLCELLSETLIMITf, 4974 mmu_params.total_cell_memory_for_admission_sw_cfg); 4975 SOC_IF_ERROR_RETURN(WRITE_GBLLIMITSETLIMITr(unit, val)); 4976 4977 /* i11 = i10 */ 4978 SOC_IF_ERROR_RETURN(READ_GBLLIMITRESETLIMITr(unit, &val)); 4979 soc_reg_field_set(unit, GBLLIMITRESETLIMITr, &val, 4980 GBLCELLRESETLIMITf, 4981 mmu_params.total_cell_memory_for_admission_sw_cfg); 4982 SOC_IF_ERROR_RETURN(WRITE_GBLLIMITRESETLIMITr(unit, val)); 4983 4984 /* Device Wide - Egress Thresholds */ 4985 val = 0; 4986 /* i15 = c101 */ 4987 soc_reg_field_set(unit, TOTALDYNCELLSETLIMITr, 4988 &val, TOTALDYNCELLSETLIMITf, 4989 mmu_params.shared_space_cells); 4990 SOC_IF_ERROR_RETURN(WRITE_TOTALDYNCELLSETLIMITr(unit, val)); 4991 val = 0; 4992 /* i16 =i15-c82*2*/ 4993 soc_reg_field_set(unit, TOTALDYNCELLRESETLIMITr, 4994 &val, TOTALDYNCELLRESETLIMITf, 4995 mmu_params.shared_space_cells - \ 4996 (mmu_params.standard_jumbo_frame * 2)); 4997 SOC_IF_ERROR_RETURN(WRITE_TOTALDYNCELLRESETLIMITr(unit, val)); 4998 4999 /* MICCONFIGr */ 5000 SOC_IF_ERROR_RETURN(READ_MISCCONFIGr(unit, &val)); 5001 soc_reg_field_set(unit, MISCCONFIGr, &val, MULTIPLE_ACCOUNTING_FIX_ENf, 1); 5002 soc_reg_field_set(unit, MISCCONFIGr, &val, CNG_DROP_ENf, 0); 5003 soc_reg_field_set(unit, MISCCONFIGr, &val, DYN_XQ_ENf, 1); 5004 soc_reg_field_set(unit, MISCCONFIGr, &val, HOL_CELL_SOP_DROP_ENf, 1); 5005 soc_reg_field_set(unit, MISCCONFIGr, &val, DYNAMIC_MEMORY_ENf, 1); 5006 soc_reg_field_set(unit, MISCCONFIGr, &val, SKIDMARKERf, 3); 5007 SOC_IF_ERROR_RETURN(WRITE_MISCCONFIGr(unit, val)); 5008 5009 PBMP_ALL_ITER(unit, port) { 5010 pport = SOC_INFO(unit).port_l2p_mapping[port]; 5011 speed = SOC_INFO(unit).port_speed_max[port]; 5012 5013 val = 0; 5014 if (IS_CPU_PORT(unit, port)) { 5015 soc_reg_field_set(unit, PG_CTRL0r, &val, PPFC_PG_ENf, 0); 5016 } else { 5017 if (lossless) { 5018 soc_reg_field_set(unit, PG_CTRL0r, &val, PPFC_PG_ENf, 0x80); 5019 } else { 5020 soc_reg_field_set(unit, PG_CTRL0r, &val, PPFC_PG_ENf, 0); 5021 } 5022 } 5023 soc_reg_field_set(unit, PG_CTRL0r, &val, PRI0_GRPf, 7); 5024 soc_reg_field_set(unit, PG_CTRL0r, &val, PRI1_GRPf, 7); 5025 soc_reg_field_set(unit, PG_CTRL0r, &val, PRI2_GRPf, 7); 5026 soc_reg_field_set(unit, PG_CTRL0r, &val, PRI3_GRPf, 7); 5027 soc_reg_field_set(unit, PG_CTRL0r, &val, PRI4_GRPf, 7); 5028 soc_reg_field_set(unit, PG_CTRL0r, &val, PRI5_GRPf, 7); 5029 soc_reg_field_set(unit, PG_CTRL0r, &val, PRI6_GRPf, 7); 5030 soc_reg_field_set(unit, PG_CTRL0r, &val, PRI7_GRPf, 7); 5031 SOC_IF_ERROR_RETURN(WRITE_PG_CTRL0r(unit, port, val)); 5032 val = 0; 5033 soc_reg_field_set(unit, PG_CTRL1r, &val, PRI8_GRPf, 7); 5034 soc_reg_field_set(unit, PG_CTRL1r, &val, PRI9_GRPf, 7); 5035 soc_reg_field_set(unit, PG_CTRL1r, &val, PRI10_GRPf, 7); 5036 soc_reg_field_set(unit, PG_CTRL1r, &val, PRI11_GRPf, 7); 5037 soc_reg_field_set(unit, PG_CTRL1r, &val, PRI12_GRPf, 7); 5038 soc_reg_field_set(unit, PG_CTRL1r, &val, PRI13_GRPf, 7); 5039 soc_reg_field_set(unit, PG_CTRL1r, &val, PRI14_GRPf, 7); 5040 soc_reg_field_set(unit, PG_CTRL1r, &val, PRI15_GRPf, 7); 5041 SOC_IF_ERROR_RETURN(WRITE_PG_CTRL1r(unit, port, val)); 5042 val = 0; 5043 soc_reg_field_set(unit, PG2TCr, &val, PG_BMPf, 0); 5044 for (i = 0; i < 8; i++) { 5045 SOC_IF_ERROR_RETURN(WRITE_PG2TCr(unit, port, i, val)); 5046 } 5047 5048 /* Settings based on port type */ 5049 if (IS_CPU_PORT(unit, port)) { 5050 ibppktsetlimit_pktsetlimit = \ 5051 mmu_params.\ 5052 xoff_packet_thresholds_per_port_downlink_port; /* c92 */ 5053 ibppktsetlimit_resetlimitsel = 3; 5054 mmu_fc_rx_en_mmu_fc_rx_enable = 0; 5055 mmu_fc_tx_en_mmu_fc_tx_enable = 0; 5056 /* c93 */ 5057 pgcelllimit_0_2__cellsetlimit = \ 5058 mmu_params.discard_limit_per_port_pg_downlink_1g_port; 5059 /* c93 */ 5060 pgcelllimit_3__cellsetlimit = \ 5061 mmu_params.discard_limit_per_port_pg_downlink_1g_port; 5062 /* c93 */ 5063 pgcelllimit_4_6__cellsetlimit = \ 5064 mmu_params.discard_limit_per_port_pg_downlink_1g_port; 5065 /* c87 */ 5066 pgcelllimit_7__cellsetlimit = \ 5067 mmu_params.\ 5068 xoff_cell_thresholds_per_port_pg_1g_port_downlink_ports; 5069 /* c93 */ 5070 pgcelllimit_0_2__cellresetlimit = \ 5071 mmu_params.discard_limit_per_port_pg_downlink_1g_port; 5072 /* c93 */ 5073 pgcelllimit_3__cellresetlimit = \ 5074 mmu_params.discard_limit_per_port_pg_downlink_1g_port; 5075 /* c93 */ 5076 pgcelllimit_4_6__cellresetlimit = \ 5077 mmu_params.discard_limit_per_port_pg_downlink_1g_port; 5078 /* c87 */ 5079 pgcelllimit_7__cellresetlimit = \ 5080 mmu_params.\ 5081 xoff_cell_thresholds_per_port_pg_1g_port_downlink_ports; 5082 pgdiscardsetlimit_0_2__discardsetlimit = \ 5083 mmu_params.discard_limit_per_port_pg_downlink_1g_port; /* c93 */ 5084 pgdiscardsetlimit_3__discardsetlimit = \ 5085 mmu_params.discard_limit_per_port_pg_downlink_1g_port; /* c93 */ 5086 pgdiscardsetlimit_4_6__discardsetlimit = \ 5087 mmu_params.discard_limit_per_port_pg_downlink_1g_port; /* c93 */ 5088 pgdiscardsetlimit_7__discardsetlimit = \ 5089 mmu_params.discard_limit_per_port_pg_downlink_1g_port; /* c93 */ 5090 5091 holcosminxqcnt_0_2__holcosminxqcnt = \ 5092 mmu_params.egress_queue_min_reserve_cpu_ports; /* c33 */ 5093 holcosminxqcnt_3__holcosminxqcnt = \ 5094 mmu_params.egress_queue_min_reserve_cpu_ports; /* c33 */ 5095 holcosminxqcnt_4_7__holcosminxqcnt = \ 5096 mmu_params.egress_queue_min_reserve_cpu_ports; /* c33 */ 5097 holcospktsetlimit_0_2__pktsetlimit = \ 5098 mmu_params.shared_xqs_at_cpu_port - \ 5099 mmu_params.skidmarker - \ 5100 mmu_params.prefetch + \ 5101 holcosminxqcnt_0_2__holcosminxqcnt; /* C107-C72-C74+Q70 */ 5102 holcospktsetlimit_3__pktsetlimit = \ 5103 mmu_params.shared_xqs_at_cpu_port - \ 5104 mmu_params.skidmarker - \ 5105 mmu_params.prefetch + \ 5106 holcosminxqcnt_3__holcosminxqcnt; /* C107-C72-C74+Q71 */ 5107 holcospktsetlimit_4_7__pktsetlimit = \ 5108 mmu_params.shared_xqs_at_cpu_port - \ 5109 mmu_params.skidmarker - \ 5110 mmu_params.prefetch + \ 5111 holcosminxqcnt_4_7__holcosminxqcnt; /* C107-C72-C74+Q72 */ 5112 holcospktresetlimit_0_2__pktresetlimit = \ 5113 holcospktsetlimit_0_2__pktsetlimit - 1; /* q73 - 1 */ 5114 holcospktresetlimit_3__pktresetlimit = \ 5115 holcospktsetlimit_3__pktsetlimit - 1; /* q74 - 1 */ 5116 holcospktresetlimit_4_7__pktresetlimit = \ 5117 holcospktsetlimit_4_7__pktsetlimit - 1; /* q75 - 1 */ 5118 cngcospktlimit0_0_7__cngpktsetlimit0 = \ 5119 mmu_params.numxq_per_downlink_ports_and_cpu_port - 1; /*c63-1*/ 5120 cngcospktlimit1_0_7__cngpktsetlimit1 = \ 5121 mmu_params.numxq_per_downlink_ports_and_cpu_port - 1; /*c63-1*/ 5122 cngportpktlimit0_cngportpktlimit0 = \ 5123 mmu_params.numxq_per_downlink_ports_and_cpu_port - 1; /*c63-1*/ 5124 cngportpktlimit1_cngportpktlimit1 = \ 5125 mmu_params.numxq_per_downlink_ports_and_cpu_port - 1; /*c63-1*/ 5126 dynxqcntport_dynxqcntport = \ 5127 mmu_params.shared_xqs_at_cpu_port - \ 5128 mmu_params.skidmarker - \ 5129 mmu_params.prefetch; /* c107-c72-c74 */ 5130 dynresetlimport_dynresetlimport = \ 5131 dynxqcntport_dynxqcntport - 2; /* q83 - 2 */ 5132 lwmcoscellsetlimit_0_2__cellsetlimit = \ 5133 mmu_params.egress_queue_min_reserve_cpu_ports; /* c33 */ 5134 lwmcoscellsetlimit_3__cellsetlimit = \ 5135 mmu_params.egress_queue_min_reserve_cpu_ports; /* c33 */ 5136 lwmcoscellsetlimit_4_7__cellsetlimit = \ 5137 mmu_params.egress_queue_min_reserve_cpu_ports; /* c33 */ 5138 lwmcoscellsetlimit_0_2__cellresetlimit = \ 5139 mmu_params.egress_queue_min_reserve_cpu_ports; /* c33 */ 5140 lwmcoscellsetlimit_3__cellresetlimit = \ 5141 mmu_params.egress_queue_min_reserve_cpu_ports; /* c33 */ 5142 lwmcoscellsetlimit_4_7__cellresetlimit = \ 5143 mmu_params.egress_queue_min_reserve_cpu_ports; /* c33 */ 5144 /* CEILING(c101*C25+Q85, 1) */ 5145 tmp = _ceil_func((mmu_params.shared_space_cells * 10 / 4), 10); 5146 holcoscellmaxlimit_0_2__cellmaxlimit = \ 5147 tmp + lwmcoscellsetlimit_0_2__cellsetlimit; 5148 /* CEILING(c101*C25+Q86, 1) */ 5149 tmp = _ceil_func((mmu_params.shared_space_cells * 10 / 4), 10); 5150 holcoscellmaxlimit_3__cellmaxlimit = \ 5151 tmp + lwmcoscellsetlimit_3__cellsetlimit; 5152 /* CEILING(c101*C25+Q87, 1) */ 5153 tmp = _ceil_func((mmu_params.shared_space_cells * 10 / 4), 10); 5154 holcoscellmaxlimit_4_7__cellmaxlimit = \ 5155 tmp + lwmcoscellsetlimit_4_7__cellsetlimit; 5156 holcoscellmaxlimit_0_2__cellmaxresumelimit = \ 5157 holcoscellmaxlimit_0_2__cellmaxlimit - \ 5158 mmu_params.ethernet_mtu; /* q91 - c80 */ 5159 holcoscellmaxlimit_3__cellmaxresumelimit = \ 5160 holcoscellmaxlimit_3__cellmaxlimit - \ 5161 mmu_params.ethernet_mtu; /* q92 - c80 */ 5162 holcoscellmaxlimit_4_7__cellmaxresumelimit = \ 5163 holcoscellmaxlimit_4_7__cellmaxlimit - \ 5164 mmu_params.ethernet_mtu; /* q93 - c80 */ 5165 dyncelllimit_dyncellsetlimit = \ 5166 mmu_params.shared_space_cells; /* c101 */ 5167 dyncelllimit_dyncellresetlimit = \ 5168 dyncelllimit_dyncellsetlimit - \ 5169 (mmu_params.ethernet_mtu * 2); /* q97-c80*2 */ 5170 color_drop_en_color_drop_en = 0; 5171 shared_pool_ctrl_dynamic_cos_drop_en = 255; 5172 shared_pool_ctrl_shared_pool_discard_en = 255; 5173 shared_pool_ctrl_sharded_pool_xoff_en = 0; 5174 } else if (pport >= 34) { /* uplink port 1G, 2.5G */ 5175 SOC_IF_ERROR_RETURN(WRITE_PG2TCr(unit, port, 7, 0x80)); 5176 5177 if (speed == 10) { /* 1G */ 5178 /* c95 */ 5179 pgcelllimit_0_2__cellsetlimit = \ 5180 mmu_params.discard_limit_per_port_pg_uplink_port; 5181 /* c95 */ 5182 pgcelllimit_3__cellsetlimit = \ 5183 mmu_params.discard_limit_per_port_pg_uplink_port; 5184 /* c95 */ 5185 pgcelllimit_4_6__cellsetlimit = \ 5186 mmu_params.discard_limit_per_port_pg_uplink_port; 5187 /* c89 */ 5188 pgcelllimit_7__cellsetlimit = \ 5189 mmu_params.\ 5190 xoff_cell_threshold_1g_uplink_ports; 5191 /* c95 */ 5192 pgcelllimit_0_2__cellresetlimit = \ 5193 mmu_params.discard_limit_per_port_pg_uplink_port; 5194 /* c95 */ 5195 pgcelllimit_3__cellresetlimit = \ 5196 mmu_params.discard_limit_per_port_pg_uplink_port; 5197 /* c95 */ 5198 pgcelllimit_4_6__cellresetlimit = \ 5199 mmu_params.discard_limit_per_port_pg_uplink_port; 5200 /* c89 */ 5201 pgcelllimit_7__cellresetlimit = \ 5202 mmu_params.\ 5203 xoff_cell_threshold_1g_uplink_ports; 5204 } else { /* 2.5 G */ 5205 /* c95 */ 5206 pgcelllimit_0_2__cellsetlimit = \ 5207 mmu_params.discard_limit_per_port_pg_uplink_port; 5208 /* c95 */ 5209 pgcelllimit_3__cellsetlimit = \ 5210 mmu_params.discard_limit_per_port_pg_uplink_port; 5211 /* c95 */ 5212 pgcelllimit_4_6__cellsetlimit = \ 5213 mmu_params.discard_limit_per_port_pg_uplink_port; 5214 /* c90 */ 5215 pgcelllimit_7__cellsetlimit = \ 5216 mmu_params.\ 5217 xoff_cell_threshold_2p5g_uplink_ports; 5218 /* c95 */ 5219 pgcelllimit_0_2__cellresetlimit = \ 5220 mmu_params.discard_limit_per_port_pg_uplink_port; 5221 /* c95 */ 5222 pgcelllimit_3__cellresetlimit = \ 5223 mmu_params.discard_limit_per_port_pg_uplink_port; 5224 /* c95 */ 5225 pgcelllimit_4_6__cellresetlimit = \ 5226 mmu_params.discard_limit_per_port_pg_uplink_port; 5227 /* c90 */ 5228 pgcelllimit_7__cellresetlimit = \ 5229 mmu_params.\ 5230 xoff_cell_threshold_2p5g_uplink_ports; 5231 } 5232 /* c91 */ 5233 ibppktsetlimit_pktsetlimit = \ 5234 mmu_params.\ 5235 xoff_packet_thresholds_per_port_uplink_port; 5236 ibppktsetlimit_resetlimitsel = 3; 5237 mmu_fc_rx_en_mmu_fc_rx_enable = 0; 5238 if (lossless) { 5239 mmu_fc_tx_en_mmu_fc_tx_enable = 0x80; 5240 } else { 5241 mmu_fc_tx_en_mmu_fc_tx_enable = 0; 5242 } 5243 /* c95 */ 5244 pgdiscardsetlimit_0_2__discardsetlimit = \ 5245 mmu_params.discard_limit_per_port_pg_uplink_port; 5246 /* c95 */ 5247 pgdiscardsetlimit_3__discardsetlimit = \ 5248 mmu_params.discard_limit_per_port_pg_uplink_port; 5249 /* c95 */ 5250 pgdiscardsetlimit_4_6__discardsetlimit = \ 5251 mmu_params.discard_limit_per_port_pg_uplink_port; 5252 /* c95 */ 5253 pgdiscardsetlimit_7__discardsetlimit = \ 5254 mmu_params.discard_limit_per_port_pg_uplink_port; 5255 5256 /* 0 */ 5257 holcosminxqcnt_0_2__holcosminxqcnt = 0; 5258 /* 0 */ 5259 holcosminxqcnt_3__holcosminxqcnt = 0; 5260 /* c36 */ 5261 holcosminxqcnt_4_7__holcosminxqcnt = \ 5262 mmu_params.egress_xq_min_reserve_lossless_downlink_ports; 5263 /* C103-C72-C74+M70 */ 5264 holcospktsetlimit_0_2__pktsetlimit = \ 5265 mmu_params.shared_xqs_per_uplink_port - \ 5266 mmu_params.skidmarker - \ 5267 mmu_params.prefetch + \ 5268 holcosminxqcnt_0_2__holcosminxqcnt; 5269 /* C103-C72-C74+M71 */ 5270 holcospktsetlimit_3__pktsetlimit = \ 5271 mmu_params.shared_xqs_per_uplink_port - \ 5272 mmu_params.skidmarker - \ 5273 mmu_params.prefetch + \ 5274 holcosminxqcnt_3__holcosminxqcnt; 5275 /* C103-C72-C74+M72 */ 5276 holcospktsetlimit_4_7__pktsetlimit = \ 5277 mmu_params.shared_xqs_per_uplink_port - \ 5278 mmu_params.skidmarker - \ 5279 mmu_params.prefetch + \ 5280 holcosminxqcnt_4_7__holcosminxqcnt; 5281 /* m73 - 1 */ 5282 holcospktresetlimit_0_2__pktresetlimit = \ 5283 holcospktsetlimit_0_2__pktsetlimit - 1; 5284 /* m74 - 1 */ 5285 holcospktresetlimit_3__pktresetlimit = \ 5286 holcospktsetlimit_3__pktsetlimit - 1; 5287 /* m75 - 1 */ 5288 holcospktresetlimit_4_7__pktresetlimit = \ 5289 holcospktsetlimit_4_7__pktsetlimit - 1; 5290 /* c62 - 1 */ 5291 cngcospktlimit0_0_7__cngpktsetlimit0 = \ 5292 mmu_params.numxq_per_uplink_ports - 1; 5293 /* c62 - 1 */ 5294 cngcospktlimit1_0_7__cngpktsetlimit1 = \ 5295 mmu_params.numxq_per_uplink_ports - 1; 5296 /* c62 - 1 */ 5297 cngportpktlimit0_cngportpktlimit0 = \ 5298 mmu_params.numxq_per_uplink_ports - 1; 5299 /* c62 - 1 */ 5300 cngportpktlimit1_cngportpktlimit1 = \ 5301 mmu_params.numxq_per_uplink_ports - 1; 5302 /* c103-c72-c74 */ 5303 dynxqcntport_dynxqcntport = \ 5304 mmu_params.shared_xqs_per_uplink_port - \ 5305 mmu_params.skidmarker - \ 5306 mmu_params.prefetch; 5307 /* m83 - 2 */ 5308 dynresetlimport_dynresetlimport = \ 5309 dynxqcntport_dynxqcntport - 2; 5310 /* 0 */ 5311 lwmcoscellsetlimit_0_2__cellsetlimit = 0; 5312 /* 0 */ 5313 lwmcoscellsetlimit_3__cellsetlimit = 0; 5314 /* c31 */ 5315 lwmcoscellsetlimit_4_7__cellsetlimit = \ 5316 mmu_params.egress_queue_min_reserve_uplink_ports_lossless; 5317 /* 0 */ 5318 lwmcoscellsetlimit_0_2__cellresetlimit = 0; 5319 /* 0 */ 5320 lwmcoscellsetlimit_3__cellresetlimit = 0; 5321 /* c31 */ 5322 lwmcoscellsetlimit_4_7__cellresetlimit = \ 5323 mmu_params.egress_queue_min_reserve_uplink_ports_lossless; 5324 /* CEILING((C87+C85)*C54+(C88+C86)*C55+(C89+C85)*C53+(C90+C86)*C52+I85,1) */ 5325 tmp = (mmu_params.\ 5326 xoff_cell_thresholds_per_port_pg_1g_port_downlink_ports + 5327 mmu_params.headroom_for_1g_port) * \ 5328 mmu_params.num_1g_ports_downlink_ports + \ 5329 (mmu_params.\ 5330 xoff_cell_thresholds_per_port_pg_2p5g_port_downlink_ports + 5331 mmu_params.headroom_for_2p5g_port) * \ 5332 mmu_params.num_2p5g_ports_downlink_ports + \ 5333 (mmu_params.\ 5334 xoff_cell_threshold_1g_uplink_ports + \ 5335 mmu_params.headroom_for_1g_port) * \ 5336 mmu_params.num_2p5g_ports_uplink_ports + \ 5337 (mmu_params.xoff_cell_threshold_2p5g_uplink_ports + \ 5338 mmu_params.headroom_for_2p5g_port) * \ 5339 mmu_params.num_1g_ports_uplink_ports + \ 5340 lwmcoscellsetlimit_0_2__cellsetlimit; 5341 holcoscellmaxlimit_0_2__cellmaxlimit = _ceil_func(tmp, 1); 5342 /* CEILING((C87+C85)*C54+(C88+C86)*C55+(C89+C85)*C53+(C90+C86)*C52+I86, 1) */ 5343 tmp = (mmu_params.\ 5344 xoff_cell_thresholds_per_port_pg_1g_port_downlink_ports + 5345 mmu_params.headroom_for_1g_port) * \ 5346 mmu_params.num_1g_ports_downlink_ports + \ 5347 (mmu_params.\ 5348 xoff_cell_thresholds_per_port_pg_2p5g_port_downlink_ports + 5349 mmu_params.headroom_for_2p5g_port) * \ 5350 mmu_params.num_2p5g_ports_downlink_ports + \ 5351 (mmu_params.\ 5352 xoff_cell_threshold_1g_uplink_ports + \ 5353 mmu_params.headroom_for_1g_port) * \ 5354 mmu_params.num_2p5g_ports_uplink_ports + \ 5355 (mmu_params.xoff_cell_threshold_2p5g_uplink_ports + \ 5356 mmu_params.headroom_for_2p5g_port) * \ 5357 mmu_params.num_1g_ports_uplink_ports + \ 5358 lwmcoscellsetlimit_3__cellsetlimit; 5359 holcoscellmaxlimit_3__cellmaxlimit = _ceil_func(tmp, 1);; 5360 /* CEILING((C87+C85)*C54+(C88+C86)*C55+(C89+C85)*C53+(C90+C86)*C52+I87, 1) */ 5361 tmp = (mmu_params.\ 5362 xoff_cell_thresholds_per_port_pg_1g_port_downlink_ports + 5363 mmu_params.headroom_for_1g_port) * \ 5364 mmu_params.num_1g_ports_downlink_ports + \ 5365 (mmu_params.\ 5366 xoff_cell_thresholds_per_port_pg_2p5g_port_downlink_ports + 5367 mmu_params.headroom_for_2p5g_port) * \ 5368 mmu_params.num_2p5g_ports_downlink_ports + \ 5369 (mmu_params.\ 5370 xoff_cell_threshold_1g_uplink_ports + \ 5371 mmu_params.headroom_for_1g_port) * \ 5372 mmu_params.num_2p5g_ports_uplink_ports + \ 5373 (mmu_params.xoff_cell_threshold_2p5g_uplink_ports + \ 5374 mmu_params.headroom_for_2p5g_port) * \ 5375 mmu_params.num_1g_ports_uplink_ports + \ 5376 lwmcoscellsetlimit_4_7__cellsetlimit; 5377 holcoscellmaxlimit_4_7__cellmaxlimit = _ceil_func(tmp, 1);; 5378 /* o91 - c80 */ 5379 holcoscellmaxlimit_0_2__cellmaxresumelimit = \ 5380 holcoscellmaxlimit_0_2__cellmaxlimit - \ 5381 mmu_params.ethernet_mtu; 5382 /* o92 - c80 */ 5383 holcoscellmaxlimit_3__cellmaxresumelimit = \ 5384 holcoscellmaxlimit_3__cellmaxlimit - \ 5385 mmu_params.ethernet_mtu; 5386 /* o93 - c80 */ 5387 holcoscellmaxlimit_4_7__cellmaxresumelimit = \ 5388 holcoscellmaxlimit_4_7__cellmaxlimit - \ 5389 mmu_params.ethernet_mtu; 5390 /* c101 */ 5391 dyncelllimit_dyncellsetlimit = \ 5392 mmu_params.shared_space_cells; 5393 /* o97-c80*2 */ 5394 dyncelllimit_dyncellresetlimit = \ 5395 dyncelllimit_dyncellsetlimit - \ 5396 (mmu_params.ethernet_mtu * 2); 5397 color_drop_en_color_drop_en = 0; 5398 shared_pool_ctrl_dynamic_cos_drop_en = 255; 5399 shared_pool_ctrl_shared_pool_discard_en = 255; 5400 shared_pool_ctrl_sharded_pool_xoff_en = 0; 5401 } else { /* downlink port 1G, 2.5G */ 5402 SOC_IF_ERROR_RETURN(WRITE_PG2TCr(unit, port, 7, 0x80)); 5403 5404 if (speed == 10) { /* 1G */ 5405 /* c93 */ 5406 pgcelllimit_0_2__cellsetlimit = \ 5407 mmu_params.discard_limit_per_port_pg_downlink_1g_port; 5408 /* c93 */ 5409 pgcelllimit_3__cellsetlimit = \ 5410 mmu_params.discard_limit_per_port_pg_downlink_1g_port; 5411 /* c93 */ 5412 pgcelllimit_4_6__cellsetlimit = \ 5413 mmu_params.discard_limit_per_port_pg_downlink_1g_port; 5414 /* c87 */ 5415 pgcelllimit_7__cellsetlimit = \ 5416 mmu_params.\ 5417 xoff_cell_thresholds_per_port_pg_1g_port_downlink_ports; 5418 /* c93 */ 5419 pgcelllimit_0_2__cellresetlimit = \ 5420 mmu_params.discard_limit_per_port_pg_downlink_1g_port; 5421 /* c93 */ 5422 pgcelllimit_3__cellresetlimit = \ 5423 mmu_params.discard_limit_per_port_pg_downlink_1g_port; 5424 /* c93 */ 5425 pgcelllimit_4_6__cellresetlimit = \ 5426 mmu_params.discard_limit_per_port_pg_downlink_1g_port; 5427 /* c87 */ 5428 pgcelllimit_7__cellresetlimit = \ 5429 mmu_params.\ 5430 xoff_cell_thresholds_per_port_pg_1g_port_downlink_ports; 5431 /* c93 */ 5432 pgdiscardsetlimit_0_2__discardsetlimit = \ 5433 mmu_params.discard_limit_per_port_pg_downlink_1g_port; 5434 /* c93 */ 5435 pgdiscardsetlimit_3__discardsetlimit = \ 5436 mmu_params.discard_limit_per_port_pg_downlink_1g_port; 5437 /* c93 */ 5438 pgdiscardsetlimit_4_6__discardsetlimit = \ 5439 mmu_params.discard_limit_per_port_pg_downlink_1g_port; 5440 /* c93 */ 5441 pgdiscardsetlimit_7__discardsetlimit = \ 5442 mmu_params.discard_limit_per_port_pg_downlink_1g_port; 5443 } else { /* 2.5 G */ 5444 /* c94 */ 5445 pgcelllimit_0_2__cellsetlimit = \ 5446 mmu_params.discard_limit_per_port_pg_downlink_2p5g_port; 5447 /* c94 */ 5448 pgcelllimit_3__cellsetlimit = \ 5449 mmu_params.discard_limit_per_port_pg_downlink_2p5g_port; 5450 /* c94 */ 5451 pgcelllimit_4_6__cellsetlimit = \ 5452 mmu_params.discard_limit_per_port_pg_downlink_2p5g_port; 5453 /* c88 */ 5454 pgcelllimit_7__cellsetlimit = \ 5455 mmu_params.\ 5456 xoff_cell_thresholds_per_port_pg_2p5g_port_downlink_ports; 5457 /* c94 */ 5458 pgcelllimit_0_2__cellresetlimit = \ 5459 mmu_params.discard_limit_per_port_pg_downlink_2p5g_port; 5460 /* c94 */ 5461 pgcelllimit_3__cellresetlimit = \ 5462 mmu_params.discard_limit_per_port_pg_downlink_2p5g_port; 5463 /* c94 */ 5464 pgcelllimit_4_6__cellresetlimit = \ 5465 mmu_params.discard_limit_per_port_pg_downlink_2p5g_port; 5466 /* c88 */ 5467 pgcelllimit_7__cellresetlimit = \ 5468 mmu_params.\ 5469 xoff_cell_thresholds_per_port_pg_2p5g_port_downlink_ports; 5470 /* c94 */ 5471 pgdiscardsetlimit_0_2__discardsetlimit = \ 5472 mmu_params.discard_limit_per_port_pg_downlink_2p5g_port; 5473 /* c94 */ 5474 pgdiscardsetlimit_3__discardsetlimit = \ 5475 mmu_params.discard_limit_per_port_pg_downlink_2p5g_port; 5476 /* c94 */ 5477 pgdiscardsetlimit_4_6__discardsetlimit = \ 5478 mmu_params.discard_limit_per_port_pg_downlink_2p5g_port; 5479 /* c94 */ 5480 pgdiscardsetlimit_7__discardsetlimit = \ 5481 mmu_params.discard_limit_per_port_pg_downlink_2p5g_port; 5482 } 5483 /* c92 */ 5484 ibppktsetlimit_pktsetlimit = \ 5485 mmu_params.\ 5486 xoff_packet_thresholds_per_port_downlink_port; 5487 ibppktsetlimit_resetlimitsel = 3; 5488 mmu_fc_rx_en_mmu_fc_rx_enable = 0; 5489 if (lossless) { 5490 mmu_fc_tx_en_mmu_fc_tx_enable = 0x80; 5491 } else { 5492 mmu_fc_tx_en_mmu_fc_tx_enable = 0; 5493 } 5494 5495 /* 0 */ 5496 holcosminxqcnt_0_2__holcosminxqcnt = 0; 5497 /* 0 */ 5498 holcosminxqcnt_3__holcosminxqcnt = 0; 5499 /* c35 */ 5500 holcosminxqcnt_4_7__holcosminxqcnt = \ 5501 mmu_params.egress_xq_min_reserve_lossless_uplink_ports; 5502 /* C105-C72-C74+I70 */ 5503 holcospktsetlimit_0_2__pktsetlimit = \ 5504 mmu_params.shared_xqs_per_downlink_port - \ 5505 mmu_params.skidmarker - \ 5506 mmu_params.prefetch + \ 5507 holcosminxqcnt_0_2__holcosminxqcnt; 5508 /* C105-C72-C74+I71 */ 5509 holcospktsetlimit_3__pktsetlimit = \ 5510 mmu_params.shared_xqs_per_downlink_port - \ 5511 mmu_params.skidmarker - \ 5512 mmu_params.prefetch + \ 5513 holcosminxqcnt_3__holcosminxqcnt; 5514 /* C105-C72-C74+I72 */ 5515 holcospktsetlimit_4_7__pktsetlimit = \ 5516 mmu_params.shared_xqs_per_downlink_port - \ 5517 mmu_params.skidmarker - \ 5518 mmu_params.prefetch + \ 5519 holcosminxqcnt_4_7__holcosminxqcnt; 5520 /* I73 -1 */ 5521 holcospktresetlimit_0_2__pktresetlimit = \ 5522 holcospktsetlimit_0_2__pktsetlimit - 1; 5523 /* I74 -1 */ 5524 holcospktresetlimit_3__pktresetlimit = \ 5525 holcospktsetlimit_3__pktsetlimit - 1; 5526 /* I75 -1 */ 5527 holcospktresetlimit_4_7__pktresetlimit = \ 5528 holcospktsetlimit_4_7__pktsetlimit - 1; 5529 /* c63 - 1 */ 5530 cngcospktlimit0_0_7__cngpktsetlimit0 = \ 5531 mmu_params.numxq_per_downlink_ports_and_cpu_port - 1; 5532 /* c63 - 1 */ 5533 cngcospktlimit1_0_7__cngpktsetlimit1 = \ 5534 mmu_params.numxq_per_downlink_ports_and_cpu_port - 1; 5535 /* c63 - 1 */ 5536 cngportpktlimit0_cngportpktlimit0 = \ 5537 mmu_params.numxq_per_downlink_ports_and_cpu_port - 1; 5538 /* c63 - 1 */ 5539 cngportpktlimit1_cngportpktlimit1 = \ 5540 mmu_params.numxq_per_downlink_ports_and_cpu_port - 1; 5541 /* c105-c72-c74 */ 5542 dynxqcntport_dynxqcntport = \ 5543 mmu_params.shared_xqs_per_downlink_port - \ 5544 mmu_params.skidmarker - \ 5545 mmu_params.prefetch; 5546 /* I83-2 */ 5547 dynresetlimport_dynresetlimport = \ 5548 dynxqcntport_dynxqcntport - 2; 5549 /* 0 */ 5550 lwmcoscellsetlimit_0_2__cellsetlimit = 0; 5551 /* 0 */ 5552 lwmcoscellsetlimit_3__cellsetlimit = 0; 5553 /* c32 */ 5554 lwmcoscellsetlimit_4_7__cellsetlimit = \ 5555 mmu_params.egress_queue_min_reserve_downlink_ports_lossless; 5556 /* 0 */ 5557 lwmcoscellsetlimit_0_2__cellresetlimit = 0; 5558 /* 0 */ 5559 lwmcoscellsetlimit_3__cellresetlimit = 0; 5560 /* c32 */ 5561 lwmcoscellsetlimit_4_7__cellresetlimit = \ 5562 mmu_params.egress_queue_min_reserve_downlink_ports_lossless; 5563 /* CEILING((C87+C85)*C54+(C88+C86)*C55+(C89+C85)*C53+(C90+C86)*C52+I85, 1) */ 5564 tmp = (mmu_params.\ 5565 xoff_cell_thresholds_per_port_pg_1g_port_downlink_ports + 5566 mmu_params.headroom_for_1g_port) * \ 5567 mmu_params.num_1g_ports_downlink_ports + \ 5568 (mmu_params.\ 5569 xoff_cell_thresholds_per_port_pg_2p5g_port_downlink_ports + 5570 mmu_params.headroom_for_2p5g_port) * \ 5571 mmu_params.num_2p5g_ports_downlink_ports + \ 5572 (mmu_params.\ 5573 xoff_cell_threshold_1g_uplink_ports + \ 5574 mmu_params.headroom_for_1g_port) * \ 5575 mmu_params.num_2p5g_ports_uplink_ports + \ 5576 (mmu_params.xoff_cell_threshold_2p5g_uplink_ports + \ 5577 mmu_params.headroom_for_2p5g_port) * \ 5578 mmu_params.num_1g_ports_uplink_ports + \ 5579 lwmcoscellsetlimit_0_2__cellsetlimit; 5580 holcoscellmaxlimit_0_2__cellmaxlimit = _ceil_func(tmp, 1); 5581 /* CEILING((C87+C85)*C54+(C88+C86)*C55+(C89+C85)*C53+(C90+C86)*C52+I86, 1) */ 5582 tmp = (mmu_params.\ 5583 xoff_cell_thresholds_per_port_pg_1g_port_downlink_ports + 5584 mmu_params.headroom_for_1g_port) * \ 5585 mmu_params.num_1g_ports_downlink_ports + \ 5586 (mmu_params.\ 5587 xoff_cell_thresholds_per_port_pg_2p5g_port_downlink_ports + 5588 mmu_params.headroom_for_2p5g_port) * \ 5589 mmu_params.num_2p5g_ports_downlink_ports + \ 5590 (mmu_params.\ 5591 xoff_cell_threshold_1g_uplink_ports + \ 5592 mmu_params.headroom_for_1g_port) * \ 5593 mmu_params.num_2p5g_ports_uplink_ports + \ 5594 (mmu_params.xoff_cell_threshold_2p5g_uplink_ports + \ 5595 mmu_params.headroom_for_2p5g_port) * \ 5596 mmu_params.num_1g_ports_uplink_ports + \ 5597 lwmcoscellsetlimit_3__cellsetlimit; 5598 holcoscellmaxlimit_3__cellmaxlimit = _ceil_func(tmp, 1); 5599 /* CEILING((C87+C85)*C54+(C88+C86)*C55+(C89+C85)*C53+(C90+C86)*C52+I87, 1) */ 5600 tmp = (mmu_params.\ 5601 xoff_cell_thresholds_per_port_pg_1g_port_downlink_ports + 5602 mmu_params.headroom_for_1g_port) * \ 5603 mmu_params.num_1g_ports_downlink_ports + \ 5604 (mmu_params.\ 5605 xoff_cell_thresholds_per_port_pg_2p5g_port_downlink_ports + 5606 mmu_params.headroom_for_2p5g_port) * \ 5607 mmu_params.num_2p5g_ports_downlink_ports + \ 5608 (mmu_params.\ 5609 xoff_cell_threshold_1g_uplink_ports + \ 5610 mmu_params.headroom_for_1g_port) * \ 5611 mmu_params.num_2p5g_ports_uplink_ports + \ 5612 (mmu_params.xoff_cell_threshold_2p5g_uplink_ports + \ 5613 mmu_params.headroom_for_2p5g_port) * \ 5614 mmu_params.num_1g_ports_uplink_ports + \ 5615 lwmcoscellsetlimit_4_7__cellsetlimit; 5616 holcoscellmaxlimit_4_7__cellmaxlimit = _ceil_func(tmp, 1); 5617 /* I91-C80 */ 5618 holcoscellmaxlimit_0_2__cellmaxresumelimit = \ 5619 holcoscellmaxlimit_0_2__cellmaxlimit - \ 5620 mmu_params.ethernet_mtu; 5621 /* I92-C80 */ 5622 holcoscellmaxlimit_3__cellmaxresumelimit = \ 5623 holcoscellmaxlimit_3__cellmaxlimit - \ 5624 mmu_params.ethernet_mtu; 5625 /* I93-C80 */ 5626 holcoscellmaxlimit_4_7__cellmaxresumelimit = \ 5627 holcoscellmaxlimit_4_7__cellmaxlimit - \ 5628 mmu_params.ethernet_mtu; 5629 /* c101 */ 5630 dyncelllimit_dyncellsetlimit = \ 5631 mmu_params.shared_space_cells; 5632 /* o97-c80*2 */ 5633 dyncelllimit_dyncellresetlimit = \ 5634 dyncelllimit_dyncellsetlimit - \ 5635 (mmu_params.ethernet_mtu * 2); 5636 color_drop_en_color_drop_en = 0; 5637 shared_pool_ctrl_dynamic_cos_drop_en = 255; 5638 shared_pool_ctrl_shared_pool_discard_en = 255; 5639 shared_pool_ctrl_sharded_pool_xoff_en = 0; 5640 } 5641 5642 /* Program the setting */ 5643 val = 0; 5644 /* i52 = c92 */ 5645 soc_reg_field_set(unit, IBPPKTSETLIMITr, &val, PKTSETLIMITf, 5646 ibppktsetlimit_pktsetlimit); 5647 soc_reg_field_set(unit, IBPPKTSETLIMITr, &val, RESETLIMITSELf, 5648 ibppktsetlimit_resetlimitsel); 5649 SOC_IF_ERROR_RETURN(WRITE_IBPPKTSETLIMITr(unit, port, val)); 5650 5651 val = 0; 5652 soc_reg_field_set(unit, MMU_FC_RX_ENr, &val, MMU_FC_RX_ENABLEf, 5653 mmu_fc_rx_en_mmu_fc_rx_enable); 5654 SOC_IF_ERROR_RETURN(WRITE_MMU_FC_RX_ENr(unit, port, val)); 5655 val = 0; 5656 soc_reg_field_set(unit, MMU_FC_TX_ENr, &val, MMU_FC_TX_ENABLEf, 5657 mmu_fc_tx_en_mmu_fc_tx_enable); 5658 SOC_IF_ERROR_RETURN(WRITE_MMU_FC_TX_ENr(unit, port, val)); 5659 5660 for (cos = 0; cos < WH2_QUEUE_MAX_NUM; cos++) { 5661 if ((cos >= 0) && (cos <= 2)) { 5662 fld_val = holcospktsetlimit_0_2__pktsetlimit; 5663 } else if (cos == 3) { 5664 fld_val = holcospktsetlimit_3__pktsetlimit; 5665 } else { 5666 fld_val = holcospktsetlimit_4_7__pktsetlimit; 5667 } 5668 SOC_IF_ERROR_RETURN 5669 (READ_HOLCOSPKTSETLIMITr(unit, port, cos, &val)); 5670 soc_reg_field_set(unit, HOLCOSPKTSETLIMITr, &val, 5671 PKTSETLIMITf, fld_val); 5672 SOC_IF_ERROR_RETURN 5673 (WRITE_HOLCOSPKTSETLIMITr(unit, port, cos, val)); 5674 5675 if ((cos >= 0) && (cos <= 2)) { 5676 fld_val = holcospktresetlimit_0_2__pktresetlimit; 5677 } else if (cos == 3) { 5678 fld_val = holcospktresetlimit_3__pktresetlimit; 5679 } else { 5680 fld_val = holcospktresetlimit_4_7__pktresetlimit; 5681 } 5682 SOC_IF_ERROR_RETURN 5683 (READ_HOLCOSPKTRESETLIMITr(unit, port, cos, &val)); 5684 soc_reg_field_set(unit, HOLCOSPKTRESETLIMITr, &val, 5685 PKTRESETLIMITf, fld_val); 5686 SOC_IF_ERROR_RETURN 5687 (WRITE_HOLCOSPKTRESETLIMITr(unit, port, cos, val)); 5688 5689 if ((cos >= 0) && (cos <= 2)) { 5690 fld_val = holcosminxqcnt_0_2__holcosminxqcnt; 5691 } else if (cos == 3) { 5692 fld_val = holcosminxqcnt_3__holcosminxqcnt; 5693 } else { 5694 fld_val = holcosminxqcnt_4_7__holcosminxqcnt; 5695 } 5696 val = 0; 5697 soc_reg_field_set(unit, HOLCOSMINXQCNTr, &val, 5698 HOLCOSMINXQCNTf, fld_val); 5699 SOC_IF_ERROR_RETURN 5700 (WRITE_HOLCOSMINXQCNTr(unit, port, cos, val)); 5701 5702 val = 0; 5703 if ((cos >= 0) && (cos <= 2)) { 5704 fld_val = lwmcoscellsetlimit_0_2__cellsetlimit; 5705 } else if (cos == 3) { 5706 fld_val = lwmcoscellsetlimit_3__cellsetlimit; 5707 } else { 5708 fld_val = lwmcoscellsetlimit_4_7__cellsetlimit; 5709 } 5710 soc_reg_field_set(unit, LWMCOSCELLSETLIMITr, &val, 5711 CELLSETLIMITf, fld_val); 5712 if ((cos >= 0) && (cos <= 2)) { 5713 fld_val = lwmcoscellsetlimit_0_2__cellresetlimit; 5714 } else if (cos == 3) { 5715 fld_val = lwmcoscellsetlimit_3__cellresetlimit; 5716 } else { 5717 fld_val = lwmcoscellsetlimit_4_7__cellresetlimit; 5718 } 5719 soc_reg_field_set(unit, LWMCOSCELLSETLIMITr, &val, 5720 CELLRESETLIMITf, fld_val); 5721 SOC_IF_ERROR_RETURN 5722 (WRITE_LWMCOSCELLSETLIMITr(unit, port, cos, val)); 5723 5724 val = 0; 5725 if ((cos >= 0) && (cos <= 2)) { 5726 fld_val = holcoscellmaxlimit_0_2__cellmaxlimit; 5727 } else if (cos == 3) { 5728 fld_val = holcoscellmaxlimit_3__cellmaxlimit; 5729 } else { 5730 fld_val = holcoscellmaxlimit_4_7__cellmaxlimit; 5731 } 5732 soc_reg_field_set(unit, HOLCOSCELLMAXLIMITr, &val, 5733 CELLMAXLIMITf, fld_val); 5734 if ((cos >= 0) && (cos <= 2)) { 5735 fld_val = holcoscellmaxlimit_0_2__cellmaxresumelimit; 5736 } else if (cos == 3) { 5737 fld_val = holcoscellmaxlimit_3__cellmaxresumelimit; 5738 } else { 5739 fld_val = holcoscellmaxlimit_4_7__cellmaxresumelimit; 5740 } 5741 soc_reg_field_set(unit, HOLCOSCELLMAXLIMITr, &val, 5742 CELLMAXRESUMELIMITf, fld_val); 5743 SOC_IF_ERROR_RETURN 5744 (WRITE_HOLCOSCELLMAXLIMITr(unit, port, cos, val)); 5745 5746 val = 0; 5747 if ((cos >= 0) && (cos <= 2)) { 5748 fld_val = pgcelllimit_0_2__cellsetlimit; 5749 } else if (cos == 3) { 5750 fld_val = pgcelllimit_3__cellsetlimit; 5751 } else if ((cos >= 4) && (cos <= 6)) { 5752 fld_val = pgcelllimit_4_6__cellsetlimit; 5753 } else { 5754 fld_val = pgcelllimit_7__cellsetlimit; 5755 } 5756 soc_reg_field_set(unit, PGCELLLIMITr, &val, 5757 CELLSETLIMITf, fld_val); 5758 if ((cos >= 0) && (cos <= 2)) { 5759 fld_val = pgcelllimit_0_2__cellresetlimit; 5760 } else if (cos == 3) { 5761 fld_val = pgcelllimit_3__cellresetlimit; 5762 } else if ((cos >= 4) && (cos <= 6)) { 5763 fld_val = pgcelllimit_4_6__cellresetlimit; 5764 } else { 5765 fld_val = pgcelllimit_7__cellresetlimit; 5766 } 5767 soc_reg_field_set(unit, PGCELLLIMITr, &val, 5768 CELLRESETLIMITf, fld_val); 5769 SOC_IF_ERROR_RETURN 5770 (WRITE_PGCELLLIMITr(unit, port, cos, val)); 5771 5772 val = 0; 5773 if ((cos >= 0) && (cos <= 2)) { 5774 fld_val = pgdiscardsetlimit_0_2__discardsetlimit; 5775 } else if (cos == 3) { 5776 fld_val = pgdiscardsetlimit_3__discardsetlimit; 5777 } else if ((cos >= 4) && (cos <= 6)) { 5778 fld_val = pgdiscardsetlimit_4_6__discardsetlimit; 5779 } else { 5780 fld_val = pgdiscardsetlimit_7__discardsetlimit; 5781 } 5782 soc_reg_field_set(unit, PGDISCARDSETLIMITr, &val, 5783 DISCARDSETLIMITf, fld_val); 5784 SOC_IF_ERROR_RETURN 5785 (WRITE_PGDISCARDSETLIMITr(unit, port, cos, val)); 5786 5787 val = 0; 5788 soc_reg_field_set(unit, CNGCOSPKTLIMIT0r, &val, 5789 CNGPKTSETLIMIT0f, 5790 cngcospktlimit0_0_7__cngpktsetlimit0); 5791 SOC_IF_ERROR_RETURN 5792 (WRITE_CNGCOSPKTLIMIT0r(unit, port, cos, val)); 5793 val = 0; 5794 soc_reg_field_set(unit, CNGCOSPKTLIMIT1r, &val, 5795 CNGPKTSETLIMIT1f, 5796 cngcospktlimit1_0_7__cngpktsetlimit1); 5797 SOC_IF_ERROR_RETURN 5798 (WRITE_CNGCOSPKTLIMIT1r(unit, port, cos, val)); 5799 } 5800 5801 val = 0; 5802 soc_reg_field_set(unit, CNGPORTPKTLIMIT0r, &val, 5803 CNGPORTPKTLIMIT0f, 5804 cngportpktlimit0_cngportpktlimit0); 5805 SOC_IF_ERROR_RETURN(WRITE_CNGPORTPKTLIMIT0r(unit, port, val)); 5806 5807 val = 0; 5808 soc_reg_field_set(unit, CNGPORTPKTLIMIT1r, &val, 5809 CNGPORTPKTLIMIT1f, 5810 cngportpktlimit1_cngportpktlimit1); 5811 SOC_IF_ERROR_RETURN(WRITE_CNGPORTPKTLIMIT1r(unit, port, val)); 5812 5813 val = 0; 5814 soc_reg_field_set(unit, DYNXQCNTPORTr, &val, 5815 DYNXQCNTPORTf, 5816 dynxqcntport_dynxqcntport); 5817 SOC_IF_ERROR_RETURN(WRITE_DYNXQCNTPORTr(unit, port, val)); 5818 5819 val = 0; 5820 soc_reg_field_set(unit, DYNRESETLIMPORTr, &val, 5821 DYNRESETLIMPORTf, 5822 dynresetlimport_dynresetlimport); 5823 SOC_IF_ERROR_RETURN(WRITE_DYNRESETLIMPORTr(unit, port, val)); 5824 5825 val = 0; 5826 soc_reg_field_set(unit, DYNCELLLIMITr, &val, 5827 DYNCELLSETLIMITf, 5828 dyncelllimit_dyncellsetlimit); 5829 soc_reg_field_set(unit, DYNCELLLIMITr, &val, 5830 DYNCELLRESETLIMITf, 5831 dyncelllimit_dyncellresetlimit); 5832 SOC_IF_ERROR_RETURN(WRITE_DYNCELLLIMITr(unit, port, val)); 5833 5834 val = 0; 5835 soc_reg_field_set(unit, COLOR_DROP_ENr, &val, 5836 COLOR_DROP_ENf, 5837 color_drop_en_color_drop_en); 5838 SOC_IF_ERROR_RETURN(WRITE_COLOR_DROP_ENr(unit, port, val)); 5839 5840 val = 0; 5841 soc_reg_field_set(unit, SHARED_POOL_CTRLr, &val, 5842 DYNAMIC_COS_DROP_ENf, 5843 shared_pool_ctrl_dynamic_cos_drop_en); 5844 soc_reg_field_set(unit, SHARED_POOL_CTRLr, &val, 5845 SHARED_POOL_DISCARD_ENf, 5846 shared_pool_ctrl_shared_pool_discard_en); 5847 soc_reg_field_set(unit, SHARED_POOL_CTRLr, &val, 5848 SHARED_POOL_XOFF_ENf, 5849 shared_pool_ctrl_sharded_pool_xoff_en); 5850 SOC_IF_ERROR_RETURN(WRITE_SHARED_POOL_CTRLr(unit, port, val)); 5851 } 5852 5853 return SOC_E_NONE; 5854 } 5855 5856 STATIC int 5857 soc_wolfhound2_mmu_8_cosq_init_helper(int unit, int lossless) 5858 { 5859 uint32 tmp; 5860 wh2_sku_info_t *matched_port_config = NULL; 5861 int option; 5862 int downlink_port_1g; 5863 int downlink_port_2p5g; 5864 int uplink_port_1g; 5865 int uplink_port_2p5g; 5866 5867 matched_port_config = &wh2_sku_port_config[matched_devid_idx[unit]]; 5868 option = matched_port_config->config_option; 5869 /* MMU settings */ 5870 switch (option) { 5871 case 1: 5872 downlink_port_1g = 20; 5873 downlink_port_2p5g = 4; 5874 uplink_port_1g = 0; 5875 uplink_port_2p5g = 4; 5876 break; 5877 case 2: 5878 case 3: 5879 downlink_port_1g = 24; 5880 downlink_port_2p5g = 0; 5881 uplink_port_1g = 0; 5882 uplink_port_2p5g = 4; 5883 break; 5884 case 4: 5885 case 5: 5886 case 6: 5887 downlink_port_1g = 24; 5888 downlink_port_2p5g = 0; 5889 uplink_port_1g = 4; 5890 uplink_port_2p5g = 0; 5891 break; 5892 case 7: 5893 downlink_port_1g = 12; 5894 downlink_port_2p5g = 4; 5895 uplink_port_1g = 0; 5896 uplink_port_2p5g = 4; 5897 break; 5898 case 8: 5899 case 9: 5900 downlink_port_1g = 16; 5901 downlink_port_2p5g = 0; 5902 uplink_port_1g = 0; 5903 uplink_port_2p5g = 4; 5904 break; 5905 case 10: 5906 case 11: 5907 case 12: 5908 downlink_port_1g = 16; 5909 downlink_port_2p5g = 0; 5910 uplink_port_1g = 4; 5911 uplink_port_2p5g = 0; 5912 break; 5913 case 13: 5914 downlink_port_1g = 4; 5915 downlink_port_2p5g = 4; 5916 uplink_port_1g = 0; 5917 uplink_port_2p5g = 4; 5918 break; 5919 case 14: 5920 case 15: 5921 downlink_port_1g = 8; 5922 downlink_port_2p5g = 0; 5923 uplink_port_1g = 0; 5924 uplink_port_2p5g = 4; 5925 break; 5926 case 16: 5927 case 17: 5928 case 18: 5929 downlink_port_1g = 8; 5930 downlink_port_2p5g = 0; 5931 uplink_port_1g = 4; 5932 uplink_port_2p5g = 0; 5933 break; 5934 default: 5935 /* Default matched wh2_sku_port_config[0] */ 5936 downlink_port_1g = 20; 5937 downlink_port_2p5g = 4; 5938 uplink_port_1g = 0; 5939 uplink_port_2p5g = 4; 5940 break; 5941 } 5942 5943 /* Prepare MMU settings */ 5944 /* 5945 * Traffic Attributes 5946 */ 5947 /* c7 */ 5948 mmu_params.min_packet_size_traffic_attr = 64; 5949 /* 5950 * c8 5951 * the value is 1.5 in doc, save 15 instead in sw. 5952 * any later usage should take care of this. 5953 */ 5954 mmu_params.ethernet_mtu_traffic_attr = 15; 5955 /* c9 */ 5956 mmu_params.max_packet_size_traffic_attr = 12288; 5957 /* c10 */ 5958 mmu_params.standard_jumbo_frame_traffic_attr = 9216; 5959 /* c11 */ 5960 mmu_params.lossless_traffic_mtu_size_traffic_attr = 2048; 5961 5962 /* 5963 * General Information 5964 * moved to earlier place as these are needed by others 5965 */ 5966 /* c79 = CEILING(C7/c49, 1)*/ 5967 tmp = mmu_params.min_packet_size_traffic_attr / CELL_SIZE; 5968 mmu_params.min_packet_size = _ceil_func(tmp, 1); 5969 /* c80 = CEILING(C8*1024/c49, 1)*/ 5970 tmp = (mmu_params.ethernet_mtu_traffic_attr * 1024) / CELL_SIZE; 5971 tmp /= 10; /* The value is 1.5 in MMU setting data, save as 15 in SW */ 5972 mmu_params.ethernet_mtu = _ceil_func(tmp, 1); 5973 /* c81 = CEILING(C9/c49, 1)*/ 5974 tmp = mmu_params.max_packet_size_traffic_attr / CELL_SIZE; 5975 mmu_params.max_packet_size = _ceil_func(tmp, 1); 5976 /* c82 = CEILING(C10/c49, 1)*/ 5977 tmp = mmu_params.standard_jumbo_frame_traffic_attr / CELL_SIZE; 5978 mmu_params.standard_jumbo_frame = _ceil_func(tmp, 1); 5979 /* c83 = CEILING(C11/c49, 1)*/ 5980 tmp = mmu_params.lossless_traffic_mtu_size_traffic_attr / CELL_SIZE; 5981 mmu_params.lossless_traffic_mtu_size = _ceil_func(tmp, 1); 5982 5983 /* 5984 * Reservations 5985 * moved to earlier place as these are needed by others 5986 */ 5987 /* c70 = c80*4*/ 5988 mmu_params.wrr_reserve = mmu_params.ethernet_mtu * 4; 5989 /* c71 = (31)*2 +7+29*/ 5990 mmu_params.reserved_for_cfap = 98; 5991 /* c72 */ 5992 mmu_params.skidmarker = 7; 5993 /* c73 */ 5994 mmu_params.skidmarker_option = 3; 5995 /* c74 */ 5996 mmu_params.prefetch = 9; 5997 5998 /* 5999 * SW Config Property 6000 */ 6001 /* c14 */ 6002 mmu_params.total_physical_memory_sw_cfg = 4096; 6003 /* c15 = c14-c71 */ 6004 mmu_params.cfapfullsetpoint_sw_cfg = \ 6005 mmu_params.total_physical_memory_sw_cfg - mmu_params.reserved_for_cfap; 6006 /* c16 = c15 */ 6007 mmu_params.total_cell_memory_for_admission_sw_cfg = \ 6008 mmu_params.cfapfullsetpoint_sw_cfg; 6009 6010 /* c17 configurable */ 6011 mmu_params.num_1g_ports_uplink_ports_sw_cfg = uplink_port_1g; 6012 /* c18 configurable */ 6013 mmu_params.num_2p5g_ports_uplink_ports_sw_cfg = uplink_port_2p5g; 6014 /* c19 configurable */ 6015 mmu_params.num_1g_ports_downlink_ports_sw_cfg = downlink_port_1g; 6016 /* c20 configurable */ 6017 mmu_params.num_2p5g_ports_downlink_ports_sw_cfg = downlink_port_2p5g; 6018 /* c21 = SUM(C17:C18) */ 6019 mmu_params.number_of_uplink_ports_sw_cfg = \ 6020 mmu_params.num_1g_ports_uplink_ports_sw_cfg + \ 6021 mmu_params.num_2p5g_ports_uplink_ports_sw_cfg; 6022 /* c22 = SUM(C19:C20)*/ 6023 mmu_params.number_of_downlink_ports_sw_cfg = \ 6024 mmu_params.num_1g_ports_downlink_ports_sw_cfg + \ 6025 mmu_params.num_2p5g_ports_downlink_ports_sw_cfg; 6026 /* c23 lossless */ 6027 if (lossless) { 6028 mmu_params.flow_control_enabled_sw_cfg = 1; 6029 } else { 6030 mmu_params.flow_control_enabled_sw_cfg = 0; 6031 } 6032 /* c24 PFC = 0 */ 6033 mmu_params.flow_control_type_sw_cfg = 0; 6034 /* c25 = 0.25, not used */ 6035 /* mmu_params.queue_port_limit_ratio_sw_cfg = 0.25; */ 6036 6037 /* 6038 * Device Attributes 6039 * moved to earlier place as these are needed by others 6040 */ 6041 /* c49 */ 6042 mmu_params.cell_size = CELL_SIZE; 6043 /* c50 */ 6044 mmu_params.num_egress_queues_per_port = WH2_QUEUE_MAX_NUM; /* 8 */ 6045 /* c51 */ 6046 mmu_params.num_cpu_queues = 8; 6047 /* c52 = c17*/ 6048 mmu_params.num_1g_ports_uplink_ports = \ 6049 mmu_params.num_1g_ports_uplink_ports_sw_cfg; 6050 /* c53 = c18 */ 6051 mmu_params.num_2p5g_ports_uplink_ports = \ 6052 mmu_params.num_2p5g_ports_uplink_ports_sw_cfg; 6053 /* c54 = c19 */ 6054 mmu_params.num_1g_ports_downlink_ports = \ 6055 mmu_params.num_1g_ports_downlink_ports_sw_cfg; 6056 /* c55 = c20 */ 6057 mmu_params.num_2p5g_ports_downlink_ports = \ 6058 mmu_params.num_2p5g_ports_downlink_ports_sw_cfg; 6059 /* c56 */ 6060 mmu_params.num_cpu_ports = 1; 6061 /* c57 = c21*/ 6062 mmu_params.number_of_uplink_ports = \ 6063 mmu_params.number_of_uplink_ports_sw_cfg; 6064 /* c58 = c22 */ 6065 mmu_params.number_of_downlink_ports = \ 6066 mmu_params.number_of_downlink_ports_sw_cfg; 6067 /* c59 = c14 */ 6068 mmu_params.total_physical_memory = \ 6069 mmu_params.total_physical_memory_sw_cfg; 6070 /* c60 = c16 */ 6071 mmu_params.total_cell_memory = \ 6072 mmu_params.total_cell_memory_for_admission_sw_cfg; 6073 /* c61 = c60 */ 6074 mmu_params.total_advertised_cell_memory = \ 6075 mmu_params.total_cell_memory; 6076 /* c62 */ 6077 mmu_params.numxq_per_uplink_ports = 512; 6078 /* c63 */ 6079 mmu_params.numxq_per_downlink_ports_and_cpu_port = 512; 6080 /* c64 */ 6081 mmu_params.the_number_of_pipelines_per_device = 1; 6082 /* c66 */ 6083 mmu_params.n_egress_queues_active_per_xpe = 1; 6084 /* c67 */ 6085 mmu_params.n_ingress_ports_active_per_xpe = 1; 6086 6087 /* 6088 * SW Config Parameter 6089 */ 6090 /* c29 */ 6091 mmu_params.egress_queue_min_reserve_uplink_ports_lossy = 0; 6092 /* c30 */ 6093 mmu_params.egress_queue_min_reserve_downlink_ports_lossy = 0; 6094 /* c31 */ 6095 mmu_params.egress_queue_min_reserve_uplink_ports_lossless = 12; 6096 /* c32 */ 6097 mmu_params.egress_queue_min_reserve_downlink_ports_lossless = 12; 6098 /* c33 = c80 */ 6099 mmu_params.egress_queue_min_reserve_cpu_ports = \ 6100 mmu_params.ethernet_mtu; 6101 /* c34 */ 6102 mmu_params.egress_xq_min_reserve_lossy_uplink_and_downlink_ports = 0; 6103 /* c35 */ 6104 mmu_params.egress_xq_min_reserve_lossless_uplink_ports = 12; 6105 /* c36 */ 6106 mmu_params.egress_xq_min_reserve_lossless_downlink_ports = 12; 6107 /* c37 */ 6108 mmu_params.num_total_pri_groups = 4; 6109 /* c38 */ 6110 mmu_params.num_active_pri_group_lossless = 1; 6111 /* c39 */ 6112 mmu_params.num_lossless_queues = 4; 6113 /* c40 */ 6114 mmu_params.num_lossy_queues = 0; 6115 /* c41 = c61 */ 6116 mmu_params.mmu_xoff_pkt_threshold_uplink_ports = 12; 6117 /* c42 = c61 */ 6118 mmu_params.mmu_xoff_pkt_threshold_downlink_ports = 12; 6119 /* c43 = c61 */ 6120 mmu_params.mmu_xoff_cell_threshold_1g_port_uplink_ports = 36; 6121 /* c44 = c61 */ 6122 mmu_params.mmu_xoff_cell_threshold_2p5g_port_uplink_ports = 36; 6123 /* c45 = c61 */ 6124 mmu_params.mmu_xoff_cell_threshold_1g_downlink_ports = 36; 6125 /* c46 = c61 */ 6126 mmu_params.mmu_xoff_cell_threshold_2p5g_downlink_ports = 36; 6127 6128 /* 6129 * Ingress Thresholds 6130 */ 6131 /* c85 */ 6132 mmu_params.headroom_for_1g_port = 36; 6133 /* c86 */ 6134 mmu_params.headroom_for_2p5g_port = 36; 6135 /* c87 = c45 */ 6136 mmu_params.xoff_cell_thresholds_per_port_pg_1g_port_downlink_ports = \ 6137 mmu_params.mmu_xoff_cell_threshold_1g_downlink_ports; 6138 /* c88 = c46 */ 6139 mmu_params.xoff_cell_thresholds_per_port_pg_2p5g_port_downlink_ports = \ 6140 mmu_params.mmu_xoff_cell_threshold_2p5g_downlink_ports; 6141 /* c89 = c43 */ 6142 mmu_params.xoff_cell_threshold_1g_uplink_ports = \ 6143 mmu_params.mmu_xoff_cell_threshold_1g_port_uplink_ports; 6144 /* c90 = c44 */ 6145 mmu_params.xoff_cell_threshold_2p5g_uplink_ports = \ 6146 mmu_params.mmu_xoff_cell_threshold_2p5g_port_uplink_ports; 6147 /* c91 = c41 */ 6148 mmu_params.xoff_packet_thresholds_per_port_uplink_port = \ 6149 mmu_params.mmu_xoff_pkt_threshold_uplink_ports; 6150 /* c92 = c42 */ 6151 mmu_params.xoff_packet_thresholds_per_port_downlink_port = \ 6152 mmu_params.mmu_xoff_pkt_threshold_downlink_ports; 6153 /* c93 = c61 */ 6154 mmu_params.discard_limit_per_port_pg_downlink_1g_port = \ 6155 mmu_params.total_advertised_cell_memory; 6156 /* c94 = c61 */ 6157 mmu_params.discard_limit_per_port_pg_downlink_2p5g_port = \ 6158 mmu_params.total_advertised_cell_memory; 6159 /* c95 = c61 */ 6160 mmu_params.discard_limit_per_port_pg_uplink_port = \ 6161 mmu_params.total_advertised_cell_memory; 6162 6163 /* 6164 * Egress Thresholds 6165 */ 6166 /* c97 = c29*c57*c40+c57*c31*c39 */ 6167 mmu_params.total_reserved_cells_for_uplink_ports = \ 6168 (mmu_params.egress_queue_min_reserve_uplink_ports_lossy * \ 6169 mmu_params.number_of_uplink_ports * \ 6170 mmu_params.num_lossy_queues) + \ 6171 (mmu_params.number_of_uplink_ports * \ 6172 mmu_params.egress_queue_min_reserve_uplink_ports_lossless * \ 6173 mmu_params.num_lossless_queues); 6174 /* c98 = c58*c30*(c40)+c58*c32*c39 */ 6175 mmu_params.total_reserved_cells_for_downlink_ports = \ 6176 (mmu_params.number_of_downlink_ports * \ 6177 mmu_params.egress_queue_min_reserve_downlink_ports_lossy * \ 6178 mmu_params.num_lossy_queues) + \ 6179 (mmu_params.number_of_downlink_ports * \ 6180 mmu_params.egress_queue_min_reserve_downlink_ports_lossless * \ 6181 mmu_params.num_lossless_queues); 6182 /* c99 = c56*c33*c51 */ 6183 mmu_params.total_reserved_cells_for_cpu_port = \ 6184 mmu_params.num_cpu_ports * \ 6185 mmu_params.egress_queue_min_reserve_cpu_ports * \ 6186 mmu_params.num_cpu_queues; 6187 /* c100 = SUM(c97:c99) */ 6188 mmu_params.total_reserved = \ 6189 mmu_params.total_reserved_cells_for_uplink_ports + \ 6190 mmu_params.total_reserved_cells_for_downlink_ports + \ 6191 mmu_params.total_reserved_cells_for_cpu_port; 6192 /* c101 = c61-c100 */ 6193 mmu_params.shared_space_cells = \ 6194 mmu_params.total_advertised_cell_memory - \ 6195 mmu_params.total_reserved; 6196 /* c102 = c34*c40+c35*c39 */ 6197 mmu_params.reserved_xqs_per_uplink_port = \ 6198 (mmu_params.egress_xq_min_reserve_lossy_uplink_and_downlink_ports * \ 6199 mmu_params.num_lossy_queues) + \ 6200 (mmu_params.egress_xq_min_reserve_lossless_uplink_ports * \ 6201 mmu_params.num_lossless_queues); 6202 /* c103 = c62-c102 */ 6203 mmu_params.shared_xqs_per_uplink_port = \ 6204 mmu_params.numxq_per_uplink_ports - \ 6205 mmu_params.reserved_xqs_per_uplink_port; 6206 /* c104 = c34*c40+c36*c39 */ 6207 mmu_params.reserved_xqs_per_downlink_port = \ 6208 (mmu_params.egress_xq_min_reserve_lossy_uplink_and_downlink_ports * \ 6209 mmu_params.num_lossy_queues) + \ 6210 (mmu_params.egress_xq_min_reserve_lossless_downlink_ports * \ 6211 mmu_params.num_lossless_queues); 6212 /* c105 = c63-c104 */ 6213 mmu_params.shared_xqs_per_downlink_port = \ 6214 mmu_params.numxq_per_downlink_ports_and_cpu_port - \ 6215 mmu_params.reserved_xqs_per_downlink_port; 6216 /* c106 = c33 * c51 */ 6217 mmu_params.reserved_xqs_at_cpu_port = \ 6218 mmu_params.egress_queue_min_reserve_cpu_ports * \ 6219 mmu_params.num_cpu_queues; 6220 /* c107 = c63 - c106 */ 6221 mmu_params.shared_xqs_at_cpu_port = \ 6222 mmu_params.numxq_per_downlink_ports_and_cpu_port - \ 6223 mmu_params.reserved_xqs_at_cpu_port; 6224 6225 /* Program MMU settings */ 6226 SOC_IF_ERROR_RETURN( 6227 soc_wolfhound2_mmu_8_cosq_config_helper(unit, lossless)); 6228 6229 return SOC_E_NONE; 6230 } 6231 6232 STATIC int 6233 soc_wolfhound2_mmu_init(int unit) 6234 { 6235 uint32 val, oval, cfap_max_idx; 6236 int lossless_mode = 0; 6237 soc_pbmp_t pbmp_lossless; 6238 int count = 0; 6239 int num_cos; 6240 int cfg_8_queues = 0; /* Default configuration for 4 COSQ.*/ 6241 6242 SOC_IF_ERROR_RETURN(soc_wolfhound2_tdm_init(unit)); 6243 6244 cfap_max_idx = soc_mem_index_max(unit, MMU_CFAPm); 6245 SOC_IF_ERROR_RETURN(READ_CFAPCONFIGr(unit, &val)); 6246 oval = val; 6247 soc_reg_field_set(unit, CFAPCONFIGr, &val, CFAPPOOLSIZEf, cfap_max_idx); 6248 if (oval != val) { 6249 SOC_IF_ERROR_RETURN(WRITE_CFAPCONFIGr(unit, val)); 6250 } 6251 6252 /* Default lossy mode */ 6253 lossless_mode = soc_property_get(unit, spn_MMU_LOSSLESS, 0); 6254 6255 SOC_PBMP_CLEAR(pbmp_lossless); 6256 pbmp_lossless = soc_property_get_pbmp_default(unit, spn_MMU_LOSSLESS_PBMP, 6257 pbmp_lossless); 6258 SOC_PBMP_COUNT(pbmp_lossless, count); 6259 6260 /* Default 4 COSQ if config file not assigned */ 6261 num_cos = soc_property_get(unit, spn_BCM_NUM_COS, WH2_QUEUE_DEFAULT_NUM); 6262 if ((num_cos < 1) || (num_cos > WH2_QUEUE_MAX_NUM)) { 6263 LOG_WARN(BSL_LS_SOC_COMMON, 6264 (BSL_META_U(unit, 6265 "Warning: invalid COSQ number %d specified. " 6266 "Use default 4 COSQ. \n"), num_cos)); 6267 num_cos = WH2_QUEUE_DEFAULT_NUM; 6268 } 6269 if (num_cos > WH2_QUEUE_DEFAULT_NUM) { 6270 cfg_8_queues = 1; 6271 } 6272 6273 if (cfg_8_queues) { 6274 /* 8 COSQ setting.*/ 6275 if (lossless_mode) { 6276 SOC_IF_ERROR_RETURN( 6277 soc_wolfhound2_mmu_8_cosq_init_helper(unit, 1)); 6278 } else { 6279 SOC_IF_ERROR_RETURN( 6280 soc_wolfhound2_mmu_8_cosq_init_helper(unit, 0)); 6281 } 6282 } else { 6283 /* 4 COSQ setting (default). */ 6284 if (lossless_mode) { 6285 if ((count > 0) && (count <= 4)) { 6286 /* 6287 * Lossy+Lossless(PFC) mode. Maximum 4 support ports lossless. 6288 */ 6289 SOC_IF_ERROR_RETURN( 6290 soc_wolfhound2_mmu_lossy_lossless_pfc_init_helper(unit)); 6291 } else { 6292 /* Lossless(Pause) mode. Legacy lossless mode.*/ 6293 SOC_IF_ERROR_RETURN( 6294 soc_wolfhound2_mmu_lossy_or_lossless_init_helper(unit, 1)); 6295 } 6296 } else { 6297 /* Legacy loss mode.*/ 6298 SOC_IF_ERROR_RETURN( 6299 soc_wolfhound2_mmu_lossy_or_lossless_init_helper(unit, 0)); 6300 } 6301 } 6302 6303 /* Enable IP to CMICM credit transfer */ 6304 val = 0; 6305 soc_reg_field_set(unit, IP_TO_CMICM_CREDIT_TRANSFERr, &val, 6306 TRANSFER_ENABLEf, 1); 6307 soc_reg_field_set(unit, IP_TO_CMICM_CREDIT_TRANSFERr, &val, 6308 NUM_OF_CREDITSf, 32); 6309 SOC_IF_ERROR_RETURN(WRITE_IP_TO_CMICM_CREDIT_TRANSFERr(unit, val)); 6310 6311 /* 6312 * Port enable 6313 */ 6314 val = 0; 6315 soc_reg_field_set(unit, MMUPORTENABLEr, &val, MMUPORTENABLEf, 6316 SOC_PBMP_WORD_GET(PBMP_ALL(unit), 0)); 6317 SOC_IF_ERROR_RETURN(WRITE_MMUPORTENABLEr(unit, val)); 6318 6319 return SOC_E_NONE; 6320 } 6321 6322 STATIC int 6323 soc_wolfhound2_age_timer_get(int unit, int *age_seconds, int *enabled) 6324 { 6325 uint32 value; 6326 6327 SOC_IF_ERROR_RETURN(READ_L2_AGE_TIMERr(unit, &value)); 6328 *enabled = soc_reg_field_get(unit, L2_AGE_TIMERr, value, AGE_ENAf); 6329 *age_seconds = soc_reg_field_get(unit, L2_AGE_TIMERr, value, AGE_VALf); 6330 6331 return SOC_E_NONE; 6332 } 6333 6334 STATIC int 6335 soc_wolfhound2_age_timer_max_get(int unit, int *max_seconds) 6336 { 6337 *max_seconds = 6338 soc_reg_field_get(unit, L2_AGE_TIMERr, 0xffffffff, AGE_VALf); 6339 6340 return SOC_E_NONE; 6341 } 6342 6343 STATIC int 6344 soc_wolfhound2_age_timer_set(int unit, int age_seconds, int enable) 6345 { 6346 uint32 value; 6347 6348 value = 0; 6349 soc_reg_field_set(unit, L2_AGE_TIMERr, &value, AGE_ENAf, enable); 6350 soc_reg_field_set(unit, L2_AGE_TIMERr, &value, AGE_VALf, age_seconds); 6351 SOC_IF_ERROR_RETURN(WRITE_L2_AGE_TIMERr(unit, value)); 6352 6353 return SOC_E_NONE; 6354 } 6355 6356 /* 6357 * Wolfhound2 chip driver functions. 6358 */ 6359 soc_functions_t soc_wolfhound2_drv_funs = { 6360 soc_wolfhound2_misc_init, 6361 soc_wolfhound2_mmu_init, 6362 soc_wolfhound2_age_timer_get, 6363 soc_wolfhound2_age_timer_max_get, 6364 soc_wolfhound2_age_timer_set, 6365 NULL, 6366 NULL, 6367 NULL, 6368 }; 6369 6370 #endif /* BCM_HURRICANE3_SUPPORT */