tcam.c (260478B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: tcam.c 8 * Purpose: TR3 specific ESM code. 9 * Requires: 10 */ 11 12 #include <sal/core/boot.h> 13 #include <shared/bsl.h> 14 #include <soc/triumph3.h> 15 #include <soc/drv.h> 16 #include <soc/error.h> 17 #include <soc/debug.h> 18 #include <soc/mem.h> 19 #include <soc/tcam/tcamtype1.h> 20 #include <soc/er_tcam.h> 21 22 #ifdef BCM_TRIUMPH3_SUPPORT 23 24 /* 25 * sorted order of TCAM partitions in ascending order of entry size, per 26 * entry type (L2, L3, ACL). Order of L2 and L3 partitions can change 27 * depending on database duplication 28 */ 29 uint32 tr3_tcam_partition_order[] = { 30 TCAM_PARTITION_FWD_L2, /* Triumph */ 31 TCAM_PARTITION_FWD_L2_WIDE, /* Triumph3 */ 32 TCAM_PARTITION_FWD_IP4_UCAST,/* Triumph3 */ 33 TCAM_PARTITION_FWD_IP4_UCAST_WIDE, /* Triumph3 */ 34 TCAM_PARTITION_FWD_IP4, /* Triumph */ 35 TCAM_PARTITION_FWD_IP6U, /* Triumph */ 36 TCAM_PARTITION_FWD_IP6_128_UCAST, /* Triumph3 */ 37 TCAM_PARTITION_FWD_IP6_128_UCAST_WIDE, /* Triumph3 */ 38 TCAM_PARTITION_FWD_IP6, /* Triumph */ 39 TCAM_PARTITION_ACL80, /* Triumph3 */ 40 TCAM_PARTITION_ACL_L2C, /* Triumph */ 41 TCAM_PARTITION_ACL_IP4C, /* Triumph */ 42 TCAM_PARTITION_ACL_IP6C, /* Triumph */ 43 TCAM_PARTITION_ACL160, /* Triumph3 */ 44 TCAM_PARTITION_ACL_L2, /* Triumph */ 45 TCAM_PARTITION_ACL_IP4, /* Triumph */ 46 TCAM_PARTITION_ACL_L2IP4, /* Triumph */ 47 TCAM_PARTITION_ACL320, /* Triumph3 */ 48 TCAM_PARTITION_ACL_IP6S, /* Triumph */ 49 TCAM_PARTITION_ACL_IP6F, /* Triumph */ 50 TCAM_PARTITION_ACL_L2IP6, /* Triumph */ 51 TCAM_PARTITION_ACL480, /* Triumph3 */ 52 0, /* to be populated with duplicate partitons if any */ 53 0, 54 0, 55 0 56 }; 57 58 uint32 tr3_tcam_partition_order_num_entries = sizeof(tr3_tcam_partition_order)/ 59 sizeof(uint32); 60 61 /* record offset of start of duplicate partitions here */ 62 uint32 tr3_dup_part_offset = 22; 63 uint32 tr3_dup_part_count; 64 65 static tr3_worst_fme_t tr3_worst_fme[SOC_MAX_NUM_DEVICES]; 66 67 int 68 soc_tr3_esm_get_worst_fme(int unit) 69 { 70 return tr3_worst_fme[unit].idx; 71 } 72 73 int 74 soc_tr3_esm_init_read_config(int unit) 75 { 76 soc_control_t *soc; 77 soc_tcam_info_t *tcam_info; 78 soc_tcam_partition_t *partitions; 79 int table_size[TCAM_PARTITION_COUNT]; 80 int i, count; 81 int ext_l2_duplicated = 0; 82 int ext_ipv4_duplicated = 0; 83 int ext_ipv6u_duplicated = 0; 84 int ext_ipv6_duplicated = 0; 85 int ext_l2_bulk_enable = 1, ext_l2_hit_bit_enable = 1; 86 int ext_l3_hit_bit_enable = 1, ext_acl80_policy_width=5; 87 int ext_acl160_policy_width=5, ext_acl320_policy_width=5; 88 int ext_acl480_policy_width=5; 89 int ext_policy_width, dup_count=0; 90 91 soc = SOC_CONTROL(unit); 92 tr3_dup_part_count = 0; 93 94 sal_memset(table_size, 0, sizeof(table_size)); 95 96 table_size[TCAM_PARTITION_FWD_L2] = 97 soc_property_get(unit, spn_EXT_L2_FWD_TABLE_SIZE, 0); 98 table_size[TCAM_PARTITION_FWD_L2_WIDE] = 99 soc_property_get(unit, spn_EXT_L2_WIDE_FWD_TABLE_SIZE, 0); 100 101 table_size[TCAM_PARTITION_FWD_IP4_UCAST] = 102 soc_property_get(unit, spn_EXT_IP4_HOST_FWD_TABLE_SIZE, 0); 103 table_size[TCAM_PARTITION_FWD_IP4_UCAST_WIDE] = 104 soc_property_get(unit, spn_EXT_IP4_HOST_WIDE_FWD_TABLE_SIZE, 0); 105 table_size[TCAM_PARTITION_FWD_IP4] = 106 soc_property_get(unit, spn_EXT_IP4_FWD_TABLE_SIZE, 0); 107 table_size[TCAM_PARTITION_FWD_IP6U] = 108 soc_property_get(unit, spn_EXT_IP6U_FWD_TABLE_SIZE, 0); 109 table_size[TCAM_PARTITION_FWD_IP6_128_UCAST] = 110 soc_property_get(unit, spn_EXT_IP6_HOST_FWD_TABLE_SIZE, 0); 111 table_size[TCAM_PARTITION_FWD_IP6_128_UCAST_WIDE] = 112 soc_property_get(unit, spn_EXT_IP6_HOST_WIDE_FWD_TABLE_SIZE, 0); 113 table_size[TCAM_PARTITION_FWD_IP6] = 114 soc_property_get(unit, spn_EXT_IP6_FWD_TABLE_SIZE, 0); 115 116 table_size[TCAM_PARTITION_ACL_L2] = 117 soc_property_get(unit, spn_EXT_L2_ACL_TABLE_SIZE, 0); 118 table_size[TCAM_PARTITION_ACL_IP4] = 119 soc_property_get(unit, spn_EXT_IP4_ACL_TABLE_SIZE, 0); 120 table_size[TCAM_PARTITION_ACL_IP6S] = 121 soc_property_get(unit, spn_EXT_IP6S_ACL_TABLE_SIZE, 0); 122 table_size[TCAM_PARTITION_ACL_IP6F] = 123 soc_property_get(unit, spn_EXT_IP6F_ACL_TABLE_SIZE, 0); 124 table_size[TCAM_PARTITION_ACL_L2C] = 125 soc_property_get(unit, spn_EXT_L2C_ACL_TABLE_SIZE, 0); 126 table_size[TCAM_PARTITION_ACL_IP4C] = 127 soc_property_get(unit, spn_EXT_IP4C_ACL_TABLE_SIZE, 0); 128 table_size[TCAM_PARTITION_ACL_IP6C] = 129 soc_property_get(unit, spn_EXT_IP6C_ACL_TABLE_SIZE, 0); 130 table_size[TCAM_PARTITION_ACL_L2IP4] = 131 soc_property_get(unit, spn_EXT_L2IP4_ACL_TABLE_SIZE, 0); 132 table_size[TCAM_PARTITION_ACL_L2IP6] = 133 soc_property_get(unit, spn_EXT_L2IP6_ACL_TABLE_SIZE, 0); 134 table_size[TCAM_PARTITION_ACL80] = 135 soc_property_get(unit, spn_EXT_ACL80_TABLE_SIZE, 0); 136 table_size[TCAM_PARTITION_ACL160] = 137 soc_property_get(unit, spn_EXT_ACL160_TABLE_SIZE, 0); 138 table_size[TCAM_PARTITION_ACL320] = 139 soc_property_get(unit, spn_EXT_ACL320_TABLE_SIZE, 0); 140 table_size[TCAM_PARTITION_ACL480] = 141 soc_property_get(unit, spn_EXT_ACL480_TABLE_SIZE, 0); 142 143 ext_l2_duplicated = soc_property_get(unit, spn_EXT_L2_TABLE_DUPLICATED, 0); 144 ext_ipv4_duplicated = soc_property_get(unit, spn_EXT_IP4_TABLE_DUPLICATED, 145 0); 146 ext_ipv6u_duplicated = soc_property_get(unit, spn_EXT_IP6U_TABLE_DUPLICATED, 147 0); 148 ext_ipv6_duplicated = soc_property_get(unit, spn_EXT_IP6_TABLE_DUPLICATED, 149 0); 150 151 /* reorder partitions if there are duplicated databases */ 152 153 154 /* L2 partition always comes first. So fake it as duplicate as far 155 * as ordering is concerned 156 */ 157 dup_count = 2; 158 tr3_tcam_partition_order[0] = TCAM_PARTITION_FWD_L2; 159 tr3_tcam_partition_order[1] = TCAM_PARTITION_FWD_L2_WIDE; 160 if (ext_l2_duplicated) { 161 table_size[TCAM_PARTITION_FWD_L2_DUP] = 162 ROUND_UP_M(table_size[TCAM_PARTITION_FWD_L2], 4096) + 163 ROUND_UP_M(table_size[TCAM_PARTITION_FWD_L2_WIDE], 4096); 164 tr3_tcam_partition_order[tr3_dup_part_offset + tr3_dup_part_count] = 165 TCAM_PARTITION_FWD_L2_DUP; 166 tr3_dup_part_count++; 167 } 168 if (ext_ipv4_duplicated) { 169 table_size[TCAM_PARTITION_FWD_IP4_DUP] = 170 ROUND_UP_M(table_size[TCAM_PARTITION_FWD_IP4_UCAST], 4096) + 171 ROUND_UP_M(table_size[TCAM_PARTITION_FWD_IP4_UCAST_WIDE], 4096) + 172 ROUND_UP_M(table_size[TCAM_PARTITION_FWD_IP4], 4096); 173 tr3_tcam_partition_order[dup_count++] = TCAM_PARTITION_FWD_IP4_UCAST; 174 tr3_tcam_partition_order[dup_count++] = 175 TCAM_PARTITION_FWD_IP4_UCAST_WIDE; 176 tr3_tcam_partition_order[dup_count++] = TCAM_PARTITION_FWD_IP4; 177 tr3_tcam_partition_order[tr3_dup_part_offset + tr3_dup_part_count] = 178 TCAM_PARTITION_FWD_IP4_DUP; 179 tr3_dup_part_count++; 180 } 181 if (ext_ipv6u_duplicated) { 182 table_size[TCAM_PARTITION_FWD_IP6U_DUP] = 183 ROUND_UP_M(table_size[TCAM_PARTITION_FWD_IP6U], 4096); 184 tr3_tcam_partition_order[dup_count++] = TCAM_PARTITION_FWD_IP6U; 185 tr3_tcam_partition_order[tr3_dup_part_offset + tr3_dup_part_count] = 186 TCAM_PARTITION_FWD_IP6U_DUP; 187 tr3_dup_part_count++; 188 } 189 if (ext_ipv6_duplicated) { 190 table_size[TCAM_PARTITION_FWD_IP6_DUP] = 191 ROUND_UP_M(table_size[TCAM_PARTITION_FWD_IP6_128_UCAST], 2048) + 192 ROUND_UP_M(table_size[TCAM_PARTITION_FWD_IP6_128_UCAST_WIDE], 2048) + 193 ROUND_UP_M(table_size[TCAM_PARTITION_FWD_IP6], 2048); 194 tr3_tcam_partition_order[dup_count++]= TCAM_PARTITION_FWD_IP6_128_UCAST; 195 tr3_tcam_partition_order[dup_count++] = 196 TCAM_PARTITION_FWD_IP6_128_UCAST_WIDE; 197 tr3_tcam_partition_order[dup_count++] = TCAM_PARTITION_FWD_IP6; 198 tr3_tcam_partition_order[tr3_dup_part_offset + tr3_dup_part_count] = 199 TCAM_PARTITION_FWD_IP6_DUP; 200 tr3_dup_part_count++; 201 } 202 if (tr3_dup_part_count) { 203 /* fill remaining part of partition_order array */ 204 /* whatever is not duplicated comes here */ 205 if (!ext_ipv4_duplicated) { 206 tr3_tcam_partition_order[dup_count++]=TCAM_PARTITION_FWD_IP4_UCAST; 207 tr3_tcam_partition_order[dup_count++] = 208 TCAM_PARTITION_FWD_IP4_UCAST_WIDE; 209 tr3_tcam_partition_order[dup_count++] = TCAM_PARTITION_FWD_IP4; 210 } 211 if (!ext_ipv6u_duplicated) { 212 tr3_tcam_partition_order[dup_count++] = TCAM_PARTITION_FWD_IP6U; 213 } 214 if (!ext_ipv6_duplicated) { 215 tr3_tcam_partition_order[dup_count++] = 216 TCAM_PARTITION_FWD_IP6_128_UCAST; 217 tr3_tcam_partition_order[dup_count++] = 218 TCAM_PARTITION_FWD_IP6_128_UCAST_WIDE; 219 tr3_tcam_partition_order[dup_count++] = TCAM_PARTITION_FWD_IP6; 220 } 221 } 222 223 count = 0; 224 for (i = TCAM_PARTITION_RAW + 1; i < TCAM_PARTITION_COUNT; i++) { 225 count += table_size[i]; 226 } 227 228 /* No table is configured, done! */ 229 if (!count) { 230 SOC_FEATURE_CLEAR(unit, soc_feature_esm_support); 231 SOC_FEATURE_CLEAR(unit, soc_feature_etu_support); 232 SOC_FEATURE_CLEAR(unit, soc_feature_esm_correction); 233 return SOC_E_NONE; 234 } 235 236 if (soc->tcam_info == NULL) { 237 soc->tcam_info = sal_alloc(sizeof(soc_tcam_info_t), "tcam info"); 238 if (soc->tcam_info == NULL) { 239 SOC_FEATURE_CLEAR(unit, soc_feature_esm_support); 240 SOC_FEATURE_CLEAR(unit, soc_feature_etu_support); 241 SOC_FEATURE_CLEAR(unit, soc_feature_esm_correction); 242 return SOC_E_MEMORY; 243 } 244 /* Clear ESM information */ 245 sal_memset(soc->tcam_info, 0, sizeof(soc_tcam_info_t)); 246 } 247 248 tcam_info = soc->tcam_info; 249 partitions = tcam_info->partitions; 250 251 for (i = TCAM_PARTITION_RAW + 1; i < TCAM_PARTITION_COUNT; i++) { 252 tcam_info->partitions[i].num_entries = table_size[i]; 253 } 254 if (table_size[TCAM_PARTITION_FWD_L2_WIDE]) { 255 if (table_size[TCAM_PARTITION_FWD_L2]) { 256 partitions[TCAM_PARTITION_FWD_L2].flags |= 257 TCAM_PARTITION_FLAGS_COALESCE; 258 } 259 } 260 if (table_size[TCAM_PARTITION_FWD_IP4_UCAST]) { 261 if (table_size[TCAM_PARTITION_FWD_IP4_UCAST_WIDE] || 262 table_size[TCAM_PARTITION_FWD_IP4]) { 263 partitions[TCAM_PARTITION_FWD_IP4_UCAST].flags |= 264 TCAM_PARTITION_FLAGS_COALESCE; 265 } 266 } 267 if (table_size[TCAM_PARTITION_FWD_IP4_UCAST_WIDE]) { 268 if (table_size[TCAM_PARTITION_FWD_IP4]) { 269 partitions[TCAM_PARTITION_FWD_IP4_UCAST_WIDE].flags |= 270 TCAM_PARTITION_FLAGS_COALESCE; 271 } 272 } 273 if (table_size[TCAM_PARTITION_FWD_IP6_128_UCAST]) { 274 if (table_size[TCAM_PARTITION_FWD_IP6_128_UCAST_WIDE] || 275 table_size[TCAM_PARTITION_FWD_IP6]) { 276 partitions[TCAM_PARTITION_FWD_IP6_128_UCAST].flags |= 277 TCAM_PARTITION_FLAGS_COALESCE; 278 } 279 } 280 if (table_size[TCAM_PARTITION_FWD_IP6_128_UCAST_WIDE]) { 281 if (table_size[TCAM_PARTITION_FWD_IP6]) { 282 partitions[TCAM_PARTITION_FWD_IP6_128_UCAST_WIDE].flags |= 283 TCAM_PARTITION_FLAGS_COALESCE; 284 } 285 } 286 287 /* get l2 acl mode. Default to non NL7K mode */ 288 tcam_info->mode = soc_property_get(unit, spn_EXT_TCAM_MODE, 0); 289 290 /* configure associated data information here */ 291 SET_TCAM_PARTITION_AD_INFO(TCAM_PARTITION_FWD_L2, 0, 0, 0, 292 ext_l2_bulk_enable, ext_l2_hit_bit_enable, 293 TCAM_PARTITION_FLAGS_TYPE_L2); 294 295 SET_TCAM_PARTITION_AD_INFO(TCAM_PARTITION_FWD_L2_WIDE, 0, 1, 0, 296 ext_l2_bulk_enable, ext_l2_hit_bit_enable, 297 TCAM_PARTITION_FLAGS_TYPE_L2); 298 299 SET_TCAM_PARTITION_AD_INFO(TCAM_PARTITION_FWD_L2_DUP, 0, 0, 0, 300 0, 0, 301 TCAM_PARTITION_FLAGS_NO_AD); 302 303 SET_TCAM_PARTITION_AD_INFO(TCAM_PARTITION_FWD_IP4_UCAST, 0, 0, 304 ET_PA_AD_L3_ENTRY_UCAST, 0, 305 ext_l3_hit_bit_enable, 306 TCAM_PARTITION_FLAGS_TYPE_L3); 307 308 SET_TCAM_PARTITION_AD_INFO(TCAM_PARTITION_FWD_IP4_UCAST_WIDE, 0, 3, 309 ET_PA_AD_L3_ENTRY_UCAST, 0, 310 ext_l3_hit_bit_enable, 311 TCAM_PARTITION_FLAGS_TYPE_L3); 312 313 SET_TCAM_PARTITION_AD_INFO(TCAM_PARTITION_FWD_IP4, 0, 0, 314 ET_PA_AD_L3_ENTRY_DEFIP, 0, 315 ext_l3_hit_bit_enable, 316 TCAM_PARTITION_FLAGS_TYPE_L3); 317 318 SET_TCAM_PARTITION_AD_INFO(TCAM_PARTITION_FWD_IP4_DUP, 0, 0, 0, 319 0, 0, 320 TCAM_PARTITION_FLAGS_NO_AD); 321 322 SET_TCAM_PARTITION_AD_INFO(TCAM_PARTITION_FWD_IP6U, 0, 0, 323 ET_PA_AD_L3_ENTRY_DEFIP, 0, 324 ext_l3_hit_bit_enable, 325 TCAM_PARTITION_FLAGS_TYPE_L3); 326 327 SET_TCAM_PARTITION_AD_INFO(TCAM_PARTITION_FWD_IP6U_DUP, 0, 0, 0, 328 0, 0, 329 TCAM_PARTITION_FLAGS_NO_AD); 330 331 SET_TCAM_PARTITION_AD_INFO(TCAM_PARTITION_FWD_IP6_128_UCAST, 1, 0, 332 ET_PA_AD_L3_ENTRY_UCAST, 0, 333 ext_l3_hit_bit_enable, 334 TCAM_PARTITION_FLAGS_TYPE_L3); 335 336 SET_TCAM_PARTITION_AD_INFO(TCAM_PARTITION_FWD_IP6_128_UCAST_WIDE, 1, 3, 337 ET_PA_AD_L3_ENTRY_UCAST, 0, 338 ext_l3_hit_bit_enable, 339 TCAM_PARTITION_FLAGS_TYPE_L3); 340 341 SET_TCAM_PARTITION_AD_INFO(TCAM_PARTITION_FWD_IP6, 1, 0, 342 ET_PA_AD_L3_ENTRY_DEFIP, 0, 343 ext_l3_hit_bit_enable, 344 TCAM_PARTITION_FLAGS_TYPE_L3); 345 346 SET_TCAM_PARTITION_AD_INFO(TCAM_PARTITION_FWD_IP6_DUP, 0, 0, 0, 347 0, 0, 348 TCAM_PARTITION_FLAGS_NO_AD); 349 350 SET_TCAM_PARTITION_AD_INFO(TCAM_PARTITION_ACL80, 0, 351 ext_acl80_policy_width, 0, 0, 352 0, TCAM_PARTITION_FLAGS_TYPE_ACL); 353 354 SET_TCAM_PARTITION_AD_INFO(TCAM_PARTITION_ACL160, 1, 355 ext_acl160_policy_width, 0, 0, 356 0, TCAM_PARTITION_FLAGS_TYPE_ACL); 357 358 SET_TCAM_PARTITION_AD_INFO(TCAM_PARTITION_ACL320, 2, 359 ext_acl320_policy_width, 0, 0, 360 0, TCAM_PARTITION_FLAGS_TYPE_ACL); 361 362 SET_TCAM_PARTITION_AD_INFO(TCAM_PARTITION_ACL480, 3, 363 ext_acl480_policy_width, 0, 0, 364 0, TCAM_PARTITION_FLAGS_TYPE_ACL); 365 366 /* TR2 type ACLs: */ 367 /* policy width is 0-based internally */ 368 ext_policy_width = soc_property_get(unit, 369 spn_EXT_L2_ACL_TABLE_POLICY_WIDTH, 1); 370 SET_TCAM_PARTITION_AD_INFO(TCAM_PARTITION_ACL_L2, 2, 371 ext_policy_width - 1, 0, 0, 372 0, TCAM_PARTITION_FLAGS_TYPE_ACL); 373 374 ext_policy_width = soc_property_get(unit, 375 spn_EXT_IP4_ACL_TABLE_POLICY_WIDTH, 1); 376 SET_TCAM_PARTITION_AD_INFO(TCAM_PARTITION_ACL_IP4, 2, 377 ext_policy_width - 1, 0, 0, 378 0, TCAM_PARTITION_FLAGS_TYPE_ACL); 379 380 ext_policy_width = soc_property_get(unit, 381 spn_EXT_IP6S_ACL_TABLE_POLICY_WIDTH, 1); 382 SET_TCAM_PARTITION_AD_INFO(TCAM_PARTITION_ACL_IP6S, 3, 383 ext_policy_width - 1, 0, 0, 384 0, TCAM_PARTITION_FLAGS_TYPE_ACL); 385 386 ext_policy_width = soc_property_get(unit, 387 spn_EXT_IP6F_ACL_TABLE_POLICY_WIDTH, 1); 388 SET_TCAM_PARTITION_AD_INFO(TCAM_PARTITION_ACL_IP6F, 3, 389 ext_policy_width - 1, 0, 0, 390 0, TCAM_PARTITION_FLAGS_TYPE_ACL); 391 392 ext_policy_width = soc_property_get(unit, 393 spn_EXT_L2C_ACL_TABLE_POLICY_WIDTH, 1); 394 SET_TCAM_PARTITION_AD_INFO(TCAM_PARTITION_ACL_L2C, 1, 395 ext_policy_width - 1, 0, 0, 396 0, TCAM_PARTITION_FLAGS_TYPE_ACL); 397 398 ext_policy_width = soc_property_get(unit, 399 spn_EXT_IP4C_ACL_TABLE_POLICY_WIDTH, 1); 400 SET_TCAM_PARTITION_AD_INFO(TCAM_PARTITION_ACL_IP4C, 1, 401 ext_policy_width - 1, 0, 0, 402 0, TCAM_PARTITION_FLAGS_TYPE_ACL); 403 404 ext_policy_width = soc_property_get(unit, 405 spn_EXT_IP6C_ACL_TABLE_POLICY_WIDTH, 1); 406 SET_TCAM_PARTITION_AD_INFO(TCAM_PARTITION_ACL_IP6C, 1, 407 ext_policy_width - 1, 0, 0, 408 0, TCAM_PARTITION_FLAGS_TYPE_ACL); 409 410 ext_policy_width = soc_property_get(unit, 411 spn_EXT_L2IP4_ACL_TABLE_POLICY_WIDTH,1); 412 SET_TCAM_PARTITION_AD_INFO(TCAM_PARTITION_ACL_L2IP4, 2, 413 ext_policy_width - 1, 0, 0, 414 0, TCAM_PARTITION_FLAGS_TYPE_ACL); 415 416 ext_policy_width = soc_property_get(unit, 417 spn_EXT_L2IP6_ACL_TABLE_POLICY_WIDTH, 1); 418 SET_TCAM_PARTITION_AD_INFO(TCAM_PARTITION_ACL_L2IP6, 3, 419 ext_policy_width - 1, 0, 0, 420 0, TCAM_PARTITION_FLAGS_TYPE_ACL); 421 422 423 /* get tcams' mdio port ids */ 424 tcam_info->mdio_port_tcam0 = soc_property_suffix_num_get(unit, 0, 425 spn_PORT_PHY_ADDR, "ext_tcam", 1); 426 tcam_info->mdio_port_tcam1 = soc_property_suffix_num_get(unit, 1, 427 spn_PORT_PHY_ADDR, "ext_tcam", 2); 428 return SOC_E_NONE; 429 } 430 431 /* 432 * Calculate the AD memory size requirements for L2, L3 and ACL, so ISM can 433 * allocate this memory for ESM 434 */ 435 int soc_tr3_esm_get_ism_mem_size(int unit, uint32 mem_type, uint32 *size) 436 { 437 soc_tcam_info_t *tcam_info; 438 uint32 num_ad_entries = 0; 439 440 if (size == NULL) { 441 return SOC_E_PARAM; 442 } 443 444 tcam_info = SOC_CONTROL(unit)->tcam_info; 445 if (tcam_info == NULL) { 446 *size = 0; 447 return SOC_E_NONE; 448 } 449 switch (mem_type) { 450 case SOC_ISM_MEM_ESM_L2: 451 num_ad_entries = tcam_info->partitions[TCAM_PARTITION_FWD_L2].num_entries 452 + 2 * tcam_info->partitions[TCAM_PARTITION_FWD_L2_WIDE].num_entries; 453 break; 454 case SOC_ISM_MEM_ESM_L3: 455 num_ad_entries = 456 tcam_info->partitions[TCAM_PARTITION_FWD_IP4_UCAST].num_entries 457 + 4 * tcam_info->partitions[TCAM_PARTITION_FWD_IP4_UCAST_WIDE].num_entries 458 + tcam_info->partitions[TCAM_PARTITION_FWD_IP4].num_entries 459 + tcam_info->partitions[TCAM_PARTITION_FWD_IP6U].num_entries 460 + tcam_info->partitions[TCAM_PARTITION_FWD_IP6_128_UCAST].num_entries 461 +4*tcam_info->partitions[TCAM_PARTITION_FWD_IP6_128_UCAST_WIDE].num_entries 462 + tcam_info->partitions[TCAM_PARTITION_FWD_IP6].num_entries; 463 break; 464 case SOC_ISM_MEM_ESM_ACL: 465 num_ad_entries = 466 tcam_info->partitions[TCAM_PARTITION_ACL80].num_entries * 467 (tcam_info->partitions[TCAM_PARTITION_ACL80].ad_info.ad_width + 1) + 468 tcam_info->partitions[TCAM_PARTITION_ACL160].num_entries * 469 (tcam_info->partitions[TCAM_PARTITION_ACL160].ad_info.ad_width + 1) + 470 tcam_info->partitions[TCAM_PARTITION_ACL320].num_entries * 471 (tcam_info->partitions[TCAM_PARTITION_ACL320].ad_info.ad_width + 1) + 472 tcam_info->partitions[TCAM_PARTITION_ACL480].num_entries * 473 (tcam_info->partitions[TCAM_PARTITION_ACL480].ad_info.ad_width + 1) + 474 tcam_info->partitions[TCAM_PARTITION_ACL_L2C].num_entries * 475 (tcam_info->partitions[TCAM_PARTITION_ACL_L2C].ad_info.ad_width + 1)+ 476 tcam_info->partitions[TCAM_PARTITION_ACL_IP4C].num_entries * 477 (tcam_info->partitions[TCAM_PARTITION_ACL_IP4C].ad_info.ad_width +1)+ 478 tcam_info->partitions[TCAM_PARTITION_ACL_IP6C].num_entries * 479 (tcam_info->partitions[TCAM_PARTITION_ACL_IP6C].ad_info.ad_width +1)+ 480 tcam_info->partitions[TCAM_PARTITION_ACL_L2].num_entries * 481 (tcam_info->partitions[TCAM_PARTITION_ACL_L2].ad_info.ad_width +1)+ 482 tcam_info->partitions[TCAM_PARTITION_ACL_IP4].num_entries * 483 (tcam_info->partitions[TCAM_PARTITION_ACL_IP4].ad_info.ad_width +1)+ 484 tcam_info->partitions[TCAM_PARTITION_ACL_L2IP4].num_entries * 485 (tcam_info->partitions[TCAM_PARTITION_ACL_L2IP4].ad_info.ad_width+1)+ 486 tcam_info->partitions[TCAM_PARTITION_ACL_IP6S].num_entries * 487 (tcam_info->partitions[TCAM_PARTITION_ACL_IP6S].ad_info.ad_width+1)+ 488 tcam_info->partitions[TCAM_PARTITION_ACL_IP6F].num_entries * 489 (tcam_info->partitions[TCAM_PARTITION_ACL_IP6F].ad_info.ad_width+1)+ 490 tcam_info->partitions[TCAM_PARTITION_ACL_L2IP6].num_entries * 491 (tcam_info->partitions[TCAM_PARTITION_ACL_L2IP6].ad_info.ad_width+1); 492 493 if (SAL_BOOT_QUICKTURN || SAL_BOOT_SIMULATION) { 494 /* running close to full, increase to avoid spillover */ 495 num_ad_entries *= 4; 496 } 497 break; 498 default: 499 *size = 0; 500 return SOC_E_PARAM; 501 } 502 *size = ((num_ad_entries + 11)/12 + 1023)/1024; 503 /* ESM can only use ISM banks of size min 4K. Align size to 4K boundary */ 504 if (*size) { 505 /* Alignment needed only when the *size is not at 4 boundary */ 506 if (((*size)%4) != 0) { 507 *size += (4 - (*size)%4); 508 } 509 *size *= 1024; 510 } 511 return SOC_E_NONE; 512 } 513 514 uint32 tr3_tcam_access_debug=0; 515 uint32 tr3_tcam_sim =0; 516 517 /* dbus is always 80 bytes, i.e, 20 words */ 518 /* ibus is one word per tcam */ 519 int 520 soc_triumph3_tcam_access(int unit, int op_type, int num_inst, int num_pre_nop, 521 int num_post_nop, uint32 *dbus, int *ibus, 522 int num_bits, int num_rsps) 523 { 524 int j, retry; 525 int eop_val; 526 int num_long_words, rv; 527 uint32 tcam_raw_control_word=0; 528 uint32 *start_word; 529 uint32 status; /* status2=0, status3=0; */ 530 etu_tx_raw_req_data_word_entry_t etu_data; 531 etu_dbg_rx_raw_rsp_entry_t raw_rsp; 532 int raw_data_fields[10] = {DW0f, DW1f, DW2f, DW3f, DW4f, DW5f, DW6f, DW7f, 533 DW8f, DW9f}; 534 535 /* dbus data maps to data words and ibus data maps to control word for 536 * nl11k 537 */ 538 539 /* clear start and complete bits in raw_req first */ 540 rv = READ_ETU_TX_RAW_REQ_CONTROL_WORDr(unit, &tcam_raw_control_word); 541 SOC_IF_ERROR_RETURN(rv); 542 soc_reg_field_set(unit, ETU_TX_RAW_REQ_CONTROL_WORDr, 543 &tcam_raw_control_word, COMPLETEf, 0); 544 soc_reg_field_set(unit, ETU_TX_RAW_REQ_CONTROL_WORDr, 545 &tcam_raw_control_word, STARTf, 0); 546 rv = WRITE_ETU_TX_RAW_REQ_CONTROL_WORDr(unit, tcam_raw_control_word); 547 SOC_IF_ERROR_RETURN(rv); 548 549 #if 1 550 if (tr3_tcam_access_debug) { 551 LOG_CLI((BSL_META_U(unit, 552 "initial ETU_SBUS_CMD_ERR register state:\n"))); 553 SOC_IF_ERROR_RETURN(READ_ETU_SBUS_CMD_ERR_INFO1r(unit, &status)); 554 LOG_CLI((BSL_META_U(unit, 555 "ETU_SBUS_CMD_ERR_INFO1:0x%08x\n"), status)); 556 SOC_IF_ERROR_RETURN(READ_ETU_SBUS_CMD_ERR_INFO2r(unit, &status)); 557 LOG_CLI((BSL_META_U(unit, 558 "ETU_SBUS_CMD_ERR_INFO2:0x%08x\n"), status)); 559 } 560 #endif 561 562 /* num_inst is always 1 */ 563 /* put data words into raw data words.*/ 564 start_word = dbus; 565 for (j = 0; j < 10; j++) { 566 soc_mem_field_set(unit, ETU_TX_RAW_REQ_DATA_WORDm, (uint32 *)&etu_data, 567 raw_data_fields[j], start_word); 568 start_word += 2; 569 } 570 SOC_IF_ERROR_RETURN(soc_mem_write(unit, ETU_TX_RAW_REQ_DATA_WORDm, 571 MEM_BLOCK_ALL, 0, &etu_data)); 572 573 #if 1 574 if (tr3_tcam_access_debug) { 575 LOG_CLI((BSL_META_U(unit, 576 "after dw wr ETU_SBUS_CMD_ERR register state:\n"))); 577 SOC_IF_ERROR_RETURN(READ_ETU_SBUS_CMD_ERR_INFO1r(unit, &status)); 578 LOG_CLI((BSL_META_U(unit, 579 "ETU_SBUS_CMD_ERR_INFO1:0x%08x\n"), status)); 580 SOC_IF_ERROR_RETURN(READ_ETU_SBUS_CMD_ERR_INFO2r(unit, &status)); 581 LOG_CLI((BSL_META_U(unit, 582 "ETU_SBUS_CMD_ERR_INFO2:0x%08x\n"), status)); 583 } 584 #endif 585 /* put control word into raw control words => set start bit */ 586 587 /* set CAPTURE bit */ 588 soc_reg_field_set(unit, ETU_TX_RAW_REQ_CONTROL_WORDr, 589 &tcam_raw_control_word, CAPTUREf, 1); 590 /* nl11k opcode */ 591 soc_reg_field_set(unit, ETU_TX_RAW_REQ_CONTROL_WORDr, 592 &tcam_raw_control_word, OPCf, ibus[0]); 593 594 /* num nops */ 595 if (num_pre_nop) { 596 soc_reg_field_set(unit, ETU_TX_RAW_REQ_CONTROL_WORDr, 597 &tcam_raw_control_word, NUM_NOPf, num_pre_nop); 598 soc_reg_field_set(unit, ETU_TX_RAW_REQ_CONTROL_WORDr, 599 &tcam_raw_control_word, NOP_PRE_PSTf, 1); 600 } else if (num_post_nop) { 601 soc_reg_field_set(unit, ETU_TX_RAW_REQ_CONTROL_WORDr, 602 &tcam_raw_control_word, NUM_NOPf, num_post_nop); 603 soc_reg_field_set(unit, ETU_TX_RAW_REQ_CONTROL_WORDr, 604 &tcam_raw_control_word, NOP_PRE_PSTf, 0); 605 } else { 606 soc_reg_field_set(unit, ETU_TX_RAW_REQ_CONTROL_WORDr, 607 &tcam_raw_control_word, NUM_NOPf, 0); 608 } 609 610 /* number of datawords */ 611 num_long_words = (num_bits + 63)/64; 612 soc_reg_field_set(unit, ETU_TX_RAW_REQ_CONTROL_WORDr, 613 &tcam_raw_control_word, NUM_DWf, num_long_words); 614 615 /* EOP field. Assume modul0 8 bytes */ 616 if ((op_type == TCAM_TR3_OP_REG_DB_X_READ)||(op_type==TCAM_TR3_OP_WRITE)|| 617 (op_type == TCAM_TR3_OP_CB_WR_CMP1)||(op_type==TCAM_TR3_OP_CB_WR_CMP2)){ 618 eop_val = 8; 619 } else { 620 eop_val = ((num_bits % 64) + 7)/8; 621 if (eop_val == 0) eop_val = 8; 622 } 623 soc_reg_field_set(unit, ETU_TX_RAW_REQ_CONTROL_WORDr, 624 &tcam_raw_control_word, EOPf, eop_val); 625 626 /* Number of response indices */ 627 #ifdef not_def 628 if ((op_type == TCAM_TR_OP_SINGLE_SEARCH1) || 629 (op_type == TCAM_TR_OP_SINGLE_SEARCH0)) { 630 soc_reg_field_set(unit, ETU_TX_RAW_REQ_CONTROL_WORDr, 631 &tcam_raw_control_word, TOTAL_NUM_RSPf, 1); 632 } else if (op_type == TCAM_TR_OP_PARALLEL_SEARCH) { 633 soc_reg_field_set(unit, ETU_TX_RAW_REQ_CONTROL_WORDr, 634 &tcam_raw_control_word, TOTAL_NUM_RSPf, 4); 635 } else { 636 soc_reg_field_set(unit, ETU_TX_RAW_REQ_CONTROL_WORDr, 637 &tcam_raw_control_word, TOTAL_NUM_RSPf, 0); 638 } 639 #endif 640 soc_reg_field_set(unit, ETU_TX_RAW_REQ_CONTROL_WORDr, 641 &tcam_raw_control_word, TOTAL_NUM_RSPf, num_rsps); 642 643 /* not using the optimization of endian flipping */ 644 soc_reg_field_set(unit, ETU_TX_RAW_REQ_CONTROL_WORDr, 645 &tcam_raw_control_word, NOT_SEARCHf, 1); 646 647 /* complete flag */ 648 soc_reg_field_set(unit, ETU_TX_RAW_REQ_CONTROL_WORDr, 649 &tcam_raw_control_word, COMPLETEf, 0); 650 651 /* start flag */ 652 soc_reg_field_set(unit, ETU_TX_RAW_REQ_CONTROL_WORDr, 653 &tcam_raw_control_word, STARTf, 1); 654 655 /* start the tcam operation */ 656 rv = WRITE_ETU_TX_RAW_REQ_CONTROL_WORDr(unit, tcam_raw_control_word); 657 658 #if 1 659 if (tr3_tcam_access_debug) { 660 LOG_CLI((BSL_META_U(unit, 661 "after 1st cw wr ETU_SBUS_CMD_ERR register state:\n"))); 662 SOC_IF_ERROR_RETURN(READ_ETU_SBUS_CMD_ERR_INFO1r(unit, &status)); 663 LOG_CLI((BSL_META_U(unit, 664 "ETU_SBUS_CMD_ERR_INFO1:0x%08x\n"), status)); 665 SOC_IF_ERROR_RETURN(READ_ETU_SBUS_CMD_ERR_INFO2r(unit, &status)); 666 LOG_CLI((BSL_META_U(unit, 667 "ETU_SBUS_CMD_ERR_INFO2:0x%08x\n"), status)); 668 } 669 #endif 670 671 /* check if operation completed */ 672 if (SOC_SUCCESS(rv)) { 673 for (retry = 2000; retry; retry--) { 674 rv = READ_ETU_TX_RAW_REQ_CONTROL_WORDr(unit, &tcam_raw_control_word); 675 if (tr3_tcam_access_debug) { 676 LOG_CLI((BSL_META_U(unit, 677 "ETU_TX_RAW_REQ_CONTROL_WORD readback: 0x%08x\n"), 678 tcam_raw_control_word)); 679 } 680 if (SOC_FAILURE(rv)) { 681 break; 682 } 683 #if 0 684 if (soc_reg_field_get(unit, ETU_GLOBAL_INTR_STSr, status, 685 TX_RAW_REQ_DONEf)) { 686 break; 687 } 688 #else 689 if (soc_reg_field_get(unit, ETU_TX_RAW_REQ_CONTROL_WORDr, tcam_raw_control_word, 690 COMPLETEf)) { 691 break; 692 } 693 #endif 694 if(tr3_tcam_sim) { 695 sal_usleep(1); 696 } else { 697 sal_udelay(5); 698 } 699 } 700 if (!retry) { 701 LOG_CLI((BSL_META_U(unit, 702 "soc_triumph3_tcam_access: Instruction timeout\n"))); 703 if (tr3_tcam_sim) { return SOC_E_NONE; } 704 rv = SOC_E_TIMEOUT; 705 } 706 rv = READ_ETU_GLOBAL_INTR_STSr(unit, &status); 707 if (tr3_tcam_access_debug) { 708 LOG_CLI((BSL_META_U(unit, 709 "ETU_GLOBAL_INTR_STS: 0x%08x\n"), status)); 710 } 711 if (!(soc_reg_field_get(unit, ETU_GLOBAL_INTR_STSr, status, TX_RAW_REQ_DONEf))) rv = SOC_E_FAIL; 712 #if 0 713 else { 714 soc_reg_field_set(unit, ETU_GLOBAL_INTR_STSr, &status, TX_RAW_REQ_DONEf, 0); 715 if (status) { 716 SOC_IF_ERROR_RETURN(READ_ETU_SBUS_CMD_ERR_INFO1r(unit, &status3)); 717 if (tr3_tcam_access_debug) { 718 LOG_CLI((BSL_META_U(unit, 719 "ETU_SBUS_CMD_ERR_INFO1:0x%08x\n"), status3)); 720 } 721 SOC_IF_ERROR_RETURN(READ_ETU_SBUS_CMD_ERR_INFO2r(unit, &status3)); 722 if (tr3_tcam_access_debug) { 723 LOG_CLI((BSL_META_U(unit, 724 "ETU_SBUS_CMD_ERR_INFO2:0x%08x\n"), status3)); 725 } 726 727 rv = SOC_E_FAIL; 728 } 729 /* prepare to clear corresponding bit in ETU_GLOBAL_INTR_CLEAR */ 730 soc_reg_field_set(unit, ETU_GLOBAL_INTR_STSr, &status2, TX_RAW_REQ_DONEf, 1); 731 SOC_IF_ERROR_RETURN(WRITE_ETU_GLOBAL_INTR_CLEARr(unit, status2)); 732 } 733 #endif 734 } 735 736 /* return responses */ 737 SOC_IF_ERROR_RETURN(soc_mem_read(unit, ETU_DBG_RX_RAW_RSPm, MEM_BLOCK_ANY, 738 0, &raw_rsp)); 739 /* order of fields seems to vary from one regsfile to another */ 740 #if 1 741 soc_mem_field_get(unit, ETU_DBG_RX_RAW_RSPm, (uint32 *) &raw_rsp, DW0f, 742 &dbus[0]); 743 soc_mem_field_get(unit, ETU_DBG_RX_RAW_RSPm, (uint32 *) &raw_rsp, DW1f, 744 &dbus[2]); 745 #else 746 /* This is going to be the newer regs file. */ 747 soc_mem_field_get(unit, ETU_DBG_RX_RAW_RSPm, (uint32 *) &raw_rsp, DW1f, 748 &dbus[0]); 749 soc_mem_field_get(unit, ETU_DBG_RX_RAW_RSPm, (uint32 *) &raw_rsp, DW0f, 750 &dbus[2]); 751 #endif 752 return SOC_E_NONE; 753 } 754 755 int _soc_write_et_pa_xlat_entry(int unit, int idx, soc_et_pa_xlat_t *entry) 756 { 757 et_pa_xlat_entry_t et_pa_entry; 758 759 sal_memset(&et_pa_entry, 0, sizeof(et_pa_entry)); 760 soc_mem_field32_set(unit, ET_PA_XLATm, (uint32 *) &et_pa_entry, ET_WIDTHf, 761 entry->et_width); 762 soc_mem_field32_set(unit, ET_PA_XLATm, (uint32 *) &et_pa_entry, AD_WIDTHf, 763 entry->ad_width); 764 soc_mem_field32_set(unit, ET_PA_XLATm, (uint32 *) &et_pa_entry, ENTRY_TYPEf, 765 entry->entry_type); 766 soc_mem_field32_set(unit, ET_PA_XLATm, (uint32 *) &et_pa_entry, L2_BULK_ENf, 767 entry->l2_bulk_enable); 768 soc_mem_field32_set(unit, ET_PA_XLATm, (uint32 *) &et_pa_entry, HBIT_ENf, 769 entry->hit_bit_enable); 770 771 soc_mem_field32_set(unit, ET_PA_XLATm, (uint32 *) &et_pa_entry, 772 HBIT_PA_BASEf, entry->hit_bit_pa_base); 773 soc_mem_field32_set(unit, ET_PA_XLATm, (uint32 *) &et_pa_entry, AD_BAf, 774 entry->ad_ba); 775 soc_mem_field32_set(unit, ET_PA_XLATm, (uint32 *) &et_pa_entry, AD_RA_BASEf, 776 entry->ad_ra_base); 777 soc_mem_field32_set(unit, ET_PA_XLATm, (uint32 *) &et_pa_entry, AD_CAf, 778 entry->ad_ca); 779 SOC_IF_ERROR_RETURN(soc_mem_write(unit, ET_PA_XLATm, MEM_BLOCK_ALL, 780 idx, &et_pa_entry)); 781 return SOC_E_NONE; 782 } 783 784 typedef struct esm_key_to_field_ { 785 /* waste one entry, use only 1 to 11 for convenience*/ 786 uint8 esm_key_subtype; 787 uint8 f_selects[12]; 788 uint8 flags_field_not_present; 789 uint8 mux_sel_flags[16]; 790 uint8 total_num_cwords; 791 uint8 rsp_index_count[3]; 792 uint8 eop_cw[3]; 793 uint8 num_dwords_cw[3]; 794 uint8 context_addr_lsb_cw[3]; 795 uint8 opcode_cw[3]; 796 uint8 rsp_index_count_cw[3]; 797 uint8 lookup_type_rsp[4]; 798 uint8 drop_pkt_when_adm_ctl_deny; 799 uint8 optional_cost[3]; 800 uint8 cost_cw[3]; 801 uint8 last_cword_is_optional; 802 uint8 hwtl_exp_rsp_ptr; 803 } esm_key_to_field_t; 804 805 uint32 f_select_field[12] = {0, F1_SELECTf, 0, F3_SELECTf, 806 F4_SELECTf, F5_SELECTf, F6_SELECTf, F7_SELECTf, 807 F8_SELECTf, F9_SELECTf, F10_SELECTf, F11_SELECTf}; 808 uint32 rsp_index_count_field[3] = {RSP_INDEX_COUNT_CW0f, RSP_INDEX_COUNT_CW1f, 809 RSP_INDEX_COUNT_CW2f}; 810 uint32 eop_cw_field[3] = {EOP_CW0f, EOP_CW1f, EOP_CW2f}; 811 uint32 context_addr_lsb_cw_field[3] = {CONTEXT_ADDR_LSB_CW0f, 812 CONTEXT_ADDR_LSB_CW1f, CONTEXT_ADDR_LSB_CW2f}; 813 uint32 num_dwords_field[3] = {NUM_DWORDS_CW0f, NUM_DWORDS_CW1f, NUM_DWORDS_CW2f}; 814 uint32 opcode_cw_field[3] = {OPCODE_CW0f, OPCODE_CW1f, OPCODE_CW2f}; 815 uint32 cost_cw_field[3] = {COST0f, COST1f, COST2f}; 816 uint32 lookup_type_rsp_field[4] = {LOOKUP_TYPE_RSP_0f, LOOKUP_TYPE_RSP_1f, 817 LOOKUP_TYPE_RSP_2f, LOOKUP_TYPE_RSP_3f}; 818 uint32 flags_field[16] = {MUX_SEL_FLAG0f, MUX_SEL_FLAG1f, MUX_SEL_FLAG2f, 819 MUX_SEL_FLAG3f, MUX_SEL_FLAG4f, MUX_SEL_FLAG5f, 820 MUX_SEL_FLAG6f, MUX_SEL_FLAG7f, MUX_SEL_FLAG8f, 821 MUX_SEL_FLAG9f, MUX_SEL_FLAG10f, MUX_SEL_FLAG11f, 822 MUX_SEL_FLAG12f, MUX_SEL_FLAG13f, MUX_SEL_FLAG14f, 823 MUX_SEL_FLAG15f} ; 824 825 int _soc_write_esm_key_id_to_field_map_entry(int unit, int idx, 826 esm_key_to_field_t *key_map) 827 { 828 int i; 829 esm_key_id_to_field_mapper_entry_t key_id; 830 831 sal_memset(&key_id, 0, sizeof(key_id)); 832 833 /* L2 DA, SA as per spreadsheet */ 834 for (i = 1; i < 12; i++) { 835 if (i == 2) continue; 836 soc_mem_field32_set(unit, ESM_KEY_ID_TO_FIELD_MAPPERm, 837 (uint32 *)&key_id, f_select_field[i], 838 key_map->f_selects[i]); 839 } 840 841 if (!key_map->flags_field_not_present) { 842 for (i = 0; i < 16; i++) { 843 soc_mem_field32_set(unit, ESM_KEY_ID_TO_FIELD_MAPPERm, 844 (uint32 *)&key_id, flags_field[i], 845 key_map->mux_sel_flags[i]); 846 } 847 } 848 849 soc_mem_field32_set(unit, ESM_KEY_ID_TO_FIELD_MAPPERm, (uint32 *)&key_id, 850 ESM_KEY_SUBTYPEf, key_map->esm_key_subtype); 851 soc_mem_field32_set(unit, ESM_KEY_ID_TO_FIELD_MAPPERm, (uint32 *)&key_id, 852 FLAGS_FIELD_NOT_PRESENTf, key_map->flags_field_not_present); 853 854 soc_mem_field32_set(unit, ESM_KEY_ID_TO_FIELD_MAPPERm, (uint32 *)&key_id, 855 TOTAL_NUM_CWORDSf, key_map->total_num_cwords); 856 857 for (i = 0; i < 3; i++) { 858 soc_mem_field32_set(unit, ESM_KEY_ID_TO_FIELD_MAPPERm, 859 (uint32 *)&key_id, rsp_index_count_field[i], 860 key_map->rsp_index_count[i]); 861 soc_mem_field32_set(unit, ESM_KEY_ID_TO_FIELD_MAPPERm, 862 (uint32 *)&key_id, eop_cw_field[i], 863 key_map->eop_cw[i]); 864 soc_mem_field32_set(unit, ESM_KEY_ID_TO_FIELD_MAPPERm, 865 (uint32 *)&key_id, context_addr_lsb_cw_field[i], 866 key_map->context_addr_lsb_cw[i]); 867 soc_mem_field32_set(unit, ESM_KEY_ID_TO_FIELD_MAPPERm, 868 (uint32 *)&key_id, num_dwords_field[i], 869 key_map->num_dwords_cw[i]); 870 soc_mem_field32_set(unit, ESM_KEY_ID_TO_FIELD_MAPPERm, 871 (uint32 *)&key_id, opcode_cw_field[i], 872 key_map->opcode_cw[i]); 873 soc_mem_field32_set(unit, ESM_KEY_ID_TO_FIELD_MAPPERm, 874 (uint32 *)&key_id, cost_cw_field[i], 875 key_map->cost_cw[i]); 876 } 877 for (i = 0; i < 4; i++) { 878 soc_mem_field32_set(unit, ESM_KEY_ID_TO_FIELD_MAPPERm, 879 (uint32 *)&key_id, lookup_type_rsp_field[i], 880 key_map->lookup_type_rsp[i]); 881 } 882 soc_mem_field32_set(unit, ESM_KEY_ID_TO_FIELD_MAPPERm, (uint32 *)&key_id, 883 DROP_PKT_WHEN_ADM_CTL_DENYf, 884 key_map->drop_pkt_when_adm_ctl_deny); 885 soc_mem_field32_set(unit, ESM_KEY_ID_TO_FIELD_MAPPERm, (uint32 *)&key_id, 886 HWTL_EXP_RSP_PTRf, key_map->hwtl_exp_rsp_ptr); 887 888 /* update worst case FME */ 889 if ((key_map->cost_cw[0] + key_map->cost_cw[1] + key_map->cost_cw[2]) > 890 (tr3_worst_fme[unit].cost0 + tr3_worst_fme[unit].cost1 + 891 tr3_worst_fme[unit].cost2)) { 892 tr3_worst_fme[unit].cost0 = key_map->cost_cw[0]; 893 tr3_worst_fme[unit].cost1 = key_map->cost_cw[1]; 894 tr3_worst_fme[unit].cost2 = key_map->cost_cw[2]; 895 tr3_worst_fme[unit].idx = idx; 896 } 897 return soc_mem_write(unit, ESM_KEY_ID_TO_FIELD_MAPPERm, MEM_BLOCK_ANY, idx, 898 &key_id); 899 } 900 901 int soc_set_src_trunk_map_esm_srch_priority(int unit, 902 int start_idx, int end_idx, 903 int esm_srch_offset, 904 int esm_srch_priority) 905 { 906 source_trunk_map_table_entry_t *stm_entry; 907 int index, alloc_size, rv; 908 void *buf; 909 910 alloc_size = ((end_idx) - (start_idx) + 1) * sizeof((*(stm_entry))); 911 buf = soc_cm_salloc((unit), alloc_size, "source_trunk_map_table"); 912 913 if (buf == NULL) { 914 return SOC_E_MEMORY; 915 } 916 917 soc_mem_lock(unit, SOURCE_TRUNK_MAP_TABLEm); 918 rv = soc_mem_read_range((unit), (SOURCE_TRUNK_MAP_TABLEm), 919 MEM_BLOCK_ANY, (start_idx), (end_idx), buf); 920 921 if (rv < 0) { 922 soc_cm_sfree((unit), buf); 923 soc_mem_unlock(unit, SOURCE_TRUNK_MAP_TABLEm); 924 return SOC_E_FAIL; 925 } 926 927 for (index = 0; index < (end_idx) - (start_idx) + 1; index++) { 928 (stm_entry) = 929 soc_mem_table_idx_to_pointer((unit), 930 (SOURCE_TRUNK_MAP_TABLEm), 931 source_trunk_map_table_entry_t *, 932 buf, index); 933 934 soc_mem_field32_set((unit), (SOURCE_TRUNK_MAP_TABLEm), (stm_entry), 935 ESM_SEARCH_OFFSETf, (esm_srch_offset)); 936 937 /* port (l2 lookup) always wins */ 938 soc_mem_field32_set((unit), (SOURCE_TRUNK_MAP_TABLEm), (stm_entry), 939 ESM_SEARCH_PRIORITYf, (esm_srch_priority)); 940 } 941 942 rv = soc_mem_write_range((unit), (SOURCE_TRUNK_MAP_TABLEm), MEM_BLOCK_ANY, 943 (start_idx), (end_idx), (void *) buf); 944 soc_cm_sfree((unit), buf); 945 soc_mem_unlock(unit, SOURCE_TRUNK_MAP_TABLEm); 946 947 if (rv < 0) { 948 return SOC_E_FAIL; 949 } 950 951 return SOC_E_NONE; 952 } 953 954 typedef struct esm_pkt_id_tcam_entry_ { 955 uint8 pkt_type; 956 uint32 mask[2]; 957 uint8 l2_2nd_lkup_hit; 958 uint8 l2_1st_lkup_hit; 959 uint8 l3_key_type_2nd_lkup; 960 uint8 l3_key_type_1st_lkup; 961 uint8 l2_key_type_2nd_lkup; 962 uint8 l2_key_type_1st_lkup; 963 uint8 l3_lkup_status; 964 uint8 l2_lkup_type_vlan_or_vfi; 965 uint8 l3_iif_valid; 966 uint8 svp_valid; 967 uint8 udf_payload_id; 968 uint8 my_stn_hit_and_enabled; 969 uint8 tunnel_hit; 970 uint8 tunnel_and_lpbk_type; 971 uint8 l3_type; 972 uint8 l2_payload; 973 uint16 payload_type; 974 uint8 valid; 975 } esm_pkt_id_tcam_entry_t; 976 977 int soc_set_pkt_id_tcam_entry(int unit, int idx, esm_pkt_id_tcam_entry_t *pkt_id) 978 { 979 esm_pkt_type_id_entry_t tcam_entry; 980 981 sal_memset(&tcam_entry, 0, sizeof(tcam_entry)); 982 /* set pkt_id tcam basic L2 search entry to pkt_type 0 */ 983 soc_mem_field32_set(unit, ESM_PKT_TYPE_IDm, &tcam_entry, PACKET_TYPEf, pkt_id->pkt_type); 984 soc_mem_field_set(unit, ESM_PKT_TYPE_IDm, (uint32 *) &tcam_entry, MASKf, 985 pkt_id->mask); 986 soc_mem_field32_set(unit, ESM_PKT_TYPE_IDm, &tcam_entry, 987 L2_SECOND_LOOKUP_HITf, pkt_id->l2_2nd_lkup_hit); 988 soc_mem_field32_set(unit, ESM_PKT_TYPE_IDm, &tcam_entry, 989 L2_FIRST_LOOKUP_HITf, pkt_id->l2_1st_lkup_hit); 990 soc_mem_field32_set(unit, ESM_PKT_TYPE_IDm, &tcam_entry, 991 L3_KEY_TYPE_SECOND_LOOKUPf, pkt_id->l3_key_type_2nd_lkup); 992 soc_mem_field32_set(unit, ESM_PKT_TYPE_IDm, &tcam_entry, 993 L3_KEY_TYPE_FIRST_LOOKUPf, pkt_id->l3_key_type_1st_lkup); 994 soc_mem_field32_set(unit, ESM_PKT_TYPE_IDm, &tcam_entry, 995 L2_KEY_TYPE_SECOND_LOOKUPf, pkt_id->l2_key_type_2nd_lkup); 996 soc_mem_field32_set(unit, ESM_PKT_TYPE_IDm, &tcam_entry, 997 L2_KEY_TYPE_FIRST_LOOKUPf, pkt_id->l2_key_type_1st_lkup); 998 soc_mem_field32_set(unit, ESM_PKT_TYPE_IDm, &tcam_entry, 999 L3_LOOKUP_STATUSf, pkt_id->l3_lkup_status); 1000 soc_mem_field32_set(unit, ESM_PKT_TYPE_IDm, &tcam_entry, 1001 L2_LOOKUP_TYPE_VLAN_OR_VFIf, pkt_id->l2_lkup_type_vlan_or_vfi); 1002 soc_mem_field32_set(unit, ESM_PKT_TYPE_IDm, &tcam_entry, 1003 L3_IIF_VALIDf, pkt_id->l3_iif_valid); 1004 soc_mem_field32_set(unit, ESM_PKT_TYPE_IDm, &tcam_entry, SVP_VALIDf, 1005 pkt_id->svp_valid); 1006 soc_mem_field32_set(unit, ESM_PKT_TYPE_IDm, &tcam_entry, UDF_PAYLOAD_IDf, 1007 pkt_id->udf_payload_id); 1008 soc_mem_field32_set(unit, ESM_PKT_TYPE_IDm, &tcam_entry, 1009 MY_STATION_HIT_AND_ENABLEDf, pkt_id->my_stn_hit_and_enabled); 1010 soc_mem_field32_set(unit, ESM_PKT_TYPE_IDm, &tcam_entry, TUNNEL_HITf, 1011 pkt_id->tunnel_hit); 1012 soc_mem_field32_set(unit, ESM_PKT_TYPE_IDm, &tcam_entry, 1013 TUNNEL_AND_LOOPBACK_TYPEf, pkt_id->tunnel_and_lpbk_type); 1014 soc_mem_field32_set(unit, ESM_PKT_TYPE_IDm, &tcam_entry, L3_TYPEf, 1015 pkt_id->l3_type); 1016 soc_mem_field32_set(unit, ESM_PKT_TYPE_IDm, &tcam_entry, L2_PAYLOADf, 1017 pkt_id->l2_payload); 1018 soc_mem_field32_set(unit, ESM_PKT_TYPE_IDm, &tcam_entry, PAYLOAD_TYPEf, 1019 pkt_id->payload_type); 1020 soc_mem_field32_set(unit, ESM_PKT_TYPE_IDm, &tcam_entry, VALIDf, 1021 pkt_id->valid); 1022 SOC_IF_ERROR_RETURN(soc_mem_write(unit, ESM_PKT_TYPE_IDm, MEM_BLOCK_ANY, 1023 idx, &tcam_entry)); 1024 return SOC_E_NONE; 1025 } 1026 1027 int soc_set_esm_search_profile_range(int unit, int idx_start, int idx_end, 1028 int esm_eligible, int search_key_id) 1029 { 1030 int rv, i, alloc_size; 1031 void *buf; 1032 esm_search_profile_entry_t *profile_entry; 1033 1034 /* 32 entries per search offset */ 1035 alloc_size = (idx_end-idx_start+1) * sizeof(esm_search_profile_entry_t); 1036 buf = soc_cm_salloc(unit, alloc_size, "esm_search_profile_range"); 1037 if (buf == NULL) return SOC_E_MEMORY; 1038 1039 for (i = idx_start; i <= idx_end; i++) { 1040 /* pointer to each entry : */ 1041 profile_entry = soc_mem_table_idx_to_pointer 1042 (unit, ESM_SEARCH_PROFILEm, esm_search_profile_entry_t *, 1043 buf, (i - idx_start)); 1044 soc_mem_field32_set(unit, ESM_SEARCH_PROFILEm, profile_entry, 1045 ESM_ELIGIBLEf, esm_eligible); 1046 soc_mem_field32_set(unit, ESM_SEARCH_PROFILEm, profile_entry, 1047 ESM_SEARCH_KEY_IDf, search_key_id); 1048 } 1049 rv = soc_mem_write_range(unit, ESM_SEARCH_PROFILEm, MEM_BLOCK_ANY, 1050 idx_start, idx_end, (void *) buf); 1051 soc_cm_sfree(unit, buf); 1052 return rv; 1053 } 1054 1055 1056 #ifdef later 1057 int soc_triumph3_esm_test_init(int unit) 1058 { 1059 esm_range_check_entry_t buf, idx_end; 1060 esm_key_to_field_t key_map_l2; 1061 int rv; 1062 1063 soc_mem_field32_set(unit, ESM_RANGE_CHECKm, (uint32 *) buf, 1064 ESM_HWTL_SEARCH_KEYf, 0x1b1b2b2b); 1065 soc_mem_write(unit, ESM_RANGE_CHECKm, MEM_BLOCK_ANY, 1066 21, &buf); 1067 buf[21]=0x1b1b2b2b; buf[20]=0x3b3b4b4b; buf[19]=0x5b4b5b5b; 1068 buf[18]=0x6b6b7b7b; 1069 buf[17]=0x1a1a2a2a; buf[16]=0x3a3a4a4a; buf[15]=0x5a4a5a5a; 1070 buf[14]=0x6a6a7a7a; 1071 buf[13]=0x19192929; buf[12]=0x39394949; buf[11]=0x59495959; 1072 buf[10]=0x69697979; 1073 buf[9]=0x87868584; buf[8]=0x83828180; 1074 buf[7]=0x73727270; 1075 buf[6]=0x63626160; 1076 buf[5]=0x51504140; 1077 buf[4]=0x31302120; 1078 buf[3]=0x1f1e1d1c; buf[2]=0x1b1a1918;buf[1]=0x17161514; 1079 buf[0]=0x13121110; 1080 1081 idx_end = soc_mem_index_max(unit, ESM_RANGE_CHECKm); 1082 1083 rv = soc_mem_write_range(unit, ESM_RANGE_CHECKm, MEM_BLOCK_ANY, 1084 0, idx_end, (void *) buf); 1085 1086 /* one test field mapper entry */ 1087 sal_memset(&key_map_l2, 0, sizeof(key_map_l2)); 1088 1089 key_map_l2.f_selects[11] = F11_HWTL; 1090 key_map_l2.f_selects[8] = F8_HWTL; 1091 key_map_l2.f_selects[6] = F6_HWTL; 1092 key_map_l2.f_selects[4] = F4_HWTL; 1093 key_map_l2.f_selects[3] = F3_HWTL; 1094 key_map_l2.flags_field_not_present = 1; 1095 key_map_l2.total_num_cwords = 2; 1096 key_map_l2.rsp_index_count[0] = 1; 1097 key_map_l2.eop_cw[0] = 8; 1098 key_map_l2.context_addr_lsb_cw[0] = 0; 1099 key_map_l2.num_dwords_cw[0] = 2; 1100 key_map_l2.opcode_cw[0] = (1 << 6) | TR3_LTR_FWD_L2_DA; 1101 key_map_l2.rsp_index_count[1] = 1; 1102 key_map_l2.eop_cw[1] = 8; 1103 key_map_l2.eop_cw[2] = 8; 1104 key_map_l2.context_addr_lsb_cw[1] = 2; 1105 key_map_l2.num_dwords_cw[1] = 2; 1106 key_map_l2.opcode_cw[1] = (1 << 6) | TR3_LTR_FWD_L2_SA; 1107 key_map_l2.lookup_type_rsp[0] = KEY_GEN_RSP_TYPE_L2_DA; 1108 key_map_l2.lookup_type_rsp[1] = KEY_GEN_RSP_TYPE_L2_SA; 1109 key_map_l2.cost_cw[0] = 2; 1110 key_map_l2.cost_cw[1] = 6; 1111 key_map_l2.cost_cw[2] = 4; 1112 key_map_l2.drop_pkt_when_adm_ctl_deny = 1; 1113 key_map_l2.hwtl_exp_rsp_ptr = 127; 1114 /* for test L2 */ 1115 SOC_IF_ERROR_RETURN(_soc_write_esm_key_id_to_field_map_entry(unit, 1116 31, &key_map_l2)); 1117 1118 return rv; 1119 } 1120 #endif 1121 1122 STATIC int 1123 _soc_tr3_set_dup_db_offset(int unit) 1124 { 1125 soc_tcam_info_t *tcam_info; 1126 soc_tcam_partition_t *partitions; 1127 int part, dup_part, dup_db_offset; 1128 uint32 tmp2; 1129 1130 tcam_info = SOC_CONTROL(unit)->tcam_info; 1131 if (tcam_info == NULL) { 1132 return 0; 1133 } 1134 SOC_IF_ERROR_RETURN(READ_ETU_CONFIG0r(unit, &tmp2)); 1135 1136 partitions = tcam_info->partitions; 1137 /* calculate duplicate database offset if there is one */ 1138 part = 0; 1139 dup_part = 0; 1140 dup_db_offset = 0; 1141 if (partitions[TCAM_PARTITION_FWD_L2_DUP].num_entries) { 1142 soc_reg_field_set(unit, ETU_CONFIG0r, &tmp2, DUP_L2f, 1); 1143 part = TCAM_PARTITION_FWD_L2; 1144 dup_part = TCAM_PARTITION_FWD_L2_DUP; 1145 } 1146 if (partitions[TCAM_PARTITION_FWD_IP4_DUP].num_entries) { 1147 soc_reg_field_set(unit, ETU_CONFIG0r, &tmp2, DUP_IPV4f, 1); 1148 if (!part) { 1149 part = TCAM_PARTITION_FWD_IP4_UCAST; 1150 dup_part = TCAM_PARTITION_FWD_IP4_DUP; 1151 } 1152 } 1153 if (partitions[TCAM_PARTITION_FWD_IP6U_DUP].num_entries) { 1154 soc_reg_field_set(unit, ETU_CONFIG0r, &tmp2, DUP_IPV6_64f, 1); 1155 if (!part) { 1156 part = TCAM_PARTITION_FWD_IP6U; 1157 dup_part = TCAM_PARTITION_FWD_IP6U_DUP; 1158 } 1159 } 1160 if (partitions[TCAM_PARTITION_FWD_IP6_DUP].num_entries) { 1161 soc_reg_field_set(unit, ETU_CONFIG0r, &tmp2, DUP_IPV6_128f, 1); 1162 if (!part) { 1163 part = TCAM_PARTITION_FWD_IP6_128_UCAST; 1164 dup_part = TCAM_PARTITION_FWD_IP6_DUP; 1165 } 1166 } 1167 if (part) { 1168 dup_db_offset = partitions[dup_part].tcam_base - 1169 partitions[part].tcam_base; 1170 dup_db_offset >>= 12; 1171 } 1172 soc_reg_field_set(unit, ETU_CONFIG0r, &tmp2, DUP_BLK_OFFSETf, 1173 dup_db_offset); 1174 SOC_IF_ERROR_RETURN(WRITE_ETU_CONFIG0r(unit, tmp2)); 1175 return SOC_E_NONE; 1176 } 1177 1178 #ifdef for_later 1179 /* given a type of lookup, this function returns the appropriate field 1180 * mapper entry offset to be programmed into the search profile table 1181 */ 1182 /* 1. If lookup type is L2, then 1183 if any of the L2 ACL partitions is non0 then return that FM entry. 1184 else return FM offset of L2 only entry. 1185 2. If lookup type is IPV4 then if any of the V4 ACL partitions in non0 1186 then return the FM entry for the first of these. 1187 else return the FM offset of V4 only entry. 1188 3. Same fo V6. with following difference: if v6_64 is configured, then 1189 consider only ACLIP6C partition. If v6_128 is configured then 1190 consider all the ACL IP6 partitions. 1191 1192 This is only one behaviour for one section of the SEARCH_PROFILE table 1193 indexed by src_trunk_map index 1. Index 0 is non-ESM. Other behaviours 1194 can be define at other offsets (e.g, other ACLs for L2/L3) in this 1195 src_trunk_map section of the SEARCH_PROFILE table. Similarly other 1196 behaviours can be defined for other sources (other than src_trunk_map). 1197 */ 1198 int _soc_get_fieldmapper_offset(int unit, int lookup_type) 1199 { 1200 soc_tcam_info_t *tcam_info; 1201 soc_tcam_partition_t *partitions; 1202 int part, default_offset; 1203 1204 tcam_info = SOC_CONTROL(unit)->tcam_info; 1205 if (tcam_info == NULL) { 1206 return SOC_E_INIT; 1207 } 1208 1209 partitions = tcam_info->partitions; 1210 switch (lookup_type) { 1211 case FM_LOOKUP_TYPE_L2: 1212 default_offset = KEY_GEN_OFFSET_L2; 1213 if (partitions[TCAM_PARTITION_ACL_L2C].num_entries) { 1214 default_offset = KEY_GEN_OFFSET_TR2_ACL_L2C; 1215 } else { 1216 default_offset = KEY_GEN_OFFSET_TR2_ACL_L2; 1217 } 1218 break; 1219 case FM_LOOKUP_TYPE_IPV4: 1220 default_offset = KEY_GEN_OFFSET_IPV4_ONLY; 1221 if (partitions[TCAM_PARTITION_ACL_IP4C].num_entries) { 1222 default_offset = KEY_GEN_OFFSET_TR2_ACL_IP4C; 1223 } else if (partitions[TCAM_PARTITION_ACL_IP4].num_entries) { 1224 default_offset = KEY_GEN_OFFSET_TR2_ACL_IP4; 1225 } else if (partitions[TCAM_PARTITION_ACL_L2IP4].num_entries) { 1226 default_offset = KEY_GEN_OFFSET_TR2_ACL_L2IP4; 1227 } 1228 break; 1229 case FM_LOOKUP_TYPE_IPV6: 1230 if (partitions[TCAM_PARTITION_FWD_IP6U].num_entries) { 1231 default_offset = KEY_GEN_OFFSET_IPV6_64_ONLY; 1232 if (partitions[TCAM_PARTITION_ACL_IP6C].num_entries) { 1233 default_offset = KEY_GEN_OFFSET_TR2_ACL_IP6C; 1234 } 1235 } else { 1236 default_offset = KEY_GEN_OFFSET_IPV6_128_ONLY; 1237 if (partitions[TCAM_PARTITION_ACL_IP6S].num_entries) { 1238 default_offset = KEY_GEN_OFFSET_TR2_ACL_IP6S; 1239 } else if (partitions[TCAM_PARTITION_ACL_IP6F].num_entries) { 1240 default_offset = KEY_GEN_OFFSET_TR2_ACL_IP6F; 1241 } else if (partitions[TCAM_PARTITION_ACL_L2IP6].num_entries) { 1242 default_offset = KEY_GEN_OFFSET_TR2_ACL_L2IP6; 1243 } 1244 } 1245 break; 1246 default: 1247 default_offset = KEY_GEN_OFFSET_L2; 1248 } 1249 return default_offset; 1250 } 1251 #endif 1252 1253 STATIC int 1254 _soc_tr3_esm_init_pkt_type_tcam(int unit, soc_tcam_partition_t *partitions) 1255 { 1256 esm_pkt_id_tcam_entry_t l2_entry_id; 1257 1258 if (partitions == NULL) { 1259 return SOC_E_NONE; 1260 } 1261 1262 sal_memset(&l2_entry_id, 0, sizeof(l2_entry_id)); 1263 l2_entry_id.pkt_type = FWD_TYPE_L2_VFI; /* L2 + SVP valid */ 1264 l2_entry_id.l2_lkup_type_vlan_or_vfi = 1; 1265 l2_entry_id.l2_payload = 1; 1266 l2_entry_id.valid = 1; 1267 l2_entry_id.tunnel_and_lpbk_type = 2; 1268 l2_entry_id.mask[1] = 0x0; 1269 l2_entry_id.mask[0] = 0x410000; 1270 SOC_IF_ERROR_RETURN(soc_set_pkt_id_tcam_entry(unit, 1, &l2_entry_id)); 1271 1272 sal_memset(&l2_entry_id, 0, sizeof(l2_entry_id)); 1273 l2_entry_id.pkt_type = FWD_TYPE_L2_VLAN; /* L2 + SGLP valid */ 1274 l2_entry_id.l2_lkup_type_vlan_or_vfi = 0; 1275 l2_entry_id.l2_payload = 1; 1276 l2_entry_id.valid = 1; 1277 l2_entry_id.mask[1] = 0x40; 1278 l2_entry_id.mask[0] = 0x10000; 1279 SOC_IF_ERROR_RETURN(soc_set_pkt_id_tcam_entry(unit, 2, &l2_entry_id)); 1280 1281 /* create an SVP valid variant */ 1282 l2_entry_id.pkt_type = FWD_TYPE_L2_VFI; /* L2 + SVP valid */ 1283 l2_entry_id.l2_lkup_type_vlan_or_vfi = 1; 1284 SOC_IF_ERROR_RETURN(soc_set_pkt_id_tcam_entry(unit, 3, &l2_entry_id)); 1285 1286 sal_memset(&l2_entry_id, 0, sizeof(l2_entry_id)); 1287 l2_entry_id.pkt_type = FWD_TYPE_L2_VFI; /* L2 + SVP valid */ 1288 l2_entry_id.l2_lkup_type_vlan_or_vfi = 1; 1289 l2_entry_id.l2_payload = 0; 1290 l2_entry_id.valid = 1; 1291 l2_entry_id.tunnel_and_lpbk_type = 2; 1292 l2_entry_id.mask[1] = 0x40; 1293 l2_entry_id.mask[0] = 0x410000; 1294 SOC_IF_ERROR_RETURN(soc_set_pkt_id_tcam_entry(unit, 4, &l2_entry_id)); 1295 1296 sal_memset(&l2_entry_id, 0, sizeof(l2_entry_id)); 1297 l2_entry_id.pkt_type = FWD_TYPE_V4_BRIDGE; /* IPV4 l2 switching */ 1298 l2_entry_id.l2_payload = 0; 1299 l2_entry_id.l3_type = 0; 1300 l2_entry_id.valid = 1; 1301 l2_entry_id.mask[1] = 0; 1302 l2_entry_id.mask[0] = 0x8190000; 1303 SOC_IF_ERROR_RETURN(soc_set_pkt_id_tcam_entry(unit, 5, &l2_entry_id)); 1304 1305 sal_memset(&l2_entry_id, 0, sizeof(l2_entry_id)); 1306 l2_entry_id.pkt_type = FWD_TYPE_V6_BRIDGE; /* V6 l2 switching */ 1307 l2_entry_id.l2_payload = 0; 1308 l2_entry_id.l3_type = 4; 1309 l2_entry_id.valid = 1; 1310 l2_entry_id.mask[1] = 0; 1311 l2_entry_id.mask[0] = 0x8190000; 1312 SOC_IF_ERROR_RETURN(soc_set_pkt_id_tcam_entry(unit, 6, &l2_entry_id)); 1313 1314 sal_memset(&l2_entry_id, 0, sizeof(l2_entry_id)); 1315 l2_entry_id.pkt_type = FWD_TYPE_V4_ROUTE; /* IPV4 */ 1316 l2_entry_id.l2_payload = 0; 1317 l2_entry_id.l3_type = 0; 1318 l2_entry_id.valid = 1; 1319 l2_entry_id.my_stn_hit_and_enabled = 1; 1320 l2_entry_id.mask[1] = 0; 1321 l2_entry_id.mask[0] = 0x8190000; 1322 SOC_IF_ERROR_RETURN(soc_set_pkt_id_tcam_entry(unit, 7, &l2_entry_id)); 1323 1324 sal_memset(&l2_entry_id, 0, sizeof(l2_entry_id)); 1325 l2_entry_id.pkt_type = FWD_TYPE_V6_ROUTE; /* V6 128 */ 1326 l2_entry_id.l2_payload = 0; 1327 l2_entry_id.l3_type = 4; 1328 l2_entry_id.valid = 1; 1329 l2_entry_id.my_stn_hit_and_enabled = 1; 1330 l2_entry_id.mask[1] = 0; 1331 l2_entry_id.mask[0] = 0x8190000; 1332 SOC_IF_ERROR_RETURN(soc_set_pkt_id_tcam_entry(unit, 8, &l2_entry_id)); 1333 1334 sal_memset(&l2_entry_id, 0, sizeof(l2_entry_id)); 1335 l2_entry_id.pkt_type = FWD_TYPE_L2_VLAN; /* L2 + SGLP valid */ 1336 l2_entry_id.l2_lkup_type_vlan_or_vfi = 0; 1337 l2_entry_id.l2_payload = 0; 1338 l2_entry_id.valid = 1; 1339 l2_entry_id.mask[1] = 0x40; 1340 l2_entry_id.mask[0] = 0x10000; 1341 SOC_IF_ERROR_RETURN(soc_set_pkt_id_tcam_entry(unit, 9, &l2_entry_id)); 1342 1343 return SOC_E_NONE; 1344 } 1345 1346 /* populate the search profile table for the various sources. Currently 1347 only src_trunk_map source, 2 profiles are populated. There are 6 more 1348 profiles avail. Other sources are all available 1349 */ 1350 STATIC int 1351 _soc_tr3_esm_fill_search_profile(int unit) 1352 { 1353 1354 int rv; 1355 /* profile 0, esm ineligible, which is also default */ 1356 rv = soc_set_esm_search_profile_range(unit, SRCH_PROFILE_SRC_TRUNK_MAP_0, 1357 SRCH_PROFILE_SRC_TRUNK_MAP_0+31, 0, 0); 1358 SOC_IF_ERROR_RETURN(rv); 1359 1360 /* profile 1 for SRC_TRUNK_MAP: */ 1361 rv = soc_set_esm_search_profile_range(unit, SRCH_PROFILE_SRC_TRUNK_MAP_1, 1362 SRCH_PROFILE_SRC_TRUNK_MAP_1, 0, 0); 1363 SOC_IF_ERROR_RETURN(rv); 1364 1365 rv = soc_set_esm_search_profile_range(unit, 1366 SRCH_PROFILE_SRC_TRUNK_MAP_1 + FWD_TYPE_L2_VLAN, 1367 SRCH_PROFILE_SRC_TRUNK_MAP_1+FWD_TYPE_L2_VLAN, 1, 1368 KEY_GEN_OFFSET_L2); 1369 SOC_IF_ERROR_RETURN(rv); 1370 1371 rv = soc_set_esm_search_profile_range(unit, 1372 SRCH_PROFILE_SRC_TRUNK_MAP_1 + FWD_TYPE_L2_VFI, 1373 SRCH_PROFILE_SRC_TRUNK_MAP_1+FWD_TYPE_L2_VFI, 1, KEY_GEN_OFFSET_L2); 1374 SOC_IF_ERROR_RETURN(rv); 1375 1376 rv = soc_set_esm_search_profile_range(unit, 1377 SRCH_PROFILE_SRC_TRUNK_MAP_1 + FWD_TYPE_V4_ROUTE, 1378 SRCH_PROFILE_SRC_TRUNK_MAP_1+FWD_TYPE_V4_ROUTE, 1, KEY_GEN_OFFSET_IPV4_SA); 1379 SOC_IF_ERROR_RETURN(rv); 1380 1381 rv = soc_set_esm_search_profile_range(unit, 1382 SRCH_PROFILE_SRC_TRUNK_MAP_1 + FWD_TYPE_V4_BRIDGE, 1383 SRCH_PROFILE_SRC_TRUNK_MAP_1+FWD_TYPE_V4_BRIDGE, 1, KEY_GEN_OFFSET_L2); 1384 SOC_IF_ERROR_RETURN(rv); 1385 1386 rv = soc_set_esm_search_profile_range(unit, 1387 SRCH_PROFILE_SRC_TRUNK_MAP_1 + FWD_TYPE_V6_ROUTE, 1388 SRCH_PROFILE_SRC_TRUNK_MAP_1+FWD_TYPE_V6_ROUTE, 1, KEY_GEN_OFFSET_IPV6_128_SA); 1389 SOC_IF_ERROR_RETURN(rv); 1390 1391 rv = soc_set_esm_search_profile_range(unit, 1392 SRCH_PROFILE_SRC_TRUNK_MAP_1 + FWD_TYPE_V6_BRIDGE, 1393 SRCH_PROFILE_SRC_TRUNK_MAP_1+FWD_TYPE_V6_BRIDGE, 1, KEY_GEN_OFFSET_L2); 1394 SOC_IF_ERROR_RETURN(rv); 1395 1396 /* 1397 * ESM search profile for KEY_GEN_OFFSET_TR3_WAR_L2SA_ONLY is created for 1398 * Source Mac based ESM lookup thorugh VFP Action 1399 * bcmFieldActionEsmSearchKeySrcMac purpose 1400 */ 1401 rv = soc_set_esm_search_profile_range(unit, 1402 SRCH_PROFILE_SRC_VFP_BASE + 32 + FWD_TYPE_L2_VLAN, 1403 SRCH_PROFILE_SRC_VFP_BASE + 32 + FWD_TYPE_L2_VLAN, 1, 1404 KEY_GEN_OFFSET_TR3_WAR_L2SA_ONLY); 1405 1406 return rv; 1407 } 1408 1409 int 1410 soc_tr3_esm_pkt_type_to_slice_map_set(int unit, int pkt_type, int slice) 1411 { 1412 int offset1, offset2, fwd_type1, fwd_type2, rv; 1413 int fwd_ipv4_present, fwd_l2_present, fwd_ipv6_present; 1414 soc_tcam_info_t *tcam_info; 1415 soc_tcam_partition_t *partitions; 1416 1417 #ifdef LATER 1418 int fwd_ipv6u_present; 1419 #endif 1420 1421 tcam_info = SOC_CONTROL(unit)->tcam_info; 1422 if (tcam_info == NULL) { 1423 return SOC_E_NONE; 1424 } 1425 1426 partitions = tcam_info->partitions; 1427 1428 fwd_l2_present = partitions[TCAM_PARTITION_FWD_L2].num_entries || 1429 partitions[TCAM_PARTITION_FWD_L2_WIDE].num_entries; 1430 fwd_ipv4_present = partitions[TCAM_PARTITION_FWD_IP4].num_entries || 1431 partitions[TCAM_PARTITION_FWD_IP4_UCAST].num_entries || 1432 partitions[TCAM_PARTITION_FWD_IP4_UCAST_WIDE].num_entries; 1433 fwd_ipv6_present = partitions[TCAM_PARTITION_FWD_IP6].num_entries || 1434 partitions[TCAM_PARTITION_FWD_IP6_128_UCAST].num_entries || 1435 partitions[TCAM_PARTITION_FWD_IP6_128_UCAST_WIDE].num_entries; 1436 1437 switch (slice) { 1438 case TCAM_PARTITION_ACL_L2C: 1439 if(!fwd_l2_present) { 1440 offset1 = offset2 = KEY_GEN_OFFSET_TR2_ACL_L2C_ONLY; 1441 } else { 1442 offset1 = offset2 = KEY_GEN_OFFSET_TR2_ACL_L2C; 1443 } 1444 break; 1445 case TCAM_PARTITION_ACL_L2: 1446 if (!fwd_l2_present) { 1447 /* L2 ACL only */ 1448 offset1 = offset2 = KEY_GEN_OFFSET_TR2_ACL_L2_ONLY; 1449 } else if (tcam_info->mode) { 1450 offset1 = KEY_GEN_OFFSET_TR2_ACL_L2_NON7K_SGLP; 1451 offset2 = KEY_GEN_OFFSET_TR2_ACL_L2_NON7K_SVP; 1452 } else { 1453 offset1 = KEY_GEN_OFFSET_TR2_ACL_L2_7K_SGLP; 1454 offset2 = KEY_GEN_OFFSET_TR2_ACL_L2_7K_SVP; 1455 } 1456 break; 1457 case TCAM_PARTITION_ACL_IP4C: 1458 offset1 = fwd_ipv4_present ? KEY_GEN_OFFSET_TR2_ACL_IP4C : 1459 KEY_GEN_OFFSET_TR2_ACL_IP4C_ONLY; 1460 offset2 = fwd_l2_present ? KEY_GEN_OFFSET_TR2_ACL_IP4C_L2 : 1461 KEY_GEN_OFFSET_TR2_ACL_IP4C_ONLY; 1462 break; 1463 case TCAM_PARTITION_ACL_IP4: 1464 offset1 = fwd_ipv4_present ? KEY_GEN_OFFSET_TR2_ACL_IP4 : 1465 KEY_GEN_OFFSET_TR2_ACL_IP4_ONLY; 1466 offset2 = fwd_l2_present ? KEY_GEN_OFFSET_TR2_ACL_IP4_L2 : 1467 KEY_GEN_OFFSET_TR2_ACL_IP4_ONLY; 1468 break; 1469 case TCAM_PARTITION_ACL_L2IP4: 1470 offset1 = fwd_ipv4_present ? KEY_GEN_OFFSET_TR2_ACL_L2IP4 : 1471 KEY_GEN_OFFSET_TR2_ACL_L2IP4_ONLY; 1472 offset2 = fwd_l2_present ? KEY_GEN_OFFSET_TR2_ACL_L2IP4_L2 : 1473 KEY_GEN_OFFSET_TR2_ACL_L2IP4_ONLY; 1474 break; 1475 case TCAM_PARTITION_ACL_IP6C: 1476 offset1 = fwd_ipv6_present ? KEY_GEN_OFFSET_TR2_ACL_IP6C : 1477 KEY_GEN_OFFSET_TR2_ACL_IP6C_ONLY; 1478 offset2 = fwd_l2_present ? KEY_GEN_OFFSET_TR2_ACL_IP6C_L2 : 1479 KEY_GEN_OFFSET_TR2_ACL_IP6C_ONLY; 1480 break; 1481 case TCAM_PARTITION_ACL_IP6S: 1482 offset1 = fwd_ipv6_present ? KEY_GEN_OFFSET_TR2_ACL_IP6S : 1483 KEY_GEN_OFFSET_TR2_ACL_IP6S_ONLY; 1484 offset2 = fwd_l2_present ? KEY_GEN_OFFSET_TR2_ACL_IP6S_L2 : 1485 KEY_GEN_OFFSET_TR2_ACL_IP6S_ONLY; 1486 break; 1487 case TCAM_PARTITION_ACL_IP6F: 1488 offset1 = fwd_ipv6_present ? KEY_GEN_OFFSET_TR2_ACL_IP6F : 1489 KEY_GEN_OFFSET_TR2_ACL_IP6F_ONLY; 1490 offset2 = fwd_l2_present ? KEY_GEN_OFFSET_TR2_ACL_IP6F_L2 : 1491 KEY_GEN_OFFSET_TR2_ACL_IP6F_ONLY; 1492 break; 1493 case TCAM_PARTITION_ACL_L2IP6: 1494 offset1 = fwd_ipv6_present ? KEY_GEN_OFFSET_TR2_ACL_L2IP6 : 1495 KEY_GEN_OFFSET_TR2_ACL_L2IP6_ONLY; 1496 offset2 = fwd_l2_present ? KEY_GEN_OFFSET_TR2_ACL_L2IP6_L2 : 1497 KEY_GEN_OFFSET_TR2_ACL_L2IP6_ONLY; 1498 break; 1499 default: 1500 return SOC_E_PARAM; 1501 } 1502 1503 switch (pkt_type) { 1504 case PKT_TYPE_L2: 1505 fwd_type1 = FWD_TYPE_L2_VLAN; 1506 fwd_type2 = FWD_TYPE_L2_VFI; 1507 break; 1508 case PKT_TYPE_IPV4: 1509 fwd_type1 = FWD_TYPE_V4_ROUTE; 1510 fwd_type2 = FWD_TYPE_V4_BRIDGE; 1511 break; 1512 case PKT_TYPE_IPV6: 1513 fwd_type1 = FWD_TYPE_V6_ROUTE; 1514 fwd_type2 = FWD_TYPE_V6_BRIDGE; 1515 break; 1516 default: 1517 return SOC_E_PARAM; 1518 } 1519 1520 rv = soc_set_esm_search_profile_range(unit, 1521 SRCH_PROFILE_SRC_TRUNK_MAP_1+fwd_type1, 1522 SRCH_PROFILE_SRC_TRUNK_MAP_1+fwd_type1, 1, offset1); 1523 SOC_IF_ERROR_RETURN(rv); 1524 rv = soc_set_esm_search_profile_range(unit, 1525 SRCH_PROFILE_SRC_TRUNK_MAP_1+fwd_type2, 1526 SRCH_PROFILE_SRC_TRUNK_MAP_1+fwd_type2, 1, offset2); 1527 SOC_IF_ERROR_RETURN(rv); 1528 return SOC_E_NONE; 1529 } 1530 1531 /* 1532 * Forwarding key value encoding: 1533 * L2 (always 80-bit) 1534 * IP4 (always 80-bit) 1535 * IP6 (0:80-bit, 1:160-bit) 1536 * ACL key value encoding: 1537 * L2 (0:disable, 1:320-bit, 2:160-bit) 1538 * IP4 (0:disable, 1:320-bit, 2:160-bit, 3:L2+IP4, 4:L2) 1539 * IP6 (0:disable, 1:480-bit, 2:480-bit, 3:160-bit, 4:L2+IP6, 5:L2) 1540 */ 1541 STATIC int 1542 _soc_tr3_esm_init_set_esm_mode_per_port(int unit) 1543 { 1544 soc_tcam_info_t *tcam_info; 1545 soc_tcam_partition_t *partitions; 1546 int fwd_ip6_key, acl_l2_key, acl_ip4_key, acl_ip6_key; 1547 int rv; 1548 int offset1, offset2, l2_fm_offset1 = KEY_GEN_OFFSET_TR2_ACL_L2_7K_SGLP; 1549 int l2_fm_offset2 = KEY_GEN_OFFSET_TR2_ACL_L2_7K_SVP; 1550 int fwd_l2_present, fwd_ipv4_present, fwd_ipv6_present; 1551 int fwd_ipv6u_present; 1552 1553 tcam_info = SOC_CONTROL(unit)->tcam_info; 1554 if (tcam_info == NULL) { 1555 LOG_CLI((BSL_META_U(unit, 1556 "unit %d: tr3_set_esm_mode_per_port: No tcam entries\n"), 1557 unit)); 1558 return SOC_E_NONE; 1559 } 1560 partitions = tcam_info->partitions; 1561 1562 fwd_l2_present = partitions[TCAM_PARTITION_FWD_L2].num_entries || 1563 partitions[TCAM_PARTITION_FWD_L2_WIDE].num_entries; 1564 fwd_ipv4_present = partitions[TCAM_PARTITION_FWD_IP4].num_entries || 1565 partitions[TCAM_PARTITION_FWD_IP4_UCAST].num_entries || 1566 partitions[TCAM_PARTITION_FWD_IP4_UCAST_WIDE].num_entries; 1567 fwd_ipv6_present = partitions[TCAM_PARTITION_FWD_IP6].num_entries || 1568 partitions[TCAM_PARTITION_FWD_IP6_128_UCAST].num_entries || 1569 partitions[TCAM_PARTITION_FWD_IP6_128_UCAST_WIDE].num_entries; 1570 fwd_ipv6u_present = partitions[TCAM_PARTITION_FWD_IP6U].num_entries; 1571 1572 fwd_ip6_key = soc_property_get(unit, spn_EXT_IP6_FWD_KEY, -1); 1573 acl_l2_key = soc_property_get(unit, spn_EXT_L2_ACL_KEY, -1); 1574 acl_ip4_key = soc_property_get(unit, spn_EXT_IP4_ACL_KEY, -1); 1575 acl_ip6_key = soc_property_get(unit, spn_EXT_IP6_ACL_KEY, -1); 1576 1577 /* IP6 FWD key is not specified in config, figure it out from table size */ 1578 if (fwd_ip6_key == -1) { 1579 fwd_ip6_key = 0; /* default 72-bit key (prefix length 64) */ 1580 if (!partitions[TCAM_PARTITION_FWD_IP6U].num_entries) { 1581 if (partitions[TCAM_PARTITION_FWD_IP6].num_entries) { 1582 fwd_ip6_key = 1; /* 144-bit key (prefix length 128) */ 1583 } 1584 } 1585 } 1586 1587 /* L2 ACL key is not specified in config, figure it out from table size */ 1588 if (acl_l2_key == -1) { /* L2 ACL key not specified in config */ 1589 acl_l2_key = 0; /* default disable */ 1590 if (partitions[TCAM_PARTITION_ACL_L2].num_entries) { 1591 acl_l2_key = 1; /* 288-bit key */ 1592 } else if (partitions[TCAM_PARTITION_ACL_L2C].num_entries) { 1593 acl_l2_key = 2; /* 144-bit key */ 1594 } 1595 } 1596 1597 /* IP4 ACL key is not specified in config, figure it out from table size */ 1598 if (acl_ip4_key == -1) { /* IP4 ACL key not specified in config */ 1599 acl_ip4_key = 0; /* default disable */ 1600 if (partitions[TCAM_PARTITION_ACL_IP4].num_entries) { 1601 acl_ip4_key = 1; /* 288-bit key */ 1602 } else if (partitions[TCAM_PARTITION_ACL_IP4C].num_entries) { 1603 acl_ip4_key = 2; /* 144-bit key */ 1604 } else if (partitions[TCAM_PARTITION_ACL_L2IP4].num_entries) { 1605 acl_ip4_key = 3; /* 432-bit L2+L3 key */ 1606 } else if (partitions[TCAM_PARTITION_ACL_L2].num_entries) { 1607 acl_ip4_key = 4; /* 288-bit L2 key */ 1608 } 1609 } 1610 1611 /* IP6 ACL key is not specified in config, figure it out from table size */ 1612 if (acl_ip6_key == -1) { /* IP6 ACL key not specified in config */ 1613 acl_ip6_key = 0; /* default disable */ 1614 if (partitions[TCAM_PARTITION_ACL_IP6S].num_entries) { 1615 acl_ip6_key = 1; /* 360-bit key */ 1616 } else if (partitions[TCAM_PARTITION_ACL_IP6F].num_entries) { 1617 acl_ip6_key = 2; /* 432-bit key */ 1618 } else if (partitions[TCAM_PARTITION_ACL_IP6C].num_entries) { 1619 acl_ip6_key = 3; /* 144-bit key */ 1620 } else if (partitions[TCAM_PARTITION_ACL_L2IP6].num_entries) { 1621 acl_ip6_key = 4; /* 432-bit L2+L3 key */ 1622 } else if (partitions[TCAM_PARTITION_ACL_L2].num_entries) { 1623 acl_ip6_key = 5; /* 288-bit L2 key */ 1624 } 1625 } 1626 1627 if (fwd_ip6_key < 0 || fwd_ip6_key > 1 || 1628 acl_l2_key < 0 || acl_l2_key > 2 || 1629 acl_ip4_key < 0 || acl_ip4_key > 4 || 1630 acl_ip6_key < 0 || acl_ip6_key > 5) { 1631 LOG_ERROR(BSL_LS_SOC_TCAM, 1632 (BSL_META_U(unit, 1633 "ESM init: unit %d incorrect key selection\n"), 1634 unit)); 1635 return SOC_E_PARAM; 1636 } 1637 1638 if (tcam_info->mode) { /* 350 MHz */ 1639 if (acl_ip6_key == 1 || acl_ip6_key == 2) { 1640 acl_ip6_key = 3; 1641 } 1642 l2_fm_offset1 = KEY_GEN_OFFSET_TR2_ACL_L2_NON7K_SGLP; 1643 l2_fm_offset2 = KEY_GEN_OFFSET_TR2_ACL_L2_NON7K_SVP; 1644 } 1645 1646 if (fwd_ip6_key) { 1647 if (fwd_l2_present) { 1648 /* If L2 present, add SA to V6-128*/ 1649 rv = soc_set_esm_search_profile_range(unit, 1650 SRCH_PROFILE_SRC_TRUNK_MAP_1 + FWD_TYPE_V6_ROUTE, 1651 SRCH_PROFILE_SRC_TRUNK_MAP_1 + FWD_TYPE_V6_ROUTE, 1, 1652 KEY_GEN_OFFSET_IPV6_128_SA); 1653 } else { 1654 /* set V6 lookup type to V6-128 */ 1655 rv = soc_set_esm_search_profile_range(unit, 1656 SRCH_PROFILE_SRC_TRUNK_MAP_1 + FWD_TYPE_V6_ROUTE, 1657 SRCH_PROFILE_SRC_TRUNK_MAP_1 + FWD_TYPE_V6_ROUTE, 1, 1658 KEY_GEN_OFFSET_IPV6_128_ONLY); 1659 } 1660 SOC_IF_ERROR_RETURN(rv); 1661 } else { 1662 if (fwd_l2_present) { 1663 /* If L2 present, add SA to V6-64*/ 1664 rv = soc_set_esm_search_profile_range(unit, 1665 SRCH_PROFILE_SRC_TRUNK_MAP_1 + FWD_TYPE_V6_ROUTE, 1666 SRCH_PROFILE_SRC_TRUNK_MAP_1 + FWD_TYPE_V6_ROUTE, 1, 1667 KEY_GEN_OFFSET_IPV6_64_SA); 1668 } else { 1669 rv = soc_set_esm_search_profile_range(unit, 1670 SRCH_PROFILE_SRC_TRUNK_MAP_1 + FWD_TYPE_V6_ROUTE, 1671 SRCH_PROFILE_SRC_TRUNK_MAP_1 + FWD_TYPE_V6_ROUTE, 1, 1672 KEY_GEN_OFFSET_IPV6_64_ONLY); 1673 } 1674 SOC_IF_ERROR_RETURN(rv); 1675 } 1676 if (acl_l2_key) { 1677 if (acl_l2_key == 2) { 1678 /* point to acl_l2c fieldmapper */ 1679 rv = soc_set_esm_search_profile_range(unit, 1680 SRCH_PROFILE_SRC_TRUNK_MAP_1 + FWD_TYPE_L2_VLAN, 1681 SRCH_PROFILE_SRC_TRUNK_MAP_1 + FWD_TYPE_L2_VLAN, 1, 1682 fwd_l2_present ? KEY_GEN_OFFSET_TR2_ACL_L2C : 1683 KEY_GEN_OFFSET_TR2_ACL_L2C_ONLY); 1684 SOC_IF_ERROR_RETURN(rv); 1685 } else { 1686 /* point to acl_l2 fieldmapper */ 1687 rv = soc_set_esm_search_profile_range(unit, 1688 SRCH_PROFILE_SRC_TRUNK_MAP_1 + FWD_TYPE_L2_VLAN, 1689 SRCH_PROFILE_SRC_TRUNK_MAP_1 + FWD_TYPE_L2_VLAN, 1, 1690 fwd_l2_present ? l2_fm_offset1 : 1691 KEY_GEN_OFFSET_TR2_ACL_L2_ONLY); 1692 SOC_IF_ERROR_RETURN(rv); 1693 rv = soc_set_esm_search_profile_range(unit, 1694 SRCH_PROFILE_SRC_TRUNK_MAP_1 + FWD_TYPE_L2_VFI, 1695 SRCH_PROFILE_SRC_TRUNK_MAP_1 + FWD_TYPE_L2_VFI, 1, 1696 fwd_l2_present ? l2_fm_offset2 : 1697 KEY_GEN_OFFSET_TR2_ACL_L2_ONLY); 1698 SOC_IF_ERROR_RETURN(rv); 1699 } 1700 } 1701 switch (acl_ip4_key) { 1702 case 1: /* ACL_IP4, 288-bit */ 1703 offset1 = fwd_ipv4_present ? KEY_GEN_OFFSET_TR2_ACL_IP4 : 1704 KEY_GEN_OFFSET_TR2_ACL_IP4_ONLY; 1705 offset2 = fwd_l2_present ? KEY_GEN_OFFSET_TR2_ACL_IP4_L2 : 1706 KEY_GEN_OFFSET_TR2_ACL_IP4_ONLY; 1707 break; 1708 case 2: /* ACL_IP4C, 144-bit */ 1709 offset1 = fwd_ipv4_present ? KEY_GEN_OFFSET_TR2_ACL_IP4C : 1710 KEY_GEN_OFFSET_TR2_ACL_IP4C_ONLY; 1711 offset2 = fwd_l2_present ? KEY_GEN_OFFSET_TR2_ACL_IP4C_L2 : 1712 KEY_GEN_OFFSET_TR2_ACL_IP4C_ONLY; 1713 break; 1714 case 3: /* ACL_L2IP4, 432-bit */ 1715 offset1 = fwd_ipv4_present ? KEY_GEN_OFFSET_TR2_ACL_L2IP4 : 1716 KEY_GEN_OFFSET_TR2_ACL_L2IP4_ONLY; 1717 offset2 = fwd_l2_present ? KEY_GEN_OFFSET_TR2_ACL_L2IP4_L2 : 1718 KEY_GEN_OFFSET_TR2_ACL_L2IP4_ONLY; 1719 break; 1720 case 4: /* ACL_L2 or ACL_L2C */ 1721 1722 offset1 = -1; 1723 /* pick the correct L2 ACL variant instead of forcing 7K */ 1724 offset2 = l2_fm_offset1; 1725 break; 1726 default: 1727 offset1 = offset2 = -1; 1728 break; 1729 } 1730 if (offset1 > 0) { 1731 rv = soc_set_esm_search_profile_range(unit, 1732 SRCH_PROFILE_SRC_TRUNK_MAP_1 + FWD_TYPE_V4_ROUTE, 1733 SRCH_PROFILE_SRC_TRUNK_MAP_1 + FWD_TYPE_V4_ROUTE, 1, 1734 offset1); 1735 SOC_IF_ERROR_RETURN(rv); 1736 } 1737 if (offset2 > 0) { 1738 rv = soc_set_esm_search_profile_range(unit, 1739 SRCH_PROFILE_SRC_TRUNK_MAP_1 + FWD_TYPE_V4_BRIDGE, 1740 SRCH_PROFILE_SRC_TRUNK_MAP_1 + FWD_TYPE_V4_BRIDGE, 1, 1741 offset2); 1742 SOC_IF_ERROR_RETURN(rv); 1743 } 1744 switch (acl_ip6_key) { 1745 case 1: /* ACL_IP6S, 360-bit */ 1746 offset1 = (!fwd_ipv6_present && !fwd_ipv6u_present) ? 1747 KEY_GEN_OFFSET_TR2_ACL_IP6S_ONLY : 1748 (fwd_ip6_key ? KEY_GEN_OFFSET_TR2_ACL_IP6S : 1749 KEY_GEN_OFFSET_TR2_ACL_IP6S_IP6U_FWD); 1750 offset2 = fwd_l2_present ? KEY_GEN_OFFSET_TR2_ACL_IP6S_L2 : 1751 KEY_GEN_OFFSET_TR2_ACL_IP6S_ONLY; 1752 break; 1753 case 2: /* ACL_IP6F, 432-bit */ 1754 offset1 = (!fwd_ipv6_present && !fwd_ipv6u_present) ? 1755 KEY_GEN_OFFSET_TR2_ACL_IP6F_ONLY : 1756 (fwd_ip6_key ? KEY_GEN_OFFSET_TR2_ACL_IP6F : 1757 KEY_GEN_OFFSET_TR2_ACL_IP6F_IP6U_FWD); 1758 offset2 = fwd_l2_present ? KEY_GEN_OFFSET_TR2_ACL_IP6F_L2 : 1759 KEY_GEN_OFFSET_TR2_ACL_IP6F_ONLY; 1760 break; 1761 case 3: /* ACL_IP6C, 144-bit */ 1762 offset1 = (!fwd_ipv6_present && !fwd_ipv6u_present) ? 1763 KEY_GEN_OFFSET_TR2_ACL_IP6C_ONLY : 1764 (fwd_ip6_key ? KEY_GEN_OFFSET_TR2_ACL_IP6C : 1765 KEY_GEN_OFFSET_TR2_ACL_IP6C_IP6U_FWD); 1766 offset2 = fwd_l2_present ? KEY_GEN_OFFSET_TR2_ACL_IP6C_L2 : 1767 KEY_GEN_OFFSET_TR2_ACL_IP6C_ONLY; 1768 break; 1769 case 4: /* ACL_L2IP6, 432-bit */ 1770 offset1 = fwd_ip6_key ? KEY_GEN_OFFSET_TR2_ACL_L2IP6 : 1771 KEY_GEN_OFFSET_TR2_ACL_L2IP6_ONLY; 1772 offset2 = fwd_l2_present ? KEY_GEN_OFFSET_TR2_ACL_L2IP6_L2 : 1773 KEY_GEN_OFFSET_TR2_ACL_L2IP6_ONLY; 1774 break; 1775 case 5: /* ACL_L2 or ACL_L2C */ 1776 offset1 = -1; offset2 = l2_fm_offset1; 1777 break; 1778 default: 1779 offset1 = -1; 1780 offset2 = -1; 1781 break; 1782 } 1783 if (offset1 > 0) { 1784 rv = soc_set_esm_search_profile_range(unit, 1785 SRCH_PROFILE_SRC_TRUNK_MAP_1 + FWD_TYPE_V6_ROUTE, 1786 SRCH_PROFILE_SRC_TRUNK_MAP_1 + FWD_TYPE_V6_ROUTE, 1, 1787 offset1); 1788 SOC_IF_ERROR_RETURN(rv); 1789 } 1790 if (offset2 > 0) { 1791 rv = soc_set_esm_search_profile_range(unit, 1792 SRCH_PROFILE_SRC_TRUNK_MAP_1 + FWD_TYPE_V6_BRIDGE, 1793 SRCH_PROFILE_SRC_TRUNK_MAP_1 + FWD_TYPE_V6_BRIDGE, 1, 1794 offset2); 1795 SOC_IF_ERROR_RETURN(rv); 1796 } 1797 return SOC_E_NONE; 1798 } 1799 1800 #if 1 1801 1802 STATIC int 1803 _soc_triumph3_esm_init_set_et_pa_xlate(int unit) 1804 { 1805 soc_tcam_info_t *tcam_info; 1806 soc_tcam_partition_t *partitions; 1807 int i, rv, hbit_base, order_idx, mem_rv=0; 1808 int part, dup_part, index, entries_per_blk, blks_per_part; 1809 int hbit_avail=1; 1810 int db_duplicated=0; 1811 uint32 dup_db_offset = 0; 1812 uint32 ism_bank_size_l2[20], max_hit_bits, tmp; 1813 uint32 ism_bank_size_l3[20], ism_bank_size_acl[20], *ism_bank_size=0; 1814 uint8 ism_banks_l2[20], ism_bank_count_l2; 1815 uint8 ism_banks_l3[20], ism_bank_count_l3; 1816 uint8 ism_banks_acl[20], ism_bank_count_acl, ism_bank_count, *ism_banks = 0; 1817 int cur_col; 1818 uint32 cur_bank, cur_row; 1819 1820 tcam_info = SOC_CONTROL(unit)->tcam_info; 1821 if (tcam_info == NULL) { 1822 return SOC_E_NONE; 1823 } 1824 partitions = tcam_info->partitions; 1825 SOC_IF_ERROR_RETURN(READ_ETU_CONFIG0r(unit, &tmp)); 1826 if (soc_reg_field_get(unit, ETU_CONFIG0r, tmp, EN_LOCAL_SA_HBITf)) { 1827 max_hit_bits = 512*1024; 1828 } else { 1829 max_hit_bits = 1024*1024; 1830 } 1831 1832 hbit_base = 0; 1833 1834 rv = soc_ism_get_banks(unit, SOC_ISM_MEM_ESM_L2, ism_banks_l2, ism_bank_size_l2, 1835 &ism_bank_count_l2); 1836 #ifdef testing 1837 ism_banks_l3[0] = ism_banks_l2[5]; 1838 ism_banks_l3[1] = ism_banks_l2[6]; 1839 ism_banks_l3[2] = ism_banks_l2[7]; 1840 ism_banks_l3[3] = ism_banks_l2[8]; 1841 ism_banks_l3[4] = ism_banks_l2[9]; 1842 ism_banks_acl[0] = ism_banks_l2[10]; 1843 ism_banks_acl[1] = ism_banks_l2[11]; 1844 ism_banks_acl[2] = ism_banks_l2[12]; 1845 ism_banks_acl[3] = ism_banks_l2[13]; 1846 ism_banks_acl[4] = ism_banks_l2[14]; 1847 ism_bank_count_l2 = ism_bank_count_l3 = 5; 1848 ism_bank_count_acl = 10; 1849 ism_bank_size_l3[0] = ism_bank_size_l2[5]; 1850 ism_bank_size_l3[1] = ism_bank_size_l2[6]; 1851 ism_bank_size_l3[2] = ism_bank_size_l2[7]; 1852 ism_bank_size_l3[3] = ism_bank_size_l2[8]; 1853 ism_bank_size_l3[4] = ism_bank_size_l2[9]; 1854 ism_bank_size_acl[0] = ism_bank_size_l2[10]; 1855 ism_bank_size_acl[1] = ism_bank_size_l2[11]; 1856 ism_bank_size_acl[2] = ism_bank_size_l2[12]; 1857 ism_bank_size_acl[3] = ism_bank_size_l2[13]; 1858 ism_bank_size_acl[4] = ism_bank_size_l2[14]; 1859 #else 1860 if (rv < 0) return SOC_E_FAIL; 1861 rv = soc_ism_get_banks(unit, SOC_ISM_MEM_ESM_L3, ism_banks_l3, ism_bank_size_l3, 1862 &ism_bank_count_l3); 1863 if (rv < 0) return SOC_E_FAIL; 1864 rv = soc_ism_get_banks(unit, SOC_ISM_MEM_ESM_ACL, ism_banks_acl, ism_bank_size_acl, 1865 &ism_bank_count_acl); 1866 if (rv < 0) return SOC_E_FAIL; 1867 #endif 1868 1869 /* calculate duplicate database offset if there is one */ 1870 part = 0; 1871 dup_part = 0; 1872 if (partitions[TCAM_PARTITION_FWD_L2_DUP].num_entries) { 1873 part = TCAM_PARTITION_FWD_L2; 1874 dup_part = TCAM_PARTITION_FWD_L2_DUP; 1875 } else if (partitions[TCAM_PARTITION_FWD_IP4_DUP].num_entries) { 1876 part = TCAM_PARTITION_FWD_IP4_UCAST; 1877 dup_part = TCAM_PARTITION_FWD_IP4_DUP; 1878 } else if (partitions[TCAM_PARTITION_FWD_IP6U_DUP].num_entries) { 1879 part = TCAM_PARTITION_FWD_IP6U; 1880 dup_part = TCAM_PARTITION_FWD_IP6U_DUP; 1881 } else if (partitions[TCAM_PARTITION_FWD_IP6_DUP].num_entries) { 1882 part = TCAM_PARTITION_FWD_IP6_128_UCAST; 1883 dup_part = TCAM_PARTITION_FWD_IP6_DUP; 1884 } 1885 if (part) { 1886 dup_db_offset = partitions[dup_part].tcam_base - 1887 partitions[part].tcam_base; 1888 dup_db_offset >>= 12; 1889 } 1890 1891 cur_row = 0; 1892 cur_col = 11; 1893 cur_bank = 0; 1894 /* 1895 * go in reverse order so that row addresses within a bank will only go 1896 * in increasing order 1897 */ 1898 for (order_idx = sizeof(tr3_tcam_partition_order)/sizeof(uint32)-1; 1899 order_idx >= 0; order_idx--) { 1900 part = tr3_tcam_partition_order[order_idx]; 1901 if ((part == 0) || (!partitions[part].num_entries) || 1902 (partitions[part].flags & TCAM_PARTITION_FLAGS_NO_AD)) { 1903 db_duplicated = 0; 1904 continue; 1905 } 1906 switch (partitions[part].flags & TCAM_PARTITION_FLAGS_TYPE_MASK) { 1907 case TCAM_PARTITION_FLAGS_TYPE_ACL: 1908 /* acl partitions are assumed to be always last in the partition order */ 1909 ism_banks = ism_banks_acl; 1910 ism_bank_size = ism_bank_size_acl; 1911 ism_bank_count = ism_bank_count_acl; 1912 db_duplicated = 0; 1913 break; 1914 case TCAM_PARTITION_FLAGS_TYPE_L3: 1915 if (ism_banks != ism_banks_l3) { 1916 cur_row = 0; 1917 cur_col = 11; 1918 cur_bank = 0; 1919 } 1920 ism_banks = ism_banks_l3; 1921 ism_bank_size = ism_bank_size_l3; 1922 ism_bank_count = ism_bank_count_l3; 1923 switch (part) { 1924 case TCAM_PARTITION_FWD_IP4_UCAST: 1925 case TCAM_PARTITION_FWD_IP4_UCAST_WIDE: 1926 case TCAM_PARTITION_FWD_IP4: 1927 if (partitions[TCAM_PARTITION_FWD_IP4_DUP].num_entries) { 1928 db_duplicated = 1; 1929 } else { 1930 db_duplicated = 0; 1931 } 1932 break; 1933 case TCAM_PARTITION_FWD_IP6U: 1934 if (partitions[TCAM_PARTITION_FWD_IP6U_DUP].num_entries) { 1935 db_duplicated = 1; 1936 } else { 1937 db_duplicated = 0; 1938 } 1939 break; 1940 case TCAM_PARTITION_FWD_IP6_128_UCAST: 1941 case TCAM_PARTITION_FWD_IP6_128_UCAST_WIDE: 1942 case TCAM_PARTITION_FWD_IP6: 1943 if (partitions[TCAM_PARTITION_FWD_IP6_DUP].num_entries) { 1944 db_duplicated = 1; 1945 } else { 1946 db_duplicated = 0; 1947 } 1948 break; 1949 default: 1950 db_duplicated = 0; 1951 break; 1952 } 1953 break; 1954 case TCAM_PARTITION_FLAGS_TYPE_L2: 1955 if (ism_banks != ism_banks_l2) { 1956 cur_row = 0; 1957 cur_col = 11; 1958 cur_bank = 0; 1959 } 1960 ism_banks = ism_banks_l2; 1961 ism_bank_size = ism_bank_size_l2; 1962 ism_bank_count = ism_bank_count_l2; 1963 if (partitions[TCAM_PARTITION_FWD_L2_DUP].num_entries) { 1964 db_duplicated = 1; 1965 } else { 1966 db_duplicated = 0; 1967 } 1968 break; 1969 default: 1970 return SOC_E_PARAM; 1971 } 1972 1973 entries_per_blk = 4096 >> partitions[part].ad_info.et_width; 1974 1975 blks_per_part = (partitions[part].num_entries + 1976 entries_per_blk - 1)/entries_per_blk; 1977 1978 /* get index into ET_PA_XLAT table */ 1979 index = partitions[part].tcam_base >> 12; 1980 1981 for (i = 0; i < blks_per_part; i++) { 1982 /* configure hbit pa */ 1983 if (partitions[part].ad_info.hit_bit_enable) { 1984 if (hbit_avail) { 1985 partitions[part].ad_info.hit_bit_pa_base = hbit_base; 1986 partitions[part].ad_info.hit_bit_enable = 1; 1987 hbit_base += (2 - partitions[part].tcam_width_shift); 1988 } else { 1989 partitions[part].ad_info.hit_bit_enable = 0; 1990 } 1991 if ((hbit_base << 11) >= max_hit_bits) { 1992 /* flag error */ 1993 LOG_CLI((BSL_META_U(unit, 1994 "unit %d: ESM max no. of hit bits (%d) reached."), 1995 unit, max_hit_bits)); 1996 LOG_CLI((BSL_META_U(unit, 1997 "Some entries may not have hit bits\n"))); 1998 hbit_avail = 0; 1999 } 2000 } 2001 2002 if (i > 0) { 2003 SOC_TR3_INCR_AD_ADDR(cur_row, cur_col, cur_bank, 2004 partitions[part].ad_info.ad_width + 1, mem_rv); 2005 } 2006 2007 /* check return value of ad increment here since we should check the 2008 * value only if more mem is needed 2009 */ 2010 if (!SOC_SUCCESS(mem_rv)) { 2011 LOG_CLI((BSL_META_U(unit, 2012 "unit %d: No more et_pa_xlat memory. " 2013 "Partition = %d\n"), unit, part)); 2014 return mem_rv; 2015 } 2016 2017 /* wrap to new column if current column space may not be enough */ 2018 if ((cur_col + 1) < (partitions[part].ad_info.ad_width + 1)) { 2019 SOC_TR3_INCR_AD_ADDR(cur_row, cur_col, cur_bank, cur_col + 1,mem_rv); 2020 } else if (partitions[part].ad_info.ad_width == 5) { 2021 /* for max width might still have to increment */ 2022 if ((cur_col+1) % (partitions[part].ad_info.ad_width + 1)) { 2023 /* cur_col != 11 or 5 */ 2024 if (cur_col > 8) { 2025 /* fit starting to col. no. 8 */ 2026 SOC_TR3_INCR_AD_ADDR(cur_row, cur_col, cur_bank, 2027 cur_col - 8, mem_rv); 2028 } else if ((cur_col < 8) && (cur_col > 6)) { 2029 SOC_TR3_INCR_AD_ADDR(cur_row, cur_col, cur_bank, 2030 cur_col - 6, mem_rv); 2031 } 2032 } 2033 } 2034 2035 if (!SOC_SUCCESS(mem_rv)) { 2036 LOG_CLI((BSL_META_U(unit, 2037 "unit %d: Could not get more et_pa_xlat memory. " 2038 "Partition = %d\n"), unit, part)); 2039 return mem_rv; 2040 } 2041 2042 /* configure ad_ba, ad_ra_base, ad_ca */ 2043 partitions[part].ad_info.ad_ba = ism_banks[cur_bank]; 2044 partitions[part].ad_info.ad_ra_base = cur_row; 2045 partitions[part].ad_info.ad_ca = cur_col; 2046 2047 rv = _soc_write_et_pa_xlat_entry(unit, index + i, 2048 &partitions[part].ad_info); 2049 2050 if (!SOC_SUCCESS(rv)) { 2051 LOG_CLI((BSL_META_U(unit, 2052 "unit %d: Failure writing et_pa_xlat entry. " 2053 "Partition = %d\n"), unit, part)); 2054 return rv; 2055 2056 } 2057 if (db_duplicated) { 2058 rv = _soc_write_et_pa_xlat_entry(unit, 2059 dup_db_offset + index + i, 2060 &partitions[part].ad_info); 2061 if (!SOC_SUCCESS(rv)) { 2062 LOG_CLI((BSL_META_U(unit, 2063 "unit %d: Failure writing duplicated " 2064 "db et_pa_xlat entry. Partition = %d\n"), 2065 unit, part)); 2066 return rv; 2067 2068 } 2069 } 2070 } 2071 } 2072 return SOC_E_NONE; 2073 } 2074 #endif 2075 2076 int 2077 _soc_triumph3_esm_init_adjust_mem_size(int unit) 2078 { 2079 soc_persist_t *sop; 2080 sop_memstate_t *memState; 2081 soc_tcam_info_t *tcam_info; 2082 soc_tcam_partition_t *partitions; 2083 int policy_width; 2084 2085 sop = SOC_PERSIST(unit); 2086 memState = sop->memState; 2087 tcam_info = SOC_CONTROL(unit)->tcam_info; 2088 if (tcam_info == NULL) 2089 { 2090 LOG_CLI((BSL_META_U(unit, 2091 "unit: %d No external tables configured\n"), unit)); 2092 return SOC_E_NONE; 2093 } 2094 partitions = tcam_info->partitions; 2095 2096 /* L2 forwarding partition */ 2097 memState[EXT_L2_ENTRY_1m].index_max = /* TCAM + SRAM */ 2098 memState[EXT_L2_ENTRY_TCAMm].index_max = /* TCAM */ 2099 memState[EXT_L2_ENTRY_DATA_ONLYm].index_max = /* SRAM */ 2100 partitions[TCAM_PARTITION_FWD_L2].num_entries - 1; 2101 memState[EXT_SRC_HIT_BITS_L2m].index_max = 2102 memState[EXT_LOC_SRC_HIT_BITS_L2m].index_max = 2103 memState[EXT_DST_HIT_BITS_L2m].index_max = 2104 memState[EXT_TCAM_VBIT_L2_ENTRY_1m].index_max = 2105 (partitions[TCAM_PARTITION_FWD_L2].num_entries + 31) / 32 - 1; 2106 2107 memState[EXT_L2_ENTRY_2m].index_max = /* TCAM + SRAM */ 2108 memState[EXT_L2_ENTRY_TCAM_WIDEm].index_max = /* TCAM */ 2109 memState[EXT_L2_ENTRY_DATA_ONLY_WIDEm].index_max = /* SRAM */ 2110 partitions[TCAM_PARTITION_FWD_L2_WIDE].num_entries - 1; 2111 memState[EXT_SRC_HIT_BITS_L2_WIDEm].index_max = 2112 memState[EXT_LOC_SRC_HIT_BITS_L2_WIDEm].index_max = 2113 memState[EXT_DST_HIT_BITS_L2_WIDEm].index_max = 2114 memState[EXT_TCAM_VBIT_L2_ENTRY_2m].index_max = /* TCAM */ 2115 (partitions[TCAM_PARTITION_FWD_L2_WIDE].num_entries + 31) / 32 - 1; 2116 2117 /* IP4 forwarding partition */ 2118 memState[EXT_IPV4_DEFIPm].index_max = /* TCAM + SRAM */ 2119 memState[EXT_IPV4_DEFIP_TCAMm].index_max = /* TCAM */ 2120 memState[EXT_DEFIP_DATA_IPV4m].index_max = /* SRAM */ 2121 partitions[TCAM_PARTITION_FWD_IP4].num_entries - 1; 2122 memState[EXT_SRC_HIT_BITS_IPV4m].index_max = 2123 memState[EXT_DST_HIT_BITS_IPV4m].index_max = 2124 memState[EXT_TCAM_VBIT_DEFIP_IPV4m].index_max = 2125 (partitions[TCAM_PARTITION_FWD_IP4].num_entries + 31) / 32 - 1; 2126 2127 memState[EXT_IPV4_UCASTm].index_max = /* TCAM + SRAM */ 2128 memState[EXT_IPV4_UCAST_TCAMm].index_max = /* TCAM + SRAM */ 2129 memState[EXT_L3_UCAST_DATA_IPV4m].index_max = /* TCAM + SRAM */ 2130 partitions[TCAM_PARTITION_FWD_IP4_UCAST].num_entries - 1; 2131 memState[EXT_SRC_HIT_BITS_IPV4_UCASTm].index_max = 2132 memState[EXT_DST_HIT_BITS_IPV4_UCASTm].index_max = 2133 memState[EXT_TCAM_VBIT_IPV4_UCASTm].index_max = 2134 (partitions[TCAM_PARTITION_FWD_IP4_UCAST].num_entries + 31) / 32 - 1; 2135 2136 memState[EXT_IPV4_UCAST_WIDEm].index_max = /* TCAM + SRAM */ 2137 memState[EXT_IPV4_UCAST_WIDE_TCAMm].index_max = /* TCAM + SRAM */ 2138 memState[EXT_L3_UCAST_DATA_WIDE_IPV4m].index_max = /* TCAM + SRAM */ 2139 partitions[TCAM_PARTITION_FWD_IP4_UCAST_WIDE].num_entries - 1; 2140 memState[EXT_SRC_HIT_BITS_IPV4_UCAST_WIDEm].index_max = 2141 memState[EXT_DST_HIT_BITS_IPV4_UCAST_WIDEm].index_max = 2142 memState[EXT_TCAM_VBIT_IPV4_UCAST_WIDEm].index_max = 2143 (partitions[TCAM_PARTITION_FWD_IP4_UCAST_WIDE].num_entries + 31)/32 - 1; 2144 2145 memState[EXT_IPV4_TCAMm].index_max = /* SRC hit bit */ 2146 partitions[TCAM_PARTITION_FWD_IP4].num_entries + 2147 partitions[TCAM_PARTITION_FWD_IP4_UCAST].num_entries + 2148 partitions[TCAM_PARTITION_FWD_IP4_UCAST_WIDE].num_entries - 1; 2149 2150 /* IP6 64-bit prefix forwarding partition */ 2151 memState[EXT_IPV6_64_DEFIPm].index_max = /* TCAM + SRAM */ 2152 memState[EXT_IPV6_64_DEFIP_TCAMm].index_max = /* TCAM */ 2153 memState[EXT_DEFIP_DATA_IPV6_64m].index_max = /* SRAM */ 2154 partitions[TCAM_PARTITION_FWD_IP6U].num_entries - 1; 2155 2156 memState[EXT_IPV6_64_TCAMm].index_max = /* TCAM */ 2157 partitions[TCAM_PARTITION_FWD_IP6U].num_entries - 1; 2158 2159 memState[EXT_SRC_HIT_BITS_IPV6_64m].index_max = /* SRC hit bit */ 2160 memState[EXT_DST_HIT_BITS_IPV6_64m].index_max = /* DST hit bit */ 2161 memState[EXT_TCAM_VBIT_DEFIP_IPV6_64m].index_max = 2162 (partitions[TCAM_PARTITION_FWD_IP6U].num_entries + 31) / 32 - 1; 2163 2164 /* IP6 128-bit prefix forwarding partition */ 2165 memState[EXT_IPV6_128_DEFIPm].index_max = /* TCAM + SRAM */ 2166 memState[EXT_IPV6_128_DEFIP_TCAMm].index_max = /* TCAM */ 2167 memState[EXT_DEFIP_DATA_IPV6_128m].index_max = /* SRAM */ 2168 partitions[TCAM_PARTITION_FWD_IP6].num_entries - 1; 2169 memState[EXT_SRC_HIT_BITS_IPV6_128m].index_max = /* SRC hit bit */ 2170 memState[EXT_DST_HIT_BITS_IPV6_128m].index_max = /* DST hit bit */ 2171 memState[EXT_TCAM_VBIT_DEFIP_IPV6_128m].index_max = 2172 (partitions[TCAM_PARTITION_FWD_IP6].num_entries + 31)/32 - 1; 2173 2174 memState[EXT_IPV6_128_UCASTm].index_max = /* TCAM + SRAM */ 2175 memState[EXT_IPV6_128_UCAST_TCAMm].index_max = /* TCAM */ 2176 memState[EXT_L3_UCAST_DATA_IPV6_128m].index_max = /* SRAM */ 2177 partitions[TCAM_PARTITION_FWD_IP6_128_UCAST].num_entries - 1; 2178 memState[EXT_SRC_HIT_BITS_IPV6_128_UCASTm].index_max = /* SRC hit bit */ 2179 memState[EXT_DST_HIT_BITS_IPV6_128_UCASTm].index_max = /* DST hit bit*/ 2180 memState[EXT_TCAM_VBIT_IPV6_128_UCASTm].index_max = 2181 (partitions[TCAM_PARTITION_FWD_IP6_128_UCAST].num_entries + 63)/64 - 1; 2182 2183 memState[EXT_IPV6_128_UCAST_WIDEm].index_max = /* TCAM + SRAM */ 2184 memState[EXT_IPV6_128_UCAST_WIDE_TCAMm].index_max = /* TCAM + SRAM */ 2185 memState[EXT_L3_UCAST_DATA_WIDE_IPV6_128m].index_max = /* SRAM */ 2186 partitions[TCAM_PARTITION_FWD_IP6_128_UCAST_WIDE].num_entries - 1; 2187 memState[EXT_SRC_HIT_BITS_IPV6_128_UCAST_WIDEm].index_max = /* SRC hit bit */ 2188 memState[EXT_DST_HIT_BITS_IPV6_128_UCAST_WIDEm].index_max=/* DST hitbit*/ 2189 memState[EXT_TCAM_VBIT_IPV6_128_UCAST_WIDEm].index_max = 2190 (partitions[TCAM_PARTITION_FWD_IP6_128_UCAST_WIDE].num_entries+63/64)-1; 2191 2192 memState[EXT_IPV6_128_TCAMm].index_max = /* TCAM */ 2193 partitions[TCAM_PARTITION_FWD_IP6].num_entries + 2194 partitions[TCAM_PARTITION_FWD_IP6_128_UCAST].num_entries + 2195 partitions[TCAM_PARTITION_FWD_IP6_128_UCAST_WIDE].num_entries - 1; 2196 2197 /* L2 288-bit ACL partition */ 2198 memState[EXT_ACL288_TCAM_L2m].index_max = /* TCAM */ 2199 partitions[TCAM_PARTITION_ACL_L2].num_entries - 1; 2200 policy_width = soc_property_get(unit, spn_EXT_L2_ACL_TABLE_POLICY_WIDTH, 0); 2201 SOC_TR3_SET_POLICY_TABLE_SIZE(EXT_FP_POLICY_ACL288_L2_1Xm, 2202 EXT_FP_POLICY_ACL288_L2_2Xm, 2203 EXT_FP_POLICY_ACL288_L2_3Xm, 2204 EXT_FP_POLICY_ACL288_L2_4Xm, 2205 EXT_FP_POLICY_ACL288_L2_6Xm, 2206 policy_width, 2207 partitions[TCAM_PARTITION_ACL_L2].num_entries - 1); 2208 2209 /* IP4 288-bit ACL partition */ 2210 memState[EXT_ACL288_TCAM_IPV4m].index_max = /* TCAM */ 2211 partitions[TCAM_PARTITION_ACL_IP4].num_entries - 1; 2212 policy_width =soc_property_get(unit, spn_EXT_IP4_ACL_TABLE_POLICY_WIDTH, 0); 2213 SOC_TR3_SET_POLICY_TABLE_SIZE(EXT_FP_POLICY_ACL288_IPV4_1Xm, 2214 EXT_FP_POLICY_ACL288_IPV4_2Xm, 2215 EXT_FP_POLICY_ACL288_IPV4_3Xm, 2216 EXT_FP_POLICY_ACL288_IPV4_4Xm, 2217 EXT_FP_POLICY_ACL288_IPV4_6Xm, 2218 policy_width, 2219 partitions[TCAM_PARTITION_ACL_IP4].num_entries - 1); 2220 2221 /* IP6 short form 360-bit ACL partition */ 2222 memState[EXT_ACL360_TCAM_DATA_IPV6_SHORTm].index_max = /* TCAM data */ 2223 partitions[TCAM_PARTITION_ACL_IP6S].num_entries - 1; 2224 policy_width=soc_property_get(unit, spn_EXT_IP6S_ACL_TABLE_POLICY_WIDTH, 0); 2225 SOC_TR3_SET_POLICY_TABLE_SIZE(EXT_FP_POLICY_ACL360_IPV6_SHORT_1Xm, 2226 EXT_FP_POLICY_ACL360_IPV6_SHORT_2Xm, 2227 EXT_FP_POLICY_ACL360_IPV6_SHORT_3Xm, 2228 EXT_FP_POLICY_ACL360_IPV6_SHORT_4Xm, 2229 EXT_FP_POLICY_ACL360_IPV6_SHORT_6Xm, 2230 policy_width, 2231 partitions[TCAM_PARTITION_ACL_IP6S].num_entries - 1); 2232 2233 /* IP6 full form 432-bit ACL partition */ 2234 memState[EXT_ACL432_TCAM_DATA_IPV6_LONGm].index_max = /* TCAM data */ 2235 partitions[TCAM_PARTITION_ACL_IP6F].num_entries - 1; 2236 policy_width=soc_property_get(unit, spn_EXT_IP6F_ACL_TABLE_POLICY_WIDTH, 0); 2237 SOC_TR3_SET_POLICY_TABLE_SIZE(EXT_FP_POLICY_ACL432_IPV6_LONG_1Xm, 2238 EXT_FP_POLICY_ACL432_IPV6_LONG_2Xm, 2239 EXT_FP_POLICY_ACL432_IPV6_LONG_3Xm, 2240 EXT_FP_POLICY_ACL432_IPV6_LONG_4Xm, 2241 EXT_FP_POLICY_ACL432_IPV6_LONG_6Xm, 2242 policy_width, 2243 partitions[TCAM_PARTITION_ACL_IP6F].num_entries - 1); 2244 2245 /* L2 compact form 144-bit ACL partition */ 2246 memState[EXT_ACL144_TCAM_L2m].index_max = /* TCAM */ 2247 partitions[TCAM_PARTITION_ACL_L2C].num_entries - 1; 2248 policy_width=soc_property_get(unit, spn_EXT_L2C_ACL_TABLE_POLICY_WIDTH, 0); 2249 SOC_TR3_SET_POLICY_TABLE_SIZE(EXT_FP_POLICY_ACL144_L2_1Xm, 2250 EXT_FP_POLICY_ACL144_L2_2Xm, 2251 EXT_FP_POLICY_ACL144_L2_3Xm, 2252 EXT_FP_POLICY_ACL144_L2_4Xm, 2253 EXT_FP_POLICY_ACL144_L2_6Xm, 2254 policy_width, 2255 partitions[TCAM_PARTITION_ACL_L2C].num_entries - 1); 2256 2257 /* IP4 compact form 144-bit ACL partition */ 2258 memState[EXT_ACL144_TCAM_IPV4m].index_max = /* TCAM */ 2259 partitions[TCAM_PARTITION_ACL_IP4C].num_entries - 1; 2260 policy_width=soc_property_get(unit, spn_EXT_IP4C_ACL_TABLE_POLICY_WIDTH, 0); 2261 SOC_TR3_SET_POLICY_TABLE_SIZE(EXT_FP_POLICY_ACL144_IPV4_1Xm, 2262 EXT_FP_POLICY_ACL144_IPV4_2Xm, 2263 EXT_FP_POLICY_ACL144_IPV4_3Xm, 2264 EXT_FP_POLICY_ACL144_IPV4_4Xm, 2265 EXT_FP_POLICY_ACL144_IPV4_6Xm, 2266 policy_width, 2267 partitions[TCAM_PARTITION_ACL_IP4C].num_entries - 1); 2268 2269 /* IP6 compact form 144-bit ACL partition */ 2270 memState[EXT_ACL144_TCAM_IPV6m].index_max = /* TCAM */ 2271 partitions[TCAM_PARTITION_ACL_IP6C].num_entries - 1; 2272 policy_width=soc_property_get(unit, spn_EXT_IP6C_ACL_TABLE_POLICY_WIDTH, 0); 2273 SOC_TR3_SET_POLICY_TABLE_SIZE(EXT_FP_POLICY_ACL144_IPV6_1Xm, 2274 EXT_FP_POLICY_ACL144_IPV6_2Xm, 2275 EXT_FP_POLICY_ACL144_IPV6_3Xm, 2276 EXT_FP_POLICY_ACL144_IPV6_4Xm, 2277 EXT_FP_POLICY_ACL144_IPV6_6Xm, 2278 policy_width, 2279 partitions[TCAM_PARTITION_ACL_IP6C].num_entries - 1); 2280 2281 /* L2+IP4 432-bit ACL partition */ 2282 memState[EXT_ACL432_TCAM_DATA_L2_IPV4m].index_max = /* TCAM data */ 2283 memState[EXT_FP_POLICY_ACL432_L2_IPV4m].index_max = /* SRAM */ 2284 partitions[TCAM_PARTITION_ACL_L2IP4].num_entries - 1; 2285 policy_width=soc_property_get(unit, spn_EXT_L2IP4_ACL_TABLE_POLICY_WIDTH,0); 2286 SOC_TR3_SET_POLICY_TABLE_SIZE(EXT_FP_POLICY_ACL432_L2_IPV4_1Xm, 2287 EXT_FP_POLICY_ACL432_L2_IPV4_2Xm, 2288 EXT_FP_POLICY_ACL432_L2_IPV4_3Xm, 2289 EXT_FP_POLICY_ACL432_L2_IPV4_4Xm, 2290 EXT_FP_POLICY_ACL432_L2_IPV4_6Xm, 2291 policy_width, 2292 partitions[TCAM_PARTITION_ACL_L2IP4].num_entries - 1); 2293 2294 /* L2+IP6 432-bit ACL partition */ 2295 memState[EXT_ACL432_TCAM_DATA_L2_IPV6m].index_max = /* TCAM data */ 2296 partitions[TCAM_PARTITION_ACL_L2IP6].num_entries - 1; 2297 policy_width = soc_property_get(unit, spn_EXT_L2IP6_ACL_TABLE_POLICY_WIDTH, 2298 0); 2299 SOC_TR3_SET_POLICY_TABLE_SIZE(EXT_FP_POLICY_ACL432_L2_IPV6_1Xm, 2300 EXT_FP_POLICY_ACL432_L2_IPV6_2Xm, 2301 EXT_FP_POLICY_ACL432_L2_IPV6_3Xm, 2302 EXT_FP_POLICY_ACL432_L2_IPV6_4Xm, 2303 EXT_FP_POLICY_ACL432_L2_IPV6_6Xm, 2304 policy_width, 2305 partitions[TCAM_PARTITION_ACL_L2IP6].num_entries - 1); 2306 2307 /* 80-bit ACL partition */ 2308 memState[EXT_ACL80_TCAMm].index_max = /* TCAM */ 2309 memState[EXT_ACL80_FP_POLICY_1Xm].index_max = /* SRAM */ 2310 memState[EXT_ACL80_FP_POLICY_2Xm].index_max = /* SRAM */ 2311 memState[EXT_ACL80_FP_POLICY_3Xm].index_max = /* SRAM */ 2312 memState[EXT_ACL80_FP_POLICY_4Xm].index_max = /* SRAM */ 2313 memState[EXT_ACL80_FP_POLICY_6Xm].index_max = /* SRAM */ 2314 partitions[TCAM_PARTITION_ACL80].num_entries - 1; 2315 memState[EXT_TCAM_VBIT_ACL80m].index_max = 2316 (partitions[TCAM_PARTITION_ACL80].num_entries + 31 / 32) - 1; 2317 2318 /* 160-bit ACL partition */ 2319 memState[EXT_ACL160_TCAMm].index_max = /* TCAM */ 2320 memState[EXT_ACL160_FP_POLICY_1Xm].index_max = /* SRAM */ 2321 memState[EXT_ACL160_FP_POLICY_2Xm].index_max = /* SRAM */ 2322 memState[EXT_ACL160_FP_POLICY_3Xm].index_max = /* SRAM */ 2323 memState[EXT_ACL160_FP_POLICY_4Xm].index_max = /* SRAM */ 2324 memState[EXT_ACL160_FP_POLICY_6Xm].index_max = /* SRAM */ 2325 partitions[TCAM_PARTITION_ACL160].num_entries - 1; 2326 memState[EXT_TCAM_VBIT_ACL160m].index_max = 2327 (partitions[TCAM_PARTITION_ACL160].num_entries + 31 / 32) - 1; 2328 2329 /* 320-bit ACL partition */ 2330 memState[EXT_ACL320_TCAMm].index_max = /* TCAM */ 2331 memState[EXT_ACL320_FP_POLICY_1Xm].index_max = /* SRAM */ 2332 memState[EXT_ACL320_FP_POLICY_2Xm].index_max = /* SRAM */ 2333 memState[EXT_ACL320_FP_POLICY_3Xm].index_max = /* SRAM */ 2334 memState[EXT_ACL320_FP_POLICY_4Xm].index_max = /* SRAM */ 2335 memState[EXT_ACL320_FP_POLICY_6Xm].index_max = /* SRAM */ 2336 partitions[TCAM_PARTITION_ACL320].num_entries - 1; 2337 memState[EXT_TCAM_VBIT_ACL320m].index_max = 2338 (partitions[TCAM_PARTITION_ACL320].num_entries + 31 / 32) - 1; 2339 2340 /* 480-bit ACL partition */ 2341 /* this is a special 1-entry memory */ 2342 memState[EXT_ACL480_TCAM_MASKm].index_max = 0; 2343 memState[EXT_ACL360_TCAM_MASKm].index_max = 0; 2344 memState[EXT_ACL432_TCAM_MASKm].index_max = 0; 2345 memState[EXT_ACL360_TCAM_MASK_IPV6_SHORTm].index_max = 0; 2346 memState[EXT_ACL432_TCAM_MASK_IPV6_LONGm].index_max = 0; 2347 memState[EXT_ACL432_TCAM_MASK_L2_IPV6m].index_max = 0; 2348 2349 memState[EXT_ACL480_TCAM_DATAm].index_max = /* TCAM */ 2350 memState[EXT_ACL480_FP_POLICY_1Xm].index_max = /* SRAM */ 2351 memState[EXT_ACL480_FP_POLICY_2Xm].index_max = /* SRAM */ 2352 memState[EXT_ACL480_FP_POLICY_3Xm].index_max = /* SRAM */ 2353 memState[EXT_ACL480_FP_POLICY_4Xm].index_max = /* SRAM */ 2354 memState[EXT_ACL480_FP_POLICY_6Xm].index_max = /* SRAM */ 2355 partitions[TCAM_PARTITION_ACL480].num_entries - 1; 2356 memState[EXT_TCAM_VBIT_ACL480m].index_max = 2357 (partitions[TCAM_PARTITION_ACL480].num_entries + 31 / 32) - 1; 2358 2359 /* All L2+L3 forwarding entries */ 2360 memState[EXT_SRC_HBITSm].index_max = /* SRC hit bit */ 2361 memState[EXT_DST_HBITSm].index_max = /* DST hit bit */ 2362 (partitions[TCAM_PARTITION_FWD_L2].num_entries + 31) / 32 + 2363 (partitions[TCAM_PARTITION_FWD_L2_WIDE].num_entries + 31) / 32 + 2364 (partitions[TCAM_PARTITION_FWD_IP4].num_entries + 31) / 32 + 2365 (partitions[TCAM_PARTITION_FWD_IP4_UCAST].num_entries + 31) / 32 + 2366 (partitions[TCAM_PARTITION_FWD_IP4_UCAST_WIDE].num_entries + 31) / 32 + 2367 (partitions[TCAM_PARTITION_FWD_IP6U].num_entries + 31) / 32 + 2368 (partitions[TCAM_PARTITION_FWD_IP6].num_entries + 31) / 32 + 2369 (partitions[TCAM_PARTITION_FWD_IP6_128_UCAST].num_entries + 31) / 32 + 2370 (partitions[TCAM_PARTITION_FWD_IP6_128_UCAST_WIDE].num_entries+31)/32-1; 2371 2372 /* All L2 */ 2373 memState[EXT_LOC_SRC_HBITSm].index_max = /* Local src hit bit */ 2374 (partitions[TCAM_PARTITION_FWD_L2].num_entries + 31) / 32 + 2375 (partitions[TCAM_PARTITION_FWD_L2_WIDE].num_entries + 31) / 32 - 1; 2376 2377 /* All L3 forwarding entries */ 2378 memState[EXT_DEFIP_DATAm].index_max = /* SRAM */ 2379 partitions[TCAM_PARTITION_FWD_IP4].num_entries + 2380 partitions[TCAM_PARTITION_FWD_IP6U].num_entries + 2381 partitions[TCAM_PARTITION_FWD_IP6].num_entries - 1; 2382 2383 memState[EXT_L3_UCAST_DATAm].index_max = /* SRAM */ 2384 partitions[TCAM_PARTITION_FWD_IP4_UCAST].num_entries + 2385 partitions[TCAM_PARTITION_FWD_IP6_128_UCAST].num_entries - 1; 2386 2387 memState[EXT_L3_UCAST_DATA_WIDEm].index_max = /* SRAM */ 2388 partitions[TCAM_PARTITION_FWD_IP4_UCAST_WIDE].num_entries + 2389 partitions[TCAM_PARTITION_FWD_IP6_128_UCAST_WIDE].num_entries - 1; 2390 2391 /* All ACL entries */ 2392 memState[EXT_FP_POLICY_1Xm].index_max = /* SRAM */ 2393 memState[EXT_FP_POLICY_2Xm].index_max = /* SRAM */ 2394 memState[EXT_FP_POLICY_3Xm].index_max = /* SRAM */ 2395 memState[EXT_FP_POLICY_4Xm].index_max = /* SRAM */ 2396 memState[EXT_FP_POLICY_6Xm].index_max = /* SRAM */ 2397 partitions[TCAM_PARTITION_ACL_L2].num_entries + 2398 partitions[TCAM_PARTITION_ACL_IP4].num_entries + 2399 partitions[TCAM_PARTITION_ACL_IP6S].num_entries + 2400 partitions[TCAM_PARTITION_ACL_IP6F].num_entries + 2401 partitions[TCAM_PARTITION_ACL_L2C].num_entries + 2402 partitions[TCAM_PARTITION_ACL_IP4C].num_entries + 2403 partitions[TCAM_PARTITION_ACL_IP6C].num_entries + 2404 partitions[TCAM_PARTITION_ACL_L2IP4].num_entries + 2405 partitions[TCAM_PARTITION_ACL_L2IP6].num_entries + 2406 partitions[TCAM_PARTITION_ACL80].num_entries + 2407 partitions[TCAM_PARTITION_ACL160].num_entries + 2408 partitions[TCAM_PARTITION_ACL320].num_entries + 2409 partitions[TCAM_PARTITION_ACL480].num_entries - 1; 2410 2411 memState[EXT_TCAM_VBITm].index_max = 1048575; 2412 return SOC_E_NONE; 2413 } 2414 2415 #define SOC_TR3_BUILD_FM_ENTRY(fm_entry, esm_key_type, f11, f10, f9, f8, f7, \ 2416 f6, f5, f4, f3, \ 2417 f1, f2_15, f2_14, f2_13, f2_12, f2_11, f2_10, \ 2418 f2_9, f2_8, f2_7, f2_6, f2_5, f2_4, f2_3, f2_2, \ 2419 f2_1, f2_0, drop_adm_deny, rsp_type0, \ 2420 rsp_type1, rsp_type2, rsp_type3, cost0, \ 2421 cost1, cost2, cw0_ltr, cw1_ltr, cw2_ltr, \ 2422 num_cwords, rsp0_cnt, rsp1_cnt, rsp2_cnt, \ 2423 eop_cw0, eop_cw1, eop_cw2, ctx_addr_lsb0,\ 2424 ctx_addr_lsb1, ctx_addr_lsb2, cw0_dwords,\ 2425 cw1_dwords, cw2_dwords, cw0_opc, cw1_opc, \ 2426 cw2_opc, last_cw_opt, opt_cost0, opt_cost1,\ 2427 opt_cost2)\ 2428 do {\ 2429 int nl_macro1, nl_macro2, nl_macro3;\ 2430 sal_memset(&(fm_entry), 0, sizeof((fm_entry)));\ 2431 (fm_entry).esm_key_subtype = (esm_key_type);\ 2432 (fm_entry).f_selects[11] = (f11);\ 2433 (fm_entry).f_selects[10] = (f10);\ 2434 (fm_entry).f_selects[9] = (f9);\ 2435 (fm_entry).f_selects[8] = (f8);\ 2436 (fm_entry).f_selects[7] = (f7);\ 2437 (fm_entry).f_selects[6] = (f6);\ 2438 (fm_entry).f_selects[5] = (f5);\ 2439 (fm_entry).f_selects[4] = (f4);\ 2440 (fm_entry).f_selects[3] = (f3);\ 2441 (fm_entry).f_selects[1] = (f1);\ 2442 if (!(f2_15) && !(f2_14) && !(f2_13) && !(f2_12) && !(f2_11) && !(f2_10) \ 2443 && !(f2_9) && !(f2_8) && !(f2_7) && !(f2_6) && !(f2_5) && !(f2_4) && \ 2444 !(f2_3) && !(f2_2) && !(f2_1) && !(f2_0)) {\ 2445 (fm_entry).flags_field_not_present = 1;\ 2446 } else {\ 2447 (fm_entry).mux_sel_flags[0] = (f2_0);\ 2448 (fm_entry).mux_sel_flags[1] = (f2_1);\ 2449 (fm_entry).mux_sel_flags[2] = (f2_2);\ 2450 (fm_entry).mux_sel_flags[3] = (f2_3);\ 2451 (fm_entry).mux_sel_flags[4] = (f2_4);\ 2452 (fm_entry).mux_sel_flags[5] = (f2_5);\ 2453 (fm_entry).mux_sel_flags[6] = (f2_6);\ 2454 (fm_entry).mux_sel_flags[7] = (f2_7);\ 2455 (fm_entry).mux_sel_flags[8] = (f2_8);\ 2456 (fm_entry).mux_sel_flags[9] = (f2_9);\ 2457 (fm_entry).mux_sel_flags[10] = (f2_10);\ 2458 (fm_entry).mux_sel_flags[11] = (f2_11);\ 2459 (fm_entry).mux_sel_flags[12] = (f2_12);\ 2460 (fm_entry).mux_sel_flags[13] = (f2_13);\ 2461 (fm_entry).mux_sel_flags[14] = (f2_14);\ 2462 (fm_entry).mux_sel_flags[15] = (f2_15);\ 2463 }\ 2464 (fm_entry).drop_pkt_when_adm_ctl_deny = (drop_adm_deny);\ 2465 (fm_entry).total_num_cwords = (num_cwords);\ 2466 if ((rsp_type0)) {\ 2467 (fm_entry).lookup_type_rsp[0] = (rsp_type0); \ 2468 }\ 2469 if ((rsp_type1)) {\ 2470 (fm_entry).lookup_type_rsp[1] = (rsp_type1); \ 2471 }\ 2472 if ((rsp_type2)) {\ 2473 (fm_entry).lookup_type_rsp[2] = (rsp_type2); \ 2474 }\ 2475 if ((rsp_type3)) {\ 2476 (fm_entry).lookup_type_rsp[3] = (rsp_type3); \ 2477 }\ 2478 if ((cost0)) {\ 2479 (fm_entry).cost_cw[0] = (cost0); \ 2480 }\ 2481 if ((cost1)) {\ 2482 (fm_entry).cost_cw[1] = (cost1); \ 2483 }\ 2484 if (cost2) {\ 2485 (fm_entry).cost_cw[2] = (cost2); \ 2486 }\ 2487 if (cw0_ltr >= 0) {\ 2488 nl_macro1 = soc_tr3_build_ltr(unit, (cw0_ltr));\ 2489 if (nl_macro1 < 0) {\ 2490 return SOC_E_MEMORY;\ 2491 }\ 2492 }\ 2493 if (cw1_ltr >= 0) {\ 2494 nl_macro2 = soc_tr3_build_ltr(unit, (cw1_ltr));\ 2495 if (nl_macro2 < 0) {\ 2496 return SOC_E_MEMORY;\ 2497 }\ 2498 }\ 2499 if (cw2_ltr >= 0) {\ 2500 nl_macro3 = soc_tr3_build_ltr(unit, (cw2_ltr));\ 2501 if (nl_macro3 < 0) {\ 2502 return SOC_E_MEMORY;\ 2503 }\ 2504 }\ 2505 if ((rsp0_cnt)) {\ 2506 (fm_entry).rsp_index_count[0] = (rsp0_cnt)%4;\ 2507 (fm_entry).eop_cw[0] = (eop_cw0);\ 2508 (fm_entry).num_dwords_cw[0] = (cw0_dwords);\ 2509 (fm_entry).opcode_cw[0] = ((cw0_opc) << 6) | nl_macro1;\ 2510 }\ 2511 (fm_entry).context_addr_lsb_cw[0] = (ctx_addr_lsb0);\ 2512 if ((rsp1_cnt)) {\ 2513 (fm_entry).rsp_index_count[1] = (rsp1_cnt);\ 2514 (fm_entry).eop_cw[1] = (eop_cw1);\ 2515 (fm_entry).num_dwords_cw[1] = (cw1_dwords);\ 2516 (fm_entry).opcode_cw[1] = ((cw1_opc) << 6) | nl_macro2;\ 2517 } else {\ 2518 (fm_entry).eop_cw[1] = 8;\ 2519 }\ 2520 (fm_entry).context_addr_lsb_cw[1] = (ctx_addr_lsb1);\ 2521 if ((rsp2_cnt)) {\ 2522 (fm_entry).rsp_index_count[2] = (rsp2_cnt);\ 2523 (fm_entry).eop_cw[2] = (eop_cw2);\ 2524 (fm_entry).num_dwords_cw[2] = (cw2_dwords);\ 2525 (fm_entry).opcode_cw[2] = ((cw2_opc) << 6) | nl_macro3;\ 2526 } else {\ 2527 (fm_entry).eop_cw[2] = 8;\ 2528 }\ 2529 (fm_entry).context_addr_lsb_cw[2] = (ctx_addr_lsb2);\ 2530 (fm_entry).last_cword_is_optional = (last_cw_opt);\ 2531 (fm_entry).optional_cost[2] = (opt_cost2); \ 2532 (fm_entry).optional_cost[1] = (opt_cost1); \ 2533 (fm_entry).optional_cost[0] = (opt_cost0); \ 2534 } while(0) 2535 2536 int 2537 _soc_tr3_build_fm_table(int unit, soc_tcam_info_t *tcam_info) 2538 { 2539 soc_tcam_partition_t *partitions; 2540 esm_key_to_field_t key_map; 2541 int acl_key_type = 0; 2542 int fwd_l2_present, fwd_ipv4_present, fwd_ipv6_present; 2543 int fwd_ipv6u_present, fwd_ip6_key; 2544 int fwd_ipv6_configured, fwd_ipv6u_configured; 2545 2546 partitions = tcam_info->partitions; 2547 2548 fwd_l2_present = partitions[TCAM_PARTITION_FWD_L2].num_entries || 2549 partitions[TCAM_PARTITION_FWD_L2_WIDE].num_entries; 2550 fwd_ipv4_present = partitions[TCAM_PARTITION_FWD_IP4].num_entries || 2551 partitions[TCAM_PARTITION_FWD_IP4_UCAST].num_entries || 2552 partitions[TCAM_PARTITION_FWD_IP4_UCAST_WIDE].num_entries; 2553 fwd_ipv6_configured = partitions[TCAM_PARTITION_FWD_IP6].num_entries || 2554 partitions[TCAM_PARTITION_FWD_IP6_128_UCAST].num_entries || 2555 partitions[TCAM_PARTITION_FWD_IP6_128_UCAST_WIDE].num_entries; 2556 fwd_ipv6u_configured = (partitions[TCAM_PARTITION_FWD_IP6U].num_entries != 0); 2557 2558 /* 0: v6_64 fwding, 1: v6_128 fwding */ 2559 fwd_ip6_key = soc_property_get(unit, spn_EXT_IP6_FWD_KEY, -1); 2560 if (fwd_ip6_key == -1) { 2561 /* default to v6_64 */ 2562 fwd_ip6_key = 0; 2563 if (!fwd_ipv6u_configured) { 2564 if (fwd_ipv6_configured) { 2565 fwd_ip6_key = 1; 2566 } 2567 } 2568 } 2569 fwd_ipv6u_present = fwd_ipv6u_configured && !fwd_ip6_key; 2570 fwd_ipv6_present = fwd_ipv6_configured && fwd_ip6_key; 2571 2572 if (fwd_l2_present) { 2573 if (!partitions[TCAM_PARTITION_FWD_L2_DUP].num_entries) { 2574 sal_memset(&key_map, 0, sizeof(key_map)); 2575 SOC_TR3_BUILD_FM_ENTRY(key_map, 0, 2576 F11_DA_ETHTYPE_SA_VID_VFI_SEL_VID_VFI_DATA_SRC, 2577 0, 0, 2578 F8_SA_DA_3210, 0, F6_DA_3210, 2579 0, F4_DA_54, 2580 F3_FREE_BIT_VID_VFI_SEL_VID_VFI_DATA_DST, 2581 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2582 0, 0, 0, 0, 0, 0, 1, KEY_GEN_RSP_TYPE_L2_DA, 2583 KEY_GEN_RSP_TYPE_L2_SA, 2584 0, 0, 2585 2, 6, 4, TR3_LTR_LIB_L2_FWD_DA, 2586 TR3_LTR_LIB_L2_FWD_SA, -1, 2, 1, 1, 2587 0, 8, 8, 8, 0, 2, 6, 2, 2, 0, 1, 1, 0, 0, 2588 0, 0, 0); 2589 } else { 2590 SOC_TR3_BUILD_FM_ENTRY(key_map, 0, 2591 F11_DA_ETHTYPE_SA_VID_VFI_SEL_VID_VFI_DATA_SRC, 2592 0, 0, 2593 F8_SA_DA_3210, 0, F6_DA_3210, 2594 0, F4_DA_54, 2595 F3_FREE_BIT_VID_VFI_SEL_VID_VFI_DATA_DST, 2596 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2597 0, 0, 0, 0, 0, 0, 1, KEY_GEN_RSP_TYPE_L2_DA, 2598 KEY_GEN_RSP_TYPE_L2_SA, 2599 0, 0, 2600 1, 5, 2, TR3_LTR_LIB_L2_FWD_DUP, 2601 -1, -1, 1, 2, 0, 2602 0, 8, 8, 8, 0, 4, 6, 4, 0, 0, 1, 0, 0, 0, 2603 0, 0, 0); 2604 } 2605 SOC_IF_ERROR_RETURN(_soc_write_esm_key_id_to_field_map_entry(unit, 2606 KEY_GEN_OFFSET_L2, &key_map)); 2607 } 2608 /* L3 keygen entries */ 2609 sal_memset(&key_map, 0, sizeof(key_map)); 2610 SOC_TR3_BUILD_FM_ENTRY(key_map, 0, 2611 0, 0, 0, F8_SIPV4_DIPV4, 0, 0, 0, 0, F3_FLAGS_IP_1_VRF, 2612 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2613 0, 0, 0, 0, 0, 0, 1, KEY_GEN_RSP_TYPE_DIP, 2614 KEY_GEN_RSP_TYPE_SIP, 0, 0, 2615 2, 6, 4, TR3_LTR_LIB_V4_ONLY_DIP, 2616 TR3_LTR_LIB_V4_ONLY_SIP, -1, 2, 1, 1, 2617 0, 8, 8, 8, 0, 2, 4, 2, 2, 0, 1, 1, 0, 0, 2618 0, 0, 0); 2619 SOC_IF_ERROR_RETURN(_soc_write_esm_key_id_to_field_map_entry(unit, 2620 KEY_GEN_OFFSET_IPV4_ONLY, &key_map)); 2621 2622 sal_memset(&key_map, 0, sizeof(key_map)); 2623 SOC_TR3_BUILD_FM_ENTRY(key_map, 0, 2624 0, F10_SIPV6_U64_DIPV6_U64, 0, 0, 0, 0, 0, 0, 2625 F3_FLAGS_IP_1_VRF, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2626 0, 0, 0, 0, 0, 0, 1, KEY_GEN_RSP_TYPE_DIP, 2627 KEY_GEN_RSP_TYPE_SIP, 0, 0, 2628 2, 6, 4, TR3_LTR_LIB_V6_64_ONLY_DIP, 2629 TR3_LTR_LIB_V6_64_ONLY_SIP, -1, 2, 1, 1, 2630 0, 8, 8, 8, 0, 2, 4, 2, 2, 0, 1, 1, 0, 0, 2631 0, 0, 0); 2632 SOC_IF_ERROR_RETURN(_soc_write_esm_key_id_to_field_map_entry(unit, 2633 KEY_GEN_OFFSET_IPV6_64_ONLY, &key_map)); 2634 2635 sal_memset(&key_map, 0, sizeof(key_map)); 2636 SOC_TR3_BUILD_FM_ENTRY(key_map, 0, 2637 0, 0, F9_SIPV6, 0, 0, F6_SA_3210, 0, F4_FLAGS_IP_1_VRF, 2638 F3_FLAGS_IP_1_VRF, F1_DIPV6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2639 0, 0, 0, 0, 0, 0, 0, 1, KEY_GEN_RSP_TYPE_DIP, 2640 KEY_GEN_RSP_TYPE_SIP, 0, 0, 2641 2, 7, 4, TR3_LTR_LIB_V6_128_ONLY_DIP, 2642 TR3_LTR_LIB_V6_128_ONLY_SIP, -1, 2, 1, 1, 2643 0, 8, 8, 8, 0, 3, 5, 3, 2, 0, 1, 1, 0, 0, 2644 0, 0, 0); 2645 SOC_IF_ERROR_RETURN(_soc_write_esm_key_id_to_field_map_entry(unit, 2646 KEY_GEN_OFFSET_IPV6_128_ONLY, &key_map)); 2647 2648 /* L2 + L3 keygens */ 2649 if (!partitions[TCAM_PARTITION_FWD_IP4_DUP].num_entries) { 2650 SOC_TR3_BUILD_FM_ENTRY(key_map, 0, 2651 F11_DA_ETHTYPE_SA_VID_VFI_SEL_VID_VFI_DATA_SRC, 0, 0, 2652 F8_SIPV4_DIPV4, 0, 0, 0, 0, F3_FLAGS_IP_1_VRF, 2653 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2654 0, 0, 0, 0, 0, 0, 1, KEY_GEN_RSP_TYPE_DIP, 2655 KEY_GEN_RSP_TYPE_SIP, KEY_GEN_RSP_TYPE_L2_SA, 0, 2656 2, 6, 4, TR3_LTR_LIB_V4_ONLY_DIP, 2657 TR3_LTR_LIB_V4_SIP_SA, -1, 2, 1, 2, 2658 0, 8, 8, 8, 0, 2, 4, 2, 2, 0, 1, 1, 0, 0, 2659 0, 0, 0); 2660 } else { 2661 SOC_TR3_BUILD_FM_ENTRY(key_map, 0, 2662 F11_DA_ETHTYPE_SA_VID_VFI_SEL_VID_VFI_DATA_SRC, 0, 0, 2663 F8_SIPV4_DIPV4, 0, 0, 0, 0, F3_FLAGS_IP_1_VRF, 2664 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2665 0, 0, 0, 0, 0, 0, 1, KEY_GEN_RSP_TYPE_SIP, 2666 KEY_GEN_RSP_TYPE_L2_SA, KEY_GEN_RSP_TYPE_DIP, 0, 2667 1, 5, 3, TR3_LTR_LIB_V4_DUP, 2668 -1, -1, 1, 3, 0, 2669 0, 8, 8, 8, 0, 4, 6, 4, 0, 0, 1, 0, 0, 0, 2670 0, 0, 0); 2671 } 2672 SOC_IF_ERROR_RETURN(_soc_write_esm_key_id_to_field_map_entry(unit, 2673 KEY_GEN_OFFSET_IPV4_SA, &key_map)); 2674 2675 /* L2 + L3 keygens */ 2676 sal_memset(&key_map, 0, sizeof(key_map)); 2677 if (!partitions[TCAM_PARTITION_FWD_IP6_DUP].num_entries) { 2678 SOC_TR3_BUILD_FM_ENTRY(key_map, 0, 2679 0, 0, F9_SIPV6, F8_SA_3210_DA_3210, 0, F6_SA_54_DA_54, 2680 0, F4_FREE_BIT_VID_VFI_SEL_VID_VFI_DATA_SRC, 2681 F3_FLAGS_IP_1_VRF, F1_DIPV6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2682 0, 0, 0, 0, 0, 0, 0, 1, KEY_GEN_RSP_TYPE_DIP, 2683 KEY_GEN_RSP_TYPE_SIP, KEY_GEN_RSP_TYPE_L2_SA, 0, 2684 2, 8, 4, TR3_LTR_LIB_V6_128_ONLY_DIP, 2685 TR3_LTR_LIB_V6_128_SIP_SA, -1, 2, 1, 2, 2686 0, 8, 8, 8, 0, 3, 6, 3, 3, 0, 1, 1, 0, 0, 2687 0, 0, 0); 2688 } else { 2689 SOC_TR3_BUILD_FM_ENTRY(key_map, 0, 2690 0, 0, F9_SIPV6, F8_SA_3210_DA_3210, 0, F6_SA_54_DA_54, 2691 0, F4_FREE_BIT_VID_VFI_SEL_VID_VFI_DATA_SRC, 2692 F3_FLAGS_IP_1_VRF, F1_DIPV6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2693 0, 0, 0, 0, 0, 0, 0, 1, KEY_GEN_RSP_TYPE_SIP, 2694 KEY_GEN_RSP_TYPE_L2_SA, KEY_GEN_RSP_TYPE_DIP, 0, 2695 1, 7, 3, TR3_LTR_LIB_V6_128_DUP, 2696 -1, -1, 1, 3, 0, 2697 0, 8, 8, 8, 0, 6, 6, 6, 0, 0, 1, 0, 0, 0, 2698 0, 0, 0); 2699 } 2700 SOC_IF_ERROR_RETURN(_soc_write_esm_key_id_to_field_map_entry(unit, 2701 KEY_GEN_OFFSET_IPV6_128_SA, &key_map)); 2702 2703 /* L2 + L3 keygens */ 2704 sal_memset(&key_map, 0, sizeof(key_map)); 2705 if (!partitions[TCAM_PARTITION_FWD_IP6U_DUP].num_entries) { 2706 SOC_TR3_BUILD_FM_ENTRY(key_map, 0, 2707 F11_DA_ETHTYPE_SA_VID_VFI_SEL_VID_VFI_DATA_SRC, 2708 F10_SIPV6_U64_DIPV6_U64, 2709 0, 0, 0, 0, 2710 0, 0, F3_FLAGS_IP_1_VRF, 0, 0, 0, 0, 0, 0, 0, 2711 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, KEY_GEN_RSP_TYPE_DIP, 2712 KEY_GEN_RSP_TYPE_SIP, KEY_GEN_RSP_TYPE_L2_SA, 0, 2713 2, 6, 4, TR3_LTR_LIB_V6_64_ONLY_DIP, 2714 TR3_LTR_LIB_V6_64_SIP_SA, -1, 2, 1, 2, 2715 0, 8, 8, 8, 0, 2, 6, 2, 2, 0, 1, 1, 0, 0, 2716 0, 0, 0); 2717 } else { 2718 SOC_TR3_BUILD_FM_ENTRY(key_map, 0, 2719 F11_DA_ETHTYPE_SA_VID_VFI_SEL_VID_VFI_DATA_SRC, 2720 F10_SIPV6_U64_DIPV6_U64, 2721 0, 0, 0, 0, 2722 0, 0, F3_FLAGS_IP_1_VRF, 0, 0, 0, 0, 0, 0, 0, 2723 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, KEY_GEN_RSP_TYPE_SIP, 2724 KEY_GEN_RSP_TYPE_L2_SA, KEY_GEN_RSP_TYPE_DIP, 0, 2725 1, 5, 3, TR3_LTR_LIB_V6_64_DUP, 2726 -1, -1, 1, 3, 0, 2727 0, 8, 8, 8, 0, 4, 6, 4, 0, 0, 1, 0, 0, 0, 2728 0, 0, 0); 2729 } 2730 SOC_IF_ERROR_RETURN(_soc_write_esm_key_id_to_field_map_entry(unit, 2731 KEY_GEN_OFFSET_IPV6_64_SA, &key_map)); 2732 2733 sal_memset(&key_map, 0, sizeof(key_map)); 2734 SOC_TR3_BUILD_FM_ENTRY(key_map, 0, 2735 F11_DA_ETHTYPE_SA_VID_VFI_SEL_VID_VFI_DATA_SRC, 2736 0, 0, 2737 F8_SA_DA_3210, 2738 0, F6_DA_3210, 2739 0, 0, 2740 F3_FREE_BIT_VID_VFI_SEL_VID_VFI_DATA_DST, 2741 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2742 0, 0, 0, 0, 1, KEY_GEN_RSP_TYPE_L2_SA, 2743 0, 0, 0, 2744 3, 0, 0, 2745 TR3_LTR_LIB_L2_FWD_SA, -1, -1, 1, 1, 2746 0, 0, 8, 0, 0, 0, 0, 0, 2, 2747 0, 0, 1, 0, 0, 0, 0, 0, 0); 2748 SOC_IF_ERROR_RETURN(_soc_write_esm_key_id_to_field_map_entry(unit, 2749 KEY_GEN_OFFSET_TR3_WAR_L2SA_ONLY, &key_map)); 2750 2751 /* ACL7 + V6_128 + SA */ 2752 if (partitions[TCAM_PARTITION_ACL480].num_entries) { 2753 sal_memset(&key_map, 0, sizeof(key_map)); 2754 SOC_TR3_BUILD_FM_ENTRY(key_map, 0, 2755 F11_SA_OTAG_DA_ETHTYPE, 2756 0, F9_SIPV6, 2757 0, 2758 F7_L4_SRC_L4_DST, F6_OTAG_ITAG, 2759 0, F4_FLAGS_IP_1_VRF, 2760 F3_FREE_BIT_VID_VFI_SEL_VID_VFI_DATA_SRC, 2761 F1_DIPV6, F2_FLAG_RESERVED_0, 2762 F2_FLAG_RESERVED_0, 2763 F2_FLAG_RESERVED_0, F2_FLAG_RESERVED_0, 2764 F2_FLAG_L3_PROTOCOL_FN_3, 2765 F2_FLAG_L3_PROTOCOL_FN_2, 2766 F2_FLAG_L3_PROTOCOL_FN_1, 2767 F2_FLAG_L3_PROTOCOL_FN_0, 2768 F2_FLAG_TOS_7, 2769 F2_FLAG_TOS_6, 2770 F2_FLAG_TOS_5, 2771 F2_FLAG_TOS_4, 2772 F2_FLAG_TOS_3, 2773 F2_FLAG_TOS_2, 2774 F2_FLAG_TOS_1, 2775 F2_FLAG_TOS_0, 2776 1, KEY_GEN_RSP_TYPE_DIP, 2777 KEY_GEN_RSP_TYPE_ACL, KEY_GEN_RSP_TYPE_SIP, 2778 KEY_GEN_RSP_TYPE_L2_SA, 2779 3, 10, 5, TR3_LTR_LIB_AFLSS0_DIP, 2780 TR3_LTR_LIB_AFLSS0_ACL_SIP_SA, -1, 2, 1, 2781 3, 0, 8, 8, 8, 0, 4, 7, 5, 3, 0, 1, 2, 0, 0, 2782 0, 0, 0); 2783 SOC_IF_ERROR_RETURN(_soc_write_esm_key_id_to_field_map_entry(unit, 2784 KEY_GEN_OFFSET_AFLSS0, &key_map)); 2785 2786 /* AFLSS2: ACL480 + V6_64_FWD + SA */ 2787 sal_memset(&key_map, 0, sizeof(key_map)); 2788 SOC_TR3_BUILD_FM_ENTRY(key_map, 0, 2789 F11_SA_OTAG_DA_ETHTYPE, 2790 0, F9_SIPV6, 2791 0, 2792 F7_L4_SRC_L4_DST, F6_OTAG_ITAG, 2793 0, F4_FLAGS_IP_1_VRF, 2794 F3_FREE_BIT_VID_VFI_SEL_VID_VFI_DATA_SRC, 2795 F1_DIPV6, 0, 2796 0, 0, 0, F2_FLAG_L3_PROTOCOL_FN_3, 2797 F2_FLAG_L3_PROTOCOL_FN_2, 2798 F2_FLAG_L3_PROTOCOL_FN_1, 2799 F2_FLAG_L3_PROTOCOL_FN_0, 2800 F2_FLAG_TOS_7, 2801 F2_FLAG_TOS_6, 2802 F2_FLAG_TOS_5, 2803 F2_FLAG_TOS_4, 2804 F2_FLAG_TOS_3, 2805 F2_FLAG_TOS_2, 2806 F2_FLAG_TOS_1, 2807 F2_FLAG_TOS_0, 2808 1, KEY_GEN_RSP_TYPE_DIP, 2809 KEY_GEN_RSP_TYPE_ACL, KEY_GEN_RSP_TYPE_SIP, 2810 KEY_GEN_RSP_TYPE_L2_SA, 2811 3, 8, 5, TR3_LTR_LIB_AFLSS2_DIP, 2812 TR3_LTR_LIB_AFLSS2_ACL_SIP_SA, -1, 2, 1, 2813 3, 0, 8, 8, 8, 0, 4, 6, 4, 2, 0, 1, 2, 0, 0, 2814 0, 0, 0); 2815 SOC_IF_ERROR_RETURN(_soc_write_esm_key_id_to_field_map_entry(unit, 2816 KEY_GEN_OFFSET_AFLSS2, &key_map)); 2817 } 2818 2819 if (partitions[TCAM_PARTITION_ACL320].num_entries) { 2820 /* AFLSS1: ACL320 + V4_FWD + SA */ 2821 sal_memset(&key_map, 0, sizeof(key_map)); 2822 SOC_TR3_BUILD_FM_ENTRY(key_map, 0, 2823 F11_SA_OTAG_DA_ETHTYPE, 2824 0, 0, 2825 0, 2826 F7_L4_SRC_L4_DST, F6_OTAG_ITAG, 2827 0, F4_FLAGS_IP_1_VRF, 2828 F3_FREE_BIT_VID_VFI_SEL_VID_VFI_DATA_SRC, 2829 0, 0, 2830 0, 0, 0, F2_FLAG_L3_PROTOCOL_FN_3, 2831 F2_FLAG_L3_PROTOCOL_FN_2, 2832 F2_FLAG_L3_PROTOCOL_FN_1, 2833 F2_FLAG_L3_PROTOCOL_FN_0, 2834 0, 0, 0, 0, 0, 0, 0, 0, 2835 1, KEY_GEN_RSP_TYPE_DIP, 2836 KEY_GEN_RSP_TYPE_ACL, KEY_GEN_RSP_TYPE_SIP, 2837 KEY_GEN_RSP_TYPE_L2_SA, 2838 2, 7, 5, TR3_LTR_LIB_AFLSS1_DIP, 2839 TR3_LTR_LIB_AFLSS1_ACL_SIP_SA, -1, 2, 1, 2840 3, 0, 8, 8, 8, 0, 3, 6, 3, 2, 0, 1, 1, 0, 0, 2841 0, 0, 0); 2842 SOC_IF_ERROR_RETURN(_soc_write_esm_key_id_to_field_map_entry(unit, 2843 KEY_GEN_OFFSET_AFLSS1, &key_map)); 2844 2845 /* AFLSS0A: ACL320 + V6_128_FWD + SA */ 2846 sal_memset(&key_map, 0, sizeof(key_map)); 2847 SOC_TR3_BUILD_FM_ENTRY(key_map, 0, 2848 F11_DA_ETHTYPE_SA_VID_VFI_SEL_VID_VFI_DATA_SRC, 2849 0, F9_SIPV6, 0, F7_L4_SRC_L4_DST, 0, 2850 0, F4_FLAGS_IP_1_VRF, 0, 2851 F1_DIPV6, 0, 0, 0, 0, F2_FLAG_L3_PROTOCOL_FN_3, 2852 F2_FLAG_L3_PROTOCOL_FN_2, 2853 F2_FLAG_L3_PROTOCOL_FN_1, 2854 F2_FLAG_L3_PROTOCOL_FN_0, 2855 F2_FLAG_TOS_7, F2_FLAG_TOS_6, F2_FLAG_TOS_5, 2856 F2_FLAG_TOS_4, F2_FLAG_TOS_3, F2_FLAG_TOS_2, 2857 F2_FLAG_TOS_1, F2_FLAG_TOS_0, 2858 1, KEY_GEN_RSP_TYPE_DIP, 2859 KEY_GEN_RSP_TYPE_ACL, KEY_GEN_RSP_TYPE_SIP, 2860 KEY_GEN_RSP_TYPE_L2_SA, 2861 2, 8, 5, TR3_LTR_LIB_AFLSS0A_DIP, 2862 TR3_LTR_LIB_AFLSS0A_ACL_SIP_SA, -1, 2, 1, 2863 3, 0, 8, 8, 8, 0, 3, 7, 3, 3, 0, 1, 1, 0, 0, 2864 0, 0, 0); 2865 SOC_IF_ERROR_RETURN(_soc_write_esm_key_id_to_field_map_entry(unit, 2866 KEY_GEN_OFFSET_AFLSS0A, &key_map)); 2867 2868 /* AFLSS2A: ACL320 + V6_64_FWD + SA */ 2869 sal_memset(&key_map, 0, sizeof(key_map)); 2870 SOC_TR3_BUILD_FM_ENTRY(key_map, 0, 2871 F11_DA_ETHTYPE_SA_VID_VFI_SEL_VID_VFI_DATA_SRC, 2872 F10_SIPV6_U64_DIPV6_U64, 0, 0, 0, 0, 2873 F5_L4_SRC, F4_L4_DST, F3_FLAGS_IP_1_VRF, 2874 0, 0, 0, 0, 0, F2_FLAG_L3_PROTOCOL_FN_3, 2875 F2_FLAG_L3_PROTOCOL_FN_2, 2876 F2_FLAG_L3_PROTOCOL_FN_1, 2877 F2_FLAG_L3_PROTOCOL_FN_0, 2878 F2_FLAG_TOS_7, F2_FLAG_TOS_6, F2_FLAG_TOS_5, 2879 F2_FLAG_TOS_4, F2_FLAG_TOS_3, F2_FLAG_TOS_2, 2880 F2_FLAG_TOS_1, F2_FLAG_TOS_0, 2881 1, KEY_GEN_RSP_TYPE_DIP, 2882 KEY_GEN_RSP_TYPE_ACL, KEY_GEN_RSP_TYPE_SIP, 2883 KEY_GEN_RSP_TYPE_L2_SA, 2884 2, 6, 5, TR3_LTR_LIB_AFLSS2A_DIP, 2885 TR3_LTR_LIB_AFLSS2A_ACL_SIP_SA, -1, 2, 1, 2886 3, 0, 8, 8, 8, 0, 2, 4, 2, 2, 0, 1, 1, 0, 0, 2887 0, 0, 0); 2888 SOC_IF_ERROR_RETURN(_soc_write_esm_key_id_to_field_map_entry(unit, 2889 KEY_GEN_OFFSET_AFLSS2A, &key_map)); 2890 } 2891 2892 if (partitions[TCAM_PARTITION_ACL160].num_entries) { 2893 /* AFLSS3: ACL160 + L2_FWD */ 2894 sal_memset(&key_map, 0, sizeof(key_map)); 2895 SOC_TR3_BUILD_FM_ENTRY(key_map, 0, 2896 F11_DA_ETHTYPE_SA_VID_VFI_SEL_VID_VFI_DATA_SRC, 2897 0, 0, 0, F7_OTAG_ITAG, F6_DA_3210, 2898 0, F4_DA_54, 2899 F3_FREE_BIT_VID_VFI_SEL_VID_VFI_DATA_SRC, 2900 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2901 0, 0, 1, KEY_GEN_RSP_TYPE_L2_DA, 2902 KEY_GEN_RSP_TYPE_ACL, KEY_GEN_RSP_TYPE_L2_SA, 2903 0, 2, 6, 4, TR3_LTR_LIB_L2_FWD_DA, 2904 TR3_LTR_LIB_AFLSS3_ACL_SA, -1, 2, 1, 2905 2, 0, 8, 8, 8, 0, 2, 4, 2, 2, 0, 1, 1, 0, 0, 2906 0, 0, 0); 2907 SOC_IF_ERROR_RETURN(_soc_write_esm_key_id_to_field_map_entry(unit, 2908 KEY_GEN_OFFSET_AFLSS3, &key_map)); 2909 2910 /* AFLSS1A: ACL160 + V4_FWD + SA */ 2911 sal_memset(&key_map, 0, sizeof(key_map)); 2912 SOC_TR3_BUILD_FM_ENTRY(key_map, 0, 2913 F11_DA_ETHTYPE_SA_VID_VFI_SEL_VID_VFI_DATA_SRC, 2914 0, 0, F8_SIPV4_DIPV4, F7_L4_SRC_L4_DST, 0, 2915 0, F4_FLAGS_IP_1_VRF, 0, 2916 0, 0, 0, 0, 0, F2_FLAG_L3_PROTOCOL_FN_3, 2917 F2_FLAG_L3_PROTOCOL_FN_2, 2918 F2_FLAG_L3_PROTOCOL_FN_1, 2919 F2_FLAG_L3_PROTOCOL_FN_0, 2920 0, 0, 0, 0, 0, 0, 0, 0, 2921 1, KEY_GEN_RSP_TYPE_DIP, 2922 KEY_GEN_RSP_TYPE_ACL, KEY_GEN_RSP_TYPE_SIP, 2923 KEY_GEN_RSP_TYPE_L2_SA, 2924 2, 6, 5, TR3_LTR_LIB_AFLSS1A_DIP, 2925 TR3_LTR_LIB_AFLSS1A_ACL_SIP_SA, -1, 2, 1, 2926 3, 0, 8, 8, 8, 0, 2, 4, 2, 2, 0, 1, 1, 0, 0, 2927 0, 0, 0); 2928 SOC_IF_ERROR_RETURN(_soc_write_esm_key_id_to_field_map_entry(unit, 2929 KEY_GEN_OFFSET_AFLSS1A, &key_map)); 2930 2931 /* AFLSS1MP: ACL160 + V4_FWD + SA */ 2932 sal_memset(&key_map, 0, sizeof(key_map)); 2933 SOC_TR3_BUILD_FM_ENTRY(key_map, 0, 2934 F11_DA_ETHTYPE_SA_VID_VFI_SEL_VID_VFI_DATA_SRC, 2935 0, 0, F8_SIPV4_DIPV4, F7_L4_SRC_L4_DST, 0, 2936 0, F4_FLAGS_IP_1_VRF, 0, 2937 0, 0, 0, 0, 0, F2_FLAG_L3_PROTOCOL_FN_3, 2938 F2_FLAG_L3_PROTOCOL_FN_2, 2939 F2_FLAG_L3_PROTOCOL_FN_1, 2940 F2_FLAG_L3_PROTOCOL_FN_0, 2941 0, 0, 0, 0, 0, 0, 0, 0, 2942 1, KEY_GEN_RSP_TYPE_ACL, 2943 KEY_GEN_RSP_TYPE_DIP, KEY_GEN_RSP_TYPE_SIP, 2944 KEY_GEN_RSP_TYPE_L2_SA, 2945 1, 4, 3, TR3_LTR_LIB_AFLSS1AMP, 2946 -1, -1, 1, 4, 2947 0, 0, 8, 8, 8, 0, 3, 3, 3, 0, 0, 1, 1, 0, 0, 2948 0, 0, 0); 2949 SOC_IF_ERROR_RETURN(_soc_write_esm_key_id_to_field_map_entry(unit, 2950 KEY_GEN_OFFSET_AFLSS1MP, &key_map)); 2951 } 2952 2953 /* FLSS0 */ 2954 sal_memset(&key_map, 0, sizeof(key_map)); 2955 SOC_TR3_BUILD_FM_ENTRY(key_map, 0, 2956 F11_DA_ETHTYPE_SA_VID_VFI_SEL_VID_VFI_DATA_SRC, 2957 0, F9_SIPV6, 0, F7_L4_SRC_L4_DST, 0, 2958 0, F4_FLAGS_IP_1_VRF, 2959 F3_FREE_BIT_VID_VFI_SEL_VID_VFI_DATA_DST, 2960 F1_DIPV6, 0, 0, 0, 0, 0, 0, 0, 0, 2961 0, 0, 0, 0, 0, 0, 0, 0, 2962 1, KEY_GEN_RSP_TYPE_DIP, 2963 KEY_GEN_RSP_TYPE_SIP, KEY_GEN_RSP_TYPE_L2_SA, 2964 0, 3, 10, 6, TR3_LTR_LIB_AFLSS0A_DIP, 2965 TR3_LTR_LIB_FLSS0_SIP, TR3_LTR_LIB_FLSS0_SA, 3, 1, 2966 1, 1, 8, 8, 8, 0, 3, 5, 3, 2, 5, 1, 1, 1, 0, 2967 0, 0, 0); 2968 SOC_IF_ERROR_RETURN(_soc_write_esm_key_id_to_field_map_entry(unit, 2969 KEY_GEN_OFFSET_FLSS0, &key_map)); 2970 2971 /* TR2 L2_ACLC */ 2972 if (partitions[TCAM_PARTITION_ACL_L2C].num_entries) { 2973 if (fwd_ipv4_present) { 2974 sal_memset(&key_map, 0, sizeof(key_map)); 2975 SOC_TR3_BUILD_FM_ENTRY(key_map, 0, 2976 F11_DA_ETHTYPE_SA_VID_VFI_SEL_VID_VFI_DATA_SRC, 2977 0, 0, F8_OTAG_DA, F7_SIPV4, F6_DIPV4, 2978 F5_SGLP, F4_FLAGS_IP_1_VRF, 2979 F3_FREE_BIT_VID_VFI_SEL_VID_VFI_DATA_DST, 2980 0, 0, 0, 0, 0, 0, 0, 0, 0, 2981 0, 0, 0, 0, 0, 0, 0, F2_FLAG_MH_MIRROR_ONLY, 2982 1, KEY_GEN_RSP_TYPE_DIP, 2983 KEY_GEN_RSP_TYPE_L2_SA, KEY_GEN_RSP_TYPE_ACL, 2984 KEY_GEN_RSP_TYPE_SIP, 2, 7, 5, 2985 TR3_LTR_LIB_ACL_L2C_DIP, 2986 TR3_LTR_LIB_ACL_L2C_SA_ACL_SIP, -1, 2, 1, 2987 3, 0, 8, 8, 8, 0, 2, 5, 2, 3, 0, 1, 1, 0, 0, 2988 0, 0, 0); 2989 SOC_IF_ERROR_RETURN(_soc_write_esm_key_id_to_field_map_entry(unit, 2990 KEY_GEN_OFFSET_TR2_ACL_L2C_IP4, &key_map)); 2991 } 2992 if (fwd_ipv6u_present) { 2993 sal_memset(&key_map, 0, sizeof(key_map)); 2994 SOC_TR3_BUILD_FM_ENTRY(key_map, 0, 2995 F11_DA_ETHTYPE_SA_VID_VFI_SEL_VID_VFI_DATA_SRC, 2996 F10_SIPV6_U64_DIPV6_U64, 0, F8_OTAG_DA, 0, 0, 2997 F5_SGLP, F4_FLAGS_IP_1_VRF, 2998 F3_FREE_BIT_VID_VFI_SEL_VID_VFI_DATA_DST, 2999 0, 0, 0, 0, 0, 0, 0, 0, 0, 3000 0, 0, 0, 0, 0, 0, 0, F2_FLAG_MH_MIRROR_ONLY, 3001 1, KEY_GEN_RSP_TYPE_DIP, 3002 KEY_GEN_RSP_TYPE_L2_SA, KEY_GEN_RSP_TYPE_ACL, 3003 KEY_GEN_RSP_TYPE_SIP, 2, 8, 5, 3004 TR3_LTR_LIB_ACL_L2C_DIPV6_64, 3005 TR3_LTR_LIB_ACL_L2C_SA_ACL_SIPV6_64, -1, 2, 1, 3006 3, 0, 8, 8, 8, 0, 4, 6, 4, 2, 0, 1, 1, 0, 0, 3007 0, 0, 0); 3008 SOC_IF_ERROR_RETURN(_soc_write_esm_key_id_to_field_map_entry(unit, 3009 KEY_GEN_OFFSET_TR2_ACL_L2C_IP6U, &key_map)); 3010 } 3011 if (fwd_ipv6_present) { 3012 sal_memset(&key_map, 0, sizeof(key_map)); 3013 SOC_TR3_BUILD_FM_ENTRY(key_map, 0, 3014 F11_DA_ETHTYPE_SA_VID_VFI_SEL_VID_VFI_DATA_SRC, 3015 0, F9_SIPV6, F8_OTAG_DA, 0, 0, 3016 F5_SGLP, F4_FLAGS_IP_1_VRF, 3017 F3_FREE_BIT_VID_VFI_SEL_VID_VFI_DATA_DST, 3018 F1_DIPV6, 0, 0, 0, 0, 0, 0, 0, 0, 3019 0, 0, 0, 0, 0, 0, 0, F2_FLAG_MH_MIRROR_ONLY, 3020 1, KEY_GEN_RSP_TYPE_DIP, 3021 KEY_GEN_RSP_TYPE_L2_SA, KEY_GEN_RSP_TYPE_ACL, 3022 KEY_GEN_RSP_TYPE_SIP, 2, 10, 5, 3023 TR3_LTR_LIB_ACL_L2C_DIPV6_128, 3024 TR3_LTR_LIB_ACL_L2C_SA_ACL_SIPV6_128, -1, 2, 1, 3025 3, 0, 8, 8, 8, 0, 4, 7, 4, 4, 0, 1, 1, 0, 0, 3026 0, 0, 0); 3027 SOC_IF_ERROR_RETURN(_soc_write_esm_key_id_to_field_map_entry(unit, 3028 KEY_GEN_OFFSET_TR2_ACL_L2C_IP6, &key_map)); 3029 } 3030 if (fwd_l2_present) { 3031 sal_memset(&key_map, 0, sizeof(key_map)); 3032 SOC_TR3_BUILD_FM_ENTRY(key_map, 0, 3033 F11_DA_ETHTYPE_SA_VID_VFI_SEL_VID_VFI_DATA_SRC, 3034 0, 0, F8_OTAG_DA, 0, 0, 3035 F5_SGLP, F4_DA_54, 3036 F3_FREE_BIT_VID_VFI_SEL_VID_VFI_DATA_DST, 3037 0, 0, 0, 0, 0, 0, 0, 0, 0, 3038 0, 0, 0, 0, 0, 0, 0, F2_FLAG_MH_MIRROR_ONLY, 3039 1, KEY_GEN_RSP_TYPE_L2_DA, 3040 KEY_GEN_RSP_TYPE_L2_SA, KEY_GEN_RSP_TYPE_ACL, 3041 0, 2, 6, 4, TR3_LTR_LIB_ACL_L2C_DA, 3042 TR3_LTR_LIB_ACL_L2C_SA_ACL, -1, 2, 1, 3043 2, 0, 8, 8, 8, 0, 2, 4, 2, 2, 0, 1, 1, 0, 0, 3044 0, 0, 0); 3045 SOC_IF_ERROR_RETURN(_soc_write_esm_key_id_to_field_map_entry(unit, 3046 KEY_GEN_OFFSET_TR2_ACL_L2C, &key_map)); 3047 } 3048 if (!fwd_ipv4_present || !fwd_ipv6u_present || !fwd_ipv6_present || 3049 !fwd_l2_present) { 3050 /* install ACL only */ 3051 sal_memset(&key_map, 0, sizeof(key_map)); 3052 SOC_TR3_BUILD_FM_ENTRY(key_map, 0, 3053 F11_DA_ETHTYPE_SA_VID_VFI_SEL_VID_VFI_DATA_SRC, 3054 0, 0, F8_OTAG_DA, 0, 0, 3055 F5_SGLP, F4_DA_54, 3056 F3_FREE_BIT_VID_VFI_SEL_VID_VFI_DATA_DST, 3057 0, 0, 0, 0, 0, 0, 0, 0, 0, 3058 0, 0, 0, 0, 0, 0, 0, F2_FLAG_MH_MIRROR_ONLY, 3059 1, KEY_GEN_RSP_TYPE_ACL, 3060 0, 0, 3061 0, 1, 5, 2, TR3_LTR_LIB_ACL_L2C_ONLY, 3062 -1, -1, 1, 1, 3063 0, 0, 8, 8, 8, 0, 4, 6, 4, 0, 0, 1, 0, 0, 0, 3064 0, 0, 0); 3065 SOC_IF_ERROR_RETURN(_soc_write_esm_key_id_to_field_map_entry(unit, 3066 KEY_GEN_OFFSET_TR2_ACL_L2C_ONLY, &key_map)); 3067 } 3068 } 3069 3070 /* TR2 L2_ACL (non7k) */ 3071 if (partitions[TCAM_PARTITION_ACL_L2].num_entries) { 3072 if (fwd_l2_present) { 3073 sal_memset(&key_map, 0, sizeof(key_map)); 3074 /* TR2 L2_ACL (non7k) */ 3075 SOC_TR3_BUILD_FM_ENTRY(key_map, 0, 3076 F11_DA_ETHTYPE_SA_VID_VFI_SEL_VID_VFI_DATA_SRC, 3077 F10_UDF1, 0, F8_OTAG_DA, F7_SGLP_DGLP, 3078 F6_CLASSID_ALL, F5_FLAGS_IP_1_VRF, F4_ITAG, 3079 F3_UDF_1_AND_2_VALID, 3080 0, 0, F2_FLAG_HG, F2_FLAG_L3_TYPE_3, 3081 F2_FLAG_L3_TYPE_2, F2_FLAG_L3_TYPE_1, 3082 F2_FLAG_L3_TYPE_0, 3083 F2_FLAG_LOOKUP_STATUS_VECTOR_15, 3084 F2_FLAG_INCOMING_TAG_STATUS_1, 3085 F2_FLAG_INCOMING_TAG_STATUS_0, 3086 F2_FLAG_MH_MIRROR_ONLY, 3087 F2_FLAG_LOOKUP_STATUS_VECTOR_0, 3088 F2_FLAG_ESM_KEY_SUBTYPE_0, 3089 F2_FLAG_MY_STATION_HIT, 3090 F2_FLAG_FORWARDING_TYPE_2, 3091 F2_FLAG_FORWARDING_TYPE_1, F2_FLAG_L3_IIF_VALID, 3092 1, KEY_GEN_RSP_TYPE_L2_DA, 3093 KEY_GEN_RSP_TYPE_L2_SA, KEY_GEN_RSP_TYPE_ACL, 3094 0, 2, 9, 5, TR3_LTR_LIB_ACL_L2_DA, 3095 TR3_LTR_LIB_ACL_L2_SA_ACL_N7K, -1, 2, 1, 3096 2, 0, 8, 8, 8, 0, 5, 7, 6, 2, 0, 1, 1, 0, 0, 3097 0, 0, 0); 3098 SOC_IF_ERROR_RETURN(_soc_write_esm_key_id_to_field_map_entry(unit, 3099 KEY_GEN_OFFSET_TR2_ACL_L2_NON7K_SGLP, &key_map)); 3100 3101 /* create a SVP variant */ 3102 key_map.f_selects[7] = F7_SVP_DVP; 3103 key_map.esm_key_subtype = 1; /* SVP gets bit 1 in flags */ 3104 SOC_IF_ERROR_RETURN(_soc_write_esm_key_id_to_field_map_entry(unit, 3105 KEY_GEN_OFFSET_TR2_ACL_L2_NON7K_SVP, &key_map)); 3106 3107 /* TR2 L2_ACL (7k) */ 3108 SOC_TR3_BUILD_FM_ENTRY(key_map, 0, 3109 F11_DA_ETHTYPE_SA_VID_VFI_SEL_VID_VFI_DATA_SRC, 3110 F10_UDF1, 0, F8_OTAG_DA, F7_SGLP_DGLP, 3111 F6_CLASSID_ALL, F5_INT_RANGE_CHECK, F4_ITAG, 3112 F3_UDF_1_AND_2_VALID, 3113 0, 0, F2_FLAG_HG, F2_FLAG_L3_TYPE_3, 3114 F2_FLAG_L3_TYPE_2, F2_FLAG_L3_TYPE_1, 3115 F2_FLAG_L3_TYPE_0, 3116 F2_FLAG_LOOKUP_STATUS_VECTOR_15, 3117 F2_FLAG_INCOMING_TAG_STATUS_1, 3118 F2_FLAG_INCOMING_TAG_STATUS_0, 3119 F2_FLAG_MH_MIRROR_ONLY, 3120 F2_FLAG_LOOKUP_STATUS_VECTOR_0, 3121 F2_FLAG_ESM_KEY_SUBTYPE_0, 3122 F2_FLAG_MY_STATION_HIT, 3123 F2_FLAG_FORWARDING_TYPE_2, 3124 F2_FLAG_FORWARDING_TYPE_1, F2_FLAG_L3_IIF_VALID, 3125 1, KEY_GEN_RSP_TYPE_L2_DA, 3126 KEY_GEN_RSP_TYPE_L2_SA, KEY_GEN_RSP_TYPE_ACL, 3127 0, 2, 9, 5, TR3_LTR_LIB_ACL_L2_DA, 3128 TR3_LTR_LIB_ACL_L2_SA_ACL, -1, 2, 1, 3129 2, 0, 8, 8, 8, 0, 5, 7, 6, 2, 0, 1, 1, 0, 0, 3130 0, 0, 0); 3131 SOC_IF_ERROR_RETURN(_soc_write_esm_key_id_to_field_map_entry(unit, 3132 KEY_GEN_OFFSET_TR2_ACL_L2_7K_SGLP, &key_map)); 3133 3134 key_map.f_selects[7] = F7_SVP_DVP; 3135 key_map.esm_key_subtype = 0; /* SGLP gets bit 0 in flags */ 3136 SOC_IF_ERROR_RETURN(_soc_write_esm_key_id_to_field_map_entry(unit, 3137 KEY_GEN_OFFSET_TR2_ACL_L2_7K_SVP, &key_map)); 3138 } 3139 if (fwd_ipv6u_present) { 3140 /* only SGLP variant makes sense */ 3141 sal_memset(&key_map, 0, sizeof(key_map)); 3142 /* TR2 L2_ACL (non7k) */ 3143 SOC_TR3_BUILD_FM_ENTRY(key_map, 0, 3144 F11_DA_ETHTYPE_SA_VID_VFI_SEL_VID_VFI_DATA_SRC, 3145 F10_SIPV6_U64_DIPV6_U64, F9_UDF1, F8_OTAG_DA, 3146 F7_SGLP_DGLP, F6_CLASSID_ALL, 3147 F5_FLAGS_IP_1_VRF, 3148 F4_ITAG, 3149 F3_UDF_1_AND_2_VALID, 3150 0, 0, F2_FLAG_HG, F2_FLAG_L3_TYPE_3, 3151 F2_FLAG_L3_TYPE_2, F2_FLAG_L3_TYPE_1, 3152 F2_FLAG_L3_TYPE_0, 3153 F2_FLAG_LOOKUP_STATUS_VECTOR_15, 3154 F2_FLAG_INCOMING_TAG_STATUS_1, 3155 F2_FLAG_INCOMING_TAG_STATUS_0, 3156 F2_FLAG_MH_MIRROR_ONLY, 3157 F2_FLAG_LOOKUP_STATUS_VECTOR_0, 3158 F2_FLAG_ESM_KEY_SUBTYPE_0, 3159 F2_FLAG_MY_STATION_HIT, 3160 F2_FLAG_FORWARDING_TYPE_2, 3161 F2_FLAG_FORWARDING_TYPE_1, F2_FLAG_L3_IIF_VALID, 3162 1, KEY_GEN_RSP_TYPE_DIP, 3163 KEY_GEN_RSP_TYPE_L2_SA, KEY_GEN_RSP_TYPE_ACL, 3164 KEY_GEN_RSP_TYPE_SIP, 2, 11, 5, 3165 TR3_LTR_LIB_ACL_L2_DIPV6_64, 3166 TR3_LTR_LIB_ACL_L2_SA_ACL_SIPV6_64, -1, 2, 1, 3167 3, 0, 8, 8, 8, 0, 5, 7, 6, 3, 0, 1, 1, 0, 0, 3168 0, 0, 0); 3169 SOC_IF_ERROR_RETURN(_soc_write_esm_key_id_to_field_map_entry(unit, 3170 KEY_GEN_OFFSET_TR2_ACL_L2_V6U_NON7K_SGLP, &key_map)); 3171 } 3172 3173 if (!fwd_l2_present || !fwd_ipv6u_present) { 3174 int non7k = 0; 3175 if (tcam_info->mode) { /* 350 Mhz */ 3176 non7k = 1; 3177 } 3178 /* only SGLP variant makes sense */ 3179 sal_memset(&key_map, 0, sizeof(key_map)); 3180 if (non7k) { 3181 /* TR2 L2_ACL non7k) */ 3182 SOC_TR3_BUILD_FM_ENTRY(key_map, 0, 3183 F11_DA_ETHTYPE_SA_VID_VFI_SEL_VID_VFI_DATA_SRC, 3184 0, F9_UDF1, F8_OTAG_DA, 3185 F7_SGLP_DGLP, F6_CLASSID_ALL, 3186 F5_FLAGS_IP_1_VRF, 3187 F4_ITAG, 3188 F3_UDF_1_AND_2_VALID, 3189 0, 0, F2_FLAG_HG, F2_FLAG_L3_TYPE_3, 3190 F2_FLAG_L3_TYPE_2, F2_FLAG_L3_TYPE_1, 3191 F2_FLAG_L3_TYPE_0, 3192 F2_FLAG_LOOKUP_STATUS_VECTOR_15, 3193 F2_FLAG_INCOMING_TAG_STATUS_1, 3194 F2_FLAG_INCOMING_TAG_STATUS_0, 3195 F2_FLAG_MH_MIRROR_ONLY, 3196 F2_FLAG_LOOKUP_STATUS_VECTOR_0, 3197 F2_FLAG_ESM_KEY_SUBTYPE_0, 3198 F2_FLAG_MY_STATION_HIT, 3199 F2_FLAG_FORWARDING_TYPE_2, 3200 F2_FLAG_FORWARDING_TYPE_1, F2_FLAG_L3_IIF_VALID, 3201 1, KEY_GEN_RSP_TYPE_ACL, 3202 0, 0, 0, 1, 8, 2, 3203 TR3_LTR_LIB_ACL_L2_ONLY_N7K, -1, -1, 1, 1, 3204 0, 0, 8, 8, 8, 0, 6, 7, 7, 0, 0, 1, 0, 0, 0, 3205 0, 0, 0); 3206 SOC_IF_ERROR_RETURN( 3207 _soc_write_esm_key_id_to_field_map_entry(unit, 3208 KEY_GEN_OFFSET_TR2_ACL_L2_ONLY, &key_map)); 3209 } else { 3210 /* TR2 L2_ACL (7k) */ 3211 SOC_TR3_BUILD_FM_ENTRY(key_map, 0, 3212 F11_DA_ETHTYPE_SA_VID_VFI_SEL_VID_VFI_DATA_SRC, 3213 0, F9_UDF1, F8_OTAG_DA, 3214 F7_SGLP_DGLP, F6_CLASSID_ALL, 3215 F5_INT_RANGE_CHECK, 3216 F4_ITAG, 3217 F3_UDF_1_AND_2_VALID, 3218 0, 0, F2_FLAG_HG, F2_FLAG_L3_TYPE_3, 3219 F2_FLAG_L3_TYPE_2, F2_FLAG_L3_TYPE_1, 3220 F2_FLAG_L3_TYPE_0, 3221 F2_FLAG_LOOKUP_STATUS_VECTOR_15, 3222 F2_FLAG_INCOMING_TAG_STATUS_1, 3223 F2_FLAG_INCOMING_TAG_STATUS_0, 3224 F2_FLAG_MH_MIRROR_ONLY, 3225 F2_FLAG_LOOKUP_STATUS_VECTOR_0, 3226 F2_FLAG_ESM_KEY_SUBTYPE_0, 3227 F2_FLAG_MY_STATION_HIT, 3228 F2_FLAG_FORWARDING_TYPE_2, 3229 F2_FLAG_FORWARDING_TYPE_1, F2_FLAG_L3_IIF_VALID, 3230 1, KEY_GEN_RSP_TYPE_ACL, 3231 0, 0, 0, 1, 8, 2, 3232 TR3_LTR_LIB_ACL_L2_ONLY, -1, -1, 1, 1, 3233 0, 0, 8, 8, 8, 0, 6, 7, 7, 0, 0, 1, 0, 0, 0, 3234 0, 0, 0); 3235 SOC_IF_ERROR_RETURN( 3236 _soc_write_esm_key_id_to_field_map_entry(unit, 3237 KEY_GEN_OFFSET_TR2_ACL_L2_ONLY, &key_map)); 3238 } 3239 } 3240 } 3241 3242 /* TR2 IPV4_ACL144 (ACL_IP4C) */ 3243 if (partitions[TCAM_PARTITION_ACL_IP4C].num_entries) { 3244 sal_memset(&key_map, 0, sizeof(key_map)); 3245 acl_key_type = 0; 3246 if (fwd_ipv4_present) { 3247 SOC_TR3_BUILD_FM_ENTRY(key_map, acl_key_type, 3248 F11_SA_OTAG_DA_ETHTYPE, 0, 0, 3249 F8_SIPV4_DIPV4, F7_L4_SRC_L4_DST, 0, 3250 F5_L3_PROTOCOL_TOS, F4_FLAGS_IP_1_VRF, 3251 F3_FREE_BIT_VID_VFI_SEL_VID_VFI_DATA_SRC, 3252 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3253 F2_FLAG_ESM_KEY_SUBTYPE_0, 3254 F2_FLAG_MH_MIRROR_ONLY, 3255 F2_FLAG_MY_STATION_HIT, 3256 F2_FLAG_FORWARDING_TYPE_2, 3257 F2_FLAG_FORWARDING_TYPE_1, 3258 F2_FLAG_L3_IIF_VALID, 3259 1, KEY_GEN_RSP_TYPE_DIP, 3260 KEY_GEN_RSP_TYPE_ACL, 3261 KEY_GEN_RSP_TYPE_SIP,KEY_GEN_RSP_TYPE_L2_SA, 3262 2, 6, 5, TR3_LTR_LIB_ACL_IP4C_DIP, 3263 TR3_LTR_LIB_ACL_IP4C_ACL_SIP_SA, -1, 2, 1, 3, 3264 0, 8, 8, 8, 0, 2, 6, 2, 3, 0, 1, 1, 0, 0, 3265 0, 0, 0); 3266 SOC_IF_ERROR_RETURN(_soc_write_esm_key_id_to_field_map_entry(unit, 3267 KEY_GEN_OFFSET_TR2_ACL_IP4C, &key_map)); 3268 acl_key_type ^= 1; 3269 } 3270 if (fwd_l2_present) { 3271 sal_memset(&key_map, 0, sizeof(key_map)); 3272 /* install IP4C ACL with l2 forwarding */ 3273 3274 SOC_TR3_BUILD_FM_ENTRY(key_map, acl_key_type, 3275 F11_DA_ETHTYPE_SA_VID_VFI_SEL_VID_VFI_DATA_SRC, 3276 0, 0, F8_SIPV4_DIPV4, F7_L4_SRC_L4_DST, 3277 F6_OTAG_ITAG, F5_L3_PROTOCOL_TOS, 3278 F4_FLAGS_IP_1_VRF, 3279 F3_FREE_BIT_VID_VFI_SEL_VID_VFI_DATA_DST, 3280 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3281 F2_FLAG_ESM_KEY_SUBTYPE_0, 3282 F2_FLAG_MH_MIRROR_ONLY, 3283 F2_FLAG_MY_STATION_HIT, 3284 F2_FLAG_FORWARDING_TYPE_2, 3285 F2_FLAG_FORWARDING_TYPE_1, 3286 F2_FLAG_L3_IIF_VALID, 3287 1, KEY_GEN_RSP_TYPE_L2_SA, 3288 KEY_GEN_RSP_TYPE_ACL, 3289 KEY_GEN_RSP_TYPE_L2_DA, 0, 3290 2, 8, 4, TR3_LTR_LIB_ACL_IP4C_L2_SA, 3291 TR3_LTR_LIB_ACL_IP4C_L2_ACL_DA, -1, 2, 1, 3292 2, 0, 8, 8, 8, 0, 4, 6, 4, 2, 0, 1, 1, 0, 0, 3293 0, 0, 0); 3294 SOC_IF_ERROR_RETURN(_soc_write_esm_key_id_to_field_map_entry(unit, 3295 KEY_GEN_OFFSET_TR2_ACL_IP4C_L2, &key_map)); 3296 acl_key_type ^= 1; 3297 } 3298 if (!fwd_ipv4_present || !fwd_l2_present) { 3299 /* install IP4C ACL only */ 3300 /* install IP4C ACL with no forwarding */ 3301 3302 sal_memset(&key_map, 0, sizeof(key_map)); 3303 SOC_TR3_BUILD_FM_ENTRY(key_map, acl_key_type, 3304 F11_SA_OTAG_DA_ETHTYPE, 0, 0, 3305 F8_SIPV4_DIPV4, F7_L4_SRC_L4_DST, 0, 3306 F5_L3_PROTOCOL_TOS, F4_FLAGS_IP_1_VRF, 3307 F3_FREE_BIT_VID_VFI_SEL_VID_VFI_DATA_SRC, 3308 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3309 F2_FLAG_ESM_KEY_SUBTYPE_0, 3310 F2_FLAG_MH_MIRROR_ONLY, 3311 F2_FLAG_MY_STATION_HIT, 3312 F2_FLAG_FORWARDING_TYPE_2, 3313 F2_FLAG_FORWARDING_TYPE_1, 3314 F2_FLAG_L3_IIF_VALID, 3315 1, KEY_GEN_RSP_TYPE_ACL, 3316 0, 0, 0, 3317 1, 5, 2, TR3_LTR_LIB_ACL_IP4C_ONLY, 3318 -1, -1, 1, 1, 3319 0, 0, 8, 8, 8, 0, 5, 6, 5, 0, 0, 1, 0, 0, 0, 3320 0, 0, 0); 3321 SOC_IF_ERROR_RETURN(_soc_write_esm_key_id_to_field_map_entry(unit, 3322 KEY_GEN_OFFSET_TR2_ACL_IP4C_ONLY, &key_map)); 3323 } 3324 } 3325 3326 /* TR2 IPV4_ACL (ACL_IP4) */ 3327 if (partitions[TCAM_PARTITION_ACL_IP4].num_entries) { 3328 if (fwd_ipv4_present) { 3329 sal_memset(&key_map, 0, sizeof(key_map)); 3330 SOC_TR3_BUILD_FM_ENTRY(key_map, 0, 3331 F11_DA_ETHTYPE_SA_VID_VFI_SEL_VID_VFI_DATA_SRC, 3332 0, 0, 3333 F8_SIPV4_DIPV4, 3334 F7_L4_SRC_L4_DST, F6_CLASSID_ALL, 3335 F5_INT_RANGE_CHECK, F4_FLAGS_IP_1_VRF, 3336 F3_TOS_TTL, 3337 0, F2_FLAG_HG, F2_FLAG_L3_TYPE_3, 3338 F2_FLAG_L3_TYPE_2, F2_FLAG_L3_TYPE_1, 3339 F2_FLAG_L3_TYPE_0, 3340 F2_FLAG_LOOKUP_STATUS_VECTOR_15, 3341 F2_FLAG_LOOKUP_STATUS_VECTOR_0, 3342 F2_FLAG_MH_MIRROR_ONLY, 3343 F2_FLAG_L3_PROTOCOL_FN_3, 3344 F2_FLAG_L3_PROTOCOL_FN_2, 3345 F2_FLAG_L3_PROTOCOL_FN_1, 3346 F2_FLAG_L3_PROTOCOL_FN_0, 3347 F2_FLAG_MY_STATION_HIT, 3348 F2_FLAG_FORWARDING_TYPE_2, 3349 F2_FLAG_FORWARDING_TYPE_1, 3350 F2_FLAG_L3_IIF_VALID, 3351 1, KEY_GEN_RSP_TYPE_DIP, 3352 KEY_GEN_RSP_TYPE_ACL, KEY_GEN_RSP_TYPE_SIP, 3353 KEY_GEN_RSP_TYPE_L2_SA, 3354 2, 7, 5, TR3_LTR_LIB_ACL_IP4_DIP, 3355 TR3_LTR_LIB_ACL_IP4_ACL_SIP_SA, -1, 2, 1, 3356 3, 0, 8, 8, 8, 0, 3, 6, 3, 2, 0, 1, 1, 0, 0, 3357 0, 0, 0); 3358 SOC_IF_ERROR_RETURN(_soc_write_esm_key_id_to_field_map_entry(unit, 3359 KEY_GEN_OFFSET_TR2_ACL_IP4, &key_map)); 3360 } 3361 if (fwd_l2_present) { 3362 sal_memset(&key_map, 0, sizeof(key_map)); 3363 SOC_TR3_BUILD_FM_ENTRY(key_map, 0, 3364 F11_DA_ETHTYPE_SA_VID_VFI_SEL_VID_VFI_DATA_SRC, 3365 0, 0, 3366 F8_SIPV4_DIPV4, 3367 F7_L4_SRC_L4_DST, F6_CLASSID_ALL, 3368 F5_INT_RANGE_CHECK, 3369 F4_FREE_BIT_VID_VFI_SEL_VID_VFI_DATA_DST, 3370 F3_TOS_TTL, 3371 0, F2_FLAG_HG, F2_FLAG_L3_TYPE_3, 3372 F2_FLAG_L3_TYPE_2, F2_FLAG_L3_TYPE_1, 3373 F2_FLAG_L3_TYPE_0, 3374 F2_FLAG_LOOKUP_STATUS_VECTOR_15, 3375 F2_FLAG_LOOKUP_STATUS_VECTOR_0, 3376 F2_FLAG_MH_MIRROR_ONLY, 3377 F2_FLAG_L3_PROTOCOL_FN_3, 3378 F2_FLAG_L3_PROTOCOL_FN_2, 3379 F2_FLAG_L3_PROTOCOL_FN_1, 3380 F2_FLAG_L3_PROTOCOL_FN_0, 3381 F2_FLAG_MY_STATION_HIT, 3382 F2_FLAG_FORWARDING_TYPE_2, 3383 F2_FLAG_FORWARDING_TYPE_1, 3384 F2_FLAG_L3_IIF_VALID, 3385 1, KEY_GEN_RSP_TYPE_ACL, 3386 KEY_GEN_RSP_TYPE_L2_SA, KEY_GEN_RSP_TYPE_L2_DA, 3387 0, 2, 8, 4, TR3_LTR_LIB_ACL_IP4_L2_ACL_SA, 3388 TR3_LTR_LIB_ACL_IP4_L2_DA, -1, 2, 2, 3389 1, 0, 8, 8, 8, 0, 4, 6, 4, 2, 0, 1, 1, 0, 0, 3390 0, 0, 0); 3391 SOC_IF_ERROR_RETURN(_soc_write_esm_key_id_to_field_map_entry(unit, 3392 KEY_GEN_OFFSET_TR2_ACL_IP4_L2, &key_map)); 3393 } 3394 if (!fwd_ipv4_present || !fwd_l2_present) { 3395 sal_memset(&key_map, 0, sizeof(key_map)); 3396 SOC_TR3_BUILD_FM_ENTRY(key_map, 0, 3397 F11_DA_ETHTYPE_SA_VID_VFI_SEL_VID_VFI_DATA_SRC, 3398 0, 0, 3399 F8_SIPV4_DIPV4, 3400 F7_L4_SRC_L4_DST, F6_CLASSID_ALL, 3401 F5_INT_RANGE_CHECK, 3402 F4_FLAGS_IP_1_VRF, 3403 F3_TOS_TTL, 3404 0, F2_FLAG_HG, F2_FLAG_L3_TYPE_3, 3405 F2_FLAG_L3_TYPE_2, F2_FLAG_L3_TYPE_1, 3406 F2_FLAG_L3_TYPE_0, 3407 F2_FLAG_LOOKUP_STATUS_VECTOR_15, 3408 F2_FLAG_LOOKUP_STATUS_VECTOR_0, 3409 F2_FLAG_MH_MIRROR_ONLY, 3410 F2_FLAG_L3_PROTOCOL_FN_3, 3411 F2_FLAG_L3_PROTOCOL_FN_2, 3412 F2_FLAG_L3_PROTOCOL_FN_1, 3413 F2_FLAG_L3_PROTOCOL_FN_0, 3414 F2_FLAG_MY_STATION_HIT, 3415 F2_FLAG_FORWARDING_TYPE_2, 3416 F2_FLAG_FORWARDING_TYPE_1, 3417 F2_FLAG_L3_IIF_VALID, 3418 1, KEY_GEN_RSP_TYPE_ACL, 3419 0, 0, 3420 0, 1, 4, 2, TR3_LTR_LIB_ACL_IP4_ONLY, 3421 -1, -1, 1, 1, 3422 0, 0, 8, 8, 8, 0, 3, 5, 3, 0, 0, 1, 1, 0, 0, 3423 0, 0, 0); 3424 SOC_IF_ERROR_RETURN(_soc_write_esm_key_id_to_field_map_entry(unit, 3425 KEY_GEN_OFFSET_TR2_ACL_IP4_ONLY, &key_map)); 3426 } 3427 } 3428 3429 /* TR2 L2_IPV4_ACL (ACL_L2IP4) */ 3430 /* Same F-selects and flags as ACL_IP4 above */ 3431 if (partitions[TCAM_PARTITION_ACL_L2IP4].num_entries) { 3432 if (fwd_ipv4_present) { 3433 sal_memset(&key_map, 0, sizeof(key_map)); 3434 if (soc_property_get(unit, spn_EXT_L2IP4_ACL_TABLE_MASTER_KEY_TYPE, 0) == 1){ 3435 SOC_TR3_BUILD_FM_ENTRY(key_map, 0, 3436 F11_SA_OTAG_DA_ETHTYPE, 3437 0, 0, 3438 F8_SIPV4_DIPV4, 3439 F7_L4_SRC_L4_DST, F6_SGLP_DGLP, 3440 F5_L3_PROTOCOL_TOS, F4_FLAGS_IP_1_VRF, 3441 F3_FREE_BIT_VID_VFI_SEL_VID_VFI_DATA_DST, 3442 0, F2_FLAG_LOOKUP_STATUS_VECTOR_15, 3443 F2_FLAG_LOOKUP_STATUS_VECTOR_13, 3444 F2_FLAG_LOOKUP_STATUS_VECTOR_12, 3445 F2_FLAG_LOOKUP_STATUS_VECTOR_11, 3446 F2_FLAG_LOOKUP_STATUS_VECTOR_10, 3447 F2_FLAG_LOOKUP_STATUS_VECTOR_9, 3448 F2_FLAG_LOOKUP_STATUS_VECTOR_8, 3449 F2_FLAG_LOOKUP_STATUS_VECTOR_7, 3450 F2_FLAG_LOOKUP_STATUS_VECTOR_6, 3451 F2_FLAG_LOOKUP_STATUS_VECTOR_2, 3452 F2_FLAG_LOOKUP_STATUS_VECTOR_1, 3453 F2_FLAG_LOOKUP_STATUS_VECTOR_0, 3454 F2_FLAG_MY_STATION_HIT, 3455 F2_FLAG_FORWARDING_TYPE_2, 3456 F2_FLAG_FORWARDING_TYPE_1, 3457 F2_FLAG_L3_IIF_VALID, 3458 1, KEY_GEN_RSP_TYPE_DIP, 3459 KEY_GEN_RSP_TYPE_ACL, KEY_GEN_RSP_TYPE_SIP, 3460 KEY_GEN_RSP_TYPE_L2_SA, 3461 2, 7, 5, TR3_LTR_LIB_ACL_IP4_DIP, 3462 TR3_LTR_LIB_ACL_L2IP4_ACL_SIP_SA, -1, 2, 1, 3463 3, 0, 8, 8, 8, 0, 3, 6, 3, 2, 0, 1, 1, 0, 0, 3464 0, 0, 0); 3465 SOC_IF_ERROR_RETURN(_soc_write_esm_key_id_to_field_map_entry(unit, 3466 KEY_GEN_OFFSET_TR2_ACL_L2IP4, &key_map)); 3467 } else { 3468 SOC_TR3_BUILD_FM_ENTRY(key_map, 0, 3469 F11_DA_ETHTYPE_SA_VID_VFI_SEL_VID_VFI_DATA_SRC, 3470 0, 0, 3471 F8_SIPV4_DIPV4, 3472 F7_L4_SRC_L4_DST, F6_CLASSID_ALL, 3473 F5_INT_RANGE_CHECK, F4_FLAGS_IP_1_VRF, 3474 F3_TOS_TTL, 3475 0, F2_FLAG_HG, F2_FLAG_L3_TYPE_3, 3476 F2_FLAG_L3_TYPE_2, F2_FLAG_L3_TYPE_1, 3477 F2_FLAG_L3_TYPE_0, 3478 F2_FLAG_LOOKUP_STATUS_VECTOR_15, 3479 F2_FLAG_LOOKUP_STATUS_VECTOR_0, 3480 F2_FLAG_MH_MIRROR_ONLY, 3481 F2_FLAG_L3_PROTOCOL_FN_3, 3482 F2_FLAG_L3_PROTOCOL_FN_2, 3483 F2_FLAG_L3_PROTOCOL_FN_1, 3484 F2_FLAG_L3_PROTOCOL_FN_0, 3485 F2_FLAG_MY_STATION_HIT, 3486 F2_FLAG_FORWARDING_TYPE_2, 3487 F2_FLAG_FORWARDING_TYPE_1, 3488 F2_FLAG_L3_IIF_VALID, 3489 1, KEY_GEN_RSP_TYPE_DIP, 3490 KEY_GEN_RSP_TYPE_ACL, KEY_GEN_RSP_TYPE_SIP, 3491 KEY_GEN_RSP_TYPE_L2_SA, 3492 2, 7, 5, TR3_LTR_LIB_ACL_IP4_DIP, 3493 TR3_LTR_LIB_ACL_L2IP4_ACL_SIP_SA, -1, 2, 1, 3494 3, 0, 8, 8, 8, 0, 3, 6, 3, 2, 0, 1, 1, 0, 0, 3495 0, 0, 0); 3496 SOC_IF_ERROR_RETURN(_soc_write_esm_key_id_to_field_map_entry(unit, 3497 KEY_GEN_OFFSET_TR2_ACL_L2IP4, &key_map)); 3498 } 3499 } 3500 if (fwd_l2_present) { 3501 sal_memset(&key_map, 0, sizeof(key_map)); 3502 if (soc_property_get(unit, spn_EXT_L2IP4_ACL_TABLE_MASTER_KEY_TYPE, 0) == 1) { 3503 SOC_TR3_BUILD_FM_ENTRY(key_map, 0, 3504 F11_SA_OTAG_DA_ETHTYPE, 3505 0, 0, 3506 F8_SIPV4_DIPV4, 3507 F7_L4_SRC_L4_DST, F6_SGLP_DGLP, 3508 F5_L3_PROTOCOL_TOS, F4_FLAGS_IP_1_VRF, 3509 F3_FREE_BIT_VID_VFI_SEL_VID_VFI_DATA_DST, 3510 0, F2_FLAG_LOOKUP_STATUS_VECTOR_15, 3511 F2_FLAG_LOOKUP_STATUS_VECTOR_13, 3512 F2_FLAG_LOOKUP_STATUS_VECTOR_12, 3513 F2_FLAG_LOOKUP_STATUS_VECTOR_11, 3514 F2_FLAG_LOOKUP_STATUS_VECTOR_10, 3515 F2_FLAG_LOOKUP_STATUS_VECTOR_9, 3516 F2_FLAG_LOOKUP_STATUS_VECTOR_8, 3517 F2_FLAG_LOOKUP_STATUS_VECTOR_7, 3518 F2_FLAG_LOOKUP_STATUS_VECTOR_6, 3519 F2_FLAG_LOOKUP_STATUS_VECTOR_2, 3520 F2_FLAG_LOOKUP_STATUS_VECTOR_1, 3521 F2_FLAG_LOOKUP_STATUS_VECTOR_0, 3522 F2_FLAG_MY_STATION_HIT, 3523 F2_FLAG_FORWARDING_TYPE_2, 3524 F2_FLAG_FORWARDING_TYPE_1, 3525 F2_FLAG_L3_IIF_VALID, 3526 1, KEY_GEN_RSP_TYPE_L2_DA, 3527 KEY_GEN_RSP_TYPE_ACL, KEY_GEN_RSP_TYPE_L2_SA, 3528 0, 3529 2, 8, 4, TR3_LTR_LIB_ACL_L2IP4_L2_DA, 3530 TR3_LTR_LIB_ACL_L2IP4_L2_ACL_SA, -1, 2, 1, 3531 2, 0, 8, 8, 8, 0, 4, 6, 4, 2, 0, 1, 1, 0, 0, 3532 0, 0, 0); 3533 SOC_IF_ERROR_RETURN(_soc_write_esm_key_id_to_field_map_entry(unit, 3534 KEY_GEN_OFFSET_TR2_ACL_L2IP4_L2, &key_map)); 3535 } else { 3536 SOC_TR3_BUILD_FM_ENTRY(key_map, 0, 3537 F11_DA_ETHTYPE_SA_VID_VFI_SEL_VID_VFI_DATA_SRC, 3538 0, 0, 3539 F8_SIPV4_DIPV4, 3540 F7_L4_SRC_L4_DST, F6_CLASSID_ALL, 3541 F5_INT_RANGE_CHECK, 3542 F4_FREE_BIT_VID_VFI_SEL_VID_VFI_DATA_DST, 3543 F3_TOS_TTL, 3544 0, F2_FLAG_HG, F2_FLAG_L3_TYPE_3, 3545 F2_FLAG_L3_TYPE_2, F2_FLAG_L3_TYPE_1, 3546 F2_FLAG_L3_TYPE_0, 3547 F2_FLAG_LOOKUP_STATUS_VECTOR_15, 3548 F2_FLAG_LOOKUP_STATUS_VECTOR_0, 3549 F2_FLAG_MH_MIRROR_ONLY, 3550 F2_FLAG_L3_PROTOCOL_FN_3, 3551 F2_FLAG_L3_PROTOCOL_FN_2, 3552 F2_FLAG_L3_PROTOCOL_FN_1, 3553 F2_FLAG_L3_PROTOCOL_FN_0, 3554 F2_FLAG_MY_STATION_HIT, 3555 F2_FLAG_FORWARDING_TYPE_2, 3556 F2_FLAG_FORWARDING_TYPE_1, 3557 F2_FLAG_L3_IIF_VALID, 3558 1, KEY_GEN_RSP_TYPE_L2_DA, 3559 KEY_GEN_RSP_TYPE_ACL, KEY_GEN_RSP_TYPE_L2_SA, 3560 0, 3561 2, 8, 4, TR3_LTR_LIB_ACL_L2IP4_L2_DA, 3562 TR3_LTR_LIB_ACL_L2IP4_L2_ACL_SA, -1, 2, 1, 3563 2, 0, 8, 8, 8, 0, 4, 6, 4, 2, 0, 1, 1, 0, 0, 3564 0, 0, 0); 3565 SOC_IF_ERROR_RETURN(_soc_write_esm_key_id_to_field_map_entry(unit, 3566 KEY_GEN_OFFSET_TR2_ACL_L2IP4_L2, &key_map)); 3567 } 3568 } 3569 if (!fwd_ipv4_present || !fwd_l2_present) { 3570 sal_memset(&key_map, 0, sizeof(key_map)); 3571 if (soc_property_get(unit, spn_EXT_L2IP4_ACL_TABLE_MASTER_KEY_TYPE, 0) == 1) { 3572 SOC_TR3_BUILD_FM_ENTRY(key_map, 0, 3573 F11_SA_OTAG_DA_ETHTYPE, 3574 0, 0, 3575 F8_SIPV4_DIPV4, 3576 F7_L4_SRC_L4_DST, F6_SGLP_DGLP, 3577 F5_L3_PROTOCOL_TOS, F4_FLAGS_IP_1_VRF, 3578 0, 3579 0, F2_FLAG_LOOKUP_STATUS_VECTOR_15, 3580 F2_FLAG_LOOKUP_STATUS_VECTOR_13, 3581 F2_FLAG_LOOKUP_STATUS_VECTOR_12, 3582 F2_FLAG_LOOKUP_STATUS_VECTOR_11, 3583 F2_FLAG_LOOKUP_STATUS_VECTOR_10, 3584 F2_FLAG_LOOKUP_STATUS_VECTOR_9, 3585 F2_FLAG_LOOKUP_STATUS_VECTOR_8, 3586 F2_FLAG_LOOKUP_STATUS_VECTOR_7, 3587 F2_FLAG_LOOKUP_STATUS_VECTOR_6, 3588 F2_FLAG_LOOKUP_STATUS_VECTOR_2, 3589 F2_FLAG_LOOKUP_STATUS_VECTOR_1, 3590 F2_FLAG_LOOKUP_STATUS_VECTOR_0, 3591 F2_FLAG_MY_STATION_HIT, 3592 F2_FLAG_FORWARDING_TYPE_2, 3593 F2_FLAG_FORWARDING_TYPE_1, 3594 F2_FLAG_L3_IIF_VALID, 3595 1, KEY_GEN_RSP_TYPE_ACL, 3596 0, 0, 0, 1, 6, 2, TR3_LTR_LIB_ACL_L2IP4_ONLY, 3597 -1, -1, 1, 1, 3598 0, 0, 8, 8, 8, 0, 4, 6, 5, 0, 0, 1, 1, 0, 0, 3599 0, 0, 0); 3600 SOC_IF_ERROR_RETURN(_soc_write_esm_key_id_to_field_map_entry(unit, 3601 KEY_GEN_OFFSET_TR2_ACL_L2IP4_ONLY, &key_map)); 3602 } else { 3603 SOC_TR3_BUILD_FM_ENTRY(key_map, 0, 3604 F11_DA_ETHTYPE_SA_VID_VFI_SEL_VID_VFI_DATA_SRC, 3605 0, 0, 3606 F8_SIPV4_DIPV4, 3607 F7_L4_SRC_L4_DST, F6_CLASSID_ALL, 3608 F5_INT_RANGE_CHECK, F4_FLAGS_IP_1_VRF, 3609 F3_TOS_TTL, 3610 0, F2_FLAG_HG, F2_FLAG_L3_TYPE_3, 3611 F2_FLAG_L3_TYPE_2, F2_FLAG_L3_TYPE_1, 3612 F2_FLAG_L3_TYPE_0, 3613 F2_FLAG_LOOKUP_STATUS_VECTOR_15, 3614 F2_FLAG_LOOKUP_STATUS_VECTOR_0, 3615 F2_FLAG_MH_MIRROR_ONLY, 3616 F2_FLAG_L3_PROTOCOL_FN_3, 3617 F2_FLAG_L3_PROTOCOL_FN_2, 3618 F2_FLAG_L3_PROTOCOL_FN_1, 3619 F2_FLAG_L3_PROTOCOL_FN_0, 3620 F2_FLAG_MY_STATION_HIT, 3621 F2_FLAG_FORWARDING_TYPE_2, 3622 F2_FLAG_FORWARDING_TYPE_1, 3623 F2_FLAG_L3_IIF_VALID, 3624 1, KEY_GEN_RSP_TYPE_ACL, 3625 0, 0, 0, 1, 6, 2, TR3_LTR_LIB_ACL_L2IP4_ONLY, 3626 -1, -1, 1, 1, 3627 0, 0, 8, 8, 8, 0, 4, 6, 5, 0, 0, 1, 1, 0, 0, 3628 0, 0, 0); 3629 SOC_IF_ERROR_RETURN(_soc_write_esm_key_id_to_field_map_entry(unit, 3630 KEY_GEN_OFFSET_TR2_ACL_L2IP4_ONLY, &key_map)); 3631 } 3632 } 3633 } 3634 3635 /* TR2 ACL144_IPV6 (ACL_IP6C */ 3636 if (partitions[TCAM_PARTITION_ACL_IP6C].num_entries) { 3637 if (fwd_ipv6_present) { 3638 sal_memset(&key_map, 0, sizeof(key_map)); 3639 SOC_TR3_BUILD_FM_ENTRY(key_map, 0, 3640 F11_DA_ETHTYPE_SA_VID_VFI_SEL_VID_VFI_DATA_SRC, 3641 0, F9_SIPV6, 3642 0, 3643 0, 0, 3644 0, 3645 F4_OTAG, 3646 F3_FLAGS_IP_1_VRF, 3647 F1_DIPV6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3648 0, 0, 0, 0, 1, KEY_GEN_RSP_TYPE_DIP, 3649 KEY_GEN_RSP_TYPE_ACL, KEY_GEN_RSP_TYPE_SIP, 3650 KEY_GEN_RSP_TYPE_L2_SA, 2, 9, 5, 3651 TR3_LTR_LIB_ACL_IP6C_DIPV6_128, 3652 TR3_LTR_LIB_ACL_IP6C_ACL_SIPV6_128_SA, -1, 2, 1, 3653 3, 0, 8, 8, 8, 0, 3, 6, 3, 4, 0, 1, 1, 0, 0, 3654 0, 0, 0); 3655 SOC_IF_ERROR_RETURN(_soc_write_esm_key_id_to_field_map_entry(unit, 3656 KEY_GEN_OFFSET_TR2_ACL_IP6C, &key_map)); 3657 } 3658 if (fwd_ipv6u_present) { 3659 sal_memset(&key_map, 0, sizeof(key_map)); 3660 SOC_TR3_BUILD_FM_ENTRY(key_map, 0, 3661 F11_DA_ETHTYPE_SA_VID_VFI_SEL_VID_VFI_DATA_SRC, 3662 F10_SIPV6_U64_DIPV6_U64, 0, 3663 0, 3664 0, 0, 3665 0, 3666 F4_OTAG, 3667 F3_FLAGS_IP_1_VRF, 3668 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3669 0, 0, 1, KEY_GEN_RSP_TYPE_DIP, 3670 KEY_GEN_RSP_TYPE_ACL, KEY_GEN_RSP_TYPE_SIP, 3671 KEY_GEN_RSP_TYPE_L2_SA, 2, 7, 5, 3672 TR3_LTR_LIB_ACL_IP6C_DIP, 3673 TR3_LTR_LIB_ACL_IP6C_ACL_SIP_SA, -1, 2, 1, 3674 3, 0, 8, 8, 8, 0, 2, 4, 2, 3, 0, 1, 1, 0, 0, 3675 0, 0, 0); 3676 SOC_IF_ERROR_RETURN(_soc_write_esm_key_id_to_field_map_entry(unit, 3677 KEY_GEN_OFFSET_TR2_ACL_IP6C_IP6U_FWD, &key_map)); 3678 } 3679 if (fwd_l2_present) { 3680 sal_memset(&key_map, 0, sizeof(key_map)); 3681 SOC_TR3_BUILD_FM_ENTRY(key_map, 0, 3682 F11_DA_ETHTYPE_SA_VID_VFI_SEL_VID_VFI_DATA_SRC, 3683 F10_SIPV6_U64_DIPV6_U64, 0, 3684 0, 3685 0, 0, 3686 0, 3687 F4_OTAG, 3688 F3_FREE_BIT_VID_VFI_SEL_VID_VFI_DATA_DST, 3689 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3690 0, 0, 1, KEY_GEN_RSP_TYPE_ACL, 3691 KEY_GEN_RSP_TYPE_L2_SA, KEY_GEN_RSP_TYPE_L2_DA, 3692 0, 2, 8, 4, 3693 TR3_LTR_LIB_ACL_IP6C_L2_ACL_SA, 3694 TR3_LTR_LIB_ACL_IP6C_L2_DA, -1, 2, 2, 3695 1, 0, 8, 8, 8, 0, 4, 6, 4, 2, 0, 1, 1, 0, 0, 3696 0, 0, 0); 3697 SOC_IF_ERROR_RETURN(_soc_write_esm_key_id_to_field_map_entry(unit, 3698 KEY_GEN_OFFSET_TR2_ACL_IP6C_L2, &key_map)); 3699 } 3700 if (!fwd_ipv6_present || !fwd_ipv6u_present || !fwd_l2_present) { 3701 sal_memset(&key_map, 0, sizeof(key_map)); 3702 SOC_TR3_BUILD_FM_ENTRY(key_map, 0, 3703 0, 3704 F10_SIPV6_U64_DIPV6_U64, 0, 3705 0, 3706 0, 0, 3707 0, 3708 F4_OTAG, 3709 0, 3710 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3711 0, 0, 1, KEY_GEN_RSP_TYPE_ACL, 3712 0, 0, 0, 1, 4, 2, 3713 TR3_LTR_LIB_ACL_IP6C_ONLY, 3714 -1, -1, 1, 1, 3715 0, 0, 8, 8, 8, 0, 2, 4, 3, 0, 0, 1, 0, 0, 0, 3716 0, 0, 0); 3717 SOC_IF_ERROR_RETURN(_soc_write_esm_key_id_to_field_map_entry(unit, 3718 KEY_GEN_OFFSET_TR2_ACL_IP6C_ONLY, &key_map)); 3719 } 3720 } 3721 3722 /* TR2 SHORT_IPV6_ACL (ACL_IP6S) */ 3723 if (partitions[TCAM_PARTITION_ACL_IP6S].num_entries) { 3724 if (fwd_ipv6u_present) { 3725 sal_memset(&key_map, 0, sizeof(key_map)); 3726 acl_key_type = 0; 3727 SOC_TR3_BUILD_FM_ENTRY(key_map, acl_key_type, 3728 F11_DA_ETHTYPE_SA_VID_VFI_SEL_VID_VFI_DATA_SRC, 3729 0, F9_SIPV6, F8_OTAG_SA, 3730 F7_INT_RANGE_CHECK_L3_IIF, F6_L4_SRC_L4_DST, 3731 F5_CLASSID_SRC, F4_TOS_TTL, F3_FLAGS_IP_1_VRF, 3732 F1_DIPV6, 0, F2_FLAG_ESM_KEY_SUBTYPE_0, 3733 F2_FLAG_HG, F2_FLAG_L3_TYPE_3, 3734 F2_FLAG_L3_TYPE_2, F2_FLAG_L3_TYPE_1, 3735 F2_FLAG_L3_TYPE_0, 3736 F2_FLAG_LOOKUP_STATUS_VECTOR_15, 3737 F2_FLAG_L3_PROTOCOL_FN_3, 3738 F2_FLAG_L3_PROTOCOL_FN_2, 3739 F2_FLAG_L3_PROTOCOL_FN_1, 3740 F2_FLAG_L3_PROTOCOL_FN_0, 3741 F2_FLAG_MY_STATION_HIT, 3742 F2_FLAG_FORWARDING_TYPE_2, 3743 F2_FLAG_FORWARDING_TYPE_1, 3744 F2_FLAG_L3_IIF_VALID, 1, KEY_GEN_RSP_TYPE_DIP, 3745 KEY_GEN_RSP_TYPE_ACL, KEY_GEN_RSP_TYPE_SIP, 3746 KEY_GEN_RSP_TYPE_L2_SA, 3, 11, 5, 3747 TR3_LTR_LIB_ACL_IP6S_DIPV6_64, 3748 TR3_LTR_LIB_ACL_IP6S_ACL_SIPV6_64_SA, -1, 2, 1, 3749 3, 0, 8, 8, 8, 0, 3, 7, 3, 6, 0, 1, 2, 0, 0, 3750 0, 0, 0); 3751 SOC_IF_ERROR_RETURN(_soc_write_esm_key_id_to_field_map_entry(unit, 3752 KEY_GEN_OFFSET_TR2_ACL_IP6S_IP6U_FWD, &key_map)); 3753 acl_key_type ^= 1; 3754 } 3755 if (fwd_ipv6_present) { 3756 sal_memset(&key_map, 0, sizeof(key_map)); 3757 acl_key_type = 0; 3758 SOC_TR3_BUILD_FM_ENTRY(key_map, acl_key_type, 3759 F11_DA_ETHTYPE_SA_VID_VFI_SEL_VID_VFI_DATA_SRC, 3760 0, F9_SIPV6, F8_OTAG_SA, 3761 F7_INT_RANGE_CHECK_L3_IIF, F6_L4_SRC_L4_DST, 3762 F5_CLASSID_SRC, F4_TOS_TTL, F3_FLAGS_IP_1_VRF, 3763 F1_DIPV6, 0, F2_FLAG_ESM_KEY_SUBTYPE_0, 3764 F2_FLAG_HG, F2_FLAG_L3_TYPE_3, 3765 F2_FLAG_L3_TYPE_2, F2_FLAG_L3_TYPE_1, 3766 F2_FLAG_L3_TYPE_0, 3767 F2_FLAG_LOOKUP_STATUS_VECTOR_15, 3768 F2_FLAG_L3_PROTOCOL_FN_3, 3769 F2_FLAG_L3_PROTOCOL_FN_2, 3770 F2_FLAG_L3_PROTOCOL_FN_1, 3771 F2_FLAG_L3_PROTOCOL_FN_0, 3772 F2_FLAG_MY_STATION_HIT, 3773 F2_FLAG_FORWARDING_TYPE_2, 3774 F2_FLAG_FORWARDING_TYPE_1, 3775 F2_FLAG_L3_IIF_VALID, 1, KEY_GEN_RSP_TYPE_DIP, 3776 KEY_GEN_RSP_TYPE_ACL, KEY_GEN_RSP_TYPE_SIP, 3777 KEY_GEN_RSP_TYPE_L2_SA, 2, 11, 5, 3778 TR3_LTR_LIB_ACL_IP6S_DIP, 3779 TR3_LTR_LIB_ACL_IP6S_ACL_SIP_SA, -1, 2, 1, 3780 3, 0, 8, 8, 8, 0, 3, 7, 3, 6, 0, 1, 2, 0, 0, 3781 0, 0, 0); 3782 SOC_IF_ERROR_RETURN(_soc_write_esm_key_id_to_field_map_entry(unit, 3783 KEY_GEN_OFFSET_TR2_ACL_IP6S, &key_map)); 3784 acl_key_type ^= 1; 3785 } 3786 if (fwd_l2_present) { 3787 sal_memset(&key_map, 0, sizeof(key_map)); 3788 SOC_TR3_BUILD_FM_ENTRY(key_map, acl_key_type, 3789 F11_DA_ETHTYPE_SA_VID_VFI_SEL_VID_VFI_DATA_SRC, 3790 0, F9_SIPV6, F8_OTAG_DA, 3791 F7_INT_RANGE_CHECK_L3_IIF, F6_L4_SRC_L4_DST, 3792 F5_CLASSID_SRC, F4_TOS_TTL, 3793 F3_FREE_BIT_VID_VFI_SEL_VID_VFI_DATA_DST, 3794 F1_DIPV6, 0, F2_FLAG_ESM_KEY_SUBTYPE_0, 3795 F2_FLAG_HG, F2_FLAG_L3_TYPE_3, 3796 F2_FLAG_L3_TYPE_2, 3797 F2_FLAG_L3_TYPE_1, F2_FLAG_L3_TYPE_0, 3798 F2_FLAG_LOOKUP_STATUS_VECTOR_15, 3799 F2_FLAG_L3_PROTOCOL_FN_3, 3800 F2_FLAG_L3_PROTOCOL_FN_2, 3801 F2_FLAG_L3_PROTOCOL_FN_1, 3802 F2_FLAG_L3_PROTOCOL_FN_0, 3803 F2_FLAG_MY_STATION_HIT, 3804 F2_FLAG_FORWARDING_TYPE_2, 3805 F2_FLAG_FORWARDING_TYPE_1, 3806 F2_FLAG_L3_IIF_VALID, 1, 3807 KEY_GEN_RSP_TYPE_L2_DA, KEY_GEN_RSP_TYPE_ACL, 3808 KEY_GEN_RSP_TYPE_L2_SA, 0, 2, 11, 4, 3809 TR3_LTR_LIB_ACL_IP6S_L2_DA, 3810 TR3_LTR_LIB_ACL_IP6S_L2_ACL_SA, -1, 2, 1, 3811 2, 0, 8, 8, 8, 0, 4, 7, 5, 4, 0, 1, 2, 0, 0, 3812 0, 0, 0); 3813 SOC_IF_ERROR_RETURN(_soc_write_esm_key_id_to_field_map_entry(unit, 3814 KEY_GEN_OFFSET_TR2_ACL_IP6S_L2, &key_map)); 3815 acl_key_type ^= 1; 3816 } 3817 if (!fwd_ipv6_present || !fwd_ipv6u_present || !fwd_l2_present) { 3818 sal_memset(&key_map, 0, sizeof(key_map)); 3819 SOC_TR3_BUILD_FM_ENTRY(key_map, acl_key_type, 3820 F11_DA_ETHTYPE_SA_VID_VFI_SEL_VID_VFI_DATA_SRC, 3821 0, F9_SIPV6, F8_OTAG_SA, 3822 F7_INT_RANGE_CHECK_L3_IIF, F6_L4_SRC_L4_DST, 3823 F5_CLASSID_SRC, F4_TOS_TTL, F3_FLAGS_IP_1_VRF, 3824 F1_DIPV6, 0, F2_FLAG_ESM_KEY_SUBTYPE_0, 3825 F2_FLAG_HG, F2_FLAG_L3_TYPE_3, 3826 F2_FLAG_L3_TYPE_2, 3827 F2_FLAG_L3_TYPE_1, F2_FLAG_L3_TYPE_0, 3828 F2_FLAG_LOOKUP_STATUS_VECTOR_15, 3829 F2_FLAG_L3_PROTOCOL_FN_3, 3830 F2_FLAG_L3_PROTOCOL_FN_2, 3831 F2_FLAG_L3_PROTOCOL_FN_1, 3832 F2_FLAG_L3_PROTOCOL_FN_0, 3833 F2_FLAG_MY_STATION_HIT, 3834 F2_FLAG_FORWARDING_TYPE_2, 3835 F2_FLAG_FORWARDING_TYPE_1, 3836 F2_FLAG_L3_IIF_VALID, 1, 3837 KEY_GEN_RSP_TYPE_ACL, 3838 0, 0, 0, 3839 1, 11, 2, 3840 TR3_LTR_LIB_ACL_IP6S_ONLY, 3841 -1, -1, 1, 1, 3842 0, 0, 8, 8, 8, 0, 7, 7, 9, 0, 0, 2, 0, 0, 0, 3843 0, 0, 0); 3844 SOC_IF_ERROR_RETURN(_soc_write_esm_key_id_to_field_map_entry(unit, 3845 KEY_GEN_OFFSET_TR2_ACL_IP6S_ONLY, &key_map)); 3846 } 3847 } 3848 3849 /* TR2 FULL_IPV6_ACL (ACL_IP6F) */ 3850 if (partitions[TCAM_PARTITION_ACL_IP6F].num_entries) { 3851 if (fwd_ipv6u_present) { 3852 sal_memset(&key_map, 0, sizeof(key_map)); 3853 acl_key_type = 0; 3854 SOC_TR3_BUILD_FM_ENTRY(key_map, acl_key_type, 3855 F11_DA_ETHTYPE_SA_VID_VFI_SEL_VID_VFI_DATA_SRC, 3856 0, F9_SIPV6, F8_OTAG_DA, 3857 F7_L4_SRC_L4_DST, F6_CLASSID_ALL, 3858 F5_INT_RANGE_CHECK, F4_TOS_TTL, 3859 F3_FLAGS_IP_1_VRF, 3860 F1_DIPV6, 0, 0, 0, F2_FLAG_ESM_KEY_SUBTYPE_0, 3861 F2_FLAG_HG, F2_FLAG_L3_TYPE_3, 3862 F2_FLAG_L3_TYPE_2, F2_FLAG_L3_TYPE_1, 3863 F2_FLAG_L3_TYPE_0, 3864 F2_FLAG_LOOKUP_STATUS_VECTOR_15, 3865 F2_FLAG_LOOKUP_STATUS_VECTOR_0, 3866 F2_FLAG_MH_MIRROR_ONLY, 3867 F2_FLAG_MY_STATION_HIT, 3868 F2_FLAG_FORWARDING_TYPE_2, 3869 F2_FLAG_FORWARDING_TYPE_1, 3870 F2_FLAG_L3_IIF_VALID, 1, KEY_GEN_RSP_TYPE_DIP, 3871 KEY_GEN_RSP_TYPE_ACL, KEY_GEN_RSP_TYPE_SIP, 3872 KEY_GEN_RSP_TYPE_L2_SA, 3, 11, 5, 3873 TR3_LTR_LIB_ACL_IP6S_DIPV6_64, 3874 TR3_LTR_LIB_ACL_IP6F_ACL_SIPV6_64_SA, -1, 2, 1, 3875 3, 0, 8, 8, 8, 0, 3, 7, 3, 6, 0, 1, 2, 0, 0, 3876 0, 0, 0); 3877 SOC_IF_ERROR_RETURN(_soc_write_esm_key_id_to_field_map_entry(unit, 3878 KEY_GEN_OFFSET_TR2_ACL_IP6F_IP6U_FWD, &key_map)); 3879 acl_key_type ^= 1; 3880 } 3881 if (fwd_ipv6_present) { 3882 sal_memset(&key_map, 0, sizeof(key_map)); 3883 acl_key_type = 0; 3884 SOC_TR3_BUILD_FM_ENTRY(key_map, acl_key_type, 3885 F11_DA_ETHTYPE_SA_VID_VFI_SEL_VID_VFI_DATA_SRC, 3886 0, F9_SIPV6, F8_OTAG_DA, 3887 F7_L4_SRC_L4_DST, F6_CLASSID_ALL, 3888 F5_INT_RANGE_CHECK, F4_TOS_TTL, 3889 F3_FLAGS_IP_1_VRF, 3890 F1_DIPV6, 0, 0, 0, F2_FLAG_ESM_KEY_SUBTYPE_0, 3891 F2_FLAG_HG, F2_FLAG_L3_TYPE_3, 3892 F2_FLAG_L3_TYPE_2, F2_FLAG_L3_TYPE_1, 3893 F2_FLAG_L3_TYPE_0, 3894 F2_FLAG_LOOKUP_STATUS_VECTOR_15, 3895 F2_FLAG_LOOKUP_STATUS_VECTOR_0, 3896 F2_FLAG_MH_MIRROR_ONLY, 3897 F2_FLAG_MY_STATION_HIT, 3898 F2_FLAG_FORWARDING_TYPE_2, 3899 F2_FLAG_FORWARDING_TYPE_1, 3900 F2_FLAG_L3_IIF_VALID, 1, KEY_GEN_RSP_TYPE_DIP, 3901 KEY_GEN_RSP_TYPE_ACL, KEY_GEN_RSP_TYPE_SIP, 3902 KEY_GEN_RSP_TYPE_L2_SA, 3, 11, 5, 3903 TR3_LTR_LIB_ACL_IP6S_DIP, 3904 TR3_LTR_LIB_ACL_IP6F_ACL_SIP_SA, -1, 2, 1, 3905 3, 0, 8, 8, 8, 0, 3, 7, 3, 5, 0, 1, 2, 0, 0, 3906 0, 0, 0); 3907 SOC_IF_ERROR_RETURN(_soc_write_esm_key_id_to_field_map_entry(unit, 3908 KEY_GEN_OFFSET_TR2_ACL_IP6F, &key_map)); 3909 acl_key_type ^= 1; 3910 } 3911 if (fwd_l2_present) { 3912 sal_memset(&key_map, 0, sizeof(key_map)); 3913 SOC_TR3_BUILD_FM_ENTRY(key_map, acl_key_type, 3914 F11_DA_ETHTYPE_SA_VID_VFI_SEL_VID_VFI_DATA_SRC, 3915 0, F9_SIPV6, F8_OTAG_DA, 3916 F7_L4_SRC_L4_DST, F6_CLASSID_ALL, 3917 F5_INT_RANGE_CHECK, F4_TOS_TTL, 3918 F3_FREE_BIT_VID_VFI_SEL_VID_VFI_DATA_DST, 3919 F1_DIPV6, 0, 0, 0, F2_FLAG_ESM_KEY_SUBTYPE_0, 3920 F2_FLAG_HG, F2_FLAG_L3_TYPE_3, 3921 F2_FLAG_L3_TYPE_2, F2_FLAG_L3_TYPE_1, 3922 F2_FLAG_L3_TYPE_0, 3923 F2_FLAG_LOOKUP_STATUS_VECTOR_15, 3924 F2_FLAG_LOOKUP_STATUS_VECTOR_0, 3925 F2_FLAG_MH_MIRROR_ONLY, 3926 F2_FLAG_MY_STATION_HIT, 3927 F2_FLAG_FORWARDING_TYPE_2, 3928 F2_FLAG_FORWARDING_TYPE_1, 3929 F2_FLAG_L3_IIF_VALID, 1, 3930 KEY_GEN_RSP_TYPE_L2_DA, KEY_GEN_RSP_TYPE_ACL, 3931 KEY_GEN_RSP_TYPE_L2_SA, 3932 0, 3, 11, 4, 3933 TR3_LTR_LIB_ACL_IP6F_L2_DA, 3934 TR3_LTR_LIB_ACL_IP6F_L2_ACL_SA, -1, 2, 1, 3935 2, 0, 8, 8, 8, 0, 4, 7, 5, 4, 0, 1, 2, 0, 0, 3936 0, 0, 0); 3937 SOC_IF_ERROR_RETURN(_soc_write_esm_key_id_to_field_map_entry(unit, 3938 KEY_GEN_OFFSET_TR2_ACL_IP6F_L2, &key_map)); 3939 acl_key_type ^= 1; 3940 } 3941 if (!fwd_ipv6_present || !fwd_ipv6u_present || !fwd_l2_present) { 3942 sal_memset(&key_map, 0, sizeof(key_map)); 3943 acl_key_type = 0; 3944 SOC_TR3_BUILD_FM_ENTRY(key_map, acl_key_type, 3945 F11_DA_ETHTYPE_SA_VID_VFI_SEL_VID_VFI_DATA_SRC, 3946 0, F9_SIPV6, F8_OTAG_DA, 3947 F7_L4_SRC_L4_DST, F6_CLASSID_ALL, 3948 F5_INT_RANGE_CHECK, F4_TOS_TTL, 3949 F3_FLAGS_IP_1_VRF, 3950 F1_DIPV6, 0, 0, 0, F2_FLAG_ESM_KEY_SUBTYPE_0, 3951 F2_FLAG_HG, F2_FLAG_L3_TYPE_3, 3952 F2_FLAG_L3_TYPE_2, F2_FLAG_L3_TYPE_1, 3953 F2_FLAG_L3_TYPE_0, 3954 F2_FLAG_LOOKUP_STATUS_VECTOR_15, 3955 F2_FLAG_LOOKUP_STATUS_VECTOR_0, 3956 F2_FLAG_MH_MIRROR_ONLY, 3957 F2_FLAG_MY_STATION_HIT, 3958 F2_FLAG_FORWARDING_TYPE_2, 3959 F2_FLAG_FORWARDING_TYPE_1, 3960 F2_FLAG_L3_IIF_VALID, 1, 3961 KEY_GEN_RSP_TYPE_ACL, 3962 0, 0, 0, 3963 2, 11, 2, 3964 TR3_LTR_LIB_ACL_IP6F_ONLY, 3965 -1, -1, 1, 1, 3966 0, 0, 8, 8, 8, 0, 7, 7, 9, 0, 0, 2, 0, 0, 0, 3967 0, 0, 0); 3968 SOC_IF_ERROR_RETURN(_soc_write_esm_key_id_to_field_map_entry(unit, 3969 KEY_GEN_OFFSET_TR2_ACL_IP6F_ONLY, &key_map)); 3970 } 3971 } 3972 3973 /* TR2 L2_IPV6_ACL (ACL_L2IP6) */ 3974 if (partitions[TCAM_PARTITION_ACL_L2IP6].num_entries) { 3975 if (fwd_ipv6_present) { 3976 sal_memset(&key_map, 0, sizeof(key_map)); 3977 acl_key_type = 0; 3978 if (soc_property_get(unit, spn_EXT_L2IP6_ACL_TABLE_MASTER_KEY_TYPE, 0) == 1) { 3979 SOC_TR3_BUILD_FM_ENTRY(key_map, acl_key_type, 3980 F11_DA_ETHTYPE_SA_VID_VFI_SEL_VID_VFI_DATA_SRC, 3981 0, F9_SIPV6, F8_IP_FLOW_V6_BITS_FLAGS_IPV4, 3982 F7_SGLP_DGLP, F6_L4_SRC_L4_DST, 3983 F5_L3_PROTOCOL_TOS, F4_OTAG, 3984 F3_FLAGS_IP_1_VRF, 3985 F1_DIPV6, 3986 F2_FLAG_LOOKUP_STATUS_VECTOR_15, 3987 F2_FLAG_LOOKUP_STATUS_VECTOR_13, 3988 F2_FLAG_LOOKUP_STATUS_VECTOR_12, 3989 F2_FLAG_LOOKUP_STATUS_VECTOR_11, 3990 F2_FLAG_LOOKUP_STATUS_VECTOR_10, 3991 F2_FLAG_LOOKUP_STATUS_VECTOR_9, 3992 F2_FLAG_LOOKUP_STATUS_VECTOR_8, 3993 F2_FLAG_LOOKUP_STATUS_VECTOR_7, 3994 F2_FLAG_LOOKUP_STATUS_VECTOR_6, 3995 F2_FLAG_LOOKUP_STATUS_VECTOR_2, 3996 F2_FLAG_LOOKUP_STATUS_VECTOR_1, 3997 F2_FLAG_LOOKUP_STATUS_VECTOR_0, 3998 F2_FLAG_MY_STATION_HIT, 3999 F2_FLAG_FORWARDING_TYPE_2, 4000 F2_FLAG_FORWARDING_TYPE_1, 4001 F2_FLAG_L3_IIF_VALID, 4002 1, KEY_GEN_RSP_TYPE_DIP, 4003 KEY_GEN_RSP_TYPE_ACL, KEY_GEN_RSP_TYPE_SIP, 4004 KEY_GEN_RSP_TYPE_L2_SA, 3, 10, 5, 4005 TR3_LTR_LIB_ACL_IP6S_DIP, 4006 TR3_LTR_LIB_ACL_L2IP6_ACL_SIP_SA, -1, 2, 1, 4007 3, 0, 8, 8, 8, 0, 3, 7, 3, 6, 0, 1, 2, 0, 0, 4008 0, 0, 0); 4009 SOC_IF_ERROR_RETURN(_soc_write_esm_key_id_to_field_map_entry(unit, 4010 KEY_GEN_OFFSET_TR2_ACL_L2IP6, &key_map)); 4011 } else { 4012 SOC_TR3_BUILD_FM_ENTRY(key_map, acl_key_type, 4013 F11_DA_ETHTYPE_SA_VID_VFI_SEL_VID_VFI_DATA_SRC, 4014 0, F9_SIPV6, 0, 0, F6_L4_SRC_L4_DST, 4015 F5_L3_PROTOCOL_TOS, F4_OTAG, 4016 F3_FLAGS_IP_1_VRF, 4017 F1_DIPV6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4018 F2_FLAG_ESM_KEY_SUBTYPE_0, F2_FLAG_HG, 4019 F2_FLAG_LOOKUP_STATUS_VECTOR_15, 4020 F2_FLAG_MY_STATION_HIT, 4021 F2_FLAG_FORWARDING_TYPE_2, 4022 F2_FLAG_FORWARDING_TYPE_1, 4023 F2_FLAG_L3_IIF_VALID, 1, KEY_GEN_RSP_TYPE_DIP, 4024 KEY_GEN_RSP_TYPE_ACL, KEY_GEN_RSP_TYPE_SIP, 4025 KEY_GEN_RSP_TYPE_L2_SA, 3, 10, 5, 4026 TR3_LTR_LIB_ACL_IP6S_DIP, 4027 TR3_LTR_LIB_ACL_L2IP6_ACL_SIP_SA, -1, 2, 1, 4028 3, 0, 8, 8, 8, 0, 3, 7, 3, 5, 0, 1, 2, 0, 0, 4029 0, 0, 0); 4030 SOC_IF_ERROR_RETURN(_soc_write_esm_key_id_to_field_map_entry(unit, 4031 KEY_GEN_OFFSET_TR2_ACL_L2IP6, &key_map)); 4032 } 4033 acl_key_type ^= 1; 4034 } 4035 if (fwd_l2_present) { 4036 sal_memset(&key_map, 0, sizeof(key_map)); 4037 if (soc_property_get(unit, spn_EXT_L2IP6_ACL_TABLE_MASTER_KEY_TYPE, 0) == 1) { 4038 SOC_TR3_BUILD_FM_ENTRY(key_map, acl_key_type, 4039 F11_SA_OTAG_DA_ETHTYPE, 4040 0, F9_SIPV6, F8_IP_FLOW_V6_BITS_FLAGS_IPV4, 4041 F7_SGLP_DGLP, F6_L4_SRC_L4_DST, 4042 F5_L3_PROTOCOL_TOS, 4043 F4_FREE_BIT_VID_VFI_SEL_VID_VFI_DATA_DST, 4044 F3_FLAGS_IP_1_VRF, 4045 F1_DIPV6, 4046 F2_FLAG_LOOKUP_STATUS_VECTOR_15, 4047 F2_FLAG_LOOKUP_STATUS_VECTOR_13, 4048 F2_FLAG_LOOKUP_STATUS_VECTOR_12, 4049 F2_FLAG_LOOKUP_STATUS_VECTOR_11, 4050 F2_FLAG_LOOKUP_STATUS_VECTOR_10, 4051 F2_FLAG_LOOKUP_STATUS_VECTOR_9, 4052 F2_FLAG_LOOKUP_STATUS_VECTOR_8, 4053 F2_FLAG_LOOKUP_STATUS_VECTOR_7, 4054 F2_FLAG_LOOKUP_STATUS_VECTOR_6, 4055 F2_FLAG_LOOKUP_STATUS_VECTOR_2, 4056 F2_FLAG_LOOKUP_STATUS_VECTOR_1, 4057 F2_FLAG_LOOKUP_STATUS_VECTOR_0, 4058 F2_FLAG_MY_STATION_HIT, 4059 F2_FLAG_FORWARDING_TYPE_2, 4060 F2_FLAG_FORWARDING_TYPE_1, 4061 F2_FLAG_L3_IIF_VALID, 4062 1, KEY_GEN_RSP_TYPE_L2_DA, 4063 KEY_GEN_RSP_TYPE_ACL, KEY_GEN_RSP_TYPE_L2_SA, 4064 0, 3, 11, 4, 4065 TR3_LTR_LIB_ACL_L2IP6_L2_DA, 4066 TR3_LTR_LIB_ACL_L2IP6_L2_ACL_SA, -1, 2, 1, 4067 2, 0, 8, 8, 8, 0, 7, 7, 8, 1, 0, 1, 2, 0, 0, 4068 0, 0, 0); 4069 SOC_IF_ERROR_RETURN(_soc_write_esm_key_id_to_field_map_entry(unit, 4070 KEY_GEN_OFFSET_TR2_ACL_L2IP6_L2, &key_map)); 4071 } else { 4072 SOC_TR3_BUILD_FM_ENTRY(key_map, acl_key_type, 4073 F11_DA_ETHTYPE_SA_VID_VFI_SEL_VID_VFI_DATA_SRC, 4074 0, F9_SIPV6, F8_OTAG_DA, 4075 0, F6_L4_SRC_L4_DST, 4076 F5_L3_PROTOCOL_TOS, F4_FLAGS_IP_1_VRF, 4077 F3_FREE_BIT_VID_VFI_SEL_VID_VFI_DATA_DST, 4078 F1_DIPV6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4079 F2_FLAG_ESM_KEY_SUBTYPE_0, F2_FLAG_HG, 4080 F2_FLAG_LOOKUP_STATUS_VECTOR_15, 4081 F2_FLAG_MY_STATION_HIT, 4082 F2_FLAG_FORWARDING_TYPE_2, 4083 F2_FLAG_FORWARDING_TYPE_1, 4084 F2_FLAG_L3_IIF_VALID, 1,KEY_GEN_RSP_TYPE_L2_DA, 4085 KEY_GEN_RSP_TYPE_ACL, KEY_GEN_RSP_TYPE_L2_SA, 4086 0, 3, 11, 4, 4087 TR3_LTR_LIB_ACL_L2IP6_L2_DA, 4088 TR3_LTR_LIB_ACL_L2IP6_L2_ACL_SA, -1, 2, 1, 4089 2, 0, 8, 8, 8, 0, 4, 7, 5, 4, 0, 1, 2, 0, 0, 4090 0, 0, 0); 4091 SOC_IF_ERROR_RETURN(_soc_write_esm_key_id_to_field_map_entry(unit, 4092 KEY_GEN_OFFSET_TR2_ACL_L2IP6_L2, &key_map)); 4093 } 4094 acl_key_type ^= 1; 4095 } 4096 if (!fwd_ipv6_present || !fwd_l2_present) { 4097 sal_memset(&key_map, 0, sizeof(key_map)); 4098 if (soc_property_get(unit, spn_EXT_L2IP6_ACL_TABLE_MASTER_KEY_TYPE, 0) == 1) { 4099 SOC_TR3_BUILD_FM_ENTRY(key_map, acl_key_type, 4100 F11_DA_ETHTYPE_SA_VID_VFI_SEL_VID_VFI_DATA_SRC, 4101 0, F9_SIPV6, F8_IP_FLOW_V6_BITS_FLAGS_IPV4, 4102 F7_SGLP_DGLP, F6_L4_SRC_L4_DST, 4103 F5_L3_PROTOCOL_TOS, F4_OTAG, 4104 F3_FLAGS_IP_1_VRF, 4105 F1_DIPV6, 4106 F2_FLAG_LOOKUP_STATUS_VECTOR_15, 4107 F2_FLAG_LOOKUP_STATUS_VECTOR_13, 4108 F2_FLAG_LOOKUP_STATUS_VECTOR_12, 4109 F2_FLAG_LOOKUP_STATUS_VECTOR_11, 4110 F2_FLAG_LOOKUP_STATUS_VECTOR_10, 4111 F2_FLAG_LOOKUP_STATUS_VECTOR_9, 4112 F2_FLAG_LOOKUP_STATUS_VECTOR_8, 4113 F2_FLAG_LOOKUP_STATUS_VECTOR_7, 4114 F2_FLAG_LOOKUP_STATUS_VECTOR_6, 4115 F2_FLAG_LOOKUP_STATUS_VECTOR_2, 4116 F2_FLAG_LOOKUP_STATUS_VECTOR_1, 4117 F2_FLAG_LOOKUP_STATUS_VECTOR_0, 4118 F2_FLAG_MY_STATION_HIT, 4119 F2_FLAG_FORWARDING_TYPE_2, 4120 F2_FLAG_FORWARDING_TYPE_1, 4121 F2_FLAG_L3_IIF_VALID, 4122 1, KEY_GEN_RSP_TYPE_ACL, 4123 0, 0, 0, 2, 9, 2, 4124 TR3_LTR_LIB_ACL_L2IP6_ONLY, 4125 -1, -1, 1, 1, 4126 0, 0, 8, 8, 8, 0, 7, 7, 9, 0, 0, 2, 0, 0, 0, 4127 0, 0, 0); 4128 SOC_IF_ERROR_RETURN(_soc_write_esm_key_id_to_field_map_entry(unit, 4129 KEY_GEN_OFFSET_TR2_ACL_L2IP6_L2, &key_map)); 4130 } else { 4131 SOC_TR3_BUILD_FM_ENTRY(key_map, acl_key_type, 4132 F11_DA_ETHTYPE_SA_VID_VFI_SEL_VID_VFI_DATA_SRC, 4133 0, F9_SIPV6, 0, 0, F6_L4_SRC_L4_DST, 4134 F5_L3_PROTOCOL_TOS, F4_OTAG, 4135 F3_FLAGS_IP_1_VRF, 4136 F1_DIPV6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4137 F2_FLAG_ESM_KEY_SUBTYPE_0, F2_FLAG_HG, 4138 F2_FLAG_LOOKUP_STATUS_VECTOR_15, 4139 F2_FLAG_MY_STATION_HIT, 4140 F2_FLAG_FORWARDING_TYPE_2, 4141 F2_FLAG_FORWARDING_TYPE_1, 4142 F2_FLAG_L3_IIF_VALID, 1, KEY_GEN_RSP_TYPE_ACL, 4143 0, 0, 0, 2, 9, 2, 4144 TR3_LTR_LIB_ACL_L2IP6_ONLY, 4145 -1, -1, 1, 1, 4146 0, 0, 8, 8, 8, 0, 7, 7, 8, 0, 0, 2, 0, 0, 0, 4147 0, 0, 0); 4148 SOC_IF_ERROR_RETURN(_soc_write_esm_key_id_to_field_map_entry(unit, 4149 KEY_GEN_OFFSET_TR2_ACL_L2IP6_ONLY, &key_map)); 4150 } 4151 } 4152 } 4153 return SOC_E_NONE; 4154 } 4155 4156 int soc_triumph3_esm_init(int unit) 4157 { 4158 uint32 esm_search_profile_base=0; 4159 /* 64 ports, 100 bits of source_trunk_map per port */ 4160 int idx_end=63; 4161 int alloc_size, rv; 4162 uint8 *buf; 4163 uint32 tmp2=0; 4164 uint32 l2_entry_mask[2]; 4165 ext_l2_entry_tcam_entry_t l2_entry; 4166 int i; 4167 int blks_per_dev; 4168 esm_range_check_entry_t *range_check_entry; 4169 esm_l3_protocol_fn_entry_t *l3_proto_fn_entry; 4170 soc_tcam_info_t *tcam_info; 4171 soc_tcam_partition_t *partitions; 4172 int l2_fast_init_done = 0, l2_wide_fast_init_done = 0; 4173 int l2_start_tcam_idx, l2_num_tcams; 4174 4175 tcam_info = SOC_CONTROL(unit)->tcam_info; 4176 if (tcam_info == NULL) { 4177 return SOC_E_NONE; 4178 } 4179 partitions = tcam_info->partitions; 4180 blks_per_dev = tcam_info->blks_per_dev; 4181 4182 SOC_IF_ERROR_RETURN(_soc_triumph3_esm_init_adjust_mem_size(unit)); 4183 4184 SOC_IF_ERROR_RETURN(READ_ESM_EXT_HITBIT_CONTROLr(unit, &tmp2)); 4185 soc_reg_field_set(unit, ESM_EXT_HITBIT_CONTROLr, &tmp2, EN_SET_L2_DST_HITf, 4186 1); 4187 soc_reg_field_set(unit, ESM_EXT_HITBIT_CONTROLr, &tmp2,EN_SET_L2_SRC_HITf, 4188 1); 4189 soc_reg_field_set(unit, ESM_EXT_HITBIT_CONTROLr, &tmp2, EN_SET_L3_DST_HITf, 4190 1); 4191 soc_reg_field_set(unit, ESM_EXT_HITBIT_CONTROLr, &tmp2,EN_SET_L3_SRC_HITf, 4192 1); 4193 SOC_IF_ERROR_RETURN(WRITE_ESM_EXT_HITBIT_CONTROLr(unit, tmp2)); 4194 4195 SOC_IF_ERROR_RETURN(_soc_tr3_set_dup_db_offset(unit)); 4196 4197 /* MISC ACL fields */ 4198 #if 1 4199 idx_end = soc_mem_index_max(unit, ESM_RANGE_CHECKm); 4200 alloc_size = (idx_end+1) * sizeof(esm_range_check_entry_t); 4201 buf = soc_cm_salloc(unit, alloc_size, "esm_range_check"); 4202 if (buf == NULL) return SOC_E_MEMORY; 4203 rv = soc_mem_read_range(unit, ESM_RANGE_CHECKm, MEM_BLOCK_ANY, 4204 0, idx_end, buf); 4205 if (rv < 0) { 4206 soc_cm_sfree(unit, buf); 4207 return SOC_E_FAIL; 4208 } 4209 for (i = 0; i < idx_end + 1; i++) { 4210 range_check_entry = soc_mem_table_idx_to_pointer 4211 (unit, ESM_RANGE_CHECKm, esm_range_check_entry_t *, buf, i); 4212 soc_mem_field32_set(unit, ESM_RANGE_CHECKm, range_check_entry, 4213 ENABLEf, 0); 4214 soc_mem_field32_set(unit, ESM_RANGE_CHECKm, range_check_entry, 4215 FIELD_SELECTf, 0); 4216 soc_mem_field32_set(unit, ESM_RANGE_CHECKm, range_check_entry, 4217 UPPER_BOUNDSf, 0); 4218 soc_mem_field32_set(unit, ESM_RANGE_CHECKm, range_check_entry, 4219 LOWER_BOUNDSf, 0); 4220 } 4221 rv = soc_mem_write_range(unit, ESM_RANGE_CHECKm, MEM_BLOCK_ANY, 4222 0, idx_end, (void *) buf); 4223 soc_cm_sfree(unit, buf); 4224 if (rv < 0 ) return SOC_E_FAIL; 4225 #else 4226 soc_mem_clear(unit, ESM_RANGE_CHECKm, MEM_BLOCK_ALL, TRUE); 4227 #endif 4228 4229 #if 1 4230 /* ESM_L3_PROTOCOL_FN */ 4231 idx_end = soc_mem_index_max(unit, ESM_L3_PROTOCOL_FNm); 4232 alloc_size = (idx_end+1) * sizeof(esm_l3_protocol_fn_entry_t); 4233 buf = soc_cm_salloc(unit, alloc_size, "esm_l3_protocol_fn"); 4234 if (buf == NULL) return SOC_E_MEMORY; 4235 rv = soc_mem_read_range(unit, ESM_L3_PROTOCOL_FNm, MEM_BLOCK_ANY, 4236 0, idx_end, buf); 4237 if (rv < 0) { 4238 soc_cm_sfree(unit, buf); 4239 return SOC_E_FAIL; 4240 } 4241 for (i = 0; i < idx_end + 1; i++) { 4242 l3_proto_fn_entry = soc_mem_table_idx_to_pointer 4243 (unit, ESM_L3_PROTOCOL_FNm, esm_l3_protocol_fn_entry_t *, buf, i); 4244 soc_mem_field32_set(unit, ESM_L3_PROTOCOL_FNm, l3_proto_fn_entry, 4245 L3_PROTOCOL_FNf, 0); 4246 } 4247 rv = soc_mem_write_range(unit, ESM_L3_PROTOCOL_FNm, MEM_BLOCK_ANY, 4248 0, idx_end, (void *) buf); 4249 soc_cm_sfree(unit, buf); 4250 if (rv < 0 ) return SOC_E_FAIL; 4251 #else 4252 soc_mem_clear(unit, ESM_L3_PROTOCOL_FNm, MEM_BLOCK_ALL, TRUE); 4253 #endif 4254 4255 /* ESM_CONTAINER_SELECT */ 4256 tmp2 = 0; 4257 SOC_IF_ERROR_RETURN(WRITE_ESM_CONTAINER_SELECTr(unit, tmp2)); 4258 4259 /* program the ET_PA_XLAT entries */ 4260 SOC_IF_ERROR_RETURN(_soc_triumph3_esm_init_set_et_pa_xlate(unit)); 4261 4262 /* initialize worst_case fme entry */ 4263 tr3_worst_fme[unit].cost0 = 0; 4264 tr3_worst_fme[unit].cost1 = 0; 4265 tr3_worst_fme[unit].cost2 = 0; 4266 tr3_worst_fme[unit].idx = 0; 4267 SOC_IF_ERROR_RETURN(_soc_tr3_build_fm_table(unit, tcam_info)); 4268 4269 4270 /* program ESM search profile base */ 4271 soc_reg_field_set(unit, ESM_SEARCH_PROFILE_BASEr, &esm_search_profile_base, 4272 SRC_TRUNK_MAPf, 5); 4273 soc_reg_field_set(unit, ESM_SEARCH_PROFILE_BASEr, &esm_search_profile_base, 4274 VLAN_XLATEf, 4); 4275 soc_reg_field_set(unit, ESM_SEARCH_PROFILE_BASEr, &esm_search_profile_base, 4276 VFPf, 3); 4277 soc_reg_field_set(unit, ESM_SEARCH_PROFILE_BASEr, &esm_search_profile_base, 4278 VLANf, 2); 4279 soc_reg_field_set(unit, ESM_SEARCH_PROFILE_BASEr, &esm_search_profile_base, 4280 SOURCE_VPf, 1); 4281 soc_reg_field_set(unit, ESM_SEARCH_PROFILE_BASEr, &esm_search_profile_base, 4282 L3_IIFf, 0); 4283 SOC_IF_ERROR_RETURN(WRITE_ESM_SEARCH_PROFILE_BASEr(unit, 4284 esm_search_profile_base)); 4285 4286 rv = _soc_tr3_esm_init_pkt_type_tcam(unit, partitions); 4287 SOC_IF_ERROR_RETURN(rv); 4288 4289 rv = _soc_tr3_esm_fill_search_profile(unit); 4290 SOC_IF_ERROR_RETURN(rv); 4291 4292 /* better init values, using TR2 ACL info: */ 4293 rv = _soc_tr3_esm_init_set_esm_mode_per_port(unit); 4294 SOC_IF_ERROR_RETURN(rv); 4295 4296 /* initialize L2 table to free */ 4297 sal_memset(&l2_entry, 0, sizeof(l2_entry)); 4298 soc_mem_field32_set(unit, EXT_L2_ENTRY_TCAMm, &l2_entry, FREEf, 1); 4299 soc_mem_field32_set(unit, EXT_L2_ENTRY_TCAMm, &l2_entry, MASK_FREEf, 0); 4300 l2_entry_mask[0]=0xffffffff; 4301 l2_entry_mask[1]=0xffff; 4302 soc_mem_field_set(unit, EXT_L2_ENTRY_TCAMm, (uint32 *) &l2_entry, 4303 MASK_MAC_ADDRf, l2_entry_mask); 4304 soc_mem_field32_set(unit, EXT_L2_ENTRY_TCAMm, &l2_entry, MASK_VLAN_IDf, 4305 0xfff); 4306 soc_mem_field32_set(unit, EXT_L2_ENTRY_TCAMm, &l2_entry, 4307 MASK_VLAN_ID_UNUSEDf, 0x3); 4308 soc_mem_field32_set(unit, EXT_L2_ENTRY_TCAMm, &l2_entry, 4309 MASK_KEY_TYPEf, 0x1); 4310 4311 /* 4312 * If a TCAM is entirely allocated for L2/L2_WIDE partition, 4313 * then initialize that TCAM with fast init sequence to save time. 4314 * In case TCAM is not entirely allocated for L2/L2_WIDE, then it'll be 4315 * fast inited using soc_tr3_tcam_fast_init() and then the L2 4316 * partitions will be initialized by soc_mem_write per each index 4317 */ 4318 if (!(soc_mem_index_count(unit, EXT_L2_ENTRY_TCAMm) % 4319 (blks_per_dev * TR3_ENTRIES_PER_BLK))) { 4320 if (!(partitions[TCAM_PARTITION_FWD_L2].tcam_base % 4321 (blks_per_dev * TR3_ENTRIES_PER_BLK))) { 4322 l2_num_tcams = soc_mem_index_count(unit, EXT_L2_ENTRY_TCAMm) / 4323 (blks_per_dev * TR3_ENTRIES_PER_BLK); 4324 if (l2_num_tcams) { 4325 l2_start_tcam_idx = 4326 partitions[TCAM_PARTITION_FWD_L2].tcam_base / 4327 (blks_per_dev * TR3_ENTRIES_PER_BLK); 4328 SOC_IF_ERROR_RETURN(soc_tr3_tcam_l2_fast_init(unit, 4329 l2_start_tcam_idx, l2_num_tcams, &l2_entry)); 4330 } 4331 l2_fast_init_done = TRUE; 4332 } 4333 } 4334 4335 if (!(soc_mem_index_count(unit, EXT_L2_ENTRY_TCAM_WIDEm) % 4336 (blks_per_dev * TR3_ENTRIES_PER_BLK))) { 4337 if (!(partitions[TCAM_PARTITION_FWD_L2_WIDE].tcam_base % 4338 (blks_per_dev * TR3_ENTRIES_PER_BLK))) { 4339 l2_num_tcams = soc_mem_index_count(unit, EXT_L2_ENTRY_TCAM_WIDEm) / 4340 (blks_per_dev * TR3_ENTRIES_PER_BLK); 4341 if (l2_num_tcams) { 4342 l2_start_tcam_idx = 4343 partitions[TCAM_PARTITION_FWD_L2_WIDE].tcam_base / 4344 (blks_per_dev * TR3_ENTRIES_PER_BLK); 4345 SOC_IF_ERROR_RETURN(soc_tr3_tcam_l2_fast_init(unit, 4346 l2_start_tcam_idx, l2_num_tcams, &l2_entry)); 4347 } 4348 l2_wide_fast_init_done = TRUE; 4349 } 4350 } 4351 4352 /* 4353 * Fast Init the other TCAMs not covered in L2 fast init 4354 */ 4355 if (!SOC_WARM_BOOT(unit)) { 4356 soc_tr3_tcam_fast_init(unit); 4357 } 4358 4359 if (!l2_fast_init_done) { 4360 for (i = 0; i < soc_mem_index_count(unit, EXT_L2_ENTRY_TCAMm); i++) { 4361 SOC_IF_ERROR_RETURN(soc_mem_write(unit, EXT_L2_ENTRY_TCAMm, 4362 MEM_BLOCK_ANY, i, &l2_entry)); 4363 } 4364 } 4365 4366 if (!l2_wide_fast_init_done) { 4367 for (i = 0; i < soc_mem_index_count(unit, EXT_L2_ENTRY_TCAM_WIDEm); 4368 i++) { 4369 SOC_IF_ERROR_RETURN(soc_mem_write(unit, EXT_L2_ENTRY_TCAM_WIDEm, 4370 MEM_BLOCK_ANY, i, &l2_entry)); 4371 } 4372 } 4373 4374 return SOC_E_NONE; 4375 } 4376 4377 void 4378 soc_triumph3_esm_init_mem_config(int unit) 4379 { 4380 soc_persist_t *sop; 4381 sop_memstate_t *memState; 4382 4383 if (soc_property_get(unit, "AV_SIMULATION", 0)) { 4384 return; 4385 } 4386 4387 sop = SOC_PERSIST(unit); 4388 memState = sop->memState; 4389 4390 /* L2 forwarding partition */ 4391 memState[EXT_L2_ENTRY_1m].index_max = -1; /* TCAM + SRAM */ 4392 memState[EXT_L2_ENTRY_2m].index_max = -1; /* TCAM */ 4393 memState[EXT_L2_ENTRY_TCAMm].index_max = -1; /* TCAM */ 4394 memState[EXT_L2_ENTRY_TCAM_WIDEm].index_max = -1; /* TCAM */ 4395 memState[EXT_L2_ENTRY_DATA_ONLYm].index_max = -1; /* SRAM */ 4396 memState[EXT_L2_ENTRY_DATA_ONLY_WIDEm].index_max = -1; /* SRAM */ 4397 memState[EXT_SRC_HIT_BITS_L2m].index_max = -1; /* SRC hit bit */ 4398 memState[EXT_DST_HIT_BITS_L2m].index_max = -1; /* DST hit bit */ 4399 memState[EXT_SRC_HIT_BITS_L2_WIDEm].index_max = -1; /* SRC hit bit */ 4400 memState[EXT_DST_HIT_BITS_L2_WIDEm].index_max = -1; /* DST hit bit */ 4401 memState[EXT_LOC_SRC_HIT_BITS_L2m].index_max = -1; /* DST hit bit */ 4402 memState[EXT_LOC_SRC_HIT_BITS_L2_WIDEm].index_max = -1; /* DST hit bit */ 4403 memState[EXT_TCAM_VBIT_L2_ENTRY_1m].index_max = -1; 4404 memState[EXT_TCAM_VBIT_L2_ENTRY_2m].index_max = -1; 4405 4406 /* IP4 forwarding partition */ 4407 memState[EXT_IPV4_DEFIPm].index_max = -1; /* TCAM + SRAM */ 4408 memState[EXT_IPV4_DEFIP_TCAMm].index_max = -1; /* TCAM */ 4409 memState[EXT_DEFIP_DATA_IPV4m].index_max = -1; /* SRAM */ 4410 memState[EXT_IPV4_UCASTm].index_max = -1; /* TCAM + SRAM */ 4411 memState[EXT_IPV4_UCAST_TCAMm].index_max = -1; /* TCAM + SRAM */ 4412 memState[EXT_L3_UCAST_DATA_IPV4m].index_max = -1; /* TCAM + SRAM */ 4413 memState[EXT_IPV4_UCAST_WIDEm].index_max = -1; /* TCAM + SRAM */ 4414 memState[EXT_IPV4_UCAST_WIDE_TCAMm].index_max = -1; /* TCAM + SRAM */ 4415 memState[EXT_L3_UCAST_DATA_WIDE_IPV4m].index_max = -1; /* TCAM + SRAM */ 4416 memState[EXT_SRC_HIT_BITS_IPV4_UCASTm].index_max = -1; /* SRC hit bit */ 4417 memState[EXT_DST_HIT_BITS_IPV4_UCASTm].index_max = -1; /* DST hit bit */ 4418 memState[EXT_SRC_HIT_BITS_IPV4_UCAST_WIDEm].index_max = -1; /* SRC hit bit */ 4419 memState[EXT_DST_HIT_BITS_IPV4_UCAST_WIDEm].index_max = -1; /* DST hit bit */ 4420 memState[EXT_SRC_HIT_BITS_IPV4m].index_max = -1; /* SRC hit bit */ 4421 memState[EXT_DST_HIT_BITS_IPV4m].index_max = -1; /* DST hit bit */ 4422 memState[EXT_TCAM_VBIT_DEFIP_IPV4m].index_max = -1; 4423 memState[EXT_TCAM_VBIT_IPV4_UCASTm].index_max = -1; 4424 memState[EXT_TCAM_VBIT_IPV4_UCAST_WIDEm].index_max = -1; 4425 4426 /* IP6 64-bit prefix forwarding partition */ 4427 memState[EXT_IPV6_64_DEFIPm].index_max = -1; /* TCAM + SRAM */ 4428 memState[EXT_IPV6_64_DEFIP_TCAMm].index_max = -1; /* TCAM */ 4429 memState[EXT_DEFIP_DATA_IPV6_64m].index_max = -1; /* SRAM */ 4430 memState[EXT_SRC_HIT_BITS_IPV6_64m].index_max = -1; /* SRC hit bit */ 4431 memState[EXT_DST_HIT_BITS_IPV6_64m].index_max = -1; /* DST hit bit */ 4432 memState[EXT_TCAM_VBIT_DEFIP_IPV6_64m].index_max = -1; 4433 4434 /* IP6 128-bit prefix forwarding partition */ 4435 memState[EXT_IPV6_128_DEFIPm].index_max = -1; /* TCAM + SRAM */ 4436 memState[EXT_IPV6_128_DEFIP_TCAMm].index_max = -1; /* TCAM */ 4437 memState[EXT_DEFIP_DATA_IPV6_128m].index_max = -1; /* SRAM */ 4438 memState[EXT_IPV6_128_UCASTm].index_max = -1; /* TCAM + SRAM */ 4439 memState[EXT_IPV6_128_UCAST_TCAMm].index_max = -1; /* TCAM + SRAM */ 4440 memState[EXT_L3_UCAST_DATA_IPV6_128m].index_max = -1; /* TCAM + SRAM */ 4441 memState[EXT_IPV6_128_UCAST_WIDEm].index_max = -1; /* TCAM + SRAM */ 4442 memState[EXT_IPV6_128_UCAST_WIDE_TCAMm].index_max = -1; /* TCAM + SRAM */ 4443 memState[EXT_L3_UCAST_DATA_WIDE_IPV6_128m].index_max = -1; /* TCAM + SRAM */ 4444 memState[EXT_SRC_HIT_BITS_IPV6_128_UCASTm].index_max = -1; /* SRC hit bit */ 4445 memState[EXT_DST_HIT_BITS_IPV6_128_UCASTm].index_max = -1; /* DST hit bit */ 4446 memState[EXT_SRC_HIT_BITS_IPV6_128_UCAST_WIDEm].index_max = 4447 -1; /* SRC hit bit */ 4448 memState[EXT_DST_HIT_BITS_IPV6_128_UCAST_WIDEm].index_max = 4449 -1; /* DST hit bit */ 4450 memState[EXT_SRC_HIT_BITS_IPV6_128m].index_max = -1; /* SRC hit bit */ 4451 memState[EXT_DST_HIT_BITS_IPV6_128m].index_max = -1; /* DST hit bit */ 4452 memState[EXT_TCAM_VBIT_IPV6_128_UCASTm].index_max = -1; 4453 memState[EXT_TCAM_VBIT_IPV6_128_UCAST_WIDEm].index_max = -1; 4454 memState[EXT_TCAM_VBIT_DEFIP_IPV6_128m].index_max = -1; 4455 4456 /* L2 288-bit ACL partition */ 4457 memState[EXT_ACL288_TCAM_L2m].index_max = -1; /* TCAM */ 4458 memState[EXT_FP_POLICY_ACL288_L2_1Xm].index_max = -1; /* SRAM */ 4459 memState[EXT_FP_POLICY_ACL288_L2_2Xm].index_max = -1; /* SRAM */ 4460 memState[EXT_FP_POLICY_ACL288_L2_3Xm].index_max = -1; /* SRAM */ 4461 memState[EXT_FP_POLICY_ACL288_L2_4Xm].index_max = -1; /* SRAM */ 4462 memState[EXT_FP_POLICY_ACL288_L2_6Xm].index_max = -1; /* SRAM */ 4463 4464 /* IP4 288-bit ACL partition */ 4465 memState[EXT_ACL288_TCAM_IPV4m].index_max = -1; /* TCAM */ 4466 memState[EXT_FP_POLICY_ACL288_IPV4_1Xm].index_max = -1; /* SRAM */ 4467 memState[EXT_FP_POLICY_ACL288_IPV4_2Xm].index_max = -1; /* SRAM */ 4468 memState[EXT_FP_POLICY_ACL288_IPV4_3Xm].index_max = -1; /* SRAM */ 4469 memState[EXT_FP_POLICY_ACL288_IPV4_4Xm].index_max = -1; /* SRAM */ 4470 memState[EXT_FP_POLICY_ACL288_IPV4_6Xm].index_max = -1; /* SRAM */ 4471 4472 /* IP6 short form 360-bit ACL partition */ 4473 memState[EXT_ACL360_TCAM_DATA_IPV6_SHORTm].index_max = -1; /* TCAM data */ 4474 memState[EXT_FP_POLICY_ACL360_IPV6_SHORT_1Xm].index_max = -1; /* SRAM */ 4475 memState[EXT_FP_POLICY_ACL360_IPV6_SHORT_2Xm].index_max = -1; /* SRAM */ 4476 memState[EXT_FP_POLICY_ACL360_IPV6_SHORT_3Xm].index_max = -1; /* SRAM */ 4477 memState[EXT_FP_POLICY_ACL360_IPV6_SHORT_4Xm].index_max = -1; /* SRAM */ 4478 memState[EXT_FP_POLICY_ACL360_IPV6_SHORT_6Xm].index_max = -1; /* SRAM */ 4479 4480 /* IP6 full form 432-bit ACL partition */ 4481 memState[EXT_ACL432_TCAM_DATA_IPV6_LONGm].index_max = -1; /* TCAM data */ 4482 memState[EXT_FP_POLICY_ACL432_IPV6_LONG_1Xm].index_max = -1; /* SRAM */ 4483 memState[EXT_FP_POLICY_ACL432_IPV6_LONG_2Xm].index_max = -1; /* SRAM */ 4484 memState[EXT_FP_POLICY_ACL432_IPV6_LONG_3Xm].index_max = -1; /* SRAM */ 4485 memState[EXT_FP_POLICY_ACL432_IPV6_LONG_4Xm].index_max = -1; /* SRAM */ 4486 memState[EXT_FP_POLICY_ACL432_IPV6_LONG_6Xm].index_max = -1; /* SRAM */ 4487 4488 /* L2 compact form 144-bit ACL partition */ 4489 memState[EXT_ACL144_TCAM_L2m].index_max = -1; /* TCAM */ 4490 memState[EXT_FP_POLICY_ACL144_L2_1Xm].index_max = -1; /* SRAM */ 4491 memState[EXT_FP_POLICY_ACL144_L2_2Xm].index_max = -1; /* SRAM */ 4492 memState[EXT_FP_POLICY_ACL144_L2_3Xm].index_max = -1; /* SRAM */ 4493 memState[EXT_FP_POLICY_ACL144_L2_4Xm].index_max = -1; /* SRAM */ 4494 memState[EXT_FP_POLICY_ACL144_L2_6Xm].index_max = -1; /* SRAM */ 4495 4496 /* IP4 compact form 144-bit ACL partition */ 4497 memState[EXT_ACL144_TCAM_IPV4m].index_max = -1; /* TCAM */ 4498 memState[EXT_FP_POLICY_ACL144_IPV4_1Xm].index_max = -1; /* SRAM */ 4499 memState[EXT_FP_POLICY_ACL144_IPV4_2Xm].index_max = -1; /* SRAM */ 4500 memState[EXT_FP_POLICY_ACL144_IPV4_3Xm].index_max = -1; /* SRAM */ 4501 memState[EXT_FP_POLICY_ACL144_IPV4_4Xm].index_max = -1; /* SRAM */ 4502 memState[EXT_FP_POLICY_ACL144_IPV4_6Xm].index_max = -1; /* SRAM */ 4503 4504 /* IP6 compact form 144-bit ACL partition */ 4505 memState[EXT_ACL144_TCAM_IPV6m].index_max = -1; /* TCAM */ 4506 memState[EXT_FP_POLICY_ACL144_IPV6_1Xm].index_max = -1; /* SRAM */ 4507 memState[EXT_FP_POLICY_ACL144_IPV6_2Xm].index_max = -1; /* SRAM */ 4508 memState[EXT_FP_POLICY_ACL144_IPV6_3Xm].index_max = -1; /* SRAM */ 4509 memState[EXT_FP_POLICY_ACL144_IPV6_4Xm].index_max = -1; /* SRAM */ 4510 memState[EXT_FP_POLICY_ACL144_IPV6_6Xm].index_max = -1; /* SRAM */ 4511 4512 /* L2+IP4 432-bit ACL partition */ 4513 memState[EXT_ACL432_TCAM_DATA_L2_IPV4m].index_max = -1; /* TCAM data */ 4514 memState[EXT_FP_POLICY_ACL432_L2_IPV4_1Xm].index_max = -1; /* SRAM */ 4515 memState[EXT_FP_POLICY_ACL432_L2_IPV4_2Xm].index_max = -1; /* SRAM */ 4516 memState[EXT_FP_POLICY_ACL432_L2_IPV4_3Xm].index_max = -1; /* SRAM */ 4517 memState[EXT_FP_POLICY_ACL432_L2_IPV4_4Xm].index_max = -1; /* SRAM */ 4518 memState[EXT_FP_POLICY_ACL432_L2_IPV4_6Xm].index_max = -1; /* SRAM */ 4519 4520 /* L2+IP6 432-bit ACL partition */ 4521 memState[EXT_ACL432_TCAM_DATA_L2_IPV6m].index_max = -1; /* TCAM data */ 4522 memState[EXT_FP_POLICY_ACL432_L2_IPV6_1Xm].index_max = -1; /* SRAM */ 4523 memState[EXT_FP_POLICY_ACL432_L2_IPV6_2Xm].index_max = -1; /* SRAM */ 4524 memState[EXT_FP_POLICY_ACL432_L2_IPV6_3Xm].index_max = -1; /* SRAM */ 4525 memState[EXT_FP_POLICY_ACL432_L2_IPV6_4Xm].index_max = -1; /* SRAM */ 4526 memState[EXT_FP_POLICY_ACL432_L2_IPV6_6Xm].index_max = -1; /* SRAM */ 4527 4528 /* 80-bit ACL partition */ 4529 memState[EXT_ACL80_TCAMm].index_max = -1; /* TCAM */ 4530 memState[EXT_ACL80_FP_POLICY_1Xm].index_max = -1; /* AD */ 4531 memState[EXT_ACL80_FP_POLICY_2Xm].index_max = -1; /* AD */ 4532 memState[EXT_ACL80_FP_POLICY_3Xm].index_max = -1; /* AD */ 4533 memState[EXT_ACL80_FP_POLICY_4Xm].index_max = -1; /* AD */ 4534 memState[EXT_ACL80_FP_POLICY_6Xm].index_max = -1; /* AD */ 4535 4536 /* 160-bit ACL partition */ 4537 memState[EXT_ACL160_TCAMm].index_max = -1; /* TCAM */ 4538 memState[EXT_ACL160_FP_POLICY_1Xm].index_max = -1; /* AD */ 4539 memState[EXT_ACL160_FP_POLICY_2Xm].index_max = -1; /* AD */ 4540 memState[EXT_ACL160_FP_POLICY_3Xm].index_max = -1; /* AD */ 4541 memState[EXT_ACL160_FP_POLICY_4Xm].index_max = -1; /* AD */ 4542 memState[EXT_ACL160_FP_POLICY_6Xm].index_max = -1; /* AD */ 4543 4544 /* 320-bit ACL partition */ 4545 memState[EXT_ACL320_TCAMm].index_max = -1; /* TCAM */ 4546 memState[EXT_ACL320_FP_POLICY_1Xm].index_max = -1; /* AD */ 4547 memState[EXT_ACL320_FP_POLICY_2Xm].index_max = -1; /* AD */ 4548 memState[EXT_ACL320_FP_POLICY_3Xm].index_max = -1; /* AD */ 4549 memState[EXT_ACL320_FP_POLICY_4Xm].index_max = -1; /* AD */ 4550 memState[EXT_ACL320_FP_POLICY_6Xm].index_max = -1; /* AD */ 4551 4552 /* 480-bit ACL partition */ 4553 memState[EXT_ACL432_TCAM_MASKm].index_max = -1; /* TCAM */ 4554 memState[EXT_ACL432_TCAM_MASK_L2_IPV6m].index_max = -1; 4555 memState[EXT_ACL432_TCAM_MASK_IPV6_LONGm].index_max = -1; 4556 memState[EXT_ACL360_TCAM_MASKm].index_max = -1; /* TCAM */ 4557 memState[EXT_ACL360_TCAM_MASK_IPV6_SHORTm].index_max = -1; /* TCAM */ 4558 memState[EXT_ACL480_TCAM_MASKm].index_max = -1; /* TCAM */ 4559 memState[EXT_ACL480_TCAM_DATAm].index_max = -1; /* TCAM */ 4560 memState[EXT_ACL480_FP_POLICY_1Xm].index_max = -1; /* AD */ 4561 memState[EXT_ACL480_FP_POLICY_2Xm].index_max = -1; /* AD */ 4562 memState[EXT_ACL480_FP_POLICY_3Xm].index_max = -1; /* AD */ 4563 memState[EXT_ACL480_FP_POLICY_4Xm].index_max = -1; /* AD */ 4564 memState[EXT_ACL480_FP_POLICY_6Xm].index_max = -1; /* AD */ 4565 4566 /* All L2 local src entries */ 4567 memState[EXT_LOC_SRC_HBITSm].index_max = -1; /* SRC hit bit */ 4568 4569 /* All L2+L3 forwarding entries */ 4570 memState[EXT_SRC_HBITSm].index_max = -1; /* SRC hit bit */ 4571 memState[EXT_DST_HBITSm].index_max = -1; /* DST hit bit */ 4572 4573 /* All L3 forwarding entries */ 4574 memState[EXT_IPV4_TCAMm].index_max = -1; /* SRAM */ 4575 memState[EXT_IPV6_64_TCAMm].index_max = -1; /* SRAM */ 4576 memState[EXT_IPV6_128_TCAMm].index_max = -1; /* SRAM */ 4577 memState[EXT_DEFIP_DATAm].index_max = -1; /* SRAM */ 4578 memState[EXT_L3_UCAST_DATAm].index_max = -1; /* SRAM */ 4579 memState[EXT_L3_UCAST_DATA_WIDEm].index_max = -1; /* SRAM */ 4580 4581 /* All ACL entries */ 4582 memState[EXT_FP_POLICY_1Xm].index_max = -1; /* SRAM */ 4583 memState[EXT_FP_POLICY_2Xm].index_max = -1; /* SRAM */ 4584 memState[EXT_FP_POLICY_3Xm].index_max = -1; /* SRAM */ 4585 memState[EXT_FP_POLICY_4Xm].index_max = -1; /* SRAM */ 4586 memState[EXT_FP_POLICY_6Xm].index_max = -1; /* SRAM */ 4587 4588 memState[EXT_TCAM_VBIT_ACL80m].index_max = -1; /* TCAM */ 4589 memState[EXT_TCAM_VBIT_ACL160m].index_max = -1; /* TCAM */ 4590 memState[EXT_TCAM_VBIT_ACL320m].index_max = -1; /* TCAM */ 4591 memState[EXT_TCAM_VBIT_ACL480m].index_max = -1; /* TCAM */ 4592 memState[EXT_TCAM_VBITm].index_max = -1; /* TCAM */ 4593 } 4594 4595 /* 4596 * Function: 4597 * soc_tr3_search_ext_mem 4598 * Purpose: 4599 * Search triumph3 external memory L3 host tables for a key. 4600 * Parameters: 4601 * mem Memory to search. Specifying EXT_IPV4_UCASTm will 4602 * will search ext V4 host tables and EXT_IPV6_128_UCASTm 4603 * will search ext V6 host tables. 4604 * On successful search the memory in which match occured 4605 * is returned. 4606 * key IN: Data to search for 4607 * index_ptr OUT: 4608 * If entry found gets the location of the entry. 4609 * Returns: 4610 * SOC_E_NOT_FOUND 4611 * Entry not found. 4612 * SOC_E_NONE Entry is found: index_ptr gets location 4613 * SOC_E_XXX If internal error occurs 4614 */ 4615 int 4616 soc_tr3_search_ext_mem(int unit, soc_mem_t *mem, void *key, int *index_ptr) 4617 { 4618 soc_tcam_info_t *tcam_info; 4619 soc_tcam_partition_t *partitions; 4620 uint32 key_words[6], ip_addr_v4; 4621 int v6_key = 0; 4622 int rv=0, part, tmp; 4623 uint16 vrf_id; 4624 uint32 part_to_mem[6] = {EXT_IPV4_UCASTm, EXT_IPV4_UCAST_WIDEm, 0, 0, 4625 EXT_IPV6_128_UCASTm, EXT_IPV6_128_UCAST_WIDEm}; 4626 uint32 field[SOC_MAX_MEM_FIELD_WORDS]; 4627 4628 if ((key == NULL) || (index_ptr == NULL)) { 4629 return SOC_E_PARAM; 4630 } 4631 4632 tcam_info = SOC_CONTROL(unit)->tcam_info; 4633 if (tcam_info == NULL) { 4634 return SOC_E_NOT_FOUND; 4635 } 4636 partitions = tcam_info->partitions; 4637 4638 switch (*mem) { 4639 case EXT_IPV4_UCASTm: 4640 case EXT_IPV4_UCAST_WIDEm: 4641 part = TCAM_PARTITION_FWD_IP4; 4642 break; 4643 case EXT_IPV6_128_UCASTm: 4644 case EXT_IPV6_128_UCAST_WIDEm: 4645 part = TCAM_PARTITION_FWD_IP6; 4646 v6_key = 1; 4647 break; 4648 default: 4649 LOG_CLI((BSL_META_U(unit, 4650 "Invalid memory %d\n"), *mem)); 4651 return SOC_E_PARAM; 4652 } 4653 4654 sal_memset(key_words, 0, sizeof(key_words)); 4655 4656 /* v4/v6 need min of 6 bytes */ 4657 if (!v6_key) { 4658 #if 0 4659 uint8 *keyp; 4660 #endif 4661 4662 vrf_id = soc_EXT_IPV4_TCAMm_field32_get(unit, (uint32 *)key, VRF_IDf); 4663 key_words[2] = 0; 4664 key_words[1] = MAKE_WORD(0, 0, vrf_id >> 8, vrf_id & 0xff); 4665 4666 ip_addr_v4 = soc_EXT_IPV4_TCAMm_field32_get(unit, (uint32 *)key, IP_ADDRf); 4667 #if 0 4668 key_words[0] = MAKE_WORD(keyp[0], keyp[1], keyp[2], keyp[3]); 4669 #else 4670 key_words[0] = ip_addr_v4; 4671 #endif 4672 } else { 4673 #if 0 4674 uint32 *keyp; 4675 #endif 4676 4677 vrf_id = soc_EXT_IPV6_128_TCAMm_field32_get(unit, key, VRF_IDf); 4678 (void) soc_EXT_IPV6_128_TCAMm_field_get(unit, key, IP_ADDRf, field); 4679 #if 0 4680 key_words[0] = MAKE_WORD(keyp[14], keyp[15], keyp[16], keyp[17]); 4681 key_words[1] = MAKE_WORD(keyp[10], keyp[11], keyp[12], keyp[13]); 4682 key_words[2] = MAKE_WORD(keyp[6], keyp[7], keyp[8], keyp[9]); 4683 key_words[3] = MAKE_WORD(keyp[2], keyp[3], keyp[4], keyp[5]); 4684 key_words[4] = MAKE_WORD(0, 0, keyp[0], keyp[1]); 4685 #else 4686 key_words[0] = field[0]; 4687 key_words[4] = field[1]; 4688 key_words[2] = field[2]; 4689 key_words[1] = field[3]; 4690 key_words[3] = MAKE_WORD(0, 0, vrf_id >> 8, vrf_id & 0xff); 4691 4692 #endif 4693 } 4694 4695 /* call underlying search function */ 4696 rv = soc_tr3_tcam_search_entry(unit, part, 0, key_words, index_ptr, &tmp); 4697 if (rv < 0) { 4698 LOG_CLI((BSL_META_U(unit, 4699 "Internal search request failed\n"))); 4700 return rv; 4701 } 4702 tmp = *index_ptr; 4703 if (!(tmp & MAKE_FIELD(TR3_WRCMP_RSP_SMF, 1))) { 4704 LOG_VERBOSE(BSL_LS_SOC_COMMON, 4705 (BSL_META_U(unit, 4706 "Lookup failed\n"))); 4707 return SOC_E_NOT_FOUND; 4708 } 4709 /* get the result index */ 4710 tmp = MAKE_FIELD(TR3_WRCMP_RSP_RESULT, tmp); 4711 4712 /* check which host table the index falls in */ 4713 /* tmp -= partitions[TCAM_PARTITION_FWD_IP4_UCAST].tcam_base; */ 4714 for (part = TCAM_PARTITION_FWD_IP4_UCAST; 4715 part <= TCAM_PARTITION_FWD_IP6_128_UCAST_WIDE; part++) { 4716 if (tmp < (partitions[part].tcam_base+(partitions[part].num_entries << 4717 partitions[part].tcam_width_shift))) { 4718 *index_ptr = (tmp - partitions[part].tcam_base) 4719 >> partitions[part].tcam_width_shift; 4720 *mem = part_to_mem[part - TCAM_PARTITION_FWD_IP4_UCAST]; 4721 if (*mem != 0) { 4722 return SOC_E_NONE; 4723 } else { 4724 return SOC_E_NOT_FOUND; 4725 } 4726 } 4727 /* 4728 tmp -= (partitions[part].num_entries << 4729 partitions[part].tcam_width_shift); 4730 */ 4731 } 4732 LOG_CLI((BSL_META_U(unit, 4733 "Exiting with miss\n"))); 4734 return SOC_E_NOT_FOUND; 4735 } 4736 4737 4738 /* 4739 * Function: 4740 * soc_tr3_tcam_partition_get 4741 * Purpose: 4742 * Maps EXT_* mem to TCAM parition number 4743 * Parameters: 4744 * mem (IN) Memory name in EXT_* view. 4745 * partition (OUT) Partition number corresponding to the EXT mem 4746 * Returns: 4747 * SOC_E_PARAM Invalid memory 4748 * SOC_E_NONE Success 4749 */ 4750 STATIC int 4751 soc_tr3_tcam_partition_get(int unit, soc_mem_t mem, int *partition) 4752 { 4753 int part; 4754 4755 if (partition == NULL) { 4756 return SOC_E_PARAM; 4757 } 4758 4759 switch (mem) { 4760 case EXT_IPV4_UCASTm: 4761 part = TCAM_PARTITION_FWD_IP4_UCAST; 4762 break; 4763 case EXT_IPV4_UCAST_WIDEm: 4764 part = TCAM_PARTITION_FWD_IP4_UCAST_WIDE; 4765 break; 4766 case EXT_IPV4_DEFIPm: 4767 part = TCAM_PARTITION_FWD_IP4; 4768 break; 4769 case EXT_IPV6_64_DEFIPm: 4770 part = TCAM_PARTITION_FWD_IP6U; 4771 break; 4772 case EXT_IPV6_128_UCASTm: 4773 part = TCAM_PARTITION_FWD_IP6_128_UCAST; 4774 break; 4775 case EXT_IPV6_128_UCAST_WIDEm: 4776 part = TCAM_PARTITION_FWD_IP6_128_UCAST_WIDE; 4777 break; 4778 case EXT_IPV6_128_DEFIPm: 4779 part = TCAM_PARTITION_FWD_IP6; 4780 break; 4781 case EXT_ACL144_TCAM_L2m: 4782 part = TCAM_PARTITION_ACL_L2C; 4783 break; 4784 case EXT_ACL144_TCAM_IPV4m: 4785 part = TCAM_PARTITION_ACL_IP4C; 4786 break; 4787 case EXT_ACL144_TCAM_IPV6m: 4788 part = TCAM_PARTITION_ACL_IP6C; 4789 break; 4790 case EXT_ACL288_TCAM_L2m: 4791 part = TCAM_PARTITION_ACL_L2; 4792 break; 4793 case EXT_ACL288_TCAM_IPV4m: 4794 part = TCAM_PARTITION_ACL_IP4; 4795 break; 4796 case EXT_ACL432_TCAM_DATA_L2_IPV4m: 4797 part = TCAM_PARTITION_ACL_L2IP4; 4798 break; 4799 case EXT_ACL360_TCAM_DATA_IPV6_SHORTm: 4800 part = TCAM_PARTITION_ACL_IP6S; 4801 break; 4802 case EXT_ACL432_TCAM_DATA_IPV6_LONGm: 4803 part = TCAM_PARTITION_ACL_IP6F; 4804 break; 4805 case EXT_ACL432_TCAM_DATA_L2_IPV6m: 4806 part = TCAM_PARTITION_ACL_L2IP6; 4807 break; 4808 default: 4809 return (SOC_E_PARAM); 4810 } 4811 4812 *partition = part; 4813 4814 return (SOC_E_NONE); 4815 } 4816 4817 /* 4818 * Function: 4819 * soc_tr3_get_vbit 4820 * Purpose: 4821 * Gets valid status for a given memory index 4822 * Parameters: 4823 * mem (IN) Memory name in EXT_* view. 4824 * index (IN) Location of the entry in the memory 4825 * partition (OUT) Partition number corresponding to the EXT mem 4826 * Returns: 4827 * SOC_E_PARAM Invalid memory. 4828 * SOC_E_XXX Internal Error in accessing the tcam 4829 * SOC_E_NONE Success. 4830 */ 4831 int 4832 soc_tr3_get_vbit(int unit, soc_mem_t mem, int index, int *valid) 4833 { 4834 soc_tcam_info_t *tcam_info; 4835 uint32 dbus[2 * TCAM_TR_WORDS_PER_ENTRY]; 4836 int ibus[2]; 4837 int addr, len, i, tmp, part, rv; 4838 4839 tcam_info = SOC_CONTROL(unit)->tcam_info; 4840 if (tcam_info == NULL) { 4841 return SOC_E_NONE; 4842 } 4843 4844 SOC_IF_ERROR_RETURN(soc_tr3_tcam_partition_get(unit, mem, &part)); 4845 4846 4847 4848 /* Read from TCAM */ 4849 4850 if (part >= TCAM_PARTITION_COUNT || 4851 index >= tcam_info->partitions[part].num_entries) { 4852 return SOC_E_PARAM; 4853 } 4854 4855 addr = (index << tcam_info->partitions[part].tcam_width_shift) + 4856 tcam_info->partitions[part].tcam_base; 4857 4858 len = 1 << tcam_info->partitions[part].tcam_width_shift; 4859 4860 /* we only do a max of 480 bits */ 4861 if (len == 8) { 4862 len = 6; 4863 } 4864 4865 *valid = 1; 4866 for (i = 0; i < len; i++) { 4867 sal_memset(dbus, 0, sizeof(dbus)); 4868 4869 /* normalize address for cascaded mode */ 4870 tmp = (((addr+i) / (128 * 4096)) << 23) | ((addr+i) % (128 * 4096)); 4871 4872 /* set bit 25 of addr to 1 to indicate database read */ 4873 dbus[1] = MAKE_WORD(GET_BYTE(tmp, 0), GET_BYTE(tmp, 1), 4874 GET_BYTE(tmp, 2), 4875 (GET_BYTE(tmp, 3) & 0x3) | 0x2); 4876 4877 ibus[0] = TR3_OPCODE_RD_REG_DBX; 4878 4879 rv = soc_triumph3_tcam_access(unit, TCAM_TR3_OP_REG_DB_X_READ, 4880 1, 0, 0, (uint32 *)dbus, ibus, 2*64, 1); 4881 if (rv < 0) { 4882 *valid = 0; 4883 return rv; 4884 } 4885 4886 *valid &= ((dbus[3] >> 12) & 1); 4887 } 4888 4889 return SOC_E_NONE; 4890 } 4891 4892 4893 /* 4894 * Set/Clear the vbit of an external tcam entry 4895 */ 4896 int 4897 soc_tr3_set_vbit(int unit, soc_mem_t mem, int index, int val) 4898 { 4899 soc_tcam_info_t *tcam_info; 4900 soc_tcam_partition_t *partitions; 4901 int part, rv = 0, duplicate = 0; 4902 int physical_index; 4903 uint32 vbit_data, shift_count; 4904 ext_tcam_vbit_entry_t vbits; 4905 4906 4907 tcam_info = SOC_CONTROL(unit)->tcam_info; 4908 if (tcam_info == NULL) { 4909 return SOC_E_NONE; 4910 } 4911 partitions = tcam_info->partitions; 4912 4913 switch (mem) { 4914 case EXT_IPV4_UCASTm: 4915 part = TCAM_PARTITION_FWD_IP4_UCAST; 4916 shift_count = 0; 4917 if (partitions[TCAM_PARTITION_FWD_IP4_DUP].num_entries) { 4918 duplicate=1; 4919 } 4920 break; 4921 case EXT_IPV4_UCAST_WIDEm: 4922 part = TCAM_PARTITION_FWD_IP4_UCAST_WIDE; 4923 shift_count = 0; 4924 if (partitions[TCAM_PARTITION_FWD_IP4_DUP].num_entries) { 4925 duplicate=1; 4926 } 4927 break; 4928 case EXT_IPV4_DEFIPm: 4929 part = TCAM_PARTITION_FWD_IP4; 4930 shift_count = 0; 4931 if (partitions[TCAM_PARTITION_FWD_IP4_DUP].num_entries) { 4932 duplicate=1; 4933 } 4934 break; 4935 case EXT_IPV6_64_DEFIPm: 4936 part = TCAM_PARTITION_FWD_IP6U; 4937 shift_count = 0; 4938 if (partitions[TCAM_PARTITION_FWD_IP6U_DUP].num_entries) { 4939 duplicate=1; 4940 } 4941 break; 4942 case EXT_IPV6_128_UCASTm: 4943 part = TCAM_PARTITION_FWD_IP6_128_UCAST; 4944 shift_count = 1; 4945 if (partitions[TCAM_PARTITION_FWD_IP6_DUP].num_entries) { 4946 duplicate=1; 4947 } 4948 break; 4949 case EXT_IPV6_128_UCAST_WIDEm: 4950 part = TCAM_PARTITION_FWD_IP6_128_UCAST_WIDE; 4951 shift_count = 1; 4952 if (partitions[TCAM_PARTITION_FWD_IP6_DUP].num_entries) { 4953 duplicate=1; 4954 } 4955 break; 4956 case EXT_IPV6_128_DEFIPm: 4957 part = TCAM_PARTITION_FWD_IP6; 4958 shift_count = 1; 4959 if (partitions[TCAM_PARTITION_FWD_IP6_DUP].num_entries) { 4960 duplicate=1; 4961 } 4962 break; 4963 case EXT_ACL144_TCAM_L2m: 4964 part = TCAM_PARTITION_ACL_L2C; 4965 shift_count = 1; 4966 break; 4967 case EXT_ACL144_TCAM_IPV4m: 4968 part = TCAM_PARTITION_ACL_IP4C; 4969 shift_count = 1; 4970 break; 4971 case EXT_ACL144_TCAM_IPV6m: 4972 part = TCAM_PARTITION_ACL_IP6C; 4973 shift_count = 1; 4974 break; 4975 case EXT_ACL288_TCAM_L2m: 4976 part = TCAM_PARTITION_ACL_L2; 4977 shift_count = 3; 4978 break; 4979 case EXT_ACL288_TCAM_IPV4m: 4980 part = TCAM_PARTITION_ACL_IP4; 4981 shift_count = 3; 4982 break; 4983 case EXT_ACL432_TCAM_DATA_L2_IPV4m: 4984 part = TCAM_PARTITION_ACL_L2IP4; 4985 shift_count = 3; 4986 break; 4987 case EXT_ACL360_TCAM_DATA_IPV6_SHORTm: 4988 part = TCAM_PARTITION_ACL_IP6S; 4989 shift_count = 5; 4990 break; 4991 case EXT_ACL432_TCAM_DATA_IPV6_LONGm: 4992 part = TCAM_PARTITION_ACL_IP6F; 4993 shift_count = 5; 4994 break; 4995 case EXT_ACL432_TCAM_DATA_L2_IPV6m: 4996 part = TCAM_PARTITION_ACL_L2IP6; 4997 shift_count = 5; 4998 break; 4999 default: 5000 return SOC_E_PARAM; 5001 } 5002 5003 physical_index = partitions[part].tcam_base + 5004 (index << partitions[part].tcam_width_shift); 5005 5006 sal_memset(&vbits, 0, sizeof(vbits)); 5007 5008 /* need to set correct bit in the returned data and return */ 5009 if (val & 1) { 5010 /* set higher bit of entry to avoid unintended consequences */ 5011 5012 vbit_data = (1 << ((physical_index % 32) + 5013 partitions[part].tcam_width_shift)); 5014 } else { 5015 vbit_data = ~(1 | (1 << shift_count)); 5016 } 5017 soc_mem_field32_set(unit, EXT_TCAM_VBITm, (uint32 *) &vbits, VBITf, 5018 vbit_data); 5019 if (duplicate) { 5020 soc_mem_field32_set(unit, EXT_TCAM_VBITm, (uint32 *) &vbits, DUPLICATEf, 5021 duplicate); 5022 } 5023 5024 /* write back modified data */ 5025 rv = soc_mem_write(unit, EXT_TCAM_VBITm, MEM_BLOCK_ALL, physical_index, 5026 (void *)&vbits); 5027 if (rv < 0) return rv; 5028 return SOC_E_NONE; 5029 } 5030 5031 #ifdef later 5032 int 5033 soc_tr3_configure_rpf(int unit, bool enable) 5034 { 5035 /* currently a global setting */ 5036 if (enable) { 5037 /* move all ports to urpf profile */ 5038 } else { 5039 /* move all ports to base profile */ 5040 } 5041 return SOC_E_NONE; 5042 } 5043 #endif 5044 5045 #if 0 5046 5047 /* 5048 NL11K external TCAM init sequences 5049 */ 5050 int soc_tr3_nl11k_init(int unit) { 5051 5052 #define MAX_WCL_NUM 5 5053 #define MASTER_WCL_ID 2 5054 #define TX_PLL_LOCK_WAIT_TIME_USECS 60000000 5055 #define NL_METAFRAME_LENGTH 2048 5056 #define NL11K_MDIO_ADDRESS 0x101 5057 #define NL11K_DEVICE_CNT 2 5058 #define RX_FIFO_THRESHOLD 0x181F 5059 #define TX_FIFO_THRESHOLD 0x181F 5060 5061 5062 5063 #define NL11K_COMMON_CONFIG_STATUS_BLK 1 5064 5065 #define RX_LANE_ENABLE_0_REG 0x8100 5066 #define RX_LANE_ENABLE_1_REG 0x8101 5067 #define TX_LANE_ENABLE_0_REG 0x8102 5068 #define CRX_LANE_ENABLE_0_REG 0x8103 5069 #define CTX_LANE_ENABLE_0_REG 0x8104 5070 #define CTX_LANE_ENABLE_1_REG 0x8105 5071 #define RX_METAFRAME_LEN_REG 0x8106 5072 #define TX_METAFRAME_LEN_REG 0x8107 5073 #define LANE_SWAP_REG 0x8108 5074 #define RX_FIFO_THRESHOLD_REG 0x8109 5075 #define TX_FIFO_THRESHOLD_REG 0x810A 5076 #define TX_BURST_SHORT_REG 0x810B 5077 #define GLOBAL_RX_TX_ENABLE_REG 0x810C 5078 #define GLOBAL_SW_RESET_REG 0x811C 5079 #define TX_SERDES_SQUELCH_11_00_REG 0x8117 5080 #define CTX_SERDES_SQUELCH_15_00_REG 0x8118 5081 #define CTX_SERDES_SQUELCH_23_16_REG 0x8119 5082 #define SERDES_SW_RESET_REG 0x811B 5083 #define SPEED_MODE_SELECT_REG 0x811D 5084 #define GEN_PURPOSE_STATUS_REG_2 0x8183 5085 5086 uint32 etu_cfg4 = 0, temp32 = 0; 5087 uint16 temp16=0; 5088 soc_timeout_t to; 5089 sal_usecs_t timeout_usecs = TX_PLL_LOCK_WAIT_TIME_USECS; 5090 int rv; 5091 /* int cond;*/ 5092 int index=0, temp1 = 0, temp2 = 0, temp3 = 0, cond; 5093 5094 5095 5096 5097 5098 5099 5100 /* 5101 *-------------------------------------------------- 5102 * Reset: 5103 * ext_tcam, 5104 * wcl, 5105 * ilamac 5106 *-------------------------------------------------- 5107 */ 5108 5109 /* Reset tcam, first de-assert it(high) and then assert(pull low) 5110 */ 5111 SOC_IF_ERROR_RETURN(READ_ETU_CONFIG4r(unit, &etu_cfg4)); 5112 soc_reg_field_set(unit, ETU_CONFIG4r, &etu_cfg4, EXT_TCAM_SRST_Lf, 1); 5113 soc_reg_field_set(unit, ETU_CONFIG4r, &etu_cfg4, EXT_TCAM_CRST_Lf, 1); 5114 SOC_IF_ERROR_RETURN(WRITE_ETU_CONFIG4r(unit, etu_cfg4)); 5115 soc_reg_field_set(unit, ETU_CONFIG4r, &etu_cfg4, EXT_TCAM_SRST_Lf, 0); 5116 soc_reg_field_set(unit, ETU_CONFIG4r, &etu_cfg4, EXT_TCAM_CRST_Lf, 0); 5117 SOC_IF_ERROR_RETURN(WRITE_ETU_CONFIG4r(unit, etu_cfg4)); 5118 5119 /* Reset all wcl */ 5120 for(index=0; index <= MAX_WCL_NUM; ++index) { 5121 SOC_IF_ERROR_RETURN(READ_WCL_CTLr(unit, index, &temp32)); 5122 5123 soc_reg_field_set(unit, WCL_CTLr, &temp32, PWRDWNf, 1); 5124 soc_reg_field_set(unit, WCL_CTLr, &temp32, IDDQf, 1); 5125 soc_reg_field_set(unit, WCL_CTLr, &temp32, RSTB_HWf, 0); 5126 soc_reg_field_set(unit, WCL_CTLr, &temp32, RSTB_MDIOREGSf, 0); 5127 soc_reg_field_set(unit, WCL_CTLr, &temp32, RSTB_PLLf, 0); 5128 soc_reg_field_set(unit, WCL_CTLr, &temp32, TXD1G_FIFO_RSTBf, 0); 5129 soc_reg_field_set(unit, WCL_CTLr, &temp32, PLL_BYPASSf, 0); 5130 soc_reg_field_set(unit, WCL_CTLr, &temp32, LCREF_ENf, 0); 5131 soc_reg_field_set(unit, WCL_CTLr, &temp32, REFOUT_ENf, 0); 5132 5133 SOC_IF_ERROR_RETURN(WRITE_WCL_CTLr(unit, index, temp32)); 5134 } 5135 5136 /* Reset ILAMAC 5137 */ 5138 SOC_IF_ERROR_RETURN(READ_ETU_CONFIG4r(unit, &etu_cfg4)); 5139 soc_reg_field_set(unit, ETU_CONFIG4r, &etu_cfg4, ILAMAC_RX_SERDES_RST_f, 0); 5140 soc_reg_field_set(unit, ETU_CONFIG4r, &etu_cfg4, ILAMAC_RX_LBUS_RST_f, 0); 5141 soc_reg_field_set(unit, ETU_CONFIG4r, &etu_cfg4, ILAMAC_TX_SERDES_RST_f, 0); 5142 soc_reg_field_set(unit, ETU_CONFIG4r, &etu_cfg4, ILAMAC_TX_LBUS_RST_f, 0); 5143 SOC_IF_ERROR_RETURN(WRITE_ETU_CONFIG4r(unit, etu_cfg4)); 5144 5145 /* tx_serdes_refclk mux select. select one txck from 24 lanes. Default = 0x9 */ 5146 soc_reg_field_set(unit, ETU_CONFIG4r, &etu_cfg4, ILAMAC_TX_SERDES_REFCLK_SELf, 0x9); 5147 SOC_IF_ERROR_RETURN(WRITE_ETU_CONFIG4r(unit, etu_cfg4)); 5148 5149 5150 5151 /* 5152 *-------------------------------------------------- 5153 * WCL Init Sequence 5154 *-------------------------------------------------- 5155 */ 5156 5157 5158 /* 5159 wcl_ctl_pwrdwn from etu controls both pwrdwn_tx and pwrdwn_rx, 5160 so if we want to turn-off rx only, then we will have to do it thro mdio 5161 */ 5162 for(index=0; index <= MAX_WCL_NUM; ++index) { 5163 SOC_IF_ERROR_RETURN(READ_WCL_CTLr(unit, index, &temp32)); 5164 soc_reg_field_set(unit, WCL_CTLr, &temp32, PWRDWNf, 0); 5165 SOC_IF_ERROR_RETURN(WRITE_WCL_CTLr(unit, index, temp32)); 5166 } 5167 5168 /* wcl - master, slave clock assignment 5169 */ 5170 temp32 = 0; 5171 for(index=0; index <= MAX_WCL_NUM; ++index) { 5172 SOC_IF_ERROR_RETURN(READ_WCL_CTLr(unit, index, &temp32)); 5173 5174 temp1 = (index == MASTER_WCL_ID)? 0 : 1; /* lcref_en */ 5175 temp2 = (index == MASTER_WCL_ID)? 1 : 0; /* refout_en */ 5176 5177 soc_reg_field_set(unit, WCL_CTLr, &temp32, LCREF_ENf, temp1); 5178 soc_reg_field_set(unit, WCL_CTLr, &temp32, REFOUT_ENf, temp2); 5179 SOC_IF_ERROR_RETURN(WRITE_WCL_CTLr(unit, index, temp32)); 5180 } 5181 5182 /* Sleep 1ms */ 5183 sal_usleep(1000); 5184 5185 5186 /* wcl - Deassert pwrdwn and iddq */ 5187 temp32 = 0; 5188 for(index=0; index <= MAX_WCL_NUM; ++index) { 5189 SOC_IF_ERROR_RETURN(READ_WCL_CTLr(unit, index, &temp32)); 5190 soc_reg_field_set(unit, WCL_CTLr, &temp32, PWRDWNf, 0); 5191 soc_reg_field_set(unit, WCL_CTLr, &temp32, IDDQf, 0); 5192 SOC_IF_ERROR_RETURN(WRITE_WCL_CTLr(unit, index, temp32)); 5193 } 5194 /* wcl - Deassert RSTB_HW */ 5195 temp32 = 0; 5196 for(index=0; index <= MAX_WCL_NUM; ++index) { 5197 SOC_IF_ERROR_RETURN(READ_WCL_CTLr(unit, index, &temp32)); 5198 soc_reg_field_set(unit, WCL_CTLr, &temp32, RSTB_HWf, 1); 5199 SOC_IF_ERROR_RETURN(WRITE_WCL_CTLr(unit, index, temp32)); 5200 } 5201 /* wcl - Deassert MDIOREGS */ 5202 temp32 = 0; 5203 for(index=0; index <= MAX_WCL_NUM; ++index) { 5204 SOC_IF_ERROR_RETURN(READ_WCL_CTLr(unit, index, &temp32)); 5205 soc_reg_field_set(unit, WCL_CTLr, &temp32, RSTB_MDIOREGSf, 1); 5206 SOC_IF_ERROR_RETURN(WRITE_WCL_CTLr(unit, index, temp32)); 5207 } 5208 5209 /* 5210 *-------------------------------------------------- 5211 * ESM SERDES INIT - wcmod driver??? - ESM serdes init - pll... 5212 to run the tests if mdio access is working 5213 *-------------------------------------------------- 5214 */ 5215 wcmod_esm_serdes_init(unit); 5216 5217 /* wcl - Deassert RSTB_PLL */ 5218 temp32 = 0; 5219 for(index=0; index <= MAX_WCL_NUM; ++index) { 5220 SOC_IF_ERROR_RETURN(READ_WCL_CTLr(unit, index, &temp32)); 5221 soc_reg_field_set(unit, WCL_CTLr, &temp32, RSTB_PLLf, 1); 5222 SOC_IF_ERROR_RETURN(WRITE_WCL_CTLr(unit, index, temp32)); 5223 } 5224 5225 /* Tx PLL Lock */ 5226 temp32 = 0; 5227 soc_timeout_init(&to, timeout_usecs, 0); 5228 do { 5229 SOC_IF_ERROR_RETURN(READ_WCL_CUR_STSr(unit, &temp32)); 5230 cond = temp32 & 0x3f000; 5231 if (cond || SOC_FAILURE(rv)) { 5232 break; 5233 } 5234 } while (!soc_timeout_check(&to)); 5235 /* Check again */ 5236 temp32 = 0; 5237 SOC_IF_ERROR_RETURN(READ_WCL_CUR_STSr(unit, &temp32)); 5238 if((temp32 & 0x3f000) || SOC_FAILURE(rv)){ 5239 return SOC_E_INIT; /* PLL not locked, error */ 5240 } 5241 5242 /* 5243 *-------------------------------------------------- 5244 * Configure ILAMAC 5245 *-------------------------------------------------- 5246 */ 5247 SOC_IF_ERROR_RETURN(READ_ILAMAC_RX_CONFIGr(unit, &temp32)); 5248 5249 soc_reg_field_set(unit, ILAMAC_TX_CONFIG0r, &temp32, BIT_ORDER_INVERTf, 1); 5250 soc_reg_field_set(unit, ILAMAC_TX_CONFIG0r, &temp32, TX_XOFF_MODEf, 0); 5251 soc_reg_field_set(unit, ILAMAC_TX_CONFIG0r, &temp32, TX_RLIM_ENABLEf, 0); 5252 soc_reg_field_set(unit, ILAMAC_TX_CONFIG0r, &temp32, TX_RDYOUT_THRESHf, 0); 5253 soc_reg_field_set(unit, ILAMAC_TX_CONFIG0r, &temp32, TX_DISABLE_SKIPWORDf, 0); 5254 soc_reg_field_set(unit, ILAMAC_TX_CONFIG0r, &temp32, TX_BURSTSHORTf, 1); 5255 soc_reg_field_set(unit, ILAMAC_TX_CONFIG0r, &temp32, TX_BURSTMAXf, 1); 5256 soc_reg_field_set(unit, ILAMAC_TX_CONFIG0r, &temp32, TX_MFRAMELEN_MINUS1f, NL_METAFRAME_LENGTH - 1); 5257 soc_reg_field_set(unit, ILAMAC_TX_CONFIG0r, &temp32, TX_ENABLEf, 1); 5258 soc_reg_field_set(unit, ILAMAC_TX_CONFIG0r, &temp32, XON_RX_CH0f, 1); 5259 SOC_IF_ERROR_RETURN(WRITE_ILAMAC_TX_CONFIG0r(unit, temp32)); 5260 5261 soc_reg_field_set(unit, ILAMAC_RX_CONFIGr, &temp32, BIT_ORDER_INVERTf, 1); 5262 soc_reg_field_set(unit, ILAMAC_RX_CONFIGr, &temp32, RX_BURSTMAXf, 1); 5263 soc_reg_field_set(unit, ILAMAC_RX_CONFIGr, &temp32, RX_MFRAMELEN_MINUS1f, NL_METAFRAME_LENGTH - 1); 5264 SOC_IF_ERROR_RETURN(WRITE_ILAMAC_RX_CONFIGr(unit, temp32)); 5265 5266 /* 5267 Now that tx_serdes_clk is stable, we can bring tx_ilamac out of reset 5268 by first de-asserting lbus_rst, and then serdes_rst 5269 */ 5270 SOC_IF_ERROR_RETURN(READ_ETU_CONFIG4r(unit, &temp32)); 5271 5272 soc_reg_field_set(unit, ETU_CONFIG4r, &temp32, ILAMAC_TX_LBUS_RST_f, 1); 5273 SOC_IF_ERROR_RETURN(WRITE_ETU_CONFIG4r(unit, temp32)); 5274 5275 soc_reg_field_set(unit, ETU_CONFIG4r, &temp32, ILAMAC_TX_SERDES_RST_f, 1); 5276 SOC_IF_ERROR_RETURN(WRITE_ETU_CONFIG4r(unit, temp32)); 5277 5278 /* Now connect ilamac_tx to serdes */ 5279 soc_reg_field_set(unit, ETU_BIST_CTLr, &temp32, ENABLEf, 0); 5280 SOC_IF_ERROR_RETURN(WRITE_ETU_CONFIG4r(unit, temp32)); 5281 5282 5283 5284 5285 5286 /* 5287 * At this point, we should be sending out idle control words 5288 * to NL (which is still in reset) 5289 * We can de-assert SRST_L for NL only after we are sending 5290 * idle control words 5291 */ 5292 5293 /* 5294 *-------------------------------------------------- 5295 * NL11K init, section 6.6 NL datasheet 5296 *-------------------------------------------------- 5297 */ 5298 5299 /* 5300 1. Ensure NL's SRST, CRST are de-asserted (pulled high) 5301 and then assert SRST, CRST.....skip this step as resets for 5302 NL11K are already asserted at this point. 5303 */ 5304 5305 #if 0 5306 /* Reset tcam, first de-assert it(high) and then assert(pull low) */ 5307 soc_reg_field_set(unit, ETU_CONFIG4r, &etu_cfg4, EXT_TCAM_SRST_Lf, 1); 5308 soc_reg_field_set(unit, ETU_CONFIG4r, &etu_cfg4, EXT_TCAM_CRST_Lf, 1); 5309 SOC_IF_ERROR_RETURN(WRITE_ETU_CONFIG4r(unit, etu_cfg4)); 5310 etu_cfg4=0; 5311 soc_reg_field_set(unit, ETU_CONFIG4r, &etu_cfg4, EXT_TCAM_SRST_Lf, 0); 5312 soc_reg_field_set(unit, ETU_CONFIG4r, &etu_cfg4, EXT_TCAM_CRST_Lf, 0); 5313 SOC_IF_ERROR_RETURN(WRITE_ETU_CONFIG4r(unit, etu_cfg4)); 5314 5315 #endif 5316 5317 /* 2. Wait for 3.0usec and de-assert SRST_L */ 5318 sal_usleep(3); 5319 soc_reg_field_set(unit, ETU_CONFIG4r, &temp32, EXT_TCAM_SRST_Lf, 1); 5320 SOC_IF_ERROR_RETURN(WRITE_ETU_CONFIG4r(unit, temp32)); 5321 5322 /* 3. MDIO based device configuration */ 5323 5324 /* 5325 * Squelch the Transmit SerDes 5326 */ 5327 for (index = 0; index < NL11K_DEVICE_CNT; ++index) { 5328 soc_esw_miimc45_write(unit, NL11K_MDIO_ADDRESS + index, 5329 TX_SERDES_SQUELCH_11_00_REG, 5330 0xfff); 5331 soc_esw_miimc45_write(unit, NL11K_MDIO_ADDRESS + index, 5332 CTX_SERDES_SQUELCH_15_00_REG, 5333 0xffff); 5334 soc_esw_miimc45_write(unit, NL11K_MDIO_ADDRESS + index, 5335 CTX_SERDES_SQUELCH_23_16_REG, 5336 0xff); 5337 } 5338 5339 5340 /* 5341 * Disable RX and TX PCS using Global RX / TX Enable register 5342 */ 5343 for (index = 0; index < NL11K_DEVICE_CNT; ++index) { 5344 soc_esw_miimc45_write(unit, NL11K_MDIO_ADDRESS + index, 5345 GLOBAL_RX_TX_ENABLE_REG, 5346 0x00); 5347 } 5348 5349 /* 5350 * Reset SerDes-Initialization state machine, Core PLL and 5351 * Core Logic by writing 16'h7 to Global SW Reset register 5352 */ 5353 for (index = 0; index < NL11K_DEVICE_CNT; ++index) { 5354 soc_esw_miimc45_write(unit, NL11K_MDIO_ADDRESS + index, 5355 GLOBAL_SW_RESET_REG, 5356 0x07); 5357 } 5358 5359 /* 5360 * Configure MDIO registers 5361 */ 5362 for (index = 0; index < NL11K_DEVICE_CNT; ++index) { 5363 soc_esw_miimc45_write(unit, NL11K_MDIO_ADDRESS + index, 5364 GLOBAL_SW_RESET_REG, 5365 0x07); 5366 } 5367 5368 for (index = 0; index < NL11K_DEVICE_CNT; ++index) { 5369 #if 0 5370 soc_esw_miimc45_write(unit, NL11K_MDIO_ADDRESS + index, 5371 NL11K_COMMON_CONFIG_STATUS_BLK, 5372 LANE_SWAP_REG, 5373 NL_METAFRAME_LENGTH); 5374 #endif 5375 soc_esw_miimc45_write(unit, NL11K_MDIO_ADDRESS + index, 5376 RX_METAFRAME_LEN_REG, 5377 NL_METAFRAME_LENGTH); 5378 soc_esw_miimc45_write(unit, NL11K_MDIO_ADDRESS + index, 5379 TX_METAFRAME_LEN_REG, 5380 NL_METAFRAME_LENGTH); 5381 soc_esw_miimc45_write(unit, NL11K_MDIO_ADDRESS + index, 5382 RX_FIFO_THRESHOLD_REG, 5383 RX_FIFO_THRESHOLD); 5384 soc_esw_miimc45_write(unit, NL11K_MDIO_ADDRESS + index, 5385 TX_FIFO_THRESHOLD_REG, 5386 TX_FIFO_THRESHOLD); 5387 #if 0 5388 /* TX Burst Short (0 means 8 bytes, 1 means 16 bytes) */ 5389 soc_esw_miimc45_write(unit, NL11K_MDIO_ADDRESS + index, 5390 NL11K_COMMON_CONFIG_STATUS_BLK, 5391 TX_BURST_SHORT_REG, 5392 0x1); 5393 /* Speed mode select, bits 2:0 select speed for rx serdes, 5394 bits 6:4 select speed for tx serdes 5395 3'b100 means 6.250 Gbps, 3'b000 means 3.125 Gbps 5396 */ 5397 soc_esw_miimc45_write(unit, NL11K_MDIO_ADDRESS + index, 5398 NL11K_COMMON_CONFIG_STATUS_BLK, 5399 SPEED_MODE_SELECT_REG, 5400 0x00); 5401 #endif 5402 } 5403 5404 #if 0 5405 for (index = 0; index < NL11K_DEVICE_CNT; ++index) { 5406 /* RX Lane Enable 0 (RX lane enable for lanes 15 to 0) */ 5407 soc_esw_miimc45_write(unit, NL11K_MDIO_ADDRESS + index, 5408 NL11K_COMMON_CONFIG_STATUS_BLK, 5409 RX_LANE_ENABLE_0_REG, 5410 0xffff); 5411 /* RX Lane Enable 1 (RX lane enable for lanes 23 to 16) */ 5412 soc_esw_miimc45_write(unit, NL11K_MDIO_ADDRESS + index, 5413 NL11K_COMMON_CONFIG_STATUS_BLK, 5414 RX_LANE_ENABLE_1_REG, 5415 0xff); 5416 /* TX Lane Enable 0 (TX lane enable for lanes 11 to 0) */ 5417 soc_esw_miimc45_write(unit, NL11K_MDIO_ADDRESS + index, 5418 NL11K_COMMON_CONFIG_STATUS_BLK, 5419 TX_LANE_ENABLE_0_REG, 5420 0xfff); 5421 5422 } 5423 #endif 5424 5425 /* enable CTX lanes for DEV0, DEV1, DEV2 5426 (all not_last devices) 5427 */ 5428 temp1 = 0xffff; 5429 temp2 = 0xff; 5430 for (index = 0; index < NL11K_DEVICE_CNT; ++index) { 5431 if( index +1 == NL11K_DEVICE_CNT) { 5432 /* For the last device in cascade */ 5433 temp1 = 0x0000; 5434 temp2 = 0x0000; 5435 } 5436 soc_esw_miimc45_write(unit, NL11K_MDIO_ADDRESS + index, 5437 CTX_LANE_ENABLE_0_REG, 5438 temp1); 5439 soc_esw_miimc45_write(unit, NL11K_MDIO_ADDRESS + index, 5440 CTX_LANE_ENABLE_1_REG, 5441 temp2); 5442 5443 } 5444 5445 /* 5446 Enable CRX lanes for DEV1, DEV2, DEV3 5447 (all not_first devices) 5448 */ 5449 temp1 = 0xfff; 5450 for (index = 0; index < NL11K_DEVICE_CNT; ++index) { 5451 if(index == 0) { 5452 /* For the first device in cascade */ 5453 temp1 = 0x0000; 5454 } 5455 soc_esw_miimc45_write(unit, NL11K_MDIO_ADDRESS + index, 5456 CRX_LANE_ENABLE_0_REG, 5457 temp1); 5458 } 5459 5460 /* 5461 Deassert Core PLL and Core Logic reset, and 5462 trigger the SerDes-Initialization state 5463 */ 5464 for (index = 0; index < NL11K_DEVICE_CNT; ++index) { 5465 soc_esw_miimc45_write(unit, NL11K_MDIO_ADDRESS + index, 5466 GLOBAL_SW_RESET_REG, 5467 0x0); 5468 } 5469 5470 5471 5472 /* Poll for assertion of bit[3], SerDes Reset Sequence Done, 5473 in the General Purpose Status 5474 */ 5475 for (index = 0; index < NL11K_DEVICE_CNT; ++index) { 5476 soc_timeout_init(&to, timeout_usecs, 0); 5477 do { 5478 rv = soc_esw_miimc45_read(unit, NL11K_MDIO_ADDRESS + index, 5479 GEN_PURPOSE_STATUS_REG_2, 5480 &temp16); 5481 cond = temp16 & 0x8; 5482 if (cond || SOC_FAILURE(rv)) { 5483 break; 5484 } 5485 } while (!soc_timeout_check(&to)); 5486 5487 /* Check again */ 5488 temp16 = 0; 5489 rv = soc_esw_miimc45_read(unit, NL11K_MDIO_ADDRESS + index, 5490 GEN_PURPOSE_STATUS_REG_2, 5491 &temp16); 5492 if((temp16 & 0x8) || SOC_FAILURE(rv)){ 5493 return SOC_E_FAIL; /* Serdes Reset Sequence not done */ 5494 } 5495 } 5496 5497 /* 5498 Enable RX and TX PCS using Global RX / TX Enable register 5499 */ 5500 for (index = 0; index < NL11K_DEVICE_CNT; ++index) { 5501 soc_esw_miimc45_write(unit, NL11K_MDIO_ADDRESS + index, 5502 GLOBAL_RX_TX_ENABLE_REG, 5503 0x3); 5504 5505 } 5506 5507 /* 5508 Disable squelch for the Transmit SerDes using TX_SerDes_11_0_squelch, 5509 CTX_SerDes_15_0_squelch, and CTX_SerDes_23_16_squelch registers. 5510 */ 5511 temp1 = temp2 = temp3 = 0; 5512 for (index = 0; index < NL11K_DEVICE_CNT; ++index) { 5513 if( index + 1 == NL11K_DEVICE_CNT) { 5514 /* For last device in cascade - 5515 leave squelching enabled for CTX - 5516 as these connect to nowhere 5517 */ 5518 temp1 = 0xfff; 5519 temp2 = 0xffff; 5520 temp3 = 0xff; 5521 } 5522 soc_esw_miimc45_write(unit, NL11K_MDIO_ADDRESS + index, 5523 TX_SERDES_SQUELCH_11_00_REG, 5524 temp1); 5525 soc_esw_miimc45_write(unit, NL11K_MDIO_ADDRESS + index, 5526 CTX_SERDES_SQUELCH_15_00_REG, 5527 temp2); 5528 soc_esw_miimc45_write(unit, NL11K_MDIO_ADDRESS + index, 5529 CTX_SERDES_SQUELCH_23_16_REG, 5530 temp3); 5531 } 5532 5533 5534 /* 5535 4. Wait for 2.5 mS and de-assert NL's CRST 5536 */ 5537 temp32 = 0; 5538 sal_usleep(25000); /*2.5 msec*/ 5539 soc_reg_field_set(unit, ETU_CONFIG4r, &temp32, EXT_TCAM_CRST_Lf, 1); 5540 SOC_IF_ERROR_RETURN(WRITE_ETU_CONFIG4r(unit, temp32)); 5541 5542 /* 5543 5. Interlaken Look-Aside framing and synchronization. Idle control 5544 words will be sent on the response port with XOFF until 5545 synchronization is complete. It is expected that only idle control 5546 words are sent on the RX port until XON is provided on the TX port. 5547 */ 5548 5549 /* 5550 Rx portion of wcl must now be seeing idle words sent from NL and 5551 so must be able to recover clock 5552 - check if wcl has recovered rx_clk for each lane 5553 */ 5554 temp32 = 0; 5555 soc_timeout_init(&to, timeout_usecs, 0); 5556 do { 5557 rv = READ_WCL_CUR_STSr(unit, &temp32); 5558 cond = temp32 & 0xfff; 5559 if (cond || SOC_FAILURE(rv)) { 5560 break; 5561 } 5562 } while (!soc_timeout_check(&to)); 5563 5564 /* Check again */ 5565 temp32 = 0; 5566 rv = READ_WCL_CUR_STSr(unit, &temp32); 5567 if((temp32 & 0xfff) || SOC_FAILURE(rv)){ 5568 return SOC_E_FAIL; /* RXLANE_LOCK is not seen */ 5569 } 5570 5571 /* 5572 Once rx_lane_clk (rx_serdes_clk) is stable, we can bring rx_ilamac 5573 out of reset by first de-asserting lbus_rst, and then serdes_rst 5574 */ 5575 temp32 = 0; 5576 soc_reg_field_set(unit, ETU_CONFIG4r, &temp32, ILAMAC_RX_LBUS_RST_f, 1); 5577 SOC_IF_ERROR_RETURN(WRITE_ETU_CONFIG4r(unit, temp32)); 5578 temp32 = 0; 5579 soc_reg_field_set(unit, ETU_CONFIG4r, &temp32, ILAMAC_RX_SERDES_RST_f, 0xfff); 5580 SOC_IF_ERROR_RETURN(WRITE_ETU_CONFIG4r(unit, temp32)); 5581 5582 5583 /* Wait for rx_ilamac sync */ 5584 temp32 = 0; 5585 soc_timeout_init(&to, timeout_usecs, 0); 5586 do { 5587 rv = READ_ILAMAC_RX_INTF_STATE0r(unit, &temp32); 5588 /*[27] = 1, [26]=1, [25,24]=0, [23:12] = 0xfff, [11:0] = 0xfff */ 5589 cond = temp32 & 0xCffffff; 5590 if (cond || SOC_FAILURE(rv)) { 5591 break; 5592 } 5593 } while (!soc_timeout_check(&to)); 5594 5595 /* Check again */ 5596 temp32 = 0; 5597 rv = READ_ILAMAC_RX_INTF_STATE0r(unit, &temp32); 5598 if((temp32 & 0xCffffff) || SOC_FAILURE(rv)){ 5599 return SOC_E_FAIL; /* RXLANE_LOCK is not seen */ 5600 } 5601 5602 5603 5604 5605 5606 /* 5607 6. Assert, then deassert "Reset RX Satellite Sticky Registers" bit 5608 in SerDes SW Reset register. 5609 */ 5610 for (index = 0; index < NL11K_DEVICE_CNT; ++index) { 5611 soc_esw_miimc45_write(unit, NL11K_MDIO_ADDRESS + index, 5612 SERDES_SW_RESET_REG, 5613 0x40); 5614 soc_esw_miimc45_write(unit, NL11K_MDIO_ADDRESS + index, 5615 SERDES_SW_RESET_REG, 5616 0x00); 5617 5618 } 5619 5620 5621 /* 5622 7. Device is ready for normal operation. 5623 */ 5624 5625 5626 5627 return SOC_E_NONE; 5628 } 5629 #endif 5630 5631 5632 #endif /* BCM_TRIUMPH3_SUPPORT */