esmif.c (259979B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: tcam.c 8 * Purpose: Initialize serial link to external TCAM 9 * Requires: 10 */ 11 12 #include <soc/defs.h> 13 #ifdef BCM_TRIUMPH3_SUPPORT 14 15 /* Translation of Tcl files in /projects/ntsw-sw3/home/smaskai/TR3_A0/TCL_FOR_SW */ 16 17 #include <sal/core/boot.h> 18 #include <shared/bsl.h> 19 #include <soc/triumph3.h> 20 #include <soc/drv.h> 21 #include <soc/error.h> 22 #include <soc/debug.h> 23 #include <soc/mem.h> 24 #include <soc/er_tcam.h> 25 #include <soc/l2x.h> 26 27 #define NUM_WCLS 6 28 #define ESMIF_MAX_FIFO_DEPTH 870 29 #define ESMIF_ALLOWED_FIFO_DEPTH ((9 * ESMIF_MAX_FIFO_DEPTH) / 10) 30 #define REQD_RX_BW_FOR_CPU_PERCENT 0 31 #define REQD_TX_BW_FOR_CPU_PERCENT 0 32 #define REQD_NL_CCLK_BW_FOR_CPU_PERCENT 0 33 #define ESMIF_MAX_RSP_COST2 255 34 #define ESMIF_MAX_REQ_COST1 255 35 #define ESMIF_MAX_CCLK_COST0 255 36 #define NL_DEV_ID 0xc1 37 #define NL_NUM_REQ_LANES \ 38 ((((soc_tcam_info_t *) SOC_CONTROL(unit)->tcam_info)->num_tcams == 2) ?\ 39 16 : 24) 40 #define NL_NUM_RSP_LANES 12 41 #define NL_OVERHEAD_WORDS 4 42 #define NL_LANE_SPEED_MBPS 6250 43 #define NL_BITS_PER_ENC_WORD 67 44 #define NL_OPC_NOP 0x0 45 #define NL_OPC_REG_WRITE 0x1 46 #define NL_OPC_DB_WRITE 0x1 47 #define NL_OPC_REG_READ 0x2 48 #define NL_OPC_DBX_READ 0x2 49 #define NL_OPC_DBY_READ 0x3 50 #define NL_OPC_CBW 0x100 51 52 #define SRST_L_DEASSERTION_DELAY_US 30 /* uSec */ 53 #define CRST_L_DEASSERTION_DELAY_US 3000 /* uSec */ 54 55 56 #define ESM_MAX(a, b) (a) > (b) ? (a) : (b) 57 58 59 #define NL_TCAM_ERR_THRESHOLD_COUNT (3) 60 61 int apply_low_jitter_nl_settings = FALSE; 62 63 uint8 nl_tcam_err_count[SOC_MAX_NUM_DEVICES] = {0}; 64 65 extern int soc_tr3_restore_ltr(int unit, int dev, int ltr); 66 67 STATIC unsigned 68 esmif_clk_freq_khz(int unit) 69 { 70 unsigned speed; 71 72 speed = soc_tr3_core_clock_speed(unit); 73 if (speed == 415) { 74 return (1000 * soc_tr3_core_clock_speed(unit) + 646); 75 } 76 return (1000 * soc_tr3_core_clock_speed(unit) + 100); 77 } 78 79 80 STATIC unsigned 81 nl_core_clk_freq_khz(int unit) 82 { 83 return (1000 * soc_property_get(unit, spn_EXT_TCAM_FREQ, 400)); 84 } 85 86 87 STATIC int 88 chk_esmif_init_config(int unit, unsigned exp_iesmif_latency) 89 { 90 unsigned errcnt = 0; 91 uint32 esmif_init_config_buf, latency; 92 93 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, 94 ESMIF_INIT_CONFIGr, 95 0, 96 0, 97 &esmif_init_config_buf 98 ) 99 ); 100 101 if (soc_reg_field_get(unit, 102 ESMIF_INIT_CONFIGr, 103 esmif_init_config_buf, 104 IESMIF_BYPASS_ENABLEf 105 ) 106 ) { 107 ++errcnt; /* ESMIF stage is bypassed */ 108 } 109 if (soc_reg_field_get(unit, 110 ESMIF_INIT_CONFIGr, 111 esmif_init_config_buf, 112 WR_ENABLEf) 113 == 0 114 ) { 115 ++errcnt; /* WR_ENABLE for ESM CTRL_BUS and AUX1 fifo is still 0 */ 116 } 117 118 latency = soc_reg_field_get(unit, 119 ESMIF_INIT_CONFIGr, 120 esmif_init_config_buf, 121 LATENCYf 122 ); 123 124 if (latency != exp_iesmif_latency) { 125 ++errcnt; /* Unexpected value for LATENCY */ 126 } 127 if (latency & 1) { 128 ++errcnt; /* LATENCY is odd */ 129 } 130 if (latency == 0) { 131 ++errcnt; /* LATENCY is 0 */ 132 } 133 if (latency > 1000) { 134 ++errcnt; /* LATENCY is greater than 1000 */ 135 } 136 137 _SHR_RETURN(errcnt == 0 ? SOC_E_NONE : SOC_E_FAIL); 138 } 139 140 /* Disable interrupts */ 141 142 STATIC int 143 dis_intr(int unit) 144 { 145 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, ESM_EVENT_ERR_STATUS_INTR_ENABLEr, 0, 0, 0)); 146 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, ETU_GLOBAL_INTR_ENABLEr, 0, 0, 0)); 147 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, ILAMAC_RX_INTF_INTR0_ENABLEr, 0, 0, 0)); 148 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, ILAMAC_RX_INTF_INTR1_ENABLEr, 0, 0, 0)); 149 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, ILAMAC_RX_LANE_INTR0_ENABLEr, 0, 0, 0)); 150 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, ILAMAC_RX_LANE_INTR1_ENABLEr, 0, 0, 0)); 151 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, ILAMAC_RX_LANE_INTR2_ENABLEr, 0, 0, 0)); 152 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, ILAMAC_RX_LANE_INTR3_ENABLEr, 0, 0, 0)); 153 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, ILAMAC_TX_INTR_ENABLEr, 0, 0, 0)); 154 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, WCL_INTR_ENABLEr, 0, 0, 0)); 155 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, ETU_TX_REQ_FIFO_INTR_ENABLEr, 0, 0, 0)); 156 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, ETU_TX_PIPE_CTL_FIFO_INTR_ENABLEr, 0, 0, 0)); 157 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, ETU_RX_RSP_FIFO_INTR_ENABLEr, 0, 0, 0)); 158 159 _SHR_RETURN(SOC_E_NONE); 160 } 161 162 163 STATIC int 164 etu_rst_nl_wcl_ilamac(int unit, unsigned tx_serdes_refclk_sel) 165 { 166 /* Reset TCAM */ 167 168 { 169 uint32 etu_config4_buf; 170 171 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, ETU_CONFIG4r, 0, 0, &etu_config4_buf)); 172 soc_reg_field_set(unit, ETU_CONFIG4r, &etu_config4_buf, EXT_TCAM_CRST_Lf, 1); 173 soc_reg_field_set(unit, ETU_CONFIG4r, &etu_config4_buf, EXT_TCAM_SRST_Lf, 1); 174 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, ETU_CONFIG4r, 0, 0, etu_config4_buf)); 175 soc_reg_field_set(unit, ETU_CONFIG4r, &etu_config4_buf, EXT_TCAM_CRST_Lf, 0); 176 soc_reg_field_set(unit, ETU_CONFIG4r, &etu_config4_buf, EXT_TCAM_SRST_Lf, 0); 177 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, ETU_CONFIG4r, 0, 0, etu_config4_buf)); 178 } 179 180 /* Reset all wcl */ 181 182 { 183 uint32 wcl_ctl_buf; 184 unsigned wcl_num; 185 186 for (wcl_num = 0; wcl_num < NUM_WCLS; ++wcl_num) { 187 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, WCL_CTLr, 0, wcl_num, &wcl_ctl_buf)); 188 soc_reg_field_set(unit, WCL_CTLr, &wcl_ctl_buf, PWRDWNf, 1); 189 soc_reg_field_set(unit, WCL_CTLr, &wcl_ctl_buf, IDDQf, 1); 190 soc_reg_field_set(unit, WCL_CTLr, &wcl_ctl_buf, RSTB_HWf, 0); 191 soc_reg_field_set(unit, WCL_CTLr, &wcl_ctl_buf, RSTB_MDIOREGSf, 0); 192 soc_reg_field_set(unit, WCL_CTLr, &wcl_ctl_buf, RSTB_PLLf, 0); 193 soc_reg_field_set(unit, WCL_CTLr, &wcl_ctl_buf, TXD1G_FIFO_RSTBf, 0); 194 soc_reg_field_set(unit, WCL_CTLr, &wcl_ctl_buf, PLL_BYPASSf, 0); 195 soc_reg_field_set(unit, WCL_CTLr, &wcl_ctl_buf, LCREF_ENf, 0); 196 soc_reg_field_set(unit, WCL_CTLr, &wcl_ctl_buf, REFOUT_ENf, 0); 197 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, WCL_CTLr, 0, wcl_num, wcl_ctl_buf)); 198 } 199 } 200 201 { 202 /* Reset ILAMAC */ 203 204 uint32 etu_config4_buf; 205 206 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, ETU_CONFIG4r, 0, 0, &etu_config4_buf)); 207 soc_reg_field_set(unit, ETU_CONFIG4r, &etu_config4_buf, ILAMAC_RX_SERDES_RST_f, 0); 208 soc_reg_field_set(unit, ETU_CONFIG4r, &etu_config4_buf, ILAMAC_RX_LBUS_RST_f, 0); 209 soc_reg_field_set(unit, ETU_CONFIG4r, &etu_config4_buf, ILAMAC_TX_SERDES_RST_f, 0); 210 soc_reg_field_set(unit, ETU_CONFIG4r, &etu_config4_buf, ILAMAC_TX_LBUS_RST_f, 0); 211 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, ETU_CONFIG4r, 0, 0, etu_config4_buf)); 212 213 /* Select one of the 24 txck from WCL - should not matter if things are ok */ 214 215 soc_reg_field_set(unit, ETU_CONFIG4r, &etu_config4_buf, ILAMAC_TX_SERDES_REFCLK_SELf, tx_serdes_refclk_sel); 216 } 217 218 _SHR_RETURN(SOC_E_NONE); 219 } 220 221 222 STATIC int 223 tcam_phy_init(int unit) 224 { 225 _SHR_RETURN(wcmod_esm_serdes_init(unit)); 226 } 227 228 229 STATIC int 230 wcl_mdio_init_seq(int unit) 231 { 232 _SHR_RETURN(tcam_phy_init(unit)); 233 } 234 235 236 STATIC int 237 wcl_chk_txpll_lock(int unit) 238 { 239 static const soc_field_t txpll_lock_fld[] = { 240 TXPLL_LOCK_0f, 241 TXPLL_LOCK_1f, 242 TXPLL_LOCK_2f, 243 TXPLL_LOCK_3f, 244 TXPLL_LOCK_4f, 245 TXPLL_LOCK_5f 246 }; 247 248 uint32 wcl_cur_sts_buf; 249 unsigned i; 250 251 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, WCL_CUR_STSr, 0, 0, &wcl_cur_sts_buf)); 252 for (i = 0; i < COUNTOF(txpll_lock_fld); ++i) { 253 if (soc_reg_field_get(unit, WCL_CUR_STSr, wcl_cur_sts_buf, txpll_lock_fld[i]) == 0) { 254 return (SOC_E_BUSY); 255 } 256 } 257 258 return (SOC_E_NONE); 259 } 260 261 262 STATIC int 263 wcl_poll_txpll_lock(int unit) 264 { 265 unsigned n; 266 267 for (n = 1000; n; --n) { 268 int errcode = wcl_chk_txpll_lock(unit); 269 270 if (errcode == SOC_E_BUSY) { 271 sal_usleep(1000); /* Wait 1 ms */ 272 continue; 273 } 274 275 _SHR_RETURN(errcode); 276 } 277 278 _SHR_RETURN(SOC_E_TIMEOUT); 279 } 280 281 282 STATIC int 283 wcl_reset_seq(int unit, unsigned master_wcl_num) 284 { 285 uint32 wcl_ctl_buf; 286 unsigned wcl_num; 287 288 /* Dont rely on previous state - restore default state of WCL_CTL 289 wcl - assert pwrdwn, iddq, etc. 290 Set iddq to '0' and rstb_pll to '0' (if it is not '0' to start with, this 291 is to keep pll in reset). 292 */ 293 294 for (wcl_num = 0; wcl_num < NUM_WCLS; ++wcl_num) { 295 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, WCL_CTLr, 0, wcl_num, &wcl_ctl_buf)); 296 soc_reg_field_set(unit, WCL_CTLr, &wcl_ctl_buf, PWRDWNf, 1); 297 soc_reg_field_set(unit, WCL_CTLr, &wcl_ctl_buf, IDDQf, 1); 298 soc_reg_field_set(unit, WCL_CTLr, &wcl_ctl_buf, RSTB_HWf, 0); 299 soc_reg_field_set(unit, WCL_CTLr, &wcl_ctl_buf, RSTB_MDIOREGSf, 0); 300 soc_reg_field_set(unit, WCL_CTLr, &wcl_ctl_buf, RSTB_PLLf, 0); 301 soc_reg_field_set(unit, WCL_CTLr, &wcl_ctl_buf, TXD1G_FIFO_RSTBf, 0); 302 soc_reg_field_set(unit, WCL_CTLr, &wcl_ctl_buf, PLL_BYPASSf, 0); 303 soc_reg_field_set(unit, WCL_CTLr, &wcl_ctl_buf, LCREF_ENf, 0); /* LCREF_EN=0 means PLL input clock = pad_refclk_p/n */ 304 soc_reg_field_set(unit, WCL_CTLr, &wcl_ctl_buf, REFOUT_ENf, 0); /* REFOUT_EN=0 means lcrefoutp/n = HiZ */ 305 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, WCL_CTLr, 0, wcl_num, wcl_ctl_buf)); 306 } 307 308 /* Note: By default PLL_BYPASS=0 and we will keep it this way */ 309 310 /* Note: following sequence is based on email dated 6/17/2011, from Prasun Paul */ 311 312 /* wcl - remove iddq 313 Set iddq to 0 and rstb_pll to 0 (if it is not 0 to start with, this is to keep pll in reset). */ 314 315 for (wcl_num = 0; wcl_num < NUM_WCLS; ++wcl_num) { 316 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, WCL_CTLr, 0, wcl_num, &wcl_ctl_buf)); 317 soc_reg_field_set(unit, WCL_CTLr, &wcl_ctl_buf, IDDQf, 0); 318 soc_reg_field_set(unit, WCL_CTLr, &wcl_ctl_buf, RSTB_PLLf, 0); 319 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, WCL_CTLr, 0, wcl_num, wcl_ctl_buf)); 320 } 321 322 /* wcl - remove powerdown 323 Set pwrdwn_tx[3:0]/ pwrdwn_rx[3:0] to '0' to release power down of Tx and Rx path. 324 Can be controlled thru internal MDIO register bits as well to overwrite pin info. 325 Note: wcl_ctl_pwrdwn from etu controls both pwrdwn_tx and pwrdwn_rx, 326 so if we want to turn-off rx only, then we will have to do it thro mdio 327 */ 328 329 for (wcl_num = 0; wcl_num < NUM_WCLS; ++wcl_num) { 330 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, WCL_CTLr, 0, wcl_num, &wcl_ctl_buf)); 331 soc_reg_field_set(unit, WCL_CTLr, &wcl_ctl_buf, PWRDWNf, 0); 332 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, WCL_CTLr, 0, wcl_num, wcl_ctl_buf)); 333 } 334 335 /* wcl - master, slave clock assignment 336 Set lcref_en and refout_en as desired. Do you need any explanation here? 337 By default: LCREF_EN=0, REFOUT_EN=0 for all WCLs 338 */ 339 340 for (wcl_num = 0; wcl_num < NUM_WCLS; ++wcl_num) { 341 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, WCL_CTLr, 0, wcl_num, &wcl_ctl_buf)); 342 if (wcl_num == master_wcl_num) { 343 /* Master */ 344 345 soc_reg_field_set(unit, WCL_CTLr, &wcl_ctl_buf, LCREF_ENf, 0); 346 soc_reg_field_set(unit, WCL_CTLr, &wcl_ctl_buf, REFOUT_ENf, 1); 347 } else { 348 /* Slave */ 349 350 soc_reg_field_set(unit, WCL_CTLr, &wcl_ctl_buf, LCREF_ENf, 1); 351 soc_reg_field_set(unit, WCL_CTLr, &wcl_ctl_buf, REFOUT_ENf, 0); 352 } 353 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, WCL_CTLr, 0, wcl_num, wcl_ctl_buf)); 354 } 355 356 sal_usleep(1000); /* Wait 1 ms */ 357 358 /* wcl - De-assert RSTB_HW - hardware_reset 359 Release rstb_hw and rstb_mdioregs. That means set to '1's 360 */ 361 362 for (wcl_num = 0; wcl_num < NUM_WCLS; ++wcl_num) { 363 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, WCL_CTLr, 0, wcl_num, &wcl_ctl_buf)); 364 soc_reg_field_set(unit, WCL_CTLr, &wcl_ctl_buf, RSTB_HWf, 1); 365 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, WCL_CTLr, 0, wcl_num, wcl_ctl_buf)); 366 } 367 for (wcl_num = 0; wcl_num < NUM_WCLS; ++wcl_num) { 368 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, WCL_CTLr, 0, wcl_num, &wcl_ctl_buf)); 369 soc_reg_field_set(unit, WCL_CTLr, &wcl_ctl_buf, RSTB_MDIOREGSf, 1); 370 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, WCL_CTLr, 0, wcl_num, wcl_ctl_buf)); 371 } 372 373 /* wcl - Set all the MDIO registers inside the ESM SerDes. Take care of any 374 necessary initial programming. 375 For example, we may have to set the PLL divider, multiplier, etc thro 376 mdio writes, reads 377 */ 378 379 SOC_IF_ERROR_RETURN(wcl_mdio_init_seq(unit)); 380 381 /* wcl - De-assert RSTB_PLL - pll_reset 382 Release rstb_pll 383 */ 384 385 for (wcl_num = 0; wcl_num < NUM_WCLS; ++wcl_num) { 386 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, WCL_CTLr, 0, wcl_num, &wcl_ctl_buf)); 387 soc_reg_field_set(unit, WCL_CTLr, &wcl_ctl_buf, RSTB_PLLf, 1); 388 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, WCL_CTLr, 0, wcl_num, wcl_ctl_buf)); 389 } 390 391 _SHR_RETURN(wcl_poll_txpll_lock(unit)); 392 } 393 394 395 STATIC int 396 phy_c45_read(int unit, 397 unsigned phy_id, 398 unsigned phy_devad, 399 unsigned phy_reg, 400 uint16 *phy_data 401 ) 402 { 403 _SHR_RETURN(soc_miimc45_read(unit, phy_id, phy_devad, phy_reg, phy_data)); 404 } 405 406 407 STATIC int 408 phy_c45_write(int unit, 409 unsigned phy_id, 410 unsigned phy_devad, 411 unsigned phy_reg, 412 uint16 phy_data 413 ) 414 { 415 _SHR_RETURN(soc_miimc45_write(unit, phy_id, phy_devad, phy_reg, phy_data)); 416 } 417 418 419 STATIC int 420 nl_mdio_read(int unit, 421 unsigned mdio_portid, 422 unsigned mdio_dev_id, 423 unsigned mdio_addr, 424 uint16 *rd_data 425 ) 426 { 427 const unsigned phy_id = (1 << 8) | (0 << 7) | (0 << 5) | mdio_portid; 428 429 _SHR_RETURN(phy_c45_read(unit, phy_id, mdio_dev_id, mdio_addr, rd_data)); 430 } 431 432 433 STATIC int 434 nl_mdio_write(int unit, 435 unsigned mdio_portid, 436 unsigned mdio_dev_id, 437 unsigned mdio_addr, 438 uint16 wr_data, 439 unsigned verify_wr 440 ) 441 { 442 const unsigned phy_id = (1 << 8) | (0 << 7) | (0 << 5) | mdio_portid; 443 444 SOC_IF_ERROR_RETURN(phy_c45_write(unit, phy_id, mdio_dev_id, mdio_addr, wr_data)); 445 446 if (verify_wr) { 447 uint16 rd_data; 448 449 SOC_IF_ERROR_RETURN(nl_mdio_read(unit, 450 mdio_portid, 451 mdio_dev_id, 452 mdio_addr, 453 &rd_data 454 ) 455 ); 456 457 if (rd_data != wr_data) _SHR_RETURN(SOC_E_FAIL); 458 } 459 460 _SHR_RETURN(SOC_E_NONE); 461 } 462 463 464 STATIC int 465 nl_mdio_test_reg_access(int unit, unsigned mdio_portid) 466 { 467 const unsigned mdio_dev_id = 2; 468 469 unsigned errcnt = 0; 470 uint16 val; 471 472 /* Will use following mdio regs for this test: 473 RX SerDes - PRBS Control and Status Registers, MDIO Device ID = 2 to 10, see Table 24 474 */ 475 476 /* Verify default value for registers */ 477 478 if (SOC_FAILURE(nl_mdio_read(unit, mdio_portid, mdio_dev_id, 0x12, &val)) 479 || val != 0xaaaa 480 ) { 481 ++errcnt; 482 } 483 if (SOC_FAILURE(nl_mdio_read(unit, mdio_portid, mdio_dev_id, 0x13, &val)) 484 || val != 0xaaaa 485 ) { 486 ++errcnt; 487 } 488 489 /* Test write_verify */ 490 491 if (SOC_FAILURE(nl_mdio_write(unit, mdio_portid, mdio_dev_id, 0x12, 0x5555, 1))) { 492 ++errcnt; 493 } 494 if (SOC_FAILURE(nl_mdio_write(unit, mdio_portid, mdio_dev_id, 0x13, 0x1234, 1))) { 495 ++errcnt; 496 } 497 498 /* Make sure our above writes went to different registers */ 499 500 if (SOC_FAILURE(nl_mdio_read(unit, mdio_portid, mdio_dev_id, 0x12, &val)) 501 || val != 0x5555 502 ) { 503 ++errcnt; 504 } 505 if (SOC_FAILURE(nl_mdio_read(unit, mdio_portid, mdio_dev_id, 0x13, &val)) 506 || val != 0x1234 507 ) { 508 ++errcnt; 509 } 510 511 /* Restore default values */ 512 513 if (SOC_FAILURE(nl_mdio_write(unit, mdio_portid, mdio_dev_id, 0x12, 0xaaaa, 1))) { 514 ++errcnt; 515 } 516 if (SOC_FAILURE(nl_mdio_write(unit, mdio_portid, mdio_dev_id, 0x13, 0xaaaa, 1))) { 517 ++errcnt; 518 } 519 520 _SHR_RETURN(errcnt ? SOC_E_FAIL : SOC_E_NONE); 521 } 522 523 524 unsigned 525 mdio_portid_get(int unit, unsigned dev_id) 526 { 527 soc_tcam_info_t *tcam_info; 528 529 tcam_info = (soc_tcam_info_t *) SOC_CONTROL(unit)->tcam_info; 530 return (dev_id == 1 ? tcam_info->mdio_port_tcam1 : 531 tcam_info->mdio_port_tcam0); 532 } 533 534 535 STATIC int 536 nl_mdio_chk_serdes_reset_seq_done(int unit, unsigned mdio_portid) 537 { 538 uint16 val; 539 540 SOC_IF_ERROR_RETURN(nl_mdio_read(unit, mdio_portid, 1, 0x8183, &val)); 541 return (val & (1 << 3) ? SOC_E_NONE : SOC_E_BUSY); 542 } 543 544 545 STATIC int 546 nl_mdio_poll_serdes_reset_seq_done(int unit, unsigned mdio_portid) 547 { 548 unsigned n; 549 550 for (n = 1000; n; --n) { 551 int errcode = nl_mdio_chk_serdes_reset_seq_done(unit, mdio_portid); 552 553 if (errcode == SOC_E_BUSY) { 554 sal_usleep(1000); /* Wait 1 ms */ 555 continue; 556 } 557 558 _SHR_RETURN(errcode); 559 } 560 561 _SHR_RETURN(SOC_E_TIMEOUT); 562 } 563 564 STATIC int 565 nl_set_analog_parameters(int unit, int tcam_num) { 566 int transmitter, receiver, lane, config_val, post_cursor_val, main_tap, rx_gain; 567 uint16 mdio_rval; 568 unsigned mdio_dev, mdio_addr; 569 unsigned mdio_portid = mdio_portid_get(unit, tcam_num); 570 571 /* Setup all transmitters (12 TX and 24 CTX) */ 572 for (transmitter = 0; transmitter < 36; transmitter++) { 573 if (transmitter < 12) { 574 lane = transmitter; 575 if (tcam_num == 0) { 576 config_val = soc_property_suffix_num_get(unit, lane, 577 spn_EXT_TCAM0_TX_DRIVER_CURRENT, 578 "tx_lane", 0); 579 post_cursor_val = soc_property_suffix_num_get(unit, lane, 580 spn_EXT_TCAM0_TX_POSTCURSOR_TAP, 581 "tx_lane", 0); 582 main_tap = soc_property_suffix_num_get(unit, lane, 583 spn_EXT_TCAM0_TX_MAIN_TAP, 584 "tx_lane", 0x3f); 585 } else { 586 config_val = soc_property_suffix_num_get(unit, lane, 587 spn_EXT_TCAM1_TX_DRIVER_CURRENT, 588 "tx_lane", 0); 589 post_cursor_val = soc_property_suffix_num_get(unit, lane, 590 spn_EXT_TCAM1_TX_POSTCURSOR_TAP, 591 "tx_lane", 0); 592 main_tap = soc_property_suffix_num_get(unit, lane, 593 spn_EXT_TCAM1_TX_MAIN_TAP, 594 "tx_lane", 0x3f); 595 } 596 } else { 597 lane = transmitter - 12; 598 if (tcam_num == 0) { 599 config_val = soc_property_suffix_num_get(unit, lane, 600 spn_EXT_TCAM0_TX_DRIVER_CURRENT, 601 "ctx_lane", 0); 602 post_cursor_val = soc_property_suffix_num_get(unit, lane, 603 spn_EXT_TCAM0_TX_POSTCURSOR_TAP, 604 "ctx_lane", 0); 605 main_tap = soc_property_suffix_num_get(unit, lane, 606 spn_EXT_TCAM0_TX_MAIN_TAP, 607 "ctx_lane", 0x3f); 608 } else { 609 config_val = soc_property_suffix_num_get(unit, lane, 610 spn_EXT_TCAM1_TX_DRIVER_CURRENT, 611 "ctx_lane", 0); 612 post_cursor_val = soc_property_suffix_num_get(unit, lane, 613 spn_EXT_TCAM1_TX_POSTCURSOR_TAP, 614 "ctx_lane", 0); 615 main_tap = soc_property_suffix_num_get(unit, lane, 616 spn_EXT_TCAM1_TX_MAIN_TAP, 617 "ctx_lane", 0x3f); 618 } 619 } 620 621 /* Set transmitter bias settings */ 622 config_val &= 0x3; 623 switch (transmitter / 4) { 624 case 0: 625 case 1: 626 case 2: 627 mdio_dev = 22; 628 mdio_addr = 0x118 - (lane / 4 * 7); 629 break; 630 case 3: 631 case 4: 632 case 5: 633 case 6: 634 case 7: 635 case 8: 636 mdio_dev = 23; 637 mdio_addr = 0x11f - (lane / 4 * 7); 638 break; 639 /* 640 * COVERITY 641 * 642 * This default is unreachable but kept intentionally 643 * as a defensive check. 644 */ 645 /* coverity[dead_error_begin] */ 646 default: 647 mdio_dev = 22; 648 mdio_addr = 0x103; 649 break; 650 } 651 switch (lane % 4) { 652 case 0: 653 nl_mdio_read(unit, mdio_portid, mdio_dev, mdio_addr, &mdio_rval); 654 mdio_rval &= 0xfff0; 655 mdio_rval |= (config_val << 2) | (config_val << 0); 656 nl_mdio_write(unit, mdio_portid, mdio_dev, mdio_addr, mdio_rval, 1); 657 mdio_addr -= 3; 658 nl_mdio_read(unit, mdio_portid, mdio_dev, mdio_addr, &mdio_rval); 659 mdio_rval &= 0xf000; 660 mdio_rval |= (config_val << 10) | (config_val << 8) | 661 (config_val << 6) | (config_val << 4) | 662 (config_val << 2) | (config_val << 0); 663 nl_mdio_write(unit, mdio_portid, mdio_dev, mdio_addr, mdio_rval, 1); 664 break; 665 case 1: 666 nl_mdio_read(unit, mdio_portid, mdio_dev, mdio_addr, &mdio_rval); 667 mdio_rval &= 0xff0f; 668 mdio_rval |= (config_val << 6) | (config_val << 4); 669 nl_mdio_write(unit, mdio_portid, mdio_dev, mdio_addr, mdio_rval, 1); 670 mdio_addr -= 2; 671 nl_mdio_read(unit, mdio_portid, mdio_dev, mdio_addr, &mdio_rval); 672 mdio_rval &= 0xff00; 673 mdio_rval |= (config_val << 6) | (config_val << 4) | 674 (config_val << 2) | (config_val << 0); 675 nl_mdio_write(unit, mdio_portid, mdio_dev, mdio_addr, mdio_rval, 1); 676 mdio_addr -= 1; 677 nl_mdio_read(unit, mdio_portid, mdio_dev, mdio_addr, &mdio_rval); 678 mdio_rval &= 0x0fff; 679 mdio_rval |= (config_val << 14) | (config_val << 12); 680 nl_mdio_write(unit, mdio_portid, mdio_dev, mdio_addr, mdio_rval, 1); 681 break; 682 case 2: 683 nl_mdio_read(unit, mdio_portid, mdio_dev, mdio_addr, &mdio_rval); 684 mdio_rval &= 0xf0ff; 685 mdio_rval |= (config_val << 10) | (config_val << 8); 686 nl_mdio_write(unit, mdio_portid, mdio_dev, mdio_addr, mdio_rval, 1); 687 mdio_addr -= 1; 688 nl_mdio_read(unit, mdio_portid, mdio_dev, mdio_addr, &mdio_rval); 689 mdio_rval &= 0xfff0; 690 mdio_rval |= (config_val << 2) | (config_val << 0); 691 nl_mdio_write(unit, mdio_portid, mdio_dev, mdio_addr, mdio_rval, 1); 692 mdio_addr -= 1; 693 nl_mdio_read(unit, mdio_portid, mdio_dev, mdio_addr, &mdio_rval); 694 mdio_rval &= 0x00ff; 695 mdio_rval |= (config_val << 14) | (config_val << 12) | 696 (config_val << 10) | (config_val << 8); 697 nl_mdio_write(unit, mdio_portid, mdio_dev, mdio_addr, mdio_rval, 1); 698 break; 699 case 3: 700 nl_mdio_read(unit, mdio_portid, mdio_dev, mdio_addr, &mdio_rval); 701 mdio_rval &= 0x0fff; 702 mdio_rval |= (config_val << 14) | (config_val << 12); 703 nl_mdio_write(unit, mdio_portid, mdio_dev, mdio_addr, mdio_rval, 1); 704 mdio_addr -= 1; 705 nl_mdio_read(unit, mdio_portid, mdio_dev, mdio_addr, &mdio_rval); 706 mdio_rval &= 0x000f; 707 mdio_rval |= (config_val << 14) | (config_val << 12) | 708 (config_val << 10) | (config_val << 8) | 709 (config_val << 6) | (config_val << 4); 710 nl_mdio_write(unit, mdio_portid, mdio_dev, mdio_addr, mdio_rval, 1); 711 break; 712 /* 713 * COVERITY 714 * 715 * This default is unreachable but kept intentionally 716 * as a defensive check. 717 */ 718 /* coverity[dead_error_begin] */ 719 default: 720 break; 721 } 722 723 /* Set transmitter post-cursor tap */ 724 mdio_rval = post_cursor_val & 0x1f; 725 mdio_dev = 11 + (transmitter / 4); 726 mdio_addr = 0x104 + (lane % 4 * 0x10); 727 nl_mdio_write(unit, mdio_portid, mdio_dev, mdio_addr, mdio_rval, 1); 728 729 /* Set transmitter main tap */ 730 mdio_rval = main_tap & 0x3f; 731 mdio_dev = 11 + (transmitter / 4); 732 mdio_addr = 0x103 + (lane % 4 * 0x10); 733 nl_mdio_write(unit, mdio_portid, mdio_dev, mdio_addr, mdio_rval, 1); 734 735 /* Enable the preemphasis */ 736 mdio_rval = 0x0001; 737 mdio_dev = 11 + (transmitter / 4); 738 mdio_addr = 0x105 + (lane % 4 * 0x10); 739 nl_mdio_write(unit, mdio_portid, mdio_dev, mdio_addr, mdio_rval, 1); 740 } 741 742 /* Setup all receivers (24 RX and 12 CRX) */ 743 for (receiver = 0; receiver < 36; receiver++) { 744 if (receiver < 24) { 745 lane = receiver; 746 if (tcam_num == 0) { 747 rx_gain = soc_property_suffix_num_get(unit, lane, 748 spn_EXT_TCAM0_RX_GAIN, 749 "rx_lane", 0); 750 } else { 751 rx_gain = soc_property_suffix_num_get(unit, lane, 752 spn_EXT_TCAM1_RX_GAIN, 753 "rx_lane", 0); 754 } 755 } else { 756 lane = receiver - 24; 757 if (tcam_num == 0) { 758 rx_gain = soc_property_suffix_num_get(unit, lane, 759 spn_EXT_TCAM0_RX_GAIN, 760 "crx_lane", 0); 761 } else { 762 rx_gain = soc_property_suffix_num_get(unit, lane, 763 spn_EXT_TCAM1_RX_GAIN, 764 "crx_lane", 0); 765 } 766 } 767 768 /* Set receiver gain 769 The serdes always operates at 6.25G, so no need to set Fc*/ 770 mdio_rval = (3 << 6) | ((rx_gain & 0x1f) << 1) | 0x0001; 771 mdio_dev = 2 + (receiver / 4); 772 mdio_addr = 0x128 + (lane % 4 * 0x10); 773 nl_mdio_write(unit, mdio_portid, mdio_dev, mdio_addr, mdio_rval, 1); 774 } 775 776 return SOC_E_NONE; 777 } 778 779 #define NL_METAFRAME_LENGTH 2048 780 781 STATIC int 782 nl_mdio_init_seq(int unit, 783 unsigned num_nl, 784 unsigned rx_fifo_thr, 785 unsigned tx_fifo_thr, 786 unsigned tx_burst_short_16b 787 ) 788 { 789 const unsigned mdio_dev_id = 1; 790 unsigned dev_id; 791 unsigned int nl_16lane_mode = 0; 792 793 /* Device configuration using mdio (section 6.7) 794 795 CSM - Config Regs, MDIO Devid=1, see Table 18 in NL spec 796 - All regs are 16b wide 797 NL's init seq: 4 Rx lanes, 2 Tx lanes 798 See Table 17 in NL spec, it shows mapping of MDIO Device ID to SerDes lanes within NL 799 This is must to understand when we want to enable prbs generators, 800 checkers 801 */ 802 803 if (num_nl == 2) { 804 nl_16lane_mode = 1; 805 } 806 for (dev_id = 0; dev_id < num_nl; ++dev_id) { 807 unsigned mdio_portid = mdio_portid_get(unit, dev_id); 808 809 /* TX_SerDes_11_0_squelch (Active high squelch for TX SerDes 11:0) */ 810 SOC_IF_ERROR_RETURN(nl_mdio_write(unit, 811 mdio_portid, 812 mdio_dev_id, 813 0x8117, 814 0xfff, 815 1 816 ) 817 ); 818 /* CTX_SerDes_15_0_squelch (Active high squelch for CTX SerDes 15:0) */ 819 SOC_IF_ERROR_RETURN(nl_mdio_write(unit, 820 mdio_portid, 821 mdio_dev_id, 822 0x8118, 823 0xffff, 824 1 825 ) 826 ); 827 /* CTX_SerDes_23_16_squelch (Active high squelch for CTX SerDes 23:16) */ 828 SOC_IF_ERROR_RETURN(nl_mdio_write(unit, 829 mdio_portid, 830 mdio_dev_id, 831 0x8119, 832 0xff, 833 1 834 ) 835 ); 836 } 837 838 for (dev_id = 0; dev_id < num_nl; ++dev_id) { 839 unsigned mdio_portid = mdio_portid_get(unit, dev_id); 840 841 /* Global RX / TX Enable (PCS enables), Bit[0] = RX PCS Enable, Bit[1] = 842 TX PCS Enable 843 */ 844 SOC_IF_ERROR_RETURN(nl_mdio_write(unit, 845 mdio_portid, 846 mdio_dev_id, 847 0x810c, 848 0, 849 1 850 ) 851 ); 852 } 853 854 for (dev_id = 0; dev_id < num_nl; ++dev_id) { 855 unsigned mdio_portid = mdio_portid_get(unit, dev_id); 856 857 /* Global SW Reset - ASSERT (only bits 2:0 are defined) 858 Bit[2] SerDes Initialization Sequence Trigger, 859 Bit[1] Reset Core Logic, 860 Bit[0] Reset Core PLL 861 */ 862 SOC_IF_ERROR_RETURN(nl_mdio_write(unit, 863 mdio_portid, 864 mdio_dev_id, 865 0x811c, 866 7, 867 1 868 ) 869 ); 870 } 871 872 if ((!nl_16lane_mode) && (num_nl > 1)) { 873 const unsigned dev_id = 1; 874 const unsigned mdio_portid = mdio_portid_get(unit, dev_id); 875 876 uint16 regval; 877 878 SOC_IF_ERROR_RETURN(nl_mdio_read(unit, mdio_portid, 1, 0x8236, ®val)); 879 SOC_IF_ERROR_RETURN(nl_mdio_write(unit, mdio_portid, 1, 0x8236, regval & ~(1 << 2), 1)); 880 881 SOC_IF_ERROR_RETURN(nl_mdio_read(unit, mdio_portid, 1, 0x8237, ®val)); 882 SOC_IF_ERROR_RETURN(nl_mdio_write(unit, mdio_portid, 1, 0x8237, regval & ~(1 << 0), 1)); 883 } 884 885 886 for (dev_id = 0; dev_id < num_nl; ++dev_id) { 887 unsigned mdio_portid = mdio_portid_get(unit, dev_id); 888 889 /* Lane Swap 890 Bit[0] for RX lanes swap, Bit[0]=1 means Lane 0 and Lane 23, Lane 1 and Lane 22, 891 ... Lane 11 and Lane 12 are swapped 892 Bit[1] for TX lanes swap, Bit[1]=1 means Lane 0 and Lane 11, Lane 1 and Lane 10, 893 ... Lane 5 and Lane 6 are swapped 894 */ 895 SOC_IF_ERROR_RETURN(nl_mdio_write(unit, 896 mdio_portid, 897 mdio_dev_id, 898 0x8108, 899 0, 900 1 901 ) 902 ); 903 /* RX Metaframe Length */ 904 SOC_IF_ERROR_RETURN(nl_mdio_write(unit, 905 mdio_portid, 906 mdio_dev_id, 907 0x8106, 908 NL_METAFRAME_LENGTH, 909 1 910 ) 911 ); 912 /* TX Metaframe Length */ 913 SOC_IF_ERROR_RETURN(nl_mdio_write(unit, 914 mdio_portid, 915 mdio_dev_id, 916 0x8107, 917 NL_METAFRAME_LENGTH, 918 1 919 ) 920 ); 921 /* RX (req) FIFO Threshold */ 922 SOC_IF_ERROR_RETURN(nl_mdio_write(unit, 923 mdio_portid, 924 mdio_dev_id, 925 0x8109, 926 rx_fifo_thr, 927 1 928 ) 929 ); 930 /* TX (rsp) FIFO Threshold */ 931 SOC_IF_ERROR_RETURN(nl_mdio_write(unit, 932 mdio_portid, 933 mdio_dev_id, 934 0x810a, 935 tx_fifo_thr, 936 1 937 ) 938 ); 939 /* TX Burst Short (0 means 8 bytes, 1 means 16 bytes) */ 940 SOC_IF_ERROR_RETURN(nl_mdio_write(unit, 941 mdio_portid, 942 mdio_dev_id, 943 0x810b, 944 tx_burst_short_16b ? 1 : 0, 945 1 946 ) 947 ); 948 /* Speed mode select, bits 2:0 select speed for rx serdes, bits 6:4 949 select speed for tx serdes 950 3'b100 means 6.250 Gbps, 3'b000 means 3.125 Gbps 951 */ 952 SOC_IF_ERROR_RETURN(nl_mdio_write(unit, 953 mdio_portid, 954 mdio_dev_id, 955 0x811d, 956 0x44, 957 1 958 ) 959 ); 960 /* Add TX/RX analog configuration */ 961 SOC_IF_ERROR_RETURN(nl_set_analog_parameters(unit, dev_id)); 962 /* Apply the low jitter settings */ 963 if (apply_low_jitter_nl_settings) { 964 /* TX pll charge pump enable */ 965 SOC_IF_ERROR_RETURN(nl_mdio_write(unit, 966 mdio_portid, 967 31, 968 0x0501, 969 0x0031, 970 1 971 ) 972 ); 973 974 /* TX regulator bandwidth */ 975 SOC_IF_ERROR_RETURN(nl_mdio_write(unit, 976 mdio_portid, 977 31, 978 0x0502, 979 0x0940, 980 1 981 ) 982 ); 983 984 /* TX clock mode override */ 985 SOC_IF_ERROR_RETURN(nl_mdio_write(unit, 986 mdio_portid, 987 31, 988 0x0200, 989 0x0007, 990 1 991 ) 992 ); 993 994 /* TX transmit PLL divider */ 995 SOC_IF_ERROR_RETURN(nl_mdio_write(unit, 996 mdio_portid, 997 31, 998 0x0500, 999 0x0501, 1000 1 1001 ) 1002 ); 1003 1004 /* TX BIAS generators for CTX23-20, TX11-0 */ 1005 SOC_IF_ERROR_RETURN(nl_mdio_write(unit, 1006 mdio_portid, 1007 22, 1008 0x0105, 1009 0x0010, 1010 1 1011 ) 1012 ); 1013 1014 SOC_IF_ERROR_RETURN(nl_mdio_write(unit, 1015 mdio_portid, 1016 22, 1017 0x010C, 1018 0x0010, 1019 1 1020 ) 1021 ); 1022 1023 SOC_IF_ERROR_RETURN(nl_mdio_write(unit, 1024 mdio_portid, 1025 22, 1026 0x0113, 1027 0x0010, 1028 1 1029 ) 1030 ); 1031 1032 SOC_IF_ERROR_RETURN(nl_mdio_write(unit, 1033 mdio_portid, 1034 22, 1035 0x011A, 1036 0x0010, 1037 1 1038 ) 1039 ); 1040 1041 SOC_IF_ERROR_RETURN(nl_mdio_write(unit, 1042 mdio_portid, 1043 22, 1044 0x0121, 1045 0x0010, 1046 1 1047 ) 1048 ); 1049 1050 /* TX BIAS generators for CTX19-0 */ 1051 SOC_IF_ERROR_RETURN(nl_mdio_write(unit, 1052 mdio_portid, 1053 23, 1054 0x0105, 1055 0x0010, 1056 1 1057 ) 1058 ); 1059 1060 SOC_IF_ERROR_RETURN(nl_mdio_write(unit, 1061 mdio_portid, 1062 23, 1063 0x010C, 1064 0x0010, 1065 1 1066 ) 1067 ); 1068 1069 SOC_IF_ERROR_RETURN(nl_mdio_write(unit, 1070 mdio_portid, 1071 23, 1072 0x0113, 1073 0x0010, 1074 1 1075 ) 1076 ); 1077 1078 SOC_IF_ERROR_RETURN(nl_mdio_write(unit, 1079 mdio_portid, 1080 23, 1081 0x011A, 1082 0x0010, 1083 1 1084 ) 1085 ); 1086 1087 SOC_IF_ERROR_RETURN(nl_mdio_write(unit, 1088 mdio_portid, 1089 23, 1090 0x0121, 1091 0x0010, 1092 1 1093 ) 1094 ); 1095 1096 } 1097 } 1098 1099 for (dev_id = 0; dev_id < num_nl; ++dev_id) { 1100 unsigned mdio_portid = mdio_portid_get(unit, dev_id); 1101 1102 /* RX Lane Enable 0 (RX lane enable for lanes 15 to 0) */ 1103 SOC_IF_ERROR_RETURN(nl_mdio_write(unit, 1104 mdio_portid, 1105 mdio_dev_id, 1106 0x8100, 1107 0xffff, 1108 1 1109 ) 1110 ); 1111 /* RX Lane Enable 1 (RX lane enable for lanes 23 to 16) */ 1112 SOC_IF_ERROR_RETURN(nl_mdio_write(unit, 1113 mdio_portid, 1114 mdio_dev_id, 1115 0x8101, 1116 (nl_16lane_mode) ? 0x00 : 0xff, 1117 1 1118 ) 1119 ); 1120 /* TX Lane Enable 0 (TX lane enable for lanes 11 to 0) */ 1121 SOC_IF_ERROR_RETURN(nl_mdio_write(unit, 1122 mdio_portid, 1123 mdio_dev_id, 1124 0x8102, 1125 0xfff, 1126 1 1127 ) 1128 ); 1129 } 1130 1131 for (dev_id = 0; dev_id < num_nl; ++dev_id) { 1132 unsigned mdio_portid = mdio_portid_get(unit, dev_id); 1133 1134 SOC_IF_ERROR_RETURN(nl_mdio_write(unit, 1135 mdio_portid, 1136 mdio_dev_id, 1137 0x8104, 1138 dev_id == (num_nl - 1) ? 0 : 0xffff, 1139 1 1140 ) 1141 ); 1142 SOC_IF_ERROR_RETURN(nl_mdio_write(unit, 1143 mdio_portid, 1144 mdio_dev_id, 1145 0x8105, 1146 (nl_16lane_mode) ? 0x00 : dev_id == (num_nl - 1) ? 0 : 0xff, 1147 1 1148 ) 1149 ); 1150 } 1151 1152 for (dev_id = 0; dev_id < num_nl; ++dev_id) { 1153 unsigned mdio_portid = mdio_portid_get(unit, dev_id); 1154 1155 SOC_IF_ERROR_RETURN(nl_mdio_write(unit, 1156 mdio_portid, 1157 mdio_dev_id, 1158 0x8103, 1159 dev_id ? 0xfff : 0, 1160 1 1161 ) 1162 ); 1163 } 1164 1165 for (dev_id = 0; dev_id < num_nl; ++dev_id) { 1166 unsigned mdio_portid = mdio_portid_get(unit, dev_id); 1167 1168 /* Global SW Reset - Deassert (only bits 2:0 are defined) 1169 Bit[2] SerDes Initialization Sequence Trigger, 1170 Bit[1] Reset Core Logic, 1171 Bit[0] Reset Core PLL 1172 */ 1173 SOC_IF_ERROR_RETURN(nl_mdio_write(unit, 1174 mdio_portid, 1175 mdio_dev_id, 1176 0x811c, 1177 0, 1178 1 1179 ) 1180 ); 1181 } 1182 1183 for (dev_id = 0; dev_id < num_nl; ++dev_id) { 1184 unsigned mdio_portid = mdio_portid_get(unit, dev_id); 1185 1186 SOC_IF_ERROR_RETURN(nl_mdio_poll_serdes_reset_seq_done(unit, mdio_portid)); 1187 } 1188 1189 for (dev_id = 0; dev_id < num_nl; ++dev_id) { 1190 unsigned mdio_portid = mdio_portid_get(unit, dev_id); 1191 1192 /* Global RX / TX Enable (PCS enables), Bit[0] = RX PCS Enable, Bit[1] = 1193 TX PCS Enable 1194 */ 1195 SOC_IF_ERROR_RETURN(nl_mdio_write(unit, 1196 mdio_portid, 1197 mdio_dev_id, 1198 0x810c, 1199 3, 1200 1 1201 ) 1202 ); 1203 } 1204 1205 for (dev_id = 0; dev_id < num_nl; ++dev_id) { 1206 unsigned mdio_portid = mdio_portid_get(unit, dev_id); 1207 1208 /* TX_SerDes_11_0_squelch (Active high squelch for TX SerDes 11:0) */ 1209 SOC_IF_ERROR_RETURN(nl_mdio_write(unit, 1210 mdio_portid, 1211 mdio_dev_id, 1212 0x8117, 1213 0, 1214 1 1215 ) 1216 ); 1217 SOC_IF_ERROR_RETURN(nl_mdio_write(unit, 1218 mdio_portid, 1219 mdio_dev_id, 1220 0x8118, 1221 dev_id == (num_nl - 1) ? 0xffff : 0, 1222 1 1223 ) 1224 ); 1225 SOC_IF_ERROR_RETURN(nl_mdio_write(unit, 1226 mdio_portid, 1227 mdio_dev_id, 1228 0x8119, 1229 dev_id == (num_nl - 1) ? 0xff : 0, 1230 1 1231 ) 1232 ); 1233 } 1234 1235 _SHR_RETURN(SOC_E_NONE); 1236 } 1237 1238 1239 int 1240 nl_mdio_prbs_chk(int unit, uint16 mdio_portid, uint16 prbs, uint32 seed, 1241 uint16 crx, uint32 enable) 1242 { 1243 uint16 nl_tcams = ((soc_tcam_info_t *)SOC_CONTROL(unit)->tcam_info)->num_tcams; 1244 uint16 mdio_devid_max = crx? 10 : 7; 1245 uint16 mdio_devid_min = 2; 1246 uint16 mdio_devid; 1247 1248 seed = enable && (seed!=0)? seed : 0xAAAAAAAA; 1249 1250 if (prbs == 1) { 1251 _SHR_RETURN(SOC_E_PARAM); 1252 } 1253 /* PRBS control [2:1] - poly */ 1254 prbs = enable? (prbs == 0? 0x4: ((prbs == 2)? 0x2: 0x0)) : 0x0; 1255 /* PRBS control [0] - enable */ 1256 prbs = enable? prbs | 0x1: prbs; 1257 1258 for(mdio_devid = mdio_devid_min; mdio_devid <= mdio_devid_max; ++mdio_devid) { 1259 /* If cascaded tcam, request lines are just 16 lanes not 24, 1260 Skip for devid 6 & 7. 1261 */ 1262 if((nl_tcams>1) && ((mdio_devid == 6) || (mdio_devid == 7))) { 1263 continue; 1264 } 1265 SOC_IF_ERROR_RETURN 1266 (nl_mdio_write(unit, mdio_portid, mdio_devid, 0x12, seed & 0xffff, 1)); 1267 SOC_IF_ERROR_RETURN 1268 (nl_mdio_write(unit, mdio_portid, mdio_devid, 0x13, (seed >> 16) & 0xffff, 1)); 1269 SOC_IF_ERROR_RETURN 1270 (nl_mdio_write(unit, mdio_portid, mdio_devid, 0x11, prbs, 1)); 1271 } 1272 1273 _SHR_RETURN(SOC_E_NONE); 1274 } 1275 1276 1277 int 1278 nl_mdio_prbs_gen(int unit, uint16 mdio_portid, uint16 prbs, uint32 seed, 1279 uint16 ctx, uint32 enable) 1280 { 1281 uint16 nl_tcams = ((soc_tcam_info_t *)SOC_CONTROL(unit)->tcam_info)->num_tcams; 1282 uint16 mdio_devid_max = ctx? ((nl_tcams>1)? 17: 19) : 13; 1283 uint16 mdio_devid_min = 11; 1284 uint16 mdio_devid; 1285 1286 seed = enable && (seed!=0)? seed : 0xAAAAAAAA; 1287 1288 if (prbs == 1) { 1289 _SHR_RETURN(SOC_E_PARAM); 1290 } 1291 /* PRBS control [2:1] - poly */ 1292 prbs = enable? (prbs == 0? 0x4: ((prbs == 2)? 0x2: 0x0)) : 0x0; 1293 /* PRBS control [0] - enable */ 1294 prbs = enable? prbs | 0x1: 0x0; 1295 1296 for(mdio_devid = mdio_devid_min; mdio_devid <= mdio_devid_max; ++mdio_devid) { 1297 SOC_IF_ERROR_RETURN 1298 (nl_mdio_write(unit, mdio_portid, mdio_devid, 0x12, seed & 0xffff, 1)); 1299 SOC_IF_ERROR_RETURN 1300 (nl_mdio_write(unit, mdio_portid, mdio_devid, 0x13, (seed >> 16) & 0xffff, 1)); 1301 SOC_IF_ERROR_RETURN 1302 (nl_mdio_write(unit, mdio_portid, mdio_devid, 0x11, prbs, 1)); 1303 } 1304 1305 _SHR_RETURN(SOC_E_NONE); 1306 } 1307 1308 int 1309 nl_mdio_prbs_chk_err(int unit, uint16 mdio_portid, uint16 crx) 1310 { 1311 uint16 nl_tcams = ((soc_tcam_info_t *)SOC_CONTROL(unit)->tcam_info)->num_tcams; 1312 uint16 mdio_devid_max = crx?10:7; 1313 uint16 mdio_devid_min = 2; 1314 uint16 mdio_devid; 1315 uint16 prbs_ctrl, prbs_pass = 1; 1316 uint16 err_count_l0 = 0, err_count_l1 = 0, err_count_l2, err_count_l3 = 0; 1317 char if_name[10]; 1318 int if_lane_base; 1319 1320 sal_memset(if_name, 0, sizeof(if_name)); 1321 for(mdio_devid = mdio_devid_min; mdio_devid <= mdio_devid_max; ++mdio_devid) { 1322 /* If cascaded tcam, request lines are just 16 lanes not 24, 1323 Skip for devid 6 & 7. 1324 */ 1325 if((nl_tcams>1) && ((mdio_devid == 6) || (mdio_devid == 7))) { 1326 continue; 1327 } 1328 SOC_IF_ERROR_RETURN 1329 (nl_mdio_read(unit, mdio_portid, mdio_devid, 0x11, &prbs_ctrl)); 1330 if((prbs_ctrl & 0x1) == 0x0) { 1331 LOG_WARN(BSL_LS_SOC_ESM, 1332 (BSL_META_U(unit, 1333 "PRBS is not enabled for NL TCAM mdio_portid=%d\n"), mdio_portid)); 1334 return SOC_E_FAIL; 1335 } 1336 SOC_IF_ERROR_RETURN 1337 (nl_mdio_read(unit, mdio_portid, mdio_devid, 0x14, &err_count_l0)); 1338 SOC_IF_ERROR_RETURN 1339 (nl_mdio_read(unit, mdio_portid, mdio_devid, 0x15, &err_count_l1)); 1340 SOC_IF_ERROR_RETURN 1341 (nl_mdio_read(unit, mdio_portid, mdio_devid, 0x16, &err_count_l2)); 1342 SOC_IF_ERROR_RETURN 1343 (nl_mdio_read(unit, mdio_portid, mdio_devid, 0x17, &err_count_l3)); 1344 1345 (mdio_devid < 8) ? sal_strncpy(if_name, "RX", (sizeof(if_name)-1)) : 1346 sal_strncpy(if_name, "CRX",(sizeof(if_name)-1)); 1347 if_lane_base = (mdio_devid < 8) ? (mdio_devid - 2) * 4 : (mdio_devid - 8) * 4; 1348 1349 if(err_count_l0) { 1350 LOG_WARN(BSL_LS_SOC_ESM, 1351 (BSL_META_U(unit, 1352 "\t%d PRBS errors seen on lane %d of %s interface\n"), err_count_l0, if_lane_base + 0, if_name)); 1353 } 1354 if(err_count_l1) { 1355 LOG_WARN(BSL_LS_SOC_ESM, 1356 (BSL_META_U(unit, 1357 "\t%d PRBS errors seen on lane %d of %s interface\n"), err_count_l1, if_lane_base + 1, if_name)); 1358 } 1359 if(err_count_l2) { 1360 LOG_WARN(BSL_LS_SOC_ESM, 1361 (BSL_META_U(unit, 1362 "\t%d PRBS errors seen on lane %d of %s interface\n"), err_count_l2, if_lane_base + 2, if_name)); 1363 } 1364 if(err_count_l3) { 1365 LOG_WARN(BSL_LS_SOC_ESM, 1366 (BSL_META_U(unit, 1367 "\t%d PRBS errors seen on lane %d of %s interface\n"), err_count_l3, if_lane_base + 3, if_name)); 1368 } 1369 if (err_count_l0 || err_count_l1 || err_count_l2 || err_count_l3) prbs_pass = 0; 1370 } 1371 if(prbs_pass) { 1372 LOG_WARN(BSL_LS_SOC_ESM, 1373 (BSL_META_U(unit, 1374 "\tPRBS OK \n"))); 1375 } 1376 _SHR_RETURN(SOC_E_NONE); 1377 } 1378 1379 1380 1381 STATIC int 1382 wcl_chk_rxlane_lock(int unit) 1383 { 1384 static const soc_field_t flds[] = { 1385 RXSEQDONE1G_4_3f, 1386 RXSEQDONE1G_4_2f, 1387 RXSEQDONE1G_4_1f, 1388 RXSEQDONE1G_4_0f, 1389 RXSEQDONE1G_2_3f, 1390 RXSEQDONE1G_2_2f, 1391 RXSEQDONE1G_2_1f, 1392 RXSEQDONE1G_2_0f, 1393 RXSEQDONE1G_0_3f, 1394 RXSEQDONE1G_0_2f, 1395 RXSEQDONE1G_0_1f, 1396 RXSEQDONE1G_0_0f 1397 }; 1398 1399 uint32 wcl_cur_sts_buf; 1400 unsigned i; 1401 1402 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, WCL_CUR_STSr, 0, 0, &wcl_cur_sts_buf)); 1403 for (i = 0; i < COUNTOF(flds); ++i) { 1404 if (soc_reg_field_get(unit, WCL_CUR_STSr, wcl_cur_sts_buf, flds[i]) == 0) { 1405 return (SOC_E_BUSY); 1406 } 1407 } 1408 1409 return (SOC_E_NONE); 1410 } 1411 1412 1413 STATIC int 1414 wcl_poll_rxlane_lock(int unit) 1415 { 1416 unsigned n; 1417 1418 for (n = 1000; n; --n) { 1419 int errcode = wcl_chk_rxlane_lock(unit); 1420 1421 if (errcode == SOC_E_BUSY) { 1422 continue; 1423 } 1424 1425 _SHR_RETURN(errcode); 1426 } 1427 1428 _SHR_RETURN(SOC_E_TIMEOUT); 1429 } 1430 1431 1432 STATIC int 1433 ilamac_chk_rx_intf_state0(int unit) 1434 { 1435 static const struct { 1436 soc_field_t fld; 1437 unsigned exp_val; 1438 } flds[] = { 1439 { XON_TX_CH0f, 1 }, 1440 { RX_ALIGNEDf, 1 }, 1441 { RX_MISALIGNEDf, 0 }, 1442 { RX_ALIGNED_ERRf, 0 }, 1443 { RX_WORD_SYNCf, 0xfff }, 1444 { RX_SYNCEDf, 0xfff } 1445 }; 1446 1447 uint32 ilamac_rx_intf_state0_buf; 1448 unsigned i; 1449 1450 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, ILAMAC_RX_INTF_STATE0r, 0, 0, &ilamac_rx_intf_state0_buf)); 1451 for (i = 0; i < COUNTOF(flds); ++i) { 1452 if (soc_reg_field_get(unit, ILAMAC_RX_INTF_STATE0r, ilamac_rx_intf_state0_buf, flds[i].fld) != flds[i].exp_val) { 1453 return (SOC_E_BUSY); 1454 } 1455 } 1456 1457 return (SOC_E_NONE); 1458 } 1459 1460 1461 STATIC int 1462 ilamac_poll_rx_intf_state0(int unit) 1463 { 1464 unsigned n; 1465 1466 for (n = 60; n; --n) { 1467 int errcode = ilamac_chk_rx_intf_state0(unit); 1468 1469 if (errcode == SOC_E_BUSY) { 1470 sal_usleep(1000); /* Wait 1 ms */ 1471 continue; 1472 } 1473 1474 _SHR_RETURN(errcode); 1475 } 1476 1477 _SHR_RETURN(SOC_E_TIMEOUT); 1478 } 1479 1480 1481 STATIC int 1482 ilamac_chk_rx_intf_state1(int unit) 1483 { 1484 uint32 ilamac_rx_intf_state1_buf; 1485 1486 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, ILAMAC_RX_INTF_STATE1r, 0, 0, &ilamac_rx_intf_state1_buf)); 1487 _SHR_RETURN(ilamac_rx_intf_state1_buf == 0 ? SOC_E_NONE : SOC_E_FAIL); 1488 } 1489 1490 1491 STATIC int 1492 ilamac_chk_tx_intf_state(int unit) 1493 { 1494 static const struct { 1495 soc_field_t fld; 1496 unsigned exp_val; 1497 } flds[] = { 1498 { TX_OVERFLOW_ERRf, 0 }, 1499 { TX_UNDERFLOW_ERRf, 0 }, 1500 { TX_BURST_ERRf, 0 }, 1501 { TX_OVFOUTf, 0 }, 1502 { TX_RDYOUTf, 1 } 1503 }; 1504 1505 uint32 ilamac_tx_intf_state_buf; 1506 unsigned i; 1507 1508 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, ILAMAC_TX_INTF_STATEr, 0, 0, &ilamac_tx_intf_state_buf)); 1509 for (i = 0; i < COUNTOF(flds); ++i) { 1510 if (soc_reg_field_get(unit, ILAMAC_TX_INTF_STATEr, ilamac_tx_intf_state_buf, flds[i].fld) != flds[i].exp_val) { 1511 _SHR_RETURN(SOC_E_FAIL); 1512 } 1513 } 1514 1515 _SHR_RETURN(SOC_E_NONE); 1516 } 1517 1518 1519 STATIC int 1520 nl_mdio_clr_csm_status_regs(int unit, unsigned mdio_portid, uint8 log) 1521 { 1522 static const uint16 mdio_regs[] = { 1523 0x8180, 1524 0x8183, 1525 0x8184, 1526 0x8185, 1527 0x8186, 1528 0x8187, 1529 0x8188, 1530 0x8189, 1531 0x818a 1532 }; 1533 1534 const unsigned mdio_dev_id = 1; 1535 1536 unsigned i; 1537 1538 uint16 dummy; 1539 1540 for (i = 0; i < COUNTOF(mdio_regs); ++i) { 1541 dummy = 0; 1542 1543 SOC_IF_ERROR_RETURN( 1544 nl_mdio_read(unit, mdio_portid, mdio_dev_id, mdio_regs[i], &dummy)); 1545 /* Log incase of any error */ 1546 if (dummy && log) { 1547 LOG_ERROR(BSL_LS_SOC_ESM, 1548 (BSL_META_U(unit, 1549 "NL11K MDIO [0x%x] error [0x%x] on " 1550 "portid %d on unit %d.\n"), 1551 mdio_regs[i], 1552 dummy, mdio_portid, unit)); 1553 1554 } 1555 } 1556 1557 _SHR_RETURN(SOC_E_NONE); 1558 } 1559 1560 1561 STATIC int 1562 nl_mdio_chk_csm_status_regs(int unit, unsigned mdio_portid, unsigned chk_crx) 1563 { 1564 static const struct { 1565 uint8 crxf; 1566 uint16 reg_addr; 1567 uint16 exp_val; 1568 } regvals[] = { 1569 { 0, 0x8180, 0 }, 1570 { 0, 0x8184, 0 }, 1571 { 1, 0x8185, 0 }, 1572 { 0, 0x8186, 0 }, 1573 { 0, 0x8187, 0 }, 1574 { 1, 0x8188, 0 }, 1575 { 0, 0x8189, 0 }, 1576 { 0, 0x818a, 0 } 1577 }; 1578 1579 const unsigned mdio_dev_id = 1; 1580 1581 unsigned i; 1582 uint16 regval; 1583 1584 for (i = 0; i < COUNTOF(regvals); ++i) { 1585 if (regvals[i].crxf && !chk_crx) { 1586 continue; 1587 } 1588 1589 /* Erratum: CRC24 error register crx_idle_crc24_err (0x8185) may increament 1590 even when no CRC24 error is detected. So, ignoring 0x8185 register. Real 1591 CRC24 errors are detected and handled as expected */ 1592 if (regvals[i].reg_addr == 0x8185) { 1593 continue; 1594 } 1595 1596 SOC_IF_ERROR_RETURN(nl_mdio_read(unit, mdio_portid, mdio_dev_id, regvals[i].reg_addr, ®val)); 1597 if (regval != regvals[i].exp_val) { 1598 _SHR_RETURN(SOC_E_FAIL); 1599 } 1600 } 1601 1602 SOC_IF_ERROR_RETURN(nl_mdio_read(unit, mdio_portid, mdio_dev_id, 0x8183, ®val)); 1603 if (regval != (chk_crx ? 0xf : 0xe)) { 1604 _SHR_RETURN(SOC_E_FAIL); 1605 } 1606 1607 _SHR_RETURN(SOC_E_NONE); 1608 } 1609 1610 1611 STATIC int 1612 nl_mdio_chk_csm_error_counters(int unit, unsigned mdio_portid, unsigned chk_crx) 1613 { 1614 static const uint16 regaddrs[] = { 1615 0x8203, 1616 0x8204, 1617 0x8205, 1618 0x8284, 1619 0x8285, 1620 0x8288, 1621 0x8289, 1622 0x828a, 1623 0x828b, 1624 0x8290, 1625 0x8291, 1626 0x8292, 1627 0x8293 1628 }; 1629 1630 const unsigned mdio_dev_id = 1; 1631 1632 unsigned i; 1633 uint16 regval; 1634 1635 for (i = 0; i < COUNTOF(regaddrs); ++i) { 1636 /* Erratum: CRC24 error register rx_nmac_csm_cres_crc_err (0x8292, 0x8293) may 1637 increament even when no CRC24 error is detected. So, ignoring 0x8292 and 0x8293 1638 registers. Real CRC24 errors are detected and handled as expected */ 1639 if (regaddrs[i] == 0x8292 || regaddrs[i] == 0x8293) { 1640 continue; 1641 } 1642 1643 SOC_IF_ERROR_RETURN(nl_mdio_read(unit, mdio_portid, mdio_dev_id, regaddrs[i], ®val)); 1644 if (regval != 0) { 1645 _SHR_RETURN(SOC_E_FAIL); 1646 } 1647 } 1648 1649 _SHR_RETURN(SOC_E_NONE); 1650 } 1651 1652 1653 STATIC int 1654 nl_mdio_chk_pcs_error_status(int unit, unsigned mdio_portid, unsigned chk_crx) 1655 { 1656 const unsigned min_mdio_dev_id = 2; 1657 const unsigned max_mdio_dev_id = chk_crx ? 10 : 7; 1658 const unsigned min_mdio_addr = 0x8300; 1659 const unsigned max_mdio_addr = 0x8308; 1660 1661 unsigned errcnt = 0; 1662 unsigned mdio_dev_id, mdio_addr; 1663 uint16 exp_val, obs_val; 1664 unsigned int nl_16lane_mode = 0; 1665 1666 1667 if (((soc_tcam_info_t *) SOC_CONTROL(unit)->tcam_info)->num_tcams == 2) { 1668 nl_16lane_mode = 1; 1669 } 1670 1671 for (mdio_dev_id = min_mdio_dev_id; mdio_dev_id <= max_mdio_dev_id; ++mdio_dev_id) { 1672 for (mdio_addr = min_mdio_addr; mdio_addr <= max_mdio_addr; ++mdio_addr) { 1673 exp_val = mdio_addr == 0x8300 ? 0xff0 : 0; 1674 if (nl_16lane_mode) { 1675 /* mdio_dev_id - 6,7 are for NL_RX_LANES 16-19, 20-23 respectively - not needed for 16 req lane config*/ 1676 1677 if ((mdio_dev_id == 6) || (mdio_dev_id == 7)) { 1678 exp_val = 0; 1679 } 1680 } 1681 SOC_IF_ERROR_RETURN(nl_mdio_read(unit, mdio_portid, mdio_dev_id, mdio_addr, &obs_val)); 1682 if (obs_val != exp_val) { 1683 ++errcnt; 1684 } 1685 } 1686 } 1687 1688 _SHR_RETURN(errcnt ? SOC_E_FAIL : SOC_E_NONE); 1689 } 1690 1691 1692 STATIC int 1693 nl_mdio_chk_pcs_error_counters(int unit, unsigned mdio_portid, unsigned chk_crx) 1694 { 1695 const unsigned min_mdio_dev_id = 2, 1696 max_mdio_dev_id = chk_crx ? 10 : 7, 1697 min_mdio_addr = 0x8380, 1698 max_mdio_addr = 0x83a7; 1699 1700 int errcode = SOC_E_NONE; 1701 unsigned mdio_dev_id, mdio_addr; 1702 1703 for (mdio_dev_id = min_mdio_dev_id; mdio_dev_id <= max_mdio_dev_id; ++mdio_dev_id) { 1704 for (mdio_addr = min_mdio_addr; mdio_addr <= max_mdio_addr; ++mdio_addr) { 1705 uint16 regval; 1706 1707 SOC_IF_ERROR_RETURN(nl_mdio_read(unit, mdio_portid, mdio_dev_id, mdio_addr, ®val)); 1708 if (regval != 0) { 1709 errcode = SOC_E_FAIL; 1710 } 1711 } 1712 } 1713 1714 if (SOC_FAILURE(errcode) && mdio_portid == 2) { 1715 1716 1717 _SHR_RETURN(SOC_E_NONE); 1718 } 1719 1720 _SHR_RETURN(errcode); 1721 } 1722 1723 1724 STATIC int 1725 chk_fifos(int unit) 1726 { 1727 unsigned errcnt = 0; 1728 1729 { 1730 uint32 esm_et_rsp_fifo_status_buf; 1731 1732 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, ESM_ET_RSP_FIFO_STATUSr, 0, 0, &esm_et_rsp_fifo_status_buf)); 1733 if (soc_reg_field_get(unit, ESM_ET_RSP_FIFO_STATUSr, esm_et_rsp_fifo_status_buf, WRITE_POINTERf) != soc_reg_field_get(unit, ESM_ET_RSP_FIFO_STATUSr, esm_et_rsp_fifo_status_buf, READ_POINTERf)) { 1734 ++errcnt; 1735 } 1736 if (!soc_reg_field_get(unit, ESM_ET_RSP_FIFO_STATUSr, esm_et_rsp_fifo_status_buf, EMPTYf)) { 1737 ++errcnt; 1738 } 1739 if (soc_reg_field_get(unit, ESM_ET_RSP_FIFO_STATUSr, esm_et_rsp_fifo_status_buf, FULLf)) { 1740 ++errcnt; 1741 } 1742 } 1743 1744 { 1745 uint32 esm_adm_ctrl_fifo_status_buf; 1746 1747 1748 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, ESM_ADM_CTRL_FIFO_STATUSr, 0, 0, &esm_adm_ctrl_fifo_status_buf)); 1749 if (soc_reg_field_get(unit, ESM_ADM_CTRL_FIFO_STATUSr, esm_adm_ctrl_fifo_status_buf, WRITE_POINTERf) != soc_reg_field_get(unit, ESM_ADM_CTRL_FIFO_STATUSr, esm_adm_ctrl_fifo_status_buf, READ_POINTERf)) { 1750 ++errcnt; 1751 } 1752 if (!soc_reg_field_get(unit, ESM_ADM_CTRL_FIFO_STATUSr, esm_adm_ctrl_fifo_status_buf, EMPTYf)) { 1753 ++errcnt; 1754 } 1755 if (soc_reg_field_get(unit, ESM_ADM_CTRL_FIFO_STATUSr, esm_adm_ctrl_fifo_status_buf, FULLf)) { 1756 ++errcnt; 1757 } 1758 1759 } 1760 1761 { 1762 uint32 esm_max_latency_recorded_buf; 1763 1764 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, ESM_MAX_LATENCY_RECORDEDr, 0, 0, &esm_max_latency_recorded_buf)); 1765 if (soc_reg_field_get(unit, ESM_MAX_LATENCY_RECORDEDr, esm_max_latency_recorded_buf, MAX_LATENCYf) > ESMIF_ALLOWED_FIFO_DEPTH) { 1766 ++errcnt; 1767 } 1768 } 1769 1770 { 1771 uint64 etu_tx_req_fifo_sts_buf; 1772 1773 SOC_IF_ERROR_RETURN(soc_reg64_get(unit, ETU_TX_REQ_FIFO_STSr, 0, 0, &etu_tx_req_fifo_sts_buf)); 1774 if (soc_reg64_field32_get(unit, ETU_TX_REQ_FIFO_STSr, etu_tx_req_fifo_sts_buf, WPTf) != 1775 soc_reg64_field32_get(unit, ETU_TX_REQ_FIFO_STSr, etu_tx_req_fifo_sts_buf, RPTf)) { 1776 ++errcnt; 1777 } 1778 if (!soc_reg64_field32_get(unit, ETU_TX_REQ_FIFO_STSr, etu_tx_req_fifo_sts_buf, EMPTYf)) { 1779 ++errcnt; 1780 } 1781 if (soc_reg64_field32_get(unit, ETU_TX_REQ_FIFO_STSr, etu_tx_req_fifo_sts_buf, FULLf)) { 1782 ++errcnt; 1783 } 1784 if (soc_reg64_field32_get(unit, ETU_TX_REQ_FIFO_STSr, etu_tx_req_fifo_sts_buf, EARLY_FULLf)) { 1785 ++errcnt; 1786 } 1787 if (soc_reg64_field32_get(unit, ETU_TX_REQ_FIFO_STSr, etu_tx_req_fifo_sts_buf, GTE_CP_ACC_THRf) != 0) { 1788 ++errcnt; 1789 } 1790 } 1791 1792 { 1793 uint32 etu_tx_pipe_ctl_fifo_sts_buf; 1794 1795 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, ETU_TX_PIPE_CTL_FIFO_STSr, 0, 0, &etu_tx_pipe_ctl_fifo_sts_buf)); 1796 if (soc_reg_field_get(unit, ETU_TX_PIPE_CTL_FIFO_STSr, etu_tx_pipe_ctl_fifo_sts_buf, WPTf) != soc_reg_field_get(unit, ETU_TX_PIPE_CTL_FIFO_STSr, etu_tx_pipe_ctl_fifo_sts_buf, RPTf)) { 1797 ++errcnt; 1798 } 1799 if (!soc_reg_field_get(unit, ETU_TX_PIPE_CTL_FIFO_STSr, etu_tx_pipe_ctl_fifo_sts_buf, EMPTYf)) { 1800 ++errcnt; 1801 } 1802 if (soc_reg_field_get(unit, ETU_TX_PIPE_CTL_FIFO_STSr, etu_tx_pipe_ctl_fifo_sts_buf, EARLY_FULLf)) { 1803 ++errcnt; 1804 } 1805 } 1806 1807 { 1808 uint32 etu_rx_rsp_fifo_sts_buf; 1809 1810 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, ETU_RX_RSP_FIFO_STSr, 0, 0, &etu_rx_rsp_fifo_sts_buf)); 1811 if (soc_reg_field_get(unit, ETU_RX_RSP_FIFO_STSr, etu_rx_rsp_fifo_sts_buf, WPTf) != soc_reg_field_get(unit, ETU_RX_RSP_FIFO_STSr, etu_rx_rsp_fifo_sts_buf, RPTf)) { 1812 ++errcnt; 1813 } 1814 if (!soc_reg_field_get(unit, ETU_RX_RSP_FIFO_STSr, etu_rx_rsp_fifo_sts_buf, EMPTYf)) { 1815 ++errcnt; 1816 } 1817 if (soc_reg_field_get(unit, ETU_RX_RSP_FIFO_STSr, etu_rx_rsp_fifo_sts_buf, FULLf)) { 1818 ++errcnt; 1819 } 1820 if (!soc_reg_field_get(unit, ETU_RX_RSP_FIFO_STSr, etu_rx_rsp_fifo_sts_buf, XON_RXf)) { 1821 ++errcnt; 1822 } 1823 } 1824 1825 _SHR_RETURN(errcnt ? SOC_E_FAIL : SOC_E_NONE); 1826 } 1827 1828 1829 STATIC int 1830 chk_etu_counters(int unit) 1831 { 1832 unsigned errcnt = 0; 1833 1834 { 1835 uint32 etu_dbg_ipipe_req_rsp_count_buf; 1836 1837 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, ETU_DBG_IPIPE_REQ_RSP_COUNTr, 0, 0, &etu_dbg_ipipe_req_rsp_count_buf)); 1838 if (soc_reg_field_get(unit, ETU_DBG_IPIPE_REQ_RSP_COUNTr, etu_dbg_ipipe_req_rsp_count_buf, RSP_COUNTf) 1839 != soc_reg_field_get(unit, ETU_DBG_IPIPE_REQ_RSP_COUNTr, etu_dbg_ipipe_req_rsp_count_buf, REQ_COUNTf) 1840 ) { 1841 ++errcnt; 1842 } 1843 } 1844 1845 { 1846 uint32 etu_dbg_ipipe_err_rsp_count_buf; 1847 1848 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, ETU_DBG_IPIPE_ERR_RSP_COUNTr, 0, 0, &etu_dbg_ipipe_err_rsp_count_buf)); 1849 if (soc_reg_field_get(unit, ETU_DBG_IPIPE_ERR_RSP_COUNTr, etu_dbg_ipipe_err_rsp_count_buf, ERR_RSP_COUNTf) != 0) { 1850 ++errcnt; 1851 } 1852 } 1853 1854 { 1855 uint64 ilamac_tx_packets_count_buf, ilamac_rx_packets_count_buf; 1856 uint64 tx_cnt, rx_cnt; 1857 1858 SOC_IF_ERROR_RETURN(soc_reg64_get(unit, ILAMAC_RX_PACKETS_COUNTr, 0, 0, &ilamac_rx_packets_count_buf)); 1859 SOC_IF_ERROR_RETURN(soc_reg64_get(unit, ILAMAC_TX_PACKETS_COUNTr, 0, 0, &ilamac_tx_packets_count_buf)); 1860 rx_cnt = soc_reg64_field_get(unit, ILAMAC_RX_PACKETS_COUNTr, ilamac_rx_packets_count_buf, COUNTf); 1861 tx_cnt = soc_reg64_field_get(unit, ILAMAC_TX_PACKETS_COUNTr, ilamac_tx_packets_count_buf, COUNTf); 1862 if (COMPILER_64_NE(rx_cnt, tx_cnt)) { 1863 ++errcnt; 1864 } 1865 } 1866 1867 { 1868 uint32 ilamac_debug_count_buf; 1869 1870 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, ILAMAC_DEBUG_COUNTr, 0, 0, &ilamac_debug_count_buf)); 1871 if (soc_reg_field_get(unit, ILAMAC_DEBUG_COUNTr, ilamac_debug_count_buf, XOFF_TX_CH0_COUNTf) != 0) { 1872 ++errcnt; 1873 } 1874 if (soc_reg_field_get(unit, ILAMAC_DEBUG_COUNTr, ilamac_debug_count_buf, TX_RDYOUT_COUNTf) != 0) { 1875 ++errcnt; 1876 } 1877 } 1878 1879 { 1880 static const soc_reg_t regs[] = { 1881 ILAMAC_RX_WORD_SYNC_ERRORS_COUNTr, 1882 ILAMAC_RX_FRAMING_ERRORS_COUNTr, 1883 ILAMAC_RX_BAD_TYPE_ERRORS_COUNTr, 1884 ILAMAC_RX_DESCRAM_ERRORS_COUNTr, 1885 ILAMAC_RX_ALIGNMENT_ERRORS_COUNTr, 1886 ILAMAC_RX_ALIGNMENT_FAILURES_ERRORS_COUNTr, 1887 ILAMAC_RX_CRC_ERRORS_COUNTr, 1888 ILAMAC_RX_BURSTMAX_ERRORS_COUNTr, 1889 ILAMAC_RX_LANE_CRC_ERRORS_COUNTr, 1890 ILAMAC_RX_BAD_PACKETS_COUNTr, 1891 WCL_RX_LOST_LOCK_COUNTr 1892 }; 1893 1894 unsigned i; 1895 1896 for (i = 0; i < COUNTOF(regs); ++i) { 1897 unsigned rx_lane; 1898 1899 for (rx_lane = 0; rx_lane < NL_NUM_RSP_LANES; ++rx_lane) { 1900 uint32 regbuf; 1901 1902 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, regs[i], 0, rx_lane, ®buf)); 1903 if (soc_reg_field_get(unit, regs[i], regbuf, CMSBf) != 0 1904 || soc_reg_field_get(unit, regs[i], regbuf, COUNTf) != 0 1905 ) { 1906 ++errcnt; 1907 } 1908 } 1909 } 1910 } 1911 1912 { 1913 uint32 etu_dbg_sm_buf; 1914 1915 SOC_IF_ERROR_RETURN(READ_ETU_DBG_SMr(unit, &etu_dbg_sm_buf)); 1916 if (etu_dbg_sm_buf != 0) { 1917 ++errcnt; 1918 } 1919 } 1920 1921 _SHR_RETURN(errcnt ? SOC_E_FAIL : SOC_E_NONE); 1922 } 1923 1924 1925 STATIC int 1926 chk_reg_flds_w_mask(int unit, 1927 soc_reg_t reg, 1928 uint32 intr_mask, 1929 const soc_field_t *flds, 1930 unsigned nflds 1931 ) 1932 { 1933 uint32 regbuf; 1934 unsigned i; 1935 1936 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, reg, 0, 0, ®buf)); 1937 for (i = 0; i < nflds; ++i) { 1938 if ((~soc_reg_field_get(unit, reg, intr_mask, flds[i]) 1939 & soc_reg_field_get(unit, reg, regbuf, flds[i]) 1940 ) 1941 != 0 1942 ) { 1943 _SHR_RETURN(SOC_E_FAIL); 1944 } 1945 } 1946 1947 _SHR_RETURN(SOC_E_NONE); 1948 } 1949 1950 1951 STATIC int 1952 chk_esmif_intr_status(int unit, uint32 intr_mask) 1953 { 1954 static const soc_field_t flds[] = { 1955 DROP_COUNT_MSBf, 1956 CNP_SEARCH_REQ_COUNT_MSBf, 1957 SOP_DROPf, 1958 XOFF_AXP_OVERSUBSf, 1959 MANDATORY_DENYf, 1960 DROP_ALLf, 1961 OPT_REQ_TRICKLEDf, 1962 OPTIONAL_DENYf, 1963 DROP_OPTIONALf, 1964 ET_RSP_ERRf, 1965 CNP_SEARCH_REQf, 1966 ET_REQ_FIFO_FULL_DENYf, 1967 ET_REQ_FIFO_FULLf, 1968 ADM_CTRL_FIFO_FULL_DENYf, 1969 ADM_CTRL_FIFO_FULLf, 1970 ET_RSP_FIFO_FULLf, 1971 CBA_MISMATCHf, 1972 ADM_CTRL_FIFO_UNDERFLOWf, 1973 ET_RSP_FIFO_UNDERFLOWf, 1974 ET_RSP_FIFO_OVERFLOWf 1975 }; 1976 1977 _SHR_RETURN(chk_reg_flds_w_mask(unit, 1978 ESM_EVENT_ERR_STATUS_INTRr, 1979 intr_mask, 1980 flds, 1981 COUNTOF(flds) 1982 ) 1983 ); 1984 } 1985 1986 STATIC int nl_chk_err_status_reg(int unit, unsigned dev_id); 1987 1988 STATIC int 1989 chk_etu_global_intr_sts(int unit, uint32 intr_mask, unsigned num_nl) 1990 { 1991 static const soc_field_t flds[] = { 1992 ILAMAC_RX_INTF_INTR1f, 1993 ILAMAC_RX_INTF_INTR0f, 1994 ILAMAC_RX_LANE_INTR3f, 1995 ILAMAC_RX_LANE_INTR2f, 1996 ILAMAC_RX_LANE_INTR1f, 1997 ILAMAC_RX_LANE_INTR0f, 1998 ILAMAC_TX_INTRf, 1999 RX_RSP_FIFO_INTRf, 2000 TX_PIPE_CTL_FIFO_INTRf, 2001 TX_REQ_FIFO_INTRf, 2002 WCL_INTRf, 2003 RSVDf, 2004 EXT_L2_REQ_LTH_ERRf, 2005 TWO_MISSING_PKTf, 2006 INT_MEM_RST_DONEf, 2007 TX_RAW_REQ_DONEf, 2008 RRFE_WAIT_PENDING0f, 2009 RRFE_WAIT_FULLf, 2010 PP_XLAT1_PERRf, 2011 PP_XLAT0_PERRf, 2012 EXT_L2_CMD_ERRf, 2013 SBUS_CMD_ERRf 2014 }; 2015 2016 int errcode = SOC_E_NONE; 2017 uint32 etu_global_intr_sts_buf; 2018 unsigned i, dev_id; 2019 2020 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, ETU_GLOBAL_INTR_STSr, 0, 0, &etu_global_intr_sts_buf)); 2021 2022 for (i = 0; i < COUNTOF(flds); ++i) { 2023 if ((~soc_reg_field_get(unit, ETU_GLOBAL_INTR_STSr, intr_mask, flds[i]) 2024 & soc_reg_field_get(unit, ETU_GLOBAL_INTR_STSr, etu_global_intr_sts_buf, flds[i]) 2025 ) 2026 != 0 2027 ) { 2028 errcode = SOC_E_FAIL; 2029 } 2030 } 2031 2032 if ((~soc_reg_field_get(unit, ETU_GLOBAL_INTR_STSr, intr_mask, EXT_TCAM_INTR0f) 2033 & soc_reg_field_get(unit, ETU_GLOBAL_INTR_STSr, etu_global_intr_sts_buf, EXT_TCAM_INTR0f) 2034 ) 2035 != 0 2036 || (~soc_reg_field_get(unit, ETU_GLOBAL_INTR_STSr, intr_mask, EXT_TCAM_INTR1f) 2037 & soc_reg_field_get(unit, ETU_GLOBAL_INTR_STSr, etu_global_intr_sts_buf, EXT_TCAM_INTR1f) 2038 ) 2039 != 0 2040 || (~soc_reg_field_get(unit, ETU_GLOBAL_INTR_STSr, intr_mask, RX_CW_ERS1f) 2041 & soc_reg_field_get(unit, ETU_GLOBAL_INTR_STSr, etu_global_intr_sts_buf, RX_CW_ERS1f) 2042 ) 2043 != 0 2044 ) { 2045 for (dev_id = 0; dev_id < num_nl; ++dev_id) { 2046 if (SOC_FAILURE(nl_chk_err_status_reg(unit, dev_id))) { 2047 errcode = SOC_E_FAIL; 2048 } 2049 } 2050 } 2051 2052 if ((~soc_reg_field_get(unit, ETU_GLOBAL_INTR_STSr, intr_mask, RX_CW_ERRf) 2053 & soc_reg_field_get(unit, ETU_GLOBAL_INTR_STSr, etu_global_intr_sts_buf, RX_CW_ERRf) 2054 ) 2055 != 0 2056 ) { 2057 /* Received packet error - must read: 2058 ETU_RX_CW_ERR_INFO1, ETU_RX_CW_ERR_INFO2, ETU_RX_CW_ERR_CHANOUT, 2059 ETU_RX_CW_ERR_DW0_LO, ETU_RX_CW_ERR_DW0_HI, ETU_RX_CW_ERR_DW1_LO, 2060 ETU_RX_CW_ERR_DW1_HI registers 2061 */ 2062 2063 uint32 dummy; 2064 uint64 dummy64; 2065 2066 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, ETU_RX_CW_ERR_INFO1r, 0, 0, &dummy)); 2067 SOC_IF_ERROR_RETURN(soc_reg_get(unit, ETU_RX_CW_ERR_INFO2r, 0, 0, &dummy64)); 2068 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, ETU_RX_CW_ERR_CHANOUTr, 0, 0, &dummy)); 2069 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, ETU_RX_CW_ERR_DW0_LOr, 0, 0, &dummy)); 2070 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, ETU_RX_CW_ERR_DW0_HIr, 0, 0, &dummy)); 2071 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, ETU_RX_CW_ERR_DW1_LOr, 0, 0, &dummy)); 2072 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, ETU_RX_CW_ERR_DW1_HIr, 0, 0, &dummy)); 2073 2074 errcode = SOC_E_FAIL; 2075 } 2076 2077 if ((~soc_reg_field_get(unit, ETU_GLOBAL_INTR_STSr, intr_mask, RX_CW_ERS0f) 2078 & soc_reg_field_get(unit, ETU_GLOBAL_INTR_STSr, etu_global_intr_sts_buf, RX_CW_ERS0f) 2079 ) 2080 != 0 2081 ) { 2082 uint32 dummy; 2083 2084 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, ETU_RX_ERS0_CHANOUTr, 0, 0, &dummy)); 2085 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, ETU_RX_ERS0_DW0_HIr, 0, 0, &dummy)); 2086 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, ETU_RX_ERS0_DW0_LOr, 0, 0, &dummy)); 2087 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, ETU_RX_ERS0_DW1_HIr, 0, 0, &dummy)); 2088 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, ETU_RX_ERS0_DW1_LOr, 0, 0, &dummy)); 2089 2090 errcode = SOC_E_FAIL; 2091 } 2092 2093 _SHR_RETURN(errcode); 2094 } 2095 2096 2097 STATIC int 2098 chk_ilamac_rx_intf_intr0_sts(int unit, uint32 intr_mask) 2099 { 2100 static const soc_field_t flds[] = { 2101 XOFF_TX_CH1f, 2102 XOFF_TX_CH0f, 2103 RX_ALIGNEDf, 2104 RX_MISALIGNEDf, 2105 RX_ALIGNED_ERRf, 2106 RX_WORD_SYNCf, 2107 RX_SYNCEDf 2108 }; 2109 2110 _SHR_RETURN(chk_reg_flds_w_mask(unit, 2111 ILAMAC_RX_INTF_INTR0_STSr, 2112 intr_mask, 2113 flds, 2114 COUNTOF(flds) 2115 ) 2116 ); 2117 } 2118 2119 2120 STATIC int 2121 chk_ilamac_rx_intf_intr1_sts(int unit, uint32 intr_mask) 2122 { 2123 static const soc_field_t flds[] = { 2124 RX_BURST_GT_16B_ERRf, 2125 RX_CRC24_ERRf, 2126 RX_MSOP_ERRf, 2127 RX_MEOP_ERRf, 2128 RX_OVERFLOW_ERRf, 2129 RX_BURSTMAX_ERRf, 2130 RX_BURST_ERRf 2131 }; 2132 2133 _SHR_RETURN(chk_reg_flds_w_mask(unit, 2134 ILAMAC_RX_INTF_INTR1_STSr, 2135 intr_mask, 2136 flds, 2137 COUNTOF(flds) 2138 ) 2139 ); 2140 } 2141 2142 2143 STATIC int 2144 chk_ilamac_rx_lane_intr0_sts(int unit, uint32 intr_mask) 2145 { 2146 static const soc_field_t flds[] = { 2147 RX_SYNCED_ERRf, 2148 RX_FRAMING_ERRf 2149 }; 2150 2151 _SHR_RETURN(chk_reg_flds_w_mask(unit, 2152 ILAMAC_RX_LANE_INTR0_STSr, 2153 intr_mask, 2154 flds, 2155 COUNTOF(flds) 2156 ) 2157 ); 2158 } 2159 2160 2161 STATIC int 2162 chk_ilamac_rx_lane_intr1_sts(int unit, uint32 intr_mask) 2163 { 2164 static const soc_field_t flds[] = { 2165 RX_BAD_TYPE_ERRf, 2166 RX_MF_ERRf 2167 }; 2168 2169 _SHR_RETURN(chk_reg_flds_w_mask(unit, 2170 ILAMAC_RX_LANE_INTR1_STSr, 2171 intr_mask, 2172 flds, 2173 COUNTOF(flds) 2174 ) 2175 ); 2176 } 2177 2178 2179 STATIC int 2180 chk_ilamac_rx_lane_intr2_sts(int unit, uint32 intr_mask) 2181 { 2182 static const soc_field_t flds[] = { 2183 RX_DESCRAM_ERRf, 2184 RX_MF_LEN_ERRf 2185 }; 2186 2187 _SHR_RETURN(chk_reg_flds_w_mask(unit, 2188 ILAMAC_RX_LANE_INTR2_STSr, 2189 intr_mask, 2190 flds, 2191 COUNTOF(flds) 2192 ) 2193 ); 2194 } 2195 2196 2197 STATIC int 2198 chk_ilamac_rx_lane_intr3_sts(int unit, uint32 intr_mask) 2199 { 2200 static const soc_field_t flds[] = { 2201 RX_MF_REPEAT_ERRf, 2202 RX_CRC32_ERRf 2203 }; 2204 2205 _SHR_RETURN(chk_reg_flds_w_mask(unit, 2206 ILAMAC_RX_LANE_INTR3_STSr, 2207 intr_mask, 2208 flds, 2209 COUNTOF(flds) 2210 ) 2211 ); 2212 } 2213 2214 2215 STATIC int 2216 chk_ilamac_tx_intr_sts(int unit, uint32 intr_mask) 2217 { 2218 static const soc_field_t flds[] = { 2219 TX_ERRINf, 2220 TX_OVERFLOW_ERRf, 2221 TX_UNDERFLOW_ERRf, 2222 TX_BURST_ERRf, 2223 TX_OVFOUTf, 2224 TX_RDYOUTf 2225 }; 2226 2227 _SHR_RETURN(chk_reg_flds_w_mask(unit, 2228 ILAMAC_TX_INTR_STSr, 2229 intr_mask, 2230 flds, 2231 COUNTOF(flds) 2232 ) 2233 ); 2234 } 2235 2236 2237 STATIC int 2238 chk_wcl_intr_sts(int unit, uint32 intr_mask) 2239 { 2240 static const soc_field_t flds[] = { 2241 TXPLL_LOCK_5f, 2242 TXPLL_LOCK_4f, 2243 TXPLL_LOCK_3f, 2244 TXPLL_LOCK_2f, 2245 TXPLL_LOCK_1f, 2246 TXPLL_LOCK_0f, 2247 RXSEQDONE1G_4_3f, 2248 RXSEQDONE1G_4_2f, 2249 RXSEQDONE1G_4_1f, 2250 RXSEQDONE1G_4_0f, 2251 RXSEQDONE1G_2_3f, 2252 RXSEQDONE1G_2_2f, 2253 RXSEQDONE1G_2_1f, 2254 RXSEQDONE1G_2_0f, 2255 RXSEQDONE1G_0_3f, 2256 RXSEQDONE1G_0_2f, 2257 RXSEQDONE1G_0_1f, 2258 RXSEQDONE1G_0_0f 2259 }; 2260 2261 _SHR_RETURN(chk_reg_flds_w_mask(unit, 2262 WCL_INTR_STSr, 2263 intr_mask, 2264 flds, 2265 COUNTOF(flds) 2266 ) 2267 ); 2268 } 2269 2270 2271 STATIC int 2272 chk_etu_tx_req_fifo_intr_sts(int unit, uint32 intr_mask) 2273 { 2274 static const soc_field_t flds[] = { 2275 SBUS_STALL_MAX_LATf, 2276 EXT_L2_STALL_MAX_LATf, 2277 SBUS_STALL_GTE_CP_ACC_THRf, 2278 EXT_L2_STALL_GTE_CP_ACC_THRf, 2279 UNDERFLOW_DETECTEDf, 2280 OVERFLOW_DETECTEDf, 2281 FULLf, 2282 EARLY_FULLf, 2283 DBE_EVf, 2284 SBE_EVf, 2285 DBE_ODf, 2286 SBE_ODf 2287 }; 2288 2289 _SHR_RETURN(chk_reg_flds_w_mask(unit, 2290 ETU_TX_REQ_FIFO_INTR_STSr, 2291 intr_mask, 2292 flds, 2293 COUNTOF(flds) 2294 ) 2295 ); 2296 } 2297 2298 2299 STATIC int 2300 chk_etu_tx_pipe_ctl_fifo_intr_sts(int unit, uint32 intr_mask) 2301 { 2302 static const soc_field_t flds[] = { 2303 UNDERFLOW_DETECTEDf, 2304 OVERFLOW_DETECTEDf, 2305 FULLf, 2306 EARLY_FULLf, 2307 DBEf, 2308 SBEf 2309 }; 2310 2311 _SHR_RETURN(chk_reg_flds_w_mask(unit, 2312 ETU_TX_PIPE_CTL_FIFO_INTR_STSr, 2313 intr_mask, 2314 flds, 2315 COUNTOF(flds) 2316 ) 2317 ); 2318 } 2319 2320 2321 STATIC int 2322 chk_etu_rx_rsp_fifo_intr_sts(int unit, uint32 intr_mask) 2323 { 2324 static const soc_field_t flds[] = { 2325 XOFF_RXf, 2326 UNDERFLOW_DETECTEDf, 2327 OVERFLOW_DETECTEDf, 2328 FULLf, 2329 DBE_EVf, 2330 SBE_EVf, 2331 DBE_ODf, 2332 SBE_ODf 2333 }; 2334 2335 _SHR_RETURN(chk_reg_flds_w_mask(unit, 2336 ETU_RX_RSP_FIFO_INTR_STSr, 2337 intr_mask, 2338 flds, 2339 COUNTOF(flds) 2340 ) 2341 ); 2342 } 2343 2344 2345 STATIC int 2346 chk_all_intr_sts(int unit, unsigned num_nl) 2347 { 2348 SOC_IF_ERROR_RETURN(chk_esmif_intr_status(unit, 0x800)); 2349 SOC_IF_ERROR_RETURN(chk_etu_global_intr_sts(unit, 0x600, num_nl)); 2350 SOC_IF_ERROR_RETURN(chk_ilamac_rx_intf_intr0_sts(unit, 0)); 2351 SOC_IF_ERROR_RETURN(chk_ilamac_rx_intf_intr1_sts(unit, 0)); 2352 SOC_IF_ERROR_RETURN(chk_ilamac_rx_lane_intr0_sts(unit, 0)); 2353 SOC_IF_ERROR_RETURN(chk_ilamac_rx_lane_intr1_sts(unit, 0)); 2354 SOC_IF_ERROR_RETURN(chk_ilamac_rx_lane_intr2_sts(unit, 0)); 2355 SOC_IF_ERROR_RETURN(chk_ilamac_rx_lane_intr3_sts(unit, 0)); 2356 SOC_IF_ERROR_RETURN(chk_ilamac_tx_intr_sts(unit, 1)); 2357 SOC_IF_ERROR_RETURN(chk_wcl_intr_sts(unit, 0)); 2358 SOC_IF_ERROR_RETURN(chk_etu_tx_req_fifo_intr_sts(unit, 0)); 2359 SOC_IF_ERROR_RETURN(chk_etu_tx_pipe_ctl_fifo_intr_sts(unit, 0)); 2360 SOC_IF_ERROR_RETURN(chk_etu_rx_rsp_fifo_intr_sts(unit, 0)); 2361 2362 _SHR_RETURN(SOC_E_NONE); 2363 } 2364 2365 2366 STATIC int 2367 chk_esmif_adc(int unit) 2368 { 2369 unsigned errcnt = 0; 2370 2371 { 2372 uint32 esmif_cur_pending_cost0_buf; 2373 2374 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, ESMIF_CUR_PENDING_COST0r, 0, 0, &esmif_cur_pending_cost0_buf)); 2375 if (soc_reg_field_get(unit, ESMIF_CUR_PENDING_COST0r, esmif_cur_pending_cost0_buf, COSTf) != 0) { 2376 ++errcnt; 2377 } 2378 } 2379 { 2380 uint32 esmif_cur_pending_cost1_buf; 2381 2382 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, ESMIF_CUR_PENDING_COST1r, 0, 0, &esmif_cur_pending_cost1_buf)); 2383 if (soc_reg_field_get(unit, ESMIF_CUR_PENDING_COST1r, esmif_cur_pending_cost1_buf, COSTf) != 0) { 2384 ++errcnt; 2385 } 2386 } 2387 { 2388 uint32 esmif_cur_pending_cost2_buf; 2389 2390 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, ESMIF_CUR_PENDING_COST2r, 0, 0, &esmif_cur_pending_cost2_buf)); 2391 if (soc_reg_field_get(unit, ESMIF_CUR_PENDING_COST2r, esmif_cur_pending_cost2_buf, COSTf) != 0) { 2392 ++errcnt; 2393 } 2394 } 2395 { 2396 uint32 esmif_adm_ctrl_status_buf; 2397 2398 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, ESMIF_ADM_CTRL_STATUSr, 0, 0, &esmif_adm_ctrl_status_buf)); 2399 if (soc_reg_field_get(unit, ESMIF_ADM_CTRL_STATUSr, esmif_adm_ctrl_status_buf, DROP_ALLf)) { 2400 ++errcnt; 2401 } 2402 if (soc_reg_field_get(unit, ESMIF_ADM_CTRL_STATUSr, esmif_adm_ctrl_status_buf, DROP_OPTIONALf)) { 2403 ++errcnt; 2404 } 2405 if (soc_reg_field_get(unit, ESMIF_ADM_CTRL_STATUSr, esmif_adm_ctrl_status_buf, XOFF_AXP_OVERSUBSf)) { 2406 ++errcnt; 2407 } 2408 } 2409 { 2410 uint32 esmif_cnp_search_req_count_buf; 2411 2412 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, ESMIF_CNP_SEARCH_REQ_COUNTr, 0, 0, &esmif_cnp_search_req_count_buf)); 2413 if (soc_reg_field_get(unit, ESMIF_CNP_SEARCH_REQ_COUNTr, esmif_cnp_search_req_count_buf, COUNTf) != 0) { 2414 ++errcnt; 2415 } 2416 } 2417 { 2418 uint32 esmif_drop_count_buf; 2419 2420 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, ESMIF_DROP_COUNTr, 0, 0, &esmif_drop_count_buf)); 2421 if (soc_reg_field_get(unit, ESMIF_DROP_COUNTr, esmif_drop_count_buf, COUNTf) != 0) { 2422 ++errcnt; 2423 } 2424 } 2425 { 2426 uint32 esm_max_latency_recorded_buf; 2427 2428 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, ESM_MAX_LATENCY_RECORDEDr, 0, 0, &esm_max_latency_recorded_buf)); 2429 if (soc_reg_field_get(unit, ESM_MAX_LATENCY_RECORDEDr, esm_max_latency_recorded_buf, MAX_LATENCYf) > ESMIF_ALLOWED_FIFO_DEPTH) { 2430 ++errcnt; 2431 } 2432 } 2433 2434 _SHR_RETURN(errcnt ? SOC_E_FAIL : SOC_E_NONE); 2435 } 2436 2437 STATIC int 2438 clr_etu_counters(int unit) 2439 { 2440 static const soc_reg_t regs64[] = { 2441 ILAMAC_RX_PACKETS_COUNTr, 2442 ILAMAC_RX_BYTES_COUNTr, 2443 ILAMAC_TX_PACKETS_COUNTr, 2444 ILAMAC_TX_BYTES_COUNTr 2445 }, regs[] = { 2446 ILAMAC_RX_ALIGNMENT_ERRORS_COUNTr, 2447 ILAMAC_RX_ALIGNMENT_FAILURES_ERRORS_COUNTr, 2448 ILAMAC_RX_CRC_ERRORS_COUNTr, 2449 ILAMAC_RX_BURSTMAX_ERRORS_COUNTr, 2450 ILAMAC_RX_BAD_PACKETS_COUNTr, 2451 ILAMAC_DEBUG_COUNTr, 2452 ETU_DBG_IPIPE_ERR_RSP_COUNTr, 2453 ETU_DBG_IPIPE_REQ_RSP_COUNTr 2454 }, regs_w_lanes[] = { 2455 ILAMAC_RX_WORD_SYNC_ERRORS_COUNTr, 2456 ILAMAC_RX_FRAMING_ERRORS_COUNTr, 2457 ILAMAC_RX_BAD_TYPE_ERRORS_COUNTr, 2458 ILAMAC_RX_DESCRAM_ERRORS_COUNTr, 2459 ILAMAC_RX_LANE_CRC_ERRORS_COUNTr, 2460 WCL_RX_LOST_LOCK_COUNTr 2461 }; 2462 2463 unsigned i; 2464 2465 { 2466 uint64 zero; 2467 2468 COMPILER_64_ZERO(zero); 2469 for (i = 0; i < COUNTOF(regs64); ++i) { 2470 SOC_IF_ERROR_RETURN(soc_reg64_set(unit, regs64[i], 0, 0, zero)); 2471 } 2472 } 2473 2474 for (i = 0; i < COUNTOF(regs); ++i) { 2475 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, regs[i], 0, 0, 0)); 2476 } 2477 2478 for (i = 0; i < COUNTOF(regs_w_lanes); ++i) { 2479 unsigned rx_lane; 2480 2481 for (rx_lane = 0; rx_lane < NL_NUM_RSP_LANES; ++rx_lane) { 2482 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, regs_w_lanes[i], 0, rx_lane, 0)); 2483 } 2484 } 2485 2486 _SHR_RETURN(SOC_E_NONE); 2487 } 2488 2489 2490 STATIC int 2491 clr_all_intr_sts(int unit) 2492 { 2493 static const soc_reg_t regs[] = { 2494 ESM_EVENT_ERR_STATUS_INTRr, 2495 ETU_GLOBAL_INTR_STSr, 2496 ILAMAC_RX_INTF_INTR0_STSr, 2497 ILAMAC_RX_INTF_INTR1_STSr, 2498 ILAMAC_RX_LANE_INTR0_STSr, 2499 ILAMAC_RX_LANE_INTR1_STSr, 2500 ILAMAC_RX_LANE_INTR2_STSr, 2501 ILAMAC_RX_LANE_INTR3_STSr, 2502 ILAMAC_TX_INTR_STSr, 2503 WCL_INTR_STSr, 2504 ETU_TX_REQ_FIFO_INTR_STSr, 2505 ETU_TX_PIPE_CTL_FIFO_INTR_STSr, 2506 ETU_RX_RSP_FIFO_INTR_STSr 2507 }; 2508 2509 unsigned i; 2510 2511 for (i = 0; i < COUNTOF(regs); ++i) { 2512 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, regs[i], 0, 0, 0)); 2513 } 2514 2515 _SHR_RETURN(SOC_E_NONE); 2516 } 2517 2518 2519 STATIC int 2520 clr_adc_max_logs(int unit) 2521 { 2522 SOC_IF_ERROR_RETURN(WRITE_ESMIF_CNP_SEARCH_REQ_COUNTr(unit, 0)); 2523 SOC_IF_ERROR_RETURN(WRITE_ESMIF_DROP_COUNTr(unit, 0)); 2524 2525 { 2526 uint32 esm_et_hwtl_control_buf; 2527 2528 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, ESM_ET_HWTL_CONTROLr, 0, 0, &esm_et_hwtl_control_buf)); 2529 soc_reg_field_set(unit, ESM_ET_HWTL_CONTROLr, &esm_et_hwtl_control_buf, START_HWTL_TESTf, 1); 2530 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, ESM_ET_HWTL_CONTROLr, 0, 0, esm_et_hwtl_control_buf)); 2531 soc_reg_field_set(unit, ESM_ET_HWTL_CONTROLr, &esm_et_hwtl_control_buf, START_HWTL_TESTf, 0); 2532 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, ESM_ET_HWTL_CONTROLr, 0, 0, esm_et_hwtl_control_buf)); 2533 } 2534 2535 _SHR_RETURN(SOC_E_NONE); 2536 } 2537 2538 2539 STATIC int 2540 init1(int unit, 2541 unsigned num_nl, 2542 unsigned master_wcl_num, 2543 unsigned rx_fifo_thr, 2544 unsigned tx_fifo_thr, 2545 unsigned tx_burst_short_16b 2546 ) 2547 { 2548 unsigned dev_id; 2549 unsigned int nl_16lane_mode = 0; 2550 2551 2552 if (num_nl == 2) { 2553 nl_16lane_mode = 1; 2554 } 2555 2556 SOC_IF_ERROR_RETURN(chk_esmif_init_config(unit, ESMIF_MAX_FIFO_DEPTH)); 2557 2558 { 2559 uint32 esm_misc_control_buf; 2560 2561 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, ESM_MISC_CONTROLr, 0, 0, &esm_misc_control_buf)); 2562 soc_reg_field_set(unit, ESM_MISC_CONTROLr, &esm_misc_control_buf, EXT_LOOKUP_ENABLEf, 0); 2563 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, ESM_MISC_CONTROLr, 0, 0, esm_misc_control_buf)); 2564 } 2565 2566 SOC_IF_ERROR_RETURN(dis_intr(unit)); 2567 2568 SOC_IF_ERROR_RETURN(etu_rst_nl_wcl_ilamac(unit, 9)); 2569 2570 SOC_IF_ERROR_RETURN(wcl_reset_seq(unit, master_wcl_num)); 2571 2572 { 2573 uint32 ilamac_tx_config0_buf; 2574 2575 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, ILAMAC_TX_CONFIG0r, 0, 0, &ilamac_tx_config0_buf)); 2576 soc_reg_field_set(unit, ILAMAC_TX_CONFIG0r, &ilamac_tx_config0_buf, BIT_ORDER_INVERTf, 1); 2577 soc_reg_field_set(unit, ILAMAC_TX_CONFIG0r, &ilamac_tx_config0_buf, TX_XOFF_MODEf, 0); 2578 soc_reg_field_set(unit, ILAMAC_TX_CONFIG0r, &ilamac_tx_config0_buf, TX_RLIM_ENABLEf, 0); 2579 soc_reg_field_set(unit, ILAMAC_TX_CONFIG0r, &ilamac_tx_config0_buf, TX_RDYOUT_THRESHf, 0); 2580 soc_reg_field_set(unit, ILAMAC_TX_CONFIG0r, &ilamac_tx_config0_buf, TX_DISABLE_SKIPWORDf, 0); 2581 soc_reg_field_set(unit, ILAMAC_TX_CONFIG0r, &ilamac_tx_config0_buf, TX_BURSTSHORTf, 1); 2582 soc_reg_field_set(unit, ILAMAC_TX_CONFIG0r, &ilamac_tx_config0_buf, TX_BURSTMAXf, 1); 2583 soc_reg_field_set(unit, ILAMAC_TX_CONFIG0r, &ilamac_tx_config0_buf, TX_MFRAMELEN_MINUS1f, NL_METAFRAME_LENGTH - 1); 2584 soc_reg_field_set(unit, ILAMAC_TX_CONFIG0r, &ilamac_tx_config0_buf, TX_ENABLEf, 1); 2585 soc_reg_field_set(unit, ILAMAC_TX_CONFIG0r, &ilamac_tx_config0_buf, XON_RX_CH1f, 0); 2586 soc_reg_field_set(unit, ILAMAC_TX_CONFIG0r, &ilamac_tx_config0_buf, XON_RX_CH0f, 1); 2587 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, ILAMAC_TX_CONFIG0r, 0, 0, ilamac_tx_config0_buf)); 2588 } 2589 2590 /* Allow ETU_RX_RSP_FIFO.XON_RX to go out. At this point in time, etu_rx_rsp_fifo is empty so XON_RX=1 2591 This signals NL that it is ok to send response packets 2592 We have not even checked if ilamac_rx is aligned - so why tell NL to send packets ?? 2593 It will not matter because NL is slave device - it sends response packets 2594 only if we send a request 2595 */ 2596 2597 /* Error injection fields. Some default values of non-zero - so make it 0 */ 2598 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, ILAMAC_TX_CONFIG4r, 0, 0, 0)); 2599 2600 { 2601 uint32 ilamac_tx_config2_buf; 2602 /* Set tx lanes to 16 for cascaded mode */ 2603 if (nl_16lane_mode) { 2604 /* Cascaded mode: set num lanes to 16 */ 2605 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, ILAMAC_TX_CONFIG2r, 0, 0, &ilamac_tx_config2_buf)); 2606 soc_reg_field_set(unit, ILAMAC_TX_CONFIG2r, &ilamac_tx_config2_buf, TX_LAST_LANEf, 15); 2607 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, ILAMAC_TX_CONFIG2r, 0, 0, ilamac_tx_config2_buf)); 2608 } 2609 } 2610 { 2611 uint32 ilamac_rx_config_buf; 2612 2613 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, ILAMAC_RX_CONFIGr, 0, 0, &ilamac_rx_config_buf)); 2614 soc_reg_field_set(unit, ILAMAC_RX_CONFIGr, &ilamac_rx_config_buf, BIT_ORDER_INVERTf, 1); 2615 soc_reg_field_set(unit, ILAMAC_RX_CONFIGr, &ilamac_rx_config_buf, RX_BURSTMAXf, 0); 2616 soc_reg_field_set(unit, ILAMAC_RX_CONFIGr, &ilamac_rx_config_buf, RX_MFRAMELEN_MINUS1f, NL_METAFRAME_LENGTH - 1); 2617 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, ILAMAC_RX_CONFIGr, 0, 0, ilamac_rx_config_buf)); 2618 } 2619 2620 { 2621 uint32 etu_config4_buf; 2622 2623 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, ETU_CONFIG4r, 0, 0, &etu_config4_buf)); 2624 soc_reg_field_set(unit, ETU_CONFIG4r, &etu_config4_buf, ILAMAC_TX_LBUS_RST_f, 1); 2625 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, ETU_CONFIG4r, 0, 0, etu_config4_buf)); 2626 sal_usleep(10); 2627 /* wait 10uS between de-assertion of ILAMAC_TX_LBUS_RST_ and asertion of 2628 ILAMAC_TX_SERDES_RST_ */ 2629 soc_reg_field_set(unit, ETU_CONFIG4r, &etu_config4_buf, ILAMAC_TX_SERDES_RST_f, 1); 2630 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, ETU_CONFIG4r, 0, 0, etu_config4_buf)); 2631 } 2632 2633 { 2634 uint32 etu_bist_ctl_buf; 2635 2636 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, ETU_BIST_CTLr, 0, 0, &etu_bist_ctl_buf)); 2637 soc_reg_field_set(unit, ETU_BIST_CTLr, &etu_bist_ctl_buf, ENABLEf, 0); 2638 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, ETU_BIST_CTLr, 0, 0, etu_bist_ctl_buf)); 2639 } 2640 2641 sal_usleep(1); /* wait 1uS after connecting ilamac_tx to SerDes */ 2642 2643 wcmod_esm_serdes_fifo_reset(unit); 2644 2645 /* At this point, we should be sending out idle control words to NL (which 2646 is still in reset). 2647 We can de-assert SRST_L for NL only after we are sending idle control 2648 words 2649 */ 2650 sal_usleep(SRST_L_DEASSERTION_DELAY_US); 2651 /* wait 30uS after serdes_fifo_reset and before SRST_L de-assertion 2652 * Min time for SRST_L assertion as per NL11K datasheet is 3 uS 2653 */ 2654 2655 { 2656 uint32 etu_config4_buf; 2657 2658 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, ETU_CONFIG4r, 0, 0, &etu_config4_buf)); 2659 soc_reg_field_set(unit, ETU_CONFIG4r, &etu_config4_buf, EXT_TCAM_SRST_Lf, 1); 2660 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, ETU_CONFIG4r, 0, 0, etu_config4_buf)); 2661 } 2662 2663 /* Waiting after srst_l de-assertion is not specified in NL data sheet - from Hong's tcl */ 2664 2665 sal_usleep(10); /* wait 10uS after SRST_L de-assertion */ 2666 2667 for (dev_id = 0; dev_id < num_nl; ++dev_id) { 2668 SOC_IF_ERROR_RETURN(nl_mdio_test_reg_access(unit, 2669 mdio_portid_get(unit, dev_id) 2670 ) 2671 ); 2672 } 2673 2674 SOC_IF_ERROR_RETURN(nl_mdio_init_seq(unit, num_nl, rx_fifo_thr, tx_fifo_thr, tx_burst_short_16b)); 2675 2676 for (dev_id = 0; dev_id < num_nl; ++dev_id) { 2677 uint16 dummy; 2678 2679 nl_mdio_read(unit, mdio_portid_get(unit, dev_id), 1, 0x8184, &dummy); 2680 } 2681 2682 sal_usleep(CRST_L_DEASSERTION_DELAY_US); 2683 /* wait 3000uS between SRST_L de-assertion and CRST_L de-assertion. 2684 * 10 uS above nl_mdio_test_reg, nl_mdio_init_seq, reading 2685 * of 0x8184 are already adding delay between SRST_L 2686 * de-assertion and CRST_L de-assertion. So, above delay 2687 * of 3 mSec is just as precaution. NL11K requirement is 2.5 mSec 2688 */ 2689 { 2690 uint32 etu_config4_buf; 2691 2692 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, ETU_CONFIG4r, 0, 0, &etu_config4_buf)); 2693 soc_reg_field_set(unit, ETU_CONFIG4r, &etu_config4_buf, EXT_TCAM_CRST_Lf, 1); 2694 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, ETU_CONFIG4r, 0, 0, etu_config4_buf)); 2695 } 2696 2697 SOC_IF_ERROR_RETURN(wcl_poll_rxlane_lock(unit)); 2698 2699 { 2700 uint32 etu_config4_buf; 2701 2702 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, ETU_CONFIG4r, 0, 0, &etu_config4_buf)); 2703 /* First de-asserting lbus_rst */ 2704 soc_reg_field_set(unit, ETU_CONFIG4r, &etu_config4_buf, ILAMAC_RX_LBUS_RST_f, 1); 2705 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, ETU_CONFIG4r, 0, 0, etu_config4_buf)); 2706 sal_usleep(10); 2707 /* wait 10uS between de-assertion of ILAMAC_RX_LBUS_RST_ and asertion of 2708 ILAMAC_RX_SERDES_RESET_ */ 2709 soc_reg_field_set(unit, ETU_CONFIG4r, &etu_config4_buf, ILAMAC_RX_SERDES_RST_f, 0xfff); 2710 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, ETU_CONFIG4r, 0, 0, etu_config4_buf)); 2711 } 2712 2713 SOC_IF_ERROR_RETURN(ilamac_poll_rx_intf_state0(unit)); 2714 SOC_IF_ERROR_RETURN(ilamac_chk_rx_intf_state1(unit)); 2715 SOC_IF_ERROR_RETURN(ilamac_chk_tx_intf_state(unit)); 2716 2717 { 2718 const unsigned mdio_dev_id = 1; 2719 2720 unsigned dev_id; 2721 2722 for (dev_id = 0; dev_id < num_nl; ++dev_id) { 2723 unsigned mdio_portid = mdio_portid_get(unit, dev_id); 2724 2725 /* Toggle "Reset RX Satellite Sticky Registers" bit */ 2726 SOC_IF_ERROR_RETURN(nl_mdio_write(unit, 2727 mdio_portid, 2728 mdio_dev_id, 2729 0x811b, 2730 0x40, 2731 1 2732 ) 2733 ); 2734 SOC_IF_ERROR_RETURN(nl_mdio_write(unit, 2735 mdio_portid, 2736 mdio_dev_id, 2737 0x811b, 2738 0, 2739 1 2740 ) 2741 ); 2742 } 2743 2744 for (dev_id = 0; dev_id < num_nl; ++dev_id) { 2745 unsigned chk_crx = (dev_id != 0); 2746 unsigned mdio_portid = mdio_portid_get(unit, dev_id); 2747 2748 SOC_IF_ERROR_RETURN(nl_mdio_clr_csm_status_regs(unit, mdio_portid, 0)); 2749 SOC_IF_ERROR_RETURN(nl_mdio_chk_csm_status_regs(unit, mdio_portid, chk_crx)); 2750 SOC_IF_ERROR_RETURN(nl_mdio_chk_csm_error_counters(unit, mdio_portid, chk_crx)); 2751 SOC_IF_ERROR_RETURN(nl_mdio_chk_pcs_error_status(unit, mdio_portid, chk_crx)); 2752 SOC_IF_ERROR_RETURN(nl_mdio_chk_pcs_error_counters(unit, mdio_portid, chk_crx)); 2753 } 2754 } 2755 2756 chk_fifos(unit); 2757 chk_etu_counters(unit); 2758 chk_all_intr_sts(unit, num_nl); 2759 chk_esmif_adc(unit); 2760 2761 SOC_IF_ERROR_RETURN(clr_etu_counters(unit)); 2762 SOC_IF_ERROR_RETURN(clr_all_intr_sts(unit)); 2763 SOC_IF_ERROR_RETURN(clr_adc_max_logs(unit)); 2764 2765 SOC_IF_ERROR_RETURN(chk_fifos(unit)); 2766 SOC_IF_ERROR_RETURN(chk_etu_counters(unit)); 2767 SOC_IF_ERROR_RETURN(chk_all_intr_sts(unit, num_nl)); 2768 SOC_IF_ERROR_RETURN(chk_esmif_adc(unit)); 2769 2770 _SHR_RETURN(SOC_E_NONE); 2771 } 2772 2773 2774 #define NL_REG_BUF_SIZE 10 2775 typedef uint8 nl_reg_buf_t[NL_REG_BUF_SIZE]; /* Little-endian */ 2776 2777 #ifndef BIT 2778 #define BIT(n) (1U << (n)) 2779 #endif 2780 #ifndef BITS 2781 #define BITS(n) ((n) == 32 ? ~0 : BIT(n) - 1) 2782 #endif 2783 #ifndef MIN 2784 #define MIN(a, b) ((a) < (b) ? (a) : (b)) 2785 #endif 2786 2787 STATIC uint32 2788 nl_reg_buf_bitfield_get(nl_reg_buf_t buf, unsigned ofs, unsigned width) 2789 { 2790 unsigned sh = ofs & BITS(3), r = 8 - sh, n, rsh; 2791 uint8 *p, m; 2792 uint32 result; 2793 2794 /* assert((ofs + width) <= COUNTOF(buf) * sizeof(buf[0])); */ 2795 /* assert(width <= 32); */ 2796 2797 for (rsh = result = 0, p = &buf[ofs >> 3]; width; width -= n, ++p) { 2798 n = MIN(width, 8); 2799 m = BITS(n); 2800 2801 result |= ((p[0] >> sh) & m) << rsh; 2802 rsh += r; 2803 if (n > r) { 2804 result |= (p[1] & (m >> r)) << rsh; 2805 rsh += n - r; 2806 } 2807 } 2808 2809 return (result); 2810 } 2811 2812 STATIC void 2813 nl_reg_buf_bitfield_set(nl_reg_buf_t buf, unsigned ofs, unsigned width, uint32 val) 2814 { 2815 unsigned sh = ofs & BITS(3), r = 8 - sh, n; 2816 uint8 *p, m, u; 2817 2818 /* assert((ofs + width) <= COUNTOF(buf) * sizeof(buf[0])); */ 2819 /* assert(width <= 32); */ 2820 /* assert(val <= BITS(width)); */ 2821 2822 for (p = &buf[ofs >> 3]; width; width -= n, ++p, val >>= 8) { 2823 n = MIN(width, 8); 2824 m = BITS(n); 2825 u = val & m; 2826 2827 p[0] = (p[0] & ~(m << sh)) | (u << sh); 2828 if (n > r) { 2829 p[1] = (p[1] & ~(m >> r)) | (u >> r); 2830 } 2831 } 2832 } 2833 2834 STATIC unsigned 2835 nl_reg_buf_is_zero(nl_reg_buf_t buf) 2836 { 2837 uint8 *p; 2838 unsigned n; 2839 2840 for (p = buf, n = NL_REG_BUF_SIZE; n; --n, ++p) { 2841 if (*p != 0) return (0); 2842 } 2843 return (1); 2844 } 2845 2846 STATIC uint32 2847 nl_reg_adr26b(unsigned dev_id, unsigned reg_adr20b) 2848 { 2849 return ((dev_id << 23) | (reg_adr20b & 0xfffff)); 2850 } 2851 2852 2853 STATIC int 2854 nl_raw_req_submit(int unit, 2855 unsigned capture_rsp, 2856 unsigned flip_dw_byte_order, 2857 unsigned rsp_index_count, 2858 unsigned eop, 2859 unsigned num_dw, 2860 unsigned nop_pre, 2861 unsigned num_nops, 2862 unsigned opcode 2863 ) 2864 { 2865 uint32 etu_tx_raw_req_control_word_buf; 2866 2867 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, ETU_TX_RAW_REQ_CONTROL_WORDr, 0, 0, &etu_tx_raw_req_control_word_buf)); 2868 if (soc_reg_field_get(unit, ETU_TX_RAW_REQ_CONTROL_WORDr, etu_tx_raw_req_control_word_buf, STARTf) == 1 2869 && soc_reg_field_get(unit, ETU_TX_RAW_REQ_CONTROL_WORDr, etu_tx_raw_req_control_word_buf, COMPLETEf) == 0 2870 ) { 2871 _SHR_RETURN(SOC_E_BUSY); 2872 } 2873 2874 soc_reg_field_set(unit, ETU_TX_RAW_REQ_CONTROL_WORDr, &etu_tx_raw_req_control_word_buf, STARTf, 0); 2875 soc_reg_field_set(unit, ETU_TX_RAW_REQ_CONTROL_WORDr, &etu_tx_raw_req_control_word_buf, COMPLETEf, 0); 2876 soc_reg_field_set(unit, ETU_TX_RAW_REQ_CONTROL_WORDr, &etu_tx_raw_req_control_word_buf, CAPTUREf, capture_rsp ? 1 : 0); 2877 soc_reg_field_set(unit, ETU_TX_RAW_REQ_CONTROL_WORDr, &etu_tx_raw_req_control_word_buf, NOT_SEARCHf, !flip_dw_byte_order); 2878 soc_reg_field_set(unit, ETU_TX_RAW_REQ_CONTROL_WORDr, &etu_tx_raw_req_control_word_buf, TOTAL_NUM_RSPf, rsp_index_count); 2879 soc_reg_field_set(unit, ETU_TX_RAW_REQ_CONTROL_WORDr, &etu_tx_raw_req_control_word_buf, EOPf, eop); 2880 soc_reg_field_set(unit, ETU_TX_RAW_REQ_CONTROL_WORDr, &etu_tx_raw_req_control_word_buf, NUM_DWf, num_dw); 2881 soc_reg_field_set(unit, ETU_TX_RAW_REQ_CONTROL_WORDr, &etu_tx_raw_req_control_word_buf, NOP_PRE_PSTf, nop_pre ? 1 : 0); 2882 soc_reg_field_set(unit, ETU_TX_RAW_REQ_CONTROL_WORDr, &etu_tx_raw_req_control_word_buf, NUM_NOPf, num_nops); 2883 soc_reg_field_set(unit, ETU_TX_RAW_REQ_CONTROL_WORDr, &etu_tx_raw_req_control_word_buf, OPCf, opcode); 2884 SOC_IF_ERROR_RETURN(WRITE_ETU_TX_RAW_REQ_CONTROL_WORDr(unit, etu_tx_raw_req_control_word_buf)); 2885 2886 soc_reg_field_set(unit, ETU_TX_RAW_REQ_CONTROL_WORDr, &etu_tx_raw_req_control_word_buf, STARTf, 1); 2887 SOC_IF_ERROR_RETURN(WRITE_ETU_TX_RAW_REQ_CONTROL_WORDr(unit, etu_tx_raw_req_control_word_buf)); 2888 2889 _SHR_RETURN(SOC_E_NONE); 2890 } 2891 2892 2893 STATIC int 2894 nl_raw_req_check_done(int unit) 2895 { 2896 uint32 etu_tx_raw_req_control_word_buf; 2897 2898 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, ETU_TX_RAW_REQ_CONTROL_WORDr, 0, 0, &etu_tx_raw_req_control_word_buf)); 2899 if (soc_reg_field_get(unit, ETU_TX_RAW_REQ_CONTROL_WORDr, etu_tx_raw_req_control_word_buf, STARTf) != 1) { 2900 _SHR_RETURN(SOC_E_FAIL); 2901 } 2902 return (soc_reg_field_get(unit, ETU_TX_RAW_REQ_CONTROL_WORDr, etu_tx_raw_req_control_word_buf, COMPLETEf) ? SOC_E_NONE : SOC_E_BUSY); 2903 } 2904 2905 2906 STATIC int 2907 nl_raw_req_poll_done(int unit, unsigned max_polls) 2908 { 2909 for ( ; max_polls; --max_polls) { 2910 int errcode = nl_raw_req_check_done(unit); 2911 2912 if (errcode == SOC_E_BUSY) { 2913 sal_usleep(1000); /* Wait 1 ms */ 2914 continue; 2915 } 2916 2917 _SHR_RETURN(errcode); 2918 } 2919 2920 _SHR_RETURN(SOC_E_TIMEOUT); 2921 } 2922 2923 enum nl_read_type { NL_READ_TYPE_REG, NL_READ_TYPE_DBX, NL_READ_TYPE_DBY }; 2924 2925 STATIC int 2926 nl_raw_rsp_parse_for_read(int unit, nl_reg_buf_t rd_data) 2927 { 2928 etu_dbg_rx_raw_rsp_entry_t etu_dbg_rx_raw_rsp_buf; 2929 uint64 dw0, dw1; 2930 unsigned i, sh; 2931 2932 SOC_IF_ERROR_RETURN(soc_mem_read(unit, ETU_DBG_RX_RAW_RSPm, MEM_BLOCK_ANY, 0, etu_dbg_rx_raw_rsp_buf.entry_data)); 2933 soc_mem_field64_get(unit, ETU_DBG_RX_RAW_RSPm, etu_dbg_rx_raw_rsp_buf.entry_data, DW0f, &dw0); 2934 soc_mem_field64_get(unit, ETU_DBG_RX_RAW_RSPm, etu_dbg_rx_raw_rsp_buf.entry_data, DW1f, &dw1); 2935 for (sh = 56, i = 0; i < 8; ++i, sh -= 8) { 2936 uint64 temp = dw0; 2937 2938 COMPILER_64_SHR(temp, sh); 2939 rd_data[i] = COMPILER_64_LO(temp); 2940 } 2941 for (sh = 56; i < NL_REG_BUF_SIZE; ++i, sh -= 8) { 2942 uint64 temp = dw1; 2943 2944 COMPILER_64_SHR(temp, sh); 2945 rd_data[i] = COMPILER_64_LO(temp); 2946 } 2947 2948 _SHR_RETURN(SOC_E_NONE); 2949 } 2950 2951 2952 STATIC int 2953 nl_reg_read(int unit, unsigned dev_id, uint32 reg_adr, nl_reg_buf_t rd_data) 2954 { 2955 uint32 reg_adr26b = nl_reg_adr26b(dev_id, reg_adr); 2956 uint64 dw0, dw1; 2957 etu_tx_raw_req_data_word_entry_t etu_tx_raw_req_data_word_buf; 2958 2959 COMPILER_64_SET(dw0, 2960 ((reg_adr26b & (BITS(8) << 0)) << 24) 2961 | ((reg_adr26b & (BITS(8) << 8)) << 8) 2962 | ((reg_adr26b & (BITS(8) << 16)) >> 8) 2963 | ((reg_adr26b & (BITS(2) << 24)) >> 24), 2964 0 2965 ); 2966 COMPILER_64_ZERO(dw1); 2967 2968 SOC_IF_ERROR_RETURN(soc_mem_read(unit, ETU_TX_RAW_REQ_DATA_WORDm, MEM_BLOCK_ANY, 0, etu_tx_raw_req_data_word_buf.entry_data)); 2969 soc_mem_field64_set(unit, ETU_TX_RAW_REQ_DATA_WORDm, etu_tx_raw_req_data_word_buf.entry_data, DW0f, dw0); 2970 soc_mem_field64_set(unit, ETU_TX_RAW_REQ_DATA_WORDm, etu_tx_raw_req_data_word_buf.entry_data, DW1f, dw1); 2971 SOC_IF_ERROR_RETURN(soc_mem_write(unit, ETU_TX_RAW_REQ_DATA_WORDm, MEM_BLOCK_ALL, 0, etu_tx_raw_req_data_word_buf.entry_data)); 2972 2973 SOC_IF_ERROR_RETURN(nl_raw_req_submit(unit, 1, 0, 1, 8, 2, 1, 0, 0x2)); 2974 SOC_IF_ERROR_RETURN(nl_raw_req_poll_done(unit, 60)); 2975 SOC_IF_ERROR_RETURN(nl_raw_rsp_parse_for_read(unit, rd_data)); 2976 2977 _SHR_RETURN(SOC_E_NONE); 2978 } 2979 2980 2981 STATIC int 2982 nl_reg_write(int unit, 2983 unsigned dev_id, 2984 uint32 reg_adr, 2985 const nl_reg_buf_t wr_data, 2986 unsigned num_nops, 2987 unsigned nop_pre, 2988 unsigned capture_rsp 2989 ) 2990 { 2991 uint32 reg_adr26b = nl_reg_adr26b(dev_id, reg_adr); 2992 uint64 dw0, dw1, dw2; 2993 etu_tx_raw_req_data_word_entry_t etu_tx_raw_req_data_word_buf; 2994 2995 COMPILER_64_SET(dw0, 2996 ((reg_adr26b & (BITS(8) << 0)) << 24) 2997 | ((reg_adr26b & (BITS(8) << 8)) << 8) 2998 | ((reg_adr26b & (BITS(8) << 16)) >> 8) 2999 | ((reg_adr26b & (BITS(2) << 24)) >> 24), 3000 (wr_data[0] << 24) 3001 | (wr_data[1] << 16) 3002 | (wr_data[2] << 8) 3003 | wr_data[3] 3004 ); 3005 COMPILER_64_SET(dw1, 3006 (wr_data[4] << 24) 3007 | (wr_data[5] << 16) 3008 | (wr_data[6] << 8) 3009 | wr_data[7], 3010 (wr_data[8] << 24) 3011 | (wr_data[9] << 16) 3012 ); 3013 COMPILER_64_ZERO(dw2); 3014 3015 SOC_IF_ERROR_RETURN(soc_mem_read(unit, ETU_TX_RAW_REQ_DATA_WORDm, MEM_BLOCK_ANY, 0, etu_tx_raw_req_data_word_buf.entry_data)); 3016 soc_mem_field64_set(unit, ETU_TX_RAW_REQ_DATA_WORDm, etu_tx_raw_req_data_word_buf.entry_data, DW0f, dw0); 3017 soc_mem_field64_set(unit, ETU_TX_RAW_REQ_DATA_WORDm, etu_tx_raw_req_data_word_buf.entry_data, DW1f, dw1); 3018 soc_mem_field64_set(unit, ETU_TX_RAW_REQ_DATA_WORDm, etu_tx_raw_req_data_word_buf.entry_data, DW2f, dw2); 3019 SOC_IF_ERROR_RETURN(soc_mem_write(unit, ETU_TX_RAW_REQ_DATA_WORDm, MEM_BLOCK_ALL, 0, etu_tx_raw_req_data_word_buf.entry_data)); 3020 3021 SOC_IF_ERROR_RETURN(nl_raw_req_submit(unit, capture_rsp, 0, 1, 8, 3, nop_pre, num_nops, 0x1)); 3022 SOC_IF_ERROR_RETURN(nl_raw_req_poll_done(unit, 60)); 3023 3024 _SHR_RETURN(SOC_E_NONE); 3025 } 3026 3027 #define NL_REG_ADDR_DEV_ID 0x00000 3028 #define NL_REG_ADDR_DEV_CFG 0x00001 3029 #define NL_REG_ADDR_ERR_STS 0x00002 3030 #define NL_REG_ADDR_ERR_STS_MSK 0x00003 3031 #define NL_REG_ADDR_DB_SOFT_ERR_FIFO 0x00005 3032 #define NL_REG_ADDR_ADV_FEATURES_SOFT_ERR 0x00019 3033 #define NL_REG_ADDR_LPM_ENABLE 0x00020 3034 #define NL_REG_ADDR_DEBUG_REG0 0x003FE 3035 #define NL_REG_ADDR_DEBUG_REG1 0x003FF 3036 #define NL_REG_ADDR_CONTEXT_BUFFER_BASE 0x08000 3037 #define NL_REG_ADDR_SCRATCHPAD_REG0 0x80000 3038 #define NL_REG_ADDR_SCRATCHPAD_REG1 0x80001 3039 #define NL_REG_ADDR_RESULT_REG0 0x80010 3040 #define NL_REG_ADDR_RESULT_REG1 0x80011 3041 #define NL_REG_ADDR_RANGE_CONTROL_BASE 0x85000 3042 #define NL_REG_ADDR_LTR_BLOCK_SEL_REG0(ltr) (0x04000 + ((ltr) << 5)) 3043 #define NL_REG_ADDR_LTR_BLOCK_SEL_REG1(ltr) (0x04001 + ((ltr) << 5)) 3044 #define NL_REG_ADDR_LTR_MISCELLANEOUS_REG(ltr) (0x04009 + ((ltr) << 5)) 3045 3046 STATIC int 3047 nl_reg_access_test(int unit, unsigned dev_id) 3048 { 3049 const unsigned num_nops = 0, nop_pre = 0; 3050 const uint32 reg_adr0 = NL_REG_ADDR_SCRATCHPAD_REG0, reg_adr1 = NL_REG_ADDR_SCRATCHPAD_REG1; 3051 3052 { 3053 static const nl_reg_buf_t wr_data0 = { 0x34, 0x12, 0xf0, 0xde, 0xbc, 0x9a, 0x78, 0x56, 0x34, 0x12 }; 3054 static const nl_reg_buf_t wr_data1 = { 0xcd, 0xab, 0x89, 0x67, 0x45, 0x23, 0x01, 0xef, 0xcd, 0xab }; 3055 3056 nl_reg_buf_t rd_data0, rd_data1; 3057 3058 SOC_IF_ERROR_RETURN(nl_reg_write(unit, dev_id, reg_adr0, wr_data0, num_nops, nop_pre, 0)); 3059 SOC_IF_ERROR_RETURN(nl_reg_write(unit, dev_id, reg_adr1, wr_data1, num_nops, nop_pre, 0)); 3060 SOC_IF_ERROR_RETURN(nl_reg_read(unit, dev_id, reg_adr0, rd_data0)); 3061 SOC_IF_ERROR_RETURN(nl_reg_read(unit, dev_id, reg_adr1, rd_data1)); 3062 if (sal_memcmp(rd_data0, wr_data0, sizeof(rd_data0)) != 0) { 3063 _SHR_RETURN(SOC_E_FAIL); 3064 } 3065 if (sal_memcmp(rd_data1, wr_data1, sizeof(rd_data1)) != 0) { 3066 _SHR_RETURN(SOC_E_FAIL); 3067 } 3068 } 3069 3070 { 3071 static const nl_reg_buf_t wr_data0 = { 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa }; 3072 static const nl_reg_buf_t wr_data1 = { 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55 }; 3073 3074 SOC_IF_ERROR_RETURN(nl_reg_write(unit, dev_id, reg_adr0, wr_data0, num_nops, nop_pre, 0)); 3075 SOC_IF_ERROR_RETURN(nl_reg_write(unit, dev_id, reg_adr1, wr_data1, num_nops, nop_pre, 0)); 3076 } 3077 3078 _SHR_RETURN(SOC_E_NONE); 3079 } 3080 3081 #if 0 /* <HP> Skip for now, since db test fails </HP> */ 3082 3083 STATIC int 3084 nl_db_adr26b(uint32 et_pa22b, unsigned dev_density_mb, uint32 *adr26b) 3085 { 3086 unsigned sh; 3087 3088 switch (dev_density_mb) { 3089 case 80: 3090 sh = 20; 3091 break; 3092 case 40: 3093 sh = 19; 3094 break; 3095 case 20: 3096 sh = 18; 3097 break; 3098 case 10: 3099 sh = 17; 3100 break; 3101 default: 3102 _SHR_RETURN(SOC_E_FAIL); 3103 } 3104 3105 *adr26b = (((et_pa22b >> sh) & BITS(2)) << 23) | (et_pa22b & BITS(sh)); 3106 3107 _SHR_RETURN(SOC_E_NONE); 3108 } 3109 3110 3111 STATIC int 3112 nl_db_read(int unit, 3113 uint32 et_pa22b, 3114 enum nl_read_type read_type, 3115 unsigned dev_density_mb, 3116 nl_reg_buf_t rd_data 3117 ) 3118 { 3119 uint32 adr26; 3120 uint64 dw0, dw1; 3121 etu_tx_raw_req_data_word_entry_t etu_tx_raw_req_data_word_buf; 3122 3123 SOC_IF_ERROR_RETURN(nl_db_adr26b(et_pa22b, dev_density_mb, &adr26)); 3124 COMPILER_64_SET(dw0, 3125 ((reg_adr26b & (BITS(8) << 0)) << 24) 3126 | ((reg_adr26b & (BITS(8) << 8)) << 8) 3127 | ((reg_adr26b & (BITS(8) << 16)) >> 8) 3128 | ((reg_adr26b & (BITS(2) << 24)) >> 24), 3129 0 3130 ); 3131 COMPILTER_64_ZERO(dw1); 3132 3133 SOC_IF_ERROR_RETURN(soc_mem_read(unit, ETU_TX_RAW_REQ_DATA_WORDm, MEM_BLOCK_ANY, 0, etu_tx_raw_req_data_word_buf.entry_data)); 3134 soc_mem_field64_set(unit, ETU_TX_RAW_REQ_DATA_WORDm, etu_tx_raw_req_data_word_buf.entry_data, DW0f, dw0); 3135 soc_mem_field64_set(unit, ETU_TX_RAW_REQ_DATA_WORDm, etu_tx_raw_req_data_word_buf.entry_data, DW1f, dw1); 3136 SOC_IF_ERROR_RETURN(soc_mem_write(unit, ETU_TX_RAW_REQ_DATA_WORDm, MEM_BLOCK_ALL, 0, etu_tx_raw_req_data_word_buf.entry_data)); 3137 3138 SOC_IF_ERROR_RETURN(nl_raw_req_submit(unit, 1, 0, 1, 8, 2, 1, 0, read_type == NL_READ_TYPE_DBX ? 2 : 3)); 3139 SOC_IF_ERROR_RETURN(nl_raw_req_poll_done(unit, 60)); 3140 SOC_IF_ERROR_RETURN(nl_raw_rsp_parse_for_read(unit, rd_data)); 3141 3142 _SHR_RETURN(SOC_E_NONE); 3143 } 3144 3145 3146 STATIC int 3147 nl_db_write(int unit, 3148 uint32 et_pa22b, 3149 nl_reg_buf_t wr_data, 3150 nl_reg_buf_t wr_mask, 3151 unsigned vbit, 3152 unsigned wr_mode_xy, 3153 unsigned dev_density_mb, 3154 unsigned capture_rsp 3155 ) 3156 { 3157 uint32 adr26; 3158 uint64 dw0, dw1, dw2; 3159 unsigned i; 3160 int sh; 3161 etu_tx_raw_req_data_word_entry_t etu_tx_raw_req_data_word_buf; 3162 3163 SOC_IF_ERROR_RETURN(nl_db_adr26b(et_pa22b, dev_density_mb, &adr26)); 3164 COMPILER_64_SET(dw0, 3165 ((adr26 & (BITS(8) << 0)) << 24) 3166 | ((adr26 & (BITS(8) << 8)) << 8) 3167 | ((adr26 & (BITS(8) << 16)) >> 8) 3168 | ((adr26 & (BITS(2) << 24)) >> 24) 3169 | ((wr_mode_xy ? 1 : 0) << 7) 3170 | ((vibt ? 1 : 0) << 6), 3171 (wr_data[0] << 24) 3172 | (wr_data[1] << 16) 3173 | (wr_data[2] << 8) 3174 | wr_data[3] 3175 ); 3176 COMPILER_64_SET(dw1, 3177 (wr_data[4] << 24) 3178 | (wr_data[5] << 16) 3179 | (wr_data[6] << 8) 3180 | wr_data[7], 3181 (wr_data[8] << 24) 3182 | (wr_data[9] << 16) 3183 | (wr_mask[0] << 8) 3184 | wr_mask[1] 3185 ); 3186 COMPILER_64_SET(dw2, 3187 (wr_mask[2] << 24) 3188 | (wr_mask[3] << 16) 3189 | (wr_mask[4] << 8) 3190 | wr_mask[5], 3191 (wr_mask[6] << 24) 3192 | (wr_mask[7] << 16) 3193 | (wr_mask[8] << 8) 3194 | wr_mask[9] 3195 ); 3196 3197 SOC_IF_ERROR_RETURN(soc_mem_read(unit, ETU_TX_RAW_REQ_DATA_WORDm, MEM_BLOCK_ANY, 0, etu_tx_raw_req_data_word_buf.entry_data)); 3198 soc_mem_field64_set(unit, ETU_TX_RAW_REQ_DATA_WORDm, etu_tx_raw_req_data_word_buf.entry_data, DW0f, dw0); 3199 soc_mem_field64_set(unit, ETU_TX_RAW_REQ_DATA_WORDm, etu_tx_raw_req_data_word_buf.entry_data, DW1f, dw1); 3200 soc_mem_field64_set(unit, ETU_TX_RAW_REQ_DATA_WORDm, etu_tx_raw_req_data_word_buf.entry_data, DW2f, dw2); 3201 SOC_IF_ERROR_RETURN(soc_mem_write(unit, ETU_TX_RAW_REQ_DATA_WORDm, MEM_BLOCK_ALL, 0, etu_tx_raw_req_data_word_buf.entry_data)); 3202 3203 SOC_IF_ERROR_RETURN(nl_raw_req_submit(unit, capture_rsp, 0, 1, 8, 3, 1, 0, 1)); 3204 SOC_IF_ERROR_RETURN(nl_raw_req_poll_done(unit, 60)); 3205 3206 _SHR_RETURN(SOC_E_NONE); 3207 } 3208 3209 3210 STATIC int 3211 nl_db_dup_entry_ofs_get(int unit, unsigned *dup_entry_ofs) 3212 { 3213 uint32 etu_config0_buf; 3214 3215 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, ETU_CONFIG0r, 0, 0, &etu_config0_buf)); 3216 *dup_entry_ofs = soc_reg_field_get(unit, ETU_CONFIG0r, etu_config0_buf, DUP_BLK_OFFSETf) << 12; 3217 3218 _SHR_RETURN(SOC_E_NONE); 3219 } 3220 3221 3222 STATIC int 3223 nl_db_invalidate(int unit, uint32 et_pa22b, uint32 vbit_bmp, unsigned duplicate) 3224 { 3225 uint32 tmp_dup_et_pa22b, tmp_et_pa22b; 3226 unsigned invalidation_reqd, i; 3227 3228 if (duplicate) { 3229 unsigned dup_entry_ofs; 3230 3231 SOC_IF_ERROR_RETURN(nl_db_dup_entry_ofs_get(unit, &dup_entry_ofs)); 3232 tmp_dup_et_pa22b = et_pa22b + dup_entry_ofs; 3233 } else { 3234 tmp_dup_et_pa22b = 0; 3235 } 3236 tmp_et_pa22b = et_pa22b; 3237 invalidation_reqd = 0; 3238 for (i = 0; i < 32; ++i) { 3239 if ((vbit_bmp & BIT(i)) == 0) { 3240 invalidation_reqd = 1; 3241 } 3242 ++tmp_et_pa22b; 3243 ++tmp_dup_et_pa22b; 3244 } 3245 if (invalidation_reqd) { 3246 ext_tcam_vbit_entry_t ext_tcam_vbit_buf; 3247 3248 SOC_IF_ERROR_RETURN(soc_mem_read(unit, EXT_TCAM_VBITm, MEM_BLOCK_ANY, et_pa22b, ext_tcam_vbit_buf.entry_data)); 3249 soc_mem_field32_set(unit, EXT_TCAM_VBITm, ext_tcam_vbit_buf.entry_data, DUPLICATEf, duplicate ? 1 : 0); 3250 soc_mem_field32_set(unit, EXT_TCAM_VBITm, ext_tcam_vbit_buf.entry_data, VBITf, vbit_bmp); 3251 SOC_IF_ERROR_RETURN(soc_mem_write(unit, EXT_TCAM_VBITm, MEM_BLOCK_ALL, et_pa22b, ext_tcam_vbit_buf.entry_data)); 3252 } 3253 3254 _SHR_RETURN(SOC_E_NONE); 3255 } 3256 3257 3258 STATIC int 3259 nl_db_access_dm_test(int unit, unsigned dev_id) 3260 { 3261 static const nl_reg_buf_t wr_data = { 0xcd, 0xab, 0x89, 0x67, 0x45, 0x23, 0x01, 0xef, 0xcd, 0xab }; 3262 static const nl_reg_buf_t wr_mask = { 0x00, 0x00, 0xff, 0xff, 0x00, 0x00, 0xff, 0xff, 0x00, 0x00 }; 3263 3264 const uint32 et_pa22b = (((dev_id << 7) + 126) << 12) + 25; 3265 const uint32 et_pa22b_for_delete = ((dev_id << 7) + 126) << 12; 3266 const uint32 vbit_bmp = ~(1 << 25); 3267 const unsigned dev_density_mb = 40; 3268 3269 nl_reg_buf_t exp_data, rd_data; 3270 unsigned i; 3271 3272 SOC_IF_ERROR_RETURN(nl_db_write(unit, 3273 et_pa22b, 3274 (uint8 *) wr_data, 3275 (uint8 *) wr_mask, 3276 1, 3277 0, 3278 dev_density_mb, 3279 0 3280 ) 3281 ); 3282 3283 SOC_IF_ERROR_RETURN(nl_db_read(unit, 3284 et_pa22b, 3285 NL_READ_TYPE_DBX, 3286 dev_density_mb, 3287 rd_data 3288 ) 3289 ); 3290 for (i = 0; i < NL_REG_BUF_SIZE; ++i) { 3291 exp_data[i] = wr_data[i] & ~wr_mask[i]; 3292 } 3293 if (sal_memcmp(rd_data, exp_data, sizeof(rd_data)) != 0) { 3294 _SHR_RETURN(SOC_E_FAIL); 3295 } 3296 3297 SOC_IF_ERROR_RETURN(nl_db_read(unit, 3298 et_pa22b, 3299 NL_READ_TYPE_DBY, 3300 dev_density_mb, 3301 rd_data 3302 ) 3303 ); 3304 for (i = 0; i < NL_REG_BUF_SIZE; ++i) { 3305 exp_data[i] = ~wr_data[i] & ~wr_mask[i]; 3306 } 3307 if (sal_memcmp(rd_data, exp_data, sizeof(rd_data)) != 0) { 3308 _SHR_RETURN(SOC_E_FAIL); 3309 } 3310 3311 SOC_IF_ERROR_RETURN(nl_db_invalidate(unit, 3312 et_pa22b_for_delete, 3313 vbit_bmp, 3314 0 3315 ) 3316 ); 3317 3318 SOC_IF_ERROR_RETURN(nl_db_read(unit, 3319 et_pa22b, 3320 NL_READ_TYPE_DBX, 3321 dev_density_mb, 3322 rd_data 3323 ) 3324 ); 3325 sal_memset(exp_data, 0, sizeof(exp_data)); 3326 if (sal_memcmp(rd_data, exp_data, sizeof(rd_data)) != 0) { 3327 _SHR_RETURN(SOC_E_FAIL); 3328 } 3329 3330 SOC_IF_ERROR_RETURN(nl_db_read(unit, 3331 et_pa22b, 3332 NL_READ_TYPE_DBY, 3333 dev_density_mb, 3334 rd_data 3335 ) 3336 ); 3337 sal_memset(exp_data, 0xff, sizeof(exp_data)); 3338 if (sal_memcmp(rd_data, exp_data, sizeof(rd_data)) != 0) { 3339 _SHR_RETURN(SOC_E_FAIL); 3340 } 3341 3342 _SHR_RETURN(SOC_E_NONE); 3343 } 3344 3345 #endif 3346 3347 STATIC int 3348 nl_chk_err_status_mask_reg(int unit, unsigned dev_id) 3349 { 3350 unsigned errcnt = 0; 3351 nl_reg_buf_t nl_reg_err_sts_msk_buf; 3352 3353 SOC_IF_ERROR_RETURN(nl_reg_read(unit, dev_id, NL_REG_ADDR_ERR_STS_MSK, nl_reg_err_sts_msk_buf)); 3354 if (nl_reg_buf_bitfield_get(nl_reg_err_sts_msk_buf, 79, 1) == 0) { 3355 ++errcnt; 3356 } 3357 if (nl_reg_buf_bitfield_get(nl_reg_err_sts_msk_buf, 50, 1) != BITS(1)) { 3358 ++errcnt; 3359 } 3360 if (nl_reg_buf_bitfield_get(nl_reg_err_sts_msk_buf, 48, 3) != BITS(3)) { 3361 ++errcnt; 3362 } 3363 if (nl_reg_buf_bitfield_get(nl_reg_err_sts_msk_buf, 31, 1) != BITS(1)) { 3364 ++errcnt; 3365 } 3366 if (nl_reg_buf_bitfield_get(nl_reg_err_sts_msk_buf, 16, 14) != BITS(14)) { 3367 ++errcnt; 3368 } 3369 if (nl_reg_buf_bitfield_get(nl_reg_err_sts_msk_buf, 5, 1) != BITS(1)) { 3370 ++errcnt; 3371 } 3372 if (nl_reg_buf_bitfield_get(nl_reg_err_sts_msk_buf, 0, 3) != BITS(3)) { 3373 ++errcnt; 3374 } 3375 3376 _SHR_RETURN(errcnt ? SOC_E_FAIL : SOC_E_NONE); 3377 } 3378 3379 3380 STATIC int 3381 nl_prog_err_status_mask_reg(int unit, unsigned dev_id) 3382 { 3383 nl_reg_buf_t nl_reg_err_sts_msk_buf; 3384 3385 sal_memset(nl_reg_err_sts_msk_buf, 0, sizeof(nl_reg_err_sts_msk_buf)); 3386 nl_reg_buf_bitfield_set(nl_reg_err_sts_msk_buf, 0, 3, 0x7); 3387 nl_reg_buf_bitfield_set(nl_reg_err_sts_msk_buf, 5, 1, 1); 3388 nl_reg_buf_bitfield_set(nl_reg_err_sts_msk_buf, 16, 16, 0xffff); 3389 nl_reg_buf_bitfield_set(nl_reg_err_sts_msk_buf, 48, 3, 0x7); 3390 nl_reg_buf_bitfield_set(nl_reg_err_sts_msk_buf, 79, 1, 1); 3391 SOC_IF_ERROR_RETURN(nl_reg_write(unit, dev_id, NL_REG_ADDR_ERR_STS_MSK, nl_reg_err_sts_msk_buf, 0, 0, 0)); 3392 _SHR_RETURN(nl_chk_err_status_mask_reg(unit, dev_id)); 3393 } 3394 3395 3396 STATIC int 3397 nl_chk_err_status_reg(int unit, unsigned dev_id) 3398 { 3399 nl_reg_buf_t nl_reg_err_sts_buf; 3400 3401 SOC_IF_ERROR_RETURN(nl_reg_read(unit, dev_id, NL_REG_ADDR_ERR_STS, nl_reg_err_sts_buf)); 3402 _SHR_RETURN(nl_reg_buf_is_zero(nl_reg_err_sts_buf) ? SOC_E_NONE : SOC_E_FAIL); 3403 } 3404 3405 STATIC int 3406 nl_chk_low_jitter_settings(int unit) 3407 { 3408 const uint32 reg_adr0 = NL_REG_ADDR_DEBUG_REG0, reg_adr1 = NL_REG_ADDR_DEBUG_REG1; 3409 static const uint32 wr_data0[3] = { 0x0, 0x0, 0x000204f4 }; 3410 static const uint32 wr_data1[3] = { 0xffffffff, 0xffffffff, 0xffffffff }; 3411 static const uint32 wr_data2[3] = { 0x0, 0x0, 0x00020800 }; 3412 static uint32 rd_data[3]; 3413 3414 SOC_IF_ERROR_RETURN(soc_tr3_tcam_write_reg(unit, reg_adr0, wr_data0[0], 3415 wr_data0[1], wr_data0[2])); 3416 SOC_IF_ERROR_RETURN(soc_tr3_tcam_write_reg(unit, reg_adr1, wr_data1[0], 3417 wr_data1[1], wr_data1[2])); 3418 SOC_IF_ERROR_RETURN(soc_tr3_tcam_write_reg(unit, reg_adr0, wr_data2[0], 3419 wr_data2[1], wr_data2[2])); 3420 SOC_IF_ERROR_RETURN(soc_tr3_tcam_read_reg(unit, reg_adr1, rd_data, 3421 rd_data + 1, rd_data + 2)); 3422 if (((*rd_data) & (BIT(8) | BIT(9))) == 0) { 3423 return 1; 3424 } else { 3425 return 0; 3426 } 3427 } 3428 3429 STATIC int 3430 etu_mems_rst(int unit, unsigned clr_hbits, unsigned clr_et_pa_xlat) 3431 { 3432 uint32 etu_int_mem_rst_buf = 0; 3433 3434 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, ETU_INT_MEM_RSTr, 0, 0, etu_int_mem_rst_buf)); 3435 if (clr_hbits) { 3436 soc_reg_field_set(unit, ETU_INT_MEM_RSTr, &etu_int_mem_rst_buf, EXT_DST_HBITSf, 1); 3437 soc_reg_field_set(unit, ETU_INT_MEM_RSTr, &etu_int_mem_rst_buf, EXT_SRC_HBITSf, 1); 3438 soc_reg_field_set(unit, ETU_INT_MEM_RSTr, &etu_int_mem_rst_buf, EXT_LOC_SRC_HBITSf, 1); 3439 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, ETU_INT_MEM_RSTr, 0, 0, etu_int_mem_rst_buf)); 3440 } 3441 if (clr_et_pa_xlat) { 3442 soc_reg_field_set(unit, ETU_INT_MEM_RSTr, &etu_int_mem_rst_buf, ET_PA_XLAT1f, 1); 3443 soc_reg_field_set(unit, ETU_INT_MEM_RSTr, &etu_int_mem_rst_buf, ET_PA_XLAT0f, 1); 3444 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, ETU_INT_MEM_RSTr, 0, 0, etu_int_mem_rst_buf)); 3445 } 3446 soc_reg_field_set(unit, ETU_INT_MEM_RSTr, &etu_int_mem_rst_buf, STARTf, 1); 3447 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, ETU_INT_MEM_RSTr, 0, 0, etu_int_mem_rst_buf)); 3448 3449 _SHR_RETURN(SOC_E_NONE); 3450 } 3451 3452 3453 STATIC int 3454 etu_mems_chk_rst_done(int unit) 3455 { 3456 uint32 etu_int_mem_rst_buf; 3457 3458 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, ETU_INT_MEM_RSTr, 0, 0, &etu_int_mem_rst_buf)); 3459 if (soc_reg_field_get(unit, ETU_INT_MEM_RSTr, etu_int_mem_rst_buf, COMPLETEf) 3460 && soc_reg_field_get(unit, ETU_INT_MEM_RSTr, etu_int_mem_rst_buf, STARTf) 3461 ) { 3462 uint32 etu_global_intr_sts_buf; 3463 3464 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, ETU_GLOBAL_INTR_STSr, 0, 0, &etu_global_intr_sts_buf)); 3465 if (soc_reg_field_get(unit, ETU_GLOBAL_INTR_STSr, etu_global_intr_sts_buf, INT_MEM_RST_DONEf)) { 3466 return (SOC_E_NONE); 3467 } 3468 } 3469 3470 return (SOC_E_BUSY); 3471 } 3472 3473 3474 STATIC int 3475 etu_mems_poll_rst_done(int unit) 3476 { 3477 unsigned n; 3478 3479 for (n = 1000; n; --n) { 3480 int errcode = etu_mems_chk_rst_done(unit); 3481 3482 if (errcode == SOC_E_BUSY) { 3483 sal_usleep(1000); /* Wait 1 ms */ 3484 continue; 3485 } 3486 3487 _SHR_RETURN(errcode); 3488 } 3489 3490 _SHR_RETURN(SOC_E_TIMEOUT); 3491 } 3492 3493 3494 STATIC int 3495 hwtl_zero_out_esm_range_check(int unit) 3496 { 3497 unsigned i; 3498 3499 for (i = 0; i < 22; ++i) { 3500 esm_range_check_entry_t esm_range_check_buf; 3501 3502 SOC_IF_ERROR_RETURN(soc_mem_read(unit, ESM_RANGE_CHECKm, MEM_BLOCK_ANY, i, esm_range_check_buf.entry_data)); 3503 soc_mem_field32_set(unit, ESM_RANGE_CHECKm, esm_range_check_buf.entry_data, ENABLEf, 0); 3504 soc_mem_field32_set(unit, ESM_RANGE_CHECKm, esm_range_check_buf.entry_data, FIELD_SELECTf, 0); 3505 soc_mem_field32_set(unit, ESM_RANGE_CHECKm, esm_range_check_buf.entry_data, ESM_HWTL_SEARCH_KEYf, 0); 3506 SOC_IF_ERROR_RETURN(soc_mem_write(unit, ESM_RANGE_CHECKm, MEM_BLOCK_ALL, i, esm_range_check_buf.entry_data)); 3507 } 3508 3509 _SHR_RETURN(SOC_E_NONE); 3510 } 3511 3512 #define PTR_FME_REQ_NULL 0 3513 #define PTR_FME_REQ_CBI 63 3514 #define PTR_FME_RSP_CBI (64 + PTR_FME_REQ_CBI) 3515 3516 STATIC int 3517 hwtl_prog_fme_req_cbi(int unit) 3518 { 3519 esm_key_id_to_field_mapper_entry_t esm_key_id_to_field_mapper_buf; 3520 3521 sal_memset(esm_key_id_to_field_mapper_buf.entry_data, 0, sizeof(esm_key_id_to_field_mapper_buf.entry_data)); 3522 SOC_IF_ERROR_RETURN(soc_mem_write(unit, ESM_KEY_ID_TO_FIELD_MAPPERm, MEM_BLOCK_ALL, PTR_FME_REQ_CBI, esm_key_id_to_field_mapper_buf.entry_data)); 3523 3524 { 3525 static const soc_field_t flds[] = { 3526 F1_SELECTf, 3527 FLAGS_FIELD_NOT_PRESENTf, 3528 F6_SELECTf, 3529 F7_SELECTf, 3530 F8_SELECTf, 3531 F9_SELECTf, 3532 F10_SELECTf, 3533 F11_SELECTf, 3534 RSP_INDEX_COUNT_CW0f, 3535 COST2f, 3536 COST1f, 3537 COST0f, 3538 EOP_CW0f, 3539 CONTEXT_ADDR_LSB_CW0f, 3540 NUM_DWORDS_CW0f, 3541 OPCODE_CW0f, 3542 TOTAL_NUM_CWORDSf, 3543 HWTL_EXP_RSP_PTRf 3544 }; 3545 static const uint32 fld_vals[] = { 3546 7, 3547 1, 3548 31, 3549 31, 3550 31, 3551 7, 3552 7, 3553 7, 3554 0, 3555 3, 3556 11, 3557 1, 3558 8, 3559 0, 3560 10, 3561 1 << 6, 3562 1, 3563 64 + 63 3564 }; 3565 3566 SOC_IF_ERROR_RETURN(soc_mem_fields32_modify(unit, ESM_KEY_ID_TO_FIELD_MAPPERm, PTR_FME_REQ_CBI, COUNTOF(flds), (soc_field_t *) flds, (uint32 *) fld_vals)); 3567 } 3568 3569 _SHR_RETURN(SOC_E_NONE); 3570 } 3571 3572 3573 STATIC int 3574 hwtl_prog_fme_rsp_cbi(int unit) 3575 { 3576 esm_key_id_to_field_mapper_entry_t esm_key_id_to_field_mapper_buf; 3577 3578 sal_memset(esm_key_id_to_field_mapper_buf.entry_data, 0, sizeof(esm_key_id_to_field_mapper_buf.entry_data)); 3579 _SHR_RETURN(soc_mem_write(unit, ESM_KEY_ID_TO_FIELD_MAPPERm, MEM_BLOCK_ALL, PTR_FME_RSP_CBI, esm_key_id_to_field_mapper_buf.entry_data)); 3580 } 3581 3582 3583 STATIC int 3584 nl_prog_ltr_block_sel(int unit, unsigned dev_id, unsigned ltr, unsigned num_blks, unsigned *blknums) 3585 { 3586 nl_reg_buf_t reg0_data, reg1_data; 3587 3588 sal_memset(reg0_data, 0, sizeof(reg0_data)); 3589 sal_memset(reg1_data, 0, sizeof(reg1_data)); 3590 3591 for ( ; num_blks; --num_blks, ++blknums) { 3592 unsigned blknum = *blknums; 3593 3594 if (blknum < 64) { 3595 nl_reg_buf_bitfield_set(reg0_data, blknum, 1, 1); 3596 } else if (blknum < 128) { 3597 nl_reg_buf_bitfield_set(reg1_data, blknum - 64, 1, 1); 3598 } else { 3599 _SHR_RETURN(SOC_E_FAIL); 3600 } 3601 } 3602 3603 SOC_IF_ERROR_RETURN(nl_reg_write(unit, dev_id, NL_REG_ADDR_LTR_BLOCK_SEL_REG0(ltr), reg0_data, 2, 0, 0)); 3604 SOC_IF_ERROR_RETURN(nl_reg_write(unit, dev_id, NL_REG_ADDR_LTR_BLOCK_SEL_REG1(ltr), reg1_data, 2, 0, 0)); 3605 3606 _SHR_RETURN(SOC_E_NONE); 3607 } 3608 3609 3610 STATIC int 3611 nl_prog_ltr_miscellaneous(int unit, unsigned dev_id, unsigned ltr, unsigned rsp_index_count, unsigned bmr_sel3, unsigned bmr_sel2, unsigned bmr_sel1, unsigned bmr_sel0) 3612 { 3613 nl_reg_buf_t reg_data; 3614 3615 sal_memset(reg_data, 0, sizeof(reg_data)); 3616 nl_reg_buf_bitfield_set(reg_data, 56, 2, rsp_index_count); 3617 nl_reg_buf_bitfield_set(reg_data, 12, 3, bmr_sel3); 3618 nl_reg_buf_bitfield_set(reg_data, 8, 3, bmr_sel2); 3619 nl_reg_buf_bitfield_set(reg_data, 4, 3, bmr_sel1); 3620 nl_reg_buf_bitfield_set(reg_data, 0, 3, bmr_sel0); 3621 3622 _SHR_RETURN(nl_reg_write(unit, dev_id, NL_REG_ADDR_LTR_MISCELLANEOUS_REG(ltr), reg_data, 2, 0, 0)); 3623 } 3624 3625 3626 STATIC int 3627 hwtl_prog_ltr_cbi(int unit, unsigned dev_id) 3628 { 3629 const unsigned ltr = 0; 3630 3631 SOC_IF_ERROR_RETURN(nl_prog_ltr_block_sel(unit, dev_id, ltr, 0, 0)); 3632 _SHR_RETURN(nl_prog_ltr_miscellaneous(unit, dev_id, ltr, 0, 0, 0, 0, 0)); 3633 } 3634 3635 3636 STATIC int 3637 hwtl_find_tx_pkt_count(int unit, uint32 *esm_key_id_to_field_mapper_buf_entry_data) 3638 { 3639 if (soc_mem_field32_get(unit, ESM_KEY_ID_TO_FIELD_MAPPERm, esm_key_id_to_field_mapper_buf_entry_data, LAST_CWORD_IS_OPTIONALf)) { 3640 return (-1); 3641 } 3642 3643 return (soc_mem_field32_get(unit, ESM_KEY_ID_TO_FIELD_MAPPERm, esm_key_id_to_field_mapper_buf_entry_data, TOTAL_NUM_CWORDSf)); 3644 } 3645 3646 3647 STATIC int 3648 hwtl_find_rx_byte_count(int unit, uint32 *esm_key_id_to_field_mapper_buf_entry_data) 3649 { 3650 const unsigned total_num_cwords = soc_mem_field32_get(unit, ESM_KEY_ID_TO_FIELD_MAPPERm, esm_key_id_to_field_mapper_buf_entry_data, TOTAL_NUM_CWORDSf), 3651 last_cword_is_optional = soc_mem_field32_get(unit, ESM_KEY_ID_TO_FIELD_MAPPERm, esm_key_id_to_field_mapper_buf_entry_data, LAST_CWORD_IS_OPTIONALf), 3652 rsp_index_count_cw2 = soc_mem_field32_get(unit, ESM_KEY_ID_TO_FIELD_MAPPERm, esm_key_id_to_field_mapper_buf_entry_data, RSP_INDEX_COUNT_CW2f), 3653 rsp_index_count_cw1 = soc_mem_field32_get(unit, ESM_KEY_ID_TO_FIELD_MAPPERm, esm_key_id_to_field_mapper_buf_entry_data, RSP_INDEX_COUNT_CW1f), 3654 rsp_index_count_cw0 = soc_mem_field32_get(unit, ESM_KEY_ID_TO_FIELD_MAPPERm, esm_key_id_to_field_mapper_buf_entry_data, RSP_INDEX_COUNT_CW0f); 3655 3656 unsigned num_rx_bytes_cw2, num_rx_bytes_cw1, num_rx_bytes_cw0; 3657 int result; 3658 3659 if (rsp_index_count_cw2 > 2) { 3660 num_rx_bytes_cw2 = 8 * 2; /* rsp with 2 dwords */ 3661 } else if (rsp_index_count_cw2 == 0) { 3662 num_rx_bytes_cw2 = 8 * 2; /* 4 rsp indexes */ 3663 } else { 3664 num_rx_bytes_cw2 = 8 * 1; /* rsp with 1 dword */ 3665 } 3666 3667 if (rsp_index_count_cw1 > 2) { 3668 num_rx_bytes_cw1 = 8 * 2; /* rsp with 2 dwords */ 3669 } else if (rsp_index_count_cw1 == 0) { 3670 num_rx_bytes_cw1 = 8 * 2; /* 4 rsp indexes */ 3671 } else { 3672 num_rx_bytes_cw1 = 8 * 1; /* rsp with 1 dword */ 3673 } 3674 3675 if (rsp_index_count_cw0 > 2) { 3676 num_rx_bytes_cw0 = 8 * 2; /* rsp with 2 dwords */ 3677 } else if (rsp_index_count_cw0 == 0) { 3678 num_rx_bytes_cw0 = 8 * 2; /* 4 rsp indexes */ 3679 } else { 3680 num_rx_bytes_cw0 = 8 * 1; /* rsp with 1 dword */ 3681 } 3682 3683 result = -1; 3684 if (last_cword_is_optional == 0) { 3685 if (total_num_cwords == 1) { 3686 result = num_rx_bytes_cw0; 3687 } else if (total_num_cwords == 2) { 3688 result = num_rx_bytes_cw0 + num_rx_bytes_cw1; 3689 } else if (total_num_cwords == 3) { 3690 result = num_rx_bytes_cw0 + num_rx_bytes_cw1 + num_rx_bytes_cw2; 3691 } 3692 } 3693 3694 return (result); 3695 } 3696 3697 3698 STATIC int 3699 hwtl_calc_num_tx_bytes(unsigned num_dwords, unsigned eop) 3700 { 3701 int num_tx_bytes, num_tx_bytes_last_dword; 3702 3703 if (num_dwords > 1) { 3704 num_tx_bytes = 8 * (num_dwords - 1); /* 8 bytes for each complete DW */ 3705 3706 if (eop > 15) { 3707 return (-9999); /* error */ 3708 } else if (eop == 8) { 3709 num_tx_bytes_last_dword = 8; 3710 } else if (eop > 8) { 3711 num_tx_bytes_last_dword = eop - 8; 3712 } else { 3713 return (-9999); /* error */ 3714 } 3715 3716 num_tx_bytes += num_tx_bytes_last_dword; 3717 } else { 3718 return (-9999); /* error */ 3719 } 3720 3721 return (num_tx_bytes); 3722 } 3723 3724 3725 STATIC int 3726 hwtl_find_tx_byte_count(int unit, uint32 *esm_key_id_to_field_mapper_buf_entry_data) 3727 { 3728 const unsigned total_num_cwords = soc_mem_field32_get(unit, ESM_KEY_ID_TO_FIELD_MAPPERm, esm_key_id_to_field_mapper_buf_entry_data, TOTAL_NUM_CWORDSf), 3729 last_cword_is_optional = soc_mem_field32_get(unit, ESM_KEY_ID_TO_FIELD_MAPPERm, esm_key_id_to_field_mapper_buf_entry_data, LAST_CWORD_IS_OPTIONALf), 3730 num_tx_dwords_cw2 = soc_mem_field32_get(unit, ESM_KEY_ID_TO_FIELD_MAPPERm, esm_key_id_to_field_mapper_buf_entry_data, NUM_DWORDS_CW2f), 3731 num_tx_dwords_cw1 = soc_mem_field32_get(unit, ESM_KEY_ID_TO_FIELD_MAPPERm, esm_key_id_to_field_mapper_buf_entry_data, NUM_DWORDS_CW1f), 3732 num_tx_dwords_cw0 = soc_mem_field32_get(unit, ESM_KEY_ID_TO_FIELD_MAPPERm, esm_key_id_to_field_mapper_buf_entry_data, NUM_DWORDS_CW0f), 3733 eop_cw2 = soc_mem_field32_get(unit, ESM_KEY_ID_TO_FIELD_MAPPERm, esm_key_id_to_field_mapper_buf_entry_data, EOP_CW2f), 3734 eop_cw1 = soc_mem_field32_get(unit, ESM_KEY_ID_TO_FIELD_MAPPERm, esm_key_id_to_field_mapper_buf_entry_data, EOP_CW1f), 3735 eop_cw0 = soc_mem_field32_get(unit, ESM_KEY_ID_TO_FIELD_MAPPERm, esm_key_id_to_field_mapper_buf_entry_data, EOP_CW0f); 3736 3737 int num_tx_bytes_cw2 = hwtl_calc_num_tx_bytes(num_tx_dwords_cw2, eop_cw2), 3738 num_tx_bytes_cw1 = hwtl_calc_num_tx_bytes(num_tx_dwords_cw1, eop_cw1), 3739 num_tx_bytes_cw0 = hwtl_calc_num_tx_bytes(num_tx_dwords_cw0, eop_cw0); 3740 int num_tx_bytes = -1; 3741 3742 if (last_cword_is_optional == 0) { 3743 if (total_num_cwords == 1) { 3744 num_tx_bytes = num_tx_bytes_cw0; 3745 } else if (total_num_cwords == 2) { 3746 num_tx_bytes = num_tx_bytes_cw0 + num_tx_bytes_cw1; 3747 } else if (total_num_cwords == 3) { 3748 num_tx_bytes = num_tx_bytes_cw0 + num_tx_bytes_cw1 + num_tx_bytes_cw2; 3749 } 3750 } 3751 3752 return (num_tx_bytes); 3753 } 3754 3755 3756 STATIC int 3757 hwtl_prog_sp_entry(int unit, unsigned sp_index, unsigned ptr_fme_req, unsigned ee) 3758 { 3759 esm_search_profile_entry_t esm_search_profile_buf; 3760 3761 sal_memset(esm_search_profile_buf.entry_data, 0, sizeof(esm_search_profile_buf.entry_data)); 3762 soc_mem_field32_set(unit, ESM_SEARCH_PROFILEm, esm_search_profile_buf.entry_data, ESM_ELIGIBLEf, ee); 3763 soc_mem_field32_set(unit, ESM_SEARCH_PROFILEm, esm_search_profile_buf.entry_data, ESM_SEARCH_KEY_IDf, ptr_fme_req); 3764 _SHR_RETURN(soc_mem_write(unit, ESM_SEARCH_PROFILEm, MEM_BLOCK_ALL, sp_index, esm_search_profile_buf.entry_data)); 3765 } 3766 3767 3768 STATIC int 3769 hwtl_start(int unit, unsigned last_adr, unsigned last_iteration, unsigned endless, unsigned use_incr_cba) 3770 { 3771 { 3772 uint64 zero; 3773 3774 COMPILER_64_ZERO(zero); 3775 SOC_IF_ERROR_RETURN(soc_reg64_set(unit, ILAMAC_TX_PACKETS_COUNTr, 0, 0, zero)); 3776 SOC_IF_ERROR_RETURN(soc_reg64_set(unit, ILAMAC_RX_PACKETS_COUNTr, 0, 0, zero)); 3777 SOC_IF_ERROR_RETURN(soc_reg64_set(unit, ILAMAC_TX_BYTES_COUNTr, 0, 0, zero)); 3778 SOC_IF_ERROR_RETURN(soc_reg64_set(unit, ILAMAC_RX_BYTES_COUNTr, 0, 0, zero)); 3779 } 3780 3781 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, ETU_DBG_IPIPE_REQ_RSP_COUNTr, 0, 0, 0)); 3782 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, ETU_DBG_IPIPE_ERR_RSP_COUNTr, 0, 0, 0)); 3783 3784 { 3785 uint32 esm_misc_control_buf; 3786 3787 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, ESM_MISC_CONTROLr, 0, 0, &esm_misc_control_buf)); 3788 soc_reg_field_set(unit, ESM_MISC_CONTROLr, &esm_misc_control_buf, EXT_LOOKUP_ENABLEf, 0); 3789 soc_reg_field_set(unit, ESM_MISC_CONTROLr, &esm_misc_control_buf, ETU_REQ_SEQ_NUM_SELf, use_incr_cba); 3790 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, ESM_MISC_CONTROLr, 0, 0, esm_misc_control_buf)); 3791 } 3792 3793 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, ESM_ET_HWTL_CONTROLr, 0, 0, 0)); 3794 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, ESM_EVENT_ERR_STATUS_INTRr, 0, 0, 0)); 3795 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, ESM_ET_HWTL_STATUS_0r, 0, 0, 0)); 3796 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, ESM_ET_HWTL_STATUS_1r, 0, 0, 0)); 3797 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, ESM_ET_HWTL_MM_INFOr, 0, 0, 0)); 3798 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, ESM_ET_HWTL_EVENT_ERR_INFOr, 0, 0, 0)); 3799 3800 { 3801 uint32 esm_event_err_status_intr_enable_buf; 3802 3803 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, ESM_EVENT_ERR_STATUS_INTR_ENABLEr, 0, 0, &esm_event_err_status_intr_enable_buf)); 3804 soc_reg_field_set(unit, ESM_EVENT_ERR_STATUS_INTR_ENABLEr, &esm_event_err_status_intr_enable_buf, DROP_COUNT_MSBf, 1); 3805 soc_reg_field_set(unit, ESM_EVENT_ERR_STATUS_INTR_ENABLEr, &esm_event_err_status_intr_enable_buf, CNP_SEARCH_REQ_COUNT_MSBf, 1); 3806 soc_reg_field_set(unit, ESM_EVENT_ERR_STATUS_INTR_ENABLEr, &esm_event_err_status_intr_enable_buf, SOP_DROPf, 1); 3807 soc_reg_field_set(unit, ESM_EVENT_ERR_STATUS_INTR_ENABLEr, &esm_event_err_status_intr_enable_buf, XOFF_AXP_OVERSUBSf, 1); 3808 soc_reg_field_set(unit, ESM_EVENT_ERR_STATUS_INTR_ENABLEr, &esm_event_err_status_intr_enable_buf, MANDATORY_DENYf, 1); 3809 soc_reg_field_set(unit, ESM_EVENT_ERR_STATUS_INTR_ENABLEr, &esm_event_err_status_intr_enable_buf, DROP_ALLf, 1); 3810 soc_reg_field_set(unit, ESM_EVENT_ERR_STATUS_INTR_ENABLEr, &esm_event_err_status_intr_enable_buf, OPT_REQ_TRICKLEDf, 1); 3811 soc_reg_field_set(unit, ESM_EVENT_ERR_STATUS_INTR_ENABLEr, &esm_event_err_status_intr_enable_buf, OPTIONAL_DENYf, 1); 3812 soc_reg_field_set(unit, ESM_EVENT_ERR_STATUS_INTR_ENABLEr, &esm_event_err_status_intr_enable_buf, DROP_OPTIONALf, 1); 3813 soc_reg_field_set(unit, ESM_EVENT_ERR_STATUS_INTR_ENABLEr, &esm_event_err_status_intr_enable_buf, ET_RSP_ERRf, 1); 3814 soc_reg_field_set(unit, ESM_EVENT_ERR_STATUS_INTR_ENABLEr, &esm_event_err_status_intr_enable_buf, CNP_SEARCH_REQf, 1); 3815 soc_reg_field_set(unit, ESM_EVENT_ERR_STATUS_INTR_ENABLEr, &esm_event_err_status_intr_enable_buf, ET_REQ_FIFO_FULL_DENYf, 1); 3816 soc_reg_field_set(unit, ESM_EVENT_ERR_STATUS_INTR_ENABLEr, &esm_event_err_status_intr_enable_buf, ET_REQ_FIFO_FULLf, 1); 3817 soc_reg_field_set(unit, ESM_EVENT_ERR_STATUS_INTR_ENABLEr, &esm_event_err_status_intr_enable_buf, ADM_CTRL_FIFO_FULL_DENYf, 1); 3818 soc_reg_field_set(unit, ESM_EVENT_ERR_STATUS_INTR_ENABLEr, &esm_event_err_status_intr_enable_buf, ADM_CTRL_FIFO_FULLf, 1); 3819 soc_reg_field_set(unit, ESM_EVENT_ERR_STATUS_INTR_ENABLEr, &esm_event_err_status_intr_enable_buf, ET_RSP_FIFO_FULLf, 1); 3820 soc_reg_field_set(unit, ESM_EVENT_ERR_STATUS_INTR_ENABLEr, &esm_event_err_status_intr_enable_buf, CBA_MISMATCHf, 1); 3821 soc_reg_field_set(unit, ESM_EVENT_ERR_STATUS_INTR_ENABLEr, &esm_event_err_status_intr_enable_buf, ADM_CTRL_FIFO_UNDERFLOWf, 1); 3822 soc_reg_field_set(unit, ESM_EVENT_ERR_STATUS_INTR_ENABLEr, &esm_event_err_status_intr_enable_buf, ET_RSP_FIFO_UNDERFLOWf, 1); 3823 soc_reg_field_set(unit, ESM_EVENT_ERR_STATUS_INTR_ENABLEr, &esm_event_err_status_intr_enable_buf, ET_RSP_FIFO_OVERFLOWf, 1); 3824 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, ESM_EVENT_ERR_STATUS_INTR_ENABLEr, 0, 0, esm_event_err_status_intr_enable_buf)); 3825 } 3826 3827 { 3828 uint32 esm_et_hwtl_control_buf; 3829 3830 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, ESM_ET_HWTL_CONTROLr, 0, 0, &esm_et_hwtl_control_buf)); 3831 soc_reg_field_set(unit, ESM_ET_HWTL_CONTROLr, &esm_et_hwtl_control_buf, EN_HWTL_MODEf, 1); 3832 soc_reg_field_set(unit, ESM_ET_HWTL_CONTROLr, &esm_et_hwtl_control_buf, LAST_ITERATIONf, last_iteration); 3833 soc_reg_field_set(unit, ESM_ET_HWTL_CONTROLr, &esm_et_hwtl_control_buf, ENDLESSf, endless); 3834 soc_reg_field_set(unit, ESM_ET_HWTL_CONTROLr, &esm_et_hwtl_control_buf, LAST_HWTL_ADRf, last_adr); 3835 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, ESM_ET_HWTL_CONTROLr, 0, 0, esm_et_hwtl_control_buf)); 3836 soc_reg_field_set(unit, ESM_ET_HWTL_CONTROLr, &esm_et_hwtl_control_buf, START_HWTL_TESTf, 1); 3837 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, ESM_ET_HWTL_CONTROLr, 0, 0, esm_et_hwtl_control_buf)); 3838 } 3839 3840 _SHR_RETURN(SOC_E_NONE); 3841 } 3842 3843 3844 #if 0 3845 STATIC unsigned 3846 calc_mwps_per_lane(void) 3847 { 3848 unsigned user_words = NL_METAFRAME_LENGTH - NL_OVERHEAD_WORDS; 3849 unsigned usable_lane_speed_mbps = 3850 (NL_LANE_SPEED_MBPS * user_words) / NL_METAFRAME_LENGTH; 3851 3852 return (usable_lane_speed_mbps / NL_BITS_PER_ENC_WORD); 3853 } 3854 #endif 3855 3856 STATIC unsigned 3857 calc_mwps_per_lane_x(void) 3858 { 3859 unsigned user_words = NL_METAFRAME_LENGTH - NL_OVERHEAD_WORDS; 3860 unsigned usable_lane_speed_mbps_x = 3861 (NL_LANE_SPEED_MBPS * user_words) / NL_METAFRAME_LENGTH*1000; 3862 3863 return (usable_lane_speed_mbps_x / NL_BITS_PER_ENC_WORD); 3864 } 3865 3866 STATIC int 3867 esm_calc_new_step_size_ps(int unit, unsigned list_cost210_len, 3868 unsigned *list_cost210) 3869 { 3870 unsigned cost2_num_rsp_words, cost1_num_req_words, cost0_num_nl_cclks; 3871 unsigned nl_core_clk_freq_mhz; 3872 unsigned tmp; 3873 unsigned num_rsp_words, max_rsp_mwps, rsp_mpps, time_to_receive_rsp_ns; 3874 unsigned num_req_words, max_req_mwps, req_mpps, time_to_transmit_req_ns; 3875 unsigned num_nl_cclks, nl_core_mpps, time_for_nl_to_execute_search_ns; 3876 unsigned worst_req_proc_cost_ns, max_cost_value_can_be, step_size_ps; 3877 3878 3879 nl_core_clk_freq_mhz = nl_core_clk_freq_khz(unit)/1000; 3880 if (list_cost210_len == 3) { 3881 cost2_num_rsp_words = list_cost210[0]; 3882 cost1_num_req_words = list_cost210[1]; 3883 cost0_num_nl_cclks = list_cost210[2]; 3884 } else { 3885 /* use worst possible cost values */ 3886 cost2_num_rsp_words = 3*(1+2); 3887 cost1_num_req_words = 3+11; /* 3 CW, 11 DW */ 3888 cost0_num_nl_cclks = 1 + 1 + 2; 3889 } 3890 3891 /* mpps limited by rsp */ 3892 num_rsp_words = cost2_num_rsp_words; 3893 max_rsp_mwps = (calc_mwps_per_lane_x() * NL_NUM_RSP_LANES * 3894 (100 - REQD_RX_BW_FOR_CPU_PERCENT))/100; 3895 rsp_mpps = max_rsp_mwps / num_rsp_words; 3896 time_to_receive_rsp_ns = 1000000000 / rsp_mpps; 3897 3898 /* mpps limited by req */ 3899 num_req_words = cost1_num_req_words; /* per ipipe_pkt */ 3900 max_req_mwps = (calc_mwps_per_lane_x() * NL_NUM_REQ_LANES * 3901 (100 - REQD_TX_BW_FOR_CPU_PERCENT))/100; 3902 req_mpps = max_req_mwps / num_req_words; 3903 time_to_transmit_req_ns = 1000000000 / req_mpps; 3904 3905 /* mpps limited by nl_core_clk_freq */ 3906 num_nl_cclks = cost0_num_nl_cclks; /* per ipipe_pkt */ 3907 nl_core_mpps = ((nl_core_clk_freq_mhz * 1000 * 3908 (100 - REQD_NL_CCLK_BW_FOR_CPU_PERCENT)) / 100) / num_nl_cclks; 3909 time_for_nl_to_execute_search_ns = 1000000000 / nl_core_mpps; 3910 3911 3912 tmp = ESM_MAX(time_to_receive_rsp_ns, time_to_transmit_req_ns); 3913 worst_req_proc_cost_ns = ESM_MAX(tmp, time_for_nl_to_execute_search_ns); 3914 3915 max_cost_value_can_be = 255; /* 2**8 - 1 */ 3916 3917 /* round up */ 3918 step_size_ps = (worst_req_proc_cost_ns * 1000) / max_cost_value_can_be + 3919 ((worst_req_proc_cost_ns * 1000) % max_cost_value_can_be ? 1000 : 0); 3920 /* Is rounding-up really necessary ? - because anyways we are going to be 3921 * dividing real-numbers by step-size, so how does rouding-up to nearest 3922 * integer value help ? 3923 */ 3924 LOG_VERBOSE(BSL_LS_SOC_COMMON, 3925 (BSL_META_U(unit, 3926 "esm_calc_new_step_size_ps: "))); 3927 LOG_VERBOSE(BSL_LS_SOC_COMMON, 3928 (BSL_META_U(unit, 3929 "worst_req_proc_cost_ns=%d"), 3930 worst_req_proc_cost_ns)); 3931 LOG_VERBOSE(BSL_LS_SOC_COMMON, 3932 (BSL_META_U(unit, 3933 " step_size_ps=%d"), step_size_ps)); 3934 LOG_VERBOSE(BSL_LS_SOC_COMMON, 3935 (BSL_META_U(unit, 3936 "(num_bits_to_represent_worst_req_proc_cost=8)"))); 3937 return (step_size_ps/1000) * 1000; 3938 } 3939 3940 STATIC unsigned 3941 esm_calc_new_drop_all_cost2 (int unit, unsigned idle_req_rsp_latency_ns, 3942 unsigned step_size_ps) 3943 { 3944 /* unused */ 3945 return 0x100000 - 1; 3946 } 3947 3948 STATIC unsigned 3949 esm_calc_new_drop_all_cost1 (int unit, unsigned idle_req_rsp_latency_ns_x, 3950 unsigned step_size_ps_x) 3951 { 3952 unsigned max_allowed_qdly_ns_x, new_drop_all_cost1_qdly, esmif_clk_period_ns_x; 3953 unsigned esmif_max_allowed_latency_ns_x; 3954 unsigned esmif_clk_freq_mhz_x; 3955 3956 /* compute max_allowed_qdly */ 3957 esmif_clk_freq_mhz_x = esmif_clk_freq_khz(unit); 3958 /* carry ns upto 3 more decimal places */ 3959 esmif_clk_period_ns_x = (1000 * 1000 * 1000) / esmif_clk_freq_mhz_x; 3960 esmif_max_allowed_latency_ns_x = ESMIF_ALLOWED_FIFO_DEPTH * 3961 esmif_clk_period_ns_x; 3962 max_allowed_qdly_ns_x = esmif_max_allowed_latency_ns_x - 3963 idle_req_rsp_latency_ns_x; 3964 3965 /* compute new_drop_all_costs */ 3966 new_drop_all_cost1_qdly = (max_allowed_qdly_ns_x * 1000) / step_size_ps_x; 3967 3968 return new_drop_all_cost1_qdly; 3969 } 3970 3971 STATIC unsigned 3972 esm_calc_new_drop_all_cost0(int unit, unsigned idle_req_rsp_latency_ns_x, 3973 unsigned step_size_ps_x) 3974 { 3975 unsigned esmif_clk_freq_mhz_x = esmif_clk_freq_khz(unit); 3976 unsigned max_allowed_latency_ns_x, new_drop_all_cost0_worst_req_proc; 3977 unsigned tmp_x; 3978 3979 /* compute max_allowed_latency */ 3980 tmp_x = (1000*1000*1000)/esmif_clk_freq_mhz_x; 3981 max_allowed_latency_ns_x = ESMIF_ALLOWED_FIFO_DEPTH * tmp_x; 3982 3983 /* compute new_drop_all_costs */ 3984 new_drop_all_cost0_worst_req_proc = (max_allowed_latency_ns_x * 1000) / 3985 step_size_ps_x; 3986 3987 return new_drop_all_cost0_worst_req_proc; 3988 } 3989 3990 STATIC int 3991 esm_prog_new_drop_all_costs(int unit, unsigned idle_req_rsp_latency_ns_x, 3992 unsigned step_size_x, 3993 unsigned percent_hysteresis) 3994 { 3995 /* compute drop_all_cost as function of max_allowed_latency_ns delay */ 3996 unsigned drop_all_cost2, drop_all_cost1, drop_all_cost0; 3997 unsigned drop_all_reset_cost2, drop_all_reset_cost1, drop_all_reset_cost0; 3998 3999 drop_all_cost2 = esm_calc_new_drop_all_cost2(unit, idle_req_rsp_latency_ns_x, 4000 step_size_x); 4001 drop_all_cost1 = esm_calc_new_drop_all_cost1(unit, idle_req_rsp_latency_ns_x, 4002 step_size_x); 4003 drop_all_cost0 = esm_calc_new_drop_all_cost0(unit, idle_req_rsp_latency_ns_x, 4004 step_size_x); 4005 4006 /* compute drop_all_reset_cost as % of drop_all_cost */ 4007 drop_all_reset_cost2 = (drop_all_cost2 * percent_hysteresis) / 100; 4008 drop_all_reset_cost1 = (drop_all_cost1 * percent_hysteresis) / 100; 4009 drop_all_reset_cost0 = (drop_all_cost0 * percent_hysteresis) / 100; 4010 4011 /* program drop_all_cost */ 4012 SOC_IF_ERROR_RETURN(WRITE_ESM_ADM_THR_DROP_ALL_COST2r(unit, drop_all_cost2)); 4013 SOC_IF_ERROR_RETURN(WRITE_ESM_ADM_THR_DROP_ALL_COST1r(unit, drop_all_cost1)); 4014 SOC_IF_ERROR_RETURN(WRITE_ESM_ADM_THR_DROP_ALL_COST0r(unit, drop_all_cost0)); 4015 4016 /* program drop_all_reset_cost */ 4017 SOC_IF_ERROR_RETURN(WRITE_ESM_ADM_THR_DROP_ALL_RESET_COST2r(unit, 4018 drop_all_reset_cost2)); 4019 SOC_IF_ERROR_RETURN(WRITE_ESM_ADM_THR_DROP_ALL_RESET_COST1r(unit, 4020 drop_all_reset_cost1)); 4021 SOC_IF_ERROR_RETURN(WRITE_ESM_ADM_THR_DROP_ALL_RESET_COST0r(unit, 4022 drop_all_reset_cost0)); 4023 4024 LOG_VERBOSE(BSL_LS_SOC_COMMON, 4025 (BSL_META_U(unit, 4026 "esm_prog_drop_all_costs: drop_all_cost2=%d, "), 4027 drop_all_cost2)); 4028 LOG_VERBOSE(BSL_LS_SOC_COMMON, 4029 (BSL_META_U(unit, 4030 "drop_all_reset_cost2=%d (is "), drop_all_reset_cost2)); 4031 LOG_VERBOSE(BSL_LS_SOC_COMMON, 4032 (BSL_META_U(unit, 4033 "%d %% of drop_all_cost2"), percent_hysteresis)); 4034 4035 4036 LOG_VERBOSE(BSL_LS_SOC_COMMON, 4037 (BSL_META_U(unit, 4038 "esm_prog_drop_all_costs: drop_all_cost1=%d, "), 4039 drop_all_cost1)); 4040 LOG_VERBOSE(BSL_LS_SOC_COMMON, 4041 (BSL_META_U(unit, 4042 "drop_all_reset_cost1=%d (is "), drop_all_reset_cost1)); 4043 LOG_VERBOSE(BSL_LS_SOC_COMMON, 4044 (BSL_META_U(unit, 4045 "%d %% of drop_all_cost1"), percent_hysteresis)); 4046 4047 LOG_VERBOSE(BSL_LS_SOC_COMMON, 4048 (BSL_META_U(unit, 4049 "esm_prog_drop_all_costs: drop_all_cost0=%d, "), 4050 drop_all_cost0)); 4051 LOG_VERBOSE(BSL_LS_SOC_COMMON, 4052 (BSL_META_U(unit, 4053 "drop_all_reset_cost0=%d (is "), drop_all_reset_cost0)); 4054 LOG_VERBOSE(BSL_LS_SOC_COMMON, 4055 (BSL_META_U(unit, 4056 "%d %% of drop_all_cost0"), percent_hysteresis)); 4057 return SOC_E_NONE; 4058 } 4059 4060 STATIC int 4061 hwtl_check_done(int unit) 4062 { 4063 { 4064 uint32 esm_et_hwtl_status_0_buf; 4065 4066 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, ESM_ET_HWTL_STATUS_0r, 0, 0, &esm_et_hwtl_status_0_buf)); 4067 if (!(soc_reg_field_get(unit, ESM_ET_HWTL_STATUS_0r, esm_et_hwtl_status_0_buf, REQ_DONEf) 4068 && soc_reg_field_get(unit, ESM_ET_HWTL_STATUS_0r, esm_et_hwtl_status_0_buf, RSP_DONEf) 4069 ) 4070 ) { 4071 return (SOC_E_BUSY); 4072 } 4073 } 4074 4075 { 4076 uint32 esm_et_hwtl_status_1_buf; 4077 4078 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, ESM_ET_HWTL_STATUS_1r, 0, 0, &esm_et_hwtl_status_1_buf)); 4079 if (esm_et_hwtl_status_1_buf != 0) { 4080 _SHR_RETURN(SOC_E_FAIL); 4081 } 4082 } 4083 4084 return (SOC_E_NONE); 4085 } 4086 4087 4088 STATIC int 4089 hwtl_poll_done(int unit) 4090 { 4091 unsigned n; 4092 4093 for (n = 1000; n; --n) { 4094 int errcode = hwtl_check_done(unit); 4095 4096 if (errcode == SOC_E_BUSY) { 4097 sal_usleep(1000); /* Wait 1 ms */ 4098 continue; 4099 } 4100 4101 _SHR_RETURN(errcode); 4102 } 4103 4104 _SHR_RETURN(SOC_E_TIMEOUT); 4105 } 4106 4107 4108 STATIC int 4109 hwtl_verify_pb_counters(int unit, 4110 uint32 exp_ipipe_req_count, 4111 uint64 exp_tx_pkt_count, 4112 uint64 exp_rx_byte_count, 4113 uint64 exp_tx_byte_count, 4114 unsigned skip_exp_txrx_pbc_chk, 4115 unsigned skip_exp_ipipe_req_chk 4116 ) 4117 { 4118 unsigned errcnt = 0; 4119 4120 { 4121 uint64 cnt_mask; 4122 4123 exp_ipipe_req_count &= BITS(16); 4124 /* coverity[large_shift:FALSE] */ 4125 COMPILER_64_SET(cnt_mask, BITS(8), BITS(32)); 4126 COMPILER_64_AND(exp_tx_pkt_count, cnt_mask); 4127 COMPILER_64_AND(exp_rx_byte_count, cnt_mask); 4128 COMPILER_64_AND(exp_tx_byte_count, cnt_mask); 4129 } 4130 4131 { 4132 uint32 etu_dbg_ipipe_req_rsp_count_buf; 4133 unsigned req_count, rsp_count; 4134 4135 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, ETU_DBG_IPIPE_REQ_RSP_COUNTr, 0, 0, &etu_dbg_ipipe_req_rsp_count_buf)); 4136 req_count = soc_reg_field_get(unit, ETU_DBG_IPIPE_REQ_RSP_COUNTr, etu_dbg_ipipe_req_rsp_count_buf, REQ_COUNTf); 4137 rsp_count = soc_reg_field_get(unit, ETU_DBG_IPIPE_REQ_RSP_COUNTr, etu_dbg_ipipe_req_rsp_count_buf, RSP_COUNTf); 4138 if (rsp_count != req_count) { 4139 ++errcnt; 4140 } 4141 if (!skip_exp_ipipe_req_chk && req_count != exp_ipipe_req_count) { 4142 ++errcnt; 4143 } 4144 } 4145 4146 { 4147 uint32 etu_dbg_ipipe_err_rsp_count_buf; 4148 4149 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, ETU_DBG_IPIPE_ERR_RSP_COUNTr, 0, 0, &etu_dbg_ipipe_err_rsp_count_buf)); 4150 if (etu_dbg_ipipe_err_rsp_count_buf != 0) { 4151 ++errcnt; 4152 } 4153 } 4154 4155 { 4156 uint64 ilamac_tx_packets_count_buf, ilamac_rx_packets_count_buf; 4157 uint64 tx_pkt_count, rx_pkt_count; 4158 4159 SOC_IF_ERROR_RETURN(soc_reg64_get(unit, ILAMAC_RX_PACKETS_COUNTr, 0, 0, &ilamac_rx_packets_count_buf)); 4160 SOC_IF_ERROR_RETURN(soc_reg64_get(unit, ILAMAC_TX_PACKETS_COUNTr, 0, 0, &ilamac_tx_packets_count_buf)); 4161 rx_pkt_count = soc_reg64_field_get(unit, ILAMAC_RX_PACKETS_COUNTr, ilamac_rx_packets_count_buf, COUNTf); 4162 tx_pkt_count = soc_reg64_field_get(unit, ILAMAC_TX_PACKETS_COUNTr, ilamac_tx_packets_count_buf, COUNTf); 4163 if (COMPILER_64_NE(rx_pkt_count, tx_pkt_count)) { 4164 ++errcnt; 4165 } 4166 if (!skip_exp_txrx_pbc_chk && COMPILER_64_NE(tx_pkt_count, exp_tx_pkt_count)) { 4167 ++errcnt; 4168 } 4169 } 4170 4171 { 4172 uint64 ilamac_tx_bytes_count_buf; 4173 uint64 tx_byte_count; 4174 4175 SOC_IF_ERROR_RETURN(soc_reg64_get(unit, ILAMAC_TX_BYTES_COUNTr, 0, 0, &ilamac_tx_bytes_count_buf)); 4176 tx_byte_count = soc_reg64_field_get(unit, ILAMAC_TX_BYTES_COUNTr, ilamac_tx_bytes_count_buf, COUNTf); 4177 if (!skip_exp_txrx_pbc_chk && COMPILER_64_NE(tx_byte_count, exp_tx_byte_count)) { 4178 ++errcnt; 4179 } 4180 } 4181 4182 { 4183 uint64 ilamac_rx_bytes_count_buf; 4184 uint64 rx_byte_count; 4185 4186 SOC_IF_ERROR_RETURN(soc_reg64_get(unit, ILAMAC_RX_BYTES_COUNTr, 0, 0, &ilamac_rx_bytes_count_buf)); 4187 rx_byte_count = soc_reg64_field_get(unit, ILAMAC_RX_BYTES_COUNTr, ilamac_rx_bytes_count_buf, COUNTf); 4188 if (!skip_exp_txrx_pbc_chk && COMPILER_64_NE(rx_byte_count, exp_rx_byte_count)) { 4189 ++errcnt; 4190 } 4191 } 4192 4193 _SHR_RETURN(errcnt ? SOC_E_FAIL : SOC_E_NONE); 4194 } 4195 4196 4197 STATIC int 4198 hwtl_start_cbi(int unit, unsigned num_sp_entries, unsigned ee_entry) 4199 { 4200 unsigned endless = 0; 4201 unsigned last_iteration = (2040 / num_sp_entries) - 1; 4202 uint32 exp_ipipe_req_count = 0; 4203 uint64 exp_tx_pkt_count; 4204 uint64 exp_rx_byte_count; 4205 uint64 exp_tx_byte_count; 4206 unsigned sp_index, ee; 4207 unsigned num_iterations, last_sp_index; 4208 4209 COMPILER_64_ZERO(exp_tx_pkt_count); 4210 COMPILER_64_ZERO(exp_rx_byte_count); 4211 COMPILER_64_ZERO(exp_tx_byte_count); 4212 for (sp_index = 0; sp_index < num_sp_entries; ++sp_index) { 4213 if (sp_index == ee_entry) { 4214 esm_key_id_to_field_mapper_entry_t esm_key_id_to_field_mapper_buf; 4215 4216 ee = 1; 4217 SOC_IF_ERROR_RETURN(hwtl_prog_sp_entry(unit, sp_index, PTR_FME_REQ_CBI, ee)); 4218 SOC_IF_ERROR_RETURN(soc_mem_read(unit, ESM_KEY_ID_TO_FIELD_MAPPERm, MEM_BLOCK_ANY, PTR_FME_REQ_CBI, esm_key_id_to_field_mapper_buf.entry_data)); 4219 ++exp_ipipe_req_count; 4220 4221 COMPILER_64_ADD_32(exp_tx_pkt_count, hwtl_find_tx_pkt_count(unit, esm_key_id_to_field_mapper_buf.entry_data)); 4222 COMPILER_64_ADD_32(exp_rx_byte_count, hwtl_find_rx_byte_count(unit, esm_key_id_to_field_mapper_buf.entry_data)); 4223 COMPILER_64_ADD_32(exp_tx_byte_count, hwtl_find_tx_byte_count(unit, esm_key_id_to_field_mapper_buf.entry_data)); 4224 } else { 4225 ee = 0; 4226 SOC_IF_ERROR_RETURN(hwtl_prog_sp_entry(unit, sp_index, PTR_FME_REQ_NULL, ee)); 4227 } 4228 } 4229 4230 num_iterations = last_iteration + 1; 4231 exp_ipipe_req_count *= num_iterations; 4232 COMPILER_64_UMUL_32(exp_tx_pkt_count, num_iterations); 4233 COMPILER_64_UMUL_32(exp_rx_byte_count, num_iterations); 4234 COMPILER_64_UMUL_32(exp_tx_byte_count, num_iterations); 4235 4236 last_sp_index = num_sp_entries - 1; 4237 SOC_IF_ERROR_RETURN(hwtl_start(unit, last_sp_index, last_iteration, endless, 1)); 4238 SOC_IF_ERROR_RETURN(hwtl_poll_done(unit)); 4239 SOC_IF_ERROR_RETURN(hwtl_verify_pb_counters(unit, exp_ipipe_req_count, exp_tx_pkt_count, exp_rx_byte_count, exp_tx_byte_count, 0, 0)); 4240 4241 _SHR_RETURN(SOC_E_NONE); 4242 } 4243 4244 STATIC int 4245 hwtl_kill_endless (int unit) 4246 { 4247 4248 int rc, status; 4249 unsigned hwtl_control; 4250 uint64 zero_64; 4251 4252 SOC_IF_ERROR_RETURN(READ_ESM_ET_HWTL_CONTROLr(unit, &hwtl_control)); 4253 soc_reg_field_set(unit, ESM_ET_HWTL_CONTROLr, &hwtl_control, ENDLESSf, 0); 4254 SOC_IF_ERROR_RETURN(WRITE_ESM_ET_HWTL_CONTROLr(unit, hwtl_control)); 4255 4256 COMPILER_64_ZERO(zero_64); 4257 4258 /* wait for hwtl_done */ 4259 rc = hwtl_poll_done(unit); 4260 4261 if (!SOC_SUCCESS(rc)) { 4262 /* hwtl did not complete */ 4263 LOG_ERROR(BSL_LS_SOC_ESM, 4264 (BSL_META_U(unit, 4265 "unit: %d HWTL did not complete, will not "), unit)); 4266 LOG_ERROR(BSL_LS_SOC_ESM, 4267 (BSL_META_U(unit, 4268 "verify packet, byte counters\n"))); 4269 return rc; 4270 } else { 4271 /* hwtl had completed without mismatch */ 4272 status = hwtl_verify_pb_counters(unit, 0, zero_64, zero_64, zero_64, 4273 1, 1); 4274 if (!SOC_SUCCESS(status)) { 4275 LOG_ERROR(BSL_LS_SOC_ESM, 4276 (BSL_META_U(unit, 4277 "unit %d: HWTL test PASSED (completed without"), 4278 unit)); 4279 LOG_ERROR(BSL_LS_SOC_ESM, 4280 (BSL_META_U(unit, 4281 "mismatches), but packet, byte counters"))); 4282 LOG_ERROR(BSL_LS_SOC_ESM, 4283 (BSL_META_U(unit, 4284 "check FAILED\n"))); 4285 } else { 4286 LOG_VERBOSE(BSL_LS_SOC_COMMON, 4287 (BSL_META_U(unit, 4288 "unit %d: Packet, byte counters check also PASSED\n"), 4289 unit)); 4290 } 4291 return status; 4292 } 4293 return SOC_E_NONE; 4294 } 4295 4296 STATIC int 4297 hwtl_start_burst (int unit, int ptr_fme_req, int num_bb_req, int num_gaps, 4298 int last_iteration, int endless) 4299 { 4300 unsigned exp_ipipe_req_count = 0; /* also exp_ipipe_rsp_count */ 4301 uint64 exp_tx_pkt_count; /* also exp_rx_pkt_count, num_CWs sent */ 4302 uint64 exp_rx_byte_count; /* num of received bytes in DW */ 4303 uint64 exp_tx_byte_count; /* num of bytes transmitted in DW */ 4304 esm_key_id_to_field_mapper_entry_t fme; 4305 int rc = 0, sp_index; 4306 unsigned last_sp_index, use_incr_cba; 4307 unsigned inc_tx_pkt_count, inc_rx_byte_count, inc_tx_byte_count; 4308 unsigned last_cword_is_optional, num_iterations; 4309 4310 COMPILER_64_ZERO(exp_tx_pkt_count); 4311 COMPILER_64_ZERO(exp_rx_byte_count); 4312 COMPILER_64_ZERO(exp_tx_byte_count); 4313 /* 4314 esm_puts_fyi "hwtl_start_burst: ptr_fme_req=$ptr_fme_req, num_bb_req=$num_bb_req, num_gaps=$num_gaps, last_iteration=$last_iteration, endless=$endless"; 4315 */ 4316 SOC_IF_ERROR_RETURN(soc_mem_read(unit, ESM_KEY_ID_TO_FIELD_MAPPERm, 4317 MEM_BLOCK_ANY, ptr_fme_req, &fme)); 4318 inc_tx_pkt_count = hwtl_find_tx_pkt_count(unit, fme.entry_data); 4319 inc_rx_byte_count = hwtl_find_rx_byte_count(unit, fme.entry_data); 4320 inc_tx_byte_count = hwtl_find_tx_byte_count(unit, fme.entry_data); 4321 last_cword_is_optional = soc_ESM_KEY_ID_TO_FIELD_MAPPERm_field32_get(unit, 4322 fme.entry_data, LAST_CWORD_IS_OPTIONALf); 4323 4324 for (sp_index = 0; sp_index < num_bb_req; sp_index++) { 4325 int ee = 1; 4326 rc = hwtl_prog_sp_entry(unit, sp_index, ptr_fme_req, ee); 4327 SOC_IF_ERROR_RETURN(rc); 4328 exp_ipipe_req_count += 1; 4329 COMPILER_64_ADD_32(exp_tx_pkt_count, inc_tx_pkt_count); 4330 COMPILER_64_ADD_32(exp_rx_byte_count, inc_rx_byte_count); 4331 COMPILER_64_ADD_32(exp_tx_byte_count, inc_tx_byte_count); 4332 /* 4333 #esm_puts_fyi "ee=1, sp_index=$sp_index, ptr_fme_req=$ptr_fme_req, tx_pkt_count=$inc_tx_pkt_count, tx_byte_count=$inc_tx_byte_count, rx_byte_count=$inc_rx_byte_count"; 4334 */ 4335 } 4336 4337 for (sp_index = num_bb_req; sp_index < num_bb_req + num_gaps; sp_index++) { 4338 int ee = 0; 4339 rc = hwtl_prog_sp_entry(unit, sp_index, PTR_FME_REQ_NULL, ee); 4340 SOC_IF_ERROR_RETURN(rc); 4341 } 4342 4343 4344 /* num_iterations */ 4345 num_iterations = last_iteration + 1; 4346 exp_ipipe_req_count = exp_ipipe_req_count * num_iterations; 4347 COMPILER_64_UMUL_32(exp_tx_pkt_count, num_iterations); 4348 COMPILER_64_UMUL_32(exp_rx_byte_count, num_iterations); 4349 COMPILER_64_UMUL_32(exp_tx_byte_count, num_iterations); 4350 4351 /* kickoff */ 4352 last_sp_index = num_bb_req + num_gaps - 1; 4353 use_incr_cba = 0; /* use sp_index as cba */ 4354 rc = hwtl_start(unit, last_sp_index, last_iteration, endless, use_incr_cba); 4355 SOC_IF_ERROR_RETURN(rc); 4356 4357 4358 /* check results */ 4359 if (endless) { 4360 /* 4361 #esm_puts_fyi " WARNING: will not check for hwtl_done, will not verify packet, byte counters (ENDLESS=1), HWTL is still running"; 4362 */ 4363 LOG_VERBOSE(BSL_LS_SOC_COMMON, 4364 (BSL_META_U(unit, 4365 "unit %d: WARNING: will not check for hwtl_done,"), unit)); 4366 LOG_VERBOSE(BSL_LS_SOC_COMMON, 4367 (BSL_META_U(unit, 4368 "will not verify packet, byte counters"))); 4369 LOG_VERBOSE(BSL_LS_SOC_COMMON, 4370 (BSL_META_U(unit, 4371 "(ENDLESS=1), HWTL is still running\n"))); 4372 return SOC_E_NONE; 4373 } else { 4374 /* wait for hwtl_done */ 4375 rc = hwtl_poll_done(unit); 4376 if (rc != SOC_E_NONE) { 4377 /* hwtl did not complete */ 4378 LOG_ERROR(BSL_LS_SOC_ESM, 4379 (BSL_META_U(unit, 4380 "unit %d: HWTL did not complete !!, will not"), 4381 unit)); 4382 LOG_ERROR(BSL_LS_SOC_ESM, 4383 (BSL_META_U(unit, 4384 "verify packet, byte counters"))); 4385 return rc; 4386 } else { 4387 unsigned skip_exp_ipipe_req_chk = 0; 4388 unsigned skip_exp_txrx_pbc_chk; 4389 /* hwtl had completed without mismatch */ 4390 LOG_VERBOSE(BSL_LS_SOC_COMMON, 4391 (BSL_META_U(unit, 4392 "unit %d: HWTL PASSED (completed"), unit)); 4393 LOG_VERBOSE(BSL_LS_SOC_COMMON, 4394 (BSL_META_U(unit, 4395 "without mismatch), will now verify "))); 4396 LOG_VERBOSE(BSL_LS_SOC_COMMON, 4397 (BSL_META_U(unit, 4398 "packet, byte counters\n"))); 4399 skip_exp_txrx_pbc_chk = last_cword_is_optional; 4400 rc = hwtl_verify_pb_counters(unit, exp_ipipe_req_count, 4401 exp_tx_pkt_count, exp_rx_byte_count, 4402 exp_tx_byte_count, 4403 skip_exp_txrx_pbc_chk, 4404 skip_exp_ipipe_req_chk); 4405 if (rc != SOC_E_NONE) { 4406 LOG_ERROR(BSL_LS_SOC_ESM, 4407 (BSL_META_U(unit, 4408 "unit: %d HWTL PASSED (completed without "), 4409 unit)); 4410 LOG_ERROR(BSL_LS_SOC_ESM, 4411 (BSL_META_U(unit, 4412 "mismatches), but packet, byte counters "))); 4413 LOG_ERROR(BSL_LS_SOC_ESM, 4414 (BSL_META_U(unit, 4415 "check FAILED !!"))); 4416 } else { 4417 LOG_VERBOSE(BSL_LS_SOC_COMMON, 4418 (BSL_META_U(unit, 4419 "unit: %d Packet, byte counters check"), 4420 unit)); 4421 LOG_VERBOSE(BSL_LS_SOC_COMMON, 4422 (BSL_META_U(unit, 4423 " also PASSED"))); 4424 } 4425 return rc; 4426 } 4427 } 4428 } 4429 4430 int 4431 hwtl_find_idle_req_rsp_latency(int unit, int ptr_fme_req, 4432 int test_runtime_seconds, 4433 unsigned *latency_ns) 4434 { 4435 int num_bb_req = 1, num_gaps=299; 4436 int endless, last_iteration; 4437 int failed = 0, junk; 4438 int rv = 0, index=0; 4439 unsigned esmif_max_latency_recorded, esmif_clk_period_ns; 4440 4441 LOG_VERBOSE(BSL_LS_SOC_COMMON, 4442 (BSL_META_U(unit, 4443 "test_runtime_seconds=%d\n"),test_runtime_seconds)); 4444 if (test_runtime_seconds <= 0) { 4445 endless = 0; 4446 last_iteration = test_runtime_seconds * -1; 4447 failed = hwtl_start_burst(unit, ptr_fme_req, num_bb_req, num_gaps, 4448 last_iteration, endless); 4449 } else { 4450 endless = 1; 4451 last_iteration = 0; 4452 junk = hwtl_start_burst(unit, ptr_fme_req, num_bb_req, num_gaps, 4453 last_iteration, endless); 4454 /* above will never return non-zero because endless=1 */ 4455 SOC_IF_ERROR_RETURN(junk); 4456 4457 sal_sleep(test_runtime_seconds); 4458 4459 failed = hwtl_kill_endless(unit); 4460 } 4461 4462 if (failed) { 4463 LOG_ERROR(BSL_LS_SOC_ESM, 4464 (BSL_META_U(unit, 4465 "unit %d: hwtl_find_idle_req_rsp_latency: FAILED !!\n"), 4466 unit)); 4467 rv = SOC_E_FAIL; 4468 } else { 4469 /* num_esmif_clks */ 4470 rv = READ_ESM_MAX_LATENCY_RECORDEDr(unit, &esmif_max_latency_recorded); 4471 SOC_IF_ERROR_RETURN(rv); 4472 esmif_clk_period_ns = (1000 * 1000 * 1000)/esmif_clk_freq_khz(unit); 4473 *latency_ns = esmif_clk_period_ns * esmif_max_latency_recorded; 4474 4475 if (esmif_max_latency_recorded > ESMIF_MAX_FIFO_DEPTH) { 4476 LOG_ERROR(BSL_LS_SOC_ESM, 4477 (BSL_META_U(unit, 4478 "unit %d: ESMIF.MAX_LATENCY_RECORDED = "), unit)); 4479 LOG_ERROR(BSL_LS_SOC_ESM, 4480 (BSL_META_U(unit, 4481 "%d !! - number "), esmif_max_latency_recorded)); 4482 LOG_ERROR(BSL_LS_SOC_ESM, 4483 (BSL_META_U(unit, 4484 "greater than %d means "), ESMIF_MAX_FIFO_DEPTH )); 4485 LOG_ERROR(BSL_LS_SOC_ESM, 4486 (BSL_META_U(unit, 4487 "catastrophy !!\n"))); 4488 rv = SOC_E_FAIL; 4489 } else if (esmif_max_latency_recorded > ESMIF_ALLOWED_FIFO_DEPTH) { 4490 LOG_VERBOSE(BSL_LS_SOC_COMMON, 4491 (BSL_META_U(unit, 4492 "unit %d: ESMIF.MAX_LATENCY_RECORDED = "), 4493 unit)); 4494 LOG_VERBOSE(BSL_LS_SOC_COMMON, 4495 (BSL_META_U(unit, 4496 "%d !! - which "),esmif_max_latency_recorded )); 4497 LOG_VERBOSE(BSL_LS_SOC_COMMON, 4498 (BSL_META_U(unit, 4499 "is greater than budgeted %d !!"), 4500 ESMIF_ALLOWED_FIFO_DEPTH)); 4501 LOG_VERBOSE(BSL_LS_SOC_COMMON, 4502 (BSL_META_U(unit, 4503 "@ %d MHz,this \n corresponds to latency of %d nS"), 4504 esmif_clk_freq_khz(unit)/1000, *latency_ns)); 4505 rv = SOC_E_NONE; 4506 } else { 4507 LOG_VERBOSE(BSL_LS_SOC_COMMON, 4508 (BSL_META_U(unit, 4509 "ESMIF.MAX_LATENCY_RECORDED = %d "), 4510 esmif_max_latency_recorded)); 4511 LOG_VERBOSE(BSL_LS_SOC_COMMON, 4512 (BSL_META_U(unit, 4513 "(num_esmif_clks) @ %d MHz, this "), 4514 esmif_clk_freq_khz(unit)/1000)); 4515 LOG_VERBOSE(BSL_LS_SOC_COMMON, 4516 (BSL_META_U(unit, 4517 "corresponds \n to latency of %d nS\n"), 4518 *latency_ns)); 4519 rv = SOC_E_NONE; 4520 } 4521 } 4522 4523 /* Cleanup */ 4524 for (index = 0; index < (num_bb_req + num_gaps); index++) { 4525 SOC_IF_ERROR_RETURN(hwtl_prog_sp_entry(unit, index, 0, 0)); 4526 } 4527 return rv; 4528 4529 } 4530 4531 STATIC int 4532 nl_ctx_buf_reg_write_loc80(int unit, unsigned dev_id, unsigned location, nl_reg_buf_t wr_data) 4533 { 4534 _SHR_RETURN(nl_reg_write(unit, dev_id, NL_REG_ADDR_CONTEXT_BUFFER_BASE + location, wr_data, 0, 0, 0)); 4535 } 4536 4537 4538 STATIC int 4539 nl_ctx_buf_init(int unit, unsigned num_nl, unsigned use_hwtl) 4540 { 4541 unsigned first_location; 4542 4543 if (use_hwtl) { 4544 const unsigned num_sp_entries = 10; 4545 4546 unsigned dev_id, ee_entry; 4547 4548 SOC_IF_ERROR_RETURN(hwtl_zero_out_esm_range_check(unit)); 4549 SOC_IF_ERROR_RETURN(hwtl_prog_fme_req_cbi(unit)); 4550 SOC_IF_ERROR_RETURN(hwtl_prog_fme_rsp_cbi(unit)); 4551 for (dev_id = 0; dev_id < num_nl; ++dev_id) { 4552 SOC_IF_ERROR_RETURN(hwtl_prog_ltr_cbi(unit, dev_id)); 4553 } 4554 for (ee_entry = 0; ee_entry < num_sp_entries; ++ee_entry) { 4555 SOC_IF_ERROR_RETURN(hwtl_start_cbi(unit, num_sp_entries, ee_entry)); 4556 } 4557 4558 first_location = (0x7f7 + 1) << 3; 4559 } else { 4560 first_location = 0; 4561 } 4562 4563 { 4564 unsigned dev_id; 4565 nl_reg_buf_t wr_data; 4566 4567 sal_memset(wr_data, 0, sizeof(wr_data)); 4568 for (dev_id = 0; dev_id < num_nl; ++dev_id) { 4569 unsigned location; 4570 4571 for (location = first_location; location < 0x4000; ++location) { 4572 SOC_IF_ERROR_RETURN(nl_ctx_buf_reg_write_loc80(unit, dev_id, location, wr_data)); 4573 } 4574 } 4575 } 4576 4577 _SHR_RETURN(SOC_E_NONE); 4578 } 4579 4580 4581 STATIC int 4582 nl_prog_dev_cfg_reg(int unit, unsigned dev_id, unsigned en_nl_parity_scan) 4583 { 4584 nl_reg_buf_t nl_reg_dev_cfg_buf; 4585 4586 sal_memset(nl_reg_dev_cfg_buf, 0, sizeof(nl_reg_dev_cfg_buf)); 4587 nl_reg_buf_bitfield_set(nl_reg_dev_cfg_buf, 7, 1, 1); /* db_parity_error_entry_invalidate = 1*/ 4588 if (en_nl_parity_scan) { 4589 nl_reg_buf_bitfield_set(nl_reg_dev_cfg_buf, 6, 1, 1); /* soft_error_scan_enable = 1*/ 4590 } 4591 SOC_IF_ERROR_RETURN(nl_reg_write(unit, dev_id, NL_REG_ADDR_DEV_CFG, nl_reg_dev_cfg_buf, 0, 0, 0)); 4592 4593 _SHR_RETURN(SOC_E_NONE); 4594 } 4595 4596 4597 STATIC int 4598 nl_cfg_low_power_mode(int unit, unsigned num_nl, unsigned num_blks, unsigned *blknums) 4599 { 4600 nl_reg_buf_t reg0_data, reg1_data, reg2_data, reg3_data; 4601 4602 sal_memset(reg0_data, 0, sizeof(reg0_data)); 4603 sal_memset(reg1_data, 0, sizeof(reg1_data)); 4604 sal_memset(reg2_data, 0, sizeof(reg2_data)); 4605 sal_memset(reg3_data, 0, sizeof(reg3_data)); 4606 4607 for ( ; num_blks; --num_blks, ++blknums) { 4608 unsigned blknum = *blknums; 4609 4610 if (blknum >= 128) { 4611 _SHR_RETURN(SOC_E_FAIL); 4612 } 4613 if (blknum >= 96) { 4614 nl_reg_buf_bitfield_set(reg3_data, blknum - 96, 1, 1); 4615 } else if (blknum >= 64) { 4616 nl_reg_buf_bitfield_set(reg2_data, blknum - 64, 1, 1); 4617 } else if (blknum >= 32) { 4618 nl_reg_buf_bitfield_set(reg1_data, blknum - 32, 1, 1); 4619 } else { 4620 nl_reg_buf_bitfield_set(reg0_data, blknum, 1, 1); 4621 } 4622 } 4623 4624 SOC_IF_ERROR_RETURN(nl_reg_write(unit, 0, NL_REG_ADDR_LPM_ENABLE, reg0_data, 0, 0, 0)); 4625 sal_usleep(1); /* Wait 1 us */ 4626 if (num_nl > 1) { 4627 SOC_IF_ERROR_RETURN(nl_reg_write(unit, 1, NL_REG_ADDR_LPM_ENABLE, reg1_data, 0, 0, 0)); 4628 sal_usleep(1); /* Wait 1 us */ 4629 } 4630 if (num_nl > 2) { 4631 SOC_IF_ERROR_RETURN(nl_reg_write(unit, 2, NL_REG_ADDR_LPM_ENABLE, reg2_data, 0, 0, 0)); 4632 sal_usleep(1); /* Wait 1 us */ 4633 } 4634 if (num_nl > 3) { 4635 SOC_IF_ERROR_RETURN(nl_reg_write(unit, 3, NL_REG_ADDR_LPM_ENABLE, reg3_data, 0, 0, 0)); 4636 sal_usleep(1); /* Wait 1 us */ 4637 } 4638 4639 _SHR_RETURN(SOC_E_NONE); 4640 } 4641 4642 4643 STATIC int 4644 chk_misc_config(int unit) 4645 { 4646 unsigned errcnt = 0; 4647 4648 { 4649 static const struct { 4650 soc_field_t fld; 4651 uint32 exp_val; 4652 } flds[] = { 4653 { BIT_ORDER_INVERTf, 1 }, 4654 { TX_XOFF_MODEf, 0 }, 4655 { TX_ENABLEf, 1 }, 4656 { XON_RX_CH1f, 0 }, 4657 { XON_RX_CH0f, 1 }, 4658 { TX_RLIM_ENABLEf, 0 }, 4659 { TX_RDYOUT_THRESHf, 0 }, 4660 { TX_DISABLE_SKIPWORDf, 0 }, 4661 { TX_BURSTSHORTf, 1 }, 4662 { TX_BURSTMAXf, 1 }, 4663 { TX_MFRAMELEN_MINUS1f, 2047 } 4664 }; 4665 4666 uint32 ilamac_tx_config0_buf; 4667 unsigned i; 4668 4669 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, ILAMAC_TX_CONFIG0r, 0, 0, &ilamac_tx_config0_buf)); 4670 for (i = 0; i < COUNTOF(flds); ++i) { 4671 if (soc_reg_field_get(unit, ILAMAC_TX_CONFIG0r, ilamac_tx_config0_buf, flds[i].fld) != flds[i].exp_val) { 4672 ++errcnt; 4673 } 4674 } 4675 } 4676 4677 { 4678 uint32 ilamac_tx_config1_buf; 4679 4680 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, ILAMAC_TX_CONFIG1r, 0, 0, &ilamac_tx_config1_buf)); 4681 if (ilamac_tx_config1_buf != 0) { 4682 ++errcnt; 4683 } 4684 } 4685 4686 { 4687 static struct { 4688 soc_field_t fld; 4689 uint32 exp_val; 4690 } flds[] = { 4691 { TX_CW56_RSVDf, 0 }, 4692 { TX_CW_CP_CBA_MSBf, 0x7f8 }, 4693 { TX_CW_CP_CBA_LSBf, 0 }, 4694 { TX_CW_CHNLf, 0 }, 4695 { TX_CW_ERR_STATUSf, 0 }, 4696 { TX_CW29_27_RSVDf, 0 }, 4697 { TX_LAST_LANEf, 23 }, 4698 { TX_HAS_BAD_LANEf, 0 } 4699 }; 4700 4701 uint32 ilamac_tx_config2_buf; 4702 unsigned i; 4703 4704 unsigned int nl_16lane_mode = 0; 4705 4706 if (((soc_tcam_info_t *) SOC_CONTROL(unit)->tcam_info)->num_tcams == 2) { 4707 nl_16lane_mode = 1; 4708 } 4709 4710 if (nl_16lane_mode) { 4711 /* Cascaded mode: set num lanes to 16 */ 4712 flds[6].exp_val = 15; 4713 } 4714 4715 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, ILAMAC_TX_CONFIG2r, 0, 0, &ilamac_tx_config2_buf)); 4716 for (i = 0; i < COUNTOF(flds); ++i) { 4717 if (soc_reg_field_get(unit, ILAMAC_TX_CONFIG2r, ilamac_tx_config2_buf, flds[i].fld) != flds[i].exp_val) { 4718 ++errcnt; 4719 } 4720 } 4721 } 4722 4723 { 4724 static const struct { 4725 soc_field_t fld; 4726 uint32 exp_val; 4727 } flds[] = { 4728 { TX_DIAGWORD_INTFSTATf, 1 }, 4729 { TX_DIAGWORD_LANESTATf, 0xffffff } 4730 }; 4731 4732 uint32 ilamac_tx_config3_buf; 4733 unsigned i; 4734 4735 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, ILAMAC_TX_CONFIG3r, 0, 0, &ilamac_tx_config3_buf)); 4736 for (i = 0; i < COUNTOF(flds); ++i) { 4737 if (soc_reg_field_get(unit, ILAMAC_TX_CONFIG3r, ilamac_tx_config3_buf, flds[i].fld) != flds[i].exp_val) { 4738 ++errcnt; 4739 } 4740 } 4741 } 4742 4743 { 4744 uint32 ilamac_tx_config4_buf; 4745 4746 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, ILAMAC_TX_CONFIG4r, 0, 0, &ilamac_tx_config4_buf)); 4747 if (ilamac_tx_config4_buf != 0) { 4748 ++errcnt; 4749 } 4750 } 4751 4752 { 4753 uint32 ilamac_tx_config5_buf; 4754 4755 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, ILAMAC_TX_CONFIG5r, 0, 0, &ilamac_tx_config5_buf)); 4756 if (ilamac_tx_config5_buf != 0) { 4757 ++errcnt; 4758 } 4759 } 4760 4761 { 4762 static const struct { 4763 soc_field_t fld; 4764 uint32 exp_val; 4765 } flds[] = { 4766 { BIT_ORDER_INVERTf, 1 }, 4767 { RX_FORCE_RESYNCf, 0 }, 4768 { RX_LAST_LANEf, 11 }, 4769 { RX_HAS_BAD_LANEf, 0 }, 4770 { RX_BURSTMAXf, 0 }, 4771 { RX_MFRAMELEN_MINUS1f, 2047 } 4772 }; 4773 4774 uint32 ilamac_rx_config_buf; 4775 unsigned i; 4776 4777 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, ILAMAC_RX_CONFIGr, 0, 0, &ilamac_rx_config_buf)); 4778 for (i = 0; i < COUNTOF(flds); ++i) { 4779 if (soc_reg_field_get(unit, ILAMAC_RX_CONFIGr, ilamac_rx_config_buf, flds[i].fld) != flds[i].exp_val) { 4780 ++errcnt; 4781 } 4782 } 4783 } 4784 4785 { 4786 static const struct { 4787 soc_field_t fld; 4788 uint32 exp_val; 4789 } flds[] = { 4790 { HBIT_MEM_PSM_VDDf, 0 }, 4791 { EXT_TCAM_DENSITYf, 2 } 4792 }; 4793 4794 uint32 etu_config0_buf; 4795 unsigned i; 4796 4797 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, ETU_CONFIG0r, 0, 0, &etu_config0_buf)); 4798 for (i = 0; i < COUNTOF(flds); ++i) { 4799 if (soc_reg_field_get(unit, ETU_CONFIG0r, etu_config0_buf, flds[i].fld) != flds[i].exp_val) { 4800 ++errcnt; 4801 } 4802 } 4803 } 4804 4805 { 4806 static const struct { 4807 soc_field_t fld; 4808 uint32 exp_val; 4809 } flds[] = { 4810 { LTR_CP_EXT_L2_ALLf, 0x3f }, 4811 { LTR_CP_EXT_L2_WIDEf, 0x3e }, 4812 { LTR_CP_EXT_L2f, 0x3d } 4813 }; 4814 4815 uint64 etu_config1_buf; 4816 unsigned i; 4817 4818 SOC_IF_ERROR_RETURN(soc_reg64_get(unit, ETU_CONFIG1r, 0, 0, &etu_config1_buf)); 4819 for (i = 0; i < COUNTOF(flds); ++i) { 4820 if (soc_reg64_field32_get(unit, ETU_CONFIG1r, etu_config1_buf, flds[i].fld) != flds[i].exp_val) { 4821 ++errcnt; 4822 } 4823 } 4824 } 4825 4826 { 4827 static const struct { 4828 soc_field_t fld; 4829 uint32 exp_val; 4830 } flds[] = { 4831 { ET_POST_WR_ENABLEf, 1 }, 4832 { DB_WR_MODEf, 0 } 4833 }; 4834 4835 uint32 etu_config2_buf; 4836 unsigned i; 4837 4838 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, ETU_CONFIG2r, 0, 0, &etu_config2_buf)); 4839 for (i = 0; i < COUNTOF(flds); ++i) { 4840 if (soc_reg_field_get(unit, ETU_CONFIG2r, etu_config2_buf, flds[i].fld) != flds[i].exp_val) { 4841 ++errcnt; 4842 } 4843 } 4844 } 4845 4846 { 4847 static const struct { 4848 soc_field_t fld; 4849 uint32 exp_val; 4850 } flds[] = { 4851 { WR_DB_NUM_NOPf, 0 }, 4852 { WR_DB_NOP_MODEf, 0 }, 4853 { IGNORE_RX_CW_CBA_MMf, 0 }, 4854 { IGNORE_RX_CW_OPC_MMf, 0 }, 4855 { IGNORE_RX_CW_CH_ERRf, 0 }, 4856 { MIN_RX_PKT_LEN_16Bf, 0 }, 4857 { CHK_PAR_XLAT1f, 1 }, 4858 { CHK_PAR_XLAT0f, 1 }, 4859 { GEN_PAR_XLAT1f, 1 }, 4860 { GEN_PAR_XLAT0f, 1 }, 4861 { GEN_PAR_L2_ENTRY_DATAf, 1 }, 4862 { GEN_PAR_L2_ENTRY_DATA_WIDEf, 1 }, 4863 { GEN_PAR_DEFIP_DATAf, 1 }, 4864 { GEN_PAR_L3_UCAST_DATAf, 1 }, 4865 { GEN_PAR_L3_UCAST_DATA_WIDEf, 1 }, 4866 { GEN_PAR_FP_POLICY_1Xf, 1 }, 4867 { GEN_PAR_FP_POLICY_2Xf, 1 }, 4868 { GEN_PAR_FP_POLICY_3Xf, 1 }, 4869 { GEN_PAR_FP_POLICY_4Xf, 1 }, 4870 { GEN_PAR_FP_POLICY_6Xf, 1 }, 4871 { CHK_PAR_L2_ENTRY_DATAf, 1 }, 4872 { CHK_PAR_L2_ENTRY_DATA_WIDEf, 1 }, 4873 { CHK_PAR_DEFIP_DATAf, 1 }, 4874 { CHK_PAR_L3_UCAST_DATAf, 1 }, 4875 { CHK_PAR_L3_UCAST_DATA_WIDEf, 1 }, 4876 { CHK_PAR_FP_POLICY_1Xf, 1 }, 4877 { CHK_PAR_FP_POLICY_2Xf, 1 }, 4878 { CHK_PAR_FP_POLICY_3Xf, 1 }, 4879 { CHK_PAR_FP_POLICY_4Xf, 1 }, 4880 { CHK_PAR_FP_POLICY_6Xf, 1 } 4881 }; 4882 4883 uint32 etu_config3_buf; 4884 unsigned i; 4885 4886 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, ETU_CONFIG3r, 0, 0, &etu_config3_buf)); 4887 for (i = 0; i < COUNTOF(flds); ++i) { 4888 if (soc_reg_field_get(unit, ETU_CONFIG3r, etu_config3_buf, flds[i].fld) != flds[i].exp_val) { 4889 ++errcnt; 4890 } 4891 } 4892 } 4893 4894 { 4895 static const struct { 4896 soc_field_t fld; 4897 uint32 exp_val; 4898 } flds[] = { 4899 { DATAPATH_RST_f, 0 }, 4900 { ILAMAC_RX_SERDES_RST_f, 0xfff }, 4901 { ILAMAC_RX_LBUS_RST_f, 1 }, 4902 { ILAMAC_TX_SERDES_RST_f, 1 }, 4903 { ILAMAC_TX_LBUS_RST_f, 1 }, 4904 { EXT_TCAM_CRST_Lf, 1 }, 4905 { EXT_TCAM_SRST_Lf, 1 } 4906 }; 4907 4908 uint32 etu_config4_buf; 4909 unsigned i; 4910 4911 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, ETU_CONFIG4r, 0, 0, &etu_config4_buf)); 4912 for (i = 0; i < COUNTOF(flds); ++i) { 4913 if (soc_reg_field_get(unit, ETU_CONFIG4r, etu_config4_buf, flds[i].fld) != flds[i].exp_val) { 4914 ++errcnt; 4915 } 4916 } 4917 } 4918 4919 { 4920 uint32 etu_rrfe_wait_timer_buf, cnt; 4921 4922 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, ETU_RRFE_WAIT_TIMERr, 0, 0, &etu_rrfe_wait_timer_buf)); 4923 cnt = soc_reg_field_get(unit, ETU_RRFE_WAIT_TIMERr, etu_rrfe_wait_timer_buf, CNTf); 4924 if (cnt == 0xffffff || (cnt > 0 && cnt < 15)) { 4925 ++errcnt; 4926 } 4927 } 4928 4929 { 4930 static const struct { 4931 soc_field_t fld; 4932 uint32 exp_val; 4933 } flds[] = { 4934 { INJECT_SEC_EVf, 0 }, 4935 { INJECT_DED_EVf, 0 }, 4936 { INJECT_SEC_ODf, 0 }, 4937 { INJECT_DED_ODf, 0 }, 4938 { DIS_CHK_ECC_EVf, 0 }, 4939 { DIS_CHK_ECC_ODf, 0 }, 4940 { SHOW_CUR_CNTf, 0 }, 4941 { EARLY_FULL_THRf, 700 }, 4942 { CP_ACC_THRf, 200 } 4943 }; 4944 4945 uint32 etu_tx_req_fifo_ctl_buf; 4946 unsigned i; 4947 4948 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, ETU_TX_REQ_FIFO_CTLr, 0, 0, &etu_tx_req_fifo_ctl_buf)); 4949 for (i = 0; i < COUNTOF(flds); ++i) { 4950 if (soc_reg_field_get(unit, ETU_TX_REQ_FIFO_CTLr, etu_tx_req_fifo_ctl_buf, flds[i].fld) != flds[i].exp_val) { 4951 ++errcnt; 4952 } 4953 } 4954 } 4955 4956 { 4957 static const struct { 4958 soc_field_t fld; 4959 uint32 exp_val; 4960 } flds[] = { 4961 { INJECT_SECf, 0 }, 4962 { INJECT_DEDf, 0 }, 4963 { DIS_CHK_ECCf, 0 }, 4964 { SHOW_CUR_CNTf, 0 }, 4965 { EARLY_FULL_THRf, 1015 } 4966 }; 4967 4968 uint32 etu_tx_pipe_ctl_fifo_ctl_buf; 4969 unsigned i; 4970 4971 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, ETU_TX_PIPE_CTL_FIFO_CTLr, 0, 0, &etu_tx_pipe_ctl_fifo_ctl_buf)); 4972 for (i = 0; i < COUNTOF(flds); ++i) { 4973 if (soc_reg_field_get(unit, ETU_TX_PIPE_CTL_FIFO_CTLr, etu_tx_pipe_ctl_fifo_ctl_buf, flds[i].fld) != flds[i].exp_val) { 4974 ++errcnt; 4975 } 4976 } 4977 } 4978 4979 { 4980 static const struct { 4981 soc_field_t fld; 4982 uint32 exp_val; 4983 } flds[] = { 4984 { INJECT_SEC_EVf, 0 }, 4985 { INJECT_DED_EVf, 0 }, 4986 { INJECT_SEC_ODf, 0 }, 4987 { INJECT_DED_ODf, 0 }, 4988 { DIS_CHK_ECCf, 0 }, 4989 { SHOW_CUR_CNTf, 0 }, 4990 { XOFF_RX_THRf, 200 }, 4991 { XON_RX_THRf, 150 } 4992 }; 4993 4994 uint32 etu_rx_rsp_fifo_ctl_buf; 4995 unsigned i; 4996 4997 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, ETU_RX_RSP_FIFO_CTLr, 0, 0, &etu_rx_rsp_fifo_ctl_buf)); 4998 for (i = 0; i < COUNTOF(flds); ++i) { 4999 if (soc_reg_field_get(unit, ETU_RX_RSP_FIFO_CTLr, etu_rx_rsp_fifo_ctl_buf, flds[i].fld) != flds[i].exp_val) { 5000 ++errcnt; 5001 } 5002 } 5003 } 5004 5005 { 5006 static const struct { 5007 soc_field_t fld; 5008 uint32 exp_val; 5009 } flds[] = { 5010 { RX_RESET_Nf, 0 }, 5011 { STARTf, 0 }, 5012 { ENABLEf, 0 } 5013 }; 5014 5015 uint32 etu_bist_ctl_buf; 5016 unsigned i; 5017 5018 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, ETU_BIST_CTLr, 0, 0, &etu_bist_ctl_buf)); 5019 for (i = 0; i < COUNTOF(flds); ++i) { 5020 if (soc_reg_field_get(unit, ETU_BIST_CTLr, etu_bist_ctl_buf, flds[i].fld) != flds[i].exp_val) { 5021 ++errcnt; 5022 } 5023 } 5024 } 5025 5026 { 5027 static const struct { 5028 soc_field_t fld; 5029 uint32 exp_val; 5030 } flds[] = { 5031 { ACLf, 3 }, 5032 { SIPf, 1 }, 5033 { DIPf, 2 }, 5034 { DAf, 2 }, 5035 { SAf, 0 } 5036 }; 5037 5038 uint32 esm_request_lane_map_buf; 5039 unsigned i; 5040 5041 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, ESM_REQUEST_LANE_MAPr, 0, 0, &esm_request_lane_map_buf)); 5042 for (i = 0; i < COUNTOF(flds); ++i) { 5043 if (soc_reg_field_get(unit, ESM_REQUEST_LANE_MAPr, esm_request_lane_map_buf, flds[i].fld) != flds[i].exp_val) { 5044 ++errcnt; 5045 } 5046 } 5047 } 5048 5049 { 5050 static const struct { 5051 soc_field_t fld; 5052 uint32 exp_val; 5053 } flds[] = { 5054 { FORCE_ADM_CTRL_FIFO_READf, 0 }, 5055 { FORCE_ET_RSP_FIFO_READf, 0 }, 5056 { FORCE_L2ETU_ACKf, 0 }, 5057 { ETU_REQ_SEQ_NUM_SELf, 1 }, 5058 { EXT_LOOKUP_ENABLEf, 1 } 5059 }; 5060 5061 uint32 esm_misc_control_buf; 5062 unsigned i; 5063 5064 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, ESM_MISC_CONTROLr, 0, 0, &esm_misc_control_buf)); 5065 for (i = 0; i < COUNTOF(flds); ++i) { 5066 if (soc_reg_field_get(unit, ESM_MISC_CONTROLr, esm_misc_control_buf, flds[i].fld) != flds[i].exp_val) { 5067 ++errcnt; 5068 } 5069 } 5070 if (soc_reg_field_get(unit, ESM_MISC_CONTROLr, esm_misc_control_buf, MAX_CONTEXT_ADR_MSBf) > 0x7f7) { 5071 ++errcnt; 5072 } 5073 } 5074 5075 { 5076 static const struct { 5077 soc_field_t fld; 5078 uint32 exp_val; 5079 } flds[] = { 5080 { SER_STATUS_BUS_INJECT_DBEf , 0 }, 5081 { SER_STATUS_BUS_INJECT_SBEf, 0 }, 5082 { SER_STATUS_BUS_ECC_ENf, 1 }, 5083 { CTRL_BUS_FIFO_1_INJECT_DBEf, 0 }, 5084 { CTRL_BUS_FIFO_1_INJECT_SBEf, 0 }, 5085 { CTRL_BUS_FIFO_1_ECC_ENf, 1 }, 5086 { CTRL_BUS_FIFO_INJECT_DBEf, 0 }, 5087 { CTRL_BUS_FIFO_INJECT_SBEf, 0 }, 5088 { CTRL_BUS_FIFO_ECC_ENf, 1 }, 5089 { AUX1_FIFO_INJECT_DBEf, 0 }, 5090 { AUX1_FIFO_INJECT_SBEf, 0 }, 5091 { AUX1_FIFO_ECC_ENf, 1 }, 5092 { ADM_CTRL_FIFO_INJECT_DBEf, 0 }, 5093 { ADM_CTRL_FIFO_INJECT_SBEf, 0 }, 5094 { ADM_CTRL_FIFO_ECC_ENf, 1 }, 5095 { ET_RSP_FIFO_INJECT_DBEf, 0 }, 5096 { ET_RSP_FIFO_INJECT_SBEf, 0 }, 5097 { ET_RSP_FIFO_ECC_ENf, 1 } 5098 }; 5099 5100 uint32 iesmif_ecc_control_buf; 5101 unsigned i; 5102 5103 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, IESMIF_ECC_CONTROLr, 0, 0, &iesmif_ecc_control_buf)); 5104 for (i = 0; i < COUNTOF(flds); ++i) { 5105 if (soc_reg_field_get(unit, IESMIF_ECC_CONTROLr, iesmif_ecc_control_buf, flds[i].fld) != flds[i].exp_val) { 5106 ++errcnt; 5107 } 5108 } 5109 } 5110 5111 { 5112 static const struct { 5113 soc_field_t fld; 5114 uint32 exp_val; 5115 } flds[] = { 5116 { IESMIF_BUS_FORCE_ERRORf, 0 }, 5117 { IESMIF_BUS_PARITY_ENf, 0 }, 5118 { L3_PROTOCOL_FN_PARITY_ENf, 1 }, 5119 { KEY_ID_TO_FIELD_MAPPER_PARITY_ENf, 1 }, 5120 { SEARCH_PROFILE_PARITY_ENf, 1 }, 5121 { PKT_TYPE_ID_PARITY_ENf, 1 }, 5122 { AD_6X_PARITY_ENf, 1 }, 5123 { AD_4X_PARITY_ENf, 1 }, 5124 { AD_3X_PARITY_ENf, 1 }, 5125 { AD_2X_PARITY_ENf, 1 }, 5126 { AD_1X_PARITY_ENf, 1 } 5127 }; 5128 5129 uint32 iesmif_parity_control_buf; 5130 unsigned i; 5131 5132 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, IESMIF_PARITY_CONTROLr, 0, 0, &iesmif_parity_control_buf)); 5133 for (i = 0; i < COUNTOF(flds); ++i) { 5134 if (soc_reg_field_get(unit, IESMIF_PARITY_CONTROLr, iesmif_parity_control_buf, flds[i].fld) != flds[i].exp_val) { 5135 ++errcnt; 5136 } 5137 } 5138 } 5139 5140 _SHR_RETURN(errcnt ? SOC_E_FAIL : SOC_E_NONE); 5141 } 5142 5143 5144 STATIC int 5145 nl_mdio_chk_csm_counters(int unit, unsigned mdio_portid, unsigned chk_crx) 5146 { 5147 return (SOC_E_NONE); 5148 } 5149 5150 5151 STATIC int 5152 nl_mdio_chk_error_counters_status(int unit, unsigned dev_id, unsigned chk_crx) 5153 { 5154 const unsigned mdio_portid = mdio_portid_get(unit, dev_id); 5155 5156 unsigned errcnt = 0; 5157 5158 if (SOC_FAILURE(nl_mdio_chk_csm_status_regs(unit, mdio_portid, chk_crx))) { 5159 ++errcnt; 5160 } 5161 if (SOC_FAILURE(nl_mdio_chk_csm_error_counters(unit, mdio_portid, chk_crx))) { 5162 ++errcnt; 5163 } 5164 if (SOC_FAILURE(nl_mdio_chk_csm_counters(unit, mdio_portid, chk_crx))) { 5165 ++errcnt; 5166 } 5167 if (SOC_FAILURE(nl_mdio_chk_pcs_error_status(unit, mdio_portid, chk_crx))) { 5168 ++errcnt; 5169 } 5170 if (SOC_FAILURE(nl_mdio_chk_pcs_error_counters(unit, mdio_portid, chk_crx))) { 5171 ++errcnt; 5172 } 5173 5174 _SHR_RETURN(errcnt ? SOC_E_FAIL : SOC_E_NONE); 5175 } 5176 5177 5178 STATIC int 5179 init2(int unit, 5180 unsigned num_nl, 5181 unsigned en_nl_parity_scan, 5182 unsigned num_superblocks_lowpowermode, 5183 unsigned *superblocknums_lowpowermode 5184 ) 5185 { 5186 unsigned dev_id; 5187 5188 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, ETU_CONFIG2r, 0, ET_POST_WR_ENABLEf, 1)); 5189 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, ETU_TX_EXT_L2_MAX_LATENCYr, 0, CNTf, 10)); 5190 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, ETU_TX_CP_MAX_LATENCYr, 0, CNTf, 10)); 5191 5192 for (dev_id = 0; dev_id < num_nl; ++dev_id) { 5193 SOC_IF_ERROR_RETURN(nl_reg_access_test(unit, dev_id)); 5194 5195 #if 0 /* <HP> Skip for now, since it fails </HP> */ 5196 SOC_IF_ERROR_RETURN(nl_db_access_dm_test(unit, dev_id)); 5197 #endif 5198 5199 SOC_IF_ERROR_RETURN(nl_prog_err_status_mask_reg(unit, dev_id)); 5200 SOC_IF_ERROR_RETURN(nl_chk_err_status_reg(unit, dev_id)); 5201 } 5202 5203 { 5204 static const soc_field_t flds[] = { 5205 SER_STATUS_BUS_ECC_ENf, 5206 CTRL_BUS_FIFO_1_ECC_ENf, 5207 CTRL_BUS_FIFO_ECC_ENf, 5208 AUX1_FIFO_ECC_ENf, 5209 ADM_CTRL_FIFO_ECC_ENf, 5210 ET_RSP_FIFO_ECC_ENf 5211 }; 5212 5213 uint32 iesmif_ecc_control_buf = 0; 5214 unsigned i; 5215 5216 for (i = 0; i < COUNTOF(flds); ++i) { 5217 soc_reg_field_set(unit, IESMIF_ECC_CONTROLr, &iesmif_ecc_control_buf, flds[i], 1); 5218 } 5219 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, IESMIF_ECC_CONTROLr, 0, 0, iesmif_ecc_control_buf)); 5220 } 5221 5222 { 5223 static const soc_field_t flds[] = { 5224 L3_PROTOCOL_FN_PARITY_ENf, 5225 KEY_ID_TO_FIELD_MAPPER_PARITY_ENf, 5226 SEARCH_PROFILE_PARITY_ENf, 5227 PKT_TYPE_ID_PARITY_ENf, 5228 AD_6X_PARITY_ENf, 5229 AD_4X_PARITY_ENf, 5230 AD_3X_PARITY_ENf, 5231 AD_2X_PARITY_ENf, 5232 AD_1X_PARITY_ENf 5233 }; 5234 5235 uint32 iesmif_parity_control_buf = 0; 5236 unsigned i; 5237 5238 for (i = 0; i < COUNTOF(flds); ++i) { 5239 soc_reg_field_set(unit, IESMIF_PARITY_CONTROLr, &iesmif_parity_control_buf, flds[i], 1); 5240 } 5241 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, IESMIF_PARITY_CONTROLr, 0, 0, iesmif_parity_control_buf)); 5242 } 5243 5244 { 5245 static const soc_field_t flds[] = { 5246 EXT_LOOKUP_ENABLEf, 5247 MAX_CONTEXT_ADR_MSBf 5248 }; 5249 static const uint32 fld_vals[] = { 5250 0, 5251 0x7f7 5252 }; 5253 5254 SOC_IF_ERROR_RETURN(soc_reg_fields32_modify(unit, 5255 ESM_MISC_CONTROLr, 5256 0, 5257 COUNTOF(flds), 5258 (soc_field_t *) flds, 5259 (uint32 *) fld_vals 5260 ) 5261 ); 5262 } 5263 5264 { 5265 static const struct { 5266 soc_reg_t reg; 5267 uint32 cost; 5268 } regs_and_vals[] = { 5269 { ESM_ADM_THR_DROP_ALL_COST0r, 0xfffff }, 5270 { ESM_ADM_THR_DROP_ALL_COST1r, 0xfffff }, 5271 { ESM_ADM_THR_DROP_ALL_COST2r, 0xfffff }, 5272 { ESM_ADM_THR_DROP_OPT_COST0r, 0xfffff }, 5273 { ESM_ADM_THR_DROP_OPT_COST1r, 0xfffff }, 5274 { ESM_ADM_THR_DROP_OPT_COST2r, 0xfffff }, 5275 { ESM_AXP_THR_XOFF_COST0r, 0xffff }, 5276 { ESM_AXP_THR_XOFF_COST1r, 0xffff }, 5277 { ESM_AXP_THR_XOFF_COST2r, 0xffff } 5278 }; 5279 5280 unsigned i; 5281 5282 for (i = 0; i < COUNTOF(regs_and_vals); ++i) { 5283 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, regs_and_vals[i].reg, 0, COSTf, regs_and_vals[i].cost)); 5284 } 5285 } 5286 5287 SOC_IF_ERROR_RETURN(etu_mems_rst(unit, 1, 1)); 5288 SOC_IF_ERROR_RETURN(etu_mems_poll_rst_done(unit)); 5289 5290 if (en_nl_parity_scan) { 5291 SOC_IF_ERROR_RETURN(nl_ctx_buf_init(unit, num_nl, 1)); 5292 } 5293 5294 SOC_IF_ERROR_RETURN(chk_all_intr_sts(unit, num_nl)); 5295 5296 { 5297 static const soc_field_t flds[] = { 5298 EXT_LOOKUP_ENABLEf, 5299 ETU_REQ_SEQ_NUM_SELf, 5300 MAX_CONTEXT_ADR_MSBf 5301 }; 5302 static const uint32 fld_vals[] = { 5303 1, 5304 1, 5305 0x7f7 5306 }; 5307 5308 SOC_IF_ERROR_RETURN(soc_reg_fields32_modify(unit, 5309 ESM_MISC_CONTROLr, 5310 0, 5311 COUNTOF(flds), 5312 (soc_field_t *) flds, 5313 (uint32 *) fld_vals 5314 ) 5315 ); 5316 } 5317 5318 for (dev_id = 0; dev_id < num_nl; ++dev_id) { 5319 SOC_IF_ERROR_RETURN(nl_prog_dev_cfg_reg(unit, dev_id, en_nl_parity_scan)); 5320 } 5321 5322 SOC_IF_ERROR_RETURN(nl_cfg_low_power_mode(unit, num_nl, 0, 0)); 5323 5324 SOC_IF_ERROR_RETURN(chk_all_intr_sts(unit, num_nl)); 5325 5326 SOC_IF_ERROR_RETURN(soc_tcam_init(unit)); 5327 SOC_IF_ERROR_RETURN(soc_triumph3_esm_init(unit)); 5328 5329 SOC_IF_ERROR_RETURN(chk_fifos(unit)); 5330 SOC_IF_ERROR_RETURN(chk_etu_counters(unit)); 5331 SOC_IF_ERROR_RETURN(chk_all_intr_sts(unit, num_nl)); 5332 SOC_IF_ERROR_RETURN(chk_esmif_adc(unit)); 5333 SOC_IF_ERROR_RETURN(chk_misc_config(unit)); 5334 5335 for (dev_id = 0; dev_id < num_nl; ++dev_id) { 5336 unsigned chk_crx = (dev_id != 0); 5337 5338 SOC_IF_ERROR_RETURN(nl_mdio_chk_error_counters_status(unit, dev_id, chk_crx)); 5339 } 5340 5341 _SHR_RETURN(SOC_E_NONE); 5342 } 5343 5344 5345 STATIC unsigned 5346 calc_cost2_num_rsp_words(int unit, 5347 uint32 *esm_key_id_to_field_mapper_buf_entry_data, 5348 unsigned calc_optional_cost 5349 ) 5350 { 5351 unsigned total_num_cwords; 5352 unsigned last_cword_is_optional; 5353 unsigned rsp_index_count_cw2; 5354 unsigned rsp_index_count_cw1; 5355 unsigned rsp_index_count_cw0; 5356 unsigned num_rsp_dwords_cw2; 5357 unsigned num_rsp_dwords_cw1; 5358 unsigned num_rsp_dwords_cw0; 5359 unsigned total_num_rsp_words; 5360 5361 total_num_cwords = soc_mem_field32_get(unit, ESM_KEY_ID_TO_FIELD_MAPPERm, esm_key_id_to_field_mapper_buf_entry_data, TOTAL_NUM_CWORDSf); 5362 last_cword_is_optional = soc_mem_field32_get(unit, ESM_KEY_ID_TO_FIELD_MAPPERm, esm_key_id_to_field_mapper_buf_entry_data, LAST_CWORD_IS_OPTIONALf); 5363 5364 if (total_num_cwords < 1 || total_num_cwords > 3) { 5365 return (0xffff); 5366 } 5367 5368 if (calc_optional_cost) { 5369 if (!last_cword_is_optional) { 5370 return (0); 5371 } 5372 } 5373 5374 if (!calc_optional_cost) { 5375 if (last_cword_is_optional) { 5376 if (total_num_cwords == 1) { 5377 return (0); 5378 } 5379 5380 --total_num_cwords; 5381 } 5382 } 5383 5384 rsp_index_count_cw2 = soc_mem_field32_get(unit, ESM_KEY_ID_TO_FIELD_MAPPERm, esm_key_id_to_field_mapper_buf_entry_data, RSP_INDEX_COUNT_CW2f); 5385 rsp_index_count_cw1 = soc_mem_field32_get(unit, ESM_KEY_ID_TO_FIELD_MAPPERm, esm_key_id_to_field_mapper_buf_entry_data, RSP_INDEX_COUNT_CW1f); 5386 rsp_index_count_cw0 = soc_mem_field32_get(unit, ESM_KEY_ID_TO_FIELD_MAPPERm, esm_key_id_to_field_mapper_buf_entry_data, RSP_INDEX_COUNT_CW0f); 5387 5388 if (rsp_index_count_cw2 == 3) { 5389 num_rsp_dwords_cw2 = 2; 5390 } else if (rsp_index_count_cw2 == 0) { 5391 num_rsp_dwords_cw2 = 2; 5392 } else { 5393 num_rsp_dwords_cw2 = 1; 5394 } 5395 if (rsp_index_count_cw1 == 3) { 5396 num_rsp_dwords_cw1 = 2; 5397 } else if (rsp_index_count_cw1 == 0) { 5398 num_rsp_dwords_cw1 = 2; 5399 } else { 5400 num_rsp_dwords_cw1 = 1; 5401 } 5402 if (rsp_index_count_cw0 == 3) { 5403 num_rsp_dwords_cw0 = 2; 5404 } else if (rsp_index_count_cw0 == 0) { 5405 num_rsp_dwords_cw0 = 2; 5406 } else { 5407 num_rsp_dwords_cw0 = 1; 5408 } 5409 5410 if (total_num_cwords == 1) { 5411 total_num_rsp_words = total_num_cwords + num_rsp_dwords_cw0; 5412 } else if (total_num_cwords == 2) { 5413 total_num_rsp_words = total_num_cwords + num_rsp_dwords_cw0 + num_rsp_dwords_cw1; 5414 } else if (total_num_cwords == 3) { 5415 total_num_rsp_words = total_num_cwords + num_rsp_dwords_cw0 + num_rsp_dwords_cw1 + num_rsp_dwords_cw2; 5416 } else { 5417 /* coverity[dead_error_line] */ 5418 total_num_rsp_words = 0xffff; 5419 } 5420 5421 return (total_num_rsp_words); 5422 } 5423 5424 STATIC unsigned 5425 calc_cost1_num_req_words(int unit, 5426 uint32 *esm_key_id_to_field_mapper_buf_entry_data, 5427 unsigned calc_optional_cost 5428 ) 5429 { 5430 unsigned total_num_cwords; 5431 unsigned last_cword_is_optional; 5432 unsigned num_req_dwords_cw2; 5433 unsigned num_req_dwords_cw1; 5434 unsigned num_req_dwords_cw0; 5435 unsigned total_num_req_words; 5436 5437 total_num_cwords = soc_mem_field32_get(unit, ESM_KEY_ID_TO_FIELD_MAPPERm, esm_key_id_to_field_mapper_buf_entry_data, TOTAL_NUM_CWORDSf); 5438 last_cword_is_optional = soc_mem_field32_get(unit, ESM_KEY_ID_TO_FIELD_MAPPERm, esm_key_id_to_field_mapper_buf_entry_data, LAST_CWORD_IS_OPTIONALf); 5439 5440 if (total_num_cwords < 1 || total_num_cwords > 3) { 5441 return (0xffff); 5442 } 5443 5444 if (calc_optional_cost) { 5445 if (!last_cword_is_optional) { 5446 return (0); 5447 } 5448 } 5449 5450 if (!calc_optional_cost) { 5451 if (last_cword_is_optional) { 5452 if (total_num_cwords == 1) { 5453 return (0); 5454 } 5455 5456 --total_num_cwords; 5457 } 5458 } 5459 5460 num_req_dwords_cw2 = soc_mem_field32_get(unit, ESM_KEY_ID_TO_FIELD_MAPPERm, esm_key_id_to_field_mapper_buf_entry_data, NUM_DWORDS_CW2f); 5461 num_req_dwords_cw1 = soc_mem_field32_get(unit, ESM_KEY_ID_TO_FIELD_MAPPERm, esm_key_id_to_field_mapper_buf_entry_data, NUM_DWORDS_CW1f); 5462 num_req_dwords_cw0 = soc_mem_field32_get(unit, ESM_KEY_ID_TO_FIELD_MAPPERm, esm_key_id_to_field_mapper_buf_entry_data, NUM_DWORDS_CW0f); 5463 5464 if (total_num_cwords == 1) { 5465 total_num_req_words = total_num_cwords + num_req_dwords_cw0; 5466 } else if (total_num_cwords == 2) { 5467 total_num_req_words = total_num_cwords + num_req_dwords_cw0 + num_req_dwords_cw1; 5468 } else if (total_num_cwords == 3) { 5469 total_num_req_words = total_num_cwords + num_req_dwords_cw0 + num_req_dwords_cw1 + num_req_dwords_cw2; 5470 } else { 5471 /* coverity[dead_error_line] */ 5472 total_num_req_words = 0xffff; 5473 } 5474 5475 return (total_num_req_words); 5476 } 5477 5478 STATIC unsigned 5479 nl_find_num_cclks(unsigned nl_opcode) 5480 { 5481 unsigned bits_8_6 = (nl_opcode >> 6) & 0x7; 5482 5483 if (bits_8_6 == 1) { 5484 return (1); 5485 } 5486 if (bits_8_6 == 2) { 5487 return (2); 5488 } 5489 switch (nl_opcode) { 5490 case NL_OPC_NOP: 5491 case NL_OPC_CBW: 5492 return (1); 5493 case NL_OPC_REG_WRITE: 5494 return (2); 5495 case NL_OPC_REG_READ: 5496 case NL_OPC_DBY_READ: 5497 return (3); 5498 default: 5499 ; 5500 } 5501 5502 return (0xffff); 5503 } 5504 5505 STATIC unsigned 5506 calc_cost0_num_nl_cclks(int unit, 5507 uint32 *esm_key_id_to_field_mapper_buf_entry_data, 5508 unsigned calc_optional_cost 5509 ) 5510 { 5511 unsigned total_num_cwords; 5512 unsigned last_cword_is_optional; 5513 unsigned opcode_cw2; 5514 unsigned opcode_cw1; 5515 unsigned opcode_cw0; 5516 unsigned num_nl_cclks_cw2; 5517 unsigned num_nl_cclks_cw1; 5518 unsigned num_nl_cclks_cw0; 5519 unsigned total_num_nl_cclks; 5520 5521 total_num_cwords = soc_mem_field32_get(unit, ESM_KEY_ID_TO_FIELD_MAPPERm, esm_key_id_to_field_mapper_buf_entry_data, TOTAL_NUM_CWORDSf); 5522 last_cword_is_optional = soc_mem_field32_get(unit, ESM_KEY_ID_TO_FIELD_MAPPERm, esm_key_id_to_field_mapper_buf_entry_data, LAST_CWORD_IS_OPTIONALf); 5523 5524 if (total_num_cwords < 1 || total_num_cwords > 3) { 5525 return (0xffff); 5526 } 5527 5528 if (calc_optional_cost) { 5529 if (!last_cword_is_optional) { 5530 return (0); 5531 } 5532 } 5533 5534 if (!calc_optional_cost) { 5535 if (last_cword_is_optional) { 5536 if (total_num_cwords == 1) { 5537 return (0); 5538 } 5539 5540 --total_num_cwords; 5541 } 5542 } 5543 5544 opcode_cw2 = soc_mem_field32_get(unit, ESM_KEY_ID_TO_FIELD_MAPPERm, esm_key_id_to_field_mapper_buf_entry_data, OPCODE_CW2f); 5545 opcode_cw1 = soc_mem_field32_get(unit, ESM_KEY_ID_TO_FIELD_MAPPERm, esm_key_id_to_field_mapper_buf_entry_data, OPCODE_CW1f); 5546 opcode_cw0 = soc_mem_field32_get(unit, ESM_KEY_ID_TO_FIELD_MAPPERm, esm_key_id_to_field_mapper_buf_entry_data, OPCODE_CW0f); 5547 5548 num_nl_cclks_cw2 = nl_find_num_cclks(opcode_cw2); 5549 num_nl_cclks_cw1 = nl_find_num_cclks(opcode_cw1); 5550 num_nl_cclks_cw0 = nl_find_num_cclks(opcode_cw0); 5551 5552 if (total_num_cwords == 1) { 5553 total_num_nl_cclks = num_nl_cclks_cw0; 5554 } else if (total_num_cwords == 2) { 5555 total_num_nl_cclks = num_nl_cclks_cw0 + num_nl_cclks_cw1; 5556 } else if (total_num_cwords == 3) { 5557 total_num_nl_cclks = num_nl_cclks_cw0 + num_nl_cclks_cw1 + num_nl_cclks_cw2; 5558 } else { 5559 /* coverity[dead_error_line] */ 5560 total_num_nl_cclks = 0xffff; 5561 } 5562 5563 return (total_num_nl_cclks); 5564 } 5565 5566 STATIC int 5567 calc_cost210_num(int unit, unsigned ptr_fme_req, unsigned calc_optional_cost, unsigned *list_cost210_len, unsigned *list_cost210) 5568 { 5569 esm_key_id_to_field_mapper_entry_t esm_key_id_to_field_mapper_buf; 5570 unsigned cost2_num_rsp_words; 5571 unsigned cost1_num_req_words; 5572 unsigned cost0_num_nl_cclks; 5573 5574 SOC_IF_ERROR_RETURN(soc_mem_read(unit, ESM_KEY_ID_TO_FIELD_MAPPERm, MEM_BLOCK_ANY, ptr_fme_req, esm_key_id_to_field_mapper_buf.entry_data)); 5575 5576 cost2_num_rsp_words = calc_cost2_num_rsp_words(unit, esm_key_id_to_field_mapper_buf.entry_data, calc_optional_cost); 5577 cost1_num_req_words = calc_cost1_num_req_words(unit, esm_key_id_to_field_mapper_buf.entry_data, calc_optional_cost); 5578 cost0_num_nl_cclks = calc_cost0_num_nl_cclks(unit, esm_key_id_to_field_mapper_buf.entry_data, calc_optional_cost); 5579 5580 list_cost210[0] = cost2_num_rsp_words; 5581 list_cost210[1] = cost1_num_req_words; 5582 list_cost210[2] = cost0_num_nl_cclks; 5583 *list_cost210_len = 3; 5584 5585 _SHR_RETURN(SOC_E_NONE); 5586 } 5587 5588 5589 STATIC int 5590 esm_calc_new_fme_cost210 (int unit, int ptr_fme_req, int calc_optional_cost, 5591 unsigned step_size_ps_x, unsigned *fme_llength, 5592 unsigned *fme_cost210) 5593 { 5594 char proc_name[80]; 5595 esm_key_id_to_field_mapper_entry_t fme; 5596 unsigned list_cost210[3] = {0, 0, 0}, llength = 0; 5597 unsigned cost2_num_rsp_words, cost1_num_req_words; 5598 unsigned cost0_num_nl_cclks, num_rsp_words, max_rsp_mwps, rsp_mpps; 5599 unsigned time_to_receive_rsp_ns_x, num_req_words, max_req_mwps, req_mpps; 5600 unsigned num_nl_cclks, nl_core_mpps, time_for_nl_to_execute_search_ns_x; 5601 unsigned worst_req_proc_cost_ns_x, esmif_req_cost_ns_x, qdly_per_esmif_req_ns_x; 5602 unsigned last_cword_is_optional, time_to_transmit_req_ns_x, tmp; 5603 unsigned num_cwords; 5604 int rc = SOC_E_NONE; 5605 5606 if (calc_optional_cost) { 5607 sal_strncpy(proc_name, "esm_calc_new_OPTIONAL_fme_cost210", 5608 (sizeof(proc_name)-1)); 5609 } else { 5610 sal_strncpy(proc_name, "esm_calc_new_fme_cost210", 5611 (sizeof(proc_name)-1)); 5612 } 5613 5614 /* 5615 esm_puts_fyi "$proc_name: ptr_fme_req=$ptr_fme_req, calc_optional_cost=$calc_optional_cost, step_size_ps=$step_size_ps"; 5616 */ 5617 5618 /* compute num_rsp_words, num_req_words, nl_cclks for this fme_req */ 5619 SOC_IF_ERROR_RETURN(soc_mem_read(unit, ESM_KEY_ID_TO_FIELD_MAPPERm, 5620 MEM_BLOCK_ANY, ptr_fme_req, &fme)); 5621 num_cwords = soc_ESM_KEY_ID_TO_FIELD_MAPPERm_field32_get(unit, 5622 fme.entry_data, TOTAL_NUM_CWORDSf); 5623 if (calc_optional_cost) { 5624 last_cword_is_optional = 5625 soc_ESM_KEY_ID_TO_FIELD_MAPPERm_field32_get(unit, 5626 fme.entry_data, LAST_CWORD_IS_OPTIONALf); 5627 if (last_cword_is_optional) { 5628 /* calc OPTIONAL_COST fields */ 5629 if (num_cwords == 0) { 5630 /* don't care values. */ 5631 *fme_llength = 3; 5632 fme_cost210[2] = fme_cost210[1] = fme_cost210[0] = 0; 5633 return SOC_E_NONE; 5634 } 5635 rc = calc_cost210_num(unit, ptr_fme_req, 1, &llength, list_cost210); 5636 } else { 5637 /* 5638 esm_puts_fyi "$proc_name: ptr_fme_req=$ptr_fme_req, new_fme_cost210 are 0 0 0\n"; 5639 */ 5640 /* don't care values. */ 5641 *fme_llength = 3; 5642 fme_cost210[2] = fme_cost210[1] = fme_cost210[0] = 0; 5643 return SOC_E_NONE; 5644 } 5645 } else { 5646 if (num_cwords == 0) { 5647 /* don't care values. */ 5648 *fme_llength = 3; 5649 fme_cost210[2] = fme_cost210[1] = fme_cost210[0] = 0; 5650 return SOC_E_NONE; 5651 } 5652 /* calc COST fields */ 5653 rc = calc_cost210_num(unit, ptr_fme_req, 0, &llength, list_cost210); 5654 SOC_IF_ERROR_RETURN(rc); 5655 } 5656 if (llength != 3) { 5657 LOG_ERROR(BSL_LS_SOC_ESM, 5658 (BSL_META_U(unit, 5659 "unit %d: %s: ptr_fme_req=%d, could not"), 5660 unit, proc_name, ptr_fme_req)); 5661 LOG_ERROR(BSL_LS_SOC_ESM, 5662 (BSL_META_U(unit, 5663 "compute cost in terms of num_rsp_words,"))); 5664 LOG_ERROR(BSL_LS_SOC_ESM, 5665 (BSL_META_U(unit, 5666 "num_req_words, num_nl_cclks\n"))); 5667 /* failure */ 5668 return SOC_E_FAIL; 5669 } 5670 cost2_num_rsp_words = list_cost210[0]; 5671 cost1_num_req_words = list_cost210[1]; 5672 cost0_num_nl_cclks = list_cost210[2]; 5673 5674 /*mpps limited by rsp */ 5675 num_rsp_words = cost2_num_rsp_words; 5676 if (num_rsp_words) { 5677 max_rsp_mwps = (calc_mwps_per_lane_x() * NL_NUM_RSP_LANES * 5678 (100 - REQD_RX_BW_FOR_CPU_PERCENT))/100; 5679 rsp_mpps = max_rsp_mwps / num_rsp_words; 5680 time_to_receive_rsp_ns_x = (1000*1000*1000) / rsp_mpps; 5681 } else { 5682 LOG_ERROR(BSL_LS_SOC_ESM, 5683 (BSL_META_U(unit, 5684 "unit %d: %s: ptr_fme_req=%d, num_rsp_words"), 5685 unit, proc_name, ptr_fme_req)); 5686 LOG_ERROR(BSL_LS_SOC_ESM, 5687 (BSL_META_U(unit, 5688 "must be non-zero, exitting\n"))); 5689 return SOC_E_FAIL; /* failed */ 5690 } 5691 5692 /*mpps limited by req */ 5693 num_req_words = cost1_num_req_words; 5694 if (num_req_words) { 5695 max_req_mwps = (calc_mwps_per_lane_x() * NL_NUM_REQ_LANES * 5696 (100 - REQD_TX_BW_FOR_CPU_PERCENT))/100; 5697 req_mpps = max_req_mwps / num_req_words; 5698 time_to_transmit_req_ns_x = (1000*1000*1000) / req_mpps; 5699 } else { 5700 LOG_ERROR(BSL_LS_SOC_ESM, 5701 (BSL_META_U(unit, 5702 "unit %d: %s: ptr_fme_req=%d, num_req_words"), 5703 unit, proc_name, ptr_fme_req)); 5704 LOG_ERROR(BSL_LS_SOC_ESM, 5705 (BSL_META_U(unit, 5706 "must be non-zero, exitting\n"))); 5707 return SOC_E_FAIL; /* failed */ 5708 } 5709 5710 /* mpps limited by nl_core_clk_freq */ 5711 num_nl_cclks = cost0_num_nl_cclks; 5712 if (num_nl_cclks) { 5713 nl_core_mpps = ((nl_core_clk_freq_khz(unit) * 5714 (100 - REQD_NL_CCLK_BW_FOR_CPU_PERCENT))/100) / num_nl_cclks; 5715 time_for_nl_to_execute_search_ns_x = (1000*1000*1000) / nl_core_mpps; 5716 } else { 5717 LOG_VERBOSE(BSL_LS_SOC_COMMON, 5718 (BSL_META_U(unit, 5719 "unit %d: %s: ptr_fme_req=%d, num_nl_cclks"), 5720 unit, proc_name, ptr_fme_req)); 5721 LOG_VERBOSE(BSL_LS_SOC_COMMON, 5722 (BSL_META_U(unit, 5723 "must be non-zero, exitting\n"))); 5724 return SOC_E_FAIL; /* failed */ 5725 } 5726 5727 tmp = ESM_MAX(time_to_receive_rsp_ns_x, time_to_transmit_req_ns_x); 5728 worst_req_proc_cost_ns_x = ESM_MAX(tmp, time_for_nl_to_execute_search_ns_x); 5729 5730 /* compute qdly_per_esmif_req_ns */ 5731 /* 1 clock to post the ipipe_request */ 5732 esmif_req_cost_ns_x = (1000 * 1000 *1000) / esmif_clk_freq_khz(unit); 5733 if (worst_req_proc_cost_ns_x > esmif_req_cost_ns_x) { 5734 qdly_per_esmif_req_ns_x = worst_req_proc_cost_ns_x - esmif_req_cost_ns_x; 5735 } else { 5736 qdly_per_esmif_req_ns_x = 0; 5737 } 5738 5739 /* compute new_fme_costs */ 5740 /* cost2 */ 5741 fme_cost210[0] = 0; 5742 5743 /* round up */ 5744 /* cost1 */ 5745 fme_cost210[1] = (qdly_per_esmif_req_ns_x * 1000) / step_size_ps_x + 5746 ((qdly_per_esmif_req_ns_x * 1000) % step_size_ps_x ? 1 : 0); 5747 5748 /* cost0 */ 5749 fme_cost210[2] = (worst_req_proc_cost_ns_x * 1000)/step_size_ps_x 5750 + ((worst_req_proc_cost_ns_x * 1000) % step_size_ps_x ? 1 : 0); 5751 *fme_llength = 3; 5752 return SOC_E_NONE; 5753 } 5754 5755 STATIC int 5756 esm_prog_new_fme_costs (int unit, int ptr_fme_req, int prog_optional_cost, 5757 unsigned step_size_ps_x) 5758 { 5759 int rc; 5760 unsigned list_cost210[3], llength; 5761 unsigned fme_cost2, fme_cost1, fme_cost0; 5762 esm_key_id_to_field_mapper_entry_t fme; 5763 unsigned num_cwords; 5764 5765 rc = esm_calc_new_fme_cost210(unit, ptr_fme_req, prog_optional_cost, 5766 step_size_ps_x, &llength, list_cost210); 5767 if (rc < 0) { 5768 return rc; 5769 } 5770 if (llength != 3) { 5771 LOG_ERROR(BSL_LS_SOC_ESM, 5772 (BSL_META_U(unit, 5773 "unit %d: esm_prog_new_fme_costs: will not "), 5774 unit)); 5775 LOG_ERROR(BSL_LS_SOC_ESM, 5776 (BSL_META_U(unit, 5777 "to program costs in FIELDMAPPER table"))); 5778 return SOC_E_FAIL; 5779 } 5780 fme_cost2 = list_cost210[0]; /* element_0 of list */ 5781 fme_cost1 = list_cost210[1]; /* element_1 of list */ 5782 fme_cost0 = list_cost210[2]; /* element_2 of list */ 5783 LOG_VERBOSE(BSL_LS_SOC_COMMON, 5784 (BSL_META_U(unit, 5785 "unit %d: esm_prog_new_fme_costs: ptr_fme_req=%d"), 5786 unit, ptr_fme_req)); 5787 LOG_VERBOSE(BSL_LS_SOC_COMMON, 5788 (BSL_META_U(unit, 5789 "fme_cost2=%d, fme_cost1=%d, fme_cost0=%d\n"), 5790 fme_cost2, fme_cost1, fme_cost0)); 5791 5792 SOC_IF_ERROR_RETURN(soc_mem_read(unit, ESM_KEY_ID_TO_FIELD_MAPPERm, 5793 MEM_BLOCK_ANY, ptr_fme_req, &fme)); 5794 5795 num_cwords = soc_ESM_KEY_ID_TO_FIELD_MAPPERm_field32_get(unit, 5796 fme.entry_data, TOTAL_NUM_CWORDSf); 5797 if (num_cwords == 0) { 5798 /* don't program anything for unused FMEs */ 5799 return SOC_E_NONE; 5800 } 5801 if (prog_optional_cost) { 5802 soc_ESM_KEY_ID_TO_FIELD_MAPPERm_field32_set(unit, fme.entry_data, 5803 OPTIONAL_COST2f, 5804 fme_cost2); 5805 soc_ESM_KEY_ID_TO_FIELD_MAPPERm_field32_set(unit, fme.entry_data, 5806 OPTIONAL_COST1f, 5807 fme_cost1); 5808 soc_ESM_KEY_ID_TO_FIELD_MAPPERm_field32_set(unit, fme.entry_data, 5809 OPTIONAL_COST0f, 5810 fme_cost0); 5811 } else { 5812 soc_ESM_KEY_ID_TO_FIELD_MAPPERm_field32_set(unit, fme.entry_data, 5813 COST2f, 5814 fme_cost2); 5815 soc_ESM_KEY_ID_TO_FIELD_MAPPERm_field32_set(unit, fme.entry_data, 5816 COST1f, 5817 fme_cost1); 5818 soc_ESM_KEY_ID_TO_FIELD_MAPPERm_field32_set(unit, fme.entry_data, 5819 COST0f, 5820 fme_cost0); 5821 } 5822 SOC_IF_ERROR_RETURN(soc_mem_write(unit, ESM_KEY_ID_TO_FIELD_MAPPERm, 5823 MEM_BLOCK_ALL, ptr_fme_req, fme.entry_data)); 5824 return SOC_E_NONE; /* passed */ 5825 } 5826 5827 #if 0 5828 STATIC int 5829 prog_fme_costs(int unit, unsigned ptr_fme_req, unsigned prog_optional_cost, unsigned list_cost210_len, unsigned *list_cost210) 5830 { 5831 unsigned _list_cost210[3]; 5832 unsigned cost2_num_rsp_words; 5833 unsigned cost1_num_req_words; 5834 unsigned cost0_num_nl_cclks; 5835 unsigned fme_cost2_rsp; 5836 unsigned fme_cost1_req; 5837 unsigned fme_cost0_nl_cclks; 5838 esm_key_id_to_field_mapper_entry_t esm_key_id_to_field_mapper_buf; 5839 5840 if (list_cost210_len != 3) { 5841 SOC_IF_ERROR_RETURN(calc_cost210_num(unit, ptr_fme_req, prog_optional_cost, &list_cost210_len, _list_cost210)); 5842 list_cost210 = _list_cost210; 5843 } 5844 5845 cost2_num_rsp_words = list_cost210[0]; 5846 cost1_num_req_words = list_cost210[1]; 5847 cost0_num_nl_cclks = list_cost210[2]; 5848 5849 fme_cost2_rsp = cost2_num_rsp_words; 5850 fme_cost1_req = cost1_num_req_words; 5851 fme_cost0_nl_cclks = cost0_num_nl_cclks; 5852 5853 SOC_IF_ERROR_RETURN(soc_mem_read(unit, ESM_KEY_ID_TO_FIELD_MAPPERm, MEM_BLOCK_ANY, ptr_fme_req, esm_key_id_to_field_mapper_buf.entry_data)); 5854 5855 if (soc_mem_field32_get(unit, 5856 ESM_KEY_ID_TO_FIELD_MAPPERm, 5857 esm_key_id_to_field_mapper_buf.entry_data, 5858 TOTAL_NUM_CWORDSf 5859 ) 5860 == 0) { 5861 /* Not used => skip cost programming */ 5862 5863 _SHR_RETURN(SOC_E_NONE); 5864 } 5865 5866 if (prog_optional_cost) { 5867 soc_mem_field32_set(unit, 5868 ESM_KEY_ID_TO_FIELD_MAPPERm, 5869 esm_key_id_to_field_mapper_buf.entry_data, 5870 OPTIONAL_COST2f, 5871 fme_cost2_rsp 5872 ); 5873 soc_mem_field32_set(unit, 5874 ESM_KEY_ID_TO_FIELD_MAPPERm, 5875 esm_key_id_to_field_mapper_buf.entry_data, 5876 OPTIONAL_COST1f, 5877 fme_cost1_req 5878 ); 5879 soc_mem_field32_set(unit, 5880 ESM_KEY_ID_TO_FIELD_MAPPERm, 5881 esm_key_id_to_field_mapper_buf.entry_data, 5882 OPTIONAL_COST0f, 5883 fme_cost0_nl_cclks 5884 ); 5885 } else { 5886 soc_mem_field32_set(unit, 5887 ESM_KEY_ID_TO_FIELD_MAPPERm, 5888 esm_key_id_to_field_mapper_buf.entry_data, 5889 COST2f, 5890 fme_cost2_rsp 5891 ); 5892 soc_mem_field32_set(unit, 5893 ESM_KEY_ID_TO_FIELD_MAPPERm, 5894 esm_key_id_to_field_mapper_buf.entry_data, 5895 COST1f, 5896 fme_cost1_req 5897 ); 5898 soc_mem_field32_set(unit, 5899 ESM_KEY_ID_TO_FIELD_MAPPERm, 5900 esm_key_id_to_field_mapper_buf.entry_data, 5901 COST0f, 5902 fme_cost0_nl_cclks 5903 ); 5904 } 5905 SOC_IF_ERROR_RETURN(soc_mem_write(unit, ESM_KEY_ID_TO_FIELD_MAPPERm, MEM_BLOCK_ALL, ptr_fme_req, esm_key_id_to_field_mapper_buf.entry_data)); 5906 5907 SOC_IF_ERROR_RETURN(soc_mem_read(unit, ESM_KEY_ID_TO_FIELD_MAPPERm, MEM_BLOCK_ANY, ptr_fme_req, esm_key_id_to_field_mapper_buf.entry_data)); 5908 if (soc_mem_field32_get(unit, 5909 ESM_KEY_ID_TO_FIELD_MAPPERm, 5910 esm_key_id_to_field_mapper_buf.entry_data, 5911 prog_optional_cost ? OPTIONAL_COST2f : COST2f 5912 ) 5913 != fme_cost2_rsp 5914 || soc_mem_field32_get(unit, 5915 ESM_KEY_ID_TO_FIELD_MAPPERm, 5916 esm_key_id_to_field_mapper_buf.entry_data, 5917 prog_optional_cost ? OPTIONAL_COST1f : COST1f 5918 ) 5919 != fme_cost1_req 5920 || soc_mem_field32_get(unit, 5921 ESM_KEY_ID_TO_FIELD_MAPPERm, 5922 esm_key_id_to_field_mapper_buf.entry_data, 5923 prog_optional_cost ? OPTIONAL_COST0f : COST0f 5924 ) 5925 != fme_cost0_nl_cclks 5926 ) { 5927 _SHR_RETURN(SOC_E_FAIL); 5928 } 5929 5930 _SHR_RETURN(SOC_E_NONE); 5931 } 5932 5933 5934 STATIC unsigned 5935 calc_drop_all_cost2_rsp(unsigned max_allowed_latency_ns) 5936 { 5937 unsigned rsp_mwps, rsp_word_duration_ps, drop_all_cost2_rsp; 5938 5939 rsp_mwps = (calc_mwps_per_lane() * NL_NUM_RSP_LANES * (100 - REQD_RX_BW_FOR_CPU_PERCENT)) / 100; 5940 rsp_word_duration_ps = 1000000 / rsp_mwps; 5941 drop_all_cost2_rsp = (1000 * max_allowed_latency_ns) / rsp_word_duration_ps; 5942 5943 return (drop_all_cost2_rsp); 5944 } 5945 5946 5947 STATIC unsigned 5948 calc_drop_all_cost1_req(unsigned max_allowed_latency_ns) 5949 { 5950 unsigned req_mwps, req_word_duration_ps, drop_all_cost1_req; 5951 5952 req_mwps = (calc_mwps_per_lane() * NL_NUM_REQ_LANES * (100 - REQD_TX_BW_FOR_CPU_PERCENT)) / 100; 5953 req_word_duration_ps = 1000000 / req_mwps; 5954 drop_all_cost1_req = (1000 * max_allowed_latency_ns) / req_word_duration_ps; 5955 5956 return (drop_all_cost1_req); 5957 } 5958 5959 5960 STATIC unsigned 5961 calc_drop_all_cost0_nl_cclks(int unit, unsigned max_allowed_latency_ns) 5962 { 5963 unsigned nl_core_khz, nl_cclks_duration_ps, drop_all_cost0_nl_cclks; 5964 5965 nl_core_khz = (nl_core_clk_freq_khz(unit) * (100 - REQD_NL_CCLK_BW_FOR_CPU_PERCENT)) / 100; 5966 nl_cclks_duration_ps = 1000000000 / nl_core_khz; 5967 drop_all_cost0_nl_cclks = (1000 * max_allowed_latency_ns) / nl_cclks_duration_ps; 5968 5969 return (drop_all_cost0_nl_cclks); 5970 } 5971 5972 5973 STATIC int 5974 prog_drop_all_costs(int unit, unsigned max_latency_ns, unsigned percent_hysteresis) 5975 { 5976 uint32 drop_all_cost2 = calc_drop_all_cost2_rsp(max_latency_ns); 5977 uint32 drop_all_cost1 = calc_drop_all_cost1_req(max_latency_ns); 5978 uint32 drop_all_cost0 = calc_drop_all_cost0_nl_cclks(unit, max_latency_ns); 5979 uint32 drop_all_reset_cost2 = (percent_hysteresis * drop_all_cost2) / 100; 5980 uint32 drop_all_reset_cost1 = (percent_hysteresis * drop_all_cost1) / 100; 5981 uint32 drop_all_reset_cost0 = (percent_hysteresis * drop_all_cost0) / 100; 5982 5983 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, ESM_ADM_THR_DROP_ALL_COST2r, 0, 0, drop_all_cost2)); 5984 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, ESM_ADM_THR_DROP_ALL_COST1r, 0, 0, drop_all_cost1)); 5985 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, ESM_ADM_THR_DROP_ALL_COST0r, 0, 0, drop_all_cost0)); 5986 5987 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, ESM_ADM_THR_DROP_ALL_RESET_COST2r, 0, 0, drop_all_reset_cost2)); 5988 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, ESM_ADM_THR_DROP_ALL_RESET_COST1r, 0, 0, drop_all_reset_cost1)); 5989 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, ESM_ADM_THR_DROP_ALL_RESET_COST0r, 0, 0, drop_all_reset_cost0)); 5990 5991 _SHR_RETURN(SOC_E_NONE); 5992 } 5993 #endif 5994 5995 5996 STATIC int 5997 prog_drop_opt_costs(int unit, unsigned percent_drop_all, unsigned percent_hysteresis) 5998 { 5999 uint32 drop_all_cost2; 6000 uint32 drop_all_cost1; 6001 uint32 drop_all_cost0; 6002 uint32 drop_opt_cost2; 6003 uint32 drop_opt_cost1; 6004 uint32 drop_opt_cost0; 6005 uint32 drop_opt_reset_cost2; 6006 uint32 drop_opt_reset_cost1; 6007 uint32 drop_opt_reset_cost0; 6008 6009 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, ESM_ADM_THR_DROP_ALL_COST2r, 0, 0, &drop_all_cost2)); 6010 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, ESM_ADM_THR_DROP_ALL_COST1r, 0, 0, &drop_all_cost1)); 6011 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, ESM_ADM_THR_DROP_ALL_COST0r, 0, 0, &drop_all_cost0)); 6012 6013 drop_opt_cost2 = (percent_drop_all * drop_all_cost2) / 100; 6014 drop_opt_cost1 = (percent_drop_all * drop_all_cost1) / 100; 6015 drop_opt_cost0 = (percent_drop_all * drop_all_cost0) / 100; 6016 6017 drop_opt_reset_cost2 = (percent_hysteresis * drop_opt_cost2) / 100; 6018 drop_opt_reset_cost1 = (percent_hysteresis * drop_opt_cost1) / 100; 6019 drop_opt_reset_cost0 = (percent_hysteresis * drop_opt_cost0) / 100; 6020 6021 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, ESM_ADM_THR_DROP_OPT_COST2r, 0, 0, drop_opt_cost2)); 6022 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, ESM_ADM_THR_DROP_OPT_COST1r, 0, 0, drop_opt_cost1)); 6023 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, ESM_ADM_THR_DROP_OPT_COST0r, 0, 0, drop_opt_cost0)); 6024 6025 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, ESM_ADM_THR_DROP_OPT_RESET_COST2r, 0, 0, drop_opt_reset_cost2)); 6026 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, ESM_ADM_THR_DROP_OPT_RESET_COST1r, 0, 0, drop_opt_reset_cost1)); 6027 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, ESM_ADM_THR_DROP_OPT_RESET_COST0r, 0, 0, drop_opt_reset_cost0)); 6028 6029 _SHR_RETURN(SOC_E_NONE); 6030 } 6031 6032 STATIC int 6033 esm_prog_drop_all_cost_fme_req_cost(int unit, unsigned *idle_req_rsp_latency_ns_x, 6034 int idle_req_rsp_ptr_fme_req) 6035 { 6036 /* compute step_size_ps (independent of idle_req_rsp_latency_ns) */ 6037 /* use 'worst possible' cost numbers */ 6038 unsigned list_user_cost210[] = {9, 14, 4}; 6039 unsigned step_size_ps_x; 6040 int rc = 0, ptr_fme_req, max_ptr_fme_req = KEY_GEN_OFFSET_MAX; 6041 6042 step_size_ps_x = esm_calc_new_step_size_ps(unit, 3, list_user_cost210); 6043 6044 6045 /* 6046 esm_puts_fyi "======= Will use : ptr_fme_req=$idle_req_rsp_ptr_fme_req to measure idle_req_rsp_latency_ns ...."; 6047 */ 6048 if (*idle_req_rsp_latency_ns_x == 0) { 6049 rc = hwtl_find_idle_req_rsp_latency(unit, idle_req_rsp_ptr_fme_req, 6050 30, idle_req_rsp_latency_ns_x); 6051 SOC_IF_ERROR_RETURN(rc); 6052 LOG_CLI((BSL_META_U(unit, 6053 "config add idle_req_rsp_latency_ns.%d=%d\n"), 6054 unit, *idle_req_rsp_latency_ns_x)); 6055 } 6056 if (*idle_req_rsp_latency_ns_x == 0) { 6057 LOG_ERROR(BSL_LS_SOC_ESM, 6058 (BSL_META_U(unit, 6059 "unit %d: ptr_fme_req=%d: idle_req_rsp_latency"), 6060 unit, idle_req_rsp_ptr_fme_req)); 6061 LOG_ERROR(BSL_LS_SOC_ESM, 6062 (BSL_META_U(unit, 6063 "measurement FAILED, will quit\n"))); 6064 return SOC_E_FAIL; 6065 } 6066 /* Already an int, no need to do this: 6067 set idle_req_rsp_latency_ns [esm_mpexpr int(ceil($idle_req_rsp_latency_ns + 10))]; 6068 */ 6069 /* program new drop_all_costs */ 6070 rc = esm_prog_new_drop_all_costs(unit, *idle_req_rsp_latency_ns_x, 6071 step_size_ps_x, 90); 6072 SOC_IF_ERROR_RETURN(rc); 6073 rc = prog_drop_opt_costs(unit, 50, 90); 6074 SOC_IF_ERROR_RETURN(rc); 6075 6076 /* For each fme_entry program correct costs */ 6077 for (ptr_fme_req = 1; ptr_fme_req <= max_ptr_fme_req; ++ptr_fme_req) { 6078 SOC_IF_ERROR_RETURN(esm_prog_new_fme_costs(unit, ptr_fme_req, 0, 6079 step_size_ps_x)); 6080 SOC_IF_ERROR_RETURN(esm_prog_new_fme_costs(unit, ptr_fme_req, 1, 6081 step_size_ps_x)); 6082 } 6083 return SOC_E_NONE; 6084 } 6085 6086 STATIC int 6087 enable_report_all_intr(int unit) 6088 { 6089 { 6090 static const struct { 6091 soc_field_t fld; 6092 uint32 val; 6093 } fldvals[] = { 6094 { DROP_COUNT_MSBf, 1 }, 6095 { CNP_SEARCH_REQ_COUNT_MSBf, 1 }, 6096 { SOP_DROPf, 1 }, 6097 { XOFF_AXP_OVERSUBSf, 1 }, 6098 { MANDATORY_DENYf, 1 }, 6099 { DROP_ALLf, 1 }, 6100 { OPT_REQ_TRICKLEDf, 1 }, 6101 { OPTIONAL_DENYf, 1 }, 6102 { ET_RSP_ERRf, 1 }, 6103 { CNP_SEARCH_REQf, 1 }, 6104 { ET_REQ_FIFO_FULL_DENYf, 1 }, 6105 { ET_REQ_FIFO_FULLf, 1 }, 6106 { ADM_CTRL_FIFO_FULL_DENYf, 1 }, 6107 { ADM_CTRL_FIFO_FULLf, 1 }, 6108 { ET_RSP_FIFO_FULLf, 1 }, 6109 { CBA_MISMATCHf, 1 }, 6110 { ADM_CTRL_FIFO_UNDERFLOWf, 1 }, 6111 { ET_RSP_FIFO_UNDERFLOWf, 1 }, 6112 { ET_RSP_FIFO_OVERFLOWf, 1 } 6113 }; 6114 6115 uint32 esm_event_err_status_intr_enable_buf = 0; 6116 unsigned i; 6117 6118 for (i = 0; i < COUNTOF(fldvals); ++i) { 6119 soc_reg_field_set(unit, ESM_EVENT_ERR_STATUS_INTRr, &esm_event_err_status_intr_enable_buf, fldvals[i].fld, fldvals[i].val); 6120 } 6121 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, ESM_EVENT_ERR_STATUS_INTR_ENABLEr, 0, 0, esm_event_err_status_intr_enable_buf)); 6122 } 6123 6124 { 6125 static const struct { 6126 soc_field_t fld; 6127 uint32 val; 6128 } fldvals[] = { 6129 { EXT_TCAM_INTR1f, 1 }, 6130 { EXT_TCAM_INTR0f, 1 }, 6131 { EXT_L2_REQ_LTH_ERRf, 1 }, 6132 { TWO_MISSING_PKTf, 1 }, 6133 { RRFE_WAIT_PENDING0f, 1 }, 6134 { RRFE_WAIT_FULLf, 1 }, 6135 { PP_XLAT1_PERRf, 1 }, 6136 { PP_XLAT0_PERRf, 1 }, 6137 { EXT_L2_CMD_ERRf, 1 }, 6138 { SBUS_CMD_ERRf, 1 }, 6139 { RX_CW_ERRf, 1 }, 6140 { RX_CW_ERS1f, 1 }, 6141 { RX_CW_ERS0f, 1 } 6142 }; 6143 6144 uint32 etu_global_intr_enable_buf = 0; 6145 unsigned i; 6146 6147 for (i = 0; i < COUNTOF(fldvals); ++i) { 6148 soc_reg_field_set(unit, ETU_GLOBAL_INTR_STSr, &etu_global_intr_enable_buf, fldvals[i].fld, fldvals[i].val); 6149 } 6150 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, ETU_GLOBAL_INTR_ENABLEr, 0, 0, etu_global_intr_enable_buf)); 6151 } 6152 6153 { 6154 static const struct { 6155 soc_field_t fld; 6156 uint32 val; 6157 } fldvals[] = { 6158 { XOFF_TX_CH1f, 1 }, 6159 { XOFF_TX_CH0f, 1 }, 6160 { RX_ALIGNEDf, 1 }, 6161 { RX_MISALIGNEDf, 1 }, 6162 { RX_ALIGNED_ERRf, 1 }, 6163 { RX_WORD_SYNCf, 0xfff }, 6164 { RX_SYNCEDf, 0xfff } 6165 }; 6166 6167 uint32 ilamac_rx_intf_intr0_enable_buf = 0; 6168 unsigned i; 6169 6170 for (i = 0; i < COUNTOF(fldvals); ++i) { 6171 soc_reg_field_set(unit, ILAMAC_RX_INTF_INTR0_STSr, &ilamac_rx_intf_intr0_enable_buf, fldvals[i].fld, fldvals[i].val); 6172 } 6173 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, ILAMAC_RX_INTF_INTR0_ENABLEr, 0, 0, ilamac_rx_intf_intr0_enable_buf)); 6174 } 6175 6176 { 6177 static const struct { 6178 soc_field_t fld; 6179 uint32 val; 6180 } fldvals[] = { 6181 { RX_BURST_GT_16B_ERRf, 1 }, 6182 { RX_CRC24_ERRf, 1 }, 6183 { RX_MSOP_ERRf, 1 }, 6184 { RX_MEOP_ERRf, 1 }, 6185 { RX_OVERFLOW_ERRf, 1 }, 6186 { RX_BURSTMAX_ERRf, 1 }, 6187 { RX_BURST_ERRf, 1 } 6188 }; 6189 6190 uint32 ilamac_rx_intf_intr1_enable_buf = 0; 6191 unsigned i; 6192 6193 for (i = 0; i < COUNTOF(fldvals); ++i) { 6194 soc_reg_field_set(unit, ILAMAC_RX_INTF_INTR1_STSr, &ilamac_rx_intf_intr1_enable_buf, fldvals[i].fld, fldvals[i].val); 6195 } 6196 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, ILAMAC_RX_INTF_INTR1_ENABLEr, 0, 0, ilamac_rx_intf_intr1_enable_buf)); 6197 } 6198 6199 { 6200 uint32 ilamac_rx_lane_intr0_enable_buf = 0; 6201 6202 soc_reg_field_set(unit, ILAMAC_RX_LANE_INTR0_STSr, &ilamac_rx_lane_intr0_enable_buf, RX_SYNCED_ERRf, 0xfff); 6203 soc_reg_field_set(unit, ILAMAC_RX_LANE_INTR0_STSr, &ilamac_rx_lane_intr0_enable_buf, RX_FRAMING_ERRf, 0xfff); 6204 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, ILAMAC_RX_LANE_INTR0_ENABLEr, 0, 0, ilamac_rx_lane_intr0_enable_buf)); 6205 } 6206 6207 { 6208 uint32 ilamac_rx_lane_intr1_enable_buf = 0; 6209 6210 soc_reg_field_set(unit, ILAMAC_RX_LANE_INTR1_STSr, &ilamac_rx_lane_intr1_enable_buf, RX_BAD_TYPE_ERRf, 0xfff); 6211 soc_reg_field_set(unit, ILAMAC_RX_LANE_INTR1_STSr, &ilamac_rx_lane_intr1_enable_buf, RX_MF_ERRf, 0xfff); 6212 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, ILAMAC_RX_LANE_INTR1_ENABLEr, 0, 0, ilamac_rx_lane_intr1_enable_buf)); 6213 } 6214 6215 { 6216 uint32 ilamac_rx_lane_intr2_enable_buf = 0; 6217 6218 soc_reg_field_set(unit, ILAMAC_RX_LANE_INTR2_STSr, &ilamac_rx_lane_intr2_enable_buf, RX_DESCRAM_ERRf, 0xfff); 6219 soc_reg_field_set(unit, ILAMAC_RX_LANE_INTR2_STSr, &ilamac_rx_lane_intr2_enable_buf, RX_MF_LEN_ERRf, 0xfff); 6220 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, ILAMAC_RX_LANE_INTR2_ENABLEr, 0, 0, ilamac_rx_lane_intr2_enable_buf)); 6221 } 6222 6223 { 6224 uint32 ilamac_rx_lane_intr3_enable_buf = 0; 6225 6226 soc_reg_field_set(unit, ILAMAC_RX_LANE_INTR3_STSr, &ilamac_rx_lane_intr3_enable_buf, RX_MF_REPEAT_ERRf, 0xfff); 6227 soc_reg_field_set(unit, ILAMAC_RX_LANE_INTR3_STSr, &ilamac_rx_lane_intr3_enable_buf, RX_CRC32_ERRf, 0xfff); 6228 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, ILAMAC_RX_LANE_INTR3_ENABLEr, 0, 0, ilamac_rx_lane_intr3_enable_buf)); 6229 } 6230 6231 { 6232 static const struct { 6233 soc_field_t fld; 6234 uint32 val; 6235 } fldvals[] = { 6236 { TX_ERRINf, 1 }, 6237 { TX_OVERFLOW_ERRf, 1 }, 6238 { TX_UNDERFLOW_ERRf, 1 }, 6239 { TX_BURST_ERRf, 1 }, 6240 { TX_OVFOUTf, 1 } 6241 }; 6242 6243 uint32 ilamac_tx_intr_enable_buf = 0; 6244 unsigned i; 6245 6246 for (i = 0; i < COUNTOF(fldvals); ++i) { 6247 soc_reg_field_set(unit, ILAMAC_TX_INTR_STSr, &ilamac_tx_intr_enable_buf, fldvals[i].fld, fldvals[i].val); 6248 } 6249 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, ILAMAC_TX_INTR_ENABLEr, 0, 0, ilamac_tx_intr_enable_buf)); 6250 } 6251 6252 { 6253 static const struct { 6254 soc_field_t fld; 6255 uint32 val; 6256 } fldvals[] = { 6257 { TXPLL_LOCK_5f, 1 }, 6258 { TXPLL_LOCK_4f, 1 }, 6259 { TXPLL_LOCK_3f, 1 }, 6260 { TXPLL_LOCK_2f, 1 }, 6261 { TXPLL_LOCK_1f, 1 }, 6262 { TXPLL_LOCK_0f, 1 }, 6263 { RXSEQDONE1G_4_3f, 1 }, 6264 { RXSEQDONE1G_4_2f, 1 }, 6265 { RXSEQDONE1G_4_1f, 1 }, 6266 { RXSEQDONE1G_4_0f, 1 }, 6267 { RXSEQDONE1G_2_3f, 1 }, 6268 { RXSEQDONE1G_2_2f, 1 }, 6269 { RXSEQDONE1G_2_1f, 1 }, 6270 { RXSEQDONE1G_2_0f, 1 }, 6271 { RXSEQDONE1G_0_3f, 1 }, 6272 { RXSEQDONE1G_0_2f, 1 }, 6273 { RXSEQDONE1G_0_1f, 1 }, 6274 { RXSEQDONE1G_0_0f, 1 } 6275 }; 6276 6277 uint32 wcl_intr_enable_buf = 0; 6278 unsigned i; 6279 6280 for (i = 0; i < COUNTOF(fldvals); ++i) { 6281 soc_reg_field_set(unit, WCL_INTR_STSr, &wcl_intr_enable_buf, fldvals[i].fld, fldvals[i].val); 6282 } 6283 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, WCL_INTR_ENABLEr, 0, 0, wcl_intr_enable_buf)); 6284 } 6285 6286 { 6287 static const struct { 6288 soc_field_t fld; 6289 uint32 val; 6290 } fldvals[] = { 6291 { SBUS_STALL_MAX_LATf, 1 }, 6292 { EXT_L2_STALL_MAX_LATf, 1 }, 6293 { SBUS_STALL_GTE_CP_ACC_THRf, 1 }, 6294 { EXT_L2_STALL_GTE_CP_ACC_THRf, 1 }, 6295 { UNDERFLOW_DETECTEDf, 1 }, 6296 { OVERFLOW_DETECTEDf, 1 }, 6297 { FULLf, 1 }, 6298 { EARLY_FULLf, 1 }, 6299 { DBE_EVf, 1 }, 6300 { SBE_EVf, 1 }, 6301 { DBE_ODf, 1 }, 6302 { SBE_ODf, 1 } 6303 }; 6304 6305 uint32 etu_tx_req_fifo_intr_enable_buf = 0; 6306 unsigned i; 6307 6308 for (i = 0; i < COUNTOF(fldvals); ++i) { 6309 soc_reg_field_set(unit, ETU_TX_REQ_FIFO_INTR_STSr, &etu_tx_req_fifo_intr_enable_buf, fldvals[i].fld, fldvals[i].val); 6310 } 6311 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, ETU_TX_REQ_FIFO_INTR_ENABLEr, 0, 0, etu_tx_req_fifo_intr_enable_buf)); 6312 } 6313 6314 { 6315 static const struct { 6316 soc_field_t fld; 6317 uint32 val; 6318 } fldvals[] = { 6319 { UNDERFLOW_DETECTEDf, 1 }, 6320 { OVERFLOW_DETECTEDf, 1 }, 6321 { FULLf, 1 }, 6322 { EARLY_FULLf, 1 }, 6323 { DBEf, 1 }, 6324 { SBEf, 1 } 6325 }; 6326 6327 uint32 etu_tx_pipe_ctl_fifo_intr_enable_buf = 0; 6328 unsigned i; 6329 6330 for (i = 0; i < COUNTOF(fldvals); ++i) { 6331 soc_reg_field_set(unit, ETU_TX_PIPE_CTL_FIFO_INTR_STSr, &etu_tx_pipe_ctl_fifo_intr_enable_buf, fldvals[i].fld, fldvals[i].val); 6332 } 6333 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, ETU_TX_PIPE_CTL_FIFO_INTR_ENABLEr, 0, 0, etu_tx_pipe_ctl_fifo_intr_enable_buf)); 6334 } 6335 6336 { 6337 static const struct { 6338 soc_field_t fld; 6339 uint32 val; 6340 } fldvals[] = { 6341 { XOFF_RXf, 1 }, 6342 { UNDERFLOW_DETECTEDf, 1 }, 6343 { OVERFLOW_DETECTEDf, 1 }, 6344 { FULLf, 1 }, 6345 { DBE_EVf, 1 }, 6346 { SBE_EVf, 1 }, 6347 { DBE_ODf, 1 }, 6348 { SBE_ODf, 1 } 6349 }; 6350 6351 uint32 etu_rx_rsp_fifo_intr_enable_buf = 0; 6352 unsigned i; 6353 6354 for (i = 0; i < COUNTOF(fldvals); ++i) { 6355 soc_reg_field_set(unit, ETU_RX_RSP_FIFO_INTR_STSr, &etu_rx_rsp_fifo_intr_enable_buf, fldvals[i].fld, fldvals[i].val); 6356 } 6357 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, ETU_RX_RSP_FIFO_INTR_ENABLEr, 0, 0, etu_rx_rsp_fifo_intr_enable_buf)); 6358 } 6359 6360 _SHR_RETURN(SOC_E_NONE); 6361 } 6362 6363 6364 STATIC int 6365 init3(int unit, unsigned num_nl) 6366 { 6367 #if 0 6368 { 6369 const unsigned max_ptr_fme_req = 28; 6370 6371 unsigned ptr_fme_req; 6372 6373 for (ptr_fme_req = 1; ptr_fme_req <= max_ptr_fme_req; ++ptr_fme_req) { 6374 SOC_IF_ERROR_RETURN(prog_fme_costs(unit, ptr_fme_req, 0, 0, 0)); 6375 SOC_IF_ERROR_RETURN(prog_fme_costs(unit, ptr_fme_req, 1, 0, 0)); 6376 } 6377 } 6378 6379 { 6380 const unsigned max_allowed_latency_ns = (1000000 * ESMIF_ALLOWED_FIFO_DEPTH) / esmif_clk_freq_khz(unit); 6381 const unsigned percent_hysteresis = 90; 6382 const unsigned percent_drop_all = 50; 6383 6384 SOC_IF_ERROR_RETURN(prog_drop_all_costs(unit, max_allowed_latency_ns, percent_hysteresis)); 6385 SOC_IF_ERROR_RETURN(prog_drop_opt_costs(unit, percent_drop_all, percent_hysteresis)); 6386 } 6387 #else 6388 unsigned idle_req_rsp_latency_ns = 0; 6389 6390 /* get worst case fme ptr */ 6391 6392 6393 idle_req_rsp_latency_ns = soc_property_get(unit, spn_EXT_TCAM_REQUEST_RESPONSE_LATENCY, 0); 6394 SOC_IF_ERROR_RETURN(esm_prog_drop_all_cost_fme_req_cost(unit, 6395 &idle_req_rsp_latency_ns, 6396 soc_tr3_esm_get_worst_fme(unit))); 6397 #endif 6398 6399 SOC_IF_ERROR_RETURN(chk_esmif_adc(unit)); 6400 6401 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, ESM_ET_HWTL_CONTROLr, 0, 0, 0)); 6402 6403 { 6404 static const struct { 6405 soc_field_t fld; 6406 uint32 val; 6407 } fldvals[] = { 6408 { FORCE_ADM_CTRL_FIFO_READf, 0 }, 6409 { FORCE_ET_RSP_FIFO_READf, 0 }, 6410 { FORCE_L2ETU_ACKf, 0 }, 6411 { ETU_REQ_SEQ_NUM_SELf, 1 }, 6412 { MAX_CONTEXT_ADR_MSBf, 0x7f7 }, 6413 { EXT_LOOKUP_ENABLEf, 1 } 6414 }; 6415 6416 uint32 esm_misc_control_buf = 0; 6417 unsigned i; 6418 6419 for (i = 0; i < COUNTOF(fldvals); ++i) { 6420 soc_reg_field_set(unit, ESM_MISC_CONTROLr, &esm_misc_control_buf, fldvals[i].fld, fldvals[i].val); 6421 } 6422 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, ESM_MISC_CONTROLr, 0, 0, esm_misc_control_buf)); 6423 } 6424 6425 SOC_IF_ERROR_RETURN(enable_report_all_intr(unit)); 6426 6427 _SHR_RETURN(SOC_E_NONE); 6428 } 6429 6430 6431 STATIC unsigned 6432 num_nl_find_wb(int unit) 6433 { 6434 unsigned mdio_dev_id = 2; 6435 unsigned dev_id, num_nl; 6436 uint16 val; 6437 6438 for (num_nl = dev_id = 0; dev_id < 2; ++dev_id) { 6439 if (SOC_FAILURE(nl_mdio_read(unit, mdio_portid_get(unit, dev_id), 6440 mdio_dev_id, 0x12, &val)) || val != 0xaaaa) { 6441 break; 6442 } 6443 if (SOC_FAILURE(nl_mdio_read(unit, mdio_portid_get(unit, dev_id), 6444 mdio_dev_id, 0x13, &val)) || val != 0xaaaa) { 6445 break; 6446 } 6447 ++num_nl; 6448 } 6449 return num_nl; 6450 } 6451 6452 STATIC unsigned 6453 num_nl_find(int unit, unsigned first_reset_nl) 6454 { 6455 unsigned num_nl, dev_id; 6456 6457 if (SOC_WARM_BOOT(unit)) { 6458 return num_nl_find_wb(unit); 6459 } 6460 SOC_IF_ERROR_RETURN(etu_rst_nl_wcl_ilamac(unit, 0x9)); 6461 6462 sal_usleep(SRST_L_DEASSERTION_DELAY_US); 6463 6464 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, ETU_CONFIG4r, 0, EXT_TCAM_SRST_Lf, 1)); 6465 6466 sal_usleep(10); 6467 6468 for (num_nl = dev_id = 0; dev_id < 2; ++dev_id) { 6469 if (SOC_FAILURE(nl_mdio_test_reg_access(unit, 6470 mdio_portid_get(unit, dev_id)))) { 6471 break; 6472 } 6473 ++num_nl; 6474 } 6475 6476 return (num_nl); 6477 } 6478 6479 STATIC int 6480 clr_esm_mems(int unit) 6481 { 6482 esm_key_id_to_field_mapper_entry_t entry; 6483 6484 sal_memset(entry.entry_data, 0, sizeof(entry.entry_data)); 6485 6486 /* Clean up after the hardware tests are complete */ 6487 SOC_IF_ERROR_RETURN(soc_mem_write(unit, ESM_KEY_ID_TO_FIELD_MAPPERm, 6488 MEM_BLOCK_ALL, PTR_FME_REQ_CBI, entry.entry_data)); 6489 6490 _SHR_RETURN(SOC_E_NONE); 6491 } 6492 6493 int 6494 soc_tr3_esmif_init(int unit) 6495 { 6496 const unsigned max_init1_attempts = 5, /* <HP> Check this </HP> */ 6497 en_nl_parity_scan = 1, 6498 rx_fifo_thr = (100 << 8) | 120, 6499 tx_fifo_thr = (100 << 8) | 120, 6500 tx_burst_short_16b = 0; /* Specifying 0 => 8 bytes. less efficient 6501 choice is 16 bytes */ 6502 6503 unsigned first_reset_nl, num_nl, init1_cnt; 6504 unsigned master_wcl_num = 2; 6505 6506 if (SAL_BOOT_SIMULATION) { 6507 _SHR_RETURN(SOC_E_NONE); 6508 } 6509 6510 /* ESM Serdes master clk src */ 6511 master_wcl_num = soc_property_get(unit, spn_ESM_SERDES_MASTER_CLK_SRC, 2); 6512 6513 6514 SOC_IF_ERROR_RETURN(wcl_reset_seq(unit, master_wcl_num)); 6515 6516 first_reset_nl = 1; 6517 num_nl = num_nl_find(unit, first_reset_nl); 6518 if (num_nl < 1 || num_nl > 2) { 6519 return (SOC_E_FAIL); /* Only 1 or 2 NL devices allowed */ 6520 } 6521 6522 ((soc_tcam_info_t *) SOC_CONTROL(unit)->tcam_info)->num_tcams = num_nl; 6523 6524 if (SOC_WARM_BOOT(unit)) { 6525 SOC_IF_ERROR_RETURN(soc_tcam_init(unit)); 6526 SOC_IF_ERROR_RETURN(soc_triumph3_esm_init(unit)); 6527 return SOC_E_NONE; 6528 } 6529 6530 for (init1_cnt = 0; init1_cnt < max_init1_attempts; ++init1_cnt) { 6531 if (SOC_SUCCESS(init1(unit, 6532 num_nl, 6533 master_wcl_num, 6534 rx_fifo_thr, 6535 tx_fifo_thr, 6536 tx_burst_short_16b 6537 ) 6538 ) 6539 ) { 6540 break; 6541 } 6542 } 6543 /* If enable low jitter settings, re-run the initialization sequence */ 6544 if (nl_chk_low_jitter_settings(unit)) { 6545 apply_low_jitter_nl_settings = TRUE; 6546 for (init1_cnt = 0; init1_cnt < max_init1_attempts; ++init1_cnt) { 6547 if (SOC_SUCCESS(init1(unit, 6548 num_nl, 6549 master_wcl_num, 6550 rx_fifo_thr, 6551 tx_fifo_thr, 6552 tx_burst_short_16b 6553 ) 6554 ) 6555 ) { 6556 break; 6557 } 6558 } 6559 } 6560 6561 if (init1_cnt >= max_init1_attempts) { 6562 _SHR_RETURN(SOC_E_FAIL); 6563 } 6564 6565 SOC_IF_ERROR_RETURN(init2(unit, num_nl, en_nl_parity_scan, 0, 0)); 6566 6567 SOC_IF_ERROR_RETURN(init3(unit, num_nl)); 6568 6569 SOC_IF_ERROR_RETURN(chk_all_intr_sts(unit, num_nl)); 6570 SOC_IF_ERROR_RETURN(chk_fifos(unit)); 6571 SOC_IF_ERROR_RETURN(chk_esmif_adc(unit)); 6572 SOC_IF_ERROR_RETURN(chk_etu_counters(unit)); 6573 6574 { 6575 uint32 regbuf; 6576 6577 SOC_IF_ERROR_RETURN(READ_ESM_ET_HWTL_CONTROLr(unit, ®buf)); 6578 if (regbuf != 0) { 6579 return (SOC_E_FAIL); 6580 } 6581 6582 SOC_IF_ERROR_RETURN(READ_ESM_MISC_CONTROLr(unit, ®buf)); 6583 if (regbuf != 0x1fef) { 6584 return (SOC_E_FAIL); 6585 } 6586 } 6587 6588 SOC_IF_ERROR_RETURN(clr_esm_mems(unit)); 6589 6590 _SHR_RETURN(SOC_E_NONE); 6591 } 6592 6593 STATIC int 6594 etu_chk_errors(int unit) 6595 { 6596 static const soc_field_t flds[] = { 6597 RX_CW_ERS0f, 6598 RX_CW_ERRf 6599 }; 6600 uint32 rval, i; 6601 6602 READ_ETU_GLOBAL_INTR_STSr(unit, &rval); 6603 for (i = 0; i < COUNTOF(flds); i++) { 6604 if (soc_reg_field_get(unit, ETU_GLOBAL_INTR_STSr, rval, flds[i])) { 6605 return 1; 6606 } 6607 } 6608 return 0; 6609 } 6610 6611 #define NL_CRC_24_ERROR 0x0001 6612 #define NL_SOP_ERROR 0x0002 6613 #define NL_EOP_ERROR 0x0004 6614 #define NL_NO_DATA_ERROR 0x0008 6615 #define NL_BURST_MAX_ERROR 0x0010 6616 #define NL_ALIGNMENT_ERROR 0x0020 6617 #define NL_FRAMING_CW_ERROR 0x0040 6618 #define NL_RX_FIFO_ERROR 0x0080 6619 #define NL_INSTRUCTION_ERROR 0x0100 6620 #define NL_PROTOCOL_ERROR 0x0200 6621 #define NL_CHANNEL_ERROR 0x0400 6622 #define NL_CONTROL_WORD_ERROR 0x0800 6623 #define NL_EFIFO_ERROR 0x1000 6624 #define NL_CRX_UI_ERROR 0x2000 6625 #define NL_RX_UI_ERROR 0x4000 6626 #define NL_TX_FIFO_ERROR 0x8000 6627 STATIC int 6628 nl_chk_errors(int unit, unsigned dev_id) 6629 { 6630 unsigned mdio_portid; 6631 const unsigned mdio_dev_id = 1; 6632 uint16 nl_mdioval; 6633 uint32 i; 6634 6635 /* Array of all fields in the Common Status register in NL11K that would 6636 be considered a fatal error requiring recovery */ 6637 static const uint16 error_types[] = { 6638 NL_ALIGNMENT_ERROR 6639 }; 6640 6641 mdio_portid = mdio_portid_get(unit, dev_id); 6642 nl_mdio_read(unit, mdio_portid, mdio_dev_id, 0x8180, &nl_mdioval); 6643 for (i = 0; i < COUNTOF(error_types); i++) { 6644 if (nl_mdioval & error_types[i]) { 6645 return 1; 6646 } 6647 } 6648 return 0; 6649 } 6650 6651 STATIC int 6652 esm_chk_giol(int unit) 6653 { 6654 uint32 rval; 6655 unsigned giol0, giol1; 6656 6657 READ_ETU_GLOBAL_INTR_STSr(unit, &rval); 6658 giol0 = soc_reg_field_get(unit, ETU_GLOBAL_INTR_STSr, rval, 6659 EXT_TCAM_INTR0f); 6660 giol1 = soc_reg_field_get(unit, ETU_GLOBAL_INTR_STSr, rval, 6661 EXT_TCAM_INTR1f); 6662 6663 if (giol0) { 6664 LOG_ERROR(BSL_LS_SOC_ESM, 6665 (BSL_META_U(unit, 6666 "GIOL0 is asserted on unit %d!.\n"), unit)); 6667 } 6668 if (giol1) { 6669 LOG_ERROR(BSL_LS_SOC_ESM, 6670 (BSL_META_U(unit, 6671 "GIOL1 is asserted on unit %d!.\n"), unit)); 6672 } 6673 return giol0 | giol1; 6674 } 6675 6676 /* 6677 * Function to be filled-in by customer to do required operations when max 6678 * threshold is reached. 6679 * Eg: A msg can be posted to application thread to do switch reset operations 6680 */ 6681 STATIC int 6682 nl_tcam_err_max_threshold(int unit, unsigned dev_id) 6683 { 6684 LOG_ERROR(BSL_LS_SOC_ESM, 6685 (BSL_META_U(unit, 6686 "NL11K error max threshold reached on " 6687 "device %d on unit %d.\n"), 6688 dev_id, unit)); 6689 return SOC_E_NONE; 6690 } 6691 6692 STATIC int 6693 nl_clear_tcam_error(int unit, unsigned dev_id, nl_reg_buf_t regval) 6694 { 6695 int rv; 6696 nl_reg_buf_t nl_regval; 6697 nl_reg_buf_t nl_regval_adv; 6698 nl_reg_buf_t wr_data; 6699 unsigned reg_addr; 6700 uint32 nl_ltr; 6701 6702 rv = SOC_E_NONE; 6703 6704 sal_memcpy(nl_regval, regval, sizeof(nl_reg_buf_t)); 6705 6706 SOC_IF_ERROR_RETURN( 6707 nl_reg_read(unit, dev_id, NL_REG_ADDR_ADV_FEATURES_SOFT_ERR, 6708 nl_regval_adv)); 6709 6710 LOG_ERROR(BSL_LS_SOC_ESM, 6711 (BSL_META_U(unit, 6712 "NL11K error register" 6713 "[0x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x] on " 6714 "device %d on unit %d.\n"), 6715 nl_regval[9], 6716 nl_regval[8], 6717 nl_regval[7], 6718 nl_regval[6], 6719 nl_regval[5], 6720 nl_regval[4], 6721 nl_regval[3], 6722 nl_regval[2], 6723 nl_regval[1], 6724 nl_regval[0], 6725 dev_id, unit)); 6726 6727 LOG_ERROR(BSL_LS_SOC_ESM, 6728 (BSL_META_U(unit, 6729 "NL11K Adv Feat soft error register" 6730 "[0x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x] on " 6731 "device %d on unit %d.\n"), 6732 nl_regval_adv[9], 6733 nl_regval_adv[8], 6734 nl_regval_adv[7], 6735 nl_regval_adv[6], 6736 nl_regval_adv[5], 6737 nl_regval_adv[4], 6738 nl_regval_adv[3], 6739 nl_regval_adv[2], 6740 nl_regval_adv[1], 6741 nl_regval_adv[0], 6742 dev_id, unit)); 6743 6744 /* Check status of bit 28 LTR Parity Error */ 6745 if (nl_reg_buf_bitfield_get(nl_regval, 28, 1)) { 6746 /* Get LTR info from ADV FEAT SOFT ERR register. 6747 * It can be LTR number or LTR address 6748 * irrespective of operation type bits [58:53] will 6749 * represent LTR number */ 6750 nl_ltr = nl_reg_buf_bitfield_get(nl_regval_adv, 53, 6); 6751 6752 rv = soc_tr3_restore_ltr(unit, dev_id, nl_ltr); 6753 if (SOC_FAILURE(rv)) { 6754 LOG_ERROR(BSL_LS_SOC_ESM, 6755 (BSL_META_U(unit, 6756 "Failed to restore LTR parity error on " 6757 "LTR number %d on unit %d. rv %d\n"), 6758 nl_ltr, unit, rv)); 6759 } 6760 } 6761 6762 /* Check status of bit 29 Context Buffer Parity Error */ 6763 if (nl_reg_buf_bitfield_get(nl_regval, 29, 1)) { 6764 /* Get Context buffer address from ADV FEAT SOFT ERR register */ 6765 reg_addr = nl_reg_buf_bitfield_get(nl_regval_adv, 0, 14); 6766 sal_memset(wr_data, 0, sizeof(wr_data)); 6767 rv = nl_ctx_buf_reg_write_loc80(unit, dev_id, reg_addr, wr_data); 6768 if (SOC_FAILURE(rv)) { 6769 LOG_ERROR(BSL_LS_SOC_ESM, 6770 (BSL_META_U(unit, 6771 "Failed to reset Context parity error on " 6772 "addr 0x%x on unit %d. rv %d\n"), 6773 reg_addr, unit, rv)); 6774 } 6775 } 6776 6777 /* Reset bits 28, 29 */ 6778 nl_reg_buf_bitfield_set(nl_regval, 28, 2 , 0); 6779 6780 /* Check if any other error bits are set */ 6781 if (!nl_reg_buf_is_zero(nl_regval)) { 6782 if (++nl_tcam_err_count[unit] > NL_TCAM_ERR_THRESHOLD_COUNT) { 6783 SOC_IF_ERROR_RETURN(nl_tcam_err_max_threshold(unit, dev_id)); 6784 nl_tcam_err_count[unit] = 0; 6785 } 6786 } 6787 6788 return rv; 6789 } 6790 6791 STATIC int 6792 nl_clear_giol(int unit, unsigned num_nl) 6793 { 6794 int rv; 6795 unsigned dev_id, mdio_portid, chk_crx; 6796 nl_reg_buf_t nl_regval; 6797 6798 /* Clear ERROR_STATUS register to de-assert GIO_L[0] */ 6799 for (dev_id = 0; dev_id < num_nl; ++dev_id) { 6800 SOC_IF_ERROR_RETURN(nl_reg_read(unit, dev_id, NL_REG_ADDR_ERR_STS, 6801 nl_regval)); 6802 6803 /* Check if any error bits are set */ 6804 if (nl_reg_buf_is_zero(nl_regval) == 0) { 6805 SOC_IF_ERROR_RETURN(nl_clear_tcam_error(unit, dev_id, nl_regval)); 6806 } 6807 6808 SOC_IF_ERROR_RETURN(nl_reg_write(unit, dev_id, NL_REG_ADDR_ERR_STS, 6809 nl_regval, 0, 0, 0)); 6810 if (nl_chk_err_status_reg(unit, dev_id)) { 6811 LOG_ERROR(BSL_LS_SOC_ESM, 6812 (BSL_META_U(unit, 6813 "Failed to clear the NL11K error register on " 6814 "device %d on unit %d.\n"), dev_id, unit)); 6815 } 6816 } 6817 6818 /* Clear GIO_L[1] */ 6819 for (dev_id = 0; dev_id < num_nl; ++dev_id) { 6820 mdio_portid = mdio_portid_get(unit, dev_id); 6821 chk_crx = (dev_id != 0); 6822 /* 1st time: chk csm_status and ignore any errors (that could have 6823 happened during init sequence of NL) */ 6824 SOC_IF_ERROR_RETURN(nl_mdio_clr_csm_status_regs(unit, mdio_portid, 1)); 6825 6826 /* from now on : chk csm_status and make sure there are no errors */ 6827 rv = nl_mdio_chk_csm_status_regs(unit, mdio_portid, chk_crx); 6828 if (rv < SOC_E_NONE) { 6829 LOG_ERROR(BSL_LS_SOC_ESM, 6830 (BSL_META_U(unit, 6831 "Status check failed on NL11K " 6832 "device %d on unit %d.\n"), dev_id, unit)); 6833 } 6834 } 6835 6836 if (esm_chk_giol(unit)) { 6837 LOG_ERROR(BSL_LS_SOC_ESM, 6838 (BSL_META_U(unit, 6839 "Failed to clear GIOL status on unit %d.\n"), unit)); 6840 return SOC_E_FAIL; 6841 } 6842 return SOC_E_NONE; 6843 } 6844 6845 #define ESM_IF_ERROR_RETURN_UNLOCK(unit, rv) \ 6846 if (SOC_FAILURE(rv)) { \ 6847 MEM_UNLOCK(unit, ETU_TX_RAW_REQ_DATA_WORDm); \ 6848 SOC_ESM_UNLOCK(unit); \ 6849 return rv; \ 6850 } \ 6851 6852 STATIC int 6853 esm_err_recovery_seq(int unit, unsigned num_nl) 6854 { 6855 uint32 error = 0; 6856 uint32 l2x_running = 0, l2x_flags; 6857 sal_usecs_t l2x_interval; 6858 uint32 rval; 6859 uint32 learn_ctrl, kt_a, kt_b; 6860 uint32 ipipe_req_count0, ipipe_rsp_count0; 6861 uint32 ipipe_req_count1, ipipe_rsp_count1; 6862 uint64 tx_pkt_count0, rx_pkt_count0; 6863 uint64 tx_pkt_count1, rx_pkt_count1; 6864 unsigned dev_id; 6865 int rv; 6866 6867 /* Disable reporting of interrupts */ 6868 SOC_IF_ERROR_RETURN(dis_intr(unit)); 6869 6870 /* set etu_int_mem_rst.start = 0 to prevent xlat table being reset */ 6871 SOC_IF_ERROR_RETURN(READ_ETU_INT_MEM_RSTr(unit, &rval)); 6872 soc_reg_field_set(unit, ETU_INT_MEM_RSTr, &rval, STARTf, 0); 6873 soc_reg_field_set(unit, ETU_INT_MEM_RSTr, &rval, COMPLETEf, 0); 6874 SOC_IF_ERROR_RETURN(WRITE_ETU_INT_MEM_RSTr(unit, rval)); 6875 6876 /* Disable sending of lookup requests from IPIPE */ 6877 SOC_IF_ERROR_RETURN(READ_ESM_MISC_CONTROLr(unit, &rval)); 6878 soc_reg_field_set(unit, ESM_MISC_CONTROLr, &rval, EXT_LOOKUP_ENABLEf, 0); 6879 SOC_IF_ERROR_RETURN(WRITE_ESM_MISC_CONTROLr(unit, rval)); 6880 6881 /* Disable all software and hardware accesses to NL11K */ 6882 if (soc_l2x_running(unit, &l2x_flags, &l2x_interval)) { 6883 l2x_running = 1; 6884 SOC_IF_ERROR_RETURN(soc_l2x_stop(unit)); 6885 } 6886 /* Add MEM_LOCK to avoid deadlock with external TCAM memory access */ 6887 MEM_LOCK(unit, ETU_TX_RAW_REQ_DATA_WORDm); 6888 SOC_ESM_LOCK(unit); 6889 6890 /* Ensure that no hardware learns happen by making use of the 6891 LEARN_FLOOD cabaility to cover keys that ESM supports (BRIDGE/VFI) */ 6892 rv = READ_FLOOD_LEARN_KEY_TYPE_PORT_Ar(unit, &kt_a); 6893 ESM_IF_ERROR_RETURN_UNLOCK(unit, rv); 6894 6895 rv = READ_FLOOD_LEARN_KEY_TYPE_PORT_Br(unit, &kt_b); 6896 ESM_IF_ERROR_RETURN_UNLOCK(unit, rv); 6897 6898 rv = READ_FLOOD_LEARN_CONTROLr(unit, &learn_ctrl); 6899 ESM_IF_ERROR_RETURN_UNLOCK(unit, rv); 6900 6901 rval = 0; 6902 soc_reg_field_set(unit, FLOOD_LEARN_KEY_TYPE_PORT_Ar, &rval, KEY_TYPEf, 0); 6903 rv = WRITE_FLOOD_LEARN_KEY_TYPE_PORT_Ar(unit, rval); 6904 ESM_IF_ERROR_RETURN_UNLOCK(unit, rv); 6905 6906 rval = 0; 6907 soc_reg_field_set(unit, FLOOD_LEARN_KEY_TYPE_PORT_Br, &rval, KEY_TYPEf, 1); 6908 rv = WRITE_FLOOD_LEARN_KEY_TYPE_PORT_Br(unit, rval); 6909 ESM_IF_ERROR_RETURN_UNLOCK(unit, rv); 6910 6911 rval = 0; 6912 soc_reg_field_set(unit, FLOOD_LEARN_CONTROLr, &rval, 6913 MATCH_KEY_TYPE_PORT_Af, 1); 6914 soc_reg_field_set(unit, FLOOD_LEARN_CONTROLr, &rval, 6915 MATCH_KEY_TYPE_PORT_Bf, 1); 6916 soc_reg_field_set(unit, FLOOD_LEARN_CONTROLr, &rval, 6917 LEARN_DISABLEf, 1); 6918 rv = WRITE_FLOOD_LEARN_CONTROLr(unit, rval); 6919 ESM_IF_ERROR_RETURN_UNLOCK(unit, rv); 6920 6921 /* Make sure that ipipe_req_count, ipipe_rsp_count are no longer 6922 incrementing - this tells us that tcam + etu system is IDLING */ 6923 /* max buffer_size in esmif is 2 uS, so 4 uS should be enough to 6924 flush everything in etu-NL11K */ 6925 sal_usleep(4); 6926 rv = READ_ETU_DBG_IPIPE_REQ_RSP_COUNTr(unit, &rval); 6927 ESM_IF_ERROR_RETURN_UNLOCK(unit, rv); 6928 6929 ipipe_req_count0 = soc_reg_field_get(unit, ETU_DBG_IPIPE_REQ_RSP_COUNTr, 6930 rval, REQ_COUNTf); 6931 ipipe_rsp_count0 = soc_reg_field_get(unit, ETU_DBG_IPIPE_REQ_RSP_COUNTr, 6932 rval, RSP_COUNTf); 6933 rv = READ_ILAMAC_TX_PACKETS_COUNTr(unit, &tx_pkt_count0); 6934 ESM_IF_ERROR_RETURN_UNLOCK(unit, rv); 6935 6936 rv = READ_ILAMAC_RX_PACKETS_COUNTr(unit, &rx_pkt_count0); 6937 ESM_IF_ERROR_RETURN_UNLOCK(unit, rv); 6938 6939 sal_usleep(1); 6940 rv = READ_ETU_DBG_IPIPE_REQ_RSP_COUNTr(unit, &rval); 6941 ESM_IF_ERROR_RETURN_UNLOCK(unit, rv); 6942 6943 ipipe_req_count1 = soc_reg_field_get(unit, ETU_DBG_IPIPE_REQ_RSP_COUNTr, 6944 rval, REQ_COUNTf); 6945 ipipe_rsp_count1 = soc_reg_field_get(unit, ETU_DBG_IPIPE_REQ_RSP_COUNTr, 6946 rval, RSP_COUNTf); 6947 rv = READ_ILAMAC_TX_PACKETS_COUNTr(unit, &tx_pkt_count1); 6948 ESM_IF_ERROR_RETURN_UNLOCK(unit, rv); 6949 6950 rv = READ_ILAMAC_RX_PACKETS_COUNTr(unit, &rx_pkt_count1); 6951 ESM_IF_ERROR_RETURN_UNLOCK(unit, rv); 6952 6953 if (ipipe_req_count0 != ipipe_req_count1) { 6954 LOG_ERROR(BSL_LS_SOC_ESM, 6955 (BSL_META_U(unit, 6956 "Not successful in stopping Esmif lookup " 6957 "requests to Etu on unit %d.\n"), unit)); 6958 error++; 6959 } 6960 if (COMPILER_64_NE(tx_pkt_count0, tx_pkt_count1)) { 6961 LOG_ERROR(BSL_LS_SOC_ESM, 6962 (BSL_META_U(unit, 6963 "Not successful in stopping ETU requests " 6964 "to NL11K on unit %d.\n"), unit)); 6965 error++; 6966 } 6967 if (COMPILER_64_NE(rx_pkt_count0, rx_pkt_count1)) { 6968 LOG_ERROR(BSL_LS_SOC_ESM, 6969 (BSL_META_U(unit, 6970 "Not successful in stopping NL11K responses " 6971 "to ETU on unit %d.\n"), unit)); 6972 error++; 6973 } 6974 if (ipipe_rsp_count0 != ipipe_rsp_count1) { 6975 LOG_ERROR(BSL_LS_SOC_ESM, 6976 (BSL_META_U(unit, 6977 "Not successful in stopping Etu responses to " 6978 "to Esmif on unit %d.\n"), unit)); 6979 error++; 6980 } 6981 6982 /* Force draining of Esmif fifos */ 6983 rv = READ_ESM_MISC_CONTROLr(unit, &rval); 6984 ESM_IF_ERROR_RETURN_UNLOCK(unit, rv); 6985 6986 soc_reg_field_set(unit, ESM_MISC_CONTROLr, &rval, 6987 FORCE_ADM_CTRL_FIFO_READf, 1); 6988 soc_reg_field_set(unit, ESM_MISC_CONTROLr, &rval, 6989 FORCE_ET_RSP_FIFO_READf, 1); 6990 rv = WRITE_ESM_MISC_CONTROLr(unit, rval); 6991 ESM_IF_ERROR_RETURN_UNLOCK(unit, rv); 6992 6993 /* Reset etu datapath */ 6994 rv = READ_ETU_CONFIG4r(unit, &rval); 6995 ESM_IF_ERROR_RETURN_UNLOCK(unit, rv); 6996 6997 soc_reg_field_set(unit, ETU_CONFIG4r, &rval, 6998 DATAPATH_RST_f, 1); 6999 rv = WRITE_ETU_CONFIG4r(unit, rval); 7000 ESM_IF_ERROR_RETURN_UNLOCK(unit, rv); 7001 7002 sal_usleep(1); 7003 rv = READ_ETU_CONFIG4r(unit, &rval); 7004 ESM_IF_ERROR_RETURN_UNLOCK(unit, rv); 7005 7006 soc_reg_field_set(unit, ETU_CONFIG4r, &rval, 7007 DATAPATH_RST_f, 0); 7008 rv = WRITE_ETU_CONFIG4r(unit, rval); 7009 ESM_IF_ERROR_RETURN_UNLOCK(unit, rv); 7010 7011 /* Release forced draining of esmif fifos */ 7012 rv = READ_ESM_MISC_CONTROLr(unit, &rval); 7013 ESM_IF_ERROR_RETURN_UNLOCK(unit, rv); 7014 7015 soc_reg_field_set(unit, ESM_MISC_CONTROLr, &rval, 7016 FORCE_ADM_CTRL_FIFO_READf, 0); 7017 soc_reg_field_set(unit, ESM_MISC_CONTROLr, &rval, 7018 FORCE_ET_RSP_FIFO_READf, 0); 7019 rv = WRITE_ESM_MISC_CONTROLr(unit, rval); 7020 ESM_IF_ERROR_RETURN_UNLOCK(unit, rv); 7021 7022 /* Clear pending costs in esmif_adc */ 7023 rval = 0; 7024 rv = WRITE_ESMIF_CUR_PENDING_COST0r(unit, rval); 7025 ESM_IF_ERROR_RETURN_UNLOCK(unit, rv); 7026 7027 rv = WRITE_ESMIF_CUR_PENDING_COST1r(unit, rval); 7028 ESM_IF_ERROR_RETURN_UNLOCK(unit, rv); 7029 7030 rv = WRITE_ESMIF_CUR_PENDING_COST2r(unit, rval); 7031 ESM_IF_ERROR_RETURN_UNLOCK(unit, rv); 7032 7033 /* Clean up all nl status regs */ 7034 rv = nl_clear_giol(unit, num_nl); 7035 ESM_IF_ERROR_RETURN_UNLOCK(unit, rv); 7036 7037 /* Clear all interrupts, etu_counters, adc_max_logs */ 7038 if (clr_all_intr_sts(unit)) error++; 7039 if (clr_etu_counters(unit)) error++; 7040 if (clr_adc_max_logs(unit)) error++; 7041 7042 /* make sure nothing is reported without traffic */ 7043 if (chk_fifos(unit)) { 7044 LOG_ERROR(BSL_LS_SOC_ESM, 7045 (BSL_META_U(unit, 7046 "ESM FIFO check failed on unit %d.\n"), unit)); 7047 error++; 7048 } 7049 if (chk_etu_counters(unit)) { 7050 LOG_ERROR(BSL_LS_SOC_ESM, 7051 (BSL_META_U(unit, 7052 "ESM counter check failed on unit %d.\n"), unit)); 7053 error++; 7054 } 7055 if (chk_all_intr_sts(unit, num_nl)) { 7056 LOG_ERROR(BSL_LS_SOC_ESM, 7057 (BSL_META_U(unit, 7058 "ESM interrupt check failed on unit %d.\n"), unit)); 7059 error++; 7060 } 7061 if (chk_esmif_adc(unit)) { 7062 LOG_ERROR(BSL_LS_SOC_ESM, 7063 (BSL_META_U(unit, 7064 "ESM ADC check failed on unit %d.\n"), unit)); 7065 error++; 7066 } 7067 for (dev_id = 0; dev_id < num_nl; ++dev_id) { 7068 if (nl_chk_errors(unit, dev_id)) { 7069 LOG_ERROR(BSL_LS_SOC_ESM, 7070 (BSL_META_U(unit, 7071 "Failed to clear errors on NL11K " 7072 "device %d on unit %d.\n"), dev_id, unit)); 7073 error++; 7074 } 7075 } 7076 7077 if (!error) { 7078 /* resume sending of lookup requests from IPIPE */ 7079 rv = READ_ESM_MISC_CONTROLr(unit, &rval); 7080 ESM_IF_ERROR_RETURN_UNLOCK(unit, rv); 7081 7082 soc_reg_field_set(unit, ESM_MISC_CONTROLr, &rval, EXT_LOOKUP_ENABLEf, 1); 7083 rv = WRITE_ESM_MISC_CONTROLr(unit, rval); 7084 ESM_IF_ERROR_RETURN_UNLOCK(unit, rv); 7085 } 7086 7087 /* Allow software and hardware access to the NL11K */ 7088 rv = WRITE_FLOOD_LEARN_KEY_TYPE_PORT_Ar(unit, kt_a); 7089 ESM_IF_ERROR_RETURN_UNLOCK(unit, rv); 7090 7091 rv = WRITE_FLOOD_LEARN_KEY_TYPE_PORT_Br(unit, kt_b); 7092 ESM_IF_ERROR_RETURN_UNLOCK(unit, rv); 7093 7094 rv= WRITE_FLOOD_LEARN_CONTROLr(unit, learn_ctrl); 7095 ESM_IF_ERROR_RETURN_UNLOCK(unit, rv); 7096 7097 MEM_UNLOCK(unit, ETU_TX_RAW_REQ_DATA_WORDm); 7098 SOC_ESM_UNLOCK(unit); 7099 7100 if (l2x_running) { 7101 rv = soc_l2x_start(unit, l2x_flags, l2x_interval); 7102 if (SOC_FAILURE(rv)) { 7103 return rv; 7104 } 7105 } 7106 7107 /* resume reporting of interrupts */ 7108 rv = enable_report_all_intr(unit); 7109 if (SOC_FAILURE(rv)) { 7110 return rv; 7111 } 7112 if (error) { 7113 return SOC_E_FAIL; 7114 } 7115 7116 return SOC_E_NONE; 7117 } 7118 7119 STATIC void 7120 soc_tr3_esm_interrupt_process(int unit) 7121 { 7122 unsigned num_nl; 7123 static unsigned count = 0; 7124 int rv; 7125 7126 num_nl = ((soc_tcam_info_t *) SOC_CONTROL(unit)->tcam_info)->num_tcams; 7127 7128 /* If ETU error, apply recovery sequence */ 7129 if (etu_chk_errors(unit)) { 7130 count++; 7131 LOG_ERROR(BSL_LS_SOC_ESM, 7132 (BSL_META_U(unit, 7133 "Recovering from ETU alignment error on " 7134 "unit %d (incident #%d).\n"), unit, count)); 7135 rv = esm_err_recovery_seq(unit, num_nl); 7136 if (rv < SOC_E_NONE) { 7137 LOG_ERROR(BSL_LS_SOC_ESM, 7138 (BSL_META_U(unit, 7139 "ETU alignment recovery failed on " 7140 "unit %d.\n"), unit)); 7141 } 7142 } 7143 return; 7144 } 7145 7146 STATIC void 7147 soc_tr3_esm_recovery_thread(void* unit_vp) 7148 { 7149 int unit = PTR_TO_INT(unit_vp); 7150 soc_control_t * soc = SOC_CONTROL(unit); 7151 7152 while(1) { 7153 sal_sem_take(soc->esm_recovery_notify, sal_sem_FOREVER); 7154 if (soc->esm_recovery_enable == TRUE) { 7155 soc_tr3_esm_interrupt_process(unit); 7156 } else { 7157 break; 7158 } 7159 } 7160 soc->esm_recovery_pid = SAL_THREAD_ERROR; 7161 sal_thread_exit(0); 7162 } 7163 7164 int 7165 soc_tr3_esm_recovery_start(int unit) 7166 { 7167 soc_control_t * soc = SOC_CONTROL(unit); 7168 7169 if (soc->esm_recovery_pid != SAL_THREAD_ERROR) { 7170 SOC_IF_ERROR_RETURN(soc_tr3_esm_recovery_stop(unit)); 7171 } 7172 7173 soc->esm_recovery_enable = TRUE; 7174 /* Spawn a task */ 7175 soc->esm_recovery_pid = sal_thread_create("esm_recovery", 7176 SAL_THREAD_STKSZ, 7177 soc_property_get(unit, spn_ESM_RECOVERY_THREAD_PRI, 50), 7178 soc_tr3_esm_recovery_thread, INT_TO_PTR(unit)); 7179 7180 if (soc->esm_recovery_pid == SAL_THREAD_ERROR) { 7181 LOG_ERROR(BSL_LS_SOC_ESM, 7182 (BSL_META_U(unit, 7183 "soc_tr3_esm_recovery_start: " 7184 "Could not start esm recovery thread\n"))); 7185 return SOC_E_MEMORY; 7186 } 7187 7188 return SOC_E_NONE; 7189 } 7190 7191 int 7192 soc_tr3_esm_recovery_stop (int unit) 7193 { 7194 soc_control_t *soc = SOC_CONTROL(unit); 7195 int rv = SOC_E_NONE; 7196 soc_timeout_t to; 7197 7198 soc->esm_recovery_enable = FALSE; 7199 7200 if (soc->esm_recovery_pid != SAL_THREAD_ERROR) { 7201 sal_sem_give(soc->esm_recovery_notify); 7202 7203 /* Give thread 5 seconds to wake up and exit */ 7204 soc_timeout_init(&to, 5 * 1000000, 0); 7205 /* wait for esm thread quit completely */ 7206 while (soc->esm_recovery_pid != SAL_THREAD_ERROR) { 7207 if (soc_timeout_check(&to)) { 7208 LOG_ERROR(BSL_LS_SOC_ESM, 7209 (BSL_META_U(unit, 7210 "soc_tr3_esm_recovery_stop: " 7211 "esm_thread not exit timeout 5 seconds\n"))); 7212 rv = SOC_E_TIMEOUT; 7213 break; 7214 } 7215 } 7216 } 7217 return rv; 7218 } 7219 7220 #endif /* BCM_TRIUMPH3_SUPPORT */