triumph3.c (874357B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: triumph3.c 8 * Purpose: 9 * Requires: 10 */ 11 12 13 #include <shared/bsl.h> 14 15 #include <sal/core/boot.h> 16 #include <shared/bsl.h> 17 #include <soc/drv.h> 18 #include <soc/error.h> 19 #include <soc/debug.h> 20 #include <soc/mem.h> 21 #include <soc/mmu_config.h> 22 #include <soc/tcam/tcamtype1.h> 23 #include <soc/er_tcam.h> 24 #include <soc/bradley.h> 25 #include <soc/triumph3.h> 26 #include <soc/mspi.h> 27 #include <soc/l2x.h> 28 #include <soc/soc_ser_log.h> 29 #ifdef BCM_HELIX4_SUPPORT 30 #include <soc/helix4.h> 31 #endif /* BCM_HELIX4_SUPPORT */ 32 #include <soc/post.h> 33 34 #ifdef BCM_TRIUMPH3_SUPPORT 35 36 #define SOC_MAX_PHY_PORTS 86 37 38 #define CORE_MODE_SINGLE 0 39 #define CORE_MODE_DUAL 1 40 #define CORE_MODE_QUAD 2 41 #define CORE_MODE_NOTDM 3 42 43 #define PHY_MODE_SINGLE 0 44 #define PHY_MODE_DUAL 1 45 #define PHY_MODE_QUAD 2 46 47 #define MAC_MODE_INDEP 0 48 #define MAC_MODE_AGGR 1 49 50 #define _MAX_TR3_FLEX_PORT_PROPS 11 51 #define _MAX_TR3_PORT_CFG _MAX_TR3_FLEX_PORT_PROPS 52 /* #define _MAX_TR3_FLEX_PORT_GROUPS 20 */ /* Total num of XC, WC -1 */ 53 #define _MAX_TR3_TDM_SLOTS 380 54 55 #define WC40_UCMEM_DATA_ENTRY_LEN 16 56 57 #define _TR3_MMU_CELLS_RSVD_IP 100 58 59 #define _TR3_MMU_MAX_PACKET_BYTES 10240 /* bytes */ 60 #define _TR3_MMU_PACKET_HEADER_BYTES 64 /* bytes */ 61 #define _TR3_MMU_JUMBO_FRAME_BYTES 9216 /* bytes */ 62 #define _TR3_MMU_DEFAULT_MTU_BYTES 1536 /* bytes */ 63 64 #define _TR3_MMU_TOTAL_CELLS_24K 24576 /* 24k cells */ 65 #define _TR3_MMU_TOTAL_CELLS_19K 19456 /* 19k cells */ 66 67 int _soc_tr3_mmu_buffer_cells[SOC_MAX_NUM_DEVICES]; 68 69 #define _TR3_MMU_TOTAL_CELLS(unit) _soc_tr3_mmu_buffer_cells[(unit)] 70 71 #define _TR3_MMU_BYTES_PER_CELL 208 /* bytes (1664 bits) */ 72 #define _TR3_MMU_NUM_PG 8 73 #define _TR3_MMU_NUM_POOL 4 74 75 /* Default ISM mem config sizes 76 * These are scaled down automatically for various SKU's 77 */ 78 #define _ISM_MAX_MEMS 8 79 #define _ISM_MEM_VLAN_XLATE_SIZE (32*1024) 80 #define _ISM_MEM_L2_SIZE (64*1024) 81 #define _ISM_MEM_L3_SIZE (32*1024) 82 #define _ISM_MEM_EP_VLAN_XLATE_SIZE (16*1024) 83 #define _ISM_MEM_MPLS_SIZE (32*1024) 84 85 #define _SOC_TR3_DEFIP_MAX_TCAMS 8 86 #define _SOC_TR3_DEFIP_TCAM_DEPTH 1024 87 88 #define _SOC_AP2_DEFIP_MAX_TCAMS 6 89 #define _SOC_AP2_DEFIP_TCAM_DEPTH 1024 90 91 #define _BCM_TR3_NUM_L2_UC_LEAVES 1024 92 93 #define _TR3_RESUME_OPTION_CELL 0 94 #define _TR3_RESUME_OFFSET_RED_CELL 2 95 /*wireless reassembly cell*/ 96 #define _TR3_MMU_WL_RESERVE_CELL_NUM 2 97 98 void soc_tr3_oam_interrupt_process(int unit); 99 100 typedef enum { 101 _SOC_PARITY_TYPE_NONE, 102 _SOC_PARITY_TYPE_GENERIC, 103 _SOC_PARITY_TYPE_PARITY, 104 _SOC_PARITY_TYPE_ECC, 105 _SOC_PARITY_TYPE_MMU_THDO, 106 _SOC_PARITY_TYPE_MMU_THDI, 107 _SOC_PARITY_TYPE_MMU_WRED, 108 _SOC_PARITY_TYPE_MMU_QCN, 109 _SOC_PARITY_TYPE_MMU_LLS, 110 _SOC_PARITY_TYPE_AXP, 111 _SOC_PARITY_TYPE_BST, 112 _SOC_PARITY_TYPE_SER, 113 _SOC_PARITY_INFO_TYPE_OAM, 114 _SOC_PARITY_TYPE_MMU_MTRO, 115 _SOC_PARITY_TYPE_MMU_OVQ, 116 _SOC_PARITY_INFO_TYPE_NUM 117 } _soc_tr3_parity_info_type_t; 118 119 typedef struct _soc_tr3_parity_info_s { 120 soc_reg_t enable_reg; 121 soc_field_t enable_field; 122 } _soc_tr3_fifo_parity_info_t; 123 124 typedef struct _soc_tr3_parity_block_info_s { 125 soc_block_t blocktype; 126 soc_reg_t fifo_reset_reg; 127 _soc_tr3_fifo_parity_info_t *info; 128 } _soc_tr3_parity_block_info_t; 129 130 typedef struct _soc_tr3_parity_reg_s { 131 soc_reg_t reg; 132 char *mem_str; 133 } _soc_tr3_parity_reg_t; 134 135 typedef struct _soc_tr3_parity_mmu_bit_s { 136 uint32 bit_pos; 137 soc_mem_t mem; 138 } _soc_tr3_parity_mmu_bit_t; 139 140 typedef struct _soc_tr3_parity_mmu_bit_reg_s { 141 uint32 bit_pos; 142 soc_mem_t mem; 143 soc_reg_t addr_reg; 144 } _soc_tr3_parity_mmu_bit_reg_t; 145 146 typedef struct _soc_tr3_parity_mmu_bit_fld_s { 147 uint32 bit_pos; 148 soc_mem_t mem; 149 soc_field_t idxf; 150 } _soc_tr3_parity_mmu_bit_fld_t; 151 152 typedef struct _soc_tr3_parity_mmu_bit_reg_idx_s { 153 uint32 bit_pos; 154 soc_mem_t mem; 155 soc_reg_t addr_reg; 156 soc_field_t idxf; 157 uint8 uncorrectable; 158 } _soc_tr3_parity_mmu_bit_reg_fld_t; 159 160 typedef struct _soc_tr3_parity_enable_extra_info_s { 161 soc_reg_t enable_reg; 162 soc_field_t *enable_field_list; 163 } _soc_tr3_parity_enable_extra_info_t; 164 165 typedef struct _soc_tr3_legacy_parity_info_s { 166 _soc_tr3_parity_info_type_t type; 167 struct _soc_tr3_legacy_parity_info_s *info; 168 int id; 169 soc_field_t group_reg_enable_field; 170 soc_field_t group_reg_status_field; 171 soc_mem_t mem; 172 char *mem_str; 173 soc_reg_t enable_reg; 174 soc_field_t enable_field; 175 soc_reg_t intr_status_reg; 176 _soc_tr3_parity_enable_extra_info_t *ext_en; 177 soc_reg_t correction_reg; 178 soc_field_t correction_addr_field; 179 } _soc_tr3_parity_info_t; 180 181 typedef struct _soc_tr3_parity_route_block_s { 182 uint8 cmic_reg; /* 0: intr2, 1: intr1 */ 183 uint32 cmic_bit; 184 soc_block_t blocktype; 185 soc_reg_t enable_reg; 186 soc_reg_t status_reg; 187 soc_field_t enable_field; 188 _soc_tr3_parity_info_t *info; 189 uint8 id; 190 } _soc_tr3_parity_route_block_t; 191 192 static 193 _soc_tr3_parity_info_t _soc_tr3_mmu_parity_info[] = { 194 { _SOC_PARITY_TYPE_GENERIC, NULL, 0, AGING_CTR_PAR_ERR_ENf, 195 AGING_CTR_PAR_ERRf, MMU_AGING_CTRm, "MMU AGING CTR", 196 INVALIDr, INVALIDf, INVALIDr, NULL, PERR_PTR_CTRr, PTRf }, 197 { _SOC_PARITY_TYPE_GENERIC, NULL, 0, AGING_EXP_PAR_ERR_ENf, 198 AGING_EXP_PAR_ERRf, MMU_AGING_EXPm, "MMU AGING EXP", 199 INVALIDr, INVALIDf, INVALIDr, NULL, PERR_PTR_EXPr, PTRf }, 200 { _SOC_PARITY_TYPE_GENERIC, NULL, 0, CCP_PAR_ERR_ENf, 201 CCP_PAR_ERRf, MMU_CCP_MEMm, "MMU CCP", INVALIDr, 202 INVALIDf, INVALIDr, NULL, INVALIDr, INVALIDf }, 203 { _SOC_PARITY_TYPE_GENERIC, NULL, 0, CFAP_PAR_ERR_ENf, 204 CFAP_PAR_ERRf, INVALIDm, "MMU CFAP", 205 INVALIDr, INVALIDf, INVALIDr, NULL, INVALIDr, INVALIDf }, 206 { _SOC_PARITY_TYPE_GENERIC, NULL, 0, CTR_UC_CNT_ENf, 207 CTR_UC_CNTf, MMU_CTR_UC_DROP_MEMm, "MMU CTR UC CNT", INVALIDr, 208 INVALIDf, INVALIDr, NULL, MMU_CTR_PARITY_ERRr, ERRADDRf }, 209 { _SOC_PARITY_TYPE_GENERIC, NULL, 0, CTR_MC_CNT_ENf, 210 CTR_MC_CNTf, MMU_CTR_MC_DROP_MEMm, "MMU CTR MC CNT", INVALIDr, 211 INVALIDf, INVALIDr, NULL, MMU_CTR_PARITY_ERRr, ERRADDRf }, 212 { _SOC_PARITY_TYPE_GENERIC, NULL, 0, CTR_COLOR_CNT_ERR_ENf, 213 CTR_COLOR_CNT_ERRf, MMU_CTR_COLOR_DROP_MEMm, "MMU CTR COLOR CNT", 214 INVALIDr, INVALIDf, INVALIDr, NULL, MMU_CTR_PARITY_ERRr, ERRADDRf }, 215 { _SOC_PARITY_TYPE_GENERIC, NULL, 0, TOQ_REPL_HEAD_TBL_PAR_ERR_ENf, 216 TOQ_REPL_HEAD_TBL_PAR_ERRf, MMU_REPL_HEAD_TBLm, "MMU TOQ REPL HEAD TBL", 217 INVALIDr, INVALIDf, INVALIDr, NULL, MCQ_REPLHEADERRPTRr, 218 REPLHEADERRORPOINTERf }, 219 { _SOC_PARITY_TYPE_GENERIC, NULL, 0, TOQ_MC_FIFO_PAR_ERR_ENf, 220 TOQ_MC_FIFO_PAR_ERRf, INVALIDm, "MMU TOQ MCFIFO", 221 INVALIDr, INVALIDf, INVALIDr, NULL, INVALIDr, INVALIDf }, 222 { _SOC_PARITY_TYPE_GENERIC, NULL, 0, TOQ_PKTLINK_PAR_ERR_ENf, 223 TOQ_PKTLINK_PAR_ERRf, INVALIDm, "MMU TOQ PKTLINK", 224 INVALIDr, INVALIDf, INVALIDr, NULL, INVALIDr, INVALIDf }, 225 { _SOC_PARITY_TYPE_GENERIC, NULL, 0, TOQ_CELLLINK_PAR_ERR_ENf, 226 TOQ_CELLLINK_PAR_ERRf, INVALIDm, "MMU TOQ CELLLINK", 227 INVALIDr, INVALIDf, INVALIDr, NULL, INVALIDr, INVALIDf }, 228 { _SOC_PARITY_TYPE_GENERIC, NULL, 0, TOQ_UC_QDB_PAR_ERR_ENf, 229 TOQ_UC_QDB_PAR_ERRf, INVALIDm, "MMU TOQ UC QDB", 230 INVALIDr, INVALIDf, INVALIDr, NULL, INVALIDr, INVALIDf }, 231 { _SOC_PARITY_TYPE_GENERIC, NULL, 0, TOQ_WAMULINK_PAR_ERR_ENf, 232 TOQ_WAMULINK_PAR_ERRf, INVALIDm, "MMU TOQ WAMULINK", 233 INVALIDr, INVALIDf, INVALIDr, NULL, INVALIDr, INVALIDf }, 234 { _SOC_PARITY_TYPE_GENERIC, NULL, 0, RDE_PAR_ERR_ENf, 235 RDE_PAR_ERRf, INVALIDm, "MMU RDE PAR", INVALIDr, INVALIDf, 236 INVALIDr, NULL, RDEPARITYERRORPTRr, PARITYERRORPTRf }, 237 { _SOC_PARITY_TYPE_GENERIC, NULL, 0, WAMU_PAR_ERR_ENf, 238 WAMU_PAR_ERRf, INVALIDm, "MMU WAMU PAR", 239 INVALIDr, INVALIDf, INVALIDr, NULL, INVALIDr, INVALIDf }, 240 { _SOC_PARITY_TYPE_MMU_MTRO, NULL, 0, MTRO_PAR_ERR_ENf, 241 MTRO_PAR_ERRf, INVALIDm, "MMU MTRO PAR", 242 INVALIDr, INVALIDf, INVALIDr, NULL, EGRSHAPEPARITYERRORPTRr, PTRf }, 243 { _SOC_PARITY_TYPE_MMU_WRED, NULL, 0, WRED_PAR_ERR_ENf, 244 WRED_PAR_ERRf, INVALIDm, "MMU WRED", 245 INVALIDr, INVALIDf, INVALIDr, NULL, WRED_PARITY_ERROR_INFOr, POINTERf }, 246 { _SOC_PARITY_TYPE_MMU_OVQ, NULL, 0, OVQ_PAR_ERR_ENf, 247 OVQ_PAR_ERRf, INVALIDm, "MMU OVQ", 248 INVALIDr, INVALIDf, INVALIDr, NULL, OVQ_ECC_BITMAPr, ECC_2B_ERR_ADDRESSf }, 249 { _SOC_PARITY_TYPE_GENERIC, NULL, 0, PQE_PAR_ERR_ENf, 250 PQE_PAR_ERRf, INVALIDm, "MMU PQE PAR", 251 INVALIDr, INVALIDf, INVALIDr, NULL, INVALIDr, INVALIDf }, 252 { _SOC_PARITY_TYPE_MMU_QCN, NULL, 0, QCN_PAR_ERR_ENf, 253 QCN_PAR_ERRf, INVALIDm, "MMU QCN PAR", 254 INVALIDr, INVALIDf, INVALIDr, NULL, MMU_QCN_PARITY_ERRr, ERRADDRf }, 255 { _SOC_PARITY_TYPE_MMU_THDO, NULL, 0, THDO_PAR_ERR_ENf, 256 THDO_PAR_ERRf, INVALIDm, "MMU THDO", 257 INVALIDr, INVALIDf, INVALIDr, NULL, INVALIDr, INVALIDf }, 258 { _SOC_PARITY_TYPE_MMU_THDI, NULL, 0, THDI_PAR_ERR_ENf, 259 THDI_PAR_ERRf, INVALIDm, "MMU THDI", 260 INVALIDr, INVALIDf, INVALIDr, NULL, INVALIDr, INVALIDf }, 261 { _SOC_PARITY_TYPE_MMU_LLS, NULL, 0, LLS_PAR_ERR_ENf, 262 LLS_PAR_ERRf, INVALIDm, "MMU LLS", 263 INVALIDr, INVALIDf, INVALIDr, NULL, INVALIDr, INVALIDf }, 264 { _SOC_PARITY_TYPE_GENERIC, NULL, 0, RDE_DESCP_PAR_ERR_ENf, 265 RDE_DESCP_PAR_ERRf, INVALIDm, "MMU RDE DESCP", INVALIDr, INVALIDf, 266 INVALIDr, NULL, DEQ_RDEDESCPERRPTRr, RDERRORPOINTERf }, 267 { _SOC_PARITY_TYPE_GENERIC, NULL, 0, E2EFC_PAR_ERR_ENf, 268 E2EFC_PAR_ERRf, INVALIDm, "MMU E2EFC", 269 INVALIDr, INVALIDf, INVALIDr, NULL, INVALIDr, INVALIDf }, 270 { _SOC_PARITY_TYPE_GENERIC, NULL, 0, DEQ_REPL_LIST_PAR_ERR_ENf, 271 DEQ_REPL_LIST_PAR_ERRf, MMU_REPL_LIST_TBLm, "MMU REPL LIST", 272 INVALIDr, INVALIDf, INVALIDr, NULL, DEQ_REPLISTERRPTRr, 273 REPLISTERRORPOINTERf }, 274 { _SOC_PARITY_TYPE_GENERIC, NULL, 0, INTFI_PAR_ERR_ENf, 275 INTFI_PAR_ERRf, INVALIDm, "MMU INTFI", 276 INVALIDr, INVALIDf, INVALIDr, NULL, INVALIDr, INVALIDf }, 277 { _SOC_PARITY_TYPE_GENERIC, NULL, 0, INTFO2_PAR_ERR_ENf, 278 INTFO2_PAR_ERRf, INVALIDm, "MMU INTFO2", 279 INVALIDr, INVALIDf, INVALIDr, NULL, INVALIDr, INVALIDf }, 280 { _SOC_PARITY_TYPE_GENERIC, NULL, 0, DEQ_SM_PAR_ERR_ENf, 281 DEQ_SM_PAR_ERRf, INVALIDm, "MMU DEQ SM", 282 INVALIDr, INVALIDf, INVALIDr, NULL, INVALIDr, INVALIDf }, 283 { _SOC_PARITY_TYPE_GENERIC, NULL, 0, HSP_PAR_ERR_ENf, 284 HSP_PAR_ERRf, INVALIDm, "MMU HSP", 285 INVALIDr, INVALIDf, INVALIDr, NULL, INVALIDr, INVALIDf }, 286 { _SOC_PARITY_TYPE_BST, NULL, 0, INVALIDf, 287 BST_THDI_INTf, INVALIDm, NULL, 288 INVALIDr, INVALIDf, INVALIDr, NULL, INVALIDr, INVALIDf }, 289 { _SOC_PARITY_TYPE_BST, NULL, 0, INVALIDf, 290 BST_THDO_INTf, INVALIDm, NULL, 291 INVALIDr, INVALIDf, INVALIDr, NULL, INVALIDr, INVALIDf }, 292 { _SOC_PARITY_TYPE_BST, NULL, 0, INVALIDf, 293 BST_CFAP_INTf, INVALIDm, NULL, 294 INVALIDr, INVALIDf, INVALIDr, NULL, INVALIDr, INVALIDf }, 295 { _SOC_PARITY_TYPE_NONE } /* table terminator */ 296 }; 297 298 static 299 _soc_tr3_parity_info_t _soc_tr3_port_parity_info[] = { 300 { _SOC_PARITY_TYPE_ECC, NULL, 0, TXFIFO0_MEM_ERRf, 301 TXFIFO0_MEM_ERRf, INVALIDm, "TX FIFO 0", PORT_ECC_CONTROLr, 302 TXFIFO_MEM_ENf, PORT_TXFIFO0_ECC_STATUSr, NULL, INVALIDr, INVALIDf }, 303 { _SOC_PARITY_TYPE_ECC, NULL, 0, TXFIFO1_MEM_ERRf, 304 TXFIFO1_MEM_ERRf, INVALIDm, "TX FIFO 1", PORT_ECC_CONTROLr, 305 TXFIFO_MEM_ENf, PORT_TXFIFO1_ECC_STATUSr, NULL, INVALIDr, INVALIDf }, 306 { _SOC_PARITY_TYPE_ECC, NULL, 0, TXFIFO2_MEM_ERRf, 307 TXFIFO2_MEM_ERRf, INVALIDm, "TX FIFO 2", PORT_ECC_CONTROLr, 308 TXFIFO_MEM_ENf, PORT_TXFIFO2_ECC_STATUSr, NULL, INVALIDr, INVALIDf }, 309 { _SOC_PARITY_TYPE_ECC, NULL, 0, CDC_TXFIFO_MEM_ERRf, CDC_TXFIFO_MEM_ERRf, 310 INVALIDm, "CDC TX FIFO", PORT_ECC_CONTROLr, CDC_TXFIFO_MEM_ENf, 311 PORT_CDC_TXFIFO_ECC_STATUSr, NULL, INVALIDr, INVALIDf }, 312 { _SOC_PARITY_TYPE_ECC, NULL, 0, CDC_RXFIFO_MEM_ERRf, CDC_RXFIFO_MEM_ERRf, 313 INVALIDm, "CDC RX FIFO", PORT_ECC_CONTROLr, CDC_RXFIFO_MEM_ENf, 314 PORT_CDC_RXFIFO_ECC_STATUSr, NULL, INVALIDr, INVALIDf }, 315 316 { _SOC_PARITY_TYPE_ECC, NULL, 0, EHG0_RX_MASK_MEM_ERRf, 317 EHG0_RX_MASK_MEM_ERRf, INVALIDm, "HG 0 RX MASK MEM", 318 PORT_EHG_ECC_CONTROLr, EHG_RX_MASK_MEM_ENf, 319 PORT_EHG0_RX_MASK_ECC_STATUSr, NULL, INVALIDr, INVALIDf }, 320 { _SOC_PARITY_TYPE_ECC, NULL, 0, EHG1_RX_MASK_MEM_ERRf, 321 EHG1_RX_MASK_MEM_ERRf, INVALIDm, "HG 1 RX MASK MEM", 322 PORT_EHG_ECC_CONTROLr, EHG_RX_MASK_MEM_ENf, 323 PORT_EHG1_RX_MASK_ECC_STATUSr, NULL, INVALIDr, INVALIDf }, 324 { _SOC_PARITY_TYPE_ECC, NULL, 0, EHG2_RX_MASK_MEM_ERRf, 325 EHG2_RX_MASK_MEM_ERRf, INVALIDm, "HG 2 RX MASK MEM", 326 PORT_EHG_ECC_CONTROLr, EHG_RX_MASK_MEM_ENf, 327 PORT_EHG2_RX_MASK_ECC_STATUSr, NULL, INVALIDr, INVALIDf }, 328 { _SOC_PARITY_TYPE_ECC, NULL, 0, EHG0_RX_DATA_MEM_ERRf, 329 EHG0_RX_DATA_MEM_ERRf, INVALIDm, "HG 0 RX DATA MEM", 330 PORT_EHG_ECC_CONTROLr, EHG_RX_DATA_MEM_ENf, 331 PORT_EHG0_RX_DATA_ECC_STATUSr, NULL, INVALIDr, INVALIDf }, 332 { _SOC_PARITY_TYPE_ECC, NULL, 0, EHG1_RX_DATA_MEM_ERRf, 333 EHG1_RX_DATA_MEM_ERRf, INVALIDm, "HG 1 RX DATA MEM", 334 PORT_EHG_ECC_CONTROLr, EHG_RX_DATA_MEM_ENf, 335 PORT_EHG1_RX_DATA_ECC_STATUSr, NULL, INVALIDr, INVALIDf }, 336 { _SOC_PARITY_TYPE_ECC, NULL, 0, EHG2_RX_DATA_MEM_ERRf, 337 EHG2_RX_DATA_MEM_ERRf, INVALIDm, "HG 2 RX DATA MEM", 338 PORT_EHG_ECC_CONTROLr, EHG_RX_DATA_MEM_ENf, 339 PORT_EHG2_RX_DATA_ECC_STATUSr, NULL, INVALIDr, INVALIDf }, 340 { _SOC_PARITY_TYPE_ECC, NULL, 0, EHG0_TX_DATA_MEM_ERRf, 341 EHG0_TX_DATA_MEM_ERRf, INVALIDm, "HG 0 TX DATA MEM", 342 PORT_EHG_ECC_CONTROLr, EHG_TX_DATA_MEM_ENf, 343 PORT_EHG0_TX_DATA_ECC_STATUSr, NULL, INVALIDr, INVALIDf }, 344 { _SOC_PARITY_TYPE_ECC, NULL, 0, EHG1_TX_DATA_MEM_ERRf, 345 EHG1_TX_DATA_MEM_ERRf, INVALIDm, "HG 1 TX DATA MEM", 346 PORT_EHG_ECC_CONTROLr, EHG_TX_DATA_MEM_ENf, 347 PORT_EHG1_TX_DATA_ECC_STATUSr, NULL, INVALIDr, INVALIDf }, 348 { _SOC_PARITY_TYPE_ECC, NULL, 0, EHG2_TX_DATA_MEM_ERRf, 349 EHG2_TX_DATA_MEM_ERRf, INVALIDm, "HG 2 TX DATA MEM", 350 PORT_EHG_ECC_CONTROLr, EHG_TX_DATA_MEM_ENf, 351 PORT_EHG2_TX_DATA_ECC_STATUSr, NULL, INVALIDr, INVALIDf }, 352 { _SOC_PARITY_TYPE_ECC, NULL, 0, EHG0_RXFIFO_MEM_ERRf, 353 EHG0_RXFIFO_MEM_ERRf, INVALIDm, "HG 0 RX FIFO MEM", 354 PORT_EHG_ECC_CONTROLr, EHG_RXFIFO_MEM_ENf, 355 PORT_EHG0_RXFIFO_ECC_STATUSr, NULL, INVALIDr, INVALIDf }, 356 { _SOC_PARITY_TYPE_ECC, NULL, 0, EHG1_RXFIFO_MEM_ERRf, 357 EHG1_RXFIFO_MEM_ERRf, INVALIDm, "HG 1 RX FIFO MEM", 358 PORT_EHG_ECC_CONTROLr, EHG_RXFIFO_MEM_ENf, 359 PORT_EHG1_RXFIFO_ECC_STATUSr, NULL, INVALIDr, INVALIDf }, 360 { _SOC_PARITY_TYPE_ECC, NULL, 0, EHG2_RXFIFO_MEM_ERRf, 361 EHG2_RXFIFO_MEM_ERRf, INVALIDm, "HG 2 RX FIFO MEM", 362 PORT_EHG_ECC_CONTROLr, EHG_RXFIFO_MEM_ENf, 363 PORT_EHG2_RXFIFO_ECC_STATUSr, NULL, INVALIDr, INVALIDf }, 364 { _SOC_PARITY_TYPE_NONE } /* table terminator */ 365 }; 366 367 static 368 _soc_tr3_parity_info_t _soc_tr3_axp_intb_parity_info[] = { 369 { _SOC_PARITY_TYPE_ECC, NULL, 0, MASKf, STATUSf, INVALIDm, "INT BUFF 1B", 370 AXP_CH_INBUF_ECC_CONTROLr, REPORT_1B_ERRf, INVALIDr, NULL, 371 INVALIDr, INVALIDf }, 372 { _SOC_PARITY_TYPE_ECC, NULL, 0, MASKf, STATUSf, INVALIDm, "INT BUFF", 373 AXP_CH_INBUF_ECC_CONTROLr, ENABLEf, AXP_CH_INBUF_ECC_STATUS_INTRr, NULL, 374 INVALIDr, INVALIDf }, 375 { _SOC_PARITY_TYPE_NONE } /* table terminator */ 376 }; 377 378 static 379 _soc_tr3_parity_info_t _soc_tr3_axp_wrx_parity_info[] = { 380 { _SOC_PARITY_TYPE_ECC, NULL, 0, SVP_PARITY_ERR_INTR_ENf, SVP_PARITY_ERRf, 381 AXP_WRX_SVP_ASSIGNMENTm, "WRX SVP", INVALIDr, INVALIDf, 382 AXP_WRX_SVP_PARITY_STATUS_INTRr, NULL, INVALIDr, INVALIDf }, 383 { _SOC_PARITY_TYPE_ECC, NULL, 0, WCD_PARITY_ERR_INTR_ENf, WCD_PARITY_ERRf, 384 AXP_WRX_WCDm, "WRX WCD", INVALIDr, INVALIDf, 385 AXP_WRX_WCD_PARITY_STATUS_INTRr, NULL, INVALIDr, INVALIDf }, 386 { _SOC_PARITY_TYPE_NONE } /* table terminator */ 387 }; 388 389 static 390 _soc_tr3_parity_info_t _soc_tr3_axp_wtx_parity_info[] = { 391 { _SOC_PARITY_TYPE_ECC, NULL, 0, DVP_PROFILEf, DVP_PROFILEf, 392 AXP_WTX_DVP_PROFILEm, "WTX DVP PROFILE", AXP_WTX_ERR_CHK_ENr, 393 DVP_PROFILE_ECC_ENf, AXP_WTX_DVP_PROFILE_ECC_STATUS_INTRr, NULL, 394 INVALIDr, INVALIDf }, 395 { _SOC_PARITY_TYPE_ECC, NULL, 0, TUNNELf, TUNNELf, 396 AXP_WTX_TUNNELm, "WTX TUNNEL", AXP_WTX_ERR_CHK_ENr, TUNNEL_ECC_ENf, 397 AXP_WTX_TUNNEL_ECC_STATUS_INTRr, NULL, INVALIDr, INVALIDf }, 398 { _SOC_PARITY_TYPE_ECC, NULL, 0, FRAG_IDf, FRAG_IDf, 399 AXP_WTX_FRAG_IDm, "WTX FRAG ID", AXP_WTX_ERR_CHK_ENr, FRAG_ID_PAR_ENf, 400 AXP_WTX_FRAG_ID_PAR_STATUS_INTRr, NULL, INVALIDr, INVALIDf }, 401 { _SOC_PARITY_TYPE_ECC, NULL, 0, PRI_MAPf, PRI_MAPf, 402 AXP_WTX_PRI_MAPm, "WTX PRI MAP", AXP_WTX_ERR_CHK_ENr, PRI_MAP_PAR_ENf, 403 AXP_WTX_PRI_MAP_PAR_STATUS_INTRr, NULL, INVALIDr, INVALIDf }, 404 { _SOC_PARITY_TYPE_ECC, NULL, 0, DSCP_MAPf, DSCP_MAPf, 405 AXP_WTX_DSCP_MAPm, "WTX DSCP MAP", AXP_WTX_ERR_CHK_ENr, DSCP_MAP_PAR_ENf, 406 AXP_WTX_DSCP_MAP_PAR_STATUS_INTRr, NULL, INVALIDr, INVALIDf }, 407 { _SOC_PARITY_TYPE_ECC, NULL, 0, TRUNK_BLOCK_MASKf, TRUNK_BLOCK_MASKf, 408 AXP_WTX_TRUNK_BLOCK_MASKm, "WTX TRUNK BLOCK", AXP_WTX_ERR_CHK_ENr, 409 TRUNK_BLOCK_MASK_PAR_ENf, AXP_WTX_TRUNK_BLOCK_MASK_PAR_STATUS_INTRr, 410 NULL, INVALIDr, INVALIDf }, 411 { _SOC_PARITY_TYPE_ECC, NULL, 0, TRUNK_GROUP_BITMAPf, TRUNK_GROUP_BITMAPf, 412 AXP_WTX_TRUNK_GROUP_BITMAPm, "WTX TRUNK GROUP", AXP_WTX_ERR_CHK_ENr, 413 TRUNK_GROUP_BITMAP_PAR_ENf, AXP_WTX_TRUNK_GROUP_BITMAP_PAR_STATUS_INTRr, 414 NULL, INVALIDr, INVALIDf }, 415 { _SOC_PARITY_TYPE_NONE } /* table terminator */ 416 }; 417 418 static 419 soc_field_t _soc_tr3_axp_sm_extended_enable_fields[] = { 420 DOUBLE_BIT_ERR_INTR_ENf, 421 MULTIPLE_ERR_INTR_ENf, 422 PARITY_ERR_INTR_ENf, 423 INVALIDf 424 }; 425 426 static 427 _soc_tr3_parity_enable_extra_info_t _soc_tr3_axp_sm_char_remap_extr_enable = { 428 AXP_SM_CHAR_REMAP_ECC_INTR_ENABLE_CONTROLr, 429 _soc_tr3_axp_sm_extended_enable_fields 430 }; 431 432 static 433 _soc_tr3_parity_enable_extra_info_t _soc_tr3_axp_sm_pkt_buff_extr_enable = { 434 AXP_SM_PACKET_BUFFER_ECC_INTR_ENABLE_CONTROLr, 435 _soc_tr3_axp_sm_extended_enable_fields 436 }; 437 438 static 439 _soc_tr3_parity_enable_extra_info_t _soc_tr3_axp_sm_flow_tbl_extr_enable = { 440 AXP_SM_FLOW_TABLE_ECC_INTR_ENABLE_CONTROLr, 441 _soc_tr3_axp_sm_extended_enable_fields 442 }; 443 444 static 445 _soc_tr3_parity_enable_extra_info_t _soc_tr3_axp_sm_match_ctr_extr_enable = { 446 AXP_SM_MATCH_COUNTER_ECC_INTR_ENABLE_CONTROLr, 447 _soc_tr3_axp_sm_extended_enable_fields 448 }; 449 450 static 451 _soc_tr3_parity_enable_extra_info_t _soc_tr3_axp_sm_match_tbl_extr_enable = { 452 AXP_SM_MATCH_TABLE_ECC_INTR_ENABLE_CONTROLr, 453 _soc_tr3_axp_sm_extended_enable_fields 454 }; 455 456 static 457 _soc_tr3_parity_enable_extra_info_t _soc_tr3_axp_sm_state_tbl_extr_enable = { 458 AXP_SM_STATE_TABLE_ECC_INTR_ENABLE_CONTROLr, 459 _soc_tr3_axp_sm_extended_enable_fields 460 }; 461 462 static 463 _soc_tr3_parity_info_t _soc_tr3_axp_sm_parity_info[] = { 464 { _SOC_PARITY_TYPE_ECC, NULL, 0, INVALIDf, INVALIDf, INVALIDm, 465 "CHAR REMAP", INVALIDr, INVALIDf, AXP_SM_CHAR_REMAP_ECC_INTR_STATUSr, 466 &_soc_tr3_axp_sm_char_remap_extr_enable, INVALIDr, INVALIDf }, 467 { _SOC_PARITY_TYPE_ECC, NULL, 0, INVALIDf, INVALIDf, 468 AXP_SM_PACKET_BUFFER_MEMm, "PACKET BUFFER", INVALIDr, INVALIDf, 469 AXP_SM_PACKET_BUFFER_ECC_INTR_STATUSr, 470 &_soc_tr3_axp_sm_pkt_buff_extr_enable, INVALIDr, INVALIDf }, 471 { _SOC_PARITY_TYPE_ECC, NULL, 0, INVALIDf, INVALIDf, INVALIDm, 472 "FLOW TABLE", INVALIDr, INVALIDf, AXP_SM_FLOW_TABLE_ECC_INTR_STATUSr, 473 &_soc_tr3_axp_sm_flow_tbl_extr_enable, INVALIDr, INVALIDf }, 474 { _SOC_PARITY_TYPE_ECC, NULL, 0, INVALIDf, INVALIDf, INVALIDm, 475 "MATCH COUNTER", INVALIDr, INVALIDf, 476 AXP_SM_MATCH_COUNTER_ECC_INTR_STATUSr, 477 &_soc_tr3_axp_sm_match_ctr_extr_enable, INVALIDr, INVALIDf }, 478 { _SOC_PARITY_TYPE_ECC, NULL, 0, INVALIDf, INVALIDf, INVALIDm, 479 "MATCH TABLE", INVALIDr, INVALIDf, AXP_SM_MATCH_TABLE_ECC_INTR_STATUSr, 480 &_soc_tr3_axp_sm_match_tbl_extr_enable, INVALIDr, INVALIDf }, 481 { _SOC_PARITY_TYPE_ECC, NULL, 0, INVALIDf, INVALIDf, INVALIDm, 482 "STATE TABLE", INVALIDr, INVALIDf, AXP_SM_STATE_TABLE_ECC_INTR_STATUSr, 483 &_soc_tr3_axp_sm_state_tbl_extr_enable, INVALIDr, INVALIDf }, 484 { _SOC_PARITY_TYPE_NONE } /* table terminator */ 485 }; 486 487 static 488 soc_field_t _soc_tr3_axp_sm_enable_fields[] = { 489 REMAP_TABLES_ECC_GEN_ENABLEf, 490 PACKET_BUFFER_ECC_GEN_ENABLEf, 491 FLOW_TABLE_ECC_GEN_ENABLEf, 492 MATCH_COUNTER3_ECC_GEN_ENABLEf, 493 MATCH_COUNTER2_ECC_GEN_ENABLEf, 494 MATCH_COUNTER1_ECC_GEN_ENABLEf, 495 MATCH_COUNTER0_ECC_GEN_ENABLEf, 496 MATCH_TABLE3_ECC_GEN_ENABLEf, 497 MATCH_TABLE2_ECC_GEN_ENABLEf, 498 MATCH_TABLE1_ECC_GEN_ENABLEf, 499 MATCH_TABLE0_ECC_GEN_ENABLEf, 500 STATE_TABLE7_ECC_GEN_ENABLEf, 501 STATE_TABLE6_ECC_GEN_ENABLEf, 502 STATE_TABLE5_ECC_GEN_ENABLEf, 503 STATE_TABLE4_ECC_GEN_ENABLEf, 504 STATE_TABLE3_ECC_GEN_ENABLEf, 505 STATE_TABLE2_ECC_GEN_ENABLEf, 506 STATE_TABLE1_ECC_GEN_ENABLEf, 507 STATE_TABLE0_ECC_GEN_ENABLEf, 508 INVALIDf 509 }; 510 511 static 512 _soc_tr3_parity_enable_extra_info_t _soc_tr3_axp_sm_extra_enable = { 513 AXP_SM_MEM_ECC_GEN_CONTROLr, 514 _soc_tr3_axp_sm_enable_fields 515 }; 516 517 static 518 _soc_tr3_parity_info_t _soc_tr3_axp_parity_info[] = { 519 { _SOC_PARITY_TYPE_AXP, _soc_tr3_axp_intb_parity_info, 0, 520 AXP_INT_BUF_MASKf, AXP_INT_BUF_STATUSf, INVALIDm, "AXP INT BUFF", 521 AXP_CH_LCL_INT_MASKr, INVALIDf, AXP_CH_LCL_INT_STATUSr, NULL, 522 INVALIDr, INVALIDf }, 523 { _SOC_PARITY_TYPE_AXP, _soc_tr3_axp_wrx_parity_info, 0, 524 AXP_WRX_MASKf, AXP_WRX_STATUSf, INVALIDm, "AXP WRX", 525 AXP_WRX_INTR_ENABLEr, INVALIDf, AXP_WRX_INTR_STATUSr, NULL, 526 INVALIDr, INVALIDf }, 527 { _SOC_PARITY_TYPE_AXP, _soc_tr3_axp_wtx_parity_info, 0, 528 AXP_WTX_MASKf, AXP_WTX_STATUSf, INVALIDm, "AXP WTX", 529 AXP_WTX_INT_MASKr, INVALIDf, AXP_WTX_INT_STATUSr, NULL, 530 INVALIDr, INVALIDf }, 531 { _SOC_PARITY_TYPE_AXP, _soc_tr3_axp_sm_parity_info, 0, 532 AXP_SM_MASKf, AXP_SM_STATUSf, INVALIDm, "AXP SM", 533 INVALIDr, INVALIDf, INVALIDr, &_soc_tr3_axp_sm_extra_enable, 534 INVALIDr, INVALIDf }, 535 { _SOC_PARITY_TYPE_NONE } /* table terminator */ 536 }; 537 538 static 539 _soc_tr3_parity_info_t _soc_tr3_ibod_parity_info[] = { 540 { _SOC_PARITY_TYPE_ECC, NULL, 0, CL1_DATA_FIFO_PERR_INTR_MASKf, 541 CL1_DATA_FIFO_PERR_INTR_STATUSf, INVALIDm, "CL1 DATA FIFO", 542 INVALIDr, INVALIDf, IBOD_CL1_FIFO_ECC_STATUS_INTRr, NULL, 543 INVALIDr, INVALIDf }, 544 { _SOC_PARITY_TYPE_ECC, NULL, 1, CL1_CTRL_FIFO_PERR_INTR_MASKf, 545 CL1_CTRL_FIFO_PERR_INTR_STATUSf, INVALIDm, "CL1 CTRL FIFO", 546 INVALIDr, INVALIDf, IBOD_CL1_FIFO_ECC_STATUS_INTRr, NULL, 547 INVALIDr, INVALIDf }, 548 { _SOC_PARITY_TYPE_ECC, NULL, 0, CL0_DATA_FIFO_PERR_INTR_MASKf, 549 CL0_DATA_FIFO_PERR_INTR_STATUSf, INVALIDm, "CL0 DATA FIFO", 550 INVALIDr, INVALIDf, IBOD_CL0_FIFO_ECC_STATUS_INTRr, NULL, 551 INVALIDr, INVALIDf }, 552 { _SOC_PARITY_TYPE_ECC, NULL, 1, CL0_CTRL_FIFO_PERR_INTR_MASKf, 553 CL0_CTRL_FIFO_PERR_INTR_STATUSf, INVALIDm, "CL0 CTRL FIFO", 554 INVALIDr, INVALIDf, IBOD_CL0_FIFO_ECC_STATUS_INTRr, NULL, 555 INVALIDr, INVALIDf }, 556 { _SOC_PARITY_TYPE_ECC, NULL, 0, XL1_DATA_FIFO_PERR_INTR_MASKf, 557 XL1_DATA_FIFO_PERR_INTR_STATUSf, INVALIDm, "XL1 DATA FIFO", 558 INVALIDr, INVALIDf, IBOD_XL1_FIFO_ECC_STATUS_INTRr, NULL, 559 INVALIDr, INVALIDf }, 560 { _SOC_PARITY_TYPE_ECC, NULL, 1, XL1_CTRL_FIFO_PERR_INTR_MASKf, 561 XL1_CTRL_FIFO_PERR_INTR_STATUSf, INVALIDm, "XL1 CTRL FIFO", 562 INVALIDr, INVALIDf, IBOD_XL1_FIFO_ECC_STATUS_INTRr, NULL, 563 INVALIDr, INVALIDf }, 564 { _SOC_PARITY_TYPE_ECC, NULL, 0, XL0_DATA_FIFO_PERR_INTR_MASKf, 565 XL0_DATA_FIFO_PERR_INTR_STATUSf, INVALIDm, "XL0 DATA FIFO", 566 INVALIDr, INVALIDf, IBOD_XL0_FIFO_ECC_STATUS_INTRr, NULL, 567 INVALIDr, INVALIDf }, 568 { _SOC_PARITY_TYPE_ECC, NULL, 1, XL0_CTRL_FIFO_PERR_INTR_MASKf, 569 XL0_CTRL_FIFO_PERR_INTR_STATUSf, INVALIDm, "XL0 CTRL FIFO", 570 INVALIDr, INVALIDf, IBOD_XL0_FIFO_ECC_STATUS_INTRr, NULL, 571 INVALIDr, INVALIDf }, 572 { _SOC_PARITY_TYPE_ECC, NULL, 0, XT3_DATA_FIFO_PERR_INTR_MASKf, 573 XT3_DATA_FIFO_PERR_INTR_STATUSf, INVALIDm, "XT3 DATA FIFO", 574 INVALIDr, INVALIDf, IBOD_XT3_FIFO_ECC_STATUS_INTRr, NULL, 575 INVALIDr, INVALIDf }, 576 { _SOC_PARITY_TYPE_ECC, NULL, 1, XT3_CTRL_FIFO_PERR_INTR_MASKf, 577 XT3_CTRL_FIFO_PERR_INTR_STATUSf, INVALIDm, "XT3 CTRL FIFO", 578 INVALIDr, INVALIDf, IBOD_XT3_FIFO_ECC_STATUS_INTRr, NULL, 579 INVALIDr, INVALIDf }, 580 { _SOC_PARITY_TYPE_ECC, NULL, 0, XT2_DATA_FIFO_PERR_INTR_MASKf, 581 XT2_DATA_FIFO_PERR_INTR_STATUSf, INVALIDm, "XT2 DATA FIFO", 582 INVALIDr, INVALIDf, IBOD_XT2_FIFO_ECC_STATUS_INTRr, NULL, 583 INVALIDr, INVALIDf }, 584 { _SOC_PARITY_TYPE_ECC, NULL, 1, XT2_CTRL_FIFO_PERR_INTR_MASKf, 585 XT2_CTRL_FIFO_PERR_INTR_STATUSf, INVALIDm, "XT2 CTRL FIFO", 586 INVALIDr, INVALIDf, IBOD_XT2_FIFO_ECC_STATUS_INTRr, NULL, 587 INVALIDr, INVALIDf }, 588 { _SOC_PARITY_TYPE_ECC, NULL, 0, XT1_DATA_FIFO_PERR_INTR_MASKf, 589 XT1_DATA_FIFO_PERR_INTR_STATUSf, INVALIDm, "XT1 DATA FIFO", 590 INVALIDr, INVALIDf, IBOD_XT1_FIFO_ECC_STATUS_INTRr, NULL, 591 INVALIDr, INVALIDf }, 592 { _SOC_PARITY_TYPE_ECC, NULL, 1, XT1_CTRL_FIFO_PERR_INTR_MASKf, 593 XT1_CTRL_FIFO_PERR_INTR_STATUSf, INVALIDm, "XT1 CTRL FIFO", 594 INVALIDr, INVALIDf, IBOD_XT1_FIFO_ECC_STATUS_INTRr, NULL, 595 INVALIDr, INVALIDf }, 596 { _SOC_PARITY_TYPE_ECC, NULL, 0, XT0_DATA_FIFO_PERR_INTR_MASKf, 597 XT0_DATA_FIFO_PERR_INTR_STATUSf, INVALIDm, "XT0 DATA FIFO", 598 INVALIDr, INVALIDf, IBOD_XT0_FIFO_ECC_STATUS_INTRr, NULL, 599 INVALIDr, INVALIDf }, 600 { _SOC_PARITY_TYPE_ECC, NULL, 1, XT0_CTRL_FIFO_PERR_INTR_MASKf, 601 XT0_CTRL_FIFO_PERR_INTR_STATUSf, INVALIDm, "XT0 CTRL FIFO", 602 INVALIDr, INVALIDf, IBOD_XT0_FIFO_ECC_STATUS_INTRr, NULL, 603 INVALIDr, INVALIDf }, 604 { _SOC_PARITY_TYPE_NONE } /* table terminator */ 605 }; 606 607 static 608 _soc_tr3_parity_info_t _soc_hx4_ibod_parity_info[] = { 609 { _SOC_PARITY_TYPE_ECC, NULL, 0, CL1_DATA_FIFO_PERR_INTR_MASKf, 610 CL1_DATA_FIFO_PERR_INTR_STATUSf, INVALIDm, "CL1 DATA FIFO", 611 INVALIDr, INVALIDf, IBOD_CL1_FIFO_ECC_STATUS_INTRr, NULL, 612 INVALIDr, INVALIDf }, 613 { _SOC_PARITY_TYPE_ECC, NULL, 1, CL1_CTRL_FIFO_PERR_INTR_MASKf, 614 CL1_CTRL_FIFO_PERR_INTR_STATUSf, INVALIDm, "CL1 CTRL FIFO", 615 INVALIDr, INVALIDf, IBOD_CL1_FIFO_ECC_STATUS_INTRr, NULL, 616 INVALIDr, INVALIDf }, 617 { _SOC_PARITY_TYPE_ECC, NULL, 0, CL0_DATA_FIFO_PERR_INTR_MASKf, 618 CL0_DATA_FIFO_PERR_INTR_STATUSf, INVALIDm, "CL0 DATA FIFO", 619 INVALIDr, INVALIDf, IBOD_CL0_FIFO_ECC_STATUS_INTRr, NULL, 620 INVALIDr, INVALIDf }, 621 { _SOC_PARITY_TYPE_ECC, NULL, 1, CL0_CTRL_FIFO_PERR_INTR_MASKf, 622 CL0_CTRL_FIFO_PERR_INTR_STATUSf, INVALIDm, "CL0 CTRL FIFO", 623 INVALIDr, INVALIDf, IBOD_CL0_FIFO_ECC_STATUS_INTRr, NULL, 624 INVALIDr, INVALIDf }, 625 { _SOC_PARITY_TYPE_ECC, NULL, 0, CL2_DATA_FIFO_PERR_INTR_MASKf, 626 CL2_DATA_FIFO_PERR_INTR_STATUSf, INVALIDm, "CL2 DATA FIFO", 627 INVALIDr, INVALIDf, IBOD_CL2_FIFO_ECC_STATUS_INTRr, NULL, 628 INVALIDr, INVALIDf }, 629 { _SOC_PARITY_TYPE_ECC, NULL, 1, CL2_CTRL_FIFO_PERR_INTR_MASKf, 630 CL2_CTRL_FIFO_PERR_INTR_STATUSf, INVALIDm, "CL2 CTRL FIFO", 631 INVALIDr, INVALIDf, IBOD_CL2_FIFO_ECC_STATUS_INTRr, NULL, 632 INVALIDr, INVALIDf }, 633 { _SOC_PARITY_TYPE_ECC, NULL, 0, XL0_DATA_FIFO_PERR_INTR_MASKf, 634 XL0_DATA_FIFO_PERR_INTR_STATUSf, INVALIDm, "XL0 DATA FIFO", 635 INVALIDr, INVALIDf, IBOD_XL0_FIFO_ECC_STATUS_INTRr, NULL, 636 INVALIDr, INVALIDf }, 637 { _SOC_PARITY_TYPE_ECC, NULL, 1, XL0_CTRL_FIFO_PERR_INTR_MASKf, 638 XL0_CTRL_FIFO_PERR_INTR_STATUSf, INVALIDm, "XL0 CTRL FIFO", 639 INVALIDr, INVALIDf, IBOD_XL0_FIFO_ECC_STATUS_INTRr, NULL, 640 INVALIDr, INVALIDf }, 641 { _SOC_PARITY_TYPE_ECC, NULL, 0, XT3_DATA_FIFO_PERR_INTR_MASKf, 642 XT3_DATA_FIFO_PERR_INTR_STATUSf, INVALIDm, "XT3 DATA FIFO", 643 INVALIDr, INVALIDf, IBOD_XT3_FIFO_ECC_STATUS_INTRr, NULL, 644 INVALIDr, INVALIDf }, 645 { _SOC_PARITY_TYPE_ECC, NULL, 1, XT3_CTRL_FIFO_PERR_INTR_MASKf, 646 XT3_CTRL_FIFO_PERR_INTR_STATUSf, INVALIDm, "XT3 CTRL FIFO", 647 INVALIDr, INVALIDf, IBOD_XT3_FIFO_ECC_STATUS_INTRr, NULL, 648 INVALIDr, INVALIDf }, 649 { _SOC_PARITY_TYPE_ECC, NULL, 0, XT2_DATA_FIFO_PERR_INTR_MASKf, 650 XT2_DATA_FIFO_PERR_INTR_STATUSf, INVALIDm, "XT2 DATA FIFO", 651 INVALIDr, INVALIDf, IBOD_XT2_FIFO_ECC_STATUS_INTRr, NULL, 652 INVALIDr, INVALIDf }, 653 { _SOC_PARITY_TYPE_ECC, NULL, 1, XT2_CTRL_FIFO_PERR_INTR_MASKf, 654 XT2_CTRL_FIFO_PERR_INTR_STATUSf, INVALIDm, "XT2 CTRL FIFO", 655 INVALIDr, INVALIDf, IBOD_XT2_FIFO_ECC_STATUS_INTRr, NULL, 656 INVALIDr, INVALIDf }, 657 { _SOC_PARITY_TYPE_ECC, NULL, 0, XT1_DATA_FIFO_PERR_INTR_MASKf, 658 XT1_DATA_FIFO_PERR_INTR_STATUSf, INVALIDm, "XT1 DATA FIFO", 659 INVALIDr, INVALIDf, IBOD_XT1_FIFO_ECC_STATUS_INTRr, NULL, 660 INVALIDr, INVALIDf }, 661 { _SOC_PARITY_TYPE_ECC, NULL, 1, XT1_CTRL_FIFO_PERR_INTR_MASKf, 662 XT1_CTRL_FIFO_PERR_INTR_STATUSf, INVALIDm, "XT1 CTRL FIFO", 663 INVALIDr, INVALIDf, IBOD_XT1_FIFO_ECC_STATUS_INTRr, NULL, 664 INVALIDr, INVALIDf }, 665 { _SOC_PARITY_TYPE_ECC, NULL, 0, XT0_DATA_FIFO_PERR_INTR_MASKf, 666 XT0_DATA_FIFO_PERR_INTR_STATUSf, INVALIDm, "XT0 DATA FIFO", 667 INVALIDr, INVALIDf, IBOD_XT0_FIFO_ECC_STATUS_INTRr, NULL, 668 INVALIDr, INVALIDf }, 669 { _SOC_PARITY_TYPE_ECC, NULL, 1, XT0_CTRL_FIFO_PERR_INTR_MASKf, 670 XT0_CTRL_FIFO_PERR_INTR_STATUSf, INVALIDm, "XT0 CTRL FIFO", 671 INVALIDr, INVALIDf, IBOD_XT0_FIFO_ECC_STATUS_INTRr, NULL, 672 INVALIDr, INVALIDf }, 673 { _SOC_PARITY_TYPE_NONE } /* table terminator */ 674 }; 675 676 static 677 _soc_tr3_fifo_parity_info_t _soc_tr3_ip_parity_info[] = { 678 { ISW2_SER_CONTROL_1r, IP_COUNTERS_PARITY_ENf }, 679 { ISW2_SER_CONTROL_1r, RDBGC_MEM_INST0_PARITY_ENf }, 680 { ISW2_SER_CONTROL_1r, HG_COUNTERS_PARITY_ENf }, 681 { ISW2_SER_CONTROL_1r, RDBGC_MEM_INST2_PARITY_ENf }, 682 { ISW2_SER_CONTROL_1r, ING_TRILL_RX_PKTS_PARITY_ENf }, 683 { ISW2_SER_CONTROL_1r, ING_TRILL_RX_ACCESS_PORT_TRILL_PKTS_DISCARDED_PARITY_ENf }, 684 { ISW2_SER_CONTROL_1r, ING_TRILL_RX_NETWORK_PORT_NON_TRILL_PKTS_DISCARDED_PARITY_ENf }, 685 { ISW2_SER_CONTROL_1r, ING_NIV_RX_FRAMES_ERROR_DROP_PARITY_ENf }, 686 { ISW2_SER_CONTROL_1r, ING_NIV_RX_FRAMES_FORWARDING_DROP_PARITY_ENf }, 687 { ISW2_SER_CONTROL_1r, ING_NIV_RX_FRAMES_VLAN_TAGGED_PARITY_ENf }, 688 /* { ISW2_SER_CONTROL_1r, SW2_EOP_BUFFER_A_PARITY_ENf }, 689 { ISW2_SER_CONTROL_1r, SW2_EOP_BUFFER_B_PARITY_ENf }, 690 { ISW2_SER_CONTROL_1r, SW2_EOP_BUFFER_C_PARITY_ENf },*/ 691 { IARB_SER_CONTROLr, LMEP_PARITY_ENf }, 692 { IARB_SER_CONTROLr, LMEP_DA_PARITY_ENf }, 693 { IARB_SER_CONTROLr, CMIC_BUF_ECC_ENf }, 694 { IARB_SER_CONTROLr, AXP_BUF_ECC_ENf }, 695 { IARB_SER_CONTROLr, CPU_BUF_ECC_ENf }, 696 { ICFG_SER_CONTROLr, PORT_TABLE_ECC_ENf }, 697 { ICFG_SER_CONTROLr, SYSTEM_CONFIG_MODVIEW_PARITY_ENf }, 698 { ICFG_SER_CONTROLr, SYSTEM_CONFIG_PARITY_PARITY_ENf }, 699 { ICFG_SER_CONTROLr, SOURCE_TRUNK_MAP_MODVIEW_PARITY_ENf }, 700 { IPARS_SER_CONTROLr, SRC_TRUNK_ECC_ENf }, 701 { IPARS_SER_CONTROLr, L3_TUNNEL_PARITY_ENf }, 702 { IPARS_SER_CONTROLr, FP_UDF_PARITY_ENf }, 703 { IPARS_SER_CONTROLr, MOD_MAP_PARITY_ENf }, 704 { IPARS_SER_CONTROLr, LPORT_TABLE_ECC_ENf }, 705 { IPARS_SER_CONTROLr, VLAN_RANGE_PARITY_ENf }, 706 { IPARS_SER_CONTROLr, CPU_TS_PARITY_ENf }, 707 { IPARS_SER_CONTROLr, SOURCE_VP_ATTRIBUTES_2_PARITY_ENf }, 708 { IPARS_SER_CONTROLr, PTP_LABEL_RANGE_PROFILE_TABLE_PARITY_ENf }, 709 710 { IVXLT_SER_CONTROLr, VLAN_PROT_PARITY_ENf }, 711 { IVXLT_SER_CONTROLr, VLAN_SUBNET_PARITY_ENf }, 712 { IVXLT_SER_CONTROLr, VFP_POLICY_PARITY_ENf }, 713 714 { IMPLS_SER_CONTROLr, MY_STATION_DATA_PARITY_ENf }, 715 { IMPLS_SER_CONTROLr, VRF_PARITY_ENf }, 716 { IMPLS_SER_CONTROLr, VFI_1_PARITY_ENf }, 717 { IMPLS_SER_CONTROLr, VFI_PARITY_ENf }, 718 { IMPLS_SER_CONTROLr, VLAN_MPLS_PARITY_ENf }, 719 { IMPLS_SER_CONTROLr, L3_IIF_PARITY_ENf }, 720 { IMPLS_SER_CONTROLr, SOURCE_VP_PARITY_ENf }, 721 722 { IVLAN_SER_CONTROLr, VLAN_PARITY_ENf }, 723 { IVLAN_SER_CONTROLr, VLAN_STG_PARITY_ENf }, 724 { IL2LU_SER_CONTROLr, L2_USER_ENTRY_DATA_PARITY_ENf }, 725 { ILPM_SER_CONTROLr, L3_DEFIP_DATA_PARITY_ENf }, 726 { ILPM_SER_CONTROLr, RTAG7_FLOW_BASED_HASH_PARITY_ENf }, 727 { IESMIF_PARITY_CONTROLr, L3_PROTOCOL_FN_PARITY_ENf }, 728 { IESMIF_PARITY_CONTROLr, KEY_ID_TO_FIELD_MAPPER_PARITY_ENf }, 729 { IESMIF_PARITY_CONTROLr, SEARCH_PROFILE_PARITY_ENf }, 730 { IESMIF_PARITY_CONTROLr, PKT_TYPE_ID_PARITY_ENf }, 731 732 { IRSEL1_SER_CONTROLr, INITIAL_L3_ECMP_GROUP_PARITY_ENf }, 733 { IRSEL1_SER_CONTROLr, INITIAL_L3_ECMP_PARITY_ENf }, 734 { IRSEL1_SER_CONTROLr, ING_DVP_TABLE_PARITY_ENf }, 735 { IRSEL1_SER_CONTROLr, INITIAL_PROT_NHI_TABLE_PARITY_ENf }, 736 { IRSEL1_SER_CONTROLr, INITIAL_ING_L3_NEXT_HOP_PARITY_ENf }, 737 { IRSEL1_SER_CONTROLr, L3_IPMC_1_PARITY_ENf }, 738 { IRSEL1_SER_CONTROLr, MA_INDEX_PARITY_ENf }, 739 { IRSEL1_SER_CONTROLr, MAID_REDUCTION_PARITY_ENf }, 740 { IRSEL1_SER_CONTROLr, RMEP_PARITY_ENf }, 741 { IRSEL1_SER_CONTROLr, MA_STATE_PARITY_ENf }, 742 { IRSEL1_SER_CONTROLr, PORT_CBL_TABLE_MODBASE_PARITY_ENf }, 743 { IRSEL1_SER_CONTROLr, PORT_CBL_TABLE_PARITY_ENf }, 744 { IRSEL1_SER_CONTROLr, OAM_OPCODE_CONTROL_PROFILE_PARITY_ENf }, 745 { IRSEL1_SER_CONTROLr, ESM_ACL_ACTION_TABLE_PARITY_ENf }, 746 { IRSEL1_SER_CONTROLr, ESM_ACL_PROFILE_TABLE_PARITY_ENf }, 747 748 { ISW1_SER_CONTROLr, DSCP_TABLE_PARITY_ENf }, 749 { ISW1_SER_CONTROLr, ING_PRI_CNG_MAP_PARITY_ENf }, 750 { ISW1_SER_CONTROLr, FP_PORT_FIELD_SEL_PARITY_ENf }, 751 { ISW1_SER_CONTROLr, TTL_FN_PARITY_ENf }, 752 { ISW1_SER_CONTROLr, TOS_FN_PARITY_ENf }, 753 { ISW1_SER_CONTROLr, ING_UNTAGGED_PHB_PARITY_ENf }, 754 755 { IFP_PARITY_CONTROLr, POLICY_PARITY_ENf }, 756 { IFP_PARITY_CONTROLr, METER_PARITY_ENf }, 757 { IFP_PARITY_CONTROLr, COUNTER_PARITY_ENf }, 758 { IFP_PARITY_CONTROLr, ING_DVP_2_PARITY_ENf }, 759 { IFP_PARITY_CONTROLr, STORM_PARITY_ENf }, 760 { IFP_PARITY_CONTROLr, COUNTER_MUX_DATA_STAGING_PARITY_ENf }, 761 { IRSEL2_SER_CONTROLr, ING_L3_NEXT_HOP_PARITY_ENf }, 762 { IRSEL2_SER_CONTROLr, L3_ECMP_PARITY_ENf }, 763 { IRSEL2_SER_CONTROLr, L3_IPMC_REMAP_PARITY_ENf }, 764 { IRSEL2_SER_CONTROLr, L3_IPMC_PARITY_ENf }, 765 { IRSEL2_SER_CONTROLr, L3_ECMP_GROUP_PARITY_ENf }, 766 { IRSEL2_SER_CONTROLr, IFP_REDIRECTION_PROFILE_PARITY_ENf }, 767 { IRSEL2_SER_CONTROLr, L2MC_PARITY_ENf }, 768 { IRSEL2_SER_CONTROLr, TRUNK_GROUP_PARITY_ENf }, 769 { IRSEL2_SER_CONTROLr, ICONTROL_OPCODE_BITMAP_PARITY_ENf }, 770 { IRSEL2_SER_CONTROLr, EGR_MASK_MODBASE_PARITY_ENf }, 771 { IRSEL2_SER_CONTROLr, TRUNK_MEMBER_PARITY_ENf }, 772 { IRSEL2_SER_CONTROLr, DEST_TRUNK_BITMAP_PARITY_ENf }, 773 774 { ING_IPFIX_SER_CONTROLr, SESSION_TBLf }, 775 { ING_IPFIX_SER_CONTROLr, EXPORT_FIFOf }, 776 { ING_IPFIX_SER_CONTROLr, EOP_TBLf }, 777 { ING_IPFIX_SER_CONTROLr, FLOW_TBLf }, 778 { DLB_ECMP_SER_CONTROLr, DLB_ECMP_FLOWSET_PARITY_ENf }, 779 { DLB_ECMP_SER_CONTROLr, DLB_ECMP_FLOWSET_TIMESTAMP_PAGE_PARITY_ENf }, 780 { DLB_LAG_SER_CONTROLr, DLB_LAG_FLOWSET_PARITY_ENf }, 781 { DLB_LAG_SER_CONTROLr, DLB_LAG_FLOWSET_TIMESTAMP_PAGE_PARITY_ENf }, 782 { FT_SER_CONTROLr, SESSION_TBLf }, 783 { FT_SER_CONTROLr, EXP_TBLf }, 784 { FT_SER_CONTROLr, EOP_TBLf }, 785 { FT_SER_CONTROLr, LAG_TBLf }, 786 { ISW2_SER_CONTROL_0r, ING_L3_NEXT_HOP_ATTRIBUTE_1_INDEX_PARITY_ENf }, 787 { ISW2_SER_CONTROL_0r, EGR_MASK_PARITY_ENf }, 788 { ISW2_SER_CONTROL_0r, ING_PW_TERM_SEQ_NUM_PARITY_ENf }, 789 { ISW2_SER_CONTROL_0r, MODPORT_MAP_SW_PARITY_ENf }, 790 { ISW2_SER_CONTROL_0r, MODPORT_MAP_MIRROR_PARITY_ENf }, 791 { ISW2_SER_CONTROL_0r, SRC_MODID_EGRESS_PARITY_ENf }, 792 { ISW2_SER_CONTROL_0r, TRUNK_BITMAP_TABLE_PARITY_ENf }, 793 { ISW2_SER_CONTROL_0r, MAC_BLOCK_TABLE_PARITY_ENf }, 794 { ISW2_SER_CONTROL_0r, NONUCAST_TRUNK_BLOCK_MASK_PARITY_ENf }, 795 { ISW2_SER_CONTROL_0r, E2E_HOL_STATUS_PARITY_ENf }, 796 { ISW2_SER_CONTROL_0r, E2E_HOL_STATUS_1_PARITY_ENf }, 797 { ISW2_SER_CONTROL_0r, SRC_MODID_INGRESS_BLOCK_PARITY_ENf }, 798 { ISW2_SER_CONTROL_0r, ALTERNATE_EMIRROR_BITMAP_PARITY_ENf }, 799 { ISW2_SER_CONTROL_0r, PORT_LAG_FAILOVER_SET_PARITY_ENf }, 800 { ISW2_SER_CONTROL_0r, VLAN_PROFILE_2_PARITY_ENf }, 801 { ISW2_SER_CONTROL_0r, UNKNOWN_UCAST_BLOCK_MASK_PARITY_ENf }, 802 { ISW2_SER_CONTROL_0r, UNKNOWN_MCAST_BLOCK_MASK_PARITY_ENf }, 803 { ISW2_SER_CONTROL_0r, BCAST_BLOCK_MASK_PARITY_ENf }, 804 { ISW2_SER_CONTROL_0r, ING_EGRMSKBMAP_PARITY_ENf }, 805 { ISW2_SER_CONTROL_0r, LOCAL_SW_DISABLE_DEFAULT_PBM_PARITY_ENf }, 806 { ISW2_SER_CONTROL_0r, KNOWN_MCAST_BLOCK_MASK_PARITY_ENf }, 807 { ISW2_SER_CONTROL_0r, LOCAL_SW_DISABLE_DEFAULT_PBM_MIRR_PARITY_ENf }, 808 { ISW2_SER_CONTROL_0r, IMIRROR_BITMAP_PARITY_ENf }, 809 { ISW2_SER_CONTROL_0r, UNKNOWN_HGI_BITMAP_PARITY_ENf }, 810 { ISW2_SER_CONTROL_0r, ING_HIGIG_TRUNK_OVERRIDE_PROFILE_PARITY_ENf }, 811 { ISW2_SER_CONTROL_0r, NUM_QCN_CNM_RECEIVED_PARITY_ENf }, 812 { ISW2_SER_CONTROL_0r, OAM_LM_COUNTERS_PARITY_ENf }, 813 { ISW2_SER_CONTROL_0r, AXP_WLAN_COS_MAP_PARITY_ENf }, 814 { ISW2_SER_CONTROL_0r, ING_L3_NEXT_HOP_ATTRIBUTE_1_PARITY_ENf }, 815 { ISW2_SER_CONTROL_0r, VOQ_MOD_MAP_PARITY_ENf }, 816 { ISW2_SER_CONTROL_1r, EMIRROR_CONTROL_PARITY_ENf }, 817 { ISW2_SER_CONTROL_1r, EMIRROR_CONTROL1_PARITY_ENf }, 818 { ISW2_SER_CONTROL_1r, EMIRROR_CONTROL2_PARITY_ENf }, 819 { ISW2_SER_CONTROL_1r, EMIRROR_CONTROL3_PARITY_ENf }, 820 { ISW2_SER_CONTROL_1r, VOQ_PORT_MAP_PARITY_ENf }, 821 { ISW2_SER_CONTROL_1r, SERVICE_QUEUE_MAP_PARITY_ENf }, 822 { ISW2_SER_CONTROL_1r, SERVICE_PORT_MAP_PARITY_ENf }, 823 { ING_FLEX_CTR_OFFSET_TABLE_CONTROL_0r, PARITY_ENf }, 824 { ING_FLEX_CTR_OFFSET_TABLE_CONTROL_1r, PARITY_ENf }, 825 { ING_FLEX_CTR_OFFSET_TABLE_CONTROL_2r, PARITY_ENf }, 826 { ING_FLEX_CTR_OFFSET_TABLE_CONTROL_3r, PARITY_ENf }, 827 { ING_FLEX_CTR_OFFSET_TABLE_CONTROL_4r, PARITY_ENf }, 828 { ING_FLEX_CTR_OFFSET_TABLE_CONTROL_5r, PARITY_ENf }, 829 { ING_FLEX_CTR_OFFSET_TABLE_CONTROL_6r, PARITY_ENf }, 830 { ING_FLEX_CTR_OFFSET_TABLE_CONTROL_7r, PARITY_ENf }, 831 { ING_FLEX_CTR_OFFSET_TABLE_CONTROL_8r, PARITY_ENf }, 832 { ING_FLEX_CTR_OFFSET_TABLE_CONTROL_9r, PARITY_ENf }, 833 { ING_FLEX_CTR_OFFSET_TABLE_CONTROL_10r, PARITY_ENf }, 834 { ING_FLEX_CTR_OFFSET_TABLE_CONTROL_11r, PARITY_ENf }, 835 { ING_FLEX_CTR_OFFSET_TABLE_CONTROL_12r, PARITY_ENf }, 836 { ING_FLEX_CTR_OFFSET_TABLE_CONTROL_13r, PARITY_ENf }, 837 { ING_FLEX_CTR_OFFSET_TABLE_CONTROL_14r, PARITY_ENf }, 838 { ING_FLEX_CTR_OFFSET_TABLE_CONTROL_15r, PARITY_ENf }, 839 { ING_FLEX_CTR_COUNTER_TABLE_CONTROL_0r, PARITY_ENf }, 840 { ING_FLEX_CTR_COUNTER_TABLE_CONTROL_1r, PARITY_ENf }, 841 { ING_FLEX_CTR_COUNTER_TABLE_CONTROL_2r, PARITY_ENf }, 842 { ING_FLEX_CTR_COUNTER_TABLE_CONTROL_3r, PARITY_ENf }, 843 { ING_FLEX_CTR_COUNTER_TABLE_CONTROL_4r, PARITY_ENf }, 844 { ING_FLEX_CTR_COUNTER_TABLE_CONTROL_5r, PARITY_ENf }, 845 { ING_FLEX_CTR_COUNTER_TABLE_CONTROL_6r, PARITY_ENf }, 846 { ING_FLEX_CTR_COUNTER_TABLE_CONTROL_7r, PARITY_ENf }, 847 { ING_FLEX_CTR_COUNTER_TABLE_CONTROL_8r, PARITY_ENf }, 848 { ING_FLEX_CTR_COUNTER_TABLE_CONTROL_9r, PARITY_ENf }, 849 { ING_FLEX_CTR_COUNTER_TABLE_CONTROL_10r, PARITY_ENf }, 850 { ING_FLEX_CTR_COUNTER_TABLE_CONTROL_11r, PARITY_ENf }, 851 { ING_FLEX_CTR_COUNTER_TABLE_CONTROL_12r, PARITY_ENf }, 852 { ING_FLEX_CTR_COUNTER_TABLE_CONTROL_13r, PARITY_ENf }, 853 { ING_FLEX_CTR_COUNTER_TABLE_CONTROL_14r, PARITY_ENf }, 854 { ING_FLEX_CTR_COUNTER_TABLE_CONTROL_15r, PARITY_ENf }, 855 { ING_SVM_MACROFLOW_INDEX_TABLE_CONTROLr, PARITY_ENf }, 856 { ING_SVM_METER_TABLE_CONTROLr, PARITY_ENf }, 857 { ING_SVM_OFFSET_TABLE_CONTROLr, PARITY_ENf }, 858 { ING_SVM_POLICY_TABLE_CONTROLr, PARITY_ENf }, 859 /* { IL2L3_BUS_SER_CONTROLr, PARITY_ENf }, */ 860 /* { FP_BUS_PARITY_CONTROLr, IFP_BUS_PARITY_ENf }, */ 861 { IESMIF_ECC_CONTROLr, AUX1_FIFO_ECC_ENf }, 862 { IESMIF_ECC_CONTROLr, ADM_CTRL_FIFO_ECC_ENf }, 863 { IESMIF_ECC_CONTROLr, ET_RSP_FIFO_ECC_ENf }, 864 { IESMIF_ECC_CONTROLr, CTRL_BUS_FIFO_ECC_ENf }, 865 { IESMIF_ECC_CONTROLr, CTRL_BUS_FIFO_1_ECC_ENf }, 866 { IESMIF_ECC_CONTROLr, SER_STATUS_BUS_ECC_ENf }, 867 { IESMIF_PARITY_CONTROLr, AD_6X_PARITY_ENf }, 868 { IESMIF_PARITY_CONTROLr, AD_4X_PARITY_ENf }, 869 { IESMIF_PARITY_CONTROLr, AD_3X_PARITY_ENf }, 870 { IESMIF_PARITY_CONTROLr, AD_2X_PARITY_ENf }, 871 { IESMIF_PARITY_CONTROLr, AD_1X_PARITY_ENf }, 872 { INVALIDr } 873 }; 874 875 static 876 _soc_tr3_fifo_parity_info_t _soc_tr3_ep_parity_info[] = { 877 { EGR_EL3_SER_CONTROLr, EGR_L3_NEXT_HOP_PARITY_ENf }, 878 { EGR_EL3_SER_CONTROLr, EGR_MAC_DA_PROFILE_PARITY_ENf }, 879 { EGR_EL3_SER_CONTROLr, EGR_L3_INTF_PARITY_ENf }, 880 { EGR_EL3_SER_CONTROLr, EGR_DVP_ATTRIBUTE_PARITY_ENf }, 881 { EGR_EL3_SER_CONTROLr, EGR_MPLS_VC_AND_SWAP_LABEL_TABLE_PARITY_ENf }, 882 { EGR_EL3_SER_CONTROLr, EGR_VFI_PARITY_ENf }, 883 { EGR_EL3_SER_CONTROLr, EGR_IPMC_PARITY_ENf }, 884 { EGR_EL3_SER_CONTROLr, EGR_MAP_MH_PARITY_ENf }, 885 { EGR_EL3_SER_CONTROLr, EGR_IFP_MOD_FIELDS_PARITY_ENf }, 886 { EGR_EL3_SER_CONTROLr, EGR_MPB_ECC_ENf }, 887 { EGR_EVLAN_SER_CONTROLr, EGR_VLAN_PARITY_ENf }, 888 { EGR_EVLAN_SER_CONTROLr, EGR_VLAN_STG_PARITY_ENf }, 889 { EGR_EVLAN_SER_CONTROLr, EGR_PRI_CNG_MAP_PARITY_ENf }, 890 { EGR_EVLAN_SER_CONTROLr, EGR_IP_TUNNEL_PARITY_ENf }, 891 { EGR_EVLAN_SER_CONTROLr, EGR_MPLS_EXP_MAPPING_1_PARITY_ENf }, 892 { EGR_EVLAN_SER_CONTROLr, EGR_MPLS_EXP_MAPPING_2_PARITY_ENf }, 893 { EGR_EVLAN_SER_CONTROLr, EGR_MPLS_PRI_MAPPING_PARITY_ENf }, 894 { EGR_EVLAN_SER_CONTROLr, EGR_FRAGMENT_ID_TABLE_PARITY_ENf }, 895 { EGR_EVLAN_SER_CONTROLr, EGR_DSCP_TABLE_PARITY_ENf }, 896 { EGR_EVLAN_SER_CONTROLr, EGR_GPP_ATTRIBUTES_MODBASE_PARITY_ENf }, 897 { EGR_EVLAN_SER_CONTROLr, EGR_GPP_ATTRIBUTES_PARITY_ENf }, 898 { EGR_EVLAN_SER_CONTROLr, EGR_EHG_QOS_MAPPING_TABLE_PARITY_ENf }, 899 { EGR_EVLAN_SER_CONTROLr, EVLAN_BUS_PARITY_ENf }, 900 { EGR_EHCPM_SER_CONTROLr, MOD_MAP_PARITY_ENf }, 901 { EGR_EHCPM_SER_CONTROLr, EHCPM_BUS_PARITY_ENf }, 902 { EGR_EHCPM_SER_CONTROLr, INITBUF_ECC_ENf }, 903 { EGR_EFPPARS_SER_CONTROLr, EGR_1588_SA_PARITY_ENf }, 904 { EGR_EFPPARS_SER_CONTROLr, EFPPARS_BUS_PARITY_ENf }, 905 { EFP_PARITY_CONTROLr, POLICY_PARITY_ENf }, 906 { EFP_PARITY_CONTROLr, METER_PARITY_ENf }, /* B0 onwards only */ 907 { EFP_PARITY_CONTROLr, EGR_PW_INIT_COUNTER_PARITY_ENf }, 908 { EGR_EDATABUF_PARITY_CONTROLr, EFPCTR_PAR_ENf }, 909 { EGR_EDATABUF_PARITY_CONTROLr, PERQ_PAR_ENf }, 910 { EGR_EDATABUF_PARITY_CONTROLr, STATS_PAR_ENf }, 911 { EGR_EDATABUF_PARITY_CONTROLr, XTP_RESI_ECC_ENf }, /* B0 onwards only */ 912 { EGR_EDATABUF_PARITY_CONTROLr, CLP1_ECC_ENf }, 913 { EGR_EDATABUF_PARITY_CONTROLr, CLP0_ECC_ENf }, 914 { EGR_EDATABUF_PARITY_CONTROLr, XTP3_ECC_ENf }, 915 { EGR_EDATABUF_PARITY_CONTROLr, XTP2_ECC_ENf }, 916 { EGR_EDATABUF_PARITY_CONTROLr, XTP1_ECC_ENf }, 917 { EGR_EDATABUF_PARITY_CONTROLr, XTP0_ECC_ENf }, 918 { EGR_EDATABUF_PARITY_CONTROLr, XLP1_ECC_ENf }, 919 { EGR_EDATABUF_PARITY_CONTROLr, XLP0_ECC_ENf }, 920 { EGR_EDATABUF_PARITY_CONTROLr, CM_ECC_ENf }, 921 { EGR_IPFIX_SER_CONTROLr, SESSION_TBLf }, 922 { EGR_IPFIX_SER_CONTROLr, EXPORT_FIFOf }, 923 { EGR_IPFIX_SER_CONTROLr, EOP_TBLf }, 924 { EGR_IPFIX_SER_CONTROLr, FLOW_TBLf }, 925 { EGR_FLEX_CTR_OFFSET_TABLE_CONTROL_0r, PARITY_ENf }, 926 { EGR_FLEX_CTR_OFFSET_TABLE_CONTROL_1r, PARITY_ENf }, 927 { EGR_FLEX_CTR_OFFSET_TABLE_CONTROL_2r, PARITY_ENf }, 928 { EGR_FLEX_CTR_OFFSET_TABLE_CONTROL_3r, PARITY_ENf }, 929 { EGR_FLEX_CTR_OFFSET_TABLE_CONTROL_4r, PARITY_ENf }, 930 { EGR_FLEX_CTR_OFFSET_TABLE_CONTROL_5r, PARITY_ENf }, 931 { EGR_FLEX_CTR_OFFSET_TABLE_CONTROL_6r, PARITY_ENf }, 932 { EGR_FLEX_CTR_OFFSET_TABLE_CONTROL_7r, PARITY_ENf }, 933 { EGR_FLEX_CTR_COUNTER_TABLE_CONTROL_0r, PARITY_ENf }, 934 { EGR_FLEX_CTR_COUNTER_TABLE_CONTROL_1r, PARITY_ENf }, 935 { EGR_FLEX_CTR_COUNTER_TABLE_CONTROL_2r, PARITY_ENf }, 936 { EGR_FLEX_CTR_COUNTER_TABLE_CONTROL_3r, PARITY_ENf }, 937 { EGR_FLEX_CTR_COUNTER_TABLE_CONTROL_4r, PARITY_ENf }, 938 { EGR_FLEX_CTR_COUNTER_TABLE_CONTROL_5r, PARITY_ENf }, 939 { EGR_FLEX_CTR_COUNTER_TABLE_CONTROL_6r, PARITY_ENf }, 940 { EGR_FLEX_CTR_COUNTER_TABLE_CONTROL_7r, PARITY_ENf }, 941 { EGR_EPMOD_SER_CONTROLr, EPMOD_BUS_PARITY_ENf }, 942 { EFP_BUS_PARITY_CONTROLr, EFP_BUS_PARITY_ENf }, 943 { INVALIDr } 944 }; 945 946 static 947 _soc_tr3_fifo_parity_info_t _soc_tr3_ism_parity_info[] = { 948 { HASH_TABLE_PARITY_CONTROLr, TABLE0_PARITY_ENf }, 949 { HASH_TABLE_PARITY_CONTROLr, TABLE1_PARITY_ENf }, 950 { HASH_TABLE_PARITY_CONTROLr, TABLE2_PARITY_ENf }, 951 { HASH_TABLE_PARITY_CONTROLr, TABLE3_PARITY_ENf }, 952 { HASH_TABLE_PARITY_CONTROLr, TABLE4_PARITY_ENf }, 953 { L2_MOD_FIFO_PARITY_CONTROLr, L2_MOD_FIFO_PARITY_ENf }, 954 /*{ MAC_LIMIT_PARITY_CONTROLr, PORT_OR_TRUNK_MAC_COUNT_PARITY_ENf }, 955 { MAC_LIMIT_PARITY_CONTROLr, PORT_OR_TRUNK_MAC_LIMIT_PARITY_ENf },*/ 956 { MAC_LIMIT_PARITY_CONTROLr, VLAN_OR_VFI_MAC_COUNT_PARITY_ENf }, 957 { MAC_LIMIT_PARITY_CONTROLr, VLAN_OR_VFI_MAC_LIMIT_PARITY_ENf }, 958 { LEARN_FIFO_ECC_CONTROLr, ECC_ENf }, 959 { INVALIDr } 960 }; 961 962 static const 963 _soc_tr3_parity_block_info_t _soc_tr3_parity_block_info[] = { 964 { SOC_BLK_IPIPE, ING_SER_FIFO_CTRLr, _soc_tr3_ip_parity_info }, 965 { SOC_BLK_EPIPE, EGR_SER_FIFO_CTRLr, _soc_tr3_ep_parity_info }, 966 { SOC_BLK_ISM, ISM_SER_FIFO_CTRLr, _soc_tr3_ism_parity_info }, 967 { 0 } 968 }; 969 970 #define _TR3_IRSEL1_TO_CMIC_OAM_INTR 0x00000010 971 #define _TR3_IP0_TO_CMIC_PERR_INTR 0x00000004 972 #define _TR3_IP5_TO_CMIC_PERR_INTR 0x00000020 973 #define _TR3_IP_TO_CMIC_PERR_INTR (_TR3_IP0_TO_CMIC_PERR_INTR | _TR3_IP5_TO_CMIC_PERR_INTR) 974 975 static const 976 _soc_tr3_parity_route_block_t _soc_tr3_parity_route_blocks[] = { 977 { 0, 0x00000001, /* MMU_TO_CMIC_MEMFAIL_INTR */ 978 SOC_BLK_MMU, MEM_FAIL_INT_EN_64r, MEM_FAIL_INT_STAT_64r, INVALIDf, 979 _soc_tr3_mmu_parity_info, 0 }, 980 { 0, _TR3_IP0_TO_CMIC_PERR_INTR, /* IP0_TO_CMIC_PERR_INTR */ 981 SOC_BLK_IPIPE, INVALIDr, INVALIDr, INVALIDf, NULL, 0 }, 982 { 0, 0x00000008, /* IESMIF_TO_CMIC_ERR_INTR */ 983 SOC_BLK_IPIPE, INVALIDr, INVALIDr, INVALIDf, NULL, 0 }, 984 { 0, 0x00000010, /* IRSEL1_TO_CMIC_OAM_INTR */ 985 SOC_BLK_IPIPE, INVALIDr, INVALIDr, INVALIDf, NULL, 0 }, 986 { 0, _TR3_IP5_TO_CMIC_PERR_INTR, /* IP5_TO_CMIC_PERR_INTR */ 987 SOC_BLK_IPIPE, INVALIDr, INVALIDr, INVALIDf, NULL, 0 }, 988 { 0, 0x00000040, /* XTP0_TO_CMIC_PERR_INTR */ 989 SOC_BLK_XTPORT, PORT_INTR_ENABLEr, PORT_INTR_STATUSr, INVALIDf, 990 _soc_tr3_port_parity_info, 0 }, 991 { 0, 0x00000080, /* XTP1_TO_CMIC_PERR_INTR */ 992 SOC_BLK_XTPORT, PORT_INTR_ENABLEr, PORT_INTR_STATUSr, INVALIDf, 993 _soc_tr3_port_parity_info, 1 }, 994 { 0, 0x00000100, /* XTP2_TO_CMIC_PERR_INTR */ 995 SOC_BLK_XTPORT, PORT_INTR_ENABLEr, PORT_INTR_STATUSr, INVALIDf, 996 _soc_tr3_port_parity_info, 2 }, 997 { 0, 0x00000200, /* XTP3_TO_CMIC_PERR_INTR */ 998 SOC_BLK_XTPORT, PORT_INTR_ENABLEr, PORT_INTR_STATUSr, INVALIDf, 999 _soc_tr3_port_parity_info, 3 }, 1000 { 0, 0x00000400, /* XLP0_TO_CMIC_PERR_INTR */ 1001 SOC_BLK_XLPORT, PORT_INTR_ENABLEr, PORT_INTR_STATUSr, INVALIDf, 1002 _soc_tr3_port_parity_info, 0 }, 1003 { 0, 0x00000800, /* XLP1_TO_CMIC_PERR_INTR */ 1004 SOC_BLK_XLPORT, PORT_INTR_ENABLEr, PORT_INTR_STATUSr, INVALIDf, 1005 _soc_tr3_port_parity_info, 1 }, 1006 { 0, 0x00001000, /* CLP0_TO_CMIC_PERR_INTR */ 1007 SOC_BLK_CLPORT, PORT_INTR_ENABLEr, PORT_INTR_STATUSr, INVALIDf, 1008 _soc_tr3_port_parity_info, 0 }, 1009 { 0, 0x00002000, /* CLP0_TO_CMIC_PERR_INTR */ 1010 SOC_BLK_CLPORT, PORT_INTR_ENABLEr, PORT_INTR_STATUSr, INVALIDf, 1011 _soc_tr3_port_parity_info, 1 }, 1012 { 0, 0x00004000, /* PCIE_REPLAY_PERR */ 1013 SOC_BLK_CMIC, INVALIDr, INVALIDr, INVALIDf, NULL, 0 }, 1014 /* Make the SER engine to deal the EGR_VLAN_XLATE SER event 1015 earlier than the SOP CELL ERROR to break the loop of raising 1016 SOP CELL ERROR. 1017 */ 1018 { 1, _SOC_TR3_ISM_INTR_MASK, /* ISM_TO_CMIC_INTR */ 1019 SOC_BLK_ISM, ISM_INTR_MASKr, ISM_INTRr, SER_FIFO_NOT_EMPTYf, NULL, 0 }, 1020 { 0, 0x00000002, /* EP2_TO_CMIC_PERR_INTR */ 1021 SOC_BLK_EPIPE, EGR_INTR_ENABLEr, INVALIDr, SER_FIFO_NON_EMPTYf, 1022 NULL, 0 }, 1023 { 1, _SOC_TR3_AXP_INTR_MASK, /* AXP_TO_CMIC_INTR */ 1024 SOC_BLK_AXP, AXP_CH_INT_MASKr, AXP_CH_INT_STATUSr, INVALIDf, 1025 _soc_tr3_axp_parity_info, 0 }, 1026 { 1, _SOC_TR3_IBOD_INTR_MASK, /* BOD_TO_CMIC_INTR */ 1027 SOC_BLK_IBOD, IBOD_INTR_MASKr, IBOD_INTR_STATUSr, INVALIDf, 1028 _soc_tr3_ibod_parity_info, 0 }, 1029 { 0, 0 } /* table terminator */ 1030 }; 1031 1032 static const 1033 _soc_tr3_parity_route_block_t _soc_hx4_parity_route_blocks[] = { 1034 { 0, 0x00000001, /* MMU_TO_CMIC_MEMFAIL_INTR */ 1035 SOC_BLK_MMU, MEM_FAIL_INT_EN_64r, MEM_FAIL_INT_STAT_64r, INVALIDf, 1036 _soc_tr3_mmu_parity_info, 0 }, 1037 { 0, 0x00000002, /* EP2_TO_CMIC_PERR_INTR */ 1038 SOC_BLK_EPIPE, EGR_INTR_ENABLEr, INVALIDr, SER_FIFO_NON_EMPTYf, 1039 NULL, 0 }, 1040 { 0, _TR3_IP0_TO_CMIC_PERR_INTR, /* IP0_TO_CMIC_PERR_INTR */ 1041 SOC_BLK_IPIPE, INVALIDr, INVALIDr, INVALIDf, NULL, 0 }, 1042 { 0, 0x00000010, /* IRSEL1_TO_CMIC_OAM_INTR */ 1043 SOC_BLK_IPIPE, INVALIDr, INVALIDr, INVALIDf, NULL, 0 }, 1044 { 0, _TR3_IP5_TO_CMIC_PERR_INTR, /* IP5_TO_CMIC_PERR_INTR */ 1045 SOC_BLK_IPIPE, INVALIDr, INVALIDr, INVALIDf, NULL, 0 }, 1046 { 0, 0x00000040, /* XTP0_TO_CMIC_PERR_INTR */ 1047 SOC_BLK_XTPORT, PORT_INTR_ENABLEr, PORT_INTR_STATUSr, INVALIDf, 1048 _soc_tr3_port_parity_info, 0 }, 1049 { 0, 0x00000080, /* XTP1_TO_CMIC_PERR_INTR */ 1050 SOC_BLK_XTPORT, PORT_INTR_ENABLEr, PORT_INTR_STATUSr, INVALIDf, 1051 _soc_tr3_port_parity_info, 1 }, 1052 { 0, 0x00000100, /* XTP2_TO_CMIC_PERR_INTR */ 1053 SOC_BLK_XTPORT, PORT_INTR_ENABLEr, PORT_INTR_STATUSr, INVALIDf, 1054 _soc_tr3_port_parity_info, 2 }, 1055 { 0, 0x00000200, /* XTP3_TO_CMIC_PERR_INTR */ 1056 SOC_BLK_XTPORT, PORT_INTR_ENABLEr, PORT_INTR_STATUSr, INVALIDf, 1057 _soc_tr3_port_parity_info, 3 }, 1058 { 0, 0x00000400, /* XLP0_TO_CMIC_PERR_INTR */ 1059 SOC_BLK_XLPORT, PORT_INTR_ENABLEr, PORT_INTR_STATUSr, INVALIDf, 1060 _soc_tr3_port_parity_info, 0 }, 1061 { 0, 0x00000800, /* XWP0_TO_CMIC_PERR_INTR */ 1062 SOC_BLK_XWPORT, PORT_INTR_ENABLEr, PORT_INTR_STATUSr, INVALIDf, 1063 _soc_tr3_port_parity_info, 0 }, 1064 { 0, 0x00001000, /* XWP1_TO_CMIC_PERR_INTR */ 1065 SOC_BLK_XWPORT, PORT_INTR_ENABLEr, PORT_INTR_STATUSr, INVALIDf, 1066 _soc_tr3_port_parity_info, 1 }, 1067 { 0, 0x00002000, /* XWP2_TO_CMIC_PERR_INTR */ 1068 SOC_BLK_XWPORT, PORT_INTR_ENABLEr, PORT_INTR_STATUSr, INVALIDf, 1069 _soc_tr3_port_parity_info, 2 }, 1070 { 0, 0x00004000, /* PCIE_REPLAY_PERR */ 1071 SOC_BLK_CMIC, INVALIDr, INVALIDr, INVALIDf, NULL, 0 }, 1072 { 1, _SOC_TR3_ISM_INTR_MASK, /* ISM_TO_CMIC_INTR */ 1073 SOC_BLK_ISM, ISM_INTR_MASKr, ISM_INTRr, SER_FIFO_NOT_EMPTYf, NULL, 0 }, 1074 { 1, _SOC_TR3_AXP_INTR_MASK, /* AXP_TO_CMIC_INTR */ 1075 SOC_BLK_AXP, AXP_CH_INT_MASKr, AXP_CH_INT_STATUSr, INVALIDf, 1076 _soc_tr3_axp_parity_info, 0 }, 1077 { 1, _SOC_TR3_IBOD_INTR_MASK, /* BOD_TO_CMIC_INTR */ 1078 SOC_BLK_IBOD, IBOD_INTR_MASKr, IBOD_INTR_STATUSr, INVALIDf, 1079 _soc_hx4_ibod_parity_info, 0 }, 1080 { 0, 0 } /* table terminator */ 1081 }; 1082 1083 static soc_ser_functions_t _tr3_ser_functions; 1084 1085 static soc_tr3_oam_handler_t tr3_oam_handler[SOC_MAX_NUM_DEVICES] = {NULL}; 1086 static soc_tr3_oam_ser_handler_t tr3_oam_ser_handler[SOC_MAX_NUM_DEVICES] = {NULL}; 1087 1088 STATIC int 1089 _soc_tr3_parity_enable_info(int unit, int port, soc_reg_t group_reg, uint64 *group_rval, 1090 const _soc_tr3_parity_info_t *info_list, 1091 soc_mem_t mem, int enable) 1092 { 1093 const _soc_tr3_parity_info_t *info; 1094 int info_index; 1095 soc_reg_t reg; 1096 uint32 rval; 1097 1098 /* Loop through each info entry in the list */ 1099 for (info_index = 0; ; info_index++) { 1100 info = &info_list[info_index]; 1101 if (info->type == _SOC_PARITY_TYPE_NONE) { 1102 /* End of table */ 1103 break; 1104 } 1105 1106 if (mem != INVALIDm && info->mem != mem) { 1107 continue; 1108 } 1109 1110 if (group_reg != INVALIDr && group_rval && 1111 info->group_reg_enable_field != INVALIDf) { 1112 /* Enable the info entry in the group register */ 1113 if (SOC_REG_IS_64(unit, group_reg)) { 1114 soc_reg64_field32_set(unit, group_reg, group_rval, 1115 info->group_reg_enable_field, enable ? 1 : 0); 1116 } else { 1117 rval = COMPILER_64_LO(*group_rval); 1118 soc_reg_field_set(unit, group_reg, &rval, 1119 info->group_reg_enable_field, enable ? 1 : 0); 1120 COMPILER_64_SET(*group_rval, 0, rval); 1121 } 1122 } 1123 /* Handle different parity error enabling style */ 1124 switch (info->type) { 1125 case _SOC_PARITY_TYPE_PARITY: 1126 case _SOC_PARITY_TYPE_ECC: 1127 case _SOC_PARITY_TYPE_AXP: 1128 reg = info->enable_reg; 1129 if (reg != INVALIDr && info->enable_field != INVALIDf) { 1130 SOC_IF_ERROR_RETURN 1131 (soc_reg32_get(unit, reg, port, 0, &rval)); 1132 soc_reg_field_set(unit, reg, &rval, info->enable_field, 1133 enable ? 1 : 0); 1134 SOC_IF_ERROR_RETURN 1135 (soc_reg32_set(unit, reg, port, 0, rval)); 1136 } 1137 if (info->ext_en != NULL) { 1138 reg = info->ext_en->enable_reg; 1139 if (reg != INVALIDr) { 1140 uint8 fidx = 0; 1141 1142 SOC_IF_ERROR_RETURN 1143 (soc_reg32_get(unit, reg, port, 0, &rval)); 1144 while (info->ext_en->enable_field_list[fidx] != INVALIDf) { 1145 soc_reg_field_set(unit, reg, &rval, 1146 info->ext_en->enable_field_list[fidx], 1147 enable ? 1 : 0); 1148 fidx++; 1149 } 1150 SOC_IF_ERROR_RETURN 1151 (soc_reg32_set(unit, reg, port, 0, rval)); 1152 } 1153 } 1154 if (info->info != NULL) { 1155 if (info->enable_reg != INVALIDr) { 1156 uint64 rval64; 1157 SOC_IF_ERROR_RETURN 1158 (soc_reg32_get(unit, info->enable_reg, port, 0, &rval)); 1159 COMPILER_64_SET(rval64, 0, rval); 1160 SOC_IF_ERROR_RETURN 1161 (_soc_tr3_parity_enable_info(unit, port, info->enable_reg, 1162 &rval64, info->info, 1163 INVALIDm, enable)); 1164 1165 rval = COMPILER_64_LO(rval64); 1166 SOC_IF_ERROR_RETURN 1167 (soc_reg32_set(unit, info->enable_reg, port, 0, rval)); 1168 } else { 1169 SOC_IF_ERROR_RETURN 1170 (_soc_tr3_parity_enable_info(unit, port, INVALIDr, 1171 NULL, info->info, 1172 INVALIDm, enable)); 1173 } 1174 } 1175 break; 1176 case _SOC_PARITY_TYPE_GENERIC: 1177 case _SOC_PARITY_TYPE_MMU_THDO: 1178 case _SOC_PARITY_TYPE_MMU_THDI: 1179 case _SOC_PARITY_TYPE_MMU_WRED: 1180 case _SOC_PARITY_TYPE_MMU_QCN: 1181 case _SOC_PARITY_TYPE_MMU_LLS: 1182 case _SOC_PARITY_TYPE_BST: 1183 default: 1184 break; 1185 } /* Handle different parity error enabling style */ 1186 if (mem != INVALIDm) { 1187 break; 1188 } 1189 } /* Loop through each info entry in the route block */ 1190 return SOC_E_NONE; 1191 } 1192 1193 STATIC int 1194 _soc_tr3_parity_enable_all(int unit, int enable) 1195 { 1196 int rv, blk_inf_idx, port = REG_PORT_ANY; 1197 uint8 rbi, bcount; 1198 uint16 pcount; 1199 uint32 cmic_bit, cmic_rval1 = 0, cmic_rval2 = 0; 1200 uint32 rval; 1201 uint64 rval64; 1202 soc_reg_t reg; 1203 soc_field_t field; 1204 const _soc_tr3_parity_route_block_t *rb; 1205 uint16 dev_id; 1206 uint8 rev_id; 1207 1208 soc_cm_get_id(unit, &dev_id, &rev_id); 1209 1210 for (bcount = 0; _soc_tr3_parity_block_info[bcount].blocktype; bcount++) { 1211 for (pcount = 0; 1212 _soc_tr3_parity_block_info[bcount].info[pcount].enable_reg != INVALIDr; 1213 pcount++) { 1214 reg = _soc_tr3_parity_block_info[bcount].info[pcount].enable_reg; 1215 field = _soc_tr3_parity_block_info[bcount].info[pcount].enable_field; 1216 if (!SOC_REG_IS_VALID(unit, reg) || 1217 !soc_reg_field_valid(unit, reg, field)) { 1218 continue; 1219 } 1220 if (!(soc_feature(unit, soc_feature_esm_support) || SOC_CONTROL(unit)->tcam_info) && 1221 SOC_BLOCK_IS(SOC_REG_INFO(unit,reg).block, SOC_BLK_IPIPE) && 1222 SOC_REG_STAGE(unit, reg) == 0x9) { /* IESMIF */ 1223 continue; 1224 } 1225 1226 /* coverity[Logically dead code] */ 1227 if ((reg == ING_SVM_METER_TABLE_CONTROLr) && 1228 (soc_mem_index_max(unit, SVM_METER_TABLEm) < 0)) { 1229 continue; 1230 } 1231 1232 /* coverity[Logically dead code] */ 1233 if ((reg == ING_SVM_POLICY_TABLE_CONTROLr) && 1234 (soc_mem_index_max(unit, SVM_POLICY_TABLEm) < 0)) { 1235 continue; 1236 } 1237 1238 /* disable parity on egress residual buffer */ 1239 if (reg == EGR_EDATABUF_PARITY_CONTROLr && 1240 field == XTP_RESI_ECC_ENf) { 1241 rv = soc_reg_field32_modify(unit, reg, REG_PORT_ANY, field, 0); 1242 if (SOC_FAILURE(rv)) { 1243 return rv; 1244 } 1245 continue; 1246 } 1247 1248 if (!(rev_id & 0xF0) && /* These work on B0 onwards only */ 1249 (reg == EFP_PARITY_CONTROLr && field == METER_PARITY_ENf)) { 1250 continue; 1251 } 1252 rv = soc_reg_field32_modify(unit, reg, REG_PORT_ANY, field, 1253 (enable ? 1 : 0)); 1254 if (SOC_FAILURE(rv)) { 1255 return rv; 1256 } 1257 } 1258 /* Loop through each place-and-route block entry */ 1259 for (rbi = 0; ; rbi++) { 1260 rb = SOC_IS_HELIX4(unit) ? &_soc_hx4_parity_route_blocks[rbi]: 1261 &_soc_tr3_parity_route_blocks[rbi]; 1262 cmic_bit = rb->cmic_bit; 1263 if (cmic_bit == 0) { 1264 /* End of table */ 1265 break; 1266 } 1267 if (rb->blocktype == _soc_tr3_parity_block_info[bcount].blocktype) { 1268 /* New SER mechanism */ 1269 if (enable) { 1270 if (rb->cmic_reg == 0) { 1271 cmic_rval1 |= cmic_bit; 1272 } else { 1273 cmic_rval2 |= cmic_bit; 1274 } 1275 } 1276 if (rb->enable_reg != INVALIDr) { 1277 SOC_IF_ERROR_RETURN 1278 (soc_reg_field32_modify(unit, rb->enable_reg, 1279 REG_PORT_ANY, rb->enable_field, enable ? 1 : 0)); 1280 } 1281 } 1282 } 1283 /* reset (toggle) fifo if applicable */ 1284 if (_soc_tr3_parity_block_info[bcount].fifo_reset_reg != INVALIDr) { 1285 SOC_IF_ERROR_RETURN 1286 (soc_reg_field32_modify(unit, 1287 _soc_tr3_parity_block_info[bcount].fifo_reset_reg, 1288 REG_PORT_ANY, FIFO_RESETf, 1)); 1289 SOC_IF_ERROR_RETURN 1290 (soc_reg_field32_modify(unit, 1291 _soc_tr3_parity_block_info[bcount].fifo_reset_reg, 1292 REG_PORT_ANY, FIFO_RESETf, 0)); 1293 } 1294 } 1295 /* Loop through each place-and-route block entry */ 1296 for (rbi = 0; ; rbi++) { 1297 rb = SOC_IS_HELIX4(unit) ? &_soc_hx4_parity_route_blocks[rbi]: 1298 &_soc_tr3_parity_route_blocks[rbi]; 1299 cmic_bit = rb->cmic_bit; 1300 if (cmic_bit == 0) { 1301 /* End of table */ 1302 break; 1303 } 1304 if (rb->info == NULL) { 1305 continue; 1306 } 1307 if (enable) { 1308 if (rb->cmic_reg == 0) { 1309 cmic_rval1 |= cmic_bit; 1310 } else { 1311 cmic_rval2 |= cmic_bit; 1312 } 1313 } 1314 /* Legacy style SER enabling */ 1315 SOC_BLOCK_ITER(unit, blk_inf_idx, rb->blocktype) { 1316 if (SOC_BLOCK_INFO(unit, blk_inf_idx).number == rb->id) { 1317 port = SOC_BLOCK_PORT(unit, blk_inf_idx); 1318 break; 1319 } 1320 } 1321 if (SOC_BLOCK_IN_LIST(SOC_REG_INFO(unit, rb->enable_reg).block, 1322 SOC_BLK_PORT) && (port == REG_PORT_ANY)) { 1323 /* This port block is not configured */ 1324 continue; 1325 } 1326 if (rb->enable_reg != INVALIDr) { 1327 if (SOC_REG_IS_64(unit, rb->enable_reg)) { 1328 SOC_IF_ERROR_RETURN(soc_reg_get(unit, rb->enable_reg, 1329 port, 0, &rval64)); 1330 } else { 1331 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, rb->enable_reg, 1332 port, 0, &rval)); 1333 1334 COMPILER_64_SET(rval64, 0, rval); 1335 } 1336 } 1337 rv = _soc_tr3_parity_enable_info(unit, port, rb->enable_reg, 1338 &rval64, rb->info, 1339 INVALIDm, enable); 1340 if (rv == SOC_E_NOT_FOUND) { 1341 continue; 1342 } else if (SOC_FAILURE(rv)) { 1343 return rv; 1344 } 1345 /* Write per route block parity enable register */ 1346 if (rb->enable_reg != INVALIDr) { 1347 if (SOC_REG_IS_64(unit, rb->enable_reg)) { 1348 SOC_IF_ERROR_RETURN 1349 (soc_reg_set(unit, rb->enable_reg, port, 0, rval64)); 1350 } else { 1351 rval = COMPILER_64_LO(rval64); 1352 SOC_IF_ERROR_RETURN 1353 (soc_reg32_set(unit, rb->enable_reg, port, 0, rval)); 1354 } 1355 } 1356 } 1357 1358 SOC_IF_ERROR_RETURN(READ_MISCCONFIGr(unit, &rval)); 1359 soc_reg_field_set(unit, MISCCONFIGr, &rval, PARITY_STAT_CLEARf, 1); 1360 SOC_IF_ERROR_RETURN(WRITE_MISCCONFIGr(unit, rval)); 1361 if (enable) { 1362 /* MMU enables */ 1363 soc_reg_field_set(unit, MISCCONFIGr, &rval, PARITY_CHK_ENf, 1); 1364 soc_reg_field_set(unit, MISCCONFIGr, &rval, PARITY_GEN_ENf, 1); 1365 soc_reg_field_set(unit, MISCCONFIGr, &rval, PARITY_STAT_CLEARf, 0); 1366 soc_reg_field_set(unit, MISCCONFIGr, &rval, METERING_CLK_ENf, 1); 1367 SOC_IF_ERROR_RETURN(WRITE_MISCCONFIGr(unit, rval)); 1368 /* Write CMIC enable register */ 1369 #ifdef BCM_CMICM_SUPPORT 1370 if (soc_feature(unit, soc_feature_cmicm)) { 1371 (void)soc_cmicm_intr2_enable(unit, cmic_rval1); 1372 (void)soc_cmicm_intr1_enable(unit, cmic_rval2); 1373 } 1374 #endif 1375 } else { 1376 /* MMU disables */ 1377 soc_reg_field_set(unit, MISCCONFIGr, &rval, PARITY_CHK_ENf, 0); 1378 soc_reg_field_set(unit, MISCCONFIGr, &rval, PARITY_GEN_ENf, 0); 1379 soc_reg_field_set(unit, MISCCONFIGr, &rval, PARITY_STAT_CLEARf, 0); 1380 soc_reg_field_set(unit, MISCCONFIGr, &rval, METERING_CLK_ENf, 0); 1381 SOC_IF_ERROR_RETURN(WRITE_MISCCONFIGr(unit, rval)); 1382 /* Write CMIC disable register */ 1383 #ifdef BCM_CMICM_SUPPORT 1384 if (soc_feature(unit, soc_feature_cmicm)) { 1385 (void)soc_cmicm_intr2_disable(unit, cmic_rval1); 1386 (void)soc_cmicm_intr1_disable(unit, cmic_rval2); 1387 } 1388 #endif 1389 } 1390 1391 return SOC_E_NONE; 1392 } 1393 1394 static char *_soc_tr3_ser_hwmem_base_info[] = { 1395 "CMIC PKT BUFFER - In Iarb", 1396 "CPU PKT BUFFER - In Iarb", 1397 "AXP PACKET BUFFER - In Iarb", 1398 "IFP COUNTER MUX DATA STAGING - In Ifp", 1399 "INGRESS PACKET BUFFER - In Ipars", 1400 "ESM AUX1 FIFO - In Iesmif", 1401 "ESM CTRL BUS FIFO - In Iesmif", 1402 "ESM ADM CTRL FIFO - In Iesmif", 1403 "ESM ET RSP FIFO - In Iesmif", 1404 "ESM CTRL BUS FIFO 1 - In Iesmif", 1405 "ESM SER STATUS BUS FIFO - In Iesmif", 1406 "ISW2 EOP BUFFER A - In Iesmif", 1407 "ISW2 EOP BUFFER B - In Iesmif", 1408 "ISW2 EOP BUFFER C - In Iesmif", 1409 "Invalid value", 1410 "Invalid value", 1411 "EP MPB DATA - In El3", 1412 "EP INITBUF - In Ehcpm", 1413 "CM DATA BUFFER - In Edatabuf", 1414 "XLP0 DATA BUFFER - In Edatabuf", 1415 "XLP1 DATA BUFFER - In Edatabuf", 1416 "XTP0 DATA BUFFER - In Edatabuf", 1417 "XTP1 DATA BUFFER - In Edatabuf", 1418 "XTP2 DATA BUFFER - In Edatabuf", 1419 "XTP3 DATA BUFFER - In Edatabuf", 1420 "CLP0 DATA BUFFER - In Edatabuf", 1421 "CLP1 DATA BUFFER - In Edatabuf", 1422 "XTP RESI DATA BUFFER - In Edatabuf", 1423 "Invalid value", 1424 "Invalid value", 1425 "Invalid value", 1426 "Invalid value", 1427 "Invalid value", 1428 "IPARS - PassThrought bus parity check", 1429 "IVXLT - PassThrought bus parity check", 1430 "IMPLS - PassThrought bus parity check", 1431 "IL2L3 - PassThrought bus parity check", 1432 "IESMIF - PassThrought bus parity check", 1433 "IFP - PassThrought bus parity check", 1434 "IRSEL1 - PassThrought bus parity check", 1435 "ISW1 - PassThrought bus parity check", 1436 "IRSEL2 - PassThrought bus parity check", 1437 "Invalid value", 1438 "Invalid value", 1439 "Invalid value", 1440 "Invalid value", 1441 "Invalid value", 1442 "Invalid value", 1443 "Invalid value", 1444 "EGR VLAN - PassThrought bus parity check", 1445 "EGR HCPM - PassThrought bus parity check", 1446 "EGR PMOD - PassThrought bus parity check", 1447 "EGR FPPARS - PassThrought bus parity check", 1448 "EFP - PassThrought bus parity check", 1449 }; 1450 /*Variables for MMU recovery*/ 1451 1452 int _soc_prev_port_speeds[SOC_MAX_PHY_PORTS]; 1453 1454 uint8 *_soc_tr3_base_index_tbl[SOC_MAX_NUM_DEVICES]; 1455 uint8 *_soc_tr3_chfc_sysport_mapping[SOC_MAX_NUM_DEVICES]; 1456 uint8 *_soc_tr3_ctr_color_drop[SOC_MAX_NUM_DEVICES]; 1457 uint8 *_soc_tr3_ctr_mc_drop[SOC_MAX_NUM_DEVICES]; 1458 uint8 *_soc_tr3_ctr_uc_drop[SOC_MAX_NUM_DEVICES]; 1459 uint8 *_soc_tr3_fc_map_tbl0[SOC_MAX_NUM_DEVICES]; 1460 uint8 *_soc_tr3_fc_map_tbl1[SOC_MAX_NUM_DEVICES]; 1461 uint8 *_soc_tr3_fc_map_tbl2[SOC_MAX_NUM_DEVICES]; 1462 uint8 *_soc_tr3_fc_st_tbl0[SOC_MAX_NUM_DEVICES]; 1463 uint8 *_soc_tr3_fc_st_tbl1[SOC_MAX_NUM_DEVICES]; 1464 uint8 *_soc_tr3_fc_st_tbl2[SOC_MAX_NUM_DEVICES]; 1465 uint8 *_soc_tr3_intfo_tc2pri_mapping[SOC_MAX_NUM_DEVICES]; 1466 uint8 *_soc_tr3_ipmc_vlan[SOC_MAX_NUM_DEVICES]; 1467 uint8 *_soc_tr3_lls_l0_child_weight_cfg[SOC_MAX_NUM_DEVICES]; 1468 uint8 *_soc_tr3_lls_l0_config[SOC_MAX_NUM_DEVICES]; 1469 uint8 *_soc_tr3_lls_l0_parent[SOC_MAX_NUM_DEVICES]; 1470 uint8 *_soc_tr3_lls_l1_child_weight_cfg[SOC_MAX_NUM_DEVICES]; 1471 uint8 *_soc_tr3_lls_l1_config[SOC_MAX_NUM_DEVICES]; 1472 uint8 *_soc_tr3_lls_l1_parent[SOC_MAX_NUM_DEVICES]; 1473 uint8 *_soc_tr3_lls_l2_child_weight_cfg[SOC_MAX_NUM_DEVICES]; 1474 uint8 *_soc_tr3_lls_l2_parent[SOC_MAX_NUM_DEVICES]; 1475 uint8 *_soc_tr3_lls_port_config[SOC_MAX_NUM_DEVICES]; 1476 uint8 *_soc_tr3_lls_port_tdm[SOC_MAX_NUM_DEVICES]; 1477 uint8 *_soc_tr3_mmu_mtro_config_l0_mem[SOC_MAX_NUM_DEVICES]; 1478 uint8 *_soc_tr3_mmu_mtro_config_l1_mem[SOC_MAX_NUM_DEVICES]; 1479 uint8 *_soc_tr3_mmu_mtro_config_l2_mem[SOC_MAX_NUM_DEVICES]; 1480 uint8 *_soc_tr3_mmu_qcn_cnm_counter[SOC_MAX_NUM_DEVICES]; 1481 uint8 *_soc_tr3_mmu_thdo_offset_qgroup[SOC_MAX_NUM_DEVICES]; 1482 uint8 *_soc_tr3_mmu_thdo_offset_queue[SOC_MAX_NUM_DEVICES]; 1483 uint8 *_soc_tr3_mmu_thdo_q_to_qgrp_map[SOC_MAX_NUM_DEVICES]; 1484 uint8 *_soc_tr3_mmu_wred_drop_curve_profile_0[SOC_MAX_NUM_DEVICES]; 1485 uint8 *_soc_tr3_mmu_wred_drop_curve_profile_1[SOC_MAX_NUM_DEVICES]; 1486 uint8 *_soc_tr3_mmu_wred_drop_curve_profile_2[SOC_MAX_NUM_DEVICES]; 1487 uint8 *_soc_tr3_mmu_wred_drop_curve_profile_3[SOC_MAX_NUM_DEVICES]; 1488 uint8 *_soc_tr3_mmu_wred_drop_curve_profile_4[SOC_MAX_NUM_DEVICES]; 1489 uint8 *_soc_tr3_mmu_wred_drop_curve_profile_5[SOC_MAX_NUM_DEVICES]; 1490 uint8 *_soc_tr3_mmu_wred_uc_queue_config[SOC_MAX_NUM_DEVICES]; 1491 uint8 *_soc_tr3_offset_map_tbl[SOC_MAX_NUM_DEVICES]; 1492 uint8 *_soc_tr3_pfc_st_tbl[SOC_MAX_NUM_DEVICES]; 1493 uint8 *_soc_tr3_qcn_enable[SOC_MAX_NUM_DEVICES]; 1494 uint8 *_soc_tr3_qcn_qfbtb[SOC_MAX_NUM_DEVICES]; 1495 uint8 *_soc_tr3_qcn_sitb[SOC_MAX_NUM_DEVICES]; 1496 uint8 *_soc_tr3_qcn_tbid_tbl[SOC_MAX_NUM_DEVICES]; 1497 uint8 *_soc_tr3_qcn_tov_tbl[SOC_MAX_NUM_DEVICES]; 1498 uint8 *_soc_tr3_repl_group[SOC_MAX_NUM_DEVICES]; 1499 uint8 *_soc_tr3_repl_head[SOC_MAX_NUM_DEVICES]; 1500 uint8 *_soc_tr3_st_trans_tbl[SOC_MAX_NUM_DEVICES]; 1501 uint8 *_soc_tr3_thdi_port_pg_config[SOC_MAX_NUM_DEVICES]; 1502 uint8 *_soc_tr3_thdi_port_sp_config[SOC_MAX_NUM_DEVICES]; 1503 uint8 *_soc_tr3_thdo_port_sp_config[SOC_MAX_NUM_DEVICES]; 1504 uint8 *_soc_tr3_thdo_uc_qgroup_config[SOC_MAX_NUM_DEVICES]; 1505 uint8 *_soc_tr3_thdo_uc_queue_config[SOC_MAX_NUM_DEVICES]; 1506 uint8 *_soc_tr3_wred_port_sp_drop_thd[SOC_MAX_NUM_DEVICES]; 1507 uint8 *_soc_tr3_wred_qgroup_drop_thd[SOC_MAX_NUM_DEVICES]; 1508 uint8 *_soc_tr3_wred_uc_queue_drop_thd_deq[SOC_MAX_NUM_DEVICES]; 1509 uint8 *_soc_tr3_wred_uc_queue_drop_thd_enq[SOC_MAX_NUM_DEVICES]; 1510 uint8 *_soc_tr3_iarb_tdm[SOC_MAX_NUM_DEVICES]; 1511 1512 typedef struct _soc_tr3_mmu_data_s { 1513 uint64 _soc_tr3_bkpmeteringconfig_64[_SOC_TR3_MAX_NUM_LPORTS]; 1514 uint32 _soc_tr3_bst_tracking_config; 1515 uint32 _soc_tr3_bst_tracking_enable; 1516 uint32 _soc_tr3_buffer_cell_limit_sp[4]; 1517 uint32 _soc_tr3_buffer_cell_limit_sp_shared; 1518 uint32 _soc_tr3_cell_reset_limit_offset_sp[4]; 1519 uint32 _soc_tr3_cell_spap_red_offset_sp[4]; 1520 uint32 _soc_tr3_cell_spap_yellow_offset_sp[4]; 1521 uint32 _soc_tr3_cfapbankfull[16]; 1522 uint32 _soc_tr3_cfapbstthrs; 1523 uint32 _soc_tr3_cfapconfig; 1524 uint32 _soc_tr3_cfapfullthreshold; 1525 uint32 _soc_tr3_ch_base_expected; 1526 uint32 _soc_tr3_cntx_aging_limit; 1527 uint32 _soc_tr3_cntx_lru_en; 1528 uint32 _soc_tr3_color_aware; 1529 uint32 _soc_tr3_congestion_state_bytes[4]; 1530 uint64 _soc_tr3_cos_mode_64; 1531 uint32 _soc_tr3_deq_agingmask[_SOC_TR3_MAX_NUM_LPORTS]; 1532 uint64 _soc_tr3_deq_agingmask_cpu_port; 1533 uint32 _soc_tr3_deq_agingmask_rde; 1534 uint64 _soc_tr3_deq_agingmask_ucq_0; 1535 uint64 _soc_tr3_deq_agingmask_ucq_1; 1536 uint64 _soc_tr3_deq_agingmask_ucq_10; 1537 uint64 _soc_tr3_deq_agingmask_ucq_11; 1538 uint64 _soc_tr3_deq_agingmask_ucq_12; 1539 uint64 _soc_tr3_deq_agingmask_ucq_13; 1540 uint64 _soc_tr3_deq_agingmask_ucq_14; 1541 uint64 _soc_tr3_deq_agingmask_ucq_15; 1542 uint64 _soc_tr3_deq_agingmask_ucq_2; 1543 uint64 _soc_tr3_deq_agingmask_ucq_3; 1544 uint64 _soc_tr3_deq_agingmask_ucq_4; 1545 uint64 _soc_tr3_deq_agingmask_ucq_5; 1546 uint64 _soc_tr3_deq_agingmask_ucq_6; 1547 uint64 _soc_tr3_deq_agingmask_ucq_7; 1548 uint64 _soc_tr3_deq_agingmask_ucq_8; 1549 uint64 _soc_tr3_deq_agingmask_ucq_9; 1550 uint32 _soc_tr3_deq_qcn_lb_cos; 1551 uint64 _soc_tr3_drop_byte_cnt_ing_64[_SOC_TR3_MAX_NUM_LPORTS]; 1552 uint64 _soc_tr3_drop_cbp_64; 1553 uint32 _soc_tr3_drop_pkt_cnt_ing[_SOC_TR3_MAX_NUM_LPORTS]; 1554 uint32 _soc_tr3_drop_pkt_cnt_ovq[_SOC_TR3_MAX_NUM_LPORTS]; 1555 uint32 _soc_tr3_e2ecc_hol_en; 1556 uint32 _soc_tr3_e2ecc_max_tx_timer; 1557 uint32 _soc_tr3_e2ecc_min_tx_timer; 1558 uint32 _soc_tr3_e2ecc_tx_enable_bmp[7]; 1559 uint32 _soc_tr3_e2ecc_tx_mode; 1560 uint32 _soc_tr3_e2ecc_tx_ports_num; 1561 uint32 _soc_tr3_e2efc_cnt_attr[64]; 1562 uint32 _soc_tr3_e2efc_cnt_reset_limit[64]; 1563 uint32 _soc_tr3_e2efc_cnt_set_limit[64]; 1564 uint32 _soc_tr3_e2efc_cnt_val[64]; 1565 uint32 _soc_tr3_e2efc_config; 1566 uint32 _soc_tr3_e2efc_ibp_en; 1567 uint32 _soc_tr3_e2efc_max_tx_timer[7]; 1568 uint32 _soc_tr3_e2efc_min_tx_timer[7]; 1569 uint32 _soc_tr3_e2efc_port_mapping_config; 1570 uint32 _soc_tr3_e2efc_rmod_cfg[4]; 1571 uint64 _soc_tr3_e2efc_rx_rmodid_64; 1572 uint32 _soc_tr3_e2efc_rx_rmt_timeout[4]; 1573 uint64 _soc_tr3_e2efc_tx_rmodid_64; 1574 uint64 _soc_tr3_egrmeteringconfig_64[_SOC_TR3_MAX_NUM_LPORTS]; 1575 uint32 _soc_tr3_enq_config; 1576 uint32 _soc_tr3_enq_ctrl_pkt_mode; 1577 uint32 _soc_tr3_global_hdrm_limit; 1578 uint32 _soc_tr3_gmhighbank; 1579 uint32 _soc_tr3_gmlowbank; 1580 uint32 _soc_tr3_gmmemwarmup; 1581 uint64 _soc_tr3_input_port_rx_enable_64; 1582 uint32 _soc_tr3_intfi_cfg; 1583 uint32 _soc_tr3_intfo_fcn_en; 1584 uint32 _soc_tr3_lls_asf_credit_high_threshold_for_ports_32_37; 1585 uint32 _soc_tr3_lls_asf_credit_high_threshold_for_ports_38_43; 1586 uint32 _soc_tr3_lls_asf_credit_high_threshold_for_ports_44_49; 1587 uint32 _soc_tr3_lls_asf_credit_high_threshold_for_ports_50_55; 1588 uint32 _soc_tr3_lls_axp_port_56_cfg_weight; 1589 uint32 _soc_tr3_lls_axp_port_57_cfg_weight; 1590 uint32 _soc_tr3_lls_axp_port_58_cfg_weight; 1591 uint32 _soc_tr3_lls_axp_port_61_cfg_weight; 1592 uint32 _soc_tr3_lls_axp_port_62_cfg_weight; 1593 uint32 _soc_tr3_lls_cfg_err_byte_adjust; 1594 uint32 _soc_tr3_lls_config_sp_min_priority; 1595 uint32 _soc_tr3_lls_config_spare; 1596 uint32 _soc_tr3_lls_config0; 1597 uint32 _soc_tr3_lls_debug_enq_block_on_l0; 1598 uint32 _soc_tr3_lls_debug_enq_block_on_l1; 1599 uint32 _soc_tr3_lls_debug_enq_block_on_l2; 1600 uint32 _soc_tr3_lls_debug_enq_block_on_port; 1601 uint32 _soc_tr3_lls_debug_p_werr_max_sc_reset; 1602 uint32 _soc_tr3_lls_fc_config; 1603 uint32 _soc_tr3_lls_fixed_deq_len; 1604 uint32 _soc_tr3_lls_initr; 1605 uint32 _soc_tr3_lls_pkt_acc_config1; 1606 uint32 _soc_tr3_lls_pkt_acc_config2; 1607 uint32 _soc_tr3_lls_tdm_axp_scheduling; 1608 uint32 _soc_tr3_lls_tdm_cal_cfg; 1609 uint32 _soc_tr3_lls_tdm_opportunistic_spacing; 1610 uint32 _soc_tr3_mcfifo_config; 1611 uint32 _soc_tr3_mcq_config; 1612 uint32 _soc_tr3_mcq_fifo_base_reg[8][10]; 1613 uint32 _soc_tr3_mcq_fifo_base_reg_32_35[4][8]; 1614 uint32 _soc_tr3_mcq_fifo_base_reg_36_39[4][8]; 1615 uint32 _soc_tr3_mcq_fifo_base_reg_48_55[8][10]; 1616 uint32 _soc_tr3_mcq_fifo_base_reg_56[8]; 1617 uint32 _soc_tr3_mcq_fifo_base_reg_cpu[48]; 1618 uint32 _soc_tr3_mcq_fifo_base_reg_passthru[8]; 1619 uint64 _soc_tr3_mem_fail_int_en_64; 1620 /*uint32 _soc_tr3_miscconfig;*/ 1621 uint32 _soc_tr3_mmu_cfg_hsp_config; 1622 uint32 _soc_tr3_mmu_llfc_tx_config_1; 1623 uint32 _soc_tr3_mmu_llfc_tx_config_2; 1624 uint64 _soc_tr3_mmu_qcn_cnm_ctrl_64; 1625 uint32 _soc_tr3_mmu_qcn_cpq_seq[8]; 1626 uint32 _soc_tr3_mmu_to_logic_port_mapping[63]; 1627 uint32 _soc_tr3_mmu_to_phy_port_mapping[63]; 1628 uint32 _soc_tr3_mtp_cos; 1629 uint32 _soc_tr3_mtri_ifg[_SOC_TR3_MAX_NUM_LPORTS]; 1630 uint32 _soc_tr3_mtri_refresh_config; 1631 uint32 _soc_tr3_mtro_refresh_config; 1632 uint64 _soc_tr3_oobfc_channel_base_64; 1633 uint32 _soc_tr3_oobfc_chif_cfg; 1634 uint64 _soc_tr3_oobfc_eng_port_en_64; 1635 uint64 _soc_tr3_oobfc_eng_port_qsel_64; 1636 uint32 _soc_tr3_oobfc_gcs; 1637 uint64 _soc_tr3_oobfc_ing_port_en_64; 1638 uint32 _soc_tr3_oobfc_tx_idle; 1639 uint32 _soc_tr3_oobif_debug; 1640 uint32 _soc_tr3_op_buffer_limit_red_cell[4]; 1641 uint32 _soc_tr3_op_buffer_limit_resume_red_cell[4]; 1642 uint32 _soc_tr3_op_buffer_limit_resume_yellow_cell[4]; 1643 uint32 _soc_tr3_op_buffer_limit_yellow_cell[4]; 1644 uint32 _soc_tr3_op_buffer_shared_limit_cell[4]; 1645 uint32 _soc_tr3_op_buffer_shared_limit_resume_cell[4]; 1646 uint32 _soc_tr3_op_cpu_queue_bst_threshold[_SOC_TR3_MAX_NUM_LPORTS][48]; 1647 uint32 _soc_tr3_op_cpu_queue_bst_threshold_profile[8]; 1648 uint32 _soc_tr3_op_mc_sp_bst_threshold[4]; 1649 uint32 _soc_tr3_op_mcuc_sp_bst_threshold[4]; 1650 uint32 _soc_tr3_op_port_config_cell[_SOC_TR3_MAX_NUM_LPORTS][4]; 1651 uint32 _soc_tr3_op_port_config1_cell[_SOC_TR3_MAX_NUM_LPORTS]; 1652 uint32 _soc_tr3_op_port_limit_color_cell[_SOC_TR3_MAX_NUM_LPORTS][4]; 1653 uint32 _soc_tr3_op_port_limit_resume_color_cell[_SOC_TR3_MAX_NUM_LPORTS][4]; 1654 uint32 _soc_tr3_op_queue_config_cell[_SOC_TR3_MAX_NUM_LPORTS][48]; 1655 uint32 _soc_tr3_op_queue_config1_cell[_SOC_TR3_MAX_NUM_LPORTS][48]; 1656 uint32 _soc_tr3_op_queue_limit_color_cell[_SOC_TR3_MAX_NUM_LPORTS][48]; 1657 uint32 _soc_tr3_op_queue_limit_resume_color_cell[_SOC_TR3_MAX_NUM_LPORTS][48]; 1658 uint32 _soc_tr3_op_queue_reset_offset_cell[_SOC_TR3_MAX_NUM_LPORTS][48]; 1659 uint32 _soc_tr3_op_resume_offset_color_cell_profile[8]; 1660 uint32 _soc_tr3_op_sp_bst_threshold_sel; 1661 uint32 _soc_tr3_op_thr_config; 1662 uint32 _soc_tr3_op_thr_config_plus; 1663 uint32 _soc_tr3_op_uc_port_bst_threshold[8]; 1664 uint32 _soc_tr3_op_uc_qgroup_bst_threshold[8]; 1665 uint32 _soc_tr3_op_uc_queue_bst_threshold[8]; 1666 uint64 _soc_tr3_output_port_rx_enable0_64; 1667 uint32 _soc_tr3_ovq_bubble_size_reg; 1668 uint32 _soc_tr3_ovq_bubble_threshold; 1669 uint32 _soc_tr3_ovq_dft; 1670 uint32 _soc_tr3_ovq_drop_threshold_reg; 1671 uint32 _soc_tr3_ovq_drop_threshold_reset_limit; 1672 uint32 _soc_tr3_ovq_drop_threshold0; 1673 uint32 _soc_tr3_ovq_flowcontrol_threshold; 1674 uint32 _soc_tr3_ovq_linked_list_select; 1675 uint32 _soc_tr3_parity_chk_en; 1676 uint32 _soc_tr3_pktaginglimit0; 1677 uint32 _soc_tr3_pktaginglimit1; 1678 uint32 _soc_tr3_pktagingtimer; 1679 uint32 _soc_tr3_port_max_pkt_size[_SOC_TR3_MAX_NUM_LPORTS]; 1680 uint64 _soc_tr3_port_ovq_pause_enable_64; 1681 uint64 _soc_tr3_port_pause_enable_64; 1682 uint64 _soc_tr3_port_pfc_cfg0; 1683 uint64 _soc_tr3_port_pfc_cfg1; 1684 uint32 _soc_tr3_port_pg_spid[_SOC_TR3_MAX_NUM_LPORTS]; 1685 uint32 _soc_tr3_port_pri_grp0[_SOC_TR3_MAX_NUM_LPORTS]; 1686 uint32 _soc_tr3_port_pri_grp1[_SOC_TR3_MAX_NUM_LPORTS]; 1687 uint32 _soc_tr3_port_pri_xon_enable[_SOC_TR3_MAX_NUM_LPORTS]; 1688 uint32 _soc_tr3_prio2cos_profile[64]; 1689 uint32 _soc_tr3_prio2cos_profile0[16]; 1690 uint32 _soc_tr3_prio2cos_profile1[16]; 1691 uint32 _soc_tr3_prio2cos_profile2[16]; 1692 uint32 _soc_tr3_prio2cos_profile3[16]; 1693 uint32 _soc_tr3_pwr_watch_dog_control_mb; 1694 uint32 _soc_tr3_scqm_qgrp; 1695 uint32 _soc_tr3_src_mod_id[16]; 1696 uint32 _soc_tr3_thdi_bst_profile_thresh_pg_hdrm[8]; 1697 uint32 _soc_tr3_thdi_bst_profile_thresh_pg_shared[8]; 1698 uint32 _soc_tr3_thdi_bst_profile_thresh_port_shared[8]; 1699 uint32 _soc_tr3_thdi_bst_profile_thresh_sp[5]; 1700 uint32 _soc_tr3_thdi_bypass; 1701 uint32 _soc_tr3_thdo_bypass; 1702 uint32 _soc_tr3_thdo_interop_config; 1703 uint32 _soc_tr3_thdo_port_e2ecc_cos_spid[_SOC_TR3_MAX_NUM_LPORTS]; 1704 uint32 _soc_tr3_thdo_rde_sp_select; 1705 uint32 _soc_tr3_thdo_unicast_drop_emirror_cnt; 1706 uint32 _soc_tr3_time_domain; 1707 uint32 _soc_tr3_tx_cnt_config[8]; 1708 uint32 _soc_tr3_ucq_config; 1709 uint32 _soc_tr3_use_sp_shared; 1710 uint32 _soc_tr3_wamu_pg_first_fragment_drop_offset[2]; 1711 uint32 _soc_tr3_wamu_pg_min_cell[2]; 1712 uint32 _soc_tr3_wamu_pg_reset_floor_cell[2]; 1713 uint32 _soc_tr3_wamu_pg_reset_offset_cell[2]; 1714 uint32 _soc_tr3_wamu_pg_shared_limit_cell[2]; 1715 uint32 _soc_tr3_wamu_pool_select; 1716 uint32 _soc_tr3_wamu_pri_grp; 1717 uint32 _soc_tr3_wamudropcnt2berr; 1718 uint32 _soc_tr3_wamudropcntaging; 1719 uint32 _soc_tr3_wamudropcntglbthdipkt; 1720 uint32 _soc_tr3_wamudropcntlen; 1721 uint32 _soc_tr3_wamudropcntlenbyte; 1722 uint32 _soc_tr3_wamudropcntlru; 1723 uint32 _soc_tr3_wamudropcntnolru; 1724 uint32 _soc_tr3_wamudropcntnolrubyte; 1725 uint32 _soc_tr3_wamudropcntthdibyte; 1726 uint32 _soc_tr3_wamudropcntthdipkt; 1727 uint32 _soc_tr3_wamudropcntthdobyte[8]; 1728 uint32 _soc_tr3_wamudropcntthdopkt[8]; 1729 uint32 _soc_tr3_wamudropcnttype; 1730 uint32 _soc_tr3_wamuminlmtpg[2]; 1731 uint32 _soc_tr3_wamuminlmtpktq[8]; 1732 uint32 _soc_tr3_wamurstoffsetcellpg[2]; 1733 uint32 _soc_tr3_wamurstoffsetpktpg[2]; 1734 uint32 _soc_tr3_wamurstoffsetpktq[8]; 1735 uint32 _soc_tr3_wamushrlmtcellpg[2]; 1736 uint32 _soc_tr3_wamushrlmtpktpg[2]; 1737 uint32 _soc_tr3_wamushrlmtpktq[8]; 1738 uint32 _soc_tr3_wamunonfragmcnt; 1739 uint32 _soc_tr3_wamureasmbcnt; 1740 uint32 _soc_tr3_wamuthdbypass; 1741 uint32 _soc_tr3_wamutotalshrlmting; 1742 uint32 _soc_tr3_wamutotalshrlmtpktegr; 1743 uint32 _soc_tr3_wred_refresh_control; 1744 uint32 _soc_tr3_hes_l0_config[_SOC_TR3_MAX_NUM_LPORTS]; 1745 uint32 _soc_tr3_hes_port_config[_SOC_TR3_MAX_NUM_LPORTS]; 1746 uint32 _soc_tr3_hes_q_cosmask[_SOC_TR3_MAX_NUM_LPORTS]; 1747 uint32 _soc_tr3_hes_q_cosweights[_SOC_TR3_MAX_NUM_LPORTS][20]; 1748 uint32 _soc_tr3_hes_q_minsp[_SOC_TR3_MAX_NUM_LPORTS]; 1749 uint32 _soc_tr3_hsp_config; 1750 uint32 _soc_tr3_l0_cosweights[_SOC_TR3_MAX_NUM_LPORTS][10]; 1751 uint32 _soc_tr3_ing_cos_mode[_SOC_TR3_MAX_NUM_LPORTS]; 1752 }_soc_tr3_mmu_data_t; 1753 1754 _soc_tr3_mmu_data_t *_soc_tr3_mmu_data[SOC_MAX_NUM_DEVICES]; 1755 1756 STATIC void 1757 _soc_tr3_print_parity_fifo_details(int unit, uint8 regmem, soc_block_t blk, uint32 sblk, 1758 uint32 address, uint32 stage, uint32 base, 1759 uint32 index, uint32 hwmbase, uint32 hwmbase_ism, 1760 uint32 type, uint8 drop) 1761 { 1762 if (bsl_check(bslLayerSoc, bslSourceCommon, bslSeverityError, unit)) { 1763 switch (type) { 1764 case 0: 1765 LOG_ERROR(BSL_LS_SOC_COMMON, 1766 (BSL_META_U(unit, 1767 "Error in: SOP cell.\n"))); 1768 break; 1769 case 1: 1770 LOG_ERROR(BSL_LS_SOC_COMMON, 1771 (BSL_META_U(unit, 1772 "Error in: MOP cell.\n"))); 1773 break; 1774 case 2: 1775 LOG_ERROR(BSL_LS_SOC_COMMON, 1776 (BSL_META_U(unit, 1777 "Error in: EOP cell.\n"))); 1778 break; 1779 case 3: 1780 LOG_ERROR(BSL_LS_SOC_COMMON, 1781 (BSL_META_U(unit, 1782 "Error in: SBUS transaction.\n"))); 1783 break; 1784 case 4: 1785 LOG_ERROR(BSL_LS_SOC_COMMON, 1786 (BSL_META_U(unit, 1787 "Error in: miscellaneous transaction.\n"))); 1788 break; 1789 default: 1790 LOG_ERROR(BSL_LS_SOC_COMMON, 1791 (BSL_META_U(unit, 1792 "Invalid error reported !!\n"))); 1793 break; 1794 } 1795 LOG_ERROR(BSL_LS_SOC_COMMON, 1796 (BSL_META_U(unit, 1797 "Blk: %d, Address: 0x%08x, base: 0x%x, stage: %d, index: %d\n"), 1798 sblk, address, base, stage, index)); 1799 if (!regmem) { 1800 LOG_VERBOSE(BSL_LS_SOC_COMMON, 1801 (BSL_META_U(unit, 1802 "Mem hwbase: 0x%02x [%s], ISM hwbase: 0x%x\n"), hwmbase, 1803 (hwmbase < 0x35) ? 1804 (SOC_IS_HELIX4(unit) ? _soc_hx4_ser_hwmem_base_info[hwmbase] : 1805 _soc_tr3_ser_hwmem_base_info[hwmbase]) : "--", 1806 (blk == SOC_BLK_ISM) ? hwmbase_ism : 0)); 1807 } 1808 if (drop) { 1809 LOG_ERROR(BSL_LS_SOC_COMMON, 1810 (BSL_META_U(unit, 1811 "SER caused packet drop.\n"))); 1812 } 1813 } 1814 } 1815 1816 STATIC int 1817 _soc_tr3_process_parity_fifo(int unit, soc_block_t blk, char *prefix_str) 1818 { 1819 uint32 reg_val, mask, entry[SOC_MAX_MEM_WORDS]; 1820 soc_reg_t reg = INVALIDr; 1821 soc_mem_t mem; 1822 uint32 sblk = 0, regmem, sbus, drop, ecc_parity, address; 1823 uint32 stage, addrbase, index, hwmbase, hwmbase_ism, type; 1824 uint8 bidx; 1825 char blk_str[10]; 1826 _soc_ser_correct_info_t spci; 1827 1828 switch (blk) { 1829 case SOC_BLK_IPIPE: 1830 mem = ING_SER_FIFOm; 1831 mask = _TR3_IP_TO_CMIC_PERR_INTR; 1832 sal_sprintf(blk_str, "IPIPE"); 1833 break; 1834 case SOC_BLK_EPIPE: 1835 mem = EGR_SER_FIFOm; 1836 mask = 0x00000001; /* SER_FIFO_NON_EMPTYf */ 1837 reg = EGR_INTR_STATUSr; 1838 sal_sprintf(blk_str, "EPIPE"); 1839 break; 1840 case SOC_BLK_ISM: 1841 mem = ISM_SER_FIFOm; 1842 mask = 0x00000002; /* SER_FIFO_NOT_EMPTYf */ 1843 reg = ISM_INTRr; 1844 sal_sprintf(blk_str, "ISM"); 1845 break; 1846 default: return SOC_E_PARAM; 1847 } 1848 1849 do { 1850 SOC_IF_ERROR_RETURN 1851 (soc_mem_pop(unit, mem, MEM_BLOCK_ANY, entry)); 1852 /* process entry */ 1853 if (soc_mem_field32_get(unit, mem, entry, VALIDf)) { 1854 ecc_parity = soc_mem_field32_get(unit, mem, entry, ECC_PARITYf); 1855 regmem = soc_mem_field32_get(unit, mem, entry, MEM_TYPEf); 1856 address = soc_mem_field32_get(unit, mem, entry, ADDRESSf); 1857 stage = soc_mem_field32_get(unit, mem, entry, PIPE_STAGEf); 1858 type = soc_mem_field32_get(unit, mem, entry, INSTRUCTION_TYPEf); 1859 drop = soc_mem_field32_get(unit, mem, entry, DROPf); 1860 SOC_BLOCK_ITER(unit, bidx, blk) { 1861 sblk = SOC_BLOCK2SCH(unit, bidx); 1862 break; 1863 } 1864 LOG_ERROR(BSL_LS_SOC_COMMON, 1865 (BSL_META_U(unit, 1866 "%s\n"), prefix_str)); 1867 if (soc_mem_field32_get(unit, mem, entry, MULTIPLEf)) { 1868 LOG_ERROR(BSL_LS_SOC_COMMON, 1869 (BSL_META_U(unit, 1870 "Multiple: "))); 1871 } 1872 if (regmem) { 1873 LOG_ERROR(BSL_LS_SOC_COMMON, 1874 (BSL_META_U(unit, 1875 "Reg: "))); 1876 } else { 1877 LOG_ERROR(BSL_LS_SOC_COMMON, 1878 (BSL_META_U(unit, 1879 "Mem: "))); 1880 } 1881 sal_memset(&spci, 0, sizeof(spci)); 1882 spci.double_bit = 0; 1883 switch (ecc_parity) { 1884 case 0: 1885 LOG_ERROR(BSL_LS_SOC_COMMON, 1886 (BSL_META_U(unit, 1887 "Parity error..\n"))); 1888 break; 1889 case 1: 1890 LOG_ERROR(BSL_LS_SOC_COMMON, 1891 (BSL_META_U(unit, 1892 "Corrected single bit ECC error..\n"))); 1893 break; 1894 case 2: 1895 LOG_ERROR(BSL_LS_SOC_COMMON, 1896 (BSL_META_U(unit, 1897 "Double or Multiple bit ECC error..\n"))); 1898 spci.double_bit = 1; 1899 break; 1900 default: 1901 LOG_ERROR(BSL_LS_SOC_COMMON, 1902 (BSL_META_U(unit, 1903 "Invalid SER issue !!\n"))); 1904 return SOC_E_INTERNAL; 1905 } 1906 if (regmem == 0) { 1907 /* process mem */ 1908 sbus = soc_mem_field32_get(unit, mem, entry, NON_SBUSf); 1909 addrbase = soc_mem_field32_get(unit, mem, entry, MEMBASEf); 1910 index = soc_mem_field32_get(unit, mem, entry, MEMINDEXf); 1911 hwmbase = soc_mem_field32_get(unit, mem, entry, HWMEMBASEf); 1912 if ((blk == SOC_BLK_IPIPE) && (stage == 14)) { 1913 uint32 address1 = address & 0XFFFFF000; 1914 #if defined(BCM_TRIUMPH3_SUPPORT) 1915 uint32 mask = 0; 1916 if (SOC_IS_TRIUMPH3(unit)) { 1917 /* All Pools 0-15 have same size as pool 0 */ 1918 mask = soc_mem_index_max(unit, 1919 ING_FLEX_CTR_COUNTER_TABLE_0m); 1920 address1 = address & (~mask); 1921 } 1922 #endif 1923 switch (address1) { 1924 /*ING_FLEX_CTR_COUNTER_TABLE_0 -3*/ 1925 case 0x3a804000: 1926 case 0x3a808000: 1927 case 0x3a80c000: 1928 case 0x3a810000: 1929 /*ING_FLEX_CTR_COUNTER_TABLE_4 -7*/ 1930 case 0x3a824000: 1931 case 0x3a828000: 1932 case 0x3a82c000: 1933 case 0x3a830000: 1934 /*ING_FLEX_CTR_COUNTER_TABLE_8 -11*/ 1935 case 0x3a844000: 1936 case 0x3a848000: 1937 case 0x3a84c000: 1938 case 0x3a850000: 1939 /*ING_FLEX_CTR_COUNTER_TABLE_12 -15*/ 1940 case 0x3a884000: 1941 case 0x3a888000: 1942 case 0x3a88c000: 1943 case 0x3a890000: 1944 /*ING_FLEX_CTR_OFFSET_TABLE_0 -3*/ 1945 case 0x3a800000: 1946 case 0x3a801000: 1947 case 0x3a802000: 1948 case 0x3a803000: 1949 /*ING_FLEX_CTR_OFFSET_TABLE_4 -7*/ 1950 case 0x3a820000: 1951 case 0x3a821000: 1952 case 0x3a822000: 1953 case 0x3a823000: 1954 /*ING_FLEX_CTR_OFFSET_TABLE_8 -11*/ 1955 case 0x3a840000: 1956 case 0x3a841000: 1957 case 0x3a842000: 1958 case 0x3a843000: 1959 /*ING_FLEX_CTR_OFFSET_TABLE_12 -15*/ 1960 case 0x3a880000: 1961 case 0x3a881000: 1962 case 0x3a882000: 1963 case 0x3a883000: 1964 #if defined(BCM_TRIUMPH3_SUPPORT) 1965 if (SOC_IS_TRIUMPH3(unit)) { 1966 index &= mask; 1967 } else 1968 #endif 1969 { 1970 index &= 0xfff; 1971 } 1972 break; 1973 default: 1974 break; 1975 } 1976 } 1977 if ((blk == SOC_BLK_EPIPE) && (stage == 10)) { 1978 switch (address & 0XFFFFF000) { 1979 /*EGR_FLEX_CTR_COUNTER_TABLE_0 -7*/ 1980 case 0x2a804000: 1981 case 0x2a808000: 1982 case 0x2a80c000: 1983 case 0x2a810000: 1984 case 0x2a824000: 1985 case 0x2a828000: 1986 case 0x2a82c000: 1987 case 0x2a830000: 1988 /*EGR_FLEX_CTR_OFFSET_TABLE_0 -7*/ 1989 case 0x2a800000: 1990 case 0x2a801000: 1991 case 0x2a802000: 1992 case 0x2a803000: 1993 case 0x2a820000: 1994 case 0x2a821000: 1995 case 0x2a822000: 1996 case 0x2a823000: 1997 index &= 0xfff; 1998 break; 1999 default: 2000 break; 2001 } 2002 } 2003 if (sbus == 0) { 2004 hwmbase_ism = soc_mem_field32_get(unit, mem, entry, HWMEMBASE_ISMf); 2005 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 2006 ecc_parity == 0 ? 2007 SOC_SWITCH_EVENT_DATA_ERROR_PARITY : 2008 SOC_SWITCH_EVENT_DATA_ERROR_ECC, 2009 sblk | SOC_SER_ERROR_DATA_BLK_ADDR_SET, address); 2010 _soc_tr3_print_parity_fifo_details(unit, 0, blk, sblk, 2011 address, stage, addrbase, 2012 index, hwmbase, hwmbase_ism, 2013 type, drop); 2014 spci.flags = SOC_SER_SRC_MEM | SOC_SER_REG_MEM_UNKNOWN; 2015 spci.reg = INVALIDr; 2016 spci.mem = INVALIDm; 2017 spci.blk_type = blk; 2018 spci.sblk = sblk; 2019 spci.addr = address - index; 2020 spci.index = index; 2021 spci.parity_type = ecc_parity ? SOC_PARITY_TYPE_ECC : SOC_PARITY_TYPE_PARITY; 2022 spci.double_bit = (ecc_parity == 2) ? 1 : 0; 2023 (void)soc_ser_correction(unit, &spci); 2024 } else { 2025 LOG_ERROR(BSL_LS_SOC_COMMON, 2026 (BSL_META_U(unit, 2027 "%s SER mem address un-accessable !!\n"), blk_str)); 2028 _soc_tr3_print_parity_fifo_details(unit, 0, blk, sblk, 2029 address, stage, addrbase, 2030 index, hwmbase, 0, 2031 type, drop); 2032 } 2033 } else { 2034 /* process reg */ 2035 sbus = soc_mem_field32_get(unit, mem, entry, NON_SBUSf); 2036 addrbase = soc_mem_field32_get(unit, mem, entry, REGBASEf); 2037 index = soc_mem_field32_get(unit, mem, entry, REGINDEXf); 2038 if (sbus == 0) { 2039 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 2040 ecc_parity == 0 ? 2041 SOC_SWITCH_EVENT_DATA_ERROR_PARITY : 2042 SOC_SWITCH_EVENT_DATA_ERROR_ECC, 2043 sblk | SOC_SER_ERROR_DATA_BLK_ADDR_SET, address); 2044 _soc_tr3_print_parity_fifo_details(unit, 1, blk, sblk, 2045 address, stage, addrbase, 2046 index, 0, 0, type, drop); 2047 spci.flags = SOC_SER_SRC_REG | SOC_SER_REG_MEM_UNKNOWN; 2048 spci.reg = INVALIDr; 2049 spci.mem = INVALIDm; 2050 spci.blk_type = blk; 2051 spci.sblk = sblk; 2052 spci.addr = address; 2053 spci.index = index; 2054 spci.parity_type = ecc_parity ? SOC_PARITY_TYPE_ECC : SOC_PARITY_TYPE_PARITY; 2055 spci.double_bit = (ecc_parity == 2) ? 1 : 0; 2056 (void)soc_ser_correction(unit, &spci); 2057 } else { 2058 LOG_ERROR(BSL_LS_SOC_COMMON, 2059 (BSL_META_U(unit, 2060 "%s SER reg address un-accessable !!\n"), blk_str)); 2061 _soc_tr3_print_parity_fifo_details(unit, 1, blk, sblk, 2062 address, stage, addrbase, 2063 index, 0, 0, type, drop); 2064 } 2065 } 2066 } else { 2067 LOG_ERROR(BSL_LS_SOC_COMMON, 2068 (BSL_META_U(unit, 2069 "Got invalid mem pop from %s !!\n"), 2070 SOC_MEM_NAME(unit, mem))); 2071 } 2072 /* check if any more pending */ 2073 if (reg == INVALIDr) { 2074 /* coverity[result_independent_of_operands] */ 2075 SOC_IF_ERROR_RETURN 2076 (READ_CMIC_CMC0_IRQ_STAT2r(unit, ®_val)); 2077 } else { 2078 SOC_IF_ERROR_RETURN 2079 (soc_reg32_get(unit, reg, REG_PORT_ANY, 0, ®_val)); 2080 } 2081 } while (reg_val & mask); 2082 return SOC_E_NONE; 2083 } 2084 2085 STATIC int 2086 _soc_tr3_parity_process_ecc(int unit, soc_mem_t mem, uint8 force_check, int port, 2087 const _soc_tr3_parity_info_t *info, 2088 char *prefix_str, char *mem_str) 2089 { 2090 _soc_tr3_parity_reg_t reg_entry[2], *reg_ptr; 2091 soc_reg_t reg; 2092 uint8 has_error; 2093 uint32 rval; 2094 uint32 multiple, double_bit, entry_idx, idx; 2095 char *mem_str_ptr; 2096 _soc_ser_correct_info_t spci; 2097 soc_field_t ecc_fields[][5] = { 2098 { ECC_ERRf, DOUBLE_BIT_ERRf, MULTIPLE_ERRf, ENTRY_IDXf, TABLE_IDXf }, 2099 { PARITY_ERRf, DOUBLE_BIT_ERRf, MULTIPLE_ERRf, ENTRY_IDXf, TABLE_IDXf }, 2100 { CTRL_FIFO_ECC_ERRf, CTRL_FIFO_DOUBLE_BIT_ERRf, CTRL_FIFO_MULTIPLE_ERRf, 2101 CTRL_FIFO_ENTRY_IDXf, TABLE_IDXf }, 2102 { DATA_FIFO_ECC_ERRf, DATA_FIFO_DOUBLE_BIT_ERRf, DATA_FIFO_MULTIPLE_ERRf, 2103 DATA_FIFO_ENTRY_IDXf, TABLE_IDXf } 2104 }; 2105 2106 if (info->intr_status_reg != INVALIDr) { 2107 reg_entry[0].reg = info->intr_status_reg; 2108 reg_entry[0].mem_str = NULL; 2109 reg_entry[1].reg = INVALIDr; 2110 reg_ptr = reg_entry; 2111 } else { 2112 return SOC_E_NONE; 2113 } 2114 2115 has_error = FALSE; 2116 for (idx = 0; reg_ptr[idx].reg != INVALIDr; idx++) { 2117 uint8 combo = 0; 2118 soc_field_t *fields = ecc_fields[0]; 2119 reg = reg_ptr[idx].reg; 2120 mem_str_ptr = reg_ptr[idx].mem_str != NULL ? 2121 reg_ptr[idx].mem_str : mem_str; 2122 SOC_IF_ERROR_RETURN 2123 (soc_reg32_get(unit, reg, port, 0, &rval)); 2124 if (!SOC_REG_FIELD_VALID(unit, reg, fields[0])) { 2125 fields = ecc_fields[1]; 2126 } 2127 if (!SOC_REG_FIELD_VALID(unit, reg, fields[0])) { 2128 fields = ecc_fields[2]; 2129 if (info->id) { 2130 fields = ecc_fields[3]; 2131 } 2132 combo = 1; 2133 } 2134 if (soc_reg_field_get(unit, reg, rval, fields[0])) { 2135 uint8 mt = FALSE, ti = 0; 2136 has_error = TRUE; 2137 double_bit = soc_reg_field_get(unit, reg, rval, fields[1]); 2138 multiple = soc_reg_field_get(unit, reg, rval, fields[2]); 2139 entry_idx = soc_reg_field_get(unit, reg, rval, fields[3]); 2140 if (SOC_REG_FIELD_VALID(unit, reg, fields[4])) { 2141 mt = TRUE; 2142 ti = soc_reg_field_get(unit, reg, rval, fields[4]); 2143 } 2144 if (double_bit) { 2145 if (!mt) { 2146 spci.double_bit = 1; 2147 LOG_ERROR(BSL_LS_SOC_COMMON, 2148 (BSL_META_U(unit, 2149 "%s %s entry %d double-bit ECC error\n"), 2150 prefix_str, mem_str_ptr, entry_idx)); 2151 } else { 2152 LOG_ERROR(BSL_LS_SOC_COMMON, 2153 (BSL_META_U(unit, 2154 "%s %s table %d entry %d double-bit ECC error\n"), 2155 prefix_str, mem_str_ptr, ti, entry_idx)); 2156 } 2157 } else { 2158 spci.double_bit = 0; 2159 } 2160 if (!mt && mem != INVALIDm) { 2161 LOG_ERROR(BSL_LS_SOC_COMMON, 2162 (BSL_META_U(unit, 2163 "%s %s entry %d ECC error\n"), 2164 prefix_str, mem_str_ptr, entry_idx)); 2165 sal_memset(&spci, 0, sizeof(spci)); 2166 spci.flags = SOC_SER_SRC_MEM | SOC_SER_REG_MEM_KNOWN; 2167 spci.reg = INVALIDr; 2168 spci.mem = mem; 2169 spci.blk_type = -1; 2170 spci.index = entry_idx; 2171 spci.parity_type = SOC_PARITY_TYPE_ECC; 2172 (void)soc_ser_correction(unit, &spci); 2173 } else { 2174 LOG_ERROR(BSL_LS_SOC_COMMON, 2175 (BSL_META_U(unit, 2176 "%s %s table %d entry %d ECC error\n"), 2177 prefix_str, mem_str_ptr, ti, entry_idx)); 2178 } 2179 if (mem != INVALIDm) { 2180 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 2181 SOC_SWITCH_EVENT_DATA_ERROR_ECC, 2182 mem | SOC_SER_ERROR_DATA_ID_OFFSET_SET, entry_idx); 2183 } else { 2184 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 2185 SOC_SWITCH_EVENT_DATA_ERROR_ECC, 2186 info->enable_field | 2187 SOC_SER_ERROR_DATA_FIELD_ID_OFFSET, entry_idx); 2188 } 2189 if (multiple) { 2190 LOG_ERROR(BSL_LS_SOC_COMMON, 2191 (BSL_META_U(unit, 2192 "%s %s has multiple ECC errors\n"), 2193 prefix_str, mem_str_ptr)); 2194 } 2195 } 2196 /* Clear parity status */ 2197 if (!combo) { 2198 SOC_IF_ERROR_RETURN 2199 (soc_reg32_set(unit, reg, port, 0, 0)); 2200 } else { 2201 soc_reg_field_set(unit, reg, &rval, fields[0], 0); 2202 soc_reg_field_set(unit, reg, &rval, fields[1], 0); 2203 soc_reg_field_set(unit, reg, &rval, fields[2], 0); 2204 SOC_IF_ERROR_RETURN 2205 (soc_reg32_set(unit, reg, port, 0, rval)); 2206 } 2207 } 2208 if (!has_error && !force_check) { 2209 LOG_ERROR(BSL_LS_SOC_COMMON, 2210 (BSL_META_U(unit, 2211 "%s %s ECC hardware inconsistency\n"), 2212 prefix_str, mem_str)); 2213 } 2214 return SOC_E_NONE; 2215 } 2216 2217 STATIC int 2218 _soc_tr3_mmu_parity_stat_clear(int unit) 2219 { 2220 uint32 rval; 2221 2222 SOC_IF_ERROR_RETURN(READ_MISCCONFIGr(unit, &rval)); 2223 soc_reg_field_set(unit, MISCCONFIGr, &rval, PARITY_STAT_CLEARf, 1); 2224 SOC_IF_ERROR_RETURN(WRITE_MISCCONFIGr(unit, rval)); 2225 soc_reg_field_set(unit, MISCCONFIGr, &rval, PARITY_STAT_CLEARf, 0); 2226 SOC_IF_ERROR_RETURN(WRITE_MISCCONFIGr(unit, rval)); 2227 2228 return SOC_E_NONE; 2229 } 2230 2231 STATIC int 2232 _soc_tr3_parity_process_mmu_thdo(int unit, soc_block_t blocktype, 2233 char *prefix_str) 2234 { 2235 uint64 rval64; 2236 uint32 entry_idx, rval_hi, rval_lo; 2237 int i; 2238 _soc_ser_correct_info_t spci; 2239 static const _soc_tr3_parity_mmu_bit_reg_t thdo[] = { 2240 { 0, MMU_THDO_Q_TO_QGRP_MAPm, THDO_Q_TO_QGRP_MAP_ECC_ERROR_ADDRESSr }, 2241 { 1, MMU_THDO_CONFIG_QUEUEm, THDO_CONFIG_QUEUE_ECC_ERROR_ADDRESSr }, 2242 { 2, MMU_THDO_OFFSET_QUEUEm, THDO_OFFSET_QUEUE_ECC_ERROR_ADDRESSr }, 2243 { 3, MMU_THDO_CONFIG_QGROUPm, THDO_CONFIG_QGROUP_ECC_ERROR_ADDRESSr }, 2244 { 4, MMU_THDO_OFFSET_QGROUPm, THDO_OFFSET_QGROUP_ECC_ERROR_ADDRESSr }, 2245 { 5, MMU_THDO_COUNTER_QUEUEm, THDO_COUNTER_QUEUE_ECC_ERROR_ADDRESSr }, 2246 { 6, MMU_THDO_COUNTER_QGROUPm, THDO_COUNTER_QGROUP_ECC_ERROR_ADDRESSr }, 2247 { 7, MMU_THDO_COUNTER_PORTm, THDO_COUNTER_PORT_ECC_ERROR_ADDRESSr }, 2248 { 8, MMU_THDO_BST_QUEUEm, THDO_BST_QUEUE_ECC_ERROR_ADDRESSr }, 2249 { 9, MMU_THDO_BST_QGROUPm, THDO_BST_QGROUP_ECC_ERROR_ADDRESSr }, 2250 { 10, MMU_THDO_BST_PORTm, THDO_BST_PORT_ECC_ERROR_ADDRESSr }, 2251 { 11, MMU_THDO_RESUME_QUEUEm, THDO_RESUME_QUEUE_ECC_ERROR_ADDRESSr }, 2252 { 12, MMU_THDO_RESUME_QGROUPm, THDO_RESUME_QGROUP_ECC_ERROR_ADDRESSr }, 2253 { 13, MMU_THDO_CONFIG_PORTm, THDO_CONFIG_PORT_ECC_ERROR_ADDRESSr }, 2254 { 14, MMU_THDO_Q_TO_QGRP_MAPm, THDO_Q_TO_QGRP_MAP_ECC_ERROR_ADDRESSr }, 2255 { 15, MMU_THDO_CONFIG_QUEUEm, THDO_CONFIG_QUEUE_ECC_ERROR_ADDRESSr }, 2256 { 16, MMU_THDO_OFFSET_QUEUEm, THDO_OFFSET_QUEUE_ECC_ERROR_ADDRESSr }, 2257 { 17, MMU_THDO_CONFIG_QGROUPm, THDO_CONFIG_QGROUP_ECC_ERROR_ADDRESSr }, 2258 { 18, MMU_THDO_OFFSET_QGROUPm, THDO_OFFSET_QGROUP_ECC_ERROR_ADDRESSr }, 2259 { 19, MMU_THDO_COUNTER_QUEUEm, THDO_COUNTER_QUEUE_ECC_ERROR_ADDRESSr }, 2260 { 20, MMU_THDO_COUNTER_QGROUPm, THDO_COUNTER_QGROUP_ECC_ERROR_ADDRESSr }, 2261 { 21, MMU_THDO_COUNTER_PORTm, THDO_COUNTER_PORT_ECC_ERROR_ADDRESSr }, 2262 { 22, MMU_THDO_BST_QUEUEm, THDO_BST_QUEUE_ECC_ERROR_ADDRESSr }, 2263 { 23, MMU_THDO_BST_QGROUPm, THDO_BST_QGROUP_ECC_ERROR_ADDRESSr }, 2264 { 24, MMU_THDO_BST_PORTm, THDO_BST_PORT_ECC_ERROR_ADDRESSr }, 2265 { 25, MMU_THDO_RESUME_QUEUEm, THDO_RESUME_QUEUE_ECC_ERROR_ADDRESSr }, 2266 { 26, MMU_THDO_RESUME_QGROUPm, THDO_RESUME_QGROUP_ECC_ERROR_ADDRESSr }, 2267 { 27, MMU_THDO_CONFIG_PORTm, THDO_CONFIG_PORT_ECC_ERROR_ADDRESSr } 2268 }; 2269 2270 SOC_IF_ERROR_RETURN(READ_THDO_PARITY_ERROR_STATUS_64r(unit, &rval64)); 2271 rval_hi = COMPILER_64_HI(rval64); 2272 rval_lo = COMPILER_64_LO(rval64); 2273 for (i = 0; i < COUNTOF(thdo); i++) { 2274 if (thdo[i].bit_pos < 32) { 2275 if (!(rval_lo & (1 << thdo[i].bit_pos))) { 2276 continue; 2277 } 2278 } else { 2279 if (!(rval_hi & (1 << (thdo[i].bit_pos - 32)))) { 2280 continue; 2281 } 2282 } 2283 entry_idx = soc_reg_field_get(unit, thdo[i].addr_reg, 2284 (thdo[i].bit_pos < 32) ? rval_lo : rval_hi, 2285 ADDRESSf); 2286 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 2287 SOC_SWITCH_EVENT_DATA_ERROR_ECC, 2288 thdo[i].mem | SOC_SER_ERROR_DATA_ID_OFFSET_SET, entry_idx); 2289 LOG_ERROR(BSL_LS_SOC_COMMON, 2290 (BSL_META_U(unit, 2291 "%s %s %s ECC error, entry: %d\n"), prefix_str, 2292 SOC_MEM_NAME(unit, thdo[i].mem), i < 14 ? "2B" : "1B", 2293 entry_idx)); 2294 if (i >= 14) { 2295 sal_memset(&spci, 0, sizeof(spci)); 2296 spci.flags = SOC_SER_SRC_MEM | SOC_SER_REG_MEM_KNOWN; 2297 spci.reg = INVALIDr; 2298 spci.mem = thdo[i].mem; 2299 spci.blk_type = blocktype; 2300 spci.index = entry_idx; 2301 (void)soc_ser_correction(unit, &spci); 2302 } 2303 } 2304 /* Clear parity status */ 2305 COMPILER_64_ZERO(rval64); 2306 SOC_IF_ERROR_RETURN(WRITE_THDO_PARITY_ERROR_STATUS_64r(unit, rval64)); 2307 2308 SOC_IF_ERROR_RETURN(_soc_tr3_mmu_parity_stat_clear(unit)); 2309 2310 return SOC_E_NONE; 2311 } 2312 2313 STATIC int 2314 _soc_tr3_parity_process_mmu_thdi(int unit, soc_block_t blocktype, 2315 char *prefix_str) 2316 { 2317 uint64 rval64; 2318 uint32 entry_idx, rval_hi, rval_lo; 2319 int i; 2320 _soc_ser_correct_info_t spci; 2321 static const _soc_tr3_parity_mmu_bit_fld_t thdi0[] = { 2322 { 63, THDI_PORT_PG_CNTRSm, PORT_PG_CNTR_ADDRf }, 2323 { 62, THDI_PORT_SP_CNTRSm, PORT_SP_CNTR_ADDRf }, 2324 { 61, THDI_PORT_PG_CONFIGm, PORT_PG_CFG_ADDRf }, 2325 { 60, THDI_PORT_SP_CONFIGm, PORT_SP_CFG_ADDRf }, 2326 { 59, THDI_PORT_PG_CNTRSm, PORT_PG_CNTR_ADDRf }, 2327 { 58, THDI_PORT_SP_CNTRSm, PORT_SP_CNTR_ADDRf }, 2328 { 57, THDI_PORT_PG_CONFIGm, PORT_PG_CFG_ADDRf }, 2329 { 56, THDI_PORT_SP_CONFIGm, PORT_SP_CFG_ADDRf } 2330 }; 2331 static const _soc_tr3_parity_mmu_bit_fld_t thdi1[] = { 2332 { 25, THDI_PORT_PG_BSTm, PORT_PG_BST_ADDRf }, 2333 { 24, THDI_PORT_SP_BSTm, PORT_SP_BST_ADDRf } 2334 }; 2335 2336 SOC_IF_ERROR_RETURN(READ_PARITY_ERROR_STATUS_0_64r(unit, &rval64)); 2337 rval_hi = COMPILER_64_HI(rval64); 2338 rval_lo = COMPILER_64_LO(rval64); 2339 for (i = 0; i < COUNTOF(thdi0); i++) { 2340 if (thdi0[i].bit_pos < 32) { 2341 if (!(rval_lo & (1 << thdi0[i].bit_pos))) { 2342 continue; 2343 } 2344 } else { 2345 if (!(rval_hi & (1 << (thdi0[i].bit_pos - 32)))) { 2346 continue; 2347 } 2348 } 2349 entry_idx = soc_reg64_field32_get(unit, PARITY_ERROR_STATUS_0_64r, rval64, 2350 thdi0[i].idxf); 2351 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 2352 SOC_SWITCH_EVENT_DATA_ERROR_ECC, 2353 thdi0[i].mem | SOC_SER_ERROR_DATA_ID_OFFSET_SET, entry_idx); 2354 LOG_ERROR(BSL_LS_SOC_COMMON, 2355 (BSL_META_U(unit, 2356 "%s %s %s ECC error, entry: %d\n"), prefix_str, 2357 SOC_MEM_NAME(unit, thdi0[i].mem), i > 59 ? "2B" : "1B", 2358 entry_idx)); 2359 if (i <= 59) { 2360 sal_memset(&spci, 0, sizeof(spci)); 2361 spci.flags = SOC_SER_SRC_MEM | SOC_SER_REG_MEM_KNOWN; 2362 spci.reg = INVALIDr; 2363 spci.mem = thdi0[i].mem; 2364 spci.blk_type = blocktype; 2365 spci.index = entry_idx; 2366 (void)soc_ser_correction(unit, &spci); 2367 } 2368 } 2369 /* Clear parity status */ 2370 COMPILER_64_ZERO(rval64); 2371 SOC_IF_ERROR_RETURN(WRITE_PARITY_ERROR_STATUS_0_64r(unit, rval64)); 2372 2373 SOC_IF_ERROR_RETURN(READ_PARITY_ERROR_STATUS_1r(unit, &rval64)); 2374 rval_hi = COMPILER_64_HI(rval64); 2375 rval_lo = COMPILER_64_LO(rval64); 2376 for (i = 0; i < COUNTOF(thdi1); i++) { 2377 if (thdi1[i].bit_pos < 32) { 2378 if (!(rval_lo & (1 << thdi1[i].bit_pos))) { 2379 continue; 2380 } 2381 } else { 2382 if (!(rval_hi & (1 << (thdi1[i].bit_pos - 32)))) { 2383 continue; 2384 } 2385 } 2386 entry_idx = soc_reg64_field32_get(unit, PARITY_ERROR_STATUS_1r, rval64, 2387 thdi1[i].idxf); 2388 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 2389 SOC_SWITCH_EVENT_DATA_ERROR_ECC, 2390 thdi1[i].mem | SOC_SER_ERROR_DATA_ID_OFFSET_SET, entry_idx); 2391 LOG_ERROR(BSL_LS_SOC_COMMON, 2392 (BSL_META_U(unit, 2393 "%s 1B %s ECC error, entry: %d\n"), prefix_str, 2394 SOC_MEM_NAME(unit, thdi1[i].mem), entry_idx)); 2395 sal_memset(&spci, 0, sizeof(spci)); 2396 spci.flags = SOC_SER_SRC_MEM | SOC_SER_REG_MEM_KNOWN; 2397 spci.reg = INVALIDr; 2398 spci.mem = thdi1[i].mem; 2399 spci.blk_type = blocktype; 2400 spci.index = entry_idx; 2401 (void)soc_ser_correction(unit, &spci); 2402 } 2403 /* Clear parity status */ 2404 COMPILER_64_ZERO(rval64); 2405 SOC_IF_ERROR_RETURN(WRITE_PARITY_ERROR_STATUS_1r(unit, rval64)); 2406 2407 SOC_IF_ERROR_RETURN(_soc_tr3_mmu_parity_stat_clear(unit)); 2408 2409 return SOC_E_NONE; 2410 } 2411 2412 STATIC int 2413 _soc_tr3_parity_process_mmu_wred(int unit, soc_block_t blocktype, 2414 soc_reg_t addr_reg, soc_field_t addr_field, 2415 char *prefix_str) 2416 { 2417 uint32 entry_idx, rval, rval1; 2418 int i; 2419 _soc_ser_correct_info_t spci; 2420 static const _soc_tr3_parity_mmu_bit_t wred[] = { 2421 { 14, MMU_WRED_PORT_SP_SHARED_COUNTm }, 2422 { 13, MMU_WRED_QGROUP_SHARED_COUNTm }, 2423 { 12, MMU_WRED_UC_QUEUE_TOTAL_COUNTm }, 2424 { 11, MMU_WRED_PORT_SP_DROP_THDm }, 2425 { 10, MMU_WRED_QGROUP_DROP_THDm }, 2426 { 9, MMU_WRED_UC_QUEUE_DROP_THD_DEQm }, 2427 { 8, MMU_WRED_UC_QUEUE_DROP_THD_ENQm }, 2428 { 7, MMU_WRED_DROP_CURVE_PROFILE_5m }, 2429 { 6, MMU_WRED_DROP_CURVE_PROFILE_4m }, 2430 { 5, MMU_WRED_DROP_CURVE_PROFILE_3m }, 2431 { 4, MMU_WRED_DROP_CURVE_PROFILE_2m }, 2432 { 3, MMU_WRED_DROP_CURVE_PROFILE_1m }, 2433 { 2, MMU_WRED_DROP_CURVE_PROFILE_0m }, 2434 { 1, MMU_WRED_AVG_QSIZEm }, 2435 { 0, MMU_WRED_CONFIGm } 2436 }; 2437 2438 SOC_IF_ERROR_RETURN(READ_WRED_PARITY_ERROR_BITMAPr(unit, &rval)); 2439 for (i = 0; i < COUNTOF(wred); i++) { 2440 if (!(rval & (1 << wred[i].bit_pos))) { 2441 continue; 2442 } 2443 2444 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, addr_reg, REG_PORT_ANY, 0, 2445 &rval1)); 2446 entry_idx = soc_reg_field_get(unit, addr_reg, rval1, addr_field); 2447 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 2448 SOC_SWITCH_EVENT_DATA_ERROR_ECC, 2449 wred[i].mem | SOC_SER_ERROR_DATA_ID_OFFSET_SET, entry_idx); 2450 LOG_ERROR(BSL_LS_SOC_COMMON, 2451 (BSL_META_U(unit, 2452 "%s %s ECC error, entry: %d\n"), prefix_str, 2453 SOC_MEM_NAME(unit, wred[i].mem), 2454 entry_idx)); 2455 sal_memset(&spci, 0, sizeof(spci)); 2456 spci.flags = SOC_SER_SRC_MEM | SOC_SER_REG_MEM_KNOWN; 2457 spci.reg = INVALIDr; 2458 spci.mem = wred[i].mem; 2459 spci.blk_type = blocktype; 2460 spci.index = entry_idx; 2461 (void)soc_ser_correction(unit, &spci); 2462 } 2463 SOC_IF_ERROR_RETURN(WRITE_WRED_PARITY_ERROR_BITMAPr(unit, 0)); 2464 2465 SOC_IF_ERROR_RETURN(_soc_tr3_mmu_parity_stat_clear(unit)); 2466 2467 return SOC_E_NONE; 2468 } 2469 2470 STATIC int 2471 _soc_tr3_parity_process_mmu_qcn(int unit, soc_block_t blocktype, 2472 soc_reg_t info_addr_reg, soc_field_t addr_field, 2473 char *prefix_str) 2474 { 2475 uint32 entry_idx, rval; 2476 int i; 2477 _soc_ser_correct_info_t spci; 2478 static const _soc_tr3_parity_mmu_bit_t qcn[] = { 2479 { 16, MMU_QCN_QLEN_SHADOWm }, 2480 { 15, MMU_QCN_QFBTBm }, 2481 { 14, MMU_QCN_CPQST_TSSLSm }, 2482 { 13, MMU_QCN_CPQST_QLENm }, 2483 { 12, MMU_QCN_ENABLEm }, 2484 { 11, MMU_QCN_CNM_QUEUEm }, 2485 { 10, MMU_QCN_CNM_COUNTERm } 2486 }; 2487 2488 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, info_addr_reg, REG_PORT_ANY, 0, 2489 &rval)); 2490 for (i = 0; i < COUNTOF(qcn); i++) { 2491 if (!(rval & (1 << qcn[i].bit_pos))) { 2492 continue; 2493 } 2494 entry_idx = soc_reg_field_get(unit, info_addr_reg, rval, addr_field); 2495 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 2496 SOC_SWITCH_EVENT_DATA_ERROR_ECC, 2497 qcn[i].mem | SOC_SER_ERROR_DATA_ID_OFFSET_SET, entry_idx); 2498 LOG_ERROR(BSL_LS_SOC_COMMON, 2499 (BSL_META_U(unit, 2500 "%s %s ECC error, entry: %d\n"), prefix_str, 2501 SOC_MEM_NAME(unit, qcn[i].mem), 2502 entry_idx)); 2503 sal_memset(&spci, 0, sizeof(spci)); 2504 spci.flags = SOC_SER_SRC_MEM | SOC_SER_REG_MEM_KNOWN; 2505 spci.reg = INVALIDr; 2506 spci.mem = qcn[i].mem; 2507 spci.blk_type = blocktype; 2508 spci.index = entry_idx; 2509 (void)soc_ser_correction(unit, &spci); 2510 } 2511 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, info_addr_reg, REG_PORT_ANY, 0, 0)); 2512 2513 SOC_IF_ERROR_RETURN(_soc_tr3_mmu_parity_stat_clear(unit)); 2514 2515 return SOC_E_NONE; 2516 } 2517 STATIC int 2518 _soc_tr3_parity_process_mmu_mtro(int unit, soc_block_t blocktype, 2519 soc_reg_t info_addr_reg, soc_field_t addr_field, 2520 char *prefix_str) 2521 { 2522 uint32 entry_idx, rval; 2523 int i; 2524 _soc_ser_correct_info_t spci; 2525 static const _soc_tr3_parity_mmu_bit_t mtro[] = { 2526 { 13, MMU_MTRO_L2_MEMm }, 2527 { 12, MMU_MTRO_L1_MEMm }, 2528 { 11, MMU_MTRO_L0_MEMm } 2529 }; 2530 2531 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, info_addr_reg, REG_PORT_ANY, 0, 2532 &rval)); 2533 for (i = 0; i < COUNTOF(mtro); i++) { 2534 if (!(rval & (1 << mtro[i].bit_pos))) { 2535 continue; 2536 } 2537 entry_idx = soc_reg_field_get(unit, info_addr_reg, rval, addr_field); 2538 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 2539 SOC_SWITCH_EVENT_DATA_ERROR_ECC, 2540 mtro[i].mem | SOC_SER_ERROR_DATA_ID_OFFSET_SET, entry_idx); 2541 LOG_ERROR(BSL_LS_SOC_COMMON, 2542 (BSL_META_U(unit, 2543 "%s %s parity error, entry: %d\n"), prefix_str, 2544 SOC_MEM_NAME(unit, mtro[i].mem), entry_idx)); 2545 sal_memset(&spci, 0, sizeof(spci)); 2546 spci.flags = SOC_SER_SRC_MEM | SOC_SER_REG_MEM_KNOWN; 2547 spci.reg = INVALIDr; 2548 spci.mem = mtro[i].mem; 2549 spci.blk_type = blocktype; 2550 spci.index = entry_idx; 2551 (void)soc_ser_correction(unit, &spci); 2552 } 2553 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, info_addr_reg, REG_PORT_ANY, 0, 0)); 2554 2555 SOC_IF_ERROR_RETURN(_soc_tr3_mmu_parity_stat_clear(unit)); 2556 2557 return SOC_E_NONE; 2558 } 2559 2560 STATIC int 2561 _soc_tr3_parity_process_mmu_ovq(int unit, soc_block_t blocktype, 2562 soc_reg_t info_addr_reg, soc_field_t info_addr_field, 2563 char *prefix_str) 2564 { 2565 uint32 entry_idx; 2566 uint64 rval64, zero; 2567 int i; 2568 _soc_ser_correct_info_t spci; 2569 static const _soc_tr3_parity_mmu_bit_t ovq[] = { 2570 { 31, MMU_REPL_GROUPm } 2571 }; 2572 2573 SOC_IF_ERROR_RETURN(soc_reg64_get(unit, info_addr_reg, REG_PORT_ANY, 0, 2574 &rval64)); 2575 for (i = 0; i < COUNTOF(ovq); i++) { 2576 if (!(COMPILER_64_LO(rval64) & (1 << ovq[i].bit_pos))) { 2577 continue; 2578 } 2579 2580 entry_idx = soc_reg64_field32_get(unit, info_addr_reg, rval64, info_addr_field); 2581 2582 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 2583 SOC_SWITCH_EVENT_DATA_ERROR_ECC, 2584 ovq[i].mem | SOC_SER_ERROR_DATA_ID_OFFSET_SET, entry_idx); 2585 LOG_ERROR(BSL_LS_SOC_COMMON, 2586 (BSL_META_U(unit, 2587 "%s %s ECC error, entry: %d\n"), prefix_str, 2588 SOC_MEM_NAME(unit, ovq[i].mem), 2589 entry_idx)); 2590 sal_memset(&spci, 0, sizeof(spci)); 2591 spci.flags = SOC_SER_SRC_MEM | SOC_SER_REG_MEM_KNOWN; 2592 spci.reg = INVALIDr; 2593 spci.mem = ovq[i].mem; 2594 spci.blk_type = blocktype; 2595 spci.index = entry_idx; 2596 (void)soc_ser_correction(unit, &spci); 2597 } 2598 2599 COMPILER_64_ZERO(zero); 2600 SOC_IF_ERROR_RETURN(soc_reg64_set(unit, info_addr_reg, REG_PORT_ANY, 0, zero)); 2601 2602 SOC_IF_ERROR_RETURN(_soc_tr3_mmu_parity_stat_clear(unit)); 2603 2604 return SOC_E_NONE; 2605 } 2606 2607 STATIC int 2608 _soc_tr3_parity_process_mmu_lls(int unit, soc_block_t blocktype, 2609 char *prefix_str) 2610 { 2611 uint32 entry_idx, rval, rval1; 2612 int i; 2613 _soc_ser_correct_info_t spci; 2614 static const _soc_tr3_parity_mmu_bit_reg_fld_t lls[] = { 2615 { 3, LLS_PORT_TDMm, LLS_PORT_TDM_ECC_STATUSr, 2616 DB_PORT_TDM_ECC_ERROR_ADDRESSf, 0 }, 2617 { 2, LLS_PORT_TDMm, LLS_PORT_TDM_ECC_STATUSr, 2618 DB_PORT_TDM_ECC_ERROR_ADDRESSf, 1 }, 2619 { 1, LLS_PORT_WERR_MAX_SCm, LLS_PORT_WERR_MAX_SC_ECC_STATUSr, 2620 DB_PORT_WERR_MAX_SC_ECC_ERROR_ADDRESSf, 0 }, 2621 { 0, LLS_PORT_WERR_MAX_SCm, LLS_PORT_WERR_MAX_SC_ECC_STATUSr, 2622 DB_PORT_WERR_MAX_SC_ECC_ERROR_ADDRESSf, 1 } 2623 }; 2624 static const _soc_tr3_parity_mmu_bit_reg_fld_t lls_l0[] = { 2625 { 23, LLS_L0_CHILD_WEIGHT_WORKINGm, 2626 LLS_L0_CHILD_WEIGHT_WORKING_ECC_STATUSr, 2627 DB_L0_CHILD_WEIGHT_WORKING_ECC_ERROR_ADDRESSf, 0 }, 2628 { 22, LLS_L0_CHILD_WEIGHT_WORKINGm, 2629 LLS_L0_CHILD_WEIGHT_WORKING_ECC_STATUSr, 2630 DB_L0_CHILD_WEIGHT_WORKING_ECC_ERROR_ADDRESSf, 1 }, 2631 { 21, LLS_L0_MIN_NEXTm, LLS_L0_MIN_NEXT_ECC_STATUSr, 2632 DB_L0_MIN_NEXT_ECC_ERROR_ADDRESSf, 0 }, 2633 { 20, LLS_L0_MIN_NEXTm, LLS_L0_MIN_NEXT_ECC_STATUSr, 2634 DB_L0_MIN_NEXT_ECC_ERROR_ADDRESSf, 1 }, 2635 { 19, LLS_L0_PARENTm, LLS_L0_PARENT_ECC_STATUSr, 2636 DB_L0_PARENT_ECC_ERROR_ADDRESSf, 0 }, 2637 { 18, LLS_L0_PARENTm, LLS_L0_PARENT_ECC_STATUSr, 2638 DB_L0_PARENT_ECC_ERROR_ADDRESSf, 1 }, 2639 { 17, LLS_L0_CONFIGm, 2640 LLS_L0_CONFIG_ECC_STATUSr, 2641 DB_L0_CONFIG_ECC_ERROR_ADDRESSf, 0 }, 2642 { 16, LLS_L0_CONFIGm, 2643 LLS_L0_CONFIG_ECC_STATUSr, 2644 DB_L0_CONFIG_ECC_ERROR_ADDRESSf, 1 }, 2645 { 15, LLS_L0_PARENT_STATEm, 2646 LLS_L0_PARENT_STATE_ECC_STATUSr, 2647 DB_L0_PARENT_STATE_ECC_ERROR_ADDRESSf, 0 }, 2648 { 14, LLS_L0_PARENT_STATEm, 2649 LLS_L0_PARENT_STATE_ECC_STATUSr, 2650 DB_L0_PARENT_STATE_ECC_ERROR_ADDRESSf, 1 }, 2651 { 13, LLS_L0_HEADS_TAILSm, 2652 LLS_L0_HEADS_TAILS_ECC_STATUSr, 2653 DB_L0_HEADS_TAILS_ECC_ERROR_ADDRESSf, 0 }, 2654 { 12, LLS_L0_HEADS_TAILSm, 2655 LLS_L0_HEADS_TAILS_ECC_STATUSr, 2656 DB_L0_HEADS_TAILS_ECC_ERROR_ADDRESSf, 1 }, 2657 { 11, LLS_L0_WERR_MAX_SCm, 2658 LLS_L0_WERR_MAX_SC_ECC_STATUSr, 2659 DB_L0_WERR_MAX_SC_ECC_ERROR_ADDRESSf, 0 }, 2660 { 10, LLS_L0_WERR_MAX_SCm, 2661 LLS_L0_WERR_MAX_SC_ECC_STATUSr, 2662 DB_L0_WERR_MAX_SC_ECC_ERROR_ADDRESSf, 1 }, 2663 { 9, LLS_L0_CHILD_STATE1m, 2664 LLS_L0_CHILD_STATE1_ECC_STATUSr, 2665 DB_L0_CHILD_STATE1_ECC_ERROR_ADDRESSf, 0 }, 2666 { 8, LLS_L0_CHILD_STATE1m, 2667 LLS_L0_CHILD_STATE1_ECC_STATUSr, 2668 DB_L0_CHILD_STATE1_ECC_ERROR_ADDRESSf, 1 }, 2669 { 7, LLS_L0_CHILD_WEIGHT_CFGm, 2670 LLS_L0_CHILD_WEIGHT_CFG_ECC_STATUSr, 2671 DB_L0_CHILD_WEIGHT_CFG_ECC_ERROR_ADDRESSf, 0 }, 2672 { 6, LLS_L0_CHILD_WEIGHT_CFGm, 2673 LLS_L0_CHILD_WEIGHT_CFG_ECC_STATUSr, 2674 DB_L0_CHILD_WEIGHT_CFG_ECC_ERROR_ADDRESSf, 1 }, 2675 { 5, LLS_L0_WERR_NEXTm, 2676 LLS_L0_WERR_NEXT_ECC_STATUSr, 2677 DB_L0_WERR_NEXT_ECC_ERROR_ADDRESSf, 0 }, 2678 { 4, LLS_L0_WERR_NEXTm, 2679 LLS_L0_WERR_NEXT_ECC_STATUSr, 2680 DB_L0_WERR_NEXT_ECC_ERROR_ADDRESSf, 1 }, 2681 { 3, LLS_L0_EF_NEXTm, 2682 LLS_L0_EF_NEXT_ECC_STATUSr, 2683 DB_L0_EF_NEXT_ECC_ERROR_ADDRESSf, 0 }, 2684 { 2, LLS_L0_EF_NEXTm, 2685 LLS_L0_EF_NEXT_ECC_STATUSr, 2686 DB_L0_EF_NEXT_ECC_ERROR_ADDRESSf, 1 }, 2687 { 1, LLS_L0_ERRORm, 2688 LLS_L0_ERROR_ECC_STATUSr, 2689 DB_L0_ERROR_ECC_ERROR_ADDRESSf, 0 }, 2690 { 0, LLS_L0_ERRORm, 2691 LLS_L0_ERROR_ECC_STATUSr, 2692 DB_L0_ERROR_ECC_ERROR_ADDRESSf, 1 } 2693 }; 2694 static const _soc_tr3_parity_mmu_bit_reg_fld_t lls_l1[] = { 2695 { 23, LLS_L1_CHILD_WEIGHT_WORKINGm, 2696 LLS_L1_CHILD_WEIGHT_WORKING_ECC_STATUSr, 2697 DB_L1_CHILD_WEIGHT_WORKING_ECC_ERROR_ADDRESSf, 0 }, 2698 { 22, LLS_L1_CHILD_WEIGHT_WORKINGm, 2699 LLS_L1_CHILD_WEIGHT_WORKING_ECC_STATUSr, 2700 DB_L1_CHILD_WEIGHT_WORKING_ECC_ERROR_ADDRESSf, 1 }, 2701 { 21, LLS_L1_MIN_NEXTm, LLS_L1_MIN_NEXT_ECC_STATUSr, 2702 DB_L1_MIN_NEXT_ECC_ERROR_ADDRESSf, 0 }, 2703 { 20, LLS_L1_MIN_NEXTm, LLS_L1_MIN_NEXT_ECC_STATUSr, 2704 DB_L1_MIN_NEXT_ECC_ERROR_ADDRESSf, 1 }, 2705 { 19, LLS_L1_PARENTm, LLS_L1_PARENT_ECC_STATUSr, 2706 DB_L1_PARENT_ECC_ERROR_ADDRESSf, 0 }, 2707 { 18, LLS_L1_PARENTm, LLS_L1_PARENT_ECC_STATUSr, 2708 DB_L1_PARENT_ECC_ERROR_ADDRESSf, 1 }, 2709 { 17, LLS_L1_CONFIGm, 2710 LLS_L1_CONFIG_ECC_STATUSr, 2711 DB_L1_CONFIG_ECC_ERROR_ADDRESSf, 0 }, 2712 { 16, LLS_L1_CONFIGm, 2713 LLS_L1_CONFIG_ECC_STATUSr, 2714 DB_L1_CONFIG_ECC_ERROR_ADDRESSf, 1 }, 2715 { 15, LLS_L1_PARENT_STATEm, 2716 LLS_L1_PARENT_STATE_ECC_STATUSr, 2717 DB_L1_PARENT_STATE_ECC_ERROR_ADDRESSf, 0 }, 2718 { 14, LLS_L1_PARENT_STATEm, 2719 LLS_L1_PARENT_STATE_ECC_STATUSr, 2720 DB_L1_PARENT_STATE_ECC_ERROR_ADDRESSf, 1 }, 2721 { 13, LLS_L1_HEADS_TAILSm, 2722 LLS_L1_HEADS_TAILS_ECC_STATUSr, 2723 DB_L1_HEADS_TAILS_ECC_ERROR_ADDRESSf, 0 }, 2724 { 12, LLS_L1_HEADS_TAILSm, 2725 LLS_L1_HEADS_TAILS_ECC_STATUSr, 2726 DB_L1_HEADS_TAILS_ECC_ERROR_ADDRESSf, 1 }, 2727 { 11, LLS_L1_WERR_MAX_SCm, 2728 LLS_L1_WERR_MAX_SC_ECC_STATUSr, 2729 DB_L1_WERR_MAX_SC_ECC_ERROR_ADDRESSf, 0 }, 2730 { 10, LLS_L1_WERR_MAX_SCm, 2731 LLS_L1_WERR_MAX_SC_ECC_STATUSr, 2732 DB_L1_WERR_MAX_SC_ECC_ERROR_ADDRESSf, 1 }, 2733 { 9, LLS_L1_CHILD_STATE1m, 2734 LLS_L1_CHILD_STATE1_ECC_STATUSr, 2735 DB_L1_CHILD_STATE1_ECC_ERROR_ADDRESSf, 0 }, 2736 { 8, LLS_L1_CHILD_STATE1m, 2737 LLS_L1_CHILD_STATE1_ECC_STATUSr, 2738 DB_L1_CHILD_STATE1_ECC_ERROR_ADDRESSf, 1 }, 2739 { 7, LLS_L1_CHILD_WEIGHT_CFGm, 2740 LLS_L1_CHILD_WEIGHT_CFG_ECC_STATUSr, 2741 DB_L1_CHILD_WEIGHT_CFG_ECC_ERROR_ADDRESSf, 0 }, 2742 { 6, LLS_L1_CHILD_WEIGHT_CFGm, 2743 LLS_L1_CHILD_WEIGHT_CFG_ECC_STATUSr, 2744 DB_L1_CHILD_WEIGHT_CFG_ECC_ERROR_ADDRESSf, 1 }, 2745 { 5, LLS_L1_WERR_NEXTm, 2746 LLS_L1_WERR_NEXT_ECC_STATUSr, 2747 DB_L1_WERR_NEXT_ECC_ERROR_ADDRESSf, 0 }, 2748 { 4, LLS_L1_WERR_NEXTm, 2749 LLS_L1_WERR_NEXT_ECC_STATUSr, 2750 DB_L1_WERR_NEXT_ECC_ERROR_ADDRESSf, 1 }, 2751 { 3, LLS_L1_EF_NEXTm, 2752 LLS_L1_EF_NEXT_ECC_STATUSr, 2753 DB_L1_EF_NEXT_ECC_ERROR_ADDRESSf, 0 }, 2754 { 2, LLS_L1_EF_NEXTm, 2755 LLS_L1_EF_NEXT_ECC_STATUSr, 2756 DB_L1_EF_NEXT_ECC_ERROR_ADDRESSf, 1 }, 2757 { 1, LLS_L1_ERRORm, 2758 LLS_L1_ERROR_ECC_STATUSr, 2759 DB_L1_ERROR_ECC_ERROR_ADDRESSf, 0 }, 2760 { 0, LLS_L1_ERRORm, 2761 LLS_L1_ERROR_ECC_STATUSr, 2762 DB_L1_ERROR_ECC_ERROR_ADDRESSf, 1 } 2763 }; 2764 static const _soc_tr3_parity_mmu_bit_reg_fld_t lls_l2[] = { 2765 { 13, LLS_L2_CHILD_WEIGHT_WORKINGm, 2766 LLS_L2_CHILD_WEIGHT_WORKING_ECC_STATUSr, 2767 DB_L2_CHILD_WEIGHT_WORKING_ECC_ERROR_ADDRESSf, 0 }, 2768 { 12, LLS_L2_CHILD_WEIGHT_WORKINGm, 2769 LLS_L2_CHILD_WEIGHT_WORKING_ECC_STATUSr, 2770 DB_L2_CHILD_WEIGHT_WORKING_ECC_ERROR_ADDRESSf, 1 }, 2771 { 11, LLS_L2_CHILD_STATE1m, 2772 LLS_L2_CHILD_STATE1_ECC_STATUSr, 2773 DB_L2_CHILD_STATE1_ECC_ERROR_ADDRESSf, 0 }, 2774 { 10, LLS_L2_CHILD_STATE1m, 2775 LLS_L2_CHILD_STATE1_ECC_STATUSr, 2776 DB_L2_CHILD_STATE1_ECC_ERROR_ADDRESSf, 1 }, 2777 { 9, LLS_L2_PARENTm, LLS_L2_PARENT_ECC_STATUSr, 2778 DB_L2_PARENT_ECC_ERROR_ADDRESSf, 0 }, 2779 { 8, LLS_L2_PARENTm, LLS_L2_PARENT_ECC_STATUSr, 2780 DB_L2_PARENT_ECC_ERROR_ADDRESSf, 1 }, 2781 { 7, LLS_L2_CHILD_WEIGHT_CFGm, 2782 LLS_L2_CHILD_WEIGHT_CFG_ECC_STATUSr, 2783 DB_L2_CHILD_WEIGHT_CFG_ECC_ERROR_ADDRESSf, 0 }, 2784 { 6, LLS_L2_CHILD_WEIGHT_CFGm, 2785 LLS_L2_CHILD_WEIGHT_CFG_ECC_STATUSr, 2786 DB_L2_CHILD_WEIGHT_CFG_ECC_ERROR_ADDRESSf, 1 }, 2787 { 5, LLS_L2_WERR_NEXTm, 2788 LLS_L2_WERR_NEXT_ECC_STATUSr, 2789 DB_L2_WERR_NEXT_ECC_ERROR_ADDRESSf, 0 }, 2790 { 4, LLS_L2_WERR_NEXTm, 2791 LLS_L2_WERR_NEXT_ECC_STATUSr, 2792 DB_L2_WERR_NEXT_ECC_ERROR_ADDRESSf, 1 }, 2793 { 3, LLS_L2_MIN_NEXTm, 2794 LLS_L2_MIN_NEXT_ECC_STATUSr, 2795 DB_L2_MIN_NEXT_ECC_ERROR_ADDRESSf, 0 }, 2796 { 2, LLS_L2_MIN_NEXTm, 2797 LLS_L2_MIN_NEXT_ECC_STATUSr, 2798 DB_L2_MIN_NEXT_ECC_ERROR_ADDRESSf, 1 }, 2799 { 1, LLS_L2_ERRORm, 2800 LLS_L2_ERROR_ECC_STATUSr, 2801 DB_L2_ERROR_ECC_ERROR_ADDRESSf, 0 }, 2802 { 0, LLS_L2_ERRORm, 2803 LLS_L2_ERROR_ECC_STATUSr, 2804 DB_L2_ERROR_ECC_ERROR_ADDRESSf, 1 } 2805 }; 2806 SOC_IF_ERROR_RETURN(READ_LLS_PORT_ECC_ERRORr(unit, &rval)); 2807 for (i = 0; i < COUNTOF(lls); i++) { 2808 if (!(rval & (1 << lls[i].bit_pos))) { 2809 continue; 2810 } 2811 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, lls[i].addr_reg, REG_PORT_ANY, 0, 2812 &rval1)); 2813 entry_idx = soc_reg_field_get(unit, lls[i].addr_reg, rval1, lls[i].idxf); 2814 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 2815 SOC_SWITCH_EVENT_DATA_ERROR_ECC, 2816 lls[i].mem | SOC_SER_ERROR_DATA_ID_OFFSET_SET, entry_idx); 2817 LOG_ERROR(BSL_LS_SOC_COMMON, 2818 (BSL_META_U(unit, 2819 "%s %s %s ECC error, entry: %d\n"), prefix_str, 2820 SOC_MEM_NAME(unit, lls[i].mem), 2821 lls[i].uncorrectable ? "Uncorrectable" : "Correctable", 2822 entry_idx)); 2823 if (!lls[i].uncorrectable) { 2824 sal_memset(&spci, 0, sizeof(spci)); 2825 spci.flags = SOC_SER_SRC_MEM | SOC_SER_REG_MEM_KNOWN; 2826 spci.reg = INVALIDr; 2827 spci.mem = lls[i].mem; 2828 spci.blk_type = blocktype; 2829 spci.index = entry_idx; 2830 (void)soc_ser_correction(unit, &spci); 2831 } 2832 } 2833 SOC_IF_ERROR_RETURN(WRITE_LLS_PORT_ECC_ERRORr(unit, 0)); 2834 2835 SOC_IF_ERROR_RETURN(READ_LLS_L0_ECC_ERROR1r(unit, &rval)); 2836 for (i = 0; i < COUNTOF(lls_l0); i++) { 2837 if (!(rval & (1 << lls_l0[i].bit_pos))) { 2838 continue; 2839 } 2840 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, lls_l0[i].addr_reg, REG_PORT_ANY, 0, 2841 &rval1)); 2842 entry_idx = soc_reg_field_get(unit, lls_l0[i].addr_reg, rval1, 2843 lls_l0[i].idxf); 2844 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 2845 SOC_SWITCH_EVENT_DATA_ERROR_ECC, 2846 lls_l0[i].mem | SOC_SER_ERROR_DATA_ID_OFFSET_SET, entry_idx); 2847 LOG_ERROR(BSL_LS_SOC_COMMON, 2848 (BSL_META_U(unit, 2849 "%s %s %s ECC error, entry: %d\n"), prefix_str, 2850 SOC_MEM_NAME(unit, lls_l0[i].mem), 2851 lls_l0[i].uncorrectable ? "Uncorrectable" : "Correctable", 2852 entry_idx)); 2853 if (!lls_l0[i].uncorrectable) { 2854 sal_memset(&spci, 0, sizeof(spci)); 2855 spci.flags = SOC_SER_SRC_MEM | SOC_SER_REG_MEM_KNOWN; 2856 spci.reg = INVALIDr; 2857 spci.mem = lls_l0[i].mem; 2858 spci.blk_type = blocktype; 2859 spci.index = entry_idx; 2860 (void)soc_ser_correction(unit, &spci); 2861 } 2862 } 2863 2864 SOC_IF_ERROR_RETURN(WRITE_LLS_L0_ECC_ERROR1r(unit, 0)); 2865 2866 SOC_IF_ERROR_RETURN(READ_LLS_L1_ECC_ERROR1r(unit, &rval)); 2867 for (i = 0; i < COUNTOF(lls_l1); i++) { 2868 if (!(rval & (1 << lls_l1[i].bit_pos))) { 2869 continue; 2870 } 2871 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, lls_l1[i].addr_reg, REG_PORT_ANY, 0, 2872 &rval1)); 2873 entry_idx = soc_reg_field_get(unit, lls_l1[i].addr_reg, rval1, 2874 lls_l1[i].idxf); 2875 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 2876 SOC_SWITCH_EVENT_DATA_ERROR_ECC, 2877 lls_l1[i].mem | SOC_SER_ERROR_DATA_ID_OFFSET_SET, entry_idx); 2878 LOG_ERROR(BSL_LS_SOC_COMMON, 2879 (BSL_META_U(unit, 2880 "%s %s %s ECC error, entry: %d\n"), prefix_str, 2881 SOC_MEM_NAME(unit, lls_l1[i].mem), 2882 lls_l1[i].uncorrectable ? "Uncorrectable" : "Correctable", 2883 entry_idx)); 2884 if (!lls_l1[i].uncorrectable) { 2885 sal_memset(&spci, 0, sizeof(spci)); 2886 spci.flags = SOC_SER_SRC_MEM | SOC_SER_REG_MEM_KNOWN; 2887 spci.reg = INVALIDr; 2888 spci.mem = lls_l1[i].mem; 2889 spci.blk_type = blocktype; 2890 spci.index = entry_idx; 2891 (void)soc_ser_correction(unit, &spci); 2892 } 2893 } 2894 SOC_IF_ERROR_RETURN(WRITE_LLS_L1_ECC_ERROR1r(unit, 0)); 2895 2896 SOC_IF_ERROR_RETURN(READ_LLS_L2_ECC_ERROR1r(unit, &rval)); 2897 for (i = 0; i < COUNTOF(lls_l2); i++) { 2898 if (!(rval & (1 << lls_l2[i].bit_pos))) { 2899 continue; 2900 } 2901 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, lls_l2[i].addr_reg, REG_PORT_ANY, 0, 2902 &rval1)); 2903 entry_idx = soc_reg_field_get(unit, lls_l2[i].addr_reg, rval1, 2904 lls_l2[i].idxf); 2905 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 2906 SOC_SWITCH_EVENT_DATA_ERROR_ECC, 2907 lls_l2[i].mem | SOC_SER_ERROR_DATA_ID_OFFSET_SET, entry_idx); 2908 LOG_ERROR(BSL_LS_SOC_COMMON, 2909 (BSL_META_U(unit, 2910 "%s %s %s ECC error, entry: %d\n"), prefix_str, 2911 SOC_MEM_NAME(unit, lls_l2[i].mem), 2912 lls_l2[i].uncorrectable ? "Uncorrectable" : "Correctable", 2913 entry_idx)); 2914 if (!lls_l2[i].uncorrectable) { 2915 sal_memset(&spci, 0, sizeof(spci)); 2916 spci.flags = SOC_SER_SRC_MEM | SOC_SER_REG_MEM_KNOWN; 2917 spci.reg = INVALIDr; 2918 spci.mem = lls_l2[i].mem; 2919 spci.blk_type = blocktype; 2920 spci.index = entry_idx; 2921 (void)soc_ser_correction(unit, &spci); 2922 } 2923 } 2924 SOC_IF_ERROR_RETURN(WRITE_LLS_L2_ECC_ERROR1r(unit, 0)); 2925 2926 SOC_IF_ERROR_RETURN(_soc_tr3_mmu_parity_stat_clear(unit)); 2927 2928 return SOC_E_NONE; 2929 } 2930 2931 static _soc_tr3_bst_hw_cb bst_cb; 2932 2933 STATIC int 2934 _soc_tr3_process_mmu_bst(int unit) 2935 { 2936 if (bst_cb) { 2937 bst_cb(unit); 2938 } 2939 return SOC_E_NONE; 2940 } 2941 2942 int soc_tr3_set_bst_callback(int unit, _soc_tr3_bst_hw_cb cb) 2943 { 2944 bst_cb = cb; 2945 return SOC_E_NONE; 2946 } 2947 2948 static int 2949 _soc_tr3_process_parity(int unit, soc_block_t blocktype, 2950 uint8 blk_id, soc_reg_t reg, 2951 _soc_tr3_parity_info_t *info_list, 2952 char *prefix_str) 2953 { 2954 int port = REG_PORT_ANY, blk_inf_idx; 2955 int info_index, blk; 2956 uint32 rval; 2957 uint64 rval64; 2958 char *mem_str = ""; 2959 _soc_tr3_parity_info_t *info; 2960 char new_prefix_str[80]; 2961 uint8 no_top = 0; 2962 2963 SOC_BLOCK_ITER(unit, blk_inf_idx, blocktype) { 2964 if (SOC_BLOCK_INFO(unit, blk_inf_idx).number == blk_id) { 2965 port = SOC_BLOCK_PORT(unit, blk_inf_idx); 2966 break; 2967 } 2968 } 2969 if (reg != INVALIDr) { 2970 if (SOC_REG_IS_64(unit, reg)) { 2971 SOC_IF_ERROR_RETURN(soc_reg_get(unit, reg, port, 0, &rval64)); 2972 } else { 2973 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, reg, port, 0, &rval)); 2974 } 2975 } else { 2976 no_top = 1; /* No top level status reg, so check all */ 2977 } 2978 /* Loop through each info entry in the list */ 2979 for (info_index = 0; ; info_index++) { 2980 info = &info_list[info_index]; 2981 if (info->type == _SOC_PARITY_TYPE_NONE) { 2982 /* End of table */ 2983 break; 2984 } 2985 if (!no_top) { 2986 if (SOC_REG_IS_64(unit, reg)) { 2987 if (!soc_reg64_field32_get(unit, reg, rval64, 2988 info->group_reg_status_field)) { 2989 continue; 2990 } 2991 } else if (!soc_reg_field_get(unit, reg, rval, 2992 info->group_reg_status_field)) { 2993 continue; 2994 } 2995 } 2996 if (info->mem_str) { 2997 mem_str = info->mem_str; 2998 } 2999 sal_sprintf(new_prefix_str, "%s %s\n", prefix_str, mem_str); 3000 3001 /* Handle different parity error reporting style */ 3002 switch (info->type) { 3003 case _SOC_PARITY_TYPE_GENERIC: 3004 blk = SOC_BLOCK_INFO(unit, blk_inf_idx).cmic; 3005 LOG_ERROR(BSL_LS_SOC_COMMON, 3006 (BSL_META_U(unit, 3007 "%s Blk: %d %s generic parity error.\n"), 3008 prefix_str, blk, mem_str)); 3009 if (info->mem != INVALIDm) { 3010 uint32 entry_idx = 0; 3011 _soc_ser_correct_info_t spci; 3012 3013 if (info->correction_reg != INVALIDr) { 3014 SOC_IF_ERROR_RETURN 3015 (soc_reg32_get(unit, info->correction_reg, REG_PORT_ANY, 0, 3016 &rval)); 3017 entry_idx = soc_reg_field_get(unit, info->correction_reg, 3018 rval, info->correction_addr_field); 3019 } 3020 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 3021 SOC_SWITCH_EVENT_DATA_ERROR_PARITY, 3022 info->mem | SOC_SER_ERROR_DATA_ID_OFFSET_SET, entry_idx); 3023 sal_memset(&spci, 0, sizeof(spci)); 3024 spci.flags = SOC_SER_SRC_MEM | SOC_SER_REG_MEM_KNOWN; 3025 spci.reg = INVALIDr; 3026 spci.mem = info->mem; 3027 spci.blk_type = blocktype; 3028 spci.index = entry_idx; 3029 (void)soc_ser_correction(unit, &spci); 3030 } 3031 break; 3032 case _SOC_PARITY_TYPE_ECC: 3033 /* ECC_ERRf, MULTIPLE_ERRf, DOUBLE_BIT_ERRf, ENTRY_IDXf */ 3034 SOC_IF_ERROR_RETURN 3035 (_soc_tr3_parity_process_ecc(unit, info->mem, no_top ? 1 : 0, 3036 port, info, prefix_str, 3037 mem_str)); 3038 break; 3039 case _SOC_PARITY_TYPE_AXP: 3040 /* nested parity info */ 3041 SOC_IF_ERROR_RETURN 3042 (_soc_tr3_process_parity(unit, blocktype, blk_id, 3043 info->intr_status_reg, info->info, 3044 new_prefix_str)); 3045 break; 3046 case _SOC_PARITY_TYPE_MMU_THDO: 3047 SOC_IF_ERROR_RETURN 3048 (_soc_tr3_parity_process_mmu_thdo(unit, blocktype, new_prefix_str)); 3049 break; 3050 case _SOC_PARITY_TYPE_MMU_THDI: 3051 SOC_IF_ERROR_RETURN 3052 (_soc_tr3_parity_process_mmu_thdi(unit, blocktype, new_prefix_str)); 3053 break; 3054 case _SOC_PARITY_TYPE_MMU_WRED: 3055 SOC_IF_ERROR_RETURN 3056 (_soc_tr3_parity_process_mmu_wred(unit, blocktype, 3057 info->correction_reg, 3058 info->correction_addr_field, 3059 new_prefix_str)); 3060 break; 3061 case _SOC_PARITY_TYPE_MMU_QCN: 3062 SOC_IF_ERROR_RETURN 3063 (_soc_tr3_parity_process_mmu_qcn(unit, blocktype, 3064 info->correction_reg, 3065 info->correction_addr_field, 3066 new_prefix_str)); 3067 break; 3068 case _SOC_PARITY_TYPE_MMU_LLS: 3069 SOC_IF_ERROR_RETURN 3070 (_soc_tr3_parity_process_mmu_lls(unit, blocktype, new_prefix_str)); 3071 break; 3072 case _SOC_PARITY_TYPE_BST: 3073 SOC_IF_ERROR_RETURN(_soc_tr3_process_mmu_bst(unit)); 3074 break; 3075 case _SOC_PARITY_TYPE_MMU_MTRO: 3076 if (info->correction_reg != INVALIDr) { 3077 SOC_IF_ERROR_RETURN 3078 (_soc_tr3_parity_process_mmu_mtro(unit, blocktype, 3079 info->correction_reg, 3080 info->correction_addr_field, 3081 new_prefix_str)); 3082 } else { 3083 return SOC_E_INTERNAL; 3084 } 3085 break; 3086 case _SOC_PARITY_TYPE_MMU_OVQ: 3087 SOC_IF_ERROR_RETURN 3088 (_soc_tr3_parity_process_mmu_ovq(unit, blocktype, 3089 info->correction_reg, 3090 info->correction_addr_field, 3091 new_prefix_str)); 3092 break; 3093 default: 3094 break; 3095 } 3096 } 3097 3098 if (reg != INVALIDr) { 3099 if (SOC_REG_IS_64(unit, reg)) { 3100 sal_memset(&rval64, 0, sizeof(rval64)); 3101 SOC_IF_ERROR_RETURN(soc_reg_set(unit, reg, port, 0, rval64)); 3102 } else { 3103 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, reg, port, 0, 0)); 3104 } 3105 } 3106 3107 return SOC_E_NONE; 3108 } 3109 3110 STATIC int 3111 _soc_tr3_parity_process_all(int unit) 3112 { 3113 uint8 none = 0, rbi; 3114 uint32 rval, cmic_rval1, cmic_rval2, cmic_bit; 3115 const _soc_tr3_parity_route_block_t *rb; 3116 char prefix_str[10]; 3117 soc_stat_t *stat = SOC_STAT(unit); 3118 3119 sal_sprintf(prefix_str, "Unit: %d \n", unit); 3120 3121 /* Read CMIC parity status register */ 3122 /* coverity[result_independent_of_operands] */ 3123 SOC_IF_ERROR_RETURN 3124 (READ_CMIC_CMC0_IRQ_STAT2r(unit, &cmic_rval2)); 3125 if (cmic_rval2 == 0) { 3126 none = 1; 3127 } 3128 /* Read ISM/AXP parity status register */ 3129 /* coverity[result_independent_of_operands] */ 3130 SOC_IF_ERROR_RETURN 3131 (READ_CMIC_CMC0_IRQ_STAT1r(unit, &cmic_rval1)); 3132 if (((cmic_rval1 & _SOC_TR3_FUNC_PARITY_INTR_MASK) == 0) && (none)) { 3133 return SOC_E_NONE; 3134 } 3135 /* Loop through each place-and-route block entry */ 3136 for (rbi = 0; ; rbi++) { 3137 rb = SOC_IS_HELIX4(unit) ? &_soc_hx4_parity_route_blocks[rbi]: 3138 &_soc_tr3_parity_route_blocks[rbi]; 3139 cmic_bit = rb->cmic_bit; 3140 if (cmic_bit == 0) { 3141 /* End of table */ 3142 break; 3143 } 3144 /* Check status for the route block in the CMIC register */ 3145 if (rb->cmic_reg == 0) { 3146 if (!(cmic_rval2 & cmic_bit)) { 3147 /* No interrupt bit asserted for the route block */ 3148 continue; 3149 } 3150 } 3151 if (rb->cmic_reg == 1) { 3152 if (!(cmic_rval1 & cmic_bit)) { 3153 /* No interrupt bit asserted for the route block */ 3154 continue; 3155 } 3156 } 3157 if (rb->blocktype == SOC_BLK_IPIPE || rb->blocktype == SOC_BLK_EPIPE || 3158 rb->blocktype == SOC_BLK_ISM) { 3159 if (rb->blocktype == SOC_BLK_IPIPE) { 3160 if (READ_IP2_INTR_STATUS_2r(unit, &rval)) { 3161 LOG_ERROR(BSL_LS_SOC_COMMON, 3162 (BSL_META_U(unit, 3163 "unit %d: Error reading %s reg !!\n"), 3164 unit, SOC_REG_NAME(unit, IP2_INTR_STATUS_2r))); 3165 return SOC_E_INTERNAL; 3166 } 3167 if (rval) { 3168 /* Call OAM interrupt handler */ 3169 soc_tr3_oam_interrupt_process(unit); 3170 } 3171 } 3172 /* New fifo style processing */ 3173 (void)_soc_tr3_process_parity_fifo(unit, rb->blocktype, prefix_str); 3174 stat->ser_err_fifo++; 3175 } else { 3176 /* Legacy processing */ 3177 (void)_soc_tr3_process_parity(unit, rb->blocktype, rb->id, 3178 rb->status_reg, rb->info, 3179 prefix_str); 3180 stat->ser_err_int++; 3181 } 3182 } 3183 return SOC_E_NONE; 3184 } 3185 3186 void 3187 soc_tr3_process_func_intr(void *unit_vp, void *d1, void *d2, void *d3, void *d4) 3188 { 3189 int unit = PTR_TO_INT(unit_vp); 3190 uint32 rval; 3191 3192 if (soc_feature(unit, soc_feature_l2_overflow)) { 3193 if (READ_ISM_INTRr(unit, &rval)) { 3194 LOG_ERROR(BSL_LS_SOC_COMMON, 3195 (BSL_META_U(unit, 3196 "unit %d: Error reading %s reg !!\n"), 3197 unit, SOC_REG_NAME(unit, ISM_INTRr))); 3198 return; 3199 } 3200 3201 if (soc_reg_field_get(unit, ISM_INTRr, rval, L2_LEARN_INSERT_FAILUREf) && SOC_CONTROL(unit)->l2_overflow_active) { 3202 soc_tr3_l2_overflow_interrupt_handler(unit); 3203 } else { 3204 (void)_soc_tr3_parity_process_all(unit); 3205 } 3206 } else { 3207 (void)_soc_tr3_parity_process_all(unit); 3208 } 3209 sal_usleep(SAL_BOOT_QUICKTURN ? 100000 : 1000); /* Don't reenable too soon */ 3210 #ifdef BCM_CMICM_SUPPORT 3211 if (soc_feature(unit, soc_feature_cmicm)) { 3212 if (d1 != NULL) { 3213 (void)soc_cmicm_intr1_enable(unit, PTR_TO_INT(d1)); 3214 } else if (d2 != NULL) { 3215 (void)soc_cmicm_intr2_enable(unit, PTR_TO_INT(d2)); 3216 } 3217 } 3218 #endif 3219 } 3220 3221 int 3222 _soc_triumph3_mem_parity_control(int unit, soc_mem_t mem, 3223 int copyno, int enable) 3224 { 3225 uint32 parity_enable, intfo_dis = 0, llsfc_cfg, aac2, mscfg; 3226 uint16 dev_id; 3227 uint8 rev_id; 3228 3229 soc_cm_get_id(unit, &dev_id, &rev_id); 3230 3231 3232 3233 /* Do the following toggles even if the memory is invalid, 3234 * so the register tests can use this routine. */ 3235 SOC_IF_ERROR_RETURN(READ_AUX_ARB_CONTROL_2r(unit, &aac2)); 3236 3237 if (!enable) { 3238 /* Disable HW updates */ 3239 soc_reg_field_set(unit, INTFO_HW_UPDATE_DISr, &intfo_dis, 3240 EG_SPf, 1); 3241 soc_reg_field_set(unit, INTFO_HW_UPDATE_DISr, &intfo_dis, 3242 ING_SPf, 1); 3243 soc_reg_field_set(unit, INTFO_HW_UPDATE_DISr, &intfo_dis, 3244 CONGST_STf, 1); 3245 SOC_IF_ERROR_RETURN(WRITE_INTFO_HW_UPDATE_DISr(unit, intfo_dis)); 3246 3247 SOC_IF_ERROR_RETURN 3248 (soc_reg_field32_modify(unit, INTFI_CFGr, REG_PORT_ANY, 3249 PFC_ST_TBL_DISABLEf, 1)); 3250 3251 SOC_IF_ERROR_RETURN(READ_LLS_FC_CONFIGr(unit, &llsfc_cfg)); 3252 soc_reg_field_set(unit, LLS_FC_CONFIGr, &llsfc_cfg, 3253 FC_CFG_DISABLE_XOFFf, 1); 3254 soc_reg_field_set(unit, LLS_FC_CONFIGr, &llsfc_cfg, 3255 FC_CFG_DISABLE_ALL_XOFFf, 1); 3256 soc_reg_field_set(unit, LLS_FC_CONFIGr, &llsfc_cfg, 3257 FC_CFG_DISABLE_L2_COSMASK_XOFFf, 1); 3258 SOC_IF_ERROR_RETURN(WRITE_LLS_FC_CONFIGr(unit, llsfc_cfg)); 3259 3260 SOC_IF_ERROR_RETURN 3261 (soc_reg_field32_modify(unit, 3262 IFP_METER_WRITE_LAST_REFRESH_NUMBERr, 3263 REG_PORT_ANY, WRITE_ENf, 1)); 3264 SOC_IF_ERROR_RETURN 3265 (soc_reg_field32_modify(unit, 3266 ING_SVM_CONTROLr, REG_PORT_ANY, 3267 DISABLE_CPU_WRITE_TO_LAST_REFRESH_NUMBERf, 0)); 3268 3269 /* Refresh disables */ 3270 soc_reg_field_set(unit, AUX_ARB_CONTROL_2r, &aac2, 3271 DLB_1US_TICK_ENABLEf, 0); 3272 soc_reg_field_set(unit, AUX_ARB_CONTROL_2r, &aac2, 3273 STORM_CONTROL_REFRESH_ENABLEf, 0); 3274 soc_reg_field_set(unit, AUX_ARB_CONTROL_2r, &aac2, 3275 SVC_MTR_REFRESH_ENABLEf, 0); 3276 soc_reg_field_set(unit, AUX_ARB_CONTROL_2r, &aac2, 3277 OAM_REFRESH_ENABLEf, 0); 3278 soc_reg_field_set(unit, AUX_ARB_CONTROL_2r, &aac2, 3279 DLB_REFRESH_ENABLEf, 0); 3280 soc_reg_field_set(unit, AUX_ARB_CONTROL_2r, &aac2, 3281 FT_REFRESH_ENABLEf, 0); 3282 soc_reg_field_set(unit, AUX_ARB_CONTROL_2r, &aac2, 3283 IPFIX_REFRESH_ENABLEf, 0); 3284 soc_reg_field_set(unit, AUX_ARB_CONTROL_2r, &aac2, 3285 FP_REFRESH_ENABLEf, 0); 3286 SOC_IF_ERROR_RETURN(WRITE_AUX_ARB_CONTROL_2r(unit, aac2)); 3287 } 3288 3289 parity_enable = soc_property_get(unit, spn_PARITY_ENABLE, TRUE); 3290 if (parity_enable) { 3291 (void)_soc_tr3_parity_enable_all(unit, enable); 3292 } else { 3293 SOC_IF_ERROR_RETURN(READ_MISCCONFIGr(unit, &mscfg)); 3294 soc_reg_field_set(unit, MISCCONFIGr, &mscfg, PARITY_STAT_CLEARf, 1); 3295 SOC_IF_ERROR_RETURN(WRITE_MISCCONFIGr(unit, mscfg)); 3296 if (enable) { 3297 /* MMU enables */ 3298 soc_reg_field_set(unit, MISCCONFIGr, &mscfg, PARITY_CHK_ENf, 1); 3299 soc_reg_field_set(unit, MISCCONFIGr, &mscfg, PARITY_GEN_ENf, 1); 3300 soc_reg_field_set(unit, MISCCONFIGr, &mscfg, PARITY_STAT_CLEARf, 0); 3301 soc_reg_field_set(unit, MISCCONFIGr, &mscfg, METERING_CLK_ENf, 1); 3302 SOC_IF_ERROR_RETURN(WRITE_MISCCONFIGr(unit, mscfg)); 3303 } else { 3304 /* MMU disables */ 3305 soc_reg_field_set(unit, MISCCONFIGr, &mscfg, PARITY_CHK_ENf, 0); 3306 soc_reg_field_set(unit, MISCCONFIGr, &mscfg, PARITY_GEN_ENf, 0); 3307 soc_reg_field_set(unit, MISCCONFIGr, &mscfg, PARITY_STAT_CLEARf, 0); 3308 soc_reg_field_set(unit, MISCCONFIGr, &mscfg, METERING_CLK_ENf, 0); 3309 SOC_IF_ERROR_RETURN(WRITE_MISCCONFIGr(unit, mscfg)); 3310 } 3311 } 3312 3313 if (enable) { 3314 /* Re-enable HW updates */ 3315 SOC_IF_ERROR_RETURN(WRITE_INTFO_HW_UPDATE_DISr(unit, intfo_dis)); 3316 3317 SOC_IF_ERROR_RETURN 3318 (soc_reg_field32_modify(unit, INTFI_CFGr, REG_PORT_ANY, 3319 PFC_ST_TBL_DISABLEf, 0)); 3320 3321 SOC_IF_ERROR_RETURN(READ_LLS_FC_CONFIGr(unit, &llsfc_cfg)); 3322 soc_reg_field_set(unit, LLS_FC_CONFIGr, &llsfc_cfg, 3323 FC_CFG_DISABLE_XOFFf, 0); 3324 soc_reg_field_set(unit, LLS_FC_CONFIGr, &llsfc_cfg, 3325 FC_CFG_DISABLE_ALL_XOFFf, 0); 3326 soc_reg_field_set(unit, LLS_FC_CONFIGr, &llsfc_cfg, 3327 FC_CFG_DISABLE_L2_COSMASK_XOFFf, 0); 3328 SOC_IF_ERROR_RETURN(WRITE_LLS_FC_CONFIGr(unit, llsfc_cfg)); 3329 3330 SOC_IF_ERROR_RETURN 3331 (soc_reg_field32_modify(unit, 3332 IFP_METER_WRITE_LAST_REFRESH_NUMBERr, 3333 REG_PORT_ANY, WRITE_ENf, 0)); 3334 SOC_IF_ERROR_RETURN 3335 (soc_reg_field32_modify(unit, 3336 ING_SVM_CONTROLr, REG_PORT_ANY, 3337 DISABLE_CPU_WRITE_TO_LAST_REFRESH_NUMBERf, 1)); 3338 3339 /* Refresh enables */ 3340 soc_reg_field_set(unit, AUX_ARB_CONTROL_2r, &aac2, 3341 DLB_1US_TICK_ENABLEf, 1); 3342 soc_reg_field_set(unit, AUX_ARB_CONTROL_2r, &aac2, 3343 STORM_CONTROL_REFRESH_ENABLEf, 1); 3344 soc_reg_field_set(unit, AUX_ARB_CONTROL_2r, &aac2, 3345 SVC_MTR_REFRESH_ENABLEf, 1); 3346 soc_reg_field_set(unit, AUX_ARB_CONTROL_2r, &aac2, 3347 OAM_REFRESH_ENABLEf, 1); 3348 soc_reg_field_set(unit, AUX_ARB_CONTROL_2r, &aac2, 3349 DLB_REFRESH_ENABLEf, 1); 3350 soc_reg_field_set(unit, AUX_ARB_CONTROL_2r, &aac2, 3351 FT_REFRESH_ENABLEf, 1); 3352 soc_reg_field_set(unit, AUX_ARB_CONTROL_2r, &aac2, 3353 IPFIX_REFRESH_ENABLEf, 1); 3354 soc_reg_field_set(unit, AUX_ARB_CONTROL_2r, &aac2, 3355 FP_REFRESH_ENABLEf, 1); 3356 SOC_IF_ERROR_RETURN(WRITE_AUX_ARB_CONTROL_2r(unit, aac2)); 3357 } 3358 sal_usleep(SAL_BOOT_QUICKTURN ? 100000 : 1000); /* Allow things to stabalize */ 3359 return SOC_E_NONE; 3360 } 3361 3362 /* SER processing for TCAMs */ 3363 static _soc_ser_parity_info_t _soc_tr3_ser_parity_info_template[] = { 3364 /* EP */ 3365 { EFP_TCAMm, _SOC_SER_PARITY_MODE_4BITS, 3366 CMIC_SER1_START_ADDR_0r, CMIC_SER1_END_ADDR_0r, 3367 CMIC_SER1_MEM_ADDR_0r, CMIC_SER1_PARITY_MODE_SEL_15_0r, 3368 RANGE_0_PARITY_BITSf, 470, CMIC_SER1_RANGE0_DATAENTRY_LENr, 1, 0, 0, 3369 _SOC_SER_FLAG_XY_READ}, 3370 /* IP */ 3371 { FP_TCAMm, _SOC_SER_PARITY_MODE_4BITS, 3372 CMIC_SER0_START_ADDR_1r, CMIC_SER0_END_ADDR_1r, 3373 CMIC_SER0_MEM_ADDR_1r, CMIC_SER0_PARITY_MODE_SEL_15_0r, 3374 RANGE_1_PARITY_BITSf, 470, CMIC_SER0_RANGE1_DATAENTRY_LENr, 0, 0, 0, 3375 _SOC_SER_FLAG_XY_READ}, 3376 { VFP_TCAMm, _SOC_SER_PARITY_MODE_4BITS, 3377 CMIC_SER0_START_ADDR_2r, CMIC_SER0_END_ADDR_2r, 3378 CMIC_SER0_MEM_ADDR_2r, CMIC_SER0_PARITY_MODE_SEL_15_0r, 3379 RANGE_2_PARITY_BITSf, 470, CMIC_SER0_RANGE2_DATAENTRY_LENr, 0, 0, 0, 3380 _SOC_SER_FLAG_XY_READ}, 3381 { FP_UDF_TCAMm, _SOC_SER_PARITY_MODE_2BITS, 3382 CMIC_SER0_START_ADDR_3r, CMIC_SER0_END_ADDR_3r, 3383 CMIC_SER0_MEM_ADDR_3r, CMIC_SER0_PARITY_MODE_SEL_15_0r, 3384 RANGE_3_PARITY_BITSf, 161, CMIC_SER0_RANGE3_DATAENTRY_LENr, 0, 0, 0, 3385 _SOC_SER_FLAG_XY_READ}, 3386 { L3_TUNNELm, _SOC_SER_PARITY_MODE_4BITS, 3387 CMIC_SER0_START_ADDR_4r, CMIC_SER0_END_ADDR_4r, 3388 CMIC_SER0_MEM_ADDR_4r, CMIC_SER0_PARITY_MODE_SEL_15_0r, 3389 RANGE_4_PARITY_BITSf, 213, CMIC_SER0_RANGE4_DATAENTRY_LENr, 0, 0, 0, 3390 _SOC_SER_FLAG_XY_READ}, 3391 { VLAN_SUBNETm, _SOC_SER_PARITY_MODE_2BITS, 3392 CMIC_SER0_START_ADDR_5r, CMIC_SER0_END_ADDR_5r, 3393 CMIC_SER0_MEM_ADDR_5r, CMIC_SER0_PARITY_MODE_SEL_15_0r, 3394 RANGE_5_PARITY_BITSf, 129, CMIC_SER0_RANGE5_DATAENTRY_LENr, 0, 0, 0, 3395 _SOC_SER_FLAG_XY_READ}, 3396 { MY_STATION_TCAMm, _SOC_SER_PARITY_MODE_8BITS, 3397 CMIC_SER0_START_ADDR_6r, CMIC_SER0_END_ADDR_6r, 3398 CMIC_SER0_MEM_ADDR_6r, CMIC_SER0_PARITY_MODE_SEL_15_0r, 3399 RANGE_6_PARITY_BITSf, 153, CMIC_SER0_RANGE6_DATAENTRY_LENr, 0, 0, 0, 3400 _SOC_SER_FLAG_XY_READ}, 3401 { L2_USER_ENTRYm, _SOC_SER_PARITY_MODE_4BITS, 3402 CMIC_SER0_START_ADDR_7r, CMIC_SER0_END_ADDR_7r, 3403 CMIC_SER0_MEM_ADDR_7r, CMIC_SER0_PARITY_MODE_SEL_15_0r, 3404 RANGE_7_PARITY_BITSf, 127, CMIC_SER0_RANGE7_DATAENTRY_LENr, 0, 0, 0, 3405 _SOC_SER_FLAG_XY_READ}, 3406 { FP_GLOBAL_MASK_TCAMm, _SOC_SER_PARITY_MODE_2BITS, 3407 CMIC_SER0_START_ADDR_8r, CMIC_SER0_END_ADDR_8r, 3408 CMIC_SER0_MEM_ADDR_8r, CMIC_SER0_PARITY_MODE_SEL_15_0r, 3409 RANGE_8_PARITY_BITSf, 177, CMIC_SER0_RANGE8_DATAENTRY_LENr, 0, 0, 0, 3410 _SOC_SER_FLAG_XY_READ}, 3411 { CPU_COS_MAPm, _SOC_SER_PARITY_MODE_2BITS, 3412 CMIC_SER0_START_ADDR_9r, CMIC_SER0_END_ADDR_9r, 3413 CMIC_SER0_MEM_ADDR_9r, CMIC_SER0_PARITY_MODE_SEL_15_0r, 3414 RANGE_9_PARITY_BITSf, 231, CMIC_SER0_RANGE9_DATAENTRY_LENr, 0, 0, 0, 3415 _SOC_SER_FLAG_XY_READ}, 3416 { ESM_PKT_TYPE_IDm, _SOC_SER_PARITY_MODE_2BITS, 3417 CMIC_SER0_START_ADDR_10r, CMIC_SER0_END_ADDR_10r, 3418 CMIC_SER0_MEM_ADDR_10r, CMIC_SER0_PARITY_MODE_SEL_15_0r, 3419 RANGE_10_PARITY_BITSf, 129, CMIC_SER0_RANGE10_DATAENTRY_LENr, 0, 0, 0, 3420 _SOC_SER_FLAG_XY_READ}, 3421 { L3_DEFIPm, _SOC_SER_PARITY_MODE_2BITS, 3422 CMIC_SER0_START_ADDR_11r, CMIC_SER0_END_ADDR_11r, 3423 CMIC_SER0_MEM_ADDR_11r, CMIC_SER0_PARITY_MODE_SEL_15_0r, 3424 RANGE_11_PARITY_BITSf, 190, CMIC_SER0_RANGE11_DATAENTRY_LENr, 0, 0, 0, 3425 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_SIZE_VERIFY | 3426 _SOC_SER_FLAG_NO_DMA | _SOC_SER_FLAG_REMAP_READ}, 3427 { L3_DEFIP_PAIR_128m, _SOC_SER_PARITY_MODE_2BITS, 3428 CMIC_SER0_START_ADDR_12r, CMIC_SER0_END_ADDR_12r, 3429 CMIC_SER0_MEM_ADDR_12r, CMIC_SER0_PARITY_MODE_SEL_15_0r, 3430 RANGE_12_PARITY_BITSf, 380, CMIC_SER0_RANGE12_DATAENTRY_LENr, 0, 0, 0, 3431 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_SIZE_VERIFY | 3432 _SOC_SER_FLAG_NO_DMA | _SOC_SER_FLAG_REMAP_READ}, 3433 { INVALIDm, _SOC_SER_PARITY_MODE_NUM}, 3434 }; 3435 3436 static _soc_ser_parity_info_t *_soc_tr3_ser_parity_info[SOC_MAX_NUM_DEVICES]; 3437 extern _soc_generic_ser_info_t *_soc_hx4_tcam_ser_info[SOC_MAX_NUM_DEVICES]; 3438 3439 #define SOC_TR3_SER_MEM_AVAILABLE (4096 * 32) /* bits */ 3440 3441 STATIC void 3442 _soc_tr3_ser_info_flag_update(_soc_ser_parity_info_t *ser_info, 3443 soc_mem_t mem, uint32 flag, int enable) 3444 { 3445 int ser_idx = 0; 3446 3447 while (INVALIDm != ser_info[ser_idx].mem) { 3448 if (ser_info[ser_idx].mem == mem) { 3449 if (enable) { 3450 ser_info[ser_idx].ser_flags |= flag; 3451 } else { 3452 ser_info[ser_idx].ser_flags &= ~flag; 3453 } 3454 } 3455 ser_idx++; 3456 } 3457 } 3458 3459 STATIC int 3460 _soc_tr3_ser_init(int unit) 3461 { 3462 _soc_ser_parity_info_t *ser_info; 3463 int alloc_size, ser_idx = 0; 3464 soc_tcam_info_t *tcam_info; 3465 soc_tcam_partition_t *ipv4_defip_partition; 3466 3467 /* First, make per-unit copy of the master TCAM list */ 3468 alloc_size = sizeof(_soc_tr3_ser_parity_info_template); 3469 if (NULL == _soc_tr3_ser_parity_info[unit]) { 3470 if ((_soc_tr3_ser_parity_info[unit] = 3471 sal_alloc(alloc_size, "tr3 tcam list")) == NULL) { 3472 return SOC_E_MEMORY; 3473 } 3474 } 3475 /* Make a fresh copy of the TCAM template info */ 3476 sal_memcpy(_soc_tr3_ser_parity_info[unit], 3477 &(_soc_tr3_ser_parity_info_template), 3478 alloc_size); 3479 3480 /* Now make per-unit modifications */ 3481 ser_info = _soc_tr3_ser_parity_info[unit]; 3482 tcam_info = SOC_CONTROL(unit)->tcam_info; 3483 if (NULL != tcam_info) { 3484 ipv4_defip_partition = &(tcam_info->partitions[ 3485 TCAM_PARTITION_FWD_IP4]); 3486 if (0 != ipv4_defip_partition->num_entries) { 3487 /* No internal DEFIP tables, truncate the TCAM list */ 3488 while (INVALIDm != ser_info[ser_idx].mem) { 3489 if (ser_info[ser_idx].mem == L3_DEFIPm) { 3490 ser_info[ser_idx].mem = INVALIDm; 3491 break; 3492 } 3493 ser_idx++; 3494 } 3495 } 3496 } 3497 3498 if (soc_feature(unit, soc_feature_field_stage_half_slice) || 3499 soc_feature(unit, soc_feature_field_stage_ingress_256_half_slice) || 3500 soc_feature(unit, soc_feature_field_slice_size128) || 3501 soc_feature(unit, soc_feature_field_stage_quarter_slice)) { 3502 _soc_tr3_ser_info_flag_update(ser_info, FP_GLOBAL_MASK_TCAMm, 3503 _SOC_SER_FLAG_NO_DMA, TRUE); 3504 _soc_tr3_ser_info_flag_update(ser_info, FP_TCAMm, 3505 _SOC_SER_FLAG_NO_DMA, TRUE); 3506 } 3507 3508 if (soc_feature(unit, soc_feature_field_stage_half_slice) || 3509 soc_feature(unit, soc_feature_field_stage_egress_256_half_slice) || 3510 soc_feature(unit, soc_feature_field_stage_quarter_slice)) { 3511 _soc_tr3_ser_info_flag_update(ser_info, EFP_TCAMm, 3512 _SOC_SER_FLAG_NO_DMA, TRUE); 3513 } 3514 3515 if (soc_feature(unit, soc_feature_field_stage_lookup_512_half_slice) || 3516 soc_feature(unit, soc_feature_field_stage_quarter_slice)) { 3517 _soc_tr3_ser_info_flag_update(ser_info, VFP_TCAMm, 3518 _SOC_SER_FLAG_NO_DMA, TRUE); 3519 } 3520 3521 return soc_ser_init(unit, ser_info, SOC_TR3_SER_MEM_AVAILABLE); 3522 } 3523 3524 int 3525 soc_tr3_ser_mem_clear(int unit, soc_mem_t mem) 3526 { 3527 return soc_cmicm_ser_mem_clear(unit, 3528 _soc_tr3_ser_parity_info[unit], mem); 3529 } 3530 3531 STATIC void 3532 soc_tr3_ser_fail(int unit) 3533 { 3534 #ifdef BCM_HELIX4_SUPPORT 3535 if (SOC_IS_HELIX4(unit)) { 3536 soc_hx4_ser_fail(unit); 3537 return; 3538 } 3539 #endif /* BCM_HELIX4_SUPPORT */ 3540 soc_process_cmicm_ser_parity_error(unit, _soc_tr3_ser_parity_info[unit], 3541 _SOC_PARITY_TYPE_SER); 3542 return; 3543 } 3544 3545 /* FCOE standard FC header configurations */ 3546 static _soc_fcoe_header_info_t _soc_tr3_fcoe_header_info[] = { 3547 { SOC_FCOE_HDR_TYPE_STD , 0, 7 }, 3548 { SOC_FCOE_HDR_TYPE_STD , 33, 35 }, 3549 { SOC_FCOE_HDR_TYPE_STD , 50, 51 }, 3550 { SOC_FCOE_HDR_TYPE_STD , 64, 71 }, 3551 { SOC_FCOE_HDR_TYPE_VFT , 80, 80 }, 3552 { SOC_FCOE_HDR_TYPE_IFR , 81, 81 }, 3553 { SOC_FCOE_HDR_TYPE_ENCAP, 82, 82 }, 3554 { SOC_FCOE_HDR_TYPE_STD, 128, 134 }, 3555 { SOC_FCOE_HDR_TYPE_STD, 192, 201 }, 3556 }; 3557 3558 STATIC int 3559 _soc_tr3_fcoe_config_init(int unit) 3560 { 3561 int index, rctl, count = COUNTOF(_soc_tr3_fcoe_header_info); 3562 3563 for (index = 0; index < count; index++) { 3564 /* Configure FCOE header for routing control indexes */ 3565 for (rctl = _soc_tr3_fcoe_header_info[index].r_ctl_min; 3566 rctl <= _soc_tr3_fcoe_header_info[index].r_ctl_max; rctl++) { 3567 SOC_IF_ERROR_RETURN( 3568 soc_mem_field32_modify(unit, FC_HEADER_TYPEm, rctl, 3569 FC_HDR_ENCODEf, _soc_tr3_fcoe_header_info[index].fc_hdr_type)); 3570 } 3571 } 3572 return SOC_E_NONE; 3573 } 3574 3575 STATIC int 3576 soc_tr3_mem_clear(int unit) 3577 { 3578 uint32 rval, index; 3579 int pipe_init_usec; 3580 soc_timeout_t to; 3581 int tcam_protect_write; 3582 3583 static const soc_mem_t cam[] = { 3584 L3_TUNNELm, 3585 FP_UDF_TCAMm, 3586 VLAN_SUBNETm, 3587 VFP_TCAMm, 3588 MY_STATION_TCAMm, 3589 L2_USER_ENTRYm, 3590 L3_DEFIPm, 3591 L3_DEFIP_PAIR_128m, 3592 ESM_PKT_TYPE_IDm, 3593 FP_TCAMm, 3594 FP_GLOBAL_MASK_TCAMm, 3595 CPU_COS_MAPm, 3596 EFP_TCAMm 3597 }; 3598 3599 static const soc_mem_t axp[] = { 3600 AXP_WTX_TUNNELm, 3601 AXP_WRX_WCDm, 3602 AXP_WRX_SVP_ASSIGNMENTm, 3603 AXP_WTX_DVP_PROFILEm, 3604 AXP_WTX_PRI_MAPm, 3605 AXP_WTX_FRAG_IDm 3606 }; 3607 3608 /* 3609 * Reset the IPIPE and EPIPE block 3610 */ 3611 rval = 0; 3612 SOC_IF_ERROR_RETURN(WRITE_ING_HW_RESET_CONTROL_1r(unit, rval)); 3613 soc_reg_field_set(unit, ING_HW_RESET_CONTROL_2r, &rval, RESET_ALLf, 1); 3614 soc_reg_field_set(unit, ING_HW_RESET_CONTROL_2r, &rval, VALIDf, 1); 3615 /* Set count to # entries in largest IPIPE table */ 3616 soc_reg_field_set(unit, ING_HW_RESET_CONTROL_2r, &rval, COUNTf, 65536); 3617 SOC_IF_ERROR_RETURN(WRITE_ING_HW_RESET_CONTROL_2r(unit, rval)); 3618 3619 rval = 0; 3620 SOC_IF_ERROR_RETURN(WRITE_EGR_HW_RESET_CONTROL_0r(unit, rval)); 3621 soc_reg_field_set(unit, EGR_HW_RESET_CONTROL_1r, &rval, RESET_ALLf, 1); 3622 soc_reg_field_set(unit, EGR_HW_RESET_CONTROL_1r, &rval, VALIDf, 1); 3623 /* Set count to # entries in largest EPIPE table */ 3624 soc_reg_field_set(unit, EGR_HW_RESET_CONTROL_1r, &rval, COUNTf, 65536); 3625 SOC_IF_ERROR_RETURN(WRITE_EGR_HW_RESET_CONTROL_1r(unit, rval)); 3626 3627 rval = 0; 3628 SOC_IF_ERROR_RETURN(WRITE_ISM_HW_RESET_CONTROL_0r(unit, rval)); 3629 soc_reg_field_set(unit, ISM_HW_RESET_CONTROL_1r, &rval, RESET_ALLf, 1); 3630 soc_reg_field_set(unit, ISM_HW_RESET_CONTROL_1r, &rval, VALIDf, 1); 3631 /* Set count to # entries in largest ISM table */ 3632 soc_reg_field_set(unit, ISM_HW_RESET_CONTROL_1r, &rval, COUNTf, 131072); 3633 SOC_IF_ERROR_RETURN(WRITE_ISM_HW_RESET_CONTROL_1r(unit, rval)); 3634 3635 /* Clear AXP block mems */ 3636 rval = 0; 3637 soc_reg_field_set(unit, AXP_WRX_MEMORY_BULK_RESETr, &rval, START_RESETf, 1); 3638 SOC_IF_ERROR_RETURN(WRITE_AXP_WRX_MEMORY_BULK_RESETr(unit, rval)); 3639 SOC_IF_ERROR_RETURN(WRITE_AXP_WTX_MEMORY_BULK_RESETr(unit, rval)); 3640 if (soc_feature(unit, soc_feature_regex)) { 3641 SOC_IF_ERROR_RETURN(WRITE_AXP_SM_MEMORY_BULK_RESETr(unit, rval)); 3642 } 3643 3644 /* For simulation, set timeout to 10 sec. Otherwise, timeout = 50 ms */ 3645 if (SAL_BOOT_SIMULATION) { 3646 pipe_init_usec = 10000000; 3647 } else { 3648 pipe_init_usec = 50000; 3649 } 3650 soc_timeout_init(&to, pipe_init_usec, 0); 3651 /* Wait for IPIPE memory initialization done. */ 3652 do { 3653 SOC_IF_ERROR_RETURN(READ_ING_HW_RESET_CONTROL_2r(unit, &rval)); 3654 if (soc_reg_field_get(unit, ING_HW_RESET_CONTROL_2r, rval, DONEf)) { 3655 break; 3656 } 3657 if (soc_timeout_check(&to)) { 3658 LOG_WARN(BSL_LS_SOC_COMMON, 3659 (BSL_META_U(unit, 3660 "unit %d : ING_HW_RESET timeout\n"), unit)); 3661 break; 3662 } 3663 } while (TRUE); 3664 soc_timeout_init(&to, pipe_init_usec, 0); 3665 /* Wait for EPIPE memory initialization done. */ 3666 do { 3667 SOC_IF_ERROR_RETURN(READ_EGR_HW_RESET_CONTROL_1r(unit, &rval)); 3668 if (soc_reg_field_get(unit, EGR_HW_RESET_CONTROL_1r, rval, DONEf)) { 3669 break; 3670 } 3671 if (soc_timeout_check(&to)) { 3672 LOG_WARN(BSL_LS_SOC_COMMON, 3673 (BSL_META_U(unit, 3674 "unit %d : EGR_HW_RESET timeout\n"), unit)); 3675 break; 3676 } 3677 } while (TRUE); 3678 soc_timeout_init(&to, pipe_init_usec, 0); 3679 /* Wait for ISM memory initialization done. */ 3680 do { 3681 SOC_IF_ERROR_RETURN(READ_ISM_HW_RESET_CONTROL_1r(unit, &rval)); 3682 if (soc_reg_field_get(unit, ISM_HW_RESET_CONTROL_1r, rval, DONEf)) { 3683 break; 3684 } 3685 if (soc_timeout_check(&to)) { 3686 LOG_WARN(BSL_LS_SOC_COMMON, 3687 (BSL_META_U(unit, 3688 "unit %d : ISM_HW_RESET timeout\n"), unit)); 3689 break; 3690 } 3691 } while (TRUE); 3692 soc_timeout_init(&to, pipe_init_usec, 0); 3693 /* Wait for AXP WLAN RX memory initialization done. */ 3694 do { 3695 SOC_IF_ERROR_RETURN(READ_AXP_WRX_MEMORY_BULK_RESETr(unit, &rval)); 3696 if (soc_reg_field_get(unit, AXP_WRX_MEMORY_BULK_RESETr, rval, RESET_DONEf) || 3697 SAL_BOOT_PLISIM) { 3698 break; 3699 } 3700 if (soc_timeout_check(&to)) { 3701 LOG_WARN(BSL_LS_SOC_COMMON, 3702 (BSL_META_U(unit, 3703 "unit %d : AXP_WRX_MEMORY timeout\n"), unit)); 3704 break; 3705 } 3706 } while (TRUE); 3707 soc_timeout_init(&to, pipe_init_usec, 0); 3708 /* Wait for AXP WLAN TX memory initialization done. */ 3709 do { 3710 SOC_IF_ERROR_RETURN(READ_AXP_WTX_MEMORY_BULK_RESETr(unit, &rval)); 3711 if (soc_reg_field_get(unit, AXP_WTX_MEMORY_BULK_RESETr, rval, RESET_DONEf) || 3712 SAL_BOOT_PLISIM) { 3713 break; 3714 } 3715 if (soc_timeout_check(&to)) { 3716 LOG_WARN(BSL_LS_SOC_COMMON, 3717 (BSL_META_U(unit, 3718 "unit %d : AXP_WTX_MEMORY timeout\n"), unit)); 3719 break; 3720 } 3721 } while (TRUE); 3722 if (soc_feature(unit, soc_feature_regex)) { 3723 soc_timeout_init(&to, pipe_init_usec, 0); 3724 /* Wait for AXP SM memory initialization done. */ 3725 do { 3726 SOC_IF_ERROR_RETURN(READ_AXP_SM_MEMORY_BULK_RESETr(unit, &rval)); 3727 if (soc_reg_field_get(unit, AXP_SM_MEMORY_BULK_RESETr, rval, RESET_DONEf) || 3728 SAL_BOOT_PLISIM) { 3729 break; 3730 } 3731 if (soc_timeout_check(&to)) { 3732 LOG_WARN(BSL_LS_SOC_COMMON, 3733 (BSL_META_U(unit, 3734 "unit %d : AXP_SM_MEMORY timeout\n"), unit)); 3735 break; 3736 } 3737 } while (TRUE); 3738 } 3739 rval = 0; 3740 SOC_IF_ERROR_RETURN(WRITE_ING_HW_RESET_CONTROL_2r(unit, rval)); 3741 SOC_IF_ERROR_RETURN(WRITE_EGR_HW_RESET_CONTROL_1r(unit, rval)); 3742 SOC_IF_ERROR_RETURN(WRITE_ISM_HW_RESET_CONTROL_1r(unit, rval)); 3743 rval = 0; 3744 soc_reg_field_set(unit, AXP_WRX_MEMORY_BULK_RESETr, &rval, START_RESETf, 0); 3745 SOC_IF_ERROR_RETURN(WRITE_AXP_WRX_MEMORY_BULK_RESETr(unit, rval)); 3746 SOC_IF_ERROR_RETURN(WRITE_AXP_WTX_MEMORY_BULK_RESETr(unit, rval)); 3747 if (soc_feature(unit, soc_feature_regex)) { 3748 SOC_IF_ERROR_RETURN(WRITE_AXP_SM_MEMORY_BULK_RESETr(unit, rval)); 3749 } 3750 3751 if (!SAL_BOOT_SIMULATION || SAL_BOOT_BCMSIM) { 3752 /* TCAM tables are not handled by hardware reset control */ 3753 tcam_protect_write = SOC_CONTROL(unit)->tcam_protect_write; 3754 SOC_CONTROL(unit)->tcam_protect_write = FALSE; 3755 for (index = 0; index < sizeof(cam) / sizeof(soc_mem_t); index++) { 3756 if (SOC_MEM_IS_VALID(unit, cam[index])) { 3757 if (SAL_BOOT_BCMSIM && 3758 !((cam[index] == VLAN_SUBNET_ONLYm) || 3759 (cam[index] == VFP_TCAMm) || 3760 (cam[index] == L2_USER_ENTRY_ONLYm))) { 3761 continue; 3762 } 3763 SOC_IF_ERROR_RETURN(soc_mem_clear(unit, cam[index], 3764 COPYNO_ALL, TRUE)); 3765 } 3766 } 3767 SOC_CONTROL(unit)->tcam_protect_write = tcam_protect_write; 3768 } 3769 if (!SAL_BOOT_SIMULATION) { 3770 for (index = 0; index < sizeof(axp) / sizeof(soc_mem_t); index++) { 3771 SOC_IF_ERROR_RETURN(soc_mem_clear(unit, axp[index], COPYNO_ALL, TRUE)); 3772 } 3773 SOC_IF_ERROR_RETURN 3774 (soc_mem_clear(unit, EGR_MPLS_VC_AND_SWAP_LABEL_TABLEm, COPYNO_ALL, 3775 TRUE)); 3776 SOC_IF_ERROR_RETURN 3777 (soc_mem_clear(unit, ING_DVP_2_TABLEm, COPYNO_ALL, TRUE)); 3778 } 3779 return SOC_E_NONE; 3780 } 3781 3782 int 3783 soc_tr3_init_port_mapping(int unit) 3784 { 3785 soc_info_t *si; 3786 soc_mem_t mem; 3787 uint32 rval; 3788 ing_physical_to_logical_port_number_mapping_table_entry_t entry; 3789 int port, phy_port, mmu_port; 3790 int num_port, num_phy_port, num_mmu_port; 3791 3792 si = &SOC_INFO(unit); 3793 3794 /* Ingress physical to logical port mapping */ 3795 mem = ING_PHYSICAL_TO_LOGICAL_PORT_NUMBER_MAPPING_TABLEm; 3796 num_phy_port = soc_mem_index_count(unit, mem); 3797 sal_memset(&entry, 0, sizeof(entry)); 3798 for (phy_port = 0; phy_port < num_phy_port; phy_port++) { 3799 port = si->port_p2l_mapping[phy_port]; 3800 soc_mem_field32_set(unit, mem, &entry, LOGICAL_PORT_NUMBERf, 3801 port == -1 ? 0x7f : port); 3802 SOC_IF_ERROR_RETURN 3803 (soc_mem_write(unit, mem, MEM_BLOCK_ALL, phy_port, &entry)); 3804 } 3805 num_port = soc_mem_index_count(unit, PORT_TABm); 3806 /* Egress logical to physical port mapping */ 3807 for (port = 0; port < num_port; port++) { 3808 phy_port = si->port_l2p_mapping[port]; 3809 rval = 0; 3810 soc_reg_field_set(unit, EGR_LOGICAL_TO_PHYSICAL_PORT_NUMBER_MAPPINGr, 3811 &rval, PHYSICAL_PORT_NUMBERf, 3812 phy_port == -1 ? 0x7f : phy_port); 3813 SOC_IF_ERROR_RETURN 3814 (WRITE_EGR_LOGICAL_TO_PHYSICAL_PORT_NUMBER_MAPPINGr(unit, port, 3815 rval)); 3816 } 3817 3818 /* MMU to physical port mapping and MMU to logical port mapping */ 3819 num_mmu_port = SOC_REG_NUMELS(unit, MMU_TO_PHY_PORT_MAPPINGr); 3820 for (mmu_port = 0; mmu_port < num_mmu_port; mmu_port++) { 3821 phy_port = si->port_m2p_mapping[mmu_port]; 3822 port = phy_port == -1 ? -1 : si->port_p2l_mapping[phy_port]; 3823 3824 rval = 0; 3825 soc_reg_field_set(unit, MMU_TO_PHY_PORT_MAPPINGr, &rval, PHY_PORTf, 3826 phy_port == -1 ? 0x7f : phy_port); 3827 SOC_IF_ERROR_RETURN 3828 (WRITE_MMU_TO_PHY_PORT_MAPPINGr(unit, mmu_port, rval)); 3829 3830 rval = 0; 3831 soc_reg_field_set(unit, MMU_TO_LOGIC_PORT_MAPPINGr, &rval, LOGIC_PORTf, 3832 port == -1 ? 0x3f : port); 3833 SOC_IF_ERROR_RETURN 3834 (WRITE_MMU_TO_LOGIC_PORT_MAPPINGr(unit, mmu_port, rval)); 3835 } 3836 3837 return SOC_E_NONE; 3838 } 3839 3840 int 3841 soc_triumph3_init_num_cosq(int unit) 3842 { 3843 soc_info_t *si; 3844 int port; 3845 int mc_numq, mc_base; 3846 int uc_numq, uc_base; 3847 3848 si = &SOC_INFO(unit); 3849 3850 SOC_PBMP_CLEAR(si->eq_pbm); 3851 PBMP_ALL_ITER(unit, port) { 3852 if (IS_HG_PORT(unit, port)) { 3853 SOC_PBMP_PORT_ADD(si->eq_pbm, port); 3854 } 3855 } 3856 3857 PBMP_ALL_ITER(unit, port) { 3858 soc_tr3_get_def_qbase(unit, port, _SOC_TR3_INDEX_STYLE_UCAST_QUEUE, 3859 &uc_base, &uc_numq); 3860 soc_tr3_get_def_qbase(unit, port, _SOC_TR3_INDEX_STYLE_MCAST_QUEUE, 3861 &mc_base, &mc_numq); 3862 si->port_num_cosq[port] = mc_numq; 3863 si->port_cosq_base[port] = mc_base; 3864 si->port_num_uc_cosq[port] = uc_numq; 3865 si->port_uc_cosq_base[port] = uc_base; 3866 si->port_group[port] = -1; 3867 LOG_VERBOSE(BSL_LS_SOC_COMMON, 3868 (BSL_META_U(unit, 3869 "Port-%d : UC: %d:%d, MC: %d:%d\n"), 3870 port, uc_base, uc_numq, mc_base, mc_numq)); 3871 } 3872 3873 return SOC_E_NONE; 3874 } 3875 3876 /* TR3 Port Configs: 3877 ================ 3878 3879 F.HG[127] = Boot Config between HG[127]/3xF.HG[42] 3880 F.HG[42] = Hot Swap between HG[42]/2xHGd[21]/2xRXAUI/4xHGs[11]/4xXFI/4x1GE/4x2.5GE 3881 F.XAUI = Hot Swap between XAUI/4x1GE/4x2.5GE 3882 F.HG[21] = Hot Swap between HG[21]/XAUI/4x1GE/4x2.5G 3883 F.40GE = Hot Swap between XE40/2xRXAUI/4xXFI/4x1GE/4x2.5GE 3884 3885 ------------------------------------------------------------------------------------------------------------------------------------------ 3886 dev-id | cfg-id | configuration | property | Hot swap 3887 ------------------------------------------------------------------------------------------------------------------------------------------ 3888 BCM56640 | 37 | 3xF.HG[42] + 1xHG[127] + 1GE | none | yes 3889 BCM56640 | 35 | TR3_100GE_260: 1x100GE + 1xHG[127] + 1GE | bcm56640_1x100_1x127 | no 3890 BCM56640 | 36 | 1x100GE + 4xHG[32] + 1GE | bcm56640_1x100_4x32 | no 3891 BCM56640 | 81 | 1x100GE + 8xHGd[16] + 1GE | bcm56640_1x100_8x16 | no 3892 BCM56640 | 38 | 1x100GE + 3xF.HG[42] + 1GE | bcm56640_1x100_3x42 | yes 3893 BCM56640 | 82 | 3xF.HG[42] + 4xHG[32] + 1GE | bcm56640_3x42_4x32 | yes 3894 BCM56640 | 83 | 3xF.HG[42] + 8xHGd[16] + 1GE | bcm56640_3x42_8x16 | yes 3895 BCM56640 | 71 | 3xF.40GE + 3xF.HG[42] + 1GE | bcm56640_3x40_3x42 | yes 3896 BCM56640 | 72 | 3xF.HG[42] + 3xF.40GE + 1GE | bcm56640_3x42_3x40 | yes 3897 | | | | 3898 BCM56643 | 95 | TR3_1G_280: 48xGE + 4xXFI + 4xHG[42] + 1GE | none | no 3899 BCM56643 | 195 | TR3_1G_280: 48xGE + 1x40GE + 4xHG[42] + 1GE | bcm56640_1x40_4x42 | no 3900 BCM56643 | 295 | TR3_1G_280: 48xGE + 4xXFI + 1xHG[127] + 1GE | bcm56640_4x10_1x127 | no 3901 BCM56643 | 100 | TR3_1G_280_FX: 36xGE + 4xXFI + 2xHG[42] + 2xF.HG[42] + 1GE | bcm56640_4x10_4x42 | yes 3902 BCM56643 | 102 | TR3_1G_280_FX: 36xGE + 4xXFI + 2xF.HG[42] + 2xHG[42] + 1GE | bcm56643_4x10_4x42 | Yes 3903 | | | | 3904 BCM56644 | 90 | FB3_1G_200_HG25: 48xGE + 2xHG[25] + 2xHG[25] + 1GE | none | no 3905 BCM56644 | 190 | FB3_1G_200_HG25: 24xGE (line rate encap) + 2xXAUI + 2xHG[25] + 1GE | bcm56644_24g | no 3906 | | | | 3907 BCM56540/BCM56545 | 10 | FB3_1G_200: 48xGE + 2xHG[42] + 2xHG[21] + 1GE | none | no 3908 BCM56540/BCM56545 | 103 | 48xGE + 4xXFI/4x11GE + 2xHG[42] + 1GE | bcm56545_4x11_2x42 | no 3909 BCM56540/BCM56545 | 12 | FB4_1G_200: 48xGE + 4xXFI + 2xHG[42] + 1GE | bcm56540_4x10_2x42 | no 3910 BCM56540/BCM56545 | 96 | FB3_1G_200_XFI: 48xGE + 8xXFI + 1GE | bcm56540_8x10 | no 3911 BCM56545 | 99 | 24xGE + 4xXAUI + 2xXFI + 2xHG[12] + 1GE | bcm56545_24g | no 3912 BCM56545K | 103 | 48xGE + 4x11GE + 2xHG[42] + 1GE | bcm56545_4x11_2x42 | no 3913 BCM56545K | 203 | 48xGE + 1x40GE + 2xHG[42] + 1GE | bcm56640_1x40_4x42 | no 3914 BCM56545K | 100 | 36xGE + 4xXFI + 2xHG[42] + 2xF.HG[42] + 1GE | bcm56640_4x10_4x42 | yes 3915 BCM56545K | 595 | 48xGE + 4xXFI + 4xHG[42] + 1GE | bcm56545_4x11_4x42 | no 3916 BCM56545K | 195 | 48xGE + 1x40GE + 4xHG[42] + 1GE | bcm56545_1x40_4x42 | no 3917 | | | | 3918 BCM56648 | 95 | TR3_1G_280: 48xGE + 4xXFI + 4xHG[42] + 1GE | none | no 3919 BCM56648 | 195 | TR3_1G_280: 48xGE + 1x40GE + 4xHG[42] + 1GE | bcm56640_1x40_4x42 | no 3920 BCM56648 | 100 | TR3_1G_280_FX: 36xGE + 4xXFI + 2xHG[42] + 2xF.HG[42] + 1GE | bcm56640_4x10_4x42 | yes 3921 | | | | 3922 BCM56544 | 91 | FB4_XAUI_200_C: 10xF.XAUI + 4xHG[21] + 1GE | none | yes 3923 BCM56544 | 97 | 10xF.XAUI + 4xXFI + 1GE | bcm56544_10x10_4x10 | yes 3924 BCM56544 | 98 | 10xF.XAUI + 2xHG[42] | bcm56544_10x10_2x42 | yes 3925 BCM56544 | 94 | FB4_XAUI_200_F: 4xXAUI + 12xXFI + 1GE | bcm56544_4x10_12x10 | no 3926 | | | | 3927 BCM56541 | 110 | 28xGE + 2xHG[42] + 2xHG[21] + 1GE | none | no 3928 BCM56541 | 112 | 28xGE + 4xXFI + 2xHG[42] + 1GE | bcm56540_4x10_2x42 | no 3929 BCM56541 | 196 | 28xGE + 8xXFI + 1GE | bcm56540_8x10 | no 3930 | | | | 3931 BCM56542 | 40 | AP2_1G_200_A: 28xGE + 2xF.XAUI/2x10GE + 2xF.HG[42] + 2xF.HG[21] + 1GE | bcm56542_2x10_2x42_2x21 | yes 3932 BCM56542 | 41 | AP2_1G_200_B: 28xGE + 8xGE/8x2.5GE + 2xHG[42] + 2xHG[21] + 1GE | none | no 3933 | | | | 3934 BCM56543 | 35 | 1x100GE + 1xHG[127] + 1GE | none | no 3935 BCM56543 | 38 | 1x100GE + 3xF.HG[42] + 1GE | bcm56640_1x100_3x42 | yes 3936 BCM56543 | 72 | 3xF.HG[42] + 3xF.40GE + 1GE | bcm56640_3x42_3x40 | yes 3937 BCM56543 | 37 | 3xF.HG[42] + 1xHG[127] + 1GE | bcm56640_3x42_1x127 | yes 3938 BCM56543 | 71 | 3xF.40GE + 3xF.HG[42] + 1GE | bcm56640_3x40_3x42 | yes 3939 | | | | 3940 BCM56546 | 110 | 28xGE + 2xHG[42] + 2xHG[21] + 1GE | none | no 3941 BCM56546 | 112 | 28xGE + 4xXFI + 2xHG[42] + 1GE | bcm56540_4x10_2x42 | no 3942 BCM56546 | 196 | 28xGE + 8xXFI + 1GE | bcm56540_8x10 | no 3943 BCM56546K | 303 | 48xGE + 4x11GE + 2xHG[42] + 1GE | bcm56545_4x11_2x42 | no 3944 BCM56546K | 403 | 48xGE + 1x40GE + 2xHG[42] + 1GE | bcm56640_1x40_4x42 | no 3945 BCM56546K | 101 | 36xGE + 4xXFI + 2xHG[42] + 2xF.HG[42] + 1GE | bcm56640_4x10_4x42 | yes 3946 BCM56546K | 695 | 48xGE + 4xXFI + 4xHG[42] + 1GE | bcm56545_4x11_4x42 | no 3947 BCM56546K | 495 | 48xGE + 1x40GE + 4xHG[42] + 1GE | bcm56545_1x40_4x42 | no 3948 | | | | 3949 BCM56649 | 395 | 28xGE + 4xXFI + 4xHG[42] + 1GE | none | no 3950 BCM56649 | 495 | 28xGE + 1x40GE + 4xHG[42] + 1GE | bcm56640_1x40_4x42 | no 3951 BCM56649 | 101 | 28xGE + 4xXFI + 2xHG[42] + 2xF.HG[42] + 1GE | bcm56640_4x10_4x42 | yes 3952 | | | | 3953 BCM56044 | 38 | 1x100GE + 3xF.HG[42] + 1GE | none | yes 3954 | | | | 3955 BCM56045 | 55 | RNGR_XAUI_260: 12xXAUI + 3xF.HG[42] + 1GE | none | yes 3956 BCM56045 | 71 | 3xF.40GE + 3xF.HG[42] + 1GE | bcm56640_3x40_3x42 | yes 3957 BCM56045 | 72 | 3xF.HG[42] + 3xF.40GE + 1GE | bcm56640_3x42_3x40 | yes 3958 | | | | 3959 BCM56046 | 155 | 12xXAUI + 2xF.HG[42] + 1GE | none | yes 3960 BCM56046 | 171 | 3xF.40GE + 2xF.HG[42] + 1GE | bcm56640_3x40_2x42 | yes 3961 BCM56046 | 172 | 3xF.HG[42] + 2xF.40GE + 1GE | bcm56640_3x42_2x40 | yes 3962 ------------------------------------------------------------------------------------------------------------------------------------------ 3963 */ 3964 3965 3966 typedef struct { 3967 uint16 dev_id; 3968 uint8 opp_spacing; 3969 int def_cfg; 3970 int cfg[_MAX_TR3_PORT_CFG]; 3971 } _soc_tr3_port_cfg_t; 3972 3973 typedef struct { 3974 uint16 dev_id; 3975 char *props[_MAX_TR3_FLEX_PORT_PROPS]; 3976 } _soc_tr3_flex_port_cfg_t; 3977 3978 static _soc_tr3_flex_port_cfg_t tr3_flex_props[] = { 3979 { BCM56640_DEVICE_ID, { spn_BCM56640_3X40_3X42, spn_BCM56640_3X42_3X40, 3980 spn_BCM56640_1X100_1X127, spn_BCM56640_1X100_4X32, 3981 spn_BCM56640_1X100_8X16, spn_BCM56640_1X100_3X42, 3982 spn_BCM56640_3X42_4X32, spn_BCM56640_3X42_8X16, 3983 /* NOTE: Following 2 are test only configs */ 3984 "REGRESSION", "EMULATION", NULL } }, 3985 { BCM56643_DEVICE_ID, { spn_BCM56640_1X40_4X42, spn_BCM56640_4X10_1X127, 3986 spn_BCM56640_4X10_4X42, spn_BCM56643_4X10_4X42, 3987 NULL} }, 3988 3989 { BCM56644_DEVICE_ID, { spn_BCM56644_24G, NULL } }, 3990 { BCM56540_DEVICE_ID, { spn_BCM56540_4X10_2X42, spn_BCM56540_8X10, spn_BCM56545_4X11_2X42, NULL } }, 3991 { BCM56541_DEVICE_ID, { spn_BCM56540_4X10_2X42, spn_BCM56540_8X10, NULL } }, 3992 { BCM56542_DEVICE_ID, { spn_BCM56542_2X10_2X42_2X21, NULL } }, 3993 { BCM56543_DEVICE_ID, { spn_BCM56640_1X100_3X42, spn_BCM56640_3X42_3X40, 3994 spn_BCM56640_3X42_1X127, spn_BCM56640_3X40_3X42, NULL} }, 3995 { BCM56544_DEVICE_ID, { spn_BCM56544_10X10_4X10, spn_BCM56544_10X10_2X42, 3996 spn_BCM56544_4X10_12X10, NULL } }, 3997 { BCM56545_DEVICE_ID, { spn_BCM56540_4X10_2X42, spn_BCM56540_8X10, 3998 spn_BCM56545_24G, spn_BCM56545_4X11_2X42, 3999 spn_BCM56640_4X10_4X42, spn_BCM56545_4X11_4X42, 4000 spn_BCM56640_1X40_4X42, spn_BCM56545_1X40_2X42, NULL } }, 4001 { BCM56546_DEVICE_ID, { spn_BCM56540_4X10_2X42, spn_BCM56540_8X10, 4002 spn_BCM56545_4X11_2X42, 4003 spn_BCM56640_4X10_4X42, spn_BCM56545_4X11_4X42, 4004 spn_BCM56640_1X40_4X42, spn_BCM56545_1X40_2X42, NULL } }, 4005 { BCM56648_DEVICE_ID, { spn_BCM56640_1X40_4X42, spn_BCM56640_4X10_4X42, NULL } }, 4006 { BCM56649_DEVICE_ID, { spn_BCM56640_1X40_4X42, spn_BCM56640_4X10_4X42, NULL } }, 4007 { BCM56044_DEVICE_ID, { NULL } }, 4008 { BCM56045_DEVICE_ID, { spn_BCM56640_3X40_3X42, spn_BCM56640_3X42_3X40, NULL } }, 4009 { BCM56046_DEVICE_ID, { spn_BCM56640_3X40_2X42, spn_BCM56640_3X42_2X40, NULL } } 4010 }; 4011 4012 int16 _tr3_wc_flex_port_speeds_1[] = { 42, 21, 10, 11, 10, 3, 1, -1 }; 4013 int16 _tr3_wc_flex_port_lanes_1[] = { 4, 2, 2, 1, 1, 1, 1, -1 }; 4014 int16 _tr3_wc_def_flex_port_speeds_1[] = { 42, 21, 11 }; 4015 int16 _tr3_wc_flex_port_speeds_2[] = { 21, 10, 3, 1, -1 }; 4016 int16 _tr3_wc_flex_port_lanes_2[] = { 4, 4, 1, 1, -1 }; 4017 int16 _tr3_wc_def_flex_port_speeds_2[] = { 21, 0, 3 }; 4018 int16 _tr3_wc_flex_port_speeds_3[] = { 40, 10, 10, 3, 1, -1 }; 4019 int16 _tr3_wc_flex_port_lanes_3[] = { 4, 2, 1, 1, 1, -1 }; 4020 int16 _tr3_wc_def_flex_port_speeds_3[] = { 40, 10, 10 }; 4021 int16 _tr3_xc_flex_port_speeds[] = { 10, 3, 1, -1 }; 4022 int16 _tr3_xc_flex_port_lanes[] = { 4, 1, 1, -1 }; 4023 int16 _tr3_xc_def_flex_port_speeds[] = { 10, 0, 3 }; 4024 _soc_tr3_flex_port_inf_t _tr3_flex_port_inf[SOC_MAX_NUM_DEVICES]; 4025 int _tr3_port_config_id[SOC_MAX_NUM_DEVICES] = {-1}; 4026 int _tr3_tdm_opp_spacing[SOC_MAX_NUM_DEVICES] = {0}; 4027 _soc_tr3_flex_port_data_t _tr3_flex_port_data[SOC_MAX_NUM_DEVICES] = {{0}}; 4028 4029 STATIC void 4030 _soc_tr3_resolve_port_config(int unit, int dev_id) { 4031 static _soc_tr3_port_cfg_t tr3_port_cfg[] = { 4032 { BCM56640_DEVICE_ID, 3, 37, { 71, 72, 35, 36, 81, 38, 82, 83, 4033 /* NOTE: Following 2 are test only configs */ 4034 11, 50, -1 } }, 4035 { BCM56643_DEVICE_ID, 3, 95, { 195, 295, 100, 102, -1 } }, 4036 { BCM56644_DEVICE_ID, 3, 90, { 190, -1 } }, 4037 { BCM56540_DEVICE_ID, 3, 10, { 12, 96, 103, -1 } }, 4038 { BCM56541_DEVICE_ID, 3, 110, { 112, 196, -1 } }, 4039 { BCM56542_DEVICE_ID, 3, 41, { 40, -1 } }, 4040 { BCM56543_DEVICE_ID, 3, 35, { 38, 72, 37, 71, -1} }, 4041 { BCM56544_DEVICE_ID, 3, 91, { 97, 98, 94, -1 } }, 4042 { BCM56545_DEVICE_ID, 3, 10, { 12, 96, 99, 103, 100, 595, 195, 203, -1 } }, 4043 { BCM56546_DEVICE_ID, 3, 110, { 112, 196, 303, 101, 695, 495, 403, -1 } }, 4044 { BCM56648_DEVICE_ID, 3, 95, { 195, 100, -1 } }, 4045 { BCM56649_DEVICE_ID, 3, 395, { 495, 101, -1 } }, 4046 { BCM56044_DEVICE_ID, 3, 38, { -1 } }, 4047 { BCM56045_DEVICE_ID, 3, 55, { 71, 72, -1 } }, 4048 { BCM56046_DEVICE_ID, 3, 155, { 171, 172, -1 } } 4049 }; 4050 int i, c, config, cfg_id = 0; 4051 uint8 entries; 4052 4053 entries = COUNTOF(tr3_flex_props); 4054 for (i = 0; i < entries; i++) { 4055 if (dev_id == tr3_flex_props[i].dev_id) { 4056 _tr3_tdm_opp_spacing[unit] = tr3_port_cfg[i].opp_spacing; 4057 cfg_id = tr3_port_cfg[i].def_cfg; 4058 for (c = 0; tr3_flex_props[i].props[c] != NULL ;c++) { 4059 config = soc_property_get(unit, tr3_flex_props[i].props[c], 0); 4060 if (config) { 4061 cfg_id = tr3_port_cfg[i].cfg[c]; 4062 break; 4063 } 4064 } 4065 } 4066 } 4067 _tr3_port_config_id[unit] = cfg_id; 4068 _tr3_flex_port_data[unit].dev_id = dev_id; 4069 } 4070 4071 int _soc_tr3_port_speed_max[SOC_MAX_PHY_PORTS]; /* max phy port speed */ 4072 /* 4073 * Tr3 port mapping 4074 * cpu port number is fixed: physical 0, logical 0, mmu 0 4075 * loopback port numbers are fixed 4076 */ 4077 int 4078 soc_triumph3_get_port_mapping(int unit, uint16 dev_id) 4079 { 4080 /* COVERITY: Intentional: static array of mappings */ 4081 /* coverity[stack_use_callee_max : FALSE] */ 4082 /* FB3_1G_200: 48xGE + 2xHG[42] + 2xHG[21] + 1GE */ 4083 static const int p2l_mapping_10[] = { 4084 0, 4085 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 4086 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 4087 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 4088 37, -1, -1, -1, 4089 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 4090 -1, -1, -1, -1, 50, -1, -1, -1, 51, -1, -1, -1, 4091 -1, -1, -1, -1, 4092 -1, -1, -1, -1, 52, -1, -1, -1, 53, -1, -1, -1, 4093 61, 59, 58, 60, 62 4094 }; 4095 static const int p2m_mapping_10[] = { 4096 59, 4097 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 4098 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 4099 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 4100 60, -1, -1, -1, 4101 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 4102 -1, -1, -1, -1, 48, -1, -1, -1, 49, -1, -1, -1, 4103 -1, -1, -1, -1, 4104 -1, -1, -1, -1, 50, -1, -1, -1, 51, -1, -1, -1, 4105 58, 62, 56, 61, 57 4106 }; 4107 static const int port_speed_max_10[] = { 4108 -1, 4109 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 4110 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 4111 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 4112 1, -1, -1, -1, 4113 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 4114 -1, -1, -1, -1, 42, -1, -1, -1, 42, -1, -1, -1, 4115 -1, -1, -1, -1, 4116 -1, -1, -1, -1, 21, -1, -1, -1, 21, -1, -1, -1, 4117 -1, -1, -1, -1, -1 4118 }; 4119 /* 56541/56546: 28xGE + 2xHG[42] + 2xHG[21] + 1GE */ 4120 static const int p2l_mapping_110[] = { 4121 0, 4122 -1, -1, -1, -1, -1, -1, -1, -1, 1, 2, 3, 4, 4123 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 4124 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 4125 37, -1, -1, -1, 4126 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4127 -1, -1, -1, -1, 50, -1, -1, -1, 51, -1, -1, -1, 4128 -1, -1, -1, -1, 4129 -1, -1, -1, -1, 52, -1, -1, -1, 53, -1, -1, -1, 4130 61, 59, 58, 60, 62 4131 }; 4132 static const int p2m_mapping_110[] = { 4133 59, 4134 -1, -1, -1, -1, -1, -1, -1, -1, 0, 1, 2, 3, 4135 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 4136 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 4137 60, -1, -1, -1, 4138 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4139 -1, -1, -1, -1, 48, -1, -1, -1, 49, -1, -1, -1, 4140 -1, -1, -1, -1, 4141 -1, -1, -1, -1, 50, -1, -1, -1, 51, -1, -1, -1, 4142 58, 62, 56, 61, 57 4143 }; 4144 static const int port_speed_max_110[] = { 4145 -1, 4146 -1, -1, -1, -1, -1, -1, -1, -1, 1, 1, 1, 1, 4147 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 4148 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 4149 1, -1, -1, -1, 4150 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4151 -1, -1, -1, -1, 42, -1, -1, -1, 42, -1, -1, -1, 4152 -1, -1, -1, -1, 4153 -1, -1, -1, -1, 21, -1, -1, -1, 21, -1, -1, -1, 4154 -1, -1, -1, -1, -1 4155 }; 4156 /* TR3_1G_200: 48xGE + 4xXFI + 4xHG[25] + 1GE */ 4157 static const int p2l_mapping_11[] = { 4158 0, 4159 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 4160 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 4161 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 4162 37, -1, -1, -1, 4163 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 4164 -1, -1, -1, -1, 50, 51, 52, 53, -1, -1, -1, -1, 4165 54, -1, -1, -1, 4166 55, -1, -1, -1, 56, -1, -1, -1, 57, -1, -1, -1, 4167 61, 59, 58, 60, 62 4168 }; 4169 static const int p2m_mapping_11[] = { 4170 59, 4171 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 4172 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 4173 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 4174 60, -1, -1, -1, 4175 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 4176 -1, -1, -1, -1, 48, 49, 50, 51, -1, -1, -1, -1, 4177 52, -1, -1, -1, 4178 53, -1, -1, -1, 54, -1, -1, -1, 55, -1, -1, -1, 4179 58, 62, 56, 61, 57 4180 }; 4181 static const int port_speed_max_11[] = { 4182 -1, 4183 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 4184 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 4185 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 4186 1, -1, -1, -1, 4187 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 4188 -1, -1, -1, -1, 10, 10, 10, 10, -1, -1, -1, -1, 4189 25, -1, -1, -1, 4190 25, -1, -1, -1, 25, -1, -1, -1, 25, -1, -1, -1, 4191 -1, -1, -1, -1, -1 4192 }; 4193 /* FB4_1G_200: 48xGE + 4xXFI + 2xHG[42] + 1GE */ 4194 static const int p2l_mapping_12[] = { 4195 0, 4196 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 4197 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 4198 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 4199 37, -1, -1, -1, 4200 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 4201 -1, -1, -1, -1, 50, 51, 52, 53, -1, -1, -1, -1, 4202 -1, -1, -1, -1, 4203 -1, -1, -1, -1, 54, -1, -1, -1, 55, -1, -1, -1, 4204 61, 59, 58, 60, 62 4205 }; 4206 static const int flex_p2l_mapping_12[] = { 4207 0, 4208 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 4209 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 4210 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 4211 37, -1, -1, -1, 4212 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 4213 -1, -1, -1, -1, 50, 51, 52, 53, -1, -1, -1, -1, 4214 -1, -1, -1, -1, 4215 -1, -1, -1, -1, 54, -1, -1, -1, 55, -1, -1, -1, 4216 61, 59, 58, 60, 62 4217 }; 4218 static const int p2m_mapping_12[] = { 4219 59, 4220 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 4221 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 4222 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 4223 60, -1, -1, -1, 4224 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 4225 -1, -1, -1, -1, 48, 49, 50, 51, -1, -1, -1, -1, 4226 -1, -1, -1, -1, 4227 -1, -1, -1, -1, 52, -1, -1, -1, 53, -1, -1, -1, 4228 58, 62, 56, 61, 57 4229 }; 4230 static const int port_speed_max_12[] = { 4231 -1, 4232 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 4233 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 4234 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 4235 1, -1, -1, -1, 4236 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 4237 -1, -1, -1, -1, 10, 10, 10, 10, -1, -1, -1, -1, 4238 -1, -1, -1, -1, 4239 -1, -1, -1, -1, 42, -1, -1, -1, 42, -1, -1, -1, 4240 -1, -1, -1, -1, -1 4241 }; 4242 /* 56541/56546: 28xGE + 4xXFI + 2xHG[42] + 1GE */ 4243 static const int p2l_mapping_112[] = { 4244 0, 4245 -1, -1, -1, -1, -1, -1, -1, -1, 1, 2, 3, 4, 4246 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 4247 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 4248 37, -1, -1, -1, 4249 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4250 -1, -1, -1, -1, 50, 51, 52, 53, -1, -1, -1, -1, 4251 -1, -1, -1, -1, 4252 -1, -1, -1, -1, 54, -1, -1, -1, 55, -1, -1, -1, 4253 61, 59, 58, 60, 62 4254 }; 4255 static const int flex_p2l_mapping_112[] = { 4256 0, 4257 -1, -1, -1, -1, -1, -1, -1, -1, 1, 2, 3, 4, 4258 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 4259 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 4260 37, -1, -1, -1, 4261 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4262 -1, -1, -1, -1, 50, 51, 52, 53, -1, -1, -1, -1, 4263 -1, -1, -1, -1, 4264 -1, -1, -1, -1, 54, -1, -1, -1, 55, -1, -1, -1, 4265 61, 59, 58, 60, 62 4266 }; 4267 static const int p2m_mapping_112[] = { 4268 59, 4269 -1, -1, -1, -1, -1, -1, -1, -1, 0, 1, 2, 3, 4270 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 4271 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 4272 60, -1, -1, -1, 4273 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4274 -1, -1, -1, -1, 48, 49, 50, 51, -1, -1, -1, -1, 4275 -1, -1, -1, -1, 4276 -1, -1, -1, -1, 52, -1, -1, -1, 53, -1, -1, -1, 4277 58, 62, 56, 61, 57 4278 }; 4279 static const int port_speed_max_112[] = { 4280 -1, 4281 -1, -1, -1, -1, -1, -1, -1, -1, 1, 1, 1, 1, 4282 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 4283 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 4284 1, -1, -1, -1, 4285 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4286 -1, -1, -1, -1, 10, 10, 10, 10, -1, -1, -1, -1, 4287 -1, -1, -1, -1, 4288 -1, -1, -1, -1, 42, -1, -1, -1, 42, -1, -1, -1, 4289 -1, -1, -1, -1, -1 4290 }; 4291 static _soc_tr3_flex_port_inf_t flex_port_inf_112 = { 4292 1, 4293 { 18, 19, -1 }, 4294 { _tr3_wc_flex_port_speeds_1, _tr3_wc_flex_port_speeds_1, 4295 NULL }, 4296 { _tr3_wc_def_flex_port_speeds_1, _tr3_wc_def_flex_port_speeds_1, 4297 NULL }, 4298 { _tr3_wc_flex_port_lanes_1, _tr3_wc_flex_port_lanes_1, 4299 NULL } 4300 }; 4301 /* TR3_100GE_260: 1x100GE + 1xHG[127] */ 4302 static const int p2l_mapping_35[] = { 4303 0, 4304 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4305 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4306 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4307 1, -1, -1, -1, 4308 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4309 5, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4310 -1, -1, -1, -1, 4311 21, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4312 61, 59, 58, 60, 62 4313 }; 4314 static const int p2m_mapping_35[] = { 4315 59, 4316 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4317 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4318 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4319 60, -1, -1, -1, 4320 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4321 48, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4322 -1, -1, -1, -1, 4323 52, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4324 58, 62, 56, 61, 57 4325 }; 4326 static const int port_speed_max_35[] = { 4327 -1, 4328 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4329 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4330 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4331 1, -1, -1, -1, 4332 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4333 100, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4334 -1, -1, -1, -1, 4335 127, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4336 -1, -1, -1, -1, -1 4337 }; 4338 /* 1x100GE + 4xHG[32] */ 4339 static const int p2l_mapping_36[] = { 4340 0, 4341 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4342 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4343 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4344 1, -1, -1, -1, 4345 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4346 5, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4347 17, -1, -1, -1, 4348 21, -1, -1, -1, 25, -1, -1, -1, 29, -1, -1, -1, 4349 61, 59, 58, 60, 62 4350 }; 4351 static const int p2m_mapping_36[] = { 4352 59, 4353 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4354 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4355 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4356 60, -1, -1, -1, 4357 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4358 48, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4359 53, -1, -1, -1, 4360 52, -1, -1, -1, 54, -1, -1, -1, 55, -1, -1, -1, 4361 58, 62, 56, 61, 57 4362 }; 4363 static const int port_speed_max_36[] = { 4364 -1, 4365 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4366 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4367 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4368 1, -1, -1, -1, 4369 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4370 100, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4371 30, -1, -1, -1, 4372 30, -1, -1, -1, 30, -1, -1, -1, 30, -1, -1, -1, 4373 -1, -1, -1, -1, -1 4374 }; 4375 /* 3xF.HG[42] + 1xHG[127] */ 4376 static const int p2l_mapping_37[] = { 4377 0, 4378 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4379 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4380 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4381 1, -1, -1, -1, 4382 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4383 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 4384 -1, -1, -1, -1, 4385 21, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4386 61, 59, 58, 60, 62 4387 }; 4388 static const int flex_p2l_mapping_37[] = { 4389 0, 4390 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4391 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4392 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4393 1, -1, -1, -1, 4394 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4395 5, -1, -1, -1, 9, -1, -1, -1, 13, -1, -1, -1, 4396 -1, -1, -1, -1, 4397 21, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4398 61, 59, 58, 60, 62 4399 }; 4400 static const int p2m_mapping_37[] = { 4401 59, 4402 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4403 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4404 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4405 60, -1, -1, -1, 4406 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4407 48, 40, 41, 42, 49, 43, 44, 45, 50, 46, 47, 51, 4408 -1, -1, -1, -1, 4409 52, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4410 58, 62, 56, 61, 57 4411 }; 4412 static const int port_speed_max_37[] = { 4413 -1, 4414 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4415 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4416 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4417 1, -1, -1, -1, 4418 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4419 42, -1, -1, -1, 42, -1, -1, -1, 42, -1, -1, -1, 4420 -1, -1, -1, -1, 4421 127, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4422 -1, -1, -1, -1, -1 4423 }; 4424 static _soc_tr3_flex_port_inf_t flex_port_inf_37 = { 4425 1, 4426 { 13, 14, 15, -1 }, 4427 { _tr3_wc_flex_port_speeds_1, _tr3_wc_flex_port_speeds_1, 4428 _tr3_wc_flex_port_speeds_1, NULL }, 4429 { _tr3_wc_def_flex_port_speeds_1, _tr3_wc_def_flex_port_speeds_1, 4430 _tr3_wc_def_flex_port_speeds_1, NULL }, 4431 { _tr3_wc_flex_port_lanes_1, _tr3_wc_flex_port_lanes_1, 4432 _tr3_wc_flex_port_lanes_1, NULL } 4433 }; 4434 /* 1x100GE + 3xF.HG[42] */ 4435 static const int p2l_mapping_38[] = { 4436 0, 4437 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4438 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4439 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4440 1, -1, -1, -1, 4441 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4442 5, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4443 -1, -1, -1, -1, 4444 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 4445 61, 59, 58, 60, 62 4446 }; 4447 static const int flex_p2l_mapping_38[] = { 4448 0, 4449 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4450 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4451 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4452 1, -1, -1, -1, 4453 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4454 5, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4455 -1, -1, -1, -1, 4456 21, -1, -1, -1, 25, -1, -1, -1, 29, -1, -1, -1, 4457 61, 59, 58, 60, 62 4458 }; 4459 static const int p2m_mapping_38[] = { 4460 59, 4461 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4462 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4463 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4464 60, -1, -1, -1, 4465 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4466 52, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4467 -1, -1, -1, -1, 4468 48, 40, 41, 42, 49, 43, 44, 45, 50, 46, 47, 51, 4469 58, 62, 56, 61, 57 4470 }; 4471 static const int port_speed_max_38[] = { 4472 -1, 4473 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4474 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4475 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4476 1, -1, -1, -1, 4477 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4478 100, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4479 -1, -1, -1, -1, 4480 42, -1, -1, -1, 42, -1, -1, -1, 42, -1, -1, -1, 4481 -1, -1, -1, -1, -1 4482 }; 4483 static _soc_tr3_flex_port_inf_t flex_port_inf_38 = { 4484 1, 4485 { 17, 18, 19, -1 }, 4486 { _tr3_wc_flex_port_speeds_1, _tr3_wc_flex_port_speeds_1, 4487 _tr3_wc_flex_port_speeds_1, NULL }, 4488 { _tr3_wc_def_flex_port_speeds_1, _tr3_wc_def_flex_port_speeds_1, 4489 _tr3_wc_def_flex_port_speeds_1, NULL }, 4490 { _tr3_wc_flex_port_lanes_1, _tr3_wc_flex_port_lanes_1, 4491 _tr3_wc_flex_port_lanes_1, NULL } 4492 }; 4493 /* AP2_1G_200_A: 28xGE + 2xF.XAUI/2x10GE + 2xF.HG[42] + 2xF.HG[21] + 1GE */ 4494 static const int p2l_mapping_40[] = { 4495 0, 4496 -1, -1, -1, -1, -1, -1, -1, -1, 1, 2, 3, 4, 4497 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 4498 17, 18, 19, 20, -1, -1, -1, -1, 21, 22, 23, 24, 4499 25, -1, -1, -1, 4500 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 4501 -1, -1, -1, -1, 38, 39, 40, 41, 42, 43, 44, 45, 4502 -1, -1, -1, -1, 4503 -1, -1, -1, -1, 46, 47, 48, 49, 50, 51, 52, 53, 4504 61, 59, 58, 60, 62 4505 }; 4506 static const int flex_p2l_mapping_40[] = { 4507 0, 4508 -1, -1, -1, -1, -1, -1, -1, -1, 1, 2, 3, 4, 4509 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 4510 17, 18, 19, 20, -1, -1, -1, -1, 21, 22, 23, 24, 4511 25, -1, -1, -1, 4512 26, 27, 28, 29, 30, -1, -1, -1, 34, -1, -1, -1, 4513 -1, -1, -1, -1, 38, -1, -1, -1, 42, -1, -1, -1, 4514 -1, -1, -1, -1, 4515 -1, -1, -1, -1, 46, -1, -1, -1, 50, -1, -1, -1, 4516 61, 59, 58, 60, 62 4517 }; 4518 static const int p2m_mapping_40[] = { 4519 59, 4520 -1, -1, -1, -1, -1, -1, -1, -1, 0, 1, 2, 3, 4521 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 4522 16, 17, 18, 19, -1, -1, -1, -1, 20, 21, 22, 23, 4523 60, -1, -1, -1, 4524 24, 25, 26, 27, 32, 28, 29, 30, 33, 31, 36, 37, 4525 -1, -1, -1, -1, 48, 49, 50, 51, 52, 53, 54, 55, 4526 -1, -1, -1, -1, 4527 -1, -1, -1, -1, 44, 38, 39, 40, 47, 41, 42, 43, 4528 58, 62, 56, 61, 57 4529 }; 4530 static const int port_speed_max_40[] = { 4531 -1, 4532 -1, -1, -1, -1, -1, -1, -1, -1, 1, 1, 1, 1, 4533 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 4534 1, 1, 1, 1, -1, -1, -1, -1, 1, 1, 1, 1, 4535 1, -1, -1, -1, 4536 1, 1, 1, 1, 10, -1, -1, -1, 10, -1, -1, -1, 4537 -1, -1, -1, -1, 42, -1, -1, -1, 42, -1, -1, -1, 4538 -1, -1, -1, -1, 4539 -1, -1, -1, -1, 21, -1, -1, -1, 21, -1, -1, -1, 4540 -1, -1, -1, -1, -1 4541 }; 4542 static _soc_tr3_flex_port_inf_t flex_port_inf_40 = { 4543 1, 4544 { 11, 12, 14, 15, 18, 19, -1 }, 4545 { _tr3_xc_flex_port_speeds, _tr3_xc_flex_port_speeds, 4546 _tr3_wc_flex_port_speeds_1, _tr3_wc_flex_port_speeds_1, 4547 _tr3_wc_flex_port_speeds_2, _tr3_wc_flex_port_speeds_2, NULL }, 4548 { _tr3_xc_def_flex_port_speeds, _tr3_xc_def_flex_port_speeds, 4549 _tr3_wc_def_flex_port_speeds_1, _tr3_wc_def_flex_port_speeds_1, 4550 _tr3_wc_def_flex_port_speeds_2, _tr3_wc_def_flex_port_speeds_2, NULL }, 4551 { _tr3_xc_flex_port_lanes, _tr3_xc_flex_port_lanes, 4552 _tr3_wc_flex_port_lanes_1, _tr3_wc_flex_port_lanes_1, 4553 _tr3_wc_flex_port_lanes_2, _tr3_wc_flex_port_lanes_2, NULL } 4554 }; 4555 /* AP2_1G_200_B: 28xGE + 8xGE/8x2.5GE + 2xHG[42] + 2xHG[21] + 1GE */ 4556 static const int p2l_mapping_41[] = { 4557 0, 4558 -1, -1, -1, -1, -1, -1, -1, -1, 1, 2, 3, 4, 4559 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 4560 17, 18, 19, 20, -1, -1, -1, -1, 21, 22, 23, 24, 4561 25, -1, -1, -1, 4562 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 4563 -1, -1, -1, -1, 38, -1, -1, -1, 42, -1, -1, -1, 4564 -1, -1, -1, -1, 4565 -1, -1, -1, -1, 46, -1, -1, -1, 50, -1, -1, -1, 4566 61, 59, 58, 60, 62 4567 }; 4568 static const int p2m_mapping_41[] = { 4569 59, 4570 -1, -1, -1, -1, -1, -1, -1, -1, 0, 1, 2, 3, 4571 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 4572 16, 17, 18, 19, -1, -1, -1, -1, 20, 21, 22, 23, 4573 60, -1, -1, -1, 4574 24, 25, 26, 27, 32, 28, 29, 30, 33, 31, 36, 37, 4575 -1, -1, -1, -1, 48, -1, -1, -1, 52, -1, -1, -1, 4576 -1, -1, -1, -1, 4577 -1, -1, -1, -1, 44, -1, -1, -1, 47, -1, -1, -1, 4578 58, 62, 56, 61, 57 4579 }; 4580 static const int port_speed_max_41[] = { 4581 -1, 4582 -1, -1, -1, -1, -1, -1, -1, -1, 1, 1, 1, 1, 4583 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 4584 1, 1, 1, 1, -1, -1, -1, -1, 1, 1, 1, 1, 4585 1, -1, -1, -1, 4586 1, 1, 1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 4587 -1, -1, -1, -1, 42, -1, -1, -1, 42, -1, -1, -1, 4588 -1, -1, -1, -1, 4589 -1, -1, -1, -1, 21, -1, -1, -1, 21, -1, -1, -1, 4590 -1, -1, -1, -1, -1 4591 }; 4592 /* FB4_1G_260_EMU: 48xGE + 4xXFI + 2xHG[42] + 1GE */ 4593 static const int p2l_mapping_50[] = { 4594 0, 4595 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 4596 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 4597 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 4598 37, -1, -1, -1, 4599 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 4600 -1, -1, -1, -1, 50, 51, 52, 53, -1, -1, -1, -1, 4601 -1, -1, -1, -1, 4602 -1, -1, -1, -1, 54, -1, -1, -1, 55, -1, -1, -1, 4603 61, 59, 58, 60, 62 4604 }; 4605 static const int p2m_mapping_50[] = { 4606 59, 4607 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 4608 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 4609 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 4610 60, -1, -1, -1, 4611 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 4612 -1, -1, -1, -1, 48, 49, 50, 51, -1, -1, -1, -1, 4613 -1, -1, -1, -1, 4614 -1, -1, -1, -1, 52, -1, -1, -1, 53, -1, -1, -1, 4615 58, 62, 56, 61, 57 4616 }; 4617 static const int port_speed_max_50[] = { 4618 -1, 4619 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 4620 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 4621 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 4622 1, -1, -1, -1, 4623 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 4624 -1, -1, -1, -1, 10, 10, 10, 10, -1, -1, -1, -1, 4625 -1, -1, -1, -1, 4626 -1, -1, -1, -1, 42, -1, -1, -1, 42, -1, -1, -1, 4627 -1, -1, -1, -1, -1 4628 }; 4629 /* RNGR_XAUI_260: 12xXAUI + 3xF.HG[42] + 1GE */ 4630 static const int p2l_mapping_55[] = { 4631 0, 4632 1, -1, -1, -1, 2, -1, -1, -1, 3, -1, -1, -1, 4633 4, -1, -1, -1, 5, -1, -1, -1, 6, -1, -1, -1, 4634 7, -1, -1, -1, 8, -1, -1, -1, 9, -1, -1, -1, 4635 37, -1, -1, -1, 4636 10, -1, -1, -1, 11, -1, -1, -1, 12, -1, -1, -1, 4637 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4638 -1, -1, -1, -1, 4639 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 4640 61, 59, 58, 60, 62 4641 }; 4642 static const int flex_p2l_mapping_55[] = { 4643 0, 4644 1, -1, -1, -1, 2, -1, -1, -1, 3, -1, -1, -1, 4645 4, -1, -1, -1, 5, -1, -1, -1, 6, -1, -1, -1, 4646 7, -1, -1, -1, 8, -1, -1, -1, 9, -1, -1, -1, 4647 37, -1, -1, -1, 4648 10, -1, -1, -1, 11, -1, -1, -1, 12, -1, -1, -1, 4649 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4650 -1, -1, -1, -1, 4651 21, -1, -1, -1, 25, -1, -1, -1, 29, -1, -1, -1, 4652 61, 59, 58, 60, 62 4653 }; 4654 static const int p2m_mapping_55[] = { 4655 59, 4656 48, -1, -1, -1, 36, -1, -1, -1, 32, -1, -1, -1, 4657 37, -1, -1, -1, 49, -1, -1, -1, 38, -1, -1, -1, 4658 33, -1, -1, -1, 39, -1, -1, -1, 50, -1, -1, -1, 4659 60, -1, -1, -1, 4660 40, -1, -1, -1, 51, -1, -1, -1, 41, -1, -1, -1, 4661 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4662 -1, -1, -1, -1, 4663 52, 42, 34, 43, 53, 44, 35, 45, 54, 46, 55, 47, 4664 58, 62, 56, 61, 57 4665 }; 4666 static const int port_speed_max_55[] = { 4667 -1, 4668 10, -1, -1, -1, 10, -1, -1, -1, 10, -1, -1, -1, 4669 10, -1, -1, -1, 10, -1, -1, -1, 10, -1, -1, -1, 4670 10, -1, -1, -1, 10, -1, -1, -1, 10, -1, -1, -1, 4671 1, -1, -1, -1, 4672 10, -1, -1, -1, 10, -1, -1, -1, 10, -1, -1, -1, 4673 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4674 -1, -1, -1, -1, 4675 42, -1, -1, -1, 42, -1, -1, -1, 42, -1, -1, -1, 4676 -1, -1, -1, -1, -1 4677 }; 4678 static _soc_tr3_flex_port_inf_t flex_port_inf_55 = { 4679 1, 4680 { 17, 18, 19, -1 }, 4681 { _tr3_wc_flex_port_speeds_1, _tr3_wc_flex_port_speeds_1, 4682 _tr3_wc_flex_port_speeds_1, NULL }, 4683 { _tr3_wc_def_flex_port_speeds_1, _tr3_wc_def_flex_port_speeds_1, 4684 _tr3_wc_def_flex_port_speeds_1, NULL }, 4685 { _tr3_wc_flex_port_lanes_1, _tr3_wc_flex_port_lanes_1, 4686 _tr3_wc_flex_port_lanes_1, NULL } 4687 }; 4688 /* 12xXAUI + 2xF.HG[42] + 1GE */ 4689 static const int p2l_mapping_155[] = { 4690 0, 4691 1, -1, -1, -1, 2, -1, -1, -1, 3, -1, -1, -1, 4692 4, -1, -1, -1, 5, -1, -1, -1, 6, -1, -1, -1, 4693 7, -1, -1, -1, 8, -1, -1, -1, 9, -1, -1, -1, 4694 37, -1, -1, -1, 4695 10, -1, -1, -1, 11, -1, -1, -1, 12, -1, -1, -1, 4696 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4697 -1, -1, -1, -1, 4698 21, 22, 23, 24, 25, 26, 27, 28, -1, -1, -1, -1, 4699 61, 59, 58, 60, 62 4700 }; 4701 static const int flex_p2l_mapping_155[] = { 4702 0, 4703 1, -1, -1, -1, 2, -1, -1, -1, 3, -1, -1, -1, 4704 4, -1, -1, -1, 5, -1, -1, -1, 6, -1, -1, -1, 4705 7, -1, -1, -1, 8, -1, -1, -1, 9, -1, -1, -1, 4706 37, -1, -1, -1, 4707 10, -1, -1, -1, 11, -1, -1, -1, 12, -1, -1, -1, 4708 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4709 -1, -1, -1, -1, 4710 21, -1, -1, -1, 25, -1, -1, -1, -1, -1, -1, -1, 4711 61, 59, 58, 60, 62 4712 }; 4713 static const int p2m_mapping_155[] = { 4714 59, 4715 48, -1, -1, -1, 36, -1, -1, -1, 32, -1, -1, -1, 4716 37, -1, -1, -1, 49, -1, -1, -1, 38, -1, -1, -1, 4717 33, -1, -1, -1, 39, -1, -1, -1, 50, -1, -1, -1, 4718 60, -1, -1, -1, 4719 40, -1, -1, -1, 51, -1, -1, -1, 41, -1, -1, -1, 4720 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4721 -1, -1, -1, -1, 4722 52, 42, 34, 43, 53, 44, 35, 45, -1, -1, -1, -1, 4723 58, 62, 56, 61, 57 4724 }; 4725 static const int port_speed_max_155[] = { 4726 -1, 4727 10, -1, -1, -1, 10, -1, -1, -1, 10, -1, -1, -1, 4728 10, -1, -1, -1, 10, -1, -1, -1, 10, -1, -1, -1, 4729 10, -1, -1, -1, 10, -1, -1, -1, 10, -1, -1, -1, 4730 1, -1, -1, -1, 4731 10, -1, -1, -1, 10, -1, -1, -1, 10, -1, -1, -1, 4732 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4733 -1, -1, -1, -1, 4734 42, -1, -1, -1, 42, -1, -1, -1, -1, -1, -1, -1, 4735 -1, -1, -1, -1, -1 4736 }; 4737 static _soc_tr3_flex_port_inf_t flex_port_inf_155 = { 4738 1, 4739 { 17, 18, -1 }, 4740 { _tr3_wc_flex_port_speeds_1, _tr3_wc_flex_port_speeds_1, NULL }, 4741 { _tr3_wc_def_flex_port_speeds_1, _tr3_wc_def_flex_port_speeds_1, NULL }, 4742 { _tr3_wc_flex_port_lanes_1, _tr3_wc_flex_port_lanes_1, NULL } 4743 }; 4744 /* 3xF.40GE + 3xF.HG[42] */ 4745 static const int p2l_mapping_71[] = { 4746 0, 4747 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4748 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4749 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4750 1, -1, -1, -1, 4751 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4752 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 4753 -1, -1, -1, -1, 4754 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 4755 61, 59, 58, 60, 62 4756 }; 4757 static const int flex_p2l_mapping_71[] = { 4758 0, 4759 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4760 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4761 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4762 1, -1, -1, -1, 4763 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4764 5, -1, -1, -1, 9, -1, -1, -1, 13, -1, -1, -1, 4765 -1, -1, -1, -1, 4766 21, -1, -1, -1, 25, -1, -1, -1, 29, -1, -1, -1, 4767 61, 59, 58, 60, 62 4768 }; 4769 static const int p2m_mapping_71[] = { 4770 59, 4771 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4772 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4773 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4774 60, -1, -1, -1, 4775 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4776 48, 32, 33, 34, 49, 35, 36, 37, 50, 38, 51, 39, 4777 -1, -1, -1, -1, 4778 52, 40, 41, 42, 53, 43, 44, 45, 54, 46, 55, 47, 4779 58, 62, 56, 61, 57 4780 }; 4781 static const int port_speed_max_71[] = { 4782 -1, 4783 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4784 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4785 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4786 1, -1, -1, -1, 4787 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4788 40, -1, -1, -1, 40, -1, -1, -1, 40, -1, -1, -1, 4789 -1, -1, -1, -1, 4790 42, -1, -1, -1, 42, -1, -1, -1, 42, -1, -1, -1, 4791 -1, -1, -1, -1, -1 4792 }; 4793 static _soc_tr3_flex_port_inf_t flex_port_inf_71 = { 4794 1, 4795 { 13, 14, 15, 17, 18, 19, -1 }, 4796 { _tr3_wc_flex_port_speeds_3, _tr3_wc_flex_port_speeds_3, 4797 _tr3_wc_flex_port_speeds_3, _tr3_wc_flex_port_speeds_1, 4798 _tr3_wc_flex_port_speeds_1, _tr3_wc_flex_port_speeds_1, NULL }, 4799 { _tr3_wc_def_flex_port_speeds_3, _tr3_wc_def_flex_port_speeds_3, 4800 _tr3_wc_def_flex_port_speeds_3, _tr3_wc_def_flex_port_speeds_1, 4801 _tr3_wc_def_flex_port_speeds_1, _tr3_wc_def_flex_port_speeds_1, NULL }, 4802 { _tr3_wc_flex_port_lanes_3, _tr3_wc_flex_port_lanes_3, 4803 _tr3_wc_flex_port_lanes_3, _tr3_wc_flex_port_lanes_1, 4804 _tr3_wc_flex_port_lanes_1, _tr3_wc_flex_port_lanes_1, NULL } 4805 }; 4806 /* 3xF.HG[42] + 3xF.40GE */ 4807 static const int p2l_mapping_72[] = { 4808 0, 4809 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4810 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4811 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4812 1, -1, -1, -1, 4813 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4814 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 4815 -1, -1, -1, -1, 4816 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 4817 61, 59, 58, 60, 62 4818 }; 4819 static const int flex_p2l_mapping_72[] = { 4820 0, 4821 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4822 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4823 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4824 1, -1, -1, -1, 4825 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4826 5, -1, -1, -1, 9, -1, -1, -1, 13, -1, -1, -1, 4827 -1, -1, -1, -1, 4828 21, -1, -1, -1, 25, -1, -1, -1, 29, -1, -1, -1, 4829 61, 59, 58, 60, 62 4830 }; 4831 static const int p2m_mapping_72[] = { 4832 59, 4833 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4834 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4835 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4836 60, -1, -1, -1, 4837 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4838 52, 40, 41, 42, 53, 43, 44, 45, 54, 46, 55, 47, 4839 -1, -1, -1, -1, 4840 48, 32, 33, 34, 49, 35, 36, 37, 50, 38, 51, 39, 4841 58, 62, 56, 61, 57 4842 }; 4843 static const int port_speed_max_72[] = { 4844 -1, 4845 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4846 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4847 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4848 1, -1, -1, -1, 4849 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4850 42, -1, -1, -1, 42, -1, -1, -1, 42, -1, -1, -1, 4851 -1, -1, -1, -1, 4852 40, -1, -1, -1, 40, -1, -1, -1, 40, -1, -1, -1, 4853 -1, -1, -1, -1, -1 4854 }; 4855 static _soc_tr3_flex_port_inf_t flex_port_inf_72 = { 4856 1, 4857 { 13, 14, 15, 17, 18, 19, -1 }, 4858 { _tr3_wc_flex_port_speeds_1, _tr3_wc_flex_port_speeds_1, 4859 _tr3_wc_flex_port_speeds_1, _tr3_wc_flex_port_speeds_3, 4860 _tr3_wc_flex_port_speeds_3, _tr3_wc_flex_port_speeds_3, NULL }, 4861 { _tr3_wc_def_flex_port_speeds_1, _tr3_wc_def_flex_port_speeds_1, 4862 _tr3_wc_def_flex_port_speeds_1, _tr3_wc_def_flex_port_speeds_3, 4863 _tr3_wc_def_flex_port_speeds_3, _tr3_wc_def_flex_port_speeds_3, NULL }, 4864 { _tr3_wc_flex_port_lanes_1, _tr3_wc_flex_port_lanes_1, 4865 _tr3_wc_flex_port_lanes_1, _tr3_wc_flex_port_lanes_3, 4866 _tr3_wc_flex_port_lanes_3, _tr3_wc_flex_port_lanes_3, NULL } 4867 }; 4868 /* 3xF.40GE + 2xF.HG[42] */ 4869 static const int p2l_mapping_171[] = { 4870 0, 4871 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4872 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4873 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4874 1, -1, -1, -1, 4875 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4876 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 4877 -1, -1, -1, -1, 4878 21, 22, 23, 24, 25, 26, 27, 28, -1, -1, -1, -1, 4879 61, 59, 58, 60, 62 4880 }; 4881 static const int flex_p2l_mapping_171[] = { 4882 0, 4883 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4884 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4885 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4886 1, -1, -1, -1, 4887 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4888 5, -1, -1, -1, 9, -1, -1, -1, 13, -1, -1, -1, 4889 -1, -1, -1, -1, 4890 21, -1, -1, -1, 25, -1, -1, -1, -1, -1, -1, -1, 4891 61, 59, 58, 60, 62 4892 }; 4893 static const int p2m_mapping_171[] = { 4894 59, 4895 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4896 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4897 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4898 60, -1, -1, -1, 4899 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4900 48, 32, 33, 34, 49, 35, 36, 37, 50, 38, 51, 39, 4901 -1, -1, -1, -1, 4902 52, 40, 41, 42, 53, 43, 44, 45, -1, -1, -1, -1, 4903 58, 62, 56, 61, 57 4904 }; 4905 static const int port_speed_max_171[] = { 4906 -1, 4907 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4908 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4909 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4910 1, -1, -1, -1, 4911 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4912 40, -1, -1, -1, 40, -1, -1, -1, 40, -1, -1, -1, 4913 -1, -1, -1, -1, 4914 42, -1, -1, -1, 42, -1, -1, -1, -1, -1, -1, -1, 4915 -1, -1, -1, -1, -1 4916 }; 4917 static _soc_tr3_flex_port_inf_t flex_port_inf_171 = { 4918 1, 4919 { 13, 14, 15, 17, 18, -1 }, 4920 { _tr3_wc_flex_port_speeds_3, _tr3_wc_flex_port_speeds_3, 4921 _tr3_wc_flex_port_speeds_3, _tr3_wc_flex_port_speeds_1, 4922 _tr3_wc_flex_port_speeds_1, NULL }, 4923 { _tr3_wc_def_flex_port_speeds_3, _tr3_wc_def_flex_port_speeds_3, 4924 _tr3_wc_def_flex_port_speeds_3, _tr3_wc_def_flex_port_speeds_1, 4925 _tr3_wc_def_flex_port_speeds_1, NULL }, 4926 { _tr3_wc_flex_port_lanes_3, _tr3_wc_flex_port_lanes_3, 4927 _tr3_wc_flex_port_lanes_3, _tr3_wc_flex_port_lanes_1, 4928 _tr3_wc_flex_port_lanes_1, NULL } 4929 }; 4930 /* 3xF.HG[42] + 2xF.40GE */ 4931 static const int p2l_mapping_172[] = { 4932 0, 4933 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4934 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4935 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4936 1, -1, -1, -1, 4937 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4938 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 4939 -1, -1, -1, -1, 4940 21, 22, 23, 24, 25, 26, 27, 28, -1, -1, -1, -1, 4941 61, 59, 58, 60, 62 4942 }; 4943 static const int flex_p2l_mapping_172[] = { 4944 0, 4945 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4946 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4947 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4948 1, -1, -1, -1, 4949 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4950 5, -1, -1, -1, 9, -1, -1, -1, 13, -1, -1, -1, 4951 -1, -1, -1, -1, 4952 21, -1, -1, -1, 25, -1, -1, -1, -1, -1, -1, -1, 4953 61, 59, 58, 60, 62 4954 }; 4955 static const int p2m_mapping_172[] = { 4956 59, 4957 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4958 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4959 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4960 60, -1, -1, -1, 4961 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4962 52, 40, 41, 42, 53, 43, 44, 45, 54, 46, 55, 47, 4963 -1, -1, -1, -1, 4964 48, 32, 33, 34, 49, 35, 36, 37, -1, -1, -1, -1, 4965 58, 62, 56, 61, 57 4966 }; 4967 static const int port_speed_max_172[] = { 4968 -1, 4969 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4970 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4971 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4972 1, -1, -1, -1, 4973 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4974 42, -1, -1, -1, 42, -1, -1, -1, 42, -1, -1, -1, 4975 -1, -1, -1, -1, 4976 40, -1, -1, -1, 40, -1, -1, -1, -1, -1, -1, -1, 4977 -1, -1, -1, -1, -1 4978 }; 4979 static _soc_tr3_flex_port_inf_t flex_port_inf_172 = { 4980 1, 4981 { 13, 14, 15, 17, 18, 19, -1 }, 4982 { _tr3_wc_flex_port_speeds_1, _tr3_wc_flex_port_speeds_1, 4983 _tr3_wc_flex_port_speeds_1, _tr3_wc_flex_port_speeds_3, 4984 _tr3_wc_flex_port_speeds_3, NULL }, 4985 { _tr3_wc_def_flex_port_speeds_1, _tr3_wc_def_flex_port_speeds_1, 4986 _tr3_wc_def_flex_port_speeds_1, _tr3_wc_def_flex_port_speeds_3, 4987 _tr3_wc_def_flex_port_speeds_3, NULL }, 4988 { _tr3_wc_flex_port_lanes_1, _tr3_wc_flex_port_lanes_1, 4989 _tr3_wc_flex_port_lanes_1, _tr3_wc_flex_port_lanes_3, 4990 _tr3_wc_flex_port_lanes_3, NULL } 4991 }; 4992 /* 1x100GE + 8xHGd[16] */ 4993 static const int p2l_mapping_81[] = { 4994 0, 4995 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4996 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4997 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 4998 1, -1, -1, -1, 4999 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5000 5, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5001 17, -1, 19, -1, 5002 21, -1, 23, -1, 25, -1, 27, -1, 29, -1, 31, -1, 5003 61, 59, 58, 60, 62 5004 }; 5005 static const int p2m_mapping_81[] = { 5006 59, 5007 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5008 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5009 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5010 60, -1, -1, -1, 5011 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5012 48, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5013 53, -1, 33, -1, 5014 52, -1, 32, -1, 54, -1, 34, -1, 55, -1, 35, -1, 5015 58, 62, 56, 61, 57 5016 }; 5017 static const int port_speed_max_81[] = { 5018 -1, 5019 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5020 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5021 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5022 1, -1, -1, -1, 5023 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5024 100, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5025 16, -1, 16, -1, 5026 16, -1, 16, -1, 16, -1, 16, -1, 16, -1, 16, -1, 5027 -1, -1, -1, -1, -1 5028 }; 5029 /* 3xF.HG[42] + 4xHG[32] */ 5030 static const int p2l_mapping_82[] = { 5031 0, 5032 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5033 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5034 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5035 1, -1, -1, -1, 5036 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5037 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 5038 17, -1, -1, -1, 5039 21, -1, -1, -1, 25, -1, -1, -1, 29, -1, -1, -1, 5040 61, 59, 58, 60, 62 5041 }; 5042 static const int flex_p2l_mapping_82[] = { 5043 0, 5044 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5045 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5046 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5047 1, -1, -1, -1, 5048 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5049 5, -1, -1, -1, 9, -1, -1, -1, 13, -1, -1, -1, 5050 17, -1, -1, -1, 5051 21, -1, -1, -1, 25, -1, -1, -1, 29, -1, -1, -1, 5052 61, 59, 58, 60, 62 5053 }; 5054 static const int p2m_mapping_82[] = { 5055 59, 5056 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5057 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5058 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5059 60, -1, -1, -1, 5060 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5061 48, 40, 41, 42, 49, 43, 44, 45, 50, 46, 47, 51, 5062 53, -1, -1, -1, 5063 52, -1, -1, -1, 54, -1, -1, -1, 55, -1, -1, -1, 5064 58, 62, 56, 61, 57 5065 }; 5066 static const int port_speed_max_82[] = { 5067 -1, 5068 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5069 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5070 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5071 1, -1, -1, -1, 5072 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5073 42, -1, -1, -1, 42, -1, -1, -1, 42, -1, -1, -1, 5074 30, -1, -1, -1, 5075 30, -1, -1, -1, 30, -1, -1, -1, 30, -1, -1, -1, 5076 -1, -1, -1, -1, -1 5077 }; 5078 /* 3xF.HG[42] + 8xHGd[16] */ 5079 static const int p2l_mapping_83[] = { 5080 0, 5081 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5082 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5083 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5084 1, -1, -1, -1, 5085 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5086 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 5087 17, -1, 19, -1, 5088 21, -1, 23, -1, 25, -1, 27, -1, 29, -1, 31, -1, 5089 61, 59, 58, 60, 62 5090 }; 5091 static const int flex_p2l_mapping_83[] = { 5092 0, 5093 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5094 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5095 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5096 1, -1, -1, -1, 5097 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5098 5, -1, -1, -1, 9, -1, -1, -1, 13, -1, -1, -1, 5099 17, -1, 19, -1, 5100 21, -1, 23, -1, 25, -1, 27, -1, 29, -1, 31, -1, 5101 61, 59, 58, 60, 62 5102 }; 5103 static const int p2m_mapping_83[] = { 5104 59, 5105 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5106 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5107 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5108 60, -1, -1, -1, 5109 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5110 48, 40, 41, 42, 49, 43, 44, 45, 50, 46, 47, 51, 5111 53, -1, 33, -1, 5112 52, -1, 32, -1, 54, -1, 34, -1, 55, -1, 35, -1, 5113 58, 62, 56, 61, 57 5114 }; 5115 static const int port_speed_max_83[] = { 5116 -1, 5117 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5118 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5119 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5120 1, -1, -1, -1, 5121 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5122 42, -1, -1, -1, 42, -1, -1, -1, 42, -1, -1, -1, 5123 16, -1, 16, -1, 5124 16, -1, 16, -1, 16, -1, 16, -1, 16, -1, 16, -1, 5125 -1, -1, -1, -1, -1 5126 }; 5127 /* FB3_1G_200_HG25: 48xGE + 2xHG[21] + 2xHG[21] + 1GE */ 5128 static const int p2l_mapping_90[] = { 5129 0, 5130 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 5131 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 5132 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 5133 37, -1, -1, -1, 5134 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 5135 -1, -1, -1, -1, 50, -1, -1, -1, 51, -1, -1, -1, 5136 -1, -1, -1, -1, 5137 -1, -1, -1, -1, 52, -1, -1, -1, 53, -1, -1, -1, 5138 61, 59, 58, 60, 62 5139 }; 5140 static const int p2m_mapping_90[] = { 5141 59, 5142 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 5143 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 5144 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 5145 60, -1, -1, -1, 5146 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 5147 -1, -1, -1, -1, 48, -1, -1, -1, 49, -1, -1, -1, 5148 -1, -1, -1, -1, 5149 -1, -1, -1, -1, 50, -1, -1, -1, 51, -1, -1, -1, 5150 58, 62, 56, 61, 57 5151 }; 5152 static const int port_speed_max_90[] = { 5153 -1, 5154 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 5155 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 5156 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 5157 1, -1, -1, -1, 5158 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 5159 -1, -1, -1, -1, 25, -1, -1, -1, 25, -1, -1, -1, 5160 -1, -1, -1, -1, 5161 -1, -1, -1, -1, 25, -1, -1, -1, 25, -1, -1, -1, 5162 -1, -1, -1, -1, -1 5163 }; 5164 /* 56644: 24xGE-LR + 2xXAUI + 2xHG[21] + 1GE */ 5165 static const int p2l_mapping_190[] = { 5166 0, 5167 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 5168 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 5169 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5170 37, -1, -1, -1, 5171 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5172 -1, -1, -1, -1, 50, -1, -1, -1, 51, -1, -1, -1, 5173 -1, -1, -1, -1, 5174 -1, -1, -1, -1, 52, -1, -1, -1, 53, -1, -1, -1, 5175 61, 59, 58, 60, 62 5176 }; 5177 static const int p2m_mapping_190[] = { 5178 59, 5179 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 5180 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 5181 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5182 60, -1, -1, -1, 5183 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5184 -1, -1, -1, -1, 48, -1, -1, -1, 49, -1, -1, -1, 5185 -1, -1, -1, -1, 5186 -1, -1, -1, -1, 50, -1, -1, -1, 51, -1, -1, -1, 5187 58, 62, 56, 61, 57 5188 }; 5189 static const int port_speed_max_190[] = { 5190 -1, 5191 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 5192 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 5193 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5194 1, -1, -1, -1, 5195 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5196 -1, -1, -1, -1, 10, -1, -1, -1, 10, -1, -1, -1, 5197 -1, -1, -1, -1, 5198 -1, -1, -1, -1, 25, -1, -1, -1, 25, -1, -1, -1, 5199 -1, -1, -1, -1, -1 5200 }; 5201 /* FB4_XAUI_200_C: 10xF.XAUI + 4xHG[21] + 1GE */ 5202 static const int p2l_mapping_91[] = { 5203 0, 5204 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 5205 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 5206 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 5207 37, -1, -1, -1, 5208 -1, -1, -1, -1, -1, -1, -1, -1, 38, 39, 40, 41, 5209 -1, -1, -1, -1, 42, -1, -1, -1, 46, -1, -1, -1, 5210 -1, -1, -1, -1, 5211 -1, -1, -1, -1, 50, -1, -1, -1, 51, -1, -1, -1, 5212 61, 59, 58, 60, 62 5213 }; 5214 static const int flex_p2l_mapping_91[] = { 5215 0, 5216 1, -1, -1, -1, 5, -1, -1, -1, 9, -1, -1, -1, 5217 13, -1, -1, -1, 17, -1, -1, -1, 21, -1, -1, -1, 5218 25, -1, -1, -1, 29, -1, -1, -1, 33, -1, -1, -1, 5219 37, -1, -1, -1, 5220 -1, -1, -1, -1, -1, -1, -1, -1, 38, -1, -1, -1, 5221 -1, -1, -1, -1, 42, -1, -1, -1, 46, -1, -1, -1, 5222 -1, -1, -1, -1, 5223 -1, -1, -1, -1, 50, -1, -1, -1, 51, -1, -1, -1, 5224 61, 59, 58, 60, 62 5225 }; 5226 static const int p2m_mapping_91[] = { 5227 59, 5228 32, 0, 1, 2, 33, 3, 4, 5, 34, 6, 7, 8, 5229 35, 9, 10, 11, 45, 12, 13, 14, 46, 15, 16, 17, 5230 48, 18, 19, 20, 49, 21, 22, 23, 50, 24, 25, 26, 5231 60, -1, -1, -1, 5232 -1, -1, -1, -1, -1, -1, -1, -1, 51, 27, 28, 29, 5233 -1, -1, -1, -1, 52, -1, -1, -1, 53, -1, -1, -1, 5234 -1, -1, -1, -1, 5235 -1, -1, -1, -1, 54, -1, -1, -1, 55, -1, -1, -1, 5236 58, 62, 56, 61, 57 5237 }; 5238 static const int port_speed_max_91[] = { 5239 -1, 5240 10, -1, -1, -1, 10, -1, -1, -1, 10, -1, -1, -1, 5241 10, -1, -1, -1, 10, -1, -1, -1, 10, -1, -1, -1, 5242 10, -1, -1, -1, 10, -1, -1, -1, 10, -1, -1, -1, 5243 1, -1, -1, -1, 5244 -1, -1, -1, -1, -1, -1, -1, -1, 10, -1, -1, -1, 5245 -1, -1, -1, -1, 21, -1, -1, -1, 21, -1, -1, -1, 5246 -1, -1, -1, -1, 5247 -1, -1, -1, -1, 21, -1, -1, -1, 21, -1, -1, -1, 5248 -1, -1, -1, -1, -1 5249 }; 5250 static _soc_tr3_flex_port_inf_t flex_port_inf_91 = { 5251 1, 5252 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 12, -1 }, 5253 { _tr3_xc_flex_port_speeds, _tr3_xc_flex_port_speeds, 5254 _tr3_xc_flex_port_speeds, _tr3_xc_flex_port_speeds, 5255 _tr3_xc_flex_port_speeds, _tr3_xc_flex_port_speeds, 5256 _tr3_xc_flex_port_speeds, _tr3_xc_flex_port_speeds, 5257 _tr3_xc_flex_port_speeds, _tr3_xc_flex_port_speeds, NULL }, 5258 { _tr3_xc_def_flex_port_speeds, _tr3_xc_def_flex_port_speeds, 5259 _tr3_xc_def_flex_port_speeds, _tr3_xc_def_flex_port_speeds, 5260 _tr3_xc_def_flex_port_speeds, _tr3_xc_def_flex_port_speeds, 5261 _tr3_xc_def_flex_port_speeds, _tr3_xc_def_flex_port_speeds, 5262 _tr3_xc_def_flex_port_speeds, _tr3_xc_def_flex_port_speeds, NULL }, 5263 { _tr3_xc_flex_port_lanes, _tr3_xc_flex_port_lanes, 5264 _tr3_xc_flex_port_lanes, _tr3_xc_flex_port_lanes, 5265 _tr3_xc_flex_port_lanes, _tr3_xc_flex_port_lanes, 5266 _tr3_xc_flex_port_lanes, _tr3_xc_flex_port_lanes, 5267 _tr3_xc_flex_port_lanes, _tr3_xc_flex_port_lanes, NULL } 5268 }; 5269 /* FB4_XAUI_200_F: 4xXAUI + 12xXFI + 1GE */ 5270 static const int p2l_mapping_94[] = { 5271 0, 5272 1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5273 -1, -1, -1, -1, 17, -1, -1, -1, -1, -1, -1, -1, 5274 -1, -1, -1, -1, 29, -1, -1, -1, -1, -1, -1, -1, 5275 37, -1, -1, -1, 5276 -1, -1, -1, -1, -1, -1, -1, -1, 38, -1, -1, -1, 5277 -1, -1, -1, -1, 42, 43, 44, 45, -1, -1, -1, -1, 5278 -1, -1, -1, -1, 5279 -1, -1, -1, -1, 46, 47, 48, 49, 50, 51, 52, 53, 5280 61, 59, 58, 60, 62 5281 }; 5282 static const int p2m_mapping_94[] = { 5283 59, 5284 40, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5285 -1, -1, -1, -1, 41, -1, -1, -1, -1, -1, -1, -1, 5286 -1, -1, -1, -1, 42, -1, -1, -1, -1, -1, -1, -1, 5287 60, -1, -1, -1, 5288 -1, -1, -1, -1, -1, -1, -1, -1, 43, -1, -1, -1, 5289 -1, -1, -1, -1, 48, 32, 33, 34, -1, -1, -1, -1, 5290 -1, -1, -1, -1, 5291 -1, -1, -1, -1, 49, 35, 50, 51, 52, 53, 54, 55, 5292 58, 62, 56, 61, 57 5293 }; 5294 static const int port_speed_max_94[] = { 5295 -1, 5296 10, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5297 -1, -1, -1, -1, 10, -1, -1, -1, -1, -1, -1, -1, 5298 -1, -1, -1, -1, 10, -1, -1, -1, -1, -1, -1, -1, 5299 1, -1, -1, -1, 5300 -1, -1, -1, -1, -1, -1, -1, -1, 10, -1, -1, -1, 5301 -1, -1, -1, -1, 10, 10, 10, 10, -1, -1, -1, -1, 5302 -1, -1, -1, -1, 5303 -1, -1, -1, -1, 10, 10, 10, 10, 10, 10, 10, 10, 5304 -1, -1, -1, -1, -1 5305 }; 5306 /* TR3_1G_280: 48xGE + 4xXFI + 4xHG[42] + 1GE */ 5307 static const int p2l_mapping_95[] = { 5308 0, 5309 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 5310 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 5311 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 5312 37, -1, -1, -1, 5313 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 5314 -1, -1, -1, -1, 50, 51, 52, 53, -1, -1, -1, -1, 5315 54, -1, -1, -1, 5316 55, -1, -1, -1, 56, -1, -1, -1, 57, -1, -1, -1, 5317 61, 59, 58, 60, 62 5318 }; 5319 static const int p2m_mapping_95[] = { 5320 59, 5321 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 5322 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 5323 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 5324 60, -1, -1, -1, 5325 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 5326 -1, -1, -1, -1, 48, 49, 50, 51, -1, -1, -1, -1, 5327 52, -1, -1, -1, 5328 53, -1, -1, -1, 54, -1, -1, -1, 55, -1, -1, -1, 5329 58, 62, 56, 61, 57 5330 }; 5331 static const int port_speed_max_95[] = { 5332 -1, 5333 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 5334 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 5335 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 5336 1, -1, -1, -1, 5337 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 5338 -1, -1, -1, -1, 10, 10, 10, 10, -1, -1, -1, -1, 5339 42, -1, -1, -1, 5340 42, -1, -1, -1, 42, -1, -1, -1, 42, -1, -1, -1, 5341 -1, -1, -1, -1, -1 5342 }; 5343 /* 48xGE + 1x40GE + 4xHG[42] + 1GE */ 5344 static const int p2l_mapping_195[] = { 5345 0, 5346 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 5347 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 5348 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 5349 37, -1, -1, -1, 5350 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 5351 -1, -1, -1, -1, 50, -1, -1, -1, -1, -1, -1, -1, 5352 54, -1, -1, -1, 5353 55, -1, -1, -1, 56, -1, -1, -1, 57, -1, -1, -1, 5354 61, 59, 58, 60, 62 5355 }; 5356 static const int p2m_mapping_195[] = { 5357 59, 5358 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 5359 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 5360 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 5361 60, -1, -1, -1, 5362 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 5363 -1, -1, -1, -1, 48, -1, -1, -1, -1, -1, -1, -1, 5364 52, -1, -1, -1, 5365 53, -1, -1, -1, 54, -1, -1, -1, 55, -1, -1, -1, 5366 58, 62, 56, 61, 57 5367 }; 5368 static const int port_speed_max_195[] = { 5369 -1, 5370 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 5371 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 5372 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 5373 1, -1, -1, -1, 5374 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 5375 -1, -1, -1, -1, 40, -1, -1, -1, -1, -1, -1, -1, 5376 42, -1, -1, -1, 5377 42, -1, -1, -1, 42, -1, -1, -1, 42, -1, -1, -1, 5378 -1, -1, -1, -1, -1 5379 }; 5380 /* TR3_1G_280: 48xGE + 4xXFI + 1xHG[127] + 1GE */ 5381 static const int p2l_mapping_295[] = { 5382 0, 5383 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 5384 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 5385 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 5386 37, -1, -1, -1, 5387 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 5388 -1, -1, -1, -1, 50, 51, 52, 53, -1, -1, -1, -1, 5389 -1, -1, -1, -1, 5390 55, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5391 61, 59, 58, 60, 62 5392 }; 5393 static const int p2m_mapping_295[] = { 5394 59, 5395 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 5396 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 5397 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 5398 60, -1, -1, -1, 5399 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 5400 -1, -1, -1, -1, 48, 49, 50, 51, -1, -1, -1, -1, 5401 -1, -1, -1, -1, 5402 52, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5403 58, 62, 56, 61, 57 5404 }; 5405 static const int port_speed_max_295[] = { 5406 -1, 5407 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 5408 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 5409 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 5410 1, -1, -1, -1, 5411 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 5412 -1, -1, -1, -1, 10, 10, 10, 10, -1, -1, -1, -1, 5413 -1, -1, -1, -1, 5414 127, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5415 -1, -1, -1, -1, -1 5416 }; 5417 /* 28xGE + 4xXFI + 4xHG[42] + 1GE */ 5418 static const int p2l_mapping_395[] = { 5419 0, 5420 -1, -1, -1, -1, -1, -1, -1, -1, 1, 2, 3, 4, 5421 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 5422 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 5423 29, -1, -1, -1, 5424 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5425 -1, -1, -1, -1, 50, 51, 52, 53, -1, -1, -1, -1, 5426 54, -1, -1, -1, 5427 55, -1, -1, -1, 56, -1, -1, -1, 57, -1, -1, -1, 5428 61, 59, 58, 60, 62 5429 }; 5430 static const int p2m_mapping_395[] = { 5431 59, 5432 -1, -1, -1, -1, -1, -1, -1, -1, 0, 1, 2, 3, 5433 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 5434 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 5435 60, -1, -1, -1, 5436 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5437 -1, -1, -1, -1, 48, 49, 50, 51, -1, -1, -1, -1, 5438 52, -1, -1, -1, 5439 53, -1, -1, -1, 54, -1, -1, -1, 55, -1, -1, -1, 5440 58, 62, 56, 61, 57 5441 }; 5442 static const int port_speed_max_395[] = { 5443 -1, 5444 -1, -1, -1, -1, -1, -1, -1, -1, 1, 1, 1, 1, 5445 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 5446 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 5447 1, -1, -1, -1, 5448 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5449 -1, -1, -1, -1, 10, 10, 10, 10, -1, -1, -1, -1, 5450 42, -1, -1, -1, 5451 42, -1, -1, -1, 42, -1, -1, -1, 42, -1, -1, -1, 5452 -1, -1, -1, -1, -1 5453 }; 5454 /* 28xGE + 1x40GE + 4xHG[42] + 1GE */ 5455 static const int p2l_mapping_495[] = { 5456 0, 5457 -1, -1, -1, -1, -1, -1, -1, -1, 1, 2, 3, 4, 5458 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 5459 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 5460 29, -1, -1, -1, 5461 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5462 -1, -1, -1, -1, 50, -1, -1, -1, -1, -1, -1, -1, 5463 54, -1, -1, -1, 5464 55, -1, -1, -1, 56, -1, -1, -1, 57, -1, -1, -1, 5465 61, 59, 58, 60, 62 5466 }; 5467 static const int p2m_mapping_495[] = { 5468 59, 5469 -1, -1, -1, -1, -1, -1, -1, -1, 0, 1, 2, 3, 5470 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 5471 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 5472 60, -1, -1, -1, 5473 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5474 -1, -1, -1, -1, 48, -1, -1, -1, -1, -1, -1, -1, 5475 52, -1, -1, -1, 5476 53, -1, -1, -1, 54, -1, -1, -1, 55, -1, -1, -1, 5477 58, 62, 56, 61, 57 5478 }; 5479 static const int port_speed_max_495[] = { 5480 -1, 5481 -1, -1, -1, -1, -1, -1, -1, -1, 1, 1, 1, 1, 5482 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 5483 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 5484 1, -1, -1, -1, 5485 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5486 -1, -1, -1, -1, 40, -1, -1, -1, -1, -1, -1, -1, 5487 42, -1, -1, -1, 5488 42, -1, -1, -1, 42, -1, -1, -1, 42, -1, -1, -1, 5489 -1, -1, -1, -1, -1 5490 }; 5491 static const int port_speed_max_595[] = { 5492 -1, 5493 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 5494 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 5495 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 5496 1, -1, -1, -1, 5497 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 5498 -1, -1, -1, -1, 11, 11, 11, 11, -1, -1, -1, -1, 5499 42, -1, -1, -1, 5500 42, -1, -1, -1, 42, -1, -1, -1, 42, -1, -1, -1, 5501 -1, -1, -1, -1, -1 5502 }; 5503 static const int port_speed_max_695[] = { 5504 -1, 5505 -1, -1, -1, -1, -1, -1, -1, -1, 1, 1, 1, 1, 5506 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 5507 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 5508 1, -1, -1, -1, 5509 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5510 -1, -1, -1, -1, 11, 11, 11, 11, -1, -1, -1, -1, 5511 42, -1, -1, -1, 5512 42, -1, -1, -1, 42, -1, -1, -1, 42, -1, -1, -1, 5513 -1, -1, -1, -1, -1 5514 }; 5515 /* FB3_1G_200_XFI: 48xGE + 8xXFI + 1GE */ 5516 static const int p2l_mapping_96[] = { 5517 0, 5518 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 5519 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 5520 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 5521 37, -1, -1, -1, 5522 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 5523 -1, -1, -1, -1, 50, 51, 52, 53, 54, 55, 56, 57, 5524 -1, -1, -1, -1, 5525 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5526 61, 59, 58, 60, 62 5527 }; 5528 static const int p2m_mapping_96[] = { 5529 59, 5530 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 5531 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 5532 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 5533 60, -1, -1, -1, 5534 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 5535 -1, -1, -1, -1, 48, 49, 50, 51, 52, 53, 54, 55, 5536 -1, -1, -1, -1, 5537 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5538 58, 62, 56, 61, 57 5539 }; 5540 static const int port_speed_max_96[] = { 5541 -1, 5542 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 5543 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 5544 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 5545 1, -1, -1, -1, 5546 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 5547 -1, -1, -1, -1, 10, 10, 10, 10, 10, 10, 10, 10, 5548 -1, -1, -1, -1, 5549 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5550 -1, -1, -1, -1, -1 5551 }; 5552 /* 56541/56546: 28xGE + 8xXFI + 1GE */ 5553 static const int p2l_mapping_196[] = { 5554 0, 5555 -1, -1, -1, -1, -1, -1, -1, -1, 1, 2, 3, 4, 5556 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 5557 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 5558 37, -1, -1, -1, 5559 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5560 -1, -1, -1, -1, 50, 51, 52, 53, 54, 55, 56, 57, 5561 -1, -1, -1, -1, 5562 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5563 61, 59, 58, 60, 62 5564 }; 5565 static const int p2m_mapping_196[] = { 5566 59, 5567 -1, -1, -1, -1, -1, -1, -1, -1, 0, 1, 2, 3, 5568 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 5569 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 5570 60, -1, -1, -1, 5571 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5572 -1, -1, -1, -1, 48, 49, 50, 51, 52, 53, 54, 55, 5573 -1, -1, -1, -1, 5574 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5575 58, 62, 56, 61, 57 5576 }; 5577 static const int port_speed_max_196[] = { 5578 -1, 5579 -1, -1, -1, -1, -1, -1, -1, -1, 1, 1, 1, 1, 5580 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 5581 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 5582 1, -1, -1, -1, 5583 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5584 -1, -1, -1, -1, 10, 10, 10, 10, 10, 10, 10, 10, 5585 -1, -1, -1, -1, 5586 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5587 -1, -1, -1, -1, -1 5588 }; 5589 /* 10xF.XAUI + 4xXFI */ 5590 static const int p2l_mapping_97[] = { 5591 0, 5592 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 5593 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 5594 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 5595 37, -1, -1, -1, 5596 -1, -1, -1, -1, -1, -1, -1, -1, 38, 39, 40, 41, 5597 -1, -1, -1, -1, 42, 43, 44, 45, -1, -1, -1, -1, 5598 -1, -1, -1, -1, 5599 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5600 61, 59, 58, 60, 62 5601 }; 5602 static const int flex_p2l_mapping_97[] = { 5603 0, 5604 1, -1, -1, -1, 5, -1, -1, -1, 9, -1, -1, -1, 5605 13, -1, -1, -1, 17, -1, -1, -1, 21, -1, -1, -1, 5606 25, -1, -1, -1, 29, -1, -1, -1, 33, -1, -1, -1, 5607 37, -1, -1, -1, 5608 -1, -1, -1, -1, -1, -1, -1, -1, 38, -1, -1, -1, 5609 -1, -1, -1, -1, 42, 43, 44, 45, -1, -1, -1, -1, 5610 -1, -1, -1, -1, 5611 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5612 61, 59, 58, 60, 62 5613 }; 5614 static const int p2m_mapping_97[] = { 5615 59, 5616 32, 0, 1, 2, 33, 3, 4, 5, 34, 6, 7, 8, 5617 35, 9, 10, 11, 45, 12, 13, 14, 46, 15, 16, 17, 5618 48, 18, 19, 20, 49, 21, 22, 23, 50, 24, 25, 26, 5619 60, -1, -1, -1, 5620 -1, -1, -1, -1, -1, -1, -1, -1, 51, 27, 28, 29, 5621 -1, -1, -1, -1, 52, 53, 54, 55, -1, -1, -1, -1, 5622 -1, -1, -1, -1, 5623 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5624 58, 62, 56, 61, 57 5625 }; 5626 static const int port_speed_max_97[] = { 5627 -1, 5628 10, -1, -1, -1, 10, -1, -1, -1, 10, -1, -1, -1, 5629 10, -1, -1, -1, 10, -1, -1, -1, 10, -1, -1, -1, 5630 10, -1, -1, -1, 10, -1, -1, -1, 10, -1, -1, -1, 5631 1, -1, -1, -1, 5632 -1, -1, -1, -1, -1, -1, -1, -1, 10, -1, -1, -1, 5633 -1, -1, -1, -1, 10, 10, 10, 10, -1, -1, -1, -1, 5634 -1, -1, -1, -1, 5635 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5636 -1, -1, -1, -1, -1 5637 }; 5638 /* 10xF.XAUI + 2xHG[42] */ 5639 static const int p2l_mapping_98[] = { 5640 0, 5641 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 5642 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 5643 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 5644 37, -1, -1, -1, 5645 -1, -1, -1, -1, -1, -1, -1, -1, 38, 39, 40, 41, 5646 -1, -1, -1, -1, 42, -1, -1, -1, 46, -1, -1, -1, 5647 -1, -1, -1, -1, 5648 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5649 61, 59, 58, 60, 62 5650 }; 5651 static const int flex_p2l_mapping_98[] = { 5652 0, 5653 1, -1, -1, -1, 5, -1, -1, -1, 9, -1, -1, -1, 5654 13, -1, -1, -1, 17, -1, -1, -1, 21, -1, -1, -1, 5655 25, -1, -1, -1, 29, -1, -1, -1, 33, -1, -1, -1, 5656 37, -1, -1, -1, 5657 -1, -1, -1, -1, -1, -1, -1, -1, 38, -1, -1, -1, 5658 -1, -1, -1, -1, 42, -1, -1, -1, 46, -1, -1, -1, 5659 -1, -1, -1, -1, 5660 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5661 61, 59, 58, 60, 62 5662 }; 5663 static const int p2m_mapping_98[] = { 5664 59, 5665 32, 0, 1, 2, 33, 3, 4, 5, 34, 6, 7, 8, 5666 35, 9, 10, 11, 45, 12, 13, 14, 46, 15, 16, 17, 5667 48, 18, 19, 20, 49, 21, 22, 23, 50, 24, 25, 26, 5668 60, -1, -1, -1, 5669 -1, -1, -1, -1, -1, -1, -1, -1, 51, 27, 28, 29, 5670 -1, -1, -1, -1, 52, -1, -1, -1, 53, -1, -1, -1, 5671 -1, -1, -1, -1, 5672 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5673 58, 62, 56, 61, 57 5674 }; 5675 static const int port_speed_max_98[] = { 5676 -1, 5677 10, -1, -1, -1, 10, -1, -1, -1, 10, -1, -1, -1, 5678 10, -1, -1, -1, 10, -1, -1, -1, 10, -1, -1, -1, 5679 10, -1, -1, -1, 10, -1, -1, -1, 10, -1, -1, -1, 5680 1, -1, -1, -1, 5681 -1, -1, -1, -1, -1, -1, -1, -1, 10, -1, -1, -1, 5682 -1, -1, -1, -1, 42, -1, -1, -1, 42, -1, -1, -1, 5683 -1, -1, -1, -1, 5684 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5685 -1, -1, -1, -1, -1 5686 }; 5687 /* 56546: 24xGE + 4xXAUI + 2xXFI + 2xHG[12] + 1GE */ 5688 static const int p2l_mapping_99[] = { 5689 0, 5690 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 5691 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 5692 25, -1, -1, -1, 26, -1, -1, -1, 27, -1, -1, -1, 5693 28, -1, -1, -1, 5694 -1, -1, -1, -1, -1, -1, -1, -1, 29, -1, -1, -1, 5695 -1, -1, -1, -1, 30, 31, -1, -1, -1, -1, -1, -1, 5696 -1, -1, -1, -1, 5697 -1, -1, -1, -1, 32, -1, -1, -1, 33, -1, -1, -1, 5698 61, 59, 58, 60, 62 5699 }; 5700 static const int p2m_mapping_99[] = { 5701 59, 5702 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 5703 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 5704 49, -1, -1, -1, 50, -1, -1, -1, 51, -1, -1, -1, 5705 60, -1, -1, -1, 5706 -1, -1, -1, -1, -1, -1, -1, -1, 53, -1, -1, -1, 5707 -1, -1, -1, -1, 54, 55, -1, -1, -1, -1, -1, -1, 5708 -1, -1, -1, -1, 5709 -1, -1, -1, -1, 48, -1, -1, -1, 52, -1, -1, -1, 5710 58, 62, 56, 61, 57 5711 }; 5712 static const int port_speed_max_99[] = { 5713 -1, 5714 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 5715 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 5716 10, -1, -1, -1, 10, -1, -1, -1, 10, -1, -1, -1, 5717 1, -1, -1, -1, 5718 -1, -1, -1, -1, -1, -1, -1, -1, 10, -1, -1, -1, 5719 -1, -1, -1, -1, 10, 10, -1, -1, -1, -1, -1, -1, 5720 -1, -1, -1, -1, 5721 -1, -1, -1, -1, 12, -1, -1, -1, 12, -1, -1, -1, 5722 -1, -1, -1, -1, -1 5723 }; 5724 /* TR3_1G_280_FX: 36xGE + 4xXFI + 2xF.HG[42] + 2xHG[42] + 1GE */ 5725 static const int p2l_mapping_100[] = { 5726 0, 5727 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 5728 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 5729 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 5730 37, -1, -1, -1, 5731 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5732 -1, -1, -1, -1, 42, 43, 44, 45, -1, -1, -1, -1, 5733 46, -1, -1, -1, 5734 47, -1, -1, -1, 48, 49, 50, 51, 52, 53, 54, 55, 5735 61, 59, 58, 60, 62 5736 }; 5737 static const int flex_p2l_mapping_100[] = { 5738 0, 5739 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 5740 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 5741 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 5742 37, -1, -1, -1, 5743 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5744 -1, -1, -1, -1, 42, 43, 44, 45, -1, -1, -1, -1, 5745 46, -1, -1, -1, 5746 47, -1, -1, -1, 48, -1, -1, -1, 52, -1, -1, -1, 5747 61, 59, 58, 60, 62 5748 }; 5749 static const int p2m_mapping_100[] = { 5750 59, 5751 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 5752 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 5753 24, 25, 26, 27, 28, 29, 30, 31, 36, 37, 38, 39, 5754 60, -1, -1, -1, 5755 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5756 -1, -1, -1, -1, 32, 33, 34, 35, -1, -1, -1, -1, 5757 48, -1, -1, -1, 5758 49, -1, -1, -1, 54, 46, 50, 47, 55, 52, 51, 53, 5759 58, 62, 56, 61, 57 5760 }; 5761 static const int port_speed_max_100[] = { 5762 -1, 5763 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 5764 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 5765 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 5766 1, -1, -1, -1, 5767 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5768 -1, -1, -1, -1, 10, 10, 10, 10, -1, -1, -1, -1, 5769 42, -1, -1, -1, 5770 42, -1, -1, -1, 42, -1, -1, -1, 42, -1, -1, -1, 5771 -1, -1, -1, -1, -1 5772 }; 5773 static _soc_tr3_flex_port_inf_t flex_port_inf_100 = { 5774 1, 5775 { 18, 19, -1 }, 5776 { _tr3_wc_flex_port_speeds_1, _tr3_wc_flex_port_speeds_1, NULL }, 5777 { _tr3_wc_def_flex_port_speeds_1, _tr3_wc_def_flex_port_speeds_1, NULL }, 5778 { _tr3_wc_flex_port_lanes_1, _tr3_wc_flex_port_lanes_1, NULL } 5779 }; 5780 /* 28xGE + 4xXFI + 2xF.HG[42] + 2xHG[42] + 1GE */ 5781 static const int p2l_mapping_101[] = { 5782 0, 5783 -1, -1, -1, -1, -1, -1, -1, -1, 1, 2, 3, 4, 5784 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 5785 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 5786 37, -1, -1, -1, 5787 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5788 -1, -1, -1, -1, 42, 43, 44, 45, -1, -1, -1, -1, 5789 46, -1, -1, -1, 5790 47, -1, -1, -1, 48, 49, 50, 51, 52, 53, 54, 55, 5791 61, 59, 58, 60, 62 5792 }; 5793 static const int flex_p2l_mapping_101[] = { 5794 0, 5795 -1, -1, -1, -1, -1, -1, -1, -1, 1, 2, 3, 4, 5796 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 5797 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 5798 37, -1, -1, -1, 5799 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5800 -1, -1, -1, -1, 42, 43, 44, 45, -1, -1, -1, -1, 5801 46, -1, -1, -1, 5802 47, -1, -1, -1, 48, -1, -1, -1, 52, -1, -1, -1, 5803 61, 59, 58, 60, 62 5804 }; 5805 static const int p2m_mapping_101[] = { 5806 59, 5807 -1, -1, -1, -1, -1, -1, -1, -1, 0, 1, 2, 3, 5808 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 5809 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 5810 60, -1, -1, -1, 5811 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5812 -1, -1, -1, -1, 32, 33, 34, 35, -1, -1, -1, -1, 5813 48, -1, -1, -1, 5814 49, -1, -1, -1, 54, 46, 50, 47, 55, 52, 51, 53, 5815 58, 62, 56, 61, 57 5816 }; 5817 static const int port_speed_max_101[] = { 5818 -1, 5819 -1, -1, -1, -1, -1, -1, -1, -1, 1, 1, 1, 1, 5820 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 5821 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 5822 1, -1, -1, -1, 5823 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5824 -1, -1, -1, -1, 10, 10, 10, 10, -1, -1, -1, -1, 5825 42, -1, -1, -1, 5826 42, -1, -1, -1, 42, -1, -1, -1, 42, -1, -1, -1, 5827 -1, -1, -1, -1, -1 5828 }; 5829 /* TR3_1G_280_FX: 36xGE + 4xXFI + 2xHG[42] + 2xF.HG[42] + 1GE */ 5830 static const int p2l_mapping_102[] = { 5831 0, 5832 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 5833 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 5834 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 5835 37, -1, -1, -1, 5836 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5837 -1, -1, -1, -1, 42, 43, 44, 45, -1, -1, -1, -1, 5838 46, 47, 48, 49, 5839 50, 51, 52, 53, 54, -1, -1, -1, 55, -1, -1, -1, 5840 61, 59, 58, 60, 62 5841 }; 5842 static const int flex_p2l_mapping_102[] = { 5843 0, 5844 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 5845 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 5846 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 5847 37, -1, -1, -1, 5848 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5849 -1, -1, -1, -1, 42, 43, 44, 45, -1, -1, -1, -1, 5850 46, -1, -1, -1, 5851 50, -1, -1, -1, 54, -1, -1, -1, 55, -1, -1, -1, 5852 61, 59, 58, 60, 62 5853 }; 5854 static const int p2m_mapping_102[] = { 5855 59, 5856 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 5857 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 5858 24, 25, 26, 27, 28, 29, 30, 31, 36, 37, 38, 39, 5859 60, -1, -1, -1, 5860 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5861 -1, -1, -1, -1, 32, 33, 34, 35, -1, -1, -1, -1, 5862 48, 46, 50, 47, 5863 49, 52, 51, 53, 54, -1, -1, -1, 55, -1, -1, -1, 5864 58, 62, 56, 61, 57 5865 }; 5866 static _soc_tr3_flex_port_inf_t flex_port_inf_102 = { 5867 1, 5868 { 16, 17, -1 }, 5869 { _tr3_wc_flex_port_speeds_1, _tr3_wc_flex_port_speeds_1, NULL }, 5870 { _tr3_wc_def_flex_port_speeds_1, _tr3_wc_def_flex_port_speeds_1, NULL }, 5871 { _tr3_wc_flex_port_lanes_1, _tr3_wc_flex_port_lanes_1, NULL } 5872 }; 5873 /* TR3_1G_280: 48xGE + 4xXFI + 4xHG[42] + 1GE */ 5874 static const int p2l_mapping_103[] = { 5875 0, 5876 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 5877 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 5878 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 5879 37, -1, -1, -1, 5880 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 5881 -1, -1, -1, -1, 50, 51, 52, 53, -1, -1, -1, -1, 5882 -1, -1, -1, -1, 5883 -1, -1, -1, -1, 56, -1, -1, -1, 57, -1, -1, -1, 5884 61, 59, 58, 60, 62 5885 }; 5886 static const int p2m_mapping_103[] = { 5887 59, 5888 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 5889 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 5890 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 5891 60, -1, -1, -1, 5892 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 5893 -1, -1, -1, -1, 48, 49, 50, 51, -1, -1, -1, -1, 5894 -1, -1, -1, -1, 5895 -1, -1, -1, -1, 54, -1, -1, -1, 55, -1, -1, -1, 5896 58, 62, 56, 61, 57 5897 }; 5898 static const int port_speed_max_103[] = { 5899 -1, 5900 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 5901 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 5902 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 5903 1, -1, -1, -1, 5904 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 5905 -1, -1, -1, -1, 11, 11, 11, 11, -1, -1, -1, -1, 5906 -1, -1, -1, -1, 5907 -1, -1, -1, -1, 42, -1, -1, -1, 42, -1, -1, -1, 5908 -1, -1, -1, -1, -1 5909 }; 5910 /* TR3_1G_280: 48xGE + 1x40 + 4xHG[42] + 1GE */ 5911 static const int p2l_mapping_203[] = { 5912 0, 5913 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 5914 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 5915 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 5916 37, -1, -1, -1, 5917 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 5918 -1, -1, -1, -1, 50, -1, -1, -1, -1, -1, -1, -1, 5919 -1, -1, -1, -1, 5920 -1, -1, -1, -1, 56, -1, -1, -1, 57, -1, -1, -1, 5921 -1, -1, -1, -1, 5922 -1, -1, -1, -1, 56, -1, -1, -1, 57, -1, -1, -1, 5923 61, 59, 58, 60, 62 5924 }; 5925 static const int p2m_mapping_203[] = { 5926 59, 5927 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 5928 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 5929 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 5930 60, -1, -1, -1, 5931 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 5932 -1, -1, -1, -1, 48, -1, -1, -1, -1, -1, -1, -1, 5933 -1, -1, -1, -1, 5934 -1, -1, -1, -1, 54, -1, -1, -1, 55, -1, -1, -1, 5935 58, 62, 56, 61, 57 5936 }; 5937 static const int port_speed_max_203[] = { 5938 -1, 5939 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 5940 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 5941 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 5942 1, -1, -1, -1, 5943 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 5944 -1, -1, -1, -1, 40, -1, -1, -1, -1, -1, -1, -1, 5945 -1, -1, -1, -1, 5946 -1, -1, -1, -1, 42, -1, -1, -1, 42, -1, -1, -1, 5947 -1, -1, -1, -1, -1 5948 }; 5949 /* TR3_1G_280: 28xGE + 4xXFI + 4xHG[42] + 1GE */ 5950 static const int p2l_mapping_303[] = { 5951 0, 5952 -1, -1, -1, -1, -1, -1, -1, -1, 1, 2, 3, 4, 5953 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 5954 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 5955 29, -1, -1, -1, 5956 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5957 -1, -1, -1, -1, 50, 51, 52, 53, -1, -1, -1, -1, 5958 -1, -1, -1, -1, 5959 -1, -1, -1, -1, 56, -1, -1, -1, 57, -1, -1, -1, 5960 61, 59, 58, 60, 62 5961 }; 5962 static const int p2m_mapping_303[] = { 5963 59, 5964 -1, -1, -1, -1, -1, -1, -1, -1, 0, 1, 2, 3, 5965 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 5966 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 5967 60, -1, -1, -1, 5968 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5969 -1, -1, -1, -1, 48, 49, 50, 51, -1, -1, -1, -1, 5970 -1, -1, -1, -1, 5971 -1, -1, -1, -1, 54, -1, -1, -1, 55, -1, -1, -1, 5972 58, 62, 56, 61, 57 5973 }; 5974 static const int port_speed_max_303[] = { 5975 -1, 5976 -1, -1, -1, -1, -1, -1, -1, -1, 3, 3, 3, 3, 5977 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 5978 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 5979 1, -1, -1, -1, 5980 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5981 -1, -1, -1, -1, 11, 11, 11, 11, -1, -1, -1, -1, 5982 -1, -1, -1, -1, 5983 -1, -1, -1, -1, 42, -1, -1, -1, 42, -1, -1, -1, 5984 -1, -1, -1, -1, -1 5985 }; 5986 /* TR3_1G_280: 28xGE + 1x40 + 4xHG[42] + 1GE */ 5987 static const int p2l_mapping_403[] = { 5988 0, 5989 -1, -1, -1, -1, -1, -1, -1, -1, 1, 2, 3, 4, 5990 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 5991 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 5992 29, -1, -1, -1, 5993 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 5994 -1, -1, -1, -1, 50, -1, -1, -1, -1, -1, -1, -1, 5995 -1, -1, -1, -1, 5996 -1, -1, -1, -1, 56, -1, -1, -1, 57, -1, -1, -1, 5997 61, 59, 58, 60, 62 5998 }; 5999 static const int p2m_mapping_403[] = { 6000 59, 6001 -1, -1, -1, -1, -1, -1, -1, -1, 0, 1, 2, 3, 6002 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 6003 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 6004 60, -1, -1, -1, 6005 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 6006 -1, -1, -1, -1, 48, -1, -1, -1, -1, -1, -1, -1, 6007 -1, -1, -1, -1, 6008 -1, -1, -1, -1, 54, -1, -1, -1, 55, -1, -1, -1, 6009 58, 62, 56, 61, 57 6010 }; 6011 static const int port_speed_max_403[] = { 6012 -1, 6013 -1, -1, -1, -1, -1, -1, -1, -1, 3, 3, 3, 3, 6014 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 6015 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 6016 1, -1, -1, -1, 6017 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 6018 -1, -1, -1, -1, 40, -1, -1, -1, -1, -1, -1, -1, 6019 -1, -1, -1, -1, 6020 -1, -1, -1, -1, 42, -1, -1, -1, 42, -1, -1, -1, 6021 -1, -1, -1, -1, -1 6022 }; 6023 6024 6025 soc_info_t *si; 6026 int rv = SOC_E_NONE; 6027 int phy_port; 6028 soc_pbmp_t pbmp_xport_xe; 6029 soc_pbmp_t pbmp_xport_ge; 6030 const int *p2l_mapping, *p2l_flex_mapping = NULL, *p2m_mapping, *speed_max; 6031 int flex_p2l_mapping[SOC_MAX_PHY_PORTS] = {-1}, 6032 flex_speed_max[SOC_MAX_PHY_PORTS] = {0}; 6033 6034 sal_memset(&_tr3_flex_port_inf[unit], 0, sizeof(_soc_tr3_flex_port_inf_t)); 6035 _soc_tr3_resolve_port_config(unit, dev_id); 6036 LOG_VERBOSE(BSL_LS_SOC_COMMON, 6037 (BSL_META_U(unit, 6038 "Port config id: %d\n"), _tr3_port_config_id[unit])); 6039 6040 switch (_tr3_port_config_id[unit]) { 6041 case 10: 6042 p2l_mapping = p2l_mapping_10; 6043 p2m_mapping = p2m_mapping_10; 6044 speed_max = port_speed_max_10; 6045 break; 6046 case 110: 6047 p2l_mapping = p2l_mapping_110; 6048 p2m_mapping = p2m_mapping_110; 6049 speed_max = port_speed_max_110; 6050 break; 6051 case 11: 6052 p2l_mapping = p2l_mapping_11; 6053 p2m_mapping = p2m_mapping_11; 6054 speed_max = port_speed_max_11; 6055 break; 6056 case 12: 6057 p2l_mapping = p2l_mapping_12; 6058 p2m_mapping = p2m_mapping_12; 6059 speed_max = port_speed_max_12; 6060 p2l_flex_mapping = flex_p2l_mapping_12; 6061 _tr3_flex_port_inf[unit] = flex_port_inf_112; 6062 break; 6063 case 112: 6064 p2l_mapping = p2l_mapping_112; 6065 p2m_mapping = p2m_mapping_112; 6066 speed_max = port_speed_max_112; 6067 p2l_flex_mapping = flex_p2l_mapping_112; 6068 _tr3_flex_port_inf[unit] = flex_port_inf_112; 6069 break; 6070 case 35: 6071 p2l_mapping = p2l_mapping_35; 6072 p2m_mapping = p2m_mapping_35; 6073 speed_max = port_speed_max_35; 6074 break; 6075 case 36: 6076 p2l_mapping = p2l_mapping_36; 6077 p2m_mapping = p2m_mapping_36; 6078 speed_max = port_speed_max_36; 6079 break; 6080 case 37: 6081 p2l_mapping = p2l_mapping_37; 6082 p2m_mapping = p2m_mapping_37; 6083 speed_max = port_speed_max_37; 6084 p2l_flex_mapping = flex_p2l_mapping_37; 6085 _tr3_flex_port_inf[unit] = flex_port_inf_37; 6086 break; 6087 case 38: 6088 p2l_mapping = p2l_mapping_38; 6089 p2m_mapping = p2m_mapping_38; 6090 speed_max = port_speed_max_38; 6091 p2l_flex_mapping = flex_p2l_mapping_38; 6092 _tr3_flex_port_inf[unit] = flex_port_inf_38; 6093 break; 6094 case 40: 6095 p2l_mapping = p2l_mapping_40; 6096 p2m_mapping = p2m_mapping_40; 6097 speed_max = port_speed_max_40; 6098 p2l_flex_mapping = flex_p2l_mapping_40; 6099 _tr3_flex_port_inf[unit] = flex_port_inf_40; 6100 break; 6101 case 41: 6102 p2l_mapping = p2l_mapping_41; 6103 p2m_mapping = p2m_mapping_41; 6104 speed_max = port_speed_max_41; 6105 break; 6106 case 50: 6107 p2l_mapping = p2l_mapping_50; 6108 p2m_mapping = p2m_mapping_50; 6109 speed_max = port_speed_max_50; 6110 break; 6111 case 55: 6112 p2l_mapping = p2l_mapping_55; 6113 p2m_mapping = p2m_mapping_55; 6114 speed_max = port_speed_max_55; 6115 p2l_flex_mapping = flex_p2l_mapping_55; 6116 _tr3_flex_port_inf[unit] = flex_port_inf_55; 6117 break; 6118 case 155: 6119 p2l_mapping = p2l_mapping_155; 6120 p2m_mapping = p2m_mapping_155; 6121 speed_max = port_speed_max_155; 6122 p2l_flex_mapping = flex_p2l_mapping_155; 6123 _tr3_flex_port_inf[unit] = flex_port_inf_155; 6124 break; 6125 case 71: 6126 p2l_mapping = p2l_mapping_71; 6127 p2m_mapping = p2m_mapping_71; 6128 speed_max = port_speed_max_71; 6129 p2l_flex_mapping = flex_p2l_mapping_71; 6130 _tr3_flex_port_inf[unit] = flex_port_inf_71; 6131 break; 6132 case 72: 6133 p2l_mapping = p2l_mapping_72; 6134 p2m_mapping = p2m_mapping_72; 6135 speed_max = port_speed_max_72; 6136 p2l_flex_mapping = flex_p2l_mapping_72; 6137 _tr3_flex_port_inf[unit] = flex_port_inf_72; 6138 break; 6139 case 171: 6140 p2l_mapping = p2l_mapping_171; 6141 p2m_mapping = p2m_mapping_171; 6142 speed_max = port_speed_max_171; 6143 p2l_flex_mapping = flex_p2l_mapping_171; 6144 _tr3_flex_port_inf[unit] = flex_port_inf_171; 6145 break; 6146 case 172: 6147 p2l_mapping = p2l_mapping_172; 6148 p2m_mapping = p2m_mapping_172; 6149 speed_max = port_speed_max_172; 6150 p2l_flex_mapping = flex_p2l_mapping_172; 6151 _tr3_flex_port_inf[unit] = flex_port_inf_172; 6152 break; 6153 case 81: 6154 p2l_mapping = p2l_mapping_81; 6155 p2m_mapping = p2m_mapping_81; 6156 speed_max = port_speed_max_81; 6157 break; 6158 case 82: 6159 p2l_mapping = p2l_mapping_82; 6160 p2m_mapping = p2m_mapping_82; 6161 speed_max = port_speed_max_82; 6162 p2l_flex_mapping = flex_p2l_mapping_82; 6163 _tr3_flex_port_inf[unit] = flex_port_inf_37; 6164 break; 6165 case 83: 6166 p2l_mapping = p2l_mapping_83; 6167 p2m_mapping = p2m_mapping_83; 6168 speed_max = port_speed_max_83; 6169 p2l_flex_mapping = flex_p2l_mapping_83; 6170 _tr3_flex_port_inf[unit] = flex_port_inf_37; 6171 break; 6172 case 90: 6173 p2l_mapping = p2l_mapping_90; 6174 p2m_mapping = p2m_mapping_90; 6175 speed_max = port_speed_max_90; 6176 break; 6177 case 190: 6178 p2l_mapping = p2l_mapping_190; 6179 p2m_mapping = p2m_mapping_190; 6180 speed_max = port_speed_max_190; 6181 break; 6182 case 91: 6183 p2l_mapping = p2l_mapping_91; 6184 p2m_mapping = p2m_mapping_91; 6185 speed_max = port_speed_max_91; 6186 p2l_flex_mapping = flex_p2l_mapping_91; 6187 _tr3_flex_port_inf[unit] = flex_port_inf_91; 6188 break; 6189 case 94: 6190 p2l_mapping = p2l_mapping_94; 6191 p2m_mapping = p2m_mapping_94; 6192 speed_max = port_speed_max_94; 6193 break; 6194 case 95: 6195 p2l_mapping = p2l_mapping_95; 6196 p2m_mapping = p2m_mapping_95; 6197 speed_max = port_speed_max_95; 6198 break; 6199 case 195: 6200 p2l_mapping = p2l_mapping_195; 6201 p2m_mapping = p2m_mapping_195; 6202 speed_max = port_speed_max_195; 6203 break; 6204 case 295: 6205 p2l_mapping = p2l_mapping_295; 6206 p2m_mapping = p2m_mapping_295; 6207 speed_max = port_speed_max_295; 6208 break; 6209 case 395: 6210 p2l_mapping = p2l_mapping_395; 6211 p2m_mapping = p2m_mapping_395; 6212 speed_max = port_speed_max_395; 6213 break; 6214 case 495: 6215 p2l_mapping = p2l_mapping_495; 6216 p2m_mapping = p2m_mapping_495; 6217 speed_max = port_speed_max_495; 6218 break; 6219 case 595: 6220 p2l_mapping = p2l_mapping_95; 6221 p2m_mapping = p2m_mapping_95; 6222 speed_max = port_speed_max_595; 6223 break; 6224 case 695: 6225 p2l_mapping = p2l_mapping_395; 6226 p2m_mapping = p2m_mapping_395; 6227 speed_max = port_speed_max_695; 6228 break; 6229 case 96: 6230 p2l_mapping = p2l_mapping_96; 6231 p2m_mapping = p2m_mapping_96; 6232 speed_max = port_speed_max_96; 6233 break; 6234 case 196: 6235 p2l_mapping = p2l_mapping_196; 6236 p2m_mapping = p2m_mapping_196; 6237 speed_max = port_speed_max_196; 6238 break; 6239 case 97: 6240 p2l_mapping = p2l_mapping_97; 6241 p2m_mapping = p2m_mapping_97; 6242 speed_max = port_speed_max_97; 6243 p2l_flex_mapping = flex_p2l_mapping_97; 6244 _tr3_flex_port_inf[unit] = flex_port_inf_91; 6245 break; 6246 case 98: 6247 p2l_mapping = p2l_mapping_98; 6248 p2m_mapping = p2m_mapping_98; 6249 speed_max = port_speed_max_98; 6250 p2l_flex_mapping = flex_p2l_mapping_98; 6251 _tr3_flex_port_inf[unit] = flex_port_inf_91; 6252 break; 6253 case 99: 6254 p2l_mapping = p2l_mapping_99; 6255 p2m_mapping = p2m_mapping_99; 6256 speed_max = port_speed_max_99; 6257 break; 6258 case 100: 6259 p2l_mapping = p2l_mapping_100; 6260 p2m_mapping = p2m_mapping_100; 6261 speed_max = port_speed_max_100; 6262 p2l_flex_mapping = flex_p2l_mapping_100; 6263 _tr3_flex_port_inf[unit] = flex_port_inf_100; 6264 break; 6265 case 101: 6266 p2l_mapping = p2l_mapping_101; 6267 p2m_mapping = p2m_mapping_101; 6268 speed_max = port_speed_max_101; 6269 p2l_flex_mapping = flex_p2l_mapping_101; 6270 _tr3_flex_port_inf[unit] = flex_port_inf_100; 6271 break; 6272 case 102: 6273 p2l_mapping = p2l_mapping_102; 6274 p2m_mapping = p2m_mapping_102; 6275 speed_max = port_speed_max_100; 6276 p2l_flex_mapping = flex_p2l_mapping_102; 6277 _tr3_flex_port_inf[unit] = flex_port_inf_102; 6278 break; 6279 case 103: 6280 p2l_mapping = p2l_mapping_103; 6281 p2m_mapping = p2m_mapping_103; 6282 speed_max = port_speed_max_103; 6283 break; 6284 case 203: 6285 p2l_mapping = p2l_mapping_203; 6286 p2m_mapping = p2m_mapping_203; 6287 speed_max = port_speed_max_203; 6288 break; 6289 case 303: 6290 p2l_mapping = p2l_mapping_303; 6291 p2m_mapping = p2m_mapping_303; 6292 speed_max = port_speed_max_303; 6293 break; 6294 case 403: 6295 p2l_mapping = p2l_mapping_403; 6296 p2m_mapping = p2m_mapping_403; 6297 speed_max = port_speed_max_403; 6298 break; 6299 default: 6300 return SOC_E_PARAM; 6301 } 6302 6303 /* Handle any init time flex port configs */ 6304 if (_tr3_flex_port_inf[unit].valid) { 6305 uint8 idx, i, j, port_groups = 0; 6306 char *config_str, *sub_str, *sub_str_end; 6307 int num_lanes, port_bw; 6308 6309 if (p2l_flex_mapping) { 6310 sal_memcpy(flex_p2l_mapping, p2l_flex_mapping, 6311 sizeof(int) * SOC_MAX_PHY_PORTS); 6312 } 6313 sal_memcpy(flex_speed_max, speed_max, sizeof(int) * SOC_MAX_PHY_PORTS); 6314 for (i = 0; ; i++) { 6315 if (_tr3_flex_port_inf[unit].flex_port_groups[i] == -1) { 6316 break; 6317 } 6318 } 6319 port_groups = i; 6320 LOG_VERBOSE(BSL_LS_SOC_COMMON, 6321 (BSL_META_U(unit, 6322 "Flex port groups: %d\n"), port_groups)); 6323 _tr3_flex_port_data[unit].port_groups = port_groups; 6324 for (i = 0; i < port_groups; i++) { 6325 config_str = soc_property_port_get_str(unit, i, spn_PORTGROUP); 6326 if (config_str == NULL) { 6327 continue; 6328 } 6329 LOG_VERBOSE(BSL_LS_SOC_COMMON, 6330 (BSL_META_U(unit, 6331 "Flex group cfg: %d=%s\n"), i, config_str)); 6332 /* 6333 * portgroup_<port group>=<num of lanes> 6334 */ 6335 sub_str = config_str; 6336 num_lanes = sal_ctoi(sub_str, &sub_str_end); 6337 if (sub_str == sub_str_end) { 6338 LOG_ERROR(BSL_LS_SOC_COMMON, 6339 (BSL_META_U(unit, 6340 "Port group %d: Missing number of lanes information \"%s\"\n"), 6341 i, config_str)); 6342 rv = SOC_E_FAIL; 6343 continue; 6344 } 6345 if (num_lanes == 0) { 6346 LOG_ERROR(BSL_LS_SOC_COMMON, 6347 (BSL_META_U(unit, 6348 "Port group %d: Missing number of lanes information \"%s\"\n"), 6349 i, config_str)); 6350 rv = SOC_E_FAIL; 6351 continue; 6352 } 6353 SOC_PBMP_CLEAR(pbmp_xport_xe); 6354 SOC_PBMP_CLEAR(pbmp_xport_ge); 6355 idx = _tr3_flex_port_inf[unit].flex_port_groups[i]*4 + 1; 6356 switch (num_lanes) { 6357 case 1: 6358 _tr3_flex_port_data[unit].ports[i] = 4; 6359 /* Determine bandwidth */ 6360 port_bw = _tr3_flex_port_inf[unit].def_flex_port_speeds[i][2]; 6361 /* Check for properties */ 6362 pbmp_xport_ge = soc_property_get_pbmp_default(unit, spn_PBMP_XPORT_GE, 6363 pbmp_xport_ge); 6364 /* Force 10 -> 1 */ 6365 if (SOC_PBMP_MEMBER(pbmp_xport_ge, p2l_mapping[idx])) { 6366 if (port_bw >= 10) { 6367 for (j = 0; _tr3_flex_port_inf[unit].flex_port_speeds[i][j] != -1;j++) { 6368 if (_tr3_flex_port_inf[unit].flex_port_speeds[i][j] == 1 && 6369 _tr3_flex_port_inf[unit].flex_port_lanes[i][j] == num_lanes) { 6370 port_bw = 1; 6371 break; 6372 } 6373 } 6374 } 6375 } 6376 LOG_VERBOSE(BSL_LS_SOC_COMMON, 6377 (BSL_META_U(unit, 6378 "Flex group: %d, lanes: %d, ports: %d, speed: %d gbps\n"), i, 6379 num_lanes, _tr3_flex_port_data[unit].ports[i], port_bw)); 6380 if (!SOC_IS_HELIX4(unit) && (_tr3_port_config_id[unit] == 112 || 6381 _tr3_port_config_id[unit] == 12)) { 6382 flex_p2l_mapping[idx+1] = p2l_mapping[idx+1]; 6383 flex_p2l_mapping[idx+2] = p2l_mapping[idx+2]; 6384 flex_p2l_mapping[idx+3] = p2l_mapping[idx+3]; 6385 flex_speed_max[idx] = port_bw; 6386 flex_speed_max[idx+1] = (flex_p2l_mapping[idx+1]>0) ? port_bw : -1; 6387 flex_speed_max[idx+2] = (flex_p2l_mapping[idx+2]>0) ? port_bw : -1; 6388 flex_speed_max[idx+3] = (flex_p2l_mapping[idx+3]>0) ? port_bw : -1; 6389 } else { 6390 flex_p2l_mapping[idx+1] = flex_p2l_mapping[idx]+1; 6391 flex_p2l_mapping[idx+2] = flex_p2l_mapping[idx]+2; 6392 flex_p2l_mapping[idx+3] = flex_p2l_mapping[idx]+3; 6393 flex_speed_max[idx] = port_bw; 6394 flex_speed_max[idx+1] = port_bw; 6395 flex_speed_max[idx+2] = port_bw; 6396 flex_speed_max[idx+3] = port_bw; 6397 } 6398 break; 6399 case 2: 6400 if (!SOC_IS_HELIX4(unit) && ((_tr3_port_config_id[unit] == 112 || 6401 _tr3_port_config_id[unit] == 12) && 6402 (idx == 73 || idx == 77))) { 6403 return SOC_E_PARAM; 6404 } 6405 _tr3_flex_port_data[unit].ports[i] = 2; 6406 /* Determine bandwidth */ 6407 port_bw = _tr3_flex_port_inf[unit].def_flex_port_speeds[i][1]; 6408 /* Check for properties */ 6409 pbmp_xport_xe = soc_property_get_pbmp_default(unit, spn_PBMP_XPORT_XE, 6410 pbmp_xport_xe); 6411 /* Force 21 -> 10 */ 6412 if (SOC_PBMP_MEMBER(pbmp_xport_xe, flex_p2l_mapping[idx])) { 6413 if (port_bw == 21) { 6414 for (j = 0; _tr3_flex_port_inf[unit].flex_port_speeds[i][j] != -1;j++) { 6415 if (_tr3_flex_port_inf[unit].flex_port_speeds[i][j] == 10 && 6416 _tr3_flex_port_inf[unit].flex_port_lanes[i][j] == num_lanes) { 6417 port_bw = 10; 6418 break; 6419 } 6420 } 6421 } 6422 } 6423 LOG_VERBOSE(BSL_LS_SOC_COMMON, 6424 (BSL_META_U(unit, 6425 "Flex group: %d, lanes: %d, ports: %d, speed: %d gbps\n"), i, 6426 num_lanes, _tr3_flex_port_data[unit].ports[i], port_bw)); 6427 flex_p2l_mapping[idx+1] = -1; 6428 flex_p2l_mapping[idx+2] = flex_p2l_mapping[idx]+2; 6429 flex_p2l_mapping[idx+3] = -1; 6430 flex_speed_max[idx] = port_bw; 6431 flex_speed_max[idx+1] = -1; 6432 flex_speed_max[idx+2] = port_bw; 6433 flex_speed_max[idx+3] = -1; 6434 break; 6435 case 4: 6436 _tr3_flex_port_data[unit].ports[i] = 1; 6437 /* Determine bandwidth */ 6438 port_bw = _tr3_flex_port_inf[unit].def_flex_port_speeds[i][0]; 6439 /* Check for properties */ 6440 pbmp_xport_xe = soc_property_get_pbmp_default(unit, spn_PBMP_XPORT_XE, 6441 pbmp_xport_xe); 6442 /* Force 21 -> 10 */ 6443 if (SOC_PBMP_MEMBER(pbmp_xport_xe, flex_p2l_mapping[idx])) { 6444 if (port_bw == 21) { 6445 for (j = 0; _tr3_flex_port_inf[unit].flex_port_speeds[i][j] != -1;j++) { 6446 if (_tr3_flex_port_inf[unit].flex_port_speeds[i][j] == 10 && 6447 _tr3_flex_port_inf[unit].flex_port_lanes[i][j] == num_lanes) { 6448 port_bw = 10; 6449 break; 6450 } 6451 } 6452 } 6453 } 6454 LOG_VERBOSE(BSL_LS_SOC_COMMON, 6455 (BSL_META_U(unit, 6456 "Flex group: %d, lanes: %d, ports: %d, speed: %d gbps\n"), i, 6457 num_lanes, _tr3_flex_port_data[unit].ports[i], port_bw)); 6458 flex_p2l_mapping[idx+1] = -1; 6459 flex_p2l_mapping[idx+2] = -1; 6460 flex_p2l_mapping[idx+3] = -1; 6461 flex_speed_max[idx] = port_bw; 6462 flex_speed_max[idx+1] = -1; 6463 flex_speed_max[idx+2] = -1; 6464 flex_speed_max[idx+3] = -1; 6465 break; 6466 default: break; 6467 } 6468 } 6469 } 6470 6471 si = &SOC_INFO(unit); 6472 if ((_tr3_port_config_id[unit] >= 10 && _tr3_port_config_id[unit] <= 14) || 6473 (_tr3_port_config_id[unit] >= 20 && _tr3_port_config_id[unit] <= 23) || 6474 (_tr3_port_config_id[unit] >= 40 && _tr3_port_config_id[unit] <= 41) || 6475 (_tr3_port_config_id[unit] >= 60 && _tr3_port_config_id[unit] <= 61)) { 6476 si->bandwidth = 200000; 6477 } else if ((_tr3_port_config_id[unit] >= 30 && _tr3_port_config_id[unit] <= 35) || 6478 (_tr3_port_config_id[unit] == 50) || (_tr3_port_config_id[unit] == 62)) { 6479 si->bandwidth = 260000; 6480 } 6481 for (phy_port = 0; phy_port < SOC_MAX_PHY_PORTS; phy_port++) { 6482 /* coverity[dead_error_condition] */ 6483 if (phy_port >= SOC_MAX_NUM_PORTS) { 6484 /* coverity[dead_error_line] */ 6485 break; 6486 } 6487 si->port_p2l_mapping[phy_port] = p2l_mapping[phy_port]; 6488 si->flex_port_p2l_mapping[phy_port] = _tr3_flex_port_inf[unit].valid ? flex_p2l_mapping[phy_port] : 6489 p2l_mapping[phy_port]; /* for disabling unavailable ports */ 6490 si->port_p2m_mapping[phy_port] = p2m_mapping[phy_port]; 6491 _soc_tr3_port_speed_max[phy_port] = 0; 6492 if (_tr3_flex_port_inf[unit].valid) { 6493 if (flex_speed_max[phy_port] != -1) { 6494 si->port_speed_max[si->port_p2l_mapping[phy_port]] = 6495 flex_speed_max[phy_port] * 1000; 6496 _soc_tr3_port_speed_max[phy_port] = flex_speed_max[phy_port] * 1000; 6497 } 6498 } else { 6499 if (speed_max[phy_port] != -1) { 6500 si->port_speed_max[si->port_p2l_mapping[phy_port]] = 6501 speed_max[phy_port] * 1000; 6502 _soc_tr3_port_speed_max[phy_port] = speed_max[phy_port] * 1000; 6503 } 6504 } 6505 } 6506 return rv; 6507 } 6508 int 6509 soc_tr3_flex_port_grp(int unit, soc_port_t port,int8 *fgrp) 6510 { 6511 uint8 i, port_groups = 0; 6512 uint16 idx; 6513 int p; 6514 soc_info_t *si = &SOC_INFO(unit); 6515 *fgrp = -1; 6516 6517 if (!_tr3_flex_port_inf[unit].valid) { 6518 return FALSE; 6519 } 6520 if (IS_CL_PORT(unit, port) && (IS_CE_PORT(unit, port) || 6521 si->port_speed_max[port] >= 100000)) { 6522 return FALSE; 6523 } 6524 for (i = 0; ; i++) { 6525 if (_tr3_flex_port_inf[unit].flex_port_groups[i] == -1) { 6526 break; 6527 } 6528 } 6529 port_groups = i; 6530 for (i = 0; i < port_groups; i++) { 6531 idx = _tr3_flex_port_inf[unit].flex_port_groups[i]*4 + 1; 6532 p = si->port_p2l_mapping[idx]; 6533 /* Only the first port in a group is the controlling/deciding port */ 6534 if (port == p) { 6535 *fgrp = (int8)i; 6536 return TRUE; 6537 } 6538 } 6539 return FALSE; 6540 } 6541 6542 int 6543 soc_tr3_port_is_flex_port(int unit, soc_port_t port) 6544 { 6545 uint8 i, port_groups = 0; 6546 uint16 idx; 6547 int p; 6548 soc_info_t *si = &SOC_INFO(unit); 6549 6550 if (!_tr3_flex_port_inf[unit].valid) { 6551 return FALSE; 6552 } 6553 if (IS_CL_PORT(unit, port) && (IS_CE_PORT(unit, port) || 6554 si->port_speed_max[port] >= 100000)) { 6555 return FALSE; 6556 } 6557 for (i = 0; ; i++) { 6558 if (_tr3_flex_port_inf[unit].flex_port_groups[i] == -1) { 6559 break; 6560 } 6561 } 6562 port_groups = i; 6563 LOG_VERBOSE(BSL_LS_SOC_COMMON, 6564 (BSL_META_U(unit, 6565 "Flex port groups: %d\n"), port_groups)); 6566 for (i = 0; i < port_groups; i++) { 6567 idx = _tr3_flex_port_inf[unit].flex_port_groups[i]*4 + 1; 6568 p = si->port_p2l_mapping[idx]; 6569 /* Only the first port in a group is the controlling/deciding port */ 6570 if (port == p) { 6571 return TRUE; 6572 } 6573 } 6574 return FALSE; 6575 } 6576 6577 soc_pbmp_t 6578 soc_tr3_get_control_port_bitmap(int unit) 6579 { 6580 soc_port_t port; 6581 int phy_port, phy_port_base; 6582 soc_pbmp_t ctr_pbmp; 6583 soc_info_t *si = &SOC_INFO(unit); 6584 6585 SOC_PBMP_CLEAR(ctr_pbmp); 6586 6587 PBMP_PORT_ITER(unit, port){ 6588 if (SOC_PBMP_MEMBER(SOC_PORT_DISABLED_BITMAP(unit,all), port)) { 6589 continue; 6590 } 6591 if(IS_CL_PORT(unit, port) || IS_XT_PORT(unit,port) || IS_XW_PORT(unit,port)) { 6592 phy_port = si->port_l2p_mapping[port]; 6593 phy_port_base = ((phy_port - 1) & ~0x3) + 1; 6594 6595 if (phy_port == phy_port_base) { 6596 SOC_PBMP_PORT_ADD(ctr_pbmp, port); 6597 } 6598 } 6599 } 6600 6601 return ctr_pbmp; 6602 } 6603 6604 /* Map of block to first physical port in the block */ 6605 int _soc_tr3_b2pp[SOC_MAX_NUM_BLKS]; 6606 6607 /* 6608 * TR3 port mapping 6609 */ 6610 int 6611 soc_tr3_port_config_init(int unit, uint16 dev_id) 6612 { 6613 int b, p; 6614 for (b=0; SOC_BLOCK_TYPE(unit, b) != -1; b++) { 6615 _soc_tr3_b2pp[b] = -1; 6616 for (p=0; SOC_PORT_BLOCK(unit, p)!= -1; p++) { 6617 if (b == SOC_PORT_BLOCK(unit, p)) { 6618 _soc_tr3_b2pp[b] = p; 6619 break; 6620 } 6621 } 6622 } 6623 SOC_INFO(unit).blk_fpp = _soc_tr3_b2pp; 6624 #ifdef BCM_HELIX4_SUPPORT 6625 if (SOC_IS_HELIX4(unit)) { 6626 return soc_hx4_get_port_mapping(unit, dev_id); 6627 } else 6628 #endif /* BCM_HELIX4_SUPPORT */ 6629 { 6630 return soc_triumph3_get_port_mapping(unit, dev_id); 6631 } 6632 } 6633 6634 /* 6635 * This function is used to set the MDIO frequency. 6636 * If freq == 0Mhz, it means to restore the frequency by 6637 * default configuration. 6638 */ 6639 int 6640 soc_tr3_set_mdio_freq(int unit, uint32 freq) 6641 { 6642 uint32 reg_val; 6643 static uint32 divisor, dividend; 6644 int is_set = (freq > 0) ? 1 : 0; 6645 6646 if (is_set) { 6647 if (soc_tr3_core_clock_speed(unit) == SOC_TR3_CORE_CLOCK_UNKNOWN) { 6648 return SOC_E_PARAM; 6649 } 6650 divisor = (soc_tr3_core_clock_speed(unit) + 2 * freq - 1) / (2 * freq); 6651 dividend = 1; 6652 } else { 6653 /* restore the frequency*/ 6654 divisor = soc_property_get(unit, spn_RATE_EXT_MDIO_DIVISOR, 24); 6655 dividend = soc_property_get(unit, spn_RATE_EXT_MDIO_DIVIDEND, 1); 6656 } 6657 6658 reg_val = 0; 6659 soc_reg_field_set(unit, CMIC_RATE_ADJUSTr, ®_val, DIVISORf, divisor); 6660 soc_reg_field_set(unit, CMIC_RATE_ADJUSTr, ®_val, DIVIDENDf, dividend); 6661 /* coverity[result_independent_of_operands] */ 6662 SOC_IF_ERROR_RETURN(WRITE_CMIC_RATE_ADJUSTr(unit, reg_val)); 6663 return SOC_E_NONE; 6664 } 6665 6666 int 6667 soc_tr3_lls_bmap_alloc(int unit) 6668 { 6669 soc_control_t *soc; 6670 soc_info_t *si; 6671 int port, index, hw_index; 6672 int alloc_size_l0, alloc_size_l1, alloc_size_l2; 6673 6674 soc = SOC_CONTROL(unit); 6675 si = &SOC_INFO(unit); 6676 6677 alloc_size_l0 = 6678 SHR_BITALLOCSIZE(soc_mem_index_count(unit, LLS_L0_PARENTm)); 6679 alloc_size_l1 = 6680 SHR_BITALLOCSIZE(soc_mem_index_count(unit, LLS_L1_PARENTm)); 6681 alloc_size_l2 = 6682 SHR_BITALLOCSIZE(soc_mem_index_count(unit, LLS_L2_PARENTm)); 6683 6684 PBMP_ALL_ITER(unit, port) { 6685 soc->port_lls_l0_bmap[port] = sal_alloc(alloc_size_l0, "LLS_L0_BMAP"); 6686 soc->port_lls_l1_bmap[port] = sal_alloc(alloc_size_l1, "LLS_L1_BMAP"); 6687 soc->port_lls_l2_bmap[port] = sal_alloc(alloc_size_l2, "LLS_L2_BMAP"); 6688 sal_memset(soc->port_lls_l0_bmap[port], 0, alloc_size_l0); 6689 sal_memset(soc->port_lls_l1_bmap[port], 0, alloc_size_l1); 6690 sal_memset(soc->port_lls_l2_bmap[port], 0, alloc_size_l2); 6691 if (IS_CE_PORT(unit,port) || 6692 (IS_HG_PORT(unit,port) && (si->port_speed_max[port] >= 100000))) { /* HSP port */ 6693 for (index = 0; index < 10; index++) { 6694 if(!soc_tr3_sched_hw_index_get(unit, port, SOC_TR3_NODE_LVL_L0, 6695 index, &hw_index)) { 6696 SHR_BITSET(SOC_CONTROL(unit)->port_lls_l0_bmap[port], hw_index); 6697 } 6698 SHR_BITSET(SOC_CONTROL(unit)->port_lls_l1_bmap[port], 6699 si->port_uc_cosq_base[port] + index); 6700 } 6701 } 6702 } 6703 6704 return SOC_E_NONE; 6705 } 6706 6707 /* 6708 * Function: 6709 * soc_triumph3_chip_reset 6710 * Purpose: 6711 * Special reset sequencing for BCM56640 6712 * Setup SBUS block mapping. 6713 */ 6714 int 6715 soc_triumph3_chip_reset(int unit) 6716 { 6717 uint32 rval, to_usec; 6718 soc_reg_t reg; 6719 int index, rv; 6720 uint16 dev_id_local; 6721 uint8 rev_id_local; 6722 soc_persist_t *sop = SOC_PERSIST(unit); 6723 soc_info_t *si = &SOC_INFO(unit); 6724 int defip_config = 0; 6725 int num_ipv6_128b_entries = 0; 6726 int config_v6_entries = 0; 6727 6728 static const soc_reg_t pll_ctrl0_reg[] = { 6729 TOP_XG_PLL0_CTRL_0r, TOP_XG_PLL1_CTRL_0r, 6730 TOP_XG_PLL2_CTRL_0r, TOP_XG_PLL3_CTRL_0r 6731 }; 6732 static const soc_reg_t pll_ctrl1_reg[] = { 6733 TOP_XG_PLL0_CTRL_1r, TOP_XG_PLL1_CTRL_1r, 6734 TOP_XG_PLL2_CTRL_1r, TOP_XG_PLL3_CTRL_1r 6735 }; 6736 static const soc_reg_t pll_ctrl3_reg[] = { 6737 TOP_XG_PLL0_CTRL_3r, TOP_XG_PLL1_CTRL_3r, 6738 TOP_XG_PLL2_CTRL_3r, TOP_XG_PLL3_CTRL_3r 6739 }; 6740 static const soc_reg_t pll_ctrl4_reg[] = { 6741 TOP_XG_PLL0_CTRL_4r, TOP_XG_PLL1_CTRL_4r, 6742 TOP_XG_PLL2_CTRL_4r, TOP_XG_PLL3_CTRL_4r 6743 }; 6744 6745 /* TS_PLL settings - reference SDK-59644 */ 6746 unsigned ts_ref_freq = 0; 6747 unsigned ts_idx=0; 6748 static const soc_pll_param_t triumph3_ts_pll[] = { 6749 /* Fref, Ndiv_int, Ndiv_frac, Pdiv, Mdiv, Ka, Ki, Kp, VCO_div2 */ 6750 {25000000, 100, 0, 1, 10, 2, 2, 6, 1}, 6751 {20000000, 125, 0, 1, 10, 2, 2, 6, 1}, 6752 /* 25MHz internal reference */ 6753 { 0, 100, 0, 1, 10, 2, 2, 6, 1} 6754 }; 6755 6756 /* BS PLL settings - reference SDK-59644 */ 6757 unsigned bs_ref_freq = 0; 6758 unsigned bs_idx=0; 6759 static const soc_pll_param_t triumph3_bs_pll[] = { 6760 /* Fref, Ndiv_int, Ndiv_frac, Pdiv, Mdiv, Ka, Ki, Kp, VCO_div2 */ 6761 {25000000, 320, 0, 2, 200, 2, 4, 9, 0}, 6762 {20000000, 400, 0, 2, 200, 2, 3, 8, 0}, 6763 /* 25MHz internal reference */ 6764 { 0, 320, 0, 2, 200, 2, 4, 9, 0} 6765 }; 6766 6767 6768 to_usec = SAL_BOOT_QUICKTURN ? (250 * MILLISECOND_USEC) : 6769 (10 * MILLISECOND_USEC); 6770 6771 /* 6772 * SBUS ring and block number: 6773 * ring 0: IP(1) 6774 * ring 1: EP(2) 6775 * ring 2: MMU(3) 6776 * ring 3: ISM(16) 6777 * ring 4: ETU(17) 6778 * ring 5: AXP(4) 6779 * ring 6: XTP0(8)..XTP2(10), XLP0(11), XTP3(12), IBOD(18), 6780 CLP0(13), XLP1(14), CLP1(15) 6781 * ring 7: OTPC(5), TOP_REGS(6) 6782 */ 6783 WRITE_CMIC_SBUS_RING_MAP_0_7r(unit, 0x07752100); /* block 7 - 0 */ 6784 WRITE_CMIC_SBUS_RING_MAP_8_15r(unit, 0x66666666); /* block 15 - 8 */ 6785 WRITE_CMIC_SBUS_RING_MAP_16_23r(unit, 0x00000643); /* block 23 - 16 */ 6786 WRITE_CMIC_SBUS_RING_MAP_24_31r(unit, 0x00000000); /* block 31 - 24 */ 6787 6788 /* Halt all uC cores */ 6789 READ_UC_0_RST_CONTROLr(unit, &rval); 6790 soc_reg_field_set(unit, UC_0_RST_CONTROLr, &rval, 6791 BYPASS_RSTFSM_CTRLf, 1); 6792 soc_reg_field_set(unit, UC_0_RST_CONTROLr, &rval, 6793 CPUHALT_Nf, 0); 6794 WRITE_UC_0_RST_CONTROLr(unit, rval); 6795 6796 READ_UC_1_RST_CONTROLr(unit, &rval); 6797 soc_reg_field_set(unit, UC_1_RST_CONTROLr, &rval, 6798 CPUHALT_Nf, 0); 6799 WRITE_UC_1_RST_CONTROLr(unit, rval); 6800 6801 6802 /* Note that only PLL0 & PLL1 are used by TR3 */ 6803 /* Set the OOBFC clock speed to 125MHz */ 6804 for (index = 0; index < 4; index++) { 6805 rv = soc_reg_field32_modify(unit, pll_ctrl0_reg[index], 6806 REG_PORT_ANY, CH3_MDIVf, 25); 6807 if (rv < 0) { 6808 LOG_ERROR(BSL_LS_SOC_COMMON, 6809 (BSL_META_U(unit, 6810 "Modifying TOP_PLL%d_CTRL_0 failed !!\n"), 6811 index)); 6812 return rv; 6813 } 6814 } 6815 6816 /* Use 156.25Mhz reference clock for LCPLL */ 6817 if (soc_property_get(unit, spn_XGXS_LCPLL_XTAL_REFCLK, 0)) { 6818 for (index = 0; index < 4; index++) { 6819 reg = pll_ctrl0_reg[index]; 6820 rv = soc_reg32_get(unit, reg, REG_PORT_ANY, 0, &rval); 6821 if (rv < 0) { 6822 LOG_ERROR(BSL_LS_SOC_COMMON, 6823 (BSL_META_U(unit, 6824 "Reading TOP_PLL%d_CTRL_0 failed !!\n"), 6825 index)); 6826 return rv; 6827 } 6828 soc_reg_field_set(unit, reg, &rval, CH0_MDIVf, 20); 6829 soc_reg_field_set(unit, reg, &rval, CH4_MDIVf, 125); 6830 soc_reg_field_set(unit, reg, &rval, CH5_MDIVf, 25); 6831 rv = soc_reg32_set(unit, reg, REG_PORT_ANY, 0, rval); 6832 if (rv < 0) { 6833 LOG_ERROR(BSL_LS_SOC_COMMON, 6834 (BSL_META_U(unit, 6835 "Writing TOP_PLL%d_CTRL_0 failed !!\n"), 6836 index)); 6837 return rv; 6838 } 6839 6840 rv = soc_reg_field32_modify(unit, pll_ctrl4_reg[index], 6841 REG_PORT_ANY, NDIV_INTf, 40); 6842 if (rv < 0) { 6843 LOG_ERROR(BSL_LS_SOC_COMMON, 6844 (BSL_META_U(unit, 6845 "Modifying TOP_PLL%d_CTRL_4 failed !!\n"), 6846 index)); 6847 return rv; 6848 } 6849 6850 rv = soc_reg_field32_modify(unit, pll_ctrl1_reg[index], 6851 REG_PORT_ANY, PDIVf, 2); 6852 if (rv < 0) { 6853 LOG_ERROR(BSL_LS_SOC_COMMON, 6854 (BSL_META_U(unit, 6855 "Modifying TOP_PLL%d_CTRL_1 failed !!\n"), 6856 index)); 6857 return rv; 6858 } 6859 6860 rv = soc_reg_field32_modify(unit, pll_ctrl3_reg[index], 6861 REG_PORT_ANY, CML_BYP_ENf, 1); 6862 if (rv < 0) { 6863 LOG_ERROR(BSL_LS_SOC_COMMON, 6864 (BSL_META_U(unit, 6865 "Modifying TOP_PLL%d_CTRL_3 failed !!\n"), 6866 index)); 6867 return rv; 6868 } 6869 } 6870 } 6871 6872 rv = READ_TOP_MISC_CONTROLr(unit, &rval); 6873 if (rv < 0) { 6874 LOG_ERROR(BSL_LS_SOC_COMMON, 6875 (BSL_META_U(unit, 6876 "Reading TOP_MISC_CONTROL failed !!\n"))); 6877 return rv; 6878 } 6879 soc_reg_field_set(unit, TOP_MISC_CONTROLr, &rval, 6880 CMIC_TO_XG_PLL0_SW_OVWRf, 1); 6881 soc_reg_field_set(unit, TOP_MISC_CONTROLr, &rval, 6882 CMIC_TO_XG_PLL1_SW_OVWRf, 1); 6883 soc_reg_field_set(unit, TOP_MISC_CONTROLr, &rval, 6884 CMIC_TO_XG_PLL2_SW_OVWRf, 1); 6885 soc_reg_field_set(unit, TOP_MISC_CONTROLr, &rval, 6886 CMIC_TO_XG_PLL3_SW_OVWRf, 1); 6887 rv = WRITE_TOP_MISC_CONTROLr(unit, rval); 6888 if (rv < 0) { 6889 LOG_ERROR(BSL_LS_SOC_COMMON, 6890 (BSL_META_U(unit, 6891 "Writing TOP_MISC_CONTROL failed !!\n"))); 6892 return rv; 6893 } 6894 6895 /* Bring LCPLL out of reset */ 6896 rv = READ_TOP_SOFT_RESET_REG_2r(unit, &rval); 6897 if (rv < 0) { 6898 LOG_ERROR(BSL_LS_SOC_COMMON, 6899 (BSL_META_U(unit, 6900 "Reading TOP_SOFT_RESET_REG_2 failed !!\n"))); 6901 return rv; 6902 } 6903 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, TOP_XG_PLL0_RST_Lf, 1); 6904 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, TOP_XG_PLL1_RST_Lf, 1); 6905 rv = WRITE_TOP_SOFT_RESET_REG_2r(unit, rval); 6906 if (rv < 0) { 6907 LOG_ERROR(BSL_LS_SOC_COMMON, 6908 (BSL_META_U(unit, 6909 "Writing TOP_SOFT_RESET_REG_2 failed !!\n"))); 6910 return rv; 6911 } 6912 sal_usleep(to_usec); 6913 6914 /* Wait for LCPLL lock */ 6915 if (!SAL_BOOT_SIMULATION) { 6916 rv = READ_TOP_XG_PLL0_STATUSr(unit, &rval); 6917 if (rv < 0) { 6918 LOG_ERROR(BSL_LS_SOC_COMMON, 6919 (BSL_META_U(unit, 6920 "Reading TOP_XG_PLL0_STATUS failed !!\n"))); 6921 return rv; 6922 } 6923 if (!soc_reg_field_get(unit, TOP_XG_PLL0_STATUSr, rval, TOP_XGPLL_LOCKf)) { 6924 LOG_ERROR(BSL_LS_SOC_COMMON, 6925 (BSL_META_U(unit, 6926 "LCPLL 0 not locked on unit %d " 6927 "status = 0x%08x\n"), unit, rval)); 6928 } 6929 rv = READ_TOP_XG_PLL1_STATUSr(unit, &rval); 6930 if (rv < 0) { 6931 LOG_ERROR(BSL_LS_SOC_COMMON, 6932 (BSL_META_U(unit, 6933 "Reading TOP_XG_PLL1_STATUS failed !!\n"))); 6934 return rv; 6935 } 6936 if (!soc_reg_field_get(unit, TOP_XG_PLL1_STATUSr, rval, TOP_XGPLL_LOCKf)) { 6937 LOG_ERROR(BSL_LS_SOC_COMMON, 6938 (BSL_META_U(unit, 6939 "LCPLL 1 not locked on unit %d " 6940 "status = 0x%08x\n"), unit, rval)); 6941 } 6942 } 6943 6944 /* De-assert LCPLL's post reset */ 6945 rv = READ_TOP_SOFT_RESET_REG_2r(unit, &rval); 6946 if (rv < 0) { 6947 LOG_ERROR(BSL_LS_SOC_COMMON, 6948 (BSL_META_U(unit, 6949 "Reading TOP_SOFT_RESET_REG_2 failed !!\n"))); 6950 return rv; 6951 } 6952 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, TOP_XG_PLL0_POST_RST_Lf, 1); 6953 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, TOP_XG_PLL1_POST_RST_Lf, 1); 6954 rv = WRITE_TOP_SOFT_RESET_REG_2r(unit, rval); 6955 if (rv < 0) { 6956 LOG_ERROR(BSL_LS_SOC_COMMON, 6957 (BSL_META_U(unit, 6958 "Writing TOP_SOFT_RESET_REG_2 failed !!\n"))); 6959 return rv; 6960 } 6961 sal_usleep(to_usec); 6962 6963 6964 /* Configure TS PLL */ 6965 ts_ref_freq = soc_property_get(unit, spn_PTP_TS_PLL_FREF, 0); 6966 for (ts_idx =0; ts_idx < (sizeof(triumph3_ts_pll)/sizeof(triumph3_ts_pll[0])); 6967 ++ts_idx) { 6968 if (triumph3_ts_pll[ts_idx].ref_freq == ts_ref_freq) { 6969 break; 6970 }; 6971 } 6972 if (ts_idx >= (sizeof(triumph3_ts_pll)/sizeof(triumph3_ts_pll[0]))) { 6973 ts_idx = 2; /* wrong config, for now use internal 25MHZ reference */ 6974 ts_ref_freq = 0; 6975 } 6976 6977 SOC_IF_ERROR_RETURN(READ_TOP_TS_PLL_CTRL_2r(unit,&rval)); 6978 soc_reg_field_set(unit, TOP_TS_PLL_CTRL_2r, &rval, PDIVf, 6979 soc_property_get(unit, spn_PTP_TS_PLL_PDIV, 6980 triumph3_ts_pll[ts_idx].pdiv)); 6981 soc_reg_field_set(unit, TOP_TS_PLL_CTRL_2r, &rval, CH0_MDIVf, 6982 soc_property_get(unit, spn_PTP_TS_PLL_MNDIV, 6983 triumph3_ts_pll[ts_idx].mdiv)); 6984 WRITE_TOP_TS_PLL_CTRL_2r(unit, rval); 6985 6986 SOC_IF_ERROR_RETURN(READ_TOP_TS_PLL_CTRL_3r(unit,&rval)); 6987 soc_reg_field_set(unit, TOP_TS_PLL_CTRL_3r, &rval, NDIV_INTf, 6988 soc_property_get(unit, spn_PTP_TS_PLL_N, 6989 triumph3_ts_pll[ts_idx].ndiv_int)); 6990 soc_reg_field_set(unit, TOP_TS_PLL_CTRL_3r, &rval, NDIV_FRACf, 6991 triumph3_ts_pll[ts_idx].ndiv_frac); 6992 WRITE_TOP_TS_PLL_CTRL_3r(unit, rval); 6993 6994 SOC_IF_ERROR_RETURN(READ_TOP_TS_PLL_CTRL_4r(unit,&rval)); 6995 soc_reg_field_set(unit, TOP_TS_PLL_CTRL_4r, &rval, KAf, 6996 soc_property_get(unit, spn_PTP_TS_KA, 6997 triumph3_ts_pll[ts_idx].ka)); 6998 soc_reg_field_set(unit, TOP_TS_PLL_CTRL_4r, &rval, KIf, 6999 soc_property_get(unit, spn_PTP_TS_KI, 7000 triumph3_ts_pll[ts_idx].ki)); 7001 soc_reg_field_set(unit, TOP_TS_PLL_CTRL_4r, &rval, KPf, 7002 soc_property_get(unit, spn_PTP_TS_KP, 7003 triumph3_ts_pll[ts_idx].kp)); 7004 soc_reg_field_set(unit, TOP_TS_PLL_CTRL_4r, &rval, REFCLK_SELf, 7005 (ts_ref_freq != 0)); 7006 WRITE_TOP_TS_PLL_CTRL_4r(unit, rval); 7007 7008 /* Set 250Mhz (implies 4ns resolution) default timesync clock to 7009 calculate assymentric delays */ 7010 SOC_TIMESYNC_PLL_CLOCK_NS(unit) = (1/250 * 1000); /* clock period in nanoseconds */ 7011 7012 /* Configure BS PLL */ 7013 bs_ref_freq = soc_property_get(unit, spn_PTP_BS_FREF, 0); 7014 for (bs_idx =0; bs_idx < (sizeof(triumph3_bs_pll)/sizeof(triumph3_bs_pll[0])); 7015 ++bs_idx) { 7016 if (triumph3_bs_pll[bs_idx].ref_freq == bs_ref_freq) { 7017 break; 7018 }; 7019 } 7020 if (bs_idx >= (sizeof(triumph3_bs_pll)/sizeof(triumph3_bs_pll[0]))) { 7021 bs_idx = 2; /* wrong config, for now use internal 25MHZ reference */ 7022 bs_ref_freq = 0; 7023 } 7024 SOC_IF_ERROR_RETURN(READ_TOP_BS_PLL_CTRL_0r(unit,&rval)); 7025 soc_reg_field_set(unit, TOP_BS_PLL_CTRL_0r, &rval, VCO_DIV2f, 7026 1); /* soc_property_get(unit, spn_BROAD_SYNC_VCO_DIV2, 1)); */ 7027 WRITE_TOP_BS_PLL_CTRL_0r(unit, rval); 7028 7029 SOC_IF_ERROR_RETURN(READ_TOP_BS_PLL_CTRL_2r(unit,&rval)); 7030 soc_reg_field_set(unit, TOP_BS_PLL_CTRL_2r, &rval, PDIVf, 7031 soc_property_get(unit, spn_PTP_BS_PDIV, 7032 triumph3_bs_pll[bs_idx].pdiv)); 7033 soc_reg_field_set(unit, TOP_BS_PLL_CTRL_2r, &rval, CH0_MDIVf, 7034 soc_property_get(unit, spn_PTP_BS_MNDIV, 7035 triumph3_bs_pll[bs_idx].mdiv)); 7036 WRITE_TOP_BS_PLL_CTRL_2r(unit, rval); 7037 7038 SOC_IF_ERROR_RETURN(READ_TOP_BS_PLL_CTRL_3r(unit,&rval)); 7039 soc_reg_field_set(unit, TOP_BS_PLL_CTRL_3r, &rval, NDIV_INTf, 7040 soc_property_get(unit, spn_PTP_BS_NDIV_INT, 7041 triumph3_bs_pll[bs_idx].ndiv_int)); 7042 soc_reg_field_set(unit, TOP_BS_PLL_CTRL_3r, &rval, NDIV_FRACf, 7043 triumph3_bs_pll[bs_idx].ndiv_frac); 7044 WRITE_TOP_BS_PLL_CTRL_3r(unit, rval); 7045 7046 SOC_IF_ERROR_RETURN(READ_TOP_BS_PLL_CTRL_4r(unit,&rval)); 7047 soc_reg_field_set(unit, TOP_BS_PLL_CTRL_4r, &rval, KAf, 7048 soc_property_get(unit, spn_PTP_BS_KA, 7049 triumph3_bs_pll[bs_idx].ka)); 7050 soc_reg_field_set(unit, TOP_BS_PLL_CTRL_4r, &rval, KIf, 7051 soc_property_get(unit, spn_PTP_BS_KI, 7052 triumph3_bs_pll[bs_idx].ki)); 7053 soc_reg_field_set(unit, TOP_BS_PLL_CTRL_4r, &rval, KPf, 7054 soc_property_get(unit, spn_PTP_BS_KP, 7055 triumph3_bs_pll[bs_idx].kp)); 7056 soc_reg_field_set(unit, TOP_BS_PLL_CTRL_4r, &rval, REFCLK_SELf, 7057 (bs_ref_freq != 0)); 7058 WRITE_TOP_BS_PLL_CTRL_4r(unit, rval); 7059 7060 /* Timesync and broadsync out of reset */ 7061 rv = READ_TOP_SOFT_RESET_REG_2r(unit, &rval); 7062 if (rv < 0) { 7063 LOG_ERROR(BSL_LS_SOC_COMMON, 7064 (BSL_META_U(unit, 7065 "Reading TOP_SOFT_RESET_REG_2 failed !!\n"))); 7066 return rv; 7067 } 7068 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, TOP_TS_PLL_RST_Lf, 1); 7069 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, TOP_BS_PLL_RST_Lf, 1); 7070 rv = WRITE_TOP_SOFT_RESET_REG_2r(unit, rval); 7071 if (rv < 0) { 7072 LOG_ERROR(BSL_LS_SOC_COMMON, 7073 (BSL_META_U(unit, 7074 "Writing TOP_SOFT_RESET_REG_2 failed !!\n"))); 7075 return rv; 7076 } 7077 sal_usleep(to_usec); 7078 7079 /* Wait for the BS/TS pll to lock */ 7080 if (!SAL_BOOT_SIMULATION) { 7081 7082 rv = READ_TOP_TS_PLL_STATUSr(unit, &rval); 7083 if (rv < 0) { 7084 LOG_ERROR(BSL_LS_SOC_COMMON, 7085 (BSL_META_U(unit, 7086 "Reading TOP_TS_PLL_STATUS failed !!\n"))); 7087 return rv; 7088 } 7089 if (!soc_reg_field_get(unit, TOP_TS_PLL_STATUSr, rval, PLL_LOCKf)) { 7090 LOG_ERROR(BSL_LS_SOC_COMMON, 7091 (BSL_META_U(unit, 7092 "TimeSync PLL not locked on unit %d " 7093 "status = 0x%08x\n"), unit, rval)); 7094 } 7095 7096 rv = READ_TOP_BS_PLL_STATUSr(unit, &rval); 7097 if (rv < 0) { 7098 LOG_ERROR(BSL_LS_SOC_COMMON, 7099 (BSL_META_U(unit, 7100 "Reading TOP_BS_PLL_STATUS failed !!\n"))); 7101 return rv; 7102 } 7103 if (!soc_reg_field_get(unit, TOP_BS_PLL_STATUSr, rval, PLL_LOCKf)) { 7104 LOG_ERROR(BSL_LS_SOC_COMMON, 7105 (BSL_META_U(unit, 7106 "BroadSync PLL not locked on unit %d " 7107 "status = 0x%08x\n"), unit, rval)); 7108 } 7109 } 7110 7111 /* Deassert Post reset */ 7112 rv = READ_TOP_SOFT_RESET_REG_2r(unit, &rval); 7113 if (rv < 0) { 7114 LOG_ERROR(BSL_LS_SOC_COMMON, 7115 (BSL_META_U(unit, 7116 "Reading TOP_SOFT_RESET_REG_2 failed !!\n"))); 7117 return rv; 7118 } 7119 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, TOP_TS_PLL_POST_RST_Lf, 7120 1); 7121 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, TOP_BS_PLL_POST_RST_Lf, 7122 1); 7123 rv = WRITE_TOP_SOFT_RESET_REG_2r(unit, rval); 7124 if (rv < 0) { 7125 LOG_ERROR(BSL_LS_SOC_COMMON, 7126 (BSL_META_U(unit, 7127 "Writing TOP_SOFT_RESET_REG_2 failed !!\n"))); 7128 return rv; 7129 } 7130 7131 soc_cm_get_id(unit, &dev_id_local, &rev_id_local); 7132 SOC_IF_ERROR_RETURN(READ_TOP_SWITCH_FEATURE_ENABLEr(unit, &rval)); 7133 if (rval & 0x1) { 7134 /* BOND_1588_ENABLE */ 7135 SOC_FEATURE_SET(unit, soc_feature_timesync_support); 7136 if (((dev_id_local == BCM56545_DEVICE_ID) && 7137 (rev_id_local <= BCM56545_A1_REV_ID)) || 7138 ((dev_id_local == BCM56546_DEVICE_ID) && 7139 (rev_id_local <= BCM56546_A1_REV_ID))) { 7140 /* 7141 * BOND_1588_ENABLE bit is set on 56545/6 A0,A1s 7142 * But Timesync & ESM support is not available on them. 7143 */ 7144 SOC_FEATURE_CLEAR(unit, soc_feature_timesync_support); 7145 sop->memState[ESM_ACL_ACTION_CONTROLm].index_max = -1; 7146 sop->memState[ESM_ACL_PROFILEm].index_max = -1; 7147 } 7148 7149 if ((dev_id_local == BCM56545_DEVICE_ID) && 7150 (rev_id_local == BCM56545_A1_REV_ID)) { 7151 SOC_FEATURE_CLEAR(unit, soc_feature_etu_support); 7152 SOC_FEATURE_CLEAR(unit, soc_feature_esm_support); 7153 SOC_FEATURE_CLEAR(unit, soc_feature_esm_correction); 7154 } 7155 7156 if (((dev_id_local == BCM56545_DEVICE_ID) && 7157 (rev_id_local == BCM56545_B0_REV_ID)) || 7158 ((dev_id_local == BCM56546_DEVICE_ID) && 7159 (rev_id_local == BCM56546_B0_REV_ID))) { 7160 SOC_FEATURE_CLEAR(unit, soc_feature_regex); 7161 SOC_FEATURE_CLEAR(unit, soc_feature_ptp); 7162 SOC_FEATURE_CLEAR(unit, soc_feature_l3_reduced_defip_table); 7163 SOC_FEATURE_SET(unit, soc_feature_mpls); 7164 SOC_FEATURE_SET(unit, soc_feature_oam); 7165 SOC_FEATURE_SET(unit, soc_feature_esm_support); 7166 /* L3 Next hop */ 7167 sop->memState[INITIAL_ING_L3_NEXT_HOPm].index_max = 65535; 7168 sop->memState[ING_L3_NEXT_HOPm].index_max = 65535; 7169 sop->memState[EGR_L3_NEXT_HOPm].index_max = 65535; 7170 sop->memState[INITIAL_PROT_NHI_TABLEm].index_max = 65535; 7171 sop->memState[ING_L3_NEXT_HOP_ATTRIBUTE_1_INDEXm].index_max = 32767; 7172 /* L3 IPMC groups */ 7173 sop->memState[L3_IPMCm].index_max = 16383; 7174 sop->memState[L3_IPMC_1m].index_max = 16383; 7175 sop->memState[L3_IPMC_REMAPm].index_max = 16383; 7176 sop->memState[EGR_IPMCm].index_max = 16383; 7177 sop->memState[MMU_REPL_GROUPm].index_max = 16383; 7178 /* Counters */ 7179 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_0m].index_max = 4095; 7180 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_1m].index_max = 4095; 7181 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_2m].index_max = 4095; 7182 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_3m].index_max = 4095; 7183 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_4m].index_max = 4095; 7184 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_5m].index_max = 4095; 7185 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_6m].index_max = 4095; 7186 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_7m].index_max = 4095; 7187 /* OAM */ 7188 sop->memState[OAM_LM_COUNTERSm].index_max = 16383; 7189 sop->memState[LMEPm].index_max = 2047; 7190 sop->memState[LMEP_DAm].index_max = 2047; 7191 sop->memState[RMEPm].index_max = 8191; 7192 /* Others */ 7193 sop->memState[VLAN_PROFILE_TABm].index_max = 127; 7194 sop->memState[VLAN_PROFILE_2m].index_max = 127; 7195 /* REGEX DISABLE */ 7196 sop->memState[AXP_SM_CHAR_REMAP0m].index_max = -1; 7197 sop->memState[AXP_SM_CHAR_REMAP1m].index_max = -1; 7198 sop->memState[AXP_SM_CHAR_REMAP2m].index_max = -1; 7199 sop->memState[AXP_SM_CHAR_REMAP3m].index_max = -1; 7200 sop->memState[AXP_SM_CHAR_REMAP4m].index_max = -1; 7201 sop->memState[AXP_SM_CHAR_REMAP5m].index_max = -1; 7202 sop->memState[AXP_SM_CHAR_REMAP6m].index_max = -1; 7203 sop->memState[AXP_SM_CHAR_REMAP7m].index_max = -1; 7204 sop->memState[AXP_SM_CHAR_REMAP8m].index_max = -1; 7205 sop->memState[AXP_SM_CHAR_REMAP9m].index_max = -1; 7206 sop->memState[AXP_SM_CHAR_REMAP10m].index_max = -1; 7207 sop->memState[AXP_SM_CHAR_REMAP11m].index_max = -1; 7208 sop->memState[AXP_SM_CHAR_REMAP12m].index_max = -1; 7209 sop->memState[AXP_SM_CHAR_REMAP13m].index_max = -1; 7210 sop->memState[AXP_SM_CHAR_REMAP14m].index_max = -1; 7211 sop->memState[AXP_SM_CHAR_REMAP15m].index_max = -1; 7212 sop->memState[AXP_SM_CHAR_REMAP16m].index_max = -1; 7213 sop->memState[AXP_SM_CHAR_REMAP17m].index_max = -1; 7214 sop->memState[AXP_SM_CHAR_REMAP18m].index_max = -1; 7215 sop->memState[AXP_SM_CHAR_REMAP19m].index_max = -1; 7216 sop->memState[AXP_SM_CHAR_REMAP20m].index_max = -1; 7217 sop->memState[AXP_SM_CHAR_REMAP21m].index_max = -1; 7218 sop->memState[AXP_SM_CHAR_REMAP22m].index_max = -1; 7219 sop->memState[AXP_SM_CHAR_REMAP23m].index_max = -1; 7220 sop->memState[AXP_SM_CHAR_REMAP24m].index_max = -1; 7221 sop->memState[AXP_SM_CHAR_REMAP25m].index_max = -1; 7222 sop->memState[AXP_SM_CHAR_REMAP26m].index_max = -1; 7223 sop->memState[AXP_SM_CHAR_REMAP27m].index_max = -1; 7224 sop->memState[AXP_SM_CHAR_REMAP28m].index_max = -1; 7225 sop->memState[AXP_SM_CHAR_REMAP29m].index_max = -1; 7226 sop->memState[AXP_SM_CHAR_REMAP30m].index_max = -1; 7227 sop->memState[AXP_SM_CHAR_REMAP31m].index_max = -1; 7228 sop->memState[AXP_SM_FLOW_TABLE_BULK_MATCH_DATAm].index_max = -1; 7229 sop->memState[AXP_SM_FLOW_TABLE_BULK_MATCH_MASKm].index_max = -1; 7230 sop->memState[AXP_SM_FLOW_TABLE_BULK_REPLACE_DATAm].index_max = -1; 7231 sop->memState[AXP_SM_FLOW_TABLE_BULK_REPLACE_MASKm].index_max = -1; 7232 sop->memState[AXP_SM_FLOW_TABLE_MEMm].index_max = -1; 7233 sop->memState[AXP_SM_MATCH_COUNTERS_MEM0m].index_max = -1; 7234 sop->memState[AXP_SM_MATCH_COUNTERS_MEM1m].index_max = -1; 7235 sop->memState[AXP_SM_MATCH_COUNTERS_MEM2m].index_max = -1; 7236 sop->memState[AXP_SM_MATCH_COUNTERS_MEM3m].index_max = -1; 7237 sop->memState[AXP_SM_MATCH_TABLE_BULK_MATCH_DATAm].index_max = -1; 7238 sop->memState[AXP_SM_MATCH_TABLE_BULK_MATCH_MASKm].index_max = -1; 7239 sop->memState[AXP_SM_MATCH_TABLE_BULK_REPLACE_DATAm].index_max = -1; 7240 sop->memState[AXP_SM_MATCH_TABLE_BULK_REPLACE_MASKm].index_max = -1; 7241 sop->memState[AXP_SM_MATCH_TABLE_MEM0m].index_max = -1; 7242 sop->memState[AXP_SM_MATCH_TABLE_MEM1m].index_max = -1; 7243 sop->memState[AXP_SM_MATCH_TABLE_MEM2m].index_max = -1; 7244 sop->memState[AXP_SM_MATCH_TABLE_MEM3m].index_max = -1; 7245 sop->memState[AXP_SM_PACKET_BUFFER_MEMm].index_max = -1; 7246 sop->memState[AXP_SM_STATE_TABLE_BULK_MATCH_DATAm].index_max = -1; 7247 sop->memState[AXP_SM_STATE_TABLE_BULK_MATCH_MASKm].index_max = -1; 7248 sop->memState[AXP_SM_STATE_TABLE_BULK_REPLACE_DATAm].index_max = -1; 7249 sop->memState[AXP_SM_STATE_TABLE_BULK_REPLACE_MASKm].index_max = -1; 7250 sop->memState[AXP_SM_STATE_TABLE_MEM0m].index_max = -1; 7251 sop->memState[AXP_SM_STATE_TABLE_MEM1m].index_max = -1; 7252 sop->memState[AXP_SM_STATE_TABLE_MEM2m].index_max = -1; 7253 sop->memState[AXP_SM_STATE_TABLE_MEM3m].index_max = -1; 7254 sop->memState[AXP_SM_STATE_TABLE_MEM4m].index_max = -1; 7255 sop->memState[AXP_SM_STATE_TABLE_MEM5m].index_max = -1; 7256 sop->memState[AXP_SM_STATE_TABLE_MEM6m].index_max = -1; 7257 sop->memState[AXP_SM_STATE_TABLE_MEM7m].index_max = -1; 7258 sop->memState[FT_SESSIONm].index_max = -1; 7259 sop->memState[FT_EXPORT_FIFOm].index_max = -1; 7260 sop->memState[FT_EXPORT_DATA_ONLYm].index_max = -1; 7261 sop->memState[FT_EOP_TBLm].index_max = -1; 7262 sop->memState[FT_AGE_PROFILEm].index_max = -1; 7263 sop->memState[FT_L4PORTm].index_max = -1; 7264 sop->memState[FT_DST_LAG_CONFIGm].index_max = -1; 7265 sop->memState[FT_DST_PORT_CONFIGm].index_max = -1; 7266 sop->memState[FT_POLICYm].index_max = -1; 7267 sop->memState[FT_SESSION_IPV6m].index_max = -1; 7268 sop->memState[FT_EXPORT_CNTR_ONLYm].index_max = -1; 7269 /* MMU buffer */ 7270 _soc_tr3_mmu_buffer_cells[unit] = _TR3_MMU_TOTAL_CELLS_24K; 7271 /* ingress_pool */ 7272 si->size_flex_ingress_pool = 4096; 7273 /* L3 DEF_IP */ 7274 SOC_CONTROL(unit)->l3_defip_max_tcams = _SOC_TR3_DEFIP_MAX_TCAMS; 7275 SOC_CONTROL(unit)->l3_defip_tcam_size = _SOC_TR3_DEFIP_TCAM_DEPTH; 7276 sop->memState[L3_DEFIPm].index_max = 8191; 7277 sop->memState[L3_DEFIP_ONLYm].index_max = 8191; 7278 sop->memState[L3_DEFIP_DATA_ONLYm].index_max = 8191; 7279 sop->memState[L3_DEFIP_HIT_ONLYm].index_max = 8191; 7280 /* L3_DEFIP sizing */ 7281 if (soc_property_get(unit, "l3_defip_sizing", TRUE)) { 7282 defip_config = soc_property_get(unit, spn_IPV6_LPM_128B_ENABLE, 1); 7283 7284 num_ipv6_128b_entries = soc_property_get(unit, 7285 spn_NUM_IPV6_LPM_128B_ENTRIES, 7286 (defip_config ? 2048 : 0)); 7287 num_ipv6_128b_entries = num_ipv6_128b_entries + 7288 (num_ipv6_128b_entries % 2); 7289 config_v6_entries = num_ipv6_128b_entries; 7290 if (soc_property_get(unit, spn_LPM_SCALING_ENABLE, 0)) { 7291 num_ipv6_128b_entries = 0; 7292 if (!soc_property_get(unit, spn_LPM_IPV6_128B_RESERVED, 1)) { 7293 config_v6_entries = ((config_v6_entries / 7294 SOC_CONTROL(unit)->l3_defip_tcam_size) + 7295 ((config_v6_entries % 7296 SOC_CONTROL(unit)->l3_defip_tcam_size) 7297 ? 1 : 0)) * SOC_CONTROL(unit)->l3_defip_tcam_size; 7298 } 7299 7300 } 7301 7302 sop->memState[L3_DEFIP_PAIR_128m].index_max = 7303 num_ipv6_128b_entries - 1; 7304 sop->memState[L3_DEFIP_PAIR_128_ONLYm].index_max = 7305 num_ipv6_128b_entries - 1; 7306 sop->memState[L3_DEFIP_PAIR_128_DATA_ONLYm].index_max = 7307 num_ipv6_128b_entries - 1; 7308 sop->memState[L3_DEFIP_PAIR_128_HIT_ONLYm].index_max = 7309 num_ipv6_128b_entries - 1; 7310 sop->memState[L3_DEFIPm].index_max = 7311 (SOC_CONTROL(unit)->l3_defip_max_tcams * 7312 SOC_CONTROL(unit)->l3_defip_tcam_size) - 7313 (num_ipv6_128b_entries * 2) - 1; 7314 sop->memState[L3_DEFIP_ONLYm].index_max = 7315 sop->memState[L3_DEFIPm].index_max; 7316 sop->memState[L3_DEFIP_DATA_ONLYm].index_max = 7317 sop->memState[L3_DEFIPm].index_max; 7318 sop->memState[L3_DEFIP_HIT_ONLYm].index_max = 7319 sop->memState[L3_DEFIPm].index_max; 7320 SOC_CONTROL(unit)->l3_defip_index_remap = num_ipv6_128b_entries; 7321 soc_l3_defip_indexes_init(unit, config_v6_entries); 7322 } 7323 } 7324 } else { 7325 if ((dev_id_local == BCM56545_DEVICE_ID) || 7326 (dev_id_local == BCM56546_DEVICE_ID)) { 7327 sop->memState[ESM_ACL_ACTION_CONTROLm].index_max = -1; 7328 sop->memState[ESM_ACL_PROFILEm].index_max = -1; 7329 SOC_FEATURE_CLEAR(unit, soc_feature_etu_support); 7330 SOC_FEATURE_CLEAR(unit, soc_feature_esm_support); 7331 SOC_FEATURE_CLEAR(unit, soc_feature_esm_correction); 7332 } 7333 } 7334 7335 /* 7336 * Bring port blocks out of reset 7337 */ 7338 rv = READ_TOP_SOFT_RESET_REGr(unit, &rval); 7339 if (rv < 0) { 7340 LOG_ERROR(BSL_LS_SOC_COMMON, 7341 (BSL_META_U(unit, 7342 "Reading TOP_SOFT_RESET_REG failed !!\n"))); 7343 return rv; 7344 } 7345 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_XTP0_RST_Lf, 1); 7346 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_XTP1_RST_Lf, 1); 7347 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_XTP2_RST_Lf, 1); 7348 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_XTP3_RST_Lf, 1); 7349 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_XLP0_RST_Lf, 1); 7350 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_XLP1_RST_Lf, 1); 7351 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_CLP0_RST_Lf, 1); 7352 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_CLP1_RST_Lf, 1); 7353 rv = WRITE_TOP_SOFT_RESET_REGr(unit, rval); 7354 if (rv < 0) { 7355 LOG_ERROR(BSL_LS_SOC_COMMON, 7356 (BSL_META_U(unit, 7357 "Writing TOP_SOFT_RESET_REG failed !!\n"))); 7358 return rv; 7359 } 7360 7361 sal_usleep(to_usec); 7362 7363 /* Bring network sync out of reset */ 7364 rv = READ_TOP_SOFT_RESET_REGr(unit, &rval); 7365 if (rv < 0) { 7366 LOG_ERROR(BSL_LS_SOC_COMMON, 7367 (BSL_META_U(unit, 7368 "Reading TOP_SOFT_RESET_REG failed !!\n"))); 7369 return rv; 7370 } 7371 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_NS_RST_Lf, 1); 7372 rv = WRITE_TOP_SOFT_RESET_REGr(unit, rval); 7373 if (rv < 0) { 7374 LOG_ERROR(BSL_LS_SOC_COMMON, 7375 (BSL_META_U(unit, 7376 "Writing TOP_SOFT_RESET_REG failed !!\n"))); 7377 return rv; 7378 } 7379 7380 sal_usleep(to_usec); 7381 7382 WRITE_CMIC_SBUS_TIMEOUTr(unit, 0x7d0); 7383 7384 /* Bring IP, EP, ISM, ETU, AXP, and MMU blocks out of reset */ 7385 rv = READ_TOP_SOFT_RESET_REGr(unit, &rval); 7386 if (rv < 0) { 7387 LOG_ERROR(BSL_LS_SOC_COMMON, 7388 (BSL_META_U(unit, 7389 "Reading TOP_SOFT_RESET_REG failed !!\n"))); 7390 return rv; 7391 } 7392 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_EP_RST_Lf, 1); 7393 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_IP_RST_Lf, 1); 7394 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_MMU_RST_Lf, 1); 7395 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_ISM_RST_Lf, 1); 7396 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_AXP_RST_Lf, 1); 7397 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_ETU_RST_Lf, 1); 7398 rv = WRITE_TOP_SOFT_RESET_REGr(unit, rval); 7399 if (rv < 0) { 7400 LOG_ERROR(BSL_LS_SOC_COMMON, 7401 (BSL_META_U(unit, 7402 "Writing TOP_SOFT_RESET_REG failed !!\n"))); 7403 return rv; 7404 } 7405 7406 sal_usleep(to_usec); 7407 7408 SOC_IF_ERROR_RETURN(READ_TOP_PVTMON_CTRL_1r(unit, &rval)); 7409 soc_reg_field_set(unit, TOP_PVTMON_CTRL_1r, &rval, PVTMON_RESET_Nf, 1); 7410 SOC_IF_ERROR_RETURN(WRITE_TOP_PVTMON_CTRL_1r(unit, rval)); 7411 soc_reg_field_set(unit, TOP_PVTMON_CTRL_1r, &rval, PVTMON_RESET_Nf, 0); 7412 SOC_IF_ERROR_RETURN(WRITE_TOP_PVTMON_CTRL_1r(unit, rval)); 7413 soc_reg_field_set(unit, TOP_PVTMON_CTRL_1r, &rval, PVTMON_RESET_Nf, 1); 7414 SOC_IF_ERROR_RETURN(WRITE_TOP_PVTMON_CTRL_1r(unit, rval)); 7415 7416 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REG_2r(unit, &rval)); 7417 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, 7418 TOP_TEMP_MON_PEAK_RST_Lf, 0); 7419 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REG_2r(unit, rval)); 7420 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, 7421 TOP_TEMP_MON_PEAK_RST_Lf, 1); 7422 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REG_2r(unit, rval)); 7423 7424 /* need higher timeout for access to 480 bit tcam entries */ 7425 WRITE_CMIC_SBUS_TIMEOUTr(unit, 0x7A120); 7426 /* Enable access to ESM regs */ 7427 if (soc_feature(unit, soc_feature_esm_support)) { 7428 to_usec = SAL_BOOT_QUICKTURN ? (250 * MILLISECOND_USEC) : 7429 (10 * MILLISECOND_USEC); 7430 7431 rv = READ_ESMIF_INIT_CONFIGr(unit, &rval); 7432 if (rv < 0) { 7433 LOG_ERROR(BSL_LS_SOC_COMMON, 7434 (BSL_META_U(unit, 7435 "Reading ESMIF_INIT_CONFIG failed !!\n"))); 7436 return rv; 7437 } 7438 soc_reg_field_set(unit, ESMIF_INIT_CONFIGr, &rval, LATENCYf, 870); 7439 rv = WRITE_ESMIF_INIT_CONFIGr(unit, rval); 7440 if (rv < 0) { 7441 LOG_ERROR(BSL_LS_SOC_COMMON, 7442 (BSL_META_U(unit, 7443 "Writing ESMIF_INIT_CONFIG failed !!\n"))); 7444 return rv; 7445 } 7446 soc_reg_field_set(unit, ESMIF_INIT_CONFIGr, &rval, WR_ENABLEf, 1); 7447 sal_usleep(to_usec); 7448 soc_reg_field_set(unit, ESMIF_INIT_CONFIGr, &rval, 7449 IESMIF_BYPASS_ENABLEf, 0); 7450 rv = WRITE_ESMIF_INIT_CONFIGr(unit, rval); 7451 if (rv < 0) { 7452 LOG_ERROR(BSL_LS_SOC_COMMON, 7453 (BSL_META_U(unit, 7454 "Writing ESMIF_INIT_CONFIG failed !!\n"))); 7455 return rv; 7456 } 7457 } 7458 /* Set MDIO IO PAD voltage */ 7459 if (0 != soc_property_get(unit, spn_MDIO_IO_VOLTAGE, 0)) { 7460 rv = READ_TOP_MISC_CONTROLr(unit, &rval); 7461 if (rv < 0) { 7462 LOG_ERROR(BSL_LS_SOC_COMMON, 7463 (BSL_META_U(unit, 7464 "Reading TOP_MISC_CONTROL failed !!\n"))); 7465 return rv; 7466 } 7467 soc_reg_field_set(unit, TOP_MISC_CONTROLr, &rval, 7468 XG_MDIO0_CL_SELf, 1); 7469 rv = WRITE_TOP_MISC_CONTROLr(unit, rval); 7470 if (rv < 0) { 7471 LOG_ERROR(BSL_LS_SOC_COMMON, 7472 (BSL_META_U(unit, 7473 "Writing TOP_MISC_CONTROL failed !!\n"))); 7474 return rv; 7475 } 7476 } 7477 return SOC_E_NONE; 7478 } 7479 7480 7481 #ifdef BCM_ISM_SUPPORT 7482 /* Default mem config size */ 7483 static soc_ism_mem_size_config_t _ism_alloc_size[_ISM_MAX_MEMS] = { 7484 { SOC_ISM_MEM_VLAN_XLATE, _ISM_MEM_VLAN_XLATE_SIZE , 0 , 0}, 7485 { SOC_ISM_MEM_L2_ENTRY, _ISM_MEM_L2_SIZE , 0 , 0}, 7486 { SOC_ISM_MEM_L3_ENTRY, _ISM_MEM_L3_SIZE , 0 , 0}, 7487 { SOC_ISM_MEM_EP_VLAN_XLATE, _ISM_MEM_EP_VLAN_XLATE_SIZE , 0 , 0}, 7488 { SOC_ISM_MEM_MPLS, _ISM_MEM_MPLS_SIZE , 0 , 0}, 7489 { SOC_ISM_MEM_ESM_L2, 0 , 0 , 0}, 7490 { SOC_ISM_MEM_ESM_L3, 0 , 0 , 0}, 7491 { SOC_ISM_MEM_ESM_ACL, 0 , 0 , 0} 7492 }; 7493 #endif 7494 7495 /* Return the TR3 devid core clock speed in MHz */ 7496 int 7497 soc_tr3_core_clock_speed(int unit) 7498 { 7499 uint16 dev_id; 7500 uint8 rev_id; 7501 7502 soc_cm_get_id(unit, &dev_id, &rev_id); 7503 7504 switch (dev_id) { 7505 case BCM56643_DEVICE_ID: 7506 return SOC_TR3_CORE_CLOCK_450; 7507 case BCM56640_DEVICE_ID: 7508 case BCM56644_DEVICE_ID: 7509 case BCM56648_DEVICE_ID: 7510 case BCM56649_DEVICE_ID: 7511 case BCM56543_DEVICE_ID: 7512 return SOC_TR3_CORE_CLOCK_415; 7513 case BCM56540_DEVICE_ID: 7514 case BCM56541_DEVICE_ID: 7515 case BCM56542_DEVICE_ID: 7516 case BCM56544_DEVICE_ID: 7517 case BCM56545_DEVICE_ID: 7518 case BCM56546_DEVICE_ID: 7519 if (((dev_id == BCM56545_DEVICE_ID) || (dev_id == BCM56546_DEVICE_ID)) && 7520 (!soc_feature(unit, soc_feature_regex))) { 7521 return SOC_TR3_CORE_CLOCK_450; 7522 } 7523 return SOC_TR3_CORE_CLOCK_315; 7524 default: 7525 return SOC_TR3_CORE_CLOCK_UNKNOWN; 7526 } 7527 } 7528 7529 STATIC int 7530 _soc_tr3_set_defip_table_size(int unit, soc_mem_t mem, int size) 7531 { 7532 soc_persist_t *sop = SOC_PERSIST(unit); 7533 7534 if (mem == L3_DEFIPm) { 7535 sop->memState[L3_DEFIPm].index_max = size; 7536 sop->memState[L3_DEFIP_ONLYm].index_max = size; 7537 sop->memState[L3_DEFIP_DATA_ONLYm].index_max = size; 7538 sop->memState[L3_DEFIP_HIT_ONLYm].index_max = size; 7539 } else if (mem == L3_DEFIP_PAIR_128m) { 7540 sop->memState[L3_DEFIP_PAIR_128m].index_max = size; 7541 sop->memState[L3_DEFIP_PAIR_128_ONLYm].index_max = size; 7542 sop->memState[L3_DEFIP_PAIR_128_DATA_ONLYm].index_max = size; 7543 sop->memState[L3_DEFIP_PAIR_128_HIT_ONLYm].index_max = size; 7544 } else { 7545 return SOC_E_PARAM; 7546 } 7547 7548 return SOC_E_NONE; 7549 } 7550 7551 int 7552 soc_tr3_mem_config(int unit, int dev_id, int rev_id) 7553 { 7554 int rv = SOC_E_NONE; 7555 uint16 scale = 1; 7556 int num_ipv6_128b_entries = 0; 7557 int config_v6_entries = 0; 7558 int defip_config = 0; 7559 int ism_defip_pair_128_size; 7560 int ism_defip_size; 7561 int ism_defip_max_index; 7562 7563 soc_persist_t *sop = SOC_PERSIST(unit); 7564 7565 switch (dev_id) { 7566 case BCM56540_DEVICE_ID: 7567 case BCM56541_DEVICE_ID: 7568 case BCM56542_DEVICE_ID: 7569 case BCM56543_DEVICE_ID: 7570 case BCM56544_DEVICE_ID: 7571 case BCM56545_DEVICE_ID: 7572 case BCM56546_DEVICE_ID: 7573 /* ISM Raw and ESM */ 7574 sop->memState[EXT_L2_ENTRY_1m].index_max = -1; 7575 sop->memState[EXT_L2_ENTRY_2m].index_max = -1; 7576 /* L3 Next hop */ 7577 sop->memState[INITIAL_ING_L3_NEXT_HOPm].index_max = 32767; 7578 sop->memState[ING_L3_NEXT_HOPm].index_max = 32767; 7579 sop->memState[EGR_L3_NEXT_HOPm].index_max = 32767; 7580 sop->memState[INITIAL_PROT_NHI_TABLEm].index_max = 32767; 7581 sop->memState[ING_L3_NEXT_HOP_ATTRIBUTE_1_INDEXm].index_max = 24575; 7582 /* L3 LPM */ 7583 SOC_CONTROL(unit)->l3_defip_max_tcams = _SOC_AP2_DEFIP_MAX_TCAMS; 7584 SOC_CONTROL(unit)->l3_defip_tcam_size = _SOC_AP2_DEFIP_TCAM_DEPTH; 7585 sop->memState[L3_DEFIPm].index_max = 6143; 7586 sop->memState[L3_DEFIP_ONLYm].index_max = 6143; 7587 sop->memState[L3_DEFIP_DATA_ONLYm].index_max = 6143; 7588 sop->memState[L3_DEFIP_HIT_ONLYm].index_max = 6143; 7589 /* L3 IPMC groups */ 7590 sop->memState[L3_IPMCm].index_max = 8191; 7591 sop->memState[L3_IPMC_1m].index_max = 8191; 7592 sop->memState[L3_IPMC_REMAPm].index_max = 8191; 7593 sop->memState[EGR_IPMCm].index_max = 8191; 7594 sop->memState[MMU_REPL_GROUPm].index_max = 8191; 7595 /* L2 VFI */ 7596 sop->memState[VFIm].index_max = 4095; 7597 sop->memState[VFI_1m].index_max = 4095; 7598 sop->memState[EGR_VFIm].index_max = 4095; 7599 /* L3 Tunnels */ 7600 sop->memState[EGR_IP_TUNNELm].index_max = 1023; 7601 sop->memState[EGR_IP_TUNNEL_IPV6m].index_max = 511; 7602 sop->memState[EGR_IP_TUNNEL_MPLSm].index_max = 1023; 7603 sop->memState[EGR_FRAGMENT_ID_TABLEm].index_max = 1023; 7604 /* Virtual ports */ 7605 sop->memState[SOURCE_VP_ATTRIBUTES_2m].index_max = 16383; 7606 sop->memState[SOURCE_VPm].index_max = 16383; 7607 sop->memState[ING_DVP_TABLEm].index_max = 16383; 7608 sop->memState[ING_DVP_2_TABLEm].index_max = 16383; 7609 sop->memState[EGR_DVP_ATTRIBUTEm].index_max = 16383; 7610 sop->memState[EGR_DVP_ATTRIBUTE_1m].index_max = 16383; 7611 /* Counters */ 7612 if (dev_id == BCM56543_DEVICE_ID) { 7613 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_0m].index_max = 4095; 7614 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_1m].index_max = 4095; 7615 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_2m].index_max = 4095; 7616 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_3m].index_max = 4095; 7617 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_4m].index_max = 4095; 7618 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_5m].index_max = 4095; 7619 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_6m].index_max = 4095; 7620 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_7m].index_max = 4095; 7621 } else { 7622 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_0m].index_max = 2047; 7623 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_1m].index_max = 2047; 7624 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_2m].index_max = 2047; 7625 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_3m].index_max = 2047; 7626 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_4m].index_max = 2047; 7627 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_5m].index_max = 2047; 7628 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_6m].index_max = 2047; 7629 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_7m].index_max = 2047; 7630 } 7631 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_8m].index_max = -1; 7632 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_9m].index_max = -1; 7633 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_10m].index_max = -1; 7634 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_11m].index_max = -1; 7635 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_12m].index_max = -1; 7636 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_13m].index_max = -1; 7637 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_14m].index_max = -1; 7638 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_15m].index_max = -1; 7639 sop->memState[ING_FLEX_CTR_OFFSET_TABLE_8m].index_max = -1; 7640 sop->memState[ING_FLEX_CTR_OFFSET_TABLE_9m].index_max = -1; 7641 sop->memState[ING_FLEX_CTR_OFFSET_TABLE_10m].index_max = -1; 7642 sop->memState[ING_FLEX_CTR_OFFSET_TABLE_11m].index_max = -1; 7643 sop->memState[ING_FLEX_CTR_OFFSET_TABLE_12m].index_max = -1; 7644 sop->memState[ING_FLEX_CTR_OFFSET_TABLE_13m].index_max = -1; 7645 sop->memState[ING_FLEX_CTR_OFFSET_TABLE_14m].index_max = -1; 7646 sop->memState[ING_FLEX_CTR_OFFSET_TABLE_15m].index_max = -1; 7647 sop->memState[VLAN_OR_VFI_MAC_COUNTm].index_max = 8191; 7648 sop->memState[VLAN_OR_VFI_MAC_LIMITm].index_max = 8191; 7649 /* LMEP */ 7650 if (dev_id == BCM56543_DEVICE_ID) { 7651 sop->memState[LMEPm].index_max = 2047; 7652 sop->memState[LMEP_DAm].index_max = 2047; 7653 } else { 7654 sop->memState[LMEPm].index_max = 1023; 7655 sop->memState[LMEP_DAm].index_max = 1023; 7656 } 7657 /* RMEP */ 7658 if (dev_id == BCM56543_DEVICE_ID) { 7659 sop->memState[RMEPm].index_max = 8191; 7660 } else { 7661 sop->memState[RMEPm].index_max = 4095; 7662 } 7663 7664 /* MAID_REDUCTION / MA_STATE */ 7665 if (dev_id == BCM56543_DEVICE_ID) { 7666 sop->memState[MAID_REDUCTIONm].index_max = 2047; 7667 sop->memState[MA_STATEm].index_max = 2047; 7668 } else { 7669 sop->memState[MAID_REDUCTIONm].index_max = 1023; 7670 sop->memState[MA_STATEm].index_max = 1023; 7671 } 7672 7673 sop->memState[ESM_ACL_ACTION_CONTROLm].index_max = -1; 7674 sop->memState[ESM_ACL_PROFILEm].index_max = -1; 7675 /* Others */ 7676 sop->memState[L3_IIFm].index_max = 8191; 7677 sop->memState[VLAN_PROFILE_TABm].index_max = 63; 7678 sop->memState[VLAN_PROFILE_2m].index_max = 63; 7679 /* L3_DEFIP sizing */ 7680 if (soc_property_get(unit, "l3_defip_sizing", TRUE)) { 7681 defip_config = soc_property_get(unit, spn_IPV6_LPM_128B_ENABLE, 1); 7682 7683 num_ipv6_128b_entries = soc_property_get(unit, 7684 spn_NUM_IPV6_LPM_128B_ENTRIES, 7685 (defip_config ? 2048 : 0)); 7686 num_ipv6_128b_entries = num_ipv6_128b_entries + 7687 (num_ipv6_128b_entries % 2); 7688 config_v6_entries = num_ipv6_128b_entries; 7689 if (soc_property_get(unit, spn_LPM_SCALING_ENABLE, 0)) { 7690 num_ipv6_128b_entries = 0; 7691 if (!soc_property_get(unit, spn_LPM_IPV6_128B_RESERVED, 1)) { 7692 config_v6_entries = ((config_v6_entries / 7693 SOC_CONTROL(unit)->l3_defip_tcam_size) + 7694 ((config_v6_entries % 7695 SOC_CONTROL(unit)->l3_defip_tcam_size) 7696 ? 1 : 0)) * SOC_CONTROL(unit)->l3_defip_tcam_size; 7697 } 7698 7699 } 7700 7701 sop->memState[L3_DEFIP_PAIR_128m].index_max = 7702 num_ipv6_128b_entries - 1; 7703 sop->memState[L3_DEFIP_PAIR_128_ONLYm].index_max = 7704 num_ipv6_128b_entries - 1; 7705 sop->memState[L3_DEFIP_PAIR_128_DATA_ONLYm].index_max = 7706 num_ipv6_128b_entries - 1; 7707 sop->memState[L3_DEFIP_PAIR_128_HIT_ONLYm].index_max = 7708 num_ipv6_128b_entries - 1; 7709 sop->memState[L3_DEFIPm].index_max = 7710 (SOC_CONTROL(unit)->l3_defip_max_tcams * 7711 SOC_CONTROL(unit)->l3_defip_tcam_size) - 7712 (num_ipv6_128b_entries * 2) - 1; 7713 sop->memState[L3_DEFIP_ONLYm].index_max = 7714 sop->memState[L3_DEFIPm].index_max; 7715 sop->memState[L3_DEFIP_DATA_ONLYm].index_max = 7716 sop->memState[L3_DEFIPm].index_max; 7717 sop->memState[L3_DEFIP_HIT_ONLYm].index_max = 7718 sop->memState[L3_DEFIPm].index_max; 7719 SOC_CONTROL(unit)->l3_defip_index_remap = num_ipv6_128b_entries; 7720 soc_l3_defip_indexes_init(unit, config_v6_entries); 7721 } 7722 if (dev_id == BCM56543_DEVICE_ID) { 7723 /* REGEX DISABLE */ 7724 sop->memState[AXP_SM_CHAR_REMAP0m].index_max = -1; 7725 sop->memState[AXP_SM_CHAR_REMAP1m].index_max = -1; 7726 sop->memState[AXP_SM_CHAR_REMAP2m].index_max = -1; 7727 sop->memState[AXP_SM_CHAR_REMAP3m].index_max = -1; 7728 sop->memState[AXP_SM_CHAR_REMAP4m].index_max = -1; 7729 sop->memState[AXP_SM_CHAR_REMAP5m].index_max = -1; 7730 sop->memState[AXP_SM_CHAR_REMAP6m].index_max = -1; 7731 sop->memState[AXP_SM_CHAR_REMAP7m].index_max = -1; 7732 sop->memState[AXP_SM_CHAR_REMAP8m].index_max = -1; 7733 sop->memState[AXP_SM_CHAR_REMAP9m].index_max = -1; 7734 sop->memState[AXP_SM_CHAR_REMAP10m].index_max = -1; 7735 sop->memState[AXP_SM_CHAR_REMAP11m].index_max = -1; 7736 sop->memState[AXP_SM_CHAR_REMAP12m].index_max = -1; 7737 sop->memState[AXP_SM_CHAR_REMAP13m].index_max = -1; 7738 sop->memState[AXP_SM_CHAR_REMAP14m].index_max = -1; 7739 sop->memState[AXP_SM_CHAR_REMAP15m].index_max = -1; 7740 sop->memState[AXP_SM_CHAR_REMAP16m].index_max = -1; 7741 sop->memState[AXP_SM_CHAR_REMAP17m].index_max = -1; 7742 sop->memState[AXP_SM_CHAR_REMAP18m].index_max = -1; 7743 sop->memState[AXP_SM_CHAR_REMAP19m].index_max = -1; 7744 sop->memState[AXP_SM_CHAR_REMAP20m].index_max = -1; 7745 sop->memState[AXP_SM_CHAR_REMAP21m].index_max = -1; 7746 sop->memState[AXP_SM_CHAR_REMAP22m].index_max = -1; 7747 sop->memState[AXP_SM_CHAR_REMAP23m].index_max = -1; 7748 sop->memState[AXP_SM_CHAR_REMAP24m].index_max = -1; 7749 sop->memState[AXP_SM_CHAR_REMAP25m].index_max = -1; 7750 sop->memState[AXP_SM_CHAR_REMAP26m].index_max = -1; 7751 sop->memState[AXP_SM_CHAR_REMAP27m].index_max = -1; 7752 sop->memState[AXP_SM_CHAR_REMAP28m].index_max = -1; 7753 sop->memState[AXP_SM_CHAR_REMAP29m].index_max = -1; 7754 sop->memState[AXP_SM_CHAR_REMAP30m].index_max = -1; 7755 sop->memState[AXP_SM_CHAR_REMAP31m].index_max = -1; 7756 sop->memState[AXP_SM_FLOW_TABLE_BULK_MATCH_DATAm].index_max = -1; 7757 sop->memState[AXP_SM_FLOW_TABLE_BULK_MATCH_MASKm].index_max = -1; 7758 sop->memState[AXP_SM_FLOW_TABLE_BULK_REPLACE_DATAm].index_max = -1; 7759 sop->memState[AXP_SM_FLOW_TABLE_BULK_REPLACE_MASKm].index_max = -1; 7760 sop->memState[AXP_SM_FLOW_TABLE_MEMm].index_max = -1; 7761 sop->memState[AXP_SM_MATCH_COUNTERS_MEM0m].index_max = -1; 7762 sop->memState[AXP_SM_MATCH_COUNTERS_MEM1m].index_max = -1; 7763 sop->memState[AXP_SM_MATCH_COUNTERS_MEM2m].index_max = -1; 7764 sop->memState[AXP_SM_MATCH_COUNTERS_MEM3m].index_max = -1; 7765 sop->memState[AXP_SM_MATCH_TABLE_BULK_MATCH_DATAm].index_max = -1; 7766 sop->memState[AXP_SM_MATCH_TABLE_BULK_MATCH_MASKm].index_max = -1; 7767 sop->memState[AXP_SM_MATCH_TABLE_BULK_REPLACE_DATAm].index_max = -1; 7768 sop->memState[AXP_SM_MATCH_TABLE_BULK_REPLACE_MASKm].index_max = -1; 7769 sop->memState[AXP_SM_MATCH_TABLE_MEM0m].index_max = -1; 7770 sop->memState[AXP_SM_MATCH_TABLE_MEM1m].index_max = -1; 7771 sop->memState[AXP_SM_MATCH_TABLE_MEM2m].index_max = -1; 7772 sop->memState[AXP_SM_MATCH_TABLE_MEM3m].index_max = -1; 7773 sop->memState[AXP_SM_PACKET_BUFFER_MEMm].index_max = -1; 7774 sop->memState[AXP_SM_STATE_TABLE_BULK_MATCH_DATAm].index_max = -1; 7775 sop->memState[AXP_SM_STATE_TABLE_BULK_MATCH_MASKm].index_max = -1; 7776 sop->memState[AXP_SM_STATE_TABLE_BULK_REPLACE_DATAm].index_max = -1; 7777 sop->memState[AXP_SM_STATE_TABLE_BULK_REPLACE_MASKm].index_max = -1; 7778 sop->memState[AXP_SM_STATE_TABLE_MEM0m].index_max = -1; 7779 sop->memState[AXP_SM_STATE_TABLE_MEM1m].index_max = -1; 7780 sop->memState[AXP_SM_STATE_TABLE_MEM2m].index_max = -1; 7781 sop->memState[AXP_SM_STATE_TABLE_MEM3m].index_max = -1; 7782 sop->memState[AXP_SM_STATE_TABLE_MEM4m].index_max = -1; 7783 sop->memState[AXP_SM_STATE_TABLE_MEM5m].index_max = -1; 7784 sop->memState[AXP_SM_STATE_TABLE_MEM6m].index_max = -1; 7785 sop->memState[AXP_SM_STATE_TABLE_MEM7m].index_max = -1; 7786 sop->memState[FT_SESSIONm].index_max = -1; 7787 sop->memState[FT_EXPORT_FIFOm].index_max = -1; 7788 sop->memState[FT_EXPORT_DATA_ONLYm].index_max = -1; 7789 sop->memState[FT_EOP_TBLm].index_max = -1; 7790 sop->memState[FT_AGE_PROFILEm].index_max = -1; 7791 sop->memState[FT_L4PORTm].index_max = -1; 7792 sop->memState[FT_DST_LAG_CONFIGm].index_max = -1; 7793 sop->memState[FT_DST_PORT_CONFIGm].index_max = -1; 7794 sop->memState[FT_POLICYm].index_max = -1; 7795 sop->memState[FT_SESSION_IPV6m].index_max = -1; 7796 sop->memState[FT_EXPORT_CNTR_ONLYm].index_max = -1; 7797 } 7798 break; 7799 7800 case BCM56044_DEVICE_ID: 7801 case BCM56045_DEVICE_ID: 7802 case BCM56046_DEVICE_ID: 7803 /* ISM Raw and ESM */ 7804 sop->memState[EXT_L2_ENTRY_1m].index_max = -1; 7805 sop->memState[EXT_L2_ENTRY_2m].index_max = -1; 7806 /* L3 Next hop */ 7807 sop->memState[INITIAL_ING_L3_NEXT_HOPm].index_max = 1023; 7808 sop->memState[ING_L3_NEXT_HOPm].index_max = 1023; 7809 sop->memState[EGR_L3_NEXT_HOPm].index_max = 1023; 7810 sop->memState[INITIAL_PROT_NHI_TABLEm].index_max = 1023; 7811 7812 sop->memState[ING_L3_NEXT_HOP_ATTRIBUTE_1_INDEXm].index_max = 24575; 7813 /* L3 LPM */ 7814 SOC_CONTROL(unit)->l3_defip_max_tcams = _SOC_TR3_DEFIP_MAX_TCAMS/4; 7815 SOC_CONTROL(unit)->l3_defip_tcam_size = _SOC_TR3_DEFIP_TCAM_DEPTH; 7816 7817 sop->memState[L3_DEFIPm].index_max = 7818 (SOC_CONTROL(unit)->l3_defip_max_tcams * 7819 SOC_CONTROL(unit)->l3_defip_tcam_size) - 1; 7820 sop->memState[L3_DEFIP_ONLYm].index_max = 7821 (SOC_CONTROL(unit)->l3_defip_max_tcams * 7822 SOC_CONTROL(unit)->l3_defip_tcam_size) - 1; 7823 sop->memState[L3_DEFIP_DATA_ONLYm].index_max = 7824 (SOC_CONTROL(unit)->l3_defip_max_tcams * 7825 SOC_CONTROL(unit)->l3_defip_tcam_size) - 1; 7826 sop->memState[L3_DEFIP_HIT_ONLYm].index_max = 7827 (SOC_CONTROL(unit)->l3_defip_max_tcams * 7828 SOC_CONTROL(unit)->l3_defip_tcam_size) - 1; 7829 7830 /* L3 IPMC */ 7831 sop->memState[L3_IPMCm].index_max = 256; 7832 sop->memState[L3_IPMC_1m].index_max = 256; 7833 sop->memState[L3_IPMC_REMAPm].index_max = 256; 7834 sop->memState[MMU_REPL_GROUPm].index_max = 256; 7835 sop->memState[ING_UNTAGGED_PHBm].index_max = 62; 7836 sop->memState[EGR_IPMCm].index_max = 256; 7837 sop->memState[EGR_L3_INTFm].index_max = 512; 7838 7839 /* Counters */ 7840 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_0m].index_max = 255; 7841 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_1m].index_max = 255; 7842 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_2m].index_max = 255; 7843 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_3m].index_max = 255; 7844 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_4m].index_max = 255; 7845 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_5m].index_max = 255; 7846 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_6m].index_max = 255; 7847 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_7m].index_max = 255; 7848 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_8m].index_max = -1; 7849 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_9m].index_max = -1; 7850 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_10m].index_max = -1; 7851 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_11m].index_max = -1; 7852 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_12m].index_max = -1; 7853 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_13m].index_max = -1; 7854 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_14m].index_max = -1; 7855 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_15m].index_max = -1; 7856 sop->memState[ING_FLEX_CTR_OFFSET_TABLE_8m].index_max = -1; 7857 sop->memState[ING_FLEX_CTR_OFFSET_TABLE_9m].index_max = -1; 7858 sop->memState[ING_FLEX_CTR_OFFSET_TABLE_10m].index_max = -1; 7859 sop->memState[ING_FLEX_CTR_OFFSET_TABLE_11m].index_max = -1; 7860 sop->memState[ING_FLEX_CTR_OFFSET_TABLE_12m].index_max = -1; 7861 sop->memState[ING_FLEX_CTR_OFFSET_TABLE_13m].index_max = -1; 7862 sop->memState[ING_FLEX_CTR_OFFSET_TABLE_14m].index_max = -1; 7863 sop->memState[ING_FLEX_CTR_OFFSET_TABLE_15m].index_max = -1; 7864 sop->memState[VLAN_OR_VFI_MAC_COUNTm].index_max = 8191; 7865 sop->memState[VLAN_OR_VFI_MAC_LIMITm].index_max = 8191; 7866 sop->memState[OAM_LM_COUNTERSm].index_max = 8191; 7867 sop->memState[EGR_FLEX_CTR_COUNTER_TABLE_0m].index_max = 63; 7868 sop->memState[EGR_FLEX_CTR_COUNTER_TABLE_1m].index_max = 63; 7869 sop->memState[EGR_FLEX_CTR_COUNTER_TABLE_2m].index_max = 63; 7870 sop->memState[EGR_FLEX_CTR_COUNTER_TABLE_3m].index_max = 63; 7871 sop->memState[EGR_FLEX_CTR_COUNTER_TABLE_4m].index_max = 63; 7872 sop->memState[EGR_FLEX_CTR_COUNTER_TABLE_5m].index_max = 63; 7873 sop->memState[EGR_FLEX_CTR_COUNTER_TABLE_6m].index_max = 63; 7874 sop->memState[EGR_FLEX_CTR_COUNTER_TABLE_7m].index_max = 63; 7875 7876 /* LMEP */ 7877 sop->memState[LMEPm].index_max = -1; 7878 sop->memState[LMEP_DAm].index_max = -1; 7879 /* RMEP */ 7880 sop->memState[RMEPm].index_max = -1; 7881 sop->memState[MAID_REDUCTIONm].index_max = -1; 7882 sop->memState[MA_STATEm].index_max = -1; 7883 sop->memState[ESM_ACL_ACTION_CONTROLm].index_max = -1; 7884 sop->memState[ESM_ACL_PROFILEm].index_max = -1; 7885 7886 /* L3_DEFIP sizing */ 7887 if (soc_property_get(unit, "l3_defip_sizing", TRUE)) { 7888 defip_config = soc_property_get(unit, spn_IPV6_LPM_128B_ENABLE, 0); 7889 7890 num_ipv6_128b_entries = soc_property_get(unit, 7891 spn_NUM_IPV6_LPM_128B_ENTRIES, 7892 (defip_config ? 128 : 0)); 7893 num_ipv6_128b_entries = num_ipv6_128b_entries + 7894 (num_ipv6_128b_entries % 2); 7895 config_v6_entries = num_ipv6_128b_entries; 7896 if (soc_property_get(unit, spn_LPM_SCALING_ENABLE, 0)) { 7897 num_ipv6_128b_entries = 0; 7898 if (!soc_property_get(unit, spn_LPM_IPV6_128B_RESERVED, 1)) { 7899 config_v6_entries = ((config_v6_entries / 7900 SOC_CONTROL(unit)->l3_defip_tcam_size) + 7901 ((config_v6_entries % 7902 SOC_CONTROL(unit)->l3_defip_tcam_size) 7903 ? 1 : 0)) * SOC_CONTROL(unit)->l3_defip_tcam_size; 7904 } 7905 7906 } 7907 7908 sop->memState[L3_DEFIP_PAIR_128m].index_max = 7909 num_ipv6_128b_entries - 1; 7910 sop->memState[L3_DEFIP_PAIR_128_ONLYm].index_max = 7911 num_ipv6_128b_entries - 1; 7912 sop->memState[L3_DEFIP_PAIR_128_DATA_ONLYm].index_max = 7913 num_ipv6_128b_entries - 1; 7914 sop->memState[L3_DEFIP_PAIR_128_HIT_ONLYm].index_max = 7915 num_ipv6_128b_entries - 1; 7916 sop->memState[L3_DEFIPm].index_max = 7917 (SOC_CONTROL(unit)->l3_defip_max_tcams * 7918 SOC_CONTROL(unit)->l3_defip_tcam_size) - 7919 (num_ipv6_128b_entries * 2) - 1; 7920 sop->memState[L3_DEFIP_ONLYm].index_max = 7921 sop->memState[L3_DEFIPm].index_max; 7922 sop->memState[L3_DEFIP_DATA_ONLYm].index_max = 7923 sop->memState[L3_DEFIPm].index_max; 7924 sop->memState[L3_DEFIP_HIT_ONLYm].index_max = 7925 sop->memState[L3_DEFIPm].index_max; 7926 SOC_CONTROL(unit)->l3_defip_index_remap = num_ipv6_128b_entries; 7927 soc_l3_defip_indexes_init(unit, config_v6_entries); 7928 } 7929 7930 7931 /* These memories are not present in Ranger+ */ 7932 sop->memState[AXP_SM_CHAR_REMAP0m].index_max = -1; 7933 sop->memState[AXP_SM_CHAR_REMAP1m].index_max = -1; 7934 sop->memState[AXP_SM_CHAR_REMAP2m].index_max = -1; 7935 sop->memState[AXP_SM_CHAR_REMAP3m].index_max = -1; 7936 sop->memState[AXP_SM_CHAR_REMAP4m].index_max = -1; 7937 sop->memState[AXP_SM_CHAR_REMAP5m].index_max = -1; 7938 sop->memState[AXP_SM_CHAR_REMAP6m].index_max = -1; 7939 sop->memState[AXP_SM_CHAR_REMAP7m].index_max = -1; 7940 sop->memState[AXP_SM_CHAR_REMAP8m].index_max = -1; 7941 sop->memState[AXP_SM_CHAR_REMAP9m].index_max = -1; 7942 sop->memState[AXP_SM_CHAR_REMAP10m].index_max = -1; 7943 sop->memState[AXP_SM_CHAR_REMAP11m].index_max = -1; 7944 sop->memState[AXP_SM_CHAR_REMAP12m].index_max = -1; 7945 sop->memState[AXP_SM_CHAR_REMAP13m].index_max = -1; 7946 sop->memState[AXP_SM_CHAR_REMAP14m].index_max = -1; 7947 sop->memState[AXP_SM_CHAR_REMAP15m].index_max = -1; 7948 sop->memState[AXP_SM_CHAR_REMAP16m].index_max = -1; 7949 sop->memState[AXP_SM_CHAR_REMAP17m].index_max = -1; 7950 sop->memState[AXP_SM_CHAR_REMAP18m].index_max = -1; 7951 sop->memState[AXP_SM_CHAR_REMAP19m].index_max = -1; 7952 sop->memState[AXP_SM_CHAR_REMAP20m].index_max = -1; 7953 sop->memState[AXP_SM_CHAR_REMAP21m].index_max = -1; 7954 sop->memState[AXP_SM_CHAR_REMAP22m].index_max = -1; 7955 sop->memState[AXP_SM_CHAR_REMAP23m].index_max = -1; 7956 sop->memState[AXP_SM_CHAR_REMAP24m].index_max = -1; 7957 sop->memState[AXP_SM_CHAR_REMAP25m].index_max = -1; 7958 sop->memState[AXP_SM_CHAR_REMAP26m].index_max = -1; 7959 sop->memState[AXP_SM_CHAR_REMAP27m].index_max = -1; 7960 sop->memState[AXP_SM_CHAR_REMAP28m].index_max = -1; 7961 sop->memState[AXP_SM_CHAR_REMAP29m].index_max = -1; 7962 sop->memState[AXP_SM_CHAR_REMAP30m].index_max = -1; 7963 sop->memState[AXP_SM_CHAR_REMAP31m].index_max = -1; 7964 sop->memState[AXP_SM_FLOW_TABLE_BULK_MATCH_DATAm].index_max = -1; 7965 sop->memState[AXP_SM_FLOW_TABLE_BULK_MATCH_MASKm].index_max = -1; 7966 sop->memState[AXP_SM_FLOW_TABLE_BULK_REPLACE_DATAm].index_max = -1; 7967 sop->memState[AXP_SM_FLOW_TABLE_BULK_REPLACE_MASKm].index_max = -1; 7968 sop->memState[AXP_SM_FLOW_TABLE_MEMm].index_max = -1; 7969 sop->memState[AXP_SM_MATCH_COUNTERS_MEM0m].index_max = -1; 7970 sop->memState[AXP_SM_MATCH_COUNTERS_MEM1m].index_max = -1; 7971 sop->memState[AXP_SM_MATCH_COUNTERS_MEM2m].index_max = -1; 7972 sop->memState[AXP_SM_MATCH_COUNTERS_MEM3m].index_max = -1; 7973 sop->memState[AXP_SM_MATCH_TABLE_BULK_MATCH_DATAm].index_max = -1; 7974 sop->memState[AXP_SM_MATCH_TABLE_BULK_MATCH_MASKm].index_max = -1; 7975 sop->memState[AXP_SM_MATCH_TABLE_BULK_REPLACE_DATAm].index_max = -1; 7976 sop->memState[AXP_SM_MATCH_TABLE_BULK_REPLACE_MASKm].index_max = -1; 7977 sop->memState[AXP_SM_MATCH_TABLE_MEM0m].index_max = -1; 7978 sop->memState[AXP_SM_MATCH_TABLE_MEM1m].index_max = -1; 7979 sop->memState[AXP_SM_MATCH_TABLE_MEM2m].index_max = -1; 7980 sop->memState[AXP_SM_MATCH_TABLE_MEM3m].index_max = -1; 7981 sop->memState[AXP_SM_PACKET_BUFFER_MEMm].index_max = -1; 7982 sop->memState[AXP_SM_STATE_TABLE_BULK_MATCH_DATAm].index_max = -1; 7983 sop->memState[AXP_SM_STATE_TABLE_BULK_MATCH_MASKm].index_max = -1; 7984 sop->memState[AXP_SM_STATE_TABLE_BULK_REPLACE_DATAm].index_max = -1; 7985 sop->memState[AXP_SM_STATE_TABLE_BULK_REPLACE_MASKm].index_max = -1; 7986 sop->memState[AXP_SM_STATE_TABLE_MEM0m].index_max = -1; 7987 sop->memState[AXP_SM_STATE_TABLE_MEM1m].index_max = -1; 7988 sop->memState[AXP_SM_STATE_TABLE_MEM2m].index_max = -1; 7989 sop->memState[AXP_SM_STATE_TABLE_MEM3m].index_max = -1; 7990 sop->memState[AXP_SM_STATE_TABLE_MEM4m].index_max = -1; 7991 sop->memState[AXP_SM_STATE_TABLE_MEM5m].index_max = -1; 7992 sop->memState[AXP_SM_STATE_TABLE_MEM6m].index_max = -1; 7993 sop->memState[AXP_SM_STATE_TABLE_MEM7m].index_max = -1; 7994 7995 sop->memState[AXP_WLAN_COS_MAPm].index_max = -1; 7996 sop->memState[AXP_WRX_SVP_ASSIGNMENTm].index_max = -1; 7997 sop->memState[AXP_WRX_WCDm].index_max = -1; 7998 sop->memState[AXP_WRX_SVP_ASSIGNMENTm].index_max = -1; 7999 sop->memState[AXP_WRX_WCDm].index_max = -1; 8000 sop->memState[AXP_WTX_DSCP_MAPm].index_max = -1; 8001 sop->memState[AXP_WTX_DVP_PROFILEm].index_max = -1; 8002 sop->memState[AXP_WTX_FRAG_IDm].index_max = -1; 8003 sop->memState[AXP_WTX_PRI_MAPm].index_max = -1; 8004 sop->memState[AXP_WTX_TRUNK_BLOCK_MASKm].index_max = -1; 8005 sop->memState[AXP_WTX_TRUNK_GROUP_BITMAPm].index_max = -1; 8006 sop->memState[AXP_WTX_TUNNELm].index_max = -1; 8007 sop->memState[VRFm].index_max = -1; 8008 sop->memState[SVM_METER_TABLEm].index_max = -1; 8009 sop->memState[SVM_OFFSET_TABLEm].index_max = -1; 8010 sop->memState[SVM_POLICY_TABLEm].index_max = -1; 8011 break; 8012 case BCM56640_DEVICE_ID: 8013 SOC_CONTROL(unit)->l3_defip_max_tcams = _SOC_TR3_DEFIP_MAX_TCAMS; 8014 SOC_CONTROL(unit)->l3_defip_tcam_size = _SOC_TR3_DEFIP_TCAM_DEPTH; 8015 if (soc_property_get(unit, "l3_defip_sizing", TRUE)) { 8016 defip_config = soc_property_get(unit, spn_IPV6_LPM_128B_ENABLE, 1); 8017 8018 num_ipv6_128b_entries = soc_property_get(unit, 8019 spn_NUM_IPV6_LPM_128B_ENTRIES, 8020 (defip_config ? 2048 : 0)); 8021 num_ipv6_128b_entries = num_ipv6_128b_entries + 8022 (num_ipv6_128b_entries % 2); 8023 config_v6_entries = num_ipv6_128b_entries; 8024 if (soc_property_get(unit, spn_LPM_SCALING_ENABLE, 0)) { 8025 num_ipv6_128b_entries = 0; 8026 if (!soc_property_get(unit, spn_LPM_IPV6_128B_RESERVED, 1)) { 8027 config_v6_entries = ((config_v6_entries / 8028 SOC_CONTROL(unit)->l3_defip_tcam_size) + 8029 ((config_v6_entries % 8030 SOC_CONTROL(unit)->l3_defip_tcam_size) 8031 ? 1 : 0)) * SOC_CONTROL(unit)->l3_defip_tcam_size; 8032 } 8033 8034 } 8035 ism_defip_pair_128_size = config_v6_entries; 8036 ism_defip_size = (SOC_CONTROL(unit)->l3_defip_max_tcams * 8037 SOC_CONTROL(unit)->l3_defip_tcam_size) - 8038 (num_ipv6_128b_entries * 2); 8039 8040 SOC_IF_ERROR_RETURN(_soc_tr3_set_defip_table_size(unit, 8041 L3_DEFIP_PAIR_128m, ism_defip_pair_128_size - 1)); 8042 SOC_IF_ERROR_RETURN(_soc_tr3_set_defip_table_size(unit, 8043 L3_DEFIPm, ism_defip_size - 1)); 8044 8045 if (SOC_MEM_IS_ENABLED(unit, EXT_IPV6_128_DEFIPm) && 8046 soc_mem_index_count(unit, EXT_IPV6_128_DEFIPm)) { 8047 /* set size L3_DEFIP_PAIR_128m to 0 */ 8048 ism_defip_pair_128_size = 0; 8049 num_ipv6_128b_entries = 0; 8050 } 8051 8052 if (SOC_MEM_IS_ENABLED(unit, EXT_IPV4_DEFIPm) && 8053 soc_mem_index_count(unit, EXT_IPV4_DEFIPm) && 8054 SOC_MEM_IS_ENABLED(unit, EXT_IPV6_64_DEFIPm) && 8055 soc_mem_index_count(unit, EXT_IPV6_64_DEFIPm)) { 8056 /* set size of L3_DEFIPm to 0 */ 8057 ism_defip_size = 0; 8058 } 8059 8060 SOC_CONTROL(unit)->l3_defip_index_remap = ism_defip_pair_128_size; 8061 8062 if (ism_defip_size == 0) { 8063 SOC_IF_ERROR_RETURN(_soc_tr3_set_defip_table_size(unit, 8064 L3_DEFIPm, -1)); 8065 } else { 8066 if (ism_defip_pair_128_size == 0) { 8067 ism_defip_max_index = (SOC_CONTROL(unit)->l3_defip_max_tcams * 8068 SOC_CONTROL(unit)->l3_defip_tcam_size) - 1; 8069 SOC_IF_ERROR_RETURN(_soc_tr3_set_defip_table_size(unit, 8070 L3_DEFIPm, ism_defip_max_index)); 8071 soc_l3_defip_indexes_init(unit, 0); 8072 } 8073 } 8074 if (ism_defip_pair_128_size == 0) { 8075 SOC_IF_ERROR_RETURN(_soc_tr3_set_defip_table_size(unit, 8076 L3_DEFIP_PAIR_128m, -1)); 8077 } else { 8078 if (ism_defip_size == 0) { 8079 ism_defip_max_index = ((SOC_CONTROL(unit)->l3_defip_max_tcams * 8080 SOC_CONTROL(unit)->l3_defip_tcam_size) >> 1) - 1; 8081 SOC_IF_ERROR_RETURN(_soc_tr3_set_defip_table_size(unit, 8082 L3_DEFIP_PAIR_128m, ism_defip_max_index)); 8083 8084 SOC_CONTROL(unit)->l3_defip_index_remap = ism_defip_max_index + 1; 8085 soc_l3_defip_indexes_init(unit, ism_defip_max_index + 1); 8086 } 8087 } 8088 if (ism_defip_size == 0 && ism_defip_pair_128_size == 0) { 8089 soc_l3_defip_indexes_init(unit, 0); 8090 } 8091 if (ism_defip_size != 0 && ism_defip_pair_128_size != 0) { 8092 soc_l3_defip_indexes_init(unit, config_v6_entries); 8093 } 8094 } 8095 break; 8096 case BCM56648_DEVICE_ID: 8097 case BCM56649_DEVICE_ID: 8098 /* L3 IPMC */ 8099 sop->memState[L3_IPMCm].index_max = 8191; 8100 sop->memState[L3_IPMC_1m].index_max = 8191; 8101 sop->memState[L3_IPMC_REMAPm].index_max = 8191; 8102 sop->memState[MMU_REPL_GROUPm].index_max = 8191; 8103 sop->memState[ING_UNTAGGED_PHBm].index_max = 62; 8104 if (rev_id & 0xF0) { /* B0 onwards size changed */ 8105 sop->memState[EGR_IPMCm].index_max = 8191; 8106 } 8107 /* Fall through for L3_DEFIP config */ 8108 default: 8109 /* L3_DEFIP sizing */ 8110 SOC_CONTROL(unit)->l3_defip_max_tcams = _SOC_TR3_DEFIP_MAX_TCAMS; 8111 SOC_CONTROL(unit)->l3_defip_tcam_size = _SOC_TR3_DEFIP_TCAM_DEPTH; 8112 if (soc_property_get(unit, "l3_defip_sizing", TRUE)) { 8113 defip_config = soc_property_get(unit, spn_IPV6_LPM_128B_ENABLE, 1); 8114 8115 num_ipv6_128b_entries = soc_property_get(unit, 8116 spn_NUM_IPV6_LPM_128B_ENTRIES, 8117 (defip_config ? 2048 : 0)); 8118 num_ipv6_128b_entries = num_ipv6_128b_entries + 8119 (num_ipv6_128b_entries % 2); 8120 config_v6_entries = num_ipv6_128b_entries; 8121 if (soc_property_get(unit, spn_LPM_SCALING_ENABLE, 0)) { 8122 num_ipv6_128b_entries = 0; 8123 if (!soc_property_get(unit, spn_LPM_IPV6_128B_RESERVED, 1)) { 8124 config_v6_entries = ((config_v6_entries / 8125 SOC_CONTROL(unit)->l3_defip_tcam_size) + 8126 ((config_v6_entries % 8127 SOC_CONTROL(unit)->l3_defip_tcam_size) 8128 ? 1 : 0)) * SOC_CONTROL(unit)->l3_defip_tcam_size; 8129 } 8130 8131 } 8132 8133 sop->memState[L3_DEFIP_PAIR_128m].index_max = 8134 num_ipv6_128b_entries - 1; 8135 sop->memState[L3_DEFIP_PAIR_128_ONLYm].index_max = 8136 num_ipv6_128b_entries - 1; 8137 sop->memState[L3_DEFIP_PAIR_128_DATA_ONLYm].index_max = 8138 num_ipv6_128b_entries - 1; 8139 sop->memState[L3_DEFIP_PAIR_128_HIT_ONLYm].index_max = 8140 num_ipv6_128b_entries - 1; 8141 sop->memState[L3_DEFIPm].index_max = 8142 (SOC_CONTROL(unit)->l3_defip_max_tcams * 8143 SOC_CONTROL(unit)->l3_defip_tcam_size) - 8144 (num_ipv6_128b_entries * 2) - 1; 8145 sop->memState[L3_DEFIP_ONLYm].index_max = 8146 sop->memState[L3_DEFIPm].index_max; 8147 sop->memState[L3_DEFIP_DATA_ONLYm].index_max = 8148 sop->memState[L3_DEFIPm].index_max; 8149 sop->memState[L3_DEFIP_HIT_ONLYm].index_max = 8150 sop->memState[L3_DEFIPm].index_max; 8151 SOC_CONTROL(unit)->l3_defip_index_remap = num_ipv6_128b_entries; 8152 soc_l3_defip_indexes_init(unit, config_v6_entries); 8153 } 8154 break; 8155 } 8156 sop->memState[ING_UNTAGGED_PHBm].index_max = 62; 8157 if (!(rev_id & 0xF0)) { /* This mem is only available B0 onwards */ 8158 sop->memState[L2_LEARN_INSERT_FAILUREm].index_max = -1; 8159 } 8160 8161 /* MMU buffer size config */ 8162 switch (dev_id) { 8163 case BCM56640_DEVICE_ID: 8164 case BCM56643_DEVICE_ID: 8165 case BCM56644_DEVICE_ID: 8166 case BCM56648_DEVICE_ID: 8167 case BCM56649_DEVICE_ID: 8168 case BCM56044_DEVICE_ID: 8169 _soc_tr3_mmu_buffer_cells[unit] = _TR3_MMU_TOTAL_CELLS_24K; 8170 break; 8171 case BCM56540_DEVICE_ID: 8172 case BCM56541_DEVICE_ID: 8173 case BCM56542_DEVICE_ID: 8174 case BCM56543_DEVICE_ID: 8175 case BCM56544_DEVICE_ID: 8176 case BCM56545_DEVICE_ID: 8177 case BCM56546_DEVICE_ID: 8178 case BCM56045_DEVICE_ID: 8179 case BCM56046_DEVICE_ID: 8180 _soc_tr3_mmu_buffer_cells[unit] = _TR3_MMU_TOTAL_CELLS_19K; 8181 break; 8182 default: 8183 _soc_tr3_mmu_buffer_cells[unit] = _TR3_MMU_TOTAL_CELLS_19K; 8184 break; 8185 } 8186 8187 #ifdef BCM_ISM_SUPPORT 8188 switch (dev_id) { 8189 case BCM56648_DEVICE_ID: 8190 case BCM56649_DEVICE_ID: 8191 case BCM56540_DEVICE_ID: 8192 case BCM56541_DEVICE_ID: 8193 case BCM56542_DEVICE_ID: 8194 case BCM56543_DEVICE_ID: 8195 case BCM56544_DEVICE_ID: 8196 case BCM56545_DEVICE_ID: 8197 case BCM56546_DEVICE_ID: scale = 3; 8198 break; 8199 case BCM56044_DEVICE_ID: 8200 case BCM56045_DEVICE_ID: 8201 case BCM56046_DEVICE_ID: scale = 8; 8202 break; 8203 default: break; 8204 } 8205 8206 if (soc_feature(unit, soc_feature_ism_memory)) { 8207 soc_ism_mem_size_config_t ism_alloc_size[_ISM_MAX_MEMS]; 8208 sal_memcpy(ism_alloc_size, _ism_alloc_size, sizeof(ism_alloc_size)); 8209 ism_alloc_size[0].size = 8210 soc_property_get(unit, spn_VLAN_XLATE_MEM_ENTRIES, 8211 ism_alloc_size[0].size/scale); 8212 ism_alloc_size[1].size = 8213 soc_property_get(unit, spn_L2_MEM_ENTRIES, 8214 ism_alloc_size[1].size/scale); 8215 ism_alloc_size[2].size = 8216 soc_property_get(unit, spn_L3_MEM_ENTRIES, 8217 ism_alloc_size[2].size/scale); 8218 ism_alloc_size[3].size = 8219 soc_property_get(unit, spn_EGR_VLAN_XLATE_MEM_ENTRIES, 8220 ism_alloc_size[3].size/scale); 8221 ism_alloc_size[4].size = 8222 soc_property_get(unit, spn_MPLS_MEM_ENTRIES, 8223 ism_alloc_size[4].size/scale); 8224 if (soc_feature(unit, soc_feature_esm_support)) { 8225 rv = soc_tr3_esm_init_read_config(unit); 8226 (void)soc_tr3_esm_get_ism_mem_size(unit, SOC_ISM_MEM_ESM_L2, 8227 &ism_alloc_size[5].size); 8228 (void)soc_tr3_esm_get_ism_mem_size(unit, SOC_ISM_MEM_ESM_L3, 8229 &ism_alloc_size[6].size); 8230 (void)soc_tr3_esm_get_ism_mem_size(unit, SOC_ISM_MEM_ESM_ACL, 8231 &ism_alloc_size[7].size); 8232 if (NULL == SOC_CONTROL(unit)->tcam_info) { 8233 sop->memState[ESM_PKT_TYPE_IDm].index_max = -1; 8234 sop->memState[ESM_PKT_TYPE_ID_ONLYm].index_max = -1; 8235 sop->memState[ESM_PKT_TYPE_ID_DATA_ONLYm].index_max = -1; 8236 sop->memState[ESM_SEARCH_PROFILEm].index_max = -1; 8237 sop->memState[ESM_KEY_ID_TO_FIELD_MAPPERm].index_max = -1; 8238 sop->memState[ESM_RANGE_CHECKm].index_max = -1; 8239 sop->memState[ESM_L3_PROTOCOL_FNm].index_max = -1; 8240 sop->memState[ESM_HWTL_OBSERVED_ET_RSPm].index_max = -1; 8241 sop->memState[ESM_ACL_ACTION_CONTROLm].index_max = -1; 8242 sop->memState[ESM_ACL_PROFILEm].index_max = -1; 8243 } 8244 } 8245 if (ism_alloc_size[1].size <= 0 && ism_alloc_size[5].size <= 0) { 8246 LOG_ERROR(BSL_LS_SOC_COMMON, 8247 (BSL_META_U(unit, 8248 "No L2 memory configured !!\n"))); 8249 return SOC_E_RESOURCE; 8250 } 8251 ism_alloc_size[0].banks = 8252 soc_property_get(unit, spn_VLAN_XLATE_MEM_BANKS, 8253 ism_alloc_size[0].banks); 8254 ism_alloc_size[1].banks = 8255 soc_property_get(unit, spn_L2_MEM_BANKS, 8256 ism_alloc_size[1].banks); 8257 ism_alloc_size[2].banks = 8258 soc_property_get(unit, spn_L3_MEM_BANKS, 8259 ism_alloc_size[2].banks); 8260 ism_alloc_size[3].banks = 8261 soc_property_get(unit, spn_EGR_VLAN_XLATE_MEM_BANKS, 8262 ism_alloc_size[3].banks); 8263 ism_alloc_size[4].banks = 8264 soc_property_get(unit, spn_MPLS_MEM_BANKS, 8265 ism_alloc_size[4].banks); 8266 rv = soc_ism_mem_config(unit, ism_alloc_size, COUNTOF(ism_alloc_size)); 8267 if (SOC_FAILURE(rv)) { 8268 LOG_ERROR(BSL_LS_SOC_COMMON, 8269 (BSL_META_U(unit, 8270 "Invalid or unsupported ISM memory config !!\n"))); 8271 return rv; 8272 } 8273 } 8274 #endif 8275 return rv; 8276 } 8277 8278 #define _TR3_INDEX_1K_ENTRIES 1023 8279 #define _TR3_INDEX_2K_ENTRIES 2047 8280 #define _TR3_OFFSET_2K_ENTRIES 2048 8281 #define _TR3_OFFSET_3K_ENTRIES 3072 8282 #define _TR3_INDEX_4K_ENTRIES 4095 8283 #define _TR3_INDEX_6K_ENTRIES 6143 8284 #define _TR3_OFFSET_6K_ENTRIES 6144 8285 8286 /* Map logical (always starts from 0 and contiguous) index to physical index 8287 which can have a starting offset and/or holes. 8288 Input : logical index 8289 Returns: physical index */ 8290 int 8291 soc_tr3_l3_defip_index_map(int unit, soc_mem_t mem, int index) 8292 { 8293 int wide = 0; 8294 8295 if (SOC_CONTROL(unit)->l3_defip_index_remap == 0) { 8296 return index; 8297 } 8298 8299 if (mem == L3_DEFIP_PAIR_128m || 8300 mem == L3_DEFIP_PAIR_128_ONLYm || 8301 mem == L3_DEFIP_PAIR_128_DATA_ONLYm || 8302 mem == L3_DEFIP_PAIR_128_HIT_ONLYm) { 8303 wide = 1; 8304 } 8305 8306 if (SOC_CONTROL(unit)->tcam_protect_write_init && SOC_IS_HELIX4(unit)) { 8307 int incr = 0, hole = 0, phy_index; 8308 int defip128_tbl_sz = SOC_CONTROL(unit)->l3_defip_index_remap; 8309 8310 incr = soc_mem_index_count(unit, mem) / 8311 (SOC_L3_DEFIP_MAX_TCAMS_GET(unit) >> wide); 8312 hole = index / incr; 8313 if (defip128_tbl_sz == 0) { 8314 phy_index = index; 8315 } else { 8316 phy_index = soc_l3_defip_urpf_index_map(unit, wide, index); 8317 8318 } 8319 if (SOC_CONTROL(unit)->tcam_protect_write) { 8320 if (defip128_tbl_sz == 0) { 8321 phy_index += hole; 8322 } else { 8323 if (wide && soc_mem_index_count(unit, L3_DEFIPm)) { 8324 hole = hole * 2; 8325 } else if (!wide && soc_mem_index_count(unit, L3_DEFIP_PAIR_128m)) { 8326 hole = hole + (hole / 2 * 2) + (hole % 2) + 1; 8327 } 8328 phy_index += hole; 8329 } 8330 } 8331 8332 return phy_index; 8333 } 8334 8335 if (SOC_CONTROL(unit)->l3_defip_urpf) { 8336 if (soc_feature(unit, soc_feature_l3_reduced_defip_table)) { 8337 return soc_l3_defip_urpf_index_map(unit, wide, index); 8338 } else if (!(soc_feature(unit, soc_feature_esm_support) && 8339 SOC_MEM_IS_ENABLED(unit, EXT_IPV4_DEFIPm) && 8340 soc_mem_index_count(unit, EXT_IPV4_DEFIPm) && 8341 SOC_MEM_IS_ENABLED(unit, EXT_IPV6_64_DEFIPm) && 8342 soc_mem_index_count(unit, EXT_IPV6_64_DEFIPm))) { 8343 /* TR3 no ESM */ 8344 if (!soc_feature(unit, soc_feature_l3_256_defip_table)) { 8345 return soc_l3_defip_urpf_index_map(unit, wide, index); 8346 } 8347 8348 if (wide == 0) { 8349 if (index > _TR3_INDEX_2K_ENTRIES) { 8350 return index + SOC_CONTROL(unit)->l3_defip_index_remap; 8351 } 8352 return index + SOC_CONTROL(unit)->l3_defip_index_remap / 2; 8353 } else { 8354 if (index > _TR3_INDEX_1K_ENTRIES) { 8355 return index + SOC_CONTROL(unit)->l3_defip_index_remap / 4; 8356 } 8357 return index; 8358 } 8359 } 8360 } else { /* urpf not enabled */ 8361 if (!(soc_feature(unit, soc_feature_esm_support) && 8362 SOC_MEM_IS_ENABLED(unit, EXT_IPV4_DEFIPm) && 8363 soc_mem_index_count(unit, EXT_IPV4_DEFIPm) && 8364 SOC_MEM_IS_ENABLED(unit, EXT_IPV6_64_DEFIPm) && 8365 soc_mem_index_count(unit, EXT_IPV6_64_DEFIPm))) { 8366 /* TR3 no ESM */ 8367 if (!soc_feature(unit, soc_feature_l3_reduced_defip_table) && 8368 !soc_feature(unit, soc_feature_l3_256_defip_table)) { 8369 return soc_l3_defip_index_map(unit, wide, index); 8370 } 8371 } 8372 8373 if (soc_feature(unit, soc_feature_l3_reduced_defip_table)) { 8374 /* AP2, FB4 */ 8375 return soc_l3_defip_index_map(unit, wide, index); 8376 } 8377 } 8378 8379 /* Ranger, Ranger+ dont support uRPF */ 8380 return (wide) ? index : index + SOC_CONTROL(unit)->l3_defip_index_remap; 8381 } 8382 8383 /* Reverse map physical index to logical index. 8384 Input : physical index 8385 Returns: logical index */ 8386 int 8387 soc_tr3_l3_defip_index_remap(int unit, soc_mem_t mem, int index) 8388 { 8389 int wide = 0; 8390 8391 if (SOC_CONTROL(unit)->l3_defip_index_remap == 0) { 8392 return index; 8393 } 8394 8395 if (mem == L3_DEFIP_PAIR_128m || 8396 mem == L3_DEFIP_PAIR_128_ONLYm || 8397 mem == L3_DEFIP_PAIR_128_DATA_ONLYm || 8398 mem == L3_DEFIP_PAIR_128_HIT_ONLYm) { 8399 wide = 1; 8400 } 8401 8402 if (SOC_CONTROL(unit)->tcam_protect_write_init && SOC_IS_HELIX4(unit)) { 8403 int tcam_size = SOC_L3_DEFIP_TCAM_DEPTH_GET(unit); 8404 int hole = 0, log_index; 8405 int defip128_tbl_sz = SOC_CONTROL(unit)->l3_defip_index_remap; 8406 8407 if (soc_mem_index_count(unit, L3_DEFIP_PAIR_128m)) { 8408 tcam_size++; 8409 defip128_tbl_sz += 4; 8410 } 8411 if (soc_mem_index_count(unit, L3_DEFIPm)) { 8412 tcam_size++; 8413 } 8414 8415 if (SOC_CONTROL(unit)->tcam_protect_write) { 8416 if (defip128_tbl_sz == 0) { 8417 hole = index / tcam_size; 8418 index -= hole; 8419 } else { 8420 hole = index / tcam_size; 8421 if (wide && soc_mem_index_count(unit, L3_DEFIPm)) { 8422 hole = hole * 2; 8423 } else if (!wide && soc_mem_index_count(unit, L3_DEFIP_PAIR_128m)) { 8424 hole = hole + (hole / 2 * 2) + (hole % 2) + 1; 8425 } 8426 index -= hole; 8427 } 8428 } 8429 if (defip128_tbl_sz == 0) { 8430 log_index = index; 8431 } else { 8432 log_index = soc_l3_defip_urpf_index_remap(unit, wide, index); 8433 } 8434 8435 return log_index; 8436 } 8437 8438 if (SOC_CONTROL(unit)->l3_defip_urpf) { 8439 if (soc_feature(unit, soc_feature_l3_reduced_defip_table)) { 8440 /* AP2, FB4 */ 8441 if (wide == 0) { 8442 return index - (SOC_CONTROL(unit)->l3_defip_index_remap); 8443 } else if (wide == 1 && index > _TR3_INDEX_1K_ENTRIES) { 8444 return index - (SOC_CONTROL(unit)->l3_defip_index_remap / 2); 8445 } 8446 return index; 8447 } else if (!(soc_feature(unit, soc_feature_esm_support) && 8448 SOC_MEM_IS_ENABLED(unit, EXT_IPV4_DEFIPm) && 8449 soc_mem_index_count(unit, EXT_IPV4_DEFIPm))) { 8450 /* TR3 no ESM */ 8451 if (!soc_feature(unit, soc_feature_l3_256_defip_table)) { 8452 return soc_l3_defip_urpf_index_remap(unit, wide, index); 8453 } 8454 8455 if (wide == 0) { 8456 if (index > _TR3_INDEX_6K_ENTRIES) { 8457 return index - SOC_CONTROL(unit)->l3_defip_index_remap; 8458 } 8459 return index - SOC_CONTROL(unit)->l3_defip_index_remap / 2; 8460 } else { 8461 if (index > _TR3_INDEX_1K_ENTRIES) { 8462 return index - SOC_CONTROL(unit)->l3_defip_index_remap / 4; 8463 } 8464 return index; 8465 } 8466 } 8467 } else { /* urpf not enabled */ 8468 if (!(soc_feature(unit, soc_feature_esm_support) && 8469 SOC_MEM_IS_ENABLED(unit, EXT_IPV4_DEFIPm) && 8470 soc_mem_index_count(unit, EXT_IPV4_DEFIPm))) { 8471 /* TR3 no ESM */ 8472 8473 if (!soc_feature(unit, soc_feature_l3_reduced_defip_table) && 8474 !soc_feature(unit, soc_feature_l3_256_defip_table)) { 8475 return soc_l3_defip_index_remap(unit, wide, index); 8476 } 8477 } 8478 8479 if (soc_feature(unit, soc_feature_l3_reduced_defip_table)) { 8480 /* AP2, FB4 */ 8481 return (wide) ? index : index - 8482 (SOC_CONTROL(unit)->l3_defip_index_remap * 2); 8483 } 8484 } 8485 8486 /* Ranger, Ranger+ dont support uRPF */ 8487 return (wide) ? index : index - SOC_CONTROL(unit)->l3_defip_index_remap; 8488 } 8489 8490 /* Given a physical index (always in terms of the narrow entry) 8491 return the logical index and memory type */ 8492 int 8493 soc_tr3_l3_defip_mem_index_get(int unit, int pindex, soc_mem_t *mem) 8494 { 8495 int cam_size = 1024; 8496 8497 *mem = L3_DEFIPm; 8498 8499 if (!(soc_feature(unit, soc_feature_esm_support) && 8500 SOC_MEM_IS_ENABLED(unit, EXT_IPV4_DEFIPm) && 8501 soc_mem_index_count(unit, EXT_IPV4_DEFIPm))) { 8502 /* TR3 no ESM */ 8503 8504 if (!soc_feature(unit, soc_feature_l3_reduced_defip_table) && 8505 !soc_feature(unit, soc_feature_l3_256_defip_table)) { 8506 return soc_l3_defip_index_mem_map(unit, pindex, mem); 8507 } 8508 } 8509 8510 if (SOC_CONTROL(unit)->l3_defip_urpf) { 8511 if (soc_feature(unit, soc_feature_l3_reduced_defip_table)) { 8512 /* AP2, FB4 */ 8513 if (SOC_CONTROL(unit)->l3_defip_index_remap == 0) { 8514 *mem = L3_DEFIPm; 8515 return pindex; 8516 } 8517 if (pindex < _TR3_OFFSET_2K_ENTRIES || pindex > _TR3_INDEX_4K_ENTRIES) { 8518 *mem = L3_DEFIP_PAIR_128m; 8519 pindex = ((pindex / (cam_size * 2)) * cam_size) + 8520 (pindex % cam_size); 8521 } 8522 } else if (!(soc_feature(unit, soc_feature_esm_support) && 8523 SOC_MEM_IS_ENABLED(unit, EXT_IPV4_DEFIPm) && 8524 soc_mem_index_count(unit, EXT_IPV4_DEFIPm))) { 8525 /* TR3 no ESM */ 8526 if (pindex < _TR3_OFFSET_2K_ENTRIES || 8527 ((pindex > _TR3_INDEX_4K_ENTRIES) && 8528 (pindex < _TR3_OFFSET_6K_ENTRIES))) { 8529 *mem = L3_DEFIP_PAIR_128m; 8530 pindex = pindex/2; 8531 } 8532 } 8533 } else { 8534 if (soc_feature(unit, soc_feature_l3_reduced_defip_table)) { /* AP2 */ 8535 if (SOC_CONTROL(unit)->l3_defip_index_remap == 0) { 8536 *mem = L3_DEFIPm; 8537 return pindex; 8538 } 8539 if (pindex < (SOC_CONTROL(unit)->l3_defip_index_remap * 2)) { 8540 *mem = L3_DEFIP_PAIR_128m; 8541 pindex = ((pindex / (cam_size * 2)) * cam_size) + 8542 (pindex % cam_size); 8543 } 8544 } else if (pindex < SOC_CONTROL(unit)->l3_defip_index_remap) { 8545 *mem = L3_DEFIP_PAIR_128m; 8546 pindex = pindex/2; 8547 } 8548 } 8549 return soc_tr3_l3_defip_index_remap(unit, *mem, pindex); 8550 } 8551 8552 int 8553 _soc_tr3_port_mem_blk_enabled(int unit, int blk) 8554 { 8555 int block_has_ports = FALSE, port, phy, lane, high_speed_port; 8556 soc_info_t *si = &SOC_INFO(unit); 8557 8558 switch (SOC_BLOCK_TYPE(unit, blk)) { 8559 case SOC_BLK_XLPORT: 8560 #ifdef BCM_HELIX4_SUPPORT 8561 case SOC_BLK_XWPORT: 8562 #endif 8563 /* Only one PHY per XLPORT/XWPORT */ 8564 for (lane = 0; lane < _SOC_TR3_LANES_PER_PHY; lane++) { 8565 port = si->port_p2l_mapping[si->blk_fpp[blk] + lane]; 8566 if (SOC_PORT_VALID(unit, port)) { 8567 block_has_ports = TRUE; 8568 break; 8569 } 8570 } 8571 if (block_has_ports) { 8572 return TRUE; 8573 } 8574 break; 8575 case SOC_BLK_XTPORT: 8576 for (phy = 0; phy < _SOC_TR3_PHY_PER_PORT_BLOCK; phy++) { 8577 for (lane = 0; lane < _SOC_TR3_LANES_PER_PHY; lane++) { 8578 port = si->port_p2l_mapping[si->blk_fpp[blk] + 8579 ((phy * _SOC_TR3_LANES_PER_PHY) + lane)]; 8580 if (SOC_PORT_VALID(unit, port)) { 8581 block_has_ports |= 1 << phy; 8582 break; /* Only need to reset PHY once */ 8583 } 8584 } 8585 } 8586 if (block_has_ports) { 8587 return TRUE; 8588 } 8589 break; 8590 case SOC_BLK_CLPORT: 8591 high_speed_port = -1; 8592 for (phy = 0; phy < _SOC_TR3_PHY_PER_PORT_BLOCK; phy++) { 8593 for (lane = 0; lane < _SOC_TR3_LANES_PER_PHY; lane++) { 8594 port = si->port_p2l_mapping[si->blk_fpp[blk] + 8595 ((phy * _SOC_TR3_LANES_PER_PHY) + lane)]; 8596 if (SOC_PORT_VALID(unit, port) && 8597 si->port_speed_max[port] >= 100000) { 8598 high_speed_port = port; 8599 } else if (high_speed_port >= 0) { 8600 port = high_speed_port; 8601 } 8602 if (SOC_PORT_VALID(unit, port)) { 8603 block_has_ports |= 1 << phy; 8604 } 8605 } 8606 } 8607 if (block_has_ports) { 8608 return TRUE; 8609 } 8610 break; 8611 default: break; 8612 } 8613 return FALSE; 8614 } 8615 8616 uint32 _soc_tr3_tdm_arr[_MAX_TR3_TDM_SLOTS] = {-1}; 8617 int _soc_tr3_tdm_size = 0; 8618 _soc_tr3_flex_tdm_inf_t _soc_tr3_flex_tdm = {0}; 8619 8620 8621 STATIC int 8622 _soc_tr3_mmu_tdm_init(int unit) 8623 { 8624 static uint32 tr3_tdm_10[] = { /* FB3_1G_200 */ 8625 57, 73, 61, 1, 13, 57, 77, 61, 25, 41, 57, 73, 61, 81, 57, 77, 5, 61, 81, 8626 57, 73, 61, 9, 17, 57, 77, 61, 29, 45, 57, 73, 61, 81, 57, 77, 21, 61, 0, 8627 57, 73, 61, 2, 14, 57, 77, 61, 33, 49, 57, 73, 61, 81, 57, 77, 26, 61, 81, 8628 57, 73, 61, 6, 18, 57, 77, 61, 30, 42, 57, 73, 61, 81, 57, 77, 46, 61, 0, 8629 57, 73, 61, 10, 22, 57, 77, 61, 34, 50, 57, 73, 61, 81, 57, 77, 37, 61, -1, 8630 57, 73, 61, 3, 15, 57, 77, 61, 27, 43, 57, 73, 61, 81, 57, 77, 7, 61, 81, 8631 57, 73, 61, 11, 19, 57, 77, 61, 31, 47, 57, 73, 61, 81, 57, 77, 23, 61, 0, 8632 57, 73, 61, 4, 16, 57, 77, 61, 35, 51, 57, 73, 61, 81, 57, 77, 28, 61, 81, 8633 57, 73, 61, 8, 20, 57, 77, 61, 32, 44, 57, 73, 61, 81, 57, 77, 48, 61, 0, 8634 57, 73, 61, 12, 24, 57, 77, 61, 36, 52, 57, 73, 61, 81, 57, 77, 37, 61, -1 8635 }; 8636 static uint32 tr3_tdm_110[] = { /* 28xGE + 2xHG[42] + 2xHG[21] + 1GE */ 8637 57, 73, 61, -1, 13, 57, 77, 61, 25, -1, 57, 73, 61, 81, 57, 77, -1, 61, 81, 8638 57, 73, 61, 9, 17, 57, 77, 61, 29, -1, 57, 73, 61, 81, 57, 77, 21, 61, 0, 8639 57, 73, 61, -1, 14, 57, 77, 61, 33, -1, 57, 73, 61, 81, 57, 77, 26, 61, 81, 8640 57, 73, 61, -1, 18, 57, 77, 61, 30, -1, 57, 73, 61, 81, 57, 77, -1, 61, 0, 8641 57, 73, 61, 10, 22, 57, 77, 61, 34, -1, 57, 73, 61, 81, 57, 77, 37, 61, -1, 8642 57, 73, 61, -1, 15, 57, 77, 61, 27, -1, 57, 73, 61, 81, 57, 77, -1, 61, 81, 8643 57, 73, 61, 11, 19, 57, 77, 61, 31, -1, 57, 73, 61, 81, 57, 77, 23, 61, 0, 8644 57, 73, 61, -1, 16, 57, 77, 61, 35, -1, 57, 73, 61, 81, 57, 77, 28, 61, 81, 8645 57, 73, 61, -1, 20, 57, 77, 61, 32, -1, 57, 73, 61, 81, 57, 77, -1, 61, 0, 8646 57, 73, 61, 12, 24, 57, 77, 61, 36, -1, 57, 73, 61, 81, 57, 77, 37, 61, -1 8647 }; 8648 static uint32 tr3_tdm_11[] = { /* TR3_1G_200 */ 8649 69, 57, 73, 1, 13, 77, 58, 69, 25, 41, 73, 59, 65, 77, 60, 69, 5, 73, 65, 8650 77, 57, 69, 9, 17, 65, 58, 73, 29, 45, 77, 59, 65, 69, 60, 73, 21, 0, 65, 8651 77, 57, 69, 2, 14, 73, 58, 77, 33, 49, 69, 59, 65, 73, 60, 77, 26, 69, 65, 8652 73, 57, 77, 6, 18, 65, 58, 69, 30, 42, 73, 59, 65, 77, 60, 69, 46, 81, 65, 8653 73, 57, 77, 10, 22, 69, 58, 73, 34, 50, 77, 59, 65, 69, 60, 73, 37, 77, 65, 8654 69, 57, 73, 3, 15, 77, 58, 69, 27, 43, 73, 59, 65, 77, 60, 69, 7, 73, 65, 8655 77, 57, 69, 11, 19, 65, 58, 73, 31, 47, 77, 59, 65, 69, 60, 73, 23, 0, 65, 8656 77, 57, 69, 4, 16, 73, 58, 77, 35, 51, 69, 59, 65, 73, 60, 77, 28, 69, 65, 8657 73, 57, 77, 8, 20, 65, 58, 69, 32, 44, 73, 59, 65, 77, 60, 69, 48, -1, 65, 8658 73, 57, 77, 12, 24, 69, 58, 73, 36, 52, 77, 59, 65, 69, 60, 73, 37, 77, 65 8659 }; 8660 static uint32 tr3_tdm_12[] = { /* FB4_1G_200 */ 8661 73, 57, 77, 1, 13, 73, 58, 77, 25, 41, 73, 59, 77, 81, 73, 60, 5, 77, 81, 8662 73, 57, 77, 9, 17, 73, 58, 77, 29, 45, 73, 59, 77, 81, 73, 60, 21, 77, 0, 8663 73, 57, 77, 2, 14, 73, 58, 77, 33, 49, 73, 59, 77, 81, 73, 60, 26, 77, 81, 8664 73, 57, 77, 6, 18, 73, 58, 77, 30, 42, 73, 59, 77, 81, 73, 60, 46, 77, 0, 8665 73, 57, 77, 10, 22, 73, 58, 77, 34, 50, 73, 59, 77, 81, 73, 60, 37, 77, -1, 8666 73, 57, 77, 3, 15, 73, 58, 77, 27, 43, 73, 59, 77, 81, 73, 60, 7, 77, 81, 8667 73, 57, 77, 11, 19, 73, 58, 77, 31, 47, 73, 59, 77, 81, 73, 60, 23, 77, 0, 8668 73, 57, 77, 4, 16, 73, 58, 77, 35, 51, 73, 59, 77, 81, 73, 60, 28, 77, 81, 8669 73, 57, 77, 8, 20, 73, 58, 77, 32, 44, 73, 59, 77, 81, 73, 60, 48, 77, 0, 8670 73, 57, 77, 12, 24, 73, 58, 77, 36, 52, 73, 59, 77, 81, 73, 60, 37, 77, -1 8671 }; 8672 static uint32 tr3_tdm_112[] = { /* 28xGE + 4xXFI + 2xHG[42] + 1GE */ 8673 73, 57, 77, -1, 13, 73, 58, 77, 25, -1, 73, 59, 77, 81, 73, 60, -1, 77, 81, 8674 73, 57, 77, 9, 17, 73, 58, 77, 29, -1, 73, 59, 77, 81, 73, 60, 21, 77, 0, 8675 73, 57, 77, -1, 14, 73, 58, 77, 33, -1, 73, 59, 77, 81, 73, 60, 26, 77, 81, 8676 73, 57, 77, -1, 18, 73, 58, 77, 30, -1, 73, 59, 77, 81, 73, 60, -1, 77, 0, 8677 73, 57, 77, 10, 22, 73, 58, 77, 34, -1, 73, 59, 77, 81, 73, 60, 37, 77, -1, 8678 73, 57, 77, -1, 15, 73, 58, 77, 27, -1, 73, 59, 77, 81, 73, 60, -1, 77, 81, 8679 73, 57, 77, 11, 19, 73, 58, 77, 31, -1, 73, 59, 77, 81, 73, 60, 23, 77, 0, 8680 73, 57, 77, -1, 16, 73, 58, 77, 35, -1, 73, 59, 77, 81, 73, 60, 28, 77, 81, 8681 73, 57, 77, -1, 20, 73, 58, 77, 32, -1, 73, 59, 77, 81, 73, 60, -1, 77, 0, 8682 73, 57, 77, 12, 24, 73, 58, 77, 36, -1, 73, 59, 77, 81, 73, 60, 37, 77, -1 8683 }; 8684 static _soc_tr3_flex_tdm_inf_t flex_tr3_tdm_112 = { 8685 1, 8686 { 19, 19 }, 8687 { 0, 2 }, 8688 { 5, 5 } 8689 }; 8690 static uint32 tr3_tdm_35[] = { /* TR3_100GE_260 */ 8691 53, 69, 53, 69, 53, 69, 53, 69, 53, 69, 53, 69, 53, 69, 53, 69, 53, 69, 53, 69, 53, 69, 53, 69, 0, 8692 53, 69, 53, 69, 53, 69, 53, 69, 53, 69, 53, 69, 53, 69, 53, 69, 53, 69, 53, 69, 53, 69, 53, 69, 81, 8693 53, 69, 53, 69, 53, 69, 53, 69, 53, 69, 53, 69, 53, 69, 53, 69, 53, 69, 53, 69, 53, 69, 53, 69, 0, 8694 53, 69, 53, 69, 53, 69, 53, 69, 53, 69, 53, 69, 53, 69, 53, 69, 53, 69, 53, 69, 53, 69, 53, 69, 37, 8695 53, 69, 53, 69, 53, 69, 53, 69, 53, 69, 53, 69, 53, 69, 53, 69, 53, 69, 53, 69, 53, 69, 53, 69, 81, 8696 53, 69, 53, 69, 53, 69, 53, 69, 53, 69, 53, 69, 53, 69, 53, 69, 53, 69, 53, 69, 53, 69, 53, 69, 0, 8697 53, 69, 53, 69, 53, 69, 53, 69, 53, 69, 53, 69, 53, 69, 53, 69, 53, 69, 53, 69, 53, 69, 53, 69, 81, 8698 53, 69, 53, 69, 53, 69, 53, 69, 53, 69, 53, 69, 53, 69, 53, 69, 53, 69, 53, 69, 53, 69, 53, 69, -1, 8699 53, 69, 53, 69, 53, 69, 53, 69, 53, 69, 53, 69, 53, 69, 53, 69, 53, 69, 53, 69, 53, 69, 53, 69, 0, 8700 53, 69, 53, 69, 53, 69, 53, 69, 53, 69, 53, 69, 53, 69, 53, 69, 53, 69, 53, 69, 53, 69, 53, 69, 81 8701 }; 8702 static uint32 tr3_tdm_36[] = { /* 1x100GE + 4xHG[32] */ 8703 53, 69, 53, 65, 53, 73, 53, 77, 53, 69, 53, 65, 53, 73, 53, 77, 53, 69, 53, 65, 53, 73, 53, 77, 0, 8704 53, 69, 53, 65, 53, 73, 53, 77, 53, 69, 53, 65, 53, 73, 53, 77, 53, 69, 53, 65, 53, 73, 53, 77, 81, 8705 53, 69, 53, 65, 53, 73, 53, 77, 53, 69, 53, 65, 53, 73, 53, 77, 53, 69, 53, 65, 53, 73, 53, 77, 0, 8706 53, 69, 53, 65, 53, 73, 53, 77, 53, 69, 53, 65, 53, 73, 53, 77, 53, 69, 53, 65, 53, 73, 53, 77, 37, 8707 53, 69, 53, 65, 53, 73, 53, 77, 53, 69, 53, 65, 53, 73, 53, 77, 53, 69, 53, 65, 53, 73, 53, 77, 81, 8708 53, 69, 53, 65, 53, 73, 53, 77, 53, 69, 53, 65, 53, 73, 53, 77, 53, 69, 53, 65, 53, 73, 53, 77, 0, 8709 53, 69, 53, 65, 53, 73, 53, 77, 53, 69, 53, 65, 53, 73, 53, 77, 53, 69, 53, 65, 53, 73, 53, 77, 81, 8710 53, 69, 53, 65, 53, 73, 53, 77, 53, 69, 53, 65, 53, 73, 53, 77, 53, 69, 53, 65, 53, 73, 53, 77, -1, 8711 53, 69, 53, 65, 53, 73, 53, 77, 53, 69, 53, 65, 53, 73, 53, 77, 53, 69, 53, 65, 53, 73, 53, 77, 0, 8712 53, 69, 53, 65, 53, 73, 53, 77, 53, 69, 53, 65, 53, 73, 53, 77, 53, 69, 53, 65, 53, 73, 53, 77, 81 8713 }; 8714 static uint32 tr3_tdm_37[] = { /* 3xF.HG[42] + 1xHG[127] */ 8715 53, 69, 57, 69, 61, 69, 53, 69, 57, 69, 61, 69, 53, 69, 57, 69, 61, 69, 53, 69, 57, 69, 61, 69, 0, 8716 53, 69, 57, 69, 61, 69, 53, 69, 57, 69, 61, 69, 53, 69, 57, 69, 61, 69, 53, 69, 57, 69, 61, 69, 81, 8717 53, 69, 57, 69, 61, 69, 53, 69, 57, 69, 61, 69, 53, 69, 57, 69, 61, 69, 53, 69, 57, 69, 61, 69, 0, 8718 53, 69, 57, 69, 61, 69, 53, 69, 57, 69, 61, 69, 53, 69, 57, 69, 61, 69, 53, 69, 57, 69, 61, 69, 37, 8719 53, 69, 57, 69, 61, 69, 53, 69, 57, 69, 61, 69, 53, 69, 57, 69, 61, 69, 53, 69, 57, 69, 61, 69, 81, 8720 53, 69, 57, 69, 61, 69, 53, 69, 57, 69, 61, 69, 53, 69, 57, 69, 61, 69, 53, 69, 57, 69, 61, 69, 0, 8721 53, 69, 57, 69, 61, 69, 53, 69, 57, 69, 61, 69, 53, 69, 57, 69, 61, 69, 53, 69, 57, 69, 61, 69, 81, 8722 53, 69, 57, 69, 61, 69, 53, 69, 57, 69, 61, 69, 53, 69, 57, 69, 61, 69, 53, 69, 57, 69, 61, 69, -1, 8723 53, 69, 57, 69, 61, 69, 53, 69, 57, 69, 61, 69, 53, 69, 57, 69, 61, 69, 53, 69, 57, 69, 61, 69, 0, 8724 53, 69, 57, 69, 61, 69, 53, 69, 57, 69, 61, 69, 53, 69, 57, 69, 61, 69, 53, 69, 57, 69, 61, 69, 81 8725 }; 8726 static _soc_tr3_flex_tdm_inf_t flex_tr3_tdm_37 = { 8727 1, 8728 { 25, 25, 25 }, 8729 { 0, 2, 4 }, 8730 { 6, 6, 6 } 8731 }; 8732 static uint32 tr3_tdm_38[] = { /* 1x100GE + 3xF.HG[42] */ 8733 69, 53, 73, 53, 77, 53, 69, 53, 73, 53, 77, 53, 69, 53, 73, 53, 77, 53, 69, 53, 73, 53, 77, 53, 0, 8734 69, 53, 73, 53, 77, 53, 69, 53, 73, 53, 77, 53, 69, 53, 73, 53, 77, 53, 69, 53, 73, 53, 77, 53, 81, 8735 69, 53, 73, 53, 77, 53, 69, 53, 73, 53, 77, 53, 69, 53, 73, 53, 77, 53, 69, 53, 73, 53, 77, 53, 0, 8736 69, 53, 73, 53, 77, 53, 69, 53, 73, 53, 77, 53, 69, 53, 73, 53, 77, 53, 69, 53, 73, 53, 77, 53, 37, 8737 69, 53, 73, 53, 77, 53, 69, 53, 73, 53, 77, 53, 69, 53, 73, 53, 77, 53, 69, 53, 73, 53, 77, 53, 81, 8738 69, 53, 73, 53, 77, 53, 69, 53, 73, 53, 77, 53, 69, 53, 73, 53, 77, 53, 69, 53, 73, 53, 77, 53, 0, 8739 69, 53, 73, 53, 77, 53, 69, 53, 73, 53, 77, 53, 69, 53, 73, 53, 77, 53, 69, 53, 73, 53, 77, 53, 81, 8740 69, 53, 73, 53, 77, 53, 69, 53, 73, 53, 77, 53, 69, 53, 73, 53, 77, 53, 69, 53, 73, 53, 77, 53, -1, 8741 69, 53, 73, 53, 77, 53, 69, 53, 73, 53, 77, 53, 69, 53, 73, 53, 77, 53, 69, 53, 73, 53, 77, 53, 0, 8742 69, 53, 73, 53, 77, 53, 69, 53, 73, 53, 77, 53, 69, 53, 73, 53, 77, 53, 69, 53, 73, 53, 77, 53, 81 8743 }; 8744 static _soc_tr3_flex_tdm_inf_t flex_tr3_tdm_38 = { 8745 1, 8746 { 25, 25, 25 }, 8747 { 0, 2, 4 }, 8748 { 6, 6, 6 } 8749 }; 8750 static uint32 tr3_tdm_40[] = { /* AP2_1G_200_A */ 8751 57, 73, 61, 41, 81, 57, 77, 61, 25, 45, 57, 73, 61, 13, 57, 77, 49, 61, 0, 8752 57, 73, 61, 42, 21, 57, 77, 61, 9, 45, 57, 73, 61, 17, 57, 77, 49, 61, 81, 8753 57, 73, 61, 43, 81, 57, 77, 61, 33, 45, 57, 73, 61, 14, 57, 77, 49, 61, 0, 8754 57, 73, 61, 44, 26, 57, 77, 61, 10, 45, 57, 73, 61, 18, 57, 77, 49, 61, 81, 8755 57, 73, 61, 41, -1, 57, 77, 61, 34, 45, 57, 73, 61, 22, 57, 77, 49, 61, 37, 8756 57, 73, 61, 42, 81, 57, 77, 61, 27, 45, 57, 73, 61, 15, 57, 77, 49, 61, 0, 8757 57, 73, 61, 43, 23, 57, 77, 61, 11, 45, 57, 73, 61, 19, 57, 77, 49, 61, 81, 8758 57, 73, 61, 44, 81, 57, 77, 61, 35, 45, 57, 73, 61, 16, 57, 77, 49, 61, 0, 8759 57, 73, 61, 41, 28, 57, 77, 61, 12, 45, 57, 73, 61, 20, 57, 77, 49, 61, 81, 8760 57, 73, 61, 42, -1, 57, 77, 61, 36, 45, 57, 73, 61, 24, 57, 77, 49, 61, 37, 8761 57, 73, 61, 43, 81, 57, 77, 61, 25, 45, 57, 73, 61, 13, 57, 77, 49, 61, 0, 8762 57, 73, 61, 44, 21, 57, 77, 61, 9, 45, 57, 73, 61, 17, 57, 77, 49, 61, 81, 8763 57, 73, 61, 41, 81, 57, 77, 61, 33, 45, 57, 73, 61, 14, 57, 77, 49, 61, 0, 8764 57, 73, 61, 42, 26, 57, 77, 61, 10, 45, 57, 73, 61, 18, 57, 77, 49, 61, 81, 8765 57, 73, 61, 43, -1, 57, 77, 61, 34, 45, 57, 73, 61, 22, 57, 77, 49, 61, 37, 8766 57, 73, 61, 44, 81, 57, 77, 61, 27, 45, 57, 73, 61, 15, 57, 77, 49, 61, 0, 8767 57, 73, 61, 41, 23, 57, 77, 61, 11, 45, 57, 73, 61, 19, 57, 77, 49, 61, 81, 8768 57, 73, 61, 42, 81, 57, 77, 61, 35, 45, 57, 73, 61, 16, 57, 77, 49, 61, 0, 8769 57, 73, 61, 43, 28, 57, 77, 61, 12, 45, 57, 73, 61, 20, 57, 77, 49, 61, 81, 8770 57, 73, 61, 44, -1, 57, 77, 61, 36, 45, 57, 73, 61, 24, 57, 77, 49, 61, 37 8771 }; 8772 static _soc_tr3_flex_tdm_inf_t flex_tr3_tdm_40 = { 8773 1, 8774 { 76, 76, 19, 19, 38, 38 }, 8775 { 9, 16, 0, 2, 1, 6 }, 8776 { 19, 19, 5, 5, 10, 9 } 8777 }; 8778 static uint32 tr3_tdm_41[] = { /* AP2_1G_200_B */ 8779 57, 73, 61, 41, 81, 57, 77, 61, 25, 45, 57, 73, 61, 13, 57, 77, 49, 61, 0, 8780 57, 73, 61, 42, 21, 57, 77, 61, 9, 46, 57, 73, 61, 17, 57, 77, 50, 61, 81, 8781 57, 73, 61, 43, 81, 57, 77, 61, 33, 47, 57, 73, 61, 14, 57, 77, 51, 61, 0, 8782 57, 73, 61, 44, 26, 57, 77, 61, 10, 48, 57, 73, 61, 18, 57, 77, 52, 61, 81, 8783 57, 73, 61, 41, -1, 57, 77, 61, 34, 45, 57, 73, 61, 22, 57, 77, 49, 61, 37, 8784 57, 73, 61, 42, 81, 57, 77, 61, 27, 46, 57, 73, 61, 15, 57, 77, 50, 61, 0, 8785 57, 73, 61, 43, 23, 57, 77, 61, 11, 47, 57, 73, 61, 19, 57, 77, 51, 61, 81, 8786 57, 73, 61, 44, 81, 57, 77, 61, 35, 48, 57, 73, 61, 16, 57, 77, 52, 61, 0, 8787 57, 73, 61, 41, 28, 57, 77, 61, 12, 45, 57, 73, 61, 20, 57, 77, 49, 61, 81, 8788 57, 73, 61, 42, -1, 57, 77, 61, 36, 46, 57, 73, 61, 24, 57, 77, 50, 61, 37, 8789 57, 73, 61, 43, 81, 57, 77, 61, 25, 47, 57, 73, 61, 13, 57, 77, 51, 61, 0, 8790 57, 73, 61, 44, 21, 57, 77, 61, 9, 48, 57, 73, 61, 17, 57, 77, 52, 61, 81, 8791 57, 73, 61, 41, 81, 57, 77, 61, 33, 45, 57, 73, 61, 14, 57, 77, 49, 61, 0, 8792 57, 73, 61, 42, 26, 57, 77, 61, 10, 46, 57, 73, 61, 18, 57, 77, 50, 61, 81, 8793 57, 73, 61, 43, -1, 57, 77, 61, 34, 47, 57, 73, 61, 22, 57, 77, 51, 61, 37, 8794 57, 73, 61, 44, 81, 57, 77, 61, 27, 48, 57, 73, 61, 15, 57, 77, 52, 61, 0, 8795 57, 73, 61, 41, 23, 57, 77, 61, 11, 45, 57, 73, 61, 19, 57, 77, 49, 61, 81, 8796 57, 73, 61, 42, 81, 57, 77, 61, 35, 46, 57, 73, 61, 16, 57, 77, 50, 61, 0, 8797 57, 73, 61, 43, 28, 57, 77, 61, 12, 47, 57, 73, 61, 20, 57, 77, 51, 61, 81, 8798 57, 73, 61, 44, -1, 57, 77, 61, 36, 48, 57, 73, 61, 24, 57, 77, 52, 61, 37 8799 }; 8800 static const uint32 tr3_tdm_50[] = { /* FB4_1G_260_EMU */ 8801 73, -1, 57, 77, 1, 13, 73, 81, 58, 77, 25, 41, 73, -1, 59, 77, -1, 81, 73, 5, 60, 77, -1, -1, 0, 8802 73, -1, 57, 77, 9, 17, 73, 81, 58, 77, 29, 45, 73, -1, 59, 77, -1, 81, 73, 21, 60, 77, -1, -1, 81, 8803 73, -1, 57, 77, 2, 14, 73, 81, 58, 77, 33, 49, 73, -1, 59, 77, -1, 81, 73, 26, 60, 77, -1, -1, 0, 8804 73, -1, 57, 77, 6, 18, 73, 81, 58, 77, 30, 42, 73, -1, 59, 77, -1, 81, 73, 46, 60, 77, -1, -1, -1, 8805 73, -1, 57, 77, 10, 22, 73, 81, 58, 77, 34, 50, 73, -1, 59, 77, -1, 81, 73, 37, 60, 77, -1, -1, 81, 8806 73, -1, 57, 77, 3, 15, 73, 81, 58, 77, 27, 43, 73, -1, 59, 77, -1, 81, 73, 7, 60, 77, -1, -1, 0, 8807 73, -1, 57, 77, 11, 19, 73, 81, 58, 77, 31, 47, 73, -1, 59, 77, -1, 81, 73, 23, 60, 77, -1, -1, 81, 8808 73, -1, 57, 77, 4, 16, 73, 81, 58, 77, 35, 51, 73, -1, 59, 77, -1, 81, 73, 28, 60, 77, -1, -1, -1, 8809 73, -1, 57, 77, 8, 20, 73, 81, 58, 77, 32, 44, 73, -1, 59, 77, -1, 81, 73, 48, 60, 77, -1, -1, 0, 8810 73, -1, 57, 77, 12, 24, 73, 81, 58, 77, 36, 52, 73, -1, 59, 77, -1, 81, 73, 37, 60, 77, -1, -1, 81 8811 }; 8812 static const uint32 tr3_tdm_55[] = { /* RNGR_XAUI_260: 12xXAUI + 3xF.HG[42] + 1GE */ 8813 1, 69, 13, 73, 25, 77, 41, 69, 5, 73, 17, 77, 29, 69, 45, 73, 9, 77, 21, 69, 33, 73, 49, 77, 0, 8814 1, 69, 13, 73, 25, 77, 41, 69, 5, 73, 17, 77, 29, 69, 45, 73, 9, 77, 21, 69, 33, 73, 49, 77, 81, 8815 1, 69, 13, 73, 25, 77, 41, 69, 5, 73, 17, 77, 29, 69, 45, 73, 9, 77, 21, 69, 33, 73, 49, 77, 0, 8816 1, 69, 13, 73, 25, 77, 41, 69, 5, 73, 17, 77, 29, 69, 45, 73, 9, 77, 21, 69, 33, 73, 49, 77, 37, 8817 1, 69, 13, 73, 25, 77, 41, 69, 5, 73, 17, 77, 29, 69, 45, 73, 9, 77, 21, 69, 33, 73, 49, 77, 81, 8818 1, 69, 13, 73, 25, 77, 41, 69, 5, 73, 17, 77, 29, 69, 45, 73, 9, 77, 21, 69, 33, 73, 49, 77, 0, 8819 1, 69, 13, 73, 25, 77, 41, 69, 5, 73, 17, 77, 29, 69, 45, 73, 9, 77, 21, 69, 33, 73, 49, 77, 81, 8820 1, 69, 13, 73, 25, 77, 41, 69, 5, 73, 17, 77, 29, 69, 45, 73, 9, 77, 21, 69, 33, 73, 49, 77, -1, 8821 1, 69, 13, 73, 25, 77, 41, 69, 5, 73, 17, 77, 29, 69, 45, 73, 9, 77, 21, 69, 33, 73, 49, 77, 0, 8822 1, 69, 13, 73, 25, 77, 41, 69, 5, 73, 17, 77, 29, 69, 45, 73, 9, 77, 21, 69, 33, 73, 49, 77, 81 8823 }; 8824 static _soc_tr3_flex_tdm_inf_t flex_tr3_tdm_55 = { 8825 1, 8826 { 25, 25, 25 }, 8827 { 1, 3, 5 }, 8828 { 6, 6, 6 } 8829 }; 8830 static const uint32 tr3_tdm_155[] = { /* 12xXAUI + 2xF.HG[42] + 1GE */ 8831 1, 69, 13, 73, 25, -1, 41, 69, 5, 73, 17, -1, 29, 69, 45, 73, 9, -1, 21, 69, 33, 73, 49, -1, 0, 8832 1, 69, 13, 73, 25, -1, 41, 69, 5, 73, 17, -1, 29, 69, 45, 73, 9, -1, 21, 69, 33, 73, 49, -1, 81, 8833 1, 69, 13, 73, 25, -1, 41, 69, 5, 73, 17, -1, 29, 69, 45, 73, 9, -1, 21, 69, 33, 73, 49, -1, 0, 8834 1, 69, 13, 73, 25, -1, 41, 69, 5, 73, 17, -1, 29, 69, 45, 73, 9, -1, 21, 69, 33, 73, 49, -1, 37, 8835 1, 69, 13, 73, 25, -1, 41, 69, 5, 73, 17, -1, 29, 69, 45, 73, 9, -1, 21, 69, 33, 73, 49, -1, 81, 8836 1, 69, 13, 73, 25, -1, 41, 69, 5, 73, 17, -1, 29, 69, 45, 73, 9, -1, 21, 69, 33, 73, 49, -1, 0, 8837 1, 69, 13, 73, 25, -1, 41, 69, 5, 73, 17, -1, 29, 69, 45, 73, 9, -1, 21, 69, 33, 73, 49, -1, 81, 8838 1, 69, 13, 73, 25, -1, 41, 69, 5, 73, 17, -1, 29, 69, 45, 73, 9, -1, 21, 69, 33, 73, 49, -1, -1, 8839 1, 69, 13, 73, 25, -1, 41, 69, 5, 73, 17, -1, 29, 69, 45, 73, 9, -1, 21, 69, 33, 73, 49, -1, 0, 8840 1, 69, 13, 73, 25, -1, 41, 69, 5, 73, 17, -1, 29, 69, 45, 73, 9, -1, 21, 69, 33, 73, 49, -1, 81 8841 }; 8842 static _soc_tr3_flex_tdm_inf_t flex_tr3_tdm_155 = { 8843 1, 8844 { 25, 25 }, 8845 { 1, 3 }, 8846 { 6, 6 } 8847 }; 8848 static const uint32 tr3_tdm_71[] = { /* 3xF.40GE + 3xF.HG[42], 3xF.HG[42] + 3xF.40GE */ 8849 53, 69, 57, 73, 61, 77, 53, 69, 57, 73, 61, 77, 53, 69, 57, 73, 61, 77, 53, 69, 57, 73, 61, 77, 0, 8850 53, 69, 57, 73, 61, 77, 53, 69, 57, 73, 61, 77, 53, 69, 57, 73, 61, 77, 53, 69, 57, 73, 61, 77, 81, 8851 53, 69, 57, 73, 61, 77, 53, 69, 57, 73, 61, 77, 53, 69, 57, 73, 61, 77, 53, 69, 57, 73, 61, 77, 0, 8852 53, 69, 57, 73, 61, 77, 53, 69, 57, 73, 61, 77, 53, 69, 57, 73, 61, 77, 53, 69, 57, 73, 61, 77, 37, 8853 53, 69, 57, 73, 61, 77, 53, 69, 57, 73, 61, 77, 53, 69, 57, 73, 61, 77, 53, 69, 57, 73, 61, 77, 81, 8854 53, 69, 57, 73, 61, 77, 53, 69, 57, 73, 61, 77, 53, 69, 57, 73, 61, 77, 53, 69, 57, 73, 61, 77, 0, 8855 53, 69, 57, 73, 61, 77, 53, 69, 57, 73, 61, 77, 53, 69, 57, 73, 61, 77, 53, 69, 57, 73, 61, 77, 81, 8856 53, 69, 57, 73, 61, 77, 53, 69, 57, 73, 61, 77, 53, 69, 57, 73, 61, 77, 53, 69, 57, 73, 61, 77, -1, 8857 53, 69, 57, 73, 61, 77, 53, 69, 57, 73, 61, 77, 53, 69, 57, 73, 61, 77, 53, 69, 57, 73, 61, 77, 0, 8858 53, 69, 57, 73, 61, 77, 53, 69, 57, 73, 61, 77, 53, 69, 57, 73, 61, 77, 53, 69, 57, 73, 61, 77, 81 8859 }; 8860 static _soc_tr3_flex_tdm_inf_t flex_tr3_tdm_71 = { 8861 1, 8862 { 25, 25, 25, 25, 25, 25 }, 8863 { 0, 2, 4, 1, 3, 5 }, 8864 { 6, 6, 6, 6, 6, 6 } 8865 }; 8866 static const uint32 tr3_tdm_171[] = { /* 3xF.40GE + 2xF.HG[42], 3xF.HG[42] + 2xF.40GE */ 8867 53, 69, 57, 73, 61, -1, 53, 69, 57, 73, 61, -1, 53, 69, 57, 73, 61, -1, 53, 69, 57, 73, 61, -1, 0, 8868 53, 69, 57, 73, 61, -1, 53, 69, 57, 73, 61, -1, 53, 69, 57, 73, 61, -1, 53, 69, 57, 73, 61, -1, 81, 8869 53, 69, 57, 73, 61, -1, 53, 69, 57, 73, 61, -1, 53, 69, 57, 73, 61, -1, 53, 69, 57, 73, 61, -1, 0, 8870 53, 69, 57, 73, 61, -1, 53, 69, 57, 73, 61, -1, 53, 69, 57, 73, 61, -1, 53, 69, 57, 73, 61, -1, 37, 8871 53, 69, 57, 73, 61, -1, 53, 69, 57, 73, 61, -1, 53, 69, 57, 73, 61, -1, 53, 69, 57, 73, 61, -1, 81, 8872 53, 69, 57, 73, 61, -1, 53, 69, 57, 73, 61, -1, 53, 69, 57, 73, 61, -1, 53, 69, 57, 73, 61, -1, 0, 8873 53, 69, 57, 73, 61, -1, 53, 69, 57, 73, 61, -1, 53, 69, 57, 73, 61, -1, 53, 69, 57, 73, 61, -1, 81, 8874 53, 69, 57, 73, 61, -1, 53, 69, 57, 73, 61, -1, 53, 69, 57, 73, 61, -1, 53, 69, 57, 73, 61, -1, -1, 8875 53, 69, 57, 73, 61, -1, 53, 69, 57, 73, 61, -1, 53, 69, 57, 73, 61, -1, 53, 69, 57, 73, 61, -1, 0, 8876 53, 69, 57, 73, 61, -1, 53, 69, 57, 73, 61, -1, 53, 69, 57, 73, 61, -1, 53, 69, 57, 73, 61, -1, 81 8877 }; 8878 static _soc_tr3_flex_tdm_inf_t flex_tr3_tdm_171 = { 8879 1, 8880 { 25, 25, 25, 25, 25 }, 8881 { 0, 2, 4, 1, 3 }, 8882 { 6, 6, 6, 6, 6 } 8883 }; 8884 static uint32 tr3_tdm_81[] = { /* 1x100GE + 8xHGd[16] */ 8885 53, 69, 53, 73, 53, 65, 53, 77, 53, 71, 53, 67, 53, 75, 53, 79, 53, 65, 69, 53, 73, 53, 77, 53, 0, 8886 53, 71, 53, 75, 53, 67, 53, 79, 53, 69, 53, 65, 53, 73, 53, 77, 53, 67, 71, 53, 75, 53, 79, 53, 81, 8887 53, 69, 53, 73, 53, 65, 53, 77, 53, 71, 53, 67, 53, 75, 53, 79, 53, 65, 69, 53, 73, 53, 77, 53, 0, 8888 53, 71, 53, 75, 53, 67, 53, 79, 53, 69, 53, 65, 53, 73, 53, 77, 53, 67, 71, 53, 75, 53, 79, 53, 37, 8889 53, 69, 53, 73, 53, 65, 53, 77, 53, 71, 53, 67, 53, 75, 53, 79, 53, 65, 69, 53, 73, 53, 77, 53, 81, 8890 53, 71, 53, 75, 53, 67, 53, 79, 53, 69, 53, 65, 53, 73, 53, 77, 53, 67, 71, 53, 75, 53, 79, 53, 0, 8891 53, 69, 53, 73, 53, 65, 53, 77, 53, 71, 53, 67, 53, 75, 53, 79, 53, 65, 69, 53, 73, 53, 77, 53, 81, 8892 53, 71, 53, 75, 53, 67, 53, 79, 53, 69, 53, 65, 53, 73, 53, 77, 53, 67, 71, 53, 75, 53, 79, 53, -1, 8893 53, 69, 53, 73, 53, 65, 53, 77, 53, 71, 53, 67, 53, 75, 53, 79, 53, 65, 69, 53, 73, 53, 77, 53, 0, 8894 53, 71, 53, 75, 53, 67, 53, 79, 53, 69, 53, 65, 53, 73, 53, 77, 53, 67, 71, 53, 75, 53, 79, 53, 81 8895 }; 8896 static uint32 tr3_tdm_82[] = { /* 3xF.HG[42] + 4xHG[32] */ 8897 53, 69, 57, 65, 61, 73, 53, 77, 57, 69, 61, 65, 53, 73, 57, 77, 61, 69, 53, 65, 57, 73, 61, 77, 0, 8898 53, 69, 57, 65, 61, 73, 53, 77, 57, 69, 61, 65, 53, 73, 57, 77, 61, 69, 53, 65, 57, 73, 61, 77, 81, 8899 53, 69, 57, 65, 61, 73, 53, 77, 57, 69, 61, 65, 53, 73, 57, 77, 61, 69, 53, 65, 57, 73, 61, 77, 0, 8900 53, 69, 57, 65, 61, 73, 53, 77, 57, 69, 61, 65, 53, 73, 57, 77, 61, 69, 53, 65, 57, 73, 61, 77, 37, 8901 53, 69, 57, 65, 61, 73, 53, 77, 57, 69, 61, 65, 53, 73, 57, 77, 61, 69, 53, 65, 57, 73, 61, 77, 81, 8902 53, 69, 57, 65, 61, 73, 53, 77, 57, 69, 61, 65, 53, 73, 57, 77, 61, 69, 53, 65, 57, 73, 61, 77, 0, 8903 53, 69, 57, 65, 61, 73, 53, 77, 57, 69, 61, 65, 53, 73, 57, 77, 61, 69, 53, 65, 57, 73, 61, 77, 81, 8904 53, 69, 57, 65, 61, 73, 53, 77, 57, 69, 61, 65, 53, 73, 57, 77, 61, 69, 53, 65, 57, 73, 61, 77, -1, 8905 53, 69, 57, 65, 61, 73, 53, 77, 57, 69, 61, 65, 53, 73, 57, 77, 61, 69, 53, 65, 57, 73, 61, 77, 0, 8906 53, 69, 57, 65, 61, 73, 53, 77, 57, 69, 61, 65, 53, 73, 57, 77, 61, 69, 53, 65, 57, 73, 61, 77, 81 8907 }; 8908 static uint32 tr3_tdm_83[] = { /* 3xF.HG[42] + 8xHGd[16] */ 8909 53, 69, 57, 73, 61, 65, 53, 77, 57, 71, 61, 67, 53, 75, 57, 79, 61, 65, 69, 53, 73, 57, 77, 61, 0, 8910 53, 71, 57, 75, 61, 67, 53, 79, 57, 69, 61, 65, 53, 73, 57, 77, 61, 67, 71, 53, 75, 57, 79, 61, 81, 8911 53, 69, 57, 73, 61, 65, 53, 77, 57, 71, 61, 67, 53, 75, 57, 79, 61, 65, 69, 53, 73, 57, 77, 61, 0, 8912 53, 71, 57, 75, 61, 67, 53, 79, 57, 69, 61, 65, 53, 73, 57, 77, 61, 67, 71, 53, 75, 57, 79, 61, 37, 8913 53, 69, 57, 73, 61, 65, 53, 77, 57, 71, 61, 67, 53, 75, 57, 79, 61, 65, 69, 53, 73, 57, 77, 61, 81, 8914 53, 71, 57, 75, 61, 67, 53, 79, 57, 69, 61, 65, 53, 73, 57, 77, 61, 67, 71, 53, 75, 57, 79, 61, 0, 8915 53, 69, 57, 73, 61, 65, 53, 77, 57, 71, 61, 67, 53, 75, 57, 79, 61, 65, 69, 53, 73, 57, 77, 61, 81, 8916 53, 71, 57, 75, 61, 67, 53, 79, 57, 69, 61, 65, 53, 73, 57, 77, 61, 67, 71, 53, 75, 57, 79, 61, -1, 8917 53, 69, 57, 73, 61, 65, 53, 77, 57, 71, 61, 67, 53, 75, 57, 79, 61, 65, 69, 53, 73, 57, 77, 61, 0, 8918 53, 71, 57, 75, 61, 67, 53, 79, 57, 69, 61, 65, 53, 73, 57, 77, 61, 67, 71, 53, 75, 57, 79, 61, 81 8919 }; 8920 static const uint32 tr3_tdm_90[] = { /* FB3_1G_200_HG25 */ 8921 57, 73, 1, 13, 61, 77, 25, 41, 57, 73, 81, 61, 77, 5, 57, 73, 0, 61, 77, 8922 57, 73, 9, 17, 61, 77, 29, 45, 57, 73, 81, 61, 77, 21, 57, 73, -1, 61, 77, 8923 57, 73, 2, 14, 61, 77, 33, 49, 57, 73, 81, 61, 77, 26, 57, 73, 0, 61, 77, 8924 57, 73, 6, 18, 61, 77, 30, 42, 57, 73, 81, 61, 77, 46, 57, 73, -1, 61, 77, 8925 57, 73, 10, 22, 61, 77, 34, 50, 57, 73, 81, 61, 77, 37, 57, 73, 0, 61, 77, 8926 57, 73, 3, 15, 61, 77, 27, 43, 57, 73, 81, 61, 77, 7, 57, 73, 0, 61, 77, 8927 57, 73, 11, 19, 61, 77, 31, 47, 57, 73, 81, 61, 77, 23, 57, 73, -1, 61, 77, 8928 57, 73, 4, 16, 61, 77, 35, 51, 57, 73, 81, 61, 77, 28, 57, 73, 0, 61, 77, 8929 57, 73, 8, 20, 61, 77, 32, 44, 57, 73, 81, 61, 77, 48, 57, 73, -1, 61, 77, 8930 57, 73, 12, 24, 61, 77, 36, 52, 57, 73, 81, 61, 77, 37, 57, 73, 0, 61, 77 8931 }; 8932 static const uint32 tr3_tdm_190[] = { /* 24xGE-LR + 2xXAUI + 2xHG[21] + 1GE */ 8933 73, 57, 1, 13, 77, 61, 81, 73, 5, 17, 57, 77, 61, 0, 73, 9, 57, 77, 61, 8934 73, 57, 2, 21, 77, 61, 81, 73, 6, 14, 57, 77, 61, -1, 73, 18, 57, 77, 61, 8935 73, 57, 10, 22, 77, 61, 81, 73, 3, 15, 57, 77, 61, 0, 73, 7, 57, 77, 61, 8936 73, 57, 11, 19, 77, 61, 81, 73, 4, 23, 57, 77, 61, -1, 73, 16, 57, 77, 61, 8937 73, 57, 8, 20, 77, 61, 81, 73, 12, 24, 57, 77, 61, 0, 73, 37, 57, 77, 61 8938 }; 8939 static uint32 tr3_tdm_91[] = { /* FB4_XAUI_200_C -> 10xF.XAUI + 4xHG[21] + 1GE */ 8940 57, 1, 73, 13, 61, 25, 77, 5, 57, 17, 73, 29, 49, 61, 9, 77, 21, 33, 81, 8941 57, 1, 73, 13, 61, 25, 77, 5, 57, 17, 73, 29, 49, 61, 9, 77, 21, 33, 0, 8942 57, 1, 73, 13, 61, 25, 77, 5, 57, 17, 73, 29, 49, 61, 9, 77, 21, 33, 37, 8943 57, 1, 73, 13, 61, 25, 77, 5, 57, 17, 73, 29, 49, 61, 9, 77, 21, 33, 0, 8944 57, 1, 73, 13, 61, 25, 77, 5, 57, 17, 73, 29, 49, 61, 9, 77, 21, 33, -1, 8945 57, 1, 73, 13, 61, 25, 77, 5, 57, 17, 73, 29, 49, 61, 9, 77, 21, 33, 81, 8946 57, 1, 73, 13, 61, 25, 77, 5, 57, 17, 73, 29, 49, 61, 9, 77, 21, 33, 0, 8947 57, 1, 73, 13, 61, 25, 77, 5, 57, 17, 73, 29, 49, 61, 9, 77, 21, 33, 37, 8948 57, 1, 73, 13, 61, 25, 77, 5, 57, 17, 73, 29, 49, 61, 9, 77, 21, 33, 0, 8949 57, 1, 73, 13, 61, 25, 77, 5, 57, 17, 73, 29, 49, 61, 9, 77, 21, 33, -1, 8950 57, 1, 73, 13, 61, 25, 77, 5, 57, 17, 73, 29, 49, 61, 9, 77, 21, 33, 81, 8951 57, 1, 73, 13, 61, 25, 77, 5, 57, 17, 73, 29, 49, 61, 9, 77, 21, 33, 0, 8952 57, 1, 73, 13, 61, 25, 77, 5, 57, 17, 73, 29, 49, 61, 9, 77, 21, 33, 37, 8953 57, 1, 73, 13, 61, 25, 77, 5, 57, 17, 73, 29, 49, 61, 9, 77, 21, 33, 0, 8954 57, 1, 73, 13, 61, 25, 77, 5, 57, 17, 73, 29, 49, 61, 9, 77, 21, 33, -1, 8955 57, 1, 73, 13, 61, 25, 77, 5, 57, 17, 73, 29, 49, 61, 9, 77, 21, 33, 81, 8956 57, 1, 73, 13, 61, 25, 77, 5, 57, 17, 73, 29, 49, 61, 9, 77, 21, 33, 0, 8957 57, 1, 73, 13, 61, 25, 77, 5, 57, 17, 73, 29, 49, 61, 9, 77, 21, 33, 37, 8958 57, 1, 73, 13, 61, 25, 77, 5, 57, 17, 73, 29, 49, 61, 9, 77, 21, 33, 0, 8959 57, 1, 73, 13, 61, 25, 77, 5, 57, 17, 73, 29, 49, 61, 9, 77, 21, 33, -1 8960 }; 8961 static _soc_tr3_flex_tdm_inf_t flex_tr3_tdm_91 = { 8962 1, 8963 { 76, 76, 76, 76, 76, 76, 76, 76, 76, 76 }, 8964 { 1, 7, 14, 3, 9, 16, 5, 11, 17, 12 }, 8965 { 19, 19, 19, 19, 19, 19, 19, 19, 19, 19 } 8966 }; 8967 static uint32 tr3_tdm_94[] = { /* FB4_XAUI_200_F */ 8968 57, 73, 1, 77, 81, 58, 74, 17, 78, -1, 59, 75, 29, 79, 81, 60, 76, 49, 80, 8969 57, 73, 1, 77, 81, 58, 74, 17, 78, 0, 59, 75, 29, 79, 81, 60, 76, 49, 80, 8970 57, 73, 1, 77, 81, 58, 74, 17, 78, 37, 59, 75, 29, 79, 81, 60, 76, 49, 80, 8971 57, 73, 1, 77, 81, 58, 74, 17, 78, 0, 59, 75, 29, 79, 81, 60, 76, 49, 80, 8972 57, 73, 1, 77, 81, 58, 74, 17, 78, -1, 59, 75, 29, 79, 81, 60, 76, 49, 80 8973 }; 8974 static uint32 tr3_tdm_95[] = { /* TR3_1G_280 */ 8975 1, 69, 57, 73, 65, 77, 13, 69, 58, 73, 65, 77, 5, 69, 59, 73, 65, 77, 25, 69, 60, 73, 65, 77, 41, 0, 8976 9, 69, 57, 73, 65, 77, 17, 69, 58, 73, 65, 77, 21, 69, 59, 73, 65, 77, 29, 69, 60, 73, 65, 77, 45, 81, 8977 2, 69, 57, 73, 65, 77, 14, 69, 58, 73, 65, 77, 33, 69, 59, 73, 65, 77, 26, 69, 60, 73, 65, 77, 49, 0, 8978 6, 69, 57, 73, 65, 77, 18, 69, 58, 73, 65, 77, 42, 69, 59, 73, 65, 77, 30, 69, 60, 73, 65, 77, 46, 81, 8979 10, 69, 57, 73, 65, 77, 22, 69, 58, 73, 65, 77, 37, 69, 59, 73, 65, 77, 34, 69, 60, 73, 65, 77, 50, 0, 8980 3, 69, 57, 73, 65, 77, 15, 69, 58, 73, 65, 77, 7, 69, 59, 73, 65, 77, 27, 69, 60, 73, 65, 77, 43, 81, 8981 11, 69, 57, 73, 65, 77, 19, 69, 58, 73, 65, 77, 23, 69, 59, 73, 65, 77, 31, 69, 60, 73, 65, 77, 47, 0, 8982 4, 69, 57, 73, 65, 77, 16, 69, 58, 73, 65, 77, 35, 69, 59, 73, 65, 77, 28, 69, 60, 73, 65, 77, 51, 81, 8983 8, 69, 57, 73, 65, 77, 20, 69, 58, 73, 65, 77, 44, 69, 59, 73, 65, 77, 32, 69, 60, 73, 65, 77, 48, -1, 8984 12, 69, 57, 73, 65, 77, 24, 69, 58, 73, 65, 77, 37, 69, 59, 73, 65, 77, 36, 69, 60, 73, 65, 77, 52, 81 8985 }; 8986 static uint32 tr3_tdm_195[] = { /* 48xGE + 1x40GE + 4xHG[42] */ 8987 1, 69, 57, 73, 65, 77, 13, 69, 57, 73, 65, 77, 5, 69, 57, 73, 65, 77, 25, 69, 57, 73, 65, 77, 41, 0, 8988 9, 69, 57, 73, 65, 77, 17, 69, 57, 73, 65, 77, 21, 69, 57, 73, 65, 77, 29, 69, 57, 73, 65, 77, 45, 81, 8989 2, 69, 57, 73, 65, 77, 14, 69, 57, 73, 65, 77, 33, 69, 57, 73, 65, 77, 26, 69, 57, 73, 65, 77, 49, 0, 8990 6, 69, 57, 73, 65, 77, 18, 69, 57, 73, 65, 77, 42, 69, 57, 73, 65, 77, 30, 69, 57, 73, 65, 77, 46, 81, 8991 10, 69, 57, 73, 65, 77, 22, 69, 57, 73, 65, 77, 37, 69, 57, 73, 65, 77, 34, 69, 57, 73, 65, 77, 50, 0, 8992 3, 69, 57, 73, 65, 77, 15, 69, 57, 73, 65, 77, 7, 69, 57, 73, 65, 77, 27, 69, 57, 73, 65, 77, 43, 81, 8993 11, 69, 57, 73, 65, 77, 19, 69, 57, 73, 65, 77, 23, 69, 57, 73, 65, 77, 31, 69, 57, 73, 65, 77, 47, 0, 8994 4, 69, 57, 73, 65, 77, 16, 69, 57, 73, 65, 77, 35, 69, 57, 73, 65, 77, 28, 69, 57, 73, 65, 77, 51, 81, 8995 8, 69, 57, 73, 65, 77, 20, 69, 57, 73, 65, 77, 44, 69, 57, 73, 65, 77, 32, 69, 57, 73, 65, 77, 48, -1, 8996 12, 69, 57, 73, 65, 77, 24, 69, 57, 73, 65, 77, 37, 69, 57, 73, 65, 77, 36, 69, 57, 73, 65, 77, 52, 81 8997 }; 8998 static uint32 tr3_tdm_295[] = { /* 48xGE + 4xXFI + 1xHG[127] */ 8999 1, 69, 57, 69, -1, 69, 13, 69, 58, 69, -1, 69, 5, 69, 59, 69, -1, 69, 25, 69, 60, 69, -1, 69, 41, 0, 9000 9, 69, 57, 69, -1, 69, 17, 69, 58, 69, -1, 69, 21, 69, 59, 69, -1, 69, 29, 69, 60, 69, -1, 69, 45, 81, 9001 2, 69, 57, 69, -1, 69, 14, 69, 58, 69, -1, 69, 33, 69, 59, 69, -1, 69, 26, 69, 60, 69, -1, 69, 49, 0, 9002 6, 69, 57, 69, -1, 69, 18, 69, 58, 69, -1, 69, 42, 69, 59, 69, -1, 69, 30, 69, 60, 69, -1, 69, 46, 81, 9003 10, 69, 57, 69, -1, 69, 22, 69, 58, 69, -1, 69, 37, 69, 59, 69, -1, 69, 34, 69, 60, 69, -1, 69, 50, 0, 9004 3, 69, 57, 69, -1, 69, 15, 69, 58, 69, -1, 69, 7, 69, 59, 69, -1, 69, 27, 69, 60, 69, -1, 69, 43, 81, 9005 11, 69, 57, 69, -1, 69, 19, 69, 58, 69, -1, 69, 23, 69, 59, 69, -1, 69, 31, 69, 60, 69, -1, 69, 47, 0, 9006 4, 69, 57, 69, -1, 69, 16, 69, 58, 69, -1, 69, 35, 69, 59, 69, -1, 69, 28, 69, 60, 69, -1, 69, 51, 81, 9007 8, 69, 57, 69, -1, 69, 20, 69, 58, 69, -1, 69, 44, 69, 59, 69, -1, 69, 32, 69, 60, 69, -1, 69, 48, -1, 9008 12, 69, 57, 69, -1, 69, 24, 69, 58, 69, -1, 69, 37, 69, 59, 69, -1, 69, 36, 69, 60, 69, -1, 69, 52, 81 9009 }; 9010 static uint32 tr3_tdm_395[] = { /* 28xGE + 4xXFI + 4xHG[42] */ 9011 -1, 69, 57, 73, 65, 77, 13, 69, 58, 73, 65, 77, -1, 69, 59, 73, 65, 77, 25, 69, 60, 73, 65, 77, -1, 0, 9012 9, 69, 57, 73, 65, 77, 17, 69, 58, 73, 65, 77, 21, 69, 59, 73, 65, 77, 29, 69, 60, 73, 65, 77, -1, 81, 9013 -1, 69, 57, 73, 65, 77, 14, 69, 58, 73, 65, 77, 33, 69, 59, 73, 65, 77, 26, 69, 60, 73, 65, 77, -1, 0, 9014 -1, 69, 57, 73, 65, 77, 18, 69, 58, 73, 65, 77, -1, 69, 59, 73, 65, 77, 30, 69, 60, 73, 65, 77, -1, 81, 9015 10, 69, 57, 73, 65, 77, 22, 69, 58, 73, 65, 77, 37, 69, 59, 73, 65, 77, 34, 69, 60, 73, 65, 77, -1, 0, 9016 -1, 69, 57, 73, 65, 77, 15, 69, 58, 73, 65, 77, -1, 69, 59, 73, 65, 77, 27, 69, 60, 73, 65, 77, -1, 81, 9017 11, 69, 57, 73, 65, 77, 19, 69, 58, 73, 65, 77, 23, 69, 59, 73, 65, 77, 31, 69, 60, 73, 65, 77, -1, 0, 9018 -1, 69, 57, 73, 65, 77, 16, 69, 58, 73, 65, 77, 35, 69, 59, 73, 65, 77, 28, 69, 60, 73, 65, 77, -1, 81, 9019 -1, 69, 57, 73, 65, 77, 20, 69, 58, 73, 65, 77, -1, 69, 59, 73, 65, 77, 32, 69, 60, 73, 65, 77, -1, -1, 9020 12, 69, 57, 73, 65, 77, 24, 69, 58, 73, 65, 77, 37, 69, 59, 73, 65, 77, 36, 69, 60, 73, 65, 77, -1, 81 9021 }; 9022 static uint32 tr3_tdm_495[] = { /* 28xGE + 1x40GE + 4xHG[42] */ 9023 -1, 69, 57, 73, 65, 77, 13, 69, 57, 73, 65, 77, -1, 69, 57, 73, 65, 77, 25, 69, 57, 73, 65, 77, -1, 0, 9024 9, 69, 57, 73, 65, 77, 17, 69, 57, 73, 65, 77, 21, 69, 57, 73, 65, 77, 29, 69, 57, 73, 65, 77, -1, 81, 9025 -1, 69, 57, 73, 65, 77, 14, 69, 57, 73, 65, 77, 33, 69, 57, 73, 65, 77, 26, 69, 57, 73, 65, 77, -1, 0, 9026 -1, 69, 57, 73, 65, 77, 18, 69, 57, 73, 65, 77, -1, 69, 57, 73, 65, 77, 30, 69, 57, 73, 65, 77, -1, 81, 9027 10, 69, 57, 73, 65, 77, 22, 69, 57, 73, 65, 77, 37, 69, 57, 73, 65, 77, 34, 69, 57, 73, 65, 77, -1, 0, 9028 -1, 69, 57, 73, 65, 77, 15, 69, 57, 73, 65, 77, -1, 69, 57, 73, 65, 77, 27, 69, 57, 73, 65, 77, -1, 81, 9029 11, 69, 57, 73, 65, 77, 19, 69, 57, 73, 65, 77, 23, 69, 57, 73, 65, 77, 31, 69, 57, 73, 65, 77, -1, 0, 9030 -1, 69, 57, 73, 65, 77, 16, 69, 57, 73, 65, 77, 35, 69, 57, 73, 65, 77, 28, 69, 57, 73, 65, 77, -1, 81, 9031 -1, 69, 57, 73, 65, 77, 20, 69, 57, 73, 65, 77, -1, 69, 57, 73, 65, 77, 32, 69, 57, 73, 65, 77, -1, -1, 9032 12, 69, 57, 73, 65, 77, 24, 69, 57, 73, 65, 77, 37, 69, 57, 73, 65, 77, 36, 69, 57, 73, 65, 77, -1, 81 9033 }; 9034 static uint32 tr3_tdm_96[] = { /* FB3_1G_200_XFI */ 9035 57, 81, 61, 1, 13, 58, 81, 62, 25, 41, 59, 81, 63, 0, 60, 81, 5, 64, -1, 9036 57, 81, 61, 9, 17, 58, 81, 62, 29, 45, 59, 81, 63, 0, 60, 81, 21, 64, -1, 9037 57, 81, 61, 2, 14, 58, 81, 62, 33, 49, 59, 81, 63, 0, 60, 81, 26, 64, -1, 9038 57, 81, 61, 6, 18, 58, 81, 62, 30, 42, 59, 81, 63, 0, 60, 81, 46, 64, -1, 9039 57, 81, 61, 10, 22, 58, 81, 62, 34, 50, 59, 81, 63, 0, 60, 81, 37, 64, -1, 9040 57, 81, 61, 3, 15, 58, 81, 62, 27, 43, 59, 81, 63, 0, 60, 81, 7, 64, -1, 9041 57, 81, 61, 11, 19, 58, 81, 62, 31, 47, 59, 81, 63, 0, 60, 81, 23, 64, -1, 9042 57, 81, 61, 4, 16, 58, 81, 62, 35, 51, 59, 81, 63, 0, 60, 81, 28, 64, -1, 9043 57, 81, 61, 8, 20, 58, 81, 62, 32, 44, 59, 81, 63, 0, 60, 81, 48, 64, -1, 9044 57, 81, 61, 12, 24, 58, 81, 62, 36, 52, 59, 81, 63, 0, 60, 81, 37, 64, -1 9045 }; 9046 static uint32 tr3_tdm_196[] = { /* 28xGE + 8xXFI + 1GE */ 9047 57, 81, 61, -1, 13, 58, 81, 62, 25, -1, 59, 81, 63, 0, 60, 81, -1, 64, -1, 9048 57, 81, 61, 9, 17, 58, 81, 62, 29, -1, 59, 81, 63, 0, 60, 81, 21, 64, -1, 9049 57, 81, 61, -1, 14, 58, 81, 62, 33, -1, 59, 81, 63, 0, 60, 81, 26, 64, -1, 9050 57, 81, 61, -1, 18, 58, 81, 62, 30, -1, 59, 81, 63, 0, 60, 81, -1, 64, -1, 9051 57, 81, 61, 10, 22, 58, 81, 62, 34, -1, 59, 81, 63, 0, 60, 81, 37, 64, -1, 9052 57, 81, 61, -1, 15, 58, 81, 62, 27, -1, 59, 81, 63, 0, 60, 81, -1, 64, -1, 9053 57, 81, 61, 11, 19, 58, 81, 62, 31, -1, 59, 81, 63, 0, 60, 81, 23, 64, -1, 9054 57, 81, 61, -1, 16, 58, 81, 62, 35, -1, 59, 81, 63, 0, 60, 81, 28, 64, -1, 9055 57, 81, 61, -1, 20, 58, 81, 62, 32, -1, 59, 81, 63, 0, 60, 81, -1, 64, -1, 9056 57, 81, 61, 12, 24, 58, 81, 62, 36, -1, 59, 81, 63, 0, 60, 81, 37, 64, -1 9057 }; 9058 static uint32 tr3_tdm_97[] = { /* 10xF.XAUI + 4xXFI */ 9059 57, 1, -1, 13, 58, 25, 81, 5, 59, 17, 81, 29, 49, 60, 9, -1, 21, 33, 81, 9060 57, 1, -1, 13, 58, 25, 81, 5, 59, 17, 81, 29, 49, 60, 9, -1, 21, 33, 0, 9061 57, 1, -1, 13, 58, 25, 81, 5, 59, 17, 81, 29, 49, 60, 9, -1, 21, 33, 37, 9062 57, 1, -1, 13, 58, 25, 81, 5, 59, 17, 81, 29, 49, 60, 9, -1, 21, 33, 0, 9063 57, 1, -1, 13, 58, 25, 81, 5, 59, 17, 81, 29, 49, 60, 9, -1, 21, 33, -1, 9064 57, 1, -1, 13, 58, 25, 81, 5, 59, 17, 81, 29, 49, 60, 9, -1, 21, 33, 81, 9065 57, 1, -1, 13, 58, 25, 81, 5, 59, 17, 81, 29, 49, 60, 9, -1, 21, 33, 0, 9066 57, 1, -1, 13, 58, 25, 81, 5, 59, 17, 81, 29, 49, 60, 9, -1, 21, 33, 37, 9067 57, 1, -1, 13, 58, 25, 81, 5, 59, 17, 81, 29, 49, 60, 9, -1, 21, 33, 0, 9068 57, 1, -1, 13, 58, 25, 81, 5, 59, 17, 81, 29, 49, 60, 9, -1, 21, 33, -1, 9069 57, 1, -1, 13, 58, 25, 81, 5, 59, 17, 81, 29, 49, 60, 9, -1, 21, 33, 81, 9070 57, 1, -1, 13, 58, 25, 81, 5, 59, 17, 81, 29, 49, 60, 9, -1, 21, 33, 0, 9071 57, 1, -1, 13, 58, 25, 81, 5, 59, 17, 81, 29, 49, 60, 9, -1, 21, 33, 37, 9072 57, 1, -1, 13, 58, 25, 81, 5, 59, 17, 81, 29, 49, 60, 9, -1, 21, 33, 0, 9073 57, 1, -1, 13, 58, 25, 81, 5, 59, 17, 81, 29, 49, 60, 9, -1, 21, 33, -1, 9074 57, 1, -1, 13, 58, 25, 81, 5, 59, 17, 81, 29, 49, 60, 9, -1, 21, 33, 81, 9075 57, 1, -1, 13, 58, 25, 81, 5, 59, 17, 81, 29, 49, 60, 9, -1, 21, 33, 0, 9076 57, 1, -1, 13, 58, 25, 81, 5, 59, 17, 81, 29, 49, 60, 9, -1, 21, 33, 37, 9077 57, 1, -1, 13, 58, 25, 81, 5, 59, 17, 81, 29, 49, 60, 9, -1, 21, 33, 0, 9078 57, 1, -1, 13, 58, 25, 81, 5, 59, 17, 81, 29, 49, 60, 9, -1, 21, 33, -1 9079 }; 9080 static _soc_tr3_flex_tdm_inf_t flex_tr3_tdm_97 = { 9081 1, 9082 { 76, 76, 76, 76, 76, 76, 76, 76, 76, 76 }, 9083 { 1, 7, 14, 3, 9, 16, 5, 11, 17, 12 }, 9084 { 19, 19, 19, 19, 19, 19, 19, 19, 19, 19 } 9085 }; 9086 static uint32 tr3_tdm_98[] = { /* 10xF.XAUI + 2xHG[42] */ 9087 57, 81, 1, 61, 13, 57, 25, 61, 5, 57, 17, 61, 29, 49, 57, 9, 61, 21, 33, 9088 57, 0, 1, 61, 13, 57, 25, 61, 5, 57, 17, 61, 29, 49, 57, 9, 61, 21, 33, 9089 57, 37, 1, 61, 13, 57, 25, 61, 5, 57, 17, 61, 29, 49, 57, 9, 61, 21, 33, 9090 57, 0, 1, 61, 13, 57, 25, 61, 5, 57, 17, 61, 29, 49, 57, 9, 61, 21, 33, 9091 57, -1, 1, 61, 13, 57, 25, 61, 5, 57, 17, 61, 29, 49, 57, 9, 61, 21, 33, 9092 57, 81, 1, 61, 13, 57, 25, 61, 5, 57, 17, 61, 29, 49, 57, 9, 61, 21, 33, 9093 57, 0, 1, 61, 13, 57, 25, 61, 5, 57, 17, 61, 29, 49, 57, 9, 61, 21, 33, 9094 57, 37, 1, 61, 13, 57, 25, 61, 5, 57, 17, 61, 29, 49, 57, 9, 61, 21, 33, 9095 57, 0, 1, 61, 13, 57, 25, 61, 5, 57, 17, 61, 29, 49, 57, 9, 61, 21, 33, 9096 57, -1, 1, 61, 13, 57, 25, 61, 5, 57, 17, 61, 29, 49, 57, 9, 61, 21, 33, 9097 57, 81, 1, 61, 13, 57, 25, 61, 5, 57, 17, 61, 29, 49, 57, 9, 61, 21, 33, 9098 57, 0, 1, 61, 13, 57, 25, 61, 5, 57, 17, 61, 29, 49, 57, 9, 61, 21, 33, 9099 57, 37, 1, 61, 13, 57, 25, 61, 5, 57, 17, 61, 29, 49, 57, 9, 61, 21, 33, 9100 57, 0, 1, 61, 13, 57, 25, 61, 5, 57, 17, 61, 29, 49, 57, 9, 61, 21, 33, 9101 57, -1, 1, 61, 13, 57, 25, 61, 5, 57, 17, 61, 29, 49, 57, 9, 61, 21, 33, 9102 57, 81, 1, 61, 13, 57, 25, 61, 5, 57, 17, 61, 29, 49, 57, 9, 61, 21, 33, 9103 57, 0, 1, 61, 13, 57, 25, 61, 5, 57, 17, 61, 29, 49, 57, 9, 61, 21, 33, 9104 57, 37, 1, 61, 13, 57, 25, 61, 5, 57, 17, 61, 29, 49, 57, 9, 61, 21, 33, 9105 57, 0, 1, 61, 13, 57, 25, 61, 5, 57, 17, 61, 29, 49, 57, 9, 61, 21, 33, 9106 57, -1, 1, 61, 13, 57, 25, 61, 5, 57, 17, 61, 29, 49, 57, 9, 61, 21, 33 9107 }; 9108 static _soc_tr3_flex_tdm_inf_t flex_tr3_tdm_98 = { 9109 1, 9110 { 76, 76, 76, 76, 76, 76, 76, 76, 76, 76 }, 9111 { 2, 8, 15, 4, 10, 17, 6, 12, 18, 13 }, 9112 { 19, 19, 19, 19, 19, 19, 19, 19, 19, 19 } 9113 }; 9114 static uint32 tr3_tdm_99[] = { /* 24xGE + 4xXAUI + 2xXFI + 2xHG[12] + 1GE */ 9115 57, 1, 73, 13, 81, 25, 77, 5, 58, 17, 73, 29, 49, 0, 9, 77, 21, 33, -1, 9116 57, 2, 73, 14, 81, 25, 77, 6, 58, 18, 73, 29, 49, 0, 10, 77, 22, 33, -1, 9117 57, 3, 73, 15, 81, 25, 77, 7, 58, 19, 73, 29, 49, 0, 11, 77, 23, 33, -1, 9118 57, 4, 73, 16, 81, 25, 77, 8, 58, 20, 73, 29, 49, 0, 12, 77, 24, 33, -1, 9119 57, 1, 73, 13, 81, 25, 77, 5, 58, 17, 73, 29, 49, 37, 9, 77, 21, 33, -1, 9120 57, 2, 73, 14, 81, 25, 77, 6, 58, 18, 73, 29, 49, 0, 10, 77, 22, 33, -1, 9121 57, 3, 73, 15, 81, 25, 77, 7, 58, 19, 73, 29, 49, 0, 11, 77, 23, 33, -1, 9122 57, 4, 73, 16, 81, 25, 77, 8, 58, 20, 73, 29, 49, 0, 12, 77, 24, 33, -1, 9123 57, 1, 73, 13, 81, 25, 77, 5, 58, 17, 73, 29, 49, 0, 9, 77, 21, 33, -1, 9124 57, 2, 73, 14, 81, 25, 77, 6, 58, 18, 73, 29, 49, 37, 10, 77, 22, 33, -1, 9125 57, 3, 73, 15, 81, 25, 77, 7, 58, 19, 73, 29, 49, 0, 11, 77, 23, 33, -1, 9126 57, 4, 73, 16, 81, 25, 77, 8, 58, 20, 73, 29, 49, 0, 12, 77, 24, 33, -1, 9127 57, 1, 73, 13, 81, 25, 77, 5, 58, 17, 73, 29, 49, 0, 9, 77, 21, 33, -1, 9128 57, 2, 73, 14, 81, 25, 77, 6, 58, 18, 73, 29, 49, 0, 10, 77, 22, 33, -1, 9129 57, 3, 73, 15, 81, 25, 77, 7, 58, 19, 73, 29, 49, 37, 11, 77, 23, 33, -1, 9130 57, 4, 73, 16, 81, 25, 77, 8, 58, 20, 73, 29, 49, 0, 12, 77, 24, 33, -1, 9131 57, 1, 73, 13, 81, 25, 77, 5, 58, 17, 73, 29, 49, 0, 9, 77, 21, 33, -1, 9132 57, 2, 73, 14, 81, 25, 77, 6, 58, 18, 73, 29, 49, 0, 10, 77, 22, 33, -1, 9133 57, 3, 73, 15, 81, 25, 77, 7, 58, 19, 73, 29, 49, 0, 11, 77, 23, 33, -1, 9134 57, 4, 73, 16, 81, 25, 77, 8, 58, 20, 73, 29, 49, 37, 12, 77, 24, 33, -1 9135 }; 9136 static uint32 tr3_tdm_100[] = { /* TR3_1G_280_FX */ 9137 1, 69, 57, 73, 65, 77, 13, 69, 58, 73, 65, 77, 5, 69, 59, 73, 65, 77, 25, 69, 60, 73, 65, 77, -1, 0, 9138 9, 69, 57, 73, 65, 77, 17, 69, 58, 73, 65, 77, 21, 69, 59, 73, 65, 77, 29, 69, 60, 73, 65, 77, -1, 81, 9139 2, 69, 57, 73, 65, 77, 14, 69, 58, 73, 65, 77, 33, 69, 59, 73, 65, 77, 26, 69, 60, 73, 65, 77, -1, 0, 9140 6, 69, 57, 73, 65, 77, 18, 69, 58, 73, 65, 77, -1, 69, 59, 73, 65, 77, 30, 69, 60, 73, 65, 77, -1, 81, 9141 10, 69, 57, 73, 65, 77, 22, 69, 58, 73, 65, 77, 37, 69, 59, 73, 65, 77, 34, 69, 60, 73, 65, 77, -1, 0, 9142 3, 69, 57, 73, 65, 77, 15, 69, 58, 73, 65, 77, 7, 69, 59, 73, 65, 77, 27, 69, 60, 73, 65, 77, -1, 81, 9143 11, 69, 57, 73, 65, 77, 19, 69, 58, 73, 65, 77, 23, 69, 59, 73, 65, 77, 31, 69, 60, 73, 65, 77, -1, 0, 9144 4, 69, 57, 73, 65, 77, 16, 69, 58, 73, 65, 77, 35, 69, 59, 73, 65, 77, 28, 69, 60, 73, 65, 77, -1, 81, 9145 8, 69, 57, 73, 65, 77, 20, 69, 58, 73, 65, 77, -1, 69, 59, 73, 65, 77, 32, 69, 60, 73, 65, 77, -1, -1, 9146 12, 69, 57, 73, 65, 77, 24, 69, 58, 73, 65, 77, 37, 69, 59, 73, 65, 77, 36, 69, 60, 73, 65, 77, -1, 81 9147 }; 9148 static _soc_tr3_flex_tdm_inf_t flex_tr3_tdm_100 = { 9149 1, 9150 { 26, 26 }, 9151 { 3, 5 }, 9152 { 6, 6 } 9153 }; 9154 static uint32 tr3_tdm_101[] = { /* 28xGE + 4xXFI + 2xF.HG[42] + 2xHG[42] + 1GE */ 9155 -1, 69, 57, 73, 65, 77, 13, 69, 58, 73, 65, 77, -1, 69, 59, 73, 65, 77, 25, 69, 60, 73, 65, 77, -1, 0, 9156 9, 69, 57, 73, 65, 77, 17, 69, 58, 73, 65, 77, 21, 69, 59, 73, 65, 77, 29, 69, 60, 73, 65, 77, -1, 81, 9157 -1, 69, 57, 73, 65, 77, 14, 69, 58, 73, 65, 77, 33, 69, 59, 73, 65, 77, 26, 69, 60, 73, 65, 77, -1, 0, 9158 -1, 69, 57, 73, 65, 77, 18, 69, 58, 73, 65, 77, -1, 69, 59, 73, 65, 77, 30, 69, 60, 73, 65, 77, -1, 81, 9159 10, 69, 57, 73, 65, 77, 22, 69, 58, 73, 65, 77, 37, 69, 59, 73, 65, 77, 34, 69, 60, 73, 65, 77, -1, 0, 9160 -1, 69, 57, 73, 65, 77, 15, 69, 58, 73, 65, 77, -1, 69, 59, 73, 65, 77, 27, 69, 60, 73, 65, 77, -1, 81, 9161 11, 69, 57, 73, 65, 77, 19, 69, 58, 73, 65, 77, 23, 69, 59, 73, 65, 77, 31, 69, 60, 73, 65, 77, -1, 0, 9162 -1, 69, 57, 73, 65, 77, 16, 69, 58, 73, 65, 77, 35, 69, 59, 73, 65, 77, 28, 69, 60, 73, 65, 77, -1, 81, 9163 -1, 69, 57, 73, 65, 77, 20, 69, 58, 73, 65, 77, -1, 69, 59, 73, 65, 77, 32, 69, 60, 73, 65, 77, -1, -1, 9164 12, 69, 57, 73, 65, 77, 24, 69, 58, 73, 65, 77, 37, 69, 59, 73, 65, 77, 36, 69, 60, 73, 65, 77, -1, 81 9165 }; 9166 static _soc_tr3_flex_tdm_inf_t flex_tr3_tdm_102 = { 9167 1, 9168 { 26, 26 }, 9169 { 4, 1 }, 9170 { 6, 6 } 9171 }; 9172 static uint32 tr3_tdm_103[] = { /* 48xGE + 4xXFI + 2xHG[42] + 1GE */ 9173 57, 1, 73, 13 ,77, 25, 58, 41, 73, 5, 77, 17, 59, 29, 73, 45, 77, 81, 9174 60, 9, 73, 21 ,77, 33, 57, 49, 73, 2, 77, 14, 58, 26, 73, 42, 77, 0, 9175 59, 6, 73, 18 ,77, 30, 60, 46, 73, 10, 77, 22, 57, 34, 73, 50, 77, 81, 9176 58, 3, 73, 15 ,77, 27, 59, 43, 73, 7, 77, 19, 60, 31, 73, 47, 77, 0, 9177 57, 11, 73, 23 ,77, 35, 58, 51, 73, 4, 77, 16, 59, 28, 73, 44, 77, 81, 9178 60, 8, 73, 20 ,77, 32, 57, 48, -1, 12, 77, 24, 58, 36, 73, 52, 37, 81, 9179 59, 1, 73, 13 ,77, 25, 60, 41, 73, 5, 77, 17, 57, 29, 73, 45, 77, 81, 9180 58, 9, 73, 21 ,77, 33, 59, 49, 73, 2, 77, 14, 60, 26, 73, 42, 77, 0, 9181 57, 6, 73, 18 ,77, 30, 58, 46, 73, 10, 77, 22, 59, 34, 73, 50, 77, 81, 9182 60, 3, 73, 15 ,77, 27, 57, 43, 73, 7, 77, 19, 58, 31, 73, 47, 77, 0, 9183 59, 11, 73, 23 ,77, 35, 60, 51, 73, 4, 77, 16, 57, 28, 73, 44, 77, 81, 9184 58, 8, 73, 20 ,77, 32, 59, 48, -1, 12, 77, 24, 60, 36, 73, 52, 37, 81, 9185 }; 9186 static uint32 tr3_tdm_203[] = { /* 48xGE + 1xHG[40] + 2xHG[42] + 1GE */ 9187 57, 1, 73, 13 ,77, 25, 57, 41, 73, 5, 77, 17, 57, 29, 73, 45, 77, 81, 9188 57, 9, 73, 21 ,77, 33, 57, 49, 73, 2, 77, 14, 57, 26, 73, 42, 77, 0, 9189 57, 6, 73, 18 ,77, 30, 57, 46, 73, 10, 77, 22, 57, 34, 73, 50, 77, 81, 9190 57, 3, 73, 15 ,77, 27, 57, 43, 73, 7, 77, 19, 57, 31, 73, 47, 77, 0, 9191 57, 11, 73, 23 ,77, 35, 57, 51, 73, 4, 77, 16, 57, 28, 73, 44, 77, 81, 9192 57, 8, 73, 20 ,77, 32, 57, 48, -1, 12, 77, 24, 57, 36, 73, 52, 37, 81, 9193 57, 1, 73, 13 ,77, 25, 57, 41, 73, 5, 77, 17, 57, 29, 73, 45, 77, 81, 9194 57, 9, 73, 21 ,77, 33, 57, 49, 73, 2, 77, 14, 57, 26, 73, 42, 77, 0, 9195 57, 6, 73, 18 ,77, 30, 57, 46, 73, 10, 77, 22, 57, 34, 73, 50, 77, 81, 9196 57, 3, 73, 15 ,77, 27, 57, 43, 73, 7, 77, 19, 57, 31, 73, 47, 77, 0, 9197 57, 11, 73, 23 ,77, 35, 57, 51, 73, 4, 77, 16, 57, 28, 73, 44, 77, 81, 9198 57, 8, 73, 20 ,77, 32, 57, 48, -1, 12, 77, 24, 57, 36, 73, 52, 37, 81, 9199 }; 9200 static uint32 tr3_tdm_303[] = { /* 28xGE + 4xXFI + 2xHG[42] + 1GE */ 9201 57, -1, 73, 13, 77, 25, 58, -1, 73, -1, 77, 17, 59, 29, 73, -1, 77, 81, 9202 60, 9, 73, 21, 77, 33, 57, -1, 73, -1, 77, 14, 58, 26, 73, -1, 77, 0, 9203 59, -1, 73, 18, 77, 30, 60, -1, 73, 10, 77, 22, 57, 34, 73, -1, 77, 81, 9204 58, -1, 73, 15, 77, 27, 59, -1, 73, -1, 77, 19, 60, 31, 73, -1, 77, 0, 9205 57, 11, 73, 23, 77, 35, 58, -1, 73, -1, 77, 16, 59, 28, 73, -1, 77, 81, 9206 60, -1, 73, 20, 77, 32, 57, -1, -1, 12, 77, 24, 58, 36, 73, -1, 37, 81, 9207 59, -1, 73, 13, 77, 25, 60, -1, 73, -1, 77, 17, 57, 29, 73, -1, 77, 81, 9208 58, 9, 73, 21, 77, 33, 59, -1, 73, -1, 77, 14, 60, 26, 73, -1, 77, 0, 9209 57, -1, 73, 18, 77, 30, 58, -1, 73, 10, 77, 22, 59, 34, 73, -1, 77, 81, 9210 60, -1, 73, 15, 77, 27, 57, -1, 73, -1, 77, 19, 58, 31, 73, -1, 77, 0, 9211 59, 11, 73, 23, 77, 35, 60, -1, 73, -1, 77, 16, 57, 28, 73, -1, 77, 81, 9212 58, -1, 73, 20, 77, 32, 59, -1, -1, 12, 77, 24, 60, 36, 73, -1, 37, 81, 9213 }; 9214 static uint32 tr3_tdm_403[] = { /* 28xGE + 1xHG[40] + 2xHG[42] + 1GE */ 9215 57, -1, 73, 13, 77, 25, 57, -1, 73, -1, 77, 17, 57, 29, 73, -1, 77, 81, 9216 57, 9, 73, 21, 77, 33, 57, -1, 73, -1, 77, 14, 57, 26, 73, -1, 77, 0, 9217 57, -1, 73, 18, 77, 30, 57, -1, 73, 10, 77, 22, 57, 34, 73, -1, 77, 81, 9218 57, -1, 73, 15, 77, 27, 57, -1, 73, -1, 77, 19, 57, 31, 73, -1, 77, 0, 9219 57, 11, 73, 23, 77, 35, 57, -1, 73, -1, 77, 16, 57, 28, 73, -1, 77, 81, 9220 57, -1, 73, 20, 77, 32, 57, -1, -1, 12, 77, 24, 57, 36, 73, -1, 37, 81, 9221 57, -1, 73, 13, 77, 25, 57, -1, 73, -1, 77, 17, 57, 29, 73, -1, 77, 81, 9222 57, 9, 73, 21, 77, 33, 57, -1, 73, -1, 77, 14, 57, 26, 73, -1, 77, 0, 9223 57, -1, 73, 18, 77, 30, 57, -1, 73, 10, 77, 22, 57, 34, 73, -1, 77, 81, 9224 57, -1, 73, 15, 77, 27, 57, -1, 73, -1, 77, 19, 57, 31, 73, -1, 77, 0, 9225 57, 11, 73, 23, 77, 35, 57, -1, 73, -1, 77, 16, 57, 28, 73, -1, 77, 81, 9226 57, -1, 73, 20, 77, 32, 57, -1, -1, 12, 77, 24, 57, 36, 73, -1, 37, 81, 9227 }; 9228 9229 9230 soc_info_t *si; 9231 int i; 9232 iarb_tdm_table_entry_t iarb_tdm; 9233 lls_port_tdm_entry_t lls_tdm; 9234 uint32 rval, tdmv; 9235 int port = -1; 9236 9237 _soc_tr3_flex_tdm.valid = 0; 9238 #ifdef BCM_HELIX4_SUPPORT 9239 if (SOC_IS_HELIX4(unit)) { 9240 _soc_hx4_mmu_tdm_array_init(unit); 9241 } else 9242 #endif 9243 { 9244 switch (_tr3_port_config_id[unit]) { 9245 case 10: 9246 _soc_tr3_tdm_size = COUNTOF(tr3_tdm_10); 9247 sal_memcpy(&_soc_tr3_tdm_arr, &tr3_tdm_10, sizeof(uint32) * _soc_tr3_tdm_size); 9248 break; 9249 case 110: 9250 _soc_tr3_tdm_size = COUNTOF(tr3_tdm_110); 9251 sal_memcpy(&_soc_tr3_tdm_arr, &tr3_tdm_110, sizeof(uint32) * _soc_tr3_tdm_size); 9252 break; 9253 case 11: 9254 _soc_tr3_tdm_size = COUNTOF(tr3_tdm_11); 9255 sal_memcpy(&_soc_tr3_tdm_arr, &tr3_tdm_11, sizeof(uint32) * _soc_tr3_tdm_size); 9256 break; 9257 case 12: 9258 _soc_tr3_tdm_size = COUNTOF(tr3_tdm_12); 9259 sal_memcpy(&_soc_tr3_tdm_arr, &tr3_tdm_12, sizeof(uint32) * _soc_tr3_tdm_size); 9260 _soc_tr3_flex_tdm = flex_tr3_tdm_112; 9261 break; 9262 case 112: 9263 _soc_tr3_tdm_size = COUNTOF(tr3_tdm_112); 9264 sal_memcpy(&_soc_tr3_tdm_arr, &tr3_tdm_112, sizeof(uint32) * _soc_tr3_tdm_size); 9265 _soc_tr3_flex_tdm = flex_tr3_tdm_112; 9266 break; 9267 case 35: 9268 _soc_tr3_tdm_size = COUNTOF(tr3_tdm_35); 9269 sal_memcpy(&_soc_tr3_tdm_arr, &tr3_tdm_35, sizeof(uint32) * _soc_tr3_tdm_size); 9270 break; 9271 case 36: 9272 _soc_tr3_tdm_size = COUNTOF(tr3_tdm_36); 9273 sal_memcpy(&_soc_tr3_tdm_arr, &tr3_tdm_36, sizeof(uint32) * _soc_tr3_tdm_size); 9274 break; 9275 case 37: 9276 _soc_tr3_tdm_size = COUNTOF(tr3_tdm_37); 9277 sal_memcpy(&_soc_tr3_tdm_arr, &tr3_tdm_37, sizeof(uint32) * _soc_tr3_tdm_size); 9278 _soc_tr3_flex_tdm = flex_tr3_tdm_37; 9279 break; 9280 case 38: 9281 _soc_tr3_tdm_size = COUNTOF(tr3_tdm_38); 9282 sal_memcpy(&_soc_tr3_tdm_arr, &tr3_tdm_38, sizeof(uint32) * _soc_tr3_tdm_size); 9283 _soc_tr3_flex_tdm = flex_tr3_tdm_38; 9284 break; 9285 case 40: 9286 _soc_tr3_tdm_size = COUNTOF(tr3_tdm_40); 9287 sal_memcpy(&_soc_tr3_tdm_arr, &tr3_tdm_40, sizeof(uint32) * _soc_tr3_tdm_size); 9288 _soc_tr3_flex_tdm = flex_tr3_tdm_40; 9289 break; 9290 case 41: 9291 _soc_tr3_tdm_size = COUNTOF(tr3_tdm_41); 9292 sal_memcpy(&_soc_tr3_tdm_arr, &tr3_tdm_41, sizeof(uint32) * _soc_tr3_tdm_size); 9293 break; 9294 case 50: 9295 _soc_tr3_tdm_size = COUNTOF(tr3_tdm_50); 9296 sal_memcpy(&_soc_tr3_tdm_arr, &tr3_tdm_50, sizeof(uint32) * _soc_tr3_tdm_size); 9297 break; 9298 case 55: 9299 _soc_tr3_tdm_size = COUNTOF(tr3_tdm_55); 9300 sal_memcpy(&_soc_tr3_tdm_arr, &tr3_tdm_55, sizeof(uint32) * _soc_tr3_tdm_size); 9301 _soc_tr3_flex_tdm = flex_tr3_tdm_55; 9302 break; 9303 case 155: 9304 _soc_tr3_tdm_size = COUNTOF(tr3_tdm_155); 9305 sal_memcpy(&_soc_tr3_tdm_arr, &tr3_tdm_155, sizeof(uint32) * _soc_tr3_tdm_size); 9306 _soc_tr3_flex_tdm = flex_tr3_tdm_155; 9307 break; 9308 case 71: 9309 case 72: 9310 _soc_tr3_tdm_size = COUNTOF(tr3_tdm_71); 9311 sal_memcpy(&_soc_tr3_tdm_arr, &tr3_tdm_71, sizeof(uint32) * _soc_tr3_tdm_size); 9312 _soc_tr3_flex_tdm = flex_tr3_tdm_71; 9313 break; 9314 case 171: 9315 case 172: 9316 _soc_tr3_tdm_size = COUNTOF(tr3_tdm_171); 9317 sal_memcpy(&_soc_tr3_tdm_arr, &tr3_tdm_171, sizeof(uint32) * _soc_tr3_tdm_size); 9318 _soc_tr3_flex_tdm = flex_tr3_tdm_171; 9319 break; 9320 case 81: 9321 _soc_tr3_tdm_size = COUNTOF(tr3_tdm_81); 9322 sal_memcpy(&_soc_tr3_tdm_arr, &tr3_tdm_81, sizeof(uint32) * _soc_tr3_tdm_size); 9323 break; 9324 case 82: 9325 _soc_tr3_tdm_size = COUNTOF(tr3_tdm_82); 9326 sal_memcpy(&_soc_tr3_tdm_arr, &tr3_tdm_82, sizeof(uint32) * _soc_tr3_tdm_size); 9327 _soc_tr3_flex_tdm = flex_tr3_tdm_37; 9328 break; 9329 case 83: 9330 _soc_tr3_tdm_size = COUNTOF(tr3_tdm_83); 9331 sal_memcpy(&_soc_tr3_tdm_arr, &tr3_tdm_83, sizeof(uint32) * _soc_tr3_tdm_size); 9332 _soc_tr3_flex_tdm = flex_tr3_tdm_37; 9333 break; 9334 case 90: 9335 _soc_tr3_tdm_size = COUNTOF(tr3_tdm_90); 9336 sal_memcpy(&_soc_tr3_tdm_arr, &tr3_tdm_90, sizeof(uint32) * _soc_tr3_tdm_size); 9337 break; 9338 case 190: 9339 _soc_tr3_tdm_size = COUNTOF(tr3_tdm_190); 9340 sal_memcpy(&_soc_tr3_tdm_arr, &tr3_tdm_190, sizeof(uint32) * _soc_tr3_tdm_size); 9341 break; 9342 case 91: 9343 _soc_tr3_tdm_size = COUNTOF(tr3_tdm_91); 9344 sal_memcpy(&_soc_tr3_tdm_arr, &tr3_tdm_91, sizeof(uint32) * _soc_tr3_tdm_size); 9345 _soc_tr3_flex_tdm = flex_tr3_tdm_91; 9346 break; 9347 case 94: 9348 _soc_tr3_tdm_size = COUNTOF(tr3_tdm_94); 9349 sal_memcpy(&_soc_tr3_tdm_arr, &tr3_tdm_94, sizeof(uint32) * _soc_tr3_tdm_size); 9350 break; 9351 case 95: 9352 case 595: 9353 _soc_tr3_tdm_size = COUNTOF(tr3_tdm_95); 9354 sal_memcpy(&_soc_tr3_tdm_arr, &tr3_tdm_95, sizeof(uint32) * _soc_tr3_tdm_size); 9355 break; 9356 case 195: 9357 _soc_tr3_tdm_size = COUNTOF(tr3_tdm_195); 9358 sal_memcpy(&_soc_tr3_tdm_arr, &tr3_tdm_195, sizeof(uint32) * _soc_tr3_tdm_size); 9359 break; 9360 case 295: 9361 _soc_tr3_tdm_size = COUNTOF(tr3_tdm_295); 9362 sal_memcpy(&_soc_tr3_tdm_arr, &tr3_tdm_295, sizeof(uint32) * _soc_tr3_tdm_size); 9363 break; 9364 case 395: 9365 case 695: 9366 _soc_tr3_tdm_size = COUNTOF(tr3_tdm_395); 9367 sal_memcpy(&_soc_tr3_tdm_arr, &tr3_tdm_395, sizeof(uint32) * _soc_tr3_tdm_size); 9368 break; 9369 case 495: 9370 _soc_tr3_tdm_size = COUNTOF(tr3_tdm_495); 9371 sal_memcpy(&_soc_tr3_tdm_arr, &tr3_tdm_495, sizeof(uint32) * _soc_tr3_tdm_size); 9372 break; 9373 case 96: 9374 _soc_tr3_tdm_size = COUNTOF(tr3_tdm_96); 9375 sal_memcpy(&_soc_tr3_tdm_arr, &tr3_tdm_96, sizeof(uint32) * _soc_tr3_tdm_size); 9376 break; 9377 case 196: 9378 _soc_tr3_tdm_size = COUNTOF(tr3_tdm_196); 9379 sal_memcpy(&_soc_tr3_tdm_arr, &tr3_tdm_196, sizeof(uint32) * _soc_tr3_tdm_size); 9380 break; 9381 case 97: 9382 _soc_tr3_tdm_size = COUNTOF(tr3_tdm_97); 9383 sal_memcpy(&_soc_tr3_tdm_arr, &tr3_tdm_97, sizeof(uint32) * _soc_tr3_tdm_size); 9384 _soc_tr3_flex_tdm = flex_tr3_tdm_97; 9385 break; 9386 case 98: 9387 _soc_tr3_tdm_size = COUNTOF(tr3_tdm_98); 9388 sal_memcpy(&_soc_tr3_tdm_arr, &tr3_tdm_98, sizeof(uint32) * _soc_tr3_tdm_size); 9389 _soc_tr3_flex_tdm = flex_tr3_tdm_98; 9390 break; 9391 case 99: 9392 _soc_tr3_tdm_size = COUNTOF(tr3_tdm_99); 9393 sal_memcpy(&_soc_tr3_tdm_arr, &tr3_tdm_99, sizeof(uint32) * _soc_tr3_tdm_size); 9394 break; 9395 case 100: 9396 _soc_tr3_tdm_size = COUNTOF(tr3_tdm_100); 9397 sal_memcpy(&_soc_tr3_tdm_arr, &tr3_tdm_100, sizeof(uint32) * _soc_tr3_tdm_size); 9398 _soc_tr3_flex_tdm = flex_tr3_tdm_100; 9399 break; 9400 case 101: 9401 _soc_tr3_tdm_size = COUNTOF(tr3_tdm_101); 9402 sal_memcpy(&_soc_tr3_tdm_arr, &tr3_tdm_101, sizeof(uint32) * _soc_tr3_tdm_size); 9403 _soc_tr3_flex_tdm = flex_tr3_tdm_100; 9404 break; 9405 case 102: 9406 _soc_tr3_tdm_size = COUNTOF(tr3_tdm_100); 9407 sal_memcpy(&_soc_tr3_tdm_arr, &tr3_tdm_100, sizeof(uint32) * _soc_tr3_tdm_size); 9408 _soc_tr3_flex_tdm = flex_tr3_tdm_102; 9409 break; 9410 case 103: 9411 _soc_tr3_tdm_size = COUNTOF(tr3_tdm_103); 9412 sal_memcpy(&_soc_tr3_tdm_arr, &tr3_tdm_103, sizeof(uint32) * _soc_tr3_tdm_size); 9413 break; 9414 case 203: 9415 _soc_tr3_tdm_size = COUNTOF(tr3_tdm_203); 9416 sal_memcpy(&_soc_tr3_tdm_arr, &tr3_tdm_203, sizeof(uint32) * _soc_tr3_tdm_size); 9417 break; 9418 case 303: 9419 _soc_tr3_tdm_size = COUNTOF(tr3_tdm_303); 9420 sal_memcpy(&_soc_tr3_tdm_arr, &tr3_tdm_303, sizeof(uint32) * _soc_tr3_tdm_size); 9421 break; 9422 case 403: 9423 _soc_tr3_tdm_size = COUNTOF(tr3_tdm_403); 9424 sal_memcpy(&_soc_tr3_tdm_arr, &tr3_tdm_403, sizeof(uint32) * _soc_tr3_tdm_size); 9425 break; 9426 default: 9427 return SOC_E_PARAM; 9428 } 9429 } 9430 9431 si = &SOC_INFO(unit); 9432 assert(_soc_tr3_tdm_size); 9433 /* Disable IARB TDM before programming... */ 9434 SOC_IF_ERROR_RETURN(READ_IARB_TDM_CONTROLr(unit, &rval)); 9435 soc_reg_field_set(unit, IARB_TDM_CONTROLr, &rval, DISABLEf, 1); 9436 soc_reg_field_set(unit, IARB_TDM_CONTROLr, &rval, TDM_WRAP_PTRf, 9437 _soc_tr3_tdm_size -1); 9438 SOC_IF_ERROR_RETURN(WRITE_IARB_TDM_CONTROLr(unit, rval)); 9439 9440 if (_soc_tr3_flex_tdm.valid) { 9441 uint16 j, k, c; 9442 for (j = 0; j < _tr3_flex_port_data[unit].port_groups; j++) { 9443 LOG_VERBOSE(BSL_LS_SOC_COMMON, 9444 (BSL_META_U(unit, 9445 "base slot[port]: %d[%d]\n"), _soc_tr3_flex_tdm.base_slot[j], 9446 _soc_tr3_tdm_arr[_soc_tr3_flex_tdm.base_slot[j]])); 9447 if (!_soc_tr3_flex_tdm.cells_per_row[j]) { 9448 if (_tr3_flex_port_data[unit].ports[j] == 1) { 9449 for (i=_soc_tr3_flex_tdm.base_slot[j]+1; i < _soc_tr3_tdm_size; i+=1) { 9450 int port_group_range = 9451 _soc_tr3_tdm_arr[i] - _soc_tr3_tdm_arr[_soc_tr3_flex_tdm.base_slot[j]]; 9452 if (port_group_range > 0 && port_group_range <= 3) { 9453 LOG_VERBOSE(BSL_LS_SOC_COMMON, 9454 (BSL_META_U(unit, 9455 "arr[%d]: %d->%d\n"), i, _soc_tr3_tdm_arr[i], 9456 _soc_tr3_tdm_arr[_soc_tr3_flex_tdm.base_slot[j]])); 9457 _soc_tr3_tdm_arr[i] = _soc_tr3_tdm_arr[_soc_tr3_flex_tdm.base_slot[j]]; 9458 } 9459 } 9460 } 9461 continue; 9462 } 9463 for (i = 0; i < _soc_tr3_tdm_size; i+=_soc_tr3_flex_tdm.cells_per_row[j]) { 9464 for (k = _soc_tr3_flex_tdm.base_slot[j]; 9465 k < _soc_tr3_flex_tdm.cells_per_row[j]+_soc_tr3_flex_tdm.cell_offset[j]; 9466 k+=_soc_tr3_flex_tdm.cell_offset[j]) { 9467 c = k; 9468 /* Some exceptions to deal with slots not aligned on fixed multiples */ 9469 if (!SOC_IS_HELIX4(unit)) { 9470 /* TR3 only */ 9471 if ((_soc_tr3_flex_tdm.cells_per_row[j] == 25) && (k >= 24)) { 9472 continue; 9473 } 9474 if ((_soc_tr3_flex_tdm.cells_per_row[j] == 26) && (k >= 25)) { 9475 continue; 9476 } 9477 if (_tr3_port_config_id[unit] == 83) { 9478 if ((k / _soc_tr3_flex_tdm.cell_offset[j]) == 3) { 9479 c++; 9480 } 9481 } else if (_tr3_port_config_id[unit] == 40) { 9482 if ((j == 2) && ((k / _soc_tr3_flex_tdm.cell_offset[j]) == 3)) { 9483 c-=1; 9484 } 9485 if ((j == 4) && ((k / _soc_tr3_flex_tdm.cell_offset[j]) >= 2)) { 9486 c-=1; 9487 } 9488 if ((j == 5) && ((k / _soc_tr3_flex_tdm.cell_offset[j]) >= 2)) { 9489 c+=1; 9490 } 9491 } else if (_tr3_port_config_id[unit] == 112 || _tr3_port_config_id[unit] == 12) { 9492 if (((_soc_tr3_tdm_arr[_soc_tr3_flex_tdm.base_slot[j]] == 73) && 9493 ((k / _soc_tr3_flex_tdm.cell_offset[j]) >= 3))) { 9494 c-=1; 9495 } 9496 } 9497 } else { 9498 /* Helix4 specific */ 9499 if (_tr3_port_config_id[unit] == 490 || _tr3_port_config_id[unit] == 500 || 9500 _tr3_port_config_id[unit] == 495 || _tr3_port_config_id[unit] == 491 || 9501 _tr3_port_config_id[unit] == 514 || _tr3_port_config_id[unit] == 497 || 9502 _tr3_port_config_id[unit] == 510 || _tr3_port_config_id[unit] == 492) { 9503 if ((k / _soc_tr3_flex_tdm.cell_offset[j]) == 5) { 9504 c--; 9505 } 9506 if ((k / _soc_tr3_flex_tdm.cell_offset[j]) >= 6) { 9507 c-=2; 9508 } 9509 } else if (_tr3_port_config_id[unit] == 460 || 9510 _tr3_port_config_id[unit] == 462) { 9511 if ((k / _soc_tr3_flex_tdm.cell_offset[j]) >= 1) { 9512 c++; 9513 } 9514 } else if (_tr3_port_config_id[unit] == 464 || 9515 _tr3_port_config_id[unit] == 463 ) { 9516 if (_soc_tr3_flex_tdm.cell_offset[j] == 5) { 9517 c += (k/5 -1); 9518 } else if ((k / _soc_tr3_flex_tdm.cell_offset[j]) >= 1) { 9519 c++; 9520 } 9521 } else if (_tr3_port_config_id[unit] == 410 || 9522 _tr3_port_config_id[unit] == 420 || 9523 _tr3_port_config_id[unit] == 412 || 9524 _tr3_port_config_id[unit] == 413 || 9525 _tr3_port_config_id[unit] == 414) { 9526 if (((_tr3_port_config_id[unit] == 410)||(_tr3_port_config_id[unit] == 413)) && 9527 ((_soc_tr3_tdm_arr[_soc_tr3_flex_tdm.base_slot[j]] == 57) || 9528 (_soc_tr3_tdm_arr[_soc_tr3_flex_tdm.base_slot[j]] == 61))) { 9529 if ((_soc_tr3_tdm_arr[_soc_tr3_flex_tdm.base_slot[j]] == 57) && 9530 ((k / _soc_tr3_flex_tdm.cell_offset[j]) >= 2)) { 9531 c++; 9532 } 9533 } else { 9534 if ((k / _soc_tr3_flex_tdm.cell_offset[j]) >= 7) { 9535 c-=3; 9536 } else if ((k / _soc_tr3_flex_tdm.cell_offset[j]) >= 5) { 9537 c-=2; 9538 } else if ((k / _soc_tr3_flex_tdm.cell_offset[j]) >= 2) { 9539 c--; 9540 } 9541 } 9542 } else if (_tr3_port_config_id[unit] == 450) { 9543 if ((k / _soc_tr3_flex_tdm.cell_offset[j]) >= 6) { 9544 c-=2; 9545 } else if ((k / _soc_tr3_flex_tdm.cell_offset[j]) >= 2) { 9546 c--; 9547 } 9548 } else if (_tr3_port_config_id[unit] == 610) { 9549 if ((k / _soc_tr3_flex_tdm.cell_offset[j]) > 1 && 9550 (k / _soc_tr3_flex_tdm.cell_offset[j]) < 5) { 9551 c--; 9552 } else if ((k / _soc_tr3_flex_tdm.cell_offset[j]) == 7) { 9553 c-=3; 9554 } else if ((k / _soc_tr3_flex_tdm.cell_offset[j]) > 4) { 9555 c-=2; 9556 } 9557 } 9558 } 9559 if (c >= _soc_tr3_flex_tdm.cells_per_row[j]) { 9560 break; 9561 } 9562 switch (_tr3_flex_port_data[unit].ports[j]) { 9563 case 1: 9564 LOG_VERBOSE(BSL_LS_SOC_COMMON, 9565 (BSL_META_U(unit, 9566 "arr[%d]: %d->%d\n"), i+c, _soc_tr3_tdm_arr[i+c], 9567 _soc_tr3_tdm_arr[_soc_tr3_flex_tdm.base_slot[j]])); 9568 _soc_tr3_tdm_arr[i+c] = _soc_tr3_tdm_arr[_soc_tr3_flex_tdm.base_slot[j]]; 9569 break; 9570 case 2: 9571 LOG_VERBOSE(BSL_LS_SOC_COMMON, 9572 (BSL_META_U(unit, 9573 "arr[%d]: %d->%d\n"), i+c, _soc_tr3_tdm_arr[i+c], 9574 ((k / _soc_tr3_flex_tdm.cell_offset[j]) % 2) ? 9575 (_soc_tr3_tdm_arr[_soc_tr3_flex_tdm.base_slot[j]] + 2) : 9576 _soc_tr3_tdm_arr[_soc_tr3_flex_tdm.base_slot[j]])); 9577 if( ((413 == _tr3_port_config_id[unit])||(463 == _tr3_port_config_id[unit]))&& 9578 ((_soc_tr3_tdm_arr[_soc_tr3_flex_tdm.base_slot[j]] == 57)|| 9579 (_soc_tr3_tdm_arr[_soc_tr3_flex_tdm.base_slot[j]] == 61))){ 9580 _soc_tr3_tdm_arr[i+c] = _soc_tr3_tdm_arr[_soc_tr3_flex_tdm.base_slot[j]]; 9581 }else{ 9582 _soc_tr3_tdm_arr[i+c] = ((k / _soc_tr3_flex_tdm.cell_offset[j]) % 2) ? 9583 (_soc_tr3_tdm_arr[_soc_tr3_flex_tdm.base_slot[j]] + 2) : 9584 _soc_tr3_tdm_arr[_soc_tr3_flex_tdm.base_slot[j]]; 9585 } 9586 9587 break; 9588 case 4: 9589 if ((_tr3_port_config_id[unit] == 464) && 9590 (_soc_tr3_flex_tdm.cell_offset[j] == 9591 _soc_tr3_flex_tdm.base_slot[j])) { 9592 tdmv = _soc_tr3_tdm_arr[_soc_tr3_flex_tdm.base_slot[j]] + 9593 ((k-1) / _soc_tr3_flex_tdm.cell_offset[j] %4); 9594 } else if (_tr3_port_config_id[unit] == 463 ) { 9595 if(_soc_tr3_flex_tdm.cell_offset[j] == _soc_tr3_flex_tdm.base_slot[j]){ 9596 if ((_soc_tr3_tdm_arr[_soc_tr3_flex_tdm.base_slot[j]] == 57)|| 9597 (_soc_tr3_tdm_arr[_soc_tr3_flex_tdm.base_slot[j]] == 61)){ 9598 tdmv = _soc_tr3_tdm_arr[_soc_tr3_flex_tdm.base_slot[j]] + 9599 ((k-1) / _soc_tr3_flex_tdm.cell_offset[j] %2); 9600 }else{ 9601 tdmv = _soc_tr3_tdm_arr[_soc_tr3_flex_tdm.base_slot[j]] + 9602 ((k-1) / _soc_tr3_flex_tdm.cell_offset[j] %4); 9603 } 9604 } 9605 else { 9606 if ((_soc_tr3_tdm_arr[_soc_tr3_flex_tdm.base_slot[j]] == 57)|| 9607 (_soc_tr3_tdm_arr[_soc_tr3_flex_tdm.base_slot[j]] == 61)){ 9608 tdmv = _soc_tr3_tdm_arr[_soc_tr3_flex_tdm.base_slot[j]] + 9609 (k / _soc_tr3_flex_tdm.cell_offset[j] %2); 9610 }else{ 9611 tdmv = _soc_tr3_tdm_arr[_soc_tr3_flex_tdm.base_slot[j]] + 9612 (k / _soc_tr3_flex_tdm.cell_offset[j] %4); 9613 } 9614 } 9615 port = si->port_p2l_mapping[tdmv]; 9616 if (port == -1 ) { 9617 tdmv = -1; 9618 } 9619 }else if ((_tr3_port_config_id[unit] == 410)||(_tr3_port_config_id[unit] == 414)) { 9620 tdmv = _soc_tr3_tdm_arr[_soc_tr3_flex_tdm.base_slot[j]] + 9621 (k / _soc_tr3_flex_tdm.cell_offset[j] %4); 9622 port = si->port_p2l_mapping[tdmv]; 9623 if (port == -1 ){ 9624 tdmv = -1; 9625 } 9626 }else if ((_tr3_port_config_id[unit] == 413)&& 9627 ((_soc_tr3_tdm_arr[_soc_tr3_flex_tdm.base_slot[j]] == 57)|| 9628 (_soc_tr3_tdm_arr[_soc_tr3_flex_tdm.base_slot[j]] == 61))){ 9629 tdmv = ((k / _soc_tr3_flex_tdm.cell_offset[j]) % 2) ? 9630 (_soc_tr3_tdm_arr[_soc_tr3_flex_tdm.base_slot[j]] + 1) : 9631 _soc_tr3_tdm_arr[_soc_tr3_flex_tdm.base_slot[j]]; 9632 } else if (_tr3_port_config_id[unit] == 112 || _tr3_port_config_id[unit] == 12) { 9633 tdmv = _soc_tr3_tdm_arr[_soc_tr3_flex_tdm.base_slot[j]] + 9634 (k / _soc_tr3_flex_tdm.cell_offset[j] %4); 9635 port = si->port_p2l_mapping[tdmv]; 9636 if (port == -1 ) { 9637 tdmv = -1; 9638 } 9639 } else { 9640 tdmv = _soc_tr3_tdm_arr[_soc_tr3_flex_tdm.base_slot[j]] + 9641 (k / _soc_tr3_flex_tdm.cell_offset[j] %4); 9642 } 9643 LOG_VERBOSE(BSL_LS_SOC_COMMON, 9644 (BSL_META_U(unit, 9645 "arr[%d]: %d->%d\n"), i+c, _soc_tr3_tdm_arr[i+c], 9646 tdmv)); 9647 _soc_tr3_tdm_arr[i+c] = tdmv; 9648 break; 9649 default: 9650 break; 9651 } 9652 } 9653 } 9654 } 9655 } 9656 9657 for (i = 0; i < _soc_tr3_tdm_size; i++) { 9658 sal_memset(&iarb_tdm, 0, sizeof(iarb_tdm_table_entry_t)); 9659 if (_soc_tr3_tdm_arr[i] == -1) { 9660 soc_IARB_TDM_TABLEm_field32_set(unit, &iarb_tdm, PORT_NUMf, 9661 127); 9662 LOG_VERBOSE(BSL_LS_SOC_COMMON, 9663 (BSL_META_U(unit, 9664 "TDM slot: %d, NOP\n"), i)); 9665 } else { 9666 soc_IARB_TDM_TABLEm_field32_set(unit, &iarb_tdm, PORT_NUMf, 9667 _soc_tr3_tdm_arr[i]); 9668 LOG_VERBOSE(BSL_LS_SOC_COMMON, 9669 (BSL_META_U(unit, 9670 "TDM slot: %d, phy port: %d\n"), 9671 i, _soc_tr3_tdm_arr[i])); 9672 } 9673 SOC_IF_ERROR_RETURN(WRITE_IARB_TDM_TABLEm(unit, SOC_BLOCK_ALL, i, 9674 &iarb_tdm)); 9675 if (0 == (i%2)) { 9676 /* Two entries per mem entry */ 9677 sal_memset(&lls_tdm, 0, sizeof(lls_port_tdm_entry_t)); 9678 soc_LLS_PORT_TDMm_field32_set(unit, &lls_tdm, PORT_ID_0f, 9679 (_soc_tr3_tdm_arr[i] != -1) ? 9680 si->port_p2m_mapping[_soc_tr3_tdm_arr[i]] : 63); 9681 soc_LLS_PORT_TDMm_field32_set(unit, &lls_tdm, PORT_ID_0_ENABLEf, 1); 9682 } else { 9683 soc_LLS_PORT_TDMm_field32_set(unit, &lls_tdm, PORT_ID_1f, 9684 (_soc_tr3_tdm_arr[i] != -1) ? 9685 si->port_p2m_mapping[_soc_tr3_tdm_arr[i]] : 63); 9686 soc_LLS_PORT_TDMm_field32_set(unit, &lls_tdm, PORT_ID_1_ENABLEf, 1); 9687 SOC_IF_ERROR_RETURN(WRITE_LLS_PORT_TDMm(unit, SOC_BLOCK_ALL, (i/2), 9688 &lls_tdm)); 9689 SOC_IF_ERROR_RETURN(WRITE_LLS_PORT_TDMm(unit, SOC_BLOCK_ALL, 512+(i/2), 9690 &lls_tdm)); 9691 LOG_VERBOSE(BSL_LS_SOC_COMMON, 9692 (BSL_META_U(unit, 9693 "LLS TDM: %d, [%d],[%d]\n"), i/2, 9694 soc_LLS_PORT_TDMm_field32_get(unit, &lls_tdm, PORT_ID_0f), 9695 soc_LLS_PORT_TDMm_field32_get(unit, &lls_tdm, PORT_ID_1f))); 9696 } 9697 if ((_soc_tr3_tdm_size%2) && (i == (_soc_tr3_tdm_size-1))) { /* Handle last single odd entry */ 9698 SOC_IF_ERROR_RETURN 9699 (WRITE_LLS_PORT_TDMm(unit, SOC_BLOCK_ALL, (i/2), &lls_tdm)); 9700 SOC_IF_ERROR_RETURN 9701 (WRITE_LLS_PORT_TDMm(unit, SOC_BLOCK_ALL, 512+(i/2), &lls_tdm)); 9702 LOG_VERBOSE(BSL_LS_SOC_COMMON, 9703 (BSL_META_U(unit, 9704 "LLS TDM: %d, [%d],[%d]\n"), i/2, 9705 soc_LLS_PORT_TDMm_field32_get(unit, &lls_tdm, PORT_ID_0f), 9706 soc_LLS_PORT_TDMm_field32_get(unit, &lls_tdm, PORT_ID_1f))); 9707 } 9708 } 9709 9710 /* 9711 * bcmsim: C model cannot support cell based flow 9712 */ 9713 if (SAL_BOOT_BCMSIM) { 9714 soc_reg_field_set(unit, IARB_TDM_CONTROLr, &rval, DISABLEf, 1); 9715 } else { 9716 soc_reg_field_set(unit, IARB_TDM_CONTROLr, &rval, DISABLEf, 0); 9717 } 9718 soc_reg_field_set(unit, IARB_TDM_CONTROLr, &rval, AUX_CMICM_SLOT_ENf, 1); 9719 soc_reg_field_set(unit, IARB_TDM_CONTROLr, &rval, AUX_AXP_SLOT_ENf, 1); 9720 SOC_IF_ERROR_RETURN(WRITE_IARB_TDM_CONTROLr(unit, rval)); 9721 9722 SOC_IF_ERROR_RETURN(READ_LLS_TDM_CAL_CFGr(unit, &rval)); 9723 soc_reg_field_set(unit, LLS_TDM_CAL_CFGr, &rval, END_Af, (_soc_tr3_tdm_size) -1); 9724 soc_reg_field_set(unit, LLS_TDM_CAL_CFGr, &rval, END_Bf, (_soc_tr3_tdm_size) -1); 9725 soc_reg_field_set(unit, LLS_TDM_CAL_CFGr, &rval, DEFAULT_PORTf, 58); /* AXP MMU port num */ 9726 soc_reg_field_set(unit, LLS_TDM_CAL_CFGr, &rval, ENABLEf, 1); 9727 SOC_IF_ERROR_RETURN(WRITE_LLS_TDM_CAL_CFGr(unit, rval)); 9728 9729 SOC_IF_ERROR_RETURN 9730 (WRITE_LLS_TDM_OPPORTUNISTIC_SPACINGr(unit, _tr3_tdm_opp_spacing[unit])); 9731 if (SAL_BOOT_QUICKTURN) { 9732 SOC_IF_ERROR_RETURN(READ_PASSTHRU_NLF_MTU_CHECKr(unit, &rval)); 9733 soc_reg_field_set(unit, PASSTHRU_NLF_MTU_CHECKr, &rval, MTU_IN_BYTESf, 9734 0x3fff); 9735 SOC_IF_ERROR_RETURN(WRITE_PASSTHRU_NLF_MTU_CHECKr(unit, rval)); 9736 } 9737 9738 return SOC_E_NONE; 9739 } 9740 9741 STATIC int 9742 _soc_tr3_tdm_update(int unit, soc_port_t port, int lanes, int update_hw) 9743 { 9744 /* update the table values */ 9745 uint8 new_cal; 9746 uint16 i, j, k, c, p, delta = 0; 9747 uint32 rval, tdmv; 9748 int iter = 0, phy; 9749 int subport = -1; 9750 iarb_tdm_table_entry_t iarb_tdm; 9751 lls_port_tdm_entry_t lls_tdm; 9752 soc_info_t *si = &SOC_INFO(unit); 9753 9754 phy = si->port_l2p_mapping[port]; 9755 LOG_VERBOSE(BSL_LS_SOC_COMMON, 9756 (BSL_META_U(unit, 9757 "Phy port: %d\n"), phy)); 9758 for (j = 0; j < _tr3_flex_port_data[unit].port_groups; j++) { 9759 LOG_VERBOSE(BSL_LS_SOC_COMMON, 9760 (BSL_META_U(unit, 9761 "base slot[port]: %d[%d]\n"), _soc_tr3_flex_tdm.base_slot[j], 9762 _soc_tr3_tdm_arr[_soc_tr3_flex_tdm.base_slot[j]])); 9763 if (!_soc_tr3_flex_tdm.cells_per_row[j]) { 9764 continue; 9765 } 9766 for (i = 0; i < _soc_tr3_tdm_size; i+=_soc_tr3_flex_tdm.cells_per_row[j]) { 9767 for (k = _soc_tr3_flex_tdm.base_slot[j]; 9768 k < _soc_tr3_flex_tdm.cells_per_row[j]+_soc_tr3_flex_tdm.cell_offset[j]; 9769 k+=_soc_tr3_flex_tdm.cell_offset[j]) { 9770 c = k; 9771 /* Some exceptions - TR3 only */ 9772 if (!SOC_IS_HELIX4(unit)) { 9773 if ((_soc_tr3_flex_tdm.cells_per_row[j] == 25) && (k >= 24)) { 9774 continue; 9775 } 9776 if ((_soc_tr3_flex_tdm.cells_per_row[j] == 26) && (k >= 25)) { 9777 continue; 9778 } 9779 if (_tr3_port_config_id[unit] == 83) { 9780 if ((k / _soc_tr3_flex_tdm.cell_offset[j]) == 3) { 9781 c++; 9782 } 9783 } 9784 if (_tr3_port_config_id[unit] == 40) { 9785 if ((j == 2) && ((k / _soc_tr3_flex_tdm.cell_offset[j]) == 3)) { 9786 c-=1; 9787 } 9788 if ((j == 4) && ((k / _soc_tr3_flex_tdm.cell_offset[j]) >= 2)) { 9789 c-=1; 9790 } 9791 if ((j == 5) && ((k / _soc_tr3_flex_tdm.cell_offset[j]) >= 2)) { 9792 c+=1; 9793 } 9794 } 9795 if (_tr3_port_config_id[unit] == 112 || _tr3_port_config_id[unit] == 12) { 9796 if (((_soc_tr3_tdm_arr[_soc_tr3_flex_tdm.base_slot[j]] == 73) && 9797 ((k / _soc_tr3_flex_tdm.cell_offset[j]) >= 3))) { 9798 c-=1; 9799 } 9800 } 9801 } else { 9802 /* Helix4 specific */ 9803 if (_tr3_port_config_id[unit] == 490 || _tr3_port_config_id[unit] == 500 || 9804 _tr3_port_config_id[unit] == 495 || _tr3_port_config_id[unit] == 491 || 9805 _tr3_port_config_id[unit] == 514 || _tr3_port_config_id[unit] == 497 || 9806 _tr3_port_config_id[unit] == 510 || _tr3_port_config_id[unit] == 492) { 9807 if ((k / _soc_tr3_flex_tdm.cell_offset[j]) == 5) { 9808 c--; 9809 } 9810 if ((k / _soc_tr3_flex_tdm.cell_offset[j]) >= 6) { 9811 c-=2; 9812 } 9813 } else if (_tr3_port_config_id[unit] == 460 || 9814 _tr3_port_config_id[unit] == 462) { 9815 if ((k / _soc_tr3_flex_tdm.cell_offset[j]) >= 1) { 9816 c++; 9817 } 9818 } else if (_tr3_port_config_id[unit] == 464 || 9819 _tr3_port_config_id[unit] == 463) { 9820 if (_soc_tr3_flex_tdm.cell_offset[j] == 5) { 9821 c += (k/5 -1); 9822 } else if ((k / _soc_tr3_flex_tdm.cell_offset[j]) >= 1) { 9823 c++; 9824 } 9825 } else if (_tr3_port_config_id[unit] == 410 || 9826 _tr3_port_config_id[unit] == 420 || 9827 _tr3_port_config_id[unit] == 412 || 9828 _tr3_port_config_id[unit] == 413 || 9829 _tr3_port_config_id[unit] == 414) { 9830 if (((_tr3_port_config_id[unit] == 410) || (_tr3_port_config_id[unit] == 413))&& 9831 ((phy == 57) || (phy == 61))) { 9832 if ((phy == 57) && ((k / _soc_tr3_flex_tdm.cell_offset[j]) >= 2)) { 9833 c++; 9834 } 9835 } else { 9836 if ((k / _soc_tr3_flex_tdm.cell_offset[j]) >= 7) { 9837 c-=3; 9838 } else if ((k / _soc_tr3_flex_tdm.cell_offset[j]) >= 5) { 9839 c-=2; 9840 } else if ((k / _soc_tr3_flex_tdm.cell_offset[j]) >= 2) { 9841 c--; 9842 } 9843 } 9844 } else if (_tr3_port_config_id[unit] == 450) { 9845 if ((k / _soc_tr3_flex_tdm.cell_offset[j]) >= 6) { 9846 c-=2; 9847 } else if ((k / _soc_tr3_flex_tdm.cell_offset[j]) >= 2) { 9848 c--; 9849 } 9850 } else if (_tr3_port_config_id[unit] == 610) { 9851 if ((k / _soc_tr3_flex_tdm.cell_offset[j]) > 1 && 9852 (k / _soc_tr3_flex_tdm.cell_offset[j]) < 5) { 9853 c--; 9854 } else if ((k / _soc_tr3_flex_tdm.cell_offset[j]) == 7) { 9855 c-=3; 9856 } else if ((k / _soc_tr3_flex_tdm.cell_offset[j]) > 4) { 9857 c-=2; 9858 } 9859 } 9860 } 9861 if (c >= _soc_tr3_flex_tdm.cells_per_row[j]) { 9862 break; 9863 } 9864 if (k == _soc_tr3_flex_tdm.base_slot[j] && _soc_tr3_tdm_arr[i+c] != phy) { 9865 break; 9866 } 9867 switch(lanes) { /* Note: The meaning of lanes here is how many lanes/slot does a port use */ 9868 case 4: /* This is a single high speed port */ 9869 if (_soc_tr3_tdm_arr[i+c] != _soc_tr3_tdm_arr[_soc_tr3_flex_tdm.base_slot[j]]) { 9870 LOG_VERBOSE(BSL_LS_SOC_COMMON, 9871 (BSL_META_U(unit, 9872 "arr[%d]: %d->%d\n"), i+c, _soc_tr3_tdm_arr[i+c], 9873 _soc_tr3_tdm_arr[_soc_tr3_flex_tdm.base_slot[j]])); 9874 _soc_tr3_tdm_arr[i+c] = _soc_tr3_tdm_arr[_soc_tr3_flex_tdm.base_slot[j]]; 9875 delta++; 9876 } 9877 break; 9878 case 2: /* This is a set of 2 dual lane ports */ 9879 p = ((k / _soc_tr3_flex_tdm.cell_offset[j]) % 2) ? 9880 (_soc_tr3_tdm_arr[_soc_tr3_flex_tdm.base_slot[j]] + 2) : 9881 _soc_tr3_tdm_arr[_soc_tr3_flex_tdm.base_slot[j]]; 9882 if (_soc_tr3_tdm_arr[i+c] != p) { 9883 LOG_VERBOSE(BSL_LS_SOC_COMMON, 9884 (BSL_META_U(unit, 9885 "arr[%d]: %d->%d\n"), i+c, _soc_tr3_tdm_arr[i+c], 9886 ((k / _soc_tr3_flex_tdm.cell_offset[j]) % 2) ? 9887 (_soc_tr3_tdm_arr[_soc_tr3_flex_tdm.base_slot[j]] + 2) : 9888 _soc_tr3_tdm_arr[_soc_tr3_flex_tdm.base_slot[j]])); 9889 if( ((413 == _tr3_port_config_id[unit])||(463 == _tr3_port_config_id[unit]))&& 9890 ((_soc_tr3_tdm_arr[_soc_tr3_flex_tdm.base_slot[j]] == 57)|| 9891 (_soc_tr3_tdm_arr[_soc_tr3_flex_tdm.base_slot[j]] == 61))){ 9892 _soc_tr3_tdm_arr[i+c] = _soc_tr3_tdm_arr[_soc_tr3_flex_tdm.base_slot[j]]; 9893 }else{ 9894 _soc_tr3_tdm_arr[i+c] = ((k / _soc_tr3_flex_tdm.cell_offset[j]) % 2) ? 9895 (_soc_tr3_tdm_arr[_soc_tr3_flex_tdm.base_slot[j]] + 2) : 9896 _soc_tr3_tdm_arr[_soc_tr3_flex_tdm.base_slot[j]]; 9897 } 9898 delta++; 9899 } 9900 break; 9901 case 1: /* This is a single lane port group of 4 ports */ 9902 if ((_tr3_port_config_id[unit] == 464) && 9903 (_soc_tr3_flex_tdm.cell_offset[j] == _soc_tr3_flex_tdm.base_slot[j])) { 9904 tdmv = _soc_tr3_tdm_arr[_soc_tr3_flex_tdm.base_slot[j]] + 9905 ((k-1) / _soc_tr3_flex_tdm.cell_offset[j] %4); 9906 } else if (_tr3_port_config_id[unit] == 463 ) { 9907 if(_soc_tr3_flex_tdm.cell_offset[j] == _soc_tr3_flex_tdm.base_slot[j]){ 9908 if ((_soc_tr3_tdm_arr[_soc_tr3_flex_tdm.base_slot[j]] == 57)|| 9909 (_soc_tr3_tdm_arr[_soc_tr3_flex_tdm.base_slot[j]] == 61)){ 9910 tdmv = _soc_tr3_tdm_arr[_soc_tr3_flex_tdm.base_slot[j]] + 9911 ((k-1) / _soc_tr3_flex_tdm.cell_offset[j] %2); 9912 }else{ 9913 tdmv = _soc_tr3_tdm_arr[_soc_tr3_flex_tdm.base_slot[j]] + 9914 ((k-1) / _soc_tr3_flex_tdm.cell_offset[j] %4); 9915 } 9916 } 9917 else { 9918 if ((_soc_tr3_tdm_arr[_soc_tr3_flex_tdm.base_slot[j]] == 57)|| 9919 (_soc_tr3_tdm_arr[_soc_tr3_flex_tdm.base_slot[j]] == 61)){ 9920 tdmv = _soc_tr3_tdm_arr[_soc_tr3_flex_tdm.base_slot[j]] + 9921 (k / _soc_tr3_flex_tdm.cell_offset[j] %2); 9922 }else{ 9923 tdmv = _soc_tr3_tdm_arr[_soc_tr3_flex_tdm.base_slot[j]] + 9924 (k / _soc_tr3_flex_tdm.cell_offset[j] %4); 9925 } 9926 } 9927 port = si->port_p2l_mapping[tdmv]; 9928 if (port == -1 ) { 9929 tdmv = -1; 9930 } 9931 } else if ((_tr3_port_config_id[unit] == 410) ||(_tr3_port_config_id[unit] == 414)) { 9932 tdmv = _soc_tr3_tdm_arr[_soc_tr3_flex_tdm.base_slot[j]] + 9933 (k / _soc_tr3_flex_tdm.cell_offset[j] %4); 9934 subport = si->port_p2l_mapping[tdmv]; 9935 if (subport == -1 ) { 9936 tdmv = -1; 9937 } 9938 }else if((_tr3_port_config_id[unit] == 413)&& 9939 ((_soc_tr3_tdm_arr[_soc_tr3_flex_tdm.base_slot[j]] == 57)|| 9940 (_soc_tr3_tdm_arr[_soc_tr3_flex_tdm.base_slot[j]] == 61))){ 9941 tdmv = _soc_tr3_tdm_arr[_soc_tr3_flex_tdm.base_slot[j]] + 9942 (k / _soc_tr3_flex_tdm.cell_offset[j] %2); 9943 subport = si->port_p2l_mapping[tdmv]; 9944 if (subport == -1 ) { 9945 tdmv = -1; 9946 } 9947 } else if (_tr3_port_config_id[unit] == 112 || _tr3_port_config_id[unit] == 12) { 9948 tdmv = _soc_tr3_tdm_arr[_soc_tr3_flex_tdm.base_slot[j]] + 9949 (k / _soc_tr3_flex_tdm.cell_offset[j] %4); 9950 subport = si->port_p2l_mapping[tdmv]; 9951 if (subport == -1 ) { 9952 tdmv = -1; 9953 } 9954 } else { 9955 tdmv = _soc_tr3_tdm_arr[_soc_tr3_flex_tdm.base_slot[j]] + 9956 (k / _soc_tr3_flex_tdm.cell_offset[j] %4); 9957 } 9958 if (_soc_tr3_tdm_arr[i+c] != tdmv ) { 9959 LOG_VERBOSE(BSL_LS_SOC_COMMON, 9960 (BSL_META_U(unit, 9961 "arr[%d]: %d->%d\n"), i+c, _soc_tr3_tdm_arr[i+c], 9962 tdmv)); 9963 _soc_tr3_tdm_arr[i+c] = tdmv; 9964 delta++; 9965 } 9966 break; 9967 default: 9968 break; 9969 } 9970 } 9971 } 9972 } 9973 if (!delta) { 9974 LOG_VERBOSE(BSL_LS_SOC_COMMON, 9975 (BSL_META_U(unit, 9976 "No LLs TDM change needed..\n"))); 9977 return SOC_E_NONE; 9978 } 9979 if (!update_hw) { 9980 LOG_VERBOSE(BSL_LS_SOC_COMMON, 9981 (BSL_META_U(unit, 9982 "No LLs TDM h/w change requested..\n"))); 9983 return SOC_E_NONE; 9984 } 9985 /* Determine current calendar */ 9986 SOC_IF_ERROR_RETURN(READ_LLS_TDM_STATUSr(unit, &rval)); 9987 new_cal = ~(soc_reg_field_get(unit, LLS_TDM_STATUSr, rval, CURRENT_CALENDARf)) & 1; 9988 j = new_cal * 512; 9989 9990 /* Check and update h/w with deltas only */ 9991 for (i = 0; i < _soc_tr3_tdm_size; i++) { 9992 SOC_IF_ERROR_RETURN(READ_IARB_TDM_TABLEm(unit, SOC_BLOCK_ALL, i, 9993 &iarb_tdm)); 9994 if (_soc_tr3_tdm_arr[i] != -1) { 9995 if (_soc_tr3_tdm_arr[i] != 9996 soc_IARB_TDM_TABLEm_field32_get(unit, &iarb_tdm, PORT_NUMf)) { 9997 soc_IARB_TDM_TABLEm_field32_set(unit, &iarb_tdm, PORT_NUMf, 9998 _soc_tr3_tdm_arr[i]); 9999 LOG_VERBOSE(BSL_LS_SOC_COMMON, 10000 (BSL_META_U(unit, 10001 "TDM slot: %d, phy port: %d\n"), 10002 i, _soc_tr3_tdm_arr[i])); 10003 SOC_IF_ERROR_RETURN(WRITE_IARB_TDM_TABLEm(unit, SOC_BLOCK_ALL, i, 10004 &iarb_tdm)); 10005 } 10006 } else if (soc_IARB_TDM_TABLEm_field32_get(unit, &iarb_tdm, PORT_NUMf) != 127) { 10007 soc_IARB_TDM_TABLEm_field32_set(unit, &iarb_tdm, PORT_NUMf, 127); 10008 SOC_IF_ERROR_RETURN(WRITE_IARB_TDM_TABLEm(unit, SOC_BLOCK_ALL, i, 10009 &iarb_tdm)); 10010 } 10011 if (0 == (i%2)) { 10012 delta = 0; 10013 SOC_IF_ERROR_RETURN(READ_LLS_PORT_TDMm(unit, SOC_BLOCK_ALL, j+(i/2), 10014 &lls_tdm)); 10015 if (_soc_tr3_tdm_arr[i] != -1) { 10016 if (si->port_p2m_mapping[_soc_tr3_tdm_arr[i]] != 10017 soc_LLS_PORT_TDMm_field32_get(unit, &lls_tdm, PORT_ID_0f)) { 10018 soc_LLS_PORT_TDMm_field32_set(unit, &lls_tdm, PORT_ID_0f, 10019 si->port_p2m_mapping[_soc_tr3_tdm_arr[i]]); 10020 delta = 1; 10021 LOG_VERBOSE(BSL_LS_SOC_COMMON, 10022 (BSL_META_U(unit, 10023 "i_0 %d: %d\n"), i, si->port_p2m_mapping[_soc_tr3_tdm_arr[i]])); 10024 } 10025 } else if (soc_LLS_PORT_TDMm_field32_get(unit, &lls_tdm, PORT_ID_0f) != 63) { 10026 soc_LLS_PORT_TDMm_field32_set(unit, &lls_tdm, PORT_ID_0f, 63); 10027 delta = 1; 10028 } 10029 } else { 10030 if (_soc_tr3_tdm_arr[i] != -1) { 10031 if (si->port_p2m_mapping[_soc_tr3_tdm_arr[i]] != 10032 soc_LLS_PORT_TDMm_field32_get(unit, &lls_tdm, PORT_ID_1f)) { 10033 soc_LLS_PORT_TDMm_field32_set(unit, &lls_tdm, PORT_ID_1f, 10034 si->port_p2m_mapping[_soc_tr3_tdm_arr[i]]); 10035 delta = 1; 10036 LOG_VERBOSE(BSL_LS_SOC_COMMON, 10037 (BSL_META_U(unit, 10038 "i_1 %d: %d\n"), i, si->port_p2m_mapping[_soc_tr3_tdm_arr[i]])); 10039 } 10040 } else if (soc_LLS_PORT_TDMm_field32_get(unit, &lls_tdm, PORT_ID_1f) != 63) { 10041 soc_LLS_PORT_TDMm_field32_set(unit, &lls_tdm, PORT_ID_1f, 63); 10042 delta = 1; 10043 } 10044 if (delta) { 10045 SOC_IF_ERROR_RETURN(WRITE_LLS_PORT_TDMm(unit, SOC_BLOCK_ALL, j+(i/2), 10046 &lls_tdm)); 10047 LOG_VERBOSE(BSL_LS_SOC_COMMON, 10048 (BSL_META_U(unit, 10049 "LLS TDM: %d, [%d],[%d]\n"), j+(i/2), 10050 soc_LLS_PORT_TDMm_field32_get(unit, &lls_tdm, PORT_ID_0f), 10051 soc_LLS_PORT_TDMm_field32_get(unit, &lls_tdm, PORT_ID_1f))); 10052 delta = 0; 10053 } 10054 } 10055 /* Handle last single odd entry */ 10056 if ((_soc_tr3_tdm_size%2) && (i == (_soc_tr3_tdm_size-1)) && delta) { 10057 SOC_IF_ERROR_RETURN(WRITE_LLS_PORT_TDMm(unit, SOC_BLOCK_ALL, j+(i/2), 10058 &lls_tdm)); 10059 LOG_VERBOSE(BSL_LS_SOC_COMMON, 10060 (BSL_META_U(unit, 10061 "LLS TDM: %d, [%d],[%d]\n"), j+(i/2), 10062 soc_LLS_PORT_TDMm_field32_get(unit, &lls_tdm, PORT_ID_0f), 10063 soc_LLS_PORT_TDMm_field32_get(unit, &lls_tdm, PORT_ID_1f))); 10064 } 10065 } 10066 /* Switch LLS calendar */ 10067 SOC_IF_ERROR_RETURN(WRITE_LLS_TDM_CAL_CFG_SWITCHr(unit, 1)); 10068 do { 10069 SOC_IF_ERROR_RETURN(READ_LLS_TDM_STATUSr(unit, &rval)); 10070 sal_udelay(100); 10071 } while ((iter++ < 100000) && 10072 (soc_reg_field_get(unit, LLS_TDM_STATUSr, rval, 10073 CURRENT_CALENDARf) != new_cal) && 10074 !(SAL_BOOT_BCMSIM || SAL_BOOT_PLISIM)); 10075 if (iter >= 100000) { 10076 LOG_ERROR(BSL_LS_SOC_COMMON, 10077 (BSL_META_U(unit, 10078 "LLS Calendar switch failed !!\n"))); 10079 return SOC_E_INTERNAL; 10080 } 10081 SOC_IF_ERROR_RETURN(WRITE_LLS_TDM_CAL_CFG_SWITCHr(unit, 0)); 10082 return SOC_E_NONE; 10083 } 10084 10085 STATIC int 10086 _soc_tr3_ledup_init(int unit) 10087 { 10088 int ix; 10089 uint32 rval = 0; 10090 struct led_remap { 10091 uint32 reg_addr0; 10092 uint32 reg_addr1; 10093 uint32 port0; 10094 uint32 port1; 10095 uint32 port2; 10096 uint32 port3; 10097 } led_remap[] = { 10098 { CMIC_LEDUP0_PORT_ORDER_REMAP_0_3r, CMIC_LEDUP1_PORT_ORDER_REMAP_0_3r, 10099 REMAP_PORT_0f,REMAP_PORT_1f,REMAP_PORT_2f,REMAP_PORT_3f }, 10100 { CMIC_LEDUP0_PORT_ORDER_REMAP_4_7r, CMIC_LEDUP1_PORT_ORDER_REMAP_4_7r, 10101 REMAP_PORT_4f,REMAP_PORT_5f,REMAP_PORT_6f,REMAP_PORT_7f }, 10102 { CMIC_LEDUP0_PORT_ORDER_REMAP_8_11r, CMIC_LEDUP1_PORT_ORDER_REMAP_8_11r, 10103 REMAP_PORT_8f,REMAP_PORT_9f,REMAP_PORT_10f,REMAP_PORT_11f }, 10104 { CMIC_LEDUP0_PORT_ORDER_REMAP_12_15r, CMIC_LEDUP1_PORT_ORDER_REMAP_12_15r, 10105 REMAP_PORT_12f,REMAP_PORT_13f,REMAP_PORT_14f,REMAP_PORT_15f }, 10106 { CMIC_LEDUP0_PORT_ORDER_REMAP_16_19r, CMIC_LEDUP1_PORT_ORDER_REMAP_16_19r, 10107 REMAP_PORT_16f,REMAP_PORT_17f,REMAP_PORT_18f,REMAP_PORT_19f }, 10108 { CMIC_LEDUP0_PORT_ORDER_REMAP_20_23r, CMIC_LEDUP1_PORT_ORDER_REMAP_20_23r, 10109 REMAP_PORT_20f,REMAP_PORT_21f,REMAP_PORT_22f,REMAP_PORT_23f }, 10110 { CMIC_LEDUP0_PORT_ORDER_REMAP_24_27r, CMIC_LEDUP1_PORT_ORDER_REMAP_24_27r, 10111 REMAP_PORT_24f,REMAP_PORT_25f,REMAP_PORT_26f,REMAP_PORT_27f }, 10112 { CMIC_LEDUP0_PORT_ORDER_REMAP_28_31r, CMIC_LEDUP1_PORT_ORDER_REMAP_28_31r, 10113 REMAP_PORT_28f,REMAP_PORT_29f,REMAP_PORT_30f,REMAP_PORT_31f }, 10114 { CMIC_LEDUP0_PORT_ORDER_REMAP_32_35r, CMIC_LEDUP1_PORT_ORDER_REMAP_32_35r, 10115 REMAP_PORT_32f,REMAP_PORT_33f,REMAP_PORT_34f,REMAP_PORT_35f }, 10116 { CMIC_LEDUP0_PORT_ORDER_REMAP_36_39r, CMIC_LEDUP1_PORT_ORDER_REMAP_36_39r, 10117 REMAP_PORT_36f,REMAP_PORT_37f,REMAP_PORT_38f,REMAP_PORT_39f }, 10118 { CMIC_LEDUP0_PORT_ORDER_REMAP_40_43r, CMIC_LEDUP1_PORT_ORDER_REMAP_40_43r, 10119 REMAP_PORT_40f,REMAP_PORT_41f,REMAP_PORT_42f,REMAP_PORT_43f }, 10120 { CMIC_LEDUP0_PORT_ORDER_REMAP_44_47r, CMIC_LEDUP1_PORT_ORDER_REMAP_44_47r, 10121 REMAP_PORT_44f,REMAP_PORT_45f,REMAP_PORT_46f,REMAP_PORT_47f }, 10122 { CMIC_LEDUP0_PORT_ORDER_REMAP_48_51r, CMIC_LEDUP1_PORT_ORDER_REMAP_48_51r, 10123 REMAP_PORT_48f,REMAP_PORT_49f,REMAP_PORT_50f,REMAP_PORT_51f }/*, 10124 { CMIC_LEDUP0_PORT_ORDER_REMAP_52_55r, CMIC_LEDUP1_PORT_ORDER_REMAP_52_55r, 10125 REMAP_PORT_52f,REMAP_PORT_53f,REMAP_PORT_54f,REMAP_PORT_55f }, 10126 { CMIC_LEDUP0_PORT_ORDER_REMAP_56_59r, CMIC_LEDUP1_PORT_ORDER_REMAP_56_59r, 10127 REMAP_PORT_56f,REMAP_PORT_57f,REMAP_PORT_58f,REMAP_PORT_59f }, 10128 { CMIC_LEDUP0_PORT_ORDER_REMAP_60_63r, CMIC_LEDUP1_PORT_ORDER_REMAP_60_63r, 10129 REMAP_PORT_60f,REMAP_PORT_61f,REMAP_PORT_62f,REMAP_PORT_63f }*/ 10130 }; 10131 10132 10133 /* initialize the led remap register settings */ 10134 for (ix = 0; ix < COUNTOF(led_remap); ix++) { 10135 rval = 0; 10136 soc_reg_field_set(unit, led_remap[ix].reg_addr0, &rval, 10137 led_remap[ix].port0, ix * 4 + 1); 10138 soc_reg_field_set(unit, led_remap[ix].reg_addr0, &rval, 10139 led_remap[ix].port1, ix * 4 + 2); 10140 soc_reg_field_set(unit, led_remap[ix].reg_addr0, &rval, 10141 led_remap[ix].port2, ix * 4 + 3); 10142 soc_reg_field_set(unit, led_remap[ix].reg_addr0, &rval, 10143 led_remap[ix].port3, ix * 4 + 4); 10144 /* coverity[result_independent_of_operands] */ 10145 SOC_IF_ERROR_RETURN 10146 (soc_pci_write(unit, 10147 soc_reg_addr(unit, led_remap[ix].reg_addr0, REG_PORT_ANY, 0), 10148 rval)); 10149 if (ix < 7) { 10150 /* coverity[result_independent_of_operands] */ 10151 SOC_IF_ERROR_RETURN 10152 (soc_pci_write(unit, 10153 soc_reg_addr(unit, led_remap[ix].reg_addr1, REG_PORT_ANY, 0), 10154 rval)); 10155 } 10156 } 10157 10158 /* configure the LED scan delay cycles */ 10159 /* coverity[result_independent_of_operands] */ 10160 SOC_IF_ERROR_RETURN(READ_CMIC_LEDUP0_CTRLr(unit, &rval)); 10161 soc_reg_field_set(unit, CMIC_LEDUP0_CTRLr, &rval, LEDUP_SCAN_START_DELAYf, 11); 10162 /* coverity[result_independent_of_operands] */ 10163 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP0_CTRLr(unit, rval)); 10164 /* coverity[result_independent_of_operands] */ 10165 SOC_IF_ERROR_RETURN(READ_CMIC_LEDUP1_CTRLr(unit, &rval)); 10166 soc_reg_field_set(unit, CMIC_LEDUP1_CTRLr, &rval, LEDUP_SCAN_START_DELAYf, 4); 10167 /* coverity[result_independent_of_operands] */ 10168 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP1_CTRLr(unit, rval)); 10169 10170 rval =0; 10171 10172 /* coverity[result_independent_of_operands] */ 10173 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP0_PORT_ORDER_REMAP_0_3r(unit, rval)); 10174 /* coverity[result_independent_of_operands] */ 10175 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP0_PORT_ORDER_REMAP_4_7r(unit, rval)); 10176 /* coverity[result_independent_of_operands] */ 10177 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP0_PORT_ORDER_REMAP_8_11r(unit, rval)); 10178 /* coverity[result_independent_of_operands] */ 10179 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP0_PORT_ORDER_REMAP_12_15r(unit, rval)); 10180 /* coverity[result_independent_of_operands] */ 10181 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP0_PORT_ORDER_REMAP_16_19r(unit, rval)); 10182 /* coverity[result_independent_of_operands] */ 10183 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP0_PORT_ORDER_REMAP_20_23r(unit, rval)); 10184 /* coverity[result_independent_of_operands] */ 10185 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP0_PORT_ORDER_REMAP_24_27r(unit, rval)); 10186 /* coverity[result_independent_of_operands] */ 10187 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP0_PORT_ORDER_REMAP_28_31r(unit, rval)); 10188 /* coverity[result_independent_of_operands] */ 10189 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP0_PORT_ORDER_REMAP_32_35r(unit, rval)); 10190 /* coverity[result_independent_of_operands] */ 10191 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP0_PORT_ORDER_REMAP_36_39r(unit, rval)); 10192 /* coverity[result_independent_of_operands] */ 10193 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP0_PORT_ORDER_REMAP_40_43r(unit, rval)); 10194 /* coverity[result_independent_of_operands] */ 10195 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP0_PORT_ORDER_REMAP_44_47r(unit, rval)); 10196 /* coverity[result_independent_of_operands] */ 10197 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP0_PORT_ORDER_REMAP_48_51r(unit, rval)); 10198 /* coverity[result_independent_of_operands] */ 10199 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP0_PORT_ORDER_REMAP_52_55r(unit, rval)); 10200 /* coverity[result_independent_of_operands] */ 10201 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP0_PORT_ORDER_REMAP_56_59r(unit, rval)); 10202 /* coverity[result_independent_of_operands] */ 10203 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP0_PORT_ORDER_REMAP_60_63r(unit, rval)); 10204 10205 rval = 0; 10206 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_0_3r, &rval, REMAP_PORT_0f, 48); 10207 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_0_3r, &rval, REMAP_PORT_1f, 47); 10208 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_0_3r, &rval, REMAP_PORT_2f, 46); 10209 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_0_3r, &rval, REMAP_PORT_3f, 45); 10210 /* coverity[result_independent_of_operands] */ 10211 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP0_PORT_ORDER_REMAP_0_3r(unit, rval)); 10212 10213 rval = 0; 10214 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_4_7r, &rval, REMAP_PORT_4f, 44); 10215 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_4_7r, &rval, REMAP_PORT_5f, 43); 10216 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_4_7r, &rval, REMAP_PORT_6f, 42); 10217 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_4_7r, &rval, REMAP_PORT_7f, 41); 10218 /* coverity[result_independent_of_operands] */ 10219 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP0_PORT_ORDER_REMAP_4_7r(unit, rval)); 10220 10221 rval = 0; 10222 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_8_11r, &rval, REMAP_PORT_8f, 40); 10223 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_8_11r, &rval, REMAP_PORT_9f, 39); 10224 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_8_11r, &rval, REMAP_PORT_10f, 38); 10225 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_8_11r, &rval, REMAP_PORT_11f, 37); 10226 /* coverity[result_independent_of_operands] */ 10227 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP0_PORT_ORDER_REMAP_8_11r(unit, rval)); 10228 10229 /* m CMIC_LEDUP0_PORT_ORDER_REMAP_12_15 REMAP_PORT_15=49 */ 10230 rval = 0; 10231 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_12_15r, &rval, REMAP_PORT_15f, 49); 10232 /* coverity[result_independent_of_operands] */ 10233 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP0_PORT_ORDER_REMAP_12_15r(unit, rval)); 10234 10235 10236 rval = 0; 10237 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_16_19r, &rval, REMAP_PORT_16f, 36); 10238 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_16_19r, &rval, REMAP_PORT_17f, 35); 10239 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_16_19r, &rval, REMAP_PORT_18f, 34); 10240 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_16_19r, &rval, REMAP_PORT_19f, 33); 10241 /* coverity[result_independent_of_operands] */ 10242 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP0_PORT_ORDER_REMAP_16_19r(unit, rval)); 10243 10244 rval = 0; 10245 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_20_23r, &rval, REMAP_PORT_20f, 32); 10246 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_20_23r, &rval, REMAP_PORT_21f, 31); 10247 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_20_23r, &rval, REMAP_PORT_22f, 30); 10248 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_20_23r, &rval, REMAP_PORT_23f, 29); 10249 /* coverity[result_independent_of_operands] */ 10250 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP0_PORT_ORDER_REMAP_20_23r(unit, rval)); 10251 10252 rval = 0; 10253 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_24_27r, &rval, REMAP_PORT_24f, 28); 10254 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_24_27r, &rval, REMAP_PORT_25f, 27); 10255 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_24_27r, &rval, REMAP_PORT_26f, 26); 10256 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_24_27r, &rval, REMAP_PORT_27f, 25); 10257 /* coverity[result_independent_of_operands] */ 10258 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP0_PORT_ORDER_REMAP_24_27r(unit, rval)); 10259 10260 rval = 0; 10261 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_28_31r, &rval, REMAP_PORT_28f, 24); 10262 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_28_31r, &rval, REMAP_PORT_29f, 23); 10263 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_28_31r, &rval, REMAP_PORT_30f, 22); 10264 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_28_31r, &rval, REMAP_PORT_31f, 21); 10265 /* coverity[result_independent_of_operands] */ 10266 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP0_PORT_ORDER_REMAP_28_31r(unit, rval)); 10267 10268 rval = 0; 10269 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_32_35r, &rval, REMAP_PORT_32f, 20); 10270 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_32_35r, &rval, REMAP_PORT_33f, 19); 10271 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_32_35r, &rval, REMAP_PORT_34f, 18); 10272 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_32_35r, &rval, REMAP_PORT_35f, 17); 10273 /* coverity[result_independent_of_operands] */ 10274 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP0_PORT_ORDER_REMAP_32_35r(unit, rval)); 10275 10276 rval = 0; 10277 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_36_39r, &rval, REMAP_PORT_36f, 16); 10278 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_36_39r, &rval, REMAP_PORT_37f, 15); 10279 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_36_39r, &rval, REMAP_PORT_38f, 14); 10280 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_36_39r, &rval, REMAP_PORT_39f, 13); 10281 /* coverity[result_independent_of_operands] */ 10282 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP0_PORT_ORDER_REMAP_36_39r(unit, rval)); 10283 10284 rval = 0; 10285 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_40_43r, &rval, REMAP_PORT_40f, 12); 10286 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_40_43r, &rval, REMAP_PORT_41f, 11); 10287 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_40_43r, &rval, REMAP_PORT_42f, 10); 10288 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_40_43r, &rval, REMAP_PORT_43f, 9); 10289 /* coverity[result_independent_of_operands] */ 10290 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP0_PORT_ORDER_REMAP_40_43r(unit, rval)); 10291 10292 rval = 0; 10293 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_44_47r, &rval, REMAP_PORT_44f, 8); 10294 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_44_47r, &rval, REMAP_PORT_45f, 7); 10295 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_44_47r, &rval, REMAP_PORT_46f, 6); 10296 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_44_47r, &rval, REMAP_PORT_47f, 5); 10297 /* coverity[result_independent_of_operands] */ 10298 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP0_PORT_ORDER_REMAP_44_47r(unit, rval)); 10299 10300 rval = 0; 10301 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_48_51r, &rval, REMAP_PORT_48f, 4); 10302 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_48_51r, &rval, REMAP_PORT_49f, 3); 10303 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_48_51r, &rval, REMAP_PORT_50f, 2); 10304 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_48_51r, &rval, REMAP_PORT_51f, 1); 10305 /* coverity[result_independent_of_operands] */ 10306 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP0_PORT_ORDER_REMAP_48_51r(unit, rval)); 10307 10308 10309 rval = 0; 10310 /* coverity[result_independent_of_operands] */ 10311 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP1_PORT_ORDER_REMAP_0_3r(unit, rval)); 10312 /* coverity[result_independent_of_operands] */ 10313 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP1_PORT_ORDER_REMAP_4_7r(unit, rval)); 10314 /* coverity[result_independent_of_operands] */ 10315 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP1_PORT_ORDER_REMAP_8_11r(unit, rval)); 10316 /* coverity[result_independent_of_operands] */ 10317 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP1_PORT_ORDER_REMAP_12_15r(unit, rval)); 10318 /* coverity[result_independent_of_operands] */ 10319 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP1_PORT_ORDER_REMAP_16_19r(unit, rval)); 10320 /* coverity[result_independent_of_operands] */ 10321 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP1_PORT_ORDER_REMAP_20_23r(unit, rval)); 10322 /* coverity[result_independent_of_operands] */ 10323 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP1_PORT_ORDER_REMAP_24_27r(unit, rval)); 10324 /* coverity[result_independent_of_operands] */ 10325 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP1_PORT_ORDER_REMAP_28_31r(unit, rval)); 10326 /* coverity[result_independent_of_operands] */ 10327 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP1_PORT_ORDER_REMAP_32_35r(unit, rval)); 10328 /* coverity[result_independent_of_operands] */ 10329 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP1_PORT_ORDER_REMAP_36_39r(unit, rval)); 10330 /* coverity[result_independent_of_operands] */ 10331 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP1_PORT_ORDER_REMAP_40_43r(unit, rval)); 10332 /* coverity[result_independent_of_operands] */ 10333 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP1_PORT_ORDER_REMAP_44_47r(unit, rval)); 10334 /* coverity[result_independent_of_operands] */ 10335 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP1_PORT_ORDER_REMAP_48_51r(unit, rval)); 10336 /* coverity[result_independent_of_operands] */ 10337 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP1_PORT_ORDER_REMAP_52_55r(unit, rval)); 10338 /* coverity[result_independent_of_operands] */ 10339 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP1_PORT_ORDER_REMAP_56_59r(unit, rval)); 10340 /* coverity[result_independent_of_operands] */ 10341 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP1_PORT_ORDER_REMAP_60_63r(unit, rval)); 10342 10343 10344 /* c1 WC-C0/13/0 CMIC_LEDUP1_PORT_ORDER_REMAP_24_27.REMAP_PORT_27 */ 10345 /* c1 WC-C0/13/1 CMIC_LEDUP1_PORT_ORDER_REMAP_24_27.REMAP_PORT_26 */ 10346 /* c1 WC-C0/13/2 CMIC_LEDUP1_PORT_ORDER_REMAP_24_27.REMAP_PORT_25 */ 10347 10348 /* c1 WC-C0/13/3, WC-C0/16/4 CMIC_LEDUP1_PORT_ORDER_REMAP_24_27.REMAP_PORT_24 */ 10349 10350 rval = 0; 10351 soc_reg_field_set(unit, CMIC_LEDUP1_PORT_ORDER_REMAP_24_27r, &rval, REMAP_PORT_27f, 5); 10352 soc_reg_field_set(unit, CMIC_LEDUP1_PORT_ORDER_REMAP_24_27r, &rval, REMAP_PORT_26f, 6); 10353 soc_reg_field_set(unit, CMIC_LEDUP1_PORT_ORDER_REMAP_24_27r, &rval, REMAP_PORT_25f, 7); 10354 soc_reg_field_set(unit, CMIC_LEDUP1_PORT_ORDER_REMAP_24_27r, &rval, REMAP_PORT_24f, 8); 10355 /* coverity[result_independent_of_operands] */ 10356 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP1_PORT_ORDER_REMAP_24_27r(unit, rval)); 10357 10358 10359 /* c5 WC-C0/14/0 CMIC_LEDUP1_PORT_ORDER_REMAP_20_23.REMAP_PORT_23 */ 10360 /* c5 WC-C0/14/1 CMIC_LEDUP1_PORT_ORDER_REMAP_20_23.REMAP_PORT_22 */ 10361 /* c5 WC-C0/14/2 CMIC_LEDUP1_PORT_ORDER_REMAP_20_23.REMAP_PORT_21 */ 10362 /* c5 WC-C0/14/3 CMIC_LEDUP1_PORT_ORDER_REMAP_20_23.REMAP_PORT_20 */ 10363 10364 rval = 0; 10365 soc_reg_field_set(unit, CMIC_LEDUP1_PORT_ORDER_REMAP_20_23r, &rval, REMAP_PORT_23f, 9); 10366 soc_reg_field_set(unit, CMIC_LEDUP1_PORT_ORDER_REMAP_20_23r, &rval, REMAP_PORT_22f, 10); 10367 soc_reg_field_set(unit, CMIC_LEDUP1_PORT_ORDER_REMAP_20_23r, &rval, REMAP_PORT_21f, 11); 10368 soc_reg_field_set(unit, CMIC_LEDUP1_PORT_ORDER_REMAP_20_23r, &rval, REMAP_PORT_20f, 12); 10369 /* coverity[result_independent_of_operands] */ 10370 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP1_PORT_ORDER_REMAP_20_23r(unit, rval)); 10371 10372 10373 /* c9 WC-C0/15/0 CMIC_LEDUP1_PORT_ORDER_REMAP_16_19.REMAP_PORT_19 */ 10374 /* c9 WC-C0/15/1 CMIC_LEDUP1_PORT_ORDER_REMAP_16_19.REMAP_PORT_18 */ 10375 /* c9 WC-C0/15/2 CMIC_LEDUP1_PORT_ORDER_REMAP_16_19.REMAP_PORT_17 */ 10376 /* c9 WC-C0/15/3, WC-C0/16/4 CMIC_LEDUP1_PORT_ORDER_REMAP_16_19.REMAP_PORT_16 */ 10377 10378 rval = 0; 10379 soc_reg_field_set(unit, CMIC_LEDUP1_PORT_ORDER_REMAP_16_19r, &rval, REMAP_PORT_19f, 13); 10380 soc_reg_field_set(unit, CMIC_LEDUP1_PORT_ORDER_REMAP_16_19r, &rval, REMAP_PORT_18f, 14); 10381 soc_reg_field_set(unit, CMIC_LEDUP1_PORT_ORDER_REMAP_16_19r, &rval, REMAP_PORT_17f, 15); 10382 soc_reg_field_set(unit, CMIC_LEDUP1_PORT_ORDER_REMAP_16_19r, &rval, REMAP_PORT_16f, 16); 10383 /* coverity[result_independent_of_operands] */ 10384 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP1_PORT_ORDER_REMAP_16_19r(unit, rval)); 10385 10386 10387 /* cd WC-C0/16/0 CMIC_LEDUP1_PORT_ORDER_REMAP_12_15.REMAP_PORT_15 */ 10388 /* cd WC-C0/16/1 CMIC_LEDUP1_PORT_ORDER_REMAP_12_15.REMAP_PORT_14 */ 10389 /* cd WC-C0/16/2 CMIC_LEDUP1_PORT_ORDER_REMAP_12_15.REMAP_PORT_13 */ 10390 /* cd WC-C0/16/3, WC-C0/16/4 CMIC_LEDUP1_PORT_ORDER_REMAP_12_15.REMAP_PORT_12 */ 10391 10392 rval = 0; 10393 soc_reg_field_set(unit, CMIC_LEDUP1_PORT_ORDER_REMAP_12_15r, &rval, REMAP_PORT_15f, 17); 10394 soc_reg_field_set(unit, CMIC_LEDUP1_PORT_ORDER_REMAP_12_15r, &rval, REMAP_PORT_14f, 18); 10395 soc_reg_field_set(unit, CMIC_LEDUP1_PORT_ORDER_REMAP_12_15r, &rval, REMAP_PORT_13f, 19); 10396 soc_reg_field_set(unit, CMIC_LEDUP1_PORT_ORDER_REMAP_12_15r, &rval, REMAP_PORT_12f, 20); 10397 /* coverity[result_independent_of_operands] */ 10398 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP1_PORT_ORDER_REMAP_12_15r(unit, rval)); 10399 10400 10401 /* d1 WC-C0/17/0 CMIC_LEDUP1_PORT_ORDER_REMAP_8_11.REMAP_PORT_11 */ 10402 /* d1 WC-C0/17/1 CMIC_LEDUP1_PORT_ORDER_REMAP_8_11.REMAP_PORT_10 */ 10403 /* d1 WC-C0/17/2 CMIC_LEDUP1_PORT_ORDER_REMAP_8_11.REMAP_PORT_9 */ 10404 /* d1 WC-C0/17/3, WC-C0/16/4 CMIC_LEDUP1_PORT_ORDER_REMAP_8_11.REMAP_PORT_8 */ 10405 10406 rval = 0; 10407 soc_reg_field_set(unit, CMIC_LEDUP1_PORT_ORDER_REMAP_8_11r, &rval, REMAP_PORT_11f, 21); 10408 soc_reg_field_set(unit, CMIC_LEDUP1_PORT_ORDER_REMAP_8_11r, &rval, REMAP_PORT_10f, 22); 10409 soc_reg_field_set(unit, CMIC_LEDUP1_PORT_ORDER_REMAP_8_11r, &rval, REMAP_PORT_9f, 23); 10410 soc_reg_field_set(unit, CMIC_LEDUP1_PORT_ORDER_REMAP_8_11r, &rval, REMAP_PORT_8f, 24); 10411 /* coverity[result_independent_of_operands] */ 10412 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP1_PORT_ORDER_REMAP_8_11r(unit, rval)); 10413 10414 10415 /* d5 WC-C0/18/0 CMIC_LEDUP1_PORT_ORDER_REMAP_4_7.REMAP_PORT_7 */ 10416 /* d5 WC-C0/18/1 CMIC_LEDUP1_PORT_ORDER_REMAP_4_7.REMAP_PORT_6 */ 10417 /* d5 WC-C0/18/2 CMIC_LEDUP1_PORT_ORDER_REMAP_4_7.REMAP_PORT_5 */ 10418 /* d5 WC-C0/18/3, WC-C0/16/4 CMIC_LEDUP1_PORT_ORDER_REMAP_4_7.REMAP_PORT_4 */ 10419 10420 rval = 0; 10421 soc_reg_field_set(unit, CMIC_LEDUP1_PORT_ORDER_REMAP_4_7r, &rval, REMAP_PORT_7f, 25); 10422 soc_reg_field_set(unit, CMIC_LEDUP1_PORT_ORDER_REMAP_4_7r, &rval, REMAP_PORT_6f, 26); 10423 soc_reg_field_set(unit, CMIC_LEDUP1_PORT_ORDER_REMAP_4_7r, &rval, REMAP_PORT_5f, 27); 10424 soc_reg_field_set(unit, CMIC_LEDUP1_PORT_ORDER_REMAP_4_7r, &rval, REMAP_PORT_4f, 28); 10425 /* coverity[result_independent_of_operands] */ 10426 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP1_PORT_ORDER_REMAP_4_7r(unit, rval)); 10427 10428 10429 /* d9 WC-C0/19/0 CMIC_LEDUP1_PORT_ORDER_REMAP_0_3.REMAP_PORT_3 */ 10430 /* d9 WC-C0/19/1 CMIC_LEDUP1_PORT_ORDER_REMAP_0_3.REMAP_PORT_2 */ 10431 /* d9 WC-C0/19/2 CMIC_LEDUP1_PORT_ORDER_REMAP_0_3.REMAP_PORT_1 */ 10432 /* d9 WC-C0/19/3, WC-C0/16/4 CMIC_LEDUP1_PORT_ORDER_REMAP_0_3.REMAP_PORT_0 */ 10433 10434 rval = 0; 10435 soc_reg_field_set(unit, CMIC_LEDUP1_PORT_ORDER_REMAP_0_3r, &rval, REMAP_PORT_3f, 29); 10436 soc_reg_field_set(unit, CMIC_LEDUP1_PORT_ORDER_REMAP_0_3r, &rval, REMAP_PORT_2f, 30); 10437 soc_reg_field_set(unit, CMIC_LEDUP1_PORT_ORDER_REMAP_0_3r, &rval, REMAP_PORT_1f, 31); 10438 soc_reg_field_set(unit, CMIC_LEDUP1_PORT_ORDER_REMAP_0_3r, &rval, REMAP_PORT_0f, 32); 10439 /* coverity[result_independent_of_operands] */ 10440 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP1_PORT_ORDER_REMAP_0_3r(unit, rval)); 10441 10442 10443 /* 10444 Raw SCHAN ops due to missing blocks in certain SKUs 10445 PORT_LED_CHAIN_CONFIGr 10446 set rcerror=0 10447 schan 0x34d00200 0x02029700 0x00000002 10448 schan 0x34f00200 0x02029700 0x00000002 10449 schan 0x34e00200 0x02029700 0x00000002 10450 set rcerror=1 10451 */ 10452 10453 { 10454 _soc_reg32_set(unit, 0x8,0, (0x02029700), (0x00000002)); 10455 _soc_reg32_set(unit, 0x9,0, (0x02029700), (0x00000002)); 10456 _soc_reg32_set(unit, 0xa,0, (0x02029700), (0x00000002)); 10457 _soc_reg32_set(unit, 0xb,0, (0x02029700), (0x00000002)); 10458 _soc_reg32_set(unit, 0xc,0, (0x02029700), (0x00000002)); 10459 _soc_reg32_set(unit, 0xd,0, (0x02029700), (0x00000002)); 10460 _soc_reg32_set(unit, 0xe,0, (0x02029700), (0x00000002)); 10461 _soc_reg32_set(unit, 0xf,0, (0x02029700), (0x00000002)); 10462 } 10463 10464 /* initialize the UP0, UP1 data ram */ 10465 rval = 0; 10466 for (ix = 0; ix < 256; ix++) { 10467 /* coverity[result_independent_of_operands] */ 10468 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP0_DATA_RAMr(unit,ix, rval)); 10469 /* coverity[result_independent_of_operands] */ 10470 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP1_DATA_RAMr(unit,ix, rval)); 10471 } 10472 return SOC_E_NONE; 10473 } 10474 10475 #ifdef BCM_HELIX4_SUPPORT 10476 extern int (*_phy_wc40_firmware_set_helper[SOC_MAX_NUM_DEVICES])(int, int, uint8 *,int); 10477 10478 int 10479 _hx4_wc40_firmware_set(int unit, int port, uint8 *array,int datalen) 10480 { 10481 return soc_warpcore_firmware_set(unit, port, array, datalen, 0, 10482 PORT_WC_UCMEM_DATAm, 10483 PORT_WC_UCMEM_CTRLr); 10484 } 10485 #endif /* BCM_HELIX4_SUPPORT */ 10486 10487 extern int (*_phy_wcmod_firmware_set_helper[SOC_MAX_NUM_DEVICES])(int, int, uint8 *,int); 10488 10489 STATIC int 10490 tr3_wc_firmware_set(int unit, int port, uint8 *array, int datalen) 10491 { 10492 int blk, phy_port, wc_inst; 10493 10494 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 10495 blk = SOC_PORT_BLOCK(unit, phy_port); 10496 10497 /* Which WC in this port block? 10498 * Find port offset, then divide by 4 (lanes per WC) 10499 */ 10500 if ((phy_port < _soc_tr3_b2pp[blk]) || 10501 (phy_port >= (_soc_tr3_b2pp[blk] + 12))) { 10502 return SOC_E_INTERNAL; 10503 } 10504 wc_inst = (phy_port - _soc_tr3_b2pp[blk]) / 4; 10505 10506 10507 return soc_warpcore_firmware_set(unit, port, array, datalen, wc_inst, 10508 PORT_WC_UCMEM_DATAm, 10509 PORT_WC_UCMEM_CTRLr); 10510 } 10511 10512 int 10513 soc_tr3_port_lanes_gen(int unit, soc_port_t port, int *lanes, soc_block_type_t *pbt) 10514 { 10515 uint8 match = 0; 10516 int i, blk, blk_num, p, rv = SOC_E_PORT; 10517 soc_info_t *si = &SOC_INFO(unit); 10518 int phy = si->port_l2p_mapping[port]; 10519 10520 LOG_VERBOSE(BSL_LS_SOC_COMMON, 10521 (BSL_META_U(unit, 10522 "Get lane, port: %d\n"), port)); 10523 *lanes = -1; 10524 if (pbt) { 10525 *pbt = SOC_BLK_NONE; 10526 } 10527 if (IS_CL_PORT(unit, port) && (IS_C_PORT(unit, port) || 10528 (si->port_speed_max[port] > 106000))) { 10529 *lanes = 12; 10530 if (si->port_speed_max[port] <= 106000) { 10531 *lanes = 10; 10532 } 10533 rv = SOC_E_NONE; 10534 LOG_VERBOSE(BSL_LS_SOC_COMMON, 10535 (BSL_META_U(unit, 10536 "CE\n"))); 10537 LOG_VERBOSE(BSL_LS_SOC_COMMON, 10538 (BSL_META_U(unit, 10539 ": %d\n"), *lanes)); 10540 return rv; 10541 } 10542 SOC_BLOCK_ITER(unit, blk, SOC_BLK_XLPORT) { 10543 blk_num = SOC_BLOCK_INFO(unit, blk).number; 10544 for (i = 0; i < 4; i++) { 10545 p = si->flex_port_p2l_mapping[_soc_tr3_b2pp[blk]+i]; 10546 if (p < 0) { 10547 continue; 10548 } 10549 if (p == port) { 10550 match = 1; 10551 break; 10552 } 10553 } 10554 if (!match) { 10555 continue; 10556 } 10557 if (si->port_speed_max[port] == -1) { 10558 break; 10559 } 10560 LOG_VERBOSE(BSL_LS_SOC_COMMON, 10561 (BSL_META_U(unit, 10562 "XL\n"))); 10563 if (pbt) { 10564 *pbt = SOC_BLK_XLPORT; 10565 } 10566 rv = SOC_E_NONE; 10567 if (blk_num == 0) { 10568 *lanes = 1; 10569 } else { 10570 *lanes = 1; 10571 if (si->port_speed_max[port] > 11000) { 10572 *lanes = 2; 10573 } 10574 if (si->port_speed_max[port] > 21000) { 10575 *lanes = 4; 10576 } 10577 } 10578 break; 10579 } 10580 if (!match) { 10581 SOC_BLOCK_ITER(unit, blk, SOC_BLK_XTPORT) { 10582 for (i = 0; i < 12; i++) { 10583 p = si->flex_port_p2l_mapping[_soc_tr3_b2pp[blk]+i]; 10584 if (p < 0) { 10585 continue; 10586 } 10587 if (p == port) { 10588 match = 1; 10589 break; 10590 } 10591 } 10592 if (!match) { 10593 continue; 10594 } 10595 if (si->port_speed_max[port] == -1) { 10596 break; 10597 } 10598 LOG_VERBOSE(BSL_LS_SOC_COMMON, 10599 (BSL_META_U(unit, 10600 "XT\n"))); 10601 if (pbt) { 10602 *pbt = SOC_BLK_XTPORT; 10603 } 10604 rv = SOC_E_NONE; 10605 *lanes = 1; 10606 if (SOC_IS_HELIX4(unit)) { 10607 if (si->port_speed_max[port] > 1000) { 10608 *lanes = 4; 10609 } 10610 } else { 10611 if (si->port_speed_max[port] > 3000) { 10612 *lanes = 4; 10613 } 10614 } 10615 break; 10616 } 10617 } 10618 if (!match) { 10619 SOC_BLOCK_ITER(unit, blk, SOC_BLK_XWPORT) { 10620 uint8 d_0 = 0, d_1 = 0; 10621 for (i = 0; i < 4; i++) { 10622 p = si->flex_port_p2l_mapping[_soc_tr3_b2pp[blk]+i]; 10623 if (p < 0) { 10624 continue; 10625 } 10626 if (p == port) { 10627 match = 1; 10628 if (i == 0) { 10629 d_0 = 1; 10630 } else if (i == 2) { 10631 d_1 = 1; 10632 } 10633 break; 10634 } 10635 } 10636 if (!match) { 10637 continue; 10638 } 10639 if (si->port_speed_max[port] == -1) { 10640 break; 10641 } 10642 LOG_VERBOSE(BSL_LS_SOC_COMMON, 10643 (BSL_META_U(unit, 10644 "XW\n"))); 10645 if (pbt) { 10646 *pbt = SOC_BLK_XWPORT; 10647 } 10648 rv = SOC_E_NONE; 10649 *lanes = 1; 10650 if (si->port_speed_max[port] >= 10000 && si->port_speed_max[port] <= 12000) { 10651 switch (i) { 10652 case 0: 10653 *lanes = 4; 10654 if (((si->flex_port_p2l_mapping[phy + 1] >= 0) && 10655 (si->flex_port_p2l_mapping[phy + 2] >= 0) && 10656 (si->flex_port_p2l_mapping[phy + 3] >= 0)) || 10657 ((si->flex_port_p2l_mapping[phy + 1] >= 0) && 10658 (si->flex_port_p2l_mapping[phy + 2] < 0) && 10659 (si->flex_port_p2l_mapping[phy + 3] < 0))) { 10660 *lanes = 1; 10661 } else if ((si->flex_port_p2l_mapping[phy + 1] < 0) && 10662 (si->flex_port_p2l_mapping[phy + 2] >= 0) && 10663 (si->flex_port_p2l_mapping[phy + 3] < 0)) { 10664 *lanes = 2; 10665 } 10666 break; 10667 case 1: 10668 *lanes = 4; 10669 if (((si->flex_port_p2l_mapping[phy - 1] >= 0) && 10670 (si->flex_port_p2l_mapping[phy + 1] >= 0) && 10671 (si->flex_port_p2l_mapping[phy + 2] >= 0)) || 10672 ((si->flex_port_p2l_mapping[phy - 1] >= 0) && 10673 (si->flex_port_p2l_mapping[phy + 1] < 0) && 10674 (si->flex_port_p2l_mapping[phy + 2] < 0))) { 10675 *lanes = 1; 10676 } 10677 break; 10678 case 2: 10679 *lanes = 4; 10680 if ((si->flex_port_p2l_mapping[phy - 2] >= 0) && 10681 (si->flex_port_p2l_mapping[phy - 1] >= 0) && 10682 (si->flex_port_p2l_mapping[phy + 1] >= 0)) { 10683 *lanes = 1; 10684 } else if ((si->flex_port_p2l_mapping[phy - 2] >= 0) && 10685 (si->flex_port_p2l_mapping[phy - 1] < 0) && 10686 (si->flex_port_p2l_mapping[phy + 1] < 0)) { 10687 *lanes = 2; 10688 } 10689 break; 10690 case 3: 10691 *lanes = 4; 10692 if ((si->flex_port_p2l_mapping[phy - 3] >= 0) && 10693 (si->flex_port_p2l_mapping[phy - 2] >= 0) && 10694 (si->flex_port_p2l_mapping[phy - 1] >= 0)) { 10695 *lanes = 1; 10696 } 10697 break; 10698 } 10699 } else if (si->port_speed_max[port] > 12000) { 10700 *lanes = 4; 10701 10702 if ((d_0 || d_1) && (si->port_speed_max[port] <= 25000)) { 10703 int dual_pair; 10704 if (d_0) { 10705 #ifdef BCM_HELIX4_SUPPORT 10706 if ( SOC_IS_HELIX4(unit) && ((_tr3_port_config_id[unit] == 463)|| 10707 (_tr3_port_config_id[unit] == 413)) && 10708 (57 == si->port_l2p_mapping[port] || 61 == si->port_l2p_mapping[port])){ 10709 *lanes = 2; 10710 }else 10711 10712 #endif 10713 { 10714 dual_pair = si->flex_port_p2l_mapping[phy + 2]; 10715 if (dual_pair >= 0) { 10716 if (si->port_speed_max[dual_pair] > 0) { /* HGd */ 10717 *lanes = 2; 10718 } 10719 } 10720 } 10721 } else if (d_1) { 10722 dual_pair = si->flex_port_p2l_mapping[phy - 2]; 10723 if (dual_pair >= 0) { 10724 if (si->port_speed_max[dual_pair] > 0) { /* HGd */ 10725 *lanes = 2; 10726 } 10727 } 10728 } 10729 } 10730 } 10731 break; 10732 } 10733 } 10734 if (!match) { 10735 SOC_BLOCK_ITER(unit, blk, SOC_BLK_CLPORT) { 10736 uint8 d_0 = 0, d_1 = 0; 10737 for (i = 0; i < 12; i++) { 10738 p = si->flex_port_p2l_mapping[_soc_tr3_b2pp[blk]+i]; 10739 if (p < 0) { 10740 continue; 10741 } 10742 if (p == port) { 10743 match = 1; 10744 if (i == 0 || i == 4 || i == 8) { 10745 d_0 = 1; 10746 } else if (i == 2 || i == 6 || i == 10) { 10747 d_1 = 1; 10748 } 10749 break; 10750 } 10751 } 10752 if (!match) { 10753 continue; 10754 } 10755 if (si->port_speed_max[port] == -1) { 10756 break; 10757 } 10758 LOG_VERBOSE(BSL_LS_SOC_COMMON, 10759 (BSL_META_U(unit, 10760 "CL\n"))); 10761 if (pbt) { 10762 *pbt = SOC_BLK_CLPORT; 10763 } 10764 rv = SOC_E_NONE; 10765 *lanes = 1; 10766 10767 if (si->port_speed_max[port] >= 10000 && si->port_speed_max[port] <= 12000) { 10768 switch (i%4) { 10769 case 0: 10770 *lanes = 4; 10771 if ((si->flex_port_p2l_mapping[phy + 1] >= 0) && 10772 (si->flex_port_p2l_mapping[phy + 2] >= 0) && 10773 (si->flex_port_p2l_mapping[phy + 3] >= 0)) { 10774 *lanes = 1; 10775 } else if ((si->flex_port_p2l_mapping[phy + 1] < 0) && 10776 (si->flex_port_p2l_mapping[phy + 2] >= 0) && 10777 (si->flex_port_p2l_mapping[phy + 3] < 0)) { 10778 *lanes = 2; 10779 } else if (_tr3_port_config_id[unit] == 99) { /* 2xXFI case */ 10780 if ((si->flex_port_p2l_mapping[phy + 1] >= 0) && 10781 (si->flex_port_p2l_mapping[phy + 2] < 0) && 10782 (si->flex_port_p2l_mapping[phy + 3] < 0)) { 10783 *lanes = 1; 10784 } 10785 } else if(_tr3_port_config_id[unit] == 112 || 10786 _tr3_port_config_id[unit] == 12) { 10787 *lanes = 1; 10788 } 10789 break; 10790 case 1: 10791 *lanes = 4; 10792 if ((si->flex_port_p2l_mapping[phy - 1] >= 0) && 10793 (si->flex_port_p2l_mapping[phy + 1] >= 0) && 10794 (si->flex_port_p2l_mapping[phy + 2] >= 0)) { 10795 *lanes = 1; 10796 } else if (_tr3_port_config_id[unit] == 99) { /* 2xXFI case */ 10797 if ((si->flex_port_p2l_mapping[phy - 1] >= 0) && 10798 (si->flex_port_p2l_mapping[phy + 1] < 0) && 10799 (si->flex_port_p2l_mapping[phy + 2] < 0)) { 10800 *lanes = 1; 10801 } 10802 } 10803 break; 10804 case 2: 10805 *lanes = 4; 10806 if ((si->flex_port_p2l_mapping[phy - 2] >= 0) && 10807 (si->flex_port_p2l_mapping[phy - 1] >= 0) && 10808 (si->flex_port_p2l_mapping[phy + 1] >= 0)) { 10809 *lanes = 1; 10810 } else if ((si->flex_port_p2l_mapping[phy - 2] >= 0) && 10811 (si->flex_port_p2l_mapping[phy - 1] < 0) && 10812 (si->flex_port_p2l_mapping[phy + 1] < 0)) { 10813 *lanes = 2; 10814 } 10815 break; 10816 case 3: 10817 *lanes = 4; 10818 if ((si->flex_port_p2l_mapping[phy - 3] >= 0) && 10819 (si->flex_port_p2l_mapping[phy - 2] >= 0) && 10820 (si->flex_port_p2l_mapping[phy - 1] >= 0)) { 10821 *lanes = 1; 10822 } 10823 break; 10824 } 10825 } else if (si->port_speed_max[port] > 12000) { 10826 *lanes = 4; 10827 if ((d_0 || d_1) && (si->port_speed_max[port] <= 25000)) { 10828 int dual_pair; 10829 if (d_0) { 10830 dual_pair = si->flex_port_p2l_mapping[phy + 2]; 10831 if (dual_pair >= 0) { 10832 if (si->port_speed_max[dual_pair] > 0) { /* HGd */ 10833 *lanes = 2; 10834 } 10835 } 10836 } else if (d_1) { 10837 dual_pair = si->flex_port_p2l_mapping[phy - 2]; 10838 if (dual_pair >= 0) { 10839 if (si->port_speed_max[dual_pair] > 0) { /* HGd */ 10840 *lanes = 2; 10841 } 10842 } 10843 } 10844 } 10845 } 10846 break; 10847 } 10848 } 10849 LOG_VERBOSE(BSL_LS_SOC_COMMON, 10850 (BSL_META_U(unit, 10851 ": %d\n"), *lanes)); 10852 return rv; 10853 } 10854 10855 int 10856 soc_tr3_port_lanes_get(int unit, soc_port_t port, int *lanes) 10857 { 10858 if (!SOC_PORT_VALID(unit, port)) { 10859 return SOC_E_PORT; 10860 } 10861 *lanes = SOC_INFO(unit).port_num_lanes[port]; 10862 return SOC_E_NONE; 10863 } 10864 10865 #define _SOC_TR3_LCPLL0 0 10866 #define _SOC_TR3_LCPLL1 1 10867 #define _SOC_TR3_COREPLL 2 10868 #define _SOC_TR3_STOP_CLK 1 10869 #define _SOC_TR3_START_CLK 0 10870 10871 STATIC int 10872 _soc_tr3_hx4_clock_sync(int unit, int pll, int port, int stop_clk) { 10873 uint32 rval; 10874 10875 sal_usleep(10000); 10876 if (SOC_IS_HELIX4(unit)) { 10877 LOG_VERBOSE(BSL_LS_SOC_COMMON, 10878 (BSL_META_U(unit, 10879 "%s called with port %d (stop_clk = %d)\n"), 10880 FUNCTION_NAME(), port, stop_clk)); 10881 switch (pll) { 10882 case _SOC_TR3_LCPLL0: 10883 SOC_IF_ERROR_RETURN(READ_TOP_XG_PLL0_CTRL_1r(unit, &rval)); 10884 soc_reg_field_set(unit, TOP_XG_PLL0_CTRL_1r, &rval, HOLD_CHf, stop_clk ? 0x10 : 0); 10885 SOC_IF_ERROR_RETURN(WRITE_TOP_XG_PLL0_CTRL_1r(unit, rval)); 10886 break; 10887 case _SOC_TR3_LCPLL1: 10888 SOC_IF_ERROR_RETURN(READ_TOP_XG_PLL1_CTRL_1r(unit, &rval)); 10889 soc_reg_field_set(unit, TOP_XG_PLL1_CTRL_1r, &rval, HOLD_CHf, stop_clk ? 0x10 : 0); 10890 SOC_IF_ERROR_RETURN(WRITE_TOP_XG_PLL1_CTRL_1r(unit, rval)); 10891 break; 10892 default: 10893 break; 10894 } 10895 } 10896 else if (SOC_IS_TRIUMPH3(unit)) { 10897 /*TR3 same CORE_PLL ch1 provides mac_cclk for XLP and CLP*/ 10898 if (pll == _SOC_TR3_COREPLL) { 10899 SOC_IF_ERROR_RETURN(READ_TOP_CORE_PLL_CTRL2r(unit, &rval)); 10900 soc_reg_field_set(unit, TOP_CORE_PLL_CTRL2r, &rval, HOLD_CH1f, stop_clk ? 1 : 0); 10901 SOC_IF_ERROR_RETURN(WRITE_TOP_CORE_PLL_CTRL2r(unit, rval)); 10902 } 10903 } 10904 sal_usleep(10000); 10905 10906 10907 return SOC_E_NONE; 10908 } 10909 10910 STATIC void 10911 _soc_ser_init_sync(int unit, soc_mem_t mem) 10912 { 10913 uint32 *tbl_chnk; 10914 int rv, buf_size, chunksize; 10915 int chnk_idx, chnk_idx_max, mem_idx_max; 10916 chunksize = 256; 10917 buf_size = 4 * SOC_MAX_MEM_WORDS * chunksize; 10918 tbl_chnk = soc_cm_salloc(unit, buf_size, "cache sync"); 10919 10920 if (!SOC_MEM_IS_VALID(unit, mem)) { 10921 return; 10922 } 10923 if (NULL == tbl_chnk) { 10924 LOG_ERROR(BSL_LS_SOC_COMMON, 10925 (BSL_META_U(unit, 10926 "SW cache sync failed !!\n"))); 10927 return; 10928 } 10929 10930 mem_idx_max = soc_mem_index_max(unit, mem); 10931 MEM_LOCK(unit, mem); 10932 for (chnk_idx = soc_mem_index_min(unit, mem); 10933 chnk_idx <= mem_idx_max; chnk_idx += chunksize) { 10934 10935 sal_memset((void *)tbl_chnk, 0, buf_size); 10936 chnk_idx_max = ((chnk_idx + chunksize) <= mem_idx_max) ? 10937 (chnk_idx + chunksize - 1) : mem_idx_max; 10938 rv = soc_mem_read_range(unit, mem, MEM_BLOCK_ANY, chnk_idx, 10939 chnk_idx_max, tbl_chnk); 10940 if (SOC_FAILURE(rv)) { 10941 LOG_ERROR(BSL_LS_SOC_COMMON, 10942 (BSL_META_U(unit, 10943 "DMA failure during cache sync for %s mem\n"), 10944 SOC_MEM_NAME(unit, mem))); 10945 10946 MEM_UNLOCK(unit, mem); 10947 soc_cm_sfree(unit, tbl_chnk); 10948 return; 10949 } 10950 soc_mem_write_range(unit, mem, MEM_BLOCK_ANY, chnk_idx, 10951 chnk_idx_max, tbl_chnk); 10952 } 10953 MEM_UNLOCK(unit, mem); 10954 soc_cm_sfree(unit, tbl_chnk); 10955 } 10956 10957 #if defined(SER_TR_TEST_SUPPORT) 10958 soc_ser_test_functions_t ser_triumph3_test_fun; 10959 #endif 10960 10961 int 10962 _soc_tr3_misc_init(int unit) 10963 { 10964 static const soc_field_t port_field[] = { 10965 PORT0f, PORT1f, PORT2f, PORT3f, 10966 PORT4f, PORT5f, PORT6f, PORT7f, 10967 PORT8f, PORT9f, PORT10f, PORT11f 10968 }; 10969 static const soc_field_t core_mode_field[] = { 10970 XPORT0_CORE_PORT_MODEf, 10971 XPORT1_CORE_PORT_MODEf, 10972 XPORT2_CORE_PORT_MODEf 10973 }; 10974 static const soc_field_t phy_mode_field[] = { 10975 XPORT0_PHY_PORT_MODEf, 10976 XPORT1_PHY_PORT_MODEf, 10977 XPORT2_PHY_PORT_MODEf 10978 }; 10979 static const soc_field_t xpc_gmii_enable_field[] = { 10980 XPC0_GMII_MII_ENABLEf, 10981 XPC1_GMII_MII_ENABLEf, 10982 XPC2_GMII_MII_ENABLEf 10983 }; 10984 static const soc_field_t vfp_tcam_blksel_field[] = { 10985 SLICE_3_Uf, SLICE_3_Lf, SLICE_2_Uf, SLICE_2_Lf, 10986 SLICE_1_Uf, SLICE_1_Lf, SLICE_0_Uf, SLICE_0_Lf 10987 }; 10988 static const soc_field_t efp_tcam_blksel_field[] = { 10989 SLICE_3f, SLICE_2f, 10990 SLICE_1f, SLICE_0f 10991 }; 10992 soc_info_t *si; 10993 uint64 val64; 10994 uint32 rval, entry[SOC_MAX_MEM_WORDS], tmpval; 10995 soc_pbmp_t pbmp; 10996 int speed, divisor, dividend, delay; 10997 int i, axp, lpt, port, phy_port, blk, blk_num, bindex; 10998 int parity_enable, phy, lane, port_attr, maxsp = 8; 10999 uint32 mac_mode = MAC_MODE_INDEP, core_mode[3], phy_mode[3]; 11000 uint16 cl_port_valid[2], xt_port_valid[4], xl_port_valid[2], xw_port_valid[3]; 11001 #ifdef BCM_ISM_SUPPORT 11002 int total, rv = SOC_E_NONE; 11003 uint8 banks[_SOC_ISM_MAX_BANKS], count; 11004 uint32 bank_size[_SOC_ISM_MAX_BANKS]; 11005 #endif 11006 uint16 dev_id; 11007 uint8 rev_id; 11008 soc_field_t fields[2]; 11009 uint32 values[2]; 11010 uint32 hash_control; 11011 static int rtag7_field_width[] = { 16, 16, 4, 16, 8, 8, 16, 16 }; 11012 int index, index_count, sub_sel, offset, mtufield_len; 11013 int higig2 = 0; 11014 11015 si = &SOC_INFO(unit); 11016 soc_cm_get_id(unit, &dev_id, &rev_id); 11017 11018 if (SAL_BOOT_QUICKTURN) { 11019 sop_memstate_t *memState; 11020 11021 memState = SOC_PERSIST(unit)->memState; 11022 memState[L2_USER_ENTRYm].index_max = 7; 11023 memState[MY_STATION_TCAMm].index_max = 7; 11024 } 11025 11026 /* Stop the mem scan task before all of the parity init takes place */ 11027 SOC_IF_ERROR_RETURN(soc_generic_ser_mem_scan_stop(unit)); 11028 11029 parity_enable = soc_property_get(unit, spn_PARITY_ENABLE, TRUE); 11030 11031 if (parity_enable) { 11032 #ifdef BCM_HELIX4_SUPPORT 11033 if (SOC_IS_HELIX4(unit)) { 11034 (void)_soc_hx4_tcam_ser_init(unit); 11035 /* SER list registration moved into HX4 init because 11036 * SER TCAM info structure isn't in this file's scope. */ 11037 } else 11038 #endif /* BCM_HELIX4_SUPPORT */ 11039 { 11040 (void)_soc_tr3_ser_init(unit); 11041 #ifdef INCLUDE_MEM_SCAN 11042 soc_mem_scan_ser_list_register(unit, FALSE, 11043 _soc_tr3_ser_parity_info[unit]); 11044 #endif /* INCLUDE_MEM_SCAN */ 11045 } 11046 _soc_ser_init_sync(unit, MMU_MTRO_L0_MEMm); 11047 _soc_ser_init_sync(unit, MMU_MTRO_L1_MEMm); 11048 _soc_ser_init_sync(unit, MMU_MTRO_L2_MEMm); 11049 SOC_SER_SUPPORT(unit) = 1; 11050 memset(&_tr3_ser_functions, 0, sizeof(soc_ser_functions_t)); 11051 _tr3_ser_functions._soc_ser_fail_f = &soc_tr3_ser_fail; 11052 _tr3_ser_functions._soc_ser_parity_error_cmicm_intr_f = 11053 &soc_tr3_process_func_intr; 11054 soc_ser_function_register(unit, &_tr3_ser_functions); 11055 11056 #if defined(SER_TR_TEST_SUPPORT) 11057 /*Initialize chip-specific functions for SER testing*/ 11058 memset(&ser_triumph3_test_fun, 0, sizeof(soc_ser_test_functions_t)); 11059 ser_triumph3_test_fun.inject_error_f = &soc_tr3_ser_inject_error; 11060 ser_triumph3_test_fun.test_mem = &soc_tr3_ser_test_mem; 11061 ser_triumph3_test_fun.test = &soc_tr3_ser_test; 11062 ser_triumph3_test_fun.injection_support = &soc_tr3_ser_error_injection_support; 11063 soc_ser_test_functions_register(unit, &ser_triumph3_test_fun); 11064 #endif /*defined(SER_TR_TEST_SUPPORT*/ 11065 } 11066 11067 #ifdef BCM_HELIX4_SUPPORT 11068 if (soc_feature(unit, soc_feature_l3_expanded_defip_table)) { 11069 /* 11070 * Enable DEFIP CAMs for HElix4 variants. 11071 * each bit corresponds a pair of tcams 11072 */ 11073 if (soc_feature(unit, soc_feature_l3_32k_defip_table)) { 11074 /* Enable only 16 Tcams for Firescout. rest will be powered off */ 11075 soc_reg32_set(unit, L3_DEFIP_CAM_ENABLEr, REG_PORT_ANY, 0, 0xFF); 11076 } else { 11077 /* Enable only 8 tcams for HX4 variant */ 11078 soc_reg32_set(unit, L3_DEFIP_CAM_ENABLEr, REG_PORT_ANY, 0, 0xF); 11079 } 11080 } 11081 #endif /* BCM_HELIX4_SUPPORT */ 11082 11083 SOC_IF_ERROR_RETURN 11084 (soc_reg_field32_modify(unit, 11085 IFP_METER_WRITE_LAST_REFRESH_NUMBERr, 11086 REG_PORT_ANY, WRITE_ENf, 1)); 11087 SOC_IF_ERROR_RETURN 11088 (soc_reg_field32_modify(unit, ING_SVM_CONTROLr, REG_PORT_ANY, 11089 DISABLE_CPU_WRITE_TO_LAST_REFRESH_NUMBERf, 0)); 11090 11091 if (!SOC_IS_RELOADING(unit) && !SOC_WARM_BOOT(unit)) { 11092 uint32 data[SOC_MAX_MEM_WORDS]; 11093 11094 SOC_IF_ERROR_RETURN(soc_tr3_mem_clear(unit)); 11095 11096 if (!SOC_IS_HELIX4(unit)) { 11097 11098 if (soc_feature(unit, soc_feature_global_meter)) { 11099 SOC_IF_ERROR_RETURN 11100 (soc_mem_read(unit, SVM_POLICY_TABLEm, MEM_BLOCK_ANY, 0, data)); 11101 } 11102 SOC_IF_ERROR_RETURN 11103 (soc_mem_read(unit, SVM_MACROFLOW_INDEX_TABLEm, MEM_BLOCK_ANY, 0, data)); 11104 SOC_IF_ERROR_RETURN 11105 (soc_mem_read(unit, ING_FLEX_CTR_OFFSET_TABLE_0m, MEM_BLOCK_ANY, 0, data)); 11106 SOC_IF_ERROR_RETURN 11107 (soc_mem_read(unit, ING_FLEX_CTR_OFFSET_TABLE_1m, MEM_BLOCK_ANY, 0, data)); 11108 SOC_IF_ERROR_RETURN 11109 (soc_mem_read(unit, ING_FLEX_CTR_OFFSET_TABLE_2m, MEM_BLOCK_ANY, 0, data)); 11110 SOC_IF_ERROR_RETURN 11111 (soc_mem_read(unit, ING_FLEX_CTR_OFFSET_TABLE_3m, MEM_BLOCK_ANY, 0, data)); 11112 SOC_IF_ERROR_RETURN 11113 (soc_mem_read(unit, ING_FLEX_CTR_OFFSET_TABLE_4m, MEM_BLOCK_ANY, 0, data)); 11114 SOC_IF_ERROR_RETURN 11115 (soc_mem_read(unit, ING_FLEX_CTR_OFFSET_TABLE_5m, MEM_BLOCK_ANY, 0, data)); 11116 SOC_IF_ERROR_RETURN 11117 (soc_mem_read(unit, ING_FLEX_CTR_OFFSET_TABLE_6m, MEM_BLOCK_ANY, 0, data)); 11118 SOC_IF_ERROR_RETURN 11119 (soc_mem_read(unit, ING_FLEX_CTR_OFFSET_TABLE_7m, MEM_BLOCK_ANY, 0, data)); 11120 switch (dev_id) { 11121 case BCM56640_DEVICE_ID: 11122 case BCM56643_DEVICE_ID: 11123 case BCM56644_DEVICE_ID: 11124 case BCM56648_DEVICE_ID: 11125 case BCM56649_DEVICE_ID: 11126 SOC_IF_ERROR_RETURN 11127 (soc_mem_read(unit, ING_FLEX_CTR_OFFSET_TABLE_8m, MEM_BLOCK_ANY, 0, data)); 11128 SOC_IF_ERROR_RETURN 11129 (soc_mem_read(unit, ING_FLEX_CTR_OFFSET_TABLE_9m, MEM_BLOCK_ANY, 0, data)); 11130 SOC_IF_ERROR_RETURN 11131 (soc_mem_read(unit, ING_FLEX_CTR_OFFSET_TABLE_10m, MEM_BLOCK_ANY, 0, data)); 11132 SOC_IF_ERROR_RETURN 11133 (soc_mem_read(unit, ING_FLEX_CTR_OFFSET_TABLE_11m, MEM_BLOCK_ANY, 0, data)); 11134 SOC_IF_ERROR_RETURN 11135 (soc_mem_read(unit, ING_FLEX_CTR_OFFSET_TABLE_12m, MEM_BLOCK_ANY, 0, data)); 11136 SOC_IF_ERROR_RETURN 11137 (soc_mem_read(unit, ING_FLEX_CTR_OFFSET_TABLE_13m, MEM_BLOCK_ANY, 0, data)); 11138 SOC_IF_ERROR_RETURN 11139 (soc_mem_read(unit, ING_FLEX_CTR_OFFSET_TABLE_14m, MEM_BLOCK_ANY, 0, data)); 11140 SOC_IF_ERROR_RETURN 11141 (soc_mem_read(unit, ING_FLEX_CTR_OFFSET_TABLE_15m, MEM_BLOCK_ANY, 0, data)); 11142 break; 11143 default: 11144 break; 11145 } 11146 } 11147 } 11148 11149 SOC_IF_ERROR_RETURN 11150 (soc_reg_field32_modify(unit, IFP_METER_WRITE_LAST_REFRESH_NUMBERr, 11151 REG_PORT_ANY, WRITE_ENf, 0)); 11152 SOC_IF_ERROR_RETURN 11153 (soc_reg_field32_modify(unit, ING_SVM_CONTROLr, REG_PORT_ANY, 11154 DISABLE_CPU_WRITE_TO_LAST_REFRESH_NUMBERf, 1)); 11155 11156 /* Read ESM config now as it effects ser init */ 11157 if (soc_feature(unit, soc_feature_esm_support)) { 11158 SOC_IF_ERROR_RETURN(soc_tr3_esm_init_read_config(unit)); 11159 } 11160 11161 /* Disable IBOD FIFO full interrupts */ 11162 SOC_IF_ERROR_RETURN(WRITE_IBOD_INTR_MASKr(unit, 0)); 11163 11164 (void)_soc_tr3_parity_enable_all(unit, parity_enable); 11165 if (!parity_enable) { 11166 /* Clear AXP SER calculations if parity isn't enabled */ 11167 SOC_IF_ERROR_RETURN(WRITE_AXP_SM_MEM_ECC_GEN_CONTROLr(unit, 0)); 11168 } 11169 11170 /* Disable unused flex counter pools */ 11171 switch (dev_id) { 11172 case BCM56540_DEVICE_ID: 11173 case BCM56541_DEVICE_ID: 11174 case BCM56542_DEVICE_ID: 11175 case BCM56543_DEVICE_ID: 11176 case BCM56544_DEVICE_ID: 11177 case BCM56545_DEVICE_ID: 11178 case BCM56546_DEVICE_ID: 11179 case BCM56044_DEVICE_ID: 11180 case BCM56045_DEVICE_ID: 11181 case BCM56046_DEVICE_ID: 11182 SOC_IF_ERROR_RETURN 11183 (soc_reg_field32_modify(unit, ING_FLEX_CTR_COUNTER_UPDATE_CONTROL_8r, 11184 REG_PORT_ANY, COUNTER_POOL_ENABLEf, 0)); 11185 SOC_IF_ERROR_RETURN 11186 (soc_reg_field32_modify(unit, ING_FLEX_CTR_COUNTER_UPDATE_CONTROL_9r, 11187 REG_PORT_ANY, COUNTER_POOL_ENABLEf, 0)); 11188 SOC_IF_ERROR_RETURN 11189 (soc_reg_field32_modify(unit, ING_FLEX_CTR_COUNTER_UPDATE_CONTROL_10r, 11190 REG_PORT_ANY, COUNTER_POOL_ENABLEf, 0)); 11191 SOC_IF_ERROR_RETURN 11192 (soc_reg_field32_modify(unit, ING_FLEX_CTR_COUNTER_UPDATE_CONTROL_11r, 11193 REG_PORT_ANY, COUNTER_POOL_ENABLEf, 0)); 11194 SOC_IF_ERROR_RETURN 11195 (soc_reg_field32_modify(unit, ING_FLEX_CTR_COUNTER_UPDATE_CONTROL_12r, 11196 REG_PORT_ANY, COUNTER_POOL_ENABLEf, 0)); 11197 SOC_IF_ERROR_RETURN 11198 (soc_reg_field32_modify(unit, ING_FLEX_CTR_COUNTER_UPDATE_CONTROL_13r, 11199 REG_PORT_ANY, COUNTER_POOL_ENABLEf, 0)); 11200 SOC_IF_ERROR_RETURN 11201 (soc_reg_field32_modify(unit, ING_FLEX_CTR_COUNTER_UPDATE_CONTROL_14r, 11202 REG_PORT_ANY, COUNTER_POOL_ENABLEf, 0)); 11203 SOC_IF_ERROR_RETURN 11204 (soc_reg_field32_modify(unit, ING_FLEX_CTR_COUNTER_UPDATE_CONTROL_15r, 11205 REG_PORT_ANY, COUNTER_POOL_ENABLEf, 0)); 11206 break; 11207 default: 11208 break; 11209 } 11210 11211 /* Enable Green mode power savings for Ranger+ */ 11212 switch (dev_id) { 11213 case BCM56044_DEVICE_ID: 11214 case BCM56045_DEVICE_ID: 11215 case BCM56046_DEVICE_ID: 11216 /* Disable unused ING_L3_NEXT_HOP table */ 11217 COMPILER_64_SET(val64, 0xffffffff, 0xffffff00); 11218 SOC_IF_ERROR_RETURN(WRITE_IRSEL2_NEXT_HOP_PDA_CONTROLr(unit, val64)); 11219 /* Disable unused EGR_L3_NEXT_HOP table */ 11220 SOC_IF_ERROR_RETURN(WRITE_EGR_L3_NEXT_HOP_PDA_CTRL0r(unit, 0xffff0000)); 11221 SOC_IF_ERROR_RETURN(WRITE_EGR_L3_NEXT_HOP_PDA_CTRL1r(unit, 0xffffffff)); 11222 SOC_IF_ERROR_RETURN(WRITE_EGR_L3_NEXT_HOP_PDA_CTRL2r(unit, 0xffffffff)); 11223 SOC_IF_ERROR_RETURN(WRITE_EGR_L3_NEXT_HOP_PDA_CTRL3r(unit, 0xffffffff)); 11224 /* Disable unused L3_IPMC table */ 11225 SOC_IF_ERROR_RETURN(WRITE_IRSEL2_IPMC_PDA_CONTROLr(unit, 0xfff0)); 11226 /* Disable unused LPM TCAM mems */ 11227 SOC_IF_ERROR_RETURN(WRITE_L3_DEFIP_CAM_DBGCTRL5r(unit, 0)); 11228 /* Disable comparison opeartions on unused VFP TCAM entries */ 11229 rval = 0; 11230 for (i = 0; i < 8; i++) { 11231 /* 11232 In VFP_TCAM_BLKSEL register 2 bits are allocated for each tcam 11233 in each slice.Setting lower bit enables comparison operation 11234 on upper half of the TCAM and setting upper bit enables 11235 comparison operation on lower half of the TCAM.In Ranger+ VFP, 11236 only 1/4th of total entries in a slice are used i.e In each slice 11237 lower half of upper TCAM and lower TCAM are unused. 11238 Since VFP has 4 slices and each slice has two tcams int it, this 11239 is looping 8 times. 11240 */ 11241 soc_reg_field_set(unit, VFP_TCAM_BLKSELr, &rval, 11242 vfp_tcam_blksel_field[i], 0x1); 11243 } 11244 SOC_IF_ERROR_RETURN(WRITE_VFP_TCAM_BLKSELr(unit, rval)); 11245 11246 /* Disable comparison opeartions on unused EFP TCAM entries */ 11247 rval = 0; 11248 for (i = 0; i < 4; i++) { 11249 /* 11250 In EFP_TCAM_BLKSEL register 2 bits are allocated for each tcam 11251 in each slice.Setting lower bit enables comparison operation 11252 on upper half of the TCAM and setting upper bit enables 11253 comparison operation on lower half of the TCAM.In Ranger+ EFP, 11254 only half of total entries in a slice are used i.e In each slice 11255 lower half of the single TCAM available is unused.Since EFP has 11256 4 slices ahd each slice has only single TCAM in it, this is 11257 looping 4 times. 11258 */ 11259 soc_reg_field_set(unit, EFP_TCAM_BLKSELr, &rval, 11260 efp_tcam_blksel_field[i], 0x1); 11261 } 11262 SOC_IF_ERROR_RETURN(WRITE_EFP_TCAM_BLKSELr(unit, rval)); 11263 break; 11264 default: 11265 break; 11266 } 11267 11268 #ifdef BCM_ISM_SUPPORT 11269 /* Main ISM h/w config */ 11270 rv = soc_ism_hw_config(unit); 11271 if (SOC_FAILURE(rv)) { 11272 LOG_ERROR(BSL_LS_SOC_COMMON, 11273 (BSL_META_U(unit, 11274 "Error configuring ISM h/w !!\n"))); 11275 return rv; 11276 } 11277 /* During warmboot hash config get and hash offset config get is 11278 * performed in soc_do_init*/ 11279 if (!SOC_WARM_BOOT(unit)) { 11280 /* Misc ISM h/w configs */ 11281 rv = soc_ism_table_hash_config(unit, SOC_ISM_MEM_VLAN_XLATE, 1); 11282 rv |= soc_ism_table_hash_config(unit, SOC_ISM_MEM_L2_ENTRY, 1); 11283 rv |= soc_ism_table_hash_config(unit, SOC_ISM_MEM_L3_ENTRY, 1); 11284 rv |= soc_ism_table_hash_config(unit, SOC_ISM_MEM_EP_VLAN_XLATE, 1); 11285 rv |= soc_ism_table_hash_config(unit, SOC_ISM_MEM_MPLS, 1); 11286 if (SOC_FAILURE(rv)) { 11287 LOG_ERROR(BSL_LS_SOC_COMMON, 11288 (BSL_META_U(unit, 11289 "Error configuring ISM hash zero_lsb !!\n"))); 11290 return SOC_E_INTERNAL; 11291 } 11292 SOC_IF_ERROR_RETURN(soc_ism_get_total_banks(unit, &total)); 11293 SOC_IF_ERROR_RETURN(soc_ism_hash_max_offset_get(unit, &offset)); 11294 offset = offset/total; 11295 11296 rv = soc_ism_get_banks(unit, SOC_ISM_MEM_VLAN_XLATE, banks, bank_size, 11297 &count); 11298 if (rv < 0) { 11299 LOG_ERROR(BSL_LS_SOC_COMMON, 11300 (BSL_META_U(unit, 11301 "ISM VLAN_XLATE bank enumeration retrieval failed\n"))); 11302 return rv; 11303 } 11304 for (i = 0; i < count; i++) { 11305 /* Offset 0 is CRC32 low */ 11306 rv = soc_ism_hash_offset_config(unit, banks[i], i*offset); 11307 if (rv < 0) { 11308 LOG_ERROR(BSL_LS_SOC_COMMON, 11309 (BSL_META_U(unit, 11310 "ISM VLAN_XLATE bank %d hash offset set failure\n"), 11311 banks[i])); 11312 return rv; 11313 } 11314 } 11315 rv = soc_ism_get_banks(unit, SOC_ISM_MEM_L2_ENTRY, banks, bank_size, 11316 &count); 11317 if (rv < 0) { 11318 LOG_ERROR(BSL_LS_SOC_COMMON, 11319 (BSL_META_U(unit, 11320 "ISM L2 bank enumeration retrieval failed\n"))); 11321 return rv; 11322 } 11323 for (i = 0; i < count; i++) { 11324 /* Offset 0 is CRC32 low */ 11325 rv = soc_ism_hash_offset_config(unit, banks[i], i*offset); 11326 if (rv < 0) { 11327 LOG_ERROR(BSL_LS_SOC_COMMON, 11328 (BSL_META_U(unit, 11329 "ISM L2 bank %d hash offset set failure\n"), banks[i])); 11330 return rv; 11331 } 11332 } 11333 rv = soc_ism_get_banks(unit, SOC_ISM_MEM_L3_ENTRY, 11334 banks, bank_size, &count); 11335 if (rv < 0) { 11336 LOG_ERROR(BSL_LS_SOC_COMMON, 11337 (BSL_META_U(unit, 11338 "ISM L3 bank enumeration retrieval failed\n"))); 11339 return rv; 11340 } 11341 for (i = 0; i < count; i++) { 11342 /* Offset 0 is CRC32 low */ 11343 rv = soc_ism_hash_offset_config(unit, banks[i], i*offset); 11344 if (rv < 0) { 11345 LOG_ERROR(BSL_LS_SOC_COMMON, 11346 (BSL_META_U(unit, 11347 "ISM L3 bank %d hash offset set failure\n"), banks[i])); 11348 return rv; 11349 } 11350 } 11351 rv = soc_ism_get_banks(unit, SOC_ISM_MEM_EP_VLAN_XLATE, 11352 banks, bank_size, &count); 11353 if (rv < 0) { 11354 LOG_ERROR(BSL_LS_SOC_COMMON, 11355 (BSL_META_U(unit, 11356 "ISM EP_VLAN_XLATE bank enumeration retrieval failed\n"))); 11357 return rv; 11358 } 11359 for (i = 0; i < count; i++) { 11360 /* Offset 0 is CRC32 low */ 11361 rv = soc_ism_hash_offset_config(unit, banks[i], i*offset); 11362 if (rv < 0) { 11363 LOG_ERROR(BSL_LS_SOC_COMMON, 11364 (BSL_META_U(unit, 11365 "ISM EP_VLAN_XLATE bank %d hash offset set failure\n"), 11366 banks[i])); 11367 return rv; 11368 } 11369 } 11370 rv = soc_ism_get_banks(unit, SOC_ISM_MEM_MPLS, 11371 banks, bank_size, &count); 11372 if (rv < 0) { 11373 LOG_ERROR(BSL_LS_SOC_COMMON, 11374 (BSL_META_U(unit, 11375 "ISM MPLS bank enumeration retrieval failed\n"))); 11376 return rv; 11377 } 11378 for (i = 0; i < count; i++) { 11379 /* Offset 0 is CRC32 low */ 11380 rv = soc_ism_hash_offset_config(unit, banks[i], i*offset); 11381 if (rv < 0) { 11382 LOG_ERROR(BSL_LS_SOC_COMMON, 11383 (BSL_META_U(unit, 11384 "ISM MPLS bank %d hash offset set failure\n"), 11385 banks[i])); 11386 return rv; 11387 } 11388 } 11389 } 11390 #endif 11391 11392 SOC_IF_ERROR_RETURN(soc_tr3_init_port_mapping(unit)); 11393 11394 sal_memset(entry, 0, sizeof(cpu_pbm_entry_t)); 11395 soc_mem_pbmp_field_set(unit, CPU_PBMm, entry, BITMAPf, &PBMP_CMIC(unit)); 11396 SOC_IF_ERROR_RETURN 11397 (soc_mem_write(unit, CPU_PBMm, MEM_BLOCK_ALL, 0, entry)); 11398 11399 sal_memset(entry, 0, sizeof(cpu_pbm_2_entry_t)); 11400 soc_mem_pbmp_field_set(unit, CPU_PBM_2m, entry, BITMAPf, &PBMP_CMIC(unit)); 11401 SOC_IF_ERROR_RETURN 11402 (soc_mem_write(unit, CPU_PBM_2m, MEM_BLOCK_ALL, 0, entry)); 11403 11404 SOC_PBMP_CLEAR(pbmp); 11405 PBMP_ALL_ITER(unit, port) { 11406 if (IS_LB_PORT(unit, port) || 11407 (si->port_group[port] >= 2 && si->port_group[port] <= 3)) { 11408 SOC_PBMP_PORT_ADD(pbmp, port); 11409 } 11410 } 11411 11412 sal_memset(cl_port_valid, 0, sizeof(cl_port_valid)); 11413 sal_memset(xt_port_valid, 0, sizeof(xt_port_valid)); 11414 sal_memset(xl_port_valid, 0, sizeof(xl_port_valid)); 11415 sal_memset(xw_port_valid, 0, sizeof(xw_port_valid)); 11416 11417 for (phy_port = 1; phy_port < SOC_MAX_PHY_PORTS; phy_port++) { 11418 /* Only enable the required subports */ 11419 if (phy_port >= SOC_MAX_NUM_PORTS) { 11420 break; 11421 } 11422 port = si->flex_port_p2l_mapping[phy_port]; 11423 if (port < 0) { 11424 continue; 11425 } 11426 blk = SOC_PORT_BLOCK(unit, phy_port); 11427 bindex = SOC_PORT_BINDEX(unit, phy_port); 11428 blk_num = SOC_BLOCK_INFO(unit, blk).number; 11429 if (!SOC_PORT_VALID(unit, port)) { 11430 continue; 11431 } 11432 if (IS_CL_PORT(unit, port)) { 11433 cl_port_valid[blk_num] |= 1 << bindex; 11434 } else if (IS_XT_PORT(unit, port)) { 11435 xt_port_valid[blk_num] |= 1 << bindex; 11436 } else if (IS_XL_PORT(unit, port)) { 11437 xl_port_valid[blk_num] |= 1 << bindex; 11438 } else if (IS_XW_PORT(unit, port)) { 11439 xw_port_valid[blk_num] |= 1 << bindex; 11440 } 11441 } 11442 11443 SOC_BLOCK_ITER(unit, blk, SOC_BLK_CLPORT) { 11444 blk_num = SOC_BLOCK_INFO(unit, blk).number; 11445 if (_soc_tr3_port_speed_max[_soc_tr3_b2pp[blk]] >= 100000) { 11446 mac_mode = MAC_MODE_AGGR; 11447 port = si->port_p2l_mapping[_soc_tr3_b2pp[blk]]; 11448 /* Put in reset */ 11449 SOC_IF_ERROR_RETURN 11450 (soc_reg_field32_modify(unit, PORT_MAC_CONTROLr, port, 11451 CMAC_RESETf, 1)); 11452 sal_udelay(10); 11453 rval = 0; 11454 soc_reg_field_set(unit, PORT_MODE_REGr, &rval, MAC_MODEf, 11455 mac_mode); 11456 SOC_IF_ERROR_RETURN(WRITE_PORT_MODE_REGr(unit, port, rval)); 11457 /* Release from reset */ 11458 SOC_IF_ERROR_RETURN 11459 (soc_reg_field32_modify(unit, PORT_MAC_CONTROLr, port, 11460 CMAC_RESETf, 0)); 11461 } else { 11462 port = -1; 11463 for (phy = 0; phy < _SOC_TR3_PHY_PER_PORT_BLOCK; phy++) { 11464 int base_lane = (phy * _SOC_TR3_LANES_PER_PHY); 11465 core_mode[phy] = CORE_MODE_NOTDM; 11466 phy_mode[phy] = PHY_MODE_SINGLE; 11467 speed = _soc_tr3_port_speed_max[_soc_tr3_b2pp[blk] + base_lane]; 11468 if (speed > 0) { 11469 core_mode[phy] = CORE_MODE_QUAD; 11470 phy_mode[phy] = PHY_MODE_QUAD; 11471 } 11472 if ((speed >= 10000) && (speed <= 12000)) { 11473 core_mode[phy] = CORE_MODE_SINGLE; /* XAUI */ 11474 if (si->flex_port_p2l_mapping[_soc_tr3_b2pp[blk] + base_lane] >= 0) { 11475 if ((((si->flex_port_p2l_mapping[_soc_tr3_b2pp[blk] + 11476 base_lane + 1]) >= 0) && 11477 ((si->flex_port_p2l_mapping[_soc_tr3_b2pp[blk] + 11478 base_lane + 2]) >= 0) && 11479 ((si->flex_port_p2l_mapping[_soc_tr3_b2pp[blk] + 11480 base_lane + 3]) >= 0)) || ((_tr3_port_config_id[unit] == 99) && 11481 (((si->flex_port_p2l_mapping[_soc_tr3_b2pp[blk] + 11482 base_lane + 1]) >= 0) && 11483 ((si->flex_port_p2l_mapping[_soc_tr3_b2pp[blk] + 11484 base_lane + 2]) < 0) && 11485 ((si->flex_port_p2l_mapping[_soc_tr3_b2pp[blk] + 11486 base_lane + 3]) < 0)))) { 11487 core_mode[phy] = CORE_MODE_QUAD; /* XFI */ 11488 } else if (((si->flex_port_p2l_mapping[_soc_tr3_b2pp[blk] + 11489 base_lane + 1]) < 0) && 11490 ((si->flex_port_p2l_mapping[_soc_tr3_b2pp[blk] + 11491 base_lane + 2]) >= 0) && 11492 ((si->flex_port_p2l_mapping[_soc_tr3_b2pp[blk] + 11493 base_lane + 3]) < 0)) { 11494 core_mode[phy] = CORE_MODE_DUAL; /* RXAUI */ 11495 } 11496 } 11497 } else if (speed > 12000) { 11498 core_mode[phy] = CORE_MODE_SINGLE; 11499 phy_mode[phy] = PHY_MODE_SINGLE; 11500 if (si->flex_port_p2l_mapping[_soc_tr3_b2pp[blk] + base_lane] >= 0) { 11501 if (((si->flex_port_p2l_mapping[_soc_tr3_b2pp[blk] + 11502 base_lane + 1]) < 0) && 11503 ((si->flex_port_p2l_mapping[_soc_tr3_b2pp[blk] + 11504 base_lane + 2]) >= 0) && 11505 ((si->flex_port_p2l_mapping[_soc_tr3_b2pp[blk] + 11506 base_lane + 3]) < 0)) { /* HIGIG-Duo */ 11507 core_mode[phy] = CORE_MODE_DUAL; 11508 phy_mode[phy] = PHY_MODE_DUAL; 11509 } 11510 } 11511 } 11512 for (lane = 0; lane < _SOC_TR3_LANES_PER_PHY; lane++) { 11513 if (port < 0) { 11514 port = si->port_p2l_mapping[_soc_tr3_b2pp[blk] + 11515 base_lane + lane]; 11516 if (SOC_PORT_VALID(unit, port)) { 11517 break; 11518 } else { 11519 port = -1; 11520 } 11521 } 11522 } 11523 } 11524 if (port < 0) { /* Block not in use */ 11525 continue; 11526 } 11527 11528 /* Put in reset */ 11529 rval = 0; 11530 soc_reg_field_set(unit, PORT_MAC_CONTROLr, &rval, 11531 XMAC0_RESETf, 1); 11532 soc_reg_field_set(unit, PORT_MAC_CONTROLr, &rval, 11533 XMAC1_RESETf, 1); 11534 soc_reg_field_set(unit, PORT_MAC_CONTROLr, &rval, 11535 XMAC2_RESETf, 1); 11536 SOC_IF_ERROR_RETURN(WRITE_PORT_MAC_CONTROLr(unit, port, rval)); 11537 /* Configure core and phy modes */ 11538 rval = 0; 11539 for (phy = 0; phy < _SOC_TR3_PHY_PER_PORT_BLOCK; phy++) { 11540 if ((phy == 0) && 11541 ((dev_id == BCM56545_DEVICE_ID) || (dev_id == BCM56546_DEVICE_ID) || 11542 (dev_id == BCM56643_DEVICE_ID) || (dev_id == BCM56648_DEVICE_ID) || 11543 (dev_id == BCM56649_DEVICE_ID)) && 11544 (core_mode[phy] == CORE_MODE_NOTDM)) { 11545 soc_reg_field_set(unit, PORT_MODE_REGr, &rval, 11546 core_mode_field[0], 0); 11547 } else { 11548 soc_reg_field_set(unit, PORT_MODE_REGr, &rval, 11549 core_mode_field[phy], core_mode[phy]); 11550 } 11551 soc_reg_field_set(unit, PORT_MODE_REGr, &rval, 11552 phy_mode_field[phy], phy_mode[phy]); 11553 } 11554 SOC_IF_ERROR_RETURN(WRITE_PORT_MODE_REGr(unit, port, rval)); 11555 /* Release from reset */ 11556 rval = 0; 11557 soc_reg_field_set(unit, PORT_MAC_CONTROLr, &rval, 11558 XMAC0_RESETf, 0); 11559 soc_reg_field_set(unit, PORT_MAC_CONTROLr, &rval, 11560 XMAC1_RESETf, 0); 11561 soc_reg_field_set(unit, PORT_MAC_CONTROLr, &rval, 11562 XMAC2_RESETf, 0); 11563 SOC_IF_ERROR_RETURN(WRITE_PORT_MAC_CONTROLr(unit, port, rval)); 11564 } 11565 /* Reset MIB counter */ 11566 if (cl_port_valid[blk_num]) { 11567 rval = 0; 11568 soc_reg_field_set(unit, PORT_MIB_RESETr, &rval, CLR_CNTf, 11569 cl_port_valid[blk_num]); 11570 SOC_IF_ERROR_RETURN(WRITE_PORT_MIB_RESETr(unit, port, rval)); 11571 SOC_IF_ERROR_RETURN(WRITE_PORT_MIB_RESETr(unit, port, 0)); 11572 } 11573 /* Enable subports */ 11574 rval = 0; 11575 for (bindex = 0; bindex < 12; bindex++) { 11576 if (cl_port_valid[blk_num] & (1 << bindex)) { 11577 soc_reg_field_set(unit, PORT_ENABLE_REGr, &rval, 11578 port_field[bindex], 1); 11579 } 11580 } 11581 SOC_IF_ERROR_RETURN(_soc_tr3_hx4_clock_sync(unit, _SOC_TR3_COREPLL, port, 11582 _SOC_TR3_STOP_CLK)); 11583 SOC_IF_ERROR_RETURN(WRITE_PORT_ENABLE_REGr(unit, port, rval)); 11584 SOC_IF_ERROR_RETURN(_soc_tr3_hx4_clock_sync(unit, _SOC_TR3_COREPLL, port, 11585 _SOC_TR3_START_CLK)); 11586 /* Configure the LED intra port delay */ 11587 rval = 2; 11588 SOC_IF_ERROR_RETURN(WRITE_PORT_LED_CHAIN_CONFIGr(unit, port, rval)); 11589 11590 /* Clear per block PORT_EHG memories */ 11591 SOC_IF_ERROR_RETURN 11592 (soc_mem_clear(unit, PORT_EHG_RX_TUNNEL_DATAm, blk, TRUE)); 11593 SOC_IF_ERROR_RETURN 11594 (soc_mem_clear(unit, PORT_EHG_RX_TUNNEL_MASKm, blk, TRUE)); 11595 SOC_IF_ERROR_RETURN 11596 (soc_mem_clear(unit, PORT_EHG_TX_TUNNEL_DATAm, blk, TRUE)); 11597 } 11598 11599 SOC_BLOCK_ITER(unit, blk, SOC_BLK_XTPORT) { 11600 blk_num = SOC_BLOCK_INFO(unit, blk).number; 11601 port = -1; 11602 for (phy = 0; phy < _SOC_TR3_PHY_PER_PORT_BLOCK; phy++) { 11603 int base_lane = (phy * _SOC_TR3_LANES_PER_PHY); 11604 core_mode[phy] = CORE_MODE_QUAD; 11605 phy_mode[phy] = PHY_MODE_SINGLE; 11606 speed = _soc_tr3_port_speed_max[_soc_tr3_b2pp[blk] + base_lane]; 11607 if (speed > 3000) { 11608 core_mode[phy] = CORE_MODE_SINGLE; 11609 phy_mode[phy] = PHY_MODE_DUAL; 11610 } else if (speed > 0) { 11611 core_mode[phy] = CORE_MODE_QUAD; 11612 phy_mode[phy] = PHY_MODE_QUAD; 11613 } 11614 for (lane = 0; lane < _SOC_TR3_LANES_PER_PHY; lane++) { 11615 if (port < 0) { 11616 port = si->port_p2l_mapping[_soc_tr3_b2pp[blk] + base_lane + lane]; 11617 if (SOC_PORT_VALID(unit, port)) { 11618 break; 11619 } else { 11620 port = -1; 11621 } 11622 } 11623 } 11624 } 11625 if (port < 0) { /* Block not in use */ 11626 continue; 11627 } 11628 11629 rval = 0; 11630 /* Put in reset */ 11631 soc_reg_field_set(unit, PORT_MAC_CONTROLr, &rval, 11632 XMAC0_RESETf, 1); 11633 soc_reg_field_set(unit, PORT_MAC_CONTROLr, &rval, 11634 XMAC1_RESETf, 1); 11635 soc_reg_field_set(unit, PORT_MAC_CONTROLr, &rval, 11636 XMAC2_RESETf, 1); 11637 SOC_IF_ERROR_RETURN(WRITE_PORT_MAC_CONTROLr(unit, port, rval)); 11638 /* Configure core and phy modes */ 11639 rval = 0; 11640 for (phy = 0; phy < _SOC_TR3_PHY_PER_PORT_BLOCK; phy++) { 11641 soc_reg_field_set(unit, PORT_MODE_REGr, &rval, 11642 core_mode_field[phy], core_mode[phy]); 11643 soc_reg_field_set(unit, PORT_MODE_REGr, &rval, 11644 phy_mode_field[phy], phy_mode[phy]); 11645 soc_reg_field_set(unit, PORT_MODE_REGr, &rval, 11646 xpc_gmii_enable_field[phy], 11647 ((core_mode[phy] == CORE_MODE_QUAD) && 11648 (!SOC_IS_HELIX4(unit)) ) ? 1 : 0); 11649 } 11650 SOC_IF_ERROR_RETURN(WRITE_PORT_MODE_REGr(unit, port, rval)); 11651 /* Release from reset */ 11652 rval = 0; 11653 soc_reg_field_set(unit, PORT_MAC_CONTROLr, &rval, 11654 XMAC0_RESETf, 0); 11655 soc_reg_field_set(unit, PORT_MAC_CONTROLr, &rval, 11656 XMAC1_RESETf, 0); 11657 soc_reg_field_set(unit, PORT_MAC_CONTROLr, &rval, 11658 XMAC2_RESETf, 0); 11659 SOC_IF_ERROR_RETURN(WRITE_PORT_MAC_CONTROLr(unit, port, rval)); 11660 11661 /* Reset MIB counter */ 11662 if (xt_port_valid[blk_num]) { 11663 rval = 0; 11664 soc_reg_field_set(unit, PORT_MIB_RESETr, &rval, CLR_CNTf, 11665 xt_port_valid[blk_num]); 11666 SOC_IF_ERROR_RETURN(WRITE_PORT_MIB_RESETr(unit, port, rval)); 11667 SOC_IF_ERROR_RETURN(WRITE_PORT_MIB_RESETr(unit, port, 0)); 11668 } 11669 /* Enable subports */ 11670 rval = 0; 11671 for (bindex = 0; bindex < 12; bindex++) { 11672 if (xt_port_valid[blk_num] & (1 << bindex)) { 11673 soc_reg_field_set(unit, PORT_ENABLE_REGr, &rval, 11674 port_field[bindex], 1); 11675 } 11676 } 11677 SOC_IF_ERROR_RETURN(_soc_tr3_hx4_clock_sync(unit, _SOC_TR3_LCPLL0, port, 11678 _SOC_TR3_STOP_CLK)); 11679 SOC_IF_ERROR_RETURN(WRITE_PORT_ENABLE_REGr(unit, port, rval)); 11680 SOC_IF_ERROR_RETURN(_soc_tr3_hx4_clock_sync(unit, _SOC_TR3_LCPLL0, port, 11681 _SOC_TR3_START_CLK)); 11682 11683 /* Configure the LED intra port delay */ 11684 rval = 2; 11685 SOC_IF_ERROR_RETURN(WRITE_PORT_LED_CHAIN_CONFIGr(unit, port, rval)); 11686 11687 /* Clear per block PORT_EHG memories */ 11688 SOC_IF_ERROR_RETURN 11689 (soc_mem_clear(unit, PORT_EHG_RX_TUNNEL_DATAm, blk, TRUE)); 11690 SOC_IF_ERROR_RETURN 11691 (soc_mem_clear(unit, PORT_EHG_RX_TUNNEL_MASKm, blk, TRUE)); 11692 SOC_IF_ERROR_RETURN 11693 (soc_mem_clear(unit, PORT_EHG_TX_TUNNEL_DATAm, blk, TRUE)); 11694 } 11695 11696 SOC_BLOCK_ITER(unit, blk, SOC_BLK_XLPORT) { 11697 blk_num = SOC_BLOCK_INFO(unit, blk).number; 11698 port = SOC_BLOCK_PORT(unit, blk); 11699 if (port < 0) { 11700 continue; 11701 } 11702 core_mode[0] = CORE_MODE_QUAD; 11703 phy_mode[0] = PHY_MODE_QUAD; 11704 /* XL0 only operates in Quad (single 1G) mode */ 11705 if (blk_num != 0) { 11706 maxsp = 4; 11707 if (si->port_speed_max[port] > 11000) { 11708 core_mode[0] = CORE_MODE_DUAL; 11709 phy_mode[0] = PHY_MODE_DUAL; 11710 } 11711 if (si->port_speed_max[port] > 21000) { 11712 core_mode[0] = CORE_MODE_SINGLE; 11713 phy_mode[0] = PHY_MODE_SINGLE; 11714 } 11715 } else { 11716 maxsp = 1; 11717 si->management_port = port; /* XL0 */ 11718 } 11719 /* Put in reset */ 11720 rval = 0; 11721 soc_reg_field_set(unit, PORT_MAC_CONTROLr, &rval, 11722 XMAC0_RESETf, 1); 11723 SOC_IF_ERROR_RETURN(WRITE_PORT_MAC_CONTROLr(unit, port, rval)); 11724 /* Configure core and phy modes */ 11725 rval = 0; 11726 soc_reg_field_set(unit, PORT_MODE_REGr, &rval, core_mode_field[0], 11727 core_mode[0]); 11728 soc_reg_field_set(unit, PORT_MODE_REGr, &rval, phy_mode_field[0], 11729 phy_mode[0]); 11730 /* Only set XPC on XL0 */ 11731 soc_reg_field_set(unit, PORT_MODE_REGr, &rval, 11732 xpc_gmii_enable_field[0], 11733 ((maxsp == 1) && (!SOC_IS_HELIX4(unit)) && 11734 (phy_mode[0] == PHY_MODE_QUAD)) ? 1 : 0); 11735 SOC_IF_ERROR_RETURN(WRITE_PORT_MODE_REGr(unit, port, rval)); 11736 /* Release from reset */ 11737 rval = 0; 11738 soc_reg_field_set(unit, PORT_MAC_CONTROLr, &rval, 11739 XMAC0_RESETf, 0); 11740 SOC_IF_ERROR_RETURN(WRITE_PORT_MAC_CONTROLr(unit, port, rval)); 11741 /* Enable subports */ 11742 rval = 0; 11743 for (bindex = 0; bindex < maxsp; bindex++) { 11744 if (xl_port_valid[blk_num] & (1 << bindex)) { 11745 soc_reg_field_set(unit, PORT_ENABLE_REGr, &rval, 11746 port_field[bindex], 1); 11747 } 11748 } 11749 SOC_IF_ERROR_RETURN(_soc_tr3_hx4_clock_sync(unit, _SOC_TR3_COREPLL, port, 11750 _SOC_TR3_STOP_CLK)); 11751 SOC_IF_ERROR_RETURN(WRITE_PORT_ENABLE_REGr(unit, port, rval)); 11752 SOC_IF_ERROR_RETURN(_soc_tr3_hx4_clock_sync(unit, _SOC_TR3_COREPLL, port, 11753 _SOC_TR3_START_CLK)); 11754 /* Configure the LED intra port delay */ 11755 rval = 2; 11756 SOC_IF_ERROR_RETURN(WRITE_PORT_LED_CHAIN_CONFIGr(unit, port, rval)); 11757 11758 /* Clear per block PORT_EHG memories */ 11759 sal_memset(entry, 0, sizeof(entry)); 11760 for (i = 0; i < 16; i++) { 11761 SOC_IF_ERROR_RETURN 11762 (soc_mem_write(unit, PORT_EHG_RX_TUNNEL_DATAm, blk, i, entry)); 11763 SOC_IF_ERROR_RETURN 11764 (soc_mem_write(unit, PORT_EHG_RX_TUNNEL_MASKm, blk, i, entry)); 11765 SOC_IF_ERROR_RETURN 11766 (soc_mem_write(unit, PORT_EHG_TX_TUNNEL_DATAm, blk, i, entry)); 11767 } 11768 } 11769 11770 SOC_BLOCK_ITER(unit, blk, SOC_BLK_XWPORT) { 11771 blk_num = SOC_BLOCK_INFO(unit, blk).number; 11772 port = SOC_BLOCK_PORT(unit, blk); 11773 if (port < 0) { 11774 continue; 11775 } 11776 core_mode[1] = core_mode[2] = CORE_MODE_NOTDM; 11777 phy_mode[1] = phy_mode[2] = 0; 11778 rval = 0; 11779 /* XW0/1/2 operates in: 11780 * - Quad (single 1G and single XFI) 11781 * - Dual (two HGd and two XFI (XFI ports are contiguous)) 11782 * - Single (HGd, HG, 40G) 11783 */ 11784 if (_soc_tr3_port_speed_max[_soc_tr3_b2pp[blk]] < 10000) { 11785 core_mode[0] = CORE_MODE_QUAD; 11786 phy_mode[0] = PHY_MODE_QUAD; 11787 maxsp = 4; 11788 soc_reg_field_set(unit, PORT_MODE_REGr, &rval, 11789 xpc_gmii_enable_field[0], 11790 (!SOC_IS_HELIX4(unit)) ? 1 : 0); 11791 } else if (_soc_tr3_port_speed_max[_soc_tr3_b2pp[blk]] >= 10000 && 11792 _soc_tr3_port_speed_max[_soc_tr3_b2pp[blk]] < 21000) { 11793 if (((si->flex_port_p2l_mapping[_soc_tr3_b2pp[blk] + 1]) < 0) && 11794 ((si->flex_port_p2l_mapping[_soc_tr3_b2pp[blk] + 2]) >= 0) && 11795 ((si->flex_port_p2l_mapping[_soc_tr3_b2pp[blk] + 3]) < 0)) { 11796 /* RXAUI */ 11797 core_mode[0] = CORE_MODE_DUAL; 11798 if (_soc_tr3_port_speed_max[_soc_tr3_b2pp[blk]] == 10000) { 11799 phy_mode[0] = PHY_MODE_QUAD; 11800 } 11801 else { 11802 phy_mode[0] = PHY_MODE_DUAL; 11803 } 11804 maxsp = 3; 11805 } else { 11806 core_mode[0] = CORE_MODE_QUAD; 11807 phy_mode[0] = PHY_MODE_QUAD; 11808 maxsp = 4; /* 2 */ 11809 } 11810 } else if (_soc_tr3_port_speed_max[_soc_tr3_b2pp[blk]] >= 21000 && 11811 _soc_tr3_port_speed_max[_soc_tr3_b2pp[blk]] < 40000) { 11812 /* Differentiate between HG and HGd */ 11813 if (xw_port_valid[blk_num] & (1 << 2)) { 11814 /* If port2 in the Port block is valid this is HGd */ 11815 core_mode[0] = CORE_MODE_DUAL; 11816 phy_mode[0] = PHY_MODE_DUAL; 11817 maxsp = 3; 11818 } else { 11819 core_mode[0] = CORE_MODE_SINGLE; 11820 phy_mode[0] = PHY_MODE_SINGLE; 11821 maxsp = 1; 11822 } 11823 } else if (_soc_tr3_port_speed_max[_soc_tr3_b2pp[blk]] >= 40000) { 11824 core_mode[0] = CORE_MODE_SINGLE; 11825 phy_mode[0] = PHY_MODE_SINGLE; 11826 maxsp = 1; 11827 } 11828 /* Put in reset */ 11829 { 11830 uint32 rval1 = 0; 11831 soc_reg_field_set(unit, PORT_MAC_CONTROLr, &rval1, 11832 XMAC0_RESETf, 1); 11833 SOC_IF_ERROR_RETURN(WRITE_PORT_MAC_CONTROLr(unit, port, rval1)); 11834 } 11835 /* Configure core and phy modes */ 11836 soc_reg_field_set(unit, PORT_MODE_REGr, &rval, core_mode_field[0], 11837 core_mode[0]); 11838 soc_reg_field_set(unit, PORT_MODE_REGr, &rval, phy_mode_field[0], 11839 phy_mode[0]); 11840 SOC_IF_ERROR_RETURN(WRITE_PORT_MODE_REGr(unit, port, rval)); 11841 /* Release from reset */ 11842 rval = 0; 11843 soc_reg_field_set(unit, PORT_MAC_CONTROLr, &rval, 11844 XMAC0_RESETf, 0); 11845 SOC_IF_ERROR_RETURN(WRITE_PORT_MAC_CONTROLr(unit, port, rval)); 11846 /* Enable subports */ 11847 rval = 0; 11848 for (bindex = 0; bindex < maxsp; bindex++) { 11849 if (xw_port_valid[blk_num] & (1 << bindex)) { 11850 soc_reg_field_set(unit, PORT_ENABLE_REGr, &rval, 11851 port_field[bindex], 1); 11852 } 11853 } 11854 SOC_IF_ERROR_RETURN(_soc_tr3_hx4_clock_sync(unit, _SOC_TR3_LCPLL0, port, 11855 _SOC_TR3_STOP_CLK)); 11856 SOC_IF_ERROR_RETURN(WRITE_PORT_ENABLE_REGr(unit, port, rval)); 11857 SOC_IF_ERROR_RETURN(_soc_tr3_hx4_clock_sync(unit, _SOC_TR3_LCPLL0, port, 11858 _SOC_TR3_START_CLK)); 11859 /* Configure the LED intra port delay */ 11860 rval = 2; 11861 SOC_IF_ERROR_RETURN(WRITE_PORT_LED_CHAIN_CONFIGr(unit, port, rval)); 11862 11863 /* Clear per block PORT_EHG memories */ 11864 for (i = 0; i < 16; i++) { 11865 SOC_IF_ERROR_RETURN 11866 (soc_mem_write(unit, PORT_EHG_RX_TUNNEL_DATAm, blk, i, entry)); 11867 SOC_IF_ERROR_RETURN 11868 (soc_mem_write(unit, PORT_EHG_RX_TUNNEL_MASKm, blk, i, entry)); 11869 SOC_IF_ERROR_RETURN 11870 (soc_mem_write(unit, PORT_EHG_TX_TUNNEL_DATAm, blk, i, entry)); 11871 } 11872 } 11873 11874 sal_memset(entry, 0, sizeof(egr_ing_port_entry_t)); 11875 soc_mem_field32_set(unit, EGR_ING_PORTm, entry, PORT_TYPEf, 1); 11876 PBMP_HG_ITER(unit, port) { 11877 SOC_IF_ERROR_RETURN 11878 (soc_reg_field32_modify(unit, PORT_CONFIGr, port, HIGIG_MODEf, 1)); 11879 if(soc_property_port_get(unit, port, spn_HIGIG2_HDR_MODE, 0)) { 11880 SOC_IF_ERROR_RETURN 11881 (soc_reg_field32_modify(unit, PORT_CONFIGr, port, HIGIG2_MODEf, 1)); 11882 11883 } 11884 SOC_IF_ERROR_RETURN 11885 (soc_mem_write(unit, EGR_ING_PORTm, MEM_BLOCK_ALL, port, entry)); 11886 } 11887 higig2 = soc_property_port_get(unit, CMIC_PORT(unit), spn_HIGIG2_HDR_MODE, 0) ? 1 : 0; 11888 soc_mem_field32_set(unit, EGR_ING_PORTm, entry, HIGIG2f, higig2); 11889 SOC_IF_ERROR_RETURN 11890 (soc_mem_write(unit, EGR_ING_PORTm, MEM_BLOCK_ALL, si->cpu_hg_index, 11891 entry)); 11892 /* Reset HIGIG2 field as it will be written even for Loopback port */ 11893 soc_mem_field32_set(unit, EGR_ING_PORTm, entry, HIGIG2f, 0); 11894 11895 /* Change Loopback port default MTU Size */ 11896 if(SOC_REG_IS_VALID(unit,PASSTHRU_NLF_MTU_CHECKr)){ 11897 SOC_IF_ERROR_RETURN(READ_PASSTHRU_NLF_MTU_CHECKr(unit, &rval)); 11898 mtufield_len = soc_reg_field_length(unit,PASSTHRU_NLF_MTU_CHECKr, MTU_IN_BYTESf); 11899 soc_reg_field_set(unit, PASSTHRU_NLF_MTU_CHECKr, &rval, MTU_IN_BYTESf, 11900 (1 << mtufield_len)-1); 11901 SOC_IF_ERROR_RETURN(WRITE_PASSTHRU_NLF_MTU_CHECKr(unit, rval)); 11902 } 11903 11904 /* Enable pri/cfi remarking on egress ports. */ 11905 rval = 0; 11906 soc_reg_field_set(unit, EGR_VLAN_CONTROL_1r, &rval, REMARK_OUTER_DOT1Pf, 11907 1); 11908 PBMP_ALL_ITER(unit, port) { 11909 SOC_IF_ERROR_RETURN(WRITE_EGR_VLAN_CONTROL_1r(unit, port, rval)); 11910 } 11911 11912 PBMP_ALL_ITER(unit, port) { 11913 if (IS_CPU_PORT(unit, port)) { 11914 continue; 11915 } 11916 /* Set loopback port type */ 11917 if (IS_LB_PORT(unit, port)) { 11918 soc_mem_field32_set(unit, EGR_ING_PORTm, entry, PORT_TYPEf, 2); 11919 SOC_IF_ERROR_RETURN 11920 (soc_mem_write(unit, EGR_ING_PORTm, MEM_BLOCK_ALL, port, entry)); 11921 continue; 11922 } 11923 /* Set max packet size that is used in statistic counter update */ 11924 11925 SOC_IF_ERROR_RETURN(WRITE_PORT_CNTMAXSIZEr(unit, port, 16383)); 11926 } 11927 11928 /* Enable 1588 indication in Higig extension header */ 11929 if (SOC_PBMP_NOT_NULL(PBMP_HG_ALL(unit))) { 11930 SOC_IF_ERROR_RETURN 11931 (soc_reg_field32_modify(unit, HG_EH_CONTROLr, REG_PORT_ANY, 11932 EH_1588_INDICATION_ENABLEf, 1)); 11933 11934 COMPILER_64_ZERO(val64); 11935 SOC_IF_ERROR_RETURN(READ_EGR_HG_EH_CONTROL_64r(unit, &val64)); 11936 soc_reg64_field32_set(unit, EGR_HG_EH_CONTROL_64r, &val64, 11937 EH_1588_INDICATION_ENABLEf, 1); 11938 SOC_IF_ERROR_RETURN(WRITE_EGR_HG_EH_CONTROL_64r(unit, val64)); 11939 } 11940 11941 SOC_IF_ERROR_RETURN(READ_MISCCONFIGr(unit, &rval)); 11942 soc_reg_field_set(unit, MISCCONFIGr, &rval, METERING_CLK_ENf, 1); 11943 SOC_IF_ERROR_RETURN(WRITE_MISCCONFIGr(unit, rval)); 11944 11945 SOC_IF_ERROR_RETURN 11946 (soc_reg_field32_modify(unit, AUX_ARB_CONTROL_2r, REG_PORT_ANY, 11947 STORM_CONTROL_REFRESH_ENABLEf, 1)); 11948 11949 /* Adjust storm control refresh rate to 8000/sec (1 token per 125 us) */ 11950 SOC_IF_ERROR_RETURN 11951 (soc_reg_field32_modify(unit, REFRESH_COUNT_CONTROLr, REG_PORT_ANY, 11952 STORM_CONTROL_REFRESH_MAXf, 0xf)); 11953 11954 /* AXP configuration */ 11955 if (soc_feature(unit, soc_feature_axp)) { 11956 for (axp = 0; axp < SOC_AXP_NLF_NUM; axp++) { 11957 SOC_IF_ERROR_RETURN 11958 (READ_AXP_CH_NLF_PORT_MAPPINGr(unit, axp, &rval)); 11959 soc_reg_field_set(unit, AXP_CH_NLF_PORT_MAPPINGr, &rval, 11960 NLF_PORT_NUMf, AXP_PORT(unit, axp)); 11961 SOC_IF_ERROR_RETURN 11962 (WRITE_AXP_CH_NLF_PORT_MAPPINGr(unit, axp, rval)); 11963 } 11964 for (lpt = 0; lpt < SOC_AXP_LPT_NUM; lpt++) { 11965 port_attr = SOC_AXP_EPP_USE_SGLP; 11966 switch (lpt) { 11967 case SOC_AXP_LPT_WLAN_ENCAP: 11968 port = AXP_PORT(unit, SOC_AXP_NLF_WLAN_ENCAP); 11969 break; 11970 case SOC_AXP_LPT_WLAN_DECAP: 11971 port = AXP_PORT(unit, SOC_AXP_NLF_WLAN_DECAP); 11972 port_attr = SOC_AXP_EPP_USE_SVP; 11973 break; 11974 case SOC_AXP_LPT_DPI_SM: 11975 port = AXP_PORT(unit, SOC_AXP_NLF_SM); 11976 break; 11977 default: 11978 port = AXP_PORT(unit, SOC_AXP_NLF_PASSTHRU); 11979 } 11980 SOC_IF_ERROR_RETURN 11981 (soc_mem_field32_modify(unit, ING_NLF_PORT_MAPm, lpt, 11982 PORT_NUMf, port)); 11983 11984 /* USE_SVP for WLAN_DECAP, otherwise USE_SGLP in SOURCE_TRUNK_MAP 11985 * TABLE to get LPORT index. 11986 */ 11987 SOC_IF_ERROR_RETURN 11988 (soc_mem_field32_modify(unit, EGR_AXP_PORT_PROPERTYm, lpt, 11989 SELf, port_attr)); 11990 } 11991 11992 rval = 0; 11993 soc_reg_field_set(unit, IP_TO_AXP_CREDIT_TRANSFERr, 11994 &rval, NUM_OF_CREDITSf, 0x10); 11995 soc_reg_field_set(unit, IP_TO_AXP_CREDIT_TRANSFERr, 11996 &rval, TRANSFER_ENABLEf, 1); 11997 SOC_IF_ERROR_RETURN(WRITE_IP_TO_AXP_CREDIT_TRANSFERr(unit, rval)); 11998 11999 SOC_IF_ERROR_RETURN(READ_AXP_WRX_MASTER_CTRLr(unit, &rval)); 12000 soc_reg_field_set(unit, AXP_WRX_MASTER_CTRLr, &rval, CREDIT_TO_AXP_ENABLEf, 1); 12001 SOC_IF_ERROR_RETURN(WRITE_AXP_WRX_MASTER_CTRLr(unit, rval)); 12002 12003 rval = 0; 12004 soc_reg_field_set(unit, AXP_WTX_ICREDIT_CTLr, &rval, CREDIT_ENf, 1); 12005 SOC_IF_ERROR_RETURN(WRITE_AXP_WTX_ICREDIT_CTLr(unit, rval)); 12006 12007 for (axp = 0; axp < 4; axp++) { 12008 SOC_IF_ERROR_RETURN(READ_AXP_CH_NLFIB_PTRr(unit, axp, &rval)); 12009 soc_reg_field_set(unit, AXP_CH_NLFIB_PTRr, &rval, START_PTRf, axp*160); 12010 tmpval = (axp + 1)*160 - 1; 12011 if (tmpval >= 512) { 12012 tmpval = 511; 12013 } 12014 soc_reg_field_set(unit, AXP_CH_NLFIB_PTRr, &rval, END_PTRf, tmpval); 12015 SOC_IF_ERROR_RETURN(WRITE_AXP_CH_NLFIB_PTRr(unit, axp, rval)); 12016 12017 SOC_IF_ERROR_RETURN(READ_AXP_CH_NLFOB_CTRLr(unit, axp, &rval)); 12018 soc_reg_field_set(unit, AXP_CH_NLFOB_CTRLr, &rval, CREDIT_ENf, 1); 12019 SOC_IF_ERROR_RETURN(WRITE_AXP_CH_NLFOB_CTRLr(unit, axp, rval)); 12020 12021 rval = 0; 12022 soc_reg_field_set(unit, AXP_CH_MAX_MMU_REQr, &rval, REQ_MAXf, 0x18); 12023 SOC_IF_ERROR_RETURN(WRITE_AXP_CH_MAX_MMU_REQr(unit, axp, rval)); 12024 } 12025 12026 rval = 0; 12027 soc_reg_field_set(unit, UCQ_CONFIGr, &rval, WAMU_QUEUE_BASEf, 12028 si->port_uc_cosq_base[AXP_PORT(unit, SOC_AXP_NLF_WLAN_DECAP)]); 12029 SOC_IF_ERROR_RETURN(WRITE_UCQ_CONFIGr(unit, rval)); 12030 12031 rval = 0; 12032 soc_reg_field_set(unit, AXP_CH_MMU_REQ_ENr, &rval, ENABLEf, 0xf); 12033 SOC_IF_ERROR_RETURN(WRITE_AXP_CH_MMU_REQ_ENr(unit, rval)); 12034 12035 /* initializing default hashing scheme */ 12036 SOC_IF_ERROR_RETURN 12037 (soc_reg_read_any_block(unit, AXP_WRX_SVP_HASH_CTRLr, &hash_control)); 12038 soc_reg_field_set(unit, AXP_WRX_SVP_HASH_CTRLr, &hash_control, SELECT_Af, 12039 FB_HASH_CRC32_UPPER); 12040 soc_reg_field_set(unit, AXP_WRX_SVP_HASH_CTRLr, &hash_control, SELECT_Bf, 12041 FB_HASH_CRC32_LOWER); 12042 12043 SOC_IF_ERROR_RETURN 12044 (soc_reg_write_all_blocks(unit, AXP_WRX_SVP_HASH_CTRLr, hash_control)); 12045 } 12046 12047 /* 12048 * Egress Enable 12049 */ 12050 sal_memset(entry, 0, sizeof(egr_enable_entry_t)); 12051 soc_mem_field32_set(unit, EGR_ENABLEm, entry, PRT_ENABLEf, 1); 12052 PBMP_ALL_ITER(unit, port) { 12053 if (IS_AXP_PORT(unit, port)) { 12054 /* Physical port table index doesn't exist for AXP ports */ 12055 continue; 12056 } 12057 phy_port = si->port_l2p_mapping[port]; 12058 SOC_IF_ERROR_RETURN 12059 (WRITE_EGR_ENABLEm(unit, MEM_BLOCK_ALL, phy_port, entry)); 12060 /* cache num of port lanes */ 12061 (void)soc_tr3_port_lanes_gen(unit, port, &si->port_num_lanes[port], NULL); 12062 } 12063 12064 PBMP_XT_ITER(unit, port) { 12065 if ( si->port_speed_max[port] <= 3000) { 12066 SOC_IF_ERROR_RETURN (soc_reg_field32_modify( 12067 unit, PORT_EHG_RX_CONTROLr, port, THROTTLE_RX_FIFOf, 1)); 12068 } 12069 } 12070 12071 sal_memset(entry, 0, sizeof(epc_link_bmap_entry_t)); 12072 soc_mem_pbmp_field_set(unit, EPC_LINK_BMAPm, entry, PORT_BITMAPf, 12073 &PBMP_CMIC(unit)); 12074 SOC_IF_ERROR_RETURN(WRITE_EPC_LINK_BMAPm(unit, MEM_BLOCK_ALL, 0, entry)); 12075 12076 SOC_IF_ERROR_RETURN(READ_ING_CONFIG_64r(unit, &val64)); 12077 soc_reg64_field32_set(unit, ING_CONFIG_64r, &val64, 12078 APPLY_EGR_MASK_ON_L2f, 1); 12079 soc_reg64_field32_set(unit, ING_CONFIG_64r, &val64, 12080 APPLY_EGR_MASK_ON_L3f, 1); 12081 soc_reg64_field32_set(unit, ING_CONFIG_64r, &val64, 12082 ARP_RARP_TO_FPf, 0x3); /* enable both ARP & RARP */ 12083 soc_reg64_field32_set(unit, ING_CONFIG_64r, &val64, 12084 ARP_VALIDATION_ENf, 1); 12085 SOC_IF_ERROR_RETURN(WRITE_ING_CONFIG_64r(unit, val64)); 12086 12087 /* set to allow Mirror bit in Module Header */ 12088 SOC_IF_ERROR_RETURN 12089 (soc_reg_field32_modify(unit, EGR_CONFIG_1r, REG_PORT_ANY, 12090 RING_MODEf, 1)); 12091 12092 /* Multicast range initialization */ 12093 SOC_IF_ERROR_RETURN 12094 (soc_hbx_higig2_mcast_sizes_set(unit, 12095 soc_property_get(unit, spn_HIGIG2_MULTICAST_VLAN_RANGE, 12096 SOC_HBX_MULTICAST_RANGE_DEFAULT), 12097 soc_property_get(unit, spn_HIGIG2_MULTICAST_L2_RANGE, 12098 SOC_HBX_MULTICAST_RANGE_DEFAULT), 12099 soc_property_get(unit, spn_HIGIG2_MULTICAST_L3_RANGE, 12100 SOC_HBX_MULTICAST_RANGE_DEFAULT))); 12101 12102 /* Initialize FCOE standard Headers */ 12103 SOC_IF_ERROR_RETURN(_soc_tr3_fcoe_config_init(unit)); 12104 12105 /* 12106 * Set external MDIO freq to 12107 * 9.38MHz (450MHz), 8.65MHz (415MHz), or 6.56MHz (315 MHz) 12108 * target_freq = core_clock_freq * DIVIDEND / DIVISOR / 2 12109 */ 12110 divisor = soc_property_get(unit, spn_RATE_EXT_MDIO_DIVISOR, 24); 12111 dividend = soc_property_get(unit, spn_RATE_EXT_MDIO_DIVIDEND, 1); 12112 rval = 0; 12113 soc_reg_field_set(unit, CMIC_RATE_ADJUSTr, &rval, 12114 DIVISORf, divisor); 12115 soc_reg_field_set(unit, CMIC_RATE_ADJUSTr, &rval, 12116 DIVIDENDf, dividend); 12117 /* coverity[result_independent_of_operands] */ 12118 SOC_IF_ERROR_RETURN(WRITE_CMIC_RATE_ADJUSTr(unit, rval)); 12119 12120 /* 12121 * Set internal MDIO freq to 12122 * 37.5MHz (450MHz), 34.58MHz (415MHz), or 26.25MHz (315 MHz) 12123 * Valid range is from 2.5MHz to 40MHz 12124 * target_freq = core_clock_freq * DIVIDEND / DIVISOR / 2 12125 */ 12126 divisor = soc_property_get(unit, spn_RATE_INT_MDIO_DIVISOR, 18); 12127 dividend = soc_property_get(unit, spn_RATE_INT_MDIO_DIVIDEND, 1); 12128 rval = 0; 12129 soc_reg_field_set(unit, CMIC_RATE_ADJUST_INT_MDIOr, &rval, 12130 DIVISORf, divisor); 12131 soc_reg_field_set(unit, CMIC_RATE_ADJUST_INT_MDIOr, &rval, 12132 DIVIDENDf, dividend); 12133 /* coverity[result_independent_of_operands] */ 12134 SOC_IF_ERROR_RETURN(WRITE_CMIC_RATE_ADJUST_INT_MDIOr(unit, rval)); 12135 12136 delay = soc_property_get(unit, spn_MDIO_OUTPUT_DELAY, -1); 12137 if (delay >= 1 && delay <= 15) { 12138 /* coverity[result_independent_of_operands] */ 12139 SOC_IF_ERROR_RETURN(READ_CMIC_MIIM_CONFIGr(unit, &rval)); 12140 soc_reg_field_set(unit, CMIC_MIIM_CONFIGr, &rval, MDIO_OUT_DELAYf, 12141 delay); 12142 /* coverity[result_independent_of_operands] */ 12143 SOC_IF_ERROR_RETURN(WRITE_CMIC_MIIM_CONFIGr(unit, rval)); 12144 } 12145 12146 /* Enable IPFIX : default register value disable IPFIX. */ 12147 if (soc_feature(unit, soc_feature_ipfix)) { 12148 SOC_IF_ERROR_RETURN(READ_ING_IPFIX_CONFIGr(unit, &rval)); 12149 soc_reg_field_set(unit, ING_IPFIX_CONFIGr, &rval, DISABLE_ALLf, 0); 12150 SOC_IF_ERROR_RETURN(WRITE_ING_IPFIX_CONFIGr(unit, rval)); 12151 12152 SOC_IF_ERROR_RETURN(READ_EGR_IPFIX_CONFIGr(unit, &rval)); 12153 soc_reg_field_set(unit, EGR_IPFIX_CONFIGr, &rval, DISABLE_ALLf, 0); 12154 SOC_IF_ERROR_RETURN(WRITE_EGR_IPFIX_CONFIGr(unit, rval)); 12155 } 12156 12157 if ((!SOC_IS_HELIX4(unit)) && (rev_id & 0xF0)) { 12158 SOC_IF_ERROR_RETURN(READ_EGR_Q_BEGINr(unit, &rval)); 12159 soc_reg_field_set(unit, EGR_Q_BEGINr, &rval, 12160 L2_TUNNEL_DSCP_REMARK_SELf, 1); 12161 SOC_IF_ERROR_RETURN(WRITE_EGR_Q_BEGINr(unit, rval)); 12162 } 12163 12164 /* Setup SW2_FP_DST_ACTION_CONTROL */ 12165 fields[0] = HGTRUNK_RES_ENf; 12166 values[0] = 1; 12167 fields[1] = LAG_RES_ENf; 12168 values[1] = 1; 12169 SOC_IF_ERROR_RETURN(soc_reg_fields32_modify(unit, 12170 SW2_FP_DST_ACTION_CONTROLr, REG_PORT_ANY, 2, fields, values)); 12171 12172 #ifdef BCM_HELIX4_SUPPORT 12173 /* initialize LED UP0 */ 12174 if (SOC_IS_HELIX4(unit)) { 12175 if (!SOC_WARM_BOOT(unit)) { 12176 SOC_IF_ERROR_RETURN(_soc_hx4_ledup_init(unit)); 12177 } 12178 } else 12179 #endif /* BCM_HELIX4_SUPPORT */ 12180 { 12181 if (!SOC_WARM_BOOT(unit)) { 12182 SOC_IF_ERROR_RETURN(_soc_tr3_ledup_init(unit)); 12183 } 12184 } 12185 #ifdef BCM_CMICM_SUPPORT 12186 if (soc_mspi_init(unit) != SOC_E_NONE) { 12187 LOG_WARN(BSL_LS_SOC_COMMON, 12188 (BSL_META_U(unit, 12189 "unit %d : MSPI Init Failed\n"), unit)); 12190 } 12191 #endif 12192 12193 #ifdef BCM_HELIX4_SUPPORT 12194 if (SOC_IS_HELIX4(unit)) { 12195 _phy_wc40_firmware_set_helper[unit] = _hx4_wc40_firmware_set; 12196 }else 12197 #endif /* BCM_HELIX4_SUPPORT */ 12198 { 12199 _phy_wcmod_firmware_set_helper[unit] = tr3_wc_firmware_set; 12200 } 12201 12202 /* Initialize external TCAM */ 12203 if (soc_feature(unit, soc_feature_esm_support) && 12204 SOC_CONTROL(unit)->tcam_info) { 12205 /* The KBP MDIO interface is spec'd to run at 5MHz or less */ 12206 rv = soc_tr3_set_mdio_freq(unit, 5); 12207 if (rv < 0) { 12208 LOG_ERROR(BSL_LS_SOC_COMMON, 12209 (BSL_META_U(unit, 12210 "Failed to decrease the MDIO frequency\n"))); 12211 return rv; 12212 } 12213 /* initialize the ESMIF too */ 12214 rv = soc_tr3_esmif_init(unit); 12215 if (rv < 0) { 12216 soc_tr3_set_mdio_freq(unit, 0); 12217 LOG_ERROR(BSL_LS_SOC_COMMON, 12218 (BSL_META_U(unit, 12219 "ESM if initialization failed\n"))); 12220 return rv; 12221 } 12222 /*Restore the MDIO original configuration*/ 12223 rv = soc_tr3_set_mdio_freq(unit, 0); 12224 if (rv < 0) { 12225 LOG_ERROR(BSL_LS_SOC_COMMON, 12226 (BSL_META_U(unit, 12227 "Failed to restore the MDIO frequency\n"))); 12228 return rv; 12229 } 12230 12231 } else if (!SOC_IS_HELIX4(unit)) { 12232 /* put ESMIF in bypass */ 12233 rv = READ_ESMIF_INIT_CONFIGr(unit, &rval); 12234 if (rv < 0) { 12235 LOG_ERROR(BSL_LS_SOC_COMMON, 12236 (BSL_META_U(unit, 12237 "Reading ESMIF_INIT_CONFIG failed !!\n"))); 12238 return rv; 12239 } 12240 soc_reg_field_set(unit, ESMIF_INIT_CONFIGr, &rval, 12241 IESMIF_BYPASS_ENABLEf, 1); 12242 rv = WRITE_ESMIF_INIT_CONFIGr(unit, rval); 12243 if (rv < 0) { 12244 LOG_ERROR(BSL_LS_SOC_COMMON, 12245 (BSL_META_U(unit, 12246 "Writing ESMIF_INIT_CONFIG failed !!\n"))); 12247 return rv; 12248 } 12249 /* power down IESMIF memories */ 12250 rv = WRITE_IESMIF_MEMORY_CONTROLr(unit, 3); 12251 if (rv < 0) { 12252 LOG_ERROR(BSL_LS_SOC_COMMON, 12253 (BSL_META_U(unit, 12254 "Writing IESMIF_MEMORY_CONTROL failed !!\n"))); 12255 return rv; 12256 } 12257 } 12258 if (soc_feature(unit, soc_feature_esm_correction)) { 12259 rv = soc_tr3_esm_recovery_start(unit); 12260 if (rv < 0) { 12261 LOG_ERROR(BSL_LS_SOC_COMMON, 12262 (BSL_META_U(unit, 12263 "Creating ESM recovery thread failed\n"))); 12264 return rv; 12265 } 12266 } 12267 /* Populate and enable RTAG7 Macro flow offset table */ 12268 if (soc_mem_is_valid(unit, RTAG7_FLOW_BASED_HASHm)) { 12269 index_count = soc_mem_index_count(unit, RTAG7_FLOW_BASED_HASHm); 12270 sal_memset(entry, 0, sizeof(rtag7_flow_based_hash_entry_t)); 12271 for (index = 0; index < index_count; ) { 12272 for (sub_sel = 0; sub_sel < 8 && index < index_count; sub_sel++) { 12273 for (offset = 0; 12274 offset < rtag7_field_width[sub_sel] && index < index_count; 12275 offset++) { 12276 soc_mem_field32_set(unit, RTAG7_FLOW_BASED_HASHm, &entry, 12277 SUB_SEL_ECMPf, sub_sel); 12278 soc_mem_field32_set(unit, RTAG7_FLOW_BASED_HASHm, &entry, 12279 OFFSET_ECMPf, offset); 12280 SOC_IF_ERROR_RETURN 12281 (soc_mem_write(unit, RTAG7_FLOW_BASED_HASHm, 12282 MEM_BLOCK_ANY, index, &entry)); 12283 index++; 12284 } 12285 } 12286 } 12287 rval = 0; 12288 soc_reg_field_set(unit, RTAG7_HASH_SELr, &rval, USE_FLOW_SEL_ECMPf, 1); 12289 soc_reg_field_set(unit, RTAG7_HASH_SELr, &rval, 12290 USE_FLOW_SEL_TRILL_ECMPf, 1); 12291 SOC_IF_ERROR_RETURN(WRITE_RTAG7_HASH_SELr(unit, rval)); 12292 } 12293 if (parity_enable) { 12294 SOC_IF_ERROR_RETURN(soc_generic_ser_mem_scan_start(unit)); 12295 } 12296 12297 return SOC_E_NONE; 12298 } 12299 12300 STATIC int 12301 _soc_tr3_port_control(int unit, soc_port_t port, soc_block_type_t pbt, 12302 uint8 enable) 12303 { 12304 int blk, phy; 12305 soc_info_t *si = &SOC_INFO(unit); 12306 12307 phy = si->port_l2p_mapping[port]; 12308 LOG_VERBOSE(BSL_LS_SOC_COMMON, 12309 (BSL_META_U(unit, 12310 "%s port: log %d, phy %d\n"), FUNCTION_NAME(), port, phy)); 12311 12312 switch (pbt) { 12313 case SOC_BLK_XLPORT: 12314 SOC_BLOCK_ITER(unit, blk, SOC_BLK_XLPORT) { 12315 if (phy >= _soc_tr3_b2pp[blk] && phy <= _soc_tr3_b2pp[blk]+3) { 12316 SOC_IF_ERROR_RETURN 12317 (soc_reg_field32_modify(unit, PORT_MAC_CONTROLr, port, 12318 XMAC0_RESETf, enable ? 0 : 1)); 12319 return SOC_E_NONE; 12320 } else { 12321 LOG_ERROR(BSL_LS_SOC_COMMON, 12322 (BSL_META_U(unit, 12323 "Invalid port !!\n"))); 12324 } 12325 } 12326 break; 12327 case SOC_BLK_XWPORT: 12328 SOC_BLOCK_ITER(unit, blk, SOC_BLK_XWPORT) { 12329 if (phy >= _soc_tr3_b2pp[blk] && phy <= _soc_tr3_b2pp[blk]+3) { 12330 SOC_IF_ERROR_RETURN 12331 (soc_reg_field32_modify(unit, PORT_MAC_CONTROLr, port, 12332 XMAC0_RESETf, enable ? 0 : 1)); 12333 return SOC_E_NONE; 12334 } 12335 } 12336 break; 12337 case SOC_BLK_XTPORT: 12338 SOC_BLOCK_ITER(unit, blk, SOC_BLK_XTPORT) { 12339 if (phy >= _soc_tr3_b2pp[blk] && phy <= _soc_tr3_b2pp[blk]+3) { 12340 SOC_IF_ERROR_RETURN 12341 (soc_reg_field32_modify(unit, PORT_MAC_CONTROLr, port, 12342 XMAC0_RESETf, enable ? 0 : 1)); 12343 return SOC_E_NONE; 12344 } else if (phy >= _soc_tr3_b2pp[blk]+4 && phy <= _soc_tr3_b2pp[blk]+7) { 12345 SOC_IF_ERROR_RETURN 12346 (soc_reg_field32_modify(unit, PORT_MAC_CONTROLr, port, 12347 XMAC1_RESETf, enable ? 0 : 1)); 12348 return SOC_E_NONE; 12349 } else if (phy <= _soc_tr3_b2pp[blk]+11) { 12350 SOC_IF_ERROR_RETURN 12351 (soc_reg_field32_modify(unit, PORT_MAC_CONTROLr, port, 12352 XMAC2_RESETf, enable ? 0 : 1)); 12353 return SOC_E_NONE; 12354 } 12355 } 12356 break; 12357 case SOC_BLK_CLPORT: 12358 SOC_BLOCK_ITER(unit, blk, SOC_BLK_CLPORT) { 12359 if (phy >= _soc_tr3_b2pp[blk] && phy <= _soc_tr3_b2pp[blk]+3) { 12360 SOC_IF_ERROR_RETURN 12361 (soc_reg_field32_modify(unit, PORT_MAC_CONTROLr, port, 12362 XMAC0_RESETf, enable ? 0 : 1)); 12363 return SOC_E_NONE; 12364 } else if (phy >= _soc_tr3_b2pp[blk]+4 && phy <= _soc_tr3_b2pp[blk]+7) { 12365 SOC_IF_ERROR_RETURN 12366 (soc_reg_field32_modify(unit, PORT_MAC_CONTROLr, port, 12367 XMAC1_RESETf, enable ? 0 : 1)); 12368 return SOC_E_NONE; 12369 } else if (phy <= _soc_tr3_b2pp[blk]+11) { 12370 SOC_IF_ERROR_RETURN 12371 (soc_reg_field32_modify(unit, PORT_MAC_CONTROLr, port, 12372 XMAC2_RESETf, enable ? 0 : 1)); 12373 return SOC_E_NONE; 12374 } 12375 } 12376 break; 12377 default: 12378 return SOC_E_PORT; 12379 } 12380 return SOC_E_PORT; 12381 } 12382 12383 STATIC int 12384 _soc_tr3_egress_buffer_reset(int unit, soc_port_t port, soc_block_type_t pbt, 12385 uint8 reset) 12386 { 12387 int f=0, blk, phy; 12388 soc_info_t *si = &SOC_INFO(unit); 12389 soc_field_t field_xl[] = {XLP0_RESETf, XLP1_RESETf}; 12390 soc_field_t field_xw[] = {XWP0_RESETf, XWP1_RESETf, XWP2_RESETf}; 12391 soc_field_t field_xt[] = {XTP0_RESETf, XTP1_RESETf, XTP2_RESETf, XTP3_RESETf}; 12392 soc_field_t field_cl[] = {CLP0_RESETf, CLP1_RESETf}; 12393 12394 phy = si->port_l2p_mapping[port]; 12395 LOG_VERBOSE(BSL_LS_SOC_COMMON, 12396 (BSL_META_U(unit, 12397 "%s port: log %d, phy %d\n"), FUNCTION_NAME(), port, phy)); 12398 12399 switch (pbt) { 12400 case SOC_BLK_XLPORT: 12401 SOC_BLOCK_ITER(unit, blk, SOC_BLK_XLPORT) { 12402 if (phy >= _soc_tr3_b2pp[blk] && phy <= _soc_tr3_b2pp[blk]+3) { 12403 SOC_IF_ERROR_RETURN 12404 (soc_reg_field32_modify(unit, EGR_PORT_BUFFER_SFT_RESETr, port, 12405 field_xl[f], reset ? 0x1 : 0)); 12406 return SOC_E_NONE; 12407 } 12408 f++; 12409 } 12410 break; 12411 case SOC_BLK_XWPORT: 12412 SOC_BLOCK_ITER(unit, blk, SOC_BLK_XWPORT) { 12413 if (phy >= _soc_tr3_b2pp[blk] && phy <= _soc_tr3_b2pp[blk]+3) { 12414 #ifdef BCM_HELIX4_SUPPORT 12415 if( SOC_IS_HELIX4(unit) && (_tr3_port_config_id[unit]== 414) && 12416 (57 == si->port_l2p_mapping[port] || 61 == si->port_l2p_mapping[port])){ 12417 SOC_IF_ERROR_RETURN 12418 (soc_reg_field32_modify(unit, EGR_PORT_BUFFER_SFT_RESETr, port, 12419 field_xw[f+1], reset ? 0x1 : 0)); 12420 }else 12421 #endif 12422 { 12423 SOC_IF_ERROR_RETURN 12424 (soc_reg_field32_modify(unit, EGR_PORT_BUFFER_SFT_RESETr, port, 12425 field_xw[f], reset ? 0x1 : 0)); 12426 } 12427 return SOC_E_NONE; 12428 } 12429 f++; 12430 } 12431 break; 12432 case SOC_BLK_XTPORT: 12433 SOC_BLOCK_ITER(unit, blk, SOC_BLK_XTPORT) { 12434 if (phy >= _soc_tr3_b2pp[blk] && phy <= _soc_tr3_b2pp[blk]+3) { 12435 SOC_IF_ERROR_RETURN 12436 (soc_reg_field32_modify(unit, EGR_PORT_BUFFER_SFT_RESETr, port, 12437 field_xt[f], reset ? 0x1 : 0)); 12438 return SOC_E_NONE; 12439 } else if (phy >= _soc_tr3_b2pp[blk]+4 && phy <= _soc_tr3_b2pp[blk]+7) { 12440 SOC_IF_ERROR_RETURN 12441 (soc_reg_field32_modify(unit, EGR_PORT_BUFFER_SFT_RESETr, port, 12442 field_xt[f], reset ? 0x2 : 0)); 12443 return SOC_E_NONE; 12444 } else if (phy <= _soc_tr3_b2pp[blk]+11) { 12445 SOC_IF_ERROR_RETURN 12446 (soc_reg_field32_modify(unit, EGR_PORT_BUFFER_SFT_RESETr, port, 12447 field_xt[f], reset ? 0x4 : 0)); 12448 return SOC_E_NONE; 12449 } 12450 f++; 12451 } 12452 break; 12453 case SOC_BLK_CLPORT: 12454 SOC_BLOCK_ITER(unit, blk, SOC_BLK_CLPORT) { 12455 if (phy >= _soc_tr3_b2pp[blk] && phy <= _soc_tr3_b2pp[blk]+3) { 12456 SOC_IF_ERROR_RETURN 12457 (soc_reg_field32_modify(unit, EGR_PORT_BUFFER_SFT_RESETr, port, 12458 field_cl[f], reset ? 0x1 : 0)); 12459 return SOC_E_NONE; 12460 } else if (phy >= _soc_tr3_b2pp[blk]+4 && phy <= _soc_tr3_b2pp[blk]+7) { 12461 SOC_IF_ERROR_RETURN 12462 (soc_reg_field32_modify(unit, EGR_PORT_BUFFER_SFT_RESETr, port, 12463 field_cl[f], reset ? 0x2 : 0)); 12464 return SOC_E_NONE; 12465 } else if (phy <= _soc_tr3_b2pp[blk]+11) { 12466 SOC_IF_ERROR_RETURN 12467 (soc_reg_field32_modify(unit, EGR_PORT_BUFFER_SFT_RESETr, port, 12468 field_cl[f], reset ? 0x4 : 0)); 12469 return SOC_E_NONE; 12470 } 12471 f++; 12472 } 12473 break; 12474 default: 12475 return SOC_E_PORT; 12476 } 12477 return SOC_E_PORT; 12478 } 12479 12480 STATIC int 12481 _soc_tr3_port_soft_reset(int unit, soc_port_t port, soc_block_type_t pbt, 12482 uint8 reset) 12483 { 12484 int blk, phy; 12485 soc_info_t *si = &SOC_INFO(unit); 12486 12487 phy = si->port_l2p_mapping[port]; 12488 LOG_VERBOSE(BSL_LS_SOC_COMMON, 12489 (BSL_META_U(unit, 12490 "%s port: log %d, phy %d\n"), FUNCTION_NAME(), port, phy)); 12491 12492 switch (pbt) { 12493 case SOC_BLK_XLPORT: 12494 SOC_BLOCK_ITER(unit, blk, SOC_BLK_XLPORT) { 12495 if (phy >= _soc_tr3_b2pp[blk] && phy <= _soc_tr3_b2pp[blk]+3) { 12496 SOC_IF_ERROR_RETURN 12497 (soc_reg_field32_modify(unit, PORT_SOFT_RESETr, port, 12498 XPORT_CORE0f, reset ? 1 : 0)); 12499 return SOC_E_NONE; 12500 } else { 12501 LOG_ERROR(BSL_LS_SOC_COMMON, 12502 (BSL_META_U(unit, 12503 "Invalid port !!\n"))); 12504 } 12505 } 12506 break; 12507 case SOC_BLK_XWPORT: 12508 SOC_BLOCK_ITER(unit, blk, SOC_BLK_XWPORT) { 12509 if (phy >= _soc_tr3_b2pp[blk] && phy <= _soc_tr3_b2pp[blk]+3) { 12510 SOC_IF_ERROR_RETURN 12511 (soc_reg_field32_modify(unit, PORT_SOFT_RESETr, port, 12512 XPORT_CORE0f, reset ? 1 : 0)); 12513 return SOC_E_NONE; 12514 } 12515 } 12516 break; 12517 case SOC_BLK_XTPORT: 12518 SOC_BLOCK_ITER(unit, blk, SOC_BLK_XTPORT) { 12519 if (phy >= _soc_tr3_b2pp[blk] && phy <= _soc_tr3_b2pp[blk]+3) { 12520 SOC_IF_ERROR_RETURN 12521 (soc_reg_field32_modify(unit, PORT_SOFT_RESETr, port, 12522 XPORT_CORE0f, reset ? 1 : 0)); 12523 return SOC_E_NONE; 12524 } else if (phy >= _soc_tr3_b2pp[blk]+4 && phy <= _soc_tr3_b2pp[blk]+7) { 12525 SOC_IF_ERROR_RETURN 12526 (soc_reg_field32_modify(unit, PORT_SOFT_RESETr, port, 12527 XPORT_CORE1f, reset ? 1 : 0)); 12528 return SOC_E_NONE; 12529 } else if (phy <= _soc_tr3_b2pp[blk]+11) { 12530 SOC_IF_ERROR_RETURN 12531 (soc_reg_field32_modify(unit, PORT_SOFT_RESETr, port, 12532 XPORT_CORE2f, reset ? 1 : 0)); 12533 return SOC_E_NONE; 12534 } 12535 } 12536 break; 12537 case SOC_BLK_CLPORT: 12538 SOC_BLOCK_ITER(unit, blk, SOC_BLK_CLPORT) { 12539 if (phy >= _soc_tr3_b2pp[blk] && phy <= _soc_tr3_b2pp[blk]+3) { 12540 SOC_IF_ERROR_RETURN 12541 (soc_reg_field32_modify(unit, PORT_SOFT_RESETr, port, 12542 XPORT_CORE0f, reset ? 1 : 0)); 12543 return SOC_E_NONE; 12544 } else if (phy >= _soc_tr3_b2pp[blk]+4 && phy <= _soc_tr3_b2pp[blk]+7) { 12545 SOC_IF_ERROR_RETURN 12546 (soc_reg_field32_modify(unit, PORT_SOFT_RESETr, port, 12547 XPORT_CORE1f, reset ? 1 : 0)); 12548 return SOC_E_NONE; 12549 } else if (phy <= _soc_tr3_b2pp[blk]+11) { 12550 SOC_IF_ERROR_RETURN 12551 (soc_reg_field32_modify(unit, PORT_SOFT_RESETr, port, 12552 XPORT_CORE2f, reset ? 1 : 0)); 12553 return SOC_E_NONE; 12554 } 12555 } 12556 break; 12557 default: 12558 return SOC_E_PORT; 12559 } 12560 return SOC_E_PORT; 12561 } 12562 12563 STATIC int 12564 _soc_tr3_subport_disable(int unit, soc_port_t port, soc_block_type_t pbt, 12565 int count, uint8 disable) 12566 { 12567 static const soc_field_t port_field[] = { 12568 PORT0f, PORT1f, PORT2f, PORT3f, 12569 PORT4f, PORT5f, PORT6f, PORT7f, 12570 PORT8f, PORT9f, PORT10f, PORT11f 12571 }; 12572 12573 int bindex, blk, phy, incr = 1; 12574 soc_info_t *si = &SOC_INFO(unit); 12575 uint32 rval = 0; 12576 12577 #ifdef BCM_HELIX4_SUPPORT 12578 if ( SOC_IS_HELIX4(unit) && ((_tr3_port_config_id[unit]== 463)|| 12579 (_tr3_port_config_id[unit] == 413)) && 12580 (57 == si->port_l2p_mapping[port] || 61 == si->port_l2p_mapping[port])) 12581 { 12582 ; 12583 }else 12584 #endif 12585 { 12586 if (count==2) { 12587 count++; 12588 incr = 2; 12589 } 12590 } 12591 phy = si->port_l2p_mapping[port]; 12592 LOG_VERBOSE(BSL_LS_SOC_COMMON, 12593 (BSL_META_U(unit, 12594 "%s port: log %d, phy %d\n"), FUNCTION_NAME(), port, phy)); 12595 12596 switch (pbt) { 12597 case SOC_BLK_XLPORT: 12598 SOC_BLOCK_ITER(unit, blk, SOC_BLK_XLPORT) { 12599 if (phy >= _soc_tr3_b2pp[blk] && phy <= _soc_tr3_b2pp[blk]+3) { 12600 SOC_IF_ERROR_RETURN(READ_PORT_ENABLE_REGr(unit, port, &rval)); 12601 for (bindex = 0; bindex < count; bindex+=incr) { 12602 soc_reg_field_set(unit, PORT_ENABLE_REGr, &rval, 12603 port_field[bindex], disable ? 0 : 1); 12604 } 12605 SOC_IF_ERROR_RETURN(WRITE_PORT_ENABLE_REGr(unit, port, rval)); 12606 return SOC_E_NONE; 12607 } else { 12608 LOG_ERROR(BSL_LS_SOC_COMMON, 12609 (BSL_META_U(unit, 12610 "Invalid port !!\n"))); 12611 } 12612 } 12613 break; 12614 case SOC_BLK_XWPORT: 12615 SOC_BLOCK_ITER(unit, blk, SOC_BLK_XWPORT) { 12616 if (phy >= _soc_tr3_b2pp[blk] && phy <= _soc_tr3_b2pp[blk]+3) { 12617 SOC_IF_ERROR_RETURN(READ_PORT_ENABLE_REGr(unit, port, &rval)); 12618 for (bindex = 0; bindex < count; bindex+=incr) { 12619 soc_reg_field_set(unit, PORT_ENABLE_REGr, &rval, 12620 port_field[bindex], disable ? 0 : 1); 12621 } 12622 SOC_IF_ERROR_RETURN(WRITE_PORT_ENABLE_REGr(unit, port, rval)); 12623 return SOC_E_NONE; 12624 } 12625 } 12626 break; 12627 case SOC_BLK_XTPORT: 12628 SOC_BLOCK_ITER(unit, blk, SOC_BLK_XTPORT) { 12629 if (phy >= _soc_tr3_b2pp[blk] && phy <= _soc_tr3_b2pp[blk]+3) { 12630 SOC_IF_ERROR_RETURN(READ_PORT_ENABLE_REGr(unit, port, &rval)); 12631 for (bindex = 0; bindex < count; bindex+=incr) { 12632 soc_reg_field_set(unit, PORT_ENABLE_REGr, &rval, 12633 port_field[bindex], disable ? 0 : 1); 12634 } 12635 SOC_IF_ERROR_RETURN(WRITE_PORT_ENABLE_REGr(unit, port, rval)); 12636 return SOC_E_NONE; 12637 } else if (phy >= _soc_tr3_b2pp[blk]+4 && phy <= _soc_tr3_b2pp[blk]+7) { 12638 SOC_IF_ERROR_RETURN(READ_PORT_ENABLE_REGr(unit, port, &rval)); 12639 for (bindex = 4; bindex < 4+count; bindex+=incr) { 12640 soc_reg_field_set(unit, PORT_ENABLE_REGr, &rval, 12641 port_field[bindex], disable ? 0 : 1); 12642 } 12643 SOC_IF_ERROR_RETURN(WRITE_PORT_ENABLE_REGr(unit, port, rval)); 12644 return SOC_E_NONE; 12645 } else if (phy <= _soc_tr3_b2pp[blk]+11) { 12646 SOC_IF_ERROR_RETURN(READ_PORT_ENABLE_REGr(unit, port, &rval)); 12647 for (bindex = 8; bindex < 8+count; bindex+=incr) { 12648 soc_reg_field_set(unit, PORT_ENABLE_REGr, &rval, 12649 port_field[bindex], disable ? 0 : 1); 12650 } 12651 SOC_IF_ERROR_RETURN(WRITE_PORT_ENABLE_REGr(unit, port, rval)); 12652 return SOC_E_NONE; 12653 } 12654 } 12655 break; 12656 case SOC_BLK_CLPORT: 12657 SOC_BLOCK_ITER(unit, blk, SOC_BLK_CLPORT) { 12658 if (phy >= _soc_tr3_b2pp[blk] && phy <= _soc_tr3_b2pp[blk]+3) { 12659 SOC_IF_ERROR_RETURN(READ_PORT_ENABLE_REGr(unit, port, &rval)); 12660 for (bindex = 0; bindex < count; bindex+=incr) { 12661 soc_reg_field_set(unit, PORT_ENABLE_REGr, &rval, 12662 port_field[bindex], disable ? 0 : 1); 12663 } 12664 SOC_IF_ERROR_RETURN(WRITE_PORT_ENABLE_REGr(unit, port, rval)); 12665 return SOC_E_NONE; 12666 } else if (phy >= _soc_tr3_b2pp[blk]+4 && phy <= _soc_tr3_b2pp[blk]+7) { 12667 SOC_IF_ERROR_RETURN(READ_PORT_ENABLE_REGr(unit, port, &rval)); 12668 for (bindex = 4; bindex < 4+count; bindex+=incr) { 12669 soc_reg_field_set(unit, PORT_ENABLE_REGr, &rval, 12670 port_field[bindex], disable ? 0 : 1); 12671 } 12672 SOC_IF_ERROR_RETURN(WRITE_PORT_ENABLE_REGr(unit, port, rval)); 12673 return SOC_E_NONE; 12674 } else if (phy <= _soc_tr3_b2pp[blk]+11) { 12675 SOC_IF_ERROR_RETURN(READ_PORT_ENABLE_REGr(unit, port, &rval)); 12676 for (bindex = 8; bindex < 8+count; bindex+=incr) { 12677 soc_reg_field_set(unit, PORT_ENABLE_REGr, &rval, 12678 port_field[bindex], disable ? 0 : 1); 12679 } 12680 SOC_IF_ERROR_RETURN(WRITE_PORT_ENABLE_REGr(unit, port, rval)); 12681 return SOC_E_NONE; 12682 } 12683 } 12684 break; 12685 default: 12686 return SOC_E_PORT; 12687 } 12688 return SOC_E_PORT; 12689 } 12690 12691 STATIC int 12692 _soc_tr3_port_mode_set(int unit, soc_port_t port, soc_block_type_t pbt, 12693 int lanes) 12694 { 12695 int blk, phy; 12696 uint32 core_mode, phy_mode; 12697 soc_info_t *si = &SOC_INFO(unit); 12698 12699 phy = si->port_l2p_mapping[port]; 12700 LOG_VERBOSE(BSL_LS_SOC_COMMON, 12701 (BSL_META_U(unit, 12702 "%s port: log %d, phy %d\n"), FUNCTION_NAME(), port, phy)); 12703 12704 /* Note: lanes => means how many physical lanes/slot does a port use */ 12705 switch (lanes) { 12706 case 4: core_mode = CORE_MODE_SINGLE; 12707 phy_mode = (pbt == SOC_BLK_XTPORT) ? PHY_MODE_DUAL : 12708 ((si->port_speed_max[port] >= 10000) && 12709 (si->port_speed_max[port] <= 12000)) ? PHY_MODE_QUAD : 12710 PHY_MODE_SINGLE; 12711 break; 12712 case 2: core_mode = CORE_MODE_DUAL; 12713 phy_mode = (si->port_speed_max[port] == 10000) ? PHY_MODE_QUAD : 12714 PHY_MODE_DUAL; 12715 break; 12716 case 1: core_mode = CORE_MODE_QUAD; phy_mode = PHY_MODE_QUAD; 12717 break; 12718 default: 12719 return SOC_E_PARAM; 12720 } 12721 12722 switch (pbt) { 12723 case SOC_BLK_XLPORT: 12724 SOC_BLOCK_ITER(unit, blk, SOC_BLK_XLPORT) { 12725 if (phy >= _soc_tr3_b2pp[blk] && phy <= _soc_tr3_b2pp[blk]+3) { 12726 SOC_IF_ERROR_RETURN 12727 (soc_reg_field32_modify(unit, PORT_MODE_REGr, port, 12728 XPORT0_CORE_PORT_MODEf, core_mode)); 12729 SOC_IF_ERROR_RETURN 12730 (soc_reg_field32_modify(unit, PORT_MODE_REGr, port, 12731 XPORT0_PHY_PORT_MODEf, phy_mode)); 12732 SOC_IF_ERROR_RETURN 12733 (soc_reg_field32_modify(unit, PORT_MODE_REGr, port, 12734 XPC0_GMII_MII_ENABLEf, 12735 ((core_mode == CORE_MODE_QUAD)&& 12736 (!SOC_IS_HELIX4(unit))) ? 1 : 0)); 12737 return SOC_E_NONE; 12738 } else { 12739 LOG_ERROR(BSL_LS_SOC_COMMON, 12740 (BSL_META_U(unit, 12741 "Invalid port !!\n"))); 12742 } 12743 } 12744 break; 12745 case SOC_BLK_XWPORT: 12746 SOC_BLOCK_ITER(unit, blk, SOC_BLK_XWPORT) { 12747 if (phy >= _soc_tr3_b2pp[blk] && phy <= _soc_tr3_b2pp[blk]+3) { 12748 SOC_IF_ERROR_RETURN 12749 (soc_reg_field32_modify(unit, PORT_MODE_REGr, port, 12750 XPORT0_CORE_PORT_MODEf, core_mode)); 12751 SOC_IF_ERROR_RETURN 12752 (soc_reg_field32_modify(unit, PORT_MODE_REGr, port, 12753 XPORT0_PHY_PORT_MODEf, phy_mode)); 12754 SOC_IF_ERROR_RETURN 12755 (soc_reg_field32_modify(unit, PORT_MODE_REGr, port, 12756 XPC0_GMII_MII_ENABLEf, 12757 (!SOC_IS_HELIX4(unit)) ? 1 : 0)); 12758 return SOC_E_NONE; 12759 } 12760 } 12761 break; 12762 case SOC_BLK_XTPORT: 12763 SOC_BLOCK_ITER(unit, blk, SOC_BLK_XTPORT) { 12764 if (phy >= _soc_tr3_b2pp[blk] && phy <= _soc_tr3_b2pp[blk]+3) { 12765 SOC_IF_ERROR_RETURN 12766 (soc_reg_field32_modify(unit, PORT_MODE_REGr, port, 12767 XPORT0_CORE_PORT_MODEf, core_mode)); 12768 SOC_IF_ERROR_RETURN 12769 (soc_reg_field32_modify(unit, PORT_MODE_REGr, port, 12770 XPORT0_PHY_PORT_MODEf, phy_mode)); 12771 SOC_IF_ERROR_RETURN 12772 (soc_reg_field32_modify(unit, PORT_MODE_REGr, port, 12773 XPC0_GMII_MII_ENABLEf, 12774 ((core_mode == CORE_MODE_QUAD) && 12775 (!SOC_IS_HELIX4(unit)) ) ? 1 : 0)); 12776 return SOC_E_NONE; 12777 } else if (phy >= _soc_tr3_b2pp[blk]+4 && phy <= _soc_tr3_b2pp[blk]+7) { 12778 SOC_IF_ERROR_RETURN 12779 (soc_reg_field32_modify(unit, PORT_MODE_REGr, port, 12780 XPORT1_CORE_PORT_MODEf, core_mode)); 12781 SOC_IF_ERROR_RETURN 12782 (soc_reg_field32_modify(unit, PORT_MODE_REGr, port, 12783 XPORT1_PHY_PORT_MODEf, phy_mode)); 12784 SOC_IF_ERROR_RETURN 12785 (soc_reg_field32_modify(unit, PORT_MODE_REGr, port, 12786 XPC1_GMII_MII_ENABLEf, 12787 ((core_mode == CORE_MODE_QUAD) && 12788 (!SOC_IS_HELIX4(unit)) ) ? 1 : 0)); 12789 return SOC_E_NONE; 12790 } else if (phy <= _soc_tr3_b2pp[blk]+11) { 12791 SOC_IF_ERROR_RETURN 12792 (soc_reg_field32_modify(unit, PORT_MODE_REGr, port, 12793 XPORT2_CORE_PORT_MODEf, core_mode)); 12794 SOC_IF_ERROR_RETURN 12795 (soc_reg_field32_modify(unit, PORT_MODE_REGr, port, 12796 XPORT2_PHY_PORT_MODEf, phy_mode)); 12797 SOC_IF_ERROR_RETURN 12798 (soc_reg_field32_modify(unit, PORT_MODE_REGr, port, 12799 XPC2_GMII_MII_ENABLEf, 12800 ((core_mode == CORE_MODE_QUAD) && 12801 (!SOC_IS_HELIX4(unit)) ) ? 1 : 0)); 12802 return SOC_E_NONE; 12803 } 12804 } 12805 break; 12806 case SOC_BLK_CLPORT: 12807 SOC_BLOCK_ITER(unit, blk, SOC_BLK_CLPORT) { 12808 if (phy >= _soc_tr3_b2pp[blk] && phy <= _soc_tr3_b2pp[blk]+3) { 12809 SOC_IF_ERROR_RETURN 12810 (soc_reg_field32_modify(unit, PORT_MODE_REGr, port, 12811 XPORT0_CORE_PORT_MODEf, core_mode)); 12812 SOC_IF_ERROR_RETURN 12813 (soc_reg_field32_modify(unit, PORT_MODE_REGr, port, 12814 XPORT0_PHY_PORT_MODEf, phy_mode)); 12815 return SOC_E_NONE; 12816 } else if (phy >= _soc_tr3_b2pp[blk]+4 && phy <= _soc_tr3_b2pp[blk]+7) { 12817 SOC_IF_ERROR_RETURN 12818 (soc_reg_field32_modify(unit, PORT_MODE_REGr, port, 12819 XPORT1_CORE_PORT_MODEf, core_mode)); 12820 SOC_IF_ERROR_RETURN 12821 (soc_reg_field32_modify(unit, PORT_MODE_REGr, port, 12822 XPORT1_PHY_PORT_MODEf, phy_mode)); 12823 return SOC_E_NONE; 12824 } else if (phy <= _soc_tr3_b2pp[blk]+11) { 12825 SOC_IF_ERROR_RETURN 12826 (soc_reg_field32_modify(unit, PORT_MODE_REGr, port, 12827 XPORT2_CORE_PORT_MODEf, core_mode)); 12828 SOC_IF_ERROR_RETURN 12829 (soc_reg_field32_modify(unit, PORT_MODE_REGr, port, 12830 XPORT2_PHY_PORT_MODEf, phy_mode)); 12831 return SOC_E_NONE; 12832 } 12833 } 12834 break; 12835 default: 12836 return SOC_E_PORT; 12837 } 12838 return SOC_E_PORT; 12839 } 12840 12841 STATIC int 12842 _soc_tr3_port_type_set(int unit, soc_port_t port, int type) 12843 { 12844 port_tab_entry_t ptab; 12845 egr_port_entry_t eport; 12846 icontrol_opcode_bitmap_entry_t entry; 12847 soc_pbmp_t pbmp; 12848 12849 SOC_IF_ERROR_RETURN(READ_PORT_TABm(unit, MEM_BLOCK_ANY, port, &ptab)); 12850 soc_PORT_TABm_field32_set(unit, &ptab, PORT_TYPEf, type); 12851 SOC_IF_ERROR_RETURN(WRITE_PORT_TABm(unit, MEM_BLOCK_ANY, port, &ptab)); 12852 12853 SOC_IF_ERROR_RETURN(READ_EGR_PORTm(unit, MEM_BLOCK_ANY, port, &eport)); 12854 soc_EGR_PORTm_field32_set(unit, &eport, PORT_TYPEf, type); 12855 SOC_IF_ERROR_RETURN(WRITE_EGR_PORTm(unit, MEM_BLOCK_ANY, port, &eport)); 12856 12857 SOC_IF_ERROR_RETURN(READ_EGR_ING_PORTm(unit, MEM_BLOCK_ANY, port, &eport)); 12858 soc_EGR_ING_PORTm_field32_set(unit, &eport, PORT_TYPEf, type); 12859 SOC_IF_ERROR_RETURN(WRITE_EGR_ING_PORTm(unit, MEM_BLOCK_ANY, port, &eport)); 12860 12861 SOC_IF_ERROR_RETURN 12862 (READ_ICONTROL_OPCODE_BITMAPm(unit, MEM_BLOCK_ANY, port, &entry)); 12863 SOC_PBMP_CLEAR(pbmp); 12864 if (type == SOC_ENCAP_HIGIG) { 12865 SOC_PBMP_PORT_SET(pbmp, CMIC_PORT(unit)); 12866 } 12867 soc_mem_pbmp_field_set(unit, ICONTROL_OPCODE_BITMAPm, &entry, 12868 BITMAPf, &pbmp); 12869 SOC_IF_ERROR_RETURN 12870 (WRITE_ICONTROL_OPCODE_BITMAPm(unit, MEM_BLOCK_ANY, port, &entry)); 12871 return SOC_E_NONE; 12872 } 12873 12874 STATIC int 12875 _soc_tr3_current_port_speeds(int unit, int *m2s) 12876 { 12877 int mmu_port, port, phy_port; 12878 soc_info_t *si; 12879 12880 si = &SOC_INFO(unit); 12881 12882 for (mmu_port = 0; mmu_port < SOC_MAX_PHY_PORTS; mmu_port++) { 12883 m2s[mmu_port] = -1; 12884 } 12885 12886 PBMP_PORT_ITER(unit, port) { 12887 if (IS_CPU_PORT(unit, port) || IS_AXP_PORT(unit, port) || 12888 IS_LB_PORT(unit, port)) { 12889 continue; 12890 } 12891 phy_port = si->port_l2p_mapping[port]; 12892 mmu_port = si->port_p2m_mapping[phy_port]; 12893 m2s[mmu_port] = si->port_speed_max[port]; 12894 } 12895 12896 return 0; 12897 } 12898 12899 STATIC uint32 12900 _soc_tr3_get_mcfifo_config_val(int unit) 12901 { 12902 int i, j, l; 12903 int cm2s[SOC_MAX_PHY_PORTS]; 12904 uint32 mcfval = 0; 12905 12906 _soc_tr3_current_port_speeds(unit, cm2s); 12907 12908 for (i = 32; i < 48; i++) { 12909 if (cm2s[i] <= 0) { 12910 continue; 12911 } else if (cm2s[i] >= 10000) { 12912 mcfval |= 1 << (i - 32); 12913 } 12914 } 12915 12916 for (i = 47; i >= 44; i-= 1) { 12917 if (cm2s[i] <= 0) { 12918 continue; 12919 } else if (mcfval & (1 << (i - 32))) { 12920 l = (i - 36)*4; 12921 for (j = l; j < l + 4; j++) { 12922 if (i == j) { 12923 continue; 12924 } 12925 12926 if (cm2s[j] > 0) { 12927 mcfval |= 1 << (j - 32); 12928 } 12929 } 12930 } 12931 } 12932 12933 for (i = 32; i < 36; i++) { 12934 if (cm2s[i] <= 0) { 12935 mcfval &= ~(1 << (i - 32)); 12936 } else { 12937 l = (i/4) + 4; 12938 if (mcfval & (1 << l)) { 12939 mcfval |= 1 << (i - 32); 12940 } 12941 } 12942 } 12943 12944 return mcfval; 12945 } 12946 12947 #if 0 12948 STATIC int 12949 _soc_tr3_get_numq_and_fifo_size(int unit, int port, int *pcredits, int *pnumq) 12950 { 12951 int credits = 0, numq = 8, phy_port, mmu_port, speed; 12952 soc_info_t *si; 12953 uint32 mcfval = 0; 12954 12955 *pcredits = 0; 12956 *pnumq = 0; 12957 12958 si = &SOC_INFO(unit); 12959 12960 phy_port = si->port_l2p_mapping[port]; 12961 mmu_port = si->port_p2m_mapping[phy_port]; 12962 12963 if (mmu_port == 59) { 12964 *pnumq = 48; 12965 *pcredits = (12 * 1024)/48 & ~3; 12966 return 0; 12967 } else if (mmu_port == 56) { 12968 *pnumq = 8; 12969 *pcredits = (2 * 1024)/8 & ~3; 12970 return 0; 12971 } else if (mmu_port == 58) { 12972 *pnumq = 8; 12973 *pcredits = (4 * 1024)/8 & ~3; 12974 return 0; 12975 } else if (mmu_port == 60) { 12976 #if 0 12977 *pnumq = 8; 12978 *pcredits = (256)/numq; 12979 #else 12980 return 0; 12981 #endif 12982 } else if (mmu_port == 61) { 12983 *pnumq = 1; 12984 *pcredits = (256)/1 & ~3; 12985 return 0; 12986 } 12987 12988 speed = si->port_speed_max[port]; 12989 12990 if (speed <= 0) { 12991 return 0; 12992 } 12993 12994 numq = (((mmu_port >= 40) && (mmu_port <= 55)) && (IS_HG_PORT(unit,port))) ? 10 : 8; 12995 12996 if (mmu_port < 48) { 12997 if (mmu_port < 32) { 12998 if ((speed >= 1000) && (speed < 10000)) { 12999 credits = (256/numq) & ~3; 13000 } else if (speed >= 10000) { 13001 credits = (1024/numq) & ~3; 13002 } 13003 } else { 13004 mcfval = _soc_tr3_get_mcfifo_config_val(unit); 13005 if ((mmu_port >= 32) && (mmu_port <= 35)) { 13006 if (mcfval & (1 << 12)) { 13007 credits = 2048/numq & ~3; 13008 } else if (mcfval & (1 << (mmu_port - 32))) { 13009 credits = 2048/numq & ~3; 13010 } else { 13011 credits = 256/numq & ~3; 13012 } 13013 } else { 13014 if (mcfval & (1 << (mmu_port - 32))) { 13015 credits = 1024/numq & ~3; 13016 } else { 13017 credits = 256/numq & ~3; 13018 } 13019 } 13020 } 13021 } else { 13022 if (speed >= 100000) { 13023 credits = (10 * 2 * 2048)/numq & ~3; 13024 } else { 13025 credits = (2 * 2048)/numq & ~3; 13026 } 13027 } 13028 13029 LOG_VERBOSE(BSL_LS_SOC_COMMON, 13030 (BSL_META_U(unit, 13031 "MMU port=%d numq=%d credits=%d\n"), mmu_port, numq, credits)); 13032 13033 *pcredits = credits; 13034 *pnumq = numq; 13035 return 0; 13036 } 13037 #else 13038 STATIC int 13039 _soc_tr3_get_numq_and_fifo_size(int unit, int port, int *pcredits, int *pnumq) 13040 { 13041 int credits = 0, numq = 8, phy_port, mmu_port, speed; 13042 soc_info_t *si; 13043 13044 *pcredits = 0; 13045 *pnumq = 0; 13046 13047 si = &SOC_INFO(unit); 13048 13049 phy_port = si->port_l2p_mapping[port]; 13050 mmu_port = si->port_p2m_mapping[phy_port]; 13051 13052 if (mmu_port == 59) { 13053 *pnumq = 48; 13054 *pcredits = (12 * 1024)/48 & ~3; 13055 LOG_VERBOSE(BSL_LS_SOC_COMMON, 13056 (BSL_META_U(unit, 13057 "%s MMU port=%d numq=%d credits=%d\n"), 13058 SOC_PORT_NAME(unit, port), mmu_port, *pnumq, *pcredits)); 13059 return 0; 13060 } else if (mmu_port == 56) { 13061 *pnumq = 8; 13062 *pcredits = (2 * 1024)/8 & ~3; 13063 LOG_VERBOSE(BSL_LS_SOC_COMMON, 13064 (BSL_META_U(unit, 13065 "%s MMU port=%d numq=%d credits=%d\n"), 13066 SOC_PORT_NAME(unit, port), mmu_port, *pnumq, *pcredits)); 13067 return 0; 13068 } else if (mmu_port == 58) { 13069 *pnumq = 8; 13070 *pcredits = (4 * 1024)/8 & ~3; 13071 LOG_VERBOSE(BSL_LS_SOC_COMMON, 13072 (BSL_META_U(unit, 13073 "%s MMU port=%d numq=%d credits=%d\n"), 13074 SOC_PORT_NAME(unit, port), mmu_port, *pnumq, *pcredits)); 13075 return 0; 13076 } else if (mmu_port == 60) { 13077 *pnumq = 8; 13078 *pcredits = 256/8 & ~3; 13079 LOG_VERBOSE(BSL_LS_SOC_COMMON, 13080 (BSL_META_U(unit, 13081 "%s MMU port=%d numq=%d credits=%d\n"), 13082 SOC_PORT_NAME(unit, port), mmu_port, *pnumq, *pcredits)); 13083 return 0; 13084 } else if (mmu_port == 61) { 13085 *pnumq = 1; 13086 *pcredits = (256)/1 & ~3; 13087 LOG_VERBOSE(BSL_LS_SOC_COMMON, 13088 (BSL_META_U(unit, 13089 "%s MMU port=%d numq=%d credits=%d\n"), 13090 SOC_PORT_NAME(unit, port), mmu_port, *pnumq, *pcredits)); 13091 return 0; 13092 } 13093 13094 speed = si->port_speed_max[port]; 13095 13096 if (speed <= 0) { 13097 return 0; 13098 } 13099 13100 numq = ((mmu_port >= 40) && (mmu_port <= 55)) ? 10 : 8; 13101 13102 if ((speed >= 1000) && (speed < 10000)) { 13103 credits = (256/numq) & ~3; 13104 } else if ((speed >= 10000) && (speed < 20000)) { 13105 credits = (1024/numq) & ~3; 13106 } else if ((speed >= 20000) && (speed < 40000)) { 13107 if (mmu_port < 48) { 13108 credits = ((1 * 1024)/numq) & ~3; 13109 } else { 13110 credits = ((2 * 1024)/numq) & ~3; 13111 } 13112 } else if ((speed >= 40000) && (speed <= 42000)) { 13113 credits = ((2 * 2 * 1024)/numq) & ~3; 13114 } else if (speed > 42000) { 13115 numq = 10; 13116 credits = 2048; 13117 } 13118 13119 LOG_VERBOSE(BSL_LS_SOC_COMMON, 13120 (BSL_META_U(unit, 13121 "%s MMU port=%d numq=%d credits=%d\n"), 13122 SOC_PORT_NAME(unit, port), mmu_port, numq, credits)); 13123 13124 *pcredits = credits; 13125 *pnumq = numq; 13126 return 0; 13127 } 13128 #endif 13129 13130 STATIC int 13131 _soc_tr3_set_mcfifo_config(int unit) 13132 { 13133 uint32 fval, mcfval = 0, rval; 13134 13135 mcfval = _soc_tr3_get_mcfifo_config_val(unit); 13136 13137 SOC_IF_ERROR_RETURN(READ_MCFIFO_CONFIGr(unit, &rval)); 13138 fval = soc_reg_field_get(unit, MCFIFO_CONFIGr, rval, MODE_COMBINEf); 13139 if (fval != mcfval) { 13140 soc_reg_field_set(unit, MCFIFO_CONFIGr, &rval, MODE_COMBINEf, mcfval); 13141 13142 SOC_IF_ERROR_RETURN(WRITE_MCFIFO_CONFIGr(unit, rval)); 13143 } 13144 13145 LOG_VERBOSE(BSL_LS_SOC_COMMON, 13146 (BSL_META_U(unit, 13147 "MCFIFO_CONFIG=0x%08x\n"), mcfval)); 13148 return 0; 13149 } 13150 13151 STATIC int 13152 _soc_tr3_update_mcq_fifo(int unit, int *pm2s) 13153 { 13154 int cm2s[SOC_MAX_PHY_PORTS], mmu_port, port, phy_port, i, total_queues; 13155 soc_info_t *si; 13156 int credits = 0, numq; 13157 soc_reg_t reg; 13158 13159 si = &SOC_INFO(unit); 13160 13161 _soc_tr3_current_port_speeds(unit, cm2s); 13162 13163 PBMP_PORT_ITER(unit, port) { 13164 if (IS_CPU_PORT(unit, port) || IS_AXP_PORT(unit, port) || 13165 IS_LB_PORT(unit, port)) { 13166 continue; 13167 } 13168 phy_port = si->port_l2p_mapping[port]; 13169 mmu_port = si->port_p2m_mapping[phy_port]; 13170 13171 if (pm2s[mmu_port] == cm2s[mmu_port]) { 13172 continue; 13173 } 13174 13175 if (cm2s[mmu_port] <= 0) { 13176 continue; 13177 } 13178 13179 total_queues = ((mmu_port >= 40) && (mmu_port <= 55)) ? 10 : 8; 13180 13181 _soc_tr3_get_numq_and_fifo_size(unit, port, &credits, &numq); 13182 13183 13184 if ((mmu_port >= 40) && (mmu_port <= 47)) { 13185 reg = MCQ_FIFO_BASE_REGr; 13186 } else if ((mmu_port >= 48) && (mmu_port <= 55)) { 13187 reg = MCQ_FIFO_BASE_REG_48_55r; 13188 } else if ((mmu_port >= 36) && (mmu_port <= 39)) { 13189 reg = MCQ_FIFO_BASE_REG_36_39r; 13190 } else if ((mmu_port >= 32) && (mmu_port <= 35)) { 13191 reg = MCQ_FIFO_BASE_REG_32_35r; 13192 } else if (mmu_port == 56) { 13193 reg = MCQ_FIFO_BASE_REG_56r; 13194 } else if (mmu_port == 58) { 13195 reg = MCQ_FIFO_BASE_REG_PASSTHRUr; 13196 } else { 13197 reg = INVALIDr; 13198 } 13199 13200 for (i = 0; i < numq; i++) { 13201 LOG_VERBOSE(BSL_LS_SOC_COMMON, 13202 (BSL_META_U(unit, 13203 "Updating OVQ credits for port: %s(%d) = %d\n"), 13204 SOC_PORT_NAME(unit, port),i, credits)); 13205 LOG_VERBOSE(BSL_LS_SOC_COMMON, 13206 (BSL_META_U(unit, 13207 "Updating MCQ base for port: %s(%d) = %d\n"), 13208 SOC_PORT_NAME(unit, port), i, i*credits)); 13209 if (reg != INVALIDr) { 13210 if (credits < 2048) { 13211 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, reg, port, i, i*credits)); 13212 } else { 13213 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, reg, port, i, 0)); 13214 } 13215 } 13216 SOC_IF_ERROR_RETURN(WRITE_OVQ_MCQ_CREDITSr(unit, port, i, credits)); 13217 } 13218 13219 for (i = numq; i < total_queues; i++) { 13220 if (reg != INVALIDr) { 13221 if (credits < 2048) { 13222 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, reg, port, i, i*credits)); 13223 } else { 13224 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, reg, port, i, 0)); 13225 } 13226 } 13227 SOC_IF_ERROR_RETURN(WRITE_OVQ_MCQ_CREDITSr(unit, port, i, 0)); 13228 } 13229 } 13230 13231 _soc_tr3_set_mcfifo_config(unit); 13232 13233 return 0; 13234 } 13235 13236 /* 13237 * NOTE: number of lanes and number of ports mapping: 13238 * lanes: 1 => ports 4 13239 * lanes: 2 => ports 2 13240 * lanes: 4 => ports 1 13241 */ 13242 int 13243 soc_tr3_port_lanes_set(int unit, soc_port_t port, int lanes, 13244 int *old_lanes, int *mode_change) 13245 { 13246 static const soc_reg_t lls_port_credit_reg[] = { 13247 LLS_PORT_0_CREDITr, LLS_PORT_1_CREDITr, LLS_PORT_2_CREDITr, 13248 LLS_PORT_3_CREDITr, LLS_PORT_4_CREDITr, LLS_PORT_5_CREDITr, 13249 LLS_PORT_6_CREDITr, LLS_PORT_7_CREDITr, LLS_PORT_8_CREDITr, 13250 LLS_PORT_9_CREDITr, LLS_PORT_10_CREDITr, LLS_PORT_11_CREDITr, 13251 LLS_PORT_12_CREDITr, LLS_PORT_13_CREDITr, LLS_PORT_14_CREDITr, 13252 LLS_PORT_15_CREDITr, LLS_PORT_16_CREDITr, LLS_PORT_17_CREDITr, 13253 LLS_PORT_18_CREDITr, LLS_PORT_19_CREDITr, LLS_PORT_20_CREDITr, 13254 LLS_PORT_21_CREDITr, LLS_PORT_22_CREDITr, LLS_PORT_23_CREDITr, 13255 LLS_PORT_24_CREDITr, LLS_PORT_25_CREDITr, LLS_PORT_26_CREDITr, 13256 LLS_PORT_27_CREDITr, LLS_PORT_28_CREDITr, LLS_PORT_29_CREDITr, 13257 LLS_PORT_30_CREDITr, LLS_PORT_31_CREDITr, LLS_PORT_32_CREDITr, 13258 LLS_PORT_33_CREDITr, LLS_PORT_34_CREDITr, LLS_PORT_35_CREDITr, 13259 LLS_PORT_36_CREDITr, LLS_PORT_37_CREDITr, LLS_PORT_38_CREDITr, 13260 LLS_PORT_39_CREDITr, LLS_PORT_40_CREDITr, LLS_PORT_41_CREDITr, 13261 LLS_PORT_42_CREDITr, LLS_PORT_43_CREDITr, LLS_PORT_44_CREDITr, 13262 LLS_PORT_45_CREDITr, LLS_PORT_46_CREDITr, LLS_PORT_47_CREDITr, 13263 LLS_PORT_48_CREDITr, LLS_PORT_49_CREDITr, LLS_PORT_50_CREDITr, 13264 LLS_PORT_51_CREDITr, LLS_PORT_52_CREDITr, LLS_PORT_53_CREDITr, 13265 LLS_PORT_54_CREDITr, LLS_PORT_55_CREDITr, LLS_PORT_56_CREDITr, 13266 LLS_PORT_57_CREDITr, LLS_PORT_58_CREDITr, LLS_PORT_59_CREDITr, 13267 LLS_PORT_60_CREDITr, LLS_PORT_61_CREDITr, LLS_PORT_62_CREDITr 13268 }; 13269 13270 int hp, hgc = 0; 13271 int prev_port_speeds[SOC_MAX_PHY_PORTS]; 13272 soc_block_type_t pbt = 0; 13273 int i, phy, lport, old_value, count = 0; 13274 uint32 rval; 13275 soc_port_t it_port=0; 13276 egr_enable_entry_t egr_en; 13277 soc_info_t *si = &SOC_INFO(unit); 13278 int8 fgrp; 13279 int j; 13280 #ifdef BCM_HELIX4_SUPPORT 13281 uint16 dev_id = 0; 13282 uint8 rev_id = 0; 13283 #endif 13284 LOG_VERBOSE(BSL_LS_SOC_COMMON, 13285 (BSL_META_U(unit, 13286 "Set lane, port: %d : %d\n"), port, lanes)); 13287 if (!(lanes == 1 || lanes == 2 || lanes == 4)) { 13288 return SOC_E_PARAM; 13289 } 13290 #ifdef BCM_HELIX4_SUPPORT 13291 soc_cm_get_id(unit, &dev_id, &rev_id); 13292 if ((BCM56548H_DEVICE_ID == dev_id) && (lanes == 4) 13293 && ((port >= 46) && (port <= 53))) { 13294 return SOC_E_PARAM; 13295 } 13296 if ( SOC_IS_HELIX4(unit) && (_tr3_port_config_id[unit] == 463 || _tr3_port_config_id[unit] == 413) && 13297 (lanes == 4) && ((si->port_l2p_mapping[port] >= 57) && (si->port_l2p_mapping[port] <= 64))){ 13298 return SOC_E_PARAM; 13299 } 13300 if (SOC_IS_HELIX4(unit) && (_tr3_port_config_id[unit] == 414) && (lanes == 4)) { 13301 return SOC_E_PARAM; 13302 } 13303 #endif 13304 if (!soc_tr3_port_is_flex_port(unit, port)) { 13305 return SOC_E_PORT; 13306 } 13307 SOC_IF_ERROR_RETURN(soc_tr3_port_lanes_gen(unit, port, &old_value, &pbt)); 13308 *old_lanes = old_value; 13309 LOG_VERBOSE(BSL_LS_SOC_COMMON, 13310 (BSL_META_U(unit, 13311 "Old value: %d, pbt: %d\n"), old_value, pbt)); 13312 if (old_value == lanes) { 13313 return SOC_E_EXISTS; 13314 } 13315 if (IS_XT_PORT(unit, port) && lanes == 2) { 13316 return SOC_E_PARAM; 13317 } 13318 if ((SOC_IS_HELIX4(unit) && (lanes == 2) && 13319 (((_tr3_port_config_id[unit] == 464) || (_tr3_port_config_id[unit] == 410)) && 13320 (si->port_l2p_mapping[port] == 57 || si->port_l2p_mapping[port] == 61))) || 13321 (!SOC_IS_HELIX4(unit) && (lanes == 2) && 13322 ((_tr3_port_config_id[unit] == 112 || _tr3_port_config_id[unit] == 12) && 13323 (si->port_l2p_mapping[port] == 73 || si->port_l2p_mapping[port] == 77)))) { 13324 return SOC_E_PARAM; 13325 } 13326 13327 #define RECONFIGURE_PORT_TYPE_INFO(ptype) \ 13328 si->ptype.num = 0; \ 13329 si->ptype.min = si->ptype.max = -1; \ 13330 PBMP_ITER(si->ptype.bitmap, it_port) { \ 13331 si->ptype.port[si->ptype.num++] = it_port; \ 13332 if (si->ptype.min < 0) { \ 13333 si->ptype.min = it_port; \ 13334 } \ 13335 if (it_port > si->ptype.max) { \ 13336 si->ptype.max = it_port; \ 13337 } \ 13338 } 13339 SOC_CONTROL_LOCK(unit); 13340 13341 if (!SOC_WARM_BOOT(unit)) { 13342 _soc_tr3_current_port_speeds(unit, prev_port_speeds); 13343 } 13344 13345 /* update various speeds, bitmaps and port types */ 13346 /* NOTE: For 1 to n and 2 to n, do not assume that all ports in a group are the same */ 13347 if (old_value == 1 && lanes == 2) { /* 4xHGs[11] -> 2xHGd[21], 4xXFI/4x1GE -> 2xRXAUI */ 13348 if (IS_XE_PORT(unit, port) || IS_GE_PORT(unit, port)) { 13349 si->port_speed_max[port] = 10000; 13350 if (IS_GE_PORT(unit, port)) { 13351 SOC_PBMP_PORT_REMOVE(si->ge.bitmap, port); 13352 } else { 13353 SOC_PBMP_PORT_ADD(si->xe.bitmap, port); 13354 } 13355 #ifdef BCM_HELIX4_SUPPORT 13356 if(SOC_IS_HELIX4(unit) && (si->port_l2p_mapping[port] == 57 || si->port_l2p_mapping[port] == 61) && 13357 ((463 == _tr3_port_config_id[unit]) || (413 == _tr3_port_config_id[unit]))){ 13358 i = port + 1; 13359 if (IS_HG_PORT(unit, i)) { 13360 SOC_PBMP_PORT_ADD(si->st.disabled_bitmap, i); 13361 SOC_PBMP_PORT_ADD(si->hg.disabled_bitmap, i); 13362 _soc_tr3_port_type_set(unit, i, SOC_ENCAP_IEEE); 13363 *mode_change = SOC_ENCAP_IEEE; 13364 } else if (IS_GE_PORT(unit, i)) { 13365 SOC_PBMP_PORT_ADD(si->ge.disabled_bitmap, i); 13366 } else if (IS_XE_PORT(unit, i)) { 13367 SOC_PBMP_PORT_ADD(si->xe.disabled_bitmap, i); 13368 } 13369 SOC_PBMP_PORT_ADD(si->port.disabled_bitmap, i); 13370 SOC_PBMP_PORT_ADD(si->all.disabled_bitmap, i); 13371 si->port_speed_max[i] = 0; 13372 }else 13373 #endif 13374 { 13375 for (i = port + 1; i < port + 4; i++) { 13376 if (i == port+2) { 13377 if (IS_HG_PORT(unit, i)) { 13378 SOC_PBMP_PORT_REMOVE(si->st.bitmap, i); 13379 SOC_PBMP_PORT_REMOVE(si->hg.bitmap, i); 13380 _soc_tr3_port_type_set(unit, i, SOC_ENCAP_IEEE); 13381 *mode_change = SOC_ENCAP_IEEE; 13382 } else if (IS_GE_PORT(unit, i)) { 13383 SOC_PBMP_PORT_REMOVE(si->ge.bitmap, i); 13384 } 13385 si->port_speed_max[i] = si->port_speed_max[port]; 13386 SOC_PBMP_PORT_ADD(si->xe.bitmap, i); 13387 SOC_PBMP_PORT_ADD(si->ether.bitmap, i); 13388 } else { 13389 if (IS_HG_PORT(unit, i)) { 13390 SOC_PBMP_PORT_ADD(si->st.disabled_bitmap, i); 13391 SOC_PBMP_PORT_ADD(si->hg.disabled_bitmap, i); 13392 _soc_tr3_port_type_set(unit, i, SOC_ENCAP_IEEE); 13393 *mode_change = SOC_ENCAP_IEEE; 13394 } else if (IS_GE_PORT(unit, i)) { 13395 SOC_PBMP_PORT_ADD(si->ge.disabled_bitmap, i); 13396 } else if (IS_XE_PORT(unit, i)) { 13397 SOC_PBMP_PORT_ADD(si->xe.disabled_bitmap, i); 13398 } 13399 SOC_PBMP_PORT_ADD(si->port.disabled_bitmap, i); 13400 SOC_PBMP_PORT_ADD(si->all.disabled_bitmap, i); 13401 si->port_speed_max[i] = 0; 13402 } 13403 } 13404 } 13405 } else if (IS_HG_PORT(unit, port)) { 13406 si->port_speed_max[port] = 21000; 13407 #ifdef BCM_HELIX4_SUPPORT 13408 if(SOC_IS_HELIX4(unit) && (si->port_l2p_mapping[port] == 57 || si->port_l2p_mapping[port] == 61) && 13409 ((463 == _tr3_port_config_id[unit]) || (413 == _tr3_port_config_id[unit]))){ 13410 i = port + 1; 13411 if (IS_HG_PORT(unit, i)) { 13412 SOC_PBMP_PORT_ADD(si->st.disabled_bitmap, i); 13413 SOC_PBMP_PORT_ADD(si->hg.disabled_bitmap, i); 13414 } else if (IS_GE_PORT(unit, i)) { 13415 SOC_PBMP_PORT_ADD(si->ge.disabled_bitmap, i); 13416 } else if (IS_XE_PORT(unit, i)) { 13417 SOC_PBMP_PORT_ADD(si->xe.disabled_bitmap, i); 13418 } 13419 SOC_PBMP_PORT_ADD(si->port.disabled_bitmap, i); 13420 SOC_PBMP_PORT_ADD(si->all.disabled_bitmap, i); 13421 si->port_speed_max[i] = 0; 13422 }else 13423 #endif 13424 { 13425 for (i = port + 1; i < port + 4; i++) { 13426 if (i == port+2) { 13427 si->port_speed_max[i] = si->port_speed_max[port]; 13428 if (IS_XE_PORT(unit, i)) { 13429 SOC_PBMP_PORT_REMOVE(si->xe.bitmap, i); 13430 SOC_PBMP_PORT_REMOVE(si->ether.bitmap, i); 13431 _soc_tr3_port_type_set(unit, i, SOC_ENCAP_HIGIG); 13432 *mode_change = SOC_ENCAP_HIGIG; 13433 } else if (IS_GE_PORT(unit, port)) { 13434 SOC_PBMP_PORT_REMOVE(si->ge.bitmap, i); 13435 SOC_PBMP_PORT_REMOVE(si->ether.bitmap, i); 13436 _soc_tr3_port_type_set(unit, i, SOC_ENCAP_HIGIG); 13437 *mode_change = SOC_ENCAP_HIGIG; 13438 } 13439 SOC_PBMP_PORT_ADD(si->hg.bitmap, i); 13440 SOC_PBMP_PORT_ADD(si->st.bitmap, i); 13441 } else { 13442 if (IS_HG_PORT(unit, i)) { 13443 SOC_PBMP_PORT_ADD(si->st.disabled_bitmap, i); 13444 SOC_PBMP_PORT_ADD(si->hg.disabled_bitmap, i); 13445 } else if (IS_GE_PORT(unit, i)) { 13446 SOC_PBMP_PORT_ADD(si->ge.disabled_bitmap, i); 13447 } else if (IS_XE_PORT(unit, i)) { 13448 SOC_PBMP_PORT_ADD(si->xe.disabled_bitmap, i); 13449 } 13450 SOC_PBMP_PORT_ADD(si->port.disabled_bitmap, i); 13451 SOC_PBMP_PORT_ADD(si->all.disabled_bitmap, i); 13452 si->port_speed_max[i] = 0; 13453 } 13454 } 13455 } 13456 } else { 13457 LOG_ERROR(BSL_LS_SOC_COMMON, 13458 (BSL_META_U(unit, 13459 "Invalid port config for hotswap !!\n"))); 13460 SOC_CONTROL_UNLOCK(unit); 13461 return SOC_E_PARAM; 13462 } 13463 RECONFIGURE_PORT_TYPE_INFO(ether); 13464 RECONFIGURE_PORT_TYPE_INFO(st); 13465 RECONFIGURE_PORT_TYPE_INFO(hg); 13466 RECONFIGURE_PORT_TYPE_INFO(xe); 13467 RECONFIGURE_PORT_TYPE_INFO(ge); 13468 } else if (old_value == 1 && lanes == 4) { 13469 /* 4xHGs[11]/4xXFI/4x1GE/4x2.5GE -> HG[42]/40GE, 4x1GE/4x2.5GE -> XAUI */ 13470 if (IS_XT_PORT(unit, port)) { /* No HG allowed in XT so all ports are the same */ 13471 SOC_PBMP_PORT_REMOVE(si->ge.bitmap, port); 13472 SOC_PBMP_PORT_ADD(si->xe.bitmap, port); 13473 si->port_speed_max[port] = 11000; 13474 for (i = port + 1; i < port + 4; i++) { 13475 SOC_PBMP_PORT_ADD(si->ge.disabled_bitmap, i); 13476 SOC_PBMP_PORT_ADD(si->ether.disabled_bitmap, i); 13477 SOC_PBMP_PORT_ADD(si->port.disabled_bitmap, i); 13478 SOC_PBMP_PORT_ADD(si->all.disabled_bitmap, i); 13479 si->port_speed_max[i] = 0; 13480 } 13481 RECONFIGURE_PORT_TYPE_INFO(xe); 13482 RECONFIGURE_PORT_TYPE_INFO(ge); 13483 } else if (IS_XE_PORT(unit, port) || IS_GE_PORT(unit, port)) { 13484 uint8 to_xe = 0, to_40ge = 0; 13485 /* convert to XE for ports in CL1 block as per SKU/config */ 13486 if ((si->port_l2p_mapping[port] == 73 || si->port_l2p_mapping[port] == 77) && 13487 (_tr3_port_config_id[unit] == 40)) { 13488 to_xe = 1; 13489 } 13490 if (((si->port_l2p_mapping[port] == 53 || si->port_l2p_mapping[port] == 57 || 13491 si->port_l2p_mapping[port] == 61) && (_tr3_port_config_id[unit] == 71)) || 13492 ((si->port_l2p_mapping[port] == 53 || si->port_l2p_mapping[port] == 57 || 13493 si->port_l2p_mapping[port] == 61) && (_tr3_port_config_id[unit] == 72))) { 13494 to_40ge = 1; 13495 } 13496 if (IS_XE_PORT(unit, port)) { 13497 if (!(to_xe || to_40ge)) { 13498 SOC_PBMP_PORT_REMOVE(si->xe.bitmap, port); 13499 } 13500 SOC_PBMP_PORT_REMOVE(si->xl.bitmap, port); 13501 } else if (IS_GE_PORT(unit, port)) { 13502 SOC_PBMP_PORT_REMOVE(si->ge.bitmap, port); 13503 } 13504 if (!(to_xe || to_40ge)) { 13505 /* Validate new HG count */ 13506 PBMP_HG_ITER(unit, hp) { 13507 if (!SOC_PBMP_MEMBER(SOC_PORT_DISABLED_BITMAP(unit, port), hp)) { 13508 hgc++; 13509 } 13510 } 13511 if (hgc+1 > _SOC_TR3_MAX_HG_PORT_COUNT) { 13512 LOG_ERROR(BSL_LS_SOC_COMMON, 13513 (BSL_META_U(unit, 13514 "Port config error (Higig port count[%d] exceeded) !!\n"), 13515 hgc)); 13516 return SOC_E_PARAM; 13517 } 13518 SOC_PBMP_PORT_REMOVE(si->ether.bitmap, port); 13519 SOC_PBMP_PORT_ADD(si->hg.bitmap, port); 13520 SOC_PBMP_PORT_ADD(si->st.bitmap, port); 13521 _soc_tr3_port_type_set(unit, port, SOC_ENCAP_HIGIG); 13522 *mode_change = SOC_ENCAP_HIGIG; 13523 } 13524 if (SOC_IS_HELIX4(unit) || (!SOC_IS_HELIX4(unit) && ((_tr3_port_config_id[unit] == 112 || 13525 _tr3_port_config_id[unit] == 12) && (si->port_l2p_mapping[port] == 73 || 13526 si->port_l2p_mapping[port] == 77)))) { 13527 soc_tr3_flex_port_grp(unit,port,&fgrp); 13528 si->port_speed_max[port] = _tr3_flex_port_inf[unit].def_flex_port_speeds[fgrp][0] * 1000; 13529 phy = si->port_l2p_mapping[port]; 13530 for (j = phy + 1; j < phy + 4; j++) { 13531 i = si->port_p2l_mapping[j]; 13532 if (i < 0) { 13533 continue; 13534 } 13535 if (IS_XE_PORT(unit, i) || IS_GE_PORT(unit, i)) { 13536 if (IS_XE_PORT(unit, i)) { 13537 SOC_PBMP_PORT_ADD(si->xe.disabled_bitmap, i); 13538 } else if (IS_GE_PORT(unit, i)) { 13539 SOC_PBMP_PORT_ADD(si->ge.disabled_bitmap, i); 13540 } 13541 SOC_PBMP_PORT_ADD(si->ether.disabled_bitmap, i); 13542 } else if (IS_HG_PORT(unit, i)) { 13543 SOC_PBMP_PORT_ADD(si->st.disabled_bitmap, i); 13544 SOC_PBMP_PORT_ADD(si->hg.disabled_bitmap, i); 13545 } 13546 SOC_PBMP_PORT_ADD(si->port.disabled_bitmap, i); 13547 SOC_PBMP_PORT_ADD(si->all.disabled_bitmap, i); 13548 si->port_speed_max[i] = 0; 13549 } 13550 } else { 13551 si->port_speed_max[port] = (to_xe) ? ((to_40ge) ? 40000 : 11000) : 42000; 13552 for (i = port + 1; i < port + 4; i++) { 13553 if (IS_XE_PORT(unit, i) || IS_GE_PORT(unit, i)) { 13554 if (IS_XE_PORT(unit, i)) { 13555 SOC_PBMP_PORT_ADD(si->xe.disabled_bitmap, i); 13556 } else if (IS_GE_PORT(unit, i)) { 13557 SOC_PBMP_PORT_ADD(si->ge.disabled_bitmap, i); 13558 } 13559 SOC_PBMP_PORT_ADD(si->ether.disabled_bitmap, i); 13560 } else if (IS_HG_PORT(unit, i)) { 13561 SOC_PBMP_PORT_ADD(si->st.disabled_bitmap, i); 13562 SOC_PBMP_PORT_ADD(si->hg.disabled_bitmap, i); 13563 } 13564 SOC_PBMP_PORT_ADD(si->port.disabled_bitmap, i); 13565 SOC_PBMP_PORT_ADD(si->all.disabled_bitmap, i); 13566 si->port_speed_max[i] = 0; 13567 } 13568 } 13569 RECONFIGURE_PORT_TYPE_INFO(ether); 13570 RECONFIGURE_PORT_TYPE_INFO(st); 13571 RECONFIGURE_PORT_TYPE_INFO(hg); 13572 RECONFIGURE_PORT_TYPE_INFO(xe); 13573 RECONFIGURE_PORT_TYPE_INFO(ge); 13574 } else if (IS_HG_PORT(unit, port)) { 13575 if (SOC_IS_HELIX4(unit) || (!SOC_IS_HELIX4(unit) && ((_tr3_port_config_id[unit] == 112 || 13576 _tr3_port_config_id[unit] == 12) && (si->port_l2p_mapping[port] == 73 || 13577 si->port_l2p_mapping[port] == 77)))) { 13578 soc_tr3_flex_port_grp(unit,port,&fgrp); 13579 si->port_speed_max[port] = _tr3_flex_port_inf[unit].def_flex_port_speeds[fgrp][0] * 1000; 13580 phy = si->port_l2p_mapping[port]; 13581 for (j = phy + 1; j < phy + 4; j++) { 13582 i = si->port_p2l_mapping[j]; 13583 if (i < 0) { 13584 continue; 13585 } 13586 if (IS_HG_PORT(unit, i)) { 13587 SOC_PBMP_PORT_ADD(si->hg.disabled_bitmap, i); 13588 SOC_PBMP_PORT_ADD(si->st.disabled_bitmap, i); 13589 } else if (IS_XE_PORT(unit, i) || IS_GE_PORT(unit, i)) { 13590 if (IS_XE_PORT(unit, i)) { 13591 SOC_PBMP_PORT_ADD(si->xe.disabled_bitmap, i); 13592 } else if (IS_GE_PORT(unit, i)) { 13593 SOC_PBMP_PORT_ADD(si->ge.disabled_bitmap, i); 13594 } 13595 SOC_PBMP_PORT_ADD(si->ether.disabled_bitmap, i); 13596 } 13597 SOC_PBMP_PORT_ADD(si->port.disabled_bitmap, i); 13598 SOC_PBMP_PORT_ADD(si->all.disabled_bitmap, i); 13599 si->port_speed_max[i] = 0; 13600 } 13601 } else { 13602 si->port_speed_max[port] = 42000; 13603 for (i = port + 1; i < port + 4; i++) { 13604 if (IS_HG_PORT(unit, i)) { 13605 SOC_PBMP_PORT_ADD(si->hg.disabled_bitmap, i); 13606 SOC_PBMP_PORT_ADD(si->st.disabled_bitmap, i); 13607 } else if (IS_XE_PORT(unit, i) || IS_GE_PORT(unit, i)) { 13608 if (IS_XE_PORT(unit, i)) { 13609 SOC_PBMP_PORT_ADD(si->xe.disabled_bitmap, i); 13610 } else if (IS_GE_PORT(unit, i)) { 13611 SOC_PBMP_PORT_ADD(si->ge.disabled_bitmap, i); 13612 } 13613 SOC_PBMP_PORT_ADD(si->ether.disabled_bitmap, i); 13614 } 13615 SOC_PBMP_PORT_ADD(si->port.disabled_bitmap, i); 13616 SOC_PBMP_PORT_ADD(si->all.disabled_bitmap, i); 13617 si->port_speed_max[i] = 0; 13618 } 13619 } 13620 RECONFIGURE_PORT_TYPE_INFO(ether); 13621 RECONFIGURE_PORT_TYPE_INFO(st); 13622 RECONFIGURE_PORT_TYPE_INFO(hg); 13623 RECONFIGURE_PORT_TYPE_INFO(xe); 13624 RECONFIGURE_PORT_TYPE_INFO(ge); 13625 } else { 13626 LOG_ERROR(BSL_LS_SOC_COMMON, 13627 (BSL_META_U(unit, 13628 "Invalid port config for hotswap !!\n"))); 13629 SOC_CONTROL_UNLOCK(unit); 13630 return SOC_E_PARAM; 13631 } 13632 } else if (old_value == 2 && lanes == 1) { 13633 if (IS_HG_PORT(unit, port)) { /* 2HGd[21] -> 4xHGs[11] */ 13634 /* Validate new HG count */ 13635 PBMP_HG_ITER(unit, hp) { 13636 if (!SOC_PBMP_MEMBER(SOC_PORT_DISABLED_BITMAP(unit, port), hp)) { 13637 hgc++; 13638 } 13639 } 13640 if (hgc+3 > _SOC_TR3_MAX_HG_PORT_COUNT) { 13641 LOG_ERROR(BSL_LS_SOC_COMMON, 13642 (BSL_META_U(unit, 13643 "Port config error (Higig port count[%d] exceeded) !!\n"), 13644 hgc)); 13645 return SOC_E_PARAM; 13646 } 13647 si->port_speed_max[port] = 11000; 13648 for (i = port + 1; i < port + 4; i++) { 13649 #ifdef BCM_HELIX4_SUPPORT 13650 if(SOC_IS_HELIX4(unit) && (si->port_l2p_mapping[port] == 57 || 13651 si->port_l2p_mapping[port] == 61) && ((463 == _tr3_port_config_id[unit]) 13652 || (413 == _tr3_port_config_id[unit]))&& 13653 (i>(port + 1))){ 13654 break; 13655 } 13656 #endif 13657 si->port_speed_max[i] = si->port_speed_max[port]; 13658 SOC_PBMP_PORT_ADD(si->hg.bitmap, i); 13659 SOC_PBMP_PORT_ADD(si->st.bitmap, i); 13660 SOC_PBMP_PORT_REMOVE(si->xe.bitmap, i); 13661 SOC_PBMP_PORT_REMOVE(si->ge.bitmap, i); 13662 SOC_PBMP_PORT_REMOVE(si->ether.bitmap, i); 13663 SOC_PBMP_PORT_REMOVE(si->st.disabled_bitmap, i); 13664 SOC_PBMP_PORT_REMOVE(si->hg.disabled_bitmap, i); 13665 SOC_PBMP_PORT_REMOVE(si->port.disabled_bitmap, i); 13666 SOC_PBMP_PORT_REMOVE(si->all.disabled_bitmap, i); 13667 } 13668 } else if (IS_XE_PORT(unit, port)) { /* 2xRXAUI -> 4xXFI */ 13669 si->port_speed_max[port] = 11000; 13670 for (i = port + 1; i < port + 4; i++) { 13671 #ifdef BCM_HELIX4_SUPPORT 13672 if(SOC_IS_HELIX4(unit) && (si->port_l2p_mapping[port] == 57 || 13673 si->port_l2p_mapping[port] == 61) && ((463 == _tr3_port_config_id[unit])|| 13674 (413 == _tr3_port_config_id[unit])) && (i>(port + 1))){ 13675 break; 13676 } 13677 #endif 13678 si->port_speed_max[i] = si->port_speed_max[port]; 13679 SOC_PBMP_PORT_ADD(si->xe.bitmap, i); 13680 SOC_PBMP_PORT_ADD(si->ether.bitmap, i); 13681 SOC_PBMP_PORT_REMOVE(si->st.bitmap, i); 13682 SOC_PBMP_PORT_REMOVE(si->hg.bitmap, i); 13683 SOC_PBMP_PORT_REMOVE(si->xe.disabled_bitmap, i); 13684 SOC_PBMP_PORT_REMOVE(si->ether.disabled_bitmap, i); 13685 SOC_PBMP_PORT_REMOVE(si->port.disabled_bitmap, i); 13686 SOC_PBMP_PORT_REMOVE(si->all.disabled_bitmap, i); 13687 } 13688 } else { 13689 LOG_ERROR(BSL_LS_SOC_COMMON, 13690 (BSL_META_U(unit, 13691 "Invalid port config for hotswap !!\n"))); 13692 SOC_CONTROL_UNLOCK(unit); 13693 return SOC_E_PARAM; 13694 } 13695 RECONFIGURE_PORT_TYPE_INFO(ether); 13696 RECONFIGURE_PORT_TYPE_INFO(st); 13697 RECONFIGURE_PORT_TYPE_INFO(hg); 13698 RECONFIGURE_PORT_TYPE_INFO(xe); 13699 RECONFIGURE_PORT_TYPE_INFO(ge); 13700 } else if (old_value == 2 && lanes == 4) { /* 2HGd[21]/2xRXAUI -> HG[42]/40GE */ 13701 if (IS_HG_PORT(unit, port)) { 13702 #ifdef BCM_HELIX4_SUPPORT 13703 if (SOC_IS_HELIX4(unit)) { 13704 soc_tr3_flex_port_grp(unit,port,&fgrp); 13705 si->port_speed_max[port] = _tr3_flex_port_inf[unit].def_flex_port_speeds[fgrp][0] * 1000; 13706 } 13707 else 13708 #endif 13709 { 13710 si->port_speed_max[port] = 42000; 13711 } 13712 13713 SOC_PBMP_PORT_ADD(si->st.disabled_bitmap, port+2); 13714 SOC_PBMP_PORT_ADD(si->hg.disabled_bitmap, port+2); 13715 SOC_PBMP_PORT_ADD(si->port.disabled_bitmap, port+2); 13716 SOC_PBMP_PORT_ADD(si->all.disabled_bitmap, port+2); 13717 si->port_speed_max[port+2] = 0; 13718 } else if (IS_XE_PORT(unit, port)) { 13719 if (((si->port_l2p_mapping[port] == 53 || si->port_l2p_mapping[port] == 57 || 13720 si->port_l2p_mapping[port] == 61) && (_tr3_port_config_id[unit] == 71)) || 13721 ((si->port_l2p_mapping[port] == 53 || si->port_l2p_mapping[port] == 57 || 13722 si->port_l2p_mapping[port] == 61) && (_tr3_port_config_id[unit] == 72))) { 13723 si->port_speed_max[port] = 40000; 13724 SOC_PBMP_PORT_ADD(si->xe.disabled_bitmap, port+2); 13725 SOC_PBMP_PORT_ADD(si->port.disabled_bitmap, port+2); 13726 SOC_PBMP_PORT_ADD(si->all.disabled_bitmap, port+2); 13727 si->port_speed_max[port+2] = 0; 13728 } else { 13729 /* Validate new HG count */ 13730 PBMP_HG_ITER(unit, hp) { 13731 if (!SOC_PBMP_MEMBER(SOC_PORT_DISABLED_BITMAP(unit, port), hp)) { 13732 hgc++; 13733 } 13734 } 13735 if (hgc+1 > _SOC_TR3_MAX_HG_PORT_COUNT) { 13736 LOG_ERROR(BSL_LS_SOC_COMMON, 13737 (BSL_META_U(unit, 13738 "Port config error (Higig port count[%d] exceeded) !!\n"), 13739 hgc)); 13740 return SOC_E_PARAM; 13741 } 13742 13743 #ifdef BCM_HELIX4_SUPPORT 13744 if (SOC_IS_HELIX4(unit)) { 13745 soc_tr3_flex_port_grp(unit,port,&fgrp); 13746 si->port_speed_max[port] = _tr3_flex_port_inf[unit].def_flex_port_speeds[fgrp][0] * 1000; 13747 } 13748 else 13749 #endif 13750 { 13751 si->port_speed_max[port] = 42000; 13752 } 13753 13754 SOC_PBMP_PORT_REMOVE(si->xe.bitmap, port); 13755 SOC_PBMP_PORT_REMOVE(si->ether.bitmap, port); 13756 SOC_PBMP_PORT_ADD(si->hg.bitmap, port); 13757 SOC_PBMP_PORT_ADD(si->st.bitmap, port); 13758 _soc_tr3_port_type_set(unit, port, SOC_ENCAP_HIGIG); 13759 *mode_change = SOC_ENCAP_HIGIG; 13760 SOC_PBMP_PORT_ADD(si->xe.disabled_bitmap, port+2); 13761 SOC_PBMP_PORT_ADD(si->ether.disabled_bitmap, port+2); 13762 SOC_PBMP_PORT_ADD(si->port.disabled_bitmap, port+2); 13763 SOC_PBMP_PORT_ADD(si->all.disabled_bitmap, port+2); 13764 si->port_speed_max[port+2] = 0; 13765 RECONFIGURE_PORT_TYPE_INFO(ether); 13766 RECONFIGURE_PORT_TYPE_INFO(st); 13767 RECONFIGURE_PORT_TYPE_INFO(hg); 13768 RECONFIGURE_PORT_TYPE_INFO(xe); 13769 } 13770 } else { 13771 LOG_ERROR(BSL_LS_SOC_COMMON, 13772 (BSL_META_U(unit, 13773 "Invalid port config for hotswap !!\n"))); 13774 SOC_CONTROL_UNLOCK(unit); 13775 return SOC_E_PARAM; 13776 } 13777 } else if (old_value == 4 && lanes == 1) { 13778 /* HG[42] -> 4xHGs[11], HG[21]/XAUI -> 4x1GE, 40GE -> 4x10GE */ 13779 if (IS_HG_PORT(unit, port)) { 13780 /* Handle F.HG[21] HG[21] case */ 13781 if (si->port_speed_max[port] == 21000 && 13782 si->port_l2p_mapping[port] > 72) { 13783 SOC_PBMP_PORT_REMOVE(si->hg.bitmap, port); 13784 SOC_PBMP_PORT_REMOVE(si->st.bitmap, port); 13785 SOC_PBMP_PORT_ADD(si->ge.bitmap, port); 13786 si->port_speed_max[port] = 1000; 13787 _soc_tr3_port_type_set(unit, port, SOC_ENCAP_IEEE); 13788 *mode_change = SOC_ENCAP_IEEE; 13789 for (i = port + 1; i < port + 4; i++) { 13790 si->port_speed_max[i] = 1000; 13791 SOC_PBMP_PORT_ADD(si->ge.bitmap, i); 13792 SOC_PBMP_PORT_ADD(si->ether.bitmap, i); 13793 if (IS_XE_PORT(unit, i)) { 13794 SOC_PBMP_PORT_REMOVE(si->xe.bitmap, i); 13795 } else { 13796 SOC_PBMP_PORT_REMOVE(si->hg.bitmap, i); 13797 SOC_PBMP_PORT_REMOVE(si->st.bitmap, i); 13798 _soc_tr3_port_type_set(unit, i, SOC_ENCAP_IEEE); 13799 *mode_change = SOC_ENCAP_IEEE; 13800 } 13801 SOC_PBMP_PORT_REMOVE(si->ge.disabled_bitmap, i); 13802 SOC_PBMP_PORT_REMOVE(si->ether.disabled_bitmap, i); 13803 SOC_PBMP_PORT_REMOVE(si->port.disabled_bitmap, i); 13804 SOC_PBMP_PORT_REMOVE(si->all.disabled_bitmap, i); 13805 } 13806 } else { 13807 /* Validate new HG count */ 13808 PBMP_HG_ITER(unit, hp) { 13809 if (!SOC_PBMP_MEMBER(SOC_PORT_DISABLED_BITMAP(unit, port), hp)) { 13810 hgc++; 13811 } 13812 } 13813 if (hgc+3 > _SOC_TR3_MAX_HG_PORT_COUNT) { 13814 LOG_ERROR(BSL_LS_SOC_COMMON, 13815 (BSL_META_U(unit, 13816 "Port config error (Higig port count[%d] exceeded) !!\n"), 13817 hgc)); 13818 return SOC_E_PARAM; 13819 } 13820 if ((SOC_IS_HELIX4(unit) && (((_tr3_port_config_id[unit] == 464 )||(_tr3_port_config_id[unit] == 410 )) && 13821 (si->port_l2p_mapping[port] == 57 || si->port_l2p_mapping[port] == 61))) || 13822 (!SOC_IS_HELIX4(unit) && ((_tr3_port_config_id[unit] == 112 || _tr3_port_config_id[unit] == 12) && 13823 (si->port_l2p_mapping[port] == 73 || si->port_l2p_mapping[port] == 77)))) { 13824 soc_tr3_flex_port_grp(unit,port,&fgrp); 13825 si->port_speed_max[port] = _tr3_flex_port_inf[unit].def_flex_port_speeds[fgrp][2] * 1000; 13826 phy = si->port_l2p_mapping[port]; 13827 for (j = phy + 1; j < phy + 4; j++) { 13828 i = si->port_p2l_mapping[j]; 13829 if (i < 0) { 13830 continue; 13831 } 13832 SOC_PBMP_PORT_ADD(si->ge.disabled_bitmap, i); 13833 SOC_PBMP_PORT_ADD(si->ether.disabled_bitmap, i); 13834 SOC_PBMP_PORT_ADD(si->port.disabled_bitmap, i); 13835 SOC_PBMP_PORT_ADD(si->all.disabled_bitmap, i); 13836 si->port_speed_max[i] = 0; 13837 SOC_PBMP_PORT_REMOVE(si->xe.bitmap, i); 13838 SOC_PBMP_PORT_REMOVE(si->ether.bitmap, i); 13839 *mode_change = SOC_ENCAP_HIGIG; 13840 } 13841 } else { 13842 si->port_speed_max[port] = 11000; 13843 for (i = port + 1; i < port + 4; i++) { 13844 si->port_speed_max[i] = si->port_speed_max[port]; 13845 SOC_PBMP_PORT_ADD(si->hg.bitmap, i); 13846 SOC_PBMP_PORT_ADD(si->st.bitmap, i); 13847 SOC_PBMP_PORT_REMOVE(si->xe.bitmap, i); 13848 SOC_PBMP_PORT_REMOVE(si->ether.bitmap, i); 13849 SOC_PBMP_PORT_REMOVE(si->port.disabled_bitmap, i); 13850 SOC_PBMP_PORT_REMOVE(si->all.disabled_bitmap, i); 13851 _soc_tr3_port_type_set(unit, i, SOC_ENCAP_HIGIG); 13852 *mode_change = SOC_ENCAP_HIGIG; 13853 } 13854 } 13855 } 13856 RECONFIGURE_PORT_TYPE_INFO(ether); 13857 RECONFIGURE_PORT_TYPE_INFO(st); 13858 RECONFIGURE_PORT_TYPE_INFO(hg); 13859 RECONFIGURE_PORT_TYPE_INFO(xe); 13860 RECONFIGURE_PORT_TYPE_INFO(ge); 13861 } else if (IS_XT_PORT(unit, port)) { 13862 SOC_PBMP_PORT_REMOVE(si->xe.bitmap, port); 13863 SOC_PBMP_PORT_ADD(si->ge.bitmap, port); 13864 si->port_speed_max[port] = 1000; 13865 for (i = port + 1; i < port + 4; i++) { 13866 si->port_speed_max[i] = 1000; 13867 SOC_PBMP_PORT_REMOVE(si->ge.disabled_bitmap, i); 13868 SOC_PBMP_PORT_REMOVE(si->ether.disabled_bitmap, i); 13869 SOC_PBMP_PORT_REMOVE(si->port.disabled_bitmap, i); 13870 SOC_PBMP_PORT_REMOVE(si->all.disabled_bitmap, i); 13871 } 13872 RECONFIGURE_PORT_TYPE_INFO(xe); 13873 RECONFIGURE_PORT_TYPE_INFO(ge); 13874 } else if (IS_XE_PORT(unit, port)) { /* CL block as XE */ 13875 if (si->port_speed_max[port] > 10000) { /* 1x40G -> 4xXFI*/ 13876 if ((SOC_IS_HELIX4(unit) && (((_tr3_port_config_id[unit] == 464 ) || (_tr3_port_config_id[unit] == 410 )) && 13877 (si->port_l2p_mapping[port] == 57 || si->port_l2p_mapping[port] == 61))) || 13878 (!SOC_IS_HELIX4(unit) && ((_tr3_port_config_id[unit] == 112 || _tr3_port_config_id[unit] == 12) && 13879 (si->port_l2p_mapping[port] == 73 || si->port_l2p_mapping[port] == 77)))) { 13880 soc_tr3_flex_port_grp(unit,port,&fgrp); 13881 si->port_speed_max[port] = _tr3_flex_port_inf[unit].def_flex_port_speeds[fgrp][2] * 1000; 13882 phy = si->port_l2p_mapping[port]; 13883 for (j = phy + 1; j < phy + 4; j++) { 13884 i = si->port_p2l_mapping[j]; 13885 if (i < 0) { 13886 continue; 13887 } 13888 if (IS_HG_PORT(unit, i)) { 13889 SOC_PBMP_PORT_REMOVE(si->hg.bitmap, i); 13890 SOC_PBMP_PORT_REMOVE(si->st.bitmap, i); 13891 *mode_change = SOC_ENCAP_IEEE; 13892 } 13893 SOC_PBMP_PORT_ADD(si->ge.disabled_bitmap, i); 13894 SOC_PBMP_PORT_ADD(si->ether.disabled_bitmap, i); 13895 SOC_PBMP_PORT_ADD(si->port.disabled_bitmap, i); 13896 SOC_PBMP_PORT_ADD(si->all.disabled_bitmap, i); 13897 si->port_speed_max[i] = 0; 13898 } 13899 } else { 13900 si->port_speed_max[port] = 11000; 13901 for (i = port + 1; i < port + 4; i++) { 13902 si->port_speed_max[i] = si->port_speed_max[port]; 13903 SOC_PBMP_PORT_ADD(si->xe.bitmap, i); 13904 SOC_PBMP_PORT_ADD(si->ether.bitmap, i); 13905 SOC_PBMP_PORT_REMOVE(si->xe.disabled_bitmap, i); 13906 SOC_PBMP_PORT_REMOVE(si->ether.disabled_bitmap, i); 13907 SOC_PBMP_PORT_REMOVE(si->port.disabled_bitmap, i); 13908 SOC_PBMP_PORT_REMOVE(si->all.disabled_bitmap, i); 13909 if (IS_HG_PORT(unit, i)) { 13910 SOC_PBMP_PORT_REMOVE(si->hg.bitmap, i); 13911 SOC_PBMP_PORT_REMOVE(si->st.bitmap, i); 13912 _soc_tr3_port_type_set(unit, i, SOC_ENCAP_IEEE); 13913 *mode_change = SOC_ENCAP_IEEE; 13914 } 13915 if (IS_GE_PORT(unit, i)) { 13916 SOC_PBMP_PORT_REMOVE(si->ge.bitmap, i); 13917 } 13918 } 13919 } 13920 RECONFIGURE_PORT_TYPE_INFO(st); 13921 RECONFIGURE_PORT_TYPE_INFO(hg); 13922 RECONFIGURE_PORT_TYPE_INFO(ether); 13923 RECONFIGURE_PORT_TYPE_INFO(xe); 13924 } else if (si->port_speed_max[port+1] == 0) { 13925 /* XAUI -> 4x1G */ 13926 SOC_PBMP_PORT_REMOVE(si->xe.bitmap, port); 13927 SOC_PBMP_PORT_ADD(si->ge.bitmap, port); 13928 si->port_speed_max[port] = 1000; 13929 for (i = port + 1; i < port + 4; i++) { 13930 si->port_speed_max[i] = 1000; 13931 SOC_PBMP_PORT_REMOVE(si->ge.disabled_bitmap, i); 13932 SOC_PBMP_PORT_REMOVE(si->ether.disabled_bitmap, i); 13933 SOC_PBMP_PORT_REMOVE(si->port.disabled_bitmap, i); 13934 SOC_PBMP_PORT_REMOVE(si->all.disabled_bitmap, i); 13935 } 13936 RECONFIGURE_PORT_TYPE_INFO(ether); 13937 RECONFIGURE_PORT_TYPE_INFO(xe); 13938 RECONFIGURE_PORT_TYPE_INFO(ge); 13939 } else { 13940 LOG_ERROR(BSL_LS_SOC_COMMON, 13941 (BSL_META_U(unit, 13942 "Invalid port config for hotswap !!\n"))); 13943 SOC_CONTROL_UNLOCK(unit); 13944 return SOC_E_PARAM; 13945 } 13946 } else { 13947 LOG_ERROR(BSL_LS_SOC_COMMON, 13948 (BSL_META_U(unit, 13949 "Invalid port config for hotswap !!\n"))); 13950 SOC_CONTROL_UNLOCK(unit); 13951 return SOC_E_PARAM; 13952 } 13953 } else if (old_value == 4 && lanes == 2) { /* HG[42] -> 2xHGd[21] */ 13954 if (IS_HG_PORT(unit, port)) { 13955 /* Validate new HG count */ 13956 PBMP_HG_ITER(unit, hp) { 13957 if (!SOC_PBMP_MEMBER(SOC_PORT_DISABLED_BITMAP(unit, port), hp)) { 13958 hgc++; 13959 } 13960 } 13961 if (hgc+1 > _SOC_TR3_MAX_HG_PORT_COUNT) { 13962 LOG_ERROR(BSL_LS_SOC_COMMON, 13963 (BSL_META_U(unit, 13964 "Port config error (Higig port count[%d] exceeded) !!\n"), 13965 hgc)); 13966 return SOC_E_PARAM; 13967 } 13968 si->port_speed_max[port] = 21000; 13969 si->port_speed_max[port+2] = si->port_speed_max[port]; 13970 if (IS_XE_PORT(unit, port+2)) { 13971 SOC_PBMP_PORT_REMOVE(si->xe.bitmap, port+2); 13972 SOC_PBMP_PORT_REMOVE(si->ether.bitmap, port+2); 13973 _soc_tr3_port_type_set(unit, port+2, SOC_ENCAP_HIGIG); 13974 *mode_change = SOC_ENCAP_HIGIG; 13975 } else if (IS_GE_PORT(unit, port+2)) { 13976 SOC_PBMP_PORT_REMOVE(si->ge.bitmap, port+2); 13977 SOC_PBMP_PORT_REMOVE(si->ether.bitmap, port+2); 13978 _soc_tr3_port_type_set(unit, port+2, SOC_ENCAP_HIGIG); 13979 *mode_change = SOC_ENCAP_HIGIG; 13980 } 13981 SOC_PBMP_PORT_ADD(si->hg.bitmap, port+2); 13982 SOC_PBMP_PORT_ADD(si->st.bitmap, port+2); 13983 SOC_PBMP_PORT_REMOVE(si->st.disabled_bitmap, port+2); 13984 SOC_PBMP_PORT_REMOVE(si->hg.disabled_bitmap, port+2); 13985 SOC_PBMP_PORT_REMOVE(si->port.disabled_bitmap, port+2); 13986 SOC_PBMP_PORT_REMOVE(si->all.disabled_bitmap, port+2); 13987 if (IS_XE_PORT(unit, port+2)) { 13988 RECONFIGURE_PORT_TYPE_INFO(ether); 13989 RECONFIGURE_PORT_TYPE_INFO(xe); 13990 } else if (IS_GE_PORT(unit, port+2)) { 13991 RECONFIGURE_PORT_TYPE_INFO(ether); 13992 RECONFIGURE_PORT_TYPE_INFO(ge); 13993 } 13994 RECONFIGURE_PORT_TYPE_INFO(st); 13995 RECONFIGURE_PORT_TYPE_INFO(hg); 13996 } else { /* 40GE -> 2xRXAUI */ 13997 si->port_speed_max[port] = 10000; 13998 si->port_speed_max[port+2] = si->port_speed_max[port]; 13999 if (IS_HG_PORT(unit, port+2)) { 14000 SOC_PBMP_PORT_REMOVE(si->hg.bitmap, port+2); 14001 SOC_PBMP_PORT_REMOVE(si->st.bitmap, port+2); 14002 _soc_tr3_port_type_set(unit, port+2, SOC_ENCAP_IEEE); 14003 *mode_change = SOC_ENCAP_IEEE; 14004 } 14005 SOC_PBMP_PORT_ADD(si->xe.bitmap, port+2); 14006 SOC_PBMP_PORT_ADD(si->ether.bitmap, port+2); 14007 SOC_PBMP_PORT_REMOVE(si->xe.disabled_bitmap, port+2); 14008 SOC_PBMP_PORT_REMOVE(si->ether.disabled_bitmap, port+2); 14009 SOC_PBMP_PORT_REMOVE(si->port.disabled_bitmap, port+2); 14010 SOC_PBMP_PORT_REMOVE(si->all.disabled_bitmap, port+2); 14011 RECONFIGURE_PORT_TYPE_INFO(hg); 14012 RECONFIGURE_PORT_TYPE_INFO(xe); 14013 } 14014 } 14015 #undef RECONFIGURE_PORT_TYPE_INFO 14016 soc_dport_map_update(unit); 14017 SOC_CONTROL_UNLOCK(unit); 14018 /* 14019 * NOTE: using 'old_value' for new port count loops and 14020 * 'lanes' for old port count loops. 14021 */ 14022 14023 /* reset port h/w (assume port en=f by now, pkts drained and link is down in 14024 EPC_LINK_BMAP) */ 14025 #ifdef BCM_WARM_BOOT_SUPPORT 14026 if (SOC_WARM_BOOT(unit)) { 14027 /* update tdm s/w array */ 14028 (void)_soc_tr3_tdm_update(unit, port, lanes, FALSE); 14029 goto _skip_flex_hw_reconfig; 14030 } 14031 #endif /* BCM_WARM_BOOT_SUPPORT */ 14032 SOC_IF_ERROR_RETURN(_soc_tr3_port_control(unit, port, pbt, FALSE)); 14033 14034 switch (old_value) { 14035 case 1: 14036 if ((SOC_IS_HELIX4(unit) && ((_tr3_port_config_id[unit] == 410) && 14037 (si->port_l2p_mapping[port] == 57 || si->port_l2p_mapping[port] == 61))) || 14038 (!SOC_IS_HELIX4(unit) && ((_tr3_port_config_id[unit] == 112 || 14039 _tr3_port_config_id[unit] == 12) && 14040 (si->port_l2p_mapping[port] == 73 || si->port_l2p_mapping[port] == 77)))) { 14041 count = 1; 14042 } 14043 #ifdef BCM_HELIX4_SUPPORT 14044 else if(SOC_IS_HELIX4(unit) && ((_tr3_port_config_id[unit] == 463) || 14045 (_tr3_port_config_id[unit] == 413))&& (si->port_l2p_mapping[port] == 57 || 14046 si->port_l2p_mapping[port] == 61)){ 14047 count = 2; 14048 } 14049 #endif 14050 else { 14051 count = 4; 14052 } 14053 break; 14054 case 2: 14055 #ifdef BCM_HELIX4_SUPPORT 14056 if(SOC_IS_HELIX4(unit) && (((_tr3_port_config_id[unit] == 463)||(_tr3_port_config_id[unit] == 413)) && 14057 (si->port_l2p_mapping[port] == 57 || si->port_l2p_mapping[port] == 61))){ 14058 count = 1; 14059 }else 14060 #endif 14061 { 14062 count = 2; 14063 } 14064 break; 14065 case 4: count = 1; break; 14066 default: break; 14067 } 14068 /* Disable egress cell request generation */ 14069 sal_memset(&egr_en, 0, sizeof(egr_enable_entry_t)); 14070 for (i = 0; i < count; i++) { 14071 if ((!SOC_IS_HELIX4(unit) && ((_tr3_port_config_id[unit] == 112 || _tr3_port_config_id[unit] == 12) && 14072 (si->port_l2p_mapping[port] == 73 || si->port_l2p_mapping[port] == 77))) || 14073 (SOC_IS_HELIX4(unit) && (((_tr3_port_config_id[unit] == 464) || (_tr3_port_config_id[unit] == 410))&& 14074 (si->port_l2p_mapping[port] == 57 || si->port_l2p_mapping[port] == 61)))) { 14075 phy = si->port_l2p_mapping[port] + i; 14076 } else { 14077 phy = si->port_l2p_mapping[port + i]; 14078 } 14079 SOC_IF_ERROR_RETURN 14080 (WRITE_EGR_ENABLEm(unit, SOC_BLOCK_ANY, phy, 14081 &egr_en)); 14082 } 14083 /* reset egress buffers */ 14084 SOC_IF_ERROR_RETURN(_soc_tr3_egress_buffer_reset(unit, port, pbt, TRUE)); 14085 /* do port reset */ 14086 SOC_IF_ERROR_RETURN(_soc_tr3_port_soft_reset(unit, port, pbt, TRUE)); 14087 /* disable old subports */ 14088 SOC_IF_ERROR_RETURN(_soc_tr3_subport_disable(unit, port, pbt, count, TRUE)); 14089 /* clear ports mmu link list credit */ 14090 for (i = 0; i < 4; i++) { 14091 if ((!SOC_IS_HELIX4(unit) && ((_tr3_port_config_id[unit] == 112 || _tr3_port_config_id[unit] == 12) && 14092 (si->port_l2p_mapping[port] == 73 || si->port_l2p_mapping[port] == 77))) || 14093 (SOC_IS_HELIX4(unit) && (((_tr3_port_config_id[unit] == 464) || (_tr3_port_config_id[unit] == 410) || 14094 (_tr3_port_config_id[unit] == 463) || (_tr3_port_config_id[unit] == 413))&& 14095 (si->port_l2p_mapping[port] == 57 || si->port_l2p_mapping[port] == 61)))) { 14096 phy = si->port_l2p_mapping[port] + i; 14097 } else { 14098 phy = si->port_l2p_mapping[port + i]; 14099 } 14100 if (si->port_p2m_mapping[phy] < 0) { 14101 continue; 14102 } 14103 SOC_IF_ERROR_RETURN 14104 (soc_reg32_set(unit, lls_port_credit_reg[si->port_p2m_mapping[phy]], 14105 REG_PORT_ANY, 0, 0)); 14106 } 14107 14108 /* Done with most of the stuff for the old ports, now work on the new ports */ 14109 /* update port mode */ 14110 SOC_IF_ERROR_RETURN(_soc_tr3_port_mode_set(unit, port, pbt, lanes)); 14111 /*update tdm's*/ 14112 SOC_IF_ERROR_RETURN(_soc_tr3_tdm_update(unit, port, lanes, TRUE)); 14113 SOC_IF_ERROR_RETURN(_soc_tr3_update_mcq_fifo(unit, prev_port_speeds)); 14114 /* port reinit */ 14115 SOC_IF_ERROR_RETURN(_soc_tr3_port_control(unit, port, pbt, TRUE)); 14116 /* Set higig modes */ 14117 PBMP_HG_ITER(unit, it_port) { 14118 SOC_IF_ERROR_RETURN 14119 (soc_reg_field32_modify(unit, PORT_CONFIGr, it_port, HIGIG_MODEf, 1)); 14120 } 14121 /* Clear non-higig mode */ 14122 PBMP_XE_ITER(unit, it_port) { 14123 SOC_IF_ERROR_RETURN 14124 (soc_reg_field32_modify(unit, PORT_CONFIGr, it_port, HIGIG_MODEf, 0)); 14125 } 14126 PBMP_GE_ITER(unit, it_port) { 14127 SOC_IF_ERROR_RETURN 14128 (soc_reg_field32_modify(unit, PORT_CONFIGr, it_port, HIGIG_MODEf, 0)); 14129 } 14130 if(IS_XT_PORT(unit, port)) { 14131 for (i = 0 ; i < 4; i++) { 14132 phy = si->port_l2p_mapping[port]+i; 14133 lport = si->port_p2l_mapping[phy]; 14134 if(lport == -1) { 14135 continue; 14136 } 14137 rval = (si->port_speed_max[port] <= 3000)? 1 : 0; 14138 SOC_IF_ERROR_RETURN (soc_reg_field32_modify(unit, 14139 PORT_EHG_RX_CONTROLr, lport, THROTTLE_RX_FIFOf, rval)); 14140 } 14141 } 14142 14143 /* release port reset */ 14144 SOC_IF_ERROR_RETURN(_soc_tr3_port_soft_reset(unit, port, pbt, FALSE)); 14145 /* release egress buffer reset */ 14146 SOC_IF_ERROR_RETURN(_soc_tr3_egress_buffer_reset(unit, port, pbt, FALSE)); 14147 switch (lanes) { 14148 case 1: 14149 if ((SOC_IS_HELIX4(unit) && ((_tr3_port_config_id[unit] == 410) && 14150 (si->port_l2p_mapping[port] == 57 || si->port_l2p_mapping[port] == 61))) || 14151 (!SOC_IS_HELIX4(unit) && ((_tr3_port_config_id[unit] == 112 || 14152 _tr3_port_config_id[unit] == 12) && 14153 (si->port_l2p_mapping[port] == 73 || si->port_l2p_mapping[port] == 77)))) { 14154 count = 1; 14155 } 14156 #ifdef BCM_HELIX4_SUPPORT 14157 else if(SOC_IS_HELIX4(unit) && (((_tr3_port_config_id[unit] == 463)|| 14158 (_tr3_port_config_id[unit] == 413)) && (si->port_l2p_mapping[port] == 57 || 14159 si->port_l2p_mapping[port] == 61))){ 14160 count = 2; 14161 } 14162 #endif 14163 else { 14164 count = 4; 14165 } 14166 break; 14167 case 2: 14168 #ifdef BCM_HELIX4_SUPPORT 14169 if(SOC_IS_HELIX4(unit) && (((_tr3_port_config_id[unit] == 463)|| 14170 (_tr3_port_config_id[unit] == 413)) && (si->port_l2p_mapping[port] == 57 || 14171 si->port_l2p_mapping[port] == 61))){ 14172 count = 1; 14173 }else 14174 #endif 14175 { 14176 count = 2; 14177 } 14178 break; 14179 default: count = 1; break; /* case 4 */ 14180 } 14181 /* Enable new subports */ 14182 SOC_IF_ERROR_RETURN(_soc_tr3_subport_disable(unit, port, pbt, count, FALSE)); 14183 /* Enable egress cell request generation */ 14184 soc_EGR_ENABLEm_field32_set(unit, &egr_en, PRT_ENABLEf, 1); 14185 14186 #ifdef BCM_WARM_BOOT_SUPPORT 14187 _skip_flex_hw_reconfig: 14188 #endif /* BCM_WARM_BOOT_SUPPORT */ 14189 /* update num lanes, flex p2l maps */ 14190 phy = si->port_l2p_mapping[port]; 14191 SOC_CONTROL_LOCK(unit); 14192 switch (lanes) { 14193 case 1: 14194 if ((SOC_IS_HELIX4(unit) && ((_tr3_port_config_id[unit] == 464) || (_tr3_port_config_id[unit] == 410)|| 14195 (_tr3_port_config_id[unit] == 463) || (_tr3_port_config_id[unit] == 413))&& 14196 (si->port_l2p_mapping[port] == 57 || si->port_l2p_mapping[port] == 61)) || 14197 (!SOC_IS_HELIX4(unit) && ((_tr3_port_config_id[unit] == 112 || _tr3_port_config_id[unit] == 12) && 14198 (si->port_l2p_mapping[port] == 73 || si->port_l2p_mapping[port] == 77)))) { 14199 if (!SOC_WARM_BOOT(unit)) { 14200 for (i = 0; i < count; i++) { 14201 SOC_IF_ERROR_RETURN 14202 (WRITE_EGR_ENABLEm(unit, SOC_BLOCK_ANY, 14203 phy+i, &egr_en)); 14204 } 14205 } 14206 si->port_num_lanes[port] = lanes; 14207 if (si->port_p2l_mapping[phy+1] >= 0) { 14208 si->port_num_lanes[si->port_p2l_mapping[phy+1]] = lanes; 14209 } 14210 if (si->port_p2l_mapping[phy+2] >= 0) { 14211 si->port_num_lanes[si->port_p2l_mapping[phy+2]] = lanes; 14212 } 14213 if (si->port_p2l_mapping[phy+3] >= 0) { 14214 si->port_num_lanes[si->port_p2l_mapping[phy+3]] = lanes; 14215 } 14216 si->flex_port_p2l_mapping[phy+1] = si->port_p2l_mapping[phy+1]; 14217 si->flex_port_p2l_mapping[phy+2] = si->port_p2l_mapping[phy+2]; 14218 si->flex_port_p2l_mapping[phy+3] = si->port_p2l_mapping[phy+3]; 14219 } else { 14220 if (!SOC_WARM_BOOT(unit)) { 14221 for (i = 0; i < count; i++) { 14222 SOC_IF_ERROR_RETURN 14223 (WRITE_EGR_ENABLEm(unit, SOC_BLOCK_ANY, 14224 si->port_l2p_mapping[port + i], &egr_en)); 14225 } 14226 } 14227 si->port_num_lanes[port] = lanes; 14228 si->port_num_lanes[port+1] = lanes; 14229 si->port_num_lanes[port+2] = lanes; 14230 si->port_num_lanes[port+3] = lanes; 14231 si->flex_port_p2l_mapping[phy+1] = port+1; 14232 si->flex_port_p2l_mapping[phy+2] = port+2; 14233 si->flex_port_p2l_mapping[phy+3] = port+3; 14234 } 14235 break; 14236 case 2: 14237 if (!SOC_WARM_BOOT(unit)) { 14238 #ifdef BCM_HELIX4_SUPPORT 14239 if(SOC_IS_HELIX4(unit) && ((_tr3_port_config_id[unit] == 463) || 14240 (_tr3_port_config_id[unit] == 413))&&(si->port_l2p_mapping[port] == 57 || 14241 si->port_l2p_mapping[port] == 61)) 14242 { 14243 SOC_IF_ERROR_RETURN 14244 (WRITE_EGR_ENABLEm(unit, SOC_BLOCK_ANY, si->port_l2p_mapping[port], 14245 &egr_en)); 14246 }else 14247 #endif 14248 { 14249 SOC_IF_ERROR_RETURN 14250 (WRITE_EGR_ENABLEm(unit, SOC_BLOCK_ANY, si->port_l2p_mapping[port], 14251 &egr_en)); 14252 SOC_IF_ERROR_RETURN 14253 (WRITE_EGR_ENABLEm(unit, SOC_BLOCK_ANY, si->port_l2p_mapping[port + 2], 14254 &egr_en)); 14255 } 14256 } 14257 #ifdef BCM_HELIX4_SUPPORT 14258 if(SOC_IS_HELIX4(unit) && ((_tr3_port_config_id[unit] == 463) || 14259 (_tr3_port_config_id[unit] == 413))&& 14260 (si->port_l2p_mapping[port] == 57 || si->port_l2p_mapping[port] == 61)){ 14261 si->port_num_lanes[port] = lanes; 14262 if (si->port_p2l_mapping[phy+1] >= 0) { 14263 si->port_num_lanes[si->port_p2l_mapping[phy+1]] = 0; 14264 } 14265 if (si->port_p2l_mapping[phy+2] >= 0) { 14266 si->port_num_lanes[si->port_p2l_mapping[phy+2]] = lanes; 14267 } 14268 if (si->port_p2l_mapping[phy+3] >= 0) { 14269 si->port_num_lanes[si->port_p2l_mapping[phy+3]] = 0; 14270 } 14271 si->flex_port_p2l_mapping[phy+1] = -1; 14272 si->flex_port_p2l_mapping[phy+2] = -1; 14273 si->flex_port_p2l_mapping[phy+3] = -1; 14274 }else 14275 #endif 14276 { 14277 si->port_num_lanes[port] = lanes; 14278 si->port_num_lanes[port+1] = 0; 14279 si->port_num_lanes[port+2] = lanes; 14280 si->port_num_lanes[port+3] = 0; 14281 si->flex_port_p2l_mapping[phy+1] = -1; 14282 si->flex_port_p2l_mapping[phy+2] = port+2; 14283 si->flex_port_p2l_mapping[phy+3] = -1; 14284 } 14285 break; 14286 default: /* case 4 */ 14287 if ((SOC_IS_HELIX4(unit) && (((_tr3_port_config_id[unit] == 464) || (_tr3_port_config_id[unit] == 410))&& 14288 (si->port_l2p_mapping[port] == 57 || si->port_l2p_mapping[port] == 61))) || 14289 (!SOC_IS_HELIX4(unit) && ((_tr3_port_config_id[unit] == 112 || _tr3_port_config_id[unit] == 12)&& 14290 (si->port_l2p_mapping[port] == 73 || si->port_l2p_mapping[port] == 77)))) { 14291 if (!SOC_WARM_BOOT(unit)) { 14292 SOC_IF_ERROR_RETURN 14293 (WRITE_EGR_ENABLEm(unit, SOC_BLOCK_ANY, si->port_l2p_mapping[port], 14294 &egr_en)); 14295 } 14296 si->port_num_lanes[port] = lanes; 14297 if (si->port_p2l_mapping[phy+1] >= 0) { 14298 si->port_num_lanes[si->port_p2l_mapping[phy+1]] = 0; 14299 } 14300 if (si->port_p2l_mapping[phy+2] >= 0) { 14301 si->port_num_lanes[si->port_p2l_mapping[phy+2]] = 0; 14302 } 14303 if (si->port_p2l_mapping[phy+1] >= 0) { 14304 si->port_num_lanes[si->port_p2l_mapping[phy+3]] = 0; 14305 } 14306 si->flex_port_p2l_mapping[phy+1] = -1; 14307 si->flex_port_p2l_mapping[phy+2] = -1; 14308 si->flex_port_p2l_mapping[phy+3] = -1; 14309 } else { 14310 if (!SOC_WARM_BOOT(unit)) { 14311 SOC_IF_ERROR_RETURN 14312 (WRITE_EGR_ENABLEm(unit, SOC_BLOCK_ANY, si->port_l2p_mapping[port], 14313 &egr_en)); 14314 } 14315 si->port_num_lanes[port] = lanes; 14316 si->port_num_lanes[port+1] = 0; 14317 si->port_num_lanes[port+2] = 0; 14318 si->port_num_lanes[port+3] = 0; 14319 si->flex_port_p2l_mapping[phy+1] = -1; 14320 si->flex_port_p2l_mapping[phy+2] = -1; 14321 si->flex_port_p2l_mapping[phy+3] = -1; 14322 } 14323 break; 14324 } 14325 SOC_CONTROL_UNLOCK(unit); 14326 /* assume port en=t follows and link will be up in EPC_LINK_BMAP */ 14327 14328 return SOC_E_NONE; 14329 } 14330 14331 int 14332 soc_tr3_phy_addr_get(int unit, soc_port_t port, uint16 *int_addr) 14333 { 14334 /* NOTE: this is copied from phyident.c and should be kept in sync */ 14335 static const uint16 _soc_triumph3_int_phy_addr[] = { 14336 0x80, /* Port 0 (cmic) N/A */ 14337 0x81, /* Port 1 (XC0) IntBus=0 Addr=0x01 */ 14338 0x82, /* Port 2 (XC0) IntBus=0 Addr=0x02 */ 14339 0x83, /* Port 3 (XC0) IntBus=0 Addr=0x03 */ 14340 0x84, /* Port 4 (XC0) IntBus=0 Addr=0x04 */ 14341 0x85, /* Port 5 (XC1) IntBus=0 Addr=0x05 */ 14342 0x86, /* Port 6 (XC1) IntBus=0 Addr=0x06 */ 14343 0x87, /* Port 7 (XC1) IntBus=0 Addr=0x07 */ 14344 0x88, /* Port 8 (XC1) IntBus=0 Addr=0x08 */ 14345 0x89, /* Port 9 (XC2) IntBus=0 Addr=0x09 */ 14346 0x8A, /* Port 10 (XC2) IntBus=0 Addr=0x0A */ 14347 0x8B, /* Port 11 (XC2) IntBus=0 Addr=0x0B */ 14348 0x8C, /* Port 12 (XC2) IntBus=0 Addr=0x0C */ 14349 0x8D, /* Port 13 (XC3) IntBus=0 Addr=0x0D */ 14350 0x8E, /* Port 14 (XC3) IntBus=0 Addr=0x0E */ 14351 0x8F, /* Port 15 (XC3) IntBus=0 Addr=0x0F */ 14352 0x90, /* Port 16 (XC3) IntBus=0 Addr=0x10 */ 14353 0x91, /* Port 17 (XC4) IntBus=0 Addr=0x11 */ 14354 0x92, /* Port 18 (XC4) IntBus=0 Addr=0x12 */ 14355 0x93, /* Port 19 (XC4) IntBus=0 Addr=0x13 */ 14356 0x94, /* Port 20 (XC4) IntBus=0 Addr=0x14 */ 14357 0x95, /* Port 21 (XC5) IntBus=0 Addr=0x15 */ 14358 0x96, /* Port 22 (XC5) IntBus=0 Addr=0x16 */ 14359 0x97, /* Port 23 (XC5) IntBus=0 Addr=0x17 */ 14360 0x98, /* Port 24 (XC5) IntBus=0 Addr=0x18 */ 14361 0x99, /* Port 25 (XC6) IntBus=0 Addr=0x19 */ 14362 0x9A, /* Port 26 (XC6) IntBus=0 Addr=0x1A */ 14363 0x9B, /* Port 27 (XC6) IntBus=0 Addr=0x1B */ 14364 0x9C, /* Port 28 (XC6) IntBus=0 Addr=0x1C */ 14365 14366 0xA1, /* Port 29 (XC7) IntBus=1 Addr=0x01 */ 14367 0xA2, /* Port 30 (XC7) IntBus=1 Addr=0x02 */ 14368 0xA3, /* Port 31 (XC7) IntBus=1 Addr=0x03 */ 14369 0xA4, /* Port 32 (XC7) IntBus=1 Addr=0x04 */ 14370 0xA5, /* Port 33 (XC8) IntBus=1 Addr=0x05 */ 14371 0xA6, /* Port 34 (XC8) IntBus=1 Addr=0x06 */ 14372 0xA7, /* Port 35 (XC8) IntBus=1 Addr=0x07 */ 14373 0xA8, /* Port 36 (XC8) IntBus=1 Addr=0x08 */ 14374 0xA9, /* Port 37 (XC9) IntBus=1 Addr=0x09 */ 14375 0, /* Port 38 (---) IntBus=1 Addr=0 */ 14376 0, /* Port 39 (---) IntBus=1 Addr=0 */ 14377 0, /* Port 40 (---) IntBus=1 Addr=0 */ 14378 0xAD, /* Port 41 (XC10) IntBus=1 Addr=0x0D */ 14379 0xAE, /* Port 42 (XC10) IntBus=1 Addr=0x0E */ 14380 0xAF, /* Port 43 (XC10) IntBus=1 Addr=0x0F */ 14381 0xB0, /* Port 44 (XC10) IntBus=1 Addr=0x10 */ 14382 0xB1, /* Port 45 (XC11) IntBus=1 Addr=0x11 */ 14383 0xB2, /* Port 46 (XC11) IntBus=1 Addr=0x12 */ 14384 0xB3, /* Port 47 (XC11) IntBus=1 Addr=0x13 */ 14385 0xB4, /* Port 48 (XC11) IntBus=1 Addr=0x14 */ 14386 0xB5, /* Port 49 (XC12) IntBus=1 Addr=0x15 */ 14387 0xB6, /* Port 50 (XC12) IntBus=1 Addr=0x16 */ 14388 0xB7, /* Port 51 (XC12) IntBus=1 Addr=0x17 */ 14389 0xB8, /* Port 52 (XC12) IntBus=1 Addr=0x18 */ 14390 14391 #ifdef TR3_WCMOD_MULTIPORT_SUPPORT 14392 14393 0xC1, /* Port 53 (WC0) IntBus=2 Addr=0x01 */ 14394 0xC2, /* Port 54 (WC0) IntBus=2 Addr=0x02 */ 14395 0xC3, /* Port 55 (WC0) IntBus=2 Addr=0x03 */ 14396 0xC4, /* Port 56 (WC0) IntBus=2 Addr=0x04 */ 14397 0xC5, /* Port 57 (WC1) IntBus=2 Addr=0x05 */ 14398 0xC6, /* Port 58 (WC1) IntBus=2 Addr=0x06 */ 14399 0xC7, /* Port 59 (WC1) IntBus=2 Addr=0x07 */ 14400 0xC8, /* Port 60 (WC1) IntBus=2 Addr=0x08 */ 14401 0xC9, /* Port 61 (WC2) IntBus=2 Addr=0x09 */ 14402 0xCA, /* Port 62 (WC2) IntBus=2 Addr=0x0A */ 14403 0xCB, /* Port 63 (WC2) IntBus=2 Addr=0x0B */ 14404 0xCC, /* Port 64 (WC2) IntBus=2 Addr=0x0C */ 14405 0xCD, /* Port 65 (WC3) IntBus=2 Addr=0x0D */ 14406 0xCE, /* Port 66 (WC3) IntBus=2 Addr=0x0E */ 14407 0xCF, /* Port 67 (WC3) IntBus=2 Addr=0x0F */ 14408 0xD0, /* Port 68 (WC3) IntBus=2 Addr=0x10 */ 14409 0xD1, /* Port 69 (WC4) IntBus=2 Addr=0x11 */ 14410 0xD2, /* Port 70 (WC4) IntBus=2 Addr=0x12 */ 14411 0xD3, /* Port 71 (WC4) IntBus=2 Addr=0x13 */ 14412 0xD4, /* Port 72 (WC4) IntBus=2 Addr=0x14 */ 14413 0xD5, /* Port 73 (WC5) IntBus=2 Addr=0x15 */ 14414 0xD6, /* Port 74 (WC5) IntBus=2 Addr=0x16 */ 14415 0xD7, /* Port 75 (WC5) IntBus=2 Addr=0x17 */ 14416 0xD8, /* Port 76 (WC5) IntBus=2 Addr=0x18 */ 14417 0xD9, /* Port 77 (WC6) IntBus=2 Addr=0x19 */ 14418 0xDA, /* Port 78 (WC6) IntBus=2 Addr=0x1A */ 14419 0xDB, /* Port 79 (WC6) IntBus=2 Addr=0x1B */ 14420 0xDC, /* Port 80 (WC6) IntBus=2 Addr=0x1C */ 14421 #else 14422 0xC1, /* Port 53 (WC0) IntBus=2 Addr=0x01 */ 14423 0xC1, /* Port 54 (WC0) IntBus=2 Addr=0x02 */ 14424 0xC1, /* Port 55 (WC0) IntBus=2 Addr=0x03 */ 14425 0xC1, /* Port 56 (WC0) IntBus=2 Addr=0x04 */ 14426 0xC5, /* Port 57 (WC1) IntBus=2 Addr=0x05 */ 14427 0xC5, /* Port 58 (WC1) IntBus=2 Addr=0x06 */ 14428 0xC5, /* Port 59 (WC1) IntBus=2 Addr=0x07 */ 14429 0xC5, /* Port 60 (WC1) IntBus=2 Addr=0x08 */ 14430 0xC9, /* Port 61 (WC2) IntBus=2 Addr=0x09 */ 14431 0xC9, /* Port 62 (WC2) IntBus=2 Addr=0x0A */ 14432 0xC9, /* Port 63 (WC2) IntBus=2 Addr=0x0B */ 14433 0xC9, /* Port 64 (WC2) IntBus=2 Addr=0x0C */ 14434 0xCD, /* Port 65 (WC3) IntBus=2 Addr=0x0D */ 14435 0xCD, /* Port 66 (WC3) IntBus=2 Addr=0x0E */ 14436 0xCD, /* Port 67 (WC3) IntBus=2 Addr=0x0F */ 14437 0xCD, /* Port 68 (WC3) IntBus=2 Addr=0x10 */ 14438 0xD1, /* Port 69 (WC4) IntBus=2 Addr=0x11 */ 14439 0xD1, /* Port 70 (WC4) IntBus=2 Addr=0x12 */ 14440 0xD1, /* Port 71 (WC4) IntBus=2 Addr=0x13 */ 14441 0xD1, /* Port 72 (WC4) IntBus=2 Addr=0x14 */ 14442 0xD5, /* Port 73 (WC5) IntBus=2 Addr=0x15 */ 14443 0xD5, /* Port 74 (WC5) IntBus=2 Addr=0x16 */ 14444 0xD5, /* Port 75 (WC5) IntBus=2 Addr=0x17 */ 14445 0xD5, /* Port 76 (WC5) IntBus=2 Addr=0x18 */ 14446 0xD9, /* Port 77 (WC6) IntBus=2 Addr=0x19 */ 14447 0xD9, /* Port 78 (WC6) IntBus=2 Addr=0x1A */ 14448 0xD9, /* Port 79 (WC6) IntBus=2 Addr=0x1B */ 14449 0xD9, /* Port 80 (WC6) IntBus=2 Addr=0x1C */ 14450 #endif /* TR3_WCMOD_MULTIPORT_SUPPORT */ 14451 }; 14452 *int_addr = _soc_triumph3_int_phy_addr[SOC_INFO(unit).port_l2p_mapping[port]]; 14453 return SOC_E_NONE; 14454 } 14455 14456 #define _TR3_MMU_BYTES_TO_CELLS(_byte_) \ 14457 (((_byte_) + _TR3_MMU_BYTES_PER_CELL - 1) / _TR3_MMU_BYTES_PER_CELL) 14458 14459 STATIC void 14460 _soc_tr3_mmu_init_dev_config(int unit, _soc_mmu_device_info_t *devcfg) 14461 { 14462 sal_memset(devcfg, 0, sizeof(_soc_mmu_device_info_t)); 14463 14464 devcfg->max_pkt_byte = _TR3_MMU_MAX_PACKET_BYTES; 14465 devcfg->mmu_hdr_byte = _TR3_MMU_PACKET_HEADER_BYTES; 14466 devcfg->jumbo_pkt_size = _TR3_MMU_JUMBO_FRAME_BYTES; 14467 devcfg->default_mtu_size = _TR3_MMU_DEFAULT_MTU_BYTES; 14468 devcfg->mmu_cell_size = _TR3_MMU_BYTES_PER_CELL; 14469 devcfg->mmu_total_cell = _TR3_MMU_TOTAL_CELLS(unit) - _TR3_MMU_CELLS_RSVD_IP; /* cells for IP */ 14470 devcfg->num_pg = _TR3_MMU_NUM_PG; 14471 devcfg->num_service_pool = _TR3_MMU_NUM_POOL; 14472 } 14473 14474 STATIC int 14475 _soc_tr3_default_pg_headroom(int unit, soc_port_t port, int lossless) 14476 { 14477 int speed = 1000, hdrm = 0; 14478 14479 if ((!lossless)) { 14480 return 0; 14481 } 14482 14483 if((IS_AXP_PORT(unit, port))) { 14484 return 118; 14485 } 14486 speed = SOC_INFO(unit).port_speed_max[port]; 14487 14488 if ((speed >= 1000) && (speed < 10000)) { 14489 hdrm = 118; 14490 } else if ((speed >= 10000) && (speed < 20000)) { 14491 hdrm = 198; 14492 } else if ((speed >= 20000) && (speed <= 42000)) { 14493 hdrm = 300; 14494 } else if (speed >= 100000) { 14495 hdrm = 768; 14496 } else { 14497 hdrm = 118; 14498 } 14499 return hdrm; 14500 } 14501 14502 STATIC void 14503 _soc_tr3_mmu_config_buf_default(int unit, _soc_mmu_cfg_buf_t *buf) 14504 { 14505 soc_info_t *si; 14506 _soc_mmu_cfg_buf_pool_t *buf_pool; 14507 _soc_mmu_cfg_buf_port_t *buf_port; 14508 _soc_mmu_cfg_buf_port_pool_t *buf_port_pool; 14509 _soc_mmu_cfg_buf_prigroup_t *buf_prigroup; 14510 _soc_mmu_cfg_buf_queue_t *buf_queue; 14511 int max_packet_cells, jumbo_frame_cells, default_mtu_cells; 14512 int port, idx, per_q_guarentee; 14513 int total_pool_size = 0, egr_shared_total = 0, lossless = 1; 14514 int q_reserved = 0, numq, tmp, in_reserved = 0; 14515 _soc_mmu_cfg_buf_qgroup_t *queue_grp; 14516 14517 si = &SOC_INFO(unit); 14518 14519 LOG_VERBOSE(BSL_LS_SOC_COMMON, 14520 (BSL_META_U(unit, 14521 "Initializing default MMU config (u=%d)\n"), unit)); 14522 max_packet_cells = _MMU_CFG_MMU_BYTES_TO_CELLS(_TR3_MMU_MAX_PACKET_BYTES + 14523 _TR3_MMU_PACKET_HEADER_BYTES, 14524 _TR3_MMU_BYTES_PER_CELL); 14525 jumbo_frame_cells = _MMU_CFG_MMU_BYTES_TO_CELLS(_TR3_MMU_JUMBO_FRAME_BYTES + 14526 _TR3_MMU_PACKET_HEADER_BYTES, 14527 _TR3_MMU_BYTES_PER_CELL); 14528 default_mtu_cells = _MMU_CFG_MMU_BYTES_TO_CELLS(_TR3_MMU_DEFAULT_MTU_BYTES + 14529 _TR3_MMU_PACKET_HEADER_BYTES, 14530 _TR3_MMU_BYTES_PER_CELL); 14531 14532 total_pool_size = _TR3_MMU_TOTAL_CELLS(unit) - _TR3_MMU_CELLS_RSVD_IP; 14533 14534 lossless = soc_property_get(unit, spn_MMU_LOSSLESS, 1); 14535 14536 buf->headroom = 2 * jumbo_frame_cells; 14537 14538 in_reserved += buf->headroom; 14539 14540 per_q_guarentee = (lossless) ? 0 : default_mtu_cells; 14541 PBMP_ALL_ITER(unit, port) { 14542 numq = 0; 14543 soc_tr3_get_def_qbase(unit, port, _SOC_TR3_INDEX_STYLE_UCAST_QUEUE, 14544 NULL, &tmp); 14545 numq += tmp; 14546 soc_tr3_get_def_qbase(unit, port, _SOC_TR3_INDEX_STYLE_MCAST_QUEUE, 14547 NULL, &tmp); 14548 numq += tmp; 14549 q_reserved += per_q_guarentee * numq; 14550 } 14551 14552 egr_shared_total = total_pool_size - q_reserved; 14553 14554 for (idx = 0; idx < _TR3_MMU_NUM_POOL; idx++) { 14555 buf_pool = &buf->pools[idx]; 14556 14557 if (idx == 0) { /* 100% scale up by 100 */ 14558 buf_pool->size = 10000 | _MMU_CFG_BUF_PERCENT_FLAG; 14559 buf_pool->yellow_size = 10000 | _MMU_CFG_BUF_PERCENT_FLAG; 14560 buf_pool->red_size = 10000 | _MMU_CFG_BUF_PERCENT_FLAG; 14561 } else { 14562 buf_pool->size = 0; 14563 buf_pool->yellow_size = 0; 14564 buf_pool->red_size = 0; 14565 } 14566 } 14567 14568 for (idx = 0; idx < SOC_MMU_CFG_QGROUP_MAX; idx++) { 14569 queue_grp = &buf->qgroups[idx]; 14570 queue_grp->guarantee = 0; 14571 queue_grp->pool_limit = total_pool_size; 14572 queue_grp->pool_resume = default_mtu_cells * 2; 14573 queue_grp->yellow_resume = default_mtu_cells * 2; 14574 queue_grp->red_resume = default_mtu_cells * 2; 14575 if (lossless) { 14576 queue_grp->pool_scale = -1; 14577 queue_grp->discard_enable = 0 ; 14578 queue_grp->red_limit = total_pool_size ; 14579 queue_grp->yellow_limit = total_pool_size ; 14580 } else { 14581 queue_grp->pool_scale = 7; 14582 queue_grp->discard_enable = 1; 14583 queue_grp->red_limit = 7 | _MMU_CFG_BUF_DYNAMIC_FLAG; 14584 queue_grp->yellow_limit = 7 | _MMU_CFG_BUF_DYNAMIC_FLAG; 14585 } 14586 } 14587 14588 PBMP_ALL_ITER(unit, port) { 14589 buf_port = &buf->ports[port]; 14590 14591 /* internal priority to priority group mapping */ 14592 for (idx = 0; idx < 16; idx++) { 14593 buf_port->pri_to_prigroup[idx] = 7; 14594 } 14595 14596 /* priority group to pool mapping */ 14597 for (idx = 0; idx < _TR3_MMU_NUM_PG; idx++) { 14598 buf_port->prigroups[idx].pool_idx = 0; 14599 } 14600 14601 for (idx = 0; idx < _TR3_MMU_NUM_POOL; idx++) { 14602 buf_port_pool = &buf_port->pools[idx]; 14603 buf_port_pool->guarantee = 0; 14604 buf_port_pool->pool_limit = 0; 14605 buf_port_pool->pool_resume = 0; 14606 if (idx == 0) { 14607 buf_port_pool->pool_limit = total_pool_size; 14608 buf_port_pool->pool_resume = 14609 total_pool_size - (default_mtu_cells * 2); 14610 } 14611 in_reserved += buf_port_pool->guarantee; 14612 } 14613 14614 buf_port->pkt_size = max_packet_cells; 14615 14616 /* priority group */ 14617 for (idx = 0; idx < _TR3_MMU_NUM_PG; idx++) { 14618 buf_prigroup = &buf_port->prigroups[idx]; 14619 buf_prigroup->guarantee = 1; 14620 buf_prigroup->user_delay = -1; 14621 buf_prigroup->switch_delay = -1; 14622 buf_prigroup->pkt_size = max_packet_cells; 14623 buf_prigroup->device_headroom_enable = 0; 14624 buf_prigroup->pool_limit = 0; 14625 buf_prigroup->pool_floor = 0; 14626 buf_prigroup->pool_scale = -1; 14627 buf_prigroup->headroom = 0; 14628 buf_prigroup->pool_resume = 0; 14629 buf_prigroup->flow_control_enable = 0; 14630 if (idx == 7) { 14631 buf_prigroup->device_headroom_enable = 1; 14632 buf_prigroup->guarantee = jumbo_frame_cells; 14633 buf_prigroup->flow_control_enable = lossless; 14634 if (lossless) { 14635 buf_prigroup->headroom = 14636 _soc_tr3_default_pg_headroom(unit, port, lossless); 14637 buf_prigroup->pool_scale = 7; 14638 buf_prigroup->pool_resume = 16; 14639 } 14640 } 14641 14642 in_reserved += buf_prigroup->guarantee + buf_prigroup->headroom; 14643 } 14644 14645 /* multicast queue */ 14646 for (idx = 0; idx < si->port_num_cosq[port]; idx++) { 14647 buf_queue = &buf_port->queues[idx]; 14648 buf_queue->qgroup_id = -1; 14649 if (lossless) { 14650 buf_queue->guarantee = 0; 14651 buf_queue->discard_enable = 0; 14652 buf_queue->pool_scale = -1; 14653 buf_queue->pool_limit = egr_shared_total; 14654 buf_queue->red_limit = egr_shared_total; 14655 buf_queue->color_discard_enable = 0; 14656 buf_queue->pool_resume = 16; 14657 } else { 14658 buf_queue->guarantee = default_mtu_cells; 14659 buf_queue->discard_enable = 1; 14660 buf_queue->pool_scale = 7; 14661 buf_queue->pool_limit = 0; 14662 buf_queue->red_limit = 7 | _MMU_CFG_BUF_DYNAMIC_FLAG; 14663 buf_queue->color_discard_enable = 0; 14664 buf_queue->pool_resume = 16; 14665 } 14666 } 14667 14668 /* unicast queue */ 14669 for (idx = 0; idx < si->port_num_uc_cosq[port]; idx++) { 14670 buf_queue = &buf_port->queues[si->port_num_cosq[port] + idx]; 14671 buf_queue->qgroup_id = -1; 14672 if (lossless) { 14673 buf_queue->guarantee = 0; 14674 buf_queue->discard_enable = 0; 14675 buf_queue->pool_scale = -1; 14676 buf_queue->pool_limit = egr_shared_total; 14677 buf_queue->red_limit = egr_shared_total; 14678 buf_queue->yellow_limit = egr_shared_total; 14679 buf_queue->color_discard_enable = 0; 14680 buf_queue->pool_resume = default_mtu_cells * 2; 14681 buf_queue->yellow_resume = default_mtu_cells * 2; 14682 buf_queue->red_resume = default_mtu_cells * 2; 14683 } else { 14684 buf_queue->guarantee = default_mtu_cells; 14685 buf_queue->discard_enable = 1; 14686 buf_queue->pool_scale = 7; 14687 buf_queue->pool_limit = 0; 14688 buf_queue->red_limit = 7 | _MMU_CFG_BUF_DYNAMIC_FLAG; 14689 buf_queue->yellow_limit = 7 | _MMU_CFG_BUF_DYNAMIC_FLAG; 14690 buf_queue->color_discard_enable = 0; 14691 buf_queue->pool_resume = default_mtu_cells * 2; 14692 buf_queue->yellow_resume = default_mtu_cells * 2; 14693 buf_queue->red_resume = default_mtu_cells * 2; 14694 } 14695 } 14696 14697 /* queue to pool mapping */ 14698 for (idx = 0; 14699 idx < si->port_num_cosq[port] + si->port_num_uc_cosq[port]; idx++) { 14700 buf_port->queues[idx].pool_idx = 0; 14701 } 14702 } 14703 14704 /*reserve 2 cells for wireless reassembly.*/ 14705 in_reserved += _TR3_MMU_WL_RESERVE_CELL_NUM; 14706 14707 PBMP_ALL_ITER(unit, port) { 14708 buf_port = &buf->ports[port]; 14709 buf_prigroup = &buf_port->prigroups[7]; 14710 if (!lossless) { 14711 buf_prigroup->pool_limit = total_pool_size - in_reserved; 14712 } 14713 } 14714 14715 /* extended queue profiles */ 14716 for (idx = 0; idx < SOC_MMU_CFG_EQUEUE_MAX; idx++) { 14717 buf_queue = &buf->equeues[idx]; 14718 buf_queue->numq = 0; 14719 buf_queue->guarantee = 0; 14720 buf_queue->pool_limit = 0; 14721 buf_queue->discard_enable = 1; 14722 14723 /* As per SDK-63816, we need to set alpha to 2. Low alpha limits 14724 burst absorbtion. However, with higher alpha value, 14725 fewer congested queues are enough to affect other queues. 14726 */ 14727 buf_queue->pool_scale = 2; 14728 buf_queue->pool_resume = default_mtu_cells * 2; 14729 buf_queue->red_limit = 7 | _MMU_CFG_BUF_DYNAMIC_FLAG; 14730 buf_queue->yellow_limit = 7 | _MMU_CFG_BUF_DYNAMIC_FLAG; 14731 buf_queue->yellow_resume = default_mtu_cells * 2; 14732 buf_queue->red_resume = default_mtu_cells * 2; 14733 } 14734 14735 } 14736 14737 14738 STATIC int 14739 _soc_tr3_mmu_config_buf_set_hw(int unit, _soc_mmu_cfg_buf_t *buf) 14740 { 14741 soc_info_t *si; 14742 _soc_mmu_cfg_buf_pool_t *buf_pool; 14743 _soc_mmu_cfg_buf_port_t *buf_port; 14744 _soc_mmu_cfg_buf_prigroup_t *buf_prigroup; 14745 _soc_mmu_cfg_buf_queue_t *buf_queue; 14746 _soc_mmu_cfg_buf_port_pool_t *buf_port_pool; 14747 soc_reg_t reg = INVALIDr; 14748 uint32 rval, fval; 14749 uint32 entry0[SOC_MAX_MEM_WORDS], entry1[SOC_MAX_MEM_WORDS]; 14750 thdi_port_pg_config_entry_t pg_config_mem; 14751 thdi_port_sp_config_entry_t thdi_sp_config; 14752 mmu_thdo_config_qgroup_entry_t cfg_qgrp; 14753 mmu_thdo_offset_qgroup_entry_t offset_qgrp; 14754 int default_mtu_cells, limit, midx, pri, pool; 14755 int port, phy_port, mmu_port, base = 0, numq = 0, idx; 14756 int jumbo_frame_cells; 14757 _soc_mmu_cfg_buf_qgroup_t *queue_grp; 14758 static const soc_field_t prigroup_reg[] = { 14759 PORT_PRI_GRP0r, PORT_PRI_GRP1r 14760 }; 14761 static const soc_field_t prigroup_field[] = { 14762 PRI0_GRPf, PRI1_GRPf, PRI2_GRPf, PRI3_GRPf, 14763 PRI4_GRPf, PRI5_GRPf, PRI6_GRPf, PRI7_GRPf, 14764 PRI8_GRPf, PRI9_GRPf, PRI10_GRPf, PRI11_GRPf, 14765 PRI12_GRPf, PRI13_GRPf, PRI14_GRPf, PRI15_GRPf 14766 }; 14767 static const soc_field_t prigroup_spid_field[] = { 14768 PG0_SPIDf, PG1_SPIDf, PG2_SPIDf, PG3_SPIDf, 14769 PG4_SPIDf, PG5_SPIDf, PG6_SPIDf, PG7_SPIDf 14770 }; 14771 uint16 dev_id; 14772 uint8 rev_id; 14773 14774 si = &SOC_INFO(unit); 14775 soc_cm_get_id(unit, &dev_id, &rev_id); 14776 14777 default_mtu_cells = _MMU_CFG_MMU_BYTES_TO_CELLS(_TR3_MMU_DEFAULT_MTU_BYTES + 14778 _TR3_MMU_PACKET_HEADER_BYTES, 14779 _TR3_MMU_BYTES_PER_CELL); 14780 14781 jumbo_frame_cells = _MMU_CFG_MMU_BYTES_TO_CELLS(_TR3_MMU_JUMBO_FRAME_BYTES + 14782 _TR3_MMU_PACKET_HEADER_BYTES, 14783 _TR3_MMU_BYTES_PER_CELL); 14784 14785 if (dev_id == BCM56543_DEVICE_ID) { 14786 SOC_IF_ERROR_RETURN( WRITE_CFAPCONFIGr( unit, 0x4ec5)); 14787 } 14788 rval = 0; 14789 fval = _TR3_MMU_TOTAL_CELLS(unit) - _TR3_MMU_CELLS_RSVD_IP; 14790 soc_reg_field_set(unit, CFAPFULLTHRESHOLDr, &rval, CFAPFULLSETPOINTf, fval); 14791 soc_reg_field_set(unit, CFAPFULLTHRESHOLDr, &rval, CFAPFULLRESETPOINTf, 14792 fval - 2*jumbo_frame_cells); 14793 SOC_IF_ERROR_RETURN(WRITE_CFAPFULLTHRESHOLDr(unit, rval)); 14794 14795 /* internal priority to priority group mapping */ 14796 PBMP_ALL_ITER(unit, port) { 14797 buf_port = &buf->ports[port]; 14798 14799 for (idx = 0; idx < 16; idx++) { 14800 if (idx % 8 == 0) { /* 8 fields per register */ 14801 reg = prigroup_reg[idx / 8]; 14802 rval = 0; 14803 } 14804 soc_reg_field_set(unit, reg, &rval, prigroup_field[idx], 14805 buf_port->pri_to_prigroup[idx]); 14806 if (idx % 8 == 7) { /* 8 fields per register */ 14807 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, reg, port, 0, rval)); 14808 } 14809 } 14810 } 14811 14812 /* Input port device settings */ 14813 rval = 0; 14814 soc_reg_field_set(unit, GLOBAL_HDRM_LIMITr, &rval, GLOBAL_HDRM_LIMITf, 14815 buf->headroom); 14816 SOC_IF_ERROR_RETURN(WRITE_GLOBAL_HDRM_LIMITr(unit, rval)); 14817 14818 fval = 0; 14819 for (idx = 0; idx < _TR3_MMU_NUM_POOL; idx++) { 14820 if ((buf->pools[idx].size & ~_MMU_CFG_BUF_PERCENT_FLAG) != 0) { 14821 fval |= 1 << idx; 14822 } 14823 } 14824 rval = 0; 14825 soc_reg_field_set(unit, USE_SP_SHAREDr, &rval, ENABLEf, fval); 14826 SOC_IF_ERROR_RETURN(WRITE_USE_SP_SHAREDr(unit, rval)); 14827 14828 fval = 0; 14829 for (idx = 0; idx < _TR3_MMU_NUM_POOL; idx++) { 14830 buf_pool = &buf->pools[idx]; 14831 if ((buf_pool->size & ~_MMU_CFG_BUF_PERCENT_FLAG) == 0) { 14832 continue; 14833 } 14834 14835 if (buf_pool->yellow_size & _MMU_CFG_BUF_PERCENT_FLAG) { 14836 if ((buf_pool->yellow_size & ~_MMU_CFG_BUF_PERCENT_FLAG) < 10000) { 14837 fval |= 1 << idx; 14838 } 14839 } else { 14840 if (buf->pools[idx].size != buf->pools[idx].yellow_size) { 14841 fval |= 1 << idx; 14842 } 14843 } 14844 } 14845 rval = 0; 14846 soc_reg_field_set(unit, COLOR_AWAREr, &rval, ENABLEf, fval); 14847 SOC_IF_ERROR_RETURN(WRITE_COLOR_AWAREr(unit, rval)); 14848 14849 /* configure Q-groups */ 14850 for (idx = 0; idx < SOC_MMU_CFG_QGROUP_MAX; idx++) { 14851 queue_grp = &buf->qgroups[idx]; 14852 14853 sal_memset(&cfg_qgrp, 0, sizeof(cfg_qgrp)); 14854 sal_memset(&offset_qgrp, 0, sizeof(offset_qgrp)); 14855 14856 soc_mem_field32_set(unit, MMU_THDO_CONFIG_QGROUPm, &cfg_qgrp, 14857 Q_MIN_LIMIT_CELLf, queue_grp->guarantee); 14858 if (queue_grp->pool_scale != -1) { 14859 soc_mem_field32_set(unit, MMU_THDO_CONFIG_QGROUPm, &cfg_qgrp, 14860 Q_SHARED_ALPHA_CELLf, queue_grp->pool_scale); 14861 soc_mem_field32_set(unit, MMU_THDO_CONFIG_QGROUPm, &cfg_qgrp, 14862 Q_LIMIT_DYNAMIC_CELLf, 1); 14863 } else { 14864 soc_mem_field32_set(unit, MMU_THDO_CONFIG_QGROUPm, &cfg_qgrp, 14865 Q_SHARED_LIMIT_CELLf, queue_grp->pool_limit); 14866 } 14867 14868 if ((queue_grp->red_limit & _MMU_CFG_BUF_DYNAMIC_FLAG) || 14869 (queue_grp->yellow_limit & _MMU_CFG_BUF_DYNAMIC_FLAG)) { 14870 soc_mem_field32_set(unit, MMU_THDO_CONFIG_QGROUPm, &cfg_qgrp, 14871 Q_COLOR_LIMIT_DYNAMIC_CELLf, 1); 14872 } 14873 14874 if (queue_grp->red_limit & _MMU_CFG_BUF_DYNAMIC_FLAG) { 14875 soc_mem_field32_set(unit, MMU_THDO_CONFIG_QGROUPm, &cfg_qgrp, LIMIT_RED_CELLf, 14876 queue_grp->red_limit & ~_MMU_CFG_BUF_DYNAMIC_FLAG); 14877 14878 } else { 14879 soc_mem_field32_set(unit, MMU_THDO_CONFIG_QGROUPm, &cfg_qgrp, 14880 LIMIT_RED_CELLf, queue_grp->red_limit/8); 14881 } 14882 14883 if (queue_grp->yellow_limit & _MMU_CFG_BUF_DYNAMIC_FLAG) { 14884 soc_mem_field32_set(unit, MMU_THDO_CONFIG_QGROUPm, &cfg_qgrp, LIMIT_YELLOW_CELLf, 14885 queue_grp->yellow_limit & ~_MMU_CFG_BUF_DYNAMIC_FLAG); 14886 } else { 14887 soc_mem_field32_set(unit, MMU_THDO_CONFIG_QGROUPm, &cfg_qgrp, 14888 LIMIT_YELLOW_CELLf, queue_grp->yellow_limit/8); 14889 } 14890 14891 if (queue_grp->discard_enable) { 14892 soc_mem_field32_set(unit, MMU_THDO_CONFIG_QGROUPm, &cfg_qgrp, 14893 Q_LIMIT_ENABLE_CELLf, 1); 14894 } 14895 14896 SOC_IF_ERROR_RETURN 14897 (soc_mem_write(unit, MMU_THDO_CONFIG_QGROUPm, MEM_BLOCK_ALL, 14898 idx, &cfg_qgrp)); 14899 14900 soc_mem_field32_set(unit, MMU_THDO_OFFSET_QGROUPm, 14901 &offset_qgrp, RESET_OFFSET_CELLf, queue_grp->pool_resume / 8); 14902 soc_mem_field32_set(unit, MMU_THDO_OFFSET_QGROUPm, 14903 &offset_qgrp, RESET_OFFSET_YELLOW_CELLf, queue_grp->yellow_resume / 8); 14904 soc_mem_field32_set(unit, MMU_THDO_OFFSET_QGROUPm, 14905 &offset_qgrp, RESET_OFFSET_RED_CELLf, queue_grp->red_resume / 8); 14906 14907 SOC_IF_ERROR_RETURN 14908 (soc_mem_write(unit, MMU_THDO_OFFSET_QGROUPm, MEM_BLOCK_ALL, 14909 idx, &offset_qgrp)); 14910 } 14911 14912 /* per service pool settings */ 14913 for (idx = 0; idx < _TR3_MMU_NUM_POOL; idx++) { 14914 buf_pool = &buf->pools[idx]; 14915 if ((buf_pool->size & ~_MMU_CFG_BUF_PERCENT_FLAG) == 0) { 14916 continue; 14917 } 14918 14919 limit = buf_pool->total - (buf_pool->prigroup_headroom + 14920 buf_pool->prigroup_guarantee + 14921 buf->headroom) - 14922 _TR3_MMU_WL_RESERVE_CELL_NUM; 14923 14924 rval = 0; 14925 soc_reg_field_set(unit, BUFFER_CELL_LIMIT_SPr, &rval, LIMITf, limit); 14926 SOC_IF_ERROR_RETURN(WRITE_BUFFER_CELL_LIMIT_SPr(unit, idx, rval)); 14927 14928 rval = 0; 14929 soc_reg_field_set(unit, CELL_RESET_LIMIT_OFFSET_SPr, &rval, OFFSETf, 14930 NUM_PORT(unit) * default_mtu_cells / 2); 14931 SOC_IF_ERROR_RETURN(WRITE_CELL_RESET_LIMIT_OFFSET_SPr(unit, idx, rval)); 14932 14933 if (buf_pool->yellow_size & _MMU_CFG_BUF_PERCENT_FLAG) { 14934 if ((buf_pool->yellow_size & ~_MMU_CFG_BUF_PERCENT_FLAG) == 10000) { 14935 continue; 14936 } 14937 } else { 14938 if (buf_pool->size == buf_pool->yellow_size) { 14939 continue; 14940 } 14941 } 14942 14943 if (buf_pool->yellow_size & _MMU_CFG_BUF_PERCENT_FLAG) { 14944 fval = (buf_pool->yellow_size & ~_MMU_CFG_BUF_PERCENT_FLAG) * limit / 14945 10000; 14946 } else { 14947 fval = buf_pool->yellow_size; 14948 } 14949 rval = 0; 14950 soc_reg_field_set(unit, CELL_SPAP_YELLOW_OFFSET_SPr, &rval, OFFSETf, 14951 limit - fval); 14952 SOC_IF_ERROR_RETURN 14953 (WRITE_CELL_SPAP_YELLOW_OFFSET_SPr(unit, idx, rval)); 14954 14955 if (buf_pool->red_size & _MMU_CFG_BUF_PERCENT_FLAG) { 14956 fval = (buf_pool->red_size & ~_MMU_CFG_BUF_PERCENT_FLAG) * limit / 14957 10000; 14958 } else { 14959 fval = buf_pool->red_size; 14960 } 14961 rval = 0; 14962 soc_reg_field_set(unit, CELL_SPAP_RED_OFFSET_SPr, &rval, OFFSETf, 14963 limit - fval); 14964 SOC_IF_ERROR_RETURN(WRITE_CELL_SPAP_RED_OFFSET_SPr(unit, idx, rval)); 14965 } 14966 14967 /* Input port per port settings */ 14968 PBMP_ALL_ITER(unit, port) { 14969 phy_port = si->port_l2p_mapping[port]; 14970 mmu_port = si->port_p2m_mapping[phy_port]; 14971 buf_port = &buf->ports[port]; 14972 14973 rval = 0; 14974 for (idx = 0; idx < _TR3_MMU_NUM_PG; idx++) { 14975 soc_reg_field_set(unit, PORT_PG_SPIDr, &rval, 14976 prigroup_spid_field[idx], 14977 buf_port->prigroups[idx].pool_idx); 14978 } 14979 SOC_IF_ERROR_RETURN(WRITE_PORT_PG_SPIDr(unit, port, rval)); 14980 14981 /* Per port per pool settings */ 14982 for (idx = 0; idx < _TR3_MMU_NUM_POOL; idx++) { 14983 buf_port_pool = &buf_port->pools[idx]; 14984 midx = (mmu_port * 4) + idx; 14985 sal_memset(&thdi_sp_config, 0, sizeof(thdi_sp_config)); 14986 soc_mem_field32_set(unit, THDI_PORT_SP_CONFIGm, &thdi_sp_config, 14987 PORT_SP_MIN_LIMITf, buf_port_pool->guarantee); 14988 soc_mem_field32_set(unit, THDI_PORT_SP_CONFIGm, &thdi_sp_config, 14989 PORT_SP_RESUME_LIMITf, buf_port_pool->pool_resume); 14990 soc_mem_field32_set(unit, THDI_PORT_SP_CONFIGm, &thdi_sp_config, 14991 PORT_SP_MAX_LIMITf, buf_port_pool->pool_limit); 14992 SOC_IF_ERROR_RETURN 14993 (soc_mem_write(unit, THDI_PORT_SP_CONFIGm, MEM_BLOCK_ALL, 14994 midx, &thdi_sp_config)); 14995 } 14996 14997 fval = 0; 14998 for (idx = 0; idx < _TR3_MMU_NUM_PG; idx++) { 14999 if (buf_port->prigroups[idx].flow_control_enable != 0) { 15000 for (pri=0; pri < 16; pri++) { 15001 if (buf_port->pri_to_prigroup[pri] == idx) { 15002 fval |= 1 << pri; 15003 } 15004 } 15005 } 15006 } 15007 15008 rval = 0; 15009 soc_reg_field_set(unit, PORT_PRI_XON_ENABLEr, &rval, 15010 PORT_PRI_XON_ENABLEf, fval); 15011 SOC_IF_ERROR_RETURN(WRITE_PORT_PRI_XON_ENABLEr(unit, port, rval)); 15012 15013 rval = 0; 15014 soc_reg_field_set(unit, PORT_MAX_PKT_SIZEr, &rval, PORT_MAX_PKT_SIZEf, 15015 buf_port->pkt_size); 15016 SOC_IF_ERROR_RETURN(WRITE_PORT_MAX_PKT_SIZEr(unit, port, rval)); 15017 15018 /* Input port per port per priority group settings */ 15019 for (idx = 0; idx < _TR3_MMU_NUM_PG; idx++) { 15020 buf_prigroup = &buf->ports[port].prigroups[idx]; 15021 15022 midx = (mmu_port * 8) + idx; 15023 sal_memset(&pg_config_mem, 0, sizeof(pg_config_mem)); 15024 soc_mem_field32_set(unit, THDI_PORT_PG_CONFIGm, &pg_config_mem, PG_MIN_LIMITf, 15025 buf_prigroup->guarantee > 1 ? buf_prigroup->guarantee : 1); 15026 15027 if (buf_prigroup->pool_scale != -1) { 15028 soc_mem_field32_set(unit, THDI_PORT_PG_CONFIGm, &pg_config_mem, 15029 PG_SHARED_DYNAMICf, 1); 15030 soc_mem_field32_set(unit, THDI_PORT_PG_CONFIGm, &pg_config_mem, 15031 PG_SHARED_LIMITf, buf_prigroup->pool_scale); 15032 } else { 15033 soc_mem_field32_set(unit, THDI_PORT_PG_CONFIGm, &pg_config_mem, 15034 PG_SHARED_LIMITf, buf_prigroup->pool_limit); 15035 } 15036 15037 soc_mem_field32_set(unit, THDI_PORT_PG_CONFIGm, &pg_config_mem, 15038 PG_GBL_HDRM_ENf, buf_prigroup->device_headroom_enable); 15039 soc_mem_field32_set(unit, THDI_PORT_PG_CONFIGm, &pg_config_mem, 15040 PG_HDRM_LIMITf, buf_prigroup->headroom); 15041 15042 soc_mem_field32_set(unit, THDI_PORT_PG_CONFIGm, &pg_config_mem, 15043 PG_RESET_OFFSETf, buf_prigroup->pool_resume); 15044 15045 soc_mem_field32_set(unit, THDI_PORT_PG_CONFIGm, &pg_config_mem, 15046 PG_RESET_FLOORf, buf_prigroup->pool_floor); 15047 15048 SOC_IF_ERROR_RETURN(soc_mem_write(unit, THDI_PORT_PG_CONFIGm, 15049 MEM_BLOCK_ALL, midx, &pg_config_mem)); 15050 } 15051 } 15052 15053 /*********************************** 15054 * THDO 15055 */ 15056 15057 /* Output port per port per queue setting for multicast queue */ 15058 PBMP_ALL_ITER(unit, port) { 15059 for (idx = 0; idx < si->port_num_cosq[port]; idx++) { 15060 buf_queue = &buf->ports[port].queues[idx]; 15061 pool = buf_queue->pool_idx; 15062 buf_pool = &buf->pools[pool]; 15063 limit = buf_pool->total - buf_pool->queue_guarantee; 15064 if (limit < 0) { 15065 limit = 0; 15066 } 15067 rval = 0; 15068 soc_reg_field_set(unit, OP_QUEUE_CONFIG_CELLr, &rval, Q_MIN_CELLf, 15069 buf_queue->guarantee); 15070 if (buf_queue->pool_scale != -1) { 15071 soc_reg_field_set(unit, OP_QUEUE_CONFIG_CELLr, &rval, 15072 Q_SHARED_ALPHA_CELLf, buf_queue->pool_scale); 15073 } else { 15074 soc_reg_field_set(unit, OP_QUEUE_CONFIG_CELLr, &rval, 15075 Q_SHARED_LIMIT_CELLf, buf_queue->pool_limit); 15076 } 15077 SOC_IF_ERROR_RETURN 15078 (WRITE_OP_QUEUE_CONFIG_CELLr(unit, port, idx, rval)); 15079 15080 rval = 0; 15081 if (buf_queue->discard_enable) { 15082 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_CELLr, &rval, 15083 Q_LIMIT_ENABLE_CELLf, 1); 15084 } 15085 if (buf_queue->pool_scale != -1) { 15086 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_CELLr, &rval, 15087 Q_LIMIT_DYNAMIC_CELLf, 1); 15088 } 15089 if (buf_queue->color_discard_enable) { 15090 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_CELLr, &rval, 15091 Q_COLOR_ENABLE_CELLf, 1); 15092 } 15093 if (buf_queue->red_limit & _MMU_CFG_BUF_DYNAMIC_FLAG) { 15094 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_CELLr, &rval, 15095 Q_COLOR_LIMIT_DYNAMIC_CELLf, 1); 15096 } 15097 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_CELLr, &rval, 15098 Q_SPIDf, buf_queue->pool_idx); 15099 SOC_IF_ERROR_RETURN 15100 (WRITE_OP_QUEUE_CONFIG1_CELLr(unit, port, idx, rval)); 15101 15102 rval = 0; 15103 if (buf_queue->red_limit & _MMU_CFG_BUF_DYNAMIC_FLAG) { 15104 soc_reg_field_set(unit, OP_QUEUE_LIMIT_COLOR_CELLr, &rval, REDf, 15105 (buf_queue->red_limit & ~_MMU_CFG_BUF_DYNAMIC_FLAG)); 15106 } else { 15107 soc_reg_field_set(unit, OP_QUEUE_LIMIT_COLOR_CELLr, &rval, REDf, 15108 buf_queue->red_limit/8); 15109 } 15110 SOC_IF_ERROR_RETURN 15111 (WRITE_OP_QUEUE_LIMIT_COLOR_CELLr(unit, port, idx, rval)); 15112 15113 rval = 0; 15114 soc_reg_field_set(unit, OP_QUEUE_RESET_OFFSET_CELLr, &rval, 15115 Q_RESET_OFFSET_CELLf, 15116 buf_queue->pool_resume / 8); 15117 SOC_IF_ERROR_RETURN 15118 (WRITE_OP_QUEUE_RESET_OFFSET_CELLr(unit, port, idx, rval)); 15119 15120 rval = 0; 15121 soc_reg_field_set(unit, OP_QUEUE_LIMIT_RESUME_COLOR_CELLr, &rval, 15122 RESUME_OPTION_CELLf, _TR3_RESUME_OPTION_CELL); 15123 SOC_IF_ERROR_RETURN 15124 (WRITE_OP_QUEUE_LIMIT_RESUME_COLOR_CELLr(unit, port, idx, rval)); 15125 15126 } 15127 /* For CPU port only 45 queue are configured and queue 45, 46 and 47 are 15128 mapped to L0 nodes.So set discard enable to 1 for these three queues. */ 15129 if (IS_CPU_PORT(unit, port)) { 15130 rval = 0; 15131 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_CELLr, &rval, 15132 Q_LIMIT_ENABLE_CELLf, 1); 15133 for (idx = 45; idx < 48; idx++) { 15134 SOC_IF_ERROR_RETURN 15135 (WRITE_OP_QUEUE_CONFIG1_CELLr(unit, port, idx, rval)); 15136 } 15137 } 15138 } 15139 15140 /*OP_RESUME_OFFSET_COLOR_CELL_PROFILE setting*/ 15141 for (idx = 0; idx < 8; idx++) { 15142 rval = 0; 15143 soc_reg_field_set(unit, OP_RESUME_OFFSET_COLOR_CELL_PROFILEr, &rval, 15144 RESUME_OFFSET_RED_CELLf, _TR3_RESUME_OFFSET_RED_CELL); 15145 SOC_IF_ERROR_RETURN 15146 (WRITE_OP_RESUME_OFFSET_COLOR_CELL_PROFILEr(unit, idx, rval)); 15147 } 15148 15149 /* Output port per port per queue setting for regular unicast queue */ 15150 PBMP_ALL_ITER(unit, port) { 15151 if (IS_CPU_PORT(unit, port)) { 15152 continue; 15153 } 15154 15155 /* per port regular unicast queue */ 15156 soc_tr3_get_def_qbase(unit, port, _SOC_TR3_INDEX_STYLE_UCAST_QUEUE, 15157 &base, &numq); 15158 for (idx = 0; idx < numq; idx++) { 15159 buf_queue = &buf->ports[port].queues[si->port_num_cosq[port] + idx]; 15160 15161 sal_memset(entry0, 0, sizeof(mmu_thdo_config_queue_entry_t)); 15162 sal_memset(entry1, 0, sizeof(mmu_thdo_offset_0_entry_t)); 15163 15164 soc_mem_field32_set(unit, MMU_THDO_CONFIG_QUEUEm, entry0, 15165 Q_MIN_LIMIT_CELLf, buf_queue->guarantee); 15166 if (buf_queue->discard_enable) { 15167 soc_mem_field32_set(unit, MMU_THDO_CONFIG_QUEUEm, entry0, 15168 Q_LIMIT_ENABLE_CELLf, 1); 15169 } 15170 if (buf_queue->pool_scale != -1) { 15171 soc_mem_field32_set(unit, MMU_THDO_CONFIG_QUEUEm, entry0, 15172 Q_LIMIT_DYNAMIC_CELLf, 1); 15173 soc_mem_field32_set(unit, MMU_THDO_CONFIG_QUEUEm, entry0, 15174 Q_SHARED_ALPHA_CELLf, buf_queue->pool_scale); 15175 } else { 15176 /* Q_LIMIT_DYNAMIC_CELLf is 0 */ 15177 soc_mem_field32_set(unit, MMU_THDO_CONFIG_QUEUEm, entry0, 15178 Q_SHARED_LIMIT_CELLf, buf_queue->pool_limit); 15179 } 15180 15181 if (buf_queue->yellow_limit & _MMU_CFG_BUF_DYNAMIC_FLAG) { 15182 soc_mem_field32_set(unit, MMU_THDO_CONFIG_QUEUEm, entry0, 15183 Q_COLOR_LIMIT_DYNAMIC_CELLf, 1); 15184 soc_mem_field32_set 15185 (unit, MMU_THDO_CONFIG_QUEUEm, entry0, LIMIT_YELLOW_CELLf, 15186 buf_queue->yellow_limit & ~_MMU_CFG_BUF_DYNAMIC_FLAG); 15187 soc_mem_field32_set 15188 (unit, MMU_THDO_CONFIG_QUEUEm, entry0, LIMIT_RED_CELLf, 15189 buf_queue->red_limit & ~_MMU_CFG_BUF_DYNAMIC_FLAG); 15190 } else { 15191 /* Q_COLOR_LIMIT_DYNAMIC_CELLf is 0 */ 15192 soc_mem_field32_set 15193 (unit, MMU_THDO_CONFIG_QUEUEm, entry0, LIMIT_YELLOW_CELLf, 15194 buf_queue->yellow_limit / 8); 15195 soc_mem_field32_set 15196 (unit, MMU_THDO_CONFIG_QUEUEm, entry0, LIMIT_RED_CELLf, 15197 buf_queue->red_limit / 8); 15198 } 15199 15200 SOC_IF_ERROR_RETURN 15201 (soc_mem_write(unit, MMU_THDO_CONFIG_QUEUEm, MEM_BLOCK_ALL, 15202 base + idx, entry0)); 15203 15204 soc_mem_field32_set 15205 (unit, MMU_THDO_OFFSET_QUEUEm, entry1, RESET_OFFSET_CELLf, 15206 buf_queue->pool_resume / 8); 15207 15208 soc_mem_field32_set 15209 (unit, MMU_THDO_OFFSET_QUEUEm, entry1, RESET_OFFSET_YELLOW_CELLf, 15210 buf_queue->yellow_resume / 8); 15211 soc_mem_field32_set 15212 (unit, MMU_THDO_OFFSET_QUEUEm, entry1, RESET_OFFSET_RED_CELLf, 15213 buf_queue->red_resume / 8); 15214 15215 SOC_IF_ERROR_RETURN 15216 (soc_mem_write(unit, MMU_THDO_OFFSET_QUEUEm, MEM_BLOCK_ALL, 15217 base + idx, entry1)); 15218 15219 sal_memset(entry0, 0, sizeof(mmu_thdo_q_to_qgrp_map_entry_t)); 15220 soc_mem_field32_set(unit, MMU_THDO_Q_TO_QGRP_MAPm, 15221 entry0, Q_SPIDf, buf_queue->pool_idx); 15222 if (buf_queue->color_discard_enable) { 15223 soc_mem_field32_set(unit, MMU_THDO_Q_TO_QGRP_MAPm, entry0, 15224 Q_COLOR_ENABLE_CELLf, 1); 15225 } 15226 15227 if (buf_queue->qgroup_id != -1) { 15228 soc_mem_field32_set(unit, MMU_THDO_Q_TO_QGRP_MAPm, entry0, 15229 QGROUP_VALIDf, 1); 15230 soc_mem_field32_set(unit, MMU_THDO_Q_TO_QGRP_MAPm, entry0, 15231 QGROUPf, buf_queue->qgroup_id); 15232 if (buf_queue->qgroup_min_enable) { 15233 soc_mem_field32_set(unit, MMU_THDO_Q_TO_QGRP_MAPm, entry0, 15234 USE_QGROUP_MINf, 1); 15235 } 15236 } 15237 15238 SOC_IF_ERROR_RETURN(soc_mem_write(unit, MMU_THDO_Q_TO_QGRP_MAPm, 15239 MEM_BLOCK_ALL, base + idx, entry0)); 15240 } 15241 } 15242 15243 base = base + numq; 15244 15245 /* extended queue profiles.*/ 15246 for (idx = 0; idx < SOC_MMU_CFG_EQUEUE_MAX; idx++) { 15247 if ((base + idx) >= _BCM_TR3_NUM_L2_UC_LEAVES) { 15248 break; 15249 } 15250 buf_queue = &buf->equeues[idx]; 15251 sal_memset(entry0, 0, sizeof(mmu_thdo_config_queue_entry_t)); 15252 soc_mem_field32_set(unit, MMU_THDO_CONFIG_QUEUEm, entry0, 15253 Q_MIN_LIMIT_CELLf, buf_queue->guarantee); 15254 if (buf_queue->discard_enable) { 15255 soc_mem_field32_set(unit, MMU_THDO_CONFIG_QUEUEm, entry0, 15256 Q_LIMIT_ENABLE_CELLf, 1); 15257 } 15258 if (buf_queue->pool_scale != -1) { 15259 soc_mem_field32_set(unit, MMU_THDO_CONFIG_QUEUEm, entry0, 15260 Q_LIMIT_DYNAMIC_CELLf, 1); 15261 soc_mem_field32_set(unit, MMU_THDO_CONFIG_QUEUEm, entry0, 15262 Q_SHARED_ALPHA_CELLf, buf_queue->pool_scale); 15263 } else { 15264 /* Q_LIMIT_DYNAMIC_CELLf is 0 */ 15265 soc_mem_field32_set(unit, MMU_THDO_CONFIG_QUEUEm, entry0, 15266 Q_SHARED_LIMIT_CELLf, buf_queue->pool_limit); 15267 } 15268 SOC_IF_ERROR_RETURN(soc_mem_write(unit, MMU_THDO_CONFIG_QUEUEm, 15269 MEM_BLOCK_ALL, base + idx, entry0)); 15270 } 15271 15272 /* Output port per pool settings */ 15273 for (idx = 0; idx < _TR3_MMU_NUM_POOL; idx++) { 15274 buf_pool = &buf->pools[idx]; 15275 if ((buf_pool->size & ~_MMU_CFG_BUF_PERCENT_FLAG) == 0) { 15276 continue; 15277 } 15278 15279 limit = buf_pool->total - buf_pool->queue_guarantee; 15280 15281 rval = 0; 15282 soc_reg_field_set(unit, OP_BUFFER_SHARED_LIMIT_CELLr, &rval, 15283 OP_BUFFER_SHARED_LIMIT_CELLf, limit); 15284 SOC_IF_ERROR_RETURN 15285 (soc_reg32_set(unit, OP_BUFFER_SHARED_LIMIT_CELLr, REG_PORT_ANY, 15286 idx, rval)); 15287 15288 rval = 0; 15289 soc_reg_field_set(unit, OP_BUFFER_LIMIT_YELLOW_CELLr, &rval, 15290 OP_BUFFER_LIMIT_YELLOW_CELLf, limit / 8); 15291 SOC_IF_ERROR_RETURN 15292 (soc_reg32_set(unit, OP_BUFFER_LIMIT_YELLOW_CELLr, REG_PORT_ANY, 15293 idx, rval)); 15294 15295 rval = 0; 15296 soc_reg_field_set(unit, OP_BUFFER_LIMIT_RED_CELLr, &rval, 15297 OP_BUFFER_LIMIT_RED_CELLf, limit / 8); 15298 SOC_IF_ERROR_RETURN 15299 (soc_reg32_set(unit, OP_BUFFER_LIMIT_RED_CELLr, REG_PORT_ANY, 15300 idx, rval)); 15301 15302 rval = 0; 15303 soc_reg_field_set(unit, OP_BUFFER_SHARED_LIMIT_RESUME_CELLr, &rval, 15304 OP_BUFFER_SHARED_LIMIT_RESUME_CELLf, limit); 15305 SOC_IF_ERROR_RETURN 15306 (soc_reg32_set(unit, OP_BUFFER_SHARED_LIMIT_RESUME_CELLr, 15307 REG_PORT_ANY, idx, rval)); 15308 15309 rval = 0; 15310 soc_reg_field_set(unit, OP_BUFFER_LIMIT_RESUME_YELLOW_CELLr, &rval, 15311 OP_BUFFER_LIMIT_RESUME_YELLOW_CELLf, limit / 8); 15312 SOC_IF_ERROR_RETURN 15313 (soc_reg32_set(unit, OP_BUFFER_LIMIT_RESUME_YELLOW_CELLr, 15314 REG_PORT_ANY, idx, rval)); 15315 15316 rval = 0; 15317 soc_reg_field_set(unit, OP_BUFFER_LIMIT_RESUME_RED_CELLr, &rval, 15318 OP_BUFFER_LIMIT_RESUME_RED_CELLf, limit / 8); 15319 SOC_IF_ERROR_RETURN 15320 (soc_reg32_set(unit, OP_BUFFER_LIMIT_RESUME_RED_CELLr, 15321 REG_PORT_ANY, idx, rval)); 15322 15323 /* Output port per port per pool setting */ 15324 PBMP_PORT_ITER(unit, port) { 15325 phy_port = si->port_l2p_mapping[port]; 15326 mmu_port = si->port_p2m_mapping[phy_port]; 15327 15328 sal_memset(entry0, 0, sizeof(mmu_thdo_config_port_entry_t)); 15329 soc_mem_field32_set(unit, MMU_THDO_CONFIG_PORTm, entry0, 15330 SHARED_LIMITf, limit); 15331 soc_mem_field32_set(unit, MMU_THDO_CONFIG_PORTm, entry0, 15332 SHARED_RESUMEf, limit - (default_mtu_cells * 2)); 15333 15334 soc_mem_field32_set(unit, MMU_THDO_CONFIG_PORTm, entry0, 15335 YELLOW_LIMITf, limit/8); 15336 soc_mem_field32_set(unit, MMU_THDO_CONFIG_PORTm, entry0, 15337 YELLOW_RESUMEf, (limit - (default_mtu_cells*2))/8); 15338 15339 soc_mem_field32_set(unit, MMU_THDO_CONFIG_PORTm, entry0, 15340 RED_LIMITf, limit/8); 15341 soc_mem_field32_set(unit, MMU_THDO_CONFIG_PORTm, entry0, 15342 RED_RESUMEf, (limit - (default_mtu_cells * 2))/8); 15343 15344 SOC_IF_ERROR_RETURN 15345 (WRITE_MMU_THDO_CONFIG_PORTm(unit, MEM_BLOCK_ANY, 15346 (mmu_port*4) + idx, &entry0)); 15347 } 15348 15349 /* Output port per port per pool setting for multicast queues */ 15350 PBMP_PORT_ITER(unit, port) { 15351 rval = 0; 15352 soc_reg_field_set(unit, OP_PORT_CONFIG_CELLr, &rval, 15353 OP_SHARED_LIMIT_CELLf, limit); 15354 soc_reg_field_set(unit, OP_PORT_CONFIG_CELLr, &rval, 15355 OP_SHARED_RESET_VALUE_CELLf, 15356 limit - (2 * default_mtu_cells)); 15357 SOC_IF_ERROR_RETURN 15358 (soc_reg32_set(unit, OP_PORT_CONFIG_CELLr, port, idx, rval)); 15359 15360 rval = 0; 15361 soc_reg_field_set(unit, OP_PORT_LIMIT_COLOR_CELLr, &rval, REDf, 15362 limit / 8); 15363 SOC_IF_ERROR_RETURN 15364 (soc_reg32_set(unit, OP_PORT_LIMIT_COLOR_CELLr, port, idx, 15365 rval)); 15366 15367 rval = 0; 15368 soc_reg_field_set 15369 (unit, OP_PORT_LIMIT_RESUME_COLOR_CELLr, &rval, REDf, 15370 (limit - (2*default_mtu_cells)) / 8); 15371 SOC_IF_ERROR_RETURN 15372 (soc_reg32_set(unit, OP_PORT_LIMIT_RESUME_COLOR_CELLr, port, 15373 idx, rval)); 15374 } 15375 } 15376 15377 /* setup WAMU */ 15378 rval = 0; 15379 soc_reg_field_set(unit, WAMUTOTALSHRLMTINGr, &rval, SHRPKT_LMTf, 0xfff); 15380 soc_reg_field_set(unit, WAMUTOTALSHRLMTINGr, &rval, SHRCELL_LMTf, 0x7fff); 15381 SOC_IF_ERROR_RETURN 15382 (soc_reg32_set(unit, WAMUTOTALSHRLMTINGr, REG_PORT_ANY, 0, rval)); 15383 15384 rval = 0; 15385 soc_reg_field_set(unit, WAMUTOTALSHRLMTPKTEGRr, &rval, SHR_LMTf, 0xfff); 15386 SOC_IF_ERROR_RETURN 15387 (soc_reg32_set(unit, WAMUTOTALSHRLMTPKTEGRr, REG_PORT_ANY, 0, rval)); 15388 15389 rval = 0; 15390 soc_reg_field_set(unit, CNTX_AGING_LIMITr, &rval, AGING_LIMITf, 0x1fff); 15391 SOC_IF_ERROR_RETURN 15392 (soc_reg32_set(unit, CNTX_AGING_LIMITr, REG_PORT_ANY, 0, rval)); 15393 15394 rval = 0; 15395 SOC_IF_ERROR_RETURN 15396 (soc_reg32_set(unit, WAMUTHDBYPASSr, REG_PORT_ANY, 0, rval)); 15397 15398 rval = 0; 15399 soc_reg_field_set(unit, WAMU_PG_MIN_CELLr, &rval, PG_MIN_ENf, 1); 15400 soc_reg_field_set(unit, WAMU_PG_MIN_CELLr, &rval, PG_MINf, 15401 jumbo_frame_cells); 15402 SOC_IF_ERROR_RETURN 15403 (soc_reg32_set(unit, WAMU_PG_MIN_CELLr, REG_PORT_ANY, 0, rval)); 15404 15405 rval = 0; 15406 soc_reg_field_set(unit, WAMU_PG_SHARED_LIMIT_CELLr, &rval, 15407 PG_SHARED_LIMITf, 6); 15408 soc_reg_field_set(unit, WAMU_PG_SHARED_LIMIT_CELLr, &rval, 15409 PG_SHARED_DYNAMICf, 1); 15410 SOC_IF_ERROR_RETURN 15411 (soc_reg32_set(unit, WAMU_PG_SHARED_LIMIT_CELLr, REG_PORT_ANY, 0, rval)); 15412 15413 rval = 0; 15414 soc_reg_field_set(unit, WAMU_PG_RESET_OFFSET_CELLr, &rval, 15415 WAMU_PG_RESET_OFFSETf, 1); 15416 SOC_IF_ERROR_RETURN 15417 (soc_reg32_set(unit, WAMU_PG_RESET_OFFSET_CELLr, REG_PORT_ANY, 0, rval)); 15418 15419 rval = 0; 15420 soc_reg_field_set(unit, WAMUMINLMTPGr, &rval, PKTLMTf, 2); 15421 soc_reg_field_set(unit, WAMUMINLMTPGr, &rval, CELLLMTf, default_mtu_cells); 15422 SOC_IF_ERROR_RETURN 15423 (soc_reg32_set(unit, WAMUMINLMTPGr, REG_PORT_ANY, 0, rval)); 15424 15425 rval = 0; 15426 soc_reg_field_set(unit, WAMUSHRLMTCELLPGr, &rval, SHRLMTf, 6); 15427 soc_reg_field_set(unit, WAMUSHRLMTCELLPGr, &rval, DYNMf, 1); 15428 SOC_IF_ERROR_RETURN 15429 (soc_reg32_set(unit, WAMUSHRLMTCELLPGr, REG_PORT_ANY, 0, rval)); 15430 15431 for (idx = 0; idx < 8; idx++) { 15432 rval = 0; 15433 soc_reg_field_set(unit, WAMUSHRLMTPKTQr, &rval, SHRLMTPKTf, 0xfff); 15434 soc_reg_field_set(unit, WAMUSHRLMTPKTQr, &rval, DYNMf, 1); 15435 SOC_IF_ERROR_RETURN 15436 (soc_reg32_set(unit, WAMUSHRLMTPKTQr, REG_PORT_ANY, idx, rval)); 15437 15438 rval = 0; 15439 soc_reg_field_set(unit, WAMUMINLMTPKTQr, &rval, MINLMTPKTf, 2); 15440 SOC_IF_ERROR_RETURN 15441 (soc_reg32_set(unit, WAMUMINLMTPKTQr, REG_PORT_ANY, idx, rval)); 15442 15443 rval = 0; 15444 soc_reg_field_set(unit, WAMURSTOFFSETPKTQr, &rval, RSTOFFSETf, 2); 15445 SOC_IF_ERROR_RETURN 15446 (soc_reg32_set(unit, WAMURSTOFFSETPKTQr, REG_PORT_ANY, idx, rval)); 15447 } 15448 15449 return SOC_E_NONE; 15450 } 15451 15452 int soc_tr3_mmu_get_shared_size(int unit, int *shared_size) 15453 { 15454 soc_info_t *si; 15455 uint32 entry0[SOC_MAX_MEM_WORDS]; 15456 int idx, total_min_limit = 0; 15457 int port, base = 0, numq = 0; 15458 uint32 rval; 15459 int total_pool_size = _TR3_MMU_TOTAL_CELLS(unit) - _TR3_MMU_CELLS_RSVD_IP; 15460 15461 si = &SOC_INFO(unit); 15462 PBMP_ALL_ITER(unit, port) { 15463 for (idx = 0; idx < si->port_num_cosq[port]; idx++) { 15464 SOC_IF_ERROR_RETURN 15465 (READ_OP_QUEUE_CONFIG_CELLr(unit, port, idx, &rval)); 15466 total_min_limit += soc_reg_field_get(unit, OP_QUEUE_CONFIG_CELLr, 15467 rval, Q_MIN_CELLf); 15468 } 15469 /* per port regular unicast queue */ 15470 soc_tr3_get_def_qbase(unit, port, _SOC_TR3_INDEX_STYLE_UCAST_QUEUE, 15471 &base, &numq); 15472 for (idx = 0; idx < numq; idx++) { 15473 sal_memset(entry0, 0, sizeof(mmu_thdo_config_queue_entry_t)); 15474 15475 SOC_IF_ERROR_RETURN 15476 (soc_mem_read(unit, MMU_THDO_CONFIG_QUEUEm, MEM_BLOCK_ALL, 15477 base + idx, entry0)); 15478 total_min_limit += soc_mem_field32_get(unit, MMU_THDO_CONFIG_QUEUEm, entry0, 15479 Q_MIN_LIMIT_CELLf); 15480 } 15481 } 15482 base = base + numq; 15483 /* extended queue profiles.*/ 15484 for (idx = 0; idx < SOC_MMU_CFG_EQUEUE_MAX; idx++) { 15485 if ((base + idx) >= _BCM_TR3_NUM_L2_UC_LEAVES) { 15486 break; 15487 } 15488 sal_memset(entry0, 0, sizeof(mmu_thdo_config_queue_entry_t)); 15489 SOC_IF_ERROR_RETURN 15490 (soc_mem_read(unit, MMU_THDO_CONFIG_QUEUEm, MEM_BLOCK_ALL, 15491 base + idx, entry0)); 15492 total_min_limit += soc_mem_field32_get(unit, MMU_THDO_CONFIG_QUEUEm, entry0, 15493 Q_MIN_LIMIT_CELLf); 15494 } 15495 15496 *shared_size = (total_pool_size - total_min_limit); 15497 return SOC_E_NONE; 15498 } 15499 15500 STATIC int 15501 _soc_tr3_mmu_config_shared_update_check(int unit, int val1, int val2, int flags) 15502 { 15503 int rv = 0; 15504 if (!flags) { 15505 return 1; 15506 } 15507 if (flags == 1) { 15508 if (val1 > val2) { 15509 rv = 1; 15510 } 15511 } 15512 return rv; 15513 } 15514 15515 int 15516 soc_tr3_mmu_config_shared_buf_recalc(int unit, uint32 spid, int delta, int flags) 15517 { 15518 soc_info_t *si; 15519 soc_reg_t reg = INVALIDr; 15520 soc_reg_t reg2 = INVALIDr; 15521 soc_mem_t mem = INVALIDm; 15522 uint32 rval; 15523 uint32 rval2; 15524 uint32 entry0[SOC_MAX_MEM_WORDS]; 15525 thdi_port_pg_config_entry_t pg_config_mem; 15526 mmu_thdo_config_qgroup_entry_t cfg_qgrp; 15527 int default_mtu_cells, midx; 15528 int port, phy_port, mmu_port, base = 0, numq = 0, idx; 15529 soc_field_t field = INVALIDf; 15530 soc_field_t field2 = INVALIDf; 15531 int reset_limit, granularity, cur_limit; 15532 static const soc_field_t pg_spid_field[] = { 15533 PG0_SPIDf, PG1_SPIDf, PG2_SPIDf, PG3_SPIDf, 15534 PG4_SPIDf, PG5_SPIDf, PG6_SPIDf, PG7_SPIDf 15535 }; 15536 15537 if (spid >= _TR3_MMU_NUM_POOL) { 15538 return SOC_E_PARAM; 15539 } 15540 15541 si = &SOC_INFO(unit); 15542 default_mtu_cells = _MMU_CFG_MMU_BYTES_TO_CELLS(_TR3_MMU_DEFAULT_MTU_BYTES + 15543 _TR3_MMU_PACKET_HEADER_BYTES, 15544 _TR3_MMU_BYTES_PER_CELL); 15545 /* configure Q-groups */ 15546 for (idx = 0; idx < SOC_MMU_CFG_QGROUP_MAX; idx++) { 15547 mem = MMU_THDO_CONFIG_QGROUPm; 15548 field = Q_SHARED_LIMIT_CELLf; 15549 granularity = 1; 15550 SOC_IF_ERROR_RETURN 15551 (soc_mem_read(unit, mem, MEM_BLOCK_ALL, idx, &cfg_qgrp)); 15552 if (!soc_mem_field32_get(unit, mem, &cfg_qgrp, Q_LIMIT_DYNAMIC_CELLf)) { 15553 cur_limit = soc_mem_field32_get(unit, mem, &cfg_qgrp, field); 15554 cur_limit *= granularity; 15555 if (_soc_tr3_mmu_config_shared_update_check(unit, cur_limit, delta, flags)) { 15556 if (flags) { 15557 soc_mem_field32_set(unit, mem, &cfg_qgrp, 15558 field, (cur_limit - delta)/granularity); 15559 } else { 15560 soc_mem_field32_set(unit, mem, &cfg_qgrp, 15561 field, (cur_limit + delta)/granularity); 15562 } 15563 } 15564 } 15565 SOC_IF_ERROR_RETURN 15566 (soc_mem_write(unit, mem, MEM_BLOCK_ALL, idx, &cfg_qgrp)); 15567 } 15568 15569 /* Input port per port settings */ 15570 PBMP_ALL_ITER(unit, port) { 15571 phy_port = si->port_l2p_mapping[port]; 15572 mmu_port = si->port_p2m_mapping[phy_port]; 15573 15574 mem = THDI_PORT_PG_CONFIGm; 15575 /* Input port per port per priority group settings */ 15576 for (idx = 0; idx < _TR3_MMU_NUM_PG; idx++) { 15577 midx = (mmu_port * 8) + idx; 15578 field = PG_SHARED_LIMITf; 15579 SOC_IF_ERROR_RETURN(READ_PORT_PG_SPIDr(unit, port, &rval)); 15580 if (spid != soc_reg_field_get(unit, PORT_PG_SPIDr, rval, 15581 pg_spid_field[idx])) { 15582 continue; 15583 } 15584 SOC_IF_ERROR_RETURN(soc_mem_read(unit, mem, MEM_BLOCK_ALL, 15585 midx, &pg_config_mem)); 15586 granularity = 1; 15587 if (!soc_mem_field32_get(unit, mem, &pg_config_mem, PG_SHARED_DYNAMICf)) { 15588 cur_limit = soc_mem_field32_get(unit, mem, &pg_config_mem, 15589 field); 15590 cur_limit *= granularity; 15591 if (_soc_tr3_mmu_config_shared_update_check(unit, cur_limit, delta, flags)) { 15592 if (flags) { 15593 soc_mem_field32_set(unit, mem, &pg_config_mem, 15594 field, (cur_limit - delta)/granularity); 15595 } else { 15596 soc_mem_field32_set(unit, mem, &pg_config_mem, 15597 field, (cur_limit + delta)/granularity); 15598 } 15599 } 15600 } 15601 SOC_IF_ERROR_RETURN 15602 (soc_mem_write(unit, mem, MEM_BLOCK_ALL, 15603 midx, &pg_config_mem)); 15604 } 15605 } 15606 15607 /*********************************** 15608 * THDO 15609 */ 15610 15611 /* Output port per port per queue setting for multicast queue */ 15612 PBMP_ALL_ITER(unit, port) { 15613 for (idx = 0; idx < si->port_num_cosq[port]; idx++) { 15614 reg = OP_QUEUE_CONFIG_CELLr; 15615 reg2 = OP_QUEUE_CONFIG1_CELLr; 15616 field = Q_SHARED_LIMIT_CELLf; 15617 SOC_IF_ERROR_RETURN 15618 (READ_OP_QUEUE_CONFIG_CELLr(unit, port, idx, &rval)); 15619 SOC_IF_ERROR_RETURN 15620 (READ_OP_QUEUE_CONFIG1_CELLr(unit, port, idx, &rval2)); 15621 if (spid != soc_reg_field_get(unit, OP_QUEUE_CONFIG1_CELLr, rval2, 15622 Q_SPIDf)) { 15623 continue; 15624 } 15625 granularity = 1; 15626 if (!soc_reg_field_get(unit, reg2, rval2, Q_LIMIT_DYNAMIC_CELLf)) { 15627 cur_limit = soc_reg_field_get(unit, reg, rval, field); 15628 cur_limit *= granularity; 15629 if (_soc_tr3_mmu_config_shared_update_check(unit, cur_limit, delta, flags)) { 15630 if (flags) { 15631 soc_reg_field_set(unit, reg, &rval, field, (cur_limit - delta)/granularity); 15632 } else { 15633 soc_reg_field_set(unit, reg, &rval, field, (cur_limit + delta)/granularity); 15634 } 15635 } 15636 } 15637 SOC_IF_ERROR_RETURN 15638 (WRITE_OP_QUEUE_CONFIG_CELLr(unit, port, idx, rval)); 15639 } 15640 } 15641 /* Output port per port per queue setting for regular unicast queue */ 15642 PBMP_ALL_ITER(unit, port) { 15643 if (IS_CPU_PORT(unit, port)) { 15644 continue; 15645 } 15646 15647 /* per port regular unicast queue */ 15648 soc_tr3_get_def_qbase(unit, port, _SOC_TR3_INDEX_STYLE_UCAST_QUEUE, 15649 &base, &numq); 15650 for (idx = 0; idx < numq; idx++) { 15651 mem = MMU_THDO_CONFIG_QUEUEm; 15652 field = Q_SHARED_LIMIT_CELLf; 15653 granularity = 1; 15654 SOC_IF_ERROR_RETURN 15655 (soc_mem_read(unit, MMU_THDO_Q_TO_QGRP_MAPm, 15656 MEM_BLOCK_ALL, base + idx, &entry0)); 15657 if (spid != soc_mem_field32_get(unit, MMU_THDO_Q_TO_QGRP_MAPm, 15658 &entry0, Q_SPIDf)) { 15659 continue; 15660 } 15661 SOC_IF_ERROR_RETURN 15662 (soc_mem_read(unit, mem, MEM_BLOCK_ALL, base + idx, &entry0)); 15663 if (!soc_mem_field32_get(unit, mem, &entry0, Q_LIMIT_DYNAMIC_CELLf)) { 15664 cur_limit = soc_mem_field32_get(unit, mem, &entry0, field); 15665 cur_limit *= granularity; 15666 if (_soc_tr3_mmu_config_shared_update_check(unit, cur_limit, delta, flags)) { 15667 if (flags) { 15668 soc_mem_field32_set(unit, mem, &entry0, 15669 field, (cur_limit - delta)/granularity); 15670 } else { 15671 soc_mem_field32_set(unit, mem, &entry0, 15672 field, (cur_limit + delta)/granularity); 15673 } 15674 } 15675 } 15676 15677 SOC_IF_ERROR_RETURN 15678 (soc_mem_write(unit, MMU_THDO_CONFIG_QUEUEm, MEM_BLOCK_ALL, 15679 base + idx, entry0)); 15680 } 15681 } 15682 base = base + numq; 15683 /* extended queue profiles.*/ 15684 for (idx = 0; idx < SOC_MMU_CFG_EQUEUE_MAX; idx++) { 15685 if ((base + idx) >= _BCM_TR3_NUM_L2_UC_LEAVES) { 15686 break; 15687 } 15688 mem = MMU_THDO_CONFIG_QUEUEm; 15689 field = Q_SHARED_LIMIT_CELLf; 15690 granularity = 1; 15691 SOC_IF_ERROR_RETURN 15692 (soc_mem_read(unit, MMU_THDO_Q_TO_QGRP_MAPm, 15693 MEM_BLOCK_ALL, base + idx, &entry0)); 15694 if (spid != soc_mem_field32_get(unit, MMU_THDO_Q_TO_QGRP_MAPm, 15695 &entry0, Q_SPIDf)) { 15696 continue; 15697 } 15698 SOC_IF_ERROR_RETURN 15699 (soc_mem_read(unit, mem, MEM_BLOCK_ALL, base + idx, &entry0)); 15700 if (!soc_mem_field32_get(unit, mem, &entry0, Q_LIMIT_DYNAMIC_CELLf)) { 15701 cur_limit = soc_mem_field32_get(unit, mem, &entry0, field); 15702 cur_limit *= granularity; 15703 if (_soc_tr3_mmu_config_shared_update_check(unit, cur_limit, delta, flags)) { 15704 if (flags) { 15705 soc_mem_field32_set(unit, mem, &entry0, 15706 field, (cur_limit - delta)/granularity); 15707 } else { 15708 soc_mem_field32_set(unit, mem, &entry0, 15709 field, (cur_limit + delta)/granularity); 15710 } 15711 } 15712 } 15713 SOC_IF_ERROR_RETURN 15714 (soc_mem_write(unit, MMU_THDO_CONFIG_QUEUEm, MEM_BLOCK_ALL, 15715 base + idx, entry0)); 15716 } 15717 15718 /* Output port per pool settings */ 15719 idx = spid; 15720 reg = OP_BUFFER_SHARED_LIMIT_CELLr; 15721 field = OP_BUFFER_SHARED_LIMIT_CELLf; 15722 reg2 = OP_BUFFER_SHARED_LIMIT_RESUME_CELLr; 15723 field2 = OP_BUFFER_SHARED_LIMIT_RESUME_CELLf; 15724 15725 SOC_IF_ERROR_RETURN 15726 (soc_reg32_get(unit, reg, REG_PORT_ANY, idx, &rval)); 15727 SOC_IF_ERROR_RETURN 15728 (soc_reg32_get(unit, reg2, REG_PORT_ANY, idx, &rval2)); 15729 granularity = 1; 15730 cur_limit = soc_reg_field_get(unit, reg, rval, field); 15731 cur_limit *= granularity; 15732 if (_soc_tr3_mmu_config_shared_update_check(unit, cur_limit, delta, flags)) { 15733 if (flags) { 15734 soc_reg_field_set(unit, reg, &rval, field, (cur_limit - delta)/granularity); 15735 soc_reg_field_set(unit, reg2, &rval2, field2, (cur_limit - delta)/granularity); 15736 } else { 15737 soc_reg_field_set(unit, reg, &rval, field, (cur_limit + delta)/granularity); 15738 soc_reg_field_set(unit, reg2, &rval2, field2, (cur_limit + delta)/granularity); 15739 } 15740 } 15741 SOC_IF_ERROR_RETURN 15742 (soc_reg32_set(unit, reg, REG_PORT_ANY, idx, rval)); 15743 SOC_IF_ERROR_RETURN 15744 (soc_reg32_set(unit, reg2, REG_PORT_ANY, idx, rval2)); 15745 15746 /* Output port per port per pool setting */ 15747 PBMP_PORT_ITER(unit, port) { 15748 phy_port = si->port_l2p_mapping[port]; 15749 mmu_port = si->port_p2m_mapping[phy_port]; 15750 midx = (mmu_port * 4) + idx; 15751 mem = MMU_THDO_CONFIG_PORTm; 15752 field = SHARED_LIMITf; 15753 field2 = SHARED_RESUMEf; 15754 SOC_IF_ERROR_RETURN 15755 (soc_mem_read(unit, mem, MEM_BLOCK_ALL, midx, &entry0)); 15756 granularity = 1; 15757 cur_limit = soc_mem_field32_get(unit, mem, &entry0, 15758 field); 15759 cur_limit *= granularity; 15760 if (_soc_tr3_mmu_config_shared_update_check(unit, cur_limit, delta, flags)) { 15761 if (flags) { 15762 reset_limit = (cur_limit - delta/granularity) - (2 * default_mtu_cells); 15763 if (reset_limit < 0) { 15764 reset_limit = 0; 15765 } 15766 soc_mem_field32_set(unit, mem, &entry0, 15767 field, (cur_limit - delta)/granularity); 15768 soc_mem_field32_set(unit, mem, &entry0, 15769 field2, reset_limit); 15770 } else { 15771 reset_limit = (cur_limit + delta/granularity) - (2 * default_mtu_cells); 15772 if (reset_limit < 0) { 15773 reset_limit = 0; 15774 } 15775 soc_mem_field32_set(unit, mem, &entry0, 15776 field, (cur_limit + delta)/granularity); 15777 soc_mem_field32_set(unit, mem, &entry0, 15778 field2, reset_limit); 15779 } 15780 } 15781 SOC_IF_ERROR_RETURN 15782 (soc_mem_write(unit, mem, MEM_BLOCK_ALL, 15783 midx, &entry0)); 15784 } 15785 15786 /* Output port per port per pool setting for multicast queues */ 15787 PBMP_PORT_ITER(unit, port) { 15788 reg = OP_PORT_CONFIG_CELLr; 15789 field = OP_SHARED_LIMIT_CELLf; 15790 field2 = OP_SHARED_RESET_VALUE_CELLf; 15791 SOC_IF_ERROR_RETURN 15792 (soc_reg32_get(unit, reg, port, 15793 idx, &rval)); 15794 granularity = 1; 15795 cur_limit = soc_reg_field_get(unit, reg, rval, field); 15796 cur_limit *= granularity; 15797 if (_soc_tr3_mmu_config_shared_update_check(unit, cur_limit, delta/granularity, flags)) { 15798 if (flags) { 15799 reset_limit = ((cur_limit - delta)/granularity) - (2 * default_mtu_cells); 15800 if (reset_limit < 0) { 15801 reset_limit = 0; 15802 } 15803 soc_reg_field_set(unit, reg, &rval, field, ((cur_limit - delta)/granularity)); 15804 soc_reg_field_set(unit, reg, &rval, field2, reset_limit); 15805 } else { 15806 reset_limit = ((cur_limit + delta)/granularity) - (2 * default_mtu_cells); 15807 if (reset_limit < 0) { 15808 reset_limit = 0; 15809 } 15810 soc_reg_field_set(unit, reg, &rval, field, ((cur_limit + delta)/granularity)); 15811 soc_reg_field_set(unit, reg, &rval, field2, reset_limit); 15812 } 15813 } 15814 SOC_IF_ERROR_RETURN 15815 (soc_reg32_set(unit, reg, port, 15816 idx, rval)); 15817 } 15818 return SOC_E_NONE; 15819 } 15820 15821 int 15822 soc_tr3_mmu_config_init(int unit, int test_only) 15823 { 15824 int rv; 15825 _soc_mmu_cfg_buf_t *buf; 15826 _soc_mmu_device_info_t devcfg; 15827 15828 buf = soc_mmu_cfg_alloc(unit); 15829 if (!buf) { 15830 return SOC_E_MEMORY; 15831 } 15832 15833 _soc_tr3_mmu_init_dev_config(unit, &devcfg); 15834 _soc_tr3_mmu_config_buf_default(unit, buf); 15835 _soc_mmu_cfg_buf_read(unit, buf, &devcfg); 15836 rv = _soc_mmu_cfg_buf_check(unit, buf, &devcfg); 15837 if (!test_only) { 15838 if (SOC_FAILURE(rv)) { 15839 LOG_VERBOSE(BSL_LS_SOC_COMMON, 15840 (BSL_META_U(unit, 15841 "MMU config: Use default setting\n"))); 15842 _soc_tr3_mmu_config_buf_default(unit, buf); 15843 _soc_mmu_cfg_buf_calculate(unit, buf, &devcfg); 15844 } 15845 rv = _soc_tr3_mmu_config_buf_set_hw(unit, buf); 15846 } 15847 15848 soc_mmu_cfg_free(unit, buf); 15849 15850 LOG_VERBOSE(BSL_LS_SOC_COMMON, 15851 (BSL_META_U(unit, 15852 "MMU THDI/THDO init done\n"))); 15853 return rv; 15854 } 15855 15856 int 15857 soc_tr3_lls_sched_init(int unit) 15858 { 15859 uint32 rval; 15860 int mmu_init_usec; 15861 soc_timeout_t to; 15862 15863 /* Init Link List Scheduler */ 15864 rval = 0; 15865 soc_reg_field_set(unit, LLS_SOFT_RESETr, &rval, SOFT_RESETf, 0); 15866 SOC_IF_ERROR_RETURN(WRITE_LLS_SOFT_RESETr(unit, rval)); 15867 15868 rval = 0; 15869 soc_reg_field_set(unit, LLS_INITr, &rval, INITf, 1); 15870 SOC_IF_ERROR_RETURN(WRITE_LLS_INITr(unit, rval)); 15871 15872 /* Wait for LLS init done. */ 15873 if (SAL_BOOT_SIMULATION) { 15874 mmu_init_usec = 10000000; /* Simulation .. 10sec */ 15875 } else { 15876 mmu_init_usec = 50000; 15877 } 15878 soc_timeout_init(&to, mmu_init_usec, 0); 15879 do { 15880 SOC_IF_ERROR_RETURN(READ_LLS_INITr(unit, &rval)); 15881 if (soc_reg_field_get(unit, LLS_INITr, rval, INIT_DONEf)) { 15882 break; 15883 } 15884 if (soc_timeout_check(&to)) { 15885 LOG_WARN(BSL_LS_SOC_COMMON, 15886 (BSL_META_U(unit, 15887 "unit %d : LLS INIT timeout\n"), unit)); 15888 break; 15889 } 15890 } while (TRUE); 15891 15892 return SOC_E_NONE; 15893 } 15894 int 15895 _soc_tr3_mmu_init(int unit) 15896 { 15897 uint32 rval; 15898 uint64 r64val; 15899 int port, i, numq = 0, credits = 0, total_queues; 15900 egr_edb_xmit_ctrl_entry_t e; 15901 soc_reg_t reg; 15902 int phy_port, mmu_port; 15903 soc_info_t *si; 15904 15905 si = &SOC_INFO(unit); 15906 15907 /* Init Link List Scheduler */ 15908 SOC_IF_ERROR_RETURN(soc_tr3_lls_sched_init(unit));; 15909 15910 /* Setup TDM for MMU Arb & LLS */ 15911 SOC_IF_ERROR_RETURN(_soc_tr3_mmu_tdm_init(unit)); 15912 SOC_IF_ERROR_RETURN(soc_tr3_mmu_config_init(unit, FALSE)); 15913 15914 /* Enable LLS */ 15915 rval = 0; 15916 soc_reg_field_set(unit, LLS_CONFIG0r, &rval, DEQUEUE_ENABLEf, 1); 15917 soc_reg_field_set(unit, LLS_CONFIG0r, &rval, ENQUEUE_ENABLEf, 1); 15918 soc_reg_field_set(unit, LLS_CONFIG0r, &rval, PORT_SCHEDULER_ENABLEf, 1); 15919 SOC_IF_ERROR_RETURN(WRITE_LLS_CONFIG0r(unit, rval)); 15920 15921 /* LLS default init */ 15922 SOC_IF_ERROR_RETURN(soc_tr3_lls_init(unit)); 15923 15924 /* Enable IP to CMICM credit transfer */ 15925 rval = 0; 15926 soc_reg_field_set(unit, IP_TO_CMICM_CREDIT_TRANSFERr, &rval, TRANSFER_ENABLEf, 1); 15927 soc_reg_field_set(unit, IP_TO_CMICM_CREDIT_TRANSFERr, &rval, NUM_OF_CREDITSf, 32); 15928 SOC_IF_ERROR_RETURN(WRITE_IP_TO_CMICM_CREDIT_TRANSFERr(unit, rval)); 15929 15930 PBMP_ALL_ITER(unit, port) { 15931 phy_port = si->port_l2p_mapping[port]; 15932 mmu_port = si->port_p2m_mapping[phy_port]; 15933 15934 total_queues = ((mmu_port >= 40) && (mmu_port <= 55)) ? 10 : 8; 15935 15936 _soc_tr3_get_numq_and_fifo_size(unit, port, &credits, &numq); 15937 if (numq == 0) { 15938 continue; 15939 } 15940 15941 if ((mmu_port >= 40) && (mmu_port <= 47)) { 15942 reg = MCQ_FIFO_BASE_REGr; 15943 } else if ((mmu_port >= 48) && (mmu_port <= 55)) { 15944 reg = MCQ_FIFO_BASE_REG_48_55r; 15945 } else if ((mmu_port >= 36) && (mmu_port <= 39)) { 15946 reg = MCQ_FIFO_BASE_REG_36_39r; 15947 } else if ((mmu_port >= 32) && (mmu_port <= 35)) { 15948 reg = MCQ_FIFO_BASE_REG_32_35r; 15949 } else if (mmu_port == 56) { 15950 reg = MCQ_FIFO_BASE_REG_56r; 15951 } else if (mmu_port == 58) { 15952 reg = MCQ_FIFO_BASE_REG_PASSTHRUr; 15953 } else if (mmu_port == 59) { 15954 reg = MCQ_FIFO_BASE_REG_CPUr; 15955 } else { 15956 reg = INVALIDr; 15957 } 15958 15959 for (i = 0; i < numq; i++) { 15960 LOG_VERBOSE(BSL_LS_SOC_COMMON, 15961 (BSL_META_U(unit, 15962 "seting OVQ credits for port: %s(%d) = %d\n"), 15963 SOC_PORT_NAME(unit, port),i, credits)); 15964 if (reg != INVALIDr) { 15965 if (credits < 2048) { 15966 LOG_VERBOSE(BSL_LS_SOC_COMMON, 15967 (BSL_META_U(unit, 15968 "setting MCQ base for port: %s(queue%d) = %d\n"), 15969 SOC_PORT_NAME(unit, port), i, i*credits)); 15970 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, reg, port, i, i*credits)); 15971 } else { 15972 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, reg, port, i, 0)); 15973 } 15974 } 15975 SOC_IF_ERROR_RETURN(WRITE_OVQ_MCQ_CREDITSr(unit, port, i, credits)); 15976 } 15977 15978 for (i = numq; i < total_queues; i++) { 15979 if (reg != INVALIDr) { 15980 if (credits < 2048) { 15981 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, reg, port, i, i*credits)); 15982 } else { 15983 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, reg, port, i, 0)); 15984 } 15985 } 15986 SOC_IF_ERROR_RETURN(WRITE_OVQ_MCQ_CREDITSr(unit, port, i, 0)); 15987 } 15988 15989 COMPILER_64_ZERO(r64val); 15990 soc_reg64_field32_set(unit, MMU_INTFO_CONGST_STr, &r64val, ENf, 1); 15991 SOC_IF_ERROR_RETURN(WRITE_MMU_INTFO_CONGST_STr(unit, port, r64val)); 15992 } 15993 15994 SOC_IF_ERROR_RETURN(WRITE_OVQ_MCQ_CREDITSr(unit, 15995 AXP_PORT(unit, SOC_AXP_NLF_SM), 0, 32)); 15996 15997 _soc_tr3_set_mcfifo_config(unit); 15998 15999 for (i=0; i<80; i++) { 16000 sal_memset(&e, 0, sizeof(egr_edb_xmit_ctrl_entry_t)); 16001 soc_mem_field32_set(unit, EGR_EDB_XMIT_CTRLm, &e, START_CNTf, 16002 (i < 53) ? 7 : 2); 16003 /* XL ports should have WAIT_FOR_MOP field set. */ 16004 if ((i > 64) && (i < 69)) { 16005 soc_mem_field32_set(unit, EGR_EDB_XMIT_CTRLm, &e, WAIT_FOR_MOPf, 1); 16006 } 16007 SOC_IF_ERROR_RETURN(WRITE_EGR_EDB_XMIT_CTRLm(unit, MEM_BLOCK_ALL, i, &e)); 16008 } 16009 16010 /* OVQ settings */ 16011 rval = 0; 16012 soc_reg_field_set(unit, OVQ_DROP_THRESHOLD0r, &rval, 16013 OVQ_DROP_THRESHOLD0f, 0x17cf); 16014 SOC_IF_ERROR_RETURN(WRITE_OVQ_DROP_THRESHOLD0r(unit, rval)); 16015 16016 rval = 0; 16017 soc_reg_field_set(unit, OVQ_DROP_THRESHOLD_RESET_LIMITr, &rval, 16018 OVQ_DROP_THRESHOLD_RESET_LIMITf, 0x1700); 16019 SOC_IF_ERROR_RETURN(WRITE_OVQ_DROP_THRESHOLD_RESET_LIMITr(unit, rval)); 16020 16021 rval = 0; 16022 soc_reg_field_set(unit, OP_THR_CONFIGr, &rval, MOP_POLICYf, 7); 16023 soc_reg_field_set(unit, OP_THR_CONFIGr, &rval, YELLOW_CELL_DS_SELECTf, 1); 16024 SOC_IF_ERROR_RETURN(WRITE_OP_THR_CONFIGr(unit, rval)); 16025 16026 #if 0 16027 rval = 0; 16028 soc_reg_field_set(unit, OVQ_FLOWCONTROL_THRESHOLDr, &rval, 16029 OVQ_FC_ENABLEf, 1); 16030 soc_reg_field_set(unit, OVQ_FLOWCONTROL_THRESHOLDr, &rval, 16031 OVQ_FC_THRESHOLDf, 11250); 16032 soc_reg_field_set(unit, OVQ_FLOWCONTROL_THRESHOLDr, &rval, 16033 OVQ_FC_THRESHOLD_RESET_LIMITf, 11249); 16034 SOC_IF_ERROR_RETURN(WRITE_OVQ_FLOWCONTROL_THRESHOLDr(unit, rval)); 16035 #endif 16036 16037 /* Enable all ports */ 16038 COMPILER_64_ZERO(r64val); 16039 COMPILER_64_SET(r64val, 0x7fffffff, 0xffffffff); 16040 SOC_IF_ERROR_RETURN(WRITE_INPUT_PORT_RX_ENABLE_64r(unit, r64val)); 16041 COMPILER_64_ZERO(r64val); 16042 COMPILER_64_SET(r64val, 0x7fffffff, 0xffffffff); 16043 SOC_IF_ERROR_RETURN(WRITE_OUTPUT_PORT_RX_ENABLE0_64r(unit, r64val)); 16044 16045 /* init dual modid */ 16046 if ((NUM_MODID(unit) == 2) && 16047 (SOC_REG_IS_VALID(unit, E2EFC_CONFIGr)) ) { 16048 SOC_IF_ERROR_RETURN(READ_E2EFC_CONFIGr(unit, &rval)); 16049 soc_reg_field_set(unit, E2EFC_CONFIGr, &rval, DUAL_MODID_ENf, 1); 16050 SOC_IF_ERROR_RETURN(WRITE_E2EFC_CONFIGr(unit, rval)); 16051 } 16052 16053 PBMP_ALL_ITER(unit, port) { 16054 if (SOC_INFO(unit).port_num_uc_cosq[port] > 0) { 16055 COMPILER_64_ZERO(r64val); 16056 soc_reg64_field32_set(unit, ING_COS_MODEr, &r64val, 16057 BASE_QUEUE_NUM_0f, SOC_INFO(unit).port_uc_cosq_base[port]); 16058 16059 soc_reg64_field32_set(unit, ING_COS_MODEr, &r64val, 16060 BASE_QUEUE_NUM_1f, SOC_INFO(unit).port_uc_cosq_base[port]); 16061 16062 SOC_IF_ERROR_RETURN(WRITE_ING_COS_MODEr(unit, port, 16063 COMPILER_64_LO(r64val))); 16064 } 16065 } 16066 16067 rval = 0; 16068 soc_reg_field_set(unit, PRIORITY_CONTROLr, &rval, USE_SC_FOR_MH_PRIf, 1); 16069 soc_reg_field_set(unit, PRIORITY_CONTROLr, &rval, USE_QM_FOR_MH_PRIf, 1); 16070 SOC_IF_ERROR_RETURN(WRITE_PRIORITY_CONTROLr(unit, rval)); 16071 16072 /* Input port pause enable */ 16073 COMPILER_64_ZERO(r64val); 16074 if (soc_property_get(unit, spn_MMU_LOSSLESS, 1)) { 16075 COMPILER_64_SET(r64val, 0x7fffffff, 0xffffffff); 16076 } 16077 SOC_IF_ERROR_RETURN(WRITE_PORT_PAUSE_ENABLE_64r(unit, r64val)); 16078 16079 SOC_IF_ERROR_RETURN(WRITE_THDI_BYPASSr(unit, 0)); 16080 SOC_IF_ERROR_RETURN(WRITE_THDO_BYPASSr(unit, 0)); 16081 16082 #ifdef BCM_WARM_BOOT_SUPPORT 16083 if (SOC_WARM_BOOT(unit) && soc_feature(unit, soc_feature_esm_support)) { 16084 SOC_IF_ERROR_RETURN(soc_tr3_esm_init_read_config(unit)); 16085 if (SOC_CONTROL(unit)->tcam_info) { 16086 SOC_IF_ERROR_RETURN(_soc_triumph3_esm_init_adjust_mem_size(unit)); 16087 } 16088 } 16089 #endif 16090 16091 if (soc_feature(unit, soc_feature_post)) { 16092 SOC_IF_ERROR_RETURN(soc_mmu_post_init(unit)); 16093 } 16094 16095 return SOC_E_NONE; 16096 } 16097 16098 STATIC int 16099 _soc_tr3_age_timer_get(int unit, int *age_seconds, int *enabled) 16100 { 16101 soc_control_t *soc = SOC_CONTROL(unit); 16102 *age_seconds = soc->l2x_age_interval ? (soc->l2x_age_interval) : 0; 16103 *enabled = (soc->l2x_age_pid != SAL_THREAD_ERROR) && (soc->l2x_age_interval ? 1 : 0); 16104 return SOC_E_NONE; 16105 } 16106 16107 STATIC int 16108 _soc_tr3_age_timer_max_get(int unit, int *max_seconds) 16109 { 16110 *max_seconds = 0xffffffff; 16111 return SOC_E_NONE; 16112 } 16113 16114 STATIC int 16115 _soc_tr3_age_timer_set(int unit, int age_seconds, int enable) 16116 { 16117 soc_control_t *soc = SOC_CONTROL(unit); 16118 sal_usecs_t interval = soc->l2x_age_interval; 16119 16120 /* SW aging thread running */ 16121 if (soc->l2x_age_interval) { 16122 if (!enable) { 16123 SOC_IF_ERROR_RETURN(soc_tr3_l2_bulk_age_stop(unit)); 16124 } else { 16125 if (age_seconds) { 16126 SOC_CONTROL_LOCK(unit); 16127 soc->l2x_age_interval = age_seconds; 16128 soc->l2x_prev_age_timeout = age_seconds; 16129 SOC_CONTROL_UNLOCK(unit); 16130 } 16131 /* Wake up thread to update the new age timer */ 16132 if (age_seconds != interval) { 16133 sal_sem_give(soc->l2x_age_notify); 16134 } 16135 } 16136 } else { 16137 /* SW aging not runninig, start the thread */ 16138 if (enable) { 16139 if (age_seconds) { 16140 SOC_CONTROL_LOCK(unit); 16141 soc->l2x_prev_age_timeout = age_seconds; 16142 SOC_CONTROL_UNLOCK(unit); 16143 } 16144 SOC_IF_ERROR_RETURN 16145 (soc_tr3_l2_bulk_age_start(unit, age_seconds)); 16146 } 16147 } 16148 return SOC_E_NONE; 16149 } 16150 16151 static 16152 soc_field_t _soc_tr3_oam_interrupt_fields[] = { 16153 SOME_RDI_DEFECT_INTRf, 16154 SOME_RMEP_CCM_DEFECT_INTRf, 16155 ERROR_CCM_DEFECT_INTRf, 16156 ANY_RMEP_TLV_PORT_DOWN_INTRf, 16157 ANY_RMEP_TLV_PORT_UP_INTRf, 16158 ANY_RMEP_TLV_INTERFACE_DOWN_INTRf, 16159 ANY_RMEP_TLV_INTERFACE_UP_INTRf, 16160 XCON_CCM_DEFECT_INTRf, 16161 INVALIDf 16162 }; 16163 16164 void 16165 soc_tr3_oam_handler_register(int unit, soc_tr3_oam_handler_t handler) 16166 { 16167 uint32 rval; 16168 int rv, fidx = 0; 16169 16170 tr3_oam_handler[unit] = handler; 16171 16172 rv = READ_IP2_INTR_ENABLE_2r(unit, &rval); 16173 if (rv) { 16174 LOG_ERROR(BSL_LS_SOC_COMMON, 16175 (BSL_META_U(unit, 16176 "unit %d: Error reading %s reg !!\n"), 16177 unit, SOC_REG_NAME(unit, IP2_INTR_ENABLE_2r))); 16178 } 16179 while (_soc_tr3_oam_interrupt_fields[fidx] != INVALIDf) { 16180 soc_reg_field_set(unit, IP2_INTR_ENABLE_2r, &rval, 16181 _soc_tr3_oam_interrupt_fields[fidx], 1); 16182 fidx++; 16183 } 16184 rv = WRITE_IP2_INTR_ENABLE_2r(unit, rval); 16185 if (rv) { 16186 LOG_ERROR(BSL_LS_SOC_COMMON, 16187 (BSL_META_U(unit, 16188 "unit %d: Error writing %s reg !!\n"), 16189 unit, SOC_REG_NAME(unit, IP2_INTR_ENABLE_2r))); 16190 } 16191 /* Enable Interrupt */ 16192 #ifdef BCM_CMICM_SUPPORT 16193 if (soc_feature(unit, soc_feature_cmicm)) { 16194 (void)soc_cmicm_intr2_enable(unit, _TR3_IRSEL1_TO_CMIC_OAM_INTR); 16195 } 16196 #endif 16197 } 16198 16199 void 16200 soc_tr3_oam_interrupt_process(int unit) 16201 { 16202 soc_tr3_oam_handler_t oam_handler_snapshot = tr3_oam_handler[unit]; 16203 16204 if (oam_handler_snapshot != NULL) { 16205 /* We don't need to specify the OAM interrupt to OAM handler as 16206 OAM Handler it checks for all OAM interrupts */ 16207 (void)(oam_handler_snapshot(unit, 0)); 16208 } 16209 } 16210 16211 void 16212 soc_tr3_oam_ser_handler_register(int unit, soc_tr3_oam_ser_handler_t handler) 16213 { 16214 tr3_oam_ser_handler[unit] = handler; 16215 } 16216 16217 int 16218 soc_tr3_oam_ser_process(int unit, soc_mem_t mem, int index) 16219 { 16220 if (tr3_oam_ser_handler[unit]) { 16221 return tr3_oam_ser_handler[unit](unit, mem, index); 16222 } else { 16223 return SOC_E_UNAVAIL; 16224 } 16225 } 16226 16227 static const soc_reg_t thermal_reg[] = { 16228 TOP_PVTMON_RESULT_0r, TOP_PVTMON_RESULT_1r, 16229 TOP_PVTMON_RESULT_2r, TOP_PVTMON_RESULT_3r, 16230 TOP_PVTMON_RESULT_4r 16231 }; 16232 16233 int 16234 soc_tr3_temperature_monitor_get(int unit, 16235 int temperature_max, 16236 soc_switch_temperature_monitor_t *temperature_array, 16237 int *temperature_count) 16238 { 16239 uint32 rval; 16240 soc_reg_t reg; 16241 int index; 16242 int fval, cur, peak; 16243 int num_entries_out; 16244 16245 *temperature_count = 0; 16246 if (COUNTOF(thermal_reg) > temperature_max) { 16247 num_entries_out = temperature_max; 16248 } else { 16249 num_entries_out = COUNTOF(thermal_reg); 16250 } 16251 #ifdef BCM_HELIX4_SUPPORT 16252 if (SOC_IS_HELIX4(unit)) { 16253 num_entries_out -= 2; 16254 } 16255 #endif 16256 reg = TOP_PVTMON_CTRL_0r; 16257 SOC_IF_ERROR_RETURN(READ_TOP_PVTMON_CTRL_0r(unit, &rval)); 16258 soc_reg_field_set(unit, reg, &rval, FUNC_MODE_SELf, 0); 16259 soc_reg_field_set(unit, reg, &rval, MEASUREMENT_CALLIBRATIONf, 5); 16260 soc_reg_field_set(unit, reg, &rval, BG_ADJf, 2); 16261 SOC_IF_ERROR_RETURN(WRITE_TOP_PVTMON_CTRL_0r(unit, rval)); 16262 16263 sal_usleep(1000); 16264 16265 for (index = 0; index < num_entries_out; index++) { 16266 reg = thermal_reg[index]; 16267 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, reg, REG_PORT_ANY, 0, &rval)); 16268 fval = soc_reg_field_get(unit, reg, rval, TEMP_DATAf); 16269 cur = (4180000 - (5556 * fval)) / 1000; 16270 fval = soc_reg_field_get(unit, reg, rval, PEAK_TEMP_DATAf); 16271 peak = (4180000 - (5556 * fval)) / 1000; 16272 (temperature_array + index)->curr = cur; 16273 (temperature_array + index)->peak = peak; 16274 } 16275 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REG_2r(unit, &rval)); 16276 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, 16277 TOP_TEMP_MON_PEAK_RST_Lf, 0); 16278 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REG_2r(unit, rval)); 16279 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, 16280 TOP_TEMP_MON_PEAK_RST_Lf, 1); 16281 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REG_2r(unit, rval)); 16282 *temperature_count=num_entries_out; 16283 16284 return SOC_E_NONE; 16285 } 16286 16287 soc_blk_ctr_reg_desc_t _soc_tr3_blk_ctr_reg_desc[] = { 16288 { 16289 SOC_BLK_AXP, 16290 { 16291 {AXP_SM_PACKETS_RECEIVED_COUNTERr, 1, 1, 0}, 16292 {AXP_SM_PACKETS_SENT_COUNTERr, 1, 1, 0}, 16293 {AXP_SM_PACKETS_DROPPED_COUNTERr, 1, 1, 0}, 16294 {AXP_SM_BYTES_MATCHED_COUNTERr, 1, 1, 0}, 16295 {AXP_SM_MATCHED_FLOWS_COUNTERr, 1, 1, 0}, 16296 {AXP_SM_UNMATCHED_FLOWS_COUNTERr, 1, 1, 0}, 16297 {AXP_SM_TOTAL_MATCH_COUNTERr, 1, 1, 0}, 16298 {AXP_SM_TOTAL_CROSS_SIG_FLAGS_COUNTERr, 1, 1, 0}, 16299 {AXP_SM_FRAGMENTS_RECEIVED_COUNTERr, 1, 1, 0}, 16300 {AXP_SM_IN_PACKET_ERROR_COUNTERr, 1, 1, 0}, 16301 {AXP_SM_FLOW_TRACKER_ERROR_COUNTERr, 1, 1, 0}, 16302 {AXP_SM_PACKET_LENGTH_ERROR_COUNTERr, 1, 1, 0}, 16303 {AXP_SM_L4_CHECKSUM_ERROR_COUNTERr, 1, 1, 0}, 16304 {AXP_SM_FLOW_DONE_PACKET_DROP_COUNTERr, 1, 1, 0}, 16305 {AXP_SM_FLOW_TIMESTAMP_ERROR_COUNTERr, 1, 1, 0}, 16306 {AXP_SM_FLOW_PACKET_NUM_ERROR_COUNTERr, 1, 1, 0}, 16307 {AXP_SM_ECC_ERROR_COUNTERr, 1, 1, 0}, 16308 {INVALIDr, 0, 0} 16309 } 16310 }, 16311 { 16312 SOC_BLK_ETU, 16313 { 16314 {ILAMAC_RX_PACKETS_COUNTr, 2, 1, 0}, 16315 {ILAMAC_RX_BYTES_COUNTr, 2, 1, 0}, 16316 {ILAMAC_TX_PACKETS_COUNTr, 2, 1, 0}, 16317 {ILAMAC_TX_BYTES_COUNTr, 2, 1, 0}, 16318 {ILAMAC_RX_WORD_SYNC_ERRORS_COUNTr, 1, 12, 8}, 16319 {ILAMAC_RX_FRAMING_ERRORS_COUNTr, 1, 12, 8}, 16320 {ILAMAC_RX_BAD_TYPE_ERRORS_COUNTr, 1, 12, 8}, 16321 {ILAMAC_RX_DESCRAM_ERRORS_COUNTr, 1, 12, 8}, 16322 {ILAMAC_RX_ALIGNMENT_ERRORS_COUNTr, 1, 1, 0}, 16323 {ILAMAC_RX_ALIGNMENT_FAILURES_ERRORS_COUNTr, 1, 1, 0}, 16324 {ILAMAC_RX_CRC_ERRORS_COUNTr, 1, 1, 0}, 16325 {ILAMAC_RX_BURSTMAX_ERRORS_COUNTr, 1, 1, 0}, 16326 {ILAMAC_RX_LANE_CRC_ERRORS_COUNTr, 1, 12, 8}, 16327 {ILAMAC_RX_BAD_PACKETS_COUNTr, 1, 1, 0}, 16328 {WCL_RX_LOST_LOCK_COUNTr, 1, 12, 8}, 16329 {INVALIDr, 0, 0} 16330 } 16331 } 16332 }; 16333 16334 void 16335 soc_tr3_blk_counter_config(int unit) 16336 { 16337 soc_control_t *soc = SOC_CONTROL(unit); 16338 soc->blk_ctr_desc_count = COUNTOF(_soc_tr3_blk_ctr_reg_desc); 16339 soc->blk_ctr_desc = _soc_tr3_blk_ctr_reg_desc; 16340 } 16341 16342 int _soc_tr3_ur_port_reset(int unit, int num_ports, soc_port_t port, 16343 soc_block_type_t pbt) 16344 { 16345 static const soc_reg_t lls_port_credit_reg[] = { 16346 LLS_PORT_0_CREDITr, LLS_PORT_1_CREDITr, LLS_PORT_2_CREDITr, 16347 LLS_PORT_3_CREDITr, LLS_PORT_4_CREDITr, LLS_PORT_5_CREDITr, 16348 LLS_PORT_6_CREDITr, LLS_PORT_7_CREDITr, LLS_PORT_8_CREDITr, 16349 LLS_PORT_9_CREDITr, LLS_PORT_10_CREDITr, LLS_PORT_11_CREDITr, 16350 LLS_PORT_12_CREDITr, LLS_PORT_13_CREDITr, LLS_PORT_14_CREDITr, 16351 LLS_PORT_15_CREDITr, LLS_PORT_16_CREDITr, LLS_PORT_17_CREDITr, 16352 LLS_PORT_18_CREDITr, LLS_PORT_19_CREDITr, LLS_PORT_20_CREDITr, 16353 LLS_PORT_21_CREDITr, LLS_PORT_22_CREDITr, LLS_PORT_23_CREDITr, 16354 LLS_PORT_24_CREDITr, LLS_PORT_25_CREDITr, LLS_PORT_26_CREDITr, 16355 LLS_PORT_27_CREDITr, LLS_PORT_28_CREDITr, LLS_PORT_29_CREDITr, 16356 LLS_PORT_30_CREDITr, LLS_PORT_31_CREDITr, LLS_PORT_32_CREDITr, 16357 LLS_PORT_33_CREDITr, LLS_PORT_34_CREDITr, LLS_PORT_35_CREDITr, 16358 LLS_PORT_36_CREDITr, LLS_PORT_37_CREDITr, LLS_PORT_38_CREDITr, 16359 LLS_PORT_39_CREDITr, LLS_PORT_40_CREDITr, LLS_PORT_41_CREDITr, 16360 LLS_PORT_42_CREDITr, LLS_PORT_43_CREDITr, LLS_PORT_44_CREDITr, 16361 LLS_PORT_45_CREDITr, LLS_PORT_46_CREDITr, LLS_PORT_47_CREDITr, 16362 LLS_PORT_48_CREDITr, LLS_PORT_49_CREDITr, LLS_PORT_50_CREDITr, 16363 LLS_PORT_51_CREDITr, LLS_PORT_52_CREDITr, LLS_PORT_53_CREDITr, 16364 LLS_PORT_54_CREDITr, LLS_PORT_55_CREDITr, LLS_PORT_56_CREDITr, 16365 LLS_PORT_57_CREDITr, LLS_PORT_58_CREDITr, LLS_PORT_59_CREDITr, 16366 LLS_PORT_60_CREDITr, LLS_PORT_61_CREDITr, LLS_PORT_62_CREDITr 16367 }; 16368 16369 int prev_port_speeds[_SOC_HX4_FIFO_CHK_MAX_PORTS]; 16370 int lanes, rv = SOC_E_NONE; 16371 egr_enable_entry_t egr_en; 16372 soc_info_t *si = &SOC_INFO(unit); 16373 #ifdef BCM_HELIX4_SUPPORT 16374 if ( SOC_IS_HELIX4(unit) && 16375 ((_tr3_port_config_id[unit] == 463) || (_tr3_port_config_id[unit] == 413)) && 16376 (57 == si->port_l2p_mapping[port] || 61 == si->port_l2p_mapping[port])){ 16377 switch (num_ports) { 16378 case 1: lanes = 2; break; 16379 case 2: lanes = 1; break; 16380 case 4: lanes = 1; break; 16381 default: lanes = 1; 16382 } 16383 }else 16384 #endif 16385 { 16386 switch (num_ports) { 16387 case 1: lanes = 4; break; 16388 case 2: lanes = 2; break; 16389 case 4: lanes = 1; break; 16390 default: lanes = 1; 16391 } 16392 } 16393 if (!SOC_WARM_BOOT(unit)) { 16394 _soc_tr3_current_port_speeds(unit, prev_port_speeds); 16395 } 16396 16397 /* put the port in reset */ 16398 SOC_IF_ERROR_RETURN 16399 (_soc_tr3_port_control(unit, port, pbt, FALSE)); 16400 /* reset egress buffers */ 16401 SOC_IF_ERROR_RETURN 16402 (_soc_tr3_egress_buffer_reset(unit, port, pbt, TRUE)); 16403 /* do port soft reset */ 16404 SOC_IF_ERROR_RETURN 16405 (_soc_tr3_port_soft_reset(unit, port, pbt, TRUE)); 16406 /* disable port */ 16407 SOC_IF_ERROR_RETURN 16408 (_soc_tr3_subport_disable(unit, port, pbt, num_ports, TRUE)); 16409 /* clear ports mmu link list credit */ 16410 SOC_IF_ERROR_RETURN 16411 (soc_reg32_set(unit, 16412 lls_port_credit_reg[si->port_p2m_mapping[si->port_l2p_mapping[port]]], 16413 REG_PORT_ANY, 0, 0)); 16414 /* setup the port modes */ 16415 SOC_IF_ERROR_RETURN 16416 (_soc_tr3_port_mode_set(unit, port, pbt, lanes)); 16417 16418 SOC_IF_ERROR_RETURN(_soc_tr3_update_mcq_fifo(unit, prev_port_speeds)); 16419 16420 /* port reinit */ 16421 SOC_IF_ERROR_RETURN 16422 (_soc_tr3_port_control(unit, port, pbt, TRUE)); 16423 /* release port reset */ 16424 SOC_IF_ERROR_RETURN 16425 (_soc_tr3_port_soft_reset(unit, port, pbt, FALSE)); 16426 /* release egress buffer reset */ 16427 SOC_IF_ERROR_RETURN 16428 (_soc_tr3_egress_buffer_reset(unit, port, pbt, FALSE)); 16429 /* Enable new subports */ 16430 SOC_IF_ERROR_RETURN 16431 (_soc_tr3_subport_disable(unit, port, pbt, num_ports, FALSE)); 16432 16433 /* Enable egress cell request generation */ 16434 SOC_IF_ERROR_RETURN 16435 (READ_EGR_ENABLEm(unit, SOC_BLOCK_ANY, si->port_l2p_mapping[port], 16436 &egr_en)); 16437 soc_EGR_ENABLEm_field32_set(unit, &egr_en, PRT_ENABLEf, 1); 16438 SOC_IF_ERROR_RETURN 16439 (WRITE_EGR_ENABLEm(unit, SOC_BLOCK_ANY, si->port_l2p_mapping[port], 16440 &egr_en)); 16441 16442 return rv; 16443 } 16444 16445 int _soc_hx4_xmac_cclk_config(int unit) 16446 { 16447 int rv = SOC_E_NONE; 16448 uint32 rval; 16449 uint32 ndiv = 111, mdiv = 11; 16450 16451 16452 /* TOP_CORE_PLL_CTRL0 -> FAST_LOCK */ 16453 if (SOC_E_NONE != (rv = READ_TOP_CORE_PLL_CTRL0r(unit, &rval))) { 16454 return rv; 16455 } 16456 soc_reg_field_set(unit, TOP_CORE_PLL_CTRL0r, &rval, FAST_LOCKf, 1); 16457 if (SOC_E_NONE != (rv = WRITE_TOP_CORE_PLL_CTRL0r(unit, rval))) { 16458 return rv; 16459 } 16460 /* TOP_CORE_PLL_CTRL3 -> MSTR_NDIV_INTf */ 16461 if (SOC_E_NONE != (rv = READ_TOP_CORE_PLL_CTRL3r(unit, &rval))) { 16462 return rv; 16463 } 16464 soc_reg_field_set(unit, TOP_CORE_PLL_CTRL3r, &rval, MSTR_NDIV_INTf, ndiv); 16465 if (SOC_E_NONE != (rv = WRITE_TOP_CORE_PLL_CTRL3r(unit, rval))) { 16466 return rv; 16467 } 16468 /* TOP_CORE_PLL_CTRL4 -> MSTR_CH0_MDIVf */ 16469 if (SOC_E_NONE != (rv = READ_TOP_CORE_PLL_CTRL4r(unit, &rval))) { 16470 return rv; 16471 } 16472 soc_reg_field_set(unit, TOP_CORE_PLL_CTRL4r, &rval, MSTR_CH0_MDIVf, mdiv); 16473 if (SOC_E_NONE != (rv = WRITE_TOP_CORE_PLL_CTRL4r(unit, rval))) { 16474 return rv; 16475 } 16476 /* TOP_MISC_CONTROL -> CMIC_TO_CORE_PLL_LOAD */ 16477 if (SOC_E_NONE != (rv = READ_TOP_MISC_CONTROL_1r(unit, &rval))) { 16478 return rv; 16479 } 16480 soc_reg_field_set(unit, TOP_MISC_CONTROL_1r, &rval, 16481 CMIC_TO_CORE_PLL_LOADf, 1); 16482 if (SOC_E_NONE != (rv = WRITE_TOP_MISC_CONTROL_1r(unit, rval))) { 16483 return rv; 16484 } 16485 /* TOP_CORE_PLL_CTRL2 -> LOAD_EN_CH0 */ 16486 if (SOC_E_NONE != (rv = READ_TOP_CORE_PLL_CTRL2r(unit, &rval))) { 16487 return rv; 16488 } 16489 soc_reg_field_set(unit, TOP_CORE_PLL_CTRL2r, &rval, LOAD_EN_CH0f, 1); 16490 if (SOC_E_NONE != (rv = WRITE_TOP_CORE_PLL_CTRL2r(unit, rval))) { 16491 return rv; 16492 } 16493 16494 return rv; 16495 } 16496 16497 #if defined(SER_TR_TEST_SUPPORT) 16498 STATIC int 16499 _ser_tr3_parity_control_reg_set(int unit, 16500 ser_test_data_t *test_data, int enable) 16501 { 16502 16503 return _soc_tr3_parity_enable_all(unit, enable); 16504 } 16505 16506 STATIC void 16507 _soc_tr3_create_test_date(int unit, soc_mem_t mem, 16508 int block, int index, ser_test_data_t *test_data) 16509 { 16510 int ser_idx; 16511 soc_mem_t tcam_mem; 16512 soc_field_t test_field = VALIDf; 16513 soc_reg_t parity_enable_reg = CMIC_SER0_PROTECT_ADDR_RANGE_VALIDr; 16514 _soc_ser_parity_info_t *ser_tr3_info = _soc_tr3_ser_parity_info[unit]; 16515 #ifdef BCM_HELIX4_SUPPORT 16516 _soc_generic_ser_info_t *ser_hx4_info = _soc_hx4_tcam_ser_info[unit]; 16517 #endif /* BCM_HELIX4_SUPPORT */ 16518 16519 /*Search for TCAM memories*/ 16520 for (ser_idx = 0; ; ser_idx++) { 16521 #ifdef BCM_HELIX4_SUPPORT 16522 if (SOC_IS_HELIX4(unit)) { 16523 tcam_mem = ser_hx4_info[ser_idx].mem; 16524 } else 16525 #endif /* BCM_HELIX4_SUPPORT */ 16526 { 16527 tcam_mem = ser_tr3_info[ser_idx].mem; 16528 } 16529 16530 if (tcam_mem == INVALIDm) { 16531 break; 16532 } 16533 16534 if (tcam_mem != mem) { 16535 continue; 16536 } 16537 16538 if (mem == L3_DEFIPm) { 16539 test_field = VALID0f; 16540 } else if (mem == L3_DEFIP_PAIR_128m) { 16541 test_field = VALID0_LWRf; 16542 } else { 16543 test_field = VALIDf; 16544 } 16545 16546 #ifdef BCM_HELIX4_SUPPORT 16547 if (SOC_IS_HELIX4(unit)) { 16548 parity_enable_reg = SER_RANGE_ENABLEr; 16549 } else 16550 #endif /* BCM_HELIX4_SUPPORT */ 16551 { 16552 if (ser_tr3_info[ser_idx].cmic_ser_id) { 16553 parity_enable_reg = CMIC_SER1_PROTECT_ADDR_RANGE_VALIDr; 16554 } 16555 } 16556 16557 soc_ser_create_test_data(unit, test_data->entry_buf, test_data->field_buf, 16558 parity_enable_reg, ser_idx, INVALIDf, mem, 16559 test_field, block, REG_PORT_ANY, 16560 _SOC_ACC_TYPE_PIPE_ANY, index, test_data); 16561 16562 #ifdef BCM_HELIX4_SUPPORT 16563 if (SOC_IS_HELIX4(unit)) { 16564 ser_triumph3_test_fun.parity_control = &_ser_test_parity_control_reg_set; 16565 } else 16566 #endif /* BCM_HELIX4_SUPPORT */ 16567 { 16568 ser_triumph3_test_fun.parity_control = &_ser_test_parity_control_pci_write; 16569 } 16570 16571 return; 16572 } 16573 16574 soc_ser_create_test_data(unit, test_data->entry_buf, test_data->field_buf, 16575 INVALIDr, SOC_INVALID_TCAM_PARITY_BIT, 16576 INVALIDr, mem, EVEN_PARITYf, block, 16577 REG_PORT_ANY, _SOC_ACC_TYPE_PIPE_ANY, 16578 index, test_data); 16579 16580 ser_triumph3_test_fun.parity_control = &_ser_tr3_parity_control_reg_set; 16581 16582 return; 16583 16584 } 16585 16586 const soc_mem_t _tr3_skipped_mems[] = { 16587 AXP_WRX_SVP_ASSIGNMENTm, 16588 AXP_WRX_WCDm, 16589 AXP_WTX_DSCP_MAPm, 16590 AXP_WTX_DVP_PROFILEm, 16591 AXP_WTX_PRI_MAPm, 16592 AXP_WTX_TRUNK_BLOCK_MASKm, 16593 AXP_WTX_TRUNK_GROUP_BITMAPm, 16594 AXP_WTX_TUNNELm,/*AXP memories ser action cannot be triggered*/ 16595 FT_POLICYm,/*the reg is not enable*/ 16596 RTAG7_PORT_BASED_HASHm, /*The field RTAG7_PORT_BASED_HASH_PARITY_ENf is not enabled*/ 16597 PORT_OR_TRUNK_MAC_LIMITm,/*This memories isnot used*/ 16598 INVALIDm 16599 }; 16600 16601 /* 16602 * Function: 16603 * soc_tr3_ser_error_injection_support 16604 * Purpose: 16605 * Checks if a memory is supported by error injection interface 16606 */ 16607 soc_error_t 16608 soc_tr3_ser_error_injection_support (int unit, soc_mem_t mem, 16609 int pipe) 16610 { 16611 int i; 16612 int ser_idx; 16613 soc_mem_t tcam_mem; 16614 _soc_ser_parity_info_t *ser_tr3_info = _soc_tr3_ser_parity_info[unit]; 16615 #ifdef BCM_HELIX4_SUPPORT 16616 _soc_generic_ser_info_t *ser_hx4_info = _soc_hx4_tcam_ser_info[unit]; 16617 #endif /* BCM_HELIX4_SUPPORT */ 16618 16619 for (i = 0; _tr3_skipped_mems[i] != INVALIDm; i++) { 16620 if (mem == _tr3_skipped_mems[i]) { 16621 return SOC_E_UNAVAIL; 16622 } 16623 } 16624 16625 if ((!soc_mem_is_valid(unit, mem)) || 16626 (!soc_mem_is_cachable(unit, mem)) || 16627 (!soc_mem_cache_get(unit, mem, MEM_BLOCK_ALL))) { 16628 16629 return SOC_E_UNAVAIL; 16630 } 16631 16632 if (soc_mem_index_max(unit, mem) <= 0) 16633 { 16634 return SOC_E_UNAVAIL; 16635 } 16636 16637 if (soc_mem_is_cam(unit, mem)) 16638 { 16639 for (ser_idx = 0; ; ser_idx++) { 16640 #ifdef BCM_HELIX4_SUPPORT 16641 if (SOC_IS_HELIX4(unit)) { 16642 tcam_mem = ser_hx4_info[ser_idx].mem; 16643 } else 16644 #endif /* BCM_HELIX4_SUPPORT */ 16645 { 16646 tcam_mem = ser_tr3_info[ser_idx].mem; 16647 } 16648 16649 if (tcam_mem == INVALIDm) { 16650 return SOC_E_UNAVAIL; 16651 } 16652 16653 if (tcam_mem == mem) { 16654 return SOC_E_NONE; 16655 } 16656 } 16657 } 16658 16659 return SOC_E_NONE; 16660 } 16661 16662 const soc_mem_t _tr3_ecc_mems[] = { 16663 LPORT_TABm, 16664 PORT_TABm, 16665 SOURCE_TRUNK_MAP_TABLEm, 16666 INVALIDm 16667 }; 16668 16669 /* 16670 * Function: 16671 * soc_tr3_ser_inject_error 16672 * Purpose: 16673 * Injects an error into a single tr3 memory 16674 */ 16675 soc_error_t 16676 soc_tr3_ser_inject_error (int unit, uint32 flags, soc_mem_t mem, 16677 int pipe_target, int block, int index) 16678 { 16679 int i; 16680 ser_test_data_t test_data; 16681 uint32 tmp_entry[SOC_MAX_MEM_WORDS], field_data[SOC_MAX_MEM_FIELD_WORDS]; 16682 16683 /* Check if memory needs to be skipped */ 16684 if (ser_triumph3_test_fun.injection_support) { 16685 SOC_IF_ERROR_RETURN( 16686 soc_tr3_ser_error_injection_support(unit, mem, pipe_target)); 16687 } 16688 16689 test_data.entry_buf = tmp_entry; 16690 test_data.field_buf = field_data; 16691 16692 for (i = 0; _tr3_ecc_mems[i] != INVALIDm; i++) { 16693 if (mem == _tr3_ecc_mems[i]) { 16694 flags |= SOC_INJECT_ERROR_2BIT_ECC; 16695 } 16696 } 16697 16698 _soc_tr3_create_test_date(unit, mem, block, index, &test_data); 16699 SOC_IF_ERROR_RETURN(soc_mem_parity_control(unit, INVALIDm, COPYNO_ALL, 0)); 16700 /* Disable parity */ 16701 SOC_IF_ERROR_RETURN(_ser_test_parity_control(unit, &test_data, 0)); 16702 /* Read the memory (required for successful injection) */ 16703 SOC_IF_ERROR_RETURN(ser_test_mem_read(unit, 0, &test_data)); 16704 /* Inject error */ 16705 SOC_IF_ERROR_RETURN(soc_ser_test_inject_full(unit, flags, &test_data)); 16706 /* Enable parity */ 16707 SOC_IF_ERROR_RETURN(_ser_test_parity_control(unit, &test_data, 1)); 16708 SOC_IF_ERROR_RETURN(soc_mem_parity_control(unit, INVALIDm, COPYNO_ALL, 1)); 16709 16710 return SOC_E_NONE; 16711 } 16712 16713 /* 16714 * Function: 16715 * soc_tr3_ser_test_mem 16716 * Purpose: 16717 * Perform SER test on a single memory, or generate a test the user can 16718 * enter by the command line. 16719 */ 16720 soc_error_t 16721 soc_tr3_ser_test_mem(int unit, soc_mem_t mem, _soc_ser_test_t test_type, 16722 int cmd) 16723 { 16724 soc_error_t rv; 16725 int error_count = 0; 16726 ser_test_data_t test_data; 16727 uint32 tmp_entry[SOC_MAX_MEM_WORDS], field_data[SOC_MAX_MEM_FIELD_WORDS]; 16728 16729 test_data.entry_buf = tmp_entry; 16730 test_data.field_buf = field_data; 16731 16732 /* Check if memory needs to be skipped */ 16733 if (ser_triumph3_test_fun.injection_support) { 16734 SOC_IF_ERROR_RETURN( 16735 soc_tr3_ser_error_injection_support(unit, mem, _SOC_ACC_TYPE_PIPE_ANY)); 16736 } 16737 16738 _soc_tr3_create_test_date(unit, mem, MEM_BLOCK_ANY, 0, &test_data); 16739 SOC_IF_ERROR_RETURN(soc_mem_parity_control(unit, INVALIDm, COPYNO_ALL, 0)); 16740 rv = ser_test_mem(unit, 0, &test_data, test_type, &error_count); 16741 SOC_IF_ERROR_RETURN(soc_mem_parity_control(unit, INVALIDm, COPYNO_ALL, 1)); 16742 16743 if (error_count != 0) { 16744 LOG_CLI((BSL_META_U(unit,"SER test failed for memory:%s.\n"), SOC_MEM_NAME(unit, mem))); 16745 } 16746 else{ 16747 LOG_CLI((BSL_META_U(unit,"SER test PASSED for memory:%s.\n"), SOC_MEM_NAME(unit, mem))); 16748 } 16749 16750 return rv; 16751 } 16752 16753 16754 /* 16755 * Function: 16756 * soc_tr3_ser_test 16757 * Purpose: 16758 * Tests that SER is working for all supported memories. 16759 */ 16760 soc_error_t 16761 soc_tr3_ser_test (int unit, _soc_ser_test_t test_type) 16762 { 16763 soc_mem_t mem; 16764 int error_count = 0; 16765 int test_count = 0; 16766 ser_test_data_t test_data; 16767 uint32 tmp_entry[SOC_MAX_MEM_WORDS], field_data[SOC_MAX_MEM_FIELD_WORDS]; 16768 16769 test_data.entry_buf = tmp_entry; 16770 test_data.field_buf = field_data; 16771 16772 SOC_IF_ERROR_RETURN(soc_mem_parity_control(unit, INVALIDm, COPYNO_ALL, 0)); 16773 16774 for (mem = 0; mem < NUM_SOC_MEM; mem++) { 16775 if (SOC_FAILURE(soc_tr3_ser_error_injection_support(unit, mem, _SOC_ACC_TYPE_PIPE_ANY))){ 16776 continue; 16777 } 16778 16779 test_count++; 16780 _soc_tr3_create_test_date(unit, mem, MEM_BLOCK_ANY, 0, &test_data); 16781 ser_test_mem(unit, 0, &test_data, test_type, &error_count); 16782 } 16783 16784 SOC_IF_ERROR_RETURN(soc_mem_parity_control(unit, INVALIDm, COPYNO_ALL, 1)); 16785 16786 if (error_count != 0) { 16787 LOG_CLI((BSL_META_U(unit,"TR 144 test failed, failed cases:%d, test all:%d.\n"), error_count, test_count)); 16788 return SOC_E_FAIL; 16789 } 16790 16791 LOG_CLI((BSL_META_U(unit,"TR 144 test passed:%d.\n"), test_count)); 16792 return SOC_E_NONE; 16793 } 16794 16795 #endif /*defined(SER_TR_TEST_SUPPORT*/ 16796 16797 STATIC int 16798 _soc_tr3_tdm_store(int unit) 16799 { 16800 /* update the table values */ 16801 uint8 cur_cal; 16802 uint32 rval; 16803 int start_index, end_index; 16804 16805 /* Determine current calendar */ 16806 SOC_IF_ERROR_RETURN(READ_LLS_TDM_STATUSr(unit, &rval)); 16807 cur_cal = (soc_reg_field_get(unit, LLS_TDM_STATUSr, rval, CURRENT_CALENDARf)) & 1; 16808 16809 if(cur_cal == 0){ 16810 start_index = 0; 16811 end_index = 511; 16812 } 16813 else{ 16814 start_index = 512; 16815 end_index = 1023; 16816 } 16817 16818 SOC_IF_ERROR_RETURN(soc_mem_read_range(unit, LLS_PORT_TDMm, MEM_BLOCK_ANY, 16819 start_index, end_index, _soc_tr3_lls_port_tdm[unit])); 16820 16821 return soc_mem_read_range(unit, IARB_TDM_TABLEm, MEM_BLOCK_ANY, 16822 soc_mem_index_min(unit, IARB_TDM_TABLEm), 16823 soc_mem_index_max(unit, IARB_TDM_TABLEm), 16824 _soc_tr3_iarb_tdm[unit]); 16825 } 16826 16827 STATIC int 16828 _soc_tr3_tdm_restore(int unit) 16829 { 16830 /* update the table values */ 16831 int iter = 0; 16832 uint8 new_cal; 16833 uint32 rval, rval_iarb; 16834 int start_index, end_index; 16835 16836 SOC_IF_ERROR_RETURN(READ_IARB_TDM_CONTROLr(unit, &rval_iarb)); 16837 soc_reg_field_set(unit, IARB_TDM_CONTROLr, &rval_iarb, DISABLEf, 1); 16838 soc_reg_field_set(unit, IARB_TDM_CONTROLr, &rval_iarb, TDM_WRAP_PTRf, 16839 (_soc_tr3_tdm_size -1)); 16840 SOC_IF_ERROR_RETURN(WRITE_IARB_TDM_CONTROLr(unit, rval_iarb)); 16841 16842 SOC_IF_ERROR_RETURN(soc_mem_write_range(unit, IARB_TDM_TABLEm, MEM_BLOCK_ANY, 16843 soc_mem_index_min(unit, IARB_TDM_TABLEm), 16844 soc_mem_index_max(unit, IARB_TDM_TABLEm), 16845 _soc_tr3_iarb_tdm[unit])); 16846 if (SAL_BOOT_BCMSIM) { 16847 soc_reg_field_set(unit, IARB_TDM_CONTROLr, &rval_iarb, DISABLEf, 1); 16848 } else { 16849 soc_reg_field_set(unit, IARB_TDM_CONTROLr, &rval_iarb, DISABLEf, 0); 16850 } 16851 soc_reg_field_set(unit, IARB_TDM_CONTROLr, &rval_iarb, AUX_CMICM_SLOT_ENf, 1); 16852 soc_reg_field_set(unit, IARB_TDM_CONTROLr, &rval_iarb, AUX_AXP_SLOT_ENf, 1); 16853 SOC_IF_ERROR_RETURN(WRITE_IARB_TDM_CONTROLr(unit, rval_iarb)); 16854 16855 /* Determine current calendar */ 16856 SOC_IF_ERROR_RETURN(READ_LLS_TDM_STATUSr(unit, &rval)); 16857 new_cal = ~(soc_reg_field_get(unit, LLS_TDM_STATUSr, rval, CURRENT_CALENDARf)) & 1; 16858 16859 if(new_cal == 0){ 16860 start_index = 0; 16861 end_index = 511; 16862 } 16863 else{ 16864 start_index = 512; 16865 end_index = 1023; 16866 } 16867 16868 SOC_IF_ERROR_RETURN(soc_mem_write_range(unit, LLS_PORT_TDMm, MEM_BLOCK_ANY, 16869 start_index, end_index, _soc_tr3_lls_port_tdm[unit])); 16870 16871 /* Switch LLS calendar */ 16872 SOC_IF_ERROR_RETURN(WRITE_LLS_TDM_CAL_CFG_SWITCHr(unit, 1)); 16873 do { 16874 SOC_IF_ERROR_RETURN(READ_LLS_TDM_STATUSr(unit, &rval)); 16875 sal_udelay(100); 16876 } while ((iter++ < 100000) && 16877 (soc_reg_field_get(unit, LLS_TDM_STATUSr, rval, 16878 CURRENT_CALENDARf) != new_cal) && 16879 !(SAL_BOOT_BCMSIM || SAL_BOOT_PLISIM)); 16880 if (iter >= 100000) { 16881 LOG_ERROR(BSL_LS_SOC_COMMON, 16882 (BSL_META_U(unit, 16883 "LLS Calendar switch failed !!\n"))); 16884 return SOC_E_INTERNAL; 16885 } 16886 SOC_IF_ERROR_RETURN(WRITE_LLS_TDM_CAL_CFG_SWITCHr(unit, 0)); 16887 return SOC_E_NONE; 16888 } 16889 16890 16891 int 16892 soc_tr3_mmu_register_store(int unit) 16893 { 16894 int port, idx, mmu_port, phy_port; 16895 soc_info_t *si = &SOC_INFO(unit); 16896 _soc_tr3_mmu_data_t *mmu_data; 16897 16898 _soc_tr3_current_port_speeds(unit, _soc_prev_port_speeds); 16899 mmu_data = (_soc_tr3_mmu_data_t *) _soc_tr3_mmu_data[unit]; 16900 if(mmu_data == NULL) { 16901 LOG_ERROR(BSL_LS_SOC_COMMON, 16902 (BSL_META_U(unit, 16903 "NULL pointer for MMU data\n"))); 16904 return SOC_E_INTERNAL; 16905 } 16906 16907 for (idx = 0; idx < 2; idx++) { 16908 SOC_IF_ERROR_RETURN(READ_WAMU_PG_MIN_CELLr(unit, idx, 16909 &mmu_data->_soc_tr3_wamu_pg_min_cell[idx])); 16910 SOC_IF_ERROR_RETURN(READ_WAMU_PG_RESET_OFFSET_CELLr(unit, idx, 16911 &mmu_data->_soc_tr3_wamu_pg_reset_offset_cell[idx])); 16912 SOC_IF_ERROR_RETURN(READ_WAMU_PG_SHARED_LIMIT_CELLr(unit, idx, 16913 &mmu_data->_soc_tr3_wamu_pg_shared_limit_cell[idx])); 16914 SOC_IF_ERROR_RETURN(READ_WAMUMINLMTPGr(unit, idx, 16915 &mmu_data->_soc_tr3_wamuminlmtpg[idx])); 16916 SOC_IF_ERROR_RETURN(READ_WAMUSHRLMTCELLPGr(unit, idx, 16917 &mmu_data->_soc_tr3_wamushrlmtcellpg[idx])); 16918 SOC_IF_ERROR_RETURN(READ_WAMU_PG_RESET_FLOOR_CELLr(unit, idx, 16919 &mmu_data->_soc_tr3_wamu_pg_reset_floor_cell[idx])); 16920 SOC_IF_ERROR_RETURN(READ_WAMURSTOFFSETCELLPGr(unit, idx, 16921 &mmu_data->_soc_tr3_wamurstoffsetcellpg[idx])); 16922 SOC_IF_ERROR_RETURN(READ_WAMURSTOFFSETPKTPGr(unit, idx, 16923 &mmu_data->_soc_tr3_wamurstoffsetpktpg[idx])); 16924 SOC_IF_ERROR_RETURN(READ_WAMUSHRLMTPKTPGr(unit, idx, 16925 &mmu_data->_soc_tr3_wamushrlmtpktpg[idx])); 16926 SOC_IF_ERROR_RETURN(READ_WAMU_PG_FIRST_FRAGMENT_DROP_OFFSETr(unit, idx, 16927 &mmu_data->_soc_tr3_wamu_pg_first_fragment_drop_offset[idx])); 16928 } 16929 16930 for (idx = 0; idx < 4; idx++) { 16931 SOC_IF_ERROR_RETURN (READ_BUFFER_CELL_LIMIT_SPr( 16932 unit, idx, 16933 &mmu_data->_soc_tr3_buffer_cell_limit_sp[idx])); 16934 SOC_IF_ERROR_RETURN (READ_CELL_RESET_LIMIT_OFFSET_SPr( 16935 unit, idx, 16936 &mmu_data->_soc_tr3_cell_reset_limit_offset_sp[idx])); 16937 SOC_IF_ERROR_RETURN (READ_CELL_SPAP_YELLOW_OFFSET_SPr( 16938 unit, idx, 16939 &mmu_data->_soc_tr3_cell_spap_yellow_offset_sp[idx])); 16940 SOC_IF_ERROR_RETURN(READ_CELL_SPAP_RED_OFFSET_SPr( 16941 unit, idx, 16942 &mmu_data->_soc_tr3_cell_spap_red_offset_sp[idx])); 16943 SOC_IF_ERROR_RETURN(READ_CONGESTION_STATE_BYTESr(unit, idx, 16944 &mmu_data->_soc_tr3_congestion_state_bytes[idx])); 16945 SOC_IF_ERROR_RETURN(READ_E2EFC_RMOD_CFGr(unit, idx, 16946 &mmu_data->_soc_tr3_e2efc_rmod_cfg[idx])); 16947 SOC_IF_ERROR_RETURN(READ_E2EFC_RX_RMT_TIMEOUTr(unit, idx, 16948 &mmu_data->_soc_tr3_e2efc_rx_rmt_timeout[idx])); 16949 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, OP_BUFFER_LIMIT_RED_CELLr, 16950 REG_PORT_ANY, idx, 16951 &mmu_data->_soc_tr3_op_buffer_limit_red_cell[idx])); 16952 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, OP_BUFFER_LIMIT_RESUME_RED_CELLr, 16953 REG_PORT_ANY, idx, 16954 &mmu_data->_soc_tr3_op_buffer_limit_resume_red_cell[idx])); 16955 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, OP_BUFFER_LIMIT_RESUME_YELLOW_CELLr, 16956 REG_PORT_ANY, idx, 16957 &mmu_data->_soc_tr3_op_buffer_limit_resume_yellow_cell[idx])); 16958 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, OP_BUFFER_LIMIT_YELLOW_CELLr, 16959 REG_PORT_ANY, idx, 16960 &mmu_data->_soc_tr3_op_buffer_limit_yellow_cell[idx])); 16961 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, OP_BUFFER_SHARED_LIMIT_CELLr, 16962 REG_PORT_ANY, idx, 16963 &mmu_data->_soc_tr3_op_buffer_shared_limit_cell[idx])); 16964 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, OP_BUFFER_SHARED_LIMIT_RESUME_CELLr, 16965 REG_PORT_ANY, idx, 16966 &mmu_data->_soc_tr3_op_buffer_shared_limit_resume_cell[idx])); 16967 SOC_IF_ERROR_RETURN(READ_OP_MC_SP_BST_THRESHOLDr(unit, idx, 16968 &mmu_data->_soc_tr3_op_mc_sp_bst_threshold[idx])); 16969 SOC_IF_ERROR_RETURN(READ_OP_MCUC_SP_BST_THRESHOLDr(unit, idx, 16970 &mmu_data->_soc_tr3_op_mcuc_sp_bst_threshold[idx])); 16971 } 16972 16973 for (idx = 0; idx < 5; idx++) { 16974 SOC_IF_ERROR_RETURN(READ_THDI_BST_PROFILE_THRESH_SPr(unit, idx, 16975 &mmu_data->_soc_tr3_thdi_bst_profile_thresh_sp[idx])); 16976 } 16977 16978 for (idx = 0; idx < 7; idx++) { 16979 SOC_IF_ERROR_RETURN(READ_E2ECC_TX_ENABLE_BMPr(unit, idx, 16980 &mmu_data->_soc_tr3_e2ecc_tx_enable_bmp[idx])); 16981 SOC_IF_ERROR_RETURN(READ_E2EFC_MAX_TX_TIMERr(unit, idx, 16982 &mmu_data->_soc_tr3_e2efc_max_tx_timer[idx])); 16983 SOC_IF_ERROR_RETURN(READ_E2EFC_MIN_TX_TIMERr(unit, idx, 16984 &mmu_data->_soc_tr3_e2efc_min_tx_timer[idx])); 16985 } 16986 16987 for (idx = 0; idx < 8; idx++) { 16988 SOC_IF_ERROR_RETURN(READ_OP_CPU_QUEUE_BST_THRESHOLD_PROFILEr(unit, idx, 16989 &mmu_data->_soc_tr3_op_cpu_queue_bst_threshold_profile[idx])); 16990 SOC_IF_ERROR_RETURN(READ_OP_RESUME_OFFSET_COLOR_CELL_PROFILEr(unit, idx, 16991 &mmu_data->_soc_tr3_op_resume_offset_color_cell_profile[idx])); 16992 SOC_IF_ERROR_RETURN(READ_OP_UC_PORT_BST_THRESHOLDr(unit, idx, 16993 &mmu_data->_soc_tr3_op_uc_port_bst_threshold[idx])); 16994 SOC_IF_ERROR_RETURN(READ_OP_UC_QGROUP_BST_THRESHOLDr(unit, idx, 16995 &mmu_data->_soc_tr3_op_uc_qgroup_bst_threshold[idx])); 16996 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, OP_UC_QUEUE_BST_THRESHOLDr, 16997 REG_PORT_ANY, idx, 16998 &mmu_data->_soc_tr3_op_uc_queue_bst_threshold[idx])); 16999 SOC_IF_ERROR_RETURN(READ_THDI_BST_PROFILE_THRESH_PG_HDRMr(unit, 17000 idx, &mmu_data->_soc_tr3_thdi_bst_profile_thresh_pg_hdrm[idx])); 17001 SOC_IF_ERROR_RETURN(READ_THDI_BST_PROFILE_THRESH_PG_SHAREDr(unit, 17002 idx, &mmu_data->_soc_tr3_thdi_bst_profile_thresh_pg_shared[idx])); 17003 SOC_IF_ERROR_RETURN(READ_THDI_BST_PROFILE_THRESH_PORT_SHAREDr(unit, 17004 idx, &mmu_data->_soc_tr3_thdi_bst_profile_thresh_port_shared[idx])); 17005 if (!SOC_IS_MONTEREY(unit)) { 17006 SOC_IF_ERROR_RETURN(READ_TX_CNT_CONFIGr_REG32(unit, idx, 17007 &mmu_data->_soc_tr3_tx_cnt_config[idx])); 17008 } 17009 SOC_IF_ERROR_RETURN(READ_WAMUDROPCNTTHDOBYTEr(unit, idx, 17010 &mmu_data->_soc_tr3_wamudropcntthdobyte[idx])); 17011 SOC_IF_ERROR_RETURN(READ_WAMUMINLMTPKTQr(unit, idx, 17012 &mmu_data->_soc_tr3_wamuminlmtpktq[idx])); 17013 SOC_IF_ERROR_RETURN(READ_WAMURSTOFFSETPKTQr(unit, idx, 17014 &mmu_data->_soc_tr3_wamurstoffsetpktq[idx])); 17015 SOC_IF_ERROR_RETURN(READ_WAMUSHRLMTPKTQr(unit, idx, 17016 &mmu_data->_soc_tr3_wamushrlmtpktq[idx])); 17017 SOC_IF_ERROR_RETURN(READ_MMU_QCN_CPQ_SEQr(unit, idx, 17018 &mmu_data->_soc_tr3_mmu_qcn_cpq_seq[idx])); 17019 SOC_IF_ERROR_RETURN(READ_WAMUDROPCNTTHDOPKTr(unit, idx, 17020 &mmu_data->_soc_tr3_wamudropcntthdopkt[idx])); 17021 } 17022 for (idx = 0; idx < 16; idx++) { 17023 SOC_IF_ERROR_RETURN(READ_CFAPBANKFULLr(unit, idx, 17024 &mmu_data->_soc_tr3_cfapbankfull[idx])); 17025 SOC_IF_ERROR_RETURN(READ_PRIO2COS_PROFILE0r(unit, idx, 17026 &mmu_data->_soc_tr3_prio2cos_profile0[idx])); 17027 SOC_IF_ERROR_RETURN(READ_PRIO2COS_PROFILE1r(unit, idx, 17028 &mmu_data->_soc_tr3_prio2cos_profile1[idx])); 17029 SOC_IF_ERROR_RETURN(READ_PRIO2COS_PROFILE2r(unit, idx, 17030 &mmu_data->_soc_tr3_prio2cos_profile2[idx])); 17031 SOC_IF_ERROR_RETURN(READ_PRIO2COS_PROFILE3r(unit, idx, 17032 &mmu_data->_soc_tr3_prio2cos_profile3[idx])); 17033 SOC_IF_ERROR_RETURN(READ_SRC_MOD_IDr(unit, idx, 17034 &mmu_data->_soc_tr3_src_mod_id[idx])); 17035 } 17036 17037 for (idx = 0; idx < 63; idx++) { 17038 SOC_IF_ERROR_RETURN(READ_MMU_TO_LOGIC_PORT_MAPPINGr(unit, idx, 17039 &mmu_data->_soc_tr3_mmu_to_logic_port_mapping[idx])); 17040 SOC_IF_ERROR_RETURN(READ_MMU_TO_PHY_PORT_MAPPINGr(unit, idx, 17041 &mmu_data->_soc_tr3_mmu_to_phy_port_mapping[idx])); 17042 } 17043 17044 for (idx = 0; idx < 64; idx++) { 17045 SOC_IF_ERROR_RETURN(READ_E2EFC_CNT_ATTRr(unit, idx, 17046 &mmu_data->_soc_tr3_e2efc_cnt_attr[idx])); 17047 SOC_IF_ERROR_RETURN(READ_E2EFC_CNT_RESET_LIMITr(unit, idx, 17048 &mmu_data->_soc_tr3_e2efc_cnt_reset_limit[idx])); 17049 SOC_IF_ERROR_RETURN(READ_E2EFC_CNT_SET_LIMITr(unit, idx, 17050 &mmu_data->_soc_tr3_e2efc_cnt_set_limit[idx])); 17051 SOC_IF_ERROR_RETURN(READ_E2EFC_CNT_VALr(unit, idx, 17052 &mmu_data->_soc_tr3_e2efc_cnt_val[idx])); 17053 SOC_IF_ERROR_RETURN(READ_PRIO2COS_PROFILEr(unit, idx, 17054 &mmu_data->_soc_tr3_prio2cos_profile[idx])); 17055 } 17056 17057 PBMP_ALL_ITER(unit, port) { 17058 if (port != 0){ 17059 SOC_IF_ERROR_RETURN(READ_DEQ_AGINGMASKr(unit, port, 17060 &mmu_data->_soc_tr3_deq_agingmask[port])); 17061 } 17062 SOC_IF_ERROR_RETURN(READ_DROP_BYTE_CNT_ING_64r(unit, port, 17063 &mmu_data->_soc_tr3_drop_byte_cnt_ing_64[port])); 17064 SOC_IF_ERROR_RETURN(READ_DROP_PKT_CNT_INGr(unit, port, 17065 &mmu_data->_soc_tr3_drop_pkt_cnt_ing[port])); 17066 SOC_IF_ERROR_RETURN(READ_DROP_PKT_CNT_OVQr(unit, port, 17067 &mmu_data->_soc_tr3_drop_pkt_cnt_ovq[port])); 17068 SOC_IF_ERROR_RETURN(READ_EGRMETERINGCONFIG_64r(unit, port, 17069 &mmu_data->_soc_tr3_egrmeteringconfig_64[port])); 17070 SOC_IF_ERROR_RETURN(READ_MTRI_IFGr(unit, port, 17071 &mmu_data->_soc_tr3_mtri_ifg[port])); 17072 SOC_IF_ERROR_RETURN(READ_OP_PORT_CONFIG1_CELLr(unit, port, 17073 &mmu_data->_soc_tr3_op_port_config1_cell[port])); 17074 SOC_IF_ERROR_RETURN(READ_PORT_MAX_PKT_SIZEr(unit, port, 17075 &mmu_data->_soc_tr3_port_max_pkt_size[port])); 17076 SOC_IF_ERROR_RETURN(READ_PORT_PG_SPIDr(unit, port, 17077 &mmu_data->_soc_tr3_port_pg_spid[port])); 17078 SOC_IF_ERROR_RETURN(READ_PORT_PRI_GRP0r(unit, port, 17079 &mmu_data->_soc_tr3_port_pri_grp0[port])); 17080 SOC_IF_ERROR_RETURN(READ_PORT_PRI_GRP1r(unit, port, 17081 &mmu_data->_soc_tr3_port_pri_grp1[port])); 17082 SOC_IF_ERROR_RETURN(READ_PORT_PRI_XON_ENABLEr(unit, port, 17083 &mmu_data->_soc_tr3_port_pri_xon_enable[port])); 17084 SOC_IF_ERROR_RETURN(READ_THDO_PORT_E2ECC_COS_SPIDr(unit, port, 17085 &mmu_data->_soc_tr3_thdo_port_e2ecc_cos_spid[port])); 17086 SOC_IF_ERROR_RETURN(READ_BKPMETERINGCONFIG_64r(unit, port, 17087 &mmu_data->_soc_tr3_bkpmeteringconfig_64[port])); 17088 SOC_IF_ERROR_RETURN(READ_ING_COS_MODEr(unit, port, 17089 &mmu_data->_soc_tr3_ing_cos_mode[port])); 17090 } 17091 17092 for (idx = 0; idx < 8; idx++) { 17093 SOC_IF_ERROR_RETURN(READ_MCQ_FIFO_BASE_REG_56r(unit, 58, idx, 17094 &mmu_data->_soc_tr3_mcq_fifo_base_reg_56[idx])); 17095 SOC_IF_ERROR_RETURN(READ_MCQ_FIFO_BASE_REG_PASSTHRUr(unit, 61, idx, 17096 &mmu_data->_soc_tr3_mcq_fifo_base_reg_passthru[idx])); 17097 } 17098 17099 for (idx = 0; idx < 48; idx++) { 17100 SOC_IF_ERROR_RETURN(READ_MCQ_FIFO_BASE_REG_CPUr(unit, 0, idx, 17101 &mmu_data->_soc_tr3_mcq_fifo_base_reg_cpu[idx])); 17102 } 17103 17104 PBMP_ALL_ITER(unit, port) { 17105 phy_port = si->port_l2p_mapping[port]; 17106 if(phy_port == -1) { 17107 continue; 17108 } 17109 mmu_port = si->port_p2m_mapping[phy_port]; 17110 17111 for (idx = 0; idx < 4; idx++) { 17112 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, OP_PORT_CONFIG_CELLr, 17113 port, idx, 17114 &mmu_data->_soc_tr3_op_port_config_cell[port][idx])); 17115 SOC_IF_ERROR_RETURN (READ_OP_PORT_LIMIT_COLOR_CELLr( 17116 unit, port, idx, 17117 &mmu_data->_soc_tr3_op_port_limit_color_cell[port][idx])); 17118 SOC_IF_ERROR_RETURN (READ_OP_PORT_LIMIT_RESUME_COLOR_CELLr( 17119 unit, port, idx, 17120 &mmu_data->_soc_tr3_op_port_limit_resume_color_cell[port][idx])); 17121 } 17122 for (idx = 0; idx < 8; idx++) { 17123 if ((mmu_port >= 32) && (mmu_port <= 35)) { 17124 SOC_IF_ERROR_RETURN(READ_MCQ_FIFO_BASE_REG_32_35r(unit, 17125 port, idx, 17126 &mmu_data->_soc_tr3_mcq_fifo_base_reg_32_35[mmu_port-32][idx])); 17127 } 17128 if ((mmu_port >= 36) && (mmu_port <= 39)) { 17129 SOC_IF_ERROR_RETURN(READ_MCQ_FIFO_BASE_REG_36_39r(unit, 17130 port, idx, 17131 &mmu_data->_soc_tr3_mcq_fifo_base_reg_36_39[mmu_port-36][idx])); 17132 } 17133 } 17134 for (idx = 0; idx < 10; idx++) { 17135 if ((mmu_port >= 40) && (mmu_port <= 47)) { 17136 SOC_IF_ERROR_RETURN(READ_MCQ_FIFO_BASE_REGr(unit, 17137 port, idx, 17138 &mmu_data->_soc_tr3_mcq_fifo_base_reg[mmu_port-40][idx])); 17139 } 17140 if ((mmu_port >= 48) && (mmu_port <= 55)) { 17141 SOC_IF_ERROR_RETURN(READ_MCQ_FIFO_BASE_REG_48_55r(unit, 17142 port, idx, 17143 &mmu_data->_soc_tr3_mcq_fifo_base_reg_48_55[mmu_port-48][idx])); 17144 } 17145 } 17146 17147 for (idx = 0; idx < 48; idx++) { 17148 SOC_IF_ERROR_RETURN (READ_OP_QUEUE_CONFIG_CELLr( 17149 unit, port, idx, 17150 &mmu_data->_soc_tr3_op_queue_config_cell[port][idx])); 17151 SOC_IF_ERROR_RETURN (READ_OP_QUEUE_CONFIG1_CELLr( 17152 unit, port, idx, 17153 &mmu_data->_soc_tr3_op_queue_config1_cell[port][idx])); 17154 SOC_IF_ERROR_RETURN (READ_OP_QUEUE_LIMIT_COLOR_CELLr( 17155 unit, port, idx, 17156 &mmu_data->_soc_tr3_op_queue_limit_color_cell[port][idx])); 17157 SOC_IF_ERROR_RETURN (READ_OP_QUEUE_RESET_OFFSET_CELLr( 17158 unit, port, idx, 17159 &mmu_data->_soc_tr3_op_queue_reset_offset_cell[port][idx])); 17160 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_LIMIT_RESUME_COLOR_CELLr( 17161 unit, port, idx, 17162 &mmu_data->_soc_tr3_op_queue_limit_resume_color_cell[port][idx])); 17163 SOC_IF_ERROR_RETURN(READ_OP_CPU_QUEUE_BST_THRESHOLDr(unit, 17164 port, idx, 17165 &mmu_data->_soc_tr3_op_cpu_queue_bst_threshold[port][idx])); 17166 } 17167 } 17168 17169 SOC_IF_ERROR_RETURN(READ_BST_TRACKING_CONFIGr(unit, 17170 &mmu_data->_soc_tr3_bst_tracking_config)); 17171 SOC_IF_ERROR_RETURN(READ_BST_TRACKING_ENABLEr(unit, 17172 &mmu_data->_soc_tr3_bst_tracking_enable)); 17173 SOC_IF_ERROR_RETURN(READ_BUFFER_CELL_LIMIT_SP_SHAREDr(unit, 17174 &mmu_data->_soc_tr3_buffer_cell_limit_sp_shared)); 17175 SOC_IF_ERROR_RETURN(READ_CFAPBSTTHRSr(unit, 17176 &mmu_data->_soc_tr3_cfapbstthrs)); 17177 SOC_IF_ERROR_RETURN(READ_CFAPCONFIGr(unit, 17178 &mmu_data->_soc_tr3_cfapconfig)); 17179 SOC_IF_ERROR_RETURN(READ_CFAPFULLTHRESHOLDr(unit, 17180 &mmu_data->_soc_tr3_cfapfullthreshold)); 17181 SOC_IF_ERROR_RETURN(READ_CH_BASE_EXPECTEDr(unit, 17182 &mmu_data->_soc_tr3_ch_base_expected)); 17183 SOC_IF_ERROR_RETURN(READ_CNTX_AGING_LIMITr(unit, 17184 &mmu_data->_soc_tr3_cntx_aging_limit)); 17185 SOC_IF_ERROR_RETURN(READ_CNTX_LRU_ENr(unit, 17186 &mmu_data->_soc_tr3_cntx_lru_en)); 17187 SOC_IF_ERROR_RETURN(READ_COLOR_AWAREr(unit, 17188 &mmu_data->_soc_tr3_color_aware)); 17189 SOC_IF_ERROR_RETURN(READ_COS_MODE_64r(unit, 17190 &mmu_data->_soc_tr3_cos_mode_64)); 17191 SOC_IF_ERROR_RETURN(READ_E2ECC_TX_MODEr(unit, 17192 &mmu_data->_soc_tr3_e2ecc_tx_mode)); 17193 SOC_IF_ERROR_RETURN(READ_E2ECC_TX_PORTS_NUMr(unit, 17194 &mmu_data->_soc_tr3_e2ecc_tx_ports_num)); 17195 SOC_IF_ERROR_RETURN(READ_DEQ_AGINGMASK_CPU_PORTr(unit, 17196 &mmu_data->_soc_tr3_deq_agingmask_cpu_port)); 17197 SOC_IF_ERROR_RETURN(READ_DEQ_AGINGMASK_RDEr(unit, 17198 &mmu_data->_soc_tr3_deq_agingmask_rde)); 17199 SOC_IF_ERROR_RETURN(READ_DEQ_AGINGMASK_UCQ_0r(unit, 17200 &mmu_data->_soc_tr3_deq_agingmask_ucq_0)); 17201 SOC_IF_ERROR_RETURN(READ_DEQ_AGINGMASK_UCQ_1r(unit, 17202 &mmu_data->_soc_tr3_deq_agingmask_ucq_1)); 17203 SOC_IF_ERROR_RETURN(READ_DEQ_AGINGMASK_UCQ_10r(unit, 17204 &mmu_data->_soc_tr3_deq_agingmask_ucq_10)); 17205 SOC_IF_ERROR_RETURN(READ_DEQ_AGINGMASK_UCQ_11r(unit, 17206 &mmu_data->_soc_tr3_deq_agingmask_ucq_11)); 17207 SOC_IF_ERROR_RETURN(READ_DEQ_AGINGMASK_UCQ_12r(unit, 17208 &mmu_data->_soc_tr3_deq_agingmask_ucq_12)); 17209 SOC_IF_ERROR_RETURN(READ_DEQ_AGINGMASK_UCQ_13r(unit, 17210 &mmu_data->_soc_tr3_deq_agingmask_ucq_13)); 17211 SOC_IF_ERROR_RETURN(READ_DEQ_AGINGMASK_UCQ_14r(unit, 17212 &mmu_data->_soc_tr3_deq_agingmask_ucq_14)); 17213 SOC_IF_ERROR_RETURN(READ_DEQ_AGINGMASK_UCQ_15r(unit, 17214 &mmu_data->_soc_tr3_deq_agingmask_ucq_15)); 17215 SOC_IF_ERROR_RETURN(READ_DEQ_AGINGMASK_UCQ_2r(unit, 17216 &mmu_data->_soc_tr3_deq_agingmask_ucq_2)); 17217 SOC_IF_ERROR_RETURN(READ_DEQ_AGINGMASK_UCQ_3r(unit, 17218 &mmu_data->_soc_tr3_deq_agingmask_ucq_3)); 17219 SOC_IF_ERROR_RETURN(READ_DEQ_AGINGMASK_UCQ_4r(unit, 17220 &mmu_data->_soc_tr3_deq_agingmask_ucq_4)); 17221 SOC_IF_ERROR_RETURN(READ_DEQ_AGINGMASK_UCQ_5r(unit, 17222 &mmu_data->_soc_tr3_deq_agingmask_ucq_5)); 17223 SOC_IF_ERROR_RETURN(READ_DEQ_AGINGMASK_UCQ_6r(unit, 17224 &mmu_data->_soc_tr3_deq_agingmask_ucq_6)); 17225 SOC_IF_ERROR_RETURN(READ_DEQ_AGINGMASK_UCQ_7r(unit, 17226 &mmu_data->_soc_tr3_deq_agingmask_ucq_7)); 17227 SOC_IF_ERROR_RETURN(READ_DEQ_AGINGMASK_UCQ_8r(unit, 17228 &mmu_data->_soc_tr3_deq_agingmask_ucq_8)); 17229 SOC_IF_ERROR_RETURN(READ_DEQ_AGINGMASK_UCQ_9r(unit, 17230 &mmu_data->_soc_tr3_deq_agingmask_ucq_9)); 17231 SOC_IF_ERROR_RETURN(READ_DEQ_QCN_LB_COSr(unit, 17232 &mmu_data->_soc_tr3_deq_qcn_lb_cos)); 17233 SOC_IF_ERROR_RETURN(READ_DROP_CBP_64r(unit, 17234 &mmu_data->_soc_tr3_drop_cbp_64)); 17235 SOC_IF_ERROR_RETURN(READ_E2ECC_HOL_ENr(unit, 17236 &mmu_data->_soc_tr3_e2ecc_hol_en)); 17237 SOC_IF_ERROR_RETURN(READ_E2ECC_MAX_TX_TIMERr(unit, 17238 &mmu_data->_soc_tr3_e2ecc_max_tx_timer)); 17239 SOC_IF_ERROR_RETURN(READ_E2ECC_MIN_TX_TIMERr(unit, 17240 &mmu_data->_soc_tr3_e2ecc_min_tx_timer)); 17241 SOC_IF_ERROR_RETURN(READ_E2EFC_CONFIGr(unit, 17242 &mmu_data->_soc_tr3_e2efc_config)); 17243 SOC_IF_ERROR_RETURN(READ_E2EFC_IBP_ENr(unit, 17244 &mmu_data->_soc_tr3_e2efc_ibp_en)); 17245 SOC_IF_ERROR_RETURN(READ_E2EFC_PORT_MAPPING_CONFIGr(unit, 17246 &mmu_data->_soc_tr3_e2efc_port_mapping_config)); 17247 SOC_IF_ERROR_RETURN(READ_E2EFC_RX_RMODID_64r(unit, 17248 &mmu_data->_soc_tr3_e2efc_rx_rmodid_64)); 17249 SOC_IF_ERROR_RETURN(READ_E2EFC_TX_RMODID_64r(unit, 17250 &mmu_data->_soc_tr3_e2efc_tx_rmodid_64)); 17251 SOC_IF_ERROR_RETURN(READ_ENQ_CONFIGr(unit, 17252 &mmu_data->_soc_tr3_enq_config)); 17253 SOC_IF_ERROR_RETURN(READ_ENQ_CTRL_PKT_MODEr(unit, 17254 &mmu_data->_soc_tr3_enq_ctrl_pkt_mode)); 17255 SOC_IF_ERROR_RETURN(READ_GLOBAL_HDRM_LIMITr(unit, 17256 &mmu_data->_soc_tr3_global_hdrm_limit)); 17257 SOC_IF_ERROR_RETURN(READ_GMHIGHBANKr(unit, 17258 &mmu_data->_soc_tr3_gmhighbank)); 17259 SOC_IF_ERROR_RETURN(READ_GMLOWBANKr(unit, 17260 &mmu_data->_soc_tr3_gmlowbank)); 17261 SOC_IF_ERROR_RETURN(READ_GMMEMWARMUPr(unit, 17262 &mmu_data->_soc_tr3_gmmemwarmup)); 17263 SOC_IF_ERROR_RETURN(READ_INPUT_PORT_RX_ENABLE_64r(unit, 17264 &mmu_data->_soc_tr3_input_port_rx_enable_64)); 17265 SOC_IF_ERROR_RETURN(READ_INTFI_CFGr(unit, 17266 &mmu_data->_soc_tr3_intfi_cfg)); 17267 SOC_IF_ERROR_RETURN(READ_INTFO_FCN_ENr(unit, 17268 &mmu_data->_soc_tr3_intfo_fcn_en)); 17269 SOC_IF_ERROR_RETURN( 17270 READ_LLS_ASF_CREDIT_HIGH_THRESHOLD_FOR_PORTS_32_37r(unit, 17271 &mmu_data->_soc_tr3_lls_asf_credit_high_threshold_for_ports_32_37)); 17272 SOC_IF_ERROR_RETURN( 17273 READ_LLS_ASF_CREDIT_HIGH_THRESHOLD_FOR_PORTS_38_43r(unit, 17274 &mmu_data->_soc_tr3_lls_asf_credit_high_threshold_for_ports_38_43)); 17275 SOC_IF_ERROR_RETURN( 17276 READ_LLS_ASF_CREDIT_HIGH_THRESHOLD_FOR_PORTS_44_49r(unit, 17277 &mmu_data->_soc_tr3_lls_asf_credit_high_threshold_for_ports_44_49)); 17278 SOC_IF_ERROR_RETURN( 17279 READ_LLS_ASF_CREDIT_HIGH_THRESHOLD_FOR_PORTS_50_55r(unit, 17280 &mmu_data->_soc_tr3_lls_asf_credit_high_threshold_for_ports_50_55)); 17281 SOC_IF_ERROR_RETURN(READ_LLS_AXP_PORT_56_CFG_WEIGHTr(unit, 17282 &mmu_data->_soc_tr3_lls_axp_port_56_cfg_weight)); 17283 SOC_IF_ERROR_RETURN(READ_LLS_AXP_PORT_57_CFG_WEIGHTr(unit, 17284 &mmu_data->_soc_tr3_lls_axp_port_57_cfg_weight)); 17285 SOC_IF_ERROR_RETURN(READ_LLS_AXP_PORT_58_CFG_WEIGHTr(unit, 17286 &mmu_data->_soc_tr3_lls_axp_port_58_cfg_weight)); 17287 SOC_IF_ERROR_RETURN(READ_LLS_AXP_PORT_61_CFG_WEIGHTr(unit, 17288 &mmu_data->_soc_tr3_lls_axp_port_61_cfg_weight)); 17289 SOC_IF_ERROR_RETURN(READ_LLS_AXP_PORT_62_CFG_WEIGHTr(unit, 17290 &mmu_data->_soc_tr3_lls_axp_port_62_cfg_weight)); 17291 SOC_IF_ERROR_RETURN(READ_LLS_CFG_ERR_BYTE_ADJUSTr(unit, 17292 &mmu_data->_soc_tr3_lls_cfg_err_byte_adjust)); 17293 SOC_IF_ERROR_RETURN(READ_LLS_CONFIG_SP_MIN_PRIORITYr(unit, 17294 &mmu_data->_soc_tr3_lls_config_sp_min_priority)); 17295 SOC_IF_ERROR_RETURN(READ_LLS_CONFIG_SPAREr(unit, 17296 &mmu_data->_soc_tr3_lls_config_spare)); 17297 SOC_IF_ERROR_RETURN(READ_LLS_CONFIG0r(unit, &mmu_data->_soc_tr3_lls_config0)); 17298 SOC_IF_ERROR_RETURN(READ_LLS_DEBUG_ENQ_BLOCK_ON_L0r(unit, 17299 &mmu_data->_soc_tr3_lls_debug_enq_block_on_l0)); 17300 SOC_IF_ERROR_RETURN(READ_LLS_DEBUG_ENQ_BLOCK_ON_L1r(unit, 17301 &mmu_data->_soc_tr3_lls_debug_enq_block_on_l1)); 17302 SOC_IF_ERROR_RETURN(READ_LLS_DEBUG_ENQ_BLOCK_ON_L2r(unit, 17303 &mmu_data->_soc_tr3_lls_debug_enq_block_on_l2)); 17304 SOC_IF_ERROR_RETURN(READ_LLS_DEBUG_ENQ_BLOCK_ON_PORTr(unit, 17305 &mmu_data->_soc_tr3_lls_debug_enq_block_on_port)); 17306 SOC_IF_ERROR_RETURN(READ_LLS_DEBUG_P_WERR_MAX_SC_RESETr(unit, 17307 &mmu_data->_soc_tr3_lls_debug_p_werr_max_sc_reset)); 17308 SOC_IF_ERROR_RETURN(READ_LLS_FC_CONFIGr(unit, 17309 &mmu_data->_soc_tr3_lls_fc_config)); 17310 SOC_IF_ERROR_RETURN(READ_LLS_FIXED_DEQ_LENr(unit, 17311 &mmu_data->_soc_tr3_lls_fixed_deq_len)); 17312 SOC_IF_ERROR_RETURN(READ_LLS_INITr(unit, 17313 &mmu_data->_soc_tr3_lls_initr)); 17314 SOC_IF_ERROR_RETURN(READ_LLS_PKT_ACC_CONFIG1r(unit, 17315 &mmu_data->_soc_tr3_lls_pkt_acc_config1)); 17316 SOC_IF_ERROR_RETURN(READ_LLS_PKT_ACC_CONFIG2r(unit, 17317 &mmu_data->_soc_tr3_lls_pkt_acc_config2)); 17318 SOC_IF_ERROR_RETURN(READ_LLS_TDM_AXP_SCHEDULINGr(unit, 17319 &mmu_data->_soc_tr3_lls_tdm_axp_scheduling)); 17320 SOC_IF_ERROR_RETURN(READ_LLS_TDM_CAL_CFGr(unit, 17321 &mmu_data->_soc_tr3_lls_tdm_cal_cfg)); 17322 SOC_IF_ERROR_RETURN(READ_LLS_TDM_OPPORTUNISTIC_SPACINGr(unit, 17323 &mmu_data->_soc_tr3_lls_tdm_opportunistic_spacing)); 17324 SOC_IF_ERROR_RETURN(READ_MCFIFO_CONFIGr(unit, 17325 &mmu_data->_soc_tr3_mcfifo_config)); 17326 SOC_IF_ERROR_RETURN(READ_MCQ_CONFIGr(unit, 17327 &mmu_data->_soc_tr3_mcq_config)); 17328 SOC_IF_ERROR_RETURN(READ_MEM_FAIL_INT_EN_64r(unit, 17329 &mmu_data->_soc_tr3_mem_fail_int_en_64)); 17330 SOC_IF_ERROR_RETURN(READ_MMU_CFG_HSP_CONFIGr(unit, 17331 &mmu_data->_soc_tr3_mmu_cfg_hsp_config)); 17332 SOC_IF_ERROR_RETURN(READ_MMU_LLFC_TX_CONFIG_1r(unit, 17333 &mmu_data->_soc_tr3_mmu_llfc_tx_config_1)); 17334 SOC_IF_ERROR_RETURN(READ_MMU_LLFC_TX_CONFIG_2r(unit, 17335 &mmu_data->_soc_tr3_mmu_llfc_tx_config_2)); 17336 SOC_IF_ERROR_RETURN(READ_MMU_QCN_CNM_CTRL_64r(unit, 17337 &mmu_data->_soc_tr3_mmu_qcn_cnm_ctrl_64)); 17338 SOC_IF_ERROR_RETURN(READ_MTP_COSr(unit, &mmu_data->_soc_tr3_mtp_cos)); 17339 SOC_IF_ERROR_RETURN(READ_MTRI_REFRESH_CONFIGr(unit, 17340 &mmu_data->_soc_tr3_mtri_refresh_config)); 17341 SOC_IF_ERROR_RETURN(READ_MTRO_REFRESH_CONFIGr(unit, 17342 &mmu_data->_soc_tr3_mtro_refresh_config)); 17343 SOC_IF_ERROR_RETURN(READ_OOBFC_CHANNEL_BASE_64r(unit, 17344 &mmu_data->_soc_tr3_oobfc_channel_base_64)); 17345 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, 17346 OOBFC_CHIF_CFGr, REG_PORT_ANY, 0, 17347 &mmu_data->_soc_tr3_oobfc_chif_cfg)); 17348 SOC_IF_ERROR_RETURN(READ_OOBFC_ENG_PORT_EN_64r(unit, 17349 &mmu_data->_soc_tr3_oobfc_eng_port_en_64)); 17350 SOC_IF_ERROR_RETURN(READ_OOBFC_ENG_PORT_QSEL_64r(unit, 17351 &mmu_data->_soc_tr3_oobfc_eng_port_qsel_64)); 17352 SOC_IF_ERROR_RETURN(READ_OOBFC_GCSr(unit, &mmu_data->_soc_tr3_oobfc_gcs)); 17353 SOC_IF_ERROR_RETURN(READ_OOBFC_ING_PORT_EN_64r(unit, 17354 &mmu_data->_soc_tr3_oobfc_ing_port_en_64)); 17355 SOC_IF_ERROR_RETURN(READ_OOBFC_TX_IDLEr(unit, 17356 &mmu_data->_soc_tr3_oobfc_tx_idle)); 17357 SOC_IF_ERROR_RETURN(READ_OOBIF_DEBUGr(unit, 17358 &mmu_data->_soc_tr3_oobif_debug)); 17359 SOC_IF_ERROR_RETURN(READ_OP_SP_BST_THRESHOLD_SELr(unit, 17360 &mmu_data->_soc_tr3_op_sp_bst_threshold_sel)); 17361 SOC_IF_ERROR_RETURN(READ_OP_THR_CONFIGr(unit, 17362 &mmu_data->_soc_tr3_op_thr_config)); 17363 SOC_IF_ERROR_RETURN(READ_OP_THR_CONFIG_PLUSr(unit, 17364 &mmu_data->_soc_tr3_op_thr_config_plus)); 17365 SOC_IF_ERROR_RETURN(READ_OUTPUT_PORT_RX_ENABLE0_64r(unit, 17366 &mmu_data->_soc_tr3_output_port_rx_enable0_64)); 17367 SOC_IF_ERROR_RETURN(READ_OVQ_BUBBLE_SIZE_REGr(unit, 17368 &mmu_data->_soc_tr3_ovq_bubble_size_reg)); 17369 SOC_IF_ERROR_RETURN(READ_OVQ_BUBBLE_THRESHOLDr(unit, 17370 &mmu_data->_soc_tr3_ovq_bubble_threshold)); 17371 SOC_IF_ERROR_RETURN(READ_OVQ_DFTr(unit, &mmu_data->_soc_tr3_ovq_dft)); 17372 SOC_IF_ERROR_RETURN(READ_OVQ_DROP_THRESHOLD_REGr(unit, 17373 &mmu_data->_soc_tr3_ovq_drop_threshold_reg)); 17374 SOC_IF_ERROR_RETURN(READ_OVQ_DROP_THRESHOLD_RESET_LIMITr(unit, 17375 &mmu_data->_soc_tr3_ovq_drop_threshold_reset_limit)); 17376 SOC_IF_ERROR_RETURN(READ_OVQ_DROP_THRESHOLD0r(unit, 17377 &mmu_data->_soc_tr3_ovq_drop_threshold0)); 17378 SOC_IF_ERROR_RETURN(READ_OVQ_FLOWCONTROL_THRESHOLDr(unit, 17379 &mmu_data->_soc_tr3_ovq_flowcontrol_threshold)); 17380 SOC_IF_ERROR_RETURN(READ_OVQ_LINKED_LIST_SELECTr(unit, 17381 &mmu_data->_soc_tr3_ovq_linked_list_select)); 17382 SOC_IF_ERROR_RETURN(READ_PARITY_CHK_ENr(unit, 17383 &mmu_data->_soc_tr3_parity_chk_en)); 17384 SOC_IF_ERROR_RETURN(READ_PKTAGINGLIMIT0r(unit, 17385 &mmu_data->_soc_tr3_pktaginglimit0)); 17386 SOC_IF_ERROR_RETURN(READ_PKTAGINGLIMIT1r(unit, 17387 &mmu_data->_soc_tr3_pktaginglimit1)); 17388 SOC_IF_ERROR_RETURN(READ_PKTAGINGTIMERr(unit, 17389 &mmu_data->_soc_tr3_pktagingtimer)); 17390 SOC_IF_ERROR_RETURN(READ_PORT_OVQ_PAUSE_ENABLE_64r(unit, 17391 &mmu_data->_soc_tr3_port_ovq_pause_enable_64)); 17392 SOC_IF_ERROR_RETURN(READ_PORT_PAUSE_ENABLE_64r(unit, 17393 &mmu_data->_soc_tr3_port_pause_enable_64)); 17394 SOC_IF_ERROR_RETURN(READ_PORT_PFC_CFG0r(unit, 17395 &mmu_data->_soc_tr3_port_pfc_cfg0)); 17396 SOC_IF_ERROR_RETURN(READ_PORT_PFC_CFG1r(unit, 17397 &mmu_data->_soc_tr3_port_pfc_cfg1)); 17398 SOC_IF_ERROR_RETURN(READ_PWR_WATCH_DOG_CONTROL_MBr(unit, 17399 &mmu_data->_soc_tr3_pwr_watch_dog_control_mb)); 17400 SOC_IF_ERROR_RETURN(READ_SCQM_QGRPr(unit, 17401 &mmu_data->_soc_tr3_scqm_qgrp)); 17402 SOC_IF_ERROR_RETURN(READ_THDI_BYPASSr(unit, 17403 &mmu_data->_soc_tr3_thdi_bypass)); 17404 SOC_IF_ERROR_RETURN(READ_THDO_BYPASSr(unit, 17405 &mmu_data->_soc_tr3_thdo_bypass)); 17406 SOC_IF_ERROR_RETURN(READ_THDO_INTEROP_CONFIGr(unit, 17407 &mmu_data->_soc_tr3_thdo_interop_config)); 17408 SOC_IF_ERROR_RETURN(READ_THDO_RDE_SP_SELECTr(unit, 17409 &mmu_data->_soc_tr3_thdo_rde_sp_select)); 17410 SOC_IF_ERROR_RETURN(READ_THDO_UNICAST_DROP_EMIRROR_CNTr(unit, 17411 &mmu_data->_soc_tr3_thdo_unicast_drop_emirror_cnt)); 17412 SOC_IF_ERROR_RETURN(READ_TIME_DOMAINr(unit, &mmu_data->_soc_tr3_time_domain)); 17413 SOC_IF_ERROR_RETURN(READ_UCQ_CONFIGr(unit, &mmu_data->_soc_tr3_ucq_config)); 17414 SOC_IF_ERROR_RETURN(READ_USE_SP_SHAREDr(unit, 17415 &mmu_data->_soc_tr3_use_sp_shared)); 17416 SOC_IF_ERROR_RETURN(READ_WAMU_POOL_SELECTr(unit, 17417 &mmu_data->_soc_tr3_wamu_pool_select)); 17418 SOC_IF_ERROR_RETURN(READ_WAMU_PRI_GRPr(unit, 17419 &mmu_data->_soc_tr3_wamu_pri_grp)); 17420 SOC_IF_ERROR_RETURN(READ_WAMUDROPCNT2BERRr(unit, 17421 &mmu_data->_soc_tr3_wamudropcnt2berr)); 17422 SOC_IF_ERROR_RETURN(READ_WAMUDROPCNTAGINGr(unit, 17423 &mmu_data->_soc_tr3_wamudropcntaging)); 17424 SOC_IF_ERROR_RETURN(READ_WAMUDROPCNTGLBTHDIPKTr(unit, 17425 &mmu_data->_soc_tr3_wamudropcntglbthdipkt)); 17426 SOC_IF_ERROR_RETURN(READ_WAMUDROPCNTLENr(unit, 17427 &mmu_data->_soc_tr3_wamudropcntlen)); 17428 SOC_IF_ERROR_RETURN(READ_WAMUDROPCNTLENBYTEr(unit, 17429 &mmu_data->_soc_tr3_wamudropcntlenbyte)); 17430 SOC_IF_ERROR_RETURN(READ_WAMUDROPCNTLRUr(unit, 17431 &mmu_data->_soc_tr3_wamudropcntlru)); 17432 SOC_IF_ERROR_RETURN(READ_WAMUDROPCNTNOLRUr(unit, 17433 &mmu_data->_soc_tr3_wamudropcntnolru)); 17434 SOC_IF_ERROR_RETURN(READ_WAMUDROPCNTNOLRUBYTEr(unit, 17435 &mmu_data->_soc_tr3_wamudropcntnolrubyte)); 17436 SOC_IF_ERROR_RETURN(READ_WAMUDROPCNTTHDIBYTEr(unit, 17437 &mmu_data->_soc_tr3_wamudropcntthdibyte)); 17438 SOC_IF_ERROR_RETURN(READ_WAMUDROPCNTTHDIPKTr(unit, 17439 &mmu_data->_soc_tr3_wamudropcntthdipkt)); 17440 SOC_IF_ERROR_RETURN(READ_WAMUDROPCNTTYPEr(unit, 17441 &mmu_data->_soc_tr3_wamudropcnttype)); 17442 SOC_IF_ERROR_RETURN(READ_WAMUNONFRAGMCNTr(unit, 17443 &mmu_data->_soc_tr3_wamunonfragmcnt)); 17444 SOC_IF_ERROR_RETURN(READ_WAMUREASMBCNTr(unit, 17445 &mmu_data->_soc_tr3_wamureasmbcnt)); 17446 SOC_IF_ERROR_RETURN(READ_WAMUTHDBYPASSr(unit, 17447 &mmu_data->_soc_tr3_wamuthdbypass)); 17448 SOC_IF_ERROR_RETURN(READ_WAMUTOTALSHRLMTINGr(unit, 17449 &mmu_data->_soc_tr3_wamutotalshrlmting)); 17450 SOC_IF_ERROR_RETURN(READ_WAMUTOTALSHRLMTPKTEGRr(unit, 17451 &mmu_data->_soc_tr3_wamutotalshrlmtpktegr)); 17452 SOC_IF_ERROR_RETURN(READ_WRED_REFRESH_CONTROLr(unit, 17453 &mmu_data->_soc_tr3_wred_refresh_control)); 17454 17455 if (!SOC_IS_HELIX4(unit) && SOC_IS_TRIUMPH3(unit)) { 17456 SOC_IF_ERROR_RETURN(READ_HSP_CONFIGr(unit, 17457 &mmu_data->_soc_tr3_hsp_config)); 17458 PBMP_C_ITER(unit, port) { 17459 SOC_IF_ERROR_RETURN(READ_HES_L0_CONFIGr(unit, port, 17460 &mmu_data->_soc_tr3_hes_l0_config[port])); 17461 SOC_IF_ERROR_RETURN(READ_HES_PORT_CONFIGr(unit, port, 17462 &mmu_data->_soc_tr3_hes_port_config[port])); 17463 SOC_IF_ERROR_RETURN(READ_HES_Q_COSMASKr(unit, port, 17464 &mmu_data->_soc_tr3_hes_q_cosmask[port])); 17465 SOC_IF_ERROR_RETURN(READ_HES_Q_MINSPr(unit, port, 17466 &mmu_data->_soc_tr3_hes_q_minsp[port])); 17467 for (idx=0; idx<20; idx++) { 17468 SOC_IF_ERROR_RETURN(READ_HES_Q_COSWEIGHTSr(unit, port, idx, 17469 &mmu_data->_soc_tr3_hes_q_cosweights[port][idx])); 17470 } 17471 for (idx=0; idx<10; idx++) { 17472 SOC_IF_ERROR_RETURN(READ_L0_COSWEIGHTSr(unit, port, idx, 17473 &mmu_data->_soc_tr3_l0_cosweights[port][idx])); 17474 } 17475 } 17476 } 17477 17478 return SOC_E_NONE; 17479 } 17480 17481 17482 int 17483 soc_tr3_mmu_register_restore(int unit) 17484 { 17485 int port, idx, mmu_port, phy_port; 17486 soc_info_t *si = &SOC_INFO(unit); 17487 _soc_tr3_mmu_data_t *mmu_data; 17488 17489 mmu_data = (_soc_tr3_mmu_data_t *) _soc_tr3_mmu_data[unit]; 17490 if(mmu_data == NULL) { 17491 LOG_ERROR(BSL_LS_SOC_COMMON, 17492 (BSL_META_U(unit, 17493 "NULL pointer for MMU data\n"))); 17494 return SOC_E_INTERNAL; 17495 } 17496 17497 for (idx = 0; idx < 2; idx++) { 17498 SOC_IF_ERROR_RETURN(WRITE_WAMU_PG_RESET_FLOOR_CELLr(unit, idx, 17499 mmu_data->_soc_tr3_wamu_pg_reset_floor_cell[idx])); 17500 SOC_IF_ERROR_RETURN(WRITE_WAMURSTOFFSETCELLPGr(unit, idx, 17501 mmu_data->_soc_tr3_wamurstoffsetcellpg[idx])); 17502 SOC_IF_ERROR_RETURN(WRITE_WAMURSTOFFSETPKTPGr(unit, idx, 17503 mmu_data->_soc_tr3_wamurstoffsetpktpg[idx])); 17504 SOC_IF_ERROR_RETURN(WRITE_WAMUSHRLMTPKTPGr(unit, idx, 17505 mmu_data->_soc_tr3_wamushrlmtpktpg[idx])); 17506 SOC_IF_ERROR_RETURN( 17507 WRITE_WAMU_PG_FIRST_FRAGMENT_DROP_OFFSETr(unit, idx, 17508 mmu_data->_soc_tr3_wamu_pg_first_fragment_drop_offset[idx])); 17509 } 17510 17511 for (idx = 0; idx < 4; idx++) { 17512 SOC_IF_ERROR_RETURN (WRITE_CELL_SPAP_YELLOW_OFFSET_SPr( 17513 unit, idx, 17514 mmu_data->_soc_tr3_cell_spap_yellow_offset_sp[idx])); 17515 SOC_IF_ERROR_RETURN(WRITE_CELL_SPAP_RED_OFFSET_SPr( 17516 unit, idx, 17517 mmu_data->_soc_tr3_cell_spap_red_offset_sp[idx])); 17518 SOC_IF_ERROR_RETURN(WRITE_CONGESTION_STATE_BYTESr(unit, idx, 17519 mmu_data->_soc_tr3_congestion_state_bytes[idx])); 17520 SOC_IF_ERROR_RETURN(WRITE_E2EFC_RMOD_CFGr(unit, idx, 17521 mmu_data->_soc_tr3_e2efc_rmod_cfg[idx])); 17522 SOC_IF_ERROR_RETURN(WRITE_E2EFC_RX_RMT_TIMEOUTr(unit, idx, 17523 mmu_data->_soc_tr3_e2efc_rx_rmt_timeout[idx])); 17524 SOC_IF_ERROR_RETURN(WRITE_OP_MC_SP_BST_THRESHOLDr(unit, idx, 17525 mmu_data->_soc_tr3_op_mc_sp_bst_threshold[idx])); 17526 SOC_IF_ERROR_RETURN(WRITE_OP_MCUC_SP_BST_THRESHOLDr(unit, idx, 17527 mmu_data->_soc_tr3_op_mcuc_sp_bst_threshold[idx])); 17528 } 17529 17530 for (idx = 0; idx < 5; idx++) { 17531 SOC_IF_ERROR_RETURN(WRITE_THDI_BST_PROFILE_THRESH_SPr(unit, idx, 17532 mmu_data->_soc_tr3_thdi_bst_profile_thresh_sp[idx])); 17533 } 17534 17535 for (idx = 0; idx < 7; idx++) { 17536 SOC_IF_ERROR_RETURN(WRITE_E2ECC_TX_ENABLE_BMPr(unit, idx, 17537 mmu_data->_soc_tr3_e2ecc_tx_enable_bmp[idx])); 17538 SOC_IF_ERROR_RETURN(WRITE_E2EFC_MAX_TX_TIMERr(unit, idx, 17539 mmu_data->_soc_tr3_e2efc_max_tx_timer[idx])); 17540 SOC_IF_ERROR_RETURN(WRITE_E2EFC_MIN_TX_TIMERr(unit, idx, 17541 mmu_data->_soc_tr3_e2efc_min_tx_timer[idx])); 17542 } 17543 17544 for (idx = 0; idx < 8; idx++) { 17545 SOC_IF_ERROR_RETURN( 17546 WRITE_OP_CPU_QUEUE_BST_THRESHOLD_PROFILEr(unit, idx, 17547 mmu_data->_soc_tr3_op_cpu_queue_bst_threshold_profile[idx])); 17548 SOC_IF_ERROR_RETURN( 17549 WRITE_OP_RESUME_OFFSET_COLOR_CELL_PROFILEr(unit, idx, 17550 mmu_data->_soc_tr3_op_resume_offset_color_cell_profile[idx])); 17551 SOC_IF_ERROR_RETURN( 17552 WRITE_OP_UC_PORT_BST_THRESHOLDr(unit, idx, 17553 mmu_data->_soc_tr3_op_uc_port_bst_threshold[idx])); 17554 SOC_IF_ERROR_RETURN( 17555 WRITE_OP_UC_QGROUP_BST_THRESHOLDr(unit, idx, 17556 mmu_data->_soc_tr3_op_uc_qgroup_bst_threshold[idx])); 17557 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, OP_UC_QUEUE_BST_THRESHOLDr, 17558 REG_PORT_ANY, idx, 17559 mmu_data->_soc_tr3_op_uc_queue_bst_threshold[idx])); 17560 SOC_IF_ERROR_RETURN( 17561 WRITE_THDI_BST_PROFILE_THRESH_PG_HDRMr(unit, idx, 17562 mmu_data->_soc_tr3_thdi_bst_profile_thresh_pg_hdrm[idx])); 17563 SOC_IF_ERROR_RETURN( 17564 WRITE_THDI_BST_PROFILE_THRESH_PG_SHAREDr(unit, idx, 17565 mmu_data->_soc_tr3_thdi_bst_profile_thresh_pg_shared[idx])); 17566 SOC_IF_ERROR_RETURN( 17567 WRITE_THDI_BST_PROFILE_THRESH_PORT_SHAREDr(unit, idx, 17568 mmu_data->_soc_tr3_thdi_bst_profile_thresh_port_shared[idx])); 17569 SOC_IF_ERROR_RETURN(WRITE_TX_CNT_CONFIGr_REG32(unit, idx, 17570 mmu_data->_soc_tr3_tx_cnt_config[idx])); 17571 SOC_IF_ERROR_RETURN(WRITE_WAMUDROPCNTTHDOBYTEr(unit, idx, 17572 mmu_data->_soc_tr3_wamudropcntthdobyte[idx])); 17573 SOC_IF_ERROR_RETURN(WRITE_MMU_QCN_CPQ_SEQr(unit, idx, 17574 mmu_data->_soc_tr3_mmu_qcn_cpq_seq[idx])); 17575 SOC_IF_ERROR_RETURN(WRITE_WAMUDROPCNTTHDOPKTr(unit, idx, 17576 mmu_data->_soc_tr3_wamudropcntthdopkt[idx])); 17577 } 17578 17579 for (idx = 0; idx < 16; idx++) { 17580 SOC_IF_ERROR_RETURN(WRITE_CFAPBANKFULLr(unit, idx, 17581 mmu_data->_soc_tr3_cfapbankfull[idx])); 17582 SOC_IF_ERROR_RETURN(WRITE_PRIO2COS_PROFILE0r(unit, idx, 17583 mmu_data->_soc_tr3_prio2cos_profile0[idx])); 17584 SOC_IF_ERROR_RETURN(WRITE_PRIO2COS_PROFILE1r(unit, idx, 17585 mmu_data->_soc_tr3_prio2cos_profile1[idx])); 17586 SOC_IF_ERROR_RETURN(WRITE_PRIO2COS_PROFILE2r(unit, idx, 17587 mmu_data->_soc_tr3_prio2cos_profile2[idx])); 17588 SOC_IF_ERROR_RETURN(WRITE_PRIO2COS_PROFILE3r(unit, idx, 17589 mmu_data->_soc_tr3_prio2cos_profile3[idx])); 17590 SOC_IF_ERROR_RETURN(WRITE_SRC_MOD_IDr(unit, idx, 17591 mmu_data->_soc_tr3_src_mod_id[idx])); 17592 } 17593 for (idx = 0; idx < 63; idx++) { 17594 SOC_IF_ERROR_RETURN( 17595 WRITE_MMU_TO_LOGIC_PORT_MAPPINGr(unit, idx, 17596 mmu_data->_soc_tr3_mmu_to_logic_port_mapping[idx])); 17597 SOC_IF_ERROR_RETURN( 17598 WRITE_MMU_TO_PHY_PORT_MAPPINGr(unit, idx, 17599 mmu_data->_soc_tr3_mmu_to_phy_port_mapping[idx])); 17600 } 17601 for (idx = 0; idx < 64; idx++) { 17602 SOC_IF_ERROR_RETURN(WRITE_E2EFC_CNT_ATTRr(unit, idx, 17603 mmu_data->_soc_tr3_e2efc_cnt_attr[idx])); 17604 SOC_IF_ERROR_RETURN(WRITE_E2EFC_CNT_RESET_LIMITr(unit, idx, 17605 mmu_data->_soc_tr3_e2efc_cnt_reset_limit[idx])); 17606 SOC_IF_ERROR_RETURN(WRITE_E2EFC_CNT_SET_LIMITr(unit, idx, 17607 mmu_data->_soc_tr3_e2efc_cnt_set_limit[idx])); 17608 SOC_IF_ERROR_RETURN(WRITE_E2EFC_CNT_VALr(unit, idx, 17609 mmu_data->_soc_tr3_e2efc_cnt_val[idx])); 17610 SOC_IF_ERROR_RETURN(WRITE_PRIO2COS_PROFILEr(unit, idx, 17611 mmu_data->_soc_tr3_prio2cos_profile[idx])); 17612 } 17613 17614 PBMP_ALL_ITER(unit, port) { 17615 if (port != 0) { 17616 SOC_IF_ERROR_RETURN(WRITE_DEQ_AGINGMASKr(unit, port, 17617 mmu_data->_soc_tr3_deq_agingmask[port])); 17618 } 17619 SOC_IF_ERROR_RETURN(WRITE_DROP_BYTE_CNT_ING_64r(unit, port, 17620 mmu_data->_soc_tr3_drop_byte_cnt_ing_64[port])); 17621 SOC_IF_ERROR_RETURN(WRITE_DROP_PKT_CNT_INGr(unit, port, 17622 mmu_data->_soc_tr3_drop_pkt_cnt_ing[port])); 17623 SOC_IF_ERROR_RETURN(WRITE_DROP_PKT_CNT_OVQr(unit, port, 17624 mmu_data->_soc_tr3_drop_pkt_cnt_ovq[port])); 17625 SOC_IF_ERROR_RETURN(WRITE_EGRMETERINGCONFIG_64r(unit, port, 17626 mmu_data->_soc_tr3_egrmeteringconfig_64[port])); 17627 SOC_IF_ERROR_RETURN(WRITE_MTRI_IFGr(unit, port, 17628 mmu_data->_soc_tr3_mtri_ifg[port])); 17629 SOC_IF_ERROR_RETURN(WRITE_OP_PORT_CONFIG1_CELLr(unit, port, 17630 mmu_data->_soc_tr3_op_port_config1_cell[port])); 17631 SOC_IF_ERROR_RETURN(WRITE_THDO_PORT_E2ECC_COS_SPIDr(unit, port, 17632 mmu_data->_soc_tr3_thdo_port_e2ecc_cos_spid[port])); 17633 SOC_IF_ERROR_RETURN(WRITE_BKPMETERINGCONFIG_64r(unit, port, 17634 mmu_data->_soc_tr3_bkpmeteringconfig_64[port])); 17635 SOC_IF_ERROR_RETURN(WRITE_ING_COS_MODEr(unit, port, 17636 mmu_data->_soc_tr3_ing_cos_mode[port])); 17637 } 17638 17639 for (idx = 0; idx < 8; idx++) { 17640 SOC_IF_ERROR_RETURN( 17641 WRITE_MCQ_FIFO_BASE_REG_56r(unit, 58, idx, 17642 mmu_data->_soc_tr3_mcq_fifo_base_reg_56[idx])); 17643 SOC_IF_ERROR_RETURN( 17644 WRITE_MCQ_FIFO_BASE_REG_PASSTHRUr(unit, 61, idx, 17645 mmu_data->_soc_tr3_mcq_fifo_base_reg_passthru[idx])); 17646 } 17647 17648 for (idx = 0; idx < 48; idx++) { 17649 SOC_IF_ERROR_RETURN( 17650 WRITE_MCQ_FIFO_BASE_REG_CPUr(unit, 0, idx, 17651 mmu_data->_soc_tr3_mcq_fifo_base_reg_cpu[idx])); 17652 } 17653 17654 PBMP_ALL_ITER(unit, port) { 17655 phy_port = si->port_l2p_mapping[port]; 17656 if (phy_port == -1) { 17657 continue; 17658 } 17659 mmu_port = si->port_p2m_mapping[phy_port]; 17660 17661 for (idx = 0; idx < 8; idx++) { 17662 if ((mmu_port >= 32) && (mmu_port <= 35)) { 17663 SOC_IF_ERROR_RETURN(WRITE_MCQ_FIFO_BASE_REG_32_35r(unit, 17664 port, idx, 17665 mmu_data->_soc_tr3_mcq_fifo_base_reg_32_35[mmu_port-32][idx])); 17666 } 17667 if ((mmu_port >= 36) && (mmu_port <= 39)) { 17668 SOC_IF_ERROR_RETURN(WRITE_MCQ_FIFO_BASE_REG_36_39r(unit, 17669 port, idx, 17670 mmu_data->_soc_tr3_mcq_fifo_base_reg_36_39[mmu_port-36][idx])); 17671 } 17672 } 17673 for (idx = 0; idx < 10; idx++) { 17674 if ((mmu_port >= 40) && (mmu_port <= 47)) { 17675 SOC_IF_ERROR_RETURN(WRITE_MCQ_FIFO_BASE_REGr(unit, 17676 port, idx, 17677 mmu_data->_soc_tr3_mcq_fifo_base_reg[mmu_port-40][idx])); 17678 } 17679 if ((mmu_port >= 48) && (mmu_port <= 55)) { 17680 SOC_IF_ERROR_RETURN(WRITE_MCQ_FIFO_BASE_REG_48_55r(unit, 17681 port, idx, 17682 mmu_data->_soc_tr3_mcq_fifo_base_reg_48_55[mmu_port-48][idx])); 17683 } 17684 } 17685 for (idx = 0; idx < 48; idx++) { 17686 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_LIMIT_RESUME_COLOR_CELLr( 17687 unit, port, idx, 17688 mmu_data->_soc_tr3_op_queue_limit_resume_color_cell[port][idx])); 17689 SOC_IF_ERROR_RETURN(WRITE_OP_CPU_QUEUE_BST_THRESHOLDr(unit, 17690 port, idx, 17691 mmu_data->_soc_tr3_op_cpu_queue_bst_threshold[port][idx])); 17692 } 17693 } 17694 17695 SOC_IF_ERROR_RETURN(WRITE_BST_TRACKING_CONFIGr(unit, 17696 mmu_data->_soc_tr3_bst_tracking_config)); 17697 SOC_IF_ERROR_RETURN(WRITE_BST_TRACKING_ENABLEr(unit, 17698 mmu_data->_soc_tr3_bst_tracking_enable)); 17699 SOC_IF_ERROR_RETURN(WRITE_CFAPBSTTHRSr(unit, 17700 mmu_data->_soc_tr3_cfapbstthrs)); 17701 SOC_IF_ERROR_RETURN(WRITE_CFAPCONFIGr(unit, 17702 mmu_data->_soc_tr3_cfapconfig)); 17703 SOC_IF_ERROR_RETURN(WRITE_LLS_DEBUG_ENQ_BLOCK_ON_L0r(unit, 17704 mmu_data->_soc_tr3_lls_debug_enq_block_on_l0)); 17705 SOC_IF_ERROR_RETURN(WRITE_LLS_DEBUG_ENQ_BLOCK_ON_L1r(unit, 17706 mmu_data->_soc_tr3_lls_debug_enq_block_on_l1)); 17707 SOC_IF_ERROR_RETURN(WRITE_LLS_DEBUG_ENQ_BLOCK_ON_L2r(unit, 17708 mmu_data->_soc_tr3_lls_debug_enq_block_on_l2)); 17709 SOC_IF_ERROR_RETURN(WRITE_LLS_DEBUG_ENQ_BLOCK_ON_PORTr(unit, 17710 mmu_data->_soc_tr3_lls_debug_enq_block_on_port)); 17711 SOC_IF_ERROR_RETURN(WRITE_CH_BASE_EXPECTEDr(unit, 17712 mmu_data->_soc_tr3_ch_base_expected)); 17713 SOC_IF_ERROR_RETURN(WRITE_CNTX_LRU_ENr(unit, 17714 mmu_data->_soc_tr3_cntx_lru_en)); 17715 SOC_IF_ERROR_RETURN(WRITE_COS_MODE_64r(unit, 17716 mmu_data->_soc_tr3_cos_mode_64)); 17717 SOC_IF_ERROR_RETURN(WRITE_E2ECC_TX_MODEr(unit, 17718 mmu_data->_soc_tr3_e2ecc_tx_mode)); 17719 SOC_IF_ERROR_RETURN(WRITE_E2ECC_TX_PORTS_NUMr(unit, 17720 mmu_data->_soc_tr3_e2ecc_tx_ports_num)); 17721 SOC_IF_ERROR_RETURN(WRITE_DEQ_AGINGMASK_CPU_PORTr(unit, 17722 mmu_data->_soc_tr3_deq_agingmask_cpu_port)); 17723 SOC_IF_ERROR_RETURN(WRITE_DEQ_AGINGMASK_RDEr(unit, 17724 mmu_data->_soc_tr3_deq_agingmask_rde)); 17725 SOC_IF_ERROR_RETURN(WRITE_DEQ_AGINGMASK_UCQ_0r(unit, 17726 mmu_data->_soc_tr3_deq_agingmask_ucq_0)); 17727 SOC_IF_ERROR_RETURN(WRITE_DEQ_AGINGMASK_UCQ_1r(unit, 17728 mmu_data->_soc_tr3_deq_agingmask_ucq_1)); 17729 SOC_IF_ERROR_RETURN(WRITE_DEQ_AGINGMASK_UCQ_10r(unit, 17730 mmu_data->_soc_tr3_deq_agingmask_ucq_10)); 17731 SOC_IF_ERROR_RETURN(WRITE_DEQ_AGINGMASK_UCQ_11r(unit, 17732 mmu_data->_soc_tr3_deq_agingmask_ucq_11)); 17733 SOC_IF_ERROR_RETURN(WRITE_DEQ_AGINGMASK_UCQ_12r(unit, 17734 mmu_data->_soc_tr3_deq_agingmask_ucq_12)); 17735 SOC_IF_ERROR_RETURN(WRITE_DEQ_AGINGMASK_UCQ_13r(unit, 17736 mmu_data->_soc_tr3_deq_agingmask_ucq_13)); 17737 SOC_IF_ERROR_RETURN(WRITE_DEQ_AGINGMASK_UCQ_14r(unit, 17738 mmu_data->_soc_tr3_deq_agingmask_ucq_14)); 17739 SOC_IF_ERROR_RETURN(WRITE_DEQ_AGINGMASK_UCQ_15r(unit, 17740 mmu_data->_soc_tr3_deq_agingmask_ucq_15)); 17741 SOC_IF_ERROR_RETURN(WRITE_DEQ_AGINGMASK_UCQ_2r(unit, 17742 mmu_data->_soc_tr3_deq_agingmask_ucq_2)); 17743 SOC_IF_ERROR_RETURN(WRITE_DEQ_AGINGMASK_UCQ_3r(unit, 17744 mmu_data->_soc_tr3_deq_agingmask_ucq_3)); 17745 SOC_IF_ERROR_RETURN(WRITE_DEQ_AGINGMASK_UCQ_4r(unit, 17746 mmu_data->_soc_tr3_deq_agingmask_ucq_4)); 17747 SOC_IF_ERROR_RETURN(WRITE_DEQ_AGINGMASK_UCQ_5r(unit, 17748 mmu_data->_soc_tr3_deq_agingmask_ucq_5)); 17749 SOC_IF_ERROR_RETURN(WRITE_DEQ_AGINGMASK_UCQ_6r(unit, 17750 mmu_data->_soc_tr3_deq_agingmask_ucq_6)); 17751 SOC_IF_ERROR_RETURN(WRITE_DEQ_AGINGMASK_UCQ_7r(unit, 17752 mmu_data->_soc_tr3_deq_agingmask_ucq_7)); 17753 SOC_IF_ERROR_RETURN(WRITE_DEQ_AGINGMASK_UCQ_8r(unit, 17754 mmu_data->_soc_tr3_deq_agingmask_ucq_8)); 17755 SOC_IF_ERROR_RETURN(WRITE_DEQ_AGINGMASK_UCQ_9r(unit, 17756 mmu_data->_soc_tr3_deq_agingmask_ucq_9)); 17757 SOC_IF_ERROR_RETURN(WRITE_DEQ_QCN_LB_COSr(unit, 17758 mmu_data->_soc_tr3_deq_qcn_lb_cos)); 17759 SOC_IF_ERROR_RETURN(WRITE_DROP_CBP_64r(unit, 17760 mmu_data->_soc_tr3_drop_cbp_64)); 17761 SOC_IF_ERROR_RETURN(WRITE_E2ECC_HOL_ENr(unit, 17762 mmu_data->_soc_tr3_e2ecc_hol_en)); 17763 SOC_IF_ERROR_RETURN(WRITE_E2ECC_MAX_TX_TIMERr(unit, 17764 mmu_data->_soc_tr3_e2ecc_max_tx_timer)); 17765 SOC_IF_ERROR_RETURN(WRITE_E2ECC_MIN_TX_TIMERr(unit, 17766 mmu_data->_soc_tr3_e2ecc_min_tx_timer)); 17767 SOC_IF_ERROR_RETURN(WRITE_E2EFC_CONFIGr(unit, 17768 mmu_data->_soc_tr3_e2efc_config)); 17769 SOC_IF_ERROR_RETURN(WRITE_E2EFC_IBP_ENr(unit, 17770 mmu_data->_soc_tr3_e2efc_ibp_en)); 17771 SOC_IF_ERROR_RETURN(WRITE_E2EFC_PORT_MAPPING_CONFIGr(unit, 17772 mmu_data->_soc_tr3_e2efc_port_mapping_config)); 17773 SOC_IF_ERROR_RETURN(WRITE_E2EFC_RX_RMODID_64r(unit, 17774 mmu_data->_soc_tr3_e2efc_rx_rmodid_64)); 17775 SOC_IF_ERROR_RETURN(WRITE_E2EFC_TX_RMODID_64r(unit, 17776 mmu_data->_soc_tr3_e2efc_tx_rmodid_64)); 17777 SOC_IF_ERROR_RETURN(WRITE_ENQ_CONFIGr(unit, 17778 mmu_data->_soc_tr3_enq_config)); 17779 SOC_IF_ERROR_RETURN(WRITE_ENQ_CTRL_PKT_MODEr(unit, 17780 mmu_data->_soc_tr3_enq_ctrl_pkt_mode)); 17781 SOC_IF_ERROR_RETURN(WRITE_GMHIGHBANKr(unit, mmu_data->_soc_tr3_gmhighbank)); 17782 SOC_IF_ERROR_RETURN(WRITE_GMLOWBANKr(unit, mmu_data->_soc_tr3_gmlowbank)); 17783 SOC_IF_ERROR_RETURN(WRITE_GMMEMWARMUPr(unit, mmu_data->_soc_tr3_gmmemwarmup)); 17784 SOC_IF_ERROR_RETURN(WRITE_INTFI_CFGr(unit, mmu_data->_soc_tr3_intfi_cfg)); 17785 SOC_IF_ERROR_RETURN(WRITE_INTFO_FCN_ENr(unit, mmu_data->_soc_tr3_intfo_fcn_en)); 17786 SOC_IF_ERROR_RETURN( 17787 WRITE_LLS_ASF_CREDIT_HIGH_THRESHOLD_FOR_PORTS_32_37r(unit, 17788 mmu_data->_soc_tr3_lls_asf_credit_high_threshold_for_ports_32_37)); 17789 SOC_IF_ERROR_RETURN( 17790 WRITE_LLS_ASF_CREDIT_HIGH_THRESHOLD_FOR_PORTS_38_43r(unit, 17791 mmu_data->_soc_tr3_lls_asf_credit_high_threshold_for_ports_38_43)); 17792 SOC_IF_ERROR_RETURN( 17793 WRITE_LLS_ASF_CREDIT_HIGH_THRESHOLD_FOR_PORTS_44_49r(unit, 17794 mmu_data->_soc_tr3_lls_asf_credit_high_threshold_for_ports_44_49)); 17795 SOC_IF_ERROR_RETURN( 17796 WRITE_LLS_ASF_CREDIT_HIGH_THRESHOLD_FOR_PORTS_50_55r(unit, 17797 mmu_data->_soc_tr3_lls_asf_credit_high_threshold_for_ports_50_55)); 17798 SOC_IF_ERROR_RETURN(WRITE_LLS_AXP_PORT_56_CFG_WEIGHTr(unit, 17799 mmu_data->_soc_tr3_lls_axp_port_56_cfg_weight)); 17800 SOC_IF_ERROR_RETURN(WRITE_LLS_AXP_PORT_57_CFG_WEIGHTr(unit, 17801 mmu_data->_soc_tr3_lls_axp_port_57_cfg_weight)); 17802 SOC_IF_ERROR_RETURN(WRITE_LLS_AXP_PORT_58_CFG_WEIGHTr(unit, 17803 mmu_data->_soc_tr3_lls_axp_port_58_cfg_weight)); 17804 SOC_IF_ERROR_RETURN(WRITE_LLS_AXP_PORT_61_CFG_WEIGHTr(unit, 17805 mmu_data->_soc_tr3_lls_axp_port_61_cfg_weight)); 17806 SOC_IF_ERROR_RETURN(WRITE_LLS_AXP_PORT_62_CFG_WEIGHTr(unit, 17807 mmu_data->_soc_tr3_lls_axp_port_62_cfg_weight)); 17808 SOC_IF_ERROR_RETURN(WRITE_LLS_CFG_ERR_BYTE_ADJUSTr(unit, 17809 mmu_data->_soc_tr3_lls_cfg_err_byte_adjust)); 17810 SOC_IF_ERROR_RETURN(WRITE_LLS_CONFIG_SP_MIN_PRIORITYr(unit, 17811 mmu_data->_soc_tr3_lls_config_sp_min_priority)); 17812 SOC_IF_ERROR_RETURN(WRITE_LLS_CONFIG_SPAREr(unit, 17813 mmu_data->_soc_tr3_lls_config_spare)); 17814 SOC_IF_ERROR_RETURN(WRITE_LLS_DEBUG_P_WERR_MAX_SC_RESETr(unit, 17815 mmu_data->_soc_tr3_lls_debug_p_werr_max_sc_reset)); 17816 SOC_IF_ERROR_RETURN(WRITE_LLS_FC_CONFIGr(unit, 17817 mmu_data->_soc_tr3_lls_fc_config)); 17818 SOC_IF_ERROR_RETURN(WRITE_LLS_FIXED_DEQ_LENr(unit, 17819 mmu_data->_soc_tr3_lls_fixed_deq_len)); 17820 SOC_IF_ERROR_RETURN(WRITE_LLS_INITr(unit, 17821 mmu_data->_soc_tr3_lls_initr)); 17822 SOC_IF_ERROR_RETURN(WRITE_LLS_PKT_ACC_CONFIG1r(unit, 17823 mmu_data->_soc_tr3_lls_pkt_acc_config1)); 17824 SOC_IF_ERROR_RETURN(WRITE_LLS_PKT_ACC_CONFIG2r(unit, 17825 mmu_data->_soc_tr3_lls_pkt_acc_config2)); 17826 SOC_IF_ERROR_RETURN(WRITE_LLS_TDM_AXP_SCHEDULINGr(unit, 17827 mmu_data->_soc_tr3_lls_tdm_axp_scheduling)); 17828 SOC_IF_ERROR_RETURN(WRITE_LLS_TDM_CAL_CFGr(unit, 17829 mmu_data->_soc_tr3_lls_tdm_cal_cfg)); 17830 SOC_IF_ERROR_RETURN(WRITE_LLS_TDM_OPPORTUNISTIC_SPACINGr(unit, 17831 mmu_data->_soc_tr3_lls_tdm_opportunistic_spacing)); 17832 SOC_IF_ERROR_RETURN(WRITE_MCFIFO_CONFIGr(unit, 17833 mmu_data->_soc_tr3_mcfifo_config)); 17834 SOC_IF_ERROR_RETURN(WRITE_MCQ_CONFIGr(unit, mmu_data->_soc_tr3_mcq_config)); 17835 SOC_IF_ERROR_RETURN(WRITE_MEM_FAIL_INT_EN_64r(unit, 17836 mmu_data->_soc_tr3_mem_fail_int_en_64)); 17837 SOC_IF_ERROR_RETURN(WRITE_MMU_CFG_HSP_CONFIGr(unit, 17838 mmu_data->_soc_tr3_mmu_cfg_hsp_config)); 17839 SOC_IF_ERROR_RETURN(WRITE_MMU_LLFC_TX_CONFIG_1r(unit, 17840 mmu_data->_soc_tr3_mmu_llfc_tx_config_1)); 17841 SOC_IF_ERROR_RETURN(WRITE_MMU_LLFC_TX_CONFIG_2r(unit, 17842 mmu_data->_soc_tr3_mmu_llfc_tx_config_2)); 17843 SOC_IF_ERROR_RETURN(WRITE_MMU_QCN_CNM_CTRL_64r(unit, 17844 mmu_data->_soc_tr3_mmu_qcn_cnm_ctrl_64)); 17845 SOC_IF_ERROR_RETURN(WRITE_MTP_COSr(unit, 17846 mmu_data->_soc_tr3_mtp_cos)); 17847 SOC_IF_ERROR_RETURN(WRITE_MTRI_REFRESH_CONFIGr(unit, 17848 mmu_data->_soc_tr3_mtri_refresh_config)); 17849 SOC_IF_ERROR_RETURN(WRITE_MTRO_REFRESH_CONFIGr(unit, 17850 mmu_data->_soc_tr3_mtro_refresh_config)); 17851 SOC_IF_ERROR_RETURN(WRITE_OOBFC_CHANNEL_BASE_64r(unit, 17852 mmu_data->_soc_tr3_oobfc_channel_base_64)); 17853 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, OOBFC_CHIF_CFGr, 17854 REG_PORT_ANY, 0, mmu_data->_soc_tr3_oobfc_chif_cfg)); 17855 SOC_IF_ERROR_RETURN(WRITE_OOBFC_ENG_PORT_EN_64r(unit, 17856 mmu_data->_soc_tr3_oobfc_eng_port_en_64)); 17857 SOC_IF_ERROR_RETURN(WRITE_OOBFC_ENG_PORT_QSEL_64r(unit, 17858 mmu_data->_soc_tr3_oobfc_eng_port_qsel_64)); 17859 SOC_IF_ERROR_RETURN(WRITE_OOBFC_GCSr(unit, 17860 mmu_data->_soc_tr3_oobfc_gcs)); 17861 SOC_IF_ERROR_RETURN(WRITE_OOBFC_ING_PORT_EN_64r(unit, 17862 mmu_data->_soc_tr3_oobfc_ing_port_en_64)); 17863 SOC_IF_ERROR_RETURN(WRITE_OOBFC_TX_IDLEr(unit, 17864 mmu_data->_soc_tr3_oobfc_tx_idle)); 17865 SOC_IF_ERROR_RETURN(WRITE_OOBIF_DEBUGr(unit, 17866 mmu_data->_soc_tr3_oobif_debug)); 17867 SOC_IF_ERROR_RETURN(WRITE_OP_SP_BST_THRESHOLD_SELr(unit, 17868 mmu_data->_soc_tr3_op_sp_bst_threshold_sel)); 17869 SOC_IF_ERROR_RETURN(WRITE_OP_THR_CONFIG_PLUSr(unit, 17870 mmu_data->_soc_tr3_op_thr_config_plus)); 17871 SOC_IF_ERROR_RETURN(WRITE_OVQ_BUBBLE_SIZE_REGr(unit, 17872 mmu_data->_soc_tr3_ovq_bubble_size_reg)); 17873 SOC_IF_ERROR_RETURN(WRITE_OVQ_BUBBLE_THRESHOLDr(unit, 17874 mmu_data->_soc_tr3_ovq_bubble_threshold)); 17875 SOC_IF_ERROR_RETURN(WRITE_OVQ_DFTr(unit, mmu_data->_soc_tr3_ovq_dft)); 17876 SOC_IF_ERROR_RETURN(WRITE_OVQ_DROP_THRESHOLD_REGr(unit, 17877 mmu_data->_soc_tr3_ovq_drop_threshold_reg)); 17878 SOC_IF_ERROR_RETURN(WRITE_OVQ_FLOWCONTROL_THRESHOLDr(unit, 17879 mmu_data->_soc_tr3_ovq_flowcontrol_threshold)); 17880 SOC_IF_ERROR_RETURN(WRITE_OVQ_LINKED_LIST_SELECTr(unit, 17881 mmu_data->_soc_tr3_ovq_linked_list_select)); 17882 SOC_IF_ERROR_RETURN(WRITE_PARITY_CHK_ENr(unit, 17883 mmu_data->_soc_tr3_parity_chk_en)); 17884 SOC_IF_ERROR_RETURN(WRITE_PKTAGINGLIMIT0r(unit, 17885 mmu_data->_soc_tr3_pktaginglimit0)); 17886 SOC_IF_ERROR_RETURN(WRITE_PKTAGINGLIMIT1r(unit, 17887 mmu_data->_soc_tr3_pktaginglimit1)); 17888 SOC_IF_ERROR_RETURN(WRITE_PKTAGINGTIMERr(unit, 17889 mmu_data->_soc_tr3_pktagingtimer)); 17890 SOC_IF_ERROR_RETURN(WRITE_PORT_OVQ_PAUSE_ENABLE_64r(unit, 17891 mmu_data->_soc_tr3_port_ovq_pause_enable_64)); 17892 SOC_IF_ERROR_RETURN(WRITE_PORT_PFC_CFG0r(unit, 17893 mmu_data->_soc_tr3_port_pfc_cfg0)); 17894 SOC_IF_ERROR_RETURN(WRITE_PORT_PFC_CFG1r(unit, 17895 mmu_data->_soc_tr3_port_pfc_cfg1)); 17896 SOC_IF_ERROR_RETURN(WRITE_PWR_WATCH_DOG_CONTROL_MBr(unit, 17897 mmu_data->_soc_tr3_pwr_watch_dog_control_mb)); 17898 SOC_IF_ERROR_RETURN(WRITE_SCQM_QGRPr(unit, mmu_data->_soc_tr3_scqm_qgrp)); 17899 SOC_IF_ERROR_RETURN(WRITE_THDO_INTEROP_CONFIGr(unit, 17900 mmu_data->_soc_tr3_thdo_interop_config)); 17901 SOC_IF_ERROR_RETURN(WRITE_THDO_RDE_SP_SELECTr(unit, 17902 mmu_data->_soc_tr3_thdo_rde_sp_select)); 17903 SOC_IF_ERROR_RETURN(WRITE_THDO_UNICAST_DROP_EMIRROR_CNTr(unit, 17904 mmu_data->_soc_tr3_thdo_unicast_drop_emirror_cnt)); 17905 SOC_IF_ERROR_RETURN(WRITE_TIME_DOMAINr(unit, 17906 mmu_data->_soc_tr3_time_domain)); 17907 SOC_IF_ERROR_RETURN(WRITE_UCQ_CONFIGr(unit, mmu_data->_soc_tr3_ucq_config)); 17908 SOC_IF_ERROR_RETURN(WRITE_WAMU_POOL_SELECTr(unit, 17909 mmu_data->_soc_tr3_wamu_pool_select)); 17910 SOC_IF_ERROR_RETURN(WRITE_WAMU_PRI_GRPr(unit, 17911 mmu_data->_soc_tr3_wamu_pri_grp)); 17912 SOC_IF_ERROR_RETURN(WRITE_WAMUDROPCNT2BERRr(unit, 17913 mmu_data->_soc_tr3_wamudropcnt2berr)); 17914 SOC_IF_ERROR_RETURN(WRITE_WAMUNONFRAGMCNTr(unit, 17915 mmu_data->_soc_tr3_wamunonfragmcnt)); 17916 SOC_IF_ERROR_RETURN(WRITE_WAMUREASMBCNTr(unit, 17917 mmu_data->_soc_tr3_wamureasmbcnt)); 17918 SOC_IF_ERROR_RETURN(WRITE_WAMUDROPCNTAGINGr(unit, 17919 mmu_data->_soc_tr3_wamudropcntaging)); 17920 SOC_IF_ERROR_RETURN(WRITE_WAMUDROPCNTGLBTHDIPKTr(unit, 17921 mmu_data->_soc_tr3_wamudropcntglbthdipkt)); 17922 SOC_IF_ERROR_RETURN(WRITE_WAMUDROPCNTLENr(unit, 17923 mmu_data->_soc_tr3_wamudropcntlen)); 17924 SOC_IF_ERROR_RETURN(WRITE_WAMUDROPCNTLENBYTEr(unit, 17925 mmu_data->_soc_tr3_wamudropcntlenbyte)); 17926 SOC_IF_ERROR_RETURN(WRITE_WAMUDROPCNTLRUr(unit, 17927 mmu_data->_soc_tr3_wamudropcntlru)); 17928 SOC_IF_ERROR_RETURN(WRITE_WAMUDROPCNTNOLRUr(unit, 17929 mmu_data->_soc_tr3_wamudropcntnolru)); 17930 SOC_IF_ERROR_RETURN(WRITE_WAMUDROPCNTNOLRUBYTEr(unit, 17931 mmu_data->_soc_tr3_wamudropcntnolrubyte)); 17932 SOC_IF_ERROR_RETURN(WRITE_WAMUDROPCNTTHDIBYTEr(unit, 17933 mmu_data->_soc_tr3_wamudropcntthdibyte)); 17934 SOC_IF_ERROR_RETURN(WRITE_WAMUDROPCNTTHDIPKTr(unit, 17935 mmu_data->_soc_tr3_wamudropcntthdipkt)); 17936 SOC_IF_ERROR_RETURN(WRITE_WAMUDROPCNTTYPEr(unit, 17937 mmu_data->_soc_tr3_wamudropcnttype)); 17938 SOC_IF_ERROR_RETURN(WRITE_WRED_REFRESH_CONTROLr(unit, 17939 mmu_data->_soc_tr3_wred_refresh_control)); 17940 17941 if (!SOC_IS_HELIX4(unit) && SOC_IS_TRIUMPH3(unit)) { 17942 SOC_IF_ERROR_RETURN(WRITE_HSP_CONFIGr(unit, 17943 mmu_data->_soc_tr3_hsp_config)); 17944 PBMP_C_ITER(unit, port) { 17945 SOC_IF_ERROR_RETURN(WRITE_HES_L0_CONFIGr(unit, port, 17946 mmu_data->_soc_tr3_hes_l0_config[port])); 17947 SOC_IF_ERROR_RETURN(WRITE_HES_PORT_CONFIGr(unit, port, 17948 mmu_data->_soc_tr3_hes_port_config[port])); 17949 SOC_IF_ERROR_RETURN(WRITE_HES_Q_COSMASKr(unit, port, 17950 mmu_data->_soc_tr3_hes_q_cosmask[port])); 17951 SOC_IF_ERROR_RETURN(WRITE_HES_Q_MINSPr(unit, port, 17952 mmu_data->_soc_tr3_hes_q_minsp[port])); 17953 for (idx=0; idx<20; idx++) { 17954 SOC_IF_ERROR_RETURN(WRITE_HES_Q_COSWEIGHTSr(unit, port, idx, 17955 mmu_data->_soc_tr3_hes_q_cosweights[port][idx])); 17956 } 17957 for (idx=0; idx<10; idx++) { 17958 SOC_IF_ERROR_RETURN(WRITE_L0_COSWEIGHTSr(unit, port, idx, 17959 mmu_data->_soc_tr3_l0_cosweights[port][idx])); 17960 } 17961 } 17962 } 17963 return SOC_E_NONE; 17964 } 17965 17966 #define _SOC_TR3_MEM_TBL_SZIE(unit, mem) \ 17967 4*soc_mem_entry_words(unit, mem) * \ 17968 (soc_mem_index_max(unit, mem) - soc_mem_index_min(unit, mem)+1) 17969 17970 int 17971 soc_tr3_mmu_store_alloc(int unit) 17972 { 17973 _soc_tr3_base_index_tbl[unit] = soc_cm_salloc(unit, 17974 _SOC_TR3_MEM_TBL_SZIE(unit, MMU_INTFI_BASE_INDEX_TBLm), "MMU_INTFI_BASE_INDEX_TBLm"); 17975 if (_soc_tr3_base_index_tbl[unit] == NULL) { 17976 return SOC_E_MEMORY; 17977 } 17978 _soc_tr3_chfc_sysport_mapping[unit] = soc_cm_salloc(unit, 17979 _SOC_TR3_MEM_TBL_SZIE(unit, MMU_CHFC_SYSPORT_MAPPINGm), "MMU_CHFC_SYSPORT_MAPPINGm"); 17980 if (_soc_tr3_chfc_sysport_mapping[unit] == NULL) { 17981 return SOC_E_MEMORY; 17982 } 17983 _soc_tr3_ctr_color_drop[unit] = soc_cm_salloc(unit, 17984 _SOC_TR3_MEM_TBL_SZIE(unit, MMU_CTR_COLOR_DROP_MEMm), "MMU_CTR_COLOR_DROP_MEMm"); 17985 if (_soc_tr3_ctr_color_drop[unit] == NULL) { 17986 return SOC_E_MEMORY; 17987 } 17988 _soc_tr3_ctr_mc_drop[unit] = soc_cm_salloc(unit, 17989 _SOC_TR3_MEM_TBL_SZIE(unit, MMU_CTR_MC_DROP_MEMm), "MMU_CTR_MC_DROP_MEMm"); 17990 if (_soc_tr3_ctr_mc_drop[unit] == NULL) { 17991 return SOC_E_MEMORY; 17992 } 17993 _soc_tr3_ctr_uc_drop[unit] = soc_cm_salloc(unit, 17994 _SOC_TR3_MEM_TBL_SZIE(unit, MMU_CTR_UC_DROP_MEMm), "MMU_CTR_UC_DROP_MEMm"); 17995 if (_soc_tr3_ctr_uc_drop[unit] == NULL) { 17996 return SOC_E_MEMORY; 17997 } 17998 _soc_tr3_fc_map_tbl0[unit] = soc_cm_salloc(unit, 17999 _SOC_TR3_MEM_TBL_SZIE(unit, MMU_INTFI_FC_MAP_TBL0m), "MMU_INTFI_FC_MAP_TBL0m"); 18000 if (_soc_tr3_fc_map_tbl0[unit] == NULL) { 18001 return SOC_E_MEMORY; 18002 } 18003 _soc_tr3_fc_map_tbl1[unit] = soc_cm_salloc(unit, 18004 _SOC_TR3_MEM_TBL_SZIE(unit, MMU_INTFI_FC_MAP_TBL1m), "MMU_INTFI_FC_MAP_TBL1m"); 18005 if (_soc_tr3_fc_map_tbl1[unit] == NULL) { 18006 return SOC_E_MEMORY; 18007 } 18008 _soc_tr3_fc_map_tbl2[unit] = soc_cm_salloc(unit, 18009 _SOC_TR3_MEM_TBL_SZIE(unit, MMU_INTFI_FC_MAP_TBL2m), "MMU_INTFI_FC_MAP_TBL2m"); 18010 if (_soc_tr3_fc_map_tbl2[unit] == NULL) { 18011 return SOC_E_MEMORY; 18012 } 18013 _soc_tr3_fc_st_tbl0[unit] = soc_cm_salloc(unit, 18014 _SOC_TR3_MEM_TBL_SZIE(unit, MMU_INTFI_FC_ST_TBL0m), "MMU_INTFI_FC_ST_TBL0m"); 18015 if (_soc_tr3_fc_st_tbl0[unit] == NULL) { 18016 return SOC_E_MEMORY; 18017 } 18018 _soc_tr3_fc_st_tbl1[unit] = soc_cm_salloc(unit, 18019 _SOC_TR3_MEM_TBL_SZIE(unit, MMU_INTFI_FC_ST_TBL1m), "MMU_INTFI_FC_ST_TBL1m"); 18020 if (_soc_tr3_fc_st_tbl1[unit] == NULL) { 18021 return SOC_E_MEMORY; 18022 } 18023 _soc_tr3_fc_st_tbl2[unit] = soc_cm_salloc(unit, 18024 _SOC_TR3_MEM_TBL_SZIE(unit, MMU_INTFI_FC_ST_TBL2m), "MMU_INTFI_FC_ST_TBL2m"); 18025 if (_soc_tr3_fc_st_tbl2[unit] == NULL) { 18026 return SOC_E_MEMORY; 18027 } 18028 _soc_tr3_intfo_tc2pri_mapping[unit] = soc_cm_salloc(unit, 18029 _SOC_TR3_MEM_TBL_SZIE(unit, MMU_INTFO_TC2PRI_MAPPINGm), "MMU_INTFO_TC2PRI_MAPPINGm"); 18030 if (_soc_tr3_intfo_tc2pri_mapping[unit] == NULL) { 18031 return SOC_E_MEMORY; 18032 } 18033 _soc_tr3_ipmc_vlan[unit] = soc_cm_salloc(unit, 18034 _SOC_TR3_MEM_TBL_SZIE(unit, MMU_REPL_LIST_TBLm), "MMU_REPL_LIST_TBLm"); 18035 if (_soc_tr3_ipmc_vlan[unit] == NULL) { 18036 return SOC_E_MEMORY; 18037 } 18038 _soc_tr3_lls_l0_child_weight_cfg[unit] = soc_cm_salloc(unit, 18039 _SOC_TR3_MEM_TBL_SZIE(unit, LLS_L0_CHILD_WEIGHT_CFGm), "LLS_L0_CHILD_WEIGHT_CFGm"); 18040 if (_soc_tr3_lls_l0_child_weight_cfg[unit] == NULL) { 18041 return SOC_E_MEMORY; 18042 } 18043 _soc_tr3_lls_l0_config[unit] = soc_cm_salloc(unit, 18044 _SOC_TR3_MEM_TBL_SZIE(unit, LLS_L0_CONFIGm), "LLS_L0_CONFIGm"); 18045 if (_soc_tr3_lls_l0_config[unit] == NULL) { 18046 return SOC_E_MEMORY; 18047 } 18048 _soc_tr3_lls_l0_parent[unit] = soc_cm_salloc(unit, 18049 _SOC_TR3_MEM_TBL_SZIE(unit, LLS_L0_PARENTm), "LLS_L0_PARENTm"); 18050 if (_soc_tr3_lls_l0_parent[unit] == NULL) { 18051 return SOC_E_MEMORY; 18052 } 18053 _soc_tr3_lls_l1_child_weight_cfg[unit] = soc_cm_salloc(unit, 18054 _SOC_TR3_MEM_TBL_SZIE(unit, LLS_L1_CHILD_WEIGHT_CFGm), "LLS_L1_CHILD_WEIGHT_CFGm"); 18055 if (_soc_tr3_lls_l1_child_weight_cfg[unit] == NULL) { 18056 return SOC_E_MEMORY; 18057 } 18058 _soc_tr3_lls_l1_config[unit] = soc_cm_salloc(unit, 18059 _SOC_TR3_MEM_TBL_SZIE(unit, LLS_L1_CONFIGm), "LLS_L1_CONFIGm"); 18060 if (_soc_tr3_lls_l1_config[unit] == NULL) { 18061 return SOC_E_MEMORY; 18062 } 18063 _soc_tr3_lls_l1_parent[unit] = soc_cm_salloc(unit, 18064 _SOC_TR3_MEM_TBL_SZIE(unit, LLS_L1_PARENTm), "LLS_L1_PARENTm"); 18065 if (_soc_tr3_lls_l1_parent[unit] == NULL) { 18066 return SOC_E_MEMORY; 18067 } 18068 _soc_tr3_lls_l2_child_weight_cfg[unit] = soc_cm_salloc(unit, 18069 _SOC_TR3_MEM_TBL_SZIE(unit, LLS_L2_CHILD_WEIGHT_CFGm), "LLS_L2_CHILD_WEIGHT_CFGm"); 18070 if (_soc_tr3_lls_l2_child_weight_cfg[unit] == NULL) { 18071 return SOC_E_MEMORY; 18072 } 18073 _soc_tr3_lls_l2_parent[unit] = soc_cm_salloc(unit, 18074 _SOC_TR3_MEM_TBL_SZIE(unit, LLS_L2_PARENTm), "LLS_L2_PARENTm"); 18075 if (_soc_tr3_lls_l2_parent[unit] == NULL) { 18076 return SOC_E_MEMORY; 18077 } 18078 _soc_tr3_lls_port_config[unit] = soc_cm_salloc(unit, 18079 _SOC_TR3_MEM_TBL_SZIE(unit, LLS_PORT_CONFIGm), "LLS_PORT_CONFIGm"); 18080 if (_soc_tr3_lls_port_config[unit] == NULL) { 18081 return SOC_E_MEMORY; 18082 } 18083 _soc_tr3_lls_port_tdm[unit] = soc_cm_salloc(unit, 18084 _SOC_TR3_MEM_TBL_SZIE(unit, LLS_PORT_TDMm)/2, "LLS_PORT_TDMm"); 18085 if (_soc_tr3_lls_port_tdm[unit] == NULL) { 18086 return SOC_E_MEMORY; 18087 } 18088 _soc_tr3_mmu_mtro_config_l0_mem[unit] = soc_cm_salloc(unit, 18089 _SOC_TR3_MEM_TBL_SZIE(unit, MMU_MTRO_L0_MEMm), "MMU_MTRO_L0_MEMm"); 18090 if (_soc_tr3_mmu_mtro_config_l0_mem[unit] == NULL) { 18091 return SOC_E_MEMORY; 18092 } 18093 _soc_tr3_mmu_mtro_config_l1_mem[unit] = soc_cm_salloc(unit, 18094 _SOC_TR3_MEM_TBL_SZIE(unit, MMU_MTRO_L1_MEMm), "MMU_MTRO_L1_MEMm"); 18095 if (_soc_tr3_mmu_mtro_config_l1_mem[unit] == NULL) { 18096 return SOC_E_MEMORY; 18097 } 18098 _soc_tr3_mmu_mtro_config_l2_mem[unit] = soc_cm_salloc(unit, 18099 _SOC_TR3_MEM_TBL_SZIE(unit, MMU_MTRO_L2_MEMm), "MMU_MTRO_L2_MEMm"); 18100 if (_soc_tr3_mmu_mtro_config_l2_mem[unit] == NULL) { 18101 return SOC_E_MEMORY; 18102 } 18103 _soc_tr3_mmu_qcn_cnm_counter[unit] = soc_cm_salloc(unit, 18104 _SOC_TR3_MEM_TBL_SZIE(unit, MMU_QCN_CNM_COUNTERm), "MMU_QCN_CNM_COUNTERm"); 18105 if (_soc_tr3_mmu_qcn_cnm_counter[unit] == NULL) { 18106 return SOC_E_MEMORY; 18107 } 18108 _soc_tr3_mmu_thdo_offset_qgroup[unit] = soc_cm_salloc(unit, 18109 _SOC_TR3_MEM_TBL_SZIE(unit, MMU_THDO_OFFSET_QGROUPm), "MMU_THDO_OFFSET_QGROUPm"); 18110 if (_soc_tr3_mmu_thdo_offset_qgroup[unit] == NULL) { 18111 return SOC_E_MEMORY; 18112 } 18113 _soc_tr3_mmu_thdo_offset_queue[unit] = soc_cm_salloc(unit, 18114 _SOC_TR3_MEM_TBL_SZIE(unit, MMU_THDO_OFFSET_QUEUEm), "MMU_THDO_OFFSET_QUEUEm"); 18115 if (_soc_tr3_mmu_thdo_offset_queue[unit] == NULL) { 18116 return SOC_E_MEMORY; 18117 } 18118 _soc_tr3_mmu_thdo_q_to_qgrp_map[unit] = soc_cm_salloc(unit, 18119 _SOC_TR3_MEM_TBL_SZIE(unit, MMU_THDO_Q_TO_QGRP_MAPm), "MMU_THDO_Q_TO_QGRP_MAPm"); 18120 if (_soc_tr3_mmu_thdo_q_to_qgrp_map[unit] == NULL) { 18121 return SOC_E_MEMORY; 18122 } 18123 _soc_tr3_mmu_wred_drop_curve_profile_0[unit] = soc_cm_salloc(unit, 18124 _SOC_TR3_MEM_TBL_SZIE(unit, MMU_WRED_DROP_CURVE_PROFILE_0m), 18125 "MMU_WRED_DROP_CURVE_PROFILE_0m"); 18126 if (_soc_tr3_mmu_wred_drop_curve_profile_0[unit] == NULL) { 18127 return SOC_E_MEMORY; 18128 } 18129 _soc_tr3_mmu_wred_drop_curve_profile_1[unit] = soc_cm_salloc(unit, 18130 _SOC_TR3_MEM_TBL_SZIE(unit, MMU_WRED_DROP_CURVE_PROFILE_1m), 18131 "MMU_WRED_DROP_CURVE_PROFILE_1m"); 18132 if (_soc_tr3_mmu_wred_drop_curve_profile_1[unit] == NULL) { 18133 return SOC_E_MEMORY; 18134 } 18135 _soc_tr3_mmu_wred_drop_curve_profile_2[unit] = soc_cm_salloc(unit, 18136 _SOC_TR3_MEM_TBL_SZIE(unit, MMU_WRED_DROP_CURVE_PROFILE_2m), 18137 "MMU_WRED_DROP_CURVE_PROFILE_2m"); 18138 if (_soc_tr3_mmu_wred_drop_curve_profile_2[unit] == NULL) { 18139 return SOC_E_MEMORY; 18140 } 18141 _soc_tr3_mmu_wred_drop_curve_profile_3[unit] = soc_cm_salloc(unit, 18142 _SOC_TR3_MEM_TBL_SZIE(unit, MMU_WRED_DROP_CURVE_PROFILE_3m), 18143 "MMU_WRED_DROP_CURVE_PROFILE_3m"); 18144 if (_soc_tr3_mmu_wred_drop_curve_profile_3[unit] == NULL) { 18145 return SOC_E_MEMORY; 18146 } 18147 _soc_tr3_mmu_wred_drop_curve_profile_4[unit] = soc_cm_salloc(unit, 18148 _SOC_TR3_MEM_TBL_SZIE(unit, MMU_WRED_DROP_CURVE_PROFILE_4m), 18149 "MMU_WRED_DROP_CURVE_PROFILE_4m"); 18150 if (_soc_tr3_mmu_wred_drop_curve_profile_4[unit] == NULL) { 18151 return SOC_E_MEMORY; 18152 } 18153 _soc_tr3_mmu_wred_drop_curve_profile_5[unit] = soc_cm_salloc(unit, 18154 _SOC_TR3_MEM_TBL_SZIE(unit, MMU_WRED_DROP_CURVE_PROFILE_5m), 18155 "MMU_WRED_DROP_CURVE_PROFILE_5m"); 18156 if (_soc_tr3_mmu_wred_drop_curve_profile_5[unit] == NULL) { 18157 return SOC_E_MEMORY; 18158 } 18159 _soc_tr3_mmu_wred_uc_queue_config[unit] = soc_cm_salloc(unit, 18160 _SOC_TR3_MEM_TBL_SZIE(unit, MMU_WRED_CONFIGm), "MMU_WRED_CONFIGm"); 18161 if (_soc_tr3_mmu_wred_uc_queue_config[unit] == NULL) { 18162 return SOC_E_MEMORY; 18163 } 18164 _soc_tr3_offset_map_tbl[unit] = soc_cm_salloc(unit, 18165 _SOC_TR3_MEM_TBL_SZIE(unit, MMU_INTFI_OFFSET_MAP_TBLm), "MMU_INTFI_OFFSET_MAP_TBLm"); 18166 if (_soc_tr3_offset_map_tbl[unit] == NULL) { 18167 return SOC_E_MEMORY; 18168 } 18169 18170 _soc_tr3_pfc_st_tbl[unit] = soc_cm_salloc(unit, 18171 _SOC_TR3_MEM_TBL_SZIE(unit, MMU_INTFI_PFC_ST_TBLm), "MMU_INTFI_PFC_ST_TBLm"); 18172 if (_soc_tr3_pfc_st_tbl[unit] == NULL) { 18173 return SOC_E_MEMORY; 18174 } 18175 _soc_tr3_qcn_enable[unit] = soc_cm_salloc(unit, 18176 _SOC_TR3_MEM_TBL_SZIE(unit, MMU_QCN_ENABLEm), "MMU_QCN_ENABLEm"); 18177 if (_soc_tr3_qcn_enable[unit] == NULL) { 18178 return SOC_E_MEMORY; 18179 } 18180 _soc_tr3_qcn_qfbtb[unit] = soc_cm_salloc(unit, 18181 _SOC_TR3_MEM_TBL_SZIE(unit, MMU_QCN_QFBTBm), "QCN_QFBTBm"); 18182 if (_soc_tr3_qcn_qfbtb[unit] == NULL) { 18183 return SOC_E_MEMORY; 18184 } 18185 _soc_tr3_qcn_sitb[unit] = soc_cm_salloc(unit, 18186 _SOC_TR3_MEM_TBL_SZIE(unit, MMU_QCN_SITBm), "MMU_QCN_SITBm"); 18187 if (_soc_tr3_qcn_sitb[unit] == NULL) { 18188 return SOC_E_MEMORY; 18189 } 18190 _soc_tr3_qcn_tbid_tbl[unit] = soc_cm_salloc(unit, 18191 _SOC_TR3_MEM_TBL_SZIE(unit, MMU_INTFO_QCN_TBID_TBLm), "QCN_TBID_TBLm"); 18192 if (_soc_tr3_qcn_tbid_tbl[unit] == NULL) { 18193 return SOC_E_MEMORY; 18194 } 18195 _soc_tr3_qcn_tov_tbl[unit] = soc_cm_salloc(unit, 18196 _SOC_TR3_MEM_TBL_SZIE(unit, MMU_INTFO_QCN_TOV_TBLm), "MMU_INTFO_QCN_TOV_TBLm"); 18197 if (_soc_tr3_qcn_tov_tbl[unit] == NULL) { 18198 return SOC_E_MEMORY; 18199 } 18200 _soc_tr3_repl_group[unit] = soc_cm_salloc(unit, 18201 _SOC_TR3_MEM_TBL_SZIE(unit, MMU_REPL_GROUPm), "MMU_REPL_GROUPm"); 18202 if (_soc_tr3_repl_group[unit] == NULL) { 18203 return SOC_E_MEMORY; 18204 } 18205 _soc_tr3_repl_head[unit] = soc_cm_salloc(unit, 18206 _SOC_TR3_MEM_TBL_SZIE(unit, MMU_REPL_HEAD_TBLm), "MMU_REPL_HEAD_TBLm"); 18207 if (_soc_tr3_repl_head[unit] == NULL) { 18208 return SOC_E_MEMORY; 18209 } 18210 _soc_tr3_st_trans_tbl[unit] = soc_cm_salloc(unit, 18211 _SOC_TR3_MEM_TBL_SZIE(unit, MMU_INTFI_ST_TRANS_TBLm), "MMU_INTFI_ST_TRANS_TBLm"); 18212 if (_soc_tr3_st_trans_tbl[unit] == NULL) { 18213 return SOC_E_MEMORY; 18214 } 18215 _soc_tr3_thdi_port_pg_config[unit] = soc_cm_salloc(unit, 18216 _SOC_TR3_MEM_TBL_SZIE(unit, THDI_PORT_PG_CONFIGm), "THDI_PORT_PG_CONFIGm"); 18217 if (_soc_tr3_thdi_port_pg_config[unit] == NULL) { 18218 return SOC_E_MEMORY; 18219 } 18220 _soc_tr3_thdi_port_sp_config[unit] = soc_cm_salloc(unit, 18221 _SOC_TR3_MEM_TBL_SZIE(unit, THDI_PORT_SP_CONFIGm), "THDI_PORT_SP_CONFIGm"); 18222 if (_soc_tr3_thdi_port_sp_config[unit] == NULL) { 18223 return SOC_E_MEMORY; 18224 } 18225 _soc_tr3_thdo_port_sp_config[unit] = soc_cm_salloc(unit, 18226 _SOC_TR3_MEM_TBL_SZIE(unit, MMU_THDO_CONFIG_PORTm), "MMU_THDO_CONFIG_PORTm"); 18227 if (_soc_tr3_thdo_port_sp_config[unit] == NULL) { 18228 return SOC_E_MEMORY; 18229 } 18230 _soc_tr3_thdo_uc_qgroup_config[unit] = soc_cm_salloc(unit, 18231 _SOC_TR3_MEM_TBL_SZIE(unit, MMU_THDO_CONFIG_QGROUPm), "MMU_THDO_CONFIG_QGROUPm"); 18232 18233 if (_soc_tr3_thdo_uc_qgroup_config[unit] == NULL) { 18234 return SOC_E_MEMORY; 18235 } 18236 _soc_tr3_thdo_uc_queue_config[unit] = soc_cm_salloc(unit, 18237 _SOC_TR3_MEM_TBL_SZIE(unit, MMU_THDO_CONFIG_QUEUEm), "MMU_THDO_CONFIG_QUEUEm"); 18238 18239 if (_soc_tr3_thdo_uc_queue_config[unit] == NULL) { 18240 return SOC_E_MEMORY; 18241 } 18242 _soc_tr3_wred_port_sp_drop_thd[unit] = soc_cm_salloc(unit, 18243 _SOC_TR3_MEM_TBL_SZIE(unit, MMU_WRED_PORT_SP_DROP_THDm), "MMU_WRED_PORT_SP_DROP_THDm"); 18244 if (_soc_tr3_wred_port_sp_drop_thd[unit] == NULL) { 18245 return SOC_E_MEMORY; 18246 } 18247 _soc_tr3_wred_qgroup_drop_thd[unit] = soc_cm_salloc(unit, 18248 _SOC_TR3_MEM_TBL_SZIE(unit, MMU_WRED_QGROUP_DROP_THDm), 18249 "MMU_WRED_QGROUP_DROP_THDm"); 18250 if (_soc_tr3_wred_qgroup_drop_thd[unit] == NULL) { 18251 return SOC_E_MEMORY; 18252 } 18253 _soc_tr3_wred_uc_queue_drop_thd_deq[unit] = soc_cm_salloc(unit, 18254 _SOC_TR3_MEM_TBL_SZIE(unit, MMU_WRED_UC_QUEUE_DROP_THD_DEQm), 18255 "MMU_WRED_UC_QUEUE_DROP_THD_DEQm"); 18256 if (_soc_tr3_wred_uc_queue_drop_thd_deq[unit] == NULL) { 18257 return SOC_E_MEMORY; 18258 } 18259 _soc_tr3_wred_uc_queue_drop_thd_enq[unit] = soc_cm_salloc(unit, 18260 _SOC_TR3_MEM_TBL_SZIE(unit, MMU_WRED_UC_QUEUE_DROP_THD_ENQm), 18261 "MMU_WRED_UC_QUEUE_DROP_THD_ENQm"); 18262 if (_soc_tr3_wred_uc_queue_drop_thd_enq[unit] == NULL) { 18263 return SOC_E_MEMORY; 18264 } 18265 18266 _soc_tr3_iarb_tdm[unit] = soc_cm_salloc(unit, 18267 _SOC_TR3_MEM_TBL_SZIE(unit, IARB_TDM_TABLEm), 18268 "IARB_TDM_TABLEm"); 18269 if (_soc_tr3_iarb_tdm[unit] == NULL) { 18270 return SOC_E_MEMORY; 18271 } 18272 18273 _soc_tr3_mmu_data[unit] = soc_cm_salloc(unit, sizeof(_soc_tr3_mmu_data_t), 18274 "MMU store restore data"); 18275 if(_soc_tr3_mmu_data[unit] == NULL) { 18276 return SOC_E_MEMORY; 18277 } 18278 return SOC_E_NONE; 18279 } 18280 18281 void 18282 soc_tr3_mmu_store_free(int unit) 18283 { 18284 soc_cm_sfree(unit, _soc_tr3_base_index_tbl[unit]); 18285 soc_cm_sfree(unit, _soc_tr3_chfc_sysport_mapping[unit]); 18286 soc_cm_sfree(unit, _soc_tr3_ctr_color_drop[unit]); 18287 soc_cm_sfree(unit, _soc_tr3_ctr_mc_drop[unit]); 18288 soc_cm_sfree(unit, _soc_tr3_ctr_uc_drop[unit]); 18289 soc_cm_sfree(unit, _soc_tr3_fc_map_tbl0[unit]); 18290 soc_cm_sfree(unit, _soc_tr3_fc_map_tbl1[unit]); 18291 soc_cm_sfree(unit, _soc_tr3_fc_map_tbl2[unit]); 18292 soc_cm_sfree(unit, _soc_tr3_fc_st_tbl0[unit]); 18293 soc_cm_sfree(unit, _soc_tr3_fc_st_tbl1[unit]); 18294 soc_cm_sfree(unit, _soc_tr3_fc_st_tbl2[unit]); 18295 soc_cm_sfree(unit, _soc_tr3_intfo_tc2pri_mapping[unit]); 18296 soc_cm_sfree(unit, _soc_tr3_ipmc_vlan[unit]); 18297 soc_cm_sfree(unit, _soc_tr3_lls_l0_child_weight_cfg[unit]); 18298 soc_cm_sfree(unit, _soc_tr3_lls_l0_config[unit]); 18299 soc_cm_sfree(unit, _soc_tr3_lls_l0_parent[unit]); 18300 soc_cm_sfree(unit, _soc_tr3_lls_l1_child_weight_cfg[unit]); 18301 soc_cm_sfree(unit, _soc_tr3_lls_l1_config[unit]); 18302 soc_cm_sfree(unit, _soc_tr3_lls_l1_parent[unit]); 18303 soc_cm_sfree(unit, _soc_tr3_lls_l2_child_weight_cfg[unit]); 18304 soc_cm_sfree(unit, _soc_tr3_lls_l2_parent[unit]); 18305 soc_cm_sfree(unit, _soc_tr3_lls_port_config[unit]); 18306 soc_cm_sfree(unit, _soc_tr3_lls_port_tdm[unit]); 18307 soc_cm_sfree(unit, _soc_tr3_mmu_mtro_config_l0_mem[unit]); 18308 soc_cm_sfree(unit, _soc_tr3_mmu_mtro_config_l1_mem[unit]); 18309 soc_cm_sfree(unit, _soc_tr3_mmu_mtro_config_l2_mem[unit]); 18310 soc_cm_sfree(unit, _soc_tr3_mmu_qcn_cnm_counter[unit]); 18311 soc_cm_sfree(unit, _soc_tr3_mmu_thdo_offset_qgroup[unit]); 18312 soc_cm_sfree(unit, _soc_tr3_mmu_thdo_offset_queue[unit]); 18313 soc_cm_sfree(unit, _soc_tr3_mmu_thdo_q_to_qgrp_map[unit]); 18314 soc_cm_sfree(unit, _soc_tr3_mmu_wred_drop_curve_profile_0[unit]); 18315 soc_cm_sfree(unit, _soc_tr3_mmu_wred_drop_curve_profile_1[unit]); 18316 soc_cm_sfree(unit, _soc_tr3_mmu_wred_drop_curve_profile_2[unit]); 18317 soc_cm_sfree(unit, _soc_tr3_mmu_wred_drop_curve_profile_3[unit]); 18318 soc_cm_sfree(unit, _soc_tr3_mmu_wred_drop_curve_profile_4[unit]); 18319 soc_cm_sfree(unit, _soc_tr3_mmu_wred_drop_curve_profile_5[unit]); 18320 soc_cm_sfree(unit, _soc_tr3_mmu_wred_uc_queue_config[unit]); 18321 soc_cm_sfree(unit, _soc_tr3_offset_map_tbl[unit]); 18322 soc_cm_sfree(unit, _soc_tr3_pfc_st_tbl[unit]); 18323 soc_cm_sfree(unit, _soc_tr3_qcn_enable[unit]); 18324 soc_cm_sfree(unit, _soc_tr3_qcn_qfbtb[unit]); 18325 soc_cm_sfree(unit, _soc_tr3_qcn_sitb[unit]); 18326 soc_cm_sfree(unit, _soc_tr3_qcn_tbid_tbl[unit]); 18327 soc_cm_sfree(unit, _soc_tr3_qcn_tov_tbl[unit]); 18328 soc_cm_sfree(unit, _soc_tr3_repl_group[unit]); 18329 soc_cm_sfree(unit, _soc_tr3_repl_head[unit]); 18330 soc_cm_sfree(unit, _soc_tr3_st_trans_tbl[unit]); 18331 soc_cm_sfree(unit, _soc_tr3_thdi_port_pg_config[unit]); 18332 soc_cm_sfree(unit, _soc_tr3_thdi_port_sp_config[unit]); 18333 soc_cm_sfree(unit, _soc_tr3_thdo_port_sp_config[unit]); 18334 soc_cm_sfree(unit, _soc_tr3_thdo_uc_qgroup_config[unit]); 18335 soc_cm_sfree(unit, _soc_tr3_thdo_uc_queue_config[unit]); 18336 soc_cm_sfree(unit, _soc_tr3_wred_port_sp_drop_thd[unit]); 18337 soc_cm_sfree(unit, _soc_tr3_wred_qgroup_drop_thd[unit]); 18338 soc_cm_sfree(unit, _soc_tr3_wred_uc_queue_drop_thd_deq[unit]); 18339 soc_cm_sfree(unit, _soc_tr3_wred_uc_queue_drop_thd_enq[unit]); 18340 soc_cm_sfree(unit, _soc_tr3_iarb_tdm[unit]); 18341 soc_cm_sfree(unit, _soc_tr3_mmu_data[unit]); 18342 } 18343 18344 int 18345 soc_tr3_mmu_memory_store(int unit) 18346 { 18347 18348 SOC_IF_ERROR_RETURN(_soc_tr3_tdm_store(unit)); 18349 18350 SOC_IF_ERROR_RETURN(soc_mem_read_range(unit, MMU_INTFI_BASE_INDEX_TBLm, MEM_BLOCK_ANY, 18351 soc_mem_index_min(unit, MMU_INTFI_BASE_INDEX_TBLm), 18352 soc_mem_index_max(unit, MMU_INTFI_BASE_INDEX_TBLm), 18353 _soc_tr3_base_index_tbl[unit])); 18354 SOC_IF_ERROR_RETURN(soc_mem_read_range(unit, MMU_CHFC_SYSPORT_MAPPINGm, MEM_BLOCK_ANY, 18355 soc_mem_index_min(unit, MMU_CHFC_SYSPORT_MAPPINGm), 18356 soc_mem_index_max(unit, MMU_CHFC_SYSPORT_MAPPINGm), 18357 _soc_tr3_chfc_sysport_mapping[unit])); 18358 SOC_IF_ERROR_RETURN(soc_mem_read_range(unit, MMU_CTR_COLOR_DROP_MEMm, MEM_BLOCK_ANY, 18359 soc_mem_index_min(unit, MMU_CTR_COLOR_DROP_MEMm), 18360 soc_mem_index_max(unit, MMU_CTR_COLOR_DROP_MEMm), 18361 _soc_tr3_ctr_color_drop[unit])); 18362 SOC_IF_ERROR_RETURN(soc_mem_read_range(unit, MMU_CTR_MC_DROP_MEMm, MEM_BLOCK_ANY, 18363 soc_mem_index_min(unit, MMU_CTR_MC_DROP_MEMm), 18364 soc_mem_index_max(unit, MMU_CTR_MC_DROP_MEMm), 18365 _soc_tr3_ctr_mc_drop[unit])); 18366 SOC_IF_ERROR_RETURN(soc_mem_read_range(unit, MMU_CTR_UC_DROP_MEMm, MEM_BLOCK_ANY, 18367 soc_mem_index_min(unit, MMU_CTR_UC_DROP_MEMm), 18368 soc_mem_index_max(unit, MMU_CTR_UC_DROP_MEMm), 18369 _soc_tr3_ctr_uc_drop[unit])); 18370 SOC_IF_ERROR_RETURN(soc_mem_read_range(unit, MMU_INTFI_FC_MAP_TBL0m, MEM_BLOCK_ANY, 18371 soc_mem_index_min(unit, MMU_INTFI_FC_MAP_TBL0m), 18372 soc_mem_index_max(unit, MMU_INTFI_FC_MAP_TBL0m), 18373 _soc_tr3_fc_map_tbl0[unit])); 18374 SOC_IF_ERROR_RETURN(soc_mem_read_range(unit, MMU_INTFI_FC_MAP_TBL1m, MEM_BLOCK_ANY, 18375 soc_mem_index_min(unit, MMU_INTFI_FC_MAP_TBL1m), 18376 soc_mem_index_max(unit, MMU_INTFI_FC_MAP_TBL1m), 18377 _soc_tr3_fc_map_tbl1[unit])); 18378 SOC_IF_ERROR_RETURN(soc_mem_read_range(unit, MMU_INTFI_FC_MAP_TBL2m, MEM_BLOCK_ANY, 18379 soc_mem_index_min(unit, MMU_INTFI_FC_MAP_TBL2m), 18380 soc_mem_index_max(unit, MMU_INTFI_FC_MAP_TBL2m), 18381 _soc_tr3_fc_map_tbl2[unit])); 18382 SOC_IF_ERROR_RETURN(soc_mem_read_range(unit, MMU_INTFI_FC_ST_TBL0m, MEM_BLOCK_ANY, 18383 soc_mem_index_min(unit, MMU_INTFI_FC_ST_TBL0m), 18384 soc_mem_index_max(unit, MMU_INTFI_FC_ST_TBL0m), 18385 _soc_tr3_fc_st_tbl0[unit])); 18386 SOC_IF_ERROR_RETURN(soc_mem_read_range(unit, MMU_INTFI_FC_ST_TBL1m, MEM_BLOCK_ANY, 18387 soc_mem_index_min(unit, MMU_INTFI_FC_ST_TBL1m), 18388 soc_mem_index_max(unit, MMU_INTFI_FC_ST_TBL1m), 18389 _soc_tr3_fc_st_tbl1[unit])); 18390 SOC_IF_ERROR_RETURN(soc_mem_read_range(unit, MMU_INTFI_FC_ST_TBL2m, MEM_BLOCK_ANY, 18391 soc_mem_index_min(unit, MMU_INTFI_FC_ST_TBL2m), 18392 soc_mem_index_max(unit, MMU_INTFI_FC_ST_TBL2m), 18393 _soc_tr3_fc_st_tbl2[unit])); 18394 SOC_IF_ERROR_RETURN(soc_mem_read_range(unit, MMU_INTFO_TC2PRI_MAPPINGm, MEM_BLOCK_ANY, 18395 soc_mem_index_min(unit, MMU_INTFO_TC2PRI_MAPPINGm), 18396 soc_mem_index_max(unit, MMU_INTFO_TC2PRI_MAPPINGm), 18397 _soc_tr3_intfo_tc2pri_mapping[unit])); 18398 SOC_IF_ERROR_RETURN(soc_mem_read_range(unit, MMU_REPL_LIST_TBLm, MEM_BLOCK_ANY, 18399 soc_mem_index_min(unit, MMU_REPL_LIST_TBLm), 18400 soc_mem_index_max(unit, MMU_REPL_LIST_TBLm), 18401 _soc_tr3_ipmc_vlan[unit])); 18402 SOC_IF_ERROR_RETURN(soc_mem_read_range(unit, LLS_L0_CHILD_WEIGHT_CFGm, MEM_BLOCK_ANY, 18403 soc_mem_index_min(unit, LLS_L0_CHILD_WEIGHT_CFGm), 18404 soc_mem_index_max(unit, LLS_L0_CHILD_WEIGHT_CFGm), 18405 _soc_tr3_lls_l0_child_weight_cfg[unit])); 18406 SOC_IF_ERROR_RETURN(soc_mem_read_range(unit, LLS_L0_CONFIGm, MEM_BLOCK_ANY, 18407 soc_mem_index_min(unit, LLS_L0_CONFIGm), 18408 soc_mem_index_max(unit, LLS_L0_CONFIGm), 18409 _soc_tr3_lls_l0_config[unit])); 18410 SOC_IF_ERROR_RETURN(soc_mem_read_range(unit, LLS_L0_PARENTm, MEM_BLOCK_ANY, 18411 soc_mem_index_min(unit, LLS_L0_PARENTm), 18412 soc_mem_index_max(unit, LLS_L0_PARENTm), 18413 _soc_tr3_lls_l0_parent[unit])); 18414 SOC_IF_ERROR_RETURN(soc_mem_read_range(unit, LLS_L1_CHILD_WEIGHT_CFGm, MEM_BLOCK_ANY, 18415 soc_mem_index_min(unit, LLS_L1_CHILD_WEIGHT_CFGm), 18416 soc_mem_index_max(unit, LLS_L1_CHILD_WEIGHT_CFGm), 18417 _soc_tr3_lls_l1_child_weight_cfg[unit])); 18418 SOC_IF_ERROR_RETURN(soc_mem_read_range(unit, LLS_L1_CONFIGm, MEM_BLOCK_ANY, 18419 soc_mem_index_min(unit, LLS_L1_CONFIGm), 18420 soc_mem_index_max(unit, LLS_L1_CONFIGm), 18421 _soc_tr3_lls_l1_config[unit])); 18422 SOC_IF_ERROR_RETURN(soc_mem_read_range(unit, LLS_L1_PARENTm, MEM_BLOCK_ANY, 18423 soc_mem_index_min(unit, LLS_L1_PARENTm), 18424 soc_mem_index_max(unit, LLS_L1_PARENTm), 18425 _soc_tr3_lls_l1_parent[unit])); 18426 SOC_IF_ERROR_RETURN(soc_mem_read_range(unit, LLS_L2_CHILD_WEIGHT_CFGm, MEM_BLOCK_ANY, 18427 soc_mem_index_min(unit, LLS_L2_CHILD_WEIGHT_CFGm), 18428 soc_mem_index_max(unit, LLS_L2_CHILD_WEIGHT_CFGm), 18429 _soc_tr3_lls_l2_child_weight_cfg[unit])); 18430 SOC_IF_ERROR_RETURN(soc_mem_read_range(unit, LLS_L2_PARENTm, MEM_BLOCK_ANY, 18431 soc_mem_index_min(unit, LLS_L2_PARENTm), 18432 soc_mem_index_max(unit, LLS_L2_PARENTm), 18433 _soc_tr3_lls_l2_parent[unit])); 18434 SOC_IF_ERROR_RETURN(soc_mem_read_range(unit, LLS_PORT_CONFIGm, MEM_BLOCK_ANY, 18435 soc_mem_index_min(unit, LLS_PORT_CONFIGm), 18436 soc_mem_index_max(unit, LLS_PORT_CONFIGm), 18437 _soc_tr3_lls_port_config[unit])); 18438 SOC_IF_ERROR_RETURN(soc_mem_read_range(unit, MMU_MTRO_L0_MEMm, MEM_BLOCK_ANY, 18439 soc_mem_index_min(unit, MMU_MTRO_L0_MEMm), 18440 soc_mem_index_max(unit, MMU_MTRO_L0_MEMm), 18441 _soc_tr3_mmu_mtro_config_l0_mem[unit])); 18442 SOC_IF_ERROR_RETURN(soc_mem_read_range(unit, MMU_MTRO_L1_MEMm, MEM_BLOCK_ANY, 18443 soc_mem_index_min(unit, MMU_MTRO_L1_MEMm), 18444 soc_mem_index_max(unit, MMU_MTRO_L1_MEMm), 18445 _soc_tr3_mmu_mtro_config_l1_mem[unit])); 18446 SOC_IF_ERROR_RETURN(soc_mem_read_range(unit, MMU_MTRO_L2_MEMm, MEM_BLOCK_ANY, 18447 soc_mem_index_min(unit, MMU_MTRO_L2_MEMm), 18448 soc_mem_index_max(unit, MMU_MTRO_L2_MEMm), 18449 _soc_tr3_mmu_mtro_config_l2_mem[unit])); 18450 SOC_IF_ERROR_RETURN(soc_mem_read_range(unit, MMU_QCN_CNM_COUNTERm, MEM_BLOCK_ANY, 18451 soc_mem_index_min(unit, MMU_QCN_CNM_COUNTERm), 18452 soc_mem_index_max(unit, MMU_QCN_CNM_COUNTERm), 18453 _soc_tr3_mmu_qcn_cnm_counter[unit])); 18454 SOC_IF_ERROR_RETURN(soc_mem_read_range(unit, MMU_THDO_OFFSET_QGROUPm, MEM_BLOCK_ANY, 18455 soc_mem_index_min(unit, MMU_THDO_OFFSET_QGROUPm), 18456 soc_mem_index_max(unit, MMU_THDO_OFFSET_QGROUPm), 18457 _soc_tr3_mmu_thdo_offset_qgroup[unit])); 18458 SOC_IF_ERROR_RETURN(soc_mem_read_range(unit, MMU_THDO_OFFSET_QUEUEm, MEM_BLOCK_ANY, 18459 soc_mem_index_min(unit, MMU_THDO_OFFSET_QUEUEm), 18460 soc_mem_index_max(unit, MMU_THDO_OFFSET_QUEUEm), 18461 _soc_tr3_mmu_thdo_offset_queue[unit])); 18462 SOC_IF_ERROR_RETURN(soc_mem_read_range(unit, MMU_THDO_Q_TO_QGRP_MAPm, MEM_BLOCK_ANY, 18463 soc_mem_index_min(unit, MMU_THDO_Q_TO_QGRP_MAPm), 18464 soc_mem_index_max(unit, MMU_THDO_Q_TO_QGRP_MAPm), 18465 _soc_tr3_mmu_thdo_q_to_qgrp_map[unit])); 18466 SOC_IF_ERROR_RETURN(soc_mem_read_range(unit, MMU_WRED_DROP_CURVE_PROFILE_0m, MEM_BLOCK_ANY, 18467 soc_mem_index_min(unit, MMU_WRED_DROP_CURVE_PROFILE_0m), 18468 soc_mem_index_max(unit, MMU_WRED_DROP_CURVE_PROFILE_0m), 18469 _soc_tr3_mmu_wred_drop_curve_profile_0[unit])); 18470 SOC_IF_ERROR_RETURN(soc_mem_read_range(unit, MMU_WRED_DROP_CURVE_PROFILE_1m, MEM_BLOCK_ANY, 18471 soc_mem_index_min(unit, MMU_WRED_DROP_CURVE_PROFILE_1m), 18472 soc_mem_index_max(unit, MMU_WRED_DROP_CURVE_PROFILE_1m), 18473 _soc_tr3_mmu_wred_drop_curve_profile_1[unit])); 18474 SOC_IF_ERROR_RETURN(soc_mem_read_range(unit, MMU_WRED_DROP_CURVE_PROFILE_2m, MEM_BLOCK_ANY, 18475 soc_mem_index_min(unit, MMU_WRED_DROP_CURVE_PROFILE_2m), 18476 soc_mem_index_max(unit, MMU_WRED_DROP_CURVE_PROFILE_2m), 18477 _soc_tr3_mmu_wred_drop_curve_profile_2[unit])); 18478 SOC_IF_ERROR_RETURN(soc_mem_read_range(unit, MMU_WRED_DROP_CURVE_PROFILE_3m, MEM_BLOCK_ANY, 18479 soc_mem_index_min(unit, MMU_WRED_DROP_CURVE_PROFILE_3m), 18480 soc_mem_index_max(unit, MMU_WRED_DROP_CURVE_PROFILE_3m), 18481 _soc_tr3_mmu_wred_drop_curve_profile_3[unit])); 18482 SOC_IF_ERROR_RETURN(soc_mem_read_range(unit, MMU_WRED_DROP_CURVE_PROFILE_4m, MEM_BLOCK_ANY, 18483 soc_mem_index_min(unit, MMU_WRED_DROP_CURVE_PROFILE_4m), 18484 soc_mem_index_max(unit, MMU_WRED_DROP_CURVE_PROFILE_4m), 18485 _soc_tr3_mmu_wred_drop_curve_profile_4[unit])); 18486 SOC_IF_ERROR_RETURN(soc_mem_read_range(unit, MMU_WRED_DROP_CURVE_PROFILE_5m, MEM_BLOCK_ANY, 18487 soc_mem_index_min(unit, MMU_WRED_DROP_CURVE_PROFILE_5m), 18488 soc_mem_index_max(unit, MMU_WRED_DROP_CURVE_PROFILE_5m), 18489 _soc_tr3_mmu_wred_drop_curve_profile_5[unit])); 18490 SOC_IF_ERROR_RETURN(soc_mem_read_range(unit, MMU_WRED_CONFIGm, MEM_BLOCK_ANY, 18491 soc_mem_index_min(unit, MMU_WRED_CONFIGm), 18492 soc_mem_index_max(unit, MMU_WRED_CONFIGm), 18493 _soc_tr3_mmu_wred_uc_queue_config[unit])); 18494 SOC_IF_ERROR_RETURN(soc_mem_read_range(unit, MMU_INTFI_OFFSET_MAP_TBLm, MEM_BLOCK_ANY, 18495 soc_mem_index_min(unit, MMU_INTFI_OFFSET_MAP_TBLm), 18496 soc_mem_index_max(unit, MMU_INTFI_OFFSET_MAP_TBLm), 18497 _soc_tr3_offset_map_tbl[unit])); 18498 SOC_IF_ERROR_RETURN(soc_mem_read_range(unit, MMU_INTFI_PFC_ST_TBLm, MEM_BLOCK_ANY, 18499 soc_mem_index_min(unit, MMU_INTFI_PFC_ST_TBLm), 18500 soc_mem_index_max(unit, MMU_INTFI_PFC_ST_TBLm), 18501 _soc_tr3_pfc_st_tbl[unit])); 18502 SOC_IF_ERROR_RETURN(soc_mem_read_range(unit, MMU_QCN_ENABLEm , MEM_BLOCK_ANY, 18503 soc_mem_index_min(unit, MMU_QCN_ENABLEm ), 18504 soc_mem_index_max(unit, MMU_QCN_ENABLEm ), 18505 _soc_tr3_qcn_enable[unit])); 18506 SOC_IF_ERROR_RETURN(soc_mem_read_range(unit, MMU_QCN_QFBTBm , MEM_BLOCK_ANY, 18507 soc_mem_index_min(unit, MMU_QCN_QFBTBm ), 18508 soc_mem_index_max(unit, MMU_QCN_QFBTBm ), 18509 _soc_tr3_qcn_qfbtb[unit])); 18510 SOC_IF_ERROR_RETURN(soc_mem_read_range(unit, MMU_QCN_SITBm , MEM_BLOCK_ANY, 18511 soc_mem_index_min(unit, MMU_QCN_SITBm ), 18512 soc_mem_index_max(unit, MMU_QCN_SITBm ), 18513 _soc_tr3_qcn_sitb[unit])); 18514 SOC_IF_ERROR_RETURN(soc_mem_read_range(unit, MMU_INTFO_QCN_TBID_TBLm , MEM_BLOCK_ANY, 18515 soc_mem_index_min(unit, MMU_INTFO_QCN_TBID_TBLm ), 18516 soc_mem_index_max(unit, MMU_INTFO_QCN_TBID_TBLm ), 18517 _soc_tr3_qcn_tbid_tbl[unit])); 18518 SOC_IF_ERROR_RETURN(soc_mem_read_range(unit, MMU_INTFO_QCN_TOV_TBLm , MEM_BLOCK_ANY, 18519 soc_mem_index_min(unit, MMU_INTFO_QCN_TOV_TBLm ), 18520 soc_mem_index_max(unit, MMU_INTFO_QCN_TOV_TBLm ), 18521 _soc_tr3_qcn_tov_tbl[unit])); 18522 SOC_IF_ERROR_RETURN(soc_mem_read_range(unit, MMU_REPL_GROUPm, MEM_BLOCK_ANY, 18523 soc_mem_index_min(unit, MMU_REPL_GROUPm), 18524 soc_mem_index_max(unit, MMU_REPL_GROUPm), 18525 _soc_tr3_repl_group[unit])); 18526 SOC_IF_ERROR_RETURN(soc_mem_read_range(unit, MMU_REPL_HEAD_TBLm, MEM_BLOCK_ANY, 18527 soc_mem_index_min(unit, MMU_REPL_HEAD_TBLm), 18528 soc_mem_index_max(unit, MMU_REPL_HEAD_TBLm), 18529 _soc_tr3_repl_head[unit])); 18530 SOC_IF_ERROR_RETURN(soc_mem_read_range(unit, MMU_INTFI_ST_TRANS_TBLm, MEM_BLOCK_ANY, 18531 soc_mem_index_min(unit, MMU_INTFI_ST_TRANS_TBLm), 18532 soc_mem_index_max(unit, MMU_INTFI_ST_TRANS_TBLm), 18533 _soc_tr3_st_trans_tbl[unit])); 18534 SOC_IF_ERROR_RETURN(soc_mem_read_range(unit, THDI_PORT_PG_CONFIGm, MEM_BLOCK_ANY, 18535 soc_mem_index_min(unit, THDI_PORT_PG_CONFIGm), 18536 soc_mem_index_max(unit, THDI_PORT_PG_CONFIGm), 18537 _soc_tr3_thdi_port_pg_config[unit])); 18538 SOC_IF_ERROR_RETURN(soc_mem_read_range(unit, THDI_PORT_SP_CONFIGm, MEM_BLOCK_ANY, 18539 soc_mem_index_min(unit, THDI_PORT_SP_CONFIGm), 18540 soc_mem_index_max(unit, THDI_PORT_SP_CONFIGm), 18541 _soc_tr3_thdi_port_sp_config[unit])); 18542 SOC_IF_ERROR_RETURN(soc_mem_read_range(unit, MMU_THDO_CONFIG_PORTm, MEM_BLOCK_ANY, 18543 soc_mem_index_min(unit, MMU_THDO_CONFIG_PORTm), 18544 soc_mem_index_max(unit, MMU_THDO_CONFIG_PORTm), 18545 _soc_tr3_thdo_port_sp_config[unit])); 18546 SOC_IF_ERROR_RETURN(soc_mem_read_range(unit, MMU_THDO_CONFIG_QGROUPm, MEM_BLOCK_ANY, 18547 soc_mem_index_min(unit, MMU_THDO_CONFIG_QGROUPm), 18548 soc_mem_index_max(unit, MMU_THDO_CONFIG_QGROUPm), 18549 _soc_tr3_thdo_uc_qgroup_config[unit])); 18550 SOC_IF_ERROR_RETURN(soc_mem_read_range(unit, MMU_THDO_CONFIG_QUEUEm, MEM_BLOCK_ANY, 18551 soc_mem_index_min(unit, MMU_THDO_CONFIG_QUEUEm), 18552 soc_mem_index_max(unit, MMU_THDO_CONFIG_QUEUEm), 18553 _soc_tr3_thdo_uc_queue_config[unit])); 18554 SOC_IF_ERROR_RETURN(soc_mem_read_range(unit, MMU_WRED_PORT_SP_DROP_THDm, MEM_BLOCK_ANY, 18555 soc_mem_index_min(unit, MMU_WRED_PORT_SP_DROP_THDm), 18556 soc_mem_index_max(unit, MMU_WRED_PORT_SP_DROP_THDm), 18557 _soc_tr3_wred_port_sp_drop_thd[unit])); 18558 SOC_IF_ERROR_RETURN(soc_mem_read_range(unit, MMU_WRED_QGROUP_DROP_THDm, MEM_BLOCK_ANY, 18559 soc_mem_index_min(unit, MMU_WRED_QGROUP_DROP_THDm), 18560 soc_mem_index_max(unit, MMU_WRED_QGROUP_DROP_THDm), 18561 _soc_tr3_wred_qgroup_drop_thd[unit])); 18562 SOC_IF_ERROR_RETURN(soc_mem_read_range(unit, MMU_WRED_UC_QUEUE_DROP_THD_DEQm, MEM_BLOCK_ANY, 18563 soc_mem_index_min(unit, MMU_WRED_UC_QUEUE_DROP_THD_DEQm), 18564 soc_mem_index_max(unit, MMU_WRED_UC_QUEUE_DROP_THD_DEQm), 18565 _soc_tr3_wred_uc_queue_drop_thd_deq[unit])); 18566 SOC_IF_ERROR_RETURN(soc_mem_read_range(unit, MMU_WRED_UC_QUEUE_DROP_THD_ENQm, MEM_BLOCK_ANY, 18567 soc_mem_index_min(unit, MMU_WRED_UC_QUEUE_DROP_THD_ENQm), 18568 soc_mem_index_max(unit, MMU_WRED_UC_QUEUE_DROP_THD_ENQm), 18569 _soc_tr3_wred_uc_queue_drop_thd_enq[unit])); 18570 return SOC_E_NONE; 18571 } 18572 18573 int 18574 soc_tr3_mmu_memory_restore(int unit) 18575 { 18576 SOC_IF_ERROR_RETURN(soc_mem_write_range(unit, MMU_INTFI_BASE_INDEX_TBLm, MEM_BLOCK_ANY, 18577 soc_mem_index_min(unit, MMU_INTFI_BASE_INDEX_TBLm), 18578 soc_mem_index_max(unit, MMU_INTFI_BASE_INDEX_TBLm), 18579 _soc_tr3_base_index_tbl[unit])); 18580 SOC_IF_ERROR_RETURN(soc_mem_write_range(unit, MMU_CHFC_SYSPORT_MAPPINGm, MEM_BLOCK_ANY, 18581 soc_mem_index_min(unit, MMU_CHFC_SYSPORT_MAPPINGm), 18582 soc_mem_index_max(unit, MMU_CHFC_SYSPORT_MAPPINGm), 18583 _soc_tr3_chfc_sysport_mapping[unit])); 18584 SOC_IF_ERROR_RETURN(soc_mem_write_range(unit, MMU_CTR_COLOR_DROP_MEMm, MEM_BLOCK_ANY, 18585 soc_mem_index_min(unit, MMU_CTR_COLOR_DROP_MEMm), 18586 soc_mem_index_max(unit, MMU_CTR_COLOR_DROP_MEMm), 18587 _soc_tr3_ctr_color_drop[unit])); 18588 SOC_IF_ERROR_RETURN(soc_mem_write_range(unit, MMU_CTR_MC_DROP_MEMm, MEM_BLOCK_ANY, 18589 soc_mem_index_min(unit, MMU_CTR_MC_DROP_MEMm), 18590 soc_mem_index_max(unit, MMU_CTR_MC_DROP_MEMm), 18591 _soc_tr3_ctr_mc_drop[unit])); 18592 SOC_IF_ERROR_RETURN(soc_mem_write_range(unit, MMU_CTR_UC_DROP_MEMm, MEM_BLOCK_ANY, 18593 soc_mem_index_min(unit, MMU_CTR_UC_DROP_MEMm), 18594 soc_mem_index_max(unit, MMU_CTR_UC_DROP_MEMm), 18595 _soc_tr3_ctr_uc_drop[unit])); 18596 SOC_IF_ERROR_RETURN(soc_mem_write_range(unit, MMU_INTFI_FC_MAP_TBL0m, MEM_BLOCK_ANY, 18597 soc_mem_index_min(unit, MMU_INTFI_FC_MAP_TBL0m), 18598 soc_mem_index_max(unit, MMU_INTFI_FC_MAP_TBL0m), 18599 _soc_tr3_fc_map_tbl0[unit])); 18600 SOC_IF_ERROR_RETURN(soc_mem_write_range(unit, MMU_INTFI_FC_MAP_TBL1m, MEM_BLOCK_ANY, 18601 soc_mem_index_min(unit, MMU_INTFI_FC_MAP_TBL1m), 18602 soc_mem_index_max(unit, MMU_INTFI_FC_MAP_TBL1m), 18603 _soc_tr3_fc_map_tbl1[unit])); 18604 SOC_IF_ERROR_RETURN(soc_mem_write_range(unit, MMU_INTFI_FC_MAP_TBL2m, MEM_BLOCK_ANY, 18605 soc_mem_index_min(unit, MMU_INTFI_FC_MAP_TBL2m), 18606 soc_mem_index_max(unit, MMU_INTFI_FC_MAP_TBL2m), 18607 _soc_tr3_fc_map_tbl2[unit])); 18608 SOC_IF_ERROR_RETURN(soc_mem_write_range(unit, MMU_INTFI_FC_ST_TBL0m, MEM_BLOCK_ANY, 18609 soc_mem_index_min(unit, MMU_INTFI_FC_ST_TBL0m), 18610 soc_mem_index_max(unit, MMU_INTFI_FC_ST_TBL0m), 18611 _soc_tr3_fc_st_tbl0[unit])); 18612 SOC_IF_ERROR_RETURN(soc_mem_write_range(unit, MMU_INTFI_FC_ST_TBL1m, MEM_BLOCK_ANY, 18613 soc_mem_index_min(unit, MMU_INTFI_FC_ST_TBL1m), 18614 soc_mem_index_max(unit, MMU_INTFI_FC_ST_TBL1m), 18615 _soc_tr3_fc_st_tbl1[unit])); 18616 SOC_IF_ERROR_RETURN(soc_mem_write_range(unit, MMU_INTFI_FC_ST_TBL2m, MEM_BLOCK_ANY, 18617 soc_mem_index_min(unit, MMU_INTFI_FC_ST_TBL2m), 18618 soc_mem_index_max(unit, MMU_INTFI_FC_ST_TBL2m), 18619 _soc_tr3_fc_st_tbl2[unit])); 18620 SOC_IF_ERROR_RETURN(soc_mem_write_range(unit, MMU_INTFO_TC2PRI_MAPPINGm, MEM_BLOCK_ANY, 18621 soc_mem_index_min(unit, MMU_INTFO_TC2PRI_MAPPINGm), 18622 soc_mem_index_max(unit, MMU_INTFO_TC2PRI_MAPPINGm), 18623 _soc_tr3_intfo_tc2pri_mapping[unit])); 18624 SOC_IF_ERROR_RETURN(soc_mem_write_range(unit, MMU_REPL_LIST_TBLm, MEM_BLOCK_ANY, 18625 soc_mem_index_min(unit, MMU_REPL_LIST_TBLm), 18626 soc_mem_index_max(unit, MMU_REPL_LIST_TBLm), 18627 _soc_tr3_ipmc_vlan[unit])); 18628 SOC_IF_ERROR_RETURN(soc_mem_write_range(unit, LLS_PORT_CONFIGm, MEM_BLOCK_ANY, 18629 soc_mem_index_min(unit, LLS_PORT_CONFIGm), 18630 soc_mem_index_max(unit, LLS_PORT_CONFIGm), 18631 _soc_tr3_lls_port_config[unit])); 18632 SOC_IF_ERROR_RETURN(soc_mem_write_range(unit, MMU_MTRO_L0_MEMm, MEM_BLOCK_ANY, 18633 soc_mem_index_min(unit, MMU_MTRO_L0_MEMm), 18634 soc_mem_index_max(unit, MMU_MTRO_L0_MEMm), 18635 _soc_tr3_mmu_mtro_config_l0_mem[unit])); 18636 SOC_IF_ERROR_RETURN(soc_mem_write_range(unit, MMU_MTRO_L1_MEMm, MEM_BLOCK_ANY, 18637 soc_mem_index_min(unit, MMU_MTRO_L1_MEMm), 18638 soc_mem_index_max(unit, MMU_MTRO_L1_MEMm), 18639 _soc_tr3_mmu_mtro_config_l1_mem[unit])); 18640 SOC_IF_ERROR_RETURN(soc_mem_write_range(unit, MMU_MTRO_L2_MEMm, MEM_BLOCK_ANY, 18641 soc_mem_index_min(unit, MMU_MTRO_L2_MEMm), 18642 soc_mem_index_max(unit, MMU_MTRO_L2_MEMm), 18643 _soc_tr3_mmu_mtro_config_l2_mem[unit])); 18644 SOC_IF_ERROR_RETURN(soc_mem_write_range(unit, MMU_QCN_CNM_COUNTERm, MEM_BLOCK_ANY, 18645 soc_mem_index_min(unit, MMU_QCN_CNM_COUNTERm), 18646 soc_mem_index_max(unit, MMU_QCN_CNM_COUNTERm), 18647 _soc_tr3_mmu_qcn_cnm_counter[unit])); 18648 SOC_IF_ERROR_RETURN(soc_mem_write_range(unit, MMU_THDO_OFFSET_QGROUPm, MEM_BLOCK_ANY, 18649 soc_mem_index_min(unit, MMU_THDO_OFFSET_QGROUPm), 18650 soc_mem_index_max(unit, MMU_THDO_OFFSET_QGROUPm), 18651 _soc_tr3_mmu_thdo_offset_qgroup[unit])); 18652 SOC_IF_ERROR_RETURN(soc_mem_write_range(unit, MMU_THDO_OFFSET_QUEUEm, MEM_BLOCK_ANY, 18653 soc_mem_index_min(unit, MMU_THDO_OFFSET_QUEUEm), 18654 soc_mem_index_max(unit, MMU_THDO_OFFSET_QUEUEm), 18655 _soc_tr3_mmu_thdo_offset_queue[unit])); 18656 SOC_IF_ERROR_RETURN(soc_mem_write_range(unit, MMU_THDO_Q_TO_QGRP_MAPm, MEM_BLOCK_ANY, 18657 soc_mem_index_min(unit, MMU_THDO_Q_TO_QGRP_MAPm), 18658 soc_mem_index_max(unit, MMU_THDO_Q_TO_QGRP_MAPm), 18659 _soc_tr3_mmu_thdo_q_to_qgrp_map[unit])); 18660 SOC_IF_ERROR_RETURN(soc_mem_write_range(unit, MMU_WRED_DROP_CURVE_PROFILE_0m, MEM_BLOCK_ANY, 18661 soc_mem_index_min(unit, MMU_WRED_DROP_CURVE_PROFILE_0m), 18662 soc_mem_index_max(unit, MMU_WRED_DROP_CURVE_PROFILE_0m), 18663 _soc_tr3_mmu_wred_drop_curve_profile_0[unit])); 18664 SOC_IF_ERROR_RETURN(soc_mem_write_range(unit, MMU_WRED_DROP_CURVE_PROFILE_1m, MEM_BLOCK_ANY, 18665 soc_mem_index_min(unit, MMU_WRED_DROP_CURVE_PROFILE_1m), 18666 soc_mem_index_max(unit, MMU_WRED_DROP_CURVE_PROFILE_1m), 18667 _soc_tr3_mmu_wred_drop_curve_profile_1[unit])); 18668 SOC_IF_ERROR_RETURN(soc_mem_write_range(unit, MMU_WRED_DROP_CURVE_PROFILE_2m, MEM_BLOCK_ANY, 18669 soc_mem_index_min(unit, MMU_WRED_DROP_CURVE_PROFILE_2m), 18670 soc_mem_index_max(unit, MMU_WRED_DROP_CURVE_PROFILE_2m), 18671 _soc_tr3_mmu_wred_drop_curve_profile_2[unit])); 18672 SOC_IF_ERROR_RETURN(soc_mem_write_range(unit, MMU_WRED_DROP_CURVE_PROFILE_3m, MEM_BLOCK_ANY, 18673 soc_mem_index_min(unit, MMU_WRED_DROP_CURVE_PROFILE_3m), 18674 soc_mem_index_max(unit, MMU_WRED_DROP_CURVE_PROFILE_3m), 18675 _soc_tr3_mmu_wred_drop_curve_profile_3[unit])); 18676 SOC_IF_ERROR_RETURN(soc_mem_write_range(unit, MMU_WRED_DROP_CURVE_PROFILE_4m, MEM_BLOCK_ANY, 18677 soc_mem_index_min(unit, MMU_WRED_DROP_CURVE_PROFILE_4m), 18678 soc_mem_index_max(unit, MMU_WRED_DROP_CURVE_PROFILE_4m), 18679 _soc_tr3_mmu_wred_drop_curve_profile_4[unit])); 18680 SOC_IF_ERROR_RETURN(soc_mem_write_range(unit, MMU_WRED_DROP_CURVE_PROFILE_5m, MEM_BLOCK_ANY, 18681 soc_mem_index_min(unit, MMU_WRED_DROP_CURVE_PROFILE_5m), 18682 soc_mem_index_max(unit, MMU_WRED_DROP_CURVE_PROFILE_5m), 18683 _soc_tr3_mmu_wred_drop_curve_profile_5[unit])); 18684 SOC_IF_ERROR_RETURN(soc_mem_write_range(unit, MMU_WRED_CONFIGm, MEM_BLOCK_ANY, 18685 soc_mem_index_min(unit, MMU_WRED_CONFIGm), 18686 soc_mem_index_max(unit, MMU_WRED_CONFIGm), 18687 _soc_tr3_mmu_wred_uc_queue_config[unit])); 18688 SOC_IF_ERROR_RETURN(soc_mem_write_range(unit, MMU_INTFI_OFFSET_MAP_TBLm, MEM_BLOCK_ANY, 18689 soc_mem_index_min(unit, MMU_INTFI_OFFSET_MAP_TBLm), 18690 soc_mem_index_max(unit, MMU_INTFI_OFFSET_MAP_TBLm), 18691 _soc_tr3_offset_map_tbl[unit])); 18692 SOC_IF_ERROR_RETURN(soc_mem_write_range(unit, MMU_INTFI_PFC_ST_TBLm, MEM_BLOCK_ANY, 18693 soc_mem_index_min(unit, MMU_INTFI_PFC_ST_TBLm), 18694 soc_mem_index_max(unit, MMU_INTFI_PFC_ST_TBLm), 18695 _soc_tr3_pfc_st_tbl[unit])); 18696 SOC_IF_ERROR_RETURN(soc_mem_write_range(unit, MMU_QCN_ENABLEm , MEM_BLOCK_ANY, 18697 soc_mem_index_min(unit, MMU_QCN_ENABLEm ), 18698 soc_mem_index_max(unit, MMU_QCN_ENABLEm ), 18699 _soc_tr3_qcn_enable[unit])); 18700 SOC_IF_ERROR_RETURN(soc_mem_write_range(unit, MMU_QCN_QFBTBm , MEM_BLOCK_ANY, 18701 soc_mem_index_min(unit, MMU_QCN_QFBTBm ), 18702 soc_mem_index_max(unit, MMU_QCN_QFBTBm ), 18703 _soc_tr3_qcn_qfbtb[unit])); 18704 SOC_IF_ERROR_RETURN(soc_mem_write_range(unit, MMU_QCN_SITBm , MEM_BLOCK_ANY, 18705 soc_mem_index_min(unit, MMU_QCN_SITBm ), 18706 soc_mem_index_max(unit, MMU_QCN_SITBm ), 18707 _soc_tr3_qcn_sitb[unit])); 18708 SOC_IF_ERROR_RETURN(soc_mem_write_range(unit, MMU_INTFO_QCN_TBID_TBLm , MEM_BLOCK_ANY, 18709 soc_mem_index_min(unit, MMU_INTFO_QCN_TBID_TBLm ), 18710 soc_mem_index_max(unit, MMU_INTFO_QCN_TBID_TBLm ), 18711 _soc_tr3_qcn_tbid_tbl[unit])); 18712 SOC_IF_ERROR_RETURN(soc_mem_write_range(unit, MMU_INTFO_QCN_TOV_TBLm , MEM_BLOCK_ANY, 18713 soc_mem_index_min(unit, MMU_INTFO_QCN_TOV_TBLm ), 18714 soc_mem_index_max(unit, MMU_INTFO_QCN_TOV_TBLm ), 18715 _soc_tr3_qcn_tov_tbl[unit])); 18716 SOC_IF_ERROR_RETURN(soc_mem_write_range(unit, MMU_REPL_GROUPm, MEM_BLOCK_ANY, 18717 soc_mem_index_min(unit, MMU_REPL_GROUPm), 18718 soc_mem_index_max(unit, MMU_REPL_GROUPm), 18719 _soc_tr3_repl_group[unit])); 18720 SOC_IF_ERROR_RETURN(soc_mem_write_range(unit, MMU_REPL_HEAD_TBLm, MEM_BLOCK_ANY, 18721 soc_mem_index_min(unit, MMU_REPL_HEAD_TBLm), 18722 soc_mem_index_max(unit, MMU_REPL_HEAD_TBLm), 18723 _soc_tr3_repl_head[unit])); 18724 SOC_IF_ERROR_RETURN(soc_mem_write_range(unit, MMU_INTFI_ST_TRANS_TBLm, MEM_BLOCK_ANY, 18725 soc_mem_index_min(unit, MMU_INTFI_ST_TRANS_TBLm), 18726 soc_mem_index_max(unit, MMU_INTFI_ST_TRANS_TBLm), 18727 _soc_tr3_st_trans_tbl[unit])); 18728 SOC_IF_ERROR_RETURN(soc_mem_write_range(unit, MMU_WRED_PORT_SP_DROP_THDm, MEM_BLOCK_ANY, 18729 soc_mem_index_min(unit, MMU_WRED_PORT_SP_DROP_THDm), 18730 soc_mem_index_max(unit, MMU_WRED_PORT_SP_DROP_THDm), 18731 _soc_tr3_wred_port_sp_drop_thd[unit])); 18732 SOC_IF_ERROR_RETURN(soc_mem_write_range(unit, MMU_WRED_QGROUP_DROP_THDm, MEM_BLOCK_ANY, 18733 soc_mem_index_min(unit, MMU_WRED_QGROUP_DROP_THDm), 18734 soc_mem_index_max(unit, MMU_WRED_QGROUP_DROP_THDm), 18735 _soc_tr3_wred_qgroup_drop_thd[unit])); 18736 SOC_IF_ERROR_RETURN(soc_mem_write_range(unit, MMU_WRED_UC_QUEUE_DROP_THD_DEQm, MEM_BLOCK_ANY, 18737 soc_mem_index_min(unit, MMU_WRED_UC_QUEUE_DROP_THD_DEQm), 18738 soc_mem_index_max(unit, MMU_WRED_UC_QUEUE_DROP_THD_DEQm), 18739 _soc_tr3_wred_uc_queue_drop_thd_deq[unit])); 18740 SOC_IF_ERROR_RETURN(soc_mem_write_range(unit, MMU_WRED_UC_QUEUE_DROP_THD_ENQm, MEM_BLOCK_ANY, 18741 soc_mem_index_min(unit, MMU_WRED_UC_QUEUE_DROP_THD_ENQm), 18742 soc_mem_index_max(unit, MMU_WRED_UC_QUEUE_DROP_THD_ENQm), 18743 _soc_tr3_wred_uc_queue_drop_thd_enq[unit])); 18744 return SOC_E_NONE; 18745 } 18746 18747 int 18748 soc_tr3_mmu_init_restore(int unit) 18749 { 18750 int idx, port; 18751 _soc_tr3_mmu_data_t *mmu_data; 18752 18753 mmu_data = (_soc_tr3_mmu_data_t *) _soc_tr3_mmu_data[unit]; 18754 if(mmu_data == NULL) { 18755 LOG_ERROR(BSL_LS_SOC_COMMON, 18756 (BSL_META_U(unit, 18757 "NULL pointer for MMU data\n"))); 18758 return SOC_E_INTERNAL; 18759 } 18760 18761 SOC_IF_ERROR_RETURN(_soc_tr3_tdm_restore(unit)); 18762 18763 SOC_IF_ERROR_RETURN(WRITE_CFAPFULLTHRESHOLDr(unit, 18764 mmu_data->_soc_tr3_cfapfullthreshold)); 18765 18766 PBMP_ALL_ITER(unit, port) { 18767 SOC_IF_ERROR_RETURN(WRITE_PORT_PRI_GRP0r(unit, port, 18768 mmu_data->_soc_tr3_port_pri_grp0[port])); 18769 SOC_IF_ERROR_RETURN(WRITE_PORT_PRI_GRP1r(unit, port, 18770 mmu_data->_soc_tr3_port_pri_grp1[port])); 18771 } 18772 SOC_IF_ERROR_RETURN(WRITE_GLOBAL_HDRM_LIMITr(unit, 18773 mmu_data->_soc_tr3_global_hdrm_limit)); 18774 SOC_IF_ERROR_RETURN(WRITE_USE_SP_SHAREDr(unit, 18775 mmu_data->_soc_tr3_use_sp_shared)); 18776 SOC_IF_ERROR_RETURN(WRITE_COLOR_AWAREr(unit, 18777 mmu_data->_soc_tr3_color_aware)); 18778 18779 SOC_IF_ERROR_RETURN(soc_mem_write_range(unit, MMU_THDO_CONFIG_QGROUPm, 18780 MEM_BLOCK_ANY, 18781 soc_mem_index_min(unit, MMU_THDO_CONFIG_QGROUPm), 18782 soc_mem_index_max(unit, MMU_THDO_CONFIG_QGROUPm), 18783 _soc_tr3_thdo_uc_qgroup_config[unit])); 18784 18785 for (idx = 0; idx < 4; idx++) { 18786 SOC_IF_ERROR_RETURN (WRITE_BUFFER_CELL_LIMIT_SPr( 18787 unit, idx, 18788 mmu_data->_soc_tr3_buffer_cell_limit_sp[idx])); 18789 SOC_IF_ERROR_RETURN (WRITE_CELL_RESET_LIMIT_OFFSET_SPr( 18790 unit, idx, 18791 mmu_data->_soc_tr3_cell_reset_limit_offset_sp[idx])); 18792 } 18793 18794 PBMP_ALL_ITER(unit, port) { 18795 SOC_IF_ERROR_RETURN(WRITE_PORT_PG_SPIDr(unit, port, 18796 mmu_data->_soc_tr3_port_pg_spid[port])); 18797 } 18798 18799 SOC_IF_ERROR_RETURN(soc_mem_write_range(unit, THDI_PORT_SP_CONFIGm, MEM_BLOCK_ANY, 18800 soc_mem_index_min(unit, THDI_PORT_SP_CONFIGm), 18801 soc_mem_index_max(unit, THDI_PORT_SP_CONFIGm), 18802 _soc_tr3_thdi_port_sp_config[unit])); 18803 18804 PBMP_ALL_ITER(unit, port) { 18805 SOC_IF_ERROR_RETURN(WRITE_PORT_PRI_XON_ENABLEr(unit, port, 18806 mmu_data->_soc_tr3_port_pri_xon_enable[port])); 18807 SOC_IF_ERROR_RETURN(WRITE_PORT_MAX_PKT_SIZEr(unit, port, 18808 mmu_data->_soc_tr3_port_max_pkt_size[port])); 18809 } 18810 18811 SOC_IF_ERROR_RETURN(soc_mem_write_range(unit, THDI_PORT_PG_CONFIGm, MEM_BLOCK_ANY, 18812 soc_mem_index_min(unit, THDI_PORT_PG_CONFIGm), 18813 soc_mem_index_max(unit, THDI_PORT_PG_CONFIGm), 18814 _soc_tr3_thdi_port_pg_config[unit])); 18815 18816 PBMP_ALL_ITER(unit, port) { 18817 for (idx = 0; idx < 48; idx++) { 18818 SOC_IF_ERROR_RETURN (WRITE_OP_QUEUE_CONFIG_CELLr( 18819 unit, port, idx, 18820 mmu_data->_soc_tr3_op_queue_config_cell[port][idx])); 18821 SOC_IF_ERROR_RETURN (WRITE_OP_QUEUE_CONFIG1_CELLr( 18822 unit, port, idx, 18823 mmu_data->_soc_tr3_op_queue_config1_cell[port][idx])); 18824 SOC_IF_ERROR_RETURN (WRITE_OP_QUEUE_LIMIT_COLOR_CELLr( 18825 unit, port, idx, 18826 mmu_data->_soc_tr3_op_queue_limit_color_cell[port][idx])); 18827 SOC_IF_ERROR_RETURN (WRITE_OP_QUEUE_RESET_OFFSET_CELLr( 18828 unit, port, idx, 18829 mmu_data->_soc_tr3_op_queue_reset_offset_cell[port][idx])); 18830 } 18831 } 18832 SOC_IF_ERROR_RETURN(soc_mem_write_range(unit, MMU_THDO_CONFIG_QUEUEm, MEM_BLOCK_ANY, 18833 soc_mem_index_min(unit, MMU_THDO_CONFIG_QUEUEm), 18834 soc_mem_index_max(unit, MMU_THDO_CONFIG_QUEUEm), 18835 _soc_tr3_thdo_uc_queue_config[unit])); 18836 18837 for (idx = 0; idx < 4; idx++) { 18838 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, 18839 OP_BUFFER_SHARED_LIMIT_CELLr, REG_PORT_ANY, idx, 18840 mmu_data->_soc_tr3_op_buffer_shared_limit_cell[idx])); 18841 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, 18842 OP_BUFFER_LIMIT_YELLOW_CELLr, REG_PORT_ANY, idx, 18843 mmu_data->_soc_tr3_op_buffer_limit_yellow_cell[idx])); 18844 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, 18845 OP_BUFFER_LIMIT_RED_CELLr, REG_PORT_ANY, idx, 18846 mmu_data->_soc_tr3_op_buffer_limit_red_cell[idx])); 18847 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, 18848 OP_BUFFER_LIMIT_RESUME_RED_CELLr, REG_PORT_ANY, idx, 18849 mmu_data->_soc_tr3_op_buffer_limit_resume_red_cell[idx])); 18850 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, 18851 OP_BUFFER_LIMIT_RESUME_YELLOW_CELLr, REG_PORT_ANY, idx, 18852 mmu_data->_soc_tr3_op_buffer_limit_resume_yellow_cell[idx])); 18853 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, 18854 OP_BUFFER_SHARED_LIMIT_RESUME_CELLr, REG_PORT_ANY, idx, 18855 mmu_data->_soc_tr3_op_buffer_shared_limit_resume_cell[idx])); 18856 } 18857 18858 SOC_IF_ERROR_RETURN(soc_mem_write_range(unit, MMU_THDO_CONFIG_PORTm, MEM_BLOCK_ANY, 18859 soc_mem_index_min(unit, MMU_THDO_CONFIG_PORTm), 18860 soc_mem_index_max(unit, MMU_THDO_CONFIG_PORTm), 18861 _soc_tr3_thdo_port_sp_config[unit])); 18862 18863 PBMP_ALL_ITER(unit, port) { 18864 for (idx = 0; idx < 4; idx++) { 18865 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, OP_PORT_CONFIG_CELLr, 18866 port, idx, 18867 mmu_data->_soc_tr3_op_port_config_cell[port][idx])); 18868 SOC_IF_ERROR_RETURN (WRITE_OP_PORT_LIMIT_COLOR_CELLr( 18869 unit, port, idx, 18870 mmu_data->_soc_tr3_op_port_limit_color_cell[port][idx])); 18871 SOC_IF_ERROR_RETURN (WRITE_OP_PORT_LIMIT_RESUME_COLOR_CELLr( 18872 unit, port, idx, 18873 mmu_data->_soc_tr3_op_port_limit_resume_color_cell[port][idx])); 18874 } 18875 } 18876 18877 SOC_IF_ERROR_RETURN(WRITE_WAMUTOTALSHRLMTINGr(unit, 18878 mmu_data->_soc_tr3_wamutotalshrlmting)); 18879 SOC_IF_ERROR_RETURN(WRITE_WAMUTOTALSHRLMTPKTEGRr(unit, 18880 mmu_data->_soc_tr3_wamutotalshrlmtpktegr)); 18881 SOC_IF_ERROR_RETURN(WRITE_CNTX_AGING_LIMITr(unit, 18882 mmu_data->_soc_tr3_cntx_aging_limit)); 18883 SOC_IF_ERROR_RETURN(WRITE_WAMUTHDBYPASSr(unit, 18884 mmu_data->_soc_tr3_wamuthdbypass)); 18885 18886 for (idx = 0; idx < 2; idx++) { 18887 SOC_IF_ERROR_RETURN(WRITE_WAMU_PG_MIN_CELLr(unit, idx, 18888 mmu_data->_soc_tr3_wamu_pg_min_cell[idx])); 18889 SOC_IF_ERROR_RETURN(WRITE_WAMU_PG_SHARED_LIMIT_CELLr(unit, idx, 18890 mmu_data->_soc_tr3_wamu_pg_shared_limit_cell[idx])); 18891 SOC_IF_ERROR_RETURN(WRITE_WAMU_PG_RESET_OFFSET_CELLr(unit, idx, 18892 mmu_data->_soc_tr3_wamu_pg_reset_offset_cell[idx])); 18893 SOC_IF_ERROR_RETURN(WRITE_WAMUMINLMTPGr(unit, idx, 18894 mmu_data->_soc_tr3_wamuminlmtpg[idx])); 18895 SOC_IF_ERROR_RETURN(WRITE_WAMUSHRLMTCELLPGr(unit, idx, 18896 mmu_data->_soc_tr3_wamushrlmtcellpg[idx])); 18897 } 18898 18899 for (idx = 0; idx < 8; idx++) { 18900 SOC_IF_ERROR_RETURN(WRITE_WAMUSHRLMTPKTQr(unit, idx, 18901 mmu_data->_soc_tr3_wamushrlmtpktq[idx])); 18902 SOC_IF_ERROR_RETURN(WRITE_WAMUMINLMTPKTQr(unit, idx, 18903 mmu_data->_soc_tr3_wamuminlmtpktq[idx])); 18904 SOC_IF_ERROR_RETURN(WRITE_WAMURSTOFFSETPKTQr(unit, idx, 18905 mmu_data->_soc_tr3_wamurstoffsetpktq[idx])); 18906 } 18907 SOC_IF_ERROR_RETURN(WRITE_LLS_CONFIG0r(unit, 18908 mmu_data->_soc_tr3_lls_config0)); 18909 18910 SOC_IF_ERROR_RETURN(soc_mem_write_range(unit, LLS_L2_PARENTm, MEM_BLOCK_ANY, 18911 soc_mem_index_min(unit, LLS_L2_PARENTm), 18912 soc_mem_index_max(unit, LLS_L2_PARENTm), 18913 _soc_tr3_lls_l2_parent[unit])); 18914 SOC_IF_ERROR_RETURN(soc_mem_write_range(unit, LLS_L1_PARENTm, MEM_BLOCK_ANY, 18915 soc_mem_index_min(unit, LLS_L1_PARENTm), 18916 soc_mem_index_max(unit, LLS_L1_PARENTm), 18917 _soc_tr3_lls_l1_parent[unit])); 18918 SOC_IF_ERROR_RETURN(soc_mem_write_range(unit, LLS_L0_PARENTm, MEM_BLOCK_ANY, 18919 soc_mem_index_min(unit, LLS_L0_PARENTm), 18920 soc_mem_index_max(unit, LLS_L0_PARENTm), 18921 _soc_tr3_lls_l0_parent[unit])); 18922 SOC_IF_ERROR_RETURN(soc_mem_write_range(unit, LLS_L0_CHILD_WEIGHT_CFGm, 18923 MEM_BLOCK_ANY, 18924 soc_mem_index_min(unit, LLS_L0_CHILD_WEIGHT_CFGm), 18925 soc_mem_index_max(unit, LLS_L0_CHILD_WEIGHT_CFGm), 18926 _soc_tr3_lls_l0_child_weight_cfg[unit])); 18927 SOC_IF_ERROR_RETURN(soc_mem_write_range(unit, LLS_L1_CHILD_WEIGHT_CFGm, 18928 MEM_BLOCK_ANY, 18929 soc_mem_index_min(unit, LLS_L1_CHILD_WEIGHT_CFGm), 18930 soc_mem_index_max(unit, LLS_L1_CHILD_WEIGHT_CFGm), 18931 _soc_tr3_lls_l1_child_weight_cfg[unit])); 18932 SOC_IF_ERROR_RETURN(soc_mem_write_range(unit, LLS_L2_CHILD_WEIGHT_CFGm, 18933 MEM_BLOCK_ANY, 18934 soc_mem_index_min(unit, LLS_L2_CHILD_WEIGHT_CFGm), 18935 soc_mem_index_max(unit, LLS_L2_CHILD_WEIGHT_CFGm), 18936 _soc_tr3_lls_l2_child_weight_cfg[unit])); 18937 SOC_IF_ERROR_RETURN(soc_mem_write_range(unit, LLS_L0_CONFIGm, MEM_BLOCK_ANY, 18938 soc_mem_index_min(unit, LLS_L0_CONFIGm), 18939 soc_mem_index_max(unit, LLS_L0_CONFIGm), 18940 _soc_tr3_lls_l0_config[unit])); 18941 SOC_IF_ERROR_RETURN(soc_mem_write_range(unit, LLS_L1_CONFIGm, MEM_BLOCK_ANY, 18942 soc_mem_index_min(unit, LLS_L1_CONFIGm), 18943 soc_mem_index_max(unit, LLS_L1_CONFIGm), 18944 _soc_tr3_lls_l1_config[unit])); 18945 18946 SOC_IF_ERROR_RETURN(_soc_tr3_update_mcq_fifo(unit, _soc_prev_port_speeds)); 18947 SOC_IF_ERROR_RETURN(WRITE_OVQ_DROP_THRESHOLD0r(unit, 18948 mmu_data->_soc_tr3_ovq_drop_threshold0)); 18949 SOC_IF_ERROR_RETURN(WRITE_OVQ_DROP_THRESHOLD_RESET_LIMITr(unit, 18950 mmu_data->_soc_tr3_ovq_drop_threshold_reset_limit)); 18951 SOC_IF_ERROR_RETURN(WRITE_OP_THR_CONFIGr(unit, 18952 mmu_data->_soc_tr3_op_thr_config)); 18953 SOC_IF_ERROR_RETURN(WRITE_INPUT_PORT_RX_ENABLE_64r(unit, 18954 mmu_data->_soc_tr3_input_port_rx_enable_64)); 18955 SOC_IF_ERROR_RETURN(WRITE_OUTPUT_PORT_RX_ENABLE0_64r(unit, 18956 mmu_data->_soc_tr3_output_port_rx_enable0_64)); 18957 SOC_IF_ERROR_RETURN(WRITE_PORT_PAUSE_ENABLE_64r(unit, 18958 mmu_data->_soc_tr3_port_pause_enable_64)); 18959 SOC_IF_ERROR_RETURN(WRITE_THDI_BYPASSr(unit, 18960 mmu_data->_soc_tr3_thdi_bypass)); 18961 SOC_IF_ERROR_RETURN(WRITE_THDO_BYPASSr(unit, 18962 mmu_data->_soc_tr3_thdo_bypass)); 18963 18964 return SOC_E_NONE; 18965 } 18966 /* 18967 * Tr3 chip driver functions. 18968 */ 18969 soc_functions_t soc_triumph3_drv_funs = { 18970 _soc_tr3_misc_init, 18971 _soc_tr3_mmu_init, 18972 _soc_tr3_age_timer_get, 18973 _soc_tr3_age_timer_max_get, 18974 _soc_tr3_age_timer_set, 18975 }; 18976 18977 #endif /* BCM_TRIUMPH3_SUPPORT */