triumph2.c (238635B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: triumph2.c 8 * Purpose: 9 * Requires: 10 */ 11 12 #include <sal/core/boot.h> 13 #include <shared/bsl.h> 14 #include <soc/firebolt.h> 15 #include <soc/bradley.h> 16 #include <soc/triumph.h> 17 #include <soc/triumph2.h> 18 #include <soc/drv.h> 19 #include <soc/mem.h> 20 #include <soc/hash.h> 21 #include <soc/lpm.h> 22 #include <soc/error.h> 23 #include <soc/debug.h> 24 #include <soc/devids.h> 25 #include <soc/register.h> 26 #include <soc/cmic.h> 27 #include <soc/mem.h> 28 #include <soc/soc_ser_log.h> 29 #ifdef BCM_TRIUMPH2_SUPPORT 30 31 /* 32 * Triumph2 chip driver functions. 33 */ 34 soc_functions_t soc_triumph2_drv_funs = { 35 soc_triumph2_misc_init, 36 soc_triumph2_mmu_init, 37 soc_triumph2_age_timer_get, 38 soc_triumph2_age_timer_max_get, 39 soc_triumph2_age_timer_set, 40 }; 41 42 typedef enum { 43 _SOC_PARITY_INFO_TYPE_GENERIC, 44 _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 45 _SOC_PARITY_INFO_TYPE_SINGLE_ECC, 46 _SOC_PARITY_INFO_TYPE_SINGLE_COUNTER, 47 _SOC_PARITY_INFO_TYPE_DUAL_PARITY, 48 _SOC_PARITY_INFO_TYPE_MMU_PARITY, 49 _SOC_PARITY_INFO_TYPE_MMUIPMC, 50 _SOC_PARITY_INFO_TYPE_MMUWRED, 51 _SOC_PARITY_INFO_TYPE_MMUMTRO, 52 _SOC_PARITY_INFO_TYPE_OAM, /* Not parity, but same interrupt */ 53 _SOC_PARITY_INFO_TYPE_SER, /* Parity error from CMIC SER module */ 54 _SOC_PARITY_INFO_TYPE_NUM 55 }_soc_parity_info_type_t; 56 57 typedef struct _soc_parity_info_s { 58 soc_field_t enable_field; 59 soc_field_t error_field; 60 char *msg; 61 soc_mem_t mem; 62 _soc_parity_info_type_t type; 63 soc_reg_t control_reg; 64 soc_reg_t intr_status0_reg; 65 soc_reg_t intr_status1_reg; /* Also SBE force for ECC */ 66 soc_reg_t nack_status0_reg; 67 soc_reg_t nack_status1_reg; /* Also DBE force for ECC */ 68 }_soc_parity_info_t; 69 70 /* 71 * _SOC_PARITY_INFO_TYPE_SINGLE_PARITY 72 * PARITY_EN 73 * ENTRY_IDX, MULTIPLE_ERR, PARITY_ERR 74 * 75 * _SOC_PARITY_INFO_TYPE_SINGLE_ECC 76 * ECC_EN 77 * ENTRY_IDX, DOUBLE_BIT_ERR, MULTIPLE_ERR, ECC_ERR 78 * 79 * _SOC_PARITY_INFO_TYPE_SINGLE_COUNTER 80 * PARITY_EN 81 * PORT_IDX, COUNTER_IDX, MULTIPLE_ERR, PARITY_ERR 82 * 83 * _SOC_PARITY_INFO_TYPE_DUAL_PARITY 84 * PARITY_EN 85 * BUCKET_IDX, MULTIPLE_ERR, PARITY_ERR_BM 86 */ 87 88 STATIC _soc_parity_info_t _soc_tr2_ip0_parity_info[] = { 89 { PARITY_ENf, VXLT_PAR_ERRf, NULL, 90 VLAN_XLATEm, _SOC_PARITY_INFO_TYPE_DUAL_PARITY, 91 VLAN_XLATE_PARITY_CONTROLr, 92 VLAN_XLATE_PARITY_STATUS_INTR_0r, VLAN_XLATE_PARITY_STATUS_INTR_1r, 93 VLAN_XLATE_PARITY_STATUS_NACK_0r, VLAN_XLATE_PARITY_STATUS_NACK_1r}, 94 { PARITY_ENf, VFP_POLICY_PAR_ERRf, NULL, 95 VFP_POLICY_TABLEm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 96 VFP_POLICY_PARITY_CONTROLr, 97 VFP_POLICY_PARITY_STATUS_INTRr, INVALIDr, 98 VFP_POLICY_PARITY_STATUS_NACKr, INVALIDr}, 99 { PARITY_ENf, VLAN_PROT_PAR_ERRf, NULL, 100 VLAN_PROTOCOL_DATAm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 101 VLAN_PROT_PARITY_CONTROLr, 102 VLAN_PROT_PARITY_STATUS_INTRr, INVALIDr, 103 VLAN_PROT_PARITY_STATUS_NACKr, INVALIDr}, 104 { PARITY_ENf, VLAN_SUBNET_PAR_ERRf, NULL, 105 VLAN_SUBNET_DATA_ONLYm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 106 VLAN_SUBNET_PARITY_CONTROLr, 107 VLAN_SUBNET_PARITY_STATUS_INTRr, INVALIDr, 108 VLAN_SUBNET_PARITY_STATUS_NACKr, INVALIDr}, 109 { ECC_ENf, PORT_TABLE_PAR_ERRf, NULL, 110 PORT_TABm, _SOC_PARITY_INFO_TYPE_SINGLE_ECC, 111 PORT_TABLE_ECC_CONTROLr, 112 PORT_TABLE_ECC_STATUS_INTRr, INVALIDr, 113 PORT_TABLE_ECC_STATUS_NACKr, INVALIDr}, 114 { PARITY_ENf, SYS_CONFIG_PAR_ERRf, NULL, 115 SYSTEM_CONFIG_TABLEm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 116 SYSTEM_CONFIG_PARITY_CONTROLr, 117 SYSTEM_CONFIG_PARITY_STATUS_INTRr, INVALIDr, 118 SYSTEM_CONFIG_PARITY_STATUS_NACKr, INVALIDr}, 119 { PARITY_ENf, LMEP_PAR_ERRf, NULL, 120 LMEPm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 121 LMEP_PARITY_CONTROLr, 122 LMEP_PARITY_STATUS_INTRr, INVALIDr, 123 LMEP_PARITY_STATUS_NACKr, INVALIDr}, 124 { PARITY_ENf, CPU_TS_POLICY_PAR_ERRf, NULL, 125 CPU_TS_MAPm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 126 CPU_TS_PARITY_CONTROLr, 127 CPU_TS_PARITY_STATUS_INTRr, INVALIDr, 128 CPU_TS_PARITY_STATUS_NACKr, INVALIDr}, 129 { PARITY_ENf, VLAN_RANGE_PAR_ERRf, NULL, 130 ING_VLAN_RANGEm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 131 VLAN_RANGE_PARITY_CONTROLr, 132 VLAN_RANGE_PARITY_STATUS_INTRr, INVALIDr, 133 VLAN_RANGE_PARITY_STATUS_NACKr, INVALIDr}, 134 { PARITY_ENf, MOD_MAP_PAR_ERRf, NULL, 135 ING_MOD_MAP_TABLEm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 136 MOD_MAP_PARITY_CONTROLr, 137 MOD_MAP_PARITY_STATUS_INTRr, INVALIDr, 138 MOD_MAP_PARITY_STATUS_NACKr, INVALIDr}, 139 { PARITY_ENf, FP_UDF_PAR_ERRf, NULL, 140 FP_UDF_OFFSETm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 141 FP_UDF_PARITY_CONTROLr, 142 FP_UDF_PARITY_STATUS_INTRr, INVALIDr, 143 FP_UDF_PARITY_STATUS_NACKr, INVALIDr}, 144 { PARITY_ENf, L3_TUNNEL_PAR_ERRf, NULL, 145 L3_TUNNELm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 146 L3_TUNNEL_PARITY_CONTROLr, 147 L3_TUNNEL_PARITY_STATUS_INTRr, INVALIDr, 148 L3_TUNNEL_PARITY_STATUS_NACKr, INVALIDr}, 149 { ECC_ENf, WLAN_SVP_PAR_ERRf, NULL, 150 WLAN_SVP_TABLEm, _SOC_PARITY_INFO_TYPE_SINGLE_ECC, 151 WLAN_SVP_ECC_CONTROLr, 152 WLAN_SVP_ECC_STATUS_INTRr, INVALIDr, 153 WLAN_SVP_ECC_STATUS_NACKr, INVALIDr}, 154 { ECC_ENf, SRC_TRUNK_PAR_ERRf, NULL, 155 SOURCE_TRUNK_MAP_TABLEm, _SOC_PARITY_INFO_TYPE_SINGLE_ECC, 156 SRC_TRUNK_ECC_CONTROLr, 157 SRC_TRUNK_ECC_STATUS_INTRr, INVALIDr, 158 SRC_TRUNK_ECC_STATUS_NACKr, INVALIDr}, 159 { ECC_ENf, LPORT_PAR_ERRf, NULL, 160 LPORT_TABm, _SOC_PARITY_INFO_TYPE_SINGLE_ECC, 161 LPORT_ECC_CONTROLr, 162 LPORT_ECC_STATUS_INTRr, INVALIDr, 163 LPORT_ECC_STATUS_NACKr, INVALIDr}, 164 { ECC_ENf, IARB_PKT_ERRf, "Iarb packet ecc error", 165 INVALIDm, _SOC_PARITY_INFO_TYPE_SINGLE_ECC, 166 IARB_PKT_ECC_CONTROLr, 167 IARB_PKT_ECC_STATUS_INTRr, INVALIDr, 168 INVALIDr, INVALIDr}, 169 { ECC_ENf, IARB_HDR_ERRf, "Iarb header ecc error", 170 INVALIDm, _SOC_PARITY_INFO_TYPE_SINGLE_ECC, 171 IARB_HDR_ECC_CONTROLr, 172 IARB_HDR_ECC_STATUS_INTRr, INVALIDr, 173 INVALIDr, INVALIDr}, 174 { INVALIDf, INVALIDf}, /* table terminator */ 175 }; 176 177 STATIC _soc_parity_info_t _soc_tr2_ip1_parity_info[] = { 178 { PARITY_ENf, VLAN_PAR_ERRf, NULL, 179 VLAN_TABm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 180 VLAN_PARITY_CONTROLr, 181 VLAN_PARITY_STATUS_INTRr, INVALIDr, 182 VLAN_PARITY_STATUS_NACKr, INVALIDr}, 183 { PARITY_ENf, SVP_PAR_ERRf, NULL, 184 SOURCE_VPm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 185 SOURCE_VP_PARITY_CONTROLr, 186 SOURCE_VP_PARITY_STATUS_INTRr, INVALIDr, 187 SOURCE_VP_PARITY_STATUS_NACKr, INVALIDr}, 188 { PARITY_ENf, L3_IIF_PAR_ERRf, NULL, 189 L3_IIFm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 190 L3_IIF_PARITY_CONTROLr, 191 L3_IIF_PARITY_STATUS_INTRr, INVALIDr, 192 L3_IIF_PARITY_STATUS_NACKr, INVALIDr}, 193 { PARITY_ENf, MPLS_ENTRY_PAR_ERRf, NULL, 194 MPLS_ENTRYm, _SOC_PARITY_INFO_TYPE_DUAL_PARITY, 195 MPLS_ENTRY_PARITY_CONTROLr, 196 MPLS_ENTRY_PARITY_STATUS_INTR_0r, MPLS_ENTRY_PARITY_STATUS_INTR_1r, 197 MPLS_ENTRY_PARITY_STATUS_NACK_0r, MPLS_ENTRY_PARITY_STATUS_NACK_1r}, 198 { PARITY_ENf, L2_ENTRY_PAR_ERRf, NULL, 199 L2Xm, _SOC_PARITY_INFO_TYPE_DUAL_PARITY, 200 L2_ENTRY_PARITY_CONTROLr, 201 L2_ENTRY_PARITY_STATUS_INTR_0r, L2_ENTRY_PARITY_STATUS_INTR_1r, 202 L2_ENTRY_PARITY_STATUS_NACK_0r, L2_ENTRY_PARITY_STATUS_NACK_1r}, 203 { PARITY_ENf, L3_ENTRY_PAR_ERRf, NULL, 204 L3_ENTRY_ONLYm, _SOC_PARITY_INFO_TYPE_DUAL_PARITY, 205 L3_ENTRY_PARITY_CONTROLr, 206 L3_ENTRY_PARITY_STATUS_INTR_0r, L3_ENTRY_PARITY_STATUS_INTR_1r, 207 L3_ENTRY_PARITY_STATUS_NACK_0r, L3_ENTRY_PARITY_STATUS_NACK_1r}, 208 { PARITY_ENf, L3_DEFIP_DATA_PAR_ERRf, NULL, 209 L3_DEFIP_DATA_ONLYm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 210 L3_DEFIP_DATA_PARITY_CONTROLr, 211 L3_DEFIP_DATA_PARITY_STATUS_INTRr, INVALIDr, 212 L3_DEFIP_DATA_PARITY_STATUS_NACKr, INVALIDr}, 213 /* { IESMIF_INTRf }, special conditions interrupts 214 { INVALIDf, IESMIF_INTRf, "ESM interface error", 215 INVALIDm, _SOC_PARITY_INFO_TYPE_GENERIC, 216 INVALIDr, 217 INVALIDr, INVALIDr, 218 INVALIDr, INVALIDr }, */ 219 { PARITY_ENf, ING_PRI_CNG_MAP_INTRf, NULL, 220 ING_PRI_CNG_MAPm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 221 ING_PRI_CNG_MAP_PARITY_CONTROLr, 222 ING_PRI_CNG_MAP_PARITY_STATUS_INTRr, INVALIDr, 223 ING_PRI_CNG_MAP_PARITY_STATUS_NACKr, INVALIDr}, 224 { PARITY_ENf, L2_MOD_FIFO_INTRf, NULL, 225 L2_MOD_FIFOm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 226 L2_MOD_FIFO_PARITY_CONTROLr, 227 L2_MOD_FIFO_PARITY_STATUS_INTRr, INVALIDr, 228 L2_MOD_FIFO_PARITY_STATUS_NACKr, INVALIDr}, 229 { PARITY_ENf, L2_USER_ENTRY_DATA_INTRf, NULL, 230 L2_USER_ENTRY_DATA_ONLYm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 231 L2_USER_ENTRY_DATA_PARITY_CONTROLr, 232 L2_USER_ENTRY_DATA_PARITY_STATUS_INTRr, INVALIDr, 233 L2_USER_ENTRY_DATA_PARITY_STATUS_NACKr, INVALIDr}, 234 /* { L3LU_ERB_INTRf }, special conditions interrupts 235 { INVALIDf, L3LU_ERB_INTRf, "Fatal ESM error", 236 INVALIDm, _SOC_PARITY_INFO_TYPE_GENERIC, 237 INVALIDr, 238 INVALIDr, INVALIDr, 239 INVALIDr, INVALIDr }, */ 240 { PARITY_ENf, PORT_OR_TRUNK_MAC_COUNT_INTRf, NULL, 241 PORT_OR_TRUNK_MAC_COUNTm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 242 PORT_OR_TRUNK_MAC_COUNT_PARITY_CONTROLr, 243 PORT_OR_TRUNK_MAC_COUNT_PARITY_STATUS_INTRr, INVALIDr, 244 PORT_OR_TRUNK_MAC_COUNT_PARITY_STATUS_NACKr, INVALIDr}, 245 { PARITY_ENf, PORT_OR_TRUNK_MAC_LIMIT_INTRf, NULL, 246 PORT_OR_TRUNK_MAC_LIMITm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 247 PORT_OR_TRUNK_MAC_LIMIT_PARITY_CONTROLr, 248 PORT_OR_TRUNK_MAC_LIMIT_PARITY_STATUS_INTRr, INVALIDr, 249 PORT_OR_TRUNK_MAC_LIMIT_PARITY_STATUS_NACKr, INVALIDr}, 250 { PARITY_ENf, VFI_INTRf, NULL, 251 VFIm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 252 VFI_PARITY_CONTROLr, 253 VFI_PARITY_STATUS_INTRr, INVALIDr, 254 VFI_PARITY_STATUS_NACKr, INVALIDr}, 255 { PARITY_ENf, VLAN_MPLS_INTRf, NULL, 256 VLAN_MPLSm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 257 VLAN_MPLS_PARITY_CONTROLr, 258 VLAN_MPLS_PARITY_STATUS_INTRr, INVALIDr, 259 VLAN_MPLS_PARITY_STATUS_NACKr, INVALIDr}, 260 { PARITY_ENf, VLAN_OR_VFI_MAC_COUNT_INTRf,NULL, 261 VLAN_OR_VFI_MAC_COUNTm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 262 VLAN_OR_VFI_MAC_COUNT_PARITY_CONTROLr, 263 VLAN_OR_VFI_MAC_COUNT_PARITY_STATUS_INTRr, INVALIDr, 264 VLAN_OR_VFI_MAC_COUNT_PARITY_STATUS_NACKr, INVALIDr}, 265 { PARITY_ENf, VLAN_OR_VFI_MAC_LIMIT_INTRf, NULL, 266 VLAN_OR_VFI_MAC_LIMITm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 267 VLAN_OR_VFI_MAC_LIMIT_PARITY_CONTROLr, 268 VLAN_OR_VFI_MAC_LIMIT_PARITY_STATUS_INTRr, INVALIDr, 269 VLAN_OR_VFI_MAC_LIMIT_PARITY_STATUS_NACKr, INVALIDr}, 270 { PARITY_ENf, VLAN_STG_INTRf, NULL, 271 STG_TABm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 272 VLAN_STG_PARITY_CONTROLr, 273 VLAN_STG_PARITY_STATUS_INTRr, INVALIDr, 274 VLAN_STG_PARITY_STATUS_NACKr, INVALIDr}, 275 { PARITY_ENf, VRF_INTRf, NULL, 276 VRFm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 277 VRF_PARITY_CONTROLr, 278 VRF_PARITY_STATUS_INTRr, INVALIDr, 279 VRF_PARITY_STATUS_NACKr, INVALIDr}, 280 { PARITY_ENf, VFI_1_INTRf, NULL, 281 VFI_1m, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 282 VFI_1_PARITY_CONTROLr, 283 VFI_1_PARITY_STATUS_INTRr, INVALIDr, 284 VFI_1_PARITY_STATUS_NACKr, INVALIDr}, 285 { PARITY_ENf, L3_DEFIP_128_DATA_PAR_ERRf, NULL, 286 L3_DEFIP_128_DATA_ONLYm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 287 L3_DEFIP_128_DATA_PARITY_CONTROLr, 288 L3_DEFIP_128_DATA_PARITY_STATUS_INTRr, INVALIDr, 289 L3_DEFIP_128_DATA_PARITY_STATUS_NACKr, INVALIDr}, 290 { PARITY_ENf, DSCP_PAR_ERRf, NULL, 291 DSCP_TABLEm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 292 DSCP_TABLE_PARITY_CONTROLr, 293 DSCP_TABLE_PARITY_STATUS_INTRr, INVALIDr, 294 DSCP_TABLE_PARITY_STATUS_NACKr, INVALIDr}, 295 { INVALIDf, INVALIDf}, /* table terminator */ 296 }; 297 298 STATIC _soc_parity_info_t _soc_tr2_ip2_parity_info[] = { 299 { PARITY_ENf, FP_FIELD_SEL_PAR_ERRf, NULL, 300 FP_PORT_FIELD_SELm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 301 FP_FIELD_SEL_PARITY_CONTROLr, 302 FP_FIELD_SEL_PARITY_STATUS_INTRr, INVALIDr, 303 FP_FIELD_SEL_PARITY_STATUS_NACKr, INVALIDr}, 304 { PARITY_ENf, TTL_FN_PAR_ERRf, NULL, 305 TTL_FNm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 306 TTL_FN_PARITY_CONTROLr, 307 TTL_FN_PARITY_STATUS_INTRr, INVALIDr, 308 TTL_FN_PARITY_STATUS_NACKr, INVALIDr}, 309 { PARITY_ENf, TOS_FN_PAR_ERRf, NULL, 310 TOS_FNm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 311 TOS_FN_PARITY_CONTROLr, 312 TOS_FN_PARITY_STATUS_INTRr, INVALIDr, 313 TOS_FN_PARITY_STATUS_NACKr, INVALIDr}, 314 315 /* Start of parity-unrelated OAM faults */ 316 317 { ANY_RMEP_TLV_PORT_DOWN_INTRf, ANY_RMEP_TLV_PORT_DOWN_INTRf, NULL, 318 INVALIDm, _SOC_PARITY_INFO_TYPE_OAM, 319 INVALIDr, 320 INVALIDr, INVALIDr, 321 INVALIDr, INVALIDr}, 322 323 { ANY_RMEP_TLV_PORT_UP_INTRf, ANY_RMEP_TLV_PORT_UP_INTRf, NULL, 324 INVALIDm, _SOC_PARITY_INFO_TYPE_OAM, 325 INVALIDr, 326 INVALIDr, INVALIDr, 327 INVALIDr, INVALIDr}, 328 329 { ANY_RMEP_TLV_INTERFACE_DOWN_INTRf, ANY_RMEP_TLV_INTERFACE_DOWN_INTRf, 330 NULL, 331 INVALIDm, _SOC_PARITY_INFO_TYPE_OAM, 332 INVALIDr, 333 INVALIDr, INVALIDr, 334 INVALIDr, INVALIDr}, 335 336 { ANY_RMEP_TLV_INTERFACE_UP_INTRf, ANY_RMEP_TLV_INTERFACE_UP_INTRf, NULL, 337 INVALIDm, _SOC_PARITY_INFO_TYPE_OAM, 338 INVALIDr, 339 INVALIDr, INVALIDr, 340 INVALIDr, INVALIDr}, 341 342 { XCON_CCM_DEFECT_INTRf, XCON_CCM_DEFECT_INTRf, NULL, 343 INVALIDm, _SOC_PARITY_INFO_TYPE_OAM, 344 INVALIDr, 345 INVALIDr, INVALIDr, 346 INVALIDr, INVALIDr}, 347 348 { ERROR_CCM_DEFECT_INTRf, ERROR_CCM_DEFECT_INTRf, NULL, 349 INVALIDm, _SOC_PARITY_INFO_TYPE_OAM, 350 INVALIDr, 351 INVALIDr, INVALIDr, 352 INVALIDr, INVALIDr}, 353 354 { SOME_RDI_DEFECT_INTRf, SOME_RDI_DEFECT_INTRf, NULL, 355 INVALIDm, _SOC_PARITY_INFO_TYPE_OAM, 356 INVALIDr, 357 INVALIDr, INVALIDr, 358 INVALIDr, INVALIDr}, 359 360 { SOME_RMEP_CCM_DEFECT_INTRf, SOME_RMEP_CCM_DEFECT_INTRf, NULL, 361 INVALIDm, _SOC_PARITY_INFO_TYPE_OAM, 362 INVALIDr, 363 INVALIDr, INVALIDr, 364 INVALIDr, INVALIDr}, 365 366 /* End of parity-unrelated OAM faults */ 367 368 { PARITY_ENf, IFP_POLICY_PAR_ERRf, NULL, 369 FP_POLICY_TABLEm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 370 IFP_POLICY_PARITY_CONTROLr, 371 IFP_POLICY_PARITY_STATUS_INTRr, INVALIDr, 372 IFP_POLICY_PARITY_STATUS_NACKr, INVALIDr}, 373 { PARITY_ENf, IFP_STORM_PAR_ERRf, NULL, 374 FP_STORM_CONTROL_METERSm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 375 IFP_STORM_CONTROL_PARITY_CONTROLr, 376 IFP_STORM_CONTROL_PARITY_STATUS_INTRr, INVALIDr, 377 IFP_STORM_CONTROL_PARITY_STATUS_NACKr, INVALIDr}, 378 379 { PARITY_ENf, NHOP_PAR_ERRf, NULL, 380 INITIAL_ING_L3_NEXT_HOPm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 381 INITIAL_NHOP_PARITY_CONTROLr, 382 INITIAL_NHOP_PARITY_STATUS_INTRr, INVALIDr, 383 INITIAL_NHOP_PARITY_STATUS_NACKr, INVALIDr}, 384 { PARITY_ENf, ECMP_GRP_PAR_ERRf, NULL, 385 INITIAL_L3_ECMP_COUNTm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 386 INI_ECMP_GRP_PARITY_CONTROLr, 387 INI_ECMP_GRP_PARITY_STATUS_INTRr, INVALIDr, 388 INI_ECMP_GRP_PARITY_STATUS_NACKr, INVALIDr}, 389 { PARITY_ENf, L3_ECMP_PAR_ERRf, NULL, 390 INITIAL_L3_ECMPm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 391 INI_L3_ECMP_PARITY_CONTROLr, 392 INI_L3_ECMP_PARITY_STATUS_INTRr, INVALIDr, 393 INI_L3_ECMP_PARITY_STATUS_NACKr, INVALIDr}, 394 { PARITY_ENf, ING_DVP_PAR_ERRf, NULL, 395 ING_DVP_TABLEm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 396 ING_DVP_PARITY_CONTROLr, 397 ING_DVP_PARITY_STATUS_INTRr, INVALIDr, 398 ING_DVP_PARITY_STATUS_NACKr, INVALIDr}, 399 { PARITY_ENf, PROT_NHI_PAR_ERRf, NULL, 400 INITIAL_PROT_NHI_TABLEm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 401 INI_PROT_NHI_PARITY_CONTROLr, 402 INI_PROT_NHI_PARITY_STATUS_INTRr, INVALIDr, 403 INI_PROT_NHI_PARITY_STATUS_NACKr, INVALIDr}, 404 { PARITY_ENf, PORT_CBL_PAR_ERRf, NULL, 405 PORT_CBL_TABLEm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 406 PORT_CBL_PARITY_CONTROLr, 407 PORT_CBL_PARITY_STATUS_INTRr, INVALIDr, 408 PORT_CBL_PARITY_STATUS_NACKr, INVALIDr}, 409 { PARITY_ENf, L3_IPMC_1_PAR_ERRf, NULL, 410 L3_IPMC_1m, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 411 L3_IPMC_1_PARITY_CONTROLr, 412 L3_IPMC_1_PARITY_STATUS_INTRr, INVALIDr, 413 L3_IPMC_1_PARITY_STATUS_NACKr, INVALIDr}, 414 { PARITY_ENf, MA_INDEX_PAR_ERRf, NULL, 415 MA_INDEXm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 416 MA_INDEX_PARITY_CONTROLr, 417 MA_INDEX_PARITY_STATUS_INTRr, INVALIDr, 418 MA_INDEX_PARITY_STATUS_NACKr, INVALIDr}, 419 { PARITY_ENf, RMEP_PAR_ERRf, NULL, 420 RMEPm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 421 RMEP_PARITY_CONTROLr, 422 RMEP_PARITY_STATUS_INTRr, INVALIDr, 423 RMEP_PARITY_STATUS_NACKr, INVALIDr}, 424 { PARITY_ENf, MAID_PAR_ERRf, NULL, 425 MAID_REDUCTIONm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 426 MAID_PARITY_CONTROLr, 427 MAID_PARITY_STATUS_INTRr, INVALIDr, 428 MAID_PARITY_STATUS_NACKr, INVALIDr}, 429 { PARITY_ENf, MA_STATE_PAR_ERRf, NULL, 430 MA_STATEm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 431 MA_STATE_PARITY_CONTROLr, 432 MA_STATE_PARITY_STATUS_INTRr, INVALIDr, 433 MA_STATE_PARITY_STATUS_NACKr, INVALIDr}, 434 { PARITY_ENf, EXT_IFP_ACT_PAR_ERRf, NULL, 435 EXT_IFP_ACTION_PROFILEm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 436 EXT_IFP_ACT_PARITY_CONTROLr, 437 EXT_IFP_ACT_PARITY_STATUS_INTRr, INVALIDr, 438 EXT_IFP_ACT_PARITY_STATUS_NACKr, INVALIDr}, 439 { INVALIDf, INVALIDf}, /* table terminator */ 440 }; 441 442 STATIC _soc_parity_info_t _soc_tr2_ip3_parity_info[] = { 443 { PARITY_ENf, ING_NHOP_PAR_ERRf, NULL, 444 ING_L3_NEXT_HOPm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 445 ING_L3_NEXT_HOP_PARITY_CONTROLr, 446 ING_L3_NEXT_HOP_PARITY_STATUS_INTRr, INVALIDr, 447 ING_L3_NEXT_HOP_PARITY_STATUS_NACKr, INVALIDr}, 448 { PARITY_ENf, ING_IPFIX_SESS_PAR_ERRf, NULL, 449 ING_IPFIX_SESSION_TABLEm, _SOC_PARITY_INFO_TYPE_DUAL_PARITY, 450 ING_IPFIX_SESSION_PARITY_CONTROLr, 451 ING_IPFIX_SESSION_PARITY_STATUS_INTR_0r, ING_IPFIX_SESSION_PARITY_STATUS_INTR_1r, 452 ING_IPFIX_SESSION_PARITY_STATUS_NACK_0r, ING_IPFIX_SESSION_PARITY_STATUS_NACK_1r}, 453 { PARITY_ENf, ING_IPFIX_EXPORT_PAR_ERRf, NULL, 454 ING_IPFIX_EXPORT_FIFOm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 455 ING_IPFIX_EXPORT_FIFO_PARITY_CONTROLr, 456 INVALIDr, INVALIDr, 457 ING_IPFIX_EXPORT_FIFO_PARITY_STATUS_NACKr, INVALIDr}, 458 { PARITY_ENf, ING_IPFIX_EOP_PAR_ERRf, NULL, 459 ING_IPFIX_EOP_BUFFERm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 460 ING_IPFIX_EOP_BUF_PARITY_CONTROLr, 461 ING_IPFIX_EOP_BUF_PARITY_STATUS_INTRr, INVALIDr, 462 ING_IPFIX_EOP_BUF_PARITY_STATUS_NACKr, INVALIDr}, 463 { PARITY_ENf, ING_IPFIX_FLOW_PAR_ERRf, NULL, 464 ING_IPFIX_FLOW_RATE_METER_TABLEm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 465 ING_IPFIX_FLOW_PARITY_CONTROLr, 466 ING_IPFIX_FLOW_PARITY_STATUS_INTRr, INVALIDr, 467 ING_IPFIX_FLOW_PARITY_STATUS_NACKr, INVALIDr}, 468 { PARITY_ENf, ICONTROL_OPCODE_BITMAP_PAR_ERRf, "Icontrol opcode bitmap register", 469 INVALIDm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 470 ICONTROL_OPCODE_BITMAP_PARITY_CONTROLr, 471 ICONTROL_OPCODE_BITMAP_PARITY_STATUS_INTRr, INVALIDr, 472 ICONTROL_OPCODE_BITMAP_PARITY_STATUS_NACKr, INVALIDr}, 473 { PARITY_ENf, L3_IPMC_REMAP_PAR_ERRf, NULL, 474 L3_IPMC_REMAPm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 475 L3_IPMC_REMAP_PARITY_CONTROLr, 476 L3_IPMC_REMAP_PARITY_STATUS_INTRr, INVALIDr, 477 L3_IPMC_REMAP_PARITY_STATUS_NACKr, INVALIDr}, 478 { PARITY_ENf, L3_IPMC_PAR_ERRf, NULL, 479 L3_IPMCm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 480 L3_IPMC_PARITY_CONTROLr, 481 L3_IPMC_PARITY_STATUS_INTRr, INVALIDr, 482 L3_IPMC_PARITY_STATUS_NACKr, INVALIDr}, 483 { PARITY_ENf, L2MC_PAR_ERRf, NULL, 484 L2MCm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 485 L2MC_PARITY_CONTROLr, 486 L2MC_PARITY_STATUS_INTRr, INVALIDr, 487 L2MC_PARITY_STATUS_NACKr, INVALIDr}, 488 { PARITY_ENf, IFP_REDIRECTION_PROFILE_PAR_ERRf, NULL, 489 IFP_REDIRECTION_PROFILEm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 490 IFP_REDIRECTION_PROFILE_PARITY_CONTROLr, 491 IFP_REDIRECTION_PROFILE_PARITY_STATUS_INTRr, INVALIDr, 492 IFP_REDIRECTION_PROFILE_PARITY_STATUS_NACKr, INVALIDr}, 493 { PARITY_ENf, L3_ECMP_GROUP_PAR_ERRf, NULL, 494 L3_ECMP_COUNTm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 495 L3_ECMP_GROUP_PARITY_CONTROLr, 496 L3_ECMP_GROUP_PARITY_STATUS_INTRr, INVALIDr, 497 L3_ECMP_GROUP_PARITY_STATUS_NACKr, INVALIDr}, 498 { PARITY_ENf, L3_ECMP_PAR_ERRf, NULL, 499 L3_ECMPm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 500 L3_ECMP_PARITY_CONTROLr, 501 L3_ECMP_PARITY_STATUS_INTRr, INVALIDr, 502 L3_ECMP_PARITY_STATUS_NACKr, INVALIDr}, 503 { INVALIDf, INVALIDf}, /* table terminator */ 504 }; 505 506 STATIC _soc_parity_info_t _soc_tr2_ip3_1_parity_info[] = { 507 { PARITY_ENf, EGR_MASK_PAR_ERRf, NULL, 508 EGR_MASKm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 509 EGR_MASK_PARITY_CONTROLr, 510 EGR_MASK_PARITY_STATUS_INTRr, INVALIDr, 511 EGR_MASK_PARITY_STATUS_NACKr, INVALIDr}, 512 { PARITY_ENf, TRUNK_EGR_MASK_PAR_ERRf, NULL, 513 TRUNK_EGR_MASKm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 514 TRUNK_EGR_MASK_PARITY_CONTROLr, 515 TRUNK_EGR_MASK_PARITY_STATUS_INTRr, INVALIDr, 516 TRUNK_EGR_MASK_PARITY_STATUS_NACKr, INVALIDr}, 517 { PARITY_ENf, TRUNK_BITMAP_PAR_ERRf, NULL, 518 TRUNK_BITMAPm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 519 TRUNK_BITMAP_TABLE_PARITY_CONTROLr, 520 TRUNK_BITMAP_TABLE_PARITY_STATUS_INTRr, INVALIDr, 521 TRUNK_BITMAP_TABLE_PARITY_STATUS_NACKr, INVALIDr}, 522 { PARITY_ENf, TRUNK_GROUP_PAR_ERRf, NULL, 523 TRUNK_GROUPm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 524 TRUNK_GROUP_PARITY_CONTROLr, 525 TRUNK_GROUP_PARITY_STATUS_INTRr, INVALIDr, 526 TRUNK_GROUP_PARITY_STATUS_NACKr, INVALIDr}, 527 { PARITY_ENf, NONUCAST_TRUNK_BLOCK_MASK_PAR_ERRf, NULL, 528 NONUCAST_TRUNK_BLOCK_MASKm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 529 NONUCAST_TRUNK_BLOCK_MASK_PARITY_CONTROLr, 530 NONUCAST_TRUNK_BLOCK_MASK_PARITY_STATUS_INTRr, INVALIDr, 531 NONUCAST_TRUNK_BLOCK_MASK_PARITY_STATUS_NACKr, INVALIDr}, 532 { PARITY_ENf, MAC_BLOCK_TABLE_PAR_ERRf, NULL, 533 MAC_BLOCKm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 534 MAC_BLOCK_TABLE_PARITY_CONTROLr, 535 MAC_BLOCK_TABLE_PARITY_STATUS_INTRr, INVALIDr, 536 MAC_BLOCK_TABLE_PARITY_STATUS_NACKr, INVALIDr}, 537 { PARITY_ENf, MODPORT_MAP_SW_PAR_ERRf, NULL, 538 MODPORT_MAP_SWm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 539 MODPORT_MAP_SW_PARITY_CONTROLr, 540 MODPORT_MAP_SW_PARITY_STATUS_INTRr, INVALIDr, 541 MODPORT_MAP_SW_PARITY_STATUS_NACKr, INVALIDr}, 542 { PARITY_ENf, MODPORT_MAP_MIRROR_PAR_ERRf, NULL, 543 MODPORT_MAP_MIRRORm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 544 MODPORT_MAP_MIRROR_PARITY_CONTROLr, 545 MODPORT_MAP_MIRROR_PARITY_STATUS_INTRr, INVALIDr, 546 MODPORT_MAP_MIRROR_PARITY_STATUS_NACKr, INVALIDr}, 547 { PARITY_ENf, MODPORT_MAP_MIRROR_1_PAR_ERRf, NULL, 548 MODPORT_MAP_MIRROR_1m, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 549 MODPORT_MAP_MIRROR_1_PARITY_CONTROLr, 550 MODPORT_MAP_MIRROR_1_PARITY_STATUS_INTRr, INVALIDr, 551 MODPORT_MAP_MIRROR_1_PARITY_STATUS_NACKr, INVALIDr}, 552 { PARITY_ENf, SRC_MODID_INGRESS_BLOCK_PAR_ERRf, NULL, 553 SRC_MODID_INGRESS_BLOCKm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 554 SRC_MODID_INGRESS_BLOCK_PARITY_CONTROLr, 555 SRC_MODID_INGRESS_BLOCK_PARITY_STATUS_INTRr, INVALIDr, 556 SRC_MODID_INGRESS_BLOCK_PARITY_STATUS_NACKr, INVALIDr}, 557 { PARITY_ENf, SRC_MODID_EGRESS_PAR_ERRf, NULL, 558 SRC_MODID_EGRESSm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 559 SRC_MODID_EGRESS_PARITY_CONTROLr, 560 SRC_MODID_EGRESS_PARITY_STATUS_INTRr, INVALIDr, 561 SRC_MODID_EGRESS_PARITY_STATUS_NACKr, INVALIDr}, 562 { PARITY_ENf, ALTERNATE_EMIRROR_BITMAP_PAR_ERRf, NULL, 563 ALTERNATE_EMIRROR_BITMAPm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 564 ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROLr, 565 ALTERNATE_EMIRROR_BITMAP_PARITY_STATUS_INTRr, INVALIDr, 566 ALTERNATE_EMIRROR_BITMAP_PARITY_STATUS_NACKr, INVALIDr}, 567 { PARITY_ENf, PORT_LAG_FAILOVER_SET_PAR_ERRf, NULL, 568 PORT_LAG_FAILOVER_SETm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 569 PORT_LAG_FAILOVER_SET_PARITY_CONTROLr, 570 PORT_LAG_FAILOVER_SET_PARITY_STATUS_INTRr, INVALIDr, 571 PORT_LAG_FAILOVER_SET_PARITY_STATUS_NACKr, INVALIDr}, 572 { PARITY_ENf, VLAN_PROFILE_2_PAR_ERRf, NULL, 573 VLAN_PROFILE_2m, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 574 VLAN_PROFILE_2_PARITY_CONTROLr, 575 VLAN_PROFILE_2_PARITY_STATUS_INTRr, INVALIDr, 576 VLAN_PROFILE_2_PARITY_STATUS_NACKr, INVALIDr}, 577 { PARITY_ENf, L3_MTU_VALUES_PAR_ERRf, NULL, 578 L3_MTU_VALUESm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 579 L3_MTU_VALUES_PARITY_CONTROLr, 580 L3_MTU_VALUES_PARITY_STATUS_INTRr, INVALIDr, 581 L3_MTU_VALUES_PARITY_STATUS_NACKr, INVALIDr}, 582 { PARITY_ENf, ING_PW_TERM_SEQ_NUM_PAR_ERRf, NULL, 583 ING_PW_TERM_SEQ_NUMm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 584 ING_PW_TERM_SEQ_NUM_PARITY_CONTROLr, 585 ING_PW_TERM_SEQ_NUM_PARITY_STATUS_INTRr, INVALIDr, 586 ING_PW_TERM_SEQ_NUM_PARITY_STATUS_NACKr, INVALIDr}, 587 { PARITY_ENf, ING_SERVICE_COUNTER_TABLE_PAR_ERRf, NULL, 588 ING_SERVICE_COUNTER_TABLEm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 589 ING_SERVICE_COUNTER_TABLE_PARITY_CONTROLr, 590 ING_SERVICE_COUNTER_TABLE_PARITY_STATUS_INTRr, INVALIDr, 591 ING_SERVICE_COUNTER_TABLE_PARITY_STATUS_NACKr, INVALIDr}, 592 { PARITY_ENf, ING_VINTF_COUNTER_TABLE_PAR_ERRf, NULL, 593 ING_VINTF_COUNTER_TABLEm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 594 ING_VINTF_COUNTER_TABLE_PARITY_CONTROLr, 595 ING_VINTF_COUNTER_TABLE_PARITY_STATUS_INTRr, INVALIDr, 596 ING_VINTF_COUNTER_TABLE_PARITY_STATUS_NACKr, INVALIDr}, 597 { PARITY_ENf, VLAN_COS_MAP_PAR_ERRf, NULL, 598 VLAN_COS_MAPm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 599 VLAN_COS_MAP_PARITY_CONTROLr, 600 VLAN_COS_MAP_PARITY_STATUS_INTRr, INVALIDr, 601 VLAN_COS_MAP_PARITY_STATUS_NACKr, INVALIDr}, 602 { PARITY_ENf, E2E_HOL_STATUS_PAR_ERRf, NULL, 603 E2E_HOL_STATUSm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 604 E2E_HOL_STATUS_PARITY_CONTROLr, 605 E2E_HOL_STATUS_PARITY_STATUS_INTRr, INVALIDr, 606 E2E_HOL_STATUS_PARITY_STATUS_NACKr, INVALIDr}, 607 { PARITY_ENf, E2E_HOL_STATUS_1_PAR_ERRf, NULL, 608 E2E_HOL_STATUS_1m, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 609 E2E_HOL_STATUS_1_PARITY_CONTROLr, 610 E2E_HOL_STATUS_1_PARITY_STATUS_INTRr, INVALIDr, 611 E2E_HOL_STATUS_1_PARITY_STATUS_NACKr, INVALIDr}, 612 { PARITY_ENf, UNKNOWN_UCAST_BLOCK_MASK_PAR_ERRf, 613 "UNKNOWN_UCAST_BLOCK_MASK", 614 INVALIDm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 615 UNKNOWN_UCAST_BLOCK_MASK_PARITY_CONTROLr, 616 UNKNOWN_UCAST_BLOCK_MASK_PARITY_STATUS_INTRr, INVALIDr, 617 UNKNOWN_UCAST_BLOCK_MASK_PARITY_STATUS_NACKr, INVALIDr}, 618 { PARITY_ENf, UNKNOWN_MCAST_BLOCK_MASK_PAR_ERRf, 619 "UNKNOWN_MCAST_BLOCK_MASK", 620 INVALIDm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 621 UNKNOWN_MCAST_BLOCK_MASK_PARITY_CONTROLr, 622 UNKNOWN_MCAST_BLOCK_MASK_PARITY_STATUS_INTRr, INVALIDr, 623 UNKNOWN_MCAST_BLOCK_MASK_PARITY_STATUS_NACKr, INVALIDr}, 624 { PARITY_ENf, BCAST_BLOCK_MASK_PAR_ERRf, "BCAST_BLOCK_MASK", 625 INVALIDm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 626 BCAST_BLOCK_MASK_PARITY_CONTROLr, 627 BCAST_BLOCK_MASK_PARITY_STATUS_INTRr, INVALIDr, 628 BCAST_BLOCK_MASK_PARITY_STATUS_NACKr, INVALIDr}, 629 { PARITY_ENf, KNOWN_MCAST_BLOCK_MASK_PAR_ERRf, 630 "KNOWN_MCAST_BLOCK_MASK", 631 INVALIDm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 632 KNOWN_MCAST_BLOCK_MASK_PARITY_CONTROLr, 633 KNOWN_MCAST_BLOCK_MASK_PARITY_STATUS_INTRr, INVALIDr, 634 KNOWN_MCAST_BLOCK_MASK_PARITY_STATUS_NACKr, INVALIDr}, 635 { PARITY_ENf, ING_EGRMSKBMAP_PAR_ERRf, "ING_EGRMSKBMAP", 636 INVALIDm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 637 ING_EGRMSKBMAP_PARITY_CONTROLr, 638 ING_EGRMSKBMAP_PARITY_STATUS_INTRr, INVALIDr, 639 ING_EGRMSKBMAP_PARITY_STATUS_NACKr, INVALIDr}, 640 { PARITY_ENf, LOCAL_SW_DISABLE_DEFAULT_PBM_PAR_ERRf, 641 "LOCAL_SW_DISABLE_DEFAULT_PBM", 642 INVALIDm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 643 LOCAL_SW_DISABLE_DEFAULT_PBM_PARITY_CONTROLr, 644 LOCAL_SW_DISABLE_DEFAULT_PBM_PARITY_STATUS_INTRr, INVALIDr, 645 LOCAL_SW_DISABLE_DEFAULT_PBM_PARITY_STATUS_NACKr, INVALIDr}, 646 { PARITY_ENf, LOCAL_SW_DISABLE_DEFAULT_PBM_MIRR_PAR_ERRf, 647 "LOCAL_SW_DISABLE_DEFAULT_PBM_MIRR", 648 INVALIDm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 649 LOCAL_SW_DISABLE_DEFAULT_PBM_MIRR_PARITY_CONTROLr, 650 LOCAL_SW_DISABLE_DEFAULT_PBM_MIRR_PARITY_STATUS_INTRr, INVALIDr, 651 LOCAL_SW_DISABLE_DEFAULT_PBM_MIRR_PARITY_STATUS_NACKr, INVALIDr}, 652 { PARITY_ENf, IMIRROR_BITMAP_PAR_ERRf, "IMIRROR_BITMAP", 653 INVALIDm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 654 IMIRROR_BITMAP_PARITY_CONTROLr, 655 IMIRROR_BITMAP_PARITY_STATUS_INTRr, INVALIDr, 656 IMIRROR_BITMAP_PARITY_STATUS_NACKr, INVALIDr}, 657 { PARITY_ENf, UNKNOWN_HGI_BITMAP_PAR_ERRf, "UNKNOWN_HGI_BITMAP", 658 INVALIDm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 659 UNKNOWN_HGI_BITMAP_PARITY_CONTROLr, 660 UNKNOWN_HGI_BITMAP_PARITY_STATUS_INTRr, INVALIDr, 661 UNKNOWN_HGI_BITMAP_PARITY_STATUS_NACKr, INVALIDr}, 662 { INVALIDf, INVALIDf}, /* table terminator */ 663 }; 664 665 STATIC _soc_parity_info_t _soc_tr2_ip3_2_parity_info[] = { 666 { PARITY_ENf, EMIRROR_CONTROL_PAR_ERRf, "EMIRROR_CONTROL", 667 INVALIDm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 668 EMIRROR_CONTROL_PARITY_CONTROLr, 669 EMIRROR_CONTROL_PARITY_STATUS_INTRr, INVALIDr, 670 EMIRROR_CONTROL_PARITY_STATUS_NACKr, INVALIDr}, 671 { PARITY_ENf, EMIRROR_CONTROL1_PAR_ERRf, "EMIRROR_CONTROL1", 672 INVALIDm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 673 EMIRROR_CONTROL1_PARITY_CONTROLr, 674 EMIRROR_CONTROL1_PARITY_STATUS_INTRr, INVALIDr, 675 EMIRROR_CONTROL1_PARITY_STATUS_NACKr, INVALIDr}, 676 { PARITY_ENf, EMIRROR_CONTROL2_PAR_ERRf, "EMIRROR_CONTROL2", 677 INVALIDm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 678 EMIRROR_CONTROL2_PARITY_CONTROLr, 679 EMIRROR_CONTROL2_PARITY_STATUS_INTRr, INVALIDr, 680 EMIRROR_CONTROL2_PARITY_STATUS_NACKr, INVALIDr}, 681 { PARITY_ENf, EMIRROR_CONTROL3_PAR_ERRf, "EMIRROR_CONTROL3", 682 INVALIDm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 683 EMIRROR_CONTROL3_PARITY_CONTROLr, 684 EMIRROR_CONTROL3_PARITY_STATUS_INTRr, INVALIDr, 685 EMIRROR_CONTROL3_PARITY_STATUS_NACKr, INVALIDr}, 686 { PARITY_ENf, SW2_EOP_BUFFER_A_PAR_ERRf, "SW2_EOP_BUFFER_A", 687 INVALIDm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 688 SW2_EOP_BUFFER_A_PARITY_CONTROLr, 689 SW2_EOP_BUFFER_A_PARITY_STATUS_INTRr, INVALIDr, 690 INVALIDr, INVALIDr}, 691 { PARITY_ENf, SW2_EOP_BUFFER_B_PAR_ERRf, "SW2_EOP_BUFFER_B", 692 INVALIDm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 693 SW2_EOP_BUFFER_B_PARITY_CONTROLr, 694 SW2_EOP_BUFFER_B_PARITY_STATUS_INTRr, INVALIDr, 695 INVALIDr, INVALIDr}, 696 { PARITY_ENf, SW2_EOP_BUFFER_C_PAR_ERRf, "SW2_EOP_BUFFER_C", 697 INVALIDm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 698 SW2_EOP_BUFFER_C_PARITY_CONTROLr, 699 SW2_EOP_BUFFER_C_PARITY_STATUS_INTRr, INVALIDr, 700 INVALIDr, INVALIDr}, 701 { PARITY_ENf, IP_COUNTERS_PAR_ERRf, "IP_COUNTERS", 702 INVALIDm, _SOC_PARITY_INFO_TYPE_SINGLE_COUNTER, 703 IP_COUNTERS_PARITY_CONTROLr, 704 IP_COUNTERS_PARITY_STATUS_INTRr, INVALIDr, 705 IP_COUNTERS_PARITY_STATUS_NACKr, INVALIDr}, 706 { PARITY_ENf, RDBGC_MEM_INST0_PAR_ERRf, "RDBGC0", 707 INVALIDm, _SOC_PARITY_INFO_TYPE_SINGLE_COUNTER, 708 RDBGC_MEM_INST0_PARITY_CONTROLr, 709 RDBGC_MEM_INST0_PARITY_STATUS_INTRr, INVALIDr, 710 RDBGC_MEM_INST0_PARITY_STATUS_NACKr, INVALIDr}, 711 { PARITY_ENf, RDBGC_MEM_INST1_PAR_ERRf, "RDBGC1", 712 INVALIDm, _SOC_PARITY_INFO_TYPE_SINGLE_COUNTER, 713 RDBGC_MEM_INST1_PARITY_CONTROLr, 714 RDBGC_MEM_INST1_PARITY_STATUS_INTRr, INVALIDr, 715 RDBGC_MEM_INST1_PARITY_STATUS_NACKr, INVALIDr}, 716 { PARITY_ENf, RDBGC_MEM_INST2_PAR_ERRf, "RDBGC2", 717 INVALIDm, _SOC_PARITY_INFO_TYPE_SINGLE_COUNTER, 718 RDBGC_MEM_INST2_PARITY_CONTROLr, 719 RDBGC_MEM_INST2_PARITY_STATUS_INTRr, INVALIDr, 720 RDBGC_MEM_INST2_PARITY_STATUS_NACKr, INVALIDr}, 721 { PARITY_ENf, HG_COUNTERS_PAR_ERRf, "HG_COUNTERS", 722 INVALIDm, _SOC_PARITY_INFO_TYPE_SINGLE_COUNTER, 723 HG_COUNTERS_PARITY_CONTROLr, 724 HG_COUNTERS_PARITY_STATUS_INTRr, INVALIDr, 725 HG_COUNTERS_PARITY_STATUS_NACKr, INVALIDr}, 726 { INVALIDf, INVALIDf}, /* table terminator */ 727 }; 728 729 STATIC _soc_parity_info_t _soc_tr2_ep0_parity_info[] = { 730 { EGR_L3_NEXT_HOP_PARITY_ENf, EGR_NHOP_PAR_ERRf, NULL, 731 EGR_L3_NEXT_HOPm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 732 EGR_EL3_PARITY_CONTROLr, 733 EGR_L3_NEXT_HOP_PARITY_STATUS_INTRr, INVALIDr, 734 EGR_L3_NEXT_HOP_PARITY_STATUS_NACKr, INVALIDr}, 735 { EGR_L3_INTF_PARITY_ENf, EGR_L3_INTF_PAR_ERRf, NULL, 736 EGR_L3_INTFm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 737 EGR_EL3_PARITY_CONTROLr, 738 EGR_L3_INTF_PARITY_STATUS_INTRr, INVALIDr, 739 EGR_L3_INTF_PARITY_STATUS_NACKr, INVALIDr}, 740 { EGR_MPLS_VC_AND_SWAP_LABEL_PARITY_ENf, EGR_MPLS_LABEL_PAR_ERRf, NULL, 741 EGR_MPLS_VC_AND_SWAP_LABEL_TABLEm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 742 EGR_EL3_PARITY_CONTROLr, 743 EGR_MPLS_VC_AND_SWAP_LABEL_PARITY_STATUS_INTRr, INVALIDr, 744 EGR_MPLS_VC_AND_SWAP_LABEL_PARITY_STATUS_NACKr, INVALIDr}, 745 { EGR_VLAN_PARITY_ENf, EGR_VLAN_PAR_ERRf, NULL, 746 EGR_VLANm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 747 EGR_VLAN_PARITY_CONTROLr, 748 EGR_VLAN_PARITY_STATUS_INTRr, INVALIDr, 749 EGR_VLAN_PARITY_STATUS_NACKr, INVALIDr}, 750 { EGR_VLAN_STG_PARITY_ENf, EGR_VLAN_STG_PAR_ERRf, NULL, 751 EGR_VLAN_STGm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 752 EGR_VLAN_PARITY_CONTROLr, 753 EGR_VLAN_STG_PARITY_STATUS_INTRr, INVALIDr, 754 EGR_VLAN_STG_PARITY_STATUS_NACKr, INVALIDr}, 755 { EGR_IP_TUNNEL_PARITY_ENf, EGR_IP_TUNNEL_PAR_ERRf, NULL, 756 EGR_IP_TUNNELm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 757 EGR_VLAN_PARITY_CONTROLr, 758 EGR_IP_TUNNEL_PARITY_STATUS_INTRr, INVALIDr, 759 EGR_IP_TUNNEL_PARITY_STATUS_NACKr, INVALIDr}, 760 { EGR_VLAN_XLATE_PARITY_ENf, EGR_VLAN_XLATE_PAR_ERRf, NULL, 761 EGR_VLAN_XLATEm, _SOC_PARITY_INFO_TYPE_DUAL_PARITY, 762 EGR_VLAN_PARITY_CONTROLr, 763 EGR_VLAN_XLATE_PARITY_STATUS_INTR_0r, EGR_VLAN_XLATE_PARITY_STATUS_INTR_1r, 764 EGR_VLAN_XLATE_PARITY_STATUS_NACK_0r, EGR_VLAN_XLATE_PARITY_STATUS_NACK_1r}, 765 { FRAGMENT_ID_ECC_ENf, EGR_FRAGMENT_ID_TABLE_ECC_ERRf, NULL, 766 EGR_FRAGMENT_ID_TABLEm, _SOC_PARITY_INFO_TYPE_SINGLE_ECC, 767 EGR_EIPT_ECC_CONTROLr, 768 EGR_FRAGMENT_ID_ECC_STATUS_INTRr, INVALIDr, 769 EGR_FRAGMENT_ID_ECC_STATUS_NACKr, INVALIDr}, 770 { EHG_QOS_MAPPING_ECC_ENf, EGR_EHG_QOS_MAP_TABLE_ECC_ERRf, NULL, 771 EGR_EHG_QOS_MAPPING_TABLEm, _SOC_PARITY_INFO_TYPE_SINGLE_ECC, 772 EGR_EIPT_ECC_CONTROLr, 773 EGR_EHG_QOS_MAPPING_ECC_STATUS_INTRr, INVALIDr, 774 EGR_EHG_QOS_MAPPING_ECC_STATUS_NACKr, INVALIDr}, 775 { FRAG_HEADER_ECC_ENf, EGR_FRAG_HEADER_TABLE_ECC_ERRf, "EGR_FRAG_HEADER", 776 INVALIDm, _SOC_PARITY_INFO_TYPE_SINGLE_ECC, 777 EGR_EIPT_ECC_CONTROLr, 778 EGR_FRAG_HEADER_ECC_STATUS_INTRr, INVALIDr, 779 INVALIDr, INVALIDr}, 780 { FRAG_PACKET_ECC_ENf, EGR_FRAG_PKT_TABLE_ECC_ERRf, "EGR_FRAG_PACKET", 781 INVALIDm, _SOC_PARITY_INFO_TYPE_SINGLE_ECC, 782 EGR_EHCPM_ECC_PARITY_CONTROLr, 783 EGR_FRAG_PACKET_ECC_STATUS_INTRr, INVALIDr, 784 INVALIDr, INVALIDr}, 785 { MOD_MAP_PARITY_ENf, EGR_MOD_MAP_TABLE_PAR_ERRf, NULL, 786 EGR_MOD_MAP_TABLEm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 787 EGR_EHCPM_ECC_PARITY_CONTROLr, 788 EGR_MOD_MAP_PARITY_STATUS_INTRr, INVALIDr, 789 EGR_MOD_MAP_PARITY_STATUS_NACKr, INVALIDr}, 790 { EGR_MAC_DA_PROFILE_PARITY_ENf, EGR_MAC_DA_PROFILE_PAR_ERRf, NULL, 791 EGR_MAC_DA_PROFILEm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 792 EGR_EL3_PARITY_CONTROLr, 793 EGR_MAC_DA_PROFILE_PARITY_STATUS_INTRr, INVALIDr, 794 EGR_MAC_DA_PROFILE_PARITY_STATUS_NACKr, INVALIDr}, 795 { EGR_WLAN_DVP_PARITY_ENf, EGR_WLAN_DVP_PAR_ERRf, NULL, 796 EGR_WLAN_DVPm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 797 EGR_EL3_PARITY_CONTROLr, 798 EGR_WLAN_DVP_PARITY_STATUS_INTRr, INVALIDr, 799 EGR_WLAN_DVP_PARITY_STATUS_NACKr, INVALIDr}, 800 { EGR_VFI_PARITY_ENf, EGR_VFI_PAR_ERRf, NULL, 801 EGR_VFIm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 802 EGR_EL3_PARITY_CONTROLr, 803 EGR_VFI_PARITY_STATUS_INTRr, INVALIDr, 804 EGR_VFI_PARITY_STATUS_NACKr, INVALIDr}, 805 { EGR_IPMC_PARITY_ENf, EGR_IPMC_PAR_ERRf, NULL, 806 EGR_IPMCm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 807 EGR_EL3_PARITY_CONTROLr, 808 EGR_IPMC_PARITY_STATUS_INTRr, INVALIDr, 809 EGR_IPMC_PARITY_STATUS_NACKr, INVALIDr}, 810 { EGR_MPLS_EXP_MAPPING_2_PARITY_ENf, EGR_MPLS_EXP_MAPPING_2_PAR_ERRf, 811 NULL, 812 EGR_MPLS_EXP_MAPPING_2m, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 813 EGR_VLAN_PARITY_CONTROLr, 814 EGR_MPLS_EXP_MAPPING_2_PARITY_STATUS_INTRr, INVALIDr, 815 EGR_MPLS_EXP_MAPPING_2_PARITY_STATUS_NACKr, INVALIDr}, 816 { EGR_MPLS_PRI_MAPPING_PARITY_ENf, EGR_MPLS_PRI_MAPPING_PAR_ERRf, NULL, 817 EGR_MPLS_PRI_MAPPINGm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 818 EGR_VLAN_PARITY_CONTROLr, 819 EGR_MPLS_PRI_MAPPING_PARITY_STATUS_INTRr, INVALIDr, 820 EGR_MPLS_PRI_MAPPING_PARITY_STATUS_NACKr, INVALIDr}, 821 { EGR_PRI_CNG_MAP_PARITY_ENf, EGR_PRI_CNG_MAP_PAR_ERRf, NULL, 822 EGR_PRI_CNG_MAPm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 823 EGR_VLAN_PARITY_CONTROLr, 824 EGR_PRI_CNG_MAP_PARITY_STATUS_INTRr, INVALIDr, 825 EGR_PRI_CNG_MAP_PARITY_STATUS_NACKr, INVALIDr}, 826 { EGR_DSCP_TABLE_PARITY_ENf, EGR_DSCP_TABLE_PAR_ERRf, NULL, 827 EGR_DSCP_TABLEm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 828 EGR_VLAN_PARITY_CONTROLr, 829 EGR_DSCP_TABLE_PARITY_STATUS_INTRr, INVALIDr, 830 EGR_DSCP_TABLE_PARITY_STATUS_NACKr, INVALIDr}, 831 { EMOP_BUFFER_ECC_ENf, EGR_EMOP_BUFFER_ECC_ERRf, "EGR_EPMOD", 832 INVALIDm, _SOC_PARITY_INFO_TYPE_SINGLE_ECC, 833 EGR_EPMOD_ECC_CONTROLr, 834 EGR_EMOP_BUFFER_ECC_STATUS_INTRr, INVALIDr, 835 INVALIDr, INVALIDr}, 836 { PARITY_ENf, EGR_IPFIX_EXPORT_PAR_ERRf, NULL, 837 EGR_IPFIX_EXPORT_FIFOm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 838 EGR_IPFIX_EXPORT_FIFO_PARITY_CONTROLr, 839 INVALIDr, INVALIDr, 840 EGR_IPFIX_EXPORT_FIFO_PARITY_STATUS_NACKr, INVALIDr}, 841 { PARITY_ENf, EGR_IPFIX_SESS_PAR_ERRf, NULL, 842 EGR_IPFIX_SESSION_TABLEm, _SOC_PARITY_INFO_TYPE_DUAL_PARITY, 843 EGR_IPFIX_SESSION_PARITY_CONTROLr, 844 EGR_IPFIX_SESSION_PARITY_STATUS_INTR_0r, EGR_IPFIX_SESSION_PARITY_STATUS_INTR_1r, 845 EGR_IPFIX_SESSION_PARITY_STATUS_NACK_0r, EGR_IPFIX_SESSION_PARITY_STATUS_NACK_1r}, 846 { PARITY_ENf, EGR_IPFIX_EOP_PAR_ERRf, NULL, 847 EGR_IPFIX_EOP_BUFFERm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 848 EGR_IPFIX_EOP_BUF_PARITY_CONTROLr, 849 EGR_IPFIX_EOP_BUF_PARITY_STATUS_INTRr, INVALIDr, 850 EGR_IPFIX_EOP_BUF_PARITY_STATUS_NACKr, INVALIDr}, 851 { PARITY_ENf, EGR_EFP_PW_INIT_COUNTER_PAR_ERRf, NULL, 852 EGR_PW_INIT_COUNTERSm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 853 EGR_PW_INIT_COUNTERS_PARITY_CONTROLr, 854 EGR_PW_INIT_COUNTERS_PARITY_STATUS_INTRr, INVALIDr, 855 EGR_PW_INIT_COUNTERS_PARITY_STATUS_NACKr, INVALIDr}, 856 { PARITY_ENf, EGR_EFP_POLICY_TABLE_PAR_ERRf, NULL, 857 EFP_POLICY_TABLEm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 858 EFP_POLICY_PARITY_CONTROLr, 859 EFP_POLICY_PARITY_STATUS_INTRr, INVALIDr, 860 EFP_POLICY_PARITY_STATUS_NACKr, INVALIDr}, 861 { PARITY_ENf, EGR_EFP_METER_TABLE_PAR_ERRf, NULL, 862 EFP_METER_TABLEm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 863 EFP_METER_PARITY_CONTROLr, 864 EFP_METER_PARITY_STATUS_INTRr, INVALIDr, 865 EFP_METER_PARITY_STATUS_NACKr, INVALIDr}, 866 { PERQ_PAR_ENf, EGR_PERQ_XMT_COUNTERS_PAR_ERRf, "EGR_PERQ_XMT_COUNTERS", 867 INVALIDm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 868 EDATABUF_PARITY_CONTROLr, 869 EGR_PERQ_XMT_COUNTERS_STATUS_INTRr, INVALIDr, 870 EGR_PERQ_XMT_COUNTERS_STATUS_NACKr, INVALIDr}, 871 { VINTFCTR_PAR_ENf, EGR_VINTF_COUNTER_TABLE_PAR_ERRf, NULL, 872 EGR_VINTF_COUNTER_TABLEm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 873 EDATABUF_PARITY_CONTROLr, 874 EGR_VINTF_COUNTER_TABLE_STATUS_INTRr, INVALIDr, 875 EGR_VINTF_COUNTER_TABLE_STATUS_NACKr, INVALIDr}, 876 { SVCCTR_PAR_ENf, EGR_SERVICE_COUNTER_TABLE_PAR_ERRf, NULL, 877 EGR_SERVICE_COUNTER_TABLEm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 878 EDATABUF_PARITY_CONTROLr, 879 EGR_SERVICE_COUNTER_TABLE_STATUS_INTRr, INVALIDr, 880 EGR_SERVICE_COUNTER_TABLE_STATUS_NACKr, INVALIDr}, 881 { EFPCTR_PAR_ENf, EGR_FP_COUNTER_TABLE_PAR_ERRf, NULL, 882 EFP_COUNTER_TABLEm, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 883 EDATABUF_PARITY_CONTROLr, 884 EGR_FP_COUNTER_TABLE_STATUS_INTRr, INVALIDr, 885 EGR_FP_COUNTER_TABLE_STATUS_NACKr, INVALIDr}, 886 { INVALIDf, INVALIDf}, /* table terminator */ 887 }; 888 889 STATIC _soc_parity_info_t _soc_tr2_ep1_parity_info[] = { 890 { STATS_PAR_ENf, EGR_STATS_COUNTER_TABLE_PAR_ERRf, "Egress stats", 891 INVALIDm, _SOC_PARITY_INFO_TYPE_SINGLE_COUNTER, 892 EDATABUF_PARITY_CONTROLr, 893 EGR_STATS_COUNTER_TABLE_STATUS_INTRr, INVALIDr, 894 EGR_STATS_COUNTER_TABLE_STATUS_NACKr, INVALIDr}, 895 { INITBUF_ECC_ENf, EGR_INITBUF_ECC_ERRf, "EGR_INITBUF", 896 INVALIDm, _SOC_PARITY_INFO_TYPE_SINGLE_ECC, 897 EGR_EHCPM_ECC_PARITY_CONTROLr, 898 EGR_INITBUF_ECC_STATUS_INTRr, INVALIDr, 899 INVALIDr, INVALIDr}, 900 901 { INVALIDf, INVALIDf}, /* table terminator */ 902 }; 903 904 #if 0 905 STATIC _soc_parity_info_t _soc_tr2_edb_parity_info[] = { 906 { STATS_PAR_ENf, f, NULL, /* Need INTR_STATUS field */ 907 INVALIDm, _SOC_PARITY_INFO_TYPE_GENERIC, 908 EDATABUF_PARITY_CONTROLr, 909 INVALIDr, INVALIDr, 910 INVALIDr, INVALIDr}, 911 { LB_ECC_ENf, f, NULL, /* Need INTR_STATUS field */ 912 INVALIDm, _SOC_PARITY_INFO_TYPE_GENERIC, 913 EDATABUF_PARITY_CONTROLr, 914 INVALIDr, INVALIDr, 915 INVALIDr, INVALIDr}, 916 { CM_ECC_ENf, f, NULL, /* Need INTR_STATUS field */ 917 INVALIDm, _SOC_PARITY_INFO_TYPE_GENERIC, 918 EDATABUF_PARITY_CONTROLr, 919 INVALIDr, INVALIDr, 920 INVALIDr, INVALIDr}, 921 { SP_ECC_ENf, f, NULL, /* Need INTR_STATUS field */ 922 INVALIDm, _SOC_PARITY_INFO_TYPE_GENERIC, 923 EDATABUF_PARITY_CONTROLr, 924 INVALIDr, INVALIDr, 925 INVALIDr, INVALIDr}, 926 { XP3_ECC_ENf, f, NULL, /* Need INTR_STATUS field */ 927 INVALIDm, _SOC_PARITY_INFO_TYPE_GENERIC, 928 EDATABUF_PARITY_CONTROLr, 929 INVALIDr, INVALIDr, 930 INVALIDr, INVALIDr}, 931 { XP2_ECC_ENf, f, NULL, /* Need INTR_STATUS field */ 932 INVALIDm, _SOC_PARITY_INFO_TYPE_GENERIC, 933 EDATABUF_PARITY_CONTROLr, 934 INVALIDr, INVALIDr, 935 INVALIDr, INVALIDr}, 936 { XP1_ECC_ENf, f, NULL, /* Need INTR_STATUS field */ 937 INVALIDm, _SOC_PARITY_INFO_TYPE_GENERIC, 938 EDATABUF_PARITY_CONTROLr, 939 INVALIDr, INVALIDr, 940 INVALIDr, INVALIDr}, 941 { XP0_ECC_ENf, f, NULL, /* Need INTR_STATUS field */ 942 INVALIDm, _SOC_PARITY_INFO_TYPE_GENERIC, 943 EDATABUF_PARITY_CONTROLr, 944 INVALIDr, INVALIDr, 945 INVALIDr, INVALIDr}, 946 { XQP5_ECC_ENf, f, NULL, /* Need INTR_STATUS field */ 947 INVALIDm, _SOC_PARITY_INFO_TYPE_GENERIC, 948 EDATABUF_PARITY_CONTROLr, 949 INVALIDr, INVALIDr, 950 INVALIDr, INVALIDr}, 951 { XQP4_ECC_ENf, f, NULL, /* Need INTR_STATUS field */ 952 INVALIDm, _SOC_PARITY_INFO_TYPE_GENERIC, 953 EDATABUF_PARITY_CONTROLr, 954 INVALIDr, INVALIDr, 955 INVALIDr, INVALIDr}, 956 { XQP3_ECC_ENf, f, NULL, /* Need INTR_STATUS field */ 957 INVALIDm, _SOC_PARITY_INFO_TYPE_GENERIC, 958 EDATABUF_PARITY_CONTROLr, 959 INVALIDr, INVALIDr, 960 INVALIDr, INVALIDr}, 961 { XQP2_ECC_ENf, f, NULL, /* Need INTR_STATUS field */ 962 INVALIDm, _SOC_PARITY_INFO_TYPE_GENERIC, 963 EDATABUF_PARITY_CONTROLr, 964 INVALIDr, INVALIDr, 965 INVALIDr, INVALIDr}, 966 { XQP1_ECC_ENf, f, NULL, /* Need INTR_STATUS field */ 967 INVALIDm, _SOC_PARITY_INFO_TYPE_GENERIC, 968 EDATABUF_PARITY_CONTROLr, 969 INVALIDr, INVALIDr, 970 INVALIDr, INVALIDr}, 971 { XQP0_ECC_ENf, f, NULL, /* Need INTR_STATUS field */ 972 INVALIDm, _SOC_PARITY_INFO_TYPE_GENERIC, 973 EDATABUF_PARITY_CONTROLr, 974 INVALIDr, INVALIDr, 975 INVALIDr, INVALIDr}, 976 { GP1_ECC_ENf, f, NULL, /* Need INTR_STATUS field */ 977 INVALIDm, _SOC_PARITY_INFO_TYPE_GENERIC, 978 EDATABUF_PARITY_CONTROLr, 979 INVALIDr, INVALIDr, 980 INVALIDr, INVALIDr}, 981 { GP0_ECC_ENf, f, NULL, /* Need INTR_STATUS field */ 982 INVALIDm, _SOC_PARITY_INFO_TYPE_GENERIC, 983 EDATABUF_PARITY_CONTROLr, 984 INVALIDr, INVALIDr, 985 INVALIDr, INVALIDr}, 986 { RESIDBUF_ECC_ENf, f, NULL, /* Need INTR_STATUS field */ 987 INVALIDm, _SOC_PARITY_INFO_TYPE_GENERIC, 988 EDATABUF_PARITY_CONTROLr, 989 INVALIDr, INVALIDr, 990 INVALIDr, INVALIDr}, 991 { EFPCTR_PAR_ENf, f, NULL, /* Need INTR_STATUS field */ 992 INVALIDm, _SOC_PARITY_INFO_TYPE_GENERIC, 993 EDATABUF_PARITY_CONTROLr, 994 INVALIDr, INVALIDr, 995 INVALIDr, INVALIDr}, 996 { INVALIDf, INVALIDf}, /* table terminator */ 997 }; 998 #endif 999 1000 STATIC _soc_parity_info_t _soc_tr2_xqp_parity_info[] = { 1001 { EHG_TX_DATAf, EHG_TX_DATAf, NULL, 1002 XQPORT_EHG_TX_TUNNEL_DATAm, _SOC_PARITY_INFO_TYPE_SINGLE_ECC, 1003 XQPORT_PARITY_CONTROLr, 1004 XQPORT_EHG_TX_DATA_PARITY_STATUS_INTRr, XQPORT_FORCE_SINGLE_BIT_ERRORr, 1005 XQPORT_EHG_TX_DATA_PARITY_STATUS_NACKr, XQPORT_FORCE_DOUBLE_BIT_ERRORr}, 1006 1007 { XQBOD_RXFIFOf, XQBOD_RXFIFOf, "XQBOD_RXFIFO", 1008 INVALIDm, _SOC_PARITY_INFO_TYPE_SINGLE_ECC, 1009 XQPORT_PARITY_CONTROLr, 1010 XQPORT_XQBOD_RXFIFO_PARITY_STATUS_INTRr, XQPORT_FORCE_SINGLE_BIT_ERRORr, 1011 INVALIDr, XQPORT_FORCE_DOUBLE_BIT_ERRORr}, 1012 { XQBODE_TXFIFOf, XQBODE_TXFIFOf, "XQBODE_TXFIFO", 1013 INVALIDm, _SOC_PARITY_INFO_TYPE_SINGLE_ECC, 1014 XQPORT_PARITY_CONTROLr, 1015 XQPORT_XQBODE_TXFIFO_PARITY_STATUS_INTRr, XQPORT_FORCE_SINGLE_BIT_ERRORr, 1016 INVALIDr, XQPORT_FORCE_DOUBLE_BIT_ERRORr}, 1017 { INVALIDf, INVALIDf}, /* table terminator */ 1018 }; 1019 1020 STATIC _soc_parity_info_t _soc_tr2_gp_parity_info[] = { 1021 { EHG_TX_DATAf, EHG_TX_DATAf, NULL, 1022 GPORT_EHG_TX_TUNNEL_DATAm, _SOC_PARITY_INFO_TYPE_SINGLE_ECC, 1023 GPORT_PARITY_CONTROLr, 1024 GPORT_EHG_TX_DATA_PARITY_STATUS_INTRr, GPORT_FORCE_SINGLE_BIT_ERRORr, 1025 GPORT_EHG_TX_DATA_PARITY_STATUS_NACKr, GPORT_FORCE_DOUBLE_BIT_ERRORr}, 1026 1027 { GBOD_RXFIFOf, GBOD_RXFIFOf, "GBOD_RXFIFO", 1028 INVALIDm, _SOC_PARITY_INFO_TYPE_SINGLE_ECC, 1029 GPORT_PARITY_CONTROLr, 1030 GPORT_GBOD_RXFIFO_PARITY_STATUS_INTRr, GPORT_FORCE_SINGLE_BIT_ERRORr, 1031 INVALIDr, GPORT_FORCE_DOUBLE_BIT_ERRORr}, 1032 { GBODE_TXFIFOf, GBODE_TXFIFOf, "GBODE_TXFIFO", 1033 INVALIDm, _SOC_PARITY_INFO_TYPE_SINGLE_ECC, 1034 GPORT_PARITY_CONTROLr, 1035 GPORT_GBODE_TXFIFO_PARITY_STATUS_INTRr, GPORT_FORCE_SINGLE_BIT_ERRORr, 1036 INVALIDr, GPORT_FORCE_DOUBLE_BIT_ERRORr}, 1037 { INVALIDf, INVALIDf}, /* table terminator */ 1038 }; 1039 1040 STATIC _soc_parity_info_t _soc_tr2_xp_parity_info[] = { 1041 { RX_FIFO_MEM_ECC_ENf, RX_FIFO_MEM_ERRf, "XPORT_RX_FIFO_MEM", 1042 INVALIDm, _SOC_PARITY_INFO_TYPE_SINGLE_ECC, 1043 XPORT_ECC_CONTROLr, 1044 XPORT_RX_FIFO_MEM_ECC_STATUSr, XPORT_FORCE_SINGLE_BIT_ERRORr, 1045 INVALIDr, XPORT_FORCE_DOUBLE_BIT_ERRORr}, 1046 { TX_FIFO_MEM_ECC_ENf, TX_FIFO_MEM_ERRf, "XPORT_TX_FIFO_MEM", 1047 INVALIDm, _SOC_PARITY_INFO_TYPE_SINGLE_ECC, 1048 XPORT_ECC_CONTROLr, 1049 XPORT_TX_FIFO_MEM_ECC_STATUSr, XPORT_FORCE_SINGLE_BIT_ERRORr, 1050 INVALIDr, XPORT_FORCE_DOUBLE_BIT_ERRORr}, 1051 { INVALIDf, INVALIDf}, /* table terminator */ 1052 }; 1053 1054 STATIC _soc_parity_info_t _soc_tr2_sp_parity_info[] = { 1055 { RX_FIFO_MEM_ECC_ENf, RX_FIFO_MEM_ERRf, "SPORT_RX_FIFO_MEM", 1056 INVALIDm, _SOC_PARITY_INFO_TYPE_SINGLE_ECC, 1057 SPORT_ECC_CONTROLr, 1058 SPORT_RX_FIFO_MEM_ECC_STATUSr, SPORT_FORCE_SINGLE_BIT_ERRORr, 1059 INVALIDr, SPORT_FORCE_DOUBLE_BIT_ERRORr}, 1060 { TX_FIFO_MEM_ECC_ENf, TX_FIFO_MEM_ERRf, "SPORT_TX_FIFO_MEM", 1061 INVALIDm, _SOC_PARITY_INFO_TYPE_SINGLE_ECC, 1062 SPORT_ECC_CONTROLr, 1063 SPORT_TX_FIFO_MEM_ECC_STATUSr, SPORT_FORCE_SINGLE_BIT_ERRORr, 1064 INVALIDr, SPORT_FORCE_DOUBLE_BIT_ERRORr}, 1065 { INVALIDf, INVALIDf}, /* table terminator */ 1066 }; 1067 1068 #if 0 1069 STATIC _soc_parity_info_t _soc_tr2_ut_parity_info[] = { 1070 { f, f, NULL, /* Need parity enable */ 1071 INVALIDm, _SOC_PARITY_INFO_TYPE_GENERIC, 1072 _PARITY_CONTROLr, 1073 INVALIDr, INVALIDr, 1074 INVALIDr, INVALIDr}, 1075 { PARITY_ENf, NULL, 1076 m, _SOC_PARITY_INFO_TYPE_SINGLE_PARITY, 1077 _PARITY_CONTROLr, 1078 _PARITY_STATUS_INTRr, INVALIDr, 1079 _PARITY_STATUS_NACKr, INVALIDr}, 1080 { PARITY_ENf, NULL, 1081 m, _SOC_PARITY_INFO_TYPE_SINGLE_ECC, 1082 _ECC_CONTROLr, 1083 _ECC_STATUS_INTRr, INVALIDr, 1084 _ECC_STATUS_NACKr, INVALIDr}, 1085 { PARITY_ENf, NULL, 1086 m, _SOC_PARITY_INFO_TYPE_DUAL_PARITY, 1087 _PARITY_CONTROLr, 1088 _PARITY_STATUS_INTR_0r, _PARITY_STATUS_INTR_1r, 1089 _PARITY_STATUS_NACK_0r, _PARITY_STATUS_NACK_1r}, 1090 { PARITY_ENf, NULL, 1091 m, _SOC_PARITY_INFO_TYPE_SINGLE_COUNTER, 1092 _PARITY_CONTROLr, 1093 _PARITY_STATUS_INTRr, INVALIDr, 1094 _PARITY_STATUS_NACKr, INVALIDr}, 1095 { f, f, NULL, /* Need INTR_STATUS field */ 1096 INVALIDm, _SOC_PARITY_INFO_TYPE_GENERIC, 1097 _PARITY_CONTROLr, 1098 INVALIDr, INVALIDr, 1099 INVALIDr, INVALIDr}, 1100 { PARITY_ENf, NULL, INVALIDm, _SOC_PARITY_INFO_TYPE_NUM}, /* table terminator */ 1101 }; 1102 #endif 1103 1104 /* 1105 * Is DEQ_CBPERRPTRr for MMU_CBPDATA0 - MMU_CBPDATA31 (15-bit address)? 1106 * How does MMU_CELLCHKm (15-bit address) report parity error? 1107 */ 1108 STATIC _soc_parity_info_t _soc_tr2_mmu_parity_info[] = { 1109 { AGING_CTR_PAR_ERR_ENf, AGING_CTR_PAR_ERRf, NULL, 1110 MMU_AGING_CTRm, _SOC_PARITY_INFO_TYPE_MMU_PARITY, 1111 INVALIDr, 1112 INVALIDr, INVALIDr, 1113 INVALIDr, INVALIDr}, 1114 { AGING_EXP_PAR_ERR_ENf, AGING_EXP_PAR_ERRf, NULL, 1115 MMU_AGING_EXPm, _SOC_PARITY_INFO_TYPE_MMU_PARITY, 1116 INVALIDr, 1117 INVALIDr, INVALIDr, 1118 INVALIDr, INVALIDr}, 1119 { CCP_PAR_ERR_ENf, CCP_PAR_ERRf, NULL, 1120 MMU_CCP_MEMm, _SOC_PARITY_INFO_TYPE_MMU_PARITY, 1121 INVALIDr, 1122 CCPPARITYERRORPTRr, INVALIDr, 1123 INVALIDr, INVALIDr}, 1124 { CFAP_PAR_ERR_ENf, CFAP_PAR_ERRf, NULL, 1125 MMU_CFAP_MEMm, _SOC_PARITY_INFO_TYPE_MMU_PARITY, 1126 INVALIDr, 1127 CFAPPARITYERRORPTRr, INVALIDr, 1128 INVALIDr, INVALIDr}, 1129 { CFAP_MEM_FAIL_ENf, CFAP_MEM_FAILf, NULL, 1130 INVALIDm, _SOC_PARITY_INFO_TYPE_GENERIC, 1131 INVALIDr, 1132 INVALIDr, INVALIDr, 1133 INVALIDr, INVALIDr}, 1134 { DEQ_RDEHDR_ERR_ENf, DEQ_RDEHDR_ERRf, NULL, 1135 INVALIDm, _SOC_PARITY_INFO_TYPE_MMU_PARITY, 1136 INVALIDr, 1137 DEQ_RDEHDRERRPTRr, INVALIDr, 1138 INVALIDr, INVALIDr}, 1139 { DEQ_PKTHDR0_ERR_ENf, DEQ_PKTHDR0_ERRf, NULL, 1140 MMU_CBPPKTHEADER0_MEM0m, _SOC_PARITY_INFO_TYPE_MMU_PARITY, 1141 INVALIDr, 1142 DEQ_PKTHDR0ERRPTRr, INVALIDr, 1143 INVALIDr, INVALIDr}, 1144 { DEQ0_NOT_IP_ERR_ENf, DEQ0_NOT_IP_ERRf, NULL, 1145 INVALIDm, _SOC_PARITY_INFO_TYPE_GENERIC, 1146 INVALIDr, 1147 INVALIDr, INVALIDr, 1148 INVALIDr, INVALIDr}, 1149 { DEQ0_CELLCRC_ERR_ENf, DEQ0_CELLCRC_ERRf, NULL, 1150 INVALIDm, _SOC_PARITY_INFO_TYPE_GENERIC, 1151 INVALIDr, 1152 INVALIDr, INVALIDr, 1153 INVALIDr, INVALIDr}, 1154 { START_BY_START_ERR_ENf, START_BY_START_ERRf, NULL, 1155 INVALIDm, _SOC_PARITY_INFO_TYPE_GENERIC, 1156 INVALIDr, 1157 INVALIDr, INVALIDr, 1158 INVALIDr, INVALIDr}, 1159 { MEM1_IPMC_TBL_PAR_ERR_ENf, MEM1_IPMC_TBL_PAR_ERRf, "MMU_IPMC_GROUP_TBL", 1160 INVALIDm, _SOC_PARITY_INFO_TYPE_MMUIPMC, 1161 INVALIDr, 1162 MEM1_IPMCGRP_TBL_PARITYERRORPTRr, MEM1_IPMCGRP_TBL_PARITYERROR_STATUSr, 1163 INVALIDr, INVALIDr}, 1164 { MEM1_VLAN_TBL_PAR_ERR_ENf, MEM1_VLAN_TBL_PAR_ERRf, NULL, 1165 MMU_IPMC_VLAN_TBLm, _SOC_PARITY_INFO_TYPE_MMU_PARITY, 1166 INVALIDr, 1167 MEM1_IPMCVLAN_TBL_PARITYERRORPTRr, MEM1_IPMCVLAN_TBL_PARITYERROR_STATUSr, 1168 INVALIDr, INVALIDr}, 1169 { TOQ0_PKTHDR1_PAR_ERR_ENf, TOQ0_PKTHDR1_PAR_ERRf, NULL, 1170 MMU_CBPPKTHEADER1_MEM0m, _SOC_PARITY_INFO_TYPE_MMU_PARITY, 1171 INVALIDr, 1172 TOQ_PKTHDR1ERRPTRr, INVALIDr, 1173 INVALIDr, INVALIDr}, 1174 { TOQ0_PKTLINK_PAR_ERR_ENf, TOQ0_PKTLINK_PAR_ERRf, NULL, 1175 MMU_PKTLINK0m, _SOC_PARITY_INFO_TYPE_MMU_PARITY, 1176 INVALIDr, 1177 TOQ_PKTLINKERRPTRr, INVALIDr, 1178 INVALIDr, INVALIDr}, 1179 { TOQ0_CELLLINK_PAR_ERR_ENf, TOQ0_CELLLINK_PAR_ERRf, NULL, 1180 MMU_CELLLINKm, _SOC_PARITY_INFO_TYPE_MMU_PARITY, 1181 INVALIDr, 1182 TOQ_CELLLINKERRPTRr, INVALIDr, 1183 INVALIDr, INVALIDr}, 1184 /* what memory is this for? */ 1185 { TOQ0_IPMC_TBL_PAR_ERR_ENf, TOQ0_IPMC_TBL_PAR_ERRf, NULL, 1186 INVALIDm, _SOC_PARITY_INFO_TYPE_GENERIC, 1187 INVALIDr, 1188 TOQ_IPMCGRPERRPTR0r, INVALIDr, 1189 INVALIDr, INVALIDr}, 1190 /* what memory is this for? */ 1191 { TOQ0_VLAN_TBL_PAR_ERR_ENf, TOQ0_VLAN_TBL_PAR_ERRf, NULL, 1192 INVALIDm, _SOC_PARITY_INFO_TYPE_GENERIC, 1193 INVALIDr, 1194 TOQ_IPMCVLANERRPTRr, INVALIDr, 1195 INVALIDr, INVALIDr}, 1196 /* what is this memory ? use EGRSHAPEPARITYERRORPTRr for status? */ 1197 { MTRO_PAR_ERR_ENf, MTRO_PAR_ERRf, NULL, 1198 INVALIDm, _SOC_PARITY_INFO_TYPE_MMUMTRO, 1199 INVALIDr, 1200 INVALIDr, INVALIDr, 1201 INVALIDr, INVALIDr}, 1202 { PFAP_PAR_ERR_ENf, PFAP_PAR_ERRf, NULL, 1203 MMU_PFAP_MEMm, _SOC_PARITY_INFO_TYPE_MMU_PARITY, 1204 INVALIDr, 1205 PFAPPARITYERRORPTRr, INVALIDr, 1206 INVALIDr, INVALIDr}, 1207 { PFAP_MEM_FAIL_ENf, PFAP_MEM_FAILf, NULL, 1208 MMU_PFAP_MEMm, _SOC_PARITY_INFO_TYPE_GENERIC, 1209 INVALIDr, 1210 INVALIDr, INVALIDr, 1211 INVALIDr, INVALIDr}, 1212 { WRED_PAR_ERR_ENf, WRED_PAR_ERRf, NULL, 1213 INVALIDm, _SOC_PARITY_INFO_TYPE_MMUWRED, 1214 INVALIDr, 1215 WRED_PARITY_ERROR_INFOr, WRED_PARITY_ERROR_BITMAPr, 1216 INVALIDr, INVALIDr}, 1217 { DEQ_PKTHDR2_ERR_ENf, DEQ_PKTHDR2_PAR_ERRf, NULL, 1218 MMU_CBPPKTHEADER2m, _SOC_PARITY_INFO_TYPE_MMU_PARITY, 1219 INVALIDr, 1220 DEQ_PKTHDR2ERRPTRr, INVALIDr, 1221 INVALIDr, INVALIDr}, 1222 /* what memory is this for? use E2EFC_PARITYERRORPTRr.PTRf for index */ 1223 { E2EFC_ERR_ENf, E2EFC_PAR_ERRf, NULL, 1224 INVALIDm, _SOC_PARITY_INFO_TYPE_GENERIC, 1225 INVALIDr, 1226 INVALIDr, INVALIDr, 1227 INVALIDr, INVALIDr}, 1228 { WAMU_ERR_ENf, WAMU_PAR_ERRf, NULL, 1229 INVALIDm, _SOC_PARITY_INFO_TYPE_GENERIC, 1230 INVALIDr, 1231 INVALIDr, INVALIDr, 1232 INVALIDr, INVALIDr}, 1233 { PQE_ERR_ENf, PQE_PAR_ERRf, NULL, 1234 INVALIDm, _SOC_PARITY_INFO_TYPE_GENERIC, 1235 INVALIDr, 1236 INVALIDr, INVALIDr, 1237 INVALIDr, INVALIDr}, 1238 { RDE_ERR_ENf, RDE_PAR_ERRf, NULL, 1239 INVALIDm, _SOC_PARITY_INFO_TYPE_GENERIC, 1240 INVALIDr, 1241 INVALIDr, INVALIDr, 1242 INVALIDr, INVALIDr}, 1243 { INVALIDf, INVALIDf}, /* table terminator */ 1244 }; 1245 1246 STATIC struct { 1247 uint32 cpi_bit; 1248 soc_block_t blocktype; 1249 soc_reg_t enable_reg; 1250 soc_reg_t status_reg; 1251 _soc_parity_info_t *info; 1252 }_soc_tr2_parity_group_info[] = { 1253 { 0x00001, SOC_BLK_MMU, MEM_FAIL_INT_ENr, MEM_FAIL_INT_STATr, _soc_tr2_mmu_parity_info}, 1254 { 0x00002, SOC_BLK_EPIPE, EP_INTR0_ENABLEr, EP_INTR0_STATUSr, _soc_tr2_ep0_parity_info}, 1255 { 0x00002, SOC_BLK_EPIPE, EP_INTR1_ENABLEr, EP_INTR1_STATUSr, _soc_tr2_ep1_parity_info}, 1256 { 0x00004, SOC_BLK_IPIPE, IP0_INTR_ENABLEr, IP0_INTR_STATUSr, _soc_tr2_ip0_parity_info}, 1257 { 0x00008, SOC_BLK_IPIPE, IP1_INTR_ENABLEr, IP1_INTR_STATUSr, _soc_tr2_ip1_parity_info}, 1258 { 0x00010, SOC_BLK_IPIPE, IP2_INTR_ENABLEr, IP2_INTR_STATUSr, _soc_tr2_ip2_parity_info}, 1259 { 0x00020, SOC_BLK_IPIPE, IP3_INTR_ENABLEr, IP3_INTR_STATUSr, _soc_tr2_ip3_parity_info}, 1260 { 0x00020, SOC_BLK_IPIPE, IP3_INTR_ENABLE_1r, IP3_INTR_STATUS_1r, _soc_tr2_ip3_1_parity_info}, 1261 { 0x00020, SOC_BLK_IPIPE, IP3_INTR_ENABLE_2r, IP3_INTR_STATUS_2r, _soc_tr2_ip3_2_parity_info}, 1262 /* { 0x00040, PCIE_REPLAY_PERR, }, */ 1263 { 0x00080, SOC_BLK_GPORT, GPORT_INTR_ENABLEr, GPORT_INTR_STATUSr, _soc_tr2_gp_parity_info}, /* x2 */ 1264 { 0x00200, SOC_BLK_XQPORT, XQPORT_INTR_ENABLEr, XQPORT_INTR_STATUSr, _soc_tr2_xqp_parity_info}, /* x6 */ 1265 { 0x08000, SOC_BLK_GXPORT, XPORT_INTR_ENABLEr, XPORT_INTR_STATUSr, _soc_tr2_xp_parity_info}, /* x4 */ 1266 { 0x80000, SOC_BLK_SPORT, SPORT_INTR_ENABLEr, SPORT_INTR_STATUSr, _soc_tr2_sp_parity_info}, 1267 { 0}, /* table terminator */ 1268 }; 1269 1270 /* MMU MTRO conversion structure*/ 1271 #define MMU_MTRO_MAX_GROUP 30 1272 #define MMU_MTRO_MAX_PORT_IN_GROUP 5 1273 #define SOC_TRIUMPH2_MEM_PARITY_INFO(unit, block_info_idx, field_enum) \ 1274 ((SOC_BLOCK2SCH(unit, block_info_idx) << SOC_ERROR_BLK_BP) \ 1275 | (field_enum & SOC_ERROR_FIELD_ENUM_MASK)) 1276 1277 STATIC struct { 1278 int num_port; 1279 int port_list[MMU_MTRO_MAX_PORT_IN_GROUP]; 1280 int base_queue; 1281 int numq; 1282 } _soc_tr2_mtro_group_info[MMU_MTRO_MAX_GROUP] = { 1283 {5, {1, 2, 3, 4, 5}, 0, 8}, 1284 {5, {6, 7, 8, 9, 10}, 0, 8}, 1285 {5, {11, 12, 13, 14, 15}, 0, 8}, 1286 {5, {16, 17, 18, 19, 20}, 0, 8}, 1287 {5, {21, 22, 23, 24, 25}, 0, 8}, 1288 {1, {26, -1, -1, -1, -1}, 0, 24}, 1289 {1, {27, -1, -1, -1, -1}, 0, 24}, 1290 {1, {28, -1, -1, -1, -1}, 0, 24}, 1291 {1, {29, -1, -1, -1, -1}, 0, 24}, 1292 {2, {30, 31, -1, -1, -1}, 0, 24}, 1293 {2, {32, 33, -1, -1, -1}, 0, 8}, 1294 {1, {34, -1, -1, -1, -1}, 0, 24}, 1295 {3, {35, 36, 37, -1, -1}, 0, 8}, 1296 {2, {38, 39, -1, -1, -1}, 0, 24}, 1297 {2, {40, 41, -1, -1, -1}, 0, 8}, 1298 {2, {42, 43, -1, -1, -1}, 0, 24}, 1299 {2, {44, 45, -1, -1, -1}, 0, 8}, 1300 {1, {46, -1, -1, -1, -1}, 0, 24}, 1301 {3, {47, 48, 49, -1, -1}, 0, 8}, 1302 {2, {50, 51, -1, -1, -1}, 0, 24}, 1303 {2, {52, 53, -1, -1, -1}, 0, 8}, 1304 {1, {54, -1, -1, -1, -1}, 0, 24}, 1305 {1, {0, -1, -1, -1, -1}, 0, 2}, 1306 {1, {1, -1, -1, -1, -1}, 8, 2}, 1307 {1, {2, -1, -1, -1, -1}, 8, 2}, 1308 {1, {3, -1, -1, -1, -1}, 8, 2}, 1309 {5, {4, 5, 6, 7, 8}, 8, 2}, 1310 {5, {9, 10, 11, 12, 13}, 8, 2}, 1311 {1, {14, -1, -1, -1, -1}, 8, 2}, 1312 {1, {REG_PORT_ANY, -1,-1,-1,-1}, 0, 48} 1313 }; 1314 1315 STATIC soc_triumph2_oam_handler_t oam_handler[SOC_MAX_NUM_DEVICES]; 1316 STATIC soc_triumph2_oam_ser_handler_t tr2_oam_ser_handler[SOC_MAX_NUM_DEVICES] = {NULL}; 1317 1318 static int _stat_error_fixed[SOC_MAX_NUM_DEVICES]; 1319 1320 #define _SOC_SER_REG 1 1321 #define _SOC_SER_MEM 0 1322 1323 typedef struct _ser_nack_reg_mem_s { 1324 int reg_mem; 1325 soc_reg_t reg; 1326 soc_mem_t mem; 1327 } _ser_nack_reg_mem_t; 1328 1329 static soc_ser_functions_t _tr2_ser_functions; 1330 static soc_oam_event_functions_t _tr2_oam_event_functions; 1331 1332 STATIC int 1333 _soc_triumph_parity_block_port(int unit, soc_block_t block, soc_port_t *port) 1334 { 1335 *port = SOC_BLOCK_PORT(unit, block); 1336 if ((*port != REG_PORT_ANY) && !SOC_PORT_VALID(unit, *port)) { 1337 return SOC_E_PORT; 1338 } 1339 1340 return SOC_E_NONE; 1341 } 1342 #define _SOC_TR2_OAM_GROUP_NUM 5 1343 1344 STATIC int 1345 _soc_triumph2_oam_enable_only(int unit, int enable) 1346 { 1347 int table; 1348 uint32 cpi_blk_bit, group_enable, addr, regval, cmic_enable = 0; 1349 _soc_parity_info_t *info; 1350 soc_reg_t group_reg; 1351 soc_field_t enable_field; 1352 soc_port_t block_port; 1353 soc_block_t blk; 1354 1355 info = _soc_tr2_parity_group_info[_SOC_TR2_OAM_GROUP_NUM].info; 1356 group_reg = _soc_tr2_parity_group_info[_SOC_TR2_OAM_GROUP_NUM].enable_reg; 1357 cpi_blk_bit = _soc_tr2_parity_group_info[_SOC_TR2_OAM_GROUP_NUM].cpi_bit; 1358 group_enable = 0; 1359 1360 SOC_BLOCK_ITER(unit, blk, 1361 _soc_tr2_parity_group_info[_SOC_TR2_OAM_GROUP_NUM].blocktype) { 1362 if (_soc_triumph_parity_block_port(unit, blk, &block_port) < 0) { 1363 cpi_blk_bit <<= 1; 1364 continue; 1365 } 1366 1367 /* loop through each table in the group */ 1368 for (table = 0; info[table].enable_field != INVALIDf; table++) { 1369 if (info[table].type == _SOC_PARITY_INFO_TYPE_OAM) { 1370 1371 enable_field = info[table].enable_field; 1372 } else { 1373 enable_field = INVALIDf; 1374 } 1375 if (enable_field != INVALIDf) { 1376 soc_reg_field_set(unit, group_reg, &group_enable, 1377 enable_field, enable ? 1 : 0); 1378 } 1379 } /* loop through each table in the group */ 1380 if (!SOC_REG_IS_VALID(unit, group_reg)) { 1381 cpi_blk_bit <<= 1; 1382 continue; 1383 } 1384 addr = soc_reg_addr(unit, group_reg, block_port, 0); 1385 SOC_IF_ERROR_RETURN(soc_reg32_write(unit, addr, group_enable)); 1386 cmic_enable |= cpi_blk_bit; 1387 cpi_blk_bit <<= 1; 1388 } 1389 /* coverity[result_independent_of_operands] */ 1390 SOC_IF_ERROR_RETURN(WRITE_CMIC_CHIP_PARITY_INTR_ENABLEr(unit, 1391 cmic_enable)); 1392 SOC_IF_ERROR_RETURN(READ_MEM_FAIL_INT_STATr(unit, ®val)); 1393 soc_intr_enable(unit, IRQ_MEM_FAIL); 1394 return SOC_E_NONE; 1395 } 1396 1397 STATIC int 1398 _soc_triumph2_parity_enable(int unit, int enable) 1399 { 1400 int group, table; 1401 uint32 addr, group_enable, regval, misc_cfg, 1402 cmic_enable = 0, cpi_blk_bit; 1403 _soc_parity_info_t *info; 1404 soc_reg_t group_reg, reg; 1405 soc_port_t block_port; 1406 soc_field_t enable_field; 1407 soc_block_t blk; 1408 1409 /* loop through each group */ 1410 for (group = 0; _soc_tr2_parity_group_info[group].cpi_bit; group++) { 1411 info = _soc_tr2_parity_group_info[group].info; 1412 group_reg = _soc_tr2_parity_group_info[group].enable_reg; 1413 group_enable = 0; 1414 1415 cpi_blk_bit = _soc_tr2_parity_group_info[group].cpi_bit; 1416 1417 SOC_BLOCK_ITER(unit, blk, 1418 _soc_tr2_parity_group_info[group].blocktype) { 1419 if (_soc_triumph_parity_block_port(unit, blk, &block_port) < 0) { 1420 cpi_blk_bit <<= 1; 1421 continue; 1422 } 1423 1424 /* loop through each table in the group */ 1425 for (table = 0; info[table].enable_field != INVALIDf; table++) { 1426 /* handle different parity error reporting style */ 1427 switch (info[table].type) { 1428 case _SOC_PARITY_INFO_TYPE_GENERIC: 1429 case _SOC_PARITY_INFO_TYPE_MMU_PARITY: 1430 case _SOC_PARITY_INFO_TYPE_MMUIPMC: 1431 case _SOC_PARITY_INFO_TYPE_MMUWRED: 1432 case _SOC_PARITY_INFO_TYPE_MMUMTRO: 1433 case _SOC_PARITY_INFO_TYPE_OAM: 1434 enable_field = info[table].enable_field; 1435 break; 1436 case _SOC_PARITY_INFO_TYPE_SINGLE_PARITY: 1437 case _SOC_PARITY_INFO_TYPE_SINGLE_ECC: 1438 case _SOC_PARITY_INFO_TYPE_SINGLE_COUNTER: 1439 case _SOC_PARITY_INFO_TYPE_DUAL_PARITY: 1440 reg = info[table].control_reg; 1441 if (!SOC_REG_IS_VALID(unit, reg)) { 1442 continue; 1443 } 1444 addr = soc_reg_addr(unit, reg, block_port, 0); 1445 SOC_IF_ERROR_RETURN(soc_reg32_read(unit, addr, ®val)); 1446 soc_reg_field_set(unit, reg, ®val, 1447 info[table].enable_field, 1448 enable ? 1 : 0); 1449 SOC_IF_ERROR_RETURN(soc_reg32_write(unit, addr, regval)); 1450 enable_field = info[table].error_field; 1451 break; 1452 default: 1453 enable_field = INVALIDf; 1454 break; 1455 } /* handle different parity error reporting style */ 1456 if (enable_field != INVALIDf) { 1457 soc_reg_field_set(unit, group_reg, &group_enable, 1458 enable_field, enable ? 1 : 0); 1459 } 1460 } /* loop through each table in the group */ 1461 if (!SOC_REG_IS_VALID(unit, group_reg)) { 1462 cpi_blk_bit <<= 1; 1463 continue; 1464 } 1465 addr = soc_reg_addr(unit, group_reg, block_port, 0); 1466 SOC_IF_ERROR_RETURN(soc_reg32_write(unit, addr, group_enable)); 1467 cmic_enable |= cpi_blk_bit; 1468 cpi_blk_bit <<= 1; 1469 } 1470 } /* loop through each group */ 1471 1472 /* Special extras for debug */ 1473 SOC_IF_ERROR_RETURN(WRITE_ERB_INTR_ENABLEr(unit, 0x1f)); 1474 SOC_IF_ERROR_RETURN(WRITE_IESMIF_INTR_ENABLEr(unit, 0x7fff)); 1475 1476 SOC_IF_ERROR_RETURN(WRITE_EP_DATAPATH_INTR_ENABLEr(unit, 0xffff)); 1477 /* coverity[result_independent_of_operands] */ 1478 SOC_IF_ERROR_RETURN(WRITE_CMIC_CHIP_PARITY_INTR_ENABLEr(unit, 1479 cmic_enable)); 1480 1481 /* MMU enables */ 1482 SOC_IF_ERROR_RETURN(READ_MISCCONFIGr(unit, &misc_cfg)); 1483 soc_reg_field_set(unit, MISCCONFIGr, &misc_cfg, PARITY_STAT_CLEARf, 1); 1484 SOC_IF_ERROR_RETURN(WRITE_MISCCONFIGr(unit, misc_cfg)); 1485 1486 soc_reg_field_set(unit, MISCCONFIGr, &misc_cfg, PARITY_CHK_ENf, 1); 1487 soc_reg_field_set(unit, MISCCONFIGr, &misc_cfg, PARITY_GEN_ENf, 1); 1488 soc_reg_field_set(unit, MISCCONFIGr, &misc_cfg, PARITY_STAT_CLEARf, 0); 1489 SOC_IF_ERROR_RETURN(WRITE_MISCCONFIGr(unit, misc_cfg)); 1490 1491 SOC_IF_ERROR_RETURN(READ_MEM_FAIL_INT_STATr(unit, ®val)); 1492 soc_intr_enable(unit, IRQ_MEM_FAIL); 1493 1494 return SOC_E_NONE; 1495 } 1496 1497 int 1498 _soc_triumph2_mem_parity_control(int unit, soc_mem_t mem, 1499 int copyno, int enable) 1500 { 1501 int group, table; 1502 uint32 cpi_blk_bit, misc_cfg; 1503 _soc_parity_info_t *info; 1504 soc_reg_t group_reg, reg; 1505 soc_port_t block_port; 1506 soc_field_t enable_field; 1507 soc_block_t blk; 1508 1509 if (!soc_property_get(unit, spn_PARITY_ENABLE, TRUE)) { 1510 /* Parity checking is not enabled, nothing to do */ 1511 return SOC_E_NONE; 1512 } 1513 1514 /* Convert component/aggregate memories to the table for which 1515 * the parity registers correspond. */ 1516 switch(mem) { 1517 case VLAN_SUBNETm: 1518 mem = VLAN_SUBNET_DATA_ONLYm; /* Should be VLAN_SUBNET? */ 1519 break; 1520 case L2_ENTRY_ONLYm: 1521 mem = L2Xm; 1522 break; 1523 case L2_USER_ENTRY_ONLYm: 1524 case L2_USER_ENTRY_DATA_ONLYm: 1525 mem = L2_USER_ENTRYm; 1526 break; 1527 case L3_DEFIPm: 1528 mem = L3_DEFIP_DATA_ONLYm; 1529 break; 1530 case L3_DEFIP_128m: 1531 mem = L3_DEFIP_128_DATA_ONLYm; 1532 break; 1533 case EGR_IP_TUNNEL_IPV6m: 1534 case EGR_IP_TUNNEL_MPLSm: 1535 mem = EGR_IP_TUNNELm; 1536 break; 1537 default: 1538 /* Do nothing, keep memory as provided */ 1539 break; 1540 } 1541 1542 /* loop through each group */ 1543 for (group = 0; _soc_tr2_parity_group_info[group].cpi_bit; group++) { 1544 info = _soc_tr2_parity_group_info[group].info; 1545 group_reg = _soc_tr2_parity_group_info[group].enable_reg; 1546 cpi_blk_bit = _soc_tr2_parity_group_info[group].cpi_bit; 1547 1548 SOC_BLOCK_ITER(unit, blk, 1549 _soc_tr2_parity_group_info[group].blocktype) { 1550 if (_soc_triumph_parity_block_port(unit, blk, &block_port) < 0) { 1551 cpi_blk_bit <<= 1; 1552 continue; 1553 } 1554 if ((copyno != MEM_BLOCK_ANY) && (blk != copyno)) { 1555 cpi_blk_bit <<= 1; 1556 continue; 1557 } 1558 1559 /* loop through each table in the group */ 1560 for (table = 0; info[table].enable_field != INVALIDf; table++) { 1561 if (mem != info[table].mem) { 1562 continue; 1563 } 1564 1565 /* handle different parity error reporting style */ 1566 switch (info[table].type) { 1567 case _SOC_PARITY_INFO_TYPE_GENERIC: 1568 case _SOC_PARITY_INFO_TYPE_MMU_PARITY: 1569 case _SOC_PARITY_INFO_TYPE_MMUIPMC: 1570 case _SOC_PARITY_INFO_TYPE_MMUWRED: 1571 case _SOC_PARITY_INFO_TYPE_MMUMTRO: 1572 enable_field = info[table].enable_field; 1573 SOC_IF_ERROR_RETURN 1574 (soc_reg_field32_modify(unit, group_reg, block_port, 1575 enable_field, 1576 enable ? 1 : 0)); 1577 break; 1578 case _SOC_PARITY_INFO_TYPE_SINGLE_PARITY: 1579 case _SOC_PARITY_INFO_TYPE_SINGLE_ECC: 1580 case _SOC_PARITY_INFO_TYPE_SINGLE_COUNTER: 1581 case _SOC_PARITY_INFO_TYPE_DUAL_PARITY: 1582 reg = info[table].control_reg; 1583 if (!SOC_REG_IS_VALID(unit, reg)) { 1584 return SOC_E_NONE; 1585 } 1586 SOC_IF_ERROR_RETURN 1587 (soc_reg_field32_modify(unit, reg, block_port, 1588 info[table].enable_field, 1589 enable ? 1 : 0)); 1590 break; 1591 default: 1592 /* coverity[assigned_value] */ 1593 enable_field = INVALIDf; 1594 break; 1595 } /* handle different parity error reporting style */ 1596 } /* loop through each table in the group */ 1597 cpi_blk_bit <<= 1; 1598 } 1599 } /* loop through each group */ 1600 1601 /* MMU controls */ 1602 if (enable) { 1603 SOC_IF_ERROR_RETURN(READ_MISCCONFIGr(unit, &misc_cfg)); 1604 soc_reg_field_set(unit, MISCCONFIGr, &misc_cfg, 1605 PARITY_STAT_CLEARf, 1); 1606 SOC_IF_ERROR_RETURN(WRITE_MISCCONFIGr(unit, misc_cfg)); 1607 1608 soc_reg_field_set(unit, MISCCONFIGr, &misc_cfg, PARITY_CHK_ENf, 1); 1609 soc_reg_field_set(unit, MISCCONFIGr, &misc_cfg, PARITY_GEN_ENf, 1); 1610 soc_reg_field_set(unit, MISCCONFIGr, &misc_cfg, 1611 PARITY_STAT_CLEARf, 0); 1612 soc_reg_field_set(unit, MISCCONFIGr, &misc_cfg, METERING_CLK_ENf, 1); 1613 SOC_IF_ERROR_RETURN(WRITE_MISCCONFIGr(unit, misc_cfg)); 1614 } else { 1615 SOC_IF_ERROR_RETURN(READ_MISCCONFIGr(unit, &misc_cfg)); 1616 soc_reg_field_set(unit, MISCCONFIGr, &misc_cfg, PARITY_CHK_ENf, 0); 1617 soc_reg_field_set(unit, MISCCONFIGr, &misc_cfg, PARITY_GEN_ENf, 0); 1618 soc_reg_field_set(unit, MISCCONFIGr, &misc_cfg, METERING_CLK_ENf, 0); 1619 SOC_IF_ERROR_RETURN(WRITE_MISCCONFIGr(unit, misc_cfg)); 1620 } 1621 1622 return SOC_E_NONE; 1623 } 1624 1625 STATIC int 1626 _soc_triumph2_process_single_parity_error(int unit, int group, 1627 soc_port_t block_port, int table, 1628 int schan, char *msg, soc_block_t blk) 1629 { 1630 _soc_parity_info_t *info; 1631 soc_reg_t status_reg; 1632 uint32 addr, reg_val; 1633 int index, multiple, error; 1634 _soc_ser_correct_info_t spci = {0}; 1635 1636 info = _soc_tr2_parity_group_info[group].info; 1637 1638 status_reg = schan ? info[table].nack_status0_reg : 1639 info[table].intr_status0_reg; 1640 if (status_reg == INVALIDr) { 1641 return SOC_E_INTERNAL; 1642 } 1643 addr = soc_reg_addr(unit, status_reg, block_port, 0); 1644 SOC_IF_ERROR_RETURN(soc_reg32_read(unit, addr, ®_val)); 1645 index = soc_reg_field_get(unit, status_reg, reg_val, ENTRY_IDXf); 1646 multiple = soc_reg_field_get(unit, status_reg, reg_val, MULTIPLE_ERRf); 1647 error = soc_reg_field_get(unit, status_reg, reg_val, PARITY_ERRf); 1648 1649 if (error) { 1650 LOG_ERROR(BSL_LS_SOC_COMMON, 1651 (BSL_META_U(unit, 1652 "unit %d %s entry %d parity error\n"), 1653 unit, msg, index)); 1654 if (multiple) { 1655 LOG_ERROR(BSL_LS_SOC_COMMON, 1656 (BSL_META_U(unit, 1657 "unit %d %s has multiple parity errors\n"), 1658 unit, msg)); 1659 } 1660 } else { 1661 LOG_ERROR(BSL_LS_SOC_COMMON, 1662 (BSL_META_U(unit, 1663 "unit %d %s: parity hardware inconsistency\n"), 1664 unit, msg)); 1665 } 1666 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 1667 SOC_SWITCH_EVENT_DATA_ERROR_PARITY, info[table].mem, 1668 info[table].error_field); 1669 1670 if (info[table].mem != INVALIDm) { 1671 spci.flags = SOC_SER_SRC_MEM | SOC_SER_REG_MEM_KNOWN; 1672 spci.reg = INVALIDr; 1673 spci.mem = info[table].mem; 1674 spci.blk_type = blk; 1675 spci.index = index; 1676 (void)soc_ser_correction(unit, &spci); 1677 } 1678 1679 /* Clear parity status */ 1680 SOC_IF_ERROR_RETURN(soc_reg32_write(unit, addr, 0)); 1681 return SOC_E_NONE; 1682 } 1683 1684 STATIC int 1685 _soc_triumph2_process_single_ecc_error(int unit, int group, 1686 soc_port_t block_port, int table, 1687 int schan, char *msg, soc_block_t blk) 1688 { 1689 _soc_parity_info_t *info; 1690 soc_reg_t status_reg; 1691 uint32 addr, reg_val; 1692 int index, double_bit, multiple, error; 1693 _soc_ser_correct_info_t spci = {0}; 1694 1695 info = _soc_tr2_parity_group_info[group].info; 1696 1697 status_reg = schan ? info[table].nack_status0_reg : 1698 info[table].intr_status0_reg; 1699 if (status_reg == INVALIDr) { 1700 return SOC_E_INTERNAL; 1701 } 1702 addr = soc_reg_addr(unit, status_reg, block_port, 0); 1703 SOC_IF_ERROR_RETURN(soc_reg32_read(unit, addr, ®_val)); 1704 index = soc_reg_field_get(unit, status_reg, reg_val, ENTRY_IDXf); 1705 double_bit = soc_reg_field_get(unit, status_reg, 1706 reg_val, DOUBLE_BIT_ERRf); 1707 multiple = soc_reg_field_get(unit, status_reg, reg_val, MULTIPLE_ERRf); 1708 error = soc_reg_field_get(unit, status_reg, reg_val, ECC_ERRf); 1709 1710 if (error) { 1711 LOG_ERROR(BSL_LS_SOC_COMMON, 1712 (BSL_META_U(unit, 1713 "unit %d %s entry %d %s ECC error\n"), 1714 unit, msg, index, double_bit ? "double-bit" : "")); 1715 if (multiple) { 1716 LOG_ERROR(BSL_LS_SOC_COMMON, 1717 (BSL_META_U(unit, 1718 "unit %d %s has multiple ECC errors\n"), 1719 unit, msg)); 1720 } 1721 } else { 1722 LOG_ERROR(BSL_LS_SOC_COMMON, 1723 (BSL_META_U(unit, 1724 "unit %d %s: parity hardware inconsistency\n"), 1725 unit, msg)); 1726 } 1727 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 1728 SOC_SWITCH_EVENT_DATA_ERROR_ECC, info[table].mem, 1729 info[table].error_field); 1730 1731 if (info[table].mem != INVALIDm) { 1732 if (double_bit) { 1733 spci.double_bit = 1; 1734 } 1735 spci.flags = SOC_SER_SRC_MEM | SOC_SER_REG_MEM_KNOWN; 1736 spci.reg = INVALIDr; 1737 spci.mem = info[table].mem; 1738 spci.blk_type = blk; 1739 spci.index = index; 1740 spci.parity_type = SOC_PARITY_TYPE_ECC; 1741 (void)soc_ser_correction(unit, &spci); 1742 } 1743 1744 /* Clear parity status */ 1745 SOC_IF_ERROR_RETURN(soc_reg32_write(unit, addr, 0)); 1746 return SOC_E_NONE; 1747 } 1748 1749 #define _SOC_TR2_ING_CTR_ERR_NUM 0x1C 1750 char *_soc_triumph2_ingress_counter_error_map[_SOC_TR2_ING_CTR_ERR_NUM] = { 1751 "RIPD4", /* 0x00 */ 1752 "RIPC4", /* 0x01 */ 1753 "RIPHE4", /* 0x02 */ 1754 "IMRP4", /* 0x03 */ 1755 "RIPD6", /* 0x04 */ 1756 "RIPC6", /* 0x05 */ 1757 "RIPHE6", /* 0x06 */ 1758 "IMRP6", /* 0x07 */ 1759 "RDISC", /* 0x08 */ 1760 "RUC", /* 0x09 */ 1761 "RPORTD", /* 0x0A */ 1762 "RDBGC0", /* 0x0B */ 1763 "RDBGC1", /* 0x0C */ 1764 "RDBGC2", /* 0x0D */ 1765 "RDBGC3", /* 0x0E */ 1766 "RDBGC4", /* 0x0F */ 1767 NULL, /* 0x10, N/A */ 1768 "IUNHGI", /* 0x11 */ 1769 "ICTRL", /* 0x12 */ 1770 "IBCAST", /* 0x13 */ 1771 "ILTOMC", /* 0x14 */ 1772 "IIPMC", /* 0x15 */ 1773 "IUNKOPC", /* 0x16 */ 1774 NULL, /* 0x17, N/A */ 1775 "RDBGC5", /* 0x18 */ 1776 "RDBGC6", /* 0x19 */ 1777 "RDBGC7", /* 0x1A */ 1778 "RDBGC8", /* 0x1B */ 1779 /* num */ /* 0x1C */ 1780 }; 1781 1782 #define _SOC_TR2_EGR_CTR_ERR_NUM 0xC 1783 char *_soc_triumph2_egress_counter_error_map[_SOC_TR2_EGR_CTR_ERR_NUM] = { 1784 "TDBGC0", /* 0x00 */ 1785 "TDBGC1", /* 0x01 */ 1786 "TDBGC2", /* 0x02 */ 1787 "TDBGC3", /* 0x03 */ 1788 "TDBGC4", /* 0x04 */ 1789 "TDBGC5", /* 0x05 */ 1790 "TDBGC6", /* 0x06 */ 1791 "TDBGC7", /* 0x07 */ 1792 "TDBGC8", /* 0x08 */ 1793 "TDBGC9", /* 0x09 */ 1794 "TDBGC10", /* 0x0A */ 1795 "TDBGC11", /* 0x0B */ 1796 /* num */ /* 0x0C */ 1797 }; 1798 1799 STATIC int 1800 _soc_triumph2_process_single_counter_error(int unit, int group, 1801 soc_port_t block_port, int table, 1802 int schan, char *msg, soc_block_t blk) 1803 { 1804 soc_cmap_t *cmap; 1805 _soc_parity_info_t *info; 1806 soc_reg_t status_reg, counter_reg; 1807 soc_port_t error_port; 1808 uint32 addr, reg_val; 1809 int counter_idx, multiple; 1810 char *ctr_str = NULL; 1811 _soc_ser_correct_info_t spci = {0}; 1812 1813 info = _soc_tr2_parity_group_info[group].info; 1814 1815 status_reg = schan ? info[table].nack_status0_reg : 1816 info[table].intr_status0_reg; 1817 if (status_reg == INVALIDr) { 1818 return SOC_E_INTERNAL; 1819 } 1820 addr = soc_reg_addr(unit, status_reg, block_port, 0); 1821 SOC_IF_ERROR_RETURN(soc_reg32_read(unit, addr, ®_val)); 1822 error_port = soc_reg_field_get(unit, status_reg, reg_val, PORT_IDXf); 1823 counter_idx = soc_reg_field_get(unit, status_reg, 1824 reg_val, COUNTER_IDXf); 1825 multiple = soc_reg_field_get(unit, status_reg, reg_val, MULTIPLE_ERRf); 1826 1827 if (soc_reg_field_get(unit, status_reg, reg_val, PARITY_ERRf)) { 1828 if (info[table].control_reg != EDATABUF_PARITY_CONTROLr) { /*ingress */ 1829 if (counter_idx < _SOC_TR2_ING_CTR_ERR_NUM) { 1830 ctr_str = 1831 _soc_triumph2_ingress_counter_error_map[counter_idx]; 1832 } 1833 } else { /* egress */ 1834 if (counter_idx < _SOC_TR2_EGR_CTR_ERR_NUM) { 1835 ctr_str = 1836 _soc_triumph2_egress_counter_error_map[counter_idx]; 1837 } 1838 } 1839 if (ctr_str != NULL) { 1840 cmap = soc_port_cmap_get(unit, error_port); 1841 counter_reg = cmap->cmap_base[counter_idx].reg; 1842 if (SOC_REG_IS_VALID(unit, counter_reg)) { 1843 LOG_ERROR(BSL_LS_SOC_COMMON, 1844 (BSL_META_U(unit, 1845 "unit %d %s port %d %s parity error\n"), 1846 unit, msg, error_port, ctr_str)); 1847 if (multiple) { 1848 LOG_ERROR(BSL_LS_SOC_COMMON, 1849 (BSL_META_U(unit, 1850 "unit %d %s has multiple parity errors\n"), 1851 unit, msg)); 1852 } 1853 spci.flags = SOC_SER_SRC_REG | SOC_SER_REG_MEM_KNOWN; 1854 spci.reg = counter_reg; 1855 spci.mem = INVALIDm; 1856 spci.blk_type = blk; 1857 spci.port = error_port; 1858 (void)soc_ser_correction(unit, &spci); 1859 _stat_error_fixed[unit]++; 1860 } else { 1861 LOG_ERROR(BSL_LS_SOC_COMMON, 1862 (BSL_META_U(unit, 1863 "unit %d %s: parity hardware inconsistency\n"), 1864 unit, msg)); 1865 } 1866 } else { 1867 LOG_ERROR(BSL_LS_SOC_COMMON, 1868 (BSL_META_U(unit, 1869 "unit %d %s: parity hardware counter index invalid\n"), 1870 unit, msg)); 1871 } 1872 } else if (!schan) { 1873 LOG_ERROR(BSL_LS_SOC_COMMON, 1874 (BSL_META_U(unit, 1875 "unit %d %s: parity hardware inconsistency\n"), 1876 unit, msg)); 1877 } 1878 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 1879 SOC_SWITCH_EVENT_DATA_ERROR_PARITY, info[table].mem, 1880 info[table].error_field); 1881 1882 /* Clear parity status */ 1883 SOC_IF_ERROR_RETURN(soc_reg32_write(unit, addr, 0)); 1884 return SOC_E_NONE; 1885 } 1886 1887 STATIC int 1888 _soc_triumph2_process_dual_parity_error(int unit, int group, 1889 soc_port_t block_port, int table, 1890 int schan, char *msg, soc_block_t blk) 1891 { 1892 _soc_parity_info_t *info; 1893 soc_reg_t status_reg; 1894 uint32 addr, reg_val, bitmap; 1895 int index, bucket_index, multiple, ix, bits, size; 1896 _soc_ser_correct_info_t spci; 1897 1898 info = _soc_tr2_parity_group_info[group].info; 1899 1900 for (ix = 0; ix < 2; ix ++) { 1901 if (ix == 1) { 1902 status_reg = schan ? info[table].nack_status1_reg : 1903 info[table].intr_status1_reg; 1904 } else { 1905 status_reg = schan ? info[table].nack_status0_reg : 1906 info[table].intr_status0_reg; 1907 } 1908 1909 if (status_reg == INVALIDr) { 1910 continue; 1911 } 1912 1913 addr = soc_reg_addr(unit, status_reg, block_port, 0); 1914 SOC_IF_ERROR_RETURN(soc_reg32_read(unit, addr, ®_val)); 1915 bucket_index = 1916 soc_reg_field_get(unit, status_reg, reg_val, BUCKET_IDXf); 1917 multiple = 1918 soc_reg_field_get(unit, status_reg, reg_val, MULTIPLE_ERRf); 1919 bitmap = 1920 soc_reg_field_get(unit, status_reg, reg_val, PARITY_ERR_BMf); 1921 size = soc_reg_field_length(unit, status_reg, PARITY_ERR_BMf); 1922 1923 if (bitmap != 0) { 1924 for (bits = 0; bits < size; bits++) { 1925 if (bitmap & (1 << bits)) { 1926 index = 1927 bucket_index * size * 2 + bits + (ix * size); 1928 LOG_ERROR(BSL_LS_SOC_COMMON, 1929 (BSL_META_U(unit, 1930 "unit %d %s entry %d parity error\n"), 1931 unit, msg, index)); 1932 sal_memset(&spci, 0, sizeof(spci)); 1933 spci.flags = SOC_SER_SRC_MEM | SOC_SER_REG_MEM_KNOWN; 1934 spci.reg = INVALIDr; 1935 spci.mem = info[table].mem; 1936 spci.blk_type = blk; 1937 spci.index = index; 1938 (void)soc_ser_correction(unit, &spci); 1939 } 1940 } 1941 1942 if (multiple) { 1943 LOG_ERROR(BSL_LS_SOC_COMMON, 1944 (BSL_META_U(unit, 1945 "unit %d %s has multiple parity errors\n"), 1946 unit, msg)); 1947 } 1948 1949 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 1950 SOC_SWITCH_EVENT_DATA_ERROR_PARITY, info[table].mem, 1951 info[table].error_field); 1952 } 1953 1954 /* Clear parity status */ 1955 SOC_IF_ERROR_RETURN(soc_reg32_write(unit, addr, 0)); 1956 } 1957 1958 return SOC_E_NONE; 1959 } 1960 1961 STATIC int 1962 _soc_triumph2_parity_mmu_clear(int unit, soc_field_t status_field) 1963 { 1964 uint32 rval; 1965 SOC_IF_ERROR_RETURN 1966 (READ_MEM_FAIL_INT_STATr(unit, &rval)); 1967 if (soc_reg_field_valid(unit, MEM_FAIL_INT_STATr, status_field)) { 1968 soc_reg_field_set(unit, MEM_FAIL_INT_STATr, &rval, status_field, 0); 1969 } else { 1970 return SOC_E_INTERNAL; 1971 } 1972 SOC_IF_ERROR_RETURN 1973 (WRITE_MEM_FAIL_INT_STATr(unit, rval)); 1974 SOC_IF_ERROR_RETURN(READ_MISCCONFIGr(unit, &rval)); 1975 soc_reg_field_set(unit, MISCCONFIGr, &rval, PARITY_STAT_CLEARf, 1); 1976 SOC_IF_ERROR_RETURN(WRITE_MISCCONFIGr(unit, rval)); 1977 SOC_IF_ERROR_RETURN(READ_MISCCONFIGr(unit, &rval)); 1978 soc_reg_field_set(unit, MISCCONFIGr, &rval, PARITY_STAT_CLEARf, 0); 1979 SOC_IF_ERROR_RETURN(WRITE_MISCCONFIGr(unit, rval)); 1980 return SOC_E_NONE; 1981 } 1982 1983 STATIC int 1984 _soc_triumph2_process_mmu_parity_error(int unit, int group, 1985 soc_port_t block_port, int table, 1986 char *msg) 1987 { 1988 _soc_parity_info_t *info; 1989 soc_reg_t status_reg, index_reg; 1990 uint32 addr, reg_val; 1991 int index; 1992 1993 info = _soc_tr2_parity_group_info[group].info; 1994 1995 status_reg = info[table].intr_status1_reg; 1996 index_reg = info[table].intr_status0_reg; 1997 if (index_reg == INVALIDr) { 1998 LOG_ERROR(BSL_LS_SOC_COMMON, 1999 (BSL_META_U(unit, 2000 "unit %d %s parity error\n"), 2001 unit, msg)); 2002 return SOC_E_NONE; 2003 } 2004 if (status_reg != INVALIDr) { 2005 addr = soc_reg_addr(unit, status_reg, block_port, 0); 2006 SOC_IF_ERROR_RETURN(soc_reg32_read(unit, addr, ®_val)); 2007 if (reg_val == 0) { 2008 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 2009 SOC_SWITCH_EVENT_DATA_ERROR_PARITY, 2010 info[table].mem, info[table].error_field); 2011 LOG_ERROR(BSL_LS_SOC_COMMON, 2012 (BSL_META_U(unit, 2013 "unit %d %s: parity hardware inconsistency\n"), 2014 unit, msg)); 2015 return SOC_E_NONE; 2016 } 2017 } 2018 addr = soc_reg_addr(unit, index_reg, block_port, 0); 2019 SOC_IF_ERROR_RETURN(soc_reg32_read(unit, addr, ®_val)); 2020 index = reg_val; 2021 2022 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 2023 SOC_SWITCH_EVENT_DATA_ERROR_PARITY, info[table].mem, 2024 info[table].error_field); 2025 LOG_ERROR(BSL_LS_SOC_COMMON, 2026 (BSL_META_U(unit, 2027 "unit %d %s entry %d parity error\n"), 2028 unit, msg, index)); 2029 /* update soc stats for some cases */ 2030 if (info[table].error_field == CCP_PAR_ERRf) { 2031 SOC_CONTROL(unit)->stat.err_cpcrc++; 2032 } else if (info[table].error_field == CFAP_PAR_ERRf) { 2033 SOC_CONTROL(unit)->stat.err_cfap++; 2034 } 2035 if (info[table].mem == MMU_IPMC_VLAN_TBLm) { 2036 _soc_ser_correct_info_t spci; 2037 uint32 rval = 0; 2038 memset(&spci, 0, sizeof(_soc_ser_correct_info_t)); 2039 spci.flags = SOC_SER_SRC_MEM | SOC_SER_REG_MEM_KNOWN; 2040 spci.reg = INVALIDr; 2041 spci.mem = info[table].mem; 2042 spci.blk_type = SOC_BLK_MMU; 2043 spci.index = index; 2044 2045 SOC_IF_ERROR_RETURN(READ_MISCCONFIGr(unit, &rval)); 2046 soc_reg_field_set(unit, MISCCONFIGr, &rval, PARITY_CHK_ENf, 0); 2047 SOC_IF_ERROR_RETURN(WRITE_MISCCONFIGr(unit, rval)); 2048 2049 (void)soc_ser_correction(unit, &spci); 2050 SOC_IF_ERROR_RETURN(_soc_triumph2_parity_mmu_clear(unit, MEM1_VLAN_TBL_PAR_ERRf)); 2051 2052 SOC_IF_ERROR_RETURN(READ_MISCCONFIGr(unit, &rval)); 2053 soc_reg_field_set(unit, MISCCONFIGr, &rval, PARITY_CHK_ENf, 1); 2054 SOC_IF_ERROR_RETURN(WRITE_MISCCONFIGr(unit, rval)); 2055 } 2056 2057 return SOC_E_NONE; 2058 } 2059 2060 STATIC int 2061 _soc_triumph2_mtro_mmu_port_index_get(int instance_num, int ptr, 2062 int *port, int *queue) 2063 { 2064 int num_port, numq, base_queue, port_index; 2065 2066 /* Check if instance_num is valid */ 2067 if ((instance_num < 0) || 2068 (instance_num >= MMU_MTRO_MAX_GROUP)) { 2069 return SOC_E_INTERNAL; 2070 } 2071 2072 num_port = _soc_tr2_mtro_group_info[instance_num].num_port; 2073 numq = _soc_tr2_mtro_group_info[instance_num].numq; 2074 base_queue = _soc_tr2_mtro_group_info[instance_num].base_queue; 2075 2076 /* Check if ptr is valid */ 2077 if ((ptr < 0) || (ptr >= (num_port * numq))) { 2078 return SOC_E_INTERNAL; 2079 } 2080 2081 port_index = ptr / numq; 2082 *port = _soc_tr2_mtro_group_info[instance_num].port_list[port_index]; 2083 *queue = base_queue + ptr % numq; 2084 2085 return SOC_E_NONE; 2086 } 2087 2088 STATIC int 2089 _soc_triumph2_parity_process_mmumtro(int unit, _soc_parity_info_t *info, 2090 soc_block_t block) 2091 { 2092 static soc_reg_t mtro_regs[] = { 2093 MINBUCKETCONFIG_64r, 2094 MINBUCKETr, 2095 MAXBUCKETCONFIG_64r, 2096 MAXBUCKETr 2097 }; 2098 static soc_reg_t cpu_mtro_regs[] = { 2099 CPUMAXBUCKETCONFIG_64r, 2100 CPUMAXBUCKETr 2101 }; 2102 uint32 i, rval, status, val, minfo; 2103 _soc_ser_correct_info_t spci; 2104 int rv, port, index, instance_num, ptr; 2105 2106 memset(&spci, 0, sizeof(_soc_ser_correct_info_t)); 2107 spci.flags = SOC_SER_SRC_REG | SOC_SER_REG_MEM_KNOWN; 2108 spci.mem = INVALIDm; 2109 spci.blk_type = SOC_BLK_MMU; 2110 SOC_IF_ERROR_RETURN(READ_MEM_FAIL_INT_STATr(unit, &status)); 2111 if (!soc_reg_field_get(unit, MEM_FAIL_INT_STATr, status, 2112 MTRO_PAR_ERRf)) { 2113 LOG_ERROR(BSL_LS_SOC_COMMON, 2114 (BSL_META_U(unit, 2115 "unit %d MTRO: parity hardware" 2116 " inconsistency\n"), 2117 unit)); 2118 return SOC_E_NONE; 2119 } 2120 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, EGRSHAPEPARITYERRORPTRr, 2121 REG_PORT_ANY, 0, &rval)); 2122 instance_num = soc_reg_field_get(unit, EGRSHAPEPARITYERRORPTRr, 2123 rval, INSTANCE_NUMf); 2124 ptr = soc_reg_field_get(unit, EGRSHAPEPARITYERRORPTRr, rval, PTRf); 2125 SOC_IF_ERROR_RETURN( 2126 _soc_triumph2_mtro_mmu_port_index_get(instance_num, ptr, 2127 &port, &index)); 2128 /* Disable parity */ 2129 SOC_IF_ERROR_RETURN(READ_MISCCONFIGr(unit, &val)); 2130 soc_reg_field_set(unit, MISCCONFIGr, &val, PARITY_CHK_ENf, 0); 2131 SOC_IF_ERROR_RETURN(WRITE_MISCCONFIGr(unit, val)); 2132 2133 if (port == REG_PORT_ANY) { 2134 for (i = 0; i < COUNTOF(cpu_mtro_regs); i++) { 2135 spci.port = port; 2136 spci.index = index; 2137 spci.reg = cpu_mtro_regs[i]; 2138 minfo = SOC_TRIUMPH2_MEM_PARITY_INFO(unit, block, info->error_field); 2139 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 2140 SOC_SWITCH_EVENT_DATA_ERROR_PARITY, 2141 index, minfo); 2142 rv = soc_ser_correction(unit, &spci); 2143 if (SOC_FAILURE(rv)) { 2144 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 2145 SOC_SWITCH_EVENT_DATA_ERROR_FAILEDTOCORRECT, 2146 index, minfo); 2147 } 2148 } 2149 } else if (port >=1 && port <= 53) { 2150 for (i = 0; i < COUNTOF(mtro_regs); i++) { 2151 spci.port = port; 2152 spci.index = index; 2153 spci.reg = mtro_regs[i]; 2154 minfo = SOC_TRIUMPH2_MEM_PARITY_INFO(unit, block, info->error_field); 2155 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 2156 SOC_SWITCH_EVENT_DATA_ERROR_PARITY, 2157 index, minfo); 2158 rv = soc_ser_correction(unit, &spci); 2159 if (SOC_FAILURE(rv)) { 2160 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 2161 SOC_SWITCH_EVENT_DATA_ERROR_FAILEDTOCORRECT, 2162 index, minfo); 2163 } 2164 } 2165 } else { 2166 LOG_ERROR(BSL_LS_SOC_COMMON, 2167 (BSL_META_U(unit, 2168 "unit %d MTRO: parity hardware inconsistency\n"), 2169 unit)); 2170 } 2171 SOC_IF_ERROR_RETURN(_soc_triumph2_parity_mmu_clear(unit, MTRO_PAR_ERRf)); 2172 /* Enable parity */ 2173 SOC_IF_ERROR_RETURN(READ_MISCCONFIGr(unit, &val)); 2174 soc_reg_field_set(unit, MISCCONFIGr, &val, PARITY_CHK_ENf, 1); 2175 SOC_IF_ERROR_RETURN(WRITE_MISCCONFIGr(unit, val)); 2176 return SOC_E_NONE; 2177 } 2178 STATIC int 2179 _soc_triumph2_process_oam_event_only(int unit) 2180 { 2181 int table; 2182 uint32 addr, cmic_status, group_status, 2183 group_enable, group_enable_origin, cpi_blk_bit; 2184 _soc_parity_info_t *info; 2185 soc_reg_t group_reg, reg; 2186 soc_port_t block_port; 2187 soc_block_t blk; 2188 soc_triumph2_oam_handler_t oam_handler_snapshot; 2189 /* coverity[result_independent_of_operands] */ 2190 SOC_IF_ERROR_RETURN(READ_CMIC_CHIP_PARITY_INTR_STATUSr(unit, 2191 &cmic_status)); 2192 info = _soc_tr2_parity_group_info[_SOC_TR2_OAM_GROUP_NUM].info; 2193 group_reg = _soc_tr2_parity_group_info[_SOC_TR2_OAM_GROUP_NUM].enable_reg; 2194 cpi_blk_bit = _soc_tr2_parity_group_info[_SOC_TR2_OAM_GROUP_NUM].cpi_bit; 2195 2196 SOC_BLOCK_ITER(unit, blk, 2197 _soc_tr2_parity_group_info[_SOC_TR2_OAM_GROUP_NUM].blocktype) { 2198 if (_soc_triumph_parity_block_port(unit, blk, &block_port) < 0) { 2199 cpi_blk_bit <<= 1; 2200 continue; 2201 } 2202 if (!(cmic_status & cpi_blk_bit)) { 2203 cpi_blk_bit <<= 1; 2204 continue; 2205 } 2206 2207 addr = soc_reg_addr(unit, group_reg, block_port, 0); 2208 SOC_IF_ERROR_RETURN(soc_reg32_read(unit, addr, &group_status)); 2209 2210 /* loop through each table in the group */ 2211 for (table = 0; info[table].error_field != INVALIDf; table++) { 2212 if (!soc_reg_field_valid(unit, group_reg, 2213 info[table].error_field) && 2214 (info[table].mem != INVALIDm)) { 2215 LOG_ERROR(BSL_LS_SOC_COMMON, 2216 (BSL_META_U(unit, 2217 "unit %d %s has bad error field\n"), 2218 unit, SOC_MEM_NAME(unit, info[table].mem))); 2219 continue; 2220 } 2221 2222 if (!soc_reg_field_get(unit, group_reg, group_status, 2223 info[table].error_field)) { 2224 continue; 2225 } 2226 2227 if (info[table].type == _SOC_PARITY_INFO_TYPE_OAM) { 2228 /* OAM isn't parity-related but shares an interrupt */ 2229 oam_handler_snapshot = oam_handler[unit]; 2230 2231 if (oam_handler_snapshot != NULL) { 2232 SOC_IF_ERROR_RETURN(oam_handler_snapshot(unit, 2233 info[table].error_field)); 2234 } 2235 2236 } 2237 2238 } /* loop through each table in the group */ 2239 2240 reg = _soc_tr2_parity_group_info[_SOC_TR2_OAM_GROUP_NUM].enable_reg; 2241 addr = soc_reg_addr(unit, reg, block_port, 0); 2242 SOC_IF_ERROR_RETURN(soc_reg32_read(unit, addr, &group_enable)); 2243 group_enable_origin = group_enable; 2244 group_enable &= ~group_status; 2245 SOC_IF_ERROR_RETURN(soc_reg32_write(unit, addr, group_enable)); 2246 group_enable |= (group_status & group_enable_origin); 2247 SOC_IF_ERROR_RETURN(soc_reg32_write(unit, addr, group_enable)); 2248 } /* loop through tables in the group */ 2249 2250 return SOC_E_NONE; 2251 } 2252 2253 void 2254 soc_triumph2_oam_events(void *unit_vp, void *d1, void *d2, 2255 void *d3, void *d4) 2256 { 2257 int unit = PTR_TO_INT(unit_vp); 2258 2259 (void)_soc_triumph2_process_oam_event_only(unit); 2260 sal_usleep(1000); /* Don't reenable too soon */ 2261 soc_intr_enable(unit, IRQ_MEM_FAIL); 2262 } 2263 2264 2265 STATIC int 2266 _soc_triumph2_parity_process_mmuwred(int unit, _soc_parity_info_t *info, 2267 soc_port_t block_port, char *msg) 2268 { 2269 soc_reg_t reg; 2270 uint32 addr0, addr1, entry_idx, status, rval; 2271 _soc_ser_correct_info_t spci; 2272 2273 /* 2274 * status0 (WRED_PARITY_ERROR_INFOr) is index 2275 * status1 (WRED_PARITY_ERROR_BITMAPr) is table id 2276 */ 2277 reg = info->intr_status0_reg; 2278 addr0 = soc_reg_addr(unit, reg, block_port, 0); 2279 SOC_IF_ERROR_RETURN(soc_reg32_read(unit, addr0, &entry_idx)); 2280 reg = info->intr_status1_reg; 2281 addr1 = soc_reg_addr(unit, reg, block_port, 0); 2282 SOC_IF_ERROR_RETURN(soc_reg32_read(unit, addr1, &status)); 2283 sal_memset(&spci, 0, sizeof(spci)); 2284 spci.mem = info->mem; 2285 if (status & 0x000003) { 2286 msg = "WRED_CFG_CELL"; 2287 spci.mem = MMU_WRED_CFG_CELLm; 2288 } else if (status & 0x00000c) { 2289 msg = "WRED_THD_0_CELL"; 2290 spci.mem = MMU_WRED_THD_0_CELLm; 2291 } else if (status & 0x000030) { 2292 msg = "WRED_THD_1_CELL"; 2293 spci.mem = MMU_WRED_THD_1_CELLm; 2294 } else if (status & 0x0000c0) { 2295 msg = "WRED_CFG_PACKET"; 2296 spci.mem = MMU_WRED_CFG_PACKETm; 2297 } else if (status & 0x000300) { 2298 msg = "WRED_THD_0_PACKET"; 2299 spci.mem = MMU_WRED_THD_0_PACKETm; 2300 } else if (status & 0x000c00) { 2301 msg = "WRED_THD_1_PACKET"; 2302 spci.mem = MMU_WRED_THD_1_PACKETm; 2303 } else if (status & 0x003000) { 2304 msg = "WRED_PORT_CFG_CELL"; 2305 spci.mem = MMU_WRED_PORT_CFG_CELLm; 2306 } else if (status & 0x00c000) { 2307 msg = "WRED_PORT_THD_0_CELL"; 2308 spci.mem = MMU_WRED_PORT_THD_0_CELLm; 2309 } else if (status & 0x030000) { 2310 msg = "WRED_PORT_THD_1_CELL"; 2311 spci.mem = MMU_WRED_PORT_THD_1_CELLm; 2312 } else if (status & 0x0c0000) { 2313 msg = "WRED_PORT_CFG_PACKET"; 2314 spci.mem = MMU_WRED_PORT_CFG_PACKETm; 2315 } else if (status & 0x300000) { 2316 msg = "WRED_PORT_THD_0_PACKET"; 2317 spci.mem = MMU_WRED_PORT_THD_0_PACKETm; 2318 } else if (status & 0xc00000) { 2319 msg = "WRED_PORT_THD_1_PACKET"; 2320 spci.mem = MMU_WRED_PORT_THD_1_PACKETm; 2321 } else { 2322 LOG_ERROR(BSL_LS_SOC_COMMON, 2323 (BSL_META_U(unit, 2324 "unit %d %s parity hardware inconsistency\n"), 2325 unit, msg)); 2326 return SOC_E_NONE; 2327 } 2328 2329 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 2330 SOC_SWITCH_EVENT_DATA_ERROR_PARITY, 2331 info->mem, info->error_field); 2332 LOG_ERROR(BSL_LS_SOC_COMMON, 2333 (BSL_META_U(unit, 2334 "unit %d %s entry %d parity error\n"), 2335 unit, msg, entry_idx)); 2336 2337 if (spci.mem != INVALIDm) { 2338 spci.flags = SOC_SER_SRC_MEM | SOC_SER_REG_MEM_KNOWN; 2339 spci.reg = INVALIDr; 2340 spci.blk_type = SOC_BLK_MMU; 2341 spci.index = entry_idx; 2342 2343 SOC_IF_ERROR_RETURN(READ_MISCCONFIGr(unit, &rval)); 2344 soc_reg_field_set(unit, MISCCONFIGr, &rval, PARITY_CHK_ENf, 0); 2345 SOC_IF_ERROR_RETURN(WRITE_MISCCONFIGr(unit, rval)); 2346 2347 (void)soc_ser_correction(unit, &spci); 2348 SOC_IF_ERROR_RETURN(soc_reg32_write(unit, addr0, 0)); 2349 SOC_IF_ERROR_RETURN(soc_reg32_write(unit, addr1, 0)); 2350 SOC_IF_ERROR_RETURN(_soc_triumph2_parity_mmu_clear(unit, WRED_PAR_ERRf)); 2351 2352 SOC_IF_ERROR_RETURN(READ_MISCCONFIGr(unit, &rval)); 2353 soc_reg_field_set(unit, MISCCONFIGr, &rval, PARITY_CHK_ENf, 1); 2354 SOC_IF_ERROR_RETURN(WRITE_MISCCONFIGr(unit, rval)); 2355 } 2356 return SOC_E_NONE; 2357 } 2358 2359 2360 STATIC int 2361 _soc_triumph2_process_parity_error(int unit) 2362 { 2363 int group, table, index, size; 2364 uint32 addr, cmic_status, group_status, status, 2365 group_enable, group_enable_origin, cpi_blk_bit; 2366 uint32 entry_idx; 2367 _soc_parity_info_t *info; 2368 soc_reg_t group_reg, reg; 2369 soc_port_t block_port; 2370 soc_block_t blk; 2371 char *msg; 2372 soc_triumph2_oam_handler_t oam_handler_snapshot; 2373 /* coverity[result_independent_of_operands] */ 2374 SOC_IF_ERROR_RETURN(READ_CMIC_CHIP_PARITY_INTR_STATUSr(unit, 2375 &cmic_status)); 2376 2377 /* loop through each group */ 2378 for (group = 0; _soc_tr2_parity_group_info[group].cpi_bit; group++) { 2379 info = _soc_tr2_parity_group_info[group].info; 2380 group_reg = _soc_tr2_parity_group_info[group].status_reg; 2381 cpi_blk_bit = _soc_tr2_parity_group_info[group].cpi_bit; 2382 2383 SOC_BLOCK_ITER(unit, blk, 2384 _soc_tr2_parity_group_info[group].blocktype) { 2385 if (_soc_triumph_parity_block_port(unit, blk, &block_port) < 0) { 2386 cpi_blk_bit <<= 1; 2387 continue; 2388 } 2389 if (!(cmic_status & cpi_blk_bit)) { 2390 cpi_blk_bit <<= 1; 2391 continue; 2392 } 2393 2394 addr = soc_reg_addr(unit, group_reg, block_port, 0); 2395 SOC_IF_ERROR_RETURN(soc_reg32_read(unit, addr, &group_status)); 2396 2397 /* loop through each table in the group */ 2398 for (table = 0; info[table].error_field != INVALIDf; table++) { 2399 if (!soc_reg_field_valid(unit, group_reg, 2400 info[table].error_field) && 2401 (info[table].mem != INVALIDm)) { 2402 LOG_ERROR(BSL_LS_SOC_COMMON, 2403 (BSL_META_U(unit, 2404 "unit %d %s has bad error field\n"), 2405 unit, SOC_MEM_NAME(unit, info[table].mem))); 2406 continue; 2407 } 2408 2409 if (!soc_reg_field_get(unit, group_reg, group_status, 2410 info[table].error_field)) { 2411 continue; 2412 } 2413 if (info[table].msg) { 2414 msg = info[table].msg; 2415 } else if (info[table].mem != INVALIDm) { 2416 msg = SOC_MEM_NAME(unit, info[table].mem); 2417 } else { 2418 msg = SOC_FIELD_NAME(unit, info[table].error_field); 2419 } 2420 2421 /* handle different parity error reporting style */ 2422 switch (info[table].type) { 2423 case _SOC_PARITY_INFO_TYPE_GENERIC: 2424 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 2425 SOC_SWITCH_EVENT_DATA_ERROR_PARITY, 2426 info[table].mem, 2427 info[table].error_field); 2428 2429 if (info[table].enable_field == START_BY_START_ERR_ENf) { 2430 uint64 rr64; 2431 uint32 msw; 2432 uint32 lsw; 2433 uint32 regval; 2434 2435 /* Clear the start-by-start port bitmap */ 2436 SOC_IF_ERROR_RETURN 2437 (READ_START_BY_START_ERROR_64r(unit, &rr64)); 2438 COMPILER_64_TO_32_HI(msw, rr64); 2439 COMPILER_64_TO_32_LO(lsw, rr64); 2440 LOG_ERROR(BSL_LS_SOC_COMMON, 2441 (BSL_META_U(unit, 2442 "unit %d START_BY_START_ERRROR = 0x%x%08x\n"), 2443 unit, msw, lsw)); 2444 COMPILER_64_ZERO(rr64); 2445 SOC_IF_ERROR_RETURN 2446 (WRITE_START_BY_START_ERROR_64r(unit, rr64)); 2447 2448 /* Clear the start-by-start error indication*/ 2449 SOC_IF_ERROR_RETURN(READ_MEM_FAIL_INT_STATr(unit, ®val)); 2450 soc_reg_field_set(unit, MEM_FAIL_INT_STATr, ®val, 2451 START_BY_START_ERRf, 0); 2452 SOC_IF_ERROR_RETURN(WRITE_MEM_FAIL_INT_STATr(unit, regval)); 2453 } 2454 2455 LOG_ERROR(BSL_LS_SOC_COMMON, 2456 (BSL_META_U(unit, 2457 "unit %d %s asserted\n"), 2458 unit, msg)); 2459 break; 2460 case _SOC_PARITY_INFO_TYPE_SINGLE_PARITY: 2461 SOC_IF_ERROR_RETURN 2462 (_soc_triumph2_process_single_parity_error(unit, 2463 group, block_port, table, FALSE, msg, -1)); 2464 break; 2465 case _SOC_PARITY_INFO_TYPE_SINGLE_ECC: 2466 SOC_IF_ERROR_RETURN 2467 (_soc_triumph2_process_single_ecc_error(unit, 2468 group, block_port, table, FALSE, msg, -1)); 2469 break; 2470 case _SOC_PARITY_INFO_TYPE_SINGLE_COUNTER: 2471 SOC_IF_ERROR_RETURN 2472 (_soc_triumph2_process_single_counter_error(unit, 2473 group, block_port, table, FALSE, msg, -1)); 2474 break; 2475 case _SOC_PARITY_INFO_TYPE_DUAL_PARITY: 2476 SOC_IF_ERROR_RETURN 2477 (_soc_triumph2_process_dual_parity_error(unit, 2478 group, block_port, table, FALSE, msg, -1)); 2479 break; 2480 case _SOC_PARITY_INFO_TYPE_MMU_PARITY: 2481 SOC_IF_ERROR_RETURN 2482 (_soc_triumph2_process_mmu_parity_error(unit, 2483 group, block_port, table, msg)); 2484 break; 2485 case _SOC_PARITY_INFO_TYPE_MMUIPMC: 2486 /* 2487 * status0 (MEM1_IPMCGRP_TBL_PARITYERRORPTRr) is index 2488 * status1 (MEM1_IPMCGRP_TBL_PARITYERROR_STATUSr) is table id 2489 * MMU_IPMC_GROUP_TBL0m - MMU_IPMC_GROUP_TBL8m 2490 */ 2491 reg = info[table].intr_status1_reg; 2492 addr = soc_reg_addr(unit, reg, block_port, 0); 2493 SOC_IF_ERROR_RETURN(soc_reg32_read(unit, addr, &status)); 2494 size = soc_reg_field_length(unit, reg, STATUSf); 2495 reg = info[table].intr_status0_reg; 2496 for (index = 0; index < size; index++, status >>= 1) { 2497 if (!(status & 1)) { 2498 continue; 2499 } 2500 addr = soc_reg_addr(unit, reg, block_port, index); 2501 SOC_IF_ERROR_RETURN(soc_reg32_read(unit, addr, 2502 &entry_idx)); 2503 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 2504 SOC_SWITCH_EVENT_DATA_ERROR_PARITY, 2505 info[table].mem, 2506 info[table].error_field); 2507 2508 LOG_ERROR(BSL_LS_SOC_COMMON, 2509 (BSL_META_U(unit, 2510 "unit %d %s%d entry %d parity error\n"), 2511 unit, msg, index, entry_idx)); 2512 } 2513 break; 2514 case _SOC_PARITY_INFO_TYPE_MMUWRED: 2515 SOC_IF_ERROR_RETURN( 2516 _soc_triumph2_parity_process_mmuwred(unit, &info[table], 2517 block_port, msg)); 2518 break; 2519 case _SOC_PARITY_INFO_TYPE_MMUMTRO: 2520 SOC_IF_ERROR_RETURN( 2521 _soc_triumph2_parity_process_mmumtro(unit, 2522 &info[table], group)); 2523 break; 2524 case _SOC_PARITY_INFO_TYPE_OAM: 2525 /* OAM isn't parity-related but shares an interrupt */ 2526 2527 oam_handler_snapshot = oam_handler[unit]; 2528 2529 2530 if (oam_handler_snapshot != NULL) 2531 { 2532 SOC_IF_ERROR_RETURN(oam_handler_snapshot(unit, 2533 info[table].error_field)); 2534 } 2535 2536 break; 2537 default: 2538 break; 2539 } /* handle different parity error reporting style */ 2540 } /* loop through each table in the group */ 2541 2542 reg = _soc_tr2_parity_group_info[group].enable_reg; 2543 addr = soc_reg_addr(unit, reg, block_port, 0); 2544 SOC_IF_ERROR_RETURN(soc_reg32_read(unit, addr, &group_enable)); 2545 group_enable_origin = group_enable; 2546 group_enable &= ~group_status; 2547 SOC_IF_ERROR_RETURN(soc_reg32_write(unit, addr, group_enable)); 2548 group_enable |= (group_status & group_enable_origin); 2549 SOC_IF_ERROR_RETURN(soc_reg32_write(unit, addr, group_enable)); 2550 } /* loop through each block for the group */ 2551 } /* loop through each group */ 2552 2553 return SOC_E_NONE; 2554 } 2555 2556 void 2557 soc_triumph2_parity_error(void *unit_vp, void *d1, void *d2, 2558 void *d3, void *d4) 2559 { 2560 int unit = PTR_TO_INT(unit_vp); 2561 2562 _soc_triumph2_process_parity_error(unit); 2563 sal_usleep(1000); /* Don't reenable too soon */ 2564 soc_intr_enable(unit, IRQ_MEM_FAIL); 2565 } 2566 2567 STATIC int 2568 _soc_triumph2_mem_nack_error_process(int unit, _ser_nack_reg_mem_t nack_reg_mem, int block) 2569 { 2570 int group, table; 2571 _soc_parity_info_t *info; 2572 soc_port_t block_port; 2573 soc_block_t blk; 2574 char *msg; 2575 2576 if ((nack_reg_mem.mem == INVALIDm) && (nack_reg_mem.reg_mem == _SOC_SER_MEM)) { 2577 return SOC_E_PARAM; 2578 } 2579 2580 /* loop through each group */ 2581 for (group = 0; _soc_tr2_parity_group_info[group].cpi_bit; group++) { 2582 info = _soc_tr2_parity_group_info[group].info; 2583 2584 SOC_BLOCK_ITER(unit, blk, 2585 _soc_tr2_parity_group_info[group].blocktype) { 2586 if (block != SOC_BLOCK_INFO(unit, blk).schan) { 2587 continue; 2588 } 2589 if (_soc_triumph_parity_block_port(unit, blk, &block_port) < 0) { 2590 continue; 2591 } 2592 /* loop through each table in the group */ 2593 for (table = 0; info[table].error_field != INVALIDf; table++) { 2594 if ((info[table].type != _SOC_PARITY_INFO_TYPE_SINGLE_COUNTER) && 2595 (nack_reg_mem.reg_mem == _SOC_SER_REG)) { 2596 continue; 2597 } 2598 if ((info[table].mem != nack_reg_mem.mem) && (nack_reg_mem.reg_mem == _SOC_SER_MEM)) { 2599 continue; 2600 } 2601 if (info[table].nack_status0_reg == INVALIDr) { 2602 return SOC_E_NOT_FOUND; 2603 } 2604 if (info[table].msg) { 2605 msg = info[table].msg; 2606 } else { /* mem must be valid to get her */ 2607 msg = SOC_MEM_NAME(unit, info[table].mem); 2608 } 2609 2610 /* handle different parity error reporting style */ 2611 switch (info[table].type) { 2612 case _SOC_PARITY_INFO_TYPE_SINGLE_PARITY: 2613 SOC_IF_ERROR_RETURN 2614 (_soc_triumph2_process_single_parity_error(unit, 2615 group, block_port, table, TRUE, msg, blk)); 2616 break; 2617 case _SOC_PARITY_INFO_TYPE_SINGLE_ECC: 2618 SOC_IF_ERROR_RETURN 2619 (_soc_triumph2_process_single_ecc_error(unit, 2620 group, block_port, table, TRUE, msg, blk)); 2621 break; 2622 case _SOC_PARITY_INFO_TYPE_SINGLE_COUNTER: 2623 SOC_IF_ERROR_RETURN 2624 (_soc_triumph2_process_single_counter_error(unit, 2625 group, block_port, table, TRUE, msg, blk)); 2626 break; 2627 case _SOC_PARITY_INFO_TYPE_DUAL_PARITY: 2628 SOC_IF_ERROR_RETURN 2629 (_soc_triumph2_process_dual_parity_error(unit, 2630 group, block_port, table, TRUE, msg, blk)); 2631 break; 2632 default: 2633 break; 2634 } /* handle different parity error reporting style */ 2635 } /* loop through each table in the group */ 2636 } /* loop through each block of the group */ 2637 } /* loop through each group */ 2638 2639 return SOC_E_NONE; 2640 } 2641 2642 void 2643 soc_triumph2_stat_nack(int unit, int *fixed) 2644 { 2645 int rv; 2646 _ser_nack_reg_mem_t nack_reg_mem; 2647 2648 nack_reg_mem.reg_mem = _SOC_SER_REG; 2649 nack_reg_mem.mem = INVALIDm; 2650 nack_reg_mem.reg = INVALIDr; 2651 _stat_error_fixed[unit] = 0; 2652 2653 if ((rv = _soc_triumph2_mem_nack_error_process(unit, nack_reg_mem, 0)) < 0) { 2654 LOG_ERROR(BSL_LS_SOC_COMMON, 2655 (BSL_META_U(unit, 2656 "unit %d STAT SCHAN NACK analysis failure.\n"), unit)); 2657 } 2658 *fixed = _stat_error_fixed[unit]; 2659 } 2660 2661 void 2662 soc_triumph2_mem_nack(void *unit_vp, void *addr_vp, void *blk_vp, 2663 void *d3, void *d4) 2664 { 2665 int rv, unit = PTR_TO_INT(unit_vp); 2666 uint32 address = PTR_TO_INT(addr_vp); 2667 uint32 block = PTR_TO_INT(blk_vp); 2668 uint32 offset = 0, min_addr = 0, max_addr = 0; 2669 _ser_nack_reg_mem_t nack_reg_mem; 2670 soc_regaddrinfo_t ainfo; 2671 2672 nack_reg_mem.reg_mem = PTR_TO_INT(d3); 2673 nack_reg_mem.mem = INVALIDm; 2674 nack_reg_mem.reg = INVALIDr; 2675 2676 if (nack_reg_mem.reg_mem == _SOC_SER_REG) { 2677 if (address) { 2678 soc_regaddrinfo_get(unit, &ainfo, address); 2679 nack_reg_mem.reg = ainfo.reg; 2680 } 2681 } else { 2682 offset = address & ~0xC0f00000; /* Strip block ID */ 2683 2684 nack_reg_mem.mem = soc_addr_to_mem(unit, address, &block); 2685 if (nack_reg_mem.mem == INVALIDm) { 2686 LOG_ERROR(BSL_LS_SOC_COMMON, 2687 (BSL_META_U(unit, 2688 "unit %d mem decode failed " 2689 "SCHAN NACK analysis failure\n"), unit)); 2690 return; 2691 } 2692 min_addr = max_addr = SOC_MEM_INFO(unit, nack_reg_mem.mem).base; 2693 min_addr += SOC_MEM_INFO(unit, nack_reg_mem.mem).index_min; 2694 max_addr += SOC_MEM_INFO(unit, nack_reg_mem.mem).index_max; 2695 2696 /* Convert component/aggregate memories to the table for which 2697 * the parity registers correspond. */ 2698 switch(nack_reg_mem.mem) { 2699 case VLAN_SUBNETm: 2700 nack_reg_mem.mem = VLAN_SUBNET_DATA_ONLYm; /* Should be VLAN_SUBNET? */ 2701 break; 2702 case L2_ENTRY_ONLYm: 2703 nack_reg_mem.mem = L2Xm; 2704 break; 2705 case L2_USER_ENTRY_ONLYm: 2706 case L2_USER_ENTRY_DATA_ONLYm: 2707 nack_reg_mem.mem = L2_USER_ENTRYm; 2708 break; 2709 case L3_DEFIPm: 2710 nack_reg_mem.mem = L3_DEFIP_DATA_ONLYm; 2711 break; 2712 case L3_DEFIP_128m: 2713 nack_reg_mem.mem = L3_DEFIP_128_DATA_ONLYm; 2714 break; 2715 case EGR_IP_TUNNEL_IPV6m: 2716 case EGR_IP_TUNNEL_MPLSm: 2717 nack_reg_mem.mem = EGR_IP_TUNNELm; 2718 break; 2719 case L3_ENTRY_IPV4_UNICASTm: 2720 case L3_ENTRY_IPV4_MULTICASTm: 2721 case L3_ENTRY_IPV6_MULTICASTm: 2722 case L3_ENTRY_IPV6_UNICASTm: 2723 nack_reg_mem.mem = L3_ENTRY_ONLYm; 2724 break; 2725 default: 2726 /* Do nothing, keep memory as provided */ 2727 break; 2728 } 2729 } 2730 2731 2732 if ((rv = _soc_triumph2_mem_nack_error_process(unit, nack_reg_mem, block)) < 0) { 2733 if (nack_reg_mem.reg_mem == _SOC_SER_REG) { 2734 LOG_ERROR(BSL_LS_SOC_COMMON, 2735 (BSL_META_U(unit, 2736 "unit %d REG SCHAN NACK analysis failure\n"), 2737 unit)); 2738 } else { 2739 LOG_ERROR(BSL_LS_SOC_COMMON, 2740 (BSL_META_U(unit, 2741 "unit %d %s entry %d SCHAN NACK analysis failure\n"), 2742 unit, SOC_MEM_NAME(unit, nack_reg_mem.mem), 2743 min_addr - offset)); 2744 } 2745 } 2746 } 2747 2748 STATIC int 2749 _soc_triumph2_mem_ecc_force(int unit, soc_port_t block_port, 2750 _soc_parity_info_t *info) 2751 { 2752 soc_reg_t force_sbe_reg, force_dbe_reg; 2753 soc_field_t force_field; 2754 2755 force_field = info->error_field; 2756 if (force_field == RX_FIFO_MEM_ERRf) { 2757 force_field = RX_FIFO_MEMf; 2758 } else if (force_field == TX_FIFO_MEM_ERRf) { 2759 force_field = TX_FIFO_MEMf; 2760 } 2761 2762 force_sbe_reg = info->intr_status1_reg; 2763 force_dbe_reg = info->nack_status1_reg; 2764 2765 /* Single-bit error force */ 2766 if (SOC_REG_IS_VALID(unit, force_sbe_reg) && 2767 soc_reg_field_valid(unit, force_sbe_reg, force_field)) { 2768 SOC_IF_ERROR_RETURN 2769 (soc_reg_field32_modify(unit, force_sbe_reg, 2770 block_port, force_field, 1)); 2771 } else { 2772 LOG_ERROR(BSL_LS_SOC_COMMON, 2773 (BSL_META_U(unit, 2774 "unit %d %s.%s not valid\n"), 2775 unit, 2776 SOC_REG_IS_VALID(unit, force_sbe_reg) ? 2777 SOC_REG_NAME(unit, force_sbe_reg) : "Unknown", 2778 soc_reg_field_valid(unit, force_sbe_reg, force_field) ? 2779 SOC_FIELD_NAME(unit, force_field) : "Unknown")); 2780 } 2781 2782 sal_usleep(1000); /* Wait for interrupt-mode logic to kick in */ 2783 2784 /* Double-bit error force */ 2785 if (SOC_REG_IS_VALID(unit, force_dbe_reg) && 2786 soc_reg_field_valid(unit, force_dbe_reg, force_field)) { 2787 SOC_IF_ERROR_RETURN 2788 (soc_reg_field32_modify(unit, force_dbe_reg, 2789 block_port, force_field, 1)); 2790 } else { 2791 LOG_ERROR(BSL_LS_SOC_COMMON, 2792 (BSL_META_U(unit, 2793 "unit %d %s.%s not valid\n"), 2794 unit, SOC_REG_NAME(unit, force_dbe_reg), 2795 SOC_FIELD_NAME(unit, force_field))); 2796 } 2797 2798 return SOC_E_NONE; 2799 } 2800 2801 int 2802 _soc_triumph2_mem_nack_error_test(int unit, _soc_ser_test_t test_type, int *testErrors) 2803 { 2804 int group, table, rv; 2805 _soc_parity_info_t *info; 2806 soc_mem_t mem; 2807 soc_port_t block_port; 2808 soc_block_t blk; 2809 uint32 testCount = 0; 2810 2811 /* loop through each group */ 2812 for (group = 0; _soc_tr2_parity_group_info[group].cpi_bit; group++) { 2813 info = _soc_tr2_parity_group_info[group].info; 2814 2815 SOC_BLOCK_ITER(unit, blk, 2816 _soc_tr2_parity_group_info[group].blocktype) { 2817 if (_soc_triumph_parity_block_port(unit, blk, &block_port) < 0) { 2818 continue; 2819 } 2820 2821 for (table = 0; info[table].error_field != INVALIDf; table++) { 2822 mem = info[table].mem; 2823 if (mem == INVALIDm) { 2824 continue; 2825 } 2826 2827 if ((mem == PORT_OR_TRUNK_MAC_COUNTm) || (mem == VLAN_OR_VFI_MAC_COUNTm) || 2828 (mem == L2_USER_ENTRY_DATA_ONLYm)) { 2829 /*tr2 isnot supported for these two count memories because SYS_MAC_LIMIT_CONTROL is not enabled 2830 *L2_USER_ENTRY_DATA_ONLY isnot supported because L2_USER_ENTRY 2831 * does not work with the SER model*/ 2832 continue; 2833 } 2834 2835 if ((info[table].control_reg == INVALIDr) || 2836 !soc_reg_field_valid(unit, info[table].control_reg, 2837 info[table].enable_field)) { 2838 LOG_ERROR(BSL_LS_SOC_COMMON, 2839 (BSL_META_U(unit, 2840 "unit %d %s has no parity toggle\n"), 2841 unit, SOC_MEM_NAME(unit, mem))); 2842 continue; 2843 } 2844 switch (info[table].type) { 2845 case _SOC_PARITY_INFO_TYPE_SINGLE_PARITY: 2846 case _SOC_PARITY_INFO_TYPE_SINGLE_COUNTER: 2847 case _SOC_PARITY_INFO_TYPE_DUAL_PARITY: 2848 break; 2849 case _SOC_PARITY_INFO_TYPE_SINGLE_ECC: 2850 if (block_port != REG_PORT_ANY) { 2851 /* Force registers exist */ 2852 SOC_IF_ERROR_RETURN 2853 (_soc_triumph2_mem_ecc_force(unit, block_port, 2854 &(info[table]))); 2855 } 2856 break; 2857 default: 2858 /* No field to check. */ 2859 continue; 2860 } 2861 testCount++; 2862 rv = ser_test_mem_pipe(unit,info[table].control_reg, -1, 2863 info[table].enable_field, mem, INVALIDf, 2864 test_type, blk, block_port, 2865 _SOC_ACC_TYPE_PIPE_ANY, testErrors); 2866 if (rv != SOC_E_NONE) { 2867 LOG_CLI((BSL_META_U(unit, 2868 "Error during TCAM test.\n"))); 2869 continue; 2870 } 2871 } 2872 } 2873 } 2874 LOG_CLI((BSL_META_U(unit, 2875 "Hardware SER memories tested: %u\n"),testCount)); 2876 return SOC_E_NONE; 2877 } 2878 2879 /* SER processing for TCAMs */ 2880 2881 2882 STATIC _soc_ser_parity_info_t _soc_tr2_ser_parity_info[] = { 2883 { EFP_TCAMm, _SOC_SER_PARITY_MODE_2BITS, 2884 CMIC_SER_START_ADDR_0r, CMIC_SER_END_ADDR_0r, 2885 CMIC_SER_MEM_ADDR_0r, CMIC_SER_PARITY_MODE_SELr, 2886 RANGE_0_PARITY_BITSf, -1, INVALIDr, 0, 0, 0, _SOC_SER_FLAG_XY_READ}, 2887 { EGR_ERSPANm, _SOC_SER_PARITY_MODE_2BITS, 2888 CMIC_SER_START_ADDR_1r, CMIC_SER_END_ADDR_1r, 2889 CMIC_SER_MEM_ADDR_1r, CMIC_SER_PARITY_MODE_SELr, 2890 RANGE_1_PARITY_BITSf, -1, INVALIDr, 0, 0, 0, 0}, 2891 { FP_SLICE_MAPm, _SOC_SER_PARITY_MODE_2BITS, 2892 CMIC_SER_START_ADDR_2r, CMIC_SER_END_ADDR_2r, 2893 CMIC_SER_MEM_ADDR_2r, CMIC_SER_PARITY_MODE_SELr, 2894 RANGE_2_PARITY_BITSf, -1, INVALIDr, 0, 0, 0, 0}, 2895 { FP_TCAMm, _SOC_SER_PARITY_MODE_2BITS, 2896 CMIC_SER_START_ADDR_3r, CMIC_SER_END_ADDR_3r, 2897 CMIC_SER_MEM_ADDR_3r, CMIC_SER_PARITY_MODE_SELr, 2898 RANGE_3_PARITY_BITSf, -1, INVALIDr, 0, 0, 0, _SOC_SER_FLAG_XY_READ}, 2899 { ING_IPFIX_PROFILEm, _SOC_SER_PARITY_MODE_2BITS, 2900 CMIC_SER_START_ADDR_4r, CMIC_SER_END_ADDR_4r, 2901 CMIC_SER_MEM_ADDR_4r, CMIC_SER_PARITY_MODE_SELr, 2902 RANGE_4_PARITY_BITSf, -1, INVALIDr, 0, 0, 0, 0}, 2903 { MPLS_STATION_TCAMm, _SOC_SER_PARITY_MODE_2BITS, 2904 CMIC_SER_START_ADDR_5r, CMIC_SER_END_ADDR_5r, 2905 CMIC_SER_MEM_ADDR_5r, CMIC_SER_PARITY_MODE_SELr, 2906 RANGE_5_PARITY_BITSf, -1, INVALIDr, 0, 0, 0, 0}, 2907 { VFP_TCAMm, _SOC_SER_PARITY_MODE_2BITS, 2908 CMIC_SER_START_ADDR_6r, CMIC_SER_END_ADDR_6r, 2909 CMIC_SER_MEM_ADDR_6r, CMIC_SER_PARITY_MODE_SELr, 2910 RANGE_6_PARITY_BITSf, -1, INVALIDr, 0, 0, 0, _SOC_SER_FLAG_XY_READ}, 2911 2912 { INVALIDm, _SOC_SER_PARITY_MODE_NUM}, 2913 }; 2914 2915 #define SOC_TR2_SER_MEM_AVAILABLE (2048 * 32) /* bits */ 2916 2917 STATIC int 2918 _soc_triumph2_ser_init(int unit) 2919 { 2920 int info_ix; 2921 if (soc_feature(unit, soc_feature_field_stage_half_slice) || 2922 soc_feature(unit, soc_feature_field_stage_egress_256_half_slice) || 2923 soc_feature(unit, soc_feature_field_stage_quarter_slice)) { 2924 info_ix = 0; 2925 while (_soc_tr2_ser_parity_info[info_ix].mem != INVALIDm) { 2926 if (( _soc_tr2_ser_parity_info[info_ix].mem == EFP_TCAMm) || 2927 ( _soc_tr2_ser_parity_info[info_ix].mem == FP_TCAMm)) { 2928 _soc_tr2_ser_parity_info[info_ix].ser_flags |= 2929 _SOC_SER_FLAG_NO_DMA; 2930 } 2931 info_ix++; 2932 } 2933 } 2934 2935 return soc_ser_init(unit, _soc_tr2_ser_parity_info, 2936 SOC_TR2_SER_MEM_AVAILABLE); 2937 } 2938 2939 int 2940 soc_triumph2_ser_mem_clear(int unit, soc_mem_t mem) 2941 { 2942 return soc_ser_mem_clear(unit, _soc_tr2_ser_parity_info, mem); 2943 } 2944 2945 void 2946 soc_triumph2_ser_fail(int unit) 2947 2948 { 2949 soc_process_ser_parity_error(unit, _soc_tr2_ser_parity_info, 2950 SOC_SWITCH_EVENT_DATA_ERROR_PARITY); 2951 return; 2952 } 2953 2954 typedef struct _soc_esm_intr_reg_info_s { 2955 soc_field_t error_field; 2956 char *msg; 2957 soc_reg_t detail_reg[3]; 2958 }_soc_esm_intr_reg_info_t; 2959 2960 STATIC _soc_esm_intr_reg_info_t _soc_tr2_etu_intr_reg_info[] = { 2961 { ILL_SRAM_ACCf, NULL, {INVALIDr, INVALIDr, INVALIDr}}, 2962 { SBUS_REQACK_ERRf, NULL, {INVALIDr, INVALIDr, INVALIDr}}, 2963 { BKGND_PROC_SECf, NULL, 2964 { ETU_BKGND_PROC_SEC_INFOr, INVALIDr, INVALIDr}}, 2965 { BKGND_PROC_ERRf, NULL, 2966 { ETU_BKGND_PROC_ERR_INFOr, INVALIDr, INVALIDr}}, 2967 { SBUS_CMD_SECf, NULL, {ETU_SBUS_CMD_SEC_INFOr, INVALIDr, INVALIDr}}, 2968 { SBUS_CMD_ERRf, NULL, 2969 { ETU_SBUS_CMD_ERR_INFO1r, ETU_SBUS_CMD_ERR_INFO2r, INVALIDr}}, 2970 { ET_DPEO_PERRf, NULL, {INVALIDr, INVALIDr, INVALIDr}}, 2971 { ET_S1_MWS_ERRf, NULL, {INVALIDr, INVALIDr, INVALIDr}}, 2972 { ET_S0_MWS_ERRf, NULL, {INVALIDr, INVALIDr, INVALIDr}}, 2973 { ET_S1_NORV_ERRf, NULL, {INVALIDr, INVALIDr, INVALIDr}}, 2974 { ET_S0_NORV_ERRf, NULL, {INVALIDr, INVALIDr, INVALIDr}}, 2975 { ET_S1_RBUS_PERRf, NULL, {ETU_S1_RBUS_PERR_INFOr, INVALIDr, INVALIDr}}, 2976 { ET_S0_RBUS_PERRf, NULL, {ETU_S0_RBUS_PERR_INFOr, INVALIDr, INVALIDr}}, 2977 /* PPA_COMPLETEf */ 2978 /* ET_INST_REQ_COMPLETEf */ 2979 /* MRST_COMPLETEf */ 2980 { CIF_LOST2_HITHRf, NULL, {INVALIDr, INVALIDr, INVALIDr}}, /* chk_LUREQFIFO */ 2981 { LUREQFIFOCOUNT_GTE_HITHRf, NULL, {INVALIDr, INVALIDr, INVALIDr}}, /* chk_LUREQFIFO */ 2982 { ADREQ1FIFO_OVERFLOWf, NULL, {INVALIDr, INVALIDr, INVALIDr}}, /* chk_ADREQ1FIFO */ 2983 { ADREQ1FIFO_FULLf, NULL, {INVALIDr, INVALIDr, INVALIDr}}, /* chk_ADREQ1FIFO */ 2984 { ADREQ0FIFO_OVERFLOWf, NULL, {INVALIDr, INVALIDr, INVALIDr}}, /* chk_ADREQ0FIFO */ 2985 { ADREQ0FIFO_FULLf, NULL, {INVALIDr, INVALIDr, INVALIDr}}, /* chk_ADREQ0FIFO */ 2986 { L2MODFIFO_OVERFLOWf, NULL, {INVALIDr, INVALIDr, INVALIDr}}, 2987 { L2MODFIFO_UNDERRUNf, NULL, {INVALIDr, INVALIDr, INVALIDr}}, 2988 { L2MODFIFO_NOTEMPTYf, NULL, {INVALIDr, INVALIDr, INVALIDr}}, 2989 { EXT_TCAM_SE_O_L_PINf, NULL, {INVALIDr, INVALIDr, INVALIDr}}, 2990 { INVALIDf} /* table terminator */ 2991 }; 2992 2993 STATIC _soc_esm_intr_reg_info_t _soc_tr2_es01_intr_reg_info[] = { 2994 { CIF_LOST2_HITHR1f, NULL, {INVALIDr, INVALIDr, INVALIDr}}, /* chk_ADREQ1FIFO */ 2995 { ADREQ1FIFOCOUNT_GTE_HITHRf, NULL, {INVALIDr, INVALIDr, INVALIDr}}, /* chk_ADREQ1FIFO */ 2996 { CIF_LOST2_HITHR0f, NULL, {INVALIDr, INVALIDr, INVALIDr}}, /* chk_ADREQ0FIFO */ 2997 { ADREQ0FIFOCOUNT_GTE_HITHRf, NULL, {INVALIDr, INVALIDr, INVALIDr}}, /* chk_ADREQ0FIFO */ 2998 { ADL3DST_SECf, NULL, {ES01_ADL3DST_SEC_INFOr, INVALIDr, INVALIDr}}, 2999 { ADL3DST_DEDf, NULL, {ES01_ADL3DST_DED_INFOr, INVALIDr, INVALIDr}}, 3000 { ADL3SRC_SECf, NULL, {ES01_ADL3SRC_SEC_INFOr, INVALIDr, INVALIDr}}, 3001 { ADL3SRC_DEDf, NULL, {ES01_ADL3SRC_DED_INFOr, INVALIDr, INVALIDr}}, 3002 { ADL2DST_SECf, NULL, {ES01_ADL2DST_SEC_INFOr, INVALIDr, INVALIDr}}, 3003 { ADL2DST_DEDf, NULL, {ES01_ADL2DST_DED_INFOr, INVALIDr, INVALIDr}}, 3004 { ADL2SRC_SECf, NULL, {ES01_ADL2SRC_SEC_INFOr, INVALIDr, INVALIDr}}, 3005 { ADL2SRC_DEDf, NULL, {ES01_ADL2SRC_DED_INFOr, INVALIDr, INVALIDr}}, 3006 { L2L3RSPFIFO_OVERFLOWf, NULL, {INVALIDr, INVALIDr, INVALIDr}}, /* chk_L2L3RSPFIFO */ 3007 { L2L3RSPFIFO_FULLf, NULL, {INVALIDr, INVALIDr, INVALIDr}}, /* chk_L2L3RSPFIFO */ 3008 { FP0RSPFIFO_OVERFLOWf, NULL, {INVALIDr, INVALIDr, INVALIDr}}, /* chk_FP0RSPFIFO */ 3009 { FP0RSPFIFO_FULLf, NULL, {INVALIDr, INVALIDr, INVALIDr}}, /* chk_FP0RSPFIFO */ 3010 { FP1RSPFIFO_OVERFLOWf, NULL, {INVALIDr, INVALIDr, INVALIDr}}, /* chk_FP1RSPFIFO */ 3011 { FP1RSPFIFO_FULLf, NULL, {INVALIDr, INVALIDr, INVALIDr}}, /* chk_FP1RSPFIFO */ 3012 { PKT_CNT_WRAPf, NULL, {ES01_PKT_CNT_WRAP_INFOr, INVALIDr, INVALIDr}}, 3013 { BYT_CNT_WRAPf, NULL, {ES01_BYT_CNT_WRAP_INFOr, INVALIDr, INVALIDr}}, 3014 { ADFPCNTR_SECf, NULL, {ES01_ADFPCNTR_SEC_INFOr, INVALIDr, INVALIDr}}, 3015 { ADFPCNTR_DEDf, NULL, {ES01_ADFPCNTR_DED_INFOr, INVALIDr, INVALIDr}}, 3016 { INVALIDf} /* table terminator */ 3017 }; 3018 3019 STATIC _soc_esm_intr_reg_info_t _soc_tr2_iesmif_intr_reg_info[] = { 3020 { AGE_IPFIX_ERRf, NULL, {IPFIX_AGE_CONTROLr, INVALIDr, INVALIDr}}, 3021 { FP_REFRESH_ERRf, NULL, {INVALIDr, INVALIDr, INVALIDr}}, 3022 { BK2BK_ESM_ELIGIBLEf, NULL, {INVALIDr, INVALIDr, INVALIDr}}, 3023 { ESU_ASF_HI_ACCUMf, NULL, {INVALIDr, INVALIDr, INVALIDr}}, /* chk_L2L3RSPFIFO, chk_FP0RSPFIFO, chk_FP1RSPFIFO */ 3024 { LUREQFIFO_FULLf, NULL, {INVALIDr, INVALIDr, INVALIDr}}, /* chk_LUREQFIFO */ 3025 { ECB_HI_ACCUMf, NULL, {INVALIDr, INVALIDr, INVALIDr}}, /* chk_ECBFIFO */ 3026 { ECB_FULLf, NULL, {INVALIDr, INVALIDr, INVALIDr}}, /* chk_ECBFIFO */ 3027 { DROPPED_CELLf, NULL, {INVALIDr, INVALIDr, INVALIDr}}, 3028 { CNP_ES_COUNT_WRAPf, NULL, {IESMIF_STATUS7r, INVALIDr, INVALIDr}}, 3029 { CNP_EXT_SEARCHf, NULL, {IESMIF_STATUS7r, INVALIDr, INVALIDr}}, 3030 { NEW_MAX_LATENCYf, NULL, {IESMIF_STATUS3r, INVALIDr, INVALIDr}}, 3031 { ECB_SEC_COUNT_WRAPf, NULL, {IESMIF_STATUS5r, INVALIDr, INVALIDr}}, 3032 { ECB_SEC_ERRf, NULL, 3033 { IESMIF_STATUS5r, IESMIF_ECB_ECC_STATUS_SBEr, 3034 IESMIF_ECB_SBE_SYNDROME12r}}, 3035 { ECB_DED_COUNT_WRAPf, NULL, {IESMIF_STATUS6r, INVALIDr, INVALIDr}}, 3036 { ECB_DED_ERRf, NULL, 3037 { IESMIF_STATUS6r, IESMIF_ECB_ECC_STATUS_DBEr, INVALIDr}}, 3038 { INVALIDf} /* table terminator */ 3039 }; 3040 3041 STATIC _soc_esm_intr_reg_info_t _soc_tr2_erb_intr_reg_info[] = { 3042 { EXT_LU_ERRf, NULL, {INVALIDr, INVALIDr, INVALIDr}}, 3043 { IPCF_PTR_MISMATCHf, NULL, 3044 { ERB_IPCF_PTR_MISMATCH_INFOr, INVALIDr, INVALIDr}}, 3045 { ERB_OVERFLOWf, NULL, {INVALIDr, INVALIDr, INVALIDr}}, /* chk_ERBFIFO */ 3046 { ERB_FULLf, NULL, {INVALIDr, INVALIDr, INVALIDr}}, /* chk_ERBFIFO */ 3047 { ERB_UNDERRUNf, NULL, {INVALIDr, INVALIDr, INVALIDr}}, /* chk_ERBFIFO */ 3048 { INVALIDf} /* table terminator */ 3049 }; 3050 3051 STATIC _soc_esm_intr_reg_info_t _soc_tr2_es01c_intr_reg_info[] = { 3052 { EXTFP_POLICY_SECf, NULL, 3053 { ES01C_EXTFP_POLICY_SEC_INFOr, INVALIDr, INVALIDr}}, 3054 { EXTFP_POLICY_DEDf, NULL, 3055 { ES01C_EXTFP_POLICY_DED_INFOr, INVALIDr, INVALIDr}}, 3056 { FPCREQFIFO_BK2BK_WRf, NULL, {INVALIDr, INVALIDr, INVALIDr}}, 3057 { FPCREQFIFO_OVERFLOWf, NULL, {INVALIDr, INVALIDr, INVALIDr}}, /*chk_FPCREQFIFO */ 3058 { FPCREQFIFO_FULLf, NULL, {INVALIDr, INVALIDr, INVALIDr}}, /*chk_FPCREQFIFO */ 3059 { FP1RSPFIFOCOUNT_GTE_HITHRf, NULL, {INVALIDr, INVALIDr, INVALIDr}}, /* chk_FP1RSPFIFO */ 3060 { FP0RSPFIFOCOUNT_GTE_HITHRf, NULL, {INVALIDr, INVALIDr, INVALIDr}}, /* chk_FP0RSPFIFO */ 3061 { L2L3RSPFIFOCOUNT_GTE_HITHRf, NULL, {INVALIDr, INVALIDr, INVALIDr}}, /* chk_L2L3RSPFIFO */ 3062 { INVALIDf} /* table terminator */ 3063 }; 3064 3065 STATIC struct { 3066 soc_reg_t enable_reg; 3067 soc_reg_t clear_reg; 3068 soc_reg_t status_reg; 3069 _soc_esm_intr_reg_info_t *reg_info; 3070 }_soc_tr2_esm_intr_info[] = { 3071 { ETU_INTR_ENABLEr, ETU_INTR_CLEARr, ETU_INTR_STATUSr, 3072 _soc_tr2_etu_intr_reg_info}, 3073 { ES01_INTR_ENABLEr, ES01_INTR_CLEARr, ES01_INTR_STATUSr, 3074 _soc_tr2_es01_intr_reg_info}, 3075 { IESMIF_INTR_ENABLEr, IESMIF_INTR_CLEARr, IESMIF_INTR_STATUSr, 3076 _soc_tr2_iesmif_intr_reg_info}, 3077 { ERB_INTR_ENABLEr, ERB_INTR_CLEARr, ERB_INTR_STATUSr, 3078 _soc_tr2_erb_intr_reg_info}, 3079 { ES01C_INTR_ENABLEr, ES01C_INTR_CLEARr, ES01C_INTR_STATUSr, 3080 _soc_tr2_es01c_intr_reg_info}, 3081 { INVALIDr, INVALIDr, INVALIDr} /* table terminator */ 3082 }; 3083 3084 STATIC int 3085 _soc_triumph2_esm_intr_enable(int unit, int enable) 3086 { 3087 int reg_index; 3088 uint32 addr, rval; 3089 soc_reg_t reg; 3090 _soc_esm_intr_reg_info_t *intr_reg_info; 3091 3092 if (SOC_CONTROL(unit)->tcam_info == NULL) { 3093 return SOC_E_NONE; 3094 } 3095 3096 for (reg_index = 0; 3097 _soc_tr2_esm_intr_info[reg_index].status_reg != INVALIDf; 3098 reg_index++) { 3099 reg = _soc_tr2_esm_intr_info[reg_index].status_reg; 3100 rval = 0; 3101 3102 for (intr_reg_info = _soc_tr2_esm_intr_info[reg_index].reg_info; 3103 intr_reg_info->error_field != INVALIDf; intr_reg_info++) { 3104 soc_reg_field_set(unit, reg, &rval, intr_reg_info->error_field, 3105 enable ? 1 : 0); 3106 } 3107 reg = _soc_tr2_esm_intr_info[reg_index].enable_reg; 3108 addr = soc_reg_addr(unit, reg, REG_PORT_ANY, 0); 3109 SOC_IF_ERROR_RETURN(soc_reg32_write(unit, addr, rval)); 3110 } 3111 3112 soc_intr_enable(unit, IRQ_CHIP_FUNC_3); 3113 3114 return SOC_E_NONE; 3115 } 3116 3117 int 3118 _soc_triumph2_esm_process_intr_status(int unit) 3119 { 3120 int reg_index, field_index, i; 3121 uint32 addr, status, rval; 3122 soc_reg_t reg, detail_reg; 3123 _soc_esm_intr_reg_info_t *intr_reg_info; 3124 soc_reg_info_t *reg_info; 3125 soc_field_info_t *field_info; 3126 char *msg; 3127 char line_buf[80], field_buf[80]; 3128 int line_len, field_len; 3129 3130 for (reg_index = 0; _soc_tr2_esm_intr_info[reg_index].clear_reg != INVALIDf; 3131 reg_index++) { 3132 reg = _soc_tr2_esm_intr_info[reg_index].status_reg; 3133 3134 addr = soc_reg_addr(unit, reg, REG_PORT_ANY, 0); 3135 SOC_IF_ERROR_RETURN(soc_reg32_read(unit, addr, &status)); 3136 for (intr_reg_info = _soc_tr2_esm_intr_info[reg_index].reg_info; 3137 intr_reg_info->error_field != INVALIDf; intr_reg_info++) { 3138 if (!soc_reg_field_get(unit, reg, status, 3139 intr_reg_info->error_field)) { 3140 continue; 3141 } 3142 msg = intr_reg_info->msg; 3143 if (msg == NULL) { 3144 msg = SOC_FIELD_NAME(unit, intr_reg_info->error_field); 3145 } 3146 LOG_ERROR(BSL_LS_SOC_COMMON, 3147 (BSL_META_U(unit, 3148 "unit %d %s asserted\n"), unit, msg)); 3149 3150 for (i = 0; intr_reg_info->detail_reg[i] != INVALIDr; i++) { 3151 detail_reg = intr_reg_info->detail_reg[i]; 3152 addr = soc_reg_addr(unit, detail_reg, REG_PORT_ANY, 0); 3153 SOC_IF_ERROR_RETURN(soc_reg32_read(unit, addr, &rval)); 3154 sal_sprintf(line_buf, "%s=0x%08x: ", 3155 SOC_REG_NAME(unit, detail_reg), rval); 3156 line_len = sal_strlen(line_buf); 3157 reg_info = &SOC_REG_INFO(unit, detail_reg); 3158 for (field_index = reg_info->nFields - 1; field_index >= 0; 3159 field_index--) { 3160 field_info = ®_info->fields[field_index]; 3161 sal_sprintf(field_buf, "%s%s=0x%x", 3162 field_index == reg_info->nFields - 1 ? 3163 "<" : " ", 3164 SOC_FIELD_NAME(unit, field_info->field), 3165 soc_reg_field_get(unit, detail_reg, rval, 3166 field_info->field)); 3167 field_len = sal_strlen(field_buf); 3168 if (line_len + field_len >= 64) { 3169 LOG_ERROR(BSL_LS_SOC_COMMON, 3170 (BSL_META_U(unit, 3171 " %s\n"), line_buf)); 3172 line_len = 0; 3173 } 3174 sal_sprintf(&line_buf[line_len], "%s", field_buf); 3175 line_len += field_len; 3176 } 3177 LOG_ERROR(BSL_LS_SOC_COMMON, 3178 (BSL_META_U(unit, 3179 " %s>\n"), line_buf)); 3180 } 3181 } 3182 reg = _soc_tr2_esm_intr_info[reg_index].clear_reg; 3183 addr = soc_reg_addr(unit, reg, REG_PORT_ANY, 0); 3184 SOC_IF_ERROR_RETURN(soc_reg32_write(unit, addr, 0xffffffff)); 3185 } 3186 3187 return SOC_E_NONE; 3188 } 3189 3190 void 3191 soc_triumph2_esm_intr_status(void *unit_vp, void *d1, void *d2, 3192 void *d3, void *d4) 3193 { 3194 int unit = PTR_TO_INT(unit_vp); 3195 3196 _soc_triumph2_esm_process_intr_status(unit); 3197 soc_intr_enable(unit, IRQ_CHIP_FUNC_3); 3198 } 3199 3200 int 3201 soc_triumph2_pipe_mem_clear(int unit) 3202 { 3203 uint32 rval; 3204 int pipe_init_usec; 3205 soc_timeout_t to; 3206 3207 /* 3208 * Reset the IPIPE and EPIPE block 3209 */ 3210 rval = 0; 3211 SOC_IF_ERROR_RETURN(WRITE_ING_HW_RESET_CONTROL_1r(unit, rval)); 3212 soc_reg_field_set(unit, ING_HW_RESET_CONTROL_2r, &rval, RESET_ALLf, 1); 3213 soc_reg_field_set(unit, ING_HW_RESET_CONTROL_2r, &rval, VALIDf, 1); 3214 /* Set count to # entries in largest IPIPE table, L2_ENTRYm */ 3215 soc_reg_field_set(unit, ING_HW_RESET_CONTROL_2r, &rval, COUNTf, 0x8000); 3216 SOC_IF_ERROR_RETURN(WRITE_ING_HW_RESET_CONTROL_2r(unit, rval)); 3217 3218 rval = 0; 3219 SOC_IF_ERROR_RETURN(WRITE_EGR_HW_RESET_CONTROL_0r(unit, rval)); 3220 soc_reg_field_set(unit, EGR_HW_RESET_CONTROL_1r, &rval, RESET_ALLf, 1); 3221 soc_reg_field_set(unit, EGR_HW_RESET_CONTROL_1r, &rval, VALIDf, 1); 3222 /* Set count to # entries in largest EPIPE table, EGR_L3_NEXT_HOPm */ 3223 soc_reg_field_set(unit, EGR_HW_RESET_CONTROL_1r, &rval, COUNTf, 0x4000); 3224 SOC_IF_ERROR_RETURN(WRITE_EGR_HW_RESET_CONTROL_1r(unit, rval)); 3225 3226 /* For simulation, set timeout to 10 sec. Otherwise, timeout = 50 ms */ 3227 if (SAL_BOOT_SIMULATION) { 3228 pipe_init_usec = 10000000; 3229 } else { 3230 pipe_init_usec = 50000; 3231 } 3232 soc_timeout_init(&to, pipe_init_usec, 0); 3233 3234 /* Wait for IPIPE memory initialization done. */ 3235 do { 3236 SOC_IF_ERROR_RETURN(READ_ING_HW_RESET_CONTROL_2r(unit, &rval)); 3237 if (soc_reg_field_get(unit, ING_HW_RESET_CONTROL_2r, rval, DONEf)) { 3238 break; 3239 } 3240 if (soc_timeout_check(&to)) { 3241 LOG_WARN(BSL_LS_SOC_COMMON, 3242 (BSL_META_U(unit, 3243 "unit %d : ING_HW_RESET timeout\n"), unit)); 3244 break; 3245 } 3246 }while (TRUE); 3247 3248 /* Wait for EPIPE memory initialization done. */ 3249 do { 3250 SOC_IF_ERROR_RETURN(READ_EGR_HW_RESET_CONTROL_1r(unit, &rval)); 3251 if (soc_reg_field_get(unit, EGR_HW_RESET_CONTROL_1r, rval, DONEf)) { 3252 break; 3253 } 3254 if (soc_timeout_check(&to)) { 3255 LOG_WARN(BSL_LS_SOC_COMMON, 3256 (BSL_META_U(unit, 3257 "unit %d : EGR_HW_RESET timeout\n"), unit)); 3258 break; 3259 } 3260 }while (TRUE); 3261 3262 rval = 0; 3263 SOC_IF_ERROR_RETURN(WRITE_ING_HW_RESET_CONTROL_2r(unit, rval)); 3264 SOC_IF_ERROR_RETURN(WRITE_EGR_HW_RESET_CONTROL_1r(unit, rval)); 3265 3266 SOC_IF_ERROR_RETURN 3267 (soc_mem_clear(unit, SPORT_EHG_RX_TUNNEL_DATAm, COPYNO_ALL, TRUE)); 3268 SOC_IF_ERROR_RETURN 3269 (soc_mem_clear(unit, SPORT_EHG_RX_TUNNEL_MASKm, COPYNO_ALL, TRUE)); 3270 SOC_IF_ERROR_RETURN 3271 (soc_mem_clear(unit, SPORT_EHG_TX_TUNNEL_DATAm, COPYNO_ALL, TRUE)); 3272 if (SOC_IS_TRIUMPH2(unit)) { 3273 SOC_IF_ERROR_RETURN 3274 (soc_mem_clear(unit, GPORT_EHG_RX_TUNNEL_DATAm, COPYNO_ALL, TRUE)); 3275 SOC_IF_ERROR_RETURN 3276 (soc_mem_clear(unit, GPORT_EHG_RX_TUNNEL_MASKm, COPYNO_ALL, TRUE)); 3277 SOC_IF_ERROR_RETURN 3278 (soc_mem_clear(unit, GPORT_EHG_TX_TUNNEL_DATAm, COPYNO_ALL, TRUE)); 3279 } 3280 SOC_IF_ERROR_RETURN 3281 (soc_mem_clear(unit, XPORT_EHG_RX_TUNNEL_DATAm, COPYNO_ALL, TRUE)); 3282 SOC_IF_ERROR_RETURN 3283 (soc_mem_clear(unit, XPORT_EHG_RX_TUNNEL_MASKm, COPYNO_ALL, TRUE)); 3284 SOC_IF_ERROR_RETURN 3285 (soc_mem_clear(unit, XPORT_EHG_TX_TUNNEL_DATAm, COPYNO_ALL, TRUE)); 3286 SOC_IF_ERROR_RETURN 3287 (soc_mem_clear(unit, XQPORT_EHG_RX_TUNNEL_DATAm, COPYNO_ALL, TRUE)); 3288 SOC_IF_ERROR_RETURN 3289 (soc_mem_clear(unit, XQPORT_EHG_RX_TUNNEL_MASKm, COPYNO_ALL, TRUE)); 3290 SOC_IF_ERROR_RETURN 3291 (soc_mem_clear(unit, XQPORT_EHG_TX_TUNNEL_DATAm, COPYNO_ALL, TRUE)); 3292 3293 SOC_IF_ERROR_RETURN(soc_mem_clear(unit, IARB_TDM_TABLEm, COPYNO_ALL, TRUE)); 3294 SOC_IF_ERROR_RETURN(soc_mem_clear(unit, ARB_TDM_TABLEm, COPYNO_ALL, TRUE)); 3295 3296 /* LMEP table is not properly handled by reset control */ 3297 SOC_IF_ERROR_RETURN(soc_mem_clear(unit, LMEPm, COPYNO_ALL, TRUE)); 3298 3299 return SOC_E_NONE; 3300 } 3301 3302 uint32 tdmb634a[114] = {26, 2,27,14,28,30,29,26,34,27, 3303 3,28,15,29,26,38,27,42,28,4, 3304 29,26,16,27,46,28,50,29,26,5, 3305 27,17,28,31,29,26,35,27,6,28, 3306 18,29,26,39,27,43,28,7,29,26, 3307 19,27,47,28,51,29,1,26,8,27, 3308 20,28,32,29,26,36,27,9,28,21, 3309 29,26,40,27,44,28,10,29,26,22, 3310 27,48,28,52,29,26,11,27,23,28, 3311 33,29,26,37,27,12,28,24,29,26, 3312 41,27,45,28,13,29,26,25,27,49, 3313 28,53,29,0}; 3314 3315 uint32 tdmb634abp[114] = {26,2,27,14,28,30,29,26,34,27, 3316 3,28,15,29,26,38,27,42,28,4, 3317 29,26,16,27,46,28,50,29,26,5, 3318 27,17,28,31,29,26,35,27,6,28, 3319 18,29,26,39,27,43,28,7,29,26, 3320 19,27,47,28,51,1,29,26,8,27,20, 3321 28,32,29,26,36,27,9,28,21,29, 3322 26,40,27,44,28,10,29,26,22,27, 3323 48,28,52,29,26,11,27,23,28,33, 3324 29,26,37,27,12,28,24,29,26,41, 3325 27,45,28,13,29,26,25,27,49,28, 3326 53,0,29}; 3327 3328 uint32 eelist634afp[55] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 3329 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 3330 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 3331 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 3332 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 3333 1, 1, 1, 1, 0}; 3334 3335 uint32 eelist634a[55] = {1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 3336 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3337 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 3338 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3339 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3340 0, 0, 0, 0, 0}; 3341 3342 uint32 tdmb634b[110] = {2,26,30,27,14,28,34,29,54,3,26, 3343 38,27,15,28,42,29,54,4,26,46,27, 3344 16,28,50,29,54,5,26,31,27,17,28, 3345 35,29,54,6,26,39,27,18,28,43,29, 3346 54,7,26,47,27,19,28,51,29,1,54, 3347 8,26,32,27,20,28,36,29,54,9,26, 3348 40,27,21,28,44,29,54,10,26,48,27, 3349 22,28,52,29,54,11,26,33,27,23,28, 3350 37,29,54,12,26,41,27,24,28,45,29, 3351 54,13,26,49,27,25,28,53,29,0,54}; 3352 3353 uint32 tdmb634bbp[110] = {2,26,30,27,14,28,34,29,54,3,26, 3354 38,27,15,28,42,29,54,4,26,46,27, 3355 16,28,50,29,54,5,26,31,27,17,28, 3356 35,29,54,6,26,39,27,18,28,43,29, 3357 54,7,26,47,27,19,28,51,29,54,1,8, 3358 26,32,27,20,28,36,29,54,9,26,40, 3359 27,21,28,44,29,54,10,26,48,27,22, 3360 28,52,29,54,11,26,33,27,23,28,37, 3361 29,54,12,26,41,27,24,28,45,29,54, 3362 13,26,49,27,25,28,53,29,54,0}; 3363 3364 uint32 eelist634bfp[55] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 3365 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 3366 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 3367 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 3368 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 3369 1, 1, 1, 1, 0}; 3370 3371 uint32 eelist634b[55] = {1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 3372 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3373 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 3374 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3375 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3376 0, 0, 0, 0, 0}; 3377 3378 uint32 tdmb634c[110] = {2,26,30,27,14,26,34,27,54,3,26,38, 3379 27,15,26,42,27,54,4,26,46,27,16, 3380 26,50,27,54,5,26,31,27,17,26,35, 3381 27,54,6,26,39,27,18,26,43,27,54,7, 3382 26,47,27,19,26,51,27,1,54,8,26,32, 3383 27,20,26,36,27,54,9,26,40,27,21,26, 3384 44,27,54,10,26,48,27,22,26,52,27,54, 3385 11,26,33,27,23,26,37,27,54,12,26,41, 3386 27,24,26,45,27,54,13,26,49,27,25,26, 3387 53,27,0,54}; 3388 3389 uint32 tdmb634cbp[110] = {2,26,30,27,14,26,34,27,54,3,26,38, 3390 27,15,26,42,27,54,4,26,46,27,16,26, 3391 50,27,54,5,26,31,27,17,26,35,27,54, 3392 6,26,39,27,18,26,43,27,54,7,26,47, 3393 27,19,26,51,27,54,1,8,26,32,27,20, 3394 26,36,27,54,9,26,40,27,21,26,44,27, 3395 54,10,26,48,27,22,26,52,27,54,11,26, 3396 33,27,23,26,37,27,54,12,26,41,27,24, 3397 26,45,27,54,13,26,49,27,25,26,53,27, 3398 54,0}; 3399 3400 uint32 eelist634cfp[55] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 3401 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 3402 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 3403 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 3404 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 3405 1, 1, 1, 1, 0}; 3406 3407 uint32 eelist634c[55] = {1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 3408 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3409 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 3410 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3411 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3412 0, 0, 0, 0, 0}; 3413 3414 uint32 tdmb636a[114] = {26,2,27,30,28,42,29,26,50,27,3, 3415 28,34,29,26,42,27,50,28,4,29,26, 3416 38,27,42,28,50,29,26,5,27,31,28, 3417 42,29,26,50,27,6,28,35,29,26,42, 3418 27,50,28,7,29,26,39,27,42,28,50, 3419 29,1,26,8,27,32,28,42,29,26,50,27, 3420 9,28,36,29,26,42,27,50,28,10,29, 3421 26,40,27,42,28,50,29,26,11,27,33, 3422 28,42,29,26,50,27,12,28,37,29,26, 3423 42,27,50,28,13,29,26,41,27,42,28, 3424 50,29,0}; 3425 3426 uint32 tdmb636abp[114] = {26,2,27,30,28,42,29,26,50,27,3, 3427 28,34,29,26,42,27,50,28,4,29,26, 3428 38,27,42,28,50,29,26,5,27,31,28, 3429 42,29,26,50,27,6,28,35,29,26,42, 3430 27,50,28,7,29,26,39,27,42,28,50, 3431 1,29,26,8,27,32,28,42,29,26,50, 3432 27,9,28,36,29,26,42,27,50,28,10, 3433 29,26,40,27,42,28,50,29,26,11,27, 3434 33,28,42,29,26,50,27,12,28,37,29, 3435 26,42,27,50,28,13,29,26,41,27,42, 3436 28,50,0,29}; 3437 3438 uint32 eelist636afp[55] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 3439 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 3440 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3441 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 3442 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 3443 1, 0, 0, 0, 0}; 3444 3445 uint32 eelist636a[55] = {1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 3446 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3447 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 3448 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3449 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3450 0, 0, 0, 0, 0}; 3451 3452 uint32 tdmb636b[110] = {2,26,42,27,30,26,50,27,54,3,26,42, 3453 27,34,26,50,27,54,4,26,42,27,38, 3454 26,50,27,54, 5,26,42,27,31,26,50, 3455 27,54,6,26,42,27,35,26,50,27,54,7, 3456 26,42,27,39,26,50,27,1,54,8,26,42, 3457 27,32,26,50,27,54,9,26,42,27,36,26, 3458 50,27,54,10,26,42,27,40,26,50,27,54, 3459 11,26,42,27,33,26,50,27,54,12,26,42, 3460 27,37,26,50,27,54,13,26,42,27,41,26, 3461 50,27,0,54}; 3462 3463 uint32 tdmb636bbp[110] = {2,26,42,27,30,26,50,27,54,3,26,42, 3464 27,34,26,50,27,54,4,26,42,27,38,26, 3465 50,27,54,5,26,42,27,31,26,50,27,54, 3466 6,26,42,27,35,26,50,27,54,7,26,42, 3467 27,39,26,50,27,54,1,8,26,42,27,32, 3468 26,50,27,54,9,26,42,27,36,26,50,27, 3469 54,10,26,42,27,40,26,50,27,54,11,26, 3470 42,27,33,26,50,27,54,12,26,42,27,37, 3471 26,50,27,54,13,26,42,27,41,26,50,27, 3472 54,0}; 3473 3474 uint32 eelist636bfp[55] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 3475 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 3476 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3477 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 3478 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 3479 1, 0, 0, 0, 0}; 3480 3481 uint32 eelist636b[55] = {1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 3482 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3483 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 3484 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3485 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3486 0, 0, 0, 0, 0}; 3487 3488 uint32 tdmb636c[110] = {2,26,42,27,30,28,50,29,54,3,26, 3489 42,27,34,28,50,29,54,4,26,42,27, 3490 38,28,50,29,54,5,26,42,27,31,28, 3491 50,29,54,6,26,42,27,35,28,50,29, 3492 54,7,26,42,27,39,28,50,29,1,54,8, 3493 26,42,27,32,28,50,29,54,9,26,42, 3494 27,36,28,50,29,54,10,26,42,27,40, 3495 28,50,29,54,11,26,42,27,33,28,50, 3496 29,54,12,26,42,27,37,28,50,29,54, 3497 13,26,42,27,41,28,50,29,0,54}; 3498 3499 uint32 tdmb636cbp[110] = {2,26,42,27,30,28,50,29,54,3,26, 3500 42,27,34,28,50,29,54,4,26,42,27, 3501 38,28,50,29,54,5,26,42,27,31,28, 3502 50,29,54,6,26,42,27,35,28,50,29, 3503 54,7,26,42,27,39,28,50,29,54,1,8, 3504 26,42,27,32,28,50,29,54,9,26,42, 3505 27,36,28,50,29,54,10,26,42,27,40, 3506 28,50,29,54,11,26,42,27,33,28,50, 3507 29,54,12,26,42,27,37,28,50,29,54, 3508 13,26,42,27,41,28,50,29,54,0}; 3509 3510 uint32 eelist636cfp[55] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 3511 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 3512 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3513 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 3514 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 3515 1, 0, 0, 0, 0}; 3516 3517 uint32 eelist636c[55] = {1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 3518 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3519 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 3520 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3521 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3522 0, 0, 0, 0, 0}; 3523 3524 uint32 tdmb638a[114] = {26,30,27,38,28,42,29,26,50,27,30, 3525 28,38,29,26,42,27,50,28,30,29,26, 3526 38,27,42,28,50,29,26,30,27,38,28, 3527 42,29,26,50,27,30,28,38,29,26,42, 3528 27,50,28,30,29,26,38,27,42,28,50, 3529 29,1,26,30,27,38,28,42,29,26,50, 3530 27,30,28,38,29,26,42,27,50,28,30, 3531 29,26,38,27,42,28,50,29,26,30,27, 3532 38,28,42,29,26,50,27,30,28,38,29, 3533 26,42,27,50,28,30,29,26,38,27,42, 3534 28,50,29,0}; 3535 3536 uint32 tdmb638abp[114] = {26,30,27,38,28,42,29,26,50,27,30, 3537 28,38,29,26,42,27,50,28,30,29,26, 3538 38,27,42,28,50,29,26,30,27,38,28, 3539 42,29,26,50,27,30,28,38,29,26,42, 3540 27,50,28,30,29,26,38,27,42,28,50, 3541 1,29,26,30,27,38,28,42,29,26,50, 3542 27,30,28,38,29,26,42,27,50,28,30, 3543 29,26,38,27,42,28,50,29,26,30,27, 3544 38,28,42,29,26,50,27,30,28,38,29, 3545 26,42,27,50,28,30,29,26,38,27,42, 3546 28,50,0,29}; 3547 3548 uint32 eelist638afp[55] = {1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 3549 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3550 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3551 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 3552 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 3553 1, 0, 0, 0, 0}; 3554 3555 uint32 eelist638a[55] = {1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 3556 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3557 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 3558 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3559 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3560 0, 0, 0, 0, 0}; 3561 3562 uint32 tdmb638b[110] = {30,26,38,27,42,28,50,29,54,30,26, 3563 38,27,42,28,50,29,54,30,26,38,27, 3564 42,28,50,29,54,30,26,38,27,42,28, 3565 50,29,54,30,26,38,27,42,28,50,29, 3566 54,30,26,38,27,42,28,50,29,1,54,30, 3567 26,38,27,42,28,50,29,54,30,26,38, 3568 27,42,28,50,29,54,30,26,38,27,42, 3569 28,50,29,54,30,26,38,27,42,28,50, 3570 29,54,30,26,38,27,42,28,50,29,54, 3571 30,26,38,27,42,28,50,29,0,54}; 3572 3573 uint32 tdmb638bbp[110] = {30,26,38,27,42,28,50,29,54,30,26, 3574 38,27,42,28,50,29,54,30,26,38,27, 3575 42,28,50,29,54,30,26,38,27,42,28, 3576 50,29,54,30,26,38,27,42,28,50,29, 3577 54,30,26,38,27,42,28,50,29,54,1, 3578 30,26,38,27,42,28,50,29,54,30,26, 3579 38,27,42,28,50,29,54,30,26,38,27, 3580 42,28,50,29,54,30,26,38,27,42,28, 3581 50,29,54,30,26,38,27,42,28,50,29, 3582 54,30,26,38,27,42,28,50,29,54,0}; 3583 3584 uint32 eelist638bfp[55] = {1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 3585 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3586 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3587 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 3588 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 3589 1, 0, 0, 0, 0}; 3590 3591 uint32 eelist638b[55] = {1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 3592 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3593 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 3594 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3595 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3596 0, 0, 0, 0, 0}; 3597 3598 uint32 tdmb638c[110] = {30,26,38,27,42,26,50,27,54,30,26, 3599 38,27,42,26,50,27,54,30,26,38,27, 3600 42,26,50,27,54,30,26,38,27,42,26, 3601 50,27,54,30,26,38,27,42,26,50,27, 3602 54,30,26,38,27,42,26,50,27,1,54, 3603 30,26,38,27,42,26,50,27,54,30,26, 3604 38,27,42,26,50,27,54,30,26,38,27, 3605 42,26,50,27,54,30,26,38,27,42,26, 3606 50,27,54,30,26,38,27,42,26,50,27, 3607 54,30,26,38,27,42,26,50,27,0,54}; 3608 3609 uint32 tdmb638cbp[110] = {30,26,38,27,42,26,50,27,54,30, 3610 26,38,27,42,26,50,27,54,30,26, 3611 38,27,42,26,50,27,54,30,26,38, 3612 27,42,26,50,27,54,30,26,38,27, 3613 42,26,50,27,54,30,26,38,27,42, 3614 26,50,27,54,1,30,26,38,27,42,26, 3615 50,27,54,30,26,38,27,42,26,50, 3616 27,54,30,26,38,27,42,26,50,27, 3617 54,30,26,38,27,42,26,50,27,54, 3618 30,26,38,27,42,26,50,27,54,30, 3619 26,38,27,42,26,50,27,54,0}; 3620 3621 uint32 eelist638cfp[55] = {1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 3622 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3623 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3624 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 3625 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 3626 1, 0, 0, 0, 0}; 3627 3628 uint32 eelist638c[55] = {1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 3629 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3630 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 3631 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3632 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3633 0, 0, 0, 0, 0}; 3634 3635 uint32 tdmb639a[114] = {2,26,54,27,14,28,29,30,50,3,38,42, 3636 26,15,27,28,29,30,4,50,38,42,16,26, 3637 27,54,28,29,5,30,50,38,17,42,54,26, 3638 27,6,28,29,30,18,50,38,42,26,7,54, 3639 27,28,19,29,30,50,38,42,1,8,26,54, 3640 27,20,28,29,30,50,9,38,42,26,21,27, 3641 28,29,30,10,50,38,42,22,26,27,54,28, 3642 29,11,30,50,38,23,42,54,26,27,12,28, 3643 29,30,24,50,38,42,26,13,54,27,28,25, 3644 29,30,50,38,42,0}; 3645 3646 uint32 tdmb639b[114] = {2,29,54,27,14,28,46,30,50,3,38,42, 3647 29,15,27,28,47,30,4,50,38,42,16,29, 3648 27,54,28,48,5,30,50,38,17,42,54,29, 3649 27,6,28,49,30,18,50,38,42,29,7,54, 3650 27,28,19,63,30,50,38,42,1,8,29,54, 3651 27,20,28,63,30,50,9,38,42,29,21,27, 3652 28,63,30,10,50,38,42,22,29,27,54,28, 3653 63,11,30,50,38,23,42,54,29,27,12,28, 3654 63,30,24,50,38,42,29,13,54,27,28,25, 3655 63,30,50,38,42,0}; 3656 3657 uint32 tdmb685[228] = {30,26,34,27,38,28,42,46,29,50,26, 3658 31,27,35,39,28,43,29,47,26,51,32, 3659 27,36,28,40,29,54,44,26,48,27,52, 3660 28,33,37,29,41,26,45,27,49,53,28, 3661 30,29,34,26,38,42,27,46,28,50,29, 3662 54,1,31,26,35,27,39,28,43,47,29,51, 3663 26,32,27,36,40,28,44,29,48,26,52, 3664 33,27,37,28,41,29,54,45,26,49,27, 3665 53,28,30,34,29,38,26,42,27,46,50, 3666 28,31,29,35,26,39,43,27,47,28,51, 3667 29,54,0,32,26,36,27,40,28,44,48,29, 3668 52,26,33,27,37,41,28,45,29,49,26, 3669 53,30,27,34,28,38,29,54,42,26,46, 3670 27,50,28,31,35,29,39,26,43,27,47, 3671 51,28,32,29,36,26,40,44,27,48,28, 3672 52,29,54,1,33,26,37,27,41,28,45,49, 3673 29,53,26,30,27,34,38,28,42,29,46, 3674 26,50,31,27,35,28,39,29,54,43,26, 3675 47,27,51,28,32,36,29,40,26,44,27, 3676 48,52,28,33,29,37,26,41,45,27,49, 3677 28,53,29,54,0}; 3678 3679 uint32 tdmb521a[114] = {2,26,54,27,14,28,29,26,27,3,28, 3680 29,26,15,27,28,29,26,4,27,28,29, 3681 16,26,27,54,28,29,5,26,27,28,17, 3682 29,54,26,27,6,28,29,26,18,27,28, 3683 29,26,7,54,27,28,19,29,26,27,28, 3684 29,1,8,26,54,27,20,28,29,26,27, 3685 9,28,29,26,21,27,28,29,26,10,27, 3686 28,29,22,26,27,54,28,29,11,26,27, 3687 28,23,29,54,26,27,12,28,29,26,24, 3688 27,28,29,26,13,54,27,28,25,29,26, 3689 27,28,29,0}; 3690 3691 uint32 tdmb521b[110] = {2,26,27,28,14,26,27,29,54,3,26, 3692 27,28,15,26,27,29,54,4,26,27,28, 3693 16,26,27,29,54,5,26,27,28,17,26, 3694 27,29,54,6,26,27,28,18,26,27,29, 3695 54,7,26,27,28,19,26,27,29,54,1,8, 3696 26,27,28,20,26,27,29,54,9,26,27, 3697 28,21,26,27,29,54,10,26,27,28,22, 3698 26,27,29,54,11,26,27,28,23,26,27, 3699 29,54,12,26,27,28,24,26,27,29,54, 3700 13,26,27,28,25,26,27,29,54,0}; 3701 3702 uint32 tdmb524a[114] = {30,26,54,27,34,28,29,26,27,38,28, 3703 29,26,42,27,28,29,26,46,27,28,29, 3704 50,26,27,54,28,29,31,26,27,28,35, 3705 29,54,26,27,39,28,29,26,43,27,28, 3706 29,26,47,54,27,28,51,29,26,27,28, 3707 29,1,32,26,54,27,36,28,29,26,27, 3708 40,28,29,26,44,27,28,29,26,48,27, 3709 28,29,52,26,27,54,28,29,33,26,27, 3710 28,37,29,54,26,27,41,28,29,26,45, 3711 27,28,29,26,49,54,27,28,53,29,26, 3712 27,28,29,0}; 3713 3714 uint32 tdmb524b[110] = {30,26,27,28,42,26,27,29,54,34,26, 3715 27,28,46,26,27,29,54,38,26,27,28, 3716 50,26,27,29,54,31,26,27,28,43,26, 3717 27,29,54,35,26,27,28,47,26,27,29, 3718 54,39,26,27,28,51,26,27,29,54,1, 3719 32,26,27,28,44,26,27,29,54,36,26, 3720 27,28,48,26,27,29,54,40,26,27,28, 3721 52,26,27,29,54,33,26,27,28,45,26, 3722 27,29,54,37,26,27,28,49,26,27,29, 3723 54,41,26,27,28,53,26,27,29,54,0}; 3724 3725 uint32 tdmb526a[110] = {2,26,27,28,14,29,46,50,38,3,26,27, 3726 28,15,29,46,50,54,4,26,27,28,16,29, 3727 46,50,54,5,26,27,28,17,29,46,50,39, 3728 6,26,27,28,18,29,46,50,54,7,26,27, 3729 28,19,29,46,50,54,1,8,26,27,28,20, 3730 29,46,50,40,9,26,27,28,21,29,46,50, 3731 54,10,26,27,28,22,29,46,50,54,11,26, 3732 27,28,23,29,46,50,41,12,26,27,28,24, 3733 29,46,50,54,13,26,27,28,25,29,46,50,54,0}; 3734 3735 uint32 tdmb526b[114] = {26,2,27,46,28,14,29,26,50,27,3,28, 3736 46,29,26,15,27,50,28,4,29,26,46,27, 3737 16,28,50,29,26,5,27,46,28,17,29,26, 3738 50,27,6,28,46,29,26,18,27,50,28,7, 3739 29,26,46,27,19,28,50,29,1,26,8,27, 3740 46,28,20,29,26,50,27,9,28,46,29,26, 3741 21,27,50,28,10,29,26,46,27,22,28, 3742 50,29,26,11,27,46,28,23,29,26,50, 3743 27,12,28,46,29,26,24,27,50,28,13, 3744 29,26,46,27,25,28,50,29,0}; 3745 #if defined (SER_TR_TEST_SUPPORT) 3746 soc_ser_test_functions_t ser_test_fun; 3747 #endif 3748 3749 int 3750 soc_triumph2_misc_init(int unit) 3751 { 3752 uint16 dev_id; 3753 uint8 rev_id; 3754 uint32 rval, prev_reg_addr; 3755 uint64 reg64; 3756 int port; 3757 uint32 misc_cfg; 3758 uint32 mode; 3759 uint32 *arr, *eelist = NULL; 3760 int i, tdm_size, has_sport = TRUE; 3761 int front_panel_esm = TRUE; 3762 int divisor, dividend; 3763 uint64 multipass, bm64; 3764 iarb_tdm_table_entry_t iarb_tdm; 3765 arb_tdm_table_entry_t arb_tdm; 3766 soc_field_t fields[3]; 3767 uint32 values[3]; 3768 3769 SOC_IF_ERROR_RETURN(READ_IARB_TDM_CONTROLr(unit, &rval)); 3770 soc_reg_field_set(unit, IARB_TDM_CONTROLr, &rval, DISABLEf, 0); 3771 SOC_IF_ERROR_RETURN(WRITE_IARB_TDM_CONTROLr(unit, rval)); 3772 3773 soc_cm_get_id(unit, &dev_id, &rev_id); 3774 if (soc_feature(unit, soc_feature_esm_support)) { 3775 front_panel_esm = soc_property_get(unit, spn_FRONT_PANEL_ESM, TRUE); 3776 } 3777 3778 /* Turn off SER protection clearing memories */ 3779 /* coverity[result_independent_of_operands] */ 3780 SOC_IF_ERROR_RETURN(WRITE_CMIC_SER_PROTECT_ADDR_RANGE_VALIDr(unit, 0)); 3781 3782 if (!SOC_IS_RELOADING(unit) && !SOC_WARM_BOOT(unit)) { 3783 /* Clear IPIPE/EIPIE Memories */ 3784 SOC_IF_ERROR_RETURN(soc_triumph2_pipe_mem_clear(unit)); 3785 } 3786 #if defined(SER_TR_TEST_SUPPORT) 3787 /*Initialize chip-specific functions for SER testing*/ 3788 memset(&ser_test_fun, 0, sizeof(soc_ser_test_functions_t)); 3789 ser_test_fun.inject_error_f = &soc_tr2_ser_inject_error; 3790 ser_test_fun.test_mem = &soc_tr2_ser_mem_test; 3791 ser_test_fun.test = &soc_tr2_ser_test; 3792 ser_test_fun.parity_control = &_ser_test_parity_control_pci_write; 3793 soc_ser_test_functions_register(unit, &ser_test_fun); 3794 #endif /*defined(SER_TR_TEST_SUPPORT*/ 3795 switch (dev_id) { 3796 case BCM56634_DEVICE_ID: 3797 /* Fall through */ 3798 case BCM56538_DEVICE_ID: 3799 if (soc_property_get(unit, spn_BCM56634_48G_4X12, 0) || 3800 soc_property_get(unit, spn_BCM56538_48G_4X12, 0)) { 3801 /* 48x1GE + 4x12HG + 1x12G(loopback) */ 3802 tdm_size = 110; 3803 if (front_panel_esm) { 3804 arr = tdmb634b; 3805 eelist = eelist634bfp; 3806 } else { 3807 arr = tdmb634bbp; 3808 eelist = eelist634b; 3809 } 3810 } else if (soc_property_get(unit, spn_BCM56634_48G_2X24, 0) || 3811 soc_property_get(unit, spn_BCM56538_48G_2X24, 0)) { 3812 /* 48x1GE + 2x24HG + 1x12G(loopback) */ 3813 tdm_size = 110; 3814 if (front_panel_esm) { 3815 arr = tdmb634c; 3816 eelist = eelist634cfp; 3817 } else { 3818 arr = tdmb634cbp; 3819 eelist = eelist634c; 3820 } 3821 } else { 3822 /* 48x1GE + 4x16HG */ 3823 tdm_size = 114; 3824 if (front_panel_esm) { 3825 arr = tdmb634a; 3826 eelist = eelist634afp; 3827 } else { 3828 arr = tdmb634abp; 3829 eelist = eelist634a; 3830 } 3831 } 3832 break; 3833 case BCM56636_DEVICE_ID: 3834 if (soc_property_get(unit, spn_BCM56636_24G_6X12, 0)) { 3835 /* 24x1GE + 6x12HG + 1x12G(loopback) */ 3836 tdm_size = 110; 3837 if (front_panel_esm) { 3838 arr = tdmb636c; 3839 eelist = eelist636cfp; 3840 } else { 3841 arr = tdmb636cbp; 3842 eelist = eelist636c; 3843 } 3844 } else if (soc_property_get(unit, spn_BCM56636_2X12_2X24, 0)) { 3845 /* 24x1GE + 2x12HG + 2x24G(loopback) */ 3846 tdm_size = 110; 3847 if (front_panel_esm) { 3848 arr = tdmb636b; 3849 eelist = eelist636bfp; 3850 } else { 3851 arr = tdmb636bbp; 3852 eelist = eelist636b; 3853 } 3854 } else { 3855 /* 24x1GE + 2x12HG + 4x16HG */ 3856 tdm_size = 114; 3857 if (front_panel_esm) { 3858 arr = tdmb636a; 3859 eelist = eelist636afp; 3860 } else { 3861 arr = tdmb636abp; 3862 eelist = eelist636a; 3863 } 3864 } 3865 SOC_IF_ERROR_RETURN 3866 (soc_reg_field32_modify(unit, EDATABUF_XQP_FLEXPORT_CONFIGr, 3867 REG_PORT_ANY, EGR_XQP_PORT_INT_RESETf, 3868 0x28)); 3869 SOC_IF_ERROR_RETURN 3870 (soc_reg_field32_modify(unit, EDATABUF_XQP_FLEXPORT_CONFIGr, 3871 REG_PORT_ANY, EGR_XQP_PORT_MODEf, 0x28)); 3872 SOC_IF_ERROR_RETURN 3873 (soc_reg_field32_modify(unit, EDATABUF_XQP_FLEXPORT_CONFIGr, 3874 REG_PORT_ANY, EGR_XQP_PORT_INT_RESETf, 0)); 3875 soc_port_cmap_set(unit, 42, SOC_CTR_TYPE_XE); 3876 soc_port_cmap_set(unit, 50, SOC_CTR_TYPE_XE); 3877 break; 3878 case BCM56638_DEVICE_ID: 3879 if (soc_property_get(unit, spn_BCM56638_8X12, 0)) { 3880 /* 8x12HG + 1x12G(loopback) */ 3881 tdm_size = 110; 3882 if (front_panel_esm) { 3883 arr = tdmb638b; 3884 eelist = eelist638bfp; 3885 } else { 3886 arr = tdmb638bbp; 3887 eelist = eelist638b; 3888 } 3889 } else if (soc_property_get(unit, spn_BCM56638_4X12_2X24, 0)) { 3890 /* 4x12HG + 2x24G(loopback) */ 3891 tdm_size = 110; 3892 if (front_panel_esm) { 3893 arr = tdmb638c; 3894 eelist = eelist638cfp; 3895 } else { 3896 arr = tdmb638cbp; 3897 eelist = eelist638c; 3898 } 3899 } else { 3900 /* 4x12HG + 4x16HG */ 3901 tdm_size = 114; 3902 if (front_panel_esm) { 3903 arr = tdmb638a; 3904 eelist = eelist638afp; 3905 } else { 3906 arr = tdmb638abp; 3907 eelist = eelist638a; 3908 } 3909 } 3910 SOC_IF_ERROR_RETURN 3911 (soc_reg_field32_modify(unit, EDATABUF_XQP_FLEXPORT_CONFIGr, 3912 REG_PORT_ANY, EGR_XQP_PORT_INT_RESETf, 3913 0x2D)); 3914 SOC_IF_ERROR_RETURN 3915 (soc_reg_field32_modify(unit, EDATABUF_XQP_FLEXPORT_CONFIGr, 3916 REG_PORT_ANY, EGR_XQP_PORT_MODEf, 0x2D)); 3917 SOC_IF_ERROR_RETURN 3918 (soc_reg_field32_modify(unit, EDATABUF_XQP_FLEXPORT_CONFIGr, 3919 REG_PORT_ANY, EGR_XQP_PORT_INT_RESETf, 0)); 3920 soc_port_cmap_set(unit, 30, SOC_CTR_TYPE_XE); 3921 soc_port_cmap_set(unit, 38, SOC_CTR_TYPE_XE); 3922 soc_port_cmap_set(unit, 42, SOC_CTR_TYPE_XE); 3923 soc_port_cmap_set(unit, 50, SOC_CTR_TYPE_XE); 3924 break; 3925 case BCM56639_DEVICE_ID: 3926 if (!soc_property_get(unit, spn_BCM56639_28G_7X10, 0)) { 3927 /* 24x1GE + 8x10G + loopback */ 3928 arr = tdmb639a; 3929 } else { 3930 /* 28x1GE + 7x10G + loopback */ 3931 arr = tdmb639b; 3932 } 3933 tdm_size = 114; 3934 SOC_IF_ERROR_RETURN 3935 (soc_reg_field32_modify(unit, EDATABUF_XQP_FLEXPORT_CONFIGr, 3936 REG_PORT_ANY, EGR_XQP_PORT_INT_RESETf, 3937 0x2D)); 3938 SOC_IF_ERROR_RETURN 3939 (soc_reg_field32_modify(unit, EDATABUF_XQP_FLEXPORT_CONFIGr, 3940 REG_PORT_ANY, EGR_XQP_PORT_MODEf, 0x2D)); 3941 SOC_IF_ERROR_RETURN 3942 (soc_reg_field32_modify(unit, EDATABUF_XQP_FLEXPORT_CONFIGr, 3943 REG_PORT_ANY, EGR_XQP_PORT_INT_RESETf, 0)); 3944 soc_port_cmap_set(unit, 30, SOC_CTR_TYPE_XE); 3945 soc_port_cmap_set(unit, 38, SOC_CTR_TYPE_XE); 3946 soc_port_cmap_set(unit, 42, SOC_CTR_TYPE_XE); 3947 soc_port_cmap_set(unit, 50, SOC_CTR_TYPE_XE); 3948 break; 3949 case BCM56689_DEVICE_ID: 3950 has_sport = FALSE; 3951 /* Fall through */ 3952 case BCM56685_DEVICE_ID: 3953 /* 24x2.5GE + 4x12G + loopback */ 3954 tdm_size = 228; 3955 arr = tdmb685; 3956 break; 3957 case BCM56520_DEVICE_ID: 3958 /* Fall through */ 3959 case BCM56522_DEVICE_ID: 3960 if (soc_property_get(unit, spn_HIGIG_MAX_SPEED, 0) == 12000) { 3961 /* 48x1GE + 4x12HG + 1x12G(loopback) */ 3962 tdm_size = 110; 3963 arr = tdmb634b; 3964 } else { 3965 /* 24x1GE + 4x20HG + loopback */ 3966 tdm_size = 110; 3967 arr = tdmb524b; 3968 } 3969 break; 3970 case BCM56521_DEVICE_ID: 3971 has_sport = FALSE; 3972 if (soc_property_get(unit, spn_BCM56521_2X12_2X24, 0)) { 3973 /* 24x1GE + 2x12HG + 2x24HG + loopback */ 3974 tdm_size = 110; 3975 arr = tdmb521b; 3976 } else if (soc_property_get(unit, spn_HIGIG_MAX_SPEED, 0) == 12000) { 3977 /* 48x1GE + 4x12HG + 1x12G(loopback) */ 3978 tdm_size = 110; 3979 arr = tdmb634b; 3980 } else { 3981 /* 24x1GE + 4x20HG + loopback */ 3982 tdm_size = 114; 3983 arr = tdmb521a; 3984 } 3985 break; 3986 case BCM56630_DEVICE_ID: 3987 has_sport = FALSE; 3988 if (soc_property_get(unit, spn_BCM56630_2X12_2X24, 0)) { 3989 /* 24x1GE + 2x12HG + 2x24HG + loopback */ 3990 tdm_size = 110; 3991 arr = tdmb524b; 3992 } else if (soc_property_get(unit, spn_HIGIG_MAX_SPEED, 0) == 12000) { 3993 /* 48x1GE + 4x12HG + 1x12G(loopback) */ 3994 tdm_size = 110; 3995 arr = tdmb634b; 3996 } else { 3997 /* 24x1GE + 4x20HG + loopback */ 3998 tdm_size = 114; 3999 arr = tdmb524a; 4000 } 4001 break; 4002 case BCM56524_DEVICE_ID: 4003 /* Fall through */ 4004 case BCM56534_DEVICE_ID: 4005 has_sport = FALSE; 4006 if (soc_property_get(unit, spn_BCM56524_2X12_2X24, 0) || 4007 soc_property_get(unit, spn_BCM56534_2X12_2X24, 0)) { 4008 /* 24x1GE + 2x12HG + 2x24HG + loopback */ 4009 tdm_size = 110; 4010 arr = tdmb524b; 4011 } else if (soc_property_get(unit, spn_HIGIG_MAX_SPEED, 0) == 12000) { 4012 /* 48x1GE + 4x12HG + 1x12G(loopback) */ 4013 tdm_size = 110; 4014 arr = tdmb634b; 4015 } else { 4016 /* 24x1GE + 4x20HG + loopback */ 4017 tdm_size = 114; 4018 arr = tdmb524a; 4019 } 4020 break; 4021 case BCM56526_DEVICE_ID: 4022 if (soc_property_get(unit, spn_BCM56526_2X12_4X16, 0)) { 4023 /* 24X1GE + 2X12HG + 4X16HG */ 4024 tdm_size = 114; 4025 arr = tdmb526b; 4026 } else { 4027 /* 28x1GE + 6x12HG + loopback */ 4028 tdm_size = 110; 4029 arr = tdmb526a; 4030 } 4031 SOC_IF_ERROR_RETURN 4032 (soc_reg_field32_modify(unit, EDATABUF_XQP_FLEXPORT_CONFIGr, 4033 REG_PORT_ANY, EGR_XQP_PORT_INT_RESETf, 4034 0x30)); 4035 SOC_IF_ERROR_RETURN 4036 (soc_reg_field32_modify(unit, EDATABUF_XQP_FLEXPORT_CONFIGr, 4037 REG_PORT_ANY, EGR_XQP_PORT_MODEf, 0x30)); 4038 SOC_IF_ERROR_RETURN 4039 (soc_reg_field32_modify(unit, EDATABUF_XQP_FLEXPORT_CONFIGr, 4040 REG_PORT_ANY, EGR_XQP_PORT_INT_RESETf, 0)); 4041 soc_port_cmap_set(unit, 46, SOC_CTR_TYPE_XE); 4042 soc_port_cmap_set(unit, 50, SOC_CTR_TYPE_XE); 4043 break; 4044 default: 4045 tdm_size = 114; 4046 arr = tdmb634a; 4047 eelist = eelist634afp; 4048 break; 4049 } 4050 for (i = 0; i < tdm_size; i++) { 4051 sal_memset(&iarb_tdm, 0, sizeof(iarb_tdm_table_entry_t)); 4052 sal_memset(&arb_tdm, 0, sizeof(arb_tdm_table_entry_t)); 4053 soc_IARB_TDM_TABLEm_field32_set(unit, &iarb_tdm, PORT_NUMf, 4054 arr[i]); 4055 soc_ARB_TDM_TABLEm_field32_set(unit, &arb_tdm, PORT_NUMf, 4056 arr[i]); 4057 if (soc_feature(unit, soc_feature_esm_support)) { 4058 /* coverity[var_deref_op] */ 4059 soc_IARB_TDM_TABLEm_field32_set(unit, &iarb_tdm, 4060 ESM_ELIGIBLEf, eelist[arr[i]]); 4061 } 4062 /* Cache the CPU slot entry */ 4063 if (IS_CPU_PORT(unit, arr[i])) { 4064 sal_memcpy(&(SOC_CONTROL(unit)->iarb_tdm), &iarb_tdm, 4065 sizeof(iarb_tdm)); 4066 SOC_CONTROL(unit)->iarb_tdm_idx = i; 4067 } 4068 if (i == tdm_size - 1) { 4069 soc_ARB_TDM_TABLEm_field32_set(unit, &arb_tdm, WRAP_ENf, 1); 4070 } 4071 SOC_IF_ERROR_RETURN(WRITE_IARB_TDM_TABLEm(unit, SOC_BLOCK_ALL, i, 4072 &iarb_tdm)); 4073 SOC_IF_ERROR_RETURN(WRITE_ARB_TDM_TABLEm(unit, SOC_BLOCK_ALL, i, 4074 &arb_tdm)); 4075 } 4076 rval = 0; 4077 soc_reg_field_set(unit, IARB_TDM_CONTROLr, &rval, DISABLEf, 0); 4078 soc_reg_field_set(unit, IARB_TDM_CONTROLr, &rval, TDM_WRAP_PTRf, 4079 tdm_size -1); 4080 SOC_IF_ERROR_RETURN(WRITE_IARB_TDM_CONTROLr(unit, rval)); 4081 4082 /* Enable SPORT */ 4083 /* coverity[result_independent_of_operands] */ 4084 if (has_sport && SOC_PORT_VALID(unit, 1)) { 4085 SOC_IF_ERROR_RETURN(READ_SPORT_CTL_REGr(unit, 1, &rval)); 4086 soc_reg_field_set(unit, SPORT_CTL_REGr, &rval, SPORT_EN_BITf, 1); 4087 SOC_IF_ERROR_RETURN(WRITE_SPORT_CTL_REGr(unit, 1, rval)); 4088 } 4089 4090 /* Set the mode for XE ports (XPORT blocks) */ 4091 mode = 1; 4092 if (SOC_PORT_VALID(unit, 26)) { 4093 SOC_IF_ERROR_RETURN(READ_XPORT_MODE_REGr(unit, 26, &rval)); 4094 soc_reg_field_set(unit, XPORT_MODE_REGr, &rval, XPORT_MODE_BITSf, mode); 4095 SOC_IF_ERROR_RETURN(WRITE_XPORT_MODE_REGr(unit, 26, rval)); 4096 } 4097 if (SOC_PORT_VALID(unit, 27)) { 4098 SOC_IF_ERROR_RETURN(READ_XPORT_MODE_REGr(unit, 27, &rval)); 4099 soc_reg_field_set(unit, XPORT_MODE_REGr, &rval, XPORT_MODE_BITSf, mode); 4100 SOC_IF_ERROR_RETURN(WRITE_XPORT_MODE_REGr(unit, 27, rval)); 4101 } 4102 if (SOC_PORT_VALID(unit, 28)) { 4103 SOC_IF_ERROR_RETURN(READ_XPORT_MODE_REGr(unit, 28, &rval)); 4104 soc_reg_field_set(unit, XPORT_MODE_REGr, &rval, XPORT_MODE_BITSf, mode); 4105 SOC_IF_ERROR_RETURN(WRITE_XPORT_MODE_REGr(unit, 28, rval)); 4106 } 4107 if (SOC_PORT_VALID(unit, 29)) { 4108 SOC_IF_ERROR_RETURN(READ_XPORT_MODE_REGr(unit, 29, &rval)); 4109 soc_reg_field_set(unit, XPORT_MODE_REGr, &rval, XPORT_MODE_BITSf, mode); 4110 SOC_IF_ERROR_RETURN(WRITE_XPORT_MODE_REGr(unit, 29, rval)); 4111 } 4112 4113 /* Enable GPORTs and XQPORTs */ 4114 /* coverity[result_independent_of_operands] */ 4115 if (SOC_PORT_VALID(unit, 2)) { 4116 SOC_IF_ERROR_RETURN(READ_GPORT_MODE_REGr(unit, 2, &rval)); 4117 soc_reg_field_set(unit, GPORT_MODE_REGr, &rval, GPORT_MODE_BITSf, mode); 4118 SOC_IF_ERROR_RETURN(WRITE_GPORT_MODE_REGr(unit, 2, rval)); 4119 } 4120 if (SOC_PORT_VALID(unit, 14)) { 4121 SOC_IF_ERROR_RETURN(READ_GPORT_MODE_REGr(unit, 14, &rval)); 4122 soc_reg_field_set(unit, GPORT_MODE_REGr, &rval, GPORT_MODE_BITSf, mode); 4123 SOC_IF_ERROR_RETURN(WRITE_GPORT_MODE_REGr(unit, 14, rval)); 4124 } 4125 if (SOC_PORT_VALID(unit, 30)) { 4126 switch (dev_id) { 4127 case BCM56639_DEVICE_ID: 4128 case BCM56638_DEVICE_ID: 4129 mode = 2; 4130 break; 4131 default: 4132 mode = 1; 4133 break; 4134 } 4135 SOC_IF_ERROR_RETURN(READ_XQPORT_MODE_REGr(unit, 30, &rval)); 4136 soc_reg_field_set(unit, XQPORT_MODE_REGr, &rval, 4137 XQPORT_MODE_BITSf, mode); 4138 SOC_IF_ERROR_RETURN(WRITE_XQPORT_MODE_REGr(unit, 30, rval)); 4139 } 4140 if (SOC_PORT_VALID(unit, 34)) { 4141 SOC_IF_ERROR_RETURN(READ_XQPORT_MODE_REGr(unit, 34, &rval)); 4142 soc_reg_field_set(unit, XQPORT_MODE_REGr, &rval, 4143 XQPORT_MODE_BITSf, mode); 4144 SOC_IF_ERROR_RETURN(WRITE_XQPORT_MODE_REGr(unit, 34, rval)); 4145 } 4146 if (SOC_PORT_VALID(unit, 38)) { 4147 switch (dev_id) { 4148 case BCM56639_DEVICE_ID: 4149 case BCM56638_DEVICE_ID: 4150 mode = 2; 4151 break; 4152 default: 4153 mode = 1; 4154 break; 4155 } 4156 SOC_IF_ERROR_RETURN(READ_XQPORT_MODE_REGr(unit, 38, &rval)); 4157 soc_reg_field_set(unit, XQPORT_MODE_REGr, &rval, 4158 XQPORT_MODE_BITSf, mode); 4159 SOC_IF_ERROR_RETURN(WRITE_XQPORT_MODE_REGr(unit, 38, rval)); 4160 } 4161 if (SOC_PORT_VALID(unit, 42)) { 4162 switch (dev_id) { 4163 case BCM56639_DEVICE_ID: 4164 case BCM56638_DEVICE_ID: 4165 case BCM56636_DEVICE_ID: 4166 mode = 2; 4167 break; 4168 default: 4169 mode = 1; 4170 break; 4171 } 4172 SOC_IF_ERROR_RETURN(READ_XQPORT_MODE_REGr(unit, 42, &rval)); 4173 soc_reg_field_set(unit, XQPORT_MODE_REGr, &rval, 4174 XQPORT_MODE_BITSf, mode); 4175 SOC_IF_ERROR_RETURN(WRITE_XQPORT_MODE_REGr(unit, 42, rval)); 4176 } 4177 if (SOC_PORT_VALID(unit, 46)) { 4178 switch (dev_id) { 4179 case BCM56526_DEVICE_ID: 4180 mode = 2; 4181 break; 4182 default: 4183 mode = 1; 4184 break; 4185 } 4186 SOC_IF_ERROR_RETURN(READ_XQPORT_MODE_REGr(unit, 46, &rval)); 4187 soc_reg_field_set(unit, XQPORT_MODE_REGr, &rval, 4188 XQPORT_MODE_BITSf, mode); 4189 SOC_IF_ERROR_RETURN(WRITE_XQPORT_MODE_REGr(unit, 46, rval)); 4190 } 4191 if (SOC_PORT_VALID(unit, 50)) { 4192 switch (dev_id) { 4193 case BCM56639_DEVICE_ID: 4194 case BCM56638_DEVICE_ID: 4195 case BCM56636_DEVICE_ID: 4196 case BCM56526_DEVICE_ID: 4197 mode = 2; 4198 break; 4199 default: 4200 mode = 1; 4201 break; 4202 } 4203 SOC_IF_ERROR_RETURN(READ_XQPORT_MODE_REGr(unit, 50, &rval)); 4204 soc_reg_field_set(unit, XQPORT_MODE_REGr, &rval, 4205 XQPORT_MODE_BITSf, mode); 4206 SOC_IF_ERROR_RETURN(WRITE_XQPORT_MODE_REGr(unit, 50, rval)); 4207 } 4208 4209 SOC_IF_ERROR_RETURN(soc_generic_ser_mem_scan_stop(unit)); 4210 4211 if (soc_property_get(unit, spn_PARITY_ENABLE, TRUE)) { 4212 soc_ser_log_init(unit, NULL, 0); 4213 _soc_triumph2_parity_enable(unit, TRUE); 4214 if (soc_feature(unit, soc_feature_esm_support)) { 4215 SOC_IF_ERROR_RETURN(_soc_triumph2_esm_intr_enable(unit, TRUE)); 4216 } 4217 if (soc_feature(unit, soc_feature_ser_parity)) { 4218 SOC_IF_ERROR_RETURN(_soc_triumph2_ser_init(unit)); 4219 #ifdef INCLUDE_MEM_SCAN 4220 soc_mem_scan_ser_list_register(unit, FALSE, 4221 _soc_tr2_ser_parity_info); 4222 #endif /* INCLUDE_MEM_SCAN */ 4223 memset(&_tr2_ser_functions, 0, sizeof(soc_ser_functions_t)); 4224 _tr2_ser_functions._soc_ser_stat_nack_f = &soc_triumph2_stat_nack; 4225 _tr2_ser_functions._soc_ser_mem_nack_f = &soc_triumph2_mem_nack; 4226 _tr2_ser_functions._soc_ser_fail_f = &soc_triumph2_ser_fail; 4227 _tr2_ser_functions._soc_ser_parity_error_intr_f = 4228 &soc_triumph2_parity_error; 4229 soc_ser_function_register(unit, &_tr2_ser_functions); 4230 } 4231 }else { 4232 SOC_IF_ERROR_RETURN(_soc_triumph2_oam_enable_only(unit, TRUE)); 4233 memset(&_tr2_oam_event_functions, 0, sizeof(soc_oam_event_functions_t)); 4234 _tr2_oam_event_functions._soc_oam_event_intr_f = &soc_triumph2_oam_events; 4235 soc_oam_event_function_register (unit, &_tr2_oam_event_functions); 4236 } 4237 4238 /* We need the metering clock turned on regardless of parity */ 4239 SOC_IF_ERROR_RETURN(READ_MISCCONFIGr(unit, &misc_cfg)); 4240 soc_reg_field_set(unit, MISCCONFIGr, &misc_cfg, METERING_CLK_ENf, 1); 4241 SOC_IF_ERROR_RETURN(WRITE_MISCCONFIGr(unit, misc_cfg)); 4242 4243 /* Enable dual hash on L2, L3 and MPLS_ENTRY tables */ 4244 fields[0] = ENABLEf; 4245 values[0] = 1; 4246 fields[1] = HASH_SELECTf; 4247 values[1] = FB_HASH_CRC32_LOWER; 4248 fields[2] = INSERT_LEAST_FULL_HALFf; 4249 values[2] = 1; 4250 SOC_IF_ERROR_RETURN 4251 (soc_reg_fields32_modify(unit, L2_AUX_HASH_CONTROLr, REG_PORT_ANY, 3, 4252 fields, values)); 4253 SOC_IF_ERROR_RETURN 4254 (soc_reg_fields32_modify(unit, L3_AUX_HASH_CONTROLr, REG_PORT_ANY, 3, 4255 fields, values)); 4256 SOC_IF_ERROR_RETURN 4257 (soc_reg_field32_modify(unit, MPLS_ENTRY_HASH_CONTROLr, REG_PORT_ANY, 4258 INSERT_LEAST_FULL_HALFf, 1)); 4259 4260 /* 4261 * Egress Enable 4262 */ 4263 rval = 0; 4264 soc_reg_field_set(unit, EGR_ENABLEr, &rval, PRT_ENABLEf, 1); 4265 PBMP_ALL_ITER(unit, port) { 4266 if ((SOC_PBMP_MEMBER(SOC_PORT_DISABLED_BITMAP(unit,all), port))) { 4267 continue; 4268 } 4269 SOC_IF_ERROR_RETURN(WRITE_EGR_ENABLEr(unit, port, rval)); 4270 } 4271 4272 COMPILER_64_ZERO(reg64); 4273 soc_reg64_field32_set(unit, EPC_LINK_BMAP_64r, ®64, PORT_BITMAP_LOf, 4274 SOC_PBMP_WORD_GET(PBMP_CMIC(unit), 0)); 4275 soc_reg64_field32_set(unit, EPC_LINK_BMAP_64r, ®64, PORT_BITMAP_HIf, 4276 SOC_PBMP_WORD_GET(PBMP_CMIC(unit), 1)); 4277 SOC_IF_ERROR_RETURN(WRITE_EPC_LINK_BMAP_64r(unit, reg64)); 4278 4279 /* GMAC init should be moved to mac */ 4280 rval = 0; 4281 soc_reg_field_set(unit, GPORT_CONFIGr, &rval, CLR_CNTf, 1); 4282 prev_reg_addr = 0xffffffff; 4283 PBMP_GE_ITER(unit, port) { 4284 uint32 reg_addr; 4285 reg_addr = soc_reg_addr(unit, GPORT_CONFIGr, port, 0); 4286 if (reg_addr != prev_reg_addr) { 4287 SOC_IF_ERROR_RETURN(WRITE_GPORT_CONFIGr(unit, port, rval)); 4288 prev_reg_addr = reg_addr; 4289 } 4290 } 4291 prev_reg_addr = 0xffffffff; 4292 soc_reg_field_set(unit, GPORT_CONFIGr, &rval, CLR_CNTf, 0); 4293 PBMP_GE_ITER(unit, port) { 4294 uint32 reg_addr; 4295 reg_addr = soc_reg_addr(unit, GPORT_CONFIGr, port, 0); 4296 if (reg_addr != prev_reg_addr) { 4297 SOC_IF_ERROR_RETURN(WRITE_GPORT_CONFIGr(unit, port, rval)); 4298 prev_reg_addr = reg_addr; 4299 } 4300 } 4301 /* XMAC init should be moved to mac */ 4302 if (SOC_PBMP_NOT_NULL(PBMP_XE_ALL(unit)) || 4303 SOC_PBMP_NOT_NULL(PBMP_HG_ALL(unit))) { 4304 rval = 0; 4305 soc_reg_field_set(unit, XPORT_CONFIGr, &rval, XPORT_ENf, 1); 4306 soc_reg_field_set(unit, XPORT_CONFIGr, &rval, HIGIG_MODEf, 1); 4307 PBMP_HG_ITER(unit, port) { 4308 SOC_IF_ERROR_RETURN(WRITE_XPORT_CONFIGr(unit, port, rval)); 4309 } 4310 soc_reg_field_set(unit, XPORT_CONFIGr, &rval, HIGIG_MODEf, 0); 4311 PBMP_XE_ITER(unit, port) { 4312 SOC_IF_ERROR_RETURN(WRITE_XPORT_CONFIGr(unit, port, rval)); 4313 } 4314 } 4315 4316 SOC_IF_ERROR_RETURN(READ_ING_CONFIG_64r(unit, ®64)); 4317 soc_reg64_field32_set(unit, ING_CONFIG_64r, ®64, 4318 L3SRC_HIT_ENABLEf, 1); 4319 soc_reg64_field32_set(unit, ING_CONFIG_64r, ®64, 4320 L2DST_HIT_ENABLEf, 1); 4321 soc_reg64_field32_set(unit, ING_CONFIG_64r, ®64, 4322 APPLY_EGR_MASK_ON_L2f, 1); 4323 soc_reg64_field32_set(unit, ING_CONFIG_64r, ®64, 4324 APPLY_EGR_MASK_ON_L3f, 1); 4325 soc_reg64_field32_set(unit, ING_CONFIG_64r, ®64, 4326 ARP_RARP_TO_FPf, 0x3); /* enable both ARP & RARP */ 4327 soc_reg64_field32_set(unit, ING_CONFIG_64r, ®64, 4328 ARP_VALIDATION_ENf, 1); 4329 soc_reg64_field32_set(unit, ING_CONFIG_64r, ®64, 4330 IGNORE_HG_HDR_LAG_FAILOVERf, 1); 4331 SOC_IF_ERROR_RETURN(WRITE_ING_CONFIG_64r(unit, reg64)); 4332 4333 /* Backwards compatible mirroring by default */ 4334 SOC_IF_ERROR_RETURN(READ_MISCCONFIGr(unit, &rval)); 4335 soc_reg_field_set(unit, MISCCONFIGr, &rval, 4336 DRACO_1_5_MIRRORING_MODE_ENf, 1); 4337 SOC_IF_ERROR_RETURN(WRITE_MISCCONFIGr(unit, rval)); 4338 4339 SOC_IF_ERROR_RETURN(READ_ING_CONFIG_64r(unit, ®64)); 4340 soc_reg64_field32_set(unit, ING_CONFIG_64r, ®64, 4341 DRACO1_5_MIRRORf, 1); 4342 SOC_IF_ERROR_RETURN(WRITE_ING_CONFIG_64r(unit, reg64)); 4343 4344 SOC_IF_ERROR_RETURN(READ_EGR_CONFIGr(unit, &rval)); 4345 soc_reg_field_set(unit, EGR_CONFIGr, &rval, DRACO1_5_MIRRORf, 1); 4346 SOC_IF_ERROR_RETURN(WRITE_EGR_CONFIGr(unit, rval)); 4347 4348 SOC_IF_ERROR_RETURN(READ_EGR_CONFIG_1r(unit, &rval)); 4349 soc_reg_field_set(unit, EGR_CONFIG_1r, &rval, RING_MODEf, 1); 4350 SOC_IF_ERROR_RETURN(WRITE_EGR_CONFIG_1r(unit, rval)); 4351 4352 /* 4353 * Set reference clock (based on 200MHz core clock) 4354 * to be 200MHz * (1/40) = 5MHz 4355 */ 4356 divisor = soc_property_get(unit, spn_RATE_EXT_MDIO_DIVISOR, 40); 4357 dividend = soc_property_get(unit, spn_RATE_EXT_MDIO_DIVIDEND, 1); 4358 rval = 0; 4359 soc_reg_field_set(unit, CMIC_RATE_ADJUSTr, &rval, DIVISORf, divisor); 4360 soc_reg_field_set(unit, CMIC_RATE_ADJUSTr, &rval, DIVIDENDf, dividend); 4361 /* coverity[result_independent_of_operands] */ 4362 SOC_IF_ERROR_RETURN(WRITE_CMIC_RATE_ADJUSTr(unit, rval)); 4363 4364 /* Match the Internal MDC freq with above for External MDC */ 4365 rval = 0; 4366 soc_reg_field_set (unit, CMIC_RATE_ADJUST_INT_MDIOr, &rval, DIVISORf, 40); 4367 soc_reg_field_set (unit, CMIC_RATE_ADJUST_INT_MDIOr, &rval, DIVIDENDf, 1); 4368 /* coverity[result_independent_of_operands] */ 4369 SOC_IF_ERROR_RETURN(WRITE_CMIC_RATE_ADJUST_INT_MDIOr(unit, rval)); 4370 4371 /* 4372 * Set reference clock (based on 200MHz core clock) 4373 * to be 200MHz * (1/8) = 25MHz 4374 */ 4375 rval = 0; 4376 soc_reg_field_set(unit, CMIC_RATE_ADJUST_I2Cr, &rval, DIVISORf, 8); 4377 soc_reg_field_set(unit, CMIC_RATE_ADJUST_I2Cr, &rval, DIVIDENDf, 1); 4378 /* coverity[result_independent_of_operands] */ 4379 SOC_IF_ERROR_RETURN(WRITE_CMIC_RATE_ADJUST_I2Cr(unit, rval)); 4380 4381 rval = 0; 4382 soc_reg_field_set(unit, CMIC_RATE_ADJUST_STDMAr, &rval, DIVISORf, 8); 4383 soc_reg_field_set(unit, CMIC_RATE_ADJUST_STDMAr, &rval, DIVIDENDf, 1); 4384 /* coverity[result_independent_of_operands] */ 4385 SOC_IF_ERROR_RETURN(WRITE_CMIC_RATE_ADJUST_STDMAr(unit, rval)); 4386 4387 rval = 0x01; /* 125KHz I2C sampling rate based on 5Mhz reference clock */ 4388 /* coverity[result_independent_of_operands] */ 4389 SOC_IF_ERROR_RETURN(WRITE_CMIC_I2C_STATr(unit, rval)); 4390 4391 /* GMAC init should be moved to mac */ 4392 rval = 0; 4393 soc_reg_field_set(unit, GPORT_CONFIGr, &rval, CLR_CNTf, 1); 4394 PBMP_GE_ITER(unit, port) { 4395 SOC_IF_ERROR_RETURN(WRITE_GPORT_CONFIGr(unit, port, rval)); 4396 } 4397 soc_reg_field_set(unit, GPORT_CONFIGr, &rval, CLR_CNTf, 0); 4398 PBMP_GE_ITER(unit, port) { 4399 SOC_IF_ERROR_RETURN(WRITE_GPORT_CONFIGr(unit, port, rval)); 4400 } 4401 4402 /* The HW defaults for EGR_VLAN_CONTROL_1.VT_MISS_UNTAG == 1, which 4403 * causes the outer tag to be removed from packets that don't have 4404 * a hit in the egress vlan tranlation table. Set to 0 to disable this. 4405 */ 4406 rval = 0; 4407 soc_reg_field_set(unit, EGR_VLAN_CONTROL_1r, &rval, VT_MISS_UNTAGf, 0); 4408 4409 /* Enable pri/cfi remarking on egress ports. */ 4410 soc_reg_field_set(unit, EGR_VLAN_CONTROL_1r, &rval, REMARK_OUTER_DOT1Pf, 4411 1); 4412 PBMP_ALL_ITER(unit, port) { 4413 SOC_IF_ERROR_RETURN(WRITE_EGR_VLAN_CONTROL_1r(unit, port, rval)); 4414 } 4415 4416 /* Multicast range initialization */ 4417 SOC_IF_ERROR_RETURN 4418 (soc_hbx_higig2_mcast_sizes_set(unit, 4419 soc_property_get(unit, spn_HIGIG2_MULTICAST_VLAN_RANGE, 4420 SOC_HBX_MULTICAST_RANGE_DEFAULT), 4421 soc_property_get(unit, spn_HIGIG2_MULTICAST_L2_RANGE, 4422 SOC_HBX_MULTICAST_RANGE_DEFAULT), 4423 soc_property_get(unit, spn_HIGIG2_MULTICAST_L3_RANGE, 4424 SOC_HBX_MULTICAST_RANGE_DEFAULT))); 4425 4426 /* Enable vrf based l3 lookup by default. */ 4427 SOC_IF_ERROR_RETURN 4428 (soc_reg_field32_modify(unit, VRF_MASKr, REG_PORT_ANY, MASKf, 0)); 4429 4430 /* Setup SW2_FP_DST_ACTION_CONTROL */ 4431 fields[0] = HGTRUNK_RES_ENf; 4432 fields[1] = LAG_RES_ENf; 4433 values[0] = values[1] = 1; 4434 SOC_IF_ERROR_RETURN 4435 (soc_reg_fields32_modify(unit, SW2_FP_DST_ACTION_CONTROLr, 4436 REG_PORT_ANY, 2, fields, values)); 4437 4438 /* Initialize the multipass loopback bitmap to the loopback port */ 4439 COMPILER_64_ZERO(multipass); 4440 COMPILER_64_ZERO(bm64); 4441 COMPILER_64_SET(bm64, (1 << 22), 0); 4442 soc_reg64_field_set(unit, MULTIPASS_LOOPBACK_BITMAP_64r, &multipass, 4443 BITMAPf, bm64); 4444 SOC_IF_ERROR_RETURN(WRITE_MULTIPASS_LOOPBACK_BITMAP_64r(unit, multipass)); 4445 4446 /* Use same values as the CAM BIST screen test */ 4447 rval = 0; 4448 soc_reg_field_set(unit, SW2_RAM_CONTROL_4r, &rval, CPU_COS_MAP_TCAM_TMf, 4449 0x10); 4450 SOC_IF_ERROR_RETURN(WRITE_SW2_RAM_CONTROL_4r_REG32(unit, rval)); 4451 4452 rval = 0; 4453 soc_reg_field_set(unit, EFP_RAM_CONTROLr, &rval, EFP_CAM_TM_7_THRU_0f, 4454 0x10); 4455 SOC_IF_ERROR_RETURN(WRITE_EFP_RAM_CONTROLr(unit, rval)); 4456 4457 rval = 0; 4458 soc_reg_field_set(unit, FP_CAM_CONTROL_TM_7_THRU_0r, &rval, 4459 ALL_TCAMS_TM_7_0f, 0x10); 4460 soc_reg_field_set(unit, FP_CAM_CONTROL_TM_7_THRU_0r, &rval, 4461 ALL_GLOBAL_MASK_TCAMS_TM_7_0f, 0x10); 4462 SOC_IF_ERROR_RETURN(WRITE_FP_CAM_CONTROL_TM_7_THRU_0r(unit, rval)); 4463 4464 rval = 0; 4465 soc_reg_field_set(unit, L2_USER_ENTRY_CAM_DBGCTRLr, &rval, TMf, 0x10); 4466 SOC_IF_ERROR_RETURN(WRITE_L2_USER_ENTRY_CAM_DBGCTRLr(unit, rval)); 4467 4468 rval = 0; 4469 soc_reg_field_set(unit, L3_DEFIP_128_CAM_DBGCTRLr, &rval, CAM0_TMf, 0x10); 4470 soc_reg_field_set(unit, L3_DEFIP_128_CAM_DBGCTRLr, &rval, CAM1_TMf, 0x10); 4471 SOC_IF_ERROR_RETURN(WRITE_L3_DEFIP_128_CAM_DBGCTRLr(unit, rval)); 4472 4473 rval = 0; 4474 soc_reg_field_set(unit, L3_DEFIP_CAM_DBGCTRL0r, &rval, CAM0_TMf, 0x10); 4475 soc_reg_field_set(unit, L3_DEFIP_CAM_DBGCTRL0r, &rval, CAM1_TMf, 0x10); 4476 SOC_IF_ERROR_RETURN(WRITE_L3_DEFIP_CAM_DBGCTRL0r(unit, rval)); 4477 4478 rval = 0; 4479 soc_reg_field_set(unit, L3_DEFIP_CAM_DBGCTRL1r, &rval, CAM2_TMf, 0x10); 4480 soc_reg_field_set(unit, L3_DEFIP_CAM_DBGCTRL1r, &rval, CAM3_TMf, 0x10); 4481 SOC_IF_ERROR_RETURN(WRITE_L3_DEFIP_CAM_DBGCTRL1r(unit, rval)); 4482 4483 rval = 0; 4484 soc_reg_field_set(unit, L3_DEFIP_CAM_DBGCTRL2r, &rval, CAM4_TMf, 0x10); 4485 soc_reg_field_set(unit, L3_DEFIP_CAM_DBGCTRL2r, &rval, CAM5_TMf, 0x10); 4486 SOC_IF_ERROR_RETURN(WRITE_L3_DEFIP_CAM_DBGCTRL2r(unit, rval)); 4487 4488 rval = 0; 4489 soc_reg_field_set(unit, L3_DEFIP_CAM_DBGCTRL3r, &rval, CAM6_TMf, 0x10); 4490 soc_reg_field_set(unit, L3_DEFIP_CAM_DBGCTRL3r, &rval, CAM7_TMf, 0x10); 4491 SOC_IF_ERROR_RETURN(WRITE_L3_DEFIP_CAM_DBGCTRL3r(unit, rval)); 4492 4493 rval = 0; 4494 soc_reg_field_set(unit, MPLS_STATION_CAM_DBGCTRLr, &rval, CAM0_TMf, 0x10); 4495 SOC_IF_ERROR_RETURN(WRITE_MPLS_STATION_CAM_DBGCTRLr(unit, rval)); 4496 4497 rval = 0; 4498 soc_reg_field_set(unit, UDF_CAM_DBGCTRLr, &rval, TMf, 0x10); 4499 SOC_IF_ERROR_RETURN(WRITE_UDF_CAM_DBGCTRLr(unit, rval)); 4500 4501 rval = 0; 4502 soc_reg_field_set(unit, VFP_CAM_CONTROL_TM_7_THRU_0r, &rval, TMf, 0x10); 4503 SOC_IF_ERROR_RETURN(WRITE_VFP_CAM_CONTROL_TM_7_THRU_0r(unit, rval)); 4504 4505 rval = 0; 4506 soc_reg_field_set(unit, VLAN_SUBNET_CAM_DBGCTRLr, &rval, TMf, 0x10); 4507 SOC_IF_ERROR_RETURN(WRITE_VLAN_SUBNET_CAM_DBGCTRLr(unit, rval)); 4508 4509 /* Cache LMEP table */ 4510 SOC_IF_ERROR_RETURN(soc_mem_cache_set(unit, LMEPm, MEM_BLOCK_ALL, TRUE)); 4511 4512 SOC_IF_ERROR_RETURN(soc_generic_ser_mem_scan_start(unit)); 4513 4514 return SOC_E_NONE; 4515 } 4516 4517 #define TR2_MMU_NUM_PG 8 4518 #define TR2_MMU_NUM_COS 8 4519 4520 /* Standard Ethernet MTU, 1536 bytes (1 cell = 128 bytes) */ 4521 #define TR2_MMU_ETH_FRAME_CELLS 12 4522 4523 /* Jumbo Frame MTU, 9216 (1 cell = 128 bytes) */ 4524 #define TR2_MMU_JUMBO_FRAME_CELLS 72 4525 4526 /* MAX Frame MTU, 16384 (1 cell = 128 bytes) */ 4527 #define TR2_MMU_MAX_FRAME_CELLS 128 4528 4529 #define TR2_MMU_IN_PORT_MIN_CELLS 72 4530 #define TR2_MMU_IN_PORT_MIN_PKTS 1 4531 #define TR2_MMU_PG_HDRM_LIMIT_CELLS 36 4532 #define TR2_MMU_PG_HDRM_LIMIT_PKTS 36 4533 #define TR2_MMU_GLOBAL_HDRM_LIMIT_CELLS 636 4534 #define TR2_MMU_PG_RESET_OFFSET_CELLS 24 4535 #define TR2_MMU_PG_RESET_OFFSET_PKTS 1 4536 4537 #define TR2_MMU_OUT_PORT_MIN_CELLS 12 4538 #define TR2_MMU_OUT_PORT_MIN_PKTS 1 4539 #define TR2_MMU_OUT_RESET_OFFSET_CELLS 24 4540 #define TR2_MMU_OUT_RESET_OFFSET_PKTS 2 4541 #define TR2_MMU_SOP_POLICY 0 4542 #define TR2_MMU_MOP_POLICY 7 4543 4544 int 4545 soc_triumph2_mmu_init(int unit) 4546 { 4547 uint64 rval64; 4548 uint32 rval, rval0, rval1, cell_rval, pkt_rval, disc_set; 4549 uint16 dev_id; 4550 uint8 rev_id; 4551 int rv = SOC_E_NONE; 4552 int port; 4553 int total_cells, total_pkts; 4554 int in_reserved_cells, in_reserved_pkts; 4555 int out_reserved_cells, out_reserved_pkts; 4556 int out_shared_cells, out_shared_pkts; 4557 int idx, sum_all_ports, count; 4558 soc_pbmp_t pbmp_8pg, pbmp_2pg, temp; 4559 4560 soc_cm_get_id(unit, &dev_id, &rev_id); 4561 /* Total number of cells */ 4562 if ((SOC_IS_APOLLO(unit) || SOC_IS_VALKYRIE2(unit)) && 4563 (dev_id != BCM56534_DEVICE_ID) && (dev_id != BCM56630_DEVICE_ID)) { 4564 total_cells = 24 * 1024; /* 24K cells */ 4565 } else { 4566 total_cells = 32 * 1024; /* 32K cells */ 4567 } 4568 4569 /* Total number of packet pointers */ 4570 total_pkts = 11 * 1024; /* 11K packet pointers */ 4571 4572 /* 8PG_PORTS = [26..30,34,38,42,46,50,54] */ 4573 SOC_PBMP_CLEAR(pbmp_8pg); 4574 SOC_PBMP_PORT_ADD(pbmp_8pg, 26); 4575 SOC_PBMP_PORT_ADD(pbmp_8pg, 27); 4576 SOC_PBMP_PORT_ADD(pbmp_8pg, 28); 4577 SOC_PBMP_PORT_ADD(pbmp_8pg, 29); 4578 SOC_PBMP_PORT_ADD(pbmp_8pg, 30); 4579 SOC_PBMP_PORT_ADD(pbmp_8pg, 34); 4580 SOC_PBMP_PORT_ADD(pbmp_8pg, 38); 4581 SOC_PBMP_PORT_ADD(pbmp_8pg, 42); 4582 SOC_PBMP_PORT_ADD(pbmp_8pg, 46); 4583 SOC_PBMP_PORT_ADD(pbmp_8pg, 50); 4584 if (soc_feature(unit, soc_feature_internal_loopback)) { 4585 SOC_PBMP_PORT_ADD(pbmp_8pg, 54); 4586 } 4587 SOC_PBMP_AND(pbmp_8pg, PBMP_ALL(unit)); 4588 4589 /* 2PG_PORTS = [0,1..25,31..33,35..37,39..41,43..45,47..49,51..53,55,56] */ 4590 SOC_PBMP_CLEAR(pbmp_2pg); 4591 SOC_PBMP_ASSIGN(pbmp_2pg, PBMP_ALL(unit)); 4592 SOC_PBMP_PORT_REMOVE(pbmp_2pg, 26); 4593 SOC_PBMP_PORT_REMOVE(pbmp_2pg, 27); 4594 SOC_PBMP_PORT_REMOVE(pbmp_2pg, 28); 4595 SOC_PBMP_PORT_REMOVE(pbmp_2pg, 29); 4596 SOC_PBMP_PORT_REMOVE(pbmp_2pg, 30); 4597 SOC_PBMP_PORT_REMOVE(pbmp_2pg, 34); 4598 SOC_PBMP_PORT_REMOVE(pbmp_2pg, 38); 4599 SOC_PBMP_PORT_REMOVE(pbmp_2pg, 42); 4600 SOC_PBMP_PORT_REMOVE(pbmp_2pg, 46); 4601 SOC_PBMP_PORT_REMOVE(pbmp_2pg, 50); 4602 SOC_PBMP_PORT_REMOVE(pbmp_2pg, 54); 4603 if (soc_feature(unit, soc_feature_internal_loopback)) { 4604 if (soc_feature(unit, soc_feature_wlan)) { 4605 SOC_PBMP_PORT_ADD(pbmp_2pg, 55); 4606 } 4607 SOC_PBMP_PORT_ADD(pbmp_2pg, 56); 4608 } 4609 4610 /* 4611 * Reserved space calculation: 4612 * Input port: 4613 * per-port minimum 4614 * per-PG minimum (config to 0) 4615 * per-PG headroom 4616 * per-device headroom 4617 * per-port minimum for SC and QM traffic (config to 0) 4618 * Output port: 4619 * per-port per-COS minimum space 4620 * Shared space calculation: 4621 * Input port: total - input port reserved - output port reserved 4622 * Output port: total - output port reserved 4623 */ 4624 if (soc_feature(unit, soc_feature_internal_loopback)) { 4625 if (soc_feature(unit, soc_feature_wlan)) { 4626 sum_all_ports = NUM_ALL_PORT(unit) + 2; /* including 55 and 56 */ 4627 } else { 4628 sum_all_ports = NUM_ALL_PORT(unit) + 1; /* including 56 only */ 4629 } 4630 } else { 4631 sum_all_ports = NUM_ALL_PORT(unit); /* no loopback */ 4632 } 4633 in_reserved_cells = sum_all_ports * TR2_MMU_IN_PORT_MIN_CELLS + 4634 (sum_all_ports - 1) * TR2_MMU_PG_HDRM_LIMIT_CELLS + 4635 TR2_MMU_GLOBAL_HDRM_LIMIT_CELLS; 4636 in_reserved_pkts = sum_all_ports * TR2_MMU_IN_PORT_MIN_PKTS + 4637 (sum_all_ports - 1) * TR2_MMU_PG_HDRM_LIMIT_PKTS; 4638 out_reserved_cells = 4639 (NUM_PORT(unit) * TR2_MMU_NUM_COS + SOC_INFO(unit).num_cpu_cosq) * 4640 TR2_MMU_OUT_PORT_MIN_CELLS; 4641 out_reserved_pkts = 4642 (NUM_PORT(unit) * TR2_MMU_NUM_COS + SOC_INFO(unit).num_cpu_cosq) * 4643 TR2_MMU_OUT_PORT_MIN_PKTS; 4644 4645 /* 4646 * Input ports threshold 4647 */ 4648 /* Reserved space: Input port per-port minimum */ 4649 cell_rval = 0; 4650 soc_reg_field_set(unit, PORT_MIN_CELLr, &cell_rval, PORT_MINf, 4651 TR2_MMU_IN_PORT_MIN_CELLS); 4652 pkt_rval = 0; 4653 soc_reg_field_set(unit, PORT_MIN_PACKETr, &pkt_rval, PORT_MINf, 4654 TR2_MMU_IN_PORT_MIN_PKTS); 4655 PBMP_ALL_ITER(unit, port) { 4656 SOC_IF_ERROR_RETURN(WRITE_PORT_MIN_CELLr(unit, port, cell_rval)); 4657 SOC_IF_ERROR_RETURN(WRITE_PORT_MIN_PACKETr(unit, port, pkt_rval)); 4658 } 4659 if (soc_feature(unit, soc_feature_internal_loopback)) { 4660 /* Redirect port */ 4661 SOC_IF_ERROR_RETURN(WRITE_PORT_MIN_CELLr(unit, 56, cell_rval)); 4662 SOC_IF_ERROR_RETURN(WRITE_PORT_MIN_PACKETr(unit, 56, pkt_rval)); 4663 rval = 0; 4664 soc_reg_field_set(unit, RDE_PORT_SHARED_LIMIT_PACKETr, &rval, 4665 PORT_SHARED_LIMITf, 1024); 4666 SOC_IF_ERROR_RETURN(WRITE_RDE_PORT_SHARED_LIMIT_PACKETr(unit, rval)); 4667 rval = 0; 4668 soc_reg_field_set(unit, PG_RDE_RESET_OFFSET_PACKETr, &rval, 4669 PG_RESET_OFFSETf, 4); 4670 SOC_IF_ERROR_RETURN(WRITE_PG_RDE_RESET_OFFSET_PACKETr(unit, 0, rval)); 4671 SOC_IF_ERROR_RETURN(WRITE_PG_RDE_RESET_OFFSET_PACKETr(unit, 1, rval)); 4672 rval = 0; 4673 soc_reg_field_set(unit, PG_RDE_THRESH_SEL2r, &rval, 4674 PG0_THRESH_SELf, 8); 4675 SOC_IF_ERROR_RETURN(WRITE_PG_RDE_THRESH_SEL2r(unit, rval)); 4676 /* PG_RDE_MIN_PACKET = 0 : default */ 4677 /* WLAN port */ 4678 if (soc_feature(unit, soc_feature_wlan)) { 4679 SOC_IF_ERROR_RETURN(WRITE_PORT_MIN_CELLr(unit, 55, cell_rval)); 4680 SOC_IF_ERROR_RETURN(WRITE_PORT_MIN_PACKETr(unit, 55, pkt_rval)); 4681 rval = 0; 4682 soc_reg_field_set(unit, WL_PORT_SHARED_LIMIT_CELLr, &rval, 4683 PORT_SHARED_LIMITf, 8192); 4684 SOC_IF_ERROR_RETURN(WRITE_WL_PORT_SHARED_LIMIT_CELLr(unit, rval)); 4685 rval = 0; 4686 soc_reg_field_set(unit, WL_PORT_SHARED_LIMIT_PACKETr, &rval, 4687 PORT_SHARED_LIMITf, 2048); 4688 SOC_IF_ERROR_RETURN(WRITE_WL_PORT_SHARED_LIMIT_PACKETr(unit, rval)); 4689 rval = 0; 4690 soc_reg_field_set(unit, PG_WL_RESET_OFFSET_CELLr, &rval, 4691 PG_RESET_OFFSETf, 4); 4692 SOC_IF_ERROR_RETURN(WRITE_PG_WL_RESET_OFFSET_CELLr(unit, 0, rval)); 4693 SOC_IF_ERROR_RETURN(WRITE_PG_WL_RESET_OFFSET_CELLr(unit, 1, rval)); 4694 rval = 0; 4695 soc_reg_field_set(unit, PG_WL_RESET_OFFSET_PACKETr, &rval, 4696 PG_RESET_OFFSETf, 4); 4697 SOC_IF_ERROR_RETURN 4698 (WRITE_PG_WL_RESET_OFFSET_PACKETr(unit, 0, rval)); 4699 SOC_IF_ERROR_RETURN 4700 (WRITE_PG_WL_RESET_OFFSET_PACKETr(unit, 1, rval)); 4701 rval = 0; 4702 soc_reg_field_set(unit, WL_DROP_POLICYr, &rval, 4703 DROP_PG0_1ST_FRAGMENTf, 1); 4704 soc_reg_field_set(unit, WL_DROP_POLICYr, &rval, 4705 DROP_PG0_ANY_FRAGMENTf, 1); 4706 soc_reg_field_set(unit, WL_DROP_POLICYr, &rval, 4707 DROP_PG0_NON_FRAGMENTf, 1); 4708 SOC_IF_ERROR_RETURN(WRITE_WL_DROP_POLICYr(unit, rval)); 4709 } 4710 } 4711 4712 /* Reserved space: Input port per-PG minimum 4713 * Use defalt value 0 4714 * With only one PG in use PORT_MIN should be sufficient */ 4715 4716 /* PG_WL_RESET_FLOOR_CELL, PG_WL_MIN_CELL and PG_WL_MIN_PACKET 4717 * are zeroes (default) */ 4718 4719 /* Reserved space: Input port per-PG headroom 4720 * Use only 1PG (highest priority PG for the port) */ 4721 cell_rval = 0; 4722 soc_reg_field_set(unit, PG_HDRM_LIMIT_CELLr, &cell_rval, PG_HDRM_LIMITf, 4723 TR2_MMU_PG_HDRM_LIMIT_CELLS); 4724 soc_reg_field_set(unit, PG_HDRM_LIMIT_CELLr, &cell_rval, PG_GEf, 1); 4725 pkt_rval = 0; 4726 soc_reg_field_set(unit, PG_HDRM_LIMIT_PACKETr, &pkt_rval, PG_HDRM_LIMITf, 4727 TR2_MMU_PG_HDRM_LIMIT_PKTS); 4728 PBMP_PORT_ITER(unit, port) { 4729 idx = SOC_PBMP_MEMBER(pbmp_8pg, port) ? TR2_MMU_NUM_PG - 1 : 1; 4730 SOC_IF_ERROR_RETURN(WRITE_PG_HDRM_LIMIT_CELLr(unit, port, idx, 4731 cell_rval)); 4732 SOC_IF_ERROR_RETURN(WRITE_PG_HDRM_LIMIT_PACKETr(unit, port, idx, 4733 pkt_rval)); 4734 } 4735 if (soc_feature(unit, soc_feature_internal_loopback)) { 4736 /* Loopback ingress */ 4737 idx = TR2_MMU_NUM_PG - 1; 4738 SOC_IF_ERROR_RETURN(WRITE_PG_HDRM_LIMIT_CELLr(unit, 54, idx, 4739 cell_rval)); 4740 SOC_IF_ERROR_RETURN(WRITE_PG_HDRM_LIMIT_PACKETr(unit, 54, idx, 4741 pkt_rval)); 4742 /* EP redirection */ 4743 SOC_IF_ERROR_RETURN(WRITE_PG_HDRM_LIMIT_CELLr(unit, 56, 1, 4744 cell_rval)); 4745 SOC_IF_ERROR_RETURN(WRITE_PG_HDRM_LIMIT_PACKETr(unit, 56, 1, 4746 pkt_rval)); 4747 /* WLAN */ 4748 if (soc_feature(unit, soc_feature_wlan)) { 4749 SOC_IF_ERROR_RETURN(WRITE_PG_HDRM_LIMIT_CELLr(unit, 55, 1, 4750 cell_rval)); 4751 SOC_IF_ERROR_RETURN(WRITE_PG_HDRM_LIMIT_PACKETr(unit, 55, 1, 4752 pkt_rval)); 4753 } 4754 } 4755 4756 /* Reserved space: Input port per-device headroom */ 4757 cell_rval = 0; 4758 soc_reg_field_set(unit, GLOBAL_HDRM_LIMITr, &cell_rval, GLOBAL_HDRM_LIMITf, 4759 TR2_MMU_GLOBAL_HDRM_LIMIT_CELLS); 4760 SOC_IF_ERROR_RETURN(WRITE_GLOBAL_HDRM_LIMITr(unit, cell_rval)); 4761 4762 /* Input port shared space - same as service pool zero */ 4763 cell_rval = 0; 4764 soc_reg_field_set(unit, BUFFER_CELL_LIMIT_SPr, &cell_rval, LIMITf, 4765 total_cells - in_reserved_cells - out_reserved_cells); 4766 SOC_IF_ERROR_RETURN(WRITE_BUFFER_CELL_LIMIT_SPr(unit, 0, cell_rval)); 4767 pkt_rval = 0; 4768 soc_reg_field_set(unit, BUFFER_PACKET_LIMIT_SPr, &pkt_rval, LIMITf, 4769 total_pkts - in_reserved_pkts - out_reserved_pkts); 4770 SOC_IF_ERROR_RETURN(WRITE_BUFFER_PACKET_LIMIT_SPr(unit, 0, pkt_rval)); 4771 4772 /* Input port per-port shared space limit - no limit */ 4773 cell_rval = 0; 4774 soc_reg_field_set(unit, PORT_SHARED_LIMIT_CELLr, &cell_rval, 4775 PORT_SHARED_LIMITf, total_cells - 1); 4776 pkt_rval = 0; 4777 soc_reg_field_set(unit, PORT_SHARED_LIMIT_PACKETr, &pkt_rval, 4778 PORT_SHARED_LIMITf, total_pkts - 1); 4779 PBMP_ALL_ITER(unit, port) { 4780 SOC_IF_ERROR_RETURN(WRITE_PORT_SHARED_LIMIT_CELLr(unit, port, 4781 cell_rval)); 4782 SOC_IF_ERROR_RETURN(WRITE_PORT_SHARED_LIMIT_PACKETr(unit, port, 4783 pkt_rval)); 4784 } 4785 if (soc_feature(unit, soc_feature_internal_loopback)) { 4786 /* EP redirection */ 4787 SOC_IF_ERROR_RETURN(WRITE_PORT_SHARED_LIMIT_CELLr(unit, 56, 4788 cell_rval)); 4789 SOC_IF_ERROR_RETURN(WRITE_PORT_SHARED_LIMIT_PACKETr(unit, 56, 4790 pkt_rval)); 4791 /* WLAN */ 4792 if (soc_feature(unit, soc_feature_wlan)) { 4793 SOC_IF_ERROR_RETURN(WRITE_PORT_SHARED_LIMIT_CELLr(unit, 55, 4794 cell_rval)); 4795 SOC_IF_ERROR_RETURN(WRITE_PORT_SHARED_LIMIT_PACKETr(unit, 55, 4796 pkt_rval)); 4797 } 4798 } 4799 4800 /* Input port per-PG reset offset 4801 * Use only 1PG (highest priority PG for the port) 4802 * Use default value 0 for CPU */ 4803 cell_rval = 0; 4804 soc_reg_field_set(unit, PG_RESET_OFFSET_CELLr, &cell_rval, 4805 PG_RESET_OFFSETf, TR2_MMU_PG_RESET_OFFSET_CELLS); 4806 pkt_rval = 0; 4807 soc_reg_field_set(unit, PG_RESET_OFFSET_PACKETr, &pkt_rval, 4808 PG_RESET_OFFSETf, TR2_MMU_PG_RESET_OFFSET_PKTS); 4809 PBMP_PORT_ITER(unit, port) { 4810 idx = SOC_PBMP_MEMBER(pbmp_8pg, port) ? TR2_MMU_NUM_PG - 1 : 1; 4811 SOC_IF_ERROR_RETURN(WRITE_PG_RESET_OFFSET_CELLr(unit, port, idx, 4812 cell_rval)); 4813 SOC_IF_ERROR_RETURN(WRITE_PG_RESET_OFFSET_PACKETr(unit, port, idx, 4814 pkt_rval)); 4815 } 4816 if (soc_feature(unit, soc_feature_internal_loopback)) { 4817 /* Loopback ingress */ 4818 idx = TR2_MMU_NUM_PG - 1; 4819 SOC_IF_ERROR_RETURN(WRITE_PG_RESET_OFFSET_CELLr(unit, 54, idx, 4820 cell_rval)); 4821 SOC_IF_ERROR_RETURN(WRITE_PG_RESET_OFFSET_PACKETr(unit, 54, idx, 4822 pkt_rval)); 4823 /* EP redirection */ 4824 SOC_IF_ERROR_RETURN(WRITE_PG_RESET_OFFSET_CELLr(unit, 56, 1, 4825 cell_rval)); 4826 SOC_IF_ERROR_RETURN(WRITE_PG_RESET_OFFSET_PACKETr(unit, 56, 1, 4827 pkt_rval)); 4828 /* WLAN */ 4829 if (soc_feature(unit, soc_feature_wlan)) { 4830 SOC_IF_ERROR_RETURN(WRITE_PG_RESET_OFFSET_CELLr(unit, 55, 1, 4831 cell_rval)); 4832 SOC_IF_ERROR_RETURN(WRITE_PG_RESET_OFFSET_PACKETr(unit, 55, 1, 4833 pkt_rval)); 4834 } 4835 } 4836 4837 /* Input port per-PG reset floor (cell). Use default value 0 */ 4838 4839 /* Input port priority XON disable */ 4840 4841 /* Input port max packet size in cells */ 4842 rval0 = 0; 4843 soc_reg_field_set(unit, PORT_MAX_PKT_SIZEr, &rval0, PORT_MAX_PKT_SIZEf, 4844 TR2_MMU_JUMBO_FRAME_CELLS); 4845 PBMP_ALL_ITER(unit, port) { 4846 SOC_IF_ERROR_RETURN(WRITE_PORT_MAX_PKT_SIZEr(unit, port, rval0)); 4847 } 4848 /* WLAN */ 4849 if (soc_feature(unit, soc_feature_wlan)) { 4850 SOC_IF_ERROR_RETURN(WRITE_PORT_MAX_PKT_SIZEr(unit, 55, rval0)); 4851 } 4852 4853 /* Input port per-PG threshold */ 4854 rval0 = 0; 4855 soc_reg_field_set(unit, PG_THRESH_SELr, &rval0, PG0_THRESH_SELf, 0x8); 4856 soc_reg_field_set(unit, PG_THRESH_SELr, &rval0, PG1_THRESH_SELf, 0x8); 4857 soc_reg_field_set(unit, PG_THRESH_SELr, &rval0, PG2_THRESH_SELf, 0x8); 4858 soc_reg_field_set(unit, PG_THRESH_SELr, &rval0, PG3_THRESH_SELf, 0x8); 4859 soc_reg_field_set(unit, PG_THRESH_SELr, &rval0, PG4_THRESH_SELf, 0x8); 4860 soc_reg_field_set(unit, PG_THRESH_SELr, &rval0, PG5_THRESH_SELf, 0x8); 4861 soc_reg_field_set(unit, PG_THRESH_SELr, &rval0, PG6_THRESH_SELf, 0x8); 4862 PBMP_ITER(pbmp_8pg, port) { 4863 SOC_IF_ERROR_RETURN(WRITE_PG_THRESH_SELr(unit, port, rval0)); 4864 } 4865 rval0 = 0; 4866 soc_reg_field_set(unit, PG_THRESH_SEL2r, &rval0, PG0_THRESH_SELf, 0x8); 4867 PBMP_ITER(pbmp_2pg, port) { 4868 SOC_IF_ERROR_RETURN(WRITE_PG_THRESH_SEL2r(unit, port, rval0)); 4869 } 4870 4871 idx = TR2_MMU_NUM_PG - 1; 4872 rval0 = 0; 4873 soc_reg_field_set(unit, PORT_PRI_GRP0r, &rval0, PRI0_GRPf, idx); 4874 soc_reg_field_set(unit, PORT_PRI_GRP0r, &rval0, PRI1_GRPf, idx); 4875 soc_reg_field_set(unit, PORT_PRI_GRP0r, &rval0, PRI2_GRPf, idx); 4876 soc_reg_field_set(unit, PORT_PRI_GRP0r, &rval0, PRI3_GRPf, idx); 4877 soc_reg_field_set(unit, PORT_PRI_GRP0r, &rval0, PRI4_GRPf, idx); 4878 soc_reg_field_set(unit, PORT_PRI_GRP0r, &rval0, PRI5_GRPf, idx); 4879 soc_reg_field_set(unit, PORT_PRI_GRP0r, &rval0, PRI6_GRPf, idx); 4880 soc_reg_field_set(unit, PORT_PRI_GRP0r, &rval0, PRI7_GRPf, idx); 4881 rval1 = 0; 4882 soc_reg_field_set(unit, PORT_PRI_GRP1r, &rval1, PRI8_GRPf, idx); 4883 soc_reg_field_set(unit, PORT_PRI_GRP1r, &rval1, PRI9_GRPf, idx); 4884 soc_reg_field_set(unit, PORT_PRI_GRP1r, &rval1, PRI10_GRPf, idx); 4885 soc_reg_field_set(unit, PORT_PRI_GRP1r, &rval1, PRI11_GRPf, idx); 4886 soc_reg_field_set(unit, PORT_PRI_GRP1r, &rval1, PRI12_GRPf, idx); 4887 soc_reg_field_set(unit, PORT_PRI_GRP1r, &rval1, PRI13_GRPf, idx); 4888 soc_reg_field_set(unit, PORT_PRI_GRP1r, &rval1, PRI14_GRPf, idx); 4889 soc_reg_field_set(unit, PORT_PRI_GRP1r, &rval1, PRI15_GRPf, idx); 4890 PBMP_ITER(pbmp_8pg, port) { 4891 SOC_IF_ERROR_RETURN(WRITE_PORT_PRI_GRP0r(unit, port, rval0)); 4892 SOC_IF_ERROR_RETURN(WRITE_PORT_PRI_GRP1r(unit, port, rval1)); 4893 } 4894 4895 rval0 = 0; 4896 soc_reg_field_set(unit, PORT_PRI_GRP2r, &rval0, PRI_GRPf, 0xffff); 4897 PBMP_ITER(pbmp_2pg, port) { 4898 SOC_IF_ERROR_RETURN(WRITE_PORT_PRI_GRP2r(unit, port, rval0)); 4899 } 4900 4901 /* Input port pause enable */ 4902 COMPILER_64_ZERO(rval64); 4903 soc_reg64_field32_set(unit, PORT_PAUSE_ENABLE_64r, &rval64, 4904 PORT_PAUSE_ENABLE_LOf, 4905 SOC_PBMP_WORD_GET(PBMP_ALL(unit), 0)); 4906 soc_reg64_field32_set(unit, PORT_PAUSE_ENABLE_64r, &rval64, 4907 PORT_PAUSE_ENABLE_HIf, 4908 SOC_PBMP_WORD_GET(PBMP_ALL(unit), 1)); 4909 SOC_IF_ERROR_RETURN(WRITE_PORT_PAUSE_ENABLE_64r(unit, rval64)); 4910 4911 /* 4912 * Output ports threshold 4913 */ 4914 /* Reserved space: Output port per-port per-COS minimum space */ 4915 cell_rval = 0; 4916 soc_reg_field_set(unit, OP_QUEUE_CONFIG_CELLr, &cell_rval, Q_MIN_CELLf, 4917 TR2_MMU_OUT_PORT_MIN_CELLS); 4918 soc_reg_field_set(unit, OP_QUEUE_CONFIG_CELLr, &cell_rval, 4919 Q_LIMIT_ENABLE_CELLf, 0x1); 4920 soc_reg_field_set(unit, OP_QUEUE_CONFIG_CELLr, &cell_rval, 4921 Q_LIMIT_DYNAMIC_CELLf, 0x1); 4922 soc_reg_field_set(unit, OP_QUEUE_CONFIG_CELLr, &cell_rval, 4923 Q_SHARED_LIMIT_CELLf, 2); /* alpha index 2 */ 4924 pkt_rval = 0; 4925 soc_reg_field_set(unit, OP_QUEUE_CONFIG_PACKETr, &pkt_rval, Q_MIN_PACKETf, 4926 TR2_MMU_OUT_PORT_MIN_PKTS); 4927 soc_reg_field_set(unit, OP_QUEUE_CONFIG_PACKETr, &pkt_rval, 4928 Q_LIMIT_ENABLE_PACKETf, 0x1); 4929 soc_reg_field_set(unit, OP_QUEUE_CONFIG_PACKETr, &pkt_rval, 4930 Q_LIMIT_DYNAMIC_PACKETf, 0x1); 4931 soc_reg_field_set(unit, OP_QUEUE_CONFIG_PACKETr, &pkt_rval, 4932 Q_SHARED_LIMIT_PACKETf, 2); /* alpha index 2 */ 4933 PBMP_ALL_ITER(unit, port) { 4934 count = IS_CPU_PORT(unit, port) ? 4935 SOC_INFO(unit).num_cpu_cosq : TR2_MMU_NUM_COS; 4936 for (idx = 0; idx < count; idx++) { 4937 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_CONFIG_CELLr(unit, port, idx, 4938 cell_rval)); 4939 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_CONFIG_PACKETr(unit, port, idx, 4940 pkt_rval)); 4941 } 4942 } 4943 if (soc_feature(unit, soc_feature_internal_loopback)) { 4944 /* EP redirection */ 4945 pkt_rval = 0; 4946 soc_reg_field_set(unit, OP_QUEUE_REDIRECT_XQ_CONFIG_PACKETr, &pkt_rval, 4947 Q_MIN_PACKETf, TR2_MMU_OUT_PORT_MIN_PKTS); 4948 soc_reg_field_set(unit, OP_QUEUE_REDIRECT_XQ_CONFIG_PACKETr, &pkt_rval, 4949 Q_LIMIT_DYNAMIC_PACKETf, 0x1); 4950 soc_reg_field_set(unit, OP_QUEUE_REDIRECT_XQ_CONFIG_PACKETr, &pkt_rval, 4951 Q_SHARED_ALPHA_PACKETf, 2); /* alpha index 2 */ 4952 rval = 0; 4953 soc_reg_field_set(unit, OP_QUEUE_REDIRECT_CONFIG_PACKETr, &rval, 4954 Q_MIN_PACKETf, TR2_MMU_OUT_PORT_MIN_PKTS); 4955 soc_reg_field_set(unit, OP_QUEUE_REDIRECT_CONFIG_PACKETr, &rval, 4956 Q_LIMIT_DYNAMIC_PACKETf, 0x1); 4957 soc_reg_field_set(unit, OP_QUEUE_REDIRECT_CONFIG_PACKETr, &rval, 4958 Q_SHARED_ALPHA_PACKETf, 2); /* alpha index 2 */ 4959 cell_rval = 0; 4960 soc_reg_field_set(unit, OP_QUEUE_REDIRECT_CONFIG_CELLr, &cell_rval, 4961 Q_MIN_CELLf, TR2_MMU_OUT_PORT_MIN_CELLS); 4962 soc_reg_field_set(unit, OP_QUEUE_REDIRECT_CONFIG_CELLr, &cell_rval, 4963 Q_LIMIT_DYNAMIC_CELLf, 0x1); 4964 soc_reg_field_set(unit, OP_QUEUE_REDIRECT_CONFIG_CELLr, &cell_rval, 4965 Q_SHARED_ALPHA_CELLf, 2); /* alpha index 2 */ 4966 4967 for (idx = 0; idx < TR2_MMU_NUM_COS; idx++) { 4968 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_REDIRECT_XQ_CONFIG_PACKETr 4969 (unit, 54, idx, pkt_rval)); 4970 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_REDIRECT_CONFIG_PACKETr 4971 (unit, 54, idx, rval)); 4972 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_REDIRECT_CONFIG_CELLr 4973 (unit, 54, idx, cell_rval)); 4974 } 4975 /* WLAN */ 4976 if (soc_feature(unit, soc_feature_wlan)) { 4977 /* Max out (disable) first fragment shared limits */ 4978 cell_rval = (1 << soc_reg_field_length(unit, 4979 OP_QUEUE_FIRST_FRAGMENT_CONFIG_CELLr, 4980 Q_SHARED_LIMIT_CELLf)) - 1; 4981 pkt_rval = (1 << soc_reg_field_length(unit, 4982 OP_QUEUE_FIRST_FRAGMENT_CONFIG_PACKETr, 4983 Q_SHARED_LIMIT_PACKETf)) - 1; 4984 for (idx = 0; idx < TR2_MMU_NUM_COS; idx++) { 4985 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_FIRST_FRAGMENT_CONFIG_PACKETr 4986 (unit, 54, idx, pkt_rval)); 4987 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_FIRST_FRAGMENT_CONFIG_CELLr 4988 (unit, 54, idx, cell_rval)); 4989 } 4990 } 4991 4992 /* 4993 * dedicate resource for EFP copy / True egress mirror 4994 */ 4995 pkt_rval = 0; 4996 4997 /* 4998 * 1k XQ pointer, dedicated resource for ep redirect 4999 */ 5000 disc_set = 1024 - (TR2_MMU_OUT_PORT_MIN_PKTS * TR2_MMU_NUM_COS); 5001 soc_reg_field_set(unit, OP_PORT_REDIRECT_XQ_DISC_SET_THD_PACKETr, 5002 &pkt_rval, DISCARD_SET_THD_PACKETf, disc_set); 5003 SOC_IF_ERROR_RETURN(WRITE_OP_PORT_REDIRECT_XQ_DISC_SET_THD_PACKETr 5004 (unit, 54, pkt_rval)); 5005 5006 pkt_rval = 0; 5007 soc_reg_field_set(unit, OP_PORT_REDIRECT_XQ_DISC_RESUME_THD_PACKETr, 5008 &pkt_rval, DISCARD_RESUME_THD_PACKETf, (disc_set - 50)); 5009 SOC_IF_ERROR_RETURN(WRITE_OP_PORT_REDIRECT_XQ_DISC_RESUME_THD_PACKETr 5010 (unit, 54, pkt_rval)); 5011 5012 /* 5013 * 1k pointers, dedicated resource for internal loopback 5014 */ 5015 pkt_rval = 0; 5016 soc_reg_field_set(unit, OP_PORT_REDIRECT_DISC_SET_THD_PACKETr, 5017 &pkt_rval, DISCARD_SET_THD_PACKETf, disc_set); 5018 SOC_IF_ERROR_RETURN(WRITE_OP_PORT_REDIRECT_DISC_SET_THD_PACKETr 5019 (unit, 54, pkt_rval)); 5020 5021 pkt_rval = 0; 5022 soc_reg_field_set(unit, OP_PORT_REDIRECT_DISC_RESUME_THD_PACKETr, 5023 &pkt_rval, DISCARD_RESUME_THD_PACKETf, (disc_set - 50)); 5024 SOC_IF_ERROR_RETURN(WRITE_OP_PORT_REDIRECT_DISC_RESUME_THD_PACKETr 5025 (unit, 54, pkt_rval)); 5026 5027 pkt_rval = 0; 5028 disc_set = (512 * 1024) - (TR2_MMU_OUT_PORT_MIN_CELLS * TR2_MMU_NUM_COS); 5029 soc_reg_field_set(unit, OP_PORT_REDIRECT_DISC_SET_THD_CELLr, 5030 &pkt_rval, DISCARD_SET_THD_CELLf, disc_set/128); 5031 SOC_IF_ERROR_RETURN(WRITE_OP_PORT_REDIRECT_DISC_SET_THD_CELLr 5032 (unit, 54, pkt_rval)); 5033 5034 pkt_rval = 0; 5035 soc_reg_field_set(unit, OP_PORT_REDIRECT_DISC_RESUME_THD_CELLr, 5036 &pkt_rval, DISCARD_RESUME_THD_CELLf, (disc_set - (16 * 1024))/128); 5037 SOC_IF_ERROR_RETURN(WRITE_OP_PORT_REDIRECT_DISC_RESUME_THD_CELLr 5038 (unit, 54, pkt_rval)); 5039 } 5040 5041 /* Output port per-port per-COS reset offset */ 5042 cell_rval = 0; 5043 soc_reg_field_set(unit, OP_QUEUE_RESET_OFFSET_CELLr, &cell_rval, 5044 Q_RESET_OFFSET_CELLf, TR2_MMU_OUT_RESET_OFFSET_CELLS); 5045 pkt_rval = 0; 5046 soc_reg_field_set(unit, OP_QUEUE_RESET_OFFSET_PACKETr, &pkt_rval, 5047 Q_RESET_OFFSET_PACKETf, TR2_MMU_OUT_RESET_OFFSET_PKTS); 5048 PBMP_ALL_ITER(unit, port) { 5049 count = IS_CPU_PORT(unit, port) ? 5050 SOC_INFO(unit).num_cpu_cosq : TR2_MMU_NUM_COS; 5051 for (idx = 0; idx < count; idx++) { 5052 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_RESET_OFFSET_CELLr(unit, port, 5053 idx, 5054 cell_rval)); 5055 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_RESET_OFFSET_PACKETr(unit, port, 5056 idx, 5057 pkt_rval)); 5058 } 5059 } 5060 5061 out_shared_cells = total_cells - out_reserved_cells; 5062 out_shared_pkts = total_pkts - out_reserved_pkts; 5063 5064 /* Output port per-device shared */ 5065 cell_rval = 0; 5066 soc_reg_field_set(unit, OP_BUFFER_SHARED_LIMIT_CELLr, &cell_rval, 5067 OP_BUFFER_SHARED_LIMIT_CELLf, out_shared_cells); 5068 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_SHARED_LIMIT_CELLr(unit, cell_rval)); 5069 pkt_rval = 0; 5070 soc_reg_field_set(unit, OP_BUFFER_SHARED_LIMIT_PACKETr, &pkt_rval, 5071 OP_BUFFER_SHARED_LIMIT_PACKETf, out_shared_pkts); 5072 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_SHARED_LIMIT_PACKETr(unit, pkt_rval)); 5073 5074 /* Output port per-device shared for YELLOW traffic */ 5075 cell_rval = 0; 5076 soc_reg_field_set(unit, OP_BUFFER_LIMIT_YELLOW_CELLr, &cell_rval, 5077 OP_BUFFER_LIMIT_YELLOW_CELLf, out_shared_cells >> 3); 5078 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_YELLOW_CELLr(unit, cell_rval)); 5079 pkt_rval = 0; 5080 soc_reg_field_set(unit, OP_BUFFER_LIMIT_YELLOW_PACKETr, &pkt_rval, 5081 OP_BUFFER_LIMIT_YELLOW_PACKETf, out_shared_pkts >> 3); 5082 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_YELLOW_PACKETr(unit, pkt_rval)); 5083 5084 /* Output port per-device shared for RED traffic */ 5085 cell_rval = 0; 5086 soc_reg_field_set(unit, OP_BUFFER_LIMIT_RED_CELLr, &cell_rval, 5087 OP_BUFFER_LIMIT_RED_CELLf, out_shared_cells >> 3); 5088 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_RED_CELLr(unit, cell_rval)); 5089 pkt_rval = 0; 5090 soc_reg_field_set(unit, OP_BUFFER_LIMIT_RED_PACKETr, &pkt_rval, 5091 OP_BUFFER_LIMIT_RED_PACKETf, out_shared_pkts >> 3); 5092 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_RED_PACKETr(unit, pkt_rval)); 5093 5094 /* 5095 * Output port per-port shared 5096 * Limit check disabled, however still keep code as reference 5097 * OP_SHARED_LIMIT set to 3/4 of total shared space 5098 * OP_SHARED_RESET_VALUE set to 1/2 of total shared space 5099 */ 5100 cell_rval = 0; 5101 soc_reg_field_set(unit, OP_PORT_CONFIG_CELLr, &cell_rval, 5102 OP_SHARED_LIMIT_CELLf, out_shared_cells * 3 / 4); 5103 soc_reg_field_set(unit, OP_PORT_CONFIG_CELLr, &cell_rval, 5104 OP_SHARED_RESET_VALUE_CELLf, out_shared_cells / 2); 5105 soc_reg_field_set(unit, OP_PORT_CONFIG_CELLr, &cell_rval, 5106 PORT_LIMIT_ENABLE_CELLf, 0); 5107 pkt_rval = 0; 5108 soc_reg_field_set(unit, OP_PORT_CONFIG_PACKETr, &pkt_rval, 5109 OP_SHARED_LIMIT_PACKETf, out_shared_pkts * 3 / 4); 5110 soc_reg_field_set(unit, OP_PORT_CONFIG_PACKETr, &pkt_rval, 5111 OP_SHARED_RESET_VALUE_PACKETf, out_shared_pkts / 2); 5112 soc_reg_field_set(unit, OP_PORT_CONFIG_PACKETr, &pkt_rval, 5113 PORT_LIMIT_ENABLE_PACKETf, 0); 5114 PBMP_ALL_ITER(unit, port) { 5115 SOC_IF_ERROR_RETURN(WRITE_OP_PORT_CONFIG_CELLr(unit, port, cell_rval)); 5116 SOC_IF_ERROR_RETURN(WRITE_OP_PORT_CONFIG_PACKETr(unit, port, 5117 pkt_rval)); 5118 } 5119 if (soc_feature(unit, soc_feature_internal_loopback)) { 5120 /* EP redirection */ 5121 5122 } 5123 5124 /* Output port per-port shared for YELLOW traffic */ 5125 cell_rval = 0; 5126 soc_reg_field_set(unit, OP_PORT_LIMIT_YELLOW_CELLr, &cell_rval, 5127 OP_PORT_LIMIT_YELLOW_CELLf, 5128 (out_shared_cells * 3 / 4) >> 3); 5129 pkt_rval = 0; 5130 soc_reg_field_set(unit, OP_PORT_LIMIT_YELLOW_PACKETr, &pkt_rval, 5131 OP_PORT_LIMIT_YELLOW_PACKETf, 5132 (out_shared_pkts * 3 / 4) >> 3); 5133 PBMP_ALL_ITER(unit, port) { 5134 SOC_IF_ERROR_RETURN(WRITE_OP_PORT_LIMIT_YELLOW_CELLr(unit, port, 5135 cell_rval)); 5136 SOC_IF_ERROR_RETURN(WRITE_OP_PORT_LIMIT_YELLOW_PACKETr(unit, port, 5137 pkt_rval)); 5138 } 5139 5140 /* Output port per-port shared for RED traffic */ 5141 cell_rval = 0; 5142 soc_reg_field_set(unit, OP_PORT_LIMIT_RED_CELLr, &cell_rval, 5143 OP_PORT_LIMIT_RED_CELLf, 5144 (out_shared_cells * 3 / 4) >> 3); 5145 pkt_rval = 0; 5146 soc_reg_field_set(unit, OP_PORT_LIMIT_RED_PACKETr, &pkt_rval, 5147 OP_PORT_LIMIT_RED_PACKETf, 5148 (out_shared_pkts * 3 / 4) >> 3); 5149 PBMP_ALL_ITER(unit, port) { 5150 SOC_IF_ERROR_RETURN(WRITE_OP_PORT_LIMIT_RED_CELLr(unit, port, 5151 cell_rval)); 5152 SOC_IF_ERROR_RETURN(WRITE_OP_PORT_LIMIT_RED_PACKETr(unit, port, 5153 pkt_rval)); 5154 } 5155 5156 /* Output port configuration */ 5157 rval0 = 0; 5158 soc_reg_field_set(unit, OP_THR_CONFIGr, &rval0, 5159 MOP_POLICYf, TR2_MMU_MOP_POLICY); 5160 soc_reg_field_set(unit, OP_THR_CONFIGr, &rval0, 5161 SOP_POLICYf, TR2_MMU_SOP_POLICY); 5162 SOC_IF_ERROR_RETURN(WRITE_OP_THR_CONFIGr(unit, rval0)); 5163 5164 /* Port enable */ 5165 COMPILER_64_ZERO(rval64); 5166 SOC_PBMP_CLEAR(temp); 5167 SOC_PBMP_ASSIGN(temp, PBMP_ALL(unit)); 5168 soc_reg64_field32_set(unit, INPUT_PORT_RX_ENABLE_64r, &rval64, 5169 INPUT_PORT_RX_ENABLE_LOf, 5170 SOC_PBMP_WORD_GET(temp, 0)); 5171 soc_reg64_field32_set(unit, INPUT_PORT_RX_ENABLE_64r, &rval64, 5172 INPUT_PORT_RX_ENABLE_HIf, 5173 SOC_PBMP_WORD_GET(temp, 1)); 5174 SOC_IF_ERROR_RETURN(WRITE_OUTPUT_PORT_RX_ENABLE_64r(unit, rval64)); 5175 SOC_PBMP_OR(temp, PBMP_MMU(unit)); 5176 soc_reg64_field32_set(unit, INPUT_PORT_RX_ENABLE_64r, &rval64, 5177 INPUT_PORT_RX_ENABLE_LOf, 5178 SOC_PBMP_WORD_GET(temp, 0)); 5179 soc_reg64_field32_set(unit, INPUT_PORT_RX_ENABLE_64r, &rval64, 5180 INPUT_PORT_RX_ENABLE_HIf, 5181 SOC_PBMP_WORD_GET(temp, 1)); 5182 SOC_IF_ERROR_RETURN(WRITE_INPUT_PORT_RX_ENABLE_64r(unit, rval64)); 5183 5184 /* Init ESM */ 5185 SOC_IF_ERROR_RETURN(READ_IESMIF_CONTROLr(unit, &rval)); 5186 soc_reg_field_set(unit, IESMIF_CONTROLr, &rval, EN_EXT_SEARCH_REQf, 0); 5187 SOC_IF_ERROR_RETURN(WRITE_IESMIF_CONTROLr(unit, rval)); 5188 if (soc_feature(unit, soc_feature_esm_support)) { 5189 /* 5190 * FP_LOCK is taken to synchronize Counter thread counter collection 5191 * where counter thread collects counters in external memory and 5192 * soc_mmu_init() which reintializes counters in external mmeory too. 5193 */ 5194 if (NULL != SOC_CONTROL(unit)->fp_lock) { 5195 sal_mutex_take(SOC_CONTROL(unit)->fp_lock, sal_mutex_FOREVER); 5196 } 5197 /* coverity[stack_use_callee] */ 5198 /* coverity[stack_use_overflow] */ 5199 rv = soc_triumph_esm_init(unit); 5200 5201 if (NULL != SOC_CONTROL(unit)->fp_lock) { 5202 sal_mutex_give(SOC_CONTROL(unit)->fp_lock); 5203 } 5204 5205 SOC_IF_ERROR_RETURN(rv); 5206 } 5207 5208 return SOC_E_NONE; 5209 } 5210 5211 int 5212 soc_triumph2_age_timer_get(int unit, int *age_seconds, int *enabled) 5213 { 5214 uint32 value; 5215 5216 SOC_IF_ERROR_RETURN(READ_L2_AGE_TIMERr(unit, &value)); 5217 *enabled = soc_reg_field_get(unit, L2_AGE_TIMERr, value, AGE_ENAf); 5218 *age_seconds = soc_reg_field_get(unit, L2_AGE_TIMERr, value, AGE_VALf); 5219 5220 return SOC_E_NONE; 5221 } 5222 5223 int 5224 soc_triumph2_age_timer_max_get(int unit, int *max_seconds) 5225 { 5226 *max_seconds = 5227 soc_reg_field_get(unit, L2_AGE_TIMERr, 0xffffffff, AGE_VALf); 5228 5229 return SOC_E_NONE; 5230 } 5231 5232 int 5233 soc_triumph2_age_timer_set(int unit, int age_seconds, int enable) 5234 { 5235 uint32 rval; 5236 5237 rval = 0; 5238 soc_reg_field_set(unit, L2_AGE_TIMERr, &rval, AGE_ENAf, enable); 5239 soc_reg_field_set(unit, L2_AGE_TIMERr, &rval, AGE_VALf, age_seconds); 5240 SOC_IF_ERROR_RETURN(WRITE_L2_AGE_TIMERr(unit, rval)); 5241 5242 if (soc_feature(unit, soc_feature_esm_support)) { 5243 soc_triumph_ext_age_timer_set(unit, age_seconds, enable); 5244 } 5245 5246 return SOC_E_NONE; 5247 } 5248 5249 void soc_triumph2_oam_handler_register(int unit, soc_triumph2_oam_handler_t handler) 5250 { 5251 oam_handler[unit] = handler; 5252 soc_intr_enable(unit, IRQ_MEM_FAIL); 5253 } 5254 5255 void 5256 soc_triumph2_oam_ser_handler_register(int unit, soc_triumph2_oam_ser_handler_t handler) 5257 { 5258 tr2_oam_ser_handler[unit] = handler; 5259 } 5260 5261 int 5262 soc_triumph2_oam_ser_process(int unit, soc_mem_t mem, int index) 5263 { 5264 if (tr2_oam_ser_handler[unit]) { 5265 return tr2_oam_ser_handler[unit](unit, mem, index); 5266 } 5267 5268 return SOC_E_UNAVAIL; 5269 } 5270 5271 void 5272 soc_triumph2_mem_config(int unit) 5273 { 5274 uint16 dev_id; 5275 uint8 rev_id; 5276 soc_persist_t *sop; 5277 5278 sop = SOC_PERSIST(unit); 5279 soc_cm_get_id(unit, &dev_id, &rev_id); 5280 5281 switch (dev_id) { 5282 case 0xb526: 5283 case 0xb521: 5284 case 0xb520: 5285 case 0xb522: 5286 case 0xb524: 5287 sop->memState[VLAN_SUBNETm].index_max = 255; 5288 sop->memState[VLAN_SUBNET_ONLYm].index_max = 255; 5289 sop->memState[VLAN_SUBNET_DATA_ONLYm].index_max = 255; 5290 5291 sop->memState[L2_USER_ENTRYm].index_max = 255; 5292 sop->memState[L2_USER_ENTRY_ONLYm].index_max = 255; 5293 sop->memState[L2_USER_ENTRY_DATA_ONLYm].index_max = 255; 5294 5295 sop->memState[ING_IPFIX_SESSION_TABLEm].index_max = 2047; 5296 sop->memState[EGR_IPFIX_SESSION_TABLEm].index_max = 2047; 5297 sop->memState[L3_DEFIPm].index_max = 6143; 5298 sop->memState[L3_DEFIP_ONLYm].index_max = 6143; 5299 sop->memState[L3_DEFIP_DATA_ONLYm].index_max = 6143; 5300 sop->memState[L3_DEFIP_HIT_ONLYm].index_max = 6143; 5301 /* Fall through */ 5302 case 0xb685: 5303 case 0xb689: 5304 sop->memState[MMU_CBPDATA0m].index_max = 0x5fff; 5305 sop->memState[MMU_CBPDATA1m].index_max = 0x5fff; 5306 sop->memState[MMU_CBPDATA2m].index_max = 0x5fff; 5307 sop->memState[MMU_CBPDATA3m].index_max = 0x5fff; 5308 sop->memState[MMU_CBPDATA4m].index_max = 0x5fff; 5309 sop->memState[MMU_CBPDATA5m].index_max = 0x5fff; 5310 sop->memState[MMU_CBPDATA6m].index_max = 0x5fff; 5311 sop->memState[MMU_CBPDATA7m].index_max = 0x5fff; 5312 sop->memState[MMU_CBPDATA8m].index_max = 0x5fff; 5313 sop->memState[MMU_CBPDATA9m].index_max = 0x5fff; 5314 sop->memState[MMU_CBPDATA10m].index_max = 0x5fff; 5315 sop->memState[MMU_CBPDATA11m].index_max = 0x5fff; 5316 sop->memState[MMU_CBPDATA12m].index_max = 0x5fff; 5317 sop->memState[MMU_CBPDATA13m].index_max = 0x5fff; 5318 sop->memState[MMU_CBPDATA14m].index_max = 0x5fff; 5319 sop->memState[MMU_CBPDATA15m].index_max = 0x5fff; 5320 sop->memState[MMU_CBPDATA16m].index_max = 0x5fff; 5321 sop->memState[MMU_CBPDATA17m].index_max = 0x5fff; 5322 sop->memState[MMU_CBPDATA18m].index_max = 0x5fff; 5323 sop->memState[MMU_CBPDATA19m].index_max = 0x5fff; 5324 sop->memState[MMU_CBPDATA20m].index_max = 0x5fff; 5325 sop->memState[MMU_CBPDATA21m].index_max = 0x5fff; 5326 sop->memState[MMU_CBPDATA22m].index_max = 0x5fff; 5327 sop->memState[MMU_CBPDATA23m].index_max = 0x5fff; 5328 sop->memState[MMU_CBPDATA24m].index_max = 0x5fff; 5329 sop->memState[MMU_CBPDATA25m].index_max = 0x5fff; 5330 sop->memState[MMU_CBPDATA26m].index_max = 0x5fff; 5331 sop->memState[MMU_CBPDATA27m].index_max = 0x5fff; 5332 sop->memState[MMU_CBPDATA28m].index_max = 0x5fff; 5333 sop->memState[MMU_CBPDATA29m].index_max = 0x5fff; 5334 sop->memState[MMU_CBPDATA30m].index_max = 0x5fff; 5335 sop->memState[MMU_CBPDATA31m].index_max = 0x5fff; 5336 sop->memState[FP_RANGE_CHECKm].index_max = 31; 5337 break; 5338 case 0xb534: 5339 case 0xb538: 5340 sop->memState[VLAN_SUBNETm].index_max = 255; 5341 sop->memState[VLAN_SUBNET_ONLYm].index_max = 255; 5342 sop->memState[VLAN_SUBNET_DATA_ONLYm].index_max = 255; 5343 5344 sop->memState[L2_USER_ENTRYm].index_max = 255; 5345 sop->memState[L2_USER_ENTRY_ONLYm].index_max = 255; 5346 sop->memState[L2_USER_ENTRY_DATA_ONLYm].index_max = 255; 5347 5348 sop->memState[ING_IPFIX_SESSION_TABLEm].index_max = 2047; 5349 sop->memState[EGR_IPFIX_SESSION_TABLEm].index_max = 2047; 5350 sop->memState[L3_DEFIPm].index_max = 6143; 5351 sop->memState[L3_DEFIP_ONLYm].index_max = 6143; 5352 sop->memState[L3_DEFIP_DATA_ONLYm].index_max = 6143; 5353 sop->memState[L3_DEFIP_HIT_ONLYm].index_max = 6143; 5354 sop->memState[FP_RANGE_CHECKm].index_max = 31; 5355 break; 5356 default: 5357 sop->memState[FP_RANGE_CHECKm].index_max = 31; 5358 break; 5359 } 5360 return; 5361 } 5362 5363 static soc_reg_t ctr_reg[117] = { 5364 ITPOKr, 5365 ITXPFr, 5366 ITXPPr, 5367 ITFCSr, 5368 ITUCr, 5369 ITMCAr, 5370 ITBCAr, 5371 ITOVRr, 5372 ITFRGr, 5373 ITPKTr, 5374 IT64r, 5375 IT127r, 5376 IT255r, 5377 IT511r, 5378 IT1023r, 5379 IT1518r, 5380 IT2047r, 5381 IT4095r, 5382 IT9216r, 5383 IT16383r, 5384 ITMAXr, 5385 ITUFLr, 5386 ITERRr, 5387 ITBYTr, 5388 IR64r, 5389 IR127r, 5390 IR255r, 5391 IR511r, 5392 IR1023r, 5393 IR1518r, 5394 IR2047r, 5395 IR4095r, 5396 IR9216r, 5397 IR16383r, 5398 IRMAXr, 5399 IRPKTr, 5400 IRFCSr, 5401 IRUCr, 5402 IRMCAr, 5403 IRBCAr, 5404 IRXPFr, 5405 IRXPPr, 5406 IRXUOr, 5407 IRJBRr, 5408 IROVRr, 5409 IRXCFr, 5410 IRFLRr, 5411 IRPOKr, 5412 IRMEGr, 5413 IRMEBr, 5414 IRBYTr, 5415 IRUNDr, 5416 IRFRGr, 5417 IRERBYTr, 5418 IRERPKTr, 5419 IRJUNKr, 5420 MAC_RXLLFCMSGCNTr, 5421 GR64r, 5422 GR127r, 5423 GR255r, 5424 GR511r, 5425 GR1023r, 5426 GR1518r, 5427 GRMGVr, 5428 GR2047r, 5429 GR4095r, 5430 GR9216r, 5431 GRPKTr, 5432 GRBYTr, 5433 GRMCAr, 5434 GRBCAr, 5435 GRFCSr, 5436 GRXCFr, 5437 GRXPFr, 5438 GRXUOr, 5439 GRALNr, 5440 GRFLRr, 5441 GRCDEr, 5442 GRFCRr, 5443 GROVRr, 5444 GRJBRr, 5445 GRMTUEr, 5446 GRUCr, 5447 GRPOKr, 5448 RRPKTr, 5449 GRUNDr, 5450 GRFRGr, 5451 RRBYTr, 5452 GT64r, 5453 GT127r, 5454 GT255r, 5455 GT511r, 5456 GT1023r, 5457 GT1518r, 5458 GTMGVr, 5459 GT2047r, 5460 GT4095r, 5461 GT9216r, 5462 GTPKTr, 5463 GTMCAr, 5464 GTBCAr, 5465 GTXPFr, 5466 GTJBRr, 5467 GTFCSr, 5468 GTXCFr, 5469 GTOVRr, 5470 GTDFRr, 5471 GTEDFr, 5472 GTSCLr, 5473 GTMCLr, 5474 GTLCLr, 5475 GTXCLr, 5476 GTFRGr, 5477 GTNCLr, 5478 GTBYTr, 5479 GTUCr, 5480 GTPOKr 5481 }; 5482 5483 static soc_reg_t mac_reg[19] = { 5484 EHG_RX_CONTROLr, 5485 EHG_TPIDr, 5486 EHG_TX_CONTROLr, 5487 EHG_TX_IPV4IDr, 5488 MAC_RXMACSAr, 5489 MAC_TXMACSAr, 5490 PAUSE_CONTROLr, 5491 MAC_0r, 5492 MAC_1r, 5493 XQPORT_INTR_ENABLEr, 5494 XQPORT_PARITY_CONTROLr, 5495 5496 MAC_RXLSSCTRLr, 5497 MAC_TXPSETHRr, 5498 MAC_TXPPPCTRLr, 5499 XPORT_CONFIGr, 5500 XP_EGR_PKT_DROP_CTLr, 5501 MAC_TXLLFCCTRLr, 5502 XQPORT_FORCE_DOUBLE_BIT_ERRORr, 5503 XQPORT_FORCE_SINGLE_BIT_ERRORr 5504 }; 5505 5506 int 5507 soc_tr2_xqport_mode_change(int unit, soc_port_t port, soc_mac_mode_t mode) 5508 { 5509 int rv = SOC_E_NONE, rv1; 5510 uint32 old_bits, bits, rval, val2, to_usec, max_sz, bitpos = 0; 5511 uint32 linkdown_tx = 0; 5512 uint64 rval64, max_sz64; 5513 soc_field_t xq_rst2 = INVALIDf; 5514 mac_driver_t *macd; 5515 int autoneg, autoneg_done, speed, duplex, enable, master; 5516 int pause_rx, pause_tx, dual_modid; 5517 int ctr; 5518 uint64 mac_val[19], ctr_val[117]; 5519 5520 soc_port_ability_t ability; 5521 5522 if (!SOC_PORT_VALID(unit, port)) { 5523 return SOC_E_PORT; 5524 } 5525 5526 sal_memset(&ability, 0, sizeof(soc_port_ability_t)); 5527 5528 SOC_IF_ERROR_RETURN(READ_XQPORT_MODE_REGr(unit, port, &rval)); 5529 old_bits = soc_reg_field_get(unit, XQPORT_MODE_REGr, rval, 5530 XQPORT_MODE_BITSf); 5531 bits = mode == SOC_MAC_MODE_10000 ? 2 : 1; 5532 if (bits == old_bits) { 5533 return SOC_E_NONE; 5534 } 5535 5536 to_usec = SAL_BOOT_QUICKTURN ? (250 * MILLISECOND_USEC) : 5537 (10 * MILLISECOND_USEC); 5538 5539 /* get current MAC and PHY settings */ 5540 SOC_IF_ERROR_RETURN(soc_phyctrl_auto_negotiate_get(unit, port, &autoneg, 5541 &autoneg_done)); 5542 SOC_IF_ERROR_RETURN(soc_phyctrl_ability_advert_get(unit, port, &ability)); 5543 SOC_IF_ERROR_RETURN(soc_phyctrl_speed_get(unit, port, &speed)); 5544 SOC_IF_ERROR_RETURN(soc_phyctrl_duplex_get(unit, port, &duplex)); 5545 SOC_IF_ERROR_RETURN(soc_phyctrl_enable_get(unit, port, &enable)); 5546 SOC_IF_ERROR_RETURN(soc_phyctrl_master_get(unit, port, &master)); 5547 rv1 = soc_phyctrl_control_get(unit, port, SOC_PHY_CONTROL_LINKDOWN_TRANSMIT, 5548 &linkdown_tx); 5549 if (rv1 != SOC_E_NONE && rv1 != SOC_E_UNAVAIL) { 5550 return rv1; 5551 } 5552 SOC_IF_ERROR_RETURN(soc_mac_probe(unit, port, &macd)); 5553 SOC_IF_ERROR_RETURN(MAC_PAUSE_GET(macd, unit, port, &pause_tx, &pause_rx)); 5554 SOC_IF_ERROR_RETURN(READ_MAC_CNTMAXSZr(unit, port, &max_sz64)); 5555 SOC_IF_ERROR_RETURN(READ_GPORT_CNTMAXSIZEr(unit, port, &max_sz)); 5556 5557 /* 1, Disable MAC TX and RX */ 5558 SOC_IF_ERROR_RETURN(MAC_ENABLE_SET(macd, unit, port, FALSE)); 5559 5560 /* 5. Block linkscan and sbus access */ 5561 soc_linkscan_pause(unit); 5562 COUNTER_LOCK(unit); 5563 5564 /* Store the mac regs */ 5565 for (ctr = 0; ctr < 19; ctr++) { 5566 SOC_COUNTER_IF_ERROR_RETURN 5567 (soc_reg_get(unit, mac_reg[ctr], port, 0, &mac_val[ctr])); 5568 } 5569 5570 /* Store the counters */ 5571 for (ctr = 0; ctr < 117; ctr++) { 5572 SOC_COUNTER_IF_ERROR_RETURN 5573 (soc_reg_get(unit, ctr_reg[ctr], port, 0, &ctr_val[ctr])); 5574 } 5575 5576 /* Egress disable */ 5577 rval = 0; 5578 soc_reg_field_set(unit, EGR_ENABLEr, &rval, PRT_ENABLEf, 0); 5579 SOC_COUNTER_IF_ERROR_RETURN(WRITE_EGR_ENABLEr(unit, port, rval)); 5580 5581 /* Hold the XQPORT hotswap reset */ 5582 switch (port) { 5583 case 30: 5584 bitpos = 6; 5585 xq_rst2 = XQ0_HOTSWAP_RST_Lf; 5586 break; 5587 case 34: 5588 bitpos = 7; 5589 xq_rst2 = XQ1_HOTSWAP_RST_Lf; 5590 break; 5591 case 38: 5592 bitpos = 8; 5593 xq_rst2 = XQ2_HOTSWAP_RST_Lf; 5594 break; 5595 case 42: 5596 bitpos = 9; 5597 xq_rst2 = XQ3_HOTSWAP_RST_Lf; 5598 break; 5599 case 46: 5600 bitpos = 10; 5601 xq_rst2 = XQ4_HOTSWAP_RST_Lf; 5602 break; 5603 case 50: 5604 bitpos = 11; 5605 xq_rst2 = XQ5_HOTSWAP_RST_Lf; 5606 break; 5607 default: 5608 break; 5609 } 5610 /* coverity[result_independent_of_operands] */ 5611 SOC_COUNTER_IF_ERROR_RETURN(READ_CMIC_SOFT_RESET_REG_2r(unit, &val2)); 5612 soc_reg_field_set(unit, CMIC_SOFT_RESET_REG_2r, &val2, 5613 xq_rst2, 0); 5614 /* coverity[result_independent_of_operands] */ 5615 SOC_COUNTER_IF_ERROR_RETURN(WRITE_CMIC_SOFT_RESET_REG_2r(unit, val2)); 5616 sal_usleep(to_usec); 5617 5618 /* Clear the ECRC register */ 5619 SOC_COUNTER_IF_ERROR_RETURN(WRITE_TOQ_EP_CREDITr(unit, port, 0)); 5620 5621 /* Reset the EP */ 5622 SOC_COUNTER_IF_ERROR_RETURN(READ_EDATABUF_XQP_FLEXPORT_CONFIGr(unit, &rval)); 5623 rval |= (1 << (bitpos - 6)); 5624 SOC_COUNTER_IF_ERROR_RETURN(WRITE_EDATABUF_XQP_FLEXPORT_CONFIGr(unit, rval)); 5625 sal_usleep(to_usec); 5626 SOC_COUNTER_IF_ERROR_RETURN(READ_EDATABUF_XQP_FLEXPORT_CONFIGr(unit, &rval)); 5627 if (mode == SOC_MAC_MODE_10000) { 5628 rval |= (1 << bitpos); 5629 } else { 5630 rval &= ~(1 << bitpos); 5631 } 5632 rval &= ~(1 << (bitpos - 6)); 5633 /* coverity[result_independent_of_operands] */ 5634 SOC_COUNTER_IF_ERROR_RETURN(WRITE_EDATABUF_XQP_FLEXPORT_CONFIGr(unit, rval)); 5635 sal_usleep(to_usec); 5636 5637 /* Bring the XQPORT block out of reset */ 5638 /* coverity[result_independent_of_operands] */ 5639 SOC_COUNTER_IF_ERROR_RETURN(READ_CMIC_SOFT_RESET_REG_2r(unit, &val2)); 5640 soc_reg_field_set(unit, CMIC_SOFT_RESET_REG_2r, &val2, 5641 xq_rst2, 1); 5642 /* coverity[result_independent_of_operands] */ 5643 SOC_COUNTER_IF_ERROR_RETURN(WRITE_CMIC_SOFT_RESET_REG_2r(unit, val2)); 5644 sal_usleep(to_usec); 5645 5646 /* Bring the hyperlite out of reset */ 5647 soc_xgxs_reset(unit, port); 5648 SOC_COUNTER_IF_ERROR_RETURN(soc_reg_field32_modify(unit, XQPORT_XGXS_NEWCTL_REGr, 5649 port, TXD1G_FIFO_RSTBf, 0xf)); 5650 5651 /* Change the XQPORT block mode */ 5652 SOC_COUNTER_IF_ERROR_RETURN(READ_XQPORT_MODE_REGr(unit, port, &rval)); 5653 soc_reg_field_set(unit, XQPORT_MODE_REGr, &rval, 5654 XQPORT_MODE_BITSf, bits); 5655 SOC_COUNTER_IF_ERROR_RETURN(WRITE_XQPORT_MODE_REGr(unit, port, rval)); 5656 5657 /* Egress Enable */ 5658 rval = 0; 5659 soc_reg_field_set(unit, EGR_ENABLEr, &rval, PRT_ENABLEf, 1); 5660 SOC_COUNTER_IF_ERROR_RETURN(WRITE_EGR_ENABLEr(unit, port, rval)); 5661 5662 /* Step 3: Port probe and initialization */ 5663 SOC_COUNTER_IF_ERROR_RETURN(soc_phyctrl_detach(unit, port)); 5664 SOC_COUNTER_IF_ERROR_RETURN(soc_phyctrl_probe(unit, port)); 5665 SOC_COUNTER_IF_ERROR_RETURN(soc_phyctrl_init(unit, port)); 5666 5667 /* restore PHY setting */ 5668 SOC_COUNTER_IF_ERROR_RETURN(soc_phyctrl_auto_negotiate_set(unit, port, autoneg)); 5669 SOC_COUNTER_IF_ERROR_RETURN(soc_phyctrl_ability_advert_set(unit, port, &ability)); 5670 SOC_COUNTER_IF_ERROR_RETURN(soc_phyctrl_speed_set(unit, port, speed)); 5671 SOC_COUNTER_IF_ERROR_RETURN(soc_phyctrl_duplex_set(unit, port, duplex)); 5672 SOC_COUNTER_IF_ERROR_RETURN(soc_phyctrl_enable_set(unit, port, enable)); 5673 SOC_COUNTER_IF_ERROR_RETURN(soc_phyctrl_master_set(unit, port, master)); 5674 rv1 = soc_phyctrl_control_set(unit, port, SOC_PHY_CONTROL_LINKDOWN_TRANSMIT, 5675 linkdown_tx); 5676 if (rv1 != SOC_E_NONE && rv1 != SOC_E_UNAVAIL) { 5677 return rv1; 5678 } 5679 5680 /* Need to reset the Bigmac to make registers accessible */ 5681 SOC_COUNTER_IF_ERROR_RETURN(READ_MAC_CTRLr(unit, port, &rval64)); 5682 soc_reg64_field32_set(unit, MAC_CTRLr, &rval64, TXRESETf, 0); 5683 soc_reg64_field32_set(unit, MAC_CTRLr, &rval64, RXRESETf, 0); 5684 SOC_COUNTER_IF_ERROR_RETURN(WRITE_MAC_CTRLr(unit, port, rval64)); 5685 5686 SOC_COUNTER_IF_ERROR_RETURN(MAC_INIT(macd, unit, port)); 5687 5688 /* Restore MAC regs */ 5689 for (ctr = 0; ctr < 19; ctr++) { 5690 SOC_IF_ERROR_RETURN 5691 (soc_reg_set(unit, mac_reg[ctr], port, 0, mac_val[ctr])); 5692 } 5693 5694 /* Restore previous MAC settings */ 5695 SOC_COUNTER_IF_ERROR_RETURN(MAC_ENABLE_SET(macd, unit, port, enable)); 5696 SOC_COUNTER_IF_ERROR_RETURN(MAC_PAUSE_SET(macd, unit, port, pause_tx, pause_rx)); 5697 5698 /* Restore XQPORT registers that may have been reset */ 5699 dual_modid = (NUM_MODID(unit) == 2) ? 1 : 0; 5700 SOC_COUNTER_IF_ERROR_RETURN(soc_reg_field32_modify(unit, XMODID_ENr, port, 5701 DUAL_MODID_ENf, dual_modid)); 5702 SOC_COUNTER_IF_ERROR_RETURN(WRITE_MAC_CNTMAXSZr(unit, port, max_sz64)); 5703 SOC_COUNTER_IF_ERROR_RETURN(WRITE_GPORT_CNTMAXSIZEr(unit, port, max_sz)); 5704 5705 /* Restore the counters */ 5706 for (ctr = 0; ctr < 117; ctr++) { 5707 SOC_COUNTER_IF_ERROR_RETURN 5708 (soc_reg_set(unit, ctr_reg[ctr], port, 0, ctr_val[ctr])); 5709 } 5710 5711 /* 8. Resume sbus access and linkscan */ 5712 COUNTER_UNLOCK(unit); 5713 soc_linkscan_continue(unit); 5714 return rv; 5715 } 5716 5717 /* 5718 * Function: 5719 * soc_tr2_l3_defip_index_map 5720 * Purpose: 5721 * Map an index within L3_DEFIP to the real h/w index by jumping over 5722 * unused blocks ( TCAM-3 , 3k - 4k) to make the table appear contiguous 5723 * Parameters: 5724 * unit - (IN) Device Number 5725 * index - (IN) Virtual index 5726 * mpls_port - (IN/OUT) mpls port information 5727 * Returns: 5728 * index - (OUT) Hardware index 5729 */ 5730 5731 int 5732 soc_tr2_l3_defip_index_map(int unit, int index) 5733 { 5734 if (index > 0x17FF) { 5735 return index; 5736 } 5737 if (index > 0xBFF) { 5738 return (index + 0x0400); 5739 } else { 5740 return index; 5741 } 5742 } 5743 5744 5745 /* 5746 * Function: 5747 * soc_tr2_ser_mem_test 5748 * Purpose: 5749 * Performs a SER test on a single TR2 memory 5750 * Parameters: 5751 * unit - (IN) Device Number 5752 * mem - (IN) The memory to test 5753 * test_type - (IN) How many indices in the memory to test 5754 */ 5755 int 5756 soc_tr2_ser_mem_test(int unit, soc_mem_t mem, _soc_ser_test_t test_type, int cmd) 5757 { 5758 int group, table, i, rv; 5759 _soc_parity_info_t *info; 5760 soc_mem_t memTable; 5761 soc_port_t block_port; 5762 soc_block_t blk; 5763 int testErrors = 0; 5764 /*Prevent compiler error for common function signature.*/ 5765 (void) cmd; 5766 /*TCAM_test*/ 5767 for (i = 0; _soc_tr2_ser_parity_info[i].mem != INVALIDm; i++) { 5768 if (_soc_tr2_ser_parity_info[i].mem == mem) { 5769 rv = ser_test_mem_pipe(unit, CMIC_SER_PROTECT_ADDR_RANGE_VALIDr, i, 5770 -1,_soc_tr2_ser_parity_info[i].mem, INVALIDf, test_type, 5771 MEM_BLOCK_ANY, REG_PORT_ANY, _SOC_ACC_TYPE_PIPE_ANY, &testErrors); 5772 if (rv != SOC_E_NONE) { 5773 LOG_CLI((BSL_META_U(unit, 5774 "Error during TCAM test. Aborting.\n"))); 5775 return rv; 5776 } 5777 } 5778 } 5779 /*H/W memory Test*/ 5780 for (group = 0; _soc_tr2_parity_group_info[group].cpi_bit; group++) { 5781 info = _soc_tr2_parity_group_info[group].info; 5782 5783 SOC_BLOCK_ITER(unit, blk, 5784 _soc_tr2_parity_group_info[group].blocktype) { 5785 if (_soc_triumph_parity_block_port(unit, blk, &block_port) < 0) { 5786 continue; 5787 } 5788 5789 for (table = 0; info[table].error_field != INVALIDf; table++) { 5790 memTable = info[table].mem; 5791 if (memTable == INVALIDm) { 5792 continue; 5793 } 5794 if (memTable == mem) { 5795 rv = ser_test_mem_pipe(unit,info[table].control_reg, -1, 5796 info[table].enable_field, mem, 5797 INVALIDf, test_type, blk, block_port, 5798 _SOC_ACC_TYPE_PIPE_ANY, &testErrors); 5799 if (rv != SOC_E_NONE) { 5800 LOG_CLI((BSL_META_U(unit, 5801 "Error during H/W test. Aborting.\n"))); 5802 return rv; 5803 } 5804 } 5805 } 5806 } 5807 } 5808 if (testErrors == 0) { 5809 LOG_CLI((BSL_META_U(unit, 5810 "SER Test passed on unit: %d for memory %s\n "), 5811 unit, SOC_MEM_NAME(unit,mem))); 5812 } 5813 else { 5814 LOG_CLI((BSL_META_U(unit, 5815 "SER Test failed on unit: %d for memory %s\n"), 5816 unit, SOC_MEM_NAME(unit,mem))); 5817 return SOC_E_MEMORY; 5818 } 5819 return SOC_E_NONE; 5820 } 5821 5822 5823 /* 5824 * Function: 5825 * soc_tr2_ser_test 5826 * Purpose: 5827 * Performs a SER test on all TR2 Memories 5828 * Parameters: 5829 * unit - (IN) Device Number 5830 * test_type - (IN) Determines how comprehensive of a test to run 5831 */ 5832 int 5833 soc_tr2_ser_test(int unit, _soc_ser_test_t test_type) 5834 { 5835 int i, rv; 5836 int numTCAMErr = 0; 5837 int numNACKErr = 0; 5838 /*This is a NACK test for hardware-monitored memories*/ 5839 rv = _soc_triumph2_mem_nack_error_test(unit, test_type, &numNACKErr); 5840 if (rv != SOC_E_NONE) { 5841 LOG_CLI((BSL_META_U(unit, 5842 "Error during H/W test. Aborting.\n"))); 5843 return rv; 5844 } 5845 /*This is a NACK test for TCAM memories*/ 5846 /*Test each TCAM memory*/ 5847 for(i = 0; i < COUNTOF(_soc_tr2_ser_parity_info) - 1; i++) { 5848 rv = ser_test_mem_pipe(unit, CMIC_SER_PROTECT_ADDR_RANGE_VALIDr, i, -1, 5849 _soc_tr2_ser_parity_info[i].mem, INVALIDf, test_type, MEM_BLOCK_ANY, 5850 REG_PORT_ANY, _SOC_ACC_TYPE_PIPE_ANY, &numTCAMErr); 5851 if (rv != SOC_E_NONE) { 5852 LOG_CLI((BSL_META_U(unit, 5853 "Error during TCAM test. Aborting.\n"))); 5854 return rv; 5855 } 5856 } 5857 LOG_CLI((BSL_META_U(unit, 5858 "Total H/W parity errors on unit %d: %d\n"),unit, numNACKErr)); 5859 LOG_CLI((BSL_META_U(unit, 5860 "Total TCAM errors on unit %d: %d\n"), unit, numTCAMErr)); 5861 return SOC_E_NONE; 5862 } 5863 5864 /* 5865 * Function: 5866 * soc_tr2_ser_mem_test 5867 * Purpose: 5868 * Performs a SER test on a single TR2 memory 5869 * Parameters: 5870 * unit - (IN) Device Number 5871 * mem - (IN) The memory to test 5872 * test_type - (IN) How many indices in the memory to test 5873 */ 5874 int 5875 soc_tr2_ser_inject_error(int unit, uint32 flags, soc_mem_t mem, int pipeTarget, 5876 int block, int index) 5877 { 5878 int group, table, i; 5879 _soc_parity_info_t *info; 5880 soc_mem_t memTable; 5881 soc_port_t block_port; 5882 soc_block_t blk; 5883 ser_test_data_t test_data; 5884 uint32 tmp_entry[SOC_MAX_MEM_WORDS], fieldData[SOC_MAX_REG_FIELD_WORDS]; 5885 5886 sal_memset(&test_data, 0, sizeof(test_data)); 5887 test_data.index = index; 5888 test_data.index_fv = index; 5889 test_data.entry_buf = tmp_entry; 5890 test_data.field_buf = fieldData; 5891 /*TCAM_test*/ 5892 for (i = 0; _soc_tr2_ser_parity_info[i].mem != INVALIDm; i++) { 5893 if (_soc_tr2_ser_parity_info[i].mem == mem) { 5894 test_data.mem = mem; 5895 test_data.mem_fv = mem; 5896 test_data.tcam_parity_bit = i; 5897 test_data.parity_enable_reg = CMIC_SER_PROTECT_ADDR_RANGE_VALIDr; 5898 test_data.parity_enable_field = INVALIDf; 5899 test_data.mem_block = MEM_BLOCK_ANY; 5900 test_data.port = REG_PORT_ANY; 5901 test_data.acc_type = _SOC_ACC_TYPE_PIPE_ANY; 5902 test_data.mem_info = &SOC_MEM_INFO(unit,test_data.mem); 5903 /*Read the memory for successful injection*/ 5904 SOC_IF_ERROR_RETURN(ser_test_mem_read(unit, 0, &test_data)); 5905 /*Disable parity*/ 5906 SOC_IF_ERROR_RETURN(_ser_test_parity_control(unit, &test_data, 0)); 5907 /*Inject error*/ 5908 SOC_IF_ERROR_RETURN(soc_ser_test_inject_full(unit, flags, &test_data)); 5909 /*Enable parity*/ 5910 SOC_IF_ERROR_RETURN(_ser_test_parity_control(unit, &test_data, 1)); 5911 return SOC_E_NONE; 5912 5913 } 5914 } 5915 /*H/W memory Test*/ 5916 for (group = 0; _soc_tr2_parity_group_info[group].cpi_bit; group++) { 5917 info = _soc_tr2_parity_group_info[group].info; 5918 5919 SOC_BLOCK_ITER(unit, blk, 5920 _soc_tr2_parity_group_info[group].blocktype) { 5921 if (_soc_triumph_parity_block_port(unit, blk, &block_port) < 0) { 5922 continue; 5923 } 5924 5925 for (table = 0; info[table].error_field != INVALIDf; table++) { 5926 memTable = info[table].mem; 5927 if (memTable == INVALIDm) { 5928 continue; 5929 } 5930 if (memTable == mem) { 5931 if((blk == block) || (block == MEM_BLOCK_ANY)) 5932 { 5933 /*Inject error*/ 5934 test_data.mem = mem; 5935 test_data.mem_fv = mem; 5936 test_data.tcam_parity_bit = -1; 5937 test_data.parity_enable_reg = info[table].control_reg; 5938 test_data.parity_enable_field = info[table].enable_field; 5939 test_data.mem_block = blk; 5940 test_data.port = block_port; 5941 test_data.acc_type = _SOC_ACC_TYPE_PIPE_ANY; 5942 test_data.mem_info = &SOC_MEM_INFO(unit,test_data.mem); 5943 /*Read the memory for successful injection*/ 5944 SOC_IF_ERROR_RETURN(ser_test_mem_read(unit, 0, &test_data)); 5945 /*Disable parity*/ 5946 SOC_IF_ERROR_RETURN(_ser_test_parity_control(unit, &test_data, 0)); 5947 /*Inject error*/ 5948 SOC_IF_ERROR_RETURN(soc_ser_test_inject_full(unit, flags, &test_data)); 5949 /*Enable parity*/ 5950 SOC_IF_ERROR_RETURN(_ser_test_parity_control(unit, &test_data, 1)); 5951 } 5952 } 5953 } 5954 } 5955 } 5956 return SOC_E_NONE; 5957 } 5958 5959 #endif /* SOC_TRIUMPH2_SUPPORT */