port.c (22840B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: port.c 8 * Purpose: TD3 SOC Port driver. 9 */ 10 11 #include <shared/bsl.h> 12 #include <soc/error.h> 13 #include <soc/defs.h> 14 #include <soc/tdm/core/tdm_top.h> 15 16 #if defined(BCM_TRIDENT3_SUPPORT) 17 #include <soc/tdm/trident3/tdm_td3_defines.h> 18 #include <soc/flexport/trident3/trident3_flexport_defines.h> 19 #include <soc/trident3.h> 20 #include <soc/scache.h> 21 #include <soc/types.h> 22 23 #define TD3_PORTS_PER_TSC 4 24 25 #ifdef BCM_WARM_BOOT_SUPPORT 26 27 #define SOC_FLEXPORT_WB_VERSION_1_0 SOC_SCACHE_VERSION(1,0) 28 #define SOC_FLEXPORT_WB_DEFAULT_VERSION SOC_FLEXPORT_WB_VERSION_1_0 29 30 extern int 31 _soc_td3_port_speed_cap[SOC_MAX_NUM_DEVICES][132]; 32 #endif 33 /* 34 * Function: 35 * soc_td3_max_lr_bandwidth 36 * Purpose: 37 * Get the max line rate bandwidth per pipeline 38 * Parameters: 39 * unit - (IN) Unit number. 40 * max_lr_bw - (OUT) Max line rate bandwidth (Gbps). 41 * Returns: 42 * BCM_E_xxx 43 * Notes: 44 */ 45 int 46 soc_td3_max_lr_bandwidth(int unit, uint32 *max_lr_bw) 47 { 48 soc_info_t *si = &SOC_INFO(unit); 49 int second_mgmt_enable = 0; 50 int rv = SOC_E_NONE; 51 52 second_mgmt_enable = SOC_PBMP_MEMBER(PBMP_MANAGEMENT(unit), 128) ? 1 : 0; 53 54 switch (si->frequency) { 55 case 1700: 56 *max_lr_bw = 1112; 57 break; 58 case 1625: 59 *max_lr_bw = 1062; 60 break; 61 case 1525: 62 *max_lr_bw = 994; 63 break; 64 case 1425: 65 *max_lr_bw = 927; 66 break; 67 case 1325: 68 *max_lr_bw = 860; 69 break; 70 case 1275: 71 *max_lr_bw = 826; 72 break; 73 case 1012: 74 *max_lr_bw = 650; 75 break; 76 case 850: 77 *max_lr_bw = 541; 78 break; 79 default: 80 *max_lr_bw = 0; 81 rv = SOC_E_INTERNAL; 82 break; 83 } 84 85 if (second_mgmt_enable && *max_lr_bw > 0) { 86 *max_lr_bw = *max_lr_bw - 10; 87 } 88 return rv; 89 } 90 91 /* 92 * Function: 93 * soc_td3_max_lr_cal_len 94 * Purpose: 95 * Get the max cal length per pipe 96 * Parameters: 97 * unit - (IN) Unit number. 98 * eth - (IN) ethernet mode 99 * max_lr_cal - (OUT) Max line rate cal (slots). 100 * Returns: 101 * BCM_E_xxx 102 * Notes: 103 */ 104 int 105 soc_td3_max_lr_cal_len(int unit, uint32 *max_lr_cal, int eth) 106 { 107 soc_info_t *si = &SOC_INFO(unit); 108 int second_mgmt_enable = 0; 109 int rv = SOC_E_NONE; 110 111 second_mgmt_enable = SOC_PBMP_MEMBER(PBMP_MANAGEMENT(unit), 128) ? 1 : 0; 112 113 switch (si->frequency) { 114 case 1700: 115 *max_lr_cal = eth ? 456 : 430; 116 break; 117 case 1625: 118 *max_lr_cal = eth ? 436 : 411; 119 break; 120 case 1525: 121 *max_lr_cal = eth ? 409 : 386; 122 break; 123 case 1425: 124 *max_lr_cal = eth ? 383 : 361; 125 break; 126 case 1325: 127 *max_lr_cal = eth ? 356 : 335; 128 break; 129 case 1275: 130 *max_lr_cal = eth ? 342 : 323; 131 break; 132 case 1012: 133 *max_lr_cal = eth ? 272 : 256; 134 break; 135 case 850: 136 *max_lr_cal = eth ? 228 : 215; 137 break; 138 default: 139 *max_lr_cal = 0; 140 rv = SOC_E_INTERNAL; 141 break; 142 } 143 if (*max_lr_cal > 0) { 144 *max_lr_cal = *max_lr_cal - 12; /* ANCL */ 145 } 146 if (second_mgmt_enable && *max_lr_cal > 0) { 147 *max_lr_cal = *max_lr_cal - 4; 148 } 149 return rv; 150 } 151 152 /* 153 * Function: 154 * soc_td3_support_speeds 155 * Purpose: 156 * Get the supported speed of port for specified lanes 157 * Parameters: 158 * unit - (IN) Unit number. 159 * lanes - (IN) Number of Lanes for the port. 160 * speed_mask - (IN) Bitmap for supported speed. 161 * Returns: 162 * BCM_E_xxx 163 * Notes: 164 */ 165 int 166 soc_td3_support_speeds(int unit, int lanes, uint32 *speed_mask) 167 { 168 soc_info_t *si = &SOC_INFO(unit); 169 uint32 speed_valid; 170 171 switch(lanes) { 172 case 1: 173 /* Single Lane Port Speeds */ 174 speed_valid = SOC_PA_SPEED_1000MB | SOC_PA_SPEED_10GB | 175 SOC_PA_SPEED_11GB | SOC_PA_SPEED_25GB | 176 SOC_PA_SPEED_27GB; 177 break; 178 case 2: 179 /* Dual Lane Port Speeds */ 180 speed_valid = SOC_PA_SPEED_20GB | SOC_PA_SPEED_21GB | 181 SOC_PA_SPEED_40GB | SOC_PA_SPEED_42GB | 182 SOC_PA_SPEED_50GB | SOC_PA_SPEED_53GB; 183 break; 184 case 4: 185 /* Quad Lane Port Speeds */ 186 speed_valid = SOC_PA_SPEED_40GB | SOC_PA_SPEED_42GB | 187 SOC_PA_SPEED_100GB | SOC_PA_SPEED_106GB; 188 break; 189 default: 190 return SOC_E_PARAM; 191 } 192 193 if (FALSE == si->fabric_port_enable) { 194 /* Ethernet-optimized Calendar doesn't support any HG speed */ 195 speed_valid &= ~(SOC_PA_SPEED_11GB | SOC_PA_SPEED_21GB | 196 SOC_PA_SPEED_27GB | SOC_PA_SPEED_42GB | 197 SOC_PA_SPEED_53GB | SOC_PA_SPEED_106GB); 198 } 199 200 if (si->frequency < 1300) { 201 speed_valid &= ~(SOC_PA_SPEED_100GB | SOC_PA_SPEED_106GB); 202 } 203 204 if (si->frequency < 1012) { 205 speed_valid &= ~(SOC_PA_SPEED_50GB | SOC_PA_SPEED_53GB); 206 speed_valid &= ~(SOC_PA_SPEED_25GB | SOC_PA_SPEED_27GB); 207 } 208 209 if (si->frequency < 850) { 210 speed_valid &= ~(SOC_PA_SPEED_40GB | SOC_PA_SPEED_42GB); 211 speed_valid &= ~(SOC_PA_SPEED_20GB | SOC_PA_SPEED_21GB); 212 speed_valid &= ~(SOC_PA_SPEED_10GB | SOC_PA_SPEED_11GB); 213 } 214 215 *speed_mask = speed_valid; 216 217 return SOC_E_NONE; 218 } 219 220 #ifdef BCM_WARM_BOOT_SUPPORT 221 int soc_td3_flexport_scache_allocate(int unit) 222 { 223 int rv = SOC_E_NONE; 224 uint8 *flexport_scache_ptr; 225 soc_scache_handle_t scache_handle; 226 uint32 alloc_get = 0; 227 uint32 alloc_size = 0; 228 int stable_size; 229 int default_ver = SOC_FLEXPORT_WB_DEFAULT_VERSION; 230 231 alloc_size = (sizeof(int) * TRIDENT3_PHY_PORTS_PER_DEV) + /* phy to logical*/ 232 (sizeof(int) * TRIDENT3_PHY_PORTS_PER_DEV) + /* phy to mmu */ 233 (sizeof(int) * TRIDENT3_PHY_PORTS_PER_DEV) + /* logical to phy */ 234 (sizeof(int) * TRIDENT3_PHY_PORTS_PER_DEV) + /* max port speed */ 235 (sizeof(int) * TRIDENT3_PHY_PORTS_PER_DEV) + /* init port speed */ 236 (sizeof(int) * TRIDENT3_PHY_PORTS_PER_DEV) + /* num of lanes */ 237 (sizeof(pbmp_t)) + /* HG bitmap */ 238 (sizeof(pbmp_t)); /* Disabled bitmap */ 239 240 alloc_get = alloc_size; 241 242 SOC_SCACHE_HANDLE_SET(scache_handle, unit, SOC_SCACHE_FLEXIO_HANDLE, 0); 243 /* check to see if an scache table has been configured */ 244 rv = soc_stable_size_get(unit, &stable_size); 245 if (SOC_FAILURE(rv) || stable_size <= 0) { 246 return rv; 247 } 248 249 rv = soc_versioned_scache_ptr_get(unit, scache_handle, 250 TRUE, &alloc_get, 251 &flexport_scache_ptr, 252 default_ver, 253 NULL); 254 255 if (rv == SOC_E_CONFIG) { 256 /* Probably Level1 */ 257 return SOC_E_NONE; 258 } 259 /* NotRequired but just to confirm Get the pointer for the Level 2 cache */ 260 if (alloc_get != alloc_size) { 261 /* Expected size doesn't match retrieved size */ 262 LOG_ERROR(BSL_LS_SOC_COMMON, 263 (BSL_META_U(unit, 264 "ERROR: scache memory for flexport size mismatch" 265 "%s()[LINE:%d] DONE \n"),FUNCTION_NAME(), __LINE__)); 266 return SOC_E_INTERNAL; 267 } 268 269 if (NULL == flexport_scache_ptr) { 270 LOG_ERROR(BSL_LS_SOC_COMMON, 271 (BSL_META_U(unit, 272 "ERROR: scache memory not allocated for flexport" 273 "%s()[LINE:%d] DONE \n"),FUNCTION_NAME(), __LINE__)); 274 return SOC_E_MEMORY; 275 } 276 LOG_VERBOSE(BSL_LS_SOC_COMMON, 277 (BSL_META_U(unit, 278 "%s()[LINE:%d] DONE \n"),FUNCTION_NAME(), __LINE__)); 279 return SOC_E_NONE; 280 281 } 282 283 /* 284 * Function: 285 * soc_td3_flexport_scache_sync 286 * Purpose: 287 * Record Port info that maybe changed during flexport for Level 2 WB 288 * 289 * Warm Boot Version Map: 290 * 291 * BCM_WB_VERSION_1_0 292 * port_speed_max 293 * port_init_speed 294 * port_num_lanes 295 * disabled_bitmap 296 * 297 * Parameters: 298 * unit - StrataSwitch unit number. 299 * Returns: 300 * SOC_E_XXX 301 */ 302 int soc_td3_flexport_scache_sync(int unit) 303 { 304 uint8 *flexport_scache_ptr; 305 soc_scache_handle_t scache_handle; 306 uint32 alloc_get = 0; 307 uint32 alloc_size = 0; 308 uint32 var_size = 0; 309 soc_info_t *si = &SOC_INFO(unit); 310 uint32 scache_offset=0; 311 int rv = 0; 312 313 alloc_size = (sizeof(int) * TRIDENT3_PHY_PORTS_PER_DEV) + /* phy to logical*/ 314 (sizeof(int) * TRIDENT3_PHY_PORTS_PER_DEV) + /* phy to mmu */ 315 (sizeof(int) * TRIDENT3_PHY_PORTS_PER_DEV) + /* logical to phy */ 316 (sizeof(int) * TRIDENT3_PHY_PORTS_PER_DEV) + /* max port speed */ 317 (sizeof(int) * TRIDENT3_PHY_PORTS_PER_DEV) + /* init port speed */ 318 (sizeof(int) * TRIDENT3_PHY_PORTS_PER_DEV) + /* num of lanes */ 319 (sizeof(pbmp_t)) + /* HG bitmap */ 320 (sizeof(pbmp_t)); /* Disabled bitmap */ 321 322 alloc_get = alloc_size; 323 324 SOC_SCACHE_HANDLE_SET(scache_handle, unit, SOC_SCACHE_FLEXIO_HANDLE, 0); 325 rv = soc_versioned_scache_ptr_get(unit, scache_handle, 326 FALSE, &alloc_get, 327 &flexport_scache_ptr, 328 SOC_FLEXPORT_WB_DEFAULT_VERSION, 329 NULL); 330 if (rv == SOC_E_NOT_FOUND) { 331 /* Probably Level1 */ 332 return SOC_E_NONE; 333 } 334 if (alloc_get != alloc_size) { 335 /* Expected size doesn't match retrieved size */ 336 LOG_ERROR(BSL_LS_SOC_COMMON, 337 (BSL_META_U(unit, 338 "ERROR: scache memory for flexport size mismatch" 339 "%s()[LINE:%d] DONE \n"),FUNCTION_NAME(), __LINE__)); 340 return SOC_E_INTERNAL; 341 } 342 if (NULL == flexport_scache_ptr) { 343 LOG_ERROR(BSL_LS_SOC_COMMON, 344 (BSL_META_U(unit, 345 "ERROR: scache memory not allocated for flexport" 346 "%s()[LINE:%d] DONE \n"),FUNCTION_NAME(), __LINE__)); 347 return SOC_E_MEMORY; 348 } 349 350 /* Physical to logical port mapping */ 351 var_size = sizeof(int) * TRIDENT3_PHY_PORTS_PER_DEV; 352 sal_memcpy(&flexport_scache_ptr[scache_offset], 353 si->port_p2l_mapping, var_size); 354 scache_offset += var_size; 355 356 357 /* Physical to MMU port mapping */ 358 var_size = sizeof(int) * TRIDENT3_PHY_PORTS_PER_DEV; 359 sal_memcpy(&flexport_scache_ptr[scache_offset], 360 si->port_p2m_mapping, var_size); 361 scache_offset += var_size; 362 363 /* Logical to Physical port mapping */ 364 var_size = sizeof(int) * TRIDENT3_PHY_PORTS_PER_DEV; 365 sal_memcpy(&flexport_scache_ptr[scache_offset], 366 si->port_l2p_mapping, var_size); 367 scache_offset += var_size; 368 369 /* Max port speed */ 370 var_size = sizeof(int) * TRIDENT3_PHY_PORTS_PER_DEV; 371 372 sal_memcpy(&flexport_scache_ptr[scache_offset], 373 si->port_speed_max, var_size); 374 scache_offset += var_size; 375 376 /* Init port speed */ 377 sal_memcpy(&flexport_scache_ptr[scache_offset], 378 si->port_init_speed, var_size); 379 scache_offset += var_size; 380 381 /* Num of lanes */ 382 sal_memcpy(&flexport_scache_ptr[scache_offset], 383 si->port_num_lanes, var_size); 384 scache_offset += var_size; 385 386 /* HG Bitmap */ 387 sal_memcpy(&flexport_scache_ptr[scache_offset], 388 &si->hg.bitmap, 389 sizeof(pbmp_t)); 390 scache_offset += sizeof(pbmp_t); 391 392 /* Disabled Port Bitmap */ 393 sal_memcpy(&flexport_scache_ptr[scache_offset], 394 &si->all.disabled_bitmap, 395 sizeof(pbmp_t)); 396 scache_offset += sizeof(pbmp_t); 397 398 LOG_VERBOSE(BSL_LS_SOC_COMMON, 399 (BSL_META_U(unit, 400 "%s()[LINE:%d] \n"),FUNCTION_NAME(), __LINE__)); 401 402 return SOC_E_NONE; 403 } 404 405 /* 406 * Function: 407 * soc_td3_flexport_scache_recovery 408 * Purpose: 409 * Recover Port info that maybe changed during flexport for Level 2 WB 410 * 411 * Warm Boot Version Map: 412 * 413 * BCM_WB_VERSION_1_0 414 * port_p2l_mapping 415 * port_l2p_mapping 416 * port_speed_max 417 * port_init_speed 418 * port_num_lanes 419 * disabled_bitmap 420 * 421 * Parameters: 422 * unit - StrataSwitch unit number. 423 * Returns: 424 * SOC_E_XXX 425 */ 426 int soc_td3_flexport_scache_recovery(int unit) 427 { 428 uint32 alloc_get = 0, phy_port =0; 429 uint32 alloc_size = 0; 430 int rv = SOC_E_NONE; 431 uint8 *flexport_scache_ptr = NULL; 432 soc_scache_handle_t scache_handle; 433 uint32 scache_offset=0; 434 uint32 var_size = 0; 435 uint16 recovered_ver = 0, pipe=0; 436 soc_info_t *si = &SOC_INFO(unit); 437 438 alloc_size = (sizeof(int) * TRIDENT3_PHY_PORTS_PER_DEV) + /* phy to logical*/ 439 (sizeof(int) * TRIDENT3_PHY_PORTS_PER_DEV) + /* phy to mmu */ 440 (sizeof(int) * TRIDENT3_PHY_PORTS_PER_DEV) + /* logical to phy */ 441 (sizeof(int) * TRIDENT3_PHY_PORTS_PER_DEV) + /* max port speed */ 442 (sizeof(int) * TRIDENT3_PHY_PORTS_PER_DEV) + /* init port speed */ 443 (sizeof(int) * TRIDENT3_PHY_PORTS_PER_DEV) + /* num of lanes */ 444 (sizeof(pbmp_t)) + /* HG bitmap */ 445 (sizeof(pbmp_t)); /* Disabled bitmap */ 446 447 alloc_get = alloc_size; 448 449 SOC_SCACHE_HANDLE_SET(scache_handle, unit, SOC_SCACHE_FLEXIO_HANDLE, 0); 450 rv = soc_versioned_scache_ptr_get(unit, scache_handle, 451 FALSE, &alloc_get, 452 &flexport_scache_ptr, 453 SOC_FLEXPORT_WB_DEFAULT_VERSION, 454 &recovered_ver); 455 if (SOC_FAILURE(rv)) { 456 if ((rv == SOC_E_CONFIG) || 457 (rv == SOC_E_NOT_FOUND)) { 458 /* warmboot file does not contain this 459 * module, or the warmboot state does not exist. 460 * in this case return SOC_E_NOT_FOUND 461 */ 462 return SOC_E_NOT_FOUND; 463 } else { 464 /* Only Level2 - flexport treat this as a error */ 465 LOG_ERROR(BSL_LS_SOC_COMMON, 466 (BSL_META_U(unit, 467 "Failed to recover scache data - %s\n"),soc_errmsg(rv))); 468 return rv; 469 } 470 } 471 if (alloc_get != alloc_size) { 472 /* Expected size doesn't match retrieved size */ 473 LOG_ERROR(BSL_LS_SOC_COMMON, 474 (BSL_META_U(unit, 475 "ERROR: scache recovery for flexport" 476 "%s()[LINE:%d] DONE \n"), 477 FUNCTION_NAME(), __LINE__)); 478 return SOC_E_INTERNAL; 479 } 480 481 if (NULL == flexport_scache_ptr) { 482 LOG_ERROR(BSL_LS_SOC_COMMON, 483 (BSL_META_U(unit, 484 "ERROR: scache recovery for flexport" 485 "%s()[LINE:%d] DONE \n"), 486 FUNCTION_NAME(), __LINE__)); 487 return SOC_E_MEMORY; 488 } 489 490 /*Physical to logical port mapping */ 491 var_size = (sizeof(int) * TRIDENT3_PHY_PORTS_PER_DEV); 492 sal_memcpy(si->port_p2l_mapping, 493 &flexport_scache_ptr[scache_offset], 494 var_size); 495 scache_offset += var_size; 496 497 /*Physical to MMU port mapping */ 498 var_size = (sizeof(int) * TRIDENT3_PHY_PORTS_PER_DEV); 499 sal_memcpy(si->port_p2m_mapping, 500 &flexport_scache_ptr[scache_offset], 501 var_size); 502 scache_offset += var_size; 503 504 /*Logical to Physical port mapping*/ 505 var_size = (sizeof(int) * TRIDENT3_PHY_PORTS_PER_DEV); 506 sal_memcpy(si->port_l2p_mapping, 507 &flexport_scache_ptr[scache_offset], 508 var_size); 509 scache_offset += var_size; 510 511 /* Max port speed */ 512 var_size = (sizeof(int) * TRIDENT3_PHY_PORTS_PER_DEV); 513 514 sal_memcpy(_soc_td3_port_speed_cap[unit], 515 &flexport_scache_ptr[scache_offset], 516 var_size); 517 scache_offset += var_size; 518 519 /* Init port speed */ 520 sal_memcpy(si->port_speed_max, 521 &flexport_scache_ptr[scache_offset], 522 var_size); 523 scache_offset += var_size; 524 525 /* Num of lanes */ 526 sal_memcpy(si->port_num_lanes, 527 &flexport_scache_ptr[scache_offset], 528 var_size); 529 scache_offset += var_size; 530 531 /* HG Bitmap */ 532 sal_memcpy(&si->hg.bitmap, 533 &flexport_scache_ptr[scache_offset], 534 sizeof(pbmp_t)); 535 scache_offset += sizeof(pbmp_t); 536 537 /* Disabled Port Bitmap */ 538 sal_memcpy(&si->all.disabled_bitmap, 539 &flexport_scache_ptr[scache_offset], 540 sizeof(pbmp_t)); 541 scache_offset += sizeof(pbmp_t); 542 543 544 for (pipe = 0; pipe < TRIDENT3_PIPES_PER_DEV; pipe++) { 545 SOC_PBMP_CLEAR(si->pipe_pbm[pipe]); 546 } 547 for (phy_port = 1; phy_port < TRIDENT3_PHY_PORTS_PER_DEV; phy_port++) { 548 if (si->port_l2p_mapping[phy_port] == -1) { 549 continue; 550 } 551 pipe = phy_port / TRIDENT3_PHY_PORTS_PER_PIPE; 552 si->port_pipe[phy_port] = pipe; 553 SOC_PBMP_PORT_ADD(si->pipe_pbm[pipe], phy_port); 554 } 555 LOG_VERBOSE(BSL_LS_SOC_COMMON, 556 (BSL_META_U(unit, 557 "%s()[LINE:%d] \n"),FUNCTION_NAME(), __LINE__)); 558 559 return SOC_E_NONE; 560 } 561 #endif /* BCM_WARM_BOOT_SUPPORT */ 562 563 #ifdef BCM_WARM_BOOT_SUPPORT_SW_DUMP 564 void 565 soc_td3_flexport_sw_dump(int unit) 566 { 567 int port, phy_port, mmu_port, pipe, pm, cosq, numq, uc_cosq, uc_numq; 568 int max_speed, init_speed, num_lanes; 569 char pfmt[SOC_PBMP_FMT_LEN]; 570 571 LOG_CLI((BSL_META_U(unit, 572 " port(log/phy/mmu) pipe pm lanes " 573 "speed(Max) uc_Qbase/Numq mc_Qbase/Numq\n"))); 574 PBMP_ALL_ITER(unit, port) { 575 pipe = SOC_INFO(unit).port_pipe[port]; 576 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 577 mmu_port = SOC_INFO(unit).port_p2m_mapping[phy_port]; 578 num_lanes = SOC_INFO(unit).port_num_lanes[port]; 579 pm = SOC_INFO(unit).port_serdes[port]; 580 max_speed = SOC_INFO(unit).port_speed_max[port]; 581 init_speed = SOC_INFO(unit).port_init_speed[port]; 582 cosq = SOC_INFO(unit).port_cosq_base[port]; 583 numq = SOC_INFO(unit).port_num_cosq[port]; 584 uc_cosq = SOC_INFO(unit).port_uc_cosq_base[port]; 585 uc_numq = SOC_INFO(unit).port_num_uc_cosq[port]; 586 587 LOG_CLI((BSL_META_U(unit, 588 " %4s(%3d/%3d/%3d) %4d %2d %5d %7d(%7d) " 589 "%6d/%-6d %6d/%-6d\n"), 590 SOC_INFO(unit).port_name[port], port, phy_port, mmu_port, 591 pipe, pm, num_lanes, init_speed, max_speed, 592 uc_cosq, uc_numq, cosq, numq)); 593 } 594 595 LOG_CLI((BSL_META_U(unit, 596 "\n Oversub Bitmap: %s"), 597 SOC_PBMP_FMT(SOC_INFO(unit).oversub_pbm, pfmt))); 598 LOG_CLI((BSL_META_U(unit, 599 "\n Disabled Bitmap: %s \n"), 600 SOC_PBMP_FMT(SOC_INFO(unit).all.disabled_bitmap, pfmt))); 601 } 602 #endif /* BCM_WARM_BOOT_SUPPORT_SW_DUMP */ 603 604 /* 605 * Function: 606 * soc_td3_port_mode_get 607 * Description: 608 * Get port mode by giving first logical port of a core 609 * Parameters: 610 * unit - Device number 611 * port - Logical port 612 * int* - Port Mode 613 * 614 * Each core can be configured into following 5 mode: 615 * Lane number 0 1 2 3 616 * ------------ --- --- --- --- 617 * quad port 10G 10G 10G 10G 618 * tri_012 port 10G 10G 20G x 619 * tri_023 port 20G x 10G 10G 620 * dual port 20G x 20G x 621 * single port 40G x x x 622 */ 623 int 624 soc_td3_port_mode_get(int unit, int logical_port, int *mode) 625 { 626 soc_info_t *si; 627 int lane; 628 int port, first_phyport, phy_port; 629 int num_lanes[TD3_PORTS_PER_TSC]; 630 631 si = &SOC_INFO(unit); 632 first_phyport = si->port_l2p_mapping[logical_port]; 633 634 for (lane = 0; lane < TD3_PORTS_PER_TSC; lane++) { 635 phy_port = first_phyport + lane; 636 port = si->port_p2l_mapping[phy_port]; 637 if (port == -1 || SOC_PBMP_MEMBER(si->all.disabled_bitmap, port)) { 638 num_lanes[lane] = -1; 639 } else { 640 num_lanes[lane] = si->port_num_lanes[port]; 641 } 642 } 643 644 if (num_lanes[0] == 4) { 645 *mode = SOC_TD3_PORT_MODE_QUAD; 646 } else if (num_lanes[0] == 2 && num_lanes[2] == 2) { 647 *mode = SOC_TD3_PORT_MODE_DUAL; 648 } else if (num_lanes[0] == 2) { 649 *mode = SOC_TD3_PORT_MODE_TRI_023; 650 } else if (num_lanes[2] == 2) { 651 *mode = SOC_TD3_PORT_MODE_TRI_012; 652 } else { 653 *mode = SOC_TD3_PORT_MODE_SINGLE; 654 } 655 656 return SOC_E_NONE; 657 } 658 659 660 /* 661 * Function: 662 * soc_td3_speed_mix_validate 663 * Purpose: 664 * Check if the mix of all ports speed is valid 665 * Parameters: 666 * unit - Unit. 667 * speed_mask - Bitmap of speed on all ports 668 * Returns: 669 * SOC_E_NONE 670 * SOC_E_CONFIG 671 */ 672 int 673 soc_td3_speed_mix_validate(int unit, uint32 speed_mask) 674 { 675 soc_info_t *si = &SOC_INFO(unit); 676 uint32 count; 677 678 count = _shr_popcount(speed_mask); 679 680 if (si->oversub_mode) { 681 if ((count >= 4) && 682 (speed_mask & SOC_PA_SPEED_20GB) && 683 ((speed_mask & SOC_PA_SPEED_25GB) || (speed_mask & SOC_PA_SPEED_50GB))) { 684 LOG_ERROR(BSL_LS_BCM_COMMON, 685 (BSL_META_U(unit, 686 "Port configurations that contain 4 or more speed class " 687 "in oversub mode, both 20G and 25G/50G port speed " 688 "are not supported.\n"))); 689 return SOC_E_PARAM; 690 } 691 } else { 692 if ((count == 4) && 693 ((speed_mask & SOC_PA_SPEED_20GB) || (speed_mask & SOC_PA_SPEED_40GB)) && 694 ((speed_mask & SOC_PA_SPEED_25GB) || (speed_mask & SOC_PA_SPEED_50GB))) { 695 LOG_ERROR(BSL_LS_BCM_COMMON, 696 (BSL_META_U(unit, 697 "Port configurations that contain 4 speed class " 698 "and both 20G/40G and 25G/50G port speed " 699 "are not supported.\n"))); 700 return SOC_E_PARAM; 701 } 702 } 703 if ((count < 4) && 704 ((speed_mask & SOC_PA_SPEED_20GB) && (speed_mask & SOC_PA_SPEED_25GB))) { 705 LOG_ERROR(BSL_LS_BCM_COMMON, 706 (BSL_META_U(unit, 707 "Port configurations that contain both 20G " 708 "and 25G port speed are not supported.\n"))); 709 return SOC_E_PARAM; 710 } 711 712 return SOC_E_NONE; 713 } 714 #endif /* BCM_TRIDENT3_SUPPORT */