counter.c (128361B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * TD3 counter module routines. 8 */ 9 10 #include <shared/bsl.h> 11 12 #include <sal/core/libc.h> 13 14 #include <soc/debug.h> 15 #include <soc/util.h> 16 #include <soc/mem.h> 17 #include <soc/trident3.h> 18 19 #ifdef BCM_TRIDENT3_SUPPORT 20 21 int 22 soc_counter_trident3_get_child_dma_by_idx(int unit, 23 soc_counter_non_dma_t *parent, 24 int idx, soc_counter_non_dma_t **child) 25 { 26 int rv = SOC_E_NONE; 27 28 if ((parent->flags & _SOC_COUNTER_NON_DMA_SUBSET_PARENT)) { 29 if (idx >= parent->extra_ctr_ct) { 30 return SOC_E_PARAM; 31 } 32 *child = &parent->extra_ctrs[idx << 1]; 33 } else { 34 *child = parent; 35 } 36 return rv; 37 } 38 39 int 40 soc_counter_trident3_get_child_dma(int unit, soc_reg_t id, 41 soc_ctr_control_info_t ctrl_info, 42 soc_counter_non_dma_t **child_dma) 43 { 44 soc_control_t *soc = SOC_CONTROL(unit); 45 soc_counter_non_dma_t *parent_dma = NULL; 46 int c_offset = -1; 47 48 if ((id < NUM_SOC_REG) || (id >= SOC_COUNTER_NON_DMA_END)) { 49 return SOC_E_PARAM; 50 } 51 parent_dma = &soc->counter_non_dma[id - SOC_COUNTER_NON_DMA_START]; 52 53 if ((!(parent_dma->flags & _SOC_COUNTER_NON_DMA_SUBSET_PARENT)) || 54 (ctrl_info.instance == -1)) { 55 *child_dma = parent_dma; 56 return SOC_E_NONE; 57 } 58 59 switch (ctrl_info.instance_type) { 60 case SOC_CTR_INSTANCE_TYPE_POOL: 61 c_offset = ctrl_info.instance; 62 if ((c_offset < 0) || (c_offset >= parent_dma->extra_ctr_ct)) { 63 return SOC_E_PARAM; 64 } 65 66 switch (id) { 67 case SOC_COUNTER_NON_DMA_ING_FLEX_BYTE: 68 case SOC_COUNTER_NON_DMA_EGR_FLEX_BYTE: 69 case SOC_COUNTER_NON_DMA_ING_FLEX_PKT: 70 case SOC_COUNTER_NON_DMA_EGR_FLEX_PKT: 71 if ((parent_dma->flags & _SOC_COUNTER_NON_DMA_SUBSET_PARENT) && 72 (parent_dma->extra_ctrs != NULL)) { 73 /* Refer extra_ctrs_init for PKT/BYTE control block placement. 74 */ 75 *child_dma = &parent_dma->extra_ctrs[(c_offset << 1)]; 76 } 77 break; 78 default: 79 return SOC_E_PARAM; 80 } 81 break; 82 default: 83 return SOC_E_PARAM; 84 } 85 return SOC_E_NONE; 86 } 87 88 int 89 soc_counter_trident3_generic_get_info(int unit, soc_ctr_control_info_t 90 ctrl_info, soc_reg_t id, int* base_index, 91 int* num_entries) { 92 soc_info_t *si = &SOC_INFO(unit); 93 soc_control_t *soc = SOC_CONTROL(unit); 94 soc_counter_non_dma_t *non_dma; 95 soc_port_t port; 96 soc_port_t phy_port = 0, mmu_port = 0; 97 int pipe, c_offset, pipe_offset = 0; 98 99 if ((id < NUM_SOC_REG) || (id >= SOC_COUNTER_NON_DMA_END)) { 100 return SOC_E_PARAM; 101 } 102 103 non_dma = &soc->counter_non_dma[id - SOC_COUNTER_NON_DMA_START]; 104 105 if (!(non_dma->flags & _SOC_COUNTER_NON_DMA_VALID) && 106 !(non_dma->flags & _SOC_COUNTER_NON_DMA_SUBSET_PARENT)) { 107 /* For Parent-Child model, return E_UNAVAIL if child non_dma is INVALID. 108 */ 109 return SOC_E_UNAVAIL; 110 } 111 112 *base_index = 0; 113 switch (ctrl_info.instance_type) { 114 case SOC_CTR_INSTANCE_TYPE_PORT: 115 port = ctrl_info.instance; 116 if (si->port_l2p_mapping[port] == -1) { 117 *base_index = 0; 118 *num_entries = 0; 119 return SOC_E_PARAM; 120 } 121 pipe = si->port_pipe[port]; 122 123 switch (id) { 124 case SOC_COUNTER_NON_DMA_EGR_PERQ_XMT_PKT: 125 case SOC_COUNTER_NON_DMA_EGR_PERQ_XMT_BYTE: 126 if (IS_CPU_PORT(unit, port)) { 127 *base_index = 0; 128 } else { 129 *base_index = pipe * 1368 + 48 + (port % 66) * 20 + 10; 130 } 131 *num_entries = si->port_num_cosq[port]; 132 break; 133 case SOC_COUNTER_NON_DMA_EGR_PERQ_XMT_PKT_UC: 134 case SOC_COUNTER_NON_DMA_EGR_PERQ_XMT_BYTE_UC: 135 if (IS_CPU_PORT(unit, port)) { 136 *base_index = 0; 137 } else { 138 *base_index = pipe * 1368 + 48 + (port % 66) * 20; 139 } 140 *num_entries = si->port_num_cosq[port]; 141 break; 142 case SOC_COUNTER_NON_DMA_PORT_DROP_PKT_OBM_LOSSY_LO: 143 case SOC_COUNTER_NON_DMA_PORT_DROP_BYTE_OBM_LOSSY_LO: 144 case SOC_COUNTER_NON_DMA_PORT_DROP_PKT_OBM_LOSSY_HI: 145 case SOC_COUNTER_NON_DMA_PORT_DROP_BYTE_OBM_LOSSY_HI: 146 case SOC_COUNTER_NON_DMA_PORT_DROP_PKT_OBM_LOSSLESS0: 147 case SOC_COUNTER_NON_DMA_PORT_DROP_BYTE_OBM_LOSSLESS0: 148 case SOC_COUNTER_NON_DMA_PORT_DROP_PKT_OBM_LOSSLESS1: 149 case SOC_COUNTER_NON_DMA_PORT_DROP_BYTE_OBM_LOSSLESS1: 150 case SOC_COUNTER_NON_DMA_PORT_OBM_FC_EVENTS: 151 if (IS_CPU_PORT(unit, port)) { 152 return SOC_E_PARAM; 153 } 154 return soc_counter_trident3_get_info(unit, port, id, 155 base_index, 156 num_entries); 157 break; 158 default: 159 return SOC_E_PARAM; 160 } 161 break; 162 case SOC_CTR_INSTANCE_TYPE_XPE_PORT: 163 port = (ctrl_info.instance & 0xFFC000) >> 14; 164 phy_port = si->port_l2p_mapping[port]; 165 mmu_port = si->port_p2m_mapping[phy_port]; 166 pipe = si->port_pipe[port]; 167 168 switch (id) { 169 case SOC_COUNTER_NON_DMA_COSQ_DROP_BYTE: 170 case SOC_COUNTER_NON_DMA_COSQ_DROP_BYTE_UC: 171 case SOC_COUNTER_NON_DMA_COSQ_DROP_PKT: 172 case SOC_COUNTER_NON_DMA_COSQ_DROP_PKT_UC: 173 if ((id == SOC_COUNTER_NON_DMA_COSQ_DROP_PKT) || 174 (id == SOC_COUNTER_NON_DMA_COSQ_DROP_BYTE)) { 175 *base_index = si->port_cosq_base[port]; 176 *num_entries = si->port_num_cosq[port]; 177 } else { 178 *base_index = si->port_uc_cosq_base[port]; 179 *num_entries = si->port_num_uc_cosq[port]; 180 } 181 pipe_offset = (non_dma->num_entries / NUM_PIPE(unit)) * pipe; 182 *base_index += pipe_offset; 183 break; 184 185 case SOC_COUNTER_NON_DMA_PORT_DROP_PKT_YELLOW: 186 case SOC_COUNTER_NON_DMA_PORT_DROP_PKT_RED: 187 case SOC_COUNTER_NON_DMA_PORT_WRED_PKT_GREEN: 188 case SOC_COUNTER_NON_DMA_PORT_WRED_PKT_YELLOW: 189 case SOC_COUNTER_NON_DMA_PORT_WRED_PKT_RED: 190 if (IS_CPU_PORT(unit, port)) { 191 *base_index = 64; 192 } else if (IS_LB_PORT(unit, port)) { 193 *base_index = pipe * 66 + 65; 194 } else { 195 *base_index = pipe * 66 + 196 (mmu_port & SOC_TD3_MMU_PORT_STRIDE); 197 } 198 *num_entries = 1; 199 break; 200 201 case SOC_COUNTER_NON_DMA_PORT_DROP_PKT_ING: 202 case SOC_COUNTER_NON_DMA_PORT_DROP_BYTE_ING: 203 *base_index = mmu_port & SOC_TD3_MMU_PORT_STRIDE; 204 *num_entries = 1; 205 pipe_offset = (non_dma->num_entries / NUM_PIPE(unit)) * pipe; 206 *base_index += pipe_offset; 207 break; 208 case SOC_COUNTER_NON_DMA_PG_MIN_PEAK: 209 case SOC_COUNTER_NON_DMA_PG_MIN_CURRENT: 210 case SOC_COUNTER_NON_DMA_PG_SHARED_PEAK: 211 case SOC_COUNTER_NON_DMA_PG_SHARED_CURRENT: 212 case SOC_COUNTER_NON_DMA_PG_HDRM_PEAK: 213 case SOC_COUNTER_NON_DMA_PG_HDRM_CURRENT: 214 *num_entries = non_dma->entries_per_port; 215 pipe_offset = (non_dma->num_entries / NUM_PIPE(unit)) * pipe; 216 217 if (IS_CPU_PORT(unit, port)) { 218 *base_index += mmu_port * _TD3_MMU_NUM_PG; 219 } else { 220 *base_index += pipe_offset + 221 ((mmu_port & SOC_TD3_MMU_PORT_STRIDE) * 222 _TD3_MMU_NUM_PG); 223 } 224 break; 225 case SOC_COUNTER_NON_DMA_QUEUE_PEAK: 226 case SOC_COUNTER_NON_DMA_QUEUE_CURRENT: 227 case SOC_COUNTER_NON_DMA_UC_QUEUE_PEAK: 228 case SOC_COUNTER_NON_DMA_UC_QUEUE_CURRENT: 229 if ((id == SOC_COUNTER_NON_DMA_QUEUE_PEAK) || 230 (id == SOC_COUNTER_NON_DMA_QUEUE_CURRENT)) { 231 *base_index = si->port_cosq_base[port]; 232 *num_entries = si->port_num_cosq[port]; 233 } else { 234 *base_index = si->port_uc_cosq_base[port]; 235 *num_entries = si->port_num_uc_cosq[port]; 236 } 237 pipe_offset = (non_dma->num_entries / NUM_PIPE(unit)) * pipe; 238 *base_index += pipe_offset; 239 break; 240 default: 241 return SOC_E_PARAM; 242 } 243 break; 244 case SOC_CTR_INSTANCE_TYPE_XPE: 245 switch (id) { 246 case SOC_COUNTER_NON_DMA_DROP_RQ_PKT: 247 case SOC_COUNTER_NON_DMA_DROP_RQ_BYTE: 248 case SOC_COUNTER_NON_DMA_DROP_RQ_PKT_YELLOW: 249 case SOC_COUNTER_NON_DMA_DROP_RQ_PKT_RED: 250 case SOC_COUNTER_NON_DMA_POOL_PEAK: 251 case SOC_COUNTER_NON_DMA_POOL_CURRENT: 252 *base_index = 0; 253 *num_entries = non_dma->num_entries; 254 break; 255 default: 256 return SOC_E_PARAM; 257 } 258 break; 259 case SOC_CTR_INSTANCE_TYPE_PIPE: 260 pipe = ctrl_info.instance; 261 if ((pipe >= NUM_PIPE(unit)) || (pipe < -1) ) { 262 return SOC_E_PARAM; 263 } 264 switch (id) { 265 case SOC_COUNTER_NON_DMA_EFP_PKT: 266 case SOC_COUNTER_NON_DMA_EFP_BYTE: 267 *base_index = 0; 268 *num_entries = non_dma->num_entries / NUM_PIPE(unit); 269 if (pipe > 0) { 270 pipe_offset = pipe * (*num_entries); 271 *base_index += pipe_offset; 272 } 273 break; 274 default: 275 return SOC_E_INTERNAL; 276 } 277 break; 278 case SOC_CTR_INSTANCE_TYPE_POOL: 279 c_offset = ctrl_info.instance; 280 if ((c_offset < 0) || (c_offset >= non_dma->extra_ctr_ct)) { 281 return SOC_E_PARAM; 282 } 283 284 switch (id) { 285 case SOC_COUNTER_NON_DMA_ING_FLEX_BYTE: 286 case SOC_COUNTER_NON_DMA_EGR_FLEX_BYTE: 287 case SOC_COUNTER_NON_DMA_ING_FLEX_PKT: 288 case SOC_COUNTER_NON_DMA_EGR_FLEX_PKT: 289 *base_index = 0; 290 291 if ((non_dma->flags & _SOC_COUNTER_NON_DMA_SUBSET_PARENT) && 292 (non_dma->extra_ctrs != NULL)) { 293 /* Refer extra_ctrs_init for PKT/BYTE control block placement. 294 */ 295 non_dma = &non_dma->extra_ctrs[(c_offset << 1)]; 296 } 297 *num_entries = non_dma->num_entries / NUM_PIPE(unit); 298 break; 299 default: 300 return SOC_E_PARAM; 301 } 302 break; 303 case SOC_CTR_INSTANCE_TYPE_POOL_PIPE: 304 c_offset = (ctrl_info.instance & 0x3F0) >> 4; 305 pipe = ctrl_info.instance & 0xF; 306 if ((c_offset < 0) || (c_offset >= non_dma->extra_ctr_ct) || 307 (pipe >= NUM_PIPE(unit)) || (pipe < 0)) { 308 return SOC_E_PARAM; 309 } 310 switch (id) { 311 case SOC_COUNTER_NON_DMA_ING_FLEX_BYTE: 312 case SOC_COUNTER_NON_DMA_EGR_FLEX_BYTE: 313 case SOC_COUNTER_NON_DMA_ING_FLEX_PKT: 314 case SOC_COUNTER_NON_DMA_EGR_FLEX_PKT: 315 316 if ((non_dma->flags & _SOC_COUNTER_NON_DMA_SUBSET_PARENT) && 317 (non_dma->extra_ctrs != NULL)) { 318 /* Refer extra_ctrs_init for PKT/BYTE control block placement. 319 */ 320 non_dma = &non_dma->extra_ctrs[(c_offset << 1)]; 321 } 322 *num_entries = non_dma->num_entries / NUM_PIPE(unit); 323 *base_index = (*num_entries)*pipe; 324 break; 325 default: 326 return SOC_E_PARAM; 327 } 328 break; 329 330 case SOC_CTR_INSTANCE_TYPE_SFLOW: 331 c_offset = ctrl_info.instance; 332 if ((c_offset < 0) || (c_offset >= non_dma->extra_ctr_ct)) { 333 return SOC_E_PARAM; 334 } 335 336 *base_index = 0; 337 if ((non_dma->flags & _SOC_COUNTER_NON_DMA_SUBSET_PARENT) && 338 (non_dma->extra_ctrs != NULL)) { 339 non_dma = &non_dma->extra_ctrs[(c_offset << 1)]; 340 } 341 *num_entries = non_dma->num_entries; 342 break; 343 344 default: 345 return SOC_E_PARAM; 346 } 347 *base_index += non_dma->base_index; 348 return SOC_E_NONE; 349 } 350 351 352 int 353 soc_counter_trident3_get_info(int unit, soc_port_t port, soc_reg_t id, 354 int *base_index, int *num_entries) { 355 soc_info_t *si; 356 soc_control_t *soc; 357 soc_counter_non_dma_t *non_dma; 358 soc_port_t phy_port, mmu_port; 359 int pipe, pipe_offset, obm_id = 0, lane = 0; 360 uint8 c_offset = 0; /* child offset in Parent-child model */ 361 362 soc = SOC_CONTROL(unit); 363 364 if ((id < SOC_COUNTER_NON_DMA_START) || (id >= SOC_COUNTER_NON_DMA_END)) { 365 LOG_ERROR(BSL_LS_SOC_COMMON, 366 (BSL_META_U(unit, 367 "Invalid NON DMA Counter ID: %d.\n"), id)); 368 return SOC_E_PARAM; 369 } 370 non_dma = &soc->counter_non_dma[id - SOC_COUNTER_NON_DMA_START]; 371 372 if (!(non_dma->flags & _SOC_COUNTER_NON_DMA_VALID) && 373 !(non_dma->flags & _SOC_COUNTER_NON_DMA_SUBSET_PARENT)) { 374 /* For Parent-Child model, return E_UNAVAIL if child non_dma is INVALID. 375 */ 376 return SOC_E_UNAVAIL; 377 } 378 379 si = &SOC_INFO(unit); 380 if (si->port_l2p_mapping[port] == -1) { 381 *base_index = 0; 382 *num_entries = 0; 383 return SOC_E_NONE; 384 } 385 386 phy_port = si->port_l2p_mapping[port]; 387 mmu_port = si->port_p2m_mapping[phy_port]; 388 pipe = si->port_pipe[port]; 389 390 switch (id) { 391 case SOC_COUNTER_NON_DMA_EGR_PERQ_XMT_PKT: 392 case SOC_COUNTER_NON_DMA_EGR_PERQ_XMT_BYTE: 393 if (IS_CPU_PORT(unit, port)) { 394 *base_index = 0; 395 } else { 396 *base_index = pipe * 1368 + 48 + (port % 66) * 20 + 10; 397 } 398 *num_entries = si->port_num_cosq[port]; 399 break; 400 case SOC_COUNTER_NON_DMA_EGR_PERQ_XMT_PKT_UC: 401 case SOC_COUNTER_NON_DMA_EGR_PERQ_XMT_BYTE_UC: 402 if (IS_CPU_PORT(unit, port)) { 403 *base_index = 0; 404 } else { 405 *base_index = pipe * 1368 + 48 + (port % 66) * 20; 406 } 407 *num_entries = si->port_num_cosq[port]; 408 break; 409 case SOC_COUNTER_NON_DMA_COSQ_DROP_BYTE: 410 case SOC_COUNTER_NON_DMA_COSQ_DROP_BYTE_UC: 411 case SOC_COUNTER_NON_DMA_COSQ_DROP_PKT: 412 case SOC_COUNTER_NON_DMA_COSQ_DROP_PKT_UC: 413 if ((id == SOC_COUNTER_NON_DMA_COSQ_DROP_PKT) || 414 (id == SOC_COUNTER_NON_DMA_COSQ_DROP_BYTE)) { 415 *base_index = si->port_cosq_base[port]; 416 *num_entries = si->port_num_cosq[port]; 417 } else { 418 *base_index = si->port_uc_cosq_base[port]; 419 *num_entries = si->port_num_uc_cosq[port]; 420 } 421 pipe_offset = (non_dma->num_entries / NUM_PIPE(unit)) * pipe; 422 *base_index += pipe_offset; 423 break; 424 case SOC_COUNTER_NON_DMA_PORT_DROP_PKT_ING: 425 case SOC_COUNTER_NON_DMA_PORT_DROP_BYTE_ING: 426 *base_index = mmu_port & 0x3f; 427 pipe_offset = (non_dma->num_entries / NUM_PIPE(unit)) * pipe; 428 *base_index += pipe_offset; 429 *num_entries = 1; 430 break; 431 case SOC_COUNTER_NON_DMA_ING_FLEX_BYTE: 432 case SOC_COUNTER_NON_DMA_EGR_FLEX_BYTE: 433 case SOC_COUNTER_NON_DMA_ING_FLEX_PKT: 434 case SOC_COUNTER_NON_DMA_EGR_FLEX_PKT: 435 *base_index = 0; 436 437 if ((non_dma->flags & _SOC_COUNTER_NON_DMA_SUBSET_PARENT) && 438 (non_dma->extra_ctrs != NULL)) { 439 /* refer extra_ctrs_init for pkt/byte control block placement. 440 */ 441 non_dma = &non_dma->extra_ctrs[(c_offset << 1)]; 442 } 443 *num_entries = non_dma->num_entries / NUM_PIPE(unit); 444 break; 445 case SOC_COUNTER_NON_DMA_PORT_DROP_PKT_YELLOW: 446 case SOC_COUNTER_NON_DMA_PORT_DROP_PKT_RED: 447 case SOC_COUNTER_NON_DMA_PORT_WRED_PKT_GREEN: 448 case SOC_COUNTER_NON_DMA_PORT_WRED_PKT_RED: 449 case SOC_COUNTER_NON_DMA_PORT_WRED_PKT_YELLOW: 450 if (IS_CPU_PORT(unit, port)) { 451 *base_index = 64; 452 } else if (IS_LB_PORT(unit, port)) { 453 *base_index = pipe * 128 + 65; 454 } else { 455 *base_index = pipe * 128 + (mmu_port & SOC_TD3_MMU_PORT_STRIDE); 456 } 457 *num_entries = 1; 458 break; 459 460 case SOC_COUNTER_NON_DMA_EFP_PKT: 461 case SOC_COUNTER_NON_DMA_EFP_BYTE: 462 *base_index = 0; 463 *num_entries = non_dma->num_entries / NUM_PIPE(unit); 464 break; 465 case SOC_COUNTER_NON_DMA_PORT_DROP_PKT_OBM_LOSSY_LO: 466 case SOC_COUNTER_NON_DMA_PORT_DROP_BYTE_OBM_LOSSY_LO: 467 case SOC_COUNTER_NON_DMA_PORT_DROP_PKT_OBM_LOSSY_HI: 468 case SOC_COUNTER_NON_DMA_PORT_DROP_BYTE_OBM_LOSSY_HI: 469 case SOC_COUNTER_NON_DMA_PORT_DROP_PKT_OBM_LOSSLESS0: 470 case SOC_COUNTER_NON_DMA_PORT_DROP_BYTE_OBM_LOSSLESS0: 471 case SOC_COUNTER_NON_DMA_PORT_DROP_PKT_OBM_LOSSLESS1: 472 case SOC_COUNTER_NON_DMA_PORT_DROP_BYTE_OBM_LOSSLESS1: 473 case SOC_COUNTER_NON_DMA_PORT_OBM_FC_EVENTS: 474 *base_index = 0; 475 *num_entries = 1; 476 /* find obm from the port number */ 477 SOC_IF_ERROR_RETURN 478 (soc_trident3_port_obm_info_get(unit, port, &obm_id, &lane)); 479 pipe = si->port_pipe[port]; 480 soc_counter_trident3_get_child_dma_by_idx(unit, non_dma, 481 obm_id, &non_dma); 482 *base_index += (pipe * 4) + lane; 483 break; 484 default: 485 return SOC_E_INTERNAL; 486 } 487 *base_index += non_dma->base_index; 488 return SOC_E_NONE; 489 } 490 491 int 492 soc_counter_trident3_eviction_init(int unit) 493 { 494 soc_control_t *soc; 495 soc_counter_evict_t *evict; 496 int pipe, mem_id, offset=0; 497 int counter_id; 498 static const struct { 499 int pkt_counter_id; 500 int byte_counter_id; 501 soc_mem_t mem; 502 int pool_id; 503 } evict_info[SOC_TD3_NUM_EVICT_MEM] = { 504 { /* MEMORY_ID 0 is reserved */ 505 -1, 506 -1, 507 INVALIDm, 508 0 509 }, 510 { /* MEMORY_ID 1 */ 511 SOC_COUNTER_NON_DMA_ING_FLEX_PKT, 512 SOC_COUNTER_NON_DMA_ING_FLEX_BYTE, 513 ING_FLEX_CTR_COUNTER_TABLE_0m, 514 0 515 }, 516 { /* MEMORY_ID 2 */ 517 SOC_COUNTER_NON_DMA_ING_FLEX_PKT, 518 SOC_COUNTER_NON_DMA_ING_FLEX_BYTE, 519 ING_FLEX_CTR_COUNTER_TABLE_1m, 520 1 521 }, 522 { /* MEMORY_ID 3 */ 523 SOC_COUNTER_NON_DMA_ING_FLEX_PKT, 524 SOC_COUNTER_NON_DMA_ING_FLEX_BYTE, 525 ING_FLEX_CTR_COUNTER_TABLE_2m, 526 2 527 }, 528 { /* MEMORY_ID 4 */ 529 SOC_COUNTER_NON_DMA_ING_FLEX_PKT, 530 SOC_COUNTER_NON_DMA_ING_FLEX_BYTE, 531 ING_FLEX_CTR_COUNTER_TABLE_3m, 532 3 533 }, 534 { /* MEMORY_ID 5 */ 535 SOC_COUNTER_NON_DMA_ING_FLEX_PKT, 536 SOC_COUNTER_NON_DMA_ING_FLEX_BYTE, 537 ING_FLEX_CTR_COUNTER_TABLE_4m, 538 4 539 }, 540 { /* MEMORY_ID 6 */ 541 SOC_COUNTER_NON_DMA_ING_FLEX_PKT, 542 SOC_COUNTER_NON_DMA_ING_FLEX_BYTE, 543 ING_FLEX_CTR_COUNTER_TABLE_5m, 544 5 545 }, 546 { /* MEMORY_ID 7 */ 547 SOC_COUNTER_NON_DMA_ING_FLEX_PKT, 548 SOC_COUNTER_NON_DMA_ING_FLEX_BYTE, 549 ING_FLEX_CTR_COUNTER_TABLE_6m, 550 6 551 }, 552 { /* MEMORY_ID 8 */ 553 SOC_COUNTER_NON_DMA_ING_FLEX_PKT, 554 SOC_COUNTER_NON_DMA_ING_FLEX_BYTE, 555 ING_FLEX_CTR_COUNTER_TABLE_7m, 556 7 557 }, 558 { /* MEMORY_ID 9 */ 559 SOC_COUNTER_NON_DMA_ING_FLEX_PKT, 560 SOC_COUNTER_NON_DMA_ING_FLEX_BYTE, 561 ING_FLEX_CTR_COUNTER_TABLE_8m, 562 8 563 }, 564 { /* MEMORY_ID 10 */ 565 SOC_COUNTER_NON_DMA_ING_FLEX_PKT, 566 SOC_COUNTER_NON_DMA_ING_FLEX_BYTE, 567 ING_FLEX_CTR_COUNTER_TABLE_9m, 568 9 569 }, 570 { /* MEMORY_ID 11 */ 571 SOC_COUNTER_NON_DMA_ING_FLEX_PKT, 572 SOC_COUNTER_NON_DMA_ING_FLEX_BYTE, 573 ING_FLEX_CTR_COUNTER_TABLE_10m, 574 10 575 }, 576 { /* MEMORY_ID 12 */ 577 SOC_COUNTER_NON_DMA_ING_FLEX_PKT, 578 SOC_COUNTER_NON_DMA_ING_FLEX_BYTE, 579 ING_FLEX_CTR_COUNTER_TABLE_11m, 580 11 581 }, 582 { /* MEMORY_ID 13 */ 583 SOC_COUNTER_NON_DMA_ING_FLEX_PKT, 584 SOC_COUNTER_NON_DMA_ING_FLEX_BYTE, 585 ING_FLEX_CTR_COUNTER_TABLE_12m, 586 12 587 }, 588 { /* MEMORY_ID 14 */ 589 SOC_COUNTER_NON_DMA_ING_FLEX_PKT, 590 SOC_COUNTER_NON_DMA_ING_FLEX_BYTE, 591 ING_FLEX_CTR_COUNTER_TABLE_13m, 592 13 593 }, 594 { /* MEMORY_ID 15 */ 595 SOC_COUNTER_NON_DMA_ING_FLEX_PKT, 596 SOC_COUNTER_NON_DMA_ING_FLEX_BYTE, 597 ING_FLEX_CTR_COUNTER_TABLE_14m, 598 14 599 }, 600 { /* MEMORY_ID 16 */ 601 SOC_COUNTER_NON_DMA_ING_FLEX_PKT, 602 SOC_COUNTER_NON_DMA_ING_FLEX_BYTE, 603 ING_FLEX_CTR_COUNTER_TABLE_15m, 604 15 605 }, 606 { /* MEMORY_ID 17 */ 607 SOC_COUNTER_NON_DMA_ING_FLEX_PKT, 608 SOC_COUNTER_NON_DMA_ING_FLEX_BYTE, 609 ING_FLEX_CTR_COUNTER_TABLE_16m, 610 16 611 }, 612 { /* MEMORY_ID 18 */ 613 SOC_COUNTER_NON_DMA_ING_FLEX_PKT, 614 SOC_COUNTER_NON_DMA_ING_FLEX_BYTE, 615 ING_FLEX_CTR_COUNTER_TABLE_17m, 616 17 617 }, 618 { /* MEMORY_ID 19 */ 619 SOC_COUNTER_NON_DMA_ING_FLEX_PKT, 620 SOC_COUNTER_NON_DMA_ING_FLEX_BYTE, 621 ING_FLEX_CTR_COUNTER_TABLE_18m, 622 18 623 }, 624 { /* MEMORY_ID 20 */ 625 SOC_COUNTER_NON_DMA_ING_FLEX_PKT, 626 SOC_COUNTER_NON_DMA_ING_FLEX_BYTE, 627 ING_FLEX_CTR_COUNTER_TABLE_19m, 628 19 629 }, 630 { /* MEMORY_ID 21 */ 631 SOC_COUNTER_NON_DMA_EGR_FLEX_PKT, 632 SOC_COUNTER_NON_DMA_EGR_FLEX_BYTE, 633 EGR_FLEX_CTR_COUNTER_TABLE_0m, 634 0 635 }, 636 { /* MEMORY_ID 22 */ 637 SOC_COUNTER_NON_DMA_EGR_FLEX_PKT, 638 SOC_COUNTER_NON_DMA_EGR_FLEX_BYTE, 639 EGR_FLEX_CTR_COUNTER_TABLE_1m, 640 1 641 }, 642 { /* MEMORY_ID 23 */ 643 SOC_COUNTER_NON_DMA_EGR_FLEX_PKT, 644 SOC_COUNTER_NON_DMA_EGR_FLEX_BYTE, 645 EGR_FLEX_CTR_COUNTER_TABLE_2m, 646 2 647 }, 648 { /* MEMORY_ID 24 */ 649 SOC_COUNTER_NON_DMA_EGR_FLEX_PKT, 650 SOC_COUNTER_NON_DMA_EGR_FLEX_BYTE, 651 EGR_FLEX_CTR_COUNTER_TABLE_3m, 652 3 653 }, 654 { /* MEMORY_ID 25 */ 655 SOC_COUNTER_NON_DMA_EGR_PERQ_XMT_PKT, 656 SOC_COUNTER_NON_DMA_EGR_PERQ_XMT_BYTE, 657 EGR_PERQ_XMT_COUNTERSm, 658 0 659 }, 660 { /* MEMORY_ID 26 */ 661 SOC_COUNTER_NON_DMA_EFP_PKT, 662 SOC_COUNTER_NON_DMA_EFP_BYTE, 663 EFP_COUNTER_TABLEm, 664 0 665 } 666 }; 667 668 soc = SOC_CONTROL(unit); 669 670 if (soc->counter_evict == NULL) { 671 /* memory_id 0 is reserved, allocate 1 extra entries */ 672 soc->counter_evict = sal_alloc(sizeof(soc_counter_evict_t) * 673 SOC_TD3_NUM_EVICT_MEM, 674 "Trident3 counter_evict"); 675 if (soc->counter_evict == NULL) { 676 return SOC_E_MEMORY; 677 } 678 } 679 680 counter_id = -1; 681 soc->counter_evict_max_mem_id = 0; 682 for (mem_id = 1; mem_id < sizeof(evict_info) / sizeof(evict_info[0]); 683 mem_id++) { 684 evict = &soc->counter_evict[mem_id]; 685 evict->pkt_counter_id = evict_info[mem_id].pkt_counter_id; 686 evict->byte_counter_id = evict_info[mem_id].byte_counter_id; 687 evict->pool_id = evict_info[mem_id].pool_id; 688 soc->counter_evict_max_mem_id = mem_id; 689 if (counter_id != evict->pkt_counter_id) { 690 offset = 0; 691 counter_id = evict->pkt_counter_id; 692 } 693 for (pipe = 0; pipe < NUM_PIPE(unit); pipe++) { 694 evict->offset[pipe] = offset; 695 evict->mem[pipe] = 696 SOC_MEM_UNIQUE_ACC(unit, evict_info[mem_id].mem)[pipe]; 697 offset += soc_mem_index_count(unit, evict->mem[pipe]); 698 } 699 } 700 701 return SOC_E_NONE; 702 } 703 704 int 705 soc_counter_trident3_dma_flags_update(int unit, soc_counter_non_dma_t *ctr_dma, 706 uint32 flags, int val) 707 { 708 int rv = SOC_E_NONE; 709 int count = 0, subset_ct = 0; 710 711 if ((ctr_dma->flags & _SOC_COUNTER_NON_DMA_SUBSET_PARENT) && 712 (ctr_dma->extra_ctrs != NULL)) { 713 subset_ct = ctr_dma->extra_ctr_ct << 1; 714 ctr_dma = ctr_dma->extra_ctrs; 715 } else { 716 subset_ct = 1; 717 } 718 719 do { 720 switch (flags) { 721 case _SOC_COUNTER_NON_DMA_CLEAR_ON_READ: 722 /* Update only for CLR_ON_READ, until necessity calls for other 723 * FLAGS */ 724 if (ctr_dma->flags & _SOC_COUNTER_NON_DMA_CTR_EVICT) { 725 if (val) { 726 ctr_dma->flags |= _SOC_COUNTER_NON_DMA_CLEAR_ON_READ; 727 } else { 728 ctr_dma->flags &= ~_SOC_COUNTER_NON_DMA_CLEAR_ON_READ; 729 } 730 } 731 break; 732 case SOC_CTR_CTRL_CONFIG_DMA_RATE_PROFILE_ALL: 733 if (ctr_dma->flags & _SOC_COUNTER_NON_DMA_CTR_EVICT) { 734 ctr_dma->dma_rate_profile = (val) ? 735 _SOC_COUNTER_DMA_RATE_PROFILE_ALL : 0; 736 } 737 break; 738 case SOC_CTR_CTRL_CONFIG_DMA_RATE_PROFILE_AUTO: 739 case SOC_CTR_CTRL_CONFIG_DMA_RATE_PROFILE_WFS: 740 return SOC_E_UNAVAIL; 741 default: 742 return SOC_E_PARAM; 743 } 744 count++; 745 ctr_dma++; 746 } while ((count < subset_ct) && ctr_dma); 747 748 return rv; 749 } 750 751 int 752 soc_counter_trident3_extra_ctrs_init(int unit, soc_reg_t id, 753 soc_counter_non_dma_t *non_dma_parent, 754 soc_counter_non_dma_t *non_dma_extra, 755 uint32 extra_ctr_ct, 756 int *total_entries) 757 { 758 int i, pipe, count = 0; 759 soc_mem_t *base_mem_array = NULL, base_mem = INVALIDm; 760 int base_mem_ct = 0; 761 int parent_base_index = 0; 762 uint8 mmu_mem = FALSE; 763 int xpe; 764 765 soc_mem_t ing_flex_mems[] = { 766 ING_FLEX_CTR_COUNTER_TABLE_0m, /* MEMORYID 1 */ 767 ING_FLEX_CTR_COUNTER_TABLE_1m, /* MEMORYID 2 */ 768 ING_FLEX_CTR_COUNTER_TABLE_2m, /* MEMORYID 3 */ 769 ING_FLEX_CTR_COUNTER_TABLE_3m, /* MEMORYID 4 */ 770 ING_FLEX_CTR_COUNTER_TABLE_4m, /* MEMORYID 5 */ 771 ING_FLEX_CTR_COUNTER_TABLE_5m, /* MEMORYID 6 */ 772 ING_FLEX_CTR_COUNTER_TABLE_6m, /* MEMORYID 7 */ 773 ING_FLEX_CTR_COUNTER_TABLE_7m, /* MEMORYID 8 */ 774 ING_FLEX_CTR_COUNTER_TABLE_8m, /* MEMORYID 9 */ 775 ING_FLEX_CTR_COUNTER_TABLE_9m, /* MEMORYID 10 */ 776 ING_FLEX_CTR_COUNTER_TABLE_10m, /* MEMORYID 11 */ 777 ING_FLEX_CTR_COUNTER_TABLE_11m, /* MEMORYID 12 */ 778 ING_FLEX_CTR_COUNTER_TABLE_12m, /* MEMORYID 13 */ 779 ING_FLEX_CTR_COUNTER_TABLE_13m, /* MEMORYID 14 */ 780 ING_FLEX_CTR_COUNTER_TABLE_14m, /* MEMORYID 15 */ 781 ING_FLEX_CTR_COUNTER_TABLE_15m, /* MEMORYID 16 */ 782 ING_FLEX_CTR_COUNTER_TABLE_16m, /* MEMORYID 17 */ 783 ING_FLEX_CTR_COUNTER_TABLE_17m, /* MEMORYID 18 */ 784 ING_FLEX_CTR_COUNTER_TABLE_18m, /* MEMORYID 19 */ 785 ING_FLEX_CTR_COUNTER_TABLE_19m /* MEMORYID 20 */ 786 }; 787 788 soc_mem_t egr_flex_mems[] = { 789 EGR_FLEX_CTR_COUNTER_TABLE_0m, /* MEMORYID 21 */ 790 EGR_FLEX_CTR_COUNTER_TABLE_1m, /* MEMORYID 22 */ 791 EGR_FLEX_CTR_COUNTER_TABLE_2m, /* MEMORYID 23 */ 792 EGR_FLEX_CTR_COUNTER_TABLE_3m /* MEMORYID 24 */ 793 }; 794 795 /* DO SANITY CHECK FOR INPUT PARAMs */ 796 if (!(non_dma_parent->flags & _SOC_COUNTER_NON_DMA_SUBSET_PARENT)) { 797 /* Only for Extra counters */ 798 return SOC_E_PARAM; 799 } 800 801 parent_base_index = non_dma_parent->base_index; 802 *total_entries = 0; 803 804 switch (id) { 805 case SOC_COUNTER_NON_DMA_ING_FLEX_PKT: 806 case SOC_COUNTER_NON_DMA_ING_FLEX_BYTE: 807 base_mem_array = ing_flex_mems; 808 count = sizeof(ing_flex_mems) / sizeof(ing_flex_mems[0]); 809 break; 810 case SOC_COUNTER_NON_DMA_EGR_FLEX_PKT: 811 case SOC_COUNTER_NON_DMA_EGR_FLEX_BYTE: 812 base_mem_array = egr_flex_mems; 813 count = sizeof(egr_flex_mems) / sizeof(egr_flex_mems[0]); 814 break; 815 case SOC_COUNTER_NON_DMA_COSQ_DROP_PKT_UC: 816 case SOC_COUNTER_NON_DMA_COSQ_DROP_PKT: 817 case SOC_COUNTER_NON_DMA_COSQ_DROP_BYTE_UC: 818 case SOC_COUNTER_NON_DMA_COSQ_DROP_BYTE: 819 case SOC_COUNTER_NON_DMA_QUEUE_PEAK: 820 case SOC_COUNTER_NON_DMA_QUEUE_CURRENT: 821 case SOC_COUNTER_NON_DMA_UC_QUEUE_PEAK: 822 case SOC_COUNTER_NON_DMA_UC_QUEUE_CURRENT: 823 case SOC_COUNTER_NON_DMA_PORT_DROP_PKT_RED: 824 case SOC_COUNTER_NON_DMA_PORT_WRED_PKT_YELLOW: 825 case SOC_COUNTER_NON_DMA_PORT_DROP_PKT_YELLOW: 826 case SOC_COUNTER_NON_DMA_PORT_WRED_PKT_GREEN: 827 case SOC_COUNTER_NON_DMA_PORT_WRED_PKT_RED: 828 case SOC_COUNTER_NON_DMA_PORT_DROP_PKT_ING: 829 case SOC_COUNTER_NON_DMA_PORT_DROP_BYTE_ING: 830 mmu_mem = TRUE; 831 count = NUM_XPE(unit); 832 base_mem = SOC_MEM_UNIQUE_ACC_XPE_PIPE(unit, non_dma_parent->mem, 833 0, 0); 834 if (base_mem != INVALIDm) { 835 /* XPE 0/PIPE 0 combination is true for both IP/EP */ 836 base_mem_ct = soc_mem_index_max(unit, base_mem) + 1; 837 } 838 break; 839 default: 840 return SOC_E_INTERNAL; 841 } 842 843 if (extra_ctr_ct > count) { 844 return SOC_E_INTERNAL; 845 } 846 847 for (i = 0; i < count; i++) { 848 if (mmu_mem == FALSE) { 849 non_dma_extra->mem = base_mem_array[i]; 850 base_mem_ct = soc_mem_index_count(unit, non_dma_extra->mem); 851 852 /* Set Child attributes */ 853 non_dma_extra->base_index = parent_base_index + *total_entries; 854 non_dma_extra->num_entries = NUM_PIPE(unit) * base_mem_ct; 855 856 /* Inherit few info from the Parent */ 857 non_dma_extra->flags = (non_dma_parent->flags & 858 ~_SOC_COUNTER_NON_DMA_SUBSET_PARENT) | 859 _SOC_COUNTER_NON_DMA_SUBSET_CHILD; 860 861 non_dma_extra->cname = sal_alloc(sal_strlen(non_dma_parent->cname) + 9, 862 "Extra ctrs cname"); 863 864 if (non_dma_extra->cname == NULL) { 865 return SOC_E_MEMORY; 866 } 867 sal_sprintf(non_dma_extra->cname, "*%s_PL%d", 868 non_dma_parent->cname, i); 869 870 non_dma_extra->field = non_dma_parent->field; 871 non_dma_extra->reg = non_dma_parent->reg; 872 873 for (pipe = 0; pipe < NUM_PIPE(unit); pipe++) { 874 non_dma_extra->dma_mem[pipe] = 875 SOC_MEM_UNIQUE_ACC(unit, non_dma_extra->mem)[pipe]; 876 877 non_dma_extra->dma_index_max[pipe] = 878 soc_mem_index_max(unit, non_dma_extra->dma_mem[pipe]); 879 non_dma_extra->dma_index_min[pipe] = 0; 880 881 non_dma_extra->dma_buf[pipe] = non_dma_parent->dma_buf[pipe]; 882 *total_entries += (non_dma_extra->dma_index_max[pipe] - 883 non_dma_extra->dma_index_min[pipe] + 1); 884 } 885 /* Allocation of Child Control blocks. 886 * [0],..<even indices> - PKT_CTR non_dma ctrl block 887 * [1],..<odd indices> - BYTE_CTR non_dma ctrl block 888 * Hence in below code, jump by 2, so all similar control blocks are 889 * initilized at the same time. 890 */ 891 non_dma_extra += 2; 892 /* coverity[check_after_deref] */ 893 if (!non_dma_extra) { 894 /* ERR: Cannot be NULL, until 'i reaches 'count' */ 895 /* This condition may not hit but intentional for defensive check */ 896 /* coverity[dead_error_line] */ 897 return SOC_E_INTERNAL; 898 } 899 } else { 900 int entries_per_xpe = 0; 901 int entries_per_pipe = 0; 902 xpe = i; 903 /* Inherit few info from the Parent */ 904 non_dma_extra->flags = (non_dma_parent->flags & 905 ~_SOC_COUNTER_NON_DMA_SUBSET_PARENT) | 906 _SOC_COUNTER_NON_DMA_SUBSET_CHILD; 907 908 non_dma_extra->cname = non_dma_parent->cname; 909 non_dma_extra->field = non_dma_parent->field; 910 non_dma_extra->reg = non_dma_parent->reg; 911 non_dma_extra->entries_per_port = non_dma_parent->entries_per_port; 912 non_dma_extra->id = non_dma_parent->id; 913 non_dma_extra->num_valid_pipe = 0; 914 915 /* Set Child attributes */ 916 non_dma_extra->base_index = parent_base_index + *total_entries; 917 if (non_dma_parent->mem != MMU_CTR_COLOR_DROP_MEMm) { 918 for (pipe = 0; pipe < NUM_PIPE(unit); pipe++) { 919 non_dma_extra->dma_mem[pipe] = 920 SOC_MEM_UNIQUE_ACC_XPE_PIPE(unit, non_dma_parent->mem, 921 xpe, pipe); 922 non_dma_extra->dma_index_min[pipe] = 0; 923 924 if (non_dma_extra->dma_mem[pipe] != INVALIDm) { 925 non_dma_extra->dma_index_max[pipe] = base_mem_ct - 1; 926 non_dma_extra->dma_buf[pipe] = non_dma_parent->dma_buf[pipe]; 927 } else { 928 non_dma_extra->dma_index_max[pipe] = -1; 929 } 930 931 entries_per_pipe = (non_dma_extra->dma_index_max[pipe] - 932 non_dma_extra->dma_index_min[pipe] + 1); 933 if (entries_per_pipe > 0) { 934 non_dma_extra->num_valid_pipe ++; 935 } 936 entries_per_xpe += entries_per_pipe; 937 *total_entries += entries_per_pipe; 938 } 939 non_dma_extra->num_entries = entries_per_xpe; 940 non_dma_extra->mem = non_dma_parent->mem; 941 } else { 942 for(pipe = 0; pipe < NUM_PIPE(unit); pipe++) { 943 non_dma_extra->dma_mem[pipe] = 944 SOC_MEM_UNIQUE_ACC_XPE_PIPE(unit, non_dma_parent->mem, 945 xpe, pipe); 946 if (non_dma_extra->dma_mem[pipe] != INVALIDm) { 947 int mmu_total_ports; 948 949 mmu_total_ports = SOC_IS_HELIX5(unit) ? 72 : 66; 950 non_dma_extra->dma_buf[pipe] = non_dma_parent->dma_buf[pipe]; 951 switch(non_dma_extra->id) { 952 case SOC_COUNTER_NON_DMA_PORT_WRED_PKT_RED: 953 non_dma_extra->dma_index_min[pipe] = 0; 954 non_dma_extra->dma_index_max[pipe] = mmu_total_ports - 1; 955 break; 956 case SOC_COUNTER_NON_DMA_PORT_WRED_PKT_YELLOW: 957 non_dma_extra->dma_index_min[pipe] = mmu_total_ports; 958 non_dma_extra->dma_index_max[pipe]= (mmu_total_ports * 2) - 1; 959 break; 960 case SOC_COUNTER_NON_DMA_PORT_WRED_PKT_GREEN: 961 non_dma_extra->dma_index_min[pipe] = mmu_total_ports * 2; 962 non_dma_extra->dma_index_max[pipe] = (mmu_total_ports * 3) - 1; 963 break; 964 case SOC_COUNTER_NON_DMA_PORT_DROP_PKT_RED: 965 non_dma_extra->dma_index_min[pipe] = mmu_total_ports * 3; 966 non_dma_extra->dma_index_max[pipe] = (mmu_total_ports * 4) - 1; 967 break; 968 case SOC_COUNTER_NON_DMA_PORT_DROP_PKT_YELLOW: 969 non_dma_extra->dma_index_min[pipe] = mmu_total_ports * 4; 970 non_dma_extra->dma_index_max[pipe] = (mmu_total_ports * 5) - 1; 971 break; 972 default: 973 return SOC_E_PARAM; 974 } 975 }else { 976 non_dma_extra->dma_index_max[pipe] = -1; 977 } 978 entries_per_pipe = (non_dma_extra->dma_index_max[pipe] - 979 non_dma_extra->dma_index_min[pipe] + 1); 980 entries_per_xpe += entries_per_pipe; 981 *total_entries += entries_per_pipe; 982 } 983 non_dma_extra->mem = non_dma_parent->mem; 984 non_dma_extra->num_entries += entries_per_xpe; 985 } 986 987 /* Allocation of Child Control blocks. 988 * [0],..<even indices> - PKT_CTR non_dma ctrl block 989 * [1],..<odd indices> - BYTE_CTR non_dma ctrl block 990 * Hence in below code, jump by 2, so all similar control blocks are 991 * initilized at the same time. 992 */ 993 non_dma_extra += 2; 994 /* coverity[check_after_deref] */ 995 if (!non_dma_extra) { 996 /* ERR: Cannot be NULL, until 'i reaches 'count' */ 997 /* coverity[dead_error_line] */ 998 return SOC_E_INTERNAL; 999 } 1000 } 1001 } 1002 return SOC_E_NONE; 1003 } 1004 1005 /* Function to initialize sFlow extra counters */ 1006 int 1007 soc_counter_td3_extra_sflow_ctrs_init(int unit, 1008 soc_counter_non_dma_t *non_dma_parent, 1009 soc_counter_non_dma_t *non_dma_extra, 1010 uint32 extra_ctr_ct, 1011 int *total_entries) 1012 { 1013 int i, parent_base_index = 0; 1014 int base_mem_ct = 0; 1015 int do_dma = 1; 1016 int pipe; 1017 1018 soc_field_t sflow_counter_fields[] = { 1019 SAMPLE_POOLf, 1020 SAMPLE_POOL_SNAPSHOTf, 1021 SAMPLE_COUNTf 1022 }; 1023 1024 /* Do sanity check for input params */ 1025 if (!(non_dma_parent->flags & _SOC_COUNTER_NON_DMA_SUBSET_PARENT)) { 1026 /* Only for Extra counters */ 1027 return SOC_E_PARAM; 1028 } 1029 1030 parent_base_index = non_dma_parent->base_index; 1031 *total_entries = 0; 1032 1033 for (i = 0; i < extra_ctr_ct; i++) { 1034 /* Set Child attributes. Inherit few info from the Parent */ 1035 non_dma_extra->mem = non_dma_parent->mem; 1036 non_dma_extra->base_index = parent_base_index + *total_entries; 1037 base_mem_ct = (soc_mem_index_count(unit, non_dma_extra->mem) * 1038 NUM_PIPE(unit)) / _TD3_PIPES_PER_DEV; 1039 1040 if (NUM_PIPE(unit) == 1) { 1041 base_mem_ct = soc_mem_index_count(unit, non_dma_extra->mem); 1042 } 1043 1044 non_dma_extra->num_entries = base_mem_ct; 1045 1046 non_dma_extra->flags = (non_dma_parent->flags & 1047 ~_SOC_COUNTER_NON_DMA_SUBSET_PARENT) | 1048 _SOC_COUNTER_NON_DMA_SUBSET_CHILD; 1049 1050 /* DMA should be done only once to get sFlow data table */ 1051 if (do_dma != 1) { 1052 non_dma_extra->flags = (non_dma_extra->flags & 1053 ~_SOC_COUNTER_NON_DMA_DO_DMA); 1054 } 1055 1056 non_dma_extra->cname = sal_alloc(sal_strlen(non_dma_parent->cname) + 9, 1057 "Extra ctrs cname"); 1058 1059 if (non_dma_extra->cname == NULL) { 1060 return SOC_E_MEMORY; 1061 } 1062 1063 sal_sprintf(non_dma_extra->cname, "*%s_CNTR%d", 1064 non_dma_parent->cname, i); 1065 1066 non_dma_extra->field = sflow_counter_fields[i]; 1067 non_dma_extra->reg = non_dma_parent->reg; 1068 non_dma_extra->dma_mem[0] = non_dma_parent->mem; 1069 1070 /* No per-pipe instance for sFlow counters memory, hence pipe 1/2/3 1071 * are assigned to INVALIDm 1072 */ 1073 for (pipe = 1; pipe < NUM_PIPE(unit); pipe++) { 1074 non_dma_extra->dma_mem[pipe] = INVALIDm; 1075 } 1076 non_dma_extra->dma_index_max[0] = (soc_mem_index_max(unit, 1077 non_dma_parent->mem) * 1078 NUM_PIPE(unit)) / 1079 _TD3_PIPES_PER_DEV; 1080 if (NUM_PIPE(unit) == 1) { 1081 non_dma_extra->dma_index_max[0] = 1082 soc_mem_index_max(unit, non_dma_parent->mem); 1083 } 1084 1085 for (pipe = 1; pipe < NUM_PIPE(unit); pipe++) { 1086 non_dma_extra->dma_index_max[pipe] = -1; 1087 } 1088 non_dma_extra->dma_index_min[0] = 0; 1089 for (pipe = 1; pipe < NUM_PIPE(unit); pipe++) { 1090 non_dma_extra->dma_index_min[pipe] = -1; 1091 } 1092 non_dma_extra->dma_buf[0] = non_dma_parent->dma_buf[0]; 1093 1094 *total_entries += (non_dma_extra->dma_index_max[0] - 1095 non_dma_extra->dma_index_min[0] + 1); 1096 1097 /* Allocation of Child Control blocks. 1098 * [0],..<even indices> - PKT_CTR non_dma ctrl block 1099 * [1],..<odd indices> - BYTE_CTR non_dma ctrl block 1100 * Hence in below code, jump by 2, so all similar control blocks are 1101 * initilized at the same time. 1102 */ 1103 non_dma_extra += 2; 1104 1105 do_dma = 0; 1106 1107 /* coverity[check_after_deref] */ 1108 if (!non_dma_extra) { 1109 /* ERR: Cannot be NULL, until 'i reaches 'extra_ctr_ct' */ 1110 /* This condition may not hit but intentional for defensive check */ 1111 /* coverity[dead_error_line] */ 1112 return SOC_E_INTERNAL; 1113 } 1114 } 1115 1116 return SOC_E_NONE; 1117 } 1118 1119 /* Function to initialize OBM extra counters */ 1120 STATIC int 1121 soc_counter_trident3_extra_obm_ctrs_init(int unit, 1122 soc_counter_non_dma_t *non_dma_parent, 1123 soc_counter_non_dma_t *non_dma_extra, 1124 uint32 extra_ctr_ct, 1125 int *total_entries) 1126 { 1127 #define LOSSY_LO 0 1128 #define LOSSY_HI 1 1129 #define LOSSLESS0 2 1130 #define LOSSLESS1 3 1131 char obm_type_str[][12] = {"LOSSY_LO", "LOSSY_HI", 1132 "LOSSLESS0", "LOSSLESS1"}; /* For CNAME */ 1133 int i, byte_flag = 0, obm_type = 0, fc = 0, parent_base_index = 0; 1134 uint32 count = 0; 1135 1136 soc_reg_t obm_drop_pkt_regs[][4] = { 1137 {IDB_OBM0_LOSSY_LO_PKT_DROP_COUNTr, IDB_OBM0_LOSSY_HI_PKT_DROP_COUNTr, 1138 IDB_OBM0_LOSSLESS0_PKT_DROP_COUNTr, IDB_OBM0_LOSSLESS1_PKT_DROP_COUNTr 1139 }, 1140 {IDB_OBM1_LOSSY_LO_PKT_DROP_COUNTr, IDB_OBM1_LOSSY_HI_PKT_DROP_COUNTr, 1141 IDB_OBM1_LOSSLESS0_PKT_DROP_COUNTr, IDB_OBM1_LOSSLESS1_PKT_DROP_COUNTr 1142 }, 1143 {IDB_OBM2_LOSSY_LO_PKT_DROP_COUNTr, IDB_OBM2_LOSSY_HI_PKT_DROP_COUNTr, 1144 IDB_OBM2_LOSSLESS0_PKT_DROP_COUNTr, IDB_OBM2_LOSSLESS1_PKT_DROP_COUNTr 1145 }, 1146 {IDB_OBM3_LOSSY_LO_PKT_DROP_COUNTr, IDB_OBM3_LOSSY_HI_PKT_DROP_COUNTr, 1147 IDB_OBM3_LOSSLESS0_PKT_DROP_COUNTr, IDB_OBM3_LOSSLESS1_PKT_DROP_COUNTr 1148 }, 1149 {IDB_OBM4_LOSSY_LO_PKT_DROP_COUNTr, IDB_OBM4_LOSSY_HI_PKT_DROP_COUNTr, 1150 IDB_OBM4_LOSSLESS0_PKT_DROP_COUNTr, IDB_OBM4_LOSSLESS1_PKT_DROP_COUNTr 1151 }, 1152 {IDB_OBM5_LOSSY_LO_PKT_DROP_COUNTr, IDB_OBM5_LOSSY_HI_PKT_DROP_COUNTr, 1153 IDB_OBM5_LOSSLESS0_PKT_DROP_COUNTr, IDB_OBM5_LOSSLESS1_PKT_DROP_COUNTr 1154 }, 1155 {IDB_OBM6_LOSSY_LO_PKT_DROP_COUNTr, IDB_OBM6_LOSSY_HI_PKT_DROP_COUNTr, 1156 IDB_OBM6_LOSSLESS0_PKT_DROP_COUNTr, IDB_OBM6_LOSSLESS1_PKT_DROP_COUNTr 1157 }, 1158 {IDB_OBM7_LOSSY_LO_PKT_DROP_COUNTr, IDB_OBM7_LOSSY_HI_PKT_DROP_COUNTr, 1159 IDB_OBM7_LOSSLESS0_PKT_DROP_COUNTr, IDB_OBM7_LOSSLESS1_PKT_DROP_COUNTr 1160 }, 1161 {IDB_OBM8_LOSSY_LO_PKT_DROP_COUNTr, IDB_OBM8_LOSSY_HI_PKT_DROP_COUNTr, 1162 IDB_OBM8_LOSSLESS0_PKT_DROP_COUNTr, IDB_OBM8_LOSSLESS1_PKT_DROP_COUNTr 1163 }, 1164 {IDB_OBM9_LOSSY_LO_PKT_DROP_COUNTr, IDB_OBM9_LOSSY_HI_PKT_DROP_COUNTr, 1165 IDB_OBM9_LOSSLESS0_PKT_DROP_COUNTr, IDB_OBM9_LOSSLESS1_PKT_DROP_COUNTr 1166 }, 1167 {IDB_OBM10_LOSSY_LO_PKT_DROP_COUNTr, IDB_OBM10_LOSSY_HI_PKT_DROP_COUNTr, 1168 IDB_OBM10_LOSSLESS0_PKT_DROP_COUNTr, IDB_OBM10_LOSSLESS1_PKT_DROP_COUNTr 1169 }, 1170 {IDB_OBM11_LOSSY_LO_PKT_DROP_COUNTr, IDB_OBM11_LOSSY_HI_PKT_DROP_COUNTr, 1171 IDB_OBM11_LOSSLESS0_PKT_DROP_COUNTr, IDB_OBM11_LOSSLESS1_PKT_DROP_COUNTr 1172 }, 1173 {IDB_OBM12_LOSSY_LO_PKT_DROP_COUNTr, IDB_OBM12_LOSSY_HI_PKT_DROP_COUNTr, 1174 IDB_OBM12_LOSSLESS0_PKT_DROP_COUNTr, IDB_OBM12_LOSSLESS1_PKT_DROP_COUNTr 1175 }, 1176 {IDB_OBM13_LOSSY_LO_PKT_DROP_COUNTr, IDB_OBM13_LOSSY_HI_PKT_DROP_COUNTr, 1177 IDB_OBM13_LOSSLESS0_PKT_DROP_COUNTr, IDB_OBM13_LOSSLESS1_PKT_DROP_COUNTr 1178 }, 1179 {IDB_OBM14_LOSSY_LO_PKT_DROP_COUNTr, IDB_OBM14_LOSSY_HI_PKT_DROP_COUNTr, 1180 IDB_OBM14_LOSSLESS0_PKT_DROP_COUNTr, IDB_OBM14_LOSSLESS1_PKT_DROP_COUNTr 1181 }, 1182 {IDB_OBM15_LOSSY_LO_PKT_DROP_COUNTr, IDB_OBM15_LOSSY_HI_PKT_DROP_COUNTr, 1183 IDB_OBM15_LOSSLESS0_PKT_DROP_COUNTr, IDB_OBM15_LOSSLESS1_PKT_DROP_COUNTr 1184 }, 1185 #ifdef BCM_MAVERICK2_SUPPORT 1186 {IDB_OBM16_LOSSY_LO_PKT_DROP_COUNTr, IDB_OBM16_LOSSY_HI_PKT_DROP_COUNTr, 1187 IDB_OBM16_LOSSLESS0_PKT_DROP_COUNTr, IDB_OBM16_LOSSLESS1_PKT_DROP_COUNTr 1188 }, 1189 {IDB_OBM17_LOSSY_LO_PKT_DROP_COUNTr, IDB_OBM17_LOSSY_HI_PKT_DROP_COUNTr, 1190 IDB_OBM17_LOSSLESS0_PKT_DROP_COUNTr, IDB_OBM17_LOSSLESS1_PKT_DROP_COUNTr 1191 }, 1192 {IDB_OBM18_LOSSY_LO_PKT_DROP_COUNTr, IDB_OBM18_LOSSY_HI_PKT_DROP_COUNTr, 1193 IDB_OBM18_LOSSLESS0_PKT_DROP_COUNTr, IDB_OBM18_LOSSLESS1_PKT_DROP_COUNTr 1194 }, 1195 {IDB_OBM19_LOSSY_LO_PKT_DROP_COUNTr, IDB_OBM19_LOSSY_HI_PKT_DROP_COUNTr, 1196 IDB_OBM19_LOSSLESS0_PKT_DROP_COUNTr, IDB_OBM19_LOSSLESS1_PKT_DROP_COUNTr 1197 }, 1198 #endif 1199 }; 1200 soc_reg_t obm_drop_byte_regs[][4] = { 1201 {IDB_OBM0_LOSSY_LO_BYTE_DROP_COUNTr, IDB_OBM0_LOSSY_HI_BYTE_DROP_COUNTr, 1202 IDB_OBM0_LOSSLESS0_BYTE_DROP_COUNTr, IDB_OBM0_LOSSLESS1_BYTE_DROP_COUNTr 1203 }, 1204 {IDB_OBM1_LOSSY_LO_BYTE_DROP_COUNTr, IDB_OBM1_LOSSY_HI_BYTE_DROP_COUNTr, 1205 IDB_OBM1_LOSSLESS0_BYTE_DROP_COUNTr, IDB_OBM1_LOSSLESS1_BYTE_DROP_COUNTr 1206 }, 1207 {IDB_OBM2_LOSSY_LO_BYTE_DROP_COUNTr, IDB_OBM2_LOSSY_HI_BYTE_DROP_COUNTr, 1208 IDB_OBM2_LOSSLESS0_BYTE_DROP_COUNTr, IDB_OBM2_LOSSLESS1_BYTE_DROP_COUNTr 1209 }, 1210 {IDB_OBM3_LOSSY_LO_BYTE_DROP_COUNTr, IDB_OBM3_LOSSY_HI_BYTE_DROP_COUNTr, 1211 IDB_OBM3_LOSSLESS0_BYTE_DROP_COUNTr, IDB_OBM3_LOSSLESS1_BYTE_DROP_COUNTr 1212 }, 1213 {IDB_OBM4_LOSSY_LO_BYTE_DROP_COUNTr, IDB_OBM4_LOSSY_HI_BYTE_DROP_COUNTr, 1214 IDB_OBM4_LOSSLESS0_BYTE_DROP_COUNTr, IDB_OBM4_LOSSLESS1_BYTE_DROP_COUNTr 1215 }, 1216 {IDB_OBM5_LOSSY_LO_BYTE_DROP_COUNTr, IDB_OBM5_LOSSY_HI_BYTE_DROP_COUNTr, 1217 IDB_OBM5_LOSSLESS0_BYTE_DROP_COUNTr, IDB_OBM5_LOSSLESS1_BYTE_DROP_COUNTr 1218 }, 1219 {IDB_OBM6_LOSSY_LO_BYTE_DROP_COUNTr, IDB_OBM6_LOSSY_HI_BYTE_DROP_COUNTr, 1220 IDB_OBM6_LOSSLESS0_BYTE_DROP_COUNTr, IDB_OBM6_LOSSLESS1_BYTE_DROP_COUNTr 1221 }, 1222 {IDB_OBM7_LOSSY_LO_BYTE_DROP_COUNTr, IDB_OBM7_LOSSY_HI_BYTE_DROP_COUNTr, 1223 IDB_OBM7_LOSSLESS0_BYTE_DROP_COUNTr, IDB_OBM7_LOSSLESS1_BYTE_DROP_COUNTr 1224 }, 1225 {IDB_OBM8_LOSSY_LO_BYTE_DROP_COUNTr, IDB_OBM8_LOSSY_HI_BYTE_DROP_COUNTr, 1226 IDB_OBM8_LOSSLESS0_BYTE_DROP_COUNTr, IDB_OBM8_LOSSLESS1_BYTE_DROP_COUNTr 1227 }, 1228 {IDB_OBM9_LOSSY_LO_BYTE_DROP_COUNTr, IDB_OBM9_LOSSY_HI_BYTE_DROP_COUNTr, 1229 IDB_OBM9_LOSSLESS0_BYTE_DROP_COUNTr, IDB_OBM9_LOSSLESS1_BYTE_DROP_COUNTr 1230 }, 1231 {IDB_OBM10_LOSSY_LO_BYTE_DROP_COUNTr, IDB_OBM10_LOSSY_HI_BYTE_DROP_COUNTr, 1232 IDB_OBM10_LOSSLESS0_BYTE_DROP_COUNTr, IDB_OBM10_LOSSLESS1_BYTE_DROP_COUNTr 1233 }, 1234 {IDB_OBM11_LOSSY_LO_BYTE_DROP_COUNTr, IDB_OBM11_LOSSY_HI_BYTE_DROP_COUNTr, 1235 IDB_OBM11_LOSSLESS0_BYTE_DROP_COUNTr, IDB_OBM11_LOSSLESS1_BYTE_DROP_COUNTr 1236 }, 1237 {IDB_OBM12_LOSSY_LO_BYTE_DROP_COUNTr, IDB_OBM12_LOSSY_HI_BYTE_DROP_COUNTr, 1238 IDB_OBM12_LOSSLESS0_BYTE_DROP_COUNTr, IDB_OBM12_LOSSLESS1_BYTE_DROP_COUNTr 1239 }, 1240 {IDB_OBM13_LOSSY_LO_BYTE_DROP_COUNTr, IDB_OBM13_LOSSY_HI_BYTE_DROP_COUNTr, 1241 IDB_OBM13_LOSSLESS0_BYTE_DROP_COUNTr, IDB_OBM13_LOSSLESS1_BYTE_DROP_COUNTr 1242 }, 1243 {IDB_OBM14_LOSSY_LO_BYTE_DROP_COUNTr, IDB_OBM14_LOSSY_HI_BYTE_DROP_COUNTr, 1244 IDB_OBM14_LOSSLESS0_BYTE_DROP_COUNTr, IDB_OBM14_LOSSLESS1_BYTE_DROP_COUNTr 1245 }, 1246 {IDB_OBM15_LOSSY_LO_BYTE_DROP_COUNTr, IDB_OBM15_LOSSY_HI_BYTE_DROP_COUNTr, 1247 IDB_OBM15_LOSSLESS0_BYTE_DROP_COUNTr, IDB_OBM15_LOSSLESS1_BYTE_DROP_COUNTr 1248 }, 1249 #ifdef BCM_MAVERICK2_SUPPORT 1250 {IDB_OBM16_LOSSY_LO_BYTE_DROP_COUNTr, IDB_OBM16_LOSSY_HI_BYTE_DROP_COUNTr, 1251 IDB_OBM16_LOSSLESS0_BYTE_DROP_COUNTr, IDB_OBM16_LOSSLESS1_BYTE_DROP_COUNTr 1252 }, 1253 {IDB_OBM17_LOSSY_LO_BYTE_DROP_COUNTr, IDB_OBM17_LOSSY_HI_BYTE_DROP_COUNTr, 1254 IDB_OBM17_LOSSLESS0_BYTE_DROP_COUNTr, IDB_OBM17_LOSSLESS1_BYTE_DROP_COUNTr 1255 }, 1256 {IDB_OBM18_LOSSY_LO_BYTE_DROP_COUNTr, IDB_OBM18_LOSSY_HI_BYTE_DROP_COUNTr, 1257 IDB_OBM18_LOSSLESS0_BYTE_DROP_COUNTr, IDB_OBM18_LOSSLESS1_BYTE_DROP_COUNTr 1258 }, 1259 {IDB_OBM19_LOSSY_LO_BYTE_DROP_COUNTr, IDB_OBM19_LOSSY_HI_BYTE_DROP_COUNTr, 1260 IDB_OBM19_LOSSLESS0_BYTE_DROP_COUNTr, IDB_OBM19_LOSSLESS1_BYTE_DROP_COUNTr 1261 }, 1262 #endif 1263 }; 1264 soc_reg_t obm_fc_event_regs[] = { 1265 IDB_OBM0_FLOW_CONTROL_EVENT_COUNTr, 1266 IDB_OBM1_FLOW_CONTROL_EVENT_COUNTr, 1267 IDB_OBM2_FLOW_CONTROL_EVENT_COUNTr, 1268 IDB_OBM3_FLOW_CONTROL_EVENT_COUNTr, 1269 IDB_OBM4_FLOW_CONTROL_EVENT_COUNTr, 1270 IDB_OBM5_FLOW_CONTROL_EVENT_COUNTr, 1271 IDB_OBM6_FLOW_CONTROL_EVENT_COUNTr, 1272 IDB_OBM7_FLOW_CONTROL_EVENT_COUNTr, 1273 IDB_OBM8_FLOW_CONTROL_EVENT_COUNTr, 1274 IDB_OBM9_FLOW_CONTROL_EVENT_COUNTr, 1275 IDB_OBM10_FLOW_CONTROL_EVENT_COUNTr, 1276 IDB_OBM11_FLOW_CONTROL_EVENT_COUNTr, 1277 IDB_OBM12_FLOW_CONTROL_EVENT_COUNTr, 1278 IDB_OBM13_FLOW_CONTROL_EVENT_COUNTr, 1279 IDB_OBM14_FLOW_CONTROL_EVENT_COUNTr, 1280 IDB_OBM15_FLOW_CONTROL_EVENT_COUNTr, 1281 #ifdef BCM_MAVERICK2_SUPPORT 1282 IDB_OBM16_FLOW_CONTROL_EVENT_COUNTr, 1283 IDB_OBM17_FLOW_CONTROL_EVENT_COUNTr, 1284 IDB_OBM18_FLOW_CONTROL_EVENT_COUNTr, 1285 IDB_OBM19_FLOW_CONTROL_EVENT_COUNTr, 1286 #endif 1287 }; 1288 count = COUNTOF(obm_drop_byte_regs); 1289 if (count < extra_ctr_ct) { 1290 return SOC_E_PARAM; 1291 } 1292 1293 /* Do sanity check for input params */ 1294 if (!(non_dma_parent->flags & _SOC_COUNTER_NON_DMA_SUBSET_PARENT)) { 1295 /* Only for Extra counters */ 1296 return SOC_E_PARAM; 1297 } 1298 switch (non_dma_parent->id) { 1299 case SOC_COUNTER_NON_DMA_PORT_DROP_PKT_OBM_LOSSY_LO: 1300 case SOC_COUNTER_NON_DMA_PORT_DROP_PKT_OBM_LOSSY_HI: 1301 case SOC_COUNTER_NON_DMA_PORT_DROP_PKT_OBM_LOSSLESS0: 1302 case SOC_COUNTER_NON_DMA_PORT_DROP_PKT_OBM_LOSSLESS1: 1303 byte_flag = 0; 1304 break; 1305 case SOC_COUNTER_NON_DMA_PORT_DROP_BYTE_OBM_LOSSY_LO: 1306 case SOC_COUNTER_NON_DMA_PORT_DROP_BYTE_OBM_LOSSY_HI: 1307 case SOC_COUNTER_NON_DMA_PORT_DROP_BYTE_OBM_LOSSLESS0: 1308 case SOC_COUNTER_NON_DMA_PORT_DROP_BYTE_OBM_LOSSLESS1: 1309 byte_flag = 1; 1310 break; 1311 case SOC_COUNTER_NON_DMA_PORT_OBM_FC_EVENTS: 1312 fc = 1; 1313 break; 1314 default: 1315 return SOC_E_PARAM; 1316 } 1317 1318 switch (non_dma_parent->id) { 1319 case SOC_COUNTER_NON_DMA_PORT_DROP_PKT_OBM_LOSSY_LO: 1320 case SOC_COUNTER_NON_DMA_PORT_DROP_BYTE_OBM_LOSSY_LO: 1321 obm_type = LOSSY_LO; 1322 break; 1323 case SOC_COUNTER_NON_DMA_PORT_DROP_PKT_OBM_LOSSY_HI: 1324 case SOC_COUNTER_NON_DMA_PORT_DROP_BYTE_OBM_LOSSY_HI: 1325 obm_type = LOSSY_HI; 1326 break; 1327 case SOC_COUNTER_NON_DMA_PORT_DROP_PKT_OBM_LOSSLESS0: 1328 case SOC_COUNTER_NON_DMA_PORT_DROP_BYTE_OBM_LOSSLESS0: 1329 obm_type = LOSSLESS0; 1330 break; 1331 case SOC_COUNTER_NON_DMA_PORT_DROP_PKT_OBM_LOSSLESS1: 1332 case SOC_COUNTER_NON_DMA_PORT_DROP_BYTE_OBM_LOSSLESS1: 1333 obm_type = LOSSLESS1; 1334 break; 1335 } 1336 1337 parent_base_index = non_dma_parent->base_index; 1338 *total_entries = 0; 1339 1340 for (i = 0; i < extra_ctr_ct; i++) { 1341 *non_dma_extra = *non_dma_parent; 1342 if (fc) { 1343 non_dma_extra->reg = obm_fc_event_regs[i]; 1344 } else if (byte_flag == 0) { 1345 non_dma_extra->reg = obm_drop_pkt_regs[i][obm_type]; 1346 } else { 1347 non_dma_extra->reg = obm_drop_byte_regs[i][obm_type]; 1348 } 1349 non_dma_extra->extra_ctrs = NULL; 1350 non_dma_extra->extra_ctr_ct = 0; 1351 non_dma_extra->base_index = parent_base_index + *total_entries; 1352 non_dma_extra->flags = (non_dma_parent->flags & 1353 ~_SOC_COUNTER_NON_DMA_SUBSET_PARENT) | 1354 _SOC_COUNTER_NON_DMA_SUBSET_CHILD; 1355 1356 non_dma_extra->cname = sal_alloc(sal_strlen(non_dma_parent->cname) + 9, 1357 "Extra ctrs cname"); 1358 1359 if (non_dma_extra->cname == NULL) { 1360 return SOC_E_MEMORY; 1361 } 1362 1363 if (fc) { 1364 sal_sprintf(non_dma_extra->cname, "*OBM%d_FC_EVENTS", i); 1365 } else { 1366 sal_sprintf(non_dma_extra->cname, "*OBM%d_%s_DRP_%s", 1367 i, obm_type_str[obm_type], byte_flag ? "BYTE":"PKT"); 1368 } 1369 1370 non_dma_extra->num_entries = non_dma_extra->entries_per_port * 1371 NUM_PIPE(unit); 1372 *total_entries += non_dma_extra->num_entries; 1373 1374 /* Allocation of Child Control blocks. 1375 * [0],..<even indices> - PKT_CTR non_dma ctrl block 1376 * [1],..<odd indices> - BYTE_CTR non_dma ctrl block 1377 * Hence in below code, jump by 2, so all similar control blocks are 1378 * initilized at the same time. 1379 */ 1380 non_dma_extra += 2; 1381 /* coverity[check_after_deref] */ 1382 if (!non_dma_extra) { 1383 /* ERR: Cannot be NULL, until 'i reaches 'extra_ctr_ct' */ 1384 /* This condition may not hit but intentional for defensive check */ 1385 /* coverity[dead_error_line] */ 1386 return SOC_E_INTERNAL; 1387 } 1388 } 1389 return SOC_E_NONE; 1390 } 1391 1392 /* Trident3 Counters are of 2 types: 1393 * 1. Traditional Non-StatDma 1394 * 2. Counter Eviction eligible counters. 1395 * 1396 * When Counter Eviction is enabled, HW performs Clear on Read on the eviction 1397 * enabled counters when a Read is performed. 1398 * 1399 * When Counter Eviction is disabled, all counters will work as in TD2. 1400 */ 1401 int 1402 soc_counter_trident3_non_dma_init(int unit, int nports, 1403 int non_dma_start_index, 1404 int *non_dma_entries) 1405 { 1406 soc_control_t *soc; 1407 soc_counter_non_dma_t *non_dma0, *non_dma1, *non_dma2, *temp; 1408 int rv = SOC_E_NONE; 1409 int num_entries, alloc_size, entry_words, pipe, num_extra_ctr_entries; 1410 int pool_count = 0; 1411 soc_mem_t child_mem = INVALIDm; 1412 uint32 *buf; 1413 soc_counter_control_t *soc_ctr_ctrl = SOC_CTR_CTRL(unit); 1414 1415 if (soc_ctr_ctrl == NULL) { 1416 return SOC_E_INIT; 1417 } 1418 1419 soc = SOC_CONTROL(unit); 1420 *non_dma_entries = 0; 1421 1422 /* Registration of Chip specific functions to the Global Counter 1423 * control structure. 1424 */ 1425 soc_ctr_ctrl->get_child_dma = soc_counter_trident3_get_child_dma; 1426 soc_ctr_ctrl->dma_config_update = soc_counter_trident3_dma_flags_update; 1427 soc_ctr_ctrl->port_obm_info_get = soc_trident3_port_obm_info_get; 1428 1429 /* ING_FLEX_CTR_COUNTER_TABLE_0 is the largest table to be DMA'ed */ 1430 num_entries = soc_mem_index_count(unit, ING_FLEX_CTR_COUNTER_TABLE_0m); 1431 entry_words = soc_mem_entry_words(unit, ING_FLEX_CTR_COUNTER_TABLE_0m); 1432 alloc_size = NUM_PIPE(unit) * num_entries * sizeof(uint32) * entry_words; 1433 1434 buf = soc_cm_salloc(unit, alloc_size, "non_dma_counter"); 1435 if (buf == NULL) { 1436 return SOC_E_MEMORY; 1437 } 1438 sal_memset(buf, 0, alloc_size); 1439 1440 /* EGR_PERQ counters - Control Block 1441 * Eviction enabled counter 1442 */ 1443 non_dma0 = &soc->counter_non_dma[SOC_COUNTER_NON_DMA_EGR_PERQ_XMT_PKT - 1444 SOC_COUNTER_NON_DMA_START]; 1445 non_dma0->id = SOC_COUNTER_NON_DMA_EGR_PERQ_XMT_PKT; 1446 non_dma0->flags = _SOC_COUNTER_NON_DMA_VALID | 1447 _SOC_COUNTER_NON_DMA_DO_DMA | 1448 _SOC_COUNTER_NON_DMA_ALLOC | 1449 _SOC_COUNTER_NON_DMA_CTR_EVICT; 1450 1451 non_dma0->dma_rate_profile |= _SOC_COUNTER_DMA_RATE_PROFILE_ALL; 1452 1453 non_dma0->pbmp = PBMP_ALL(unit); 1454 non_dma0->base_index = non_dma_start_index + *non_dma_entries; 1455 non_dma0->entries_per_port = 48; /* cpu port has max number of queues */ 1456 non_dma0->num_entries = 1457 NUM_PIPE(unit) * soc_mem_index_count(unit, EGR_PERQ_XMT_COUNTERSm); 1458 non_dma0->mem = EGR_PERQ_XMT_COUNTERSm; 1459 non_dma0->reg = INVALIDr; 1460 non_dma0->field = PACKET_COUNTERf; 1461 non_dma0->cname = "MC_PERQ_PKT"; 1462 num_entries = soc_mem_index_count(unit, EGR_PERQ_XMT_COUNTERSm); 1463 entry_words = soc_mem_entry_words(unit, EGR_PERQ_XMT_COUNTERSm); 1464 1465 for (pipe = 0; pipe < NUM_PIPE(unit); pipe++) { 1466 non_dma0->dma_mem[pipe] = 1467 SOC_MEM_UNIQUE_ACC(unit, non_dma0->mem)[pipe]; 1468 non_dma0->dma_buf[pipe] = &buf[num_entries * entry_words * pipe]; 1469 non_dma0->dma_index_max[pipe] = 1470 soc_mem_index_max(unit, non_dma0->dma_mem[pipe]); 1471 } 1472 1473 *non_dma_entries += non_dma0->num_entries; 1474 non_dma1 = &soc->counter_non_dma[SOC_COUNTER_NON_DMA_EGR_PERQ_XMT_BYTE - 1475 SOC_COUNTER_NON_DMA_START]; 1476 *non_dma1 = *non_dma0; 1477 non_dma1->id = SOC_COUNTER_NON_DMA_EGR_PERQ_XMT_BYTE; 1478 non_dma1->flags = _SOC_COUNTER_NON_DMA_VALID | 1479 _SOC_COUNTER_NON_DMA_CTR_EVICT; 1480 non_dma0->dma_rate_profile |= _SOC_COUNTER_DMA_RATE_PROFILE0; 1481 non_dma1->base_index = non_dma_start_index + *non_dma_entries; 1482 non_dma1->field = BYTE_COUNTERf; 1483 non_dma1->cname = "MC_PERQ_BYTE"; 1484 *non_dma_entries += non_dma1->num_entries; 1485 1486 non_dma2 = &soc->counter_non_dma[SOC_COUNTER_NON_DMA_EGR_PERQ_XMT_PKT_UC - 1487 SOC_COUNTER_NON_DMA_START]; 1488 *non_dma2 = *non_dma0; 1489 non_dma2->id = SOC_COUNTER_NON_DMA_EGR_PERQ_XMT_PKT_UC; 1490 non_dma2->flags = _SOC_COUNTER_NON_DMA_VALID | 1491 _SOC_COUNTER_NON_DMA_CTR_EVICT; 1492 non_dma2->dma_rate_profile |= _SOC_COUNTER_DMA_RATE_PROFILE0; 1493 non_dma2->pbmp = PBMP_PORT_ALL(unit); 1494 non_dma2->entries_per_port = 10; /* 10 UC Qs Per port */ 1495 non_dma2->num_entries = 0; 1496 non_dma2->cname = "UC_PERQ_PKT"; 1497 1498 non_dma2 = &soc->counter_non_dma[SOC_COUNTER_NON_DMA_EGR_PERQ_XMT_BYTE_UC - 1499 SOC_COUNTER_NON_DMA_START]; 1500 *non_dma2 = *non_dma1; 1501 non_dma2->id = SOC_COUNTER_NON_DMA_EGR_PERQ_XMT_BYTE_UC; 1502 non_dma2->flags = _SOC_COUNTER_NON_DMA_VALID | 1503 _SOC_COUNTER_NON_DMA_CTR_EVICT; 1504 non_dma2->dma_rate_profile |= _SOC_COUNTER_DMA_RATE_PROFILE0; 1505 non_dma2->pbmp = PBMP_PORT_ALL(unit); 1506 non_dma2->entries_per_port = 10; /* 10 UC Qs Per port */ 1507 non_dma2->num_entries = 0; 1508 non_dma2->cname = "UC_PERQ_BYTE"; 1509 /* End of EGR_PERQ counter control block */ 1510 1511 /* CTR_MC_DROP Counters - Control Block */ 1512 non_dma0 = &soc->counter_non_dma[SOC_COUNTER_NON_DMA_COSQ_DROP_PKT - 1513 SOC_COUNTER_NON_DMA_START]; 1514 non_dma0->id = SOC_COUNTER_NON_DMA_COSQ_DROP_PKT; 1515 non_dma0->flags = _SOC_COUNTER_NON_DMA_VALID | 1516 _SOC_COUNTER_NON_DMA_DO_DMA | 1517 _SOC_COUNTER_NON_DMA_SUBSET_PARENT; 1518 non_dma0->pbmp = PBMP_ALL(unit); 1519 non_dma0->base_index = non_dma_start_index + *non_dma_entries; 1520 non_dma0->entries_per_port = 48; /* 48 for cpu port */ 1521 non_dma0->mem = MMU_CTR_MC_DROP_MEMm; 1522 1523 /* MMU memories with Unique access type have number of entries in base view 1524 * set to zero. So, get number of entries from first expanded view 1525 */ 1526 child_mem = SOC_MEM_UNIQUE_ACC_XPE_PIPE(unit, non_dma0->mem, 0, 0); 1527 num_entries = soc_mem_index_max(unit, child_mem) + 1; 1528 entry_words = soc_mem_entry_words(unit, non_dma0->mem); 1529 non_dma0->num_entries = NUM_PIPE(unit) * num_entries; 1530 non_dma0->reg = INVALIDr; 1531 non_dma0->field = PKTCNTf; 1532 non_dma0->cname = "PERQ_DROP_PKT"; 1533 1534 for(pipe = 0; pipe < NUM_PIPE(unit);pipe++) { 1535 non_dma0->dma_mem[pipe] = 1536 SOC_MEM_UNIQUE_ACC_XPE_PIPE(unit, non_dma0->mem, 0, pipe); 1537 non_dma0->dma_buf[pipe] = &buf[num_entries * entry_words * pipe]; 1538 non_dma0->dma_index_max[pipe] = 1539 soc_mem_index_max(unit, non_dma0->dma_mem[pipe]); 1540 } 1541 1542 non_dma0->extra_ctr_ct = NUM_XPE(unit); 1543 /* Incl. buffer for BYTE_CTR. 2x alloc size*/ 1544 alloc_size = (non_dma0->extra_ctr_ct << 1) * sizeof(soc_counter_non_dma_t); 1545 non_dma0->extra_ctrs = sal_alloc(alloc_size, "non_dma_ctrs_perq_drop_mc"); 1546 1547 if (non_dma0->extra_ctrs == NULL) { 1548 non_dma0->extra_ctr_ct = 0; 1549 non_dma0->flags &= ~_SOC_COUNTER_NON_DMA_VALID; 1550 return SOC_E_MEMORY; 1551 } else { 1552 sal_memset(non_dma0->extra_ctrs, 0, alloc_size); 1553 rv = soc_counter_trident3_extra_ctrs_init(unit, 1554 SOC_COUNTER_NON_DMA_COSQ_DROP_PKT, 1555 non_dma0, 1556 non_dma0->extra_ctrs, 1557 non_dma0->extra_ctr_ct, 1558 &num_extra_ctr_entries); 1559 if (rv != SOC_E_NONE) { 1560 LOG_CLI((BSL_META_U(unit, 1561 "ERR: Extra ctrs Init FAILED for id %d\n"), 1562 SOC_COUNTER_NON_DMA_COSQ_DROP_PKT - 1563 SOC_COUNTER_NON_DMA_START)); 1564 } 1565 non_dma0->num_entries = num_extra_ctr_entries; 1566 } 1567 1568 *non_dma_entries += non_dma0->num_entries; 1569 1570 non_dma1 = &soc->counter_non_dma[SOC_COUNTER_NON_DMA_COSQ_DROP_BYTE - 1571 SOC_COUNTER_NON_DMA_START]; 1572 *non_dma1 = *non_dma0; 1573 non_dma1->id = SOC_COUNTER_NON_DMA_COSQ_DROP_BYTE; 1574 non_dma1->flags = _SOC_COUNTER_NON_DMA_VALID | 1575 _SOC_COUNTER_NON_DMA_SUBSET_PARENT; 1576 non_dma1->base_index = non_dma_start_index + *non_dma_entries; 1577 non_dma1->field = BYTECNTf; 1578 non_dma1->cname = "PERQ_DROP_BYTE"; 1579 non_dma1->extra_ctr_ct = NUM_XPE(unit); 1580 1581 /* Memory for extra ctrs for BYTE_CTRS are done along with PACKET_CTR */ 1582 non_dma1->extra_ctrs = non_dma0->extra_ctrs + 1; 1583 1584 if (non_dma0->extra_ctrs) { 1585 rv = soc_counter_trident3_extra_ctrs_init(unit, 1586 SOC_COUNTER_NON_DMA_COSQ_DROP_BYTE, 1587 non_dma1, 1588 non_dma1->extra_ctrs, 1589 non_dma1->extra_ctr_ct, 1590 &num_extra_ctr_entries); 1591 if (rv != SOC_E_NONE) { 1592 LOG_CLI((BSL_META_U(unit, 1593 "ERR: Extra ctrs Init FAILED for id %d\n"), 1594 SOC_COUNTER_NON_DMA_COSQ_DROP_BYTE - 1595 SOC_COUNTER_NON_DMA_START)); 1596 } 1597 } 1598 non_dma1->flags = _SOC_COUNTER_NON_DMA_SUBSET_PARENT; 1599 *non_dma_entries += non_dma1->num_entries; 1600 /* End of CTR_MC_DROP Control Block */ 1601 1602 /* DROP_PKT_UC Counters - Control Block */ 1603 non_dma0 = &soc->counter_non_dma[SOC_COUNTER_NON_DMA_COSQ_DROP_PKT_UC - 1604 SOC_COUNTER_NON_DMA_START]; 1605 non_dma0->id = SOC_COUNTER_NON_DMA_COSQ_DROP_PKT_UC; 1606 non_dma0->flags = _SOC_COUNTER_NON_DMA_VALID | 1607 _SOC_COUNTER_NON_DMA_DO_DMA | 1608 _SOC_COUNTER_NON_DMA_SUBSET_PARENT; 1609 non_dma0->pbmp = PBMP_PORT_ALL(unit); 1610 non_dma0->base_index = non_dma_start_index + *non_dma_entries; 1611 non_dma0->entries_per_port = 10; /* 10 UC queues per port */ 1612 non_dma0->mem = MMU_CTR_UC_DROP_MEMm; 1613 1614 /* MMU memories with Unique access type have number of entries in base view 1615 * set to zero. So, get number of entries from first expanded view 1616 */ 1617 child_mem = SOC_MEM_UNIQUE_ACC_XPE_PIPE(unit, non_dma0->mem, 0, 0); 1618 num_entries = soc_mem_index_max(unit, child_mem) + 1; 1619 entry_words = soc_mem_entry_words(unit, non_dma0->mem); 1620 non_dma0->num_entries = NUM_PIPE(unit) * num_entries; 1621 non_dma0->reg = INVALIDr; 1622 non_dma0->field = PKTCNTf; 1623 non_dma0->cname = "PERQ_DROP_PKT_UC"; 1624 1625 for (pipe = 0; pipe < NUM_PIPE(unit); pipe++) { 1626 non_dma0->dma_mem[pipe] = 1627 SOC_MEM_UNIQUE_ACC_XPE_PIPE(unit, non_dma0->mem, 0, pipe); 1628 non_dma0->dma_buf[pipe] = &buf[num_entries * entry_words * pipe]; 1629 non_dma0->dma_index_max[pipe] = 1630 soc_mem_index_max(unit, non_dma0->dma_mem[pipe]); 1631 } 1632 1633 non_dma0->extra_ctr_ct = NUM_XPE(unit); 1634 /* Incl. buffer for BYTE_CTR. 2x alloc size*/ 1635 alloc_size = (non_dma0->extra_ctr_ct << 1) * sizeof(soc_counter_non_dma_t); 1636 non_dma0->extra_ctrs = sal_alloc(alloc_size, "non_dma_ctrs_perq_drop_uc"); 1637 1638 if (non_dma0->extra_ctrs == NULL) { 1639 non_dma0->extra_ctr_ct = 0; 1640 non_dma0->flags &= ~_SOC_COUNTER_NON_DMA_VALID; 1641 return SOC_E_MEMORY; 1642 } else { 1643 sal_memset(non_dma0->extra_ctrs, 0, alloc_size); 1644 rv = soc_counter_trident3_extra_ctrs_init(unit, 1645 SOC_COUNTER_NON_DMA_COSQ_DROP_PKT_UC, 1646 non_dma0, 1647 non_dma0->extra_ctrs, 1648 non_dma0->extra_ctr_ct, 1649 &num_extra_ctr_entries); 1650 if (rv != SOC_E_NONE) { 1651 LOG_CLI((BSL_META_U(unit, 1652 "ERR: Extra ctrs Init FAILED for id %d\n"), 1653 SOC_COUNTER_NON_DMA_COSQ_DROP_PKT_UC - 1654 SOC_COUNTER_NON_DMA_START)); 1655 } 1656 non_dma0->num_entries = num_extra_ctr_entries; 1657 } 1658 1659 *non_dma_entries += non_dma0->num_entries; 1660 1661 non_dma1 = &soc->counter_non_dma[SOC_COUNTER_NON_DMA_COSQ_DROP_BYTE_UC - 1662 SOC_COUNTER_NON_DMA_START]; 1663 *non_dma1 = *non_dma0; 1664 non_dma1->id = SOC_COUNTER_NON_DMA_COSQ_DROP_BYTE_UC; 1665 non_dma1->flags = _SOC_COUNTER_NON_DMA_VALID | 1666 _SOC_COUNTER_NON_DMA_SUBSET_PARENT; 1667 non_dma1->base_index = non_dma_start_index + *non_dma_entries; 1668 non_dma1->field = BYTECNTf; 1669 non_dma1->cname = "PERQ_DROP_BYTE_UC"; 1670 non_dma1->extra_ctr_ct = NUM_XPE(unit); 1671 1672 /* Memory for extra ctrs for BYTE_CTRS are done along with PACKET_CTR */ 1673 non_dma1->extra_ctrs = non_dma0->extra_ctrs + 1; 1674 1675 if (non_dma0->extra_ctrs) 1676 { 1677 rv = soc_counter_trident3_extra_ctrs_init(unit, 1678 SOC_COUNTER_NON_DMA_COSQ_DROP_BYTE_UC, 1679 non_dma1, 1680 non_dma1->extra_ctrs, 1681 non_dma1->extra_ctr_ct, 1682 &num_extra_ctr_entries); 1683 if (rv != SOC_E_NONE) { 1684 LOG_CLI((BSL_META_U(unit, 1685 "ERR: Extra ctrs Init FAILED for id %d\n"), 1686 SOC_COUNTER_NON_DMA_COSQ_DROP_BYTE_UC - 1687 SOC_COUNTER_NON_DMA_START)); 1688 } 1689 } 1690 non_dma1->flags = _SOC_COUNTER_NON_DMA_SUBSET_PARENT; 1691 1692 *non_dma_entries += non_dma1->num_entries; 1693 /* End of DROP_PKT_UC Counters Control Block */ 1694 1695 /* DROP_PKT_ING Counters - Control Block */ 1696 non_dma0 = &soc->counter_non_dma[SOC_COUNTER_NON_DMA_PORT_DROP_PKT_ING - 1697 SOC_COUNTER_NON_DMA_START]; 1698 non_dma0->id = SOC_COUNTER_NON_DMA_PORT_DROP_PKT_ING; 1699 non_dma0->flags = _SOC_COUNTER_NON_DMA_VALID | 1700 _SOC_COUNTER_NON_DMA_DO_DMA | 1701 _SOC_COUNTER_NON_DMA_SUBSET_PARENT; 1702 non_dma0->pbmp = PBMP_ALL(unit); 1703 non_dma0->base_index = non_dma_start_index + *non_dma_entries; 1704 non_dma0->entries_per_port = 1; 1705 non_dma0->mem = MMU_CTR_ING_DROP_MEMm; 1706 1707 /* MMU memories with Unique access type have number of entries in base view 1708 * set to zero. So, get number of entries from first expanded view 1709 */ 1710 child_mem = SOC_MEM_UNIQUE_ACC_XPE_PIPE(unit, non_dma0->mem, 0, 0); 1711 num_entries = soc_mem_index_max(unit, child_mem) + 1; 1712 entry_words = soc_mem_entry_words(unit, non_dma0->mem); 1713 non_dma0->num_entries = NUM_PIPE(unit) * num_entries; 1714 non_dma0->reg = INVALIDr; 1715 non_dma0->field = PKTCNTf; 1716 non_dma0->cname = "DROP_PKT_ING"; 1717 1718 for (pipe = 0; pipe < NUM_PIPE(unit); pipe++) { 1719 non_dma0->dma_mem[pipe] = 1720 SOC_MEM_UNIQUE_ACC_XPE_PIPE(unit, non_dma0->mem, 0, pipe); 1721 non_dma0->dma_buf[pipe] = &buf[num_entries * entry_words * pipe]; 1722 non_dma0->dma_index_max[pipe] = 1723 soc_mem_index_max(unit, non_dma0->dma_mem[pipe]); 1724 } 1725 1726 non_dma0->extra_ctr_ct = NUM_XPE(unit); 1727 /* Incl. buffer for BYTE_CTR. 2x alloc size*/ 1728 alloc_size = (non_dma0->extra_ctr_ct << 1) * sizeof(soc_counter_non_dma_t); 1729 non_dma0->extra_ctrs = sal_alloc(alloc_size, "non_dma_ctrs_ing_drop"); 1730 1731 if (non_dma0->extra_ctrs == NULL) { 1732 non_dma0->extra_ctr_ct = 0; 1733 non_dma0->flags &= ~_SOC_COUNTER_NON_DMA_VALID; 1734 return SOC_E_MEMORY; 1735 } else { 1736 sal_memset(non_dma0->extra_ctrs, 0, alloc_size); 1737 rv = soc_counter_trident3_extra_ctrs_init(unit, 1738 SOC_COUNTER_NON_DMA_PORT_DROP_PKT_ING, 1739 non_dma0, 1740 non_dma0->extra_ctrs, 1741 non_dma0->extra_ctr_ct, 1742 &num_extra_ctr_entries); 1743 if (rv != SOC_E_NONE) { 1744 LOG_CLI((BSL_META_U(unit, 1745 "ERR: Extra ctrs Init FAILED for id %d\n"), 1746 SOC_COUNTER_NON_DMA_PORT_DROP_PKT_ING - 1747 SOC_COUNTER_NON_DMA_START)); 1748 } 1749 non_dma0->num_entries = num_extra_ctr_entries; 1750 } 1751 *non_dma_entries += non_dma0->num_entries; 1752 1753 non_dma1 = &soc->counter_non_dma[SOC_COUNTER_NON_DMA_PORT_DROP_BYTE_ING - 1754 SOC_COUNTER_NON_DMA_START]; 1755 *non_dma1 = *non_dma0; 1756 non_dma1->id = SOC_COUNTER_NON_DMA_PORT_DROP_BYTE_ING; 1757 non_dma1->flags = _SOC_COUNTER_NON_DMA_VALID | 1758 _SOC_COUNTER_NON_DMA_SUBSET_PARENT; 1759 non_dma1->base_index = non_dma_start_index + *non_dma_entries; 1760 non_dma1->field = BYTECNTf; 1761 non_dma1->cname = "DROP_BYTE_ING"; 1762 non_dma1->extra_ctr_ct = NUM_XPE(unit); 1763 1764 /* Memory for extra ctrs for BYTE_CTRS are done along with PACKET_CTR */ 1765 non_dma1->extra_ctrs = non_dma0->extra_ctrs + 1; 1766 1767 if (non_dma0->extra_ctrs) { 1768 rv = soc_counter_trident3_extra_ctrs_init(unit, 1769 SOC_COUNTER_NON_DMA_PORT_DROP_BYTE_ING, 1770 non_dma1, 1771 non_dma1->extra_ctrs, 1772 non_dma1->extra_ctr_ct, 1773 &num_extra_ctr_entries); 1774 if (rv != SOC_E_NONE) { 1775 LOG_CLI((BSL_META_U(unit, 1776 "ERR: Extra ctrs Init FAILED for id %d\n"), 1777 SOC_COUNTER_NON_DMA_PORT_DROP_BYTE_ING - 1778 SOC_COUNTER_NON_DMA_START)); 1779 } 1780 } 1781 non_dma1->flags = _SOC_COUNTER_NON_DMA_SUBSET_PARENT; 1782 1783 *non_dma_entries += non_dma1->num_entries; 1784 /* End of DROP_PKT_ING Counters - Control Block */ 1785 1786 /* Color Drop Counter */ 1787 /* Control block for wred counter */ 1788 non_dma0 = &soc->counter_non_dma[SOC_COUNTER_NON_DMA_PORT_WRED_PKT_RED - 1789 SOC_COUNTER_NON_DMA_START]; 1790 non_dma0->id = SOC_COUNTER_NON_DMA_PORT_WRED_PKT_RED; 1791 non_dma0->flags = _SOC_COUNTER_NON_DMA_VALID | 1792 _SOC_COUNTER_NON_DMA_DO_DMA | 1793 _SOC_COUNTER_NON_DMA_SUBSET_PARENT; 1794 non_dma0->pbmp = PBMP_ALL(unit); 1795 non_dma0->base_index = non_dma_start_index + *non_dma_entries; 1796 non_dma0->entries_per_port = 1; 1797 non_dma0->mem = MMU_CTR_COLOR_DROP_MEMm; 1798 non_dma0->reg = INVALIDr; 1799 non_dma0->cname = "WRED_PKT_RED"; 1800 non_dma0->field = PKTCNTf; 1801 num_entries = 66; /* 1 per port, 66 per pipe */ 1802 non_dma0->num_entries = NUM_PIPE(unit) * num_entries; 1803 entry_words = soc_mem_entry_words(unit, non_dma0->mem); 1804 1805 for (pipe = 0; pipe < NUM_PIPE(unit); pipe++) { 1806 non_dma0->dma_mem[pipe] = 1807 SOC_MEM_UNIQUE_ACC_XPE_PIPE(unit, non_dma0->mem, 0, pipe); 1808 non_dma0->dma_buf[pipe] = &buf[num_entries * entry_words * pipe]; 1809 non_dma0->dma_index_min[pipe] = 0; 1810 non_dma0->dma_index_max[pipe] = 65; 1811 } 1812 non_dma0->extra_ctr_ct = NUM_XPE(unit); 1813 /* Buffer allocated for 2x alloc size. Though 2nd half is NOT used. */ 1814 1815 alloc_size = (non_dma0->extra_ctr_ct << 1) * sizeof(soc_counter_non_dma_t); 1816 non_dma0->extra_ctrs = sal_alloc(alloc_size, "non_dma_ctrs_wred_pkt_red"); 1817 1818 /* 1819 * Below represents how Extra cntrs are arranged for wred red pkt, wred 1820 * yellow pkt, wred green pkt, drop pkt red, drop pkt yellow counters. 1821 * 1822 * n = NUM_XPE 1823 * 1824 * [0] [2] [2n-2] 1825 * ------ ------ ------ 1826 * | || |...| | 1827 * | PKT || PKT |...| PKT | 1828 * | [0] || [1] |...| [n-1]| 1829 * ------ ------ ... ------ 1830 * | || |...| | 1831 * | N/A || N/A |...| N/A | 1832 * | [0] || [1] |...| [n-1]| 1833 * ------ ------ ------ 1834 * [1] [3] [2n-1] 1835 */ 1836 1837 if (non_dma0->extra_ctrs == NULL) { 1838 non_dma0->extra_ctr_ct = 0; 1839 non_dma0->flags &= ~_SOC_COUNTER_NON_DMA_VALID; 1840 return SOC_E_MEMORY; 1841 } else { 1842 sal_memset(non_dma0->extra_ctrs, 0, alloc_size); 1843 rv = soc_counter_trident3_extra_ctrs_init(unit, 1844 SOC_COUNTER_NON_DMA_PORT_WRED_PKT_RED, 1845 non_dma0, 1846 non_dma0->extra_ctrs, 1847 non_dma0->extra_ctr_ct, 1848 &num_extra_ctr_entries); 1849 if (rv != SOC_E_NONE) { 1850 LOG_CLI((BSL_META_U(unit, 1851 "ERR: Extra ctrs Init FAILED for id %d\n"), 1852 SOC_COUNTER_NON_DMA_PORT_WRED_PKT_RED - 1853 SOC_COUNTER_NON_DMA_START)); 1854 } 1855 non_dma0->num_entries = num_extra_ctr_entries; 1856 } 1857 *non_dma_entries += non_dma0->num_entries; 1858 1859 /* Control block for wred yellow counter */ 1860 non_dma1 = &soc->counter_non_dma[SOC_COUNTER_NON_DMA_PORT_WRED_PKT_YELLOW - 1861 SOC_COUNTER_NON_DMA_START]; 1862 *non_dma1 = *non_dma0; 1863 non_dma1->id = SOC_COUNTER_NON_DMA_PORT_WRED_PKT_YELLOW; 1864 non_dma1->base_index = non_dma_start_index + *non_dma_entries; 1865 non_dma1->cname = "WRED_PKT_YEL"; 1866 1867 for (pipe = 0; pipe < NUM_PIPE(unit); pipe++) { 1868 non_dma1->dma_buf[pipe] = &buf[num_entries * entry_words * pipe]; 1869 non_dma1->dma_index_min[pipe] = 66; 1870 non_dma1->dma_index_max[pipe] = 131; 1871 } 1872 /* Buffer allocated for 2x alloc size. Though 2nd half is NOT used. */ 1873 non_dma1->extra_ctrs = sal_alloc(alloc_size, "non_dma_ctrs_wred_pkt_yel"); 1874 1875 if (non_dma1->extra_ctrs == NULL) { 1876 non_dma1->extra_ctr_ct = 0; 1877 non_dma1->flags &= ~_SOC_COUNTER_NON_DMA_VALID; 1878 return SOC_E_MEMORY; 1879 } else { 1880 sal_memset(non_dma1->extra_ctrs, 0, alloc_size); 1881 rv = soc_counter_trident3_extra_ctrs_init(unit, 1882 SOC_COUNTER_NON_DMA_PORT_WRED_PKT_YELLOW, 1883 non_dma1, 1884 non_dma1->extra_ctrs, 1885 non_dma1->extra_ctr_ct, 1886 &num_extra_ctr_entries); 1887 if (rv != SOC_E_NONE) { 1888 LOG_CLI((BSL_META_U(unit, 1889 "ERR: Extra ctrs Init FAILED for id %d\n"), 1890 SOC_COUNTER_NON_DMA_PORT_WRED_PKT_YELLOW - 1891 SOC_COUNTER_NON_DMA_START)); 1892 } 1893 non_dma1->num_entries = num_extra_ctr_entries; 1894 } 1895 *non_dma_entries += non_dma1->num_entries; 1896 1897 /* Control block for wred green counter */ 1898 non_dma1 = &soc->counter_non_dma[SOC_COUNTER_NON_DMA_PORT_WRED_PKT_GREEN - 1899 SOC_COUNTER_NON_DMA_START]; 1900 *non_dma1 = *non_dma0; 1901 non_dma1->id = SOC_COUNTER_NON_DMA_PORT_WRED_PKT_GREEN; 1902 non_dma1->base_index = non_dma_start_index + *non_dma_entries; 1903 non_dma1->cname = "WRED_PKT_GRE"; 1904 1905 for (pipe = 0; pipe < NUM_PIPE(unit); pipe++) { 1906 non_dma1->dma_buf[pipe] = &buf[num_entries * entry_words * pipe]; 1907 non_dma1->dma_index_min[pipe] = 132; 1908 non_dma1->dma_index_max[pipe] = 197; 1909 } 1910 non_dma1->extra_ctrs = sal_alloc(alloc_size, "non_dma_ctrs_wred_pkt_gre"); 1911 1912 if (non_dma1->extra_ctrs == NULL) { 1913 non_dma1->extra_ctr_ct = 0; 1914 non_dma1->flags &= ~_SOC_COUNTER_NON_DMA_VALID; 1915 return SOC_E_MEMORY; 1916 } else { 1917 sal_memset(non_dma1->extra_ctrs, 0, alloc_size); 1918 rv = soc_counter_trident3_extra_ctrs_init(unit, 1919 SOC_COUNTER_NON_DMA_PORT_WRED_PKT_GREEN, 1920 non_dma1, 1921 non_dma1->extra_ctrs, 1922 non_dma1->extra_ctr_ct, 1923 &num_extra_ctr_entries); 1924 if (rv != SOC_E_NONE) { 1925 LOG_CLI((BSL_META_U(unit, 1926 "ERR: Extra ctrs Init FAILED for id %d\n"), 1927 SOC_COUNTER_NON_DMA_PORT_WRED_PKT_GREEN - 1928 SOC_COUNTER_NON_DMA_START)); 1929 } 1930 non_dma1->num_entries = num_extra_ctr_entries; 1931 } 1932 *non_dma_entries += non_dma1->num_entries; 1933 1934 /* Control block for red drop counter */ 1935 non_dma1 = &soc->counter_non_dma[SOC_COUNTER_NON_DMA_PORT_DROP_PKT_RED - 1936 SOC_COUNTER_NON_DMA_START]; 1937 *non_dma1 = *non_dma0; 1938 non_dma1->id = SOC_COUNTER_NON_DMA_PORT_DROP_PKT_RED; 1939 non_dma1->base_index = non_dma_start_index + *non_dma_entries; 1940 non_dma1->cname = "DROP_PKT_RED"; 1941 1942 for (pipe = 0; pipe < NUM_PIPE(unit); pipe++) { 1943 non_dma1->dma_buf[pipe] = &buf[num_entries * entry_words * pipe]; 1944 non_dma1->dma_index_min[pipe] = 198; 1945 non_dma1->dma_index_max[pipe] = 263; 1946 } 1947 non_dma1->extra_ctrs = sal_alloc(alloc_size, "non_dma_ctrs_drop_pkt_red"); 1948 1949 if (non_dma1->extra_ctrs == NULL) { 1950 non_dma1->extra_ctr_ct = 0; 1951 non_dma1->flags &= ~_SOC_COUNTER_NON_DMA_VALID; 1952 return SOC_E_MEMORY; 1953 } else { 1954 sal_memset(non_dma1->extra_ctrs, 0, alloc_size); 1955 rv = soc_counter_trident3_extra_ctrs_init(unit, 1956 SOC_COUNTER_NON_DMA_PORT_DROP_PKT_RED, 1957 non_dma1, 1958 non_dma1->extra_ctrs, 1959 non_dma1->extra_ctr_ct, 1960 &num_extra_ctr_entries); 1961 if (rv != SOC_E_NONE) { 1962 LOG_CLI((BSL_META_U(unit, 1963 "ERR: Extra ctrs Init FAILED for id %d\n"), 1964 SOC_COUNTER_NON_DMA_PORT_DROP_PKT_RED - 1965 SOC_COUNTER_NON_DMA_START)); 1966 } 1967 non_dma1->num_entries = num_extra_ctr_entries; 1968 } 1969 1970 *non_dma_entries += non_dma1->num_entries; 1971 1972 /* Control block for yellow drop counter */ 1973 non_dma1 = &soc->counter_non_dma[SOC_COUNTER_NON_DMA_PORT_DROP_PKT_YELLOW - 1974 SOC_COUNTER_NON_DMA_START]; 1975 *non_dma1 = *non_dma0; 1976 non_dma1->id = SOC_COUNTER_NON_DMA_PORT_DROP_PKT_YELLOW; 1977 non_dma1->base_index = non_dma_start_index + *non_dma_entries; 1978 non_dma1->cname = "DROP_PKT_YEL"; 1979 1980 for (pipe = 0; pipe < NUM_PIPE(unit); pipe++) { 1981 non_dma1->dma_buf[pipe] = &buf[num_entries * entry_words * pipe]; 1982 non_dma1->dma_index_min[pipe] = 264; 1983 non_dma1->dma_index_max[pipe] = 329; 1984 } 1985 non_dma1->extra_ctrs = sal_alloc(alloc_size, "non_dma_ctrs_drop_pkt_yel"); 1986 1987 if (non_dma1->extra_ctrs == NULL) { 1988 non_dma1->extra_ctr_ct = 0; 1989 non_dma1->flags &= ~_SOC_COUNTER_NON_DMA_VALID; 1990 return SOC_E_MEMORY; 1991 } else { 1992 sal_memset(non_dma1->extra_ctrs, 0, alloc_size); 1993 rv = soc_counter_trident3_extra_ctrs_init(unit, 1994 SOC_COUNTER_NON_DMA_PORT_DROP_PKT_YELLOW, 1995 non_dma1, 1996 non_dma1->extra_ctrs, 1997 non_dma1->extra_ctr_ct, 1998 &num_extra_ctr_entries); 1999 if (rv != SOC_E_NONE) { 2000 LOG_CLI((BSL_META_U(unit, 2001 "ERR: Extra ctrs Init FAILED for id %d\n"), 2002 SOC_COUNTER_NON_DMA_PORT_DROP_PKT_YELLOW - 2003 SOC_COUNTER_NON_DMA_START)); 2004 } 2005 non_dma1->num_entries = num_extra_ctr_entries; 2006 } 2007 *non_dma_entries += non_dma1->num_entries; 2008 2009 /* End Color Drop Counter */ 2010 2011 /* MC Queue Count Counters - Control Block */ 2012 non_dma0 = &soc->counter_non_dma[SOC_COUNTER_NON_DMA_QUEUE_PEAK - 2013 SOC_COUNTER_NON_DMA_START]; 2014 non_dma0->id = SOC_COUNTER_NON_DMA_QUEUE_PEAK; 2015 2016 non_dma0->flags = _SOC_COUNTER_NON_DMA_VALID | 2017 _SOC_COUNTER_NON_DMA_DO_DMA | 2018 _SOC_COUNTER_NON_DMA_PEAK | 2019 _SOC_COUNTER_NON_DMA_SUBSET_PARENT; 2020 non_dma0->pbmp = PBMP_ALL(unit); 2021 non_dma0->base_index = non_dma_start_index + *non_dma_entries; 2022 non_dma0->entries_per_port = 48; /* 48 for cpu port */ 2023 non_dma0->mem = MMU_THDM_DB_QUEUE_COUNTm; 2024 2025 /* MMU memories with Unique access type have number of entries in base view 2026 * set to zero. So, get number of entries from first expanded view 2027 */ 2028 child_mem = SOC_MEM_UNIQUE_ACC_XPE_PIPE(unit, non_dma0->mem, 0, 0); 2029 num_entries = soc_mem_index_max(unit, child_mem) + 1; 2030 entry_words = soc_mem_entry_words(unit, non_dma0->mem); 2031 non_dma0->num_entries = NUM_PIPE(unit) * num_entries; 2032 non_dma0->reg = INVALIDr; 2033 non_dma0->field = SHARED_COUNTf; 2034 non_dma0->cname = "QUEUE_PEAK"; 2035 for (pipe = 0; pipe < NUM_PIPE(unit); pipe++) { 2036 non_dma0->dma_mem[pipe] = 2037 SOC_MEM_UNIQUE_ACC_XPE_PIPE(unit, non_dma0->mem, 0, pipe); 2038 non_dma0->dma_buf[pipe] = &buf[num_entries * entry_words * pipe]; 2039 non_dma0->dma_index_max[pipe] = 2040 soc_mem_index_max(unit, non_dma0->dma_mem[pipe]); 2041 } 2042 2043 non_dma0->extra_ctr_ct = NUM_XPE(unit); 2044 alloc_size = (non_dma0->extra_ctr_ct << 1) * sizeof(soc_counter_non_dma_t); 2045 non_dma0->extra_ctrs = sal_alloc(alloc_size, "non_dma_ctrs_mc_q_ct"); 2046 2047 if (non_dma0->extra_ctrs == NULL) { 2048 non_dma0->extra_ctr_ct = 0; 2049 non_dma0->flags &= ~_SOC_COUNTER_NON_DMA_VALID; 2050 return SOC_E_MEMORY; 2051 } else { 2052 sal_memset(non_dma0->extra_ctrs, 0, alloc_size); 2053 rv = soc_counter_trident3_extra_ctrs_init(unit, 2054 SOC_COUNTER_NON_DMA_QUEUE_PEAK, 2055 non_dma0, 2056 non_dma0->extra_ctrs, 2057 non_dma0->extra_ctr_ct, 2058 &num_extra_ctr_entries); 2059 if (rv != SOC_E_NONE) { 2060 LOG_CLI((BSL_META_U(unit, 2061 "ERR: Extra ctrs Init FAILED for id %d\n"), 2062 SOC_COUNTER_NON_DMA_QUEUE_PEAK - 2063 SOC_COUNTER_NON_DMA_START)); 2064 } 2065 non_dma0->num_entries = num_extra_ctr_entries; 2066 } 2067 2068 *non_dma_entries += non_dma0->num_entries; 2069 non_dma2 = &soc->counter_non_dma[SOC_COUNTER_NON_DMA_QUEUE_CURRENT - 2070 SOC_COUNTER_NON_DMA_START]; 2071 *non_dma2 = *non_dma0; 2072 non_dma2->id = SOC_COUNTER_NON_DMA_QUEUE_CURRENT; 2073 non_dma2->flags = _SOC_COUNTER_NON_DMA_VALID | 2074 _SOC_COUNTER_NON_DMA_CURRENT | 2075 _SOC_COUNTER_NON_DMA_SUBSET_PARENT; 2076 non_dma2->cname = "QUEUE_CUR"; 2077 /* End of MC Queue Count Counters - Control Block */ 2078 2079 /* UC Queue Count Counters - Control Block */ 2080 non_dma0 = &soc->counter_non_dma[SOC_COUNTER_NON_DMA_UC_QUEUE_PEAK - 2081 SOC_COUNTER_NON_DMA_START]; 2082 non_dma0->id = SOC_COUNTER_NON_DMA_UC_QUEUE_PEAK; 2083 2084 non_dma0->flags = _SOC_COUNTER_NON_DMA_VALID | 2085 _SOC_COUNTER_NON_DMA_DO_DMA | 2086 _SOC_COUNTER_NON_DMA_PEAK | 2087 _SOC_COUNTER_NON_DMA_SUBSET_PARENT; 2088 non_dma0->pbmp = PBMP_PORT_ALL(unit); /* No UC queue for CPU/LB ports */ 2089 non_dma0->base_index = non_dma_start_index + *non_dma_entries; 2090 non_dma0->entries_per_port = 10; 2091 non_dma0->mem = MMU_THDU_COUNTER_QUEUEm; 2092 2093 /* MMU memories with Unique access type have number of entries in base view 2094 * set to zero. So, get number of entries from first expanded view 2095 */ 2096 child_mem = SOC_MEM_UNIQUE_ACC_XPE_PIPE(unit, non_dma0->mem, 0, 0); 2097 num_entries = soc_mem_index_max(unit, child_mem) + 1; 2098 entry_words = soc_mem_entry_words(unit, non_dma0->mem); 2099 non_dma0->num_entries = NUM_PIPE(unit) * num_entries; 2100 non_dma0->reg = INVALIDr; 2101 non_dma0->field = SHARED_COUNTf; 2102 non_dma0->cname = "UC_QUEUE_PEAK"; 2103 for (pipe = 0; pipe < NUM_PIPE(unit); pipe++) { 2104 non_dma0->dma_mem[pipe] = 2105 SOC_MEM_UNIQUE_ACC_XPE_PIPE(unit, non_dma0->mem, 0, pipe); 2106 non_dma0->dma_buf[pipe] = &buf[num_entries * entry_words * pipe]; 2107 non_dma0->dma_index_max[pipe] = 2108 soc_mem_index_max(unit, non_dma0->dma_mem[pipe]); 2109 } 2110 2111 non_dma0->extra_ctr_ct = NUM_XPE(unit); 2112 alloc_size = (non_dma0->extra_ctr_ct << 1) * sizeof(soc_counter_non_dma_t); 2113 non_dma0->extra_ctrs = sal_alloc(alloc_size, "non_dma_ctrs_uc_q_ct"); 2114 2115 if (non_dma0->extra_ctrs == NULL) { 2116 non_dma0->extra_ctr_ct = 0; 2117 non_dma0->flags &= ~_SOC_COUNTER_NON_DMA_VALID; 2118 return SOC_E_MEMORY; 2119 } else { 2120 sal_memset(non_dma0->extra_ctrs, 0, alloc_size); 2121 rv = soc_counter_trident3_extra_ctrs_init(unit, 2122 SOC_COUNTER_NON_DMA_UC_QUEUE_PEAK, 2123 non_dma0, 2124 non_dma0->extra_ctrs, 2125 non_dma0->extra_ctr_ct, 2126 &num_extra_ctr_entries); 2127 if (rv != SOC_E_NONE) { 2128 LOG_CLI((BSL_META_U(unit, 2129 "ERR: Extra ctrs Init FAILED for id %d\n"), 2130 SOC_COUNTER_NON_DMA_UC_QUEUE_PEAK - 2131 SOC_COUNTER_NON_DMA_START)); 2132 } 2133 non_dma0->num_entries = num_extra_ctr_entries; 2134 } 2135 2136 *non_dma_entries += non_dma0->num_entries; 2137 non_dma2 = &soc->counter_non_dma[SOC_COUNTER_NON_DMA_UC_QUEUE_CURRENT - 2138 SOC_COUNTER_NON_DMA_START]; 2139 *non_dma2 = *non_dma0; 2140 non_dma2->id = SOC_COUNTER_NON_DMA_UC_QUEUE_CURRENT; 2141 non_dma2->flags = _SOC_COUNTER_NON_DMA_VALID | 2142 _SOC_COUNTER_NON_DMA_CURRENT | 2143 _SOC_COUNTER_NON_DMA_SUBSET_PARENT; 2144 non_dma2->cname = "UC_QUEUE_CUR"; 2145 /* End of UC Queue Count Counters - Control Block */ 2146 2147 /* RQ Drop Counters - Control Block */ 2148 non_dma0 = &soc->counter_non_dma[SOC_COUNTER_NON_DMA_DROP_RQ_PKT - 2149 SOC_COUNTER_NON_DMA_START]; 2150 non_dma0->flags = _SOC_COUNTER_NON_DMA_VALID | 2151 _SOC_COUNTER_NON_DMA_DO_DMA; 2152 non_dma0->id = SOC_COUNTER_NON_DMA_DROP_RQ_PKT; 2153 SOC_PBMP_CLEAR(non_dma0->pbmp); /* Port = 0 */ 2154 non_dma0->base_index = non_dma_start_index + *non_dma_entries; 2155 non_dma0->entries_per_port = 0; 2156 non_dma0->num_entries = 11; 2157 non_dma0->mem = INVALIDm; 2158 non_dma0->reg = DROP_PKT_CNT_RQE_PKT_64r; 2159 non_dma0->field = PKTCNTf; 2160 non_dma0->cname = "RQ_DROP_PKT"; 2161 non_dma0->dma_buf[0] = buf; 2162 *non_dma_entries += non_dma0->num_entries; 2163 2164 non_dma1 = &soc->counter_non_dma[SOC_COUNTER_NON_DMA_DROP_RQ_BYTE - 2165 SOC_COUNTER_NON_DMA_START]; 2166 *non_dma1 = *non_dma0; 2167 non_dma1->id = SOC_COUNTER_NON_DMA_DROP_RQ_BYTE; 2168 non_dma1->base_index = non_dma_start_index + *non_dma_entries; 2169 non_dma1->reg = DROP_PKT_CNT_RQE_BYTE_64r; 2170 non_dma1->field = BYTECNTf; 2171 non_dma1->cname = "RQ_DROP_BYTE"; 2172 *non_dma_entries += non_dma1->num_entries; 2173 2174 non_dma1 = &soc->counter_non_dma[SOC_COUNTER_NON_DMA_DROP_RQ_PKT_YELLOW - 2175 SOC_COUNTER_NON_DMA_START]; 2176 *non_dma1 = *non_dma0; 2177 non_dma1->id = SOC_COUNTER_NON_DMA_DROP_RQ_PKT_YELLOW; 2178 non_dma1->base_index = non_dma_start_index + *non_dma_entries; 2179 non_dma1->reg = DROP_PKT_CNT_RQE_YEL_64r; 2180 non_dma1->field = PKTCNTf; 2181 non_dma1->cname = "RQ_DROP_PKT_YEL"; 2182 *non_dma_entries += non_dma1->num_entries; 2183 2184 non_dma1 = &soc->counter_non_dma[SOC_COUNTER_NON_DMA_DROP_RQ_PKT_RED - 2185 SOC_COUNTER_NON_DMA_START]; 2186 *non_dma1 = *non_dma0; 2187 non_dma1->id = SOC_COUNTER_NON_DMA_DROP_RQ_PKT_RED; 2188 non_dma1->base_index = non_dma_start_index + *non_dma_entries; 2189 non_dma1->reg = DROP_PKT_CNT_RQE_RED_64r; 2190 non_dma1->field = PKTCNTf; 2191 non_dma1->cname = "RQ_DROP_PKT_RED"; 2192 *non_dma_entries += non_dma1->num_entries; 2193 /* End of RQ Drop Counters - Control Block */ 2194 2195 /* Pool Peak Counters - Control Block */ 2196 non_dma0 = &soc->counter_non_dma[SOC_COUNTER_NON_DMA_POOL_PEAK - 2197 SOC_COUNTER_NON_DMA_START]; 2198 non_dma0->flags = _SOC_COUNTER_NON_DMA_VALID | 2199 _SOC_COUNTER_NON_DMA_PEAK; 2200 non_dma0->id = SOC_COUNTER_NON_DMA_POOL_PEAK; 2201 SOC_PBMP_CLEAR(non_dma0->pbmp); /* Port = 0 */ 2202 non_dma0->base_index = non_dma_start_index + *non_dma_entries; 2203 non_dma0->entries_per_port = 0; 2204 non_dma0->num_entries = 4; 2205 non_dma0->mem = INVALIDm; 2206 non_dma0->reg = THDI_POOL_SHARED_COUNT_SPr; 2207 non_dma0->field = TOTAL_BUFFER_COUNTf; 2208 non_dma0->cname = "POOL_PEAK"; 2209 non_dma0->dma_buf[0] = buf; 2210 *non_dma_entries += non_dma0->num_entries; 2211 2212 non_dma2 = &soc->counter_non_dma[SOC_COUNTER_NON_DMA_POOL_CURRENT - 2213 SOC_COUNTER_NON_DMA_START]; 2214 *non_dma2 = *non_dma0; 2215 non_dma2->id = SOC_COUNTER_NON_DMA_POOL_CURRENT; 2216 non_dma2->flags = _SOC_COUNTER_NON_DMA_VALID | 2217 _SOC_COUNTER_NON_DMA_CURRENT; 2218 non_dma2->cname = "POOL_CUR"; 2219 /* End of Pool Peak Counters - Control Block */ 2220 2221 /* PG Counters - Control Block */ 2222 non_dma0 = &soc->counter_non_dma[SOC_COUNTER_NON_DMA_PG_MIN_PEAK - 2223 SOC_COUNTER_NON_DMA_START]; 2224 non_dma0->id = SOC_COUNTER_NON_DMA_PG_MIN_PEAK; 2225 non_dma0->flags = _SOC_COUNTER_NON_DMA_VALID | 2226 _SOC_COUNTER_NON_DMA_DO_DMA | 2227 _SOC_COUNTER_NON_DMA_PEAK; 2228 non_dma0->pbmp = PBMP_ALL(unit); 2229 non_dma0->base_index = non_dma_start_index + *non_dma_entries; 2230 non_dma0->entries_per_port = 8; 2231 non_dma0->mem = THDI_PORT_PG_CNTRS_RT1m; 2232 2233 /* MMU memories with Unique access type have number of entries in base view 2234 * set to zero. So, get number of entries from first expanded view 2235 */ 2236 child_mem = SOC_MEM_UNIQUE_ACC_XPE_PIPE(unit, non_dma0->mem, 0, 0); 2237 num_entries = soc_mem_index_max(unit, child_mem) + 1; 2238 entry_words = soc_mem_entry_words(unit, non_dma0->mem); 2239 non_dma0->num_entries = NUM_PIPE(unit) * num_entries; 2240 non_dma0->reg = INVALIDr; 2241 non_dma0->field = PG_MIN_COUNTf; 2242 non_dma0->cname = "PG_MIN_PEAK"; 2243 2244 for (pipe = 0; pipe < NUM_PIPE(unit); pipe++) { 2245 non_dma0->dma_mem[pipe] = 2246 SOC_MEM_UNIQUE_ACC_XPE_PIPE(unit, non_dma0->mem, 0, pipe); 2247 non_dma0->dma_buf[pipe] = &buf[num_entries * entry_words * pipe]; 2248 non_dma0->dma_index_max[pipe] = 2249 soc_mem_index_max(unit, non_dma0->dma_mem[pipe]); 2250 } 2251 *non_dma_entries += non_dma0->num_entries; 2252 non_dma2 = &soc->counter_non_dma[SOC_COUNTER_NON_DMA_PG_MIN_CURRENT - 2253 SOC_COUNTER_NON_DMA_START]; 2254 *non_dma2 = *non_dma0; 2255 non_dma2->id = SOC_COUNTER_NON_DMA_PG_MIN_CURRENT; 2256 non_dma2->flags = _SOC_COUNTER_NON_DMA_VALID | 2257 _SOC_COUNTER_NON_DMA_CURRENT; 2258 non_dma2->cname = "PG_MIN_CUR"; 2259 2260 non_dma1 = &soc->counter_non_dma[SOC_COUNTER_NON_DMA_PG_SHARED_PEAK - 2261 SOC_COUNTER_NON_DMA_START]; 2262 *non_dma1 = *non_dma0; 2263 non_dma1->id = SOC_COUNTER_NON_DMA_PG_SHARED_PEAK; 2264 non_dma1->flags = _SOC_COUNTER_NON_DMA_VALID | 2265 _SOC_COUNTER_NON_DMA_PEAK; 2266 non_dma1->cname = "PG_SHARED_PEAK"; 2267 non_dma1->field = PG_SHARED_COUNTf; 2268 non_dma1->base_index = non_dma_start_index + *non_dma_entries; 2269 *non_dma_entries += non_dma1->num_entries; 2270 2271 non_dma2 = &soc->counter_non_dma[SOC_COUNTER_NON_DMA_PG_SHARED_CURRENT - 2272 SOC_COUNTER_NON_DMA_START]; 2273 *non_dma2 = *non_dma1; 2274 non_dma2->id = SOC_COUNTER_NON_DMA_PG_SHARED_CURRENT; 2275 non_dma2->flags = _SOC_COUNTER_NON_DMA_CURRENT | 2276 _SOC_COUNTER_NON_DMA_VALID; 2277 non_dma2->cname = "PG_SHARED_CUR"; 2278 2279 non_dma0 = &soc->counter_non_dma[SOC_COUNTER_NON_DMA_PG_HDRM_PEAK - 2280 SOC_COUNTER_NON_DMA_START]; 2281 non_dma0->id = SOC_COUNTER_NON_DMA_PG_HDRM_PEAK; 2282 non_dma0->flags = _SOC_COUNTER_NON_DMA_VALID | 2283 _SOC_COUNTER_NON_DMA_DO_DMA | 2284 _SOC_COUNTER_NON_DMA_PEAK; 2285 non_dma0->pbmp = PBMP_ALL(unit); 2286 non_dma0->base_index = non_dma_start_index + *non_dma_entries; 2287 non_dma0->entries_per_port = 8; 2288 non_dma0->mem = THDI_PORT_PG_CNTRS_RT2m; 2289 2290 /* MMU memories with Unique access type have number of entries in base view 2291 * set to zero. So, get number of entries from first expanded view 2292 */ 2293 child_mem = SOC_MEM_UNIQUE_ACC_XPE_PIPE(unit, non_dma0->mem, 0, 0); 2294 num_entries = soc_mem_index_max(unit, child_mem) + 1; 2295 entry_words = soc_mem_entry_words(unit, non_dma0->mem); 2296 non_dma0->num_entries = NUM_PIPE(unit) * num_entries; 2297 non_dma0->reg = INVALIDr; 2298 non_dma0->field = PG_HDRM_COUNTf; 2299 non_dma0->cname = "PG_HDRM_PEAK"; 2300 2301 for (pipe = 0; pipe < NUM_PIPE(unit); pipe++) { 2302 non_dma0->dma_mem[pipe] = 2303 SOC_MEM_UNIQUE_ACC_XPE_PIPE(unit, non_dma0->mem, 0, pipe); 2304 non_dma0->dma_buf[pipe] = &buf[num_entries * entry_words * pipe]; 2305 non_dma0->dma_index_max[pipe] = 2306 soc_mem_index_max(unit, non_dma0->dma_mem[pipe]); 2307 } 2308 *non_dma_entries += non_dma0->num_entries; 2309 2310 non_dma2 = &soc->counter_non_dma[SOC_COUNTER_NON_DMA_PG_HDRM_CURRENT - 2311 SOC_COUNTER_NON_DMA_START]; 2312 *non_dma2 = *non_dma0; 2313 non_dma2->id = SOC_COUNTER_NON_DMA_PG_HDRM_CURRENT; 2314 non_dma2->flags = _SOC_COUNTER_NON_DMA_VALID | 2315 _SOC_COUNTER_NON_DMA_CURRENT; 2316 non_dma2->cname = "PG_HDRM_CUR"; 2317 /* End of PG Counters - Control Block */ 2318 2319 /* ING_FLEX counters - Control Block 2320 * Eviction enabled counters 2321 */ 2322 non_dma0 = &soc->counter_non_dma[SOC_COUNTER_NON_DMA_ING_FLEX_PKT - 2323 SOC_COUNTER_NON_DMA_START]; 2324 non_dma0->id = SOC_COUNTER_NON_DMA_ING_FLEX_PKT; 2325 non_dma0->flags = _SOC_COUNTER_NON_DMA_VALID | 2326 _SOC_COUNTER_NON_DMA_DO_DMA | 2327 _SOC_COUNTER_NON_DMA_SUBSET_PARENT; 2328 2329 /* Clear on Read Flag set if eviction is enabled */ 2330 non_dma0->flags |= _SOC_COUNTER_NON_DMA_CTR_EVICT; 2331 non_dma0->flags |= _SOC_COUNTER_NON_DMA_NO_SHOW_C; 2332 SOC_PBMP_CLEAR(non_dma0->pbmp); 2333 non_dma0->base_index = non_dma_start_index + *non_dma_entries; 2334 non_dma0->entries_per_port = 0; 2335 pool_count = 20; 2336 non_dma0->num_entries = 2337 pool_count * NUM_PIPE(unit) * 2338 soc_mem_index_count(unit, ING_FLEX_CTR_COUNTER_TABLE_0m); 2339 non_dma0->mem = ING_FLEX_CTR_COUNTER_TABLE_0m; 2340 non_dma0->reg = INVALIDr; 2341 non_dma0->field = PACKET_COUNTERf; 2342 non_dma0->cname = "ING_FLEX_PKT"; 2343 2344 num_entries = soc_mem_index_count(unit, ING_FLEX_CTR_COUNTER_TABLE_0m); 2345 entry_words = soc_mem_entry_words(unit, ING_FLEX_CTR_COUNTER_TABLE_0m); 2346 for (pipe = 0; pipe < NUM_PIPE(unit); pipe++) { 2347 non_dma0->dma_buf[pipe] = &buf[num_entries * entry_words * pipe]; 2348 } 2349 non_dma0->extra_ctr_ct = pool_count; 2350 /* Incl. buffer for BYTE_CTR. 2x alloc size*/ 2351 alloc_size = (non_dma0->extra_ctr_ct << 1) * sizeof(soc_counter_non_dma_t); 2352 non_dma0->extra_ctrs = sal_alloc(alloc_size, "non_dma_ctrs_ing_flex"); 2353 2354 if (non_dma0->extra_ctrs == NULL) { 2355 non_dma0->extra_ctr_ct = 0; 2356 non_dma0->flags &= ~_SOC_COUNTER_NON_DMA_VALID; 2357 return SOC_E_MEMORY; 2358 } else { 2359 sal_memset(non_dma0->extra_ctrs, 0, alloc_size); 2360 rv = soc_counter_trident3_extra_ctrs_init 2361 (unit, 2362 SOC_COUNTER_NON_DMA_ING_FLEX_PKT, 2363 non_dma0, 2364 non_dma0->extra_ctrs, 2365 non_dma0->extra_ctr_ct, 2366 &num_extra_ctr_entries); 2367 if (rv != SOC_E_NONE) { 2368 LOG_CLI((BSL_META_U(unit, 2369 "ERR: Extra ctrs Init FAILED for id %d\n"), 2370 SOC_COUNTER_NON_DMA_ING_FLEX_PKT - 2371 SOC_COUNTER_NON_DMA_START)); 2372 } 2373 non_dma0->num_entries = num_extra_ctr_entries; 2374 } 2375 *non_dma_entries += non_dma0->num_entries; 2376 2377 non_dma1 = &soc->counter_non_dma[SOC_COUNTER_NON_DMA_ING_FLEX_BYTE - 2378 SOC_COUNTER_NON_DMA_START]; 2379 *non_dma1 = *non_dma0; 2380 non_dma1->id = SOC_COUNTER_NON_DMA_ING_FLEX_BYTE; 2381 2382 non_dma1->flags = _SOC_COUNTER_NON_DMA_VALID | 2383 _SOC_COUNTER_NON_DMA_SUBSET_PARENT; 2384 2385 /* Clear on Read Flag set if eviction is enabled */ 2386 non_dma1->flags |= _SOC_COUNTER_NON_DMA_CTR_EVICT; 2387 non_dma1->flags |= _SOC_COUNTER_NON_DMA_NO_SHOW_C; 2388 non_dma1->base_index = non_dma_start_index + *non_dma_entries; 2389 non_dma1->field = BYTE_COUNTERf; 2390 non_dma1->cname = "ING_FLEX_BYTE"; 2391 non_dma1->extra_ctr_ct = pool_count; /* Taken care by PKT_CTR */ 2392 2393 /* Memory for extra ctrs for BYTE_CTRS are done along with PACKET_CTR */ 2394 non_dma1->extra_ctrs = non_dma0->extra_ctrs + 1; 2395 2396 if (non_dma0->extra_ctrs) 2397 { 2398 rv = soc_counter_trident3_extra_ctrs_init(unit, 2399 SOC_COUNTER_NON_DMA_ING_FLEX_BYTE, 2400 non_dma1, 2401 non_dma1->extra_ctrs, 2402 non_dma1->extra_ctr_ct, 2403 &num_extra_ctr_entries); 2404 if (rv != SOC_E_NONE) { 2405 LOG_CLI((BSL_META_U(unit, 2406 "ERR: Extra ctrs Init FAILED for id %d\n"), 2407 SOC_COUNTER_NON_DMA_ING_FLEX_BYTE - 2408 SOC_COUNTER_NON_DMA_START)); 2409 } 2410 } 2411 2412 non_dma1->flags = _SOC_COUNTER_NON_DMA_SUBSET_PARENT; 2413 non_dma1->flags |= _SOC_COUNTER_NON_DMA_NO_SHOW_C; 2414 *non_dma_entries += non_dma1->num_entries; 2415 2416 /* End of ING_FLEX counters - Control Block */ 2417 2418 /* EGR_FLEX Counters - Control Block */ 2419 non_dma0 = &soc->counter_non_dma[SOC_COUNTER_NON_DMA_EGR_FLEX_PKT - 2420 SOC_COUNTER_NON_DMA_START]; 2421 non_dma0->id = SOC_COUNTER_NON_DMA_EGR_FLEX_PKT; 2422 non_dma0->flags = _SOC_COUNTER_NON_DMA_VALID | 2423 _SOC_COUNTER_NON_DMA_DO_DMA | 2424 _SOC_COUNTER_NON_DMA_SUBSET_PARENT; 2425 2426 /* Clear on Read Flag set if eviction is enabled */ 2427 non_dma0->flags |= _SOC_COUNTER_NON_DMA_CTR_EVICT; 2428 non_dma0->flags |= _SOC_COUNTER_NON_DMA_NO_SHOW_C; 2429 SOC_PBMP_CLEAR(non_dma0->pbmp); 2430 non_dma0->base_index = non_dma_start_index + *non_dma_entries; 2431 pool_count = 4; 2432 non_dma0->entries_per_port = 0; 2433 non_dma0->mem = EGR_FLEX_CTR_COUNTER_TABLE_0m; 2434 non_dma0->reg = INVALIDr; 2435 non_dma0->field = PACKET_COUNTERf; 2436 non_dma0->cname = "EGR_FLEX_PKT"; 2437 2438 num_entries = soc_mem_index_count(unit, EGR_FLEX_CTR_COUNTER_TABLE_0m); 2439 entry_words = soc_mem_entry_words(unit, EGR_FLEX_CTR_COUNTER_TABLE_0m); 2440 for (pipe = 0; pipe < NUM_PIPE(unit); pipe++) { 2441 non_dma0->dma_buf[pipe] = &buf[num_entries * entry_words * pipe]; 2442 } 2443 2444 non_dma0->extra_ctr_ct = pool_count; 2445 2446 /* Incl. buffer for BYTE_CTR. 2x alloc size*/ 2447 alloc_size = (non_dma0->extra_ctr_ct << 1) * sizeof(soc_counter_non_dma_t); 2448 non_dma0->extra_ctrs = sal_alloc(alloc_size, "non_dma_ctrs_ing_flex"); 2449 2450 if (non_dma0->extra_ctrs == NULL) { 2451 non_dma0->extra_ctr_ct = 0; 2452 non_dma0->flags &= ~_SOC_COUNTER_NON_DMA_VALID; 2453 return SOC_E_MEMORY; 2454 } else { 2455 sal_memset(non_dma0->extra_ctrs, 0, alloc_size); 2456 rv = soc_counter_trident3_extra_ctrs_init(unit, 2457 SOC_COUNTER_NON_DMA_EGR_FLEX_PKT, 2458 non_dma0, 2459 non_dma0->extra_ctrs, 2460 non_dma0->extra_ctr_ct, 2461 &num_extra_ctr_entries); 2462 if (rv != SOC_E_NONE) { 2463 LOG_CLI((BSL_META_U(unit, 2464 "ERR: Extra ctrs Init FAILED for id %d\n"), 2465 SOC_COUNTER_NON_DMA_EGR_FLEX_PKT - 2466 SOC_COUNTER_NON_DMA_START)); 2467 } 2468 non_dma0->num_entries = num_extra_ctr_entries; 2469 } 2470 2471 *non_dma_entries += non_dma0->num_entries; 2472 2473 non_dma1 = &soc->counter_non_dma[SOC_COUNTER_NON_DMA_EGR_FLEX_BYTE - 2474 SOC_COUNTER_NON_DMA_START]; 2475 *non_dma1 = *non_dma0; 2476 non_dma1->id = SOC_COUNTER_NON_DMA_EGR_FLEX_BYTE; 2477 2478 non_dma1->flags = _SOC_COUNTER_NON_DMA_VALID | 2479 _SOC_COUNTER_NON_DMA_SUBSET_PARENT; 2480 /* Clear on Read Flag set if eviction is enabled */ 2481 non_dma1->flags |= _SOC_COUNTER_NON_DMA_CTR_EVICT; 2482 non_dma1->flags |= _SOC_COUNTER_NON_DMA_NO_SHOW_C; 2483 non_dma1->base_index = non_dma_start_index + *non_dma_entries; 2484 non_dma1->field = BYTE_COUNTERf; 2485 non_dma1->cname = "EGR_FLEX_BYTE"; 2486 non_dma1->extra_ctr_ct = pool_count; /* Taken care by PKT_CTR */ 2487 2488 /* Memory for extra ctrs for BYTE_CTRS are done along with PACKET_CTR */ 2489 non_dma1->extra_ctrs = non_dma0->extra_ctrs + 1; 2490 2491 if (non_dma0->extra_ctrs) 2492 { 2493 rv = soc_counter_trident3_extra_ctrs_init(unit, 2494 SOC_COUNTER_NON_DMA_EGR_FLEX_BYTE, 2495 non_dma1, 2496 non_dma1->extra_ctrs, 2497 non_dma1->extra_ctr_ct, 2498 &num_extra_ctr_entries); 2499 if (rv != SOC_E_NONE) { 2500 LOG_CLI((BSL_META_U(unit, 2501 "ERR: Extra ctrs Init FAILED for id %d\n"), 2502 SOC_COUNTER_NON_DMA_EGR_FLEX_BYTE - 2503 SOC_COUNTER_NON_DMA_START)); 2504 } 2505 } 2506 non_dma1->flags = _SOC_COUNTER_NON_DMA_SUBSET_PARENT; 2507 non_dma1->flags |= _SOC_COUNTER_NON_DMA_NO_SHOW_C; 2508 2509 *non_dma_entries += non_dma1->num_entries; 2510 2511 /* End of EGR_FLEX Counters - Control Block */ 2512 2513 /* EFP Counters - Control Block */ 2514 non_dma0 = &soc->counter_non_dma[SOC_COUNTER_NON_DMA_EFP_PKT - 2515 SOC_COUNTER_NON_DMA_START]; 2516 non_dma0->id = SOC_COUNTER_NON_DMA_EFP_PKT; 2517 non_dma0->flags = _SOC_COUNTER_NON_DMA_VALID | 2518 _SOC_COUNTER_NON_DMA_DO_DMA; 2519 non_dma0->flags |= _SOC_COUNTER_NON_DMA_CTR_EVICT; 2520 non_dma0->flags |= _SOC_COUNTER_NON_DMA_NO_SHOW_C; 2521 2522 SOC_PBMP_CLEAR(non_dma0->pbmp); 2523 non_dma0->base_index = non_dma_start_index + *non_dma_entries; 2524 non_dma0->entries_per_port = 0; 2525 non_dma0->num_entries = 2526 NUM_PIPE(unit) * soc_mem_index_count(unit, EFP_COUNTER_TABLEm); 2527 non_dma0->mem = EFP_COUNTER_TABLEm; 2528 non_dma0->reg = INVALIDr; 2529 non_dma0->field = PACKET_COUNTERf; 2530 non_dma0->cname = "EFP_PKT"; 2531 2532 num_entries = soc_mem_index_count(unit, EFP_COUNTER_TABLEm); 2533 entry_words = soc_mem_entry_words(unit, EFP_COUNTER_TABLEm); 2534 2535 for (pipe = 0; pipe < NUM_PIPE(unit); pipe++) { 2536 non_dma0->dma_mem[pipe] = 2537 SOC_MEM_UNIQUE_ACC(unit, non_dma0->mem)[pipe]; 2538 non_dma0->dma_buf[pipe] = &buf[num_entries * entry_words * pipe]; 2539 non_dma0->dma_index_max[pipe] = 2540 soc_mem_index_max(unit, non_dma0->dma_mem[pipe]); 2541 } 2542 2543 *non_dma_entries += non_dma0->num_entries; 2544 2545 2546 non_dma1 = &soc->counter_non_dma[SOC_COUNTER_NON_DMA_EFP_BYTE - 2547 SOC_COUNTER_NON_DMA_START]; 2548 *non_dma1 = *non_dma0; 2549 non_dma1->id = SOC_COUNTER_NON_DMA_EFP_BYTE; 2550 non_dma1->flags = _SOC_COUNTER_NON_DMA_VALID; 2551 non_dma1->flags |= _SOC_COUNTER_NON_DMA_CTR_EVICT; 2552 non_dma1->flags |= _SOC_COUNTER_NON_DMA_NO_SHOW_C; 2553 2554 non_dma1->base_index = non_dma_start_index + *non_dma_entries; 2555 non_dma1->field = BYTE_COUNTERf; 2556 non_dma1->cname = "EFP_BYTE"; 2557 *non_dma_entries += non_dma1->num_entries; 2558 /* End of EFP Counters - Control Block */ 2559 2560 /* Control block for Ingress sFlow counters */ 2561 non_dma0 = &soc->counter_non_dma[SOC_COUNTER_NON_DMA_SFLOW_ING_PKT - 2562 SOC_COUNTER_NON_DMA_START]; 2563 non_dma0->id = SOC_COUNTER_NON_DMA_SFLOW_ING_PKT; 2564 non_dma0->flags = _SOC_COUNTER_NON_DMA_VALID | _SOC_COUNTER_NON_DMA_DO_DMA 2565 | _SOC_COUNTER_NON_DMA_SUBSET_PARENT; 2566 non_dma0->pbmp = PBMP_PORT_ALL(unit); 2567 non_dma0->base_index = non_dma_start_index + *non_dma_entries; 2568 non_dma0->entries_per_port = 1; 2569 non_dma0->mem = SFLOW_ING_DATA_SOURCEm; 2570 2571 num_entries = (soc_mem_index_count(unit, SFLOW_ING_DATA_SOURCEm) * 2572 NUM_PIPE(unit)) / _TD3_PIPES_PER_DEV; 2573 2574 #ifdef BCM_MAVERICK2_SUPPORT 2575 if (SOC_IS_MAVERICK2(unit)) { 2576 num_entries = soc_mem_index_count(unit, SFLOW_ING_DATA_SOURCEm); 2577 } 2578 #endif 2579 2580 entry_words = soc_mem_entry_words(unit, non_dma0->mem); 2581 non_dma0->num_entries = SOC_SFLOW_CTR_TYPE_COUNT * num_entries; 2582 non_dma0->reg = INVALIDr; 2583 non_dma0->cname = "SFLOW_ING_PKT"; 2584 non_dma0->field = SAMPLE_POOLf; 2585 non_dma0->dma_buf[0] = &buf[0]; 2586 2587 non_dma0->extra_ctr_ct = SOC_SFLOW_CTR_TYPE_COUNT; 2588 2589 /* Buffer allocated for 2x alloc size. Though 2nd half is NOT used. 2590 * This memory supports BYTE Count, but not implemented yet. So space 2591 * reserved. 2592 */ 2593 alloc_size = (non_dma0->extra_ctr_ct << 1) * sizeof(soc_counter_non_dma_t); 2594 non_dma0->extra_ctrs = sal_alloc(alloc_size, "non_dma_ctrs_sflow_ing"); 2595 2596 /* 2597 * Below represents how Extra cntrs are arranged 2598 * for sFlow counters. 2599 * 2600 * -------------------------- 2601 * [0] | SAMPLE_POOL [0] | 2602 * -------------------------- 2603 * [1] | N/A [0] | 2604 * -------------------------- 2605 * [2] | SAMPLE_POOL_SNAPSHOT [0] | 2606 * -------------------------- 2607 * [3] | N/A [0] | 2608 * -------------------------- 2609 * [4] | SAMPLE_COUNT [0] | 2610 * -------------------------- 2611 * [5] | N/A [0] | 2612 * -------------------------- 2613 */ 2614 2615 if (non_dma0->extra_ctrs == NULL) { 2616 non_dma0->extra_ctr_ct = 0; 2617 non_dma0->flags &= ~_SOC_COUNTER_NON_DMA_VALID; 2618 return SOC_E_MEMORY; 2619 } else { 2620 sal_memset(non_dma0->extra_ctrs, 0, alloc_size); 2621 rv = soc_counter_td3_extra_sflow_ctrs_init(unit, 2622 non_dma0, 2623 non_dma0->extra_ctrs, 2624 non_dma0->extra_ctr_ct, 2625 &num_extra_ctr_entries); 2626 if (rv != SOC_E_NONE) { 2627 LOG_CLI((BSL_META_U(unit, 2628 "ERR: Extra ctrs Init FAILED for id %d\n"), 2629 SOC_COUNTER_NON_DMA_SFLOW_ING_PKT - 2630 SOC_COUNTER_NON_DMA_START)); 2631 } 2632 non_dma0->num_entries = num_extra_ctr_entries; 2633 } 2634 *non_dma_entries += non_dma0->num_entries; 2635 2636 /* Control block for Flex sFlow counters */ 2637 non_dma0 = &soc->counter_non_dma[SOC_COUNTER_NON_DMA_SFLOW_FLEX_PKT - 2638 SOC_COUNTER_NON_DMA_START]; 2639 non_dma0->id = SOC_COUNTER_NON_DMA_SFLOW_FLEX_PKT; 2640 non_dma0->flags = _SOC_COUNTER_NON_DMA_VALID | _SOC_COUNTER_NON_DMA_DO_DMA 2641 | _SOC_COUNTER_NON_DMA_SUBSET_PARENT; 2642 non_dma0->pbmp = PBMP_PORT_ALL(unit); 2643 non_dma0->base_index = non_dma_start_index + *non_dma_entries; 2644 non_dma0->entries_per_port = 1; 2645 non_dma0->mem = SFLOW_ING_FLEX_DATA_SOURCEm; 2646 2647 num_entries = (soc_mem_index_count(unit, SFLOW_ING_FLEX_DATA_SOURCEm) * 2648 NUM_PIPE(unit)) / _TD3_PIPES_PER_DEV; 2649 2650 #ifdef BCM_MAVERICK2_SUPPORT 2651 if (SOC_IS_MAVERICK2(unit)) { 2652 num_entries = soc_mem_index_count(unit, SFLOW_ING_FLEX_DATA_SOURCEm); 2653 } 2654 #endif 2655 2656 entry_words = soc_mem_entry_words(unit, non_dma0->mem); 2657 non_dma0->num_entries = SOC_SFLOW_CTR_TYPE_COUNT * num_entries; 2658 non_dma0->reg = INVALIDr; 2659 non_dma0->cname = "SFLOW_FLEX_PKT"; 2660 non_dma0->field = SAMPLE_POOLf; 2661 non_dma0->dma_buf[0] = &buf[0]; 2662 2663 non_dma0->extra_ctr_ct = SOC_SFLOW_CTR_TYPE_COUNT; 2664 2665 /* Buffer allocated for 2x alloc size. Though 2nd half is NOT used. 2666 * This memory supports BYTE Count, but not implemented yet. So space 2667 * reserved. 2668 */ 2669 alloc_size = (non_dma0->extra_ctr_ct << 1) * sizeof(soc_counter_non_dma_t); 2670 non_dma0->extra_ctrs = sal_alloc(alloc_size, "non_dma_ctrs_sflow_flex"); 2671 2672 if (non_dma0->extra_ctrs == NULL) { 2673 non_dma0->extra_ctr_ct = 0; 2674 non_dma0->flags &= ~_SOC_COUNTER_NON_DMA_VALID; 2675 return SOC_E_MEMORY; 2676 } else { 2677 sal_memset(non_dma0->extra_ctrs, 0, alloc_size); 2678 rv = soc_counter_td3_extra_sflow_ctrs_init(unit, 2679 non_dma0, 2680 non_dma0->extra_ctrs, 2681 non_dma0->extra_ctr_ct, 2682 &num_extra_ctr_entries); 2683 if (rv != SOC_E_NONE) { 2684 LOG_CLI((BSL_META_U(unit, 2685 "ERR: Extra ctrs Init FAILED for id %d\n"), 2686 SOC_COUNTER_NON_DMA_SFLOW_FLEX_PKT - 2687 SOC_COUNTER_NON_DMA_START)); 2688 } 2689 non_dma0->num_entries = num_extra_ctr_entries; 2690 } 2691 *non_dma_entries += non_dma0->num_entries; 2692 2693 2694 2695 2696 /* Control block for IDB OBM counters */ 2697 /* Lossy LO drop counters - Pkt Counters */ 2698 non_dma0 = 2699 &soc->counter_non_dma[SOC_COUNTER_NON_DMA_PORT_DROP_PKT_OBM_LOSSY_LO - 2700 SOC_COUNTER_NON_DMA_START]; 2701 non_dma0->id = SOC_COUNTER_NON_DMA_PORT_DROP_PKT_OBM_LOSSY_LO; 2702 non_dma0->base_index = non_dma_start_index + *non_dma_entries; 2703 non_dma0->reg = IDB_OBM0_LOSSY_LO_PKT_DROP_COUNTr; 2704 non_dma0->cname = "OBM_LOSSY_LO_DRP_PKT"; 2705 2706 /* Common across all OBM structures */ 2707 non_dma0->flags = _SOC_COUNTER_NON_DMA_VALID | 2708 _SOC_COUNTER_NON_DMA_OBM; 2709 /* Use Parent-Child model to cover all 16 OBMs */ 2710 non_dma0->flags |= _SOC_COUNTER_NON_DMA_SUBSET_PARENT; 2711 non_dma0->pbmp = PBMP_PORT_ALL(unit); 2712 non_dma0->entries_per_port = 4; 2713 non_dma0->num_entries = 4 * NUM_PIPE(unit); 2714 non_dma0->mem = INVALIDm; 2715 non_dma0->field = COUNTERf; 2716 non_dma0->dma_buf[0] = &buf[0]; 2717 2718 /* 2719 * Below represents how Extra cntrs are arranged 2720 * for OBM 0-15 Drop Counters. 2721 * n = NUM_OBMs (16) 2722 * 2723 * [0] [2] [2n-2] 2724 * ------ ------ ------ 2725 * | || |...| | 2726 * | PKT || PKT |...| PKT | 2727 * | [0] || [1] |...| [n-1]| 2728 * ------ ------ ... ------ 2729 * | || |...| | 2730 * | BYTE || BYTE |...| BYTE | 2731 * | [0] || [1] |...| [n-1]| 2732 * ------ ------ ------ 2733 * [1] [3] [2n-1] 2734 */ 2735 non_dma0->extra_ctr_ct = _TD3_PBLKS_PER_PIPE; /* 16 OBMs per Pipe */ 2736 2737 #ifdef BCM_MAVERICK2_SUPPORT 2738 if (SOC_IS_MAVERICK2(unit)) { 2739 non_dma0->extra_ctr_ct = 20; /* 20 OBMs per Pipe */ 2740 } 2741 #endif 2742 2743 alloc_size = (non_dma0->extra_ctr_ct << 1) * sizeof(soc_counter_non_dma_t); 2744 temp = non_dma0->extra_ctrs = sal_alloc(alloc_size, 2745 "non_dma_ctrs_obm_lossy_lo"); 2746 2747 if (non_dma0->extra_ctrs == NULL) { 2748 non_dma0->extra_ctr_ct = 0; 2749 non_dma0->flags &= ~_SOC_COUNTER_NON_DMA_VALID; 2750 return SOC_E_MEMORY; 2751 } else { 2752 sal_memset(non_dma0->extra_ctrs, 0, alloc_size); 2753 rv = soc_counter_trident3_extra_obm_ctrs_init(unit, 2754 non_dma0, 2755 non_dma0->extra_ctrs, 2756 non_dma0->extra_ctr_ct, 2757 &num_extra_ctr_entries); 2758 if (rv != SOC_E_NONE) { 2759 LOG_CLI((BSL_META_U(unit, 2760 "ERR: Extra ctrs Init FAILED for id %d\n"), 2761 non_dma0->id - SOC_COUNTER_NON_DMA_START)); 2762 } 2763 non_dma0->num_entries = num_extra_ctr_entries; 2764 } 2765 *non_dma_entries += non_dma0->num_entries; 2766 2767 /* Lossy LO drop counters - Byte Counters */ 2768 non_dma1 = 2769 &soc->counter_non_dma[SOC_COUNTER_NON_DMA_PORT_DROP_BYTE_OBM_LOSSY_LO - 2770 SOC_COUNTER_NON_DMA_START]; 2771 *non_dma1 = *non_dma0; 2772 non_dma1->id = SOC_COUNTER_NON_DMA_PORT_DROP_BYTE_OBM_LOSSY_LO; 2773 non_dma1->base_index = non_dma_start_index + *non_dma_entries; 2774 non_dma1->reg = IDB_OBM0_LOSSY_LO_BYTE_DROP_COUNTr; 2775 non_dma1->field = COUNTERf; 2776 non_dma1->cname = "OBM_LOSSY_LO_DRP_BYTE"; 2777 2778 /* Memory for extra ctrs for BYTE_CTRS are done along with PACKET_CTR */ 2779 non_dma1->extra_ctrs = temp + 1; 2780 if (non_dma1->extra_ctrs) { 2781 rv = soc_counter_trident3_extra_obm_ctrs_init(unit, 2782 non_dma1, 2783 non_dma1->extra_ctrs, 2784 non_dma1->extra_ctr_ct, 2785 &num_extra_ctr_entries); 2786 if (rv != SOC_E_NONE) { 2787 LOG_CLI((BSL_META_U(unit, 2788 "ERR: Extra ctrs Init FAILED for id %d\n"), 2789 non_dma1->id - SOC_COUNTER_NON_DMA_START)); 2790 } 2791 } 2792 *non_dma_entries += non_dma1->num_entries; 2793 2794 /* Lossy HI drop counters - Packet Counters */ 2795 non_dma1 = 2796 &soc->counter_non_dma[SOC_COUNTER_NON_DMA_PORT_DROP_PKT_OBM_LOSSY_HI - 2797 SOC_COUNTER_NON_DMA_START]; 2798 *non_dma1 = *non_dma0; 2799 non_dma1->id = SOC_COUNTER_NON_DMA_PORT_DROP_PKT_OBM_LOSSY_HI; 2800 non_dma1->base_index = non_dma_start_index + *non_dma_entries; 2801 non_dma1->reg = IDB_OBM0_LOSSY_HI_PKT_DROP_COUNTr; 2802 non_dma1->cname = "OBM_LOSSY_HI_DRP_PKT"; 2803 2804 temp = non_dma1->extra_ctrs = sal_alloc(alloc_size, 2805 "non_dma_ctrs_obm_lossy_hi"); 2806 2807 if (non_dma1->extra_ctrs == NULL) { 2808 non_dma1->extra_ctr_ct = 0; 2809 non_dma1->flags &= ~_SOC_COUNTER_NON_DMA_VALID; 2810 return SOC_E_MEMORY; 2811 } else { 2812 sal_memset(non_dma1->extra_ctrs, 0, alloc_size); 2813 rv = soc_counter_trident3_extra_obm_ctrs_init(unit, 2814 non_dma1, 2815 non_dma1->extra_ctrs, 2816 non_dma1->extra_ctr_ct, 2817 &num_extra_ctr_entries); 2818 if (rv != SOC_E_NONE) { 2819 LOG_CLI((BSL_META_U(unit, 2820 "ERR: Extra ctrs Init FAILED for id %d\n"), 2821 non_dma1->id - SOC_COUNTER_NON_DMA_START)); 2822 } 2823 non_dma1->num_entries = num_extra_ctr_entries; 2824 } 2825 *non_dma_entries += non_dma1->num_entries; 2826 2827 2828 /* Lossy HI drop counters - Byte Counters */ 2829 non_dma1 = 2830 &soc->counter_non_dma[SOC_COUNTER_NON_DMA_PORT_DROP_BYTE_OBM_LOSSY_HI - 2831 SOC_COUNTER_NON_DMA_START]; 2832 *non_dma1 = *non_dma0; 2833 non_dma1->id = SOC_COUNTER_NON_DMA_PORT_DROP_BYTE_OBM_LOSSY_HI; 2834 non_dma1->base_index = non_dma_start_index + *non_dma_entries; 2835 non_dma1->reg = IDB_OBM0_LOSSY_HI_BYTE_DROP_COUNTr; 2836 non_dma1->field = COUNTERf; 2837 non_dma1->cname = "OBM_LOSSY_HI_DRP_BYTE"; 2838 2839 /* Memory for extra ctrs for BYTE_CTRS are done along with PACKET_CTR */ 2840 non_dma1->extra_ctrs = temp + 1; 2841 if (non_dma1->extra_ctrs) { 2842 rv = soc_counter_trident3_extra_obm_ctrs_init(unit, 2843 non_dma1, 2844 non_dma1->extra_ctrs, 2845 non_dma1->extra_ctr_ct, 2846 &num_extra_ctr_entries); 2847 if (rv != SOC_E_NONE) { 2848 LOG_CLI((BSL_META_U(unit, 2849 "ERR: Extra ctrs Init FAILED for id %d\n"), 2850 non_dma1->id - SOC_COUNTER_NON_DMA_START)); 2851 } 2852 } 2853 *non_dma_entries += non_dma1->num_entries; 2854 2855 2856 /* Lossless0 drop counters - Packet Counters */ 2857 non_dma1 = 2858 &soc->counter_non_dma[SOC_COUNTER_NON_DMA_PORT_DROP_PKT_OBM_LOSSLESS0 - 2859 SOC_COUNTER_NON_DMA_START]; 2860 *non_dma1 = *non_dma0; 2861 non_dma1->id = SOC_COUNTER_NON_DMA_PORT_DROP_PKT_OBM_LOSSLESS0; 2862 non_dma1->base_index = non_dma_start_index + *non_dma_entries; 2863 non_dma1->reg = IDB_OBM0_LOSSLESS0_PKT_DROP_COUNTr; 2864 non_dma1->cname = "OBM_LOSSLESS0_DRP_PKT"; 2865 2866 temp = non_dma1->extra_ctrs = sal_alloc(alloc_size, 2867 "non_dma_ctrs_obm_lossless0"); 2868 2869 if (non_dma1->extra_ctrs == NULL) { 2870 non_dma1->extra_ctr_ct = 0; 2871 non_dma1->flags &= ~_SOC_COUNTER_NON_DMA_VALID; 2872 return SOC_E_MEMORY; 2873 } else { 2874 sal_memset(non_dma1->extra_ctrs, 0, alloc_size); 2875 rv = soc_counter_trident3_extra_obm_ctrs_init(unit, 2876 non_dma1, 2877 non_dma1->extra_ctrs, 2878 non_dma1->extra_ctr_ct, 2879 &num_extra_ctr_entries); 2880 if (rv != SOC_E_NONE) { 2881 LOG_CLI((BSL_META_U(unit, 2882 "ERR: Extra ctrs Init FAILED for id %d\n"), 2883 non_dma1->id - SOC_COUNTER_NON_DMA_START)); 2884 } 2885 non_dma1->num_entries = num_extra_ctr_entries; 2886 } 2887 *non_dma_entries += non_dma1->num_entries; 2888 2889 /* Lossless0 drop counters - Byte Counters */ 2890 non_dma1 = 2891 &soc->counter_non_dma[SOC_COUNTER_NON_DMA_PORT_DROP_BYTE_OBM_LOSSLESS0 - 2892 SOC_COUNTER_NON_DMA_START]; 2893 *non_dma1 = *non_dma0; 2894 non_dma1->id = SOC_COUNTER_NON_DMA_PORT_DROP_BYTE_OBM_LOSSLESS0; 2895 non_dma1->base_index = non_dma_start_index + *non_dma_entries; 2896 non_dma1->reg = IDB_OBM0_LOSSLESS0_BYTE_DROP_COUNTr; 2897 non_dma1->field = COUNTERf; 2898 non_dma1->cname = "OBM_LOSSLESS0_DRP_BYTE"; 2899 2900 /* Memory for extra ctrs for BYTE_CTRS are done along with PACKET_CTR */ 2901 non_dma1->extra_ctrs = temp + 1; 2902 if (non_dma1->extra_ctrs) { 2903 rv = soc_counter_trident3_extra_obm_ctrs_init(unit, 2904 non_dma1, 2905 non_dma1->extra_ctrs, 2906 non_dma1->extra_ctr_ct, 2907 &num_extra_ctr_entries); 2908 if (rv != SOC_E_NONE) { 2909 LOG_CLI((BSL_META_U(unit, 2910 "ERR: Extra ctrs Init FAILED for id %d\n"), 2911 non_dma1->id - SOC_COUNTER_NON_DMA_START)); 2912 } 2913 } 2914 *non_dma_entries += non_dma1->num_entries; 2915 2916 /* Lossless1 drop counters - Packet counters */ 2917 non_dma1 = 2918 &soc->counter_non_dma[SOC_COUNTER_NON_DMA_PORT_DROP_PKT_OBM_LOSSLESS1 - 2919 SOC_COUNTER_NON_DMA_START]; 2920 *non_dma1 = *non_dma0; 2921 non_dma1->id = SOC_COUNTER_NON_DMA_PORT_DROP_PKT_OBM_LOSSLESS1; 2922 non_dma1->base_index = non_dma_start_index + *non_dma_entries; 2923 non_dma1->reg = IDB_OBM0_LOSSLESS1_PKT_DROP_COUNTr; 2924 non_dma1->cname = "OBM_LOSSLESS1_DRP_PKT"; 2925 2926 temp = non_dma1->extra_ctrs = sal_alloc(alloc_size, 2927 "non_dma_ctrs_obm_lossless1"); 2928 2929 if (non_dma1->extra_ctrs == NULL) { 2930 non_dma1->extra_ctr_ct = 0; 2931 non_dma1->flags &= ~_SOC_COUNTER_NON_DMA_VALID; 2932 return SOC_E_MEMORY; 2933 } else { 2934 sal_memset(non_dma1->extra_ctrs, 0, alloc_size); 2935 rv = soc_counter_trident3_extra_obm_ctrs_init(unit, 2936 non_dma1, 2937 non_dma1->extra_ctrs, 2938 non_dma1->extra_ctr_ct, 2939 &num_extra_ctr_entries); 2940 if (rv != SOC_E_NONE) { 2941 LOG_CLI((BSL_META_U(unit, 2942 "ERR: Extra ctrs Init FAILED for id %d\n"), 2943 non_dma1->id - SOC_COUNTER_NON_DMA_START)); 2944 } 2945 non_dma1->num_entries = num_extra_ctr_entries; 2946 } 2947 *non_dma_entries += non_dma1->num_entries; 2948 2949 /* Lossless1 drop counters - Byte Counters */ 2950 non_dma1 = 2951 &soc->counter_non_dma[SOC_COUNTER_NON_DMA_PORT_DROP_BYTE_OBM_LOSSLESS1 - 2952 SOC_COUNTER_NON_DMA_START]; 2953 *non_dma1 = *non_dma0; 2954 non_dma1->id = SOC_COUNTER_NON_DMA_PORT_DROP_BYTE_OBM_LOSSLESS1; 2955 non_dma1->base_index = non_dma_start_index + *non_dma_entries; 2956 non_dma1->reg = IDB_OBM0_LOSSLESS1_BYTE_DROP_COUNTr; 2957 non_dma1->field = COUNTERf; 2958 non_dma1->cname = "OBM_LOSSLESS1_DRP_BYTE"; 2959 2960 /* Memory for extra ctrs for BYTE_CTRS are done along with PACKET_CTR */ 2961 non_dma1->extra_ctrs = temp + 1; 2962 if (non_dma1->extra_ctrs) { 2963 rv = soc_counter_trident3_extra_obm_ctrs_init(unit, 2964 non_dma1, 2965 non_dma1->extra_ctrs, 2966 non_dma1->extra_ctr_ct, 2967 &num_extra_ctr_entries); 2968 if (rv != SOC_E_NONE) { 2969 LOG_CLI((BSL_META_U(unit, 2970 "ERR: Extra ctrs Init FAILED for id %d\n"), 2971 non_dma1->id - SOC_COUNTER_NON_DMA_START)); 2972 } 2973 } 2974 *non_dma_entries += non_dma1->num_entries; 2975 2976 /* FC event counters */ 2977 non_dma1 = 2978 &soc->counter_non_dma[SOC_COUNTER_NON_DMA_PORT_OBM_FC_EVENTS - 2979 SOC_COUNTER_NON_DMA_START]; 2980 *non_dma1 = *non_dma0; 2981 non_dma1->id = SOC_COUNTER_NON_DMA_PORT_OBM_FC_EVENTS; 2982 non_dma1->base_index = non_dma_start_index + *non_dma_entries; 2983 non_dma1->reg = IDB_OBM0_FLOW_CONTROL_EVENT_COUNTr; 2984 non_dma1->field = COUNTERf; 2985 non_dma1->cname = "OBM_FC_EVENTS"; 2986 2987 temp = non_dma1->extra_ctrs = sal_alloc(alloc_size, 2988 "non_dma_ctrs_obm_fc"); 2989 2990 if (non_dma1->extra_ctrs == NULL) { 2991 non_dma1->extra_ctr_ct = 0; 2992 non_dma1->flags &= ~_SOC_COUNTER_NON_DMA_VALID; 2993 return SOC_E_MEMORY; 2994 } else { 2995 sal_memset(non_dma1->extra_ctrs, 0, alloc_size); 2996 rv = soc_counter_trident3_extra_obm_ctrs_init(unit, 2997 non_dma1, 2998 non_dma1->extra_ctrs, 2999 non_dma1->extra_ctr_ct, 3000 &num_extra_ctr_entries); 3001 if (rv != SOC_E_NONE) { 3002 LOG_CLI((BSL_META_U(unit, 3003 "ERR: Extra ctrs Init FAILED for id %d\n"), 3004 non_dma1->id - SOC_COUNTER_NON_DMA_START)); 3005 } 3006 non_dma1->num_entries = num_extra_ctr_entries; 3007 } 3008 *non_dma_entries += non_dma1->num_entries; 3009 /* End of Control block for IDB OBM counters */ 3010 3011 /* Eviction table init */ 3012 SOC_IF_ERROR_RETURN(soc_counter_trident3_eviction_init(unit)); 3013 3014 return SOC_E_NONE; 3015 3016 } 3017 3018 #endif /* BCM_TRIDENT3_SUPPORT */