tomahawk3_tdm.c (88977B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: tomahawk3_set_tdm.c 8 * Purpose: 9 * Requires: 10 */ 11 12 13 #include <shared/bsl.h> 14 #include <soc/tdm/core/tdm_top.h> 15 16 #include <soc/defs.h> 17 #include <soc/mem.h> 18 19 #if defined(BCM_TOMAHAWK3_SUPPORT) 20 21 #include <soc/init/tomahawk3_tdm.h> 22 23 24 /*** START SDK API COMMON CODE ***/ 25 26 #define TH3_TDM_MAX_FREQ 1325 27 28 /* MIN_SPACING_* table */ 29 static const struct soc_tomahawk3_tdm_min_spacing_s { 30 int def; 31 int min; 32 } soc_tomahawk3_tdm_min_spacing_settings[4][4] = { 33 { /* one cell */ 34 {12 , 6}, /* 50GE */ 35 { 6, 6}, /* 100GE */ 36 { 3, 3}, /* 200GE */ 37 { 3, 3} /* 400GE */ 38 }, 39 { /* two cell */ 40 {20 , 6}, /* 50GE */ 41 { 8, 6}, /* 100GE */ 42 { 3, 3}, /* 200GE */ 43 { 3, 3} /* 400GE */ 44 }, 45 { /* three cell */ 46 {32 , 6}, /* 50GE */ 47 {14, 6}, /* 100GE */ 48 { 5, 3}, /* 200GE */ 49 { 3, 3} /* 400GE */ 50 }, 51 { /* four cell */ 52 {44 , 6}, /* 50GE */ 53 {20, 6}, /* 100GE */ 54 { 8, 3}, /* 200GE */ 55 { 3, 3} /* 400GE */ 56 } 57 }; 58 59 60 61 /*! @fn int soc_tomahawk3_tdm_set_cal_config( 62 * int unit, 63 * soc_port_schedule_state_t *port_schedule_state, 64 * tdm_sched_inst_name_e sched_inst_name, 65 * int pipe, 66 * int phy_port, 67 * int is_port_down) 68 * @param unit Chip unit number. 69 * @param port_schedule_state Pointer to a soc_port_schedule_state_t 70 * struct variable. 71 * @param sched_inst_name name enum of instance 72 * @param pipe pipe number. 73 * @param phy_port phy_port to configure. 74 * @param phy_port is_port_down. boolean to indicate if port down 75 * @brief API to initialize/clear per port CAL_CONFIG 76 * Description: 77 * API to initialize/clear per port CAL_CONFIG 78 * Regs/Mems configured: IDB/MMU SCHED 79 * Parameters: 80 * unit - Device number 81 * *port_schedule_state_t - Agreed structure between SDK and DV 82 * Return Value: 83 * SOC_E_* 84 */ 85 int soc_tomahawk3_tdm_set_cal_config( 86 int unit, 87 soc_port_schedule_state_t *port_schedule_state, 88 tdm_sched_inst_name_e sched_inst_name, 89 int pipe_num, 90 int phy_port, 91 int is_port_down) 92 { 93 uint64 this_port_cal_slot_bitmap; 94 int this_port_number; 95 int this_slot_valid; 96 int this_port_speed; 97 int log_port; 98 soc_port_map_type_t *port_map; 99 uint64 fldval64, rval64; 100 int is_special_slot; 101 int inst, slot; 102 soc_reg_t reg; 103 int port_down_slot_pos_table[_TH3_TDM_LENGTH]; 104 105 static const soc_reg_t idb_cal_config_regs[] = { 106 IS_CAL_CONFIG_PIPE0r, IS_CAL_CONFIG_PIPE1r, 107 IS_CAL_CONFIG_PIPE2r, IS_CAL_CONFIG_PIPE3r, 108 IS_CAL_CONFIG_PIPE4r, IS_CAL_CONFIG_PIPE5r, 109 IS_CAL_CONFIG_PIPE6r, IS_CAL_CONFIG_PIPE7r 110 }; 111 112 static const soc_reg_t idb_pksch_cal_config_regs[] = { 113 IS_PKSCH_CAL_CONFIG_PIPE0r, IS_PKSCH_CAL_CONFIG_PIPE1r, 114 IS_PKSCH_CAL_CONFIG_PIPE2r, IS_PKSCH_CAL_CONFIG_PIPE3r, 115 IS_PKSCH_CAL_CONFIG_PIPE4r, IS_PKSCH_CAL_CONFIG_PIPE5r, 116 IS_PKSCH_CAL_CONFIG_PIPE6r, IS_PKSCH_CAL_CONFIG_PIPE7r 117 }; 118 119 /* Set reg's variables */ 120 121 if (is_port_down == 1) { /* in_port_map used at port down */ 122 port_map = &port_schedule_state->in_port_map; 123 } else { /* out_port_map used at port up */ 124 port_map = &port_schedule_state->out_port_map; 125 } 126 127 is_special_slot = (phy_port == (SOC_MAX_NUM_PORTS + 1)) ? 1 : 0; 128 129 this_port_number = (is_port_down == 1) ? 0 : 130 ((is_special_slot == 1) ? _TH3_TDM_SCHED_SPECIAL_SLOT : 131 port_map->port_p2m_mapping[phy_port] & 0x1f); 132 133 this_slot_valid = (is_port_down == 1) ? 0 : 1; 134 135 if (is_port_down == 1) { 136 this_port_speed = 0; 137 } else if (is_special_slot == 1) { 138 this_port_speed = 3; /* speed 50G for Aux ports */ 139 } else { 140 log_port = port_map->port_p2l_mapping[phy_port]; 141 switch (port_map->log_port_speed[log_port]) { 142 case SPEED_400G: 143 this_port_speed = 0; 144 break; 145 case SPEED_200G: 146 this_port_speed = 1; 147 break; 148 case SPEED_100G: 149 this_port_speed = 2; 150 break; 151 case SPEED_50G: 152 this_port_speed = 3; 153 break; 154 default: /* speed < 50G */ 155 this_port_speed = 3; 156 break; 157 } 158 } 159 160 COMPILER_64_ZERO(this_port_cal_slot_bitmap); 161 if (is_port_down == 0) { 162 for (slot = 0; slot < _TH3_TDM_LENGTH; slot++) { 163 if (port_schedule_state->tdm_ingress_schedule_pipe[pipe_num].tdm_schedule_slice[0].linerate_schedule[slot] == 164 phy_port) { 165 COMPILER_64_BITSET( 166 this_port_cal_slot_bitmap, slot); 167 } 168 } 169 } 170 171 /* Select the right reg based on sched instance */ 172 switch (sched_inst_name) { 173 case TDM_IDB_PORT_SCHED: 174 reg = idb_cal_config_regs[pipe_num]; 175 break; 176 case TDM_IDB_PKT_SCHED: 177 reg = idb_pksch_cal_config_regs[pipe_num]; 178 break; 179 case TDM_MMU_MAIN_SCHED: 180 reg = MMU_PTSCH_CAL_CONFIGr; 181 break; 182 case TDM_MMU_EB_PORT_SCHED: 183 reg = MMU_EBPTS_CAL_CONFIGr; 184 break; 185 case TDM_MMU_EB_PKT_SCHED: 186 reg = MMU_EBPTS_PKSCH_CAL_CONFIGr; 187 break; 188 default: 189 LOG_ERROR(BSL_LS_SOC_PORT, (BSL_META_U(unit, 190 "soc_tomahawk3_tdm_set_cal_config()" 191 "Unsupported sched_inst_name\n"))); 192 return SOC_E_PARAM; 193 break; 194 } 195 196 /* Set reg's field variables and configure */ 197 COMPILER_64_ZERO(rval64); 198 COMPILER_64_SET(fldval64, 0, this_port_number); 199 soc_reg64_field_set(unit, reg, &rval64, THIS_PORT_NUMBERf, fldval64); 200 soc_reg64_field_set(unit, reg, &rval64, THIS_PORT_CAL_SLOT_BITMAPf, this_port_cal_slot_bitmap); 201 COMPILER_64_SET(fldval64, 0, this_slot_valid); 202 soc_reg64_field_set(unit, reg, &rval64, THIS_SLOT_VALIDf, fldval64); 203 COMPILER_64_SET(fldval64, 0, this_port_speed); 204 soc_reg64_field_set(unit, reg, &rval64, THIS_PORT_SPEEDf, fldval64); 205 206 sal_memset(port_down_slot_pos_table, 0, sizeof(port_down_slot_pos_table)); 207 if (is_port_down == 1) { 208 if (is_special_slot == 0) { /* FP ports */ 209 log_port = port_map->port_p2l_mapping[phy_port]; 210 /* get the slots in the scheduler table that need to be invalidated */ 211 soc_tomahawk3_set_tdm_slot_pos_tbl(phy_port, 212 port_map->log_port_speed[log_port], port_down_slot_pos_table); 213 } else { /* special slot */ 214 port_down_slot_pos_table[_TH3_TDM_LENGTH - 1] = 1; 215 } 216 } 217 218 219 /* Configure with proper set_reg API */ 220 for (slot = 0; slot < _TH3_TDM_LENGTH; slot++) { 221 if (((is_port_down == 0) && /* add port to scheduler */ 222 (port_schedule_state->tdm_ingress_schedule_pipe[pipe_num].tdm_schedule_slice[0].linerate_schedule[slot] == 223 phy_port)) || 224 ((is_port_down == 1) && /* remove port from scheduler */ 225 (port_down_slot_pos_table[slot] == 1)) ) { 226 switch (sched_inst_name) { 227 case TDM_IDB_PORT_SCHED: 228 case TDM_IDB_PKT_SCHED: 229 SOC_IF_ERROR_RETURN(soc_reg64_set( 230 unit, reg, REG_PORT_ANY, slot, rval64)); 231 break; 232 case TDM_MMU_MAIN_SCHED: 233 case TDM_MMU_EB_PORT_SCHED: 234 case TDM_MMU_EB_PKT_SCHED: 235 inst = pipe_num | SOC_REG_ADDR_INSTANCE_MASK; 236 SOC_IF_ERROR_RETURN(soc_reg64_set( 237 unit, reg, inst, slot, rval64)); 238 break; 239 default: 240 LOG_ERROR(BSL_LS_SOC_PORT, (BSL_META_U(unit, 241 "soc_tomahawk3_tdm_set_cal_config()" 242 "Unsupported sched_inst_name 2nd\n"))); 243 return SOC_E_PARAM; 244 break; 245 } 246 } 247 } 248 249 return SOC_E_NONE; 250 } 251 252 /*! @fn int soc_tomahawk3_tdm_set_max_spacing( 253 * int unit, 254 * soc_port_schedule_state_t *port_schedule_state, 255 * tdm_sched_inst_name_e sched_inst_name, 256 * int pipe_num) 257 * @param unit Chip unit number. 258 * @param port_schedule_state Pointer to a soc_port_schedule_state_t 259 * struct variable. 260 * @param sched_inst_name name enum of instance 261 * @param pipe pipe number. 262 * @brief API to initialize/clear per port CAL_CONFIG 263 * Description: 264 * API to initialize/clear per port CAL_CONFIG 265 * Regs/Mems configured: IDB/MMU SCHED 266 * Parameters: 267 * unit - Device number 268 * *port_schedule_state_t - Agreed structure between SDK and DV 269 * Return Value: 270 * SOC_E_* 271 */ 272 int soc_tomahawk3_tdm_set_max_spacing( 273 int unit, 274 soc_port_schedule_state_t *port_schedule_state, 275 tdm_sched_inst_name_e sched_inst_name, 276 int pipe_num) 277 { 278 int max_spacing_all_speeds; 279 int max_spacing_special_slot; 280 uint32 rval; 281 int skip_instance; 282 int inst; 283 soc_reg_t reg = INVALIDr; 284 285 static const soc_reg_t idb_max_spacing_regs[] = { 286 IS_MAX_SPACING_PIPE0r, IS_MAX_SPACING_PIPE1r, 287 IS_MAX_SPACING_PIPE2r, IS_MAX_SPACING_PIPE3r, 288 IS_MAX_SPACING_PIPE4r, IS_MAX_SPACING_PIPE5r, 289 IS_MAX_SPACING_PIPE6r, IS_MAX_SPACING_PIPE7r 290 }; 291 292 /* Select the right reg based on sched instance */ 293 skip_instance = 0; 294 switch (sched_inst_name) { 295 case TDM_IDB_PORT_SCHED: 296 reg = idb_max_spacing_regs[pipe_num]; 297 break; 298 case TDM_MMU_EB_PORT_SCHED: 299 reg = MMU_EBPTS_MAX_SPACINGr; 300 break; 301 case TDM_IDB_PKT_SCHED: 302 case TDM_MMU_MAIN_SCHED: 303 case TDM_MMU_EB_PKT_SCHED: 304 skip_instance = 1; 305 break; 306 default: 307 LOG_ERROR(BSL_LS_SOC_PORT, (BSL_META_U(unit, 308 "soc_tomahawk3_tdm_set_max_spacing()" 309 "Unsupported sched_inst_name\n"))); 310 return SOC_E_PARAM; 311 break; 312 } 313 314 if (skip_instance == 1) {return SOC_E_NONE;} 315 316 /* 317 * max_spacing = (52 * core_freq / 1325) 318 * where 52 is the max spacing for 50G at 1325 MHz 319 */ 320 321 max_spacing_all_speeds = 322 soc_tomahawk3_div_round(52 * port_schedule_state->frequency, TH3_TDM_MAX_FREQ); 323 max_spacing_special_slot = 33; 324 325 rval = 0; 326 soc_reg_field_set(unit, reg, &rval, MAX_SPACING_ALL_SPEEDSf, max_spacing_all_speeds); 327 soc_reg_field_set(unit, reg, &rval, MAX_SPACING_SPECIAL_SLOTf, max_spacing_special_slot); 328 329 switch (sched_inst_name) { 330 case TDM_IDB_PORT_SCHED: 331 SOC_IF_ERROR_RETURN(soc_reg32_set( 332 unit, reg, REG_PORT_ANY, 0, rval)); 333 break; 334 case TDM_MMU_EB_PORT_SCHED: 335 inst = pipe_num | SOC_REG_ADDR_INSTANCE_MASK; 336 SOC_IF_ERROR_RETURN(soc_reg32_set( 337 unit, reg, inst, 0, rval)); 338 break; 339 default: 340 LOG_ERROR(BSL_LS_SOC_PORT, (BSL_META_U(unit, 341 "soc_tomahawk3_tdm_set_max_spacing()" 342 "Unsupported sched_inst_name 2nd \n"))); 343 return SOC_E_PARAM; 344 break; 345 } 346 347 return SOC_E_NONE; 348 } 349 350 351 /*! @fn int soc_tomahawk3_tdm_set_feature_ctrl( 352 * int unit, 353 * soc_port_schedule_state_t *port_schedule_state, 354 * tdm_sched_inst_name_e sched_inst_name, 355 * int pipe_num) 356 * @param unit Chip unit number. 357 * @param port_schedule_state Pointer to a soc_port_schedule_state_t 358 * struct variable. 359 * @param sched_inst_name name enum of instance 360 * @param pipe pipe number. 361 * @brief API to initialize/clear per port FEATURE_CTRL 362 * Description: 363 * API to initialize/clear per port FEATURE_CTRL 364 * Regs/Mems configured: IDB/MMU PRT SCHED 365 * Parameters: 366 * unit - Device number 367 * *port_schedule_state_t - Agreed structure between SDK and DV 368 * Return Value: 369 * SOC_E_* 370 */ 371 int soc_tomahawk3_tdm_set_feature_ctrl( 372 int unit, 373 soc_port_schedule_state_t *port_schedule_state, 374 tdm_sched_inst_name_e sched_inst_name, 375 int pipe_num) 376 { 377 int disable_max_spacing; 378 int enable_bubble_mop; 379 int skip_instance; 380 int inst; 381 uint32 rval; 382 soc_reg_t reg; 383 384 static const soc_reg_t idb_feature_ctrl_regs[] = { 385 IS_FEATURE_CTRL_PIPE0r, IS_FEATURE_CTRL_PIPE1r, 386 IS_FEATURE_CTRL_PIPE2r, IS_FEATURE_CTRL_PIPE3r, 387 IS_FEATURE_CTRL_PIPE4r, IS_FEATURE_CTRL_PIPE5r, 388 IS_FEATURE_CTRL_PIPE6r, IS_FEATURE_CTRL_PIPE7r 389 }; 390 391 /* Select the right reg based on sched instance */ 392 skip_instance = 0; 393 disable_max_spacing = 0; 394 enable_bubble_mop = 1; 395 switch (sched_inst_name) { 396 case TDM_IDB_PORT_SCHED: 397 reg = idb_feature_ctrl_regs[pipe_num]; 398 break; 399 case TDM_MMU_EB_PORT_SCHED: 400 reg = MMU_EBPTS_FEATURE_CTRLr; 401 enable_bubble_mop = 0; /* It's don't care; set to 0 */ 402 break; 403 case TDM_IDB_PKT_SCHED: 404 case TDM_MMU_MAIN_SCHED: 405 case TDM_MMU_EB_PKT_SCHED: 406 skip_instance = 1; 407 break; 408 default: 409 LOG_ERROR(BSL_LS_SOC_PORT, (BSL_META_U(unit, 410 "soc_tomahawk3_tdm_set_feature_ctrl()" 411 "Unsupported sched_inst_name\n"))); 412 return SOC_E_PARAM; 413 break; 414 } 415 416 if (skip_instance == 1) {return SOC_E_NONE;} 417 418 rval = 0; 419 soc_reg_field_set(unit, reg, &rval, DISABLE_MAX_SPACINGf, 420 disable_max_spacing); 421 soc_reg_field_set(unit, reg, &rval, ENABLE_BUBBLE_MOPf, 422 enable_bubble_mop); 423 424 switch (sched_inst_name) { 425 case TDM_IDB_PORT_SCHED: 426 SOC_IF_ERROR_RETURN(soc_reg32_set( 427 unit, reg, REG_PORT_ANY, 0, rval)); 428 break; 429 case TDM_MMU_EB_PORT_SCHED: 430 inst = pipe_num | SOC_REG_ADDR_INSTANCE_MASK; 431 SOC_IF_ERROR_RETURN(soc_reg32_set( 432 unit, reg, inst, 0, rval)); 433 break; 434 default: 435 LOG_ERROR(BSL_LS_SOC_PORT, (BSL_META_U(unit, 436 "soc_tomahawk3_tdm_set_feature_ctrl()" 437 "Unsupported sched_inst_name 2nd\n"))); 438 return SOC_E_PARAM; 439 break; 440 } 441 442 return SOC_E_NONE; 443 } 444 445 446 447 /*! @fn int soc_tomahawk3_tdm_set_cbmg_value( 448 * int unit, 449 * soc_port_schedule_state_t *port_schedule_state, 450 * tdm_sched_inst_name_e sched_inst_name, 451 * int pipe_num) 452 * @param unit Chip unit number. 453 * @param port_schedule_state Pointer to a soc_port_schedule_state_t 454 * struct variable. 455 * @param sched_inst_name name enum of instance 456 * @param pipe pipe number. 457 * @brief API to initialize/clear per port CBMG_VALUE 458 * Description: 459 * API to initialize/clear per port CBMG_VALUE 460 * Regs/Mems configured: IDB/MMU PRT SCHED 461 * Parameters: 462 * unit - Device number 463 * *port_schedule_state_t - Agreed structure between SDK and DV 464 * Return Value: 465 * SOC_E_* 466 */ 467 int soc_tomahawk3_tdm_set_cbmg_value( 468 int unit, 469 soc_port_schedule_state_t *port_schedule_state, 470 tdm_sched_inst_name_e sched_inst_name, 471 int pipe_num) 472 { 473 int terminal_counter_value; 474 int skip_instance; 475 int inst; 476 uint32 rval = 0; 477 soc_reg_t reg; 478 int null_bw; 479 480 static const soc_reg_t idb_cbmg_value_regs[] = { 481 IS_CBMG_VALUE_PIPE0r, IS_CBMG_VALUE_PIPE1r, 482 IS_CBMG_VALUE_PIPE2r, IS_CBMG_VALUE_PIPE3r, 483 IS_CBMG_VALUE_PIPE4r, IS_CBMG_VALUE_PIPE5r, 484 IS_CBMG_VALUE_PIPE6r, IS_CBMG_VALUE_PIPE7r 485 }; 486 487 /* Select the right reg based on sched instance */ 488 skip_instance = 0; 489 490 null_bw = 12; 491 switch (sched_inst_name) { 492 case TDM_IDB_PORT_SCHED: 493 reg = idb_cbmg_value_regs[pipe_num]; 494 null_bw = 12; /* 12 MHz */ 495 break; 496 case TDM_MMU_EB_PORT_SCHED: 497 reg = MMU_EBPTS_CBMG_VALUEr; 498 null_bw = 5; /* 5 MHz */ 499 break; 500 case TDM_IDB_PKT_SCHED: 501 case TDM_MMU_MAIN_SCHED: 502 case TDM_MMU_EB_PKT_SCHED: 503 skip_instance = 1; 504 break; 505 default: 506 LOG_ERROR(BSL_LS_SOC_PORT, (BSL_META_U(unit, 507 "soc_tomahawk3_tdm_set_cbmg_value()" 508 "Unsupported sched_inst_name\n"))); 509 return SOC_E_PARAM; 510 break; 511 } 512 513 if (skip_instance == 1) {return SOC_E_NONE;} 514 515 /* TH3 bandwidth requirements are roughly as follows: 516 * For minimum guarantee of 8.1G(IP) & 3.4(EP) computed at 64B packets, 517 * Null/IDLE slots should be picked with an average TDM of once every 518 * configurable terminal_counter_value cycles. 519 * CBMG_value = [(64+20)*8] * CoreFreq(MHz) / BW(Mbps) 520 * IP: IFP Refresh 8.2MHz + 3.8MHz SBUS = 12 MHz total 521 * EP: 3.8Mhz SBUS + 1.2MHz TCAM parity scan = 5MHz total 522 * Simplified formula: 523 * CBMG_value = FLOOR[ CoreFreq(MHz) / NullRate(MHz) ] 524 */ 525 terminal_counter_value = port_schedule_state->frequency / null_bw; 526 527 switch (sched_inst_name) { 528 case TDM_IDB_PORT_SCHED: 529 SOC_IF_ERROR_RETURN(soc_reg32_get( 530 unit, reg, REG_PORT_ANY, 0, &rval)); 531 soc_reg_field_set(unit, reg, &rval, 532 TERMINAL_COUNTER_VALUEf, 533 terminal_counter_value); 534 SOC_IF_ERROR_RETURN(soc_reg32_set( 535 unit, reg, REG_PORT_ANY, 0, rval)); 536 break; 537 case TDM_MMU_EB_PORT_SCHED: 538 inst = pipe_num | SOC_REG_ADDR_INSTANCE_MASK; 539 SOC_IF_ERROR_RETURN(soc_reg32_get( 540 unit, reg, inst, 0, &rval)); 541 soc_reg_field_set(unit, reg, &rval, 542 TERMINAL_COUNTER_VALUEf, 543 terminal_counter_value); 544 SOC_IF_ERROR_RETURN(soc_reg32_set( 545 unit, reg, inst, 0, rval)); 546 break; 547 default: 548 LOG_ERROR(BSL_LS_SOC_PORT, (BSL_META_U(unit, 549 "soc_tomahawk3_tdm_set_cbmg_value()" 550 "Unsupported sched_inst_name 2nd\n"))); 551 return SOC_E_PARAM; 552 break; 553 } 554 555 return SOC_E_NONE; 556 } 557 558 559 /*! @fn int soc_tomahawk3_tdm_set_urg_cell_spacing( 560 * int unit, 561 * soc_port_schedule_state_t *port_schedule_state, 562 * tdm_sched_inst_name_e sched_inst_name, 563 * int pipe_num) 564 * @param unit Chip unit number. 565 * @param port_schedule_state Pointer to a soc_port_schedule_state_t 566 * struct variable. 567 * @param sched_inst_name name enum of instance 568 * @param pipe pipe number. 569 * @brief API to initialize/clear per port URG_CELL_SPACING 570 * Description: 571 * API to initialize/clear per port / per speed URG_CELL_SPACING 572 * Regs/Mems configured: IDB/MMU PRT SCHED 573 * Parameters: 574 * unit - Device number 575 * *port_schedule_state_t - Agreed structure between SDK and DV 576 * Return Value: 577 * SOC_E_* 578 */ 579 int soc_tomahawk3_tdm_set_urg_cell_spacing( 580 int unit, 581 soc_port_schedule_state_t *port_schedule_state, 582 tdm_sched_inst_name_e sched_inst_name, 583 int pipe_num) 584 { 585 int urg_pick_50g_spacing; 586 int urg_pick_100g_spacing; 587 int urg_pick_200g_spacing; 588 int urg_pick_400g_spacing; 589 int skip_instance; 590 int inst; 591 uint32 rval; 592 soc_reg_t reg; 593 int core_clock_freq; 594 595 static const soc_reg_t idb_urg_cell_spacing_regs[] = { 596 IS_URG_CELL_SPACING_PIPE0r, IS_URG_CELL_SPACING_PIPE1r, 597 IS_URG_CELL_SPACING_PIPE2r, IS_URG_CELL_SPACING_PIPE3r, 598 IS_URG_CELL_SPACING_PIPE4r, IS_URG_CELL_SPACING_PIPE5r, 599 IS_URG_CELL_SPACING_PIPE6r, IS_URG_CELL_SPACING_PIPE7r 600 }; 601 602 /* Select the right reg based on sched instance */ 603 skip_instance = 0; 604 605 switch (sched_inst_name) { 606 case TDM_IDB_PORT_SCHED: 607 reg = idb_urg_cell_spacing_regs[pipe_num]; 608 break; 609 case TDM_MMU_EB_PORT_SCHED: 610 reg = MMU_EBPTS_URG_CELL_SPACINGr; 611 break; 612 case TDM_IDB_PKT_SCHED: 613 case TDM_MMU_MAIN_SCHED: 614 case TDM_MMU_EB_PKT_SCHED: 615 skip_instance = 1; 616 break; 617 default: 618 LOG_ERROR(BSL_LS_SOC_PORT, (BSL_META_U(unit, 619 "soc_tomahawk3_tdm_set_urg_cell_spacing()" 620 "Unsupported sched_inst_name\n"))); 621 return SOC_E_PARAM; 622 break; 623 } 624 625 if (skip_instance == 1) {return SOC_E_NONE;} 626 627 /* 628 * FLOOR[(CoreFreq * 84 * 8) / 400000] * (400000 / SPEED); 629 */ 630 core_clock_freq = port_schedule_state->frequency; 631 if (core_clock_freq >= TH3_TDM_MAX_FREQ) { 632 urg_pick_400g_spacing = (core_clock_freq * 84 * 8) / 400000; 633 urg_pick_200g_spacing = 2 * urg_pick_400g_spacing; 634 urg_pick_100g_spacing = 4 * urg_pick_400g_spacing; 635 urg_pick_50g_spacing = 8 * urg_pick_400g_spacing; 636 } else { 637 urg_pick_200g_spacing = (core_clock_freq * 84 * 8) / 200000; 638 urg_pick_100g_spacing = 2 * urg_pick_200g_spacing; 639 urg_pick_50g_spacing = 4 * urg_pick_200g_spacing; 640 urg_pick_400g_spacing = urg_pick_200g_spacing; /* N/A */ 641 } 642 643 rval = 0; 644 soc_reg_field_set(unit, reg, &rval, URG_PICK_50G_SPACINGf, 645 urg_pick_50g_spacing); 646 soc_reg_field_set(unit, reg, &rval, URG_PICK_100G_SPACINGf, 647 urg_pick_100g_spacing); 648 soc_reg_field_set(unit, reg, &rval, URG_PICK_200G_SPACINGf, 649 urg_pick_200g_spacing); 650 soc_reg_field_set(unit, reg, &rval, URG_PICK_400G_SPACINGf, 651 urg_pick_400g_spacing); 652 653 switch (sched_inst_name) { 654 case TDM_IDB_PORT_SCHED: 655 SOC_IF_ERROR_RETURN(soc_reg32_set( 656 unit, reg, REG_PORT_ANY, 0, rval)); 657 break; 658 case TDM_MMU_EB_PORT_SCHED: 659 inst = pipe_num | SOC_REG_ADDR_INSTANCE_MASK; 660 SOC_IF_ERROR_RETURN(soc_reg32_set( 661 unit, reg, inst, 0, rval)); 662 break; 663 default: 664 LOG_ERROR(BSL_LS_SOC_PORT, (BSL_META_U(unit, 665 "soc_tomahawk3_tdm_set_urg_cell_spacing()" 666 "Unsupported sched_inst_name 2nd\n"))); 667 return SOC_E_PARAM; 668 break; 669 } 670 671 return SOC_E_NONE; 672 } 673 674 675 676 /*! @fn int soc_tomahawk3_tdm_set_pksch_pkt_credits_per_pipe( 677 * int unit, 678 * soc_port_schedule_state_t *port_schedule_state, 679 * tdm_sched_inst_name_e sched_inst_name, 680 * int pipe_num) 681 * @param unit Chip unit number. 682 * @param port_schedule_state Pointer to a soc_port_schedule_state_t 683 * struct variable. 684 * @param sched_inst_name name enum of instance 685 * @param pipe pipe number. 686 * @brief API to initialize/clear per port CBMG_VALUE 687 * Description: 688 * API to initialize/clear per port CBMG_VALUE 689 * Regs/Mems configured: IDB/MMU PRT SCHED 690 * Parameters: 691 * unit - Device number 692 * *port_schedule_state_t - Agreed structure between SDK and DV 693 * Return Value: 694 * SOC_E_* 695 */ 696 int soc_tomahawk3_tdm_set_pksch_pkt_credits_per_pipe( 697 int unit, 698 soc_port_schedule_state_t *port_schedule_state, 699 tdm_sched_inst_name_e sched_inst_name, 700 int pipe_num) 701 { 702 int pkt_credit_count; 703 int skip_instance; 704 int inst; 705 uint32 rval; 706 soc_reg_t reg; 707 708 static const soc_reg_t idb_pkt_credits_regs[] = { 709 IS_PKSCH_PKT_CREDITS_PER_PIPE_PIPE0r, IS_PKSCH_PKT_CREDITS_PER_PIPE_PIPE1r, 710 IS_PKSCH_PKT_CREDITS_PER_PIPE_PIPE2r, IS_PKSCH_PKT_CREDITS_PER_PIPE_PIPE3r, 711 IS_PKSCH_PKT_CREDITS_PER_PIPE_PIPE4r, IS_PKSCH_PKT_CREDITS_PER_PIPE_PIPE5r, 712 IS_PKSCH_PKT_CREDITS_PER_PIPE_PIPE6r, IS_PKSCH_PKT_CREDITS_PER_PIPE_PIPE7r 713 }; 714 715 /* Select the right reg based on sched instance */ 716 skip_instance = 0; 717 718 /* TH3 recommended 719 */ 720 pkt_credit_count = 21; 721 switch (sched_inst_name) { 722 case TDM_IDB_PKT_SCHED: 723 reg = idb_pkt_credits_regs[pipe_num]; 724 break; 725 case TDM_MMU_EB_PKT_SCHED: 726 reg = MMU_EBPTS_PKSCH_PKT_CREDITS_PER_PIPEr; 727 break; 728 case TDM_IDB_PORT_SCHED: 729 case TDM_MMU_MAIN_SCHED: 730 case TDM_MMU_EB_PORT_SCHED: 731 skip_instance = 1; 732 break; 733 default: 734 LOG_ERROR(BSL_LS_SOC_PORT, (BSL_META_U(unit, 735 "soc_tomahawk3_tdm_set_pksch_pkt_credits_per_pipe()" 736 "Unsupported sched_inst_name\n"))); 737 return SOC_E_PARAM; 738 break; 739 } 740 741 if (skip_instance == 1) {return SOC_E_NONE;} 742 743 rval = 0; 744 soc_reg_field_set(unit, reg, &rval, PKT_CREDIT_COUNTf, 745 pkt_credit_count); 746 747 switch (sched_inst_name) { 748 case TDM_IDB_PKT_SCHED: 749 SOC_IF_ERROR_RETURN(soc_reg32_set( 750 unit, reg, REG_PORT_ANY, 0, rval)); 751 break; 752 case TDM_MMU_EB_PKT_SCHED: 753 inst = pipe_num | SOC_REG_ADDR_INSTANCE_MASK; 754 SOC_IF_ERROR_RETURN(soc_reg32_set( 755 unit, reg, inst, 0, rval)); 756 break; 757 default: 758 LOG_ERROR(BSL_LS_SOC_PORT, (BSL_META_U(unit, 759 "soc_tomahawk3_tdm_set_pksch_pkt_credits_per_pipe()" 760 "Unsupported sched_inst_name 2nd\n"))); 761 return SOC_E_PARAM; 762 break; 763 } 764 765 return SOC_E_NONE; 766 } 767 768 /* Max EB credit configurations for EB prt shced to MMU Main prt sched*/ 769 /* Indexed by speed: 50G:0, 100G:1; 200G:2; 400G:3*/ 770 static const int soc_th3_tdm_mmu_eb_credit_config_vals[] = { 771 47, 55, 71, 104}; 772 773 /*! @fn int soc_tomahawk3_tdm_set_eb_credit_config( 774 * int unit, 775 * soc_port_schedule_state_t *port_schedule_state, 776 * tdm_sched_inst_name_e sched_inst_name, 777 * int pipe, 778 * int phy_port, 779 * int is_port_down) 780 * @param unit Chip unit number. 781 * @param port_schedule_state Pointer to a soc_port_schedule_state_t 782 * struct variable. 783 * @param sched_inst_name name enum of instance 784 * @param pipe pipe number. 785 * @param phy_port phy_port to configure. 786 * @param phy_port is_port_down. boolean to indicate if port down 787 * @brief API to initialize/clear per port EB_CREDIT_CONFIG 788 * Description: 789 * API to initialize/clear per port EB_CREDIT_CONFIG 790 * Regs/Mems configured: MMU MAIN SCHED EB_CREDIT_CONFIG 791 * Parameters: 792 * unit - Device number 793 * *port_schedule_state_t - Agreed structure between SDK and DV 794 * Return Value: 795 * SOC_E_* 796 */ 797 int soc_tomahawk3_tdm_set_eb_credit_config( 798 int unit, 799 soc_port_schedule_state_t *port_schedule_state, 800 tdm_sched_inst_name_e sched_inst_name, 801 int pipe_num, 802 int phy_port, 803 int is_port_down) 804 { 805 int mmu_port; 806 int num_eb_credits; 807 soc_port_map_type_t *port_map; 808 int log_port; 809 int skip_instance; 810 int inst; 811 uint32 rval; 812 uint64 rval64; 813 soc_reg_t reg; 814 815 skip_instance = 0; 816 switch (sched_inst_name) { 817 case TDM_MMU_MAIN_SCHED: 818 reg = MMU_PTSCH_EB_CREDIT_CONFIGr; 819 break; 820 case TDM_IDB_PORT_SCHED: 821 case TDM_IDB_PKT_SCHED: 822 case TDM_MMU_EB_PORT_SCHED: 823 case TDM_MMU_EB_PKT_SCHED: 824 skip_instance = 1; 825 break; 826 default: 827 LOG_ERROR(BSL_LS_SOC_PORT, (BSL_META_U(unit, 828 "soc_tomahawk3_tdm_set_eb_credit_config()" 829 "Unsupported sched_inst_name\n"))); 830 return SOC_E_PARAM; 831 break; 832 } 833 834 /* Only MMU main prt scheduler gets this reg configured */ 835 if (skip_instance == 1) {return SOC_E_NONE;} 836 837 /* Set reg's variables */ 838 if (is_port_down == 1) { /* in_port_map used at port down */ 839 port_map = &port_schedule_state->in_port_map; 840 } else { /* out_port_map used at port up */ 841 port_map = &port_schedule_state->out_port_map; 842 } 843 844 mmu_port = port_map->port_p2m_mapping[phy_port]; 845 846 if (is_port_down == 1) { 847 num_eb_credits = 0; 848 } else { 849 log_port = port_map->port_p2l_mapping[phy_port]; 850 switch (port_map->log_port_speed[log_port]) { 851 case SPEED_400G: 852 num_eb_credits = soc_th3_tdm_mmu_eb_credit_config_vals[3]; 853 break; 854 case SPEED_200G: 855 num_eb_credits = soc_th3_tdm_mmu_eb_credit_config_vals[2]; 856 break; 857 case SPEED_100G: 858 num_eb_credits = soc_th3_tdm_mmu_eb_credit_config_vals[1]; 859 break; 860 default: /* any speed <= 50G; */ 861 num_eb_credits = soc_th3_tdm_mmu_eb_credit_config_vals[0]; 862 break; 863 } 864 } 865 866 rval = 0; 867 soc_reg_field_set(unit, reg, &rval, NUM_EB_CREDITSf, 868 num_eb_credits); 869 870 switch (sched_inst_name) { 871 case TDM_MMU_MAIN_SCHED: 872 inst = mmu_port; 873 COMPILER_64_SET(rval64, 0, rval); 874 SOC_IF_ERROR_RETURN(soc_reg_rawport_set(unit, reg, inst, 0, rval64)); 875 break; 876 default: 877 LOG_ERROR(BSL_LS_SOC_PORT, (BSL_META_U(unit, 878 "soc_tomahawk3_tdm_set_eb_credit_config()" 879 "Unsupported sched_inst_name 2nd\n"))); 880 return SOC_E_PARAM; 881 break; 882 } 883 884 return SOC_E_NONE; 885 } 886 887 888 /*! @fn int soc_tomahawk3_tdm_set_ebshp_port_cfg( 889 * int unit, 890 * soc_port_schedule_state_t *port_schedule_state, 891 * tdm_sched_inst_name_e sched_inst_name, 892 * int pipe, 893 * int phy_port, 894 * int is_port_down) 895 * @param unit Chip unit number. 896 * @param port_schedule_state Pointer to a soc_port_schedule_state_t 897 * struct variable. 898 * @param sched_inst_name name enum of instance 899 * @param pipe pipe number. 900 * @param phy_port phy_port to configure. 901 * @param phy_port is_port_down. boolean to indicate if port down 902 * @brief API to initialize/clear per port MMU_EBPTS_EBSHP_PORT_CFG 903 * Description: 904 * API to initialize/clear per port MMU_EBPTS_EBSHP_PORT_CFG 905 * Regs/Mems configured: MMU MAIN SCHED MMU_EBPTS_EBSHP_PORT_CFG 906 * Parameters: 907 * unit - Device number 908 * *port_schedule_state_t - Agreed structure between SDK and DV 909 * Return Value: 910 * SOC_E_* 911 */ 912 int soc_tomahawk3_tdm_set_ebshp_port_cfg( 913 int unit, 914 soc_port_schedule_state_t *port_schedule_state, 915 tdm_sched_inst_name_e sched_inst_name, 916 int pipe_num, 917 int phy_port, 918 int is_port_down) 919 { 920 int mmu_port; 921 int port_speed = 0; 922 soc_port_map_type_t *port_map; 923 int log_port; 924 int skip_instance; 925 int inst; 926 uint32 rval; 927 uint64 rval64; 928 soc_reg_t reg; 929 930 skip_instance = 0; 931 switch (sched_inst_name) { 932 case TDM_MMU_EB_PORT_SCHED: 933 reg = MMU_EBPTS_EBSHP_PORT_CFGr; 934 break; 935 case TDM_IDB_PORT_SCHED: 936 case TDM_IDB_PKT_SCHED: 937 case TDM_MMU_MAIN_SCHED: 938 case TDM_MMU_EB_PKT_SCHED: 939 skip_instance = 1; 940 break; 941 default: 942 LOG_ERROR(BSL_LS_SOC_PORT, (BSL_META_U(unit, 943 "soc_tomahawk3_tdm_set_ebshp_port_cfg()" 944 "Unsupported sched_inst_name\n"))); 945 return SOC_E_PARAM; 946 break; 947 } 948 949 /* Only MMU main prt scheduler gets this reg configured */ 950 if (skip_instance == 1) {return SOC_E_NONE;} 951 952 /* Set reg's variables */ 953 if (is_port_down == 1) { /* in_port_map used at port down */ 954 port_map = &port_schedule_state->in_port_map; 955 } else { /* out_port_map used at port up */ 956 port_map = &port_schedule_state->out_port_map; 957 } 958 959 mmu_port = port_map->port_p2m_mapping[phy_port]; 960 961 if (is_port_down == 1) { 962 port_speed = 0; 963 } else { 964 log_port = port_map->port_p2l_mapping[phy_port]; 965 switch (port_map->log_port_speed[log_port]) { 966 case SPEED_400G: port_speed = 7; break; 967 case SPEED_200G: port_speed = 6; break; 968 case SPEED_100G: port_speed = 5; break; 969 case SPEED_50G : port_speed = 4; break; 970 case SPEED_40G : port_speed = 3; break; 971 case SPEED_25G : port_speed = 2; break; 972 case SPEED_10G : port_speed = 1; break; 973 default: 974 LOG_ERROR(BSL_LS_SOC_PORT, (BSL_META_U(unit, 975 "soc_tomahawk3_tdm_set_ebshp_port_cfg()" 976 "Unsupported speed\n"))); 977 return SOC_E_PARAM; 978 break; 979 } 980 } 981 982 rval = 0; 983 soc_reg_field_set(unit, reg, &rval, PORT_SPEEDf, 984 port_speed); 985 986 switch (sched_inst_name) { 987 case TDM_MMU_EB_PORT_SCHED: 988 inst = mmu_port; 989 COMPILER_64_SET(rval64, 0, rval); 990 SOC_IF_ERROR_RETURN(soc_reg_rawport_set(unit, reg, inst, 0, rval64)); 991 break; 992 default: 993 LOG_ERROR(BSL_LS_SOC_PORT, (BSL_META_U(unit, 994 "soc_tomahawk3_tdm_set_ebshp_port_cfg()" 995 "Unsupported sched_inst_name 2nd\n"))); 996 return SOC_E_PARAM; 997 break; 998 } 999 1000 return SOC_E_NONE; 1001 } 1002 1003 1004 /*! @fn int soc_tomahawk3_tdm_clear_edb_credit_counter_per_port( 1005 * int unit, 1006 * soc_port_schedule_state_t *port_schedule_state, 1007 * tdm_sched_inst_name_e sched_inst_name, 1008 * int pipe, 1009 * int phy_port, 1010 * int is_port_down) 1011 * @param unit Chip unit number. 1012 * @param port_schedule_state Pointer to a soc_port_schedule_state_t 1013 * struct variable. 1014 * @param sched_inst_name name enum of instance 1015 * @param pipe pipe number. 1016 * @param phy_port phy_port to configure. 1017 * @param is_port_down. boolean to indicate if port down 1018 * @brief API to clear per port EDB_CREDIT_COUNTER 1019 * Description: 1020 * API to initialize/clear per port EDB_CREDIT_COUNTER 1021 * Regs/Mems configured: MMU EB_PORT_SCHED 1022 * Parameters: 1023 * unit - Device number 1024 * *port_schedule_state_t - Agreed structure between SDK and DV 1025 * Return Value: 1026 * SOC_E_* 1027 */ 1028 int soc_tomahawk3_tdm_clear_edb_credit_counter_per_port( 1029 int unit, 1030 soc_port_schedule_state_t *port_schedule_state, 1031 tdm_sched_inst_name_e sched_inst_name, 1032 int pipe_num, 1033 int phy_port, 1034 int is_port_down) 1035 { 1036 int mmu_port; 1037 int num_edb_credits; 1038 soc_port_map_type_t *port_map; 1039 int skip_instance; 1040 int inst; 1041 uint32 rval; 1042 uint64 rval64; 1043 soc_reg_t reg; 1044 1045 skip_instance = 0; 1046 switch (sched_inst_name) { 1047 case TDM_MMU_EB_PORT_SCHED: 1048 reg = MMU_EBPTS_EDB_CREDIT_COUNTERr; 1049 break; 1050 case TDM_IDB_PORT_SCHED: 1051 case TDM_IDB_PKT_SCHED: 1052 case TDM_MMU_MAIN_SCHED: 1053 case TDM_MMU_EB_PKT_SCHED: 1054 skip_instance = 1; 1055 break; 1056 default: 1057 LOG_ERROR(BSL_LS_SOC_PORT, (BSL_META_U(unit, 1058 "soc_tomahawk3_tdm_clear_edb_credit_counter_per_port()" 1059 "Unsupported sched_inst_name\n"))); 1060 return SOC_E_PARAM; 1061 break; 1062 } 1063 1064 /* Only EB prt scheduler gets this reg configured */ 1065 if (skip_instance == 1) {return SOC_E_NONE;} 1066 1067 /* Set reg's variables */ 1068 if (is_port_down == 1) { /* in_port_map used at port down */ 1069 port_map = &port_schedule_state->in_port_map; 1070 } else { /* out_port_map used at port up */ 1071 port_map = &port_schedule_state->out_port_map; 1072 } 1073 1074 mmu_port = port_map->port_p2m_mapping[phy_port]; 1075 num_edb_credits = 0; 1076 1077 rval = 0; 1078 soc_reg_field_set(unit, reg, &rval, NUM_EDB_CREDITSf, 1079 num_edb_credits); 1080 1081 switch (sched_inst_name) { 1082 case TDM_MMU_EB_PORT_SCHED: 1083 inst = mmu_port; 1084 COMPILER_64_SET(rval64, 0, rval); 1085 SOC_IF_ERROR_RETURN(soc_reg_rawport_set(unit, reg, inst, 0, rval64)); 1086 break; 1087 default: 1088 LOG_ERROR(BSL_LS_SOC_PORT, (BSL_META_U(unit, 1089 "soc_tomahawk3_tdm_clear_edb_credit_counter_per_port()" 1090 "Unsupported sched_inst_name 2nd\n"))); 1091 return SOC_E_PARAM; 1092 break; 1093 } 1094 1095 return SOC_E_NONE; 1096 } 1097 1098 1099 /*! @fn int soc_tomahawk3_tdm_clear_edb_credit_counter( 1100 * int unit, 1101 * soc_port_schedule_state_t *port_schedule_state) 1102 * @param unit Chip unit number. 1103 * @param port_schedule_state Pointer to a soc_port_schedule_state_t 1104 * struct variable. 1105 * @brief API to clear per port EDB_CREDIT_COUNTER 1106 * Description: 1107 * API to initialize/clear per port EDB_CREDIT_COUNTER 1108 * Regs/Mems configured: MMU EB_PORT_SCHED 1109 * Parameters: 1110 * unit - Device number 1111 * *port_schedule_state_t - Agreed structure between SDK and DV 1112 * Return Value: 1113 * SOC_E_* 1114 */ 1115 int soc_tomahawk3_tdm_clear_edb_credit_counter( 1116 int unit, 1117 soc_port_schedule_state_t *port_schedule_state) 1118 { 1119 int i, logical_port, physical_port; 1120 int pipe_num, is_port_down; 1121 1122 is_port_down = 1; /* that is, disable port */ 1123 for (i = 0; i < port_schedule_state->nport; i++) { 1124 if (port_schedule_state->resource[i].physical_port == -1) { /* port DOWN */ 1125 logical_port = port_schedule_state->resource[i].logical_port; 1126 pipe_num = logical_port / _TH3_DEV_PORTS_PER_PIPE; 1127 physical_port = 1128 port_schedule_state->in_port_map.port_l2p_mapping[logical_port]; 1129 SOC_IF_ERROR_RETURN(soc_tomahawk3_tdm_clear_edb_credit_counter_per_port(unit, port_schedule_state, 1130 TDM_MMU_EB_PORT_SCHED, pipe_num, physical_port, is_port_down)); 1131 } 1132 } 1133 1134 return SOC_E_NONE; 1135 } 1136 1137 1138 /*! @fn int soc_tomahawk3_tdm_set_eb_satisfied_threshold( 1139 * int unit, 1140 * soc_port_schedule_state_t *port_schedule_state, 1141 * tdm_sched_inst_name_e sched_inst_name, 1142 * int pipe_num) 1143 * @param unit Chip unit number. 1144 * @param port_schedule_state Pointer to a soc_port_schedule_state_t 1145 * struct variable. 1146 * @param sched_inst_name name enum of instance 1147 * @param pipe pipe number. 1148 * @brief API to initialize/clear per port EB_SATISFIED_THRESHOLD 1149 * Description: 1150 * API to initialize/clear per port EB_SATISFIED_THRESHOLD 1151 * Regs/Mems configured: MMU MAIN PRT SCHED 1152 * Parameters: 1153 * unit - Device number 1154 * *port_schedule_state_t - Agreed structure between SDK and DV 1155 * Return Value: 1156 * SOC_E_* 1157 */ 1158 int soc_tomahawk3_tdm_set_eb_satisfied_threshold( 1159 int unit, 1160 soc_port_schedule_state_t *port_schedule_state, 1161 tdm_sched_inst_name_e sched_inst_name, 1162 int pipe_num) 1163 { 1164 int num_satisfaction_credits_200g; 1165 int num_satisfaction_credits_100g; 1166 int num_satisfaction_credits_50g; 1167 int num_satisfaction_credits_400g; 1168 int skip_instance; 1169 int inst; 1170 uint32 rval; 1171 soc_reg_t reg; 1172 1173 1174 /* Select the right reg based on sched instance */ 1175 skip_instance = 0; 1176 1177 switch (sched_inst_name) { 1178 case TDM_MMU_MAIN_SCHED: 1179 reg = MMU_PTSCH_EB_SATISFIED_THRESHOLDr; 1180 break; 1181 case TDM_IDB_PORT_SCHED: 1182 case TDM_IDB_PKT_SCHED: 1183 case TDM_MMU_EB_PORT_SCHED: 1184 case TDM_MMU_EB_PKT_SCHED: 1185 skip_instance = 1; 1186 break; 1187 default: 1188 LOG_ERROR(BSL_LS_SOC_PORT, (BSL_META_U(unit, 1189 "soc_tomahawk3_tdm_set_eb_satisfied_threshold()" 1190 "Unsupported sched_inst_name\n"))); 1191 return SOC_E_PARAM; 1192 break; 1193 } 1194 1195 if (skip_instance == 1) {return SOC_E_NONE;} 1196 1197 /* 50% from EB_CREDIT_CONFIG */ 1198 num_satisfaction_credits_50g = soc_th3_tdm_mmu_eb_credit_config_vals[0] / 2; 1199 num_satisfaction_credits_100g = soc_th3_tdm_mmu_eb_credit_config_vals[1] / 2; 1200 num_satisfaction_credits_200g = soc_th3_tdm_mmu_eb_credit_config_vals[2] / 2; 1201 num_satisfaction_credits_400g = soc_th3_tdm_mmu_eb_credit_config_vals[3] / 2; 1202 1203 rval = 0; 1204 soc_reg_field_set(unit, reg, &rval, NUM_SATISFACTION_CREDITS_200Gf, 1205 num_satisfaction_credits_200g); 1206 soc_reg_field_set(unit, reg, &rval, NUM_SATISFACTION_CREDITS_100Gf, 1207 num_satisfaction_credits_100g); 1208 soc_reg_field_set(unit, reg, &rval, NUM_SATISFACTION_CREDITS_50Gf, 1209 num_satisfaction_credits_50g); 1210 soc_reg_field_set(unit, reg, &rval, NUM_SATISFACTION_CREDITS_400Gf, 1211 num_satisfaction_credits_400g); 1212 1213 switch (sched_inst_name) { 1214 case TDM_MMU_MAIN_SCHED: 1215 inst = pipe_num | SOC_REG_ADDR_INSTANCE_MASK; 1216 SOC_IF_ERROR_RETURN(soc_reg32_set( 1217 unit, reg, inst, 0, rval)); 1218 break; 1219 default: 1220 LOG_ERROR(BSL_LS_SOC_PORT, (BSL_META_U(unit, 1221 "soc_tomahawk3_tdm_set_eb_satisfied_threshold()" 1222 "Unsupported sched_inst_name 2nd\n"))); 1223 return SOC_E_PARAM; 1224 break; 1225 } 1226 1227 return SOC_E_NONE; 1228 } 1229 1230 /*! @fn int soc_tomahawk3_tdm_set_min_spacing( 1231 * int unit, 1232 * soc_port_schedule_state_t *port_schedule_state, 1233 * tdm_sched_inst_name_e sched_inst_name, 1234 * int pipe_num) 1235 * @param unit Chip unit number. 1236 * @param port_schedule_state Pointer to a soc_port_schedule_state_t 1237 * struct variable. 1238 * @param sched_inst_name name enum of instance 1239 * @param pipe pipe number. 1240 * @brief API to initialize MIN_SPACING_* regs 1241 * Description: 1242 * API to initialize MIN_SPACING_* regs 1243 * Regs/Mems configured: MMU MAIN PRT SCHED 1244 * Parameters: 1245 * unit - Device number 1246 * *port_schedule_state_t - Agreed structure between SDK and DV 1247 * Return Value: 1248 * SOC_E_* 1249 */ 1250 int soc_tomahawk3_tdm_set_min_spacing( 1251 int unit, 1252 soc_port_schedule_state_t *port_schedule_state, 1253 tdm_sched_inst_name_e sched_inst_name, 1254 int pipe_num) 1255 { 1256 int one_cell_400g; 1257 int one_cell_200g; 1258 int one_cell_100g; 1259 int one_cell_50g; 1260 int two_cell_400g; 1261 int two_cell_200g; 1262 int two_cell_100g; 1263 int two_cell_50g; 1264 int three_cell_400g; 1265 int three_cell_200g; 1266 int three_cell_100g; 1267 int three_cell_50g; 1268 int four_cell_400g; 1269 int four_cell_200g; 1270 int four_cell_100g; 1271 int four_cell_50g; 1272 int skip_instance; 1273 int inst; 1274 uint32 one_cell_rval, two_cell_rval, 1275 three_cell_rval, four_cell_rval; 1276 soc_reg_t one_cell_reg, two_cell_reg, 1277 three_cell_reg, four_cell_reg; 1278 soc_reg_t pick_to_same_port_pick_reg; 1279 soc_reg_t pick_to_same_port_cpu_reg; 1280 uint64 pick_to_same_port_pick_val; 1281 uint32 pick_to_same_port_cpu_val; 1282 uint64 pick_min_four_cell_50g, pick_min_four_cell_100g; 1283 uint64 pick_min_one_to_three_cell_50g, pick_min_one_to_three_cell_100g; 1284 uint32 pick_min_four_cell_cpu, pick_min_one_to_three_cell_cpu; 1285 static const soc_reg_t cpu_min_spacing_regs[] = { 1286 MMU_PTSCH_PIPE_PICK_TO_SAME_PORT_CPU_MIN_SPACING_EB0r, 1287 MMU_PTSCH_PIPE_PICK_TO_SAME_PORT_CPU_MIN_SPACING_EB1r, 1288 MMU_PTSCH_PIPE_PICK_TO_SAME_PORT_CPU_MIN_SPACING_EB2r, 1289 MMU_PTSCH_PIPE_PICK_TO_SAME_PORT_CPU_MIN_SPACING_EB3r, 1290 MMU_PTSCH_PIPE_PICK_TO_SAME_PORT_CPU_MIN_SPACING_EB4r, 1291 MMU_PTSCH_PIPE_PICK_TO_SAME_PORT_CPU_MIN_SPACING_EB5r, 1292 MMU_PTSCH_PIPE_PICK_TO_SAME_PORT_CPU_MIN_SPACING_EB6r, 1293 MMU_PTSCH_PIPE_PICK_TO_SAME_PORT_CPU_MIN_SPACING_EB7r 1294 }; 1295 1296 1297 1298 /* Select the right reg based on sched instance */ 1299 skip_instance = 0; 1300 1301 switch (sched_inst_name) { 1302 case TDM_MMU_MAIN_SCHED: 1303 one_cell_reg = MMU_PTSCH_MIN_SPACING_ONE_CELLr; 1304 two_cell_reg = MMU_PTSCH_MIN_SPACING_TWO_CELLr; 1305 three_cell_reg = MMU_PTSCH_MIN_SPACING_THREE_CELLr; 1306 four_cell_reg = MMU_PTSCH_MIN_SPACING_FOUR_CELLr; 1307 pick_to_same_port_pick_reg = MMU_PTSCH_PIPE_PICK_TO_SAME_PORT_PICK_MIN_SPACINGr; 1308 pick_to_same_port_cpu_reg = cpu_min_spacing_regs[pipe_num]; /*MMU_PTSCH_PIPE_PICK_TO_SAME_PORT_CPU_MIN_SPACINGr;*/ 1309 break; 1310 case TDM_IDB_PORT_SCHED: 1311 case TDM_IDB_PKT_SCHED: 1312 case TDM_MMU_EB_PORT_SCHED: 1313 case TDM_MMU_EB_PKT_SCHED: 1314 skip_instance = 1; 1315 break; 1316 default: 1317 LOG_ERROR(BSL_LS_SOC_PORT, (BSL_META_U(unit, 1318 "soc_tomahawk3_tdm_set_min_spacing()" 1319 "Unsupported sched_inst_name\n"))); 1320 return SOC_E_PARAM; 1321 break; 1322 } 1323 1324 if (skip_instance == 1) {return SOC_E_NONE;} 1325 1326 1327 one_cell_50g = (soc_tomahawk3_tdm_min_spacing_settings[0][0].def 1328 * port_schedule_state->frequency) / TH3_TDM_MAX_FREQ; 1329 one_cell_50g = (one_cell_50g < soc_tomahawk3_tdm_min_spacing_settings[0][0].min) 1330 ? soc_tomahawk3_tdm_min_spacing_settings[0][0].min : one_cell_50g; 1331 one_cell_100g = (soc_tomahawk3_tdm_min_spacing_settings[0][1].def 1332 * port_schedule_state->frequency) / TH3_TDM_MAX_FREQ; 1333 one_cell_100g = (one_cell_100g < soc_tomahawk3_tdm_min_spacing_settings[0][1].min) 1334 ? soc_tomahawk3_tdm_min_spacing_settings[0][1].min : one_cell_100g; 1335 one_cell_200g = (soc_tomahawk3_tdm_min_spacing_settings[0][2].def 1336 * port_schedule_state->frequency) / TH3_TDM_MAX_FREQ; 1337 one_cell_200g = (one_cell_200g < soc_tomahawk3_tdm_min_spacing_settings[0][2].min) 1338 ? soc_tomahawk3_tdm_min_spacing_settings[0][2].min : one_cell_200g; 1339 one_cell_400g = (soc_tomahawk3_tdm_min_spacing_settings[0][3].def 1340 * port_schedule_state->frequency) / TH3_TDM_MAX_FREQ; 1341 one_cell_400g = (one_cell_400g < soc_tomahawk3_tdm_min_spacing_settings[0][3].min) 1342 ? soc_tomahawk3_tdm_min_spacing_settings[0][3].min : one_cell_400g; 1343 1344 two_cell_50g = (soc_tomahawk3_tdm_min_spacing_settings[1][0].def 1345 * port_schedule_state->frequency) / TH3_TDM_MAX_FREQ; 1346 two_cell_50g = (two_cell_50g < soc_tomahawk3_tdm_min_spacing_settings[1][0].min) 1347 ? soc_tomahawk3_tdm_min_spacing_settings[1][0].min : two_cell_50g; 1348 two_cell_100g = (soc_tomahawk3_tdm_min_spacing_settings[1][1].def 1349 * port_schedule_state->frequency) / TH3_TDM_MAX_FREQ; 1350 two_cell_100g = (two_cell_100g < soc_tomahawk3_tdm_min_spacing_settings[1][1].min) 1351 ? soc_tomahawk3_tdm_min_spacing_settings[1][1].min : two_cell_100g; 1352 two_cell_200g = (soc_tomahawk3_tdm_min_spacing_settings[1][2].def 1353 * port_schedule_state->frequency) / TH3_TDM_MAX_FREQ; 1354 two_cell_200g = (two_cell_200g < soc_tomahawk3_tdm_min_spacing_settings[1][2].min) 1355 ? soc_tomahawk3_tdm_min_spacing_settings[1][2].min : two_cell_200g; 1356 two_cell_400g = (soc_tomahawk3_tdm_min_spacing_settings[1][3].def 1357 * port_schedule_state->frequency) / TH3_TDM_MAX_FREQ; 1358 two_cell_400g = (two_cell_400g < soc_tomahawk3_tdm_min_spacing_settings[1][3].min) 1359 ? soc_tomahawk3_tdm_min_spacing_settings[1][3].min : two_cell_400g; 1360 1361 three_cell_50g = (soc_tomahawk3_tdm_min_spacing_settings[2][0].def 1362 * port_schedule_state->frequency) / TH3_TDM_MAX_FREQ; 1363 three_cell_50g = (three_cell_50g < soc_tomahawk3_tdm_min_spacing_settings[2][0].min) 1364 ? soc_tomahawk3_tdm_min_spacing_settings[2][0].min : three_cell_50g; 1365 three_cell_100g = (soc_tomahawk3_tdm_min_spacing_settings[2][1].def 1366 * port_schedule_state->frequency) / TH3_TDM_MAX_FREQ; 1367 three_cell_100g = (three_cell_100g < soc_tomahawk3_tdm_min_spacing_settings[2][1].min) 1368 ? soc_tomahawk3_tdm_min_spacing_settings[2][1].min : three_cell_100g; 1369 three_cell_200g = (soc_tomahawk3_tdm_min_spacing_settings[2][2].def 1370 * port_schedule_state->frequency) / TH3_TDM_MAX_FREQ; 1371 three_cell_200g = (three_cell_200g < soc_tomahawk3_tdm_min_spacing_settings[2][2].min) 1372 ? soc_tomahawk3_tdm_min_spacing_settings[2][2].min : three_cell_200g; 1373 three_cell_400g = (soc_tomahawk3_tdm_min_spacing_settings[2][3].def 1374 * port_schedule_state->frequency) / TH3_TDM_MAX_FREQ; 1375 three_cell_400g = (three_cell_400g < soc_tomahawk3_tdm_min_spacing_settings[2][3].min) 1376 ? soc_tomahawk3_tdm_min_spacing_settings[2][3].min : three_cell_400g; 1377 1378 four_cell_50g = (soc_tomahawk3_tdm_min_spacing_settings[3][0].def 1379 * port_schedule_state->frequency) / TH3_TDM_MAX_FREQ; 1380 four_cell_50g = (four_cell_50g < soc_tomahawk3_tdm_min_spacing_settings[3][0].min) 1381 ? soc_tomahawk3_tdm_min_spacing_settings[3][0].min : four_cell_50g; 1382 four_cell_100g = (soc_tomahawk3_tdm_min_spacing_settings[3][1].def 1383 * port_schedule_state->frequency) / TH3_TDM_MAX_FREQ; 1384 four_cell_100g = (four_cell_100g < soc_tomahawk3_tdm_min_spacing_settings[3][1].min) 1385 ? soc_tomahawk3_tdm_min_spacing_settings[3][1].min : four_cell_100g; 1386 four_cell_200g = (soc_tomahawk3_tdm_min_spacing_settings[3][2].def 1387 * port_schedule_state->frequency) / TH3_TDM_MAX_FREQ; 1388 four_cell_200g = (four_cell_200g < soc_tomahawk3_tdm_min_spacing_settings[3][2].min) 1389 ? soc_tomahawk3_tdm_min_spacing_settings[3][2].min : four_cell_200g; 1390 four_cell_400g = (soc_tomahawk3_tdm_min_spacing_settings[3][3].def 1391 * port_schedule_state->frequency) / TH3_TDM_MAX_FREQ; 1392 four_cell_400g = (four_cell_400g < soc_tomahawk3_tdm_min_spacing_settings[3][3].min) 1393 ? soc_tomahawk3_tdm_min_spacing_settings[3][3].min : four_cell_400g; 1394 1395 1396 one_cell_rval = 0; 1397 soc_reg_field_set(unit, one_cell_reg, &one_cell_rval, ONE_CELL_50G_MIN_SPACINGf, 1398 one_cell_50g); 1399 soc_reg_field_set(unit, one_cell_reg, &one_cell_rval, ONE_CELL_100G_MIN_SPACINGf, 1400 one_cell_100g); 1401 soc_reg_field_set(unit, one_cell_reg, &one_cell_rval, ONE_CELL_200G_MIN_SPACINGf, 1402 one_cell_200g); 1403 soc_reg_field_set(unit, one_cell_reg, &one_cell_rval, ONE_CELL_400G_MIN_SPACINGf, 1404 one_cell_400g); 1405 1406 two_cell_rval = 0; 1407 soc_reg_field_set(unit, two_cell_reg, &two_cell_rval, TWO_CELL_50G_MIN_SPACINGf, 1408 two_cell_50g); 1409 soc_reg_field_set(unit, two_cell_reg, &two_cell_rval, TWO_CELL_100G_MIN_SPACINGf, 1410 two_cell_100g); 1411 soc_reg_field_set(unit, two_cell_reg, &two_cell_rval, TWO_CELL_200G_MIN_SPACINGf, 1412 two_cell_200g); 1413 soc_reg_field_set(unit, two_cell_reg, &two_cell_rval, TWO_CELL_400G_MIN_SPACINGf, 1414 two_cell_400g); 1415 1416 three_cell_rval = 0; 1417 soc_reg_field_set(unit, three_cell_reg, &three_cell_rval, THREE_CELL_50G_MIN_SPACINGf, 1418 three_cell_50g); 1419 soc_reg_field_set(unit, three_cell_reg, &three_cell_rval, THREE_CELL_100G_MIN_SPACINGf, 1420 three_cell_100g); 1421 soc_reg_field_set(unit, three_cell_reg, &three_cell_rval, THREE_CELL_200G_MIN_SPACINGf, 1422 three_cell_200g); 1423 soc_reg_field_set(unit, three_cell_reg, &three_cell_rval, THREE_CELL_400G_MIN_SPACINGf, 1424 three_cell_400g); 1425 1426 four_cell_rval = 0; 1427 soc_reg_field_set(unit, four_cell_reg, &four_cell_rval, FOUR_CELL_50G_MIN_SPACINGf, 1428 four_cell_50g); 1429 soc_reg_field_set(unit, four_cell_reg, &four_cell_rval, FOUR_CELL_100G_MIN_SPACINGf, 1430 four_cell_100g); 1431 soc_reg_field_set(unit, four_cell_reg, &four_cell_rval, FOUR_CELL_200G_MIN_SPACINGf, 1432 four_cell_200g); 1433 soc_reg_field_set(unit, four_cell_reg, &four_cell_rval, FOUR_CELL_400G_MIN_SPACINGf, 1434 four_cell_400g); 1435 1436 1437 switch (sched_inst_name) { 1438 case TDM_MMU_MAIN_SCHED: 1439 inst = pipe_num | SOC_REG_ADDR_INSTANCE_MASK; 1440 SOC_IF_ERROR_RETURN(soc_reg32_set( 1441 unit, one_cell_reg, inst, 0, one_cell_rval)); 1442 SOC_IF_ERROR_RETURN(soc_reg32_set( 1443 unit, two_cell_reg, inst, 0, two_cell_rval)); 1444 SOC_IF_ERROR_RETURN(soc_reg32_set( 1445 unit, three_cell_reg, inst, 0, three_cell_rval)); 1446 SOC_IF_ERROR_RETURN(soc_reg32_set( 1447 unit, four_cell_reg, inst, 0, four_cell_rval)); 1448 break; 1449 default: 1450 LOG_ERROR(BSL_LS_SOC_PORT, (BSL_META_U(unit, 1451 "soc_tomahawk3_tdm_set_min_spacing()" 1452 "Unsupported sched_inst_name 2nd\n"))); 1453 return SOC_E_PARAM; 1454 break; 1455 } 1456 1457 switch (sched_inst_name) { 1458 case TDM_MMU_MAIN_SCHED: 1459 inst = pipe_num | SOC_REG_ADDR_INSTANCE_MASK; 1460 1461 SOC_IF_ERROR_RETURN(soc_reg64_get( 1462 unit, pick_to_same_port_pick_reg, inst, 0, 1463 &pick_to_same_port_pick_val)); 1464 COMPILER_64_SET(pick_min_four_cell_50g, 0, 2); 1465 COMPILER_64_SET(pick_min_four_cell_100g, 0, 2); 1466 COMPILER_64_SET(pick_min_one_to_three_cell_50g, 0, 2); 1467 COMPILER_64_SET(pick_min_one_to_three_cell_100g, 0, 2); 1468 soc_reg64_field_set(unit, pick_to_same_port_pick_reg, 1469 &pick_to_same_port_pick_val, 1470 FOUR_CELL_50G_SPACINGf, pick_min_four_cell_50g); 1471 soc_reg64_field_set(unit, pick_to_same_port_pick_reg, 1472 &pick_to_same_port_pick_val, 1473 FOUR_CELL_100G_SPACINGf, pick_min_four_cell_100g); 1474 soc_reg64_field_set(unit, pick_to_same_port_pick_reg, 1475 &pick_to_same_port_pick_val, 1476 ONE_TO_THREE_CELL_50G_SPACINGf, pick_min_one_to_three_cell_50g); 1477 soc_reg64_field_set(unit, pick_to_same_port_pick_reg, 1478 &pick_to_same_port_pick_val, 1479 ONE_TO_THREE_CELL_100G_SPACINGf, pick_min_one_to_three_cell_100g); 1480 SOC_IF_ERROR_RETURN(soc_reg64_set( 1481 unit, pick_to_same_port_pick_reg, inst, 0, 1482 pick_to_same_port_pick_val)); 1483 1484 if ((pipe_num == 1) || 1485 (pipe_num == 5)) { /* that is, MGM ports */ 1486 SOC_IF_ERROR_RETURN(soc_reg32_get( 1487 unit, pick_to_same_port_cpu_reg, REG_PORT_ANY, 0, 1488 &pick_to_same_port_cpu_val)); 1489 pick_min_four_cell_cpu = 2; 1490 pick_min_one_to_three_cell_cpu = 2; 1491 soc_reg_field_set(unit, pick_to_same_port_cpu_reg, 1492 &pick_to_same_port_cpu_val, 1493 FOUR_CELL_CPU_SPACINGf, pick_min_four_cell_cpu); 1494 soc_reg_field_set(unit, pick_to_same_port_cpu_reg, 1495 &pick_to_same_port_cpu_val, 1496 ONE_TO_THREE_CELL_CPU_SPACINGf, pick_min_one_to_three_cell_cpu); 1497 SOC_IF_ERROR_RETURN(soc_reg32_set( 1498 unit, pick_to_same_port_cpu_reg, REG_PORT_ANY, 0, 1499 pick_to_same_port_cpu_val)); 1500 } 1501 break; 1502 default: 1503 LOG_ERROR(BSL_LS_SOC_PORT, (BSL_META_U(unit, 1504 "soc_tomahawk3_tdm_set_min_spacing()" 1505 "Unsupported sched_inst_name 2nd\n"))); 1506 return SOC_E_PARAM; 1507 break; 1508 } 1509 1510 return SOC_E_NONE; 1511 } 1512 1513 /*! @fn int soc_tomahawk3_tdm_set_min_port_pick_spacing( 1514 * int unit, 1515 * soc_port_schedule_state_t *port_schedule_state, 1516 * tdm_sched_inst_name_e sched_inst_name, 1517 * int pipe_num) 1518 * @param unit Chip unit number. 1519 * @param port_schedule_state Pointer to a soc_port_schedule_state_t 1520 * struct variable. 1521 * @param sched_inst_name name enum of instance 1522 * @param pipe pipe number. 1523 * @brief API to initialize MIN_PORT_PICK_SPACING_WITHIN_PKT 1524 * Description: 1525 * API to initialize MIN_PORT_PICK_SPACING_WITHIN_PKT 1526 * Regs/Mems configured: IDB/MMU SCHED 1527 * Parameters: 1528 * unit - Device number 1529 * *port_schedule_state_t - Agreed structure between SDK and DV 1530 * Return Value: 1531 * SOC_E_* 1532 */ 1533 int soc_tomahawk3_tdm_set_min_port_pick_spacing( 1534 int unit, 1535 soc_port_schedule_state_t *port_schedule_state, 1536 tdm_sched_inst_name_e sched_inst_name, 1537 int pipe_num) 1538 { 1539 int mid_pkt_50g_min_spacing; 1540 int mid_pkt_100g_min_spacing; 1541 int mid_pkt_200g_min_spacing; 1542 int mid_pkt_400g_min_spacing; 1543 uint32 rval; 1544 int skip_instance; 1545 soc_reg_t reg; 1546 1547 static const soc_reg_t idb_min_port_pick_regs[] = { 1548 IS_MIN_PORT_PICK_SPACING_WITHIN_PKT_PIPE0r, IS_MIN_PORT_PICK_SPACING_WITHIN_PKT_PIPE1r, 1549 IS_MIN_PORT_PICK_SPACING_WITHIN_PKT_PIPE2r, IS_MIN_PORT_PICK_SPACING_WITHIN_PKT_PIPE3r, 1550 IS_MIN_PORT_PICK_SPACING_WITHIN_PKT_PIPE4r, IS_MIN_PORT_PICK_SPACING_WITHIN_PKT_PIPE5r, 1551 IS_MIN_PORT_PICK_SPACING_WITHIN_PKT_PIPE6r, IS_MIN_PORT_PICK_SPACING_WITHIN_PKT_PIPE7r 1552 }; 1553 1554 /* Select the right reg based on sched instance */ 1555 skip_instance = 0; 1556 switch (sched_inst_name) { 1557 case TDM_IDB_PORT_SCHED: 1558 reg = idb_min_port_pick_regs[pipe_num]; 1559 break; 1560 case TDM_MMU_EB_PORT_SCHED: 1561 case TDM_IDB_PKT_SCHED: 1562 case TDM_MMU_MAIN_SCHED: 1563 case TDM_MMU_EB_PKT_SCHED: 1564 skip_instance = 1; 1565 break; 1566 default: 1567 LOG_ERROR(BSL_LS_SOC_PORT, (BSL_META_U(unit, 1568 "soc_tomahawk3_tdm_set_min_port_pick_spacing()" 1569 "Unsupported sched_inst_name\n"))); 1570 return SOC_E_PARAM; 1571 break; 1572 } 1573 1574 if (skip_instance == 1) {return SOC_E_NONE;} 1575 1576 if(port_schedule_state->frequency > 1000) { 1577 mid_pkt_50g_min_spacing = 12; 1578 mid_pkt_100g_min_spacing = 12; 1579 mid_pkt_200g_min_spacing = 8; 1580 mid_pkt_400g_min_spacing = 4; 1581 } else { 1582 mid_pkt_50g_min_spacing = 11; 1583 mid_pkt_100g_min_spacing = 11; 1584 mid_pkt_200g_min_spacing = 5; 1585 mid_pkt_400g_min_spacing = 4; 1586 } 1587 1588 rval = 0; 1589 soc_reg_field_set(unit, reg, &rval, MID_PKT_50G_MIN_SPACINGf, mid_pkt_50g_min_spacing); 1590 soc_reg_field_set(unit, reg, &rval, MID_PKT_100G_MIN_SPACINGf, mid_pkt_100g_min_spacing); 1591 soc_reg_field_set(unit, reg, &rval, MID_PKT_200G_MIN_SPACINGf, mid_pkt_200g_min_spacing); 1592 soc_reg_field_set(unit, reg, &rval, MID_PKT_400G_MIN_SPACINGf, mid_pkt_400g_min_spacing); 1593 1594 1595 switch (sched_inst_name) { 1596 case TDM_IDB_PORT_SCHED: 1597 SOC_IF_ERROR_RETURN(soc_reg32_set( 1598 unit, reg, REG_PORT_ANY, 0, rval)); 1599 break; 1600 default: 1601 LOG_ERROR(BSL_LS_SOC_PORT, (BSL_META_U(unit, 1602 "soc_tomahawk3_tdm_set_min_port_pick_spacing()" 1603 "Unsupported sched_inst_name 2nd \n"))); 1604 return SOC_E_PARAM; 1605 break; 1606 } 1607 1608 return SOC_E_NONE; 1609 } 1610 1611 1612 1613 1614 /*! @fn int soc_tomahawk3_tdm_set_mmu_edb_credit_threshold( 1615 * int unit, 1616 * soc_port_schedule_state_t *port_schedule_state, 1617 * tdm_sched_inst_name_e sched_inst_name, 1618 * int pipe_num) 1619 * @param unit Chip unit number. 1620 * @param port_schedule_state Pointer to a soc_port_schedule_state_t 1621 * struct variable. 1622 * @param sched_inst_name name enum of instance 1623 * @param pipe pipe number. 1624 * @brief API to initialize/clear per port EDB_PORT_CREDIT_THRESHOLD_0/1 1625 * Description: 1626 * API to initialize/clear per port EDB_PORT_CREDIT_THRESHOLD_0/1 1627 * Regs/Mems configured: MMU EB PRT SCHED 1628 * Parameters: 1629 * unit - Device number 1630 * *port_schedule_state_t - Agreed structure between SDK and DV 1631 * Return Value: 1632 * SOC_E_* 1633 */ 1634 int soc_tomahawk3_tdm_set_mmu_edb_credit_threshold( 1635 int unit, 1636 soc_port_schedule_state_t *port_schedule_state, 1637 tdm_sched_inst_name_e sched_inst_name, 1638 int pipe_num) 1639 { 1640 int edb_credit_threshold_50g; 1641 int edb_credit_threshold_100g; 1642 int edb_credit_threshold_200g; 1643 int edb_credit_threshold_400g; 1644 int skip_instance; 1645 int inst; 1646 uint32 rval_0, rval_1; 1647 soc_reg_t reg_0, reg_1; 1648 1649 1650 /* Select the right reg based on sched instance */ 1651 skip_instance = 0; 1652 switch (sched_inst_name) { 1653 case TDM_MMU_EB_PORT_SCHED: 1654 reg_0 = MMU_EBPTS_EDB_PORT_CREDIT_THRESHOLD_0r; 1655 reg_1 = MMU_EBPTS_EDB_PORT_CREDIT_THRESHOLD_1r; 1656 break; 1657 case TDM_IDB_PORT_SCHED: 1658 case TDM_IDB_PKT_SCHED: 1659 case TDM_MMU_MAIN_SCHED: 1660 case TDM_MMU_EB_PKT_SCHED: 1661 skip_instance = 1; 1662 break; 1663 default: 1664 LOG_ERROR(BSL_LS_SOC_PORT, (BSL_META_U(unit, 1665 "soc_tomahawk3_tdm_set_mmu_edb_credit_threshold()" 1666 "Unsupported sched_inst_name\n"))); 1667 return SOC_E_PARAM; 1668 break; 1669 } 1670 1671 if (skip_instance == 1) {return SOC_E_NONE;} 1672 1673 /* 50% from EDB to MMU CREDITs for that speed 1674 */ 1675 SOC_IF_ERROR_RETURN(soc_tomahawk3_ep_get_ep2mmu_credit_per_speed( 1676 unit, port_schedule_state, SPEED_50G, &edb_credit_threshold_50g)); 1677 edb_credit_threshold_50g = edb_credit_threshold_50g / 2; 1678 SOC_IF_ERROR_RETURN(soc_tomahawk3_ep_get_ep2mmu_credit_per_speed( 1679 unit, port_schedule_state, SPEED_100G, &edb_credit_threshold_100g)); 1680 edb_credit_threshold_100g = edb_credit_threshold_100g / 2; 1681 SOC_IF_ERROR_RETURN(soc_tomahawk3_ep_get_ep2mmu_credit_per_speed( 1682 unit, port_schedule_state, SPEED_200G, &edb_credit_threshold_200g)); 1683 edb_credit_threshold_200g = edb_credit_threshold_200g / 2; 1684 SOC_IF_ERROR_RETURN(soc_tomahawk3_ep_get_ep2mmu_credit_per_speed( 1685 unit, port_schedule_state, SPEED_400G, &edb_credit_threshold_400g)); 1686 edb_credit_threshold_400g = edb_credit_threshold_400g / 2; 1687 1688 rval_0 = 0; 1689 rval_1 = 0; 1690 soc_reg_field_set(unit, reg_0, &rval_0, EDB_CREDIT_THRESHOLD_50Gf, 1691 edb_credit_threshold_50g); 1692 soc_reg_field_set(unit, reg_0, &rval_0, EDB_CREDIT_THRESHOLD_100Gf, 1693 edb_credit_threshold_100g); 1694 soc_reg_field_set(unit, reg_1, &rval_1, EDB_CREDIT_THRESHOLD_200Gf, 1695 edb_credit_threshold_200g); 1696 soc_reg_field_set(unit, reg_1, &rval_1, EDB_CREDIT_THRESHOLD_400Gf, 1697 edb_credit_threshold_400g); 1698 1699 switch (sched_inst_name) { 1700 case TDM_MMU_EB_PORT_SCHED: 1701 inst = pipe_num | SOC_REG_ADDR_INSTANCE_MASK; 1702 SOC_IF_ERROR_RETURN(soc_reg32_set( 1703 unit, reg_0, inst, 0, rval_0)); 1704 SOC_IF_ERROR_RETURN(soc_reg32_set( 1705 unit, reg_1, inst, 0, rval_1)); 1706 break; 1707 default: 1708 LOG_ERROR(BSL_LS_SOC_PORT, (BSL_META_U(unit, 1709 "soc_tomahawk3_tdm_set_mmu_edb_credit_threshold()" 1710 "Unsupported sched_inst_name 2nd\n"))); 1711 return SOC_E_PARAM; 1712 break; 1713 } 1714 1715 return SOC_E_NONE; 1716 } 1717 1718 1719 1720 /*! @fn int soc_tomahawk3_tdm_global_to_local_phy_num( 1721 * int phy_port, 1722 * int *local_phy_num) 1723 * @param phy_port phy_port to configure. 1724 * @param *local_phy_num local phy number. 1725 * @brief API to get local physical number based on global physical number 1726 * Description: 1727 * API to get local physical number based on global physical number 1728 * Return Value: 1729 * SOC_E_* 1730 */ 1731 STATIC int soc_tomahawk3_tdm_global_to_local_phy_num( 1732 int phy_port, 1733 int *local_phy_num) 1734 { 1735 *local_phy_num = 0x3f; 1736 1737 if ((0 <= phy_port) && (phy_port <= _TH3_GPHY_PORTS_PER_PIPE)) { 1738 *local_phy_num = phy_port; 1739 } else if (((_TH3_GPHY_PORTS_PER_PIPE + 1) <= phy_port) && 1740 (phy_port <= (_TH3_GPHY_PORTS_PER_PIPE * _TH3_PIPES_PER_DEV))) { 1741 *local_phy_num = ((phy_port - 1) % _TH3_GPHY_PORTS_PER_PIPE); 1742 } else if ((_TH3_PHY_PORT_MNG0 <= phy_port) && (phy_port <= _TH3_PHY_PORT_MNG1)) { 1743 *local_phy_num = 32; 1744 } else if ((_TH3_PHY_PORT_LPBK0 <= phy_port) && (phy_port <= _TH3_PHY_PORT_LPBK7)) { 1745 *local_phy_num = 33; 1746 } else { 1747 return SOC_E_PARAM; 1748 } 1749 1750 return SOC_E_NONE; 1751 } 1752 1753 1754 /*! @fn int soc_tomahawk3_tdm_set_mmu_port_to_phy_port_mapping( 1755 * int unit, 1756 * soc_port_schedule_state_t *port_schedule_state, 1757 * tdm_sched_inst_name_e sched_inst_name, 1758 * int pipe, 1759 * int phy_port, 1760 * int is_port_down) 1761 * @param unit Chip unit number. 1762 * @param port_schedule_state Pointer to a soc_port_schedule_state_t 1763 * struct variable. 1764 * @param sched_inst_name name enum of instance 1765 * @param pipe pipe number. 1766 * @param phy_port phy_port to configure. 1767 * @param phy_port is_port_down. boolean to indicate if port down 1768 * @brief API to initialize/clear per port MMU_PORT_TO_PHY_PORT_MAPPING 1769 * Description: 1770 * API to initialize/clear per port MMU_PORT_TO_PHY_PORT_MAPPING 1771 * Regs/Mems configured: MMU EB PRT 1772 * Parameters: 1773 * unit - Device number 1774 * *port_schedule_state_t - Agreed structure between SDK and DV 1775 * Return Value: 1776 * SOC_E_* 1777 */ 1778 int soc_tomahawk3_tdm_set_mmu_port_to_phy_port_mapping( 1779 int unit, 1780 soc_port_schedule_state_t *port_schedule_state, 1781 tdm_sched_inst_name_e sched_inst_name, 1782 int pipe_num, 1783 int phy_port, 1784 int is_port_down) 1785 { 1786 int mmu_port; 1787 int phy_port_num; 1788 soc_port_map_type_t *port_map; 1789 int skip_instance; 1790 int inst; 1791 uint32 rval; 1792 uint64 rval64; 1793 soc_reg_t reg; 1794 1795 skip_instance = 0; 1796 switch (sched_inst_name) { 1797 case TDM_MMU_EB_PORT_SCHED: 1798 reg = MMU_EBPTS_MMU_PORT_TO_PHY_PORT_MAPPINGr; 1799 break; 1800 case TDM_IDB_PORT_SCHED: 1801 case TDM_IDB_PKT_SCHED: 1802 case TDM_MMU_MAIN_SCHED: 1803 case TDM_MMU_EB_PKT_SCHED: 1804 skip_instance = 1; 1805 break; 1806 default: 1807 LOG_ERROR(BSL_LS_SOC_PORT, (BSL_META_U(unit, 1808 "soc_tomahawk3_tdm_set_mmu_port_to_phy_port_mapping()" 1809 "Unsupported sched_inst_name\n"))); 1810 return SOC_E_PARAM; 1811 break; 1812 } 1813 1814 /* Only MMU main prt scheduler gets this reg configured */ 1815 if (skip_instance == 1) {return SOC_E_NONE;} 1816 1817 /* Set reg's variables */ 1818 if (is_port_down == 1) { /* in_port_map used at port down */ 1819 port_map = &port_schedule_state->in_port_map; 1820 } else { /* out_port_map used at port up */ 1821 port_map = &port_schedule_state->out_port_map; 1822 } 1823 1824 mmu_port = port_map->port_p2m_mapping[phy_port]; 1825 1826 if (is_port_down == 1) { 1827 phy_port_num = 0x3f; 1828 } else { 1829 SOC_IF_ERROR_RETURN(soc_tomahawk3_tdm_global_to_local_phy_num(phy_port, &phy_port_num)); 1830 } 1831 1832 rval = 0; 1833 soc_reg_field_set(unit, reg, &rval, PHY_PORT_NUMf, 1834 phy_port_num); 1835 1836 switch (sched_inst_name) { 1837 case TDM_MMU_EB_PORT_SCHED: 1838 inst = mmu_port; 1839 COMPILER_64_SET(rval64, 0, rval); 1840 SOC_IF_ERROR_RETURN(soc_reg_rawport_set(unit, reg, inst, 0, rval64)); 1841 break; 1842 default: 1843 LOG_ERROR(BSL_LS_SOC_PORT, (BSL_META_U(unit, 1844 "soc_tomahawk3_tdm_set_mmu_port_to_phy_port_mapping()" 1845 "Unsupported sched_inst_name 2nd\n"))); 1846 return SOC_E_PARAM; 1847 break; 1848 } 1849 1850 return SOC_E_NONE; 1851 } 1852 1853 1854 /*! @fn int soc_tomahawk3_tdm_set_out_port_map(int unit, 1855 * soc_port_schedule_state_t *port_schedule_state) 1856 * @param unit Chip unit number. 1857 * @param port_schedule_state Pointer to a soc_port_schedule_state_t struct variable 1858 * @brief Helper function to calculate port_schedule_state->out_port_map from 1859 * port_schedule_state->out_port_map and port_schedule_state->resource[] 1860 * Description: 1861 * Helper function 1862 * Parameters: 1863 * unit - Device number 1864 * *port_schedule_state_t - Agreed structure between SDK and DV 1865 * Return Value: 1866 * SOC_E_* 1867 */ 1868 int 1869 soc_tomahawk3_tdm_set_out_port_map( 1870 int unit, 1871 soc_port_schedule_state_t *port_schedule_state) 1872 { 1873 int i, logical_port, physical_port; 1874 int prev_physical_port, prev_mmu_port; 1875 1876 /* Copy in_port_map in out_port_map */ 1877 for (i= 0; i< SOC_MAX_NUM_PORTS; i++) { 1878 port_schedule_state->out_port_map.log_port_speed[i] = 1879 port_schedule_state->in_port_map.log_port_speed[i]; 1880 port_schedule_state->out_port_map.port_num_lanes[i] = 1881 port_schedule_state->in_port_map.port_num_lanes[i]; 1882 } 1883 1884 sal_memcpy(port_schedule_state->out_port_map.port_p2l_mapping, 1885 port_schedule_state->in_port_map.port_p2l_mapping, 1886 sizeof(int) * SOC_MAX_NUM_PORTS); 1887 sal_memcpy(port_schedule_state->out_port_map.port_l2p_mapping, 1888 port_schedule_state->in_port_map.port_l2p_mapping, 1889 sizeof(int) * SOC_MAX_NUM_PORTS); 1890 sal_memcpy(port_schedule_state->out_port_map.port_p2m_mapping, 1891 port_schedule_state->in_port_map.port_p2m_mapping, 1892 sizeof(int) * SOC_MAX_NUM_PORTS); 1893 sal_memcpy(port_schedule_state->out_port_map.port_m2p_mapping, 1894 port_schedule_state->in_port_map.port_m2p_mapping, 1895 sizeof(int) * SOC_MAX_NUM_MMU_PORTS); 1896 sal_memcpy(port_schedule_state->out_port_map.port_l2i_mapping, 1897 port_schedule_state->in_port_map.port_l2i_mapping, 1898 sizeof(int) * SOC_MAX_NUM_PORTS); 1899 1900 sal_memcpy(&port_schedule_state->out_port_map.physical_pbm, 1901 &port_schedule_state->in_port_map.physical_pbm, sizeof(pbmp_t)); 1902 sal_memcpy(&port_schedule_state->out_port_map.hg2_pbm, 1903 &port_schedule_state->in_port_map.hg2_pbm, sizeof(pbmp_t)); 1904 sal_memcpy(&port_schedule_state->out_port_map.management_pbm, 1905 &port_schedule_state->in_port_map.management_pbm, sizeof(pbmp_t)); 1906 sal_memcpy(&port_schedule_state->out_port_map.oversub_pbm, 1907 &port_schedule_state->in_port_map.oversub_pbm, sizeof(pbmp_t)); 1908 1909 1910 if (1 == port_schedule_state->is_flexport) { 1911 /* Update for ports that are down 1912 * Remove all the mappings and bitmaps 1913 */ 1914 for (i = 0; i < port_schedule_state->nport; i++) { 1915 logical_port = port_schedule_state->resource[i].logical_port; 1916 physical_port = port_schedule_state->resource[i].physical_port; 1917 if (-1 == physical_port) { /* that is, port down */ 1918 port_schedule_state->out_port_map.log_port_speed[logical_port] = 0; 1919 port_schedule_state->out_port_map.port_num_lanes[logical_port] = 0; 1920 /* Remove previous log_port to phy_port mapping */ 1921 port_schedule_state->out_port_map.port_l2p_mapping[logical_port] = -1; 1922 /* Remove previous log_port to idb_port mapping */ 1923 port_schedule_state->out_port_map.port_l2i_mapping[logical_port] = -1; 1924 /* Remove previous phy_port to log_port mapping */ 1925 prev_physical_port = 1926 port_schedule_state->in_port_map.port_l2p_mapping[logical_port]; 1927 port_schedule_state->out_port_map.port_p2l_mapping[prev_physical_port] = -1; 1928 /* Remove previous phy_port to mmu_port mapping */ 1929 port_schedule_state->out_port_map.port_p2m_mapping[prev_physical_port] = -1; 1930 /* Remove previous mmu_port to phy_port mapping */ 1931 prev_mmu_port = 1932 port_schedule_state->in_port_map.port_p2m_mapping[prev_physical_port]; 1933 port_schedule_state->out_port_map.port_m2p_mapping[prev_mmu_port] = -1; 1934 /* Remove corresponding bitmaps */ 1935 SOC_PBMP_PORT_REMOVE( 1936 port_schedule_state->out_port_map.physical_pbm, 1937 prev_physical_port); 1938 SOC_PBMP_PORT_REMOVE(port_schedule_state->out_port_map.hg2_pbm, 1939 logical_port); 1940 SOC_PBMP_PORT_REMOVE( 1941 port_schedule_state->out_port_map.oversub_pbm, logical_port); 1942 SOC_PBMP_PORT_REMOVE( 1943 port_schedule_state->out_port_map.management_pbm, 1944 logical_port); /* That's optional */ 1945 } 1946 } 1947 1948 /* Update for ports that are brought up */ 1949 for (i = 0; i < port_schedule_state->nport; i++) { 1950 logical_port = port_schedule_state->resource[i].logical_port; 1951 physical_port = port_schedule_state->resource[i].physical_port; 1952 if (-1 != physical_port) { /* that is, port up */ 1953 port_schedule_state->out_port_map.log_port_speed[logical_port] 1954 = port_schedule_state->resource[i].speed; 1955 port_schedule_state->out_port_map.port_num_lanes[logical_port] 1956 = port_schedule_state->resource[i].num_lanes; 1957 /* Add log_port to phy_port mapping */ 1958 port_schedule_state->out_port_map.port_l2p_mapping[logical_port] 1959 = physical_port; 1960 /* Add log_port to idb_port mapping */ 1961 port_schedule_state->out_port_map.port_l2i_mapping[logical_port] 1962 = port_schedule_state->resource[i].idb_port; 1963 /* Add phy_port to log_port mapping */ 1964 port_schedule_state->out_port_map.port_p2l_mapping[physical_port] 1965 = logical_port; 1966 /* Add phy_port to mmu_port mapping */ 1967 port_schedule_state->out_port_map.port_p2m_mapping[physical_port] 1968 = port_schedule_state->resource[i].mmu_port; 1969 /* Add mmu_port to phy_port mapping */ 1970 port_schedule_state->out_port_map.port_m2p_mapping[ 1971 port_schedule_state->resource[i].mmu_port] = physical_port; 1972 /* Add corresponding bitbams */ 1973 SOC_PBMP_PORT_ADD( 1974 port_schedule_state->out_port_map.physical_pbm, 1975 physical_port); 1976 if (_SHR_PORT_ENCAP_HIGIG2 == 1977 port_schedule_state->resource[i].encap) { 1978 SOC_PBMP_PORT_ADD(port_schedule_state->out_port_map.hg2_pbm, 1979 logical_port); 1980 } 1981 if (1 == port_schedule_state->resource[i].oversub) { 1982 SOC_PBMP_PORT_ADD( 1983 port_schedule_state->out_port_map.oversub_pbm, 1984 logical_port); 1985 } 1986 if ((_TH3_PHY_PORT_MNG0 == physical_port) || 1987 (_TH3_PHY_PORT_MNG1 == physical_port) ) { 1988 SOC_PBMP_PORT_ADD( 1989 port_schedule_state->out_port_map.management_pbm, 1990 logical_port); /* That's optional */ 1991 } 1992 } 1993 } 1994 } 1995 1996 return SOC_E_NONE; 1997 } 1998 1999 2000 /*! @fn void soc_tomahawk3_get_pipe_map(int unit, 2001 * soc_port_schedule_state_t *port_schedule_state, uint32 *pipe_map) 2002 * @param unit Chip unit number. 2003 * @param port_schedule_state Pointer to a soc_port_schedule_state_t struct 2004 * variable. 2005 * @param pipe_map Returned pipe map. 2006 * @brief Handler that returns pipe map 2007 * Description: 2008 * Gets pipe map; 2009 * If init ,then a pipe gets 1 if any port active within that pipe 2010 * If flexport, then a pipe gets 1 if any port flexes (UP/DOWN) within that pipe 2011 * Parameters: 2012 * unit - Device number 2013 * *port_schedule_state_t - Agreed structure between SDK and DV 2014 * *pipe_map - returned pipe map 2015 * Return Value: 2016 * SOC_E_* 2017 */ 2018 void 2019 soc_tomahawk3_get_pipe_map( 2020 int unit, 2021 soc_port_schedule_state_t *port_schedule_state, 2022 uint32 * pipe_map) 2023 { 2024 uint32 port, pipe, i; 2025 2026 *pipe_map = 0; 2027 if (port_schedule_state->is_flexport == 0) { /* Init */ 2028 for (port = 0; port < _TH3_DEV_PORTS_PER_DEV; port++) { 2029 if (port_schedule_state->out_port_map.log_port_speed[port] > 0 ) { 2030 pipe = port / _TH3_DEV_PORTS_PER_PIPE; 2031 *pipe_map |= 1 << pipe; 2032 } 2033 } 2034 } else { /* FlexPort */ 2035 for (i = 0; i < port_schedule_state->nport; i++) { 2036 port = port_schedule_state->resource[i].logical_port; 2037 pipe = port / _TH3_DEV_PORTS_PER_PIPE; 2038 *pipe_map |= 1 << pipe; 2039 } 2040 } 2041 } 2042 2043 2044 /*! @fn int soc_tomahawk3_tdm_sched_init(int unit, 2045 * soc_port_schedule_state_t *port_schedule_state 2046 * tdm_sched_inst_name_e sched_inst_name ) 2047 * @param unit Chip unit number. 2048 * @param port_schedule_state Pointer to a soc_port_schedule_state_t 2049 * struct variable. 2050 * @param sched_inst_name Instance name enum. 2051 * @brief API to initialize the TH3 scheduler instance. 2052 * Description: 2053 * API to initialize the TH3 scheduler instance. 2054 * Regs/Mems configured: TH3 scheduler instance. 2055 * Parameters: 2056 * unit - Device number 2057 * *port_schedule_state_t - Agreed structure between SDK and DV 2058 * Return Value: 2059 * SOC_E_* 2060 */ 2061 int soc_tomahawk3_tdm_sched_init( 2062 int unit, 2063 soc_port_schedule_state_t *port_schedule_state, 2064 tdm_sched_inst_name_e sched_inst_name) 2065 { 2066 uint32 port, pipe; 2067 uint32 pipe_map; 2068 int phy_port; 2069 int is_port_down; 2070 2071 is_port_down = 0; 2072 soc_tomahawk3_get_pipe_map(unit, port_schedule_state, &pipe_map); 2073 2074 /* Configure per port registers */ 2075 for (port = 0; port < _TH3_DEV_PORTS_PER_DEV; port++) { 2076 if (port_schedule_state->out_port_map.log_port_speed[port] > 0 ) { 2077 pipe = port / _TH3_DEV_PORTS_PER_PIPE; 2078 phy_port = port_schedule_state->out_port_map.port_l2p_mapping[port]; 2079 if (_TH3_PHY_IS_FRONT_PANEL_PORT(phy_port)) { 2080 soc_tomahawk3_tdm_set_cal_config(unit, port_schedule_state, 2081 sched_inst_name, pipe, phy_port, is_port_down); 2082 soc_tomahawk3_tdm_set_ebshp_port_cfg(unit, port_schedule_state, 2083 sched_inst_name, pipe, phy_port, is_port_down); /* MMU EB PRT scheduler */ 2084 } 2085 /* This is for MMU schedulers; they will be skipped for IDB or PKT schedulers */ 2086 soc_tomahawk3_tdm_set_eb_credit_config(unit, port_schedule_state, 2087 sched_inst_name, pipe, phy_port, is_port_down); /* MMU MAIN PRT scheduler */ 2088 soc_tomahawk3_tdm_set_mmu_port_to_phy_port_mapping(unit, port_schedule_state, 2089 sched_inst_name, pipe, phy_port, is_port_down); /* MMU EB PRT scheduler */ 2090 } 2091 } 2092 2093 /* Per pipe configs; at init time only; not part of FlexPort */ 2094 for (pipe = 0; pipe < _TH3_PIPES_PER_DEV; pipe++) { 2095 if (!(pipe_map & (1 << pipe))) { 2096 continue; 2097 } 2098 /* Configure special slot in CALC_CONFIG */ 2099 soc_tomahawk3_tdm_set_cal_config(unit, port_schedule_state, 2100 sched_inst_name, pipe, (SOC_MAX_NUM_PORTS + 1), is_port_down); 2101 /* Takes effect only in IDB/MMU_EB PRT SCHED*/ 2102 soc_tomahawk3_tdm_set_max_spacing(unit, 2103 port_schedule_state, sched_inst_name, pipe); 2104 soc_tomahawk3_tdm_set_feature_ctrl(unit, 2105 port_schedule_state, sched_inst_name, pipe); 2106 soc_tomahawk3_tdm_set_cbmg_value(unit, 2107 port_schedule_state, sched_inst_name, pipe); 2108 /* Takes effect only in MMU MAIN PRT scheduler */ 2109 soc_tomahawk3_tdm_set_eb_satisfied_threshold(unit, 2110 port_schedule_state, sched_inst_name, pipe); 2111 soc_tomahawk3_tdm_set_min_spacing(unit, 2112 port_schedule_state, sched_inst_name, pipe); 2113 /* Takes effect only in IDB PRT scheduler */ 2114 soc_tomahawk3_tdm_set_min_port_pick_spacing(unit, 2115 port_schedule_state, sched_inst_name, pipe); 2116 /* Takes effect only in MMU EB PRT scheduler */ 2117 soc_tomahawk3_tdm_set_mmu_edb_credit_threshold(unit, 2118 port_schedule_state, sched_inst_name, pipe); 2119 /* Takes effect only in MMU EB PRT scheduler */ 2120 soc_tomahawk3_tdm_set_urg_cell_spacing(unit, 2121 port_schedule_state, sched_inst_name, pipe); 2122 /* Takes effect only in PKT SCH*/ 2123 soc_tomahawk3_tdm_set_pksch_pkt_credits_per_pipe(unit, 2124 port_schedule_state, sched_inst_name, pipe); 2125 } 2126 2127 return SOC_E_NONE; 2128 } 2129 2130 2131 /*! @fn int soc_tomahawk3_tdm_idb_init(int unit, 2132 * soc_port_schedule_state_t *port_schedule_state) 2133 * @param unit Chip unit number. 2134 * @param port_schedule_state Pointer to a soc_port_schedule_state_t 2135 * struct variable. 2136 * @brief API to initialize the TH3 IDB schedulers. 2137 * Description: 2138 * API to initialize the TH3 IDB schedulers. 2139 * Regs/Mems configured: TH3 IDB schedulers. 2140 * Parameters: 2141 * unit - Device number 2142 * *port_schedule_state_t - Agreed structure between SDK and DV 2143 * Return Value: 2144 * SOC_E_* 2145 */ 2146 int soc_tomahawk3_tdm_idb_init( 2147 int unit, 2148 soc_port_schedule_state_t *port_schedule_state) 2149 { 2150 2151 SOC_IF_ERROR_RETURN(soc_tomahawk3_tdm_set_out_port_map( 2152 unit, port_schedule_state)); 2153 SOC_IF_ERROR_RETURN(soc_tomahawk3_set_tdm_tbl( 2154 unit, port_schedule_state)); 2155 2156 SOC_IF_ERROR_RETURN(soc_tomahawk3_tdm_sched_init( 2157 unit, port_schedule_state, TDM_IDB_PORT_SCHED)); 2158 SOC_IF_ERROR_RETURN(soc_tomahawk3_tdm_sched_init( 2159 unit, port_schedule_state, TDM_IDB_PKT_SCHED)); 2160 2161 return SOC_E_NONE; 2162 } 2163 2164 /*! @fn int soc_tomahawk3_tdm_mmu_init(int unit, 2165 * soc_port_schedule_state_t *port_schedule_state) 2166 * @param unit Chip unit number. 2167 * @param port_schedule_state Pointer to a soc_port_schedule_state_t 2168 * struct variable. 2169 * @brief API to initialize the TH3 MMU schedulers. 2170 * Description: 2171 * API to initialize the TH3 MMU schedulers. 2172 * Regs/Mems configured: TH3 MMU schedulers. 2173 * Parameters: 2174 * unit - Device number 2175 * *port_schedule_state_t - Agreed structure between SDK and DV 2176 * Return Value: 2177 * SOC_E_* 2178 */ 2179 int soc_tomahawk3_tdm_mmu_init( 2180 int unit, 2181 soc_port_schedule_state_t *port_schedule_state) 2182 { 2183 2184 SOC_IF_ERROR_RETURN(soc_tomahawk3_tdm_set_out_port_map( 2185 unit, port_schedule_state)); 2186 SOC_IF_ERROR_RETURN(soc_tomahawk3_set_tdm_tbl( 2187 unit, port_schedule_state)); 2188 2189 SOC_IF_ERROR_RETURN(soc_tomahawk3_tdm_sched_init( 2190 unit, port_schedule_state, TDM_MMU_MAIN_SCHED)); 2191 SOC_IF_ERROR_RETURN(soc_tomahawk3_tdm_sched_init( 2192 unit, port_schedule_state, TDM_MMU_EB_PORT_SCHED)); 2193 SOC_IF_ERROR_RETURN(soc_tomahawk3_tdm_sched_init( 2194 unit, port_schedule_state, TDM_MMU_EB_PKT_SCHED)); 2195 2196 return SOC_E_NONE; 2197 } 2198 2199 2200 /*! @fn int soc_tomahawk3_tdm_init(int unit, 2201 * soc_port_schedule_state_t *port_schedule_state) 2202 * @param unit Chip unit number. 2203 * @param port_schedule_state Pointer to a soc_port_schedule_state_t 2204 * struct variable. 2205 * @brief API to initialize the TH3 IDB/MMU schedulers. 2206 * Description: 2207 * API to initialize the TH3 IDB/MMU schedulers. 2208 * Regs/Mems configured: TH3 IDB/MMU schedulers. 2209 * Parameters: 2210 * unit - Device number 2211 * *port_schedule_state_t - Agreed structure between SDK and DV 2212 * Return Value: 2213 * SOC_E_* 2214 */ 2215 int soc_tomahawk3_tdm_init( 2216 int unit, 2217 soc_port_schedule_state_t *port_schedule_state) 2218 { 2219 2220 SOC_IF_ERROR_RETURN(soc_tomahawk3_tdm_set_out_port_map( 2221 unit, port_schedule_state)); 2222 SOC_IF_ERROR_RETURN(soc_tomahawk3_set_tdm_tbl( 2223 unit, port_schedule_state)); 2224 2225 /* Ingress Schedulers */ 2226 SOC_IF_ERROR_RETURN(soc_tomahawk3_tdm_sched_init( 2227 unit, port_schedule_state, TDM_IDB_PORT_SCHED)); 2228 SOC_IF_ERROR_RETURN(soc_tomahawk3_tdm_sched_init( 2229 unit, port_schedule_state, TDM_IDB_PKT_SCHED)); 2230 2231 /* MMU Schedulers */ 2232 SOC_IF_ERROR_RETURN(soc_tomahawk3_tdm_sched_init( 2233 unit, port_schedule_state, TDM_MMU_MAIN_SCHED)); 2234 SOC_IF_ERROR_RETURN(soc_tomahawk3_tdm_sched_init( 2235 unit, port_schedule_state, TDM_MMU_EB_PORT_SCHED)); 2236 SOC_IF_ERROR_RETURN(soc_tomahawk3_tdm_sched_init( 2237 unit, port_schedule_state, TDM_MMU_EB_PKT_SCHED)); 2238 2239 return SOC_E_NONE; 2240 } 2241 2242 2243 /*! @fn int soc_tomahawk3_tdm_sched_flexport(int unit, 2244 * soc_port_schedule_state_t *port_schedule_state 2245 * tdm_sched_inst_name_e sched_inst_name ) 2246 * @param unit Chip unit number. 2247 * @param port_schedule_state Pointer to a soc_port_schedule_state_t 2248 * struct variable. 2249 * @param sched_inst_name Instance name enum. 2250 * @param ports_down Ports down or up 2251 * @brief API to flex the TH3 scheduler instance. 2252 * Description: 2253 * API to flex the TH3 scheduler instance. 2254 * Regs/Mems configured: TH3 scheduler instance. 2255 * Parameters: 2256 * unit - Device number 2257 * *port_schedule_state_t - Agreed structure between SDK and DV 2258 * Return Value: 2259 * SOC_E_* 2260 */ 2261 int soc_tomahawk3_tdm_sched_flexport( 2262 int unit, 2263 soc_port_schedule_state_t *port_schedule_state, 2264 tdm_sched_inst_name_e sched_inst_name, 2265 int ports_down) 2266 { 2267 int i, logical_port, pipe_num, phy_port; 2268 soc_port_map_type_t *port_map; 2269 2270 if (1 == ports_down) { /* remove ports from scheduler */ 2271 port_map = &port_schedule_state->in_port_map; 2272 for (i = 0; i < port_schedule_state->nport; i++) { 2273 if (port_schedule_state->resource[i].physical_port == -1) { 2274 logical_port = port_schedule_state->resource[i].logical_port; 2275 pipe_num = logical_port / _TH3_DEV_PORTS_PER_PIPE; 2276 phy_port = 2277 port_map->port_l2p_mapping[logical_port]; 2278 /* Removes slots allocated to this port from scheduler */ 2279 SOC_IF_ERROR_RETURN(soc_tomahawk3_tdm_set_cal_config( 2280 unit, port_schedule_state, 2281 sched_inst_name, pipe_num, phy_port, ports_down)); 2282 /* Clears EDB to MMU credits counter */ 2283 SOC_IF_ERROR_RETURN(soc_tomahawk3_tdm_clear_edb_credit_counter_per_port( 2284 unit, port_schedule_state, 2285 sched_inst_name, pipe_num, phy_port, ports_down)); 2286 /* Removes port from mmu to phy mapping */ 2287 SOC_IF_ERROR_RETURN(soc_tomahawk3_tdm_set_mmu_port_to_phy_port_mapping( 2288 unit, port_schedule_state, 2289 sched_inst_name, pipe_num, phy_port, ports_down)); 2290 /* Clears port_speed in EB SHAPER */ 2291 SOC_IF_ERROR_RETURN(soc_tomahawk3_tdm_set_ebshp_port_cfg( 2292 unit, port_schedule_state, 2293 sched_inst_name, pipe_num, phy_port, ports_down)); 2294 } 2295 } 2296 } else { /* add ports to scheduler */ 2297 port_map = &port_schedule_state->out_port_map; 2298 for (i = 0; i < port_schedule_state->nport; i++) { 2299 if (port_schedule_state->resource[i].physical_port != -1) { 2300 logical_port = port_schedule_state->resource[i].logical_port; 2301 pipe_num = logical_port / _TH3_DEV_PORTS_PER_PIPE; 2302 phy_port = port_schedule_state->resource[i].physical_port; 2303 /* Add slots allocated to this port in scheduler */ 2304 SOC_IF_ERROR_RETURN(soc_tomahawk3_tdm_set_cal_config( 2305 unit, port_schedule_state, 2306 sched_inst_name, pipe_num, phy_port, ports_down)); 2307 /* Configure per port EB credits */ 2308 SOC_IF_ERROR_RETURN(soc_tomahawk3_tdm_set_eb_credit_config( 2309 unit, port_schedule_state, 2310 sched_inst_name, pipe_num, phy_port, ports_down)); 2311 /* Adds port to mmu to phy mapping */ 2312 SOC_IF_ERROR_RETURN(soc_tomahawk3_tdm_set_mmu_port_to_phy_port_mapping( 2313 unit, port_schedule_state, 2314 sched_inst_name, pipe_num, phy_port, ports_down)); 2315 /* Configures port_speed in EB SHAPER */ 2316 SOC_IF_ERROR_RETURN(soc_tomahawk3_tdm_set_ebshp_port_cfg( 2317 unit, port_schedule_state, 2318 sched_inst_name, pipe_num, phy_port, ports_down)); 2319 } 2320 } 2321 } 2322 2323 return SOC_E_NONE; 2324 } 2325 2326 2327 /*! @fn int soc_tomahawk3_tdm_idb_flexport(int unit, 2328 * soc_port_schedule_state_t *port_schedule_state) 2329 * @param unit Chip unit number. 2330 * @param port_schedule_state Pointer to a soc_port_schedule_state_t 2331 * struct variable. 2332 * @brief API to FLEX the TH3 IDB schedulers. 2333 * Description: 2334 * API to FLEX the TH3 IDB schedulers. 2335 * Regs/Mems configured: TH3 IDB schedulers. 2336 * Parameters: 2337 * unit - Device number 2338 * *port_schedule_state_t - Agreed structure between SDK and DV 2339 * Return Value: 2340 * SOC_E_* 2341 */ 2342 int soc_tomahawk3_tdm_idb_flexport( 2343 int unit, 2344 soc_port_schedule_state_t *port_schedule_state) 2345 { 2346 int ports_down; 2347 2348 SOC_IF_ERROR_RETURN(soc_tomahawk3_tdm_set_out_port_map( 2349 unit, port_schedule_state)); 2350 SOC_IF_ERROR_RETURN(soc_tomahawk3_set_tdm_tbl( 2351 unit, port_schedule_state)); 2352 2353 /* Remove DOWN ports */ 2354 ports_down = 1; 2355 SOC_IF_ERROR_RETURN(soc_tomahawk3_tdm_sched_flexport( 2356 unit, port_schedule_state, TDM_IDB_PORT_SCHED, ports_down)); 2357 SOC_IF_ERROR_RETURN(soc_tomahawk3_tdm_sched_flexport( 2358 unit, port_schedule_state, TDM_IDB_PKT_SCHED, ports_down)); 2359 2360 /* Add UP ports */ 2361 ports_down = 0; 2362 SOC_IF_ERROR_RETURN(soc_tomahawk3_tdm_sched_flexport( 2363 unit, port_schedule_state, TDM_IDB_PORT_SCHED, ports_down)); 2364 SOC_IF_ERROR_RETURN(soc_tomahawk3_tdm_sched_flexport( 2365 unit, port_schedule_state, TDM_IDB_PKT_SCHED, ports_down)); 2366 2367 return SOC_E_NONE; 2368 } 2369 2370 2371 /*! @fn int soc_tomahawk3_tdm_mmu_flexport(int unit, 2372 * soc_port_schedule_state_t *port_schedule_state) 2373 * @param unit Chip unit number. 2374 * @param port_schedule_state Pointer to a soc_port_schedule_state_t 2375 * struct variable. 2376 * @brief API to FLEX the TH3 MMU schedulers. 2377 * Description: 2378 * API to FLEX the TH3 MMU schedulers. 2379 * Regs/Mems configured: TH3 MMU schedulers. 2380 * Parameters: 2381 * unit - Device number 2382 * *port_schedule_state_t - Agreed structure between SDK and DV 2383 * Return Value: 2384 * SOC_E_* 2385 */ 2386 int soc_tomahawk3_tdm_mmu_flexport( 2387 int unit, 2388 soc_port_schedule_state_t *port_schedule_state) 2389 { 2390 int ports_down; 2391 2392 SOC_IF_ERROR_RETURN(soc_tomahawk3_tdm_set_out_port_map( 2393 unit, port_schedule_state)); 2394 SOC_IF_ERROR_RETURN(soc_tomahawk3_set_tdm_tbl( 2395 unit, port_schedule_state)); 2396 2397 /* Remove DOWN ports */ 2398 ports_down = 1; 2399 SOC_IF_ERROR_RETURN(soc_tomahawk3_tdm_sched_flexport( 2400 unit, port_schedule_state, TDM_MMU_MAIN_SCHED, ports_down)); 2401 SOC_IF_ERROR_RETURN(soc_tomahawk3_tdm_sched_flexport( 2402 unit, port_schedule_state, TDM_MMU_EB_PORT_SCHED, ports_down)); 2403 SOC_IF_ERROR_RETURN(soc_tomahawk3_tdm_sched_flexport( 2404 unit, port_schedule_state, TDM_MMU_EB_PKT_SCHED, ports_down)); 2405 2406 /* Add UP ports */ 2407 ports_down = 0; 2408 SOC_IF_ERROR_RETURN(soc_tomahawk3_tdm_sched_flexport( 2409 unit, port_schedule_state, TDM_MMU_MAIN_SCHED, ports_down)); 2410 SOC_IF_ERROR_RETURN(soc_tomahawk3_tdm_sched_flexport( 2411 unit, port_schedule_state, TDM_MMU_EB_PORT_SCHED, ports_down)); 2412 SOC_IF_ERROR_RETURN(soc_tomahawk3_tdm_sched_flexport( 2413 unit, port_schedule_state, TDM_MMU_EB_PKT_SCHED, ports_down)); 2414 2415 return SOC_E_NONE; 2416 } 2417 2418 2419 /*** END SDK API COMMON CODE ***/ 2420 2421 #endif /* BCM_TOMAHAWK3_SUPPORT */