ser.c (669164B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: ser.c 8 * Purpose: SER enable/detect and test functionality. 9 * Requires: sal/soc/shared layer 10 */ 11 12 13 #include <shared/bsl.h> 14 #include <soc/drv.h> 15 #include <soc/error.h> 16 #include <soc/debug.h> 17 #include <soc/mem.h> 18 #include <soc/register.h> 19 #include <soc/iproc.h> 20 #include <soc/intr.h> 21 #ifdef ALPM_ENABLE 22 #include <soc/esw/alpm_int.h> 23 #endif 24 #if defined(BCM_TRIDENT2_SUPPORT) 25 #include <soc/trident2.h> 26 #endif /* BCM_TRIDENT2_SUPPORT */ 27 #ifdef BCM_TOMAHAWK3_SUPPORT 28 #include <soc/tomahawk3.h> 29 #endif 30 #ifdef BCM_TOMAHAWK2_SUPPORT 31 #include <soc/tomahawk2.h> 32 #endif 33 #ifdef BCM_CMICX_SUPPORT 34 #include <soc/intr_cmicx.h> 35 #endif 36 37 #ifdef BCM_TOMAHAWK_SUPPORT 38 39 #include <soc/soc_ser_log.h> 40 #include <soc/tomahawk.h> 41 42 #define READ_CMICx_INTC_INTR(unit, reg, rvp) \ 43 soc_iproc_getreg(unit, soc_reg_addr(unit, reg, REG_PORT_ANY, 0), rvp) 44 45 46 #define _SOC_MMU_BASE_INDEX_GLB 0 47 48 #define _SOC_MMU_BASE_INDEX_XPE0 0 49 #define _SOC_MMU_BASE_INDEX_XPE1 1 50 #define _SOC_MMU_BASE_INDEX_XPE2 2 51 #define _SOC_MMU_BASE_INDEX_XPE3 3 52 53 #define _SOC_MMU_BASE_INDEX_SC0 0 54 #define _SOC_MMU_BASE_INDEX_SC1 1 55 56 #define _SOC_TH_MMU_ADDR_ZERO_OUT_SEG_FIELD 0xfffc7fff /* [17:15] = 3'b000 */ 57 #define _SOC_TH_MMU_ADDR_SEG0 0x00000000 /* [17:15] = 3'b000 */ 58 #define _SOC_TH_MMU_ADDR_SEG1 0x00008000 /* [17:15] = 3'b001 */ 59 #define _SOC_TH_MMU_ADDR_SEG2 0x00010000 /* [17:15] = 3'b010 */ 60 #define _SOC_TH_MMU_ADDR_SEG3 0x00018000 /* [17:15] = 3'b011 */ 61 62 63 #define _SOC_TH2_MMU_ADDR_ZERO_OUT_SEG_FIELD 0xfffcffff /* [17:16] = 2'b00 */ 64 #define _SOC_TH2_MMU_ADDR_SEG0 0x00000000 /* [17:16] = 2'b00 */ 65 #define _SOC_TH2_MMU_ADDR_SEG1 0x00010000 /* [17:16] = 2'b01 */ 66 #define _SOC_TH2_MMU_ADDR_SEG2 0x00020000 /* [17:16] = 2'b10 */ 67 #define _SOC_TH2_MMU_ADDR_SEG3 0x00030000 /* [17:16] = 2'b11 */ 68 69 70 71 /* tomahawk [15:16] tomahawk2 [16:17] */ 72 #define _SOC_MMU_BASE_INDEX(unit, mem, bit_mask) (SOC_IS_TOMAHAWK2(unit)?((soc_mem_base(unit, mem) >> 16) & bit_mask):\ 73 ((soc_mem_base(unit, mem) >> 15) & bit_mask)) 74 75 76 #define _SOC_FIND_MMU_XPE_SER_FIFO_MEM(mmu_base_index) \ 77 ((mmu_base_index == 0)? MMU_XCFG_MEM_FAIL_ADDR_64_XPE0m : \ 78 (mmu_base_index == 1)? MMU_XCFG_MEM_FAIL_ADDR_64_XPE1m : \ 79 (mmu_base_index == 2)? MMU_XCFG_MEM_FAIL_ADDR_64_XPE2m : \ 80 MMU_XCFG_MEM_FAIL_ADDR_64_XPE3m) 81 82 #define _SOC_FIND_MMU_SC_SER_FIFO_MEM(mmu_base_index) \ 83 ((mmu_base_index == 0)? MMU_SCFG_MEM_FAIL_ADDR_64_SC0m : \ 84 MMU_SCFG_MEM_FAIL_ADDR_64_SC1m) 85 86 #define _SOC_FIND_MMU_SED_SER_FIFO_MEM(mmu_base_index) \ 87 ((mmu_base_index == 0)? MMU_SEDCFG_MEM_FAIL_ADDR_64_SC0m : \ 88 MMU_SEDCFG_MEM_FAIL_ADDR_64_SC1m) 89 90 #ifdef BCM_TOMAHAWK3_SUPPORT 91 #define _SOC_MMU_BASE_INDEX_ITM0 0 92 #define _SOC_MMU_BASE_INDEX_ITM1 1 93 94 #define _SOC_MMU_BASE_INDEX_EB0 0 95 #define _SOC_MMU_BASE_INDEX_EB1 1 96 #define _SOC_MMU_BASE_INDEX_EB2 2 97 #define _SOC_MMU_BASE_INDEX_EB3 3 98 #define _SOC_MMU_BASE_INDEX_EB4 4 99 #define _SOC_MMU_BASE_INDEX_EB5 5 100 #define _SOC_MMU_BASE_INDEX_EB6 6 101 #define _SOC_MMU_BASE_INDEX_EB7 7 102 103 #define _SOC_FIND_MMU_ITM_SER_FIFO_MEM(mmu_base_index) \ 104 ((mmu_base_index == 0)? MMU_ITMCFG_MEM_FAIL_ADDR_64_ITM0m : \ 105 MMU_ITMCFG_MEM_FAIL_ADDR_64_ITM1m) 106 107 #define _SOC_FIND_MMU_EB_SER_FIFO_MEM(mmu_base_index) \ 108 ((mmu_base_index == 0)? MMU_EBCFG_MEM_FAIL_ADDR_64_PIPE0m : \ 109 (mmu_base_index == 1)? MMU_EBCFG_MEM_FAIL_ADDR_64_PIPE1m : \ 110 (mmu_base_index == 2)? MMU_EBCFG_MEM_FAIL_ADDR_64_PIPE2m : \ 111 (mmu_base_index == 3)? MMU_EBCFG_MEM_FAIL_ADDR_64_PIPE3m : \ 112 (mmu_base_index == 4)? MMU_EBCFG_MEM_FAIL_ADDR_64_PIPE4m : \ 113 (mmu_base_index == 5)? MMU_EBCFG_MEM_FAIL_ADDR_64_PIPE5m : \ 114 (mmu_base_index == 6)? MMU_EBCFG_MEM_FAIL_ADDR_64_PIPE6m : \ 115 MMU_EBCFG_MEM_FAIL_ADDR_64_PIPE7m) 116 #endif 117 118 119 #define _SOC_TH_ACC_TYPE_UNIQUE_PIPE0 0 120 #define _SOC_TH_ACC_TYPE_UNIQUE_PIPE1 1 121 #define _SOC_TH_ACC_TYPE_UNIQUE_PIPE2 2 122 #define _SOC_TH_ACC_TYPE_UNIQUE_PIPE3 3 123 #define _SOC_TH_ACC_TYPE_UNIQUE_PIPE4 4 124 #define _SOC_TH_ACC_TYPE_UNIQUE_PIPE5 5 125 #define _SOC_TH_ACC_TYPE_UNIQUE_PIPE6 6 126 #define _SOC_TH_ACC_TYPE_UNIQUE_PIPE7 7 127 #define _SOC_TH_ACC_TYPE_SINGLE 20 128 #define _SOC_TH_ACC_TYPE_DUPLICATE 9 129 #define _SOC_TH_ACC_TYPE_ADDR_SPLIT_DIST 10 130 #define _SOC_TH_ACC_TYPE_ADDR_SPLIT_SPLIT 12 131 #define _SOC_TH_ACC_TYPE_DATA_SPLIT 14 132 #define _SOC_TH_ACC_TYPE_NAME(at) \ 133 (at == _SOC_TH_ACC_TYPE_UNIQUE_PIPE0) ? "AT_UNIQUE_PIPE0" : \ 134 (at == _SOC_TH_ACC_TYPE_UNIQUE_PIPE1) ? "AT_UNIQUE_PIPE1" : \ 135 (at == _SOC_TH_ACC_TYPE_UNIQUE_PIPE2) ? "AT_UNIQUE_PIPE2" : \ 136 (at == _SOC_TH_ACC_TYPE_UNIQUE_PIPE3) ? "AT_UNIQUE_PIPE3" : \ 137 (at == _SOC_TH_ACC_TYPE_UNIQUE_PIPE4) ? "AT_UNIQUE_PIPE4" : \ 138 (at == _SOC_TH_ACC_TYPE_UNIQUE_PIPE5) ? "AT_UNIQUE_PIPE5" : \ 139 (at == _SOC_TH_ACC_TYPE_UNIQUE_PIPE6) ? "AT_UNIQUE_PIPE6" : \ 140 (at == _SOC_TH_ACC_TYPE_UNIQUE_PIPE7) ? "AT_UNIQUE_PIPE7" : \ 141 (at == _SOC_TH_ACC_TYPE_SINGLE) ? "AT_SINGLE" : \ 142 (at == _SOC_TH_ACC_TYPE_DUPLICATE) ? "AT_DUPLICATE" : \ 143 (at == _SOC_TH_ACC_TYPE_ADDR_SPLIT_DIST) ? "AT_ADDR_SPLIT_DIST" : \ 144 (at == _SOC_TH_ACC_TYPE_ADDR_SPLIT_SPLIT) ? "AT_ADDR_SPLIT_SPLIT" : \ 145 (at == _SOC_TH_ACC_TYPE_DATA_SPLIT) ? "AT_DATA_SPLIT" : \ 146 "AT_UNKNOWN" 147 148 #define _SOC_TH_IFP_SLICE_MODE_NARROW 0 149 #define _SOC_TH_IFP_SLICE_MODE_WIDE 1 150 151 typedef struct _soc_th_ser_mmu_intr_info_s { 152 soc_reg_t int_statf; 153 int mmu_base_index; 154 int ser_info_index; 155 } _soc_th_ser_mmu_intr_info_t; 156 157 typedef enum { 158 _SOC_PARITY_TYPE_NONE, 159 _SOC_PARITY_TYPE_ECC, 160 _SOC_PARITY_TYPE_PARITY, 161 _SOC_PARITY_TYPE_MMU_SER, 162 _SOC_PARITY_TYPE_MMU_GLB, 163 _SOC_PARITY_TYPE_MMU_XPE, 164 _SOC_PARITY_TYPE_MMU_SC, 165 166 #ifdef BCM_TOMAHAWK2_SUPPORT 167 _SOC_PARITY_TYPE_MMU_SED, 168 #endif 169 #ifdef BCM_TOMAHAWK3_SUPPORT 170 _SOC_PARITY_TYPE_MMU_ITMCFG, 171 _SOC_PARITY_TYPE_MMU_EBCFG, 172 #endif 173 #if defined (BCM_TOMAHAWKPLUS_SUPPORT) || defined (BCM_TOMAHAWK2_SUPPORT) 174 _SOC_PARITY_TYPE_CLMAC, 175 #endif 176 #ifdef BCM_TOMAHAWK3_SUPPORT 177 _SOC_PARITY_TYPE_XLMAC, 178 _SOC_PARITY_TYPE_CDMAC, 179 #endif 180 _SOC_PARITY_TYPE_SER, 181 _SOC_PARITY_TYPE_MAC_RX_CDC, 182 _SOC_PARITY_TYPE_MAC_TX_CDC, 183 _SOC_PARITY_TYPE_MAC_RX_TS 184 } _soc_th_ser_info_type_t; 185 186 typedef struct _soc_th_ser_route_block_s { 187 uint8 cmic_reg; /* 3: intr3, 4: intr4, 5: intr5 */ 188 uint32 cmic_bit; 189 soc_block_t blocktype; 190 int pipe; 191 soc_reg_t enable_reg; 192 soc_reg_t status_reg; 193 soc_field_t enable_field; 194 void *info; 195 uint8 id; 196 } _soc_th_ser_route_block_t; 197 198 /* These are now generated from the regsfile processing into bcm56960_a0.c */ 199 #if defined(BCM_TOMAHAWK3_SUPPORT) 200 extern _soc_tcam_ser_en_info_t _soc_bcm56980_a0_tcam_mem_ser_info[]; 201 #endif 202 /* Above structures are defined in chip.h */ 203 204 _soc_bus_ser_en_info_t _soc_th_ip_bus_ser_info[] = { 205 { "IPARS", IPARS_SER_CONTROLr, IPARS_BUS_PARITY_ENf, INVALIDr, INVALIDf }, 206 { "IVXLT", IVXLT_SER_CONTROLr, IVXLT_BUS_PARITY_ENf, INVALIDr, INVALIDf }, 207 { "ISW1", ISW1_SER_CONTROLr, ISW1_BUS_PARITY_ENf, INVALIDr, INVALIDf }, 208 { "IRSEL1", IRSEL1_SER_CONTROLr, IRSEL1_BUS_PARITY_ENf, INVALIDr, INVALIDf }, 209 { "IFP", IFP_PARITY_CONTROLr, IFP_BUS_PARITY_ENf, INVALIDr, INVALIDf }, 210 { "IRSEL2", IRSEL2_SER_CONTROLr, IRSEL2_BUS_PARITY_ENf, INVALIDr, INVALIDf }, 211 { "ISW2", ISW2_SER_CONTROL_1r, ISW2_BUS_PARITY_ENf, INVALIDr, INVALIDf }, 212 { "IFWD", IFWD_SER_CONTROLr, IFWD_BUS_PAR_ENf, INVALIDr, INVALIDf }, 213 { "VP", VP_SER_CONTROLr, VP_BUS_PAR_ENf, INVALIDr, INVALIDf }, 214 { "IPARS_IVP_PT", IVXLT_SER_CONTROLr, PT_HWY_PARITY_ENf, INVALIDr, INVALIDf }, 215 { "IVP_ISW1_PT", IRSEL1_SER_CONTROLr, IVP_TO_ISW1_PT_HWY_PARITY_ENf, INVALIDr, INVALIDf }, 216 { "IFWD_ISW1_PT", IRSEL1_SER_CONTROLr, IFWD_TO_ISW1_PT_HWY_PARITY_ENf, INVALIDr, INVALIDf }, 217 { "ISW1_ISW2_PT", IRSEL2_SER_CONTROLr, ISW1_TO_ISW2_PT_HWY_PARITY_ENf, INVALIDr, INVALIDf }, 218 { "", INVALIDr } 219 }; 220 _soc_bus_ser_en_info_t _soc_th_ep_bus_ser_info[] = { 221 { "EVLAN", EGR_VLAN_SER_CONTROLr, EVLAN_BUS_PARITY_ENf, INVALIDr, INVALIDf }, 222 { "EHCPM", EGR_EHCPM_SER_CONTROLr, EHCPM_BUS_PARITY_ENf, INVALIDr, INVALIDf }, 223 { "EPMOD", EGR_EPMOD_SER_CONTROLr, EPMOD_BUS_PARITY_ENf, INVALIDr, INVALIDf }, 224 { "EFPPARS", EGR_EFPPARS_SER_CONTROLr, EFPPARS_BUS_PARITY_ENf, INVALIDr, INVALIDf }, 225 { "EFP", EFP_PARITY_CONTROLr, EFP_BUS_PARITY_ENf, INVALIDr, INVALIDf }, 226 { "EP_PT", EGR_VLAN_SER_CONTROLr, PT_HWY_PAR_ENf, INVALIDr, INVALIDf }, 227 { "", INVALIDr } 228 }; 229 230 _soc_buffer_ser_en_info_t _soc_th_ip_buffer_ser_info[] = { 231 { "ISW3_EOP_BUFFER_A", ISW3_SER_CONTROL_1r, SW3_EOP_BUFFER_A_PARITY_ENf, INVALIDr, INVALIDf }, 232 { "ISW3_EOP_BUFFER_B", ISW3_SER_CONTROL_1r, SW3_EOP_BUFFER_B_PARITY_ENf, INVALIDr, INVALIDf }, 233 { "BUBBLE_MOP", ISW2_SER_CONTROL_0_64r, CPB_PARITY_ENf, INVALIDr, INVALIDf }, 234 { "METER_STAGING", IFP_PARITY_CONTROLr, METER_MUX_DATA_STAGING_PARITY_ENf, INVALIDr, INVALIDf }, 235 { "COUNTER_STAGING", IFP_PARITY_CONTROLr, 236 COUNTER_MUX_DATA_STAGING_PARITY_ENf, INVALIDr, INVALIDf }, 237 /* No other good place for these for now */ 238 239 /* OBM packet buffer - DBE */ 240 { "OBM0_DATA_FIFO", IDB_OBM0_SER_CONTROLr, DATA_ECC_ENABLEf, INVALIDr, INVALIDf }, 241 { "OBM1_DATA_FIFO", IDB_OBM1_SER_CONTROLr, DATA_ECC_ENABLEf, INVALIDr, INVALIDf }, 242 { "OBM2_DATA_FIFO", IDB_OBM2_SER_CONTROLr, DATA_ECC_ENABLEf, INVALIDr, INVALIDf }, 243 { "OBM3_DATA_FIFO", IDB_OBM3_SER_CONTROLr, DATA_ECC_ENABLEf, INVALIDr, INVALIDf }, 244 { "OBM4_DATA_FIFO", IDB_OBM4_SER_CONTROLr, DATA_ECC_ENABLEf, INVALIDr, INVALIDf }, 245 { "OBM5_DATA_FIFO", IDB_OBM5_SER_CONTROLr, DATA_ECC_ENABLEf, INVALIDr, INVALIDf }, 246 { "OBM6_DATA_FIFO", IDB_OBM6_SER_CONTROLr, DATA_ECC_ENABLEf, INVALIDr, INVALIDf }, 247 { "OBM7_DATA_FIFO", IDB_OBM7_SER_CONTROLr, DATA_ECC_ENABLEf, INVALIDr, INVALIDf }, 248 249 /* OBM queue buffer - DBE */ 250 { "OBM0_QUEUE_FIFO", IDB_OBM0_QUEUE_SER_CONTROLr, ECC_ENABLEf, INVALIDr, INVALIDf }, 251 { "OBM1_QUEUE_FIFO", IDB_OBM1_QUEUE_SER_CONTROLr, ECC_ENABLEf, INVALIDr, INVALIDf }, 252 { "OBM2_QUEUE_FIFO", IDB_OBM2_QUEUE_SER_CONTROLr, ECC_ENABLEf, INVALIDr, INVALIDf }, 253 { "OBM3_QUEUE_FIFO", IDB_OBM3_QUEUE_SER_CONTROLr, ECC_ENABLEf, INVALIDr, INVALIDf }, 254 { "OBM4_QUEUE_FIFO", IDB_OBM4_QUEUE_SER_CONTROLr, ECC_ENABLEf, INVALIDr, INVALIDf }, 255 { "OBM5_QUEUE_FIFO", IDB_OBM5_QUEUE_SER_CONTROLr, ECC_ENABLEf, INVALIDr, INVALIDf }, 256 { "OBM6_QUEUE_FIFO", IDB_OBM6_QUEUE_SER_CONTROLr, ECC_ENABLEf, INVALIDr, INVALIDf }, 257 { "OBM7_QUEUE_FIFO", IDB_OBM7_QUEUE_SER_CONTROLr, ECC_ENABLEf, INVALIDr, INVALIDf }, 258 259 /* Data port CA buffer (CA-PM packet buffer) - DBE */ 260 { "CELL_ASSEM_BUFFER0", IDB_OBM0_SER_CONTROLr, CA_FIFO_ECC_ENABLEf, INVALIDr, INVALIDf }, 261 { "CELL_ASSEM_BUFFER1", IDB_OBM1_SER_CONTROLr, CA_FIFO_ECC_ENABLEf, INVALIDr, INVALIDf }, 262 { "CELL_ASSEM_BUFFER2", IDB_OBM2_SER_CONTROLr, CA_FIFO_ECC_ENABLEf, INVALIDr, INVALIDf }, 263 { "CELL_ASSEM_BUFFER3", IDB_OBM3_SER_CONTROLr, CA_FIFO_ECC_ENABLEf, INVALIDr, INVALIDf }, 264 { "CELL_ASSEM_BUFFER4", IDB_OBM4_SER_CONTROLr, CA_FIFO_ECC_ENABLEf, INVALIDr, INVALIDf }, 265 { "CELL_ASSEM_BUFFER5", IDB_OBM5_SER_CONTROLr, CA_FIFO_ECC_ENABLEf, INVALIDr, INVALIDf }, 266 { "CELL_ASSEM_BUFFER6", IDB_OBM6_SER_CONTROLr, CA_FIFO_ECC_ENABLEf, INVALIDr, INVALIDf }, 267 { "CELL_ASSEM_BUFFER7", IDB_OBM7_SER_CONTROLr, CA_FIFO_ECC_ENABLEf, INVALIDr, INVALIDf }, 268 269 /* CPU port CA buffer (CA-CM packet buffer) - DBE */ 270 { "CPU_CELL_ASSEM_BUFFER", IDB_SER_CONTROLr, CA_CPU_ECC_ENABLEf, INVALIDr, INVALIDf }, 271 272 /* Loopback port CA buffer (CA-LPBK packet buffer) - DBE */ 273 { "LPBK_CELL_ASSEM_BUFFER", IDB_SER_CONTROLr, CA_LPBK_ECC_ENABLEf, INVALIDr, INVALIDf }, 274 275 /* Ingress Scheduler - DBE */ 276 { "IS_TDM_CALENDAR", IDB_SER_CONTROLr, IS_TDM_ECC_ENf, INVALIDr, INVALIDf }, 277 /* OBM Stats - parity */ 278 { "IDB_OBMn_STATS_WIN_RES", IDB_SER_CONTROLr, OBM_MON_PAR_ENf, INVALIDr, INVALIDf }, 279 280 /* L2_Mgmt - not part of ipipe, epipe */ 281 { "L2_MOD_FIFO", L2_MOD_FIFO_PARITY_CONTROLr, L2_MOD_FIFO_PARITY_ENf, INVALIDr, INVALIDf }, 282 { "LEARN_FIFO", LEARN_FIFO_ECC_CONTROLr, ECC_ENf, INVALIDr, INVALIDf }, 283 284 285 /* OBM packet buffer - disable SBE 286 { "OBM0_DATA_FIFO_1b", IDB_OBM0_SER_CONTROLr, DATA_EN_COR_ERR_RPTf }, 287 { "OBM1_DATA_FIFO_1b", IDB_OBM1_SER_CONTROLr, DATA_EN_COR_ERR_RPTf }, 288 { "OBM2_DATA_FIFO_1b", IDB_OBM2_SER_CONTROLr, DATA_EN_COR_ERR_RPTf }, 289 { "OBM3_DATA_FIFO_1b", IDB_OBM3_SER_CONTROLr, DATA_EN_COR_ERR_RPTf }, 290 { "OBM4_DATA_FIFO_1b", IDB_OBM4_SER_CONTROLr, DATA_EN_COR_ERR_RPTf }, 291 { "OBM5_DATA_FIFO_1b", IDB_OBM5_SER_CONTROLr, DATA_EN_COR_ERR_RPTf }, 292 { "OBM6_DATA_FIFO_1b", IDB_OBM6_SER_CONTROLr, DATA_EN_COR_ERR_RPTf }, 293 { "OBM7_DATA_FIFO_1b", IDB_OBM7_SER_CONTROLr, DATA_EN_COR_ERR_RPTf }, 294 */ 295 296 /* OBM queue buffer - enable SBE */ 297 { "OBM0_QUEUE_FIFO_1b", IDB_OBM0_QUEUE_SER_CONTROLr, EN_COR_ERR_RPTf, INVALIDr, INVALIDf }, 298 { "OBM1_QUEUE_FIFO_1b", IDB_OBM1_QUEUE_SER_CONTROLr, EN_COR_ERR_RPTf, INVALIDr, INVALIDf }, 299 { "OBM2_QUEUE_FIFO_1b", IDB_OBM2_QUEUE_SER_CONTROLr, EN_COR_ERR_RPTf, INVALIDr, INVALIDf }, 300 { "OBM3_QUEUE_FIFO_1b", IDB_OBM3_QUEUE_SER_CONTROLr, EN_COR_ERR_RPTf, INVALIDr, INVALIDf }, 301 { "OBM4_QUEUE_FIFO_1b", IDB_OBM4_QUEUE_SER_CONTROLr, EN_COR_ERR_RPTf, INVALIDr, INVALIDf }, 302 { "OBM5_QUEUE_FIFO_1b", IDB_OBM5_QUEUE_SER_CONTROLr, EN_COR_ERR_RPTf, INVALIDr, INVALIDf }, 303 { "OBM6_QUEUE_FIFO_1b", IDB_OBM6_QUEUE_SER_CONTROLr, EN_COR_ERR_RPTf, INVALIDr, INVALIDf }, 304 { "OBM7_QUEUE_FIFO_1b", IDB_OBM7_QUEUE_SER_CONTROLr, EN_COR_ERR_RPTf, INVALIDr, INVALIDf }, 305 306 /* Data port CA buffer (CA-PM packet buffer) - disable SBE 307 { "CELL_ASSEM_BUFFER0_1b", IDB_OBM0_SER_CONTROLr, CA_FIFO_EN_COR_ERR_RPTf }, 308 { "CELL_ASSEM_BUFFER1_1b", IDB_OBM1_SER_CONTROLr, CA_FIFO_EN_COR_ERR_RPTf }, 309 { "CELL_ASSEM_BUFFER2_1b", IDB_OBM2_SER_CONTROLr, CA_FIFO_EN_COR_ERR_RPTf }, 310 { "CELL_ASSEM_BUFFER3_1b", IDB_OBM3_SER_CONTROLr, CA_FIFO_EN_COR_ERR_RPTf }, 311 { "CELL_ASSEM_BUFFER4_1b", IDB_OBM4_SER_CONTROLr, CA_FIFO_EN_COR_ERR_RPTf }, 312 { "CELL_ASSEM_BUFFER5_1b", IDB_OBM5_SER_CONTROLr, CA_FIFO_EN_COR_ERR_RPTf }, 313 { "CELL_ASSEM_BUFFER6_1b", IDB_OBM6_SER_CONTROLr, CA_FIFO_EN_COR_ERR_RPTf }, 314 { "CELL_ASSEM_BUFFER7_1b", IDB_OBM7_SER_CONTROLr, CA_FIFO_EN_COR_ERR_RPTf }, 315 */ 316 317 /* CPU port CA buffer (CA-CM packet buffer) - disable SBE 318 { "CPU_CELL_ASSEM_BUFFER_1b", IDB_SER_CONTROLr, CA_CPU_ERR1_RPT_EN }, 319 */ 320 321 /* Loopback port CA buffer (CA-LPBK packet buffer) - disable SBE 322 { "LPBK_CELL_ASSEM_BUFFER_1b", IDB_SER_CONTROLr, CA_LPBK_ERR1_RPT_EN }, 323 */ 324 325 /* Ingress Scheduler - disable SBE 326 { "IS_TDM_CALENDAR_1b", IDB_SER_CONTROLr, IS_TDM_ERR1_RPT_ENf }, 327 */ 328 329 /* end of list */ 330 { "", INVALIDr } 331 }; 332 333 _soc_buffer_ser_en_info_t _soc_th_ep_buffer_ser_info[] = { 334 { "EDB_PM0_MEM", EGR_EDATABUF_PARITY_CONTROLr, PM0_ECC_ENf, INVALIDr, INVALIDf }, 335 { "EDB_PM1_MEM", EGR_EDATABUF_PARITY_CONTROLr, PM1_ECC_ENf, INVALIDr, INVALIDf }, 336 { "EDB_PM2_MEM", EGR_EDATABUF_PARITY_CONTROLr, PM2_ECC_ENf, INVALIDr, INVALIDf }, 337 { "EDB_PM3_MEM", EGR_EDATABUF_PARITY_CONTROLr, PM3_ECC_ENf, INVALIDr, INVALIDf }, 338 { "EDB_PM4_MEM", EGR_EDATABUF_PARITY_CONTROLr, PM4_ECC_ENf, INVALIDr, INVALIDf }, 339 { "EDB_PM5_MEM", EGR_EDATABUF_PARITY_CONTROLr, PM5_ECC_ENf, INVALIDr, INVALIDf }, 340 { "EDB_PM6_MEM", EGR_EDATABUF_PARITY_CONTROLr, PM6_ECC_ENf, INVALIDr, INVALIDf }, 341 { "EDB_PM7_MEM", EGR_EDATABUF_PARITY_CONTROLr, PM7_ECC_ENf, INVALIDr, INVALIDf }, 342 { "EDB_CM_MEM", EGR_EDATABUF_PARITY_CONTROLr, CM_ECC_ENf, INVALIDr, INVALIDf }, 343 { "EDB_LBP_MEM", EGR_EDATABUF_PARITY_CONTROLr, LBP_ECC_ENf, INVALIDr, INVALIDf }, 344 { "EDB_PM0_CTRL", EGR_EDB_CTRL_PARITY_ENr, PM0_ECC_ENf, INVALIDr, INVALIDf }, 345 { "EDB_PM1_CTRL", EGR_EDB_CTRL_PARITY_ENr, PM1_ECC_ENf, INVALIDr, INVALIDf }, 346 { "EDB_PM2_CTRL", EGR_EDB_CTRL_PARITY_ENr, PM2_ECC_ENf, INVALIDr, INVALIDf }, 347 { "EDB_PM3_CTRL", EGR_EDB_CTRL_PARITY_ENr, PM3_ECC_ENf, INVALIDr, INVALIDf }, 348 { "EDB_PM4_CTRL", EGR_EDB_CTRL_PARITY_ENr, PM4_ECC_ENf, INVALIDr, INVALIDf }, 349 { "EDB_PM5_CTRL", EGR_EDB_CTRL_PARITY_ENr, PM5_ECC_ENf, INVALIDr, INVALIDf }, 350 { "EDB_PM6_CTRL", EGR_EDB_CTRL_PARITY_ENr, PM6_ECC_ENf, INVALIDr, INVALIDf }, 351 { "EDB_PM7_CTRL", EGR_EDB_CTRL_PARITY_ENr, PM7_ECC_ENf, INVALIDr, INVALIDf }, 352 { "EDB_CM_CTRL", EGR_EDB_CTRL_PARITY_ENr, CM_ECC_ENf, INVALIDr, INVALIDf }, 353 { "EDB_LBP_CTRL", EGR_EDB_CTRL_PARITY_ENr, LBP_ECC_ENf, INVALIDr, INVALIDf }, 354 { "INITBUF", EGR_EL3_ECC_PARITY_CONTROLr, INITBUF_ECC_ENf, INVALIDr, INVALIDf }, 355 { "EGR_MPB", EGR_EL3_ECC_PARITY_CONTROLr, EGR_MPB_ECC_ENf, INVALIDr, INVALIDf }, 356 { "EP_EDB_PM_RESI_BUFF", EGR_EDATABUF_PARITY_CONTROLr, 357 PM_RESI_BUFFER_PAR_ENf, INVALIDr, INVALIDf }, 358 { "", INVALIDr } 359 }; 360 361 _soc_bus_buffer_ser_force_info_t _soc_bcm56960_a0_bus_buffer_ser_force_info[] = { 362 { "BUBBLE_MOP", ISW2_SER_CONTROL_0_64r, CPB_PARITY_FORCE_ERRf }, 363 { "IPARS_BUS", IPARS_SER_CONTROLr, IPARS_FORCE_ERRORf }, 364 { "IVXLT_BUS", IVXLT_SER_CONTROLr, IVXLT_BUS_PARITY_FORCE_ERRORf }, 365 { "IFWD_BUS", IFWD_SER_CONTROLr, IFWD_BUS_CORRUPT_ENf }, 366 { "IRSEL1_BUS", IRSEL1_SER_CONTROLr, IRSEL1_BUS_PARITY_FORCE_ERRORf }, 367 { "ISW1_BUS", ISW1_SER_CONTROLr, ISW1_BUS_PARITY_FORCE_ERRORf }, 368 { "ISW2_BUS", ISW2_SER_CONTROL_1r, ISW2_BUS_PARITY_FORCE_ERRORf }, 369 { "IFP_BUS", IFP_PARITY_CONTROLr, IFP_BUS_PARITY_FORCE_ERRORf }, 370 { "IRSEL2_BUS", IRSEL2_SER_CONTROLr, IRSEL2_BUS_PARITY_FORCE_ERRORf }, 371 { "VP_BUS", VP_SER_CONTROLr, VP_BUS_CORRUPT_ENf }, 372 { "EP_INITBUF", EGR_EL3_ECC_PARITY_CONTROLr, EP_INITBUF_ECC_CORRUPTf }, 373 { "IP_PACKET_BUFFER", IPARS_SER_CONTROLr, INGRESS_PACKET_BUFFER_FORCE_ERRORf }, 374 { "EFP_BUS", EFP_PARITY_CONTROLr, EFP_BUS_PARITY_FORCE_ERRORf }, 375 { "EVLAN_BUS", EGR_VLAN_SER_CONTROLr, EVLAN_FORCE_ERRORf }, 376 { "EHCPM_BUS", EGR_EHCPM_SER_CONTROLr, EHCPM_FORCE_ERRORf }, 377 { "EPMOD_BUS", EGR_EPMOD_SER_CONTROLr, EPMOD_FORCE_ERRORf }, 378 { "EFPPARS_BUS", EGR_EFPPARS_SER_CONTROLr, EFPPARS_FORCE_ERRORf }, 379 { "EP_PT_BUS", EGR_VLAN_SER_CONTROLr, PT_HWY_PAR_CORf }, 380 { "IPARS_IVP_PT_BUS", IVXLT_SER_CONTROLr, PT_HWY_PARITY_FORCE_ERRORf }, 381 { "IVP_ISW1_PT_BUS", IRSEL1_SER_CONTROLr, IVP_TO_ISW1_PT_HWY_FORCE_ERRORf }, 382 { "IFWD_ISW1_PT_BUS", IRSEL1_SER_CONTROLr, IFWD_TO_ISW1_PT_HWY_FORCE_ERRORf }, 383 { "ISW1_ISW2_PT_BUS", IRSEL2_SER_CONTROLr, ISW1_TO_ISW2_PT_HWY_FORCE_ERRORf }, 384 { "", INVALIDr } /* end */ 385 }; 386 387 uint32 ser_th_bus_buffer_hwbase[] = { 388 0xa, /* BUBBLE_MOP */ 389 0x11, /* IPARS_BUS */ 390 0x12, /* IVXLT_BUS */ 391 0x14, /* IFWD_BUS */ 392 0x15, /* IRSEL1_BUS */ 393 0x16, /* ISW1_BUS */ 394 0x19, /* ISW2_BUS */ 395 0xf, /* IFP_BUS */ 396 0x18, /* IRSEL2_BUS */ 397 0x13, /* VP_BUS */ 398 0x41, /* EP_INITBUF */ 399 0x40, /* IP_PACKET_BUFFER */ 400 0x5e, /* EFP_BUS */ 401 0x5a, /* EVLAN_BUS */ 402 0x5b, /* EHCPM_BUS */ 403 0x5c, /* EPMOD_BUS */ 404 0x5d, /* EFPPARS_BUS */ 405 0x5f, /* EP_PT_BUS */ 406 0xb, /* IPARS_IVP_PT_BUS */ 407 0xc, /* IVP_ISW1_PT_BUS */ 408 0xd, /* IFWD_ISW1_PT_BUS */ 409 0xf /* ISW1_ISW2_PT_BUS */ 410 }; 411 412 typedef struct _soc_th_ser_reg_s { 413 soc_reg_t reg; 414 char *mem_str; 415 } _soc_th_ser_reg_t; 416 417 typedef struct _soc_th_ser_info_s { 418 _soc_th_ser_info_type_t type; 419 struct _soc_th_ser_info_s *info; 420 int id; 421 soc_field_t group_reg_enable_field; 422 soc_field_t group_reg_status_field; 423 soc_mem_t mem; 424 char *mem_str; 425 soc_reg_t enable_reg; 426 soc_field_t enable_field; 427 soc_field_t *enable_field_list; 428 soc_reg_t intr_enable_reg; 429 soc_field_t intr_enable_field; 430 soc_field_t *intr_enable_field_list; 431 soc_reg_t intr_status_reg; 432 _soc_th_ser_reg_t *intr_status_reg_list; 433 soc_reg_t intr_status_field; 434 soc_field_t *intr_status_field_list; 435 soc_reg_t intr_clr_reg; 436 soc_field_t intr_clr_field; 437 soc_field_t *intr_clr_field_list; 438 } _soc_th_ser_info_t; 439 440 typedef struct _soc_th_ser_block_info_s { 441 int type; 442 soc_block_t blocktype; 443 char name[16]; 444 soc_reg_t fifo_reset_reg; 445 void *info; 446 } _soc_th_ser_block_info_t; 447 448 static soc_ser_functions_t _th_ser_functions; 449 450 451 static soc_field_t _soc_th_mmu_xpe_enable_fields[] = { 452 THDM_PARITY_ENf, 453 ENQX_PARITY_ENf, 454 EPRG_PARITY_ENf, 455 RQE_PARITY_ENf, 456 THDI_PARITY_ENf, 457 THDU_PARITY_ENf, 458 PQE_PARITY_ENf, 459 WRED_PARITY_ENf, 460 DQX_PARITY_ENf, 461 CCP_PARITY_ENf, 462 CTR_PARITY_ENf, 463 INVALIDf 464 }; 465 466 static soc_field_t _soc_th_mmu_sc_enable_fields[] = { 467 MB_A_PARITY_ENf, 468 MB_B_PARITY_ENf, 469 TDM_PARITY_ENf, 470 ENQS_PARITY_ENf, 471 MTRO_PARITY_ENf, 472 VBS_PARITY_ENf, 473 DQS_PARITY_ENf, 474 TOQ_B_PARITY_ENf, 475 TOQ_A_PARITY_ENf, 476 CFAP_B_PARITY_ENf, 477 CFAP_A_PARITY_ENf, 478 INVALIDf 479 }; 480 481 static soc_field_t _soc_th_mmu_sc_int_enable_fields[] = { 482 CFAP_A_MEM_FAIL_ENf, 483 CFAP_B_MEM_FAIL_ENf, 484 MEM_PAR_ERR_ENf, 485 INVALIDf 486 }; 487 static soc_field_t _soc_th_mmu_sc_status_fields[] = { 488 CFAP_A_MEM_FAIL_STATf, 489 CFAP_B_MEM_FAIL_STATf, 490 MEM_PAR_ERR_STATf, 491 INVALIDf 492 }; 493 static soc_field_t _soc_th_mmu_sc_clr_fields[] = { 494 CFAP_A_MEM_FAIL_CLRf, 495 CFAP_B_MEM_FAIL_CLRf, 496 MEM_PAR_ERR_CLRf, 497 INVALIDf 498 }; 499 500 static _soc_th_ser_info_t _soc_th_mmu_ser_info[] = { 501 { _SOC_PARITY_TYPE_MMU_GLB, NULL, 0, 502 INVALIDf, INVALIDf, 503 INVALIDm, "MMU GLB MEM PAR", 504 MMU_GCFG_PARITY_ENr, INTFO_PARITY_ENf, NULL, 505 MMU_GCFG_GLB_CPU_INT_ENr, MEM_PAR_ERR_ENf, NULL, 506 MMU_GCFG_GLB_CPU_INT_STATr, NULL, MEM_PAR_ERR_STATf, NULL, 507 MMU_GCFG_GLB_CPU_INT_CLEARr, MEM_PAR_ERR_CLRf, NULL 508 }, 509 { _SOC_PARITY_TYPE_MMU_XPE, NULL, 0, 510 INVALIDf, INVALIDf, 511 INVALIDm, "MMU XPE MEM PAR", 512 MMU_XCFG_PARITY_ENr, INVALIDf, _soc_th_mmu_xpe_enable_fields, 513 MMU_XCFG_XPE_CPU_INT_ENr, MEM_PAR_ERR_ENf, NULL, 514 MMU_XCFG_XPE_CPU_INT_STATr, NULL, MEM_PAR_ERR_STATf, NULL, 515 MMU_XCFG_XPE_CPU_INT_CLEARr, MEM_PAR_ERR_CLRf, NULL 516 }, 517 { _SOC_PARITY_TYPE_MMU_SC, NULL, 0, 518 INVALIDf, INVALIDf, 519 INVALIDm, "MMU SC MEM PAR", 520 MMU_SCFG_PARITY_ENr, INVALIDf, _soc_th_mmu_sc_enable_fields, 521 MMU_SCFG_SC_CPU_INT_ENr, INVALIDf, _soc_th_mmu_sc_int_enable_fields, 522 MMU_SCFG_SC_CPU_INT_STATr, NULL, INVALIDf/*INVALIDf*/, 523 _soc_th_mmu_sc_status_fields/*_soc_th_mmu_sc_status_fields*/, 524 MMU_SCFG_SC_CPU_INT_CLEARr, INVALIDf/*INVALIDf*/, 525 _soc_th_mmu_sc_clr_fields/*_soc_th_mmu_sc_clr_fields*/ 526 }, 527 { _SOC_PARITY_TYPE_NONE } /* table terminator */ 528 }; 529 530 static soc_field_t _soc_th_mmu_top_int_enable_fields[] = { 531 SC_R_CPU_INT_ENf, 532 SC_S_CPU_INT_ENf, 533 XPE_R_B_CPU_INT_ENf, 534 XPE_R_A_CPU_INT_ENf, 535 XPE_S_B_CPU_INT_ENf, 536 XPE_S_A_CPU_INT_ENf, 537 GLB_CPU_INT_ENf, 538 INVALIDf 539 }; 540 541 static soc_field_t _soc_th_mmu_top_int_status_fields[] = { 542 SC_R_CPU_INT_STATf, 543 SC_S_CPU_INT_STATf, 544 XPE_R_B_CPU_INT_STATf, 545 XPE_R_A_CPU_INT_STATf, 546 XPE_S_B_CPU_INT_STATf, 547 XPE_S_A_CPU_INT_STATf, 548 GLB_CPU_INT_STATf, 549 INVALIDf 550 }; 551 552 static _soc_th_ser_info_t _soc_th_mmu_top_ser_info[] = { 553 { _SOC_PARITY_TYPE_MMU_SER, _soc_th_mmu_ser_info, 0, 554 INVALIDf, INVALIDf, 555 INVALIDm, "MMU MEM PAR", 556 INVALIDr, INVALIDf, NULL, 557 MMU_GCFG_ALL_CPU_INT_ENr, INVALIDf, 558 _soc_th_mmu_top_int_enable_fields, 559 MMU_GCFG_ALL_CPU_INT_STATr, 560 NULL, INVALIDf, _soc_th_mmu_top_int_status_fields, 561 INVALIDr, INVALIDf, NULL 562 }, 563 { _SOC_PARITY_TYPE_NONE } /* table terminator */ 564 }; 565 566 static const 567 _soc_th_ser_mmu_intr_info_t mmu_intr_info[] = { 568 { GLB_CPU_INT_STATf, _SOC_MMU_BASE_INDEX_GLB, 0 }, 569 { XPE_R_A_CPU_INT_STATf, _SOC_MMU_BASE_INDEX_XPE0, 1 }, 570 { XPE_S_A_CPU_INT_STATf, _SOC_MMU_BASE_INDEX_XPE1, 1 }, 571 { XPE_R_B_CPU_INT_STATf, _SOC_MMU_BASE_INDEX_XPE2, 1 }, 572 { XPE_S_B_CPU_INT_STATf, _SOC_MMU_BASE_INDEX_XPE3, 1 }, 573 { SC_R_CPU_INT_STATf, _SOC_MMU_BASE_INDEX_SC0, 2 }, 574 { SC_S_CPU_INT_STATf, _SOC_MMU_BASE_INDEX_SC1, 2}, 575 { INVALIDf, -1, -1 } 576 }; 577 578 static soc_field_t _soc_th_pm_rx_cdc_clear_field[] = { 579 CLEAR_RX_CDC_SINGLE_BIT_ERRf, CLEAR_RX_CDC_DOUBLE_BIT_ERRf 580 }; 581 static soc_field_t _soc_th_pm_tx_cdc_clear_field[] = { 582 CLEAR_TX_CDC_SINGLE_BIT_ERRf, CLEAR_TX_CDC_DOUBLE_BIT_ERRf 583 }; 584 static soc_field_t _soc_th_pm_rx_ts_clear_field[] = { 585 CLEAR_RX_TS_MEM_SINGLE_BIT_ERRf, CLEAR_RX_TS_MEM_DOUBLE_BIT_ERRf 586 }; 587 588 static _soc_th_ser_reg_t _soc_th_pm_clp_rx_status_reg[] = { 589 { CLPORT_MIB_RSC0_ECC_STATUSr, "CLP MIB RSC0 ECC" }, 590 { CLPORT_MIB_RSC1_ECC_STATUSr, "CLP MIB RSC1 ECC" }, 591 { INVALIDr, "INVALID"} 592 }; 593 594 static _soc_th_ser_reg_t _soc_th_pm_clp_tx_status_reg[] = { 595 { CLPORT_MIB_TSC0_ECC_STATUSr, "CLP MIB TSC0 ECC" }, 596 { CLPORT_MIB_TSC1_ECC_STATUSr, "CLP MIB TSC1 ECC" }, 597 { INVALIDr, "INVALID"} 598 }; 599 600 static _soc_th_ser_reg_t _soc_th_pm_xlp_rx_status_reg[] = { 601 { XLPORT_MIB_RSC0_ECC_STATUSr, "XLP MIB RSC0 ECC" }, 602 { XLPORT_MIB_RSC1_ECC_STATUSr, "XLP MIB RSC1 ECC" }, 603 { INVALIDr, "INVALID"} 604 }; 605 606 static _soc_th_ser_reg_t _soc_th_pm_xlp_tx_status_reg[] = { 607 { XLPORT_MIB_TSC0_ECC_STATUSr, "XLP MIB TSC0 ECC" }, 608 { XLPORT_MIB_TSC1_ECC_STATUSr, "XLP MIB TSC1 ECC" }, 609 { INVALIDr, "INVALID"} 610 }; 611 612 static _soc_th_ser_info_t _soc_th_pm_clp_ser_info[] = { 613 { _SOC_PARITY_TYPE_MAC_RX_TS, NULL, 0, 614 MAC_RX_TS_CDC_MEM_ERRf, MAC_RX_TS_CDC_MEM_ERRf, 615 INVALIDm, "MAC RX TimeStamp CDC memory", 616 CLMAC_ECC_CTRLr, RX_TS_MEM_ECC_CTRL_ENf, NULL, 617 INVALIDr, INVALIDf, NULL, 618 CLMAC_RX_TS_MEM_ECC_STATUSr, NULL, INVALIDf, NULL, 619 CLMAC_CLEAR_ECC_STATUSr, INVALIDf, _soc_th_pm_rx_ts_clear_field 620 }, 621 { _SOC_PARITY_TYPE_MAC_RX_CDC, NULL, 0, 622 MAC_RX_CDC_MEM_ERRf, MAC_RX_CDC_MEM_ERRf, 623 INVALIDm, "MAC RX CDC memory", 624 CLMAC_ECC_CTRLr, RX_CDC_ECC_CTRL_ENf, NULL, 625 INVALIDr, INVALIDf, NULL, 626 CLMAC_RX_CDC_ECC_STATUSr, NULL, INVALIDf, NULL, 627 CLMAC_CLEAR_ECC_STATUSr, INVALIDf, _soc_th_pm_rx_cdc_clear_field 628 }, 629 { _SOC_PARITY_TYPE_MAC_TX_CDC, NULL, 0, 630 MAC_TX_CDC_MEM_ERRf, MAC_TX_CDC_MEM_ERRf, 631 INVALIDm, "MAC TX CDC memory", 632 CLMAC_ECC_CTRLr, TX_CDC_ECC_CTRL_ENf, NULL, 633 INVALIDr, INVALIDf, NULL, 634 CLMAC_TX_CDC_ECC_STATUSr, NULL, INVALIDf, NULL, 635 CLMAC_CLEAR_ECC_STATUSr, INVALIDf, _soc_th_pm_tx_cdc_clear_field 636 }, 637 { _SOC_PARITY_TYPE_ECC, NULL, 0, 638 MIB_RX_MEM_ERRf, MIB_RX_MEM_ERRf, 639 INVALIDm, "MIB RX Statistic Counter memory", 640 CLPORT_ECC_CONTROLr, MIB_RSC_MEM_ENf, NULL, 641 INVALIDr, INVALIDf, NULL, 642 INVALIDr, _soc_th_pm_clp_rx_status_reg, INVALIDf, NULL, 643 INVALIDr, INVALIDf, NULL 644 }, 645 { _SOC_PARITY_TYPE_ECC, NULL, 0, 646 MIB_TX_MEM_ERRf, MIB_TX_MEM_ERRf, 647 INVALIDm, "MIB TX Statistic Counter memory", 648 CLPORT_ECC_CONTROLr, MIB_TSC_MEM_ENf, NULL, 649 INVALIDr, INVALIDf, NULL, 650 INVALIDr, _soc_th_pm_clp_tx_status_reg, INVALIDf, NULL, 651 INVALIDr, INVALIDf, NULL 652 }, 653 { _SOC_PARITY_TYPE_NONE } /* table terminator */ 654 }; 655 656 static _soc_th_ser_info_t _soc_th_pm_xlp_ser_info[] = { 657 { _SOC_PARITY_TYPE_MAC_RX_CDC, NULL, 0, 658 MAC_RX_CDC_MEM_ERRf, MAC_RX_CDC_MEM_ERRf, 659 INVALIDm, "MAC RX CDC memory", 660 XLMAC_ECC_CTRLr, RX_CDC_ECC_CTRL_ENf, NULL, 661 INVALIDr, INVALIDf, NULL, 662 XLMAC_RX_CDC_ECC_STATUSr, NULL, INVALIDf, NULL, 663 XLMAC_CLEAR_ECC_STATUSr, INVALIDf, _soc_th_pm_rx_cdc_clear_field 664 }, 665 { _SOC_PARITY_TYPE_MAC_TX_CDC, NULL, 0, 666 MAC_TX_CDC_MEM_ERRf, MAC_TX_CDC_MEM_ERRf, 667 INVALIDm, "MAC TX CDC memory", 668 XLMAC_ECC_CTRLr, TX_CDC_ECC_CTRL_ENf, NULL, 669 INVALIDr, INVALIDf, NULL, 670 XLMAC_TX_CDC_ECC_STATUSr, NULL, INVALIDf, NULL, 671 XLMAC_CLEAR_ECC_STATUSr, INVALIDf, _soc_th_pm_tx_cdc_clear_field 672 }, 673 { _SOC_PARITY_TYPE_ECC, NULL, 0, 674 MIB_RX_MEM_ERRf, MIB_RX_MEM_ERRf, 675 INVALIDm, "MIB RX Statistic Counter memory", 676 XLPORT_ECC_CONTROLr, MIB_RSC_MEM_ENf, NULL, 677 INVALIDr, INVALIDf, NULL, 678 INVALIDr, _soc_th_pm_xlp_rx_status_reg, INVALIDf, NULL, 679 INVALIDr, INVALIDf, NULL 680 }, 681 { _SOC_PARITY_TYPE_ECC, NULL, 0, 682 MIB_TX_MEM_ERRf, MIB_TX_MEM_ERRf, 683 INVALIDm, "MIB TX Statistic Counter memory", 684 XLPORT_ECC_CONTROLr, MIB_TSC_MEM_ENf, NULL, 685 INVALIDr, INVALIDf, NULL, 686 INVALIDr, _soc_th_pm_xlp_tx_status_reg, INVALIDf, NULL, 687 INVALIDr, INVALIDf, NULL 688 }, 689 { _SOC_PARITY_TYPE_NONE } /* table terminator */ 690 }; 691 692 #ifdef BCM_TOMAHAWKPLUS_SUPPORT 693 static _soc_th_ser_info_t _soc_thplus_pm_clp_ser_info[] = { 694 { _SOC_PARITY_TYPE_ECC, NULL, 0, 695 MIB_RX_MEM_ERRf, MIB_RX_MEM_ERRf, 696 INVALIDm, "MIB RX Statistic Counter memory", 697 CLPORT_ECC_CONTROLr, MIB_RSC_MEM_ENf, NULL, 698 INVALIDr, INVALIDf, NULL, 699 INVALIDr, _soc_th_pm_clp_rx_status_reg, INVALIDf, NULL, 700 INVALIDr, INVALIDf, NULL 701 }, 702 { _SOC_PARITY_TYPE_ECC, NULL, 0, 703 MIB_RX_MEM_ERRf, MIB_RX_MEM_ERRf, 704 INVALIDm, "MIB TX Statistic Counter memory", 705 CLPORT_ECC_CONTROLr, MIB_TSC_MEM_ENf, NULL, 706 INVALIDr, INVALIDf, NULL, 707 INVALIDr, _soc_th_pm_clp_tx_status_reg, INVALIDf, NULL, 708 INVALIDr, INVALIDf, NULL 709 }, 710 { _SOC_PARITY_TYPE_CLMAC, NULL, 0, 711 MAC_ERRf, MAC_ERRf, 712 INVALIDm, "CLMAC TX CDC single bit", 713 CLMAC_INTR_ENABLEr, EN_TX_CDC_SINGLE_BIT_ERRf, NULL, 714 INVALIDr, INVALIDf, NULL, 715 CLMAC_INTR_STATUSr, NULL, SUM_TX_CDC_SINGLE_BIT_ERRf, NULL, 716 CLMAC_CLEAR_ECC_STATUSr, CLEAR_TX_CDC_SINGLE_BIT_ERRf, NULL 717 }, 718 { _SOC_PARITY_TYPE_CLMAC, NULL, 0, 719 MAC_ERRf, MAC_ERRf, 720 INVALIDm, "CLMAC TX CDC double bits", 721 CLMAC_INTR_ENABLEr, EN_TX_CDC_DOUBLE_BIT_ERRf, NULL, 722 INVALIDr, INVALIDf, NULL, 723 CLMAC_INTR_STATUSr, NULL, SUM_TX_CDC_DOUBLE_BIT_ERRf, NULL, 724 CLMAC_CLEAR_ECC_STATUSr, CLEAR_TX_CDC_DOUBLE_BIT_ERRf, NULL 725 }, 726 { _SOC_PARITY_TYPE_CLMAC, NULL, 0, 727 MAC_ERRf, MAC_ERRf, 728 INVALIDm, "CLMAC RX CDC single bit", 729 CLMAC_INTR_ENABLEr, EN_RX_CDC_SINGLE_BIT_ERRf, NULL, 730 INVALIDr, INVALIDf, NULL, 731 CLMAC_INTR_STATUSr, NULL, SUM_RX_CDC_SINGLE_BIT_ERRf, NULL, 732 CLMAC_CLEAR_ECC_STATUSr, CLEAR_RX_CDC_SINGLE_BIT_ERRf, NULL 733 }, 734 { _SOC_PARITY_TYPE_CLMAC, NULL, 0, 735 MAC_ERRf, MAC_ERRf, 736 INVALIDm, "CLMAC RX CDC double bits", 737 CLMAC_INTR_ENABLEr, EN_RX_CDC_DOUBLE_BIT_ERRf, NULL, 738 INVALIDr, INVALIDf, NULL, 739 CLMAC_INTR_STATUSr, NULL, SUM_RX_CDC_DOUBLE_BIT_ERRf, NULL, 740 CLMAC_CLEAR_ECC_STATUSr, CLEAR_RX_CDC_DOUBLE_BIT_ERRf, NULL 741 }, 742 { _SOC_PARITY_TYPE_CLMAC, NULL, 0, 743 MAC_ERRf, MAC_ERRf, 744 INVALIDm, "CLMAC RX TS MEM single bit", 745 CLMAC_INTR_ENABLEr, EN_RX_TS_MEM_SINGLE_BIT_ERRf, NULL, 746 INVALIDr, INVALIDf, NULL, 747 CLMAC_INTR_STATUSr, NULL, SUM_RX_TS_MEM_SINGLE_BIT_ERRf, NULL, 748 CLMAC_CLEAR_ECC_STATUSr, CLEAR_RX_TS_MEM_SINGLE_BIT_ERRf, NULL 749 }, 750 { _SOC_PARITY_TYPE_CLMAC, NULL, 0, 751 MAC_ERRf, MAC_ERRf, 752 INVALIDm, "CLMAC RX TS MEM double bits", 753 CLMAC_INTR_ENABLEr, EN_RX_TS_MEM_DOUBLE_BIT_ERRf, NULL, 754 INVALIDr, INVALIDf, NULL, 755 CLMAC_INTR_STATUSr, NULL, SUM_TX_CDC_DOUBLE_BIT_ERRf, NULL, 756 CLMAC_CLEAR_ECC_STATUSr, CLEAR_RX_TS_MEM_DOUBLE_BIT_ERRf, NULL 757 }, 758 { _SOC_PARITY_TYPE_NONE } /* table terminator */ 759 }; 760 #endif 761 762 static _soc_th_ser_reg_t _soc_th_idb_status_reg[] = { 763 { IDB_OBM0_DATA_ECC_STATUSr, "IDB OBM0 packet data memory" }, 764 { IDB_OBM1_DATA_ECC_STATUSr, "IDB OBM1 packet data memory" }, 765 { IDB_OBM2_DATA_ECC_STATUSr, "IDB OBM2 packet data memory" }, 766 { IDB_OBM3_DATA_ECC_STATUSr, "IDB OBM3 packet data memory" }, 767 { IDB_OBM4_DATA_ECC_STATUSr, "IDB OBM4 packet data memory" }, 768 { IDB_OBM5_DATA_ECC_STATUSr, "IDB OBM5 packet data memory" }, 769 { IDB_OBM6_DATA_ECC_STATUSr, "IDB OBM6 packet data memory" }, 770 { IDB_OBM7_DATA_ECC_STATUSr, "IDB OBM7 packet data memory" }, 771 { IDB_OBM0_CA_ECC_STATUSr, "IDB OBM0 CA packet buffer memory" }, 772 { IDB_OBM1_CA_ECC_STATUSr, "IDB OBM1 CA packet buffer memory" }, 773 { IDB_OBM2_CA_ECC_STATUSr, "IDB OBM2 CA packet buffer memory" }, 774 { IDB_OBM3_CA_ECC_STATUSr, "IDB OBM3 CA packet buffer memory" }, 775 { IDB_OBM4_CA_ECC_STATUSr, "IDB OBM4 CA packet buffer memory" }, 776 { IDB_OBM5_CA_ECC_STATUSr, "IDB OBM5 CA packet buffer memory" }, 777 { IDB_OBM6_CA_ECC_STATUSr, "IDB OBM6 CA packet buffer memory" }, 778 { IDB_OBM7_CA_ECC_STATUSr, "IDB OBM7 CA packet buffer memory" }, 779 { IDB_CA_CPU_ECC_STATUSr, "CA-CPU packet buffer memory" }, 780 { IDB_CA_LPBK_ECC_STATUSr, "CA-LPBK packet buffer memory" }, 781 { IDB_IS_TDM_CAL_ECC_STATUSr, "IDB IS_TDM0,1 calendar" }, 782 { INVALIDr } 783 }; 784 785 /* OBM queue buffer */ 786 static _soc_th_ser_reg_t _soc_th_idb_status_reg2[] = { 787 { IDB_OBM0_QUEUE_ECC_STATUSr, "IDB OBM0 queue FIFO memory" }, 788 { IDB_OBM1_QUEUE_ECC_STATUSr, "IDB OBM1 queue FIFO memory" }, 789 { IDB_OBM2_QUEUE_ECC_STATUSr, "IDB OBM2 queue FIFO memory" }, 790 { IDB_OBM3_QUEUE_ECC_STATUSr, "IDB OBM3 queue FIFO memory" }, 791 { IDB_OBM4_QUEUE_ECC_STATUSr, "IDB OBM4 queue FIFO memory" }, 792 { IDB_OBM5_QUEUE_ECC_STATUSr, "IDB OBM5 queue FIFO memory" }, 793 { IDB_OBM6_QUEUE_ECC_STATUSr, "IDB OBM6 queue FIFO memory" }, 794 { IDB_OBM7_QUEUE_ECC_STATUSr, "IDB OBM7 queue FIFO memory" }, 795 { INVALIDr } 796 }; 797 798 static _soc_th_ser_info_t _soc_th_idb_ser_info[] = { 799 /* OBM queue buffer - keep this as first entry */ 800 { _SOC_PARITY_TYPE_ECC, NULL, 0, 801 MEM_ERROR_OCCURREDf, MEM_ERROR_OCCURREDf, 802 INVALIDm, "IP IDB memory", 803 INVALIDr, INVALIDf, NULL, 804 INVALIDr, INVALIDf, NULL, 805 INVALIDr, _soc_th_idb_status_reg2, ECC_ERRf, NULL, 806 INVALIDr, INVALIDf, NULL 807 }, 808 { _SOC_PARITY_TYPE_ECC, NULL, 0, 809 MEM_ERROR_OCCURREDf, MEM_ERROR_OCCURREDf, 810 INVALIDm, "IP IDB memory", 811 INVALIDr, INVALIDf, NULL, 812 INVALIDr, INVALIDf, NULL, 813 INVALIDr, _soc_th_idb_status_reg, ECC_ERRf, NULL, 814 INVALIDr, INVALIDf, NULL 815 }, 816 { _SOC_PARITY_TYPE_NONE } /* table terminator */ 817 }; 818 819 /* Setup dynamically in enable ser */ 820 static uint32 _soc_th_ip_pipe_fifo_bmask[SOC_MAX_NUM_DEVICES][4]; 821 822 #define _SOC_TH_IPIPE0_IP0_INTR 0x00000200 823 #define _SOC_TH_IPIPE1_IP0_INTR 0x00000400 824 #define _SOC_TH_IPIPE2_IP0_INTR 0x00000800 825 #define _SOC_TH_IPIPE3_IP0_INTR 0x00001000 826 static const 827 _soc_th_ser_route_block_t _soc_th_ser_route_blocks[] = { 828 { 3, 0x00000010, /* MMU_TO_CMIC_MEMFAIL_INTR */ 829 SOC_BLK_MMU, -1, INVALIDr, INVALIDr, INVALIDf, 830 _soc_th_mmu_top_ser_info, 0 }, 831 /* xsm: not using MMU_GLB or MMU_XPE or MMU_SC is on purpose */ 832 { 3, 0x00000020, /* PIPE0_EP2_TO_CMIC_PERR_INTR */ 833 SOC_BLK_EPIPE, 0, EGR_INTR_ENABLEr, INVALIDr, SER_FIFO_NON_EMPTYf, 834 NULL, 0 }, 835 { 3, 0x00000040, /* PIPE1_EP2_TO_CMIC_PERR_INTR */ 836 SOC_BLK_EPIPE, 1, EGR_INTR_ENABLEr, INVALIDr, SER_FIFO_NON_EMPTYf, 837 NULL, 0 }, 838 { 3, 0x00000080, /* PIPE2_EP2_TO_CMIC_PERR_INTR */ 839 SOC_BLK_EPIPE, 2, EGR_INTR_ENABLEr, INVALIDr, SER_FIFO_NON_EMPTYf, 840 NULL, 0 }, 841 { 3, 0x00000100, /* PIPE3_EP2_TO_CMIC_PERR_INTR */ 842 SOC_BLK_EPIPE, 3, EGR_INTR_ENABLEr, INVALIDr, SER_FIFO_NON_EMPTYf, 843 NULL, 0 }, 844 { 3, _SOC_TH_IPIPE0_IP0_INTR, /* PIPE0_IP0_TO_CMIC_PERR_INTR */ 845 /* Note: This is an exception for being legacy style in IP */ 846 SOC_BLK_IPIPE, 0, IP0_INTR_ENABLEr, IP0_INTR_STATUSr, INVALIDf, 847 _soc_th_idb_ser_info, 0 }, 848 { 3, _SOC_TH_IPIPE1_IP0_INTR, /* PIPE1_IP0_TO_CMIC_PERR_INTR */ 849 /* Note: This is an exception for being legacy style in IP */ 850 SOC_BLK_IPIPE, 1, IP0_INTR_ENABLEr, IP0_INTR_STATUSr, INVALIDf, 851 _soc_th_idb_ser_info, 0 }, 852 { 3, _SOC_TH_IPIPE2_IP0_INTR, /* PIPE2_IP0_TO_CMIC_PERR_INTR */ 853 /* Note: This is an exception for being legacy style in IP */ 854 SOC_BLK_IPIPE, 2, IP0_INTR_ENABLEr, IP0_INTR_STATUSr, INVALIDf, 855 _soc_th_idb_ser_info, 0 }, 856 { 3, _SOC_TH_IPIPE3_IP0_INTR, /* PIPE3_IP0_TO_CMIC_PERR_INTR */ 857 /* Note: This is an exception for being legacy style in IP */ 858 SOC_BLK_IPIPE, 3, IP0_INTR_ENABLEr, IP0_INTR_STATUSr, INVALIDf, 859 _soc_th_idb_ser_info, 0 }, 860 { 3, 0x00002000, /* PIPE0_IP5_TO_CMIC_PERR_INTR */ 861 SOC_BLK_IPIPE, 0, INVALIDr, INVALIDr, INVALIDf, 862 NULL, 0 }, 863 { 3, 0x00004000, /* PIPE1_IP5_TO_CMIC_PERR_INTR */ 864 SOC_BLK_IPIPE, 1, INVALIDr, INVALIDr, INVALIDf, 865 NULL, 0 }, 866 { 3, 0x00008000, /* PIPE2_IP5_TO_CMIC_PERR_INTR */ 867 SOC_BLK_IPIPE, 2, INVALIDr, INVALIDr, INVALIDf, 868 NULL, 0 }, 869 { 3, 0x00010000, /* PIPE3_IP5_TO_CMIC_PERR_INTR */ 870 SOC_BLK_IPIPE, 3, INVALIDr, INVALIDr, INVALIDf, 871 NULL, 0 }, 872 { 4, 0x00000001, /* PM0_INTR */ 873 SOC_BLK_CLPORT, 0, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 874 _soc_th_pm_clp_ser_info, 0 }, 875 { 4, 0x00000002, /* PM1_INTR */ 876 SOC_BLK_CLPORT, 0, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 877 _soc_th_pm_clp_ser_info, 1 }, 878 { 4, 0x00000004, /* PM2_INTR */ 879 SOC_BLK_CLPORT, 0, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 880 _soc_th_pm_clp_ser_info, 2 }, 881 { 4, 0x00000008, /* PM3_INTR */ 882 SOC_BLK_CLPORT, 0, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 883 _soc_th_pm_clp_ser_info, 3 }, 884 { 4, 0x00000010, /* PM4_INTR */ 885 SOC_BLK_CLPORT, 0, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 886 _soc_th_pm_clp_ser_info, 4 }, 887 { 4, 0x00000020, /* PM5_INTR */ 888 SOC_BLK_CLPORT, 0, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 889 _soc_th_pm_clp_ser_info, 5 }, 890 { 4, 0x00000040, /* PM6_INTR */ 891 SOC_BLK_CLPORT, 0, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 892 _soc_th_pm_clp_ser_info, 6 }, 893 { 4, 0x00000080, /* PM7_INTR */ 894 SOC_BLK_CLPORT, 0, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 895 _soc_th_pm_clp_ser_info, 7 }, 896 { 4, 0x00000100, /* PM8_INTR */ 897 SOC_BLK_CLPORT, 1, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 898 _soc_th_pm_clp_ser_info, 8 }, 899 { 4, 0x00000200, /* PM9_INTR */ 900 SOC_BLK_CLPORT, 1, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 901 _soc_th_pm_clp_ser_info, 9 }, 902 { 4, 0x00000400, /* PM10_INTR */ 903 SOC_BLK_CLPORT, 1, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 904 _soc_th_pm_clp_ser_info, 10 }, 905 { 4, 0x00000800, /* PM11_INTR */ 906 SOC_BLK_CLPORT, 1, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 907 _soc_th_pm_clp_ser_info, 11 }, 908 { 4, 0x00001000, /* PM12_INTR */ 909 SOC_BLK_CLPORT, 1, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 910 _soc_th_pm_clp_ser_info, 12 }, 911 { 4, 0x00002000, /* PM13_INTR */ 912 SOC_BLK_CLPORT, 1, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 913 _soc_th_pm_clp_ser_info, 13 }, 914 { 4, 0x00004000, /* PM14_INTR */ 915 SOC_BLK_CLPORT, 1, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 916 _soc_th_pm_clp_ser_info, 14 }, 917 { 4, 0x00008000, /* PM15_INTR */ 918 SOC_BLK_CLPORT, 1, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 919 _soc_th_pm_clp_ser_info, 15 }, 920 { 4, 0x00010000, /* PM16_INTR */ 921 SOC_BLK_CLPORT, 2, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 922 _soc_th_pm_clp_ser_info, 16 }, 923 { 4, 0x00020000, /* PM17_INTR */ 924 SOC_BLK_CLPORT, 2, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 925 _soc_th_pm_clp_ser_info, 17 }, 926 { 4, 0x00040000, /* PM18_INTR */ 927 SOC_BLK_CLPORT, 2, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 928 _soc_th_pm_clp_ser_info, 18 }, 929 { 4, 0x00080000, /* PM19_INTR */ 930 SOC_BLK_CLPORT, 2, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 931 _soc_th_pm_clp_ser_info, 19 }, 932 { 4, 0x00100000, /* PM20_INTR */ 933 SOC_BLK_CLPORT, 2, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 934 _soc_th_pm_clp_ser_info, 20 }, 935 { 4, 0x00200000, /* PM21_INTR */ 936 SOC_BLK_CLPORT, 2, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 937 _soc_th_pm_clp_ser_info, 21 }, 938 { 4, 0x00400000, /* PM22_INTR */ 939 SOC_BLK_CLPORT, 2, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 940 _soc_th_pm_clp_ser_info, 22 }, 941 { 4, 0x00800000, /* PM23_INTR */ 942 SOC_BLK_CLPORT, 2, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 943 _soc_th_pm_clp_ser_info, 23 }, 944 { 4, 0x01000000, /* PM24_INTR */ 945 SOC_BLK_CLPORT, 3, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 946 _soc_th_pm_clp_ser_info, 24 }, 947 { 4, 0x02000000, /* PM25_INTR */ 948 SOC_BLK_CLPORT, 3, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 949 _soc_th_pm_clp_ser_info, 25 }, 950 { 4, 0x04000000, /* PM26_INTR */ 951 SOC_BLK_CLPORT, 3, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 952 _soc_th_pm_clp_ser_info, 26 }, 953 { 4, 0x08000000, /* PM27_INTR */ 954 SOC_BLK_CLPORT, 3, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 955 _soc_th_pm_clp_ser_info, 27 }, 956 { 4, 0x10000000, /* PM28_INTR */ 957 SOC_BLK_CLPORT, 3, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 958 _soc_th_pm_clp_ser_info, 28 }, 959 { 4, 0x20000000, /* PM29_INTR */ 960 SOC_BLK_CLPORT, 3, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 961 _soc_th_pm_clp_ser_info, 29 }, 962 { 4, 0x40000000, /* PM30_INTR */ 963 SOC_BLK_CLPORT, 3, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 964 _soc_th_pm_clp_ser_info, 30 }, 965 { 4, 0x80000000, /* PM31_INTR */ 966 SOC_BLK_CLPORT, 3, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 967 _soc_th_pm_clp_ser_info, 31 }, 968 { 5, 0x00000001, /* PM32_INTR */ 969 SOC_BLK_XLPORT, 1, XLPORT_INTR_ENABLEr, XLPORT_INTR_STATUSr, INVALIDf, 970 _soc_th_pm_xlp_ser_info, 0 }, 971 { 0 } /* table terminator */ 972 }; 973 974 static soc_mem_t _soc_th_skip_populating[] = { 975 /* Shared MMU_WRED_ENABLE_ECCP_MEM.PROFILE_ECCP_EN */ 976 MMU_WRED_DROP_CURVE_PROFILE_0m, 977 MMU_WRED_DROP_CURVE_PROFILE_0_Am, 978 MMU_WRED_DROP_CURVE_PROFILE_0_Bm, 979 MMU_WRED_DROP_CURVE_PROFILE_1m, 980 MMU_WRED_DROP_CURVE_PROFILE_1_Am, 981 MMU_WRED_DROP_CURVE_PROFILE_1_Bm, 982 MMU_WRED_DROP_CURVE_PROFILE_2m, 983 MMU_WRED_DROP_CURVE_PROFILE_2_Am, 984 MMU_WRED_DROP_CURVE_PROFILE_2_Bm, 985 MMU_WRED_DROP_CURVE_PROFILE_3m, 986 MMU_WRED_DROP_CURVE_PROFILE_3_Am, 987 MMU_WRED_DROP_CURVE_PROFILE_3_Bm, 988 MMU_WRED_DROP_CURVE_PROFILE_4m, 989 MMU_WRED_DROP_CURVE_PROFILE_4_Am, 990 MMU_WRED_DROP_CURVE_PROFILE_4_Bm, 991 MMU_WRED_DROP_CURVE_PROFILE_5m, 992 MMU_WRED_DROP_CURVE_PROFILE_5_Am, 993 MMU_WRED_DROP_CURVE_PROFILE_5_Bm, 994 MMU_WRED_DROP_CURVE_PROFILE_6m, 995 MMU_WRED_DROP_CURVE_PROFILE_6_Am, 996 MMU_WRED_DROP_CURVE_PROFILE_6_Bm, 997 MMU_WRED_DROP_CURVE_PROFILE_7m, 998 MMU_WRED_DROP_CURVE_PROFILE_7_Am, 999 MMU_WRED_DROP_CURVE_PROFILE_7_Bm, 1000 MMU_WRED_DROP_CURVE_PROFILE_8m, 1001 MMU_WRED_DROP_CURVE_PROFILE_8_Am, 1002 MMU_WRED_DROP_CURVE_PROFILE_8_Bm, 1003 INVALIDm 1004 }; 1005 1006 #ifdef BCM_TOMAHAWK2_SUPPORT 1007 extern _soc_bus_ser_en_info_t _soc_bcm56970_a0_ip_bus_ser_info[]; 1008 extern _soc_buffer_ser_en_info_t _soc_bcm56970_a0_ip_buffer_ser_info[]; 1009 extern _soc_bus_ser_en_info_t _soc_bcm56970_a0_ep_bus_ser_info[]; 1010 extern _soc_buffer_ser_en_info_t _soc_bcm56970_a0_ep_buffer_ser_info[]; 1011 1012 _soc_buffer_ser_en_info_t _soc_th2_ifp_buffer_ser_info[] = { 1013 { "METER MUX DATA STAGING", IFP_PARITY_CONTROLr, METER_MUX_DATA_STAGING_PARITY_ENf, INVALIDr, INVALIDf }, 1014 { "PORT METER MAP", IFP_PARITY_CONTROLr, PORT_METER_MAP_PARITY_ENf, INVALIDr, INVALIDf }, 1015 { "COUNTER MUX DATA STAGING", IFP_PARITY_CONTROLr, COUNTER_MUX_DATA_STAGING_PARITY_ENf, INVALIDr, INVALIDf }, 1016 { "IFP COUNTER", IFP_PARITY_CONTROLr, COUNTER_PARITY_ENf, INVALIDr, INVALIDf }, 1017 { "", INVALIDr } 1018 }; 1019 1020 _soc_bus_buffer_ser_force_info_t ser_th2_bus_buffer_skip_test[] = { 1021 { "DPP_OUTPUT_EVENT_FIFO", SW4_SER_CONTROLr, EVENT_FIFO_ECC_FORCE_ERRf }, 1022 { "SLOT_PIPELINE", SW4_SER_CONTROLr, SLOT_PIPELINE_ECC_FORCE_ERRf }, 1023 { "CELL_QUEUE", SW4_SER_CONTROLr, CELL_QUEUE_ECC_FORCE_ERRf }, 1024 { "", INVALIDr } /* end */ 1025 }; 1026 1027 uint32 ser_th2_bus_buffer_hwbase[] = { 1028 0x18, /* IRSEL2_BUS */ 1029 0x15, /* IRSEL1_BUS */ 1030 0, /* DPP_OUTPUT_EVENT_FIFO */ 1031 0, /* SLOT_PIPELINE */ 1032 0x5b, /* EHCPM_BUS */ 1033 0x11, /* IPARS_BUS */ 1034 0x41, /* EP_INITBUF_RAM_WRAPPER */ 1035 0x12, /* IVXLT_BUS */ 1036 0x5a, /* EVLAN_BUS */ 1037 0x16, /* ISW1_BUS */ 1038 0x13, /* VP_BUS */ 1039 0xb, /* IPARS_IVP_PT_BUS */ 1040 0x17, /* IFP_BUS */ 1041 0xf, /* ISW1_ISW2_PT_BUS */ 1042 0xc, /* IVP_ISW1_PT_BUS */ 1043 0x5e, /* EFP_BUS */ 1044 0x5f, /* EP_PT_BUS */ 1045 0x14, /* IFWD_BUS */ 1046 0x19, /* ISW2_BUS */ 1047 0x5c, /* EPMOD_BUS */ 1048 0x40, /* IP_PACKET_BUFFER */ 1049 0x72, /* EP_EFPBUF */ 1050 0, /* CELL_QUEUE */ 1051 0xd, /* IFWD_ISW1_PT_BUS */ 1052 0x5d, /* EFPPARS_BUS */ 1053 0 /* EOP_BUFFER_MTU */ 1054 }; 1055 1056 soc_field_t _soc_th2_idb_ca_lpbk_enable_fields[] = { 1057 CA_LPBK_ECC_ENABLEf, 1058 CA_LPBK_ERR1_RPT_ENf, 1059 INVALIDf 1060 }; 1061 1062 soc_field_t _soc_th2_idb_ca_cpu_enable_fields[] = { 1063 CA_CPU_ECC_ENABLEf, 1064 CA_CPU_ERR1_RPT_ENf, 1065 INVALIDf 1066 }; 1067 1068 soc_field_t _soc_th2_idb_sop_event_enable_fields[] = { 1069 SOP_EVENT_ECC_ENABLEf, 1070 SOP_EVENT_ERR1_RPT_ENf, 1071 INVALIDf 1072 }; 1073 1074 soc_field_t _soc_th2_idb_eop_event_enable_fields[] = { 1075 EOP_EVENT_ECC_ENABLEf, 1076 EOP_EVENT_ERR1_RPT_ENf, 1077 INVALIDf 1078 }; 1079 1080 static _soc_th_ser_info_t _soc_th2_idb_ser_info[] = { 1081 { _SOC_PARITY_TYPE_ECC, NULL, 0, 1082 MEM_ERROR_OCCURREDf, MEM_ERROR_OCCURREDf, 1083 INVALIDm, "OBM0 DATA FIFO", 1084 IDB_OBM0_SER_CONTROLr, DATA_ECC_ENABLEf, NULL, 1085 INVALIDr, INVALIDf, NULL, 1086 IDB_OBM0_DATA_ECC_STATUSr, NULL, ECC_ERRf, NULL, 1087 INVALIDr, INVALIDf, NULL 1088 }, 1089 { _SOC_PARITY_TYPE_ECC, NULL, 0, 1090 MEM_ERROR_OCCURREDf, MEM_ERROR_OCCURREDf, 1091 INVALIDm, "OBM1 DATA FIFO", 1092 IDB_OBM1_SER_CONTROLr, DATA_ECC_ENABLEf, NULL, 1093 INVALIDr, INVALIDf, NULL, 1094 IDB_OBM1_DATA_ECC_STATUSr, NULL, ECC_ERRf, NULL, 1095 INVALIDr, INVALIDf, NULL 1096 }, 1097 { _SOC_PARITY_TYPE_ECC, NULL, 0, 1098 MEM_ERROR_OCCURREDf, MEM_ERROR_OCCURREDf, 1099 INVALIDm, "OBM2 DATA FIFO", 1100 IDB_OBM2_SER_CONTROLr, DATA_ECC_ENABLEf, NULL, 1101 INVALIDr, INVALIDf, NULL, 1102 IDB_OBM2_DATA_ECC_STATUSr, NULL, ECC_ERRf, NULL, 1103 INVALIDr, INVALIDf, NULL 1104 }, 1105 { _SOC_PARITY_TYPE_ECC, NULL, 0, 1106 MEM_ERROR_OCCURREDf, MEM_ERROR_OCCURREDf, 1107 INVALIDm, "OBM3 DATA FIFO", 1108 IDB_OBM3_SER_CONTROLr, DATA_ECC_ENABLEf, NULL, 1109 INVALIDr, INVALIDf, NULL, 1110 IDB_OBM3_DATA_ECC_STATUSr, NULL, ECC_ERRf, NULL, 1111 INVALIDr, INVALIDf, NULL 1112 }, 1113 { _SOC_PARITY_TYPE_ECC, NULL, 0, 1114 MEM_ERROR_OCCURREDf, MEM_ERROR_OCCURREDf, 1115 INVALIDm, "OBM4 DATA FIFO", 1116 IDB_OBM4_SER_CONTROLr, DATA_ECC_ENABLEf, NULL, 1117 INVALIDr, INVALIDf, NULL, 1118 IDB_OBM4_DATA_ECC_STATUSr, NULL, ECC_ERRf, NULL, 1119 INVALIDr, INVALIDf, NULL 1120 }, 1121 { _SOC_PARITY_TYPE_ECC, NULL, 0, 1122 MEM_ERROR_OCCURREDf, MEM_ERROR_OCCURREDf, 1123 INVALIDm, "OBM5 DATA FIFO", 1124 IDB_OBM5_SER_CONTROLr, DATA_ECC_ENABLEf, NULL, 1125 INVALIDr, INVALIDf, NULL, 1126 IDB_OBM5_DATA_ECC_STATUSr, NULL, ECC_ERRf, NULL, 1127 INVALIDr, INVALIDf, NULL 1128 }, 1129 { _SOC_PARITY_TYPE_ECC, NULL, 0, 1130 MEM_ERROR_OCCURREDf, MEM_ERROR_OCCURREDf, 1131 INVALIDm, "OBM6 DATA FIFO", 1132 IDB_OBM6_SER_CONTROLr, DATA_ECC_ENABLEf, NULL, 1133 INVALIDr, INVALIDf, NULL, 1134 IDB_OBM6_DATA_ECC_STATUSr, NULL, ECC_ERRf, NULL, 1135 INVALIDr, INVALIDf, NULL 1136 }, 1137 { _SOC_PARITY_TYPE_ECC, NULL, 0, 1138 MEM_ERROR_OCCURREDf, MEM_ERROR_OCCURREDf, 1139 INVALIDm, "OBM7 DATA FIFO", 1140 IDB_OBM7_SER_CONTROLr, DATA_ECC_ENABLEf, NULL, 1141 INVALIDr, INVALIDf, NULL, 1142 IDB_OBM7_DATA_ECC_STATUSr, NULL, ECC_ERRf, NULL, 1143 INVALIDr, INVALIDf, NULL 1144 }, 1145 { _SOC_PARITY_TYPE_ECC, NULL, 0, 1146 MEM_ERROR_OCCURREDf, MEM_ERROR_OCCURREDf, 1147 INVALIDm, "OBM8 DATA FIFO", 1148 IDB_OBM8_SER_CONTROLr, DATA_ECC_ENABLEf, NULL, 1149 INVALIDr, INVALIDf, NULL, 1150 IDB_OBM8_DATA_ECC_STATUSr, NULL, ECC_ERRf, NULL, 1151 INVALIDr, INVALIDf, NULL 1152 }, 1153 { _SOC_PARITY_TYPE_ECC, NULL, 0, 1154 MEM_ERROR_OCCURREDf, MEM_ERROR_OCCURREDf, 1155 INVALIDm, "OBM9 DATA FIFO", 1156 IDB_OBM9_SER_CONTROLr, DATA_ECC_ENABLEf, NULL, 1157 INVALIDr, INVALIDf, NULL, 1158 IDB_OBM9_DATA_ECC_STATUSr, NULL, ECC_ERRf, NULL, 1159 INVALIDr, INVALIDf, NULL 1160 }, 1161 { _SOC_PARITY_TYPE_ECC, NULL, 0, 1162 MEM_ERROR_OCCURREDf, MEM_ERROR_OCCURREDf, 1163 INVALIDm, "OBM10 DATA FIFO", 1164 IDB_OBM10_SER_CONTROLr, DATA_ECC_ENABLEf, NULL, 1165 INVALIDr, INVALIDf, NULL, 1166 IDB_OBM10_DATA_ECC_STATUSr, NULL, ECC_ERRf, NULL, 1167 INVALIDr, INVALIDf, NULL 1168 }, 1169 { _SOC_PARITY_TYPE_ECC, NULL, 0, 1170 MEM_ERROR_OCCURREDf, MEM_ERROR_OCCURREDf, 1171 INVALIDm, "OBM11 DATA FIFO", 1172 IDB_OBM11_SER_CONTROLr, DATA_ECC_ENABLEf, NULL, 1173 INVALIDr, INVALIDf, NULL, 1174 IDB_OBM11_DATA_ECC_STATUSr, NULL, ECC_ERRf, NULL, 1175 INVALIDr, INVALIDf, NULL 1176 }, 1177 { _SOC_PARITY_TYPE_ECC, NULL, 0, 1178 MEM_ERROR_OCCURREDf, MEM_ERROR_OCCURREDf, 1179 INVALIDm, "OBM12 DATA FIFO", 1180 IDB_OBM12_SER_CONTROLr, DATA_ECC_ENABLEf, NULL, 1181 INVALIDr, INVALIDf, NULL, 1182 IDB_OBM12_DATA_ECC_STATUSr, NULL, ECC_ERRf, NULL, 1183 INVALIDr, INVALIDf, NULL 1184 }, 1185 { _SOC_PARITY_TYPE_ECC, NULL, 0, 1186 MEM_ERROR_OCCURREDf, MEM_ERROR_OCCURREDf, 1187 INVALIDm, "OBM13 DATA FIFO", 1188 IDB_OBM13_SER_CONTROLr, DATA_ECC_ENABLEf, NULL, 1189 INVALIDr, INVALIDf, NULL, 1190 IDB_OBM13_DATA_ECC_STATUSr, NULL, ECC_ERRf, NULL, 1191 INVALIDr, INVALIDf, NULL 1192 }, 1193 { _SOC_PARITY_TYPE_ECC, NULL, 0, 1194 MEM_ERROR_OCCURREDf, MEM_ERROR_OCCURREDf, 1195 INVALIDm, "OBM14 DATA FIFO", 1196 IDB_OBM14_SER_CONTROLr, DATA_ECC_ENABLEf, NULL, 1197 INVALIDr, INVALIDf, NULL, 1198 IDB_OBM14_DATA_ECC_STATUSr, NULL, ECC_ERRf, NULL, 1199 INVALIDr, INVALIDf, NULL 1200 }, 1201 { _SOC_PARITY_TYPE_ECC, NULL, 0, 1202 MEM_ERROR_OCCURREDf, MEM_ERROR_OCCURREDf, 1203 INVALIDm, "OBM15 DATA FIFO", 1204 IDB_OBM15_SER_CONTROLr, DATA_ECC_ENABLEf, NULL, 1205 INVALIDr, INVALIDf, NULL, 1206 IDB_OBM15_DATA_ECC_STATUSr, NULL, ECC_ERRf, NULL, 1207 INVALIDr, INVALIDf, NULL 1208 }, 1209 { _SOC_PARITY_TYPE_ECC, NULL, 0, 1210 MEM_ERROR_OCCURREDf, MEM_ERROR_OCCURREDf, 1211 INVALIDm, "OBM0 CELL ASSEM BUFFER", 1212 IDB_OBM0_SER_CONTROLr, CA_FIFO_ECC_ENABLEf, NULL, 1213 INVALIDr, INVALIDf, NULL, 1214 IDB_OBM0_CA_ECC_STATUSr, NULL, ECC_ERRf, NULL, 1215 INVALIDr, INVALIDf, NULL 1216 }, 1217 { _SOC_PARITY_TYPE_ECC, NULL, 0, 1218 MEM_ERROR_OCCURREDf, MEM_ERROR_OCCURREDf, 1219 INVALIDm, "OBM1 CELL ASSEM BUFFER", 1220 IDB_OBM1_SER_CONTROLr, CA_FIFO_ECC_ENABLEf, NULL, 1221 INVALIDr, INVALIDf, NULL, 1222 IDB_OBM1_CA_ECC_STATUSr, NULL, ECC_ERRf, NULL, 1223 INVALIDr, INVALIDf, NULL 1224 }, 1225 { _SOC_PARITY_TYPE_ECC, NULL, 0, 1226 MEM_ERROR_OCCURREDf, MEM_ERROR_OCCURREDf, 1227 INVALIDm, "OBM2 CELL ASSEM BUFFER", 1228 IDB_OBM2_SER_CONTROLr, CA_FIFO_ECC_ENABLEf, NULL, 1229 INVALIDr, INVALIDf, NULL, 1230 IDB_OBM2_CA_ECC_STATUSr, NULL, ECC_ERRf, NULL, 1231 INVALIDr, INVALIDf, NULL 1232 }, 1233 { _SOC_PARITY_TYPE_ECC, NULL, 0, 1234 MEM_ERROR_OCCURREDf, MEM_ERROR_OCCURREDf, 1235 INVALIDm, "OBM3 CELL ASSEM BUFFER", 1236 IDB_OBM3_SER_CONTROLr, CA_FIFO_ECC_ENABLEf, NULL, 1237 INVALIDr, INVALIDf, NULL, 1238 IDB_OBM3_CA_ECC_STATUSr, NULL, ECC_ERRf, NULL, 1239 INVALIDr, INVALIDf, NULL 1240 }, 1241 { _SOC_PARITY_TYPE_ECC, NULL, 0, 1242 MEM_ERROR_OCCURREDf, MEM_ERROR_OCCURREDf, 1243 INVALIDm, "OBM4 CELL ASSEM BUFFER", 1244 IDB_OBM4_SER_CONTROLr, CA_FIFO_ECC_ENABLEf, NULL, 1245 INVALIDr, INVALIDf, NULL, 1246 IDB_OBM4_CA_ECC_STATUSr, NULL, ECC_ERRf, NULL, 1247 INVALIDr, INVALIDf, NULL 1248 }, 1249 { _SOC_PARITY_TYPE_ECC, NULL, 0, 1250 MEM_ERROR_OCCURREDf, MEM_ERROR_OCCURREDf, 1251 INVALIDm, "OBM5 CELL ASSEM BUFFER", 1252 IDB_OBM5_SER_CONTROLr, CA_FIFO_ECC_ENABLEf, NULL, 1253 INVALIDr, INVALIDf, NULL, 1254 IDB_OBM5_CA_ECC_STATUSr, NULL, ECC_ERRf, NULL, 1255 INVALIDr, INVALIDf, NULL 1256 }, 1257 { _SOC_PARITY_TYPE_ECC, NULL, 0, 1258 MEM_ERROR_OCCURREDf, MEM_ERROR_OCCURREDf, 1259 INVALIDm, "OBM6 CELL ASSEM BUFFER", 1260 IDB_OBM6_SER_CONTROLr, CA_FIFO_ECC_ENABLEf, NULL, 1261 INVALIDr, INVALIDf, NULL, 1262 IDB_OBM6_CA_ECC_STATUSr, NULL, ECC_ERRf, NULL, 1263 INVALIDr, INVALIDf, NULL 1264 }, 1265 { _SOC_PARITY_TYPE_ECC, NULL, 0, 1266 MEM_ERROR_OCCURREDf, MEM_ERROR_OCCURREDf, 1267 INVALIDm, "OBM7 CELL ASSEM BUFFER", 1268 IDB_OBM7_SER_CONTROLr, CA_FIFO_ECC_ENABLEf, NULL, 1269 INVALIDr, INVALIDf, NULL, 1270 IDB_OBM7_CA_ECC_STATUSr, NULL, ECC_ERRf, NULL, 1271 INVALIDr, INVALIDf, NULL 1272 }, 1273 { _SOC_PARITY_TYPE_ECC, NULL, 0, 1274 MEM_ERROR_OCCURREDf, MEM_ERROR_OCCURREDf, 1275 INVALIDm, "OBM8 CELL ASSEM BUFFER", 1276 IDB_OBM8_SER_CONTROLr, CA_FIFO_ECC_ENABLEf, NULL, 1277 INVALIDr, INVALIDf, NULL, 1278 IDB_OBM8_CA_ECC_STATUSr, NULL, ECC_ERRf, NULL, 1279 INVALIDr, INVALIDf, NULL 1280 }, 1281 { _SOC_PARITY_TYPE_ECC, NULL, 0, 1282 MEM_ERROR_OCCURREDf, MEM_ERROR_OCCURREDf, 1283 INVALIDm, "OBM9 CELL ASSEM BUFFER", 1284 IDB_OBM9_SER_CONTROLr, CA_FIFO_ECC_ENABLEf, NULL, 1285 INVALIDr, INVALIDf, NULL, 1286 IDB_OBM9_CA_ECC_STATUSr, NULL, ECC_ERRf, NULL, 1287 INVALIDr, INVALIDf, NULL 1288 }, 1289 { _SOC_PARITY_TYPE_ECC, NULL, 0, 1290 MEM_ERROR_OCCURREDf, MEM_ERROR_OCCURREDf, 1291 INVALIDm, "OBM10 CELL ASSEM BUFFER", 1292 IDB_OBM10_SER_CONTROLr, CA_FIFO_ECC_ENABLEf, NULL, 1293 INVALIDr, INVALIDf, NULL, 1294 IDB_OBM10_CA_ECC_STATUSr, NULL, ECC_ERRf, NULL, 1295 INVALIDr, INVALIDf, NULL 1296 }, 1297 { _SOC_PARITY_TYPE_ECC, NULL, 0, 1298 MEM_ERROR_OCCURREDf, MEM_ERROR_OCCURREDf, 1299 INVALIDm, "OBM11 CELL ASSEM BUFFER", 1300 IDB_OBM11_SER_CONTROLr, CA_FIFO_ECC_ENABLEf, NULL, 1301 INVALIDr, INVALIDf, NULL, 1302 IDB_OBM11_CA_ECC_STATUSr, NULL, ECC_ERRf, NULL, 1303 INVALIDr, INVALIDf, NULL 1304 }, 1305 { _SOC_PARITY_TYPE_ECC, NULL, 0, 1306 MEM_ERROR_OCCURREDf, MEM_ERROR_OCCURREDf, 1307 INVALIDm, "OBM12 CELL ASSEM BUFFER", 1308 IDB_OBM12_SER_CONTROLr, CA_FIFO_ECC_ENABLEf, NULL, 1309 INVALIDr, INVALIDf, NULL, 1310 IDB_OBM12_CA_ECC_STATUSr, NULL, ECC_ERRf, NULL, 1311 INVALIDr, INVALIDf, NULL 1312 }, 1313 { _SOC_PARITY_TYPE_ECC, NULL, 0, 1314 MEM_ERROR_OCCURREDf, MEM_ERROR_OCCURREDf, 1315 INVALIDm, "OBM13 CELL ASSEM BUFFER", 1316 IDB_OBM13_SER_CONTROLr, CA_FIFO_ECC_ENABLEf, NULL, 1317 INVALIDr, INVALIDf, NULL, 1318 IDB_OBM13_CA_ECC_STATUSr, NULL, ECC_ERRf, NULL, 1319 INVALIDr, INVALIDf, NULL 1320 }, 1321 { _SOC_PARITY_TYPE_ECC, NULL, 0, 1322 MEM_ERROR_OCCURREDf, MEM_ERROR_OCCURREDf, 1323 INVALIDm, "OBM14 CELL ASSEM BUFFER", 1324 IDB_OBM14_SER_CONTROLr, CA_FIFO_ECC_ENABLEf, NULL, 1325 INVALIDr, INVALIDf, NULL, 1326 IDB_OBM14_CA_ECC_STATUSr, NULL, ECC_ERRf, NULL, 1327 INVALIDr, INVALIDf, NULL 1328 }, 1329 { _SOC_PARITY_TYPE_ECC, NULL, 0, 1330 MEM_ERROR_OCCURREDf, MEM_ERROR_OCCURREDf, 1331 INVALIDm, "OBM15 CELL ASSEM BUFFER", 1332 IDB_OBM15_SER_CONTROLr, CA_FIFO_ECC_ENABLEf, NULL, 1333 INVALIDr, INVALIDf, NULL, 1334 IDB_OBM15_CA_ECC_STATUSr, NULL, ECC_ERRf, NULL, 1335 INVALIDr, INVALIDf, NULL 1336 }, 1337 { _SOC_PARITY_TYPE_ECC, NULL, 0, 1338 MEM_ERROR_OCCURREDf, MEM_ERROR_OCCURREDf, 1339 INVALIDm, "OBM0 OBM QUEUE FIFO", 1340 IDB_OBM0_SER_CONTROLr, QUEUE_ECC_ENABLEf, NULL, 1341 INVALIDr, INVALIDf, NULL, 1342 IDB_OBM0_QUEUE_ECC_STATUSr, NULL, ECC_ERRf, NULL, 1343 INVALIDr, INVALIDf, NULL 1344 }, 1345 { _SOC_PARITY_TYPE_ECC, NULL, 0, 1346 MEM_ERROR_OCCURREDf, MEM_ERROR_OCCURREDf, 1347 INVALIDm, "OBM1 OBM QUEUE FIFO", 1348 IDB_OBM1_SER_CONTROLr, QUEUE_ECC_ENABLEf, NULL, 1349 INVALIDr, INVALIDf, NULL, 1350 IDB_OBM1_QUEUE_ECC_STATUSr, NULL, ECC_ERRf, NULL, 1351 INVALIDr, INVALIDf, NULL 1352 }, 1353 { _SOC_PARITY_TYPE_ECC, NULL, 0, 1354 MEM_ERROR_OCCURREDf, MEM_ERROR_OCCURREDf, 1355 INVALIDm, "OBM2 OBM QUEUE FIFO", 1356 IDB_OBM2_SER_CONTROLr, QUEUE_ECC_ENABLEf, NULL, 1357 INVALIDr, INVALIDf, NULL, 1358 IDB_OBM2_QUEUE_ECC_STATUSr, NULL, ECC_ERRf, NULL, 1359 INVALIDr, INVALIDf, NULL 1360 }, 1361 { _SOC_PARITY_TYPE_ECC, NULL, 0, 1362 MEM_ERROR_OCCURREDf, MEM_ERROR_OCCURREDf, 1363 INVALIDm, "OBM3 OBM QUEUE FIFO", 1364 IDB_OBM3_SER_CONTROLr, QUEUE_ECC_ENABLEf, NULL, 1365 INVALIDr, INVALIDf, NULL, 1366 IDB_OBM3_QUEUE_ECC_STATUSr, NULL, ECC_ERRf, NULL, 1367 INVALIDr, INVALIDf, NULL 1368 }, 1369 { _SOC_PARITY_TYPE_ECC, NULL, 0, 1370 MEM_ERROR_OCCURREDf, MEM_ERROR_OCCURREDf, 1371 INVALIDm, "OBM4 OBM QUEUE FIFO", 1372 IDB_OBM4_SER_CONTROLr, QUEUE_ECC_ENABLEf, NULL, 1373 INVALIDr, INVALIDf, NULL, 1374 IDB_OBM4_QUEUE_ECC_STATUSr, NULL, ECC_ERRf, NULL, 1375 INVALIDr, INVALIDf, NULL 1376 }, 1377 { _SOC_PARITY_TYPE_ECC, NULL, 0, 1378 MEM_ERROR_OCCURREDf, MEM_ERROR_OCCURREDf, 1379 INVALIDm, "OBM5 OBM QUEUE FIFO", 1380 IDB_OBM5_SER_CONTROLr, QUEUE_ECC_ENABLEf, NULL, 1381 INVALIDr, INVALIDf, NULL, 1382 IDB_OBM5_QUEUE_ECC_STATUSr, NULL, ECC_ERRf, NULL, 1383 INVALIDr, INVALIDf, NULL 1384 }, 1385 { _SOC_PARITY_TYPE_ECC, NULL, 0, 1386 MEM_ERROR_OCCURREDf, MEM_ERROR_OCCURREDf, 1387 INVALIDm, "OBM6 OBM QUEUE FIFO", 1388 IDB_OBM6_SER_CONTROLr, QUEUE_ECC_ENABLEf, NULL, 1389 INVALIDr, INVALIDf, NULL, 1390 IDB_OBM6_QUEUE_ECC_STATUSr, NULL, ECC_ERRf, NULL, 1391 INVALIDr, INVALIDf, NULL 1392 }, 1393 { _SOC_PARITY_TYPE_ECC, NULL, 0, 1394 MEM_ERROR_OCCURREDf, MEM_ERROR_OCCURREDf, 1395 INVALIDm, "OBM7 OBM QUEUE FIFO", 1396 IDB_OBM7_SER_CONTROLr, QUEUE_ECC_ENABLEf, NULL, 1397 INVALIDr, INVALIDf, NULL, 1398 IDB_OBM7_QUEUE_ECC_STATUSr, NULL, ECC_ERRf, NULL, 1399 INVALIDr, INVALIDf, NULL 1400 }, 1401 { _SOC_PARITY_TYPE_ECC, NULL, 0, 1402 MEM_ERROR_OCCURREDf, MEM_ERROR_OCCURREDf, 1403 INVALIDm, "OBM8 OBM QUEUE FIFO", 1404 IDB_OBM8_SER_CONTROLr, QUEUE_ECC_ENABLEf, NULL, 1405 INVALIDr, INVALIDf, NULL, 1406 IDB_OBM8_QUEUE_ECC_STATUSr, NULL, ECC_ERRf, NULL, 1407 INVALIDr, INVALIDf, NULL 1408 }, 1409 { _SOC_PARITY_TYPE_ECC, NULL, 0, 1410 MEM_ERROR_OCCURREDf, MEM_ERROR_OCCURREDf, 1411 INVALIDm, "OBM9 OBM QUEUE FIFO", 1412 IDB_OBM9_SER_CONTROLr, QUEUE_ECC_ENABLEf, NULL, 1413 INVALIDr, INVALIDf, NULL, 1414 IDB_OBM9_QUEUE_ECC_STATUSr, NULL, ECC_ERRf, NULL, 1415 INVALIDr, INVALIDf, NULL 1416 }, 1417 { _SOC_PARITY_TYPE_ECC, NULL, 0, 1418 MEM_ERROR_OCCURREDf, MEM_ERROR_OCCURREDf, 1419 INVALIDm, "OBM10 OBM QUEUE FIFO", 1420 IDB_OBM10_SER_CONTROLr, QUEUE_ECC_ENABLEf, NULL, 1421 INVALIDr, INVALIDf, NULL, 1422 IDB_OBM10_QUEUE_ECC_STATUSr, NULL, ECC_ERRf, NULL, 1423 INVALIDr, INVALIDf, NULL 1424 }, 1425 { _SOC_PARITY_TYPE_ECC, NULL, 0, 1426 MEM_ERROR_OCCURREDf, MEM_ERROR_OCCURREDf, 1427 INVALIDm, "OBM11 OBM QUEUE FIFO", 1428 IDB_OBM11_SER_CONTROLr, QUEUE_ECC_ENABLEf, NULL, 1429 INVALIDr, INVALIDf, NULL, 1430 IDB_OBM11_QUEUE_ECC_STATUSr, NULL, ECC_ERRf, NULL, 1431 INVALIDr, INVALIDf, NULL 1432 }, 1433 { _SOC_PARITY_TYPE_ECC, NULL, 0, 1434 MEM_ERROR_OCCURREDf, MEM_ERROR_OCCURREDf, 1435 INVALIDm, "OBM12 OBM QUEUE FIFO", 1436 IDB_OBM12_SER_CONTROLr, QUEUE_ECC_ENABLEf, NULL, 1437 INVALIDr, INVALIDf, NULL, 1438 IDB_OBM12_QUEUE_ECC_STATUSr, NULL, ECC_ERRf, NULL, 1439 INVALIDr, INVALIDf, NULL 1440 }, 1441 { _SOC_PARITY_TYPE_ECC, NULL, 0, 1442 MEM_ERROR_OCCURREDf, MEM_ERROR_OCCURREDf, 1443 INVALIDm, "OBM13 OBM QUEUE FIFO", 1444 IDB_OBM13_SER_CONTROLr, QUEUE_ECC_ENABLEf, NULL, 1445 INVALIDr, INVALIDf, NULL, 1446 IDB_OBM13_QUEUE_ECC_STATUSr, NULL, ECC_ERRf, NULL, 1447 INVALIDr, INVALIDf, NULL 1448 }, 1449 { _SOC_PARITY_TYPE_ECC, NULL, 0, 1450 MEM_ERROR_OCCURREDf, MEM_ERROR_OCCURREDf, 1451 INVALIDm, "OBM14 OBM QUEUE FIFO", 1452 IDB_OBM14_SER_CONTROLr, QUEUE_ECC_ENABLEf, NULL, 1453 INVALIDr, INVALIDf, NULL, 1454 IDB_OBM14_QUEUE_ECC_STATUSr, NULL, ECC_ERRf, NULL, 1455 INVALIDr, INVALIDf, NULL 1456 }, 1457 { _SOC_PARITY_TYPE_ECC, NULL, 0, 1458 MEM_ERROR_OCCURREDf, MEM_ERROR_OCCURREDf, 1459 INVALIDm, "OBM15 OBM QUEUE FIFO", 1460 IDB_OBM15_SER_CONTROLr, QUEUE_ECC_ENABLEf, NULL, 1461 INVALIDr, INVALIDf, NULL, 1462 IDB_OBM15_QUEUE_ECC_STATUSr, NULL, ECC_ERRf, NULL, 1463 INVALIDr, INVALIDf, NULL 1464 }, 1465 { _SOC_PARITY_TYPE_ECC, NULL, 0, 1466 MEM_ERROR_OCCURREDf, MEM_ERROR_OCCURREDf, 1467 INVALIDm, "CA-LPBK memory ", 1468 IDB_SER_CONTROLr, INVALIDf, _soc_th2_idb_ca_lpbk_enable_fields, 1469 INVALIDr, INVALIDf, NULL, 1470 IDB_CA_LPBK_ECC_STATUSr, NULL, ECC_ERRf, NULL, 1471 INVALIDr, INVALIDf, NULL 1472 }, 1473 { _SOC_PARITY_TYPE_ECC, NULL, 0, 1474 MEM_ERROR_OCCURREDf, MEM_ERROR_OCCURREDf, 1475 INVALIDm, "CA-CPU memory", 1476 IDB_SER_CONTROLr, INVALIDf, _soc_th2_idb_ca_cpu_enable_fields, 1477 INVALIDr, INVALIDf, NULL, 1478 IDB_CA_CPU_ECC_STATUSr, NULL, ECC_ERRf, NULL, 1479 INVALIDr, INVALIDf, NULL 1480 }, 1481 { _SOC_PARITY_TYPE_ECC, NULL, 0, 1482 MEM_ERROR_OCCURREDf, MEM_ERROR_OCCURREDf, 1483 INVALIDm, "SOP_EVENT memory", 1484 IDB_SER_CONTROLr, INVALIDf, _soc_th2_idb_sop_event_enable_fields, 1485 INVALIDr, INVALIDf, NULL, 1486 IDB_SOP_EVENT_ECC_STATUSr, NULL, ECC_ERRf, NULL, 1487 INVALIDr, INVALIDf, NULL 1488 }, 1489 { _SOC_PARITY_TYPE_ECC, NULL, 0, 1490 MEM_ERROR_OCCURREDf, MEM_ERROR_OCCURREDf, 1491 INVALIDm, "IP IDB memory", 1492 IDB_SER_CONTROLr, INVALIDf, _soc_th2_idb_eop_event_enable_fields, 1493 INVALIDr, INVALIDf, NULL, 1494 IDB_EOP_EVENT_ECC_STATUSr, NULL, ECC_ERRf, NULL, 1495 INVALIDr, INVALIDf, NULL 1496 }, 1497 1498 1499 { _SOC_PARITY_TYPE_NONE } /* table terminator */ 1500 }; 1501 1502 static _soc_th_ser_info_t _soc_th2_ip7_ser_info[] = { 1503 { _SOC_PARITY_TYPE_ECC, NULL, 0, 1504 SLOT_PIPELINE_ECC_ERRf, SLOT_PIPELINE_ECC_ERRf, 1505 INVALIDm, "Slot pipeline", 1506 INVALIDr, INVALIDf, NULL, 1507 INVALIDr, INVALIDf, NULL, 1508 SLOT_PIPELINE_ECC_STATUS_INTRr, NULL, ECC_ERRf, NULL, 1509 INVALIDr, INVALIDf, NULL 1510 }, 1511 { _SOC_PARITY_TYPE_ECC, NULL, 0, 1512 CELL_QUEUE_ECC_ERRf, CELL_QUEUE_ECC_ERRf, 1513 INVALIDm, "Cell queue", 1514 INVALIDr, INVALIDf, NULL, 1515 INVALIDr, INVALIDf, NULL, 1516 CELL_QUEUE_ECC_STATUS_INTRr, NULL, ECC_ERRf, NULL, 1517 INVALIDr, INVALIDf, NULL 1518 }, 1519 { _SOC_PARITY_TYPE_ECC, NULL, 0, 1520 EOP_BUFFER_MTU_ECC_ERRf, EOP_BUFFER_MTU_ECC_ERRf, 1521 INVALIDm, "EOP_BUFFER_MTU", 1522 INVALIDr, INVALIDf, NULL, 1523 INVALIDr, INVALIDf, NULL, 1524 EOP_BUFFER_MTU_ECC_STATUS_INTRr, NULL, ECC_ERRf, NULL, 1525 INVALIDr, INVALIDf, NULL 1526 }, 1527 { _SOC_PARITY_TYPE_ECC, NULL, 0, 1528 EVENT_FIFO_ECC_ERRf, EVENT_FIFO_ECC_ERRf, 1529 INVALIDm, "Event FIFO", 1530 INVALIDr, INVALIDf, NULL, 1531 INVALIDr, INVALIDf, NULL, 1532 EVENT_FIFO_ECC_STATUS_INTRr, NULL, ECC_ERRf, NULL, 1533 INVALIDr, INVALIDf, NULL 1534 }, 1535 1536 { _SOC_PARITY_TYPE_NONE } /* table terminator */ 1537 }; 1538 1539 1540 1541 static _soc_th_ser_reg_t _soc_th2_pm_clp_tx_status_reg[] = { 1542 { CLPORT_MIB_TSC0_ECC_STATUSr, "CLP MIB TSC0 ECC" }, 1543 { CLPORT_MIB_TSC1_ECC_STATUSr, "CLP MIB TSC1 ECC" }, 1544 { INVALIDr, "INVALID"} 1545 }; 1546 1547 static _soc_th_ser_reg_t _soc_th2_pm_clp_rx_status_reg[] = { 1548 { CLPORT_MIB_RSC0_ECC_STATUSr, "CLP MIB RSC0 ECC" }, 1549 { CLPORT_MIB_RSC1_ECC_STATUSr, "CLP MIB RSC1 ECC" }, 1550 { INVALIDr, "INVALID"} 1551 }; 1552 1553 static _soc_th_ser_info_t _soc_th2_pm_clp_ser_info[] = { 1554 { _SOC_PARITY_TYPE_ECC, NULL, 0, 1555 MIB_RX_MEM_ERRf, MIB_RX_MEM_ERRf, 1556 INVALIDm, "MIB RX Statistic Counter memory", 1557 CLPORT_ECC_CONTROLr, MIB_RSC_MEM_ENf, NULL, 1558 INVALIDr, INVALIDf, NULL, 1559 INVALIDr, _soc_th2_pm_clp_rx_status_reg, INVALIDf, NULL, 1560 INVALIDr, INVALIDf, NULL 1561 }, 1562 { _SOC_PARITY_TYPE_ECC, NULL, 0, 1563 MIB_TX_MEM_ERRf, MIB_TX_MEM_ERRf, 1564 INVALIDm, "MIB TX Statistic Counter memory", 1565 CLPORT_ECC_CONTROLr, MIB_TSC_MEM_ENf, NULL, 1566 INVALIDr, INVALIDf, NULL, 1567 INVALIDr, _soc_th2_pm_clp_tx_status_reg, INVALIDf, NULL, 1568 INVALIDr, INVALIDf, NULL 1569 }, 1570 1571 { _SOC_PARITY_TYPE_CLMAC, NULL, 0, 1572 MAC_ERRf, MAC_ERRf, 1573 INVALIDm, "CLMAC TX CDC single bit", 1574 CLMAC_ECC_CTRLr, TX_CDC_ECC_CTRL_ENf, NULL, 1575 CLMAC_INTR_ENABLEr, EN_TX_CDC_SINGLE_BIT_ERRf, NULL, 1576 CLMAC_INTR_STATUSr, NULL, SUM_TX_CDC_SINGLE_BIT_ERRf, NULL, 1577 CLMAC_CLEAR_ECC_STATUSr, CLEAR_TX_CDC_SINGLE_BIT_ERRf, NULL 1578 }, 1579 { _SOC_PARITY_TYPE_CLMAC, NULL, 0, 1580 MAC_ERRf, MAC_ERRf, 1581 INVALIDm, "CLMAC TX CDC double bits", 1582 CLMAC_ECC_CTRLr, TX_CDC_ECC_CTRL_ENf, NULL, 1583 CLMAC_INTR_ENABLEr, EN_TX_CDC_DOUBLE_BIT_ERRf, NULL, 1584 CLMAC_INTR_STATUSr, NULL, SUM_TX_CDC_DOUBLE_BIT_ERRf, NULL, 1585 CLMAC_CLEAR_ECC_STATUSr, CLEAR_TX_CDC_DOUBLE_BIT_ERRf, NULL 1586 }, 1587 { _SOC_PARITY_TYPE_CLMAC, NULL, 0, 1588 MAC_ERRf, MAC_ERRf, 1589 INVALIDm, "CLMAC RX CDC single bit", 1590 CLMAC_ECC_CTRLr, RX_CDC_ECC_CTRL_ENf, NULL, 1591 CLMAC_INTR_ENABLEr, EN_RX_CDC_SINGLE_BIT_ERRf, NULL, 1592 CLMAC_INTR_STATUSr, NULL, SUM_RX_CDC_SINGLE_BIT_ERRf, NULL, 1593 CLMAC_CLEAR_ECC_STATUSr, CLEAR_RX_CDC_SINGLE_BIT_ERRf, NULL 1594 }, 1595 { _SOC_PARITY_TYPE_CLMAC, NULL, 0, 1596 MAC_ERRf, MAC_ERRf, 1597 INVALIDm, "CLMAC RX CDC double bits", 1598 CLMAC_ECC_CTRLr, RX_CDC_ECC_CTRL_ENf, NULL, 1599 CLMAC_INTR_ENABLEr, EN_RX_CDC_DOUBLE_BIT_ERRf, NULL, 1600 CLMAC_INTR_STATUSr, NULL, SUM_RX_CDC_DOUBLE_BIT_ERRf, NULL, 1601 CLMAC_CLEAR_ECC_STATUSr, CLEAR_RX_CDC_DOUBLE_BIT_ERRf, NULL 1602 }, 1603 { _SOC_PARITY_TYPE_CLMAC, NULL, 0, 1604 MAC_ERRf, MAC_ERRf, 1605 INVALIDm, "CLMAC RX TS MEM single bit", 1606 CLMAC_ECC_CTRLr, RX_TS_MEM_ECC_CTRL_ENf, NULL, 1607 CLMAC_INTR_ENABLEr, EN_RX_TS_MEM_SINGLE_BIT_ERRf, NULL, 1608 CLMAC_INTR_STATUSr, NULL, SUM_RX_TS_MEM_SINGLE_BIT_ERRf, NULL, 1609 CLMAC_CLEAR_ECC_STATUSr, CLEAR_RX_TS_MEM_SINGLE_BIT_ERRf, NULL 1610 }, 1611 { _SOC_PARITY_TYPE_CLMAC, NULL, 0, 1612 MAC_ERRf, MAC_ERRf, 1613 INVALIDm, "CLMAC RX TS MEM double bits", 1614 CLMAC_ECC_CTRLr, RX_TS_MEM_ECC_CTRL_ENf, NULL, 1615 CLMAC_INTR_ENABLEr, EN_RX_TS_MEM_DOUBLE_BIT_ERRf, NULL, 1616 CLMAC_INTR_STATUSr, NULL, SUM_RX_TS_MEM_DOUBLE_BIT_ERRf, NULL, 1617 CLMAC_CLEAR_ECC_STATUSr, CLEAR_RX_TS_MEM_DOUBLE_BIT_ERRf, NULL 1618 }, 1619 1620 { _SOC_PARITY_TYPE_NONE } /* table terminator */ 1621 }; 1622 1623 static _soc_th_ser_reg_t _soc_th2_pm_xlp_rx_status_reg[] = { 1624 { XLPORT_MIB_RSC0_ECC_STATUSr, "XLP MIB RSC0 ECC" }, 1625 { XLPORT_MIB_RSC1_ECC_STATUSr, "XLP MIB RSC1 ECC" }, 1626 { INVALIDr, "INVALID"} 1627 }; 1628 1629 static _soc_th_ser_reg_t _soc_th2_pm_xlp_tx_status_reg[] = { 1630 { XLPORT_MIB_TSC0_ECC_STATUSr, "XLP MIB TSC0 ECC" }, 1631 { XLPORT_MIB_TSC1_ECC_STATUSr, "XLP MIB TSC1 ECC" }, 1632 { INVALIDr, "INVALID"} 1633 }; 1634 1635 1636 static _soc_th_ser_info_t _soc_th2_pm_xlp_ser_info[] = { 1637 { _SOC_PARITY_TYPE_ECC, NULL, 0, 1638 MIB_RX_MEM_ERRf, MIB_RX_MEM_ERRf, 1639 INVALIDm, "MIB RX Statistic Counter memory", 1640 CLPORT_ECC_CONTROLr, MIB_RSC_MEM_ENf, NULL, 1641 INVALIDr, INVALIDf, NULL, 1642 INVALIDr, _soc_th2_pm_xlp_rx_status_reg, INVALIDf, NULL, 1643 INVALIDr, INVALIDf, NULL 1644 }, 1645 { _SOC_PARITY_TYPE_ECC, NULL, 0, 1646 MIB_RX_MEM_ERRf, MIB_RX_MEM_ERRf, 1647 INVALIDm, "MIB TX Statistic Counter memory", 1648 CLPORT_ECC_CONTROLr, MIB_TSC_MEM_ENf, NULL, 1649 INVALIDr, INVALIDf, NULL, 1650 INVALIDr, _soc_th2_pm_xlp_tx_status_reg, INVALIDf, NULL, 1651 INVALIDr, INVALIDf, NULL 1652 }, 1653 { _SOC_PARITY_TYPE_NONE } /* table terminator */ 1654 }; 1655 1656 static soc_field_t _soc_th2_mmu_top_int_enable_fields[] = { 1657 SED_R_CPU_INT_ENf, 1658 SED_S_CPU_INT_ENf, 1659 SC_R_CPU_INT_ENf, 1660 SC_S_CPU_INT_ENf, 1661 XPE_R_B_CPU_INT_ENf, 1662 XPE_R_A_CPU_INT_ENf, 1663 XPE_S_B_CPU_INT_ENf, 1664 XPE_S_A_CPU_INT_ENf, 1665 GLB_CPU_INT_ENf, 1666 INVALIDf 1667 }; 1668 1669 static soc_field_t _soc_th2_mmu_top_int_status_fields[] = { 1670 SED_R_CPU_INT_STATf, 1671 SED_S_CPU_INT_STATf, 1672 SC_R_CPU_INT_STATf, 1673 SC_S_CPU_INT_STATf, 1674 XPE_R_B_CPU_INT_STATf, 1675 XPE_R_A_CPU_INT_STATf, 1676 XPE_S_B_CPU_INT_STATf, 1677 XPE_S_A_CPU_INT_STATf, 1678 GLB_CPU_INT_STATf, 1679 INVALIDf 1680 }; 1681 1682 static soc_field_t _soc_th2_mmu_xpe_enable_fields[] = { 1683 TCB_PARITY_ENf, 1684 THDM_PARITY_ENf, 1685 ENQX_PARITY_ENf, 1686 EPRG_PARITY_ENf, 1687 RQE_PARITY_ENf, 1688 THDI_PARITY_ENf, 1689 THDU_PARITY_ENf, 1690 PQE_PARITY_ENf, 1691 WRED_PARITY_ENf, 1692 DQX_PARITY_ENf, 1693 CCP_PARITY_ENf, 1694 CTR_PARITY_ENf, 1695 INVALIDf 1696 }; 1697 1698 static soc_field_t _soc_th2_mmu_sc_enable_fields[] = { 1699 TDM_PARITY_ENf, 1700 VBS_PARITY_ENf, 1701 TOQ_B_PARITY_ENf, 1702 TOQ_A_PARITY_ENf, 1703 INVALIDf 1704 }; 1705 1706 1707 static soc_field_t _soc_th2_mmu_sed_enable_fields[] = { 1708 MB_A_PARITY_ENf, 1709 MB_B_PARITY_ENf, 1710 ENQS_PARITY_ENf, 1711 MTRO_PARITY_ENf, 1712 DQS_PARITY_ENf, 1713 CFAP_B_PARITY_ENf, 1714 CFAP_A_PARITY_ENf, 1715 INVALIDf 1716 }; 1717 1718 static soc_field_t _soc_th2_mmu_sed_int_enable_fields[] = { 1719 CFAP_A_MEM_FAIL_ENf, 1720 CFAP_B_MEM_FAIL_ENf, 1721 MEM_PAR_ERR_ENf, 1722 INVALIDf 1723 }; 1724 static soc_field_t _soc_th2_mmu_sed_int_status_fields[] = { 1725 CFAP_A_MEM_FAIL_STATf, 1726 CFAP_B_MEM_FAIL_STATf, 1727 MEM_PAR_ERR_STATf, 1728 INVALIDf 1729 }; 1730 static soc_field_t _soc_th2_mmu_sed_int_clr_fields[] = { 1731 CFAP_A_MEM_FAIL_CLRf, 1732 CFAP_B_MEM_FAIL_CLRf, 1733 MEM_PAR_ERR_CLRf, 1734 INVALIDf 1735 }; 1736 1737 static _soc_th_ser_info_t _soc_th2_mmu_ser_info[] = { 1738 { _SOC_PARITY_TYPE_MMU_GLB, NULL, 0, 1739 INVALIDf, INVALIDf, 1740 INVALIDm, "MMU GLB MEM PAR", 1741 MMU_GCFG_PARITY_ENr, INTFO_PARITY_ENf, NULL, 1742 MMU_GCFG_GLB_CPU_INT_ENr, MEM_PAR_ERR_ENf, NULL, 1743 MMU_GCFG_GLB_CPU_INT_STATr, NULL, MEM_PAR_ERR_STATf, NULL, 1744 MMU_GCFG_GLB_CPU_INT_CLEARr, MEM_PAR_ERR_CLRf, NULL 1745 }, 1746 { _SOC_PARITY_TYPE_MMU_XPE, NULL, 0, 1747 INVALIDf, INVALIDf, 1748 INVALIDm, "MMU XPE MEM PAR", 1749 MMU_XCFG_PARITY_ENr, INVALIDf, _soc_th2_mmu_xpe_enable_fields, 1750 MMU_XCFG_XPE_CPU_INT_ENr, MEM_PAR_ERR_ENf, NULL, 1751 MMU_XCFG_XPE_CPU_INT_STATr, NULL, MEM_PAR_ERR_STATf, NULL, 1752 MMU_XCFG_XPE_CPU_INT_CLEARr, MEM_PAR_ERR_CLRf, NULL 1753 }, 1754 { _SOC_PARITY_TYPE_MMU_SC, NULL, 0, 1755 INVALIDf, INVALIDf, 1756 INVALIDm, "MMU SC MEM PAR", 1757 MMU_SCFG_PARITY_ENr, INVALIDf, _soc_th2_mmu_sc_enable_fields, 1758 MMU_SCFG_SC_CPU_INT_ENr, MEM_PAR_ERR_ENf, NULL, 1759 MMU_SCFG_SC_CPU_INT_STATr, NULL, MEM_PAR_ERR_STATf, 1760 NULL, 1761 MMU_SCFG_SC_CPU_INT_CLEARr, MEM_PAR_ERR_CLRf, 1762 NULL 1763 }, 1764 { _SOC_PARITY_TYPE_MMU_SED, NULL, 0, 1765 INVALIDf, INVALIDf, 1766 INVALIDm, "MMU SED MEM PAR", 1767 MMU_SEDCFG_PARITY_ENr, INVALIDf, _soc_th2_mmu_sed_enable_fields, 1768 MMU_SEDCFG_SED_CPU_INT_ENr, INVALIDf, _soc_th2_mmu_sed_int_enable_fields, 1769 MMU_SEDCFG_SED_CPU_INT_STATr, NULL, INVALIDf, 1770 _soc_th2_mmu_sed_int_status_fields, 1771 MMU_SEDCFG_SED_CPU_INT_CLEARr, INVALIDf, 1772 _soc_th2_mmu_sed_int_clr_fields 1773 }, 1774 1775 1776 { _SOC_PARITY_TYPE_NONE } /* table terminator */ 1777 }; 1778 1779 1780 static _soc_th_ser_info_t _soc_th2_mmu_top_ser_info[] = { 1781 { _SOC_PARITY_TYPE_MMU_SER, _soc_th2_mmu_ser_info, 0, 1782 INVALIDf, INVALIDf, 1783 INVALIDm, "MMU MEM PAR", 1784 INVALIDr, INVALIDf, NULL, 1785 MMU_GCFG_ALL_CPU_INT_ENr, INVALIDf, 1786 _soc_th2_mmu_top_int_enable_fields, 1787 MMU_GCFG_ALL_CPU_INT_STATr, 1788 NULL, INVALIDf, _soc_th2_mmu_top_int_status_fields, 1789 INVALIDr, INVALIDf, NULL 1790 }, 1791 { _SOC_PARITY_TYPE_NONE } /* table terminator */ 1792 }; 1793 1794 static const 1795 _soc_th_ser_route_block_t _soc_th2_ser_route_blocks[] = { 1796 /* CMIC_CMC_IRQ_STAT3 */ 1797 { 3, 0x00000010, /* MMU_TO_CMIC_MEMFAIL_INTRf */ 1798 SOC_BLK_MMU, -1, INVALIDr, INVALIDr, INVALIDf, 1799 _soc_th2_mmu_top_ser_info, 0 }, 1800 /* xsm: not using MMU_GLB or MMU_XPE or MMU_SC is on purpose */ 1801 1802 { 3, 0x00000020, /* PIPE0_EP2_TO_CMIC_PERR_INTRf */ 1803 SOC_BLK_EPIPE, 0, EGR_INTR_ENABLEr, INVALIDr, SER_FIFO_NON_EMPTYf, 1804 NULL, 0 }, 1805 { 3, 0x00000040, /* PIPE1_EP2_TO_CMIC_PERR_INTRf */ 1806 SOC_BLK_EPIPE, 1, EGR_INTR_ENABLEr, INVALIDr, SER_FIFO_NON_EMPTYf, 1807 NULL, 0 }, 1808 { 3, 0x00000080, /* PIPE2_EP2_TO_CMIC_PERR_INTRf */ 1809 SOC_BLK_EPIPE, 2, EGR_INTR_ENABLEr, INVALIDr, SER_FIFO_NON_EMPTYf, 1810 NULL, 0 }, 1811 { 3, 0x00000100, /* PIPE3_EP2_TO_CMIC_PERR_INTRf */ 1812 SOC_BLK_EPIPE, 3, EGR_INTR_ENABLEr, INVALIDr, SER_FIFO_NON_EMPTYf, 1813 NULL, 0 }, 1814 1815 1816 /* Note: This is an exception for being legacy style in IP0 not fifo mode. 1817 * These mask bit are set for IP0 IDB Mem reset complete or IDB memories SER 1818 * interrupt, please check IP0_INTR_STATUS 1819 */ 1820 { 3, 0x00000200, /* PIPE0_IP0_TO_CMIC_PERR_INTRf */ 1821 SOC_BLK_IPIPE, 0, IP0_INTR_ENABLEr, IP0_INTR_STATUSr, INVALIDf, 1822 _soc_th2_idb_ser_info, 0 }, 1823 { 3, 0x00000400, /* PIPE1_IP0_TO_CMIC_PERR_INTRf */ 1824 /* Note: This is an exception for being legacy style in IP */ 1825 SOC_BLK_IPIPE, 1, IP0_INTR_ENABLEr, IP0_INTR_STATUSr, INVALIDf, 1826 _soc_th2_idb_ser_info, 0 }, 1827 { 3, 0x00000800, /* PIPE2_IP0_TO_CMIC_PERR_INTRf */ 1828 /* Note: This is an exception for being legacy style in IP */ 1829 SOC_BLK_IPIPE, 2, IP0_INTR_ENABLEr, IP0_INTR_STATUSr, INVALIDf, 1830 _soc_th2_idb_ser_info, 0 }, 1831 { 3, 0x000001000, /* PIPE3_IP0_TO_CMIC_PERR_INTRf */ 1832 /* Note: This is an exception for being legacy style in IP */ 1833 SOC_BLK_IPIPE, 3, IP0_INTR_ENABLEr, IP0_INTR_STATUSr, INVALIDf, 1834 _soc_th2_idb_ser_info, 0 }, 1835 1836 { 3, 0x00002000, /* PIPE0_IP6_TO_CMIC_PERR_INTRf */ 1837 SOC_BLK_IPIPE, 0, INVALIDr, INVALIDr, INVALIDf, 1838 NULL, 0 }, 1839 { 3, 0x00004000, /* PIPE1_IP6_TO_CMIC_PERR_INTRf */ 1840 SOC_BLK_IPIPE, 1, INVALIDr, INVALIDr, INVALIDf, 1841 NULL, 0 }, 1842 { 3, 0x00008000, /* PIPE2_IP6_TO_CMIC_PERR_INTRf */ 1843 SOC_BLK_IPIPE, 2, INVALIDr, INVALIDr, INVALIDf, 1844 NULL, 0 }, 1845 { 3, 0x00010000, /* PIPE3_IP6_TO_CMIC_PERR_INTRf */ 1846 SOC_BLK_IPIPE, 3, INVALIDr, INVALIDr, INVALIDf, 1847 NULL, 0 }, 1848 1849 /* IP7 interrupt signal for any parity/ecc error events, 1850 * as well as some fatal fifo full/empty events in Isw4 (IP) */ 1851 /* Note: This is an exception for being legacy style in IP */ 1852 { 3, 0x04000000, /* PIPE0_IP7_TO_CMIC_INTRf */ 1853 SOC_BLK_IPIPE, 0, IP7_INTR_ENABLEr, IP7_INTR_STATUSr, INVALIDf, 1854 _soc_th2_ip7_ser_info, 0 }, 1855 { 3, 0x08000000, /* PIPE1_IP7_TO_CMIC_INTRf */ 1856 SOC_BLK_IPIPE, 1, IP7_INTR_ENABLEr, IP7_INTR_STATUSr, INVALIDf, 1857 _soc_th2_ip7_ser_info, 0 }, 1858 { 3, 0x10000000, /* PIPE2_IP7_TO_CMIC_INTRf */ 1859 SOC_BLK_IPIPE, 2, IP7_INTR_ENABLEr, IP7_INTR_STATUSr, INVALIDf, 1860 _soc_th2_ip7_ser_info, 0 }, 1861 { 3, 0x20000000, /* PIPE3_IP7_TO_CMIC_INTRf */ 1862 SOC_BLK_IPIPE, 3, IP7_INTR_ENABLEr, IP7_INTR_STATUSr, INVALIDf, 1863 _soc_th2_ip7_ser_info, 0 }, 1864 1865 1866 /* CMIC_CMC_IRQ_STAT4 */ 1867 { 4, 0x00000001, /* PM0_INTR */ 1868 SOC_BLK_CLPORT, 0, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 1869 _soc_th2_pm_clp_ser_info, 0 }, 1870 { 4, 0x00000002, /* PM1_INTR */ 1871 SOC_BLK_CLPORT, 0, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 1872 _soc_th2_pm_clp_ser_info, 1 }, 1873 { 4, 0x00000004, /* PM2_INTR */ 1874 SOC_BLK_CLPORT, 0, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 1875 _soc_th2_pm_clp_ser_info, 2 }, 1876 { 4, 0x00000008, /* PM3_INTR */ 1877 SOC_BLK_CLPORT, 0, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 1878 _soc_th2_pm_clp_ser_info, 3 }, 1879 { 4, 0x00000010, /* PM4_INTR */ 1880 SOC_BLK_CLPORT, 0, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 1881 _soc_th2_pm_clp_ser_info, 4 }, 1882 { 4, 0x00000020, /* PM5_INTR */ 1883 SOC_BLK_CLPORT, 0, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 1884 _soc_th2_pm_clp_ser_info, 5 }, 1885 { 4, 0x00000040, /* PM6_INTR */ 1886 SOC_BLK_CLPORT, 0, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 1887 _soc_th2_pm_clp_ser_info, 6 }, 1888 { 4, 0x00000080, /* PM7_INTR */ 1889 SOC_BLK_CLPORT, 0, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 1890 _soc_th2_pm_clp_ser_info, 7 }, 1891 { 4, 0x00000100, /* PM8_INTR */ 1892 SOC_BLK_CLPORT, 1, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 1893 _soc_th2_pm_clp_ser_info, 8 }, 1894 { 4, 0x00000200, /* PM9_INTR */ 1895 SOC_BLK_CLPORT, 1, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 1896 _soc_th2_pm_clp_ser_info, 9 }, 1897 { 4, 0x00000400, /* PM10_INTR */ 1898 SOC_BLK_CLPORT, 1, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 1899 _soc_th2_pm_clp_ser_info, 10 }, 1900 { 4, 0x00000800, /* PM11_INTR */ 1901 SOC_BLK_CLPORT, 1, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 1902 _soc_th2_pm_clp_ser_info, 11 }, 1903 { 4, 0x00001000, /* PM12_INTR */ 1904 SOC_BLK_CLPORT, 1, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 1905 _soc_th2_pm_clp_ser_info, 12 }, 1906 { 4, 0x00002000, /* PM13_INTR */ 1907 SOC_BLK_CLPORT, 1, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 1908 _soc_th2_pm_clp_ser_info, 13 }, 1909 { 4, 0x00004000, /* PM14_INTR */ 1910 SOC_BLK_CLPORT, 1, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 1911 _soc_th2_pm_clp_ser_info, 14 }, 1912 { 4, 0x00008000, /* PM15_INTR */ 1913 SOC_BLK_CLPORT, 1, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 1914 _soc_th2_pm_clp_ser_info, 15 }, 1915 { 4, 0x00010000, /* PM16_INTR */ 1916 SOC_BLK_CLPORT, 2, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 1917 _soc_th2_pm_clp_ser_info, 16 }, 1918 { 4, 0x00020000, /* PM17_INTR */ 1919 SOC_BLK_CLPORT, 2, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 1920 _soc_th2_pm_clp_ser_info, 17 }, 1921 { 4, 0x00040000, /* PM18_INTR */ 1922 SOC_BLK_CLPORT, 2, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 1923 _soc_th2_pm_clp_ser_info, 18 }, 1924 { 4, 0x00080000, /* PM19_INTR */ 1925 SOC_BLK_CLPORT, 2, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 1926 _soc_th2_pm_clp_ser_info, 19 }, 1927 { 4, 0x00100000, /* PM20_INTR */ 1928 SOC_BLK_CLPORT, 2, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 1929 _soc_th2_pm_clp_ser_info, 20 }, 1930 { 4, 0x00200000, /* PM21_INTR */ 1931 SOC_BLK_CLPORT, 2, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 1932 _soc_th2_pm_clp_ser_info, 21 }, 1933 { 4, 0x00400000, /* PM22_INTR */ 1934 SOC_BLK_CLPORT, 2, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 1935 _soc_th2_pm_clp_ser_info, 22 }, 1936 { 4, 0x00800000, /* PM23_INTR */ 1937 SOC_BLK_CLPORT, 2, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 1938 _soc_th2_pm_clp_ser_info, 23 }, 1939 { 4, 0x01000000, /* PM24_INTR */ 1940 SOC_BLK_CLPORT, 3, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 1941 _soc_th2_pm_clp_ser_info, 24 }, 1942 { 4, 0x02000000, /* PM25_INTR */ 1943 SOC_BLK_CLPORT, 3, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 1944 _soc_th2_pm_clp_ser_info, 25 }, 1945 { 4, 0x04000000, /* PM26_INTR */ 1946 SOC_BLK_CLPORT, 3, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 1947 _soc_th2_pm_clp_ser_info, 26 }, 1948 { 4, 0x08000000, /* PM27_INTR */ 1949 SOC_BLK_CLPORT, 3, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 1950 _soc_th2_pm_clp_ser_info, 27 }, 1951 { 4, 0x10000000, /* PM28_INTR */ 1952 SOC_BLK_CLPORT, 3, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 1953 _soc_th2_pm_clp_ser_info, 28 }, 1954 { 4, 0x20000000, /* PM29_INTR */ 1955 SOC_BLK_CLPORT, 3, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 1956 _soc_th2_pm_clp_ser_info, 29 }, 1957 { 4, 0x40000000, /* PM30_INTR */ 1958 SOC_BLK_CLPORT, 3, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 1959 _soc_th2_pm_clp_ser_info, 30 }, 1960 { 4, 0x80000000, /* PM31_INTR */ 1961 SOC_BLK_CLPORT, 3, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 1962 _soc_th2_pm_clp_ser_info, 31 }, 1963 1964 /* CMIC_CMC_IRQ_STAT6 */ 1965 { 6, 0x00000001, /* PM32_INTR */ 1966 SOC_BLK_CLPORT, 0, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 1967 _soc_th2_pm_clp_ser_info, 32 }, 1968 { 6, 0x00000002, /* PM33_INTR */ 1969 SOC_BLK_CLPORT, 0, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 1970 _soc_th2_pm_clp_ser_info, 33 }, 1971 { 6, 0x00000004, /* PM34_INTR */ 1972 SOC_BLK_CLPORT, 0, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 1973 _soc_th2_pm_clp_ser_info, 34 }, 1974 { 6, 0x00000008, /* PM35_INTR */ 1975 SOC_BLK_CLPORT, 0, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 1976 _soc_th2_pm_clp_ser_info, 35 }, 1977 { 6, 0x00000010, /* PM36_INTR */ 1978 SOC_BLK_CLPORT, 0, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 1979 _soc_th2_pm_clp_ser_info, 36 }, 1980 { 6, 0x00000020, /* PM37_INTR */ 1981 SOC_BLK_CLPORT, 0, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 1982 _soc_th2_pm_clp_ser_info, 37 }, 1983 { 6, 0x00000040, /* PM38_INTR */ 1984 SOC_BLK_CLPORT, 0, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 1985 _soc_th2_pm_clp_ser_info, 38 }, 1986 { 6, 0x00000080, /* PM39_INTR */ 1987 SOC_BLK_CLPORT, 0, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 1988 _soc_th2_pm_clp_ser_info, 39 }, 1989 { 6, 0x00000100, /* PM40_INTR */ 1990 SOC_BLK_CLPORT, 1, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 1991 _soc_th2_pm_clp_ser_info, 40 }, 1992 { 6, 0x00000200, /* PM41_INTR */ 1993 SOC_BLK_CLPORT, 1, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 1994 _soc_th2_pm_clp_ser_info, 41 }, 1995 { 6, 0x00000400, /* PM42_INTR */ 1996 SOC_BLK_CLPORT, 1, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 1997 _soc_th2_pm_clp_ser_info, 42 }, 1998 { 6, 0x00000800, /* PM43_INTR */ 1999 SOC_BLK_CLPORT, 1, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 2000 _soc_th2_pm_clp_ser_info, 43 }, 2001 { 6, 0x00001000, /* PM44_INTR */ 2002 SOC_BLK_CLPORT, 1, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 2003 _soc_th2_pm_clp_ser_info, 44 }, 2004 { 6, 0x00002000, /* PM45_INTR */ 2005 SOC_BLK_CLPORT, 1, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 2006 _soc_th2_pm_clp_ser_info, 45 }, 2007 { 6, 0x00004000, /* PM46_INTR */ 2008 SOC_BLK_CLPORT, 1, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 2009 _soc_th2_pm_clp_ser_info, 46 }, 2010 { 6, 0x00008000, /* PM47_INTR */ 2011 SOC_BLK_CLPORT, 1, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 2012 _soc_th2_pm_clp_ser_info, 47 }, 2013 { 6, 0x00010000, /* PM48_INTR */ 2014 SOC_BLK_CLPORT, 2, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 2015 _soc_th2_pm_clp_ser_info, 48 }, 2016 { 6, 0x00020000, /* PM49_INTR */ 2017 SOC_BLK_CLPORT, 2, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 2018 _soc_th2_pm_clp_ser_info, 49 }, 2019 { 6, 0x00040000, /* PM50_INTR */ 2020 SOC_BLK_CLPORT, 2, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 2021 _soc_th2_pm_clp_ser_info, 50 }, 2022 { 6, 0x00080000, /* PM51_INTR */ 2023 SOC_BLK_CLPORT, 2, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 2024 _soc_th2_pm_clp_ser_info, 51 }, 2025 { 6, 0x00100000, /* PM52_INTR */ 2026 SOC_BLK_CLPORT, 2, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 2027 _soc_th2_pm_clp_ser_info, 52 }, 2028 { 6, 0x00200000, /* PM53_INTR */ 2029 SOC_BLK_CLPORT, 2, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 2030 _soc_th2_pm_clp_ser_info, 53 }, 2031 { 6, 0x00400000, /* PM54_INTR */ 2032 SOC_BLK_CLPORT, 2, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 2033 _soc_th2_pm_clp_ser_info, 54 }, 2034 { 6, 0x00800000, /* PM55_INTR */ 2035 SOC_BLK_CLPORT, 2, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 2036 _soc_th2_pm_clp_ser_info, 55 }, 2037 { 6, 0x01000000, /* PM56_INTR */ 2038 SOC_BLK_CLPORT, 3, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 2039 _soc_th2_pm_clp_ser_info, 56 }, 2040 { 6, 0x02000000, /* PM57_INTR */ 2041 SOC_BLK_CLPORT, 3, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 2042 _soc_th2_pm_clp_ser_info, 57 }, 2043 { 6, 0x04000000, /* PM58_INTR */ 2044 SOC_BLK_CLPORT, 3, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 2045 _soc_th2_pm_clp_ser_info, 58 }, 2046 { 6, 0x08000000, /* PM59_INTR */ 2047 SOC_BLK_CLPORT, 3, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 2048 _soc_th2_pm_clp_ser_info, 59 }, 2049 { 6, 0x10000000, /* PM60_INTR */ 2050 SOC_BLK_CLPORT, 3, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 2051 _soc_th2_pm_clp_ser_info, 60 }, 2052 { 6, 0x20000000, /* PM61_INTR */ 2053 SOC_BLK_CLPORT, 3, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 2054 _soc_th2_pm_clp_ser_info, 61 }, 2055 { 6, 0x40000000, /* PM62_INTR */ 2056 SOC_BLK_CLPORT, 3, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 2057 _soc_th2_pm_clp_ser_info, 62 }, 2058 { 6, 0x80000000, /* PM63_INTR */ 2059 SOC_BLK_CLPORT, 3, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 2060 _soc_th2_pm_clp_ser_info, 63 }, 2061 2062 /* CMIC_CMC_IRQ_STAT5 */ 2063 { 5, 0x00000001, /* PM64_INTR */ 2064 SOC_BLK_XLPORT, 1, XLPORT_INTR_ENABLEr, XLPORT_INTR_STATUSr, INVALIDf, 2065 _soc_th2_pm_xlp_ser_info, 0 }, 2066 2067 { 0 } /* table terminator */ 2068 }; 2069 2070 #define _SOC_MMU_BASE_INDEX_SED0 0 2071 #define _SOC_MMU_BASE_INDEX_SED1 1 2072 2073 static const 2074 _soc_th_ser_mmu_intr_info_t th2_mmu_intr_info[] = { 2075 { GLB_CPU_INT_STATf, _SOC_MMU_BASE_INDEX_GLB, 0 }, 2076 { XPE_R_A_CPU_INT_STATf, _SOC_MMU_BASE_INDEX_XPE0, 1 }, 2077 { XPE_S_A_CPU_INT_STATf, _SOC_MMU_BASE_INDEX_XPE1, 1 }, 2078 { XPE_R_B_CPU_INT_STATf, _SOC_MMU_BASE_INDEX_XPE2, 1 }, 2079 { XPE_S_B_CPU_INT_STATf, _SOC_MMU_BASE_INDEX_XPE3, 1 }, 2080 { SC_R_CPU_INT_STATf, _SOC_MMU_BASE_INDEX_SC0, 2 }, 2081 { SC_S_CPU_INT_STATf, _SOC_MMU_BASE_INDEX_SC1, 2}, 2082 { SED_R_CPU_INT_STATf, _SOC_MMU_BASE_INDEX_SED0, 3 }, 2083 { SED_S_CPU_INT_STATf, _SOC_MMU_BASE_INDEX_SED1, 3}, 2084 2085 { INVALIDf, -1, -1 } 2086 }; 2087 2088 static _soc_tcam_ser_en_info_t _soc_th2_tcam_wrapper_table[] = { 2089 { L3_TUNNELm, L3_TUNNEL_CAM_SER_CONTROLr, PARITY_ENf, TCAM_PARITY_MASKf}, 2090 { ING_SNATm, ING_SNAT_CAM_CONTROLr, PARITY_ENf, TCAM_PARITY_MASKf}, 2091 { VLAN_SUBNETm, VLAN_SUBNET_CAM_DBGCTRLr, PARITY_ENf, TCAM_PARITY_MASKf}, 2092 { MY_STATION_TCAMm, MY_STATION_CAM_CONTROLr, PARITY_ENf, TCAM_PARITY_MASKf}, 2093 { L2_USER_ENTRYm, L2_USER_ENTRY_CAM_SERCTRLr, PARITY_ENf, TCAM_PARITY_MASKf}, 2094 { SRC_COMPRESSIONm, SRC_COMPRESSION_CAM_DBGCTRLr, PARITY_ENf, TCAM_PARITY_MASKf}, 2095 { DST_COMPRESSIONm, DST_COMPRESSION_CAM_DBGCTRLr, PARITY_ENf, TCAM_PARITY_MASKf}, 2096 { FP_UDF_TCAMm, UDF_CAM_SERCTRLr, PARITY_ENf, TCAM_PARITY_MASKf}, 2097 { VFP_TCAMm, VFP_CAM_BIST_CONTROLr, PARITY_ENf, TCAM_PARITY_MASKf}, 2098 { EXACT_MATCH_LOGICAL_TABLE_SELECTm, EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_DBGCTRLr, PARITY_ENf, TCAM_PARITY_MASKf}, 2099 { IP_MULTICAST_TCAMm, IP_MULTICAST_CAM_SERCTRLr, PARITY_ENf, TCAM_PARITY_MASKf}, 2100 { CPU_COS_MAPm, CPU_COS_CAM_SERCTRLr, PARITY_ENf, TCAM_PARITY_MASKf}, 2101 { L3_DEFIPm, ILPM_SER_CONTROLr, L3_DEFIP_TCAM_PARITY_ENf, TCAM_PARITY_MASKf}, 2102 { L3_DEFIP_PAIR_128m, ILPM_SER_CONTROLr, L3_DEFIP_TCAM_PARITY_ENf, TCAM_PARITY_MASK_UPRf}, 2103 { IFP_TCAMm, IFP_TCAM_CAM_CONTROLr, PARITY_ENf, TCAM_PARITY_MASKf}, 2104 { IFP_TCAM_WIDEm, IFP_TCAM_CAM_CONTROLr, PARITY_ENf, TCAM_PARITY_MASKf}, 2105 { INVALIDm}, 2106 }; 2107 2108 static soc_mem_t _soc_th2_skip_populating[] = { 2109 /* Shared MMU_WRED_ENABLE_ECCP_MEM.PROFILE_ECCP_EN */ 2110 MMU_WRED_DROP_CURVE_PROFILE_0m, 2111 MMU_WRED_DROP_CURVE_PROFILE_0_Am, 2112 MMU_WRED_DROP_CURVE_PROFILE_0_Bm, 2113 MMU_WRED_DROP_CURVE_PROFILE_1m, 2114 MMU_WRED_DROP_CURVE_PROFILE_1_Am, 2115 MMU_WRED_DROP_CURVE_PROFILE_1_Bm, 2116 MMU_WRED_DROP_CURVE_PROFILE_2m, 2117 MMU_WRED_DROP_CURVE_PROFILE_2_Am, 2118 MMU_WRED_DROP_CURVE_PROFILE_2_Bm, 2119 MMU_WRED_DROP_CURVE_PROFILE_3m, 2120 MMU_WRED_DROP_CURVE_PROFILE_3_Am, 2121 MMU_WRED_DROP_CURVE_PROFILE_3_Bm, 2122 MMU_WRED_DROP_CURVE_PROFILE_4m, 2123 MMU_WRED_DROP_CURVE_PROFILE_4_Am, 2124 MMU_WRED_DROP_CURVE_PROFILE_4_Bm, 2125 MMU_WRED_DROP_CURVE_PROFILE_5m, 2126 MMU_WRED_DROP_CURVE_PROFILE_5_Am, 2127 MMU_WRED_DROP_CURVE_PROFILE_5_Bm, 2128 MMU_WRED_DROP_CURVE_PROFILE_6m, 2129 MMU_WRED_DROP_CURVE_PROFILE_6_Am, 2130 MMU_WRED_DROP_CURVE_PROFILE_6_Bm, 2131 MMU_WRED_DROP_CURVE_PROFILE_7m, 2132 MMU_WRED_DROP_CURVE_PROFILE_7_Am, 2133 MMU_WRED_DROP_CURVE_PROFILE_7_Bm, 2134 MMU_WRED_DROP_CURVE_PROFILE_8m, 2135 MMU_WRED_DROP_CURVE_PROFILE_8_Am, 2136 MMU_WRED_DROP_CURVE_PROFILE_8_Bm, 2137 2138 /*Shared MMU_SCFG_PARITY_EN.TDM_PARITY_EN*/ 2139 TDM_CALENDAR0m, 2140 TDM_CALENDAR1m, 2141 2142 INVALIDm 2143 }; 2144 2145 #endif 2146 2147 #ifdef BCM_TOMAHAWK2_SUPPORT 2148 static uint32 _soc_th2_ip_pipe_fifo_bmask[SOC_MAX_NUM_DEVICES][4]; 2149 2150 STATIC soc_error_t _soc_th2_ser_tcam_wrapper_found(soc_mem_t mem); 2151 STATIC soc_error_t _soc_th2_tcam_wrapper_enable(int unit, int enable); 2152 STATIC soc_error_t 2153 _soc_th2_ser_tcam_control_reg_get(soc_mem_t mem, soc_reg_t *ser_control_reg, 2154 soc_field_t *ser_enable_field); 2155 #endif 2156 2157 #if defined(BCM_TOMAHAWK3_SUPPORT) 2158 STATIC int 2159 _soc_th3_reg32_par_en_modify(int unit, soc_reg_t reg, soc_field_t field, 2160 int enable); 2161 STATIC int 2162 _soc_tomahawk3_idb_enable(int unit, soc_reg_t reg_name, int enable, int *is_idb); 2163 2164 extern _soc_bus_ser_en_info_t _soc_bcm56980_a0_ip_bus_ser_info[]; 2165 extern _soc_buffer_ser_en_info_t _soc_bcm56980_a0_ip_buffer_ser_info[]; 2166 extern _soc_bus_ser_en_info_t _soc_bcm56980_a0_ep_bus_ser_info[]; 2167 extern _soc_buffer_ser_en_info_t _soc_bcm56980_a0_ep_buffer_ser_info[]; 2168 2169 uint32 ser_th3_bus_buffer_hwbase[] = { 2170 0x5e, /* EFP_BUS */ 2171 0x64, /* EPOST_OUTPUT_EVENT_DATA_FIFO */ 2172 0x5c, /* EPMOD_BUS */ 2173 0xb, /* PT_HWY_IADAPT */ 2174 0x65, /* EPOST_SLOT_PIPELINE */ 2175 0, /* DPP_OUTPUT_EVENT_FIFO */ 2176 0x42, /* EARB_SOP_EVENT_FIFO */ 2177 0x10, /* IFWD1_PASSTHRU_BUS */ 2178 0x9, /* SW_EOP_BUFFER_B */ 2179 0x19, /* BUS_IRSEL */ 2180 0x60, /* EP_EFPBUF */ 2181 0xf, /* ALL_CELLS_IPARS_TO_ISW_PT_HWY_FIFO */ 2182 0x17, /* PT_HWY_IFP */ 2183 0x5d, /* EFPPARS_BUS */ 2184 0, /* CELL_QUEUE */ 2185 0x1, /* IARB_EVENT_FIFO */ 2186 0, /* SLOT_PIPELINE */ 2187 0x66, /* EPOST_PKT_BUF */ 2188 0x64, /* EPOST_OUTPUT_EVENT_FIFO */ 2189 0x41, /* EP_PACKET_DATA_BUS */ 2190 0x40, /* EP_MPB_BUS */ 2191 0x18 /* PT_HWY_IRSEL */ 2192 }; 2193 2194 _soc_bus_buffer_ser_force_info_t ser_th3_bus_buffer_skip_test[] = { 2195 { "EPOST_SLOT_PIPELINE", EPOST_SER_CONTROLr, SLOT_PIPELINE_ECC_CORRUPTf }, 2196 { "DPP_OUTPUT_EVENT_FIFO", IPOST_SER_CONTROLr, EVENT_FIFO_ECC_FORCE_ERRf }, 2197 { "EARB_SOP_EVENT_FIFO", EGR_EARB_SER_CONTROLr, EARB_SOP_EVENT_FIFO_ECC_FORCE_ERRf }, 2198 { "IARB_EVENT_FIFO", IARB_SER_CONTROLr, EVENT_FIFO_ECC_CORRUPTf }, 2199 { "SLOT_PIPELINE", IPOST_SER_CONTROLr, SLOT_PIPELINE_ECC_FORCE_ERRf }, 2200 { "EPOST_OUTPUT_EVENT_FIFO", EPOST_SER_CONTROLr, OUTPUT_FIFO_ECC_CORRUPTf }, 2201 { "CELL_QUEUE", IPOST_SER_CONTROLr, CELL_QUEUE_ECC_FORCE_ERRf }, 2202 { "", INVALIDr } /* end */ 2203 }; 2204 2205 _soc_buffer_ser_en_info_t _soc_th3_no_mapping_ser_info[] = { 2206 { "TCAM POOL0", IFP_TCAM_POOL0_BISTCTRLr, PARITY_ENf, INVALIDr, INVALIDf }, 2207 { "TCAM POOL1", IFP_TCAM_POOL1_BISTCTRLr, PARITY_ENf, INVALIDr, INVALIDf }, 2208 { "TCAM POOL2", IFP_TCAM_POOL2_BISTCTRLr, PARITY_ENf, INVALIDr, INVALIDf }, 2209 { "TCAM POOL3", IFP_TCAM_POOL3_BISTCTRLr, PARITY_ENf, INVALIDr, INVALIDf }, 2210 { "VFP CAM BIST CONTROL", VFP_CAM_BIST_CONTROLr, PARITY_ENf, INVALIDr, INVALIDf }, 2211 { "METER MUX DATA STAGING", IFP_PARITY_CONTROLr, METER_MUX_DATA_STAGING_PARITY_ENf, INVALIDr, INVALIDf }, 2212 { "PORT METER MAP", IFP_PARITY_CONTROLr, PORT_METER_MAP_PARITY_ENf, INVALIDr, INVALIDf }, 2213 { "COUNTER MUX DATA STAGING", IFP_PARITY_CONTROLr, COUNTER_MUX_DATA_STAGING_PARITY_ENf, INVALIDr, INVALIDf }, 2214 { "IFP COUNTER", IFP_PARITY_CONTROLr, COUNTER_PARITY_ENf, INVALIDr, INVALIDf }, 2215 { "EGR PW INIT COUNTER", EGR_EFP_EN_COR_ERR_RPTr, EGR_PW_INIT_COUNTER_EN_COR_ERR_RPTf, INVALIDr, INVALIDf }, 2216 { "EGR METER TABLE", EGR_EFP_EN_COR_ERR_RPTr, EGR_METER_TABLE_EN_COR_ERR_RPTf, INVALIDr, INVALIDf }, 2217 { "EINITBUF", EGR_ESW_EN_COR_ERR_RPTr, EINITBUFf, INVALIDr, INVALIDf }, 2218 { "ESW_BUS", EGR_ESW_SER_CONTROLr, ESW_BUS_PARITY_ENf, INVALIDr, INVALIDf }, 2219 { "", INVALIDr } 2220 }; 2221 2222 static soc_field_t _soc_th3_idb_obm_enable_fields[] = { 2223 MON_EN_COR_ERR_RPTf, 2224 MON_ECC_ENABLEf, 2225 CTRL_EN_COR_ERR_RPTf, 2226 CTRL_ECC_ENABLEf, 2227 DATA_EN_COR_ERR_RPTf, 2228 DATA_ECC_ENABLEf, 2229 INVALIDf 2230 }; 2231 2232 static _soc_th_ser_reg_t _soc_th3_idb_obm0_intr_status_regs[] = { 2233 { IDB_OBM0_DATA_ECC_STATUSr, "IDB_OBM0_DATA_ECC_STATUS" }, 2234 { IDB_OBM0_CTRL_ECC_STATUSr, "IDB_OBM0_CTRL_ECC_STATUS" }, 2235 { IDB_OBM0_OVERSUB_MON_ECC_STATUSr, "IDB_OBM0_OVERSUB_MON_ECC_STATUS" }, 2236 { INVALIDr, "INVALID" } 2237 }; 2238 static _soc_th_ser_reg_t _soc_th3_idb_obm1_intr_status_regs[] = { 2239 { IDB_OBM1_DATA_ECC_STATUSr, "IDB_OBM1_DATA_ECC_STATUS" }, 2240 { IDB_OBM1_CTRL_ECC_STATUSr, "IDB_OBM1_CTRL_ECC_STATUS" }, 2241 { IDB_OBM1_OVERSUB_MON_ECC_STATUSr, "IDB_OBM1_OVERSUB_MON_ECC_STATUS" }, 2242 { INVALIDr, "INVALID" } 2243 }; 2244 static _soc_th_ser_reg_t _soc_th3_idb_obm2_intr_status_regs[] = { 2245 { IDB_OBM2_DATA_ECC_STATUSr, "IDB_OBM2_DATA_ECC_STATUS" }, 2246 { IDB_OBM2_CTRL_ECC_STATUSr, "IDB_OBM2_CTRL_ECC_STATUS" }, 2247 { IDB_OBM2_OVERSUB_MON_ECC_STATUSr, "IDB_OBM2_OVERSUB_MON_ECC_STATUS" }, 2248 { INVALIDr, "INVALID" } 2249 }; 2250 static _soc_th_ser_reg_t _soc_th3_idb_obm3_intr_status_regs[] = { 2251 { IDB_OBM3_DATA_ECC_STATUSr, "IDB_OBM3_DATA_ECC_STATUS" }, 2252 { IDB_OBM3_CTRL_ECC_STATUSr, "IDB_OBM3_CTRL_ECC_STATUS" }, 2253 { IDB_OBM3_OVERSUB_MON_ECC_STATUSr, "IDB_OBM3_OVERSUB_MON_ECC_STATUS" }, 2254 { INVALIDr, "INVALID" } 2255 }; 2256 2257 soc_field_t _soc_th3_idb_ca_lpbk_enable_fields[] = { 2258 CA_LPBK_FIFO_ECC_ENABLEf, 2259 CA_LPBK_FIFO_EN_COR_ERR_RPTf, 2260 INVALIDf 2261 }; 2262 2263 soc_field_t _soc_th3_idb_ca_cpu_enable_fields[] = { 2264 CA_CPU_FIFO_ECC_ENABLEf, 2265 CA_CPU_FIFO_EN_COR_ERR_RPTf, 2266 INVALIDf 2267 }; 2268 2269 soc_field_t _soc_th3_idb_ca_fifo_enable_fields[] = { 2270 CA_FIFO_EN_COR_ERR_RPTf, 2271 CA_FIFO_ECC_ENABLEf, 2272 INVALIDf 2273 }; 2274 2275 2276 static _soc_th_ser_info_t _soc_th3_idb_ser_info[] = { 2277 { _SOC_PARITY_TYPE_ECC, NULL, 0, 2278 LPBK_FIFO_ECC_ERRf, LPBK_FIFO_ECC_ERRf, 2279 INVALIDm, "CA-LPBK packet buffer memory", 2280 IDB_CA_LPBK_SER_CONTROLr, INVALIDf, _soc_th3_idb_ca_lpbk_enable_fields, 2281 INVALIDr, INVALIDf, NULL, 2282 IDB_CA_LPBK_ECC_STATUSr, NULL, ECC_ERRf, NULL, 2283 INVALIDr, INVALIDf, NULL 2284 }, 2285 { _SOC_PARITY_TYPE_ECC, NULL, 0, 2286 CPU_FIFO_ECC_ERRf, CPU_FIFO_ECC_ERRf, 2287 INVALIDm, "CA-CPU packet buffer memory", 2288 IDB_CA_CPU_SER_CONTROLr, INVALIDf, _soc_th3_idb_ca_cpu_enable_fields, 2289 INVALIDr, INVALIDf, NULL, 2290 IDB_CA_CPU_ECC_STATUSr, NULL, ECC_ERRf, NULL, 2291 INVALIDr, INVALIDf, NULL 2292 }, 2293 { _SOC_PARITY_TYPE_ECC, NULL, 0, 2294 CA3_FIFO_ECC_ERRf, CA3_FIFO_ECC_ERRf, 2295 INVALIDm, "CA3 FIFO", 2296 IDB_CA3_SER_CONTROLr, INVALIDf, _soc_th3_idb_ca_fifo_enable_fields, 2297 INVALIDr, INVALIDf, NULL, 2298 /* need to confirm the status reg*/ 2299 IDB_CA_ECC_STATUSr, NULL, ECC_ERRf, NULL, 2300 INVALIDr, INVALIDf, NULL 2301 }, 2302 { _SOC_PARITY_TYPE_ECC, NULL, 0, 2303 OBM3_ECC_ERRf, OBM3_ECC_ERRf, 2304 INVALIDm, "IDB OBM3 packet data memory", 2305 IDB_OBM3_SER_CONTROLr, INVALIDf, _soc_th3_idb_obm_enable_fields, 2306 INVALIDr, INVALIDf, NULL, 2307 /* need to confirm the status reg*/ 2308 INVALIDr, _soc_th3_idb_obm3_intr_status_regs, ECC_ERRf, NULL, 2309 INVALIDr, INVALIDf, NULL 2310 }, 2311 { _SOC_PARITY_TYPE_ECC, NULL, 0, 2312 CA2_FIFO_ECC_ERRf, CA2_FIFO_ECC_ERRf, 2313 INVALIDm, "CA2 FIFO", 2314 IDB_CA2_SER_CONTROLr, INVALIDf, _soc_th3_idb_ca_fifo_enable_fields, 2315 INVALIDr, INVALIDf, NULL, 2316 /* need to confirm the status reg*/ 2317 IDB_CA_ECC_STATUSr, NULL, ECC_ERRf, NULL, 2318 INVALIDr, INVALIDf, NULL 2319 }, 2320 { _SOC_PARITY_TYPE_ECC, NULL, 0, 2321 OBM2_ECC_ERRf, OBM2_ECC_ERRf, 2322 INVALIDm, "IDB OBM2 packet data memory", 2323 IDB_OBM2_SER_CONTROLr, INVALIDf, _soc_th3_idb_obm_enable_fields, 2324 INVALIDr, INVALIDf, NULL, 2325 /* need to confirm the status reg*/ 2326 INVALIDr, _soc_th3_idb_obm2_intr_status_regs, ECC_ERRf, NULL, 2327 INVALIDr, INVALIDf, NULL 2328 }, 2329 { _SOC_PARITY_TYPE_ECC, NULL, 0, 2330 CA1_FIFO_ECC_ERRf, CA1_FIFO_ECC_ERRf, 2331 INVALIDm, "CA1 FIFO", 2332 IDB_CA1_SER_CONTROLr, INVALIDf, _soc_th3_idb_ca_fifo_enable_fields, 2333 INVALIDr, INVALIDf, NULL, 2334 /* need to confirm the status reg*/ 2335 IDB_CA_ECC_STATUSr, NULL, ECC_ERRf, NULL, 2336 INVALIDr, INVALIDf, NULL 2337 }, 2338 { _SOC_PARITY_TYPE_ECC, NULL, 0, 2339 OBM1_ECC_ERRf, OBM1_ECC_ERRf, 2340 INVALIDm, "IDB OBM1 packet data memory", 2341 IDB_OBM1_SER_CONTROLr, INVALIDf, _soc_th3_idb_obm_enable_fields, 2342 INVALIDr, INVALIDf, NULL, 2343 /* need to confirm the status reg*/ 2344 INVALIDr, _soc_th3_idb_obm1_intr_status_regs, ECC_ERRf, NULL, 2345 INVALIDr, INVALIDf, NULL 2346 }, 2347 { _SOC_PARITY_TYPE_ECC, NULL, 0, 2348 CA0_FIFO_ECC_ERRf, CA0_FIFO_ECC_ERRf, 2349 INVALIDm, "CA0 FIFO", 2350 IDB_CA0_SER_CONTROLr, INVALIDf, _soc_th3_idb_ca_fifo_enable_fields, 2351 INVALIDr, INVALIDf, NULL, 2352 /* need to confirm the status reg*/ 2353 IDB_CA_ECC_STATUSr, NULL, ECC_ERRf, NULL, 2354 INVALIDr, INVALIDf, NULL 2355 }, 2356 { _SOC_PARITY_TYPE_ECC, NULL, 0, 2357 OBM0_ECC_ERRf, OBM0_ECC_ERRf, 2358 INVALIDm, "IDB OBM0 packet data memory", 2359 IDB_OBM0_SER_CONTROLr, INVALIDf, _soc_th3_idb_obm_enable_fields, 2360 INVALIDr, INVALIDf, NULL, 2361 /* need to confirm the status reg*/ 2362 INVALIDr, _soc_th3_idb_obm0_intr_status_regs, ECC_ERRf, NULL, 2363 INVALIDr, INVALIDf, NULL 2364 }, 2365 2366 2367 { _SOC_PARITY_TYPE_NONE } /* table terminator */ 2368 }; 2369 2370 soc_field_t _soc_th3_edb_ctrl_buffer_enable_fields[] = { 2371 PM3_ECC_ENf, 2372 PM2_ECC_ENf, 2373 PM1_ECC_ENf, 2374 PM0_ECC_ENf, 2375 CM_ECC_ENf, 2376 LPBK_ECC_ENf, 2377 XMIT_START_COUNT_ECC_ENf, 2378 INVALIDf 2379 }; 2380 2381 soc_field_t _soc_th3_edb_ctrl_buffer_1b_enable_fields[] = { 2382 PM3_ENf, 2383 PM2_ENf, 2384 PM1_ENf, 2385 PM0_ENf, 2386 CM_ENf, 2387 LPBK_ENf, 2388 XMIT_START_COUNT_ENf, 2389 INVALIDf 2390 }; 2391 2392 soc_field_t _soc_th3_edb_data_buffer_enable_fields[] = { 2393 PM3_ECC_ENf, 2394 PM2_ECC_ENf, 2395 PM1_ECC_ENf, 2396 PM0_ECC_ENf, 2397 RESIDUAL_ECC_ENf, 2398 CM_ECC_ENf, 2399 LPBK_ECC_ENf, 2400 INVALIDf 2401 }; 2402 2403 soc_field_t _soc_th3_edb_data_buffer_1b_enable_fields[] = { 2404 PM3_ENf, 2405 PM2_ENf, 2406 PM1_ENf, 2407 PM0_ENf, 2408 RESIDUAL_ENf, 2409 CM_ENf, 2410 LPBK_ENf, 2411 INVALIDf 2412 }; 2413 2414 static _soc_th_ser_info_t _soc_th3_edb_ser_info[] = { 2415 { _SOC_PARITY_TYPE_ECC, NULL, 0, 2416 INVALIDf, INVALIDf, 2417 INVALIDm, "EDB control buffer", 2418 EDB_CONTROL_BUFFER_ECC_ENr, INVALIDf, _soc_th3_edb_ctrl_buffer_enable_fields, 2419 INVALIDr, INVALIDf, NULL, 2420 INVALIDr, NULL, INVALIDf, NULL, 2421 INVALIDr, INVALIDf, NULL 2422 }, 2423 { _SOC_PARITY_TYPE_ECC, NULL, 0, 2424 INVALIDf, INVALIDf, 2425 INVALIDm, "EDB data buffer", 2426 EDB_DATA_BUFFER_ECC_ENr, INVALIDf, _soc_th3_edb_data_buffer_enable_fields, 2427 INVALIDr, INVALIDf, NULL, 2428 INVALIDr, NULL, INVALIDf, NULL, 2429 INVALIDr, INVALIDf, NULL 2430 }, 2431 { _SOC_PARITY_TYPE_ECC, NULL, 0, 2432 INVALIDf, INVALIDf, 2433 INVALIDm, "EDB control buffer 1-bit", 2434 EDB_CONTROL_BUFFER_EN_COR_ERR_RPTr, INVALIDf, _soc_th3_edb_ctrl_buffer_1b_enable_fields, 2435 INVALIDr, INVALIDf, NULL, 2436 INVALIDr, NULL, INVALIDf, NULL, 2437 INVALIDr, INVALIDf, NULL 2438 }, 2439 { _SOC_PARITY_TYPE_ECC, NULL, 0, 2440 INVALIDf, INVALIDf, 2441 INVALIDm, "EDB data buffer 1-bit", 2442 EDB_DATA_BUFFER_EN_COR_ERR_RPTr, INVALIDf, _soc_th3_edb_data_buffer_1b_enable_fields, 2443 INVALIDr, INVALIDf, NULL, 2444 INVALIDr, NULL, INVALIDf, NULL, 2445 INVALIDr, INVALIDf, NULL 2446 }, 2447 2448 { _SOC_PARITY_TYPE_NONE } 2449 }; 2450 2451 static _soc_th_ser_info_t _soc_th3_ipost_ser_info[] = { 2452 { _SOC_PARITY_TYPE_ECC, NULL, 0, 2453 SLOT_PIPELINE_ECC_ERRf, SLOT_PIPELINE_ECC_ERRf, 2454 INVALIDm, "Slot pipeline", 2455 INVALIDr, INVALIDf, NULL, 2456 INVALIDr, INVALIDf, NULL, 2457 SLOT_PIPELINE_ECC_STATUS_INTRr, NULL, ECC_ERRf, NULL, 2458 INVALIDr, INVALIDf, NULL 2459 }, 2460 { _SOC_PARITY_TYPE_ECC, NULL, 0, 2461 CELL_QUEUE_ECC_ERRf, CELL_QUEUE_ECC_ERRf, 2462 INVALIDm, "Cell queue", 2463 INVALIDr, INVALIDf, NULL, 2464 INVALIDr, INVALIDf, NULL, 2465 CELL_QUEUE_ECC_STATUS_INTRr, NULL, ECC_ERRf, NULL, 2466 INVALIDr, INVALIDf, NULL 2467 }, 2468 /*{ _SOC_PARITY_TYPE_ECC, NULL, 0, 2469 EOP_BUFFER_MTU_ECC_ERRf, EOP_BUFFER_MTU_ECC_ERRf, 2470 INVALIDm, "EOP_BUFFER_MTU", 2471 INVALIDr, INVALIDf, NULL, 2472 INVALIDr, INVALIDf, NULL, 2473 INVALIDr, NULL, ECC_ERRf, NULL, 2474 INVALIDr, INVALIDf, NULL 2475 },*/ 2476 { _SOC_PARITY_TYPE_ECC, NULL, 0, 2477 EVENT_FIFO_ECC_ERRf, EVENT_FIFO_ECC_ERRf, 2478 INVALIDm, "Event FIFO", 2479 INVALIDr, INVALIDf, NULL, 2480 INVALIDr, INVALIDf, NULL, 2481 EVENT_FIFO_ECC_STATUS_INTRr, NULL, ECC_ERRf, NULL, 2482 INVALIDr, INVALIDf, NULL 2483 }, 2484 { _SOC_PARITY_TYPE_NONE } /* table terminator */ 2485 }; 2486 2487 2488 static _soc_th_ser_reg_t _soc_th3_pm_xlp_tx_status_reg[] = { 2489 { XLPORT_MIB_TSC0_ECC_STATUSr, "XLP MIB TSC0 ECC" }, 2490 { XLPORT_MIB_TSC1_ECC_STATUSr, "XLP MIB TSC1 ECC" }, 2491 { INVALIDr, "INVALID"} 2492 }; 2493 2494 static _soc_th_ser_reg_t _soc_th3_pm_xlp_rx_status_reg[] = { 2495 { XLPORT_MIB_RSC0_ECC_STATUSr, "XLP MIB RSC0 ECC" }, 2496 { XLPORT_MIB_RSC1_ECC_STATUSr, "XLP MIB RSC1 ECC" }, 2497 { INVALIDr, "INVALID"} 2498 }; 2499 2500 static _soc_th_ser_info_t _soc_th3_pm_xlp_ser_info[] = { 2501 { _SOC_PARITY_TYPE_ECC, NULL, 0, 2502 MIB_RX_MEM_ERRf, MIB_RX_MEM_ERRf, 2503 INVALIDm, "MIB RX Statistic Counter memory", 2504 XLPORT_ECC_CONTROLr, MIB_RSC_MEM_ENf, NULL, 2505 INVALIDr, INVALIDf, NULL, 2506 INVALIDr, _soc_th3_pm_xlp_rx_status_reg, INVALIDf, NULL, 2507 INVALIDr, INVALIDf, NULL 2508 }, 2509 { _SOC_PARITY_TYPE_ECC, NULL, 0, 2510 MIB_TX_MEM_ERRf, MIB_TX_MEM_ERRf, 2511 INVALIDm, "MIB TX Statistic Counter memory", 2512 XLPORT_ECC_CONTROLr, MIB_TSC_MEM_ENf, NULL, 2513 INVALIDr, INVALIDf, NULL, 2514 INVALIDr, _soc_th3_pm_xlp_tx_status_reg, INVALIDf, NULL, 2515 INVALIDr, INVALIDf, NULL 2516 }, 2517 2518 { _SOC_PARITY_TYPE_MAC_TX_CDC, NULL, 0, 2519 MAC_ERRf, MAC_ERRf, 2520 INVALIDm, "XLMAC TX CDC single bit", 2521 XLMAC_ECC_CTRLr, TX_CDC_ECC_CTRL_ENf, NULL, 2522 XLMAC_INTR_ENABLEr, EN_TX_CDC_SINGLE_BIT_ERRf, NULL, 2523 XLMAC_INTR_STATUSr, NULL, SUM_TX_CDC_SINGLE_BIT_ERRf, NULL, 2524 XLMAC_CLEAR_ECC_STATUSr, CLEAR_TX_CDC_SINGLE_BIT_ERRf, NULL 2525 }, 2526 { _SOC_PARITY_TYPE_MAC_TX_CDC, NULL, 0, 2527 MAC_ERRf, MAC_ERRf, 2528 INVALIDm, "XLMAC TX CDC double bits", 2529 XLMAC_ECC_CTRLr, TX_CDC_ECC_CTRL_ENf, NULL, 2530 XLMAC_INTR_ENABLEr, EN_TX_CDC_DOUBLE_BIT_ERRf, NULL, 2531 XLMAC_INTR_STATUSr, NULL, SUM_TX_CDC_DOUBLE_BIT_ERRf, NULL, 2532 XLMAC_CLEAR_ECC_STATUSr, CLEAR_TX_CDC_DOUBLE_BIT_ERRf, NULL 2533 }, 2534 { _SOC_PARITY_TYPE_MAC_RX_CDC, NULL, 0, 2535 MAC_ERRf, MAC_ERRf, 2536 INVALIDm, "XLMAC RX CDC single bit", 2537 XLMAC_ECC_CTRLr, RX_CDC_ECC_CTRL_ENf, NULL, 2538 XLMAC_INTR_ENABLEr, EN_RX_CDC_SINGLE_BIT_ERRf, NULL, 2539 XLMAC_INTR_STATUSr, NULL, SUM_RX_CDC_SINGLE_BIT_ERRf, NULL, 2540 XLMAC_CLEAR_ECC_STATUSr, CLEAR_RX_CDC_SINGLE_BIT_ERRf, NULL 2541 }, 2542 { _SOC_PARITY_TYPE_MAC_RX_CDC, NULL, 0, 2543 MAC_ERRf, MAC_ERRf, 2544 INVALIDm, "XLMAC RX CDC double bits", 2545 XLMAC_ECC_CTRLr, RX_CDC_ECC_CTRL_ENf, NULL, 2546 XLMAC_INTR_ENABLEr, EN_RX_CDC_DOUBLE_BIT_ERRf, NULL, 2547 XLMAC_INTR_STATUSr, NULL, SUM_RX_CDC_DOUBLE_BIT_ERRf, NULL, 2548 XLMAC_CLEAR_ECC_STATUSr, CLEAR_RX_CDC_DOUBLE_BIT_ERRf, NULL 2549 }, 2550 2551 { _SOC_PARITY_TYPE_NONE } /* table terminator */ 2552 }; 2553 2554 soc_field_t _soc_th3_cdmac_ecc_enable_fields[] = { 2555 TX_CDC_ECC_CTRL_ENf, 2556 MIB_COUNTER_ECC_CTRL_ENf, 2557 INVALIDf 2558 }; 2559 2560 soc_field_t _soc_th3_cdmac_intr_enable_fields[] = { 2561 TX_CDC_SINGLE_BIT_ERRf, 2562 TX_CDC_DOUBLE_BIT_ERRf, 2563 MIB_COUNTER_SINGLE_BIT_ERRf, 2564 MIB_COUNTER_DOUBLE_BIT_ERRf, 2565 MIB_COUNTER_MULTIPLE_ERRf, 2566 INVALIDf 2567 }; 2568 2569 soc_field_t _soc_th3_cdmac_ecc_status_fields[] = { 2570 TX_CDC_SINGLE_BIT_ERRf, 2571 TX_CDC_DOUBLE_BIT_ERRf, 2572 MIB_COUNTER_SINGLE_BIT_ERRf, 2573 MIB_COUNTER_DOUBLE_BIT_ERRf, 2574 MIB_COUNTER_MULTIPLE_ERRf, 2575 INVALIDf 2576 }; 2577 2578 static _soc_th_ser_info_t _soc_th3_pm_cdp_ser_info[] = { 2579 { _SOC_PARITY_TYPE_CDMAC, NULL, 0, 2580 MAC_ERRf, MAC_ERRf, 2581 INVALIDm, "CDMAC", 2582 CDMAC_ECC_CTRLr, INVALIDf, _soc_th3_cdmac_ecc_enable_fields, 2583 CDMAC_INTR_ENABLEr, INVALIDf, _soc_th3_cdmac_intr_enable_fields, 2584 CDMAC_ECC_STATUSr, NULL, INVALIDf, _soc_th3_cdmac_ecc_status_fields, 2585 INVALIDr, INVALIDf, NULL 2586 }, 2587 2588 { _SOC_PARITY_TYPE_NONE } /* table terminator */ 2589 }; 2590 2591 2592 static soc_field_t _soc_th3_mmu_top_int_enable_fields[] = { 2593 ITMCFG1_INT_ENf, 2594 ITMCFG0_INT_ENf, 2595 EBCFG7_INT_ENf, 2596 EBCFG6_INT_ENf, 2597 EBCFG5_INT_ENf, 2598 EBCFG4_INT_ENf, 2599 EBCFG3_INT_ENf, 2600 EBCFG2_INT_ENf, 2601 EBCFG1_INT_ENf, 2602 EBCFG0_INT_ENf, 2603 MEM_PAR_ERR_INT_ENf, 2604 INVALIDf 2605 }; 2606 2607 static soc_field_t _soc_th3_mmu_top_int_status_fields[] = { 2608 ITMCFG1_INT_STATf, 2609 ITMCFG0_INT_STATf, 2610 EBCFG7_INT_STATf, 2611 EBCFG6_INT_STATf, 2612 EBCFG5_INT_STATf, 2613 EBCFG4_INT_STATf, 2614 EBCFG3_INT_STATf, 2615 EBCFG2_INT_STATf, 2616 EBCFG1_INT_STATf, 2617 EBCFG0_INT_STATf, 2618 MEM_PAR_ERR_INT_STATf, 2619 INVALIDf 2620 }; 2621 2622 static _soc_th_ser_info_t _soc_th3_mmu_ser_info[] = { 2623 /* SW is allowed to clear an interrupt by writing 1'b1 to that status bit. */ 2624 { _SOC_PARITY_TYPE_MMU_GLB, NULL, 0, 2625 INVALIDf, INVALIDf, 2626 INVALIDm, "MMU GLB MEM PAR", 2627 INVALIDr, INVALIDf, NULL, 2628 MMU_GLBCFG_CPU_INT_ENr, MEM_PAR_ERR_INT_ENf, NULL, 2629 MMU_GLBCFG_CPU_INT_STATr, NULL, MEM_PAR_ERR_INT_STATf, NULL, 2630 MMU_GLBCFG_CPU_INT_STATr, MEM_PAR_ERR_INT_STATf, NULL 2631 }, 2632 { _SOC_PARITY_TYPE_MMU_ITMCFG, NULL, 0, 2633 INVALIDf, INVALIDf, 2634 INVALIDm, "MMU ITM MEM PAR", 2635 INVALIDr, INVALIDf, NULL, 2636 MMU_ITMCFG_CPU_INT_ENr, MEM_PAR_ERR_INT_ENf, NULL, 2637 MMU_ITMCFG_CPU_INT_STATr, NULL, MEM_PAR_ERR_INT_STATf, NULL, 2638 MMU_ITMCFG_CPU_INT_STATr, MEM_PAR_ERR_INT_STATf, NULL 2639 }, 2640 { _SOC_PARITY_TYPE_MMU_EBCFG, NULL, 0, 2641 INVALIDf, INVALIDf, 2642 INVALIDm, "MMU EB MEM PAR", 2643 INVALIDr, INVALIDf, NULL, 2644 MMU_EBCFG_CPU_INT_ENr, MEM_PAR_ERR_INT_ENf, NULL, 2645 MMU_EBCFG_CPU_INT_STATr, NULL, MEM_PAR_ERR_INT_STATf, NULL, 2646 MMU_EBCFG_CPU_INT_STATr, MEM_PAR_ERR_INT_STATf, NULL 2647 }, 2648 { _SOC_PARITY_TYPE_NONE } /* table terminator */ 2649 }; 2650 2651 2652 static _soc_th_ser_info_t _soc_th3_mmu_top_ser_info[] = { 2653 { _SOC_PARITY_TYPE_MMU_SER, _soc_th3_mmu_ser_info, 0, 2654 INVALIDf, INVALIDf, 2655 INVALIDm, "MMU MEM PAR", 2656 INVALIDr, INVALIDf, NULL, 2657 MMU_GLBCFG_CPU_INT_ENr, INVALIDf, 2658 _soc_th3_mmu_top_int_enable_fields, 2659 MMU_GLBCFG_CPU_INT_STATr, 2660 NULL, INVALIDf, _soc_th3_mmu_top_int_status_fields, 2661 INVALIDr, INVALIDf, NULL 2662 }, 2663 { _SOC_PARITY_TYPE_NONE } /* table terminator */ 2664 }; 2665 2666 static soc_field_t _soc_th3_cev_ser_enable_fields[] = { 2667 PARITY_ENf, 2668 EN_COR_ERR_RPTf, 2669 INVALIDf 2670 }; 2671 static _soc_th_ser_info_t _soc_th3_cev_ser_info[] = { 2672 { _SOC_PARITY_TYPE_ECC, NULL, 0, 2673 FIFO_PARITY_ERRORf, FIFO_PARITY_ERRORf, 2674 INVALIDm, "Central fifo", 2675 CENTRAL_CTR_EVICTION_FIFO_PARITY_CONTROLr, INVALIDf, _soc_th3_cev_ser_enable_fields, 2676 INVALIDr, INVALIDf, NULL, 2677 CENTRAL_CTR_EVICTION_INTR_STATUSr, NULL, FIFO_PARITY_ERRORf, NULL, 2678 INVALIDr, INVALIDf, NULL 2679 }, 2680 2681 { _SOC_PARITY_TYPE_NONE} /* table terminator */ 2682 }; 2683 2684 #define _SOC_TH3_CEV_INTR 0x00000001 2685 2686 static const 2687 _soc_th_ser_route_block_t _soc_th3_ser_route_blocks[] = { 2688 { 0, 0x00000001, /* CEV_TO_CMIC_INTR */ 2689 SOC_BLK_IPIPE, -1, CENTRAL_CTR_EVICTION_INTR_ENABLEr, CENTRAL_CTR_EVICTION_INTR_STATUSr, 2690 INVALIDf, _soc_th3_cev_ser_info, 0 }, 2691 { 0, 0x00000002, /* DLB_CREDIT_TO_CMIC_INTR */ 2692 SOC_BLK_IPIPE, 0, DLB_ECMP_INTR_ENABLEr, INVALIDr, SER_FIFO_NON_EMPTYf, 2693 NULL, 0 }, 2694 { 0, 0x00000010, /* MMU_TO_CMIC_INTR */ 2695 SOC_BLK_MMU, -1, INVALIDr, INVALIDr, INVALIDf, 2696 _soc_th3_mmu_top_ser_info, 0 }, 2697 /* xsm: not using MMU_GLB or MMU_XPE or MMU_SC is on purpose */ 2698 { 0, 0x00000020, /* PIPE0_EFPMOD_TO_CMIC_INTR */ 2699 SOC_BLK_EPIPE, 0, EGR_INTR_ENABLE_2r, INVALIDr, SER_FIFO_NON_EMPTYf, 2700 NULL, 0 }, 2701 { 0, 0x00000040, /* PIPE1_EFPMOD_TO_CMIC_INTR */ 2702 SOC_BLK_EPIPE, 1, EGR_INTR_ENABLE_2r, INVALIDr, SER_FIFO_NON_EMPTYf, 2703 NULL, 0 }, 2704 { 0, 0x00000080, /* PIPE2_EFPMOD_TO_CMIC_INTR */ 2705 SOC_BLK_EPIPE, 2, EGR_INTR_ENABLE_2r, INVALIDr, SER_FIFO_NON_EMPTYf, 2706 NULL, 0 }, 2707 { 0, 0x00000100, /* PIPE3_EFPMOD_TO_CMIC_INTR */ 2708 SOC_BLK_EPIPE, 3, EGR_INTR_ENABLE_2r, INVALIDr, SER_FIFO_NON_EMPTYf, 2709 NULL, 0 }, 2710 { 0, 0x00000200, /* PIPE4_EFPMOD_TO_CMIC_INTR */ 2711 SOC_BLK_EPIPE, 4, EGR_INTR_ENABLE_2r, INVALIDr, SER_FIFO_NON_EMPTYf, 2712 NULL, 0 }, 2713 { 0, 0x00000400, /* PIPE5_EFPMOD_TO_CMIC_INTR */ 2714 SOC_BLK_EPIPE, 5, EGR_INTR_ENABLE_2r, INVALIDr, SER_FIFO_NON_EMPTYf, 2715 NULL, 0 }, 2716 { 0, 0x00000800, /* PIPE6_EFPMOD_TO_CMIC_INTR */ 2717 SOC_BLK_EPIPE, 6, EGR_INTR_ENABLE_2r, INVALIDr, SER_FIFO_NON_EMPTYf, 2718 NULL, 0 }, 2719 { 0, 0x00001000, /* PIPE7_EFPMOD_TO_CMIC_INTR */ 2720 SOC_BLK_EPIPE, 7, EGR_INTR_ENABLE_2r, INVALIDr, SER_FIFO_NON_EMPTYf, 2721 NULL, 0 }, 2722 { 0, 0x00002000, /* PIPE0_EPOST_TO_CMIC_INTR */ 2723 SOC_BLK_EPIPE, 0, EGR_INTR_ENABLEr, INVALIDr, SER_FIFO_NON_EMPTYf, 2724 NULL, 0 }, 2725 { 0, 0x00004000, /* PIPE1_EPOST_TO_CMIC_INTR */ 2726 SOC_BLK_EPIPE, 1, EGR_INTR_ENABLEr, INVALIDr, SER_FIFO_NON_EMPTYf, 2727 NULL, 0 }, 2728 { 0, 0x00008000, /* PIPE2_EPOST_TO_CMIC_INTR */ 2729 SOC_BLK_EPIPE, 2, EGR_INTR_ENABLEr, INVALIDr, SER_FIFO_NON_EMPTYf, 2730 NULL, 0 }, 2731 { 0, 0x00010000, /* PIPE3_EPOST_TO_CMIC_INTR */ 2732 SOC_BLK_EPIPE, 3, EGR_INTR_ENABLEr, INVALIDr, SER_FIFO_NON_EMPTYf, 2733 NULL, 0 }, 2734 { 0, 0x00020000, /* PIPE4_EPOST_TO_CMIC_INTR */ 2735 SOC_BLK_EPIPE, 4, EGR_INTR_ENABLEr, INVALIDr, SER_FIFO_NON_EMPTYf, 2736 NULL, 0 }, 2737 { 0, 0x00040000, /* PIPE5_EPOST_TO_CMIC_INTR */ 2738 SOC_BLK_EPIPE, 5, EGR_INTR_ENABLEr, INVALIDr, SER_FIFO_NON_EMPTYf, 2739 NULL, 0 }, 2740 { 0, 0x00080000, /* PIPE6_EPOST_TO_CMIC_INTR */ 2741 SOC_BLK_EPIPE, 6, EGR_INTR_ENABLEr, INVALIDr, SER_FIFO_NON_EMPTYf, 2742 NULL, 0 }, 2743 { 0, 0x00100000, /* PIPE7_EPOST_TO_CMIC_INTR */ 2744 SOC_BLK_EPIPE, 7, EGR_INTR_ENABLEr, INVALIDr, SER_FIFO_NON_EMPTYf, 2745 NULL, 0 }, 2746 #if 0 2747 { 1, 0x00000001, /* PIPE0_IARB_TO_CMIC_INTR */ 2748 SOC_BLK_EPIPE, 0, IP0_INTR_ENABLEr, IP0_INTR_STATUSr, INVALIDf, 2749 NULL, 0 }, 2750 { 1, 0x00000002, /* PIPE1_IARB_TO_CMIC_INTR */ 2751 SOC_BLK_EPIPE, 1, IP0_INTR_ENABLEr, IP0_INTR_STATUSr, INVALIDf, 2752 NULL, 0 }, 2753 { 1, 0x00000004, /* PIPE2_IARB_TO_CMIC_INTR */ 2754 SOC_BLK_EPIPE, 2, IP0_INTR_ENABLEr, IP0_INTR_STATUSr, INVALIDf, 2755 NULL, 0 }, 2756 { 1, 0x00000008, /* PIPE3_IARB_TO_CMIC_INTR */ 2757 SOC_BLK_EPIPE, 3, IP0_INTR_ENABLEr, IP0_INTR_STATUSr, INVALIDf, 2758 NULL, 0 }, 2759 { 1, 0x00000010, /* PIPE4_IARB_TO_CMIC_INTR */ 2760 SOC_BLK_EPIPE, 4, IP0_INTR_ENABLEr, IP0_INTR_STATUSr, INVALIDf, 2761 NULL, 0 }, 2762 { 1, 0x00000020, /* PIPE5_IARB_TO_CMIC_INTR */ 2763 SOC_BLK_EPIPE, 5, IP0_INTR_ENABLEr, IP0_INTR_STATUSr, INVALIDf, 2764 NULL, 0 }, 2765 { 1, 0x00000040, /* PIPE6_IARB_TO_CMIC_INTR */ 2766 SOC_BLK_EPIPE, 6, IP0_INTR_ENABLEr, IP0_INTR_STATUSr, INVALIDf, 2767 NULL, 0 }, 2768 { 1, 0x00000080, /* PIPE7_IARB_TO_CMIC_INTR */ 2769 SOC_BLK_EPIPE, 7, IP0_INTR_ENABLEr, IP0_INTR_STATUSr, INVALIDf, 2770 NULL, 0 }, 2771 #endif 2772 { 1, 0x00010000, /* PIPE0_IP_TO_CMIC_PERR_INTR */ 2773 SOC_BLK_IPIPE, 0, INVALIDr, INVALIDr, INVALIDf, 2774 NULL, 0 }, 2775 { 1, 0x00020000, /* PIPE1_IP_TO_CMIC_PERR_INTR */ 2776 SOC_BLK_IPIPE, 1, INVALIDr, INVALIDr, INVALIDf, 2777 NULL, 0 }, 2778 { 1, 0x00040000, /* PIPE2_IP_TO_CMIC_PERR_INTR */ 2779 SOC_BLK_IPIPE, 2, INVALIDr, INVALIDr, INVALIDf, 2780 NULL, 0 }, 2781 { 1, 0x00080000, /* PIPE3_IP_TO_CMIC_PERR_INTR */ 2782 SOC_BLK_IPIPE, 3, INVALIDr, INVALIDr, INVALIDf, 2783 NULL, 0 }, 2784 { 1, 0x00100000, /* PIPE4_IP_TO_CMIC_PERR_INTR */ 2785 SOC_BLK_IPIPE, 4, INVALIDr, INVALIDr, INVALIDf, 2786 NULL, 0 }, 2787 { 1, 0x00200000, /* PIPE5_IP_TO_CMIC_PERR_INTR */ 2788 SOC_BLK_IPIPE, 5, INVALIDr, INVALIDr, INVALIDf, 2789 NULL, 0 }, 2790 { 1, 0x00400000, /* PIPE6_IP_TO_CMIC_PERR_INTR */ 2791 SOC_BLK_IPIPE, 6, INVALIDr, INVALIDr, INVALIDf, 2792 NULL, 0 }, 2793 { 1, 0x00800000, /* PIPE7_IP_TO_CMIC_PERR_INTR */ 2794 SOC_BLK_IPIPE, 7, INVALIDr, INVALIDr, INVALIDf, 2795 NULL, 0 }, 2796 { 1, 0x01000000, /* PIPE0_IPOST_TO_CMIC_INTR */ 2797 SOC_BLK_IPIPE, 0, IPOST_INTR_ENABLEr, IPOST_INTR_STATUSr, INVALIDf, 2798 _soc_th3_ipost_ser_info, 0 }, 2799 { 1, 0x02000000, /* PIPE0_IPOST_TO_CMIC_INTR */ 2800 SOC_BLK_IPIPE, 1, IPOST_INTR_ENABLEr, IPOST_INTR_STATUSr, INVALIDf, 2801 _soc_th3_ipost_ser_info, 0 }, 2802 { 1, 0x04000000, /* PIPE0_IPOST_TO_CMIC_INTR */ 2803 SOC_BLK_IPIPE, 2, IPOST_INTR_ENABLEr, IPOST_INTR_STATUSr, INVALIDf, 2804 _soc_th3_ipost_ser_info, 0 }, 2805 { 1, 0x08000000, /* PIPE0_IPOST_TO_CMIC_INTR */ 2806 SOC_BLK_IPIPE, 3, IPOST_INTR_ENABLEr, IPOST_INTR_STATUSr, INVALIDf, 2807 _soc_th3_ipost_ser_info, 0 }, 2808 { 1, 0x10000000, /* PIPE0_IPOST_TO_CMIC_INTR */ 2809 SOC_BLK_IPIPE, 4, IPOST_INTR_ENABLEr, IPOST_INTR_STATUSr, INVALIDf, 2810 _soc_th3_ipost_ser_info, 0 }, 2811 { 1, 0x20000000, /* PIPE0_IPOST_TO_CMIC_INTR */ 2812 SOC_BLK_IPIPE, 5, IPOST_INTR_ENABLEr, IPOST_INTR_STATUSr, INVALIDf, 2813 _soc_th3_ipost_ser_info, 0 }, 2814 { 1, 0x40000000, /* PIPE0_IPOST_TO_CMIC_INTR */ 2815 SOC_BLK_IPIPE, 6, IPOST_INTR_ENABLEr, IPOST_INTR_STATUSr, INVALIDf, 2816 _soc_th3_ipost_ser_info, 0 }, 2817 { 1, 0x80000000, /* PIPE0_IPOST_TO_CMIC_INTR */ 2818 SOC_BLK_IPIPE, 7, IPOST_INTR_ENABLEr, IPOST_INTR_STATUSr, INVALIDf, 2819 _soc_th3_ipost_ser_info, 0 }, 2820 { 2, 0x00000001, /* PM0_INTR */ 2821 SOC_BLK_CDPORT, 0, CDPORT_INTR_ENABLEr, CDPORT_INTR_STATUSr, INVALIDf, 2822 _soc_th3_pm_cdp_ser_info, 0 }, 2823 { 2, 0x00000002, /* PM1_INTR */ 2824 SOC_BLK_CDPORT, 0, CDPORT_INTR_ENABLEr, CDPORT_INTR_STATUSr, INVALIDf, 2825 _soc_th3_pm_cdp_ser_info, 1 }, 2826 { 2, 0x00000004, /* PM2_INTR */ 2827 SOC_BLK_CDPORT, 0, CDPORT_INTR_ENABLEr, CDPORT_INTR_STATUSr, INVALIDf, 2828 _soc_th3_pm_cdp_ser_info, 2 }, 2829 { 2, 0x00000008, /* PM3_INTR */ 2830 SOC_BLK_CDPORT, 0, CDPORT_INTR_ENABLEr, CDPORT_INTR_STATUSr, INVALIDf, 2831 _soc_th3_pm_cdp_ser_info, 3 }, 2832 { 2, 0x00000010, /* PM4_INTR */ 2833 SOC_BLK_CDPORT, 0, CDPORT_INTR_ENABLEr, CDPORT_INTR_STATUSr, INVALIDf, 2834 _soc_th3_pm_cdp_ser_info, 4 }, 2835 { 2, 0x00000020, /* PM5_INTR */ 2836 SOC_BLK_CDPORT, 0, CDPORT_INTR_ENABLEr, CDPORT_INTR_STATUSr, INVALIDf, 2837 _soc_th3_pm_cdp_ser_info, 5 }, 2838 { 2, 0x00000040, /* PM6_INTR */ 2839 SOC_BLK_CDPORT, 0, CDPORT_INTR_ENABLEr, CDPORT_INTR_STATUSr, INVALIDf, 2840 _soc_th3_pm_cdp_ser_info, 6 }, 2841 { 2, 0x00000080, /* PM7_INTR */ 2842 SOC_BLK_CDPORT, 0, CDPORT_INTR_ENABLEr, CDPORT_INTR_STATUSr, INVALIDf, 2843 _soc_th3_pm_cdp_ser_info, 7 }, 2844 { 2, 0x00000100, /* PM8_INTR */ 2845 SOC_BLK_CDPORT, 1, CDPORT_INTR_ENABLEr, CDPORT_INTR_STATUSr, INVALIDf, 2846 _soc_th3_pm_cdp_ser_info, 8 }, 2847 { 2, 0x00000200, /* PM9_INTR */ 2848 SOC_BLK_CDPORT, 1, CDPORT_INTR_ENABLEr, CDPORT_INTR_STATUSr, INVALIDf, 2849 _soc_th3_pm_cdp_ser_info, 9 }, 2850 { 2, 0x00000400, /* PM10_INTR */ 2851 SOC_BLK_CDPORT, 1, CDPORT_INTR_ENABLEr, CDPORT_INTR_STATUSr, INVALIDf, 2852 _soc_th3_pm_cdp_ser_info, 10 }, 2853 { 2, 0x00000800, /* PM11_INTR */ 2854 SOC_BLK_CDPORT, 1, CDPORT_INTR_ENABLEr, CDPORT_INTR_STATUSr, INVALIDf, 2855 _soc_th3_pm_cdp_ser_info, 11 }, 2856 { 2, 0x00001000, /* PM12_INTR */ 2857 SOC_BLK_CDPORT, 1, CDPORT_INTR_ENABLEr, CDPORT_INTR_STATUSr, INVALIDf, 2858 _soc_th3_pm_cdp_ser_info, 12 }, 2859 { 2, 0x00002000, /* PM13_INTR */ 2860 SOC_BLK_CDPORT, 1, CDPORT_INTR_ENABLEr, CDPORT_INTR_STATUSr, INVALIDf, 2861 _soc_th3_pm_cdp_ser_info, 13 }, 2862 { 2, 0x00004000, /* PM14_INTR */ 2863 SOC_BLK_CDPORT, 1, CDPORT_INTR_ENABLEr, CDPORT_INTR_STATUSr, INVALIDf, 2864 _soc_th3_pm_cdp_ser_info, 14 }, 2865 { 2, 0x00008000, /* PM15_INTR */ 2866 SOC_BLK_CDPORT, 1, CDPORT_INTR_ENABLEr, CDPORT_INTR_STATUSr, INVALIDf, 2867 _soc_th3_pm_cdp_ser_info, 15 }, 2868 { 2, 0x00010000, /* PM16_INTR */ 2869 SOC_BLK_CDPORT, 2, CDPORT_INTR_ENABLEr, CDPORT_INTR_STATUSr, INVALIDf, 2870 _soc_th3_pm_cdp_ser_info, 16 }, 2871 { 2, 0x00020000, /* PM17_INTR */ 2872 SOC_BLK_CDPORT, 2, CDPORT_INTR_ENABLEr, CDPORT_INTR_STATUSr, INVALIDf, 2873 _soc_th3_pm_cdp_ser_info, 17 }, 2874 { 2, 0x00040000, /* PM18_INTR */ 2875 SOC_BLK_CDPORT, 2, CDPORT_INTR_ENABLEr, CDPORT_INTR_STATUSr, INVALIDf, 2876 _soc_th3_pm_cdp_ser_info, 18 }, 2877 { 2, 0x00080000, /* PM19_INTR */ 2878 SOC_BLK_CDPORT, 2, CDPORT_INTR_ENABLEr, CDPORT_INTR_STATUSr, INVALIDf, 2879 _soc_th3_pm_cdp_ser_info, 19 }, 2880 { 2, 0x00100000, /* PM20_INTR */ 2881 SOC_BLK_CDPORT, 2, CDPORT_INTR_ENABLEr, CDPORT_INTR_STATUSr, INVALIDf, 2882 _soc_th3_pm_cdp_ser_info, 20 }, 2883 { 2, 0x00200000, /* PM21_INTR */ 2884 SOC_BLK_CDPORT, 2, CDPORT_INTR_ENABLEr, CDPORT_INTR_STATUSr, INVALIDf, 2885 _soc_th3_pm_cdp_ser_info, 21 }, 2886 { 2, 0x00400000, /* PM22_INTR */ 2887 SOC_BLK_CDPORT, 2, CDPORT_INTR_ENABLEr, CDPORT_INTR_STATUSr, INVALIDf, 2888 _soc_th3_pm_cdp_ser_info, 22 }, 2889 { 2, 0x00800000, /* PM23_INTR */ 2890 SOC_BLK_CDPORT, 2, CDPORT_INTR_ENABLEr, CDPORT_INTR_STATUSr, INVALIDf, 2891 _soc_th3_pm_cdp_ser_info, 23 }, 2892 { 2, 0x01000000, /* PM24_INTR */ 2893 SOC_BLK_CDPORT, 3, CDPORT_INTR_ENABLEr, CDPORT_INTR_STATUSr, INVALIDf, 2894 _soc_th3_pm_cdp_ser_info, 24 }, 2895 { 2, 0x02000000, /* PM25_INTR */ 2896 SOC_BLK_CDPORT, 3, CDPORT_INTR_ENABLEr, CDPORT_INTR_STATUSr, INVALIDf, 2897 _soc_th3_pm_cdp_ser_info, 25 }, 2898 { 2, 0x04000000, /* PM26_INTR */ 2899 SOC_BLK_CDPORT, 3, CDPORT_INTR_ENABLEr, CDPORT_INTR_STATUSr, INVALIDf, 2900 _soc_th3_pm_cdp_ser_info, 26 }, 2901 { 2, 0x08000000, /* PM27_INTR */ 2902 SOC_BLK_CDPORT, 3, CDPORT_INTR_ENABLEr, CDPORT_INTR_STATUSr, INVALIDf, 2903 _soc_th3_pm_cdp_ser_info, 27 }, 2904 { 2, 0x10000000, /* PM28_INTR */ 2905 SOC_BLK_CDPORT, 3, CDPORT_INTR_ENABLEr, CDPORT_INTR_STATUSr, INVALIDf, 2906 _soc_th3_pm_cdp_ser_info, 28 }, 2907 { 2, 0x20000000, /* PM29_INTR */ 2908 SOC_BLK_CDPORT, 3, CDPORT_INTR_ENABLEr, CDPORT_INTR_STATUSr, INVALIDf, 2909 _soc_th3_pm_cdp_ser_info, 29 }, 2910 { 2, 0x40000000, /* PM30_INTR */ 2911 SOC_BLK_CDPORT, 3, CDPORT_INTR_ENABLEr, CDPORT_INTR_STATUSr, INVALIDf, 2912 _soc_th3_pm_cdp_ser_info, 30 }, 2913 { 2, 0x80000000, /* PM31_INTR */ 2914 SOC_BLK_CDPORT, 3, CDPORT_INTR_ENABLEr, CDPORT_INTR_STATUSr, INVALIDf, 2915 _soc_th3_pm_cdp_ser_info, 31 }, 2916 { 3, 0x00000001, /* PIPE0_EDB_TO_CMIC_PERR_INTR */ 2917 SOC_BLK_XLPORT, 0, XLPORT_INTR_ENABLEr, XLPORT_INTR_STATUSr, INVALIDf, 2918 _soc_th3_pm_xlp_ser_info, 0 }, 2919 { 3, 0x00000002, /* PIPE0_EDB_TO_CMIC_PERR_INTR */ 2920 SOC_BLK_EPIPE, 0, EDB_INTR_ENABLEr, EDB_INTR_STATUSr, SER_FIFO_NON_EMPTYf, 2921 _soc_th3_edb_ser_info, 0 }, 2922 { 3, 0x00000004, /* PIPE1_EDB_TO_CMIC_PERR_INTR */ 2923 SOC_BLK_EPIPE, 1, EDB_INTR_ENABLEr, EDB_INTR_STATUSr, SER_FIFO_NON_EMPTYf, 2924 _soc_th3_edb_ser_info, 0 }, 2925 { 3, 0x00000008, /* PIPE2_EDB_TO_CMIC_PERR_INTR */ 2926 SOC_BLK_EPIPE, 2, EDB_INTR_ENABLEr, EDB_INTR_STATUSr, SER_FIFO_NON_EMPTYf, 2927 _soc_th3_edb_ser_info, 0 }, 2928 { 3, 0x00000010, /* PIPE3_EDB_TO_CMIC_PERR_INTR */ 2929 SOC_BLK_EPIPE, 3, EDB_INTR_ENABLEr, EDB_INTR_STATUSr, SER_FIFO_NON_EMPTYf, 2930 _soc_th3_edb_ser_info, 0 }, 2931 { 3, 0x00000020, /* PIPE4_EDB_TO_CMIC_PERR_INTR */ 2932 SOC_BLK_EPIPE, 4, EDB_INTR_ENABLEr, EDB_INTR_STATUSr, SER_FIFO_NON_EMPTYf, 2933 _soc_th3_edb_ser_info, 0 }, 2934 { 3, 0x00000040, /* PIPE5_EDB_TO_CMIC_PERR_INTR */ 2935 SOC_BLK_EPIPE, 5, EDB_INTR_ENABLEr, EDB_INTR_STATUSr, SER_FIFO_NON_EMPTYf, 2936 _soc_th3_edb_ser_info, 0 }, 2937 { 3, 0x00000080, /* PIPE6_EDB_TO_CMIC_PERR_INTR */ 2938 SOC_BLK_EPIPE, 6, EDB_INTR_ENABLEr, EDB_INTR_STATUSr, SER_FIFO_NON_EMPTYf, 2939 _soc_th3_edb_ser_info, 0 }, 2940 { 3, 0x00000100, /* PIPE7_EDB_TO_CMIC_PERR_INTR */ 2941 SOC_BLK_EPIPE, 7, EDB_INTR_ENABLEr, EDB_INTR_STATUSr, SER_FIFO_NON_EMPTYf, 2942 _soc_th3_edb_ser_info, 0 }, 2943 { 3, 0x00000200, /* PIPE0_IDB_TO_CMIC_PERR_INTR */ 2944 SOC_BLK_IPIPE, 0, IDB_INTR_ENABLEr, IDB_INTR_STATUSr, INVALIDf, 2945 _soc_th3_idb_ser_info, 0 }, 2946 { 3, 0x00000400, /* PIPE1_IDB_TO_CMIC_PERR_INTR */ 2947 SOC_BLK_IPIPE, 1, IDB_INTR_ENABLEr, IDB_INTR_STATUSr, INVALIDf, 2948 _soc_th3_idb_ser_info, 0 }, 2949 { 3, 0x00000800, /* PIPE2_IDB_TO_CMIC_PERR_INTR */ 2950 SOC_BLK_IPIPE, 2, IDB_INTR_ENABLEr, IDB_INTR_STATUSr, INVALIDf, 2951 _soc_th3_idb_ser_info, 0 }, 2952 { 3, 0x00001000, /* PIPE3_IDB_TO_CMIC_PERR_INTR */ 2953 SOC_BLK_IPIPE, 3, IDB_INTR_ENABLEr, IDB_INTR_STATUSr, INVALIDf, 2954 _soc_th3_idb_ser_info, 0 }, 2955 { 3, 0x00002000, /* PIPE4_IDB_TO_CMIC_PERR_INTR */ 2956 SOC_BLK_IPIPE, 4, IDB_INTR_ENABLEr, IDB_INTR_STATUSr, INVALIDf, 2957 _soc_th3_idb_ser_info, 0 }, 2958 { 3, 0x00004000, /* PIPE5_IDB_TO_CMIC_PERR_INTR */ 2959 SOC_BLK_IPIPE, 5, IDB_INTR_ENABLEr, IDB_INTR_STATUSr, INVALIDf, 2960 _soc_th3_idb_ser_info, 0 }, 2961 { 3, 0x00008000, /* PIPE6_IDB_TO_CMIC_PERR_INTR */ 2962 SOC_BLK_IPIPE, 6, IDB_INTR_ENABLEr, IDB_INTR_STATUSr, INVALIDf, 2963 _soc_th3_idb_ser_info, 0 }, 2964 { 3, 0x00010000, /* PIPE7_IDB_TO_CMIC_PERR_INTR */ 2965 SOC_BLK_IPIPE, 7, IDB_INTR_ENABLEr, IDB_INTR_STATUSr, INVALIDf, 2966 _soc_th3_idb_ser_info, 0 }, 2967 2968 { 0 } /* table terminator */ 2969 }; 2970 2971 #if 0 2972 static _soc_tcam_ser_en_info_t _soc_th3_tcam_wrapper_table[12] = { 2973 { MY_STATION_TCAMm, MY_STATION_TCAM_CAM_SERCTRLr, PARITY_ENf, TCAM_PARITY_MASKf}, 2974 { L2_USER_ENTRYm, L2_USER_ENTRY_CAM_SERCTRLr, PARITY_ENf, TCAM_PARITY_MASKf}, 2975 { FP_UDF_TCAMm, UDF_CAM_SERCTRLr, PARITY_ENf, TCAM_PARITY_MASKf}, 2976 { VFP_TCAMm, VFP_CAM_SER_CONTROLr, PARITY_ENf, TCAM_PARITY_MASKf}, 2977 { EXACT_MATCH_LOGICAL_TABLE_SELECTm, EXACT_MATCH_LOGICAL_TABLE_SELECT_CAM_DBGCTRLr, PARITY_ENf, TCAM_PARITY_MASKf}, 2978 { CPU_COS_MAPm, CPU_COS_CAM_SERCTRLr, PARITY_ENf, TCAM_PARITY_MASKf}, 2979 { L3_DEFIP_TCAM_LEVEL1m, ILPM_SER_CONTROLr, L3_DEFIP_TCAM_PARITY_ENf, TCAM_PARITY_MASKf}, 2980 { L3_DEFIP_PAIR_LEVEL1m, ILPM_SER_CONTROLr, L3_DEFIP_TCAM_PARITY_ENf, TCAM_PARITY_MASK_UPRf}, 2981 { IFP_TCAMm, IFP_TCAM_CAM_CONTROLr, PARITY_ENf, TCAM_PARITY_MASKf}, 2982 { EFP_TCAMm, EFP_RAM_CONTROL_2_64r, EFP_CAM_PARITY_ENf, TCAM_PARITY_MASKf}, 2983 { IFP_LOGICAL_TABLE_SELECTm, IFP_LOGICAL_TABLE_SELECT_CAM_DBGCTRLr, PARITY_ENf, TCAM_PARITY_MASKf}, 2984 { INVALIDm}, 2985 }; 2986 #endif 2987 2988 static const 2989 _soc_th_ser_mmu_intr_info_t th3_mmu_intr_info[] = { 2990 { MEM_PAR_ERR_INT_STATf, _SOC_MMU_BASE_INDEX_GLB, 0}, 2991 { ITMCFG1_INT_STATf, _SOC_MMU_BASE_INDEX_ITM1, 1 }, 2992 { ITMCFG0_INT_STATf, _SOC_MMU_BASE_INDEX_ITM0, 1 }, 2993 { EBCFG7_INT_STATf, _SOC_MMU_BASE_INDEX_EB7, 2 }, 2994 { EBCFG6_INT_STATf, _SOC_MMU_BASE_INDEX_EB6, 2 }, 2995 { EBCFG5_INT_STATf, _SOC_MMU_BASE_INDEX_EB5, 2 }, 2996 { EBCFG4_INT_STATf, _SOC_MMU_BASE_INDEX_EB4, 2 }, 2997 { EBCFG3_INT_STATf, _SOC_MMU_BASE_INDEX_EB3, 2 }, 2998 { EBCFG2_INT_STATf, _SOC_MMU_BASE_INDEX_EB2, 2 }, 2999 { EBCFG1_INT_STATf, _SOC_MMU_BASE_INDEX_EB1, 2 }, 3000 { EBCFG0_INT_STATf, _SOC_MMU_BASE_INDEX_EB0, 2 }, 3001 { INVALIDf, -1, -1 } 3002 }; 3003 3004 static soc_mem_t _soc_th3_skip_populating[] = { 3005 /* Shared MMU_WRED_ENABLE_ECCP_MEM.MMU_WRED_DROP_CURVE_PROFILE_ECCP_EN */ 3006 MMU_WRED_DROP_CURVE_PROFILE_0_0m, 3007 MMU_WRED_DROP_CURVE_PROFILE_0_1m, 3008 MMU_WRED_DROP_CURVE_PROFILE_0_2m, 3009 MMU_WRED_DROP_CURVE_PROFILE_0_3m, 3010 MMU_WRED_DROP_CURVE_PROFILE_0_4m, 3011 MMU_WRED_DROP_CURVE_PROFILE_0_5m, 3012 MMU_WRED_DROP_CURVE_PROFILE_1_0m, 3013 MMU_WRED_DROP_CURVE_PROFILE_1_1m, 3014 MMU_WRED_DROP_CURVE_PROFILE_1_2m, 3015 MMU_WRED_DROP_CURVE_PROFILE_1_3m, 3016 MMU_WRED_DROP_CURVE_PROFILE_1_4m, 3017 MMU_WRED_DROP_CURVE_PROFILE_1_5m, 3018 MMU_WRED_DROP_CURVE_PROFILE_2_0m, 3019 MMU_WRED_DROP_CURVE_PROFILE_2_1m, 3020 MMU_WRED_DROP_CURVE_PROFILE_2_2m, 3021 MMU_WRED_DROP_CURVE_PROFILE_2_3m, 3022 MMU_WRED_DROP_CURVE_PROFILE_2_4m, 3023 MMU_WRED_DROP_CURVE_PROFILE_2_5m, 3024 MMU_WRED_DROP_CURVE_PROFILE_3_0m, 3025 MMU_WRED_DROP_CURVE_PROFILE_3_1m, 3026 MMU_WRED_DROP_CURVE_PROFILE_3_2m, 3027 MMU_WRED_DROP_CURVE_PROFILE_3_3m, 3028 MMU_WRED_DROP_CURVE_PROFILE_3_4m, 3029 MMU_WRED_DROP_CURVE_PROFILE_3_5m, 3030 MMU_WRED_DROP_CURVE_PROFILE_4_0m, 3031 MMU_WRED_DROP_CURVE_PROFILE_4_1m, 3032 MMU_WRED_DROP_CURVE_PROFILE_4_2m, 3033 MMU_WRED_DROP_CURVE_PROFILE_4_3m, 3034 MMU_WRED_DROP_CURVE_PROFILE_4_4m, 3035 MMU_WRED_DROP_CURVE_PROFILE_4_5m, 3036 MMU_WRED_DROP_CURVE_PROFILE_5_0m, 3037 MMU_WRED_DROP_CURVE_PROFILE_5_1m, 3038 MMU_WRED_DROP_CURVE_PROFILE_5_2m, 3039 MMU_WRED_DROP_CURVE_PROFILE_5_3m, 3040 MMU_WRED_DROP_CURVE_PROFILE_5_4m, 3041 MMU_WRED_DROP_CURVE_PROFILE_5_5m, 3042 MMU_WRED_DROP_CURVE_PROFILE_6_0m, 3043 MMU_WRED_DROP_CURVE_PROFILE_6_1m, 3044 MMU_WRED_DROP_CURVE_PROFILE_6_2m, 3045 MMU_WRED_DROP_CURVE_PROFILE_6_3m, 3046 MMU_WRED_DROP_CURVE_PROFILE_6_4m, 3047 MMU_WRED_DROP_CURVE_PROFILE_6_5m, 3048 MMU_WRED_DROP_CURVE_PROFILE_7_0m, 3049 MMU_WRED_DROP_CURVE_PROFILE_7_1m, 3050 MMU_WRED_DROP_CURVE_PROFILE_7_2m, 3051 MMU_WRED_DROP_CURVE_PROFILE_7_3m, 3052 MMU_WRED_DROP_CURVE_PROFILE_7_4m, 3053 MMU_WRED_DROP_CURVE_PROFILE_7_5m, 3054 MMU_WRED_DROP_CURVE_PROFILE_8_0m, 3055 MMU_WRED_DROP_CURVE_PROFILE_8_1m, 3056 MMU_WRED_DROP_CURVE_PROFILE_8_2m, 3057 MMU_WRED_DROP_CURVE_PROFILE_8_3m, 3058 MMU_WRED_DROP_CURVE_PROFILE_8_4m, 3059 MMU_WRED_DROP_CURVE_PROFILE_8_5m, 3060 INVALIDm 3061 }; 3062 3063 static uint32 _soc_th3_ip_pipe_fifo_bmask[SOC_MAX_NUM_DEVICES][8]; 3064 STATIC soc_error_t _soc_th3_ser_tcam_wrapper_found(soc_mem_t mem); 3065 STATIC soc_error_t 3066 _soc_th3_ser_tcam_control_reg_get(soc_mem_t mem, soc_reg_t *ser_control_reg, 3067 soc_field_t *ser_enable_field); 3068 STATIC soc_error_t _soc_th3_tcam_wrapper_enable(int unit, int enable); 3069 int soc_th3_tcam_engine_enable(int unit, int enable); 3070 3071 #endif 3072 3073 3074 #ifdef BCM_TOMAHAWKPLUS_SUPPORT 3075 static const 3076 _soc_th_ser_route_block_t _soc_thplus_ser_route_blocks[] = { 3077 { 3, 0x00000010, /* MMU_TO_CMIC_MEMFAIL_INTR */ 3078 SOC_BLK_MMU, -1, INVALIDr, INVALIDr, INVALIDf, 3079 _soc_th_mmu_top_ser_info, 0 }, 3080 /* xsm: not using MMU_GLB or MMU_XPE or MMU_SC is on purpose */ 3081 { 3, 0x00000020, /* PIPE0_EP2_TO_CMIC_PERR_INTR */ 3082 SOC_BLK_EPIPE, 0, EGR_INTR_ENABLEr, INVALIDr, SER_FIFO_NON_EMPTYf, 3083 NULL, 0 }, 3084 { 3, 0x00000040, /* PIPE1_EP2_TO_CMIC_PERR_INTR */ 3085 SOC_BLK_EPIPE, 1, EGR_INTR_ENABLEr, INVALIDr, SER_FIFO_NON_EMPTYf, 3086 NULL, 0 }, 3087 { 3, 0x00000080, /* PIPE2_EP2_TO_CMIC_PERR_INTR */ 3088 SOC_BLK_EPIPE, 2, EGR_INTR_ENABLEr, INVALIDr, SER_FIFO_NON_EMPTYf, 3089 NULL, 0 }, 3090 { 3, 0x00000100, /* PIPE3_EP2_TO_CMIC_PERR_INTR */ 3091 SOC_BLK_EPIPE, 3, EGR_INTR_ENABLEr, INVALIDr, SER_FIFO_NON_EMPTYf, 3092 NULL, 0 }, 3093 { 3, _SOC_TH_IPIPE0_IP0_INTR, /* PIPE0_IP0_TO_CMIC_PERR_INTR */ 3094 /* Note: This is an exception for being legacy style in IP */ 3095 SOC_BLK_IPIPE, 0, IP0_INTR_ENABLEr, IP0_INTR_STATUSr, INVALIDf, 3096 _soc_th_idb_ser_info, 0 }, 3097 { 3, _SOC_TH_IPIPE1_IP0_INTR, /* PIPE1_IP0_TO_CMIC_PERR_INTR */ 3098 /* Note: This is an exception for being legacy style in IP */ 3099 SOC_BLK_IPIPE, 1, IP0_INTR_ENABLEr, IP0_INTR_STATUSr, INVALIDf, 3100 _soc_th_idb_ser_info, 0 }, 3101 { 3, _SOC_TH_IPIPE2_IP0_INTR, /* PIPE2_IP0_TO_CMIC_PERR_INTR */ 3102 /* Note: This is an exception for being legacy style in IP */ 3103 SOC_BLK_IPIPE, 2, IP0_INTR_ENABLEr, IP0_INTR_STATUSr, INVALIDf, 3104 _soc_th_idb_ser_info, 0 }, 3105 { 3, _SOC_TH_IPIPE3_IP0_INTR, /* PIPE3_IP0_TO_CMIC_PERR_INTR */ 3106 /* Note: This is an exception for being legacy style in IP */ 3107 SOC_BLK_IPIPE, 3, IP0_INTR_ENABLEr, IP0_INTR_STATUSr, INVALIDf, 3108 _soc_th_idb_ser_info, 0 }, 3109 { 3, 0x00002000, /* PIPE0_IP5_TO_CMIC_PERR_INTR */ 3110 SOC_BLK_IPIPE, 0, INVALIDr, INVALIDr, INVALIDf, 3111 NULL, 0 }, 3112 { 3, 0x00004000, /* PIPE1_IP5_TO_CMIC_PERR_INTR */ 3113 SOC_BLK_IPIPE, 1, INVALIDr, INVALIDr, INVALIDf, 3114 NULL, 0 }, 3115 { 3, 0x00008000, /* PIPE2_IP5_TO_CMIC_PERR_INTR */ 3116 SOC_BLK_IPIPE, 2, INVALIDr, INVALIDr, INVALIDf, 3117 NULL, 0 }, 3118 { 3, 0x00010000, /* PIPE3_IP5_TO_CMIC_PERR_INTR */ 3119 SOC_BLK_IPIPE, 3, INVALIDr, INVALIDr, INVALIDf, 3120 NULL, 0 }, 3121 { 4, 0x00000001, /* PM0_INTR */ 3122 SOC_BLK_CLPORT, 0, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 3123 _soc_thplus_pm_clp_ser_info, 0 }, 3124 { 4, 0x00000002, /* PM1_INTR */ 3125 SOC_BLK_CLPORT, 0, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 3126 _soc_thplus_pm_clp_ser_info, 1 }, 3127 { 4, 0x00000004, /* PM2_INTR */ 3128 SOC_BLK_CLPORT, 0, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 3129 _soc_thplus_pm_clp_ser_info, 2 }, 3130 { 4, 0x00000008, /* PM3_INTR */ 3131 SOC_BLK_CLPORT, 0, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 3132 _soc_thplus_pm_clp_ser_info, 3 }, 3133 { 4, 0x00000010, /* PM4_INTR */ 3134 SOC_BLK_CLPORT, 0, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 3135 _soc_thplus_pm_clp_ser_info, 4 }, 3136 { 4, 0x00000020, /* PM5_INTR */ 3137 SOC_BLK_CLPORT, 0, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 3138 _soc_thplus_pm_clp_ser_info, 5 }, 3139 { 4, 0x00000040, /* PM6_INTR */ 3140 SOC_BLK_CLPORT, 0, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 3141 _soc_thplus_pm_clp_ser_info, 6 }, 3142 { 4, 0x00000080, /* PM7_INTR */ 3143 SOC_BLK_CLPORT, 0, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 3144 _soc_thplus_pm_clp_ser_info, 7 }, 3145 { 4, 0x00000100, /* PM8_INTR */ 3146 SOC_BLK_CLPORT, 1, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 3147 _soc_thplus_pm_clp_ser_info, 8 }, 3148 { 4, 0x00000200, /* PM9_INTR */ 3149 SOC_BLK_CLPORT, 1, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 3150 _soc_thplus_pm_clp_ser_info, 9 }, 3151 { 4, 0x00000400, /* PM10_INTR */ 3152 SOC_BLK_CLPORT, 1, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 3153 _soc_thplus_pm_clp_ser_info, 10 }, 3154 { 4, 0x00000800, /* PM11_INTR */ 3155 SOC_BLK_CLPORT, 1, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 3156 _soc_thplus_pm_clp_ser_info, 11 }, 3157 { 4, 0x00001000, /* PM12_INTR */ 3158 SOC_BLK_CLPORT, 1, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 3159 _soc_thplus_pm_clp_ser_info, 12 }, 3160 { 4, 0x00002000, /* PM13_INTR */ 3161 SOC_BLK_CLPORT, 1, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 3162 _soc_thplus_pm_clp_ser_info, 13 }, 3163 { 4, 0x00004000, /* PM14_INTR */ 3164 SOC_BLK_CLPORT, 1, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 3165 _soc_thplus_pm_clp_ser_info, 14 }, 3166 { 4, 0x00008000, /* PM15_INTR */ 3167 SOC_BLK_CLPORT, 1, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 3168 _soc_thplus_pm_clp_ser_info, 15 }, 3169 { 4, 0x00010000, /* PM16_INTR */ 3170 SOC_BLK_CLPORT, 2, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 3171 _soc_thplus_pm_clp_ser_info, 16 }, 3172 { 4, 0x00020000, /* PM17_INTR */ 3173 SOC_BLK_CLPORT, 2, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 3174 _soc_thplus_pm_clp_ser_info, 17 }, 3175 { 4, 0x00040000, /* PM18_INTR */ 3176 SOC_BLK_CLPORT, 2, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 3177 _soc_thplus_pm_clp_ser_info, 18 }, 3178 { 4, 0x00080000, /* PM19_INTR */ 3179 SOC_BLK_CLPORT, 2, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 3180 _soc_thplus_pm_clp_ser_info, 19 }, 3181 { 4, 0x00100000, /* PM20_INTR */ 3182 SOC_BLK_CLPORT, 2, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 3183 _soc_thplus_pm_clp_ser_info, 20 }, 3184 { 4, 0x00200000, /* PM21_INTR */ 3185 SOC_BLK_CLPORT, 2, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 3186 _soc_thplus_pm_clp_ser_info, 21 }, 3187 { 4, 0x00400000, /* PM22_INTR */ 3188 SOC_BLK_CLPORT, 2, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 3189 _soc_thplus_pm_clp_ser_info, 22 }, 3190 { 4, 0x00800000, /* PM23_INTR */ 3191 SOC_BLK_CLPORT, 2, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 3192 _soc_thplus_pm_clp_ser_info, 23 }, 3193 { 4, 0x01000000, /* PM24_INTR */ 3194 SOC_BLK_CLPORT, 3, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 3195 _soc_thplus_pm_clp_ser_info, 24 }, 3196 { 4, 0x02000000, /* PM25_INTR */ 3197 SOC_BLK_CLPORT, 3, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 3198 _soc_thplus_pm_clp_ser_info, 25 }, 3199 { 4, 0x04000000, /* PM26_INTR */ 3200 SOC_BLK_CLPORT, 3, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 3201 _soc_thplus_pm_clp_ser_info, 26 }, 3202 { 4, 0x08000000, /* PM27_INTR */ 3203 SOC_BLK_CLPORT, 3, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 3204 _soc_thplus_pm_clp_ser_info, 27 }, 3205 { 4, 0x10000000, /* PM28_INTR */ 3206 SOC_BLK_CLPORT, 3, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 3207 _soc_thplus_pm_clp_ser_info, 28 }, 3208 { 4, 0x20000000, /* PM29_INTR */ 3209 SOC_BLK_CLPORT, 3, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 3210 _soc_thplus_pm_clp_ser_info, 29 }, 3211 { 4, 0x40000000, /* PM30_INTR */ 3212 SOC_BLK_CLPORT, 3, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 3213 _soc_thplus_pm_clp_ser_info, 30 }, 3214 { 4, 0x80000000, /* PM31_INTR */ 3215 SOC_BLK_CLPORT, 3, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 3216 _soc_thplus_pm_clp_ser_info, 31 }, 3217 { 5, 0x00000001, /* PM32_INTR */ 3218 SOC_BLK_XLPORT, 1, XLPORT_INTR_ENABLEr, XLPORT_INTR_STATUSr, INVALIDf, 3219 _soc_th_pm_xlp_ser_info, 0 }, 3220 { 0 } /* table terminator */ 3221 }; 3222 3223 soc_mem_t _soc_thp_skip_populating[] = { 3224 /* Shared MMU_WRED_ENABLE_ECCP_MEM.PROFILE_ECCP_EN */ 3225 MMU_WRED_DROP_CURVE_PROFILE_0m, 3226 MMU_WRED_DROP_CURVE_PROFILE_0_Am, 3227 MMU_WRED_DROP_CURVE_PROFILE_0_Bm, 3228 MMU_WRED_DROP_CURVE_PROFILE_1m, 3229 MMU_WRED_DROP_CURVE_PROFILE_1_Am, 3230 MMU_WRED_DROP_CURVE_PROFILE_1_Bm, 3231 MMU_WRED_DROP_CURVE_PROFILE_2m, 3232 MMU_WRED_DROP_CURVE_PROFILE_2_Am, 3233 MMU_WRED_DROP_CURVE_PROFILE_2_Bm, 3234 MMU_WRED_DROP_CURVE_PROFILE_3m, 3235 MMU_WRED_DROP_CURVE_PROFILE_3_Am, 3236 MMU_WRED_DROP_CURVE_PROFILE_3_Bm, 3237 MMU_WRED_DROP_CURVE_PROFILE_4m, 3238 MMU_WRED_DROP_CURVE_PROFILE_4_Am, 3239 MMU_WRED_DROP_CURVE_PROFILE_4_Bm, 3240 MMU_WRED_DROP_CURVE_PROFILE_5m, 3241 MMU_WRED_DROP_CURVE_PROFILE_5_Am, 3242 MMU_WRED_DROP_CURVE_PROFILE_5_Bm, 3243 MMU_WRED_DROP_CURVE_PROFILE_6m, 3244 MMU_WRED_DROP_CURVE_PROFILE_6_Am, 3245 MMU_WRED_DROP_CURVE_PROFILE_6_Bm, 3246 MMU_WRED_DROP_CURVE_PROFILE_7m, 3247 MMU_WRED_DROP_CURVE_PROFILE_7_Am, 3248 MMU_WRED_DROP_CURVE_PROFILE_7_Bm, 3249 MMU_WRED_DROP_CURVE_PROFILE_8m, 3250 MMU_WRED_DROP_CURVE_PROFILE_8_Am, 3251 MMU_WRED_DROP_CURVE_PROFILE_8_Bm, 3252 3253 /* Shared MMU_SCFG_PARITY_EN.TDM_PARITY_EN */ 3254 TDM_CALENDAR0m, 3255 TDM_CALENDAR1m, 3256 3257 INVALIDm 3258 }; 3259 3260 #endif 3261 3262 STATIC int 3263 _soc_tomahawk_mmu_ser_config(int unit, _soc_th_ser_info_t *info_list, 3264 int enable) 3265 { 3266 int info_index, f, rv; 3267 soc_field_t *fields; 3268 uint32 rval; 3269 _soc_th_ser_info_t *info; 3270 3271 switch(info_list->type) { 3272 case _SOC_PARITY_TYPE_MMU_SER: 3273 /* Interrupt enable */ 3274 fields = info_list->intr_enable_field_list; 3275 SOC_IF_ERROR_RETURN 3276 (soc_reg32_get(unit, info_list->intr_enable_reg, REG_PORT_ANY, 0, 3277 &rval)); 3278 for (f=0 ;; f++) { 3279 if (fields[f] == INVALIDf) { 3280 break; 3281 } 3282 soc_reg_field_set(unit, info_list->intr_enable_reg, &rval, 3283 fields[f], enable ? 1 : 0); 3284 } 3285 SOC_IF_ERROR_RETURN 3286 (soc_reg32_set(unit, info_list->intr_enable_reg, REG_PORT_ANY, 0, 3287 rval)); 3288 /* Loop through each info entry in the list */ 3289 for (info_index = 0; ; info_index++) { 3290 info = &(info_list->info[info_index]); 3291 if (info->type == _SOC_PARITY_TYPE_NONE) { 3292 /* End of table */ 3293 break; 3294 } 3295 rv = _soc_tomahawk_mmu_ser_config(unit, info, enable); 3296 if (SOC_FAILURE(rv)) { 3297 LOG_CLI((BSL_META_U(unit, 3298 "Error configuring %s !!\n"), 3299 info->mem_str)); 3300 return rv; 3301 } 3302 } 3303 break; 3304 case _SOC_PARITY_TYPE_MMU_GLB: 3305 case _SOC_PARITY_TYPE_MMU_XPE: 3306 case _SOC_PARITY_TYPE_MMU_SC: 3307 #ifdef BCM_TOMAHAWK2_SUPPORT 3308 case _SOC_PARITY_TYPE_MMU_SED: 3309 #endif 3310 #ifdef BCM_TOMAHAWK3_SUPPORT 3311 case _SOC_PARITY_TYPE_MMU_ITMCFG: 3312 case _SOC_PARITY_TYPE_MMU_EBCFG: 3313 #endif 3314 /* Parity enable */ 3315 if (info_list->enable_reg != INVALIDr) { 3316 SOC_IF_ERROR_RETURN 3317 (soc_reg32_get(unit, info_list->enable_reg, REG_PORT_ANY, 0, 3318 &rval)); 3319 if (info_list->enable_field_list) { 3320 fields = info_list->enable_field_list; 3321 for (f=0 ;; f++) { 3322 if (fields[f] == INVALIDf) { 3323 break; 3324 } 3325 soc_reg_field_set(unit, info_list->enable_reg, &rval, fields[f], 3326 enable ? 1 : 0); 3327 } 3328 } else if (info_list->enable_reg != INVALIDr) { 3329 soc_reg_field_set(unit, info_list->enable_reg, &rval, 3330 info_list->enable_field, enable ? 1 : 0); 3331 } 3332 SOC_IF_ERROR_RETURN 3333 (soc_reg32_set(unit, info_list->enable_reg, REG_PORT_ANY, 0, rval)); 3334 } 3335 /* Interrupt enable */ 3336 SOC_IF_ERROR_RETURN 3337 (soc_reg32_get(unit, info_list->intr_enable_reg, REG_PORT_ANY, 0, 3338 &rval)); 3339 if (info_list->intr_enable_field_list) { 3340 fields = info_list->intr_enable_field_list; 3341 for (f=0 ;; f++) { 3342 if (fields[f] == INVALIDf) { 3343 break; 3344 } 3345 soc_reg_field_set(unit, info_list->intr_enable_reg, &rval, 3346 fields[f], enable ? 1 : 0); 3347 } 3348 } else if (info_list->intr_enable_reg != INVALIDr) { 3349 soc_reg_field_set(unit, info_list->intr_enable_reg, &rval, 3350 info_list->intr_enable_field, enable ? 1 : 0); 3351 } 3352 SOC_IF_ERROR_RETURN 3353 (soc_reg32_set(unit, info_list->intr_enable_reg, REG_PORT_ANY, 0, 3354 rval)); 3355 break; 3356 default: break; 3357 } 3358 return SOC_E_NONE; 3359 } 3360 3361 STATIC int 3362 _soc_tomahawk_ser_enable_info(int unit, int block_info_idx, int inst, int port, 3363 soc_reg_t group_reg, uint64 *group_rval, 3364 _soc_th_ser_info_t *info_list, 3365 soc_mem_t mem, int enable) 3366 { 3367 _soc_th_ser_info_t *info; 3368 int info_index, rv, rv1; 3369 uint32 rval; 3370 uint32 value = 0; 3371 soc_reg_t reg; 3372 uint64 rval64; 3373 soc_field_t *field; 3374 int i = 0; 3375 int log_port; 3376 #ifdef BCM_TOMAHAWK3_SUPPORT 3377 int is_idb = 0; 3378 int idx = 0; 3379 #endif 3380 rv = SOC_E_NOT_FOUND; 3381 3382 /* Loop through each info entry in the list */ 3383 for (info_index = 0; ; info_index++) { 3384 info = &info_list[info_index]; 3385 if (info->type == _SOC_PARITY_TYPE_NONE) { 3386 /* End of table */ 3387 break; 3388 } 3389 rv = SOC_E_NONE; 3390 3391 if (group_reg != INVALIDr && info->group_reg_enable_field != INVALIDf) { 3392 /* Enable the info entry in the group register */ 3393 #ifdef BCM_TOMAHAWK3_SUPPORT 3394 if (SOC_IS_TOMAHAWK3(unit) && (group_reg == CDPORT_INTR_ENABLEr)) { 3395 value = 0xff; 3396 } else 3397 #endif 3398 #ifdef BCM_TOMAHAWK2_SUPPORT 3399 if (SOC_IS_TOMAHAWK2(unit) && (group_reg == CLPORT_INTR_ENABLEr)) { 3400 value = 0xf; 3401 } else 3402 #endif 3403 { 3404 value = 1; 3405 } 3406 soc_reg64_field32_set(unit, group_reg, group_rval, 3407 info->group_reg_enable_field, enable ? value : 0); 3408 } 3409 /* Handle different parity error reporting style */ 3410 switch (info->type) { 3411 case _SOC_PARITY_TYPE_MMU_SER: 3412 rv1 = _soc_tomahawk_mmu_ser_config(unit, info, enable); 3413 if (SOC_FAILURE(rv1)) { 3414 LOG_CLI((BSL_META_U(unit, 3415 "Error configuring MMU SER !!\n"))); 3416 return rv1; 3417 } 3418 break; 3419 case _SOC_PARITY_TYPE_ECC: 3420 case _SOC_PARITY_TYPE_PARITY: 3421 reg = info->enable_reg; 3422 if (!SOC_REG_IS_VALID(unit, reg)) { 3423 break; 3424 } 3425 #ifdef BCM_TOMAHAWK3_SUPPORT 3426 if (SOC_IS_TOMAHAWK3(unit)) { 3427 (void)_soc_tomahawk3_idb_enable(unit, reg, enable, &is_idb); 3428 if (is_idb) { 3429 continue; 3430 } 3431 } 3432 #endif 3433 if (SOC_REG_IS_64(unit, reg)) { 3434 SOC_IF_ERROR_RETURN 3435 (soc_reg_get(unit, reg, port, 0, &rval64)); 3436 if (info->enable_field == INVALIDf) { 3437 if (info->enable_field_list != NULL) { 3438 field = info->enable_field_list; 3439 i = 0; 3440 while(field[i] != INVALIDf) { 3441 soc_reg64_field32_set(unit, reg, &rval64, field[i], 3442 enable ? 1 : 0); 3443 i++; 3444 } 3445 } 3446 } else { 3447 soc_reg64_field32_set(unit, reg, &rval64, info->enable_field, 3448 enable ? 1 : 0); 3449 } 3450 SOC_IF_ERROR_RETURN 3451 (soc_reg_set(unit, reg, port, 0, rval64)); 3452 } else { 3453 SOC_IF_ERROR_RETURN 3454 (soc_reg32_get(unit, reg, port, 0, &rval)); 3455 if (info->enable_field == INVALIDf) { 3456 if (info->enable_field_list != NULL) { 3457 field = info->enable_field_list; 3458 i = 0; 3459 while(field[i] != INVALIDf) { 3460 soc_reg_field_set(unit, reg, &rval, field[i], 3461 enable ? 1 : 0); 3462 i++; 3463 } 3464 } 3465 } else { 3466 soc_reg_field_set(unit, reg, &rval, info->enable_field, 3467 enable ? 1 : 0); 3468 } 3469 SOC_IF_ERROR_RETURN 3470 (soc_reg32_set(unit, reg, port, 0, rval)); 3471 } 3472 LOG_VERBOSE(BSL_LS_SOC_SER, 3473 (BSL_META_U(unit, 3474 "SER enable for: %s\n"), 3475 (info->mem == INVALIDm) ? info->mem_str : 3476 SOC_MEM_NAME(unit, info->mem))); 3477 break; 3478 #if defined (BCM_TOMAHAWK2_SUPPORT) || defined (BCM_TOMAHAWKPLUS_SUPPORT) 3479 case _SOC_PARITY_TYPE_CLMAC: 3480 reg = info->enable_reg; 3481 /* At this moment, port mapping info is not ready on PCID server */ 3482 if (SAL_BOOT_PLISIM || SAL_BOOT_BCMSIM) { 3483 break; 3484 } 3485 if (!SOC_REG_IS_VALID(unit, reg)) { 3486 break; 3487 } 3488 if (SOC_BLOCK_INFO(unit, block_info_idx).type < 0) { 3489 break; 3490 } 3491 PBMP_ITER(SOC_BLOCK_BITMAP(unit, block_info_idx), log_port) { 3492 if (SOC_REG_IS_64(unit, reg)) { 3493 SOC_IF_ERROR_RETURN 3494 (soc_reg_get(unit, reg, log_port, 0, &rval64)); 3495 soc_reg64_field32_set(unit, reg, &rval64, info->enable_field, 3496 enable ? 1 : 0); 3497 SOC_IF_ERROR_RETURN 3498 (soc_reg_set(unit, reg, log_port, 0, rval64)); 3499 } else { 3500 SOC_IF_ERROR_RETURN 3501 (soc_reg32_get(unit, reg, log_port, 0, &rval)); 3502 soc_reg_field_set(unit, reg, &rval, info->enable_field, 3503 enable ? 1 : 0); 3504 SOC_IF_ERROR_RETURN 3505 (soc_reg32_set(unit, reg, log_port, 0, rval)); 3506 } 3507 } 3508 LOG_VERBOSE(BSL_LS_SOC_SER, 3509 (BSL_META_U(unit, 3510 "SER enable for: %s\n"), 3511 (info->mem == INVALIDm) ? info->mem_str : 3512 SOC_MEM_NAME(unit, info->mem))); 3513 break; 3514 #endif 3515 #if defined (BCM_TOMAHAWK3_SUPPORT) 3516 case _SOC_PARITY_TYPE_CDMAC: 3517 reg = info->enable_reg; 3518 /* At this moment, port mapping info is not ready on PCID server */ 3519 if (SAL_BOOT_PLISIM || SAL_BOOT_BCMSIM) { 3520 break; 3521 } 3522 if (!SOC_REG_IS_VALID(unit, reg)) { 3523 break; 3524 } 3525 if (SOC_BLOCK_INFO(unit, block_info_idx).type < 0) { 3526 break; 3527 } 3528 PBMP_ITER(SOC_BLOCK_BITMAP(unit, block_info_idx), log_port) { 3529 for (idx = 0; idx < 2; idx++) { 3530 if (SOC_REG_IS_64(unit, reg)) { 3531 SOC_IF_ERROR_RETURN 3532 (soc_reg_get(unit, reg, log_port, idx, &rval64)); 3533 if (info->enable_field == INVALIDf) { 3534 if (info->enable_field_list != NULL) { 3535 field = info->enable_field_list; 3536 i = 0; 3537 while(field[i] != INVALIDf) { 3538 soc_reg64_field32_set(unit, reg, &rval64, field[i], 3539 enable ? 1 : 0); 3540 i++; 3541 } 3542 } 3543 } else { 3544 soc_reg64_field32_set(unit, reg, &rval64, info->enable_field, 3545 enable ? 1 : 0); 3546 } 3547 SOC_IF_ERROR_RETURN 3548 (soc_reg_set(unit, reg, log_port, idx, rval64)); 3549 } else { 3550 SOC_IF_ERROR_RETURN 3551 (soc_reg32_get(unit, reg, log_port, idx, &rval)); 3552 if (info->enable_field == INVALIDf) { 3553 if (info->enable_field_list != NULL) { 3554 field = info->enable_field_list; 3555 i = 0; 3556 while(field[i] != INVALIDf) { 3557 soc_reg_field_set(unit, reg, &rval, field[i], 3558 enable ? 1 : 0); 3559 i++; 3560 } 3561 } 3562 } else { 3563 soc_reg_field_set(unit, reg, &rval, info->enable_field, 3564 enable ? 1 : 0); 3565 } 3566 SOC_IF_ERROR_RETURN 3567 (soc_reg32_set(unit, reg, log_port, idx, rval)); 3568 } 3569 } 3570 } 3571 3572 if (SOC_REG_IS_VALID(unit, info->intr_enable_reg)) { 3573 reg = info->intr_enable_reg; 3574 if (SOC_BLOCK_INFO(unit, block_info_idx).type < 0) { 3575 break; 3576 } 3577 PBMP_ITER(SOC_BLOCK_BITMAP(unit, block_info_idx), log_port) { 3578 for (idx = 0; idx < 2; idx++) { 3579 if (SOC_REG_IS_64(unit, reg)) { 3580 SOC_IF_ERROR_RETURN 3581 (soc_reg_get(unit, reg, log_port, idx, &rval64)); 3582 if (info->intr_enable_field == INVALIDf) { 3583 if (info->intr_enable_field_list != NULL) { 3584 field = info->intr_enable_field_list; 3585 i = 0; 3586 while(field[i] != INVALIDf) { 3587 soc_reg64_field32_set(unit, reg, &rval64, field[i], 3588 enable ? 1 : 0); 3589 i++; 3590 } 3591 } 3592 } else { 3593 soc_reg64_field32_set(unit, reg, &rval64, info->intr_enable_field, 3594 enable ? 1 : 0); 3595 } 3596 SOC_IF_ERROR_RETURN 3597 (soc_reg_set(unit, reg, log_port, idx, rval64)); 3598 } else { 3599 SOC_IF_ERROR_RETURN 3600 (soc_reg32_get(unit, reg, log_port, idx, &rval)); 3601 if (info->intr_enable_field == INVALIDf) { 3602 if (info->intr_enable_field_list != NULL) { 3603 field = info->intr_enable_field_list; 3604 i = 0; 3605 while(field[i] != INVALIDf) { 3606 soc_reg_field_set(unit, reg, &rval, field[i], 3607 enable ? 1 : 0); 3608 i++; 3609 } 3610 } 3611 } else { 3612 soc_reg_field_set(unit, reg, &rval, info->intr_enable_field, 3613 enable ? 1 : 0); 3614 } 3615 SOC_IF_ERROR_RETURN 3616 (soc_reg32_set(unit, reg, log_port, idx, rval)); 3617 } 3618 } 3619 } 3620 } 3621 LOG_VERBOSE(BSL_LS_SOC_SER, 3622 (BSL_META_U(unit, 3623 "SER enable for: %s\n"), 3624 (info->mem == INVALIDm) ? info->mem_str : 3625 SOC_MEM_NAME(unit, info->mem))); 3626 break; 3627 #endif 3628 case _SOC_PARITY_TYPE_MAC_TX_CDC: 3629 case _SOC_PARITY_TYPE_MAC_RX_CDC: 3630 case _SOC_PARITY_TYPE_MAC_RX_TS: 3631 reg = info->enable_reg; 3632 /* At this moment, port mapping info is not ready on PCID server */ 3633 if (SAL_BOOT_PLISIM || SAL_BOOT_BCMSIM) { 3634 break; 3635 } 3636 if (!SOC_REG_IS_VALID(unit, reg)) { 3637 break; 3638 } 3639 if (SOC_BLOCK_INFO(unit, block_info_idx).type < 0) { 3640 break; 3641 } 3642 PBMP_ITER(SOC_BLOCK_BITMAP(unit, block_info_idx), log_port) { 3643 if (SOC_REG_IS_64(unit, reg)) { 3644 SOC_IF_ERROR_RETURN 3645 (soc_reg_get(unit, reg, log_port, 0, &rval64)); 3646 soc_reg64_field32_set(unit, reg, &rval64, info->enable_field, 3647 enable ? 1 : 0); 3648 SOC_IF_ERROR_RETURN 3649 (soc_reg_set(unit, reg, log_port, 0, rval64)); 3650 } else { 3651 SOC_IF_ERROR_RETURN 3652 (soc_reg32_get(unit, reg, log_port, 0, &rval)); 3653 soc_reg_field_set(unit, reg, &rval, info->enable_field, 3654 enable ? 1 : 0); 3655 SOC_IF_ERROR_RETURN 3656 (soc_reg32_set(unit, reg, log_port, 0, rval)); 3657 } 3658 } 3659 3660 if (SOC_REG_IS_VALID(unit, info->intr_enable_reg)) { 3661 reg = info->intr_enable_reg; 3662 if (SOC_BLOCK_INFO(unit, block_info_idx).type < 0) { 3663 break; 3664 } 3665 PBMP_ITER(SOC_BLOCK_BITMAP(unit, block_info_idx), log_port) { 3666 if (SOC_REG_IS_64(unit, reg)) { 3667 SOC_IF_ERROR_RETURN 3668 (soc_reg_get(unit, reg, log_port, 0, &rval64)); 3669 soc_reg64_field32_set(unit, reg, &rval64, 3670 info->intr_enable_field, 3671 enable ? 1 : 0); 3672 SOC_IF_ERROR_RETURN 3673 (soc_reg_set(unit, reg, log_port, 0, rval64)); 3674 } else { 3675 SOC_IF_ERROR_RETURN 3676 (soc_reg32_get(unit, reg, log_port, 0, &rval)); 3677 soc_reg_field_set(unit, reg, &rval, 3678 info->intr_enable_field, 3679 enable ? 1 : 0); 3680 SOC_IF_ERROR_RETURN 3681 (soc_reg32_set(unit, reg, log_port, 0, rval)); 3682 } 3683 } 3684 } 3685 LOG_VERBOSE(BSL_LS_SOC_SER, 3686 (BSL_META_U(unit, 3687 "SER enable for: %s\n"), 3688 (info->mem == INVALIDm) ? info->mem_str : 3689 SOC_MEM_NAME(unit, info->mem))); 3690 break; 3691 default: break; 3692 } 3693 } 3694 return rv; 3695 } 3696 3697 3698 static int 3699 soc_tomahawk_ser_block_enable(int unit, int enable, uint32 *p_cmic_bit, 3700 int type, soc_block_t blocktype, 3701 soc_reg_t fifo_reset_reg, void *info) 3702 { 3703 uint8 rbi; 3704 uint8 fld_val = 0; 3705 uint16 pcount; 3706 uint32 cmic_bit; 3707 int port = REG_PORT_ANY; 3708 soc_reg_t reg, ecc1b_reg; 3709 soc_field_t field, ecc1b_field; 3710 uint8 flag = 0; 3711 uint8 ecc1b_flag = 0; 3712 _soc_reg_ser_en_info_t *reg_info; 3713 _soc_mem_ser_en_info_t *mem_info; 3714 _soc_bus_ser_en_info_t *bus_info; 3715 _soc_buffer_ser_en_info_t *buf_info; 3716 char *str_type; 3717 char *str_name; 3718 static char *parity_module_str[4] = {"REG", "MEM", "BUS", "BUF"}; 3719 int latency = 0; 3720 3721 const _soc_th_ser_route_block_t *rb; 3722 3723 int done = 0; 3724 #ifdef BCM_TOMAHAWK3_SUPPORT 3725 int is_idb = 0; 3726 #endif 3727 3728 SOC_IF_ERROR_RETURN(soc_th_latency_get(unit, &latency)); 3729 3730 reg_info = (_soc_reg_ser_en_info_t*)info; 3731 mem_info = (_soc_mem_ser_en_info_t*)info; 3732 bus_info = (_soc_bus_ser_en_info_t*)info; 3733 buf_info = (_soc_buffer_ser_en_info_t*)info; 3734 for (pcount = 0;;pcount++) { /* walk thro each entry of block_info */ 3735 ecc1b_reg = INVALIDr; 3736 ecc1b_field = INVALIDf; 3737 switch (type) { 3738 case _SOC_SER_TYPE_REG: 3739 if (reg_info[pcount].reg == INVALIDr) { 3740 done = 1; 3741 } else { 3742 reg = reg_info[pcount].en_ctrl.ctrl_type.en_reg; 3743 flag = reg_info[pcount].en_ctrl.flag_reg_mem; 3744 field = reg_info[pcount].en_ctrl.en_fld; 3745 ecc1b_reg = reg_info[pcount].ecc1b_ctrl.ctrl_type.en_reg; 3746 ecc1b_flag = reg_info[pcount].ecc1b_ctrl.flag_reg_mem; 3747 ecc1b_field = reg_info[pcount].ecc1b_ctrl.en_fld; 3748 str_name = SOC_REG_NAME(unit, reg_info[pcount].reg); 3749 } 3750 break; 3751 case _SOC_SER_TYPE_MEM: 3752 if (mem_info[pcount].mem == INVALIDm) { 3753 done = 1; 3754 } else if (!SOC_MEM_IS_VALID(unit, mem_info[pcount].mem) || 3755 (SOC_IS_TOMAHAWK(unit) && 3756 ((mem_info[pcount].mem == TRUNK_RR_CNTm) || 3757 (mem_info[pcount].mem == TRUNK_RR_CNT_PIPE0m) || 3758 (mem_info[pcount].mem == TRUNK_RR_CNT_PIPE1m) || 3759 (mem_info[pcount].mem == TRUNK_RR_CNT_PIPE2m) || 3760 (mem_info[pcount].mem == TRUNK_RR_CNT_PIPE3m))) || 3761 (SOC_MEM_INFO(unit, mem_info[pcount].mem).flags & 3762 SOC_MEM_FLAG_SER_PARITY_ENABLE_SKIP)) { 3763 LOG_VERBOSE(BSL_LS_SOC_SER, (BSL_META_U(unit, 3764 "skip SER enable for mem %s\n"), 3765 SOC_MEM_NAME(unit, mem_info[pcount].mem))); 3766 continue; 3767 } else { 3768 reg = mem_info[pcount].en_ctrl.ctrl_type.en_reg; 3769 flag = mem_info[pcount].en_ctrl.flag_reg_mem; 3770 field = mem_info[pcount].en_ctrl.en_fld; 3771 ecc1b_reg = mem_info[pcount].ecc1b_ctrl.ctrl_type.en_reg; 3772 ecc1b_flag = mem_info[pcount].ecc1b_ctrl.flag_reg_mem; 3773 ecc1b_field = mem_info[pcount].ecc1b_ctrl.en_fld; 3774 str_name = SOC_MEM_NAME(unit, mem_info[pcount].mem); 3775 #ifdef BCM_TOMAHAWK3_SUPPORT 3776 if (SOC_IS_TOMAHAWK3(unit)) { 3777 (void)_soc_tomahawk3_idb_enable(unit, reg, enable, &is_idb); 3778 if (is_idb) { 3779 continue; 3780 } 3781 } 3782 #endif 3783 3784 } 3785 break; 3786 case _SOC_SER_TYPE_BUS: 3787 if (bus_info[pcount].en_reg == INVALIDr) { 3788 done = 1; 3789 } else { 3790 reg = bus_info[pcount].en_reg; 3791 field = bus_info[pcount].en_fld; 3792 str_name = bus_info[pcount].bus_name; 3793 ecc1b_reg = bus_info[pcount].ecc1b_en_reg; 3794 ecc1b_field = bus_info[pcount].ecc1b_en_fld; 3795 } 3796 break; 3797 case _SOC_SER_TYPE_BUF: 3798 if (buf_info[pcount].en_reg == INVALIDr) { 3799 done = 1; 3800 } else { 3801 reg = buf_info[pcount].en_reg; 3802 field = buf_info[pcount].en_fld; 3803 str_name = buf_info[pcount].buffer_name; 3804 if (SOC_IS_TOMAHAWKPLUS(unit) && 3805 (field == EN_COR_ERR_RPTf) && 3806 (reg == IDB_OBM0_QUEUE_SER_CONTROLr || 3807 reg == IDB_OBM1_QUEUE_SER_CONTROLr || 3808 reg == IDB_OBM2_QUEUE_SER_CONTROLr || 3809 reg == IDB_OBM3_QUEUE_SER_CONTROLr || 3810 reg == IDB_OBM4_QUEUE_SER_CONTROLr || 3811 reg == IDB_OBM5_QUEUE_SER_CONTROLr || 3812 reg == IDB_OBM6_QUEUE_SER_CONTROLr || 3813 reg == IDB_OBM7_QUEUE_SER_CONTROLr)) { 3814 /* skip enable of SBE for IDB_OBMn_QUEUE mems */ 3815 reg = INVALIDr; 3816 field = INVALIDf; 3817 } 3818 ecc1b_reg = buf_info[pcount].ecc1b_en_reg; 3819 ecc1b_field = buf_info[pcount].ecc1b_en_fld; 3820 } 3821 break; 3822 default: 3823 LOG_CLI((BSL_META_U(unit, 3824 "Unknown parity module " 3825 "[pcount: %d].\n"), pcount)); 3826 return SOC_E_INTERNAL; 3827 } 3828 if (done) { 3829 break; 3830 } else { 3831 str_type = parity_module_str[type]; 3832 } 3833 3834 #ifdef BCM_TOMAHAWK3_SUPPORT 3835 if (SOC_IS_TOMAHAWK3(unit)) { 3836 if (enable) { 3837 if (reg == IFP_TCAM_POOL0_BISTCTRLr || 3838 reg == IFP_TCAM_POOL1_BISTCTRLr || 3839 reg == IFP_TCAM_POOL2_BISTCTRLr || 3840 reg == IFP_TCAM_POOL3_BISTCTRLr) { 3841 fld_val = 0x7; 3842 } else if (reg == VFP_CAM_BIST_CONTROLr) { 3843 fld_val = 0xff; 3844 } else { 3845 fld_val = 1; 3846 } 3847 } else { 3848 fld_val = 0; 3849 } 3850 } else 3851 #endif 3852 { 3853 fld_val = enable ? 1 : 0; 3854 } 3855 if (SOC_REG_IS_VALID(unit, reg) && (flag == 0)) { 3856 /* NOTE: Do not use the field modify routine in the following as 3857 some regs do not return the correct value due to which the 3858 modify routine skips the write */ 3859 if (SOC_REG_IS_64(unit,reg)) { 3860 soc_th_ser_reg_field_modify(unit, reg, port, field, 3861 fld_val, 0, -1); 3862 } else { 3863 soc_th_ser_reg_field32_modify(unit, reg, port, field, 3864 fld_val, 0, -1); 3865 } 3866 } 3867 if (ecc1b_reg != INVALIDr && ecc1b_field != INVALIDf && 3868 SOC_REG_IS_VALID(unit, ecc1b_reg) && (ecc1b_flag == 0)) { 3869 if (SOC_REG_IS_64(unit,reg)) { 3870 soc_th_ser_reg_field_modify(unit, ecc1b_reg, port, ecc1b_field, 3871 fld_val, 0, -1); 3872 } else { 3873 soc_th_ser_reg_field32_modify(unit, ecc1b_reg, port, ecc1b_field, 3874 fld_val, 0, -1); 3875 } 3876 } 3877 LOG_VERBOSE(BSL_LS_SOC_SER, 3878 (BSL_META_U(unit, 3879 "SER enable for %s: %s\n"), 3880 str_type, str_name)); 3881 } /* walk thro each entry of block_info */ 3882 3883 /* Loop through each place-and-route block entry */ 3884 for (rbi = 0; ; rbi++) { 3885 #ifdef BCM_TOMAHAWK3_SUPPORT 3886 if (SOC_IS_TOMAHAWK3(unit)) { 3887 rb = &_soc_th3_ser_route_blocks[rbi]; 3888 } else 3889 #endif 3890 #ifdef BCM_TOMAHAWK2_SUPPORT 3891 if (SOC_IS_TOMAHAWK2(unit)) { 3892 rb = &_soc_th2_ser_route_blocks[rbi]; 3893 } else 3894 #endif 3895 #ifdef BCM_TOMAHAWKPLUS_SUPPORT 3896 if (SOC_IS_TOMAHAWKPLUS(unit)) { 3897 rb = &_soc_thplus_ser_route_blocks[rbi]; 3898 } else 3899 #endif 3900 { 3901 rb = &_soc_th_ser_route_blocks[rbi]; 3902 } 3903 3904 cmic_bit = rb->cmic_bit; 3905 if (cmic_bit == 0) { 3906 /* End of table */ 3907 break; 3908 } 3909 if (rb->blocktype == blocktype) { 3910 /* LHS has only SOC_BLK_MMU and * RHS has only 3911 * SOC_BLK_MMU_GLB. Thus for MMU, following will not be 3912 * executed. 3913 */ 3914 /* New SER mechanism (except IP.IDB) */ 3915 *p_cmic_bit |= cmic_bit; 3916 /* block_info has entries only for BLK_IPIPE, BLK_EPIPE, 3917 * BLK_MMU_GLB. 3918 * route_block_info on other hand has BLK_MMU, BLK_IPIPE, 3919 * BLK_EPIPE, BLK_CLPORT. 3920 * So, we can he here only for BLK_IPIPE, BLK_EPIPE and for 3921 * these cmic reg is always cmic_rval3 - see block_info[] array 3922 */ 3923 if (rb->enable_reg != INVALIDr && 3924 rb->enable_field != INVALIDf) { 3925 SOC_IF_ERROR_RETURN 3926 (soc_reg_field32_modify(unit, rb->enable_reg, 3927 REG_PORT_ANY, rb->enable_field, enable ? 1 : 0)); 3928 } 3929 if ((rb->blocktype == SOC_BLK_IPIPE) 3930 && (rb->cmic_bit != _SOC_TH_IPIPE0_IP0_INTR) 3931 && (rb->cmic_bit != _SOC_TH_IPIPE1_IP0_INTR) 3932 && (rb->cmic_bit != _SOC_TH_IPIPE2_IP0_INTR) 3933 && (rb->cmic_bit != _SOC_TH_IPIPE3_IP0_INTR)) { 3934 #ifdef BCM_TOMAHAWK3_SUPPORT 3935 if (SOC_IS_TOMAHAWK3(unit) && (rb->cmic_bit != _SOC_TH3_CEV_INTR)) { 3936 _soc_th3_ip_pipe_fifo_bmask[unit][rb->pipe] |= cmic_bit; 3937 } else 3938 #endif 3939 #ifdef BCM_TOMAHAWK2_SUPPORT 3940 if (SOC_IS_TOMAHAWK2(unit)) { 3941 _soc_th2_ip_pipe_fifo_bmask[unit][rb->pipe] |= cmic_bit; 3942 } else 3943 #endif 3944 { 3945 _soc_th_ip_pipe_fifo_bmask[unit][rb->pipe] |= cmic_bit; 3946 } 3947 } 3948 } 3949 } 3950 3951 /* reset (toggle) fifo if applicable */ 3952 if (fifo_reset_reg != INVALIDr) { 3953 SOC_IF_ERROR_RETURN 3954 (soc_reg_field32_modify(unit, fifo_reset_reg, 3955 REG_PORT_ANY, FIFO_RESETf, 1)); 3956 SOC_IF_ERROR_RETURN 3957 (soc_reg_field32_modify(unit, fifo_reset_reg, 3958 REG_PORT_ANY, FIFO_RESETf, 0)); 3959 } 3960 3961 return SOC_E_NONE; 3962 } 3963 3964 int 3965 soc_tomahawk3_parity_bit_enable(int unit, soc_reg_t enreg, soc_mem_t enmem, 3966 soc_field_t enfld, int enfld_position, int enable) 3967 { 3968 uint32 rval = 0; 3969 uint32 value = 0; 3970 uint32 entry[SOC_MAX_MEM_WORDS]; 3971 uint32 copyno; 3972 uint64 rval64; 3973 3974 if (SOC_REG_IS_VALID(unit, enreg)) { 3975 if (SOC_REG_IS_64(unit, enreg)) { 3976 SOC_IF_ERROR_RETURN 3977 (soc_reg_get(unit, enreg, REG_PORT_ANY, 0, &rval64)); 3978 if (enfld_position == -1) { 3979 soc_reg64_field32_set(unit, enreg, &rval64, enfld, enable ? 1 : 0); 3980 } else { 3981 value = soc_reg64_field32_get(unit, enreg, rval64, enfld); 3982 if (enable) { 3983 value |= (1 << enfld_position); 3984 } else { 3985 value &= ~(1 << enfld_position); 3986 } 3987 soc_reg64_field32_set(unit, enreg, &rval64, enfld, value); 3988 } 3989 SOC_IF_ERROR_RETURN 3990 (soc_reg_set(unit, enreg, REG_PORT_ANY, 0, rval64)); 3991 } else { 3992 SOC_IF_ERROR_RETURN 3993 (soc_reg32_get(unit, enreg, REG_PORT_ANY, 0, &rval)); 3994 if (enfld_position == -1) { 3995 if (enreg == IFP_TCAM_CAM_CONTROLr) { 3996 soc_reg_field_set(unit, enreg, &rval, enfld, enable ? 0xf : 0); 3997 } else { 3998 soc_reg_field_set(unit, enreg, &rval, enfld, enable ? 1 : 0); 3999 } 4000 } else { 4001 value = soc_reg_field_get(unit, enreg, rval, enfld); 4002 if (enable) { 4003 value |= (1 << enfld_position); 4004 } else { 4005 value &= ~(1 << enfld_position); 4006 } 4007 soc_reg_field_set(unit, enreg, &rval, enfld, value); 4008 } 4009 SOC_IF_ERROR_RETURN 4010 (soc_reg32_set(unit, enreg, REG_PORT_ANY, 0, rval)); 4011 } 4012 } else if (SOC_MEM_IS_VALID(unit, enmem)){ 4013 SOC_MEM_BLOCK_ITER(unit, enmem, copyno) { 4014 SOC_IF_ERROR_RETURN(soc_mem_read(unit, enmem, copyno, 0, entry)); 4015 if (enfld_position == -1) { 4016 soc_mem_field32_set(unit, enmem, entry, enfld, enable ? 1 : 0); 4017 } else { 4018 value = soc_mem_field32_get(unit, enmem, entry, enfld); 4019 if (enable) { 4020 value |= (1 << enfld_position); 4021 } else { 4022 value &= ~(1 << enfld_position); 4023 } 4024 soc_mem_field32_set(unit, enmem, entry, enfld, value); 4025 } 4026 SOC_IF_ERROR_RETURN(soc_mem_write(unit, enmem, copyno, 0, entry)); 4027 } 4028 } 4029 4030 return SOC_E_NONE; 4031 } 4032 4033 int 4034 soc_tomahawk3_ser_enable_parity_table(int unit, int type, void *info, int enable) 4035 { 4036 uint32 i = 0; 4037 uint32 entry[SOC_MAX_MEM_WORDS]; 4038 uint32 copyno; 4039 uint32 done = 0; 4040 uint8 flag = 0; 4041 soc_mem_t en_mem = INVALIDm; 4042 soc_mem_t ecc1b_en_mem = INVALIDm; 4043 soc_field_t en_fld = INVALIDf; 4044 soc_field_t ecc1b_en_fld = INVALIDf; 4045 const _soc_mem_ser_en_info_t *mem_info; 4046 const _soc_reg_ser_en_info_t *reg_info; 4047 4048 mem_info = (_soc_mem_ser_en_info_t*)info; 4049 reg_info = (_soc_reg_ser_en_info_t*)info; 4050 4051 for (i = 0; ; i++) { 4052 switch(type) { 4053 case _SOC_SER_TYPE_REG: 4054 if (reg_info[i].reg == INVALIDr) { 4055 done = 1; 4056 } 4057 en_mem = reg_info[i].en_ctrl.ctrl_type.en_mem; 4058 flag = reg_info[i].en_ctrl.flag_reg_mem; 4059 en_fld = reg_info[i].en_ctrl.en_fld; 4060 ecc1b_en_mem = reg_info[i].ecc1b_ctrl.ctrl_type.en_mem; 4061 ecc1b_en_fld = reg_info[i].ecc1b_ctrl.en_fld; 4062 break; 4063 case _SOC_SER_TYPE_MEM: 4064 if (mem_info[i].mem == INVALIDm) { 4065 done = 1; 4066 } 4067 en_mem = mem_info[i].en_ctrl.ctrl_type.en_mem; 4068 flag = mem_info[i].en_ctrl.flag_reg_mem; 4069 en_fld = mem_info[i].en_ctrl.en_fld; 4070 ecc1b_en_mem = mem_info[i].ecc1b_ctrl.ctrl_type.en_mem; 4071 ecc1b_en_fld = mem_info[i].ecc1b_ctrl.en_fld; 4072 break; 4073 default: 4074 LOG_CLI((BSL_META_U(unit, 4075 "Unknown parity module " 4076 "[type: %d].\n"), type)); 4077 break; 4078 } 4079 4080 if (done == 1) { 4081 break; 4082 } 4083 4084 if (flag == 0) { 4085 continue; 4086 } 4087 4088 SOC_MEM_BLOCK_ITER(unit, en_mem, copyno) { 4089 SOC_IF_ERROR_RETURN(soc_mem_read(unit, en_mem, copyno, 0, entry)); 4090 soc_mem_field32_set(unit, en_mem, entry, en_fld, enable ? 1 : 0); 4091 SOC_IF_ERROR_RETURN(soc_mem_write(unit, en_mem, copyno, 0, entry)); 4092 } 4093 4094 if (ecc1b_en_mem != INVALIDm) { 4095 SOC_MEM_BLOCK_ITER(unit, ecc1b_en_mem, copyno) { 4096 SOC_IF_ERROR_RETURN(soc_mem_read(unit, ecc1b_en_mem, copyno, 4097 0, entry)); 4098 soc_mem_field32_set(unit, ecc1b_en_mem, entry, 4099 ecc1b_en_fld, enable ? 1 : 0); 4100 SOC_IF_ERROR_RETURN(soc_mem_write(unit, ecc1b_en_mem, copyno, 4101 0, entry)); 4102 } 4103 } 4104 } 4105 4106 return SOC_E_NONE; 4107 } 4108 4109 4110 int 4111 soc_tomahawk3_ser_enable_parity_table_all(int unit, int enable) 4112 { 4113 SOC_IF_ERROR_RETURN(soc_tomahawk3_ser_enable_parity_table(unit, 4114 _SOC_SER_TYPE_MEM, (void*) SOC_IP_MEM_SER_INFO(unit), enable)); 4115 SOC_IF_ERROR_RETURN(soc_tomahawk3_ser_enable_parity_table(unit, 4116 _SOC_SER_TYPE_REG, (void*) SOC_IP_REG_SER_INFO(unit), enable)); 4117 SOC_IF_ERROR_RETURN(soc_tomahawk3_ser_enable_parity_table(unit, 4118 _SOC_SER_TYPE_MEM, (void*) SOC_EP_MEM_SER_INFO(unit), enable)); 4119 SOC_IF_ERROR_RETURN(soc_tomahawk3_ser_enable_parity_table(unit, 4120 _SOC_SER_TYPE_REG, (void*) SOC_EP_REG_SER_INFO(unit), enable)); 4121 SOC_IF_ERROR_RETURN(soc_tomahawk3_ser_enable_parity_table(unit, 4122 _SOC_SER_TYPE_MEM, (void*) SOC_MMU_MEM_SER_INFO(unit), enable)); 4123 4124 return SOC_E_NONE; 4125 } 4126 4127 4128 int 4129 soc_tomahawk_ser_enable_all(int unit, int enable) 4130 { 4131 uint8 rbi; 4132 uint32 cmic_bit; 4133 uint32 cmic_rval3, cmic_rval4, cmic_rval5; 4134 int port = REG_PORT_ANY; 4135 int rv, block_info_idx; 4136 uint64 rval64; 4137 4138 const _soc_th_ser_route_block_t *rb; 4139 4140 #ifdef BCM_TOMAHAWK2_SUPPORT 4141 uint32 cmic_rval6 = 0; 4142 #endif 4143 #if defined(BCM_TOMAHAWK3_SUPPORT) 4144 uint32 cmicx_rval0, cmicx_rval1, cmicx_rval2, cmicx_rval3; 4145 #endif 4146 4147 #if defined(BCM_TOMAHAWK3_SUPPORT) 4148 if (SOC_IS_TOMAHAWK3(unit)) { 4149 SOC_IF_ERROR_RETURN(soc_iproc_getreg(unit, 4150 soc_reg_addr(unit, ICFG_CHIP_LP_INTR_ENABLE_REG0r, 4151 REG_PORT_ANY, 0), &cmicx_rval0)); 4152 SOC_IF_ERROR_RETURN(soc_iproc_getreg(unit, 4153 soc_reg_addr(unit, ICFG_CHIP_LP_INTR_ENABLE_REG1r, 4154 REG_PORT_ANY, 0), &cmicx_rval1)); 4155 SOC_IF_ERROR_RETURN(soc_iproc_getreg(unit, 4156 soc_reg_addr(unit, ICFG_CHIP_LP_INTR_ENABLE_REG2r, 4157 REG_PORT_ANY, 0), &cmicx_rval2)); 4158 SOC_IF_ERROR_RETURN(soc_iproc_getreg(unit, 4159 soc_reg_addr(unit, ICFG_CHIP_LP_INTR_ENABLE_REG3r, 4160 REG_PORT_ANY, 0), &cmicx_rval3)); 4161 } else 4162 #endif 4163 { 4164 4165 /* coverity[result_independent_of_operands] */ 4166 SOC_IF_ERROR_RETURN(READ_CMIC_CMC0_PCIE_IRQ_MASK3r(unit, &cmic_rval3)); 4167 /* coverity[result_independent_of_operands] */ 4168 SOC_IF_ERROR_RETURN(READ_CMIC_CMC0_PCIE_IRQ_MASK4r(unit, &cmic_rval4)); 4169 /* coverity[result_independent_of_operands] */ 4170 SOC_IF_ERROR_RETURN(READ_CMIC_CMC0_PCIE_IRQ_MASK5r(unit, &cmic_rval5)); 4171 4172 #ifdef BCM_TOMAHAWK2_SUPPORT 4173 if (SOC_IS_TOMAHAWK2(unit)) { 4174 SOC_IF_ERROR_RETURN(READ_CMIC_CMC0_PCIE_IRQ_MASK6r(unit, &cmic_rval6)); 4175 } 4176 #endif 4177 } 4178 4179 #ifdef BCM_TOMAHAWK2_SUPPORT 4180 if (SOC_IS_TOMAHAWK2(unit)) { 4181 _soc_th2_ip_pipe_fifo_bmask[unit][0] = 0; 4182 _soc_th2_ip_pipe_fifo_bmask[unit][1] = 0; 4183 _soc_th2_ip_pipe_fifo_bmask[unit][2] = 0; 4184 _soc_th2_ip_pipe_fifo_bmask[unit][3] = 0; 4185 } else 4186 #endif 4187 { 4188 _soc_th_ip_pipe_fifo_bmask[unit][0] = 0; 4189 _soc_th_ip_pipe_fifo_bmask[unit][1] = 0; 4190 _soc_th_ip_pipe_fifo_bmask[unit][2] = 0; 4191 _soc_th_ip_pipe_fifo_bmask[unit][3] = 0; 4192 } 4193 4194 SOC_IF_ERROR_RETURN(soc_tomahawk_ser_block_enable(unit, enable, &cmic_rval3, 4195 _SOC_SER_TYPE_REG, SOC_BLK_IPIPE, INVALIDr, 4196 (void*) SOC_IP_REG_SER_INFO(unit))); 4197 4198 SOC_IF_ERROR_RETURN(soc_tomahawk_ser_block_enable(unit, enable, &cmic_rval3, 4199 _SOC_SER_TYPE_MEM, SOC_BLK_IPIPE, ING_SER_FIFO_CTRLr, 4200 (void*) SOC_IP_MEM_SER_INFO(unit))); 4201 4202 SOC_IF_ERROR_RETURN(soc_tomahawk_ser_block_enable(unit, enable, &cmic_rval3, 4203 _SOC_SER_TYPE_REG, SOC_BLK_EPIPE, INVALIDr, 4204 (void*) SOC_EP_REG_SER_INFO(unit))); 4205 4206 SOC_IF_ERROR_RETURN(soc_tomahawk_ser_block_enable(unit, enable, &cmic_rval3, 4207 _SOC_SER_TYPE_MEM, SOC_BLK_EPIPE, EGR_SER_FIFO_CTRLr, 4208 (void*) SOC_EP_MEM_SER_INFO(unit))); 4209 4210 SOC_IF_ERROR_RETURN(soc_tomahawk_ser_block_enable(unit, enable, &cmic_rval3, 4211 _SOC_SER_TYPE_MEM, SOC_BLK_MMU_GLB, INVALIDr, 4212 (void*) SOC_MMU_MEM_SER_INFO(unit))); 4213 4214 if (SOC_IS_TOMAHAWK(unit)) { 4215 SOC_IF_ERROR_RETURN(soc_tomahawk_ser_block_enable(unit, enable, &cmic_rval3, 4216 _SOC_SER_TYPE_BUS, SOC_BLK_IPIPE, INVALIDr, 4217 (void*) &_soc_th_ip_bus_ser_info)); 4218 4219 SOC_IF_ERROR_RETURN(soc_tomahawk_ser_block_enable(unit, enable, &cmic_rval3, 4220 _SOC_SER_TYPE_BUF, SOC_BLK_IPIPE, INVALIDr, 4221 (void*) &_soc_th_ip_buffer_ser_info)); 4222 4223 SOC_IF_ERROR_RETURN(soc_tomahawk_ser_block_enable(unit, enable, &cmic_rval3, 4224 _SOC_SER_TYPE_BUS, SOC_BLK_EPIPE, INVALIDr, 4225 (void*) &_soc_th_ep_bus_ser_info)); 4226 4227 SOC_IF_ERROR_RETURN(soc_tomahawk_ser_block_enable(unit, enable, &cmic_rval3, 4228 _SOC_SER_TYPE_BUF, SOC_BLK_EPIPE, INVALIDr, 4229 (void*) &_soc_th_ep_buffer_ser_info)); 4230 } 4231 4232 #if defined(BCM_TOMAHAWK2_SUPPORT) && defined(BCM_56970_A0) 4233 if (SOC_IS_TOMAHAWK2(unit)) { 4234 SOC_IF_ERROR_RETURN(soc_tomahawk_ser_block_enable(unit, enable, &cmic_rval3, 4235 _SOC_SER_TYPE_BUS, SOC_BLK_IPIPE, INVALIDr, 4236 (void*) &_soc_bcm56970_a0_ip_bus_ser_info)); 4237 4238 SOC_IF_ERROR_RETURN(soc_tomahawk_ser_block_enable(unit, enable, &cmic_rval3, 4239 _SOC_SER_TYPE_BUF, SOC_BLK_IPIPE, INVALIDr, 4240 (void*) &_soc_bcm56970_a0_ip_buffer_ser_info)); 4241 4242 SOC_IF_ERROR_RETURN(soc_tomahawk_ser_block_enable(unit, enable, &cmic_rval3, 4243 _SOC_SER_TYPE_BUS, SOC_BLK_EPIPE, INVALIDr, 4244 (void*) &_soc_bcm56970_a0_ep_bus_ser_info)); 4245 4246 SOC_IF_ERROR_RETURN(soc_tomahawk_ser_block_enable(unit, enable, &cmic_rval3, 4247 _SOC_SER_TYPE_BUF, SOC_BLK_EPIPE, INVALIDr, 4248 (void*) &_soc_bcm56970_a0_ep_buffer_ser_info)); 4249 SOC_IF_ERROR_RETURN(soc_tomahawk_ser_block_enable(unit, enable, &cmic_rval3, 4250 _SOC_SER_TYPE_BUF, SOC_BLK_EPIPE, INVALIDr, 4251 (void*) &_soc_th2_ifp_buffer_ser_info)); 4252 } 4253 #endif 4254 4255 #if defined(BCM_TOMAHAWK3_SUPPORT) && defined(BCM_56980_A0) 4256 if (SOC_IS_TOMAHAWK3(unit)) { 4257 SOC_IF_ERROR_RETURN(soc_tomahawk_ser_block_enable(unit, enable, &cmic_rval3, 4258 _SOC_SER_TYPE_BUS, SOC_BLK_IPIPE, INVALIDr, 4259 (void*) &_soc_bcm56980_a0_ip_bus_ser_info)); 4260 4261 SOC_IF_ERROR_RETURN(soc_tomahawk_ser_block_enable(unit, enable, &cmic_rval3, 4262 _SOC_SER_TYPE_BUF, SOC_BLK_IPIPE, INVALIDr, 4263 (void*) &_soc_bcm56980_a0_ip_buffer_ser_info)); 4264 4265 SOC_IF_ERROR_RETURN(soc_tomahawk_ser_block_enable(unit, enable, &cmic_rval3, 4266 _SOC_SER_TYPE_BUS, SOC_BLK_EPIPE, INVALIDr, 4267 (void*) &_soc_bcm56980_a0_ep_bus_ser_info)); 4268 4269 SOC_IF_ERROR_RETURN(soc_tomahawk_ser_block_enable(unit, enable, &cmic_rval3, 4270 _SOC_SER_TYPE_BUF, SOC_BLK_EPIPE, INVALIDr, 4271 (void*) &_soc_bcm56980_a0_ep_buffer_ser_info)); 4272 SOC_IF_ERROR_RETURN(soc_tomahawk_ser_block_enable(unit, enable, &cmic_rval3, 4273 _SOC_SER_TYPE_BUF, SOC_BLK_EPIPE, INVALIDr, 4274 (void*) &_soc_th3_no_mapping_ser_info)); 4275 } 4276 #endif 4277 4278 /* Enable 1B error reporting for some special items */ 4279 4280 /* Loop through each place-and-route block entry to enable legacy 4281 style SER stuff */ 4282 /* BLK_MMU, BLK_CLPORT will be handled here */ 4283 for (rbi = 0; ; rbi++) { 4284 #ifdef BCM_TOMAHAWK3_SUPPORT 4285 if (SOC_IS_TOMAHAWK3(unit)) { 4286 rb = &_soc_th3_ser_route_blocks[rbi]; 4287 } else 4288 #endif 4289 #ifdef BCM_TOMAHAWK2_SUPPORT 4290 if (SOC_IS_TOMAHAWK2(unit)) { 4291 rb = &_soc_th2_ser_route_blocks[rbi]; 4292 } else 4293 #endif 4294 #ifdef BCM_TOMAHAWKPLUS_SUPPORT 4295 if (SOC_IS_TOMAHAWKPLUS(unit)) { 4296 rb = &_soc_thplus_ser_route_blocks[rbi]; 4297 } else 4298 #endif 4299 { 4300 rb = &_soc_th_ser_route_blocks[rbi]; 4301 } 4302 4303 port = REG_PORT_ANY; 4304 cmic_bit = rb->cmic_bit; 4305 if (cmic_bit == 0) { 4306 /* End of table */ 4307 break; 4308 } 4309 4310 if (enable) { 4311 #ifdef BCM_TOMAHAWK3_SUPPORT 4312 if (SOC_IS_TOMAHAWK3(unit)) { 4313 switch (rb->cmic_reg) { 4314 case 0: cmicx_rval0 |= cmic_bit; break; 4315 case 1: cmicx_rval1 |= cmic_bit; break; 4316 case 2: cmicx_rval2 |= cmic_bit; break; 4317 case 3: cmicx_rval3 |= cmic_bit; break; 4318 default: break; 4319 } 4320 } else 4321 #endif 4322 { 4323 switch (rb->cmic_reg) { 4324 case 3: cmic_rval3 |= cmic_bit; break; 4325 case 4: cmic_rval4 |= cmic_bit; break; 4326 case 5: cmic_rval5 |= cmic_bit; break; 4327 #ifdef BCM_TOMAHAWK2_SUPPORT 4328 case 6: cmic_rval6 |= cmic_bit; break; 4329 #endif 4330 default: break; 4331 } 4332 } 4333 } else { 4334 #ifdef BCM_TOMAHAWK3_SUPPORT 4335 if (SOC_IS_TOMAHAWK3(unit)) { 4336 switch (rb->cmic_reg) { 4337 case 0: cmicx_rval0 &= ~cmic_bit; break; 4338 case 1: cmicx_rval1 &= ~cmic_bit; break; 4339 case 2: cmicx_rval2 &= ~cmic_bit; break; 4340 case 3: cmicx_rval3 &= ~cmic_bit; break; 4341 default: break; 4342 } 4343 } 4344 #endif 4345 } 4346 4347 if (rb->info == NULL) { 4348 continue; 4349 } 4350 4351 SOC_BLOCK_ITER(unit, block_info_idx, rb->blocktype) { 4352 if (SOC_BLOCK_INFO(unit, block_info_idx).number == rb->id) { 4353 port = SOC_BLOCK_PORT(unit, block_info_idx); 4354 break; 4355 } 4356 } 4357 if (rb->enable_reg != INVALIDr) { 4358 if (SOC_BLOCK_IN_LIST(SOC_REG_INFO(unit, rb->enable_reg).block, 4359 SOC_BLK_PORT) && (port == REG_PORT_ANY)) { 4360 /* This port block is not configured */ 4361 continue; 4362 } 4363 SOC_IF_ERROR_RETURN 4364 (soc_reg_get(unit, rb->enable_reg, port, 0, &rval64)); 4365 } 4366 4367 rv = _soc_tomahawk_ser_enable_info(unit, block_info_idx, rb->id, port, 4368 rb->enable_reg, &rval64, 4369 rb->info, INVALIDm, enable); 4370 if (rv == SOC_E_NOT_FOUND) { 4371 continue; 4372 } else if (SOC_FAILURE(rv)) { 4373 return rv; 4374 } 4375 4376 if (rb->enable_reg != INVALIDr) { 4377 /* Write per route block parity enable register */ 4378 SOC_IF_ERROR_RETURN 4379 (soc_reg_set(unit, rb->enable_reg, port, 0, rval64)); 4380 } 4381 } 4382 4383 #if defined(BCM_TOMAHAWK3_SUPPORT) 4384 if (SOC_IS_TOMAHAWK3(unit)) { 4385 SOC_IF_ERROR_RETURN(soc_iproc_setreg(unit, 4386 soc_reg_addr(unit, ICFG_CHIP_LP_INTR_ENABLE_REG0r, 4387 REG_PORT_ANY, 0), cmicx_rval0)); 4388 cmicx_rval1 &= (~0xc300); 4389 SOC_IF_ERROR_RETURN(soc_iproc_setreg(unit, 4390 soc_reg_addr(unit, ICFG_CHIP_LP_INTR_ENABLE_REG1r, 4391 REG_PORT_ANY, 0), cmicx_rval1)); 4392 SOC_IF_ERROR_RETURN(soc_iproc_setreg(unit, 4393 soc_reg_addr(unit, ICFG_CHIP_LP_INTR_ENABLE_REG2r, 4394 REG_PORT_ANY, 0), cmicx_rval2)); 4395 SOC_IF_ERROR_RETURN(soc_iproc_setreg(unit, 4396 soc_reg_addr(unit, ICFG_CHIP_LP_INTR_ENABLE_REG3r, 4397 REG_PORT_ANY, 0), cmicx_rval3)); 4398 _soc_th3_tcam_wrapper_enable(unit, enable); 4399 (void)soc_th3_tcam_engine_enable(unit, enable); 4400 } 4401 #endif 4402 4403 if (enable) { 4404 /* MMU enables */ 4405 /* check trident2.c - may have to add some similar code here */ 4406 #ifdef BCM_CMICX_SUPPORT 4407 if (soc_feature(unit, soc_feature_cmicx)) { 4408 (void)soc_cmic_intr_enable(unit, CHIP_INTR_LOW_PRIORITY); 4409 } 4410 #endif 4411 #ifdef BCM_CMICM_SUPPORT 4412 /* Write CMIC enable register */ 4413 if (soc_feature(unit, soc_feature_cmicm)) { 4414 (void)soc_cmicm_intr3_enable(unit, cmic_rval3); 4415 (void)soc_cmicm_intr4_enable(unit, cmic_rval4); 4416 (void)soc_cmicm_intr5_enable(unit, cmic_rval5); 4417 #ifdef BCM_TOMAHAWK2_SUPPORT 4418 if (SOC_IS_TOMAHAWK2(unit)) { 4419 (void)soc_cmicm_intr6_enable(unit, cmic_rval6); 4420 if (soc_feature(unit, soc_feature_tcam_scan_engine)) { 4421 (void)soc_th2_tcam_engine_enable(unit, TRUE); 4422 (void) _soc_th2_tcam_wrapper_enable(unit, TRUE); 4423 } 4424 } 4425 #endif 4426 } 4427 #endif 4428 } else { 4429 /* MMU disables */ 4430 /* check trident2.c - may have to add some similar code here */ 4431 4432 /* Write CMIC disable register */ 4433 #ifdef BCM_CMICX_SUPPORT 4434 if (soc_feature(unit, soc_feature_cmicx)) { 4435 (void)soc_cmic_intr_disable(unit, CHIP_INTR_LOW_PRIORITY); 4436 } 4437 #endif 4438 #ifdef BCM_CMICM_SUPPORT 4439 if (soc_feature(unit, soc_feature_cmicm)) { 4440 (void)soc_cmicm_intr3_disable(unit, cmic_rval3); 4441 (void)soc_cmicm_intr4_disable(unit, cmic_rval4); 4442 (void)soc_cmicm_intr5_disable(unit, cmic_rval5); 4443 #ifdef BCM_TOMAHAWK2_SUPPORT 4444 if (SOC_IS_TOMAHAWK2(unit)) { 4445 (void)soc_cmicm_intr6_disable(unit, cmic_rval6); 4446 } 4447 #endif 4448 } 4449 #endif 4450 } 4451 return SOC_E_NONE; 4452 } 4453 4454 STATIC int soc_tomahawk_pipe_select(int unit, int egress, int pipe); 4455 4456 STATIC void 4457 _soc_th_ser_control_reg_get(int unit, 4458 const _soc_mem_ser_en_info_t *ser_en_info_list, 4459 soc_mem_t mem, 4460 soc_reg_t *ser_control_reg, 4461 soc_mem_t *ser_control_mem, 4462 soc_field_t *ser_enable_field) 4463 { 4464 int i; 4465 if ((ser_en_info_list == NULL) || (ser_control_reg == NULL) || 4466 (ser_enable_field == NULL)) { 4467 return; 4468 } 4469 for (i = 0; ser_en_info_list[i].mem != INVALIDm; i++) { 4470 if (ser_en_info_list[i].mem == mem) { 4471 *ser_control_reg = ser_en_info_list[i].en_ctrl.flag_reg_mem ? INVALIDr : 4472 ser_en_info_list[i].en_ctrl.ctrl_type.en_reg; 4473 *ser_control_mem = ser_en_info_list[i].en_ctrl.flag_reg_mem ? 4474 ser_en_info_list[i].en_ctrl.ctrl_type.en_mem : 4475 INVALIDm; 4476 *ser_enable_field = ser_en_info_list[i].en_ctrl.en_fld; 4477 return; 4478 } 4479 } 4480 #ifdef BCM_TOMAHAWK2_SUPPORT 4481 if ((SOC_MEM_INFO(unit, mem).flags & SOC_MEM_FLAG_CAM) && 4482 SOC_IS_TOMAHAWK2(unit) && soc_feature(unit, soc_feature_tcam_scan_engine)) { 4483 for (i = 0; _soc_th2_tcam_wrapper_table[i].mem != INVALIDm; i++) { 4484 if (_soc_th2_tcam_wrapper_table[i].mem == mem) { 4485 *ser_control_reg = _soc_th2_tcam_wrapper_table[i].enable_reg; 4486 *ser_enable_field = _soc_th2_tcam_wrapper_table[i].enable_field; 4487 return; /* found */ 4488 } 4489 } 4490 } 4491 #endif 4492 LOG_ERROR(BSL_LS_SOC_SER, 4493 (BSL_META_U(unit, 4494 "unit %d, mem %s reported in ser_fifo but not " 4495 "listed in ip, ep_mem_ser_info list !!\n"), 4496 unit, SOC_MEM_NAME(unit,mem) )); 4497 return; 4498 } 4499 4500 STATIC void 4501 _soc_th_mem_parity_info(int unit, int block_info_idx, int pipe, 4502 soc_field_t field_enum, uint32 *minfo) 4503 { 4504 *minfo = (SOC_BLOCK2SCH(unit, block_info_idx) << SOC_ERROR_BLK_BP) 4505 | ((pipe & 0xff) << SOC_ERROR_PIPE_BP) 4506 | (field_enum & SOC_ERROR_FIELD_ENUM_MASK); 4507 } 4508 4509 STATIC int 4510 _soc_th_mem_has_ecc(int unit, soc_mem_t mem) 4511 { 4512 if (SOC_MEM_FIELD_VALID(unit, mem, ECCf) || 4513 SOC_MEM_FIELD_VALID(unit, mem, ECC0f) || 4514 SOC_MEM_FIELD_VALID(unit, mem, ECC_0f) || 4515 (SOC_MEM_INFO(unit, mem).flags & SOC_MEM_FLAG_SER_ECC_CORRECTABLE)) { 4516 return 1; 4517 } 4518 return 0; 4519 } 4520 4521 STATIC int 4522 _soc_th_mem_is_dyn(int unit, soc_mem_t mem) 4523 { 4524 int rv = 0; /* mem is not dynamic */ 4525 /* 4526 * 4527 if (SOC_MEM_FIELD_VALID(unit, mem, HITf) || 4528 SOC_MEM_FIELD_VALID(unit, mem, HIT0f) || 4529 SOC_MEM_FIELD_VALID(unit, mem, HIT_0f) || 4530 SOC_MEM_FIELD_VALID(unit, mem, HITDA_0f) || 4531 SOC_MEM_FIELD_VALID(unit, mem, HITSA_0f) || 4532 SOC_MEM_FIELD_VALID(unit, mem, HITSAf) || 4533 SOC_MEM_FIELD_VALID(unit, mem, HITDAf) || 4534 SOC_MEM_FIELD_VALID(unit, mem, MY_STATION_HITf)) { 4535 return 1; 4536 } 4537 */ 4538 switch (mem) { 4539 case IFP_METER_TABLEm: 4540 case EFP_METER_TABLEm: 4541 case FP_STORM_CONTROL_METERSm: 4542 rv = 1; break; 4543 default: 4544 /* 4545 * Cannot use following, because FLAG_DYNAMIC will be set by esw/drv.c 4546 * for any mem which contains PARITY, ECC, HIT bits 4547 * if (SOC_MEM_INFO(unit, mem).flags & SOC_MEM_FLAG_DYNAMIC) { 4548 * rv = 1; break; 4549 * } 4550 */ 4551 if ((SOC_MEM_INFO(unit, mem).flags & SOC_MEM_FLAG_SER_ENTRY_CLEAR) || 4552 !(SOC_MEM_SER_CORRECTION_TYPE(unit, mem))) { 4553 /* 1st term means mem is dynamic - eg: counter */ 4554 /* 2nd term means sw cannot restore this - so mem must be dyn */ 4555 rv = 1; 4556 } else { 4557 rv = 0; 4558 } 4559 break; 4560 } 4561 if (rv) { 4562 LOG_VERBOSE(BSL_LS_SOC_SER, 4563 (BSL_META_U(unit, 4564 "unit %d, mem %s is dynamic - so read of corrupted" 4565 " entry will be skipped !!\n"), 4566 unit, SOC_MEM_NAME(unit, mem))); 4567 } 4568 return rv; 4569 } 4570 4571 STATIC int 4572 _soc_thx_mem_log_content_skip(int unit, soc_mem_t mem){ 4573 soc_mem_t *mem_list = NULL; 4574 int i = 0; 4575 4576 #ifdef BCM_TOMAHAWK3_SUPPORT 4577 if (SOC_IS_TOMAHAWK3(unit)) { 4578 mem_list = _soc_th3_skip_populating; 4579 } else 4580 #endif 4581 #ifdef BCM_TOMAHAWK2_SUPPORT 4582 if (SOC_IS_TOMAHAWK2(unit)) { 4583 mem_list = _soc_th2_skip_populating; 4584 } else 4585 #endif 4586 #ifdef BCM_TOMAHAWKPLUS_SUPPORT 4587 if (SOC_IS_TOMAHAWKPLUS(unit)) { 4588 mem_list = _soc_thp_skip_populating; 4589 } else 4590 #endif 4591 { 4592 mem_list = _soc_th_skip_populating; 4593 } 4594 4595 i = 0; 4596 while(mem_list[i] != INVALIDm) { 4597 if (mem == mem_list[i]) { 4598 return TRUE; 4599 } 4600 i++; 4601 } 4602 4603 return FALSE; 4604 } 4605 4606 STATIC int 4607 _soc_th_populate_ser_log(int unit, soc_reg_t parity_enable_reg, 4608 soc_mem_t parity_enable_mem, 4609 soc_field_t parity_enable_field, 4610 soc_mem_t mem, 4611 int mem_block, 4612 int pipe_num, 4613 int index, 4614 sal_usecs_t detect_time, 4615 uint32 sblk, 4616 uint32 address, 4617 int disable_parity, 4618 int disable_mem_read, 4619 int disable_fill_cache_log, 4620 int force_cache_log, 4621 int is_physical_index, 4622 uint32 hwbase) 4623 { 4624 uint32 tmp_entry[SOC_MAX_MEM_WORDS]; 4625 int log_entry_size, id, entry_dw; 4626 uint32 *cache; 4627 uint32 flags = SOC_MEM_NO_FLAGS; 4628 uint8 *vmap; 4629 soc_ser_log_tlv_memory_t log_mem; 4630 soc_ser_log_tlv_generic_t log_generic; 4631 int final_disable_parity = 0; 4632 int final_disable_mem_read = 0; 4633 int rv; 4634 4635 sal_memset(&log_generic, 0, sizeof(log_generic)); 4636 sal_memset(&log_mem, 0, sizeof(log_mem)); 4637 sal_memset(tmp_entry, 0, sizeof(tmp_entry)); 4638 4639 /* 4640 must be large enough for at least generic and terminator, as well as the 4641 memory type since we might decode it in soc_ser_correction. 4642 */ 4643 log_entry_size = sizeof(soc_ser_log_tlv_hdr_t)*3 + 4644 sizeof(soc_ser_log_tlv_generic_t) + 4645 sizeof(soc_ser_log_tlv_memory_t); 4646 4647 if (mem != INVALIDm) { 4648 final_disable_mem_read = disable_mem_read || 4649 _soc_th_mem_is_dyn(unit, mem) || 4650 _soc_thx_mem_log_content_skip(unit, mem) || 4651 ((parity_enable_reg == INVALIDr) && 4652 (parity_enable_mem == INVALIDm)) || 4653 (parity_enable_field == INVALIDf); 4654 4655 final_disable_parity = (!final_disable_mem_read) && 4656 disable_parity; /* over-ride if necessary */ 4657 4658 /* Check to make sure this isn't a duplicate */ 4659 /* Search for a log entry with the same mem, and index with within 4660 * the last 5 seconds */ 4661 rv = soc_ser_log_find_recent(unit, mem, index, sal_time_usecs()); 4662 if (rv > 0) { 4663 LOG_VERBOSE(BSL_LS_SOC_SER, 4664 (BSL_META_U(unit, 4665 "unit %d, ser_logging was skipped for mem %s " 4666 "- too close to similar event !!\n"), 4667 unit, SOC_MEM_NAME(unit, mem))); 4668 return rv; 4669 } 4670 4671 entry_dw = soc_mem_entry_words(unit, mem); 4672 log_entry_size += sizeof(soc_ser_log_tlv_hdr_t) + entry_dw*4; 4673 4674 if (sblk) { 4675 SOC_MEM_BLOCK_ITER(unit, mem, mem_block) { 4676 if (SOC_BLOCK2OFFSET(unit, mem_block) == sblk) { 4677 break; 4678 } 4679 } 4680 } else { 4681 mem_block = SOC_MEM_BLOCK_ANY(unit, mem); 4682 } 4683 4684 cache = SOC_MEM_STATE(unit, mem).cache[mem_block]; 4685 vmap = SOC_MEM_STATE(unit, mem).vmap[mem_block]; 4686 if ((cache != NULL && CACHE_VMAP_TST(vmap, index)) || 4687 force_cache_log) { 4688 log_entry_size += sizeof(soc_ser_log_tlv_hdr_t) + entry_dw*4; 4689 } 4690 4691 /* create the entry based on determined size, save id */ 4692 id = soc_ser_log_create_entry(unit, log_entry_size); 4693 if (id == 0) { 4694 return id; 4695 } 4696 4697 /* Add the memory information to the log now so we can detect duplicate errors */ 4698 log_generic.time = detect_time; 4699 log_mem.memory = mem; 4700 log_mem.index = index; 4701 soc_ser_log_add_tlv(unit, id, SOC_SER_LOG_TLV_MEMORY, 4702 sizeof(soc_ser_log_tlv_memory_t), &log_mem); 4703 soc_ser_log_add_tlv(unit, id, SOC_SER_LOG_TLV_GENERIC, 4704 sizeof(soc_ser_log_tlv_generic_t), &log_generic); 4705 4706 /* If we have decoded the memory we can record its contents 4707 * (which can help with analysis with nature of the error 4708 */ 4709 if (final_disable_parity) { 4710 #ifdef BCM_TOMAHAWK3_SUPPORT 4711 if (SOC_IS_TOMAHAWK3(unit)) { 4712 if (soc_tomahawk3_parity_bit_enable(unit, parity_enable_reg, 4713 parity_enable_mem, 4714 parity_enable_field, 4715 -1, 0) < 0) { 4716 return 0; 4717 } 4718 } else 4719 #endif 4720 { 4721 if (soc_reg_field32_modify(unit, parity_enable_reg, 4722 REG_PORT_ANY, parity_enable_field, 0) < 0) { 4723 return 0; 4724 } 4725 } 4726 } 4727 4728 /* read the memory into a buffer */ 4729 if (!final_disable_mem_read) { 4730 if (is_physical_index) { 4731 flags = SOC_MEM_DONT_MAP_INDEX; 4732 } 4733 if ((pipe_num >= 0) && (pipe_num < NUM_PIPE(unit))) { 4734 soc_mem_pipe_select_read(unit, flags, mem, mem_block, 4735 pipe_num, index, tmp_entry); 4736 } else { 4737 /*Enable NACK on read */ 4738 flags |= SOC_MEM_DONT_USE_CACHE | SOC_MEM_SCHAN_ERR_RETURN; 4739 soc_mem_read_extended(unit, 4740 flags, 4741 mem, 0, mem_block, 4742 index, tmp_entry); 4743 } 4744 } 4745 4746 /* Re_enable Parity */ 4747 if (final_disable_parity) { 4748 #ifdef BCM_TOMAHAWK3_SUPPORT 4749 if (SOC_IS_TOMAHAWK3(unit)) { 4750 if (soc_tomahawk3_parity_bit_enable(unit, parity_enable_reg, 4751 parity_enable_mem, 4752 parity_enable_field, 4753 -1, 1) < 0) { 4754 return 0; 4755 } 4756 } else 4757 #endif 4758 { 4759 if (soc_reg_field32_modify(unit, parity_enable_reg, 4760 REG_PORT_ANY, parity_enable_field, 1) < 0) { 4761 return 0; 4762 } 4763 } 4764 } 4765 4766 /* fill in the memory contents tlv */ 4767 if (!final_disable_mem_read) { 4768 if (soc_ser_log_add_tlv(unit, id, SOC_SER_LOG_TLV_CONTENTS, 4769 entry_dw*4, tmp_entry) < 0) { 4770 return 0; 4771 } 4772 } 4773 4774 if (cache != NULL && CACHE_VMAP_TST(vmap, index) && 4775 !disable_fill_cache_log) { 4776 /* fill in the memory cache tlv */ 4777 if (soc_ser_log_add_tlv(unit, id, SOC_SER_LOG_TLV_CACHE, 4778 entry_dw*4, (cache + index*entry_dw)) < 0) { 4779 return 0; 4780 } 4781 } 4782 } else { 4783 /* create the entry based on determined size, save id */ 4784 id = soc_ser_log_create_entry(unit, log_entry_size); 4785 if (id == 0) { 4786 return id; 4787 } 4788 log_mem.memory = mem; 4789 log_mem.index = index; 4790 log_mem.hwbase = hwbase; 4791 soc_ser_log_add_tlv(unit, id, SOC_SER_LOG_TLV_MEMORY, 4792 sizeof(soc_ser_log_tlv_memory_t), &log_mem); 4793 } 4794 return id; 4795 } 4796 4797 STATIC int 4798 _soc_add_log_generic(int unit, _soc_ser_correct_info_t *spci) 4799 { 4800 4801 if (spci->log_id != 0) { 4802 soc_ser_log_tlv_generic_t log_generic; 4803 4804 /* Add the memory information to the log now so we can detect duplicate errors */ 4805 log_generic.flags = 0; 4806 if (spci->flags & SOC_SER_ERR_CPU) { 4807 log_generic.flags |= SOC_SER_LOG_FLAG_ERR_SRC; 4808 } 4809 if (spci->flags & SOC_SER_ERR_MULTI) { 4810 log_generic.flags |= SOC_SER_LOG_FLAG_MULTIBIT; 4811 } 4812 if (spci->double_bit != 0) { 4813 log_generic.flags |= SOC_SER_LOG_FLAG_DOUBLEBIT; 4814 } 4815 log_generic.boot_count = soc_ser_log_get_boot_count(unit); 4816 log_generic.address = spci->addr; 4817 log_generic.acc_type = spci->acc_type; 4818 log_generic.block_type = spci->blk_type; 4819 log_generic.parity_type = spci->parity_type; 4820 log_generic.ser_response_flag = 0; 4821 log_generic.corrected = SOC_SER_UNCORRECTED; 4822 log_generic.pipe_num = spci->pipe_num; 4823 log_generic.time = spci->detect_time; 4824 4825 soc_ser_log_add_tlv(unit, spci->log_id, SOC_SER_LOG_TLV_GENERIC, 4826 sizeof(soc_ser_log_tlv_generic_t), &log_generic); 4827 4828 return SOC_E_NONE; 4829 } 4830 return SOC_E_FAIL; 4831 } 4832 4833 STATIC int 4834 _soc_th_ser_reg32_get(int unit, soc_reg_t reg, int port, int index, 4835 uint32 *data, int mmu_base_index) 4836 { 4837 int block_num = mmu_base_index; 4838 int base_type_index = mmu_base_index; 4839 soc_block_t blocktype = *SOC_REG_INFO(unit, reg).block; 4840 switch (blocktype) { 4841 case SOC_BLK_MMU_XPE: 4842 return soc_tomahawk_xpe_reg32_get(unit, reg, block_num, 4843 base_type_index, index, data); 4844 case SOC_BLK_MMU_SC: 4845 return soc_tomahawk_sc_reg32_get(unit, reg, block_num, 4846 base_type_index, index, data); 4847 #ifdef BCM_TOMAHAWK2_SUPPORT 4848 case SOC_BLK_MMU_SED: 4849 return soc_tomahawk2_sed_reg32_get(unit, reg, block_num, 4850 base_type_index, index, data); 4851 #endif 4852 #ifdef BCM_TOMAHAWK3_SUPPORT 4853 case SOC_BLK_MMU_ITM: 4854 return soc_tomahawk3_itm_reg32_get(unit, reg, block_num, 4855 base_type_index, index, data); 4856 case SOC_BLK_MMU_EB: 4857 return soc_tomahawk3_eb_reg32_get(unit, reg, block_num, 4858 base_type_index, index, data); 4859 #endif 4860 default: 4861 return soc_reg32_get(unit, reg, port, index, data); 4862 } 4863 } 4864 4865 STATIC int 4866 _soc_th_ser_reg32_set(int unit, soc_reg_t reg, int port, int index, 4867 uint32 data, int mmu_base_index) 4868 { 4869 int block_num = mmu_base_index; 4870 int base_type_index = mmu_base_index; 4871 soc_block_t blocktype = *SOC_REG_INFO(unit, reg).block; 4872 switch (blocktype) { 4873 case SOC_BLK_MMU_XPE: 4874 return soc_tomahawk_xpe_reg32_set(unit, reg, block_num, 4875 base_type_index, index, data); 4876 case SOC_BLK_MMU_SC: 4877 return soc_tomahawk_sc_reg32_set(unit, reg, block_num, 4878 base_type_index, index, data); 4879 #ifdef BCM_TOMAHAWK2_SUPPORT 4880 case SOC_BLK_MMU_SED: 4881 return soc_tomahawk2_sed_reg32_set(unit, reg, block_num, 4882 base_type_index, index, data); 4883 #endif 4884 #ifdef BCM_TOMAHAWK3_SUPPORT 4885 case SOC_BLK_MMU_ITM: 4886 return soc_tomahawk3_itm_reg32_set(unit, reg, block_num, 4887 base_type_index, index, data); 4888 case SOC_BLK_MMU_EB: 4889 return soc_tomahawk3_eb_reg32_set(unit, reg, block_num, 4890 base_type_index, index, data); 4891 #endif 4892 default: 4893 return soc_reg32_set(unit, reg, port, index, data); 4894 } 4895 } 4896 4897 int 4898 soc_th_ser_reg_field32_modify(int unit, soc_reg_t reg, soc_port_t port, 4899 soc_field_t field, uint32 value, 4900 int index, int mmu_base_index) 4901 { 4902 uint32 rval; 4903 4904 SOC_IF_ERROR_RETURN 4905 (_soc_th_ser_reg32_get(unit, reg, port, index, &rval, mmu_base_index)); 4906 soc_reg_field_set(unit, reg, &rval, field, value); 4907 SOC_IF_ERROR_RETURN 4908 (_soc_th_ser_reg32_set(unit, reg, port, index, rval, mmu_base_index)); 4909 return SOC_E_NONE; 4910 } 4911 4912 STATIC int 4913 _soc_th_ser_reg_get(int unit, soc_reg_t reg, int port, int index, 4914 uint64 *data, int mmu_base_index) 4915 { 4916 int block_num = mmu_base_index; 4917 int base_type_index = mmu_base_index; 4918 soc_block_t blocktype = *SOC_REG_INFO(unit, reg).block; 4919 switch (blocktype) { 4920 case SOC_BLK_MMU_XPE: 4921 return soc_tomahawk_xpe_reg_get(unit, reg, block_num, 4922 base_type_index, index, data); 4923 case SOC_BLK_MMU_SC: 4924 return soc_tomahawk_sc_reg_get(unit, reg, block_num, 4925 base_type_index, index, data); 4926 #ifdef BCM_TOMAHAWK2_SUPPORT 4927 case SOC_BLK_MMU_SED: 4928 return soc_tomahawk2_sed_reg_get(unit, reg, block_num, 4929 base_type_index, index, data); 4930 #endif 4931 #ifdef BCM_TOMAHAWK3_SUPPORT 4932 case SOC_BLK_MMU_ITM: 4933 return soc_tomahawk3_itm_reg_get(unit, reg, block_num, 4934 base_type_index, index, data); 4935 case SOC_BLK_MMU_EB: 4936 return soc_tomahawk3_eb_reg_get(unit, reg, block_num, 4937 base_type_index, index, data); 4938 #endif 4939 default: 4940 return soc_reg_get(unit, reg, port, index, data); 4941 } 4942 } 4943 4944 STATIC int 4945 _soc_th_ser_reg_set(int unit, soc_reg_t reg, int port, int index, 4946 uint64 data, int mmu_base_index) 4947 { 4948 int block_num = mmu_base_index; 4949 int base_type_index = mmu_base_index; 4950 soc_block_t blocktype = *SOC_REG_INFO(unit, reg).block; 4951 switch (blocktype) { 4952 case SOC_BLK_MMU_XPE: 4953 return soc_tomahawk_xpe_reg_set(unit, reg, block_num, 4954 base_type_index, index, data); 4955 case SOC_BLK_MMU_SC: 4956 return soc_tomahawk_sc_reg_set(unit, reg, block_num, 4957 base_type_index, index, data); 4958 #ifdef BCM_TOMAHAWK2_SUPPORT 4959 case SOC_BLK_MMU_SED: 4960 return soc_tomahawk2_sed_reg_set(unit, reg, block_num, 4961 base_type_index, index, data); 4962 #endif 4963 #ifdef BCM_TOMAHAWK3_SUPPORT 4964 case SOC_BLK_MMU_ITM: 4965 return soc_tomahawk3_itm_reg_set(unit, reg, block_num, 4966 base_type_index, index, data); 4967 case SOC_BLK_MMU_EB: 4968 return soc_tomahawk3_eb_reg_set(unit, reg, block_num, 4969 base_type_index, index, data); 4970 #endif 4971 default: 4972 return soc_reg_set(unit, reg, port, index, data); 4973 } 4974 } 4975 4976 int 4977 soc_th_ser_reg_field_modify(int unit, soc_reg_t reg, soc_port_t port, 4978 soc_field_t field, uint32 value, 4979 int index, int mmu_base_index) 4980 { 4981 uint64 rval; 4982 4983 COMPILER_64_ZERO(rval); 4984 SOC_IF_ERROR_RETURN 4985 (_soc_th_ser_reg_get(unit, reg, port, index, &rval, mmu_base_index)); 4986 soc_reg64_field32_set(unit, reg, &rval, field, value); 4987 SOC_IF_ERROR_RETURN 4988 (_soc_th_ser_reg_set(unit, reg, port, index, rval, mmu_base_index)); 4989 return SOC_E_NONE; 4990 } 4991 4992 STATIC int 4993 _soc_tomahawk_ser_mmu_mem_remap(_soc_ser_correct_info_t *spci) 4994 { 4995 if (spci == NULL) { 4996 return SOC_E_PARAM; 4997 } 4998 4999 /* LHS views are physical views of mem instances which encounter error and 5000 * are thus reported by HW. 5001 * 5002 * RHS views are logical views for which SW maintains cache and does 5003 * ser_correction writes. 5004 * 5005 * remap function thus maps physical mem views to logical mem views. 5006 */ 5007 5008 switch (spci->mem) { 5009 /* WRED */ 5010 case MMU_WRED_DROP_CURVE_PROFILE_0_Am: 5011 case MMU_WRED_DROP_CURVE_PROFILE_0_Bm: 5012 spci->mem = MMU_WRED_DROP_CURVE_PROFILE_0m; break; 5013 case MMU_WRED_DROP_CURVE_PROFILE_1_Am: 5014 case MMU_WRED_DROP_CURVE_PROFILE_1_Bm: 5015 spci->mem = MMU_WRED_DROP_CURVE_PROFILE_1m; break; 5016 case MMU_WRED_DROP_CURVE_PROFILE_2_Am: 5017 case MMU_WRED_DROP_CURVE_PROFILE_2_Bm: 5018 spci->mem = MMU_WRED_DROP_CURVE_PROFILE_2m; break; 5019 case MMU_WRED_DROP_CURVE_PROFILE_3_Am: 5020 case MMU_WRED_DROP_CURVE_PROFILE_3_Bm: 5021 spci->mem = MMU_WRED_DROP_CURVE_PROFILE_3m; break; 5022 case MMU_WRED_DROP_CURVE_PROFILE_4_Am: 5023 case MMU_WRED_DROP_CURVE_PROFILE_4_Bm: 5024 spci->mem = MMU_WRED_DROP_CURVE_PROFILE_4m; break; 5025 case MMU_WRED_DROP_CURVE_PROFILE_5_Am: 5026 case MMU_WRED_DROP_CURVE_PROFILE_5_Bm: 5027 spci->mem = MMU_WRED_DROP_CURVE_PROFILE_5m; break; 5028 case MMU_WRED_DROP_CURVE_PROFILE_6_Am: 5029 case MMU_WRED_DROP_CURVE_PROFILE_6_Bm: 5030 spci->mem = MMU_WRED_DROP_CURVE_PROFILE_6m; break; 5031 case MMU_WRED_DROP_CURVE_PROFILE_7_Am: 5032 case MMU_WRED_DROP_CURVE_PROFILE_7_Bm: 5033 spci->mem = MMU_WRED_DROP_CURVE_PROFILE_7m; break; 5034 case MMU_WRED_DROP_CURVE_PROFILE_8_Am: 5035 case MMU_WRED_DROP_CURVE_PROFILE_8_Bm: 5036 spci->mem = MMU_WRED_DROP_CURVE_PROFILE_8m; break; 5037 5038 5039 /* THDU */ 5040 case MMU_THDU_RESUME_PORT0_PIPE0m: 5041 case MMU_THDU_RESUME_PORT1_PIPE0m: 5042 case MMU_THDU_RESUME_PORT2_PIPE0m: 5043 spci->mem = MMU_THDU_RESUME_PORT_PIPE0m; break; 5044 case MMU_THDU_RESUME_PORT0_PIPE1m: 5045 case MMU_THDU_RESUME_PORT1_PIPE1m: 5046 case MMU_THDU_RESUME_PORT2_PIPE1m: 5047 spci->mem = MMU_THDU_RESUME_PORT_PIPE1m; break; 5048 case MMU_THDU_RESUME_PORT0_PIPE2m: 5049 case MMU_THDU_RESUME_PORT1_PIPE2m: 5050 case MMU_THDU_RESUME_PORT2_PIPE2m: 5051 spci->mem = MMU_THDU_RESUME_PORT_PIPE2m; break; 5052 case MMU_THDU_RESUME_PORT0_PIPE3m: 5053 case MMU_THDU_RESUME_PORT1_PIPE3m: 5054 case MMU_THDU_RESUME_PORT2_PIPE3m: 5055 spci->mem = MMU_THDU_RESUME_PORT_PIPE3m; break; 5056 5057 case MMU_THDU_CONFIG_PORT0_PIPE0m: 5058 case MMU_THDU_CONFIG_PORT1_PIPE0m: 5059 spci->mem = MMU_THDU_CONFIG_PORT_PIPE0m; break; 5060 case MMU_THDU_CONFIG_PORT0_PIPE1m: 5061 case MMU_THDU_CONFIG_PORT1_PIPE1m: 5062 spci->mem = MMU_THDU_CONFIG_PORT_PIPE1m; break; 5063 case MMU_THDU_CONFIG_PORT0_PIPE2m: 5064 case MMU_THDU_CONFIG_PORT1_PIPE2m: 5065 spci->mem = MMU_THDU_CONFIG_PORT_PIPE2m; break; 5066 case MMU_THDU_CONFIG_PORT0_PIPE3m: 5067 case MMU_THDU_CONFIG_PORT1_PIPE3m: 5068 spci->mem = MMU_THDU_CONFIG_PORT_PIPE3m; break; 5069 5070 case MMU_THDU_CONFIG_QGROUP0_PIPE0m: 5071 case MMU_THDU_CONFIG_QGROUP1_PIPE0m: 5072 spci->mem = MMU_THDU_CONFIG_QGROUP_PIPE0m; break; 5073 case MMU_THDU_CONFIG_QGROUP0_PIPE1m: 5074 case MMU_THDU_CONFIG_QGROUP1_PIPE1m: 5075 spci->mem = MMU_THDU_CONFIG_QGROUP_PIPE1m; break; 5076 case MMU_THDU_CONFIG_QGROUP0_PIPE2m: 5077 case MMU_THDU_CONFIG_QGROUP1_PIPE2m: 5078 spci->mem = MMU_THDU_CONFIG_QGROUP_PIPE2m; break; 5079 case MMU_THDU_CONFIG_QGROUP0_PIPE3m: 5080 case MMU_THDU_CONFIG_QGROUP1_PIPE3m: 5081 spci->mem = MMU_THDU_CONFIG_QGROUP_PIPE3m; break; 5082 5083 case MMU_THDU_OFFSET_QGROUP0_PIPE0m: 5084 case MMU_THDU_OFFSET_QGROUP1_PIPE0m: 5085 spci->mem = MMU_THDU_OFFSET_QGROUP_PIPE0m; break; 5086 case MMU_THDU_OFFSET_QGROUP0_PIPE1m: 5087 case MMU_THDU_OFFSET_QGROUP1_PIPE1m: 5088 spci->mem = MMU_THDU_OFFSET_QGROUP_PIPE1m; break; 5089 case MMU_THDU_OFFSET_QGROUP0_PIPE2m: 5090 case MMU_THDU_OFFSET_QGROUP1_PIPE2m: 5091 spci->mem = MMU_THDU_OFFSET_QGROUP_PIPE2m; break; 5092 case MMU_THDU_OFFSET_QGROUP0_PIPE3m: 5093 case MMU_THDU_OFFSET_QGROUP1_PIPE3m: 5094 spci->mem = MMU_THDU_OFFSET_QGROUP_PIPE3m; break; 5095 5096 case MMU_THDU_CONFIG_QUEUE0_PIPE0m: 5097 case MMU_THDU_CONFIG_QUEUE1_PIPE0m: 5098 spci->mem = MMU_THDU_CONFIG_QUEUE_PIPE0m; break; 5099 case MMU_THDU_CONFIG_QUEUE0_PIPE1m: 5100 case MMU_THDU_CONFIG_QUEUE1_PIPE1m: 5101 spci->mem = MMU_THDU_CONFIG_QUEUE_PIPE1m; break; 5102 case MMU_THDU_CONFIG_QUEUE0_PIPE2m: 5103 case MMU_THDU_CONFIG_QUEUE1_PIPE2m: 5104 spci->mem = MMU_THDU_CONFIG_QUEUE_PIPE2m; break; 5105 case MMU_THDU_CONFIG_QUEUE0_PIPE3m: 5106 case MMU_THDU_CONFIG_QUEUE1_PIPE3m: 5107 spci->mem = MMU_THDU_CONFIG_QUEUE_PIPE3m; break; 5108 5109 case MMU_THDU_OFFSET_QUEUE0_PIPE0m: 5110 case MMU_THDU_OFFSET_QUEUE1_PIPE0m: 5111 spci->mem = MMU_THDU_OFFSET_QUEUE_PIPE0m; break; 5112 case MMU_THDU_OFFSET_QUEUE0_PIPE1m: 5113 case MMU_THDU_OFFSET_QUEUE1_PIPE1m: 5114 spci->mem = MMU_THDU_OFFSET_QUEUE_PIPE1m; break; 5115 case MMU_THDU_OFFSET_QUEUE0_PIPE2m: 5116 case MMU_THDU_OFFSET_QUEUE1_PIPE2m: 5117 spci->mem = MMU_THDU_OFFSET_QUEUE_PIPE2m; break; 5118 case MMU_THDU_OFFSET_QUEUE0_PIPE3m: 5119 case MMU_THDU_OFFSET_QUEUE1_PIPE3m: 5120 spci->mem = MMU_THDU_OFFSET_QUEUE_PIPE3m; break; 5121 5122 case MMU_THDU_Q_TO_QGRP_MAP0_PIPE0m: 5123 case MMU_THDU_Q_TO_QGRP_MAP1_PIPE0m: 5124 case MMU_THDU_Q_TO_QGRP_MAP2_PIPE0m: 5125 spci->mem = MMU_THDU_Q_TO_QGRP_MAP_PIPE0m; break; 5126 case MMU_THDU_Q_TO_QGRP_MAP0_PIPE1m: 5127 case MMU_THDU_Q_TO_QGRP_MAP1_PIPE1m: 5128 case MMU_THDU_Q_TO_QGRP_MAP2_PIPE1m: 5129 spci->mem = MMU_THDU_Q_TO_QGRP_MAP_PIPE1m; break; 5130 case MMU_THDU_Q_TO_QGRP_MAP0_PIPE2m: 5131 case MMU_THDU_Q_TO_QGRP_MAP1_PIPE2m: 5132 case MMU_THDU_Q_TO_QGRP_MAP2_PIPE2m: 5133 spci->mem = MMU_THDU_Q_TO_QGRP_MAP_PIPE2m; break; 5134 case MMU_THDU_Q_TO_QGRP_MAP0_PIPE3m: 5135 case MMU_THDU_Q_TO_QGRP_MAP1_PIPE3m: 5136 case MMU_THDU_Q_TO_QGRP_MAP2_PIPE3m: 5137 spci->mem = MMU_THDU_Q_TO_QGRP_MAP_PIPE3m; break; 5138 5139 5140 /* THDI */ 5141 case THDI_PORT_SP_CONFIG0_PIPE0m: 5142 case THDI_PORT_SP_CONFIG1_PIPE0m: 5143 case THDI_PORT_SP_CONFIG2_PIPE0m: 5144 spci->mem = THDI_PORT_SP_CONFIG_PIPE0m; break; 5145 case THDI_PORT_SP_CONFIG0_PIPE1m: 5146 case THDI_PORT_SP_CONFIG1_PIPE1m: 5147 case THDI_PORT_SP_CONFIG2_PIPE1m: 5148 spci->mem = THDI_PORT_SP_CONFIG_PIPE1m; break; 5149 case THDI_PORT_SP_CONFIG0_PIPE2m: 5150 case THDI_PORT_SP_CONFIG1_PIPE2m: 5151 case THDI_PORT_SP_CONFIG2_PIPE2m: 5152 spci->mem = THDI_PORT_SP_CONFIG_PIPE2m; break; 5153 case THDI_PORT_SP_CONFIG0_PIPE3m: 5154 case THDI_PORT_SP_CONFIG1_PIPE3m: 5155 case THDI_PORT_SP_CONFIG2_PIPE3m: 5156 spci->mem = THDI_PORT_SP_CONFIG_PIPE3m; break; 5157 5158 5159 /* MTRO */ 5160 case MMU_MTRO_EGRMETERINGCONFIG_MEM_A_PIPE0m: 5161 case MMU_MTRO_EGRMETERINGCONFIG_MEM_B_PIPE0m: 5162 spci->mem = MMU_MTRO_EGRMETERINGCONFIG_MEM_PIPE0m; break; 5163 case MMU_MTRO_EGRMETERINGCONFIG_MEM_A_PIPE1m: 5164 case MMU_MTRO_EGRMETERINGCONFIG_MEM_B_PIPE1m: 5165 spci->mem = MMU_MTRO_EGRMETERINGCONFIG_MEM_PIPE1m; break; 5166 case MMU_MTRO_EGRMETERINGCONFIG_MEM_A_PIPE2m: 5167 case MMU_MTRO_EGRMETERINGCONFIG_MEM_B_PIPE2m: 5168 spci->mem = MMU_MTRO_EGRMETERINGCONFIG_MEM_PIPE2m; break; 5169 case MMU_MTRO_EGRMETERINGCONFIG_MEM_A_PIPE3m: 5170 case MMU_MTRO_EGRMETERINGCONFIG_MEM_B_PIPE3m: 5171 spci->mem = MMU_MTRO_EGRMETERINGCONFIG_MEM_PIPE3m; break; 5172 5173 5174 /* THDM */ 5175 case MMU_THDM_MCQE_QUEUE_CONFIG_A_PIPE0m: 5176 case MMU_THDM_MCQE_QUEUE_CONFIG_B_PIPE0m: 5177 case MMU_THDM_MCQE_QUEUE_CONFIG_C_PIPE0m: 5178 spci->mem = MMU_THDM_MCQE_QUEUE_CONFIG_PIPE0m; break; 5179 case MMU_THDM_MCQE_QUEUE_CONFIG_A_PIPE1m: 5180 case MMU_THDM_MCQE_QUEUE_CONFIG_B_PIPE1m: 5181 case MMU_THDM_MCQE_QUEUE_CONFIG_C_PIPE1m: 5182 spci->mem = MMU_THDM_MCQE_QUEUE_CONFIG_PIPE1m; break; 5183 case MMU_THDM_MCQE_QUEUE_CONFIG_A_PIPE2m: 5184 case MMU_THDM_MCQE_QUEUE_CONFIG_B_PIPE2m: 5185 case MMU_THDM_MCQE_QUEUE_CONFIG_C_PIPE2m: 5186 spci->mem = MMU_THDM_MCQE_QUEUE_CONFIG_PIPE2m; break; 5187 case MMU_THDM_MCQE_QUEUE_CONFIG_A_PIPE3m: 5188 case MMU_THDM_MCQE_QUEUE_CONFIG_B_PIPE3m: 5189 case MMU_THDM_MCQE_QUEUE_CONFIG_C_PIPE3m: 5190 spci->mem = MMU_THDM_MCQE_QUEUE_CONFIG_PIPE3m; break; 5191 5192 case MMU_THDM_DB_QUEUE_CONFIG_A_PIPE0m: 5193 case MMU_THDM_DB_QUEUE_CONFIG_B_PIPE0m: 5194 case MMU_THDM_DB_QUEUE_CONFIG_C_PIPE0m: 5195 spci->mem = MMU_THDM_DB_QUEUE_CONFIG_PIPE0m; break; 5196 case MMU_THDM_DB_QUEUE_CONFIG_A_PIPE1m: 5197 case MMU_THDM_DB_QUEUE_CONFIG_B_PIPE1m: 5198 case MMU_THDM_DB_QUEUE_CONFIG_C_PIPE1m: 5199 spci->mem = MMU_THDM_DB_QUEUE_CONFIG_PIPE1m; break; 5200 case MMU_THDM_DB_QUEUE_CONFIG_A_PIPE2m: 5201 case MMU_THDM_DB_QUEUE_CONFIG_B_PIPE2m: 5202 case MMU_THDM_DB_QUEUE_CONFIG_C_PIPE2m: 5203 spci->mem = MMU_THDM_DB_QUEUE_CONFIG_PIPE2m; break; 5204 case MMU_THDM_DB_QUEUE_CONFIG_A_PIPE3m: 5205 case MMU_THDM_DB_QUEUE_CONFIG_B_PIPE3m: 5206 case MMU_THDM_DB_QUEUE_CONFIG_C_PIPE3m: 5207 spci->mem = MMU_THDM_DB_QUEUE_CONFIG_PIPE3m; break; 5208 5209 case MMU_THDM_MCQE_PORTSP_CONFIG_A_PIPE0m: 5210 case MMU_THDM_MCQE_PORTSP_CONFIG_B_PIPE0m: 5211 case MMU_THDM_MCQE_PORTSP_CONFIG_C_PIPE0m: 5212 spci->mem = MMU_THDM_MCQE_PORTSP_CONFIG_PIPE0m; break; 5213 case MMU_THDM_MCQE_PORTSP_CONFIG_A_PIPE1m: 5214 case MMU_THDM_MCQE_PORTSP_CONFIG_B_PIPE1m: 5215 case MMU_THDM_MCQE_PORTSP_CONFIG_C_PIPE1m: 5216 spci->mem = MMU_THDM_MCQE_PORTSP_CONFIG_PIPE1m; break; 5217 case MMU_THDM_MCQE_PORTSP_CONFIG_A_PIPE2m: 5218 case MMU_THDM_MCQE_PORTSP_CONFIG_B_PIPE2m: 5219 case MMU_THDM_MCQE_PORTSP_CONFIG_C_PIPE2m: 5220 spci->mem = MMU_THDM_MCQE_PORTSP_CONFIG_PIPE2m; break; 5221 case MMU_THDM_MCQE_PORTSP_CONFIG_A_PIPE3m: 5222 case MMU_THDM_MCQE_PORTSP_CONFIG_B_PIPE3m: 5223 case MMU_THDM_MCQE_PORTSP_CONFIG_C_PIPE3m: 5224 spci->mem = MMU_THDM_MCQE_PORTSP_CONFIG_PIPE3m; break; 5225 5226 case MMU_THDM_DB_PORTSP_CONFIG_A_PIPE0m: 5227 case MMU_THDM_DB_PORTSP_CONFIG_B_PIPE0m: 5228 case MMU_THDM_DB_PORTSP_CONFIG_C_PIPE0m: 5229 spci->mem = MMU_THDM_DB_PORTSP_CONFIG_PIPE0m; break; 5230 case MMU_THDM_DB_PORTSP_CONFIG_A_PIPE1m: 5231 case MMU_THDM_DB_PORTSP_CONFIG_B_PIPE1m: 5232 case MMU_THDM_DB_PORTSP_CONFIG_C_PIPE1m: 5233 spci->mem = MMU_THDM_DB_PORTSP_CONFIG_PIPE1m; break; 5234 case MMU_THDM_DB_PORTSP_CONFIG_A_PIPE2m: 5235 case MMU_THDM_DB_PORTSP_CONFIG_B_PIPE2m: 5236 case MMU_THDM_DB_PORTSP_CONFIG_C_PIPE2m: 5237 spci->mem = MMU_THDM_DB_PORTSP_CONFIG_PIPE2m; break; 5238 case MMU_THDM_DB_PORTSP_CONFIG_A_PIPE3m: 5239 case MMU_THDM_DB_PORTSP_CONFIG_B_PIPE3m: 5240 case MMU_THDM_DB_PORTSP_CONFIG_C_PIPE3m: 5241 spci->mem = MMU_THDM_DB_PORTSP_CONFIG_PIPE3m; break; 5242 5243 case MMU_THDM_MCQE_QUEUE_OFFSET_A_PIPE0m: 5244 case MMU_THDM_MCQE_QUEUE_OFFSET_B_PIPE0m: 5245 case MMU_THDM_MCQE_QUEUE_OFFSET_C_PIPE0m: 5246 spci->mem = MMU_THDM_MCQE_QUEUE_OFFSET_PIPE0m; break; 5247 case MMU_THDM_MCQE_QUEUE_OFFSET_A_PIPE1m: 5248 case MMU_THDM_MCQE_QUEUE_OFFSET_B_PIPE1m: 5249 case MMU_THDM_MCQE_QUEUE_OFFSET_C_PIPE1m: 5250 spci->mem = MMU_THDM_MCQE_QUEUE_OFFSET_PIPE1m; break; 5251 case MMU_THDM_MCQE_QUEUE_OFFSET_A_PIPE2m: 5252 case MMU_THDM_MCQE_QUEUE_OFFSET_B_PIPE2m: 5253 case MMU_THDM_MCQE_QUEUE_OFFSET_C_PIPE2m: 5254 spci->mem = MMU_THDM_MCQE_QUEUE_OFFSET_PIPE2m; break; 5255 case MMU_THDM_MCQE_QUEUE_OFFSET_A_PIPE3m: 5256 case MMU_THDM_MCQE_QUEUE_OFFSET_B_PIPE3m: 5257 case MMU_THDM_MCQE_QUEUE_OFFSET_C_PIPE3m: 5258 spci->mem = MMU_THDM_MCQE_QUEUE_OFFSET_PIPE3m; break; 5259 5260 case MMU_THDM_DB_QUEUE_OFFSET_A_PIPE0m: 5261 case MMU_THDM_DB_QUEUE_OFFSET_B_PIPE0m: 5262 case MMU_THDM_DB_QUEUE_OFFSET_C_PIPE0m: 5263 spci->mem = MMU_THDM_DB_QUEUE_OFFSET_PIPE0m; break; 5264 case MMU_THDM_DB_QUEUE_OFFSET_A_PIPE1m: 5265 case MMU_THDM_DB_QUEUE_OFFSET_B_PIPE1m: 5266 case MMU_THDM_DB_QUEUE_OFFSET_C_PIPE1m: 5267 spci->mem = MMU_THDM_DB_QUEUE_OFFSET_PIPE1m; break; 5268 case MMU_THDM_DB_QUEUE_OFFSET_A_PIPE2m: 5269 case MMU_THDM_DB_QUEUE_OFFSET_B_PIPE2m: 5270 case MMU_THDM_DB_QUEUE_OFFSET_C_PIPE2m: 5271 spci->mem = MMU_THDM_DB_QUEUE_OFFSET_PIPE2m; break; 5272 case MMU_THDM_DB_QUEUE_OFFSET_A_PIPE3m: 5273 case MMU_THDM_DB_QUEUE_OFFSET_B_PIPE3m: 5274 case MMU_THDM_DB_QUEUE_OFFSET_C_PIPE3m: 5275 spci->mem = MMU_THDM_DB_QUEUE_OFFSET_PIPE3m; break; 5276 5277 5278 /* RQE */ 5279 case MMU_REPL_GROUP_INITIAL_COPY_COUNT0_SC0m: 5280 case MMU_REPL_GROUP_INITIAL_COPY_COUNT1_SC0m: 5281 spci->mem = MMU_REPL_GROUP_INITIAL_COPY_COUNT_SC0m; break; 5282 5283 case MMU_REPL_GROUP_INITIAL_COPY_COUNT0_SC1m: 5284 case MMU_REPL_GROUP_INITIAL_COPY_COUNT1_SC1m: 5285 spci->mem = MMU_REPL_GROUP_INITIAL_COPY_COUNT_SC1m; break; 5286 5287 #ifdef BCM_TOMAHAWK2_SUPPORT 5288 case TCB_THRESHOLD_PROFILE_MAP_A_XPE0m: 5289 case TCB_THRESHOLD_PROFILE_MAP_B_XPE0m: 5290 spci->mem = TCB_THRESHOLD_PROFILE_MAP_XPE0m; break; 5291 case TCB_THRESHOLD_PROFILE_MAP_A_XPE1m: 5292 case TCB_THRESHOLD_PROFILE_MAP_B_XPE1m: 5293 spci->mem = TCB_THRESHOLD_PROFILE_MAP_XPE1m; break; 5294 case TCB_THRESHOLD_PROFILE_MAP_A_XPE2m: 5295 case TCB_THRESHOLD_PROFILE_MAP_B_XPE2m: 5296 spci->mem = TCB_THRESHOLD_PROFILE_MAP_XPE2m; break; 5297 case TCB_THRESHOLD_PROFILE_MAP_A_XPE3m: 5298 case TCB_THRESHOLD_PROFILE_MAP_B_XPE3m: 5299 spci->mem = TCB_THRESHOLD_PROFILE_MAP_XPE3m; break; 5300 #endif 5301 #ifdef BCM_TOMAHAWK3_SUPPORT 5302 case MMU_MTRO_CPU_L1_Bm: 5303 case MMU_MTRO_CPU_L1_Cm: 5304 spci->mem = MMU_MTRO_CPU_L1_Am; break; 5305 case MMU_MTRO_L0_Bm: 5306 case MMU_MTRO_L0_Cm: 5307 spci->mem = MMU_MTRO_L0_Am; break; 5308 case MMU_MTRO_L0_B_PIPE0m: 5309 case MMU_MTRO_L0_C_PIPE0m: 5310 spci->mem = MMU_MTRO_L0_A_PIPE0m; break; 5311 case MMU_MTRO_L0_B_PIPE1m: 5312 case MMU_MTRO_L0_C_PIPE1m: 5313 spci->mem = MMU_MTRO_L0_A_PIPE1m; break; 5314 case MMU_MTRO_L0_B_PIPE2m: 5315 case MMU_MTRO_L0_C_PIPE2m: 5316 spci->mem = MMU_MTRO_L0_A_PIPE2m; break; 5317 case MMU_MTRO_L0_B_PIPE3m: 5318 case MMU_MTRO_L0_C_PIPE3m: 5319 spci->mem = MMU_MTRO_L0_A_PIPE3m; break; 5320 case MMU_MTRO_L0_B_PIPE4m: 5321 case MMU_MTRO_L0_C_PIPE4m: 5322 spci->mem = MMU_MTRO_L0_A_PIPE4m; break; 5323 case MMU_MTRO_L0_B_PIPE5m: 5324 case MMU_MTRO_L0_C_PIPE5m: 5325 spci->mem = MMU_MTRO_L0_A_PIPE5m; break; 5326 case MMU_MTRO_L0_B_PIPE6m: 5327 case MMU_MTRO_L0_C_PIPE6m: 5328 spci->mem = MMU_MTRO_L0_A_PIPE6m; break; 5329 case MMU_MTRO_L0_B_PIPE7m: 5330 case MMU_MTRO_L0_C_PIPE7m: 5331 spci->mem = MMU_MTRO_L0_A_PIPE7m; break; 5332 case MMU_THDI_PORT_PG_MIN_CONFIG1m: 5333 spci->mem = MMU_THDI_PORT_PG_MIN_CONFIGm; break; 5334 case MMU_THDI_PORT_PG_MIN_CONFIG1_PIPE0m: 5335 spci->mem = MMU_THDI_PORT_PG_MIN_CONFIG_PIPE0m; break; 5336 case MMU_THDI_PORT_PG_MIN_CONFIG1_PIPE1m: 5337 spci->mem = MMU_THDI_PORT_PG_MIN_CONFIG_PIPE1m; break; 5338 case MMU_THDI_PORT_PG_MIN_CONFIG1_PIPE2m: 5339 spci->mem = MMU_THDI_PORT_PG_MIN_CONFIG_PIPE2m; break; 5340 case MMU_THDI_PORT_PG_MIN_CONFIG1_PIPE3m: 5341 spci->mem = MMU_THDI_PORT_PG_MIN_CONFIG_PIPE3m; break; 5342 case MMU_THDI_PORT_PG_MIN_CONFIG1_PIPE4m: 5343 spci->mem = MMU_THDI_PORT_PG_MIN_CONFIG_PIPE4m; break; 5344 case MMU_THDI_PORT_PG_MIN_CONFIG1_PIPE5m: 5345 spci->mem = MMU_THDI_PORT_PG_MIN_CONFIG_PIPE5m; break; 5346 case MMU_THDI_PORT_PG_MIN_CONFIG1_PIPE6m: 5347 spci->mem = MMU_THDI_PORT_PG_MIN_CONFIG_PIPE6m; break; 5348 case MMU_THDI_PORT_PG_MIN_CONFIG1_PIPE7m: 5349 spci->mem = MMU_THDI_PORT_PG_MIN_CONFIG_PIPE7m; break; 5350 case MMU_THDI_PORT_PG_SHARED_CONFIG1m: 5351 spci->mem = MMU_THDI_PORT_PG_SHARED_CONFIGm; break; 5352 case MMU_THDI_PORT_PG_SHARED_CONFIG1_PIPE0m: 5353 spci->mem = MMU_THDI_PORT_PG_SHARED_CONFIG_PIPE0m; break; 5354 case MMU_THDI_PORT_PG_SHARED_CONFIG1_PIPE1m: 5355 spci->mem = MMU_THDI_PORT_PG_SHARED_CONFIG_PIPE1m; break; 5356 case MMU_THDI_PORT_PG_SHARED_CONFIG1_PIPE2m: 5357 spci->mem = MMU_THDI_PORT_PG_SHARED_CONFIG_PIPE2m; break; 5358 case MMU_THDI_PORT_PG_SHARED_CONFIG1_PIPE3m: 5359 spci->mem = MMU_THDI_PORT_PG_SHARED_CONFIG_PIPE3m; break; 5360 case MMU_THDI_PORT_PG_SHARED_CONFIG1_PIPE4m: 5361 spci->mem = MMU_THDI_PORT_PG_SHARED_CONFIG_PIPE4m; break; 5362 case MMU_THDI_PORT_PG_SHARED_CONFIG1_PIPE5m: 5363 spci->mem = MMU_THDI_PORT_PG_SHARED_CONFIG_PIPE5m; break; 5364 case MMU_THDI_PORT_PG_SHARED_CONFIG1_PIPE6m: 5365 spci->mem = MMU_THDI_PORT_PG_SHARED_CONFIG_PIPE6m; break; 5366 case MMU_THDI_PORT_PG_SHARED_CONFIG1_PIPE7m: 5367 spci->mem = MMU_THDI_PORT_PG_SHARED_CONFIG_PIPE7m; break; 5368 case MMU_THDI_PORT_PG_RESUME_CONFIG1m: 5369 spci->mem = MMU_THDI_PORT_PG_RESUME_CONFIGm; break; 5370 case MMU_THDI_PORT_PG_RESUME_CONFIG1_PIPE0m: 5371 spci->mem = MMU_THDI_PORT_PG_RESUME_CONFIG_PIPE0m; break; 5372 case MMU_THDI_PORT_PG_RESUME_CONFIG1_PIPE1m: 5373 spci->mem = MMU_THDI_PORT_PG_RESUME_CONFIG_PIPE1m; break; 5374 case MMU_THDI_PORT_PG_RESUME_CONFIG1_PIPE2m: 5375 spci->mem = MMU_THDI_PORT_PG_RESUME_CONFIG_PIPE2m; break; 5376 case MMU_THDI_PORT_PG_RESUME_CONFIG1_PIPE3m: 5377 spci->mem = MMU_THDI_PORT_PG_RESUME_CONFIG_PIPE3m; break; 5378 case MMU_THDI_PORT_PG_RESUME_CONFIG1_PIPE4m: 5379 spci->mem = MMU_THDI_PORT_PG_RESUME_CONFIG_PIPE4m; break; 5380 case MMU_THDI_PORT_PG_RESUME_CONFIG1_PIPE5m: 5381 spci->mem = MMU_THDI_PORT_PG_RESUME_CONFIG_PIPE5m; break; 5382 case MMU_THDI_PORT_PG_RESUME_CONFIG1_PIPE6m: 5383 spci->mem = MMU_THDI_PORT_PG_RESUME_CONFIG_PIPE6m; break; 5384 case MMU_THDI_PORT_PG_RESUME_CONFIG1_PIPE7m: 5385 spci->mem = MMU_THDI_PORT_PG_RESUME_CONFIG_PIPE7m; break; 5386 case MMU_THDI_PORTSP_CONFIG1m: 5387 spci->mem = MMU_THDI_PORTSP_CONFIGm; break; 5388 case MMU_THDI_PORTSP_CONFIG1_PIPE0m: 5389 spci->mem = MMU_THDI_PORTSP_CONFIG_PIPE0m; break; 5390 case MMU_THDI_PORTSP_CONFIG1_PIPE1m: 5391 spci->mem = MMU_THDI_PORTSP_CONFIG_PIPE1m; break; 5392 case MMU_THDI_PORTSP_CONFIG1_PIPE2m: 5393 spci->mem = MMU_THDI_PORTSP_CONFIG_PIPE2m; break; 5394 case MMU_THDI_PORTSP_CONFIG1_PIPE3m: 5395 spci->mem = MMU_THDI_PORTSP_CONFIG_PIPE3m; break; 5396 case MMU_THDI_PORTSP_CONFIG1_PIPE4m: 5397 spci->mem = MMU_THDI_PORTSP_CONFIG_PIPE4m; break; 5398 case MMU_THDI_PORTSP_CONFIG1_PIPE5m: 5399 spci->mem = MMU_THDI_PORTSP_CONFIG_PIPE5m; break; 5400 case MMU_THDI_PORTSP_CONFIG1_PIPE6m: 5401 spci->mem = MMU_THDI_PORTSP_CONFIG_PIPE6m; break; 5402 case MMU_THDI_PORTSP_CONFIG1_PIPE7m: 5403 spci->mem = MMU_THDI_PORTSP_CONFIG_PIPE7m; break; 5404 case MMU_THDO_Q_TO_QGRP_MAPD1m: 5405 case MMU_THDO_Q_TO_QGRP_MAPD2m: 5406 spci->mem = MMU_THDO_Q_TO_QGRP_MAPD0m; break; 5407 case MMU_THDO_QUEUE_CONFIG1m: 5408 spci->mem = MMU_THDO_QUEUE_CONFIGm; break; 5409 case MMU_THDO_QUEUE_RESUME_OFFSET1m: 5410 spci->mem = MMU_THDO_QUEUE_RESUME_OFFSETm; break; 5411 case MMU_THDO_CONFIG_UC_QGROUP1m: 5412 case MMU_THDO_CONFIG_UC_QGROUP2m: 5413 spci->mem = MMU_THDO_CONFIG_UC_QGROUP0m; break; 5414 case MMU_THDO_CONFIG_PORT_UC1m: 5415 case MMU_THDO_CONFIG_PORT_UC2m: 5416 spci->mem = MMU_THDO_CONFIG_PORT_UC0m; break; 5417 case MMU_THDO_RESUME_PORT_UC1m: 5418 case MMU_THDO_RESUME_PORT_UC2m: 5419 spci->mem = MMU_THDO_RESUME_PORT_UC0m; break; 5420 case MMU_THDO_RESUME_PORT_MC1m: 5421 case MMU_THDO_RESUME_PORT_MC2m: 5422 spci->mem = MMU_THDO_RESUME_PORT_MC0m; break; 5423 case MMU_WRED_DROP_CURVE_PROFILE_0_1m: 5424 case MMU_WRED_DROP_CURVE_PROFILE_0_2m: 5425 case MMU_WRED_DROP_CURVE_PROFILE_0_3m: 5426 case MMU_WRED_DROP_CURVE_PROFILE_0_4m: 5427 case MMU_WRED_DROP_CURVE_PROFILE_0_5m: 5428 spci->mem = MMU_WRED_DROP_CURVE_PROFILE_0_0m; break; 5429 case MMU_WRED_DROP_CURVE_PROFILE_1_1m: 5430 case MMU_WRED_DROP_CURVE_PROFILE_1_2m: 5431 case MMU_WRED_DROP_CURVE_PROFILE_1_3m: 5432 case MMU_WRED_DROP_CURVE_PROFILE_1_4m: 5433 case MMU_WRED_DROP_CURVE_PROFILE_1_5m: 5434 spci->mem = MMU_WRED_DROP_CURVE_PROFILE_1_0m; break; 5435 case MMU_WRED_DROP_CURVE_PROFILE_2_1m: 5436 case MMU_WRED_DROP_CURVE_PROFILE_2_2m: 5437 case MMU_WRED_DROP_CURVE_PROFILE_2_3m: 5438 case MMU_WRED_DROP_CURVE_PROFILE_2_4m: 5439 case MMU_WRED_DROP_CURVE_PROFILE_2_5m: 5440 spci->mem = MMU_WRED_DROP_CURVE_PROFILE_2_0m; break; 5441 case MMU_WRED_DROP_CURVE_PROFILE_3_1m: 5442 case MMU_WRED_DROP_CURVE_PROFILE_3_2m: 5443 case MMU_WRED_DROP_CURVE_PROFILE_3_3m: 5444 case MMU_WRED_DROP_CURVE_PROFILE_3_4m: 5445 case MMU_WRED_DROP_CURVE_PROFILE_3_5m: 5446 spci->mem = MMU_WRED_DROP_CURVE_PROFILE_3_0m; break; 5447 case MMU_WRED_DROP_CURVE_PROFILE_4_1m: 5448 case MMU_WRED_DROP_CURVE_PROFILE_4_2m: 5449 case MMU_WRED_DROP_CURVE_PROFILE_4_3m: 5450 case MMU_WRED_DROP_CURVE_PROFILE_4_4m: 5451 case MMU_WRED_DROP_CURVE_PROFILE_4_5m: 5452 spci->mem = MMU_WRED_DROP_CURVE_PROFILE_4_0m; break; 5453 case MMU_WRED_DROP_CURVE_PROFILE_5_1m: 5454 case MMU_WRED_DROP_CURVE_PROFILE_5_2m: 5455 case MMU_WRED_DROP_CURVE_PROFILE_5_3m: 5456 case MMU_WRED_DROP_CURVE_PROFILE_5_4m: 5457 case MMU_WRED_DROP_CURVE_PROFILE_5_5m: 5458 spci->mem = MMU_WRED_DROP_CURVE_PROFILE_5_0m; break; 5459 case MMU_WRED_DROP_CURVE_PROFILE_6_1m: 5460 case MMU_WRED_DROP_CURVE_PROFILE_6_2m: 5461 case MMU_WRED_DROP_CURVE_PROFILE_6_3m: 5462 case MMU_WRED_DROP_CURVE_PROFILE_6_4m: 5463 case MMU_WRED_DROP_CURVE_PROFILE_6_5m: 5464 spci->mem = MMU_WRED_DROP_CURVE_PROFILE_6_0m; break; 5465 case MMU_WRED_DROP_CURVE_PROFILE_7_1m: 5466 case MMU_WRED_DROP_CURVE_PROFILE_7_2m: 5467 case MMU_WRED_DROP_CURVE_PROFILE_7_3m: 5468 case MMU_WRED_DROP_CURVE_PROFILE_7_4m: 5469 case MMU_WRED_DROP_CURVE_PROFILE_7_5m: 5470 spci->mem = MMU_WRED_DROP_CURVE_PROFILE_7_0m; break; 5471 case MMU_WRED_DROP_CURVE_PROFILE_8_1m: 5472 case MMU_WRED_DROP_CURVE_PROFILE_8_2m: 5473 case MMU_WRED_DROP_CURVE_PROFILE_8_3m: 5474 case MMU_WRED_DROP_CURVE_PROFILE_8_4m: 5475 case MMU_WRED_DROP_CURVE_PROFILE_8_5m: 5476 spci->mem = MMU_WRED_DROP_CURVE_PROFILE_8_0m; break; 5477 case MMU_REPL_MEMBER_ICC_SC0m: 5478 case MMU_REPL_MEMBER_ICC_SC1m: 5479 case MMU_REPL_MEMBER_ICC_SC2m: 5480 case MMU_REPL_MEMBER_ICC_SC3m: 5481 spci->mem = MMU_REPL_MEMBER_ICCm; break; 5482 case MMU_REPL_GROUP_INFO_TBL0m: 5483 case MMU_REPL_GROUP_INFO_TBL1m: 5484 case MMU_REPL_GROUP_INFO_TBL2m: 5485 case MMU_REPL_GROUP_INFO_TBL3m: 5486 spci->mem = MMU_REPL_GROUP_INFO_TBLm; break; 5487 case MMU_INTFO_MMU_PORT_TO_OOB_PORT_MAPPING_THDO1m: 5488 spci->mem = MMU_INTFO_MMU_PORT_TO_OOB_PORT_MAPPING_THDO0m; break; 5489 #endif 5490 5491 default: 5492 break; 5493 } 5494 return SOC_E_NONE; 5495 } 5496 5497 /* correction routine for MMU_REPL_GROUP_INITIAL_COPY_COUNT mem */ 5498 STATIC int 5499 _soc_mmu_repl_group_correction(int mmu_base_index, 5500 _soc_ser_correct_info_t *spci, uint32 *addr) 5501 { 5502 if ((spci == NULL) || (addr == NULL)) { 5503 return SOC_E_PARAM; 5504 } 5505 if (spci->mem == MMU_REPL_GROUP_INITIAL_COPY_COUNT0_SC0m && 5506 ((mmu_base_index == _SOC_MMU_BASE_INDEX_XPE1) || 5507 (mmu_base_index == _SOC_MMU_BASE_INDEX_XPE3))) { 5508 spci->mem = MMU_REPL_GROUP_INITIAL_COPY_COUNT0_SC1m; 5509 *addr &= _SOC_TH_MMU_ADDR_ZERO_OUT_SEG_FIELD; 5510 *addr |= _SOC_TH_MMU_ADDR_SEG1; 5511 spci->addr = *addr; 5512 } 5513 if (spci->mem == MMU_REPL_GROUP_INITIAL_COPY_COUNT1_SC0m && 5514 ((mmu_base_index == _SOC_MMU_BASE_INDEX_XPE1) || 5515 (mmu_base_index == _SOC_MMU_BASE_INDEX_XPE3))) { 5516 spci->mem = MMU_REPL_GROUP_INITIAL_COPY_COUNT1_SC1m; 5517 *addr &= _SOC_TH_MMU_ADDR_ZERO_OUT_SEG_FIELD; 5518 *addr |= _SOC_TH_MMU_ADDR_SEG1; 5519 spci->addr = *addr; 5520 } 5521 return SOC_E_NONE; 5522 } 5523 5524 /* correction routine for MMU_WRED_CONFIG mem */ 5525 STATIC int 5526 _soc_mmu_wred_correction(int unit, _soc_ser_correct_info_t *spci, 5527 uint32 *addr, int *second_pass) 5528 { 5529 if ((spci == NULL) || (addr == NULL) || (second_pass == NULL)) { 5530 return SOC_E_PARAM; 5531 } 5532 switch (spci->mem) { 5533 case MMU_WRED_CONFIG_XPE0_PIPE0m: 5534 spci->mem = MMU_WRED_CONFIG_XPE0_PIPE1m; 5535 spci->mem_reported = MMU_WRED_CONFIG_XPE0_PIPE1m; 5536 #ifdef BCM_TOMAHAWK2_SUPPORT 5537 if (SOC_IS_TOMAHAWK2(unit)) { 5538 *addr &= _SOC_TH2_MMU_ADDR_ZERO_OUT_SEG_FIELD; 5539 *addr |= _SOC_TH2_MMU_ADDR_SEG1; 5540 } else 5541 #endif 5542 { 5543 *addr &= _SOC_TH_MMU_ADDR_ZERO_OUT_SEG_FIELD; 5544 *addr |= _SOC_TH_MMU_ADDR_SEG1; 5545 } 5546 5547 spci->index = *addr - soc_mem_base(unit, spci->mem); 5548 spci->addr = *addr; 5549 *second_pass = 1; 5550 break; 5551 case MMU_WRED_CONFIG_XPE2_PIPE0m: 5552 spci->mem = MMU_WRED_CONFIG_XPE2_PIPE1m; 5553 spci->mem_reported = MMU_WRED_CONFIG_XPE2_PIPE1m; 5554 #ifdef BCM_TOMAHAWK2_SUPPORT 5555 if (SOC_IS_TOMAHAWK2(unit)) { 5556 *addr &= _SOC_TH2_MMU_ADDR_ZERO_OUT_SEG_FIELD; 5557 *addr |= _SOC_TH2_MMU_ADDR_SEG1; 5558 } else 5559 #endif 5560 { 5561 *addr &= _SOC_TH_MMU_ADDR_ZERO_OUT_SEG_FIELD; 5562 *addr |= _SOC_TH_MMU_ADDR_SEG1; 5563 } 5564 5565 spci->index = *addr - soc_mem_base(unit, spci->mem); 5566 spci->addr = *addr; 5567 *second_pass = 1; 5568 break; 5569 case MMU_WRED_CONFIG_XPE1_PIPE2m: 5570 spci->mem = MMU_WRED_CONFIG_XPE1_PIPE3m; 5571 spci->mem_reported = MMU_WRED_CONFIG_XPE1_PIPE3m; 5572 #ifdef BCM_TOMAHAWK2_SUPPORT 5573 if (SOC_IS_TOMAHAWK2(unit)) { 5574 *addr &= _SOC_TH2_MMU_ADDR_ZERO_OUT_SEG_FIELD; 5575 *addr |= _SOC_TH2_MMU_ADDR_SEG3; 5576 } else 5577 #endif 5578 { 5579 *addr &= _SOC_TH_MMU_ADDR_ZERO_OUT_SEG_FIELD; 5580 *addr |= _SOC_TH_MMU_ADDR_SEG3; 5581 } 5582 5583 spci->index = *addr - soc_mem_base(unit, spci->mem); 5584 spci->addr = *addr; 5585 *second_pass = 1; 5586 break; 5587 case MMU_WRED_CONFIG_XPE3_PIPE2m: 5588 spci->mem = MMU_WRED_CONFIG_XPE3_PIPE3m; 5589 spci->mem_reported = MMU_WRED_CONFIG_XPE3_PIPE3m; 5590 #ifdef BCM_TOMAHAWK2_SUPPORT 5591 if (SOC_IS_TOMAHAWK2(unit)) { 5592 *addr &= _SOC_TH2_MMU_ADDR_ZERO_OUT_SEG_FIELD; 5593 *addr |= _SOC_TH2_MMU_ADDR_SEG3; 5594 } else 5595 #endif 5596 { 5597 *addr &= _SOC_TH_MMU_ADDR_ZERO_OUT_SEG_FIELD; 5598 *addr |= _SOC_TH_MMU_ADDR_SEG3; 5599 } 5600 5601 spci->index = *addr - soc_mem_base(unit, spci->mem); 5602 spci->addr = *addr; 5603 *second_pass = 1; 5604 break; 5605 case MMU_WRED_PORT_SP_SHARED_COUNT_XPE0_PIPE0m: 5606 spci->mem = MMU_WRED_PORT_SP_SHARED_COUNT_XPE0_PIPE1m; 5607 spci->mem_reported = MMU_WRED_PORT_SP_SHARED_COUNT_XPE0_PIPE1m; 5608 *addr &= _SOC_TH_MMU_ADDR_ZERO_OUT_SEG_FIELD; 5609 *addr |= _SOC_TH_MMU_ADDR_SEG1; 5610 spci->index = *addr - soc_mem_base(unit, spci->mem); 5611 spci->addr = *addr; 5612 *second_pass = 1; 5613 break; 5614 case MMU_WRED_PORT_SP_SHARED_COUNT_XPE1_PIPE2m: 5615 spci->mem = MMU_WRED_PORT_SP_SHARED_COUNT_XPE1_PIPE3m; 5616 spci->mem_reported = MMU_WRED_PORT_SP_SHARED_COUNT_XPE1_PIPE3m; 5617 *addr &= _SOC_TH_MMU_ADDR_ZERO_OUT_SEG_FIELD; 5618 *addr |= _SOC_TH_MMU_ADDR_SEG3; 5619 spci->index = *addr - soc_mem_base(unit, spci->mem); 5620 spci->addr = *addr; 5621 *second_pass = 1; 5622 break; 5623 case MMU_WRED_PORT_SP_SHARED_COUNT_XPE2_PIPE0m: 5624 spci->mem = MMU_WRED_PORT_SP_SHARED_COUNT_XPE2_PIPE1m; 5625 spci->mem_reported = MMU_WRED_PORT_SP_SHARED_COUNT_XPE2_PIPE1m; 5626 *addr &= _SOC_TH_MMU_ADDR_ZERO_OUT_SEG_FIELD; 5627 *addr |= _SOC_TH_MMU_ADDR_SEG1; 5628 spci->index = *addr - soc_mem_base(unit, spci->mem); 5629 spci->addr = *addr; 5630 *second_pass = 1; 5631 break; 5632 case MMU_WRED_PORT_SP_SHARED_COUNT_XPE3_PIPE2m: 5633 spci->mem = MMU_WRED_PORT_SP_SHARED_COUNT_XPE3_PIPE3m; 5634 spci->mem_reported = MMU_WRED_PORT_SP_SHARED_COUNT_XPE3_PIPE3m; 5635 *addr &= _SOC_TH_MMU_ADDR_ZERO_OUT_SEG_FIELD; 5636 *addr |= _SOC_TH_MMU_ADDR_SEG3; 5637 spci->index = *addr - soc_mem_base(unit, spci->mem); 5638 spci->addr = *addr; 5639 *second_pass = 1; 5640 break; 5641 default: 5642 *second_pass = 0; 5643 break; 5644 } 5645 return SOC_E_NONE; 5646 } 5647 5648 STATIC int 5649 _soc_tomahawk_ser_process_mmu_err(int unit, int block_info_idx, 5650 const _soc_th_ser_info_t *info_list, 5651 char *prefix_str, int mmu_base_index) 5652 { 5653 int rv, type = 0, multi = 0; 5654 uint32 addr = 0, rval, rval_fifo_status, rval_intr_status_reg; 5655 uint32 non_ser_intr_status_mask; 5656 uint32 entry[SOC_MAX_MEM_WORDS]; 5657 soc_reg_t fifo_status_reg, mem_fail_ctr_reg; 5658 soc_reg_t parity_enable_reg = INVALIDr; 5659 soc_field_t parity_enable_field = INVALIDf; 5660 soc_field_t *fields_stat; 5661 soc_field_t intr_stat_clr = INVALIDf; 5662 soc_mem_t ser_fifo_mem; 5663 soc_mem_t parity_enable_mem = INVALIDm; 5664 soc_block_t blocktype = SOC_BLK_NONE; 5665 uint8 blk_idx; 5666 uint32 sblk = 0; 5667 _soc_ser_correct_info_t spci; 5668 int second_pass = 0; 5669 int i; 5670 int f, parity_error = 0; 5671 static int acc_type[] = {_SOC_ACC_TYPE_PIPE_ANY, _SOC_ACC_TYPE_PIPE_ANY}; 5672 _soc_th_ser_mmu_intr_info_t *p_ser_mmu_intr_info; 5673 soc_stat_t *stat = SOC_STAT(unit); 5674 5675 #ifdef BCM_TOMAHAWK3_SUPPORT 5676 if (SOC_IS_TOMAHAWK3(unit)) { 5677 p_ser_mmu_intr_info = (_soc_th_ser_mmu_intr_info_t *) &th3_mmu_intr_info; 5678 intr_stat_clr = MEM_PAR_ERR_INT_STATf; 5679 } else 5680 #endif 5681 #ifdef BCM_TOMAHAWK2_SUPPORT 5682 if (SOC_IS_TOMAHAWK2(unit)) { 5683 p_ser_mmu_intr_info = (_soc_th_ser_mmu_intr_info_t *) &th2_mmu_intr_info; 5684 intr_stat_clr = MEM_PAR_ERR_CLRf; 5685 } else 5686 #endif 5687 { 5688 p_ser_mmu_intr_info = (_soc_th_ser_mmu_intr_info_t *) &mmu_intr_info; 5689 intr_stat_clr = MEM_PAR_ERR_CLRf; 5690 } 5691 5692 switch(info_list->type) { 5693 case _SOC_PARITY_TYPE_MMU_SER: { 5694 /* When we are here, we have been called by _soc_tomahawk_process_ser. 5695 * info_list points to 1st entry in _soc_th_mmu_top_ser_info[]. 5696 * Goal is to find src_sub_block in mmu: MMU_GLB, XPE0,1,2,3, SC0,1 */ 5697 _soc_th_ser_info_t *info = NULL; 5698 5699 /* find src of interrupt in mmu */ 5700 SOC_IF_ERROR_RETURN 5701 (soc_reg32_get(unit, info_list->intr_status_reg, REG_PORT_ANY, 0, 5702 &rval)); /* status_reg has BT,AT = CHIP,SINGLE */ 5703 for (i = 0; p_ser_mmu_intr_info[i].int_statf != INVALIDf; i++) { 5704 if (soc_reg_field_get(unit, info_list->intr_status_reg, rval, 5705 p_ser_mmu_intr_info[i].int_statf)) { 5706 #define MMU_INTR_SRC(i)\ 5707 ((i) == 0? "MMU_GLB" : \ 5708 (i) == 1? "MMU_XPE0" : \ 5709 (i) == 2? "MMU_XPE1" : \ 5710 (i) == 3? "MMU_XPE2" : \ 5711 (i) == 4? "MMU_XPE3" : \ 5712 (i) == 5? "MMU_SC0" : \ 5713 (i) == 6? "MMU_SC1" : \ 5714 (i) == 7? "MMU_SED0" : \ 5715 (i) == 8? "MMU_SED1" : \ 5716 "MMU_UNNOWN") 5717 #ifdef BCM_TOMAHAWK3_SUPPORT 5718 #define MMU_TH3_INTR_SRC(i)\ 5719 ((i) == 0? "MMU_GLB" : \ 5720 (i) == 1? "MMU_ITM0" : \ 5721 (i) == 2? "MMU_ITM1" : \ 5722 (i) == 3? "MMU_EB0" : \ 5723 (i) == 4? "MMU_EB1" : \ 5724 (i) == 5? "MMU_EB2" : \ 5725 (i) == 6? "MMU_EB3" : \ 5726 (i) == 7? "MMU_EB4" : \ 5727 (i) == 8? "MMU_EB5" : \ 5728 (i) == 9? "MMU_EB6" : \ 5729 (i) == 10? "MMU_EB7" : \ 5730 "MMU_UNNOWN") 5731 5732 if (SOC_IS_TOMAHAWK3(unit)) { 5733 LOG_VERBOSE(BSL_LS_SOC_SER, 5734 (BSL_META_U(unit, 5735 "intr_status_reg = 0x%08x, " 5736 "int_statf = %d is set, mmu_intr_info_idx " 5737 "= %d (%s) !!\n"), 5738 rval, p_ser_mmu_intr_info[i].int_statf, i, MMU_TH3_INTR_SRC(i))); 5739 } else 5740 #endif 5741 { 5742 LOG_VERBOSE(BSL_LS_SOC_SER, 5743 (BSL_META_U(unit, 5744 "intr_status_reg = 0x%08x, " 5745 "int_statf = %d is set, mmu_intr_info_idx " 5746 "= %d (%s) !!\n"), 5747 rval, p_ser_mmu_intr_info[i].int_statf, i, MMU_INTR_SRC(i))); 5748 } 5749 info = &(info_list->info[p_ser_mmu_intr_info[i].ser_info_index]); 5750 /* 'info' now points to entry info_index[i] 5751 * in _soc_th_mmu_ser_info[] */ 5752 rv = _soc_tomahawk_ser_process_mmu_err(unit, block_info_idx, 5753 info, prefix_str, 5754 p_ser_mmu_intr_info[i].mmu_base_index); 5755 if (SOC_FAILURE(rv)) { 5756 LOG_CLI((BSL_META_U(unit, 5757 "process_mmu_err: Error processing %s !!\n"), 5758 info->mem_str)); 5759 return rv; 5760 } 5761 } 5762 } 5763 #ifdef BCM_TOMAHAWK3_SUPPORT 5764 if (SOC_IS_TOMAHAWK3(unit)) { 5765 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, info_list->intr_status_reg, 5766 REG_PORT_ANY, 0, rval)); 5767 } 5768 #endif 5769 if (info == NULL) { 5770 LOG_VERBOSE(BSL_LS_SOC_SER, 5771 (BSL_META_U(unit, 5772 "In MMU SER processing with no error bit set " 5773 "0x%08x !!\n"), rval)); 5774 return SOC_E_NONE; 5775 } 5776 } break; 5777 case _SOC_PARITY_TYPE_MMU_GLB: 5778 case _SOC_PARITY_TYPE_MMU_XPE: 5779 #ifdef BCM_TOMAHAWK2_SUPPORT 5780 case _SOC_PARITY_TYPE_MMU_SED: 5781 #endif 5782 #ifdef BCM_TOMAHAWK3_SUPPORT 5783 case _SOC_PARITY_TYPE_MMU_ITMCFG: 5784 case _SOC_PARITY_TYPE_MMU_EBCFG: 5785 #endif 5786 case _SOC_PARITY_TYPE_MMU_SC: { 5787 /* we are here when we were recursively called by process_mmu_ser itself 5788 * and info_list is pointing to one of the entries in 5789 * _soc_th_mmu_ser_info[] 5790 */ 5791 switch(info_list->type) { 5792 case _SOC_PARITY_TYPE_MMU_GLB: /* all of these regs,mem have BT,AT = CHIP,SINGLE */ 5793 #ifdef BCM_TOMAHAWK3_SUPPORT 5794 if (SOC_IS_TOMAHAWK3(unit)) { 5795 fifo_status_reg = MMU_GLBCFG_MEM_SER_FIFO_STSr; 5796 ser_fifo_mem = MMU_GLBCFG_MEM_FAIL_ADDR_64m; 5797 mem_fail_ctr_reg = MMU_GLBCFG_MEM_FAIL_INT_CTRr; 5798 blocktype = SOC_BLK_MMU_GLB; 5799 acc_type[0] = _SOC_ACC_TYPE_PIPE_ANY; 5800 non_ser_intr_status_mask = ~0x1; 5801 } else 5802 #endif 5803 { 5804 fifo_status_reg = MMU_GCFG_MEM_SER_FIFO_STSr; 5805 ser_fifo_mem = MMU_GCFG_MEM_FAIL_ADDR_64m; 5806 mem_fail_ctr_reg = MMU_GCFG_MEM_FAIL_INT_CTRr; 5807 blocktype = SOC_BLK_MMU_GLB; 5808 acc_type[0] = _SOC_ACC_TYPE_PIPE_ANY; 5809 #ifdef BCM_TOMAHAWK2_SUPPORT 5810 if (SOC_IS_TOMAHAWK2(unit)) { 5811 non_ser_intr_status_mask = ~0x1; 5812 } else 5813 #endif 5814 { 5815 non_ser_intr_status_mask = 0x0; 5816 } 5817 } 5818 /* MMU_GCFG_GLB_CPU_INT_STAT has only MEM_PAR_ERR_STATf */ 5819 break; 5820 case _SOC_PARITY_TYPE_MMU_XPE: /* all of these regs,mem have BT,AT = XPE,SINGLE */ 5821 fifo_status_reg = MMU_XCFG_MEM_SER_FIFO_STSr; 5822 ser_fifo_mem = _SOC_FIND_MMU_XPE_SER_FIFO_MEM(mmu_base_index); 5823 mem_fail_ctr_reg = MMU_XCFG_MEM_FAIL_INT_CTRr; 5824 blocktype = SOC_BLK_MMU_XPE; 5825 acc_type[0] = mmu_base_index; 5826 non_ser_intr_status_mask = ~0x1; 5827 /* bit 0 in MMU_XCFG_XPE_CPU_INT_STAT is MEM_PAR_ERR_STATf */ 5828 break; 5829 case _SOC_PARITY_TYPE_MMU_SC: /* all of these regs,mem have BT,AT = SLICE,SINGLE */ 5830 fifo_status_reg = MMU_SCFG_MEM_SER_FIFO_STSr; 5831 ser_fifo_mem = _SOC_FIND_MMU_SC_SER_FIFO_MEM(mmu_base_index); 5832 mem_fail_ctr_reg = MMU_SCFG_MEM_FAIL_INT_CTRr; 5833 blocktype = SOC_BLK_MMU_SC; 5834 acc_type[0] = mmu_base_index; 5835 #ifdef BCM_TOMAHAWK2_SUPPORT 5836 if (SOC_IS_TOMAHAWK2(unit)) { 5837 non_ser_intr_status_mask = ~0x1; 5838 } else 5839 #endif 5840 { 5841 non_ser_intr_status_mask = ~0x4; 5842 } 5843 /* bit 2 in MMU_SCFG_SC_CPU_INT_STAT is MEM_PAR_ERR_STATf */ 5844 break; 5845 #ifdef BCM_TOMAHAWK2_SUPPORT 5846 case _SOC_PARITY_TYPE_MMU_SED: /* all of these regs,mem have BT,AT = SLICE,SINGLE */ 5847 fifo_status_reg = MMU_SEDCFG_MEM_SER_FIFO_STSr; 5848 ser_fifo_mem = _SOC_FIND_MMU_SED_SER_FIFO_MEM(mmu_base_index); 5849 mem_fail_ctr_reg = MMU_SEDCFG_MEM_FAIL_INT_CTRr; 5850 blocktype = SOC_BLK_MMU_SED; 5851 acc_type[0] = mmu_base_index; 5852 non_ser_intr_status_mask = ~0x4; 5853 /* bit 2 in MMU_SEDCFG_SED_CPU_INT_STAT is MEM_PAR_ERR_STATf */ 5854 break; 5855 #endif 5856 #ifdef BCM_TOMAHAWK3_SUPPORT 5857 case _SOC_PARITY_TYPE_MMU_ITMCFG: 5858 fifo_status_reg = MMU_ITMCFG_MEM_SER_FIFO_STSr; 5859 ser_fifo_mem = _SOC_FIND_MMU_ITM_SER_FIFO_MEM(mmu_base_index); 5860 mem_fail_ctr_reg = MMU_ITMCFG_MEM_FAIL_INT_CTRr; 5861 blocktype = SOC_BLK_MMU_ITM; 5862 acc_type[0] = mmu_base_index; 5863 non_ser_intr_status_mask = ~0x1; 5864 break; 5865 case _SOC_PARITY_TYPE_MMU_EBCFG: 5866 fifo_status_reg = MMU_EBCFG_MEM_SER_FIFO_STSr; 5867 ser_fifo_mem = _SOC_FIND_MMU_EB_SER_FIFO_MEM(mmu_base_index); 5868 mem_fail_ctr_reg = MMU_EBCFG_MEM_FAIL_INT_CTRr; 5869 blocktype = SOC_BLK_MMU_EB; 5870 acc_type[0] = mmu_base_index; 5871 non_ser_intr_status_mask = ~0x1; 5872 break; 5873 #endif 5874 default: 5875 return SOC_E_NONE; 5876 } 5877 SOC_IF_ERROR_RETURN 5878 (_soc_th_ser_reg32_get(unit, info_list->intr_status_reg, 5879 REG_PORT_ANY, 0, &rval_intr_status_reg, mmu_base_index)); 5880 if (info_list->intr_status_field_list) { 5881 fields_stat = info_list->intr_status_field_list; 5882 for (f=0 ;; f++) { 5883 if (fields_stat[f] == INVALIDf) { 5884 break; 5885 } 5886 if ((fields_stat[f] == MEM_PAR_ERR_STATf) && 5887 soc_reg_field_get(unit, info_list->intr_status_reg, 5888 rval_intr_status_reg, fields_stat[f])) { 5889 parity_error = 1; 5890 } 5891 } 5892 } else 5893 #ifdef BCM_TOMAHAWK3_SUPPORT 5894 if (info_list->intr_status_field == MEM_PAR_ERR_INT_STATf) { 5895 if (soc_reg_field_get(unit, info_list->intr_status_reg, 5896 rval_intr_status_reg, info_list->intr_status_field)) { 5897 parity_error = 1; 5898 } 5899 } else 5900 #endif 5901 if (info_list->intr_status_field == MEM_PAR_ERR_STATf) { 5902 if (soc_reg_field_get(unit, info_list->intr_status_reg, 5903 rval_intr_status_reg, info_list->intr_status_field)) { 5904 parity_error = 1; 5905 } 5906 } 5907 5908 if (parity_error == 1) { 5909 /* Now we know that one of the reasons for interrupt from MMU is 5910 * parity error for sure, so mmu_ser_fifo has to be non-empty */ 5911 SOC_IF_ERROR_RETURN 5912 (_soc_th_ser_reg32_get(unit, fifo_status_reg, REG_PORT_ANY, 0, 5913 &rval_fifo_status, mmu_base_index)); 5914 if (soc_reg_field_get(unit, fifo_status_reg, rval_fifo_status, EMPTYf)) { 5915 LOG_ERROR(BSL_LS_SOC_SER, 5916 (BSL_META_U(unit, 5917 "unit %d %s SER interrupt with empty fifo !!\n"), 5918 unit, info_list->mem_str)); 5919 SOC_IF_ERROR_RETURN 5920 (soc_th_ser_reg_field32_modify(unit, 5921 info_list->intr_clr_reg, 5922 REG_PORT_ANY, 5923 intr_stat_clr, 5924 1, 0, mmu_base_index)); 5925 return SOC_E_NONE; 5926 } 5927 SOC_IF_ERROR_RETURN 5928 (_soc_th_ser_reg32_get(unit, mem_fail_ctr_reg, REG_PORT_ANY, 0, 5929 &rval, mmu_base_index)); 5930 LOG_WARN(BSL_LS_SOC_SER, 5931 (BSL_META_U(unit, 5932 "unit %d %s mem error interrupt count: %d\n"), 5933 unit, info_list->mem_str, rval)); 5934 SOC_BLOCK_ITER(unit, blk_idx, blocktype) { 5935 sblk = SOC_BLOCK2SCH(unit, blk_idx); 5936 break; 5937 } 5938 do { 5939 if (!second_pass) { 5940 SOC_IF_ERROR_RETURN 5941 (soc_mem_pop(unit, ser_fifo_mem, MEM_BLOCK_ANY, entry)); 5942 /* process entry */ 5943 LOG_WARN(BSL_LS_SOC_SER, 5944 (BSL_META_U(unit, 5945 "%s\n"), info_list->mem_str)); 5946 multi = soc_mem_field32_get(unit, ser_fifo_mem, entry, 5947 ERR_MULTf); 5948 type = soc_mem_field32_get(unit, ser_fifo_mem, entry, 5949 ERR_TYPEf); 5950 addr = soc_mem_field32_get(unit, ser_fifo_mem, entry, EADDRf); 5951 LOG_WARN(BSL_LS_SOC_SER, 5952 (BSL_META_U(unit, 5953 "unit %d %s %s %s error at address 0x%08x\n"), 5954 unit, info_list->mem_str, multi ? "multiple" : "", 5955 type ? ((type == 1) ? "1bit": "parity/2bit") : "", addr)); 5956 5957 sal_memset(&spci, 0, sizeof(spci)); 5958 spci.flags |= SOC_SER_SRC_MEM; 5959 if (multi) { 5960 spci.flags |= SOC_SER_ERR_MULTI; 5961 } 5962 if (type != 1) { 5963 spci.double_bit = 1; 5964 } 5965 spci.reg = INVALIDr; 5966 spci.mem = INVALIDm; 5967 spci.blk_type = blocktype; 5968 spci.pipe_num = -1; 5969 spci.sblk = sblk; 5970 spci.acc_type = -1; 5971 spci.detect_time = sal_time_usecs(); 5972 spci.addr = addr; 5973 parity_enable_reg = INVALIDr; 5974 parity_enable_field = INVALIDf; 5975 5976 /* Try to decode memory */ 5977 for (i = 0; ; i++) { 5978 spci.mem = soc_addr_to_mem_extended(unit, sblk, 5979 acc_type[i], 5980 addr); 5981 #ifdef BCM_TOMAHAWK3_SUPPORT 5982 if (SOC_IS_TOMAHAWK3(unit)) { 5983 (void)soc_th3_mmu_mem_blk_remap(spci.mem, &spci.sblk); 5984 } 5985 #endif 5986 if (spci.mem != INVALIDm) { 5987 LOG_VERBOSE(BSL_LS_SOC_SER, 5988 (BSL_META_U(unit, 5989 "unit %d acc_type = %d " 5990 "got us mem %s \n"), 5991 unit, acc_type[i], 5992 SOC_MEM_NAME(unit,spci.mem))); 5993 break; 5994 } 5995 if (_SOC_ACC_TYPE_PIPE_ANY == acc_type[i]) { 5996 break; 5997 } 5998 } 5999 if (spci.mem != INVALIDm) { 6000 SOC_IF_ERROR_RETURN 6001 (_soc_mmu_repl_group_correction(mmu_base_index, 6002 &spci, &addr)); 6003 spci.index = addr - soc_mem_base(unit, spci.mem); 6004 spci.flags |= SOC_SER_REG_MEM_KNOWN; 6005 spci.flags |= SOC_SER_LOG_WRITE_CACHE; 6006 /* ser_correction will fill cache part in ser_log */ 6007 spci.mem_reported = spci.mem; /* before remap */ 6008 spci.flags |= SOC_SER_LOG_MEM_REPORTED; 6009 SOC_IF_ERROR_RETURN 6010 (_soc_tomahawk_ser_mmu_mem_remap(&spci)); 6011 spci.parity_type = _soc_th_mem_has_ecc(unit, spci.mem)? 6012 SOC_PARITY_TYPE_ECC : 6013 SOC_PARITY_TYPE_PARITY; 6014 LOG_VERBOSE(BSL_LS_SOC_SER, 6015 (BSL_META_U(unit, 6016 "unit %d mem for ser_correction =" 6017 " %s \n"), 6018 unit, SOC_MEM_NAME(unit,spci.mem))); 6019 6020 _soc_th_ser_control_reg_get(unit, 6021 (const _soc_mem_ser_en_info_t *)SOC_MMU_MEM_SER_INFO(unit), 6022 spci.mem, /* after remap */ 6023 &parity_enable_reg, 6024 &parity_enable_mem, 6025 &parity_enable_field); 6026 } else { 6027 spci.flags |= SOC_SER_REG_MEM_UNKNOWN; 6028 spci.mem_reported = INVALIDm; 6029 parity_enable_reg = INVALIDr; 6030 parity_enable_field = INVALIDf; 6031 } 6032 } /* !second_pass */ 6033 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 6034 SOC_SWITCH_EVENT_DATA_ERROR_ECC, 6035 sblk | SOC_SER_ERROR_DATA_BLK_ADDR_SET, 6036 addr); 6037 6038 spci.log_id = _soc_th_populate_ser_log(unit, 6039 parity_enable_reg, 6040 parity_enable_mem, 6041 parity_enable_field, 6042 spci.mem_reported, 6043 blk_idx, 6044 spci.pipe_num, 6045 spci.index, 6046 spci.detect_time, 6047 spci.sblk, 6048 spci.addr, 6049 1, /* disable_parity */ 6050 0, /* disable_mem_read */ 6051 0, /* disable_fill_cache_log */ 6052 1, /* force_cache_log */ 6053 FALSE, 0); 6054 if ((spci.mem != INVALIDm) && 6055 (SOC_MEM_SER_CORRECTION_TYPE(unit, spci.mem) != 0)) { 6056 spci.inst = mmu_base_index; 6057 6058 if ((SOC_MEM_SER_CORRECTION_TYPE(unit, spci.mem) == 6059 SOC_MEM_FLAG_SER_ENTRY_CLEAR) && 6060 (info_list->type == _SOC_PARITY_TYPE_MMU_XPE)) { 6061 6062 spci.flags |= SOC_SER_ALSO_UPDATE_SW_COUNTER; 6063 /* xpe0, 1, 2, 3 */ 6064 spci.pipe_num = (spci.addr >> 15) & 0x3; 6065 /* bits 16:15 */ 6066 switch (spci.mem) { 6067 case MMU_CTR_COLOR_DROP_MEM_XPE0m: 6068 case MMU_CTR_COLOR_DROP_MEM_XPE1m: 6069 case MMU_CTR_COLOR_DROP_MEM_XPE2m: 6070 case MMU_CTR_COLOR_DROP_MEM_XPE3m: 6071 spci.counter_base_mem = MMU_CTR_COLOR_DROP_MEMm; 6072 spci.pipe_num = -1; /* Note */ 6073 break; 6074 6075 case MMU_CTR_ING_DROP_MEM_XPE0_PIPE0m: 6076 case MMU_CTR_ING_DROP_MEM_XPE1_PIPE0m: 6077 spci.counter_base_mem = MMU_CTR_ING_DROP_MEMm; 6078 spci.pipe_num = 0; 6079 break; 6080 case MMU_CTR_ING_DROP_MEM_XPE2_PIPE1m: 6081 case MMU_CTR_ING_DROP_MEM_XPE3_PIPE1m: 6082 spci.counter_base_mem = MMU_CTR_ING_DROP_MEMm; 6083 spci.pipe_num = 1; 6084 break; 6085 case MMU_CTR_ING_DROP_MEM_XPE2_PIPE2m: 6086 case MMU_CTR_ING_DROP_MEM_XPE3_PIPE2m: 6087 spci.counter_base_mem = MMU_CTR_ING_DROP_MEMm; 6088 spci.pipe_num = 2; 6089 break; 6090 case MMU_CTR_ING_DROP_MEM_XPE0_PIPE3m: 6091 case MMU_CTR_ING_DROP_MEM_XPE1_PIPE3m: 6092 spci.counter_base_mem = MMU_CTR_ING_DROP_MEMm; 6093 spci.pipe_num = 3; 6094 break; 6095 /* Unexpected mems */ 6096 default: 6097 spci.flags &= ~SOC_SER_ALSO_UPDATE_SW_COUNTER; 6098 /* use HW only clear */ 6099 spci.counter_base_mem = INVALIDm; 6100 LOG_WARN(BSL_LS_SOC_SER, (BSL_META_U(unit, 6101 "Mem %s (sbus_addr: 0x%08x), will use hw_only_clear, " 6102 "inst %d, pipe %d\n"), 6103 SOC_MEM_NAME(unit, spci.mem), addr, 6104 spci.inst, spci.pipe_num)); 6105 break; 6106 } 6107 } 6108 rv = soc_ser_correction(unit, &spci); 6109 if (SOC_FAILURE(rv)) { 6110 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 6111 SOC_SWITCH_EVENT_DATA_ERROR_FAILEDTOCORRECT, 6112 sblk | SOC_SER_ERROR_DATA_BLK_ADDR_SET, 6113 addr); 6114 soc_ser_stat_update(unit, 0, spci.blk_type, 6115 spci.parity_type, 6116 spci.double_bit, 6117 SocSerCorrectTypeFailedToCorrect, 6118 stat); 6119 /* Dont 'return' here - as it will skip clearing of 6120 * interrupt and thus will result in processing of empty 6121 * ser fifo */ 6122 } 6123 } else if (spci.mem == INVALIDm) { 6124 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 6125 SOC_SWITCH_EVENT_DATA_ERROR_FAILEDTOCORRECT, 6126 sblk | SOC_SER_ERROR_DATA_BLK_ADDR_SET, 6127 addr); 6128 soc_ser_stat_update(unit, 0, spci.blk_type, 6129 SOC_PARITY_TYPE_PARITY, 6130 spci.double_bit, 6131 SocSerCorrectTypeNoAction, 6132 stat); 6133 LOG_ERROR(BSL_LS_SOC_SER, 6134 (BSL_META_U(unit, 6135 "unit %d %s address 0x%08x: decoding of address to mem FAILED !!\n"), 6136 unit, info_list->mem_str, addr)); 6137 6138 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 6139 SOC_SWITCH_EVENT_DATA_ERROR_FATAL, 6140 INVALIDm, 6141 spci.index); 6142 /* Dont 'return' here - as it will skip clearing of 6143 * interrupt and thus will result in processing of empty 6144 * ser fifo */ 6145 } else { 6146 rv = SOC_E_NONE; 6147 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 6148 SOC_SWITCH_EVENT_DATA_ERROR_AUTO_CORRECTED, 6149 sblk | SOC_SER_ERROR_DATA_BLK_ADDR_SET, 6150 addr); 6151 soc_ser_stat_update(unit, 0, spci.blk_type, 6152 (type == 1) ? SOC_PARITY_TYPE_ECC : 6153 SOC_PARITY_TYPE_PARITY, 6154 spci.double_bit, 6155 SocSerCorrectTypeNoAction, 6156 stat); 6157 } 6158 6159 if (spci.log_id != 0) { 6160 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 6161 SOC_SWITCH_EVENT_DATA_ERROR_LOG, 6162 spci.log_id, 0); 6163 if (soc_property_get(unit, "ser_log_print_one", 0)) { 6164 soc_ser_log_print_one(unit, spci.log_id); 6165 } 6166 } 6167 6168 if (second_pass) { 6169 /* already in second_pass, move to next fifo entry */ 6170 SOC_IF_ERROR_RETURN 6171 (_soc_th_ser_reg32_get(unit, fifo_status_reg, 6172 REG_PORT_ANY, 0, 6173 &rval_fifo_status, 6174 mmu_base_index)); 6175 second_pass = 0; 6176 /* start next fifo entry with second_pass=0 */ 6177 } else { /* in first_pass */ 6178 SOC_IF_ERROR_RETURN 6179 (_soc_mmu_wred_correction(unit, &spci, &addr, 6180 &second_pass)); 6181 if (!second_pass) { 6182 /* second_pass not needed */ 6183 SOC_IF_ERROR_RETURN 6184 (_soc_th_ser_reg32_get(unit, fifo_status_reg, 6185 REG_PORT_ANY, 0, 6186 &rval_fifo_status, 6187 mmu_base_index)); 6188 } 6189 /* else, second_pass is needed, don't read next fifo entry 6190 * yet */ 6191 } 6192 } while (!soc_reg_field_get(unit, fifo_status_reg, rval_fifo_status, EMPTYf)); 6193 SOC_IF_ERROR_RETURN 6194 (soc_th_ser_reg_field32_modify(unit, info_list->intr_clr_reg, 6195 REG_PORT_ANY, 6196 intr_stat_clr, 1, 6197 0, mmu_base_index)); 6198 } 6199 6200 /* non_ser mmu interrupts in same status reg are asserted */ 6201 if (rval_intr_status_reg & non_ser_intr_status_mask) { 6202 #ifdef BCM_TOMAHAWK3_SUPPORT 6203 if (SOC_IS_TOMAHAWK3(unit)) { 6204 rv = soc_th3_mmu_non_ser_intr_handler(unit, 6205 blocktype, 6206 /* can be SOC_BLK_MMU_ITM, 6207 * SOC_BLK_MMU_EB */ 6208 mmu_base_index, 6209 /* specifies xpe0,1,2,3 6210 * in case of SOC_BLK_MMU_XPE */ 6211 /* specifies sc0,1 6212 * in case of SOC_BLK_MMU_SC, 6213 * SOC_BLK_MMU_SED */ 6214 rval_intr_status_reg & 6215 non_ser_intr_status_mask); 6216 /* value of intr_status_reg */ 6217 } else 6218 #endif 6219 #ifdef BCM_TOMAHAWK2_SUPPORT 6220 if (SOC_IS_TOMAHAWK2(unit)) { 6221 rv = soc_th2_mmu_non_ser_intr_handler(unit, 6222 blocktype, 6223 /* can be SOC_BLK_MMU_XPE, 6224 * SOC_BLK_MMU_SC, 6225 * SOC_BLK_MMU_SED */ 6226 mmu_base_index, 6227 /* specifies xpe0,1,2,3 6228 * in case of SOC_BLK_MMU_XPE */ 6229 /* specifies sc0,1 6230 * in case of SOC_BLK_MMU_SC, 6231 * SOC_BLK_MMU_SED */ 6232 rval_intr_status_reg & 6233 non_ser_intr_status_mask); 6234 /* value of intr_status_reg */ 6235 } else 6236 #endif 6237 { 6238 rv = soc_th_mmu_non_ser_intr_handler(unit, 6239 blocktype, 6240 /* can be SOC_BLK_MMU_XPE, SOC_BLK_MMU_SC */ 6241 mmu_base_index, 6242 /* specifies xpe0,1,2,3 in case of SOC_BLK_MMU_XPE */ 6243 /* specifies sc0,1 in case of SOC_BLK_MMU_SC */ 6244 rval_intr_status_reg & 6245 non_ser_intr_status_mask); 6246 /* value of intr_status_reg */ 6247 } 6248 } 6249 } break; 6250 default: 6251 break; 6252 } 6253 6254 return SOC_E_NONE; 6255 } 6256 6257 STATIC int 6258 _soc_th_idb_counters_clear(int unit, int pipe, soc_reg_t obm_status_reg) 6259 { 6260 int i, j, obm_queue_num; 6261 uint64 tmp64; 6262 static const soc_reg_t idb_obm_reg_list[] = { 6263 IDB_OBM0_LOSSY_LO_PKT_DROP_COUNTr, 6264 IDB_OBM0_LOSSY_HI_PKT_DROP_COUNTr, 6265 IDB_OBM0_LOSSLESS0_PKT_DROP_COUNTr, 6266 IDB_OBM0_LOSSLESS1_PKT_DROP_COUNTr, 6267 IDB_OBM0_LOSSY_LO_BYTE_DROP_COUNTr, 6268 IDB_OBM0_LOSSY_HI_BYTE_DROP_COUNTr, 6269 IDB_OBM0_LOSSLESS0_BYTE_DROP_COUNTr, 6270 IDB_OBM0_LOSSLESS1_BYTE_DROP_COUNTr, 6271 IDB_OBM0_FLOW_CONTROL_EVENT_COUNTr, 6272 IDB_OBM0_MAX_USAGEr, 6273 6274 IDB_OBM1_LOSSY_LO_PKT_DROP_COUNTr, 6275 IDB_OBM1_LOSSY_HI_PKT_DROP_COUNTr, 6276 IDB_OBM1_LOSSLESS0_PKT_DROP_COUNTr, 6277 IDB_OBM1_LOSSLESS1_PKT_DROP_COUNTr, 6278 IDB_OBM1_LOSSY_LO_BYTE_DROP_COUNTr, 6279 IDB_OBM1_LOSSY_HI_BYTE_DROP_COUNTr, 6280 IDB_OBM1_LOSSLESS0_BYTE_DROP_COUNTr, 6281 IDB_OBM1_LOSSLESS1_BYTE_DROP_COUNTr, 6282 IDB_OBM1_FLOW_CONTROL_EVENT_COUNTr, 6283 IDB_OBM1_MAX_USAGEr, 6284 6285 IDB_OBM2_LOSSY_LO_PKT_DROP_COUNTr, 6286 IDB_OBM2_LOSSY_HI_PKT_DROP_COUNTr, 6287 IDB_OBM2_LOSSLESS0_PKT_DROP_COUNTr, 6288 IDB_OBM2_LOSSLESS1_PKT_DROP_COUNTr, 6289 IDB_OBM2_LOSSY_LO_BYTE_DROP_COUNTr, 6290 IDB_OBM2_LOSSY_HI_BYTE_DROP_COUNTr, 6291 IDB_OBM2_LOSSLESS0_BYTE_DROP_COUNTr, 6292 IDB_OBM2_LOSSLESS1_BYTE_DROP_COUNTr, 6293 IDB_OBM2_FLOW_CONTROL_EVENT_COUNTr, 6294 IDB_OBM2_MAX_USAGEr, 6295 6296 IDB_OBM3_LOSSY_LO_PKT_DROP_COUNTr, 6297 IDB_OBM3_LOSSY_HI_PKT_DROP_COUNTr, 6298 IDB_OBM3_LOSSLESS0_PKT_DROP_COUNTr, 6299 IDB_OBM3_LOSSLESS1_PKT_DROP_COUNTr, 6300 IDB_OBM3_LOSSY_LO_BYTE_DROP_COUNTr, 6301 IDB_OBM3_LOSSY_HI_BYTE_DROP_COUNTr, 6302 IDB_OBM3_LOSSLESS0_BYTE_DROP_COUNTr, 6303 IDB_OBM3_LOSSLESS1_BYTE_DROP_COUNTr, 6304 IDB_OBM3_FLOW_CONTROL_EVENT_COUNTr, 6305 IDB_OBM3_MAX_USAGEr, 6306 6307 IDB_OBM4_LOSSY_LO_PKT_DROP_COUNTr, 6308 IDB_OBM4_LOSSY_HI_PKT_DROP_COUNTr, 6309 IDB_OBM4_LOSSLESS0_PKT_DROP_COUNTr, 6310 IDB_OBM4_LOSSLESS1_PKT_DROP_COUNTr, 6311 IDB_OBM4_LOSSY_LO_BYTE_DROP_COUNTr, 6312 IDB_OBM4_LOSSY_HI_BYTE_DROP_COUNTr, 6313 IDB_OBM4_LOSSLESS0_BYTE_DROP_COUNTr, 6314 IDB_OBM4_LOSSLESS1_BYTE_DROP_COUNTr, 6315 IDB_OBM4_FLOW_CONTROL_EVENT_COUNTr, 6316 IDB_OBM4_MAX_USAGEr, 6317 6318 IDB_OBM5_LOSSY_LO_PKT_DROP_COUNTr, 6319 IDB_OBM5_LOSSY_HI_PKT_DROP_COUNTr, 6320 IDB_OBM5_LOSSLESS0_PKT_DROP_COUNTr, 6321 IDB_OBM5_LOSSLESS1_PKT_DROP_COUNTr, 6322 IDB_OBM5_LOSSY_LO_BYTE_DROP_COUNTr, 6323 IDB_OBM5_LOSSY_HI_BYTE_DROP_COUNTr, 6324 IDB_OBM5_LOSSLESS0_BYTE_DROP_COUNTr, 6325 IDB_OBM5_LOSSLESS1_BYTE_DROP_COUNTr, 6326 IDB_OBM5_FLOW_CONTROL_EVENT_COUNTr, 6327 IDB_OBM5_MAX_USAGEr, 6328 6329 IDB_OBM6_LOSSY_LO_PKT_DROP_COUNTr, 6330 IDB_OBM6_LOSSY_HI_PKT_DROP_COUNTr, 6331 IDB_OBM6_LOSSLESS0_PKT_DROP_COUNTr, 6332 IDB_OBM6_LOSSLESS1_PKT_DROP_COUNTr, 6333 IDB_OBM6_LOSSY_LO_BYTE_DROP_COUNTr, 6334 IDB_OBM6_LOSSY_HI_BYTE_DROP_COUNTr, 6335 IDB_OBM6_LOSSLESS0_BYTE_DROP_COUNTr, 6336 IDB_OBM6_LOSSLESS1_BYTE_DROP_COUNTr, 6337 IDB_OBM6_FLOW_CONTROL_EVENT_COUNTr, 6338 IDB_OBM6_MAX_USAGEr, 6339 6340 IDB_OBM7_LOSSY_LO_PKT_DROP_COUNTr, 6341 IDB_OBM7_LOSSY_HI_PKT_DROP_COUNTr, 6342 IDB_OBM7_LOSSLESS0_PKT_DROP_COUNTr, 6343 IDB_OBM7_LOSSLESS1_PKT_DROP_COUNTr, 6344 IDB_OBM7_LOSSY_LO_BYTE_DROP_COUNTr, 6345 IDB_OBM7_LOSSY_HI_BYTE_DROP_COUNTr, 6346 IDB_OBM7_LOSSLESS0_BYTE_DROP_COUNTr, 6347 IDB_OBM7_LOSSLESS1_BYTE_DROP_COUNTr, 6348 IDB_OBM7_FLOW_CONTROL_EVENT_COUNTr, 6349 IDB_OBM7_MAX_USAGEr 6350 }; 6351 6352 #define _SOC_IDB_OBM_NUM_DISABLE_REGS 10 6353 #define _SOC_IDB_BM_NUM_GEN_CLEAR_REGS 8 6354 switch (obm_status_reg) { 6355 case IDB_OBM0_QUEUE_ECC_STATUSr: 6356 obm_queue_num = 0; 6357 break; 6358 case IDB_OBM1_QUEUE_ECC_STATUSr: 6359 obm_queue_num = 1; 6360 break; 6361 case IDB_OBM2_QUEUE_ECC_STATUSr: 6362 obm_queue_num = 2; 6363 break; 6364 case IDB_OBM3_QUEUE_ECC_STATUSr: 6365 obm_queue_num = 3; 6366 break; 6367 case IDB_OBM4_QUEUE_ECC_STATUSr: 6368 obm_queue_num = 4; 6369 break; 6370 case IDB_OBM5_QUEUE_ECC_STATUSr: 6371 obm_queue_num = 5; 6372 break; 6373 case IDB_OBM6_QUEUE_ECC_STATUSr: 6374 obm_queue_num = 6; 6375 break; 6376 case IDB_OBM7_QUEUE_ECC_STATUSr: 6377 obm_queue_num = 7; 6378 break; 6379 default: 6380 return SOC_E_PARAM; 6381 } 6382 6383 COMPILER_64_ZERO(tmp64); 6384 for (i = 0; i < _SOC_IDB_OBM_NUM_DISABLE_REGS; i++) { 6385 soc_reg_t reg = 6386 idb_obm_reg_list[(obm_queue_num*_SOC_IDB_OBM_NUM_DISABLE_REGS) + i]; 6387 soc_reg_t base_reg = reg; 6388 if (!SOC_REG_IS_VALID(unit, reg)) { 6389 continue; 6390 } 6391 if (SOC_REG_UNIQUE_ACC(unit, reg) != NULL) { 6392 reg = SOC_REG_UNIQUE_ACC(unit, reg)[pipe]; 6393 } 6394 for (j = 0; j < SOC_REG_NUMELS(unit, reg); j++) { 6395 /* For counts collected by sw, clear both hw, sw counts */ 6396 if (i < _SOC_IDB_BM_NUM_GEN_CLEAR_REGS) { 6397 SOC_IF_ERROR_RETURN( 6398 soc_ser_update_counter(unit, 6399 1, /* is_reg */ 6400 reg, /* restore_reg */ 6401 INVALIDm, /* restore_mem */ 6402 j, /* index */ 6403 REG_PORT_ANY, /* port */ 6404 base_reg, /* base_reg */ 6405 INVALIDm, /* base_mem */ 6406 obm_queue_num,/* inst_num */ 6407 pipe, /* pipe_num */ 6408 0)); /* restore_last */ 6409 LOG_VERBOSE(BSL_LS_SOC_SER, (BSL_META_U(unit, 6410 "Cleared sw, hw reg %s, %s, pipe=%0d, numels=%0d\n\n\n"), 6411 SOC_REG_NAME(unit, reg), 6412 SOC_REG_IS_64(unit, reg)? "64b" : "32b", 6413 pipe, j)); 6414 continue; 6415 } 6416 6417 /* For counts not collected by sw, clear only hw count */ 6418 if (SOC_REG_IS_64(unit, reg)) { 6419 SOC_IF_ERROR_RETURN( 6420 soc_reg_set(unit, reg, REG_PORT_ANY, j, tmp64)); 6421 LOG_VERBOSE(BSL_LS_SOC_SER, 6422 (BSL_META_U(unit, 6423 "Cleared reg %s, 64b, pipe=%0d, numels=%0d\n"), 6424 SOC_REG_NAME(unit, reg), pipe, j)); 6425 } else { 6426 SOC_IF_ERROR_RETURN( 6427 soc_reg32_set(unit, reg, REG_PORT_ANY, j, 0)); 6428 LOG_VERBOSE(BSL_LS_SOC_SER, 6429 (BSL_META_U(unit, 6430 "Cleared reg %s, 32b, pipe=%0d, numels=%0d\n"), 6431 SOC_REG_NAME(unit, reg), pipe, j)); 6432 } 6433 } 6434 } 6435 return SOC_E_NONE; 6436 } 6437 6438 #if defined (BCM_TOMAHAWK2_SUPPORT) || defined (BCM_TOMAHAWKPLUS_SUPPORT) 6439 STATIC int 6440 _soc_tomahawk_ser_process_clmac(int unit, int block_info_idx, 6441 const _soc_th_ser_info_t *info, 6442 char *prefix_str, char *mem_str, soc_block_t blocktype) 6443 { 6444 uint64 rval64; 6445 uint32 has_error = FALSE, rval = 0; 6446 int log_port; 6447 int single_bit = 0, double_bit = 0; 6448 soc_stat_t *stat = SOC_STAT(unit); 6449 6450 COMPILER_64_ZERO(rval64); 6451 if ((info->intr_status_reg == INVALIDr) || (INVALIDf == info->intr_status_field)) { 6452 return SOC_E_NONE; 6453 } 6454 6455 PBMP_ITER(SOC_BLOCK_BITMAP(unit, block_info_idx), log_port) { 6456 single_bit = 0; 6457 double_bit = 0; 6458 if (SOC_REG_IS_64(unit, info->intr_status_reg)) { 6459 SOC_IF_ERROR_RETURN 6460 (soc_reg_get(unit, info->intr_status_reg, log_port, 0, &rval64)); 6461 if (soc_reg64_field32_get(unit, info->intr_status_reg, 6462 rval64, info->intr_status_field)) { 6463 has_error = TRUE; 6464 if (info->intr_status_field == SUM_TX_CDC_SINGLE_BIT_ERRf || 6465 info->intr_status_field == SUM_RX_CDC_SINGLE_BIT_ERRf || 6466 info->intr_status_field == SUM_RX_TS_MEM_SINGLE_BIT_ERRf) { 6467 single_bit = 1; 6468 } 6469 if (info->intr_status_field == SUM_TX_CDC_DOUBLE_BIT_ERRf || 6470 info->intr_status_field == SUM_RX_CDC_DOUBLE_BIT_ERRf || 6471 info->intr_status_field == SUM_RX_TS_MEM_DOUBLE_BIT_ERRf) { 6472 double_bit = 1; 6473 } 6474 } 6475 if ((info->intr_clr_reg != INVALIDr) && (INVALIDf != info->intr_clr_field)) { 6476 COMPILER_64_ZERO(rval64); 6477 SOC_IF_ERROR_RETURN(soc_reg_get(unit, info->intr_clr_reg, log_port, 0, &rval64)); 6478 soc_reg64_field32_set(unit, info->intr_clr_reg, &rval64, info->intr_clr_field, 6479 0); 6480 SOC_IF_ERROR_RETURN 6481 (soc_reg_set(unit, info->intr_clr_reg, log_port, 0, rval64)); 6482 } 6483 } else { 6484 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, info->intr_status_reg, log_port, 0, &rval)); 6485 if (soc_reg_field_get(unit, info->intr_status_reg, rval, 6486 info->intr_status_field)) { 6487 has_error = TRUE; 6488 if (info->intr_status_field == SUM_TX_CDC_SINGLE_BIT_ERRf || 6489 info->intr_status_field == SUM_RX_CDC_SINGLE_BIT_ERRf || 6490 info->intr_status_field == SUM_RX_TS_MEM_SINGLE_BIT_ERRf) { 6491 single_bit = 1; 6492 } 6493 if (info->intr_status_field == SUM_TX_CDC_DOUBLE_BIT_ERRf || 6494 info->intr_status_field == SUM_RX_CDC_DOUBLE_BIT_ERRf || 6495 info->intr_status_field == SUM_RX_TS_MEM_DOUBLE_BIT_ERRf) { 6496 double_bit = 1; 6497 } 6498 } 6499 if ((info->intr_clr_reg != INVALIDr) && (INVALIDf != info->intr_clr_field)) { 6500 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, info->intr_clr_reg, log_port, 0, &rval)); 6501 soc_reg_field_set(unit, info->intr_clr_reg, &rval, info->intr_clr_field,0); 6502 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, info->intr_clr_reg, log_port, 0, rval)); 6503 } 6504 } 6505 6506 if (single_bit) { 6507 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 6508 SOC_SWITCH_EVENT_DATA_ERROR_AUTO_CORRECTED, 0, 0); 6509 } 6510 if (double_bit) { 6511 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 6512 SOC_SWITCH_EVENT_DATA_ERROR_UNCORRECTABLE, 0, 0); 6513 } 6514 } 6515 6516 if (has_error) { 6517 soc_ser_stat_update(unit, 0, blocktype, SOC_PARITY_TYPE_PARITY, 6518 0, SocSerCorrectTypeNoAction, stat); 6519 } 6520 6521 if (!has_error) { 6522 LOG_VERBOSE(BSL_LS_SOC_SER, 6523 (BSL_META_U(unit, 6524 "%s %s hardware inconsistency\n"), 6525 prefix_str, mem_str)); 6526 } 6527 return SOC_E_NONE; 6528 } 6529 #endif 6530 #ifdef BCM_TOMAHAWK3_SUPPORT 6531 STATIC int 6532 _soc_tomahawk_ser_process_cdmac(int unit, int block_info_idx, 6533 const _soc_th_ser_info_t *info, 6534 char *prefix_str, char *mem_str, 6535 soc_block_t blocktype) 6536 { 6537 uint32 has_error = FALSE, rval = 0; 6538 int log_port; 6539 int i = 0; 6540 int single_bit = 0, double_bit = 0; 6541 /* Mask is based on the bits in intr_status_reg */ 6542 uint32 single_bit_mask = 0x5, double_bit_mask = 0x80a; 6543 soc_stat_t *stat = SOC_STAT(unit); 6544 6545 if ((info->intr_status_reg == INVALIDr) || 6546 ((INVALIDf == info->intr_status_field) && 6547 (NULL == info->intr_status_field_list))) { 6548 return SOC_E_NONE; 6549 } 6550 6551 PBMP_ITER(SOC_BLOCK_BITMAP(unit, block_info_idx), log_port) { 6552 single_bit = 0; 6553 double_bit = 0; 6554 for(i = 0; i < 2; i++) { 6555 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, info->intr_status_reg, log_port, i, &rval)); 6556 if (rval != 0) { 6557 has_error = TRUE; 6558 if (rval & single_bit_mask) { 6559 single_bit = 1; 6560 } 6561 if (rval & double_bit_mask) { 6562 double_bit = 1; 6563 } 6564 } 6565 if ((info->intr_clr_reg != INVALIDr) && (INVALIDf != info->intr_clr_field)) { 6566 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, info->intr_clr_reg, log_port, i, &rval)); 6567 soc_reg_field_set(unit, info->intr_clr_reg, &rval, info->intr_clr_field,i); 6568 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, info->intr_clr_reg, log_port, i, rval)); 6569 } 6570 } 6571 if (single_bit) { 6572 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 6573 SOC_SWITCH_EVENT_DATA_ERROR_AUTO_CORRECTED, 0, 0); 6574 } 6575 if (double_bit) { 6576 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 6577 SOC_SWITCH_EVENT_DATA_ERROR_UNCORRECTABLE, 0, 0); 6578 } 6579 } 6580 6581 if (has_error) { 6582 soc_ser_stat_update(unit, 0, blocktype, SOC_PARITY_TYPE_PARITY, 6583 0, SocSerCorrectTypeNoAction, stat); 6584 } 6585 6586 if (!has_error) { 6587 LOG_VERBOSE(BSL_LS_SOC_SER, 6588 (BSL_META_U(unit, 6589 "%s %s hardware inconsistency\n"), 6590 prefix_str, mem_str)); 6591 } 6592 return SOC_E_NONE; 6593 } 6594 #endif 6595 6596 STATIC int 6597 _soc_tomahawk_ser_process_ecc(int unit, int block_info_idx, int pipe, int port, 6598 const _soc_th_ser_info_t *info, 6599 char *prefix_str, char *mem_str, 6600 soc_block_t blocktype, int idb_scan_thread) 6601 { 6602 #define _SOC_TH_IF_ERROR_UNLOCK_IDB_RETURN(rv) \ 6603 if (SOC_FAILURE(rv)) { \ 6604 if (idb_lock) { \ 6605 SOC_IDB_UNLOCK(unit); \ 6606 idb_lock = 0; \ 6607 } \ 6608 return rv; \ 6609 } 6610 _soc_th_ser_reg_t reg_entry[2], *reg_ptr; 6611 soc_reg_t reg, parity_enable_reg; 6612 soc_field_t ecc_field = ECC_ERRf, parity_enable_field; 6613 uint32 rval, minfo; 6614 uint32 multiple, double_bit, entry_idx, idx, has_error; 6615 char *mem_str_ptr; 6616 _soc_ser_correct_info_t spci; 6617 int rv, idb_lock = 0; 6618 soc_stat_t *stat = SOC_STAT(unit); 6619 /* 6620 * info can be 6621 * _soc_th_pm_clp_ser_info[] for which info->mem is always INVALIDm 6622 * _soc_th_pm_xlp_ser_info[] for which info->mem is always INVALIDm 6623 * _soc_th_idb_ser_info[] for which info->mem may not be INVALIDm 6624 */ 6625 if (info->intr_status_reg != INVALIDr) { 6626 reg_entry[0].reg = info->intr_status_reg; 6627 reg_entry[0].mem_str = NULL; 6628 reg_entry[1].reg = INVALIDr; 6629 reg_ptr = reg_entry; 6630 } else if (info->intr_status_reg_list != NULL) { 6631 reg_ptr = info->intr_status_reg_list; 6632 } else { 6633 return SOC_E_NONE; 6634 } 6635 6636 if (INVALIDf != info->intr_status_field) { 6637 ecc_field = info->intr_status_field; 6638 } 6639 6640 sal_memset(&spci, 0, sizeof(spci)); 6641 has_error = FALSE; 6642 for (idx = 0; reg_ptr[idx].reg != INVALIDr; idx++) { 6643 switch (reg_ptr[idx].reg) { 6644 case IDB_OBM0_QUEUE_ECC_STATUSr: 6645 case IDB_OBM1_QUEUE_ECC_STATUSr: 6646 case IDB_OBM2_QUEUE_ECC_STATUSr: 6647 case IDB_OBM3_QUEUE_ECC_STATUSr: 6648 case IDB_OBM4_QUEUE_ECC_STATUSr: 6649 case IDB_OBM5_QUEUE_ECC_STATUSr: 6650 case IDB_OBM6_QUEUE_ECC_STATUSr: 6651 case IDB_OBM7_QUEUE_ECC_STATUSr: 6652 SOC_IDB_LOCK(unit); 6653 idb_lock = 1; 6654 break; 6655 #ifdef BCM_TOMAHAWK3_SUPPORT 6656 case IDB_OBM0_OVERSUB_MON_ECC_STATUSr: 6657 spci.mem = IDB_OBM0_IOM_STATS_WINDOW_RESULTSm; 6658 break; 6659 case IDB_OBM1_OVERSUB_MON_ECC_STATUSr: 6660 spci.mem = IDB_OBM1_IOM_STATS_WINDOW_RESULTSm; 6661 break; 6662 case IDB_OBM2_OVERSUB_MON_ECC_STATUSr: 6663 spci.mem = IDB_OBM2_IOM_STATS_WINDOW_RESULTSm; 6664 break; 6665 case IDB_OBM3_OVERSUB_MON_ECC_STATUSr: 6666 spci.mem = IDB_OBM3_IOM_STATS_WINDOW_RESULTSm; 6667 break; 6668 case CENTRAL_CTR_EVICTION_INTR_STATUSr: 6669 spci.mem = CENTRAL_CTR_EVICTION_FIFOm; 6670 break; 6671 #endif 6672 default: 6673 idb_lock = 0; 6674 break; 6675 } 6676 reg = reg_ptr[idx].reg; 6677 if ((blocktype == SOC_BLK_IPIPE || blocktype == SOC_BLK_EPIPE) && 6678 (SOC_REG_UNIQUE_ACC(unit, reg) != NULL)) { 6679 reg = SOC_REG_UNIQUE_ACC(unit, reg)[pipe]; 6680 } 6681 mem_str_ptr = reg_ptr[idx].mem_str != NULL ? 6682 reg_ptr[idx].mem_str : mem_str; 6683 6684 rv = soc_reg32_get(unit, reg, port, 0, &rval); 6685 _SOC_TH_IF_ERROR_UNLOCK_IDB_RETURN(rv); 6686 6687 multiple = 0; 6688 double_bit = 0; 6689 entry_idx = 0; 6690 6691 /* LOG_VERBOSE(BSL_LS_SOC_SER, (BSL_META_U(unit, "idb_status_reg %s, = 0x%x\n"), SOC_REG_NAME(unit, reg), rval)); */ 6692 if (SOC_REG_FIELD_VALID(unit, reg, ecc_field) && 6693 soc_reg_field_get(unit, reg, rval, ecc_field)) { 6694 has_error = TRUE; 6695 if (reg == CENTRAL_CTR_EVICTION_INTR_STATUSr) { 6696 reg = CENTRAL_CTR_EVICTION_FIFO_PARITY_ERRORr; 6697 } 6698 if (SOC_REG_FIELD_VALID(unit, reg, MULTIPLE_ERRf)) { 6699 multiple = soc_reg_field_get(unit, reg, rval, MULTIPLE_ERRf); 6700 } 6701 if (SOC_REG_FIELD_VALID(unit, reg, DOUBLE_BIT_ERRf)) { 6702 double_bit = soc_reg_field_get(unit, reg, rval, DOUBLE_BIT_ERRf); 6703 } 6704 if (SOC_REG_FIELD_VALID(unit, reg, ENTRY_IDXf)) { 6705 entry_idx = soc_reg_field_get(unit, reg, rval, ENTRY_IDXf); 6706 } else if (SOC_REG_FIELD_VALID(unit, reg, MEMINDEXf)) { 6707 entry_idx = soc_reg_field_get(unit, reg, rval, MEMINDEXf); 6708 } 6709 _soc_th_mem_parity_info(unit, block_info_idx, pipe, 6710 info->group_reg_status_field, &minfo); 6711 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 6712 SOC_SWITCH_EVENT_DATA_ERROR_ECC, 6713 SOC_SER_ERROR_ENTRY_ID_MINFO_SET | entry_idx, 6714 minfo); 6715 LOG_VERBOSE(BSL_LS_SOC_SER, 6716 (BSL_META_U(unit, 6717 "idb_status_reg %s, = 0x%x\n"), 6718 SOC_REG_NAME(unit, reg), rval)); 6719 if (double_bit) { 6720 LOG_WARN(BSL_LS_SOC_SER, 6721 (BSL_META_U(unit, 6722 "%s %s (pipe %0d) entry %d double-bit ECC error\n"), 6723 prefix_str, mem_str_ptr, pipe, entry_idx)); 6724 } else { 6725 LOG_WARN(BSL_LS_SOC_SER, 6726 (BSL_META_U(unit, 6727 "%s %s (pipe %0d) entry %d ECC error\n"), 6728 prefix_str, mem_str_ptr, pipe, entry_idx)); 6729 } 6730 if (multiple) { 6731 LOG_WARN(BSL_LS_SOC_SER, 6732 (BSL_META_U(unit, 6733 "%s %s (pipe %0d) has multiple ECC errors\n"), 6734 prefix_str, mem_str_ptr, pipe)); 6735 } 6736 6737 if (idb_lock) { /* one of the IDB_OBMn_QUEUE_ECC_STATUSr */ 6738 if (SOC_IS_TOMAHAWKPLUS(unit)) { 6739 if (double_bit) { 6740 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 6741 SOC_SWITCH_EVENT_DATA_ERROR_FATAL, 6742 INVALIDm, 6743 entry_idx); 6744 } 6745 /* SBE is turned off - so we cannot be here for SBE */ 6746 } else if (soc_feature(unit, soc_feature_th_a0_sw_war)) { 6747 /* for both SBE, DBE */ 6748 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 6749 SOC_SWITCH_EVENT_DATA_ERROR_FATAL, 6750 INVALIDm, 6751 entry_idx); 6752 } else { 6753 /* for both SBE, DBE 6754 * clear CMIC accessible OBM/CA counters */ 6755 rv = _soc_th_idb_counters_clear(unit, pipe, reg_ptr[idx].reg); 6756 _SOC_TH_IF_ERROR_UNLOCK_IDB_RETURN(rv); 6757 } 6758 } else if (IDB_IS_TDM_CAL_ECC_STATUSr == reg_ptr[idx].reg) { 6759 if (double_bit) { 6760 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 6761 SOC_SWITCH_EVENT_DATA_ERROR_FATAL, 6762 INVALIDm, 6763 entry_idx); 6764 } 6765 } 6766 6767 spci.flags = SOC_SER_SRC_MEM; 6768 if (multiple) { 6769 spci.flags |= SOC_SER_ERR_MULTI; 6770 } 6771 spci.double_bit = double_bit; 6772 spci.reg = INVALIDr; 6773 if (reg_ptr[idx].reg == IDB_IS_TDM_CAL_ECC_STATUSr) { 6774 if (entry_idx & 0x80 ) { /* MSB is set */ 6775 spci.mem = IS_TDM_CALENDAR1m; 6776 } else { 6777 spci.mem = IS_TDM_CALENDAR0m; 6778 } 6779 /* programming on each pipe can be different */ 6780 if (SOC_MEM_UNIQUE_ACC(unit, spci.mem) != NULL) { 6781 spci.mem = SOC_MEM_UNIQUE_ACC(unit, 6782 spci.mem)[pipe]; 6783 } 6784 parity_enable_reg = IDB_SER_CONTROLr; 6785 parity_enable_field = IS_TDM_ECC_ENf; 6786 } 6787 #ifdef BCM_TOMAHAWK3_SUPPORT 6788 else if(SOC_IS_TOMAHAWK3(unit) && 6789 ((reg_ptr[idx].reg == IDB_OBM0_OVERSUB_MON_ECC_STATUSr) || 6790 (reg_ptr[idx].reg == IDB_OBM1_OVERSUB_MON_ECC_STATUSr) || 6791 (reg_ptr[idx].reg == IDB_OBM2_OVERSUB_MON_ECC_STATUSr) || 6792 (reg_ptr[idx].reg == IDB_OBM3_OVERSUB_MON_ECC_STATUSr))) { 6793 if (SOC_MEM_UNIQUE_ACC(unit, spci.mem) != NULL) { 6794 spci.mem = SOC_MEM_UNIQUE_ACC(unit, spci.mem)[pipe]; 6795 } 6796 parity_enable_reg = IDB_OBM0_SER_CONTROLr; 6797 parity_enable_field = MON_ECC_ENABLEf; 6798 } 6799 #endif 6800 else { 6801 spci.mem = INVALIDm; /* non sbus-accessible */ 6802 parity_enable_reg = INVALIDr; 6803 parity_enable_field = INVALIDf; 6804 } 6805 spci.blk_type = blocktype; 6806 spci.index = entry_idx; 6807 spci.parity_type = SOC_PARITY_TYPE_ECC; 6808 spci.detect_time = sal_time_usecs(); 6809 spci.pipe_num = pipe; 6810 spci.acc_type = -1; 6811 spci.addr = (spci.mem != INVALIDm)? SOC_MEM_BASE(unit, spci.mem) : 0; 6812 if (spci.mem != INVALIDm) { 6813 spci.flags |= SOC_SER_REG_MEM_KNOWN; 6814 spci.flags |= SOC_SER_LOG_WRITE_CACHE; 6815 } 6816 if (!idb_scan_thread) { 6817 spci.log_id = _soc_th_populate_ser_log(unit, 6818 parity_enable_reg, 6819 INVALIDm, 6820 parity_enable_field, 6821 spci.mem, 6822 (spci.mem != INVALIDm) ? SOC_MEM_BLOCK_ANY(unit, spci.mem) : 0, 6823 spci.pipe_num, 6824 spci.index, 6825 spci.detect_time, 6826 spci.sblk, /* 0 */ 6827 spci.addr, 6828 1, /* disable_parity */ 6829 0, /* disable_mem_read */ 6830 0, /* disable_fill_cache_log */ 6831 1, /* force_cache_log */ 6832 FALSE, 0); 6833 } /* for idb_scan_thread, spci.log_id will be 0 */ 6834 if (spci.mem != INVALIDm) { 6835 rv = soc_ser_correction(unit, &spci); 6836 if (spci.log_id != 0) { 6837 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 6838 SOC_SWITCH_EVENT_DATA_ERROR_LOG, 6839 spci.log_id, 0); 6840 if (soc_property_get(unit, "ser_log_print_one", 0)) { 6841 soc_ser_log_print_one(unit, spci.log_id); 6842 } 6843 } 6844 if (SOC_FAILURE(rv)) { 6845 /* Add reporting failed to correct event flag to 6846 * application */ 6847 soc_event_generate(unit, 6848 SOC_SWITCH_EVENT_PARITY_ERROR, 6849 SOC_SWITCH_EVENT_DATA_ERROR_FAILEDTOCORRECT, 6850 spci.sblk | (spci.pipe_num << SOC_SER_ERROR_PIPE_BP) | 6851 SOC_SER_ERROR_DATA_BLK_ADDR_SET, spci.addr); 6852 if (idb_lock) { 6853 SOC_IDB_UNLOCK(unit); 6854 idb_lock = 0; 6855 } 6856 soc_ser_stat_update(unit, 0, spci.blk_type, 6857 spci.parity_type, 6858 spci.double_bit, 6859 SocSerCorrectTypeFailedToCorrect, 6860 stat); 6861 return rv; 6862 } 6863 } 6864 if ((spci.mem == INVALIDm) && (spci.log_id != 0)) { 6865 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 6866 SOC_SWITCH_EVENT_DATA_ERROR_LOG, 6867 spci.log_id, 0); 6868 rv = _soc_add_log_generic(unit, &spci); 6869 _SOC_TH_IF_ERROR_UNLOCK_IDB_RETURN(rv); 6870 if (soc_property_get(unit, "ser_log_print_one", 0)) { 6871 soc_ser_log_print_one(unit, spci.log_id); 6872 } 6873 } 6874 6875 if (spci.mem == INVALIDm) { 6876 /* Add reporting failed to correct event flag to application */ 6877 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 6878 SOC_SWITCH_EVENT_DATA_ERROR_FAILEDTOCORRECT, 6879 SOC_SER_ERROR_ENTRY_ID_MINFO_SET | entry_idx, minfo); 6880 soc_ser_stat_update(unit, 0, spci.blk_type, 6881 spci.parity_type, 6882 spci.double_bit, 6883 SocSerCorrectTypeNoAction, 6884 stat); 6885 } 6886 6887 /* Clear parity status */ 6888 rv = soc_reg32_set(unit, reg, port, 0, 0); 6889 _SOC_TH_IF_ERROR_UNLOCK_IDB_RETURN(rv); 6890 } 6891 if (idb_lock) { 6892 SOC_IDB_UNLOCK(unit); 6893 idb_lock = 0; 6894 } 6895 } 6896 6897 if (!has_error && !idb_scan_thread) { 6898 LOG_VERBOSE(BSL_LS_SOC_SER, 6899 (BSL_META_U(unit, 6900 "%s %s ECC hardware inconsistency (pipe %d)\n"), 6901 prefix_str, mem_str, pipe)); 6902 } 6903 return SOC_E_NONE; 6904 } 6905 6906 int 6907 soc_th_scan_idb_mem_ecc_status(int unit) 6908 { 6909 int pipe; 6910 int block_info_idx; 6911 int port = REG_PORT_ANY; 6912 char prefix_str[10]; 6913 char *mem_str = "IP IDB memory"; 6914 soc_block_t blocktype = SOC_BLK_IPIPE; 6915 static const _soc_th_ser_info_t *info = &_soc_th_idb_ser_info[0]; 6916 /* only OBM queue buffer */ 6917 int idb_scan_thread = 1; 6918 /* Scan is needed only for A0 */ 6919 sal_sprintf(prefix_str, "\nUnit: %d ", unit); 6920 SOC_BLOCK_ITER(unit, block_info_idx, blocktype) { 6921 for (pipe = 0; pipe < NUM_PIPE(unit); pipe++) { 6922 SOC_IF_ERROR_RETURN( 6923 _soc_tomahawk_ser_process_ecc(unit, 6924 block_info_idx, 6925 pipe, port, info, 6926 prefix_str, mem_str, 6927 blocktype, idb_scan_thread)); 6928 } 6929 } 6930 return SOC_E_NONE; 6931 } 6932 6933 STATIC int 6934 _soc_tomahawk_ser_process_parity(int unit, int block_info_idx, int pipe, int port, 6935 const _soc_th_ser_info_t *info, 6936 char *prefix_str, char *mem_str, 6937 soc_block_t blocktype) 6938 { 6939 _soc_th_ser_reg_t reg_entry[2], *reg_ptr; 6940 soc_reg_t reg; 6941 soc_field_t parity_error_field = PARITY_ERRORf; 6942 uint32 rval, minfo; 6943 uint32 multiple, entry_idx, idx, has_error; 6944 char *mem_str_ptr; 6945 _soc_ser_correct_info_t spci; 6946 soc_stat_t *stat = SOC_STAT(unit); 6947 6948 /* 6949 * info can be 6950 * _soc_th_idb_ser_info[] for which info->mem cannot be INVALIDm 6951 */ 6952 if (info->intr_status_reg != INVALIDr) { 6953 reg_entry[0].reg = info->intr_status_reg; 6954 reg_entry[0].mem_str = NULL; 6955 reg_entry[1].reg = INVALIDr; 6956 reg_ptr = reg_entry; 6957 } else if (info->intr_status_reg_list != NULL) { 6958 reg_ptr = info->intr_status_reg_list; 6959 } else { 6960 return SOC_E_NONE; 6961 } 6962 6963 if (INVALIDf != info->intr_status_field) { 6964 parity_error_field = info->intr_status_field; 6965 } 6966 6967 has_error = FALSE; 6968 for (idx = 0; reg_ptr[idx].reg != INVALIDr; idx++) { 6969 reg = reg_ptr[idx].reg; 6970 if ((blocktype == SOC_BLK_IPIPE || blocktype == SOC_BLK_EPIPE) && 6971 (SOC_REG_UNIQUE_ACC(unit, reg) != NULL)) { 6972 reg = SOC_REG_UNIQUE_ACC(unit, reg)[pipe]; 6973 } 6974 mem_str_ptr = reg_ptr[idx].mem_str != NULL ? 6975 reg_ptr[idx].mem_str : mem_str; 6976 6977 sal_memset(&spci, 0, sizeof(spci)); 6978 6979 SOC_IF_ERROR_RETURN 6980 (soc_reg32_get(unit, reg, port, 0, &rval)); 6981 if (soc_reg_field_get(unit, reg, rval, parity_error_field)) { 6982 has_error = TRUE; 6983 multiple = soc_reg_field_get(unit, reg, rval, MULTIPLE_ERRf); 6984 entry_idx = soc_reg_field_get(unit, reg, rval, ENTRY_IDXf); 6985 _soc_th_mem_parity_info(unit, block_info_idx, pipe, 6986 info->group_reg_status_field, &minfo); 6987 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 6988 SOC_SWITCH_EVENT_DATA_ERROR_PARITY, 6989 SOC_SER_ERROR_ENTRY_ID_MINFO_SET | entry_idx, 6990 minfo); 6991 6992 LOG_VERBOSE(BSL_LS_SOC_SER, 6993 (BSL_META_U(unit, 6994 "idb_status_reg %s, = 0x%x\n"), 6995 SOC_REG_NAME(unit, reg), rval)); 6996 LOG_WARN(BSL_LS_SOC_SER, 6997 (BSL_META_U(unit, 6998 "%s %s (pipe %0d) entry %d parity error\n"), 6999 prefix_str, mem_str_ptr, pipe, entry_idx)); 7000 if (multiple) { 7001 LOG_WARN(BSL_LS_SOC_SER, 7002 (BSL_META_U(unit, 7003 "%s %s (pipe %0d) has multiple parity errors\n"), 7004 prefix_str, mem_str_ptr, pipe)); 7005 } 7006 7007 spci.flags = SOC_SER_SRC_MEM; 7008 if (multiple) { 7009 spci.flags |= SOC_SER_ERR_MULTI; 7010 } 7011 spci.double_bit = 0; 7012 spci.reg = INVALIDr; 7013 spci.mem = info->mem; 7014 if ((spci.mem != INVALIDm) && 7015 (SOC_MEM_UNIQUE_ACC(unit, spci.mem) != NULL)) { 7016 spci.mem = SOC_MEM_UNIQUE_ACC(unit, spci.mem)[pipe]; 7017 } 7018 spci.blk_type = blocktype; 7019 spci.index = entry_idx; 7020 spci.parity_type = SOC_PARITY_TYPE_PARITY; 7021 spci.detect_time = sal_time_usecs(); 7022 spci.pipe_num = pipe; 7023 spci.acc_type = -1; 7024 spci.addr = (spci.mem != INVALIDm)? SOC_MEM_BASE(unit, spci.mem) : 0; 7025 if (spci.mem != INVALIDm) { 7026 spci.flags |= SOC_SER_REG_MEM_KNOWN; 7027 } 7028 spci.log_id = _soc_th_populate_ser_log(unit, 7029 info->enable_reg, 7030 INVALIDm, 7031 info->enable_field, 7032 spci.mem, 7033 (spci.mem != INVALIDm)? SOC_MEM_BLOCK_ANY(unit, spci.mem) : 0, 7034 spci.pipe_num, 7035 spci.index, 7036 spci.detect_time, 7037 spci.sblk, /* 0 */ 7038 spci.addr, 7039 1, /* disable_parity */ 7040 0, /* disable_mem_read */ 7041 0, /* disable_fill_cache_log */ 7042 0, /* force_cache_log */ 7043 FALSE, 0); 7044 /* for all memories in this list, ser_resonse is NONE */ 7045 7046 /* rv = soc_ser_correction(unit, &spci); */ 7047 soc_ser_stat_update(unit, 0, spci.blk_type, 7048 spci.parity_type, 7049 spci.double_bit, 7050 SocSerCorrectTypeNoAction, 7051 stat); 7052 if (spci.log_id != 0) { 7053 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 7054 SOC_SWITCH_EVENT_DATA_ERROR_LOG, 7055 spci.log_id, 0); 7056 SOC_IF_ERROR_RETURN(_soc_add_log_generic(unit, &spci)); 7057 if (soc_property_get(unit, "ser_log_print_one", 0)) { 7058 soc_ser_log_print_one(unit, spci.log_id); 7059 } 7060 } 7061 7062 /* Add reporting failed to correct event flag to application */ 7063 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 7064 SOC_SWITCH_EVENT_DATA_ERROR_FAILEDTOCORRECT, 7065 SOC_SER_ERROR_ENTRY_ID_MINFO_SET | entry_idx, minfo); 7066 7067 /* Clear parity status */ 7068 SOC_IF_ERROR_RETURN 7069 (soc_reg32_set(unit, reg, port, 0, 0)); 7070 } 7071 } 7072 7073 if (!has_error) { 7074 LOG_VERBOSE(BSL_LS_SOC_SER, 7075 (BSL_META_U(unit, 7076 "%s %s parity hardware inconsistency (pipe %d)\n"), 7077 prefix_str, mem_str, pipe)); 7078 } 7079 7080 return SOC_E_NONE; 7081 } 7082 7083 STATIC int 7084 _soc_tomahawk_ser_process_mac(int unit, int block_info_idx, int pipe, int port, 7085 const _soc_th_ser_info_t *info, 7086 int schan, char *prefix_str, char *mem_str, soc_block_t blocktype) 7087 { 7088 _soc_th_ser_reg_t reg_entry[2], *reg_ptr; 7089 soc_reg_t reg; 7090 soc_field_t single_bit_f, double_bit_f; 7091 uint64 rval; 7092 uint32 single_bit = 0, double_bit = 0, idx; 7093 char *mem_str_ptr; 7094 uint32 has_error = FALSE, db = FALSE; 7095 soc_stat_t *stat = SOC_STAT(unit); 7096 7097 if (schan) { 7098 /* Some table does not have NACK register */ 7099 return SOC_E_NONE; 7100 } else { 7101 if (info->intr_status_reg != INVALIDr) { 7102 reg_entry[0].reg = info->intr_status_reg; 7103 reg_entry[0].mem_str = NULL; 7104 reg_entry[1].reg = INVALIDr; 7105 reg_ptr = reg_entry; 7106 } else if (info->intr_status_reg_list != NULL) { 7107 reg_ptr = info->intr_status_reg_list; 7108 } else { 7109 return SOC_E_NONE; 7110 } 7111 } 7112 7113 switch (info->type) { 7114 case _SOC_PARITY_TYPE_MAC_TX_CDC: 7115 #ifdef BCM_TOMAHAWK3_SUPPORT 7116 if (SOC_IS_TOMAHAWK3(unit)) { 7117 single_bit_f = SUM_TX_CDC_SINGLE_BIT_ERRf; 7118 double_bit_f = SUM_TX_CDC_DOUBLE_BIT_ERRf; 7119 } else 7120 #endif 7121 { 7122 single_bit_f = TX_CDC_SINGLE_BIT_ERRf; 7123 double_bit_f = TX_CDC_DOUBLE_BIT_ERRf; 7124 } 7125 break; 7126 case _SOC_PARITY_TYPE_MAC_RX_CDC: 7127 #ifdef BCM_TOMAHAWK3_SUPPORT 7128 if (SOC_IS_TOMAHAWK3(unit)) { 7129 single_bit_f = SUM_RX_CDC_SINGLE_BIT_ERRf; 7130 double_bit_f = SUM_RX_CDC_DOUBLE_BIT_ERRf; 7131 } else 7132 #endif 7133 { 7134 single_bit_f = RX_CDC_SINGLE_BIT_ERRf; 7135 double_bit_f = RX_CDC_DOUBLE_BIT_ERRf; 7136 } 7137 break; 7138 case _SOC_PARITY_TYPE_MAC_RX_TS: 7139 single_bit_f = RX_TS_MEM_SINGLE_BIT_ERRf; 7140 double_bit_f = RX_TS_MEM_DOUBLE_BIT_ERRf; 7141 break; 7142 default: 7143 return SOC_E_PARAM; 7144 } 7145 7146 for (idx = 0; reg_ptr[idx].reg != INVALIDr; idx++) { 7147 reg = reg_ptr[idx].reg; 7148 mem_str_ptr = reg_ptr[idx].mem_str != NULL ? reg_ptr[idx].mem_str : mem_str; 7149 7150 if (!(SOC_REG_FIELD_VALID(unit, reg, single_bit_f) && 7151 SOC_REG_FIELD_VALID(unit, reg, double_bit_f))) { 7152 continue; 7153 } 7154 SOC_IF_ERROR_RETURN(soc_reg64_get(unit, reg, port, 0, &rval)); 7155 7156 single_bit = soc_reg64_field32_get(unit, reg, rval, single_bit_f); 7157 double_bit = soc_reg64_field32_get(unit, reg, rval, double_bit_f); 7158 if (single_bit || double_bit) { 7159 has_error = TRUE; 7160 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 7161 SOC_SWITCH_EVENT_DATA_ERROR_ECC, 0, 0); 7162 if (double_bit) { 7163 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 7164 SOC_SWITCH_EVENT_DATA_ERROR_UNCORRECTABLE, 0, 0); 7165 LOG_WARN(BSL_LS_SOC_SER, 7166 (BSL_META_U(unit, 7167 "%s %s double-bit ECC error on port %d\n"), 7168 prefix_str, mem_str_ptr, port)); 7169 db = TRUE; 7170 } else { 7171 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 7172 SOC_SWITCH_EVENT_DATA_ERROR_AUTO_CORRECTED, 0, 0); 7173 LOG_WARN(BSL_LS_SOC_SER, 7174 (BSL_META_U(unit, 7175 "%s %s single-bit ECC error on port %d\n"), 7176 prefix_str, mem_str_ptr, port)); 7177 } 7178 } 7179 7180 if (info->intr_clr_reg == INVALIDr) { 7181 continue; 7182 } 7183 7184 /* Clear parity status by a rising edge on intr_clr_field in intr_clr_reg */ 7185 #ifdef BCM_TOMAHAWK3_SUPPORT 7186 if (SOC_IS_TOMAHAWK3(unit)) { 7187 SOC_IF_ERROR_RETURN 7188 (soc_reg64_get(unit, info->intr_clr_reg, port, 0, &rval)); 7189 soc_reg64_field32_set(unit, info->intr_clr_reg, &rval, info->intr_clr_field, 0); 7190 SOC_IF_ERROR_RETURN 7191 (soc_reg64_set(unit, info->intr_clr_reg, port, 0, rval)); 7192 soc_reg64_field32_set(unit, info->intr_clr_reg, &rval, info->intr_clr_field, 1); 7193 SOC_IF_ERROR_RETURN 7194 (soc_reg64_set(unit, info->intr_clr_reg, port, 0, rval)); 7195 soc_reg64_field32_set(unit, info->intr_clr_reg, &rval, info->intr_clr_field, 0); 7196 SOC_IF_ERROR_RETURN 7197 (soc_reg64_set(unit, info->intr_clr_reg, port, 0, rval)); 7198 } else 7199 #endif 7200 { 7201 SOC_IF_ERROR_RETURN 7202 (soc_reg64_get(unit, info->intr_clr_reg, port, 0, &rval)); 7203 if (single_bit) { 7204 soc_reg64_field32_set(unit, info->intr_clr_reg, &rval, info->intr_clr_field_list[0], 0); 7205 SOC_IF_ERROR_RETURN 7206 (soc_reg64_set(unit, info->intr_clr_reg, port, 0, rval)); 7207 soc_reg64_field32_set(unit, info->intr_clr_reg, &rval, info->intr_clr_field_list[0], 1); 7208 SOC_IF_ERROR_RETURN 7209 (soc_reg64_set(unit, info->intr_clr_reg, port, 0, rval)); 7210 soc_reg64_field32_set(unit, info->intr_clr_reg, &rval, info->intr_clr_field_list[0], 0); 7211 SOC_IF_ERROR_RETURN 7212 (soc_reg64_set(unit, info->intr_clr_reg, port, 0, rval)); 7213 } 7214 if (double_bit) { 7215 soc_reg64_field32_set(unit, info->intr_clr_reg, &rval, info->intr_clr_field_list[1], 0); 7216 SOC_IF_ERROR_RETURN 7217 (soc_reg64_set(unit, info->intr_clr_reg, port, 0, rval)); 7218 soc_reg64_field32_set(unit, info->intr_clr_reg, &rval, info->intr_clr_field_list[1], 1); 7219 SOC_IF_ERROR_RETURN 7220 (soc_reg64_set(unit, info->intr_clr_reg, port, 0, rval)); 7221 soc_reg64_field32_set(unit, info->intr_clr_reg, &rval, info->intr_clr_field_list[1], 0); 7222 SOC_IF_ERROR_RETURN 7223 (soc_reg64_set(unit, info->intr_clr_reg, port, 0, rval)); 7224 } 7225 } 7226 } 7227 7228 if (has_error) { 7229 soc_ser_stat_update(unit, 0, blocktype, SOC_PARITY_TYPE_PARITY, 7230 db, SocSerCorrectTypeNoAction, stat); 7231 } 7232 7233 return SOC_E_NONE; 7234 } 7235 7236 STATIC int 7237 _soc_tomahawk_process_ser(int unit, int block_info_idx, int inst, int pipe, 7238 int port, soc_reg_t group_reg, uint64 group_rval, 7239 const _soc_th_ser_info_t *info_list, 7240 soc_block_t blocktype, 7241 char *prefix_str) 7242 { 7243 const _soc_th_ser_info_t *info; 7244 int info_index; 7245 char *mem_str; 7246 uint64 rval64; 7247 uint32 rval; 7248 /*uint32 minfo;*/ 7249 7250 /* This func (_soc_tomahawk_process_ser) is called by 7251 * _soc_tomahawk_ser_process_all which passes 7252 * _soc_th_mmu_top_ser_info[] as param to this func. 7253 * And, _soc_th_mmu_top_ser_info[] list has only one entry with type 7254 * _SOC_PARITY_TYPE_MMU_SER and 'info' for that entry pointing to 7255 * _soc_th_mmu_ser_info 7256 */ 7257 for (info_index = 0; ; info_index++) { /* Loop through each info entry in the mmu_top_ser_info list */ 7258 info = &info_list[info_index]; /* LHS points to 1st entry in _soc_th_mmu_top_ser_info[] */ 7259 if (info->type == _SOC_PARITY_TYPE_NONE) { 7260 /* End of table */ 7261 break; 7262 } 7263 7264 if (group_reg != INVALIDr) { 7265 /* Check status for the info entry in the group register */ 7266 /* for SOC_BLK_MMU, group_reg is INVALIDr */ 7267 if (!soc_reg64_field32_get(unit, group_reg, group_rval, 7268 info->group_reg_status_field)) { 7269 continue; 7270 } 7271 } 7272 7273 if (info->mem_str) { 7274 mem_str = info->mem_str; /* "MMU MME PAR" for SOC_BLK_MMU */ 7275 } else if (info->mem != INVALIDm) { 7276 mem_str = SOC_MEM_NAME(unit, info->mem); 7277 } else { 7278 mem_str = SOC_FIELD_NAME(unit, info->group_reg_status_field); 7279 } 7280 7281 /* Handle different parity error reporting style */ 7282 switch (info->type) { 7283 7284 case _SOC_PARITY_TYPE_MMU_SER: 7285 /* we can never be here for following 3 types. 7286 * _soc_th_mmu_top_ser_info has only one entry with type 7287 * _SOC_PARITY_TYPE_MMU_SER 7288 */ 7289 case _SOC_PARITY_TYPE_MMU_GLB: 7290 case _SOC_PARITY_TYPE_MMU_XPE: 7291 case _SOC_PARITY_TYPE_MMU_SC: 7292 #ifdef BCM_TOMAHAWK2_SUPPORT 7293 case _SOC_PARITY_TYPE_MMU_SED: 7294 #endif 7295 #ifdef BCM_TOMAHAWK3_SUPPORT 7296 case _SOC_PARITY_TYPE_MMU_ITMCFG: 7297 case _SOC_PARITY_TYPE_MMU_EBCFG: 7298 #endif 7299 SOC_IF_ERROR_RETURN 7300 (_soc_tomahawk_ser_process_mmu_err(unit, block_info_idx, 7301 info, prefix_str, -1)); 7302 /* info points to _soc_th_mmu_top_ser_info[0] */ 7303 break; 7304 case _SOC_PARITY_TYPE_ECC: 7305 SOC_IF_ERROR_RETURN 7306 (_soc_tomahawk_ser_process_ecc(unit, block_info_idx, pipe, 7307 port, info, prefix_str, 7308 mem_str, blocktype, 0)); 7309 if ((info->group_reg_status_field == MIB_RX_MEM_ERRf) || 7310 (info->group_reg_status_field == MIB_TX_MEM_ERRf)) { 7311 COMPILER_64_ZERO(rval64); 7312 soc_reg64_field32_set(unit, group_reg, &rval64, 7313 info->group_reg_status_field, 1); 7314 SOC_IF_ERROR_RETURN 7315 (soc_reg_set(unit, group_reg, port, 0, rval64)); 7316 } 7317 break; 7318 case _SOC_PARITY_TYPE_PARITY: 7319 SOC_IF_ERROR_RETURN 7320 (_soc_tomahawk_ser_process_parity(unit, block_info_idx, pipe, 7321 port, info, prefix_str, 7322 mem_str, blocktype)); 7323 break; 7324 #if defined (BCM_TOMAHAWK2_SUPPORT) || defined (BCM_TOMAHAWKPLUS_SUPPORT) 7325 case _SOC_PARITY_TYPE_CLMAC: 7326 SOC_IF_ERROR_RETURN 7327 (_soc_tomahawk_ser_process_clmac(unit, block_info_idx, info, 7328 prefix_str, mem_str, blocktype)); 7329 break; 7330 #endif 7331 #ifdef BCM_TOMAHAWK3_SUPPORT 7332 case _SOC_PARITY_TYPE_CDMAC: 7333 SOC_IF_ERROR_RETURN 7334 (_soc_tomahawk_ser_process_cdmac(unit, block_info_idx, info, 7335 prefix_str, mem_str, blocktype)); 7336 break; 7337 #endif 7338 case _SOC_PARITY_TYPE_MAC_TX_CDC: 7339 case _SOC_PARITY_TYPE_MAC_RX_CDC: 7340 case _SOC_PARITY_TYPE_MAC_RX_TS: 7341 /* xxx_SINGLE_BIT_ERRf, xxx_DOUBLE_BIT_ERRf */ 7342 SOC_IF_ERROR_RETURN 7343 (_soc_tomahawk_ser_process_mac(unit, block_info_idx, pipe, 7344 port, info, FALSE, 7345 prefix_str, mem_str, blocktype)); 7346 if ((info->group_reg_status_field == MAC_RX_CDC_MEM_ERRf) || 7347 (info->group_reg_status_field == MAC_TX_CDC_MEM_ERRf) || 7348 (info->group_reg_status_field == MAC_RX_TS_CDC_MEM_ERRf)) { 7349 rval = 0; 7350 soc_reg_field_set(unit, group_reg, &rval, 7351 info->group_reg_status_field, 1); 7352 SOC_IF_ERROR_RETURN 7353 (soc_reg32_set(unit, group_reg, port, 0, rval)); 7354 } 7355 break; 7356 default: 7357 break; 7358 } /* Handle different parity error reporting style */ 7359 } /* Loop through each info entry in the list */ 7360 7361 return SOC_E_NONE; 7362 } 7363 7364 #ifdef BCM_TOMAHAWK3_SUPPORT 7365 STATIC char *_soc_th3_ser_hwmem_base_info[] = { 7366 /* from SER_STATUS_BUS format in regsfile */ 7367 "Invalid value", /* 0x0 */ 7368 "IARB_EVENT_FIFO", /* 0x1 */ 7369 "Invalid value", /* 0x2 */ 7370 "Invalid value", /* 0x3 */ 7371 "Invalid value", /* 0x4 */ 7372 "Invalid value", /* 0x5 */ 7373 "Invalid value", /* 0x6 */ 7374 "INGRESS_PACKET_BUFFER", /* 0x7 */ 7375 "Invalid value", /* 0x8 */ 7376 "ISW_EOP_BUFFER_B", /* 0x9 */ 7377 "Invalid value", /* 0xa */ 7378 "IADAPT_PASSTHRU", /* 0xb */ 7379 "Invalid value", /* 0xc */ 7380 "Invalid value", /* 0xd */ 7381 "Invalid value", /* 0xe */ 7382 "IPARS_ISW_PT_BUF", /* 0xf */ 7383 "IFWD1_PASSTHRU", /* 0x10 */ 7384 "Invalid value", /* 0x11 */ 7385 "Invalid value", /* 0x12 */ 7386 "Invalid value", /* 0x13 */ 7387 "Invalid value", /* 0x14 */ 7388 "Invalid value", /* 0x15 */ 7389 "Invalid value", /* 0x16 */ 7390 "IFP_BUS", /* 0x17 */ 7391 "IRSEL_PT_BUF", /* 0x18 */ 7392 "IRSEL_BUS", /* 0x19 */ 7393 "Invalid value", /* 0x1a */ 7394 "Invalid value", /* 0x1b */ 7395 "Invalid value", /* 0x1c */ 7396 "Invalid value", /* 0x1d */ 7397 "Invalid value", /* 0x1e */ 7398 "Invalid value", /* 0x1f */ 7399 "Invalid value", /* 0x20 */ 7400 "Invalid value", /* 0x21 */ 7401 "Invalid value", /* 0x22 */ 7402 "Invalid value", /* 0x23 */ 7403 "Invalid value", /* 0x24 */ 7404 "Invalid value", /* 0x25 */ 7405 "Invalid value", /* 0x26 */ 7406 "Invalid value", /* 0x27 */ 7407 "Invalid value", /* 0x28 */ 7408 "Invalid value", /* 0x29 */ 7409 "Invalid value", /* 0x2a */ 7410 "Invalid value", /* 0x2b */ 7411 "Invalid value", /* 0x2c */ 7412 "Invalid value", /* 0x2d */ 7413 "Invalid value", /* 0x2e */ 7414 "Invalid value", /* 0x2f */ 7415 "Invalid value", /* 0x30 */ 7416 "Invalid value", /* 0x31 */ 7417 "Invalid value", /* 0x32 */ 7418 "Invalid value", /* 0x33 */ 7419 "Invalid value", /* 0x34 */ 7420 "Invalid value", /* 0x35 */ 7421 "Invalid value", /* 0x36 */ 7422 "Invalid value", /* 0x37 */ 7423 "CENTRAL_EVICTION_FIFO", /* 0x38 */ 7424 "Invalid value", /* 0x39 */ 7425 "Invalid value", /* 0x3a */ 7426 "Invalid value", /* 0x3b */ 7427 "Invalid value", /* 0x3c */ 7428 "Invalid value", /* 0x3d */ 7429 "Invalid value", /* 0x3e */ 7430 "Invalid value", /* 0x3f */ 7431 "EP_MPB_DATA", /* 0x40 */ 7432 "EP_PACKET_DATA", /* 0x41 */ 7433 "EARB_SOP_EVENT_FIFO", /* 0x42 */ 7434 "Invalid value", /* 0x43 */ 7435 "Invalid value", /* 0x44 */ 7436 "Invalid value", /* 0x45 */ 7437 "Invalid value", /* 0x46 */ 7438 "Invalid value", /* 0x47 */ 7439 "Invalid value", /* 0x48 */ 7440 "Invalid value", /* 0x49 */ 7441 "Invalid value", /* 0x4a */ 7442 "Invalid value", /* 0x4b */ 7443 "Invalid value", /* 0x4c */ 7444 "Invalid value", /* 0x4d */ 7445 "Invalid value", /* 0x4e */ 7446 "Invalid value", /* 0x4f */ 7447 "Invalid value", /* 0x50 */ 7448 "Invalid value", /* 0x51 */ 7449 "Invalid value", /* 0x52 */ 7450 "Invalid value", /* 0x53 */ 7451 "Invalid value", /* 0x54 */ 7452 "Invalid value", /* 0x55 */ 7453 "Invalid value", /* 0x56 */ 7454 "Invalid value", /* 0x57 */ 7455 "Invalid value", /* 0x58 */ 7456 "Invalid value", /* 0x59 */ 7457 "Invalid value", /* 0x5a */ 7458 "Invalid value", /* 0x5b */ 7459 "EGR_PMOD_BUS", /* 0x5c */ 7460 "EGR_FPPARS_BUS", /* 0x5d */ 7461 "EFP_BUS", /* 0x5e */ 7462 "Invalid value", /* 0x5f */ 7463 "EP_EFPBUF", /* 0x60 */ 7464 "Invalid value", /* 0x61 */ 7465 "Invalid value", /* 0x62 */ 7466 "Invalid value", /* 0x63 */ 7467 "EPOST_OUTPUT_FIFO", /* 0x64 */ 7468 "EPOST_SLOT_PIPELINE", /* 0x65 */ 7469 "EPOST_PKT_BUF", /* 0x66 */ 7470 "EDB_RESIDUAL_DATA_BUF", /* 0x67 */ 7471 "EDB_XMIT_START_COUNT", /* 0x68 */ 7472 "EDB_PM0_EOP_STATUS", /* 0x69 */ 7473 "EDB_PM0_CTRL_FIFO", /* 0x6a */ 7474 "EDB_PM0_DATA_FIFO", /* 0x6b */ 7475 "EDB_PM1_EOP_STATUS", /* 0x6c */ 7476 "EDB_PM1_CTRL_FIFO", /* 0x6d */ 7477 "EDB_PM1_DATA_FIFO", /* 0x6e */ 7478 "EDB_PM2_EOP_STATUS", /* 0x6f */ 7479 "EDB_PM2_CTRL_FIFO", /* 0x70 */ 7480 "EDB_PM2_DATA_FIFO", /* 0x71 */ 7481 "EDB_PM3_EOP_STATUS", /* 0x72 */ 7482 "EDB_PM3_CTRL_FIFO", /* 0x73 */ 7483 "EDB_PM3_DATA_FIFO", /* 0x74 */ 7484 "EDB_CM_EOP_STATUS", /* 0x75 */ 7485 "EDB_CM_CTRL_FIFO", /* 0x76 */ 7486 "EDB_CM_DATA_FIFO", /* 0x77 */ 7487 "EDB_LPBK_EOP_STATUS", /* 0x78 */ 7488 "EDB_LPBK_CTRL_FIFO", /* 0x79 */ 7489 "EDB_LPBK_DATA_FIFO" /* 0x7a */ 7490 }; 7491 #endif 7492 STATIC char *_soc_th_ser_hwmem_base_info[] = { 7493 /* from SER_STATUS_BUS format in regsfile */ 7494 "OBM_QUEUE_FIFO - In Idb", /* 0x0 */ 7495 "OBM_DATA_FIFO - In Idb", /* 0x1 */ 7496 "CELL_ASSEM_BUFFER - In Idb", /* 0x2 */ 7497 "CPU_CELL_ASSEM_BUFFER - In Idb", /* 0x3 */ 7498 "LPBK_CELL_ASSEM_BUFFER - In Idb", /* 0x4 */ 7499 "Invalid value", /* 0x5 */ 7500 "Invalid value", /* 0x6 */ 7501 "INGRESS_PACKET_BUFFER - In Ipars", /* 0x7 */ 7502 "ISW3_EOP_BUFFER_A - In Isw3", /* 0x8 */ 7503 "ISW3_EOP_BUFFER_B - In Isw3", /* 0x9 */ 7504 "BUBBLE_MOP - In Isw2", /* 0xa */ 7505 "IPARS_IVP_PT_BUS - In Ivp, Passthru Highway bus", /* 0xb */ 7506 "IVP_ISW1_PT_BUS - In Isw1, Passthru Highway bus", /* 0xc */ 7507 "IFWD_ISW1_PT_BUS - In Isw1, Passthru Highway bus", /* 0xd */ 7508 "Invalid value", /* 0xe */ 7509 "ISW1_ISW2_PT_BUS - In Isw2, Passthru Highway bus", /* 0xf */ 7510 "ICFG_BUS - PassThrought bus parity check, MEMINDEX is 0", /* 0x10 */ 7511 "IPARS_BUS - PassThrought bus parity check, MEMINDEX is 0", /* 0x11 */ 7512 "IVXLT_BUS - PassThrought bus parity check, MEMINDEX is 0", /* 0x12 */ 7513 "IVP_BUS - PassThrought bus parity check, MEMINDEX is 0", /* 0x13 */ 7514 "IFWD_BUS - PassThrought bus parity check, MEMINDEX is 0", /* 0x14 */ 7515 "IRSEL1_BUS - PassThrought bus parity check, MEMINDEX is 0", /* 0x15 */ 7516 "ISW1_BUS - PassThrought bus parity check, MEMINDEX is 0", /* 0x16 */ 7517 "IFP_BUS - PassThrought bus parity check, MEMINDEX is 0", /* 0x17 */ 7518 "IRSEL2_BUS - PassThrought bus parity check, MEMINDEX is 0", /* 0x18 */ 7519 "ISW2_BUS - PassThrought bus parity check, MEMINDEX is 0", /* 0x19 */ 7520 "Invalid value", /* 0x1a */ 7521 "Invalid value", /* 0x1b */ 7522 "Invalid value", /* 0x1c */ 7523 "Invalid value", /* 0x1d */ 7524 "Invalid value", /* 0x1e */ 7525 "Invalid value", /* 0x1f */ 7526 "Invalid value", /* 0x20 */ 7527 "Invalid value", /* 0x21 */ 7528 "Invalid value", /* 0x22 */ 7529 "Invalid value", /* 0x23 */ 7530 "Invalid value", /* 0x24 */ 7531 "Invalid value", /* 0x25 */ 7532 "Invalid value", /* 0x26 */ 7533 "Invalid value", /* 0x27 */ 7534 "Invalid value", /* 0x28 */ 7535 "Invalid value", /* 0x29 */ 7536 "Invalid value", /* 0x2a */ 7537 "Invalid value", /* 0x2b */ 7538 "Invalid value", /* 0x2c */ 7539 "Invalid value", /* 0x2d */ 7540 "Invalid value", /* 0x2e */ 7541 "Invalid value", /* 0x2f */ 7542 "LEARN_FIFO - In L2MM", /* 0x30 */ 7543 "Invalid value", /* 0x31 */ 7544 "Invalid value", /* 0x32 */ 7545 "Invalid value", /* 0x33 */ 7546 "Invalid value", /* 0x34 */ 7547 "Invalid value", /* 0x35 */ 7548 "Invalid value", /* 0x36 */ 7549 "Invalid value", /* 0x37 */ 7550 "CENTRAL_EVICTION_FIFO - In CEV", /* 0x38 */ 7551 "Invalid value", /* 0x39 */ 7552 "Invalid value", /* 0x3a */ 7553 "Invalid value", /* 0x3b */ 7554 "Invalid value", /* 0x3c */ 7555 "Invalid value", /* 0x3d */ 7556 "Invalid value", /* 0x3e */ 7557 "Invalid value", /* 0x3f */ 7558 "EP_MPB_DATA - In El3", /* 0x40 */ 7559 "EP_INITBUF - In Ehcpm", /* 0x41 */ 7560 "CM_DATA_BUFFER - In Edatabuf", /* 0x42 */ 7561 "PM0_DATA_BUFFER - In Edatabuf", /* 0x43 */ 7562 "PM1_DATA_BUFFER - In Edatabuf", /* 0x44 */ 7563 "PM2_DATA_BUFFER - In Edatabuf", /* 0x45 */ 7564 "PM3_DATA_BUFFER - In Edatabuf", /* 0x46 */ 7565 "PM4_DATA_BUFFER - In Edatabuf", /* 0x47 */ 7566 "PM5_DATA_BUFFER - In Edatabuf", /* 0x48 */ 7567 "PM6_DATA_BUFFER - In Edatabuf", /* 0x49 */ 7568 "PM7_DATA_BUFFER - In Edatabuf", /* 0x4a */ 7569 "LBP_DATA_BUFFER - In Edatabuf", /* 0x4b */ 7570 "PM_RESI0_DATA_BUFFER - In Edatabuf", /* 0x4c */ 7571 "PM_RESI1_DATA_BUFFER - In Edatabuf", /* 0x4d */ 7572 "Invalid value", /* 0x4e */ 7573 "Invalid value", /* 0x4f */ 7574 "CM_EDB_CTRL_BUFFER - In Edatabuf", /* 0x50 */ 7575 "PM0_EDB_CTRL_BUFFER - In Edatabuf", /* 0x51 */ 7576 "PM1_EDB_CTRL_BUFFER - In Edatabuf", /* 0x52 */ 7577 "PM2_EDB_CTRL_BUFFER - In Edatabuf", /* 0x53 */ 7578 "PM3_EDB_CTRL_BUFFER - In Edatabuf", /* 0x54 */ 7579 "PM4_EDB_CTRL_BUFFER - In Edatabuf", /* 0x55 */ 7580 "PM5_EDB_CTRL_BUFFER - In Edatabuf", /* 0x56 */ 7581 "PM6_EDB_CTRL_BUFFER - In Edatabuf", /* 0x57 */ 7582 "PM7_EDB_CTRL_BUFFER - In Edatabuf", /* 0x58 */ 7583 "LBP_EDB_CTRL_BUFFER - In Edatabuf", /* 0x59 */ 7584 "EGR_VLAN_BUS - PassThrought bus parity check, MEMINDEX is 0", /* 0x5a */ 7585 "EGR_HCPM_BUS - PassThrought bus parity check, MEMINDEX is 0", /* 0x5b */ 7586 "EGR_PMOD_BUS - PassThrought bus parity check, MEMINDEX is 0", /* 0x5c */ 7587 "EGR_FPPARS_BUS - PassThrought bus parity check, MEMINDEX is 0", /* 0x5d */ 7588 "EFP_BUS - PassThrought bus parity check, MEMINDEX is 0", /* 0x5e */ 7589 "EP_PT_BUS - In Esw, Passthru Highway bus" /* 0x5f */ 7590 }; 7591 7592 #define _SOC_TH_SER_REG 1 7593 #define _SOC_TH_SER_MEM 0 7594 7595 STATIC void 7596 _soc_tomahawk_print_ser_fifo_details(int unit, uint8 regmem, soc_block_t blk, 7597 uint32 sblk, int pipe, uint32 address, 7598 uint32 stage, uint32 base, uint32 index, 7599 uint32 type, uint8 drop, uint8 non_sbus, 7600 int l2_mgmt_ser_fifo) 7601 { 7602 if (bsl_check(bslLayerSoc, bslSourceCommon, bslSeverityError, unit)) { 7603 switch (type) { 7604 case 0: 7605 LOG_WARN(BSL_LS_SOC_SER, 7606 (BSL_META_U(unit, 7607 "Error in: SOP cell.\n"))); 7608 break; 7609 case 1: 7610 LOG_WARN(BSL_LS_SOC_SER, 7611 (BSL_META_U(unit, 7612 "Error in: MOP cell.\n"))); 7613 break; 7614 case 2: 7615 LOG_WARN(BSL_LS_SOC_SER, 7616 (BSL_META_U(unit, 7617 "Error in: EOP cell.\n"))); 7618 break; 7619 case 3: 7620 LOG_WARN(BSL_LS_SOC_SER, 7621 (BSL_META_U(unit, 7622 "Error in: SBUS transaction.\n"))); 7623 break; 7624 case 4: 7625 LOG_WARN(BSL_LS_SOC_SER, 7626 (BSL_META_U(unit, 7627 "Error in: transaction - refresh, aging etc.\n"))); 7628 break; 7629 default: 7630 LOG_ERROR(BSL_LS_SOC_SER, 7631 (BSL_META_U(unit, 7632 "Invalid error reported !!\n"))); 7633 } 7634 LOG_WARN(BSL_LS_SOC_SER, 7635 (BSL_META_U(unit, 7636 "Blk: %d, Pipe: %d, Address: 0x%08x, base: 0x%x, " 7637 "stage: %d, index: %d\n"), 7638 sblk, pipe, address, base, stage, index)); 7639 if (regmem == _SOC_TH_SER_MEM) { 7640 if (l2_mgmt_ser_fifo) { 7641 if (non_sbus) { 7642 LOG_WARN(BSL_LS_SOC_SER, 7643 (BSL_META_U(unit, 7644 "unit %0d: L2 LEARN_FIFO parity " 7645 "error\n"), 7646 unit)); 7647 } else { 7648 LOG_WARN(BSL_LS_SOC_SER, 7649 (BSL_META_U(unit, 7650 "unit %0d: L2_MOD_FIFO parity " 7651 "error\n"), 7652 unit)); 7653 } 7654 } else { 7655 if (non_sbus) { 7656 #ifdef BCM_TOMAHAWK3_SUPPORT 7657 if (SOC_IS_TOMAHAWK3(unit)) { 7658 LOG_WARN(BSL_LS_SOC_SER, 7659 (BSL_META_U(unit, 7660 "Mem hwbase: 0x%x [%s]\n"), base, 7661 _soc_th3_ser_hwmem_base_info[base])); 7662 } else 7663 #endif 7664 { 7665 LOG_WARN(BSL_LS_SOC_SER, 7666 (BSL_META_U(unit, 7667 "Mem hwbase: 0x%x [%s]\n"), base, 7668 _soc_th_ser_hwmem_base_info[base])); 7669 } 7670 } 7671 } 7672 } 7673 if (drop) { 7674 LOG_WARN(BSL_LS_SOC_SER, 7675 (BSL_META_U(unit, 7676 "SER caused packet drop.\n"))); 7677 } 7678 } 7679 } 7680 7681 STATIC uint32 7682 _soc_th_check_flex_ctr_addr(int unit, uint32 address, soc_block_t blk, uint32 stage, 7683 uint32 index) 7684 { 7685 uint32 index2 = index; 7686 if ((SOC_BLK_IPIPE == blk) && (21 == stage)) { 7687 switch (address & 0xfffff000) { 7688 /* pool 0 */ 7689 case 0x56800000: 7690 case 0x56801000: 7691 case 0x56802000: 7692 case 0x56803000: 7693 7694 case 0x56804000: 7695 case 0x56808000: 7696 case 0x5680c000: 7697 case 0x56810000: 7698 7699 /* pool 1 */ 7700 case 0x56820000: 7701 case 0x56821000: 7702 case 0x56822000: 7703 case 0x56823000: 7704 7705 case 0x56824000: 7706 case 0x56828000: 7707 case 0x5682c000: 7708 case 0x56830000: 7709 7710 /* pool 2 */ 7711 case 0x56840000: 7712 case 0x56841000: 7713 case 0x56842000: 7714 case 0x56843000: 7715 7716 case 0x56844000: 7717 case 0x56848000: 7718 case 0x5684c000: 7719 case 0x56850000: 7720 7721 /* pool 3 */ 7722 case 0x56880000: 7723 case 0x56881000: 7724 case 0x56882000: 7725 case 0x56883000: 7726 7727 case 0x56884000: 7728 case 0x56888000: 7729 case 0x5688c000: 7730 case 0x56890000: 7731 7732 /* pool 4 */ 7733 case 0x568a0000: 7734 case 0x568a1000: 7735 case 0x568a2000: 7736 case 0x568a3000: 7737 7738 case 0x568a4000: 7739 case 0x568a8000: 7740 case 0x568ac000: 7741 case 0x568b0000: 7742 index2 = address & 0xfff; break; /* 4K depth */ 7743 default: 7744 break; 7745 } 7746 } else if ((SOC_BLK_EPIPE == blk) && (10 == stage)) { 7747 switch (address & 0xfffff000) { 7748 /* pool 0 */ 7749 case 0x2a800000: 7750 case 0x2a801000: 7751 case 0x2a802000: 7752 case 0x2a803000: 7753 7754 case 0x2a804000: 7755 case 0x2a808000: 7756 case 0x2a80c000: 7757 case 0x2a810000: 7758 index2 = address & 0xfff; break; /* 4K depth */ 7759 default: 7760 break; 7761 } 7762 } 7763 if (index2 != index) { 7764 LOG_VERBOSE(BSL_LS_SOC_SER, 7765 (BSL_META_U(unit, 7766 "flex_ctr_addr_detected: index %d was remapped " 7767 "to %d\n"), 7768 index, index2)); 7769 } 7770 return index2; 7771 } 7772 7773 STATIC int 7774 _soc_th_check_counter_with_ecc(int unit, soc_mem_t mem) 7775 { 7776 int mem_is_ctr_with_ecc = 0; 7777 7778 if ((mem != INVALIDm) && 7779 SOC_MEM_IS_VALID(unit, mem) && 7780 (SOC_MEM_INFO(unit, mem).flags & SOC_MEM_FLAG_SER_ENTRY_CLEAR) && 7781 SOC_MEM_FIELD_VALID(unit, mem, ECCf)) { 7782 mem_is_ctr_with_ecc = 1; 7783 } 7784 if (mem_is_ctr_with_ecc) { 7785 LOG_VERBOSE(BSL_LS_SOC_SER, 7786 (BSL_META_U(unit, 7787 "counter_with_ecc_detected: mem %s \n"), 7788 SOC_MEM_NAME(unit, mem))); 7789 } 7790 return mem_is_ctr_with_ecc; 7791 } 7792 7793 STATIC int 7794 _soc_th_force_unique_mode(int unit, soc_mem_t mem) 7795 { 7796 int force_unique_mode = 0; 7797 7798 if (!SOC_MEM_IS_VALID(unit, mem)) { 7799 return 0; 7800 } 7801 if (((SOC_MEM_INFO(unit, mem).flags & SOC_MEM_FLAG_SER_ENTRY_CLEAR) && 7802 SOC_MEM_FIELD_VALID(unit, mem, ECCf)) || 7803 /* above covers 7804 * ING_FLX_CTR_COUNTER_TABLEs, 7805 * EFP_COUNTER_TABLE, 7806 * EGR_FLEX_CTR_COUNTER_TABLEs 7807 */ 7808 /* SER_ENTRY_CLEAR, but with PARITY */ 7809 (ING_PW_TERM_SEQ_NUMm == mem) || 7810 (EGR_PERQ_XMT_COUNTERSm == mem) || 7811 (EGR_PW_INIT_COUNTERSm == mem) || 7812 /* SER_CACHE_RESTORE */ 7813 /* (EGR_FRAGMENT_ID_TABLEm == mem) || - same values written to all pipes 7814 * using global view - esw/firebolt/l3.c */ 7815 #ifdef BCM_TOMAHAWK3_SUPPORT 7816 (EDB_XMIT_START_COUNTm == mem) || 7817 #endif 7818 (EGR_XMIT_START_COUNTm == mem) 7819 ) { 7820 force_unique_mode = 1; 7821 } 7822 if (force_unique_mode) { 7823 LOG_VERBOSE(BSL_LS_SOC_SER, 7824 (BSL_META_U(unit, 7825 "Will force unique mode for: mem %s \n"), 7826 SOC_MEM_NAME(unit, mem))); 7827 } 7828 return force_unique_mode; 7829 } 7830 7831 #ifdef BCM_TOMAHAWK2_SUPPORT 7832 STATIC int 7833 _soc_tomahawk2_tcam_only_remap(int unit, soc_mem_t *mem) 7834 { 7835 if (!SOC_MEM_IS_VALID(unit, *mem)) { 7836 return SOC_E_PARAM; 7837 } 7838 7839 switch(*mem) { 7840 case L3_TUNNEL_ONLYm: 7841 *mem = L3_TUNNELm; 7842 break; 7843 case ING_SNAT_ONLYm: 7844 *mem = ING_SNATm; 7845 break; 7846 case VLAN_SUBNET_ONLYm: 7847 *mem = VLAN_SUBNETm; 7848 break; 7849 case MY_STATION_TCAM_ENTRY_ONLYm: 7850 *mem = MY_STATION_TCAMm; 7851 break; 7852 case L2_USER_ENTRY_ONLYm: 7853 *mem = L2_USER_ENTRYm; 7854 break; 7855 case SRC_COMPRESSION_TCAM_ONLYm: 7856 *mem = SRC_COMPRESSIONm; 7857 break; 7858 case DST_COMPRESSION_TCAM_ONLYm: 7859 *mem = DST_COMPRESSIONm; 7860 break; 7861 case EXACT_MATCH_LOGICAL_TABLE_SELECT_TCAM_ONLYm: 7862 *mem = EXACT_MATCH_LOGICAL_TABLE_SELECTm; 7863 break; 7864 case CPU_COS_MAP_ONLYm: 7865 *mem = CPU_COS_MAPm; 7866 break; 7867 case L3_DEFIP_ONLYm: 7868 *mem = L3_DEFIPm; 7869 break; 7870 case L3_DEFIP_PAIR_128_ONLYm: 7871 *mem = L3_DEFIP_PAIR_128m; 7872 break; 7873 default: 7874 break; 7875 } 7876 7877 return SOC_E_NONE; 7878 } 7879 #endif 7880 7881 int 7882 soc_tomahawk_process_ser_fifo(int unit, soc_block_t blk, int pipe, 7883 char *prefix_str, int l2_mgmt_ser_fifo, int reg_type, int cmic_bit) 7884 { 7885 int rv, mem_mode, disable_ser_correction; 7886 int ret = SOC_E_NONE; 7887 uint8 bidx; 7888 soc_mem_t mem; 7889 char blk_str[30]; 7890 soc_reg_t reg = INVALIDr; 7891 #ifdef BCM_TOMAHAWK3_SUPPORT 7892 soc_reg_t intr_reg = INVALIDr; 7893 #endif 7894 _soc_ser_correct_info_t spci; 7895 _soc_mem_ser_en_info_t *ser_info_table = NULL; 7896 soc_reg_t parity_enable_reg; 7897 soc_mem_t parity_enable_mem = INVALIDm; 7898 soc_field_t parity_enable_field; 7899 uint32 ecc_parity = 0, address = 0; 7900 uint32 reg_val, mask, entry[SOC_MAX_MEM_WORDS]; 7901 uint32 stage = 0, addrbase = 0, index = 0, type = 0; 7902 uint32 sblk = 0, regmem = 0, non_sbus = 0, drop = 0; 7903 soc_mem_t ipsf[] = { ING_SER_FIFO_PIPE0m, ING_SER_FIFO_PIPE1m, 7904 ING_SER_FIFO_PIPE2m, ING_SER_FIFO_PIPE3m, 7905 #ifdef BCM_TOMAHAWK3_SUPPORT 7906 ING_SER_FIFO_PIPE4m, ING_SER_FIFO_PIPE5m, 7907 ING_SER_FIFO_PIPE6m, ING_SER_FIFO_PIPE7m 7908 #endif 7909 }; 7910 soc_mem_t epsf[] = { EGR_SER_FIFO_PIPE0m, EGR_SER_FIFO_PIPE1m, 7911 EGR_SER_FIFO_PIPE2m, EGR_SER_FIFO_PIPE3m, 7912 #ifdef BCM_TOMAHAWK3_SUPPORT 7913 EGR_SER_FIFO_PIPE4m, EGR_SER_FIFO_PIPE5m, 7914 EGR_SER_FIFO_PIPE6m, EGR_SER_FIFO_PIPE7m 7915 #endif 7916 }; 7917 soc_reg_t epsr[] = { 7918 EGR_INTR_STATUS_PIPE0r, EGR_INTR_STATUS_PIPE1r, 7919 EGR_INTR_STATUS_PIPE2r, EGR_INTR_STATUS_PIPE3r, 7920 #ifdef BCM_TOMAHAWK3_SUPPORT 7921 EGR_INTR_STATUS_PIPE4r, EGR_INTR_STATUS_PIPE5r, 7922 EGR_INTR_STATUS_PIPE6r, EGR_INTR_STATUS_PIPE7r 7923 #endif 7924 }; 7925 #ifdef BCM_TOMAHAWK3_SUPPORT 7926 soc_mem_t epsf2[] = { EGR_SER_FIFO_2_PIPE0m, EGR_SER_FIFO_2_PIPE1m, 7927 EGR_SER_FIFO_2_PIPE2m, EGR_SER_FIFO_2_PIPE3m, 7928 EGR_SER_FIFO_2_PIPE4m, EGR_SER_FIFO_2_PIPE5m, 7929 EGR_SER_FIFO_2_PIPE6m, EGR_SER_FIFO_2_PIPE7m, }; 7930 soc_reg_t epsr2[] = { EGR_INTR_STATUS_2_PIPE0r, EGR_INTR_STATUS_2_PIPE1r, 7931 EGR_INTR_STATUS_2_PIPE2r, EGR_INTR_STATUS_2_PIPE3r, 7932 EGR_INTR_STATUS_2_PIPE4r, EGR_INTR_STATUS_2_PIPE5r, 7933 EGR_INTR_STATUS_2_PIPE6r, EGR_INTR_STATUS_2_PIPE7r }; 7934 soc_mem_t edbsf[] = { EDB_SER_FIFO_PIPE0m, EDB_SER_FIFO_PIPE1m, 7935 EDB_SER_FIFO_PIPE2m, EDB_SER_FIFO_PIPE3m, 7936 EDB_SER_FIFO_PIPE4m, EDB_SER_FIFO_PIPE5m, 7937 EDB_SER_FIFO_PIPE6m, EDB_SER_FIFO_PIPE7m }; 7938 soc_reg_t edbsr[] = { EDB_INTR_STATUS_PIPE0r, EDB_INTR_STATUS_PIPE1r, 7939 EDB_INTR_STATUS_PIPE2r, EDB_INTR_STATUS_PIPE3r, 7940 EDB_INTR_STATUS_PIPE4r, EDB_INTR_STATUS_PIPE5r, 7941 EDB_INTR_STATUS_PIPE6r, EDB_INTR_STATUS_PIPE7r }; 7942 #endif 7943 uint32 stat_flags = 0; 7944 soc_stat_t *stat = SOC_STAT(unit); 7945 7946 LOG_VERBOSE(BSL_LS_SOC_SER, 7947 (BSL_META_U(unit, 7948 "In process fifo.\n"))); 7949 switch (blk) { 7950 case SOC_BLK_IPIPE: 7951 if (l2_mgmt_ser_fifo) { /* L2_MGMT_SER_FIFO is not per pipe */ 7952 mem = L2_MGMT_SER_FIFOm; 7953 reg = L2_MGMT_INTRr; 7954 mask = 0x00000002; /* SER_FIFO_NOT_EMPTY */ 7955 sal_sprintf(blk_str, "IPIPE_L2_MGMT_SER_FIFO"); 7956 } else { 7957 #ifdef BCM_TOMAHAWK3_SUPPORT 7958 if (SOC_IS_TOMAHAWK3(unit) && cmic_bit & 0x2) { 7959 mem = DLB_ECMP_SER_FIFOm; 7960 reg = DLB_ECMP_INTR_STATUSr; 7961 mask = 0x00000001; /* SER_FIFO_NOT_EMPTY */ 7962 sal_sprintf(blk_str, "IPIPE_DLB_SER_FIFO"); 7963 } else 7964 #endif 7965 { 7966 mem = ipsf[pipe]; 7967 #ifdef BCM_TOMAHAWK3_SUPPORT 7968 if (SOC_IS_TOMAHAWK3(unit)) { 7969 mask = _soc_th3_ip_pipe_fifo_bmask[unit][pipe]; 7970 } else 7971 #endif 7972 #ifdef BCM_TOMAHAWK2_SUPPORT 7973 if (SOC_IS_TOMAHAWK2(unit)) { 7974 mask = _soc_th2_ip_pipe_fifo_bmask[unit][pipe]; 7975 } else 7976 #endif 7977 { 7978 mask = _soc_th_ip_pipe_fifo_bmask[unit][pipe]; 7979 } 7980 } 7981 sal_sprintf(blk_str, "IPIPE"); 7982 } 7983 7984 ser_info_table = SOC_IP_MEM_SER_INFO(unit); 7985 break; 7986 case SOC_BLK_EPIPE: 7987 #ifdef BCM_TOMAHAWK3_SUPPORT 7988 if (SOC_IS_TOMAHAWK3(unit)) { 7989 if (reg_type == 3) { 7990 /* EDB interrupt belongs to reg3 */ 7991 mem = edbsf[pipe]; 7992 reg = edbsr[pipe]; 7993 } else if (cmic_bit & 0x1fe0) { 7994 /* EFPMOD interrupt uses bit 5-12 */ 7995 mem = epsf2[pipe]; 7996 reg = epsr2[pipe]; 7997 } else { 7998 mem = epsf[pipe]; 7999 reg = epsr[pipe]; 8000 } 8001 mask = 0x00000001; /* SER_FIFO_NON_EMPTYf */ 8002 sal_sprintf(blk_str, "EPIPE"); 8003 ser_info_table = SOC_EP_MEM_SER_INFO(unit); 8004 } else 8005 #endif 8006 { 8007 mem = epsf[pipe]; 8008 mask = 0x00000001; /* SER_FIFO_NON_EMPTYf */ 8009 reg = epsr[pipe]; 8010 sal_sprintf(blk_str, "EPIPE"); 8011 ser_info_table = SOC_EP_MEM_SER_INFO(unit); 8012 } 8013 break; 8014 default: return SOC_E_PARAM; 8015 } 8016 8017 do { 8018 sal_memset(entry, 0, sizeof(entry)); 8019 SOC_IF_ERROR_RETURN 8020 (soc_mem_pop(unit, mem, MEM_BLOCK_ANY, entry)); 8021 /* process entry */ 8022 if (soc_mem_field32_get(unit, mem, entry, VALIDf)) { 8023 disable_ser_correction = 0; 8024 parity_enable_reg = INVALIDr; 8025 parity_enable_field = INVALIDf; 8026 sal_memset(&spci, 0, sizeof(spci)); 8027 ecc_parity = soc_mem_field32_get(unit, mem, entry, ECC_PARITYf); 8028 regmem = soc_mem_field32_get(unit, mem, entry, MEM_TYPEf); 8029 address = soc_mem_field32_get(unit, mem, entry, ADDRESSf); 8030 stage = soc_mem_field32_get(unit, mem, entry, PIPE_STAGEf); 8031 type = soc_mem_field32_get(unit, mem, entry, INSTRUCTION_TYPEf); 8032 drop = soc_mem_field32_get(unit, mem, entry, DROPf); 8033 8034 SOC_BLOCK_ITER(unit, bidx, blk) { 8035 sblk = SOC_BLOCK2SCH(unit, bidx); 8036 break; 8037 } 8038 LOG_WARN(BSL_LS_SOC_SER, 8039 (BSL_META_U(unit, 8040 "%s\n"), prefix_str)); 8041 if (soc_mem_field32_get(unit, mem, entry, MULTIPLEf)) { 8042 LOG_WARN(BSL_LS_SOC_SER, 8043 (BSL_META_U(unit, 8044 "Multiple: "))); 8045 } 8046 if (regmem == _SOC_TH_SER_REG) { 8047 LOG_WARN(BSL_LS_SOC_SER, 8048 (BSL_META_U(unit, 8049 "Reg: "))); 8050 } else { 8051 LOG_WARN(BSL_LS_SOC_SER, 8052 (BSL_META_U(unit, 8053 "Mem: "))); 8054 } 8055 switch (ecc_parity) { 8056 case 0: 8057 LOG_WARN(BSL_LS_SOC_SER, 8058 (BSL_META_U(unit, 8059 "Parity error..\n"))); 8060 break; 8061 case 1: 8062 LOG_WARN(BSL_LS_SOC_SER, 8063 (BSL_META_U(unit, 8064 "Corrected single bit ECC error..\n"))); 8065 /* NOTE: This is supressed by default, 8066 we can choose not to supress it */ 8067 break; 8068 case 2: 8069 LOG_WARN(BSL_LS_SOC_SER, 8070 (BSL_META_U(unit, 8071 "Double or Multiple bit ECC error..\n"))); 8072 spci.double_bit = 1; 8073 break; 8074 default: 8075 LOG_ERROR(BSL_LS_SOC_SER, 8076 (BSL_META_U(unit, 8077 "Invalid SER issue !!\n"))); 8078 return SOC_E_INTERNAL; 8079 } 8080 if (regmem == _SOC_TH_SER_MEM) { 8081 /* process mem */ 8082 non_sbus = soc_mem_field32_get(unit, mem, entry, NON_SBUSf); 8083 addrbase = soc_mem_field32_get(unit, mem, entry, MEMBASEf); 8084 index = soc_mem_field32_get(unit, mem, entry, MEMINDEXf); 8085 #ifdef BCM_TOMAHAWK3_SUPPORT 8086 /* For memory EDB_XMIT_START_COUNT, we should remap the address 8087 from 0x5da00000 to 0x5c280000 8088 */ 8089 if (SOC_IS_TOMAHAWK3(unit)) { 8090 if (((address - index) == 0x5da00000) && (mem == edbsf[pipe])) { 8091 address = 0x5c280000 + index; 8092 } 8093 } 8094 #endif 8095 /* 8096 * S/W WAR for TH-4666. When we inject an error into ISW2 buffer on TH/TH+ and 8097 * trigger it, H/W fails to set NON_SBUS in the fifo memory 8098 * and S/W wrongly interprets it to HG_TRUNK_GROUPm 8099 */ 8100 if (SOC_IS_TOMAHAWK(unit) || SOC_IS_TOMAHAWKPLUS(unit)) { 8101 if (!l2_mgmt_ser_fifo && (non_sbus == 0)) { 8102 uint32 err_index = 0; 8103 soc_mem_t err_mem = INVALIDm; 8104 8105 err_index = _soc_th_check_flex_ctr_addr(unit, address, 8106 blk, stage, 8107 index); 8108 err_mem = soc_addr_to_mem_extended(unit, sblk, -1, 8109 address - err_index); 8110 if (err_mem == HG_TRUNK_GROUPm) { 8111 non_sbus = 1; 8112 } 8113 } 8114 } 8115 8116 if (non_sbus == 0) { 8117 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 8118 ecc_parity == 0 ? 8119 SOC_SWITCH_EVENT_DATA_ERROR_PARITY : 8120 SOC_SWITCH_EVENT_DATA_ERROR_ECC, 8121 sblk | (pipe << SOC_SER_ERROR_PIPE_BP) | 8122 SOC_SER_ERROR_DATA_BLK_ADDR_SET, 8123 address); 8124 if (!SOC_IS_TOMAHAWK2(unit)) { 8125 index = _soc_th_check_flex_ctr_addr(unit, address, blk, 8126 stage, index); 8127 } 8128 8129 _soc_tomahawk_print_ser_fifo_details(unit, 0, blk, sblk, 8130 pipe, address, 8131 stage, addrbase, index, 8132 type, drop, non_sbus, 8133 l2_mgmt_ser_fifo); 8134 spci.flags = SOC_SER_SRC_MEM; 8135 spci.reg = INVALIDr; 8136 spci.mem = INVALIDm; 8137 spci.blk_type = blk; 8138 spci.pipe_num = l2_mgmt_ser_fifo? -1 : pipe; 8139 spci.sblk = sblk; 8140 spci.addr = address - index; 8141 spci.index = index; 8142 spci.stage = stage; 8143 spci.acc_type = -1; /* ignore acc_type for addr2_mem_decode */ 8144 spci.detect_time = sal_time_usecs(); 8145 8146 /* Try to decode mem first */ 8147 if (l2_mgmt_ser_fifo) { 8148 spci.mem = L2_MOD_FIFOm; 8149 } else { 8150 spci.mem = soc_addr_to_mem_extended(unit, spci.sblk, 8151 spci.acc_type, 8152 spci.addr); 8153 } 8154 #ifdef BCM_TOMAHAWK3_SUPPORT 8155 /* In TH3, tcam scan engine still reports the ser error on IFP_TCAM 8156 with narrow view, even the narrow view is removed. So need to remap 8157 the index for IFP_TCAM*/ 8158 if (SOC_IS_TOMAHAWK3(unit)) { 8159 if ((spci.mem == IFP_TCAMm || spci.mem == IFP_TCAM_PIPE0m || 8160 spci.mem == IFP_TCAM_PIPE1m || spci.mem == IFP_TCAM_PIPE2m || 8161 spci.mem == IFP_TCAM_PIPE3m || spci.mem == IFP_TCAM_PIPE4m || 8162 spci.mem == IFP_TCAM_PIPE5m || spci.mem == IFP_TCAM_PIPE6m || 8163 spci.mem == IFP_TCAM_PIPE7m) && (type == 4)) { 8164 spci.index = index / 2; 8165 } 8166 } 8167 #endif 8168 #if defined(BCM_TOMAHAWK2_SUPPORT) || defined(BCM_TOMAHAWK3_SUPPORT) 8169 if ((SOC_IS_TOMAHAWK2(unit) || SOC_IS_TOMAHAWK3(unit)) && 8170 soc_feature(unit, soc_feature_tcam_scan_engine)) { 8171 _soc_tomahawk2_tcam_only_remap(unit, &spci.mem); 8172 } 8173 #endif 8174 if (spci.mem != INVALIDm) { 8175 spci.flags |= SOC_SER_REG_MEM_KNOWN; 8176 if (!spci.double_bit) { 8177 disable_ser_correction = 8178 _soc_th_check_counter_with_ecc(unit, spci.mem); 8179 } 8180 8181 spci.flags |= SOC_SER_LOG_WRITE_CACHE; 8182 8183 if ((SOC_MEM_INFO(unit, spci.mem).flags & SOC_MEM_FLAG_CAM) && 8184 soc_feature(unit, soc_feature_tcam_scan_engine)) { 8185 #ifdef BCM_TOMAHAWK2_SUPPORT 8186 if (SOC_IS_TOMAHAWK2(unit)) { 8187 ret = _soc_th2_ser_tcam_control_reg_get(spci.mem, 8188 &parity_enable_reg, 8189 &parity_enable_field); 8190 } 8191 #endif 8192 #ifdef BCM_TOMAHAWK3_SUPPORT 8193 if (SOC_IS_TOMAHAWK3(unit)) { 8194 ret = _soc_th3_ser_tcam_control_reg_get(spci.mem, 8195 &parity_enable_reg, 8196 &parity_enable_field); 8197 } 8198 #endif 8199 if ( SOC_E_NONE == ret) { 8200 LOG_VERBOSE(BSL_LS_SOC_SER, 8201 (BSL_META_U(unit, 8202 "unit %d, tcam %s reported in ser_fifo!\n"), 8203 unit, SOC_MEM_NAME(unit,mem) )); 8204 } 8205 } else { 8206 8207 _soc_th_ser_control_reg_get(unit, ser_info_table, 8208 spci.mem, 8209 &parity_enable_reg, 8210 &parity_enable_mem, 8211 &parity_enable_field); 8212 } 8213 8214 if ((SOC_MEM_SER_CORRECTION_TYPE(unit, spci.mem) == 8215 SOC_MEM_FLAG_SER_ENTRY_CLEAR) && 8216 (spci.mem != EGR_PW_INIT_COUNTERSm) && 8217 (spci.mem != ING_PW_TERM_SEQ_NUMm)) { 8218 spci.flags |= SOC_SER_ALSO_UPDATE_SW_COUNTER; 8219 spci.counter_base_mem = spci.mem; 8220 switch (spci.mem) { 8221 case ING_FLEX_CTR_COUNTER_TABLE_1m: 8222 spci.inst = 1; 8223 break; 8224 case ING_FLEX_CTR_COUNTER_TABLE_2m: 8225 spci.inst = 2; 8226 break; 8227 case ING_FLEX_CTR_COUNTER_TABLE_3m: 8228 spci.inst = 3; 8229 break; 8230 case ING_FLEX_CTR_COUNTER_TABLE_4m: 8231 spci.inst = 4; 8232 break; 8233 case ING_FLEX_CTR_COUNTER_TABLE_5m: 8234 spci.inst = 5; 8235 break; 8236 case ING_FLEX_CTR_COUNTER_TABLE_6m: 8237 spci.inst = 6; 8238 break; 8239 case ING_FLEX_CTR_COUNTER_TABLE_7m: 8240 spci.inst = 7; 8241 break; 8242 case ING_FLEX_CTR_COUNTER_TABLE_8m: 8243 spci.inst = 8; 8244 break; 8245 case ING_FLEX_CTR_COUNTER_TABLE_9m: 8246 spci.inst = 9; 8247 break; 8248 case ING_FLEX_CTR_COUNTER_TABLE_10m: 8249 spci.inst = 10; 8250 break; 8251 case ING_FLEX_CTR_COUNTER_TABLE_11m: 8252 spci.inst = 11; 8253 break; 8254 case ING_FLEX_CTR_COUNTER_TABLE_12m: 8255 spci.inst = 12; 8256 break; 8257 case ING_FLEX_CTR_COUNTER_TABLE_13m: 8258 spci.inst = 13; 8259 break; 8260 case ING_FLEX_CTR_COUNTER_TABLE_14m: 8261 spci.inst = 14; 8262 break; 8263 case ING_FLEX_CTR_COUNTER_TABLE_15m: 8264 spci.inst = 15; 8265 break; 8266 case ING_FLEX_CTR_COUNTER_TABLE_16m: 8267 spci.inst = 16; 8268 break; 8269 case ING_FLEX_CTR_COUNTER_TABLE_17m: 8270 spci.inst = 17; 8271 break; 8272 case ING_FLEX_CTR_COUNTER_TABLE_18m: 8273 spci.inst = 18; 8274 break; 8275 case ING_FLEX_CTR_COUNTER_TABLE_19m: 8276 spci.inst = 19; 8277 break; 8278 8279 case EGR_FLEX_CTR_COUNTER_TABLE_1m: 8280 spci.inst = 1; 8281 break; 8282 case EGR_FLEX_CTR_COUNTER_TABLE_2m: 8283 spci.inst = 2; 8284 break; 8285 case EGR_FLEX_CTR_COUNTER_TABLE_3m: 8286 spci.inst = 3; 8287 break; 8288 8289 default: 8290 /* ING_FLEX_CTR_COUNTER_TABLE_0m 8291 * EGR_FLEX_CTR_COUNTER_TABLE_0m 8292 * EFP_COUNTER_TABLEm 8293 * EGR_PERQ_XMT_COUNTERSm */ 8294 spci.inst = 0; 8295 break; 8296 } 8297 } 8298 rv = soc_th_ser_mem_mode_get(unit, spci.mem, 8299 &mem_mode); 8300 if ((rv == SOC_E_NONE) && 8301 (mem_mode == _SOC_SER_MEM_MODE_PIPE_UNIQUE) && 8302 (spci.mem != SRC_COMPRESSION_DATA_ONLYm && 8303 spci.mem != DST_COMPRESSION_DATA_ONLYm && 8304 spci.mem != IFP_LOGICAL_TABLE_SELECT_DATA_ONLYm && 8305 spci.mem != EXACT_MATCH_LOGICAL_TABLE_SELECT_DATA_ONLYm)) { 8306 if (SOC_MEM_UNIQUE_ACC(unit, spci.mem) != NULL) { 8307 spci.mem = SOC_MEM_UNIQUE_ACC(unit, 8308 spci.mem)[pipe]; 8309 } 8310 } else if ((rv != SOC_E_NONE) && 8311 (rv != SOC_E_UNAVAIL)) { 8312 LOG_WARN(BSL_LS_SOC_SER, 8313 (BSL_META_U(unit, 8314 "Could not determine unique-global mode for" 8315 "mem %s - will assume global mode !!\n"), 8316 SOC_MEM_NAME(unit, mem))); 8317 } else if (_soc_th_force_unique_mode(unit, spci.mem)) { 8318 /* For counters, and other mems which have response 8319 * type ENTRY_CLEAR, we must clear ONLY affected 8320 * instance and not all instances - even if field module says 8321 * it is global mode */ 8322 if (SOC_MEM_UNIQUE_ACC(unit, spci.mem) != NULL) { 8323 spci.mem = SOC_MEM_UNIQUE_ACC(unit, 8324 spci.mem)[pipe]; 8325 } 8326 } 8327 /* In general, for mems that can operate in both local, unique mode, we want 8328 * to check the current mode and if current mode is unique we want to 8329 * do ser_correction for _PIPE0,1,2,3 view. Thus, for such mems we need to 8330 * change mem to mem_PIPE01,2,3 here. 8331 * 8332 * For _DATA_ONLY mems are exception to above rule because for these, 8333 * ser_correction logic will first remap them to aggr_view and then do 8334 * correction. For such mems, by specifying them in above equation, 8335 * we dont change them to _PIPE0,1,2,3 in this function. 8336 * These will be remapped to aggr and then aggr_PIPE0,1,2,3 view in 8337 * common/ser.c 8338 * 8339 * By not specifying mems in above equation, we change them to _PIPE0,1,2,3 8340 * view. Why do we not mention following mems in above equation ? 8341 * L3_TUNNEL_DATA_ONLY - this mem never operateds in UNIQUE mode 8342 * 8343 * FPEM_ECC - mem_mode_get will return GLOBAL for this mem. 8344 * common/ser.c will remap it to EXACT_MATCH_2, 4 and then 8345 * change it to _PIPE0,1,2,3 8346 * 8347 * EXACT_MATCH_2, 4 - HW cannot report error for these views (HW will always report error with FPEM_ECC view) 8348 * 8349 * FP_UDF_OFFSET - field module accesses data view separately 8350 * VFP_POLICY_TABLE - field module accesses data view separately 8351 * EFP_POLICY_TABLE - field module accesses data view separately 8352 * IFP_POLICY_TABLE - field module accesses data view separately 8353 * EFP_COUNTER_TABLE - field module accesses data view separately 8354 * EFP_METER_TABLE - field module accesses data view separately 8355 * and so on... 8356 */ 8357 spci.parity_type = _soc_th_mem_has_ecc(unit, spci.mem)? 8358 SOC_PARITY_TYPE_ECC : 8359 SOC_PARITY_TYPE_PARITY; 8360 } else { 8361 spci.flags |= SOC_SER_REG_MEM_UNKNOWN; 8362 } 8363 #ifdef ALPM_ENABLE 8364 if ((spci.mem == L3_DEFIP_ALPM_ECCm)) { 8365 SOC_ALPM_LPM_LOCK(unit); 8366 } 8367 #endif 8368 if ((spci.mem != INVALIDm) && (spci.mem != L3_DEFIP_ALPM_ECCm)) { 8369 MEM_LOCK(unit,spci.mem); 8370 } 8371 spci.log_id = _soc_th_populate_ser_log(unit, 8372 parity_enable_reg, 8373 parity_enable_mem, 8374 parity_enable_field, 8375 spci.mem, 8376 bidx, 8377 spci.pipe_num, 8378 spci.index, 8379 spci.detect_time, 8380 spci.sblk, 8381 spci.addr, 8382 1, /* disable_parity */ 8383 0, /* disable_mem_read */ 8384 0, /* disable_fill_cache_log */ 8385 1, /* force_cache_log */ 8386 TRUE, 0); 8387 if ((spci.mem != INVALIDm) && (spci.mem != L3_DEFIP_ALPM_ECCm)) { 8388 MEM_UNLOCK(unit,spci.mem); 8389 } 8390 #ifdef ALPM_ENABLE 8391 if (spci.mem == L3_DEFIP_ALPM_ECCm) { 8392 SOC_ALPM_LPM_UNLOCK(unit); 8393 } 8394 #endif 8395 if (!disable_ser_correction && !l2_mgmt_ser_fifo) { 8396 LOG_VERBOSE(BSL_LS_SOC_SER, (BSL_META_U(unit, 8397 "unit %d will try ser_correction for mem %s, pipe %d\n"), 8398 unit, SOC_MEM_NAME(unit, spci.mem), spci.pipe_num)); 8399 rv = soc_ser_correction(unit, &spci); 8400 } else { 8401 rv = SOC_E_NONE; 8402 } 8403 if (spci.log_id != 0) { 8404 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 8405 SOC_SWITCH_EVENT_DATA_ERROR_LOG, 8406 spci.log_id, 0); 8407 if (soc_property_get(unit, "ser_log_print_one", 0)) { 8408 soc_ser_log_print_one(unit, spci.log_id); 8409 } 8410 } 8411 if (SOC_FAILURE(rv)) { 8412 /* Add reporting failed to correct event flag to 8413 * application */ 8414 soc_event_generate(unit, 8415 SOC_SWITCH_EVENT_PARITY_ERROR, 8416 SOC_SWITCH_EVENT_DATA_ERROR_FAILEDTOCORRECT, 8417 sblk | (pipe << SOC_SER_ERROR_PIPE_BP) | 8418 SOC_SER_ERROR_DATA_BLK_ADDR_SET, address); 8419 if ((spci.mem != INVALIDm) && 8420 (SOC_MEM_INFO(unit, mem).flags & SOC_MEM_FLAG_CAM)) { 8421 stat_flags = SOC_SER_STAT_TCAM; 8422 } else { 8423 stat_flags = 0; 8424 } 8425 soc_ser_stat_update(unit, stat_flags, spci.blk_type, 8426 spci.parity_type, 8427 spci.double_bit, 8428 SocSerCorrectTypeFailedToCorrect, 8429 stat); 8430 return rv; 8431 } 8432 } else { 8433 LOG_ERROR(BSL_LS_SOC_SER, 8434 (BSL_META_U(unit, 8435 "%s SER mem address un-accessable !!\n"), 8436 blk_str)); 8437 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 8438 SOC_SWITCH_EVENT_DATA_ERROR_UNCORRECTABLE, 0, 0); 8439 soc_ser_stat_update(unit, 0, blk, 8440 ecc_parity == 0 ? SOC_PARITY_TYPE_PARITY : 8441 SOC_PARITY_TYPE_ECC, 8442 spci.double_bit, 8443 SocSerCorrectTypeNoAction, 8444 stat); 8445 _soc_tomahawk_print_ser_fifo_details(unit, 0, blk, sblk, 8446 pipe, address, 8447 stage, addrbase, index, 8448 type, drop, non_sbus, 8449 l2_mgmt_ser_fifo); 8450 _soc_th_populate_ser_log(unit, INVALIDr, INVALIDm, INVALIDf, 8451 INVALIDm, bidx, 0, index, 8452 sal_time_usecs(), 0, 0, 1, 0, 0, 1, 8453 FALSE, addrbase); 8454 } 8455 } else { 8456 /* process reg */ 8457 non_sbus = soc_mem_field32_get(unit, mem, entry, NON_SBUSf); 8458 addrbase = soc_mem_field32_get(unit, mem, entry, REGBASEf); 8459 index = soc_mem_field32_get(unit, mem, entry, REGINDEXf); 8460 if (l2_mgmt_ser_fifo) { 8461 LOG_WARN(BSL_LS_SOC_SER, 8462 (BSL_META_U(unit, 8463 "%s SER reg address reported in " 8464 "L2_MGMT_SER_FIRO !!\n"), 8465 blk_str)); 8466 _soc_tomahawk_print_ser_fifo_details(unit, 0, blk, sblk, 8467 pipe, address, 8468 stage, addrbase, index, 8469 type, drop, non_sbus, 8470 1); 8471 } else if (non_sbus == 0) { 8472 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 8473 ecc_parity == 0 ? 8474 SOC_SWITCH_EVENT_DATA_ERROR_PARITY : 8475 SOC_SWITCH_EVENT_DATA_ERROR_ECC, 8476 sblk | (pipe << SOC_SER_ERROR_PIPE_BP) | 8477 SOC_SER_ERROR_DATA_BLK_ADDR_SET, 8478 address); 8479 _soc_tomahawk_print_ser_fifo_details(unit, 1, blk, sblk, 8480 pipe, address, 8481 stage, addrbase, index, 8482 type, drop, non_sbus, 8483 0); 8484 spci.flags = SOC_SER_SRC_REG | SOC_SER_REG_MEM_UNKNOWN; 8485 spci.reg = INVALIDr; 8486 spci.mem = INVALIDm; 8487 spci.blk_type = blk; 8488 spci.pipe_num = pipe; 8489 spci.sblk = sblk; 8490 spci.addr = address; 8491 spci.index = index; 8492 spci.stage = stage; 8493 spci.acc_type = -1; /* ignore acc_type for addr2_reg_decode */ 8494 spci.detect_time = sal_time_usecs(); 8495 spci.parity_type = SOC_PARITY_TYPE_PARITY; 8496 spci.log_id = soc_ser_log_create_entry(unit, 8497 sizeof(soc_ser_log_tlv_generic_t) + 8498 sizeof(soc_ser_log_tlv_register_t) + 8499 sizeof(soc_ser_log_tlv_hdr_t) *3); 8500 rv = soc_ser_correction(unit, &spci); 8501 if (spci.log_id != 0) { 8502 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 8503 SOC_SWITCH_EVENT_DATA_ERROR_LOG, 8504 spci.log_id, 0); 8505 if (soc_property_get(unit, "ser_log_print_one", 0)) { 8506 soc_ser_log_print_one(unit, spci.log_id); 8507 } 8508 } 8509 if (SOC_FAILURE(rv)) { 8510 /* Add reporting failed to correct event flag to 8511 * application */ 8512 soc_event_generate(unit, 8513 SOC_SWITCH_EVENT_PARITY_ERROR, 8514 SOC_SWITCH_EVENT_DATA_ERROR_FAILEDTOCORRECT, 8515 sblk | (pipe << SOC_SER_ERROR_PIPE_BP) | 8516 SOC_SER_ERROR_DATA_BLK_ADDR_SET, address); 8517 soc_ser_stat_update(unit, 0, spci.blk_type, 8518 spci.parity_type, 8519 spci.double_bit, 8520 SocSerCorrectTypeFailedToCorrect, 8521 stat); 8522 return rv; 8523 } 8524 } else { 8525 LOG_ERROR(BSL_LS_SOC_SER, 8526 (BSL_META_U(unit, 8527 "%s SER reg address un-accessable !!\n"), 8528 blk_str)); 8529 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 8530 SOC_SWITCH_EVENT_DATA_ERROR_UNCORRECTABLE, 0, 0); 8531 soc_ser_stat_update(unit, 0, blk, 8532 ecc_parity == 0 ? SOC_PARITY_TYPE_PARITY : 8533 SOC_PARITY_TYPE_ECC, 8534 spci.double_bit, 8535 SocSerCorrectTypeNoAction, 8536 stat); 8537 _soc_tomahawk_print_ser_fifo_details(unit, 0, blk, sblk, 8538 pipe, address, 8539 stage, addrbase, index, 8540 type, drop, non_sbus, 8541 0); 8542 } 8543 } 8544 } else { 8545 LOG_ERROR(BSL_LS_SOC_SER, 8546 (BSL_META_U(unit, 8547 "unit %d Got invalid mem pop from %s !!\n"), 8548 unit, SOC_MEM_NAME(unit, mem))); 8549 } 8550 /* check if any more pending */ 8551 if (reg == INVALIDr) { 8552 /* coverity[result_independent_of_operands] */ 8553 #ifdef BCM_TOMAHAWK3_SUPPORT 8554 if (SOC_IS_TOMAHAWK3(unit)) { 8555 if (blk == SOC_BLK_EPIPE) { 8556 intr_reg = ICFG_CHIP_LP_INTR_RAW_STATUS_REG0r; 8557 } else { 8558 intr_reg = ICFG_CHIP_LP_INTR_RAW_STATUS_REG1r; 8559 } 8560 SOC_IF_ERROR_RETURN 8561 (soc_iproc_getreg(unit, soc_reg_addr(unit, intr_reg, 8562 REG_PORT_ANY, 0), ®_val)); 8563 } else 8564 #endif 8565 { 8566 SOC_IF_ERROR_RETURN 8567 (READ_CMIC_CMC0_IRQ_STAT3r(unit, ®_val)); 8568 } 8569 } else { 8570 SOC_IF_ERROR_RETURN 8571 (soc_reg32_get(unit, reg, REG_PORT_ANY, 0, ®_val)); 8572 } 8573 } while (reg_val & mask); 8574 return SOC_E_NONE; 8575 } 8576 8577 STATIC int 8578 _soc_tomahawk_ser_check_fifo_intr(int unit, uint32 cmic_bit, uint8 cmic_reg) 8579 { 8580 if (SOC_IS_TOMAHAWK3(unit) && 8581 ((cmic_bit & 0x1fffe2 && cmic_reg == 0) || 8582 (cmic_bit & 0xff0000 && cmic_reg == 1) || 8583 (cmic_bit & 0x1fe && cmic_reg == 3))) { 8584 return TRUE; 8585 } 8586 if (SOC_IS_TOMAHAWK2(unit) && (cmic_bit & 0x1e1e0)) { 8587 return TRUE; 8588 } 8589 if (((cmic_bit != _SOC_TH_IPIPE0_IP0_INTR) 8590 && (cmic_bit != _SOC_TH_IPIPE1_IP0_INTR) 8591 && (cmic_bit != _SOC_TH_IPIPE2_IP0_INTR) 8592 && (cmic_bit != _SOC_TH_IPIPE3_IP0_INTR)) 8593 && (! SOC_IS_TOMAHAWK2(unit)) 8594 && (!SOC_IS_TOMAHAWK3(unit))) { 8595 return TRUE; 8596 } 8597 8598 return FALSE; 8599 } 8600 8601 STATIC int 8602 _soc_tomahawk_ser_process_all(int unit, int reg_type, int bit) 8603 { 8604 uint8 rbi; 8605 int port = REG_PORT_ANY; 8606 uint32 cmic_rval = 0, cmic_bit; 8607 uint64 rb_rval64; 8608 const _soc_th_ser_route_block_t *rb; 8609 char prefix_str[10]; 8610 int block_info_idx; 8611 soc_reg_t tmp_reg; 8612 int processed_an_intr = 0; 8613 soc_stat_t *stat = SOC_STAT(unit); 8614 COMPILER_64_ZERO(rb_rval64); 8615 8616 sal_sprintf(prefix_str, "\nUnit: %d ", unit); 8617 8618 LOG_VERBOSE(BSL_LS_SOC_SER, 8619 (BSL_META_U(unit, 8620 "unit %d, _soc_tomahawk_ser_process_all called: reg_type %d, bit %d \n"), 8621 unit, reg_type, bit)); 8622 8623 #ifdef BCM_CMICM_SUPPORT 8624 if (soc_feature(unit, soc_feature_cmicm)) { 8625 switch (reg_type) { 8626 case 3: 8627 /* Read CMIC parity status register */ 8628 /* coverity[result_independent_of_operands] */ 8629 SOC_IF_ERROR_RETURN 8630 (READ_CMIC_CMC0_IRQ_STAT3r(unit, &cmic_rval)); 8631 if (cmic_rval == 0) { 8632 LOG_VERBOSE(BSL_LS_SOC_SER, 8633 (BSL_META_U(unit, 8634 "unit %d, _soc_tomahawk_ser_process_all: will not process intr because cmic_rval is 0\n"), 8635 unit)); 8636 return SOC_E_NONE; 8637 } 8638 break; 8639 case 4: 8640 /* Read PM0-31 parity status register */ 8641 /* coverity[result_independent_of_operands] */ 8642 SOC_IF_ERROR_RETURN 8643 (READ_CMIC_CMC0_IRQ_STAT4r(unit, &cmic_rval)); 8644 if (cmic_rval == 0) { 8645 LOG_VERBOSE(BSL_LS_SOC_SER, 8646 (BSL_META_U(unit, 8647 "unit %d, _soc_tomahawk_ser_process_all: will not process intr because cmic_rval is 0\n"), 8648 unit)); 8649 return SOC_E_NONE; 8650 } 8651 break; 8652 case 5: 8653 /* Read PM32 parity status register */ 8654 /* coverity[result_independent_of_operands] */ 8655 SOC_IF_ERROR_RETURN 8656 (READ_CMIC_CMC0_IRQ_STAT5r(unit, &cmic_rval)); 8657 if (cmic_rval == 0) { 8658 LOG_VERBOSE(BSL_LS_SOC_SER, 8659 (BSL_META_U(unit, 8660 "unit %d, _soc_tomahawk_ser_process_all: will not process intr because cmic_rval is 0\n"), 8661 unit)); 8662 return SOC_E_NONE; 8663 } 8664 break; 8665 #ifdef BCM_TOMAHAWK2_SUPPORT 8666 case 6: 8667 /* Read PM32-63 parity status register */ 8668 /* coverity[result_independent_of_operands] */ 8669 SOC_IF_ERROR_RETURN 8670 (READ_CMIC_CMC0_IRQ_STAT6r(unit, &cmic_rval)); 8671 if (cmic_rval == 0) { 8672 LOG_VERBOSE(BSL_LS_SOC_SER, 8673 (BSL_META_U(unit, 8674 "unit %d, _soc_tomahawk_ser_process_all: will not process intr because cmic_rval is 0\n"), 8675 unit)); 8676 return SOC_E_NONE; 8677 } 8678 break; 8679 #endif 8680 default: 8681 return SOC_E_NONE; 8682 } 8683 } 8684 #endif 8685 #ifdef BCM_CMICX_SUPPORT 8686 if (soc_feature(unit, soc_feature_cmicx)) { 8687 switch(reg_type) { 8688 case 0: 8689 READ_CMICx_INTC_INTR(unit, ICFG_CHIP_LP_INTR_RAW_STATUS_REG0r, 8690 &cmic_rval); 8691 if (cmic_rval == 0) { 8692 LOG_VERBOSE(BSL_LS_SOC_SER, 8693 (BSL_META_U(unit, 8694 "unit %d, _soc_tomahawk_ser_process_all: will not process intr because cmic_rval is 0\n"), 8695 unit)); 8696 return SOC_E_NONE; 8697 } 8698 break; 8699 case 1: 8700 READ_CMICx_INTC_INTR(unit, ICFG_CHIP_LP_INTR_RAW_STATUS_REG1r, 8701 &cmic_rval); 8702 if (cmic_rval == 0) { 8703 LOG_VERBOSE(BSL_LS_SOC_SER, 8704 (BSL_META_U(unit, 8705 "unit %d, _soc_tomahawk_ser_process_all: will not process intr because cmic_rval is 0\n"), 8706 unit)); 8707 return SOC_E_NONE; 8708 } 8709 break; 8710 case 2: 8711 READ_CMICx_INTC_INTR(unit, ICFG_CHIP_LP_INTR_RAW_STATUS_REG2r, 8712 &cmic_rval); 8713 if (cmic_rval == 0) { 8714 LOG_VERBOSE(BSL_LS_SOC_SER, 8715 (BSL_META_U(unit, 8716 "unit %d, _soc_tomahawk_ser_process_all: will not process intr because cmic_rval is 0\n"), 8717 unit)); 8718 return SOC_E_NONE; 8719 } 8720 break; 8721 case 3: 8722 READ_CMICx_INTC_INTR(unit, ICFG_CHIP_LP_INTR_RAW_STATUS_REG3r, 8723 &cmic_rval); 8724 if (cmic_rval == 0) { 8725 LOG_VERBOSE(BSL_LS_SOC_SER, 8726 (BSL_META_U(unit, 8727 "unit %d, _soc_tomahawk_ser_process_all: will not process intr because cmic_rval is 0\n"), 8728 unit)); 8729 return SOC_E_NONE; 8730 } 8731 break; 8732 default: 8733 return SOC_E_NONE; 8734 } 8735 } 8736 #endif 8737 8738 /* Loop through each place-and-route block entry */ 8739 for (rbi = 0; ; rbi++) { 8740 #ifdef BCM_TOMAHAWK3_SUPPORT 8741 if (SOC_IS_TOMAHAWK3(unit)) { 8742 rb = &_soc_th3_ser_route_blocks[rbi]; 8743 } else 8744 #endif 8745 #ifdef BCM_TOMAHAWK2_SUPPORT 8746 if (SOC_IS_TOMAHAWK2(unit)) { 8747 rb = &_soc_th2_ser_route_blocks[rbi]; 8748 } else 8749 #endif 8750 #ifdef BCM_TOMAHAWKPLUS_SUPPORT 8751 if (SOC_IS_TOMAHAWKPLUS(unit)) { 8752 rb = &_soc_thplus_ser_route_blocks[rbi]; 8753 } else 8754 #endif 8755 { 8756 rb = &_soc_th_ser_route_blocks[rbi]; 8757 } 8758 cmic_bit = rb->cmic_bit; 8759 if (cmic_bit == 0) { 8760 /* End of table */ 8761 break; 8762 } 8763 if (!((rb->cmic_reg == reg_type) && (cmic_bit == 1<<bit))) { 8764 continue; 8765 } 8766 if (!(cmic_rval & cmic_bit)) { 8767 /* Indicated bit not asserted for the route block */ 8768 LOG_VERBOSE(BSL_LS_SOC_SER, 8769 (BSL_META_U(unit, 8770 "unit %d, _soc_tomahawk_ser_process_all: cmic_rval %8x, indicated cmic_bit %8x not asserted for the route block %d, so exiting\n"), 8771 unit, cmic_rval, cmic_bit, rbi)); 8772 break; 8773 } 8774 /* For TH family only IP/EP memories use soc_tomahawk_process_ser_fifo 8775 to recover the error. For TH2, IP/EP interrupt bits are in a same intr 8776 register, so just need to do AND operation with related mask. But for 8777 TH3, the new fifo EDB_SER_FIFO is added, and the interrupt bits for 8778 IP/EP belong to different intr register, so besides checking the 8779 cmic_bit, we should also check the cmic_reg number.*/ 8780 if ((rb->blocktype == SOC_BLK_IPIPE || rb->blocktype == SOC_BLK_EPIPE) && 8781 _soc_tomahawk_ser_check_fifo_intr(unit, rb->cmic_bit, rb->cmic_reg)) { 8782 /* New fifo style processing */ 8783 (void)soc_tomahawk_process_ser_fifo(unit, rb->blocktype, rb->pipe, 8784 prefix_str, 0, reg_type, rb->cmic_bit); 8785 stat->ser_err_fifo++; 8786 processed_an_intr = 1; 8787 } else { 8788 /* Legacy processing */ 8789 /* for rb->blocktype = SOC_BLK_MMU, we will be here */ 8790 SOC_BLOCK_ITER(unit, block_info_idx, rb->blocktype) { 8791 if (SOC_BLOCK_INFO(unit, block_info_idx).number == rb->id) { 8792 port = SOC_BLOCK_PORT(unit, block_info_idx); 8793 break; 8794 } 8795 /* ??? Because entry for mmu in _soc_th_ser_route_blocks array uses 8796 * SOC_BLK_MMU which is illegal for Tomahawk, so block_info_idx 8797 * determined above is incorrect for mmu. Does it matter ? 8798 */ 8799 } 8800 if (rb->enable_reg != INVALIDr) { 8801 /* for SOC_BLK_MMU, enable_reg is INVALIDr */ 8802 if (SOC_BLOCK_IN_LIST(SOC_REG_INFO(unit, rb->enable_reg).block, 8803 SOC_BLK_PORT) && (port == REG_PORT_ANY)) { 8804 /* This port block is not configured */ 8805 LOG_ERROR(BSL_LS_SOC_SER, 8806 (BSL_META_U(unit, 8807 "unit %d SER error on disabled " 8808 "port block %d !!\n"), 8809 unit, block_info_idx)); 8810 continue; 8811 } 8812 } 8813 /* Read per route block parity status register */ 8814 if (rb->status_reg != INVALIDr) { 8815 /* for SOC_BLK_MMU, status_reg is INVALIDr */ 8816 if ((rb->blocktype == SOC_BLK_IPIPE || 8817 rb->blocktype == SOC_BLK_EPIPE) && 8818 (SOC_REG_UNIQUE_ACC(unit, rb->status_reg) != NULL)) { 8819 tmp_reg = SOC_REG_UNIQUE_ACC(unit, 8820 rb->status_reg)[rb->pipe]; 8821 } else { 8822 tmp_reg = rb->status_reg; 8823 } 8824 SOC_IF_ERROR_RETURN 8825 (soc_reg_get(unit, tmp_reg, port, 0, &rb_rval64)); 8826 8827 /* 8828 * For SOC_BLK_MMU, rb->status_reg is INVALIDr, 8829 * so rb_rval64 will always be 0, so we will skip all of 8830 * following for mmu 8831 * so we will never call _soc_tomahawk_process_ser, 8832 * and hence process_mmu_err at all !! 8833 */ 8834 if (COMPILER_64_IS_ZERO(rb_rval64)) { 8835 continue; 8836 } 8837 } 8838 processed_an_intr = 1; 8839 SOC_IF_ERROR_RETURN 8840 (_soc_tomahawk_process_ser(unit, block_info_idx, rb->id, 8841 rb->pipe, port, rb->status_reg, 8842 rb_rval64, rb->info, rb->blocktype, 8843 prefix_str)); 8844 8845 stat->ser_err_int++; 8846 } /* legacy processing */ 8847 } 8848 if (!processed_an_intr) { 8849 LOG_WARN(BSL_LS_SOC_SER, 8850 (BSL_META_U(unit, 8851 "unit %d, reg_type %d, bit %d " 8852 "could not process interrupt !!\n"), 8853 unit, reg_type, bit)); 8854 8855 } 8856 return SOC_E_NONE; 8857 } 8858 8859 void 8860 soc_tomahawk_ser_error(void *unit_vp, void *d1, void *d2, void *d3, 8861 void *d4) 8862 { 8863 int unit = PTR_TO_INT(unit_vp); 8864 8865 (void)_soc_tomahawk_ser_process_all(unit, PTR_TO_INT(d3), PTR_TO_INT(d4)); 8866 sal_usleep(SAL_BOOT_QUICKTURN ? 1000000 : 10000); 8867 8868 #if defined(BCM_TOMAHAWK3_SUPPORT) 8869 if (SOC_IS_TOMAHAWK3(unit)) { 8870 soc_ser_top_intr_reg_enable(unit, PTR_TO_INT(d3), PTR_TO_INT(d4), 1); 8871 soc_cmic_intr_enable(unit, CHIP_INTR_LOW_PRIORITY); 8872 } else 8873 #endif 8874 { 8875 switch (PTR_TO_INT(d3)) { 8876 #ifdef BCM_CMICM_SUPPORT 8877 case 3: (void)soc_cmicm_intr3_enable(unit, PTR_TO_INT(d2)); 8878 break; 8879 case 4: (void)soc_cmicm_intr4_enable(unit, PTR_TO_INT(d2)); 8880 break; 8881 case 5: (void)soc_cmicm_intr5_enable(unit, PTR_TO_INT(d2)); 8882 break; 8883 #ifdef BCM_TOMAHAWK2_SUPPORT 8884 case 6: (void)soc_cmicm_intr6_enable(unit, PTR_TO_INT(d2)); 8885 break; 8886 #endif 8887 default: 8888 break; 8889 #endif 8890 } 8891 } 8892 } 8893 8894 8895 static _soc_generic_ser_info_t _soc_th_tcam_ser_info_template[] = { 8896 /* default_acc_type = DATA_SPLIT, but still need to scan each pipe separately */ 8897 { L3_TUNNELm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 8898 _SOC_SER_INTERLEAVE_MOD2, 8899 { {0, 105}, {1, 105}, {106, 210}, {107, 210} }, 0, 0, 0, 0, 8900 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 8901 _SOC_SER_FLAG_XY_READ | _SOC_MEM_ADDR_ACC_TYPE_PIPE_0 }, 8902 { L3_TUNNELm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 8903 _SOC_SER_INTERLEAVE_MOD2, 8904 { {0, 105}, {1, 105}, {106, 210}, {107, 210} }, 0, 0, 0, 0, 8905 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 8906 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 8907 _SOC_MEM_ADDR_ACC_TYPE_PIPE_1 }, 8908 { L3_TUNNELm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 8909 _SOC_SER_INTERLEAVE_MOD2, 8910 { {0, 105}, {1, 105}, {106, 210}, {107, 210} }, 0, 0, 0, 0, 8911 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 8912 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 8913 _SOC_MEM_ADDR_ACC_TYPE_PIPE_2 }, 8914 { L3_TUNNELm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 8915 _SOC_SER_INTERLEAVE_MOD2, 8916 { {0, 105}, {1, 105}, {106, 210}, {107, 210} }, 0, 0, 0, 0, 8917 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 8918 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 8919 _SOC_MEM_ADDR_ACC_TYPE_PIPE_3 }, 8920 8921 /* default_acc_type = DATA_SPLIT, but still need to scan each pipe separately */ 8922 { ING_SNATm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 8923 _SOC_SER_INTERLEAVE_MOD2, 8924 { {0, 80}, {1, 80}, {81, 160}, {82, 160} }, 0, 0, 0, 0, 8925 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 8926 _SOC_SER_FLAG_XY_READ | _SOC_MEM_ADDR_ACC_TYPE_PIPE_0 }, 8927 { ING_SNATm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 8928 _SOC_SER_INTERLEAVE_MOD2, 8929 { {0, 80}, {1, 80}, {81, 160}, {82, 160} }, 0, 0, 0, 0, 8930 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 8931 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 8932 _SOC_MEM_ADDR_ACC_TYPE_PIPE_1 }, 8933 { ING_SNATm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 8934 _SOC_SER_INTERLEAVE_MOD2, 8935 { {0, 80}, {1, 80}, {81, 160}, {82, 160} }, 0, 0, 0, 0, 8936 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 8937 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 8938 _SOC_MEM_ADDR_ACC_TYPE_PIPE_2 }, 8939 { ING_SNATm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 8940 _SOC_SER_INTERLEAVE_MOD2, 8941 { {0, 80}, {1, 80}, {81, 160}, {82, 160} }, 0, 0, 0, 0, 8942 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 8943 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 8944 _SOC_MEM_ADDR_ACC_TYPE_PIPE_3 }, 8945 8946 /* default_acc_type = DUPLICATE, so need to scan each pipe separately */ 8947 { VLAN_SUBNETm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 8948 _SOC_SER_INTERLEAVE_MOD2, 8949 { {0, 80}, {1, 80}, {81, 160}, {82, 160} }, 0, 0, 0, 0, 8950 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 8951 _SOC_SER_FLAG_XY_READ | _SOC_MEM_ADDR_ACC_TYPE_PIPE_0 }, 8952 { VLAN_SUBNETm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 8953 _SOC_SER_INTERLEAVE_MOD2, 8954 { {0, 80}, {1, 80}, {81, 160}, {82, 160} }, 0, 0, 0, 0, 8955 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 8956 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 8957 _SOC_MEM_ADDR_ACC_TYPE_PIPE_1 }, 8958 { VLAN_SUBNETm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 8959 _SOC_SER_INTERLEAVE_MOD2, 8960 { {0, 80}, {1, 80}, {81, 160}, {82, 160} }, 0, 0, 0, 0, 8961 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 8962 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 8963 _SOC_MEM_ADDR_ACC_TYPE_PIPE_2 }, 8964 { VLAN_SUBNETm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 8965 _SOC_SER_INTERLEAVE_MOD2, 8966 { {0, 80}, {1, 80}, {81, 160}, {82, 160} }, 0, 0, 0, 0, 8967 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 8968 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 8969 _SOC_MEM_ADDR_ACC_TYPE_PIPE_3 }, 8970 8971 /* default_acc_type = DUPLICATE, so need to scan each pipe separately */ 8972 { MY_STATION_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 8973 _SOC_SER_INTERLEAVE_MOD2, 8974 { {0, 80}, {1, 80}, {81, 160}, {82, 160} }, 0, 0, 0, 0, 8975 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 8976 _SOC_SER_FLAG_XY_READ | _SOC_MEM_ADDR_ACC_TYPE_PIPE_0 }, 8977 { MY_STATION_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 8978 _SOC_SER_INTERLEAVE_MOD2, 8979 { {0, 80}, {1, 80}, {81, 160}, {82, 160} }, 0, 0, 0, 0, 8980 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 8981 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 8982 _SOC_MEM_ADDR_ACC_TYPE_PIPE_1 }, 8983 { MY_STATION_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 8984 _SOC_SER_INTERLEAVE_MOD2, 8985 { {0, 80}, {1, 80}, {81, 160}, {82, 160} }, 0, 0, 0, 0, 8986 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 8987 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 8988 _SOC_MEM_ADDR_ACC_TYPE_PIPE_2 }, 8989 { MY_STATION_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 8990 _SOC_SER_INTERLEAVE_MOD2, 8991 { {0, 80}, {1, 80}, {81, 160}, {82, 160} }, 0, 0, 0, 0, 8992 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 8993 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 8994 _SOC_MEM_ADDR_ACC_TYPE_PIPE_3 }, 8995 8996 /* default_acc_type = DUPLICATE, so need to scan each pipe separately */ 8997 { IP_MULTICAST_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 8998 _SOC_SER_INTERLEAVE_MOD2, 8999 { {0, 140}, {1, 140}, {141, 280}, {142, 280} }, 0, 0, 0, 0, 9000 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9001 _SOC_SER_FLAG_XY_READ | _SOC_MEM_ADDR_ACC_TYPE_PIPE_0 }, 9002 { IP_MULTICAST_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9003 _SOC_SER_INTERLEAVE_MOD2, 9004 { {0, 140}, {1, 140}, {141, 280}, {142, 280} }, 0, 0, 0, 0, 9005 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9006 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9007 _SOC_MEM_ADDR_ACC_TYPE_PIPE_1 }, 9008 { IP_MULTICAST_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9009 _SOC_SER_INTERLEAVE_MOD2, 9010 { {0, 140}, {1, 140}, {141, 280}, {142, 280} }, 0, 0, 0, 0, 9011 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9012 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9013 _SOC_MEM_ADDR_ACC_TYPE_PIPE_2 }, 9014 { IP_MULTICAST_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9015 _SOC_SER_INTERLEAVE_MOD2, 9016 { {0, 140}, {1, 140}, {141, 280}, {142, 280} }, 0, 0, 0, 0, 9017 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9018 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9019 _SOC_MEM_ADDR_ACC_TYPE_PIPE_3 }, 9020 9021 /* default_acc_type = DUPLICATE, so need to scan each pipe separately */ 9022 { L2_USER_ENTRYm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9023 _SOC_SER_INTERLEAVE_MOD2, 9024 { {0, 80}, {1, 80}, {81, 160}, {82, 160} }, 0, 0, 0, 0, 9025 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9026 _SOC_SER_FLAG_XY_READ | _SOC_MEM_ADDR_ACC_TYPE_PIPE_0 }, 9027 { L2_USER_ENTRYm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9028 _SOC_SER_INTERLEAVE_MOD2, 9029 { {0, 80}, {1, 80}, {81, 160}, {82, 160} }, 0, 0, 0, 0, 9030 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9031 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9032 _SOC_MEM_ADDR_ACC_TYPE_PIPE_1 }, 9033 { L2_USER_ENTRYm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9034 _SOC_SER_INTERLEAVE_MOD2, 9035 { {0, 80}, {1, 80}, {81, 160}, {82, 160} }, 0, 0, 0, 0, 9036 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9037 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9038 _SOC_MEM_ADDR_ACC_TYPE_PIPE_2 }, 9039 { L2_USER_ENTRYm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9040 _SOC_SER_INTERLEAVE_MOD2, 9041 { {0, 80}, {1, 80}, {81, 160}, {82, 160} }, 0, 0, 0, 0, 9042 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9043 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9044 _SOC_MEM_ADDR_ACC_TYPE_PIPE_3 }, 9045 9046 /* default_acc_type = DUPLICATE, so need to scan each pipe separately */ 9047 { CPU_COS_MAPm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9048 _SOC_SER_INTERLEAVE_MOD2, 9049 { {0, 140}, {1, 140}, {141, 280}, {142, 280} }, 0, 0, 0, 0, 9050 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9051 _SOC_SER_FLAG_XY_READ | _SOC_MEM_ADDR_ACC_TYPE_PIPE_0 }, 9052 { CPU_COS_MAPm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9053 _SOC_SER_INTERLEAVE_MOD2, 9054 { {0, 140}, {1, 140}, {141, 280}, {142, 280} }, 0, 0, 0, 0, 9055 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9056 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9057 _SOC_MEM_ADDR_ACC_TYPE_PIPE_1 }, 9058 { CPU_COS_MAPm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9059 _SOC_SER_INTERLEAVE_MOD2, 9060 { {0, 140}, {1, 140}, {141, 280}, {142, 280} }, 0, 0, 0, 0, 9061 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9062 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9063 _SOC_MEM_ADDR_ACC_TYPE_PIPE_2 }, 9064 { CPU_COS_MAPm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9065 _SOC_SER_INTERLEAVE_MOD2, 9066 { {0, 140}, {1, 140}, {141, 280}, {142, 280} }, 0, 0, 0, 0, 9067 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9068 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9069 _SOC_MEM_ADDR_ACC_TYPE_PIPE_3 }, 9070 9071 /* default_acc_type = DATA_SPLIT, but still need to scan each pipe separately */ 9072 { L3_DEFIPm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9073 _SOC_SER_INTERLEAVE_MOD2, 9074 { {0, 97}, {1, 97}, {98, 193}, {99, 193} }, 0, 0, 0, 0, 9075 _SOC_SER_FLAG_NO_DMA | _SOC_SER_FLAG_MULTI_PIPE | 9076 _SOC_SER_FLAG_REMAP_READ | _SOC_SER_FLAG_SIZE_VERIFY | 9077 _SOC_SER_FLAG_XY_READ | _SOC_MEM_ADDR_ACC_TYPE_PIPE_0 }, 9078 { L3_DEFIPm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9079 _SOC_SER_INTERLEAVE_MOD2, 9080 { {0, 97}, {1, 97}, {98, 193}, {99, 193} }, 0, 0, 0, 0, 9081 _SOC_SER_FLAG_NO_DMA | _SOC_SER_FLAG_MULTI_PIPE | 9082 _SOC_SER_FLAG_REMAP_READ | _SOC_SER_FLAG_SIZE_VERIFY | 9083 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9084 _SOC_MEM_ADDR_ACC_TYPE_PIPE_1 }, 9085 { L3_DEFIPm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9086 _SOC_SER_INTERLEAVE_MOD2, 9087 { {0, 97}, {1, 97}, {98, 193}, {99, 193} }, 0, 0, 0, 0, 9088 _SOC_SER_FLAG_NO_DMA | _SOC_SER_FLAG_MULTI_PIPE | 9089 _SOC_SER_FLAG_REMAP_READ | _SOC_SER_FLAG_SIZE_VERIFY | 9090 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9091 _SOC_MEM_ADDR_ACC_TYPE_PIPE_2 }, 9092 { L3_DEFIPm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9093 _SOC_SER_INTERLEAVE_MOD2, 9094 { {0, 97}, {1, 97}, {98, 193}, {99, 193} }, 0, 0, 0, 0, 9095 _SOC_SER_FLAG_NO_DMA | _SOC_SER_FLAG_MULTI_PIPE | 9096 _SOC_SER_FLAG_REMAP_READ | _SOC_SER_FLAG_SIZE_VERIFY | 9097 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9098 _SOC_MEM_ADDR_ACC_TYPE_PIPE_3 }, 9099 9100 /* default_acc_type = DATA_SPLIT, but still need to scan each pipe separately */ 9101 { L3_DEFIP_PAIR_128m, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9102 _SOC_SER_INTERLEAVE_MOD2, 9103 { {0, 195}, {1, 195}, {196, 387}, {197, 387} }, 0, 0, 0, 0, 9104 _SOC_SER_FLAG_NO_DMA | _SOC_SER_FLAG_MULTI_PIPE | 9105 _SOC_SER_FLAG_REMAP_READ | _SOC_SER_FLAG_SIZE_VERIFY | 9106 _SOC_SER_FLAG_XY_READ | _SOC_MEM_ADDR_ACC_TYPE_PIPE_0 }, 9107 { L3_DEFIP_PAIR_128m, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9108 _SOC_SER_INTERLEAVE_MOD2, 9109 { {0, 195}, {1, 195}, {196, 387}, {197, 387} }, 0, 0, 0, 0, 9110 _SOC_SER_FLAG_NO_DMA | _SOC_SER_FLAG_MULTI_PIPE | 9111 _SOC_SER_FLAG_REMAP_READ | _SOC_SER_FLAG_SIZE_VERIFY | 9112 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9113 _SOC_MEM_ADDR_ACC_TYPE_PIPE_1 }, 9114 { L3_DEFIP_PAIR_128m, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9115 _SOC_SER_INTERLEAVE_MOD2, 9116 { {0, 195}, {1, 195}, {196, 387}, {197, 387} }, 0, 0, 0, 0, 9117 _SOC_SER_FLAG_NO_DMA | _SOC_SER_FLAG_MULTI_PIPE | 9118 _SOC_SER_FLAG_REMAP_READ | _SOC_SER_FLAG_SIZE_VERIFY | 9119 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9120 _SOC_MEM_ADDR_ACC_TYPE_PIPE_2 }, 9121 { L3_DEFIP_PAIR_128m, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9122 _SOC_SER_INTERLEAVE_MOD2, 9123 { {0, 195}, {1, 195}, {196, 387}, {197, 387} }, 0, 0, 0, 0, 9124 _SOC_SER_FLAG_NO_DMA | _SOC_SER_FLAG_MULTI_PIPE | 9125 _SOC_SER_FLAG_REMAP_READ | _SOC_SER_FLAG_SIZE_VERIFY | 9126 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9127 _SOC_MEM_ADDR_ACC_TYPE_PIPE_3 }, 9128 9129 /* Global view */ 9130 { SRC_COMPRESSIONm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9131 _SOC_SER_INTERLEAVE_MOD2, 9132 { {0, 144}, {1, 144}, {145, 288}, {146, 288} }, 0, 0, 0, 0, 9133 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9134 _SOC_SER_FLAG_XY_READ | _SOC_MEM_ADDR_ACC_TYPE_PIPE_0 }, 9135 { SRC_COMPRESSIONm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9136 _SOC_SER_INTERLEAVE_MOD2, 9137 { {0, 144}, {1, 144}, {145, 288}, {146, 288} }, 0, 0, 0, 0, 9138 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9139 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9140 _SOC_MEM_ADDR_ACC_TYPE_PIPE_1 }, 9141 { SRC_COMPRESSIONm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9142 _SOC_SER_INTERLEAVE_MOD2, 9143 { {0, 144}, {1, 144}, {145, 288}, {146, 288} }, 0, 0, 0, 0, 9144 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9145 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9146 _SOC_MEM_ADDR_ACC_TYPE_PIPE_2 }, 9147 { SRC_COMPRESSIONm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9148 _SOC_SER_INTERLEAVE_MOD2, 9149 { {0, 144}, {1, 144}, {145, 288}, {146, 288} }, 0, 0, 0, 0, 9150 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9151 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9152 _SOC_MEM_ADDR_ACC_TYPE_PIPE_3 }, 9153 /* Unique view - initially disabled */ 9154 { SRC_COMPRESSIONm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9155 _SOC_SER_INTERLEAVE_MOD2, 9156 { {0, 144}, {1, 144}, {145, 288}, {146, 288} }, 0, 0, 0, 0, 9157 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9158 _SOC_SER_FLAG_XY_READ | 9159 _SOC_SER_FLAG_ACC_TYPE_CHK | _SOC_SER_FLAG_VIEW_DISABLE, 4 }, 9160 9161 /* Global view */ 9162 { DST_COMPRESSIONm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9163 _SOC_SER_INTERLEAVE_MOD2, 9164 { {0, 144}, {1, 144}, {145, 288}, {146, 288} }, 0, 0, 0, 0, 9165 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9166 _SOC_SER_FLAG_XY_READ | _SOC_MEM_ADDR_ACC_TYPE_PIPE_0 }, 9167 { DST_COMPRESSIONm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9168 _SOC_SER_INTERLEAVE_MOD2, 9169 { {0, 144}, {1, 144}, {145, 288}, {146, 288} }, 0, 0, 0, 0, 9170 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9171 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9172 _SOC_MEM_ADDR_ACC_TYPE_PIPE_1 }, 9173 { DST_COMPRESSIONm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9174 _SOC_SER_INTERLEAVE_MOD2, 9175 { {0, 144}, {1, 144}, {145, 288}, {146, 288} }, 0, 0, 0, 0, 9176 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9177 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9178 _SOC_MEM_ADDR_ACC_TYPE_PIPE_2 }, 9179 { DST_COMPRESSIONm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9180 _SOC_SER_INTERLEAVE_MOD2, 9181 { {0, 144}, {1, 144}, {145, 288}, {146, 288} }, 0, 0, 0, 0, 9182 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9183 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9184 _SOC_MEM_ADDR_ACC_TYPE_PIPE_3 }, 9185 /* Unique view - initially disabled */ 9186 { DST_COMPRESSIONm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9187 _SOC_SER_INTERLEAVE_MOD2, 9188 { {0, 144}, {1, 144}, {145, 288}, {146, 288} }, 0, 0, 0, 0, 9189 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9190 _SOC_SER_FLAG_XY_READ | 9191 _SOC_SER_FLAG_ACC_TYPE_CHK | _SOC_SER_FLAG_VIEW_DISABLE, 4 }, 9192 9193 /* Global view */ 9194 { FP_UDF_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9195 _SOC_SER_INTERLEAVE_MOD2, 9196 { {0, 80}, {1, 80}, {81, 160}, {82, 160} }, 0, 0, 0, 0, 9197 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9198 _SOC_SER_FLAG_XY_READ | _SOC_MEM_ADDR_ACC_TYPE_PIPE_0 }, 9199 { FP_UDF_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9200 _SOC_SER_INTERLEAVE_MOD2, 9201 { {0, 80}, {1, 80}, {81, 160}, {82, 160} }, 0, 0, 0, 0, 9202 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9203 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9204 _SOC_MEM_ADDR_ACC_TYPE_PIPE_1 }, 9205 { FP_UDF_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9206 _SOC_SER_INTERLEAVE_MOD2, 9207 { {0, 80}, {1, 80}, {81, 160}, {82, 160} }, 0, 0, 0, 0, 9208 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9209 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9210 _SOC_MEM_ADDR_ACC_TYPE_PIPE_2 }, 9211 { FP_UDF_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9212 _SOC_SER_INTERLEAVE_MOD2, 9213 { {0, 80}, {1, 80}, {81, 160}, {82, 160} }, 0, 0, 0, 0, 9214 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9215 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9216 _SOC_MEM_ADDR_ACC_TYPE_PIPE_3 }, 9217 /* Unique view - initially disabled */ 9218 { FP_UDF_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9219 _SOC_SER_INTERLEAVE_MOD2, 9220 { {0, 80}, {1, 80}, {81, 160}, {82, 160} }, 0, 0, 0, 0, 9221 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9222 _SOC_SER_FLAG_XY_READ | 9223 _SOC_SER_FLAG_ACC_TYPE_CHK | _SOC_SER_FLAG_VIEW_DISABLE, 4 }, 9224 9225 /* Global view */ 9226 { VFP_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9227 _SOC_SER_INTERLEAVE_MOD2, 9228 { {0, 237}, {1, 237}, {238, 473}, {239, 473} }, 0, 0, 0, 0, 9229 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9230 _SOC_SER_FLAG_XY_READ | _SOC_MEM_ADDR_ACC_TYPE_PIPE_0 }, 9231 { VFP_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9232 _SOC_SER_INTERLEAVE_MOD2, 9233 { {0, 237}, {1, 237}, {238, 473}, {239, 473} }, 0, 0, 0, 0, 9234 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9235 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9236 _SOC_MEM_ADDR_ACC_TYPE_PIPE_1 }, 9237 { VFP_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9238 _SOC_SER_INTERLEAVE_MOD2, 9239 { {0, 237}, {1, 237}, {238, 473}, {239, 473} }, 0, 0, 0, 0, 9240 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9241 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9242 _SOC_MEM_ADDR_ACC_TYPE_PIPE_2 }, 9243 { VFP_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9244 _SOC_SER_INTERLEAVE_MOD2, 9245 { {0, 237}, {1, 237}, {238, 473}, {239, 473} }, 0, 0, 0, 0, 9246 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9247 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9248 _SOC_MEM_ADDR_ACC_TYPE_PIPE_3 }, 9249 /* Unique view - initially disabled */ 9250 { VFP_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9251 _SOC_SER_INTERLEAVE_MOD2, 9252 { {0, 237}, {1, 237}, {238, 473}, {239, 473} }, 0, 0, 0, 0, 9253 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9254 _SOC_SER_FLAG_XY_READ | 9255 _SOC_SER_FLAG_ACC_TYPE_CHK | _SOC_SER_FLAG_VIEW_DISABLE, 4 }, 9256 9257 /* Global view */ 9258 { IFP_LOGICAL_TABLE_SELECTm, INVALIDm, _SOC_SER_TYPE_PARITY, 9259 _SOC_SER_PARITY_8BITS, _SOC_SER_INTERLEAVE_MOD2, 9260 { {0, 96}, {1, 96}, {97, 192}, {98, 192} }, 0, 0, 0, 0, 9261 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9262 _SOC_SER_FLAG_XY_READ | _SOC_MEM_ADDR_ACC_TYPE_PIPE_0 }, 9263 { IFP_LOGICAL_TABLE_SELECTm, INVALIDm, _SOC_SER_TYPE_PARITY, 9264 _SOC_SER_PARITY_8BITS, _SOC_SER_INTERLEAVE_MOD2, 9265 { {0, 96}, {1, 96}, {97, 192}, {98, 192} }, 0, 0, 0, 0, 9266 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9267 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9268 _SOC_MEM_ADDR_ACC_TYPE_PIPE_1 }, 9269 { IFP_LOGICAL_TABLE_SELECTm, INVALIDm, _SOC_SER_TYPE_PARITY, 9270 _SOC_SER_PARITY_8BITS, _SOC_SER_INTERLEAVE_MOD2, 9271 { {0, 96}, {1, 96}, {97, 192}, {98, 192} }, 0, 0, 0, 0, 9272 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9273 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9274 _SOC_MEM_ADDR_ACC_TYPE_PIPE_2 }, 9275 { IFP_LOGICAL_TABLE_SELECTm, INVALIDm, _SOC_SER_TYPE_PARITY, 9276 _SOC_SER_PARITY_8BITS, _SOC_SER_INTERLEAVE_MOD2, 9277 { {0, 96}, {1, 96}, {97, 192}, {98, 192} }, 0, 0, 0, 0, 9278 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9279 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9280 _SOC_MEM_ADDR_ACC_TYPE_PIPE_3 }, 9281 /* Unique view - initially disabled */ 9282 { IFP_LOGICAL_TABLE_SELECTm, INVALIDm, _SOC_SER_TYPE_PARITY, 9283 _SOC_SER_PARITY_8BITS, _SOC_SER_INTERLEAVE_MOD2, 9284 { {0, 96}, {1, 96}, {97, 192}, {98, 192} }, 0, 0, 0, 0, 9285 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9286 _SOC_SER_FLAG_XY_READ | 9287 _SOC_SER_FLAG_ACC_TYPE_CHK | _SOC_SER_FLAG_VIEW_DISABLE, 4 }, 9288 9289 /* Global view */ 9290 { EXACT_MATCH_LOGICAL_TABLE_SELECTm, INVALIDm, _SOC_SER_TYPE_PARITY, 9291 _SOC_SER_PARITY_8BITS, _SOC_SER_INTERLEAVE_MOD2, 9292 { {0, 80}, {1, 80}, {81, 160}, {82, 160} }, 0, 0, 0, 0, 9293 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9294 _SOC_SER_FLAG_XY_READ | _SOC_MEM_ADDR_ACC_TYPE_PIPE_0 }, 9295 { EXACT_MATCH_LOGICAL_TABLE_SELECTm, INVALIDm, _SOC_SER_TYPE_PARITY, 9296 _SOC_SER_PARITY_8BITS, _SOC_SER_INTERLEAVE_MOD2, 9297 { {0, 80}, {1, 80}, {81, 160}, {82, 160} }, 0, 0, 0, 0, 9298 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9299 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9300 _SOC_MEM_ADDR_ACC_TYPE_PIPE_1 }, 9301 { EXACT_MATCH_LOGICAL_TABLE_SELECTm, INVALIDm, _SOC_SER_TYPE_PARITY, 9302 _SOC_SER_PARITY_8BITS, _SOC_SER_INTERLEAVE_MOD2, 9303 { {0, 80}, {1, 80}, {81, 160}, {82, 160} }, 0, 0, 0, 0, 9304 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9305 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9306 _SOC_MEM_ADDR_ACC_TYPE_PIPE_2 }, 9307 { EXACT_MATCH_LOGICAL_TABLE_SELECTm, INVALIDm, _SOC_SER_TYPE_PARITY, 9308 _SOC_SER_PARITY_8BITS, _SOC_SER_INTERLEAVE_MOD2, 9309 { {0, 80}, {1, 80}, {81, 160}, {82, 160} }, 0, 0, 0, 0, 9310 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9311 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9312 _SOC_MEM_ADDR_ACC_TYPE_PIPE_3 }, 9313 /* Unique view - initially disabled */ 9314 { EXACT_MATCH_LOGICAL_TABLE_SELECTm, INVALIDm, _SOC_SER_TYPE_PARITY, 9315 _SOC_SER_PARITY_8BITS, _SOC_SER_INTERLEAVE_MOD2, 9316 { {0, 80}, {1, 80}, {81, 160}, {82, 160} }, 0, 0, 0, 0, 9317 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9318 _SOC_SER_FLAG_XY_READ | 9319 _SOC_SER_FLAG_ACC_TYPE_CHK | _SOC_SER_FLAG_VIEW_DISABLE, 4 }, 9320 9321 /* Global view */ 9322 { EFP_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9323 _SOC_SER_INTERLEAVE_MOD2, 9324 { {0, 241}, {1, 241}, {242, 481}, {243, 481} }, 0, 0, 0, 0, 9325 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9326 _SOC_SER_FLAG_XY_READ | _SOC_MEM_ADDR_ACC_TYPE_PIPE_0 }, 9327 { EFP_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9328 _SOC_SER_INTERLEAVE_MOD2, 9329 { {0, 241}, {1, 241}, {242, 481}, {243, 481} }, 0, 0, 0, 0, 9330 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9331 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9332 _SOC_MEM_ADDR_ACC_TYPE_PIPE_1 }, 9333 { EFP_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9334 _SOC_SER_INTERLEAVE_MOD2, 9335 { {0, 241}, {1, 241}, {242, 481}, {243, 481} }, 0, 0, 0, 0, 9336 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9337 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9338 _SOC_MEM_ADDR_ACC_TYPE_PIPE_2 }, 9339 { EFP_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9340 _SOC_SER_INTERLEAVE_MOD2, 9341 { {0, 241}, {1, 241}, {242, 481}, {243, 481} }, 0, 0, 0, 0, 9342 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9343 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9344 _SOC_MEM_ADDR_ACC_TYPE_PIPE_3 }, 9345 /* Unique view - initially disabled */ 9346 { EFP_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9347 _SOC_SER_INTERLEAVE_MOD2, 9348 { {0, 241}, {1, 241}, {242, 481}, {243, 481} }, 0, 0, 0, 0, 9349 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9350 _SOC_SER_FLAG_XY_READ | 9351 _SOC_SER_FLAG_ACC_TYPE_CHK | _SOC_SER_FLAG_VIEW_DISABLE, 4 }, 9352 9353 /* Global view */ 9354 { IFP_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9355 _SOC_SER_INTERLEAVE_MOD2, 9356 { {0, 80}, {1, 80}, {81, 160}, {82, 160} }, 0, 0, 0, 0, 9357 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9358 _SOC_SER_FLAG_XY_READ | 9359 _SOC_MEM_ADDR_ACC_TYPE_PIPE_0}, 9360 { IFP_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9361 _SOC_SER_INTERLEAVE_MOD2, 9362 { {0, 80}, {1, 80}, {81, 160}, {82, 160} }, 0, 0, 0, 0, 9363 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9364 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9365 _SOC_MEM_ADDR_ACC_TYPE_PIPE_1 }, 9366 { IFP_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9367 _SOC_SER_INTERLEAVE_MOD2, 9368 { {0, 80}, {1, 80}, {81, 160}, {82, 160} }, 0, 0, 0, 0, 9369 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9370 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9371 _SOC_MEM_ADDR_ACC_TYPE_PIPE_2 }, 9372 { IFP_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9373 _SOC_SER_INTERLEAVE_MOD2, 9374 { {0, 80}, {1, 80}, {81, 160}, {82, 160} }, 0, 0, 0, 0, 9375 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9376 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9377 _SOC_MEM_ADDR_ACC_TYPE_PIPE_3 }, 9378 /* Unique view - initially disabled */ 9379 { IFP_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9380 _SOC_SER_INTERLEAVE_MOD2, 9381 { {0, 80}, {1, 80}, {81, 160}, {82, 160} }, 0, 0, 0, 0, 9382 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9383 _SOC_SER_FLAG_XY_READ | 9384 _SOC_SER_FLAG_ACC_TYPE_CHK | _SOC_SER_FLAG_VIEW_DISABLE, 4 }, 9385 9386 /* Global view */ 9387 { IFP_TCAM_WIDEm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9388 _SOC_SER_INTERLEAVE_MOD2, 9389 { {0, 161}, {1, 161}, {162, 321}, {163, 321} }, 0, 0, 0, 0, 9390 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9391 _SOC_SER_FLAG_XY_READ | 9392 _SOC_MEM_ADDR_ACC_TYPE_PIPE_0}, 9393 { IFP_TCAM_WIDEm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9394 _SOC_SER_INTERLEAVE_MOD2, 9395 { {0, 161}, {1, 161}, {162, 321}, {163, 321} }, 0, 0, 0, 0, 9396 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9397 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9398 _SOC_MEM_ADDR_ACC_TYPE_PIPE_1 }, 9399 { IFP_TCAM_WIDEm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9400 _SOC_SER_INTERLEAVE_MOD2, 9401 { {0, 161}, {1, 161}, {162, 321}, {163, 321} }, 0, 0, 0, 0, 9402 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9403 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9404 _SOC_MEM_ADDR_ACC_TYPE_PIPE_2 }, 9405 { IFP_TCAM_WIDEm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9406 _SOC_SER_INTERLEAVE_MOD2, 9407 { {0, 161}, {1, 161}, {162, 321}, {163, 321} }, 0, 0, 0, 0, 9408 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9409 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9410 _SOC_MEM_ADDR_ACC_TYPE_PIPE_3 }, 9411 /* Unique view - initially disabled */ 9412 { IFP_TCAM_WIDEm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9413 _SOC_SER_INTERLEAVE_MOD2, 9414 { {0, 161}, {1, 161}, {162, 321}, {163, 321} }, 0, 0, 0, 0, 9415 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9416 _SOC_SER_FLAG_XY_READ | 9417 _SOC_SER_FLAG_ACC_TYPE_CHK | _SOC_SER_FLAG_VIEW_DISABLE, 4 }, 9418 9419 /* End of list */ 9420 { INVALIDm }, 9421 }; 9422 9423 #ifdef BCM_TOMAHAWK2_SUPPORT 9424 static _soc_generic_ser_info_t _soc_th2_tcam_ser_info_template[] = { 9425 { L3_TUNNELm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9426 _SOC_SER_INTERLEAVE_MOD2, 9427 { {0, 140}, {1, 140}, {141, 280}, {142, 280} }, 0, 0, 0, 0, 9428 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9429 _SOC_SER_FLAG_XY_READ | _SOC_MEM_ADDR_ACC_TYPE_PIPE_0 }, 9430 { L3_TUNNELm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9431 _SOC_SER_INTERLEAVE_MOD2, 9432 { {0, 140}, {1, 140}, {141, 280}, {142, 280} }, 0, 0, 0, 0, 9433 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9434 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9435 _SOC_MEM_ADDR_ACC_TYPE_PIPE_1 }, 9436 { L3_TUNNELm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9437 _SOC_SER_INTERLEAVE_MOD2, 9438 { {0, 140}, {1, 140}, {141, 280}, {142, 280} }, 0, 0, 0, 0, 9439 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9440 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9441 _SOC_MEM_ADDR_ACC_TYPE_PIPE_2 }, 9442 { L3_TUNNELm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9443 _SOC_SER_INTERLEAVE_MOD2, 9444 { {0, 140}, {1, 140}, {141, 280}, {142, 280} }, 0, 0, 0, 0, 9445 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9446 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9447 _SOC_MEM_ADDR_ACC_TYPE_PIPE_3 }, 9448 9449 /* default_acc_type = DATA_SPLIT, but still need to scan each pipe separately */ 9450 { ING_SNATm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9451 _SOC_SER_INTERLEAVE_MOD2, 9452 { {0, 80}, {1, 80}, {81, 160}, {82, 160} }, 0, 0, 0, 0, 9453 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9454 _SOC_SER_FLAG_XY_READ | _SOC_MEM_ADDR_ACC_TYPE_PIPE_0 }, 9455 { ING_SNATm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9456 _SOC_SER_INTERLEAVE_MOD2, 9457 { {0, 80}, {1, 80}, {81, 160}, {82, 160} }, 0, 0, 0, 0, 9458 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9459 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9460 _SOC_MEM_ADDR_ACC_TYPE_PIPE_1 }, 9461 { ING_SNATm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9462 _SOC_SER_INTERLEAVE_MOD2, 9463 { {0, 80}, {1, 80}, {81, 160}, {82, 160} }, 0, 0, 0, 0, 9464 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9465 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9466 _SOC_MEM_ADDR_ACC_TYPE_PIPE_2 }, 9467 { ING_SNATm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9468 _SOC_SER_INTERLEAVE_MOD2, 9469 { {0, 80}, {1, 80}, {81, 160}, {82, 160} }, 0, 0, 0, 0, 9470 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9471 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9472 _SOC_MEM_ADDR_ACC_TYPE_PIPE_3 }, 9473 9474 /* default_acc_type = DUPLICATE, so need to scan each pipe separately */ 9475 { VLAN_SUBNETm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9476 _SOC_SER_INTERLEAVE_MOD2, 9477 { {0, 80}, {1, 80}, {81, 160}, {82, 160} }, 0, 0, 0, 0, 9478 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9479 _SOC_SER_FLAG_XY_READ | _SOC_MEM_ADDR_ACC_TYPE_PIPE_0 }, 9480 { VLAN_SUBNETm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9481 _SOC_SER_INTERLEAVE_MOD2, 9482 { {0, 80}, {1, 80}, {81, 160}, {82, 160} }, 0, 0, 0, 0, 9483 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9484 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9485 _SOC_MEM_ADDR_ACC_TYPE_PIPE_1 }, 9486 { VLAN_SUBNETm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9487 _SOC_SER_INTERLEAVE_MOD2, 9488 { {0, 80}, {1, 80}, {81, 160}, {82, 160} }, 0, 0, 0, 0, 9489 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9490 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9491 _SOC_MEM_ADDR_ACC_TYPE_PIPE_2 }, 9492 { VLAN_SUBNETm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9493 _SOC_SER_INTERLEAVE_MOD2, 9494 { {0, 80}, {1, 80}, {81, 160}, {82, 160} }, 0, 0, 0, 0, 9495 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9496 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9497 _SOC_MEM_ADDR_ACC_TYPE_PIPE_3 }, 9498 9499 /* default_acc_type = DUPLICATE, so need to scan each pipe separately */ 9500 { MY_STATION_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9501 _SOC_SER_INTERLEAVE_MOD2, 9502 { {0, 80}, {1, 80}, {81, 160}, {82, 160} }, 0, 0, 0, 0, 9503 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9504 _SOC_SER_FLAG_XY_READ | _SOC_MEM_ADDR_ACC_TYPE_PIPE_0 }, 9505 { MY_STATION_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9506 _SOC_SER_INTERLEAVE_MOD2, 9507 { {0, 80}, {1, 80}, {81, 160}, {82, 160} }, 0, 0, 0, 0, 9508 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9509 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9510 _SOC_MEM_ADDR_ACC_TYPE_PIPE_1 }, 9511 { MY_STATION_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9512 _SOC_SER_INTERLEAVE_MOD2, 9513 { {0, 80}, {1, 80}, {81, 160}, {82, 160} }, 0, 0, 0, 0, 9514 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9515 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9516 _SOC_MEM_ADDR_ACC_TYPE_PIPE_2 }, 9517 { MY_STATION_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9518 _SOC_SER_INTERLEAVE_MOD2, 9519 { {0, 80}, {1, 80}, {81, 160}, {82, 160} }, 0, 0, 0, 0, 9520 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9521 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9522 _SOC_MEM_ADDR_ACC_TYPE_PIPE_3 }, 9523 9524 /* default_acc_type = DUPLICATE, so need to scan each pipe separately */ 9525 { IP_MULTICAST_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9526 _SOC_SER_INTERLEAVE_MOD2, 9527 { {0, 145}, {1, 145}, {146, 289}, {147, 289} }, 0, 0, 0, 0, 9528 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9529 _SOC_SER_FLAG_XY_READ | _SOC_MEM_ADDR_ACC_TYPE_PIPE_0 }, 9530 { IP_MULTICAST_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9531 _SOC_SER_INTERLEAVE_MOD2, 9532 { {0, 145}, {1, 145}, {146, 289}, {147, 289} }, 0, 0, 0, 0, 9533 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9534 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9535 _SOC_MEM_ADDR_ACC_TYPE_PIPE_1 }, 9536 { IP_MULTICAST_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9537 _SOC_SER_INTERLEAVE_MOD2, 9538 { {0, 145}, {1, 145}, {146, 289}, {147, 289} }, 0, 0, 0, 0, 9539 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9540 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9541 _SOC_MEM_ADDR_ACC_TYPE_PIPE_2 }, 9542 { IP_MULTICAST_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9543 _SOC_SER_INTERLEAVE_MOD2, 9544 { {0, 145}, {1, 145}, {146, 289}, {147, 289} }, 0, 0, 0, 0, 9545 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9546 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9547 _SOC_MEM_ADDR_ACC_TYPE_PIPE_3 }, 9548 9549 /* default_acc_type = DUPLICATE, so need to scan each pipe separately */ 9550 { L2_USER_ENTRYm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9551 _SOC_SER_INTERLEAVE_MOD2, 9552 { {0, 80}, {1, 80}, {81, 160}, {82, 160} }, 0, 0, 0, 0, 9553 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9554 _SOC_SER_FLAG_XY_READ | _SOC_MEM_ADDR_ACC_TYPE_PIPE_0 }, 9555 { L2_USER_ENTRYm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9556 _SOC_SER_INTERLEAVE_MOD2, 9557 { {0, 80}, {1, 80}, {81, 160}, {82, 160} }, 0, 0, 0, 0, 9558 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9559 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9560 _SOC_MEM_ADDR_ACC_TYPE_PIPE_1 }, 9561 { L2_USER_ENTRYm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9562 _SOC_SER_INTERLEAVE_MOD2, 9563 { {0, 80}, {1, 80}, {81, 160}, {82, 160} }, 0, 0, 0, 0, 9564 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9565 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9566 _SOC_MEM_ADDR_ACC_TYPE_PIPE_2 }, 9567 { L2_USER_ENTRYm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9568 _SOC_SER_INTERLEAVE_MOD2, 9569 { {0, 80}, {1, 80}, {81, 160}, {82, 160} }, 0, 0, 0, 0, 9570 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9571 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9572 _SOC_MEM_ADDR_ACC_TYPE_PIPE_3 }, 9573 9574 /* default_acc_type = DUPLICATE, so need to scan each pipe separately */ 9575 { CPU_COS_MAPm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9576 _SOC_SER_INTERLEAVE_MOD2, 9577 { {0, 145}, {1, 145}, {146, 289}, {147, 289} }, 0, 0, 0, 0, 9578 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9579 _SOC_SER_FLAG_XY_READ | _SOC_MEM_ADDR_ACC_TYPE_PIPE_0 }, 9580 { CPU_COS_MAPm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9581 _SOC_SER_INTERLEAVE_MOD2, 9582 { {0, 145}, {1, 145}, {146, 289}, {147, 289} }, 0, 0, 0, 0, 9583 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9584 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9585 _SOC_MEM_ADDR_ACC_TYPE_PIPE_1 }, 9586 { CPU_COS_MAPm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9587 _SOC_SER_INTERLEAVE_MOD2, 9588 { {0, 145}, {1, 145}, {146, 289}, {147, 289} }, 0, 0, 0, 0, 9589 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9590 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9591 _SOC_MEM_ADDR_ACC_TYPE_PIPE_2 }, 9592 { CPU_COS_MAPm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9593 _SOC_SER_INTERLEAVE_MOD2, 9594 { {0, 145}, {1, 145}, {146, 289}, {147, 289} }, 0, 0, 0, 0, 9595 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9596 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9597 _SOC_MEM_ADDR_ACC_TYPE_PIPE_3 }, 9598 9599 /* default_acc_type = DATA_SPLIT, but still need to scan each pipe separately */ 9600 { L3_DEFIPm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9601 _SOC_SER_INTERLEAVE_MOD2, 9602 { {0, 97}, {1, 97}, {98, 193}, {99, 193} }, 0, 0, 0, 0, 9603 _SOC_SER_FLAG_NO_DMA | _SOC_SER_FLAG_MULTI_PIPE | 9604 _SOC_SER_FLAG_REMAP_READ | _SOC_SER_FLAG_SIZE_VERIFY | 9605 _SOC_SER_FLAG_XY_READ | _SOC_MEM_ADDR_ACC_TYPE_PIPE_0 }, 9606 { L3_DEFIPm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9607 _SOC_SER_INTERLEAVE_MOD2, 9608 { {0, 97}, {1, 97}, {98, 193}, {99, 193} }, 0, 0, 0, 0, 9609 _SOC_SER_FLAG_NO_DMA | _SOC_SER_FLAG_MULTI_PIPE | 9610 _SOC_SER_FLAG_REMAP_READ | _SOC_SER_FLAG_SIZE_VERIFY | 9611 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9612 _SOC_MEM_ADDR_ACC_TYPE_PIPE_1 }, 9613 { L3_DEFIPm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9614 _SOC_SER_INTERLEAVE_MOD2, 9615 { {0, 97}, {1, 97}, {98, 193}, {99, 193} }, 0, 0, 0, 0, 9616 _SOC_SER_FLAG_NO_DMA | _SOC_SER_FLAG_MULTI_PIPE | 9617 _SOC_SER_FLAG_REMAP_READ | _SOC_SER_FLAG_SIZE_VERIFY | 9618 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9619 _SOC_MEM_ADDR_ACC_TYPE_PIPE_2 }, 9620 { L3_DEFIPm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9621 _SOC_SER_INTERLEAVE_MOD2, 9622 { {0, 97}, {1, 97}, {98, 193}, {99, 193} }, 0, 0, 0, 0, 9623 _SOC_SER_FLAG_NO_DMA | _SOC_SER_FLAG_MULTI_PIPE | 9624 _SOC_SER_FLAG_REMAP_READ | _SOC_SER_FLAG_SIZE_VERIFY | 9625 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9626 _SOC_MEM_ADDR_ACC_TYPE_PIPE_3 }, 9627 9628 /* default_acc_type = DATA_SPLIT, but still need to scan each pipe separately */ 9629 { L3_DEFIP_PAIR_128m, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9630 _SOC_SER_INTERLEAVE_MOD2, 9631 { {0, 195}, {1, 195}, {196, 387}, {197, 387} }, 0, 0, 0, 0, 9632 _SOC_SER_FLAG_NO_DMA | _SOC_SER_FLAG_MULTI_PIPE | 9633 _SOC_SER_FLAG_REMAP_READ | _SOC_SER_FLAG_SIZE_VERIFY | 9634 _SOC_SER_FLAG_XY_READ | _SOC_MEM_ADDR_ACC_TYPE_PIPE_0 }, 9635 { L3_DEFIP_PAIR_128m, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9636 _SOC_SER_INTERLEAVE_MOD2, 9637 { {0, 195}, {1, 195}, {196, 387}, {197, 387} }, 0, 0, 0, 0, 9638 _SOC_SER_FLAG_NO_DMA | _SOC_SER_FLAG_MULTI_PIPE | 9639 _SOC_SER_FLAG_REMAP_READ | _SOC_SER_FLAG_SIZE_VERIFY | 9640 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9641 _SOC_MEM_ADDR_ACC_TYPE_PIPE_1 }, 9642 { L3_DEFIP_PAIR_128m, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9643 _SOC_SER_INTERLEAVE_MOD2, 9644 { {0, 195}, {1, 195}, {196, 387}, {197, 387} }, 0, 0, 0, 0, 9645 _SOC_SER_FLAG_NO_DMA | _SOC_SER_FLAG_MULTI_PIPE | 9646 _SOC_SER_FLAG_REMAP_READ | _SOC_SER_FLAG_SIZE_VERIFY | 9647 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9648 _SOC_MEM_ADDR_ACC_TYPE_PIPE_2 }, 9649 { L3_DEFIP_PAIR_128m, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9650 _SOC_SER_INTERLEAVE_MOD2, 9651 { {0, 195}, {1, 195}, {196, 387}, {197, 387} }, 0, 0, 0, 0, 9652 _SOC_SER_FLAG_NO_DMA | _SOC_SER_FLAG_MULTI_PIPE | 9653 _SOC_SER_FLAG_REMAP_READ | _SOC_SER_FLAG_SIZE_VERIFY | 9654 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9655 _SOC_MEM_ADDR_ACC_TYPE_PIPE_3 }, 9656 9657 /* Global view */ 9658 { SRC_COMPRESSIONm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9659 _SOC_SER_INTERLEAVE_MOD2, 9660 { {0, 145}, {1, 145}, {146, 289}, {147, 289} }, 0, 0, 0, 0, 9661 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9662 _SOC_SER_FLAG_XY_READ | _SOC_MEM_ADDR_ACC_TYPE_PIPE_0 }, 9663 { SRC_COMPRESSIONm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9664 _SOC_SER_INTERLEAVE_MOD2, 9665 { {0, 145}, {1, 145}, {146, 289}, {147, 289} }, 0, 0, 0, 0, 9666 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9667 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9668 _SOC_MEM_ADDR_ACC_TYPE_PIPE_1 }, 9669 { SRC_COMPRESSIONm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9670 _SOC_SER_INTERLEAVE_MOD2, 9671 { {0, 145}, {1, 145}, {146, 289}, {147, 289} }, 0, 0, 0, 0, 9672 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9673 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9674 _SOC_MEM_ADDR_ACC_TYPE_PIPE_2 }, 9675 { SRC_COMPRESSIONm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9676 _SOC_SER_INTERLEAVE_MOD2, 9677 { {0, 145}, {1, 145}, {146, 289}, {147, 289} }, 0, 0, 0, 0, 9678 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9679 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9680 _SOC_MEM_ADDR_ACC_TYPE_PIPE_3 }, 9681 /* Unique view - initially disabled */ 9682 { SRC_COMPRESSIONm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9683 _SOC_SER_INTERLEAVE_MOD2, 9684 { {0, 145}, {1, 145}, {146, 289}, {147, 289} }, 0, 0, 0, 0, 9685 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9686 _SOC_SER_FLAG_XY_READ | 9687 _SOC_SER_FLAG_ACC_TYPE_CHK | _SOC_SER_FLAG_VIEW_DISABLE, 4 }, 9688 9689 /* Global view */ 9690 { DST_COMPRESSIONm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9691 _SOC_SER_INTERLEAVE_MOD2, 9692 { {0, 145}, {1, 145}, {146, 289}, {147, 289} }, 0, 0, 0, 0, 9693 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9694 _SOC_SER_FLAG_XY_READ | _SOC_MEM_ADDR_ACC_TYPE_PIPE_0 }, 9695 { DST_COMPRESSIONm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9696 _SOC_SER_INTERLEAVE_MOD2, 9697 { {0, 145}, {1, 145}, {146, 289}, {147, 289} }, 0, 0, 0, 0, 9698 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9699 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9700 _SOC_MEM_ADDR_ACC_TYPE_PIPE_1 }, 9701 { DST_COMPRESSIONm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9702 _SOC_SER_INTERLEAVE_MOD2, 9703 { {0, 145}, {1, 145}, {146, 289}, {147, 289} }, 0, 0, 0, 0, 9704 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9705 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9706 _SOC_MEM_ADDR_ACC_TYPE_PIPE_2 }, 9707 { DST_COMPRESSIONm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9708 _SOC_SER_INTERLEAVE_MOD2, 9709 { {0, 145}, {1, 145}, {146, 289}, {147, 289} }, 0, 0, 0, 0, 9710 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9711 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9712 _SOC_MEM_ADDR_ACC_TYPE_PIPE_3 }, 9713 /* Unique view - initially disabled */ 9714 { DST_COMPRESSIONm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9715 _SOC_SER_INTERLEAVE_MOD2, 9716 { {0, 145}, {1, 145}, {146, 289}, {147, 289} }, 0, 0, 0, 0, 9717 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9718 _SOC_SER_FLAG_XY_READ | 9719 _SOC_SER_FLAG_ACC_TYPE_CHK | _SOC_SER_FLAG_VIEW_DISABLE, 4 }, 9720 9721 /* Global view */ 9722 { FP_UDF_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9723 _SOC_SER_INTERLEAVE_MOD2, 9724 { {0, 80}, {1, 80}, {81, 160}, {82, 160} }, 0, 0, 0, 0, 9725 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9726 _SOC_SER_FLAG_XY_READ | _SOC_MEM_ADDR_ACC_TYPE_PIPE_0 }, 9727 { FP_UDF_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9728 _SOC_SER_INTERLEAVE_MOD2, 9729 { {0, 80}, {1, 80}, {81, 160}, {82, 160} }, 0, 0, 0, 0, 9730 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9731 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9732 _SOC_MEM_ADDR_ACC_TYPE_PIPE_1 }, 9733 { FP_UDF_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9734 _SOC_SER_INTERLEAVE_MOD2, 9735 { {0, 80}, {1, 80}, {81, 160}, {82, 160} }, 0, 0, 0, 0, 9736 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9737 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9738 _SOC_MEM_ADDR_ACC_TYPE_PIPE_2 }, 9739 { FP_UDF_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9740 _SOC_SER_INTERLEAVE_MOD2, 9741 { {0, 80}, {1, 80}, {81, 160}, {82, 160} }, 0, 0, 0, 0, 9742 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9743 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9744 _SOC_MEM_ADDR_ACC_TYPE_PIPE_3 }, 9745 /* Unique view - initially disabled */ 9746 { FP_UDF_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9747 _SOC_SER_INTERLEAVE_MOD2, 9748 { {0, 80}, {1, 80}, {81, 160}, {82, 160} }, 0, 0, 0, 0, 9749 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9750 _SOC_SER_FLAG_XY_READ | 9751 _SOC_SER_FLAG_ACC_TYPE_CHK | _SOC_SER_FLAG_VIEW_DISABLE, 4 }, 9752 9753 /* Global view */ 9754 { VFP_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9755 _SOC_SER_INTERLEAVE_MOD2, 9756 { {0, 236}, {1, 236}, {237, 472}, {238, 472} }, 0, 0, 0, 0, 9757 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9758 _SOC_SER_FLAG_XY_READ | _SOC_MEM_ADDR_ACC_TYPE_PIPE_0 }, 9759 { VFP_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9760 _SOC_SER_INTERLEAVE_MOD2, 9761 { {0, 236}, {1, 236}, {237, 472}, {238, 472} }, 0, 0, 0, 0, 9762 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9763 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9764 _SOC_MEM_ADDR_ACC_TYPE_PIPE_1 }, 9765 { VFP_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9766 _SOC_SER_INTERLEAVE_MOD2, 9767 { {0, 236}, {1, 236}, {237, 472}, {238, 472} }, 0, 0, 0, 0, 9768 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9769 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9770 _SOC_MEM_ADDR_ACC_TYPE_PIPE_2 }, 9771 { VFP_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9772 _SOC_SER_INTERLEAVE_MOD2, 9773 { {0, 236}, {1, 236}, {237, 472}, {238, 472} }, 0, 0, 0, 0, 9774 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9775 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9776 _SOC_MEM_ADDR_ACC_TYPE_PIPE_3 }, 9777 /* Unique view - initially disabled */ 9778 { VFP_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9779 _SOC_SER_INTERLEAVE_MOD2, 9780 { {0, 236}, {1, 236}, {237, 472}, {238, 472} }, 0, 0, 0, 0, 9781 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9782 _SOC_SER_FLAG_XY_READ | 9783 _SOC_SER_FLAG_ACC_TYPE_CHK | _SOC_SER_FLAG_VIEW_DISABLE, 4 }, 9784 9785 /* Global view */ 9786 { IFP_LOGICAL_TABLE_SELECTm, INVALIDm, _SOC_SER_TYPE_PARITY, 9787 _SOC_SER_PARITY_8BITS, _SOC_SER_INTERLEAVE_MOD2, 9788 { {0, 97}, {1, 97}, {98, 193}, {99, 193} }, 0, 0, 0, 0, 9789 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9790 _SOC_SER_FLAG_XY_READ | _SOC_MEM_ADDR_ACC_TYPE_PIPE_0 }, 9791 { IFP_LOGICAL_TABLE_SELECTm, INVALIDm, _SOC_SER_TYPE_PARITY, 9792 _SOC_SER_PARITY_8BITS, _SOC_SER_INTERLEAVE_MOD2, 9793 { {0, 97}, {1, 97}, {98, 193}, {99, 193} }, 0, 0, 0, 0, 9794 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9795 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9796 _SOC_MEM_ADDR_ACC_TYPE_PIPE_1 }, 9797 { IFP_LOGICAL_TABLE_SELECTm, INVALIDm, _SOC_SER_TYPE_PARITY, 9798 _SOC_SER_PARITY_8BITS, _SOC_SER_INTERLEAVE_MOD2, 9799 { {0, 97}, {1, 97}, {98, 193}, {99, 193} }, 0, 0, 0, 0, 9800 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9801 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9802 _SOC_MEM_ADDR_ACC_TYPE_PIPE_2 }, 9803 { IFP_LOGICAL_TABLE_SELECTm, INVALIDm, _SOC_SER_TYPE_PARITY, 9804 _SOC_SER_PARITY_8BITS, _SOC_SER_INTERLEAVE_MOD2, 9805 { {0, 97}, {1, 97}, {98, 193}, {99, 193} }, 0, 0, 0, 0, 9806 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9807 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9808 _SOC_MEM_ADDR_ACC_TYPE_PIPE_3 }, 9809 /* Unique view - initially disabled */ 9810 { IFP_LOGICAL_TABLE_SELECTm, INVALIDm, _SOC_SER_TYPE_PARITY, 9811 _SOC_SER_PARITY_8BITS, _SOC_SER_INTERLEAVE_MOD2, 9812 { {0, 97}, {1, 97}, {98, 193}, {99, 193} }, 0, 0, 0, 0, 9813 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9814 _SOC_SER_FLAG_XY_READ | 9815 _SOC_SER_FLAG_ACC_TYPE_CHK | _SOC_SER_FLAG_VIEW_DISABLE, 4 }, 9816 9817 /* Global view */ 9818 { EXACT_MATCH_LOGICAL_TABLE_SELECTm, INVALIDm, _SOC_SER_TYPE_PARITY, 9819 _SOC_SER_PARITY_8BITS, _SOC_SER_INTERLEAVE_MOD2, 9820 { {0, 80}, {1, 80}, {81, 160}, {82, 160} }, 0, 0, 0, 0, 9821 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9822 _SOC_SER_FLAG_XY_READ | _SOC_MEM_ADDR_ACC_TYPE_PIPE_0 }, 9823 { EXACT_MATCH_LOGICAL_TABLE_SELECTm, INVALIDm, _SOC_SER_TYPE_PARITY, 9824 _SOC_SER_PARITY_8BITS, _SOC_SER_INTERLEAVE_MOD2, 9825 { {0, 80}, {1, 80}, {81, 160}, {82, 160} }, 0, 0, 0, 0, 9826 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9827 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9828 _SOC_MEM_ADDR_ACC_TYPE_PIPE_1 }, 9829 { EXACT_MATCH_LOGICAL_TABLE_SELECTm, INVALIDm, _SOC_SER_TYPE_PARITY, 9830 _SOC_SER_PARITY_8BITS, _SOC_SER_INTERLEAVE_MOD2, 9831 { {0, 80}, {1, 80}, {81, 160}, {82, 160} }, 0, 0, 0, 0, 9832 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9833 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9834 _SOC_MEM_ADDR_ACC_TYPE_PIPE_2 }, 9835 { EXACT_MATCH_LOGICAL_TABLE_SELECTm, INVALIDm, _SOC_SER_TYPE_PARITY, 9836 _SOC_SER_PARITY_8BITS, _SOC_SER_INTERLEAVE_MOD2, 9837 { {0, 80}, {1, 80}, {81, 160}, {82, 160} }, 0, 0, 0, 0, 9838 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9839 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9840 _SOC_MEM_ADDR_ACC_TYPE_PIPE_3 }, 9841 /* Unique view - initially disabled */ 9842 { EXACT_MATCH_LOGICAL_TABLE_SELECTm, INVALIDm, _SOC_SER_TYPE_PARITY, 9843 _SOC_SER_PARITY_8BITS, _SOC_SER_INTERLEAVE_MOD2, 9844 { {0, 80}, {1, 80}, {81, 160}, {82, 160} }, 0, 0, 0, 0, 9845 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9846 _SOC_SER_FLAG_XY_READ | 9847 _SOC_SER_FLAG_ACC_TYPE_CHK | _SOC_SER_FLAG_VIEW_DISABLE, 4 }, 9848 9849 /* Global view */ 9850 { EFP_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9851 _SOC_SER_INTERLEAVE_MOD2, 9852 { {0, 241}, {1, 241}, {242, 481}, {243, 481} }, 0, 0, 0, 0, 9853 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9854 _SOC_SER_FLAG_XY_READ | _SOC_MEM_ADDR_ACC_TYPE_PIPE_0 }, 9855 { EFP_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9856 _SOC_SER_INTERLEAVE_MOD2, 9857 { {0, 241}, {1, 241}, {242, 481}, {243, 481} }, 0, 0, 0, 0, 9858 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9859 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9860 _SOC_MEM_ADDR_ACC_TYPE_PIPE_1 }, 9861 { EFP_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9862 _SOC_SER_INTERLEAVE_MOD2, 9863 { {0, 241}, {1, 241}, {242, 481}, {243, 481} }, 0, 0, 0, 0, 9864 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9865 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9866 _SOC_MEM_ADDR_ACC_TYPE_PIPE_2 }, 9867 { EFP_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9868 _SOC_SER_INTERLEAVE_MOD2, 9869 { {0, 241}, {1, 241}, {242, 481}, {243, 481} }, 0, 0, 0, 0, 9870 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9871 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9872 _SOC_MEM_ADDR_ACC_TYPE_PIPE_3 }, 9873 /* Unique view - initially disabled */ 9874 { EFP_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9875 _SOC_SER_INTERLEAVE_MOD2, 9876 { {0, 241}, {1, 241}, {242, 481}, {243, 481} }, 0, 0, 0, 0, 9877 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9878 _SOC_SER_FLAG_XY_READ | 9879 _SOC_SER_FLAG_ACC_TYPE_CHK | _SOC_SER_FLAG_VIEW_DISABLE, 4 }, 9880 9881 /* Global view */ 9882 { IFP_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9883 _SOC_SER_INTERLEAVE_MOD2, 9884 { {0, 80}, {1, 80}, {81, 160}, {82, 160} }, 0, 0, 0, 0, 9885 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9886 _SOC_SER_FLAG_XY_READ | 9887 _SOC_MEM_ADDR_ACC_TYPE_PIPE_0}, 9888 { IFP_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9889 _SOC_SER_INTERLEAVE_MOD2, 9890 { {0, 80}, {1, 80}, {81, 160}, {82, 160} }, 0, 0, 0, 0, 9891 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9892 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9893 _SOC_MEM_ADDR_ACC_TYPE_PIPE_1 }, 9894 { IFP_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9895 _SOC_SER_INTERLEAVE_MOD2, 9896 { {0, 80}, {1, 80}, {81, 160}, {82, 160} }, 0, 0, 0, 0, 9897 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9898 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9899 _SOC_MEM_ADDR_ACC_TYPE_PIPE_2 }, 9900 { IFP_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9901 _SOC_SER_INTERLEAVE_MOD2, 9902 { {0, 80}, {1, 80}, {81, 160}, {82, 160} }, 0, 0, 0, 0, 9903 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9904 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9905 _SOC_MEM_ADDR_ACC_TYPE_PIPE_3 }, 9906 /* Unique view - initially disabled */ 9907 { IFP_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9908 _SOC_SER_INTERLEAVE_MOD2, 9909 { {0, 80}, {1, 80}, {81, 160}, {82, 160} }, 0, 0, 0, 0, 9910 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9911 _SOC_SER_FLAG_XY_READ | 9912 _SOC_SER_FLAG_ACC_TYPE_CHK | _SOC_SER_FLAG_VIEW_DISABLE, 4 }, 9913 9914 /* Global view */ 9915 { IFP_TCAM_WIDEm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9916 _SOC_SER_INTERLEAVE_MOD2, 9917 { {0, 161}, {1, 161}, {162, 321}, {163, 321} }, 0, 0, 0, 0, 9918 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9919 _SOC_SER_FLAG_XY_READ | 9920 _SOC_MEM_ADDR_ACC_TYPE_PIPE_0}, 9921 { IFP_TCAM_WIDEm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9922 _SOC_SER_INTERLEAVE_MOD2, 9923 { {0, 161}, {1, 161}, {162, 321}, {163, 321} }, 0, 0, 0, 0, 9924 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9925 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9926 _SOC_MEM_ADDR_ACC_TYPE_PIPE_1 }, 9927 { IFP_TCAM_WIDEm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9928 _SOC_SER_INTERLEAVE_MOD2, 9929 { {0, 161}, {1, 161}, {162, 321}, {163, 321} }, 0, 0, 0, 0, 9930 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9931 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9932 _SOC_MEM_ADDR_ACC_TYPE_PIPE_2 }, 9933 { IFP_TCAM_WIDEm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9934 _SOC_SER_INTERLEAVE_MOD2, 9935 { {0, 161}, {1, 161}, {162, 321}, {163, 321} }, 0, 0, 0, 0, 9936 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9937 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9938 _SOC_MEM_ADDR_ACC_TYPE_PIPE_3 }, 9939 /* Unique view - initially disabled */ 9940 { IFP_TCAM_WIDEm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9941 _SOC_SER_INTERLEAVE_MOD2, 9942 { {0, 161}, {1, 161}, {162, 321}, {163, 321} }, 0, 0, 0, 0, 9943 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9944 _SOC_SER_FLAG_XY_READ | 9945 _SOC_SER_FLAG_ACC_TYPE_CHK | _SOC_SER_FLAG_VIEW_DISABLE, 4 }, 9946 9947 /* End of list */ 9948 { INVALIDm }, 9949 }; 9950 9951 static _soc_generic_ser_info_t _soc_th2_b0_tcam_ser_info_template[] = { 9952 /* Global view */ 9953 { EFP_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9954 _SOC_SER_INTERLEAVE_MOD2, 9955 { {0, 241}, {1, 241}, {242, 481}, {243, 481} }, 0, 0, 0, 0, 9956 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9957 _SOC_SER_FLAG_XY_READ | _SOC_MEM_ADDR_ACC_TYPE_PIPE_0 }, 9958 { EFP_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9959 _SOC_SER_INTERLEAVE_MOD2, 9960 { {0, 241}, {1, 241}, {242, 481}, {243, 481} }, 0, 0, 0, 0, 9961 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9962 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9963 _SOC_MEM_ADDR_ACC_TYPE_PIPE_1 }, 9964 { EFP_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9965 _SOC_SER_INTERLEAVE_MOD2, 9966 { {0, 241}, {1, 241}, {242, 481}, {243, 481} }, 0, 0, 0, 0, 9967 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9968 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9969 _SOC_MEM_ADDR_ACC_TYPE_PIPE_2 }, 9970 { EFP_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9971 _SOC_SER_INTERLEAVE_MOD2, 9972 { {0, 241}, {1, 241}, {242, 481}, {243, 481} }, 0, 0, 0, 0, 9973 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9974 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9975 _SOC_MEM_ADDR_ACC_TYPE_PIPE_3 }, 9976 /* Unique view - initially disabled */ 9977 { EFP_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_8BITS, 9978 _SOC_SER_INTERLEAVE_MOD2, 9979 { {0, 241}, {1, 241}, {242, 481}, {243, 481} }, 0, 0, 0, 0, 9980 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9981 _SOC_SER_FLAG_XY_READ | 9982 _SOC_SER_FLAG_ACC_TYPE_CHK | _SOC_SER_FLAG_VIEW_DISABLE, 4 }, 9983 9984 /* Global view */ 9985 { IFP_LOGICAL_TABLE_SELECTm, INVALIDm, _SOC_SER_TYPE_PARITY, 9986 _SOC_SER_PARITY_8BITS, _SOC_SER_INTERLEAVE_MOD2, 9987 { {0, 97}, {1, 97}, {98, 193}, {99, 193} }, 0, 0, 0, 0, 9988 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9989 _SOC_SER_FLAG_XY_READ | _SOC_MEM_ADDR_ACC_TYPE_PIPE_0 }, 9990 { IFP_LOGICAL_TABLE_SELECTm, INVALIDm, _SOC_SER_TYPE_PARITY, 9991 _SOC_SER_PARITY_8BITS, _SOC_SER_INTERLEAVE_MOD2, 9992 { {0, 97}, {1, 97}, {98, 193}, {99, 193} }, 0, 0, 0, 0, 9993 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 9994 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 9995 _SOC_MEM_ADDR_ACC_TYPE_PIPE_1 }, 9996 { IFP_LOGICAL_TABLE_SELECTm, INVALIDm, _SOC_SER_TYPE_PARITY, 9997 _SOC_SER_PARITY_8BITS, _SOC_SER_INTERLEAVE_MOD2, 9998 { {0, 97}, {1, 97}, {98, 193}, {99, 193} }, 0, 0, 0, 0, 9999 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 10000 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 10001 _SOC_MEM_ADDR_ACC_TYPE_PIPE_2 }, 10002 { IFP_LOGICAL_TABLE_SELECTm, INVALIDm, _SOC_SER_TYPE_PARITY, 10003 _SOC_SER_PARITY_8BITS, _SOC_SER_INTERLEAVE_MOD2, 10004 { {0, 97}, {1, 97}, {98, 193}, {99, 193} }, 0, 0, 0, 0, 10005 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 10006 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_CONFIG_SKIP | 10007 _SOC_MEM_ADDR_ACC_TYPE_PIPE_3 }, 10008 /* Unique view - initially disabled */ 10009 { IFP_LOGICAL_TABLE_SELECTm, INVALIDm, _SOC_SER_TYPE_PARITY, 10010 _SOC_SER_PARITY_8BITS, _SOC_SER_INTERLEAVE_MOD2, 10011 { {0, 97}, {1, 97}, {98, 193}, {99, 193} }, 0, 0, 0, 0, 10012 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_MULTI_PIPE | 10013 _SOC_SER_FLAG_XY_READ | 10014 _SOC_SER_FLAG_ACC_TYPE_CHK | _SOC_SER_FLAG_VIEW_DISABLE, 4 }, 10015 10016 /* End of list */ 10017 { INVALIDm }, 10018 }; 10019 #endif 10020 10021 static _soc_generic_ser_info_t *_soc_th_tcam_ser_info[SOC_MAX_NUM_DEVICES]; 10022 #if defined(BCM_TOMAHAWK2_SUPPORT) 10023 STATIC void 10024 _soc_th2_ser_info_flag_update(_soc_generic_ser_info_t *ser_info, 10025 soc_mem_t mem, uint32 flag, int enable) 10026 { 10027 int ser_idx = 0; 10028 /*This will update the flag of per-pipe memory too.*/ 10029 while (INVALIDm != ser_info[ser_idx].mem) { 10030 if (ser_info[ser_idx].mem == mem) { 10031 if (enable) { 10032 ser_info[ser_idx].ser_flags |= flag; 10033 } else { 10034 ser_info[ser_idx].ser_flags &= ~flag; 10035 } 10036 } 10037 ser_idx++; 10038 } 10039 } 10040 #endif /* BCM_TOMAHAWK2_SUPPORT */ 10041 10042 int 10043 soc_tomahawk_tcam_ser_init(int unit) 10044 { 10045 int alloc_size = 0; 10046 uint32 map[] = {0, 1, 2, 3}; 10047 10048 #ifdef BCM_TOMAHAWK2_SUPPORT 10049 if (SOC_IS_TOMAHAWK2(unit)) { 10050 /* First, make per-unit copy of the master TCAM list */ 10051 if (!soc_feature(unit, soc_feature_tcam_scan_engine)) { 10052 alloc_size = sizeof(_soc_th2_tcam_ser_info_template); 10053 10054 if (NULL == _soc_th_tcam_ser_info[unit]) { 10055 if ((_soc_th_tcam_ser_info[unit] = 10056 sal_alloc(alloc_size, "th tcam list")) == NULL) { 10057 return SOC_E_MEMORY; 10058 } 10059 } 10060 10061 /* Make a fresh copy of the TCAM template info */ 10062 sal_memcpy(_soc_th_tcam_ser_info[unit], 10063 &(_soc_th2_tcam_ser_info_template), 10064 alloc_size); 10065 } else { 10066 alloc_size = sizeof(_soc_th2_b0_tcam_ser_info_template); 10067 10068 if (NULL == _soc_th_tcam_ser_info[unit]) { 10069 if ((_soc_th_tcam_ser_info[unit] = 10070 sal_alloc(alloc_size, "th tcam list")) == NULL) { 10071 return SOC_E_MEMORY; 10072 } 10073 } 10074 10075 /* Make a fresh copy of the TCAM template info */ 10076 sal_memcpy(_soc_th_tcam_ser_info[unit], 10077 &(_soc_th2_b0_tcam_ser_info_template), 10078 alloc_size); 10079 } 10080 10081 if (soc_feature(unit, soc_feature_field_stage_half_slice) || 10082 soc_feature(unit, soc_feature_field_stage_quarter_slice)) { 10083 _soc_th2_ser_info_flag_update(_soc_th_tcam_ser_info[unit], IFP_TCAMm, 10084 _SOC_SER_FLAG_NO_DMA, TRUE); 10085 _soc_th2_ser_info_flag_update(_soc_th_tcam_ser_info[unit], IFP_TCAM_WIDEm, 10086 _SOC_SER_FLAG_NO_DMA, TRUE); 10087 } 10088 } else 10089 #endif 10090 10091 { 10092 /* First, make per-unit copy of the master TCAM list */ 10093 alloc_size = sizeof(_soc_th_tcam_ser_info_template); 10094 10095 if (NULL == _soc_th_tcam_ser_info[unit]) { 10096 if ((_soc_th_tcam_ser_info[unit] = 10097 sal_alloc(alloc_size, "th tcam list")) == NULL) { 10098 return SOC_E_MEMORY; 10099 } 10100 } 10101 10102 /* Make a fresh copy of the TCAM template info */ 10103 sal_memcpy(_soc_th_tcam_ser_info[unit], 10104 &(_soc_th_tcam_ser_info_template), 10105 alloc_size); 10106 } 10107 10108 SOC_IF_ERROR_RETURN(soc_generic_ser_at_map_init(unit, map, COUNTOF(map))); 10109 return soc_generic_ser_init(unit, _soc_th_tcam_ser_info[unit]); 10110 } 10111 10112 void 10113 soc_tomahawk_ser_fail(int unit) 10114 { 10115 soc_generic_ser_process_error(unit, _soc_th_tcam_ser_info[unit], 10116 _SOC_PARITY_TYPE_SER); 10117 } 10118 10119 int 10120 soc_tomahawk_mem_ser_control(int unit, soc_mem_t mem, int copyno, 10121 int enable) 10122 { 10123 if (enable) { 10124 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, TOP_SOFT_RESET_REGr, 10125 REG_PORT_ANY, TOP_MMU_RST_Lf, 0)); 10126 sal_usleep(1000); 10127 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, TOP_SOFT_RESET_REGr, 10128 REG_PORT_ANY, TOP_MMU_RST_Lf, 1)); 10129 sal_usleep(1000); 10130 #ifdef BCM_TOMAHAWK2_SUPPORT 10131 if (SOC_IS_TOMAHAWK2(unit)) { 10132 SOC_IF_ERROR_RETURN(soc_tomahawk2_clear_mmu_memory(unit)); 10133 } else 10134 #endif 10135 { 10136 SOC_IF_ERROR_RETURN(soc_tomahawk_clear_mmu_memory(unit)); 10137 } 10138 } 10139 10140 if (enable) { 10141 if (soc_property_get(unit, spn_PARITY_ENABLE, FALSE)) { 10142 SOC_IF_ERROR_RETURN(soc_tomahawk_ser_enable_all(unit, enable)); 10143 } 10144 } else { 10145 SOC_IF_ERROR_RETURN(soc_tomahawk_ser_enable_all(unit, enable)); 10146 } 10147 10148 if (enable) { 10149 uint32 rval; 10150 /* Initialize MMU memory */ 10151 SOC_IF_ERROR_RETURN(WRITE_MMU_GCFG_MISCCONFIGr(unit, 0)); 10152 rval = 0; 10153 soc_reg_field_set(unit, MMU_GCFG_MISCCONFIGr, &rval, INIT_MEMf, 1); 10154 SOC_IF_ERROR_RETURN(WRITE_MMU_GCFG_MISCCONFIGr(unit, rval)); 10155 SOC_IF_ERROR_RETURN(WRITE_MMU_GCFG_MISCCONFIGr(unit, 0)); 10156 } 10157 return SOC_E_NONE; 10158 } 10159 10160 void 10161 soc_tomahawk_ser_register(int unit) 10162 { 10163 #ifdef INCLUDE_MEM_SCAN 10164 soc_mem_scan_ser_list_register(unit, TRUE, 10165 _soc_th_tcam_ser_info[unit]); 10166 #endif 10167 memset(&_th_ser_functions, 0, sizeof(soc_ser_functions_t)); 10168 _th_ser_functions._soc_ser_fail_f = &soc_tomahawk_ser_fail; 10169 _th_ser_functions._soc_ser_parity_error_cmicm_intr_f = 10170 &soc_tomahawk_ser_error; 10171 #if defined(BCM_TOMAHAWK3_SUPPORT) 10172 _th_ser_functions._soc_ser_parity_error_cmicx_intr_f = 10173 &soc_tomahawk_ser_error; 10174 #endif 10175 soc_ser_function_register(unit, &_th_ser_functions); 10176 } 10177 10178 int 10179 soc_tomahawk_mem_sram_info_get(int unit, soc_mem_t mem, int index, 10180 _soc_ser_sram_info_t *sram_info) 10181 { 10182 int i, base, base_index, offset, base_bucket, bkt_offset; 10183 int entries_per_ram = 0, entries_per_bank, contiguous = 0; 10184 10185 switch (mem) { 10186 case L2_ENTRY_ONLY_ECCm: 10187 #ifdef BCM_TOMAHAWK3_SUPPORT 10188 case L2_ENTRY_ECCm: 10189 #endif 10190 if (index < SOC_TH_NUM_ENTRIES_L2_BANK) { 10191 /* dedicated L2 entries - hash table */ 10192 sram_info->ram_count = 1; 10193 entries_per_ram = SOC_TH_NUM_ENTRIES_L2_BANK; 10194 base = index; 10195 } else { 10196 /* hash_xor mems, stride 8K */ 10197 /* 10198 * sram_info->disable_reg = L2_ENTRY_PARITY_CONTROLr; 10199 * sram_info->disable_field = DISABLE_SBUS_MEMWR_PARITY_CHECKf; 10200 */ 10201 sram_info->force_reg = ISS_MEMORY_CONTROL_84r; 10202 sram_info->force_field = FORCE_XOR_GENERATIONf; 10203 sram_info->disable_xor_write_field = DEBUG_DISABLE_XOR_WRITEf; 10204 #ifdef BCM_TOMAHAWK2_SUPPORT 10205 if (SOC_IS_TOMAHAWK2(unit)) { 10206 sram_info->ram_count = SOC_TH2_NUM_EL_SHARED; 10207 } else 10208 #endif 10209 { 10210 sram_info->ram_count = SOC_TH_NUM_EL_SHARED; 10211 } 10212 /* #indexes to be corrected */ 10213 #ifdef BCM_TOMAHAWK3_SUPPORT 10214 if (SOC_IS_TOMAHAWK3(unit)) { 10215 entries_per_ram = SOC_TH3_NUM_ENTRIES_XOR_BANK; 10216 } else 10217 #endif 10218 { 10219 entries_per_ram = SOC_TH_NUM_ENTRIES_XOR_BANK; 10220 } 10221 /* #entries / xor_bank in a shared bank */ 10222 entries_per_bank = entries_per_ram * sram_info->ram_count; 10223 /* #entries / uft bank */ 10224 base_index = index - SOC_TH_NUM_ENTRIES_L2_BANK; 10225 /* index in uft space */ 10226 base = (base_index/entries_per_bank)*entries_per_bank; 10227 /* base addr of uft bank */ 10228 offset = base_index % entries_per_ram; 10229 /* 1st entry within uft bank */ 10230 base += SOC_TH_NUM_ENTRIES_L2_BANK + offset; 10231 /* 1st index for correction */ 10232 } 10233 break; 10234 case L3_ENTRY_ONLY_ECCm: 10235 #ifdef BCM_TOMAHAWK3_SUPPORT 10236 case L3_ENTRY_ECCm: 10237 #endif 10238 if (index < SOC_TH_NUM_ENTRIES_L3_BANK(unit)) { 10239 /* dedicated L3 entries - hash table */ 10240 sram_info->ram_count = 1; 10241 entries_per_ram = SOC_TH_NUM_ENTRIES_L3_BANK(unit); 10242 base = index; 10243 } else { 10244 /* hash_xor mems, stride 8K */ 10245 /* 10246 * sram_info->disable_reg = L3_ENTRY_PARITY_CONTROLr; 10247 * sram_info->disable_field = DISABLE_SBUS_MEMWR_PARITY_CHECKf; 10248 */ 10249 sram_info->force_reg = ISS_MEMORY_CONTROL_84r; 10250 sram_info->force_field = FORCE_XOR_GENERATIONf; 10251 sram_info->disable_xor_write_field = DEBUG_DISABLE_XOR_WRITEf; 10252 #ifdef BCM_TOMAHAWK2_SUPPORT 10253 if (SOC_IS_TOMAHAWK2(unit)) { 10254 sram_info->ram_count = SOC_TH2_NUM_EL_SHARED; 10255 } else 10256 #endif 10257 { 10258 sram_info->ram_count = SOC_TH_NUM_EL_SHARED; 10259 } 10260 /* #indexes to be corrected */ 10261 #ifdef BCM_TOMAHAWK3_SUPPORT 10262 if (SOC_IS_TOMAHAWK3(unit)) { 10263 entries_per_ram = SOC_TH3_NUM_ENTRIES_XOR_BANK; 10264 } else 10265 #endif 10266 { 10267 entries_per_ram = SOC_TH_NUM_ENTRIES_XOR_BANK; 10268 } 10269 /* #entries / xor_bank in a shared bank */ 10270 entries_per_bank = entries_per_ram * sram_info->ram_count; 10271 /* #entries / uft bank */ 10272 base_index = index - SOC_TH_NUM_ENTRIES_L3_BANK(unit); 10273 /* index in uft space */ 10274 base = (base_index/entries_per_bank)*entries_per_bank; 10275 /* base addr of uft bank */ 10276 offset = base_index % entries_per_ram; 10277 /* 1st entry within uft bank */ 10278 base += SOC_TH_NUM_ENTRIES_L3_BANK(unit) + offset; 10279 /* 1st index for correction */ 10280 } 10281 break; 10282 case FPEM_ECCm: 10283 #ifdef BCM_TOMAHAWK3_SUPPORT 10284 case EXACT_MATCH_ECCm: 10285 #endif 10286 /* hash_xor mems, stride 8K */ 10287 /* 10288 * sram_info->disable_reg = FPEM_CONTROLr; 10289 * sram_info->disable_field = DISABLE_SBUS_MEMWR_PARITY_CHECKf; 10290 */ 10291 sram_info->force_reg = ISS_MEMORY_CONTROL_84r; 10292 sram_info->force_field = FORCE_XOR_GENERATIONf; 10293 sram_info->disable_xor_write_field = DEBUG_DISABLE_XOR_WRITEf; 10294 #ifdef BCM_TOMAHAWK2_SUPPORT 10295 if (SOC_IS_TOMAHAWK2(unit)) { 10296 sram_info->ram_count = SOC_TH2_NUM_EL_SHARED; 10297 } else 10298 #endif 10299 { 10300 sram_info->ram_count = SOC_TH_NUM_EL_SHARED; 10301 } 10302 /* #indexes to be corrected */ 10303 #ifdef BCM_TOMAHAWK3_SUPPORT 10304 if (SOC_IS_TOMAHAWK3(unit)) { 10305 entries_per_ram = SOC_TH3_NUM_ENTRIES_XOR_BANK; 10306 } else 10307 #endif 10308 { 10309 entries_per_ram = SOC_TH_NUM_ENTRIES_XOR_BANK; 10310 } 10311 /* #entries / xor_bank in a shared bank */ 10312 entries_per_bank = entries_per_ram * sram_info->ram_count; 10313 /* #entries / uft bank */ 10314 base_index = index; 10315 /* index - (SOC_TH_NUM_ENTRIES_FPEM_BANK=0) */ 10316 /* index in uft space */ 10317 base = (base_index/entries_per_bank)*entries_per_bank; 10318 /* base addr of uft bank */ 10319 offset = base_index % entries_per_ram; 10320 /* 1st entry within uft bank */ 10321 base += offset; 10322 /* base += (SOC_TH_NUM_ENTRIES_FPEM_BANK=0) + offset; */ 10323 /* 1st index for correction */ 10324 break; 10325 case L3_DEFIP_ALPM_ECCm: 10326 if (!soc_tomahawk_alpm_mode_get(unit)) { 10327 return SOC_E_PARAM; 10328 } 10329 /* 10330 * sram_info->disable_reg = ILPM_SER_CONTROLr; 10331 * sram_info->disable_field = DISABLE_SBUS_MEMWR_PARITY_CHECKf; 10332 */ 10333 sram_info->force_reg = ISS_MEMORY_CONTROL_84r; 10334 sram_info->force_field = FORCE_XOR_GENERATIONf; 10335 sram_info->disable_xor_write_field = DEBUG_DISABLE_XOR_WRITEf; 10336 #ifdef BCM_TOMAHAWK2_SUPPORT 10337 if (SOC_IS_TOMAHAWK2(unit)) { 10338 sram_info->ram_count = SOC_TH2_NUM_EL_SHARED; 10339 } else 10340 #endif 10341 { 10342 sram_info->ram_count = SOC_TH_NUM_EL_SHARED; 10343 } 10344 10345 if (soc_th_get_alpm_banks(unit) == 2) { 10346 base = index & 0x1; /* 2 uft_bank mode */ 10347 base_bucket = ((index >> 1) & SOC_TH_ALPM_BKT_MASK(unit)); 10348 LOG_VERBOSE(BSL_LS_SOC_SER, 10349 (BSL_META_U(unit, 10350 "reported bucket: 0x%08x, uft_bank:%d\n"), 10351 base_bucket, base)); 10352 base_bucket = base_bucket % SOC_TH_ALPM_BKT_OFFFSET; 10353 LOG_VERBOSE(BSL_LS_SOC_SER, 10354 (BSL_META_U(unit, 10355 "base bucket: 0x%08x\n"), 10356 base_bucket)); 10357 for (i = 0; i < sram_info->ram_count; i++) { 10358 sram_info->view[i] = mem; 10359 sram_info->index_count[i] = 1; 10360 bkt_offset = base_bucket + SOC_TH_ALPM_BKT_OFFFSET*i; 10361 sram_info->mem_indexes[i][0] = 10362 (index & SOC_TH_ALPM_MODE1_BKT_MASK) | 10363 (bkt_offset << 1) | base; 10364 } 10365 } else { 10366 base = index & 0x3; /* 4 uft_bank mode */ 10367 base_bucket = ((index >> 2) & SOC_TH_ALPM_BKT_MASK(unit)); 10368 LOG_VERBOSE(BSL_LS_SOC_SER, 10369 (BSL_META_U(unit, 10370 "reported bucket: 0x%08x, uft_bank:%d\n"), 10371 base_bucket, base)); 10372 base_bucket = base_bucket % SOC_TH_ALPM_BKT_OFFFSET; 10373 LOG_VERBOSE(BSL_LS_SOC_SER, 10374 (BSL_META_U(unit, 10375 "base bucket: 0x%08x\n"), 10376 base_bucket)); 10377 for (i = 0; i < sram_info->ram_count; i++) { 10378 sram_info->view[i] = mem; 10379 sram_info->index_count[i] = 1; 10380 bkt_offset = base_bucket + SOC_TH_ALPM_BKT_OFFFSET*i; 10381 sram_info->mem_indexes[i][0] = 10382 (index & SOC_TH_ALPM_MODE0_BKT_MASK) | 10383 (bkt_offset << 2) | base; 10384 } 10385 } 10386 return SOC_E_NONE; 10387 #ifdef BCM_TOMAHAWK3_SUPPORT 10388 case L3_DEFIP_ALPM_LEVEL3_ECCm: 10389 if (SOC_IS_TOMAHAWK3(unit)) { 10390 if (!soc_tomahawk3_alpm_mode_get(unit)) { 10391 return SOC_E_PARAM; 10392 } 10393 sram_info->force_mem = UFT_SHARED_BANKS_CONTROLm; 10394 sram_info->force_field = FORCE_XOR_GENf; 10395 sram_info->disable_xor_write_field = DISABLE_XOR_WRITEf; 10396 sram_info->ram_count = SOC_TH_NUM_EL_SHARED; 10397 10398 base_bucket = ((index >> 2) & SOC_TH3_ALPM_BKT_MASK(unit)); 10399 LOG_VERBOSE(BSL_LS_SOC_SER, 10400 (BSL_META_U(unit, 10401 "reported bucket: 0x%08x\n"), 10402 base_bucket)); 10403 base_bucket = base_bucket % SOC_TH3_ALPM_BKT_OFFFSET; 10404 LOG_VERBOSE(BSL_LS_SOC_SER, 10405 (BSL_META_U(unit, 10406 "base bucket: 0x%08x\n"), 10407 base_bucket)); 10408 for (i = 0; i < SOC_TH3_NUM_EL_SHARED; i++) { 10409 sram_info->view[i] = mem; 10410 sram_info->index_count[i] = 1; 10411 bkt_offset = base_bucket + SOC_TH3_ALPM_BKT_OFFFSET*i; 10412 sram_info->mem_indexes[i][0] = 10413 (index & SOC_TH3_ALPM_MODE_BKT_MASK) | (bkt_offset << 2); 10414 } 10415 } 10416 return SOC_E_NONE; 10417 #endif 10418 case FPEM_LPm: 10419 sram_info->disable_reg = FPEM_CONTROLr; 10420 sram_info->disable_field = DISABLE_SBUS_MEMWR_PARITY_CHECKf; 10421 /* sram_info->force_reg = ISS_MEMORY_CONTROL_84r; */ 10422 /* sram_info->force_field = FORCE_XOR_GENERATIONf; */ 10423 10424 #ifdef BCM_TOMAHAWK2_SUPPORT 10425 if (SOC_IS_TOMAHAWK2(unit)) { 10426 sram_info->ram_count = SOC_TH2_NUM_EL_SHARED; 10427 } else 10428 #endif 10429 { 10430 sram_info->ram_count = SOC_TH_NUM_EL_SHARED; 10431 } 10432 /* #indexes to be corrected */ 10433 entries_per_ram = SOC_TH_LP_ENTRIES_IN_XOR_BANK;; 10434 /* #lp_entries / lp_xor_bank of uft bank */ 10435 base = index % entries_per_ram; 10436 /* 1st lp_entry within uft bank */ 10437 entries_per_bank = SOC_TH_NUM_ENTRIES_XOR_BANK * sram_info->ram_count; 10438 /* #phy_entries / uft bank */ 10439 #ifdef BCM_TOMAHAWK2_SUPPORT 10440 if (SOC_IS_TOMAHAWK2(unit)) { 10441 offset = entries_per_bank * (index / SOC_TH2_LP_ENTRIES_IN_UFT_BANK); 10442 } else 10443 #endif 10444 { 10445 offset = entries_per_bank * (index / SOC_TH_LP_ENTRIES_IN_UFT_BANK); 10446 } 10447 /* of 1st_phy_entry in uft space */ 10448 for (i = 0; i < sram_info->ram_count; i++) { 10449 sram_info->mem_indexes[i][0] = offset; 10450 if (i < 2) { 10451 sram_info->view[i] = EXACT_MATCH_2m; 10452 sram_info->mem_indexes[i][0] += 8*(base + i*entries_per_ram); 10453 /* indexes 0 to 4K-1 correspond to em2 type entries */ 10454 /* each index in FPEM_LP corresponds to 4 consecutive em2 10455 * entries */ 10456 } else if (i == 2) { 10457 sram_info->view[i] = EXACT_MATCH_4m; 10458 sram_info->mem_indexes[i][0] += 16*base; 10459 /* indexes 4K to 6K-1 correspond to em4 type entries */ 10460 /* each index in FPEM_LP corresponds to 4 consecutive em4 10461 * entries */ 10462 } else { 10463 sram_info->view[i] = mem; 10464 offset = SOC_TH_LP_ENTRIES_IN_UFT_BANK * 10465 (index / SOC_TH_LP_ENTRIES_IN_UFT_BANK); 10466 /* of 1st_lp_entry in uft_space */ 10467 offset += base; 10468 /* of 1st_lp_entry to be corrected */ 10469 sram_info->mem_indexes[i][0] = offset + i*entries_per_ram; 10470 /* of 4th_lp_entry to be corrected */ 10471 } 10472 } 10473 return SOC_E_NONE; 10474 case L2_ENTRY_LPm: 10475 case L3_ENTRY_LPm: 10476 case VLAN_XLATE_LPm: 10477 case EGR_VLAN_XLATE_LPm: 10478 sram_info->view[0] = mem; 10479 sram_info->index_count[0] = 1; 10480 sram_info->ram_count = 1; 10481 entries_per_ram = 0; /* x */ 10482 base = index; /* index of 1st lp_entry */ 10483 break; 10484 case L2_ENTRY_ISS_LPm: 10485 case L3_ENTRY_ISS_LPm: 10486 /* hash_xor mems, stride 2K */ 10487 #ifdef BCM_TOMAHAWK2_SUPPORT 10488 if (SOC_IS_TOMAHAWK2(unit)) { 10489 sram_info->ram_count = SOC_TH2_NUM_EL_SHARED; 10490 } else 10491 #endif 10492 { 10493 sram_info->ram_count = SOC_TH_NUM_EL_SHARED; 10494 } 10495 10496 for (i=0; i < sram_info->ram_count; i++) { 10497 sram_info->view[i] = mem; 10498 sram_info->index_count[i] = 1; 10499 } 10500 /* #indexes to be corrected */ 10501 entries_per_ram = SOC_TH_LP_ENTRIES_IN_XOR_BANK; 10502 #ifdef BCM_TOMAHAWK2_SUPPORT 10503 if (SOC_IS_TOMAHAWK2(unit)) { 10504 entries_per_bank = SOC_TH2_LP_ENTRIES_IN_UFT_BANK; 10505 } else 10506 #endif 10507 { 10508 entries_per_bank = SOC_TH_LP_ENTRIES_IN_UFT_BANK; 10509 } 10510 base_index = index; /* index of lp_entry */ 10511 base = (base_index/entries_per_bank)*entries_per_bank; 10512 /* lp_entry0 in uft bank */ 10513 offset = base_index % entries_per_ram; 10514 /* lp_entry in 1st xor_bank */ 10515 base += offset; /* index of 1st lp_entry */ 10516 break; 10517 case VLAN_XLATE_ECCm: 10518 case VLAN_MACm: 10519 contiguous = 1; 10520 /* 10521 * sram_info->disable_reg = VLAN_XLATE_DBGCTRL_0r; 10522 * sram_info->disable_field = DISABLE_SBUS_MEMWR_PARITY_CHECKf; 10523 */ 10524 sram_info->force_reg = VLAN_XLATE_DBGCTRL_0r; 10525 sram_info->force_field = FORCE_XOR_GENf; 10526 sram_info->disable_xor_write_field = DEBUG_DISABLE_XOR_WRITEf; 10527 sram_info->ram_count = SOC_TH_NUM_EL_VLAN_XLATE; 10528 base = (index/4) * 4; 10529 break; 10530 case EGR_VLAN_XLATE_ECCm: 10531 contiguous = 1; 10532 /* 10533 * sram_info->disable_reg = EGR_VLAN_XLATE_CONTROLr; 10534 * sram_info->disable_field = DISABLE_SBUS_MEMWR_PARITY_CHECKf; 10535 */ 10536 sram_info->force_reg = EGR_VLAN_XLATE_CONTROLr; 10537 sram_info->force_field = FORCE_XOR_GENf; 10538 sram_info->disable_xor_write_field = DEBUG_DISABLE_XOR_WRITEf; 10539 sram_info->ram_count = SOC_TH_NUM_EL_EGR_VLAN_XLATE; 10540 base = (index/4) * 4; 10541 break; 10542 case ING_L3_NEXT_HOPm: 10543 #ifdef BCM_TOMAHAWK2_SUPPORT 10544 if (SOC_IS_TOMAHAWK2(unit)) { 10545 sram_info->ram_count = SOC_TH2_NUM_EL_ING_L3_NEXT_HOP; 10546 } else 10547 #endif 10548 { 10549 sram_info->ram_count = SOC_TH_NUM_EL_ING_L3_NEXT_HOP; 10550 } 10551 sram_info->force_reg = RSEL2_RAM_DBGCTRL5r; 10552 sram_info->force_field = FORCE_XOR_GEN_NHOPf; 10553 sram_info->disable_xor_write_field = DEBUG_DISABLE_XOR_WRITE_NHOPf; 10554 entries_per_ram = SOC_TH_RAM_OFFSET_ING_L3_NEXT_HOP; 10555 base = index % entries_per_ram; 10556 break; 10557 default: return SOC_E_PARAM; 10558 } 10559 sram_info->mem_indexes[0][0] = base; 10560 if (contiguous) { 10561 for (i=1; i < sram_info->ram_count; i++) { 10562 sram_info->mem_indexes[i][0] = sram_info->mem_indexes[i-1][0] + 1; 10563 } 10564 } else { 10565 for (i=1; i < sram_info->ram_count; i++) { 10566 sram_info->mem_indexes[i][0] = sram_info->mem_indexes[i-1][0] + 10567 entries_per_ram; 10568 } 10569 } 10570 return SOC_E_NONE; 10571 } 10572 10573 int 10574 soc_th_ifp_slice_mode_hw_get(int unit, int pipe, int slice_num, int *slice_type, 10575 int *slice_enabled) 10576 { 10577 soc_reg_t ifp_cfg_r; 10578 uint32 ifp_cfg_rval = 0; 10579 static soc_reg_t ifp_cfg_r_list[] = { 10580 IFP_CONFIG_PIPE0r, 10581 IFP_CONFIG_PIPE1r, 10582 IFP_CONFIG_PIPE2r, 10583 IFP_CONFIG_PIPE3r, 10584 IFP_CONFIG_PIPE4r, 10585 IFP_CONFIG_PIPE5r, 10586 IFP_CONFIG_PIPE6r, 10587 IFP_CONFIG_PIPE7r}; 10588 int rv = 0; 10589 10590 rv = soc_th_ifp_slice_mode_get(unit, pipe, slice_num, 10591 slice_type, slice_enabled); 10592 if (rv != SOC_E_INIT) { 10593 return rv; 10594 } 10595 10596 if ((slice_type == NULL) || (slice_enabled == NULL) || 10597 (pipe >= NUM_PIPE(unit))) { 10598 return SOC_E_PARAM; 10599 } 10600 10601 if (pipe < 0) { /* global mode */ 10602 ifp_cfg_r = IFP_CONFIGr; 10603 } else { 10604 ifp_cfg_r = ifp_cfg_r_list[pipe]; 10605 } 10606 SOC_IF_ERROR_RETURN( 10607 soc_reg32_get(unit, ifp_cfg_r, REG_PORT_ANY, slice_num, &ifp_cfg_rval)); 10608 10609 if (soc_feature(unit, soc_feature_ifp_no_narrow_mode_support)) { 10610 *slice_type = _SOC_TH_IFP_SLICE_MODE_WIDE; 10611 } else { 10612 *slice_type = soc_reg_field_get(unit, ifp_cfg_r, ifp_cfg_rval, 10613 IFP_SLICE_MODEf); 10614 } 10615 10616 *slice_enabled = soc_reg_field_get(unit, ifp_cfg_r, ifp_cfg_rval, 10617 IFP_SLICE_LOOKUP_ENABLEf); 10618 return SOC_E_NONE; 10619 } 10620 10621 /* Returns FALSE if mem is not one of the dual_mode mems tracked by SER engine 10622 * Else returns TRUE, base_mem, pipe 10623 * Note: pipe will be -1 when mem == base_mem 10624 * pipe will be >=0 when mem != base_mem 10625 */ 10626 int soc_th_mem_is_dual_mode(int unit, soc_mem_t mem, soc_mem_t *base_mem, int *pipe) 10627 { 10628 int i, p; 10629 int rv_dual_mode = FALSE; 10630 static const soc_mem_t mem_list[] = { 10631 SRC_COMPRESSIONm, 10632 DST_COMPRESSIONm, 10633 FP_UDF_TCAMm, 10634 VFP_TCAMm, 10635 IFP_LOGICAL_TABLE_SELECTm, 10636 EXACT_MATCH_LOGICAL_TABLE_SELECTm, 10637 EFP_TCAMm, 10638 IFP_TCAMm, 10639 IFP_TCAM_WIDEm, 10640 INVALIDm}; 10641 if (!SOC_MEM_IS_VALID(unit, mem)) { 10642 return FALSE; 10643 } 10644 for (i = 0; mem_list[i] != INVALIDm; i++) { 10645 /* test for base_view */ 10646 p = -1; 10647 if (mem == mem_list[i]) { 10648 rv_dual_mode = TRUE; 10649 break; 10650 } 10651 /* test for base_PIPE0,1,2,3 views */ 10652 if (SOC_MEM_UNIQUE_ACC(unit, mem_list[i]) != NULL) { 10653 for (p = 0; p < NUM_PIPE(unit); p++) { 10654 if (mem == SOC_MEM_UNIQUE_ACC(unit, mem_list[i])[p]) { 10655 rv_dual_mode = TRUE; 10656 break; /* from p loop */ 10657 } 10658 } 10659 if (rv_dual_mode) { 10660 break; /* from i loop */ 10661 } 10662 } 10663 } 10664 if (FALSE != rv_dual_mode) { 10665 if (NULL != pipe) { 10666 *pipe = p; 10667 } 10668 if (NULL != base_mem) { 10669 *base_mem = mem_list[i]; 10670 } 10671 } 10672 return rv_dual_mode; 10673 } 10674 10675 int 10676 soc_th_mem_index_invalid(int unit, soc_mem_t mem, int index, uint8 dual_mode, 10677 soc_mem_t in_base_mem, int in_pipe) 10678 { 10679 int slice_num = 0, slice_type, rv; 10680 int cfg_slice_enabled = 0; 10681 int cfg_slice_type = 0; 10682 int mem_mode = _SOC_SER_MEM_MODE_GLOBAL; 10683 soc_mem_t base_mem = INVALIDm; 10684 int pipe = -1, mode_ok = 0; 10685 int8 dual_mode_mem; 10686 10687 if (0xFF == dual_mode) { 10688 dual_mode_mem = soc_th_mem_is_dual_mode(unit, mem, &base_mem, &pipe); 10689 } else { 10690 base_mem = in_base_mem; 10691 pipe = in_pipe; 10692 dual_mode_mem = dual_mode; 10693 } 10694 10695 if (dual_mode_mem) { 10696 if (!SOC_FAILURE(soc_th_check_hw_global_mode(unit, base_mem, 10697 &mem_mode))) { 10698 mode_ok = ((_SOC_SER_MEM_MODE_GLOBAL == mem_mode) && (pipe < 0)) || 10699 ((_SOC_SER_MEM_MODE_GLOBAL != mem_mode) && (pipe >= 0)); 10700 if (!mode_ok) { 10701 LOG_VERBOSE(BSL_LS_SOC_SER, (BSL_META_U(unit, 10702 "Denied access to mem %s, pipe %d, index %d in %s mode !!\n"), 10703 SOC_MEM_NAME(unit, mem), pipe, index, mem_mode? "UNIQUE" : "GLOBAL")); 10704 return TRUE; /* skip: dual mode, but !mode_ok */ 10705 } 10706 10707 if (base_mem != IFP_TCAMm && base_mem != IFP_TCAM_WIDEm) { 10708 return FALSE; /* allow: dual_mode && mode_ok */ 10709 } 10710 #if defined(BCM_TOMAHAWK3_SUPPORT) 10711 if (SOC_IS_TOMAHAWK3(unit)) { 10712 if ((index >= 0) && (index < 1536)) { 10713 slice_num = index/256; 10714 } else if ((index >= 1536) && (index < 3072)) { 10715 slice_num = ((index - 1536) / 512) + 5; 10716 } 10717 slice_type = _SOC_TH_IFP_SLICE_MODE_WIDE; 10718 10719 if ((slice_num < 0) || (slice_num >= 9)) { 10720 return TRUE; /* invalid - skip mem_acc */ 10721 } 10722 } else 10723 #endif 10724 { 10725 /* IFP_TCAMm or IFP_TCAM_WIDEm */ 10726 if (base_mem == IFP_TCAMm) { 10727 slice_num = index/512; slice_type = 0; 10728 } else { 10729 slice_num = index/256; slice_type = 1; 10730 } 10731 if ((slice_num < 0) || (slice_num >= 12)) { 10732 return TRUE; /* invalid - skip mem_acc */ 10733 } 10734 } 10735 10736 rv = soc_th_ifp_slice_mode_hw_get(unit, pipe, slice_num, 10737 &cfg_slice_type, &cfg_slice_enabled); 10738 if (SOC_FAILURE(rv)) { 10739 /* only case where this can happen: 10740 * When slice is in global mode and we pass 'pipe != -1' or 10741 * invalid input parameters. 10742 * For example, if we are trying to access location 5 in IFP_TCAM_WIDE_PIPE2, 10743 * but if slice_0 is part of IFP_TCAM then field module will return 10744 * SOC_E_CONFIG - to indicate that slice must be skipped. 10745 */ 10746 LOG_VERBOSE(BSL_LS_SOC_SER, (BSL_META_U(unit, 10747 "unit %d, slice_mode_get failed: mem %s, " 10748 "pipe: %d, index %d, slice_num %d rv %d!!\n"), 10749 unit, SOC_MEM_NAME(unit, mem), pipe, index, slice_num, rv)); 10750 return TRUE; /* invalid - skip mem_acc */ 10751 } else if (slice_type != cfg_slice_type) { 10752 LOG_VERBOSE(BSL_LS_SOC_SER, (BSL_META_U(unit, 10753 "Denied access to mem %s, pipe %d, index %d slice %d in %s slice_mode !!\n"), 10754 SOC_MEM_NAME(unit, mem), pipe, index, slice_num, cfg_slice_type? "WIDE" : "NARROW")); 10755 return TRUE; /* invalid - skip mem_acc */ 10756 } else { 10757 return FALSE; /* proceed with mem_acc */ 10758 } 10759 } else { 10760 LOG_ERROR(BSL_LS_SOC_SER, (BSL_META_U(unit, 10761 "Denied access to mem %s, pipe %d, index %d in %s mode !!\n"), 10762 SOC_MEM_NAME(unit, mem), pipe, index, "UNKNOWN_MODE")); 10763 return TRUE; /* skip: dual mode, but could not find mode */ 10764 } 10765 } 10766 return FALSE; /* allow: !dual_mode */ 10767 } 10768 10769 /* For use during WB. 10770 * Looks at SER_RANGE_ENABLEr and determines if mem is in global mode / unique 10771 * mode. 10772 * Works ONLY for mems listed in mem_list[] below. 10773 * Cannot use: soc_th_field_mem_mode_get during WB 10774 * Note: Bit positions are HARD-CODED to match with order of entries in 10775 _soc_generic_ser_info_t _soc_th_tcam_ser_info_template[] 10776 MUST change these values if we change above array !! 10777 */ 10778 int 10779 soc_th_check_hw_global_mode(int unit, soc_mem_t mem, int *mem_mode) 10780 { 10781 int i = 0; 10782 uint32 range_enable; 10783 static const struct { 10784 soc_mem_t mem; 10785 int bit_position; 10786 } mem_list[] = { 10787 {SRC_COMPRESSIONm, 10}, 10788 {DST_COMPRESSIONm, 12}, 10789 {FP_UDF_TCAMm, 14}, 10790 {VFP_TCAMm, 16}, 10791 {IFP_LOGICAL_TABLE_SELECTm, 18}, 10792 {EXACT_MATCH_LOGICAL_TABLE_SELECTm, 20}, 10793 {EFP_TCAMm, 22}, 10794 {IFP_TCAMm, 24}, 10795 {IFP_TCAM_WIDEm, 26}, 10796 {INVALIDm, 0 } 10797 }; 10798 if (!SOC_MEM_IS_VALID(unit,mem)) { 10799 return SOC_E_PARAM; 10800 } 10801 if (NULL == mem_mode) { 10802 return SOC_E_PARAM; 10803 } 10804 *mem_mode = _SOC_SER_MEM_MODE_GLOBAL; 10805 for (i = 0; mem_list[i].mem != INVALIDm; i++) { 10806 if (mem_list[i].mem == mem) { 10807 SOC_IF_ERROR_RETURN( 10808 READ_SER_RANGE_ENABLEr(unit, &range_enable)); 10809 if ((range_enable >> mem_list[i].bit_position) & 0x1) { 10810 *mem_mode = _SOC_SER_MEM_MODE_PIPE_UNIQUE; 10811 } 10812 return SOC_E_NONE; 10813 } 10814 } 10815 return SOC_E_NONE; 10816 } 10817 10818 int 10819 soc_th_ser_mem_mode_get(int unit, soc_mem_t mem, int *mem_mode) 10820 { 10821 int rv = SOC_E_NONE; 10822 10823 /* first query field module */ 10824 rv = soc_th_field_mem_mode_get(unit, mem, mem_mode); 10825 10826 switch (rv) { 10827 case SOC_E_INIT: /* BCM_E_INIT: field module is de-initialized */ 10828 LOG_VERBOSE(BSL_LS_SOC_SER, 10829 (BSL_META_U(unit, 10830 "unit %d, field_mem_mode_get failed: mem %s " 10831 "Will consult soc_th_check_hw_global_mode !!\n"), 10832 unit, SOC_MEM_NAME(unit, mem))); 10833 switch (mem) { 10834 case VFP_TCAMm: 10835 case VFP_POLICY_TABLEm: 10836 rv = soc_th_check_hw_global_mode(unit, 10837 VFP_TCAMm, 10838 mem_mode); 10839 break; 10840 10841 case EFP_TCAMm: 10842 case EFP_POLICY_TABLEm: 10843 case EFP_COUNTER_TABLEm: 10844 case EFP_METER_TABLEm: 10845 rv = soc_th_check_hw_global_mode(unit, 10846 EFP_TCAMm, 10847 mem_mode); 10848 break; 10849 10850 case IFP_LOGICAL_TABLE_SELECTm: 10851 case IFP_LOGICAL_TABLE_SELECT_TCAM_ONLYm: 10852 case IFP_TCAMm: 10853 case IFP_LOGICAL_TABLE_SELECT_DATA_ONLYm: 10854 case IFP_LOGICAL_TABLE_ACTION_PRIORITYm: 10855 case IFP_KEY_GEN_PROGRAM_PROFILEm: 10856 case IFP_KEY_GEN_PROGRAM_PROFILE2m: 10857 case IFP_POLICY_TABLEm: 10858 case IFP_METER_TABLEm: 10859 rv = soc_th_check_hw_global_mode(unit, 10860 IFP_LOGICAL_TABLE_SELECTm, /* or IFP_TCAMm */ 10861 mem_mode); 10862 break; 10863 10864 case FP_UDF_OFFSETm: 10865 case FP_UDF_TCAMm: 10866 rv = soc_th_check_hw_global_mode(unit, 10867 FP_UDF_TCAMm, 10868 mem_mode); 10869 break; 10870 10871 case EXACT_MATCH_LOGICAL_TABLE_SELECTm: 10872 case EXACT_MATCH_LOGICAL_TABLE_SELECT_TCAM_ONLYm: 10873 case EXACT_MATCH_LOGICAL_TABLE_SELECT_DATA_ONLYm: 10874 case EXACT_MATCH_KEY_GEN_PROGRAM_PROFILEm: 10875 case EXACT_MATCH_ACTION_PROFILEm: 10876 case EXACT_MATCH_QOS_ACTIONS_PROFILEm: 10877 case EXACT_MATCH_DEFAULT_POLICYm: 10878 case EXACT_MATCH_KEY_GEN_MASKm: 10879 case EXACT_MATCH_2m: 10880 case EXACT_MATCH_4m: 10881 case EXACT_MATCH_2_ENTRY_ONLYm: 10882 case EXACT_MATCH_4_ENTRY_ONLYm: 10883 case FPEM_ECCm: 10884 rv = soc_th_check_hw_global_mode(unit, 10885 EXACT_MATCH_LOGICAL_TABLE_SELECTm, 10886 mem_mode); 10887 break; 10888 10889 case SRC_COMPRESSIONm: 10890 case SRC_COMPRESSION_TCAM_ONLYm: 10891 case SRC_COMPRESSION_DATA_ONLYm: 10892 /* stage = bcmFieldQualifyStageClass; */ 10893 /* stage_id = _BCM_FIELD_STAGE_CLASS */ 10894 rv = soc_th_check_hw_global_mode(unit, 10895 SRC_COMPRESSIONm, 10896 mem_mode); 10897 break; 10898 10899 case DST_COMPRESSIONm: 10900 case DST_COMPRESSION_TCAM_ONLYm: 10901 case DST_COMPRESSION_DATA_ONLYm: 10902 /* stage = bcmFieldQualifyStageClass; */ 10903 /* stage_id = _BCM_FIELD_STAGE_CLASS */ 10904 rv = soc_th_check_hw_global_mode(unit, 10905 DST_COMPRESSIONm, 10906 mem_mode); 10907 break; 10908 10909 case TTL_FNm: 10910 case TOS_FNm: 10911 case TCP_FNm: 10912 case IP_PROTO_MAPm: 10913 /* stage = bcmFieldQualifyStageClassExactMatch; */ 10914 /* stage_id = _BCM_FIELD_STAGE_CLASS */ 10915 rv = soc_th_check_hw_global_mode(unit, 10916 DST_COMPRESSIONm, 10917 mem_mode); 10918 break; 10919 10920 case IFP_TCAM_WIDEm: 10921 rv = soc_th_check_hw_global_mode(unit, 10922 IFP_TCAM_WIDEm, 10923 mem_mode); 10924 break; 10925 default: 10926 rv = SOC_E_UNAVAIL; 10927 break; 10928 } 10929 break; /*field module is de-initialized */ 10930 10931 default: /* field module response - may/may_not_be SOC_E_NONE */ 10932 break; 10933 } 10934 10935 return rv; 10936 } 10937 10938 STATIC int 10939 _soc_th_ifp_slice_mode_check(int unit, soc_mem_t mem, int slice, int *slice_skip) 10940 { 10941 10942 soc_reg_t reg; 10943 uint32 rval; 10944 int exp_slice_width_narrow, slice_width_narrow, slice_enabled; 10945 10946 if (NULL == slice_skip) { 10947 return SOC_E_PARAM; 10948 } 10949 *slice_skip = 0; 10950 switch (mem) { 10951 case IFP_TCAMm: 10952 exp_slice_width_narrow = _SOC_TH_IFP_SLICE_MODE_NARROW; 10953 reg = IFP_CONFIGr; 10954 break; 10955 case IFP_TCAM_PIPE0m: 10956 exp_slice_width_narrow = _SOC_TH_IFP_SLICE_MODE_NARROW; 10957 reg = IFP_CONFIG_PIPE0r; 10958 break; 10959 case IFP_TCAM_PIPE1m: 10960 exp_slice_width_narrow = _SOC_TH_IFP_SLICE_MODE_NARROW; 10961 reg = IFP_CONFIG_PIPE1r; 10962 break; 10963 case IFP_TCAM_PIPE2m: 10964 exp_slice_width_narrow = _SOC_TH_IFP_SLICE_MODE_NARROW; 10965 reg = IFP_CONFIG_PIPE2r; 10966 break; 10967 case IFP_TCAM_PIPE3m: 10968 exp_slice_width_narrow = _SOC_TH_IFP_SLICE_MODE_NARROW; 10969 reg = IFP_CONFIG_PIPE3r; 10970 break; 10971 case IFP_TCAM_PIPE4m: 10972 exp_slice_width_narrow = _SOC_TH_IFP_SLICE_MODE_NARROW; 10973 reg = IFP_CONFIG_PIPE4r; 10974 break; 10975 case IFP_TCAM_PIPE5m: 10976 exp_slice_width_narrow = _SOC_TH_IFP_SLICE_MODE_NARROW; 10977 reg = IFP_CONFIG_PIPE5r; 10978 break; 10979 case IFP_TCAM_PIPE6m: 10980 exp_slice_width_narrow = _SOC_TH_IFP_SLICE_MODE_NARROW; 10981 reg = IFP_CONFIG_PIPE6r; 10982 break; 10983 case IFP_TCAM_PIPE7m: 10984 exp_slice_width_narrow = _SOC_TH_IFP_SLICE_MODE_NARROW; 10985 reg = IFP_CONFIG_PIPE7r; 10986 break; 10987 case IFP_TCAM_WIDEm: 10988 exp_slice_width_narrow = _SOC_TH_IFP_SLICE_MODE_WIDE; 10989 reg = IFP_CONFIGr; 10990 break; 10991 case IFP_TCAM_WIDE_PIPE0m: 10992 exp_slice_width_narrow = _SOC_TH_IFP_SLICE_MODE_WIDE; 10993 reg = IFP_CONFIG_PIPE0r; 10994 break; 10995 case IFP_TCAM_WIDE_PIPE1m: 10996 exp_slice_width_narrow = _SOC_TH_IFP_SLICE_MODE_WIDE; 10997 reg = IFP_CONFIG_PIPE1r; 10998 break; 10999 case IFP_TCAM_WIDE_PIPE2m: 11000 exp_slice_width_narrow = _SOC_TH_IFP_SLICE_MODE_WIDE; 11001 reg = IFP_CONFIG_PIPE2r; 11002 break; 11003 case IFP_TCAM_WIDE_PIPE3m: 11004 exp_slice_width_narrow = _SOC_TH_IFP_SLICE_MODE_WIDE; 11005 reg = IFP_CONFIG_PIPE3r; 11006 break; 11007 default: 11008 return SOC_E_PARAM; 11009 } 11010 SOC_IF_ERROR_RETURN( 11011 soc_reg32_get(unit, reg, REG_PORT_ANY, slice, &rval)); 11012 11013 if (soc_feature(unit, soc_feature_ifp_no_narrow_mode_support)) { 11014 slice_width_narrow = _SOC_TH_IFP_SLICE_MODE_WIDE; 11015 exp_slice_width_narrow = _SOC_TH_IFP_SLICE_MODE_WIDE; 11016 } else { 11017 slice_width_narrow = soc_reg_field_get(unit, reg, rval, IFP_SLICE_MODEf); 11018 } 11019 11020 slice_enabled = soc_reg_field_get(unit, reg, rval, IFP_SLICE_ENABLEf); 11021 if (!slice_enabled || (exp_slice_width_narrow != slice_width_narrow)) { 11022 *slice_skip = 1; 11023 } 11024 LOG_VERBOSE(BSL_LS_SOC_SER, 11025 (BSL_META_U(unit, "_soc_th_ifp_slice_mode_check: For mem %s, read reg %s, slice_enabled = %0d, slice_width = %0d, slice_skip = %0d\n"), 11026 SOC_MEM_NAME(unit, mem), SOC_REG_NAME(unit, reg), slice_enabled, 11027 slice_width_narrow, *slice_skip)); 11028 return SOC_E_NONE; 11029 } 11030 11031 /* 11032 * This function creates an array of slice sizes and also returns 11033 * the slice_count per device 11034 */ 11035 int 11036 soc_th_ifp_tcam_slice_size_calculate(int unit, soc_mem_t mem, 11037 int *slice_count, 11038 int *slice_size_arr) 11039 { 11040 int slice_idx = 0; 11041 int rv = SOC_E_NONE; 11042 11043 if (NULL == slice_count) { 11044 return SOC_E_PARAM; 11045 } 11046 11047 if (NULL == slice_size_arr) { 11048 return SOC_E_PARAM; 11049 } 11050 11051 #ifdef BCM_TOMAHAWK3_SUPPORT 11052 if (SOC_IS_TOMAHAWK3(unit)) { 11053 *slice_count = 9; 11054 for (slice_idx = 0; slice_idx < *slice_count; slice_idx++) { 11055 slice_size_arr[slice_idx] = (slice_idx < 6) ? 256 : 512; 11056 } 11057 } else 11058 #endif 11059 { 11060 *slice_count = 12; 11061 switch (mem) { 11062 case IFP_TCAMm: 11063 case IFP_TCAM_PIPE0m: 11064 case IFP_TCAM_PIPE1m: 11065 case IFP_TCAM_PIPE2m: 11066 case IFP_TCAM_PIPE3m: 11067 case IFP_TCAM_PIPE4m: 11068 case IFP_TCAM_PIPE5m: 11069 case IFP_TCAM_PIPE6m: 11070 case IFP_TCAM_PIPE7m: 11071 for (slice_idx = 0; slice_idx < *slice_count; slice_idx++) { 11072 slice_size_arr[slice_idx] = 512; 11073 } 11074 break; 11075 case IFP_TCAM_WIDEm: 11076 case IFP_TCAM_WIDE_PIPE0m: 11077 case IFP_TCAM_WIDE_PIPE1m: 11078 case IFP_TCAM_WIDE_PIPE2m: 11079 case IFP_TCAM_WIDE_PIPE3m: 11080 for (slice_idx = 0; slice_idx < *slice_count; slice_idx++) { 11081 slice_size_arr[slice_idx] = 256; 11082 } 11083 break; 11084 default: 11085 rv = SOC_E_PARAM; 11086 } 11087 } 11088 return rv; 11089 } 11090 11091 /* 11092 * 0. Must not read IFP_TCAM_WIDEm for slices that are in 80b mode. 11093 * Must not read IFP_TCAMm for slices in 160b mode. 11094 * Must breakdown dma read into read of slices 11095 * 11096 * 1. Issues dma_read for each slice of mem and collects data into *table. 11097 * 11098 * 2. used for reloading sw_cache from hw_tables during WB. 11099 * This requires reading of IFP_CONFIGr to determine slice_mode. Thus 11100 * we cannot use soc_th_ifp_slice_mode_get() which will be eventually 11101 * replaced by field' module. 11102 * 11103 * 3. used for scrubbing IFP_TCAM, IFP_TCAM_WIDE views before CPU goes offline 11104 * We still cannot use standard soc_th_ifp_slice_mode_get() as defined earlier, 11105 * because exit_clean in appl/diag/shell.c first invokes _bcm_shutdown 11106 * (which de-inits field module) and then soc_shutdown (which calls this 11107 * function) 11108 */ 11109 int 11110 soc_th_ifp_tcam_dma_read(int unit, soc_mem_t mem, int blk, uint32 *table, 11111 int en_per_pipe_read, uint8 *vmap) 11112 { 11113 int slice, slice_skip = 0; 11114 int slice_start_addr, slice_end_addr, entry_dw; 11115 int rv = SOC_E_NONE; 11116 int slice_count = 0; 11117 int slice_size_arr[12] = { 0 }; 11118 11119 if (!SOC_MEM_IS_VALID(unit,mem)) { 11120 return SOC_E_PARAM; 11121 } 11122 if (NULL == table) { 11123 return SOC_E_PARAM; 11124 } 11125 11126 SOC_IF_ERROR_RETURN( 11127 soc_th_ifp_tcam_slice_size_calculate(unit, mem, 11128 &slice_count, 11129 slice_size_arr)); 11130 11131 entry_dw = soc_mem_entry_words(unit, mem); 11132 11133 slice_start_addr = soc_mem_index_min(unit, mem); 11134 for (slice = 0; slice < slice_count; slice++) { 11135 slice_end_addr = slice_start_addr + slice_size_arr[slice] - 1; 11136 SOC_IF_ERROR_RETURN( 11137 _soc_th_ifp_slice_mode_check(unit, mem, slice, 11138 &slice_skip)); 11139 if (!slice_skip) { 11140 if (en_per_pipe_read) { 11141 int i; 11142 uint32 ser_flags; 11143 int acc_type_list[] = { 11144 _SOC_TH_ACC_TYPE_UNIQUE_PIPE0, 11145 _SOC_TH_ACC_TYPE_UNIQUE_PIPE1, 11146 _SOC_TH_ACC_TYPE_UNIQUE_PIPE2, 11147 _SOC_TH_ACC_TYPE_UNIQUE_PIPE3}; 11148 for (i = 0; i < NUM_PIPE(unit); i++) { 11149 ser_flags = 0; 11150 ser_flags |= _SOC_SER_FLAG_DISCARD_READ; 11151 ser_flags |= _SOC_SER_FLAG_MULTI_PIPE; 11152 ser_flags |= acc_type_list[i]; 11153 LOG_VERBOSE(BSL_LS_SOC_SER, 11154 (BSL_META_U(unit, 11155 "soc_th_ifp_tcam_dma_read: will read slice %0d for mem %s, pipe %d\n"), 11156 slice, SOC_MEM_NAME(unit, mem), acc_type_list[i])); 11157 if (soc_mem_ser_read_range(unit, mem, blk, 11158 slice_start_addr, slice_end_addr, 11159 ser_flags, 11160 &table[slice_start_addr * entry_dw] 11161 ) < 0) { 11162 rv = SOC_E_FAIL; 11163 } 11164 } 11165 } else { 11166 LOG_VERBOSE(BSL_LS_SOC_SER, 11167 (BSL_META_U(unit, 11168 "soc_th_ifp_tcam_dma_read: will read slice %0d for mem %s\n"), 11169 slice, SOC_MEM_NAME(unit, mem))); 11170 if (soc_mem_read_range(unit, mem, blk, 11171 slice_start_addr, slice_end_addr, 11172 &table[slice_start_addr * entry_dw]) < 0) { 11173 rv = SOC_E_FAIL; 11174 } 11175 } 11176 } else { 11177 if (vmap != NULL) { 11178 sal_memset(&vmap[slice_start_addr / 8], 0, (slice_end_addr + 7 - slice_start_addr) / 8); 11179 } 11180 LOG_VERBOSE(BSL_LS_SOC_SER, 11181 (BSL_META_U(unit, 11182 "soc_th_ifp_tcam_dma_read: skipped slice %0d for mem %s\n"), 11183 slice, SOC_MEM_NAME(unit, mem))); 11184 } 11185 slice_start_addr = slice_end_addr + 1; 11186 } 11187 11188 return rv; 11189 } 11190 11191 static int 11192 _soc_th_ifp_tcam_index_valid(int unit, soc_mem_t mem, int index) { 11193 int rv = SOC_E_NONE; 11194 int slice_start_addr, slice_end_addr; 11195 int slice, slice_skip = 1; 11196 int slice_count = 0; 11197 int slice_size_arr[12] = { 0 }; 11198 11199 SOC_IF_ERROR_RETURN( 11200 soc_th_ifp_tcam_slice_size_calculate(unit, mem, 11201 &slice_count, 11202 slice_size_arr)); 11203 11204 slice_start_addr = soc_mem_index_min(unit, mem); 11205 11206 for (slice = 0; slice < slice_count && index >= slice_start_addr; slice++) { 11207 11208 slice_end_addr = slice_start_addr + slice_size_arr[slice] - 1; 11209 11210 if (index >= slice_start_addr && index <= slice_end_addr) { 11211 rv = _soc_th_ifp_slice_mode_check(unit, mem, slice, &slice_skip); 11212 if (SOC_FAILURE(rv)) { 11213 LOG_ERROR(BSL_LS_SOC_SER, 11214 (BSL_META_U(unit, 11215 "There is failure during slice mode check, slice %0d for mem %s(start 0x%x, end 0x%x)\n"), 11216 slice, SOC_MEM_NAME(unit, mem), slice_start_addr, slice_end_addr)); 11217 return FALSE; 11218 } 11219 if (slice_skip == 0) { /* slice can be read */ 11220 return TRUE; 11221 } 11222 } 11223 slice_start_addr = slice_end_addr + 1; 11224 } 11225 11226 return FALSE; 11227 } 11228 11229 int 11230 soc_th_dual_tcam_index_valid(int unit, soc_mem_t mem, int index) { 11231 soc_mem_t base_mem; 11232 int pipe; 11233 11234 if (FALSE == soc_th_mem_is_dual_mode(unit, mem, &base_mem, &pipe)) { 11235 return TRUE; /* valid index */ 11236 } 11237 11238 if (base_mem == IFP_TCAMm || base_mem == IFP_TCAM_WIDEm) { 11239 return _soc_th_ifp_tcam_index_valid(unit, mem, index); 11240 } 11241 /* add other dual mode memories here */ 11242 11243 return TRUE; /* valid index */ 11244 } 11245 11246 int 11247 soc_th_ifp_tcam_range_dma_read(int unit, soc_mem_t mem, int blk, 11248 int start_addr, uint32 num_entry, uint32 *table) 11249 { 11250 int slice, slice_skip = 0; 11251 int slice_start_addr, slice_end_addr, entry_dw; 11252 int min_addr, max_addr, end_addr; 11253 int rv = SOC_E_NONE; 11254 int slice_size_arr[12] = { 0 }; 11255 int slice_count = 0; 11256 11257 if (!SOC_MEM_IS_VALID(unit,mem)) { 11258 return SOC_E_PARAM; 11259 } 11260 if (NULL == table) { 11261 return SOC_E_PARAM; 11262 } 11263 min_addr = soc_mem_index_min(unit, mem); 11264 max_addr = soc_mem_index_max(unit, mem); 11265 end_addr = start_addr + num_entry; 11266 if (min_addr > start_addr || end_addr > max_addr) { 11267 return SOC_E_PARAM; 11268 } 11269 11270 SOC_IF_ERROR_RETURN( 11271 soc_th_ifp_tcam_slice_size_calculate(unit, mem, 11272 &slice_count, 11273 slice_size_arr)); 11274 11275 entry_dw = soc_mem_entry_words(unit, mem); 11276 11277 slice_start_addr = min_addr; 11278 11279 for (slice = 0; slice < slice_count; slice++) { 11280 slice_end_addr = slice_start_addr + slice_size_arr[slice] - 1; 11281 11282 if (start_addr > slice_end_addr) { 11283 slice_start_addr = slice_end_addr + 1; 11284 continue; 11285 } 11286 11287 SOC_IF_ERROR_RETURN( 11288 _soc_th_ifp_slice_mode_check(unit, mem, slice, 11289 &slice_skip)); 11290 if (slice_skip) { 11291 LOG_VERBOSE(BSL_LS_SOC_SER, 11292 (BSL_META_U(unit, 11293 "Skipped slice %0d for mem %s(start 0x%x, end 0x%x)\n"), 11294 slice, SOC_MEM_NAME(unit, mem), slice_start_addr, slice_end_addr)); 11295 slice_start_addr = slice_end_addr + 1; 11296 continue; 11297 } 11298 11299 if (start_addr > slice_start_addr) { 11300 slice_start_addr = start_addr; 11301 } 11302 if (end_addr < slice_end_addr) { 11303 slice_end_addr = end_addr; 11304 } 11305 11306 if (soc_mem_read_range(unit, mem, blk, 11307 slice_start_addr, slice_end_addr, 11308 &table[(slice_start_addr - start_addr) * entry_dw]) < 0) { 11309 rv = SOC_E_FAIL; 11310 LOG_ERROR(BSL_LS_SOC_SER, 11311 (BSL_META_U(unit, 11312 "Read slice %0d of mem %s(start 0x%x, end 0x%x) unsuccessfully\n"), 11313 slice, SOC_MEM_NAME(unit, mem), slice_start_addr, slice_end_addr)); 11314 return rv; 11315 } else { 11316 LOG_VERBOSE(BSL_LS_SOC_SER, 11317 (BSL_META_U(unit, 11318 "Read slice %0d of mem %s(start 0x%x, end 0x%x) successfully\n"), 11319 slice, SOC_MEM_NAME(unit, mem), slice_start_addr, slice_end_addr)); 11320 } 11321 if (end_addr <= slice_end_addr) { 11322 break; 11323 } 11324 slice_start_addr = slice_end_addr + 1; 11325 } 11326 11327 return rv; 11328 } 11329 11330 int 11331 soc_th_check_cache_skip(int unit, soc_mem_t mem) 11332 { 11333 if (!SOC_MEM_IS_VALID(unit,mem)) { 11334 return 1; 11335 } 11336 11337 switch (mem) { 11338 case L3_TUNNEL_DATA_ONLYm: 11339 11340 case DST_COMPRESSION_DATA_ONLYm: 11341 case DST_COMPRESSION_DATA_ONLY_PIPE0m: 11342 case DST_COMPRESSION_DATA_ONLY_PIPE1m: 11343 case DST_COMPRESSION_DATA_ONLY_PIPE2m: 11344 case DST_COMPRESSION_DATA_ONLY_PIPE3m: 11345 11346 case SRC_COMPRESSION_DATA_ONLYm: 11347 case SRC_COMPRESSION_DATA_ONLY_PIPE0m: 11348 case SRC_COMPRESSION_DATA_ONLY_PIPE1m: 11349 case SRC_COMPRESSION_DATA_ONLY_PIPE2m: 11350 case SRC_COMPRESSION_DATA_ONLY_PIPE3m: 11351 11352 case IFP_LOGICAL_TABLE_SELECT_DATA_ONLYm: 11353 case IFP_LOGICAL_TABLE_SELECT_DATA_ONLY_PIPE0m: 11354 case IFP_LOGICAL_TABLE_SELECT_DATA_ONLY_PIPE1m: 11355 case IFP_LOGICAL_TABLE_SELECT_DATA_ONLY_PIPE2m: 11356 case IFP_LOGICAL_TABLE_SELECT_DATA_ONLY_PIPE3m: 11357 11358 case EXACT_MATCH_LOGICAL_TABLE_SELECT_DATA_ONLYm: 11359 case EXACT_MATCH_LOGICAL_TABLE_SELECT_DATA_ONLY_PIPE0m: 11360 case EXACT_MATCH_LOGICAL_TABLE_SELECT_DATA_ONLY_PIPE1m: 11361 case EXACT_MATCH_LOGICAL_TABLE_SELECT_DATA_ONLY_PIPE2m: 11362 case EXACT_MATCH_LOGICAL_TABLE_SELECT_DATA_ONLY_PIPE3m: 11363 11364 case EXACT_MATCH_2_ENTRY_ONLYm: 11365 case EXACT_MATCH_2_ENTRY_ONLY_PIPE0m: 11366 case EXACT_MATCH_2_ENTRY_ONLY_PIPE1m: 11367 case EXACT_MATCH_2_ENTRY_ONLY_PIPE2m: 11368 case EXACT_MATCH_2_ENTRY_ONLY_PIPE3m: 11369 11370 case EXACT_MATCH_4_ENTRY_ONLYm: 11371 case EXACT_MATCH_4_ENTRY_ONLY_PIPE0m: 11372 case EXACT_MATCH_4_ENTRY_ONLY_PIPE1m: 11373 case EXACT_MATCH_4_ENTRY_ONLY_PIPE2m: 11374 case EXACT_MATCH_4_ENTRY_ONLY_PIPE3m: 11375 11376 case L2_ENTRY_ONLY_TILEm: 11377 case L2_ENTRY_TILEm: 11378 case L2_ENTRY_ONLY_ECCm: 11379 case L3_ENTRY_ONLY_ECCm: 11380 case L3_DEFIP_ALPM_ECCm: 11381 case FPEM_ECCm: 11382 case FPEM_ECC_PIPE0m: 11383 case FPEM_ECC_PIPE1m: 11384 case FPEM_ECC_PIPE2m: 11385 case FPEM_ECC_PIPE3m: 11386 case MPLS_ENTRY_ECCm: 11387 case VLAN_XLATE_ECCm: 11388 case EGR_VLAN_XLATE_ECCm: 11389 11390 case FPEM_LPm: 11391 case L2_ENTRY_ISS_LPm: 11392 case L3_ENTRY_ISS_LPm: 11393 11394 case EGR_FRAGMENT_ID_TABLEm: 11395 case EGR_FRAGMENT_ID_TABLE_PIPE0m: 11396 case EGR_FRAGMENT_ID_TABLE_PIPE1m: 11397 case EGR_FRAGMENT_ID_TABLE_PIPE2m: 11398 case EGR_FRAGMENT_ID_TABLE_PIPE3m: 11399 #ifdef BCM_TOMAHAWK3_SUPPORT 11400 case L3_DEFIP_ALPM_LEVEL2_ECCm: 11401 case L3_DEFIP_ALPM_LEVEL3_ECCm: 11402 #endif 11403 11404 LOG_VERBOSE(BSL_LS_SOC_SER, (BSL_META_U(unit, "cache_skip: skipping mem %s (soc_th_check_cache_skip)\n"), SOC_MEM_NAME(unit, mem))); 11405 return 1; 11406 11407 default: 11408 return 0; 11409 } 11410 /* 11411 case L2_ENTRY_TILEm: 11412 11413 case L3_DEFIP_ALPM_IPV4m: 11414 case L3_DEFIP_ALPM_IPV4_1m: 11415 case L3_DEFIP_ALPM_IPV6_64m: 11416 case L3_DEFIP_ALPM_IPV6_64_1m: 11417 case L3_DEFIP_ALPM_IPV6_128m: 11418 case L3_DEFIP_ALPM_RAWm: 11419 */ 11420 } 11421 11422 /* 11423 * following implement assist functions for soc_system_scrub() in 11424 * src/soc/esw/drv.c 11425 * 11426 * 1. Must not scrub 80b slices with _WIDE view and 160b slices with narrow view 11427 * 2. Must not scrub IFP_TCAM, IFP_TCAM_WIDE when in pipe_unique mode 11428 * 3. Must NOT scrub read_clear counters 11429 * 3. Can remove scrubbing of MEMm, if we are already scrubbing MEM_PIPE0-3m 11430 * 4. Are all mmu instances being scrubbed 11431 * 5. Views for which cachable=0 will not be scrubbed - so don't need to worry 11432 * about 11433 */ 11434 int 11435 soc_th_check_scrub_skip(int unit, soc_mem_t mem, int check_hw_global_mode) 11436 { 11437 if (!SOC_MEM_IS_VALID(unit,mem)) { 11438 return 1; /* skip */ 11439 } 11440 if (soc_mem_is_cam(unit, mem) && 11441 SOC_TH_MEM_CHK_TCAM_GLOBAL_UNIQUE_MODE(mem)) { 11442 /* For tcams that can operate in both global, unique modes, 11443 * we must skip read of global views when in unique mode. 11444 * This is because SER_ENGINE when configured to track tcam in unique 11445 * mode may not know which parity bits to use for comparison when it 11446 * sees read of global_view (with acc_type = 9) 11447 * Note: for srams, this skip is not necessary, because these are 11448 * not covered by SER_ENGINE 11449 * 11450 * We cannot skip read of global views when in global mode. 11451 * This is because, even though we scrub _PIPE0,1,2,3 views - these 11452 * will result in detection of error - but not correction !! 11453 * So we must scrub global views. 11454 * We can optimize by skipping scrub of _PIPE0,1,2,3 views when in 11455 * global mode. But this is not needed - because this will happen only 11456 * once during exit_clean and not during non_tcam_iterations (because 11457 * when doing non_tcam_iterations, we will be skipping all tcams) */ 11458 int rv; 11459 int mem_mode = _SOC_SER_MEM_MODE_GLOBAL; 11460 if (check_hw_global_mode) { 11461 rv = soc_th_check_hw_global_mode(unit, mem, &mem_mode); 11462 /* field module may already be de-initialized */ 11463 } else { 11464 #ifdef BCM_TOMAHAWK3_SUPPORT 11465 /* This function is invoked during system initialization and shutdown. 11466 Before calling this function, field module is already detached. So 11467 don't need to get the mem_mode, just use default GLOBAL mode. 11468 */ 11469 if (SOC_IS_TOMAHAWK3(unit)) { 11470 rv = SOC_E_NONE; 11471 } else 11472 #endif 11473 { 11474 rv = soc_th_field_mem_mode_get(unit, mem, &mem_mode); 11475 /* field module is active */ 11476 } 11477 } 11478 if ((rv == SOC_E_NONE) && (mem_mode == _SOC_SER_MEM_MODE_PIPE_UNIQUE)) { 11479 LOG_VERBOSE(BSL_LS_SOC_SER, (BSL_META_U(unit, "scrub: skipping mem %s (cannot read this mem in pipe_unique_mode)\n"), SOC_MEM_NAME(unit, mem))); 11480 return 1; /* skip */ 11481 } else { 11482 return 0; /* we know for sure this mem is not in 'skip_list' */ 11483 } 11484 } 11485 11486 switch (mem) { 11487 /* ECC views need not be scrubbed */ 11488 case L2_ENTRY_ONLY_ECCm: 11489 /* 1:1 mapping with L2Xm, so scan L2Xm */ 11490 11491 /* case L3_ENTRY_ONLY_ECCm: */ 11492 case L3_ENTRY_IPV4_UNICASTm: 11493 case L3_ENTRY_IPV4_MULTICASTm: 11494 case L3_ENTRY_IPV6_UNICASTm: 11495 case L3_ENTRY_IPV6_MULTICASTm: 11496 case L3_ENTRY_ONLYm: 11497 11498 /* case L3_DEFIP_ALPM_ECCm: */ 11499 case L3_DEFIP_ALPM_IPV4m: 11500 case L3_DEFIP_ALPM_IPV4_1m: 11501 case L3_DEFIP_ALPM_IPV6_64m: 11502 case L3_DEFIP_ALPM_IPV6_64_1m: 11503 case L3_DEFIP_ALPM_IPV6_128m: 11504 case L3_DEFIP_ALPM_RAWm: 11505 11506 case FPEM_ECCm: 11507 /* Has unique acc type, so only pipe0 will be scanned. 11508 * Instead, scan the _pipe0-3 views */ 11509 /* case FPEM_ECC_PIPE0m: */ 11510 /* case FPEM_ECC_PIPE1m: */ 11511 /* case FPEM_ECC_PIPE2m: */ 11512 /* case FPEM_ECC_PIPE3m: */ 11513 11514 case EXACT_MATCH_2m: 11515 case EXACT_MATCH_2_PIPE0m: 11516 case EXACT_MATCH_2_PIPE1m: 11517 case EXACT_MATCH_2_PIPE2m: 11518 case EXACT_MATCH_2_PIPE3m: 11519 11520 case EXACT_MATCH_4m: 11521 case EXACT_MATCH_4_PIPE0m: 11522 case EXACT_MATCH_4_PIPE1m: 11523 case EXACT_MATCH_4_PIPE2m: 11524 case EXACT_MATCH_4_PIPE3m: 11525 11526 case MPLS_ENTRY_ECCm: 11527 case VLAN_XLATE_ECCm: 11528 case EGR_VLAN_XLATE_ECCm: 11529 11530 /* DATA_ONLY, ENTRY_ONLY views need not be scrubbed */ 11531 /* 11532 case L2_USER_ENTRY_DATA_ONLYm: 11533 case L2_USER_ENTRY_ONLYm: 11534 */ 11535 case L3_TUNNEL_DATA_ONLYm: 11536 case L3_TUNNEL_ONLYm: 11537 11538 case VLAN_SUBNET_DATA_ONLYm: 11539 case VLAN_SUBNET_ONLYm: 11540 11541 case MY_STATION_TCAM_DATA_ONLYm: 11542 case MY_STATION_TCAM_ENTRY_ONLYm: 11543 11544 case ING_SNAT_DATA_ONLYm: 11545 case ING_SNAT_ONLYm: 11546 11547 case DST_COMPRESSION_DATA_ONLYm: 11548 case DST_COMPRESSION_DATA_ONLY_PIPE0m: 11549 case DST_COMPRESSION_DATA_ONLY_PIPE1m: 11550 case DST_COMPRESSION_DATA_ONLY_PIPE2m: 11551 case DST_COMPRESSION_DATA_ONLY_PIPE3m: 11552 /* 11553 case DST_COMPRESSION_TCAM_ONLYm: 11554 case DST_COMPRESSION_TCAM_ONLY_PIPE0m: 11555 case DST_COMPRESSION_TCAM_ONLY_PIPE1m: 11556 case DST_COMPRESSION_TCAM_ONLY_PIPE2m: 11557 case DST_COMPRESSION_TCAM_ONLY_PIPE3m: 11558 */ 11559 11560 case SRC_COMPRESSION_DATA_ONLYm: 11561 case SRC_COMPRESSION_DATA_ONLY_PIPE0m: 11562 case SRC_COMPRESSION_DATA_ONLY_PIPE1m: 11563 case SRC_COMPRESSION_DATA_ONLY_PIPE2m: 11564 case SRC_COMPRESSION_DATA_ONLY_PIPE3m: 11565 /* 11566 case SRC_COMPRESSION_TCAM_ONLYm: 11567 case SRC_COMPRESSION_TCAM_ONLY_PIPE0m: 11568 case SRC_COMPRESSION_TCAM_ONLY_PIPE1m: 11569 case SRC_COMPRESSION_TCAM_ONLY_PIPE2m: 11570 case SRC_COMPRESSION_TCAM_ONLY_PIPE3m: 11571 11572 case EXACT_MATCH_LOGICAL_TABLE_SELECT_DATA_ONLYm: 11573 case EXACT_MATCH_LOGICAL_TABLE_SELECT_DATA_ONLY_PIPE0m: 11574 case EXACT_MATCH_LOGICAL_TABLE_SELECT_DATA_ONLY_PIPE1m: 11575 case EXACT_MATCH_LOGICAL_TABLE_SELECT_DATA_ONLY_PIPE2m: 11576 case EXACT_MATCH_LOGICAL_TABLE_SELECT_DATA_ONLY_PIPE3m: 11577 11578 case EXACT_MATCH_LOGICAL_TABLE_SELECT_TCAM_ONLYm: 11579 case EXACT_MATCH_LOGICAL_TABLE_SELECT_TCAM_ONLY_PIPE0m: 11580 case EXACT_MATCH_LOGICAL_TABLE_SELECT_TCAM_ONLY_PIPE1m: 11581 case EXACT_MATCH_LOGICAL_TABLE_SELECT_TCAM_ONLY_PIPE2m: 11582 case EXACT_MATCH_LOGICAL_TABLE_SELECT_TCAM_ONLY_PIPE3m: 11583 */ 11584 11585 case IFP_LOGICAL_TABLE_SELECT_DATA_ONLYm: 11586 case IFP_LOGICAL_TABLE_SELECT_DATA_ONLY_PIPE0m: 11587 case IFP_LOGICAL_TABLE_SELECT_DATA_ONLY_PIPE1m: 11588 case IFP_LOGICAL_TABLE_SELECT_DATA_ONLY_PIPE2m: 11589 case IFP_LOGICAL_TABLE_SELECT_DATA_ONLY_PIPE3m: 11590 /* 11591 case IFP_LOGICAL_TABLE_SELECT_TCAM_ONLYm: 11592 case IFP_LOGICAL_TABLE_SELECT_TCAM_ONLY_PIPE0m: 11593 case IFP_LOGICAL_TABLE_SELECT_TCAM_ONLY_PIPE1m: 11594 case IFP_LOGICAL_TABLE_SELECT_TCAM_ONLY_PIPE2m: 11595 case IFP_LOGICAL_TABLE_SELECT_TCAM_ONLY_PIPE3m: 11596 */ 11597 11598 /* specials which need not be scrubbed */ 11599 case L2_BULKm: 11600 case L2_ENTRY_ONLY_TILEm: 11601 case L2_ENTRY_TILEm: 11602 case L2_LEARN_INSERT_FAILUREm: 11603 11604 case EXACT_MATCH_2_ENTRY_ONLYm: 11605 case EXACT_MATCH_2_ENTRY_ONLY_PIPE0m: 11606 case EXACT_MATCH_2_ENTRY_ONLY_PIPE1m: 11607 case EXACT_MATCH_2_ENTRY_ONLY_PIPE2m: 11608 case EXACT_MATCH_2_ENTRY_ONLY_PIPE3m: 11609 11610 case EXACT_MATCH_4_ENTRY_ONLYm: 11611 case EXACT_MATCH_4_ENTRY_ONLY_PIPE0m: 11612 case EXACT_MATCH_4_ENTRY_ONLY_PIPE1m: 11613 case EXACT_MATCH_4_ENTRY_ONLY_PIPE2m: 11614 case EXACT_MATCH_4_ENTRY_ONLY_PIPE3m: 11615 11616 /* global views which already have _PIPE0-PIPE3 views */ 11617 11618 LOG_VERBOSE(BSL_LS_SOC_SER, (BSL_META_U(unit, "scrub: skipping mem %s (soc_th_check_scrub_skip)\n"), SOC_MEM_NAME(unit, mem))); 11619 return 1; 11620 default: 11621 /* 11622 * Must NOT BE skipped 11623 * ------------------- 11624 * LP views - they could have parity errors 11625 * Mems scanned by memscan - we need to scrub them 11626 * MEMm if scanning MEM_PIPE0-3m 11627 */ 11628 break; 11629 } 11630 return 0; 11631 } 11632 11633 int 11634 soc_th_mem_is_eligible_for_scan(int unit, soc_mem_t mem) 11635 { 11636 switch (mem) { 11637 case L3_ENTRY_ONLY_ECCm: 11638 case L3_DEFIP_ALPM_ECCm: 11639 case FPEM_ECC_PIPE0m: 11640 case FPEM_ECC_PIPE1m: 11641 case FPEM_ECC_PIPE2m: 11642 case FPEM_ECC_PIPE3m: 11643 case L2_ENTRY_ISS_LPm: 11644 case L2_ENTRY_LPm: 11645 case L3_ENTRY_ISS_LPm: 11646 case L3_ENTRY_LPm: 11647 case FPEM_LPm: 11648 case VLAN_XLATE_LPm: 11649 case EGR_VLAN_XLATE_LPm: 11650 return 1; 11651 default: 11652 break; 11653 } 11654 return 0; 11655 } 11656 11657 void 11658 soc_th_mem_scan_info_get(int unit, soc_mem_t mem, int block, 11659 int *num_pipe, int *ser_flags) 11660 { 11661 int k, num_inst_to_scrub = 0, acc_type_list[8], copyno = block; 11662 #ifdef BCM_TOMAHAWK3_SUPPORT 11663 if (SOC_IS_TOMAHAWK3(unit)) { 11664 (void)soc_th3_check_scrub_info(unit, mem, block, copyno, 11665 &num_inst_to_scrub, acc_type_list); 11666 } else 11667 #endif 11668 { 11669 (void) soc_th_check_scrub_info(unit, mem, block, copyno, 11670 &num_inst_to_scrub, 11671 acc_type_list); 11672 } 11673 /* in case of SOC_FAILURE(rv), num_inst_to_scrub = 0, so 11674 * will be handled below as if we need to scrub only one 11675 * pipe */ 11676 assert(num_inst_to_scrub <= 8); 11677 if (num_inst_to_scrub == 0) { 11678 *num_pipe = 1; 11679 ser_flags[0] = 0; 11680 if (!soc_mem_dmaable(unit, mem, block)) { 11681 ser_flags[0] = _SOC_SER_FLAG_NO_DMA; 11682 } 11683 } else { 11684 *num_pipe = num_inst_to_scrub; 11685 for (k = 0; k < num_inst_to_scrub; k++) { 11686 ser_flags[k] = 0; 11687 ser_flags[k] |= _SOC_SER_FLAG_DISCARD_READ; 11688 ser_flags[k] |= _SOC_SER_FLAG_MULTI_PIPE; 11689 ser_flags[k] |= acc_type_list[k]; 11690 if (!soc_mem_dmaable(unit, mem, block)) { 11691 ser_flags[k] |= _SOC_SER_FLAG_NO_DMA; 11692 } 11693 } 11694 } 11695 } 11696 11697 int 11698 soc_th_check_scrub_info(int unit, soc_mem_t mem, int blk, int copyno, 11699 int *num_inst_to_scrub, int *acc_type_list) 11700 { 11701 int mem_acc_type = SOC_MEM_ACC_TYPE(unit, mem); 11702 int mmu_base_type, mmu_base_index; 11703 soc_block_t blk_type; 11704 11705 if (copyno == COPYNO_ALL) { 11706 return SOC_E_PARAM; 11707 } 11708 blk_type = SOC_BLOCK_TYPE(unit, copyno); 11709 11710 if ((NULL == acc_type_list) || (NULL == num_inst_to_scrub)) { 11711 return SOC_E_PARAM; 11712 } 11713 11714 *num_inst_to_scrub = 0; 11715 11716 if (!SOC_MEM_IS_VALID(unit,mem)) { 11717 return SOC_E_NONE; 11718 } 11719 11720 /* L3_DEFIPm/L3_DEFIP_PAIR_128m should be scrubed */ 11721 if ((mem == L3_DEFIPm) || (mem == L3_DEFIP_PAIR_128m)) { 11722 *num_inst_to_scrub = NUM_PIPE(unit); 11723 acc_type_list[0] = _SOC_TH_ACC_TYPE_UNIQUE_PIPE0; 11724 acc_type_list[1] = _SOC_TH_ACC_TYPE_UNIQUE_PIPE1; 11725 acc_type_list[2] = _SOC_TH_ACC_TYPE_UNIQUE_PIPE2; 11726 acc_type_list[3] = _SOC_TH_ACC_TYPE_UNIQUE_PIPE3; 11727 } 11728 11729 if (((mem_acc_type == _SOC_TH_ACC_TYPE_DUPLICATE) && 11730 ((blk_type == SOC_BLK_IPIPE) || (blk_type == SOC_BLK_EPIPE)) && 11731 (SOC_MEM_UNIQUE_ACC(unit, mem) == NULL)) || 11732 SOC_TH_MEM_CHK_TCAM_GLOBAL_UNIQUE_MODE(mem)) { 11733 /* 2nd last term: sw has not already created per-instance unique views */ 11734 *num_inst_to_scrub = NUM_PIPE(unit); 11735 acc_type_list[0] = _SOC_TH_ACC_TYPE_UNIQUE_PIPE0; 11736 acc_type_list[1] = _SOC_TH_ACC_TYPE_UNIQUE_PIPE1; 11737 acc_type_list[2] = _SOC_TH_ACC_TYPE_UNIQUE_PIPE2; 11738 acc_type_list[3] = _SOC_TH_ACC_TYPE_UNIQUE_PIPE3; 11739 LOG_VERBOSE(BSL_LS_SOC_SER, (BSL_META_U(unit, "scrub: mem.blk.blk_type %s.%d.%d has acc_type = %s (%d), num_inst_to_scrub = %0d\n"), 11740 SOC_MEM_NAME(unit,mem), blk, blk_type, 11741 _SOC_TH_ACC_TYPE_NAME(mem_acc_type), mem_acc_type, 11742 *num_inst_to_scrub)); 11743 return SOC_E_NONE; 11744 } /* need_per_pipe_scrub */ 11745 11746 if ((mem_acc_type == _SOC_TH_ACC_TYPE_DUPLICATE) && 11747 ((blk_type == SOC_BLK_MMU_GLB) || 11748 (blk_type == SOC_BLK_MMU_XPE) || 11749 (blk_type == SOC_BLK_MMU_SC))) { 11750 11751 mmu_base_type = SOC_MEM_BASE_TYPE(unit, mem); 11752 11753 11754 switch (blk_type) { 11755 case SOC_BLK_MMU_XPE: 11756 switch (mmu_base_type) { 11757 case SOC_TH_MMU_BASE_TYPE_IPIPE: 11758 mmu_base_index = _SOC_MMU_BASE_INDEX(unit, mem, 3); 11759 if ((mmu_base_index == 0) || (mmu_base_index == 3)) { 11760 /* ipipe0,3 serviced by xpe0,1 */ 11761 *num_inst_to_scrub = 2; 11762 acc_type_list[0] = 0; 11763 acc_type_list[1] = 1; 11764 } else { 11765 /* ipipe1,2 serviced by xpe2,3 */ 11766 *num_inst_to_scrub = 2; 11767 acc_type_list[0] = 2; 11768 acc_type_list[1] = 3; 11769 } 11770 break; 11771 case SOC_TH_MMU_BASE_TYPE_EPIPE: 11772 mmu_base_index = _SOC_MMU_BASE_INDEX(unit, mem, 3); 11773 if ((mmu_base_index == 0) || (mmu_base_index == 1)) { 11774 /* epipe0,1 serviced by xpe0,2 */ 11775 *num_inst_to_scrub = 2; 11776 acc_type_list[0] = 0; 11777 acc_type_list[1] = 2; 11778 } else { 11779 /* epipe2,3 serviced by xpe1,3 */ 11780 *num_inst_to_scrub = 2; 11781 acc_type_list[0] = 1; 11782 acc_type_list[1] = 3; 11783 } 11784 break; 11785 case SOC_TH_MMU_BASE_TYPE_CHIP: 11786 /* must read each xpe instance */ 11787 *num_inst_to_scrub = 4; 11788 acc_type_list[0] = 0; 11789 acc_type_list[1] = 1; 11790 acc_type_list[2] = 2; 11791 acc_type_list[3] = 3; 11792 break; 11793 case SOC_TH_MMU_BASE_TYPE_SLICE: 11794 mmu_base_index = _SOC_MMU_BASE_INDEX(unit, mem, 1); 11795 if (mmu_base_index == 0) { 11796 /* slice0 serviced by xpe0,2 */ 11797 *num_inst_to_scrub = 2; 11798 acc_type_list[0] = 0; 11799 acc_type_list[1] = 2; 11800 } else { 11801 /* slice1 serviced by xpe1,3 */ 11802 *num_inst_to_scrub = 2; 11803 acc_type_list[0] = 1; 11804 acc_type_list[1] = 3; 11805 } 11806 break; 11807 case SOC_TH_MMU_BASE_TYPE_LAYER: 11808 mmu_base_index = _SOC_MMU_BASE_INDEX(unit, mem, 1); 11809 if (mmu_base_index == 0) { 11810 /* layer_A serviced by xpe0,1 */ 11811 *num_inst_to_scrub = 2; 11812 acc_type_list[0] = 0; 11813 acc_type_list[1] = 1; 11814 } else { 11815 /* layer_B serviced by xpe2,3 */ 11816 *num_inst_to_scrub = 2; 11817 acc_type_list[0] = 2; 11818 acc_type_list[1] = 3; 11819 } 11820 break; 11821 default: /* IPORT, EPORT, XPE */ 11822 /* should not find any TH memories here */ 11823 LOG_ERROR(BSL_LS_SOC_SER, (BSL_META_U(unit, "scrub_ERROR: mem.blk.blk_type %s.%d.%d has acc_type = %s (%d), num_inst_to_scrub = %0d, mmu_base_type = %0d\n"), 11824 SOC_MEM_NAME(unit,mem), blk, blk_type, 11825 _SOC_TH_ACC_TYPE_NAME(mem_acc_type), mem_acc_type, 11826 *num_inst_to_scrub, mmu_base_type)); 11827 return SOC_E_FAIL; 11828 } /* mmu_base_type */ 11829 break; /* case: SOC_BLK_MMU_XPE */ 11830 11831 default: /* SOC_BLK_MMU_GLB, SOC_BLK_MMU_SC */ 11832 /* should not find any TH memories here */ 11833 LOG_ERROR(BSL_LS_SOC_SER, (BSL_META_U(unit, "scrub_ERROR: mem.blk.blk_type %s.%d.%d has acc_type = %s (%d), num_inst_to_scrub = %0d, mmu_base_type = %0d\n"), 11834 SOC_MEM_NAME(unit,mem), blk, blk_type, 11835 _SOC_TH_ACC_TYPE_NAME(mem_acc_type), mem_acc_type, 11836 *num_inst_to_scrub, mmu_base_type)); 11837 return SOC_E_FAIL; 11838 } /* blk_type */ 11839 LOG_VERBOSE(BSL_LS_SOC_SER, (BSL_META_U(unit, "scrub: mem.blk.blk_type %s.%d.%d has acc_type = %s (%d), num_inst_to_scrub = %0d, mmu_base_type = %0d\n"), 11840 SOC_MEM_NAME(unit,mem), blk, blk_type, 11841 _SOC_TH_ACC_TYPE_NAME(mem_acc_type), mem_acc_type, 11842 *num_inst_to_scrub, mmu_base_type)); 11843 return SOC_E_NONE; 11844 } /* need_per_mmu_membase_scrub */ 11845 return SOC_E_NONE; 11846 } 11847 11848 /* For lookup operations to folded hash tables, SER event could be on LP view or 11849 * functional view (fv), even when search is issued to functional view. 11850 * In case when there is error on LP view, rsp_word 11851 * carries index to LP view and not the functinal view. 11852 * Following function helps remap the fv_index to lp_index. 11853 * It assumes that err_info received by caller is '1' meaning HW is indicating 11854 * that error is in LP view. Because this can happen only for folded hash 11855 * tables, any other mem passed as param to this function will result in return 11856 * with error from this function. 11857 */ 11858 int 11859 soc_th_lp_to_fv_index_remap(int unit, soc_mem_t mem, int *rpt_index) 11860 { 11861 int em_lp_bank, em_lp_addr, index, rv = SOC_E_NONE; 11862 11863 if (NULL == rpt_index) { 11864 return SOC_E_PARAM; 11865 } 11866 index = *rpt_index; /* default */ 11867 switch(mem) { 11868 case VLAN_MACm: 11869 case VLAN_XLATEm: 11870 /* Error in VLAN_XLATE_LPm */ 11871 index = index << 2; /* = 4*index; for cache read */ 11872 break; 11873 case EGR_VLAN_XLATEm: 11874 /* Error in EGR_VLAN_XLATE_LPm */ 11875 index = index << 2; /* = 4*index; for cache read */ 11876 break; 11877 case EXACT_MATCH_2m: 11878 case EXACT_MATCH_2_PIPE0m: 11879 case EXACT_MATCH_2_PIPE1m: 11880 case EXACT_MATCH_2_PIPE2m: 11881 case EXACT_MATCH_2_PIPE3m: 11882 /* Error in FPEM_LPm */ 11883 assert(index < 32768); 11884 em_lp_bank = (index >> 13) & 0x3; /* = index/8K; can be 0,1,2,3 */ 11885 em_lp_addr = index & 0x1FFF; /* = index%8K; adr within lp bank */ 11886 assert(em_lp_addr < 4096); /* For EM_2 */ 11887 index = (16384 * em_lp_bank) + (4 * em_lp_addr); 11888 /* each lp bank is 8K deep, total of 4 lp banks, 1 per each uft_bank */ 11889 /* each uft bank can have 16K EM_2 entries */ 11890 /* each lp_entry covers 4 consec EM_2 entries */ 11891 /* index is the addr of first em2_entry in the bkt pointed by 11892 * lp_adr reported in err_rsp */ 11893 index = 2*index; 11894 /* Each em2 entry has 2 FPEM_ECC entries. 11895 Now index is addr of first fpem_ecc entry in the bkt pointed 11896 by lp_adr reported in err_rsp */ 11897 LOG_WARN(BSL_LS_SOC_SER, 11898 (BSL_META_U(unit, 11899 "unit %d, th_lp_to_fv_index_remap: " 11900 "mem %s, em_lp_bank %d, em_lp_addr %0d \n"), 11901 unit, SOC_MEM_NAME(unit, mem), em_lp_bank, em_lp_addr)); 11902 break; 11903 case EXACT_MATCH_4m: 11904 case EXACT_MATCH_4_PIPE0m: 11905 case EXACT_MATCH_4_PIPE1m: 11906 case EXACT_MATCH_4_PIPE2m: 11907 case EXACT_MATCH_4_PIPE3m: 11908 /* Error in FPEM_LPm */ 11909 assert(index < 32768); 11910 em_lp_bank = (index >> 13) & 0x3; /* = index/8K; can be 0,1,2,3 */ 11911 em_lp_addr = index & 0x1FFF; /* = index%8K; adr within lp bank */ 11912 assert(em_lp_addr >= 4096); /* For EM_4 */ 11913 assert(em_lp_addr < 6144); /* For EM_4 */ 11914 index = (8192 * em_lp_bank) + (4 * (em_lp_addr - 4096)); 11915 /* each lp bank is 8K deep, total of 4 lp banks, 1 per each uft_bank */ 11916 /* each uft bank can have 8K EM_4 entries */ 11917 /* each lp_entry covers 4 consec EM_4 entries */ 11918 /* index is the addr of first em4_entry in the bkt pointed by 11919 * lp_adr reported in err_rsp */ 11920 index = 4*index; 11921 /* Each em4 entry has 4 FPEM_ECC entries. 11922 Now index is addr of first fpem_ecc entry in the bkt pointed 11923 by lp_adr reported in err_rsp */ 11924 LOG_WARN(BSL_LS_SOC_SER, 11925 (BSL_META_U(unit, 11926 "unit %d, th_lp_to_fv_index_remap: " 11927 "mem %s, em_lp_bank %d, em_lp_addr %0d \n"), 11928 unit, SOC_MEM_NAME(unit, mem), em_lp_bank, em_lp_addr)); 11929 break; 11930 default: 11931 LOG_ERROR(BSL_LS_SOC_SER, 11932 (BSL_META_U(unit, 11933 "soc_th_lp_to_fv_index_remap: mem %s is not folded hash table !! index %d\n"), 11934 SOC_MEM_NAME(unit, mem), index)); 11935 rv = SOC_E_PARAM; 11936 } 11937 11938 LOG_WARN(BSL_LS_SOC_SER, 11939 (BSL_META_U(unit, 11940 "unit %d, th_lp_to_fv_index_remap: " 11941 "mem %s, rpt_lp_index %0d, fv_index %0d \n"), 11942 unit, SOC_MEM_NAME(unit, mem), *rpt_index, index)); 11943 *rpt_index = index; 11944 return rv; 11945 } 11946 11947 STATIC 11948 int 11949 _soc_th_reg32_par_en_modify(int unit, soc_reg_t reg, soc_field_t field, 11950 int enable) 11951 { 11952 uint64 rval64; 11953 uint32 rval; 11954 int port = REG_PORT_ANY; 11955 static char *mmu_base_type[8] = { 11956 "IPORT", "EPORT", "IPIPE", "EPIPE", "CHIP", "XPE", "SLICE", "LAYER"}; 11957 11958 if (SOC_REG_IS_VALID(unit, reg) && INVALIDf != field) { 11959 if (SOC_REG_IS_64(unit, reg)) { 11960 SOC_IF_ERROR_RETURN 11961 (soc_reg_get(unit, reg, port, 0, &rval64)); 11962 soc_reg64_field32_set(unit, reg, &rval64, field, enable? 1 : 0); 11963 SOC_IF_ERROR_RETURN 11964 (soc_reg_set(unit, reg, port, 0, rval64)); 11965 } else { 11966 int at, bt; 11967 SOC_IF_ERROR_RETURN 11968 (soc_reg32_get(unit, reg, port, 0, &rval)); 11969 soc_reg_field_set(unit, reg, &rval, field, 11970 enable ? 1 : 0); 11971 at = SOC_REG_ACC_TYPE(unit, reg); 11972 bt = SOC_REG_BASE_TYPE(unit, reg); 11973 if (20 == at) { /* ACC_TYPE_SINGLE - used only in MMU blocks */ 11974 int inst, pipe, max_pipe; 11975 switch (bt) { 11976 case 2: /* IPIPE */ 11977 case 3: /* EPIPE */ 11978 max_pipe = NUM_PIPE(unit); break; 11979 case 4: /* CHIP */ 11980 max_pipe = 1; break; 11981 case 5: /* XPE */ 11982 max_pipe = NUM_XPE(unit); break; 11983 case 6: /* SLICE */ 11984 max_pipe = NUM_SLICE(unit); break; 11985 case 7: /* LAYER */ 11986 max_pipe = NUM_LAYER(unit); break; 11987 default: 11988 /* 0: IPORT */ 11989 /* 1: EPORT */ 11990 max_pipe = -1; 11991 LOG_WARN(BSL_LS_SOC_SER, 11992 (BSL_META_U(unit, 11993 "unit %d, reg %s has unexpected " 11994 "base_type %s, will skip enable of " 11995 "1b err reporting\n"), 11996 unit, SOC_REG_NAME(unit, reg), 11997 mmu_base_type[bt])); 11998 break; 11999 } 12000 LOG_VERBOSE(BSL_LS_SOC_SER, 12001 (BSL_META_U(unit, 12002 "unit %d, reg %s has base_type %s\n"), 12003 unit, SOC_REG_NAME(unit, reg), 12004 mmu_base_type[bt])); 12005 for (pipe = 0; pipe < max_pipe; pipe++) { 12006 inst = pipe | SOC_REG_ADDR_INSTANCE_MASK; 12007 SOC_IF_ERROR_RETURN 12008 (soc_reg32_set(unit, reg, inst, 0, rval)); 12009 LOG_WARN(BSL_LS_SOC_SER, (BSL_META_U(unit, 12010 "HF detected: setting reg.field[%s.%s]=0, mmu_base_type %s, pipe %d, using acc_type %0d\n"), 12011 SOC_REG_NAME(unit, reg), SOC_FIELD_NAME(unit, field), 12012 mmu_base_type[bt], pipe, at)); 12013 } 12014 } else { 12015 SOC_IF_ERROR_RETURN 12016 (soc_reg32_set(unit, reg, port, 0, rval)); 12017 LOG_WARN(BSL_LS_SOC_SER, (BSL_META_U(unit, 12018 "HF detected: setting reg.field[%s.%s]=0, using acc_type %0d (default)\n"), 12019 SOC_REG_NAME(unit, reg), SOC_FIELD_NAME(unit, field), 12020 at)); 12021 } 12022 } /* reg32 */ 12023 return SOC_E_NONE; 12024 } 12025 return SOC_E_UNAVAIL; 12026 } 12027 12028 static int 12029 soc_th_mem_parity_set(int unit, soc_mem_t mem, int copyno, 12030 _soc_mem_ser_en_info_t *ser_info_list, 12031 int en, int en_1b) 12032 { 12033 int i = 0; 12034 12035 for (i = 0; INVALIDm != ser_info_list[i].mem; i++) { 12036 if (ser_info_list[i].mem == mem) { 12037 #ifdef BCM_TOMAHAWK3_SUPPORT 12038 if (SOC_IS_TOMAHAWK3(unit)) { 12039 SOC_IF_ERROR_RETURN( 12040 _soc_th3_reg32_par_en_modify(unit, 12041 ser_info_list[i].en_ctrl.ctrl_type.en_reg, 12042 ser_info_list[i].en_ctrl.en_fld, 12043 en)); 12044 SOC_IF_ERROR_RETURN( 12045 _soc_th3_reg32_par_en_modify(unit, 12046 ser_info_list[i].ecc1b_ctrl.ctrl_type.en_reg, 12047 ser_info_list[i].ecc1b_ctrl.en_fld, 12048 en_1b)); 12049 } else 12050 #endif 12051 { 12052 SOC_IF_ERROR_RETURN( 12053 _soc_th_reg32_par_en_modify(unit, 12054 ser_info_list[i].en_ctrl.ctrl_type.en_reg, 12055 ser_info_list[i].en_ctrl.en_fld, 12056 en)); 12057 SOC_IF_ERROR_RETURN( 12058 _soc_th_reg32_par_en_modify(unit, 12059 ser_info_list[i].ecc1b_ctrl.ctrl_type.en_reg, 12060 ser_info_list[i].ecc1b_ctrl.en_fld, 12061 en_1b)); 12062 } 12063 return SOC_E_NONE; 12064 } 12065 } 12066 12067 return SOC_E_UNAVAIL; 12068 12069 } 12070 12071 12072 int soc_th_mem_parity_control(int unit, soc_mem_t mem, int copyno, 12073 int en, int en_1b) 12074 { 12075 int ret = SOC_E_NONE; 12076 12077 if (!SOC_MEM_IS_VALID(unit, mem)) { 12078 return SOC_E_UNAVAIL; 12079 } 12080 12081 ret = soc_th_mem_parity_set(unit, mem, copyno, SOC_IP_MEM_SER_INFO(unit), en, en_1b); 12082 if (ret == SOC_E_NONE) { 12083 return ret; 12084 } 12085 12086 ret = soc_th_mem_parity_set(unit, mem, copyno, SOC_EP_MEM_SER_INFO(unit), en, en_1b); 12087 if (ret == SOC_E_NONE) { 12088 return ret; 12089 } 12090 12091 ret = soc_th_mem_parity_set(unit, mem, copyno, SOC_MMU_MEM_SER_INFO(unit), en, en_1b); 12092 if (ret == SOC_E_NONE) { 12093 return ret; 12094 } 12095 12096 return SOC_E_UNAVAIL; 12097 } 12098 12099 #define MEM_SER_INFO_COUNT 3 12100 /* 12101 * Function: 12102 * soc_th_ser_single_bit_error_enable_set 12103 * Purpose: 12104 * Enable/Disable single bit eror reporting for the memories which are 12105 * protected by ECC logic and whoes SER_RESPONSE is SER_NONE on TD2/TD2p chips 12106 * Parameters: 12107 * unit - (IN) Device Number 12108 * enable - (IN) Enable/Disable 12109 * Returns: 12110 * SOC_E_NONE if set successfully, an error otherwise 12111 */ 12112 int soc_th_ser_single_bit_error_enable_set(int unit, int enable) 12113 { 12114 int i, value, k; 12115 soc_reg_t ecc_reg; 12116 soc_field_t ecc_fld; 12117 _soc_mem_ser_en_info_t *mem_ser_info; 12118 _soc_mem_ser_en_info_t *mem_ser_info_all[MEM_SER_INFO_COUNT] = {NULL}; 12119 12120 value = enable ? 1:0; 12121 12122 mem_ser_info_all[0] = SOC_IP_MEM_SER_INFO(unit); 12123 mem_ser_info_all[1] = SOC_EP_MEM_SER_INFO(unit); 12124 mem_ser_info_all[2] = SOC_MMU_MEM_SER_INFO(unit); 12125 12126 if (NULL == mem_ser_info_all[0]) { 12127 /* If this is not TH or TH+, we won't be able to get the mem info */ 12128 return SOC_E_UNAVAIL; 12129 } 12130 12131 for (k = 0; k < MEM_SER_INFO_COUNT; k++) { 12132 mem_ser_info = mem_ser_info_all[k]; 12133 for (i = 0; mem_ser_info[i].mem != INVALIDm; i++) { 12134 if (!SOC_MEM_IS_VALID(unit, mem_ser_info[i].mem)) { 12135 continue; 12136 } 12137 /* Skip the memory whose SER_RESPONSE not equal SER_NONE*/ 12138 if (SOC_MEM_SER_CORRECTION_TYPE(unit, mem_ser_info[i].mem) != 0) { 12139 continue; 12140 } 12141 12142 ecc_reg = mem_ser_info[i].ecc1b_ctrl.ctrl_type.en_reg; 12143 ecc_fld = mem_ser_info[i].ecc1b_ctrl.en_fld; 12144 12145 if (!soc_reg_field_valid(unit, ecc_reg, ecc_fld)) { 12146 continue; 12147 } 12148 12149 LOG_VERBOSE(BSL_LS_SOC_SER, 12150 (BSL_META_U(unit, 12151 "unit %d, MEM %50s REG %30s FIELD %40s\n"), 12152 unit, SOC_MEM_NAME(unit, mem_ser_info[i].mem), 12153 SOC_REG_NAME(unit, ecc_reg), 12154 SOC_FIELD_NAME(unit, ecc_fld))); 12155 12156 SOC_IF_ERROR_RETURN 12157 (soc_reg_field32_modify(unit, ecc_reg, REG_PORT_ANY, 12158 ecc_fld, value)); 12159 } 12160 } 12161 return SOC_E_NONE; 12162 } 12163 12164 /* 12165 * Function: 12166 * soc_th_ser_single_bit_error_enable_get 12167 * Purpose: 12168 * Get the status of single bit eror reporting for the memories which are 12169 * protected by ECC logic and whoes SER_RESPONSE is SER_NONE on TD2/TD2p chips 12170 * Parameters: 12171 * unit - (IN) Device Number 12172 * enable - (OUT) Enable/Disable 12173 * Returns: 12174 * SOC_E_NONE if get successfully, an error otherwise 12175 */ 12176 int soc_th_ser_single_bit_error_enable_get(int unit, int *enable) 12177 { 12178 soc_reg_t ecc_reg; 12179 soc_field_t ecc_fld; 12180 _soc_mem_ser_en_info_t *mem_ser_info = NULL; 12181 uint32 rval = 0, fld_value = 0, i; 12182 12183 mem_ser_info = SOC_MMU_MEM_SER_INFO(unit); 12184 12185 if (NULL == mem_ser_info) { 12186 /* If this is not TH or TH+, we won't be able to get the mem info */ 12187 return SOC_E_UNAVAIL; 12188 } 12189 12190 for (i = 0; mem_ser_info[i].mem != INVALIDm; i++) { 12191 if (!SOC_MEM_IS_VALID(unit, mem_ser_info[i].mem)) { 12192 continue; 12193 } 12194 /* Skip the memory whose SER_RESPONSE not equal SER_NONE*/ 12195 if (SOC_MEM_SER_CORRECTION_TYPE(unit, mem_ser_info[i].mem) != 0) { 12196 continue; 12197 } 12198 12199 ecc_reg = mem_ser_info[i].ecc1b_ctrl.ctrl_type.en_reg; 12200 ecc_fld = mem_ser_info[i].ecc1b_ctrl.en_fld; 12201 12202 if (soc_reg_field_valid(unit, ecc_reg, ecc_fld)) { 12203 SOC_IF_ERROR_RETURN 12204 (soc_reg32_get(unit, ecc_reg, REG_PORT_ANY, 0, &rval)); 12205 fld_value = soc_reg_field_get(unit, ecc_reg, rval, ecc_fld); 12206 break; 12207 } 12208 } 12209 12210 *enable = fld_value ? TRUE:FALSE; 12211 return SOC_E_NONE; 12212 } 12213 12214 #if defined(SER_TR_TEST_SUPPORT) 12215 12216 #define TR_MEM_NAME_SIZE_MAX 100 12217 #ifdef SOC_MEM_NAME 12218 #define TR_TEST_MEM_NAME_GET(_unit, _msg, _mem) do { \ 12219 const char *_mem_name = SOC_MEM_NAME(_unit_, _mem); \ 12220 if (sal_strlen(_mem_name) < TR_MEM_NAME_SIZE_MAX) { \ 12221 sal_strcpy(_msg, _mem_name); \ 12222 } \ 12223 } while (0) 12224 #else 12225 #define TR_TEST_MEM_NAME_GET(_unit, _msg, _mem) 12226 #endif 12227 12228 #define TR_TEST_MEM_PRINT(_unit, _msg, _mem) do { \ 12229 sal_sprintf(_msg, "Mem ID: %d", _mem); \ 12230 TR_TEST_MEM_NAME_GET(_unit, _msg, _mem); \ 12231 LOG_WARN(BSL_LS_SOC_SER, (BSL_META_U(_unit, \ 12232 "Memory %s is valid, but not currently testable.\n"), \ 12233 _msg)); \ 12234 } while (0) 12235 12236 #define _SER_TEST_MEM_TH_ALPM_MASK(num_uft_banks) \ 12237 (SOC_IS_TOMAHAWK2(unit) ? ((num_uft_banks) == 4? 0xFFFF : 0x7FFF) : \ 12238 ((num_uft_banks) == 4? 0x7FFF : 0x3FFF)) 12239 #define _SER_TEST_MEM_TH_ALPM_SHIFT(num_uft_banks) \ 12240 (SOC_IS_TOMAHAWK2(unit) ? ((num_uft_banks) == 4? 16 : 15) : \ 12241 ((num_uft_banks) == 4? 15 : 14)) 12242 12243 #define _SOC_TH_TR144_LONG_SLEEP_TIME_US 200000 12244 12245 int 12246 ser_test_th_mem_index_remap(int unit, ser_test_data_t *test_data, 12247 int *mem_has_ecc) 12248 { 12249 int num_uft_banks = 0; 12250 int uft_bkt_bank = 0; 12251 int uft_le_fv = 0; 12252 int uft_le_ecc = 0; 12253 12254 int remap_status = 0; /* no error */ 12255 12256 if ((NULL == test_data) || (NULL == mem_has_ecc)) { 12257 return SOC_E_PARAM; 12258 } 12259 if (!SOC_MEM_IS_VALID(unit, test_data->mem_fv)) { 12260 LOG_ERROR(BSL_LS_SOC_SER, 12261 (BSL_META_U(unit, 12262 "unit %d, mem %d is INVALID or not valid " 12263 "for this unit !!\n"), 12264 unit, test_data->mem_fv)); 12265 return SOC_E_UNAVAIL; 12266 } 12267 *mem_has_ecc = 0; 12268 test_data->mem = test_data->mem_fv; 12269 test_data->index = test_data->index_fv; 12270 12271 num_uft_banks = soc_th_get_alpm_banks(unit); 12272 switch (test_data->mem_fv) { 12273 case VLAN_XLATEm: 12274 case VLAN_MACm: 12275 test_data->mem = VLAN_XLATE_ECCm; 12276 *mem_has_ecc = 1; 12277 break; 12278 case EGR_VLAN_XLATEm: 12279 test_data->mem = EGR_VLAN_XLATE_ECCm; 12280 *mem_has_ecc = 1; 12281 break; 12282 case MPLS_ENTRYm: 12283 test_data->mem = MPLS_ENTRY_ECCm; 12284 *mem_has_ecc = 1; 12285 break; 12286 case L2Xm: 12287 case L2_ENTRY_ONLY_TILEm: 12288 case L2_ENTRY_TILEm: 12289 #ifdef BCM_TOMAHAWK3_SUPPORT 12290 if (SOC_IS_TOMAHAWK3(unit)) { 12291 test_data->mem = L2_ENTRY_ECCm; 12292 } else 12293 #endif 12294 { 12295 test_data->mem = L2_ENTRY_ONLY_ECCm; 12296 } 12297 *mem_has_ecc = 1; 12298 break; 12299 case L3_ENTRY_ONLYm: 12300 case L3_ENTRY_IPV4_UNICASTm: 12301 test_data->mem = L3_ENTRY_ONLY_ECCm; 12302 test_data->index = test_data->index_fv; 12303 *mem_has_ecc = 1; 12304 break; 12305 case L3_ENTRY_IPV4_MULTICASTm: 12306 case L3_ENTRY_IPV6_UNICASTm: 12307 test_data->mem = L3_ENTRY_ONLY_ECCm; 12308 test_data->index = test_data->index_fv*2; 12309 *mem_has_ecc = 1; 12310 break; 12311 case L3_ENTRY_IPV6_MULTICASTm: 12312 test_data->mem = L3_ENTRY_ONLY_ECCm; 12313 test_data->index = test_data->index_fv*4; 12314 *mem_has_ecc = 1; 12315 break; 12316 case EXACT_MATCH_2m: 12317 case EXACT_MATCH_2_PIPE0m: 12318 case EXACT_MATCH_2_PIPE1m: 12319 case EXACT_MATCH_2_PIPE2m: 12320 case EXACT_MATCH_2_PIPE3m: 12321 case EXACT_MATCH_2_ENTRY_ONLYm: 12322 case EXACT_MATCH_2_ENTRY_ONLY_PIPE0m: 12323 case EXACT_MATCH_2_ENTRY_ONLY_PIPE1m: 12324 case EXACT_MATCH_2_ENTRY_ONLY_PIPE2m: 12325 case EXACT_MATCH_2_ENTRY_ONLY_PIPE3m: 12326 #ifdef BCM_TOMAHAWK3_SUPPORT 12327 if (SOC_IS_TOMAHAWK3(unit)) { 12328 test_data->mem = EXACT_MATCH_ECCm; 12329 } else 12330 #endif 12331 { 12332 test_data->mem = FPEM_ECCm; 12333 } 12334 test_data->index = test_data->index_fv*2; 12335 *mem_has_ecc = 1; 12336 break; 12337 case EXACT_MATCH_4m: 12338 case EXACT_MATCH_4_PIPE0m: 12339 case EXACT_MATCH_4_PIPE1m: 12340 case EXACT_MATCH_4_PIPE2m: 12341 case EXACT_MATCH_4_PIPE3m: 12342 case EXACT_MATCH_4_ENTRY_ONLYm: 12343 case EXACT_MATCH_4_ENTRY_ONLY_PIPE0m: 12344 case EXACT_MATCH_4_ENTRY_ONLY_PIPE1m: 12345 case EXACT_MATCH_4_ENTRY_ONLY_PIPE2m: 12346 case EXACT_MATCH_4_ENTRY_ONLY_PIPE3m: 12347 #ifdef BCM_TOMAHAWK3_SUPPORT 12348 if (SOC_IS_TOMAHAWK3(unit)) { 12349 test_data->mem = EXACT_MATCH_ECCm; 12350 } else 12351 #endif 12352 { 12353 test_data->mem = FPEM_ECCm; 12354 } 12355 test_data->index = test_data->index_fv*4; 12356 *mem_has_ecc = 1; 12357 break; 12358 case L3_DEFIP_ALPM_IPV4m: /* 6:4 */ 12359 *mem_has_ecc = 1; 12360 test_data->mem = L3_DEFIP_ALPM_ECCm; 12361 uft_bkt_bank = test_data->index_fv & 12362 _SER_TEST_MEM_TH_ALPM_MASK(num_uft_banks); 12363 uft_le_fv = test_data->index_fv >> 12364 _SER_TEST_MEM_TH_ALPM_SHIFT(num_uft_banks); 12365 switch (uft_le_fv) { 12366 case 0: uft_le_ecc = 0; break; 12367 case 1: uft_le_ecc = 0; break; /* or 1 */ 12368 case 2: uft_le_ecc = 1; break; 12369 case 3: uft_le_ecc = 2; break; 12370 case 4: uft_le_ecc = 2; break; /* or 3 */ 12371 case 5: uft_le_ecc = 3; break; 12372 default: remap_status = SOC_E_PARAM; uft_le_ecc = uft_le_fv; break; 12373 } 12374 test_data->index = (uft_le_ecc << 12375 _SER_TEST_MEM_TH_ALPM_SHIFT(num_uft_banks)) + uft_bkt_bank; 12376 break; 12377 case L3_DEFIP_ALPM_IPV4_1m: /* 4:4 */ 12378 case L3_DEFIP_ALPM_IPV6_64m: 12379 *mem_has_ecc = 1; 12380 test_data->mem = L3_DEFIP_ALPM_ECCm; 12381 test_data->index = test_data->index_fv; 12382 break; 12383 case L3_DEFIP_ALPM_IPV6_64_1m: /* 3:4 */ 12384 *mem_has_ecc = 1; 12385 test_data->mem = L3_DEFIP_ALPM_ECCm; 12386 uft_bkt_bank = test_data->index_fv & 12387 _SER_TEST_MEM_TH_ALPM_MASK(num_uft_banks); 12388 uft_le_fv = test_data->index_fv >> 12389 _SER_TEST_MEM_TH_ALPM_SHIFT(num_uft_banks); 12390 switch (uft_le_fv) { 12391 case 0: uft_le_ecc = 0; break; /* or 1 */ 12392 case 1: uft_le_ecc = 1; break; /* or 2 */ 12393 case 2: uft_le_ecc = 2; break; /* or 3 */ 12394 default: remap_status = SOC_E_PARAM; uft_le_ecc = uft_le_fv; break; 12395 } 12396 test_data->index = (uft_le_ecc << 12397 _SER_TEST_MEM_TH_ALPM_SHIFT(num_uft_banks)) + uft_bkt_bank; 12398 break; 12399 case L3_DEFIP_ALPM_IPV6_128m: /* 2:4 */ 12400 *mem_has_ecc = 1; 12401 test_data->mem = L3_DEFIP_ALPM_ECCm; 12402 uft_bkt_bank = test_data->index_fv & 12403 _SER_TEST_MEM_TH_ALPM_MASK(num_uft_banks); 12404 uft_le_fv = test_data->index_fv >> 12405 _SER_TEST_MEM_TH_ALPM_SHIFT(num_uft_banks); 12406 switch (uft_le_fv) { 12407 case 0: uft_le_ecc = 0; break; /* or 1 */ 12408 case 1: uft_le_ecc = 2; break; /* or 3 */ 12409 default: remap_status = SOC_E_PARAM; uft_le_ecc = uft_le_fv; break; 12410 } 12411 test_data->index = (uft_le_ecc << 12412 _SER_TEST_MEM_TH_ALPM_SHIFT(num_uft_banks)) + uft_bkt_bank; 12413 break; 12414 case L3_DEFIP_ALPM_RAWm: /* 1:4 */ 12415 *mem_has_ecc = 1; 12416 test_data->mem = L3_DEFIP_ALPM_ECCm; 12417 uft_bkt_bank = test_data->index_fv & 12418 _SER_TEST_MEM_TH_ALPM_MASK(num_uft_banks); 12419 uft_le_fv = test_data->index_fv >> 12420 _SER_TEST_MEM_TH_ALPM_SHIFT(num_uft_banks); 12421 switch (uft_le_fv) { 12422 case 0: uft_le_ecc = 0; break; /* or 1,2,3 */ 12423 default: remap_status = SOC_E_PARAM; uft_le_ecc = uft_le_fv; break; 12424 } 12425 test_data->index = (uft_le_ecc << 12426 _SER_TEST_MEM_TH_ALPM_SHIFT(num_uft_banks)) + uft_bkt_bank; 12427 break; 12428 #ifdef BCM_TOMAHAWK2_SUPPORT 12429 case MMU_INTFO_TC2PRI_MAPPINGm: 12430 if (SOC_IS_TOMAHAWK2(unit)) { 12431 test_data->mem = MMU_INTFO_TC2PRI_MAPPING0m; 12432 } 12433 break; 12434 case ING_DNAT_ADDRESS_TYPEm: 12435 if (SOC_IS_TOMAHAWK2(unit)) { 12436 test_data->mem = ING_DNAT_ADDRESS_TYPE_ECCm; 12437 *mem_has_ecc = 1; 12438 } 12439 break; 12440 case EGR_VP_VLAN_MEMBERSHIPm: 12441 if (SOC_IS_TOMAHAWK2(unit)) { 12442 test_data->mem = EGR_VP_VLAN_MEMBERSHIP_ECCm; 12443 *mem_has_ecc = 1; 12444 } 12445 break; 12446 case ING_VP_VLAN_MEMBERSHIPm: 12447 if (SOC_IS_TOMAHAWK2(unit)) { 12448 test_data->mem = ING_VP_VLAN_MEMBERSHIP_ECCm; 12449 *mem_has_ecc = 1; 12450 } 12451 break; 12452 #endif 12453 #ifdef BCM_TOMAHAWK3_SUPPORT 12454 case L3_DEFIP_ALPM_LEVEL3m: 12455 if (SOC_IS_TOMAHAWK3(unit)) { 12456 test_data->mem = L3_DEFIP_ALPM_LEVEL3_ECCm; 12457 test_data->index = test_data->index_fv * 4; 12458 *mem_has_ecc = 1; 12459 } 12460 break; 12461 case L3_DEFIP_ALPM_LEVEL3_SINGLEm: 12462 if (SOC_IS_TOMAHAWK3(unit)) { 12463 test_data->mem = L3_DEFIP_ALPM_LEVEL3_ECCm; 12464 test_data->index = test_data->index_fv; 12465 *mem_has_ecc = 1; 12466 } 12467 break; 12468 case L3_DEFIP_ALPM_LEVEL2m: 12469 if (SOC_IS_TOMAHAWK3(unit)) { 12470 test_data->mem = L3_DEFIP_ALPM_LEVEL2_ECCm; 12471 test_data->index = test_data->index_fv * 4; 12472 *mem_has_ecc = 1; 12473 } 12474 break; 12475 case L3_DEFIP_ALPM_LEVEL2_SINGLEm: 12476 if (SOC_IS_TOMAHAWK3(unit)) { 12477 test_data->mem = L3_DEFIP_ALPM_LEVEL2_ECCm; 12478 test_data->index = test_data->index_fv; 12479 *mem_has_ecc = 1; 12480 } 12481 break; 12482 case L3_ENTRY_ONLY_SINGLEm: 12483 case L3_ENTRY_SINGLEm: 12484 if (SOC_IS_TOMAHAWK3(unit)) { 12485 test_data->mem = L3_ENTRY_ECCm; 12486 test_data->index = test_data->index_fv; 12487 *mem_has_ecc = 1; 12488 } 12489 break; 12490 case L3_ENTRY_ONLY_DOUBLEm: 12491 case L3_ENTRY_DOUBLEm: 12492 if (SOC_IS_TOMAHAWK3(unit)) { 12493 test_data->mem = L3_ENTRY_ECCm; 12494 test_data->index = test_data->index_fv*2; 12495 *mem_has_ecc = 1; 12496 } 12497 break; 12498 case L3_ENTRY_ONLY_QUADm: 12499 case L3_ENTRY_QUADm: 12500 if (SOC_IS_TOMAHAWK3(unit)) { 12501 test_data->mem = L3_ENTRY_ECCm; 12502 test_data->index = test_data->index_fv*4; 12503 *mem_has_ecc = 1; 12504 } 12505 break; 12506 case MPLS_ENTRY_SINGLEm: 12507 test_data->mem = MPLS_ENTRY_ECCm; 12508 test_data->index = test_data->index_fv; 12509 *mem_has_ecc = 1; 12510 break; 12511 #endif 12512 default: 12513 test_data->mem = test_data->mem_fv; 12514 test_data->index = test_data->index_fv; 12515 break; 12516 } 12517 if ((test_data->mem != test_data->mem_fv) || 12518 (test_data->index != test_data->index_fv)) { 12519 LOG_VERBOSE(BSL_LS_SOC_SER, 12520 (BSL_META_U(unit, 12521 "unit %d, ser_test_th_mem_index_remap: " 12522 "mem_fv %s, index_fv %0d, mem %s, index %0d, " 12523 "#uft_banks %0d, uft_bkt_bank %0d, uft_le_fv %0d, " 12524 "uft_le_ecc %0d, remap_status %0d \n"), 12525 unit, SOC_MEM_NAME(unit, test_data->mem_fv), test_data->index_fv, 12526 SOC_MEM_NAME(unit, test_data->mem), test_data->index, num_uft_banks, 12527 uft_bkt_bank, uft_le_fv, uft_le_ecc, remap_status)); 12528 } 12529 return remap_status; 12530 } 12531 12532 static soc_ser_test_functions_t ser_tomahawk_test_fun; 12533 12534 typedef struct ser_th_skipped_mem_s { 12535 soc_mem_t mem; 12536 soc_acc_type_t acc_type; 12537 int allow_error_inj; 12538 } ser_th_skipped_mem_t; 12539 12540 const ser_th_skipped_mem_t th_skipped_mems[] = { 12541 { VLAN_XLATE_ECCm, _SOC_ACC_TYPE_PIPE_ANY, 0 }, 12542 { MPLS_ENTRY_ECCm, _SOC_ACC_TYPE_PIPE_ANY, 0 }, 12543 { FPEM_ECCm, _SOC_ACC_TYPE_PIPE_ANY, 0 }, 12544 { FPEM_ECC_PIPE0m, _SOC_ACC_TYPE_PIPE_ANY, 0 }, 12545 { FPEM_ECC_PIPE1m, _SOC_ACC_TYPE_PIPE_ANY, 0 }, 12546 { FPEM_ECC_PIPE2m, _SOC_ACC_TYPE_PIPE_ANY, 0 }, 12547 { FPEM_ECC_PIPE3m, _SOC_ACC_TYPE_PIPE_ANY, 0 }, 12548 { L2_ENTRY_ONLY_ECCm, _SOC_ACC_TYPE_PIPE_ANY, 0 }, 12549 { L3_ENTRY_ONLY_ECCm, _SOC_ACC_TYPE_PIPE_ANY, 0 }, 12550 { L3_DEFIP_ALPM_ECCm, _SOC_ACC_TYPE_PIPE_ANY, 0 }, 12551 { EGR_VLAN_XLATE_ECCm, _SOC_ACC_TYPE_PIPE_ANY, 0 }, 12552 12553 { L2_BULKm, _SOC_ACC_TYPE_PIPE_ANY, 0 }, 12554 { L2_LEARN_INSERT_FAILUREm, _SOC_ACC_TYPE_PIPE_ANY, 0 }, 12555 12556 { L3_DEFIP_ALPM_IPV4m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12557 { L3_DEFIP_ALPM_IPV6_64_1m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12558 { L3_DEFIP_ALPM_RAWm, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12559 #ifdef BCM_TOMAHAWK3_SUPPORT 12560 { L3_DEFIP_ALPM_LEVEL2_SINGLEm, _SOC_UNIQUE_ACC_TYPE_PIPE_0, 1}, 12561 { L3_DEFIP_ALPM_LEVEL2_SINGLEm, _SOC_UNIQUE_ACC_TYPE_PIPE_1, 0}, 12562 { L3_DEFIP_ALPM_LEVEL2_SINGLEm, _SOC_UNIQUE_ACC_TYPE_PIPE_2, 0}, 12563 { L3_DEFIP_ALPM_LEVEL2_SINGLEm, _SOC_UNIQUE_ACC_TYPE_PIPE_3, 1}, 12564 { L3_DEFIP_ALPM_LEVEL2_SINGLEm, _SOC_UNIQUE_ACC_TYPE_PIPE_4, 1}, 12565 { L3_DEFIP_ALPM_LEVEL2_SINGLEm, _SOC_UNIQUE_ACC_TYPE_PIPE_5, 0}, 12566 { L3_DEFIP_ALPM_LEVEL2_SINGLEm, _SOC_UNIQUE_ACC_TYPE_PIPE_6, 0}, 12567 { L3_DEFIP_ALPM_LEVEL2_SINGLEm, _SOC_UNIQUE_ACC_TYPE_PIPE_7, 1}, 12568 { L3_DEFIP_ALPM_LEVEL2m, _SOC_UNIQUE_ACC_TYPE_PIPE_0, 1}, 12569 { L3_DEFIP_ALPM_LEVEL2m, _SOC_UNIQUE_ACC_TYPE_PIPE_1, 0}, 12570 { L3_DEFIP_ALPM_LEVEL2m, _SOC_UNIQUE_ACC_TYPE_PIPE_2, 0}, 12571 { L3_DEFIP_ALPM_LEVEL2m, _SOC_UNIQUE_ACC_TYPE_PIPE_3, 1}, 12572 { L3_DEFIP_ALPM_LEVEL2m, _SOC_UNIQUE_ACC_TYPE_PIPE_4, 1}, 12573 { L3_DEFIP_ALPM_LEVEL2m, _SOC_UNIQUE_ACC_TYPE_PIPE_5, 0}, 12574 { L3_DEFIP_ALPM_LEVEL2m, _SOC_UNIQUE_ACC_TYPE_PIPE_6, 0}, 12575 { L3_DEFIP_ALPM_LEVEL2m, _SOC_UNIQUE_ACC_TYPE_PIPE_7, 1}, 12576 { L3_DEFIP_ALPM_LEVEL2_ECCm, _SOC_UNIQUE_ACC_TYPE_PIPE_0, 1}, 12577 { L3_DEFIP_ALPM_LEVEL2_ECCm, _SOC_UNIQUE_ACC_TYPE_PIPE_1, 0}, 12578 { L3_DEFIP_ALPM_LEVEL2_ECCm, _SOC_UNIQUE_ACC_TYPE_PIPE_2, 0}, 12579 { L3_DEFIP_ALPM_LEVEL2_ECCm, _SOC_UNIQUE_ACC_TYPE_PIPE_3, 1}, 12580 { L3_DEFIP_ALPM_LEVEL2_ECCm, _SOC_UNIQUE_ACC_TYPE_PIPE_4, 1}, 12581 { L3_DEFIP_ALPM_LEVEL2_ECCm, _SOC_UNIQUE_ACC_TYPE_PIPE_5, 0}, 12582 { L3_DEFIP_ALPM_LEVEL2_ECCm, _SOC_UNIQUE_ACC_TYPE_PIPE_6, 0}, 12583 { L3_DEFIP_ALPM_LEVEL2_ECCm, _SOC_UNIQUE_ACC_TYPE_PIPE_7, 1}, 12584 { L3_DEFIP_ALPM_LEVEL3_SINGLEm, _SOC_UNIQUE_ACC_TYPE_PIPE_0, 1}, 12585 { L3_DEFIP_ALPM_LEVEL3_SINGLEm, _SOC_UNIQUE_ACC_TYPE_PIPE_1, 0}, 12586 { L3_DEFIP_ALPM_LEVEL3_SINGLEm, _SOC_UNIQUE_ACC_TYPE_PIPE_2, 0}, 12587 { L3_DEFIP_ALPM_LEVEL3_SINGLEm, _SOC_UNIQUE_ACC_TYPE_PIPE_3, 0}, 12588 { L3_DEFIP_ALPM_LEVEL3_SINGLEm, _SOC_UNIQUE_ACC_TYPE_PIPE_4, 1}, 12589 { L3_DEFIP_ALPM_LEVEL3_SINGLEm, _SOC_UNIQUE_ACC_TYPE_PIPE_5, 0}, 12590 { L3_DEFIP_ALPM_LEVEL3_SINGLEm, _SOC_UNIQUE_ACC_TYPE_PIPE_6, 0}, 12591 { L3_DEFIP_ALPM_LEVEL3_SINGLEm, _SOC_UNIQUE_ACC_TYPE_PIPE_7, 0}, 12592 { L3_DEFIP_ALPM_LEVEL3m, _SOC_UNIQUE_ACC_TYPE_PIPE_0, 1}, 12593 { L3_DEFIP_ALPM_LEVEL3m, _SOC_UNIQUE_ACC_TYPE_PIPE_1, 0}, 12594 { L3_DEFIP_ALPM_LEVEL3m, _SOC_UNIQUE_ACC_TYPE_PIPE_2, 0}, 12595 { L3_DEFIP_ALPM_LEVEL3m, _SOC_UNIQUE_ACC_TYPE_PIPE_3, 0}, 12596 { L3_DEFIP_ALPM_LEVEL3m, _SOC_UNIQUE_ACC_TYPE_PIPE_4, 1}, 12597 { L3_DEFIP_ALPM_LEVEL3m, _SOC_UNIQUE_ACC_TYPE_PIPE_5, 0}, 12598 { L3_DEFIP_ALPM_LEVEL3m, _SOC_UNIQUE_ACC_TYPE_PIPE_6, 0}, 12599 { L3_DEFIP_ALPM_LEVEL3m, _SOC_UNIQUE_ACC_TYPE_PIPE_7, 0}, 12600 { L3_DEFIP_ALPM_LEVEL3_ECCm, _SOC_UNIQUE_ACC_TYPE_PIPE_0, 1}, 12601 { L3_DEFIP_ALPM_LEVEL3_ECCm, _SOC_UNIQUE_ACC_TYPE_PIPE_1, 0}, 12602 { L3_DEFIP_ALPM_LEVEL3_ECCm, _SOC_UNIQUE_ACC_TYPE_PIPE_2, 0}, 12603 { L3_DEFIP_ALPM_LEVEL3_ECCm, _SOC_UNIQUE_ACC_TYPE_PIPE_3, 0}, 12604 { L3_DEFIP_ALPM_LEVEL3_ECCm, _SOC_UNIQUE_ACC_TYPE_PIPE_4, 1}, 12605 { L3_DEFIP_ALPM_LEVEL3_ECCm, _SOC_UNIQUE_ACC_TYPE_PIPE_5, 0}, 12606 { L3_DEFIP_ALPM_LEVEL3_ECCm, _SOC_UNIQUE_ACC_TYPE_PIPE_6, 0}, 12607 { L3_DEFIP_ALPM_LEVEL3_ECCm, _SOC_UNIQUE_ACC_TYPE_PIPE_7, 0}, 12608 { EGR_L3_NEXT_HOPm, _SOC_UNIQUE_ACC_TYPE_PIPE_1, 0}, 12609 { EGR_L3_NEXT_HOPm, _SOC_UNIQUE_ACC_TYPE_PIPE_2, 0}, 12610 { EGR_L3_NEXT_HOPm, _SOC_UNIQUE_ACC_TYPE_PIPE_5, 0}, 12611 { EGR_L3_NEXT_HOPm, _SOC_UNIQUE_ACC_TYPE_PIPE_6, 0}, 12612 { EXACT_MATCH_2m, _SOC_UNIQUE_ACC_TYPE_PIPE_1, 0}, 12613 { EXACT_MATCH_2m, _SOC_UNIQUE_ACC_TYPE_PIPE_2, 0}, 12614 { EXACT_MATCH_2m, _SOC_UNIQUE_ACC_TYPE_PIPE_3, 0}, 12615 { EXACT_MATCH_2m, _SOC_UNIQUE_ACC_TYPE_PIPE_5, 0}, 12616 { EXACT_MATCH_2m, _SOC_UNIQUE_ACC_TYPE_PIPE_6, 0}, 12617 { EXACT_MATCH_2m, _SOC_UNIQUE_ACC_TYPE_PIPE_7, 0}, 12618 { EXACT_MATCH_4m, _SOC_UNIQUE_ACC_TYPE_PIPE_1, 0}, 12619 { EXACT_MATCH_4m, _SOC_UNIQUE_ACC_TYPE_PIPE_2, 0}, 12620 { EXACT_MATCH_4m, _SOC_UNIQUE_ACC_TYPE_PIPE_3, 0}, 12621 { EXACT_MATCH_4m, _SOC_UNIQUE_ACC_TYPE_PIPE_5, 0}, 12622 { EXACT_MATCH_4m, _SOC_UNIQUE_ACC_TYPE_PIPE_6, 0}, 12623 { EXACT_MATCH_4m, _SOC_UNIQUE_ACC_TYPE_PIPE_7, 0}, 12624 { EXACT_MATCH_ECCm, _SOC_UNIQUE_ACC_TYPE_PIPE_1, 0}, 12625 { EXACT_MATCH_ECCm, _SOC_UNIQUE_ACC_TYPE_PIPE_2, 0}, 12626 { EXACT_MATCH_ECCm, _SOC_UNIQUE_ACC_TYPE_PIPE_3, 0}, 12627 { EXACT_MATCH_ECCm, _SOC_UNIQUE_ACC_TYPE_PIPE_5, 0}, 12628 { EXACT_MATCH_ECCm, _SOC_UNIQUE_ACC_TYPE_PIPE_6, 0}, 12629 { EXACT_MATCH_ECCm, _SOC_UNIQUE_ACC_TYPE_PIPE_7, 0}, 12630 #endif 12631 { IS_TDM_CALENDAR0m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12632 { IS_TDM_CALENDAR0_PIPE0m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12633 { IS_TDM_CALENDAR0_PIPE1m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12634 { IS_TDM_CALENDAR0_PIPE2m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12635 { IS_TDM_CALENDAR0_PIPE3m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12636 { IS_TDM_CALENDAR1m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12637 { IS_TDM_CALENDAR1_PIPE0m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12638 { IS_TDM_CALENDAR1_PIPE1m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12639 { IS_TDM_CALENDAR1_PIPE2m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12640 { IS_TDM_CALENDAR1_PIPE3m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12641 12642 12643 { MMU_WRED_PORT_SP_SHARED_COUNT_XPE0_PIPE0m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12644 { MMU_WRED_PORT_SP_SHARED_COUNT_XPE0_PIPE1m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12645 { MMU_WRED_PORT_SP_SHARED_COUNT_XPE1_PIPE2m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12646 { MMU_WRED_PORT_SP_SHARED_COUNT_XPE1_PIPE3m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12647 { MMU_WRED_PORT_SP_SHARED_COUNT_XPE2_PIPE0m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12648 { MMU_WRED_PORT_SP_SHARED_COUNT_XPE2_PIPE1m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12649 { MMU_WRED_PORT_SP_SHARED_COUNT_XPE3_PIPE2m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12650 { MMU_WRED_PORT_SP_SHARED_COUNT_XPE3_PIPE3m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12651 12652 /* These memories will be accessed by HW, so skipped for TR 144 */ 12653 { TDM_CALENDAR0m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12654 { TDM_CALENDAR0_PIPE0m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12655 { TDM_CALENDAR0_PIPE1m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12656 { TDM_CALENDAR0_PIPE2m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12657 { TDM_CALENDAR0_PIPE3m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12658 #ifdef BCM_TOMAHAWK2_SUPPORT 12659 { TDM_CALENDAR1m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12660 { TDM_CALENDAR1_PIPE0m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12661 { TDM_CALENDAR1_PIPE1m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12662 { TDM_CALENDAR1_PIPE2m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12663 { TDM_CALENDAR1_PIPE3m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12664 { MMU_CFAP_BANK0m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12665 { MMU_CFAP_BANK0_XPE0m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12666 { MMU_CFAP_BANK0_XPE1m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12667 { MMU_CFAP_BANK0_XPE2m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12668 { MMU_CFAP_BANK0_XPE3m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12669 { MMU_CFAP_BANK1m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12670 { MMU_CFAP_BANK1_XPE0m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12671 { MMU_CFAP_BANK1_XPE1m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12672 { MMU_CFAP_BANK1_XPE2m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12673 { MMU_CFAP_BANK1_XPE3m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12674 { MMU_CFAP_BANK2m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12675 { MMU_CFAP_BANK2_XPE0m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12676 { MMU_CFAP_BANK2_XPE1m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12677 { MMU_CFAP_BANK2_XPE2m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12678 { MMU_CFAP_BANK2_XPE3m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12679 { MMU_CFAP_BANK3m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12680 { MMU_CFAP_BANK3_XPE0m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12681 { MMU_CFAP_BANK3_XPE1m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12682 { MMU_CFAP_BANK3_XPE2m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12683 { MMU_CFAP_BANK3_XPE3m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12684 { MMU_CFAP_BANK4m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12685 { MMU_CFAP_BANK4_XPE0m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12686 { MMU_CFAP_BANK4_XPE1m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12687 { MMU_CFAP_BANK4_XPE2m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12688 { MMU_CFAP_BANK4_XPE3m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12689 { MMU_CFAP_BANK5m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12690 { MMU_CFAP_BANK5_XPE0m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12691 { MMU_CFAP_BANK5_XPE1m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12692 { MMU_CFAP_BANK5_XPE2m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12693 { MMU_CFAP_BANK5_XPE3m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12694 { MMU_CFAP_BANK6m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12695 { MMU_CFAP_BANK6_XPE0m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12696 { MMU_CFAP_BANK6_XPE1m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12697 { MMU_CFAP_BANK6_XPE2m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12698 { MMU_CFAP_BANK6_XPE3m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12699 { MMU_CFAP_BANK7m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12700 { MMU_CFAP_BANK7_XPE0m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12701 { MMU_CFAP_BANK7_XPE1m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12702 { MMU_CFAP_BANK7_XPE2m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12703 { MMU_CFAP_BANK7_XPE3m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12704 { MMU_CFAP_BANK8m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12705 { MMU_CFAP_BANK8_XPE0m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12706 { MMU_CFAP_BANK8_XPE1m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12707 { MMU_CFAP_BANK8_XPE2m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12708 { MMU_CFAP_BANK8_XPE3m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12709 { MMU_CFAP_BANK9m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12710 { MMU_CFAP_BANK9_XPE0m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12711 { MMU_CFAP_BANK9_XPE1m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12712 { MMU_CFAP_BANK9_XPE2m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12713 { MMU_CFAP_BANK9_XPE3m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12714 { MMU_CFAP_BANK10m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12715 { MMU_CFAP_BANK10_XPE0m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12716 { MMU_CFAP_BANK10_XPE1m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12717 { MMU_CFAP_BANK10_XPE2m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12718 { MMU_CFAP_BANK10_XPE3m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12719 { MMU_CFAP_BANK11m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12720 { MMU_CFAP_BANK11_XPE0m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12721 { MMU_CFAP_BANK11_XPE1m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12722 { MMU_CFAP_BANK11_XPE2m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12723 { MMU_CFAP_BANK11_XPE3m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12724 { MMU_CFAP_BANK12m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12725 { MMU_CFAP_BANK12_XPE0m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12726 { MMU_CFAP_BANK12_XPE1m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12727 { MMU_CFAP_BANK12_XPE2m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12728 { MMU_CFAP_BANK12_XPE3m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12729 { MMU_CFAP_BANK13m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12730 { MMU_CFAP_BANK13_XPE0m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12731 { MMU_CFAP_BANK13_XPE1m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12732 { MMU_CFAP_BANK13_XPE2m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12733 { MMU_CFAP_BANK13_XPE3m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12734 { REPLICATION_FIFO_BANK0m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12735 { REPLICATION_FIFO_BANK0_XPE0m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12736 { REPLICATION_FIFO_BANK0_XPE1m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12737 { REPLICATION_FIFO_BANK0_XPE2m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12738 { REPLICATION_FIFO_BANK0_XPE3m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12739 { REPLICATION_FIFO_BANK1m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12740 { REPLICATION_FIFO_BANK1_XPE0m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12741 { REPLICATION_FIFO_BANK1_XPE1m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12742 { REPLICATION_FIFO_BANK1_XPE2m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12743 { REPLICATION_FIFO_BANK1_XPE3m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12744 { MMU_ENQS_PBI_DBm, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12745 { MMU_ENQS_PBI_DB_SED0_PIPE0m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12746 { MMU_ENQS_PBI_DB_SED0_PIPE1m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12747 { MMU_ENQS_PBI_DB_SED0_PIPE2m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12748 { MMU_ENQS_PBI_DB_SED0_PIPE3m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12749 { MMU_ENQS_PBI_DB_SED1_PIPE0m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12750 { MMU_ENQS_PBI_DB_SED1_PIPE1m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12751 { MMU_ENQS_PBI_DB_SED1_PIPE2m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12752 { MMU_ENQS_PBI_DB_SED1_PIPE3m, _SOC_ACC_TYPE_PIPE_ANY, 1 }, 12753 #endif 12754 12755 12756 /* End */ 12757 { INVALIDm } 12758 }; 12759 12760 STATIC soc_acc_type_t 12761 _soc_tomahawk_pipe_to_acc_type(int pipe) 12762 { 12763 soc_acc_type_t rv; 12764 switch (pipe) { 12765 case SOC_PIPE_SELECT_ANY: 12766 case SOC_PIPE_SELECT_0: rv = _SOC_UNIQUE_ACC_TYPE_PIPE_0; break; 12767 case SOC_PIPE_SELECT_1: rv = _SOC_UNIQUE_ACC_TYPE_PIPE_1; break; 12768 case SOC_PIPE_SELECT_2: rv = _SOC_UNIQUE_ACC_TYPE_PIPE_2; break; 12769 case SOC_PIPE_SELECT_3: rv = _SOC_UNIQUE_ACC_TYPE_PIPE_3; break; 12770 case SOC_PIPE_SELECT_4: rv = _SOC_UNIQUE_ACC_TYPE_PIPE_4; break; 12771 case SOC_PIPE_SELECT_5: rv = _SOC_UNIQUE_ACC_TYPE_PIPE_5; break; 12772 case SOC_PIPE_SELECT_6: rv = _SOC_UNIQUE_ACC_TYPE_PIPE_6; break; 12773 case SOC_PIPE_SELECT_7: rv = _SOC_UNIQUE_ACC_TYPE_PIPE_7; break; 12774 default: rv =_SOC_ACC_TYPE_PIPE_ALL; break; 12775 } 12776 return rv; 12777 /* For TH, ONLY possible values of test_data->acc_type 12778 * are: ACC_TYPE_PIPE_0, 1, 2, 3, ALL 12779 */ 12780 } 12781 12782 STATIC soc_pipe_select_t 12783 _soc_tomahawk_acc_type_to_pipe(soc_acc_type_t acc_type) 12784 { 12785 soc_pipe_select_t rv; 12786 switch (acc_type) { 12787 case _SOC_UNIQUE_ACC_TYPE_PIPE_0: rv = SOC_PIPE_SELECT_0; break; 12788 case _SOC_UNIQUE_ACC_TYPE_PIPE_1: rv = SOC_PIPE_SELECT_1; break; 12789 case _SOC_UNIQUE_ACC_TYPE_PIPE_2: rv = SOC_PIPE_SELECT_2; break; 12790 case _SOC_UNIQUE_ACC_TYPE_PIPE_3: rv = SOC_PIPE_SELECT_3; break; 12791 case _SOC_UNIQUE_ACC_TYPE_PIPE_4: rv = SOC_PIPE_SELECT_4; break; 12792 case _SOC_UNIQUE_ACC_TYPE_PIPE_5: rv = SOC_PIPE_SELECT_5; break; 12793 case _SOC_UNIQUE_ACC_TYPE_PIPE_6: rv = SOC_PIPE_SELECT_6; break; 12794 case _SOC_UNIQUE_ACC_TYPE_PIPE_7: rv = SOC_PIPE_SELECT_7; break; 12795 case _SOC_ACC_TYPE_PIPE_ANY: rv = SOC_PIPE_SELECT_ANY; break; 12796 default: rv = SOC_PIPE_SELECT_ALL; break; 12797 } 12798 return rv; 12799 } 12800 12801 STATIC int 12802 soc_tomahawk_pipe_select(int unit, int egress, int pipe) 12803 { 12804 soc_reg_t reg; 12805 12806 reg = egress ? EGR_SBS_CONTROLr : SBS_CONTROLr; 12807 if ((pipe >= 0) && (pipe <= 3)) { 12808 return soc_reg_field32_modify(unit, reg, REG_PORT_ANY, PIPE_SELECTf, 12809 pipe); 12810 } else { 12811 return soc_reg_field32_modify(unit, reg, REG_PORT_ANY, PIPE_SELECTf, 0); 12812 } 12813 } 12814 12815 STATIC soc_error_t 12816 soc_th_parity_control_reg_set(int unit, ser_test_data_t *test_data, int enable) 12817 { 12818 12819 uint32 rval; 12820 uint64 regData; 12821 12822 SOC_IF_ERROR_RETURN 12823 (soc_reg32_get(unit, test_data->parity_enable_reg, test_data->port, 0, 12824 &rval)); 12825 LOG_VERBOSE(BSL_LS_SOC_SER, 12826 (BSL_META_U(unit, 12827 "soc_th_parity_control_reg_set READ: reg %s, rval_rdat = 0x%x, bit %d \n"), 12828 SOC_REG_NAME(unit, test_data->parity_enable_reg), 12829 rval, 12830 test_data->tcam_parity_bit 12831 )); 12832 if (enable) { 12833 rval |= (1 << test_data->tcam_parity_bit); 12834 } else { 12835 rval &= ~(1 << test_data->tcam_parity_bit); 12836 } 12837 LOG_VERBOSE(BSL_LS_SOC_SER, 12838 (BSL_META_U(unit, 12839 "soc_th_parity_control_reg_set WROTE: reg %s, rval_wdat = 0x%x, bit %d \n"), 12840 SOC_REG_NAME(unit, test_data->parity_enable_reg), 12841 rval, 12842 test_data->tcam_parity_bit 12843 )); 12844 COMPILER_64_SET(regData, 0, rval); 12845 return soc_reg_set(unit, test_data->parity_enable_reg, test_data->port, 0, 12846 regData); 12847 } 12848 12849 STATIC soc_error_t 12850 _ser_th_ser_support_mem_found(int unit, soc_mem_t mem, 12851 _soc_mem_ser_en_info_t *ser_info_list) 12852 { 12853 int i = 0; 12854 12855 for (i = 0; ser_info_list[i].mem != INVALIDm; i++) { 12856 if ((ser_info_list[i].mem == mem) && 12857 (soc_mem_index_count(unit, mem))) { 12858 return SOC_E_NONE; /* found */ 12859 } 12860 } 12861 12862 return SOC_E_UNAVAIL; 12863 } 12864 12865 12866 STATIC soc_error_t 12867 _ser_th_ser_error_injection_support(int unit, soc_mem_t mem, 12868 int pipe_target) 12869 { 12870 int rv = SOC_E_UNAVAIL; 12871 int i, p; 12872 uint32 rval; 12873 _soc_generic_ser_info_t *tcams = _soc_th_tcam_ser_info[unit]; 12874 12875 soc_acc_type_t soc_acc_type_target = 12876 _soc_tomahawk_pipe_to_acc_type(pipe_target); 12877 12878 if (!SOC_MEM_IS_VALID(unit, mem) || 12879 (SOC_MEM_INFO(unit, mem).flags & SOC_MEM_FLAG_SER_PARITY_ENABLE_SKIP)) { 12880 LOG_ERROR(BSL_LS_SOC_SER, 12881 (BSL_META_U(unit, 12882 "unit %d, mem %s is INVALID or not valid " 12883 "or parity is disabled for this mem !!\n"), 12884 unit, SOC_MEM_NAME(unit,mem))); 12885 return rv; 12886 } 12887 12888 /* Check if memory is listed in skipped mems structure */ 12889 for (i = 0; th_skipped_mems[i].mem != INVALIDm; i++) { 12890 if ((th_skipped_mems[i].mem == mem) && 12891 ((_SOC_ACC_TYPE_PIPE_ANY == th_skipped_mems[i].acc_type) || 12892 (th_skipped_mems[i].acc_type == soc_acc_type_target))) { 12893 if (th_skipped_mems[i].allow_error_inj) { 12894 return SOC_E_NONE; 12895 } else { 12896 return rv; 12897 } 12898 } 12899 } 12900 12901 #ifdef BCM_TOMAHAWK2_SUPPORT 12902 if (SOC_IS_TOMAHAWK2(unit) && soc_feature(unit, soc_feature_tcam_scan_engine)) { 12903 rv = _soc_th2_ser_tcam_wrapper_found(mem); 12904 if(rv == SOC_E_NONE) { 12905 return rv; 12906 } 12907 } 12908 #endif 12909 12910 #ifdef BCM_TOMAHAWK3_SUPPORT 12911 if (SOC_IS_TOMAHAWK3(unit) && soc_feature(unit, soc_feature_tcam_scan_engine)) { 12912 rv = _soc_th3_ser_tcam_wrapper_found(mem); 12913 if(rv == SOC_E_NONE) { 12914 return rv; 12915 } 12916 } 12917 #endif 12918 /* Search TCAMs */ 12919 if (SOC_REG_IS_VALID(unit, SER_RANGE_ENABLEr)) { 12920 SOC_IF_ERROR_RETURN 12921 (soc_reg32_get(unit, SER_RANGE_ENABLEr, REG_PORT_ANY, 0, &rval)); 12922 for (i = 0; tcams[i].mem != INVALIDm; i++) { 12923 if (tcams[i].mem == mem) { 12924 if (((rval >> tcams[i].ser_hw_index) & 0x1) == 0) { 12925 return rv; /* matched mem but ser_detection is disabled */ 12926 } 12927 return SOC_E_NONE; /* found */ 12928 } 12929 if (SOC_MEM_UNIQUE_ACC(unit, tcams[i].mem) != NULL) { 12930 for (p = 0; p < NUM_PIPE(unit); p++) { 12931 if (SOC_MEM_UNIQUE_ACC(unit, tcams[i].mem)[p] == mem) { 12932 if (((rval >> (tcams[i].ser_hw_index + 1)) & 0x1) == 0) { 12933 return rv; /* matched mem but ser_detection is disabled */ 12934 } 12935 return SOC_E_NONE; /* found */ 12936 } 12937 } 12938 } 12939 } 12940 } 12941 12942 /* Search for mems listed in: 12943 * _soc_bcm56960_a0_ip_mem_ser_info, 12944 * _soc_bcm56960_a0_ep_mem_ser_info, 12945 * _soc_bcm56960_a0_mmu_mem_ser_info, 12946 */ 12947 rv = _ser_th_ser_support_mem_found(unit, mem, SOC_IP_MEM_SER_INFO(unit)); 12948 if(rv == SOC_E_NONE) { 12949 return rv; 12950 } 12951 rv = _ser_th_ser_support_mem_found(unit, mem, SOC_EP_MEM_SER_INFO(unit)); 12952 if(rv == SOC_E_NONE) { 12953 return rv; 12954 } 12955 rv = _ser_th_ser_support_mem_found(unit, mem, SOC_MMU_MEM_SER_INFO(unit)); 12956 if(rv == SOC_E_NONE) { 12957 return rv; 12958 } 12959 return rv; 12960 } 12961 12962 STATIC soc_error_t 12963 _ser_th_correction_info_get(int unit, 12964 ser_correction_info_t *corr_info) 12965 { 12966 if (!SOC_MEM_IS_VALID(unit, corr_info->inject_mem)) { 12967 LOG_ERROR(BSL_LS_SOC_SER, 12968 (BSL_META_U(unit, 12969 "unit %d, mem %d is INVALID or not valid " 12970 "for this unit !!\n"), 12971 unit, corr_info->inject_mem)); 12972 return SOC_E_UNAVAIL; 12973 } 12974 switch (corr_info->inject_mem) { 12975 /* compare index only */ 12976 case VLAN_MACm: 12977 case VLAN_XLATEm: 12978 case EGR_VLAN_XLATEm: 12979 case MPLS_ENTRYm: 12980 case MODPORT_MAP_M0m: 12981 case MODPORT_MAP_M1m: 12982 case MODPORT_MAP_M2m: 12983 case MODPORT_MAP_M3m: 12984 case L2_ENTRY_TILEm: 12985 case L2_ENTRY_ONLY_TILEm: 12986 case L3_ENTRY_ONLYm: 12987 case L3_ENTRY_IPV4_UNICASTm: 12988 corr_info->compare_mem = 0; 12989 corr_info->compare_index = 1; 12990 break; 12991 12992 /* must NOT compare view or index */ 12993 case L3_ENTRY_IPV4_MULTICASTm: 12994 case L3_ENTRY_IPV6_UNICASTm: 12995 case L3_ENTRY_IPV6_MULTICASTm: 12996 case L3_DEFIP_ALPM_IPV4m: 12997 case L3_DEFIP_ALPM_IPV4_1m: 12998 case L3_DEFIP_ALPM_IPV6_64m: 12999 case L3_DEFIP_ALPM_IPV6_64_1m: 13000 case L3_DEFIP_ALPM_IPV6_128m: 13001 case L3_DEFIP_ALPM_RAWm: 13002 case EXACT_MATCH_2m: 13003 case EXACT_MATCH_2_ENTRY_ONLYm: 13004 case EXACT_MATCH_4m: 13005 case EXACT_MATCH_4_ENTRY_ONLYm: 13006 case FPEM_LPm: 13007 corr_info->compare_mem = 0; 13008 corr_info->compare_index = 0; 13009 break; 13010 13011 /* can compare both view and index */ 13012 default: 13013 corr_info->compare_mem = 1; 13014 corr_info->compare_index = 1; 13015 break; 13016 } 13017 13018 LOG_VERBOSE(BSL_LS_SOC_SER, 13019 (BSL_META_U(unit, 13020 "==== predict: mem = %s, " 13021 "compare_mem,index = %d,%d\n"), 13022 SOC_MEM_NAME(unit, corr_info->inject_mem), 13023 corr_info->compare_mem, 13024 corr_info->compare_index)); 13025 13026 return SOC_E_NONE; 13027 } 13028 13029 typedef struct ser_th_mems_test_field_s { 13030 soc_mem_t mem; 13031 soc_acc_type_t acc_type; 13032 soc_field_t test_field; 13033 } ser_th_mems_test_field_t; 13034 13035 const ser_th_mems_test_field_t th_mems_test_field[] = { 13036 /* mem with acc_type=data_split, has separate parity field for each pipe */ 13037 { EGR_VLAN_STGm, _SOC_UNIQUE_ACC_TYPE_PIPE_0, EVEN_EGR_VLAN_STG_PARITY_P0f }, 13038 { EGR_VLAN_STGm, _SOC_UNIQUE_ACC_TYPE_PIPE_1, EVEN_EGR_VLAN_STG_PARITY_P1f }, 13039 { EGR_VLAN_STGm, _SOC_UNIQUE_ACC_TYPE_PIPE_2, EVEN_EGR_VLAN_STG_PARITY_P2f }, 13040 { EGR_VLAN_STGm, _SOC_UNIQUE_ACC_TYPE_PIPE_3, EVEN_EGR_VLAN_STG_PARITY_P3f }, 13041 13042 /* mem with acc_type=data_split, has separate parity field for each pipe */ 13043 { SRC_MODID_INGRESS_BLOCKm, _SOC_UNIQUE_ACC_TYPE_PIPE_0, EVEN_PBM_PARITY_P0f }, 13044 { SRC_MODID_INGRESS_BLOCKm, _SOC_UNIQUE_ACC_TYPE_PIPE_1, EVEN_PBM_PARITY_P1f }, 13045 { SRC_MODID_INGRESS_BLOCKm, _SOC_UNIQUE_ACC_TYPE_PIPE_2, EVEN_PBM_PARITY_P2f }, 13046 { SRC_MODID_INGRESS_BLOCKm, _SOC_UNIQUE_ACC_TYPE_PIPE_3, EVEN_PBM_PARITY_P3f }, 13047 13048 { INVALIDm, _SOC_ACC_TYPE_PIPE_ANY, INVALIDf } 13049 }; 13050 13051 #ifdef BCM_TOMAHAWK2_SUPPORT 13052 const ser_th_mems_test_field_t th2_mems_test_field[] = { 13053 /* mem with acc_type=data_split, has separate parity field for each pipe */ 13054 { EGR_VLAN_STGm, _SOC_UNIQUE_ACC_TYPE_PIPE_0, ECCP_0f }, 13055 { EGR_VLAN_STGm, _SOC_UNIQUE_ACC_TYPE_PIPE_1, ECCP_1f }, 13056 { EGR_VLAN_STGm, _SOC_UNIQUE_ACC_TYPE_PIPE_2, ECCP_2f }, 13057 { EGR_VLAN_STGm, _SOC_UNIQUE_ACC_TYPE_PIPE_3, ECCP_3f }, 13058 13059 /* mem with acc_type=data_split, has separate parity field for each pipe */ 13060 { SRC_MODID_INGRESS_BLOCKm, _SOC_UNIQUE_ACC_TYPE_PIPE_0, ECCP_P0f }, 13061 { SRC_MODID_INGRESS_BLOCKm, _SOC_UNIQUE_ACC_TYPE_PIPE_1, ECCP_P1f }, 13062 { SRC_MODID_INGRESS_BLOCKm, _SOC_UNIQUE_ACC_TYPE_PIPE_2, ECCP_P2f }, 13063 { SRC_MODID_INGRESS_BLOCKm, _SOC_UNIQUE_ACC_TYPE_PIPE_3, ECCP_P3f }, 13064 13065 { INVALIDm, _SOC_ACC_TYPE_PIPE_ANY, INVALIDf } 13066 }; 13067 #endif 13068 13069 #ifdef BCM_TOMAHAWK3_SUPPORT 13070 const ser_th_mems_test_field_t th3_mems_test_field[] = { 13071 /* mem with acc_type=data_split, has separate parity field for each pipe */ 13072 { STG_TABm, _SOC_UNIQUE_ACC_TYPE_PIPE_0, ECCP_P0f }, 13073 { STG_TABm, _SOC_UNIQUE_ACC_TYPE_PIPE_1, ECCP_P1f }, 13074 { STG_TABm, _SOC_UNIQUE_ACC_TYPE_PIPE_2, ECCP_P2f }, 13075 { STG_TABm, _SOC_UNIQUE_ACC_TYPE_PIPE_3, ECCP_P3f }, 13076 { STG_TABm, _SOC_UNIQUE_ACC_TYPE_PIPE_4, ECCP_P4f }, 13077 { STG_TABm, _SOC_UNIQUE_ACC_TYPE_PIPE_5, ECCP_P5f }, 13078 { STG_TABm, _SOC_UNIQUE_ACC_TYPE_PIPE_6, ECCP_P6f }, 13079 { STG_TABm, _SOC_UNIQUE_ACC_TYPE_PIPE_7, ECCP_P7f }, 13080 13081 { INVALIDm, _SOC_ACC_TYPE_PIPE_ANY, INVALIDf } 13082 }; 13083 #endif 13084 STATIC void 13085 _soc_ser_find_test_field(int unit, soc_mem_t mem, 13086 soc_acc_type_t soc_acc_type_target, 13087 soc_field_t *test_field) 13088 { 13089 int i; 13090 const ser_th_mems_test_field_t *mems_test_field = th_mems_test_field; 13091 13092 #ifdef BCM_TOMAHAWK2_SUPPORT 13093 if (SOC_IS_TOMAHAWK2(unit)) { 13094 mems_test_field = th2_mems_test_field; 13095 } 13096 #endif 13097 #ifdef BCM_TOMAHAWK3_SUPPORT 13098 if (SOC_IS_TOMAHAWK3(unit)) { 13099 mems_test_field = th3_mems_test_field; 13100 } 13101 #endif 13102 for (i = 0; mems_test_field[i].mem != INVALIDm; i++) { 13103 if ((mems_test_field[i].mem == mem) && 13104 ((mems_test_field[i].acc_type == soc_acc_type_target) || 13105 (mems_test_field[i].acc_type == _SOC_ACC_TYPE_PIPE_ANY)) 13106 ) { 13107 *test_field = mems_test_field[i].test_field; 13108 LOG_VERBOSE(BSL_LS_SOC_SER, 13109 (BSL_META_U(unit, 13110 "===== Selected field %s for Memory %s \n"), 13111 SOC_FIELD_NAME(unit, *test_field), 13112 SOC_MEM_NAME(unit,mem))); 13113 break; 13114 } 13115 } 13116 return; 13117 } 13118 13119 /* 13120 * Function: 13121 * _soc_tomahawk_perform_ser_test 13122 * Purpose: 13123 * Performs test operations common to TCAM and FIFO memory tests before 13124 * invoking common SER test. 13125 * Parameters: 13126 * unit - (IN) Device Number 13127 * test_data - (IN) Test data required for SER test 13128 * test_type - (IN) How many indices to test for each memory 13129 * mem_failed - (OUT) Incremented when memories fail the test. 13130 * Returns: 13131 * SOC_E_NONE if test passes, an error otherwise (multiple types of errors are 13132 * possible.) 13133 */ 13134 STATIC soc_error_t 13135 _soc_tomahawk_perform_ser_test(int unit, uint32 flags, ser_test_data_t *test_data, 13136 _soc_ser_test_t test_type, 13137 int *mem_skipped, int *mem_failed) 13138 { 13139 int k, skip_mem = FALSE; 13140 soc_error_t rv = SOC_E_NONE; 13141 soc_pipe_select_t pipe_target; 13142 uint32 mem_acc_type; 13143 13144 if (!SOC_MEM_IS_VALID(unit, test_data->mem_fv)) { 13145 LOG_ERROR(BSL_LS_SOC_SER, 13146 (BSL_META_U(unit, 13147 "unit %d, mem %d is INVALID or not valid " 13148 "for this unit !!\n"), 13149 unit, test_data->mem_fv)); 13150 skip_mem = TRUE; 13151 } 13152 for (k = 0; th_skipped_mems[k].mem != INVALIDm; k++) { 13153 if ((th_skipped_mems[k].mem == test_data->mem_fv) && 13154 ((_SOC_ACC_TYPE_PIPE_ANY == th_skipped_mems[k].acc_type) || 13155 (th_skipped_mems[k].acc_type == test_data->acc_type))) { 13156 skip_mem = TRUE; 13157 } 13158 } 13159 13160 if (soc_feature(unit, soc_feature_no_vfp) && 13161 (test_data->mem_fv == VFP_TCAMm || test_data->mem_fv == VFP_POLICY_TABLEm || 13162 test_data->mem_fv == VFP_POLICY_TABLE_PIPE0m || 13163 test_data->mem_fv == VFP_POLICY_TABLE_PIPE1m || 13164 test_data->mem_fv == VFP_POLICY_TABLE_PIPE2m || 13165 test_data->mem_fv == VFP_POLICY_TABLE_PIPE3m)) { 13166 skip_mem = TRUE; 13167 } 13168 13169 #ifdef BCM_TOMAHAWK3_SUPPORT 13170 if (SOC_IS_TOMAHAWK3(unit) && 13171 soc_th3_ser_test_skip_by_at(unit, test_data->mem_fv, test_data->acc_type)) { 13172 skip_mem = TRUE; 13173 } 13174 #endif 13175 13176 /* skip mems for which SW does not need to do error correction */ 13177 if (!(SOC_MEM_INFO(unit, test_data->mem_fv).flags & SOC_MEM_SER_FLAGS)) { 13178 LOG_VERBOSE(BSL_LS_SOC_SER, 13179 (BSL_META_U(unit, 13180 "SOC_MEM_SER_FLAGS is not set for %s " 13181 "(flags 0x%8x). Skipping.\n"), 13182 SOC_MEM_NAME(unit, test_data->mem_fv), 13183 SOC_MEM_INFO(unit,test_data->mem_fv).flags)); 13184 skip_mem = TRUE; 13185 } 13186 /* skip mems which could be of 0 depth due to config properties */ 13187 /* coverity[overrun-call] */ 13188 if (!soc_mem_index_count(unit, test_data->mem_fv)) { 13189 LOG_VERBOSE(BSL_LS_SOC_SER, 13190 (BSL_META_U(unit, 13191 "Index_Count is 0 for %s (flags 0x%8x). Skipping.\n"), 13192 SOC_MEM_NAME(unit, test_data->mem_fv), 13193 SOC_MEM_INFO(unit,test_data->mem_fv).flags)); 13194 skip_mem = TRUE; 13195 } 13196 /* skip mems which have addr_split */ 13197 mem_acc_type = SOC_MEM_ACC_TYPE(unit, test_data->mem_fv); 13198 if ((mem_acc_type == _SOC_TH_ACC_TYPE_ADDR_SPLIT_DIST) || 13199 (mem_acc_type == _SOC_TH_ACC_TYPE_ADDR_SPLIT_SPLIT)) { 13200 LOG_VERBOSE(BSL_LS_SOC_SER, 13201 (BSL_META_U(unit, 13202 "Memory %s has acc_type ADDR_SPLIT (%0d) \n"), 13203 SOC_MEM_NAME(unit,test_data->mem_fv), mem_acc_type)); 13204 /* skip_mem = TRUE; */ 13205 } 13206 13207 if (!skip_mem) { 13208 pipe_target = _soc_tomahawk_acc_type_to_pipe(test_data->acc_type); 13209 _soc_ser_find_test_field(unit, test_data->mem_fv, test_data->acc_type, 13210 &test_data->test_field); 13211 soc_tomahawk_pipe_select(unit, TRUE, pipe_target); 13212 soc_tomahawk_pipe_select(unit, FALSE, pipe_target); 13213 /* 13214 if (_soc_th_check_counter_with_ecc(unit, test_data->mem_fv)) { 13215 flags = flags | SOC_INJECT_ERROR_2BIT_ECC; 13216 } 13217 */ 13218 rv = ser_test_mem(unit, flags, test_data, test_type, mem_failed); 13219 if (SOC_FAILURE(rv)) { 13220 LOG_VERBOSE(BSL_LS_SOC_SER, 13221 (BSL_META_U(unit, 13222 "===== ser_test for Memory %s, Acc_type %d FAILED !!" 13223 " \n"), 13224 SOC_MEM_NAME(unit,test_data->mem_fv), test_data->acc_type)); 13225 } else { 13226 LOG_VERBOSE(BSL_LS_SOC_SER, 13227 (BSL_META_U(unit, 13228 "===== ser_test for Memory %s, Acc_type %d PASSED !!" 13229 " \n"), 13230 SOC_MEM_NAME(unit,test_data->mem_fv), test_data->acc_type)); 13231 } 13232 soc_tomahawk_pipe_select(unit, TRUE, 0); 13233 soc_tomahawk_pipe_select(unit, FALSE, 0); 13234 } else { 13235 LOG_VERBOSE(BSL_LS_SOC_SER, 13236 (BSL_META_U(unit, 13237 "===== ser_test for Memory %s, Acc_type %d " 13238 "SKIPPED \n"), 13239 SOC_MEM_NAME(unit,test_data->mem_fv), test_data->acc_type)); 13240 (*mem_skipped)++; 13241 } 13242 return rv; 13243 } 13244 13245 int 13246 _soc_th_refresh_modify(int unit, int enable) { 13247 struct { 13248 soc_reg_t ref_reg; 13249 soc_field_t en_field; 13250 } rf_list[] = { 13251 {AUX_ARB_CONTROLr, FP_REFRESH_ENABLEf}, 13252 {EFP_METER_CONTROLr, EFP_REFRESH_ENABLEf}, 13253 {MMU_GCFG_MISCCONFIGr, REFRESH_ENf}, 13254 #ifdef BCM_TOMAHAWK3_SUPPORT 13255 {AUX_ARB_CONTROLr, DLB_HGT_256NS_REFRESH_ENABLEf}, 13256 {MMU_MTRO_CONFIGr, REFRESH_DISABLEf}, 13257 {MMU_WRED_REFRESH_CONTROLr, REFRESH_DISABLEf}, 13258 {IFP_REFRESH_CONFIGr, IFP_REFRESH_DISABLEf}, 13259 {DLB_ECMP_REFRESH_DISABLEr, DLB_REFRESH_DISABLEf}, 13260 #endif 13261 {INVALIDr, INVALIDf} 13262 }; 13263 uint32 rval; 13264 uint32 fld_val = 0; 13265 int i; 13266 for (i = 0; rf_list[i].ref_reg != INVALIDr; i++) { 13267 if (!SOC_REG_IS_VALID(unit, rf_list[i].ref_reg) || 13268 !soc_reg_field_valid(unit, rf_list[i].ref_reg, rf_list[i].en_field)) { 13269 continue; 13270 } 13271 13272 #ifdef BCM_TOMAHAWK3_SUPPORT 13273 if (SOC_IS_TOMAHAWK3(unit) && rf_list[i].en_field == FP_REFRESH_ENABLEf) { 13274 continue; 13275 } 13276 if (SOC_IS_TOMAHAWK3(unit) && (rf_list[i].ref_reg == MMU_MTRO_CONFIGr || 13277 rf_list[i].ref_reg == MMU_WRED_REFRESH_CONTROLr || 13278 rf_list[i].ref_reg == IFP_REFRESH_CONFIGr || 13279 rf_list[i].ref_reg == DLB_ECMP_REFRESH_DISABLEr)) { 13280 fld_val = enable ? 0 : 1; 13281 } else 13282 #endif 13283 { 13284 fld_val = enable ? 1 : 0; 13285 } 13286 SOC_IF_ERROR_RETURN 13287 (soc_reg32_get(unit, rf_list[i].ref_reg, REG_PORT_ANY, 0, &rval)); 13288 soc_reg_field_set(unit, rf_list[i].ref_reg, &rval, rf_list[i].en_field, 13289 fld_val); 13290 SOC_IF_ERROR_RETURN 13291 (soc_reg32_set(unit, rf_list[i].ref_reg, REG_PORT_ANY, 0, rval)); 13292 } 13293 return SOC_E_NONE; 13294 } 13295 13296 soc_error_t 13297 soc_th_test_mem_create(int unit, soc_mem_t mem, int block, int index, 13298 uint32* p_flags, soc_acc_type_t soc_acc_type_target, 13299 uint32 * tmp_entry, uint32 * field_data, 13300 ser_test_data_t * p_test_data, 13301 _soc_mem_ser_en_info_t *ser_info_list) 13302 { 13303 int i = 0 ,found_mem = FALSE; 13304 soc_field_t test_field = INVALIDf; 13305 int mem_has_ecc = 0; 13306 13307 soc_mem_t en_mem; 13308 soc_reg_t en_reg; 13309 13310 for (i = 0; ser_info_list[i].mem != INVALIDm; i++) { 13311 if ((ser_info_list[i].mem == mem) && 13312 (soc_mem_index_count(unit, mem))) { 13313 test_field = ECCf; 13314 _soc_ser_find_test_field(unit, mem, soc_acc_type_target, 13315 &test_field); 13316 en_reg = ser_info_list[i].en_ctrl.flag_reg_mem ? INVALIDr : 13317 ser_info_list[i].en_ctrl.ctrl_type.en_reg; 13318 en_mem = ser_info_list[i].en_ctrl.flag_reg_mem ? 13319 ser_info_list[i].en_ctrl.ctrl_type.en_mem : INVALIDm; 13320 soc_ser_create_test_data_with_new_format(unit, tmp_entry, field_data, 13321 en_reg, 13322 en_mem, 13323 SOC_INVALID_TCAM_PARITY_BIT, 13324 ser_info_list[i].en_ctrl.en_fld, 13325 ser_info_list[i].en_ctrl.en_fld_position, 13326 mem, test_field, block, 13327 REG_PORT_ANY, 13328 soc_acc_type_target, 13329 index, p_test_data); 13330 found_mem = TRUE; 13331 if ((SOC_REG_IS_VALID(unit, ser_info_list[i].ecc1b_ctrl.ctrl_type.en_reg) || 13332 SOC_MEM_IS_VALID(unit, ser_info_list[i].ecc1b_ctrl.ctrl_type.en_mem)) && 13333 (INVALIDf != ser_info_list[i].ecc1b_ctrl.en_fld)) { 13334 *p_flags |= SOC_INJECT_ERROR_2BIT_ECC; 13335 } 13336 13337 SOC_IF_ERROR_RETURN 13338 (ser_test_mem_index_remap(unit, p_test_data, &mem_has_ecc)); 13339 if (mem_has_ecc) { 13340 *p_flags |= SOC_INJECT_ERROR_2BIT_ECC; 13341 } 13342 break; 13343 } 13344 } 13345 13346 if (found_mem) { 13347 return SOC_E_NONE; 13348 }else { 13349 return SOC_E_UNAVAIL; 13350 } 13351 } 13352 13353 STATIC int 13354 soc_th_ser_pipe_check(int unit, int pipe) 13355 { 13356 int rv = SOC_E_NONE; 13357 13358 #ifdef BCM_TOMAHAWK3_SUPPORT 13359 if (SOC_IS_TOMAHAWK3(unit)) { 13360 if (pipe != SOC_PIPE_SELECT_0 && 13361 pipe != SOC_PIPE_SELECT_1 && 13362 pipe != SOC_PIPE_SELECT_2 && 13363 pipe != SOC_PIPE_SELECT_3 && 13364 pipe != SOC_PIPE_SELECT_4 && 13365 pipe != SOC_PIPE_SELECT_5 && 13366 pipe != SOC_PIPE_SELECT_6 && 13367 pipe != SOC_PIPE_SELECT_7 && 13368 pipe != SOC_PIPE_SELECT_ANY && 13369 pipe != _SOC_ACC_TYPE_PIPE_ALL) { 13370 rv = SOC_E_PARAM; 13371 } 13372 } else 13373 #endif 13374 { 13375 if (pipe != SOC_PIPE_SELECT_0 && 13376 pipe != SOC_PIPE_SELECT_1 && 13377 pipe != SOC_PIPE_SELECT_2 && 13378 pipe != SOC_PIPE_SELECT_3 && 13379 pipe != SOC_PIPE_SELECT_ANY && 13380 pipe != _SOC_ACC_TYPE_PIPE_ALL) { 13381 rv = SOC_E_PARAM; 13382 } 13383 } 13384 13385 return rv; 13386 } 13387 13388 13389 /* 13390 * Function: 13391 * soc_th_ser_inject_or_test_mem 13392 * Purpose: 13393 * Provide a common function for injecting errors and testing single 13394 * single memories 13395 * Parameters: 13396 * unit - (IN) Device Number 13397 * mem - (IN) The memory into which an error will be injected 13398 * pipeTarget - (IN) The pipe (x/y) to use when injecting the error 13399 * index - (IN) The index into which the error will be injected. 13400 * test_type - (IN) How many indices to test in the passes memory 13401 * cmd - (IN) TRUE if a command-line test is desired. 13402 * Returns: 13403 * SOC_E_NONE if test passes, an error otherwise (multiple types of errors 13404 * are possible.) 13405 */ 13406 soc_error_t 13407 soc_th_ser_inject_or_test_mem(int unit, soc_mem_t mem, int pipe_target, int block, 13408 int index, _soc_ser_test_t test_type, 13409 int inject_only, int cmd, uint32 flags) 13410 { 13411 uint32 tmp_entry[SOC_MAX_MEM_WORDS], field_data[SOC_MAX_MEM_FIELD_WORDS]; 13412 ser_test_data_t test_data; 13413 _soc_generic_ser_info_t *tcams = _soc_th_tcam_ser_info[unit]; 13414 int i, p, error_count = 0, skip_count = 0, found_mem = FALSE; 13415 int fld_len; 13416 char fail_message[TR_MEM_NAME_SIZE_MAX + 1]; 13417 soc_error_t rv = SOC_E_NONE; 13418 soc_acc_type_t soc_acc_type_target, mem_acc_type; 13419 soc_field_t test_field = INVALIDf; 13420 uint32 rval; 13421 uint32 *entry = NULL; 13422 uint32 fld_value = 0; 13423 ser_correction_info_t corr_info; 13424 uint8 xor_bank = FALSE; 13425 _soc_ser_sram_info_t *sram_info = NULL; 13426 13427 SOC_IF_ERROR_RETURN(soc_th_ser_pipe_check(unit, pipe_target)); 13428 13429 if (!SOC_MEM_IS_VALID(unit, mem) || 13430 (SOC_MEM_INFO(unit, mem).flags & SOC_MEM_FLAG_SER_PARITY_ENABLE_SKIP)) { 13431 LOG_ERROR(BSL_LS_SOC_SER, 13432 (BSL_META_U(unit, 13433 "unit %d, mem %s is INVALID or not valid " 13434 "or parity is disabled for this mem !!\n"), 13435 unit, SOC_MEM_NAME(unit,mem))); 13436 return SOC_E_UNAVAIL; 13437 } 13438 /*** 13439 if (_soc_th_check_counter_with_ecc(unit, mem)) { 13440 flags |= SOC_INJECT_ERROR_2BIT_ECC; 13441 } 13442 */ 13443 13444 mem_acc_type = SOC_MEM_ACC_TYPE(unit, mem); 13445 #ifdef BCM_TOMAHAWK3_SUPPORT 13446 if (SOC_IS_TOMAHAWK3(unit) && (mem_acc_type <= _SOC_UNIQUE_ACC_TYPE_PIPE_7)) { 13447 soc_acc_type_target = mem_acc_type; 13448 LOG_VERBOSE(BSL_LS_SOC_SER, 13449 (BSL_META_U(unit, 13450 "soc_th_ser_inject_or_test_mem: unit %d, mem %s, " 13451 "pipe_target %d, BUT mem_acc_type %d will be " 13452 "used\n"), 13453 unit, SOC_MEM_NAME(unit, mem), 13454 pipe_target, soc_acc_type_target)); 13455 } else 13456 #endif 13457 if (mem_acc_type <= _SOC_UNIQUE_ACC_TYPE_PIPE_3) { 13458 soc_acc_type_target = mem_acc_type; 13459 LOG_VERBOSE(BSL_LS_SOC_SER, 13460 (BSL_META_U(unit, 13461 "soc_th_ser_inject_or_test_mem: unit %d, mem %s, " 13462 "pipe_target %d, BUT mem_acc_type %d will be " 13463 "used\n"), 13464 unit, SOC_MEM_NAME(unit, mem), 13465 pipe_target, soc_acc_type_target)); 13466 } else if ((mem_acc_type == _SOC_TH_ACC_TYPE_ADDR_SPLIT_DIST) || 13467 (mem_acc_type == _SOC_TH_ACC_TYPE_ADDR_SPLIT_SPLIT)) { 13468 /* 1. ignore pipe_target, because pipe is determined by index param 13469 * 2. For such mem, ser_en_info in bcm56960_a0.c file will not have 13470 * _PIPE0,1,2,3 views (these are created only for mems with UNIQUE 13471 * acc type. 13472 */ 13473 soc_acc_type_target = _SOC_ACC_TYPE_PIPE_ANY; 13474 } else { 13475 soc_acc_type_target = _soc_tomahawk_pipe_to_acc_type(pipe_target); 13476 } 13477 13478 corr_info.inject_mem = mem; 13479 _ser_th_correction_info_get(unit, &corr_info); 13480 13481 /* Check if the memory is to be skipped */ 13482 for (i = 0; th_skipped_mems[i].mem != INVALIDm; i++) { 13483 if ((th_skipped_mems[i].mem == mem) && 13484 ((_SOC_ACC_TYPE_PIPE_ANY == th_skipped_mems[i].acc_type) || 13485 (th_skipped_mems[i].acc_type == soc_acc_type_target))) { 13486 /* coverity[secure_coding] */ 13487 if (inject_only && th_skipped_mems[i].allow_error_inj) { 13488 break; 13489 } 13490 TR_TEST_MEM_PRINT(unit, fail_message, mem); 13491 return SOC_E_UNAVAIL; 13492 } 13493 } 13494 13495 #ifdef BCM_TOMAHAWK2_SUPPORT 13496 if (SOC_IS_TOMAHAWK2(unit) && soc_feature(unit, soc_feature_tcam_scan_engine)) { 13497 for (i = 0; _soc_th2_tcam_wrapper_table[i].mem != INVALIDm; i++) { 13498 if (_soc_th2_tcam_wrapper_table[i].mem == mem) { 13499 /* found */ 13500 found_mem = TRUE; 13501 soc_ser_create_test_data(unit, tmp_entry, field_data, 13502 _soc_th2_tcam_wrapper_table[i].enable_reg, 13503 SOC_INVALID_TCAM_PARITY_BIT, 13504 _soc_th2_tcam_wrapper_table[i].enable_field, 13505 mem, _soc_th2_tcam_wrapper_table[i].parity_field, 13506 block, REG_PORT_ANY, 13507 soc_acc_type_target, index, &test_data); 13508 break; 13509 } 13510 } 13511 } 13512 #endif 13513 #ifdef BCM_TOMAHAWK3_SUPPORT 13514 if (SOC_IS_TOMAHAWK3(unit) && soc_feature(unit, soc_feature_tcam_scan_engine)) { 13515 for (i = 0; _soc_bcm56980_a0_tcam_mem_ser_info[i].mem != INVALIDm; i++) { 13516 if (_soc_bcm56980_a0_tcam_mem_ser_info[i].mem == mem) { 13517 /* found */ 13518 found_mem = TRUE; 13519 soc_ser_create_test_data_with_new_format(unit, tmp_entry, field_data, 13520 _soc_bcm56980_a0_tcam_mem_ser_info[i].enable_reg, 13521 INVALIDm, SOC_INVALID_TCAM_PARITY_BIT, 13522 _soc_bcm56980_a0_tcam_mem_ser_info[i].enable_field, 13523 -1, mem, 13524 _soc_bcm56980_a0_tcam_mem_ser_info[i].parity_field, 13525 MEM_BLOCK_ANY, REG_PORT_ANY, soc_acc_type_target, 13526 index, &test_data); 13527 break; 13528 } 13529 } 13530 } 13531 #endif 13532 13533 if (!found_mem) { 13534 /* Search for TCAM memories */ 13535 if (SOC_REG_IS_VALID(unit, SER_RANGE_ENABLEr)) { 13536 SOC_IF_ERROR_RETURN 13537 (soc_reg32_get(unit, SER_RANGE_ENABLEr, REG_PORT_ANY, 0, &rval)); 13538 for (i = 0; tcams[i].mem != INVALIDm; i++) { 13539 if (tcams[i].mem == mem) { 13540 if (mem == L3_DEFIPm || 13541 mem == L3_DEFIP_PAIR_128m || 13542 mem == ING_SNATm || 13543 mem == L3_TUNNELm) { 13544 LOG_VERBOSE(BSL_LS_SOC_SER, (BSL_META_U(unit, 13545 "soc_th_ser_inject_or_test_mem: mem %s, will not inject error on TCAM.valid bit, but on data portion of this table\n"), 13546 SOC_MEM_NAME(unit, mem))); 13547 break; /* from tcam loop (inject error to data view) */ 13548 } 13549 switch (tcams[i].mem) { 13550 case L3_DEFIPm: 13551 test_field = VALID0f; 13552 break; 13553 case L3_DEFIP_PAIR_128m: 13554 test_field = VALID0_LWRf; 13555 break; 13556 default: 13557 test_field = VALIDf; 13558 break; 13559 } 13560 13561 /* For mems that can operate in either global/unique mode 13562 * make sure we find the correct enable bit position in 13563 * SER_RANGE_ENABLEr 13564 */ 13565 if (((rval >> tcams[i].ser_hw_index) & 0x1) == 0) { 13566 break; /* we found the matching mem in list, BUT ser_detection 13567 is disabled - so no more searching */ 13568 } 13569 LOG_VERBOSE(BSL_LS_SOC_SER, 13570 (BSL_META_U(unit, 13571 "soc_th_ser_inject_or_test_mem: unit %d, mem %s, " 13572 "i %d, ser_hw_index %d, ser_range_enable=%8x\n"), 13573 unit, SOC_MEM_NAME(unit, mem), i, tcams[i].ser_hw_index, 13574 rval)); 13575 soc_ser_create_test_data(unit, tmp_entry, field_data, 13576 SER_RANGE_ENABLEr, tcams[i].ser_hw_index, 13577 INVALIDf, mem, 13578 test_field, block, REG_PORT_ANY, 13579 soc_acc_type_target, index, &test_data); 13580 found_mem = TRUE; 13581 break; /*A memory was found that matched, so stop searching.*/ 13582 } 13583 if (SOC_MEM_UNIQUE_ACC(unit, tcams[i].mem) != NULL) { 13584 for (p = 0; p < NUM_PIPE(unit); p++) { 13585 if (SOC_MEM_UNIQUE_ACC(unit, tcams[i].mem)[p] == mem) { 13586 if (((rval >> (tcams[i].ser_hw_index + 1)) & 0x1) == 0) { 13587 break; /* from pipe loop */ 13588 /* we found matching mem, BUT ser_detection is 13589 * disabled - so no more searching */ 13590 } 13591 test_field = VALIDf; 13592 LOG_VERBOSE(BSL_LS_SOC_SER, 13593 (BSL_META_U(unit, 13594 "soc_th_ser_inject_or_test_mem: unit %d, mem %s, " 13595 "i %d, ser_hw_index+1 %d, ser_range_enable=%8x\n"), 13596 unit, SOC_MEM_NAME(unit, mem), i, 13597 tcams[i].ser_hw_index + 1, rval)); 13598 soc_ser_create_test_data(unit, tmp_entry, field_data, 13599 SER_RANGE_ENABLEr, 13600 (tcams[i].ser_hw_index + 1), 13601 INVALIDf, mem, 13602 test_field, block, REG_PORT_ANY, 13603 soc_acc_type_target, index, 13604 &test_data); 13605 found_mem = TRUE; 13606 break; /* from pipe loop */ 13607 } 13608 } 13609 } 13610 if (found_mem) { 13611 break; 13612 } 13613 } 13614 } 13615 } 13616 13617 /* Search for mems listed in: 13618 * _soc_bcm56960_a0_ip_mem_ser_info, 13619 * _soc_bcm56960_a0_ep_mem_ser_info 13620 */ 13621 if (!found_mem) { 13622 rv = soc_th_test_mem_create(unit, mem, block, index, &flags, soc_acc_type_target, 13623 tmp_entry, field_data, &test_data, SOC_IP_MEM_SER_INFO(unit)); 13624 if (rv == SOC_E_NONE) { 13625 found_mem = TRUE; 13626 }else { 13627 rv = soc_th_test_mem_create(unit, mem, block, index, &flags, soc_acc_type_target, 13628 tmp_entry, field_data, &test_data, SOC_EP_MEM_SER_INFO(unit)); 13629 if (rv == SOC_E_NONE) { 13630 found_mem = TRUE; 13631 } else { 13632 rv = soc_th_test_mem_create(unit, mem, block, index, &flags, _SOC_ACC_TYPE_PIPE_ANY, 13633 tmp_entry, field_data, &test_data, SOC_MMU_MEM_SER_INFO(unit)); 13634 if (rv == SOC_E_NONE) { 13635 found_mem = TRUE; 13636 } 13637 } 13638 } 13639 } 13640 13641 if (found_mem) { 13642 LOG_VERBOSE(BSL_LS_SOC_SER, 13643 (BSL_META_U(unit, 13644 "soc_th_ser_inject_or_test_mem: unit %d, mem %s, " 13645 "pipe_target %d, block %d, index %d, test_type %d, " 13646 "inject_only %d, cmd %d, flags 0x%x \n"), 13647 unit, SOC_MEM_NAME(unit, mem), 13648 pipe_target, block, index, test_type, inject_only, cmd, flags)); 13649 if (inject_only) { 13650 /* index check */ 13651 if (!soc_mem_index_valid(unit, mem, index)) { 13652 TR_TEST_MEM_PRINT(unit, fail_message, mem); 13653 rv = SOC_E_PARAM; 13654 return rv; 13655 } 13656 13657 xor_bank = (flags & SOC_INJECT_ERROR_XOR_BANK) ? TRUE : FALSE; 13658 if (xor_bank) { 13659 /* 13660 * To inject parity error to XOR Bank 13661 * 1) Disable parity_en of table 13662 * 2) Set DEBUG_DISABLE_XOR_WRITE==0 13663 * 3) Issue MEMWR to table with corrupt PARITY field 13664 * 4) Set DEBUG_DISABLE_XOR_WRITE==1 13665 * 5) Issue MEMWR to table with correct PARITY field 13666 * 6) Set DEBUG_DISABLE_XOR_WRITE==0 13667 * 7) Enable parity_en of table 13668 */ 13669 sram_info = sal_alloc(sizeof(_soc_ser_sram_info_t), "TH sram info"); 13670 if (NULL == sram_info) { 13671 LOG_VERBOSE(BSL_LS_SOC_SER, (BSL_META_U(unit, 13672 "soc_th_ser_inject_or_test_mem: mem %s, alloc " 13673 "memory for sram_info failed!\n"), 13674 SOC_MEM_NAME(unit, mem))); 13675 return (SOC_E_MEMORY); 13676 } 13677 _soc_sram_info_init(unit, sram_info); 13678 (void)soc_tomahawk_mem_sram_info_get(unit, 13679 test_data.mem, test_data.index, sram_info); 13680 } 13681 13682 /* Set pipe select */ 13683 soc_tomahawk_pipe_select(unit, TRUE, pipe_target); 13684 soc_tomahawk_pipe_select(unit, FALSE, pipe_target); 13685 13686 /* Disable parity */ 13687 rv = _ser_test_parity_control(unit, &test_data, 0); 13688 if (SOC_FAILURE(rv)) { 13689 LOG_ERROR(BSL_LS_SOC_SER, (BSL_META_U(unit, 13690 "soc_th_ser_inject_or_test_mem: unit %d," 13691 "Error_inject: Disable parity for mem %s FAILED\n"), 13692 unit, SOC_MEM_NAME(unit, mem))); 13693 soc_tomahawk_pipe_select(unit, TRUE, 0); 13694 soc_tomahawk_pipe_select(unit, FALSE, 0); 13695 if (xor_bank && sram_info != NULL) { 13696 sal_free(sram_info); 13697 } 13698 return rv; 13699 } 13700 13701 /* Read the memory (required for successful injection) */ 13702 rv = ser_test_mem_read(unit, 0, &test_data); 13703 if (SOC_FAILURE(rv)) { 13704 LOG_ERROR(BSL_LS_SOC_SER, (BSL_META_U(unit, 13705 "soc_th_ser_inject_or_test_mem: unit %d, Error_inject: Read for mem %s FAILED\n"), 13706 unit, SOC_MEM_NAME(unit, mem))); 13707 (void)_ser_test_parity_control(unit, &test_data, 1); 13708 soc_tomahawk_pipe_select(unit, TRUE, 0); 13709 soc_tomahawk_pipe_select(unit, FALSE, 0); 13710 if (xor_bank && sram_info != NULL) { 13711 sal_free(sram_info); 13712 } 13713 return rv; 13714 } 13715 13716 /* Inject error */ 13717 rv = soc_ser_test_inject_full(unit, flags, &test_data); 13718 if (SOC_FAILURE(rv)) { 13719 LOG_ERROR(BSL_LS_SOC_SER, (BSL_META_U(unit, 13720 "soc_th_ser_inject_or_test_mem: unit %d, Error_inject: error inject for mem %s FAILED\n"), 13721 unit, SOC_MEM_NAME(unit, mem))); 13722 (void)_ser_test_parity_control(unit, &test_data, 1); 13723 soc_tomahawk_pipe_select(unit, TRUE, 0); 13724 soc_tomahawk_pipe_select(unit, FALSE, 0); 13725 if (xor_bank && sram_info != NULL) { 13726 sal_free(sram_info); 13727 } 13728 return rv; 13729 } 13730 13731 if (xor_bank) { 13732 if (SOC_REG_IS_VALID(unit, sram_info->force_reg)) { 13733 /* Disable xor bank writing */ 13734 fld_len = soc_reg_field_length(unit, sram_info->force_reg, 13735 sram_info->disable_xor_write_field); 13736 fld_value = (1 << fld_len) - 1; 13737 soc_reg_field32_modify(unit, sram_info->force_reg, 13738 REG_PORT_ANY, 13739 sram_info->disable_xor_write_field, fld_value); 13740 13741 /* Call it again to write correct data */ 13742 rv = soc_ser_test_inject_full(unit, flags, &test_data); 13743 13744 /* Enable xor bank writing */ 13745 soc_reg_field32_modify(unit, sram_info->force_reg, 13746 REG_PORT_ANY, 13747 sram_info->disable_xor_write_field, 0); 13748 if (SOC_FAILURE(rv)) { 13749 LOG_ERROR(BSL_LS_SOC_SER, (BSL_META_U(unit, 13750 "soc_th_ser_inject_or_test_mem: unit %d," 13751 "write correct data into mem %s FAILED\n"), 13752 unit, SOC_MEM_NAME(unit, mem))); 13753 (void)_ser_test_parity_control(unit, &test_data, 1); 13754 soc_tomahawk_pipe_select(unit, TRUE, 0); 13755 soc_tomahawk_pipe_select(unit, FALSE, 0); 13756 sal_free(sram_info); 13757 return rv; 13758 } 13759 13760 cli_out("Set %sr.%sf before dump to trigger XOR bank error!\n", 13761 SOC_REG_NAME(unit, sram_info->force_reg), 13762 SOC_FIELD_NAME(unit, sram_info->force_field)); 13763 } else if(SOC_MEM_IS_VALID(unit, sram_info->force_mem)) { 13764 entry = sal_alloc((4 * SOC_MAX_MEM_WORDS), "sram_entry"); 13765 if (entry == NULL) { 13766 return SOC_E_MEMORY; 13767 } 13768 sal_memset(entry, 0, 4 * soc_mem_entry_words(unit, sram_info->force_mem)); 13769 13770 /* Disable xor bank writing */ 13771 soc_mem_read(unit, sram_info->force_mem, MEM_BLOCK_ALL, 0, entry); 13772 fld_len = soc_mem_field_length(unit, sram_info->force_mem, 13773 sram_info->disable_xor_write_field); 13774 fld_value = (1 << fld_len) - 1; 13775 soc_mem_field32_set(unit, sram_info->force_mem, entry, 13776 sram_info->disable_xor_write_field, fld_value); 13777 soc_mem_write(unit, sram_info->force_mem, MEM_BLOCK_ALL, 0, entry); 13778 13779 /* Call it again to write correct data */ 13780 rv = soc_ser_test_inject_full(unit, flags, &test_data); 13781 13782 /* Enable xor bank writing */ 13783 soc_mem_field32_set(unit, sram_info->force_mem, entry, 13784 sram_info->disable_xor_write_field, 0); 13785 soc_mem_write(unit, sram_info->force_mem, MEM_BLOCK_ALL, 0, entry); 13786 13787 if (SOC_FAILURE(rv)) { 13788 LOG_ERROR(BSL_LS_SOC_SER, (BSL_META_U(unit, 13789 "soc_th_ser_inject_or_test_mem: unit %d," 13790 "write correct data into mem %s FAILED\n"), 13791 unit, SOC_MEM_NAME(unit, mem))); 13792 (void)_ser_test_parity_control(unit, &test_data, 1); 13793 soc_tomahawk_pipe_select(unit, TRUE, 0); 13794 soc_tomahawk_pipe_select(unit, FALSE, 0); 13795 sal_free(sram_info); 13796 sal_free(entry); 13797 return rv; 13798 } 13799 LOG_CLI((BSL_META_U(unit, "Set %sm.%sf before dump to trigger XOR bank error!\n"), 13800 SOC_MEM_NAME(unit, sram_info->force_mem), 13801 SOC_FIELD_NAME(unit, sram_info->force_field))); 13802 sal_free(entry); 13803 } else { 13804 LOG_ERROR(BSL_LS_SOC_SER, (BSL_META_U(unit, 13805 "soc_th_ser_inject_or_test_mem: unit %d," 13806 "Don't support injecting error into XOR bank of " 13807 "mem %s index %d FAILED\n"), 13808 unit, SOC_MEM_NAME(unit, mem), index)); 13809 rv = SOC_E_UNAVAIL; 13810 } 13811 sal_free(sram_info); 13812 } 13813 13814 /* Enable parity */ 13815 SOC_IF_ERROR_RETURN(_ser_test_parity_control(unit, &test_data, 1)); 13816 13817 soc_tomahawk_pipe_select(unit, TRUE, 0); 13818 soc_tomahawk_pipe_select(unit, FALSE, 0); 13819 } else { 13820 if (cmd) { 13821 ser_test_cmd_generate(unit, &test_data); 13822 } else { 13823 int def_soc_ser_test_long_sleep; 13824 int def_soc_ser_test_long_sleep_time_us; 13825 13826 /* save default values, choose TH specific values */ 13827 def_soc_ser_test_long_sleep = soc_ser_test_long_sleep; 13828 def_soc_ser_test_long_sleep_time_us = soc_ser_test_long_sleep_time_us; 13829 soc_ser_test_long_sleep = TRUE; 13830 soc_ser_test_long_sleep_time_us = 13831 soc_property_get(unit, "tr144_long_sleep_time_us", 13832 _SOC_TH_TR144_LONG_SLEEP_TIME_US); 13833 LOG_VERBOSE(BSL_LS_SOC_SER, 13834 (BSL_META_U(unit, 13835 "tr 144 test will use:long_sleep = %d," 13836 "long_sleep_time = %d uS\n"), 13837 soc_ser_test_long_sleep, 13838 soc_ser_test_long_sleep_time_us)); 13839 13840 (void) _soc_th_refresh_modify(unit, 0); /* disable refresh */ 13841 rv = _soc_tomahawk_perform_ser_test(unit, flags, &test_data, test_type, 13842 &skip_count, &error_count); 13843 (void) _soc_th_refresh_modify(unit, 1); /* re-enable refresh */ 13844 13845 /* restore default values */ 13846 soc_ser_test_long_sleep = def_soc_ser_test_long_sleep; 13847 soc_ser_test_long_sleep_time_us = def_soc_ser_test_long_sleep_time_us; 13848 13849 if (!SOC_FAILURE(rv)) { 13850 if ((error_count == 0) && !skip_count) { 13851 LOG_VERBOSE(BSL_LS_SOC_SER, 13852 (BSL_META_U(unit, 13853 "SER test PASSED for memory" 13854 "%s\n"), 13855 test_data.mem_name)); 13856 } 13857 if (skip_count !=0) { 13858 LOG_VERBOSE(BSL_LS_SOC_SER, 13859 (BSL_META_U(unit, 13860 "SER test SKIPPED for memory" 13861 "%s\n"), 13862 test_data.mem_name)); 13863 } 13864 } 13865 } 13866 } 13867 } else { 13868 TR_TEST_MEM_PRINT(unit, fail_message, mem); 13869 rv = SOC_E_UNAVAIL; 13870 } 13871 return rv; 13872 } 13873 13874 /* 13875 * Function: 13876 * soc_th_ser_inject_error 13877 * Purpose: 13878 * Injects an error into a single th memory 13879 * Parameters: 13880 * unit - (IN) Device Number 13881 * mem - (IN) The memory into which an error will be injected 13882 * pipeTarget - (IN) The pipe to use when injecting the error 13883 * index - (IN) The index into which the error will be injected. 13884 */ 13885 STATIC soc_error_t 13886 soc_th_ser_inject_error(int unit, uint32 flags, soc_mem_t mem, int pipe_target, 13887 int block, int index) 13888 { 13889 return soc_th_ser_inject_or_test_mem(unit, mem, pipe_target, block, index, 13890 SER_SINGLE_INDEX, TRUE, FALSE, flags); 13891 } 13892 13893 /* 13894 * Function: 13895 * soc_th_ser_test_mem 13896 * Purpose: 13897 * Perform SER test on a single memory, or generate a test the user can 13898 * enter by the command line. 13899 * Parameters: 13900 * unit - (IN) Device Number 13901 * mem - (IN) The memory into which an error will be injected 13902 * test_type - (IN) How many indices to test in the passes memory 13903 * cmd - (IN) TRUE if a command-line test is desired. 13904 * Returns: 13905 * SOC_E_NONE if test passes, an error otherwise (multiple types of errors 13906 * are possible.) 13907 */ 13908 STATIC soc_error_t 13909 soc_th_ser_test_mem(int unit, soc_mem_t mem, _soc_ser_test_t test_type, 13910 int cmd) 13911 { 13912 return soc_th_ser_inject_or_test_mem(unit, mem, -1, MEM_BLOCK_ANY, 0, 13913 test_type, FALSE, cmd, FALSE); 13914 } 13915 13916 const soc_mem_t th3_tcam_test_skipped_mems[] = { 13917 EFP_TCAM_PIPE0m, 13918 EFP_TCAM_PIPE1m, 13919 EFP_TCAM_PIPE2m, 13920 EFP_TCAM_PIPE3m, 13921 EFP_TCAM_PIPE4m, 13922 EFP_TCAM_PIPE5m, 13923 EFP_TCAM_PIPE6m, 13924 EFP_TCAM_PIPE7m, 13925 EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE0m, 13926 EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE1m, 13927 EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE2m, 13928 EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE3m, 13929 EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE4m, 13930 EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE5m, 13931 EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE6m, 13932 EXACT_MATCH_LOGICAL_TABLE_SELECT_PIPE7m, 13933 EXACT_MATCH_LOGICAL_TABLE_SELECT_TCAM_ONLY_PIPE0m, 13934 EXACT_MATCH_LOGICAL_TABLE_SELECT_TCAM_ONLY_PIPE1m, 13935 EXACT_MATCH_LOGICAL_TABLE_SELECT_TCAM_ONLY_PIPE2m, 13936 EXACT_MATCH_LOGICAL_TABLE_SELECT_TCAM_ONLY_PIPE3m, 13937 EXACT_MATCH_LOGICAL_TABLE_SELECT_TCAM_ONLY_PIPE4m, 13938 EXACT_MATCH_LOGICAL_TABLE_SELECT_TCAM_ONLY_PIPE5m, 13939 EXACT_MATCH_LOGICAL_TABLE_SELECT_TCAM_ONLY_PIPE6m, 13940 EXACT_MATCH_LOGICAL_TABLE_SELECT_TCAM_ONLY_PIPE7m, 13941 FP_UDF_TCAM_PIPE0m, 13942 FP_UDF_TCAM_PIPE1m, 13943 FP_UDF_TCAM_PIPE2m, 13944 FP_UDF_TCAM_PIPE3m, 13945 FP_UDF_TCAM_PIPE4m, 13946 FP_UDF_TCAM_PIPE5m, 13947 FP_UDF_TCAM_PIPE6m, 13948 FP_UDF_TCAM_PIPE7m, 13949 IFP_LOGICAL_TABLE_SELECT_PIPE0m, 13950 IFP_LOGICAL_TABLE_SELECT_PIPE1m, 13951 IFP_LOGICAL_TABLE_SELECT_PIPE2m, 13952 IFP_LOGICAL_TABLE_SELECT_PIPE3m, 13953 IFP_LOGICAL_TABLE_SELECT_PIPE4m, 13954 IFP_LOGICAL_TABLE_SELECT_PIPE5m, 13955 IFP_LOGICAL_TABLE_SELECT_PIPE6m, 13956 IFP_LOGICAL_TABLE_SELECT_PIPE7m, 13957 IFP_LOGICAL_TABLE_SELECT_TCAM_ONLY_PIPE0m, 13958 IFP_LOGICAL_TABLE_SELECT_TCAM_ONLY_PIPE1m, 13959 IFP_LOGICAL_TABLE_SELECT_TCAM_ONLY_PIPE2m, 13960 IFP_LOGICAL_TABLE_SELECT_TCAM_ONLY_PIPE3m, 13961 IFP_LOGICAL_TABLE_SELECT_TCAM_ONLY_PIPE4m, 13962 IFP_LOGICAL_TABLE_SELECT_TCAM_ONLY_PIPE5m, 13963 IFP_LOGICAL_TABLE_SELECT_TCAM_ONLY_PIPE6m, 13964 IFP_LOGICAL_TABLE_SELECT_TCAM_ONLY_PIPE7m, 13965 IFP_TCAM_PIPE0m, 13966 IFP_TCAM_PIPE1m, 13967 IFP_TCAM_PIPE2m, 13968 IFP_TCAM_PIPE3m, 13969 IFP_TCAM_PIPE4m, 13970 IFP_TCAM_PIPE5m, 13971 IFP_TCAM_PIPE6m, 13972 IFP_TCAM_PIPE7m, 13973 VFP_TCAM_PIPE0m, 13974 VFP_TCAM_PIPE1m, 13975 VFP_TCAM_PIPE2m, 13976 VFP_TCAM_PIPE3m, 13977 VFP_TCAM_PIPE4m, 13978 VFP_TCAM_PIPE5m, 13979 VFP_TCAM_PIPE6m, 13980 VFP_TCAM_PIPE7m, 13981 INVALIDm 13982 }; 13983 /* 13984 * Function: 13985 * soc_th_ser_tcam_test 13986 * Purpose: 13987 * Tests that SER is working for fifo and SRAM memories 13988 * Parameters: 13989 * unit - (IN) Device Number 13990 * test_type - (IN) How many indices to test for each memory 13991 * Returns: 13992 * the number of tests which are failed 13993 */ 13994 STATIC int 13995 soc_th_ser_tcam_test(int unit, _soc_ser_test_t test_type) 13996 { 13997 uint32 tmp_entry[SOC_MAX_MEM_WORDS], field_data[SOC_MAX_MEM_FIELD_WORDS]; 13998 ser_test_data_t test_data; 13999 int mem_failed = 0, mem_tests = 0, mem_skipped = 0; 14000 _soc_generic_ser_info_t *tcams = _soc_th_tcam_ser_info[unit]; 14001 int i; 14002 #ifdef BCM_TOMAHAWK3_SUPPORT 14003 int j; 14004 int skip = FALSE; 14005 int num_inst_to_test = 0; 14006 soc_acc_type_t start_at = _SOC_MEM_ADDR_ACC_TYPE_PIPE_0; 14007 #endif 14008 soc_acc_type_t acc_type; 14009 #ifdef BCM_TOMAHAWK2_SUPPORT 14010 soc_acc_type_t wrapper_at; 14011 #endif 14012 soc_field_t test_field = VALIDf; 14013 int tcam_parity_bit; 14014 int mem_index = 0; /* dont_care */ 14015 14016 #ifdef BCM_TOMAHAWK2_SUPPORT 14017 if (SOC_IS_TOMAHAWK2(unit) && soc_feature(unit, soc_feature_tcam_scan_engine)) { 14018 for (i = 0; _soc_th2_tcam_wrapper_table[i].mem != INVALIDm; i++) { 14019 for (wrapper_at = _SOC_MEM_ADDR_ACC_TYPE_PIPE_0; wrapper_at < NUM_PIPE(unit); wrapper_at++) { 14020 mem_tests++; 14021 if (!SOC_MEM_IS_VALID(unit, _soc_th2_tcam_wrapper_table[i].mem) || 14022 (SOC_MEM_INFO(unit, _soc_th2_tcam_wrapper_table[i].mem).flags & 14023 SOC_MEM_FLAG_SER_PARITY_ENABLE_SKIP)) { 14024 LOG_WARN(BSL_LS_SOC_SER, 14025 (BSL_META_U(unit, 14026 "unit %d, mem %s is INVALID or not valid " 14027 "or parity is disabled for this mem !!\n"), 14028 unit, SOC_MEM_NAME(unit, _soc_th2_tcam_wrapper_table[i].mem))); 14029 mem_skipped++; 14030 continue; 14031 } 14032 14033 soc_ser_create_test_data(unit, tmp_entry, field_data, 14034 _soc_th2_tcam_wrapper_table[i].enable_reg, 14035 SOC_INVALID_TCAM_PARITY_BIT, 14036 _soc_th2_tcam_wrapper_table[i].enable_field, 14037 _soc_th2_tcam_wrapper_table[i].mem, 14038 _soc_th2_tcam_wrapper_table[i].parity_field, 14039 MEM_BLOCK_ANY, REG_PORT_ANY, 14040 wrapper_at, 14041 mem_index, &test_data); 14042 14043 _soc_tomahawk_perform_ser_test(unit, 0, &test_data, test_type, 14044 &mem_skipped, &mem_failed); 14045 } 14046 } 14047 } 14048 #endif 14049 14050 #ifdef BCM_TOMAHAWK3_SUPPORT 14051 if (SOC_IS_TOMAHAWK3(unit) && soc_feature(unit, soc_feature_tcam_scan_engine)) { 14052 for (i = 0; _soc_bcm56980_a0_tcam_mem_ser_info[i].mem != INVALIDm; i++) { 14053 for (j = 0; th3_tcam_test_skipped_mems[j] != INVALIDm; j++) { 14054 if (th3_tcam_test_skipped_mems[j] == _soc_bcm56980_a0_tcam_mem_ser_info[i].mem) { 14055 skip = TRUE; 14056 break; 14057 } 14058 } 14059 if (skip == TRUE) { 14060 skip = FALSE; 14061 continue; 14062 } 14063 num_inst_to_test = NUM_PIPE(unit); 14064 if (test_type == SER_FIRST_HALF_PIPES) { 14065 start_at = _SOC_MEM_ADDR_ACC_TYPE_PIPE_0; 14066 num_inst_to_test /= 2; 14067 } 14068 if (test_type == SER_SECOND_HALF_PIPES) { 14069 start_at = _SOC_MEM_ADDR_ACC_TYPE_PIPE_4; 14070 num_inst_to_test /= 2; 14071 } 14072 for (wrapper_at = start_at; wrapper_at < (start_at + num_inst_to_test); wrapper_at++) { 14073 mem_tests++; 14074 if (!SOC_MEM_IS_VALID(unit, _soc_bcm56980_a0_tcam_mem_ser_info[i].mem) || 14075 (SOC_MEM_INFO(unit, _soc_bcm56980_a0_tcam_mem_ser_info[i].mem).flags & 14076 SOC_MEM_FLAG_SER_PARITY_ENABLE_SKIP)) { 14077 LOG_WARN(BSL_LS_SOC_SER, 14078 (BSL_META_U(unit, 14079 "unit %d, mem %s is INVALID or not valid " 14080 "or parity is disabled for this mem !!\n"), 14081 unit, SOC_MEM_NAME(unit, _soc_bcm56980_a0_tcam_mem_ser_info[i].mem))); 14082 mem_skipped++; 14083 continue; 14084 } 14085 14086 soc_ser_create_test_data_with_new_format(unit, tmp_entry, field_data, 14087 _soc_bcm56980_a0_tcam_mem_ser_info[i].enable_reg, 14088 INVALIDm, SOC_INVALID_TCAM_PARITY_BIT, 14089 _soc_bcm56980_a0_tcam_mem_ser_info[i].enable_field, 14090 -1, _soc_bcm56980_a0_tcam_mem_ser_info[i].mem, 14091 _soc_bcm56980_a0_tcam_mem_ser_info[i].parity_field, 14092 MEM_BLOCK_ANY, REG_PORT_ANY, wrapper_at, mem_index, 14093 &test_data); 14094 14095 _soc_tomahawk_perform_ser_test(unit, 0, &test_data, test_type, 14096 &mem_skipped, &mem_failed); 14097 } 14098 } 14099 } 14100 #endif 14101 14102 if (tcams != NULL) { 14103 for (i = 0; tcams[i].mem != INVALIDm; i++) { 14104 mem_tests++; 14105 if (!SOC_MEM_IS_VALID(unit, tcams[i].mem) || 14106 (SOC_MEM_INFO(unit, tcams[i].mem).flags & 14107 SOC_MEM_FLAG_SER_PARITY_ENABLE_SKIP)) { 14108 LOG_VERBOSE(BSL_LS_SOC_SER, 14109 (BSL_META_U(unit, 14110 "unit %d, mem %s is INVALID or not valid " 14111 "or parity is disabled for this mem !!\n"), 14112 unit, SOC_MEM_NAME(unit, tcams[i].mem))); 14113 mem_skipped++; 14114 continue; 14115 } 14116 /* Avoid re-testing tcams that are in dual mode - they are listed 14117 * twice in the tcams list */ 14118 if (tcams[i].ser_flags & _SOC_SER_FLAG_VIEW_DISABLE) { 14119 mem_skipped++; 14120 continue; 14121 } 14122 14123 acc_type = (tcams[i].ser_flags & _SOC_SER_FLAG_ACC_TYPE_MASK); 14124 14125 switch (tcams[i].mem) { 14126 case L3_DEFIPm: 14127 test_field = VALID0f; 14128 break; 14129 case L3_DEFIP_PAIR_128m: 14130 test_field = VALID0_LWRf; 14131 break; 14132 default: 14133 test_field = VALIDf; 14134 break; 14135 } 14136 14137 /* For tcams that can operate in either global/unique mode 14138 * find correct enable bit in SER_RANGE_ENABLEr */ 14139 tcam_parity_bit = 14140 (tcams[i].ser_dynamic_state == _SOC_SER_STATE_PIPE_MODE_UNIQUE)? 14141 (tcams[i].ser_hw_index + 1) : tcams[i].ser_hw_index; 14142 14143 soc_ser_create_test_data(unit, tmp_entry, field_data, SER_RANGE_ENABLEr, 14144 tcam_parity_bit, INVALIDf, tcams[i].mem, 14145 test_field, MEM_BLOCK_ANY, REG_PORT_ANY, 14146 acc_type, mem_index, &test_data); 14147 14148 _soc_tomahawk_perform_ser_test(unit, 0, &test_data, test_type, 14149 &mem_skipped, &mem_failed); 14150 14151 /* Note: for each entry in template[], above will perform 4 tests (one 14152 * per pipe) 14153 */ 14154 } 14155 } 14156 14157 LOG_CLI((BSL_META_U(unit, "\nTCAM memories tested on unit %d: %d\n"), 14158 unit, mem_tests - mem_skipped)); 14159 LOG_CLI((BSL_META_U(unit, "TCAM tests passed:\t%d\n"), 14160 mem_tests - mem_failed - mem_skipped)); 14161 LOG_VERBOSE(BSL_LS_SOC_SER, 14162 (BSL_META_U(unit, "TCAM tests skipped:\t%d \n"), 14163 0)); 14164 LOG_CLI((BSL_META_U(unit, "TCAM tests failed:\t%d\n\n"), mem_failed)); 14165 return mem_failed; 14166 } 14167 14168 STATIC int 14169 soc_th_ser_block_test(int unit, _soc_ser_test_t test_type, 14170 int *p_mem_failed, int *p_mem_tests, int *p_mem_skipped, 14171 _soc_mem_ser_en_info_t *ser_info_list, soc_block_t blocktype) 14172 { 14173 uint32 tmp_entry[SOC_MAX_MEM_WORDS], field_data[SOC_MAX_MEM_FIELD_WORDS]; 14174 ser_test_data_t test_data; 14175 int num_inst_to_test = 0; 14176 int i; 14177 uint32 mem_acc_type, flags = 0; 14178 soc_acc_type_t acc_type; 14179 int mem_index = 0; 14180 soc_mem_t en_mem = INVALIDm; 14181 soc_reg_t en_reg = INVALIDr; 14182 #if defined(_SER_DBG_EXIT_ON_FIRST_FAILURE) 14183 int rv = SOC_E_NONE; 14184 #endif 14185 14186 for (i = 0; ser_info_list[i].mem != INVALIDm; i++) { 14187 if (!SOC_MEM_IS_VALID(unit, ser_info_list[i].mem) || 14188 !soc_mem_index_count(unit, ser_info_list[i].mem) || 14189 (SOC_MEM_INFO(unit, ser_info_list[i].mem).flags & 14190 SOC_MEM_FLAG_SER_PARITY_ENABLE_SKIP)) { 14191 LOG_VERBOSE(BSL_LS_SOC_SER, 14192 (BSL_META_U( 14193 unit, 14194 "unit %d, mem %s is INVALID or not valid " 14195 "or parity is disabled for this mem !!\n"), 14196 unit, SOC_MEM_NAME(unit, ser_info_list[i].mem))); 14197 continue; 14198 } 14199 14200 if (!soc_feature(unit, soc_feature_advanced_flex_counter)) { 14201 if ((ser_info_list[i].mem >= ING_FLEX_CTR_COUNTER_TABLE_0m && 14202 ser_info_list[i].mem <= ING_FLEX_CTR_COUNTER_TABLE_9_PIPE3m) || 14203 (ser_info_list[i].mem >= EGR_FLEX_CTR_COUNTER_TABLE_0m && 14204 ser_info_list[i].mem <= EGR_FLEX_CTR_COUNTER_TABLE_3_Ym)) { 14205 continue; 14206 } 14207 } 14208 14209 flags = 0; /* for every mem */ 14210 mem_acc_type = SOC_MEM_ACC_TYPE(unit, ser_info_list[i].mem); 14211 #ifdef BCM_TOMAHAWK3_SUPPORT 14212 if (SOC_IS_TOMAHAWK3(unit) && (mem_acc_type <= _SOC_UNIQUE_ACC_TYPE_PIPE_7)) { 14213 if ((test_type == SER_FIRST_HALF_PIPES) && 14214 (mem_acc_type > _SOC_UNIQUE_ACC_TYPE_PIPE_3)) { 14215 continue; 14216 } 14217 if ((test_type == SER_SECOND_HALF_PIPES) && 14218 (mem_acc_type <= _SOC_UNIQUE_ACC_TYPE_PIPE_3)) { 14219 continue; 14220 } 14221 num_inst_to_test = 1; 14222 acc_type = mem_acc_type; 14223 } else 14224 #endif 14225 if (blocktype == SOC_BLK_MMU_GLB) { 14226 num_inst_to_test = 1; 14227 acc_type = _SOC_ACC_TYPE_PIPE_ANY; 14228 } else if (mem_acc_type <= _SOC_UNIQUE_ACC_TYPE_PIPE_3) { 14229 num_inst_to_test = 1; 14230 acc_type = mem_acc_type; 14231 } else if ((mem_acc_type == _SOC_TH_ACC_TYPE_ADDR_SPLIT_DIST) || 14232 (mem_acc_type == _SOC_TH_ACC_TYPE_ADDR_SPLIT_SPLIT)) { 14233 /* 14234 * For such mems, pipe is determined by address. 14235 * Ideally, we want to test all 4 pipes, but as 14236 * simplification, we may test only 3 instances if tr test 14237 * is being run with T=spread option (because addr=0 means 14238 * pipe0, addr=last means pipe3 and addr=last/2 means 14239 * pipe1/pipe2 14240 */ 14241 num_inst_to_test = 1; 14242 acc_type = _SOC_ACC_TYPE_PIPE_ANY; 14243 } else { 14244 /* test all instances */ 14245 num_inst_to_test = NUM_PIPE(unit); 14246 acc_type = _SOC_UNIQUE_ACC_TYPE_PIPE_0; 14247 #ifdef BCM_TOMAHAWK3_SUPPORT 14248 if (SOC_IS_TOMAHAWK3(unit)) { 14249 if (test_type == SER_FIRST_HALF_PIPES) { 14250 num_inst_to_test /= 2; 14251 } 14252 if (test_type == SER_SECOND_HALF_PIPES) { 14253 num_inst_to_test /= 2; 14254 acc_type = _SOC_UNIQUE_ACC_TYPE_PIPE_4; 14255 } 14256 } 14257 #endif 14258 } 14259 *p_mem_tests += num_inst_to_test; 14260 test_data.test_field = ECCf; 14261 en_reg = ser_info_list[i].en_ctrl.flag_reg_mem ? INVALIDr : 14262 ser_info_list[i].en_ctrl.ctrl_type.en_reg; 14263 en_mem = ser_info_list[i].en_ctrl.flag_reg_mem ? 14264 ser_info_list[i].en_ctrl.ctrl_type.en_mem : INVALIDm; 14265 soc_ser_create_test_data_with_new_format(unit, tmp_entry, field_data, 14266 en_reg, en_mem, SOC_INVALID_TCAM_PARITY_BIT, 14267 ser_info_list[i].en_ctrl.en_fld, 14268 ser_info_list[i].en_ctrl.en_fld_position, 14269 ser_info_list[i].mem, 14270 test_data.test_field, MEM_BLOCK_ANY, 14271 REG_PORT_ANY, acc_type, mem_index, 14272 &test_data); 14273 if (test_data.mem_info == NULL) { 14274 *p_mem_skipped += num_inst_to_test; 14275 LOG_VERBOSE(BSL_LS_SOC_SER, 14276 (BSL_META_U(unit, 14277 "Memory %s skipped due to lack of" 14278 " mem_info structure.\n"), 14279 SOC_MEM_NAME(unit,test_data.mem))); 14280 continue; 14281 } 14282 if ((SOC_REG_IS_VALID(unit, ser_info_list[i].ecc1b_ctrl.ctrl_type.en_reg) || 14283 SOC_MEM_IS_VALID(unit, ser_info_list[i].ecc1b_ctrl.ctrl_type.en_mem)) && 14284 (INVALIDf != ser_info_list[i].ecc1b_ctrl.en_fld)) { 14285 flags |= SOC_INJECT_ERROR_2BIT_ECC; 14286 } 14287 #if defined(_SER_DBG_EXIT_ON_FIRST_FAILURE) 14288 rv = _soc_tomahawk_perform_ser_test(unit, flags, &test_data, test_type, 14289 p_mem_skipped, p_mem_failed); 14290 if (SOC_FAILURE(rv)) { 14291 return SOC_E_FAIL; 14292 } 14293 #else 14294 _soc_tomahawk_perform_ser_test(unit, flags, &test_data, test_type, 14295 p_mem_skipped, p_mem_failed); 14296 #endif 14297 if (num_inst_to_test > 1) { 14298 for (test_data.acc_type = (acc_type + 1); 14299 test_data.acc_type < (acc_type + num_inst_to_test); 14300 test_data.acc_type++) { 14301 #if defined(_SER_DBG_EXIT_ON_FIRST_FAILURE) 14302 rv = _soc_tomahawk_perform_ser_test(unit, flags, &test_data, 14303 test_type, 14304 p_mem_skipped, 14305 p_mem_failed); 14306 if (SOC_FAILURE(rv)) { 14307 return SOC_E_FAIL; 14308 } 14309 #else 14310 _soc_tomahawk_perform_ser_test(unit, flags, &test_data, 14311 test_type, 14312 p_mem_skipped, 14313 p_mem_failed); 14314 #endif 14315 } 14316 } 14317 } 14318 14319 return SOC_E_NONE; 14320 } 14321 14322 /* #define _SER_DBG_EXIT_ON_FIRST_FAILURE */ 14323 /* 14324 * Function: 14325 * soc_th_ser_hardware_test 14326 * Purpose: 14327 * Tests that SER is working for fio and SRAM memories 14328 * Parameters: 14329 * unit - (IN) Device Number 14330 * test_type - (IN) How many indices to test for each memory 14331 * Returns: 14332 * the number of tests which are failed 14333 */ 14334 STATIC int 14335 soc_th_ser_hardware_test(int unit, _soc_ser_test_t test_type) { 14336 int mem_failed = 0, mem_tests = 0, mem_skipped = 0 ; 14337 int rv = SOC_E_NONE; 14338 14339 (void) _soc_th_refresh_modify(unit, 0); /* disable refresh */ 14340 14341 rv = soc_th_ser_block_test(unit, test_type, &mem_failed, &mem_tests, &mem_skipped, 14342 SOC_IP_MEM_SER_INFO(unit), SOC_BLK_IPIPE); 14343 14344 14345 #if defined(_SER_DBG_EXIT_ON_FIRST_FAILURE) 14346 if (SOC_SUCCESS(rv)) 14347 #endif 14348 { 14349 rv = soc_th_ser_block_test(unit, test_type, &mem_failed, &mem_tests, &mem_skipped, 14350 SOC_EP_MEM_SER_INFO(unit), SOC_BLK_EPIPE); 14351 } 14352 14353 #if defined(_SER_DBG_EXIT_ON_FIRST_FAILURE) 14354 if (SOC_SUCCESS(rv)) 14355 #endif 14356 { 14357 rv = soc_th_ser_block_test(unit, test_type, &mem_failed, &mem_tests, &mem_skipped, 14358 SOC_MMU_MEM_SER_INFO(unit), SOC_BLK_MMU_GLB); 14359 } 14360 14361 if (SOC_FAILURE(rv)) { 14362 LOG_CLI((BSL_META_U(unit, "H/W memories test fail.\n"))); 14363 } else { 14364 LOG_CLI((BSL_META_U(unit, "H/W memories test success.\n"))); 14365 } 14366 14367 LOG_CLI((BSL_META_U(unit, "\nH/W memories tested on unit %d: %d\n"), 14368 unit, mem_tests - mem_skipped)); 14369 LOG_CLI((BSL_META_U(unit, "H/W memories tests passed:\t%d\n"), 14370 mem_tests - mem_failed - mem_skipped)); 14371 LOG_VERBOSE(BSL_LS_SOC_SER, 14372 (BSL_META_U(unit, "H/W memories tests skipped:\t%d \n"), 14373 0)); 14374 LOG_CLI((BSL_META_U(unit, "H/W memories tests failed:\t%d\n\n"), mem_failed)); 14375 (void) _soc_th_refresh_modify(unit, 1); /* re-enable refresh */ 14376 return mem_failed; 14377 } 14378 14379 soc_error_t 14380 soc_thx_ser_idb_parity_control_check(int unit, _soc_th_ser_info_t *info_list) 14381 { 14382 _soc_th_ser_info_t *info; 14383 int i, j; 14384 int match = 0; 14385 uint32 value = 0; 14386 uint32 rval = 0; 14387 uint64 rval64; 14388 soc_reg_t reg = INVALIDr; 14389 soc_field_t field = INVALIDf; 14390 uint32 total_count = 0; 14391 uint32 pass_count = 0; 14392 14393 for (i = 0; ; i++) { 14394 info = &info_list[i]; 14395 if (info->type == _SOC_PARITY_TYPE_NONE) { 14396 break; 14397 } 14398 14399 reg = info->enable_reg; 14400 if (info->enable_field_list == NULL) { 14401 field = info->enable_field; 14402 if (!soc_reg_field_valid(unit, reg, field)) { 14403 continue; 14404 } 14405 if (SOC_REG_IS_64(unit,reg)) { 14406 COMPILER_64_ZERO(rval64); 14407 SOC_IF_ERROR_RETURN(soc_reg_get(unit, reg, REG_PORT_ANY, 0, &rval64)); 14408 value = soc_reg64_field32_get(unit, reg, rval64, field); 14409 } else { 14410 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, reg, REG_PORT_ANY, 0, &rval)); 14411 value = soc_reg_field_get(unit, reg, rval, field); 14412 } 14413 if (0 == value) { 14414 match = 0; 14415 LOG_WARN(BSL_LS_SOC_SER, 14416 (BSL_META_U(unit, 14417 "parity control %s.%s is disabled !!\n"), 14418 SOC_REG_NAME(unit, reg), 14419 SOC_FIELD_NAME(unit, field))); 14420 } else { 14421 match = 1; 14422 } 14423 total_count++; 14424 if (match) { 14425 pass_count++; 14426 } 14427 } else { 14428 if (SOC_REG_IS_VALID(unit, reg)) { 14429 if (SOC_REG_IS_64(unit, reg)) { 14430 COMPILER_64_ZERO(rval64); 14431 SOC_IF_ERROR_RETURN(soc_reg_get(unit, reg, REG_PORT_ANY, 0, &rval64)); 14432 } else { 14433 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, reg, REG_PORT_ANY, 0, &rval)); 14434 } 14435 for (j = 0; ; j++) { 14436 if (info->enable_field_list[j] == INVALIDf) { 14437 break; 14438 } 14439 field = info->enable_field_list[j]; 14440 if (!soc_reg_field_valid(unit, reg, field)) { 14441 continue; 14442 } 14443 if (SOC_REG_IS_64(unit,reg)) { 14444 value = soc_reg64_field32_get(unit, reg, rval64, field); 14445 } else { 14446 value = soc_reg_field_get(unit, reg, rval, field); 14447 } 14448 if (0 == value) { 14449 match = 0; 14450 LOG_WARN(BSL_LS_SOC_SER, 14451 (BSL_META_U(unit, 14452 "parity control %s.%s is disabled !!\n"), 14453 SOC_REG_NAME(unit, reg), 14454 SOC_FIELD_NAME(unit, field))); 14455 } else { 14456 match = 1; 14457 } 14458 total_count++; 14459 if (match) { 14460 pass_count++; 14461 } 14462 } 14463 } 14464 } 14465 } 14466 LOG_CLI((BSL_META_U(unit, "\nIDB parity control checked on unit %d: %d\n"), 14467 unit, total_count)); 14468 LOG_CLI((BSL_META_U(unit, "Passed fields:\t%d\n"), pass_count)); 14469 LOG_CLI((BSL_META_U(unit, "Failed fields::\t%d\n\n"), (total_count - pass_count))); 14470 14471 return SOC_E_NONE; 14472 } 14473 14474 #define THx_XLPORT_INFO 0 14475 #define THx_CLPORT_INFO 1 14476 #define THx_CDPORT_INFO 2 14477 soc_error_t 14478 soc_thx_ser_port_parity_control_check(int unit, _soc_th_ser_info_t *info_list, int type) 14479 { 14480 int i, j; 14481 int match = 0; 14482 int port; 14483 soc_info_t *si = &SOC_INFO(unit); 14484 _soc_th_ser_info_t *info; 14485 soc_reg_t reg = INVALIDr; 14486 soc_field_t field = INVALIDf; 14487 uint32 value = 0; 14488 uint32 rval = 0; 14489 uint64 rval64; 14490 uint32 total_count = 0; 14491 uint32 pass_count = 0; 14492 14493 for (i = 0; ; i++) { 14494 info = &info_list[i]; 14495 if (info->type == _SOC_PARITY_TYPE_NONE) { 14496 break; 14497 } 14498 14499 reg = info->enable_reg; 14500 if (SOC_REG_IS_VALID(unit, reg)) { 14501 PBMP_PORT_ITER(unit, port) { 14502 if ((SOC_PBMP_MEMBER(si->management_pbm, port) && (type != THx_XLPORT_INFO)) || 14503 (!SOC_PBMP_MEMBER(si->management_pbm, port) && (type == THx_XLPORT_INFO))) { 14504 continue; 14505 } 14506 if (info->enable_field_list == NULL) { 14507 field = info->enable_field; 14508 if (SOC_REG_IS_64(unit,reg)) { 14509 COMPILER_64_ZERO(rval64); 14510 SOC_IF_ERROR_RETURN(soc_reg_get(unit, reg, port, 0, &rval64)); 14511 value = soc_reg64_field32_get(unit, reg, rval64, field); 14512 } else { 14513 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, reg, port, 0, &rval)); 14514 value = soc_reg_field_get(unit, reg, rval, field); 14515 } 14516 if (0 == value) { 14517 match = 0; 14518 LOG_WARN(BSL_LS_SOC_SER, 14519 (BSL_META_U(unit, 14520 "parity control %s.%s is disabled !!\n"), 14521 SOC_REG_NAME(unit, reg), 14522 SOC_FIELD_NAME(unit, field))); 14523 } else { 14524 match = 1; 14525 } 14526 total_count++; 14527 if (match) { 14528 pass_count++; 14529 } 14530 } else { 14531 if (SOC_REG_IS_64(unit,reg)) { 14532 COMPILER_64_ZERO(rval64); 14533 SOC_IF_ERROR_RETURN(soc_reg_get(unit, reg, port, 0, &rval64)); 14534 } else { 14535 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, reg, port, 0, &rval)); 14536 } 14537 for (j = 0; ; j++) { 14538 if (info->enable_field_list[j] == INVALIDf) { 14539 break; 14540 } 14541 field = info->enable_field_list[j]; 14542 if (SOC_REG_IS_64(unit,reg)) { 14543 value = soc_reg64_field32_get(unit, reg, rval64, field); 14544 } else { 14545 value = soc_reg_field_get(unit, reg, rval, field); 14546 } 14547 if (0 == value) { 14548 match = 0; 14549 LOG_WARN(BSL_LS_SOC_SER, 14550 (BSL_META_U(unit, 14551 "parity control %s.%s is disabled !!\n"), 14552 SOC_REG_NAME(unit, reg), 14553 SOC_FIELD_NAME(unit, field))); 14554 } else { 14555 match = 1; 14556 } 14557 total_count++; 14558 if (match) { 14559 pass_count++; 14560 } 14561 } 14562 } 14563 } 14564 } 14565 } 14566 LOG_CLI((BSL_META_U(unit, "\nPort parity control checked on unit %d: %d\n"), 14567 unit, total_count)); 14568 LOG_CLI((BSL_META_U(unit, "Passed fields:\t%d\n"), pass_count)); 14569 LOG_CLI((BSL_META_U(unit, "Failed fields::\t%d\n\n"), (total_count - pass_count))); 14570 14571 return SOC_E_NONE; 14572 } 14573 14574 void 14575 soc_thx_ser_parity_control_check_all(int unit) 14576 { 14577 (void)soc_ser_test_parity_control_check(unit, _SOC_SER_TYPE_MEM, 14578 (void*) SOC_IP_MEM_SER_INFO(unit)); 14579 (void)soc_ser_test_parity_control_check(unit, _SOC_SER_TYPE_MEM, 14580 (void*) SOC_EP_MEM_SER_INFO(unit)); 14581 (void)soc_ser_test_parity_control_check(unit, _SOC_SER_TYPE_MEM, 14582 (void*) SOC_MMU_MEM_SER_INFO(unit)); 14583 (void)soc_ser_test_parity_control_check(unit, _SOC_SER_TYPE_REG, 14584 (void*) SOC_IP_REG_SER_INFO(unit)); 14585 (void)soc_ser_test_parity_control_check(unit, _SOC_SER_TYPE_REG, 14586 (void*) SOC_EP_REG_SER_INFO(unit)); 14587 #if defined(BCM_TOMAHAWK3_SUPPORT) && defined(BCM_56980_A0) 14588 if (SOC_IS_TOMAHAWK3(unit)) { 14589 (void)soc_ser_test_parity_control_check(unit, _SOC_SER_TYPE_BUS, 14590 (void*) _soc_bcm56980_a0_ip_bus_ser_info); 14591 (void)soc_ser_test_parity_control_check(unit, _SOC_SER_TYPE_BUS, 14592 (void*) _soc_bcm56980_a0_ep_bus_ser_info); 14593 (void)soc_ser_test_parity_control_check(unit, _SOC_SER_TYPE_BUF, 14594 (void*) _soc_bcm56980_a0_ip_buffer_ser_info); 14595 (void)soc_ser_test_parity_control_check(unit, _SOC_SER_TYPE_BUF, 14596 (void*) _soc_bcm56980_a0_ep_buffer_ser_info); 14597 (void)soc_thx_ser_idb_parity_control_check(unit, _soc_th3_idb_ser_info); 14598 (void)soc_thx_ser_port_parity_control_check(unit, _soc_th3_pm_cdp_ser_info, THx_CDPORT_INFO); 14599 (void)soc_thx_ser_port_parity_control_check(unit, _soc_th3_pm_xlp_ser_info, THx_XLPORT_INFO); 14600 } 14601 #endif 14602 #if defined(BCM_TOMAHAWK2_SUPPORT) && defined(BCM_56970_A0) 14603 if (SOC_IS_TOMAHAWK2(unit)) { 14604 (void)soc_ser_test_parity_control_check(unit, _SOC_SER_TYPE_BUS, 14605 (void*) _soc_bcm56970_a0_ip_bus_ser_info); 14606 (void)soc_ser_test_parity_control_check(unit, _SOC_SER_TYPE_BUS, 14607 (void*) _soc_bcm56970_a0_ep_bus_ser_info); 14608 (void)soc_ser_test_parity_control_check(unit, _SOC_SER_TYPE_BUF, 14609 (void*) _soc_bcm56970_a0_ip_buffer_ser_info); 14610 (void)soc_ser_test_parity_control_check(unit, _SOC_SER_TYPE_BUF, 14611 (void*) _soc_bcm56970_a0_ep_buffer_ser_info); 14612 (void)soc_thx_ser_idb_parity_control_check(unit, _soc_th2_idb_ser_info); 14613 (void)soc_thx_ser_port_parity_control_check(unit, _soc_th2_pm_clp_ser_info, THx_CLPORT_INFO); 14614 (void)soc_thx_ser_port_parity_control_check(unit, _soc_th2_pm_xlp_ser_info, THx_XLPORT_INFO); 14615 } 14616 #endif 14617 if (SOC_IS_TOMAHAWK(unit)) { 14618 (void)soc_ser_test_parity_control_check(unit, _SOC_SER_TYPE_BUS, 14619 (void*) _soc_th_ip_bus_ser_info); 14620 (void)soc_ser_test_parity_control_check(unit, _SOC_SER_TYPE_BUS, 14621 (void*) _soc_th_ep_bus_ser_info); 14622 (void)soc_ser_test_parity_control_check(unit, _SOC_SER_TYPE_BUF, 14623 (void*) _soc_th_ip_buffer_ser_info); 14624 (void)soc_ser_test_parity_control_check(unit, _SOC_SER_TYPE_BUF, 14625 (void*) _soc_th_ep_buffer_ser_info); 14626 (void)soc_thx_ser_port_parity_control_check(unit, _soc_th_pm_clp_ser_info, THx_CLPORT_INFO); 14627 (void)soc_thx_ser_port_parity_control_check(unit, _soc_th_pm_xlp_ser_info, THx_XLPORT_INFO); 14628 } 14629 } 14630 14631 /* 14632 * Function: 14633 * soc_th_ser_test 14634 * Purpose: 14635 * Tests that SER is working for all supported memories. 14636 * Parameters: 14637 * unit - (IN) Device Number 14638 * test_type - (IN) How many indices to test for each memory 14639 * Returns: 14640 * SOC_E_NONE if test passes, an error otherwise (multiple types of errors are 14641 * possible.) 14642 */ 14643 STATIC soc_error_t 14644 soc_th_ser_test(int unit, _soc_ser_test_t test_type) { 14645 int errors = 0; 14646 int def_soc_ser_test_long_sleep; 14647 int def_soc_ser_test_long_sleep_time_us; 14648 14649 /* save default values, choose TH specific values */ 14650 def_soc_ser_test_long_sleep = soc_ser_test_long_sleep; 14651 def_soc_ser_test_long_sleep_time_us = soc_ser_test_long_sleep_time_us; 14652 soc_ser_test_long_sleep = TRUE; 14653 soc_ser_test_long_sleep_time_us = 14654 soc_property_get(unit, "tr144_long_sleep_time_us", 14655 _SOC_TH_TR144_LONG_SLEEP_TIME_US); 14656 14657 LOG_VERBOSE(BSL_LS_SOC_SER, 14658 (BSL_META_U(unit, 14659 "tr 144 test will use:long_sleep = %d," 14660 "long_sleep_time = %d uS\n"), 14661 soc_ser_test_long_sleep, 14662 soc_ser_test_long_sleep_time_us)); 14663 14664 /* Check parity controls before testing */ 14665 soc_thx_ser_parity_control_check_all(unit); 14666 /*Test TCAM memories*/ 14667 errors += soc_th_ser_tcam_test(unit, test_type); 14668 /*Test for FIFO memories*/ 14669 errors += soc_th_ser_hardware_test(unit, test_type); 14670 14671 /* restore default values */ 14672 soc_ser_test_long_sleep = def_soc_ser_test_long_sleep; 14673 soc_ser_test_long_sleep_time_us = def_soc_ser_test_long_sleep_time_us; 14674 14675 if (errors == 0) { 14676 return SOC_E_NONE; 14677 } else { 14678 LOG_CLI((BSL_META_U(unit, 14679 "TR 144 test failed.\n"))); 14680 return SOC_E_FAIL; 14681 } 14682 } 14683 14684 void 14685 soc_th_ser_test_register(int unit) 14686 { 14687 /*Initialize chip-specific functions for SER testing*/ 14688 memset(&ser_tomahawk_test_fun, 0, sizeof(soc_ser_test_functions_t)); 14689 ser_tomahawk_test_fun.inject_error_f = &soc_th_ser_inject_error; 14690 ser_tomahawk_test_fun.test_mem = &soc_th_ser_test_mem; 14691 ser_tomahawk_test_fun.test = &soc_th_ser_test; 14692 ser_tomahawk_test_fun.parity_control = &soc_th_parity_control_reg_set; 14693 ser_tomahawk_test_fun.injection_support = &_ser_th_ser_error_injection_support; 14694 ser_tomahawk_test_fun.correction_info_get = &_ser_th_correction_info_get; 14695 soc_ser_test_functions_register(unit, &ser_tomahawk_test_fun); 14696 } 14697 14698 #endif /*defined(SER_TR_TEST_SUPPORT)*/ 14699 14700 #ifdef BCM_TOMAHAWK2_SUPPORT 14701 int 14702 soc_th2_tcam_engine_enable(int unit, int enable) 14703 { 14704 uint64 config; 14705 COMPILER_64_ZERO(config); 14706 14707 if (enable) { 14708 SOC_IF_ERROR_RETURN(soc_reg_field32_modify 14709 (unit, AUX_ARB_CONTROLr, REG_PORT_ANY, FP_REFRESH_ENABLEf, 1)); 14710 14711 soc_reg64_field32_set(unit, IDB_SER_SCAN_CONFIGr, &config, START_IDXf, 0); 14712 soc_reg64_field32_set(unit, IDB_SER_SCAN_CONFIGr, &config, MAX_IDXf, 1023); 14713 soc_reg64_field32_set(unit, IDB_SER_SCAN_CONFIGr, &config, OP_BLOCKf, 0); 14714 soc_reg64_field32_set(unit, IDB_SER_SCAN_CONFIGr, &config, INTERVALf, 64); 14715 soc_reg64_field32_set(unit, IDB_SER_SCAN_CONFIGr, &config, ENABLEf, 1); 14716 SOC_IF_ERROR_RETURN(soc_reg64_set 14717 (unit, IDB_SER_SCAN_CONFIGr, REG_PORT_ANY, 0, config)); 14718 } else { 14719 SOC_IF_ERROR_RETURN(soc_reg_field32_modify 14720 (unit, AUX_ARB_CONTROLr, REG_PORT_ANY, FP_REFRESH_ENABLEf, 0)); 14721 14722 soc_reg64_field32_set(unit, IDB_SER_SCAN_CONFIGr, &config, START_IDXf, 0); 14723 soc_reg64_field32_set(unit, IDB_SER_SCAN_CONFIGr, &config, MAX_IDXf, 1023); 14724 soc_reg64_field32_set(unit, IDB_SER_SCAN_CONFIGr, &config, OP_BLOCKf, 0); 14725 soc_reg64_field32_set(unit, IDB_SER_SCAN_CONFIGr, &config, INTERVALf, 64); 14726 soc_reg64_field32_set(unit, IDB_SER_SCAN_CONFIGr, &config, ENABLEf, 0); 14727 SOC_IF_ERROR_RETURN(soc_reg64_set 14728 (unit, IDB_SER_SCAN_CONFIGr, REG_PORT_ANY, 0, config)); 14729 } 14730 14731 return SOC_E_NONE; 14732 } 14733 14734 STATIC soc_error_t _soc_th2_ser_tcam_wrapper_found(soc_mem_t mem) 14735 { 14736 int i; 14737 for (i = 0; _soc_th2_tcam_wrapper_table[i].mem != INVALIDm; i++) { 14738 if (_soc_th2_tcam_wrapper_table[i].mem == mem) { 14739 return SOC_E_NONE; /* found */ 14740 } 14741 } 14742 return SOC_E_UNAVAIL; 14743 } 14744 14745 STATIC soc_error_t 14746 _soc_th2_ser_tcam_control_reg_get(soc_mem_t mem, soc_reg_t *ser_control_reg, 14747 soc_field_t *ser_enable_field) 14748 { 14749 int i; 14750 for (i = 0; _soc_th2_tcam_wrapper_table[i].mem != INVALIDm; i++) { 14751 if (_soc_th2_tcam_wrapper_table[i].mem == mem) { 14752 *ser_control_reg = _soc_th2_tcam_wrapper_table[i].enable_reg; 14753 *ser_enable_field = _soc_th2_tcam_wrapper_table[i].enable_field; 14754 return SOC_E_NONE; /* found */ 14755 } 14756 } 14757 return SOC_E_UNAVAIL; 14758 } 14759 14760 STATIC soc_error_t _soc_th2_tcam_wrapper_enable(int unit, int enable) 14761 { 14762 int i; 14763 uint32 val = 0; 14764 soc_reg_t ser_control_reg; 14765 soc_field_t ser_enable_field; 14766 14767 for (i = 0; _soc_th2_tcam_wrapper_table[i].mem != INVALIDm; i++) { 14768 ser_control_reg = _soc_th2_tcam_wrapper_table[i].enable_reg; 14769 ser_enable_field = _soc_th2_tcam_wrapper_table[i].enable_field; 14770 14771 SOC_IF_ERROR_RETURN 14772 (soc_reg32_get(unit, ser_control_reg, REG_PORT_ANY, 0, &val)); 14773 soc_reg_field_set(unit, ser_control_reg, &val, ser_enable_field, enable ? 1 : 0); 14774 SOC_IF_ERROR_RETURN 14775 (soc_reg32_set(unit, ser_control_reg, REG_PORT_ANY, 0, val)); 14776 } 14777 return SOC_E_NONE; 14778 } 14779 14780 int 14781 soc_th2_vfp_ser_correction(int unit, soc_mem_t mem, int index, int copyno, int entry_dw) 14782 { 14783 int rv = SOC_E_NONE; 14784 int i = 0; 14785 uint32 entry[SOC_MAX_MEM_WORDS], *cache = NULL; 14786 uint8 *vmap; 14787 void *null_entry = NULL; 14788 14789 if (copyno < 0) { 14790 return SOC_E_INTERNAL; 14791 } 14792 cache = SOC_MEM_STATE(unit, mem).cache[copyno]; 14793 vmap = SOC_MEM_STATE(unit, mem).vmap[copyno]; 14794 14795 index = index % 128; 14796 for (i = 0; i < 8; i++) { 14797 MEM_LOCK(unit, mem); 14798 if (cache != NULL && CACHE_VMAP_TST(vmap, index)) { 14799 sal_memcpy(entry, cache + index * entry_dw, entry_dw * 4); 14800 if ((rv = soc_mem_write(unit, mem, copyno, index, entry)) < 0) { 14801 LOG_ERROR(BSL_LS_SOC_SER, 14802 (BSL_META_U(unit, 14803 "CACHE_RESTORE %s.%s[%d] failed: %s\n"), 14804 SOC_MEM_NAME(unit, mem), 14805 SOC_BLOCK_NAME(unit, copyno), 14806 index, soc_errmsg(rv))); 14807 } 14808 } else { 14809 null_entry = soc_mem_entry_null(unit, mem); 14810 if ((rv = soc_mem_write(unit, mem, copyno, index, null_entry)) < 0) { 14811 LOG_ERROR(BSL_LS_SOC_SER, 14812 (BSL_META_U(unit, 14813 "CLEAR_RESTORE %s.%s[%d] failed: %s\n"), 14814 SOC_MEM_NAME(unit, mem), 14815 SOC_BLOCK_NAME(unit, copyno), 14816 index, soc_errmsg(rv))); 14817 } 14818 } 14819 MEM_UNLOCK(unit, mem); 14820 index += 128; 14821 } 14822 return rv;} 14823 #endif /* BCM_TOMAHAWK2_SUPPORT */ 14824 14825 #if defined(BCM_TOMAHAWK3_SUPPORT) 14826 int 14827 soc_th3_check_scrub_info(int unit, soc_mem_t mem, int blk, int copyno, 14828 int *num_inst_to_scrub, int *acc_type_list) 14829 { 14830 int mem_acc_type = SOC_MEM_ACC_TYPE(unit, mem); 14831 int mmu_base_type, mmu_base_index; 14832 soc_block_t blk_type; 14833 14834 if (copyno == COPYNO_ALL) { 14835 return SOC_E_PARAM; 14836 } 14837 blk_type = SOC_BLOCK_TYPE(unit, copyno); 14838 14839 if ((NULL == acc_type_list) || (NULL == num_inst_to_scrub)) { 14840 return SOC_E_PARAM; 14841 } 14842 14843 *num_inst_to_scrub = 0; 14844 14845 if (!SOC_MEM_IS_VALID(unit,mem)) { 14846 return SOC_E_NONE; 14847 } 14848 14849 /* L3_DEFIPm/L3_DEFIP_PAIR_128m should be scrubed */ 14850 if ((mem == L3_DEFIP_LEVEL1m) || (mem == L3_DEFIP_PAIR_LEVEL1m)) { 14851 *num_inst_to_scrub = NUM_PIPE(unit); 14852 acc_type_list[0] = _SOC_TH_ACC_TYPE_UNIQUE_PIPE0; 14853 acc_type_list[1] = _SOC_TH_ACC_TYPE_UNIQUE_PIPE1; 14854 acc_type_list[2] = _SOC_TH_ACC_TYPE_UNIQUE_PIPE2; 14855 acc_type_list[3] = _SOC_TH_ACC_TYPE_UNIQUE_PIPE3; 14856 acc_type_list[4] = _SOC_TH_ACC_TYPE_UNIQUE_PIPE4; 14857 acc_type_list[5] = _SOC_TH_ACC_TYPE_UNIQUE_PIPE5; 14858 acc_type_list[6] = _SOC_TH_ACC_TYPE_UNIQUE_PIPE6; 14859 acc_type_list[7] = _SOC_TH_ACC_TYPE_UNIQUE_PIPE7; 14860 } 14861 14862 if (mem == EXACT_MATCH_2m || mem == EXACT_MATCH_4m || 14863 mem == EXACT_MATCH_ECCm || mem == L3_DEFIP_ALPM_LEVEL3_ECCm || 14864 mem == L3_DEFIP_ALPM_LEVEL3_SINGLEm || mem == L3_DEFIP_ALPM_LEVEL3m) { 14865 *num_inst_to_scrub = 2; 14866 acc_type_list[0] = _SOC_TH_ACC_TYPE_UNIQUE_PIPE0; 14867 acc_type_list[1] = _SOC_TH_ACC_TYPE_UNIQUE_PIPE4; 14868 } 14869 14870 if (mem == EGR_L3_NEXT_HOPm || mem == L3_DEFIP_ALPM_LEVEL2_SINGLEm || 14871 mem == L3_DEFIP_ALPM_LEVEL2m || mem == L3_DEFIP_ALPM_LEVEL2_ECCm) { 14872 *num_inst_to_scrub = 4; 14873 acc_type_list[0] = _SOC_TH_ACC_TYPE_UNIQUE_PIPE0; 14874 acc_type_list[1] = _SOC_TH_ACC_TYPE_UNIQUE_PIPE3; 14875 acc_type_list[2] = _SOC_TH_ACC_TYPE_UNIQUE_PIPE4; 14876 acc_type_list[3] = _SOC_TH_ACC_TYPE_UNIQUE_PIPE7; 14877 } 14878 14879 if (((mem_acc_type == _SOC_TH_ACC_TYPE_DUPLICATE) && 14880 ((blk_type == SOC_BLK_IPIPE) || (blk_type == SOC_BLK_EPIPE)) && 14881 (SOC_MEM_UNIQUE_ACC(unit, mem) == NULL)) || 14882 SOC_TH_MEM_CHK_TCAM_GLOBAL_UNIQUE_MODE(mem)) { 14883 /* 2nd last term: sw has not already created per-instance unique views */ 14884 *num_inst_to_scrub = NUM_PIPE(unit); 14885 acc_type_list[0] = _SOC_TH_ACC_TYPE_UNIQUE_PIPE0; 14886 acc_type_list[1] = _SOC_TH_ACC_TYPE_UNIQUE_PIPE1; 14887 acc_type_list[2] = _SOC_TH_ACC_TYPE_UNIQUE_PIPE2; 14888 acc_type_list[3] = _SOC_TH_ACC_TYPE_UNIQUE_PIPE3; 14889 acc_type_list[4] = _SOC_TH_ACC_TYPE_UNIQUE_PIPE4; 14890 acc_type_list[5] = _SOC_TH_ACC_TYPE_UNIQUE_PIPE5; 14891 acc_type_list[6] = _SOC_TH_ACC_TYPE_UNIQUE_PIPE6; 14892 acc_type_list[7] = _SOC_TH_ACC_TYPE_UNIQUE_PIPE7; 14893 LOG_VERBOSE(BSL_LS_SOC_SER, (BSL_META_U(unit, "scrub: mem.blk.blk_type %s.%d.%d has acc_type = %s (%d), num_inst_to_scrub = %0d\n"), 14894 SOC_MEM_NAME(unit,mem), blk, blk_type, 14895 _SOC_TH_ACC_TYPE_NAME(mem_acc_type), mem_acc_type, 14896 *num_inst_to_scrub)); 14897 return SOC_E_NONE; 14898 } /* need_per_pipe_scrub */ 14899 14900 if ((mem_acc_type == _SOC_TH_ACC_TYPE_DUPLICATE) && 14901 ((blk_type == SOC_BLK_MMU_GLB) || 14902 (blk_type == SOC_BLK_MMU_ITM) || 14903 (blk_type == SOC_BLK_MMU_EB))) { 14904 14905 mmu_base_type = SOC_MEM_BASE_TYPE(unit, mem); 14906 14907 14908 switch (blk_type) { 14909 case SOC_BLK_MMU_ITM: 14910 switch (mmu_base_type) { 14911 case SOC_TH3_MMU_BASE_TYPE_IPIPE: 14912 mmu_base_index = _SOC_MMU_BASE_INDEX(unit, mem, 0x7); 14913 if ((mmu_base_index == 0) || (mmu_base_index == 1) || 14914 (mmu_base_index == 2) || (mmu_base_index == 3)) { 14915 /* ipipe0-3 serviced by ITM0 */ 14916 *num_inst_to_scrub = 1; 14917 acc_type_list[0] = 0; 14918 } else { 14919 /* ipipe4-7 serviced by ITM1 */ 14920 *num_inst_to_scrub = 1; 14921 acc_type_list[0] = 1; 14922 } 14923 break; 14924 case SOC_TH3_MMU_BASE_TYPE_EPIPE: 14925 /* epipe0-7 serviced by both ITM0,1 */ 14926 *num_inst_to_scrub = 2; 14927 acc_type_list[0] = 0; 14928 acc_type_list[1] = 1; 14929 break; 14930 case SOC_TH3_MMU_BASE_TYPE_CHIP: 14931 /* must read each xpe instance */ 14932 *num_inst_to_scrub = 2; 14933 acc_type_list[0] = 0; 14934 acc_type_list[1] = 1; 14935 break; 14936 default: /* IPORT, EPORT, ITM */ 14937 /* should not find any TH3 MMU memories here */ 14938 LOG_ERROR(BSL_LS_SOC_SER, (BSL_META_U(unit, "scrub_ERROR: mem.blk.blk_type %s.%d.%d has acc_type = %s (%d), num_inst_to_scrub = %0d, mmu_base_type = %0d\n"), 14939 SOC_MEM_NAME(unit,mem), blk, blk_type, 14940 _SOC_TH_ACC_TYPE_NAME(mem_acc_type), mem_acc_type, 14941 *num_inst_to_scrub, mmu_base_type)); 14942 return SOC_E_FAIL; 14943 } /* mmu_base_type */ 14944 break; /* case: SOC_BLK_MMU_ITM */ 14945 case SOC_BLK_MMU_EB: 14946 switch (mmu_base_type) { 14947 case SOC_TH3_MMU_BASE_TYPE_IPIPE: 14948 *num_inst_to_scrub = 8; 14949 acc_type_list[0] = 0; 14950 acc_type_list[1] = 1; 14951 acc_type_list[2] = 2; 14952 acc_type_list[3] = 3; 14953 acc_type_list[4] = 4; 14954 acc_type_list[5] = 5; 14955 acc_type_list[6] = 6; 14956 acc_type_list[7] = 7; 14957 break; 14958 case SOC_TH3_MMU_BASE_TYPE_EPIPE: 14959 /* epipe0-7 serviced EB0-7 */ 14960 mmu_base_index = _SOC_MMU_BASE_INDEX(unit, mem, 0x7); 14961 *num_inst_to_scrub = 1; 14962 acc_type_list[0] = mmu_base_index; 14963 break; 14964 case SOC_TH3_MMU_BASE_TYPE_CHIP: 14965 /* must read each EB instance */ 14966 *num_inst_to_scrub = 8; 14967 acc_type_list[0] = 0; 14968 acc_type_list[1] = 1; 14969 acc_type_list[2] = 2; 14970 acc_type_list[3] = 3; 14971 acc_type_list[4] = 4; 14972 acc_type_list[5] = 5; 14973 acc_type_list[6] = 6; 14974 acc_type_list[7] = 7; 14975 break; 14976 case SOC_TH3_MMU_BASE_TYPE_ITM: 14977 /* must read each EB instance */ 14978 *num_inst_to_scrub = 8; 14979 acc_type_list[0] = 0; 14980 acc_type_list[1] = 1; 14981 acc_type_list[2] = 2; 14982 acc_type_list[3] = 3; 14983 acc_type_list[4] = 4; 14984 acc_type_list[5] = 5; 14985 acc_type_list[6] = 6; 14986 acc_type_list[7] = 7; 14987 break; 14988 default: /* IPORT, EPORT, EB */ 14989 /* should not find any TH3 MMU memories here */ 14990 LOG_ERROR(BSL_LS_SOC_SER, (BSL_META_U(unit, "scrub_ERROR: mem.blk.blk_type %s.%d.%d has acc_type = %s (%d), num_inst_to_scrub = %0d, mmu_base_type = %0d\n"), 14991 SOC_MEM_NAME(unit,mem), blk, blk_type, 14992 _SOC_TH_ACC_TYPE_NAME(mem_acc_type), mem_acc_type, 14993 *num_inst_to_scrub, mmu_base_type)); 14994 return SOC_E_FAIL; 14995 } /* mmu_base_type */ 14996 break; /* case: SOC_BLK_MMU_EB */ 14997 14998 default: /* SOC_BLK_MMU_GLB */ 14999 /* should not find any TH memories here */ 15000 LOG_ERROR(BSL_LS_SOC_SER, (BSL_META_U(unit, "scrub_ERROR: mem.blk.blk_type %s.%d.%d has acc_type = %s (%d), num_inst_to_scrub = %0d, mmu_base_type = %0d\n"), 15001 SOC_MEM_NAME(unit,mem), blk, blk_type, 15002 _SOC_TH_ACC_TYPE_NAME(mem_acc_type), mem_acc_type, 15003 *num_inst_to_scrub, mmu_base_type)); 15004 return SOC_E_FAIL; 15005 } /* blk_type */ 15006 LOG_VERBOSE(BSL_LS_SOC_SER, (BSL_META_U(unit, "scrub: mem.blk.blk_type %s.%d.%d has acc_type = %s (%d), num_inst_to_scrub = %0d, mmu_base_type = %0d\n"), 15007 SOC_MEM_NAME(unit,mem), blk, blk_type, 15008 _SOC_TH_ACC_TYPE_NAME(mem_acc_type), mem_acc_type, 15009 *num_inst_to_scrub, mmu_base_type)); 15010 return SOC_E_NONE; 15011 } /* need_per_mmu_membase_scrub */ 15012 return SOC_E_NONE; 15013 } 15014 15015 int 15016 soc_th3_tcam_engine_enable(int unit, int enable) 15017 { 15018 uint64 config; 15019 COMPILER_64_ZERO(config); 15020 15021 if (enable) { 15022 15023 soc_reg64_field32_set(unit, IARB_SER_SCAN_CONFIGr, &config, START_IDXf, 0); 15024 soc_reg64_field32_set(unit, IARB_SER_SCAN_CONFIGr, &config, MAX_IDXf, 1023); 15025 soc_reg64_field32_set(unit, IARB_SER_SCAN_CONFIGr, &config, OP_BLOCKf, 0); 15026 soc_reg64_field32_set(unit, IARB_SER_SCAN_CONFIGr, &config, INTERVALf, 64); 15027 soc_reg64_field32_set(unit, IARB_SER_SCAN_CONFIGr, &config, ENABLEf, 1); 15028 SOC_IF_ERROR_RETURN(soc_reg64_set 15029 (unit, IARB_SER_SCAN_CONFIGr, REG_PORT_ANY, 0, config)); 15030 15031 /* config EP HW ser scan engine */ 15032 COMPILER_64_ZERO(config); 15033 soc_reg64_field32_set(unit, EGR_ARB_SER_SCAN_CONFIGr, &config, START_IDXf, 0); 15034 soc_reg64_field32_set(unit, EGR_ARB_SER_SCAN_CONFIGr, &config, MAX_IDXf, 1023); 15035 soc_reg64_field32_set(unit, EGR_ARB_SER_SCAN_CONFIGr, &config, OP_BLOCKf, 0); 15036 soc_reg64_field32_set(unit, EGR_ARB_SER_SCAN_CONFIGr, &config, INTERVALf, 1000000); 15037 soc_reg64_field32_set(unit, EGR_ARB_SER_SCAN_CONFIGr, &config, ENABLEf, 1); 15038 SOC_IF_ERROR_RETURN(soc_reg64_set 15039 (unit, EGR_ARB_SER_SCAN_CONFIGr, REG_PORT_ANY, 0, config)); 15040 } else { 15041 15042 soc_reg64_field32_set(unit, IARB_SER_SCAN_CONFIGr, &config, START_IDXf, 0); 15043 soc_reg64_field32_set(unit, IARB_SER_SCAN_CONFIGr, &config, MAX_IDXf, 1023); 15044 soc_reg64_field32_set(unit, IARB_SER_SCAN_CONFIGr, &config, OP_BLOCKf, 0); 15045 soc_reg64_field32_set(unit, IARB_SER_SCAN_CONFIGr, &config, INTERVALf, 64); 15046 soc_reg64_field32_set(unit, IARB_SER_SCAN_CONFIGr, &config, ENABLEf, 0); 15047 SOC_IF_ERROR_RETURN(soc_reg64_set 15048 (unit, IARB_SER_SCAN_CONFIGr, REG_PORT_ANY, 0, config)); 15049 15050 /* config EP HW ser scan engine */ 15051 COMPILER_64_ZERO(config); 15052 soc_reg64_field32_set(unit, EGR_ARB_SER_SCAN_CONFIGr, &config, START_IDXf, 0); 15053 soc_reg64_field32_set(unit, EGR_ARB_SER_SCAN_CONFIGr, &config, MAX_IDXf, 1023); 15054 soc_reg64_field32_set(unit, EGR_ARB_SER_SCAN_CONFIGr, &config, OP_BLOCKf, 0); 15055 soc_reg64_field32_set(unit, EGR_ARB_SER_SCAN_CONFIGr, &config, INTERVALf, 1000000); 15056 soc_reg64_field32_set(unit, EGR_ARB_SER_SCAN_CONFIGr, &config, ENABLEf, 0); 15057 SOC_IF_ERROR_RETURN(soc_reg64_set 15058 (unit, EGR_ARB_SER_SCAN_CONFIGr, REG_PORT_ANY, 0, config)); 15059 } 15060 15061 return SOC_E_NONE; 15062 } 15063 15064 STATIC soc_error_t _soc_th3_ser_tcam_wrapper_found(soc_mem_t mem) 15065 { 15066 int i; 15067 for (i = 0; _soc_bcm56980_a0_tcam_mem_ser_info[i].mem != INVALIDm; i++) { 15068 if (_soc_bcm56980_a0_tcam_mem_ser_info[i].mem == mem) { 15069 return SOC_E_NONE; /* found */ 15070 } 15071 } 15072 return SOC_E_UNAVAIL; 15073 } 15074 15075 STATIC soc_error_t 15076 _soc_th3_ser_tcam_control_reg_get(soc_mem_t mem, soc_reg_t 15077 *ser_control_reg, 15078 soc_field_t *ser_enable_field) 15079 { 15080 int i; 15081 for (i = 0; _soc_bcm56980_a0_tcam_mem_ser_info[i].mem != INVALIDm; i++) { 15082 if (_soc_bcm56980_a0_tcam_mem_ser_info[i].mem == mem) { 15083 *ser_control_reg = _soc_bcm56980_a0_tcam_mem_ser_info[i].enable_reg; 15084 *ser_enable_field = _soc_bcm56980_a0_tcam_mem_ser_info[i].enable_field; 15085 return SOC_E_NONE; /* found */ 15086 } 15087 } 15088 return SOC_E_UNAVAIL; 15089 } 15090 15091 STATIC soc_error_t _soc_th3_tcam_wrapper_enable(int unit, int enable) 15092 { 15093 int i; 15094 uint8 fld_val = 0; 15095 uint32 val = 0; 15096 uint64 rval64; 15097 soc_reg_t ser_control_reg; 15098 soc_field_t ser_enable_field; 15099 15100 for (i = 0; _soc_bcm56980_a0_tcam_mem_ser_info[i].mem != INVALIDm; i++) { 15101 ser_control_reg = _soc_bcm56980_a0_tcam_mem_ser_info[i].enable_reg; 15102 ser_enable_field = _soc_bcm56980_a0_tcam_mem_ser_info[i].enable_field; 15103 15104 if (SOC_REG_IS_VALID(unit, ser_control_reg)) { 15105 if (enable) { 15106 if (ser_control_reg == IFP_TCAM_CAM_CONTROLr) { 15107 fld_val = 0xf; 15108 } else { 15109 fld_val = 1; 15110 } 15111 } else { 15112 fld_val = 0; 15113 } 15114 15115 if (SOC_REG_IS_64(unit, ser_control_reg)) { 15116 COMPILER_64_ZERO(rval64); 15117 SOC_IF_ERROR_RETURN 15118 (soc_reg_get(unit, ser_control_reg, REG_PORT_ANY, 0, &rval64)); 15119 soc_reg64_field32_set(unit, ser_control_reg, &rval64, ser_enable_field, 15120 fld_val); 15121 SOC_IF_ERROR_RETURN 15122 (soc_reg_set(unit, ser_control_reg, REG_PORT_ANY, 0, rval64)); 15123 } else { 15124 SOC_IF_ERROR_RETURN 15125 (soc_reg32_get(unit, ser_control_reg, REG_PORT_ANY, 0, &val)); 15126 soc_reg_field_set(unit, ser_control_reg, &val, ser_enable_field, fld_val); 15127 SOC_IF_ERROR_RETURN 15128 (soc_reg32_set(unit, ser_control_reg, REG_PORT_ANY, 0, val)); 15129 } 15130 } 15131 } 15132 return SOC_E_NONE; 15133 } 15134 15135 int 15136 soc_tomahawk3_mem_ser_control(int unit, soc_mem_t mem, int copyno, 15137 int enable) 15138 { 15139 soc_reg_t reg = INVALIDr; 15140 uint32 rval; 15141 15142 if (!enable) { 15143 /* disable FP_REFRESH */ 15144 reg = AUX_ARB_CONTROLr; 15145 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, reg, REG_PORT_ANY, 0, &rval)); 15146 soc_reg_field_set(unit, reg, &rval, FP_REFRESH_ENABLEf, 0); 15147 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, reg, REG_PORT_ANY, 0, rval)); 15148 } 15149 15150 if (enable) { 15151 if (soc_property_get(unit, spn_PARITY_ENABLE, FALSE)) { 15152 SOC_IF_ERROR_RETURN(soc_tomahawk_ser_enable_all(unit, enable)); 15153 SOC_IF_ERROR_RETURN(soc_tomahawk3_ser_enable_parity_table_all(unit, enable)); 15154 } 15155 } else { 15156 SOC_IF_ERROR_RETURN(soc_tomahawk_ser_enable_all(unit, enable)); 15157 SOC_IF_ERROR_RETURN(soc_tomahawk3_ser_enable_parity_table_all(unit, enable)); 15158 } 15159 15160 if (enable) { 15161 /*Initialize MMU memory*/ 15162 rval = 0; 15163 reg = MMU_GLBCFG_MISCCONFIGr; 15164 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, reg, REG_PORT_ANY, 0, &rval)); 15165 soc_reg_field_set(unit, reg, &rval, ECCP_ENf, 1); 15166 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, reg, REG_PORT_ANY, 0, rval)); 15167 sal_usleep(20); 15168 soc_reg_field_set(unit, reg, &rval, INIT_MEMf, 1); 15169 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, reg, REG_PORT_ANY, 0, rval)); 15170 soc_reg_field_set(unit, reg, &rval, INIT_MEMf, 0); 15171 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, reg, REG_PORT_ANY, 0, rval)); 15172 15173 /* enable FP_REFRESH */ 15174 reg = AUX_ARB_CONTROLr; 15175 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, reg, REG_PORT_ANY, 0, &rval)); 15176 soc_reg_field_set(unit, reg, &rval, FP_REFRESH_ENABLEf, 1); 15177 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, reg, REG_PORT_ANY, 0, rval)); 15178 } 15179 15180 return SOC_E_NONE; 15181 } 15182 15183 int 15184 soc_th3_mmu_mem_blk_remap(soc_mem_t mem, uint32 *block) 15185 { 15186 /* In mmu QSCH memories belong to EB block, but if there is ser error on 15187 these table, the ser event is reported to GLB ser fifo. So need to 15188 remap the block back to MMU_EB */ 15189 if (mem == MMU_QSCH_L0_ACCUM_COMP_MEMm || mem == MMU_QSCH_L0_ACCUM_COMP_MEM_PIPE0m || 15190 mem == MMU_QSCH_L0_ACCUM_COMP_MEM_PIPE1m || mem == MMU_QSCH_L0_ACCUM_COMP_MEM_PIPE2m || 15191 mem == MMU_QSCH_L0_ACCUM_COMP_MEM_PIPE3m || mem == MMU_QSCH_L0_ACCUM_COMP_MEM_PIPE4m || 15192 mem == MMU_QSCH_L0_ACCUM_COMP_MEM_PIPE5m || mem == MMU_QSCH_L0_ACCUM_COMP_MEM_PIPE6m || 15193 mem == MMU_QSCH_L0_ACCUM_COMP_MEM_PIPE7m || mem == MMU_QSCH_L0_CREDIT_MEMm || 15194 mem == MMU_QSCH_L0_CREDIT_MEM_PIPE0m || mem == MMU_QSCH_L0_CREDIT_MEM_PIPE1m || 15195 mem == MMU_QSCH_L0_CREDIT_MEM_PIPE2m || mem == MMU_QSCH_L0_CREDIT_MEM_PIPE3m || 15196 mem == MMU_QSCH_L0_CREDIT_MEM_PIPE4m || mem == MMU_QSCH_L0_CREDIT_MEM_PIPE5m || 15197 mem == MMU_QSCH_L0_CREDIT_MEM_PIPE6m || mem == MMU_QSCH_L0_CREDIT_MEM_PIPE7m || 15198 mem == MMU_QSCH_L0_FIRST_MEMm || mem == MMU_QSCH_L0_FIRST_MEM_PIPE0m || 15199 mem == MMU_QSCH_L0_FIRST_MEM_PIPE1m || mem == MMU_QSCH_L0_FIRST_MEM_PIPE2m || 15200 mem == MMU_QSCH_L0_FIRST_MEM_PIPE3m || mem == MMU_QSCH_L0_FIRST_MEM_PIPE4m || 15201 mem == MMU_QSCH_L0_FIRST_MEM_PIPE5m || mem == MMU_QSCH_L0_FIRST_MEM_PIPE6m || 15202 mem == MMU_QSCH_L0_FIRST_MEM_PIPE7m || mem == MMU_QSCH_L0_WEIGHT_MEMm || 15203 mem == MMU_QSCH_L0_WEIGHT_MEM_PIPE0m || mem == MMU_QSCH_L0_WEIGHT_MEM_PIPE1m || 15204 mem == MMU_QSCH_L0_WEIGHT_MEM_PIPE2m || mem == MMU_QSCH_L0_WEIGHT_MEM_PIPE3m || 15205 mem == MMU_QSCH_L0_WEIGHT_MEM_PIPE4m || mem == MMU_QSCH_L0_WEIGHT_MEM_PIPE5m || 15206 mem == MMU_QSCH_L0_WEIGHT_MEM_PIPE6m || mem == MMU_QSCH_L0_WEIGHT_MEM_PIPE7m || 15207 mem == MMU_QSCH_L1_ACCUM_COMP_MEMm || mem == MMU_QSCH_L1_ACCUM_COMP_MEM_PIPE0m || 15208 mem == MMU_QSCH_L1_ACCUM_COMP_MEM_PIPE1m || mem == MMU_QSCH_L1_ACCUM_COMP_MEM_PIPE2m || 15209 mem == MMU_QSCH_L1_ACCUM_COMP_MEM_PIPE3m || mem == MMU_QSCH_L1_ACCUM_COMP_MEM_PIPE4m || 15210 mem == MMU_QSCH_L1_ACCUM_COMP_MEM_PIPE5m || mem == MMU_QSCH_L1_ACCUM_COMP_MEM_PIPE6m || 15211 mem == MMU_QSCH_L1_ACCUM_COMP_MEM_PIPE7m || mem == MMU_QSCH_L1_CREDIT_MEMm || 15212 mem == MMU_QSCH_L1_CREDIT_MEM_PIPE0m || mem == MMU_QSCH_L1_CREDIT_MEM_PIPE1m || 15213 mem == MMU_QSCH_L1_CREDIT_MEM_PIPE2m || mem == MMU_QSCH_L1_CREDIT_MEM_PIPE3m || 15214 mem == MMU_QSCH_L1_CREDIT_MEM_PIPE4m || mem == MMU_QSCH_L1_CREDIT_MEM_PIPE5m || 15215 mem == MMU_QSCH_L1_CREDIT_MEM_PIPE6m || mem == MMU_QSCH_L1_CREDIT_MEM_PIPE7m || 15216 mem == MMU_QSCH_L1_FIRST_MEMm || mem == MMU_QSCH_L1_FIRST_MEM_PIPE0m || 15217 mem == MMU_QSCH_L1_FIRST_MEM_PIPE1m || mem == MMU_QSCH_L1_FIRST_MEM_PIPE2m || 15218 mem == MMU_QSCH_L1_FIRST_MEM_PIPE3m || mem == MMU_QSCH_L1_FIRST_MEM_PIPE4m || 15219 mem == MMU_QSCH_L1_FIRST_MEM_PIPE5m || mem == MMU_QSCH_L1_FIRST_MEM_PIPE6m || 15220 mem == MMU_QSCH_L1_FIRST_MEM_PIPE7m || mem == MMU_QSCH_L1_WEIGHT_MEMm || 15221 mem == MMU_QSCH_L1_WEIGHT_MEM_PIPE0m || mem == MMU_QSCH_L1_WEIGHT_MEM_PIPE1m || 15222 mem == MMU_QSCH_L1_WEIGHT_MEM_PIPE2m || mem == MMU_QSCH_L1_WEIGHT_MEM_PIPE3m || 15223 mem == MMU_QSCH_L1_WEIGHT_MEM_PIPE4m || mem == MMU_QSCH_L1_WEIGHT_MEM_PIPE5m || 15224 mem == MMU_QSCH_L1_WEIGHT_MEM_PIPE6m || mem == MMU_QSCH_L1_WEIGHT_MEM_PIPE7m || 15225 mem == MMU_QSCH_L2_ACCUM_COMP_MEMm || mem == MMU_QSCH_L2_ACCUM_COMP_MEM_PIPE0m || 15226 mem == MMU_QSCH_L2_ACCUM_COMP_MEM_PIPE1m || mem == MMU_QSCH_L2_ACCUM_COMP_MEM_PIPE2m || 15227 mem == MMU_QSCH_L2_ACCUM_COMP_MEM_PIPE3m || mem == MMU_QSCH_L2_ACCUM_COMP_MEM_PIPE4m || 15228 mem == MMU_QSCH_L2_ACCUM_COMP_MEM_PIPE5m || mem == MMU_QSCH_L2_ACCUM_COMP_MEM_PIPE6m || 15229 mem == MMU_QSCH_L2_ACCUM_COMP_MEM_PIPE7m || mem == MMU_QSCH_L2_CREDIT_MEMm || 15230 mem == MMU_QSCH_L2_CREDIT_MEM_PIPE0m || mem == MMU_QSCH_L2_CREDIT_MEM_PIPE1m || 15231 mem == MMU_QSCH_L2_CREDIT_MEM_PIPE2m || mem == MMU_QSCH_L2_CREDIT_MEM_PIPE3m || 15232 mem == MMU_QSCH_L2_CREDIT_MEM_PIPE4m || mem == MMU_QSCH_L2_CREDIT_MEM_PIPE5m || 15233 mem == MMU_QSCH_L2_CREDIT_MEM_PIPE6m || mem == MMU_QSCH_L2_CREDIT_MEM_PIPE7m || 15234 mem == MMU_QSCH_L2_WEIGHT_MEMm || mem == MMU_QSCH_L2_WEIGHT_MEM_PIPE0m || 15235 mem == MMU_QSCH_L2_WEIGHT_MEM_PIPE1m || mem == MMU_QSCH_L2_WEIGHT_MEM_PIPE2m || 15236 mem == MMU_QSCH_L2_WEIGHT_MEM_PIPE3m || mem == MMU_QSCH_L2_WEIGHT_MEM_PIPE4m || 15237 mem == MMU_QSCH_L2_WEIGHT_MEM_PIPE5m || mem == MMU_QSCH_L2_WEIGHT_MEM_PIPE6m || 15238 mem == MMU_QSCH_L2_WEIGHT_MEM_PIPE7m ) { 15239 *block = 4; /* MMU_EB */ 15240 return SOC_E_NONE; 15241 } 15242 15243 if (mem == MMU_RL_RQE_FIFO_MEMm || mem == MMU_RL_RQE_FIFO_MEM_ITM0m || 15244 mem == MMU_RL_RQE_FIFO_MEM_ITM1m || mem == MMU_RL_FBANK0m || 15245 mem == MMU_RL_FBANK0_ITM0m || mem == MMU_RL_FBANK0_ITM1m || 15246 mem == MMU_RL_FBANK1m || mem == MMU_RL_FBANK1_ITM0m || 15247 mem == MMU_RL_FBANK1_ITM1m || mem == MMU_RL_FBANK2m || 15248 mem == MMU_RL_FBANK2_ITM0m || mem == MMU_RL_FBANK2_ITM1m || 15249 mem == MMU_RL_FBANK3m || mem == MMU_RL_FBANK3_ITM0m || 15250 mem == MMU_RL_FBANK3_ITM1m || mem == MMU_RL_FBANK4m || 15251 mem == MMU_RL_FBANK4_ITM0m || mem == MMU_RL_FBANK4_ITM1m || 15252 mem == MMU_RL_FBANK5m || mem == MMU_RL_FBANK5_ITM0m || 15253 mem == MMU_RL_FBANK5_ITM1m || mem == MMU_RL_FBANK6m || 15254 mem == MMU_RL_FBANK6_ITM0m || mem == MMU_RL_FBANK6_ITM1m || 15255 mem == MMU_RL_FBANK7m || mem == MMU_RL_FBANK7_ITM0m || 15256 mem == MMU_RL_FBANK7_ITM1m || mem == MMU_RL_FBANK8m || 15257 mem == MMU_RL_FBANK8_ITM0m || mem == MMU_RL_FBANK8_ITM1m || 15258 mem == MMU_RL_FBANK9m || mem == MMU_RL_FBANK9_ITM0m || 15259 mem == MMU_RL_FBANK9_ITM1m || mem == MMU_RL_FBANK10m || 15260 mem == MMU_RL_FBANK10_ITM0m || mem == MMU_RL_FBANK10_ITM1m || 15261 mem == MMU_RL_FBANK11m || mem == MMU_RL_FBANK11_ITM0m || 15262 mem == MMU_RL_FBANK11_ITM1m || mem == MMU_RL_FBANK12m || 15263 mem == MMU_RL_FBANK12_ITM0m || mem == MMU_RL_FBANK12_ITM1m || 15264 mem == MMU_RL_FBANK13m || mem == MMU_RL_FBANK13_ITM0m || 15265 mem == MMU_RL_FBANK13_ITM1m || mem == MMU_RL_FBANK14m || 15266 mem == MMU_RL_FBANK14_ITM0m || mem == MMU_RL_FBANK14_ITM1m || 15267 mem == MMU_RL_FBANK15m || mem == MMU_RL_FBANK15_ITM0m || 15268 mem == MMU_RL_FBANK15_ITM1m || mem == MMU_THDI_PORT_PG_MIN_COUNTERm || 15269 mem == MMU_THDI_PORT_PG_SHARED_BSTm || 15270 mem == MMU_THDI_PORT_PG_HDRM_BSTm || 15271 mem == MMU_THDO_BST_TOTAL_QUEUEm || 15272 mem == MMU_THDO_BST_SHARED_PORTSP_MCm || 15273 mem == MMU_THDO_BST_SHARED_PORTSP_MC_PKTSTATm || 15274 mem == MMU_THDO_BST_SHARED_PORTSP_MC_PKTSTAT_ITM0m || 15275 mem == MMU_THDO_BST_SHARED_PORTSP_MC_PKTSTAT_ITM1m || 15276 mem == MMU_THDO_BST_TOTAL_QUEUE_PKTSTATm || 15277 mem == MMU_THDO_BST_TOTAL_QUEUE_PKTSTAT_ITM0m || 15278 mem == MMU_THDO_BST_TOTAL_QUEUE_PKTSTAT_ITM1m || 15279 mem == MMU_THDO_QUEUE_DROP_COUNTm || 15280 mem == MMU_THDO_QUEUE_DROP_COUNT_ITM0m || 15281 mem == MMU_THDO_QUEUE_DROP_COUNT_ITM1m || 15282 mem == MMU_THDO_PORT_DROP_COUNT_UCm || 15283 mem == MMU_THDO_PORT_DROP_COUNT_UC_ITM0m || 15284 mem == MMU_THDO_PORT_DROP_COUNT_UC_ITM1m || 15285 mem == MMU_THDO_PORT_DROP_COUNT_MCm || 15286 mem == MMU_THDO_PORT_DROP_COUNT_MC_ITM0m || 15287 mem == MMU_THDO_PORT_DROP_COUNT_MC_ITM1m || 15288 mem == MMU_THDO_SRC_PORT_DROP_COUNTm || 15289 mem == MMU_THDO_SRC_PORT_DROP_COUNT_PIPE0m || 15290 mem == MMU_THDO_SRC_PORT_DROP_COUNT_PIPE1m || 15291 mem == MMU_THDO_SRC_PORT_DROP_COUNT_PIPE2m || 15292 mem == MMU_THDO_SRC_PORT_DROP_COUNT_PIPE3m || 15293 mem == MMU_THDO_SRC_PORT_DROP_COUNT_PIPE4m || 15294 mem == MMU_THDO_SRC_PORT_DROP_COUNT_PIPE5m || 15295 mem == MMU_THDO_SRC_PORT_DROP_COUNT_PIPE6m || 15296 mem == MMU_THDO_SRC_PORT_DROP_COUNT_PIPE7m || 15297 mem == MMU_THDO_SRC_PORT_DROP_COUNTm) { 15298 *block = 3; /* MMU_ITM */ 15299 return SOC_E_NONE; 15300 } 15301 15302 return SOC_E_NOT_FOUND; 15303 } 15304 15305 STATIC int 15306 _soc_th3_reg32_par_en_modify(int unit, soc_reg_t reg, soc_field_t field, int enable) 15307 { 15308 uint64 rval64; 15309 uint32 rval; 15310 int port = REG_PORT_ANY; 15311 static char *mmu_base_type[8] = { 15312 "IPORT", "EPORT", "IPIPE", "EPIPE", "CHIP", "ITM"}; 15313 15314 if (SOC_REG_IS_VALID(unit, reg) && INVALIDf != field) { 15315 if (SOC_REG_IS_64(unit, reg)) { 15316 SOC_IF_ERROR_RETURN 15317 (soc_reg_get(unit, reg, port, 0, &rval64)); 15318 soc_reg64_field32_set(unit, reg, &rval64, field, enable? 1 : 0); 15319 SOC_IF_ERROR_RETURN 15320 (soc_reg_set(unit, reg, port, 0, rval64)); 15321 } else { 15322 int at, bt; 15323 SOC_IF_ERROR_RETURN 15324 (soc_reg32_get(unit, reg, port, 0, &rval)); 15325 soc_reg_field_set(unit, reg, &rval, field, 15326 enable ? 1 : 0); 15327 at = SOC_REG_ACC_TYPE(unit, reg); 15328 bt = SOC_REG_BASE_TYPE(unit, reg); 15329 if (20 == at) { /* ACC_TYPE_SINGLE - used only in MMU blocks */ 15330 int inst, pipe, max_pipe; 15331 switch (bt) { 15332 case 2: /* IPIPE */ 15333 case 3: /* EPIPE */ 15334 max_pipe = NUM_PIPE(unit); break; 15335 case 4: /* CHIP */ 15336 max_pipe = 1; break; 15337 case 5: /* ITM */ 15338 max_pipe = NUM_ITM(unit); break; 15339 default: 15340 /* 0: IPORT */ 15341 /* 1: EPORT */ 15342 max_pipe = -1; 15343 LOG_ERROR(BSL_LS_SOC_SER, 15344 (BSL_META_U(unit, 15345 "unit %d, reg %s has unexpected " 15346 "base_type %s, will skip enable of " 15347 "1b err reporting\n"), 15348 unit, SOC_REG_NAME(unit, reg), 15349 mmu_base_type[bt])); 15350 break; 15351 } 15352 LOG_VERBOSE(BSL_LS_SOC_SER, 15353 (BSL_META_U(unit, 15354 "unit %d, reg %s has base_type %s\n"), 15355 unit, SOC_REG_NAME(unit, reg), 15356 mmu_base_type[bt])); 15357 for (pipe = 0; pipe < max_pipe; pipe++) { 15358 inst = pipe | SOC_REG_ADDR_INSTANCE_MASK; 15359 SOC_IF_ERROR_RETURN 15360 (soc_reg32_set(unit, reg, inst, 0, rval)); 15361 LOG_WARN(BSL_LS_SOC_SER, (BSL_META_U(unit, 15362 "HF detected: setting reg.field[%s.%s]=0, mmu_base_type %s, pipe %d, using acc_type %0d\n"), 15363 SOC_REG_NAME(unit, reg), SOC_FIELD_NAME(unit, field), 15364 mmu_base_type[bt], pipe, at)); 15365 } 15366 } else { 15367 SOC_IF_ERROR_RETURN 15368 (soc_reg32_set(unit, reg, port, 0, rval)); 15369 LOG_WARN(BSL_LS_SOC_SER, (BSL_META_U(unit, 15370 "HF detected: setting reg.field[%s.%s]=0, using acc_type %0d (default)\n"), 15371 SOC_REG_NAME(unit, reg), SOC_FIELD_NAME(unit, field), 15372 at)); 15373 } 15374 } /* reg32 */ 15375 return SOC_E_NONE; 15376 } 15377 return SOC_E_UNAVAIL; 15378 } 15379 15380 #ifdef BCM_CMICX_SUPPORT 15381 void soc_th3_ser_intr_handler(int unit,uint32 cmic_val,int reg_num) 15382 { 15383 soc_reg_t ser_intr_reg[4] = {ICFG_CHIP_LP_INTR_ENABLE_REG0r, 15384 ICFG_CHIP_LP_INTR_ENABLE_REG1r, 15385 ICFG_CHIP_LP_INTR_ENABLE_REG2r, 15386 ICFG_CHIP_LP_INTR_ENABLE_REG3r}; 15387 uint32 mask = 0; 15388 int i = 0; 15389 15390 (void)soc_iproc_getreg(unit, soc_reg_addr(unit, ser_intr_reg[reg_num], REG_PORT_ANY, 0), 15391 &mask); 15392 cmic_val &= mask; 15393 15394 for(i = 0; i < 32; i++) { 15395 switch(reg_num){ 15396 case 0: 15397 if(cmic_val & 1 << i) { 15398 if((i >= 4 && i <= 20) || (i == 1) || (i == 0)) { 15399 (void)soc_ser_top_intr_reg_enable(unit, 0, i, 0); 15400 if (soc_ser_parity_error_cmicx_intr(INT_TO_PTR(unit), 0, 0, 15401 INT_TO_PTR(0), 15402 INT_TO_PTR(i))) { 15403 } else { 15404 LOG_ERROR(BSL_LS_SOC_COMMON, 15405 (BSL_META_U(unit, 15406 "soc_ser_cmicx_intr_handler unit %d: " 15407 "Disabling unhandled interrupt(s): %d\n"), 15408 unit, PTR_TO_INT(i))); 15409 (void)soc_ser_top_intr_reg_enable(unit, 0, i, 0); 15410 } 15411 } 15412 } 15413 break; 15414 case 1: 15415 if (cmic_val & 1 << i) { 15416 if (i >= 16 && i <= 31) { 15417 (void)soc_ser_top_intr_reg_enable(unit, 1, i, 0); 15418 if (soc_ser_parity_error_cmicx_intr(INT_TO_PTR(unit), 0, 0, 15419 INT_TO_PTR(1), 15420 INT_TO_PTR(i))) { 15421 } else { 15422 LOG_ERROR(BSL_LS_SOC_COMMON, 15423 (BSL_META_U(unit, 15424 "soc_ser_cmicx_intr_handler unit %d: " 15425 "Disabling unhandled interrupt(s): %d\n"), 15426 unit, PTR_TO_INT(i))); 15427 (void)soc_ser_top_intr_reg_enable(unit, 1, i, 0); 15428 } 15429 } 15430 } 15431 break; 15432 case 2: 15433 if (cmic_val & 1 << i) { 15434 (void)soc_ser_top_intr_reg_enable(unit, 2, i, 0); 15435 if (soc_ser_parity_error_cmicx_intr(INT_TO_PTR(unit), 0, 0, 15436 INT_TO_PTR(2), 15437 INT_TO_PTR(i))) { 15438 } else { 15439 LOG_ERROR(BSL_LS_SOC_COMMON, 15440 (BSL_META_U(unit, 15441 "soc_ser_cmicx_intr_handler unit %d: " 15442 "Disabling unhandled interrupt(s): %d\n"), 15443 unit, PTR_TO_INT(i))); 15444 (void)soc_ser_top_intr_reg_enable(unit, 2, i, 0); 15445 } 15446 } 15447 break; 15448 case 3: 15449 if (cmic_val & 1 << i) { 15450 if (i >= 0 && i <= 16) { 15451 (void)soc_ser_top_intr_reg_enable(unit, 3, i, 0); 15452 if (soc_ser_parity_error_cmicx_intr(INT_TO_PTR(unit), 0, 0, 15453 INT_TO_PTR(3), 15454 INT_TO_PTR(i))) { 15455 } else { 15456 LOG_ERROR(BSL_LS_SOC_COMMON, 15457 (BSL_META_U(unit, 15458 "soc_ser_cmicx_intr_handler unit %d: " 15459 "Disabling unhandled interrupt(s): %d\n"), 15460 unit, PTR_TO_INT(i))); 15461 (void)soc_ser_top_intr_reg_enable(unit, 3, i, 0); 15462 } 15463 } 15464 } 15465 break; 15466 default: 15467 break; 15468 } 15469 } 15470 } 15471 #endif 15472 15473 STATIC int _soc_tomahawk3_idb_enable(int unit, soc_reg_t reg_name, int enable, int *is_idb) 15474 { 15475 int i, j, pipe, pm_num; 15476 uint64 rval64; 15477 uint32 rval,rval1; 15478 uint32 addr; 15479 int block; 15480 uint8 acc_type; 15481 soc_reg_t reg = TOP_TSC_ENABLEr; 15482 soc_reg_t obm_ctrl_enable[] = 15483 { IDB_OBM0_SER_CONTROLr, 15484 IDB_OBM1_SER_CONTROLr, 15485 IDB_OBM2_SER_CONTROLr, 15486 IDB_OBM3_SER_CONTROLr }; 15487 soc_reg_t ca_ctrl_enable[] = 15488 { IDB_CA0_SER_CONTROLr, 15489 IDB_CA1_SER_CONTROLr, 15490 IDB_CA2_SER_CONTROLr, 15491 IDB_CA3_SER_CONTROLr }; 15492 15493 for (i = 0; i < _TH3_PBLKS_PER_PIPE; i++) { 15494 if ((reg_name == obm_ctrl_enable[i]) || (reg_name == ca_ctrl_enable[i])) { 15495 *is_idb = 1; 15496 break; 15497 } 15498 } 15499 15500 if (i == _TH3_PBLKS_PER_PIPE) { 15501 *is_idb = 0; 15502 return SOC_E_NOT_FOUND; 15503 } 15504 15505 addr = soc_reg_addr_get(unit, reg_name, REG_PORT_ANY, 0, 15506 SOC_REG_ADDR_OPTION_NONE, 15507 &block, &acc_type); 15508 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, reg, REG_PORT_ANY, 0, &rval1)); 15509 for (pipe = 0; pipe < _TH3_PIPES_PER_DEV; pipe++) { 15510 pm_num = pipe * _TH3_PBLKS_PER_PIPE + i; 15511 15512 if (rval1 & (1 << pm_num)) { 15513 if (SOC_REG_IS_64(unit, reg_name)) { 15514 COMPILER_64_ZERO(rval64); 15515 SOC_IF_ERROR_RETURN 15516 (_soc_reg64_get(unit, block, pipe, addr, &rval64)); 15517 } else { 15518 SOC_IF_ERROR_RETURN 15519 (_soc_reg32_get(unit, block, pipe, addr, &rval)); 15520 } 15521 if (reg_name == obm_ctrl_enable[i]) { 15522 j = 0; 15523 while(_soc_th3_idb_obm_enable_fields[j] != INVALIDf) { 15524 soc_reg_field_set(unit, reg_name, &rval, 15525 _soc_th3_idb_obm_enable_fields[j], 15526 enable ? 1 : 0); 15527 j++; 15528 } 15529 } else if (reg_name == ca_ctrl_enable[i]){ 15530 j = 0; 15531 while(_soc_th3_idb_ca_fifo_enable_fields[j] != INVALIDf) { 15532 soc_reg64_field32_set(unit, reg_name, &rval64, 15533 _soc_th3_idb_ca_fifo_enable_fields[j], 15534 enable ? 1 : 0); 15535 j++; 15536 } 15537 } 15538 15539 if (SOC_REG_IS_64(unit, reg_name)) { 15540 SOC_IF_ERROR_RETURN 15541 (_soc_reg64_set(unit, block, pipe, addr, rval64)); 15542 } else { 15543 SOC_IF_ERROR_RETURN 15544 (_soc_reg32_set(unit, block, pipe, addr, rval)); 15545 } 15546 } 15547 } 15548 15549 return SOC_E_NONE; 15550 } 15551 15552 int soc_th3_ser_test_skip_by_at(int unit, soc_mem_t mem, soc_acc_type_t at) 15553 { 15554 uint16 dev_id; 15555 uint8 rev_id; 15556 soc_cm_get_id(unit, &dev_id, &rev_id); 15557 15558 if (dev_id == BCM56983_DEVICE_ID) { 15559 if ((at == _SOC_UNIQUE_ACC_TYPE_PIPE_2) || 15560 (at == _SOC_UNIQUE_ACC_TYPE_PIPE_3) || 15561 (at == _SOC_UNIQUE_ACC_TYPE_PIPE_4) || 15562 (at == _SOC_UNIQUE_ACC_TYPE_PIPE_5)) { 15563 return TRUE; 15564 } 15565 15566 if ((mem == MMU_MTRO_L0_A_PIPE2m) || (mem == MMU_MTRO_L0_A_PIPE3m) || 15567 (mem == MMU_MTRO_L0_A_PIPE4m) || (mem == MMU_MTRO_L0_A_PIPE5m) || 15568 (mem == MMU_MTRO_L0_B_PIPE2m) || (mem == MMU_MTRO_L0_B_PIPE3m) || 15569 (mem == MMU_MTRO_L0_B_PIPE4m) || (mem == MMU_MTRO_L0_B_PIPE5m) || 15570 (mem == MMU_MTRO_L0_C_PIPE2m) || (mem == MMU_MTRO_L0_C_PIPE3m) || 15571 (mem == MMU_MTRO_L0_C_PIPE4m) || (mem == MMU_MTRO_L0_C_PIPE5m) || 15572 (mem == MMU_QSCH_L0_WEIGHT_MEM_PIPE2m) || 15573 (mem == MMU_QSCH_L0_WEIGHT_MEM_PIPE3m) || 15574 (mem == MMU_QSCH_L0_WEIGHT_MEM_PIPE4m) || 15575 (mem == MMU_QSCH_L0_WEIGHT_MEM_PIPE5m) || 15576 (mem == MMU_QSCH_L1_WEIGHT_MEM_PIPE2m) || 15577 (mem == MMU_QSCH_L1_WEIGHT_MEM_PIPE3m) || 15578 (mem == MMU_QSCH_L1_WEIGHT_MEM_PIPE4m) || 15579 (mem == MMU_QSCH_L1_WEIGHT_MEM_PIPE5m) || 15580 (mem == MMU_QSCH_L2_WEIGHT_MEM_PIPE2m) || 15581 (mem == MMU_QSCH_L2_WEIGHT_MEM_PIPE3m) || 15582 (mem == MMU_QSCH_L2_WEIGHT_MEM_PIPE4m) || 15583 (mem == MMU_QSCH_L2_WEIGHT_MEM_PIPE5m) || 15584 (mem == MMU_THDI_PORTSP_CONFIG1_PIPE2m) || 15585 (mem == MMU_THDI_PORTSP_CONFIG1_PIPE3m) || 15586 (mem == MMU_THDI_PORTSP_CONFIG1_PIPE4m) || 15587 (mem == MMU_THDI_PORTSP_CONFIG1_PIPE5m) || 15588 (mem == MMU_THDI_PORTSP_CONFIG_PIPE2m) || 15589 (mem == MMU_THDI_PORTSP_CONFIG_PIPE3m) || 15590 (mem == MMU_THDI_PORTSP_CONFIG_PIPE4m) || 15591 (mem == MMU_THDI_PORTSP_CONFIG_PIPE5m) || 15592 (mem == MMU_THDI_PORT_BST_CONFIG_PIPE2m) || 15593 (mem == MMU_THDI_PORT_BST_CONFIG_PIPE3m) || 15594 (mem == MMU_THDI_PORT_BST_CONFIG_PIPE4m) || 15595 (mem == MMU_THDI_PORT_BST_CONFIG_PIPE5m) || 15596 (mem == MMU_THDI_PORT_PG_HDRM_CONFIG_PIPE2m) || 15597 (mem == MMU_THDI_PORT_PG_HDRM_CONFIG_PIPE3m) || 15598 (mem == MMU_THDI_PORT_PG_HDRM_CONFIG_PIPE4m) || 15599 (mem == MMU_THDI_PORT_PG_HDRM_CONFIG_PIPE5m) || 15600 (mem == MMU_THDI_PORT_PG_MIN_CONFIG1_PIPE2m) || 15601 (mem == MMU_THDI_PORT_PG_MIN_CONFIG1_PIPE3m) || 15602 (mem == MMU_THDI_PORT_PG_MIN_CONFIG1_PIPE4m) || 15603 (mem == MMU_THDI_PORT_PG_MIN_CONFIG1_PIPE5m) || 15604 (mem == MMU_THDI_PORT_PG_MIN_CONFIG_PIPE2m) || 15605 (mem == MMU_THDI_PORT_PG_MIN_CONFIG_PIPE3m) || 15606 (mem == MMU_THDI_PORT_PG_MIN_CONFIG_PIPE4m) || 15607 (mem == MMU_THDI_PORT_PG_MIN_CONFIG_PIPE5m) || 15608 (mem == MMU_THDI_PORT_PG_RESUME_CONFIG1_PIPE2m) || 15609 (mem == MMU_THDI_PORT_PG_RESUME_CONFIG1_PIPE3m) || 15610 (mem == MMU_THDI_PORT_PG_RESUME_CONFIG1_PIPE4m) || 15611 (mem == MMU_THDI_PORT_PG_RESUME_CONFIG1_PIPE5m) || 15612 (mem == MMU_THDI_PORT_PG_RESUME_CONFIG_PIPE2m) || 15613 (mem == MMU_THDI_PORT_PG_RESUME_CONFIG_PIPE3m) || 15614 (mem == MMU_THDI_PORT_PG_RESUME_CONFIG_PIPE4m) || 15615 (mem == MMU_THDI_PORT_PG_RESUME_CONFIG_PIPE5m) || 15616 (mem == MMU_THDI_PORT_PG_SHARED_CONFIG1_PIPE2m) || 15617 (mem == MMU_THDI_PORT_PG_SHARED_CONFIG1_PIPE3m) || 15618 (mem == MMU_THDI_PORT_PG_SHARED_CONFIG1_PIPE4m) || 15619 (mem == MMU_THDI_PORT_PG_SHARED_CONFIG1_PIPE5m) || 15620 (mem == MMU_THDI_PORT_PG_SHARED_CONFIG_PIPE2m) || 15621 (mem == MMU_THDI_PORT_PG_SHARED_CONFIG_PIPE3m) || 15622 (mem == MMU_THDI_PORT_PG_SHARED_CONFIG_PIPE4m) || 15623 (mem == MMU_THDI_PORT_PG_SHARED_CONFIG_PIPE5m)) { 15624 return TRUE; 15625 } 15626 } 15627 15628 return FALSE; 15629 } 15630 15631 int soc_th3_ser_pipe_skip(int unit, soc_pipe_select_t pipe) 15632 { 15633 int skip = FALSE; 15634 uint16 dev_id; 15635 uint8 rev_id; 15636 15637 soc_cm_get_id(unit, &dev_id, &rev_id); 15638 if (dev_id == BCM56983_DEVICE_ID) { 15639 if ((pipe == SOC_PIPE_SELECT_2) || 15640 (pipe == SOC_PIPE_SELECT_3) || 15641 (pipe == SOC_PIPE_SELECT_4) || 15642 (pipe == SOC_PIPE_SELECT_5)) { 15643 skip = TRUE; 15644 } 15645 } 15646 15647 return skip; 15648 } 15649 #endif 15650 #endif /* BCM_TOMAHAWK_SUPPORT */