tdm_td3_parse.c (21383B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * $All Rights Reserved.$ 7 * 8 * TDM chip based printing and parsing functions 9 */ 10 #ifdef _TDM_STANDALONE 11 #include <tdm_top.h> 12 #else 13 #include <soc/tdm/core/tdm_top.h> 14 #endif 15 16 17 /** 18 @name: tdm_td3_print_pipe_config 19 @param: 20 21 Parses pipe config from class structs 22 */ 23 void 24 tdm_td3_print_pipe_config(tdm_mod_t *_tdm) 25 { 26 int port_phy, port_speed; 27 int param_port_start, param_port_end, param_phy_lo, param_phy_hi, 28 param_pipe_id; 29 30 param_port_start= _tdm->_chip_data.soc_pkg.soc_vars.td3.pipe_start; 31 param_port_end = _tdm->_chip_data.soc_pkg.soc_vars.td3.pipe_end; 32 param_phy_lo = _tdm->_chip_data.soc_pkg.soc_vars.fp_port_lo; 33 param_phy_hi = _tdm->_chip_data.soc_pkg.soc_vars.fp_port_hi; 34 param_pipe_id = _tdm->_core_data.vars_pkg.pipe; 35 36 if (param_port_start >= param_phy_lo && param_port_end <= param_phy_hi){ 37 TDM_BIG_BAR 38 TDM_PRINT3("TDM: Pipe Config: Pipe %d, Port [%d - %d] \n\n", 39 param_pipe_id, param_port_start, param_port_end); 40 TDM_PRINT5("%8s%8s%8s%8s%8s\n","port", "pm", "speed", "LR/OS", "EN/HG"); 41 for (port_phy=param_port_start; port_phy<=param_port_end; port_phy++) { 42 port_speed = tdm_td3_cmn_get_port_speed(_tdm, port_phy); 43 if (port_speed>0) { 44 TDM_PRINT1("%8d", port_phy); 45 TDM_PRINT1("%8d", tdm_td3_cmn_get_port_pm(_tdm, port_phy)); 46 TDM_PRINT1("%8d", (port_speed/1000)); 47 if (BOOL_TRUE == tdm_td3_cmn_chk_port_is_lr(_tdm, port_phy)) { 48 TDM_PRINT1("%8s", "LR"); 49 } else { 50 TDM_PRINT1("%8s", "OS"); 51 } 52 if (BOOL_TRUE == tdm_td3_cmn_chk_port_is_hg(_tdm, port_phy)) { 53 TDM_PRINT1("%8s", "HG"); 54 } else { 55 TDM_PRINT1("%8s", "EN"); 56 } 57 TDM_PRINT0("\n"); 58 } 59 } 60 TDM_BIG_BAR 61 } 62 } 63 64 /** 65 @name: tdm_td3_print_lr_cal 66 @param: 67 68 Print TDM calendar content of current pipe 69 */ 70 int 71 tdm_td3_print_lr_cal(tdm_mod_t *_tdm, int cal_id) 72 { 73 int j, token; 74 int mgmt_2nd_en = 0; 75 int param_phy_lo, param_phy_hi, 76 param_mgmt_mode, 77 param_cal_id, param_cal_len; 78 int *param_cal_main=NULL; 79 80 param_phy_lo = _tdm->_chip_data.soc_pkg.soc_vars.fp_port_lo; 81 param_phy_hi = _tdm->_chip_data.soc_pkg.soc_vars.fp_port_hi; 82 param_mgmt_mode = _tdm->_chip_data.soc_pkg.soc_vars.td3.mgmt_mode; 83 param_cal_id = cal_id; 84 param_cal_len = tdm_td3_cmn_get_pipe_cal_len(_tdm, param_cal_id); 85 TDM_SEL_CAL(param_cal_id, param_cal_main); 86 87 if (param_mgmt_mode == TD3_MGMT_MODE_2_PORT_EN || 88 param_mgmt_mode == TD3_MGMT_MODE_2_PORT_HG) { 89 mgmt_2nd_en = 1; 90 } 91 92 if (param_cal_main != NULL && param_cal_len > 0) { 93 for (j=0; j<param_cal_len; j++) { 94 token = param_cal_main[j]; 95 TDM_PRINT2("TDM: PIPE %d, element #%0d, ", param_cal_id, j); 96 if (((token != TD3_OVSB_TOKEN) && 97 !(token >= param_phy_lo && token <= param_phy_hi)) || 98 (token == TD3_MGM2_TOKEN && mgmt_2nd_en == 1)) { 99 TDM_PRINT0("contains ACCESSORY TOKEN - "); 100 switch (token) { 101 case TD3_CMIC_TOKEN: TDM_PRINT0("CMIC/CPU\n"); break; 102 case TD3_MGM1_TOKEN: TDM_PRINT0("MANAGEMENT-1\n"); break; 103 case TD3_MGM2_TOKEN: TDM_PRINT0("MANAGEMENT-2\n"); break; 104 case TD3_LPB0_TOKEN: TDM_PRINT0("LOOPBACK-0\n"); break; 105 case TD3_LPB1_TOKEN: TDM_PRINT0("LOOPBACK-1\n"); break; 106 case TD3_IDL1_TOKEN: TDM_PRINT0("OPPORTUNISTIC-1\n"); break; 107 case TD3_NULL_TOKEN: TDM_PRINT0("NULL\n"); break; 108 case TD3_IDL2_TOKEN: TDM_PRINT0("IDLE\n"); break; 109 default: TDM_PRINT0("UNKNOWN\n"); break; 110 } 111 } else { 112 TDM_PRINT1("contains physical port #%0d\n", token); 113 } 114 } 115 TDM_SML_BAR 116 } 117 118 return PASS; 119 } 120 121 /** 122 @name: tdm_td3_print_pipe_cal 123 @param: 124 125 Print TDM calendar content of current pipe 126 */ 127 void 128 tdm_td3_print_pipe_cal(tdm_mod_t *_tdm) 129 { 130 int i, j, n; 131 int param_pipe_id, param_cal_id, param_num_phy_pm, 132 param_grp_num=0, param_grp_len=0; 133 int **param_cal_grp=NULL; 134 tdm_calendar_t *param_cal=NULL; 135 136 param_pipe_id = _tdm->_core_data.vars_pkg.pipe; 137 param_cal_id = _tdm->_core_data.vars_pkg.cal_id; 138 param_num_phy_pm = _tdm->_chip_data.soc_pkg.pm_num_phy_modules; 139 140 switch(param_cal_id) { 141 case 0: param_cal = (&(_tdm->_chip_data.cal_0)); break; 142 case 1: param_cal = (&(_tdm->_chip_data.cal_1)); break; 143 /* case 2: param_cal = (&(_tdm->_chip_data.cal_2)); break; 144 case 3: param_cal = (&(_tdm->_chip_data.cal_3)); break; */ 145 default: 146 break;; 147 } 148 149 if (param_cal != NULL) { 150 param_grp_num = param_cal->grp_num; 151 param_grp_len = param_cal->grp_len; 152 param_cal_grp = param_cal->cal_grp; 153 if (param_grp_num > 0 && param_grp_len > 0 && param_cal_grp != NULL) { 154 /* OVSB groups: 1-dimension */ 155 for (i=0; i<param_grp_num; i++) { 156 for (j=0; j<param_grp_len; j++) { 157 TDM_PRINT4("TDM: PIPE %d, OVSB GROUP %2d, element #%03d, port #%0d\n", 158 param_cal_id, i, j, param_cal_grp[i][j]); 159 } 160 } 161 TDM_SML_BAR 162 /* OVSB groups: 2-dimension */ 163 TDM_PRINT1("\nTDM: PIPE %d, OVSB GROUPs 0:11\n", param_pipe_id); 164 for (i=0; i< param_grp_num; i++) { 165 n = param_grp_num/2; 166 if (n>0) { 167 if ((i%n)==0) { 168 TDM_PRINT2("\n%12s%2d\t", "HALF PIPE", (i/n)); 169 for (j=0; j<param_grp_len; j++) { 170 TDM_PRINT1("%3d\t", j+1); 171 } 172 TDM_PRINT0("\n"); 173 } 174 } 175 TDM_PRINT1("OVSB_GROUP[%2d]:\t", i); 176 for (j=0; j< param_grp_len; j++) { 177 TDM_PRINT1("%3d\t", param_cal_grp[i][j]); 178 } 179 TDM_PRINT0("\n"); 180 } 181 TDM_SML_BAR 182 /* Packet Scheduler Calendar */ 183 TDM_PRINT1("\nTDM: PIPE %d, PKT SCHEDULER HALF PIPE 0\n",param_pipe_id); 184 for (j=0; j<TD3_SHAPING_GRP_LEN; j++) { 185 if (j%16==0) { 186 TDM_PRINT2("\n %3d : %3d\t", j, j+15); 187 } 188 TDM_PRINT1("\t%d", param_cal_grp[TD3_SHAPING_GRP_IDX_0][j]); 189 } 190 TDM_PRINT0("\n\n"); 191 TDM_PRINT1("\nTDM: PIPE %d, PKT SCHEDULER HALF PIPE 1\n",param_pipe_id); 192 for (j=0; j<TD3_SHAPING_GRP_LEN; j++) { 193 if (j%16==0) { TDM_PRINT2("\n %3d : %3d\t", j, j+15);} 194 TDM_PRINT1("\t%d",param_cal_grp[TD3_SHAPING_GRP_IDX_1][j]); 195 } 196 TDM_PRINT0("\n"); 197 TDM_SML_BAR 198 } 199 /* PM_number to Port_Block_number mapping table */ 200 TDM_PRINT1("\nTDM: PIPE %d, PM_NUM to PBLK_ID MAP \nPM:PBLK_ID",param_pipe_id); 201 for (j=(16*param_cal_id); j<(16*(param_cal_id+1)) && j<param_num_phy_pm; j++) { 202 TDM_PRINT2("\t %2d:%2d",j, _tdm->_chip_data.soc_pkg.soc_vars.td3.pm_num_to_pblk[j]); 203 } 204 TDM_PRINT0("\n"); 205 TDM_SML_BAR 206 } 207 } 208 209 /** 210 @name: tdm_td3_parse_filter_2nd_mgmt 211 @param: 212 213 This filter is used to fix a RTL defect on LineRate config when 214 the 2nd management port (physical port 128) is enabled. 215 Slot distribution pattern [..., 128, x, x, 125/126/127, ...] 216 */ 217 int 218 tdm_td3_parse_filter_2nd_mgmt(tdm_mod_t *_tdm, int cal_id) 219 { 220 int port_2nd_mgmt, pm_2nd_mgmt, nb_sister_pass; 221 int i, j, k, n, i_l, i_r, p_l, p_r; 222 int param_lr_limit, param_ancl_num, param_cal_len, 223 param_lr_en, param_mgmt_mode, param_sister_min, 224 param_phy_lo, param_phy_hi; 225 int *param_cal_main; 226 227 param_lr_limit = _tdm->_chip_data.soc_pkg.lr_idx_limit; 228 param_ancl_num = _tdm->_chip_data.soc_pkg.tvec_size; 229 param_cal_len = param_lr_limit + param_ancl_num; 230 param_phy_lo = _tdm->_chip_data.soc_pkg.soc_vars.fp_port_lo; 231 param_phy_hi = _tdm->_chip_data.soc_pkg.soc_vars.fp_port_hi; 232 param_lr_en = _tdm->_core_data.vars_pkg.lr_enable; 233 param_mgmt_mode = _tdm->_chip_data.soc_pkg.soc_vars.td3.mgmt_mode; 234 param_sister_min = _tdm->_core_data.rule__prox_port_min; 235 236 TDM_SEL_CAL(cal_id, param_cal_main); 237 238 /* check if filter is applicable: linerate + 2nd_mgmt_enable */ 239 if (!((param_mgmt_mode == TD3_MGMT_MODE_2_PORT_EN || 240 param_mgmt_mode == TD3_MGMT_MODE_2_PORT_HG) && 241 (param_lr_en == BOOL_TRUE))) { 242 return 0; 243 } 244 245 /* filter 2nd management port slots */ 246 TDM_PRINT1("\nFiltering 2nd management port on pattern %s\n", 247 "..., 128, <x, x,> 125/126/127, ..."); 248 port_2nd_mgmt = TD3_MGM2_TOKEN; 249 pm_2nd_mgmt = (port_2nd_mgmt - 1) / 4; 250 for (i = 0; i < param_cal_len; i++) { 251 if (param_cal_main[i] == port_2nd_mgmt) { 252 for (j = 1; j < param_sister_min; j++) { 253 n = (i + j) % param_cal_len; 254 if (((param_cal_main[n] - 1) / 4) == pm_2nd_mgmt) { 255 nb_sister_pass = BOOL_TRUE; 256 for (k = 0; k < param_sister_min - j; k++) { 257 i_l = (i + param_cal_len - 1 - k) % param_cal_len; 258 i_r = (i_l + param_sister_min) % param_cal_len; 259 p_l = param_cal_main[i_l]; 260 p_r = param_cal_main[i_r]; 261 if ((p_l >= param_phy_lo && p_l <= param_phy_hi) && 262 ((p_l - 1) / 4 == (p_r - 1) / 4)) { 263 nb_sister_pass = BOOL_FALSE; 264 break; 265 } 266 } 267 if (nb_sister_pass == BOOL_TRUE) { 268 for (k = 0; k < param_sister_min - j; k++) { 269 i_l = (i + param_cal_len - 1 - k) % param_cal_len; 270 i_r = (i_l + 1) % param_cal_len; 271 param_cal_main[i_r] = param_cal_main[i_l]; 272 } 273 i_l = (i + param_cal_len - k) % param_cal_len; 274 param_cal_main[i_l] = port_2nd_mgmt; 275 TDM_PRINT3("Migrate port %0d from #%03d to #%03d\n", 276 port_2nd_mgmt, i, i_l); 277 } else { 278 TDM_WARN2("%s, slot index %0d\n", 279 "Failed to shift 2nd mgmt port slot", i); 280 } 281 } 282 } 283 } 284 } 285 286 TDM_SML_BAR 287 288 return 0; 289 } 290 291 /** 292 @name: tdm_td3_parse_mgmt 293 @param: 294 295 Parse MGMT/CMIC slots in IDB TDM calendar 296 */ 297 int 298 tdm_td3_parse_mgmt(tdm_mod_t *_tdm, int cal_id) 299 { 300 int cnt = 0, result = PASS; 301 int ave_space, idx = 0, lo, hi, idx_lo, idx_hi, found = BOOL_TRUE; 302 int mgmt_2nd_en, mgmt_slot_num; 303 int param_mgmt_mode, param_token_ancl, param_cal_id, param_cal_len; 304 int *param_cal_main=NULL; 305 306 param_mgmt_mode = _tdm->_chip_data.soc_pkg.soc_vars.td3.mgmt_mode; 307 param_token_ancl= _tdm->_chip_data.soc_pkg.soc_vars.ancl_token; 308 param_cal_id = cal_id; 309 param_cal_len = tdm_td3_cmn_get_pipe_cal_len(_tdm, param_cal_id); 310 TDM_SEL_CAL(param_cal_id, param_cal_main); 311 312 if (param_mgmt_mode == TD3_MGMT_MODE_2_PORT_EN || 313 param_mgmt_mode == TD3_MGMT_MODE_2_PORT_HG) { 314 mgmt_2nd_en = 1; 315 mgmt_slot_num = 8; 316 } else { 317 mgmt_2nd_en = 0; 318 mgmt_slot_num = 4; 319 } 320 321 if (mgmt_slot_num > 0) { 322 ave_space = param_cal_len / mgmt_slot_num; 323 } 324 325 if (param_cal_main != NULL && param_cal_len > 0) { 326 /* find first pos of ANCL slot */ 327 while (idx < param_cal_len && 328 param_cal_main[idx] != param_token_ancl) { 329 idx++; 330 } 331 332 /* allocate MGMT/CMIC slots */ 333 while (cnt < mgmt_slot_num && found == BOOL_TRUE) { 334 found = BOOL_FALSE; 335 if (param_cal_main[idx] == param_token_ancl) { 336 found = BOOL_TRUE; 337 } else { 338 lo = 0; 339 hi = 0; 340 idx_lo = idx; 341 idx_hi = idx; 342 do { 343 lo++; 344 hi++; 345 idx_lo = (param_cal_len + idx_lo - 1) % param_cal_len; 346 idx_hi = (idx_hi + 1) % param_cal_len; 347 } while ((lo + hi) < param_cal_len && 348 param_cal_main[idx_lo] != param_token_ancl && 349 param_cal_main[idx_hi] != param_token_ancl); 350 if (param_cal_main[idx_lo] == param_token_ancl) { 351 idx = idx_lo; 352 found = BOOL_TRUE; 353 } else if (param_cal_main[idx_hi] == param_token_ancl) { 354 idx = idx_hi; 355 found = BOOL_TRUE; 356 } 357 } 358 if (found == BOOL_TRUE) { 359 switch (param_cal_id) { 360 case 0: /* IDB pipe 0*/ 361 case 4: /* MMU pipe 0*/ 362 param_cal_main[idx] = TD3_CMIC_TOKEN; 363 break; 364 case 1: /* IDB pipe 1*/ 365 case 5: /* MMU pipe 1*/ 366 if (mgmt_2nd_en) { 367 param_cal_main[idx] = (cnt % 2 == 0) ? 368 TD3_MGM1_TOKEN : 369 TD3_MGM2_TOKEN; 370 } else { 371 param_cal_main[idx] = TD3_MGM1_TOKEN; 372 } 373 break; 374 default : 375 break; 376 } 377 TDM_PRINT2("TDM: Allocate MGMT/CMIC slot %0d at index #%03d\n", 378 cnt+1, idx); 379 cnt++; 380 idx = (idx + ave_space) % param_cal_len; 381 if (cnt >= mgmt_slot_num) { 382 break; 383 } 384 } 385 } 386 TDM_PRINT0("\n"); 387 388 /* check allocated slot amount */ 389 if (cnt < mgmt_slot_num) { 390 result = FAIL; 391 TDM_ERROR4("%s, cal_id %0d, req_slot %0d, alloc_slot %0d\n", 392 "Failed in MGMT/CMIC slot allocation", 393 param_cal_id, mgmt_slot_num, cnt); 394 } 395 } 396 397 /* Filter slots of the 2nd mamagement port (temporal fix for RTL) */ 398 tdm_td3_parse_filter_2nd_mgmt(_tdm, cal_id); 399 400 return (result); 401 } 402 403 /** 404 @name: tdm_td3_parse_acc_idb 405 @param: 406 407 Parse ACCESSORY slots (LOOPBACK, OPP1, OPP2, NULL, IDLE) 408 */ 409 int 410 tdm_td3_parse_acc_idb(tdm_mod_t *_tdm, int cal_id) 411 { 412 int j, cnt = 0; 413 int param_token_lpbk, param_token_ancl, param_cal_id, param_cal_len; 414 int *param_cal_main=NULL; 415 416 param_token_ancl= _tdm->_chip_data.soc_pkg.soc_vars.ancl_token; 417 param_cal_id = cal_id; 418 param_cal_len = tdm_td3_cmn_get_pipe_cal_len(_tdm, param_cal_id); 419 TDM_SEL_CAL(param_cal_id, param_cal_main); 420 421 switch (param_cal_id) { 422 case 0: param_token_lpbk = TD3_LPB0_TOKEN; break; 423 case 1: param_token_lpbk = TD3_LPB1_TOKEN; break; 424 default: return FAIL; break; 425 } 426 427 if (param_cal_main != NULL && param_cal_len > 0) { 428 for (j=0; j<param_cal_len; j++) { 429 if (param_cal_main[j] == param_token_ancl) { 430 cnt++; 431 switch (cnt) { 432 case 1: case 3: case 5: case 7: 433 param_cal_main[j] = param_token_lpbk; 434 break; 435 case 2: 436 param_cal_main[j] = TD3_IDL1_TOKEN; 437 break; 438 case 6: 439 param_cal_main[j] = TD3_NULL_TOKEN; 440 break; 441 case 4: case 8: 442 param_cal_main[j] = TD3_IDL2_TOKEN; 443 break; 444 default: 445 break; 446 } 447 } 448 } 449 } 450 451 return PASS; 452 } 453 454 /** 455 @name: tdm_td3_parse_acc_mmu 456 @param: 457 458 Parse ACCESSORY slots (LOOPBACK, OPP1, OPP2, NULL, IDLE) 459 */ 460 int 461 tdm_td3_parse_acc_mmu(tdm_mod_t *_tdm, int cal_id) 462 { 463 int cnt = 0, j; 464 int param_token_lpbk, param_token_ancl, param_cal_id, param_cal_len; 465 int *param_cal_main=NULL; 466 467 param_token_ancl= _tdm->_chip_data.soc_pkg.soc_vars.ancl_token; 468 param_cal_id = cal_id; 469 param_cal_len = tdm_td3_cmn_get_pipe_cal_len(_tdm, param_cal_id); 470 TDM_SEL_CAL(param_cal_id, param_cal_main); 471 472 switch (param_cal_id) { 473 case 4: param_token_lpbk = TD3_LPB0_TOKEN; break; 474 case 5: param_token_lpbk = TD3_LPB1_TOKEN; break; 475 default: return FAIL; break; 476 } 477 478 if (param_cal_main != NULL && param_cal_len > 0) { 479 for (j=0; j<param_cal_len; j++) { 480 if (param_cal_main[j] == param_token_ancl) { 481 cnt++; 482 switch (cnt) { 483 case 1: case 3: case 5: case 7: 484 param_cal_main[j] = param_token_lpbk; 485 break; 486 case 2: case 4: case 6: 487 param_cal_main[j] = TD3_NULL_TOKEN; 488 break; 489 case 8: 490 param_cal_main[j] = TD3_IDL2_TOKEN; 491 break; 492 default: 493 break; 494 } 495 } 496 } 497 } 498 499 return PASS; 500 } 501 502 /** 503 @name: tdm_td3_parse_ancl 504 @param: 505 506 Parse ANCILLARY slots (MGMT/CMIC, LOOPBACK, OPP1, OPP2, NULL, IDLE) 507 */ 508 int 509 tdm_td3_parse_ancl(tdm_mod_t *_tdm, int cal_id) 510 { 511 int idb_en = 0, mmu_en = 0, result = PASS; 512 513 switch (cal_id) { 514 case 0: case 1: idb_en = 1; break; 515 case 4: case 5: mmu_en = 1; break; 516 default: 517 TDM_ERROR1("Invalid calendar ID - %0d\n", cal_id); 518 return FAIL; 519 break; 520 } 521 522 /* MGMT/CMIC */ 523 if (tdm_td3_parse_mgmt(_tdm, cal_id) != PASS) { 524 TDM_ERROR1("Failed in MGMT/CMIC allocation, cal_id %0d\n", cal_id); 525 result = FAIL; 526 } 527 528 /* LOOPBACK, OPP1, OPP2, NULL, IDLE */ 529 if (idb_en == 1) { 530 if (tdm_td3_parse_acc_idb(_tdm, cal_id) != PASS) { 531 TDM_ERROR1("Failed in ANCL allocation, cal_id %0d\n", cal_id); 532 result = FAIL; 533 } 534 } else if (mmu_en == 1) { 535 if (tdm_td3_parse_acc_mmu(_tdm, cal_id) != PASS) { 536 TDM_ERROR1("Failed in ANCL allocation, cal_id %0d\n", cal_id); 537 result = FAIL; 538 } 539 } 540 541 return result; 542 } 543 544 /** 545 @name: tdm_td3_parse_tdm_tbl 546 @param: 547 548 Post-process TDM calendar tokenized entries 549 */ 550 int 551 tdm_td3_parse_tdm_tbl(tdm_mod_t *_tdm) 552 { 553 int j, result = PASS; 554 int param_cal_id, param_cal_id_idb, param_cal_id_mmu; 555 tdm_calendar_t *cal_idb=NULL; 556 tdm_calendar_t *cal_mmu=NULL; 557 558 param_cal_id = _tdm->_core_data.vars_pkg.cal_id; 559 560 switch(param_cal_id) { 561 case 0: 562 cal_idb = (&(_tdm->_chip_data.cal_0)); 563 cal_mmu = (&(_tdm->_chip_data.cal_4)); 564 param_cal_id_idb = 0; 565 param_cal_id_mmu = 4; 566 break; 567 case 1: 568 cal_idb = (&(_tdm->_chip_data.cal_1)); 569 cal_mmu = (&(_tdm->_chip_data.cal_5)); 570 param_cal_id_idb = 1; 571 param_cal_id_mmu = 5; 572 break; 573 case 2: 574 cal_idb = (&(_tdm->_chip_data.cal_2)); 575 cal_mmu = (&(_tdm->_chip_data.cal_6)); 576 param_cal_id_idb = 2; 577 param_cal_id_mmu = 6; 578 break; 579 case 3: 580 cal_idb = (&(_tdm->_chip_data.cal_3)); 581 cal_mmu = (&(_tdm->_chip_data.cal_7)); 582 param_cal_id_idb = 3; 583 param_cal_id_mmu = 7; 584 break; 585 default: 586 TDM_PRINT1("Invalid calendar ID - %0d\n", param_cal_id); 587 return (TDM_EXEC_CORE_SIZE+1); 588 } 589 590 /* construct MMU TDM calendar by copying from IDB TDM calendar */ 591 for (j=0; j<(cal_idb->cal_len) && j<(cal_mmu->cal_len); j++) { 592 cal_mmu->cal_main[j] = cal_idb->cal_main[j]; 593 } 594 595 /* parse ancillary slots in IDB TDM calendar */ 596 if (tdm_td3_parse_ancl(_tdm, param_cal_id_idb) != PASS) { 597 result = FAIL; 598 } 599 tdm_td3_print_lr_cal(_tdm, param_cal_id_idb); 600 601 /* parse ancillary slots in MMU TDM calendar */ 602 if (tdm_td3_parse_ancl(_tdm, param_cal_id_mmu) != PASS) { 603 result = FAIL; 604 } 605 tdm_td3_print_lr_cal(_tdm, param_cal_id_mmu); 606 607 /* construct Oversub Half Pipes */ 608 if (tdm_td3_vbs_scheduler_ovs(_tdm) != PASS) { 609 result = FAIL; 610 } 611 612 /* print: OVSB_HALF_PIPE, Packet_Scheduler, PORT_BLOCK_Map */ 613 tdm_td3_print_pipe_cal(_tdm); 614 615 if (result != PASS) { 616 return (TDM_EXEC_CORE_SIZE+1); 617 } 618 return ( _tdm->_chip_exec[TDM_CHIP_EXEC__POST]( _tdm ) ); 619 }