tdm_td2p_shim.c (15765B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * $All Rights Reserved.$ 7 * 8 * TDM chip to core API shim layer 9 */ 10 #ifdef _TDM_STANDALONE 11 #include <tdm_top.h> 12 #else 13 #include <soc/tdm/core/tdm_top.h> 14 #endif 15 16 17 /** 18 @name: tdm_chip_td2p_shim_core 19 @param: 20 21 Downward abstraction layer between TDM.4 and TDM.5 API core data 22 */ 23 int 24 tdm_chip_td2p_shim_core( tdm_mod_t *_tdm, tdm_chip_legacy_t *_tdm_td2p) 25 { 26 int idx1, idx2; 27 28 if (_tdm==NULL || _tdm_td2p==NULL) {return FAIL;} 29 30 /* port map */ 31 for (idx1=0; idx1<TD2P_NUM_PHY_PM; idx1++) { 32 for (idx2=0; idx2<TD2P_NUM_PM_LNS; idx2++) { 33 _tdm_td2p->pmap[idx1][idx2] = _tdm->_chip_data.soc_pkg.pmap[idx1][idx2]; 34 } 35 } 36 /* speed */ 37 for (idx1=0; idx1<TD2P_NUM_EXT_PORTS; idx1++) { 38 _tdm_td2p->tdm_globals.speed[idx1] = _tdm->_chip_data.soc_pkg.speed[idx1]; 39 } 40 /* freq */ 41 _tdm_td2p->tdm_globals.clk_freq = _tdm->_chip_data.soc_pkg.clk_freq; 42 /* state : Realign port state array to old specification */ 43 for (idx1=0; idx1<TD2P_NUM_EXT_PORTS; idx1++) { 44 _tdm_td2p->tdm_globals.port_rates_array[idx1] = _tdm->_chip_data.soc_pkg.state[idx1]; 45 } 46 for (idx1=0; idx1<(TD2P_NUM_EXT_PORTS-1); idx1++) { 47 _tdm_td2p->tdm_globals.port_rates_array[idx1] = _tdm_td2p->tdm_globals.port_rates_array[idx1+1]; 48 } 49 /* encap_type */ 50 for (idx1=0; idx1<TD2P_NUM_EXT_PORTS; idx1++) { 51 if (idx1%TD2P_NUM_PM_LNS==0 && (idx1/TD2P_NUM_PM_LNS)<TD2P_NUM_PM_MOD) { 52 _tdm_td2p->tdm_globals.pm_encap_type[idx1/TD2P_NUM_PM_LNS] = (_tdm->_chip_data.soc_pkg.state[idx1]==PORT_STATE__LINERATE_HG||_tdm->_chip_data.soc_pkg.state[idx1]==PORT_STATE__OVERSUB_HG)?(PM_ENCAP__HIGIG2):(PM_ENCAP__ETHRNT); 53 } 54 } 55 56 return PASS; 57 } 58 59 60 /** 61 @name: tdm_chip_td2p_shim__ing_wrap 62 @param: 63 64 Downward abstraction layer between TDM.4 and TDM.5 API ingress scheduler 65 */ 66 int 67 tdm_chip_td2p_shim__ing_wrap( tdm_mod_t *_tdm, tdm_chip_legacy_t *_tdm_td2p) 68 { 69 if (FAIL == tdm_chip_td2p_shim_core(_tdm, _tdm_td2p)) {return FAIL;} 70 71 TDM_MSET(_tdm_td2p->tdm_pgw.pgw_tdm_tbl_x0,TD2P_NUM_EXT_PORTS,TD2P_LR_LLS_LEN); 72 TDM_MSET(_tdm_td2p->tdm_pgw.ovs_tdm_tbl_x0,TD2P_NUM_EXT_PORTS,TD2P_OS_LLS_GRP_LEN); 73 TDM_MSET(_tdm_td2p->tdm_pgw.ovs_spacing_x0,TD2P_NUM_EXT_PORTS,TD2P_OS_LLS_GRP_LEN); 74 TDM_MSET(_tdm_td2p->tdm_pgw.pgw_tdm_tbl_x1,TD2P_NUM_EXT_PORTS,TD2P_LR_LLS_LEN); 75 TDM_MSET(_tdm_td2p->tdm_pgw.ovs_tdm_tbl_x1,TD2P_NUM_EXT_PORTS,TD2P_OS_LLS_GRP_LEN); 76 TDM_MSET(_tdm_td2p->tdm_pgw.ovs_spacing_x1,TD2P_NUM_EXT_PORTS,TD2P_OS_LLS_GRP_LEN); 77 TDM_MSET(_tdm_td2p->tdm_pgw.pgw_tdm_tbl_y0,TD2P_NUM_EXT_PORTS,TD2P_LR_LLS_LEN); 78 TDM_MSET(_tdm_td2p->tdm_pgw.ovs_tdm_tbl_y0,TD2P_NUM_EXT_PORTS,TD2P_OS_LLS_GRP_LEN); 79 TDM_MSET(_tdm_td2p->tdm_pgw.ovs_spacing_y0,TD2P_NUM_EXT_PORTS,TD2P_OS_LLS_GRP_LEN); 80 TDM_MSET(_tdm_td2p->tdm_pgw.pgw_tdm_tbl_y1,TD2P_NUM_EXT_PORTS,TD2P_LR_LLS_LEN); 81 TDM_MSET(_tdm_td2p->tdm_pgw.ovs_tdm_tbl_y1,TD2P_NUM_EXT_PORTS,TD2P_OS_LLS_GRP_LEN); 82 TDM_MSET(_tdm_td2p->tdm_pgw.ovs_spacing_y1,TD2P_NUM_EXT_PORTS,TD2P_OS_LLS_GRP_LEN); 83 84 TDM_MSET(_tdm_td2p->tdm_pipe_table_x.tdm_pipe_main,TD2P_NUM_EXT_PORTS,TD2P_LR_VBS_LEN); 85 TDM_MSET(_tdm_td2p->tdm_pipe_table_x.tdm_ovs_grp_0,TD2P_NUM_EXT_PORTS,TD2P_OS_VBS_GRP_LEN); 86 TDM_MSET(_tdm_td2p->tdm_pipe_table_x.tdm_ovs_grp_1,TD2P_NUM_EXT_PORTS,TD2P_OS_VBS_GRP_LEN); 87 TDM_MSET(_tdm_td2p->tdm_pipe_table_x.tdm_ovs_grp_2,TD2P_NUM_EXT_PORTS,TD2P_OS_VBS_GRP_LEN); 88 TDM_MSET(_tdm_td2p->tdm_pipe_table_x.tdm_ovs_grp_3,TD2P_NUM_EXT_PORTS,TD2P_OS_VBS_GRP_LEN); 89 TDM_MSET(_tdm_td2p->tdm_pipe_table_x.tdm_ovs_grp_4,TD2P_NUM_EXT_PORTS,TD2P_OS_VBS_GRP_LEN); 90 TDM_MSET(_tdm_td2p->tdm_pipe_table_x.tdm_ovs_grp_5,TD2P_NUM_EXT_PORTS,TD2P_OS_VBS_GRP_LEN); 91 TDM_MSET(_tdm_td2p->tdm_pipe_table_x.tdm_ovs_grp_6,TD2P_NUM_EXT_PORTS,TD2P_OS_VBS_GRP_LEN); 92 TDM_MSET(_tdm_td2p->tdm_pipe_table_x.tdm_ovs_grp_7,TD2P_NUM_EXT_PORTS,TD2P_OS_VBS_GRP_LEN); 93 94 TDM_MSET(_tdm_td2p->tdm_pipe_table_y.tdm_pipe_main,TD2P_NUM_EXT_PORTS,TD2P_LR_VBS_LEN); 95 TDM_MSET(_tdm_td2p->tdm_pipe_table_y.tdm_ovs_grp_0,TD2P_NUM_EXT_PORTS,TD2P_OS_VBS_GRP_LEN); 96 TDM_MSET(_tdm_td2p->tdm_pipe_table_y.tdm_ovs_grp_1,TD2P_NUM_EXT_PORTS,TD2P_OS_VBS_GRP_LEN); 97 TDM_MSET(_tdm_td2p->tdm_pipe_table_y.tdm_ovs_grp_2,TD2P_NUM_EXT_PORTS,TD2P_OS_VBS_GRP_LEN); 98 TDM_MSET(_tdm_td2p->tdm_pipe_table_y.tdm_ovs_grp_3,TD2P_NUM_EXT_PORTS,TD2P_OS_VBS_GRP_LEN); 99 TDM_MSET(_tdm_td2p->tdm_pipe_table_y.tdm_ovs_grp_4,TD2P_NUM_EXT_PORTS,TD2P_OS_VBS_GRP_LEN); 100 TDM_MSET(_tdm_td2p->tdm_pipe_table_y.tdm_ovs_grp_5,TD2P_NUM_EXT_PORTS,TD2P_OS_VBS_GRP_LEN); 101 TDM_MSET(_tdm_td2p->tdm_pipe_table_y.tdm_ovs_grp_6,TD2P_NUM_EXT_PORTS,TD2P_OS_VBS_GRP_LEN); 102 TDM_MSET(_tdm_td2p->tdm_pipe_table_y.tdm_ovs_grp_7,TD2P_NUM_EXT_PORTS,TD2P_OS_VBS_GRP_LEN); 103 104 return PASS; 105 106 } 107 108 109 /** 110 @name: tdm_chip_td2p_shim__egr_wrap 111 @param: 112 113 Downward abstraction layer between TDM.4 and TDM.5 API egress scheduler 114 */ 115 int 116 tdm_chip_td2p_shim__egr_wrap( tdm_mod_t *_tdm, tdm_chip_legacy_t *_tdm_td2p ) 117 { 118 if (FAIL == tdm_chip_td2p_shim_core(_tdm, _tdm_td2p)) {return FAIL;} 119 120 TDM_COPY(_tdm_td2p->tdm_pgw.pgw_tdm_tbl_x0,_tdm->_chip_data.cal_0.cal_main,sizeof(int)*TD2P_LR_LLS_LEN); 121 TDM_COPY(_tdm_td2p->tdm_pgw.ovs_tdm_tbl_x0,_tdm->_chip_data.cal_0.cal_grp[0],sizeof(int)*TD2P_OS_LLS_GRP_LEN); 122 TDM_COPY(_tdm_td2p->tdm_pgw.pgw_tdm_tbl_x1,_tdm->_chip_data.cal_1.cal_main,sizeof(int)*TD2P_LR_LLS_LEN); 123 TDM_COPY(_tdm_td2p->tdm_pgw.ovs_tdm_tbl_x1,_tdm->_chip_data.cal_1.cal_grp[0],sizeof(int)*TD2P_OS_LLS_GRP_LEN); 124 TDM_COPY(_tdm_td2p->tdm_pgw.pgw_tdm_tbl_y0,_tdm->_chip_data.cal_2.cal_main,sizeof(int)*TD2P_LR_LLS_LEN); 125 TDM_COPY(_tdm_td2p->tdm_pgw.ovs_tdm_tbl_y0,_tdm->_chip_data.cal_2.cal_grp[0],sizeof(int)*TD2P_OS_LLS_GRP_LEN); 126 TDM_COPY(_tdm_td2p->tdm_pgw.pgw_tdm_tbl_y1,_tdm->_chip_data.cal_3.cal_main,sizeof(int)*TD2P_LR_LLS_LEN); 127 TDM_COPY(_tdm_td2p->tdm_pgw.ovs_tdm_tbl_y1,_tdm->_chip_data.cal_3.cal_grp[0],sizeof(int)*TD2P_OS_LLS_GRP_LEN); 128 129 TDM_MSET(_tdm_td2p->tdm_pipe_table_x.tdm_pipe_main,TD2P_NUM_EXT_PORTS,TD2P_LR_VBS_LEN); 130 TDM_MSET(_tdm_td2p->tdm_pipe_table_x.tdm_ovs_grp_0,TD2P_NUM_EXT_PORTS,TD2P_OS_VBS_GRP_LEN); 131 TDM_MSET(_tdm_td2p->tdm_pipe_table_x.tdm_ovs_grp_1,TD2P_NUM_EXT_PORTS,TD2P_OS_VBS_GRP_LEN); 132 TDM_MSET(_tdm_td2p->tdm_pipe_table_x.tdm_ovs_grp_2,TD2P_NUM_EXT_PORTS,TD2P_OS_VBS_GRP_LEN); 133 TDM_MSET(_tdm_td2p->tdm_pipe_table_x.tdm_ovs_grp_3,TD2P_NUM_EXT_PORTS,TD2P_OS_VBS_GRP_LEN); 134 TDM_MSET(_tdm_td2p->tdm_pipe_table_x.tdm_ovs_grp_4,TD2P_NUM_EXT_PORTS,TD2P_OS_VBS_GRP_LEN); 135 TDM_MSET(_tdm_td2p->tdm_pipe_table_x.tdm_ovs_grp_5,TD2P_NUM_EXT_PORTS,TD2P_OS_VBS_GRP_LEN); 136 TDM_MSET(_tdm_td2p->tdm_pipe_table_x.tdm_ovs_grp_6,TD2P_NUM_EXT_PORTS,TD2P_OS_VBS_GRP_LEN); 137 TDM_MSET(_tdm_td2p->tdm_pipe_table_x.tdm_ovs_grp_7,TD2P_NUM_EXT_PORTS,TD2P_OS_VBS_GRP_LEN); 138 139 TDM_MSET(_tdm_td2p->tdm_pipe_table_y.tdm_pipe_main,TD2P_NUM_EXT_PORTS,TD2P_LR_VBS_LEN); 140 TDM_MSET(_tdm_td2p->tdm_pipe_table_y.tdm_ovs_grp_0,TD2P_NUM_EXT_PORTS,TD2P_OS_VBS_GRP_LEN); 141 TDM_MSET(_tdm_td2p->tdm_pipe_table_y.tdm_ovs_grp_1,TD2P_NUM_EXT_PORTS,TD2P_OS_VBS_GRP_LEN); 142 TDM_MSET(_tdm_td2p->tdm_pipe_table_y.tdm_ovs_grp_2,TD2P_NUM_EXT_PORTS,TD2P_OS_VBS_GRP_LEN); 143 TDM_MSET(_tdm_td2p->tdm_pipe_table_y.tdm_ovs_grp_3,TD2P_NUM_EXT_PORTS,TD2P_OS_VBS_GRP_LEN); 144 TDM_MSET(_tdm_td2p->tdm_pipe_table_y.tdm_ovs_grp_4,TD2P_NUM_EXT_PORTS,TD2P_OS_VBS_GRP_LEN); 145 TDM_MSET(_tdm_td2p->tdm_pipe_table_y.tdm_ovs_grp_5,TD2P_NUM_EXT_PORTS,TD2P_OS_VBS_GRP_LEN); 146 TDM_MSET(_tdm_td2p->tdm_pipe_table_y.tdm_ovs_grp_6,TD2P_NUM_EXT_PORTS,TD2P_OS_VBS_GRP_LEN); 147 TDM_MSET(_tdm_td2p->tdm_pipe_table_y.tdm_ovs_grp_7,TD2P_NUM_EXT_PORTS,TD2P_OS_VBS_GRP_LEN); 148 149 150 return PASS; 151 152 } 153 154 155 /** 156 @name: tdm_chip_td2p_shim__which_tsc 157 @param: 158 159 Upward abstraction layer between TDM.4 and TDM.5 API 160 Only returns enough of TDM.5 style struct to drive scan functions, do not use as class 161 */ 162 tdm_mod_t* 163 tdm_chip_td2p_shim__which_tsc( int port, int tsc[TD2P_NUM_PHY_PM][TD2P_NUM_PM_LNS] ) 164 { 165 int idx1, idx2; 166 tdm_mod_t *_tdm_s; 167 168 _tdm_s = TDM_ALLOC(sizeof(tdm_mod_t),"TDM shim allocation"); 169 if (!_tdm_s) { 170 return NULL; 171 } 172 173 _tdm_s->_chip_data.soc_pkg.num_ext_ports = TD2P_NUM_EXT_PORTS; 174 _tdm_s->_chip_data.soc_pkg.pmap_num_modules = TD2P_NUM_PHY_PM; 175 _tdm_s->_chip_data.soc_pkg.pmap_num_lanes = TD2P_NUM_PM_LNS; 176 _tdm_s->_chip_data.soc_pkg.pmap=(int **) TDM_ALLOC((_tdm_s->_chip_data.soc_pkg.pmap_num_modules)*sizeof(int *), "portmod_map_l1"); 177 for (idx1=0; idx1<(_tdm_s->_chip_data.soc_pkg.pmap_num_modules); idx1++) { 178 _tdm_s->_chip_data.soc_pkg.pmap[idx1]=(int *) TDM_ALLOC((_tdm_s->_chip_data.soc_pkg.pmap_num_lanes)*sizeof(int), "portmod_map_l2"); 179 TDM_MSET(_tdm_s->_chip_data.soc_pkg.pmap[idx1],(_tdm_s->_chip_data.soc_pkg.num_ext_ports),_tdm_s->_chip_data.soc_pkg.pmap_num_lanes); 180 } 181 for (idx1=0; idx1<TD2P_NUM_PHY_PM; idx1++) { 182 for (idx2=0; idx2<TD2P_NUM_PM_LNS; idx2++) { 183 _tdm_s->_chip_data.soc_pkg.pmap[idx1][idx2] = tsc[idx1][idx2]; 184 } 185 } 186 187 _tdm_s->_core_data.vars_pkg.port = port; 188 189 return _tdm_s; 190 191 } 192 193 194 /** 195 @name: tdm_chip_td2p_shim__check_ethernet 196 @param: 197 198 Upward abstraction layer between TDM.4 and TDM.5 API 199 */ 200 tdm_mod_t* 201 tdm_chip_td2p_shim__check_ethernet( int port, enum port_speed_e speed[TD2P_NUM_EXT_PORTS], int tsc[TD2P_NUM_PHY_PM][TD2P_NUM_PM_LNS], int traffic[TD2P_NUM_PM_MOD] ) 202 { 203 int idx1, idx2; 204 tdm_mod_t *_tdm_s; 205 206 _tdm_s = TDM_ALLOC(sizeof(tdm_mod_t),"TDM shim allocation"); 207 if (!_tdm_s) { 208 return NULL; 209 } 210 211 _tdm_s->_chip_data.soc_pkg.speed=TDM_ALLOC(TD2P_NUM_EXT_PORTS*sizeof(int *), "port speed list"); 212 for (idx1=0; idx1<TD2P_NUM_EXT_PORTS; idx1++) { 213 _tdm_s->_chip_data.soc_pkg.speed[idx1] = speed[idx1]; 214 } 215 _tdm_s->_chip_data.soc_pkg.pmap_num_modules = TD2P_NUM_PHY_PM; 216 _tdm_s->_chip_data.soc_pkg.pmap_num_lanes = TD2P_NUM_PM_LNS; 217 _tdm_s->_chip_data.soc_pkg.pmap=(int **) TDM_ALLOC((_tdm_s->_chip_data.soc_pkg.pmap_num_modules)*sizeof(int *), "portmod_map_l1"); 218 for (idx1=0; idx1<(_tdm_s->_chip_data.soc_pkg.pmap_num_modules); idx1++) { 219 _tdm_s->_chip_data.soc_pkg.pmap[idx1]=(int *) TDM_ALLOC((_tdm_s->_chip_data.soc_pkg.pmap_num_lanes)*sizeof(int), "portmod_map_l2"); 220 TDM_MSET(_tdm_s->_chip_data.soc_pkg.pmap[idx1],(_tdm_s->_chip_data.soc_pkg.num_ext_ports),_tdm_s->_chip_data.soc_pkg.pmap_num_lanes); 221 } 222 for (idx1=0; idx1<TD2P_NUM_PHY_PM; idx1++) { 223 for (idx2=0; idx2<TD2P_NUM_PM_LNS; idx2++) { 224 _tdm_s->_chip_data.soc_pkg.pmap[idx1][idx2] = tsc[idx1][idx2]; 225 } 226 } 227 for (idx1=0; idx1<TD2P_NUM_PM_MOD; idx1++) { 228 _tdm_s->_chip_data.soc_pkg.soc_vars.td2p.pm_encap_type[idx1] = traffic[idx1]; 229 } 230 231 _tdm_s->_core_data.vars_pkg.port = port; 232 return _tdm_s; 233 234 } 235 236 237 /** 238 @name: tdm_chip_td2p_shim__check_ethernet_d 239 @param: 240 241 Upward abstraction layer between TDM.4 and TDM.5 API 242 */ 243 tdm_mod_t* 244 tdm_chip_td2p_shim__check_ethernet_d( int port, enum port_speed_e speed[TD2P_NUM_EXT_PORTS], int **tsc, int traffic[TD2P_NUM_PM_MOD] ) 245 { 246 int idx1, idx2; 247 tdm_mod_t *_tdm_s; 248 249 _tdm_s = TDM_ALLOC(sizeof(tdm_mod_t),"TDM shim allocation"); 250 if (!_tdm_s) { 251 return NULL; 252 } 253 254 _tdm_s->_chip_data.soc_pkg.speed=TDM_ALLOC(TD2P_NUM_EXT_PORTS*sizeof(int *), "port speed list"); 255 for (idx1=0; idx1<TD2P_NUM_EXT_PORTS; idx1++) { 256 _tdm_s->_chip_data.soc_pkg.speed[idx1] = speed[idx1]; 257 } 258 _tdm_s->_chip_data.soc_pkg.pmap_num_modules = TD2P_NUM_PHY_PM; 259 _tdm_s->_chip_data.soc_pkg.pmap_num_lanes = TD2P_NUM_PM_LNS; 260 _tdm_s->_chip_data.soc_pkg.pmap=(int **) TDM_ALLOC((_tdm_s->_chip_data.soc_pkg.pmap_num_modules)*sizeof(int *), "portmod_map_l1"); 261 for (idx1=0; idx1<(_tdm_s->_chip_data.soc_pkg.pmap_num_modules); idx1++) { 262 _tdm_s->_chip_data.soc_pkg.pmap[idx1]=(int *) TDM_ALLOC((_tdm_s->_chip_data.soc_pkg.pmap_num_lanes)*sizeof(int), "portmod_map_l2"); 263 TDM_MSET(_tdm_s->_chip_data.soc_pkg.pmap[idx1],(_tdm_s->_chip_data.soc_pkg.num_ext_ports),_tdm_s->_chip_data.soc_pkg.pmap_num_lanes); 264 } 265 for (idx1=0; idx1<TD2P_NUM_PHY_PM; idx1++) { 266 for (idx2=0; idx2<TD2P_NUM_PM_LNS; idx2++) { 267 _tdm_s->_chip_data.soc_pkg.pmap[idx1][idx2] = tsc[idx1][idx2]; 268 } 269 } 270 for (idx1=0; idx1<TD2P_NUM_PM_MOD; idx1++) { 271 _tdm_s->_chip_data.soc_pkg.soc_vars.td2p.pm_encap_type[idx1] = traffic[idx1]; 272 } 273 274 _tdm_s->_core_data.vars_pkg.port = port; 275 return _tdm_s; 276 277 } 278 279 280 /** 281 @name: tdm_chip_td2p_shim__scan_which_tsc_alloc 282 @param: 283 */ 284 tdm_mod_t* 285 tdm_chip_td2p_shim__scan_which_tsc_alloc( int port, int tsc[TD2P_NUM_PHY_PM][TD2P_NUM_PM_LNS] ) 286 { 287 int idx1, idx2; 288 tdm_mod_t *_tdm_s; 289 290 _tdm_s = TDM_ALLOC(sizeof(tdm_mod_t),"TDM shim allocation"); 291 if (!_tdm_s) { 292 return NULL; 293 } 294 295 _tdm_s->_chip_data.soc_pkg.num_ext_ports = TD2P_NUM_EXT_PORTS; 296 _tdm_s->_chip_data.soc_pkg.pmap_num_modules = TD2P_NUM_PHY_PM; 297 _tdm_s->_chip_data.soc_pkg.pmap_num_lanes = TD2P_NUM_PM_LNS; 298 _tdm_s->_chip_data.soc_pkg.pmap=(int **) TDM_ALLOC((_tdm_s->_chip_data.soc_pkg.pmap_num_modules)*sizeof(int *), "portmod_map_l1"); 299 for (idx1=0; idx1<(_tdm_s->_chip_data.soc_pkg.pmap_num_modules); idx1++) { 300 _tdm_s->_chip_data.soc_pkg.pmap[idx1]=(int *) TDM_ALLOC((_tdm_s->_chip_data.soc_pkg.pmap_num_lanes)*sizeof(int), "portmod_map_l2"); 301 TDM_MSET(_tdm_s->_chip_data.soc_pkg.pmap[idx1],(_tdm_s->_chip_data.soc_pkg.num_ext_ports),_tdm_s->_chip_data.soc_pkg.pmap_num_lanes); 302 } 303 for (idx1=0; idx1<TD2P_NUM_PHY_PM; idx1++) { 304 for (idx2=0; idx2<TD2P_NUM_PM_LNS; idx2++) { 305 _tdm_s->_chip_data.soc_pkg.pmap[idx1][idx2] = tsc[idx1][idx2]; 306 } 307 } 308 309 _tdm_s->_core_data.vars_pkg.port = port; 310 311 return _tdm_s; 312 313 } 314 315 316 /** 317 @name: tdm_chip_td2p_shim__scan_which_tsc_free 318 @param: 319 */ 320 int 321 tdm_chip_td2p_shim__scan_which_tsc_free(tdm_mod_t *_tdm) 322 { 323 int idx1; 324 tdm_mod_t *_tdm_s=_tdm; 325 /* pmap */ 326 for(idx1=0;idx1<(_tdm_s->_chip_data.soc_pkg.pmap_num_modules); idx1++) { 327 TDM_FREE(_tdm_s->_chip_data.soc_pkg.pmap[idx1]); 328 } 329 TDM_FREE(_tdm_s->_chip_data.soc_pkg.pmap); 330 /* _tdm */ 331 TDM_FREE(_tdm_s); 332 333 return PASS; 334 335 } 336 337 338 /** 339 @name: tdm_chip_td2p_shim__check_pipe_ethernet_alloc 340 @param: 341 */ 342 tdm_mod_t* 343 tdm_chip_td2p_shim__check_pipe_ethernet_alloc( int port, enum port_speed_e speed[TD2P_NUM_EXT_PORTS], int **tsc, int traffic[TD2P_NUM_PM_MOD] ) 344 { 345 int idx1, idx2; 346 tdm_mod_t *_tdm_s; 347 348 _tdm_s = TDM_ALLOC(sizeof(tdm_mod_t),"TDM shim allocation"); 349 if (!_tdm_s) { 350 return NULL; 351 } 352 353 _tdm_s->_chip_data.soc_pkg.speed=TDM_ALLOC(TD2P_NUM_EXT_PORTS*sizeof(enum port_speed_e), "port speed list"); 354 for (idx1=0; idx1<TD2P_NUM_EXT_PORTS; idx1++) { 355 _tdm_s->_chip_data.soc_pkg.speed[idx1] = speed[idx1]; 356 } 357 _tdm_s->_chip_data.soc_pkg.pmap_num_modules = TD2P_NUM_PHY_PM; 358 _tdm_s->_chip_data.soc_pkg.pmap_num_lanes = TD2P_NUM_PM_LNS; 359 _tdm_s->_chip_data.soc_pkg.pmap=(int **) TDM_ALLOC((_tdm_s->_chip_data.soc_pkg.pmap_num_modules)*sizeof(int *), "portmod_map_l1"); 360 for (idx1=0; idx1<(_tdm_s->_chip_data.soc_pkg.pmap_num_modules); idx1++) { 361 _tdm_s->_chip_data.soc_pkg.pmap[idx1]=(int *) TDM_ALLOC((_tdm_s->_chip_data.soc_pkg.pmap_num_lanes)*sizeof(int), "portmod_map_l2"); 362 TDM_MSET(_tdm_s->_chip_data.soc_pkg.pmap[idx1],(_tdm_s->_chip_data.soc_pkg.num_ext_ports),_tdm_s->_chip_data.soc_pkg.pmap_num_lanes); 363 } 364 for (idx1=0; idx1<TD2P_NUM_PHY_PM; idx1++) { 365 for (idx2=0; idx2<TD2P_NUM_PM_LNS; idx2++) { 366 _tdm_s->_chip_data.soc_pkg.pmap[idx1][idx2] = tsc[idx1][idx2]; 367 } 368 } 369 for (idx1=0; idx1<TD2P_NUM_PM_MOD; idx1++) { 370 _tdm_s->_chip_data.soc_pkg.soc_vars.td2p.pm_encap_type[idx1] = traffic[idx1]; 371 } 372 373 _tdm_s->_core_data.vars_pkg.port = port; 374 return _tdm_s; 375 } 376 377 378 /** 379 @name: tdm_chip_td2p_shim__check_pipe_ethernet_free 380 @param: 381 */ 382 int 383 tdm_chip_td2p_shim__check_pipe_ethernet_free(tdm_mod_t *_tdm) 384 { 385 int idx1; 386 tdm_mod_t *_tdm_s=_tdm; 387 /* speed */ 388 TDM_FREE(_tdm_s->_chip_data.soc_pkg.speed); 389 /* pmap */ 390 for(idx1=0;idx1<(_tdm_s->_chip_data.soc_pkg.pmap_num_modules); idx1++) { 391 TDM_FREE(_tdm_s->_chip_data.soc_pkg.pmap[idx1]); 392 } 393 TDM_FREE(_tdm_s->_chip_data.soc_pkg.pmap); 394 /* _tdm */ 395 TDM_FREE(_tdm_s); 396 397 return PASS; 398 399 }