tdm_td2p_main.c (41875B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * $All Rights Reserved.$ 7 * 8 * TDM chip main functions 9 */ 10 #ifdef _TDM_STANDALONE 11 #include <tdm_top.h> 12 #else 13 #include <soc/tdm/core/tdm_top.h> 14 #endif 15 16 /* 17 #ifdef _TDM_DB_STACK 18 size_t stack_size = 0; 19 #endif */ 20 21 /** 22 @name: tdm_td2p_corereq 23 @param: 24 25 Allocate memory for core data execute request to core executive 26 */ 27 int 28 tdm_td2p_corereq( tdm_mod_t *_tdm ) 29 { 30 /* X-Pipe: */ 31 if (_tdm->_core_data.vars_pkg.pipe==TD2P_PIPE_X_ID) { 32 _tdm->_core_data.vars_pkg.cal_id=4; 33 _tdm->_core_exec[TDM_CORE_EXEC__POST]=&tdm_td2p_vbs_wrapper; 34 } 35 /* Y-Pipe: */ 36 else if (_tdm->_core_data.vars_pkg.pipe==TD2P_PIPE_Y_ID) { 37 _tdm->_core_data.vars_pkg.cal_id=5; 38 _tdm->_core_exec[TDM_CORE_EXEC__POST]=&tdm_core_post; 39 } 40 /* unrecognised Pipe number */ 41 else { 42 TDM_ERROR1("Unrecgonized PIPE ID %d \n", _tdm->_core_data.vars_pkg.pipe); 43 return (TDM_EXEC_CORE_SIZE+1); 44 } 45 46 return ( _tdm->_core_exec[TDM_CORE_EXEC__INIT]( _tdm ) ); 47 } 48 49 50 /** 51 @name: tdm_td2p_vbs_wrapper 52 @param: 53 54 Code wrapper for egress TDM scheduling 55 */ 56 int 57 tdm_td2p_vbs_wrapper( tdm_mod_t *_tdm ) 58 { 59 int idx1, idx2, lr_buffer_idx=0, os_buffer_idx=0, 60 pipe, port_exist; 61 int *pgw_tdm_tbl_0, *pgw_tdm_tbl_1, *ovs_tdm_tbl_0, *ovs_tdm_tbl_1; 62 int param_freq, param_lr_limit, param_ancl_num, 63 param_token_empty, param_higig_mgmt; 64 65 /* print stack usage */ 66 /* TDM_PRINT_STACK_SIZE("tdm_td2p_vbs_wrapper"); */ 67 68 param_freq = _tdm->_chip_data.soc_pkg.clk_freq; 69 param_lr_limit = LEN_760MHZ_EN; 70 param_ancl_num = TD2P_ACC_PORT_NUM; 71 param_token_empty = _tdm->_chip_data.soc_pkg.num_ext_ports; 72 param_higig_mgmt = BOOL_FALSE; 73 74 /* accessory slots */ 75 switch (param_freq) { 76 case 608: 77 case 609: 78 param_freq=609; param_ancl_num=TD2P_ACC_PORT_NUM; break; 79 case 517: 80 case 518: 81 param_freq=518; param_ancl_num=(TD2P_ACC_PORT_NUM-2); break; 82 case 416: 83 case 415: 84 param_freq=415; param_ancl_num=TD2P_ACC_PORT_NUM; break; 85 case 760: 86 param_freq=760; param_ancl_num=(TD2P_ACC_PORT_NUM-2); break; 87 default: 88 TDM_ERROR1("Invalid frequency %d MHz\n", param_freq); 89 return 0; 90 } 91 92 switch (_tdm->_core_data.vars_pkg.pipe){ 93 case TD2P_PIPE_X_ID: pipe = 0; tdm_td2p_print_quad(_tdm->_chip_data.soc_pkg.speed,_tdm->_chip_data.soc_pkg.state, TD2P_NUM_PHY_PORTS, 1, 64); break; 94 case TD2P_PIPE_Y_ID: pipe = 1; tdm_td2p_print_quad(_tdm->_chip_data.soc_pkg.speed,_tdm->_chip_data.soc_pkg.state, TD2P_NUM_PHY_PORTS, 65, 128); break; 95 default: 96 TDM_ERROR1("Invalid pipe ID %d \n", _tdm->_core_data.vars_pkg.pipe); 97 return 0; 98 } 99 100 /* lr_buff and os_buff */ 101 if (_tdm->_core_data.vars_pkg.pipe>TD2P_PIPE_X_ID) { 102 pgw_tdm_tbl_0 = _tdm->_chip_data.cal_2.cal_main; 103 pgw_tdm_tbl_1 = _tdm->_chip_data.cal_3.cal_main; 104 ovs_tdm_tbl_0 = _tdm->_chip_data.cal_2.cal_grp[0]; 105 ovs_tdm_tbl_1 = _tdm->_chip_data.cal_3.cal_grp[0]; 106 } 107 else { 108 pgw_tdm_tbl_0 = _tdm->_chip_data.cal_0.cal_main; 109 pgw_tdm_tbl_1 = _tdm->_chip_data.cal_1.cal_main; 110 ovs_tdm_tbl_0 = _tdm->_chip_data.cal_0.cal_grp[0]; 111 ovs_tdm_tbl_1 = _tdm->_chip_data.cal_1.cal_grp[0]; 112 } 113 for (idx1=0; idx1<TDM_AUX_SIZE; idx1++) { 114 _tdm->_core_data.vars_pkg.lr_buffer[idx1]=param_token_empty; 115 _tdm->_core_data.vars_pkg.os_buffer[idx1]=param_token_empty; 116 } 117 for (idx1=0; idx1<TD2P_LR_LLS_LEN; idx1++) { 118 TD2P_TOKEN_CHECK(pgw_tdm_tbl_0[idx1]) { 119 port_exist = BOOL_FALSE; 120 for (idx2=0; idx2<TD2P_LR_LLS_LEN; idx2++){ 121 if (_tdm->_core_data.vars_pkg.lr_buffer[idx2]==pgw_tdm_tbl_0[idx1]){ 122 port_exist = BOOL_TRUE; 123 break; 124 } 125 } 126 if (port_exist==BOOL_FALSE){ 127 if (lr_buffer_idx<TDM_AUX_SIZE){ 128 _tdm->_core_data.vars_pkg.lr_buffer[lr_buffer_idx++]=pgw_tdm_tbl_0[idx1]; 129 } 130 else{ 131 TDM_ERROR4("\n %s, port %3d, buffer_idx %3d, limit %3d\n", 132 "Number of LineRate ports overflow", 133 pgw_tdm_tbl_0[idx1], 134 lr_buffer_idx, 135 (TDM_AUX_SIZE-1)); 136 } 137 } 138 } 139 } 140 for (idx1=0; idx1<TD2P_LR_LLS_LEN; idx1++) { 141 TD2P_TOKEN_CHECK(pgw_tdm_tbl_1[idx1]) { 142 port_exist = BOOL_FALSE; 143 for (idx2=0; idx2<TD2P_LR_LLS_LEN; idx2++){ 144 if (_tdm->_core_data.vars_pkg.lr_buffer[idx2]==pgw_tdm_tbl_1[idx1]){ 145 port_exist = BOOL_TRUE; 146 break; 147 } 148 } 149 if (port_exist==BOOL_FALSE){ 150 if (lr_buffer_idx<TDM_AUX_SIZE){ 151 _tdm->_core_data.vars_pkg.lr_buffer[lr_buffer_idx++]=pgw_tdm_tbl_1[idx1]; 152 } 153 else{ 154 TDM_ERROR4("\n %s, port %3d, buffer_idx %3d, limit %3d\n", 155 "Number of LineRate ports overflow", 156 pgw_tdm_tbl_1[idx1], 157 lr_buffer_idx, 158 (TDM_AUX_SIZE-1)); 159 } 160 } 161 } 162 } 163 for (idx1=0; idx1<TD2P_OS_LLS_GRP_LEN; idx1++) { 164 TD2P_TOKEN_CHECK(ovs_tdm_tbl_0[idx1]) { 165 _tdm->_core_data.vars_pkg.os_buffer[os_buffer_idx++]=ovs_tdm_tbl_0[idx1]; 166 } 167 } 168 for (idx1=0; idx1<TD2P_OS_LLS_GRP_LEN; idx1++) { 169 TD2P_TOKEN_CHECK(ovs_tdm_tbl_1[idx1]) { 170 _tdm->_core_data.vars_pkg.os_buffer[os_buffer_idx++]=ovs_tdm_tbl_1[idx1]; 171 } 172 } 173 174 /* param_higig_mgmt */ 175 if ( (_tdm->_chip_data.soc_pkg.soc_vars.td2p.pm_encap_type[TD2P_NUM_PHY_PM]==PM_ENCAP__HIGIG2 && (pipe==1||pipe==2)) && 176 ((_tdm->_core_data.vars_pkg.lr_buffer[0]!=param_token_empty && param_freq>=MIN_HG_FREQ) || (_tdm->_core_data.vars_pkg.lr_buffer[0]==param_token_empty)) ) { 177 param_higig_mgmt=BOOL_TRUE; 178 } 179 180 /* param_lr_limit: TD2P has same cal_len for both EN and HG */ 181 switch (param_freq) { 182 case 760: param_lr_limit=(LEN_760MHZ_EN-param_ancl_num); break; 183 case 609: param_lr_limit=(LEN_608MHZ_EN-param_ancl_num); break; 184 case 518: param_lr_limit=(LEN_517MHZ_EN-param_ancl_num); break; 185 case 415: param_lr_limit=(LEN_415MHZ_EN-param_ancl_num); break; 186 default : break; 187 } 188 189 /* core parameters */ 190 _tdm->_chip_data.soc_pkg.clk_freq = param_freq; 191 _tdm->_chip_data.soc_pkg.tvec_size = param_ancl_num; 192 _tdm->_chip_data.soc_pkg.lr_idx_limit= param_lr_limit; 193 _tdm->_chip_data.soc_pkg.soc_vars.td2p.higig_mgmt = param_higig_mgmt; 194 195 return ( _tdm->_chip_exec[TDM_CHIP_EXEC__COREREQ]( _tdm ) ); 196 } 197 198 199 /** 200 @name: tdm_td2p_lls_wrapper 201 @param: 202 203 Code wrapper for ingress TDM scheduling 204 */ 205 int 206 tdm_td2p_lls_wrapper( tdm_mod_t *_tdm ) 207 { 208 int idx; 209 int n, pgw_ll_len, pgw_ll_len_max; 210 enum port_speed_e *param_speeds; 211 tdm_chip_legacy_t *_td2p_chip; 212 213 /* print stack usage */ 214 /* TDM_PRINT_STACK_SIZE("tdm_td2p_lls_wrapper"); */ 215 216 param_speeds = _tdm->_chip_data.soc_pkg.speed; 217 218 _td2p_chip = TDM_ALLOC(sizeof(tdm_chip_legacy_t), "TDM chip legacy"); 219 if (!_td2p_chip) {return FAIL;} 220 tdm_chip_td2p_shim__ing_wrap(_tdm, _td2p_chip); 221 222 TDM_PRINT0("TDM: Linked list round robin\n"); 223 for (idx=0; idx<TD2P_NUM_QUAD; idx++) { 224 _tdm->_chip_data.soc_pkg.soc_vars.td2p.pgw_num = idx; 225 _tdm->_chip_data.soc_pkg.soc_vars.td2p.start_port = (idx*(TD2P_NUM_PHY_PORTS/TD2P_NUM_QUAD)); 226 _tdm->_chip_data.soc_pkg.soc_vars.td2p.stop_port = ((idx+1)*(TD2P_NUM_PHY_PORTS/TD2P_NUM_QUAD)); 227 { 228 int i, j, first_wc=0, op_flags_str[2], relink, is_state_changed; 229 struct ll_node llist; 230 td2p_pgw_pntrs_t td2p_pntr_pkg; 231 td2p_pgw_scheduler_vars_t td2p_vars_pkg; 232 int *pgw_tdm_tbl, *ovs_tdm_tbl, *ovs_spacing; 233 234 op_flags_str[0]=0; 235 op_flags_str[1]=0; 236 llist.port=0; 237 llist.next=NULL; 238 td2p_pntr_pkg.pgw_tdm_idx=0; 239 td2p_pntr_pkg.ovs_tdm_idx=0; 240 td2p_pntr_pkg.tdm_stk_idx=0; 241 for (i=0; i<TD2P_OS_LLS_GRP_LEN; i++){ 242 td2p_vars_pkg.swap_array[i] = 0; 243 } 244 245 /* PGW calendars */ 246 switch(_tdm->_chip_data.soc_pkg.soc_vars.td2p.start_port) { 247 case 0: 248 pgw_tdm_tbl = _td2p_chip->tdm_pgw.pgw_tdm_tbl_x0; 249 ovs_tdm_tbl = _td2p_chip->tdm_pgw.ovs_tdm_tbl_x0; 250 ovs_spacing = _td2p_chip->tdm_pgw.ovs_spacing_x0; 251 break; 252 case 32: 253 pgw_tdm_tbl = _td2p_chip->tdm_pgw.pgw_tdm_tbl_x1; 254 ovs_tdm_tbl = _td2p_chip->tdm_pgw.ovs_tdm_tbl_x1; 255 ovs_spacing = _td2p_chip->tdm_pgw.ovs_spacing_x1; 256 break; 257 case 64: 258 pgw_tdm_tbl = _td2p_chip->tdm_pgw.pgw_tdm_tbl_y0; 259 ovs_tdm_tbl = _td2p_chip->tdm_pgw.ovs_tdm_tbl_y0; 260 ovs_spacing = _td2p_chip->tdm_pgw.ovs_spacing_y0; 261 break; 262 default: 263 pgw_tdm_tbl = _td2p_chip->tdm_pgw.pgw_tdm_tbl_y1; 264 ovs_tdm_tbl = _td2p_chip->tdm_pgw.ovs_tdm_tbl_y1; 265 ovs_spacing = _td2p_chip->tdm_pgw.ovs_spacing_y1; 266 break; 267 } 268 269 /* wrap core index */ 270 switch(_tdm->_chip_data.soc_pkg.soc_vars.td2p.pgw_num) { 271 case 0: first_wc = 0; break; 272 case 1: first_wc = 8; break; 273 case 2: first_wc = 16; break; 274 case 3: first_wc = 24; break; 275 } 276 /* port number range */ 277 td2p_vars_pkg.first_port=_tdm->_chip_data.soc_pkg.soc_vars.td2p.start_port; 278 td2p_vars_pkg.last_port =_tdm->_chip_data.soc_pkg.soc_vars.td2p.stop_port; 279 /* linked-list, and PGW oversub calendar */ 280 for (j=0; j<4; j++) { 281 td2p_vars_pkg.subport=j; 282 td2p_pntr_pkg.cur_idx=first_wc; 283 td2p_vars_pkg.cur_idx_max=(first_wc+8); 284 tdm_td2p_lls_scheduler(&llist, _td2p_chip, &td2p_pntr_pkg, &td2p_vars_pkg, &pgw_tdm_tbl, &ovs_tdm_tbl, op_flags_str); 285 } 286 /* single 20G mode */ 287 switch(_tdm->_chip_data.soc_pkg.clk_freq){ 288 case 415: 289 case 416: 290 pgw_ll_len_max = 12; 291 break; 292 case 517: 293 case 518: 294 pgw_ll_len_max = 16; 295 break; 296 case 608: 297 case 609: 298 if (td2p_vars_pkg.first_port==32 || 299 td2p_vars_pkg.first_port==64){ 300 pgw_ll_len_max = 20; 301 } 302 else { 303 pgw_ll_len_max = 16; 304 } 305 break; 306 case 760: 307 pgw_ll_len_max = 24; 308 break; 309 default: 310 pgw_ll_len_max = 32; 311 TDM_ERROR1("TDM: unrecognized frequency %d in PGW\n", 312 _tdm->_chip_data.soc_pkg.clk_freq); 313 break; 314 } 315 pgw_ll_len = tdm_td2p_ll_len(&llist); 316 if (pgw_ll_len>pgw_ll_len_max){ 317 TDM_PRINT2("TDM: Adjust PGW linked list, len %d, limit %d\n", 318 pgw_ll_len, pgw_ll_len_max); 319 n = pgw_ll_len - pgw_ll_len_max; 320 for (i=(pgw_ll_len-1); i>0; i--){ 321 if (tdm_td2p_ll_get(&llist,i)==TD2P_OVSB_TOKEN){ 322 tdm_td2p_ll_delete(&llist, i); 323 n--; 324 TDM_PRINT2("%s, index %d\n", 325 "remove OVSB slot from PGW linked list", 326 i); 327 } 328 if (n<=0){ 329 break; 330 } 331 } 332 } 333 td2p_pntr_pkg.pgw_tdm_idx=tdm_td2p_ll_len(&llist); 334 /* same-port-min-spacing */ 335 relink=BOOL_FALSE; 336 for (i=1; i<tdm_td2p_ll_len(&llist); i++) { 337 TD2P_TOKEN_CHECK(tdm_td2p_ll_get(&llist,i)) { 338 if ( tdm_td2p_scan_which_tsc(tdm_td2p_ll_get(&llist,i),_td2p_chip->pmap)==tdm_td2p_scan_which_tsc(tdm_td2p_ll_get(&llist,(i-1)),_td2p_chip->pmap) ) { 339 relink=BOOL_TRUE; 340 break; 341 } 342 } 343 } 344 if (relink) { 345 TDM_PRINT0("TDM: Retracing calendar\n"); 346 tdm_td2p_ll_retrace(&llist,_td2p_chip->pmap); 347 tdm_td2p_ll_print(&llist); 348 } 349 /* same-port-min-spacing */ 350 relink=BOOL_FALSE; 351 for (i=1; i<tdm_td2p_ll_len(&llist); i++) { 352 TD2P_TOKEN_CHECK(tdm_td2p_ll_get(&llist,i)) { 353 if ( tdm_td2p_scan_which_tsc(tdm_td2p_ll_get(&llist,i),_td2p_chip->pmap)==tdm_td2p_scan_which_tsc(tdm_td2p_ll_get(&llist,(i-1)),_td2p_chip->pmap) ) { 354 relink=BOOL_TRUE; 355 break; 356 } 357 } 358 } 359 if (relink) { 360 TDM_PRINT0("TDM: Reweaving calendar\n"); 361 tdm_td2p_ll_weave(&llist,_td2p_chip->pmap,TD2P_OVSB_TOKEN); 362 tdm_td2p_ll_print(&llist); 363 } 364 else if ( (tdm_td2p_ll_count(&llist,1)>0 && tdm_td2p_ll_count(&llist,TD2P_OVSB_TOKEN)>1) || (tdm_td2p_ll_single_100(&llist)) ) { 365 TDM_PRINT0("TDM: Reweaving calendar\n"); 366 tdm_td2p_ll_weave(&llist,_td2p_chip->pmap,TD2P_OVSB_TOKEN); 367 tdm_td2p_ll_print(&llist); 368 } 369 /* PGW main calendar */ 370 tdm_td2p_ll_deref(&llist,&pgw_tdm_tbl,TD2P_LR_LLS_LEN); 371 /* PGW oversub spacer calendar */ 372 TDM_SML_BAR 373 tdm_td2p_print_tbl(pgw_tdm_tbl,TD2P_LR_LLS_LEN,"PGW Main Calendar",idx); 374 if (ovs_tdm_tbl[0]!=TD2P_NUM_EXT_PORTS) { 375 tdm_td2p_ovs_spacer(&_td2p_chip->pmap,ovs_tdm_tbl,ovs_spacing, param_speeds); 376 /* tdm_td2p_print_tbl_ovs(ovs_tdm_tbl,ovs_spacing,TD2P_OS_LLS_GRP_LEN,"PGW Oversub Calendar",idx); */ 377 378 is_state_changed = BOOL_FALSE; 379 for (i=0; i<TD2P_OS_LLS_GRP_LEN; i++) { 380 if ( (ovs_tdm_tbl[i]!=TD2P_NUM_EXT_PORTS) && 381 (_tdm->_chip_data.soc_pkg.state[ovs_tdm_tbl[i]]==PORT_STATE__LINERATE || _tdm->_chip_data.soc_pkg.state[ovs_tdm_tbl[i]]==PORT_STATE__LINERATE_HG) ){ 382 switch(_tdm->_chip_data.soc_pkg.state[ovs_tdm_tbl[i]]){ 383 case PORT_STATE__LINERATE: 384 _tdm->_chip_data.soc_pkg.state[ovs_tdm_tbl[i]]=PORT_STATE__OVERSUB; 385 is_state_changed = BOOL_TRUE; 386 break; 387 case PORT_STATE__LINERATE_HG: 388 _tdm->_chip_data.soc_pkg.state[ovs_tdm_tbl[i]]=PORT_STATE__OVERSUB_HG; 389 is_state_changed = BOOL_TRUE; 390 break; 391 default: 392 break; 393 } 394 TDM_PRINT1("TDM: Port [%3d] state changes from LINERATE to OVERSUB\n", ovs_tdm_tbl[i]); 395 } 396 } 397 if(is_state_changed==BOOL_TRUE) {tdm_print_stat( _tdm );} 398 } 399 400 /* regenerate PGW oversub calendar and spacing calendar under flexport restriction */ 401 tdm_td2p_proc_pgw_os_cal(_td2p_chip, &td2p_vars_pkg, ovs_tdm_tbl, ovs_spacing); 402 tdm_td2p_print_tbl_ovs(ovs_tdm_tbl,ovs_spacing,TD2P_OS_LLS_GRP_LEN,"PGW Oversub Calendar",idx); 403 404 tdm_td2p_ll_free(&llist); 405 } 406 } 407 408 /* Bind to TDM class object */ 409 TDM_COPY(_tdm->_chip_data.cal_0.cal_main,_td2p_chip->tdm_pgw.pgw_tdm_tbl_x0,sizeof(int)*TD2P_LR_LLS_LEN); 410 TDM_COPY(_tdm->_chip_data.cal_0.cal_grp[0],_td2p_chip->tdm_pgw.ovs_tdm_tbl_x0,sizeof(int)*TD2P_OS_LLS_GRP_LEN); 411 TDM_COPY(_tdm->_chip_data.cal_0.cal_grp[1],_td2p_chip->tdm_pgw.ovs_spacing_x0,sizeof(int)*TD2P_OS_LLS_GRP_LEN); 412 TDM_COPY(_tdm->_chip_data.cal_1.cal_main,_td2p_chip->tdm_pgw.pgw_tdm_tbl_x1,sizeof(int)*TD2P_LR_LLS_LEN); 413 TDM_COPY(_tdm->_chip_data.cal_1.cal_grp[0],_td2p_chip->tdm_pgw.ovs_tdm_tbl_x1,sizeof(int)*TD2P_OS_LLS_GRP_LEN); 414 TDM_COPY(_tdm->_chip_data.cal_1.cal_grp[1],_td2p_chip->tdm_pgw.ovs_spacing_x1,sizeof(int)*TD2P_OS_LLS_GRP_LEN); 415 TDM_COPY(_tdm->_chip_data.cal_2.cal_main,_td2p_chip->tdm_pgw.pgw_tdm_tbl_y0,sizeof(int)*TD2P_LR_LLS_LEN); 416 TDM_COPY(_tdm->_chip_data.cal_2.cal_grp[0],_td2p_chip->tdm_pgw.ovs_tdm_tbl_y0,sizeof(int)*TD2P_OS_LLS_GRP_LEN); 417 TDM_COPY(_tdm->_chip_data.cal_2.cal_grp[1],_td2p_chip->tdm_pgw.ovs_spacing_y0,sizeof(int)*TD2P_OS_LLS_GRP_LEN); 418 TDM_COPY(_tdm->_chip_data.cal_3.cal_main,_td2p_chip->tdm_pgw.pgw_tdm_tbl_y1,sizeof(int)*TD2P_LR_LLS_LEN); 419 TDM_COPY(_tdm->_chip_data.cal_3.cal_grp[0],_td2p_chip->tdm_pgw.ovs_tdm_tbl_y1,sizeof(int)*TD2P_OS_LLS_GRP_LEN); 420 TDM_COPY(_tdm->_chip_data.cal_3.cal_grp[1],_td2p_chip->tdm_pgw.ovs_spacing_y1,sizeof(int)*TD2P_OS_LLS_GRP_LEN); 421 422 /* Realign port state array to old specification */ 423 for (idx=0; idx<((_tdm->_chip_data.soc_pkg.num_ext_ports)-1); idx++) { 424 _tdm->_chip_data.soc_pkg.state[idx] = _tdm->_chip_data.soc_pkg.state[idx+1]; 425 } 426 427 _tdm->_core_data.vars_pkg.pipe=TD2P_PIPE_X_ID; 428 TDM_FREE(_td2p_chip); 429 430 return ( _tdm->_chip_exec[TDM_CHIP_EXEC__EGRESS_WRAP]( _tdm ) ); 431 } 432 433 434 /** 435 @name: tdm_td2p_pmap_transcription_unsupported_quad_mode 436 @param: 437 438 Convert any unsupported quad mode to regular quad mode. 439 */ 440 static int 441 tdm_td2p_pmap_transcription_unsupported_quad_mode( tdm_mod_t *_tdm ) 442 { 443 int pm_num, lane_num, port, port_speed, 444 pm_speed_max, pm_speed_min, pm_port_cnt, pm_port_lo; 445 int param_phy_pms, param_pm_lanes; 446 447 param_phy_pms = _tdm->_chip_data.soc_pkg.pm_num_phy_modules; 448 param_pm_lanes = _tdm->_chip_data.soc_pkg.pmap_num_lanes; 449 450 for (pm_num = 0; pm_num < param_phy_pms; pm_num++) { 451 pm_port_cnt = 0; 452 pm_speed_max = 0; 453 pm_speed_min = SPEED_100G; 454 pm_port_lo = pm_num * param_pm_lanes + 1; 455 for (lane_num = 0; lane_num < param_pm_lanes; lane_num++) { 456 port = pm_port_lo + lane_num; 457 port_speed = _tdm->_chip_data.soc_pkg.speed[port]; 458 if (port_speed > 0) { 459 pm_port_cnt++; 460 pm_speed_min = (pm_speed_min > port_speed) ? port_speed : 461 pm_speed_min; 462 pm_speed_max = (pm_speed_max < port_speed) ? port_speed : 463 pm_speed_max; 464 } 465 } 466 /* force to quad mode */ 467 if (pm_port_cnt == 4 && pm_speed_min != pm_speed_max) { 468 for (lane_num = 0; lane_num < param_pm_lanes; lane_num++) { 469 port = pm_port_lo + lane_num; 470 port_speed = _tdm->_chip_data.soc_pkg.speed[port]; 471 if (port_speed != pm_speed_max) { 472 _tdm->_chip_data.soc_pkg.speed[port] = pm_speed_max; 473 TDM_PRINT5("%s, convert PM %0d port %0d from %0dG to %0dG\n", 474 "TDM: [unsupported PM Quad Mode]", 475 pm_num, port, port_speed/1000, pm_speed_max/1000); 476 } 477 } 478 } 479 } 480 481 return PASS; 482 } 483 484 485 /** 486 @name: tdm_td2p_pmap_transcription 487 @param: 488 489 For Trident2+ BCM56850 490 Transcription algorithm for generating port module mapping 491 492 40G - xxxx 493 20G - xx 494 xx 495 10G - x 496 x 497 x 498 x 499 1X0G - xxxx_xxxx_xxxx 500 */ 501 int 502 tdm_td2p_pmap_transcription( tdm_mod_t *_tdm ) 503 { 504 int i, j, last_port=TD2P_NUM_EXT_PORTS, tsc_active; 505 int phy_lo, phy_hi, pm_lane_num, bcm_config_check=PASS; 506 int p, spd_1g_en, spd_10g_plus_en; 507 508 /* Management ports */ 509 if( (_tdm->_chip_data.soc_pkg.state[TD2P_MGMT_PORT_0]==PORT_STATE__MANAGEMENT) || 510 (_tdm->_chip_data.soc_pkg.state[TD2P_MGMT_PORT_1]==PORT_STATE__MANAGEMENT) || 511 (_tdm->_chip_data.soc_pkg.state[TD2P_MGMT_PORT_2]==PORT_STATE__MANAGEMENT) || 512 (_tdm->_chip_data.soc_pkg.state[TD2P_MGMT_PORT_3]==PORT_STATE__MANAGEMENT) ){ 513 if( (((TD2P_MGMT_PORT_0-1)/TD2P_NUM_PM_LNS)==TD2P_MGMT_TSC_ID) && 514 (((TD2P_MGMT_PORT_1-1)/TD2P_NUM_PM_LNS)==TD2P_MGMT_TSC_ID) && 515 (((TD2P_MGMT_PORT_2-1)/TD2P_NUM_PM_LNS)==TD2P_MGMT_TSC_ID) && 516 (((TD2P_MGMT_PORT_3-1)/TD2P_NUM_PM_LNS)==TD2P_MGMT_TSC_ID) ){ 517 _tdm->_chip_data.soc_pkg.pmap[TD2P_MGMT_TSC_ID][0] = ((_tdm->_chip_data.soc_pkg.state[TD2P_MGMT_PORT_0]==PORT_STATE__MANAGEMENT) ? (TD2P_MGMT_TOKEN): (TD2P_NUM_EXT_PORTS) ); 518 _tdm->_chip_data.soc_pkg.pmap[TD2P_MGMT_TSC_ID][1] = ((_tdm->_chip_data.soc_pkg.state[TD2P_MGMT_PORT_1]==PORT_STATE__MANAGEMENT) ? (TD2P_MGMT_TOKEN): (TD2P_NUM_EXT_PORTS) ); 519 _tdm->_chip_data.soc_pkg.pmap[TD2P_MGMT_TSC_ID][2] = ((_tdm->_chip_data.soc_pkg.state[TD2P_MGMT_PORT_2]==PORT_STATE__MANAGEMENT) ? (TD2P_MGMT_TOKEN): (TD2P_NUM_EXT_PORTS) ); 520 _tdm->_chip_data.soc_pkg.pmap[TD2P_MGMT_TSC_ID][3] = ((_tdm->_chip_data.soc_pkg.state[TD2P_MGMT_PORT_3]==PORT_STATE__MANAGEMENT) ? (TD2P_MGMT_TOKEN): (TD2P_NUM_EXT_PORTS) ); 521 } 522 else{ 523 TDM_ERROR0("Unmatched MANAGEMENT port numbering config between physical port number and TSC index. \n"); 524 } 525 } 526 527 /* regulate unsupported PM quad modes */ 528 tdm_td2p_pmap_transcription_unsupported_quad_mode(_tdm); 529 530 /* Regular ports */ 531 for (i=1; i<=TD2P_NUM_PHY_PORTS; i+=TD2P_NUM_PM_LNS) { 532 tsc_active=BOOL_FALSE; 533 for (j=0; j<TD2P_NUM_PM_LNS; j++) { 534 if ( _tdm->_chip_data.soc_pkg.state[i+j]==PORT_STATE__LINERATE || _tdm->_chip_data.soc_pkg.state[i+j]==PORT_STATE__OVERSUB || 535 _tdm->_chip_data.soc_pkg.state[i+j]==PORT_STATE__LINERATE_HG || _tdm->_chip_data.soc_pkg.state[i+j]==PORT_STATE__OVERSUB_HG ){ 536 tsc_active=BOOL_TRUE; 537 break; 538 } 539 } 540 if(tsc_active==BOOL_TRUE){ 541 if ( _tdm->_chip_data.soc_pkg.speed[i]<=SPEED_42G_HG2 || _tdm->_chip_data.soc_pkg.state[i]==PORT_STATE__DISABLED ) { 542 for (j=0; j<TD2P_NUM_PM_LNS; j++) { 543 switch (_tdm->_chip_data.soc_pkg.state[i+j]) { 544 case PORT_STATE__LINERATE: 545 case PORT_STATE__OVERSUB: 546 case PORT_STATE__LINERATE_HG: 547 case PORT_STATE__OVERSUB_HG: 548 _tdm->_chip_data.soc_pkg.pmap[(i-1)/TD2P_NUM_PM_LNS][j]=(i+j); 549 last_port=(i+j); 550 break; 551 case PORT_STATE__COMBINE: 552 _tdm->_chip_data.soc_pkg.pmap[(i-1)/TD2P_NUM_PM_LNS][j]=last_port; 553 break; 554 default: 555 _tdm->_chip_data.soc_pkg.pmap[(i-1)/TD2P_NUM_PM_LNS][j]=TD2P_NUM_EXT_PORTS; 556 break; 557 } 558 } 559 /* tri mode x_xx */ 560 if (_tdm->_chip_data.soc_pkg.speed[i]>_tdm->_chip_data.soc_pkg.speed[i+2] && 561 _tdm->_chip_data.soc_pkg.speed[i+2]==_tdm->_chip_data.soc_pkg.speed[i+3] && 562 _tdm->_chip_data.soc_pkg.speed[i+2]!=SPEED_0 && 563 _tdm->_chip_data.soc_pkg.speed[i+2]==SPEED_0) { 564 _tdm->_chip_data.soc_pkg.pmap[(i-1)/TD2P_NUM_PM_LNS][1] = _tdm->_chip_data.soc_pkg.pmap[(i-1)/TD2P_NUM_PM_LNS][2]; 565 _tdm->_chip_data.soc_pkg.pmap[(i-1)/TD2P_NUM_PM_LNS][2] = _tdm->_chip_data.soc_pkg.pmap[(i-1)/TD2P_NUM_PM_LNS][0]; 566 } 567 /* tri mode xxx_ */ 568 else if (_tdm->_chip_data.soc_pkg.speed[i]==_tdm->_chip_data.soc_pkg.speed[i+1] && 569 _tdm->_chip_data.soc_pkg.speed[i]<_tdm->_chip_data.soc_pkg.speed[i+2] && 570 _tdm->_chip_data.soc_pkg.speed[i]!=SPEED_0 && 571 _tdm->_chip_data.soc_pkg.speed[i+3]!=SPEED_0) { 572 _tdm->_chip_data.soc_pkg.pmap[(i-1)/TD2P_NUM_PM_LNS][2] = _tdm->_chip_data.soc_pkg.pmap[(i-1)/TD2P_NUM_PM_LNS][1]; 573 _tdm->_chip_data.soc_pkg.pmap[(i-1)/TD2P_NUM_PM_LNS][1] = _tdm->_chip_data.soc_pkg.pmap[(i-1)/TD2P_NUM_PM_LNS][3]; 574 } 575 /* dual mode x_x_ */ 576 else if (_tdm->_chip_data.soc_pkg.speed[i]>SPEED_0 && 577 _tdm->_chip_data.soc_pkg.speed[i]==_tdm->_chip_data.soc_pkg.speed[i+2] && 578 _tdm->_chip_data.soc_pkg.speed[i+1]==SPEED_0 && 579 _tdm->_chip_data.soc_pkg.speed[i+3]==SPEED_0) { 580 if ( _tdm->_chip_data.soc_pkg.state[i]==PORT_STATE__COMBINE && _tdm->_chip_data.soc_pkg.state[i+2]==PORT_STATE__COMBINE ) { 581 _tdm->_chip_data.soc_pkg.pmap[(i-1)/TD2P_NUM_PM_LNS][1] = _tdm->_chip_data.soc_pkg.pmap[(i-1)/TD2P_NUM_PM_LNS][3]; 582 _tdm->_chip_data.soc_pkg.pmap[(i-1)/TD2P_NUM_PM_LNS][2] = _tdm->_chip_data.soc_pkg.pmap[(i-1)/TD2P_NUM_PM_LNS][0]; 583 } 584 } 585 } 586 else { 587 if ( (_tdm->_chip_data.soc_pkg.speed[i]==SPEED_100G || 588 _tdm->_chip_data.soc_pkg.speed[i]==SPEED_106G ) && 589 (_tdm->_chip_data.soc_pkg.state[i+10]!=PORT_STATE__COMBINE) ){ 590 _tdm->_chip_data.soc_pkg.pmap[(i-1)/TD2P_NUM_PM_LNS][0] = i; 591 _tdm->_chip_data.soc_pkg.pmap[(i-1)/TD2P_NUM_PM_LNS][1] = i; 592 _tdm->_chip_data.soc_pkg.pmap[(i-1)/TD2P_NUM_PM_LNS][2] = i; 593 _tdm->_chip_data.soc_pkg.pmap[(i-1)/TD2P_NUM_PM_LNS][3] = i; 594 _tdm->_chip_data.soc_pkg.pmap[(i+3)/TD2P_NUM_PM_LNS][0] = i; 595 _tdm->_chip_data.soc_pkg.pmap[(i+3)/TD2P_NUM_PM_LNS][1] = i; 596 _tdm->_chip_data.soc_pkg.pmap[(i+3)/TD2P_NUM_PM_LNS][2] = i; 597 _tdm->_chip_data.soc_pkg.pmap[(i+3)/TD2P_NUM_PM_LNS][3] = i; 598 _tdm->_chip_data.soc_pkg.pmap[(i+7)/TD2P_NUM_PM_LNS][0] = i; 599 _tdm->_chip_data.soc_pkg.pmap[(i+7)/TD2P_NUM_PM_LNS][1] = i; 600 _tdm->_chip_data.soc_pkg.pmap[(i+7)/TD2P_NUM_PM_LNS][2] = TD2P_NUM_EXT_PORTS; 601 _tdm->_chip_data.soc_pkg.pmap[(i+7)/TD2P_NUM_PM_LNS][3] = TD2P_NUM_EXT_PORTS; 602 } 603 else if ( _tdm->_chip_data.soc_pkg.speed[i]==SPEED_100G || 604 _tdm->_chip_data.soc_pkg.speed[i]==SPEED_106G || 605 _tdm->_chip_data.soc_pkg.speed[i]==SPEED_120G || 606 _tdm->_chip_data.soc_pkg.speed[i]==SPEED_127G ){ 607 _tdm->_chip_data.soc_pkg.pmap[(i-1)/TD2P_NUM_PM_LNS][0] = i; 608 _tdm->_chip_data.soc_pkg.pmap[(i-1)/TD2P_NUM_PM_LNS][1] = i; 609 _tdm->_chip_data.soc_pkg.pmap[(i-1)/TD2P_NUM_PM_LNS][2] = i; 610 _tdm->_chip_data.soc_pkg.pmap[(i-1)/TD2P_NUM_PM_LNS][3] = i; 611 _tdm->_chip_data.soc_pkg.pmap[(i+3)/TD2P_NUM_PM_LNS][0] = i; 612 _tdm->_chip_data.soc_pkg.pmap[(i+3)/TD2P_NUM_PM_LNS][1] = i; 613 _tdm->_chip_data.soc_pkg.pmap[(i+3)/TD2P_NUM_PM_LNS][2] = i; 614 _tdm->_chip_data.soc_pkg.pmap[(i+3)/TD2P_NUM_PM_LNS][3] = i; 615 _tdm->_chip_data.soc_pkg.pmap[(i+7)/TD2P_NUM_PM_LNS][0] = i; 616 _tdm->_chip_data.soc_pkg.pmap[(i+7)/TD2P_NUM_PM_LNS][1] = i; 617 _tdm->_chip_data.soc_pkg.pmap[(i+7)/TD2P_NUM_PM_LNS][2] = i; 618 _tdm->_chip_data.soc_pkg.pmap[(i+7)/TD2P_NUM_PM_LNS][3] = i; 619 } 620 i+=8; 621 } 622 } 623 } 624 tdm_print_stat( _tdm ); 625 /* Management port bandwidth */ 626 _tdm->_chip_data.soc_pkg.soc_vars.td2p.mgmtbw=0; 627 for (i=0; i<TD2P_NUM_PM_LNS; i++) { 628 if (_tdm->_chip_data.soc_pkg.pmap[TD2P_MGMT_TSC_ID][i]==TD2P_MGMT_TOKEN) { 629 ((_tdm->_chip_data.soc_pkg.soc_vars.td2p.mgmtbw)++); 630 } 631 } 632 633 /* Check if invalid port config exists */ 634 phy_lo = _tdm->_chip_data.soc_pkg.soc_vars.fp_port_lo; 635 phy_hi = _tdm->_chip_data.soc_pkg.soc_vars.fp_port_hi; 636 pm_lane_num= _tdm->_chip_data.soc_pkg.pmap_num_lanes; 637 for (i=phy_lo; i<=(phy_hi-pm_lane_num); i+=pm_lane_num) { 638 if (_tdm->_chip_data.soc_pkg.speed[i]==SPEED_0){ 639 for (j=1; j<pm_lane_num; j++) { 640 if (_tdm->_chip_data.soc_pkg.speed[i+j]>SPEED_0){ 641 bcm_config_check = FAIL; 642 break; 643 } 644 } 645 } 646 if (bcm_config_check==FAIL){ 647 TDM_ERROR8("Invalid port configuration, port [%3d, %3d, %3d, %3d], speed [%3dG, %3dG, %3dG, %3dG]\n", 648 i, i+1, i+2, i+3, 649 _tdm->_chip_data.soc_pkg.speed[i]/1000, 650 _tdm->_chip_data.soc_pkg.speed[i+1]/1000, 651 _tdm->_chip_data.soc_pkg.speed[i+2]/1000, 652 _tdm->_chip_data.soc_pkg.speed[i+3]/1000); 653 return FAIL; 654 } 655 } 656 657 /* 13G/16G support 658 * -- 13G/16G will be taken as 21G. 659 * -- 13G/16G only support 4-lane mode, i.e. [x, 0, 0, 0] 660 */ 661 for (i=1; i<=TD2P_NUM_PHY_PORTS; i+=TD2P_NUM_PM_LNS) { 662 /* convert speed */ 663 if (_tdm->_chip_data.soc_pkg.speed[i]==SPEED_13G || 664 _tdm->_chip_data.soc_pkg.speed[i]==SPEED_16G) { 665 _tdm->_chip_data.soc_pkg.speed[i] = SPEED_21G; 666 } 667 /* check TSC mode */ 668 for (j=1; j<TD2P_NUM_PM_LNS; j++) { 669 if (_tdm->_chip_data.soc_pkg.speed[i+j]==SPEED_13G || 670 _tdm->_chip_data.soc_pkg.speed[i+j]==SPEED_16G) { 671 TDM_ERROR1("Invalid port configuration, %s\n", 672 "13G/16G port must be 4-lane mode"); 673 return FAIL; 674 } 675 } 676 } 677 678 /* 1G/2.5G support: 679 * -- only apply on linerate PM config 680 * -- if 1G/2.5G is mixed with 10G in one PM, convert 1G/2.5G to 10G. 681 */ 682 for (i=1; i<=(phy_hi-pm_lane_num); i+=pm_lane_num) { 683 spd_1g_en = 0; 684 spd_10g_plus_en = 0; 685 for (j=0; j<pm_lane_num; j++) { 686 p = i + j; 687 if (_tdm->_chip_data.soc_pkg.state[p-1]==PORT_STATE__LINERATE) { 688 if (_tdm->_chip_data.soc_pkg.speed[p]==SPEED_1G || 689 _tdm->_chip_data.soc_pkg.speed[p]==SPEED_2p5G) { 690 spd_1g_en = 1; 691 } else if (_tdm->_chip_data.soc_pkg.speed[p]>=SPEED_10G) { 692 spd_10g_plus_en = 1; 693 } 694 } 695 } 696 if (spd_1g_en && spd_10g_plus_en) { 697 for (j=0; j<pm_lane_num; j++) { 698 p = i + j; 699 if ((_tdm->_chip_data.soc_pkg.state[p-1]==PORT_STATE__LINERATE) && 700 (_tdm->_chip_data.soc_pkg.speed[p]==SPEED_1G || 701 _tdm->_chip_data.soc_pkg.speed[p]==SPEED_2p5G)) { 702 TDM_PRINT3("%s port %3d, convert speed from %0dG to 10G\n", 703 "TDM: [1G CONFIG]", 704 p, _tdm->_chip_data.soc_pkg.speed[p]/1000); 705 _tdm->_chip_data.soc_pkg.speed[p] = SPEED_10G; 706 } 707 } 708 } 709 } 710 711 return ( _tdm->_chip_exec[TDM_CHIP_EXEC__INGRESS_WRAP]( _tdm ) ); 712 } 713 714 715 /** 716 @name: tdm_chip_td2p_init 717 @param: 718 */ 719 int 720 tdm_td2p_init( tdm_mod_t *_tdm ) 721 { 722 int index; 723 /* 724 #ifdef _TDM_DB_STACK 725 stack_size = (size_t)&index; 726 #endif */ 727 728 /* Chip: parameters */ 729 _tdm->_chip_data.soc_pkg.pmap_num_modules = TD2P_NUM_PM_MOD; 730 _tdm->_chip_data.soc_pkg.pmap_num_lanes = TD2P_NUM_PM_LNS; 731 _tdm->_chip_data.soc_pkg.pm_num_phy_modules = TD2P_NUM_PHY_PM; 732 733 _tdm->_chip_data.soc_pkg.soc_vars.ovsb_token = TD2P_OVSB_TOKEN; 734 _tdm->_chip_data.soc_pkg.soc_vars.idl1_token = TD2P_IDL1_TOKEN; 735 _tdm->_chip_data.soc_pkg.soc_vars.idl2_token = TD2P_IDL2_TOKEN; 736 _tdm->_chip_data.soc_pkg.soc_vars.ancl_token = TD2P_ANCL_TOKEN; 737 _tdm->_chip_data.soc_pkg.soc_vars.fp_port_lo = 1; 738 _tdm->_chip_data.soc_pkg.soc_vars.fp_port_hi = TD2P_NUM_PHY_PORTS; 739 740 _tdm->_chip_data.cal_0.cal_len = TD2P_LR_LLS_LEN; 741 _tdm->_chip_data.cal_0.grp_num = TD2P_OS_LLS_GRP_NUM; 742 _tdm->_chip_data.cal_0.grp_len = TD2P_OS_LLS_GRP_LEN; 743 _tdm->_chip_data.cal_1.cal_len = TD2P_LR_LLS_LEN; 744 _tdm->_chip_data.cal_1.grp_num = TD2P_OS_LLS_GRP_NUM; 745 _tdm->_chip_data.cal_1.grp_len = TD2P_OS_LLS_GRP_LEN; 746 _tdm->_chip_data.cal_2.cal_len = TD2P_LR_LLS_LEN; 747 _tdm->_chip_data.cal_2.grp_num = TD2P_OS_LLS_GRP_NUM; 748 _tdm->_chip_data.cal_2.grp_len = TD2P_OS_LLS_GRP_LEN; 749 _tdm->_chip_data.cal_3.cal_len = TD2P_LR_LLS_LEN; 750 _tdm->_chip_data.cal_3.grp_num = TD2P_OS_LLS_GRP_NUM; 751 _tdm->_chip_data.cal_3.grp_len = TD2P_OS_LLS_GRP_LEN; 752 _tdm->_chip_data.cal_4.cal_len = TD2P_LR_VBS_LEN; 753 _tdm->_chip_data.cal_4.grp_num = TD2P_OS_VBS_GRP_NUM; 754 _tdm->_chip_data.cal_4.grp_len = TD2P_OS_VBS_GRP_LEN; 755 _tdm->_chip_data.cal_5.cal_len = TD2P_LR_VBS_LEN; 756 _tdm->_chip_data.cal_5.grp_num = TD2P_OS_VBS_GRP_NUM; 757 _tdm->_chip_data.cal_5.grp_len = TD2P_OS_VBS_GRP_LEN; 758 _tdm->_chip_data.cal_6.cal_len = TD2P_LR_IARB_STATIC_LEN; 759 _tdm->_chip_data.cal_6.grp_num = 0; 760 _tdm->_chip_data.cal_6.grp_len = 0; 761 _tdm->_chip_data.cal_7.cal_len = TD2P_LR_IARB_STATIC_LEN; 762 _tdm->_chip_data.cal_7.grp_num = 0; 763 _tdm->_chip_data.cal_7.grp_len = 0; 764 765 /* Chip: management port state */ 766 if (_tdm->_chip_data.soc_pkg.soc_vars.td2p.tdm_mgmt_en!=BOOL_FALSE){ 767 /* 10_0_0_0 */ 768 if (_tdm->_chip_data.soc_pkg.speed[TD2P_MGMT_PORT_0]==SPEED_10G && 769 _tdm->_chip_data.soc_pkg.speed[TD2P_MGMT_PORT_1]==SPEED_0 && 770 _tdm->_chip_data.soc_pkg.speed[TD2P_MGMT_PORT_2]==SPEED_0 && 771 _tdm->_chip_data.soc_pkg.speed[TD2P_MGMT_PORT_3]==SPEED_0){ 772 _tdm->_chip_data.soc_pkg.state[TD2P_MGMT_PORT_0] = PORT_STATE__MANAGEMENT; 773 _tdm->_chip_data.soc_pkg.state[TD2P_MGMT_PORT_1] = PORT_STATE__DISABLED; 774 _tdm->_chip_data.soc_pkg.state[TD2P_MGMT_PORT_2] = PORT_STATE__DISABLED; 775 _tdm->_chip_data.soc_pkg.state[TD2P_MGMT_PORT_3] = PORT_STATE__DISABLED; 776 } 777 /* x_x_x_x*/ 778 else if (_tdm->_chip_data.soc_pkg.speed[TD2P_MGMT_PORT_0]<SPEED_10G && 779 _tdm->_chip_data.soc_pkg.speed[TD2P_MGMT_PORT_0]>SPEED_0 && 780 _tdm->_chip_data.soc_pkg.speed[TD2P_MGMT_PORT_0]==_tdm->_chip_data.soc_pkg.speed[TD2P_MGMT_PORT_1] && 781 _tdm->_chip_data.soc_pkg.speed[TD2P_MGMT_PORT_1]==_tdm->_chip_data.soc_pkg.speed[TD2P_MGMT_PORT_2] && 782 _tdm->_chip_data.soc_pkg.speed[TD2P_MGMT_PORT_2]==_tdm->_chip_data.soc_pkg.speed[TD2P_MGMT_PORT_3] ){ 783 _tdm->_chip_data.soc_pkg.state[TD2P_MGMT_PORT_0] = PORT_STATE__MANAGEMENT; 784 _tdm->_chip_data.soc_pkg.state[TD2P_MGMT_PORT_1] = PORT_STATE__MANAGEMENT; 785 _tdm->_chip_data.soc_pkg.state[TD2P_MGMT_PORT_2] = PORT_STATE__MANAGEMENT; 786 _tdm->_chip_data.soc_pkg.state[TD2P_MGMT_PORT_3] = PORT_STATE__MANAGEMENT; 787 } 788 } 789 /* Chip: encap */ 790 for (index=0; index<TD2P_NUM_PM_MOD; index++) { 791 _tdm->_chip_data.soc_pkg.soc_vars.td2p.pm_encap_type[index] = (_tdm->_chip_data.soc_pkg.state[index*TD2P_NUM_PM_LNS+1]==PORT_STATE__LINERATE_HG||_tdm->_chip_data.soc_pkg.state[index*TD2P_NUM_PM_LNS+1]==PORT_STATE__OVERSUB_HG)?(PM_ENCAP__HIGIG2):(PM_ENCAP__ETHRNT); 792 } 793 /* Chip: pmap */ 794 _tdm->_chip_data.soc_pkg.pmap=(int **) TDM_ALLOC((_tdm->_chip_data.soc_pkg.pmap_num_modules)*sizeof(int *), "portmod_map_l1"); 795 for (index=0; index<(_tdm->_chip_data.soc_pkg.pmap_num_modules); index++) { 796 _tdm->_chip_data.soc_pkg.pmap[index]=(int *) TDM_ALLOC((_tdm->_chip_data.soc_pkg.pmap_num_lanes)*sizeof(int), "portmod_map_l2"); 797 TDM_MSET(_tdm->_chip_data.soc_pkg.pmap[index],(_tdm->_chip_data.soc_pkg.num_ext_ports),_tdm->_chip_data.soc_pkg.pmap_num_lanes); 798 } 799 /* Chip: PGW x0 calendar group */ 800 _tdm->_chip_data.cal_0.cal_main=(int *) TDM_ALLOC((_tdm->_chip_data.cal_0.cal_len)*sizeof(int), "TDM inst 0 main calendar"); 801 TDM_MSET(_tdm->_chip_data.cal_0.cal_main,(_tdm->_chip_data.soc_pkg.num_ext_ports),_tdm->_chip_data.cal_0.cal_len); 802 _tdm->_chip_data.cal_0.cal_grp=(int **) TDM_ALLOC((_tdm->_chip_data.cal_0.grp_num)*sizeof(int *), "TDM inst 0 groups"); 803 for (index=0; index<(_tdm->_chip_data.cal_0.grp_num); index++) { 804 _tdm->_chip_data.cal_0.cal_grp[index]=(int *) TDM_ALLOC((_tdm->_chip_data.cal_0.grp_len)*sizeof(int), "TDM inst 0 group calendars"); 805 TDM_MSET(_tdm->_chip_data.cal_0.cal_grp[index],(_tdm->_chip_data.soc_pkg.num_ext_ports),_tdm->_chip_data.cal_0.grp_len); 806 } 807 /* Chip: PGW x1 calendar group */ 808 _tdm->_chip_data.cal_1.cal_main=(int *) TDM_ALLOC((_tdm->_chip_data.cal_1.cal_len)*sizeof(int), "TDM inst 1 main calendar"); 809 TDM_MSET(_tdm->_chip_data.cal_1.cal_main,(_tdm->_chip_data.soc_pkg.num_ext_ports),_tdm->_chip_data.cal_1.cal_len); 810 _tdm->_chip_data.cal_1.cal_grp=(int **) TDM_ALLOC((_tdm->_chip_data.cal_1.grp_num)*sizeof(int *), "TDM inst 1 groups"); 811 for (index=0; index<(_tdm->_chip_data.cal_1.grp_num); index++) { 812 _tdm->_chip_data.cal_1.cal_grp[index]=(int *) TDM_ALLOC((_tdm->_chip_data.cal_1.grp_len)*sizeof(int), "TDM inst 1 group calendars"); 813 TDM_MSET(_tdm->_chip_data.cal_1.cal_grp[index],(_tdm->_chip_data.soc_pkg.num_ext_ports),_tdm->_chip_data.cal_1.grp_len); 814 } 815 /* Chip: PGW y0 calendar group */ 816 _tdm->_chip_data.cal_2.cal_main=(int *) TDM_ALLOC((_tdm->_chip_data.cal_2.cal_len)*sizeof(int), "TDM inst 2 main calendar"); 817 TDM_MSET(_tdm->_chip_data.cal_2.cal_main,(_tdm->_chip_data.soc_pkg.num_ext_ports),_tdm->_chip_data.cal_2.cal_len); 818 _tdm->_chip_data.cal_2.cal_grp=(int **) TDM_ALLOC((_tdm->_chip_data.cal_2.grp_num)*sizeof(int *), "TDM inst 2 groups"); 819 for (index=0; index<(_tdm->_chip_data.cal_2.grp_num); index++) { 820 _tdm->_chip_data.cal_2.cal_grp[index]=(int *) TDM_ALLOC((_tdm->_chip_data.cal_2.grp_len)*sizeof(int), "TDM inst 2 group calendars"); 821 TDM_MSET(_tdm->_chip_data.cal_2.cal_grp[index],(_tdm->_chip_data.soc_pkg.num_ext_ports),_tdm->_chip_data.cal_2.grp_len); 822 } 823 /* Chip: PGW y1 calendar group */ 824 _tdm->_chip_data.cal_3.cal_main=(int *) TDM_ALLOC((_tdm->_chip_data.cal_3.cal_len)*sizeof(int), "TDM inst 3 main calendar"); 825 TDM_MSET(_tdm->_chip_data.cal_3.cal_main,(_tdm->_chip_data.soc_pkg.num_ext_ports),_tdm->_chip_data.cal_3.cal_len); 826 _tdm->_chip_data.cal_3.cal_grp=(int **) TDM_ALLOC((_tdm->_chip_data.cal_3.grp_num)*sizeof(int *), "TDM inst 3 groups"); 827 for (index=0; index<(_tdm->_chip_data.cal_3.grp_num); index++) { 828 _tdm->_chip_data.cal_3.cal_grp[index]=(int *) TDM_ALLOC((_tdm->_chip_data.cal_3.grp_len)*sizeof(int), "TDM inst 3 group calendars"); 829 TDM_MSET(_tdm->_chip_data.cal_3.cal_grp[index],(_tdm->_chip_data.soc_pkg.num_ext_ports),_tdm->_chip_data.cal_3.grp_len); 830 } 831 /* Chip: MMU x pipe calendar group */ 832 _tdm->_chip_data.cal_4.cal_main=(int *) TDM_ALLOC((_tdm->_chip_data.cal_4.cal_len)*sizeof(int), "TDM inst 4 main calendar"); 833 TDM_MSET(_tdm->_chip_data.cal_4.cal_main,(_tdm->_chip_data.soc_pkg.num_ext_ports),_tdm->_chip_data.cal_4.cal_len); 834 _tdm->_chip_data.cal_4.cal_grp=(int **) TDM_ALLOC((_tdm->_chip_data.cal_4.grp_num)*sizeof(int *), "TDM inst 4 groups"); 835 for (index=0; index<(_tdm->_chip_data.cal_4.grp_num); index++) { 836 _tdm->_chip_data.cal_4.cal_grp[index]=(int *) TDM_ALLOC((_tdm->_chip_data.cal_4.grp_len)*sizeof(int), "TDM inst 4 group calendars"); 837 TDM_MSET(_tdm->_chip_data.cal_4.cal_grp[index],(_tdm->_chip_data.soc_pkg.num_ext_ports),_tdm->_chip_data.cal_4.grp_len); 838 } 839 /* Chip: MMU y pipe calendar group */ 840 _tdm->_chip_data.cal_5.cal_main=(int *) TDM_ALLOC((_tdm->_chip_data.cal_5.cal_len)*sizeof(int), "TDM inst 5 main calendar"); 841 TDM_MSET(_tdm->_chip_data.cal_5.cal_main,(_tdm->_chip_data.soc_pkg.num_ext_ports),_tdm->_chip_data.cal_5.cal_len); 842 _tdm->_chip_data.cal_5.cal_grp=(int **) TDM_ALLOC((_tdm->_chip_data.cal_5.grp_num)*sizeof(int *), "TDM inst 5 groups"); 843 for (index=0; index<(_tdm->_chip_data.cal_5.grp_num); index++) { 844 _tdm->_chip_data.cal_5.cal_grp[index]=(int *) TDM_ALLOC((_tdm->_chip_data.cal_5.grp_len)*sizeof(int), "TDM inst 5 group calendars"); 845 TDM_MSET(_tdm->_chip_data.cal_5.cal_grp[index],(_tdm->_chip_data.soc_pkg.num_ext_ports),_tdm->_chip_data.cal_5.grp_len); 846 } 847 /* Chip: IARB static calendar group */ 848 _tdm->_chip_data.cal_6.cal_main=(int *) TDM_ALLOC((_tdm->_chip_data.cal_6.cal_len)*sizeof(int), "TDM inst 6 main calendar"); 849 TDM_MSET(_tdm->_chip_data.cal_6.cal_main,(_tdm->_chip_data.soc_pkg.num_ext_ports),_tdm->_chip_data.cal_6.cal_len); 850 _tdm->_chip_data.cal_7.cal_main=(int *) TDM_ALLOC((_tdm->_chip_data.cal_7.cal_len)*sizeof(int), "TDM inst 7 main calendar"); 851 TDM_MSET(_tdm->_chip_data.cal_7.cal_main,(_tdm->_chip_data.soc_pkg.num_ext_ports),_tdm->_chip_data.cal_7.cal_len); 852 853 /* Core: parameters */ 854 _tdm->_core_data.vmap_max_len = TD2P_VMAP_MAX_LEN; 855 _tdm->_core_data.vmap_max_wid = TD2P_VMAP_MAX_WID; 856 _tdm->_core_data.rule__same_port_min = LLS_MIN_SPACING; 857 _tdm->_core_data.rule__prox_port_min = VBS_MIN_SPACING; 858 /* Core: vmap */ 859 _tdm->_core_data.vmap=(unsigned short **) TDM_ALLOC((_tdm->_core_data.vmap_max_wid)*sizeof(unsigned short *), "vector_map_l1"); 860 for (index=0; index<(_tdm->_core_data.vmap_max_wid); index++) { 861 _tdm->_core_data.vmap[index]=(unsigned short *) TDM_ALLOC((_tdm->_core_data.vmap_max_len)*sizeof(unsigned short), "vector_map_l2"); 862 } 863 864 return ( _tdm->_chip_exec[TDM_CHIP_EXEC__TRANSCRIPTION]( _tdm ) ); 865 } 866 867 868 /** 869 @name: tdm_td2p_post 870 @param: 871 */ 872 int 873 tdm_td2p_post( tdm_mod_t *_tdm ) 874 { 875 /* TDM self-check */ 876 if (_tdm->_chip_data.soc_pkg.soc_vars.td2p.tdm_chk_en==BOOL_TRUE){ 877 _tdm->_chip_exec[TDM_CHIP_EXEC__CHECK](_tdm); 878 } 879 880 return PASS; 881 } 882 883 884 /** 885 @name: tdm_td2p_free 886 @param: 887 */ 888 int 889 tdm_td2p_free( tdm_mod_t *_tdm ) 890 { 891 int index; 892 /* Chip: pmap */ 893 for (index=0; index<(_tdm->_chip_data.soc_pkg.pmap_num_modules); index++) { 894 TDM_FREE(_tdm->_chip_data.soc_pkg.pmap[index]); 895 } 896 TDM_FREE(_tdm->_chip_data.soc_pkg.pmap); 897 /* Chip: PGW x0 calendar group */ 898 TDM_FREE(_tdm->_chip_data.cal_0.cal_main); 899 for (index=0; index<(_tdm->_chip_data.cal_0.grp_num); index++) { 900 TDM_FREE(_tdm->_chip_data.cal_0.cal_grp[index]); 901 } 902 TDM_FREE(_tdm->_chip_data.cal_0.cal_grp); 903 /* Chip: PGW x1 calendar group */ 904 TDM_FREE(_tdm->_chip_data.cal_1.cal_main); 905 for (index=0; index<(_tdm->_chip_data.cal_1.grp_num); index++) { 906 TDM_FREE(_tdm->_chip_data.cal_1.cal_grp[index]); 907 } 908 TDM_FREE(_tdm->_chip_data.cal_1.cal_grp); 909 /* Chip: PGW y0 calendar group */ 910 TDM_FREE(_tdm->_chip_data.cal_2.cal_main); 911 for (index=0; index<(_tdm->_chip_data.cal_2.grp_num); index++) { 912 TDM_FREE(_tdm->_chip_data.cal_2.cal_grp[index]); 913 } 914 TDM_FREE(_tdm->_chip_data.cal_2.cal_grp); 915 /* Chip: PGW y1 calendar group */ 916 TDM_FREE(_tdm->_chip_data.cal_3.cal_main); 917 for (index=0; index<(_tdm->_chip_data.cal_3.grp_num); index++) { 918 TDM_FREE(_tdm->_chip_data.cal_3.cal_grp[index]); 919 } 920 TDM_FREE(_tdm->_chip_data.cal_3.cal_grp); 921 /* Chip: MMU x pipe calendar group */ 922 TDM_FREE(_tdm->_chip_data.cal_4.cal_main); 923 for (index=0; index<(_tdm->_chip_data.cal_4.grp_num); index++) { 924 TDM_FREE(_tdm->_chip_data.cal_4.cal_grp[index]); 925 } 926 TDM_FREE(_tdm->_chip_data.cal_4.cal_grp); 927 /* Chip: MMU y pipe calendar group */ 928 TDM_FREE(_tdm->_chip_data.cal_5.cal_main); 929 for (index=0; index<(_tdm->_chip_data.cal_5.grp_num); index++) { 930 TDM_FREE(_tdm->_chip_data.cal_5.cal_grp[index]); 931 } 932 TDM_FREE(_tdm->_chip_data.cal_5.cal_grp); 933 /* Chip: IARB static calendar group */ 934 TDM_FREE(_tdm->_chip_data.cal_6.cal_main); 935 TDM_FREE(_tdm->_chip_data.cal_7.cal_main); 936 /* Core: vmap */ 937 for (index=0; index<(_tdm->_core_data.vmap_max_wid); index++) { 938 TDM_FREE(_tdm->_core_data.vmap[index]); 939 } 940 TDM_FREE(_tdm->_core_data.vmap); 941 942 return PASS; 943 }