tdm_td2p_iarb.c (51585B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * $All Rights Reserved.$ 7 * 8 * TDM Trident2+ IARB scheduler 9 */ 10 #ifdef _TDM_STANDALONE 11 #include <tdm_top.h> 12 #else 13 #include <soc/tdm/core/tdm_top.h> 14 #endif 15 16 17 /** 18 @name: tdm_td2p_init_iarb_tdm_ovs_table 19 @param: int, int, int, int, int*, int*, int[512], int[512] 20 21 IARB TDM Oversubscription Schedule: 22 Input 1 => Core bandwidth - 960/720/640/480. 23 Input 2 => 1 if there are 4x1G management ports, 0 otherwise. 24 Input 3 => 1 if there are 4x2.5G management ports, 0 otherwise. 25 Input 4 => 1 if there are 1x10G management port, 0 otherwise. 26 Output 5 => The X-pipe TDM oversubscription table wrap pointer value. 27 Output 6 => The Y-pipe TDM oversubscription table wrap pointer value. 28 Output 7 => The X-pipe TDM oversubscription schedule. 29 Output 8 => The Y-pipe TDM oversubscription schedule. 30 */ 31 void 32 tdm_td2p_init_iarb_tdm_ovs_table ( 33 int core_bw, 34 int mgm4x1, 35 int mgm4x2p5, 36 int mgm1x10, 37 int *iarb_tdm_wrap_ptr_ovs_x, 38 int *iarb_tdm_wrap_ptr_ovs_y, 39 int *iarb_tdm_tbl_ovs_x, 40 int *iarb_tdm_tbl_ovs_y) 41 { 42 int i; 43 44 switch (core_bw) { 45 case 960 : 46 /* First, assume no management ports. */ 47 *iarb_tdm_wrap_ptr_ovs_x = 199; 48 *iarb_tdm_wrap_ptr_ovs_y = 199; 49 for (i = 0; i < 24; i++) { 50 if (i%2 == 0) { 51 iarb_tdm_tbl_ovs_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 52 iarb_tdm_tbl_ovs_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 53 } else { 54 iarb_tdm_tbl_ovs_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 55 iarb_tdm_tbl_ovs_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 56 } 57 } 58 iarb_tdm_tbl_ovs_x[24] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 59 iarb_tdm_tbl_ovs_y[24] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 60 for (i = 25; i < 49; i++) { 61 if (i%2 == 0) { 62 iarb_tdm_tbl_ovs_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 63 iarb_tdm_tbl_ovs_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 64 } else { 65 iarb_tdm_tbl_ovs_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 66 iarb_tdm_tbl_ovs_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 67 } 68 } 69 iarb_tdm_tbl_ovs_x[49] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 70 iarb_tdm_tbl_ovs_y[49] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 71 for (i = 50; i < 74; i++) { 72 if (i%2 == 0) { 73 iarb_tdm_tbl_ovs_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 74 iarb_tdm_tbl_ovs_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 75 } else { 76 iarb_tdm_tbl_ovs_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 77 iarb_tdm_tbl_ovs_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 78 } 79 } 80 iarb_tdm_tbl_ovs_x[74] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 81 iarb_tdm_tbl_ovs_y[74] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 82 for (i = 75; i < 99; i++) { 83 if (i%2 == 0) { 84 iarb_tdm_tbl_ovs_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 85 iarb_tdm_tbl_ovs_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 86 } else { 87 iarb_tdm_tbl_ovs_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 88 iarb_tdm_tbl_ovs_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 89 } 90 } 91 iarb_tdm_tbl_ovs_x[99] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 92 iarb_tdm_tbl_ovs_y[99] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 93 for (i = 100; i < 124; i++) { 94 if (i%2 == 0) { 95 iarb_tdm_tbl_ovs_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 96 iarb_tdm_tbl_ovs_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 97 } else { 98 iarb_tdm_tbl_ovs_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 99 iarb_tdm_tbl_ovs_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 100 } 101 } 102 iarb_tdm_tbl_ovs_x[124] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 103 iarb_tdm_tbl_ovs_y[124] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 104 for (i = 125; i < 149; i++) { 105 if (i%2 == 0) { 106 iarb_tdm_tbl_ovs_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 107 iarb_tdm_tbl_ovs_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 108 } else { 109 iarb_tdm_tbl_ovs_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 110 iarb_tdm_tbl_ovs_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 111 } 112 } 113 iarb_tdm_tbl_ovs_x[149] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 114 iarb_tdm_tbl_ovs_y[149] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 115 for (i = 150; i < 174; i++) { 116 if (i%2 == 0) { 117 iarb_tdm_tbl_ovs_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 118 iarb_tdm_tbl_ovs_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 119 } else { 120 iarb_tdm_tbl_ovs_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 121 iarb_tdm_tbl_ovs_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 122 } 123 } 124 iarb_tdm_tbl_ovs_x[174] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 125 iarb_tdm_tbl_ovs_y[174] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 126 for (i = 175; i < 199; i++) { 127 if (i%2 == 0) { 128 iarb_tdm_tbl_ovs_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 129 iarb_tdm_tbl_ovs_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 130 } else { 131 iarb_tdm_tbl_ovs_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 132 iarb_tdm_tbl_ovs_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 133 } 134 } 135 iarb_tdm_tbl_ovs_x[199] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 136 iarb_tdm_tbl_ovs_y[199] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 137 138 /* Then check for management ports. */ 139 if (mgm4x1) { 140 iarb_tdm_tbl_ovs_x[24] = IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 141 iarb_tdm_tbl_ovs_x[49] = IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 142 iarb_tdm_tbl_ovs_x[74] = IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 143 iarb_tdm_tbl_ovs_x[99] = IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 144 } else if (mgm4x2p5 || mgm1x10) { 145 /* 146 Nate's comment in spreadsheet: "Not suppoted in Iarb. It's still possible 147 to have a 10G management port scheduled with regular ports in PGW". 148 */ 149 } 150 break; 151 case 720 : 152 /* First, assume no management ports. */ 153 *iarb_tdm_wrap_ptr_ovs_x = 159; 154 *iarb_tdm_wrap_ptr_ovs_y = 159; 155 for (i = 0; i < 15; i++) { 156 if (i%2 == 0) { 157 iarb_tdm_tbl_ovs_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 158 iarb_tdm_tbl_ovs_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 159 } else { 160 iarb_tdm_tbl_ovs_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 161 iarb_tdm_tbl_ovs_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 162 } 163 } 164 iarb_tdm_tbl_ovs_x[15] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 165 iarb_tdm_tbl_ovs_y[15] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 166 iarb_tdm_tbl_ovs_x[16] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 167 iarb_tdm_tbl_ovs_y[16] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 168 for (i = 17; i < 31; i++) { 169 if (i%2 == 0) { 170 iarb_tdm_tbl_ovs_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 171 iarb_tdm_tbl_ovs_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 172 } else { 173 iarb_tdm_tbl_ovs_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 174 iarb_tdm_tbl_ovs_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 175 } 176 } 177 iarb_tdm_tbl_ovs_x[31] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 178 iarb_tdm_tbl_ovs_y[31] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 179 for (i = 32; i < 47; i++) { 180 if (i%2 == 0) { 181 iarb_tdm_tbl_ovs_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 182 iarb_tdm_tbl_ovs_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 183 } else { 184 iarb_tdm_tbl_ovs_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 185 iarb_tdm_tbl_ovs_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 186 } 187 } 188 iarb_tdm_tbl_ovs_x[47] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 189 iarb_tdm_tbl_ovs_y[47] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 190 iarb_tdm_tbl_ovs_x[48] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 191 iarb_tdm_tbl_ovs_y[48] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 192 for (i = 49; i < 63; i++) { 193 if (i%2 == 0) { 194 iarb_tdm_tbl_ovs_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 195 iarb_tdm_tbl_ovs_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 196 } else { 197 iarb_tdm_tbl_ovs_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 198 iarb_tdm_tbl_ovs_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 199 } 200 } 201 iarb_tdm_tbl_ovs_x[63] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 202 iarb_tdm_tbl_ovs_y[63] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 203 for (i = 64; i < 79; i++) { 204 if (i%2 == 0) { 205 iarb_tdm_tbl_ovs_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 206 iarb_tdm_tbl_ovs_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 207 } else { 208 iarb_tdm_tbl_ovs_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 209 iarb_tdm_tbl_ovs_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 210 } 211 } 212 iarb_tdm_tbl_ovs_x[79] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 213 iarb_tdm_tbl_ovs_y[79] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 214 iarb_tdm_tbl_ovs_x[80] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 215 iarb_tdm_tbl_ovs_y[80] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 216 for (i = 81; i < 95; i++) { 217 if (i%2 == 0) { 218 iarb_tdm_tbl_ovs_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 219 iarb_tdm_tbl_ovs_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 220 } else { 221 iarb_tdm_tbl_ovs_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 222 iarb_tdm_tbl_ovs_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 223 } 224 } 225 iarb_tdm_tbl_ovs_x[95] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 226 iarb_tdm_tbl_ovs_y[95] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 227 for (i = 96; i < 111; i++) { 228 if (i%2 == 0) { 229 iarb_tdm_tbl_ovs_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 230 iarb_tdm_tbl_ovs_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 231 } else { 232 iarb_tdm_tbl_ovs_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 233 iarb_tdm_tbl_ovs_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 234 } 235 } 236 iarb_tdm_tbl_ovs_x[111] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 237 iarb_tdm_tbl_ovs_y[111] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 238 iarb_tdm_tbl_ovs_x[112] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 239 iarb_tdm_tbl_ovs_y[112] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 240 for (i = 113; i < 127; i++) { 241 if (i%2 == 0) { 242 iarb_tdm_tbl_ovs_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 243 iarb_tdm_tbl_ovs_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 244 } else { 245 iarb_tdm_tbl_ovs_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 246 iarb_tdm_tbl_ovs_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 247 } 248 } 249 iarb_tdm_tbl_ovs_x[127] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 250 iarb_tdm_tbl_ovs_y[127] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 251 for (i = 128; i < 143; i++) { 252 if (i%2 == 0) { 253 iarb_tdm_tbl_ovs_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 254 iarb_tdm_tbl_ovs_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 255 } else { 256 iarb_tdm_tbl_ovs_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 257 iarb_tdm_tbl_ovs_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 258 } 259 } 260 iarb_tdm_tbl_ovs_x[143] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 261 iarb_tdm_tbl_ovs_y[143] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 262 iarb_tdm_tbl_ovs_x[144] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 263 iarb_tdm_tbl_ovs_y[144] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 264 for (i = 145; i < 159; i++) { 265 if (i%2 == 0) { 266 iarb_tdm_tbl_ovs_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 267 iarb_tdm_tbl_ovs_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 268 } else { 269 iarb_tdm_tbl_ovs_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 270 iarb_tdm_tbl_ovs_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 271 } 272 } 273 iarb_tdm_tbl_ovs_x[159] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 274 iarb_tdm_tbl_ovs_y[159] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 275 276 /* Then check for management ports. */ 277 if (mgm4x1) { 278 iarb_tdm_tbl_ovs_x[16] = IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 279 iarb_tdm_tbl_ovs_x[31] = IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 280 iarb_tdm_tbl_ovs_x[48] = IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 281 iarb_tdm_tbl_ovs_x[63] = IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 282 } else if (mgm4x2p5 || mgm1x10) { 283 iarb_tdm_tbl_ovs_x[16] = IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 284 iarb_tdm_tbl_ovs_x[31] = IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 285 iarb_tdm_tbl_ovs_x[48] = IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 286 iarb_tdm_tbl_ovs_x[63] = IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 287 iarb_tdm_tbl_ovs_x[80] = IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 288 iarb_tdm_tbl_ovs_x[95] = IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 289 iarb_tdm_tbl_ovs_x[112] = IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 290 iarb_tdm_tbl_ovs_x[127] = IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 291 } 292 break; 293 case 640 : 294 /* First, assume no management ports. */ 295 *iarb_tdm_wrap_ptr_ovs_x = 135; 296 *iarb_tdm_wrap_ptr_ovs_y = 135; 297 for (i = 0; i < 16; i++) { 298 if (i%2 == 0) { 299 iarb_tdm_tbl_ovs_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 300 iarb_tdm_tbl_ovs_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 301 } else { 302 iarb_tdm_tbl_ovs_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 303 iarb_tdm_tbl_ovs_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 304 } 305 } 306 iarb_tdm_tbl_ovs_x[16] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 307 iarb_tdm_tbl_ovs_y[16] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 308 for (i = 17; i < 33; i++) { 309 if (i%2 == 0) { 310 iarb_tdm_tbl_ovs_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 311 iarb_tdm_tbl_ovs_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 312 } else { 313 iarb_tdm_tbl_ovs_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 314 iarb_tdm_tbl_ovs_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 315 } 316 } 317 iarb_tdm_tbl_ovs_x[33] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 318 iarb_tdm_tbl_ovs_y[33] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 319 for (i = 34; i < 50; i++) { 320 if (i%2 == 0) { 321 iarb_tdm_tbl_ovs_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 322 iarb_tdm_tbl_ovs_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 323 } else { 324 iarb_tdm_tbl_ovs_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 325 iarb_tdm_tbl_ovs_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 326 } 327 } 328 iarb_tdm_tbl_ovs_x[50] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 329 iarb_tdm_tbl_ovs_y[50] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 330 for (i = 51; i < 67; i++) { 331 if (i%2 == 0) { 332 iarb_tdm_tbl_ovs_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 333 iarb_tdm_tbl_ovs_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 334 } else { 335 iarb_tdm_tbl_ovs_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 336 iarb_tdm_tbl_ovs_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 337 } 338 } 339 iarb_tdm_tbl_ovs_x[67] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 340 iarb_tdm_tbl_ovs_y[67] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 341 for (i = 68; i < 84; i++) { 342 if (i%2 == 0) { 343 iarb_tdm_tbl_ovs_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 344 iarb_tdm_tbl_ovs_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 345 } else { 346 iarb_tdm_tbl_ovs_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 347 iarb_tdm_tbl_ovs_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 348 } 349 } 350 iarb_tdm_tbl_ovs_x[84] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 351 iarb_tdm_tbl_ovs_y[84] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 352 for (i = 85; i < 101; i++) { 353 if (i%2 == 0) { 354 iarb_tdm_tbl_ovs_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 355 iarb_tdm_tbl_ovs_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 356 } else { 357 iarb_tdm_tbl_ovs_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 358 iarb_tdm_tbl_ovs_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 359 } 360 } 361 iarb_tdm_tbl_ovs_x[101] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 362 iarb_tdm_tbl_ovs_y[101] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 363 for (i = 102; i < 118; i++) { 364 if (i%2 == 0) { 365 iarb_tdm_tbl_ovs_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 366 iarb_tdm_tbl_ovs_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 367 } else { 368 iarb_tdm_tbl_ovs_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 369 iarb_tdm_tbl_ovs_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 370 } 371 } 372 iarb_tdm_tbl_ovs_x[118] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 373 iarb_tdm_tbl_ovs_y[118] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 374 for (i = 119; i < 135; i++) { 375 if (i%2 == 0) { 376 iarb_tdm_tbl_ovs_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 377 iarb_tdm_tbl_ovs_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 378 } else { 379 iarb_tdm_tbl_ovs_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 380 iarb_tdm_tbl_ovs_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 381 } 382 } 383 iarb_tdm_tbl_ovs_x[135] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 384 iarb_tdm_tbl_ovs_y[135] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 385 386 /* Then check for management ports. */ 387 if (mgm4x1) { 388 iarb_tdm_tbl_ovs_x[16] = IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 389 iarb_tdm_tbl_ovs_x[50] = IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 390 iarb_tdm_tbl_ovs_x[33] = IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 391 iarb_tdm_tbl_ovs_x[67] = IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 392 } else if (mgm4x2p5 || mgm1x10) { 393 /* 394 Nate's comment in spreadsheet: "Not suppoted in Iarb. It's still possible 395 to have a 10G management port scheduled with regular ports in PGW". 396 */ 397 } 398 break; 399 case 480 : 400 /* First, assume no management ports. */ 401 *iarb_tdm_wrap_ptr_ovs_x = 105; 402 *iarb_tdm_wrap_ptr_ovs_y = 105; 403 for (i = 0; i < 10; i++) { 404 if (i%2 == 0) { 405 iarb_tdm_tbl_ovs_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 406 iarb_tdm_tbl_ovs_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 407 } else { 408 iarb_tdm_tbl_ovs_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 409 iarb_tdm_tbl_ovs_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 410 } 411 } 412 iarb_tdm_tbl_ovs_x[10] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 413 iarb_tdm_tbl_ovs_y[10] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 414 for (i = 11; i < 20; i++) { 415 if (i%2 == 0) { 416 iarb_tdm_tbl_ovs_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 417 iarb_tdm_tbl_ovs_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 418 } else { 419 iarb_tdm_tbl_ovs_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 420 iarb_tdm_tbl_ovs_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 421 } 422 } 423 iarb_tdm_tbl_ovs_x[20] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 424 iarb_tdm_tbl_ovs_y[20] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 425 iarb_tdm_tbl_ovs_x[21] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 426 iarb_tdm_tbl_ovs_y[21] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 427 for (i = 22; i < 30; i++) { 428 if (i%2 == 0) { 429 iarb_tdm_tbl_ovs_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 430 iarb_tdm_tbl_ovs_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 431 } else { 432 iarb_tdm_tbl_ovs_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 433 iarb_tdm_tbl_ovs_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 434 } 435 } 436 iarb_tdm_tbl_ovs_x[30] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 437 iarb_tdm_tbl_ovs_y[30] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 438 iarb_tdm_tbl_ovs_x[31] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 439 iarb_tdm_tbl_ovs_y[31] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 440 for (i = 32; i < 41; i++) { 441 if (i%2 == 0) { 442 iarb_tdm_tbl_ovs_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 443 iarb_tdm_tbl_ovs_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 444 } else { 445 iarb_tdm_tbl_ovs_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 446 iarb_tdm_tbl_ovs_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 447 } 448 } 449 iarb_tdm_tbl_ovs_x[41] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 450 iarb_tdm_tbl_ovs_y[41] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 451 for (i = 42; i < 52; i++) { 452 if (i%2 == 0) { 453 iarb_tdm_tbl_ovs_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 454 iarb_tdm_tbl_ovs_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 455 } else { 456 iarb_tdm_tbl_ovs_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 457 iarb_tdm_tbl_ovs_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 458 } 459 } 460 iarb_tdm_tbl_ovs_x[52] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 461 iarb_tdm_tbl_ovs_y[52] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 462 for (i = 53; i < 63; i++) { 463 if (i%2 == 0) { 464 iarb_tdm_tbl_ovs_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 465 iarb_tdm_tbl_ovs_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 466 } else { 467 iarb_tdm_tbl_ovs_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 468 iarb_tdm_tbl_ovs_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 469 } 470 } 471 iarb_tdm_tbl_ovs_x[63] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 472 iarb_tdm_tbl_ovs_y[63] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 473 for (i = 64; i < 73; i++) { 474 if (i%2 == 0) { 475 iarb_tdm_tbl_ovs_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 476 iarb_tdm_tbl_ovs_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 477 } else { 478 iarb_tdm_tbl_ovs_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 479 iarb_tdm_tbl_ovs_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 480 } 481 } 482 iarb_tdm_tbl_ovs_x[73] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 483 iarb_tdm_tbl_ovs_y[73] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 484 iarb_tdm_tbl_ovs_x[74] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 485 iarb_tdm_tbl_ovs_y[74] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 486 for (i = 75; i < 83; i++) { 487 if (i%2 == 0) { 488 iarb_tdm_tbl_ovs_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 489 iarb_tdm_tbl_ovs_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 490 } else { 491 iarb_tdm_tbl_ovs_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 492 iarb_tdm_tbl_ovs_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 493 } 494 } 495 iarb_tdm_tbl_ovs_x[83] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 496 iarb_tdm_tbl_ovs_y[83] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 497 iarb_tdm_tbl_ovs_x[84] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 498 iarb_tdm_tbl_ovs_y[84] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 499 for (i = 85; i < 94; i++) { 500 if (i%2 == 0) { 501 iarb_tdm_tbl_ovs_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 502 iarb_tdm_tbl_ovs_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 503 } else { 504 iarb_tdm_tbl_ovs_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 505 iarb_tdm_tbl_ovs_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 506 } 507 } 508 iarb_tdm_tbl_ovs_x[94] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 509 iarb_tdm_tbl_ovs_y[94] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 510 for (i = 95; i < 105; i++) { 511 if (i%2 == 0) { 512 iarb_tdm_tbl_ovs_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 513 iarb_tdm_tbl_ovs_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 514 } else { 515 iarb_tdm_tbl_ovs_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 516 iarb_tdm_tbl_ovs_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 517 } 518 } 519 iarb_tdm_tbl_ovs_x[105] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 520 iarb_tdm_tbl_ovs_y[105] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 521 522 /* Then check for management ports. */ 523 if (mgm4x1) { 524 iarb_tdm_tbl_ovs_x[10] = IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 525 iarb_tdm_tbl_ovs_x[21] = IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 526 iarb_tdm_tbl_ovs_x[30] = IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 527 iarb_tdm_tbl_ovs_x[41] = IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 528 } else if (mgm4x2p5 || mgm1x10) { 529 iarb_tdm_tbl_ovs_x[10] = IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 530 iarb_tdm_tbl_ovs_x[21] = IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 531 iarb_tdm_tbl_ovs_x[30] = IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 532 iarb_tdm_tbl_ovs_x[41] = IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 533 iarb_tdm_tbl_ovs_x[52] = IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 534 iarb_tdm_tbl_ovs_x[63] = IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 535 iarb_tdm_tbl_ovs_x[74] = IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 536 iarb_tdm_tbl_ovs_x[83] = IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 537 } 538 break; 539 } 540 } 541 542 543 /** 544 @name: tdm_td2p_init_iarb_tdm_lr_table 545 @param: int, int, int, int, int*, int*, int[512], int[512] 546 547 IARB TDM Linerate Schedule: 548 Input 1 => Core bandwidth - 960/720/640/480. 549 Input 2 => 1 if there are 4x1G management ports, 0 otherwise. 550 Input 3 => 1 if there are 4x2.5G management ports, 0 otherwise. 551 Input 4 => 1 if there are 1x10G management port, 0 otherwise. 552 Output 5 => The X-pipe TDM linerate table wrap pointer value. 553 Output 6 => The Y-pipe TDM linerate table wrap pointer value. 554 Output 7 => The X-pipe TDM linerate schedule. 555 Output 8 => The Y-pipe TDM linerate schedule. 556 */ 557 void 558 tdm_td2p_init_iarb_tdm_lr_table ( 559 int core_bw, 560 int mgm4x1, 561 int mgm4x2p5, 562 int mgm1x10, 563 int *iarb_tdm_wrap_ptr_lr_x, 564 int *iarb_tdm_wrap_ptr_lr_y, 565 int *iarb_tdm_tbl_lr_x, 566 int *iarb_tdm_tbl_lr_y) 567 { 568 int i; 569 570 switch (core_bw) { 571 case 960 : 572 /* First, assume no management ports. */ 573 *iarb_tdm_wrap_ptr_lr_x = 199; 574 *iarb_tdm_wrap_ptr_lr_y = 199; 575 for (i = 0; i < 24; i++) { 576 if (i%2 == 0) { 577 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 578 iarb_tdm_tbl_lr_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 579 } else { 580 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 581 iarb_tdm_tbl_lr_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 582 } 583 } 584 iarb_tdm_tbl_lr_x[24] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 585 iarb_tdm_tbl_lr_y[24] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 586 for (i = 25; i < 49; i++) { 587 if (i%2 == 0) { 588 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 589 iarb_tdm_tbl_lr_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 590 } else { 591 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 592 iarb_tdm_tbl_lr_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 593 } 594 } 595 iarb_tdm_tbl_lr_x[49] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 596 iarb_tdm_tbl_lr_y[49] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 597 for (i = 50; i < 74; i++) { 598 if (i%2 == 0) { 599 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 600 iarb_tdm_tbl_lr_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 601 } else { 602 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 603 iarb_tdm_tbl_lr_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 604 } 605 } 606 iarb_tdm_tbl_lr_x[74] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 607 iarb_tdm_tbl_lr_y[74] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 608 for (i = 75; i < 99; i++) { 609 if (i%2 == 0) { 610 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 611 iarb_tdm_tbl_lr_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 612 } else { 613 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 614 iarb_tdm_tbl_lr_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 615 } 616 } 617 iarb_tdm_tbl_lr_x[99] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 618 iarb_tdm_tbl_lr_y[99] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 619 for (i = 100; i < 124; i++) { 620 if (i%2 == 0) { 621 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 622 iarb_tdm_tbl_lr_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 623 } else { 624 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 625 iarb_tdm_tbl_lr_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 626 } 627 } 628 iarb_tdm_tbl_lr_x[124] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 629 iarb_tdm_tbl_lr_y[124] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 630 for (i = 125; i < 149; i++) { 631 if (i%2 == 0) { 632 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 633 iarb_tdm_tbl_lr_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 634 } else { 635 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 636 iarb_tdm_tbl_lr_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 637 } 638 } 639 iarb_tdm_tbl_lr_x[149] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 640 iarb_tdm_tbl_lr_y[149] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 641 for (i = 150; i < 174; i++) { 642 if (i%2 == 0) { 643 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 644 iarb_tdm_tbl_lr_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 645 } else { 646 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 647 iarb_tdm_tbl_lr_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 648 } 649 } 650 iarb_tdm_tbl_lr_x[174] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 651 iarb_tdm_tbl_lr_y[174] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 652 for (i = 175; i < 199; i++) { 653 if (i%2 == 0) { 654 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 655 iarb_tdm_tbl_lr_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 656 } else { 657 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 658 iarb_tdm_tbl_lr_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 659 } 660 } 661 iarb_tdm_tbl_lr_x[199] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 662 iarb_tdm_tbl_lr_y[199] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 663 664 /* Then check for management ports. */ 665 if (mgm4x1) { 666 iarb_tdm_tbl_lr_x[24] = IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 667 iarb_tdm_tbl_lr_x[74] = IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 668 iarb_tdm_tbl_lr_x[124] = IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 669 iarb_tdm_tbl_lr_x[174] = IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 670 iarb_tdm_tbl_lr_x[199] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 671 } else if (mgm4x2p5 || mgm1x10) { 672 iarb_tdm_tbl_lr_x[24] = IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 673 iarb_tdm_tbl_lr_x[74] = IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 674 iarb_tdm_tbl_lr_x[124] = IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 675 iarb_tdm_tbl_lr_x[174] = IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 676 iarb_tdm_tbl_lr_x[49] = IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 677 iarb_tdm_tbl_lr_x[99] = IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 678 iarb_tdm_tbl_lr_x[149] = IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 679 iarb_tdm_tbl_lr_x[199] = IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 680 } 681 break; 682 case 720 : 683 /* First, assume no management ports. */ 684 *iarb_tdm_wrap_ptr_lr_x = 159; 685 *iarb_tdm_wrap_ptr_lr_y = 159; 686 for (i = 0; i < 15; i++) { 687 if (i%2 == 0) { 688 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 689 iarb_tdm_tbl_lr_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 690 } else { 691 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 692 iarb_tdm_tbl_lr_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 693 } 694 } 695 iarb_tdm_tbl_lr_x[15] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 696 iarb_tdm_tbl_lr_y[15] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 697 for (i = 16; i < 31; i++) { 698 if (i%2 == 0) { 699 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 700 iarb_tdm_tbl_lr_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 701 } else { 702 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 703 iarb_tdm_tbl_lr_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 704 } 705 } 706 iarb_tdm_tbl_lr_x[31] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 707 iarb_tdm_tbl_lr_y[31] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 708 for (i = 32; i < 47; i++) { 709 if (i%2 == 0) { 710 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 711 iarb_tdm_tbl_lr_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 712 } else { 713 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 714 iarb_tdm_tbl_lr_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 715 } 716 } 717 iarb_tdm_tbl_lr_x[47] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 718 iarb_tdm_tbl_lr_y[47] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 719 for (i = 48; i < 63; i++) { 720 if (i%2 == 0) { 721 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 722 iarb_tdm_tbl_lr_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 723 } else { 724 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 725 iarb_tdm_tbl_lr_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 726 } 727 } 728 iarb_tdm_tbl_lr_x[63] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 729 iarb_tdm_tbl_lr_y[63] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 730 for (i = 64; i < 79; i++) { 731 if (i%2 == 0) { 732 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 733 iarb_tdm_tbl_lr_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 734 } else { 735 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 736 iarb_tdm_tbl_lr_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 737 } 738 } 739 iarb_tdm_tbl_lr_x[79] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 740 iarb_tdm_tbl_lr_y[79] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 741 for (i = 80; i < 95; i++) { 742 if (i%2 == 0) { 743 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 744 iarb_tdm_tbl_lr_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 745 } else { 746 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 747 iarb_tdm_tbl_lr_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 748 } 749 } 750 iarb_tdm_tbl_lr_x[95] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 751 iarb_tdm_tbl_lr_y[95] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 752 for (i = 96; i < 111; i++) { 753 if (i%2 == 0) { 754 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 755 iarb_tdm_tbl_lr_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 756 } else { 757 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 758 iarb_tdm_tbl_lr_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 759 } 760 } 761 iarb_tdm_tbl_lr_x[111] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 762 iarb_tdm_tbl_lr_y[111] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 763 for (i = 112; i < 127; i++) { 764 if (i%2 == 0) { 765 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 766 iarb_tdm_tbl_lr_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 767 } else { 768 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 769 iarb_tdm_tbl_lr_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 770 } 771 } 772 iarb_tdm_tbl_lr_x[127] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 773 iarb_tdm_tbl_lr_y[127] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 774 for (i = 128; i < 143; i++) { 775 if (i%2 == 0) { 776 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 777 iarb_tdm_tbl_lr_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 778 } else { 779 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 780 iarb_tdm_tbl_lr_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 781 } 782 } 783 iarb_tdm_tbl_lr_x[143] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 784 iarb_tdm_tbl_lr_y[143] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 785 for (i = 144; i < 159; i++) { 786 if (i%2 == 0) { 787 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 788 iarb_tdm_tbl_lr_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 789 } else { 790 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 791 iarb_tdm_tbl_lr_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 792 } 793 } 794 iarb_tdm_tbl_lr_x[159] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 795 iarb_tdm_tbl_lr_y[159] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 796 797 /* Then check for management ports. */ 798 if (mgm4x1) { 799 iarb_tdm_tbl_lr_x[15] = IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 800 iarb_tdm_tbl_lr_x[31] = IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 801 iarb_tdm_tbl_lr_x[47] = IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 802 iarb_tdm_tbl_lr_x[63] = IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 803 } else if (mgm4x2p5 || mgm1x10) { 804 iarb_tdm_tbl_lr_x[15] = IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 805 iarb_tdm_tbl_lr_x[31] = IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 806 iarb_tdm_tbl_lr_x[47] = IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 807 iarb_tdm_tbl_lr_x[63] = IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 808 iarb_tdm_tbl_lr_x[79] = IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 809 iarb_tdm_tbl_lr_x[95] = IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 810 iarb_tdm_tbl_lr_x[111] = IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 811 iarb_tdm_tbl_lr_x[127] = IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 812 } 813 break; 814 case 640 : 815 /* First, assume no management ports. */ 816 *iarb_tdm_wrap_ptr_lr_x = 135; 817 *iarb_tdm_wrap_ptr_lr_y = 135; 818 for (i = 0; i < 16; i++) { 819 if (i%2 == 0) { 820 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 821 iarb_tdm_tbl_lr_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 822 } else { 823 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 824 iarb_tdm_tbl_lr_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 825 } 826 } 827 iarb_tdm_tbl_lr_x[16] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 828 iarb_tdm_tbl_lr_y[16] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 829 for (i = 17; i < 33; i++) { 830 if (i%2 == 0) { 831 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 832 iarb_tdm_tbl_lr_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 833 } else { 834 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 835 iarb_tdm_tbl_lr_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 836 } 837 } 838 iarb_tdm_tbl_lr_x[33] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 839 iarb_tdm_tbl_lr_y[33] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 840 for (i = 34; i < 50; i++) { 841 if (i%2 == 0) { 842 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 843 iarb_tdm_tbl_lr_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 844 } else { 845 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 846 iarb_tdm_tbl_lr_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 847 } 848 } 849 iarb_tdm_tbl_lr_x[50] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 850 iarb_tdm_tbl_lr_y[50] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 851 for (i = 51; i < 67; i++) { 852 if (i%2 == 0) { 853 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 854 iarb_tdm_tbl_lr_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 855 } else { 856 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 857 iarb_tdm_tbl_lr_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 858 } 859 } 860 iarb_tdm_tbl_lr_x[67] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 861 iarb_tdm_tbl_lr_y[67] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 862 for (i = 68; i < 84; i++) { 863 if (i%2 == 0) { 864 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 865 iarb_tdm_tbl_lr_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 866 } else { 867 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 868 iarb_tdm_tbl_lr_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 869 } 870 } 871 iarb_tdm_tbl_lr_x[84] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 872 iarb_tdm_tbl_lr_y[84] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 873 for (i = 85; i < 101; i++) { 874 if (i%2 == 0) { 875 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 876 iarb_tdm_tbl_lr_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 877 } else { 878 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 879 iarb_tdm_tbl_lr_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 880 } 881 } 882 iarb_tdm_tbl_lr_x[101] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 883 iarb_tdm_tbl_lr_y[101] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 884 for (i = 102; i < 118; i++) { 885 if (i%2 == 0) { 886 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 887 iarb_tdm_tbl_lr_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 888 } else { 889 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 890 iarb_tdm_tbl_lr_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 891 } 892 } 893 iarb_tdm_tbl_lr_x[118] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 894 iarb_tdm_tbl_lr_y[118] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 895 for (i = 119; i < 135; i++) { 896 if (i%2 == 0) { 897 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 898 iarb_tdm_tbl_lr_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 899 } else { 900 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 901 iarb_tdm_tbl_lr_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 902 } 903 } 904 iarb_tdm_tbl_lr_x[135] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 905 iarb_tdm_tbl_lr_y[135] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 906 907 /* Then check for management ports. */ 908 if (mgm4x1) { 909 iarb_tdm_tbl_lr_x[16] = IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 910 iarb_tdm_tbl_lr_x[50] = IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 911 iarb_tdm_tbl_lr_x[33] = IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 912 iarb_tdm_tbl_lr_x[67] = IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 913 } else if (mgm4x2p5 || mgm1x10) { 914 iarb_tdm_tbl_lr_x[16] = IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 915 iarb_tdm_tbl_lr_x[50] = IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 916 iarb_tdm_tbl_lr_x[33] = IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 917 iarb_tdm_tbl_lr_x[67] = IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 918 iarb_tdm_tbl_lr_x[84] = IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 919 iarb_tdm_tbl_lr_x[101] = IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 920 iarb_tdm_tbl_lr_x[118] = IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 921 iarb_tdm_tbl_lr_x[135] = IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 922 } 923 break; 924 case 480 : 925 /* First, assume no management ports. */ 926 *iarb_tdm_wrap_ptr_lr_x = 105; 927 *iarb_tdm_wrap_ptr_lr_y = 105; 928 for (i = 0; i < 10; i++) { 929 if (i%2 == 0) { 930 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 931 iarb_tdm_tbl_lr_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 932 } else { 933 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 934 iarb_tdm_tbl_lr_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 935 } 936 } 937 iarb_tdm_tbl_lr_x[10] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 938 iarb_tdm_tbl_lr_y[10] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 939 for (i = 11; i < 20; i++) { 940 if (i%2 == 0) { 941 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 942 iarb_tdm_tbl_lr_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 943 } else { 944 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 945 iarb_tdm_tbl_lr_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 946 } 947 } 948 iarb_tdm_tbl_lr_x[20] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 949 iarb_tdm_tbl_lr_y[20] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 950 iarb_tdm_tbl_lr_x[21] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 951 iarb_tdm_tbl_lr_y[21] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 952 for (i = 22; i < 30; i++) { 953 if (i%2 == 0) { 954 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 955 iarb_tdm_tbl_lr_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 956 } else { 957 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 958 iarb_tdm_tbl_lr_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 959 } 960 } 961 iarb_tdm_tbl_lr_x[30] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 962 iarb_tdm_tbl_lr_y[30] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 963 iarb_tdm_tbl_lr_x[31] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 964 iarb_tdm_tbl_lr_y[31] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 965 for (i = 32; i < 41; i++) { 966 if (i%2 == 0) { 967 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 968 iarb_tdm_tbl_lr_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 969 } else { 970 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 971 iarb_tdm_tbl_lr_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 972 } 973 } 974 iarb_tdm_tbl_lr_x[41] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 975 iarb_tdm_tbl_lr_y[41] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 976 for (i = 42; i < 52; i++) { 977 if (i%2 == 0) { 978 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 979 iarb_tdm_tbl_lr_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 980 } else { 981 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 982 iarb_tdm_tbl_lr_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 983 } 984 } 985 iarb_tdm_tbl_lr_x[52] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 986 iarb_tdm_tbl_lr_y[52] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 987 for (i = 53; i < 63; i++) { 988 if (i%2 == 0) { 989 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 990 iarb_tdm_tbl_lr_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 991 } else { 992 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 993 iarb_tdm_tbl_lr_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 994 } 995 } 996 iarb_tdm_tbl_lr_x[63] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 997 iarb_tdm_tbl_lr_y[63] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 998 for (i = 64; i < 73; i++) { 999 if (i%2 == 0) { 1000 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1001 iarb_tdm_tbl_lr_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1002 } else { 1003 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1004 iarb_tdm_tbl_lr_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1005 } 1006 } 1007 iarb_tdm_tbl_lr_x[73] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1008 iarb_tdm_tbl_lr_y[73] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 1009 iarb_tdm_tbl_lr_x[74] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 1010 iarb_tdm_tbl_lr_y[74] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1011 for (i = 75; i < 83; i++) { 1012 if (i%2 == 0) { 1013 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1014 iarb_tdm_tbl_lr_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1015 } else { 1016 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1017 iarb_tdm_tbl_lr_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1018 } 1019 } 1020 iarb_tdm_tbl_lr_x[83] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 1021 iarb_tdm_tbl_lr_y[83] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1022 iarb_tdm_tbl_lr_x[84] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1023 iarb_tdm_tbl_lr_y[84] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 1024 for (i = 85; i < 94; i++) { 1025 if (i%2 == 0) { 1026 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1027 iarb_tdm_tbl_lr_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1028 } else { 1029 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1030 iarb_tdm_tbl_lr_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1031 } 1032 } 1033 iarb_tdm_tbl_lr_x[94] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 1034 iarb_tdm_tbl_lr_y[94] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 1035 for (i = 95; i < 105; i++) { 1036 if (i%2 == 0) { 1037 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1038 iarb_tdm_tbl_lr_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1039 } else { 1040 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1041 iarb_tdm_tbl_lr_y[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1042 } 1043 } 1044 iarb_tdm_tbl_lr_x[105] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 1045 iarb_tdm_tbl_lr_y[105] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 1046 1047 /* Then check for management ports. */ 1048 if (mgm4x1) { 1049 iarb_tdm_tbl_lr_x[10] = IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 1050 iarb_tdm_tbl_lr_x[21] = IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 1051 iarb_tdm_tbl_lr_x[30] = IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 1052 iarb_tdm_tbl_lr_x[41] = IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 1053 } else if (mgm4x2p5 || mgm1x10) { 1054 iarb_tdm_tbl_lr_x[10] = IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 1055 iarb_tdm_tbl_lr_x[21] = IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 1056 iarb_tdm_tbl_lr_x[30] = IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 1057 iarb_tdm_tbl_lr_x[41] = IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 1058 iarb_tdm_tbl_lr_x[52] = IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 1059 iarb_tdm_tbl_lr_x[63] = IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 1060 iarb_tdm_tbl_lr_x[74] = IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 1061 iarb_tdm_tbl_lr_x[83] = IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 1062 } 1063 break; 1064 } 1065 } 1066 1067 1068 /** 1069 @name: tdm_td2p_set_iarb_tdm_table 1070 @param: int, int, int, int, int, int, int*, int*, int[512], int[512] 1071 1072 IARB TDM Schedule Generator: 1073 Return => 1 if error, 0 otherwise. 1074 Input 1 => Core bandwidth - 960/720/640/480. 1075 Input 2 => 1 if X-pipe is oversub, 0 otherwise. 1076 Input 3 => 1 if Y-pipe is oversub, 0 otherwise. 1077 Input 4 => 1 if there are 4x1G management ports, 0 otherwise. 1078 Input 5 => 1 if there are 4x2.5G management ports, 0 otherwise. 1079 Input 6 => 1 if there are 1x10G management port, 0 otherwise. 1080 Output 7 => The X-pipe TDM table wrap pointer value. 1081 Output 8 => The Y-pipe TDM table wrap pointer value. 1082 Output 9 => The X-pipe TDM schedule. 1083 Output 10 => The Y-pipe TDM schedule. 1084 */ 1085 int 1086 tdm_td2p_set_iarb_tdm_table ( 1087 int core_bw, 1088 int is_x_ovs, 1089 int is_y_ovs, 1090 int mgm4x1, 1091 int mgm4x2p5, 1092 int mgm1x10, 1093 int *iarb_tdm_wrap_ptr_x, 1094 int *iarb_tdm_wrap_ptr_y, 1095 int iarb_tdm_tbl_x[512], 1096 int iarb_tdm_tbl_y[512]) 1097 { 1098 /* #if ( defined(_SET_TDM_DV) || defined(_SET_TDM_DEV) ) */ 1099 int i; 1100 int is_succ; 1101 int iarb_tdm_wrap_ptr_ovs_x, iarb_tdm_wrap_ptr_ovs_y; 1102 /*int iarb_tdm_tbl_ovs_x[512], iarb_tdm_tbl_ovs_y[512];*/ 1103 int iarb_tdm_wrap_ptr_lr_x, iarb_tdm_wrap_ptr_lr_y; 1104 /*int iarb_tdm_tbl_lr_x[512], iarb_tdm_tbl_lr_y[512];*/ 1105 int *iarb_tdm_tbl_ovs_x, *iarb_tdm_tbl_ovs_y; 1106 int *iarb_tdm_tbl_lr_x, *iarb_tdm_tbl_lr_y; 1107 iarb_tdm_tbl_ovs_x = (int *) TDM_ALLOC(sizeof(int) * 512, "iarb_tdm_tbl_ovs_x"); 1108 iarb_tdm_tbl_ovs_y = (int *) TDM_ALLOC(sizeof(int) * 512, "iarb_tdm_tbl_ovs_y"); 1109 iarb_tdm_tbl_lr_x = (int *) TDM_ALLOC(sizeof(int) * 512, "iarb_tdm_tbl_lr_x"); 1110 iarb_tdm_tbl_lr_y = (int *) TDM_ALLOC(sizeof(int) * 512, "iarb_tdm_tbl_lr_y"); 1111 /* #else 1112 int i; 1113 int is_succ; 1114 int iarb_tdm_wrap_ptr_ovs_x, iarb_tdm_wrap_ptr_ovs_y; 1115 int iarb_tdm_wrap_ptr_lr_x, iarb_tdm_wrap_ptr_lr_y; 1116 TDM_ALLOC(iarb_tdm_tbl_ovs_x, int, 512, "iarb_tdm_tbl_ovs_x"); 1117 TDM_ALLOC(iarb_tdm_tbl_ovs_y, int, 512, "iarb_tdm_tbl_ovs_y"); 1118 TDM_ALLOC(iarb_tdm_tbl_lr_x, int, 512, "iarb_tdm_tbl_lr_x"); 1119 TDM_ALLOC(iarb_tdm_tbl_lr_y, int, 512, "iarb_tdm_tbl_lr_y"); 1120 #endif */ 1121 1122 /* 1123 Initial IARB TDM table containers - to be copied into final container based 1124 on the TDM selected. 1125 */ 1126 if (!(!mgm4x1 && !mgm4x2p5 && !mgm1x10) && !(mgm4x1 ^ mgm4x2p5 ^ mgm1x10)) { 1127 TDM_ERROR0("IARB -- Multiple management port settings specified!\n"); 1128 } 1129 1130 tdm_td2p_init_iarb_tdm_ovs_table(core_bw, mgm4x1, mgm4x2p5, mgm1x10, 1131 &iarb_tdm_wrap_ptr_ovs_x, &iarb_tdm_wrap_ptr_ovs_y, 1132 iarb_tdm_tbl_ovs_x, iarb_tdm_tbl_ovs_y); 1133 tdm_td2p_init_iarb_tdm_lr_table(core_bw, mgm4x1, mgm4x2p5, mgm1x10, 1134 &iarb_tdm_wrap_ptr_lr_x, &iarb_tdm_wrap_ptr_lr_y, 1135 iarb_tdm_tbl_lr_x, iarb_tdm_tbl_lr_y); 1136 1137 if ((is_x_ovs == 0) && (is_y_ovs == 0)) { 1138 /* The following TDMs have linerate X-pipe and linerate Y-pipe. */ 1139 *iarb_tdm_wrap_ptr_x = iarb_tdm_wrap_ptr_lr_x; 1140 *iarb_tdm_wrap_ptr_y = iarb_tdm_wrap_ptr_lr_y; 1141 memcpy(iarb_tdm_tbl_x, iarb_tdm_tbl_lr_x, sizeof(int) * 512); 1142 memcpy(iarb_tdm_tbl_y, iarb_tdm_tbl_lr_y, sizeof(int) * 512); 1143 } 1144 if ((is_x_ovs == 0) && (is_y_ovs == 1)) { 1145 /* The following TDMs have linerate X-pipe and oversubscribed Y-pipe. */ 1146 *iarb_tdm_wrap_ptr_x = iarb_tdm_wrap_ptr_lr_x; 1147 *iarb_tdm_wrap_ptr_y = iarb_tdm_wrap_ptr_ovs_y; 1148 memcpy(iarb_tdm_tbl_x, iarb_tdm_tbl_lr_x, sizeof(int) * 512); 1149 memcpy(iarb_tdm_tbl_y, iarb_tdm_tbl_ovs_y, sizeof(int) * 512); 1150 } 1151 if ((is_x_ovs == 1) && (is_y_ovs == 0)) { 1152 /* The following TDMs have oversubscribed X-pipe and linerate Y-pipe. */ 1153 *iarb_tdm_wrap_ptr_x = iarb_tdm_wrap_ptr_ovs_x; 1154 *iarb_tdm_wrap_ptr_y = iarb_tdm_wrap_ptr_lr_y; 1155 memcpy(iarb_tdm_tbl_x, iarb_tdm_tbl_ovs_x, sizeof(int) * 512); 1156 memcpy(iarb_tdm_tbl_y, iarb_tdm_tbl_lr_y, sizeof(int) * 512); 1157 } 1158 if ((is_x_ovs == 1) && (is_y_ovs == 1)) { 1159 /* The following TDMs have oversubscribed X-pipe and oversubscribed Y-pipe. */ 1160 *iarb_tdm_wrap_ptr_x = iarb_tdm_wrap_ptr_ovs_x; 1161 *iarb_tdm_wrap_ptr_y = iarb_tdm_wrap_ptr_ovs_y; 1162 memcpy(iarb_tdm_tbl_x, iarb_tdm_tbl_ovs_x, sizeof(int) * 512); 1163 memcpy(iarb_tdm_tbl_y, iarb_tdm_tbl_ovs_y, sizeof(int) * 512); 1164 } 1165 1166 TDM_PRINT1("IARB -- iarb_tdm_wrap_ptr_x = %d\n",*iarb_tdm_wrap_ptr_x); 1167 for (i = 0; i <= *iarb_tdm_wrap_ptr_x; i++) { 1168 TDM_PRINT2("IARB -- iarb_tdm_tbl_x[%d] = %d\n",i,iarb_tdm_tbl_x[i]); 1169 } 1170 TDM_PRINT1("IARB -- iarb_tdm_wrap_ptr_y = %d\n",*iarb_tdm_wrap_ptr_y); 1171 for (i = 0; i <= *iarb_tdm_wrap_ptr_y; i++) { 1172 TDM_PRINT2("IARB -- iarb_tdm_tbl_y[%d] = %d\n",i,iarb_tdm_tbl_y[i]); 1173 } 1174 1175 /* Always succeeds by definition. */ 1176 is_succ = 1; 1177 TDM_FREE(iarb_tdm_tbl_ovs_x); 1178 TDM_FREE(iarb_tdm_tbl_ovs_y); 1179 TDM_FREE(iarb_tdm_tbl_lr_x); 1180 TDM_FREE(iarb_tdm_tbl_lr_y); 1181 return is_succ; 1182 }