tdm_th2_main.c (24973B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * $All Rights Reserved.$ 7 * 8 * TDM chip main functions 9 */ 10 #ifdef _TDM_STANDALONE 11 #include <tdm_top.h> 12 #else 13 #include <soc/tdm/core/tdm_top.h> 14 #endif 15 16 17 /** 18 @name: tdm_th2_corereq 19 @param: 20 21 Allocate memory for core data execute request to core executive 22 */ 23 int 24 tdm_th2_corereq( tdm_mod_t *_tdm ) 25 { 26 int idx1; 27 28 _tdm->_core_data.vars_pkg.cal_id=_tdm->_core_data.vars_pkg.pipe; 29 if (_tdm->_core_data.vars_pkg.pipe==0) { 30 _tdm->_core_data.vmap=(unsigned short **) TDM_ALLOC((_tdm->_core_data.vmap_max_wid)*sizeof(unsigned short *), "vector_map_l1"); 31 for (idx1=0; idx1<(_tdm->_core_data.vmap_max_wid); idx1++) { 32 _tdm->_core_data.vmap[idx1]=(unsigned short *) TDM_ALLOC((_tdm->_core_data.vmap_max_len)*sizeof(unsigned short), "vector_map_l2"); 33 } 34 } 35 return ( _tdm->_core_exec[TDM_CORE_EXEC__INIT]( _tdm ) ); 36 } 37 38 39 /** 40 @name: tdm_th2_scheduler_wrap 41 @param: 42 43 Code wrapper for ingress TDM scheduling 44 */ 45 int 46 tdm_th2_scheduler_wrap( tdm_mod_t *_tdm ) 47 { 48 int iter, idx1=0, idx2=0, ethernet_encap=BOOL_TRUE; 49 int tdm_cal_length=0; 50 51 _tdm->_core_data.vars_pkg.pipe=(_tdm->_chip_data.soc_pkg.soc_vars.th2.pipe_start/64); 52 if (_tdm->_core_data.vars_pkg.pipe>3) { 53 TDM_ERROR1("Invalid pipe ID - %0d\n",_tdm->_core_data.vars_pkg.pipe); 54 return (TDM_EXEC_CHIP_SIZE+1); 55 } 56 tdm_th2_parse_pipe(_tdm); 57 for (iter=0; iter<TDM_AUX_SIZE; iter++) { 58 _tdm->_core_data.vars_pkg.lr_buffer[iter]=TH2_NUM_EXT_PORTS; 59 _tdm->_core_data.vars_pkg.os_buffer[iter]=TH2_NUM_EXT_PORTS; 60 } 61 for (iter=(_tdm->_chip_data.soc_pkg.soc_vars.th2.pipe_start-1); iter<(_tdm->_chip_data.soc_pkg.soc_vars.th2.pipe_end); iter++) { 62 if ( (_tdm->_chip_data.soc_pkg.state[iter]==PORT_STATE__LINERATE)||(_tdm->_chip_data.soc_pkg.state[iter]==PORT_STATE__LINERATE_HG) ) { 63 if (idx1<64) { 64 _tdm->_core_data.vars_pkg.lr_buffer[idx1]=(iter+1); 65 idx1++; 66 } 67 else { 68 TDM_PRINT0("Line rate queue overflow, ports may have been skipped.\n"); 69 } 70 } 71 else if ( (_tdm->_chip_data.soc_pkg.state[iter]==PORT_STATE__OVERSUB)||(_tdm->_chip_data.soc_pkg.state[iter]==PORT_STATE__OVERSUB_HG) ) { 72 if (idx2<64) { 73 _tdm->_core_data.vars_pkg.os_buffer[idx2]=(iter+1); 74 idx2++; 75 } 76 else { 77 TDM_PRINT0("Oversub queue overflow, ports may have been skipped.\n"); 78 } 79 } 80 } 81 if ( (_tdm->_chip_data.soc_pkg.soc_vars.th2.mgmt_pm_hg==BOOL_TRUE) && 82 (_tdm->_core_data.vars_pkg.pipe==1||_tdm->_core_data.vars_pkg.pipe==2) && 83 ( ((_tdm->_core_data.vars_pkg.lr_buffer[0]!=TH2_NUM_EXT_PORTS) && (_tdm->_chip_data.soc_pkg.clk_freq>=MIN_HG_FREQ))|| 84 (_tdm->_core_data.vars_pkg.lr_buffer[0]==TH2_NUM_EXT_PORTS) ) ) { 85 _tdm->_chip_data.soc_pkg.soc_vars.th2.higig_mgmt=BOOL_TRUE; 86 } 87 for (iter=0; iter<TDM_AUX_SIZE; iter++) { 88 if (_tdm->_core_data.vars_pkg.lr_buffer[iter]!=TH2_NUM_EXT_PORTS) { 89 TDM_PUSH(_tdm->_core_data.vars_pkg.lr_buffer[iter],TDM_CORE_EXEC__ENCAP_SCAN,ethernet_encap); 90 if (!ethernet_encap) { 91 break; 92 } 93 } 94 } 95 if ((ethernet_encap)&&(!_tdm->_chip_data.soc_pkg.soc_vars.th2.higig_mgmt)&& 96 (_tdm->_chip_data.soc_pkg.soc_vars.th2.cal_universal_en == 0)) { 97 switch (_tdm->_chip_data.soc_pkg.clk_freq) { 98 case 1700 : tdm_cal_length = LEN_1700MHZ_EN; break; 99 case 1625 : tdm_cal_length = LEN_1625MHZ_EN; break; 100 case 1525 : tdm_cal_length = LEN_1525MHZ_EN; break; 101 case 1425 : tdm_cal_length = LEN_1425MHZ_EN; break; 102 case 1325 : tdm_cal_length = LEN_1325MHZ_EN; break; 103 case 1275 : tdm_cal_length = LEN_1275MHZ_EN; break; 104 case 1225 : tdm_cal_length = LEN_1225MHZ_EN; break; 105 case 1133 : tdm_cal_length = LEN_1133MHZ_EN; break; 106 case 1125 : tdm_cal_length = LEN_1125MHZ_EN; break; 107 case 1050 : tdm_cal_length = LEN_1050MHZ_EN; break; 108 case 950 : tdm_cal_length = LEN_950MHZ_EN; break; 109 case 850 : tdm_cal_length = LEN_850MHZ_EN; break; 110 default: 111 TDM_PRINT1("Invalid frequency - %0dMHz not supported\n",_tdm->_chip_data.soc_pkg.clk_freq); 112 return 0; 113 break; 114 } 115 } 116 else { 117 switch (_tdm->_chip_data.soc_pkg.clk_freq) { 118 case 1700 : tdm_cal_length = LEN_1700MHZ_HG; break; 119 case 1625 : tdm_cal_length = LEN_1625MHZ_HG; break; 120 case 1525 : tdm_cal_length = LEN_1525MHZ_HG; break; 121 case 1425 : tdm_cal_length = LEN_1425MHZ_HG; break; 122 case 1325 : tdm_cal_length = LEN_1325MHZ_HG; break; 123 case 1275 : tdm_cal_length = LEN_1275MHZ_HG; break; 124 case 1225 : tdm_cal_length = LEN_1225MHZ_HG; break; 125 case 1133 : tdm_cal_length = LEN_1133MHZ_HG; break; 126 case 1125 : tdm_cal_length = LEN_1125MHZ_HG; break; 127 case 1050 : tdm_cal_length = LEN_1050MHZ_HG; break; 128 case 950 : tdm_cal_length = LEN_950MHZ_HG; break; 129 case 850 : tdm_cal_length = LEN_850MHZ_HG; break; 130 default: 131 TDM_PRINT1("Invalid frequency - %0dMHz not supported\n",_tdm->_chip_data.soc_pkg.clk_freq); 132 return 0; 133 break; 134 } 135 } 136 _tdm->_chip_data.soc_pkg.lr_idx_limit = tdm_cal_length - _tdm->_chip_data.soc_pkg.tvec_size; 137 _tdm->_core_data.vmap_max_wid=TH2_VMAP_MAX_WID; 138 _tdm->_core_data.vmap_max_len=TH2_VMAP_MAX_LEN; 139 140 return ( _tdm->_chip_exec[TDM_CHIP_EXEC__COREREQ]( _tdm ) ); 141 } 142 143 144 /** 145 @name: tdm_th2_pmap_transcription 146 @param: 147 148 149 Transcription algorithm for generating port module mapping 150 */ 151 int 152 tdm_th2_pmap_transcription( tdm_mod_t *_tdm ) 153 { 154 int i, j, last_port=TH2_NUM_EXT_PORTS; 155 /*char tmp_str[16];*/ 156 /*sprintf (cmd_str, "soc setmem -index %x %s {", index->d, addr);*/ 157 158 for (i=0; i<TH2_NUM_PHY_PM; i++) { 159 for (j=0; j<TH2_NUM_PM_LNS; j++) { 160 _tdm->_chip_data.soc_pkg.pmap[i][j]=TH2_NUM_EXT_PORTS; 161 } 162 } 163 for (i=1; i<=TH2_NUM_PHY_PORTS; i+=TH2_NUM_PM_LNS) { 164 last_port = TH2_NUM_EXT_PORTS; 165 for (j=0; j<TH2_NUM_PM_LNS; j++) { 166 switch (_tdm->_chip_data.soc_pkg.state[i+j]) { 167 case PORT_STATE__LINERATE: case PORT_STATE__OVERSUB: 168 case PORT_STATE__LINERATE_HG: case PORT_STATE__OVERSUB_HG: 169 if (_tdm->_chip_data.soc_pkg.speed[i+j]>SPEED_0) { 170 last_port=(i+j); 171 } 172 _tdm->_chip_data.soc_pkg.pmap[(i-1)/TH2_NUM_PM_LNS][j]=last_port; 173 break; 174 case PORT_STATE__COMBINE: case PORT_STATE__COMBINE_HG: 175 _tdm->_chip_data.soc_pkg.pmap[(i-1)/TH2_NUM_PM_LNS][j]=last_port; 176 break; 177 default: 178 _tdm->_chip_data.soc_pkg.pmap[(i-1)/TH2_NUM_PM_LNS][j]=TH2_NUM_EXT_PORTS; 179 break; 180 } 181 } 182 } 183 tdm_print_stat( _tdm ); 184 for (i=0; i<(TH2_NUM_EXT_PORTS-1); i++) { 185 _tdm->_chip_data.soc_pkg.state[i]=_tdm->_chip_data.soc_pkg.state[i+1]; 186 } 187 return ( _tdm->_chip_exec[TDM_CHIP_EXEC__INGRESS_WRAP]( _tdm ) ); 188 } 189 190 191 /** 192 @name: tdm_th2_dealloc 193 @param: 194 */ 195 int 196 tdm_th2_dealloc( tdm_mod_t *_tdm ) 197 { 198 int index; 199 200 201 TDM_PRINT0("Free pmap\n"); 202 for (index=0; index<(_tdm->_chip_data.soc_pkg.pmap_num_modules); index++) { 203 TDM_FREE(_tdm->_chip_data.soc_pkg.pmap[index]); 204 } 205 TDM_FREE(_tdm->_chip_data.soc_pkg.pmap); 206 207 /* Pipe 0 calendar group */ 208 209 TDM_FREE(_tdm->_chip_data.cal_0.cal_main); 210 211 for (index=0; index<(_tdm->_chip_data.cal_0.grp_num); index++) { 212 TDM_FREE(_tdm->_chip_data.cal_0.cal_grp[index]); 213 } 214 TDM_FREE(_tdm->_chip_data.cal_0.cal_grp[SHAPING_GRP_IDX_0]); 215 TDM_FREE(_tdm->_chip_data.cal_0.cal_grp[SHAPING_GRP_IDX_1]); 216 TDM_FREE(_tdm->_chip_data.cal_0.cal_grp); 217 218 TDM_PRINT0("Free PIPE 1 \n"); 219 /* Pipe 1 calendar group */ 220 TDM_FREE(_tdm->_chip_data.cal_1.cal_main); 221 for (index=0; index<(_tdm->_chip_data.cal_1.grp_num); index++) { 222 TDM_FREE(_tdm->_chip_data.cal_1.cal_grp[index]); 223 } 224 TDM_FREE(_tdm->_chip_data.cal_1.cal_grp[SHAPING_GRP_IDX_0]); 225 TDM_FREE(_tdm->_chip_data.cal_1.cal_grp[SHAPING_GRP_IDX_1]); 226 TDM_FREE(_tdm->_chip_data.cal_1.cal_grp); 227 228 TDM_PRINT0("Free PIPE 2 \n"); 229 /* Pipe 2 calendar group */ 230 TDM_FREE(_tdm->_chip_data.cal_2.cal_main); 231 for (index=0; index<(_tdm->_chip_data.cal_2.grp_num); index++) { 232 TDM_FREE(_tdm->_chip_data.cal_2.cal_grp[index]); 233 } 234 TDM_FREE(_tdm->_chip_data.cal_2.cal_grp[SHAPING_GRP_IDX_0]); 235 TDM_FREE(_tdm->_chip_data.cal_2.cal_grp[SHAPING_GRP_IDX_1]); 236 TDM_FREE(_tdm->_chip_data.cal_2.cal_grp); 237 238 TDM_PRINT0("Free PIPE 3 \n"); 239 /* Pipe 3 calendar group */ 240 TDM_FREE(_tdm->_chip_data.cal_3.cal_main); 241 for (index=0; index<(_tdm->_chip_data.cal_3.grp_num); index++) { 242 TDM_FREE(_tdm->_chip_data.cal_3.cal_grp[index]); 243 } 244 TDM_FREE(_tdm->_chip_data.cal_3.cal_grp[SHAPING_GRP_IDX_0]); 245 TDM_FREE(_tdm->_chip_data.cal_3.cal_grp[SHAPING_GRP_IDX_1]); 246 TDM_FREE(_tdm->_chip_data.cal_3.cal_grp); 247 248 TDM_PRINT0("Free MMU cal 0-3 \n"); 249 /* Pipe 0 calendar group MMU mirror */ 250 TDM_FREE(_tdm->_chip_data.cal_4.cal_main); 251 /* Pipe 1 calendar group MMU mirror */ 252 TDM_FREE(_tdm->_chip_data.cal_5.cal_main); 253 /* Pipe 2 calendar group MMU mirror */ 254 TDM_FREE(_tdm->_chip_data.cal_6.cal_main); 255 /* Pipe 3 calendar group MMU mirror */ 256 TDM_FREE(_tdm->_chip_data.cal_7.cal_main); 257 258 259 TDM_PRINT0("Free vmap \n"); 260 for (index=0; index<(_tdm->_core_data.vmap_max_wid); index++) { 261 TDM_FREE(_tdm->_core_data.vmap[index]); 262 } 263 TDM_FREE(_tdm->_core_data.vmap); 264 265 TDM_PRINT0("Free FINISH \n"); 266 267 TDM_PRINT0("Start free for FlexPort \n"); 268 269 /* If FlexPort, deallocate previous TDM tables */ 270 if (_tdm->_chip_data.soc_pkg.flex_port_en == 1) { 271 272 /* Pipe 0 calendar group */ 273 TDM_FREE(_tdm->_prev_chip_data.cal_0.cal_main); 274 for (index=0; index<(TH2_OS_VBS_GRP_NUM); index++) { 275 TDM_FREE(_tdm->_prev_chip_data.cal_0.cal_grp[index]); 276 } 277 TDM_FREE(_tdm->_prev_chip_data.cal_0.cal_grp[SHAPING_GRP_IDX_0]); 278 TDM_FREE(_tdm->_prev_chip_data.cal_0.cal_grp[SHAPING_GRP_IDX_1]); 279 TDM_FREE(_tdm->_prev_chip_data.cal_0.cal_grp); 280 281 /* Pipe 1 calendar group */ 282 TDM_FREE(_tdm->_prev_chip_data.cal_1.cal_main); 283 for (index=0; index<(TH2_OS_VBS_GRP_NUM); index++) { 284 TDM_FREE(_tdm->_prev_chip_data.cal_1.cal_grp[index]); 285 } 286 TDM_FREE(_tdm->_prev_chip_data.cal_1.cal_grp[SHAPING_GRP_IDX_0]); 287 TDM_FREE(_tdm->_prev_chip_data.cal_1.cal_grp[SHAPING_GRP_IDX_1]); 288 TDM_FREE(_tdm->_prev_chip_data.cal_1.cal_grp); 289 290 /* Pipe 2 calendar group */ 291 TDM_FREE(_tdm->_prev_chip_data.cal_2.cal_main); 292 for (index=0; index<(TH2_OS_VBS_GRP_NUM); index++) { 293 TDM_FREE(_tdm->_prev_chip_data.cal_2.cal_grp[index]); 294 } 295 TDM_FREE(_tdm->_prev_chip_data.cal_2.cal_grp[SHAPING_GRP_IDX_0]); 296 TDM_FREE(_tdm->_prev_chip_data.cal_2.cal_grp[SHAPING_GRP_IDX_1]); 297 TDM_FREE(_tdm->_prev_chip_data.cal_2.cal_grp); 298 299 /* Pipe 3 calendar group */ 300 TDM_FREE(_tdm->_prev_chip_data.cal_3.cal_main); 301 for (index=0; index<(TH2_OS_VBS_GRP_NUM); index++) { 302 TDM_FREE(_tdm->_prev_chip_data.cal_3.cal_grp[index]); 303 } 304 TDM_FREE(_tdm->_prev_chip_data.cal_3.cal_grp[SHAPING_GRP_IDX_0]); 305 TDM_FREE(_tdm->_prev_chip_data.cal_3.cal_grp[SHAPING_GRP_IDX_1]); 306 TDM_FREE(_tdm->_prev_chip_data.cal_3.cal_grp); 307 308 /* Pipe 0 calendar group MMU mirror */ 309 TDM_FREE(_tdm->_prev_chip_data.cal_4.cal_main); 310 /* Pipe 1 calendar group MMU mirror */ 311 TDM_FREE(_tdm->_prev_chip_data.cal_5.cal_main); 312 /* Pipe 2 calendar group MMU mirror */ 313 TDM_FREE(_tdm->_prev_chip_data.cal_6.cal_main); 314 /* Pipe 3 calendar group MMU mirror */ 315 TDM_FREE(_tdm->_prev_chip_data.cal_7.cal_main); 316 317 TDM_PRINT0("Finish free for FlexPort \n"); 318 } 319 320 return 1; 321 } 322 323 324 /** 325 @name: tdm_th2_alloc_prev_chip_data 326 @param: 327 328 * Description: 329 * Helper function to allocate previous TDM tables in in _tdm_pkg->_prev_chip_data at FlexPort 330 */ 331 int 332 tdm_th2_alloc_prev_chip_data( tdm_mod_t *_tdm_pkg ) 333 { 334 int index; 335 336 /* Construct OLD tdm cal_0/1/2/3/4/5/6/7 */ 337 /* Pipe 0 calendar group */ 338 _tdm_pkg->_prev_chip_data.cal_0.cal_main=(int *) TDM_ALLOC((TH2_LR_VBS_LEN)*sizeof(int), "OLD TDM inst 0 main calendar"); 339 _tdm_pkg->_prev_chip_data.cal_0.cal_grp=(int **) TDM_ALLOC((TH2_OS_VBS_GRP_NUM+2)*sizeof(int *), "OLD TDM inst 0 groups"); 340 for (index=0; index<(TH2_OS_VBS_GRP_NUM); index++) { 341 _tdm_pkg->_prev_chip_data.cal_0.cal_grp[index]=(int *) TDM_ALLOC((TH2_OS_VBS_GRP_LEN)*sizeof(int), "OLD TDM inst 0 group calendars"); 342 } 343 _tdm_pkg->_prev_chip_data.cal_0.cal_grp[SHAPING_GRP_IDX_0]=(int *) TDM_ALLOC((SHAPING_GRP_LEN)*sizeof(int), "OLD TDM inst 0 shaping calendars"); 344 _tdm_pkg->_prev_chip_data.cal_0.cal_grp[SHAPING_GRP_IDX_1]=(int *) TDM_ALLOC((SHAPING_GRP_LEN)*sizeof(int), "OLD TDM inst 0 shaping calendars"); 345 /* Pipe 1 calendar group */ 346 _tdm_pkg->_prev_chip_data.cal_1.cal_main=(int *) TDM_ALLOC((TH2_LR_VBS_LEN)*sizeof(int), "OLD TDM inst 1 main calendar"); 347 _tdm_pkg->_prev_chip_data.cal_1.cal_grp=(int **) TDM_ALLOC((TH2_OS_VBS_GRP_NUM+2)*sizeof(int *), "OLD TDM inst 1 groups"); 348 for (index=0; index<(TH2_OS_VBS_GRP_NUM); index++) { 349 _tdm_pkg->_prev_chip_data.cal_1.cal_grp[index]=(int *) TDM_ALLOC((TH2_OS_VBS_GRP_LEN)*sizeof(int), "OLD TDM inst 1 group calendars"); 350 } 351 _tdm_pkg->_prev_chip_data.cal_1.cal_grp[SHAPING_GRP_IDX_0]=(int *) TDM_ALLOC((SHAPING_GRP_LEN)*sizeof(int), "OLD TDM inst 1 shaping calendars"); 352 _tdm_pkg->_prev_chip_data.cal_1.cal_grp[SHAPING_GRP_IDX_1]=(int *) TDM_ALLOC((SHAPING_GRP_LEN)*sizeof(int), "OLD TDM inst 1 shaping calendars"); 353 /* Pipe 2 calendar group */ 354 _tdm_pkg->_prev_chip_data.cal_2.cal_main=(int *) TDM_ALLOC((TH2_LR_VBS_LEN)*sizeof(int), "OLD TDM inst 2 main calendar"); 355 _tdm_pkg->_prev_chip_data.cal_2.cal_grp=(int **) TDM_ALLOC((TH2_OS_VBS_GRP_NUM+2)*sizeof(int *), "OLD TDM inst 2 groups"); 356 for (index=0; index<(TH2_OS_VBS_GRP_NUM); index++) { 357 _tdm_pkg->_prev_chip_data.cal_2.cal_grp[index]=(int *) TDM_ALLOC((TH2_OS_VBS_GRP_LEN)*sizeof(int), "OLD TDM inst 2 group calendars"); 358 } 359 _tdm_pkg->_prev_chip_data.cal_2.cal_grp[SHAPING_GRP_IDX_0]=(int *) TDM_ALLOC((SHAPING_GRP_LEN)*sizeof(int), "OLD TDM inst 2 shaping calendars"); 360 _tdm_pkg->_prev_chip_data.cal_2.cal_grp[SHAPING_GRP_IDX_1]=(int *) TDM_ALLOC((SHAPING_GRP_LEN)*sizeof(int), "OLD TDM inst 2 shaping calendars"); 361 /* Pipe 3 calendar group */ 362 _tdm_pkg->_prev_chip_data.cal_3.cal_main=(int *) TDM_ALLOC((TH2_LR_VBS_LEN)*sizeof(int), "OLD TDM inst 3 main calendar"); 363 _tdm_pkg->_prev_chip_data.cal_3.cal_grp=(int **) TDM_ALLOC((TH2_OS_VBS_GRP_NUM+2)*sizeof(int *), "OLD TDM inst 3 groups"); 364 for (index=0; index<(TH2_OS_VBS_GRP_NUM); index++) { 365 _tdm_pkg->_prev_chip_data.cal_3.cal_grp[index]=(int *) TDM_ALLOC((TH2_OS_VBS_GRP_LEN)*sizeof(int), "OLD TDM inst 3 group calendars"); 366 } 367 _tdm_pkg->_prev_chip_data.cal_3.cal_grp[SHAPING_GRP_IDX_0]=(int *) TDM_ALLOC((SHAPING_GRP_LEN)*sizeof(int), "OLD TDM inst 3 shaping calendars"); 368 _tdm_pkg->_prev_chip_data.cal_3.cal_grp[SHAPING_GRP_IDX_1]=(int *) TDM_ALLOC((SHAPING_GRP_LEN)*sizeof(int), "OLD TDM inst 3 shaping calendars"); 369 /* Pipe 0 calendar group MMU mirror */ 370 _tdm_pkg->_prev_chip_data.cal_4.cal_main=(int *) TDM_ALLOC((TH2_LR_VBS_LEN)*sizeof(int), "OLD TDM inst 0 mirror calendar"); 371 /* Pipe 1 calendar group MMU mirror */ 372 _tdm_pkg->_prev_chip_data.cal_5.cal_main=(int *) TDM_ALLOC((TH2_LR_VBS_LEN)*sizeof(int), "OLD TDM inst 1 mirror calendar"); 373 /* Pipe 2 calendar group MMU mirror */ 374 _tdm_pkg->_prev_chip_data.cal_6.cal_main=(int *) TDM_ALLOC((TH2_LR_VBS_LEN)*sizeof(int), "OLD TDM inst 2 mirror calendar"); 375 /* Pipe 3 calendar group MMU mirror */ 376 _tdm_pkg->_prev_chip_data.cal_7.cal_main=(int *) TDM_ALLOC((TH2_LR_VBS_LEN)*sizeof(int), "OLD TDM inst 3 mirror calendar"); 377 378 return 1; 379 } 380 381 /** 382 @name: tdm_th2_init 383 @param: 384 */ 385 int 386 tdm_th2_init( tdm_mod_t *_tdm ) 387 { 388 int index; 389 390 _tdm->_chip_data.soc_pkg.pmap_num_modules = TH2_NUM_PM_MOD; 391 _tdm->_chip_data.soc_pkg.pmap_num_lanes = TH2_NUM_PM_LNS; 392 _tdm->_chip_data.soc_pkg.pm_num_phy_modules = TH2_NUM_PHY_PM; 393 394 _tdm->_chip_data.soc_pkg.soc_vars.ovsb_token = TH2_OVSB_TOKEN; 395 _tdm->_chip_data.soc_pkg.soc_vars.idl1_token = TH2_IDL1_TOKEN; 396 _tdm->_chip_data.soc_pkg.soc_vars.idl2_token = TH2_IDL2_TOKEN; 397 _tdm->_chip_data.soc_pkg.soc_vars.ancl_token = TH2_ANCL_TOKEN; 398 _tdm->_chip_data.soc_pkg.soc_vars.fp_port_lo = 1; 399 _tdm->_chip_data.soc_pkg.soc_vars.fp_port_hi = TH2_NUM_PHY_PORTS; 400 401 _tdm->_chip_data.cal_0.cal_len = TH2_LR_VBS_LEN; 402 _tdm->_chip_data.cal_0.grp_num = TH2_OS_VBS_GRP_NUM; 403 _tdm->_chip_data.cal_0.grp_len = TH2_OS_VBS_GRP_LEN; 404 _tdm->_chip_data.cal_1.cal_len = TH2_LR_VBS_LEN; 405 _tdm->_chip_data.cal_1.grp_num = TH2_OS_VBS_GRP_NUM; 406 _tdm->_chip_data.cal_1.grp_len = TH2_OS_VBS_GRP_LEN; 407 _tdm->_chip_data.cal_2.cal_len = TH2_LR_VBS_LEN; 408 _tdm->_chip_data.cal_2.grp_num = TH2_OS_VBS_GRP_NUM; 409 _tdm->_chip_data.cal_2.grp_len = TH2_OS_VBS_GRP_LEN; 410 _tdm->_chip_data.cal_3.cal_len = TH2_LR_VBS_LEN; 411 _tdm->_chip_data.cal_3.grp_num = TH2_OS_VBS_GRP_NUM; 412 _tdm->_chip_data.cal_3.grp_len = TH2_OS_VBS_GRP_LEN; 413 _tdm->_chip_data.cal_4.cal_len = TH2_LR_VBS_LEN; 414 _tdm->_chip_data.cal_5.cal_len = TH2_LR_VBS_LEN; 415 _tdm->_chip_data.cal_6.cal_len = TH2_LR_VBS_LEN; 416 _tdm->_chip_data.cal_7.cal_len = TH2_LR_VBS_LEN; 417 418 _tdm->_core_data.vars_pkg.pipe=0; 419 _tdm->_chip_data.soc_pkg.soc_vars.th2.higig_mgmt=BOOL_FALSE; 420 _tdm->_chip_data.soc_pkg.lr_idx_limit=LEN_850MHZ_EN; 421 _tdm->_chip_data.soc_pkg.soc_vars.th2.pipe_start=1; 422 _tdm->_chip_data.soc_pkg.soc_vars.th2.pipe_end=64; 423 _tdm->_chip_data.soc_pkg.tvec_size = TH2_ACC_PORT_NUM; 424 425 _tdm->_core_data.rule__same_port_min = TH2_LR_VBS_LEN; 426 _tdm->_core_data.rule__prox_port_min = TH2_VBS_MIN_SPACING; 427 428 for (index=0; index<TH2_NUM_PM_MOD; index++) { 429 _tdm->_chip_data.soc_pkg.soc_vars.th2.pm_encap_type[index] = (_tdm->_chip_data.soc_pkg.state[index*TH2_NUM_PM_LNS]==PORT_STATE__LINERATE_HG||_tdm->_chip_data.soc_pkg.state[index]==PORT_STATE__OVERSUB_HG)?(999):(998); 430 } 431 _tdm->_chip_data.soc_pkg.pmap=(int **) TDM_ALLOC((_tdm->_chip_data.soc_pkg.pmap_num_modules)*sizeof(int *), "portmod_map_l1"); 432 for (index=0; index<(_tdm->_chip_data.soc_pkg.pmap_num_modules); index++) { 433 _tdm->_chip_data.soc_pkg.pmap[index]=(int *) TDM_ALLOC((_tdm->_chip_data.soc_pkg.pmap_num_lanes)*sizeof(int), "portmod_map_l2"); 434 TDM_MSET(_tdm->_chip_data.soc_pkg.pmap[index],(_tdm->_chip_data.soc_pkg.num_ext_ports),_tdm->_chip_data.soc_pkg.pmap_num_lanes); 435 } 436 /* Pipe 0 calendar group */ 437 _tdm->_chip_data.cal_0.cal_main=(int *) TDM_ALLOC((_tdm->_chip_data.cal_0.cal_len)*sizeof(int), "TDM inst 0 main calendar"); 438 TDM_MSET(_tdm->_chip_data.cal_0.cal_main,(_tdm->_chip_data.soc_pkg.num_ext_ports),_tdm->_chip_data.cal_0.cal_len); 439 _tdm->_chip_data.cal_0.cal_grp=(int **) TDM_ALLOC((_tdm->_chip_data.cal_0.grp_num+2)*sizeof(int *), "TDM inst 0 groups"); 440 for (index=0; index<(_tdm->_chip_data.cal_0.grp_num); index++) { 441 _tdm->_chip_data.cal_0.cal_grp[index]=(int *) TDM_ALLOC((_tdm->_chip_data.cal_0.grp_len)*sizeof(int), "TDM inst 0 group calendars"); 442 TDM_MSET(_tdm->_chip_data.cal_0.cal_grp[index],(_tdm->_chip_data.soc_pkg.num_ext_ports),_tdm->_chip_data.cal_0.grp_len); 443 } 444 _tdm->_chip_data.cal_0.cal_grp[SHAPING_GRP_IDX_0]=(int *) TDM_ALLOC((SHAPING_GRP_LEN)*sizeof(int), "TDM inst 0 shaping calendars"); 445 TDM_MSET(_tdm->_chip_data.cal_0.cal_grp[SHAPING_GRP_IDX_0],(_tdm->_chip_data.soc_pkg.num_ext_ports),SHAPING_GRP_LEN); 446 _tdm->_chip_data.cal_0.cal_grp[SHAPING_GRP_IDX_1]=(int *) TDM_ALLOC((SHAPING_GRP_LEN)*sizeof(int), "TDM inst 0 shaping calendars"); 447 TDM_MSET(_tdm->_chip_data.cal_0.cal_grp[SHAPING_GRP_IDX_1],(_tdm->_chip_data.soc_pkg.num_ext_ports),SHAPING_GRP_LEN); 448 /* Pipe 1 calendar group */ 449 _tdm->_chip_data.cal_1.cal_main=(int *) TDM_ALLOC((_tdm->_chip_data.cal_1.cal_len)*sizeof(int), "TDM inst 1 main calendar"); 450 TDM_MSET(_tdm->_chip_data.cal_1.cal_main,(_tdm->_chip_data.soc_pkg.num_ext_ports),_tdm->_chip_data.cal_1.cal_len); 451 _tdm->_chip_data.cal_1.cal_grp=(int **) TDM_ALLOC((_tdm->_chip_data.cal_1.grp_num+2)*sizeof(int *), "TDM inst 1 groups"); 452 for (index=0; index<(_tdm->_chip_data.cal_1.grp_num); index++) { 453 _tdm->_chip_data.cal_1.cal_grp[index]=(int *) TDM_ALLOC((_tdm->_chip_data.cal_1.grp_len)*sizeof(int), "TDM inst 1 group calendars"); 454 TDM_MSET(_tdm->_chip_data.cal_1.cal_grp[index],(_tdm->_chip_data.soc_pkg.num_ext_ports),_tdm->_chip_data.cal_1.grp_len); 455 } 456 _tdm->_chip_data.cal_1.cal_grp[SHAPING_GRP_IDX_0]=(int *) TDM_ALLOC((SHAPING_GRP_LEN)*sizeof(int), "TDM inst 1 shaping calendars"); 457 TDM_MSET(_tdm->_chip_data.cal_1.cal_grp[SHAPING_GRP_IDX_0],(_tdm->_chip_data.soc_pkg.num_ext_ports),SHAPING_GRP_LEN); 458 _tdm->_chip_data.cal_1.cal_grp[SHAPING_GRP_IDX_1]=(int *) TDM_ALLOC((SHAPING_GRP_LEN)*sizeof(int), "TDM inst 1 shaping calendars"); 459 TDM_MSET(_tdm->_chip_data.cal_1.cal_grp[SHAPING_GRP_IDX_1],(_tdm->_chip_data.soc_pkg.num_ext_ports),SHAPING_GRP_LEN); 460 /* Pipe 2 calendar group */ 461 _tdm->_chip_data.cal_2.cal_main=(int *) TDM_ALLOC((_tdm->_chip_data.cal_2.cal_len)*sizeof(int), "TDM inst 2 main calendar"); 462 TDM_MSET(_tdm->_chip_data.cal_2.cal_main,(_tdm->_chip_data.soc_pkg.num_ext_ports),_tdm->_chip_data.cal_2.cal_len); 463 _tdm->_chip_data.cal_2.cal_grp=(int **) TDM_ALLOC((_tdm->_chip_data.cal_2.grp_num+2)*sizeof(int *), "TDM inst 2 groups"); 464 for (index=0; index<(_tdm->_chip_data.cal_2.grp_num); index++) { 465 _tdm->_chip_data.cal_2.cal_grp[index]=(int *) TDM_ALLOC((_tdm->_chip_data.cal_2.grp_len)*sizeof(int), "TDM inst 2 group calendars"); 466 TDM_MSET(_tdm->_chip_data.cal_2.cal_grp[index],(_tdm->_chip_data.soc_pkg.num_ext_ports),_tdm->_chip_data.cal_2.grp_len); 467 } 468 _tdm->_chip_data.cal_2.cal_grp[SHAPING_GRP_IDX_0]=(int *) TDM_ALLOC((SHAPING_GRP_LEN)*sizeof(int), "TDM inst 2 shaping calendars"); 469 TDM_MSET(_tdm->_chip_data.cal_2.cal_grp[SHAPING_GRP_IDX_0],(_tdm->_chip_data.soc_pkg.num_ext_ports),SHAPING_GRP_LEN); 470 _tdm->_chip_data.cal_2.cal_grp[SHAPING_GRP_IDX_1]=(int *) TDM_ALLOC((SHAPING_GRP_LEN)*sizeof(int), "TDM inst 2 shaping calendars"); 471 TDM_MSET(_tdm->_chip_data.cal_2.cal_grp[SHAPING_GRP_IDX_1],(_tdm->_chip_data.soc_pkg.num_ext_ports),SHAPING_GRP_LEN); 472 /* Pipe 3 calendar group */ 473 _tdm->_chip_data.cal_3.cal_main=(int *) TDM_ALLOC((_tdm->_chip_data.cal_3.cal_len)*sizeof(int), "TDM inst 3 main calendar"); 474 TDM_MSET(_tdm->_chip_data.cal_3.cal_main,(_tdm->_chip_data.soc_pkg.num_ext_ports),_tdm->_chip_data.cal_3.cal_len); 475 _tdm->_chip_data.cal_3.cal_grp=(int **) TDM_ALLOC((_tdm->_chip_data.cal_3.grp_num+2)*sizeof(int *), "TDM inst 3 groups"); 476 for (index=0; index<(_tdm->_chip_data.cal_3.grp_num); index++) { 477 _tdm->_chip_data.cal_3.cal_grp[index]=(int *) TDM_ALLOC((_tdm->_chip_data.cal_3.grp_len)*sizeof(int), "TDM inst 3 group calendars"); 478 TDM_MSET(_tdm->_chip_data.cal_3.cal_grp[index],(_tdm->_chip_data.soc_pkg.num_ext_ports),_tdm->_chip_data.cal_3.grp_len); 479 } 480 _tdm->_chip_data.cal_3.cal_grp[SHAPING_GRP_IDX_0]=(int *) TDM_ALLOC((SHAPING_GRP_LEN)*sizeof(int), "TDM inst 3 shaping calendars"); 481 TDM_MSET(_tdm->_chip_data.cal_3.cal_grp[SHAPING_GRP_IDX_0],(_tdm->_chip_data.soc_pkg.num_ext_ports),SHAPING_GRP_LEN); 482 _tdm->_chip_data.cal_3.cal_grp[SHAPING_GRP_IDX_1]=(int *) TDM_ALLOC((SHAPING_GRP_LEN)*sizeof(int), "TDM inst 3 shaping calendars"); 483 TDM_MSET(_tdm->_chip_data.cal_3.cal_grp[SHAPING_GRP_IDX_1],(_tdm->_chip_data.soc_pkg.num_ext_ports),SHAPING_GRP_LEN); 484 /* Pipe 0 calendar group MMU mirror */ 485 _tdm->_chip_data.cal_4.cal_main=(int *) TDM_ALLOC((_tdm->_chip_data.cal_4.cal_len)*sizeof(int), "TDM inst 0 mirror calendar"); 486 TDM_MSET(_tdm->_chip_data.cal_4.cal_main,(_tdm->_chip_data.soc_pkg.num_ext_ports),_tdm->_chip_data.cal_4.cal_len); 487 /* Pipe 1 calendar group MMU mirror */ 488 _tdm->_chip_data.cal_5.cal_main=(int *) TDM_ALLOC((_tdm->_chip_data.cal_5.cal_len)*sizeof(int), "TDM inst 1 mirror calendar"); 489 TDM_MSET(_tdm->_chip_data.cal_5.cal_main,(_tdm->_chip_data.soc_pkg.num_ext_ports),_tdm->_chip_data.cal_5.cal_len); 490 /* Pipe 2 calendar group MMU mirror */ 491 _tdm->_chip_data.cal_6.cal_main=(int *) TDM_ALLOC((_tdm->_chip_data.cal_6.cal_len)*sizeof(int), "TDM inst 2 mirror calendar"); 492 TDM_MSET(_tdm->_chip_data.cal_6.cal_main,(_tdm->_chip_data.soc_pkg.num_ext_ports),_tdm->_chip_data.cal_6.cal_len); 493 /* Pipe 3 calendar group MMU mirror */ 494 _tdm->_chip_data.cal_7.cal_main=(int *) TDM_ALLOC((_tdm->_chip_data.cal_7.cal_len)*sizeof(int), "TDM inst 3 mirror calendar"); 495 TDM_MSET(_tdm->_chip_data.cal_7.cal_main,(_tdm->_chip_data.soc_pkg.num_ext_ports),_tdm->_chip_data.cal_7.cal_len); 496 497 for (index=(TH2_NUM_EXT_PORTS-1); index>0; index--) { 498 _tdm->_chip_data.soc_pkg.state[index]=_tdm->_chip_data.soc_pkg.state[index-1]; 499 } 500 501 return ( _tdm->_chip_exec[TDM_CHIP_EXEC__TRANSCRIPTION]( _tdm ) ); 502 } 503 504 505 /** 506 @name: tdm_th2_post 507 @param: 508 */ 509 int 510 tdm_th2_post( tdm_mod_t *_tdm ) 511 { 512 _tdm->_chip_data.soc_pkg.soc_vars.th2.pipe_start+=64; 513 _tdm->_chip_data.soc_pkg.soc_vars.th2.pipe_end+=64; 514 515 return (_tdm->_chip_data.soc_pkg.soc_vars.th2.pipe_end>TH2_NUM_EXT_PORTS)?(PASS):( _tdm->_chip_exec[TDM_CHIP_EXEC__INGRESS_WRAP]( _tdm ) ); 516 }