tdm_th_main.c (23014B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * $All Rights Reserved.$ 7 * 8 * TDM chip main functions 9 */ 10 #ifdef _TDM_STANDALONE 11 #include <tdm_top.h> 12 #else 13 #include <soc/tdm/core/tdm_top.h> 14 #endif 15 16 /* #ifdef _TDM_DB_STACK 17 size_t stack_size = 0; 18 #endif */ 19 20 /** 21 @name: tdm_th_corereq 22 @param: 23 24 Allocate memory for core data execute request to core executive 25 */ 26 int 27 tdm_th_corereq( tdm_mod_t *_tdm ) 28 { 29 _tdm->_core_data.vars_pkg.cal_id=_tdm->_core_data.vars_pkg.pipe; 30 31 return ( _tdm->_core_exec[TDM_CORE_EXEC__INIT]( _tdm ) ); 32 } 33 34 35 /** 36 @name: tdm_th_scheduler_wrap_pipe 37 @param: 38 39 Code wrapper for ingress TDM scheduling 40 */ 41 int 42 tdm_th_scheduler_wrap_pipe( tdm_mod_t *_tdm ) 43 { 44 int iter, idx1=0, idx2=0, ethernet_encap=BOOL_TRUE; 45 int param_cal_len=0, param_lr_limit=0, param_ancl_num=0, 46 param_clk_freq; 47 48 _tdm->_core_data.vars_pkg.pipe=(_tdm->_chip_data.soc_pkg.soc_vars.th.pipe_start/32); 49 if (_tdm->_core_data.vars_pkg.pipe>3) { 50 TDM_ERROR1("Invalid pipe ID - %0d\n",_tdm->_core_data.vars_pkg.pipe); 51 return (TDM_EXEC_CHIP_SIZE+1); 52 } 53 tdm_th_parse_pipe(_tdm); 54 for (iter=0; iter<TDM_AUX_SIZE; iter++) { 55 _tdm->_core_data.vars_pkg.lr_buffer[iter]=TH_NUM_EXT_PORTS; 56 _tdm->_core_data.vars_pkg.os_buffer[iter]=TH_NUM_EXT_PORTS; 57 } 58 for (iter=(_tdm->_chip_data.soc_pkg.soc_vars.th.pipe_start-1); iter<(_tdm->_chip_data.soc_pkg.soc_vars.th.pipe_end); iter++) { 59 if ( (_tdm->_chip_data.soc_pkg.state[iter]==PORT_STATE__LINERATE)||(_tdm->_chip_data.soc_pkg.state[iter]==PORT_STATE__LINERATE_HG) ) { 60 if (idx1<TDM_AUX_SIZE){ 61 _tdm->_core_data.vars_pkg.lr_buffer[idx1++]=(iter+1); 62 } 63 if (idx1>32){ 64 TDM_PRINT2("WARNING: Pipe %d, line rate queue overflow, port %d may have been skipped.\n", _tdm->_core_data.vars_pkg.pipe, (iter+1)); 65 } 66 } 67 else if ( (_tdm->_chip_data.soc_pkg.state[iter]==PORT_STATE__OVERSUB)||(_tdm->_chip_data.soc_pkg.state[iter]==PORT_STATE__OVERSUB_HG) ) { 68 if (idx2<TDM_AUX_SIZE){ 69 _tdm->_core_data.vars_pkg.os_buffer[idx2++]=(iter+1); 70 } 71 if (idx2>32){ 72 TDM_PRINT2("WARNING: Pipe %d, oversub queue overflow, port %d may have been skipped.\n", _tdm->_core_data.vars_pkg.pipe, (iter+1)); 73 } 74 } 75 } 76 if ( (_tdm->_chip_data.soc_pkg.soc_vars.th.mgmt_pm_hg==BOOL_TRUE) && 77 (_tdm->_core_data.vars_pkg.pipe==1||_tdm->_core_data.vars_pkg.pipe==2) && 78 ( (_tdm->_core_data.vars_pkg.lr_buffer[0]!=TH_NUM_EXT_PORTS&&_tdm->_chip_data.soc_pkg.clk_freq>=MIN_HG_FREQ)|| 79 (_tdm->_core_data.vars_pkg.lr_buffer[0]==TH_NUM_EXT_PORTS) ) ) { 80 _tdm->_chip_data.soc_pkg.soc_vars.th.higig_mgmt=BOOL_TRUE; 81 } 82 else { 83 _tdm->_chip_data.soc_pkg.soc_vars.th.higig_mgmt=BOOL_FALSE; 84 } 85 for (iter=0; iter<TDM_AUX_SIZE; iter++) { 86 if (_tdm->_core_data.vars_pkg.lr_buffer[iter]!=TH_NUM_EXT_PORTS) { 87 TDM_PUSH(_tdm->_core_data.vars_pkg.lr_buffer[iter],TDM_CORE_EXEC__ENCAP_SCAN,ethernet_encap); 88 if (!ethernet_encap) { 89 break; 90 } 91 } 92 if (_tdm->_core_data.vars_pkg.os_buffer[iter]!=TH_NUM_EXT_PORTS) { 93 TDM_PUSH(_tdm->_core_data.vars_pkg.os_buffer[iter],TDM_CORE_EXEC__ENCAP_SCAN,ethernet_encap); 94 if (!ethernet_encap) { 95 break; 96 } 97 } 98 } 99 param_clk_freq = _tdm->_chip_data.soc_pkg.clk_freq; 100 if ((_tdm->_chip_data.soc_pkg.soc_vars.th.higig_mgmt==BOOL_FALSE)&&(ethernet_encap) && 101 (_tdm->_chip_data.soc_pkg.soc_vars.th.cal_hg_en==BOOL_FALSE) ) { 102 switch (param_clk_freq) { 103 case TH_CLK_950MHZ: param_cal_len = TH_LEN_950MHZ_EN; break; 104 case TH_CLK_850MHZ: param_cal_len = TH_LEN_850MHZ_EN; break; 105 case TH_CLK_765MHZ: param_cal_len = TH_LEN_765MHZ_EN; break; 106 case TH_CLK_672MHZ: param_cal_len = TH_LEN_672MHZ_EN; break; 107 case TH_CLK_645MHZ: param_cal_len = TH_LEN_645MHZ_EN; break; 108 case TH_CLK_545MHZ: param_cal_len = TH_LEN_545MHZ_EN; break; 109 default: 110 TDM_PRINT1("Invalid frequency - %0dMHz not supported\n",param_clk_freq); 111 return 0; 112 break; 113 } 114 } 115 else { 116 switch (param_clk_freq) { 117 case TH_CLK_950MHZ: param_cal_len = TH_LEN_950MHZ_HG; break; 118 case TH_CLK_850MHZ: param_cal_len = TH_LEN_850MHZ_HG; break; 119 case TH_CLK_765MHZ: param_cal_len = TH_LEN_765MHZ_HG; break; 120 case TH_CLK_672MHZ: param_cal_len = TH_LEN_672MHZ_HG; break; 121 case TH_CLK_645MHZ: param_cal_len = TH_LEN_645MHZ_HG; break; 122 case TH_CLK_545MHZ: param_cal_len = TH_LEN_545MHZ_HG; break; 123 default: 124 TDM_PRINT1("Invalid frequency - %0dMHz not supported\n",param_clk_freq); 125 return 0; 126 break; 127 } 128 } 129 param_ancl_num = TH_ACC_PORT_NUM; 130 param_lr_limit = param_cal_len - param_ancl_num; 131 132 _tdm->_chip_data.soc_pkg.tvec_size = param_ancl_num; 133 _tdm->_chip_data.soc_pkg.lr_idx_limit = param_lr_limit; 134 135 return ( _tdm->_chip_exec[TDM_CHIP_EXEC__COREREQ]( _tdm ) ); 136 } 137 138 139 /** 140 @name: tdm_th_scheduler_wrap 141 @param: 142 143 Code wrapper for ingress TDM scheduling 144 */ 145 int 146 tdm_th_scheduler_wrap( tdm_mod_t *_tdm ) 147 { 148 int pipe_id, result=PASS; 149 150 /* TDM_PRINT_STACK_SIZE("tdm_th_scheduler_wrap"); */ 151 152 for (pipe_id=0; pipe_id<4; pipe_id++){ 153 result = tdm_th_scheduler_wrap_pipe(_tdm); 154 if (result!=PASS){ 155 break; 156 } 157 } 158 159 return result; 160 } 161 162 163 /** 164 @name: tdm_th_pmap_transcription 165 @param: 166 167 For Tomahawk BCM56960 168 Transcription algorithm for generating port module mapping 169 */ 170 int 171 tdm_th_pmap_transcription( tdm_mod_t *_tdm ) 172 { 173 int i, j, port_lanenum, last_port=TH_NUM_EXT_PORTS; 174 int phy_lo, phy_hi, pm_lane_num, bcm_config_check=PASS; 175 176 /* initialize pmap */ 177 for (i=0; i<TH_NUM_PHY_PM; i++) { 178 for (j=0; j<TH_NUM_PM_LNS; j++) { 179 _tdm->_chip_data.soc_pkg.pmap[i][j]=TH_NUM_EXT_PORTS; 180 } 181 } 182 /* Set combination state */ 183 for (i=1; i<=TH_NUM_PHY_PORTS; i++){ 184 if(_tdm->_chip_data.soc_pkg.speed[i]>=SPEED_40G){ 185 switch(_tdm->_chip_data.soc_pkg.speed[i]/1000){ 186 case 106: 187 case 100: 188 port_lanenum = 4; break; 189 case 53 : 190 case 50 : 191 port_lanenum = 2; break; 192 case 42 : 193 case 40 : 194 port_lanenum = 2; break; 195 default: 196 port_lanenum = 0; break; 197 } 198 for (j=1; j<port_lanenum; j++){ 199 if ((i+j)<=TH_NUM_PHY_PORTS){ 200 _tdm->_chip_data.soc_pkg.state[i+j-1] = PORT_STATE__COMBINE; 201 } 202 else{ 203 break; 204 } 205 } 206 } 207 else if ( (_tdm->_chip_data.soc_pkg.speed[i]/1000)==20 || (_tdm->_chip_data.soc_pkg.speed[i]/1000)==21 ){ 208 if (_tdm->_chip_data.soc_pkg.speed[i+1]==SPEED_0 && (i+1)<=TH_NUM_PHY_PORTS ){ 209 _tdm->_chip_data.soc_pkg.state[i] = PORT_STATE__DISABLED; 210 } 211 } 212 } 213 /* Port transcription */ 214 for (i=1; i<=TH_NUM_PHY_PORTS; i+=TH_NUM_PM_LNS) { 215 if (_tdm->_chip_data.soc_pkg.speed[i]>SPEED_0) { 216 for (j=0; j<TH_NUM_PM_LNS; j++) { 217 switch (_tdm->_chip_data.soc_pkg.state[i+j-1]) { 218 case PORT_STATE__LINERATE: 219 case PORT_STATE__OVERSUB: 220 case PORT_STATE__LINERATE_HG: 221 case PORT_STATE__OVERSUB_HG: 222 _tdm->_chip_data.soc_pkg.pmap[(i-1)/TH_NUM_PM_LNS][j]=(i+j); 223 last_port=(i+j); 224 break; 225 case PORT_STATE__COMBINE: 226 _tdm->_chip_data.soc_pkg.pmap[(i-1)/TH_NUM_PM_LNS][j]=last_port; 227 break; 228 default: 229 _tdm->_chip_data.soc_pkg.pmap[(i-1)/TH_NUM_PM_LNS][j]=TH_NUM_EXT_PORTS; 230 break; 231 } 232 } 233 /* tri mode x_xx */ 234 if (_tdm->_chip_data.soc_pkg.speed[i]>_tdm->_chip_data.soc_pkg.speed[i+2]&&_tdm->_chip_data.soc_pkg.speed[i+2]==_tdm->_chip_data.soc_pkg.speed[i+3]&&_tdm->_chip_data.soc_pkg.speed[i+2]!=SPEED_0&&_tdm->_chip_data.soc_pkg.speed[i]>=SPEED_40G) { 235 _tdm->_chip_data.soc_pkg.pmap[(i-1)/TH_NUM_PM_LNS][1] = _tdm->_chip_data.soc_pkg.pmap[(i-1)/TH_NUM_PM_LNS][2]; 236 _tdm->_chip_data.soc_pkg.pmap[(i-1)/TH_NUM_PM_LNS][2] = _tdm->_chip_data.soc_pkg.pmap[(i-1)/TH_NUM_PM_LNS][0]; 237 } 238 /* tri mode xxx_ */ 239 else if (_tdm->_chip_data.soc_pkg.speed[i]==_tdm->_chip_data.soc_pkg.speed[i+1]&&_tdm->_chip_data.soc_pkg.speed[i]<_tdm->_chip_data.soc_pkg.speed[i+2]&&_tdm->_chip_data.soc_pkg.speed[i]!=SPEED_0&&_tdm->_chip_data.soc_pkg.speed[i+2]>=SPEED_40G) { 240 _tdm->_chip_data.soc_pkg.pmap[(i-1)/TH_NUM_PM_LNS][2] = _tdm->_chip_data.soc_pkg.pmap[(i-1)/TH_NUM_PM_LNS][1]; 241 _tdm->_chip_data.soc_pkg.pmap[(i-1)/TH_NUM_PM_LNS][1] = _tdm->_chip_data.soc_pkg.pmap[(i-1)/TH_NUM_PM_LNS][3]; 242 } 243 /* dual mode x_x_ */ 244 else if (_tdm->_chip_data.soc_pkg.speed[i]!=_tdm->_chip_data.soc_pkg.speed[i+1]&&_tdm->_chip_data.soc_pkg.speed[i]==_tdm->_chip_data.soc_pkg.speed[i+2]&&_tdm->_chip_data.soc_pkg.speed[i]>=SPEED_40G) { 245 _tdm->_chip_data.soc_pkg.pmap[(i-1)/TH_NUM_PM_LNS][1] = _tdm->_chip_data.soc_pkg.pmap[(i-1)/TH_NUM_PM_LNS][3]; 246 _tdm->_chip_data.soc_pkg.pmap[(i-1)/TH_NUM_PM_LNS][2] = _tdm->_chip_data.soc_pkg.pmap[(i-1)/TH_NUM_PM_LNS][0]; 247 } 248 } 249 } 250 /* print port config after transcription */ 251 tdm_print_config( _tdm ); 252 253 /* Check if invalid port config exists */ 254 phy_lo = _tdm->_chip_data.soc_pkg.soc_vars.fp_port_lo; 255 phy_hi = _tdm->_chip_data.soc_pkg.soc_vars.fp_port_hi; 256 pm_lane_num= _tdm->_chip_data.soc_pkg.pmap_num_lanes; 257 for (i=phy_lo; i<=(phy_hi-pm_lane_num); i+=pm_lane_num) { 258 if (_tdm->_chip_data.soc_pkg.speed[i]==SPEED_0){ 259 for (j=1; j<pm_lane_num; j++) { 260 if (_tdm->_chip_data.soc_pkg.speed[i+j]>SPEED_0){ 261 bcm_config_check = FAIL; 262 break; 263 } 264 } 265 } 266 if (bcm_config_check==FAIL){ 267 TDM_ERROR8("Invalid port configuration, port [%3d, %3d, %3d, %3d], speed [%3dG, %3dG, %3dG, %3dG]\n", 268 i, i+1, i+2, i+3, 269 _tdm->_chip_data.soc_pkg.speed[i]/1000, 270 _tdm->_chip_data.soc_pkg.speed[i+1]/1000, 271 _tdm->_chip_data.soc_pkg.speed[i+2]/1000, 272 _tdm->_chip_data.soc_pkg.speed[i+3]/1000); 273 return FAIL; 274 } 275 } 276 277 return ( _tdm->_chip_exec[TDM_CHIP_EXEC__INGRESS_WRAP]( _tdm ) ); 278 } 279 280 281 /** 282 @name: tdm_th_init 283 @param: 284 */ 285 int 286 tdm_th_init( tdm_mod_t *_tdm ) 287 { 288 int index; 289 290 /* TDM_PRINT_STACK_SIZE("tdm_th_init"); */ 291 292 /* initialize chip/core parameters */ 293 _tdm->_chip_data.soc_pkg.pmap_num_modules = TH_NUM_PM_MOD; 294 _tdm->_chip_data.soc_pkg.pmap_num_lanes = TH_NUM_PM_LNS; 295 _tdm->_chip_data.soc_pkg.pm_num_phy_modules = TH_NUM_PHY_PM; 296 297 _tdm->_chip_data.soc_pkg.soc_vars.ovsb_token = TH_OVSB_TOKEN; 298 _tdm->_chip_data.soc_pkg.soc_vars.idl1_token = TH_IDL1_TOKEN; 299 _tdm->_chip_data.soc_pkg.soc_vars.idl2_token = TH_IDL2_TOKEN; 300 _tdm->_chip_data.soc_pkg.soc_vars.ancl_token = TH_ANCL_TOKEN; 301 _tdm->_chip_data.soc_pkg.soc_vars.fp_port_lo = 1; 302 _tdm->_chip_data.soc_pkg.soc_vars.fp_port_hi = TH_NUM_PHY_PORTS; 303 304 _tdm->_chip_data.cal_0.cal_len = TH_LR_VBS_LEN; 305 _tdm->_chip_data.cal_0.grp_num = TH_OS_VBS_GRP_NUM; 306 _tdm->_chip_data.cal_0.grp_len = TH_OS_VBS_GRP_LEN; 307 _tdm->_chip_data.cal_1.cal_len = TH_LR_VBS_LEN; 308 _tdm->_chip_data.cal_1.grp_num = TH_OS_VBS_GRP_NUM; 309 _tdm->_chip_data.cal_1.grp_len = TH_OS_VBS_GRP_LEN; 310 _tdm->_chip_data.cal_2.cal_len = TH_LR_VBS_LEN; 311 _tdm->_chip_data.cal_2.grp_num = TH_OS_VBS_GRP_NUM; 312 _tdm->_chip_data.cal_2.grp_len = TH_OS_VBS_GRP_LEN; 313 _tdm->_chip_data.cal_3.cal_len = TH_LR_VBS_LEN; 314 _tdm->_chip_data.cal_3.grp_num = TH_OS_VBS_GRP_NUM; 315 _tdm->_chip_data.cal_3.grp_len = TH_OS_VBS_GRP_LEN; 316 _tdm->_chip_data.cal_4.cal_len = TH_LR_VBS_LEN; 317 _tdm->_chip_data.cal_4.grp_num = TH_OS_VBS_GRP_NUM; 318 _tdm->_chip_data.cal_4.grp_len = TH_OS_VBS_GRP_LEN; 319 _tdm->_chip_data.cal_5.cal_len = TH_LR_VBS_LEN; 320 _tdm->_chip_data.cal_5.grp_num = TH_OS_VBS_GRP_NUM; 321 _tdm->_chip_data.cal_5.grp_len = TH_OS_VBS_GRP_LEN; 322 _tdm->_chip_data.cal_6.cal_len = TH_LR_VBS_LEN; 323 _tdm->_chip_data.cal_6.grp_num = TH_OS_VBS_GRP_NUM; 324 _tdm->_chip_data.cal_6.grp_len = TH_OS_VBS_GRP_LEN; 325 _tdm->_chip_data.cal_7.cal_len = TH_LR_VBS_LEN; 326 _tdm->_chip_data.cal_7.grp_num = TH_OS_VBS_GRP_NUM; 327 _tdm->_chip_data.cal_7.grp_len = TH_OS_VBS_GRP_LEN; 328 329 _tdm->_chip_data.soc_pkg.soc_vars.th.higig_mgmt=BOOL_FALSE; 330 _tdm->_chip_data.soc_pkg.soc_vars.th.cal_hg_en=BOOL_FALSE; 331 _tdm->_chip_data.soc_pkg.lr_idx_limit=LEN_850MHZ_EN; 332 _tdm->_chip_data.soc_pkg.tvec_size = TH_ACC_PORT_NUM; 333 _tdm->_chip_data.soc_pkg.soc_vars.th.pipe_start=1; 334 _tdm->_chip_data.soc_pkg.soc_vars.th.pipe_end=32; 335 336 _tdm->_core_data.vars_pkg.pipe = 0; 337 _tdm->_core_data.rule__same_port_min = TH_MIN_SPACING_SAME_PORT; 338 _tdm->_core_data.rule__prox_port_min = TH_MIN_SPACING_SISTER_PORT; 339 _tdm->_core_data.vmap_max_wid = TH_VMAP_MAX_WID; 340 _tdm->_core_data.vmap_max_len = TH_VMAP_MAX_LEN; 341 342 /* Chip: cal_hg_en */ 343 if (_tdm->_chip_data.soc_pkg.soc_vars.th.cal_universal_en==BOOL_TRUE){ 344 _tdm->_chip_data.soc_pkg.soc_vars.th.cal_hg_en=BOOL_TRUE; 345 } 346 /* Chip: encap */ 347 for (index=0; index<TH_NUM_PM_MOD; index++) { 348 _tdm->_chip_data.soc_pkg.soc_vars.th.pm_encap_type[index] = (_tdm->_chip_data.soc_pkg.state[index*TH_NUM_PM_LNS]==PORT_STATE__LINERATE_HG||_tdm->_chip_data.soc_pkg.state[index*TH_NUM_PM_LNS]==PORT_STATE__OVERSUB_HG)?(PM_ENCAP__HIGIG2):(PM_ENCAP__ETHRNT); 349 } 350 /* Chip: pmap */ 351 _tdm->_chip_data.soc_pkg.pmap=(int **) TDM_ALLOC((_tdm->_chip_data.soc_pkg.pmap_num_modules)*sizeof(int *), "portmod_map_l1"); 352 for (index=0; index<(_tdm->_chip_data.soc_pkg.pmap_num_modules); index++) { 353 _tdm->_chip_data.soc_pkg.pmap[index]=(int *) TDM_ALLOC((_tdm->_chip_data.soc_pkg.pmap_num_lanes)*sizeof(int), "portmod_map_l2"); 354 TDM_MSET(_tdm->_chip_data.soc_pkg.pmap[index],(_tdm->_chip_data.soc_pkg.num_ext_ports),_tdm->_chip_data.soc_pkg.pmap_num_lanes); 355 } 356 /* Chip: IDB Pipe 0 calendar group */ 357 _tdm->_chip_data.cal_0.cal_main=(int *) TDM_ALLOC((_tdm->_chip_data.cal_0.cal_len)*sizeof(int), "TDM inst 0 main calendar"); 358 TDM_MSET(_tdm->_chip_data.cal_0.cal_main,(_tdm->_chip_data.soc_pkg.num_ext_ports),_tdm->_chip_data.cal_0.cal_len); 359 _tdm->_chip_data.cal_0.cal_grp=(int **) TDM_ALLOC((_tdm->_chip_data.cal_0.grp_num)*sizeof(int *), "TDM inst 0 groups"); 360 for (index=0; index<(_tdm->_chip_data.cal_0.grp_num); index++) { 361 _tdm->_chip_data.cal_0.cal_grp[index]=(int *) TDM_ALLOC((_tdm->_chip_data.cal_0.grp_len)*sizeof(int), "TDM inst 0 group calendars"); 362 TDM_MSET(_tdm->_chip_data.cal_0.cal_grp[index],(_tdm->_chip_data.soc_pkg.num_ext_ports),_tdm->_chip_data.cal_0.grp_len); 363 } 364 /* Chip: IDB Pipe 1 calendar group */ 365 _tdm->_chip_data.cal_1.cal_main=(int *) TDM_ALLOC((_tdm->_chip_data.cal_1.cal_len)*sizeof(int), "TDM inst 1 main calendar"); 366 TDM_MSET(_tdm->_chip_data.cal_1.cal_main,(_tdm->_chip_data.soc_pkg.num_ext_ports),_tdm->_chip_data.cal_1.cal_len); 367 _tdm->_chip_data.cal_1.cal_grp=(int **) TDM_ALLOC((_tdm->_chip_data.cal_1.grp_num)*sizeof(int *), "TDM inst 1 groups"); 368 for (index=0; index<(_tdm->_chip_data.cal_1.grp_num); index++) { 369 _tdm->_chip_data.cal_1.cal_grp[index]=(int *) TDM_ALLOC((_tdm->_chip_data.cal_1.grp_len)*sizeof(int), "TDM inst 1 group calendars"); 370 TDM_MSET(_tdm->_chip_data.cal_1.cal_grp[index],(_tdm->_chip_data.soc_pkg.num_ext_ports),_tdm->_chip_data.cal_1.grp_len); 371 } 372 /* Chip: IDB Pipe 2 calendar group */ 373 _tdm->_chip_data.cal_2.cal_main=(int *) TDM_ALLOC((_tdm->_chip_data.cal_2.cal_len)*sizeof(int), "TDM inst 2 main calendar"); 374 TDM_MSET(_tdm->_chip_data.cal_2.cal_main,(_tdm->_chip_data.soc_pkg.num_ext_ports),_tdm->_chip_data.cal_2.cal_len); 375 _tdm->_chip_data.cal_2.cal_grp=(int **) TDM_ALLOC((_tdm->_chip_data.cal_2.grp_num)*sizeof(int *), "TDM inst 2 groups"); 376 for (index=0; index<(_tdm->_chip_data.cal_2.grp_num); index++) { 377 _tdm->_chip_data.cal_2.cal_grp[index]=(int *) TDM_ALLOC((_tdm->_chip_data.cal_2.grp_len)*sizeof(int), "TDM inst 2 group calendars"); 378 TDM_MSET(_tdm->_chip_data.cal_2.cal_grp[index],(_tdm->_chip_data.soc_pkg.num_ext_ports),_tdm->_chip_data.cal_2.grp_len); 379 } 380 /* Chip: IDB Pipe 3 calendar group */ 381 _tdm->_chip_data.cal_3.cal_main=(int *) TDM_ALLOC((_tdm->_chip_data.cal_3.cal_len)*sizeof(int), "TDM inst 3 main calendar"); 382 TDM_MSET(_tdm->_chip_data.cal_3.cal_main,(_tdm->_chip_data.soc_pkg.num_ext_ports),_tdm->_chip_data.cal_3.cal_len); 383 _tdm->_chip_data.cal_3.cal_grp=(int **) TDM_ALLOC((_tdm->_chip_data.cal_3.grp_num)*sizeof(int *), "TDM inst 3 groups"); 384 for (index=0; index<(_tdm->_chip_data.cal_3.grp_num); index++) { 385 _tdm->_chip_data.cal_3.cal_grp[index]=(int *) TDM_ALLOC((_tdm->_chip_data.cal_3.grp_len)*sizeof(int), "TDM inst 3 group calendars"); 386 TDM_MSET(_tdm->_chip_data.cal_3.cal_grp[index],(_tdm->_chip_data.soc_pkg.num_ext_ports),_tdm->_chip_data.cal_3.grp_len); 387 } 388 /* Chip: MMU Pipe 0 calendar group */ 389 _tdm->_chip_data.cal_4.cal_main=(int *) TDM_ALLOC((_tdm->_chip_data.cal_4.cal_len)*sizeof(int), "TDM inst 0 main calendar"); 390 TDM_MSET(_tdm->_chip_data.cal_4.cal_main,(_tdm->_chip_data.soc_pkg.num_ext_ports),_tdm->_chip_data.cal_4.cal_len); 391 _tdm->_chip_data.cal_4.cal_grp=(int **) TDM_ALLOC((_tdm->_chip_data.cal_4.grp_num)*sizeof(int *), "TDM inst 0 groups"); 392 for (index=0; index<(_tdm->_chip_data.cal_4.grp_num); index++) { 393 _tdm->_chip_data.cal_4.cal_grp[index]=(int *) TDM_ALLOC((_tdm->_chip_data.cal_4.grp_len)*sizeof(int), "TDM inst 0 group calendars"); 394 TDM_MSET(_tdm->_chip_data.cal_4.cal_grp[index],(_tdm->_chip_data.soc_pkg.num_ext_ports),_tdm->_chip_data.cal_4.grp_len); 395 } 396 /* Chip: MMU Pipe 1 calendar group */ 397 _tdm->_chip_data.cal_5.cal_main=(int *) TDM_ALLOC((_tdm->_chip_data.cal_5.cal_len)*sizeof(int), "TDM inst 1 main calendar"); 398 TDM_MSET(_tdm->_chip_data.cal_5.cal_main,(_tdm->_chip_data.soc_pkg.num_ext_ports),_tdm->_chip_data.cal_5.cal_len); 399 _tdm->_chip_data.cal_5.cal_grp=(int **) TDM_ALLOC((_tdm->_chip_data.cal_5.grp_num)*sizeof(int *), "TDM inst 1 groups"); 400 for (index=0; index<(_tdm->_chip_data.cal_5.grp_num); index++) { 401 _tdm->_chip_data.cal_5.cal_grp[index]=(int *) TDM_ALLOC((_tdm->_chip_data.cal_5.grp_len)*sizeof(int), "TDM inst 1 group calendars"); 402 TDM_MSET(_tdm->_chip_data.cal_5.cal_grp[index],(_tdm->_chip_data.soc_pkg.num_ext_ports),_tdm->_chip_data.cal_5.grp_len); 403 } 404 /* Chip: MMU Pipe 2 calendar group */ 405 _tdm->_chip_data.cal_6.cal_main=(int *) TDM_ALLOC((_tdm->_chip_data.cal_6.cal_len)*sizeof(int), "TDM inst 2 main calendar"); 406 TDM_MSET(_tdm->_chip_data.cal_6.cal_main,(_tdm->_chip_data.soc_pkg.num_ext_ports),_tdm->_chip_data.cal_6.cal_len); 407 _tdm->_chip_data.cal_6.cal_grp=(int **) TDM_ALLOC((_tdm->_chip_data.cal_6.grp_num)*sizeof(int *), "TDM inst 2 groups"); 408 for (index=0; index<(_tdm->_chip_data.cal_6.grp_num); index++) { 409 _tdm->_chip_data.cal_6.cal_grp[index]=(int *) TDM_ALLOC((_tdm->_chip_data.cal_6.grp_len)*sizeof(int), "TDM inst 2 group calendars"); 410 TDM_MSET(_tdm->_chip_data.cal_6.cal_grp[index],(_tdm->_chip_data.soc_pkg.num_ext_ports),_tdm->_chip_data.cal_6.grp_len); 411 } 412 /* Chip: MMU Pipe 3 calendar group */ 413 _tdm->_chip_data.cal_7.cal_main=(int *) TDM_ALLOC((_tdm->_chip_data.cal_7.cal_len)*sizeof(int), "TDM inst 3 main calendar"); 414 TDM_MSET(_tdm->_chip_data.cal_7.cal_main,(_tdm->_chip_data.soc_pkg.num_ext_ports),_tdm->_chip_data.cal_7.cal_len); 415 _tdm->_chip_data.cal_7.cal_grp=(int **) TDM_ALLOC((_tdm->_chip_data.cal_7.grp_num)*sizeof(int *), "TDM inst 3 groups"); 416 for (index=0; index<(_tdm->_chip_data.cal_7.grp_num); index++) { 417 _tdm->_chip_data.cal_7.cal_grp[index]=(int *) TDM_ALLOC((_tdm->_chip_data.cal_7.grp_len)*sizeof(int), "TDM inst 3 group calendars"); 418 TDM_MSET(_tdm->_chip_data.cal_7.cal_grp[index],(_tdm->_chip_data.soc_pkg.num_ext_ports),_tdm->_chip_data.cal_7.grp_len); 419 } 420 /* Core: vmap */ 421 _tdm->_core_data.vmap=(unsigned short **) TDM_ALLOC((_tdm->_core_data.vmap_max_wid)*sizeof(unsigned short *), "vector_map_l1"); 422 for (index=0; index<(_tdm->_core_data.vmap_max_wid); index++) { 423 _tdm->_core_data.vmap[index]=(unsigned short *) TDM_ALLOC((_tdm->_core_data.vmap_max_len)*sizeof(unsigned short), "vector_map_l2"); 424 } 425 426 return ( _tdm->_chip_exec[TDM_CHIP_EXEC__TRANSCRIPTION]( _tdm ) ); 427 } 428 429 430 /** 431 @name: tdm_th_post 432 @param: 433 */ 434 int 435 tdm_th_post( tdm_mod_t *_tdm ) 436 { 437 /* TDM_PRINT_STACK_SIZE("tdm_th_post"); */ 438 439 _tdm->_chip_data.soc_pkg.soc_vars.th.pipe_start+=32; 440 _tdm->_chip_data.soc_pkg.soc_vars.th.pipe_end+=32; 441 442 if (_tdm->_chip_data.soc_pkg.soc_vars.th.pipe_end>128){ 443 TDM_SML_BAR 444 TDM_PRINT0("\nTDM: TDM algorithm is completed.\n\n"); 445 TDM_SML_BAR 446 447 /* TDM self-check */ 448 if (_tdm->_chip_data.soc_pkg.soc_vars.th.tdm_chk_en==BOOL_TRUE){ 449 _tdm->_chip_exec[TDM_CHIP_EXEC__CHECK](_tdm); 450 } 451 } 452 453 return PASS; 454 } 455 456 457 /** 458 @name: tdm_th_free 459 @param: 460 */ 461 int 462 tdm_th_free( tdm_mod_t *_tdm ) 463 { 464 int index; 465 /* Chip: pmap */ 466 for (index=0; index<(_tdm->_chip_data.soc_pkg.pmap_num_modules); index++) { 467 TDM_FREE(_tdm->_chip_data.soc_pkg.pmap[index]); 468 } 469 TDM_FREE(_tdm->_chip_data.soc_pkg.pmap); 470 /* Chip: IDB Pipe 0 calendar group */ 471 TDM_FREE(_tdm->_chip_data.cal_0.cal_main); 472 for (index=0; index<(_tdm->_chip_data.cal_0.grp_num); index++) { 473 TDM_FREE(_tdm->_chip_data.cal_0.cal_grp[index]); 474 } 475 TDM_FREE(_tdm->_chip_data.cal_0.cal_grp); 476 /* Chip: IDB Pipe 1 calendar group */ 477 TDM_FREE(_tdm->_chip_data.cal_1.cal_main); 478 for (index=0; index<(_tdm->_chip_data.cal_1.grp_num); index++) { 479 TDM_FREE(_tdm->_chip_data.cal_1.cal_grp[index]); 480 } 481 TDM_FREE(_tdm->_chip_data.cal_1.cal_grp); 482 /* Chip: IDB Pipe 2 calendar group */ 483 TDM_FREE(_tdm->_chip_data.cal_2.cal_main); 484 for (index=0; index<(_tdm->_chip_data.cal_2.grp_num); index++) { 485 TDM_FREE(_tdm->_chip_data.cal_2.cal_grp[index]); 486 } 487 TDM_FREE(_tdm->_chip_data.cal_2.cal_grp); 488 /* Chip: IDB Pipe 3 calendar group */ 489 TDM_FREE(_tdm->_chip_data.cal_3.cal_main); 490 for (index=0; index<(_tdm->_chip_data.cal_3.grp_num); index++) { 491 TDM_FREE(_tdm->_chip_data.cal_3.cal_grp[index]); 492 } 493 TDM_FREE(_tdm->_chip_data.cal_3.cal_grp); 494 /* Chip: MMU Pipe 0 calendar group */ 495 TDM_FREE(_tdm->_chip_data.cal_4.cal_main); 496 for (index=0; index<(_tdm->_chip_data.cal_4.grp_num); index++) { 497 TDM_FREE(_tdm->_chip_data.cal_4.cal_grp[index]); 498 } 499 TDM_FREE(_tdm->_chip_data.cal_4.cal_grp); 500 /* Chip: MMU Pipe 1 calendar group */ 501 TDM_FREE(_tdm->_chip_data.cal_5.cal_main); 502 for (index=0; index<(_tdm->_chip_data.cal_5.grp_num); index++) { 503 TDM_FREE(_tdm->_chip_data.cal_5.cal_grp[index]); 504 } 505 TDM_FREE(_tdm->_chip_data.cal_5.cal_grp); 506 /* Chip: MMU Pipe 2 calendar group */ 507 TDM_FREE(_tdm->_chip_data.cal_6.cal_main); 508 for (index=0; index<(_tdm->_chip_data.cal_6.grp_num); index++) { 509 TDM_FREE(_tdm->_chip_data.cal_6.cal_grp[index]); 510 } 511 TDM_FREE(_tdm->_chip_data.cal_6.cal_grp); 512 /* Chip: MMU Pipe 3 calendar group */ 513 TDM_FREE(_tdm->_chip_data.cal_7.cal_main); 514 for (index=0; index<(_tdm->_chip_data.cal_7.grp_num); index++) { 515 TDM_FREE(_tdm->_chip_data.cal_7.cal_grp[index]); 516 } 517 TDM_FREE(_tdm->_chip_data.cal_7.cal_grp); 518 /* Core: vmap */ 519 for (index=0; index<(_tdm->_core_data.vmap_max_wid); index++) { 520 TDM_FREE(_tdm->_core_data.vmap[index]); 521 } 522 TDM_FREE(_tdm->_core_data.vmap); 523 524 return PASS; 525 }