tdm_td2.c (242280B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: set_tdm.c 8 * Purpose: Derive TDM schedules 9 */ 10 11 /* -I $(VCS_HOME)/include */ 12 #include <shared/bsl.h> 13 #include <soc/debug.h> 14 #include <soc/cm.h> 15 #include <sal/core/alloc.h> 16 #define TDM_TD2_ALLOC(_nm,_t,_sz,_id) _t *_nm = (_t *)sal_alloc(sizeof(_t)*(_sz),_id) 17 #define TDM_TD2_FREE(_nm) sal_free(_nm) 18 #define TDM_TD2_MEMCPY(_s1,_s2,_sz) sal_memcpy(_s1,_s2,_sz) 19 20 /* number of physical ports plus CPU and loopback */ 21 #define TDM_TD2_NUM_EXT_PORTS 130 22 /* number of TSCs in chip */ 23 #define TDM_TD2_NUM_WC 32 24 25 /* pgw/mmu table oversubscription token */ 26 #define TDM_TD2_OVS_TOKEN (TDM_TD2_NUM_EXT_PORTS+1) 27 /* mmu table idle token */ 28 #define TDM_TD2_IDL_TOKEN (TDM_TD2_NUM_EXT_PORTS+2) 29 /* tsc transcription management port token */ 30 #define TDM_TD2_MGM_TOKEN (TDM_TD2_NUM_EXT_PORTS+3) 31 /* port scanning microsub token */ 32 #define TDM_TD2_U1G_TOKEN (TDM_TD2_NUM_EXT_PORTS+4) 33 34 #define TDM_TD2_TOKEN_CHECK(a) \ 35 if (a!=TDM_TD2_NUM_EXT_PORTS && \ 36 a!=TDM_TD2_OVS_TOKEN && \ 37 a!=TDM_TD2_IDL_TOKEN && \ 38 a!=TDM_TD2_MGM_TOKEN && \ 39 a!=TDM_TD2_U1G_TOKEN && \ 40 a!=0 && \ 41 a!=129) \ 42 43 /* mmu table accessory token */ 44 #define TDM_TD2_ACC_TOKEN (TDM_TD2_NUM_EXT_PORTS+5) 45 #define CMIC(a) { \ 46 mmu_tdm_tbl[a]=0; \ 47 LOG_VERBOSE(BSL_LS_SOC_TDM, \ 48 (BSL_META("CMIC\n"))); \ 49 break; \ 50 } 51 #define LPBK(a) { \ 52 mmu_tdm_tbl[a]=129; \ 53 LOG_VERBOSE(BSL_LS_SOC_TDM, \ 54 (BSL_META("LOOPBACK\n"))); \ 55 break; \ 56 } 57 #define ANCL(a) { \ 58 mmu_tdm_tbl[a]=TDM_TD2_IDL_TOKEN; \ 59 LOG_VERBOSE(BSL_LS_SOC_TDM, \ 60 (BSL_META("OPPORTUNISTIC\n"))); \ 61 break; \ 62 } 63 #define REFR(a) { \ 64 mmu_tdm_tbl[a]=TDM_TD2_NUM_EXT_PORTS; \ 65 LOG_VERBOSE(BSL_LS_SOC_TDM, \ 66 (BSL_META("IDLE\n"))); \ 67 break; \ 68 } 69 #define MM13(a) { \ 70 mmu_tdm_tbl[a]=13; \ 71 LOG_VERBOSE(BSL_LS_SOC_TDM, \ 72 (BSL_META("management phyport 13\n")));\ 73 break; \ 74 } 75 #define MM14(a) { \ 76 mmu_tdm_tbl[a]=14; \ 77 LOG_VERBOSE(BSL_LS_SOC_TDM, \ 78 (BSL_META("management phyport 14\n")));\ 79 break; \ 80 } 81 #define MM15(a) { \ 82 mmu_tdm_tbl[a]=15; \ 83 LOG_VERBOSE(BSL_LS_SOC_COMMON, \ 84 (BSL_META("management phyport 15\n")));\ 85 break; \ 86 } 87 #define MM16(a) { \ 88 mmu_tdm_tbl[a]=16; \ 89 LOG_VERBOSE(BSL_LS_SOC_TDM, \ 90 (BSL_META("management phyport 16\n")));\ 91 break; \ 92 } 93 94 #define TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0 0 95 #define TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1 1 96 #define TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT 2 97 #define TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK 3 98 #define TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_QGP_PORT 4 99 #define TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_RESERVED 6 100 #define TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT 7 101 102 #define TDM_TD2_TRUE 1 103 #define TDM_TD2_PASS 1 104 #define TDM_TD2_FALSE 0 105 #define TDM_TD2_FAIL 0 106 107 enum tdm_td2_port_speed { 108 TDM_TD2_SPEED_0=0, 109 TDM_TD2_SPEED_10M=10, 110 TDM_TD2_SPEED_20M=20, 111 TDM_TD2_SPEED_25M=25, 112 TDM_TD2_SPEED_33M=33, 113 TDM_TD2_SPEED_40M=40, 114 TDM_TD2_SPEED_50M=50, 115 TDM_TD2_SPEED_100M=100, 116 TDM_TD2_SPEED_100M_FX=101, 117 TDM_TD2_SPEED_120M=120, 118 TDM_TD2_SPEED_400M=400, 119 TDM_TD2_SPEED_1G=1000, 120 TDM_TD2_SPEED_1G_FX=1001, 121 TDM_TD2_SPEED_1p2G=1200, 122 TDM_TD2_SPEED_2G=2000, 123 TDM_TD2_SPEED_2p5G=2500, 124 TDM_TD2_SPEED_4G=4000, 125 TDM_TD2_SPEED_5G=5000, 126 TDM_TD2_SPEED_7p5G=7500, 127 TDM_TD2_SPEED_10G=10000, 128 TDM_TD2_SPEED_10G_DUAL=10001, 129 TDM_TD2_SPEED_10G_XAUI=10002, 130 TDM_TD2_SPEED_12G=12000, 131 TDM_TD2_SPEED_12p5G=12500, 132 TDM_TD2_SPEED_13G=13000, 133 TDM_TD2_SPEED_15G=15000, 134 TDM_TD2_SPEED_16G=16000, 135 TDM_TD2_SPEED_20G=20000, 136 TDM_TD2_SPEED_21G=21000, 137 TDM_TD2_SPEED_21G_DUAL=21010, 138 TDM_TD2_SPEED_24G=24000, 139 TDM_TD2_SPEED_25G=25000, 140 TDM_TD2_SPEED_30G=30000, 141 TDM_TD2_SPEED_40G=40000, 142 TDM_TD2_SPEED_42G=40005, 143 TDM_TD2_SPEED_50G=50000, 144 TDM_TD2_SPEED_75G=75000, 145 TDM_TD2_SPEED_82G=82000, 146 TDM_TD2_SPEED_100G=100000, 147 TDM_TD2_SPEED_106G=106000, 148 TDM_TD2_SPEED_120G=120000, 149 TDM_TD2_SPEED_127G=127000 150 }; 151 152 /** 153 @name: TSC_port_transcription 154 @param: int[][], enum, int[] 155 156 Physical port transcriber for tsc subports into physical port numbers 157 158 40G - xxxx 159 20G - xx 160 xx 161 10G - x 162 x 163 x 164 x 165 1X0G - xxxx_xxxx_xxxx 166 */ 167 168 void TSC_port_transcription(int wc_array[TDM_TD2_NUM_WC][4], enum tdm_td2_port_speed speed[TDM_TD2_NUM_EXT_PORTS], int port_state_array[128]) 169 { 170 int i,j,last_port=TDM_TD2_NUM_EXT_PORTS,tsc_bool; 171 /*char tmp_str[16];*/ 172 /*sprintf (cmd_str, "soc setmem -index %x %s {", index->d, addr);*/ 173 174 /* automatically regulate management port configuration */ 175 if (wc_array[3][0]==TDM_TD2_MGM_TOKEN) 176 { 177 if (speed[13]==TDM_TD2_SPEED_10G || speed[13]==TDM_TD2_SPEED_10G_XAUI) 178 { 179 speed[14]=TDM_TD2_SPEED_0; 180 speed[15]=TDM_TD2_SPEED_0; 181 speed[16]=TDM_TD2_SPEED_0; 182 port_state_array[12] = 1; 183 port_state_array[13] = 0; 184 port_state_array[14] = 0; 185 port_state_array[15] = 0; 186 } 187 else if (speed[13]==TDM_TD2_SPEED_2p5G || speed[14]==TDM_TD2_SPEED_2p5G || speed[15]==TDM_TD2_SPEED_2p5G || speed[16]==TDM_TD2_SPEED_2p5G) 188 { 189 speed[13]=TDM_TD2_SPEED_2p5G; 190 speed[14]=TDM_TD2_SPEED_2p5G; 191 speed[15]=TDM_TD2_SPEED_2p5G; 192 speed[16]=TDM_TD2_SPEED_2p5G; 193 port_state_array[12] = 1; 194 port_state_array[13] = 1; 195 port_state_array[14] = 1; 196 port_state_array[15] = 1; 197 } 198 else 199 { 200 speed[13]=TDM_TD2_SPEED_1G; 201 speed[14]=TDM_TD2_SPEED_1G; 202 speed[15]=TDM_TD2_SPEED_1G; 203 speed[16]=TDM_TD2_SPEED_1G; 204 port_state_array[12] = 1; 205 port_state_array[13] = 1; 206 port_state_array[14] = 1; 207 port_state_array[15] = 1; 208 } 209 } 210 211 for (i=0; i<32; i++) { 212 for (j=0; j<4; j++) { 213 if (wc_array[i][j]!=TDM_TD2_MGM_TOKEN) { 214 wc_array[i][j]=TDM_TD2_NUM_EXT_PORTS; 215 } 216 } 217 } 218 for (i=1; i<(TDM_TD2_NUM_EXT_PORTS-1); i+=4) { 219 tsc_bool=TDM_TD2_FALSE; 220 for (j=0; j<4; j++) { 221 if (port_state_array[i-1+j]==1||port_state_array[i-1+j]==2) { 222 tsc_bool=TDM_TD2_TRUE; 223 } 224 } 225 /* set management port tokens if enabled */ 226 if (((i-1)/4==3) && wc_array[(i-1)/4][0]==TDM_TD2_MGM_TOKEN) { 227 if (speed[i] == speed[i+1]) { 228 /* wc_array[(i-1)/4][0] = TDM_TD2_MGM_TOKEN;*/ 229 wc_array[(i-1)/4][1] = TDM_TD2_MGM_TOKEN; 230 wc_array[(i-1)/4][2] = TDM_TD2_MGM_TOKEN; 231 wc_array[(i-1)/4][3] = TDM_TD2_MGM_TOKEN; 232 } 233 else { 234 /* wc_array[(i-1)/4][0] = TDM_TD2_MGM_TOKEN;*/ 235 wc_array[(i-1)/4][1] = TDM_TD2_NUM_EXT_PORTS; 236 wc_array[(i-1)/4][2] = TDM_TD2_NUM_EXT_PORTS; 237 wc_array[(i-1)/4][3] = TDM_TD2_NUM_EXT_PORTS; 238 } 239 } 240 else if (tsc_bool) { 241 if (speed[i] <= TDM_TD2_SPEED_42G || port_state_array[i-1]==0) { 242 for (j=0; j<4; j++) { 243 switch (port_state_array[i-1+j]) { 244 case 1: case 2: 245 wc_array[(i-1)/4][j] = (i+j); 246 last_port=(i+j); 247 break; 248 case 3: 249 wc_array[(i-1)/4][j] = last_port; 250 break; 251 default: 252 wc_array[(i-1)/4][j] = TDM_TD2_NUM_EXT_PORTS; 253 break; 254 } 255 } 256 /*tri mode x_xx 257 if (speed[i]>speed[i+2] && speed[i+2]==speed[i+3] && speed[i+2]!=TDM_TD2_SPEED_0) { 258 wc_array[(i-1)/4][1] = wc_array[(i-1)/4][2]; 259 wc_array[(i-1)/4][2] = wc_array[(i-1)/4][0]; 260 }*/ 261 /*tri mode xxx_ 262 else if (speed[i]==speed[i+1] && speed[i]<speed[i+2] && speed[i]!=TDM_TD2_SPEED_0) { 263 wc_array[(i-1)/4][2] = wc_array[(i-1)/4][1]; 264 wc_array[(i-1)/4][1] = wc_array[(i-1)/4][3]; 265 }*/ 266 /*dual mode 267 else if (speed[i]!=speed[i+1] && speed[i]==speed[i+2] && speed[i]!=TDM_TD2_SPEED_0) { 268 wc_array[(i-1)/4][1] = wc_array[(i-1)/4][3]; 269 wc_array[(i-1)/4][2] = wc_array[(i-1)/4][0]; 270 }*/ 271 } 272 else if ( (i+10)<(TDM_TD2_NUM_EXT_PORTS-1) ) { 273 if ( ((speed[i] == TDM_TD2_SPEED_100G) || 274 (speed[i] == TDM_TD2_SPEED_106G)) 275 && port_state_array[i+10] != 3) { 276 wc_array[(i-1)/4][0] = i; 277 wc_array[(i-1)/4][1] = i; 278 wc_array[(i-1)/4][2] = i; 279 wc_array[(i-1)/4][3] = i; 280 wc_array[(i+3)/4][0] = i; 281 wc_array[(i+3)/4][1] = i; 282 wc_array[(i+3)/4][2] = i; 283 wc_array[(i+3)/4][3] = i; 284 wc_array[(i+7)/4][0] = i; 285 wc_array[(i+7)/4][1] = i; 286 wc_array[(i+7)/4][2] = TDM_TD2_NUM_EXT_PORTS; 287 wc_array[(i+7)/4][3] = TDM_TD2_NUM_EXT_PORTS; 288 } 289 else if (speed[i] == TDM_TD2_SPEED_100G || 290 speed[i] == TDM_TD2_SPEED_106G || 291 speed[i] == TDM_TD2_SPEED_120G || 292 speed[i] == TDM_TD2_SPEED_127G) { 293 wc_array[(i-1)/4][0] = i; 294 wc_array[(i-1)/4][1] = i; 295 wc_array[(i-1)/4][2] = i; 296 wc_array[(i-1)/4][3] = i; 297 wc_array[(i+3)/4][0] = i; 298 wc_array[(i+3)/4][1] = i; 299 wc_array[(i+3)/4][2] = i; 300 wc_array[(i+3)/4][3] = i; 301 wc_array[(i+7)/4][0] = i; 302 wc_array[(i+7)/4][1] = i; 303 wc_array[(i+7)/4][2] = i; 304 wc_array[(i+7)/4][3] = i; 305 } 306 i+=8; 307 } 308 } 309 } 310 } 311 312 313 /** 314 @name: print_port 315 @param: int[][] 316 317 Prints summary of all warp cores and their associated subports 318 */ 319 320 void print_port(int wc_array[TDM_TD2_NUM_WC][4], enum tdm_td2_port_speed speed[TDM_TD2_NUM_EXT_PORTS], int state[128]) 321 { 322 int i,j,port_token,phy_port,lgc_port=0; 323 324 LOG_VERBOSE(BSL_LS_SOC_TDM, 325 (BSL_META("TDM: Portmap Summary\n"))); 326 for(i=0; i<TDM_TD2_NUM_WC; i++) { 327 LOG_VERBOSE(BSL_LS_SOC_TDM, 328 (BSL_META("\tPM_Inst [%02d]\n"), i)); 329 for (j=0; j<4; j++) { 330 LOG_VERBOSE(BSL_LS_SOC_TDM, 331 (BSL_META("\t\t\tPM_Lane [%0d]\t"),j)); 332 port_token = wc_array[i][j]; 333 if (port_token==TDM_TD2_NUM_EXT_PORTS) { 334 LOG_VERBOSE(BSL_LS_SOC_TDM, 335 (BSL_META("->\tP_Port [---]\t ->\tL_Port [---] \n"))); 336 } 337 else { 338 if (port_token==TDM_TD2_MGM_TOKEN){ 339 phy_port = i*4+j+1; 340 } 341 else { 342 phy_port = port_token; 343 } 344 LOG_VERBOSE(BSL_LS_SOC_TDM, 345 (BSL_META("->\tP_Port [%03d]\t ->\tL_Port [%03d]\t"), phy_port, (++lgc_port) )); 346 LOG_VERBOSE(BSL_LS_SOC_TDM, 347 (BSL_META("->\tSpeed [%3d Gbps]\t"), speed[phy_port]/1000 )); 348 switch(state[phy_port-1]){ 349 case 1: 350 LOG_VERBOSE(BSL_LS_SOC_TDM,(BSL_META("[LNRT]\n"))); 351 break; 352 case 2: 353 LOG_VERBOSE(BSL_LS_SOC_TDM,(BSL_META("[OVSB]\n"))); 354 break; 355 case 3: 356 LOG_VERBOSE(BSL_LS_SOC_TDM,(BSL_META("[ COM]\n"))); 357 break; 358 default: 359 LOG_VERBOSE(BSL_LS_SOC_TDM,(BSL_META("\n"))); 360 break; 361 } 362 } 363 } 364 } 365 } 366 367 368 /** 369 @name: which_tsc 370 @param: int 371 372 Returns the TSC to which the input port belongs given pointer to transcribed TSC matrix 373 */ 374 int which_tsc(unsigned char port, int tsc[TDM_TD2_NUM_WC][4]) { 375 376 int i, j, which=TDM_TD2_NUM_EXT_PORTS; 377 378 for (i=0; i<TDM_TD2_NUM_WC; i++) { 379 for (j=0; j<4; j++) { 380 if (tsc[i][j]==port) { 381 which=i; 382 } 383 } 384 if (which!=TDM_TD2_NUM_EXT_PORTS) { 385 break; 386 } 387 } 388 389 return which; 390 391 } 392 393 394 /** 395 @name: check_type_2 396 @param: unsigned char, int[][] 397 398 Complex returns port type (unique lanes) in the TSC of the input port 399 */ 400 int check_type_2(unsigned char port, int tsc[TDM_TD2_NUM_WC][4]) 401 { 402 int i, j, tmp=TDM_TD2_NUM_EXT_PORTS, cnt=1, tsc_arr[4], tsc_inst=which_tsc(port,tsc); 403 404 tsc_arr[0]=tsc[tsc_inst][0]; 405 tsc_arr[1]=tsc[tsc_inst][1]; 406 tsc_arr[2]=tsc[tsc_inst][2]; 407 tsc_arr[3]=tsc[tsc_inst][3]; 408 /* Bubble sort array into ascending order */ 409 for (i=0; i<4; i++) { 410 for (j=0; j<4-i; j++) { 411 if ((j+1)<4) { 412 if (tsc_arr[j] > tsc_arr[j+1]) { 413 tmp=tsc_arr[j]; 414 tsc_arr[j]=tsc_arr[j+1]; 415 tsc_arr[j+1]=tmp; 416 } 417 } 418 } 419 } 420 /* Count transitions */ 421 for (i=1; i<4; i++) { 422 if (tsc_arr[i]!=TDM_TD2_NUM_EXT_PORTS && tsc_arr[i]!=tsc_arr[i-1]) { 423 cnt++; 424 } 425 } 426 427 return cnt; 428 429 } 430 431 432 /** 433 @name: fill_ovs 434 @param: 435 436 Fills and sorts oversub speed buckets 437 */ 438 439 int fill_ovs(int *z, enum tdm_td2_port_speed speed[TDM_TD2_NUM_EXT_PORTS], int tsc[TDM_TD2_NUM_WC][4], int ovs_buf[64], int bucket1[16], int *z11, int bucket2[16], int *z22, int bucket3[16], int *z33, int bucket4[16], int *z44) 440 { 441 int i, j, k, l, n=0, tsc_id=0, tsc_stack[4], tsc_fetch_cnt=0, slice_factor; 442 int m, port_exist; 443 444 tsc_stack[0]=ovs_buf[*z]; ovs_buf[*z]=TDM_TD2_NUM_EXT_PORTS; 445 for (i=1; i<4; i++) { 446 tsc_stack[i]=TDM_TD2_NUM_EXT_PORTS; 447 } 448 tsc_id=which_tsc(tsc_stack[0],tsc); 449 if (tsc_id <TDM_TD2_NUM_WC ){ 450 for (i=0; i<4; i++) { 451 if (tsc[tsc_id][i]!=tsc_stack[0] && tsc[tsc_id][i]!=TDM_TD2_NUM_EXT_PORTS && speed[tsc[tsc_id][i]]==speed[tsc_stack[0]]) { 452 for (j=1; j<=*z; j++) { 453 if (ovs_buf[j]==tsc[tsc_id][i]) { 454 if (++tsc_fetch_cnt<4) { 455 tsc_stack[tsc_fetch_cnt]=tsc[tsc_id][i]; 456 for (k=j; k<*z; k++) { 457 ovs_buf[k]=ovs_buf[k+1]; 458 } 459 } 460 } 461 } 462 } 463 } 464 } 465 while (tsc_fetch_cnt<4 && ++n<4) { 466 for (l=1; l<=*z; l++) { 467 if (((check_type_2(ovs_buf[l],tsc))+tsc_fetch_cnt)<4) { 468 tsc_id = which_tsc(ovs_buf[l],tsc); 469 for (i=0; i<4; i++) { 470 if (tsc[tsc_id][i]!=TDM_TD2_NUM_EXT_PORTS && speed[tsc[tsc_id][i]]==speed[ovs_buf[l]]) { 471 for (j=1; j<=*z; j++) { 472 if (ovs_buf[j]==tsc[tsc_id][i]) { 473 if ((tsc_fetch_cnt+1)<4){ 474 port_exist = TDM_TD2_FALSE; 475 for (m=0; m<4; m++) { 476 if (tsc_stack[m]==tsc[tsc_id][i]) { 477 port_exist = TDM_TD2_TRUE; 478 break; 479 } 480 } 481 if (port_exist==TDM_TD2_FALSE) { 482 tsc_stack[++tsc_fetch_cnt]=tsc[tsc_id][i]; 483 for (k=j; k<*z; k++) { 484 ovs_buf[k]=ovs_buf[k+1]; 485 } 486 } 487 } 488 } 489 } 490 } 491 } 492 break; 493 } 494 } 495 } 496 (*z)-=(1+tsc_fetch_cnt); 497 switch (tsc_fetch_cnt) { 498 case 1: 499 slice_factor=8; 500 break; 501 case 2: 502 case 3: 503 slice_factor=4; 504 break; 505 default: 506 slice_factor=16; 507 break; 508 } 509 510 while (bucket1[*z11]!=TDM_TD2_NUM_EXT_PORTS && (*z11)<15) (*z11)++; 511 while (bucket2[*z22]!=TDM_TD2_NUM_EXT_PORTS && (*z22)<15) (*z22)++; 512 while (bucket3[*z33]!=TDM_TD2_NUM_EXT_PORTS && (*z33)<15) (*z33)++; 513 while (bucket4[*z44]!=TDM_TD2_NUM_EXT_PORTS && (*z44)<15) (*z44)++; 514 if ( (*z11+(tsc_fetch_cnt*slice_factor)) < 16 ) { 515 for (i=0; i<4; i++) { 516 if (tsc_stack[i]!=TDM_TD2_NUM_EXT_PORTS) { 517 bucket1[*z11+(i*slice_factor)] = tsc_stack[i]; 518 } 519 } 520 (*z11)++; 521 } 522 else if ( (*z22+(tsc_fetch_cnt*slice_factor)) < 16 ) { 523 for (i=0; i<4; i++) { 524 if (tsc_stack[i]!=TDM_TD2_NUM_EXT_PORTS) { 525 bucket2[*z22+(i*slice_factor)] = tsc_stack[i]; 526 } 527 } 528 (*z22)++; 529 } 530 else if ( (*z33+(tsc_fetch_cnt*slice_factor)) < 16 ) { 531 for (i=0; i<4; i++) { 532 if (tsc_stack[i]!=TDM_TD2_NUM_EXT_PORTS) { 533 bucket3[*z33+(i*slice_factor)] = tsc_stack[i]; 534 } 535 } 536 (*z33)++; 537 } 538 else if ( (*z44+(tsc_fetch_cnt*slice_factor)) < 16 ) { 539 for (i=0; i<4; i++) { 540 if (tsc_stack[i]!=TDM_TD2_NUM_EXT_PORTS) { 541 bucket4[*z44+(i*slice_factor)] = tsc_stack[i]; 542 } 543 } 544 (*z44)++; 545 } 546 else { 547 return TDM_TD2_FAIL; 548 } 549 550 return TDM_TD2_PASS; 551 552 } 553 554 /** 555 @name: check_ex_bw_en 556 @param: 557 558 Return true if extra CPU/LOOPBACK bandwidth is enabled, otherwise return false. 559 */ 560 static 561 int check_ex_bw_en(int mmu_tdm_tbl[256], enum tdm_td2_port_speed speed[TDM_TD2_NUM_EXT_PORTS], int ex_bw_type, int pipe) 562 { 563 int i, result=TDM_TD2_FALSE, 564 pipe_x_en=TDM_TD2_FALSE, pipe_y_en=TDM_TD2_FALSE, 565 full_ovsb_pipe=TDM_TD2_FALSE; 566 567 if ((pipe == 0) && (ex_bw_type == 1 || ex_bw_type == 3)) { 568 pipe_x_en = TDM_TD2_TRUE; 569 } 570 if ((pipe == 1) && (ex_bw_type == 2 || ex_bw_type == 3)) { 571 pipe_y_en = TDM_TD2_TRUE; 572 } 573 /* condition 1: pipe only contains oversubscription ports */ 574 if (pipe_x_en == TDM_TD2_TRUE || pipe_y_en == TDM_TD2_TRUE) { 575 full_ovsb_pipe = TDM_TD2_TRUE; 576 for (i=0; i<256; i++) { 577 TDM_TD2_TOKEN_CHECK(mmu_tdm_tbl[i]) { 578 if (mmu_tdm_tbl[i] != TDM_TD2_ACC_TOKEN){ 579 full_ovsb_pipe = TDM_TD2_FALSE; 580 break; 581 } 582 } 583 } 584 } 585 586 if (full_ovsb_pipe == TDM_TD2_TRUE) { 587 result = TDM_TD2_TRUE; 588 } 589 return result; 590 } 591 592 /** 593 @name: parse_mmu_tdm_tbl_ex 594 @param: 595 596 Converts accessory tokens and prints debug form summary of pipe mmu table 597 */ 598 static 599 void parse_mmu_tdm_tbl_ex(int bw, int mgmt_bw, int mmu_tdm_tbl[256], int mmu_tdm_ovs_1[16], int mmu_tdm_ovs_2[16], int mmu_tdm_ovs_3[16], int mmu_tdm_ovs_4[16], int pipe, int ex_bw_en) 600 { 601 int j, idx=0, dist_inc=0, slot_dist=0, slot_cnt=0; 602 int param_cal_len, param_acc_num, 603 param_token_cpu, param_token_lpbk, param_token_ancl, 604 param_cpu_num=0, param_lpbk_num=0, 605 param_mgmt_num=0, param_ancl_num=0, 606 param_cpu_space_min; 607 const char *pipe_name; 608 609 param_token_cpu = 0; 610 param_token_lpbk = 129; 611 param_token_ancl = TDM_TD2_IDL_TOKEN; 612 param_cpu_space_min = 11; 613 614 switch (pipe) { 615 case 0: pipe_name = "X-PIPE"; break; 616 case 1: pipe_name = "Y-PIPE"; break; 617 default: 618 pipe_name = "Unknown-PIPE"; 619 LOG_ERROR(BSL_LS_SOC_TDM, 620 (BSL_META("TDM: _____ERROR: INVALID Pipe ID %d\n"), pipe)); 621 break; 622 } 623 /* set standard ACCESSORY bandwidth */ 624 switch (bw) { 625 case 960: 626 param_cal_len = 200; 627 param_acc_num = 8; 628 if (pipe == 0) { 629 if (mgmt_bw == 0) { 630 param_cpu_num = 3; 631 param_lpbk_num = 0; 632 param_mgmt_num = 0; 633 param_ancl_num = 5; 634 } else if (mgmt_bw == 4) { 635 param_cpu_num = 1; 636 param_lpbk_num = 0; 637 param_mgmt_num = 4; 638 param_ancl_num = 3; 639 } else { 640 LOG_VERBOSE(BSL_LS_SOC_TDM, 641 (BSL_META("TDM: _____WARNING: UNSUPPORTED Management Port type %d\n"), mgmt_bw)); 642 } 643 } else { 644 param_cpu_num = 0; 645 param_lpbk_num = 3; 646 param_mgmt_num = 0; 647 param_ancl_num = 5; 648 } 649 break; 650 case 720: 651 param_cal_len = 160; 652 param_acc_num = 10; 653 if (pipe == 0) { 654 if (mgmt_bw == 0) { 655 param_cpu_num = 5; 656 param_lpbk_num = 0; 657 param_mgmt_num = 0; 658 param_ancl_num = 5; 659 } else if (mgmt_bw == 4) { 660 param_cpu_num = 3; 661 param_lpbk_num = 0; 662 param_mgmt_num = 4; 663 param_ancl_num = 3; 664 } else if (mgmt_bw == 1) { 665 param_cpu_num = 1; 666 param_lpbk_num = 0; 667 param_mgmt_num = 4; 668 param_ancl_num = 5; 669 } else { 670 LOG_VERBOSE(BSL_LS_SOC_TDM, 671 (BSL_META("TDM: _____WARNING: UNSUPPORTED Management Port type %d\n"), mgmt_bw)); 672 } 673 } else { 674 param_cpu_num = 0; 675 param_lpbk_num = 5; 676 param_mgmt_num = 0; 677 param_ancl_num = 5; 678 } 679 break; 680 case 640: 681 param_cal_len = 136; 682 param_acc_num = 8; 683 if (pipe == 0) { 684 if (mgmt_bw == 0) { 685 param_cpu_num = 3; 686 param_lpbk_num = 0; 687 param_mgmt_num = 0; 688 param_ancl_num = 5; 689 } else if (mgmt_bw == 4) { 690 param_cpu_num = 1; 691 param_lpbk_num = 0; 692 param_mgmt_num = 4; 693 param_ancl_num = 3; 694 } else { 695 LOG_VERBOSE(BSL_LS_SOC_TDM, 696 (BSL_META("TDM: _____WARNING: UNSUPPORTED Management Port type %d\n"), mgmt_bw)); 697 } 698 } else { 699 param_cpu_num = 0; 700 param_mgmt_num = 0; 701 param_lpbk_num = 3; 702 param_ancl_num = 5; 703 } 704 break; 705 case 480: 706 param_cal_len = 106; 707 param_acc_num = 10; 708 if (pipe == 0) { 709 if (mgmt_bw == 0) { 710 param_cpu_num = 5; 711 param_lpbk_num = 0; 712 param_mgmt_num = 0; 713 param_ancl_num = 5; 714 } else if (mgmt_bw == 4) { 715 param_cpu_num = 3; 716 param_lpbk_num = 0; 717 param_mgmt_num = 4; 718 param_ancl_num = 3; 719 } else if (mgmt_bw == 1) { 720 param_cpu_num = 1; 721 param_lpbk_num = 0; 722 param_mgmt_num = 4; 723 param_ancl_num = 5; 724 } else { 725 LOG_VERBOSE(BSL_LS_SOC_TDM, 726 (BSL_META("TDM: _____WARNING: UNSUPPORTED Management Port type %d\n"), mgmt_bw)); 727 } 728 } else { 729 param_cpu_num = 0; 730 param_lpbk_num = 5; 731 param_mgmt_num = 0; 732 param_ancl_num = 5; 733 } 734 break; 735 default: 736 param_cal_len = 200; 737 param_acc_num = 8; 738 if (pipe == 0) { 739 param_cpu_num = 4; 740 param_lpbk_num = 0; 741 param_mgmt_num = 0; 742 param_ancl_num = 4; 743 } else { 744 param_cpu_num = 0; 745 param_lpbk_num = 4; 746 param_mgmt_num = 0; 747 param_ancl_num = 4; 748 } 749 break; 750 } 751 /* set extra CPU bandwidth */ 752 if ((pipe == 0) && (ex_bw_en == TDM_TD2_TRUE)) { 753 switch (bw) { 754 case 960: param_cpu_num = 16; break; 755 case 720: param_cpu_num = 12; break; 756 case 640: param_cpu_num = 10; break; 757 case 480: param_cpu_num = 8; break; 758 default: break; 759 } 760 } 761 /* set extra LOOPBACK bandwidth */ 762 if ((pipe == 1) && (ex_bw_en == TDM_TD2_TRUE)) { 763 switch (bw) { 764 case 960: param_lpbk_num = 16; break; 765 case 720: param_lpbk_num = 12; break; 766 case 640: param_lpbk_num = 10; break; 767 case 480: param_lpbk_num = 8; break; 768 default: break; 769 } 770 } 771 if ((pipe == 0) && (ex_bw_en== TDM_TD2_TRUE)){ 772 LOG_VERBOSE(BSL_LS_SOC_TDM, 773 (BSL_META("TDM: Pipe X, extra CPU bandwidth allocated\n"))); 774 } else if ((pipe == 1) && (ex_bw_en== TDM_TD2_TRUE)){ 775 LOG_VERBOSE(BSL_LS_SOC_TDM, 776 (BSL_META("TDM: Pipe Y, extra LOOPBACK bandwidth allocated\n"))); 777 } 778 LOG_VERBOSE(BSL_LS_SOC_TDM, 779 (BSL_META("\t acc_slot_num %d (original)\n"), param_acc_num)); 780 LOG_VERBOSE(BSL_LS_SOC_TDM, 781 (BSL_META("\t cpu_slot_num %d\n"), param_cpu_num)); 782 LOG_VERBOSE(BSL_LS_SOC_TDM, 783 (BSL_META("\t mgmt_slot_num %d\n"), param_mgmt_num)); 784 LOG_VERBOSE(BSL_LS_SOC_TDM, 785 (BSL_META("\t lpbk_slot_num %d\n"), param_lpbk_num)); 786 LOG_VERBOSE(BSL_LS_SOC_TDM, 787 (BSL_META("\t ancl_slot_num %d\n\n"), param_ancl_num)); 788 /* recycle ACCESSORY slots */ 789 for (j=0; j<256; j++) { 790 if (mmu_tdm_tbl[j] == TDM_TD2_ACC_TOKEN) { 791 mmu_tdm_tbl[j] = TDM_TD2_OVS_TOKEN; 792 } 793 } 794 /* X-PIPE */ 795 if (pipe == 0) { 796 /* allocate CPU slots */ 797 if (param_cpu_num > 0) { 798 slot_cnt = 0; 799 slot_dist = param_cal_len/param_cpu_num; 800 if (slot_dist<param_cpu_space_min){ 801 slot_dist = param_cpu_space_min; 802 LOG_VERBOSE(BSL_LS_SOC_TDM, 803 (BSL_META("TDM WARNING: CPU bandwidth %dG exceeds %dG under core bandwidth %dG\n"), 804 ((param_cpu_num*25)/10), 805 (((param_cal_len/param_cpu_space_min)*25)/10), 806 bw)); 807 } 808 dist_inc = (slot_dist>0) ? (slot_dist-1) : (1); 809 idx = slot_dist; 810 for (j=idx; j<param_cal_len && j<256; j++) { 811 if (mmu_tdm_tbl[j] == TDM_TD2_OVS_TOKEN || 812 mmu_tdm_tbl[j] == TDM_TD2_NUM_EXT_PORTS) { 813 mmu_tdm_tbl[j] = param_token_cpu; 814 LOG_VERBOSE(BSL_LS_SOC_TDM, 815 (BSL_META("TDM: Allocate %2d-th CPU slot at index %03d\n"), 816 slot_cnt+1, j)); 817 slot_cnt++; 818 j = (j+dist_inc)%param_cal_len; 819 if (slot_cnt == param_cpu_num) { 820 break; 821 } 822 } 823 } 824 LOG_VERBOSE(BSL_LS_SOC_TDM, 825 (BSL_META("TDM: Total slots allocated for CPU is %d\n\n"), 826 slot_cnt)); 827 } 828 /* allocate MANAGEMENT slots */ 829 if (param_mgmt_num > 0) { 830 slot_cnt = 0; 831 slot_dist = param_cal_len/param_mgmt_num; 832 dist_inc = (slot_dist>0) ? (slot_dist-1) : (1); 833 idx = idx/2+1; 834 if (mgmt_bw == 4) { 835 for (j=idx; j<param_cal_len && j<256; j++){ 836 if (mmu_tdm_tbl[j] == TDM_TD2_OVS_TOKEN || 837 mmu_tdm_tbl[j] == TDM_TD2_NUM_EXT_PORTS) { 838 switch (slot_cnt) { 839 case 0: mmu_tdm_tbl[j] = 13; break; 840 case 1: mmu_tdm_tbl[j] = 14; break; 841 case 2: mmu_tdm_tbl[j] = 15; break; 842 case 3: mmu_tdm_tbl[j] = 16; break; 843 default: break; 844 } 845 LOG_VERBOSE(BSL_LS_SOC_TDM, 846 (BSL_META("TDM: Allocate %d-th MGMT slot at index %03d with port %3d\n"), 847 slot_cnt+1, j, mmu_tdm_tbl[j])); 848 slot_cnt++; 849 j = (j+dist_inc)%param_cal_len; 850 if (slot_cnt == param_mgmt_num) { 851 break; 852 } 853 } 854 } 855 } else if (mgmt_bw == 1) { 856 if (bw == 720 || bw == 480) { 857 for (j=idx; j<param_cal_len && j<256; j++){ 858 if (mmu_tdm_tbl[j] == TDM_TD2_OVS_TOKEN || 859 mmu_tdm_tbl[j] == TDM_TD2_NUM_EXT_PORTS) { 860 switch (slot_cnt) { 861 case 0: 862 case 1: 863 case 2: 864 case 3: mmu_tdm_tbl[j] = 13; break; 865 default: break; 866 } 867 LOG_VERBOSE(BSL_LS_SOC_TDM, 868 (BSL_META("TDM: Allocate %d-th MGMT slot at index %03d with port %3d\n"), 869 slot_cnt+1, j, mmu_tdm_tbl[j])); 870 slot_cnt++; 871 j = (j+dist_inc)%param_cal_len; 872 if (slot_cnt == param_mgmt_num) { 873 break; 874 } 875 } 876 } 877 } else if (bw == 960 || bw == 640) { 878 LOG_VERBOSE(BSL_LS_SOC_TDM, 879 (BSL_META("TDM WARNING: UNSUPPORTED management port configuration\n"))); 880 } 881 } 882 LOG_VERBOSE(BSL_LS_SOC_TDM, 883 (BSL_META("TDM: Total slots allocated for MGMT is %d\n\n"), 884 slot_cnt)); 885 } 886 /* allocate ANCL slots */ 887 if (param_ancl_num > 0) { 888 slot_cnt = 0; 889 slot_dist= param_cal_len/param_ancl_num; 890 dist_inc = (slot_dist>0) ? (slot_dist-1) : (1); 891 idx = slot_dist; 892 for (j=idx; j<param_cal_len && j<256; j++) { 893 if (mmu_tdm_tbl[j] == TDM_TD2_OVS_TOKEN || 894 mmu_tdm_tbl[j] == TDM_TD2_NUM_EXT_PORTS) { 895 mmu_tdm_tbl[j] = param_token_ancl; 896 LOG_VERBOSE(BSL_LS_SOC_TDM, 897 (BSL_META("TDM: Allocate %d-th ANCL slot at index %03d\n"), 898 slot_cnt+1, j)); 899 slot_cnt++; 900 j = (j+dist_inc)%param_cal_len; 901 if (slot_cnt == param_ancl_num) { 902 break; 903 } 904 } 905 } 906 LOG_VERBOSE(BSL_LS_SOC_TDM, 907 (BSL_META("TDM: Total slots allocated for ANCL is %d\n\n"), 908 slot_cnt)); 909 } 910 } 911 /* Y-PIPE */ 912 else if (pipe == 1) { 913 /* allocate LOOPBACK slots */ 914 if (param_lpbk_num > 0) { 915 slot_cnt = 0; 916 slot_dist = param_cal_len/param_lpbk_num; 917 dist_inc = (slot_dist>0) ? (slot_dist-1) : (1); 918 idx = slot_dist; 919 for (j=idx; j<param_cal_len && j<256; j++) { 920 if (mmu_tdm_tbl[j] == TDM_TD2_OVS_TOKEN || 921 mmu_tdm_tbl[j] == TDM_TD2_NUM_EXT_PORTS) { 922 mmu_tdm_tbl[j] = param_token_lpbk; 923 LOG_VERBOSE(BSL_LS_SOC_TDM, 924 (BSL_META("TDM: Allocate %0d-th LOOPBACK slot at index %03d\n"), 925 slot_cnt+1, j)); 926 slot_cnt++; 927 j = (j+dist_inc)%param_cal_len; 928 } 929 } 930 LOG_VERBOSE(BSL_LS_SOC_TDM, 931 (BSL_META("TDM: Total slots allocated for LOOPBACK is %d\n\n"), 932 slot_cnt)); 933 } 934 /* allocate ANCL slots */ 935 if (param_ancl_num > 0) { 936 slot_cnt = 0; 937 slot_dist = param_cal_len/param_ancl_num; 938 dist_inc = (slot_dist>0) ? (slot_dist-1) : (1); 939 idx = idx/2+1; 940 for (j=idx; j<param_cal_len && j<256; j++) { 941 if (mmu_tdm_tbl[j] == TDM_TD2_OVS_TOKEN || 942 mmu_tdm_tbl[j] == TDM_TD2_NUM_EXT_PORTS) { 943 mmu_tdm_tbl[j] = param_token_ancl; 944 LOG_VERBOSE(BSL_LS_SOC_TDM, 945 (BSL_META("TDM: Allocate %d-th ANCL slot at index %03d\n"), 946 slot_cnt+1, j)); 947 slot_cnt++; 948 j = (j+dist_inc)%param_cal_len; 949 } 950 } 951 LOG_VERBOSE(BSL_LS_SOC_TDM, 952 (BSL_META("TDM: Total slots allocated for ANCL is %d\n\n"), 953 slot_cnt)); 954 } 955 } 956 957 /* print MMU main calendar */ 958 for (j=0; j<256; j++) { 959 LOG_VERBOSE(BSL_LS_SOC_TDM, 960 (BSL_META("TDM: %s, MMU TDM TABLE, element #%03d, "), 961 pipe_name, j)); 962 switch (mmu_tdm_tbl[j]) { 963 case 0: 964 LOG_VERBOSE(BSL_LS_SOC_TDM, 965 (BSL_META("CONTAINS ACCESSORY TOKEN - assigned as CMIC\n"))); 966 break; 967 case 129: 968 LOG_VERBOSE(BSL_LS_SOC_TDM, 969 (BSL_META("CONTAINS ACCESSORY TOKEN - assigned as LOOPBACK\n"))); 970 break; 971 case TDM_TD2_IDL_TOKEN: 972 LOG_VERBOSE(BSL_LS_SOC_TDM, 973 (BSL_META("CONTAINS ACCESSORY TOKEN - assigned as OPPORTUNISTIC\n"))); 974 break; 975 case 13: 976 case 14: 977 case 15: 978 case 16: 979 if (param_mgmt_num > 0) { 980 LOG_VERBOSE(BSL_LS_SOC_TDM, 981 (BSL_META("CONTAINS ACCESSORY TOKEN - assigned as MANAGEMENT port %d\n"), mmu_tdm_tbl[j])); 982 } else { 983 LOG_VERBOSE(BSL_LS_SOC_TDM, 984 (BSL_META("physical port %d\n"), mmu_tdm_tbl[j])); 985 } 986 break; 987 default: 988 LOG_VERBOSE(BSL_LS_SOC_TDM, 989 (BSL_META("physical port %d\n"), mmu_tdm_tbl[j])); 990 break; 991 } 992 } 993 /* print MMU OVSB calendar */ 994 for (j=0; j<16; j++) { 995 LOG_VERBOSE(BSL_LS_SOC_TDM, 996 (BSL_META("TDM: PIPE: %s, MMU OVS BUCKET 1, element #%0d, " 997 "contains physical port #%0d\n"), pipe_name, j, mmu_tdm_ovs_1[j])); 998 } 999 for (j=0; j<16; j++) { 1000 LOG_VERBOSE(BSL_LS_SOC_TDM, 1001 (BSL_META("TDM: PIPE: %s, MMU OVS BUCKET 2, element #%0d, " 1002 "contains physical port #%0d\n"), pipe_name, j, mmu_tdm_ovs_2[j])); 1003 } 1004 for (j=0; j<16; j++) { 1005 LOG_VERBOSE(BSL_LS_SOC_TDM, 1006 (BSL_META("TDM: PIPE: %s, MMU OVS BUCKET 3, element #%0d, " 1007 "contains physical port #%0d\n"), pipe_name, j, mmu_tdm_ovs_3[j])); 1008 } 1009 for (j=0; j<16; j++) { 1010 LOG_VERBOSE(BSL_LS_SOC_TDM, 1011 (BSL_META("TDM: PIPE: %s, MMU OVS BUCKET 4, element #%0d, " 1012 "contains physical port #%0d\n"), pipe_name, j, mmu_tdm_ovs_4[j])); 1013 } 1014 } 1015 1016 1017 /** 1018 @name: parse_mmu_tdm_tbl 1019 @param: int, int, int[], int[], int[], int[], int[], int 1020 1021 Converts accessory tokens and prints debug form summary of pipe mmu table 1022 */ 1023 1024 void parse_mmu_tdm_tbl(int bw, int mgmt_bw, int mmu_tdm_tbl[256], int mmu_tdm_ovs_1[16], int mmu_tdm_ovs_2[16], int mmu_tdm_ovs_3[16], int mmu_tdm_ovs_4[16], int pipe) 1025 { 1026 int j, k=256, m=0; 1027 const char *name; 1028 int oversub=TDM_TD2_FALSE; 1029 1030 name = (pipe==0) ? "X-PIPE" : "Y-PIPE"; 1031 1032 for (j=0; j<16; j++) {if (mmu_tdm_ovs_1[j]!=TDM_TD2_NUM_EXT_PORTS || mmu_tdm_ovs_2[j]!=TDM_TD2_NUM_EXT_PORTS || mmu_tdm_ovs_3[j]!=TDM_TD2_NUM_EXT_PORTS || mmu_tdm_ovs_4[j]!=TDM_TD2_NUM_EXT_PORTS) {oversub=TDM_TD2_TRUE;}} 1033 for (j=0; j<k; j++) { 1034 if (mmu_tdm_tbl[j]!=TDM_TD2_ACC_TOKEN) { 1035 LOG_VERBOSE(BSL_LS_SOC_TDM, 1036 (BSL_META("TDM: PIPE: %s, MMU TDM TABLE, element #%0d, contains physical port #%0d\n"), name, j, mmu_tdm_tbl[j])); 1037 } 1038 else { 1039 LOG_VERBOSE(BSL_LS_SOC_TDM, 1040 (BSL_META("TDM: PIPE: %s, MMU TDM TABLE, element #%0d, CONTAINS ACCESSORY TOKEN - assigned as "), name, j)); 1041 /* hierarchically determine how to assign the accessory token */ 1042 m++; 1043 if (bw==960) { 1044 if (oversub==TDM_TD2_FALSE) { 1045 if (pipe==0) { 1046 if (mgmt_bw==0) { 1047 switch (m) { 1048 case 1: case 3: case 5: case 7: 1049 CMIC(j) 1050 case 2: case 4: case 6: case 8: 1051 ANCL(j) 1052 } 1053 } 1054 else if (mgmt_bw==4) { 1055 switch (m) { 1056 case 1: 1057 MM13(j) 1058 case 3: 1059 MM14(j) 1060 case 5: 1061 MM15(j) 1062 case 7: 1063 MM16(j) 1064 case 2: case 6: 1065 ANCL(j) 1066 case 4: case 8: 1067 CMIC(j) 1068 } 1069 } 1070 else if (mgmt_bw==1) { 1071 switch (m) 1072 { 1073 case 2: case 4: case 6: case 8: 1074 MM13(j) 1075 case 1: case 5: 1076 ANCL(j) 1077 case 3: case 7: 1078 REFR(j) 1079 } 1080 } 1081 } 1082 else if (pipe==1) { 1083 switch (m) { 1084 case 1: case 3: case 5: case 7: 1085 LPBK(j) 1086 case 2: case 4: case 6: case 8: 1087 ANCL(j) 1088 } 1089 } 1090 } 1091 else if (oversub==TDM_TD2_TRUE) { 1092 if (pipe==0) { 1093 if (mgmt_bw==0) { 1094 switch (m) { 1095 case 1: case 3: case 6: 1096 CMIC(j) 1097 case 2: case 4: case 5: case 7: case 8: 1098 ANCL(j) 1099 } 1100 } 1101 else if (mgmt_bw==4) { 1102 switch (m) { 1103 case 1: MM13(j) 1104 case 3: MM14(j) 1105 case 5: MM15(j) 1106 case 7: MM16(j) 1107 case 2: case 4: case 6: 1108 ANCL(j) 1109 case 8: CMIC(j) 1110 } 1111 } 1112 else if (mgmt_bw==1) { 1113 LOG_VERBOSE(BSL_LS_SOC_TDM, 1114 (BSL_META("UNSUPPORTED\n"))); 1115 } 1116 } 1117 else if (pipe==1) { 1118 switch (m) 1119 { 1120 case 1: case 3: case 6: 1121 LPBK(j) 1122 case 2: case 4: case 5: case 7: case 8: 1123 ANCL(j) 1124 } 1125 } 1126 } 1127 } 1128 else if (bw==720) 1129 { 1130 if (pipe==0) 1131 { 1132 if (mgmt_bw==0) 1133 { 1134 switch (m) 1135 { 1136 case 1: 1137 case 3: 1138 case 5: 1139 case 7: 1140 case 9: 1141 CMIC(j) 1142 case 2: 1143 case 4: 1144 case 6: 1145 case 8: 1146 case 10: 1147 ANCL(j) 1148 } 1149 } 1150 else if (mgmt_bw==4) 1151 { 1152 switch (m) 1153 { 1154 case 1: MM13(j) 1155 case 3: MM14(j) 1156 case 6: MM15(j) 1157 case 8: MM16(j) 1158 case 2: 1159 case 5: 1160 case 9: 1161 ANCL(j) 1162 case 4: 1163 case 7: 1164 case 10: CMIC(j) 1165 } 1166 } 1167 else if (mgmt_bw==1) 1168 { 1169 switch (m) 1170 { 1171 case 2: 1172 case 4: 1173 case 7: 1174 case 9: 1175 MM13(j) 1176 case 1: 1177 case 3: 1178 case 5: 1179 case 6: 1180 case 8: 1181 ANCL(j) 1182 case 10: CMIC(j) 1183 } 1184 } 1185 } 1186 else if (pipe==1) 1187 { 1188 switch (m) 1189 { 1190 case 1: 1191 case 3: 1192 case 5: 1193 case 7: 1194 case 9: 1195 LPBK(j) 1196 case 2: 1197 case 4: 1198 case 6: 1199 case 8: 1200 case 10: 1201 ANCL(j) 1202 } 1203 } 1204 } 1205 else if (bw==640) 1206 { 1207 if (oversub==TDM_TD2_FALSE) 1208 { 1209 if (pipe==0) 1210 { 1211 if (mgmt_bw==0) 1212 { 1213 switch (m) 1214 { 1215 case 1: 1216 case 3: 1217 case 5: 1218 case 7: 1219 CMIC(j) 1220 case 2: 1221 case 4: 1222 case 6: 1223 case 8: 1224 ANCL(j) 1225 } 1226 } 1227 else if (mgmt_bw==4) 1228 { 1229 switch (m) 1230 { 1231 case 1: MM13(j) 1232 case 3: MM14(j) 1233 case 5: MM15(j) 1234 case 7: MM16(j) 1235 case 2: 1236 case 6: 1237 ANCL(j) 1238 case 4: 1239 case 8: 1240 CMIC(j) 1241 } 1242 } 1243 else if (mgmt_bw==1) 1244 { 1245 switch (m) 1246 { 1247 case 2: 1248 case 4: 1249 case 6: 1250 case 8: 1251 MM13(j) 1252 case 1: 1253 case 5: 1254 ANCL(j) 1255 case 3: 1256 case 7: 1257 REFR(j) 1258 } 1259 } 1260 } 1261 else if (pipe==1) 1262 { 1263 switch (m) 1264 { 1265 case 1: 1266 case 3: 1267 case 5: 1268 case 7: 1269 LPBK(j) 1270 case 2: 1271 case 4: 1272 case 6: 1273 case 8: 1274 ANCL(j) 1275 } 1276 } 1277 } 1278 else if (oversub==TDM_TD2_TRUE) 1279 { 1280 if (pipe==0) 1281 { 1282 if (mgmt_bw==0) 1283 { 1284 switch (m) 1285 { 1286 case 1: 1287 case 3: 1288 case 6: 1289 CMIC(j) 1290 case 2: 1291 case 4: 1292 case 5: 1293 case 7: 1294 case 8: 1295 ANCL(j) 1296 } 1297 } 1298 else if (mgmt_bw==4) 1299 { 1300 switch (m) 1301 { 1302 case 1: MM13(j) 1303 case 3: MM14(j) 1304 case 5: MM15(j) 1305 case 7: MM16(j) 1306 case 2: 1307 case 4: 1308 case 6: 1309 ANCL(j) 1310 case 8: CMIC(j) 1311 } 1312 } 1313 else if (mgmt_bw==1) 1314 { 1315 LOG_VERBOSE(BSL_LS_SOC_TDM, 1316 (BSL_META("UNSUPPORTED\n"))); 1317 } 1318 } 1319 else if (pipe==1) 1320 { 1321 switch (m) 1322 { 1323 case 1: 1324 case 3: 1325 case 6: 1326 LPBK(j) 1327 case 2: 1328 case 4: 1329 case 5: 1330 case 7: 1331 case 8: 1332 ANCL(j) 1333 } 1334 } 1335 } 1336 } 1337 else if (bw==480) 1338 { 1339 if (pipe==0) 1340 { 1341 if (mgmt_bw==0) 1342 { 1343 switch (m) 1344 { 1345 case 1: 1346 case 3: 1347 case 5: 1348 case 7: 1349 case 9: 1350 CMIC(j) 1351 case 2: 1352 case 4: 1353 case 6: 1354 case 8: 1355 case 10: 1356 ANCL(j) 1357 } 1358 } 1359 else if (mgmt_bw==4) 1360 { 1361 switch (m) 1362 { 1363 case 1: MM13(j) 1364 case 3: MM14(j) 1365 case 6: MM15(j) 1366 case 8: MM16(j) 1367 case 2: 1368 case 5: 1369 case 9: 1370 ANCL(j) 1371 case 4: 1372 case 7: 1373 case 10: 1374 CMIC(j) 1375 } 1376 } 1377 else if (mgmt_bw==1) 1378 { 1379 switch (m) 1380 { 1381 case 2: 1382 case 4: 1383 case 7: 1384 case 9: 1385 MM13(j) 1386 case 1: 1387 case 3: 1388 case 5: 1389 case 6: 1390 case 8: 1391 ANCL(j) 1392 case 10: CMIC(j) 1393 } 1394 } 1395 } 1396 else if (pipe==1) 1397 { 1398 switch (m) 1399 { 1400 case 1: 1401 case 3: 1402 case 5: 1403 case 7: 1404 case 9: 1405 LPBK(j) 1406 case 2: 1407 case 4: 1408 case 6: 1409 case 8: 1410 case 10: 1411 ANCL(j) 1412 } 1413 } 1414 } 1415 else 1416 { 1417 LOG_VERBOSE(BSL_LS_SOC_TDM, 1418 (BSL_META("INVALID PARAMETERS\n"))); 1419 } 1420 } 1421 } 1422 for (j=0; j<16; j++) 1423 { 1424 LOG_VERBOSE(BSL_LS_SOC_TDM, 1425 (BSL_META("TDM: PIPE: %s, MMU OVS BUCKET 1, element #%0d, " 1426 "contains physical port #%0d\n"), name, j, mmu_tdm_ovs_1[j])); 1427 } 1428 for (j=0; j<16; j++) 1429 { 1430 LOG_VERBOSE(BSL_LS_SOC_TDM, 1431 (BSL_META("TDM: PIPE: %s, MMU OVS BUCKET 2, element #%0d, " 1432 "contains physical port #%0d\n"), name, j, mmu_tdm_ovs_2[j])); 1433 } 1434 for (j=0; j<16; j++) 1435 { 1436 LOG_VERBOSE(BSL_LS_SOC_TDM, 1437 (BSL_META("TDM: PIPE: %s, MMU OVS BUCKET 3, element #%0d, " 1438 "contains physical port #%0d\n"), name, j, mmu_tdm_ovs_3[j])); 1439 } 1440 for (j=0; j<16; j++) 1441 { 1442 LOG_VERBOSE(BSL_LS_SOC_TDM, 1443 (BSL_META("TDM: PIPE: %s, MMU OVS BUCKET 4, element #%0d, " 1444 "contains physical port #%0d\n"), name, j, mmu_tdm_ovs_4[j])); 1445 } 1446 } 1447 1448 1449 /** 1450 @name: print_tdm_tbl 1451 @param: int[32], const char* 1452 1453 Prints debug form summary of quadrant's table 1454 */ 1455 1456 void print_tdm_tbl(int pgw_tdm_tbl[32], const char* name) 1457 { 1458 int j; 1459 for (j = 0; j < 32; j++) 1460 { 1461 switch (pgw_tdm_tbl[j]) 1462 { 1463 case 130: 1464 LOG_VERBOSE(BSL_LS_SOC_TDM, 1465 (BSL_META("TDM: PIPE: %s, TDM Calendar, element #%0d, " 1466 "contains an invalid or disabled port\n"), name, j)); 1467 break; 1468 case 131: 1469 LOG_VERBOSE(BSL_LS_SOC_TDM, 1470 (BSL_META("TDM: PIPE: %s, TDM Calendar, element #%0d, " 1471 "contains an oversubscription token\n"), name, j)); 1472 break; 1473 default: 1474 LOG_VERBOSE(BSL_LS_SOC_TDM, 1475 (BSL_META("TDM: PIPE: %s, TDM Calendar, element #%0d, " 1476 "contains physical port #%0d\n"), name, j, pgw_tdm_tbl[j])); 1477 break; 1478 } 1479 } 1480 } 1481 1482 1483 /** 1484 @name: print_tbl_summary 1485 @param: int[32], int[32], int[32], int[32], int[32], int[32], int[32], int[32], int[32], int[32], int[32], int[32], int 1486 1487 Prints short form final summary of all tables generated 1488 */ 1489 1490 void print_tbl_summary(int x0[32], int x1[32], int y0[32], int y1[32], int ox0[32], int ox1[32], int oy0[32], int oy1[32], int sx0[32], int sx1[32], int sy0[32], int sy1[32], int bw) 1491 { 1492 int t; 1493 LOG_VERBOSE(BSL_LS_SOC_TDM, 1494 (BSL_META("TDM: core bandwidth is %0d\n"), bw)); 1495 LOG_VERBOSE(BSL_LS_SOC_TDM, 1496 (BSL_META("TDM: X0, TDM Calendar\n"))); 1497 for (t = 0; t < 32; t++) 1498 { 1499 switch (x0[t]) 1500 { 1501 case 130: 1502 LOG_VERBOSE(BSL_LS_SOC_TDM, 1503 (BSL_META(" x"))); 1504 break; 1505 case 131: 1506 LOG_VERBOSE(BSL_LS_SOC_TDM, 1507 (BSL_META(" O"))); 1508 break; 1509 default: 1510 LOG_VERBOSE(BSL_LS_SOC_TDM, 1511 (BSL_META(" %0d"), x0[t])); 1512 break; 1513 } 1514 } 1515 LOG_VERBOSE(BSL_LS_SOC_TDM, 1516 (BSL_META("\nTDM: X0, OVS Calendar\n"))); 1517 for (t = 0; t < 32; t++) 1518 { 1519 switch (ox0[t]) 1520 { 1521 case 130: 1522 LOG_VERBOSE(BSL_LS_SOC_TDM, 1523 (BSL_META(" x"))); 1524 break; 1525 default: 1526 LOG_VERBOSE(BSL_LS_SOC_TDM, 1527 (BSL_META(" %0d"), ox0[t])); 1528 break; 1529 } 1530 } 1531 LOG_VERBOSE(BSL_LS_SOC_TDM, 1532 (BSL_META("\nTDM: X0, OVS Spacing Info\n"))); 1533 for (t = 0; t < 32; t++) 1534 { 1535 switch (sx0[t]) 1536 { 1537 case 130: 1538 LOG_VERBOSE(BSL_LS_SOC_TDM, 1539 (BSL_META(" x"))); 1540 break; 1541 default: 1542 LOG_VERBOSE(BSL_LS_SOC_TDM, 1543 (BSL_META(" %0d"), sx0[t])); 1544 break; 1545 } 1546 } 1547 LOG_VERBOSE(BSL_LS_SOC_TDM, 1548 (BSL_META("\nTDM: X1, TDM Calendar\n"))); 1549 for (t = 0; t < 32; t++) 1550 { 1551 switch (x1[t]) 1552 { 1553 case 130: 1554 LOG_VERBOSE(BSL_LS_SOC_TDM, 1555 (BSL_META(" x"))); 1556 break; 1557 case 131: 1558 LOG_VERBOSE(BSL_LS_SOC_TDM, 1559 (BSL_META(" O"))); 1560 break; 1561 default: 1562 LOG_VERBOSE(BSL_LS_SOC_TDM, 1563 (BSL_META(" %0d"), x1[t])); 1564 break; 1565 } 1566 } 1567 LOG_VERBOSE(BSL_LS_SOC_TDM, 1568 (BSL_META("\nTDM: X1, OVS Calendar\n"))); 1569 for (t = 0; t < 32; t++) 1570 { 1571 switch (ox1[t]) 1572 { 1573 case 130: 1574 LOG_VERBOSE(BSL_LS_SOC_TDM, 1575 (BSL_META(" x"))); 1576 break; 1577 default: 1578 LOG_VERBOSE(BSL_LS_SOC_TDM, 1579 (BSL_META(" %0d"), ox1[t])); 1580 break; 1581 } 1582 } 1583 LOG_VERBOSE(BSL_LS_SOC_TDM, 1584 (BSL_META("\nTDM: X1, OVS Spacing Info\n"))); 1585 for (t = 0; t < 32; t++) 1586 { 1587 switch (sx1[t]) 1588 { 1589 case 130: 1590 LOG_VERBOSE(BSL_LS_SOC_TDM, 1591 (BSL_META(" x"))); 1592 break; 1593 default: 1594 LOG_VERBOSE(BSL_LS_SOC_TDM, 1595 (BSL_META(" %0d"), sx1[t])); 1596 break; 1597 } 1598 } 1599 LOG_VERBOSE(BSL_LS_SOC_TDM, 1600 (BSL_META("\nTDM: Y0, TDM Calendar\n"))); 1601 for (t = 0; t < 32; t++) 1602 { 1603 switch (y0[t]) 1604 { 1605 case 130: 1606 LOG_VERBOSE(BSL_LS_SOC_TDM, 1607 (BSL_META(" x"))); 1608 break; 1609 case 131: 1610 LOG_VERBOSE(BSL_LS_SOC_TDM, 1611 (BSL_META(" O"))); 1612 break; 1613 default: 1614 LOG_VERBOSE(BSL_LS_SOC_TDM, 1615 (BSL_META(" %0d"), y0[t])); 1616 break; 1617 } 1618 } 1619 LOG_VERBOSE(BSL_LS_SOC_TDM, 1620 (BSL_META("\nTDM: Y0, OVS Calendar\n"))); 1621 for (t = 0; t < 32; t++) 1622 { 1623 switch (oy0[t]) 1624 { 1625 case 130: 1626 LOG_VERBOSE(BSL_LS_SOC_TDM, 1627 (BSL_META(" x"))); 1628 break; 1629 default: 1630 LOG_VERBOSE(BSL_LS_SOC_TDM, 1631 (BSL_META(" %0d"), oy0[t])); 1632 break; 1633 } 1634 } 1635 LOG_VERBOSE(BSL_LS_SOC_TDM, 1636 (BSL_META("\nTDM: Y0, OVS Spacing Info\n"))); 1637 for (t = 0; t < 32; t++) 1638 { 1639 switch (sy0[t]) 1640 { 1641 case 130: 1642 LOG_VERBOSE(BSL_LS_SOC_TDM, 1643 (BSL_META(" x"))); 1644 break; 1645 default: 1646 LOG_VERBOSE(BSL_LS_SOC_TDM, 1647 (BSL_META(" %0d"), sy0[t])); 1648 break; 1649 } 1650 } 1651 LOG_VERBOSE(BSL_LS_SOC_TDM, 1652 (BSL_META("\nTDM: Y1, TDM Calendar\n"))); 1653 for (t = 0; t < 32; t++) 1654 { 1655 switch (y1[t]) 1656 { 1657 case 130: 1658 LOG_VERBOSE(BSL_LS_SOC_TDM, 1659 (BSL_META(" x"))); 1660 break; 1661 case 131: 1662 LOG_VERBOSE(BSL_LS_SOC_TDM, 1663 (BSL_META(" O"))); 1664 break; 1665 default: 1666 LOG_VERBOSE(BSL_LS_SOC_TDM, 1667 (BSL_META(" %0d"), y1[t])); 1668 break; 1669 } 1670 } 1671 LOG_VERBOSE(BSL_LS_SOC_TDM, 1672 (BSL_META("\nTDM: Y1, OVS Calendar\n"))); 1673 for (t = 0; t < 32; t++) 1674 { 1675 switch (oy1[t]) 1676 { 1677 case 130: 1678 LOG_VERBOSE(BSL_LS_SOC_TDM, 1679 (BSL_META(" x"))); 1680 break; 1681 default: 1682 LOG_VERBOSE(BSL_LS_SOC_TDM, 1683 (BSL_META(" %0d"), oy1[t])); 1684 break; 1685 } 1686 } 1687 LOG_VERBOSE(BSL_LS_SOC_TDM, 1688 (BSL_META("\nTDM: Y1, OVS Spacing Info\n"))); 1689 for (t = 0; t < 32; t++) 1690 { 1691 switch (sy1[t]) 1692 { 1693 case 130: 1694 LOG_VERBOSE(BSL_LS_SOC_TDM, 1695 (BSL_META(" x"))); 1696 break; 1697 default: 1698 LOG_VERBOSE(BSL_LS_SOC_TDM, 1699 (BSL_META(" %0d"), sy1[t])); 1700 break; 1701 } 1702 } 1703 LOG_VERBOSE(BSL_LS_SOC_TDM, 1704 (BSL_META("\n"))); 1705 } 1706 1707 1708 /** 1709 @name: TDM_scheduler_PQ 1710 @param: int 1711 1712 Customizable partial quotient ceiling function 1713 */ 1714 /* int TDM_scheduler_PQ(float f) { return (int)((f < 0.0f) ? f - 0.5f : f + 0.5f); }*/ 1715 1716 int TDM_scheduler_PQ(int f) { return ((int)((f+5)/10)); } 1717 1718 1719 /** 1720 @name: TDM_scheduler 1721 @param: int[][], enum, int*, int*, int*, int, int[], int[], int, int, int, int[], int, int, int[], int*, int 1722 1723 Populate bilayer TDM calender 1724 */ 1725 1726 int TDM_scheduler(int wc_array[TDM_TD2_NUM_WC][4], enum tdm_td2_port_speed speed[TDM_TD2_NUM_EXT_PORTS], int *cur_idx, int *pgw_tdm_idx, int *ovs_tdm_idx, int subp, int pgw_tdm_tbl[32], int ovs_tdm_tbl[32], int upperlimit, int iter1, int bw, int port_state_map[128], int iter3, int stop1, int swap_array[32], int *z, int subport, int op_flags[1]) 1727 { 1728 int max_tdm_len=bw/40, pgw_tdm_idx_sub; 1729 int p, l; 1730 int num_lr = 0, num_lr_1 = 0, num_lr_10 = 0, num_lr_20 = 0, num_lr_40 = 0, num_lr_100 = 0, num_lr_120 = 0, num_ovs = 0, num_off = 0; 1731 int l1_tdm_len, l1_ovs_cnt = 0; 1732 int gestalt_iter, gestalt_id_iter, gestalt_id = 0, gestalt_tag; 1733 int sm_iter = 0; 1734 int microsub = TDM_TD2_FALSE; 1735 int pad_40g_in_480g = TDM_TD2_FALSE; 1736 1737 LOG_VERBOSE(BSL_LS_SOC_TDM, 1738 (BSL_META("TDM: ----------------------------------------------------------------\n"))); 1739 /* set layer 1 TDM max subspace length */ 1740 switch(bw) 1741 { 1742 case 480: 1743 pgw_tdm_idx_sub = 3; 1744 break; 1745 case 640: 1746 pgw_tdm_idx_sub = 4; 1747 break; 1748 case 720: 1749 if ((iter3 == 32 || iter3 == 64) && (stop1 == 64 || stop1 == 96)) {pgw_tdm_idx_sub = 5; max_tdm_len = 20;} 1750 else {pgw_tdm_idx_sub = 4; max_tdm_len = 16;} 1751 break; 1752 case 800: 1753 pgw_tdm_idx_sub = 5; 1754 break; 1755 case 960: 1756 pgw_tdm_idx_sub = 6; 1757 break; 1758 case 1120: 1759 pgw_tdm_idx_sub = 7; 1760 break; 1761 case 1280: 1762 pgw_tdm_idx_sub = 8; 1763 break; 1764 default: 1765 pgw_tdm_idx_sub = 8; 1766 break; 1767 } 1768 for (p = iter3; p < stop1; p++) 1769 { 1770 if (port_state_map[p] == 1) 1771 { 1772 num_lr++; 1773 if (port_state_map[p+1] != 3) 1774 { 1775 if (speed[p+1]<TDM_TD2_SPEED_10G) num_lr_1++; 1776 else if (speed[p+1]==TDM_TD2_SPEED_10G || speed[p+1]==TDM_TD2_SPEED_10G_DUAL || speed[p+1]==TDM_TD2_SPEED_10G_XAUI) num_lr_10++; 1777 } 1778 else if (port_state_map[p+1] == 3 && 1779 port_state_map[p+2] != 3) num_lr_20++; 1780 else if (port_state_map[p+1] == 3 && 1781 port_state_map[p+2] == 3 && 1782 port_state_map[p+4] != 3) num_lr_40++; 1783 else if (port_state_map[p+1] == 3 && 1784 port_state_map[p+2] == 3 && 1785 port_state_map[p+4] == 3 && 1786 port_state_map[p+9] == 3 && 1787 port_state_map[p+11] != 3) num_lr_100++; 1788 else if (port_state_map[p+1] == 3 && 1789 port_state_map[p+2] == 3 && 1790 port_state_map[p+4] == 3 && 1791 port_state_map[p+9] == 3 && 1792 port_state_map[p+11] == 3) num_lr_120++; 1793 } 1794 else if (port_state_map[p] == 2) { 1795 num_ovs++; 1796 if (op_flags[0]==1 && speed[p+1]<TDM_TD2_SPEED_10G) {num_lr_1++; num_lr++;} 1797 } 1798 else if (port_state_map[p] == 0) num_off++; 1799 } 1800 if (iter3 < 17) 1801 { 1802 /* 1803 for (p=0; p<4; p++) if (wc_array[3][p]==TDM_TD2_MGM_TOKEN) */ 1804 for (p=0; p<4; p++) if (wc_array[3][p]==TDM_TD2_MGM_TOKEN && port_state_map[p+13-1] == 1) 1805 { 1806 num_lr--; 1807 if (speed[p+13]==TDM_TD2_SPEED_2p5G || speed[p+13]==TDM_TD2_SPEED_1G) num_lr_1--; 1808 else if (speed[p+13]==TDM_TD2_SPEED_10G || speed[p+13]==TDM_TD2_SPEED_10G_XAUI) num_lr_10--; 1809 } 1810 } 1811 /* assert( (num_lr_10+num_lr_20+num_lr_40+num_lr_100+num_lr_120) <= num_lr ); */ 1812 if ((num_lr_1+num_lr_10+num_lr_20+num_lr_40+num_lr_100+num_lr_120) != num_lr) 1813 { 1814 LOG_ERROR(BSL_LS_SOC_TDM, 1815 (BSL_META("TDM: _____FATAL ERROR: port allocation mismatch detected\n"))); 1816 return 0; 1817 } 1818 1819 /* number of 10G slots required */ 1820 l1_tdm_len = ((num_lr_1)+(num_lr_10)+((num_lr_20)*2)+((num_lr_40)*4)+((num_lr_100)*10)+((num_lr_120)*12)); 1821 1822 /* check bandwidth overloading */ 1823 if (l1_tdm_len > max_tdm_len) 1824 { 1825 if (num_lr_1==0) 1826 { 1827 LOG_ERROR(BSL_LS_SOC_TDM, 1828 (BSL_META("TDM: _____FATAL ERROR: bandwidth overloaded\n"))); 1829 return 0; 1830 } 1831 /* if this quadrant has too many 1G ports, override slot settings and implicitly downscale each slot's resolution */ 1832 else if ( (op_flags[0]!=1) && (num_lr_1!=0) && (num_lr_10==0) && (num_lr_20==0) && (num_lr_40==0) && (num_lr_100==0) && (num_lr_120==0)) 1833 { 1834 max_tdm_len=num_lr_1; 1835 /* if (num_lr_1 % 4 != 0) 1836 { 1837 LOG_ERROR(BSL_LS_SOC_TDM, 1838 (BSL_META("TDM: _____FATAL ERROR: illegal 1G configuration\n"))); 1839 return 0; 1840 } 1841 else pgw_tdm_idx_sub=num_lr_1/4; */ 1842 pgw_tdm_idx_sub=num_lr_1/4; 1843 } 1844 else if ( (num_lr_1!=0 && ((num_lr_10!=0) || (num_lr_20!=0) || (num_lr_40!=0) || (num_lr_100!=0) || (num_lr_120!=0))) ) 1845 { 1846 LOG_VERBOSE(BSL_LS_SOC_TDM, 1847 (BSL_META("TDM: _____VERBOSE: bandwidth granularity insufficient, using 1G microscheduling\n"))); 1848 microsub=TDM_TD2_TRUE; 1849 } 1850 } 1851 1852 if ( (num_lr_1>0) && (op_flags[0]==1) ) 1853 { 1854 microsub=TDM_TD2_TRUE; 1855 } 1856 1857 /* calculate base number of OVS tokens required */ 1858 if (num_ovs > 0) 1859 { 1860 LOG_VERBOSE(BSL_LS_SOC_TDM, 1861 (BSL_META("TDM: _____VERBOSE: oversub detected\n"))); 1862 1863 if (num_lr_100!=1 && l1_tdm_len!=0) 1864 { 1865 if ( (max_tdm_len-l1_tdm_len)%4==0 ) l1_ovs_cnt=((max_tdm_len-l1_tdm_len)/4); 1866 else if ( (max_tdm_len-l1_tdm_len)%2==0 ) 1867 { 1868 if (subport == 1 || subport == 3) l1_ovs_cnt=(max_tdm_len-l1_tdm_len+((max_tdm_len-l1_tdm_len)%4))/4; 1869 else l1_ovs_cnt = ((max_tdm_len-l1_tdm_len)/4); 1870 } 1871 else l1_ovs_cnt = ((max_tdm_len - l1_tdm_len - (4 - l1_tdm_len % 4))/4); 1872 } 1873 else if (num_lr_100==1) l1_ovs_cnt = 1; 1874 else if (l1_tdm_len == 0) l1_ovs_cnt = max_tdm_len; 1875 1876 if ((l1_ovs_cnt==0) && (op_flags[0]==0) && 1877 (subport == 1 || subport == 3)) { 1878 LOG_ERROR(BSL_LS_SOC_TDM, 1879 (BSL_META("TDM: _____ERROR: unable to partition oversubscription tokens\n"))); 1880 } 1881 else { 1882 LOG_VERBOSE(BSL_LS_SOC_TDM, 1883 (BSL_META("TDM: _____VERBOSE: %0d oversub tokens assigned\n"), l1_ovs_cnt)); 1884 } 1885 } 1886 1887 if (bw==480 && num_lr<3) { 1888 pad_40g_in_480g = TDM_TD2_TRUE; 1889 } 1890 1891 LOG_VERBOSE(BSL_LS_SOC_TDM, 1892 (BSL_META("TDM: _____VERBOSE: base oversubscription token pool is %0d\n"), l1_ovs_cnt)); 1893 LOG_VERBOSE(BSL_LS_SOC_TDM, 1894 (BSL_META("TDM: ----------------------------------------------------------------\n"))); 1895 LOG_VERBOSE(BSL_LS_SOC_TDM, 1896 (BSL_META("TDM: _____VERBOSE: 1G line rate ports in this quadrant is %0d\n"), num_lr_1)); 1897 LOG_VERBOSE(BSL_LS_SOC_TDM, 1898 (BSL_META("TDM: _____VERBOSE: 10G line rate ports in this quadrant is %0d\n"), num_lr_10)); 1899 LOG_VERBOSE(BSL_LS_SOC_TDM, 1900 (BSL_META("TDM: _____VERBOSE: 20G line rate ports in this quadrant is %0d\n"), num_lr_20)); 1901 LOG_VERBOSE(BSL_LS_SOC_TDM, 1902 (BSL_META("TDM: _____VERBOSE: 40G line rate ports in this quadrant is %0d\n"), num_lr_40)); 1903 LOG_VERBOSE(BSL_LS_SOC_TDM, 1904 (BSL_META("TDM: _____VERBOSE: 100G gestalt line rate ports in this quadrant is %0d\n"), num_lr_100)); 1905 LOG_VERBOSE(BSL_LS_SOC_TDM, 1906 (BSL_META("TDM: _____VERBOSE: 120G gestalt line rate ports in this quadrant is %0d\n"), num_lr_120)); 1907 LOG_VERBOSE(BSL_LS_SOC_TDM, 1908 (BSL_META("TDM: _____VERBOSE: oversubscribed ports in this quadrant is %0d\n"), num_ovs)); 1909 LOG_VERBOSE(BSL_LS_SOC_TDM, 1910 (BSL_META("TDM: _____VERBOSE: disabled subports in this quadrent is %0d\n"), num_off)); 1911 LOG_VERBOSE(BSL_LS_SOC_TDM, 1912 (BSL_META("TDM: _____VERBOSE: COVERAGE FROM PHYSICAL PORTS %0d to %0d\n"), iter3, stop1)); 1913 1914 if (microsub==TDM_TD2_TRUE) 1915 { 1916 if ( (num_ovs==0) && ( (op_flags[0]==1) || ( (((num_lr_1)+(10*num_lr_10)+(20*num_lr_20)+(40*num_lr_40)+(100*num_lr_100)+(120*num_lr_120)) > 32) ) ) ) 1917 { 1918 LOG_VERBOSE(BSL_LS_SOC_TDM, 1919 (BSL_META("TDM: _____VERBOSE: shunting all 1G into oversub table\n"))); 1920 op_flags[0]=1; 1921 for (l=iter3; l<stop1; l++) { 1922 if (speed[l+1]==TDM_TD2_SPEED_1G) { 1923 if (port_state_map[l]==1) { 1924 port_state_map[l]=2; 1925 num_ovs++; 1926 } 1927 } 1928 } 1929 } 1930 if (op_flags[0]==1) 1931 { 1932 int pgw_tdm_idx_lookback = 0; 1933 int sm_iter = 0; 1934 l1_ovs_cnt = ((max_tdm_len-(num_lr_10)-(num_lr_20*2)-(num_lr_40*4)-(num_lr_100*10)-(num_lr_120*12))/4); 1935 LOG_VERBOSE(BSL_LS_SOC_TDM, 1936 (BSL_META("TDM: _____VERBOSE: oversub tokens increased to %0d\n"), l1_ovs_cnt)); 1937 while (sm_iter < TDM_TD2_NUM_EXT_PORTS) 1938 { 1939 /* chopping block */ 1940 while ((*cur_idx < upperlimit) && ((wc_array[*cur_idx][subp] == TDM_TD2_NUM_EXT_PORTS) || (wc_array[*cur_idx][subp] == TDM_TD2_MGM_TOKEN))) 1941 { 1942 (*cur_idx)++; 1943 } 1944 if (*cur_idx >= upperlimit) 1945 { 1946 /* table post processing */ 1947 LOG_VERBOSE(BSL_LS_SOC_TDM, 1948 (BSL_META("TDM: _____DEBUG: entering post-processing 1, " 1949 "executing lookback %0d against subset limit %0d\n"), 1950 pgw_tdm_idx_lookback, pgw_tdm_idx_sub)); 1951 if (l1_ovs_cnt > 0) 1952 { 1953 int ovs_pad_iter = 0; 1954 while (ovs_pad_iter < l1_ovs_cnt && pgw_tdm_idx_lookback < pgw_tdm_idx_sub) 1955 { 1956 pgw_tdm_tbl[*pgw_tdm_idx] = TDM_TD2_OVS_TOKEN; 1957 LOG_VERBOSE(BSL_LS_SOC_TDM, 1958 (BSL_META("TDM: Pipe : %0d the pgw tdm tbl element #0%0d, " 1959 "insert OVS token\n"), upperlimit, *pgw_tdm_idx)); 1960 (*pgw_tdm_idx)++; 1961 pgw_tdm_idx_lookback++; 1962 ovs_pad_iter++; 1963 } 1964 } 1965 if (pad_40g_in_480g==TDM_TD2_TRUE) { 1966 /* at 480G, TDM must be padded to max length or underrun */ 1967 while ( (bw<=480) && (pgw_tdm_idx_sub > pgw_tdm_idx_lookback) ) 1968 { 1969 pgw_tdm_tbl[*pgw_tdm_idx] = TDM_TD2_OVS_TOKEN; 1970 (*pgw_tdm_idx)++; 1971 pgw_tdm_idx_lookback++; 1972 if (pgw_tdm_idx_lookback >= pgw_tdm_idx_sub) break; 1973 } 1974 } 1975 1976 return 1; 1977 } 1978 1979 LOG_VERBOSE(BSL_LS_SOC_TDM, 1980 (BSL_META("TDM: ----------------------------------------------------------------\n"))); 1981 LOG_VERBOSE(BSL_LS_SOC_TDM, 1982 (BSL_META("TDM: _____DEBUG: the present port is %0d, speed %0d\n"), 1983 wc_array[*cur_idx][subp],speed[wc_array[*cur_idx][subp]])); 1984 1985 /* port state machine */ 1986 switch(port_state_map[(wc_array[*cur_idx][subp])-1]) 1987 { 1988 case 0: 1989 LOG_VERBOSE(BSL_LS_SOC_TDM, 1990 (BSL_META("TDM: _____VERBOSE: the port is DISABLED\n"))); 1991 LOG_VERBOSE(BSL_LS_SOC_TDM, 1992 (BSL_META("TDM: Pipe : %0d the pgw tdm tbl element #0%0d " 1993 "would be an invalid port\n"), upperlimit, *pgw_tdm_idx)); 1994 if (num_lr > 0 && num_ovs > 0) 1995 { 1996 pgw_tdm_tbl[*pgw_tdm_idx] = TDM_TD2_OVS_TOKEN; 1997 (*pgw_tdm_idx)++; 1998 pgw_tdm_idx_lookback++; 1999 } 2000 (*cur_idx)++; 2001 break; 2002 /* this only iterates by active port (not lane) so it should never see this */ 2003 /* case 3: 2004 LOG_VERBOSE(BSL_LS_SOC_TDM, 2005 (BSL_META("TDM: _____VERBOSE: the port is part of a DUAL/QUAD/100G\n"))); */ 2006 case 1: 2007 LOG_VERBOSE(BSL_LS_SOC_TDM, 2008 (BSL_META("TDM: _____VERBOSE: the port is LINE RATE\n"))); 2009 if (num_ovs == 0) 2010 { 2011 LOG_VERBOSE(BSL_LS_SOC_TDM, 2012 (BSL_META("TDM: the cur_idx is %0d\n"), *cur_idx)); 2013 2014 while ((*z) > 0 && pgw_tdm_tbl[(*pgw_tdm_idx)-1] != swap_array[*z]) 2015 { 2016 LOG_VERBOSE(BSL_LS_SOC_TDM, 2017 (BSL_META("TDM: Pipe : %0d priority dequeuing " 2018 "from LIFO swap buffer, pointer index %0d, " 2019 "to pgw tdm tbl element #0%0d, content is %0d\n"), 2020 upperlimit, *z, *pgw_tdm_idx, swap_array[*z])); 2021 pgw_tdm_tbl[*pgw_tdm_idx] = swap_array[*z]; 2022 (*pgw_tdm_idx)++; 2023 (*z)--; 2024 LOG_VERBOSE(BSL_LS_SOC_TDM, 2025 (BSL_META("TDM: _____DEBUG: LIFO index pointer is %0d\n"), *z)); 2026 } 2027 if ((wc_array[*cur_idx][subp] != pgw_tdm_tbl[(*pgw_tdm_idx)-1] || (*pgw_tdm_idx)==0)) 2028 { 2029 pgw_tdm_tbl[*pgw_tdm_idx] = wc_array[*cur_idx][subp]; 2030 LOG_VERBOSE(BSL_LS_SOC_TDM, 2031 (BSL_META("TDM: Pipe : %0d the pgw tdm tbl " 2032 "element #0%0d, content is %0d\n"), 2033 upperlimit, *pgw_tdm_idx, pgw_tdm_tbl[*pgw_tdm_idx])); 2034 (*pgw_tdm_idx)++; 2035 (*cur_idx)++; 2036 } 2037 else 2038 { 2039 (*z)++; 2040 swap_array[*z] = wc_array[*cur_idx][subp]; 2041 LOG_VERBOSE(BSL_LS_SOC_TDM, 2042 (BSL_META("TDM: Pipe : %0d pushed port %0d into " 2043 "LIFO swap buffer at index %0d\n"), 2044 upperlimit, wc_array[*cur_idx][subp], *z)); 2045 (*cur_idx)++; 2046 } 2047 /* at 480G the table must be padded or underrun */ 2048 if (bw<=480 && pad_40g_in_480g==TDM_TD2_TRUE) pgw_tdm_idx_lookback++; 2049 /* all faster bandwidths ok */ 2050 else pgw_tdm_idx_lookback = pgw_tdm_idx_sub; 2051 } 2052 else if (num_ovs > 0) 2053 { 2054 LOG_VERBOSE(BSL_LS_SOC_TDM, 2055 (BSL_META("TDM: the cur_idx is %0d\n"), *cur_idx)); 2056 2057 if ((*z) > 0 && 2058 pgw_tdm_tbl[(*pgw_tdm_idx)-2] != swap_array[*z] && 2059 pgw_tdm_tbl[(*pgw_tdm_idx)-1] == TDM_TD2_OVS_TOKEN && 2060 (pgw_tdm_idx_lookback < (pgw_tdm_idx_sub-l1_ovs_cnt))) 2061 { 2062 LOG_VERBOSE(BSL_LS_SOC_TDM, 2063 (BSL_META("TDM: Pipe : %0d priority dequeuing from " 2064 "LIFO swap buffer, pointer index %0d, to pgw " 2065 "tdm tbl element #0%0d, content is %0d\n"), 2066 upperlimit, *z, *pgw_tdm_idx, swap_array[*z])); 2067 pgw_tdm_tbl[*pgw_tdm_idx] = swap_array[*z]; 2068 (*pgw_tdm_idx)++; 2069 (*z)--; 2070 pgw_tdm_idx_lookback++; 2071 LOG_VERBOSE(BSL_LS_SOC_TDM, 2072 (BSL_META("TDM: _____DEBUG: LIFO index pointer is %0d\n"), *z)); 2073 } 2074 while ((*z) > 0 && 2075 pgw_tdm_tbl[(*pgw_tdm_idx)-1] != swap_array[*z] && 2076 pgw_tdm_tbl[(*pgw_tdm_idx)-1] != TDM_TD2_OVS_TOKEN && 2077 (pgw_tdm_idx_lookback < (pgw_tdm_idx_sub-l1_ovs_cnt))) 2078 { 2079 LOG_VERBOSE(BSL_LS_SOC_TDM, 2080 (BSL_META("TDM: Pipe : %0d priority dequeuing from" 2081 "LIFO swap buffer, pointer index %0d, to pgw " 2082 "tdm tbl element #0%0d, content is %0d\n"), 2083 upperlimit, *z, *pgw_tdm_idx, swap_array[*z])); 2084 pgw_tdm_tbl[*pgw_tdm_idx] = swap_array[*z]; 2085 (*pgw_tdm_idx)++; 2086 (*z)--; 2087 pgw_tdm_idx_lookback++; 2088 LOG_VERBOSE(BSL_LS_SOC_TDM, 2089 (BSL_META("TDM: _____DEBUG: LIFO index pointer is %0d\n"), *z)); 2090 } 2091 if ((wc_array[*cur_idx][subp] != pgw_tdm_tbl[(*pgw_tdm_idx)-1] || (*pgw_tdm_idx)==0) && 2092 (pgw_tdm_idx_lookback < (pgw_tdm_idx_sub-l1_ovs_cnt))) 2093 { 2094 pgw_tdm_tbl[*pgw_tdm_idx] = wc_array[*cur_idx][subp]; 2095 LOG_VERBOSE(BSL_LS_SOC_TDM, 2096 (BSL_META("TDM: Pipe : %0d the pgw tdm tbl element #0%0d, " 2097 "content is %0d\n"), 2098 upperlimit, *pgw_tdm_idx, pgw_tdm_tbl[*pgw_tdm_idx])); 2099 (*pgw_tdm_idx)++; 2100 (*cur_idx)++; 2101 pgw_tdm_idx_lookback++; 2102 } 2103 else 2104 { 2105 (*z)++; 2106 swap_array[*z] = wc_array[*cur_idx][subp]; 2107 LOG_VERBOSE(BSL_LS_SOC_TDM, 2108 (BSL_META("TDM: Pipe : %0d pushed port %0d into " 2109 "LIFO swap buffer at index %0d\n"), 2110 upperlimit, wc_array[*cur_idx][subp], *z)); 2111 (*cur_idx)++; 2112 } 2113 } 2114 break; 2115 case 2: 2116 LOG_VERBOSE(BSL_LS_SOC_TDM, 2117 (BSL_META("TDM: _____VERBOSE: the port is OVERSUBSCRIBED\n"))); 2118 LOG_VERBOSE(BSL_LS_SOC_TDM, 2119 (BSL_META("TDM: the ovs_tdm_idx is %0d\n"), *ovs_tdm_idx)); 2120 LOG_VERBOSE(BSL_LS_SOC_TDM, 2121 (BSL_META("TDM: the cur_idx is %0d\n"), *cur_idx)); 2122 ovs_tdm_tbl[*ovs_tdm_idx] = wc_array[*cur_idx][subp]; 2123 LOG_VERBOSE(BSL_LS_SOC_TDM, 2124 (BSL_META("TDM: Pipe : %0d the ovs tdm tbl element #0%0d, " 2125 "content is %0d\n"), 2126 upperlimit, *ovs_tdm_idx, ovs_tdm_tbl[*ovs_tdm_idx])); 2127 (*ovs_tdm_idx)++; 2128 if (subp != 0 && port_state_map[(wc_array[*cur_idx][subp-1])-1] == 1) 2129 { 2130 pgw_tdm_tbl[*pgw_tdm_idx] = TDM_TD2_OVS_TOKEN; 2131 (*pgw_tdm_idx)++; 2132 pgw_tdm_idx_lookback++; 2133 } 2134 (*cur_idx)++; 2135 break; 2136 } 2137 2138 /* chopping block */ 2139 while ((*cur_idx < upperlimit) && ((wc_array[*cur_idx][subp] == TDM_TD2_NUM_EXT_PORTS) || (wc_array[*cur_idx][subp] == TDM_TD2_MGM_TOKEN))) 2140 { 2141 (*cur_idx)++; 2142 } 2143 if (*cur_idx >= upperlimit) 2144 { 2145 /* table post processing */ 2146 LOG_VERBOSE(BSL_LS_SOC_TDM, 2147 (BSL_META("TDM: _____DEBUG: entering post-processing 2, " 2148 "executing lookback %0d against subset limit %0d\n"), 2149 pgw_tdm_idx_lookback, pgw_tdm_idx_sub)); 2150 if (l1_ovs_cnt > 0) 2151 { 2152 int ovs_pad_iter = 0; 2153 while (ovs_pad_iter < l1_ovs_cnt && pgw_tdm_idx_lookback < pgw_tdm_idx_sub) 2154 { 2155 pgw_tdm_tbl[*pgw_tdm_idx] = TDM_TD2_OVS_TOKEN; 2156 LOG_VERBOSE(BSL_LS_SOC_TDM, 2157 (BSL_META("TDM: Pipe : %0d the pgw tdm tbl element #0%0d, " 2158 "insert OVS token\n"), upperlimit, *pgw_tdm_idx)); 2159 (*pgw_tdm_idx)++; 2160 pgw_tdm_idx_lookback++; 2161 ovs_pad_iter++; 2162 } 2163 } 2164 if (pad_40g_in_480g==TDM_TD2_TRUE) { 2165 /* at 480G, TDM must be padded to max length or underrun */ 2166 while ( (bw<=480) && (pgw_tdm_idx_sub > pgw_tdm_idx_lookback) ) 2167 { 2168 pgw_tdm_tbl[*pgw_tdm_idx] = TDM_TD2_OVS_TOKEN; 2169 (*pgw_tdm_idx)++; 2170 pgw_tdm_idx_lookback++; 2171 if (pgw_tdm_idx_lookback >= pgw_tdm_idx_sub) break; 2172 } 2173 } 2174 2175 return 1; 2176 } 2177 sm_iter++; 2178 } 2179 2180 } 2181 else if ( (32-((10*num_lr_10)+(20*num_lr_20)+(10*l1_ovs_cnt))) >= num_lr_1 ) 2182 { 2183 LOG_VERBOSE(BSL_LS_SOC_TDM, 2184 (BSL_META("TDM: _____VERBOSE: using per quadrant granularity reduction\n"))); 2185 for (gestalt_id_iter = iter3; gestalt_id_iter < stop1; gestalt_id_iter++) 2186 { 2187 if ( port_state_map[gestalt_id_iter] == 1 && 2188 port_state_map[gestalt_id_iter+1] != 3 && 2189 (speed[gestalt_id_iter+1]==TDM_TD2_SPEED_10G || speed[gestalt_id_iter+1]==TDM_TD2_SPEED_10G_DUAL || speed[gestalt_id_iter+1]==TDM_TD2_SPEED_10G_XAUI) ) 2190 gestalt_id = (gestalt_id_iter + 1); 2191 } 2192 2193 LOG_VERBOSE(BSL_LS_SOC_TDM, 2194 (BSL_META("TDM: _____VERBOSE: scheduling all 1G in line rate as " 2195 "1G granularity slots\n"))); 2196 max_tdm_len=((num_lr_1)+(10*num_lr_10)+(20*num_lr_20)); 2197 pgw_tdm_idx_sub=8; 2198 for (l=0; l<num_lr_10; l++) 2199 { 2200 for (gestalt_iter = 0; gestalt_iter < 5; gestalt_iter++) 2201 { 2202 gestalt_tag = TDM_scheduler_PQ((((max_tdm_len/2)*10)/5) * gestalt_iter); 2203 pgw_tdm_tbl[gestalt_tag+l] = gestalt_id; 2204 pgw_tdm_tbl[gestalt_tag+11+l] = gestalt_id; 2205 } 2206 } 2207 sm_iter=0; 2208 while (sm_iter < TDM_TD2_NUM_EXT_PORTS) 2209 { 2210 while ((*cur_idx < upperlimit) && ((wc_array[*cur_idx][subp] == TDM_TD2_NUM_EXT_PORTS) || (wc_array[*cur_idx][subp] == TDM_TD2_MGM_TOKEN))) 2211 { 2212 (*cur_idx)++; 2213 } 2214 if (*cur_idx >= upperlimit) 2215 { 2216 int pp_iter; 2217 for (pp_iter = 0; pp_iter < max_tdm_len; pp_iter++) if (pgw_tdm_tbl[pp_iter] == TDM_TD2_NUM_EXT_PORTS) pgw_tdm_tbl[pp_iter] = TDM_TD2_OVS_TOKEN; 2218 return 1; 2219 } 2220 2221 LOG_VERBOSE(BSL_LS_SOC_TDM, 2222 (BSL_META("TDM: ----------------------------------------------------------------\n"))); 2223 LOG_VERBOSE(BSL_LS_SOC_TDM, 2224 (BSL_META("TDM: _____VERBOSE: the present x1G port is %0d\n"), 2225 wc_array[*cur_idx][subp])); 2226 2227 switch(port_state_map[(wc_array[*cur_idx][subp])-1]) 2228 { 2229 case 0: 2230 LOG_VERBOSE(BSL_LS_SOC_TDM, 2231 (BSL_META("TDM: _____VERBOSE: the port is DISABLED\n"))); 2232 LOG_VERBOSE(BSL_LS_SOC_TDM, 2233 (BSL_META("TDM: Pipe : %0d the pgw tdm tbl element #0%0d " 2234 "would be an invalid port\n"), upperlimit, *pgw_tdm_idx)); 2235 if (pgw_tdm_tbl[*pgw_tdm_idx] != gestalt_id) 2236 { 2237 pgw_tdm_tbl[*pgw_tdm_idx] = TDM_TD2_OVS_TOKEN; 2238 (*pgw_tdm_idx)++; 2239 (*cur_idx)++; 2240 } 2241 else if (num_ovs > 0) 2242 { 2243 (*z)++; 2244 swap_array[*z] = TDM_TD2_OVS_TOKEN; 2245 LOG_VERBOSE(BSL_LS_SOC_TDM, 2246 (BSL_META("TDM: Pipe : %0d pushed an OVS token into " 2247 "LIFO swap buffer at index %0d\n"), upperlimit, *z)); 2248 (*cur_idx)++; 2249 } 2250 break; 2251 case 1: 2252 LOG_VERBOSE(BSL_LS_SOC_TDM, 2253 (BSL_META("TDM: _____VERBOSE: the port is LINE RATE\n"))); 2254 while (pgw_tdm_tbl[(*pgw_tdm_idx)] == gestalt_id) (*pgw_tdm_idx)++; 2255 while (swap_array[*z] == gestalt_id) 2256 { 2257 swap_array[*z] = 0; 2258 (*z)--; 2259 } 2260 if (num_ovs == 0) 2261 { 2262 LOG_VERBOSE(BSL_LS_SOC_TDM, 2263 (BSL_META("TDM: the cur_idx is %0d\n"), *cur_idx)); 2264 2265 while ((*z) > 0 && 2266 pgw_tdm_tbl[(*pgw_tdm_idx)-1] != swap_array[*z]) 2267 { 2268 LOG_VERBOSE(BSL_LS_SOC_TDM, 2269 (BSL_META("TDM: Pipe : %0d priority dequeuing from " 2270 "LIFO swap buffer, pointer index %0d, to pgw " 2271 "tdm tbl element #0%0d, content is %0d\n"), 2272 upperlimit, *z, *pgw_tdm_idx, swap_array[*z])); 2273 pgw_tdm_tbl[*pgw_tdm_idx] = swap_array[*z]; 2274 (*pgw_tdm_idx)++; 2275 (*z)--; 2276 LOG_VERBOSE(BSL_LS_SOC_TDM, 2277 (BSL_META("TDM: _____DEBUG: LIFO index pointer is %0d\n"), *z)); 2278 } 2279 if ((wc_array[*cur_idx][subp] != pgw_tdm_tbl[(*pgw_tdm_idx)-1] || (*pgw_tdm_idx)==0)) 2280 { 2281 pgw_tdm_tbl[*pgw_tdm_idx] = wc_array[*cur_idx][subp]; 2282 LOG_VERBOSE(BSL_LS_SOC_TDM, 2283 (BSL_META("TDM: Pipe : %0d the pgw tdm tbl element #0%0d, " 2284 "content is %0d\n"), 2285 upperlimit, *pgw_tdm_idx, pgw_tdm_tbl[*pgw_tdm_idx])); 2286 (*pgw_tdm_idx)++; 2287 (*cur_idx)++; 2288 } 2289 else if (wc_array[*cur_idx][subp] != gestalt_id) 2290 { 2291 (*z)++; 2292 swap_array[*z] = wc_array[*cur_idx][subp]; 2293 LOG_VERBOSE(BSL_LS_SOC_TDM, 2294 (BSL_META("TDM: Pipe : %0d pushed port %0d into " 2295 "LIFO swap buffer at index %0d\n"), 2296 upperlimit, wc_array[*cur_idx][subp], *z)); 2297 (*cur_idx)++; 2298 } 2299 else (*cur_idx)++; 2300 } 2301 else if (num_ovs > 0) 2302 { 2303 LOG_VERBOSE(BSL_LS_SOC_TDM, 2304 (BSL_META("TDM: the cur_idx is %0d\n"), *cur_idx)); 2305 2306 if ((*z) > 0 && 2307 pgw_tdm_tbl[(*pgw_tdm_idx)-2] != swap_array[*z] && 2308 pgw_tdm_tbl[(*pgw_tdm_idx)-1] == TDM_TD2_OVS_TOKEN) 2309 { 2310 LOG_VERBOSE(BSL_LS_SOC_TDM, 2311 (BSL_META("TDM: Pipe : %0d priority dequeuing from " 2312 "LIFO swap buffer, pointer index %0d, to pgw " 2313 "tdm tbl element #0%0d, content is %0d\n"), 2314 upperlimit, *z, *pgw_tdm_idx, swap_array[*z])); 2315 pgw_tdm_tbl[*pgw_tdm_idx] = swap_array[*z]; 2316 (*pgw_tdm_idx)++; 2317 (*z)--; 2318 LOG_VERBOSE(BSL_LS_SOC_TDM, 2319 (BSL_META("TDM: _____DEBUG: LIFO index pointer is %0d\n"), *z)); 2320 } 2321 while ((*z) > 0 && 2322 pgw_tdm_tbl[(*pgw_tdm_idx)-1] != swap_array[*z] && 2323 pgw_tdm_tbl[(*pgw_tdm_idx)-1] != TDM_TD2_OVS_TOKEN) 2324 { 2325 LOG_VERBOSE(BSL_LS_SOC_TDM, 2326 (BSL_META("TDM: Pipe : %0d priority dequeuing from " 2327 "LIFO swap buffer, pointer index %0d, to pgw " 2328 "tdm tbl element #0%0d, content is %0d\n"), 2329 upperlimit, *z, *pgw_tdm_idx, swap_array[*z])); 2330 pgw_tdm_tbl[*pgw_tdm_idx] = swap_array[*z]; 2331 (*pgw_tdm_idx)++; 2332 (*z)--; 2333 LOG_VERBOSE(BSL_LS_SOC_TDM, 2334 (BSL_META("TDM: _____DEBUG: LIFO index pointer is %0d\n"), *z)); 2335 } 2336 if ((wc_array[*cur_idx][subp] != pgw_tdm_tbl[(*pgw_tdm_idx)-1] || (*pgw_tdm_idx)==0) && 2337 wc_array[*cur_idx][subp] != gestalt_id) 2338 { 2339 pgw_tdm_tbl[*pgw_tdm_idx] = wc_array[*cur_idx][subp]; 2340 LOG_VERBOSE(BSL_LS_SOC_TDM, 2341 (BSL_META("TDM: Pipe : %0d the pgw tdm tbl element #0%0d, " 2342 "content is %0d\n"), 2343 upperlimit, *pgw_tdm_idx, pgw_tdm_tbl[*pgw_tdm_idx])); 2344 (*pgw_tdm_idx)++; 2345 (*cur_idx)++; 2346 } 2347 else if (wc_array[*cur_idx][subp] != gestalt_id) 2348 { 2349 (*z)++; 2350 swap_array[*z] = wc_array[*cur_idx][subp]; 2351 LOG_VERBOSE(BSL_LS_SOC_TDM, 2352 (BSL_META("TDM: Pipe : %0d pushed port %0d into LIFO swap buffer at index %0d\n"), upperlimit, wc_array[*cur_idx][subp], *z)); 2353 (*cur_idx)++; 2354 } 2355 else (*cur_idx)++; 2356 } 2357 break; 2358 case 2: 2359 LOG_VERBOSE(BSL_LS_SOC_TDM, 2360 (BSL_META("TDM: _____VERBOSE: the port is OVERSUBSCRIBED\n"))); 2361 LOG_VERBOSE(BSL_LS_SOC_TDM, 2362 (BSL_META("TDM: the ovs_tdm_idx is %0d\n"), *ovs_tdm_idx)); 2363 LOG_VERBOSE(BSL_LS_SOC_TDM, 2364 (BSL_META("TDM: the cur_idx is %0d\n"), *cur_idx)); 2365 ovs_tdm_tbl[*ovs_tdm_idx] = wc_array[*cur_idx][subp]; 2366 LOG_VERBOSE(BSL_LS_SOC_TDM, 2367 (BSL_META("TDM: Pipe : %0d the ovs tdm tbl element #0%0d, " 2368 "content is %0d\n"), 2369 upperlimit, *ovs_tdm_idx, ovs_tdm_tbl[*ovs_tdm_idx])); 2370 (*ovs_tdm_idx)++; 2371 (*cur_idx)++; 2372 break; 2373 } 2374 while ((*cur_idx < upperlimit) && ((wc_array[*cur_idx][subp] == TDM_TD2_NUM_EXT_PORTS) || (wc_array[*cur_idx][subp] == TDM_TD2_MGM_TOKEN))) 2375 { 2376 (*cur_idx)++; 2377 } 2378 if (*cur_idx >= upperlimit) 2379 { 2380 int pp_iter; 2381 for (pp_iter = 0; pp_iter < max_tdm_len; pp_iter++) if (pgw_tdm_tbl[pp_iter] == TDM_TD2_NUM_EXT_PORTS) pgw_tdm_tbl[pp_iter] = TDM_TD2_OVS_TOKEN; 2382 return 1; 2383 } 2384 2385 sm_iter++; 2386 } 2387 } 2388 else { 2389 LOG_ERROR(BSL_LS_SOC_TDM, 2390 (BSL_META("TDM: __________FATAL ERROR: cannot schedule 1G ports or " 2391 "unsupported configuration\n"))); 2392 return 0; 2393 } 2394 2395 2396 return 1; 2397 } 2398 /* obligate oversubscription */ 2399 else if ((l1_tdm_len > max_tdm_len) && (num_ovs == 0)) 2400 { 2401 int xcount; 2402 LOG_WARN(BSL_LS_SOC_TDM, 2403 (BSL_META("TDM: _____WARNING: applying obligate oversubscription correction\n"))); 2404 for (xcount = 0; xcount < max_tdm_len; xcount++) 2405 { 2406 /* chopping block */ 2407 while ((*cur_idx < upperlimit) && ((wc_array[*cur_idx][subp] == TDM_TD2_NUM_EXT_PORTS) || (wc_array[*cur_idx][subp] == TDM_TD2_MGM_TOKEN))) 2408 { 2409 (*cur_idx)++; 2410 } 2411 if (*cur_idx >= upperlimit) 2412 { 2413 return 1; 2414 } 2415 if ((*pgw_tdm_idx) < max_tdm_len) 2416 { 2417 pgw_tdm_tbl[*pgw_tdm_idx] = TDM_TD2_OVS_TOKEN; 2418 LOG_VERBOSE(BSL_LS_SOC_TDM, 2419 (BSL_META("TDM: _____VERBOSE: Pipe : %0d the pgw tdm tbl element #0%0d " 2420 "has an oversub token placed\n"), upperlimit, *pgw_tdm_idx)); 2421 (*pgw_tdm_idx)++; 2422 } 2423 ovs_tdm_tbl[*ovs_tdm_idx] = wc_array[*cur_idx][subp]; 2424 LOG_VERBOSE(BSL_LS_SOC_TDM, 2425 (BSL_META("TDM: _____VERBOSE: Pipe : %0d the ovs tdm tbl element #0%0d, " 2426 "content is %0d\n"), 2427 upperlimit, *ovs_tdm_idx, ovs_tdm_tbl[*ovs_tdm_idx])); 2428 (*ovs_tdm_idx)++; 2429 (*cur_idx)++; 2430 /* chopping block */ 2431 while ((*cur_idx < upperlimit) && ((wc_array[*cur_idx][subp] == TDM_TD2_NUM_EXT_PORTS) || (wc_array[*cur_idx][subp] == TDM_TD2_MGM_TOKEN))) 2432 { 2433 (*cur_idx)++; 2434 } 2435 if (*cur_idx >= upperlimit) 2436 { 2437 return 1; 2438 } 2439 } 2440 return 1; 2441 } 2442 /* invalid case */ 2443 else if (l1_tdm_len >= max_tdm_len && num_ovs != 0) 2444 { 2445 LOG_ERROR(BSL_LS_SOC_TDM, 2446 (BSL_META("TDM: _____ERROR: Pipe : %0d, FATAL error, invalid configuration\n"), 2447 upperlimit)); 2448 return 0; 2449 } 2450 /* 100G dominating case */ 2451 else if ((num_lr_100 + num_lr_120 == 1) && (num_lr_10)+((num_lr_20)*2)+((num_lr_40)*4) < ((num_lr_100)*10)+((num_lr_120)*12)) 2452 { 2453 LOG_WARN(BSL_LS_SOC_TDM, 2454 (BSL_META("TDM: _____WARNING: applying dominant 100G correction\n"))); 2455 for (gestalt_id_iter = iter3; gestalt_id_iter < stop1; gestalt_id_iter++) 2456 { 2457 if (port_state_map[gestalt_id_iter] == 1 && 2458 port_state_map[gestalt_id_iter+1] == 3 && 2459 port_state_map[gestalt_id_iter+2] == 3 && 2460 port_state_map[gestalt_id_iter+4] == 3 && 2461 port_state_map[gestalt_id_iter+9] == 3) gestalt_id = (gestalt_id_iter + 1); 2462 } 2463 if (num_lr_100 == 1 && num_lr_120 == 0) 2464 { 2465 for (gestalt_iter = 0; gestalt_iter < 5; gestalt_iter++) 2466 { 2467 gestalt_tag = TDM_scheduler_PQ((((max_tdm_len/2)*10)/5) * gestalt_iter); 2468 /* gestalt_tag = TDM_scheduler_PQ((((float) (max_tdm_len/2))/((float) 5.0)) * gestalt_iter); */ 2469 pgw_tdm_tbl[gestalt_tag] = gestalt_id; 2470 pgw_tdm_tbl[gestalt_tag+12] = gestalt_id; 2471 } 2472 } 2473 else if (num_lr_100 == 0 && num_lr_120 == 1) 2474 { 2475 for (gestalt_iter = 0; gestalt_iter < 12; gestalt_iter++) 2476 { 2477 gestalt_tag = TDM_scheduler_PQ((((max_tdm_len-1)*10)/11) * gestalt_iter); 2478 /* gestalt_tag = TDM_scheduler_PQ((((float) max_tdm_len-1)/((float) 11.0)) * gestalt_iter); */ 2479 pgw_tdm_tbl[gestalt_tag] = gestalt_id; 2480 } 2481 } 2482 while (sm_iter < TDM_TD2_NUM_EXT_PORTS) 2483 { 2484 /* chopping block */ 2485 while ((*cur_idx < upperlimit) && ((wc_array[*cur_idx][subp] == TDM_TD2_NUM_EXT_PORTS) || (wc_array[*cur_idx][subp] == TDM_TD2_MGM_TOKEN))) 2486 { 2487 (*cur_idx)++; 2488 } 2489 if (*cur_idx >= upperlimit) 2490 { 2491 int pp_iter; 2492 for (pp_iter = 0; pp_iter < max_tdm_len; pp_iter++) if (pgw_tdm_tbl[pp_iter] == TDM_TD2_NUM_EXT_PORTS) pgw_tdm_tbl[pp_iter] = TDM_TD2_OVS_TOKEN; 2493 return 1; 2494 } 2495 2496 LOG_VERBOSE(BSL_LS_SOC_TDM, 2497 (BSL_META("TDM: ----------------------------------------------------------------\n"))); 2498 LOG_VERBOSE(BSL_LS_SOC_TDM, 2499 (BSL_META("TDM: _____VERBOSE: the present port is %0d, speed %0d\n"), 2500 wc_array[*cur_idx][subp], speed[wc_array[*cur_idx][subp]])); 2501 2502 /* port state machine */ 2503 switch(port_state_map[(wc_array[*cur_idx][subp])-1]) 2504 { 2505 case 0: 2506 LOG_VERBOSE(BSL_LS_SOC_TDM, 2507 (BSL_META("TDM: _____VERBOSE: the port is DISABLED\n"))); 2508 LOG_VERBOSE(BSL_LS_SOC_TDM, 2509 (BSL_META("TDM: Pipe : %0d the pgw tdm tbl element #0%0d " 2510 "would be an invalid port\n"), upperlimit, *pgw_tdm_idx)); 2511 if (pgw_tdm_tbl[*pgw_tdm_idx] != gestalt_id) 2512 { 2513 pgw_tdm_tbl[*pgw_tdm_idx] = TDM_TD2_OVS_TOKEN; 2514 (*pgw_tdm_idx)++; 2515 (*cur_idx)++; 2516 } 2517 else if (num_ovs > 0) 2518 { 2519 (*z)++; 2520 swap_array[*z] = TDM_TD2_OVS_TOKEN; 2521 LOG_VERBOSE(BSL_LS_SOC_TDM, 2522 (BSL_META("TDM: Pipe : %0d pushed an OVS token into " 2523 "LIFO swap buffer at index %0d\n"), upperlimit, *z)); 2524 (*cur_idx)++; 2525 } 2526 break; 2527 /* this only iterates by active port (not lane) so it should never see this */ 2528 /* case 3: 2529 LOG_VERBOSE(BSL_LS_SOC_TDM, 2530 (BSL_META("TDM: _____VERBOSE: the port is part of a DUAL/QUAD/100G\n"))); */ 2531 case 1: 2532 LOG_VERBOSE(BSL_LS_SOC_TDM, 2533 (BSL_META("TDM: _____VERBOSE: the port is LINE RATE\n"))); 2534 while (pgw_tdm_tbl[(*pgw_tdm_idx)] == gestalt_id) (*pgw_tdm_idx)++; 2535 while (swap_array[*z] == gestalt_id) 2536 { 2537 swap_array[*z] = 0; 2538 (*z)--; 2539 } 2540 if (num_ovs == 0) 2541 { 2542 LOG_VERBOSE(BSL_LS_SOC_TDM, 2543 (BSL_META("TDM: the cur_idx is %0d\n"), *cur_idx)); 2544 2545 while ((*z) > 0 && 2546 pgw_tdm_tbl[(*pgw_tdm_idx)-1] != swap_array[*z]) 2547 { 2548 LOG_VERBOSE(BSL_LS_SOC_TDM, 2549 (BSL_META("TDM: Pipe : %0d priority dequeuing from " 2550 "LIFO swap buffer, pointer index %0d, to " 2551 "pgw tdm tbl element #0%0d, content is %0d\n"), 2552 upperlimit, *z, *pgw_tdm_idx, swap_array[*z])); 2553 pgw_tdm_tbl[*pgw_tdm_idx] = swap_array[*z]; 2554 (*pgw_tdm_idx)++; 2555 (*z)--; 2556 LOG_VERBOSE(BSL_LS_SOC_TDM, 2557 (BSL_META("TDM: _____DEBUG: LIFO index pointer is %0d\n"), *z)); 2558 } 2559 if ((wc_array[*cur_idx][subp] != pgw_tdm_tbl[(*pgw_tdm_idx)-1] || (*pgw_tdm_idx)==0)) 2560 { 2561 pgw_tdm_tbl[*pgw_tdm_idx] = wc_array[*cur_idx][subp]; 2562 LOG_VERBOSE(BSL_LS_SOC_TDM, 2563 (BSL_META("TDM: Pipe : %0d the pgw tdm tbl element #0%0d, " 2564 "content is %0d\n"), 2565 upperlimit, *pgw_tdm_idx, pgw_tdm_tbl[*pgw_tdm_idx])); 2566 (*pgw_tdm_idx)++; 2567 (*cur_idx)++; 2568 } 2569 else if (wc_array[*cur_idx][subp] != gestalt_id) 2570 { 2571 (*z)++; 2572 swap_array[*z] = wc_array[*cur_idx][subp]; 2573 LOG_VERBOSE(BSL_LS_SOC_TDM, 2574 (BSL_META("TDM: Pipe : %0d pushed port %0d into " 2575 "LIFO swap buffer at index %0d\n"), 2576 upperlimit, wc_array[*cur_idx][subp], *z)); 2577 (*cur_idx)++; 2578 } 2579 else (*cur_idx)++; 2580 } 2581 else if (num_ovs > 0) 2582 { 2583 LOG_VERBOSE(BSL_LS_SOC_TDM, 2584 (BSL_META("TDM: the cur_idx is %0d\n"), *cur_idx)); 2585 2586 if ((*z) > 0 && 2587 pgw_tdm_tbl[(*pgw_tdm_idx)-2] != swap_array[*z] && 2588 pgw_tdm_tbl[(*pgw_tdm_idx)-1] == TDM_TD2_OVS_TOKEN) 2589 { 2590 LOG_VERBOSE(BSL_LS_SOC_TDM, 2591 (BSL_META("TDM: Pipe : %0d priority dequeuing from" 2592 "LIFO swap buffer, pointer index %0d, to " 2593 "pgw tdm tbl element #0%0d, content is %0d\n"), 2594 upperlimit, *z, *pgw_tdm_idx, swap_array[*z])); 2595 pgw_tdm_tbl[*pgw_tdm_idx] = swap_array[*z]; 2596 (*pgw_tdm_idx)++; 2597 (*z)--; 2598 LOG_VERBOSE(BSL_LS_SOC_TDM, 2599 (BSL_META("TDM: _____DEBUG: LIFO index pointer is %0d\n"), *z)); 2600 } 2601 while ((*z) > 0 && 2602 pgw_tdm_tbl[(*pgw_tdm_idx)-1] != swap_array[*z] && 2603 pgw_tdm_tbl[(*pgw_tdm_idx)-1] != TDM_TD2_OVS_TOKEN) 2604 { 2605 LOG_VERBOSE(BSL_LS_SOC_TDM, 2606 (BSL_META("TDM: Pipe : %0d priority dequeuing from " 2607 "LIFO swap buffer, pointer index %0d, to " 2608 "pgw tdm tbl element #0%0d, content is %0d\n"), 2609 upperlimit, *z, *pgw_tdm_idx, swap_array[*z])); 2610 pgw_tdm_tbl[*pgw_tdm_idx] = swap_array[*z]; 2611 (*pgw_tdm_idx)++; 2612 (*z)--; 2613 LOG_VERBOSE(BSL_LS_SOC_TDM, 2614 (BSL_META("TDM: _____DEBUG: LIFO index pointer is %0d\n"), *z)); 2615 } 2616 if ((wc_array[*cur_idx][subp] != pgw_tdm_tbl[(*pgw_tdm_idx)-1] || (*pgw_tdm_idx)==0) && 2617 wc_array[*cur_idx][subp] != gestalt_id) 2618 { 2619 pgw_tdm_tbl[*pgw_tdm_idx] = wc_array[*cur_idx][subp]; 2620 LOG_VERBOSE(BSL_LS_SOC_TDM, 2621 (BSL_META("TDM: Pipe : %0d the pgw tdm tbl element #0%0d, " 2622 "content is %0d\n"), 2623 upperlimit, *pgw_tdm_idx, pgw_tdm_tbl[*pgw_tdm_idx])); 2624 (*pgw_tdm_idx)++; 2625 (*cur_idx)++; 2626 } 2627 else if (wc_array[*cur_idx][subp] != gestalt_id) 2628 { 2629 (*z)++; 2630 swap_array[*z] = wc_array[*cur_idx][subp]; 2631 LOG_VERBOSE(BSL_LS_SOC_TDM, 2632 (BSL_META("TDM: Pipe : %0d pushed port %0d into " 2633 "LIFO swap buffer at index %0d\n"), 2634 upperlimit, wc_array[*cur_idx][subp], *z)); 2635 (*cur_idx)++; 2636 } 2637 else (*cur_idx)++; 2638 } 2639 break; 2640 case 2: 2641 LOG_VERBOSE(BSL_LS_SOC_TDM, 2642 (BSL_META("TDM: _____VERBOSE: the port is OVERSUBSCRIBED\n"))); 2643 LOG_VERBOSE(BSL_LS_SOC_TDM, 2644 (BSL_META("TDM: the ovs_tdm_idx is %0d\n"), *ovs_tdm_idx)); 2645 LOG_VERBOSE(BSL_LS_SOC_TDM, 2646 (BSL_META("TDM: the cur_idx is %0d\n"), *cur_idx)); 2647 ovs_tdm_tbl[*ovs_tdm_idx] = wc_array[*cur_idx][subp]; 2648 LOG_VERBOSE(BSL_LS_SOC_TDM, 2649 (BSL_META("TDM: Pipe : %0d the ovs tdm tbl element #0%0d, " 2650 "content is %0d\n"), 2651 upperlimit, *ovs_tdm_idx, ovs_tdm_tbl[*ovs_tdm_idx])); 2652 (*ovs_tdm_idx)++; 2653 (*cur_idx)++; 2654 break; 2655 } 2656 2657 /* chopping block */ 2658 while ((*cur_idx < upperlimit) && ((wc_array[*cur_idx][subp] == TDM_TD2_NUM_EXT_PORTS) || (wc_array[*cur_idx][subp] == TDM_TD2_MGM_TOKEN))) 2659 { 2660 (*cur_idx)++; 2661 } 2662 if (*cur_idx >= upperlimit) 2663 { 2664 int pp_iter; 2665 for (pp_iter = 0; pp_iter < max_tdm_len; pp_iter++) if (pgw_tdm_tbl[pp_iter] == TDM_TD2_NUM_EXT_PORTS) pgw_tdm_tbl[pp_iter] = TDM_TD2_OVS_TOKEN; 2666 return 1; 2667 } 2668 2669 sm_iter++; 2670 } 2671 return 1; 2672 } 2673 /* standard case */ 2674 else 2675 { 2676 int pgw_tdm_idx_lookback = 0; 2677 int sm_iter = 0; 2678 while (sm_iter < TDM_TD2_NUM_EXT_PORTS) 2679 { 2680 /* chopping block */ 2681 while ((*cur_idx < upperlimit) && ((wc_array[*cur_idx][subp] == TDM_TD2_NUM_EXT_PORTS) || (wc_array[*cur_idx][subp] == TDM_TD2_MGM_TOKEN))) 2682 { 2683 (*cur_idx)++; 2684 } 2685 if (*cur_idx >= upperlimit) 2686 { 2687 /* table post processing */ 2688 LOG_VERBOSE(BSL_LS_SOC_TDM, 2689 (BSL_META("TDM: _____DEBUG: entering post-processing 1, " 2690 "executing lookback %0d against subset limit %0d\n"), 2691 pgw_tdm_idx_lookback, pgw_tdm_idx_sub)); 2692 if (l1_ovs_cnt > 0) 2693 { 2694 int ovs_pad_iter = 0; 2695 while (ovs_pad_iter < l1_ovs_cnt && pgw_tdm_idx_lookback < pgw_tdm_idx_sub) 2696 { 2697 pgw_tdm_tbl[*pgw_tdm_idx] = TDM_TD2_OVS_TOKEN; 2698 LOG_VERBOSE(BSL_LS_SOC_TDM, 2699 (BSL_META("TDM: Pipe : %0d the pgw tdm tbl element #0%0d, " 2700 "insert OVS token\n"), upperlimit, *pgw_tdm_idx)); 2701 (*pgw_tdm_idx)++; 2702 pgw_tdm_idx_lookback++; 2703 ovs_pad_iter++; 2704 } 2705 } 2706 if (pad_40g_in_480g==TDM_TD2_TRUE) { 2707 /* at 480G, TDM must be padded to max length or underrun */ 2708 while ( (bw<=480) && (pgw_tdm_idx_sub > pgw_tdm_idx_lookback) ) 2709 { 2710 pgw_tdm_tbl[*pgw_tdm_idx] = TDM_TD2_OVS_TOKEN; 2711 (*pgw_tdm_idx)++; 2712 pgw_tdm_idx_lookback++; 2713 if (pgw_tdm_idx_lookback >= pgw_tdm_idx_sub) break; 2714 } 2715 } 2716 2717 return 1; 2718 } 2719 2720 LOG_VERBOSE(BSL_LS_SOC_TDM, 2721 (BSL_META("TDM: ----------------------------------------------------------------\n"))); 2722 LOG_VERBOSE(BSL_LS_SOC_TDM, 2723 (BSL_META("TDM: _____DEBUG: the present port is %0d, speed %0d\n"), 2724 wc_array[*cur_idx][subp],speed[wc_array[*cur_idx][subp]])); 2725 2726 /* port state machine */ 2727 switch(port_state_map[(wc_array[*cur_idx][subp])-1]) 2728 { 2729 case 0: 2730 LOG_VERBOSE(BSL_LS_SOC_TDM, 2731 (BSL_META("TDM: _____VERBOSE: the port is DISABLED\n"))); 2732 LOG_VERBOSE(BSL_LS_SOC_TDM, 2733 (BSL_META("TDM: Pipe : %0d the pgw tdm tbl element #0%0d would be an invalid port\n"), upperlimit, *pgw_tdm_idx)); 2734 if (num_lr > 0 && num_ovs > 0) 2735 { 2736 pgw_tdm_tbl[*pgw_tdm_idx] = TDM_TD2_OVS_TOKEN; 2737 (*pgw_tdm_idx)++; 2738 pgw_tdm_idx_lookback++; 2739 } 2740 (*cur_idx)++; 2741 break; 2742 /* this only iterates by active port (not lane) so it should never see this */ 2743 /* case 3: 2744 LOG_VERBOSE(BSL_LS_SOC_TDM, 2745 (BSL_META("TDM: _____VERBOSE: the port is part of a DUAL/QUAD/100G\n"))); */ 2746 case 1: 2747 LOG_VERBOSE(BSL_LS_SOC_TDM, 2748 (BSL_META("TDM: _____VERBOSE: the port is LINE RATE\n"))); 2749 if (num_ovs == 0) 2750 { 2751 LOG_VERBOSE(BSL_LS_SOC_TDM, 2752 (BSL_META("TDM: the cur_idx is %0d\n"), *cur_idx)); 2753 2754 while ((*z) > 0 && pgw_tdm_tbl[(*pgw_tdm_idx)-1] != swap_array[*z]) 2755 { 2756 LOG_VERBOSE(BSL_LS_SOC_TDM, 2757 (BSL_META("TDM: Pipe : %0d priority dequeuing from " 2758 "LIFO swap buffer, pointer index %0d, to " 2759 "pgw tdm tbl element #0%0d, content is %0d\n"), 2760 upperlimit, *z, *pgw_tdm_idx, swap_array[*z])); 2761 pgw_tdm_tbl[*pgw_tdm_idx] = swap_array[*z]; 2762 (*pgw_tdm_idx)++; 2763 (*z)--; 2764 LOG_VERBOSE(BSL_LS_SOC_TDM, 2765 (BSL_META("TDM: _____DEBUG: LIFO index pointer is %0d\n"), *z)); 2766 } 2767 if ( num_lr == 1 && num_ovs == 0) { 2768 pgw_tdm_tbl[*pgw_tdm_idx] = wc_array[*cur_idx][subp]; 2769 LOG_VERBOSE(BSL_LS_SOC_TDM, 2770 (BSL_META("TDM: Pipe : %0d the pgw tdm tbl element #0%0d, " 2771 "content is %0d\n"), 2772 upperlimit, *pgw_tdm_idx, pgw_tdm_tbl[*pgw_tdm_idx])); 2773 (*pgw_tdm_idx) += pgw_tdm_idx_sub; 2774 (*cur_idx)++; 2775 } 2776 else if (((*pgw_tdm_idx) > 0 && wc_array[*cur_idx][subp] != pgw_tdm_tbl[(*pgw_tdm_idx)-1]) || 2777 ((*pgw_tdm_idx)==0) ) { 2778 pgw_tdm_tbl[*pgw_tdm_idx] = wc_array[*cur_idx][subp]; 2779 LOG_VERBOSE(BSL_LS_SOC_TDM, 2780 (BSL_META("TDM: Pipe : %0d the pgw tdm tbl element #0%0d, " 2781 "content is %0d\n"), 2782 upperlimit, *pgw_tdm_idx, pgw_tdm_tbl[*pgw_tdm_idx])); 2783 (*pgw_tdm_idx)++; 2784 (*cur_idx)++; 2785 } else { 2786 (*z)++; 2787 swap_array[*z] = wc_array[*cur_idx][subp]; 2788 LOG_VERBOSE(BSL_LS_SOC_TDM, 2789 (BSL_META("TDM: Pipe : %0d pushed port %0d into " 2790 "LIFO swap buffer at index %0d\n"), 2791 upperlimit, wc_array[*cur_idx][subp], *z)); 2792 (*cur_idx)++; 2793 } 2794 /* at 480G the table must be padded or underrun */ 2795 if (bw<=480 && pad_40g_in_480g==TDM_TD2_TRUE) pgw_tdm_idx_lookback++; 2796 /* all faster bandwidths ok */ 2797 else pgw_tdm_idx_lookback = pgw_tdm_idx_sub; 2798 } 2799 else if (num_ovs > 0) 2800 { 2801 LOG_VERBOSE(BSL_LS_SOC_TDM, 2802 (BSL_META("TDM: the cur_idx is %0d\n"), *cur_idx)); 2803 2804 if ((*z) > 0 && 2805 pgw_tdm_tbl[(*pgw_tdm_idx)-2] != swap_array[*z] && 2806 pgw_tdm_tbl[(*pgw_tdm_idx)-1] == TDM_TD2_OVS_TOKEN && 2807 (pgw_tdm_idx_lookback < (pgw_tdm_idx_sub-l1_ovs_cnt))) 2808 { 2809 LOG_VERBOSE(BSL_LS_SOC_TDM, 2810 (BSL_META("TDM: Pipe : %0d priority dequeuing from " 2811 "LIFO swap buffer, pointer index %0d, to " 2812 "pgw tdm tbl element #0%0d, content is %0d\n"), 2813 upperlimit, *z, *pgw_tdm_idx, swap_array[*z])); 2814 pgw_tdm_tbl[*pgw_tdm_idx] = swap_array[*z]; 2815 (*pgw_tdm_idx)++; 2816 (*z)--; 2817 pgw_tdm_idx_lookback++; 2818 LOG_VERBOSE(BSL_LS_SOC_TDM, 2819 (BSL_META("TDM: _____DEBUG: LIFO index pointer is %0d\n"), *z)); 2820 } 2821 while ((*z) > 0 && 2822 pgw_tdm_tbl[(*pgw_tdm_idx)-1] != swap_array[*z] && 2823 pgw_tdm_tbl[(*pgw_tdm_idx)-1] != TDM_TD2_OVS_TOKEN && 2824 (pgw_tdm_idx_lookback < (pgw_tdm_idx_sub-l1_ovs_cnt))) 2825 { 2826 LOG_VERBOSE(BSL_LS_SOC_TDM, 2827 (BSL_META("TDM: Pipe : %0d priority dequeuing from " 2828 "LIFO swap buffer, pointer index %0d, to " 2829 "pgw tdm tbl element #0%0d, content is %0d\n"), 2830 upperlimit, *z, *pgw_tdm_idx, swap_array[*z])); 2831 pgw_tdm_tbl[*pgw_tdm_idx] = swap_array[*z]; 2832 (*pgw_tdm_idx)++; 2833 (*z)--; 2834 pgw_tdm_idx_lookback++; 2835 LOG_VERBOSE(BSL_LS_SOC_TDM, 2836 (BSL_META("TDM: _____DEBUG: LIFO index pointer is %0d\n"), *z)); 2837 } 2838 if ((wc_array[*cur_idx][subp] != pgw_tdm_tbl[(*pgw_tdm_idx)-1] || (*pgw_tdm_idx)==0) && 2839 (pgw_tdm_idx_lookback < (pgw_tdm_idx_sub-l1_ovs_cnt))) 2840 { 2841 pgw_tdm_tbl[*pgw_tdm_idx] = wc_array[*cur_idx][subp]; 2842 LOG_VERBOSE(BSL_LS_SOC_TDM, 2843 (BSL_META("TDM: Pipe : %0d the pgw tdm tbl element #0%0d, " 2844 "content is %0d\n"), 2845 upperlimit, *pgw_tdm_idx, pgw_tdm_tbl[*pgw_tdm_idx])); 2846 (*pgw_tdm_idx)++; 2847 (*cur_idx)++; 2848 pgw_tdm_idx_lookback++; 2849 } 2850 else 2851 { 2852 (*z)++; 2853 swap_array[*z] = wc_array[*cur_idx][subp]; 2854 LOG_VERBOSE(BSL_LS_SOC_TDM, 2855 (BSL_META("TDM: Pipe : %0d pushed port %0d into " 2856 "LIFO swap buffer at index %0d\n"), 2857 upperlimit, wc_array[*cur_idx][subp], *z)); 2858 (*cur_idx)++; 2859 } 2860 } 2861 break; 2862 case 2: 2863 LOG_VERBOSE(BSL_LS_SOC_TDM, 2864 (BSL_META("TDM: _____VERBOSE: the port is OVERSUBSCRIBED\n"))); 2865 LOG_VERBOSE(BSL_LS_SOC_TDM, 2866 (BSL_META("TDM: the ovs_tdm_idx is %0d\n"), *ovs_tdm_idx)); 2867 LOG_VERBOSE(BSL_LS_SOC_TDM, 2868 (BSL_META("TDM: the cur_idx is %0d\n"), *cur_idx)); 2869 ovs_tdm_tbl[*ovs_tdm_idx] = wc_array[*cur_idx][subp]; 2870 LOG_VERBOSE(BSL_LS_SOC_TDM, 2871 (BSL_META("TDM: Pipe : %0d the ovs tdm tbl element #0%0d, " 2872 "content is %0d\n"), 2873 upperlimit, *ovs_tdm_idx, ovs_tdm_tbl[*ovs_tdm_idx])); 2874 (*ovs_tdm_idx)++; 2875 if (subp != 0 && port_state_map[(wc_array[*cur_idx][subp-1])-1] == 1) 2876 { 2877 pgw_tdm_tbl[*pgw_tdm_idx] = TDM_TD2_OVS_TOKEN; 2878 (*pgw_tdm_idx)++; 2879 pgw_tdm_idx_lookback++; 2880 } 2881 (*cur_idx)++; 2882 break; 2883 } 2884 2885 /* chopping block */ 2886 while ((*cur_idx < upperlimit) && ((wc_array[*cur_idx][subp] == TDM_TD2_NUM_EXT_PORTS) || (wc_array[*cur_idx][subp] == TDM_TD2_MGM_TOKEN))) 2887 { 2888 (*cur_idx)++; 2889 } 2890 if (*cur_idx >= upperlimit) 2891 { 2892 /* table post processing */ 2893 LOG_VERBOSE(BSL_LS_SOC_TDM, 2894 (BSL_META("TDM: _____DEBUG: entering post-processing 2, " 2895 "executing lookback %0d against subset limit %0d\n"), 2896 pgw_tdm_idx_lookback, pgw_tdm_idx_sub)); 2897 if (l1_ovs_cnt > 0) 2898 { 2899 int ovs_pad_iter = 0; 2900 while (ovs_pad_iter < l1_ovs_cnt && pgw_tdm_idx_lookback < pgw_tdm_idx_sub) 2901 { 2902 pgw_tdm_tbl[*pgw_tdm_idx] = TDM_TD2_OVS_TOKEN; 2903 LOG_VERBOSE(BSL_LS_SOC_TDM, 2904 (BSL_META("TDM: Pipe : %0d the pgw tdm tbl element #0%0d, insert OVS token\n"), upperlimit, *pgw_tdm_idx)); 2905 (*pgw_tdm_idx)++; 2906 pgw_tdm_idx_lookback++; 2907 ovs_pad_iter++; 2908 } 2909 } 2910 if (pad_40g_in_480g==TDM_TD2_TRUE) { 2911 /* at 480G, TDM must be padded to max length or underrun */ 2912 while ( (bw<=480) && (pgw_tdm_idx_sub > pgw_tdm_idx_lookback) ) 2913 { 2914 pgw_tdm_tbl[*pgw_tdm_idx] = TDM_TD2_OVS_TOKEN; 2915 (*pgw_tdm_idx)++; 2916 pgw_tdm_idx_lookback++; 2917 if (pgw_tdm_idx_lookback >= pgw_tdm_idx_sub) break; 2918 } 2919 } 2920 2921 return 1; 2922 } 2923 sm_iter++; 2924 } 2925 } 2926 LOG_VERBOSE(BSL_LS_SOC_TDM, 2927 (BSL_META("TDM: the pgw_tdm_idx is %0d\n"), *pgw_tdm_idx)); 2928 LOG_VERBOSE(BSL_LS_SOC_TDM, 2929 (BSL_META("TDM: the cur_idx is %0d\n"), *cur_idx)); 2930 return 1; 2931 } 2932 2933 2934 /** 2935 @name: write_mmu_tdm_tbl 2936 @param: 2937 2938 MMU table collector function 2939 */ 2940 int 2941 write_mmu_tdm_tbl(int pgw0[32], int pgw1[32], int ovs0[32], int ovs1[32], int mmu[256], int bucket1[16], int bucket2[16], int bucket3[16], int bucket4[16], int x_pipe, int port_state_map[128], int tsc[TDM_TD2_NUM_WC][4], int bw, enum tdm_td2_port_speed speed[TDM_TD2_NUM_EXT_PORTS], int (*op_flags)[1]) 2942 { 2943 long int clk; 2944 int temp_10G[4], temp_1G[4], temp_20G[4]; 2945 long int s1, s2, s3, limiter; 2946 int a=0, x=0; 2947 int b, c=0, d, e, f, g, i=0, j, k=0, l, m, v, w, y, z=0, microsubbed10G=TDM_TD2_FALSE, overload10G=0, lr_idx_limit, proxcheck; 2948 int pgw_buffer[64], u1g=0, y0=0, y1=0, y2=0, y3=0, y4=0, y5=0, yy=0, ye=0; 2949 int ovs_buffer[64], z6=0, z1=0, z2=0, z3=0, z4=0, z5=0, z11=0, z22=0, z33=0, z44=0; 2950 int pgw_120=TDM_TD2_FALSE, pgw_100=TDM_TD2_FALSE, pgw_10=TDM_TD2_FALSE, pgw_1=TDM_TD2_FALSE, pgw_20=TDM_TD2_FALSE, pgw_40=TDM_TD2_FALSE; 2951 int pgw01[64], pgw10[64], pgw20[32], pgw40[16], pgw100[8], pgw120[8]; 2952 #if 0 2953 int err_buffer[64], err_speeds[64], err_swap[64]; 2954 #endif 2955 int ovs_1=TDM_TD2_FALSE, ovs_10=TDM_TD2_FALSE, ovs_20=TDM_TD2_FALSE, ovs_40=TDM_TD2_FALSE, ovs_100=TDM_TD2_FALSE, ovs_120=TDM_TD2_FALSE; 2956 int num_ovs_1 = 0, num_ovs_10 = 0, num_ovs_20 = 0, num_ovs_40 = 0, num_ovs_100 = 0, num_ovs_120 = 0; 2957 int ovs01[64], ovs10[64], ovs20[64], ovs40[64], ovs100[64], ovs120[64]; 2958 int y4_loopback_style_46=TDM_TD2_FALSE, y4_loopback_style_54=TDM_TD2_FALSE; 2959 int jjj; 2960 int accessories; 2961 int src_port, dst_port, can_swap, s_index, swapped = 0; 2962 int lp1, lp2, right_index, left_index, right_index2, left_index2; 2963 int param_token_rsv = TDM_TD2_NUM_EXT_PORTS + 99; 2964 int ports20g[32], ports20g_num = 0, dual_20g = 0, port_found = 0, 2965 tsc_port1, tsc_port2, port_tsc, space_20g, space_40g, space_exp, 2966 slot_num = 0, slot_cnt = 0, slot_idx = 0, slot_token, 2967 idx_s = 0, idx1, idx2, idx_up, idx_dn, 2968 chk_pass = 0, test_pass = 0; 2969 switch (bw) { 2970 case 960: clk=76000; accessories=8; break; 2971 case 720: clk=59878; accessories=10; break; 2972 case 640: clk=51786; accessories=8; break; 2973 case 480: clk=39000; accessories=10; break; 2974 default: clk=76000; accessories=8; break; 2975 } 2976 for (j = 0; j < 64; j++) { 2977 pgw10[j] = 144; 2978 pgw01[j] = 144; 2979 pgw_buffer[j] = TDM_TD2_NUM_EXT_PORTS; 2980 ovs_buffer[j] = TDM_TD2_NUM_EXT_PORTS; 2981 ovs01[j] = TDM_TD2_NUM_EXT_PORTS; 2982 ovs10[j] = TDM_TD2_NUM_EXT_PORTS; 2983 ovs20[j] = TDM_TD2_NUM_EXT_PORTS; 2984 ovs40[j] = TDM_TD2_NUM_EXT_PORTS; 2985 ovs100[j]= TDM_TD2_NUM_EXT_PORTS; 2986 ovs120[j]= TDM_TD2_NUM_EXT_PORTS; 2987 #if 0 2988 err_buffer[j] = 0; 2989 err_speeds[j] = 0; 2990 err_swap[j] = 0; 2991 #endif 2992 } 2993 while ((i<32) && ((pgw0[i] != TDM_TD2_NUM_EXT_PORTS) || (pgw1[i] != TDM_TD2_NUM_EXT_PORTS))) { 2994 pgw_buffer[k] = pgw0[i]; 2995 pgw_buffer[k+1] = pgw1[i]; 2996 k+=2; 2997 i++; 2998 } 2999 for (j = 0; j < 32; j++) { 3000 ovs_buffer[j] = ovs0[j]; 3001 ovs_buffer[j+32] = ovs1[j]; 3002 } 3003 for (j = 0; j < 64; j++) { 3004 if (pgw_buffer[j] != TDM_TD2_NUM_EXT_PORTS && pgw_buffer[j] != TDM_TD2_OVS_TOKEN && port_state_map[pgw_buffer[j]-1] == 1) { 3005 if (port_state_map[pgw_buffer[j]] != 3 && (speed[pgw_buffer[j]]==TDM_TD2_SPEED_10G || speed[pgw_buffer[j]]==TDM_TD2_SPEED_10G_DUAL || speed[pgw_buffer[j]]==TDM_TD2_SPEED_10G_XAUI)) { 3006 pgw_10 = TDM_TD2_TRUE; 3007 for (y=0; y<64; y++) if (pgw10[y]==pgw_buffer[j]) microsubbed10G=TDM_TD2_TRUE; 3008 if (microsubbed10G==TDM_TD2_FALSE) {y1++; pgw10[y1] = pgw_buffer[j];} 3009 microsubbed10G=TDM_TD2_FALSE; 3010 } 3011 else if (port_state_map[pgw_buffer[j]] != 3 && speed[pgw_buffer[j]]<TDM_TD2_SPEED_10G) { 3012 pgw_1 = TDM_TD2_TRUE; 3013 y0++; 3014 u1g++; 3015 pgw01[y0] = pgw_buffer[j]; 3016 } 3017 else if (port_state_map[pgw_buffer[j]] == 3 && port_state_map[pgw_buffer[j]+1] != 3) { 3018 pgw_20 = TDM_TD2_TRUE; 3019 y2++; 3020 pgw20[y2] = pgw_buffer[j]; 3021 pgw20[0] = TDM_TD2_NUM_EXT_PORTS; 3022 for (m=0; m<y2; m++) if (pgw20[m] == pgw_buffer[j]) y2--; 3023 } 3024 else if (port_state_map[pgw_buffer[j]] == 3 && 3025 port_state_map[pgw_buffer[j]+1] == 3 && 3026 port_state_map[pgw_buffer[j]+3] != 3) 3027 { 3028 pgw_40 = TDM_TD2_TRUE; 3029 y3++; 3030 pgw40[y3] = pgw_buffer[j]; 3031 pgw40[0] = TDM_TD2_NUM_EXT_PORTS; 3032 for (m=0; m<y3; m++) if (pgw40[m] == pgw_buffer[j]) y3--; 3033 } 3034 else if ((port_state_map[pgw_buffer[j]] == 3 && 3035 port_state_map[pgw_buffer[j]+1] == 3 && 3036 port_state_map[pgw_buffer[j]+3] == 3 && 3037 port_state_map[pgw_buffer[j]+8] == 3 && 3038 port_state_map[pgw_buffer[j]+10] != 3) || 3039 (speed[pgw_buffer[j]]==TDM_TD2_SPEED_100G || 3040 speed[pgw_buffer[j]]==TDM_TD2_SPEED_106G)) 3041 { 3042 pgw_100 = TDM_TD2_TRUE; 3043 y4++; 3044 pgw100[y4] = pgw_buffer[j]; 3045 pgw100[0] = TDM_TD2_NUM_EXT_PORTS; 3046 for (m=0; m<y4; m++) if (pgw100[m] == pgw_buffer[j]) y4--; 3047 } 3048 else if ((port_state_map[pgw_buffer[j]] == 3 && 3049 port_state_map[pgw_buffer[j]+1] == 3 && 3050 port_state_map[pgw_buffer[j]+3] == 3 && 3051 port_state_map[pgw_buffer[j]+8] == 3 && 3052 port_state_map[pgw_buffer[j]+10] == 3) && 3053 (speed[pgw_buffer[j]]==TDM_TD2_SPEED_120G || 3054 speed[pgw_buffer[j]]==TDM_TD2_SPEED_127G)) 3055 { 3056 pgw_120 = TDM_TD2_TRUE; 3057 y5++; 3058 pgw120[y5] = pgw_buffer[j]; 3059 pgw120[0] = TDM_TD2_NUM_EXT_PORTS; 3060 for (m=0; m<y5; m++) if (pgw120[m] == pgw_buffer[j]) y5--; 3061 } 3062 } 3063 else if (pgw_buffer[j] != TDM_TD2_NUM_EXT_PORTS && pgw_buffer[j] != TDM_TD2_OVS_TOKEN) 3064 LOG_ERROR(BSL_LS_SOC_TDM, 3065 (BSL_META("TDM: _____ERROR: FAILURE TO LOCK PGW PORT %0d to state mapping %0d\n"), 3066 pgw_buffer[j], port_state_map[pgw_buffer[j]-1])); 3067 if (ovs_buffer[j] != TDM_TD2_NUM_EXT_PORTS && port_state_map[ovs_buffer[j]-1] == 2) 3068 { 3069 if (port_state_map[ovs_buffer[j]] != 3 && (speed[ovs_buffer[j]]==TDM_TD2_SPEED_10G || speed[ovs_buffer[j]]==TDM_TD2_SPEED_10G_DUAL || speed[ovs_buffer[j]]==TDM_TD2_SPEED_10G_XAUI) ) 3070 { 3071 ovs_10 = TDM_TD2_TRUE; 3072 num_ovs_10++; 3073 z1++; 3074 ovs10[z1] = ovs_buffer[j]; 3075 } 3076 else if (port_state_map[ovs_buffer[j]] != 3 && speed[ovs_buffer[j]]<TDM_TD2_SPEED_10G) 3077 { 3078 ovs_1 = TDM_TD2_TRUE; 3079 num_ovs_1++; 3080 z6++; 3081 ovs01[z6] = ovs_buffer[j]; 3082 } 3083 else if (port_state_map[ovs_buffer[j]] == 3 && 3084 port_state_map[ovs_buffer[j]+1] != 3) 3085 { 3086 ovs_20 = TDM_TD2_TRUE; 3087 num_ovs_20++; 3088 z2++; 3089 ovs20[z2] = ovs_buffer[j]; 3090 ovs20[0] = TDM_TD2_NUM_EXT_PORTS; 3091 for (m=0; m<z2; m++) if (ovs20[m] == ovs_buffer[j]) z2--; 3092 } 3093 else if (port_state_map[ovs_buffer[j]] == 3 && 3094 port_state_map[ovs_buffer[j]+1] == 3 && 3095 port_state_map[ovs_buffer[j]+3] != 3) 3096 { 3097 ovs_40 = TDM_TD2_TRUE; 3098 num_ovs_40++; 3099 z3++; 3100 ovs40[z3] = ovs_buffer[j]; 3101 ovs40[0] = TDM_TD2_NUM_EXT_PORTS; 3102 for (m=0; m<z3; m++) if (ovs40[m] == ovs_buffer[j]) z3--; 3103 } 3104 else if (port_state_map[ovs_buffer[j]] == 3 && 3105 port_state_map[ovs_buffer[j]+1] == 3 && 3106 port_state_map[ovs_buffer[j]+3] == 3 && 3107 port_state_map[ovs_buffer[j]+8] == 3 && 3108 port_state_map[ovs_buffer[j]+10] != 3) 3109 { 3110 ovs_100 = TDM_TD2_TRUE; 3111 num_ovs_100++; 3112 z4++; 3113 ovs100[z4] = ovs_buffer[j]; 3114 ovs100[0] = TDM_TD2_NUM_EXT_PORTS; 3115 for (m=0; m<z4; m++) if (ovs100[m] == ovs_buffer[j]) z4--; 3116 } 3117 else if (port_state_map[ovs_buffer[j]] == 3 && 3118 port_state_map[ovs_buffer[j]+1] == 3 && 3119 port_state_map[ovs_buffer[j]+3] == 3 && 3120 port_state_map[ovs_buffer[j]+8] == 3 && 3121 port_state_map[ovs_buffer[j]+10] == 3) 3122 { 3123 ovs_120 = TDM_TD2_TRUE; 3124 num_ovs_120++; 3125 z5++; 3126 ovs120[z5] = ovs_buffer[j]; 3127 ovs120[0] = TDM_TD2_NUM_EXT_PORTS; 3128 for (m=0; m<z5; m++) if (ovs120[m] == ovs_buffer[j]) z5--; 3129 } 3130 } 3131 else if (ovs_buffer[j] != TDM_TD2_NUM_EXT_PORTS) 3132 LOG_ERROR(BSL_LS_SOC_TDM, 3133 (BSL_META("TDM: _____ERROR: FAILURE TO LOCK OVS PORT #%0d to state mapping %0d\n"), 3134 ovs_buffer[j], port_state_map[ovs_buffer[j]-1])); 3135 } 3136 LOG_VERBOSE(BSL_LS_SOC_TDM, 3137 (BSL_META("TDM: _____VERBOSE: (1G - %0d) (10G - %0d) (20G - %0d) " 3138 "(40G - %0d) (100G - %0d) (120G - %0d) LR Variety - %0d\n"), 3139 y0, y1, y2, y3, y4, y5, (pgw_1+pgw_10+pgw_20+pgw_40+pgw_100+pgw_120))); 3140 if (pgw_1==TDM_TD2_TRUE) { 3141 if (u1g>0) {u1g = (u1g/4>0)? (u1g/4): (1);} 3142 LOG_VERBOSE(BSL_LS_SOC_TDM, 3143 (BSL_META("TDM: _____VERBOSE: microsubbed 1G detected, number of TSCs is %0d\n"), u1g)); 3144 while (u1g>0) 3145 { 3146 for (j=63; j>1; j--) pgw10[j]=pgw10[j-1]; 3147 y1++; 3148 pgw10[1] = TDM_TD2_U1G_TOKEN; 3149 u1g--; 3150 } 3151 } 3152 3153 switch (bw) 3154 { 3155 case 960: lr_idx_limit=48; break; 3156 case 720: lr_idx_limit=37; break; 3157 case 640: lr_idx_limit=33; break; 3158 case 480: lr_idx_limit=25; break; 3159 default: lr_idx_limit=48; break; 3160 } 3161 3162 if (y4 > 0) { 3163 LOG_VERBOSE(BSL_LS_SOC_TDM, 3164 (BSL_META("TDM: __________VERBOSE: 100G scheduling pass\n"))); 3165 if (y4==2) 3166 { 3167 y4_loopback_style_46=TDM_TD2_TRUE; 3168 while (y4 > 0) 3169 { 3170 for (j=yy; j<yy+50; j+=10) 3171 { 3172 if (mmu[j] == TDM_TD2_NUM_EXT_PORTS) 3173 mmu[j] = pgw100[y4]; 3174 else 3175 LOG_ERROR(BSL_LS_SOC_TDM, 3176 (BSL_META("TDM: _____ERROR: FAILURE TO WRITE 100G PORT #%0d " 3177 "at index %0d already has %0d\n"), pgw100[y4], j, mmu[j])); 3178 } 3179 for (j=(yy+6); j<yy+56; j+=10) 3180 { 3181 if (mmu[j] == TDM_TD2_NUM_EXT_PORTS) 3182 mmu[j] = pgw100[y4]; 3183 else 3184 LOG_ERROR(BSL_LS_SOC_TDM, 3185 (BSL_META("TDM: _____ERROR: FAILURE TO WRITE 100G PORT #%0d " 3186 "at index %0d already has %0d\n"), pgw100[y4], j, mmu[j])); 3187 } 3188 yy+=2; 3189 y4--; 3190 } 3191 } 3192 else 3193 { 3194 y4_loopback_style_54=TDM_TD2_TRUE; 3195 while (y4 > 0) { 3196 for (j=yy; j<yy+45; j+=5) 3197 { 3198 if (j==yy+25) j=(yy+24); 3199 if (mmu[j] == TDM_TD2_NUM_EXT_PORTS) 3200 mmu[j] = pgw100[y4]; 3201 else 3202 LOG_ERROR(BSL_LS_SOC_TDM, 3203 (BSL_META("TDM: _____ERROR: FAILURE TO WRITE 100G PORT #%0d " 3204 "at index %0d already has %0d\n"), pgw100[y4], j, mmu[j])); 3205 } 3206 while (mmu[yy]!=TDM_TD2_NUM_EXT_PORTS||mmu[yy+5]!=TDM_TD2_NUM_EXT_PORTS||mmu[yy+10]!=TDM_TD2_NUM_EXT_PORTS||mmu[yy+15]!=TDM_TD2_NUM_EXT_PORTS||mmu[yy+20]!=TDM_TD2_NUM_EXT_PORTS||mmu[yy+24]!=TDM_TD2_NUM_EXT_PORTS||mmu[yy+29]!=TDM_TD2_NUM_EXT_PORTS||mmu[yy+34]!=TDM_TD2_NUM_EXT_PORTS||mmu[yy+39]!=TDM_TD2_NUM_EXT_PORTS||mmu[yy+44]!=TDM_TD2_NUM_EXT_PORTS) yy++; 3207 y4--; 3208 } 3209 } 3210 } 3211 if (y5 > 0) { 3212 LOG_VERBOSE(BSL_LS_SOC_TDM, 3213 (BSL_META("TDM: __________VERBOSE: 120G scheduling pass\n"))); 3214 if (y5 == 2) { 3215 for (j=yy; j<yy+48; j+=2) if (mmu[j] != TDM_TD2_NUM_EXT_PORTS) {yy++; continue;} 3216 while (y5 > 0) 3217 { 3218 for (j=yy; j<yy+48; j+=4) 3219 { 3220 if (mmu[j] == TDM_TD2_NUM_EXT_PORTS) 3221 mmu[j] = pgw120[y5]; 3222 else 3223 LOG_ERROR(BSL_LS_SOC_TDM, 3224 (BSL_META("TDM: _____ERROR: FAILURE TO WRITE 120G #%0d PORT " 3225 "at index %0d already has %0d\n"), pgw120[y5], j, mmu[j])); 3226 } 3227 yy+=2; y5--; 3228 } 3229 } 3230 else 3231 { 3232 for (v=0; v<yy; v++) 3233 { 3234 x=0; 3235 for (w=v; w<v+48; w+=4) if (mmu[w] == TDM_TD2_NUM_EXT_PORTS) x++; 3236 if (x==12) {yy=v; break;} 3237 } 3238 while (y5 > 0) 3239 { 3240 for (j=yy; j<yy+48; j+=4) 3241 { 3242 if (mmu[j] == TDM_TD2_NUM_EXT_PORTS) 3243 mmu[j] = pgw120[y5]; 3244 else 3245 LOG_ERROR(BSL_LS_SOC_TDM, 3246 (BSL_META("TDM: _____ERROR: FAILURE TO WRITE 120G #%0d PORT " 3247 "at index %0d already has %0d\n"), pgw120[y5], j, mmu[j])); 3248 } 3249 while (mmu[yy]!=TDM_TD2_NUM_EXT_PORTS||mmu[yy+4]!=TDM_TD2_NUM_EXT_PORTS||mmu[yy+8]!=TDM_TD2_NUM_EXT_PORTS||mmu[yy+12]!=TDM_TD2_NUM_EXT_PORTS||mmu[yy+16]!=TDM_TD2_NUM_EXT_PORTS||mmu[yy+20]!=TDM_TD2_NUM_EXT_PORTS||mmu[yy+24]!=TDM_TD2_NUM_EXT_PORTS||mmu[yy+28]!=TDM_TD2_NUM_EXT_PORTS||mmu[yy+32]!=TDM_TD2_NUM_EXT_PORTS||mmu[yy+36]!=TDM_TD2_NUM_EXT_PORTS||mmu[yy+40]!=TDM_TD2_NUM_EXT_PORTS||mmu[yy+44]!=TDM_TD2_NUM_EXT_PORTS) yy++; 3250 y5--; 3251 } 3252 } 3253 } 3254 s3=(((12*((clk/76))))/1000); 3255 if (y3 > 0) { 3256 LOG_VERBOSE(BSL_LS_SOC_TDM, 3257 (BSL_META("TDM: __________VERBOSE: 40G scheduling pass\n"))); 3258 LOG_VERBOSE(BSL_LS_SOC_TDM, 3259 (BSL_META("TDM: _____VERBOSE: LLS MMU spacing for 40G: %ld\n"), s3)); 3260 for (v=0; v<lr_idx_limit; v++) {x=0; for (w=v; w<v+(4*s3); w+=s3) if (mmu[w] == TDM_TD2_NUM_EXT_PORTS) x++; if (x==4) {yy=v; break;}} 3261 while (y3 > 0) 3262 { 3263 if ((yy+(s3*3))<lr_idx_limit) 3264 for (j=yy; j<yy+(4*s3); j+=s3) mmu[j] = pgw40[y3]; 3265 else 3266 { 3267 LOG_WARN(BSL_LS_SOC_TDM, 3268 (BSL_META("TDM: _____WARNING: 40G PORT #%0d at index %0d, " 3269 "failed to schedule, push into error buffer\n"), pgw40[y3], j)); 3270 ye++; 3271 #if 0 3272 err_buffer[ye]=pgw40[y3]; 3273 err_speeds[ye]=40; 3274 #endif 3275 } 3276 while (mmu[yy]!=TDM_TD2_NUM_EXT_PORTS||mmu[yy+s3]!=TDM_TD2_NUM_EXT_PORTS||mmu[yy+(2*s3)]!=TDM_TD2_NUM_EXT_PORTS||mmu[yy+(3*s3)]!=TDM_TD2_NUM_EXT_PORTS) yy++; 3277 y3--; 3278 } 3279 } 3280 s2=(((24*((clk/76))))/1000); 3281 if (y2 > 0) { 3282 LOG_VERBOSE(BSL_LS_SOC_TDM, 3283 (BSL_META("TDM: __________VERBOSE: 20G scheduling pass\n"))); 3284 LOG_VERBOSE(BSL_LS_SOC_TDM, 3285 (BSL_META("TDM: _____VERBOSE: LLS MMU spacing for 20G: %ld\n"), s2)); 3286 /* patch: MF */ 3287 { 3288 for (i=0; i<32; i++) { 3289 ports20g[i] = TDM_TD2_NUM_EXT_PORTS; 3290 } 3291 /* store 20g ports */ 3292 for (i=0; i<=y2 && i<32; i++) { 3293 port_found = 0; 3294 for (v=0; v<ports20g_num; v++) { 3295 if (ports20g[v]==pgw20[i]) { 3296 port_found = 1; 3297 break; 3298 } 3299 } 3300 if (port_found==0 && pgw20[i]!=TDM_TD2_NUM_EXT_PORTS) { 3301 a = (pgw20[i]-1)/4; 3302 for (j=i+1; j<=y2 && j<32; j++) { 3303 b = (pgw20[j]-1)/4; 3304 if (a==b && pgw20[i]!=pgw20[j]) { 3305 ports20g[ports20g_num++] = pgw20[i]; 3306 ports20g[ports20g_num++] = pgw20[j]; 3307 break; 3308 } 3309 } 3310 } 3311 } 3312 for (i=0; i<=y2 && i<32; i++) { 3313 port_found = 0; 3314 for (v=0; v<ports20g_num; v++) { 3315 if (ports20g[v]==pgw20[i]) { 3316 port_found = 1; 3317 break; 3318 } 3319 } 3320 if (port_found==0 && pgw20[i]!=TDM_TD2_NUM_EXT_PORTS) { 3321 ports20g[ports20g_num++] = pgw20[i]; 3322 } 3323 } 3324 for (i=0; i<ports20g_num; i++) { 3325 LOG_VERBOSE(BSL_LS_SOC_TDM, 3326 (BSL_META("TDM: _____VERBOSE: ports_20g[%2d] = %0d\n"), 3327 i, ports20g[i])); 3328 } 3329 } 3330 for (v=0; v<yy; v++) { 3331 x=0; 3332 for (w=v; w<v+(2*s2); w+=s2) { 3333 if (mmu[w] == TDM_TD2_NUM_EXT_PORTS) { 3334 x++; 3335 } 3336 if (x==2) { 3337 yy=v; 3338 break; 3339 } 3340 } 3341 } 3342 z=0; 3343 while (y2 > 0) { 3344 proxcheck=TDM_TD2_FAIL; 3345 e = 0; 3346 temp_20G[e] = pgw20[y2]; 3347 y2--; 3348 for (a=0; a<TDM_TD2_NUM_WC; a++) { 3349 for (b=0; b<4; b++) { 3350 if (tsc[a][b] == pgw20[y2+1]) { 3351 c=a; 3352 } 3353 } 3354 } 3355 for (b=0; b<4; b++) { 3356 if (tsc[c][b]!=temp_20G[0] && tsc[c][b]!=TDM_TD2_NUM_EXT_PORTS) { 3357 for (a=1; a<(y2+1); a++) { 3358 if (pgw20[a]==tsc[c][b]) { 3359 d=a; 3360 e++; 3361 temp_20G[e] = tsc[c][b]; 3362 for (f=d; f<y2; f++) { 3363 pgw20[f] = pgw20[f+1]; 3364 } 3365 y2--; 3366 } 3367 } 3368 } 3369 } 3370 b=e+1; 3371 limiter=65535; 3372 while (b>0) { 3373 for (v=0; v<lr_idx_limit-s2; v++) { 3374 x=0; 3375 for (w=v; w<v+(2*s2); w+=s2) { 3376 if (mmu[w] == TDM_TD2_NUM_EXT_PORTS) { 3377 x++; 3378 } 3379 } 3380 if (x==2) { 3381 yy=v; 3382 proxcheck=TDM_TD2_PASS; 3383 for (a=1; a<6; a++) { 3384 for (jjj=0; jjj<4; jjj++) { 3385 if (yy<lr_idx_limit-a){ 3386 if (mmu[yy+a]!=TDM_TD2_NUM_EXT_PORTS && mmu[yy+a]==tsc[c][jjj]) { 3387 proxcheck=TDM_TD2_FAIL; 3388 } 3389 } 3390 else { 3391 if (mmu[(-1)+(a-(lr_idx_limit-yy-1))]!=TDM_TD2_NUM_EXT_PORTS && mmu[(-1)+(a-(lr_idx_limit-yy-1))]==tsc[c][jjj]) { 3392 proxcheck=TDM_TD2_FAIL; 3393 } 3394 } 3395 if (yy>=a) { 3396 if (mmu[yy-a]!=TDM_TD2_NUM_EXT_PORTS && mmu[yy-a]==tsc[c][jjj]) { 3397 proxcheck=TDM_TD2_FAIL; 3398 } 3399 } 3400 if ((yy+s2)<lr_idx_limit-a){ 3401 if (mmu[(yy+s2)+a]!=TDM_TD2_NUM_EXT_PORTS && mmu[(yy+s2)+a]==tsc[c][jjj]) { 3402 proxcheck=TDM_TD2_FAIL; 3403 } 3404 } 3405 else { 3406 if (mmu[(-1)+(a-(lr_idx_limit-(yy+s2)-1))]!=TDM_TD2_NUM_EXT_PORTS && mmu[(-1)+(a-(lr_idx_limit-(yy+s2)-1))]==tsc[c][jjj]) { 3407 proxcheck=TDM_TD2_FAIL; 3408 } 3409 } 3410 if ((yy+s2)>=a) { 3411 if (mmu[(yy+s2)-a]!=TDM_TD2_NUM_EXT_PORTS && mmu[(yy+s2)-a]==tsc[c][jjj]) { 3412 proxcheck=TDM_TD2_FAIL; 3413 } 3414 } 3415 } 3416 } 3417 if (proxcheck==TDM_TD2_FAIL) { 3418 continue; 3419 } 3420 else { 3421 break; 3422 } 3423 } 3424 } 3425 if (proxcheck==TDM_TD2_PASS) { 3426 for (j=yy; j<yy+(2*s2); j+=s2) { 3427 mmu[j] = temp_20G[b-1]; 3428 } 3429 b--; 3430 } 3431 limiter--; 3432 if (limiter==0) { 3433 break; 3434 } 3435 } 3436 /* patch: QH */ 3437 if (b>0) { 3438 if (b == 1) { 3439 s_index = -1; 3440 src_port = temp_20G[b-1]; 3441 for (lp1 = 0; lp1 < lr_idx_limit-s2; lp1++) { 3442 if (mmu[lp1] == TDM_TD2_NUM_EXT_PORTS && 3443 mmu[lp1+s2] == TDM_TD2_NUM_EXT_PORTS) { 3444 s_index = lp1; 3445 break; 3446 } 3447 } 3448 3449 if (s_index >0) { 3450 for (lp1 = s_index-1; lp1 > 0; lp1--) { 3451 can_swap = 1; 3452 dst_port = mmu[lp1]; 3453 if (dst_port == TDM_TD2_NUM_EXT_PORTS) continue; 3454 if (speed[dst_port] != TDM_TD2_SPEED_20G && 3455 speed[dst_port] != TDM_TD2_SPEED_21G && 3456 speed[dst_port] != TDM_TD2_SPEED_21G_DUAL) continue; 3457 if (((dst_port-1)/4 == (src_port-1)/4) && 3458 ((s_index-lp1) < 6)) continue; 3459 for (lp2 = 1; lp2 < 6; lp2++) { 3460 right_index = (s_index + lp2)%lr_idx_limit; 3461 left_index = (s_index - lp2 + lr_idx_limit)%lr_idx_limit; 3462 right_index2 = (s_index + s2 + lp2)%lr_idx_limit; 3463 left_index2 = (s_index + s2 - lp2 + lr_idx_limit)%lr_idx_limit; 3464 if ((((mmu[right_index]-1)/4 == (dst_port-1)/4) || 3465 ((mmu[left_index]-1)/4 == (dst_port-1)/4)) || 3466 (((mmu[right_index2]-1)/4 == (dst_port-1)/4) || 3467 ((mmu[left_index2]-1)/4 == (dst_port-1)/4))) { 3468 can_swap = 0; 3469 break; 3470 } 3471 right_index = (lp1 + lp2)%lr_idx_limit; 3472 left_index = (lp1 - lp2 + lr_idx_limit)%lr_idx_limit; 3473 right_index2 = (lp1 + s2 + lp2)%lr_idx_limit; 3474 left_index2 = (lp1 + s2 - lp2 + lr_idx_limit)%lr_idx_limit; 3475 if ((((mmu[right_index]-1)/4 == (src_port-1)/4) || 3476 ((mmu[left_index]-1)/4 == (src_port-1)/4 )) || 3477 (((mmu[right_index2]-1)/4 == (src_port-1)/4) || 3478 ((mmu[left_index2]-1)/4 == (src_port-1)/4))) { 3479 can_swap = 0; 3480 break; 3481 } 3482 } 3483 if (can_swap) { 3484 mmu[s_index] = dst_port; 3485 mmu[s_index+s2] = dst_port; 3486 mmu[lp1] = src_port; 3487 mmu[lp1+s2] = src_port; 3488 b--; 3489 break; 3490 } 3491 } 3492 } 3493 } 3494 } 3495 /* patch: MF */ 3496 if (b>0) { 3497 test_pass = 1; 3498 space_20g = ((24*clk/76)/1000); 3499 space_40g = ((12*clk/76)/1000); 3500 /* recycle 20g port slots from mmu calendar */ 3501 for (i=0; i<lr_idx_limit; i++) { 3502 for (v=0; v<ports20g_num; v++) { 3503 if (mmu[i]==ports20g[v]) { 3504 mmu[i] = TDM_TD2_NUM_EXT_PORTS; 3505 break; 3506 } 3507 } 3508 } 3509 /* re-allocate slots for 20g ports in mmu calendar */ 3510 for (v=0; v<ports20g_num; v++) { 3511 /* check if tsc is dual 20g */ 3512 dual_20g = 0; 3513 tsc_port1 = ports20g[v]; 3514 tsc_port2 = TDM_TD2_NUM_EXT_PORTS; 3515 if (v+1<ports20g_num) { 3516 tsc_port2 = ports20g[v+1]; 3517 if (((tsc_port1-1)/4)==((tsc_port2-1)/4)) { 3518 dual_20g = 1; 3519 } 3520 } 3521 port_tsc = (tsc_port1-1)/4; 3522 space_exp = (dual_20g==0) ? space_20g : space_40g; 3523 /* find first empty slot */ 3524 idx_s = lr_idx_limit; 3525 for (i=0; i<lr_idx_limit; i++) { 3526 if (mmu[i]==TDM_TD2_NUM_EXT_PORTS) { 3527 idx_s = i; 3528 break; 3529 } 3530 } 3531 /* reserve slots in mmu calender for port(s) */ 3532 slot_cnt = 0; 3533 for (i=idx_s; i<lr_idx_limit; i=idx_s+space_exp * slot_cnt) { 3534 i = i % lr_idx_limit; 3535 /* find slot_idx */ 3536 slot_idx = lr_idx_limit; 3537 if (mmu[i]==TDM_TD2_NUM_EXT_PORTS) { 3538 slot_idx = i; 3539 } else { 3540 idx_dn = lr_idx_limit; 3541 idx_up = lr_idx_limit; 3542 for (j=i+1; j<lr_idx_limit; j++) { 3543 if (mmu[j]==TDM_TD2_NUM_EXT_PORTS) { 3544 chk_pass = 1; 3545 for (k=1; k<6; k++) { 3546 idx1 = (j+k)%lr_idx_limit; 3547 idx2 = (j+lr_idx_limit-k)%lr_idx_limit; 3548 if ((mmu[idx1]-1)/4==port_tsc || 3549 (mmu[idx2]-1)/4==port_tsc) { 3550 chk_pass = 0; 3551 break; 3552 } 3553 } 3554 if (chk_pass==1) { 3555 idx_dn = j; 3556 break; 3557 } 3558 } 3559 } 3560 for (j=i-1; j>0; j--) { 3561 if (mmu[j]==TDM_TD2_NUM_EXT_PORTS) { 3562 chk_pass = 1; 3563 for (k=1; k<6; k++) { 3564 idx1 = (j+k)%lr_idx_limit; 3565 idx2 = (j+lr_idx_limit-k)%lr_idx_limit; 3566 if ((mmu[idx1]-1)/4==port_tsc || 3567 (mmu[idx2]-1)/4==port_tsc) { 3568 chk_pass = 0; 3569 break; 3570 } 3571 } 3572 if (chk_pass==1) { 3573 idx_up = j; 3574 break; 3575 } 3576 } 3577 } 3578 if (idx_dn!=lr_idx_limit && idx_up!=lr_idx_limit) { 3579 slot_idx = (idx_dn-i) < (i-idx_up) ? 3580 idx_dn : idx_up; 3581 } else if (idx_dn!=i) { 3582 slot_idx = idx_dn; 3583 } else if (idx_up!=i) { 3584 slot_idx = idx_up; 3585 } 3586 } 3587 /* reserve slot for port(s) */ 3588 if (slot_idx<lr_idx_limit) { 3589 mmu[slot_idx] = param_token_rsv; 3590 slot_cnt++; 3591 } else { 3592 break; 3593 } 3594 } 3595 /* allocate slots for port(s) */ 3596 slot_cnt = 0; 3597 for (i=0; i<lr_idx_limit; i++) { 3598 if (mmu[i] == param_token_rsv) { 3599 if (dual_20g==1) { 3600 slot_token = (slot_cnt % 2) ? tsc_port1 : tsc_port2; 3601 } else { 3602 slot_token = tsc_port1; 3603 } 3604 mmu[i] = slot_token; 3605 slot_cnt++; 3606 LOG_VERBOSE(BSL_LS_SOC_TDM, 3607 (BSL_META("TDM: _____VERBOSE: tsc %0d," 3608 "slot_cnt %0d, slot_idx %2d, 20G port %0d\n"), 3609 port_tsc, slot_cnt, i, mmu[i])); 3610 } 3611 } 3612 /* check */ 3613 slot_num = (dual_20g==0) ? (8/4) : (16/4); 3614 if (slot_cnt<slot_num) { 3615 test_pass = 0; 3616 LOG_ERROR(BSL_LS_SOC_TDM, 3617 (BSL_META("TDM has no solution for port %0d\n"), tsc_port1)); 3618 } 3619 /* update variables */ 3620 if (dual_20g==1) { 3621 v++; 3622 } 3623 } 3624 /* backward compatibility */ 3625 if (test_pass==1) { 3626 b = 0; 3627 } 3628 } 3629 /* check */ 3630 if (b > 0) { 3631 z++; 3632 s2++; 3633 LOG_ERROR(BSL_LS_SOC_TDM, 3634 (BSL_META("scheduling 20G has failed, y2 pointer is at %0d\n"), y2)); 3635 for (jjj=0; jjj<lr_idx_limit-s2; jjj++) { 3636 if (mmu[jjj]==TDM_TD2_NUM_EXT_PORTS) { 3637 x++; 3638 } 3639 } 3640 if (x<=1 || z>4) { 3641 LOG_ERROR(BSL_LS_SOC_TDM, 3642 (BSL_META("TDM for this port config has no solution\n"))); 3643 return 0; 3644 } 3645 } 3646 } 3647 } 3648 if (y1 > 0) { 3649 LOG_VERBOSE(BSL_LS_SOC_TDM, 3650 (BSL_META("TDM: __________VERBOSE: 10G scheduling pass\n"))); 3651 if ( pgw_120==TDM_TD2_FALSE && pgw_100==TDM_TD2_FALSE && pgw_40==TDM_TD2_FALSE && pgw_20==TDM_TD2_FALSE && pgw_1==TDM_TD2_FALSE ) 3652 { 3653 overload10G = (y1/4 > 6) ? ((y1/4)-6) : 0; 3654 LOG_VERBOSE(BSL_LS_SOC_TDM, 3655 (BSL_META("TDM: _____VERBOSE: overloaded 10G slots by +%0d\n"),overload10G)); 3656 while (y1 > 0) { 3657 proxcheck=TDM_TD2_FAIL; 3658 e = 0; 3659 temp_10G[e] = pgw10[y1]; 3660 y1--; 3661 if (temp_10G[e]!=TDM_TD2_U1G_TOKEN) { 3662 for (a=0; a<TDM_TD2_NUM_WC; a++) for (b=0; b<4; b++) if (tsc[a][b] == pgw10[y1+1]) c=a; 3663 for (b=0; b<4; b++) if (tsc[c][b]!=temp_10G[0] && tsc[c][b]!=TDM_TD2_NUM_EXT_PORTS) for (a=1; a<(y1+1); a++) if (pgw10[a]==tsc[c][b]) 3664 { 3665 d=a; 3666 e++; 3667 temp_10G[e] = tsc[c][b]; 3668 for (f=d; f<y1; f++) pgw10[f] = pgw10[f+1]; 3669 y1--; 3670 } 3671 } 3672 for (v=0; v<50; v++) if (mmu[v]==TDM_TD2_NUM_EXT_PORTS) {yy=v; break;} 3673 while (proxcheck!=TDM_TD2_PASS) { 3674 proxcheck=TDM_TD2_PASS; 3675 for (v=yy; v<(yy+(6+overload10G)*(e+1)); v+=(6+overload10G)) 3676 { 3677 if (mmu[v]!=TDM_TD2_NUM_EXT_PORTS) proxcheck=TDM_TD2_FAIL; 3678 } 3679 if (proxcheck==TDM_TD2_FAIL) {yy++; while (mmu[yy] != TDM_TD2_NUM_EXT_PORTS) yy++;} 3680 } 3681 if ((yy+(e*(6+overload10G))<lr_idx_limit)) 3682 for (a=0; a<(e+1); a++) 3683 { 3684 if (mmu[yy] == TDM_TD2_NUM_EXT_PORTS) { 3685 mmu[yy] = temp_10G[a]; yy+=(6+overload10G);} 3686 else 3687 LOG_WARN(BSL_LS_SOC_TDM, 3688 (BSL_META("TDM: _____WARNING: 10G PORT #%0d at index %0d, " 3689 "already has %0d, buffering for rescheduling\n"), 3690 temp_10G[a], yy, mmu[yy])); 3691 } 3692 else { 3693 LOG_WARN(BSL_LS_SOC_TDM, 3694 (BSL_META("TDM: _____WARNING: 10G PORT #%0d at index %0d, " 3695 "failed to schedule, push into error buffer\n"), temp_10G[a], yy)); 3696 for (a=0; a<(e+1); a++) { 3697 ye++; 3698 #if 0 3699 err_speeds[ye]=10; 3700 err_buffer[ye]=temp_10G[a]; 3701 #endif 3702 } 3703 } 3704 } 3705 } 3706 else { 3707 while (y1 > 0) { 3708 proxcheck=TDM_TD2_FAIL; 3709 e = 0; 3710 temp_10G[e] = pgw10[y1]; 3711 y1--; 3712 if (temp_10G[e]!=TDM_TD2_U1G_TOKEN) { 3713 for (a=0; a<TDM_TD2_NUM_WC; a++) for (b=0; b<4; b++) if (tsc[a][b] == pgw10[y1+1]) c=a; 3714 } 3715 b=e+1; 3716 limiter=65535; 3717 while (b>0) 3718 { 3719 for (v=0; v<lr_idx_limit; v++) if (mmu[v]==TDM_TD2_NUM_EXT_PORTS) 3720 { 3721 yy=v; 3722 proxcheck=TDM_TD2_PASS; 3723 for (a=1; a<6; a++) for (jjj=0; jjj<4; jjj++) 3724 { 3725 if (yy<lr_idx_limit-a){ 3726 if (mmu[yy+a]!=TDM_TD2_NUM_EXT_PORTS && mmu[yy+a]==tsc[c][jjj]) proxcheck=TDM_TD2_FAIL;} 3727 else{ 3728 if (mmu[(-1)+(a-(lr_idx_limit-yy-1))]!=TDM_TD2_NUM_EXT_PORTS && mmu[(-1)+(a-(lr_idx_limit-yy-1))]==tsc[c][jjj]) proxcheck=TDM_TD2_FAIL;} 3729 if (yy>=a) if (mmu[yy-a]!=TDM_TD2_NUM_EXT_PORTS && mmu[yy-a]==tsc[c][jjj]) proxcheck=TDM_TD2_FAIL; 3730 } 3731 if (proxcheck==TDM_TD2_FAIL) continue; 3732 else break; 3733 } 3734 if (proxcheck==TDM_TD2_PASS) {mmu[yy] = temp_10G[b-1]; b--;} 3735 limiter--; 3736 if (limiter==0) break; 3737 } 3738 /* patch: QH */ 3739 if (b>0) { 3740 while (b > 0) { 3741 swapped = 0; 3742 src_port = temp_10G[b-1]; 3743 if (mmu[lr_idx_limit-1] != TDM_TD2_NUM_EXT_PORTS) break; 3744 for (lp1 = 0; lp1 < lr_idx_limit; lp1++) { 3745 can_swap = 1; 3746 dst_port = mmu[lp1]; 3747 if((dst_port-1)/4 == (src_port-1)/4) continue; 3748 for (lp2 = 1; lp2 < 7; lp2++) { 3749 right_index = (lp1 + lp2)%lr_idx_limit; 3750 left_index = (lp1 -lp2 + lr_idx_limit)%lr_idx_limit; 3751 if ((mmu[right_index]-1)/4 == (src_port-1)/4 || 3752 (mmu[left_index]-1)/4 == (src_port-1)/4) { 3753 can_swap = 0; 3754 break; 3755 } 3756 } 3757 if (can_swap) { 3758 for (lp2 = lr_idx_limit-2; lp2>=lp1; lp2--) { 3759 mmu[lp2+1] = mmu[lp2]; 3760 } 3761 mmu[lp1] = src_port; 3762 b--; 3763 swapped = 1; 3764 break; 3765 } 3766 } 3767 if (!swapped) break; 3768 } 3769 if (b>0) { 3770 LOG_ERROR(BSL_LS_SOC_TDM, 3771 (BSL_META("scheduling 10G has failed, y1 pointer is at %0d\n"), y1)); 3772 for (jjj=0; jjj<lr_idx_limit; jjj++) if (mmu[jjj]==TDM_TD2_NUM_EXT_PORTS) x++; 3773 if (x<=1) { 3774 LOG_ERROR(BSL_LS_SOC_TDM, 3775 (BSL_META("TDM for this port config has no solution\n"))); 3776 return 0; 3777 } 3778 } 3779 } 3780 } 3781 } 3782 } 3783 3784 i=0; 3785 for (j=255; j>0; j--) 3786 { 3787 if (mmu[j]!=TDM_TD2_NUM_EXT_PORTS) {i=(j+1); break;} 3788 } 3789 if ((pgw_1+pgw_10+pgw_20+pgw_40+pgw_100+pgw_120) == 0) 3790 { 3791 i=0; 3792 for(j=0; j<256; j++) {mmu[j] = TDM_TD2_NUM_EXT_PORTS;} 3793 3794 } 3795 LOG_VERBOSE(BSL_LS_SOC_TDM, 3796 (BSL_META("TDM: _____VERBOSE: preprocessed MMU table terminates at index %0d\n"), i)); 3797 if (i==0) 3798 { 3799 switch (bw) 3800 { 3801 case 960: i=48; break; 3802 case 720: i=37; break; 3803 case 640: i=32; break; 3804 case 480: i=24; break; 3805 default: i=48; break; 3806 } 3807 } 3808 else if (speed[mmu[i-1]]>=TDM_TD2_SPEED_20G) { 3809 a=-1; m=1; e=1; 3810 for (j=0; j<TDM_TD2_NUM_WC; j++) 3811 { 3812 for (k=0; k<4; k++) 3813 { 3814 if (tsc[j][k]==mmu[i-1]) {a=j; break;} 3815 } 3816 if (a!=-1) break; 3817 } 3818 LOG_VERBOSE(BSL_LS_SOC_TDM, 3819 (BSL_META("TDM: _____VERBOSE: lookback warp core is %0d\n"), a)); 3820 for (j=(i-2); j>=0; j--) 3821 { 3822 if (mmu[j]!=tsc[a][0]&&mmu[j]!=tsc[a][1]&&mmu[j]!=tsc[a][2]&&mmu[j]!=tsc[a][3]) m++; 3823 else break; 3824 } 3825 LOG_VERBOSE(BSL_LS_SOC_TDM, 3826 (BSL_META("TDM: _____VERBOSE: end of MMU table, previous spacing is %0d\n"), m)); 3827 for (j=0; j<i; j++) 3828 { 3829 if (mmu[j]!=tsc[a][0]&&mmu[j]!=tsc[a][1]&&mmu[j]!=tsc[a][2]&&mmu[j]!=tsc[a][3]) e++; 3830 else break; 3831 } 3832 LOG_VERBOSE(BSL_LS_SOC_TDM, 3833 (BSL_META("TDM: _____VERBOSE: end of MMU table, loopback spacing is %0d\n"), e)); 3834 if (pgw_100==TDM_TD2_TRUE) 3835 { 3836 if (y4_loopback_style_54==TDM_TD2_TRUE) 3837 { 3838 switch (m) 3839 { 3840 case 5: i+=(4-e); break; 3841 case 4: i+=(5-e); break; 3842 } 3843 } 3844 else if (y4_loopback_style_46==TDM_TD2_TRUE) 3845 { 3846 switch (m) 3847 { 3848 case 6: i+=(4-e); break; 3849 case 4: i+=(6-e); break; 3850 } 3851 } 3852 } 3853 else if (e > m) {} 3854 else i+=(m-e); 3855 } 3856 3857 LOG_VERBOSE(BSL_LS_SOC_TDM, 3858 (BSL_META("TDM: _____VERBOSE: OVS1-%0d, OVS10-%0d, OVS20-%0d, OVS40-%0d, " 3859 "OVS100-%0d, OVS120-%0d, OVS Variety - %0d\n"), 3860 num_ovs_1, num_ovs_10, num_ovs_20, num_ovs_40, num_ovs_100, 3861 num_ovs_120, (ovs_1 + ovs_10 + ovs_20 + ovs_40 + ovs_100 + ovs_120))); 3862 LOG_VERBOSE(BSL_LS_SOC_TDM, 3863 (BSL_META("TDM: _____VERBOSE: postprocessed MMU table terminates at index %0d\n"), i)); 3864 3865 s1=(((495*((clk/76))))/10000); 3866 if (pgw_10==TDM_TD2_TRUE) 3867 { 3868 LOG_VERBOSE(BSL_LS_SOC_TDM, 3869 (BSL_META("TDM: _____VERBOSE: LLS MMU spacing for 10G: %ld\n"), s1)); 3870 if (i>s1) { 3871 LOG_WARN(BSL_LS_SOC_TDM, 3872 (BSL_META("TDM: _____WARNING: 10G ports underscheduled, " 3873 "may not satisfy line rate\n"))); 3874 } 3875 } 3876 3877 if (i>63) 3878 { 3879 LOG_ERROR(BSL_LS_SOC_TDM, 3880 (BSL_META("TDM: __________FATAL ERROR: long table causing stack overflow\n"))); 3881 return 0; 3882 } 3883 if ( (pgw_10==TDM_TD2_TRUE || pgw_1==TDM_TD2_TRUE) && (i < ((s1)-1)) ) { 3884 i = ((s1)-1); 3885 LOG_VERBOSE(BSL_LS_SOC_TDM, 3886 (BSL_META("TDM: _____VERBOSE: tdm extended to slot %0d\n"),i)); 3887 } 3888 else if ( (pgw_40==TDM_TD2_TRUE) && (bw==720) && (i < 37) ) { 3889 i=37; 3890 LOG_VERBOSE(BSL_LS_SOC_TDM, 3891 (BSL_META("TDM: _____VERBOSE: tdm extended to slot %0d\n"),i)); 3892 } 3893 for (j=0; j<i; j++) if (mmu[j]==TDM_TD2_NUM_EXT_PORTS) mmu[j] = ((ovs_1 + ovs_10 + ovs_20 + ovs_40 + ovs_100 + ovs_120)==0) ? TDM_TD2_IDL_TOKEN : TDM_TD2_OVS_TOKEN; 3894 for (j=0; j<i; j++) {mmu[j+i]=mmu[j];mmu[j+(2*i)]=mmu[j];mmu[j+(3*i)]=mmu[j];} 3895 if (y0 > 0) 3896 { 3897 while (y0 > 0) 3898 { 3899 e = 0; 3900 temp_1G[e] = pgw01[y0]; 3901 y0--; 3902 for (a=0; a<TDM_TD2_NUM_WC; a++) for (b=0; b<4; b++) if (tsc[a][b] == pgw01[y0+1]) c=a; 3903 for (b=0; b<4; b++) if (tsc[c][b]!=temp_1G[0] && tsc[c][b]!=TDM_TD2_NUM_EXT_PORTS) for (a=1; a<(y0+2); a++) if (pgw01[a]==tsc[c][b]) 3904 { 3905 d=a; 3906 e++; 3907 temp_1G[e] = tsc[c][b]; 3908 for (f=d; f<y0; f++) pgw01[f] = pgw01[f+1]; 3909 y0--; 3910 } 3911 b=TDM_TD2_FALSE; f=0; j=0; 3912 for (v=0; v<64; v++) 3913 { 3914 x=0; 3915 for (w=v; w<=v+(e*(i)); w+=(i)) if (mmu[w] == TDM_TD2_U1G_TOKEN) x++; 3916 if (x==e+1) {yy=v; break;} 3917 } 3918 j=yy; 3919 for (a=0; a<(e+1); a++) 3920 { 3921 if (mmu[j] == TDM_TD2_U1G_TOKEN) { 3922 mmu[j] = temp_1G[a]; j+=(i); 3923 } 3924 else{ 3925 LOG_ERROR( BSL_LS_SOC_TDM, 3926 (BSL_META("TDM: _____ERROR: FAILURE TO WRITE 1G PORT " 3927 "at index %0d already has %0d\n"), j, mmu[j])); 3928 } 3929 } 3930 if (y0 > 0) while (mmu[yy] != TDM_TD2_U1G_TOKEN) yy++; 3931 else while (mmu[yy] != TDM_TD2_NUM_EXT_PORTS) yy++; 3932 } 3933 } 3934 for (j=1; j<=accessories; j++) 3935 { 3936 g=TDM_scheduler_PQ((((40*i)/accessories)*j))+(j-1); 3937 for (l=255; l>g; l--) mmu[l]=mmu[l-1]; 3938 mmu[g]=TDM_TD2_ACC_TOKEN; 3939 } 3940 3941 if ((ovs_1 + ovs_10 + ovs_20 + ovs_40 + ovs_100 + ovs_120) > 4) 3942 { 3943 LOG_ERROR(BSL_LS_SOC_TDM, 3944 (BSL_META("TDM: _____FATAL ERROR: oversub variety limit exceeded\n"))); 3945 return 0; 3946 } 3947 if (((ovs_1 + ovs_10 + ovs_20 + ovs_40 + ovs_100 + ovs_120)==4 && (z6>16 || z1>16 || z2>16)) || ((ovs_1 + ovs_10 + ovs_20 + ovs_40 + ovs_100 + ovs_120)>=3 && (z6>32 || z1>32 || z2>32)) || ((ovs_1 + ovs_10 + ovs_20 + ovs_40 + ovs_100 + ovs_120)>=2 && (z6>48 || z1>48)) || ((ovs_1 + ovs_10 + ovs_20 + ovs_40 + ovs_100 + ovs_120)>=1 && (z6>64 || z1>64))) 3948 { 3949 LOG_ERROR(BSL_LS_SOC_TDM, 3950 (BSL_META("TDM: _____FATAL ERROR: oversub bucket overflow\n"))); 3951 return 0; 3952 } 3953 while (z6 > 0) { 3954 if (fill_ovs(&z6, speed, tsc, ovs01, bucket1, &z11, bucket2, &z22, bucket3, &z33, bucket4, &z44)==TDM_TD2_FAIL) { 3955 break; 3956 } 3957 } 3958 z11 = (z11>0) ? 16:0; 3959 z22 = (z22>0) ? 16:0; 3960 z33 = (z33>0) ? 16:0; 3961 z44 = (z44>0) ? 16:0; 3962 while (z1 > 0) { 3963 if (fill_ovs(&z1, speed, tsc, ovs10, bucket1, &z11, bucket2, &z22, bucket3, &z33, bucket4, &z44)==TDM_TD2_FAIL) { 3964 break; 3965 } 3966 } 3967 z11 = (z11>0) ? 16:0; 3968 z22 = (z22>0) ? 16:0; 3969 z33 = (z33>0) ? 16:0; 3970 z44 = (z44>0) ? 16:0; 3971 while (z2 > 0) { 3972 if (fill_ovs(&z2, speed, tsc, ovs20, bucket1, &z11, bucket2, &z22, bucket3, &z33, bucket4, &z44)==TDM_TD2_FAIL) { 3973 break; 3974 } 3975 } 3976 z11 = (z11>0) ? 16:0; 3977 z22 = (z22>0) ? 16:0; 3978 z33 = (z33>0) ? 16:0; 3979 z44 = (z44>0) ? 16:0; 3980 while (z3 > 0) { 3981 if (z11 < 16) { 3982 bucket1[z11] = ovs40[z3]; 3983 z11++; 3984 z3--; 3985 } 3986 else if (z22 < 16) { 3987 bucket2[z22] = ovs40[z3]; 3988 z22++; 3989 z3--; 3990 } 3991 else if (z33 < 16) { 3992 bucket3[z33] = ovs40[z3]; 3993 z33++; 3994 z3--; 3995 } 3996 else { 3997 bucket4[z44] = ovs40[z3]; 3998 z44++; 3999 z3--; 4000 } 4001 } 4002 z11 = (z11>0) ? 16:0; 4003 z22 = (z22>0) ? 16:0; 4004 z33 = (z33>0) ? 16:0; 4005 z44 = (z44>0) ? 16:0; 4006 while (z4 > 0) { 4007 if (z11 < 16) { 4008 bucket1[z11] = ovs100[z4]; 4009 z11++; 4010 z4--; 4011 } 4012 else if (z22 < 16) { 4013 bucket2[z22] = ovs100[z4]; 4014 z22++; 4015 z4--; 4016 } 4017 else if (z33 < 16) { 4018 bucket3[z33] = ovs100[z4]; 4019 z33++; 4020 z4--; 4021 } 4022 else { 4023 bucket4[z44] = ovs100[z4]; 4024 z44++; 4025 z4--; 4026 } 4027 } 4028 z11 = (z11>0) ? 16:0; 4029 z22 = (z22>0) ? 16:0; 4030 z33 = (z33>0) ? 16:0; 4031 z44 = (z44>0) ? 16:0; 4032 while (z5 > 0) { 4033 if (z11 < 16) { 4034 bucket1[z11] = ovs120[z5]; 4035 z11++; 4036 z5--; 4037 } 4038 else if (z22 < 16) { 4039 bucket2[z22] = ovs120[z5]; 4040 z22++; 4041 z5--; 4042 } 4043 else if (z33 < 16) { 4044 bucket3[z33] = ovs120[z5]; 4045 z33++; 4046 z5--; 4047 } 4048 else { 4049 bucket4[z44] = ovs120[z5]; 4050 z44++; 4051 z5--; 4052 } 4053 } 4054 4055 return 1; 4056 4057 } 4058 4059 4060 /** 4061 @name: TDM_OVS_spacer 4062 @param: int[][], int[], int[] 4063 4064 Expands OVS table into Flexport configuration 4065 */ 4066 4067 void TDM_OVS_spacer(int wc[TDM_TD2_NUM_WC][4], int ovs_tdm_tbl[32], int ovs_spacing[32]) 4068 { 4069 int i, j, v=0, w=0, k=0, a, b, c=0; 4070 int pivot[32]; for (i=0; i<32; i++) pivot[i] = -1; 4071 for (j=0; j<32; j++) if (ovs_tdm_tbl[j] == TDM_TD2_NUM_EXT_PORTS) k++; 4072 switch (k) 4073 { 4074 case 0: 4075 break; 4076 case 1: 4077 for (j=31; j>16; j--) ovs_tdm_tbl[j] = ovs_tdm_tbl[j-1]; 4078 ovs_tdm_tbl[16] = TDM_TD2_NUM_EXT_PORTS; 4079 break; 4080 case 2: 4081 for (j=30; j>16; j--) ovs_tdm_tbl[j] = ovs_tdm_tbl[j-1]; 4082 ovs_tdm_tbl[16] = TDM_TD2_NUM_EXT_PORTS; 4083 ovs_tdm_tbl[31] = TDM_TD2_NUM_EXT_PORTS; 4084 break; 4085 case 3: 4086 for (j=31; j>8; j--) ovs_tdm_tbl[j] = ovs_tdm_tbl[j-1]; 4087 for (j=31; j>16; j--) ovs_tdm_tbl[j] = ovs_tdm_tbl[j-1]; 4088 for (j=31; j>24; j--) ovs_tdm_tbl[j] = ovs_tdm_tbl[j-1]; 4089 ovs_tdm_tbl[8] = TDM_TD2_NUM_EXT_PORTS; 4090 ovs_tdm_tbl[16] = TDM_TD2_NUM_EXT_PORTS; 4091 ovs_tdm_tbl[24] = TDM_TD2_NUM_EXT_PORTS; 4092 break; 4093 default: 4094 k/=4; 4095 for (i=0; i<TDM_TD2_NUM_WC; i++) for (j=0; j<4; j++) if (wc[i][j] == ovs_tdm_tbl[0]) w = i; 4096 for (j=1; j<32; j++) if (ovs_tdm_tbl[j]==wc[w][0] || ovs_tdm_tbl[j]==wc[w][1] || ovs_tdm_tbl[j]==wc[w][2] || ovs_tdm_tbl[j]==wc[w][3]) 4097 { 4098 pivot[v] = j; 4099 v++; 4100 } 4101 for (j=0; j<3; j++) 4102 { 4103 if (pivot[j]!=-1) 4104 { 4105 for (i=31; i>(pivot[j]+k-1); i--) ovs_tdm_tbl[i] = ovs_tdm_tbl[i-k]; 4106 for (i=pivot[j]; i<(pivot[j]+k); i++) ovs_tdm_tbl[i] = TDM_TD2_NUM_EXT_PORTS; 4107 for (i=0; i<8; i++) if (pivot[i] != -1) pivot[i]+=k; 4108 } 4109 else break; 4110 } 4111 4112 break; 4113 } 4114 /* populate spacing information array (to program PGW registers) */ 4115 for (j=0; j<32; j++) 4116 { 4117 w=33; v=33; 4118 if (ovs_tdm_tbl[j]!=TDM_TD2_NUM_EXT_PORTS) for (a=0; a<TDM_TD2_NUM_WC; a++) for (b=0; b<4; b++) if (wc[a][b] == ovs_tdm_tbl[j]) c = a; 4119 if (j<31) { 4120 for (i=j+1; i<32; i++) { 4121 if (ovs_tdm_tbl[j]==ovs_tdm_tbl[i] || 4122 ovs_tdm_tbl[i]==wc[c][0] || 4123 ovs_tdm_tbl[i]==wc[c][1] || 4124 ovs_tdm_tbl[i]==wc[c][2] || 4125 ovs_tdm_tbl[i]==wc[c][3]) { 4126 w=i-j; 4127 break; 4128 } 4129 } 4130 } 4131 if (j>0) { 4132 for (k=j-1; k>=0; k--) { 4133 if (ovs_tdm_tbl[j]==ovs_tdm_tbl[k] || 4134 ovs_tdm_tbl[k]==wc[c][0] || 4135 ovs_tdm_tbl[k]==wc[c][1] || 4136 ovs_tdm_tbl[k]==wc[c][2] || 4137 ovs_tdm_tbl[k]==wc[c][3]) { 4138 v=j-k; 4139 break; 4140 } 4141 } 4142 } 4143 ovs_spacing[j] = ((w <= v) ? w : v); 4144 } 4145 for (k=0; k<32; k++) 4146 { 4147 if (ovs_spacing[k] == 33) ovs_spacing[k] = 32; 4148 if (ovs_tdm_tbl[k] == TDM_TD2_NUM_EXT_PORTS) ovs_spacing[k] = 32; 4149 } 4150 } 4151 4152 4153 /** 4154 @name: TDM_scheduler_wrap 4155 @param: 4156 4157 Wrapper for TDM populating function 4158 */ 4159 int 4160 TDM_scheduler_wrap(int wc_array[TDM_TD2_NUM_WC][4], enum tdm_td2_port_speed speed[TDM_TD2_NUM_EXT_PORTS], int pgw_tdm_tbl[32], int ovs_tdm_tbl[32], int pgw_num, int bw, int port_state_map[128], int iter2, int stop, int (*op_flags)[1]) 4161 { 4162 int first_wc = 0, cur_idx, pgw_tdm_idx = 0, ovs_tdm_idx = 0, swap_array[32], scheduler_state, op_flags_str[1], timeout, z_cnt, z_iter; 4163 int i, j, z=0; 4164 4165 for (i = 0; i < 32; i++) swap_array[i] = 0; 4166 switch(pgw_num) 4167 { 4168 case 0: first_wc = 0; break; 4169 case 1: first_wc = 8; break; 4170 case 2: first_wc = 16; break; 4171 case 3: first_wc = 24; break; 4172 } 4173 /* memcpy(&op_flags, op_flags_str, 1* sizeof(int) );*/ 4174 /* for (j=0; j<1; j++) */op_flags_str[0]=(*op_flags)[0]; 4175 for (j=0; j<4; j++) 4176 { 4177 cur_idx = first_wc; 4178 scheduler_state = TDM_scheduler(wc_array, speed, &cur_idx, &pgw_tdm_idx, &ovs_tdm_idx, j, pgw_tdm_tbl, ovs_tdm_tbl, first_wc+8, 100, bw, port_state_map, iter2, stop, swap_array, &z, j, op_flags_str); 4179 } 4180 /* for (j=0; j<1; j++) */(*op_flags)[0]=op_flags_str[0]; 4181 timeout=64; 4182 while ( (z>0) && ((--timeout)>0) ) { 4183 for (i=0; i<pgw_tdm_idx; i++) { 4184 if (pgw_tdm_tbl[i]==swap_array[z]) { 4185 z++; 4186 swap_array[z]=pgw_tdm_tbl[i]; 4187 for (j=i; j<31; j++) { 4188 pgw_tdm_tbl[j]=pgw_tdm_tbl[j+1]; 4189 } 4190 pgw_tdm_idx--; 4191 } 4192 } 4193 z_cnt=1; 4194 for (i=(z-1); i>=0; i--) { 4195 if (swap_array[i]==swap_array[z]) {z_cnt++;} 4196 } 4197 z_iter=z_cnt; 4198 for (i=pgw_tdm_idx; i>0; i-=(pgw_tdm_idx/z_cnt)) { 4199 if (pgw_tdm_tbl[i]!=swap_array[z]) { 4200 for (j=31; j>i; j--) { 4201 pgw_tdm_tbl[j]=pgw_tdm_tbl[j-1]; 4202 } 4203 pgw_tdm_tbl[i]=swap_array[z]; 4204 if ((--z_iter)==0) { 4205 break; 4206 } 4207 } 4208 } 4209 z-=z_cnt; 4210 } 4211 if (z>0) { 4212 LOG_WARN(BSL_LS_SOC_TDM, 4213 (BSL_META("TDM: _____WARNING: swap buffer not empty, index %0d, " 4214 "table at %0d, dumping all remaining entries\n"), z, pgw_tdm_idx)); 4215 } 4216 if ((*op_flags)[0]==1) { 4217 for (i=0; i<(bw/40); i++) { 4218 if (pgw_tdm_tbl[i]==TDM_TD2_NUM_EXT_PORTS) { 4219 pgw_tdm_tbl[i]=TDM_TD2_OVS_TOKEN; 4220 } 4221 } 4222 } 4223 LOG_VERBOSE(BSL_LS_SOC_TDM, 4224 (BSL_META("TDM: ----------------------------------------------------------------\n"))); 4225 4226 return scheduler_state; 4227 } 4228 4229 4230 /* ----------------------------------API------------------------------------- */ 4231 4232 #ifdef TD2_HARD_CODE_96X10G_8X40G 4233 /** 4234 @name: set_tdm_tbl 4235 @param: 4236 4237 Provides alternative hard-coded TDM instead of calling scheduler algorithm. 4238 */ 4239 int set_tdm_tbl(enum tdm_td2_port_speed speed[TDM_TD2_NUM_EXT_PORTS], int tdm_bw, 4240 int pgw_tdm_tbl_x0[32], int ovs_tdm_tbl_x0[32], int ovs_spacing_x0[32], 4241 int pgw_tdm_tbl_x1[32], int ovs_tdm_tbl_x1[32], int ovs_spacing_x1[32], 4242 int pgw_tdm_tbl_y0[32], int ovs_tdm_tbl_y0[32], int ovs_spacing_y0[32], 4243 int pgw_tdm_tbl_y1[32], int ovs_tdm_tbl_y1[32], int ovs_spacing_y1[32], 4244 int mmu_tdm_tbl_x[256], int mmu_tdm_ovs_x_1[16], int mmu_tdm_ovs_x_2[16], int mmu_tdm_ovs_x_3[16], int mmu_tdm_ovs_x_4[16], 4245 int mmu_tdm_tbl_y[256], int mmu_tdm_ovs_y_1[16], int mmu_tdm_ovs_y_2[16], int mmu_tdm_ovs_y_3[16], int mmu_tdm_ovs_y_4[16], 4246 int port_state_map[128], 4247 int iarb_tdm_tbl_x[512], int iarb_tdm_tbl_y[512]) 4248 { 4249 int wc_array[TDM_TD2_NUM_WC][4], i, j; 4250 4251 for (i=0; i< 256; i++) { 4252 mmu_tdm_tbl_x[i] = TDM_TD2_NUM_EXT_PORTS; 4253 mmu_tdm_tbl_y[i] = TDM_TD2_NUM_EXT_PORTS; 4254 } 4255 for (i=0; i<16; i++) { 4256 mmu_tdm_ovs_x_1[i] = TDM_TD2_NUM_EXT_PORTS; 4257 mmu_tdm_ovs_x_2[i] = TDM_TD2_NUM_EXT_PORTS; 4258 mmu_tdm_ovs_x_3[i] = TDM_TD2_NUM_EXT_PORTS; 4259 mmu_tdm_ovs_x_4[i] = TDM_TD2_NUM_EXT_PORTS; 4260 mmu_tdm_ovs_y_1[i] = TDM_TD2_NUM_EXT_PORTS; 4261 mmu_tdm_ovs_y_2[i] = TDM_TD2_NUM_EXT_PORTS; 4262 mmu_tdm_ovs_y_3[i] = TDM_TD2_NUM_EXT_PORTS; 4263 mmu_tdm_ovs_y_4[i] = TDM_TD2_NUM_EXT_PORTS; 4264 } 4265 for (i=0; i< 32; i++) { 4266 pgw_tdm_tbl_x0[i] = TDM_TD2_NUM_EXT_PORTS; 4267 ovs_tdm_tbl_x0[i] = TDM_TD2_NUM_EXT_PORTS; 4268 ovs_spacing_x0[i] = TDM_TD2_NUM_EXT_PORTS; 4269 pgw_tdm_tbl_x1[i] = TDM_TD2_NUM_EXT_PORTS; 4270 ovs_tdm_tbl_x1[i] = TDM_TD2_NUM_EXT_PORTS; 4271 ovs_spacing_x1[i] = TDM_TD2_NUM_EXT_PORTS; 4272 pgw_tdm_tbl_y0[i] = TDM_TD2_NUM_EXT_PORTS; 4273 ovs_tdm_tbl_y0[i] = TDM_TD2_NUM_EXT_PORTS; 4274 ovs_spacing_y0[i] = TDM_TD2_NUM_EXT_PORTS; 4275 pgw_tdm_tbl_y1[i] = TDM_TD2_NUM_EXT_PORTS; 4276 ovs_tdm_tbl_y1[i] = TDM_TD2_NUM_EXT_PORTS; 4277 ovs_spacing_y1[i] = TDM_TD2_NUM_EXT_PORTS; 4278 } 4279 4280 TSC_port_transcription(wc_array, speed, port_state_map); 4281 4282 for (i=0; i<24; i+=6) { 4283 pgw_tdm_tbl_x0[4+i]=131; pgw_tdm_tbl_x0[5+i]=131; 4284 pgw_tdm_tbl_x1[4+i]=131; pgw_tdm_tbl_x1[5+i]=131; 4285 pgw_tdm_tbl_y0[4+i]=131; pgw_tdm_tbl_y0[5+i]=131; 4286 pgw_tdm_tbl_y1[4+i]=131; pgw_tdm_tbl_y1[5+i]=131; 4287 } 4288 for (i=0; i<24; i+=6) { 4289 for (j=0; j<4; j++) { 4290 pgw_tdm_tbl_x0[i+j]=( (1+(i/6))+(j*4) ); 4291 pgw_tdm_tbl_x1[i+j]=( (33+(i/6))+(j*4) ); 4292 pgw_tdm_tbl_y0[i+j]=( (65+(i/6))+(j*4) ); 4293 pgw_tdm_tbl_y1[i+j]=( (97+(i/6))+(j*4) ); 4294 } 4295 } 4296 for (i=0; i<16; i+=4) { 4297 ovs_tdm_tbl_x0[i+2]=25; ovs_tdm_tbl_x0[i+3]=29; 4298 ovs_tdm_tbl_x1[i+2]=57; ovs_tdm_tbl_x1[i+3]=61; 4299 ovs_tdm_tbl_y0[i+2]=89; ovs_tdm_tbl_y0[i+3]=93; 4300 ovs_tdm_tbl_y1[i+2]=121; ovs_tdm_tbl_y1[i+3]=125; 4301 for (j=0; j<2; j++) { 4302 ovs_tdm_tbl_x0[i+j]= ( (17+(i/4))+(j*4) ); 4303 ovs_tdm_tbl_x1[i+j]= ( (49+(i/4))+(j*4) ); 4304 ovs_tdm_tbl_y0[i+j]= ( (81+(i/4))+(j*4) ); 4305 ovs_tdm_tbl_y1[i+j]= ( (113+(i/4))+(j*4) ); 4306 } 4307 } 4308 for (i=0; i<32; i++) { 4309 ovs_spacing_x0[i]=32; 4310 ovs_spacing_x1[i]=32; 4311 ovs_spacing_y0[i]=32; 4312 ovs_spacing_y1[i]=32; 4313 } 4314 for (i=2; i<32; i+=8) { 4315 ovs_spacing_x0[i]=8; ovs_spacing_x0[i+1]=8; 4316 ovs_spacing_x1[i]=8; ovs_spacing_x1[i+1]=8; 4317 ovs_spacing_y0[i]=8; ovs_spacing_y0[i+1]=8; 4318 ovs_spacing_y1[i]=8; ovs_spacing_y1[i+1]=8; 4319 } 4320 4321 mmu_tdm_ovs_x_1[0] = 56; 4322 mmu_tdm_ovs_x_1[1] = 52; 4323 mmu_tdm_ovs_x_1[2] = 24; 4324 mmu_tdm_ovs_x_1[3] = 20; 4325 mmu_tdm_ovs_x_1[4] = 53; 4326 mmu_tdm_ovs_x_1[5] = 49; 4327 mmu_tdm_ovs_x_1[6] = 21; 4328 mmu_tdm_ovs_x_1[7] = 17; 4329 mmu_tdm_ovs_x_1[8] = 54; 4330 mmu_tdm_ovs_x_1[9] = 50; 4331 mmu_tdm_ovs_x_1[10] = 22; 4332 mmu_tdm_ovs_x_1[11] = 18; 4333 mmu_tdm_ovs_x_1[12] = 55; 4334 mmu_tdm_ovs_x_1[13] = 51; 4335 mmu_tdm_ovs_x_1[14] = 23; 4336 mmu_tdm_ovs_x_1[15] = 19; 4337 4338 mmu_tdm_ovs_x_2[0] = 61; 4339 mmu_tdm_ovs_x_2[1] = 57; 4340 mmu_tdm_ovs_x_2[2] = 29; 4341 mmu_tdm_ovs_x_2[3] = 25; 4342 4343 mmu_tdm_ovs_y_1[0] = 120; 4344 mmu_tdm_ovs_y_1[1] = 116; 4345 mmu_tdm_ovs_y_1[2] = 88; 4346 mmu_tdm_ovs_y_1[3] = 84; 4347 mmu_tdm_ovs_y_1[4] = 117; 4348 mmu_tdm_ovs_y_1[5] = 113; 4349 mmu_tdm_ovs_y_1[6] = 85; 4350 mmu_tdm_ovs_y_1[7] = 81; 4351 mmu_tdm_ovs_y_1[8] = 118; 4352 mmu_tdm_ovs_y_1[9] = 114; 4353 mmu_tdm_ovs_y_1[10] = 86; 4354 mmu_tdm_ovs_y_1[11] = 82; 4355 mmu_tdm_ovs_y_1[12] = 119; 4356 mmu_tdm_ovs_y_1[13] = 115; 4357 mmu_tdm_ovs_y_1[14] = 87; 4358 mmu_tdm_ovs_y_1[15] = 83; 4359 4360 mmu_tdm_ovs_y_2[0] = 125; 4361 mmu_tdm_ovs_y_2[1] = 121; 4362 mmu_tdm_ovs_y_2[2] = 93; 4363 mmu_tdm_ovs_y_2[3] = 89; 4364 4365 mmu_tdm_tbl_x[0]=48; 4366 mmu_tdm_tbl_x[1]=16; 4367 mmu_tdm_tbl_x[3]=44; 4368 mmu_tdm_tbl_x[4]=12; 4369 mmu_tdm_tbl_x[6]=40; 4370 mmu_tdm_tbl_x[7]=8; 4371 mmu_tdm_tbl_x[9]=36; 4372 mmu_tdm_tbl_x[10]=4; 4373 mmu_tdm_tbl_x[12]=45; 4374 mmu_tdm_tbl_x[13]=13; 4375 mmu_tdm_tbl_x[15]=41; 4376 mmu_tdm_tbl_x[16]=9; 4377 mmu_tdm_tbl_x[18]=37; 4378 mmu_tdm_tbl_x[19]=5; 4379 mmu_tdm_tbl_x[21]=33; 4380 mmu_tdm_tbl_x[22]=1; 4381 mmu_tdm_tbl_x[24]=46; 4382 mmu_tdm_tbl_x[25]=14; 4383 mmu_tdm_tbl_x[27]=42; 4384 mmu_tdm_tbl_x[28]=10; 4385 mmu_tdm_tbl_x[30]=38; 4386 mmu_tdm_tbl_x[31]=6; 4387 mmu_tdm_tbl_x[33]=34; 4388 mmu_tdm_tbl_x[34]=2; 4389 mmu_tdm_tbl_x[36]=47; 4390 mmu_tdm_tbl_x[37]=15; 4391 mmu_tdm_tbl_x[39]=43; 4392 mmu_tdm_tbl_x[40]=11; 4393 mmu_tdm_tbl_x[42]=39; 4394 mmu_tdm_tbl_x[43]=7; 4395 mmu_tdm_tbl_x[45]=35; 4396 mmu_tdm_tbl_x[46]=3; 4397 4398 for (i=0; i<47; i++) mmu_tdm_tbl_x[i+48]=mmu_tdm_tbl_x[i]; 4399 for (i=0; i<97; i++) mmu_tdm_tbl_x[i+97]=mmu_tdm_tbl_x[i]; 4400 4401 for (i=255; i>24; i--) mmu_tdm_tbl_x[i]=mmu_tdm_tbl_x[i-1]; 4402 mmu_tdm_tbl_x[24]=0; 4403 for (i=255; i>49; i--) mmu_tdm_tbl_x[i]=mmu_tdm_tbl_x[i-1]; 4404 mmu_tdm_tbl_x[49]=132; 4405 for (i=255; i>74; i--) mmu_tdm_tbl_x[i]=mmu_tdm_tbl_x[i-1]; 4406 mmu_tdm_tbl_x[74]=0; 4407 for (i=255; i>99; i--) mmu_tdm_tbl_x[i]=mmu_tdm_tbl_x[i-1]; 4408 mmu_tdm_tbl_x[99]=132; 4409 for (i=255; i>124; i--) mmu_tdm_tbl_x[i]=mmu_tdm_tbl_x[i-1]; 4410 mmu_tdm_tbl_x[124]=132; 4411 for (i=255; i>149; i--) mmu_tdm_tbl_x[i]=mmu_tdm_tbl_x[i-1]; 4412 mmu_tdm_tbl_x[149]=0; 4413 for (i=255; i>174; i--) mmu_tdm_tbl_x[i]=mmu_tdm_tbl_x[i-1]; 4414 mmu_tdm_tbl_x[174]=132; 4415 for (i=255; i>199; i--) mmu_tdm_tbl_x[i]=mmu_tdm_tbl_x[i-1]; 4416 mmu_tdm_tbl_x[199]=132; 4417 4418 mmu_tdm_tbl_y[0]=112; 4419 mmu_tdm_tbl_y[1]=80; 4420 mmu_tdm_tbl_y[3]=108; 4421 mmu_tdm_tbl_y[4]=76; 4422 mmu_tdm_tbl_y[6]=104; 4423 mmu_tdm_tbl_y[7]=72; 4424 mmu_tdm_tbl_y[9]=100; 4425 mmu_tdm_tbl_y[10]=68; 4426 mmu_tdm_tbl_y[12]=109; 4427 mmu_tdm_tbl_y[13]=77; 4428 mmu_tdm_tbl_y[15]=105; 4429 mmu_tdm_tbl_y[16]=73; 4430 mmu_tdm_tbl_y[18]=101; 4431 mmu_tdm_tbl_y[19]=69; 4432 mmu_tdm_tbl_y[21]=97; 4433 mmu_tdm_tbl_y[22]=65; 4434 mmu_tdm_tbl_y[24]=110; 4435 mmu_tdm_tbl_y[25]=78; 4436 mmu_tdm_tbl_y[27]=106; 4437 mmu_tdm_tbl_y[28]=74; 4438 mmu_tdm_tbl_y[30]=102; 4439 mmu_tdm_tbl_y[31]=70; 4440 mmu_tdm_tbl_y[33]=98; 4441 mmu_tdm_tbl_y[34]=66; 4442 mmu_tdm_tbl_y[36]=111; 4443 mmu_tdm_tbl_y[37]=79; 4444 mmu_tdm_tbl_y[39]=107; 4445 mmu_tdm_tbl_y[40]=75; 4446 mmu_tdm_tbl_y[42]=103; 4447 mmu_tdm_tbl_y[43]=71; 4448 mmu_tdm_tbl_y[45]=99; 4449 mmu_tdm_tbl_y[46]=67; 4450 4451 for (i=0; i<47; i++) mmu_tdm_tbl_y[i+48]=mmu_tdm_tbl_y[i]; 4452 for (i=0; i<97; i++) mmu_tdm_tbl_y[i+97]=mmu_tdm_tbl_y[i]; 4453 4454 for (i=255; i>24; i--) mmu_tdm_tbl_y[i]=mmu_tdm_tbl_y[i-1]; 4455 mmu_tdm_tbl_y[24]=129; 4456 for (i=255; i>49; i--) mmu_tdm_tbl_y[i]=mmu_tdm_tbl_y[i-1]; 4457 mmu_tdm_tbl_y[49]=132; 4458 for (i=255; i>74; i--) mmu_tdm_tbl_y[i]=mmu_tdm_tbl_y[i-1]; 4459 mmu_tdm_tbl_y[74]=129; 4460 for (i=255; i>99; i--) mmu_tdm_tbl_y[i]=mmu_tdm_tbl_y[i-1]; 4461 mmu_tdm_tbl_y[99]=132; 4462 for (i=255; i>124; i--) mmu_tdm_tbl_y[i]=mmu_tdm_tbl_y[i-1]; 4463 mmu_tdm_tbl_y[124]=132; 4464 for (i=255; i>149; i--) mmu_tdm_tbl_y[i]=mmu_tdm_tbl_y[i-1]; 4465 mmu_tdm_tbl_y[149]=129; 4466 for (i=255; i>174; i--) mmu_tdm_tbl_y[i]=mmu_tdm_tbl_y[i-1]; 4467 mmu_tdm_tbl_y[174]=132; 4468 for (i=255; i>199; i--) mmu_tdm_tbl_y[i]=mmu_tdm_tbl_y[i-1]; 4469 mmu_tdm_tbl_y[199]=132; 4470 4471 for (i=0; i<200; i++) { 4472 if (mmu_tdm_tbl_x[i]==130) mmu_tdm_tbl_x[i]=131; 4473 if (mmu_tdm_tbl_y[i]==130) mmu_tdm_tbl_y[i]=131; 4474 } 4475 4476 print_tbl_summary(pgw_tdm_tbl_x0, pgw_tdm_tbl_x1, pgw_tdm_tbl_y0, pgw_tdm_tbl_y1, 4477 ovs_tdm_tbl_x0, ovs_tdm_tbl_x1, ovs_tdm_tbl_y0, ovs_tdm_tbl_y1, 4478 ovs_spacing_x0, ovs_spacing_x1, ovs_spacing_y0, ovs_spacing_y1, 4479 tdm_bw); 4480 4481 return 1; 4482 } 4483 #elif defined(TD2_HARD_CODE_92X1G_6X40G) 4484 /** 4485 @name: set_tdm_tbl 4486 @param: 4487 4488 Provides alternative hard-coded TDM instead of calling scheduler algorithm. 4489 */ 4490 int set_tdm_tbl(enum tdm_td2_port_speed speed[TDM_TD2_NUM_EXT_PORTS], int tdm_bw, 4491 int pgw_tdm_tbl_x0[32], int ovs_tdm_tbl_x0[32], int ovs_spacing_x0[32], 4492 int pgw_tdm_tbl_x1[32], int ovs_tdm_tbl_x1[32], int ovs_spacing_x1[32], 4493 int pgw_tdm_tbl_y0[32], int ovs_tdm_tbl_y0[32], int ovs_spacing_y0[32], 4494 int pgw_tdm_tbl_y1[32], int ovs_tdm_tbl_y1[32], int ovs_spacing_y1[32], 4495 int mmu_tdm_tbl_x[256], int mmu_tdm_ovs_x_1[16], int mmu_tdm_ovs_x_2[16], int mmu_tdm_ovs_x_3[16], int mmu_tdm_ovs_x_4[16], 4496 int mmu_tdm_tbl_y[256], int mmu_tdm_ovs_y_1[16], int mmu_tdm_ovs_y_2[16], int mmu_tdm_ovs_y_3[16], int mmu_tdm_ovs_y_4[16], 4497 int port_state_map[128], 4498 int iarb_tdm_tbl_x[512], int iarb_tdm_tbl_y[512]) 4499 { 4500 int wc_array[TDM_TD2_NUM_WC][4], i, j; 4501 4502 for (i=0; i< 256; i++) { 4503 mmu_tdm_tbl_x[i] = TDM_TD2_NUM_EXT_PORTS; 4504 mmu_tdm_tbl_y[i] = TDM_TD2_NUM_EXT_PORTS; 4505 } 4506 for (i=0; i<16; i++) { 4507 mmu_tdm_ovs_x_1[i] = TDM_TD2_NUM_EXT_PORTS; 4508 mmu_tdm_ovs_x_2[i] = TDM_TD2_NUM_EXT_PORTS; 4509 mmu_tdm_ovs_x_3[i] = TDM_TD2_NUM_EXT_PORTS; 4510 mmu_tdm_ovs_x_4[i] = TDM_TD2_NUM_EXT_PORTS; 4511 mmu_tdm_ovs_y_1[i] = TDM_TD2_NUM_EXT_PORTS; 4512 mmu_tdm_ovs_y_2[i] = TDM_TD2_NUM_EXT_PORTS; 4513 mmu_tdm_ovs_y_3[i] = TDM_TD2_NUM_EXT_PORTS; 4514 mmu_tdm_ovs_y_4[i] = TDM_TD2_NUM_EXT_PORTS; 4515 } 4516 for (i=0; i< 32; i++) { 4517 pgw_tdm_tbl_x0[i] = TDM_TD2_NUM_EXT_PORTS; 4518 ovs_tdm_tbl_x0[i] = TDM_TD2_NUM_EXT_PORTS; 4519 ovs_spacing_x0[i] = 32; 4520 pgw_tdm_tbl_x1[i] = TDM_TD2_NUM_EXT_PORTS; 4521 ovs_tdm_tbl_x1[i] = TDM_TD2_NUM_EXT_PORTS; 4522 ovs_spacing_x1[i] = 32; 4523 pgw_tdm_tbl_y0[i] = TDM_TD2_NUM_EXT_PORTS; 4524 ovs_tdm_tbl_y0[i] = TDM_TD2_NUM_EXT_PORTS; 4525 ovs_spacing_y0[i] = 32; 4526 pgw_tdm_tbl_y1[i] = TDM_TD2_NUM_EXT_PORTS; 4527 ovs_tdm_tbl_y1[i] = TDM_TD2_NUM_EXT_PORTS; 4528 ovs_spacing_y1[i] = 32; 4529 } 4530 4531 TSC_port_transcription(wc_array, speed, port_state_map); 4532 4533 for (i=0; i<24; i+=6) { 4534 pgw_tdm_tbl_x0[i]=1; 4535 pgw_tdm_tbl_x0[i+1]=5; 4536 pgw_tdm_tbl_y0[i]=93; 4537 pgw_tdm_tbl_y1[i]=97; 4538 pgw_tdm_tbl_y1[i+1]=121; 4539 pgw_tdm_tbl_y1[i+2]=125; 4540 } 4541 for (i=0; i<24; i++) { 4542 if (pgw_tdm_tbl_x0[i]==TDM_TD2_NUM_EXT_PORTS) pgw_tdm_tbl_x0[i]=131; 4543 if (pgw_tdm_tbl_x1[i]==TDM_TD2_NUM_EXT_PORTS) pgw_tdm_tbl_x1[i]=131; 4544 if (pgw_tdm_tbl_y0[i]==TDM_TD2_NUM_EXT_PORTS) pgw_tdm_tbl_y0[i]=131; 4545 if (pgw_tdm_tbl_y1[i]==TDM_TD2_NUM_EXT_PORTS) pgw_tdm_tbl_y1[i]=131; 4546 } 4547 for (i=0; i<32; i+=8) { 4548 for (j=0; j<6; j++) { 4549 ovs_tdm_tbl_x0[i+j]=( (9+(i/8))+(j*4) ); 4550 ovs_spacing_x0[i+j]=8; 4551 } 4552 for (j=0; j<5; j++) { 4553 ovs_tdm_tbl_x1[i+j]=( (33+(i/8))+(j*4) ); 4554 ovs_spacing_x1[i+j]=8; 4555 } 4556 for (j=0; j<7; j++) { 4557 ovs_tdm_tbl_y0[i+j]=( (65+(i/8))+(j*4) ); 4558 ovs_spacing_y0[i+j]=8; 4559 } 4560 for (j=0; j<5; j++) { 4561 ovs_tdm_tbl_y1[i+j]=( (101+(i/8))+(j*4) ); 4562 ovs_spacing_y1[i+j]=8; 4563 } 4564 } 4565 for (i=0; i<192; i+=12) mmu_tdm_tbl_x[i]=1; 4566 for (i=1; i<192; i+=12) mmu_tdm_tbl_x[i]=5; 4567 for (i=0; i<192; i+=12) mmu_tdm_tbl_y[i]=93; 4568 for (i=1; i<192; i+=12) mmu_tdm_tbl_y[i]=97; 4569 for (i=2; i<192; i+=12) mmu_tdm_tbl_y[i]=121; 4570 for (i=3; i<192; i+=12) mmu_tdm_tbl_y[i]=125; 4571 4572 for (i=255; i>24; i--) mmu_tdm_tbl_x[i]=mmu_tdm_tbl_x[i-1]; 4573 mmu_tdm_tbl_x[24]=0; 4574 for (i=255; i>49; i--) mmu_tdm_tbl_x[i]=mmu_tdm_tbl_x[i-1]; 4575 mmu_tdm_tbl_x[49]=132; 4576 for (i=255; i>74; i--) mmu_tdm_tbl_x[i]=mmu_tdm_tbl_x[i-1]; 4577 mmu_tdm_tbl_x[74]=0; 4578 for (i=255; i>99; i--) mmu_tdm_tbl_x[i]=mmu_tdm_tbl_x[i-1]; 4579 mmu_tdm_tbl_x[99]=132; 4580 for (i=255; i>124; i--) mmu_tdm_tbl_x[i]=mmu_tdm_tbl_x[i-1]; 4581 mmu_tdm_tbl_x[124]=132; 4582 for (i=255; i>149; i--) mmu_tdm_tbl_x[i]=mmu_tdm_tbl_x[i-1]; 4583 mmu_tdm_tbl_x[149]=0; 4584 for (i=255; i>174; i--) mmu_tdm_tbl_x[i]=mmu_tdm_tbl_x[i-1]; 4585 mmu_tdm_tbl_x[174]=132; 4586 for (i=255; i>199; i--) mmu_tdm_tbl_x[i]=mmu_tdm_tbl_x[i-1]; 4587 mmu_tdm_tbl_x[199]=132; 4588 4589 for (i=255; i>24; i--) mmu_tdm_tbl_y[i]=mmu_tdm_tbl_y[i-1]; 4590 mmu_tdm_tbl_y[24]=129; 4591 for (i=255; i>49; i--) mmu_tdm_tbl_y[i]=mmu_tdm_tbl_y[i-1]; 4592 mmu_tdm_tbl_y[49]=132; 4593 for (i=255; i>74; i--) mmu_tdm_tbl_y[i]=mmu_tdm_tbl_y[i-1]; 4594 mmu_tdm_tbl_y[74]=129; 4595 for (i=255; i>99; i--) mmu_tdm_tbl_y[i]=mmu_tdm_tbl_y[i-1]; 4596 mmu_tdm_tbl_y[99]=132; 4597 for (i=255; i>124; i--) mmu_tdm_tbl_y[i]=mmu_tdm_tbl_y[i-1]; 4598 mmu_tdm_tbl_y[124]=132; 4599 for (i=255; i>149; i--) mmu_tdm_tbl_y[i]=mmu_tdm_tbl_y[i-1]; 4600 mmu_tdm_tbl_y[149]=129; 4601 for (i=255; i>174; i--) mmu_tdm_tbl_y[i]=mmu_tdm_tbl_y[i-1]; 4602 mmu_tdm_tbl_y[174]=132; 4603 for (i=255; i>199; i--) mmu_tdm_tbl_y[i]=mmu_tdm_tbl_y[i-1]; 4604 mmu_tdm_tbl_y[199]=132; 4605 4606 for (i=0; i<200; i++) if (mmu_tdm_tbl_x[i]==TDM_TD2_NUM_EXT_PORTS) mmu_tdm_tbl_x[i]=131; 4607 for (i=0; i<200; i++) if (mmu_tdm_tbl_y[i]==TDM_TD2_NUM_EXT_PORTS) mmu_tdm_tbl_y[i]=131; 4608 4609 for (i=0; i<16; i+=4) { 4610 for (j=0; j<4; j++) mmu_tdm_ovs_x_1[i+j]=( (9+(i/4))+(j*4) ); 4611 for (j=0; j<4; j++) mmu_tdm_ovs_x_2[i+j]=( (25+(i/4))+(j*4) ); 4612 } 4613 for (i=0; i<12; i+=3) for (j=0; j<3; j++) mmu_tdm_ovs_x_3[i+j]=( (41+(i/3))+(j*4) ); 4614 4615 for (i=0; i<16; i+=4) { 4616 for (j=0; j<4; j++) mmu_tdm_ovs_y_1[i+j]=( (65+(i/4))+(j*4) ); 4617 for (j=0; j<4; j++) mmu_tdm_ovs_y_3[i+j]=( (105+(i/4))+(j*4) ); 4618 } 4619 for (i=0; i<16; i+=4) for (j=0; j<3; j++) mmu_tdm_ovs_y_2[i+j]=( (81+(i/4))+(j*4) ); 4620 mmu_tdm_ovs_y_2[3]=101; 4621 mmu_tdm_ovs_y_2[7]=102; 4622 mmu_tdm_ovs_y_2[11]=103; 4623 mmu_tdm_ovs_y_2[15]=104; 4624 4625 4626 print_tbl_summary(pgw_tdm_tbl_x0, pgw_tdm_tbl_x1, pgw_tdm_tbl_y0, pgw_tdm_tbl_y1, 4627 ovs_tdm_tbl_x0, ovs_tdm_tbl_x1, ovs_tdm_tbl_y0, ovs_tdm_tbl_y1, 4628 ovs_spacing_x0, ovs_spacing_x1, ovs_spacing_y0, ovs_spacing_y1, 4629 tdm_bw); 4630 4631 return 1; 4632 } 4633 #elif defined(TD2_HARD_CODE_88X1G_6X40G) 4634 /** 4635 @name: set_tdm_tbl 4636 @param: 4637 4638 Provides alternative hard-coded TDM instead of calling scheduler algorithm. 4639 */ 4640 int set_tdm_tbl(enum tdm_td2_port_speed speed[TDM_TD2_NUM_EXT_PORTS], int tdm_bw, 4641 int pgw_tdm_tbl_x0[32], int ovs_tdm_tbl_x0[32], int ovs_spacing_x0[32], 4642 int pgw_tdm_tbl_x1[32], int ovs_tdm_tbl_x1[32], int ovs_spacing_x1[32], 4643 int pgw_tdm_tbl_y0[32], int ovs_tdm_tbl_y0[32], int ovs_spacing_y0[32], 4644 int pgw_tdm_tbl_y1[32], int ovs_tdm_tbl_y1[32], int ovs_spacing_y1[32], 4645 int mmu_tdm_tbl_x[256], int mmu_tdm_ovs_x_1[16], int mmu_tdm_ovs_x_2[16], int mmu_tdm_ovs_x_3[16], int mmu_tdm_ovs_x_4[16], 4646 int mmu_tdm_tbl_y[256], int mmu_tdm_ovs_y_1[16], int mmu_tdm_ovs_y_2[16], int mmu_tdm_ovs_y_3[16], int mmu_tdm_ovs_y_4[16], 4647 int port_state_map[128], 4648 int iarb_tdm_tbl_x[512], int iarb_tdm_tbl_y[512]) 4649 { 4650 int wc_array[TDM_TD2_NUM_WC][4], i, j; 4651 4652 for (i=0; i< 256; i++) { 4653 mmu_tdm_tbl_x[i] = TDM_TD2_NUM_EXT_PORTS; 4654 mmu_tdm_tbl_y[i] = TDM_TD2_NUM_EXT_PORTS; 4655 } 4656 for (i=0; i<16; i++) { 4657 mmu_tdm_ovs_x_1[i] = TDM_TD2_NUM_EXT_PORTS; 4658 mmu_tdm_ovs_x_2[i] = TDM_TD2_NUM_EXT_PORTS; 4659 mmu_tdm_ovs_x_3[i] = TDM_TD2_NUM_EXT_PORTS; 4660 mmu_tdm_ovs_x_4[i] = TDM_TD2_NUM_EXT_PORTS; 4661 mmu_tdm_ovs_y_1[i] = TDM_TD2_NUM_EXT_PORTS; 4662 mmu_tdm_ovs_y_2[i] = TDM_TD2_NUM_EXT_PORTS; 4663 mmu_tdm_ovs_y_3[i] = TDM_TD2_NUM_EXT_PORTS; 4664 mmu_tdm_ovs_y_4[i] = TDM_TD2_NUM_EXT_PORTS; 4665 } 4666 for (i=0; i< 32; i++) { 4667 pgw_tdm_tbl_x0[i] = TDM_TD2_NUM_EXT_PORTS; 4668 ovs_tdm_tbl_x0[i] = TDM_TD2_NUM_EXT_PORTS; 4669 ovs_spacing_x0[i] = 32; 4670 pgw_tdm_tbl_x1[i] = TDM_TD2_NUM_EXT_PORTS; 4671 ovs_tdm_tbl_x1[i] = TDM_TD2_NUM_EXT_PORTS; 4672 ovs_spacing_x1[i] = 32; 4673 pgw_tdm_tbl_y0[i] = TDM_TD2_NUM_EXT_PORTS; 4674 ovs_tdm_tbl_y0[i] = TDM_TD2_NUM_EXT_PORTS; 4675 ovs_spacing_y0[i] = 32; 4676 pgw_tdm_tbl_y1[i] = TDM_TD2_NUM_EXT_PORTS; 4677 ovs_tdm_tbl_y1[i] = TDM_TD2_NUM_EXT_PORTS; 4678 ovs_spacing_y1[i] = 32; 4679 } 4680 4681 TSC_port_transcription(wc_array, speed, port_state_map); 4682 4683 for (i=0; i<24; i+=6) { 4684 pgw_tdm_tbl_x0[i]=1; 4685 pgw_tdm_tbl_x0[i+1]=5; 4686 pgw_tdm_tbl_x0[i+2]=17; 4687 pgw_tdm_tbl_x0[i+3]=21; 4688 pgw_tdm_tbl_y1[i]=109; 4689 pgw_tdm_tbl_y1[i+1]=113; 4690 } 4691 for (i=0; i<24; i++) { 4692 if (pgw_tdm_tbl_x0[i]==TDM_TD2_NUM_EXT_PORTS) pgw_tdm_tbl_x0[i]=131; 4693 if (pgw_tdm_tbl_x1[i]==TDM_TD2_NUM_EXT_PORTS) pgw_tdm_tbl_x1[i]=131; 4694 if (pgw_tdm_tbl_y0[i]==TDM_TD2_NUM_EXT_PORTS) pgw_tdm_tbl_y0[i]=131; 4695 if (pgw_tdm_tbl_y1[i]==TDM_TD2_NUM_EXT_PORTS) pgw_tdm_tbl_y1[i]=131; 4696 } 4697 ovs_tdm_tbl_x0[0]=13; ovs_spacing_x0[0]=8; 4698 ovs_tdm_tbl_x0[8]=14; ovs_spacing_x0[8]=8; 4699 ovs_tdm_tbl_x0[16]=15; ovs_spacing_x0[16]=8; 4700 ovs_tdm_tbl_x0[24]=16; ovs_spacing_x0[24]=8; 4701 for (i=0; i<32; i+=8) { 4702 for (j=0; j<2; j++) { 4703 ovs_tdm_tbl_x0[i+j+1]=( (25+(i/8))+(j*4) ); 4704 ovs_spacing_x0[i+j+1]=8; 4705 } 4706 for (j=0; j<8; j++) { 4707 ovs_tdm_tbl_x1[i+j]=( (33+(i/8))+(j*4) ); 4708 ovs_spacing_x1[i+j]=8; 4709 } 4710 for (j=0; j<8; j++) { 4711 ovs_tdm_tbl_y0[i+j]=( (65+(i/8))+(j*4) ); 4712 ovs_spacing_y0[i+j]=8; 4713 } 4714 for (j=0; j<3; j++) { 4715 ovs_tdm_tbl_y1[i+j]=( (97+(i/8))+(j*4) ); 4716 ovs_spacing_y1[i+j]=8; 4717 } 4718 } 4719 for (i=0; i<192; i+=12) mmu_tdm_tbl_x[i]=1; 4720 for (i=1; i<192; i+=12) mmu_tdm_tbl_x[i]=5; 4721 for (i=2; i<192; i+=12) mmu_tdm_tbl_x[i]=17; 4722 for (i=3; i<192; i+=12) mmu_tdm_tbl_x[i]=21; 4723 for (i=0; i<192; i+=12) mmu_tdm_tbl_y[i]=109; 4724 for (i=1; i<192; i+=12) mmu_tdm_tbl_y[i]=113; 4725 4726 for (i=255; i>24; i--) mmu_tdm_tbl_x[i]=mmu_tdm_tbl_x[i-1]; 4727 mmu_tdm_tbl_x[24]=0; 4728 for (i=255; i>49; i--) mmu_tdm_tbl_x[i]=mmu_tdm_tbl_x[i-1]; 4729 mmu_tdm_tbl_x[49]=132; 4730 for (i=255; i>74; i--) mmu_tdm_tbl_x[i]=mmu_tdm_tbl_x[i-1]; 4731 mmu_tdm_tbl_x[74]=0; 4732 for (i=255; i>99; i--) mmu_tdm_tbl_x[i]=mmu_tdm_tbl_x[i-1]; 4733 mmu_tdm_tbl_x[99]=132; 4734 for (i=255; i>124; i--) mmu_tdm_tbl_x[i]=mmu_tdm_tbl_x[i-1]; 4735 mmu_tdm_tbl_x[124]=132; 4736 for (i=255; i>149; i--) mmu_tdm_tbl_x[i]=mmu_tdm_tbl_x[i-1]; 4737 mmu_tdm_tbl_x[149]=0; 4738 for (i=255; i>174; i--) mmu_tdm_tbl_x[i]=mmu_tdm_tbl_x[i-1]; 4739 mmu_tdm_tbl_x[174]=132; 4740 for (i=255; i>199; i--) mmu_tdm_tbl_x[i]=mmu_tdm_tbl_x[i-1]; 4741 mmu_tdm_tbl_x[199]=132; 4742 4743 for (i=255; i>24; i--) mmu_tdm_tbl_y[i]=mmu_tdm_tbl_y[i-1]; 4744 mmu_tdm_tbl_y[24]=129; 4745 for (i=255; i>49; i--) mmu_tdm_tbl_y[i]=mmu_tdm_tbl_y[i-1]; 4746 mmu_tdm_tbl_y[49]=132; 4747 for (i=255; i>74; i--) mmu_tdm_tbl_y[i]=mmu_tdm_tbl_y[i-1]; 4748 mmu_tdm_tbl_y[74]=129; 4749 for (i=255; i>99; i--) mmu_tdm_tbl_y[i]=mmu_tdm_tbl_y[i-1]; 4750 mmu_tdm_tbl_y[99]=132; 4751 for (i=255; i>124; i--) mmu_tdm_tbl_y[i]=mmu_tdm_tbl_y[i-1]; 4752 mmu_tdm_tbl_y[124]=132; 4753 for (i=255; i>149; i--) mmu_tdm_tbl_y[i]=mmu_tdm_tbl_y[i-1]; 4754 mmu_tdm_tbl_y[149]=129; 4755 for (i=255; i>174; i--) mmu_tdm_tbl_y[i]=mmu_tdm_tbl_y[i-1]; 4756 mmu_tdm_tbl_y[174]=132; 4757 for (i=255; i>199; i--) mmu_tdm_tbl_y[i]=mmu_tdm_tbl_y[i-1]; 4758 mmu_tdm_tbl_y[199]=132; 4759 4760 for (i=0; i<200; i++) if (mmu_tdm_tbl_x[i]==TDM_TD2_NUM_EXT_PORTS) mmu_tdm_tbl_x[i]=131; 4761 for (i=0; i<200; i++) if (mmu_tdm_tbl_y[i]==TDM_TD2_NUM_EXT_PORTS) mmu_tdm_tbl_y[i]=131; 4762 4763 mmu_tdm_ovs_x_1[0]=13; 4764 mmu_tdm_ovs_x_1[4]=14; 4765 mmu_tdm_ovs_x_1[8]=15; 4766 mmu_tdm_ovs_x_1[12]=16; 4767 for (i=0; i<16; i+=4) for (j=0; j<2; j++) mmu_tdm_ovs_x_1[i+j+1]=( (25+(i/4))+(j*4) ); 4768 mmu_tdm_ovs_x_1[3]=33; 4769 mmu_tdm_ovs_x_1[7]=34; 4770 mmu_tdm_ovs_x_1[11]=35; 4771 mmu_tdm_ovs_x_1[15]=36; 4772 for (i=0; i<16; i+=4) for (j=0; j<4; j++) mmu_tdm_ovs_x_2[i+j]=( (37+(i/4))+(j*4) ); 4773 for (i=0; i<12; i+=3) for (j=0; j<3; j++) mmu_tdm_ovs_x_3[i+j]=( (53+(i/3))+(j*4) ); 4774 4775 for (i=0; i<16; i+=4) { 4776 for (j=0; j<4; j++) mmu_tdm_ovs_y_1[i+j]=( (65+(i/4))+(j*4) ); 4777 for (j=0; j<4; j++) mmu_tdm_ovs_y_2[i+j]=( (81+(i/4))+(j*4) ); 4778 } 4779 for (i=0; i<12; i+=3) for (j=0; j<3; j++) mmu_tdm_ovs_y_3[i+j]=( (97+(i/3))+(j*4) ); 4780 4781 print_tbl_summary(pgw_tdm_tbl_x0, pgw_tdm_tbl_x1, pgw_tdm_tbl_y0, pgw_tdm_tbl_y1, 4782 ovs_tdm_tbl_x0, ovs_tdm_tbl_x1, ovs_tdm_tbl_y0, ovs_tdm_tbl_y1, 4783 ovs_spacing_x0, ovs_spacing_x1, ovs_spacing_y0, ovs_spacing_y1, 4784 tdm_bw); 4785 4786 return 1; 4787 } 4788 #elif defined(TD2_HARD_CODE_JIRA_3668) 4789 /** 4790 @name: set_tdm_tbl 4791 @param: 4792 4793 Provides alternative hard-coded TDM instead of calling scheduler algorithm. 4794 */ 4795 int set_tdm_tbl(enum tdm_td2_port_speed speed[TDM_TD2_NUM_EXT_PORTS], int tdm_bw, 4796 int pgw_tdm_tbl_x0[32], int ovs_tdm_tbl_x0[32], int ovs_spacing_x0[32], 4797 int pgw_tdm_tbl_x1[32], int ovs_tdm_tbl_x1[32], int ovs_spacing_x1[32], 4798 int pgw_tdm_tbl_y0[32], int ovs_tdm_tbl_y0[32], int ovs_spacing_y0[32], 4799 int pgw_tdm_tbl_y1[32], int ovs_tdm_tbl_y1[32], int ovs_spacing_y1[32], 4800 int mmu_tdm_tbl_x[256], int mmu_tdm_ovs_x_1[16], int mmu_tdm_ovs_x_2[16], int mmu_tdm_ovs_x_3[16], int mmu_tdm_ovs_x_4[16], 4801 int mmu_tdm_tbl_y[256], int mmu_tdm_ovs_y_1[16], int mmu_tdm_ovs_y_2[16], int mmu_tdm_ovs_y_3[16], int mmu_tdm_ovs_y_4[16], 4802 int port_state_map[128], 4803 int iarb_tdm_tbl_x[512], int iarb_tdm_tbl_y[512]) 4804 { 4805 int wc_array[TDM_TD2_NUM_WC][4], i, j; 4806 4807 for (i=0; i< 256; i++) { 4808 mmu_tdm_tbl_x[i] = TDM_TD2_NUM_EXT_PORTS; 4809 mmu_tdm_tbl_y[i] = TDM_TD2_NUM_EXT_PORTS; 4810 } 4811 for (i=0; i<16; i++) { 4812 mmu_tdm_ovs_x_1[i] = TDM_TD2_NUM_EXT_PORTS; 4813 mmu_tdm_ovs_x_2[i] = TDM_TD2_NUM_EXT_PORTS; 4814 mmu_tdm_ovs_x_3[i] = TDM_TD2_NUM_EXT_PORTS; 4815 mmu_tdm_ovs_x_4[i] = TDM_TD2_NUM_EXT_PORTS; 4816 mmu_tdm_ovs_y_1[i] = TDM_TD2_NUM_EXT_PORTS; 4817 mmu_tdm_ovs_y_2[i] = TDM_TD2_NUM_EXT_PORTS; 4818 mmu_tdm_ovs_y_3[i] = TDM_TD2_NUM_EXT_PORTS; 4819 mmu_tdm_ovs_y_4[i] = TDM_TD2_NUM_EXT_PORTS; 4820 } 4821 for (i=0; i< 32; i++) { 4822 pgw_tdm_tbl_x0[i] = TDM_TD2_NUM_EXT_PORTS; 4823 ovs_tdm_tbl_x0[i] = TDM_TD2_NUM_EXT_PORTS; 4824 ovs_spacing_x0[i] = 32; 4825 pgw_tdm_tbl_x1[i] = TDM_TD2_NUM_EXT_PORTS; 4826 ovs_tdm_tbl_x1[i] = TDM_TD2_NUM_EXT_PORTS; 4827 ovs_spacing_x1[i] = 32; 4828 pgw_tdm_tbl_y0[i] = TDM_TD2_NUM_EXT_PORTS; 4829 ovs_tdm_tbl_y0[i] = TDM_TD2_NUM_EXT_PORTS; 4830 ovs_spacing_y0[i] = 32; 4831 pgw_tdm_tbl_y1[i] = TDM_TD2_NUM_EXT_PORTS; 4832 ovs_tdm_tbl_y1[i] = TDM_TD2_NUM_EXT_PORTS; 4833 ovs_spacing_y1[i] = 32; 4834 } 4835 4836 TSC_port_transcription(wc_array, speed, port_state_map); 4837 4838 pgw_tdm_tbl_x0[0]=1; 4839 pgw_tdm_tbl_x0[1]=5; 4840 pgw_tdm_tbl_x1[0]=33; 4841 pgw_tdm_tbl_x1[1]=37; 4842 pgw_tdm_tbl_y0[0]=93; 4843 pgw_tdm_tbl_y1[1]=97; 4844 pgw_tdm_tbl_y1[0]=121; 4845 pgw_tdm_tbl_y1[1]=125; 4846 for (i=4; i<24; i+=5) { 4847 pgw_tdm_tbl_x0[i]=1; 4848 pgw_tdm_tbl_x0[i+1]=5; 4849 pgw_tdm_tbl_x1[i]=33; 4850 pgw_tdm_tbl_x1[i+1]=37; 4851 pgw_tdm_tbl_y0[i]=93; 4852 pgw_tdm_tbl_y1[i]=97; 4853 pgw_tdm_tbl_y1[i+1]=121; 4854 pgw_tdm_tbl_y1[i+2]=125; 4855 } 4856 for (i=0; i<24; i++) { 4857 if (pgw_tdm_tbl_x0[i]==TDM_TD2_NUM_EXT_PORTS) pgw_tdm_tbl_x0[i]=131; 4858 if (pgw_tdm_tbl_x1[i]==TDM_TD2_NUM_EXT_PORTS) pgw_tdm_tbl_x1[i]=131; 4859 if (pgw_tdm_tbl_y0[i]==TDM_TD2_NUM_EXT_PORTS) pgw_tdm_tbl_y0[i]=131; 4860 if (pgw_tdm_tbl_y1[i]==TDM_TD2_NUM_EXT_PORTS) pgw_tdm_tbl_y1[i]=131; 4861 } 4862 for (i=0; i<32; i+=8) { 4863 for (j=0; j<6; j++) { 4864 ovs_tdm_tbl_x0[i+j]=( (9+(i/8))+(j*4) ); 4865 ovs_spacing_x0[i+j]=8; 4866 } 4867 for (j=0; j<6; j++) { 4868 ovs_tdm_tbl_x1[i+j]=( (41+(i/8))+(j*4) ); 4869 ovs_spacing_x1[i+j]=8; 4870 } 4871 for (j=0; j<7; j++) { 4872 ovs_tdm_tbl_y0[i+j]=( (65+(i/8))+(j*4) ); 4873 ovs_spacing_y0[i+j]=8; 4874 } 4875 for (j=0; j<5; j++) { 4876 ovs_tdm_tbl_y1[i+j]=( (101+(i/8))+(j*4) ); 4877 ovs_spacing_y1[i+j]=8; 4878 } 4879 } 4880 j=17; for (i=1; i<192; i+=11) {if (j>0) mmu_tdm_tbl_x[i]=1; j--;} 4881 j=17; for (i=4; i<192; i+=11) {if (j>0) mmu_tdm_tbl_x[i]=5; j--;} 4882 j=17; for (i=7; i<192; i+=11) {if (j>0) mmu_tdm_tbl_x[i]=33; j--;} 4883 j=17; for (i=10; i<192; i+=11) {if (j>0) mmu_tdm_tbl_x[i]=37; j--;} 4884 4885 j=17; for (i=1; i<192; i+=11) {if (j>0) mmu_tdm_tbl_y[i]=93; j--;} 4886 j=17; for (i=4; i<192; i+=11) {if (j>0) mmu_tdm_tbl_y[i]=97; j--;} 4887 j=17; for (i=7; i<192; i+=11) {if (j>0) mmu_tdm_tbl_y[i]=121; j--;} 4888 j=17; for (i=10; i<192; i+=11) {if (j>0) mmu_tdm_tbl_y[i]=125; j--;} 4889 4890 for (i=255; i>24; i--) mmu_tdm_tbl_x[i]=mmu_tdm_tbl_x[i-1]; 4891 mmu_tdm_tbl_x[24]=0; 4892 for (i=255; i>49; i--) mmu_tdm_tbl_x[i]=mmu_tdm_tbl_x[i-1]; 4893 mmu_tdm_tbl_x[49]=132; 4894 for (i=255; i>74; i--) mmu_tdm_tbl_x[i]=mmu_tdm_tbl_x[i-1]; 4895 mmu_tdm_tbl_x[74]=0; 4896 for (i=255; i>99; i--) mmu_tdm_tbl_x[i]=mmu_tdm_tbl_x[i-1]; 4897 mmu_tdm_tbl_x[99]=132; 4898 for (i=255; i>124; i--) mmu_tdm_tbl_x[i]=mmu_tdm_tbl_x[i-1]; 4899 mmu_tdm_tbl_x[124]=132; 4900 for (i=255; i>149; i--) mmu_tdm_tbl_x[i]=mmu_tdm_tbl_x[i-1]; 4901 mmu_tdm_tbl_x[149]=0; 4902 for (i=255; i>174; i--) mmu_tdm_tbl_x[i]=mmu_tdm_tbl_x[i-1]; 4903 mmu_tdm_tbl_x[174]=132; 4904 for (i=255; i>199; i--) mmu_tdm_tbl_x[i]=mmu_tdm_tbl_x[i-1]; 4905 mmu_tdm_tbl_x[199]=132; 4906 4907 for (i=255; i>24; i--) mmu_tdm_tbl_y[i]=mmu_tdm_tbl_y[i-1]; 4908 mmu_tdm_tbl_y[24]=129; 4909 for (i=255; i>49; i--) mmu_tdm_tbl_y[i]=mmu_tdm_tbl_y[i-1]; 4910 mmu_tdm_tbl_y[49]=132; 4911 for (i=255; i>74; i--) mmu_tdm_tbl_y[i]=mmu_tdm_tbl_y[i-1]; 4912 mmu_tdm_tbl_y[74]=129; 4913 for (i=255; i>99; i--) mmu_tdm_tbl_y[i]=mmu_tdm_tbl_y[i-1]; 4914 mmu_tdm_tbl_y[99]=132; 4915 for (i=255; i>124; i--) mmu_tdm_tbl_y[i]=mmu_tdm_tbl_y[i-1]; 4916 mmu_tdm_tbl_y[124]=132; 4917 for (i=255; i>149; i--) mmu_tdm_tbl_y[i]=mmu_tdm_tbl_y[i-1]; 4918 mmu_tdm_tbl_y[149]=129; 4919 for (i=255; i>174; i--) mmu_tdm_tbl_y[i]=mmu_tdm_tbl_y[i-1]; 4920 mmu_tdm_tbl_y[174]=132; 4921 for (i=255; i>199; i--) mmu_tdm_tbl_y[i]=mmu_tdm_tbl_y[i-1]; 4922 mmu_tdm_tbl_y[199]=132; 4923 4924 for (i=0; i<200; i++) if (mmu_tdm_tbl_x[i]==TDM_TD2_NUM_EXT_PORTS) mmu_tdm_tbl_x[i]=131; 4925 for (i=0; i<200; i++) if (mmu_tdm_tbl_y[i]==TDM_TD2_NUM_EXT_PORTS) mmu_tdm_tbl_y[i]=131; 4926 4927 for (i=0; i<16; i+=4) { 4928 for (j=0; j<4; j++) mmu_tdm_ovs_x_1[i+j]=( (9+(i/4))+(j*4) ); 4929 for (j=0; j<2; j++) mmu_tdm_ovs_x_2[i+j]=( (25+(i/4))+(j*4) ); 4930 for (j=2; j<4; j++) mmu_tdm_ovs_x_2[i+j]=( (33+(i/4))+(j*4) ); 4931 } 4932 for (i=0; i<12; i+=3) for (j=0; j<3; j++) mmu_tdm_ovs_x_3[i+j]=( (49+(i/3))+(j*4) ); 4933 4934 for (i=0; i<16; i+=4) { 4935 for (j=0; j<4; j++) mmu_tdm_ovs_y_1[i+j]=( (65+(i/4))+(j*4) ); 4936 for (j=0; j<4; j++) mmu_tdm_ovs_y_3[i+j]=( (105+(i/4))+(j*4) ); 4937 } 4938 for (i=0; i<16; i+=4) for (j=0; j<3; j++) mmu_tdm_ovs_y_2[i+j]=( (81+(i/4))+(j*4) ); 4939 mmu_tdm_ovs_y_2[3]=101; 4940 mmu_tdm_ovs_y_2[7]=102; 4941 mmu_tdm_ovs_y_2[11]=103; 4942 mmu_tdm_ovs_y_2[15]=104; 4943 4944 4945 print_tbl_summary(pgw_tdm_tbl_x0, pgw_tdm_tbl_x1, pgw_tdm_tbl_y0, pgw_tdm_tbl_y1, 4946 ovs_tdm_tbl_x0, ovs_tdm_tbl_x1, ovs_tdm_tbl_y0, ovs_tdm_tbl_y1, 4947 ovs_spacing_x0, ovs_spacing_x1, ovs_spacing_y0, ovs_spacing_y1, 4948 tdm_bw); 4949 4950 return 1; 4951 } 4952 #else 4953 /** 4954 @name: _soc_td2_set_tdm_tbl 4955 @param: 4956 4957 SV interfaced entry point for the 19 pre-configured TDM configurations 4958 */ 4959 int _soc_td2_set_tdm_tbl(enum tdm_td2_port_speed speed[TDM_TD2_NUM_EXT_PORTS], int tdm_bw, 4960 int pgw_tdm_tbl_x0[32], int ovs_tdm_tbl_x0[32], int ovs_spacing_x0[32], 4961 int pgw_tdm_tbl_x1[32], int ovs_tdm_tbl_x1[32], int ovs_spacing_x1[32], 4962 int pgw_tdm_tbl_y0[32], int ovs_tdm_tbl_y0[32], int ovs_spacing_y0[32], 4963 int pgw_tdm_tbl_y1[32], int ovs_tdm_tbl_y1[32], int ovs_spacing_y1[32], 4964 int mmu_tdm_tbl_x[256], int mmu_tdm_ovs_x_1[16], int mmu_tdm_ovs_x_2[16], int mmu_tdm_ovs_x_3[16], int mmu_tdm_ovs_x_4[16], 4965 int mmu_tdm_tbl_y[256], int mmu_tdm_ovs_y_1[16], int mmu_tdm_ovs_y_2[16], int mmu_tdm_ovs_y_3[16], int mmu_tdm_ovs_y_4[16], 4966 int port_state_map[128], 4967 int iarb_tdm_tbl_x[512], int iarb_tdm_tbl_y[512], 4968 int ancillary_bandwidth_mode) 4969 { 4970 int wc_array[TDM_TD2_NUM_WC][4], mgmtbw=0; 4971 int i; 4972 int checkpoint[6]; 4973 int op_flags_x[1]; 4974 int op_flags_y[1]; 4975 int ex_bw_cpu_en, ex_bw_lpbk_en; 4976 int acc_bw_type; 4977 4978 /* ancillary_bandwidth_mode: 0->regular, 1->CPU, 2->LOOPBACK, 3->CPU_and_LOOPBACK */ 4979 acc_bw_type = ancillary_bandwidth_mode; 4980 switch (acc_bw_type) { 4981 case 0: 4982 LOG_VERBOSE(BSL_LS_SOC_TDM, 4983 (BSL_META("TDM: _____VERBOSE: Ancillary Bandwidth config - %s\n"), 4984 "Regular")); 4985 break; 4986 case 1: 4987 LOG_VERBOSE(BSL_LS_SOC_TDM, 4988 (BSL_META("TDM: _____VERBOSE: Ancillary Bandwidth config - %s\n"), 4989 "Extra CPU Bandwidth")); 4990 break; 4991 case 2: 4992 LOG_VERBOSE(BSL_LS_SOC_TDM, 4993 (BSL_META("TDM: _____VERBOSE: Extra Ancillary Bandwidth config - %s\n"), 4994 "Extra LOOPBACK Bandwidth")); 4995 break; 4996 case 3: 4997 LOG_VERBOSE(BSL_LS_SOC_TDM, 4998 (BSL_META("TDM: _____VERBOSE: Extra Ancillary Bandwidth config - %s\n"), 4999 "Extra CPU_and_LOOPBACK Bandwidth")); 5000 break; 5001 default: 5002 LOG_VERBOSE(BSL_LS_SOC_TDM, 5003 (BSL_META("TDM: _____VERBOSE: Extra Ancillary Bandwidth config - %s\n"), 5004 "UNKNOWN")); 5005 acc_bw_type = 0; 5006 break; 5007 } 5008 /* if (speed[0]>=TDM_TD2_SPEED_1G && speed[129]>=TDM_TD2_SPEED_40G) { 5009 acc_bw_type = 3; 5010 } else if (speed[129]>=TDM_TD2_SPEED_40G) { 5011 acc_bw_type = 2; 5012 } else if (speed[0]>=TDM_TD2_SPEED_1G) { 5013 acc_bw_type = 1; 5014 } */ 5015 5016 if (pgw_tdm_tbl_x0[0]==1234) wc_array[3][0]=TDM_TD2_MGM_TOKEN; 5017 5018 for (i=0; i< 256; i++) 5019 { 5020 mmu_tdm_tbl_x[i] = TDM_TD2_NUM_EXT_PORTS; 5021 mmu_tdm_tbl_y[i] = TDM_TD2_NUM_EXT_PORTS; 5022 } 5023 for (i=0; i<16; i++) 5024 { 5025 mmu_tdm_ovs_x_1[i] = TDM_TD2_NUM_EXT_PORTS; 5026 mmu_tdm_ovs_x_2[i] = TDM_TD2_NUM_EXT_PORTS; 5027 mmu_tdm_ovs_x_3[i] = TDM_TD2_NUM_EXT_PORTS; 5028 mmu_tdm_ovs_x_4[i] = TDM_TD2_NUM_EXT_PORTS; 5029 mmu_tdm_ovs_y_1[i] = TDM_TD2_NUM_EXT_PORTS; 5030 mmu_tdm_ovs_y_2[i] = TDM_TD2_NUM_EXT_PORTS; 5031 mmu_tdm_ovs_y_3[i] = TDM_TD2_NUM_EXT_PORTS; 5032 mmu_tdm_ovs_y_4[i] = TDM_TD2_NUM_EXT_PORTS; 5033 } 5034 for (i=0; i< 32; i++){ 5035 pgw_tdm_tbl_x0[i] = TDM_TD2_NUM_EXT_PORTS; 5036 ovs_tdm_tbl_x0[i] = TDM_TD2_NUM_EXT_PORTS; 5037 ovs_spacing_x0[i] = TDM_TD2_NUM_EXT_PORTS; 5038 pgw_tdm_tbl_x1[i] = TDM_TD2_NUM_EXT_PORTS; 5039 ovs_tdm_tbl_x1[i] = TDM_TD2_NUM_EXT_PORTS; 5040 ovs_spacing_x1[i] = TDM_TD2_NUM_EXT_PORTS; 5041 pgw_tdm_tbl_y0[i] = TDM_TD2_NUM_EXT_PORTS; 5042 ovs_tdm_tbl_y0[i] = TDM_TD2_NUM_EXT_PORTS; 5043 ovs_spacing_y0[i] = TDM_TD2_NUM_EXT_PORTS; 5044 pgw_tdm_tbl_y1[i] = TDM_TD2_NUM_EXT_PORTS; 5045 ovs_tdm_tbl_y1[i] = TDM_TD2_NUM_EXT_PORTS; 5046 ovs_spacing_y1[i] = TDM_TD2_NUM_EXT_PORTS; 5047 } 5048 for (i=0; i<1; i++) { 5049 op_flags_x[i]=0; 5050 op_flags_y[i]=0; 5051 } 5052 5053 for (i=0; i< TDM_TD2_NUM_EXT_PORTS; i++) { 5054 LOG_VERBOSE(BSL_LS_SOC_TDM, 5055 (BSL_META("TDM: _____VERBOSE: the speed " 5056 "for port %0d is %0d\n"),i,speed[i])); 5057 } 5058 5059 TSC_port_transcription(wc_array, speed, port_state_map); 5060 print_port(wc_array, speed, port_state_map); 5061 5062 for (i=0; i<4; i++) if (wc_array[3][i]==TDM_TD2_MGM_TOKEN) mgmtbw++; 5063 5064 LOG_VERBOSE(BSL_LS_SOC_TDM, 5065 (BSL_META("TDM: _____VERBOSE: the chip bandwidth is %0d\n"), tdm_bw)); 5066 5067 checkpoint[0] = TDM_scheduler_wrap(wc_array, speed, pgw_tdm_tbl_x0, ovs_tdm_tbl_x0, 0, tdm_bw, port_state_map, 0, 32, &op_flags_x); 5068 print_tdm_tbl(pgw_tdm_tbl_x0, "Pipe_x0_PGW"); 5069 print_tdm_tbl(ovs_tdm_tbl_x0, "Pipe_x0_OVS"); 5070 checkpoint[1] = TDM_scheduler_wrap(wc_array, speed, pgw_tdm_tbl_x1, ovs_tdm_tbl_x1, 1, tdm_bw, port_state_map, 32, 64, &op_flags_x); 5071 print_tdm_tbl(pgw_tdm_tbl_x1, "Pipe_x1_PGW"); 5072 print_tdm_tbl(ovs_tdm_tbl_x1, "Pipe_x1_OVS"); 5073 checkpoint[2] = TDM_scheduler_wrap(wc_array, speed, pgw_tdm_tbl_y0, ovs_tdm_tbl_y0, 2, tdm_bw, port_state_map, 64, 96, &op_flags_y); 5074 print_tdm_tbl(pgw_tdm_tbl_y0, "Pipe_y0_PGW"); 5075 print_tdm_tbl(ovs_tdm_tbl_y0, "Pipe_y0_OVS"); 5076 checkpoint[3] = TDM_scheduler_wrap(wc_array, speed, pgw_tdm_tbl_y1, ovs_tdm_tbl_y1, 3, tdm_bw, port_state_map, 96, 128, &op_flags_y); 5077 print_tdm_tbl(pgw_tdm_tbl_y1, "Pipe_y1_PGW"); 5078 print_tdm_tbl(ovs_tdm_tbl_y1, "Pipe_y1_OVS"); 5079 5080 checkpoint[4] = write_mmu_tdm_tbl(pgw_tdm_tbl_x0, pgw_tdm_tbl_x1, ovs_tdm_tbl_x0, ovs_tdm_tbl_x1, mmu_tdm_tbl_x, mmu_tdm_ovs_x_1, mmu_tdm_ovs_x_2, mmu_tdm_ovs_x_3, mmu_tdm_ovs_x_4, TDM_TD2_TRUE, port_state_map, wc_array, tdm_bw, speed, &op_flags_x); 5081 checkpoint[5] = write_mmu_tdm_tbl(pgw_tdm_tbl_y0, pgw_tdm_tbl_y1, ovs_tdm_tbl_y0, ovs_tdm_tbl_y1, mmu_tdm_tbl_y, mmu_tdm_ovs_y_1, mmu_tdm_ovs_y_2, mmu_tdm_ovs_y_3, mmu_tdm_ovs_y_4, TDM_TD2_FALSE, port_state_map, wc_array, tdm_bw, speed, &op_flags_y); 5082 5083 if (ovs_tdm_tbl_x0[0] != TDM_TD2_NUM_EXT_PORTS) TDM_OVS_spacer(wc_array, ovs_tdm_tbl_x0, ovs_spacing_x0); 5084 if (ovs_tdm_tbl_x1[0] != TDM_TD2_NUM_EXT_PORTS) TDM_OVS_spacer(wc_array, ovs_tdm_tbl_x1, ovs_spacing_x1); 5085 if (ovs_tdm_tbl_y0[0] != TDM_TD2_NUM_EXT_PORTS) TDM_OVS_spacer(wc_array, ovs_tdm_tbl_y0, ovs_spacing_y0); 5086 if (ovs_tdm_tbl_y1[0] != TDM_TD2_NUM_EXT_PORTS) TDM_OVS_spacer(wc_array, ovs_tdm_tbl_y1, ovs_spacing_y1); 5087 5088 print_tbl_summary(pgw_tdm_tbl_x0, pgw_tdm_tbl_x1, pgw_tdm_tbl_y0, pgw_tdm_tbl_y1, 5089 ovs_tdm_tbl_x0, ovs_tdm_tbl_x1, ovs_tdm_tbl_y0, ovs_tdm_tbl_y1, 5090 ovs_spacing_x0, ovs_spacing_x1, ovs_spacing_y0, ovs_spacing_y1, 5091 tdm_bw); 5092 /* allocate ACC slots */ 5093 ex_bw_cpu_en = check_ex_bw_en(mmu_tdm_tbl_x, speed, acc_bw_type, 0); 5094 ex_bw_lpbk_en = check_ex_bw_en(mmu_tdm_tbl_y, speed, acc_bw_type, 1); 5095 if (ex_bw_cpu_en == TDM_TD2_TRUE) { 5096 parse_mmu_tdm_tbl_ex(tdm_bw, mgmtbw, mmu_tdm_tbl_x, mmu_tdm_ovs_x_1, mmu_tdm_ovs_x_2, mmu_tdm_ovs_x_3, mmu_tdm_ovs_x_4, 0, TDM_TD2_TRUE); 5097 } else { 5098 parse_mmu_tdm_tbl(tdm_bw, mgmtbw, mmu_tdm_tbl_x, mmu_tdm_ovs_x_1, mmu_tdm_ovs_x_2, mmu_tdm_ovs_x_3, mmu_tdm_ovs_x_4, 0); 5099 } 5100 if (ex_bw_lpbk_en == TDM_TD2_TRUE) { 5101 parse_mmu_tdm_tbl_ex(tdm_bw, mgmtbw, mmu_tdm_tbl_y, mmu_tdm_ovs_y_1, mmu_tdm_ovs_y_2, mmu_tdm_ovs_y_3, mmu_tdm_ovs_y_4, 1, TDM_TD2_TRUE); 5102 } else { 5103 parse_mmu_tdm_tbl(tdm_bw, mgmtbw, mmu_tdm_tbl_y, mmu_tdm_ovs_y_1, mmu_tdm_ovs_y_2, mmu_tdm_ovs_y_3, mmu_tdm_ovs_y_4, 1); 5104 } 5105 5106 if (checkpoint[0]==0||checkpoint[1]==0||checkpoint[2]==0||checkpoint[3]==0||checkpoint[4]==0||checkpoint[5]==0) 5107 { 5108 if (checkpoint[0]==0) { 5109 LOG_ERROR(BSL_LS_SOC_TDM, 5110 (BSL_META("TDM: _____ERROR: quadrant x0 failed to schedule\n"))); 5111 } 5112 if (checkpoint[1]==0) { 5113 LOG_ERROR(BSL_LS_SOC_TDM, 5114 (BSL_META("TDM: _____ERROR: quadrant x1 failed to schedule\n"))); 5115 } 5116 if (checkpoint[2]==0) { 5117 LOG_ERROR(BSL_LS_SOC_TDM, 5118 (BSL_META("TDM: _____ERROR: quadrant y0 failed to schedule\n"))); 5119 } 5120 if (checkpoint[3]==0) { 5121 LOG_ERROR(BSL_LS_SOC_TDM, 5122 (BSL_META("TDM: _____ERROR: quadrant y1 failed to schedule\n"))); 5123 } 5124 if (checkpoint[4]==0) { 5125 LOG_ERROR(BSL_LS_SOC_TDM, 5126 (BSL_META("TDM: _____ERROR: mmu x pipe table failed to schedule\n"))); 5127 } 5128 if (checkpoint[5]==0) { 5129 LOG_ERROR(BSL_LS_SOC_TDM, 5130 (BSL_META("TDM: _____ERROR: mmu y pipe table failed to schedule\n"))); 5131 } 5132 return 0; 5133 } 5134 else { 5135 return 1; 5136 } 5137 5138 } 5139 #endif 5140 5141 5142 /** 5143 @name: tdm_td2_init_iarb_tdm_ovs_table 5144 @param: int, int, int, int, int*, int*, int[512], int[512] 5145 5146 IARB TDM Oversubscription Schedule: 5147 Input 1 => Core bandwidth - 960/720/640/480. 5148 Input 2 => 1 if there are 4x1G management ports, 0 otherwise. 5149 Input 3 => 1 if there are 4x2.5G management ports, 0 otherwise. 5150 Input 4 => 1 if there are 1x10G management port, 0 otherwise. 5151 Output 5 => The X-pipe TDM oversubscription table wrap pointer value. 5152 Output 6 => The Y-pipe TDM oversubscription table wrap pointer value. 5153 Output 7 => The X-pipe TDM oversubscription schedule. 5154 Output 8 => The Y-pipe TDM oversubscription schedule. 5155 */ 5156 5157 void tdm_td2_init_iarb_tdm_ovs_table ( 5158 int core_bw, 5159 int mgm4x1, 5160 int mgm4x2p5, 5161 int mgm1x10, 5162 int *iarb_tdm_wrap_ptr_ovs_x, 5163 int *iarb_tdm_wrap_ptr_ovs_y, 5164 int iarb_tdm_tbl_ovs_x[512], 5165 int iarb_tdm_tbl_ovs_y[512] 5166 ) { 5167 int i; 5168 5169 switch (core_bw) { 5170 case 960 : 5171 /* First, assume no management ports. */ 5172 *iarb_tdm_wrap_ptr_ovs_x = 199; 5173 *iarb_tdm_wrap_ptr_ovs_y = 199; 5174 for (i = 0; i < 24; i++) { 5175 if (i%2 == 0) { 5176 iarb_tdm_tbl_ovs_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5177 iarb_tdm_tbl_ovs_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5178 } else { 5179 iarb_tdm_tbl_ovs_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5180 iarb_tdm_tbl_ovs_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5181 } 5182 } 5183 iarb_tdm_tbl_ovs_x[24] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 5184 iarb_tdm_tbl_ovs_y[24] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 5185 for (i = 25; i < 49; i++) { 5186 if (i%2 == 0) { 5187 iarb_tdm_tbl_ovs_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5188 iarb_tdm_tbl_ovs_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5189 } else { 5190 iarb_tdm_tbl_ovs_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5191 iarb_tdm_tbl_ovs_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5192 } 5193 } 5194 iarb_tdm_tbl_ovs_x[49] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 5195 iarb_tdm_tbl_ovs_y[49] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 5196 for (i = 50; i < 74; i++) { 5197 if (i%2 == 0) { 5198 iarb_tdm_tbl_ovs_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5199 iarb_tdm_tbl_ovs_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5200 } else { 5201 iarb_tdm_tbl_ovs_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5202 iarb_tdm_tbl_ovs_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5203 } 5204 } 5205 iarb_tdm_tbl_ovs_x[74] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 5206 iarb_tdm_tbl_ovs_y[74] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 5207 for (i = 75; i < 99; i++) { 5208 if (i%2 == 0) { 5209 iarb_tdm_tbl_ovs_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5210 iarb_tdm_tbl_ovs_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5211 } else { 5212 iarb_tdm_tbl_ovs_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5213 iarb_tdm_tbl_ovs_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5214 } 5215 } 5216 iarb_tdm_tbl_ovs_x[99] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 5217 iarb_tdm_tbl_ovs_y[99] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 5218 for (i = 100; i < 124; i++) { 5219 if (i%2 == 0) { 5220 iarb_tdm_tbl_ovs_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5221 iarb_tdm_tbl_ovs_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5222 } else { 5223 iarb_tdm_tbl_ovs_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5224 iarb_tdm_tbl_ovs_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5225 } 5226 } 5227 iarb_tdm_tbl_ovs_x[124] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 5228 iarb_tdm_tbl_ovs_y[124] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 5229 for (i = 125; i < 149; i++) { 5230 if (i%2 == 0) { 5231 iarb_tdm_tbl_ovs_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5232 iarb_tdm_tbl_ovs_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5233 } else { 5234 iarb_tdm_tbl_ovs_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5235 iarb_tdm_tbl_ovs_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5236 } 5237 } 5238 iarb_tdm_tbl_ovs_x[149] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 5239 iarb_tdm_tbl_ovs_y[149] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 5240 for (i = 150; i < 174; i++) { 5241 if (i%2 == 0) { 5242 iarb_tdm_tbl_ovs_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5243 iarb_tdm_tbl_ovs_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5244 } else { 5245 iarb_tdm_tbl_ovs_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5246 iarb_tdm_tbl_ovs_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5247 } 5248 } 5249 iarb_tdm_tbl_ovs_x[174] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 5250 iarb_tdm_tbl_ovs_y[174] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 5251 for (i = 175; i < 199; i++) { 5252 if (i%2 == 0) { 5253 iarb_tdm_tbl_ovs_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5254 iarb_tdm_tbl_ovs_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5255 } else { 5256 iarb_tdm_tbl_ovs_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5257 iarb_tdm_tbl_ovs_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5258 } 5259 } 5260 iarb_tdm_tbl_ovs_x[199] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 5261 iarb_tdm_tbl_ovs_y[199] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 5262 5263 /* Then check for management ports. */ 5264 if (mgm4x1) { 5265 iarb_tdm_tbl_ovs_x[24] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 5266 iarb_tdm_tbl_ovs_x[49] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 5267 iarb_tdm_tbl_ovs_x[74] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 5268 iarb_tdm_tbl_ovs_x[99] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 5269 } else if (mgm4x2p5 || mgm1x10) { 5270 /* 5271 Nate's comment in spreadsheet: "Not suppoted in Iarb. It's still possible 5272 to have a 10G management port scheduled with regular ports in PGW". 5273 */ 5274 } 5275 break; 5276 case 720 : 5277 /* First, assume no management ports. */ 5278 *iarb_tdm_wrap_ptr_ovs_x = 159; 5279 *iarb_tdm_wrap_ptr_ovs_y = 159; 5280 for (i = 0; i < 15; i++) { 5281 if (i%2 == 0) { 5282 iarb_tdm_tbl_ovs_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5283 iarb_tdm_tbl_ovs_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5284 } else { 5285 iarb_tdm_tbl_ovs_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5286 iarb_tdm_tbl_ovs_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5287 } 5288 } 5289 iarb_tdm_tbl_ovs_x[15] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5290 iarb_tdm_tbl_ovs_y[15] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 5291 iarb_tdm_tbl_ovs_x[16] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 5292 iarb_tdm_tbl_ovs_y[16] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5293 for (i = 17; i < 31; i++) { 5294 if (i%2 == 0) { 5295 iarb_tdm_tbl_ovs_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5296 iarb_tdm_tbl_ovs_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5297 } else { 5298 iarb_tdm_tbl_ovs_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5299 iarb_tdm_tbl_ovs_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5300 } 5301 } 5302 iarb_tdm_tbl_ovs_x[31] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 5303 iarb_tdm_tbl_ovs_y[31] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 5304 for (i = 32; i < 47; i++) { 5305 if (i%2 == 0) { 5306 iarb_tdm_tbl_ovs_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5307 iarb_tdm_tbl_ovs_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5308 } else { 5309 iarb_tdm_tbl_ovs_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5310 iarb_tdm_tbl_ovs_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5311 } 5312 } 5313 iarb_tdm_tbl_ovs_x[47] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5314 iarb_tdm_tbl_ovs_y[47] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 5315 iarb_tdm_tbl_ovs_x[48] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 5316 iarb_tdm_tbl_ovs_y[48] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5317 for (i = 49; i < 63; i++) { 5318 if (i%2 == 0) { 5319 iarb_tdm_tbl_ovs_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5320 iarb_tdm_tbl_ovs_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5321 } else { 5322 iarb_tdm_tbl_ovs_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5323 iarb_tdm_tbl_ovs_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5324 } 5325 } 5326 iarb_tdm_tbl_ovs_x[63] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 5327 iarb_tdm_tbl_ovs_y[63] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 5328 for (i = 64; i < 79; i++) { 5329 if (i%2 == 0) { 5330 iarb_tdm_tbl_ovs_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5331 iarb_tdm_tbl_ovs_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5332 } else { 5333 iarb_tdm_tbl_ovs_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5334 iarb_tdm_tbl_ovs_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5335 } 5336 } 5337 iarb_tdm_tbl_ovs_x[79] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5338 iarb_tdm_tbl_ovs_y[79] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 5339 iarb_tdm_tbl_ovs_x[80] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 5340 iarb_tdm_tbl_ovs_y[80] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5341 for (i = 81; i < 95; i++) { 5342 if (i%2 == 0) { 5343 iarb_tdm_tbl_ovs_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5344 iarb_tdm_tbl_ovs_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5345 } else { 5346 iarb_tdm_tbl_ovs_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5347 iarb_tdm_tbl_ovs_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5348 } 5349 } 5350 iarb_tdm_tbl_ovs_x[95] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 5351 iarb_tdm_tbl_ovs_y[95] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 5352 for (i = 96; i < 111; i++) { 5353 if (i%2 == 0) { 5354 iarb_tdm_tbl_ovs_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5355 iarb_tdm_tbl_ovs_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5356 } else { 5357 iarb_tdm_tbl_ovs_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5358 iarb_tdm_tbl_ovs_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5359 } 5360 } 5361 iarb_tdm_tbl_ovs_x[111] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5362 iarb_tdm_tbl_ovs_y[111] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 5363 iarb_tdm_tbl_ovs_x[112] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 5364 iarb_tdm_tbl_ovs_y[112] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5365 for (i = 113; i < 127; i++) { 5366 if (i%2 == 0) { 5367 iarb_tdm_tbl_ovs_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5368 iarb_tdm_tbl_ovs_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5369 } else { 5370 iarb_tdm_tbl_ovs_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5371 iarb_tdm_tbl_ovs_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5372 } 5373 } 5374 iarb_tdm_tbl_ovs_x[127] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 5375 iarb_tdm_tbl_ovs_y[127] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 5376 for (i = 128; i < 143; i++) { 5377 if (i%2 == 0) { 5378 iarb_tdm_tbl_ovs_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5379 iarb_tdm_tbl_ovs_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5380 } else { 5381 iarb_tdm_tbl_ovs_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5382 iarb_tdm_tbl_ovs_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5383 } 5384 } 5385 iarb_tdm_tbl_ovs_x[143] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5386 iarb_tdm_tbl_ovs_y[143] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 5387 iarb_tdm_tbl_ovs_x[144] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 5388 iarb_tdm_tbl_ovs_y[144] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5389 for (i = 145; i < 159; i++) { 5390 if (i%2 == 0) { 5391 iarb_tdm_tbl_ovs_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5392 iarb_tdm_tbl_ovs_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5393 } else { 5394 iarb_tdm_tbl_ovs_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5395 iarb_tdm_tbl_ovs_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5396 } 5397 } 5398 iarb_tdm_tbl_ovs_x[159] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 5399 iarb_tdm_tbl_ovs_y[159] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 5400 5401 /* Then check for management ports. */ 5402 if (mgm4x1) { 5403 iarb_tdm_tbl_ovs_x[16] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 5404 iarb_tdm_tbl_ovs_x[31] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 5405 iarb_tdm_tbl_ovs_x[48] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 5406 iarb_tdm_tbl_ovs_x[63] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 5407 } else if (mgm4x2p5 || mgm1x10) { 5408 iarb_tdm_tbl_ovs_x[16] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 5409 iarb_tdm_tbl_ovs_x[31] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 5410 iarb_tdm_tbl_ovs_x[48] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 5411 iarb_tdm_tbl_ovs_x[63] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 5412 iarb_tdm_tbl_ovs_x[80] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 5413 iarb_tdm_tbl_ovs_x[95] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 5414 iarb_tdm_tbl_ovs_x[112] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 5415 iarb_tdm_tbl_ovs_x[127] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 5416 } 5417 break; 5418 case 640 : 5419 /* First, assume no management ports. */ 5420 *iarb_tdm_wrap_ptr_ovs_x = 135; 5421 *iarb_tdm_wrap_ptr_ovs_y = 135; 5422 for (i = 0; i < 16; i++) { 5423 if (i%2 == 0) { 5424 iarb_tdm_tbl_ovs_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5425 iarb_tdm_tbl_ovs_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5426 } else { 5427 iarb_tdm_tbl_ovs_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5428 iarb_tdm_tbl_ovs_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5429 } 5430 } 5431 iarb_tdm_tbl_ovs_x[16] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 5432 iarb_tdm_tbl_ovs_y[16] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 5433 for (i = 17; i < 33; i++) { 5434 if (i%2 == 0) { 5435 iarb_tdm_tbl_ovs_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5436 iarb_tdm_tbl_ovs_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5437 } else { 5438 iarb_tdm_tbl_ovs_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5439 iarb_tdm_tbl_ovs_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5440 } 5441 } 5442 iarb_tdm_tbl_ovs_x[33] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 5443 iarb_tdm_tbl_ovs_y[33] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 5444 for (i = 34; i < 50; i++) { 5445 if (i%2 == 0) { 5446 iarb_tdm_tbl_ovs_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5447 iarb_tdm_tbl_ovs_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5448 } else { 5449 iarb_tdm_tbl_ovs_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5450 iarb_tdm_tbl_ovs_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5451 } 5452 } 5453 iarb_tdm_tbl_ovs_x[50] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 5454 iarb_tdm_tbl_ovs_y[50] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 5455 for (i = 51; i < 67; i++) { 5456 if (i%2 == 0) { 5457 iarb_tdm_tbl_ovs_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5458 iarb_tdm_tbl_ovs_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5459 } else { 5460 iarb_tdm_tbl_ovs_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5461 iarb_tdm_tbl_ovs_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5462 } 5463 } 5464 iarb_tdm_tbl_ovs_x[67] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 5465 iarb_tdm_tbl_ovs_y[67] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 5466 for (i = 68; i < 84; i++) { 5467 if (i%2 == 0) { 5468 iarb_tdm_tbl_ovs_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5469 iarb_tdm_tbl_ovs_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5470 } else { 5471 iarb_tdm_tbl_ovs_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5472 iarb_tdm_tbl_ovs_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5473 } 5474 } 5475 iarb_tdm_tbl_ovs_x[84] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 5476 iarb_tdm_tbl_ovs_y[84] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 5477 for (i = 85; i < 101; i++) { 5478 if (i%2 == 0) { 5479 iarb_tdm_tbl_ovs_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5480 iarb_tdm_tbl_ovs_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5481 } else { 5482 iarb_tdm_tbl_ovs_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5483 iarb_tdm_tbl_ovs_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5484 } 5485 } 5486 iarb_tdm_tbl_ovs_x[101] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 5487 iarb_tdm_tbl_ovs_y[101] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 5488 for (i = 102; i < 118; i++) { 5489 if (i%2 == 0) { 5490 iarb_tdm_tbl_ovs_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5491 iarb_tdm_tbl_ovs_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5492 } else { 5493 iarb_tdm_tbl_ovs_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5494 iarb_tdm_tbl_ovs_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5495 } 5496 } 5497 iarb_tdm_tbl_ovs_x[118] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 5498 iarb_tdm_tbl_ovs_y[118] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 5499 for (i = 119; i < 135; i++) { 5500 if (i%2 == 0) { 5501 iarb_tdm_tbl_ovs_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5502 iarb_tdm_tbl_ovs_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5503 } else { 5504 iarb_tdm_tbl_ovs_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5505 iarb_tdm_tbl_ovs_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5506 } 5507 } 5508 iarb_tdm_tbl_ovs_x[135] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 5509 iarb_tdm_tbl_ovs_y[135] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 5510 5511 /* Then check for management ports. */ 5512 if (mgm4x1) { 5513 iarb_tdm_tbl_ovs_x[16] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 5514 iarb_tdm_tbl_ovs_x[50] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 5515 iarb_tdm_tbl_ovs_x[33] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 5516 iarb_tdm_tbl_ovs_x[67] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 5517 } else if (mgm4x2p5 || mgm1x10) { 5518 /* 5519 Nate's comment in spreadsheet: "Not suppoted in Iarb. It's still possible 5520 to have a 10G management port scheduled with regular ports in PGW". 5521 */ 5522 } 5523 break; 5524 case 480 : 5525 /* First, assume no management ports. */ 5526 *iarb_tdm_wrap_ptr_ovs_x = 105; 5527 *iarb_tdm_wrap_ptr_ovs_y = 105; 5528 for (i = 0; i < 10; i++) { 5529 if (i%2 == 0) { 5530 iarb_tdm_tbl_ovs_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5531 iarb_tdm_tbl_ovs_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5532 } else { 5533 iarb_tdm_tbl_ovs_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5534 iarb_tdm_tbl_ovs_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5535 } 5536 } 5537 iarb_tdm_tbl_ovs_x[10] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 5538 iarb_tdm_tbl_ovs_y[10] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 5539 for (i = 11; i < 20; i++) { 5540 if (i%2 == 0) { 5541 iarb_tdm_tbl_ovs_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5542 iarb_tdm_tbl_ovs_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5543 } else { 5544 iarb_tdm_tbl_ovs_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5545 iarb_tdm_tbl_ovs_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5546 } 5547 } 5548 iarb_tdm_tbl_ovs_x[20] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5549 iarb_tdm_tbl_ovs_y[20] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 5550 iarb_tdm_tbl_ovs_x[21] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 5551 iarb_tdm_tbl_ovs_y[21] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5552 for (i = 22; i < 30; i++) { 5553 if (i%2 == 0) { 5554 iarb_tdm_tbl_ovs_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5555 iarb_tdm_tbl_ovs_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5556 } else { 5557 iarb_tdm_tbl_ovs_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5558 iarb_tdm_tbl_ovs_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5559 } 5560 } 5561 iarb_tdm_tbl_ovs_x[30] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 5562 iarb_tdm_tbl_ovs_y[30] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5563 iarb_tdm_tbl_ovs_x[31] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5564 iarb_tdm_tbl_ovs_y[31] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 5565 for (i = 32; i < 41; i++) { 5566 if (i%2 == 0) { 5567 iarb_tdm_tbl_ovs_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5568 iarb_tdm_tbl_ovs_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5569 } else { 5570 iarb_tdm_tbl_ovs_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5571 iarb_tdm_tbl_ovs_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5572 } 5573 } 5574 iarb_tdm_tbl_ovs_x[41] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 5575 iarb_tdm_tbl_ovs_y[41] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 5576 for (i = 42; i < 52; i++) { 5577 if (i%2 == 0) { 5578 iarb_tdm_tbl_ovs_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5579 iarb_tdm_tbl_ovs_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5580 } else { 5581 iarb_tdm_tbl_ovs_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5582 iarb_tdm_tbl_ovs_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5583 } 5584 } 5585 iarb_tdm_tbl_ovs_x[52] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 5586 iarb_tdm_tbl_ovs_y[52] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 5587 for (i = 53; i < 63; i++) { 5588 if (i%2 == 0) { 5589 iarb_tdm_tbl_ovs_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5590 iarb_tdm_tbl_ovs_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5591 } else { 5592 iarb_tdm_tbl_ovs_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5593 iarb_tdm_tbl_ovs_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5594 } 5595 } 5596 iarb_tdm_tbl_ovs_x[63] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 5597 iarb_tdm_tbl_ovs_y[63] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 5598 for (i = 64; i < 73; i++) { 5599 if (i%2 == 0) { 5600 iarb_tdm_tbl_ovs_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5601 iarb_tdm_tbl_ovs_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5602 } else { 5603 iarb_tdm_tbl_ovs_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5604 iarb_tdm_tbl_ovs_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5605 } 5606 } 5607 iarb_tdm_tbl_ovs_x[73] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5608 iarb_tdm_tbl_ovs_y[73] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 5609 iarb_tdm_tbl_ovs_x[74] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 5610 iarb_tdm_tbl_ovs_y[74] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5611 for (i = 75; i < 83; i++) { 5612 if (i%2 == 0) { 5613 iarb_tdm_tbl_ovs_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5614 iarb_tdm_tbl_ovs_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5615 } else { 5616 iarb_tdm_tbl_ovs_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5617 iarb_tdm_tbl_ovs_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5618 } 5619 } 5620 iarb_tdm_tbl_ovs_x[83] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 5621 iarb_tdm_tbl_ovs_y[83] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5622 iarb_tdm_tbl_ovs_x[84] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5623 iarb_tdm_tbl_ovs_y[84] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 5624 for (i = 85; i < 94; i++) { 5625 if (i%2 == 0) { 5626 iarb_tdm_tbl_ovs_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5627 iarb_tdm_tbl_ovs_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5628 } else { 5629 iarb_tdm_tbl_ovs_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5630 iarb_tdm_tbl_ovs_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5631 } 5632 } 5633 iarb_tdm_tbl_ovs_x[94] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 5634 iarb_tdm_tbl_ovs_y[94] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 5635 for (i = 95; i < 105; i++) { 5636 if (i%2 == 0) { 5637 iarb_tdm_tbl_ovs_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5638 iarb_tdm_tbl_ovs_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5639 } else { 5640 iarb_tdm_tbl_ovs_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5641 iarb_tdm_tbl_ovs_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5642 } 5643 } 5644 iarb_tdm_tbl_ovs_x[105] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 5645 iarb_tdm_tbl_ovs_y[105] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 5646 5647 /* Then check for management ports. */ 5648 if (mgm4x1) { 5649 iarb_tdm_tbl_ovs_x[10] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 5650 iarb_tdm_tbl_ovs_x[21] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 5651 iarb_tdm_tbl_ovs_x[30] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 5652 iarb_tdm_tbl_ovs_x[41] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 5653 } else if (mgm4x2p5 || mgm1x10) { 5654 iarb_tdm_tbl_ovs_x[10] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 5655 iarb_tdm_tbl_ovs_x[21] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 5656 iarb_tdm_tbl_ovs_x[30] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 5657 iarb_tdm_tbl_ovs_x[41] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 5658 iarb_tdm_tbl_ovs_x[52] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 5659 iarb_tdm_tbl_ovs_x[63] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 5660 iarb_tdm_tbl_ovs_x[74] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 5661 iarb_tdm_tbl_ovs_x[83] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 5662 } 5663 break; 5664 } 5665 } 5666 5667 5668 /** 5669 @name: tdm_td2_init_iarb_tdm_lr_table 5670 @param: int, int, int, int, int*, int*, int[512], int[512] 5671 5672 IARB TDM Linerate Schedule: 5673 Input 1 => Core bandwidth - 960/720/640/480. 5674 Input 2 => 1 if there are 4x1G management ports, 0 otherwise. 5675 Input 3 => 1 if there are 4x2.5G management ports, 0 otherwise. 5676 Input 4 => 1 if there are 1x10G management port, 0 otherwise. 5677 Output 5 => The X-pipe TDM linerate table wrap pointer value. 5678 Output 6 => The Y-pipe TDM linerate table wrap pointer value. 5679 Output 7 => The X-pipe TDM linerate schedule. 5680 Output 8 => The Y-pipe TDM linerate schedule. 5681 */ 5682 5683 void tdm_td2_init_iarb_tdm_lr_table ( 5684 int core_bw, 5685 int mgm4x1, 5686 int mgm4x2p5, 5687 int mgm1x10, 5688 int *iarb_tdm_wrap_ptr_lr_x, 5689 int *iarb_tdm_wrap_ptr_lr_y, 5690 int iarb_tdm_tbl_lr_x[512], 5691 int iarb_tdm_tbl_lr_y[512] 5692 ) { 5693 int i; 5694 5695 switch (core_bw) { 5696 case 960 : 5697 /* First, assume no management ports. */ 5698 *iarb_tdm_wrap_ptr_lr_x = 199; 5699 *iarb_tdm_wrap_ptr_lr_y = 199; 5700 for (i = 0; i < 24; i++) { 5701 if (i%2 == 0) { 5702 iarb_tdm_tbl_lr_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5703 iarb_tdm_tbl_lr_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5704 } else { 5705 iarb_tdm_tbl_lr_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5706 iarb_tdm_tbl_lr_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5707 } 5708 } 5709 iarb_tdm_tbl_lr_x[24] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 5710 iarb_tdm_tbl_lr_y[24] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 5711 for (i = 25; i < 49; i++) { 5712 if (i%2 == 0) { 5713 iarb_tdm_tbl_lr_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5714 iarb_tdm_tbl_lr_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5715 } else { 5716 iarb_tdm_tbl_lr_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5717 iarb_tdm_tbl_lr_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5718 } 5719 } 5720 iarb_tdm_tbl_lr_x[49] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 5721 iarb_tdm_tbl_lr_y[49] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 5722 for (i = 50; i < 74; i++) { 5723 if (i%2 == 0) { 5724 iarb_tdm_tbl_lr_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5725 iarb_tdm_tbl_lr_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5726 } else { 5727 iarb_tdm_tbl_lr_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5728 iarb_tdm_tbl_lr_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5729 } 5730 } 5731 iarb_tdm_tbl_lr_x[74] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 5732 iarb_tdm_tbl_lr_y[74] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 5733 for (i = 75; i < 99; i++) { 5734 if (i%2 == 0) { 5735 iarb_tdm_tbl_lr_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5736 iarb_tdm_tbl_lr_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5737 } else { 5738 iarb_tdm_tbl_lr_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5739 iarb_tdm_tbl_lr_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5740 } 5741 } 5742 iarb_tdm_tbl_lr_x[99] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 5743 iarb_tdm_tbl_lr_y[99] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 5744 for (i = 100; i < 124; i++) { 5745 if (i%2 == 0) { 5746 iarb_tdm_tbl_lr_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5747 iarb_tdm_tbl_lr_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5748 } else { 5749 iarb_tdm_tbl_lr_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5750 iarb_tdm_tbl_lr_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5751 } 5752 } 5753 iarb_tdm_tbl_lr_x[124] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 5754 iarb_tdm_tbl_lr_y[124] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 5755 for (i = 125; i < 149; i++) { 5756 if (i%2 == 0) { 5757 iarb_tdm_tbl_lr_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5758 iarb_tdm_tbl_lr_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5759 } else { 5760 iarb_tdm_tbl_lr_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5761 iarb_tdm_tbl_lr_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5762 } 5763 } 5764 iarb_tdm_tbl_lr_x[149] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 5765 iarb_tdm_tbl_lr_y[149] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 5766 for (i = 150; i < 174; i++) { 5767 if (i%2 == 0) { 5768 iarb_tdm_tbl_lr_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5769 iarb_tdm_tbl_lr_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5770 } else { 5771 iarb_tdm_tbl_lr_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5772 iarb_tdm_tbl_lr_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5773 } 5774 } 5775 iarb_tdm_tbl_lr_x[174] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 5776 iarb_tdm_tbl_lr_y[174] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 5777 for (i = 175; i < 199; i++) { 5778 if (i%2 == 0) { 5779 iarb_tdm_tbl_lr_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5780 iarb_tdm_tbl_lr_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5781 } else { 5782 iarb_tdm_tbl_lr_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5783 iarb_tdm_tbl_lr_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5784 } 5785 } 5786 iarb_tdm_tbl_lr_x[199] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 5787 iarb_tdm_tbl_lr_y[199] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 5788 5789 /* Then check for management ports. */ 5790 if (mgm4x1) { 5791 iarb_tdm_tbl_lr_x[24] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 5792 iarb_tdm_tbl_lr_x[74] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 5793 iarb_tdm_tbl_lr_x[124] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 5794 iarb_tdm_tbl_lr_x[174] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 5795 iarb_tdm_tbl_lr_x[199] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 5796 } else if (mgm4x2p5 || mgm1x10) { 5797 iarb_tdm_tbl_lr_x[24] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 5798 iarb_tdm_tbl_lr_x[74] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 5799 iarb_tdm_tbl_lr_x[124] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 5800 iarb_tdm_tbl_lr_x[174] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 5801 iarb_tdm_tbl_lr_x[49] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 5802 iarb_tdm_tbl_lr_x[99] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 5803 iarb_tdm_tbl_lr_x[149] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 5804 iarb_tdm_tbl_lr_x[199] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 5805 } 5806 break; 5807 case 720 : 5808 /* First, assume no management ports. */ 5809 *iarb_tdm_wrap_ptr_lr_x = 159; 5810 *iarb_tdm_wrap_ptr_lr_y = 159; 5811 for (i = 0; i < 15; i++) { 5812 if (i%2 == 0) { 5813 iarb_tdm_tbl_lr_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5814 iarb_tdm_tbl_lr_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5815 } else { 5816 iarb_tdm_tbl_lr_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5817 iarb_tdm_tbl_lr_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5818 } 5819 } 5820 iarb_tdm_tbl_lr_x[15] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 5821 iarb_tdm_tbl_lr_y[15] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 5822 for (i = 16; i < 31; i++) { 5823 if (i%2 == 0) { 5824 iarb_tdm_tbl_lr_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5825 iarb_tdm_tbl_lr_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5826 } else { 5827 iarb_tdm_tbl_lr_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5828 iarb_tdm_tbl_lr_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5829 } 5830 } 5831 iarb_tdm_tbl_lr_x[31] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 5832 iarb_tdm_tbl_lr_y[31] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 5833 for (i = 32; i < 47; i++) { 5834 if (i%2 == 0) { 5835 iarb_tdm_tbl_lr_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5836 iarb_tdm_tbl_lr_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5837 } else { 5838 iarb_tdm_tbl_lr_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5839 iarb_tdm_tbl_lr_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5840 } 5841 } 5842 iarb_tdm_tbl_lr_x[47] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 5843 iarb_tdm_tbl_lr_y[47] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 5844 for (i = 48; i < 63; i++) { 5845 if (i%2 == 0) { 5846 iarb_tdm_tbl_lr_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5847 iarb_tdm_tbl_lr_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5848 } else { 5849 iarb_tdm_tbl_lr_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5850 iarb_tdm_tbl_lr_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5851 } 5852 } 5853 iarb_tdm_tbl_lr_x[63] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 5854 iarb_tdm_tbl_lr_y[63] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 5855 for (i = 64; i < 79; i++) { 5856 if (i%2 == 0) { 5857 iarb_tdm_tbl_lr_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5858 iarb_tdm_tbl_lr_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5859 } else { 5860 iarb_tdm_tbl_lr_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5861 iarb_tdm_tbl_lr_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5862 } 5863 } 5864 iarb_tdm_tbl_lr_x[79] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 5865 iarb_tdm_tbl_lr_y[79] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 5866 for (i = 80; i < 95; i++) { 5867 if (i%2 == 0) { 5868 iarb_tdm_tbl_lr_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5869 iarb_tdm_tbl_lr_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5870 } else { 5871 iarb_tdm_tbl_lr_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5872 iarb_tdm_tbl_lr_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5873 } 5874 } 5875 iarb_tdm_tbl_lr_x[95] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 5876 iarb_tdm_tbl_lr_y[95] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 5877 for (i = 96; i < 111; i++) { 5878 if (i%2 == 0) { 5879 iarb_tdm_tbl_lr_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5880 iarb_tdm_tbl_lr_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5881 } else { 5882 iarb_tdm_tbl_lr_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5883 iarb_tdm_tbl_lr_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5884 } 5885 } 5886 iarb_tdm_tbl_lr_x[111] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 5887 iarb_tdm_tbl_lr_y[111] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 5888 for (i = 112; i < 127; i++) { 5889 if (i%2 == 0) { 5890 iarb_tdm_tbl_lr_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5891 iarb_tdm_tbl_lr_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5892 } else { 5893 iarb_tdm_tbl_lr_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5894 iarb_tdm_tbl_lr_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5895 } 5896 } 5897 iarb_tdm_tbl_lr_x[127] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 5898 iarb_tdm_tbl_lr_y[127] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 5899 for (i = 128; i < 143; i++) { 5900 if (i%2 == 0) { 5901 iarb_tdm_tbl_lr_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5902 iarb_tdm_tbl_lr_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5903 } else { 5904 iarb_tdm_tbl_lr_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5905 iarb_tdm_tbl_lr_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5906 } 5907 } 5908 iarb_tdm_tbl_lr_x[143] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 5909 iarb_tdm_tbl_lr_y[143] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 5910 for (i = 144; i < 159; i++) { 5911 if (i%2 == 0) { 5912 iarb_tdm_tbl_lr_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5913 iarb_tdm_tbl_lr_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5914 } else { 5915 iarb_tdm_tbl_lr_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5916 iarb_tdm_tbl_lr_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5917 } 5918 } 5919 iarb_tdm_tbl_lr_x[159] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 5920 iarb_tdm_tbl_lr_y[159] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 5921 5922 /* Then check for management ports. */ 5923 if (mgm4x1) { 5924 iarb_tdm_tbl_lr_x[15] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 5925 iarb_tdm_tbl_lr_x[31] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 5926 iarb_tdm_tbl_lr_x[47] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 5927 iarb_tdm_tbl_lr_x[63] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 5928 } else if (mgm4x2p5 || mgm1x10) { 5929 iarb_tdm_tbl_lr_x[15] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 5930 iarb_tdm_tbl_lr_x[31] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 5931 iarb_tdm_tbl_lr_x[47] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 5932 iarb_tdm_tbl_lr_x[63] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 5933 iarb_tdm_tbl_lr_x[79] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 5934 iarb_tdm_tbl_lr_x[95] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 5935 iarb_tdm_tbl_lr_x[111] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 5936 iarb_tdm_tbl_lr_x[127] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 5937 } 5938 break; 5939 case 640 : 5940 /* First, assume no management ports. */ 5941 *iarb_tdm_wrap_ptr_lr_x = 135; 5942 *iarb_tdm_wrap_ptr_lr_y = 135; 5943 for (i = 0; i < 16; i++) { 5944 if (i%2 == 0) { 5945 iarb_tdm_tbl_lr_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5946 iarb_tdm_tbl_lr_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5947 } else { 5948 iarb_tdm_tbl_lr_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5949 iarb_tdm_tbl_lr_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5950 } 5951 } 5952 iarb_tdm_tbl_lr_x[16] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 5953 iarb_tdm_tbl_lr_y[16] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 5954 for (i = 17; i < 33; i++) { 5955 if (i%2 == 0) { 5956 iarb_tdm_tbl_lr_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5957 iarb_tdm_tbl_lr_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5958 } else { 5959 iarb_tdm_tbl_lr_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5960 iarb_tdm_tbl_lr_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5961 } 5962 } 5963 iarb_tdm_tbl_lr_x[33] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 5964 iarb_tdm_tbl_lr_y[33] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 5965 for (i = 34; i < 50; i++) { 5966 if (i%2 == 0) { 5967 iarb_tdm_tbl_lr_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5968 iarb_tdm_tbl_lr_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5969 } else { 5970 iarb_tdm_tbl_lr_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5971 iarb_tdm_tbl_lr_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5972 } 5973 } 5974 iarb_tdm_tbl_lr_x[50] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 5975 iarb_tdm_tbl_lr_y[50] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 5976 for (i = 51; i < 67; i++) { 5977 if (i%2 == 0) { 5978 iarb_tdm_tbl_lr_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5979 iarb_tdm_tbl_lr_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5980 } else { 5981 iarb_tdm_tbl_lr_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5982 iarb_tdm_tbl_lr_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5983 } 5984 } 5985 iarb_tdm_tbl_lr_x[67] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 5986 iarb_tdm_tbl_lr_y[67] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 5987 for (i = 68; i < 84; i++) { 5988 if (i%2 == 0) { 5989 iarb_tdm_tbl_lr_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5990 iarb_tdm_tbl_lr_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 5991 } else { 5992 iarb_tdm_tbl_lr_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5993 iarb_tdm_tbl_lr_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 5994 } 5995 } 5996 iarb_tdm_tbl_lr_x[84] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 5997 iarb_tdm_tbl_lr_y[84] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 5998 for (i = 85; i < 101; i++) { 5999 if (i%2 == 0) { 6000 iarb_tdm_tbl_lr_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 6001 iarb_tdm_tbl_lr_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 6002 } else { 6003 iarb_tdm_tbl_lr_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 6004 iarb_tdm_tbl_lr_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 6005 } 6006 } 6007 iarb_tdm_tbl_lr_x[101] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 6008 iarb_tdm_tbl_lr_y[101] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 6009 for (i = 102; i < 118; i++) { 6010 if (i%2 == 0) { 6011 iarb_tdm_tbl_lr_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 6012 iarb_tdm_tbl_lr_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 6013 } else { 6014 iarb_tdm_tbl_lr_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 6015 iarb_tdm_tbl_lr_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 6016 } 6017 } 6018 iarb_tdm_tbl_lr_x[118] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 6019 iarb_tdm_tbl_lr_y[118] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 6020 for (i = 119; i < 135; i++) { 6021 if (i%2 == 0) { 6022 iarb_tdm_tbl_lr_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 6023 iarb_tdm_tbl_lr_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 6024 } else { 6025 iarb_tdm_tbl_lr_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 6026 iarb_tdm_tbl_lr_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 6027 } 6028 } 6029 iarb_tdm_tbl_lr_x[135] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 6030 iarb_tdm_tbl_lr_y[135] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 6031 6032 /* Then check for management ports. */ 6033 if (mgm4x1) { 6034 iarb_tdm_tbl_lr_x[16] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 6035 iarb_tdm_tbl_lr_x[50] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 6036 iarb_tdm_tbl_lr_x[33] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 6037 iarb_tdm_tbl_lr_x[67] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 6038 } else if (mgm4x2p5 || mgm1x10) { 6039 iarb_tdm_tbl_lr_x[16] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 6040 iarb_tdm_tbl_lr_x[50] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 6041 iarb_tdm_tbl_lr_x[33] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 6042 iarb_tdm_tbl_lr_x[67] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 6043 iarb_tdm_tbl_lr_x[84] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 6044 iarb_tdm_tbl_lr_x[101] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 6045 iarb_tdm_tbl_lr_x[118] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 6046 iarb_tdm_tbl_lr_x[135] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 6047 } 6048 break; 6049 case 480 : 6050 /* First, assume no management ports. */ 6051 *iarb_tdm_wrap_ptr_lr_x = 105; 6052 *iarb_tdm_wrap_ptr_lr_y = 105; 6053 for (i = 0; i < 10; i++) { 6054 if (i%2 == 0) { 6055 iarb_tdm_tbl_lr_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 6056 iarb_tdm_tbl_lr_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 6057 } else { 6058 iarb_tdm_tbl_lr_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 6059 iarb_tdm_tbl_lr_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 6060 } 6061 } 6062 iarb_tdm_tbl_lr_x[10] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 6063 iarb_tdm_tbl_lr_y[10] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 6064 for (i = 11; i < 20; i++) { 6065 if (i%2 == 0) { 6066 iarb_tdm_tbl_lr_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 6067 iarb_tdm_tbl_lr_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 6068 } else { 6069 iarb_tdm_tbl_lr_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 6070 iarb_tdm_tbl_lr_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 6071 } 6072 } 6073 iarb_tdm_tbl_lr_x[20] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 6074 iarb_tdm_tbl_lr_y[20] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 6075 iarb_tdm_tbl_lr_x[21] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 6076 iarb_tdm_tbl_lr_y[21] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 6077 for (i = 22; i < 30; i++) { 6078 if (i%2 == 0) { 6079 iarb_tdm_tbl_lr_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 6080 iarb_tdm_tbl_lr_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 6081 } else { 6082 iarb_tdm_tbl_lr_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 6083 iarb_tdm_tbl_lr_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 6084 } 6085 } 6086 iarb_tdm_tbl_lr_x[30] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 6087 iarb_tdm_tbl_lr_y[30] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 6088 iarb_tdm_tbl_lr_x[31] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 6089 iarb_tdm_tbl_lr_y[31] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 6090 for (i = 32; i < 41; i++) { 6091 if (i%2 == 0) { 6092 iarb_tdm_tbl_lr_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 6093 iarb_tdm_tbl_lr_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 6094 } else { 6095 iarb_tdm_tbl_lr_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 6096 iarb_tdm_tbl_lr_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 6097 } 6098 } 6099 iarb_tdm_tbl_lr_x[41] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 6100 iarb_tdm_tbl_lr_y[41] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 6101 for (i = 42; i < 52; i++) { 6102 if (i%2 == 0) { 6103 iarb_tdm_tbl_lr_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 6104 iarb_tdm_tbl_lr_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 6105 } else { 6106 iarb_tdm_tbl_lr_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 6107 iarb_tdm_tbl_lr_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 6108 } 6109 } 6110 iarb_tdm_tbl_lr_x[52] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 6111 iarb_tdm_tbl_lr_y[52] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 6112 for (i = 53; i < 63; i++) { 6113 if (i%2 == 0) { 6114 iarb_tdm_tbl_lr_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 6115 iarb_tdm_tbl_lr_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 6116 } else { 6117 iarb_tdm_tbl_lr_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 6118 iarb_tdm_tbl_lr_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 6119 } 6120 } 6121 iarb_tdm_tbl_lr_x[63] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 6122 iarb_tdm_tbl_lr_y[63] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 6123 for (i = 64; i < 73; i++) { 6124 if (i%2 == 0) { 6125 iarb_tdm_tbl_lr_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 6126 iarb_tdm_tbl_lr_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 6127 } else { 6128 iarb_tdm_tbl_lr_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 6129 iarb_tdm_tbl_lr_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 6130 } 6131 } 6132 iarb_tdm_tbl_lr_x[73] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 6133 iarb_tdm_tbl_lr_y[73] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 6134 iarb_tdm_tbl_lr_x[74] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 6135 iarb_tdm_tbl_lr_y[74] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 6136 for (i = 75; i < 83; i++) { 6137 if (i%2 == 0) { 6138 iarb_tdm_tbl_lr_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 6139 iarb_tdm_tbl_lr_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 6140 } else { 6141 iarb_tdm_tbl_lr_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 6142 iarb_tdm_tbl_lr_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 6143 } 6144 } 6145 iarb_tdm_tbl_lr_x[83] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 6146 iarb_tdm_tbl_lr_y[83] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 6147 iarb_tdm_tbl_lr_x[84] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 6148 iarb_tdm_tbl_lr_y[84] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 6149 for (i = 85; i < 94; i++) { 6150 if (i%2 == 0) { 6151 iarb_tdm_tbl_lr_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 6152 iarb_tdm_tbl_lr_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 6153 } else { 6154 iarb_tdm_tbl_lr_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 6155 iarb_tdm_tbl_lr_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 6156 } 6157 } 6158 iarb_tdm_tbl_lr_x[94] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 6159 iarb_tdm_tbl_lr_y[94] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 6160 for (i = 95; i < 105; i++) { 6161 if (i%2 == 0) { 6162 iarb_tdm_tbl_lr_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 6163 iarb_tdm_tbl_lr_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_1; 6164 } else { 6165 iarb_tdm_tbl_lr_x[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 6166 iarb_tdm_tbl_lr_y[i] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_PGW_0; 6167 } 6168 } 6169 iarb_tdm_tbl_lr_x[105] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 6170 iarb_tdm_tbl_lr_y[105] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 6171 6172 /* Then check for management ports. */ 6173 if (mgm4x1) { 6174 iarb_tdm_tbl_lr_x[10] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 6175 iarb_tdm_tbl_lr_x[21] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 6176 iarb_tdm_tbl_lr_x[30] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 6177 iarb_tdm_tbl_lr_x[41] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 6178 } else if (mgm4x2p5 || mgm1x10) { 6179 iarb_tdm_tbl_lr_x[10] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 6180 iarb_tdm_tbl_lr_x[21] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 6181 iarb_tdm_tbl_lr_x[30] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 6182 iarb_tdm_tbl_lr_x[41] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 6183 iarb_tdm_tbl_lr_x[52] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 6184 iarb_tdm_tbl_lr_x[63] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 6185 iarb_tdm_tbl_lr_x[74] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 6186 iarb_tdm_tbl_lr_x[83] = TDM_TD2_IARB_MAIN_TDM__TDM_SLOT_QGP_PORT; 6187 } 6188 break; 6189 } 6190 } 6191 6192 6193 /** 6194 @name: tdm_td2_set_iarb_tdm_table 6195 @param: int, int, int, int, int, int, int*, int*, int[512], int[512] 6196 6197 IARB TDM Schedule Generator: 6198 Return => 1 if error, 0 otherwise. 6199 Input 1 => Core bandwidth - 960/720/640/480. 6200 Input 2 => 1 if X-pipe is oversub, 0 otherwise. 6201 Input 3 => 1 if Y-pipe is oversub, 0 otherwise. 6202 Input 4 => 1 if there are 4x1G management ports, 0 otherwise. 6203 Input 5 => 1 if there are 4x2.5G management ports, 0 otherwise. 6204 Input 6 => 1 if there are 1x10G management port, 0 otherwise. 6205 Output 7 => The X-pipe TDM table wrap pointer value. 6206 Output 8 => The Y-pipe TDM table wrap pointer value. 6207 Output 9 => The X-pipe TDM schedule. 6208 Output 10 => The Y-pipe TDM schedule. 6209 */ 6210 int tdm_td2_set_iarb_tdm_table ( 6211 int core_bw, 6212 int is_x_ovs, 6213 int is_y_ovs, 6214 int mgm4x1, 6215 int mgm4x2p5, 6216 int mgm1x10, 6217 int *iarb_tdm_wrap_ptr_x, 6218 int *iarb_tdm_wrap_ptr_y, 6219 int iarb_tdm_tbl_x[512], 6220 int iarb_tdm_tbl_y[512] 6221 ) { 6222 6223 int i; 6224 int is_succ; 6225 int iarb_tdm_wrap_ptr_ovs_x = 0, iarb_tdm_wrap_ptr_ovs_y = 0; 6226 int iarb_tdm_wrap_ptr_lr_x = 0, iarb_tdm_wrap_ptr_lr_y = 0; 6227 TDM_TD2_ALLOC(iarb_tdm_tbl_ovs_x, int, 512, "iarb_tdm_tbl_ovs_x"); 6228 TDM_TD2_ALLOC(iarb_tdm_tbl_ovs_y, int, 512, "iarb_tdm_tbl_ovs_y"); 6229 TDM_TD2_ALLOC(iarb_tdm_tbl_lr_x, int, 512, "iarb_tdm_tbl_lr_x"); 6230 TDM_TD2_ALLOC(iarb_tdm_tbl_lr_y, int, 512, "iarb_tdm_tbl_lr_y"); 6231 6232 /* 6233 Initial IARB TDM table containers - to be copied into final container based 6234 on the TDM selected. 6235 */ 6236 if (!(!mgm4x1 && !mgm4x2p5 && !mgm1x10) && !(mgm4x1 ^ mgm4x2p5 ^ mgm1x10)) { 6237 LOG_ERROR(BSL_LS_SOC_TDM, 6238 (BSL_META("IARB TDM: _____ERROR: Multiple management port settings specified!\n"))); 6239 } 6240 6241 tdm_td2_init_iarb_tdm_ovs_table(core_bw, mgm4x1, mgm4x2p5, mgm1x10, 6242 &iarb_tdm_wrap_ptr_ovs_x, &iarb_tdm_wrap_ptr_ovs_y, 6243 iarb_tdm_tbl_ovs_x, iarb_tdm_tbl_ovs_y); 6244 tdm_td2_init_iarb_tdm_lr_table(core_bw, mgm4x1, mgm4x2p5, mgm1x10, 6245 &iarb_tdm_wrap_ptr_lr_x, &iarb_tdm_wrap_ptr_lr_y, 6246 iarb_tdm_tbl_lr_x, iarb_tdm_tbl_lr_y); 6247 6248 if ((is_x_ovs == 0) && (is_y_ovs == 0)) { 6249 /* The following TDMs have linerate X-pipe and linerate Y-pipe. */ 6250 *iarb_tdm_wrap_ptr_x = iarb_tdm_wrap_ptr_lr_x; 6251 *iarb_tdm_wrap_ptr_y = iarb_tdm_wrap_ptr_lr_y; 6252 sal_memcpy(iarb_tdm_tbl_x, iarb_tdm_tbl_lr_x, sizeof(int) * 512); 6253 sal_memcpy(iarb_tdm_tbl_y, iarb_tdm_tbl_lr_y, sizeof(int) * 512); 6254 } 6255 if ((is_x_ovs == 0) && (is_y_ovs == 1)) { 6256 /* The following TDMs have linerate X-pipe and oversubscribed Y-pipe. */ 6257 *iarb_tdm_wrap_ptr_x = iarb_tdm_wrap_ptr_lr_x; 6258 *iarb_tdm_wrap_ptr_y = iarb_tdm_wrap_ptr_ovs_y; 6259 sal_memcpy(iarb_tdm_tbl_x, iarb_tdm_tbl_lr_x, sizeof(int) * 512); 6260 sal_memcpy(iarb_tdm_tbl_y, iarb_tdm_tbl_ovs_y, sizeof(int) * 512); 6261 } 6262 if ((is_x_ovs == 1) && (is_y_ovs == 0)) { 6263 /* The following TDMs have oversubscribed X-pipe and linerate Y-pipe. */ 6264 *iarb_tdm_wrap_ptr_x = iarb_tdm_wrap_ptr_ovs_x; 6265 *iarb_tdm_wrap_ptr_y = iarb_tdm_wrap_ptr_lr_y; 6266 sal_memcpy(iarb_tdm_tbl_x, iarb_tdm_tbl_ovs_x, sizeof(int) * 512); 6267 sal_memcpy(iarb_tdm_tbl_y, iarb_tdm_tbl_lr_y, sizeof(int) * 512); 6268 } 6269 if ((is_x_ovs == 1) && (is_y_ovs == 1)) { 6270 /* The following TDMs have oversubscribed X-pipe and oversubscribed Y-pipe. */ 6271 *iarb_tdm_wrap_ptr_x = iarb_tdm_wrap_ptr_ovs_x; 6272 *iarb_tdm_wrap_ptr_y = iarb_tdm_wrap_ptr_ovs_y; 6273 sal_memcpy(iarb_tdm_tbl_x, iarb_tdm_tbl_ovs_x, sizeof(int) * 512); 6274 sal_memcpy(iarb_tdm_tbl_y, iarb_tdm_tbl_ovs_y, sizeof(int) * 512); 6275 } 6276 6277 LOG_VERBOSE(BSL_LS_SOC_TDM, 6278 (BSL_META("IARB TDM: _____DEBUG: iarb_tdm_wrap_ptr_x = %d\n"),*iarb_tdm_wrap_ptr_x)); 6279 for (i = 0; i <= *iarb_tdm_wrap_ptr_x; i++) { 6280 LOG_VERBOSE(BSL_LS_SOC_TDM, 6281 (BSL_META("IARB TDM: _____DEBUG: iarb_tdm_tbl_x[%d] = %d\n"),i,iarb_tdm_tbl_x[i])); 6282 } 6283 LOG_VERBOSE(BSL_LS_SOC_TDM, 6284 (BSL_META("IARB TDM: _____DEBUG: iarb_tdm_wrap_ptr_y = %d\n"),*iarb_tdm_wrap_ptr_y)); 6285 for (i = 0; i <= *iarb_tdm_wrap_ptr_y; i++) { 6286 LOG_VERBOSE(BSL_LS_SOC_TDM, 6287 (BSL_META("IARB TDM: _____DEBUG: iarb_tdm_tbl_y[%d] = %d\n"),i,iarb_tdm_tbl_y[i])); 6288 } 6289 6290 /* Always succeeds by definition. */ 6291 is_succ = 1; 6292 TDM_TD2_FREE(iarb_tdm_tbl_ovs_x); 6293 TDM_TD2_FREE(iarb_tdm_tbl_ovs_y); 6294 TDM_TD2_FREE(iarb_tdm_tbl_lr_x); 6295 TDM_TD2_FREE(iarb_tdm_tbl_lr_y); 6296 return is_succ; 6297 }