set_tdm.c (15714B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * All Rights Reserved.$ 7 * 8 * File: set_tdm.c 9 * Purpose: TDM algorithm 10 */ 11 #ifdef _TDM_STANDALONE 12 #include <tdm_top.h> 13 #include <sdk_drv.h> 14 #else 15 #include <soc/tdm/core/tdm_top.h> 16 #include <soc/drv.h> 17 #endif 18 19 size_t stack_size = 0; 20 21 #ifndef _TDM_STANDALONE 22 23 24 /* Trident2plus */ 25 tdm_mod_t 26 * tdm_drv_trident2plus(tdm_mod_t *_tdm) 27 { 28 #if ( defined(BCM_TRIDENT2PLUS_SUPPORT) || defined(BCM_TRIDENT2_SUPPORT) ) 29 int (*core_exec[TDM_EXEC_CORE_SIZE])( tdm_mod_t* ) = { 30 &tdm_core_init, 31 &tdm_core_post, 32 &tdm_td2p_proc_cal, 33 &tdm_core_vbs_scheduler_wrapper, 34 &tdm_core_vbs_scheduler_ovs, 35 &tdm_core_null, 36 &tdm_core_null, 37 &tdm_core_acc_alloc, 38 &tdm_core_vmap_prealloc, 39 &tdm_core_vmap_alloc, 40 &tdm_core_null, 41 &tdm_core_null, 42 &tdm_core_null, 43 &tdm_td2p_check_ethernet, 44 &tdm_pick_vec, 45 &tdm_td2p_which_tsc 46 }; 47 int (*chip_exec[TDM_EXEC_CHIP_SIZE])( tdm_mod_t* ) = { 48 &tdm_td2p_init, 49 &tdm_td2p_pmap_transcription, 50 &tdm_td2p_lls_wrapper, 51 &tdm_td2p_vbs_wrapper, 52 &tdm_td2p_filter, 53 &tdm_td2p_parse_mmu_tdm_tbl, 54 &tdm_core_null, 55 &tdm_core_null, 56 &tdm_core_null, 57 &tdm_core_null, 58 &tdm_core_null, 59 &tdm_core_null, 60 &tdm_td2p_chk, 61 &tdm_td2p_free, 62 &tdm_td2p_corereq, 63 &tdm_td2p_post 64 }; 65 TDM_COPY(_tdm->_core_exec,core_exec,sizeof(_tdm->_core_exec)); 66 TDM_COPY(_tdm->_chip_exec,chip_exec,sizeof(_tdm->_chip_exec)); 67 #endif 68 return _tdm; 69 } 70 71 /* Trident3 */ 72 tdm_mod_t 73 * tdm_drv_trident3(tdm_mod_t *_tdm) 74 { 75 #ifdef BCM_TRIDENT3_SUPPORT 76 int (*core_exec[TDM_EXEC_CORE_SIZE])( tdm_mod_t* ) = { 77 &tdm_core_init, 78 &tdm_core_post, 79 &tdm_td3_proc_cal, 80 &tdm_core_vbs_scheduler_wrapper, 81 &tdm_core_null, 82 &tdm_core_null, 83 &tdm_core_null, 84 &tdm_core_null, 85 &tdm_core_vmap_prealloc, 86 &tdm_core_vmap_alloc, 87 &tdm_core_null, 88 &tdm_core_null, 89 &tdm_core_null, 90 &tdm_td3_shim_get_pipe_ethernet, 91 &tdm_core_null, 92 &tdm_td3_shim_get_port_pm, 93 }; 94 int (*chip_exec[TDM_EXEC_CHIP_SIZE])( tdm_mod_t* ) = { 95 &tdm_td3_main_init, 96 &tdm_td3_main_transcription, 97 &tdm_td3_main_ingress, 98 &tdm_core_null, 99 &tdm_td3_filter, 100 &tdm_td3_parse_tdm_tbl, 101 &tdm_core_null, 102 &tdm_core_null, 103 &tdm_core_null, 104 &tdm_core_null, 105 &tdm_core_null, 106 &tdm_core_null, 107 &tdm_td3_chk, 108 &tdm_td3_main_free, 109 &tdm_td3_main_corereq, 110 &tdm_td3_main_post 111 }; 112 TDM_COPY(_tdm->_core_exec,core_exec,sizeof(_tdm->_core_exec)); 113 TDM_COPY(_tdm->_chip_exec,chip_exec,sizeof(_tdm->_chip_exec)); 114 #endif 115 return _tdm; 116 } 117 118 /* Tomahawk */ 119 tdm_mod_t 120 * tdm_drv_tomahawk(tdm_mod_t *_tdm) 121 { 122 #ifdef BCM_TOMAHAWK_SUPPORT 123 int (*core_exec[TDM_EXEC_CORE_SIZE])( tdm_mod_t* ) = { 124 &tdm_core_init, 125 &tdm_core_post, 126 &tdm_th_proc_cal, 127 &tdm_core_vbs_scheduler_wrapper, 128 &tdm_core_vbs_scheduler_ovs, 129 &tdm_core_null, 130 &tdm_core_null, 131 &tdm_core_acc_alloc, 132 &tdm_core_vmap_prealloc, 133 &tdm_core_vmap_alloc, 134 &tdm_core_null, 135 &tdm_core_null, 136 &tdm_core_null, 137 &tdm_th_check_ethernet, 138 &tdm_pick_vec, 139 &tdm_th_which_tsc 140 }; 141 int (*chip_exec[TDM_EXEC_CHIP_SIZE])( tdm_mod_t* ) = { 142 &tdm_th_init, 143 &tdm_th_pmap_transcription, 144 &tdm_th_scheduler_wrap, 145 &tdm_core_null, 146 &tdm_th_filter, 147 &tdm_th_parse_tdm_tbl, 148 &tdm_core_null, 149 &tdm_core_null, 150 &tdm_core_null, 151 &tdm_core_null, 152 &tdm_core_null, 153 &tdm_core_null, 154 &tdm_th_chk, 155 &tdm_th_free, 156 &tdm_th_corereq, 157 &tdm_th_post 158 }; 159 TDM_COPY(_tdm->_core_exec,core_exec,sizeof(_tdm->_core_exec)); 160 TDM_COPY(_tdm->_chip_exec,chip_exec,sizeof(_tdm->_chip_exec)); 161 #endif 162 return _tdm; 163 } 164 165 /* Tomahawk2 */ 166 tdm_mod_t 167 * tdm_drv_tomahawk2(tdm_mod_t *_tdm) 168 { 169 #ifdef BCM_TOMAHAWK2_SUPPORT 170 int (*core_exec[TDM_EXEC_CORE_SIZE])( tdm_mod_t* ) = { 171 &tdm_core_init, 172 &tdm_core_post, 173 &tdm_th2_vmap_alloc, 174 &tdm_th2_vbs_scheduler, 175 &tdm_chip_th2_shim__core_vbs_scheduler_ovs, 176 &tdm_core_null, 177 &tdm_core_null, 178 &tdm_core_null, 179 &tdm_core_null, 180 &tdm_core_null, 181 &tdm_core_null, 182 &tdm_core_null, 183 &tdm_core_null, 184 &tdm_th2_check_ethernet, 185 &tdm_pick_vec, 186 &tdm_th2_which_tsc 187 }; 188 int (*chip_exec[TDM_EXEC_CHIP_SIZE])( tdm_mod_t* ) = { 189 &tdm_th2_init, 190 &tdm_th2_pmap_transcription, 191 &tdm_th2_scheduler_wrap, 192 &tdm_core_null, 193 &tdm_th2_filter_chain, 194 &tdm_th2_parse_tdm_tbl_new, 195 &tdm_core_null, 196 &tdm_core_null, 197 &tdm_core_null, 198 &tdm_core_null, 199 &tdm_core_null, 200 &tdm_core_null, 201 &tdm_core_null, 202 &tdm_th2_acc_alloc, 203 &tdm_th2_corereq, 204 &tdm_th2_post 205 }; 206 TDM_COPY(_tdm->_core_exec,core_exec,sizeof(_tdm->_core_exec)); 207 TDM_COPY(_tdm->_chip_exec,chip_exec,sizeof(_tdm->_chip_exec)); 208 #endif 209 return _tdm; 210 } 211 212 /* Apache */ 213 tdm_mod_t 214 * tdm_drv_apache(tdm_mod_t *_tdm) 215 { 216 #ifdef BCM_APACHE_SUPPORT 217 int (*core_exec[TDM_EXEC_CORE_SIZE])( tdm_mod_t* ) = { 218 &tdm_core_init, 219 &tdm_core_post, 220 &tdm_ap_vmap_alloc, 221 &tdm_core_vbs_scheduler, 222 &tdm_chip_ap_shim__core_vbs_scheduler_ovs, 223 &tdm_core_null, 224 &tdm_core_null, 225 &tdm_core_null, 226 &tdm_core_null, 227 &tdm_core_null, 228 &tdm_core_null, 229 &tdm_core_null, 230 &tdm_core_null, 231 &tdm_ap_check_ethernet, 232 &tdm_pick_vec, 233 &tdm_ap_which_tsc 234 }; 235 int (*chip_exec[TDM_EXEC_CHIP_SIZE])( tdm_mod_t* ) = { 236 &tdm_ap_init, 237 &tdm_ap_pmap_transcription, 238 &tdm_ap_lls_wrapper, 239 &tdm_ap_vbs_wrapper, 240 &tdm_ap_filter_chain, 241 &tdm_ap_parse_mmu_tdm_tbl, 242 &tdm_core_null, 243 &tdm_core_null, 244 &tdm_core_null, 245 &tdm_core_null, 246 &tdm_core_null, 247 &tdm_core_null, 248 &tdm_ap_chk, 249 &tdm_ap_free, 250 &tdm_ap_corereq, 251 &tdm_ap_post 252 }; 253 TDM_COPY(_tdm->_core_exec,core_exec,sizeof(_tdm->_core_exec)); 254 TDM_COPY(_tdm->_chip_exec,chip_exec,sizeof(_tdm->_chip_exec)); 255 #endif 256 return _tdm; 257 } 258 259 /* Greyhound2 */ 260 tdm_mod_t * 261 tdm_drv_greyhound2(tdm_mod_t *_tdm) 262 { 263 #ifdef BCM_GREYHOUND2_SUPPORT 264 int (*core_exec[TDM_EXEC_CORE_SIZE])( tdm_mod_t* ) = { 265 &tdm_core_init, 266 &tdm_core_post, 267 &tdm_gh2_proc_cal, 268 &tdm_core_vbs_scheduler_wrapper, 269 &tdm_core_ovsb_alloc, 270 &tdm_core_null, 271 &tdm_core_null, 272 &tdm_core_acc_alloc, 273 &tdm_core_vmap_prealloc, 274 &tdm_core_vmap_alloc, 275 &tdm_core_null, 276 &tdm_core_null, 277 &tdm_core_null, 278 &tdm_gh2_check_ethernet, 279 &tdm_pick_vec, 280 &tdm_gh2_which_tsc 281 }; 282 int (*chip_exec[TDM_EXEC_CHIP_SIZE])( tdm_mod_t* ) = { 283 &tdm_gh2_init, 284 &tdm_gh2_pmap_transcription, 285 &tdm_gh2_scheduler_wrap, 286 &tdm_core_null, 287 &tdm_gh2_filter_mix, 288 &tdm_gh2_parse_tdm_tbl, 289 &tdm_core_null, 290 &tdm_core_null, 291 &tdm_core_null, 292 &tdm_core_null, 293 &tdm_core_null, 294 &tdm_core_null, 295 &tdm_gh2_chk, 296 &tdm_gh2_free, 297 &tdm_gh2_corereq, 298 &tdm_gh2_post 299 }; 300 TDM_COPY(_tdm->_core_exec,core_exec,sizeof(_tdm->_core_exec)); 301 TDM_COPY(_tdm->_chip_exec,chip_exec,sizeof(_tdm->_chip_exec)); 302 #endif 303 return _tdm; 304 } 305 /* Maverick2 */ 306 tdm_mod_t 307 * tdm_drv_maverick2(tdm_mod_t *_tdm) 308 { 309 #ifdef BCM_MAVERICK2_SUPPORT 310 int (*core_exec[TDM_EXEC_CORE_SIZE])( tdm_mod_t* ) = { 311 &tdm_core_init, 312 &tdm_core_post, 313 &tdm_mv2_proc_cal, 314 &tdm_core_vbs_scheduler_wrapper, 315 &tdm_mv2_shim_core_vbs_scheduler_ovs, 316 &tdm_core_null, 317 &tdm_core_null, 318 &tdm_core_acc_alloc, 319 &tdm_core_vmap_prealloc, 320 &tdm_core_vmap_alloc_mix, 321 &tdm_core_null, 322 &tdm_core_null, 323 &tdm_core_null, 324 &tdm_mv2_shim_get_pipe_ethernet, 325 &tdm_pick_vec, 326 &tdm_mv2_shim_get_port_pm, 327 }; 328 int (*chip_exec[TDM_EXEC_CHIP_SIZE])( tdm_mod_t* ) = { 329 &tdm_mv2_main_init, 330 &tdm_mv2_main_transcription, 331 &tdm_mv2_main_ingress, 332 &tdm_core_null, 333 &tdm_mv2_filter, 334 &tdm_mv2_parse_tdm_tbl, 335 &tdm_core_null, 336 &tdm_core_null, 337 &tdm_core_null, 338 &tdm_core_null, 339 &tdm_core_null, 340 &tdm_core_null, 341 &tdm_mv2_chk, 342 &tdm_mv2_main_free, 343 &tdm_mv2_main_corereq, 344 &tdm_mv2_main_post 345 }; 346 TDM_COPY(_tdm->_core_exec,core_exec,sizeof(_tdm->_core_exec)); 347 TDM_COPY(_tdm->_chip_exec,chip_exec,sizeof(_tdm->_chip_exec)); 348 #endif 349 return _tdm; 350 } 351 352 /* Helix5 */ 353 tdm_mod_t 354 * tdm_drv_helix5(tdm_mod_t *_tdm) 355 { 356 #ifdef BCM_HELIX5_SUPPORT 357 int (*core_exec[TDM_EXEC_CORE_SIZE])( tdm_mod_t* ) = { 358 &tdm_core_init, 359 &tdm_core_post, 360 &tdm_hx5_proc_cal, 361 &tdm_core_vbs_scheduler_wrapper, 362 &tdm_hx5_shim_core_vbs_scheduler_ovs, 363 &tdm_core_null, 364 &tdm_core_null, 365 &tdm_core_acc_alloc, 366 &tdm_hx5_core_vmap_prealloc, 367 &tdm_hx5_core_vmap_alloc_mix, 368 &tdm_core_null, 369 &tdm_core_null, 370 &tdm_core_null, 371 &tdm_hx5_shim_get_pipe_ethernet, 372 &tdm_pick_vec, 373 &tdm_hx5_shim_get_port_pm, 374 }; 375 int (*chip_exec[TDM_EXEC_CHIP_SIZE])( tdm_mod_t* ) = { 376 &tdm_hx5_main_init, 377 &tdm_hx5_main_transcription, 378 &tdm_hx5_main_ingress, 379 &tdm_core_null, 380 &tdm_hx5_filter, 381 &tdm_hx5_parse_tdm_tbl, 382 &tdm_core_null, 383 &tdm_core_null, 384 &tdm_core_null, 385 &tdm_core_null, 386 &tdm_core_null, 387 &tdm_core_null, 388 &tdm_hx5_chk, 389 &tdm_hx5_main_free, 390 &tdm_hx5_main_corereq, 391 &tdm_hx5_main_post 392 }; 393 TDM_COPY(_tdm->_core_exec,core_exec,sizeof(_tdm->_core_exec)); 394 TDM_COPY(_tdm->_chip_exec,chip_exec,sizeof(_tdm->_chip_exec)); 395 #endif 396 return _tdm; 397 } 398 399 /* Initialize TDM internal driving functions */ 400 tdm_mod_t 401 *SOC_SEL_TDM(tdm_soc_t *chip) 402 { 403 tdm_mod_t *_tdm; 404 uint16 dev_id; 405 uint16 drv_dev_id; 406 uint8 rev_id; 407 uint8 drv_rev_id; 408 409 _tdm = TDM_ALLOC(sizeof(tdm_mod_t),"TDM constructor allocation"); 410 if (!_tdm) { 411 return NULL; 412 } 413 TDM_MEMSET(_tdm, 0, sizeof(tdm_mod_t)); 414 _tdm->_chip_data.soc_pkg = (*chip); 415 416 soc_cm_get_id( _tdm->_chip_data.soc_pkg.unit, &dev_id, &rev_id ); 417 soc_cm_get_id_driver( dev_id, rev_id, &drv_dev_id, &drv_rev_id ); 418 419 420 /* Handling for HX5 SKUs which also have have different Ids from the 421 base variant */ 422 switch(drv_dev_id) { 423 case BCM56370_DEVICE_ID: 424 _tdm = tdm_drv_helix5(_tdm); 425 return _tdm; 426 } 427 428 switch (dev_id&0xfff0) { 429 /* Trident2plus */ 430 case (BCM56850_DEVICE_ID&0xfff0): 431 case (BCM56860_DEVICE_ID&0xfff0): 432 case (BCM56830_DEVICE_ID&0xfff0): 433 _tdm = tdm_drv_trident2plus(_tdm); 434 break; 435 /* Trident3/Maverick2 */ 436 case (BCM56870_DEVICE_ID&0xfff0): 437 _tdm = tdm_drv_trident3(_tdm); 438 break; 439 /* Maverick2 */ 440 case (BCM56770_DEVICE_ID & 0xfff0): 441 _tdm = tdm_drv_maverick2(_tdm); 442 break; 443 /* Tomahawk */ 444 case (BCM56960_DEVICE_ID&0xfff0): 445 case BCM56930_DEVICE_ID: 446 case (BCM56168_DEVICE_ID&0xfff0): 447 _tdm = tdm_drv_tomahawk(_tdm); 448 break; 449 /* Tomahawk2 */ 450 case (BCM56970_DEVICE_ID&0xfff0): 451 _tdm = tdm_drv_tomahawk2(_tdm); 452 break; 453 /* Apache */ 454 case (BCM56560_DEVICE_ID&0xfff0): 455 case (BCM56760_DEVICE_ID&0xfff0): 456 case (BCM56069_DEVICE_ID&0xfff0): 457 _tdm = tdm_drv_apache(_tdm); 458 break; 459 /* Greyhound2 */ 460 case (BCM56170_DEVICE_ID&0xfff0): 461 case (BCM53570_DEVICE_ID&0xfff0): 462 _tdm = tdm_drv_greyhound2(_tdm); 463 break; 464 465 case (BCM56670_DEVICE_ID&0xfff0): 466 { 467 #ifdef BCM_MONTEREY_SUPPORT 468 int (*core_exec[TDM_EXEC_CORE_SIZE])( tdm_mod_t* ) = { 469 &tdm_core_init, 470 &tdm_core_post, 471 &tdm_mn_proc_cal, 472 &tdm_core_vbs_scheduler_wrapper, 473 &tdm_core_vbs_scheduler_ovs, 474 &tdm_core_null, /* TDM_CORE_EXEC__EXTRACT */ 475 &tdm_core_null, /* TDM_CORE_EXEC__FILTER */ 476 &tdm_core_acc_alloc, 477 &tdm_core_vmap_prealloc, 478 &tdm_core_vmap_alloc, 479 &tdm_core_null, 480 &tdm_core_null, 481 &tdm_core_null, 482 &tdm_mn_check_ethernet, 483 &tdm_pick_vec, 484 &tdm_mn_which_tsc 485 }; 486 int (*chip_exec[TDM_EXEC_CHIP_SIZE])( tdm_mod_t* ) = { 487 &tdm_mn_init, 488 &tdm_mn_pmap_transcription, 489 &tdm_mn_lls_wrapper, 490 &tdm_mn_vbs_wrapper, 491 &tdm_mn_filter_chain, 492 &tdm_mn_parse_mmu_tdm_tbl, 493 &tdm_mn_proc_cal_ancl, 494 &tdm_core_null, 495 &tdm_core_null, 496 &tdm_core_null, 497 &tdm_core_null, 498 &tdm_core_null, 499 &chk_tdm_mn_tbl, 500 &tdm_mn_free, 501 &tdm_mn_corereq, 502 &tdm_mn_post 503 }; 504 TDM_COPY(_tdm->_core_exec,core_exec,sizeof(_tdm->_core_exec)); 505 TDM_COPY(_tdm->_chip_exec,chip_exec,sizeof(_tdm->_chip_exec)); 506 #endif 507 508 } 509 break; 510 /* Helix5 */ 511 case (BCM56370_DEVICE_ID&0xfff0): 512 _tdm = tdm_drv_helix5(_tdm); 513 break; 514 default: 515 TDM_FREE(_tdm); 516 TDM_ERROR1("Unrecognized device ID %0x for TDM scheduling algorithm.\n",dev_id); 517 return NULL; 518 } 519 520 return _tdm; 521 } 522 #endif 523 524 525 tdm_mod_t 526 *_soc_set_tdm_tbl( tdm_mod_t *_tdm ) 527 { 528 int index, tdm_ver_chk[8]; 529 530 /* stack_size = (size_t)&index; */ 531 532 if (!_tdm) { 533 return NULL; 534 } 535 TDM_BIG_BAR 536 TDM_PRINT0("TDM: Release version: "); 537 _soc_tdm_ver(tdm_ver_chk); 538 TDM_PRINT2("%d%d",tdm_ver_chk[0],tdm_ver_chk[1]); 539 for (index=2; index<8; index+=2) { 540 TDM_PRINT2(".%d%d",tdm_ver_chk[index],tdm_ver_chk[index+1]); 541 } 542 TDM_PRINT0("\n"); TDM_SML_BAR 543 544 /* Path virtualized API starting in chip executive */ 545 return ((_tdm->_chip_exec[TDM_CHIP_EXEC__INIT](_tdm))==PASS)?(_tdm):(NULL); 546 }