tdm_mn_shim.c (11300B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * $All Rights Reserved.$ 7 * 8 * TDM chip to core API shim layer 9 */ 10 #ifdef _TDM_STANDALONE 11 #include <tdm_top.h> 12 #include <tdmv.h> 13 #else 14 #include <soc/tdm/core/tdm_top.h> 15 #endif 16 extern int mn_is_clport(int pnum); 17 18 /** 19 @name: tdm_chip_mn_shim_core 20 @param: 21 22 Downward abstraction layer between TDM.4 and TDM.5 API core data 23 */ 24 int 25 tdm_chip_mn_shim_core( tdm_mod_t *_tdm, tdm_mn_chip_legacy_t *_tdm_mn) 26 { 27 int idx1, idx2; 28 29 if (_tdm==NULL || _tdm_mn==NULL) {return FAIL;} 30 31 /* port map */ 32 for (idx1=0; idx1<MN_NUM_PHY_PM; idx1++) { 33 for (idx2=0; idx2<MN_NUM_PM_LNS; idx2++) { 34 _tdm_mn->pmap[idx1][idx2] = _tdm->_chip_data.soc_pkg.pmap[idx1][idx2]; 35 } 36 } 37 /* speed */ 38 for (idx1=0; idx1<(MN_NUM_EXT_PORTS-64); idx1++) { 39 _tdm_mn->tdm_globals.speed[idx1] = _tdm->_chip_data.soc_pkg.speed[idx1]; 40 } 41 /* freq */ 42 _tdm_mn->tdm_globals.clk_freq = _tdm->_chip_data.soc_pkg.clk_freq; 43 /* state : Realign port state array to old specification */ 44 for (idx1=0; idx1<(MN_NUM_EXT_PORTS-64); idx1++) { 45 _tdm_mn->tdm_globals.port_rates_array[idx1] = _tdm->_chip_data.soc_pkg.state[idx1]; 46 } 47 for (idx1=0; idx1<(MN_NUM_EXT_PORTS-65); idx1++) { 48 _tdm_mn->tdm_globals.port_rates_array[idx1] = _tdm_mn->tdm_globals.port_rates_array[idx1+1]; 49 } 50 /* encap_type */ 51 for (idx1=0; idx1<(MN_NUM_EXT_PORTS-64); idx1++) { 52 if (idx1%MN_NUM_PM_LNS==0 && (idx1/MN_NUM_PM_LNS)<MN_NUM_PM_MOD) { 53 _tdm_mn->tdm_globals.pm_encap_type[idx1/MN_NUM_PM_LNS] = (_tdm->_chip_data.soc_pkg.state[idx1]==PORT_STATE__LINERATE_HG||_tdm->_chip_data.soc_pkg.state[idx1]==PORT_STATE__OVERSUB_HG)?(PM_ENCAP__HIGIG2):(PM_ENCAP__ETHRNT); 54 } 55 } 56 /*set : if clport is in 100G or 25G*/ 57 for (idx1=1; idx1<=MN_NUM_PHY_PORTS; idx1+=MN_NUM_PM_LNS) { 58 _tdm_mn->tdm_globals.cl_flag = BOOL_FALSE; 59 if( ( mn_is_clport( idx1) ) && ( _tdm->_chip_data.soc_pkg.speed[idx1]==SPEED_100G || _tdm->_chip_data.soc_pkg.speed[idx1]==SPEED_50G || _tdm->_chip_data.soc_pkg.speed[idx1]==SPEED_25G) ) { 60 _tdm_mn->tdm_globals.cl_flag = BOOL_TRUE; 61 break; 62 } 63 } 64 /*num_1g ports: required for f3_2 TDM*/ 65 _tdm_mn->tdm_globals.num_1g=0; 66 for (idx1=0; idx1<(MN_NUM_EXT_PORTS-64); idx1++) { 67 if(_tdm_mn->tdm_globals.speed[idx1] == SPEED_1G || _tdm_mn->tdm_globals.speed[idx1]==SPEED_2p5G) { _tdm_mn->tdm_globals.num_1g++ ;} 68 } 69 return PASS; 70 } 71 72 73 /** 74 @name: tdm_chip_mn_shim__ing_wrap 75 @param: 76 77 Downward abstraction layer between TDM.4 and TDM.5 API ingress scheduler 78 */ 79 int 80 tdm_chip_mn_shim__ing_wrap( tdm_mod_t *_tdm, tdm_mn_chip_legacy_t *_tdm_mn) 81 { 82 if (FAIL == tdm_chip_mn_shim_core(_tdm, _tdm_mn)) {return FAIL;} 83 84 TDM_MSET(_tdm_mn->tdm_pgw.pgw_tdm_tbl_x0,MN_NUM_EXT_PORTS,MN_LR_LLS_LEN); 85 TDM_MSET(_tdm_mn->tdm_pgw.ovs_tdm_tbl_x0,MN_NUM_EXT_PORTS,MN_OS_LLS_GRP_LEN); 86 TDM_MSET(_tdm_mn->tdm_pgw.ovs_spacing_x0,MN_NUM_EXT_PORTS,MN_OS_LLS_GRP_LEN); 87 TDM_MSET(_tdm_mn->tdm_pgw.pgw_tdm_tbl_x1,MN_NUM_EXT_PORTS,MN_LR_LLS_LEN); 88 TDM_MSET(_tdm_mn->tdm_pgw.ovs_tdm_tbl_x1,MN_NUM_EXT_PORTS,MN_OS_LLS_GRP_LEN); 89 TDM_MSET(_tdm_mn->tdm_pgw.ovs_spacing_x1,MN_NUM_EXT_PORTS,MN_OS_LLS_GRP_LEN); 90 91 TDM_MSET(_tdm_mn->tdm_pipe_table_x.tdm_pipe_main,MN_NUM_EXT_PORTS,MN_LR_VBS_LEN); 92 TDM_MSET(_tdm_mn->tdm_pipe_table_x.tdm_ovs_grp_0,MN_NUM_EXT_PORTS,MN_OS_VBS_GRP_LEN); 93 TDM_MSET(_tdm_mn->tdm_pipe_table_x.tdm_ovs_grp_1,MN_NUM_EXT_PORTS,MN_OS_VBS_GRP_LEN); 94 TDM_MSET(_tdm_mn->tdm_pipe_table_x.tdm_ovs_grp_2,MN_NUM_EXT_PORTS,MN_OS_VBS_GRP_LEN); 95 TDM_MSET(_tdm_mn->tdm_pipe_table_x.tdm_ovs_grp_3,MN_NUM_EXT_PORTS,MN_OS_VBS_GRP_LEN); 96 TDM_MSET(_tdm_mn->tdm_pipe_table_x.tdm_ovs_grp_4,MN_NUM_EXT_PORTS,MN_OS_VBS_GRP_LEN); 97 TDM_MSET(_tdm_mn->tdm_pipe_table_x.tdm_ovs_grp_5,MN_NUM_EXT_PORTS,MN_OS_VBS_GRP_LEN); 98 TDM_MSET(_tdm_mn->tdm_pipe_table_x.tdm_ovs_grp_6,MN_NUM_EXT_PORTS,MN_OS_VBS_GRP_LEN); 99 TDM_MSET(_tdm_mn->tdm_pipe_table_x.tdm_ovs_grp_7,MN_NUM_EXT_PORTS,MN_OS_VBS_GRP_LEN); 100 101 return PASS; 102 103 } 104 105 106 /** 107 @name: tdm_chip_mn_shim__egr_wrap 108 @param: 109 110 Downward abstraction layer between TDM.4 and TDM.5 API egress scheduler 111 */ 112 int 113 tdm_chip_mn_shim__egr_wrap( tdm_mod_t *_tdm, tdm_mn_chip_legacy_t *_tdm_mn ) 114 { 115 if (FAIL == tdm_chip_mn_shim_core(_tdm, _tdm_mn)) {return FAIL;} 116 117 TDM_COPY(_tdm_mn->tdm_pgw.pgw_tdm_tbl_x0,_tdm->_chip_data.cal_0.cal_main,sizeof(int)*MN_LR_LLS_LEN); 118 TDM_COPY(_tdm_mn->tdm_pgw.ovs_tdm_tbl_x0,_tdm->_chip_data.cal_0.cal_grp[0],sizeof(int)*MN_OS_LLS_GRP_LEN); 119 TDM_COPY(_tdm_mn->tdm_pgw.pgw_tdm_tbl_x1,_tdm->_chip_data.cal_1.cal_main,sizeof(int)*MN_LR_LLS_LEN); 120 TDM_COPY(_tdm_mn->tdm_pgw.ovs_tdm_tbl_x1,_tdm->_chip_data.cal_1.cal_grp[0],sizeof(int)*MN_OS_LLS_GRP_LEN); 121 122 TDM_MSET(_tdm_mn->tdm_pipe_table_x.tdm_pipe_main,MN_NUM_EXT_PORTS,MN_LR_VBS_LEN); 123 TDM_MSET(_tdm_mn->tdm_pipe_table_x.tdm_ovs_grp_0,MN_NUM_EXT_PORTS,MN_OS_VBS_GRP_LEN); 124 TDM_MSET(_tdm_mn->tdm_pipe_table_x.tdm_ovs_grp_1,MN_NUM_EXT_PORTS,MN_OS_VBS_GRP_LEN); 125 TDM_MSET(_tdm_mn->tdm_pipe_table_x.tdm_ovs_grp_2,MN_NUM_EXT_PORTS,MN_OS_VBS_GRP_LEN); 126 TDM_MSET(_tdm_mn->tdm_pipe_table_x.tdm_ovs_grp_3,MN_NUM_EXT_PORTS,MN_OS_VBS_GRP_LEN); 127 TDM_MSET(_tdm_mn->tdm_pipe_table_x.tdm_ovs_grp_4,MN_NUM_EXT_PORTS,MN_OS_VBS_GRP_LEN); 128 TDM_MSET(_tdm_mn->tdm_pipe_table_x.tdm_ovs_grp_5,MN_NUM_EXT_PORTS,MN_OS_VBS_GRP_LEN); 129 TDM_MSET(_tdm_mn->tdm_pipe_table_x.tdm_ovs_grp_6,MN_NUM_EXT_PORTS,MN_OS_VBS_GRP_LEN); 130 TDM_MSET(_tdm_mn->tdm_pipe_table_x.tdm_ovs_grp_7,MN_NUM_EXT_PORTS,MN_OS_VBS_GRP_LEN); 131 132 return PASS; 133 134 } 135 136 137 /** 138 @name: tdm_chip_mn_shim__which_tsc_alloc 139 @param: 140 141 Upward abstraction layer between TDM.4 and TDM.5 API 142 Only returns enough of TDM.5 style struct to drive scan functions, do not use as class 143 */ 144 tdm_mod_t* 145 tdm_chip_mn_shim__which_tsc_alloc( int port, int tsc[MN_NUM_PHY_PM][MN_NUM_PM_LNS] ) 146 { 147 int idx1, idx2; 148 tdm_mod_t *_tdm_s; 149 150 _tdm_s = TDM_ALLOC(sizeof(tdm_mod_t),"TDM shim allocation"); 151 if (!_tdm_s) { 152 return NULL; 153 } 154 155 _tdm_s->_chip_data.soc_pkg.num_ext_ports = MN_NUM_EXT_PORTS; 156 _tdm_s->_chip_data.soc_pkg.pmap_num_modules = MN_NUM_PHY_PM; 157 _tdm_s->_chip_data.soc_pkg.pmap_num_lanes = MN_NUM_PM_LNS; 158 _tdm_s->_chip_data.soc_pkg.pmap=(int **) TDM_ALLOC((_tdm_s->_chip_data.soc_pkg.pmap_num_modules)*sizeof(int *), "portmod_map_l1"); 159 for (idx1=0; idx1<(_tdm_s->_chip_data.soc_pkg.pmap_num_modules); idx1++) { 160 _tdm_s->_chip_data.soc_pkg.pmap[idx1]=(int *) TDM_ALLOC((_tdm_s->_chip_data.soc_pkg.pmap_num_lanes)*sizeof(int), "portmod_map_l2"); 161 TDM_MSET(_tdm_s->_chip_data.soc_pkg.pmap[idx1],(_tdm_s->_chip_data.soc_pkg.num_ext_ports),_tdm_s->_chip_data.soc_pkg.pmap_num_lanes); 162 } 163 for (idx1=0; idx1<MN_NUM_PHY_PM; idx1++) { 164 for (idx2=0; idx2<MN_NUM_PM_LNS; idx2++) { 165 _tdm_s->_chip_data.soc_pkg.pmap[idx1][idx2] = tsc[idx1][idx2]; 166 } 167 } 168 /* to get mapping of mngmnt ports*/ 169 for (idx1=0; idx1<MN_NUM_PHY_PM; idx1++) { 170 for (idx2=0; idx2<MN_NUM_PM_LNS; idx2++) { 171 if( ( mn_is_clport( _tdm_s->_chip_data.soc_pkg.pmap[idx1][idx2] ) ) && 172 (idx1 > 4 && (idx1<11)) ) { 173 _tdm_s->_chip_data.soc_pkg.pmap[idx1][idx2] = MN_NUM_EXT_PORTS; 174 } 175 } 176 } 177 178 179 _tdm_s->_core_data.vars_pkg.port = port; 180 181 return _tdm_s; 182 183 } 184 185 /** 186 @name: tdm_chip_mn_shim__which_tsc_free 187 @param: 188 */ 189 int 190 tdm_chip_mn_shim__which_tsc_free(tdm_mod_t *_tdm) 191 { 192 int idx1; 193 tdm_mod_t *_tdm_s=_tdm; 194 /* pmap */ 195 for(idx1=0;idx1<(_tdm_s->_chip_data.soc_pkg.pmap_num_modules); idx1++) { 196 TDM_FREE(_tdm_s->_chip_data.soc_pkg.pmap[idx1]); 197 } 198 TDM_FREE(_tdm_s->_chip_data.soc_pkg.pmap); 199 /* _tdm */ 200 TDM_FREE(_tdm_s); 201 202 return PASS; 203 204 } 205 206 207 /** 208 @name: tdm_chip_mn_shim__check_ethernet 209 @param: 210 211 Upward abstraction layer between TDM.4 and TDM.5 API 212 */ 213 tdm_mod_t* 214 tdm_chip_mn_shim__check_ethernet( int port, enum port_speed_e speed[MN_NUM_EXT_PORTS], int tsc[MN_NUM_PHY_PM][MN_NUM_PM_LNS], int traffic[MN_NUM_PM_MOD] ) 215 { 216 int idx1, idx2; 217 tdm_mod_t *_tdm_s; 218 219 _tdm_s = TDM_ALLOC(sizeof(tdm_mod_t),"TDM shim allocation"); 220 if (!_tdm_s) { 221 return NULL; 222 } 223 224 _tdm_s->_chip_data.soc_pkg.speed=TDM_ALLOC(MN_NUM_EXT_PORTS*sizeof(int *), "port speed list"); 225 for (idx1=0; idx1<MN_NUM_EXT_PORTS; idx1++) { 226 _tdm_s->_chip_data.soc_pkg.speed[idx1] = speed[idx1]; 227 } 228 _tdm_s->_chip_data.soc_pkg.pmap_num_modules = MN_NUM_PHY_PM; 229 _tdm_s->_chip_data.soc_pkg.pmap_num_lanes = MN_NUM_PM_LNS; 230 _tdm_s->_chip_data.soc_pkg.pmap=(int **) TDM_ALLOC((_tdm_s->_chip_data.soc_pkg.pmap_num_modules)*sizeof(int *), "portmod_map_l1"); 231 for (idx1=0; idx1<(_tdm_s->_chip_data.soc_pkg.pmap_num_modules); idx1++) { 232 _tdm_s->_chip_data.soc_pkg.pmap[idx1]=(int *) TDM_ALLOC((_tdm_s->_chip_data.soc_pkg.pmap_num_lanes)*sizeof(int), "portmod_map_l2"); 233 TDM_MSET(_tdm_s->_chip_data.soc_pkg.pmap[idx1],(_tdm_s->_chip_data.soc_pkg.num_ext_ports),_tdm_s->_chip_data.soc_pkg.pmap_num_lanes); 234 } 235 for (idx1=0; idx1<MN_NUM_PHY_PM; idx1++) { 236 for (idx2=0; idx2<MN_NUM_PM_LNS; idx2++) { 237 _tdm_s->_chip_data.soc_pkg.pmap[idx1][idx2] = tsc[idx1][idx2]; 238 } 239 } 240 for (idx1=0; idx1<MN_NUM_PM_MOD; idx1++) { 241 _tdm_s->_chip_data.soc_pkg.soc_vars.mn.pm_encap_type[idx1] = traffic[idx1]; 242 } 243 244 _tdm_s->_core_data.vars_pkg.port = port; 245 return _tdm_s; 246 247 } 248 249 250 /** 251 @name: tdm_chip_mn_shim__check_ethernet 252 @param: 253 254 Upward abstraction layer between TDM.4 and TDM.5 API 255 */ 256 tdm_mod_t* 257 tdm_chip_mn_shim__check_ethernet_d( int port, enum port_speed_e speed[MN_NUM_EXT_PORTS], enum port_state_e state[MN_NUM_EXT_PORTS], int **tsc, int traffic[MN_NUM_PM_MOD] ) 258 { 259 int idx1, idx2; 260 tdm_mod_t *_tdm_s; 261 262 _tdm_s = TDM_ALLOC(sizeof(tdm_mod_t),"TDM shim allocation"); 263 if (!_tdm_s) { 264 return NULL; 265 } 266 267 _tdm_s->_chip_data.soc_pkg.speed=TDM_ALLOC(MN_NUM_EXT_PORTS*sizeof(int *), "port speed list"); 268 _tdm_s->_chip_data.soc_pkg.state=TDM_ALLOC(MN_NUM_EXT_PORTS*sizeof(int *), "port state list"); 269 for (idx1=0; idx1<MN_NUM_EXT_PORTS; idx1++) { 270 _tdm_s->_chip_data.soc_pkg.speed[idx1] = speed[idx1]; 271 _tdm_s->_chip_data.soc_pkg.state[idx1] = state[idx1]; 272 } 273 _tdm_s->_chip_data.soc_pkg.pmap_num_modules = MN_NUM_PHY_PM; 274 _tdm_s->_chip_data.soc_pkg.pmap_num_lanes = MN_NUM_PM_LNS; 275 _tdm_s->_chip_data.soc_pkg.pmap=(int **) TDM_ALLOC((_tdm_s->_chip_data.soc_pkg.pmap_num_modules)*sizeof(int *), "portmod_map_l1"); 276 for (idx1=0; idx1<(_tdm_s->_chip_data.soc_pkg.pmap_num_modules); idx1++) { 277 _tdm_s->_chip_data.soc_pkg.pmap[idx1]=(int *) TDM_ALLOC((_tdm_s->_chip_data.soc_pkg.pmap_num_lanes)*sizeof(int), "portmod_map_l2"); 278 TDM_MSET(_tdm_s->_chip_data.soc_pkg.pmap[idx1],(_tdm_s->_chip_data.soc_pkg.num_ext_ports),_tdm_s->_chip_data.soc_pkg.pmap_num_lanes); 279 } 280 281 for (idx1=0; idx1<MN_NUM_PHY_PM; idx1++) { 282 for (idx2=0; idx2<MN_NUM_PM_LNS; idx2++) { 283 _tdm_s->_chip_data.soc_pkg.pmap[idx1][idx2] = tsc[idx1][idx2]; 284 } 285 } 286 for (idx1=0; idx1<MN_NUM_PM_MOD; idx1++) { 287 _tdm_s->_chip_data.soc_pkg.soc_vars.mn.pm_encap_type[idx1] = traffic[idx1]; 288 } 289 290 _tdm_s->_core_data.vars_pkg.port = port; 291 return _tdm_s; 292 293 } 294 295 296 /** 297 @name: tdm_chip_mn_shim__core_vbs_scheduler_ovs 298 @param: 299 300 Passthru function for oversub scheduling request from TD2/TD2+ 301 */ 302 int 303 tdm_chip_mn_shim__core_vbs_scheduler_ovs( tdm_mod_t *_tdm ) 304 { 305 /* TD2/TD2+ doesn't use 25G and 50G */ 306 /*_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.z5=0; 307 _tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.z6=0;*/ 308 309 return tdm_core_vbs_scheduler_ovs(_tdm); 310 }