tdm_mn_proc.c (108224B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * $All Rights Reserved.$ 7 * 8 * TDM chip operations 9 */ 10 #ifdef _TDM_STANDALONE 11 #include <tdm_top.h> 12 #include <tdmv.h> 13 #include <tdm_mn_vec.h> 14 #else 15 #include <soc/tdm/core/tdm_top.h> 16 #include <soc/tdm/monterey/tdm_mn_vec.h> 17 #endif 18 19 extern void tdm_mn_tdm_print(int *tdm_tbl, int length); 20 extern int chk_tdm_roundup(int m, int n); 21 extern int chk_tdm_rounddown(int m, int n); 22 extern int chk_tdm_round(int m, int n); 23 24 int tdm_core_vec_load(unsigned short **map, int bw, int port_speed, int yy, int len, int num_ext_ports); 25 26 /** 27 @name: tdm_mn_ovs_spacer 28 @param: 29 30 Reconfigures oversub TDM calendar into Flexport compatibility mode 31 */ 32 void 33 tdm_mn_ovs_spacer(int *ovs_tdm_tbl, int *ovs_spacing) 34 { 35 int i, j, w=0, k=0, port=0; 36 int idx=0, size=MN_OS_LLS_GRP_LEN; 37 unsigned short mirror_tdm_tbl[2*MN_OS_LLS_GRP_LEN]; 38 39 for(j=0; j<(2*MN_OS_LLS_GRP_LEN); j++) { mirror_tdm_tbl[j] = MN_NUM_EXT_PORTS;} 40 41 do { 42 idx++; 43 } while(ovs_tdm_tbl[idx] != MN_NUM_EXT_PORTS); 44 size =idx; 45 46 for (i=0; i<size; i++) { 47 mirror_tdm_tbl[i] = ovs_tdm_tbl[i]; 48 mirror_tdm_tbl[i+size] = ovs_tdm_tbl[i]; 49 } 50 /* Populate PGW spacing table by calculating min spacing for each non-empty slots */ 51 for (j=0; j<size; j++) { 52 w=size+1; 53 if(ovs_tdm_tbl[j]!=MN_NUM_EXT_PORTS){ 54 port = ovs_tdm_tbl[j]; 55 for (i=j+1; i<2*size; i++){ 56 if (mirror_tdm_tbl[i]== port){ 57 w=i-j; 58 break; 59 } 60 } 61 ovs_spacing[j] = w; 62 } 63 } 64 /* Regulate spacing values with MN_OS_LLS_GRP_LEN */ 65 for (k=0; k<MN_OS_LLS_GRP_LEN; k++) { 66 if (ovs_spacing[k] == (size+1) || ovs_tdm_tbl[k] == MN_OVSB_TOKEN){ 67 ovs_spacing[k] = size; 68 } 69 } 70 71 } 72 73 /** 74 OVSB TBL RECONFIG WHEN CLPORTS in 100G 75 */ 76 void tdm_mn_reconfig_ovs_tbl(int *ovs_tdm_tbl) 77 { 78 79 int i,j,k,idx,size=MN_OS_LLS_GRP_LEN; 80 int elmnt_repeating,elmnt_repeating_cnt=0, num_elements_repeating=0, rpt_slot0, rpt_slot1, rpt_slot2; 81 int uniq_elements_cnt=0, sum_of_spacing=0, current_spacing=0; 82 int temp, spacing_idx=0, timeout=16, temp_port=130; 83 84 int spacing_tbl[MN_OS_LLS_GRP_LEN],elmnt_repeating_tbl[MN_OS_LLS_GRP_LEN],uniq_elements_tbl[MN_OS_LLS_GRP_LEN]; 85 86 87 for(j=0; j<MN_OS_LLS_GRP_LEN; j++) { spacing_tbl[j] = 0;} 88 89 for(i =0; i<MN_OS_LLS_GRP_LEN; i++) { 90 if(ovs_tdm_tbl[i] == MN_NUM_EXT_PORTS) break; 91 } 92 size = i; 93 94 for(i=0; i<size; i++) { 95 MN_TOKEN_CHECK(ovs_tdm_tbl[i]) { 96 if(ovs_tdm_tbl[i]==ovs_tdm_tbl[i+1]) { 97 elmnt_repeating_tbl[num_elements_repeating++] = ovs_tdm_tbl[i]; 98 elmnt_repeating = ovs_tdm_tbl[i]; 99 for(j=0; j<size; j++) { 100 if(ovs_tdm_tbl[j] == elmnt_repeating_tbl[num_elements_repeating-1]) { 101 for(k=j-1; k>=0; k--){ 102 ovs_tdm_tbl[k+1] = ovs_tdm_tbl[k]; 103 } 104 elmnt_repeating_cnt++; 105 ovs_tdm_tbl[0] = elmnt_repeating; 106 } 107 } 108 i = elmnt_repeating_cnt; 109 } 110 } 111 } 112 113 /* move all ovsb tokens to end */ 114 while((--timeout)>0) { 115 for (i=0; i<(size-1); i++) { 116 if (ovs_tdm_tbl[i]==MN_OVSB_TOKEN && ovs_tdm_tbl[i+1]!=MN_OVSB_TOKEN) { 117 temp_port=ovs_tdm_tbl[i+1]; 118 ovs_tdm_tbl[i+1]=ovs_tdm_tbl[i]; 119 ovs_tdm_tbl[i]=temp_port; 120 } 121 } 122 } 123 for(i=elmnt_repeating_cnt; i<size; i++) { 124 MN_OVS_TOKEN_CHECK(ovs_tdm_tbl[i]) { 125 uniq_elements_tbl[uniq_elements_cnt++] = ovs_tdm_tbl[i]; 126 } 127 } 128 /*if no unique elements*/ 129 if(uniq_elements_cnt ==0 || uniq_elements_tbl[0] ==MN_OVSB_TOKEN) { 130 if(num_elements_repeating == 3) { 131 rpt_slot0=ovs_tdm_tbl[0]; rpt_slot1=ovs_tdm_tbl[10]; rpt_slot2=ovs_tdm_tbl[20]; 132 for(i=0; i<(size-4); i=i+3) { 133 ovs_tdm_tbl[i] = rpt_slot0; 134 ovs_tdm_tbl[i+1] = rpt_slot1; 135 ovs_tdm_tbl[i+2] = rpt_slot2; 136 } 137 } 138 else if (num_elements_repeating ==2) { 139 rpt_slot0=ovs_tdm_tbl[0]; rpt_slot1=ovs_tdm_tbl[10]; 140 for(i=0; i<(size-4); i++) { 141 if(i%2==0) ovs_tdm_tbl[i] = rpt_slot0; 142 else ovs_tdm_tbl[i] = rpt_slot1; 143 } 144 } 145 } 146 else if (elmnt_repeating_cnt!=0) { 147 do { 148 for(i=0; i<elmnt_repeating_cnt/num_elements_repeating; i++) { 149 spacing_tbl[i]++; 150 sum_of_spacing++; 151 if(sum_of_spacing == uniq_elements_cnt) break; 152 } 153 } while (sum_of_spacing < uniq_elements_cnt); 154 /* make the spacing table symmetric*/ 155 do { 156 spacing_idx++; 157 } while(spacing_tbl[spacing_idx] != 0); 158 159 for(i=0; i<spacing_idx; i++) { 160 temp= spacing_tbl[spacing_idx-1]; 161 for(k=spacing_idx-1; k>i; k--) { spacing_tbl[k] = spacing_tbl[k-1];} 162 spacing_tbl[i] = temp; 163 i=i+1; 164 } 165 166 /* put the repeating elements at start of tbl*/ 167 for(k=0, j=0; k<num_elements_repeating; k++) { 168 ovs_tdm_tbl[j++] = elmnt_repeating_tbl[k]; 169 } 170 171 for(i=0, current_spacing=0, idx=0 ; i<uniq_elements_cnt; ) { 172 if(current_spacing==spacing_tbl[idx]) { 173 current_spacing = 0; 174 idx++; 175 for(k=0; k<num_elements_repeating; k++) { 176 ovs_tdm_tbl[j++] = elmnt_repeating_tbl[k]; 177 } 178 } 179 else { ovs_tdm_tbl[j++]=uniq_elements_tbl[i]; current_spacing++; i++; } 180 } 181 } 182 183 184 } 185 186 /** 187 */ 188 void tdm_mn_reconfig_ovs_8x25(int *ovs_tdm_tbl, int port1, int port2) 189 { 190 191 int i, j, idx=0, size=MN_OS_LLS_GRP_LEN; 192 193 do { 194 idx++; 195 } while(ovs_tdm_tbl[idx] != MN_NUM_EXT_PORTS); 196 197 ovs_tdm_tbl[idx] = port1; 198 ovs_tdm_tbl[idx+1] = port1; 199 ovs_tdm_tbl[idx+2] = port2; 200 ovs_tdm_tbl[idx+3] = port2; 201 202 for(i=0; i<MN_OS_LLS_GRP_LEN; i++) { 203 if(ovs_tdm_tbl[i] == MN_NUM_EXT_PORTS) break; 204 } 205 size = i; 206 207 for(i=0;i<size;i++) { 208 for(j=0;j<4;j++) { 209 if(ovs_tdm_tbl[i]==(port1+j)) { 210 ovs_tdm_tbl[i] = port1; 211 } 212 if(ovs_tdm_tbl[i]==(port2+j)) { 213 ovs_tdm_tbl[i] = port2; 214 } 215 } 216 } 217 } 218 219 /** 220 */ 221 void tdm_mn_append_ovs_8x25(int *ovs_tdm_tbl, int port1, int port2, int cxx_port, enum port_speed_e cxx_speed ) 222 { 223 224 int i, cnt=0, cnt1=0, cnt2=0; 225 int token1=port1, token2=port2; 226 227 if(cxx_speed == SPEED_100G) { 228 for (i=0; i<MN_OS_LLS_GRP_LEN; i++) { 229 if( ovs_tdm_tbl[i]>=cxx_port && ovs_tdm_tbl[i] <(cxx_port+10) ) { 230 ovs_tdm_tbl[i] = cxx_port; 231 if((cnt2++)==9) break; 232 } 233 } 234 for (i=0; i<MN_OS_LLS_GRP_LEN; i++) { 235 if( ovs_tdm_tbl[i]>cxx_port && ovs_tdm_tbl[i] <(cxx_port+10) ) { 236 ovs_tdm_tbl[i] = (ovs_tdm_tbl[i] % 2)? port2 : port1; 237 } 238 } 239 } 240 for (i=0; i<MN_OS_LLS_GRP_LEN; i++) { 241 if(ovs_tdm_tbl[i]== port1) { 242 ovs_tdm_tbl[i] = token1++; 243 if((cnt++) ==3) { 244 cnt =0; 245 token1=port1; 246 } 247 } 248 if(ovs_tdm_tbl[i]== port2) { 249 ovs_tdm_tbl[i] = token2++; 250 if((cnt1++) ==3) { 251 cnt1 =0; 252 token2=port2; 253 } 254 } 255 } 256 257 } 258 259 void tdm_mn_clport_ovs_scheduler_32x25(int *ovs_tdm_tbl, int port[5], enum port_speed_e speed[5], int cxx_port, enum port_speed_e cxx_speed, int clk ) 260 { 261 262 int i, j, idx=0, size=MN_OS_LLS_GRP_LEN, k=0,index=0; 263 int elmnt_repeating,elmnt_repeating_cnt=0, num_elements_repeating=0, num_slots_for_25gport=3; 264 int elmnt_repeating_tbl[MN_OS_LLS_GRP_LEN]; 265 266 do { 267 idx++; 268 } while(ovs_tdm_tbl[idx] != MN_NUM_EXT_PORTS); 269 270 for(i=0; i<size; i++) { 271 MN_TOKEN_CHECK(ovs_tdm_tbl[i]) { 272 if(ovs_tdm_tbl[i]==ovs_tdm_tbl[i+1]) { 273 elmnt_repeating_tbl[num_elements_repeating++] = ovs_tdm_tbl[i]; 274 elmnt_repeating = ovs_tdm_tbl[i]; 275 for(j=0; j<size; j++) { 276 if(ovs_tdm_tbl[j] == elmnt_repeating_tbl[num_elements_repeating-1]) { 277 for(k=j-1; k>=0; k--){ 278 ovs_tdm_tbl[k+1] = ovs_tdm_tbl[k]; 279 } 280 elmnt_repeating_cnt++; 281 ovs_tdm_tbl[0] = elmnt_repeating; 282 } 283 } 284 i = elmnt_repeating_cnt; 285 } 286 } 287 } 288 for(i=0; i < num_slots_for_25gport; i++) { 289 for(j=0; j <num_elements_repeating/4; j++) { 290 for(k=0; k<4; k++){ 291 ovs_tdm_tbl[index] = elmnt_repeating_tbl[k]+j; 292 index +=1; 293 } 294 } 295 } 296 } 297 298 299 /* 300 void tdm_mn_scheduler_ovs_4x25(int *ovs_tdm_tbl, int port) 301 { 302 303 int i, j, k,cnt=0,div=0, cnt1=0, size=MN_OS_LLS_GRP_LEN; 304 int uniq_elements_tbl[MN_OS_LLS_GRP_LEN]; 305 int token=port; 306 307 for(j=0; j<MN_OS_LLS_GRP_LEN; j++) { uniq_elements_tbl[j] = MN_NUM_EXT_PORTS;} 308 309 for(i=0; i<MN_OS_LLS_GRP_LEN; i++) { 310 if(ovs_tdm_tbl[i] == MN_NUM_EXT_PORTS) break; 311 } 312 size = i; 313 314 for(i=0,j=0; i<size; i++) { 315 if(ovs_tdm_tbl[i]!=port) { uniq_elements_tbl[j++] = ovs_tdm_tbl[i]; } 316 else cnt++; 317 } 318 div=cnt; 319 320 for(i= ((size/div)-1); i<size; i+= (size/div) ) { 321 for(k=size-1; k>=i; k--){ 322 uniq_elements_tbl[k] = uniq_elements_tbl[k-1]; 323 } 324 uniq_elements_tbl[i]=port; 325 if ((--cnt)<=0) { 326 break; 327 } 328 } 329 330 for (i=0; i<size; i++) { 331 if(uniq_elements_tbl[i]== port) { 332 uniq_elements_tbl[i] = token++; 333 if((cnt1++) ==3) { 334 cnt1 =0; 335 token=port; 336 } 337 } 338 } 339 TDM_COPY(ovs_tdm_tbl,uniq_elements_tbl,sizeof(int)*MN_OS_LLS_GRP_LEN); 340 } 341 */ 342 343 344 /** 345 @name: tdm_postalloc 346 @param: 347 348 Unless special exceptions are needed for certain port speeds, this is the standard procedure to load time vectors into TDM vector map 349 */ 350 int 351 mn_tdm_postalloc(unsigned short **vector_map, int freq, unsigned short spd, short *yy, short *y, int lr_idx_limit, unsigned short lr_stack[TDM_AUX_SIZE], int token, const char* speed, int num_ext_ports) 352 { 353 int v, load_status; 354 355 TDM_BIG_BAR 356 TDM_PRINT1("%sG scheduling pass\n",speed); 357 TDM_SML_BAR 358 TDM_PRINT0("Stack contains: [ "); 359 for (v=*y; v>0; v--) { 360 if (lr_stack[v]!=num_ext_ports) { 361 TDM_PRINT1(" %0d ",lr_stack[v]); 362 } 363 } 364 TDM_PRINT0(" ]\n"); 365 TDM_SML_BAR 366 while (*y > 0) { 367 load_status = tdm_mn_vec_load(vector_map, freq, spd, *yy, lr_idx_limit, num_ext_ports); 368 if (load_status==FAIL) { 369 TDM_ERROR2("Failed to load %sG vector for port %0d\n",speed,lr_stack[*y]); 370 return FAIL; 371 } 372 else { 373 for (v=0; v<VEC_MAP_LEN; v++) { 374 if (vector_map[*yy][v]==token) { 375 vector_map[*yy][v]=lr_stack[*y]; 376 } 377 } 378 TDM_PRINT4("Loaded %sG port %d vector from stack pointer %d into map at index %0d\n",speed, lr_stack[*y], *y, *yy); 379 } 380 (*y)--; (*yy)++; 381 if ((*y)>0) { 382 TDM_SML_BAR 383 TDM_PRINT2("Map pointer rolled to: %0d, stack pointer is at: %0d\n", *yy, *y); 384 TDM_SML_BAR 385 } 386 else { 387 TDM_SML_BAR 388 TDM_PRINT2("Done loading %sG vectors, map pointer floating at: %0d\n",speed, *yy); 389 TDM_SML_BAR 390 } 391 } 392 TDM_BIG_BAR 393 394 return PASS; 395 396 } 397 398 int 399 mn_tdm_acc_alloc(unsigned short **vector_map, int freq, unsigned short spd, short *yy, int lr_idx_limit, int num_ext_ports) 400 { 401 int load_status; 402 403 TDM_BIG_BAR 404 TDM_PRINT0("ACC BW scheduling pass\n"); 405 TDM_SML_BAR 406 407 load_status = tdm_mn_vec_load(vector_map, freq, spd, *yy, lr_idx_limit, num_ext_ports); 408 if (load_status==FAIL) { 409 TDM_ERROR1("Failed to load acc_bw vectors for acc ports %0d\n",MN_ANCL_TOKEN); 410 return FAIL; 411 } 412 (*yy)++; 413 414 TDM_PRINT1("Done loading acc_bw vectors for acc ports, map pointer floating at: %0d\n",*yy); 415 TDM_BIG_BAR 416 417 return PASS; 418 419 } 420 421 422 int 423 tdm_mn_actual_pmap( tdm_mod_t *_tdm ) 424 { 425 int i; 426 427 if (_tdm==NULL) {return FAIL;} 428 429 for (i=1; i<=MN_NUM_PHY_PORTS; i+=MN_NUM_PM_LNS) { 430 /* CLPORTS PM4x25 in dual port mode */ 431 if (_tdm->_chip_data.soc_pkg.speed[i]==SPEED_50G && _tdm->_chip_data.soc_pkg.speed[i+2]==SPEED_50G) { 432 _tdm->_chip_data.soc_pkg.pmap[(i-1)/MN_NUM_PM_LNS][0] = i; 433 _tdm->_chip_data.soc_pkg.pmap[(i-1)/MN_NUM_PM_LNS][1] = i; 434 _tdm->_chip_data.soc_pkg.pmap[(i-1)/MN_NUM_PM_LNS][2] = i+2; 435 _tdm->_chip_data.soc_pkg.pmap[(i-1)/MN_NUM_PM_LNS][3] = i+2; 436 } 437 /* CLPORTS PM4x25 in tri-port mode x-xx or xx-x */ 438 if(i==MN_CL1_PORT || i==MN_CL2_PORT || i==MN_CL4_PORT || i==MN_CL5_PORT ){ 439 if ( _tdm->_chip_data.soc_pkg.speed[i]>_tdm->_chip_data.soc_pkg.speed[i+2] && _tdm->_chip_data.soc_pkg.speed[i+2]==_tdm->_chip_data.soc_pkg.speed[i+3] && _tdm->_chip_data.soc_pkg.speed[i+2]!=SPEED_0 ) { 440 _tdm->_chip_data.soc_pkg.pmap[(i-1)/MN_NUM_PM_LNS][1] = _tdm->_chip_data.soc_pkg.pmap[(i-1)/MN_NUM_PM_LNS][2]; 441 _tdm->_chip_data.soc_pkg.pmap[(i-1)/MN_NUM_PM_LNS][2] = _tdm->_chip_data.soc_pkg.pmap[(i-1)/MN_NUM_PM_LNS][0]; 442 } 443 else if ( _tdm->_chip_data.soc_pkg.speed[i]==_tdm->_chip_data.soc_pkg.speed[i+1] && _tdm->_chip_data.soc_pkg.speed[i]<_tdm->_chip_data.soc_pkg.speed[i+2] && _tdm->_chip_data.soc_pkg.speed[i]!=SPEED_0 ) { 444 _tdm->_chip_data.soc_pkg.pmap[(i-1)/MN_NUM_PM_LNS][2] = _tdm->_chip_data.soc_pkg.pmap[(i-1)/MN_NUM_PM_LNS][1]; 445 _tdm->_chip_data.soc_pkg.pmap[(i-1)/MN_NUM_PM_LNS][1] = _tdm->_chip_data.soc_pkg.pmap[(i-1)/MN_NUM_PM_LNS][3]; 446 } 447 } 448 } 449 450 return PASS; 451 } 452 453 454 /** 455 @name: tdm_mn_vmap_alloc 456 @param: 457 458 Populate original vmap containing all linerate ports with matched speed rates accordingly 459 */ 460 int 461 tdm_mn_vmap_alloc( tdm_mod_t *_tdm ) 462 { 463 int j, v, w, clk_freq, vmap_port_spd, cal_length; 464 unsigned short lr1[TDM_AUX_SIZE], lr10[TDM_AUX_SIZE], lr20[TDM_AUX_SIZE], lr25[TDM_AUX_SIZE], lr40[TDM_AUX_SIZE], lr50[TDM_AUX_SIZE], lr100[TDM_AUX_SIZE]; 465 int speed_type_num, 466 num_120g, num_100g, num_50g, num_40g, 467 num_25g, num_20g, num_10g, num_1g; 468 int param_vmap_wid, param_vmap_len; 469 470 param_vmap_wid = _tdm->_core_data.vmap_max_wid; 471 param_vmap_len = _tdm->_core_data.vmap_max_len; 472 473 /* Initialize speed group arrays for both linerate and oversub */ 474 for (j=0; j<(TDM_AUX_SIZE); j++) { 475 lr1[j] = MN_NUM_EXT_PORTS; 476 lr10[j] = MN_NUM_EXT_PORTS; 477 lr20[j] = MN_NUM_EXT_PORTS; 478 lr25[j] = MN_NUM_EXT_PORTS; 479 lr40[j] = MN_NUM_EXT_PORTS; 480 lr50[j] = MN_NUM_EXT_PORTS; 481 lr100[j]= MN_NUM_EXT_PORTS; 482 483 _tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.os1[j] = MN_NUM_EXT_PORTS; 484 _tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.os10[j] = MN_NUM_EXT_PORTS; 485 _tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.os20[j] = MN_NUM_EXT_PORTS; 486 _tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.os25[j] = MN_NUM_EXT_PORTS; 487 _tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.os40[j] = MN_NUM_EXT_PORTS; 488 _tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.os50[j] = MN_NUM_EXT_PORTS; 489 _tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.os100[j]= MN_NUM_EXT_PORTS; 490 _tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.os120[j]= MN_NUM_EXT_PORTS; 491 } 492 clk_freq = _tdm->_chip_data.soc_pkg.clk_freq; 493 cal_length= _tdm->_chip_data.soc_pkg.lr_idx_limit+_tdm->_chip_data.soc_pkg.tvec_size; 494 495 for (j=0; j<TDM_AUX_SIZE; j++) { 496 /* Pre-allocate linerate ports with the same speed into the same linerate speed group */ 497 if (_tdm->_core_data.vars_pkg.lr_buffer[j] != MN_NUM_EXT_PORTS){ 498 if (_tdm->_core_data.vars_pkg.lr_buffer[j] <= MN_NUM_PHY_PORTS){ 499 if (_tdm->_chip_data.soc_pkg.state[_tdm->_core_data.vars_pkg.lr_buffer[j]-1] == PORT_STATE__LINERATE || 500 _tdm->_chip_data.soc_pkg.state[_tdm->_core_data.vars_pkg.lr_buffer[j]-1] == PORT_STATE__LINERATE_HG){ 501 switch (_tdm->_chip_data.soc_pkg.speed[_tdm->_core_data.vars_pkg.lr_buffer[j]]) { 502 case SPEED_1G: 503 case SPEED_2p5G: 504 tdm_core_prealloc(lr1, _tdm->_core_data.vars_pkg.lr_buffer, &(_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y8), &(_tdm->_core_data.vars_pkg.lr_1), j); 505 break; 506 case SPEED_10G: 507 case SPEED_11G: 508 case SPEED_10G_DUAL: 509 case SPEED_10G_XAUI: 510 tdm_core_prealloc(lr10, _tdm->_core_data.vars_pkg.lr_buffer, &(_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y1), &(_tdm->_core_data.vars_pkg.lr_10), j); 511 break; 512 case SPEED_20G: 513 case SPEED_21G: 514 case SPEED_21G_DUAL: 515 tdm_core_prealloc(lr20, _tdm->_core_data.vars_pkg.lr_buffer, &(_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y2), &(_tdm->_core_data.vars_pkg.lr_20), j); 516 break; 517 case SPEED_25G: 518 case SPEED_27G: 519 tdm_core_prealloc(lr25, _tdm->_core_data.vars_pkg.lr_buffer, &(_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y6), &(_tdm->_core_data.vars_pkg.lr_25), j); 520 break; 521 case SPEED_40G: 522 case SPEED_42G: 523 case SPEED_42G_HG2: 524 tdm_core_prealloc(lr40, _tdm->_core_data.vars_pkg.lr_buffer, &(_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y3), &(_tdm->_core_data.vars_pkg.lr_40), j); 525 break; 526 case SPEED_50G: 527 case SPEED_53G: 528 tdm_core_prealloc(lr50, _tdm->_core_data.vars_pkg.lr_buffer, &(_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y5), &(_tdm->_core_data.vars_pkg.lr_50), j); 529 break; 530 case SPEED_100G: 531 case SPEED_106G: 532 tdm_core_prealloc(lr100, _tdm->_core_data.vars_pkg.lr_buffer, &(_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y4), &(_tdm->_core_data.vars_pkg.lr_100), j); 533 break; 534 default: 535 TDM_ERROR2("Speed %0d port %0d was skipped in linerate preallocation\n",_tdm->_chip_data.soc_pkg.speed[_tdm->_core_data.vars_pkg.lr_buffer[j]],_tdm->_core_data.vars_pkg.lr_buffer[j]); 536 break; 537 } 538 } 539 else{ 540 TDM_ERROR2("Failed to presort linerate port %0d with state mapping %0d\n", _tdm->_core_data.vars_pkg.lr_buffer[j], _tdm->_chip_data.soc_pkg.state[_tdm->_core_data.vars_pkg.lr_buffer[j]-1]); 541 } 542 } 543 else{ 544 TDM_ERROR1("Unrecognized linerate port %0d in linerate preallocation\n", _tdm->_core_data.vars_pkg.lr_buffer[j]); 545 } 546 } 547 /* Pre-allocate oversub ports with the same speed into the same ovesub speed group */ 548 if (_tdm->_core_data.vars_pkg.os_buffer[j] != MN_NUM_EXT_PORTS){ 549 if(_tdm->_core_data.vars_pkg.os_buffer[j] <= MN_NUM_PHY_PORTS){ 550 if (_tdm->_chip_data.soc_pkg.state[_tdm->_core_data.vars_pkg.os_buffer[j]-1] == PORT_STATE__OVERSUB || 551 _tdm->_chip_data.soc_pkg.state[_tdm->_core_data.vars_pkg.os_buffer[j]-1] == PORT_STATE__OVERSUB_HG){ 552 switch (_tdm->_chip_data.soc_pkg.speed[_tdm->_core_data.vars_pkg.os_buffer[j]]) { 553 case SPEED_1G: 554 case SPEED_2p5G: 555 tdm_core_prealloc(_tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.os1, _tdm->_core_data.vars_pkg.os_buffer, &(_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.z8), &(_tdm->_core_data.vars_pkg.os_1), j); 556 break; 557 case SPEED_10G: 558 case SPEED_11G: 559 case SPEED_10G_DUAL: 560 case SPEED_10G_XAUI: 561 tdm_core_prealloc(_tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.os10, _tdm->_core_data.vars_pkg.os_buffer, &(_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.z1), &(_tdm->_core_data.vars_pkg.os_10), j); 562 break; 563 case SPEED_20G: 564 case SPEED_21G: 565 case SPEED_21G_DUAL: 566 tdm_core_prealloc(_tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.os20, _tdm->_core_data.vars_pkg.os_buffer, &(_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.z2), &(_tdm->_core_data.vars_pkg.os_20), j); 567 break; 568 case SPEED_25G: 569 case SPEED_27G: 570 tdm_core_prealloc(_tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.os25, _tdm->_core_data.vars_pkg.os_buffer, &(_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.z6), &(_tdm->_core_data.vars_pkg.os_25), j); 571 break; 572 case SPEED_40G: 573 case SPEED_42G: 574 case SPEED_42G_HG2: 575 tdm_core_prealloc(_tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.os40, _tdm->_core_data.vars_pkg.os_buffer, &(_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.z3), &(_tdm->_core_data.vars_pkg.os_40), j); 576 break; 577 case SPEED_50G: 578 case SPEED_53G: 579 tdm_core_prealloc(_tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.os50, _tdm->_core_data.vars_pkg.os_buffer, &(_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.z5), &(_tdm->_core_data.vars_pkg.os_50), j); 580 break; 581 case SPEED_100G: 582 case SPEED_106G: 583 tdm_core_prealloc(_tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.os100, _tdm->_core_data.vars_pkg.os_buffer, &(_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.z4), &(_tdm->_core_data.vars_pkg.os_100), j); 584 break; 585 default: 586 TDM_ERROR2("Speed %0d port %0d was skipped in oversub preallocation\n",_tdm->_chip_data.soc_pkg.speed[_tdm->_core_data.vars_pkg.os_buffer[j]],_tdm->_core_data.vars_pkg.os_buffer[j]); 587 } 588 } 589 else{ 590 TDM_ERROR2("Failed to presort oversub port %0d with state mapping %0d\n", _tdm->_core_data.vars_pkg.os_buffer[j], _tdm->_chip_data.soc_pkg.state[_tdm->_core_data.vars_pkg.os_buffer[j]-1]); 591 } 592 } 593 else{ 594 TDM_ERROR1("Unrecognized oversub port %0d in oversub preallocation\n", _tdm->_core_data.vars_pkg.lr_buffer[j]); 595 } 596 } 597 } 598 /* Set part of parameters used by core execution for vmap population */ 599 _tdm->_core_data.vars_pkg.os_enable = (_tdm->_core_data.vars_pkg.os_1||_tdm->_core_data.vars_pkg.os_10||_tdm->_core_data.vars_pkg.os_20||_tdm->_core_data.vars_pkg.os_25||_tdm->_core_data.vars_pkg.os_40||_tdm->_core_data.vars_pkg.os_50||_tdm->_core_data.vars_pkg.os_100||_tdm->_core_data.vars_pkg.os_120); 600 _tdm->_core_data.vars_pkg.lr_enable = (_tdm->_core_data.vars_pkg.lr_1||_tdm->_core_data.vars_pkg.lr_10||_tdm->_core_data.vars_pkg.lr_20||_tdm->_core_data.vars_pkg.lr_25||_tdm->_core_data.vars_pkg.lr_40||_tdm->_core_data.vars_pkg.lr_50||_tdm->_core_data.vars_pkg.lr_100||_tdm->_core_data.vars_pkg.lr_120); 601 _tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.num_lr = (_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y8+_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y1+_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y2+_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y3+_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y4+_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y5+_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y6+_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y7); 602 _tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.num_os = (_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.z8+_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.z1+_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.z2+_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.z3+_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.z4+_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.z5+_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.z6+_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.z7); 603 _tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.num_100g = _tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y4; 604 _tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.num_40g = _tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y3; 605 { 606 num_120g= _tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y7; 607 num_100g= _tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y4; 608 num_50g = _tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y5; 609 num_40g = _tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y3; 610 num_25g = _tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y6; 611 num_20g = _tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y2; 612 num_10g = _tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y1; 613 num_1g = _tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y8; 614 speed_type_num = _tdm->_core_data.vars_pkg.lr_1+ 615 _tdm->_core_data.vars_pkg.lr_10+ 616 _tdm->_core_data.vars_pkg.lr_20+ 617 _tdm->_core_data.vars_pkg.lr_25+ 618 _tdm->_core_data.vars_pkg.lr_40+ 619 _tdm->_core_data.vars_pkg.lr_50+ 620 _tdm->_core_data.vars_pkg.lr_100+ 621 _tdm->_core_data.vars_pkg.lr_120; 622 TDM_PRINT2("%8s%d\n", "120G - ", num_120g); 623 TDM_PRINT2("%8s%d\n", "100G - ", num_100g); 624 TDM_PRINT2("%8s%d\n", " 50G - ", num_50g); 625 TDM_PRINT2("%8s%d\n", " 40G - ", num_40g); 626 TDM_PRINT2("%8s%d\n", " 25G - ", num_25g); 627 TDM_PRINT2("%8s%d\n", " 20G - ", num_20g); 628 TDM_PRINT2("%8s%d\n", " 10G - ", num_10g); 629 TDM_PRINT2("%8s%d\n", " 1G - ", num_1g); 630 TDM_PRINT1("\nNumber of Linerate Speed Types: %d\n\n", speed_type_num); 631 TDM_BIG_BAR 632 } 633 /* Populate original vmap with pre-allocated linerate speed groups */ 634 /* 100G */ 635 if(_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y4 > 0){ 636 vmap_port_spd = 100; 637 if (tdm_core_postalloc_vmap(_tdm->_core_data.vmap, clk_freq, vmap_port_spd, &_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.yy, &(_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y4), cal_length, lr100, TOKEN_100G, "100", MN_NUM_EXT_PORTS, param_vmap_wid, param_vmap_len)!=PASS) { 638 TDM_ERROR0("Critical error in 100G port vector preallocation\n"); 639 } 640 } 641 /* 50G */ 642 if(_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y5 > 0){ 643 for (v=_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y5; v>0; v--) { 644 if (tdm_mn_legacy_which_tsc(lr50[v+1],_tdm->_chip_data.soc_pkg.pmap)==tdm_mn_legacy_which_tsc(lr50[v],_tdm->_chip_data.soc_pkg.pmap) || 645 tdm_mn_legacy_which_tsc(lr50[v-1],_tdm->_chip_data.soc_pkg.pmap)==tdm_mn_legacy_which_tsc(lr50[v],_tdm->_chip_data.soc_pkg.pmap)) { 646 _tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.prox_swap=lr50[v]; 647 for (w=v; w>0; w--) { 648 lr50[w]=lr50[w-1]; 649 } 650 lr50[1]=_tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.prox_swap; 651 } 652 } 653 for (v=_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y5; v>0; v--) { 654 _tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.tri_chk = tdm_mn_legacy_which_tsc(lr50[v],_tdm->_chip_data.soc_pkg.pmap); 655 for (w=0; w<4; w++) { 656 if (_tdm->_chip_data.soc_pkg.speed[_tdm->_chip_data.soc_pkg.pmap[_tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.tri_chk][w]]!=SPEED_50G) { 657 _tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.tri_en_50=BOOL_TRUE; 658 TDM_PRINT0("50G triport detected\n"); 659 break; 660 } 661 } 662 } 663 vmap_port_spd = 50; 664 if (tdm_core_postalloc_vmap(_tdm->_core_data.vmap, clk_freq, vmap_port_spd, &_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.yy, &(_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y5), cal_length, lr50, TOKEN_50G, "50", MN_NUM_EXT_PORTS, param_vmap_wid, param_vmap_len)!=PASS) { 665 TDM_ERROR0("Critical error in 50G port vector preallocation\n"); 666 } 667 } 668 /* 40G */ 669 if (_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y3 > 0) { 670 for (v=_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y3; v>0; v--) { 671 if (tdm_mn_legacy_which_tsc(lr40[v+1],_tdm->_chip_data.soc_pkg.pmap)==tdm_mn_legacy_which_tsc(lr40[v],_tdm->_chip_data.soc_pkg.pmap) || 672 tdm_mn_legacy_which_tsc(lr40[v-1],_tdm->_chip_data.soc_pkg.pmap)==tdm_mn_legacy_which_tsc(lr40[v],_tdm->_chip_data.soc_pkg.pmap)) { 673 _tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.prox_swap=lr40[v]; 674 for (w=v; w>0; w--) { 675 lr40[w]=lr40[w-1]; 676 } 677 lr40[1]=_tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.prox_swap; 678 } 679 } 680 for (v=_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y3; v>0; v--) { 681 _tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.tri_chk = tdm_mn_legacy_which_tsc(lr40[v],_tdm->_chip_data.soc_pkg.pmap); 682 for (w=0; w<4; w++) { 683 if (_tdm->_chip_data.soc_pkg.speed[_tdm->_chip_data.soc_pkg.pmap[_tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.tri_chk][w]]!=SPEED_40G && _tdm->_chip_data.soc_pkg.state[_tdm->_chip_data.soc_pkg.pmap[_tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.tri_chk][w]-1]!=PORT_STATE__DISABLED) { 684 _tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.tri_en_40=BOOL_TRUE; 685 TDM_PRINT0("40G triport detected\n"); 686 break; 687 } 688 } 689 } 690 vmap_port_spd = 40; 691 if(num_100g>0) { 692 vmap_port_spd=41; 693 } 694 else if (num_100g==0 && num_50g>0){ 695 vmap_port_spd = 44; 696 } 697 if (tdm_core_postalloc_vmap(_tdm->_core_data.vmap, clk_freq, vmap_port_spd, &_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.yy, &(_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y3), cal_length, lr40, TOKEN_40G, "40", MN_NUM_EXT_PORTS, param_vmap_wid, param_vmap_len)!=PASS) { 698 TDM_ERROR0("Critical error in 40G port vector vmap allocation\n"); 699 } 700 } 701 /* 25G */ 702 if (_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y6 > 0) { 703 for (v=_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y2; v>0; v--) { 704 _tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.tri_chk = tdm_mn_legacy_which_tsc(lr20[v],_tdm->_chip_data.soc_pkg.pmap); 705 for (w=0; w<4; w++) { 706 if (_tdm->_chip_data.soc_pkg.speed[_tdm->_chip_data.soc_pkg.pmap[_tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.tri_chk][w]]!=SPEED_20G) { 707 _tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.tri_en_20=BOOL_TRUE; 708 TDM_PRINT0("20G triport detected\n"); 709 break; 710 } 711 } 712 } 713 vmap_port_spd = 25; 714 if (_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y4==0 && 715 _tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y5==0 && 716 _tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y3>0 ){ 717 vmap_port_spd = 26; 718 } 719 if (tdm_core_postalloc_vmap(_tdm->_core_data.vmap, clk_freq, vmap_port_spd, &_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.yy, &(_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y6), cal_length, lr25, TOKEN_25G, "25", MN_NUM_EXT_PORTS, param_vmap_wid, param_vmap_len)!=PASS) { 720 TDM_ERROR0("Critical error in 25G port vector preallocation\n"); 721 } 722 } 723 /* 20G */ 724 if (_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y2 > 0) { 725 vmap_port_spd = 20; 726 if (tdm_core_postalloc_vmap(_tdm->_core_data.vmap, clk_freq, vmap_port_spd, &_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.yy, &(_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y2), cal_length, lr20, TOKEN_20G, "20", MN_NUM_EXT_PORTS, param_vmap_wid, param_vmap_len)!=PASS) { 727 TDM_ERROR0("Critical error in 20G port vector preallocation\n"); 728 } 729 } 730 /* 10G */ 731 if (_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y1 > 0) { 732 vmap_port_spd = 10; 733 if (tdm_core_postalloc_vmap(_tdm->_core_data.vmap, clk_freq, vmap_port_spd, &_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.yy, &(_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y1), cal_length, lr10, TOKEN_10G, "10", MN_NUM_EXT_PORTS, param_vmap_wid, param_vmap_len)!=PASS) { 734 TDM_ERROR0("Critical error in 10G port vector preallocation\n"); 735 } 736 } 737 /* 1G */ 738 if (_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y8 > 0) { 739 vmap_port_spd = 1; 740 if (tdm_core_postalloc_vmap(_tdm->_core_data.vmap, clk_freq, vmap_port_spd, &_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.yy, &(_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y8), cal_length, lr1, TOKEN_1G, "1", MN_NUM_EXT_PORTS, param_vmap_wid, param_vmap_len)!=PASS) { 741 TDM_ERROR0("Critical error in 1G port vector preallocation\n"); 742 } 743 } 744 745 /* 746 return ( _tdm->_core_exec[TDM_CORE_EXEC__SCHEDULER]( _tdm ) ); */ 747 return (tdm_mn_vbs_scheduler(_tdm)); 748 } 749 750 751 /** 752 @name: tdm_mn_acc_alloc_new 753 @param: 754 */ 755 int 756 tdm_mn_acc_alloc_new( tdm_mod_t *_tdm ) 757 { 758 int i,j, idx, idx_opt, idx_up, idx_dn, dist_opt=0, 759 empty_slot_cnt=0, empty_slot_token, acc_slot_cnt=0, acc_slot_token, 760 acc_slot_num, result=PASS; 761 762 int *tdm_pipe_main, tdm_pipe_main_len; 763 764 TDM_SEL_CAL(_tdm->_core_data.vars_pkg.cal_id,tdm_pipe_main); 765 tdm_pipe_main_len = _tdm->_chip_data.soc_pkg.lr_idx_limit + _tdm->_chip_data.soc_pkg.tvec_size; 766 empty_slot_token = _tdm->_chip_data.soc_pkg.num_ext_ports; 767 acc_slot_num = _tdm->_chip_data.soc_pkg.tvec_size; 768 acc_slot_token = MN_ANCL_TOKEN; 769 770 /* check available slots */ 771 for (i=0; i<tdm_pipe_main_len; i++){ 772 if (tdm_pipe_main[i] == empty_slot_token){ 773 empty_slot_cnt++; 774 } 775 } 776 if (empty_slot_cnt<acc_slot_num){ 777 TDM_ERROR2("FAILED in ACC bandwidth allocation, Not enough available slots for ACC, Slot_Required %d, Slot_Available %d\n",acc_slot_cnt, empty_slot_cnt); 778 result = FAIL; 779 } 780 /* allocate acc slots */ 781 if (acc_slot_num>0 && result==PASS){ 782 dist_opt = tdm_pipe_main_len/acc_slot_num; 783 for (i=0; i<acc_slot_num; i++){ 784 idx_opt = i*dist_opt; 785 if(idx_opt<tdm_pipe_main_len){ 786 idx = tdm_pipe_main_len; 787 idx_up = tdm_pipe_main_len; 788 idx_dn = tdm_pipe_main_len; 789 for (j=idx_opt; j>0; j--){ 790 if(tdm_pipe_main[j]==empty_slot_token){ 791 idx_up = j; 792 break; 793 } 794 } 795 for (j=idx_opt; j<tdm_pipe_main_len; j++){ 796 if(tdm_pipe_main[j]==empty_slot_token){ 797 idx_dn = j; 798 break; 799 } 800 } 801 if (idx_up<tdm_pipe_main_len || idx_dn<tdm_pipe_main_len){ 802 if (idx_up==tdm_pipe_main_len){ 803 idx = idx_dn; 804 } 805 else if (idx_dn==tdm_pipe_main_len){ 806 idx = idx_up; 807 } 808 else{ 809 idx = ((idx_opt-idx_up) < (idx_dn-idx_opt))? (idx_up): (idx_dn); 810 } 811 } 812 813 if (idx < tdm_pipe_main_len){ 814 tdm_pipe_main[idx] = acc_slot_token; 815 } 816 } 817 } 818 } 819 /* check acc slots */ 820 if (acc_slot_num>0 && result==PASS){ 821 for (i=0; i<tdm_pipe_main_len; i++){ 822 if (tdm_pipe_main[i] == acc_slot_token){ 823 acc_slot_cnt++; 824 } 825 } 826 if(acc_slot_cnt != acc_slot_num){ 827 result = FAIL; 828 TDM_ERROR2("FAILED in ACC bandwidth allocation, Slot_Required %d, Slot_Allocated %d\n",acc_slot_num, acc_slot_cnt); 829 } 830 } 831 832 return result; 833 } 834 835 /** 836 @name: tdm_mn_vbs_scheduler 837 @param: 838 */ 839 int 840 tdm_mn_vbs_scheduler( tdm_mod_t *_tdm ) 841 { 842 int i, *tdm_pipe_main, tdm_cal_length, cnt=0; 843 TDM_SEL_CAL(_tdm->_core_data.vars_pkg.cal_id,tdm_pipe_main); 844 tdm_cal_length = _tdm->_chip_data.soc_pkg.lr_idx_limit+_tdm->_chip_data.soc_pkg.tvec_size; 845 846 /* Allocate slots for all linerate ports among entire TDM calendar */ 847 if (_tdm->_core_data.vars_pkg.lr_enable) { 848 if(FAIL==tdm_core_vbs_scheduler_lr(_tdm)){ 849 TDM_ERROR0("FAILED in slot allocation for LINERATE ports\n"); 850 } 851 } 852 /* Allocate ACC slots */ 853 if (_tdm->_core_data.vars_pkg.os_enable || _tdm->_core_data.vars_pkg.lr_enable) { 854 if(FAIL==tdm_mn_acc_alloc_new(_tdm)){ 855 TDM_ERROR0("FAILED in slot allocation for ANCILLARY bandwidth\n"); 856 } 857 } 858 /* Allocate OVSB and/or IDLE slots */ 859 if (_tdm->_core_data.vars_pkg.os_enable || _tdm->_core_data.vars_pkg.lr_enable) { 860 /* OVSB: Place the OVS token for all unallocated slots */ 861 if (_tdm->_core_data.vars_pkg.os_enable && (!_tdm->_core_data.vars_pkg.lr_enable)) { 862 for (i=0; i<tdm_cal_length; i++) { 863 if (tdm_pipe_main[i]==_tdm->_chip_data.soc_pkg.num_ext_ports) { 864 tdm_pipe_main[i] = _tdm->_chip_data.soc_pkg.soc_vars.ovsb_token; 865 } 866 } 867 } 868 /* IDLE: Place IDLE tokens for all unallocated slots */ 869 else { 870 for (i=0; i<tdm_cal_length; i++) { 871 if (tdm_pipe_main[i]==_tdm->_chip_data.soc_pkg.num_ext_ports) { 872 if (_tdm->_core_data.vars_pkg.os_enable) { 873 tdm_pipe_main[i] = _tdm->_chip_data.soc_pkg.soc_vars.ovsb_token; 874 } 875 else { 876 if ((cnt++)%2==0) { 877 tdm_pipe_main[i] = _tdm->_chip_data.soc_pkg.soc_vars.idl1_token; 878 } 879 else { 880 tdm_pipe_main[i] = _tdm->_chip_data.soc_pkg.soc_vars.idl2_token; 881 } 882 } 883 } 884 } 885 } 886 } 887 888 /* OVS grouping */ 889 if (_tdm->_core_exec[TDM_CORE_EXEC__SCHEDULER_OVS](_tdm)==FAIL) { 890 return (TDM_EXEC_CORE_SIZE+1); 891 } 892 893 return ( _tdm->_chip_exec[TDM_CHIP_EXEC__FILTER](_tdm) ); 894 } 895 896 /** 897 * @name: tdm_mn_cal_pgw_bw 898 * @param: 899 * 900 * Calculate PGW IO BW 901 */ 902 void 903 tdm_mn_cal_pgw_bw( tdm_mod_t *_tdm, int *pgw_io_bw, int start_offset, int *high_speed_port_slots ) 904 { 905 int p, high_speed_100G_port_found=0, high_speed_50G_port_found =0; 906 for (p = (start_offset*(MN_NUM_PHY_PORTS/MN_NUM_QUAD)); p < ( (start_offset+1) *(MN_NUM_PHY_PORTS/MN_NUM_QUAD)); p++) { 907 switch (_tdm->_chip_data.soc_pkg.speed[p+1]) { 908 case SPEED_1G: 909 *pgw_io_bw = *pgw_io_bw + 1; 910 break; 911 case SPEED_2G: 912 *pgw_io_bw = *pgw_io_bw + 3; 913 break; 914 case SPEED_2p5G: 915 *pgw_io_bw = *pgw_io_bw + 3; 916 break; 917 case SPEED_5G: 918 *pgw_io_bw = *pgw_io_bw + 5; 919 break; 920 case SPEED_10G: 921 case SPEED_10G_DUAL: 922 case SPEED_10G_XAUI: 923 case SPEED_11G: 924 *pgw_io_bw = *pgw_io_bw + 10; 925 break; 926 case SPEED_12p5G: 927 *pgw_io_bw = *pgw_io_bw + 13; 928 break; 929 case SPEED_20G: 930 case SPEED_21G: 931 case SPEED_21G_DUAL: 932 *pgw_io_bw = *pgw_io_bw + 20; 933 break; 934 case SPEED_25G: 935 case SPEED_27G: 936 *pgw_io_bw = *pgw_io_bw + 25; 937 break; 938 case SPEED_40G: 939 case SPEED_42G: 940 case SPEED_42G_HG2: 941 *pgw_io_bw = *pgw_io_bw + 40; 942 break; 943 case SPEED_50G: 944 case SPEED_53G: 945 *pgw_io_bw = *pgw_io_bw + 50; 946 high_speed_50G_port_found = 1; 947 break; 948 case SPEED_100G: 949 case SPEED_106G: 950 *pgw_io_bw = *pgw_io_bw + 100; 951 high_speed_100G_port_found = 1; 952 break; 953 default: 954 break; 955 } 956 _tdm->_chip_data.soc_pkg.soc_vars.mn.pipe_start= (start_offset*(MN_NUM_PHY_PORTS/MN_NUM_QUAD))+1; 957 _tdm->_chip_data.soc_pkg.soc_vars.mn.pipe_end = ( (start_offset+1) *(MN_NUM_PHY_PORTS/MN_NUM_QUAD) ); 958 } 959 if(high_speed_100G_port_found == 1) { 960 *high_speed_port_slots = ( (100/(TDM_SLOT_UNIT_5G/1000)) * 2); 961 } else if(high_speed_50G_port_found == 1) { 962 *high_speed_port_slots = ( (50/(TDM_SLOT_UNIT_5G/1000)) * 2); 963 } else { 964 *high_speed_port_slots = 0; 965 } 966 high_speed_50G_port_found = 0; 967 high_speed_100G_port_found = 0; 968 } 969 970 void 971 tdm_mn_chip2core_init(tdm_mod_t *_tdm) 972 { 973 int index, token_empty; 974 975 token_empty = _tdm->_chip_data.soc_pkg.num_ext_ports; 976 977 for (index=0; index<(_tdm->_core_data.vmap_max_wid); index++) { 978 TDM_MSET(_tdm->_core_data.vmap[index], token_empty, 979 _tdm->_core_data.vmap_max_len); 980 } 981 982 _tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y8=0; 983 _tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y7=0; 984 _tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y1=0; 985 _tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y2=0; 986 _tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y3=0; 987 _tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y4=0; 988 _tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y5=0; 989 _tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y6=0; 990 _tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.yy=0; 991 _tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.z8=0; 992 _tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.z7=0; 993 _tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.z6=0; 994 _tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.z1=0; 995 _tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.z2=0; 996 _tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.z3=0; 997 _tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.z4=0; 998 _tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.z5=0; 999 _tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.z11=0; 1000 _tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.z22=0; 1001 _tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.z33=0; 1002 _tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.z44=0; 1003 _tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.z55=0; 1004 _tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.z66=0; 1005 _tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.z77=0; 1006 _tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.z88=0; 1007 _tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.z99=0; 1008 _tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.zaa=0; 1009 _tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.zbb=0; 1010 _tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.zcc=0; 1011 _tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.lr_vec_cnt=0; 1012 1013 _tdm->_core_data.vars_pkg.lr_1=BOOL_FALSE; 1014 _tdm->_core_data.vars_pkg.lr_10=BOOL_FALSE; 1015 _tdm->_core_data.vars_pkg.lr_20=BOOL_FALSE; 1016 _tdm->_core_data.vars_pkg.lr_25=BOOL_FALSE; 1017 _tdm->_core_data.vars_pkg.lr_40=BOOL_FALSE; 1018 _tdm->_core_data.vars_pkg.lr_50=BOOL_FALSE; 1019 _tdm->_core_data.vars_pkg.lr_100=BOOL_FALSE; 1020 _tdm->_core_data.vars_pkg.lr_120=BOOL_FALSE; 1021 _tdm->_core_data.vars_pkg.lr_enable=BOOL_FALSE; 1022 _tdm->_core_data.vars_pkg.os_1=BOOL_FALSE; 1023 _tdm->_core_data.vars_pkg.os_10=BOOL_FALSE; 1024 _tdm->_core_data.vars_pkg.os_20=BOOL_FALSE; 1025 _tdm->_core_data.vars_pkg.os_25=BOOL_FALSE; 1026 _tdm->_core_data.vars_pkg.os_40=BOOL_FALSE; 1027 _tdm->_core_data.vars_pkg.os_50=BOOL_FALSE; 1028 _tdm->_core_data.vars_pkg.os_100=BOOL_FALSE; 1029 _tdm->_core_data.vars_pkg.os_120=BOOL_FALSE; 1030 _tdm->_core_data.vars_pkg.os_enable=BOOL_FALSE; 1031 _tdm->_core_data.vars_pkg.HG4X106G_3X40G=BOOL_FALSE; 1032 _tdm->_core_data.vars_pkg.HG1X106G_xX40G_OVERSUB=BOOL_FALSE; 1033 _tdm->_core_data.vars_pkg.HGXx120G_Xx100G=BOOL_FALSE; 1034 _tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.num_lr=0; 1035 _tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.num_os=0; 1036 _tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.num_40g=0; 1037 _tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.num_100g=0; 1038 _tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.tri_chk=BOOL_FALSE; 1039 _tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.tri_en_50=BOOL_FALSE; 1040 _tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.tri_en_40=BOOL_FALSE; 1041 _tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.tri_en_20=BOOL_FALSE; 1042 _tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.prox_swap=token_empty; 1043 1044 TDM_MSET(_tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.os1, token_empty, TDM_AUX_SIZE); 1045 TDM_MSET(_tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.os10, token_empty, TDM_AUX_SIZE); 1046 TDM_MSET(_tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.os20, token_empty, TDM_AUX_SIZE); 1047 TDM_MSET(_tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.os25, token_empty, TDM_AUX_SIZE); 1048 TDM_MSET(_tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.os40, token_empty, TDM_AUX_SIZE); 1049 TDM_MSET(_tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.os50, token_empty, TDM_AUX_SIZE); 1050 TDM_MSET(_tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.os100,token_empty, TDM_AUX_SIZE); 1051 TDM_MSET(_tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.os120,token_empty, TDM_AUX_SIZE); 1052 1053 _tdm->_core_data.vars_pkg.m_tdm_pick_vec.triport_priority=BOOL_FALSE; 1054 1055 /* NGTDM */ 1056 _tdm->_core_data.vars_pkg.pipe_info.lr_en = 0; 1057 _tdm->_core_data.vars_pkg.pipe_info.os_en = 0; 1058 _tdm->_core_data.vars_pkg.pipe_info.num_lr_prt = 0; 1059 _tdm->_core_data.vars_pkg.pipe_info.num_os_prt = 0; 1060 TDM_MSET(_tdm->_core_data.vars_pkg.pipe_info.lr_spd_en, 0, MAX_SPEED_TYPES); 1061 TDM_MSET(_tdm->_core_data.vars_pkg.pipe_info.os_spd_en, 0, MAX_SPEED_TYPES); 1062 TDM_MSET(_tdm->_core_data.vars_pkg.pipe_info.lr_prt_cnt, 0, MAX_SPEED_TYPES); 1063 TDM_MSET(_tdm->_core_data.vars_pkg.pipe_info.os_prt_cnt, 0, MAX_SPEED_TYPES); 1064 for (index = 0; index < MAX_SPEED_TYPES; index++) { 1065 TDM_MSET(_tdm->_core_data.vars_pkg.pipe_info.lr_prt[index], token_empty, TDM_AUX_SIZE); 1066 TDM_MSET(_tdm->_core_data.vars_pkg.pipe_info.os_prt[index], token_empty, TDM_AUX_SIZE); 1067 } 1068 } 1069 1070 1071 /** 1072 * @name: tdm_mn_proc_cal_lr 1073 * @param: 1074 * 1075 * Allocate linerate slots with matched speed rates accordingly 1076 */ 1077 int 1078 tdm_mn_proc_cal_lr( tdm_mod_t *_tdm ) 1079 { 1080 int result=PASS, i=0, idx1=0, j=0, acc=0, higig_mgmt=BOOL_FALSE, lr_idx_limit=0, loop=0, k=0; 1081 int pgw_tdm_tbl0[160], pgw_tdm_tbl1[160]; 1082 int pgw_io_bw=0, actual_pgw_slots_required = 0; 1083 int *high_speed_port_slots; 1084 1085 for(idx1=0; idx1<160; idx1++){ 1086 pgw_tdm_tbl0[idx1] = MN_NUM_EXT_PORTS; 1087 pgw_tdm_tbl1[idx1] = MN_NUM_EXT_PORTS; 1088 } 1089 _tdm->_chip_data.soc_pkg.soc_vars.mn.pgw0_len = 0; 1090 _tdm->_chip_data.soc_pkg.soc_vars.mn.pgw1_len = 0; 1091 for(i =0; i<MN_LR_LLS_LEN; i++) { 1092 if(_tdm->_chip_data.cal_1.cal_main[i] == MN_NUM_EXT_PORTS) break; 1093 } 1094 high_speed_port_slots = NULL; 1095 high_speed_port_slots =(int *) TDM_ALLOC(sizeof(int *), "high_speed_port_slots"); 1096 if (high_speed_port_slots==NULL) {return FAIL;} 1097 for(i=0; i < 3; i++){ 1098 /*tdm_mn_chip2core_init(_tdm);*/ 1099 pgw_io_bw = 0; 1100 switch(i) { 1101 case 0: 1102 if(_tdm->_chip_data.soc_pkg.clk_freq != 861 && _tdm->_chip_data.soc_pkg.clk_freq != 862 1103 && _tdm->_chip_data.soc_pkg.soc_vars.mn.os_config == 0 1104 ){ 1105 1106 pgw_io_bw = 0; 1107 tdm_mn_cal_pgw_bw(_tdm, &pgw_io_bw, i, high_speed_port_slots); 1108 switch (_tdm->_chip_data.soc_pkg.clk_freq) { 1109 case 815: case 817: 1110 switch (_tdm->_chip_data.soc_pkg.soc_vars.mn.sku_core_bw) { 1111 case 0: 1112 lr_idx_limit=140; 1113 actual_pgw_slots_required = lr_idx_limit; 1114 if(actual_pgw_slots_required == *high_speed_port_slots) { 1115 lr_idx_limit = actual_pgw_slots_required; 1116 } else if (actual_pgw_slots_required > *high_speed_port_slots) { 1117 lr_idx_limit = actual_pgw_slots_required; 1118 } else if (*high_speed_port_slots > actual_pgw_slots_required) { 1119 lr_idx_limit = *high_speed_port_slots; 1120 } 1121 _tdm->_chip_data.soc_pkg.soc_vars.mn.pgw0_len = lr_idx_limit; 1122 break; 1123 case 800: case 720: case 460: 1124 lr_idx_limit= ((_tdm->_chip_data.soc_pkg.soc_vars.mn.sku_core_bw)/(TDM_SLOT_UNIT_5G/1000))/2; 1125 actual_pgw_slots_required = lr_idx_limit; 1126 if(actual_pgw_slots_required == *high_speed_port_slots) { 1127 lr_idx_limit = actual_pgw_slots_required; 1128 } else if (actual_pgw_slots_required > *high_speed_port_slots) { 1129 lr_idx_limit = actual_pgw_slots_required; 1130 } else if (*high_speed_port_slots > actual_pgw_slots_required) { 1131 lr_idx_limit = *high_speed_port_slots; 1132 } 1133 _tdm->_core_data.vars_pkg.pipe_info.slot_unit = TDM_SLOT_UNIT_5G; 1134 _tdm->_chip_data.soc_pkg.soc_vars.mn.pgw0_len = lr_idx_limit; 1135 break; 1136 } 1137 break; 1138 case 450: 1139 switch (_tdm->_chip_data.soc_pkg.soc_vars.mn.sku_core_bw) { 1140 case 460: case 360: case 200: case 400: 1141 lr_idx_limit= ((_tdm->_chip_data.soc_pkg.soc_vars.mn.sku_core_bw)/(TDM_SLOT_UNIT_5G/1000))/2; 1142 actual_pgw_slots_required = lr_idx_limit; 1143 if(actual_pgw_slots_required == *high_speed_port_slots) { 1144 lr_idx_limit = actual_pgw_slots_required; 1145 } else if (actual_pgw_slots_required > *high_speed_port_slots) { 1146 lr_idx_limit = actual_pgw_slots_required; 1147 } else if (*high_speed_port_slots > actual_pgw_slots_required) { 1148 lr_idx_limit = *high_speed_port_slots; 1149 } 1150 _tdm->_core_data.vars_pkg.pipe_info.slot_unit = TDM_SLOT_UNIT_5G; 1151 _tdm->_chip_data.soc_pkg.soc_vars.mn.pgw0_len = lr_idx_limit; 1152 break; 1153 } 1154 break; 1155 case 666: 1156 lr_idx_limit=80; 1157 actual_pgw_slots_required = lr_idx_limit; 1158 if(actual_pgw_slots_required == *high_speed_port_slots) { 1159 lr_idx_limit = actual_pgw_slots_required; 1160 } else if (actual_pgw_slots_required > *high_speed_port_slots) { 1161 lr_idx_limit = actual_pgw_slots_required; 1162 } else if (*high_speed_port_slots > actual_pgw_slots_required) { 1163 lr_idx_limit = *high_speed_port_slots; 1164 } 1165 _tdm->_core_data.vars_pkg.pipe_info.slot_unit = TDM_SLOT_UNIT_5G; 1166 _tdm->_chip_data.soc_pkg.soc_vars.mn.pgw0_len = lr_idx_limit; 1167 break; 1168 case 667: 1169 switch (_tdm->_chip_data.soc_pkg.soc_vars.mn.sku_core_bw) { 1170 case 0: 1171 lr_idx_limit=56; 1172 actual_pgw_slots_required = lr_idx_limit; 1173 if(actual_pgw_slots_required == *high_speed_port_slots) { 1174 lr_idx_limit = actual_pgw_slots_required; 1175 } else if (actual_pgw_slots_required > *high_speed_port_slots) { 1176 lr_idx_limit = actual_pgw_slots_required; 1177 } else if (*high_speed_port_slots > actual_pgw_slots_required) { 1178 lr_idx_limit = *high_speed_port_slots; 1179 } 1180 _tdm->_core_data.vars_pkg.pipe_info.slot_unit = TDM_SLOT_UNIT_5G; 1181 _tdm->_chip_data.soc_pkg.soc_vars.mn.pgw0_len = lr_idx_limit; 1182 break; 1183 default: 1184 lr_idx_limit= ((_tdm->_chip_data.soc_pkg.soc_vars.mn.sku_core_bw)/(TDM_SLOT_UNIT_5G/1000))/2; 1185 actual_pgw_slots_required = lr_idx_limit; 1186 if(actual_pgw_slots_required == *high_speed_port_slots) { 1187 lr_idx_limit = actual_pgw_slots_required; 1188 } else if (actual_pgw_slots_required > *high_speed_port_slots) { 1189 lr_idx_limit = actual_pgw_slots_required; 1190 } else if (*high_speed_port_slots > actual_pgw_slots_required) { 1191 lr_idx_limit = *high_speed_port_slots; 1192 } 1193 _tdm->_core_data.vars_pkg.pipe_info.slot_unit = TDM_SLOT_UNIT_5G; 1194 _tdm->_chip_data.soc_pkg.soc_vars.mn.pgw0_len = lr_idx_limit; 1195 break; 1196 } 1197 break; 1198 case 816: 1199 lr_idx_limit=132; 1200 actual_pgw_slots_required = lr_idx_limit; 1201 if(actual_pgw_slots_required == *high_speed_port_slots) { 1202 lr_idx_limit = actual_pgw_slots_required; 1203 } else if (actual_pgw_slots_required > *high_speed_port_slots) { 1204 lr_idx_limit = actual_pgw_slots_required; 1205 } else if (*high_speed_port_slots > actual_pgw_slots_required) { 1206 lr_idx_limit = *high_speed_port_slots; 1207 } 1208 _tdm->_chip_data.soc_pkg.soc_vars.mn.pgw0_len = lr_idx_limit; 1209 break; 1210 case 818: 1211 lr_idx_limit=160; 1212 actual_pgw_slots_required = lr_idx_limit; 1213 if(actual_pgw_slots_required == *high_speed_port_slots) { 1214 lr_idx_limit = actual_pgw_slots_required; 1215 } else if (actual_pgw_slots_required > *high_speed_port_slots) { 1216 lr_idx_limit = actual_pgw_slots_required; 1217 } else if (*high_speed_port_slots > actual_pgw_slots_required) { 1218 lr_idx_limit = *high_speed_port_slots; 1219 } 1220 _tdm->_chip_data.soc_pkg.soc_vars.mn.pgw0_len = lr_idx_limit; 1221 break; 1222 case 819: 1223 lr_idx_limit=128; 1224 actual_pgw_slots_required = lr_idx_limit; 1225 if(actual_pgw_slots_required == *high_speed_port_slots) { 1226 lr_idx_limit = actual_pgw_slots_required; 1227 } else if (actual_pgw_slots_required > *high_speed_port_slots) { 1228 lr_idx_limit = actual_pgw_slots_required; 1229 } else if (*high_speed_port_slots > actual_pgw_slots_required) { 1230 lr_idx_limit = *high_speed_port_slots; 1231 } 1232 _tdm->_chip_data.soc_pkg.soc_vars.mn.pgw0_len = lr_idx_limit; 1233 break; 1234 case 820: 1235 lr_idx_limit=152; 1236 actual_pgw_slots_required = lr_idx_limit; 1237 if(actual_pgw_slots_required == *high_speed_port_slots) { 1238 lr_idx_limit = actual_pgw_slots_required; 1239 } else if (actual_pgw_slots_required > *high_speed_port_slots) { 1240 lr_idx_limit = actual_pgw_slots_required; 1241 } else if (*high_speed_port_slots > actual_pgw_slots_required) { 1242 lr_idx_limit = *high_speed_port_slots; 1243 } 1244 _tdm->_chip_data.soc_pkg.soc_vars.mn.pgw0_len = lr_idx_limit; 1245 break; 1246 case 550: 1247 switch (_tdm->_chip_data.soc_pkg.soc_vars.mn.sku_core_bw) { 1248 case 0: 1249 lr_idx_limit=84; 1250 actual_pgw_slots_required = lr_idx_limit; 1251 if(actual_pgw_slots_required == *high_speed_port_slots) { 1252 lr_idx_limit = actual_pgw_slots_required; 1253 } else if (actual_pgw_slots_required > *high_speed_port_slots) { 1254 lr_idx_limit = actual_pgw_slots_required; 1255 } else if (*high_speed_port_slots > actual_pgw_slots_required) { 1256 lr_idx_limit = *high_speed_port_slots; 1257 } 1258 _tdm->_chip_data.soc_pkg.soc_vars.mn.pgw0_len = lr_idx_limit; 1259 break; 1260 case 580: case 460: case 280: case 400: 1261 lr_idx_limit= ((_tdm->_chip_data.soc_pkg.soc_vars.mn.sku_core_bw)/(TDM_SLOT_UNIT_5G/1000))/2; 1262 actual_pgw_slots_required = lr_idx_limit; 1263 if(actual_pgw_slots_required == *high_speed_port_slots) { 1264 lr_idx_limit = actual_pgw_slots_required; 1265 } else if (actual_pgw_slots_required > *high_speed_port_slots) { 1266 lr_idx_limit = actual_pgw_slots_required; 1267 } else if (*high_speed_port_slots > actual_pgw_slots_required) { 1268 lr_idx_limit = *high_speed_port_slots; 1269 } 1270 _tdm->_core_data.vars_pkg.pipe_info.slot_unit = TDM_SLOT_UNIT_5G; 1271 _tdm->_chip_data.soc_pkg.soc_vars.mn.pgw0_len = lr_idx_limit; 1272 break; 1273 } 1274 break; 1275 default : break; 1276 } 1277 if(_tdm->_chip_data.soc_pkg.clk_freq != 861 && _tdm->_chip_data.soc_pkg.clk_freq != 862){ 1278 for (idx1=0; idx1<TDM_AUX_SIZE; idx1++) { 1279 _tdm->_core_data.vars_pkg.lr_buffer[idx1]=MN_NUM_EXT_PORTS; 1280 _tdm->_core_data.vars_pkg.os_buffer[idx1]=MN_NUM_EXT_PORTS; 1281 } 1282 /* higig_mgmt */ 1283 if ( (_tdm->_chip_data.soc_pkg.soc_vars.mn.pm_encap_type[MN_NUM_PHY_PM]==PM_ENCAP__HIGIG2 /* && (pipe==1||pipe==2)*/) && 1284 ((_tdm->_core_data.vars_pkg.lr_buffer[0]!=MN_NUM_EXT_PORTS && _tdm->_chip_data.soc_pkg.clk_freq>=MIN_HG_FREQ) || 1285 (_tdm->_core_data.vars_pkg.lr_buffer[0]==MN_NUM_EXT_PORTS)) ) { 1286 higig_mgmt=BOOL_TRUE; 1287 } 1288 pgw_io_bw = 0.0; 1289 tdm_mn_cal_pgw_bw(_tdm, &pgw_io_bw, i, high_speed_port_slots); 1290 _tdm->_chip_data.soc_pkg.soc_vars.mn.mntry_pgw0_io_bw = pgw_io_bw; 1291 _tdm->_chip_data.soc_pkg.tvec_size = 0; 1292 /*_tdm->_chip_data.soc_pkg.lr_idx_limit= (int) (pgw_io_bw/MN_PGW_PER_SLOT_IO_BW);*/ 1293 _tdm->_chip_data.soc_pkg.lr_idx_limit= lr_idx_limit; 1294 _tdm->_core_data.vars_pkg.cal_id=0; 1295 for (idx1=0; idx1<TDM_AUX_SIZE; idx1++) { 1296 _tdm->_core_data.vars_pkg.lr_buffer[idx1]=MN_NUM_EXT_PORTS; 1297 _tdm->_core_data.vars_pkg.os_buffer[idx1]=MN_NUM_EXT_PORTS; 1298 } 1299 for (idx1=1; idx1<=32; idx1++) { 1300 if((_tdm->_chip_data.soc_pkg.state[idx1-1] == PORT_STATE__LINERATE || 1301 _tdm->_chip_data.soc_pkg.state[idx1-1] == PORT_STATE__LINERATE_HG) && 1302 (_tdm->_chip_data.soc_pkg.speed[idx1] > SPEED_0) 1303 ){ 1304 _tdm->_core_data.vars_pkg.lr_buffer[j++]= (idx1); 1305 } 1306 } 1307 /* allocate Linerate slots: vmap pre-allocation */ 1308 if(_tdm->_core_exec[TDM_CORE_EXEC__VMAP_PREALLOC](_tdm)!=PASS){ 1309 result = FAIL; 1310 } 1311 /* allocate Linerate slots: vmap allocation */ 1312 else if(_tdm->_core_exec[TDM_CORE_EXEC__VMAP_ALLOC](_tdm)!=PASS){ 1313 result = FAIL; 1314 } 1315 for(loop =0; loop<MN_LR_LLS_LEN; loop++) { 1316 pgw_tdm_tbl0[loop] = _tdm->_chip_data.cal_0.cal_main[loop]; 1317 } 1318 /*_tdm->_chip_data.soc_pkg.soc_vars.mn.pgw0_len = loop;*/ 1319 TDM_PRINT0("\n==================== Monterey PGW-0 TDM Calendar ==================\n"); 1320 tdm_mn_tdm_print(_tdm->_chip_data.cal_0.cal_main, MN_LR_LLS_LEN); 1321 TDM_PRINT0("\n==================== Monterey PGW-0 TDM Calendar ==================\n"); 1322 } 1323 break; 1324 } 1325 case 1: 1326 if(_tdm->_chip_data.soc_pkg.clk_freq != 861 && _tdm->_chip_data.soc_pkg.clk_freq != 862 1327 && _tdm->_chip_data.soc_pkg.soc_vars.mn.os_config == 0 1328 ){ 1329 pgw_io_bw = 0; 1330 tdm_mn_cal_pgw_bw(_tdm, &pgw_io_bw, i, high_speed_port_slots); 1331 switch (_tdm->_chip_data.soc_pkg.clk_freq) { 1332 case 815: 1333 lr_idx_limit=152; 1334 actual_pgw_slots_required = lr_idx_limit; 1335 if(actual_pgw_slots_required == *high_speed_port_slots) { 1336 lr_idx_limit = actual_pgw_slots_required; 1337 } else if (actual_pgw_slots_required > *high_speed_port_slots) { 1338 lr_idx_limit = actual_pgw_slots_required; 1339 } else if (*high_speed_port_slots > actual_pgw_slots_required) { 1340 lr_idx_limit = *high_speed_port_slots; 1341 } 1342 _tdm->_chip_data.soc_pkg.soc_vars.mn.pgw1_len = lr_idx_limit; 1343 break; 1344 case 666: 1345 lr_idx_limit=44; 1346 actual_pgw_slots_required = lr_idx_limit; 1347 if(actual_pgw_slots_required == *high_speed_port_slots) { 1348 lr_idx_limit = actual_pgw_slots_required; 1349 } else if (actual_pgw_slots_required > *high_speed_port_slots) { 1350 lr_idx_limit = actual_pgw_slots_required; 1351 } else if (*high_speed_port_slots > actual_pgw_slots_required) { 1352 lr_idx_limit = *high_speed_port_slots; 1353 } 1354 _tdm->_core_data.vars_pkg.pipe_info.slot_unit = TDM_SLOT_UNIT_5G; 1355 _tdm->_chip_data.soc_pkg.soc_vars.mn.pgw1_len = lr_idx_limit; 1356 break; 1357 case 667: 1358 switch (_tdm->_chip_data.soc_pkg.soc_vars.mn.sku_core_bw) { 1359 case 0: 1360 lr_idx_limit=80; 1361 _tdm->_core_data.vars_pkg.pipe_info.slot_unit = TDM_SLOT_UNIT_5G; 1362 _tdm->_chip_data.soc_pkg.soc_vars.mn.pgw1_len = lr_idx_limit; 1363 break; 1364 default: 1365 lr_idx_limit= ((_tdm->_chip_data.soc_pkg.soc_vars.mn.sku_core_bw)/(TDM_SLOT_UNIT_5G/1000))/2; 1366 actual_pgw_slots_required = lr_idx_limit; 1367 if(actual_pgw_slots_required == *high_speed_port_slots) { 1368 lr_idx_limit = actual_pgw_slots_required; 1369 } else if (actual_pgw_slots_required > *high_speed_port_slots) { 1370 lr_idx_limit = actual_pgw_slots_required; 1371 } else if (*high_speed_port_slots > actual_pgw_slots_required) { 1372 lr_idx_limit = *high_speed_port_slots; 1373 } 1374 _tdm->_core_data.vars_pkg.pipe_info.slot_unit = TDM_SLOT_UNIT_5G; 1375 _tdm->_chip_data.soc_pkg.soc_vars.mn.pgw1_len = lr_idx_limit; 1376 break; 1377 } 1378 break; 1379 case 816: 1380 lr_idx_limit=136; 1381 actual_pgw_slots_required = lr_idx_limit; 1382 if(actual_pgw_slots_required == *high_speed_port_slots) { 1383 lr_idx_limit = actual_pgw_slots_required; 1384 } else if (actual_pgw_slots_required > *high_speed_port_slots) { 1385 lr_idx_limit = actual_pgw_slots_required; 1386 } else if (*high_speed_port_slots > actual_pgw_slots_required) { 1387 lr_idx_limit = *high_speed_port_slots; 1388 } 1389 _tdm->_chip_data.soc_pkg.soc_vars.mn.pgw1_len = lr_idx_limit; 1390 break; 1391 case 450: 1392 switch (_tdm->_chip_data.soc_pkg.soc_vars.mn.sku_core_bw) { 1393 case 460: case 360: case 200: case 400: 1394 lr_idx_limit= ((_tdm->_chip_data.soc_pkg.soc_vars.mn.sku_core_bw)/(TDM_SLOT_UNIT_5G/1000))/2; 1395 actual_pgw_slots_required = lr_idx_limit; 1396 if(actual_pgw_slots_required == *high_speed_port_slots) { 1397 lr_idx_limit = actual_pgw_slots_required; 1398 } else if (actual_pgw_slots_required > *high_speed_port_slots) { 1399 lr_idx_limit = actual_pgw_slots_required; 1400 } else if (*high_speed_port_slots > actual_pgw_slots_required) { 1401 lr_idx_limit = *high_speed_port_slots; 1402 } 1403 _tdm->_core_data.vars_pkg.pipe_info.slot_unit = TDM_SLOT_UNIT_5G; 1404 _tdm->_chip_data.soc_pkg.soc_vars.mn.pgw1_len = lr_idx_limit; 1405 break; 1406 } 1407 break; 1408 case 817: 1409 switch (_tdm->_chip_data.soc_pkg.soc_vars.mn.sku_core_bw) { 1410 case 0: 1411 lr_idx_limit=149; 1412 actual_pgw_slots_required = lr_idx_limit; 1413 if(actual_pgw_slots_required == *high_speed_port_slots) { 1414 lr_idx_limit = actual_pgw_slots_required; 1415 } else if (actual_pgw_slots_required > *high_speed_port_slots) { 1416 lr_idx_limit = actual_pgw_slots_required; 1417 } else if (*high_speed_port_slots > actual_pgw_slots_required) { 1418 lr_idx_limit = *high_speed_port_slots; 1419 } 1420 _tdm->_chip_data.soc_pkg.soc_vars.mn.pgw1_len = lr_idx_limit; 1421 break; 1422 case 800: case 720: case 460: 1423 lr_idx_limit= ((_tdm->_chip_data.soc_pkg.soc_vars.mn.sku_core_bw)/(TDM_SLOT_UNIT_5G/1000))/2; 1424 actual_pgw_slots_required = lr_idx_limit; 1425 if(actual_pgw_slots_required == *high_speed_port_slots) { 1426 lr_idx_limit = actual_pgw_slots_required; 1427 } else if (actual_pgw_slots_required > *high_speed_port_slots) { 1428 lr_idx_limit = actual_pgw_slots_required; 1429 } else if (*high_speed_port_slots > actual_pgw_slots_required) { 1430 lr_idx_limit = *high_speed_port_slots; 1431 } 1432 _tdm->_core_data.vars_pkg.pipe_info.slot_unit = TDM_SLOT_UNIT_5G; 1433 _tdm->_chip_data.soc_pkg.soc_vars.mn.pgw1_len = lr_idx_limit; 1434 break; 1435 } 1436 break; 1437 case 818: 1438 lr_idx_limit=160; 1439 actual_pgw_slots_required = lr_idx_limit; 1440 if(actual_pgw_slots_required == *high_speed_port_slots) { 1441 lr_idx_limit = actual_pgw_slots_required; 1442 } else if (actual_pgw_slots_required > *high_speed_port_slots) { 1443 lr_idx_limit = actual_pgw_slots_required; 1444 } else if (*high_speed_port_slots > actual_pgw_slots_required) { 1445 lr_idx_limit = *high_speed_port_slots; 1446 } 1447 _tdm->_chip_data.soc_pkg.soc_vars.mn.pgw1_len = lr_idx_limit; 1448 break; 1449 case 819: 1450 lr_idx_limit=128; 1451 actual_pgw_slots_required = lr_idx_limit; 1452 if(actual_pgw_slots_required == *high_speed_port_slots) { 1453 lr_idx_limit = actual_pgw_slots_required; 1454 } else if (actual_pgw_slots_required > *high_speed_port_slots) { 1455 lr_idx_limit = actual_pgw_slots_required; 1456 } else if (*high_speed_port_slots > actual_pgw_slots_required) { 1457 lr_idx_limit = *high_speed_port_slots; 1458 } 1459 _tdm->_chip_data.soc_pkg.soc_vars.mn.pgw1_len = lr_idx_limit; 1460 break; 1461 case 820: 1462 lr_idx_limit=152; 1463 actual_pgw_slots_required = lr_idx_limit; 1464 if(actual_pgw_slots_required == *high_speed_port_slots) { 1465 lr_idx_limit = actual_pgw_slots_required; 1466 } else if (actual_pgw_slots_required > *high_speed_port_slots) { 1467 lr_idx_limit = actual_pgw_slots_required; 1468 } else if (*high_speed_port_slots > actual_pgw_slots_required) { 1469 lr_idx_limit = *high_speed_port_slots; 1470 } 1471 _tdm->_chip_data.soc_pkg.soc_vars.mn.pgw1_len = lr_idx_limit; 1472 break; 1473 case 861: case 862: 1474 lr_idx_limit=48; 1475 actual_pgw_slots_required = lr_idx_limit; 1476 if(actual_pgw_slots_required == *high_speed_port_slots) { 1477 lr_idx_limit = actual_pgw_slots_required; 1478 } else if (actual_pgw_slots_required > *high_speed_port_slots) { 1479 lr_idx_limit = actual_pgw_slots_required; 1480 } else if (*high_speed_port_slots > actual_pgw_slots_required) { 1481 lr_idx_limit = *high_speed_port_slots; 1482 } 1483 _tdm->_chip_data.soc_pkg.soc_vars.mn.pgw1_len = lr_idx_limit; 1484 break; 1485 case 550: 1486 switch (_tdm->_chip_data.soc_pkg.soc_vars.mn.sku_core_bw) { 1487 case 0: 1488 lr_idx_limit=80; 1489 _tdm->_chip_data.soc_pkg.soc_vars.mn.pgw1_len = lr_idx_limit; 1490 break; 1491 case 580: case 460: case 280: case 400: 1492 lr_idx_limit= ((_tdm->_chip_data.soc_pkg.soc_vars.mn.sku_core_bw)/(TDM_SLOT_UNIT_5G/1000))/2; 1493 actual_pgw_slots_required = lr_idx_limit; 1494 if(actual_pgw_slots_required == *high_speed_port_slots) { 1495 lr_idx_limit = actual_pgw_slots_required; 1496 } else if (actual_pgw_slots_required > *high_speed_port_slots) { 1497 lr_idx_limit = actual_pgw_slots_required; 1498 } else if (*high_speed_port_slots > actual_pgw_slots_required) { 1499 lr_idx_limit = *high_speed_port_slots; 1500 } 1501 _tdm->_core_data.vars_pkg.pipe_info.slot_unit = TDM_SLOT_UNIT_5G; 1502 _tdm->_chip_data.soc_pkg.soc_vars.mn.pgw1_len = lr_idx_limit; 1503 break; 1504 } 1505 break; 1506 default : break; 1507 } 1508 if(_tdm->_chip_data.soc_pkg.clk_freq != 861 && _tdm->_chip_data.soc_pkg.clk_freq != 862){ 1509 for (idx1=0; idx1<TDM_AUX_SIZE; idx1++) { 1510 _tdm->_core_data.vars_pkg.lr_buffer[idx1]=MN_NUM_EXT_PORTS; 1511 _tdm->_core_data.vars_pkg.os_buffer[idx1]=MN_NUM_EXT_PORTS; 1512 } 1513 /* higig_mgmt */ 1514 if ( (_tdm->_chip_data.soc_pkg.soc_vars.mn.pm_encap_type[MN_NUM_PHY_PM]==PM_ENCAP__HIGIG2 /* && (pipe==1||pipe==2)*/) && 1515 ((_tdm->_core_data.vars_pkg.lr_buffer[0]!=MN_NUM_EXT_PORTS && _tdm->_chip_data.soc_pkg.clk_freq>=MIN_HG_FREQ) || (_tdm->_core_data.vars_pkg.lr_buffer[0]==MN_NUM_EXT_PORTS)) ) { 1516 higig_mgmt=BOOL_TRUE; 1517 } 1518 pgw_io_bw = 0.0; 1519 tdm_mn_cal_pgw_bw(_tdm, &pgw_io_bw, i, high_speed_port_slots); 1520 _tdm->_chip_data.soc_pkg.soc_vars.mn.mntry_pgw1_io_bw = pgw_io_bw; 1521 _tdm->_core_data.vars_pkg.cal_id=1; 1522 _tdm->_chip_data.soc_pkg.tvec_size = 0; 1523 /*_tdm->_chip_data.soc_pkg.lr_idx_limit= (int) (pgw_io_bw/MN_PGW_PER_SLOT_IO_BW);*/ 1524 _tdm->_chip_data.soc_pkg.lr_idx_limit= lr_idx_limit; 1525 for (idx1=0; idx1<TDM_AUX_SIZE; idx1++) { 1526 _tdm->_core_data.vars_pkg.os_buffer[idx1]=MN_NUM_EXT_PORTS; 1527 } 1528 j=0; 1529 for (idx1=(i*(MN_NUM_PHY_PORTS/MN_NUM_QUAD))+1; idx1<=( (i+1) *(MN_NUM_PHY_PORTS/MN_NUM_QUAD) ); idx1++) { 1530 if((_tdm->_chip_data.soc_pkg.state[(idx1-1)] == PORT_STATE__LINERATE || 1531 _tdm->_chip_data.soc_pkg.state[(idx1-1)] == PORT_STATE__LINERATE_HG) && 1532 (_tdm->_chip_data.soc_pkg.speed[(idx1)] > SPEED_0) 1533 ){ 1534 _tdm->_core_data.vars_pkg.lr_buffer[j++]= (idx1); 1535 } 1536 } 1537 /* allocate Linerate slots: vmap pre-allocation */ 1538 if(_tdm->_core_exec[TDM_CORE_EXEC__VMAP_PREALLOC](_tdm)!=PASS){ 1539 /*result = FAIL;*/ 1540 } 1541 /* allocate Linerate slots: vmap allocation */ 1542 else if(_tdm->_core_exec[TDM_CORE_EXEC__VMAP_ALLOC](_tdm)!=PASS){ 1543 /*result = FAIL;*/ 1544 } 1545 for(loop =0; loop<MN_LR_LLS_LEN; loop++) { 1546 pgw_tdm_tbl1[loop] = _tdm->_chip_data.cal_1.cal_main[loop]; 1547 } 1548 TDM_PRINT0("\n==================== Monterey PGW-1 TDM Calendar ==================\n"); 1549 tdm_mn_tdm_print(_tdm->_chip_data.cal_1.cal_main, MN_LR_LLS_LEN); 1550 TDM_PRINT0("\n==================== Monterey PGW-1 TDM Calendar ==================\n"); 1551 } 1552 break; 1553 } 1554 case 2: 1555 _tdm->_core_data.rule__prox_port_min = MN_MIN_SPACING_SISTER_PORT; 1556 if ( (tdm_mn_check_ethernet(_tdm)) && (higig_mgmt==BOOL_FALSE)){ 1557 switch (_tdm->_chip_data.soc_pkg.clk_freq) { 1558 case 815: 1559 acc=(MN_ACC_PORT_NUM+15); 1560 lr_idx_limit=(MN_LEN_815MHZ_EN-acc); 1561 _tdm->_chip_data.soc_pkg.soc_vars.mn.mmu_len = MN_LEN_815MHZ_EN; 1562 break; 1563 case 666: 1564 acc=(16); 1565 lr_idx_limit=(MN_LEN_666MHZ_EN-acc); 1566 _tdm->_core_data.vars_pkg.pipe_info.slot_unit = TDM_SLOT_UNIT_5G; 1567 _tdm->_chip_data.soc_pkg.soc_vars.mn.mmu_len = MN_LEN_666MHZ_EN; 1568 break; 1569 case 667: 1570 switch(_tdm->_chip_data.soc_pkg.soc_vars.mn.sku_core_bw) { 1571 case 0: 1572 acc=(16); 1573 lr_idx_limit=(MN_LEN_667MHZ_EN-acc); 1574 _tdm->_core_data.vars_pkg.pipe_info.slot_unit = TDM_SLOT_UNIT_5G; 1575 _tdm->_chip_data.soc_pkg.soc_vars.mn.mmu_len = MN_LEN_667MHZ_EN; 1576 break; 1577 case 720: case 580: 1578 acc = 15; 1579 lr_idx_limit= ((_tdm->_chip_data.soc_pkg.soc_vars.mn.sku_core_bw)/(TDM_SLOT_UNIT_5G/1000)); 1580 _tdm->_core_data.vars_pkg.pipe_info.slot_unit = TDM_SLOT_UNIT_5G; 1581 _tdm->_chip_data.soc_pkg.soc_vars.mn.mmu_len = lr_idx_limit + acc; 1582 break; 1583 case 360: case 400: 1584 acc = 14; 1585 lr_idx_limit= ((_tdm->_chip_data.soc_pkg.soc_vars.mn.sku_core_bw)/(TDM_SLOT_UNIT_5G/1000)); 1586 _tdm->_core_data.vars_pkg.pipe_info.slot_unit = TDM_SLOT_UNIT_5G; 1587 _tdm->_chip_data.soc_pkg.soc_vars.mn.mmu_len = lr_idx_limit + acc; 1588 break; 1589 case 380: case 420: 1590 if(_tdm->_chip_data.soc_pkg.soc_vars.mn.is_macsec == 1) { 1591 acc = 12; 1592 } else if(_tdm->_chip_data.soc_pkg.soc_vars.mn.is_macsec == 0) { 1593 acc = 4; 1594 } 1595 lr_idx_limit= ((_tdm->_chip_data.soc_pkg.soc_vars.mn.sku_core_bw)/(TDM_SLOT_UNIT_5G/1000)); 1596 _tdm->_core_data.vars_pkg.pipe_info.slot_unit = TDM_SLOT_UNIT_5G; 1597 _tdm->_chip_data.soc_pkg.soc_vars.mn.mmu_len = lr_idx_limit+acc; 1598 break; 1599 } 1600 break; 1601 case 816: 1602 acc=(MN_ACC_PORT_NUM); 1603 lr_idx_limit=(MN_LEN_816MHZ_EN-acc); 1604 _tdm->_chip_data.soc_pkg.soc_vars.mn.mmu_len = MN_LEN_816MHZ_EN; 1605 break; 1606 case 450: 1607 switch (_tdm->_chip_data.soc_pkg.soc_vars.mn.sku_core_bw) { 1608 case 460: case 360: case 400: 1609 acc = 15; 1610 lr_idx_limit= ((_tdm->_chip_data.soc_pkg.soc_vars.mn.sku_core_bw)/(TDM_SLOT_UNIT_5G/1000)); 1611 _tdm->_core_data.vars_pkg.pipe_info.slot_unit = TDM_SLOT_UNIT_5G; 1612 _tdm->_chip_data.soc_pkg.soc_vars.mn.mmu_len = lr_idx_limit+acc; 1613 break; 1614 case 200: 1615 acc = 14; 1616 lr_idx_limit= ((_tdm->_chip_data.soc_pkg.soc_vars.mn.sku_core_bw)/(TDM_SLOT_UNIT_5G/1000)); 1617 _tdm->_core_data.vars_pkg.pipe_info.slot_unit = TDM_SLOT_UNIT_5G; 1618 _tdm->_chip_data.soc_pkg.soc_vars.mn.mmu_len = lr_idx_limit+acc; 1619 break; 1620 case 235: case 275: 1621 if(_tdm->_chip_data.soc_pkg.soc_vars.mn.is_macsec == 1) { 1622 acc = 12; 1623 } else if(_tdm->_chip_data.soc_pkg.soc_vars.mn.is_macsec == 0) { 1624 acc = 4; 1625 } 1626 lr_idx_limit= ((_tdm->_chip_data.soc_pkg.soc_vars.mn.sku_core_bw)/(TDM_SLOT_UNIT_5G/1000)); 1627 _tdm->_core_data.vars_pkg.pipe_info.slot_unit = TDM_SLOT_UNIT_5G; 1628 _tdm->_chip_data.soc_pkg.soc_vars.mn.mmu_len = lr_idx_limit+acc; 1629 break; 1630 } 1631 break; 1632 case 817: 1633 switch (_tdm->_chip_data.soc_pkg.soc_vars.mn.sku_core_bw) { 1634 case 0: 1635 acc=(MN_ACC_PORT_NUM-1); 1636 lr_idx_limit=(MN_LEN_817MHZ_EN-acc); 1637 _tdm->_chip_data.soc_pkg.soc_vars.mn.mmu_len = MN_LEN_817MHZ_EN; 1638 break; 1639 case 800: case 720: 1640 acc = 15; 1641 lr_idx_limit= ((_tdm->_chip_data.soc_pkg.soc_vars.mn.sku_core_bw)/(TDM_SLOT_UNIT_5G/1000)); 1642 _tdm->_core_data.vars_pkg.pipe_info.slot_unit = TDM_SLOT_UNIT_5G; 1643 _tdm->_chip_data.soc_pkg.soc_vars.mn.mmu_len = lr_idx_limit+acc; 1644 break; 1645 case 460: 1646 acc = 14; 1647 lr_idx_limit= ((_tdm->_chip_data.soc_pkg.soc_vars.mn.sku_core_bw)/(TDM_SLOT_UNIT_5G/1000)); 1648 _tdm->_core_data.vars_pkg.pipe_info.slot_unit = TDM_SLOT_UNIT_5G; 1649 _tdm->_chip_data.soc_pkg.soc_vars.mn.mmu_len = lr_idx_limit+acc; 1650 break; 1651 case 475: case 515: 1652 if(_tdm->_chip_data.soc_pkg.soc_vars.mn.is_macsec == 1) { 1653 acc = 12; 1654 } else if(_tdm->_chip_data.soc_pkg.soc_vars.mn.is_macsec == 0) { 1655 acc = 4; 1656 } 1657 lr_idx_limit= ((_tdm->_chip_data.soc_pkg.soc_vars.mn.sku_core_bw)/(TDM_SLOT_UNIT_5G/1000)); 1658 _tdm->_core_data.vars_pkg.pipe_info.slot_unit = TDM_SLOT_UNIT_5G; 1659 _tdm->_chip_data.soc_pkg.soc_vars.mn.mmu_len = lr_idx_limit+acc; 1660 break; 1661 } 1662 break; 1663 case 818: 1664 acc=(MN_ACC_PORT_NUM); 1665 lr_idx_limit=(MN_LEN_818MHZ_EN-acc); 1666 _tdm->_chip_data.soc_pkg.soc_vars.mn.mmu_len = MN_LEN_818MHZ_EN; 1667 break; 1668 case 819: 1669 acc=(MN_ACC_PORT_NUM+13); 1670 lr_idx_limit=(MN_LEN_819MHZ_EN-acc); 1671 _tdm->_chip_data.soc_pkg.soc_vars.mn.mmu_len = MN_LEN_819MHZ_EN; 1672 break; 1673 case 820: 1674 acc=(MN_ACC_PORT_NUM+17); 1675 lr_idx_limit=(MN_LEN_820MHZ_EN-acc); 1676 _tdm->_chip_data.soc_pkg.soc_vars.mn.mmu_len = MN_LEN_820MHZ_EN; 1677 break; 1678 case 861: case 862: 1679 switch (_tdm->_chip_data.soc_pkg.soc_vars.mn.sku_core_bw) { 1680 case 0: 1681 acc=(MN_ACC_PORT_NUM-9); 1682 lr_idx_limit=(MN_LEN_861MHZ_EN-acc); 1683 _tdm->_chip_data.soc_pkg.soc_vars.mn.mmu_len = MN_LEN_861MHZ_EN; 1684 break; 1685 case 800: 1686 acc=(MN_ACC_PORT_NUM-6); 1687 _tdm->_core_data.vars_pkg.pipe_info.slot_unit = TDM_SLOT_UNIT_2P5G; 1688 lr_idx_limit=(MN_LEN_862MHZ_EN-acc); 1689 _tdm->_chip_data.soc_pkg.soc_vars.mn.mmu_len = MN_LEN_862MHZ_EN; 1690 break; 1691 case 548: case 508: 1692 if(_tdm->_chip_data.soc_pkg.soc_vars.mn.is_macsec == 1) { 1693 acc = 24; 1694 } else if(_tdm->_chip_data.soc_pkg.soc_vars.mn.is_macsec == 0) { 1695 acc = 8; 1696 } 1697 lr_idx_limit= (((_tdm->_chip_data.soc_pkg.soc_vars.mn.sku_core_bw*1000)/TDM_SLOT_UNIT_2P5G)); 1698 _tdm->_chip_data.soc_pkg.soc_vars.mn.mmu_len = lr_idx_limit+acc; 1699 break; 1700 1701 } 1702 break; 1703 case 550: 1704 switch (_tdm->_chip_data.soc_pkg.soc_vars.mn.sku_core_bw) { 1705 case 0: 1706 acc=(MN_ACC_PORT_NUM+15); 1707 lr_idx_limit=(MN_LEN_550MHZ_EN-acc); 1708 _tdm->_chip_data.soc_pkg.soc_vars.mn.mmu_len = MN_LEN_550MHZ_EN; 1709 break; 1710 case 580: case 460: case 400: 1711 acc = 15; 1712 lr_idx_limit= ((_tdm->_chip_data.soc_pkg.soc_vars.mn.sku_core_bw)/(TDM_SLOT_UNIT_5G/1000)); 1713 _tdm->_core_data.vars_pkg.pipe_info.slot_unit = TDM_SLOT_UNIT_5G; 1714 _tdm->_chip_data.soc_pkg.soc_vars.mn.mmu_len = lr_idx_limit+acc; 1715 break; 1716 case 280: 1717 acc = 14; 1718 lr_idx_limit= ((_tdm->_chip_data.soc_pkg.soc_vars.mn.sku_core_bw)/(TDM_SLOT_UNIT_5G/1000)); 1719 _tdm->_core_data.vars_pkg.pipe_info.slot_unit = TDM_SLOT_UNIT_5G; 1720 _tdm->_chip_data.soc_pkg.soc_vars.mn.mmu_len = lr_idx_limit+acc; 1721 break; 1722 /*case 400: 1723 acc = 8; 1724 lr_idx_limit= ((_tdm->_chip_data.soc_pkg.soc_vars.mn.sku_core_bw)/(TDM_SLOT_UNIT_5G/1000)); 1725 _tdm->_core_data.vars_pkg.pipe_info.slot_unit = TDM_SLOT_UNIT_5G; 1726 _tdm->_chip_data.soc_pkg.soc_vars.mn.mmu_len = lr_idx_limit+acc; 1727 break;*/ 1728 case 300: case 340: 1729 if(_tdm->_chip_data.soc_pkg.soc_vars.mn.is_macsec == 1) { 1730 acc = 12; 1731 } else if(_tdm->_chip_data.soc_pkg.soc_vars.mn.is_macsec == 0) { 1732 acc = 4; 1733 } 1734 lr_idx_limit= ((_tdm->_chip_data.soc_pkg.soc_vars.mn.sku_core_bw)/(TDM_SLOT_UNIT_5G/1000)); 1735 _tdm->_core_data.vars_pkg.pipe_info.slot_unit = TDM_SLOT_UNIT_5G; 1736 _tdm->_chip_data.soc_pkg.soc_vars.mn.mmu_len = lr_idx_limit+acc; 1737 break; 1738 } 1739 break; 1740 default : break; 1741 } 1742 } else { 1743 switch (_tdm->_chip_data.soc_pkg.clk_freq) { 1744 case 815: 1745 acc=(MN_ACC_PORT_NUM+15); 1746 lr_idx_limit=(MN_LEN_815MHZ_EN-acc); 1747 _tdm->_chip_data.soc_pkg.soc_vars.mn.mmu_len = MN_LEN_815MHZ_EN; 1748 break; 1749 case 666: 1750 acc=(16); 1751 lr_idx_limit=(MN_LEN_666MHZ_EN-acc); 1752 _tdm->_core_data.vars_pkg.pipe_info.slot_unit = TDM_SLOT_UNIT_5G; 1753 _tdm->_chip_data.soc_pkg.soc_vars.mn.mmu_len = MN_LEN_666MHZ_EN; 1754 break; 1755 case 667: 1756 switch(_tdm->_chip_data.soc_pkg.soc_vars.mn.sku_core_bw) { 1757 case 0: 1758 acc=(16); 1759 lr_idx_limit=(MN_LEN_667MHZ_EN-acc); 1760 _tdm->_core_data.vars_pkg.pipe_info.slot_unit = TDM_SLOT_UNIT_5G; 1761 _tdm->_chip_data.soc_pkg.soc_vars.mn.mmu_len = MN_LEN_667MHZ_EN; 1762 break; 1763 case 720: case 580: 1764 acc = 15; 1765 lr_idx_limit= ((_tdm->_chip_data.soc_pkg.soc_vars.mn.sku_core_bw)/(TDM_SLOT_UNIT_5G/1000)); 1766 _tdm->_core_data.vars_pkg.pipe_info.slot_unit = TDM_SLOT_UNIT_5G; 1767 _tdm->_chip_data.soc_pkg.soc_vars.mn.mmu_len = lr_idx_limit + acc; 1768 break; 1769 case 360: case 400: 1770 acc = 14; 1771 lr_idx_limit= ((_tdm->_chip_data.soc_pkg.soc_vars.mn.sku_core_bw)/(TDM_SLOT_UNIT_5G/1000)); 1772 _tdm->_core_data.vars_pkg.pipe_info.slot_unit = TDM_SLOT_UNIT_5G; 1773 _tdm->_chip_data.soc_pkg.soc_vars.mn.mmu_len = lr_idx_limit + acc; 1774 break; 1775 case 380: case 420: 1776 if(_tdm->_chip_data.soc_pkg.soc_vars.mn.is_macsec == 1) { 1777 acc = 12; 1778 } else if(_tdm->_chip_data.soc_pkg.soc_vars.mn.is_macsec == 0) { 1779 acc = 4; 1780 } 1781 lr_idx_limit= ((_tdm->_chip_data.soc_pkg.soc_vars.mn.sku_core_bw)/(TDM_SLOT_UNIT_5G/1000)); 1782 _tdm->_core_data.vars_pkg.pipe_info.slot_unit = TDM_SLOT_UNIT_5G; 1783 _tdm->_chip_data.soc_pkg.soc_vars.mn.mmu_len = lr_idx_limit+acc; 1784 break; 1785 } 1786 break; 1787 case 816: 1788 acc=(MN_ACC_PORT_NUM); 1789 lr_idx_limit=(MN_LEN_816MHZ_EN-acc); 1790 _tdm->_chip_data.soc_pkg.soc_vars.mn.mmu_len = MN_LEN_816MHZ_EN; 1791 break; 1792 case 450: 1793 switch (_tdm->_chip_data.soc_pkg.soc_vars.mn.sku_core_bw) { 1794 case 460: case 360: 1795 acc = 15; 1796 lr_idx_limit= ((_tdm->_chip_data.soc_pkg.soc_vars.mn.sku_core_bw)/(TDM_SLOT_UNIT_5G/1000)); 1797 _tdm->_core_data.vars_pkg.pipe_info.slot_unit = TDM_SLOT_UNIT_5G; 1798 _tdm->_chip_data.soc_pkg.soc_vars.mn.mmu_len = lr_idx_limit+acc; 1799 break; 1800 case 200: 1801 acc = 14; 1802 lr_idx_limit= ((_tdm->_chip_data.soc_pkg.soc_vars.mn.sku_core_bw)/(TDM_SLOT_UNIT_5G/1000)); 1803 _tdm->_core_data.vars_pkg.pipe_info.slot_unit = TDM_SLOT_UNIT_5G; 1804 _tdm->_chip_data.soc_pkg.soc_vars.mn.mmu_len = lr_idx_limit+acc; 1805 break; 1806 case 235: case 275: 1807 if(_tdm->_chip_data.soc_pkg.soc_vars.mn.is_macsec == 1) { 1808 acc = 12; 1809 } else if(_tdm->_chip_data.soc_pkg.soc_vars.mn.is_macsec == 0) { 1810 acc = 4; 1811 } 1812 lr_idx_limit= ((_tdm->_chip_data.soc_pkg.soc_vars.mn.sku_core_bw)/(TDM_SLOT_UNIT_5G/1000)); 1813 _tdm->_core_data.vars_pkg.pipe_info.slot_unit = TDM_SLOT_UNIT_5G; 1814 _tdm->_chip_data.soc_pkg.soc_vars.mn.mmu_len = lr_idx_limit+acc; 1815 break; 1816 } 1817 break; 1818 case 817: 1819 switch (_tdm->_chip_data.soc_pkg.soc_vars.mn.sku_core_bw) { 1820 case 0: 1821 acc=(MN_ACC_PORT_NUM-1); 1822 lr_idx_limit=(MN_LEN_817MHZ_EN-acc); 1823 _tdm->_chip_data.soc_pkg.soc_vars.mn.mmu_len = MN_LEN_817MHZ_EN; 1824 break; 1825 case 800: case 720: 1826 acc = 15; 1827 lr_idx_limit= ((_tdm->_chip_data.soc_pkg.soc_vars.mn.sku_core_bw)/(TDM_SLOT_UNIT_5G/1000)); 1828 _tdm->_core_data.vars_pkg.pipe_info.slot_unit = TDM_SLOT_UNIT_5G; 1829 _tdm->_chip_data.soc_pkg.soc_vars.mn.mmu_len = lr_idx_limit+acc; 1830 break; 1831 case 460: 1832 acc = 14; 1833 lr_idx_limit= ((_tdm->_chip_data.soc_pkg.soc_vars.mn.sku_core_bw)/(TDM_SLOT_UNIT_5G/1000)); 1834 _tdm->_core_data.vars_pkg.pipe_info.slot_unit = TDM_SLOT_UNIT_5G; 1835 _tdm->_chip_data.soc_pkg.soc_vars.mn.mmu_len = lr_idx_limit+acc; 1836 break; 1837 case 475: case 515: 1838 if(_tdm->_chip_data.soc_pkg.soc_vars.mn.is_macsec == 1) { 1839 acc = 12; 1840 } else if(_tdm->_chip_data.soc_pkg.soc_vars.mn.is_macsec == 0) { 1841 acc = 4; 1842 } 1843 lr_idx_limit= ((_tdm->_chip_data.soc_pkg.soc_vars.mn.sku_core_bw)/(TDM_SLOT_UNIT_5G/1000)); 1844 _tdm->_core_data.vars_pkg.pipe_info.slot_unit = TDM_SLOT_UNIT_5G; 1845 _tdm->_chip_data.soc_pkg.soc_vars.mn.mmu_len = lr_idx_limit+acc; 1846 break; 1847 } 1848 break; 1849 case 818: 1850 acc=(MN_ACC_PORT_NUM); 1851 lr_idx_limit=(MN_LEN_818MHZ_EN-acc); 1852 _tdm->_chip_data.soc_pkg.soc_vars.mn.mmu_len = MN_LEN_818MHZ_EN; 1853 break; 1854 case 819: 1855 acc=(MN_ACC_PORT_NUM+13); 1856 lr_idx_limit=(MN_LEN_819MHZ_EN-acc); 1857 _tdm->_chip_data.soc_pkg.soc_vars.mn.mmu_len = MN_LEN_819MHZ_EN; 1858 break; 1859 case 820: 1860 acc=(MN_ACC_PORT_NUM+17); 1861 lr_idx_limit=(MN_LEN_820MHZ_EN-acc); 1862 _tdm->_chip_data.soc_pkg.soc_vars.mn.mmu_len = MN_LEN_820MHZ_EN; 1863 break; 1864 case 861: case 862: 1865 switch (_tdm->_chip_data.soc_pkg.soc_vars.mn.sku_core_bw) { 1866 case 0: 1867 acc=(MN_ACC_PORT_NUM-9); 1868 lr_idx_limit=(MN_LEN_861MHZ_EN-acc); 1869 _tdm->_chip_data.soc_pkg.soc_vars.mn.mmu_len = MN_LEN_861MHZ_EN; 1870 break; 1871 case 800: 1872 acc=(MN_ACC_PORT_NUM-6); 1873 _tdm->_core_data.vars_pkg.pipe_info.slot_unit = TDM_SLOT_UNIT_2P5G; 1874 lr_idx_limit=(MN_LEN_862MHZ_EN-acc); 1875 _tdm->_chip_data.soc_pkg.soc_vars.mn.mmu_len = MN_LEN_862MHZ_EN; 1876 break; 1877 case 548: case 508: 1878 if(_tdm->_chip_data.soc_pkg.soc_vars.mn.is_macsec == 1) { 1879 acc = 24; 1880 } else if(_tdm->_chip_data.soc_pkg.soc_vars.mn.is_macsec == 0) { 1881 acc = 8; 1882 } 1883 lr_idx_limit= (((_tdm->_chip_data.soc_pkg.soc_vars.mn.sku_core_bw*1000)/TDM_SLOT_UNIT_2P5G)); 1884 _tdm->_chip_data.soc_pkg.soc_vars.mn.mmu_len = lr_idx_limit+acc; 1885 break; 1886 break; 1887 } 1888 break; 1889 case 550: 1890 switch (_tdm->_chip_data.soc_pkg.soc_vars.mn.sku_core_bw) { 1891 case 0: 1892 acc=(MN_ACC_PORT_NUM+15); 1893 lr_idx_limit=(MN_LEN_550MHZ_EN-acc); 1894 _tdm->_chip_data.soc_pkg.soc_vars.mn.mmu_len = MN_LEN_550MHZ_EN; 1895 break; 1896 case 580: case 460: case 400: 1897 acc = 15; 1898 lr_idx_limit= ((_tdm->_chip_data.soc_pkg.soc_vars.mn.sku_core_bw)/(TDM_SLOT_UNIT_5G/1000)); 1899 _tdm->_core_data.vars_pkg.pipe_info.slot_unit = TDM_SLOT_UNIT_5G; 1900 _tdm->_chip_data.soc_pkg.soc_vars.mn.mmu_len = lr_idx_limit+acc; 1901 break; 1902 case 280: 1903 acc = 14; 1904 lr_idx_limit= ((_tdm->_chip_data.soc_pkg.soc_vars.mn.sku_core_bw)/(TDM_SLOT_UNIT_5G/1000)); 1905 _tdm->_core_data.vars_pkg.pipe_info.slot_unit = TDM_SLOT_UNIT_5G; 1906 _tdm->_chip_data.soc_pkg.soc_vars.mn.mmu_len = lr_idx_limit+acc; 1907 break; 1908 /*case 400: 1909 acc = 8; 1910 lr_idx_limit= ((_tdm->_chip_data.soc_pkg.soc_vars.mn.sku_core_bw)/(TDM_SLOT_UNIT_5G/1000)); 1911 _tdm->_core_data.vars_pkg.pipe_info.slot_unit = TDM_SLOT_UNIT_5G; 1912 _tdm->_chip_data.soc_pkg.soc_vars.mn.mmu_len = lr_idx_limit+acc; 1913 break;*/ 1914 case 300: case 340: 1915 if(_tdm->_chip_data.soc_pkg.soc_vars.mn.is_macsec == 1) { 1916 acc = 12; 1917 } else if(_tdm->_chip_data.soc_pkg.soc_vars.mn.is_macsec == 0) { 1918 acc = 4; 1919 } 1920 lr_idx_limit= ((_tdm->_chip_data.soc_pkg.soc_vars.mn.sku_core_bw)/(TDM_SLOT_UNIT_5G/1000)); 1921 _tdm->_core_data.vars_pkg.pipe_info.slot_unit = TDM_SLOT_UNIT_5G; 1922 _tdm->_chip_data.soc_pkg.soc_vars.mn.mmu_len = lr_idx_limit+acc; 1923 break; 1924 } 1925 break; 1926 default : break; 1927 } 1928 } 1929 _tdm->_core_data.vars_pkg.cal_id=2; 1930 _tdm->_chip_data.soc_pkg.tvec_size = acc; 1931 _tdm->_chip_data.soc_pkg.lr_idx_limit= lr_idx_limit; 1932 _tdm->_chip_data.soc_pkg.soc_vars.mn.pipe_start= 1; 1933 _tdm->_chip_data.soc_pkg.soc_vars.mn.pipe_end = MN_NUM_PHY_PORTS; 1934 for(k =0; k<TDM_AUX_SIZE; k++) { 1935 _tdm->_core_data.vars_pkg.lr_buffer[k]= MN_NUM_EXT_PORTS; 1936 } 1937 for (idx1=0; idx1<TDM_AUX_SIZE; idx1++) { 1938 _tdm->_core_data.vars_pkg.os_buffer[idx1]=MN_NUM_EXT_PORTS; 1939 } 1940 j=0; 1941 for (idx1=1; idx1<=MN_NUM_PHY_PORTS; idx1++) { 1942 if(_tdm->_chip_data.soc_pkg.state[idx1-1] == PORT_STATE__LINERATE || 1943 _tdm->_chip_data.soc_pkg.state[idx1-1] == PORT_STATE__LINERATE_HG 1944 ){ 1945 _tdm->_core_data.vars_pkg.lr_buffer[j++]= (idx1); 1946 } 1947 } 1948 j=0; 1949 for (idx1=0; idx1<(MN_NUM_PHY_PORTS+1); idx1++) { 1950 if(_tdm->_chip_data.soc_pkg.state[idx1-1] == PORT_STATE__OVERSUB || 1951 _tdm->_chip_data.soc_pkg.state[idx1-1] == PORT_STATE__OVERSUB_HG 1952 ){ 1953 _tdm->_core_data.vars_pkg.os_buffer[j++]= (idx1); 1954 } 1955 } 1956 /* allocate Linerate slots: vmap pre-allocation */ 1957 if(_tdm->_core_exec[TDM_CORE_EXEC__VMAP_PREALLOC](_tdm)!=PASS){ 1958 result = FAIL; 1959 } 1960 /* allocate Linerate slots: vmap allocation */ 1961 else if(_tdm->_core_exec[TDM_CORE_EXEC__VMAP_ALLOC](_tdm)!=PASS){ 1962 result = FAIL; 1963 } 1964 TDM_PRINT0("==================== Monterey MMU TDM Calendar =================="); 1965 tdm_mn_tdm_print(_tdm->_chip_data.cal_2.cal_main, (lr_idx_limit+acc)); 1966 break; 1967 } 1968 } 1969 if(_tdm->_chip_data.soc_pkg.clk_freq != 861 && _tdm->_chip_data.soc_pkg.clk_freq != 862){ 1970 for(i =0; i<MN_LR_LLS_LEN; i++) { 1971 if(pgw_tdm_tbl0[i] == MN_NUM_EXT_PORTS) break; 1972 else { 1973 _tdm->_chip_data.cal_0.cal_main[i] = pgw_tdm_tbl0[i]; 1974 } 1975 } 1976 for(i =0; i<MN_LR_LLS_LEN; i++) { 1977 if(pgw_tdm_tbl1[i] == MN_NUM_EXT_PORTS) break; 1978 else { 1979 _tdm->_chip_data.cal_1.cal_main[i] = pgw_tdm_tbl1[i]; 1980 } 1981 } 1982 } 1983 /*if(_tdm->_chip_data.soc_pkg.clk_freq == 817){ 1984 tdm_mn_custom_post_process_pgw(_tdm); 1985 tdm_mn_custom_post_process_mmu(_tdm); 1986 tdm_mn_custom_restore_vars(_tdm); 1987 }*/ 1988 if(_tdm->_chip_data.soc_pkg.clk_freq == 816 || 1989 _tdm->_chip_data.soc_pkg.clk_freq == 817 || 1990 _tdm->_chip_data.soc_pkg.clk_freq == 818 1991 ){ 1992 tdm_mn_tdm_smooth(_tdm); 1993 } 1994 TDM_FREE(high_speed_port_slots); 1995 1996 return result; 1997 } 1998 /* 1999 * tdm_mn_tdm_smooth(tdm_mod_t *_tdm) 2000 * This API smooths 40G and 10G ports in Flex scenario where Core layer is 2001 * inserting psuedo PM and introducing Jitter errors for 40G and 10G ports. 2002 * This API is used only for Customer-25G, CPRI-25G and other SKU's. 2003 * Check for min and max distance and if violated swap with idle token 2004 * already present in TDM from core layer. 2005 */ 2006 void tdm_mn_tdm_smooth(tdm_mod_t *_tdm) 2007 { 2008 int tdm_len = 0, loop = 0, idx=0, min_jitter_int=0, max_jitter_int=0, j=0, k=0; 2009 int min_jitter=0, max_jitter=0; 2010 int *tdm_cal=NULL, lr_spacing=0, wrap_arnd=0, idle_token_location=0; 2011 enum port_speed_e *port_speeds; 2012 int apply_correction=0, idle_cnt=0, i, idle_loc_array[MN_NUM_PHY_PORTS]; 2013 int ideal_spacing_roundup=0,ideal_spacing_rounddown=0, rem=0, jitter_range=0, min_spacing=0, max_spacing=0, port_slots=0; 2014 2015 port_speeds = _tdm->_chip_data.soc_pkg.speed; 2016 2017 for(i=0; i<MN_NUM_PHY_PORTS; i++) { 2018 idle_loc_array[i] = MN_NUM_EXT_PORTS; 2019 } 2020 for(k=0; k<3; k++) { 2021 for(j=0; j<3; j++) { 2022 switch(j){ 2023 case 0: 2024 tdm_cal = _tdm->_chip_data.cal_0.cal_main; 2025 tdm_len = _tdm->_chip_data.soc_pkg.soc_vars.mn.pgw0_len; 2026 break; 2027 case 1: 2028 tdm_cal = _tdm->_chip_data.cal_1.cal_main; 2029 tdm_len = _tdm->_chip_data.soc_pkg.soc_vars.mn.pgw1_len; 2030 break; 2031 case 2: 2032 tdm_cal = _tdm->_chip_data.cal_2.cal_main; 2033 tdm_len = _tdm->_chip_data.soc_pkg.soc_vars.mn.mmu_len; 2034 break; 2035 } 2036 lr_spacing=0; apply_correction=0;wrap_arnd=0;idle_token_location=0;idx=0;loop=0; 2037 for (loop=0; loop<tdm_len; loop++ ) { 2038 lr_spacing =0; 2039 MN_TOKEN_CHECK(tdm_cal[loop]) { 2040 if(port_speeds[tdm_cal[loop]] == SPEED_40G || 2041 (port_speeds[tdm_cal[loop]] == SPEED_10G ) || 2042 (port_speeds[tdm_cal[loop]] == SPEED_50G ) 2043 ){ 2044 switch(port_speeds[tdm_cal[loop]]){ 2045 case SPEED_10G: case SPEED_40G: case SPEED_50G: 2046 port_slots = tdm_cmn_get_speed_slots(_tdm, port_speeds[tdm_cal[loop]]); 2047 ideal_spacing_roundup = chk_tdm_roundup(tdm_len, port_slots); 2048 ideal_spacing_rounddown = chk_tdm_rounddown(tdm_len, port_slots); 2049 rem = tdm_len % port_slots; 2050 jitter_range = chk_tdm_round(2*tdm_len*30,port_slots*100); /* 30% from ideal_spacing 2*tabl_len*30/port_slots/100 */ 2051 2052 if(rem < ((port_slots+1)/2)) { 2053 min_spacing = ideal_spacing_rounddown - chk_tdm_rounddown(jitter_range, 2); /*ROUNDDOWN(ideal_spacing[port_speed],0) - ROUNDDOWN(range[port_speed]/2, 0);*/ 2054 max_spacing = ideal_spacing_rounddown + chk_tdm_roundup(jitter_range, 2); /*ROUNDDOWN(ideal_spacing[port_speed],0) + ROUNDUP(range[port_speed]/2, 0);*/ 2055 } else { 2056 min_spacing = ideal_spacing_roundup - chk_tdm_roundup(jitter_range,2); /*ROUNDUP(ideal_spacing[port_speed],0) - ROUNDUP(range[port_speed]/2, 0);*/ 2057 max_spacing = ideal_spacing_roundup + chk_tdm_rounddown(jitter_range,2); /*ROUNDUP(ideal_spacing[port_speed],0) + ROUNDDOWN(range[port_speed]/2, 0);*/ 2058 } 2059 min_jitter = min_spacing; 2060 max_jitter = max_spacing; 2061 min_jitter_int = (int) ( ((min_jitter*2)+1)/2 ); 2062 max_jitter_int = (int) ( ((max_jitter*2)+1)/2 ); 2063 break; 2064 default: break; 2065 } 2066 idle_cnt = 0; 2067 for (idx=loop+1, wrap_arnd=0; idx<=tdm_len && wrap_arnd<2; idx++ ) { 2068 apply_correction = 0; 2069 if (idx == tdm_len) { 2070 idx = -1; wrap_arnd++; continue; 2071 } 2072 lr_spacing++; 2073 if(lr_spacing >= min_jitter_int && lr_spacing <= max_jitter_int){ 2074 if(tdm_cal[idx] == MN_NUM_EXT_PORTS){ 2075 idle_loc_array[idle_cnt] = loop +(idx-loop); 2076 idle_cnt++; 2077 } 2078 idle_token_location = idle_loc_array[(idle_cnt-1)]; 2079 } 2080 if (tdm_cal[loop] == tdm_cal[idx]) { 2081 if(lr_spacing >max_jitter_int ){ 2082 apply_correction = 1; 2083 } else if (lr_spacing<min_jitter_int) { 2084 apply_correction = 1; 2085 idx = loop + min_jitter_int; 2086 while (tdm_cal[idx]!=MN_NUM_EXT_PORTS) { 2087 idx++; 2088 }; 2089 idle_token_location = idx; 2090 } 2091 break; 2092 } 2093 } 2094 idle_cnt = 0; 2095 } 2096 if(apply_correction == 1 && wrap_arnd == 0){ 2097 tdm_cal[idle_token_location] = tdm_cal[(lr_spacing+loop)]; 2098 tdm_cal[(lr_spacing + loop)] = MN_NUM_EXT_PORTS; 2099 apply_correction = 0; 2100 } else if(apply_correction == 1 && wrap_arnd == 1) { 2101 tdm_cal[idle_token_location] = tdm_cal[lr_spacing - (tdm_len-loop)]; 2102 tdm_cal[lr_spacing - (tdm_len - loop)] = MN_NUM_EXT_PORTS; 2103 apply_correction = 0; 2104 } 2105 idle_token_location=0; 2106 } 2107 } 2108 } 2109 } 2110 tdm_mn_tdm_print(_tdm->_chip_data.cal_2.cal_main, (tdm_len)); 2111 return; 2112 } 2113 /* 2114 void tdm_mn_custom_post_process_pgw(tdm_mod_t *_tdm) 2115 { 2116 int i=0, j=0, idx=0, numof_12p5_in_single_pm=0, pgw_len=0, 2117 total_pm_with_12p5=0, port_to_replace=MN_NUM_EXT_PORTS, total_12p5_ports=0, curr_port_to_replace=MN_NUM_EXT_PORTS; 2118 int *pgw_cal,*speed_orig, **pmap_orig; 2119 int ports_12p5[MN_NUM_PHY_PM], pm_with_12p5[MN_NUM_PHY_PM]; 2120 int replaced_port_cnt=0, pm_12p5_cnt=0, running_pm_cnt=0; 2121 speed_orig = _tdm->_chip_data.soc_pkg.soc_vars.mn.speed; 2122 pmap_orig = _tdm->_chip_data.soc_pkg.soc_vars.mn.pmap; 2123 for(i=0; i<MN_NUM_PHY_PM; i++){ 2124 pm_with_12p5[i] = MN_NUM_EXT_PORTS; 2125 } 2126 for(i=0; i<(MN_NUM_PHY_PM);i=i++){ 2127 for(j=0;j<MN_NUM_PM_LNS;j++){ 2128 if(speed_orig[pmap_orig[i][j]] == SPEED_12p5G){ 2129 ports_12p5[idx++] = ( ( (i*MN_NUM_PM_LNS) + j) +1); 2130 numof_12p5_in_single_pm++; 2131 total_12p5_ports++; 2132 } 2133 } 2134 if(numof_12p5_in_single_pm>0){ 2135 pm_with_12p5[i] = numof_12p5_in_single_pm; 2136 total_pm_with_12p5++; 2137 } 2138 numof_12p5_in_single_pm = 0; 2139 } 2140 idx=0; 2141 for(j=0; j < MN_NUM_QUAD; j++){ 2142 switch(j){ 2143 case 0: 2144 pgw_cal = _tdm->_chip_data.cal_0.cal_main; 2145 pgw_len = _tdm->_chip_data.soc_pkg.soc_vars.mn.pgw0_len; 2146 idx=0; 2147 break; 2148 case 1: 2149 pgw_cal = _tdm->_chip_data.cal_1.cal_main; 2150 pgw_len = _tdm->_chip_data.soc_pkg.soc_vars.mn.pgw1_len; 2151 idx=0; 2152 break; 2153 default: break; 2154 } 2155 for(j=0; j<total_pm_with_12p5; j++){ 2156 numof_12p5_in_single_pm = pm_with_12p5[j]; 2157 port_to_replace = ports_12p5[j*numof_12p5_in_single_pm]; 2158 curr_port_to_replace = port_to_replace; 2159 for(i=0; i<pgw_len; i++){ 2160 if(_tdm->_chip_data.soc_pkg.soc_vars.mn.speed[pgw_cal[i]] == SPEED_12p5G && pgw_cal[i] == port_to_replace){ 2161 pgw_cal[i] = curr_port_to_replace; 2162 curr_port_to_replace++; 2163 if((curr_port_to_replace == ((j*numof_12p5_in_single_pm)+numof_12p5_in_single_pm)+1)) { 2164 curr_port_to_replace = port_to_replace; 2165 } 2166 } 2167 } 2168 } 2169 tdm_mn_tdm_print(pgw_cal, pgw_len); 2170 } 2171 } 2172 void tdm_mn_custom_post_process_mmu(tdm_mod_t *_tdm) 2173 2174 { 2175 int i=0, j=0, idx=0, numof_12p5_in_single_pm=0, mmu_len=0, 2176 total_pm_with_12p5=0, port_to_replace=MN_NUM_EXT_PORTS, total_12p5_ports=0, curr_port_to_replace=MN_NUM_EXT_PORTS; 2177 int *mmu_cal,*speed_orig, **pmap_orig; 2178 int ports_12p5[MN_NUM_PHY_PM], pm_with_12p5[MN_NUM_PHY_PM]; 2179 int replaced_port_cnt=0, pm_12p5_cnt=0, running_pm_cnt=0; 2180 speed_orig = _tdm->_chip_data.soc_pkg.soc_vars.mn.speed; 2181 pmap_orig = _tdm->_chip_data.soc_pkg.soc_vars.mn.pmap; 2182 mmu_len = _tdm->_chip_data.cal_2.cal_len; 2183 mmu_cal = _tdm->_chip_data.cal_2.cal_main; 2184 for(i=0; i<MN_NUM_PHY_PM; i++){ 2185 pm_with_12p5[i] = MN_NUM_EXT_PORTS; 2186 } 2187 for(i=0; i<(MN_NUM_PHY_PM);i=i++){ 2188 for(j=0;j<MN_NUM_PM_LNS;j++){ 2189 if(speed_orig[pmap_orig[i][j]] == SPEED_12p5G){ 2190 ports_12p5[idx++] = ( ( (i*MN_NUM_PM_LNS) + j) +1); 2191 numof_12p5_in_single_pm++; 2192 total_12p5_ports++; 2193 } 2194 } 2195 if(numof_12p5_in_single_pm>0){ 2196 pm_with_12p5[i] = numof_12p5_in_single_pm; 2197 total_pm_with_12p5++; 2198 } 2199 numof_12p5_in_single_pm = 0; 2200 } 2201 idx=0; 2202 for(j=0; j<total_pm_with_12p5; j++){ 2203 numof_12p5_in_single_pm = pm_with_12p5[j]; 2204 port_to_replace = ports_12p5[j*numof_12p5_in_single_pm]; 2205 curr_port_to_replace = port_to_replace; 2206 for(i=0; i<mmu_len; i++){ 2207 if(_tdm->_chip_data.soc_pkg.soc_vars.mn.speed[mmu_cal[i]] == SPEED_12p5G && mmu_cal[i] == port_to_replace){ 2208 mmu_cal[i] = curr_port_to_replace; 2209 curr_port_to_replace++; 2210 if((curr_port_to_replace == ((j*numof_12p5_in_single_pm)+numof_12p5_in_single_pm)+1)) { 2211 curr_port_to_replace = port_to_replace; 2212 } 2213 } 2214 } 2215 } 2216 tdm_mn_tdm_print(mmu_cal, mmu_len); 2217 } 2218 2219 void tdm_mn_custom_restore_vars(tdm_mod_t *_tdm) 2220 { 2221 int i=0, j=0; 2222 for (i=1; i<(_tdm->_chip_data.soc_pkg.num_ext_ports-MN_EXT_PLUS_CPU_PORT); i++) { 2223 _tdm->_chip_data.soc_pkg.state[i] = _tdm->_chip_data.soc_pkg.soc_vars.mn.state[i]; 2224 } 2225 for (i=0; i<(_tdm->_chip_data.soc_pkg.num_ext_ports-MN_NUM_PHY_PORTS); i++) { 2226 _tdm->_chip_data.soc_pkg.speed[i] = _tdm->_chip_data.soc_pkg.soc_vars.mn.speed[i]; 2227 } 2228 for(i=0; i<MN_NUM_PHY_PM;i++){ 2229 for(j=0; j< MN_NUM_PM_LNS; j++){ 2230 _tdm->_chip_data.soc_pkg.pmap[i][j] = _tdm->_chip_data.soc_pkg.soc_vars.mn.pmap[i][j]; 2231 } 2232 } 2233 _tdm->_chip_data.soc_pkg.state[0] = PORT_STATE__LINERATE; 2234 _tdm->_chip_data.soc_pkg.state[_tdm->_chip_data.soc_pkg.num_ext_ports-MN_EXT_PLUS_CPU_PORT] = PORT_STATE__LINERATE; 2235 2236 _tdm->_chip_data.soc_pkg.speed[MN_SBUS_TOKEN] = SPEED_5G; 2237 } 2238 */ 2239 /** 2240 @name: tdm_mn_proc_cal_ancl 2241 @param: 2242 2243 Allocate ancillary slots with matched speed rates accordingly 2244 */ 2245 int 2246 tdm_mn_proc_cal_ancl(tdm_mod_t *_tdm) 2247 { 2248 int i, j, k, k_prev, k_idx, idx_up, idx_dn, result=PASS; 2249 int param_lr_limit, param_ancl_num, param_cal_len, 2250 param_token_empty, param_token_ancl, 2251 param_lr_en; 2252 int *param_cal_main; 2253 2254 param_lr_limit = _tdm->_chip_data.soc_pkg.lr_idx_limit; 2255 param_ancl_num = _tdm->_chip_data.soc_pkg.tvec_size; 2256 param_cal_len = param_lr_limit + param_ancl_num; 2257 param_token_empty = _tdm->_chip_data.soc_pkg.num_ext_ports; 2258 param_token_ancl = _tdm->_chip_data.soc_pkg.soc_vars.ancl_token; 2259 param_lr_en = _tdm->_core_data.vars_pkg.lr_enable; 2260 /* allocate ANCL slots */ 2261 TDM_SEL_CAL(_tdm->_core_data.vars_pkg.cal_id,param_cal_main); 2262 if (param_ancl_num>0){ 2263 TDM_PRINT1("TDM: Allocate %d ANCL slots\n\n", param_ancl_num); 2264 if (param_lr_en==BOOL_TRUE){ 2265 k = 0; 2266 for (j=0; j<param_ancl_num; j++){ 2267 idx_up = 0; 2268 idx_dn = 0; 2269 k_idx = 0; 2270 k_prev = k; 2271 if (j==(param_ancl_num-1)){ 2272 k = param_cal_len - 1; 2273 } 2274 else { 2275 k = k_prev + ((param_cal_len-k_prev)/(param_ancl_num-j)) -1; 2276 } 2277 for (i=k; i>0 && i<param_cal_len; i--){ 2278 if (param_cal_main[i]==param_token_empty){ 2279 idx_up = i; 2280 break; 2281 } 2282 } 2283 for (i=k; i<param_cal_len; i++){ 2284 if (param_cal_main[i]==param_token_empty){ 2285 idx_dn = i; 2286 break; 2287 } 2288 } 2289 if (idx_up>0 || idx_dn>0){ 2290 if (idx_up>0 && idx_dn>0){ 2291 k_idx = ((k-idx_up)<(idx_dn-k))?(idx_up):(idx_dn); 2292 } 2293 else if (idx_up>0){ 2294 k_idx = idx_up; 2295 } 2296 else if (idx_dn>0){ 2297 k_idx = idx_dn; 2298 } 2299 } 2300 if (k_idx==0){ 2301 for (i=(param_cal_len-1); i>0; i--){ 2302 if (param_cal_main[i]==param_token_empty){ 2303 k_idx = i; 2304 break; 2305 } 2306 } 2307 } 2308 if (k_idx>0 && k_idx<param_cal_len){ 2309 param_cal_main[k_idx] = param_token_ancl; 2310 TDM_PRINT2("TDM: Allocate %d-th ANCL slot at index #%03d\n", 2311 j+1, k_idx); 2312 } 2313 else { 2314 TDM_WARN1("TDM: Failed in %d-th ANCL slot allocation\n",j); 2315 result = FAIL; 2316 } 2317 } 2318 } 2319 else { 2320 /* Commented for OS config k_prev = 0; 2321 for (j=0; j<param_ancl_num; j++){ 2322 k_idx = k_prev + ((param_cal_len-k_prev)/(param_ancl_num-j)) - 1; 2323 param_cal_main[k_idx] = param_token_ancl; 2324 k_prev= k_idx+1; 2325 TDM_PRINT1("TDM: Allocate ANCL slot at index #%03d\n", 2326 k_idx); 2327 }*/ 2328 } 2329 TDM_SML_BAR 2330 } 2331 2332 return result; 2333 } 2334 /** 2335 * @name: tdm_mn_proc_cal 2336 * @param: 2337 * 2338 Allocate slots for linerate/oversub/ancl ports with matched speed rates accordingly 2339 */ 2340 int 2341 tdm_mn_proc_cal( tdm_mod_t *_tdm ) 2342 { 2343 /* allocate LINERATE slots */ 2344 if(tdm_mn_proc_cal_lr(_tdm)!=PASS){ 2345 return (TDM_EXEC_CORE_SIZE+1); 2346 } 2347 2348 /* allocate ANCILLARY slots */ 2349 if( _tdm->_chip_exec[TDM_CHIP_EXEC__PROC_ANCL](_tdm)!=PASS){ 2350 return (TDM_EXEC_CORE_SIZE+1); 2351 } 2352 2353 /* allocate IDLE/OVSB slots */ 2354 if(tdm_mn_proc_cal_idle(_tdm)!=PASS){ 2355 return (TDM_EXEC_CORE_SIZE+1); 2356 } 2357 2358 return ( _tdm->_core_exec[TDM_CORE_EXEC__SCHEDULER](_tdm) ); 2359 } 2360 /** 2361 * @name: tdm_mn_proc_cal_idle 2362 * @param: 2363 * 2364 * Allocate idle slots 2365 */ 2366 int 2367 tdm_mn_proc_cal_idle( tdm_mod_t *_tdm ) 2368 { 2369 int i, result=PASS; 2370 int param_lr_limit, param_ancl_num, param_cal_len, 2371 param_token_empty, param_token_ovsb, 2372 param_token_idl1, param_token_idl2, 2373 param_os_en; 2374 int *param_cal_main; 2375 2376 /* higig_mgmt */ 2377 param_lr_limit = _tdm->_chip_data.soc_pkg.lr_idx_limit; 2378 param_ancl_num = _tdm->_chip_data.soc_pkg.tvec_size; 2379 param_cal_len = param_lr_limit + param_ancl_num; 2380 param_token_empty = _tdm->_chip_data.soc_pkg.num_ext_ports; 2381 param_token_ovsb = _tdm->_chip_data.soc_pkg.soc_vars.ovsb_token; 2382 param_token_idl1 = _tdm->_chip_data.soc_pkg.soc_vars.idl1_token; 2383 param_token_idl2 = _tdm->_chip_data.soc_pkg.soc_vars.idl2_token; 2384 param_os_en = _tdm->_core_data.vars_pkg.os_enable; 2385 2386 TDM_SEL_CAL(_tdm->_core_data.vars_pkg.cal_id,param_cal_main); 2387 2388 if (param_os_en==BOOL_TRUE){ 2389 for (i=0; i<param_cal_len; i++){ 2390 if (param_cal_main[i]==param_token_empty){ 2391 param_cal_main[i] = param_token_ovsb; 2392 } 2393 } 2394 } 2395 else { 2396 for (i=0; i<param_cal_len; i++){ 2397 if (param_cal_main[i]==param_token_empty){ 2398 if ((i%2)==0){ 2399 param_cal_main[i] = param_token_idl1; 2400 } 2401 else { 2402 param_cal_main[i] = param_token_idl2; 2403 } 2404 } 2405 } 2406 } 2407 2408 return result; 2409 }