tdm_mn_parse.c (27862B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * $All Rights Reserved.$ 7 * 8 * TDM chip based printing and parsing functions 9 */ 10 #ifdef _TDM_STANDALONE 11 #include <tdm_top.h> 12 #else 13 #include <soc/tdm/core/tdm_top.h> 14 #endif 15 16 17 /** 18 @name: tdm_mn_print_tbl 19 @param: 20 21 Prints PGW TDM main calendar 22 */ 23 void 24 tdm_mn_print_tbl(int *cal, int len, const char* name, int id) 25 { 26 int idx; 27 28 for (idx=0; idx<len; idx++) { 29 TDM_PRINT4("TDM: Pipe %d, %s, Slot -- #%03d, Port -- #%0d\n", id, name, idx, cal[idx]); 30 } 31 } 32 33 void 34 tdm_mn_tdm_print(unsigned int *tdm_tbl, int length) 35 { 36 int i; 37 for (i=0; i<length; i++) { 38 if (i%10==0) TDM_PRINT2("\nTDM-TBL %3d : %3d ", i, tdm_tbl[i]); 39 else TDM_PRINT1(" %3d ", tdm_tbl[i]); 40 } 41 TDM_PRINT0(""); 42 } 43 44 /** 45 @name: tdm_mn_print_tbl_ovs 46 @param: 47 48 Prints PGW TDM calendar oversub scheduling groups 49 */ 50 void 51 tdm_mn_print_tbl_ovs(int *cal, int *spc, int len, const char* name, int id) 52 { 53 int idx; 54 55 for (idx=0; idx<len; idx++) { 56 TDM_PRINT5("TDM: Pipe %d, %s, Slot -- #%03d, Port -- #%0d, Spacing -- #%0d\n", id, name, idx, cal[idx], spc[idx]); 57 } 58 } 59 60 61 /** 62 @name: tdm_mn_print_quad 63 @param: 64 */ 65 void 66 tdm_mn_print_quad(enum port_speed_e *speed, enum port_state_e *state, int len, int idx_start, int idx_end) 67 { 68 int iter, iter2; 69 70 if (idx_start>0 && idx_end<=len){ 71 TDM_BIG_BAR 72 TDM_PRINT0("TDM: --- Pipe Config ---: "); 73 for (iter=idx_start; iter<=idx_end; iter++) { 74 if ((((iter-1)%MN_NUM_PHY_PM)==0)) { 75 TDM_PRINT0("\nTDM: "); 76 } 77 TDM_PRINT1("{%03d}\t",(iter)); 78 if (iter%MN_NUM_PHY_PM==0) { 79 TDM_PRINT0("\nTDM: "); 80 for (iter2=(iter-MN_NUM_PHY_PM); iter2<iter; iter2++) { 81 TDM_PRINT1(" %3d \t", speed[iter2+1]/1000); 82 } 83 TDM_PRINT0("\nTDM: "); 84 for (iter2=(iter-MN_NUM_PHY_PM); iter2<iter; iter2++) { 85 if (iter2%4==0){ 86 if(speed[iter2+1]/1000>0){ 87 switch ((PSBMP_LP_MASK & state[iter2])) { 88 case 1: 89 TDM_PRINT0("LINE \t --- \t --- \t --- \t"); 90 break; 91 case 2: 92 TDM_PRINT0("OVSB \t --- \t --- \t --- \t"); 93 break; 94 default: 95 TDM_PRINT0(" \t \t \t \t"); 96 break; 97 } 98 } 99 else{ 100 TDM_PRINT0(" \t \t \t \t"); 101 } 102 } 103 } 104 TDM_PRINT0("\nTDM: "); 105 for (iter2=(iter-MN_NUM_PHY_PM); iter2<iter; iter2++) { 106 if(iter2%4==0){ 107 if(speed[iter2+1]/1000>0){ 108 switch(( PSBMP_ENCAP_HIGIG & state[iter2])){ 109 case 0: 110 TDM_PRINT0(" EN \t --- \t --- \t --- \t"); 111 break; 112 case 4: 113 TDM_PRINT0(" HG \t --- \t --- \t --- \t"); 114 break; 115 default: 116 TDM_PRINT0(" \t \t \t \t"); 117 break; 118 } 119 } 120 else{ 121 TDM_PRINT0(" \t \t \t \t"); 122 } 123 } 124 } 125 } 126 } 127 TDM_PRINT0("\n"); 128 TDM_BIG_BAR 129 } 130 131 } 132 133 /** 134 @name: tdm_mn_parse_mmu_tdm_tbl 135 @param: 136 */ 137 int 138 tdm_mn_parse_mmu_tdm_tbl( tdm_mod_t *_tdm ) 139 { 140 const char *name; 141 int i=0, j=0, k=512, m=0, cal_len=0, num_lpbk_slots=0, num_cpu_slots=0, 142 *mmu_tdm_tbl, *mmu_tdm_ovs_1, *mmu_tdm_ovs_2, *mmu_tdm_ovs_3, *mmu_tdm_ovs_4, *mmu_tdm_ovs_5, *mmu_tdm_ovs_6, 143 bw=_tdm->_chip_data.soc_pkg.clk_freq, avg_lpbk_spacing=0, avg_cpu_spacing=0, avg_anc_spacing=0 , 144 avg_sbus_spacing=0, num_anc_slots=0, num_sbus_slots=0, num_macsec_slots=0; 145 int lb_slots_required=0, cpu_slots_required=0, anc_slots_required=0, sbus_slots_required=0, macsec_slots_required=0, 146 alloted_lb_slots=0, alloted_cpu_slots=0, alloted_anc_slots=0, alloted_sbus_slots=0, alloted_macsec_slots=0; 147 tdm_calendar_t *cal; 148 149 switch (_tdm->_core_data.vars_pkg.cal_id) { 150 case 0: cal=(&(_tdm->_chip_data.cal_0)); break; 151 case 1: cal=(&(_tdm->_chip_data.cal_1)); break; 152 case 2: cal=(&(_tdm->_chip_data.cal_2)); break; 153 case 3: cal=(&(_tdm->_chip_data.cal_3)); break; 154 case 4: cal=(&(_tdm->_chip_data.cal_4)); break; 155 case 5: cal=(&(_tdm->_chip_data.cal_5)); break; 156 case 6: cal=(&(_tdm->_chip_data.cal_6)); break; 157 case 7: cal=(&(_tdm->_chip_data.cal_7)); break; 158 default: 159 TDM_PRINT1("Invalid calendar ID - %0d\n",_tdm->_core_data.vars_pkg.cal_id); 160 return (TDM_EXEC_CORE_SIZE+1); 161 } 162 switch (_tdm->_core_data.vars_pkg.cal_id) { 163 case 2: name = "X-PIPE"; break; 164 default: name = "UNKNOWN"; break; 165 } 166 mmu_tdm_tbl = cal->cal_main; 167 mmu_tdm_ovs_1 = cal->cal_grp[0]; 168 mmu_tdm_ovs_2 = cal->cal_grp[1]; 169 mmu_tdm_ovs_3 = cal->cal_grp[2]; 170 mmu_tdm_ovs_4 = cal->cal_grp[3]; 171 mmu_tdm_ovs_5 = cal->cal_grp[4]; 172 mmu_tdm_ovs_6 = cal->cal_grp[5]; 173 cal_len = _tdm->_chip_data.soc_pkg.soc_vars.mn.mmu_len; 174 175 /*for (j=0; j<MN_NUM_PHY_PM; j++) { 176 if (mmu_tdm_ovs_1[j]!=TD2P_NUM_EXT_PORTS || mmu_tdm_ovs_2[j]!=TD2P_NUM_EXT_PORTS || mmu_tdm_ovs_3[j]!=TD2P_NUM_EXT_PORTS || mmu_tdm_ovs_4[j]!=TD2P_NUM_EXT_PORTS) { 177 oversub=BOOL_TRUE; 178 } 179 }*/ 180 /* Allocate slots for MGMT, CMIC/LPBK, ANCL and RERESH among available MN_ANCL_TOKENs */ 181 if( (bw != 861 && bw != 862)/* || 182 _tdm->_chip_data.soc_pkg.soc_vars.mn.sku_core_bw != 0 */ 183 ){ 184 switch(bw){ 185 case 815: case 816: case 550: 186 switch(_tdm->_chip_data.soc_pkg.soc_vars.mn.sku_core_bw) { 187 case 0: 188 avg_lpbk_spacing = 5; lb_slots_required=6; 189 avg_cpu_spacing = 10; cpu_slots_required=3; 190 avg_anc_spacing = 9; anc_slots_required=3; 191 avg_sbus_spacing = 15; sbus_slots_required=2; 192 macsec_slots_required=15; 193 break; 194 case 580: case 460: case 400: 195 _tdm->_core_data.vars_pkg.pipe_info.slot_unit = TDM_SLOT_UNIT_5G; 196 avg_lpbk_spacing = 6; lb_slots_required=2; 197 avg_cpu_spacing = 8; cpu_slots_required=2; 198 avg_anc_spacing = 7; anc_slots_required=2; 199 avg_sbus_spacing = 9; sbus_slots_required=1; 200 macsec_slots_required=8; 201 break; 202 case 280: 203 _tdm->_core_data.vars_pkg.pipe_info.slot_unit = TDM_SLOT_UNIT_5G; 204 avg_lpbk_spacing = 6; lb_slots_required=2; 205 avg_cpu_spacing = 8; cpu_slots_required=2; 206 avg_anc_spacing = 7; anc_slots_required=1; 207 avg_sbus_spacing = 9; sbus_slots_required=1; 208 macsec_slots_required=8; 209 break; 210 /*case 400: 211 _tdm->_core_data.vars_pkg.pipe_info.slot_unit = TDM_SLOT_UNIT_5G; 212 avg_lpbk_spacing = 4; lb_slots_required=2; 213 avg_cpu_spacing = 4; cpu_slots_required=2; 214 avg_anc_spacing = 4; anc_slots_required=1; 215 avg_sbus_spacing = 6; sbus_slots_required=1; 216 macsec_slots_required=2; 217 break;*/ 218 case 300: case 340: 219 _tdm->_core_data.vars_pkg.pipe_info.slot_unit = TDM_SLOT_UNIT_5G; 220 avg_lpbk_spacing = 6; lb_slots_required=1; 221 avg_cpu_spacing = 10; cpu_slots_required=1; 222 avg_anc_spacing = 7; anc_slots_required=1; 223 avg_sbus_spacing = 9; sbus_slots_required=1; 224 if(_tdm->_chip_data.soc_pkg.soc_vars.mn.is_macsec == 1) { 225 macsec_slots_required=8; 226 } else if(_tdm->_chip_data.soc_pkg.soc_vars.mn.is_macsec == 0) { 227 macsec_slots_required=0; 228 } 229 break; 230 } 231 break; 232 case 450: 233 switch(_tdm->_chip_data.soc_pkg.soc_vars.mn.sku_core_bw) { 234 case 460: case 360: case 400: 235 _tdm->_core_data.vars_pkg.pipe_info.slot_unit = TDM_SLOT_UNIT_5G; 236 avg_lpbk_spacing = 6; lb_slots_required=2; 237 avg_cpu_spacing = 8; cpu_slots_required=2; 238 avg_anc_spacing = 7; anc_slots_required=2; 239 avg_sbus_spacing = 9; sbus_slots_required=1; 240 macsec_slots_required=8; 241 break; 242 case 200: 243 _tdm->_core_data.vars_pkg.pipe_info.slot_unit = TDM_SLOT_UNIT_5G; 244 avg_lpbk_spacing = 6; lb_slots_required=2; 245 avg_cpu_spacing = 8; cpu_slots_required=2; 246 avg_anc_spacing = 7; anc_slots_required=1; 247 avg_sbus_spacing = 9; sbus_slots_required=1; 248 macsec_slots_required=8; 249 break; 250 case 235: case 275: 251 _tdm->_core_data.vars_pkg.pipe_info.slot_unit = TDM_SLOT_UNIT_5G; 252 avg_lpbk_spacing = 6; lb_slots_required=1; 253 avg_cpu_spacing = 10; cpu_slots_required=1; 254 avg_anc_spacing = 7; anc_slots_required=1; 255 avg_sbus_spacing = 9; sbus_slots_required=1; 256 if(_tdm->_chip_data.soc_pkg.soc_vars.mn.is_macsec == 1) { 257 macsec_slots_required=8; 258 } else if(_tdm->_chip_data.soc_pkg.soc_vars.mn.is_macsec == 0) { 259 macsec_slots_required=0; 260 } 261 break; 262 } 263 break; 264 case 817: 265 avg_lpbk_spacing = 3; lb_slots_required=6; 266 avg_cpu_spacing = 6; cpu_slots_required=3; 267 avg_anc_spacing = 6; anc_slots_required=3; 268 avg_sbus_spacing = 16; sbus_slots_required=1; 269 macsec_slots_required=0; 270 switch(_tdm->_chip_data.soc_pkg.soc_vars.mn.sku_core_bw) { 271 case 0: 272 avg_lpbk_spacing = 3; lb_slots_required=6; 273 avg_cpu_spacing = 6; cpu_slots_required=3; 274 avg_anc_spacing = 6; anc_slots_required=3; 275 avg_sbus_spacing = 16; sbus_slots_required=1; 276 macsec_slots_required=0; 277 break; 278 case 800: case 720: 279 _tdm->_core_data.vars_pkg.pipe_info.slot_unit = TDM_SLOT_UNIT_5G; 280 avg_lpbk_spacing = 6; lb_slots_required=2; 281 avg_cpu_spacing = 12; cpu_slots_required=2; 282 avg_anc_spacing = 7; anc_slots_required=2; 283 avg_sbus_spacing = 9; sbus_slots_required=1; 284 macsec_slots_required=8; 285 break; 286 case 460: 287 _tdm->_core_data.vars_pkg.pipe_info.slot_unit = TDM_SLOT_UNIT_5G; 288 avg_lpbk_spacing = 6; lb_slots_required=2; 289 avg_cpu_spacing = 10; cpu_slots_required=2; 290 avg_anc_spacing = 7; anc_slots_required=1; 291 avg_sbus_spacing = 9; sbus_slots_required=1; 292 macsec_slots_required=8; 293 break; 294 case 475: case 515: 295 _tdm->_core_data.vars_pkg.pipe_info.slot_unit = TDM_SLOT_UNIT_5G; 296 avg_lpbk_spacing = 6; lb_slots_required=1; 297 avg_cpu_spacing = 10; cpu_slots_required=1; 298 avg_anc_spacing = 7; anc_slots_required=1; 299 avg_sbus_spacing = 9; sbus_slots_required=1; 300 if(_tdm->_chip_data.soc_pkg.soc_vars.mn.is_macsec == 1) { 301 macsec_slots_required=8; 302 } else if(_tdm->_chip_data.soc_pkg.soc_vars.mn.is_macsec == 0) { 303 macsec_slots_required=0; 304 } 305 break; 306 } 307 break; 308 /*case 861: 309 avg_lpbk_spacing = 8; lb_slots_required=2; 310 avg_cpu_spacing = 8; cpu_slots_required=2; 311 avg_anc_spacing = 10; anc_slots_required=3; 312 avg_sbus_spacing = 8; sbus_slots_required=1; 313 if(_tdm->_chip_data.soc_pkg.soc_vars.mn.is_macsec == 1) { 314 macsec_slots_required=16; 315 } else if(_tdm->_chip_data.soc_pkg.soc_vars.mn.is_macsec == 0) { 316 macsec_slots_required=0; 317 } 318 break;*/ 319 case 818: 320 avg_lpbk_spacing = 2; lb_slots_required=6; 321 avg_cpu_spacing = 3; cpu_slots_required=3; 322 avg_anc_spacing = 2; anc_slots_required=3; 323 avg_sbus_spacing = 1; sbus_slots_required=2; 324 macsec_slots_required=0; 325 break; 326 case 819: 327 avg_lpbk_spacing = 3; lb_slots_required=5; 328 avg_cpu_spacing = 6; cpu_slots_required=3; 329 avg_anc_spacing = 6; anc_slots_required=3; 330 avg_sbus_spacing = 9; sbus_slots_required=1; 331 macsec_slots_required=15; 332 break; 333 case 820: 334 default : 335 avg_lpbk_spacing = 6; lb_slots_required=6; 336 avg_cpu_spacing = 12; cpu_slots_required=3; 337 avg_anc_spacing = 7; anc_slots_required=4; 338 avg_sbus_spacing = 9; sbus_slots_required=1; 339 macsec_slots_required=17; 340 break; 341 case 666: 342 _tdm->_core_data.vars_pkg.pipe_info.slot_unit = TDM_SLOT_UNIT_5G; 343 avg_lpbk_spacing = 6; lb_slots_required=3; 344 avg_cpu_spacing = 12; cpu_slots_required=2; 345 avg_anc_spacing = 7; anc_slots_required=2; 346 avg_sbus_spacing = 9; sbus_slots_required=1; 347 macsec_slots_required=8; 348 break; 349 case 667: 350 switch(_tdm->_chip_data.soc_pkg.soc_vars.mn.sku_core_bw) { 351 case 0: 352 _tdm->_core_data.vars_pkg.pipe_info.slot_unit = TDM_SLOT_UNIT_5G; 353 avg_lpbk_spacing = 6; lb_slots_required=3; 354 avg_cpu_spacing = 6; cpu_slots_required=2; 355 avg_anc_spacing = 7; anc_slots_required=2; 356 avg_sbus_spacing = 9; sbus_slots_required=1; 357 macsec_slots_required=8; 358 break; 359 case 720: case 580: 360 _tdm->_core_data.vars_pkg.pipe_info.slot_unit = TDM_SLOT_UNIT_5G; 361 avg_lpbk_spacing = 6; lb_slots_required=2; 362 avg_cpu_spacing = 12; cpu_slots_required=2; 363 avg_anc_spacing = 7; anc_slots_required=2; 364 avg_sbus_spacing = 9; sbus_slots_required=1; 365 macsec_slots_required=8; 366 break; 367 case 360: case 400: 368 _tdm->_core_data.vars_pkg.pipe_info.slot_unit = TDM_SLOT_UNIT_5G; 369 avg_lpbk_spacing = 6; lb_slots_required=2; 370 avg_cpu_spacing = 10; cpu_slots_required=2; 371 avg_anc_spacing = 7; anc_slots_required=1; 372 avg_sbus_spacing = 9; sbus_slots_required=1; 373 macsec_slots_required=8; 374 break; 375 case 380: case 420: 376 _tdm->_core_data.vars_pkg.pipe_info.slot_unit = TDM_SLOT_UNIT_5G; 377 avg_lpbk_spacing = 6; lb_slots_required=1; 378 avg_cpu_spacing = 8; cpu_slots_required=1; 379 avg_anc_spacing = 6; anc_slots_required=1; 380 avg_sbus_spacing = 6; sbus_slots_required=1; 381 if(_tdm->_chip_data.soc_pkg.soc_vars.mn.is_macsec == 1) { 382 macsec_slots_required=8; 383 } else if(_tdm->_chip_data.soc_pkg.soc_vars.mn.is_macsec == 0) { 384 macsec_slots_required=0; 385 } 386 break; 387 } 388 break; 389 } 390 for(i=0; i<cal_len; i++){ 391 if(mmu_tdm_tbl[i] == MN_ANCL_TOKEN && (num_lpbk_slots % avg_lpbk_spacing == 0) && (alloted_lb_slots<lb_slots_required) ){ 392 mmu_tdm_tbl[i] = MN_LOOPBACK_PORT; 393 TDM_PRINT2("MMU TDM TABLE, element #%0d, contains LOOPBACK port #%0d \n", i, mmu_tdm_tbl[i]); 394 num_lpbk_slots = num_lpbk_slots +1; 395 alloted_lb_slots = alloted_lb_slots + 1; 396 } else if (mmu_tdm_tbl[i] == MN_ANCL_TOKEN) { 397 num_lpbk_slots = num_lpbk_slots +1; 398 } 399 } 400 for(i=0; i<cal_len; i++){ 401 if(mmu_tdm_tbl[i] == MN_ANCL_TOKEN && (num_cpu_slots % avg_cpu_spacing == 0) && (alloted_cpu_slots<cpu_slots_required) ){ 402 mmu_tdm_tbl[i] = MN_CPU_PORT; 403 TDM_PRINT2("MMU TDM TABLE, element #%0d, contains CPU port #%0d \n", i, mmu_tdm_tbl[i]); 404 num_cpu_slots = num_cpu_slots +1; 405 alloted_cpu_slots = alloted_cpu_slots + 1; 406 } else if (mmu_tdm_tbl[i] == MN_ANCL_TOKEN) { 407 num_cpu_slots = num_cpu_slots +1; 408 } 409 } 410 for(i=0; i<cal_len; i++){ 411 if(mmu_tdm_tbl[i] == MN_ANCL_TOKEN && (num_anc_slots % avg_anc_spacing == 0) && (alloted_anc_slots<anc_slots_required) ){ 412 mmu_tdm_tbl[i] = MN_AUX_TOKEN; 413 TDM_PRINT2("MMU TDM TABLE, element #%0d, contains ANCL port #%0d\n", i, mmu_tdm_tbl[i]); 414 num_anc_slots = num_anc_slots +1; 415 alloted_anc_slots = alloted_anc_slots + 1; 416 } else if (mmu_tdm_tbl[i] == MN_ANCL_TOKEN) { 417 num_anc_slots = num_anc_slots +1; 418 } 419 } 420 for(i=0; i<cal_len; i++){ 421 if(mmu_tdm_tbl[i] == MN_ANCL_TOKEN && (num_sbus_slots % avg_sbus_spacing == 0) && (alloted_sbus_slots<sbus_slots_required) ){ 422 mmu_tdm_tbl[i] = MN_SBUS_TOKEN; 423 TDM_PRINT2("MMU TDM TABLE, element #%0d, contains SBUS port #%0d\n", i, mmu_tdm_tbl[i]); 424 num_sbus_slots = num_sbus_slots +1; 425 alloted_sbus_slots = alloted_sbus_slots + 1; 426 } else if (mmu_tdm_tbl[i] == MN_ANCL_TOKEN) { 427 num_sbus_slots = num_sbus_slots +1; 428 } 429 } 430 for(i=0; i<cal_len; i++){ 431 if(macsec_slots_required>0){ 432 if(mmu_tdm_tbl[i] == MN_ANCL_TOKEN && (alloted_macsec_slots<macsec_slots_required) ){ 433 mmu_tdm_tbl[i] = MN_MACSEC_PORT; 434 TDM_PRINT2("MMU TDM TABLE, element #%0d, contains MACSEC port #%0d\n", i, mmu_tdm_tbl[i]); 435 num_macsec_slots = num_macsec_slots +1; 436 alloted_macsec_slots = alloted_macsec_slots + 1; 437 } else if (mmu_tdm_tbl[i] == MN_ANCL_TOKEN) { 438 num_macsec_slots = num_macsec_slots +1; 439 } 440 } 441 } 442 } 443 for (j=0; j<k; j++) { 444 if (mmu_tdm_tbl[j]!=MN_ANCL_TOKEN) { 445 TDM_PRINT3("PIPE: %s, MMU TDM TABLE, element #%0d, contains physical port #%0d\n", name, j, mmu_tdm_tbl[j]); 446 } 447 else { 448 TDM_PRINT2("PIPE: %s, MMU TDM TABLE, element #%0d, CONTAINS ACCESSORY TOKEN - assigned as ", name, j); 449 m++; 450 if (bw==933) { 451 if (_tdm->_core_data.vars_pkg.cal_id==MN_XPIPE_CAL_ID) { 452 switch (m) { 453 case 1: case 3: case 5: case 7: 454 MN_ANCL(j) 455 case 2: case 6: 456 MN_CMIC(j) 457 case 4: case 9: 458 MN_LPBK(j) 459 case 8: 460 MN_SBUS(j) 461 } 462 } 463 } 464 else if (bw==840) { 465 if (_tdm->_core_data.vars_pkg.cal_id==MN_XPIPE_CAL_ID) { 466 switch (m) { 467 case 1: case 3: case 5: case 7: 468 MN_ANCL(j) 469 case 2: case 6: 470 MN_CMIC(j) 471 case 4: case 9: 472 MN_LPBK(j) 473 case 8: 474 MN_SBUS(j) 475 } 476 } 477 } 478 else if (bw==793 || bw==794) { 479 if (_tdm->_core_data.vars_pkg.cal_id==MN_XPIPE_CAL_ID) { 480 switch (m) { 481 case 3: case 10: 482 MN_ANCL(j) 483 case 1: case 4: case 8: case 11: 484 MN_LPBK(j) 485 case 6: case 13: 486 MN_CMIC(j) 487 case 7: 488 MN_SBUS(j) 489 case 2: case 5: case 9: case 12: 490 MN_MACSEC(j) 491 } 492 } 493 } 494 else if (bw==705) { 495 if (_tdm->_core_data.vars_pkg.cal_id==MN_XPIPE_CAL_ID) { 496 switch (m) { 497 case 3: case 4: case 7: case 8: case 10: case 12: case 13: case 15: case 20: case 23: case 25: case 26: case 28: case 30: case 31: case 33: 498 MN_ANCL(j) 499 case 2: case 11: case 18: case 27: 500 MN_LPBK(j) 501 case 6: case 22: 502 MN_CMIC(j) 503 case 16: case 34: 504 MN_SBUS(j) 505 case 1: case 5: case 9: case 14: case 17: case 19: case 21: case 24: case 29: case 32: 506 MN_MACSEC(j) 507 } 508 } 509 } 510 else if (bw==815 || bw==816) { 511 /*if (_tdm->_core_data.vars_pkg.cal_id==MN_XPIPE_CAL_ID) { 512 switch (m) { 513 case 4:case 10: case 19: 514 MN_ANCL(j) 515 case 2: case 11: case 16: case 7: case 25:case 29: 516 MN_LPBK(j) 517 case 6: case 14: case 23: 518 MN_CMIC(j) 519 case 12: case 18: 520 MN_SBUS(j) 521 case 1: case 3: case 5: case 7: case 9: case 11: case 13: case 15: case 17: case 5: case 20: case 22: case 24: case 18: case 20: 522 MN_MACSEC(j) 523 default : MN_IDLE(j) 524 } 525 } */ 526 } 527 else if (bw==817) { 528 if (_tdm->_core_data.vars_pkg.cal_id==MN_XPIPE_CAL_ID) { 529 /*switch (m) { 530 case 3: case 11: case 5: 531 MN_ANCL(j) 532 case 2: case 4: case 6: case 8: case 10: case 12: 533 MN_LPBK(j) 534 case 7: case 9: case 13: 535 MN_CMIC(j) 536 case 1: 537 MN_SBUS(j) 538 }*/ 539 } 540 } 541 else if (bw==818) { 542 if (_tdm->_core_data.vars_pkg.cal_id==MN_XPIPE_CAL_ID) { 543 /*switch (m) { 544 case 3: case 11: case 14: 545 MN_ANCL(j) 546 case 2: case 4: case 6: case 8: case 10: case 12: 547 MN_LPBK(j) 548 case 7: case 9: case 13: 549 MN_CMIC(j) 550 case 1: case 5: 551 MN_SBUS(j) 552 default : 553 MN_IDLE(j) 554 }*/ 555 } 556 } 557 else if (bw==819) { 558 if (_tdm->_core_data.vars_pkg.cal_id==MN_XPIPE_CAL_ID) { 559 /*switch (m) { 560 case 10: case 16: case 22: 561 MN_ANCL(j) 562 case 2: case 27: case 8: case 12: case 20: 563 MN_LPBK(j) 564 case 14: case 18: case 24: 565 MN_CMIC(j) 566 case 4: 567 MN_SBUS(j) 568 case 1: case 3: case 5: case 7: case 9: case 11: case 13: case 15: case 17: case 19: case 21: case 23: case 25: case 26: case 6: 569 MN_MACSEC(j) 570 default : 571 MN_IDLE(j) 572 }*/ 573 } 574 } 575 else if (bw==820) { 576 if (_tdm->_core_data.vars_pkg.cal_id==MN_XPIPE_CAL_ID) { 577 /*switch (m) { 578 case 10: case 18: case 22: case 29: 579 MN_ANCL(j) 580 case 2: case 27: case 8: case 12: case 16: case 31: 581 MN_LPBK(j) 582 case 14: case 20: case 24: 583 MN_CMIC(j) 584 case 4: 585 MN_SBUS(j) 586 case 1: case 3: case 5: case 7: case 9: case 11: case 13: case 15: case 17: case 19: case 21: case 23: case 25: case 26: case 6: case 28: case 30: 587 MN_MACSEC(j) 588 default : 589 MN_IDLE(j) 590 }*/ 591 } 592 } 593 else if (bw==861 || bw==862) { 594 if (_tdm->_core_data.vars_pkg.cal_id==MN_XPIPE_CAL_ID) { 595 if(_tdm->_chip_data.soc_pkg.soc_vars.mn.sku_core_bw == 0) { 596 switch (m) { 597 case 2: case 5: 598 MN_ANCL(j) 599 case 1: 600 MN_LPBK(j) 601 case 3: 602 MN_CMIC(j) 603 case 4: 604 MN_SBUS(j) 605 } 606 } else if (_tdm->_chip_data.soc_pkg.soc_vars.mn.sku_core_bw !=0 ){ 607 if(_tdm->_chip_data.soc_pkg.soc_vars.mn.is_macsec == 0) { 608 switch (m) { 609 case 2: case 5: case 97: 610 MN_ANCL(j) 611 break; 612 case 50: case 100: 613 MN_LPBK(j) 614 break; 615 case 35: case 75: 616 MN_CMIC(j) 617 break; 618 case 4: 619 MN_SBUS(j) 620 break; 621 } 622 } else if(_tdm->_chip_data.soc_pkg.soc_vars.mn.is_macsec == 1) { 623 switch (m) { 624 case 0: case 14: case 28: case 42: case 56: case 70: case 84: case 98: 625 case 112: case 126: case 140: case 154: case 168: case 182: case 196: case 210: 626 mmu_tdm_tbl[j] = MN_MACSEC_PORT; 627 TDM_PRINT0("MACSEC\n"); \ 628 break; 629 case 2: case 5: case 97: 630 MN_ANCL(j) 631 break; 632 case 50: case 100: 633 MN_LPBK(j) 634 break; 635 case 35: case 75: 636 MN_CMIC(j) 637 break; 638 case 4: 639 MN_SBUS(j) 640 break; 641 } 642 } 643 } 644 } 645 } 646 else if (bw==525 ) { 647 if (_tdm->_core_data.vars_pkg.cal_id==MN_XPIPE_CAL_ID) { 648 switch (m) { 649 case 2: case 6: case 9: 650 MN_ANCL(j) 651 case 1: case 4: case 7: case 10: 652 MN_LPBK(j) 653 case 3: case 8: 654 MN_CMIC(j) 655 case 5: 656 MN_SBUS(j) 657 } 658 } 659 } 660 else if (bw==575) { 661 if (_tdm->_core_data.vars_pkg.cal_id==MN_XPIPE_CAL_ID) { 662 switch (m) { 663 case 1: case 5: 664 MN_CMIC(j) 665 case 2: case 4: case 6: case 8: 666 MN_ANCL(j) 667 case 3: case 7: 668 MN_LPBK(j) 669 case 9: 670 MN_SBUS(j) 671 } 672 } 673 } 674 else if (bw==510) { 675 if (_tdm->_core_data.vars_pkg.cal_id==MN_XPIPE_CAL_ID) { 676 switch (m) { 677 case 1: case 3: case 5: case 7: case 9: 678 MN_CMIC(j) 679 case 2: case 4: case 6: case 8: 680 MN_ANCL(j) 681 case 10: 682 MN_SBUS(j) 683 } 684 } 685 } 686 else if (bw==435) { 687 if (_tdm->_core_data.vars_pkg.cal_id==MN_XPIPE_CAL_ID) { 688 switch (m) { 689 case 1: case 3: case 6: case 8: 690 MN_ANCL(j) 691 case 2: case 5: case 7: 692 MN_LPBK(j) 693 case 4: case 9: 694 MN_CMIC(j) 695 case 10: 696 MN_SBUS(j) 697 } 698 } 699 } 700 else { 701 TDM_PRINT0("INVALID PARAMETERS\n"); 702 } 703 } 704 } 705 m =0; 706 for (j=0; j<k; j++) { 707 m++; 708 if (bw==861 || bw==862) { 709 if (_tdm->_core_data.vars_pkg.cal_id==MN_XPIPE_CAL_ID) { 710 if(_tdm->_chip_data.soc_pkg.soc_vars.mn.sku_core_bw == 0) { 711 switch (m) { 712 case 2: case 5: 713 MN_ANCL(j) 714 case 1: 715 MN_LPBK(j) 716 case 3: 717 MN_CMIC(j) 718 case 4: 719 MN_SBUS(j) 720 } 721 } else if (_tdm->_chip_data.soc_pkg.soc_vars.mn.sku_core_bw !=0 ){ 722 if(_tdm->_chip_data.soc_pkg.soc_vars.mn.is_macsec == 0) { 723 switch (m) { 724 case 2: case 5: case 97: 725 MN_ANCL(j) 726 break; 727 case 50: case 100: 728 MN_LPBK(j) 729 break; 730 case 35: case 75: 731 MN_CMIC(j) 732 break; 733 case 4: 734 MN_SBUS(j) 735 break; 736 } 737 } else if(_tdm->_chip_data.soc_pkg.soc_vars.mn.is_macsec == 1) { 738 switch (m) { 739 case 1: case 14: case 28: case 42: case 56: case 70: case 84: case 98: 740 case 112: case 126: case 140: case 154: case 168: case 182: case 196: case 210: 741 mmu_tdm_tbl[j] = MN_MACSEC_PORT; 742 TDM_PRINT0("MACSEC\n"); 743 break; 744 case 2: case 5: case 97: 745 MN_ANCL(j) 746 break; 747 case 50: case 100: 748 MN_LPBK(j) 749 break; 750 case 35: case 75: 751 MN_CMIC(j) 752 break; 753 case 4: 754 MN_SBUS(j) 755 break; 756 } 757 } 758 } 759 } 760 } 761 } 762 763 for (j=0; j<MN_OS_VBS_GRP_LEN; j++) { 764 TDM_PRINT3("PIPE: %s, MMU OVS BUCKET 0, element #%0d, contains physical port #%0d\n", name, j, mmu_tdm_ovs_1[j]); 765 } 766 for (j=0; j<MN_OS_VBS_GRP_LEN; j++) { 767 TDM_PRINT3("PIPE: %s, MMU OVS BUCKET 1, element #%0d, contains physical port #%0d\n", name, j, mmu_tdm_ovs_2[j]); 768 } 769 for (j=0; j<MN_OS_VBS_GRP_LEN; j++) { 770 TDM_PRINT3("PIPE: %s, MMU OVS BUCKET 2, element #%0d, contains physical port #%0d\n", name, j, mmu_tdm_ovs_3[j]); 771 } 772 for (j=0; j<MN_OS_VBS_GRP_LEN; j++) { 773 TDM_PRINT3("PIPE: %s, MMU OVS BUCKET 3, element #%0d, contains physical port #%0d\n", name, j, mmu_tdm_ovs_4[j]); 774 } 775 for (j=0; j<MN_OS_VBS_GRP_LEN; j++) { 776 TDM_PRINT3("PIPE: %s, MMU OVS BUCKET 4, element #%0d, contains physical port #%0d\n", name, j, mmu_tdm_ovs_5[j]); 777 } 778 for (j=0; j<MN_OS_VBS_GRP_LEN; j++) { 779 TDM_PRINT3("PIPE: %s, MMU OVS BUCKET 5, element #%0d, contains physical port #%0d\n", name, j, mmu_tdm_ovs_6[j]); 780 } 781 782 return ( ( _tdm->_core_exec[TDM_CORE_EXEC__POST]( _tdm ) ) ); 783 }