tdm_mn_main.c (57818B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * $All Rights Reserved.$ 7 * 8 * TDM chip main functions 9 */ 10 #ifdef _TDM_STANDALONE 11 #include <tdm_top.h> 12 #else 13 #include <soc/tdm/core/tdm_top.h> 14 #endif 15 16 extern void tdm_mn_tdm_print(int *tdm_tbl, int length); 17 18 /** 19 @name: chk_tdm_roundup 20 @param: 21 22 Round result to integer 23 */ 24 int chk_tdm_roundup(int m, int n) 25 { 26 if(n==0) 27 return ( m + (n+1) -1) / (n+1); 28 else 29 return (m+n-1)/n ; 30 } 31 32 /** 33 @name: chk_tdm_rounddown 34 @param: 35 36 Round result to integer 37 */ 38 int chk_tdm_rounddown(int m, int n) 39 { 40 if(n==0) 41 return m/(n+1); 42 else 43 return m/n; 44 } 45 46 47 /** 48 @name: chk_tdm_round 49 @param: 50 51 Round result to integer 52 */ 53 int chk_tdm_round(int m, int n) 54 { 55 int mod; 56 if(n==0) 57 mod = m % (n+1); 58 else 59 mod = m % n; 60 61 if( mod >= (n + 1)/2 ) 62 return chk_tdm_roundup(m,n); 63 else 64 return chk_tdm_rounddown(m,n); 65 } 66 67 int mn_is_clport(int pnum) { 68 if(pnum > 64) return 0; 69 if( (pnum >=1 && pnum <=20) || (pnum >=45 && pnum <=64)) { 70 return 1; 71 } else { 72 return 0; 73 } 74 } 75 76 /* 77 * This API checks if phy ports belongs to TSCF 3 or TSCF4 78 * Returns 1 if phy port belongs to TSCF3/4. 79 * API is used for both PGW0 and PGW1 in in-line edit API 80 */ 81 82 int mn_is_tscf_3_or_4(int pnum) 83 { 84 if(pnum > 64) return 0; 85 if( (pnum == 13) || (pnum == 17) || 86 (pnum == 57) || (pnum == 61) 87 ) { 88 return 1; 89 } else { 90 return 0; 91 } 92 } 93 94 /* 95 * This API checks if all ports are in Oversub mode 96 * Returns 1 if all ports in oversub mode else return 0 97 */ 98 99 int mn_is_os_config(tdm_mn_chip_legacy_t *_mn_chip) 100 { 101 int i=0, os_flag=0; 102 for(i=0; i < MN_NUM_PHY_PORTS; i++) { 103 if((*_mn_chip).tdm_globals.port_rates_array[i] == PORT_STATE__OVERSUB|| 104 (*_mn_chip).tdm_globals.port_rates_array[i] == PORT_STATE__OVERSUB_HG 105 ) 106 os_flag = 1; 107 if((*_mn_chip).tdm_globals.port_rates_array[i] == PORT_STATE__LINERATE || 108 (*_mn_chip).tdm_globals.port_rates_array[i] == PORT_STATE__LINERATE_HG 109 ) { 110 return 0; 111 } 112 } 113 return(os_flag); 114 } 115 116 /** 117 @name: tdm_ap_corereq 118 @param: 119 120 Allocate memory for core data execute request to core executive 121 */ 122 int 123 tdm_mn_corereq( tdm_mod_t *_tdm ) 124 { 125 126 /* X-Pipe: */ 127 if (!(_tdm->_core_data.vars_pkg.pipe==MN_PIPE_X_ID)) { 128 TDM_ERROR1("Unrecgonized PIPE ID %d \n", _tdm->_core_data.vars_pkg.pipe); 129 return (TDM_EXEC_CORE_SIZE+1); 130 } 131 132 return ( _tdm->_core_exec[TDM_CORE_EXEC__INIT]( _tdm ) ); 133 } 134 135 136 /** 137 @name: tdm_mn_vbs_wrapper 138 @param: 139 140 Code wrapper for egress TDM scheduling 141 */ 142 int 143 tdm_mn_vbs_wrapper( tdm_mod_t *_tdm ) 144 { 145 return ( _tdm->_chip_exec[TDM_CHIP_EXEC__COREREQ]( _tdm ) ); 146 } 147 148 /** 149 @name: tdm_mn_lls_wrapper 150 @param: 151 152 Code wrapper for ingress TDM scheduling 153 */ 154 int 155 tdm_mn_lls_wrapper( tdm_mod_t *_tdm ) 156 { 157 int idx=0; 158 int *iarb_tdm_wrap_ptr_lr_x, *iarb_tdm_tbl_lr_x, sku_core_bw=0, os_config=0, is_macsec=0; 159 int *ovs_tdm_tbl = NULL, *ovs_spacing = NULL, *is_falcon_32_40 = NULL; /* is_falcon_32_40 - 1 means falcon-32 and 0 means falcon-40*/ 160 tdm_mn_chip_legacy_t *_mn_chip; 161 162 _mn_chip = TDM_ALLOC(sizeof(tdm_mn_chip_legacy_t), "TDM chip legacy"); 163 is_falcon_32_40 = TDM_ALLOC(sizeof(int), "is_falcon_32_40"); 164 if (!_mn_chip) { 165 TDM_FREE(is_falcon_32_40); 166 return FAIL; 167 } 168 tdm_chip_mn_shim__ing_wrap(_tdm, _mn_chip); 169 170 sku_core_bw = _tdm->_chip_data.soc_pkg.soc_vars.mn.sku_core_bw; 171 is_macsec = _tdm->_chip_data.soc_pkg.soc_vars.mn.is_macsec; 172 iarb_tdm_wrap_ptr_lr_x = TDM_ALLOC(sizeof(int), "IARB TDM PTR"); 173 iarb_tdm_tbl_lr_x = TDM_ALLOC((sizeof(int)*512), "IARB TDM TABLE"); 174 175 for(idx=0; idx<512; idx++){ 176 iarb_tdm_tbl_lr_x[idx] = MN_NUM_EXT_PORTS; 177 } 178 179 if( 180 _tdm->_chip_data.soc_pkg.clk_freq == 861 || 181 _tdm->_chip_data.soc_pkg.clk_freq == 862 || 182 (mn_is_os_config(_mn_chip) == 1 )) 183 { 184 *is_falcon_32_40 = 0; /* Setting this to 0 for New OS support: 12.5G per slot BW */ 185 if(_tdm->_chip_data.soc_pkg.clk_freq == 862){ 186 *is_falcon_32_40 = 1; 187 }/* else if(_tdm->_chip_data.soc_pkg.clk_freq == 862) { 188 *is_falcon_32_40 = 0; 189 }*/ 190 _tdm->_chip_data.soc_pkg.soc_vars.mn.os_config = 1; /* set to 1 for os config */ 191 os_config = _tdm->_chip_data.soc_pkg.soc_vars.mn.os_config; 192 for(idx=0; idx<MN_NUM_QUAD; idx++){ 193 switch(idx){ 194 case 0: 195 ovs_spacing = _mn_chip->tdm_pgw.ovs_spacing_x0; 196 ovs_tdm_tbl = _tdm->_chip_data.cal_0.cal_grp[0]; 197 break; 198 case 1: 199 ovs_spacing = _mn_chip->tdm_pgw.ovs_spacing_x1; 200 ovs_tdm_tbl = _tdm->_chip_data.cal_1.cal_grp[0]; 201 break; 202 } 203 tdm_mn_falcon_32_40__ovs_gen(_mn_chip, ovs_tdm_tbl, ovs_spacing, idx, is_falcon_32_40, _tdm); 204 } 205 } 206 switch(_tdm->_chip_data.soc_pkg.clk_freq) { 207 case 667: 208 tdm_mn_init_iarb_tdm_table (667, iarb_tdm_wrap_ptr_lr_x, iarb_tdm_tbl_lr_x, sku_core_bw, os_config, is_macsec); /*Customer 10G*/ 209 break; 210 case 815: 211 tdm_mn_init_iarb_tdm_table (815, iarb_tdm_wrap_ptr_lr_x, iarb_tdm_tbl_lr_x, sku_core_bw, os_config, is_macsec); /*Customer 10G*/ 212 break; 213 case 816: 214 tdm_mn_init_iarb_tdm_table (816, iarb_tdm_wrap_ptr_lr_x, iarb_tdm_tbl_lr_x, sku_core_bw, os_config, is_macsec); /*Customer 25G*/ 215 break; 216 case 817: 217 tdm_mn_init_iarb_tdm_table (817, iarb_tdm_wrap_ptr_lr_x, iarb_tdm_tbl_lr_x, sku_core_bw, os_config, is_macsec); break; 218 case 818: 219 tdm_mn_init_iarb_tdm_table (818, iarb_tdm_wrap_ptr_lr_x, iarb_tdm_tbl_lr_x, sku_core_bw, os_config, is_macsec); /*CPRI 25G*/ 220 break; 221 case 819: 222 tdm_mn_init_iarb_tdm_table (819, iarb_tdm_wrap_ptr_lr_x, iarb_tdm_tbl_lr_x, sku_core_bw, os_config, is_macsec); /*CPRI10G-A*/ 223 break; 224 case 820: 225 tdm_mn_init_iarb_tdm_table (820, iarb_tdm_wrap_ptr_lr_x, iarb_tdm_tbl_lr_x, sku_core_bw, os_config, is_macsec); /*CPRI10G-B*/ 226 break; 227 case 861: case 862: /* Both Falcon32/40 has same IARB TDM */ 228 tdm_mn_init_iarb_tdm_table (861, iarb_tdm_wrap_ptr_lr_x, iarb_tdm_tbl_lr_x, sku_core_bw, os_config, is_macsec); /*FALCON32/40*/ 229 break; 230 case 550: 231 tdm_mn_init_iarb_tdm_table (550, iarb_tdm_wrap_ptr_lr_x, iarb_tdm_tbl_lr_x, sku_core_bw, os_config, is_macsec); /* 56672 */ 232 break; 233 case 450: 234 tdm_mn_init_iarb_tdm_table (450, iarb_tdm_wrap_ptr_lr_x, iarb_tdm_tbl_lr_x, sku_core_bw, os_config, is_macsec); /* 56672 */ 235 break; 236 default: break; 237 } 238 /* tdm_mn_custom(_tdm); */ 239 /* Realign port state array to old specification */ 240 for (idx=0; idx<((_tdm->_chip_data.soc_pkg.num_ext_ports) - MN_EXT_PLUS_CPU_PORT); idx++) { 241 _tdm->_chip_data.soc_pkg.state[idx] = _tdm->_chip_data.soc_pkg.state[idx+1]; 242 } 243 _tdm->_core_data.vars_pkg.pipe = 0; 244 TDM_FREE(is_falcon_32_40); 245 TDM_FREE(iarb_tdm_wrap_ptr_lr_x); 246 TDM_FREE(iarb_tdm_tbl_lr_x); 247 TDM_FREE(_mn_chip); 248 return ( _tdm->_chip_exec[TDM_CHIP_EXEC__EGRESS_WRAP]( _tdm ) ); 249 } 250 251 /** 252 * @name: tdm_mn_custom 253 */ 254 /* 255 void tdm_mn_custom(tdm_mod_t *_tdm) 256 { 257 int i=0, j=0; 258 tdm_mn_custom_vars_backup(_tdm); 259 tdm_mn_custom_change_vars(_tdm); 260 } 261 } 262 void tdm_mn_custom_change_vars(tdm_mod_t *_tdm) 263 { 264 int i=0, j=0; 265 for(i=1; i<(MN_NUM_PHY_PORTS);i=i+MN_NUM_PM_LNS){ 266 if(_tdm->_chip_data.soc_pkg.speed[i] == SPEED_12p5G){ 267 for(j=0; j<MN_NUM_PM_LNS; j++){ 268 switch(j){ 269 case 0: 270 _tdm->_chip_data.soc_pkg.state[i+j] = PORT_STATE__LINERATE; 271 break; 272 case 1: case 2: case 3: 273 _tdm->_chip_data.soc_pkg.state[i+j] = PORT_STATE__DISABLED; 274 break; 275 } 276 } 277 } 278 } 279 for(i=1; i<=(MN_NUM_PHY_PORTS);i=i+MN_NUM_PM_LNS){ 280 if(_tdm->_chip_data.soc_pkg.speed[i] == SPEED_12p5G){ 281 for(j=0; j<MN_NUM_PM_LNS; j++){ 282 switch(j){ 283 case 0: case 1: 284 _tdm->_chip_data.soc_pkg.pmap[i/MN_NUM_PM_LNS][j] = i; 285 break; 286 case 2: case 3: 287 _tdm->_chip_data.soc_pkg.pmap[i/MN_NUM_PM_LNS][j] = MN_NUM_EXT_PORTS; 288 break; 289 } 290 } 291 } 292 } 293 for(i=1; i<(MN_NUM_PHY_PORTS);i=i+MN_NUM_PM_LNS){ 294 if(_tdm->_chip_data.soc_pkg.speed[i] == SPEED_12p5G){ 295 for(j=0; j<MN_NUM_PM_LNS; j++){ 296 switch(j){ 297 case 0: 298 _tdm->_chip_data.soc_pkg.speed[i+j] = SPEED_50G; 299 break; 300 case 1: case 2: case 3: 301 _tdm->_chip_data.soc_pkg.speed[i+j] = SPEED_0; 302 break; 303 } 304 } 305 } 306 } 307 } 308 void tdm_mn_custom_vars_backup(tdm_mod_t *_tdm) 309 { 310 int i=0, j=0; 311 _tdm->_chip_data.soc_pkg.soc_vars.mn.pmap=(int **) TDM_ALLOC((_tdm->_chip_data.soc_pkg.pmap_num_modules)*sizeof(int *), "portmod_map_l1_backup"); 312 for (i=0; i<(_tdm->_chip_data.soc_pkg.pmap_num_modules); i++) { 313 _tdm->_chip_data.soc_pkg.soc_vars.mn.pmap[i]=(int *) TDM_ALLOC((_tdm->_chip_data.soc_pkg.pmap_num_lanes)*sizeof(int), "portmod_map_l2_backup"); 314 TDM_MSET(_tdm->_chip_data.soc_pkg.soc_vars.mn.pmap[i],(_tdm->_chip_data.soc_pkg.num_ext_ports),_tdm->_chip_data.soc_pkg.pmap_num_lanes); 315 } 316 for(i=0; i<MN_NUM_PHY_PM;i++){ 317 for(j=0; j< MN_NUM_PM_LNS; j++){ 318 _tdm->_chip_data.soc_pkg.soc_vars.mn.pmap[i][j] = _tdm->_chip_data.soc_pkg.pmap[i][j]; 319 } 320 } 321 _tdm->_chip_data.soc_pkg.soc_vars.mn.state = TDM_ALLOC((MN_NUM_EXT_PORTS)*sizeof(enum port_speed_e *), "port state list backup"); 322 _tdm->_chip_data.soc_pkg.soc_vars.mn.speed = TDM_ALLOC((MN_NUM_EXT_PORTS)*sizeof(enum port_state_e *), "port speed list backup"); 323 324 _tdm->_chip_data.soc_pkg.soc_vars.mn.state[0] = PORT_STATE__LINERATE; 325 for (i=1; i<(_tdm->_chip_data.soc_pkg.num_ext_ports-MN_EXT_PLUS_CPU_PORT); i++) { 326 _tdm->_chip_data.soc_pkg.soc_vars.mn.state[i] = _tdm->_chip_data.soc_pkg.state[i]; 327 } 328 _tdm->_chip_data.soc_pkg.soc_vars.mn.state[_tdm->_chip_data.soc_pkg.num_ext_ports-MN_EXT_PLUS_CPU_PORT] = PORT_STATE__LINERATE; 329 330 for (i=0; i<(_tdm->_chip_data.soc_pkg.num_ext_ports-MN_NUM_PHY_PORTS); i++) { 331 _tdm->_chip_data.soc_pkg.soc_vars.mn.speed[i] = _tdm->_chip_data.soc_pkg.speed[i]; 332 } 333 334 _tdm->_chip_data.soc_pkg.soc_vars.mn.speed[MN_SBUS_TOKEN] = SPEED_5G; 335 } 336 */ 337 /** 338 @name: tdm_mn_falcon_32_40__ovs_gen 339 @param: 340 Api to replace tdm_mn_ovs_spacer. 341 this api is helpful in generating tdm table based on the template provided by Brendan 342 */ 343 void 344 tdm_mn_falcon_32_40__ovs_gen(tdm_mn_chip_legacy_t *_mn_chip,int *ovs_tdm_tbl, int *ovs_spacing, int pgw_num, int *is_falcon_32_40, tdm_mod_t *_tdm) 345 { 346 mn_pgw_os_tdm_sel_e mn_pgw_os_tdm_sel; 347 int falcon_pgw0_ovs_tbl_template[3][48] = { 348 {1,5,9,13,1,5,9,13,1,5,9,13,1,5,9,13,1,5,9,13,1,5,9,13,1,5,9,13,1,5,9,13,1,5,9,13,1,5,9,13,1,5,9,13,1,5,9,13}, /* FALCON32 - 800G */ 349 {1,5,9,13,17,1,5,9,13,17,1,5,9,13,17,1,5,9,13,17,1,5,9,13,17,1,5,9,13,17,1,5,9,13,17,1,5,9,13,17,MN_OVSB_TOKEN,MN_OVSB_TOKEN,MN_OVSB_TOKEN,MN_OVSB_TOKEN,MN_OVSB_TOKEN,MN_OVSB_TOKEN,MN_OVSB_TOKEN,MN_OVSB_TOKEN}, /* FALCON40 - 1000G*/ 350 {1,5,9,13,17,1,5,9,21,25,29,1,5,9,13,17,1,5,9,21,25,29,1,5,9,13,17,1,5,9,21,25,29,1,5,9,13,17,1,5,9,21,25,29,MN_OVSB_TOKEN,MN_OVSB_TOKEN,MN_OVSB_TOKEN,MN_OVSB_TOKEN}, /* FALCON40 - 1000G*/ 351 }; 352 int falcon_pgw1_ovs_tbl_template[3][48] = { 353 {49,53,57,61,49,53,57,61,49,53,57,61,49,53,57,61,49,53,57,61,49,53,57,61,49,53,57,61,49,53,57,61,49,53,57,61,49,53,57,61,49,53,57,61,49,53,57,61}, /* FALCON32 - 800G */ 354 {45,49,53,57,61,45,49,53,57,61,45,49,53,57,61,45,49,53,57,61,45,49,53,57,61,45,49,53,57,61,45,49,53,57,61,45,49,53,57,61,MN_OVSB_TOKEN,MN_OVSB_TOKEN,MN_OVSB_TOKEN,MN_OVSB_TOKEN,MN_OVSB_TOKEN,MN_OVSB_TOKEN,MN_OVSB_TOKEN,MN_OVSB_TOKEN}, /* FALCON40 - 1000G */ 355 {45,49,53,57,61,45,49,53,33,37,41,45,49,53,57,61,45,49,53,33,37,41,45,49,53,57,61,45,49,53,33,37,41,45,49,53,57,61,45,49,53,33,37,41,MN_OVSB_TOKEN,MN_OVSB_TOKEN,MN_OVSB_TOKEN,MN_OVSB_TOKEN}, /* FALCON40 - 1000G */ 356 }; 357 358 tdm_mn_check_mv_fb_config(&mn_pgw_os_tdm_sel, _mn_chip, _tdm); 359 switch(_tdm->_chip_data.soc_pkg.soc_vars.mn.sku_core_bw) { 360 case 0: /* Backward compatibility */ 361 switch(pgw_num){ 362 case 0: 363 tdm_mn_falcon_32_40_ovs_tbl(_mn_chip, ovs_tdm_tbl, (unsigned int *) falcon_pgw0_ovs_tbl_template[mn_pgw_os_tdm_sel], &mn_pgw_os_tdm_sel, pgw_num, is_falcon_32_40); 364 tdm_mn_falcon_32_40_ovs_tbl_spacing(ovs_tdm_tbl, ovs_spacing); 365 tdm_mn_tdm_print((int*) falcon_pgw0_ovs_tbl_template[mn_pgw_os_tdm_sel], 48); 366 tdm_mn_tdm_print(ovs_tdm_tbl, 48); 367 tdm_mn_tdm_print(ovs_spacing, 48); 368 break; 369 case 1: 370 tdm_mn_falcon_32_40_ovs_tbl(_mn_chip, ovs_tdm_tbl, (unsigned int*) falcon_pgw1_ovs_tbl_template[mn_pgw_os_tdm_sel], &mn_pgw_os_tdm_sel, pgw_num, is_falcon_32_40); 371 tdm_mn_falcon_32_40_ovs_tbl_spacing(ovs_tdm_tbl, ovs_spacing); 372 tdm_mn_tdm_print(falcon_pgw1_ovs_tbl_template[mn_pgw_os_tdm_sel], 48); 373 tdm_mn_tdm_print(ovs_tdm_tbl, 48); 374 tdm_mn_tdm_print(ovs_spacing, 48); 375 break; 376 } 377 break; 378 default: 379 switch(pgw_num){ 380 case 0: 381 tdm_mn_ovs_tbl(_mn_chip, ovs_tdm_tbl, (unsigned int *) falcon_pgw0_ovs_tbl_template[mn_pgw_os_tdm_sel], &mn_pgw_os_tdm_sel, pgw_num); 382 tdm_mn_ovs_tbl_spacing(ovs_tdm_tbl, ovs_spacing); 383 TDM_PRINT0("\n========================================================================\n"); 384 tdm_mn_tdm_print((int*) falcon_pgw0_ovs_tbl_template[mn_pgw_os_tdm_sel], 48); 385 TDM_PRINT0("\n========================================================================\n"); 386 tdm_mn_tdm_print(ovs_tdm_tbl, 48); 387 TDM_PRINT0("\n========================================================================\n"); 388 tdm_mn_tdm_print(ovs_spacing, 48); 389 TDM_PRINT0("\n========================================================================\n"); 390 break; 391 case 1: 392 tdm_mn_ovs_tbl(_mn_chip, ovs_tdm_tbl, (unsigned int*) falcon_pgw1_ovs_tbl_template[mn_pgw_os_tdm_sel], &mn_pgw_os_tdm_sel, pgw_num); 393 tdm_mn_ovs_tbl_spacing(ovs_tdm_tbl, ovs_spacing); 394 TDM_PRINT0("\n========================================================================\n"); 395 tdm_mn_tdm_print(falcon_pgw1_ovs_tbl_template[mn_pgw_os_tdm_sel], 48); 396 TDM_PRINT0("\n========================================================================\n"); 397 tdm_mn_tdm_print(ovs_tdm_tbl, 48); 398 TDM_PRINT0("\n========================================================================\n"); 399 tdm_mn_tdm_print(ovs_spacing, 48); 400 TDM_PRINT0("\n========================================================================\n"); 401 break; 402 } 403 break; 404 } 405 } 406 407 void tdm_mn_falcon_32_40_ovs_tbl(tdm_mn_chip_legacy_t *mn_chip,int *ovs_tdm_tbl, unsigned int *pgw0_ovs_tbl_template, mn_pgw_os_tdm_sel_e *mn_pgw_os_tdm_sel, int pgw_num, int * is_falcon_32_40) 408 { 409 int i, j, token; 410 for(i=0; i<48; i++) { 411 ovs_tdm_tbl[i] = pgw0_ovs_tbl_template[i]; 412 } 413 for(i=1; i<= MN_NUM_PHY_PORTS; i=i+4) { 414 switch((*mn_chip).tdm_globals.speed[i]){ 415 case SPEED_100G: /*As template is having all Single mode port entries and 100/40G ports in single modes so skip processing */ 416 for (j=0, token=0; j<48;j++) { 417 if (ovs_tdm_tbl[j] == i) { 418 token++; 419 if(*is_falcon_32_40 == 1){ 420 if (token>10) ovs_tdm_tbl[j]= MN_OVSB_TOKEN; /* Inline-edit template has 12 slots allocated for 100G ports in template. This would eatup bandwidth of other low-speed ports. To avoid the BW loss on low speed ports, 100G port should get only 10 slots. */ 421 } else if(*is_falcon_32_40 == 0){ 422 if (token>8) ovs_tdm_tbl[j]= MN_OVSB_TOKEN; /* Falcon-40 has per slot BW of 12.5G so max slots for 100G or 4x25 port is 8 slots*/ 423 } 424 } 425 } 426 break; 427 case SPEED_40G: 428 if (mn_is_clport( i )) { /* Only for Falcon ports enter this processing. Reduce the tokens from 8 to 4 */ 429 for (j=0, token=0; j<48;j++) { 430 if (ovs_tdm_tbl[j] == i) { 431 token++; 432 if (token>4) ovs_tdm_tbl[j]= MN_OVSB_TOKEN; /* To handle FB5 config: Falcon ports can be configured in 40G mode*/ 433 else if (token%2) ovs_tdm_tbl[j]= ((*mn_chip).tdm_globals.speed[i+2] == SPEED_40G) ? i+2 : i; 434 } 435 } 436 } 437 break; 438 case SPEED_50G: 439 for (j=0, token=0; j<48;j++) { 440 if (ovs_tdm_tbl[j] == i) { 441 token++; 442 if(*is_falcon_32_40 == 1) { 443 if (token>10) ovs_tdm_tbl[j]= MN_OVSB_TOKEN; 444 else if (token%2) ovs_tdm_tbl[j]=i; 445 else ovs_tdm_tbl[j]=((*mn_chip).tdm_globals.speed[i+2] == SPEED_50G) ? i+2: 446 ((*mn_chip).tdm_globals.speed[i+1] == SPEED_25G) ? i+1 : 447 ((*mn_chip).tdm_globals.speed[i+3] == SPEED_25G) ? i+3 : MN_OVSB_TOKEN /*IDLE Port*/; 448 } else if(*is_falcon_32_40 == 0){ 449 if (token>8) ovs_tdm_tbl[j]= MN_OVSB_TOKEN; 450 switch (token) { 451 case 1: 452 case 3: 453 ovs_tdm_tbl[j] = i; 454 break; 455 case 2: 456 case 4: 457 ovs_tdm_tbl[j] = ((*mn_chip).tdm_globals.speed[i+2] == SPEED_50G) ? i+2 : 458 ((*mn_chip).tdm_globals.speed[i+2] == SPEED_25G && token == 2) ? i+2: 459 ((*mn_chip).tdm_globals.speed[i+3] == SPEED_25G && token == 4) ? i+3: 460 ((*mn_chip).tdm_globals.speed[i+2] <= SPEED_10G && token == 4) ? i+2: /* 1x50+2x10/5/2.5/1G */ 461 MN_OVSB_TOKEN; 462 break; 463 case 5: 464 case 7: 465 ovs_tdm_tbl[j] = i; 466 break; 467 case 6: 468 case 8: 469 ovs_tdm_tbl[j] = ((*mn_chip).tdm_globals.speed[i+2] == SPEED_50G) ? i+2 : 470 ((*mn_chip).tdm_globals.speed[i+2] == SPEED_25G && token == 6) ? i+2: 471 ((*mn_chip).tdm_globals.speed[i+3] == SPEED_25G && token == 8) ? i+3: 472 ((*mn_chip).tdm_globals.speed[i+3] <= SPEED_10G && token == 8) ? i+3: /* 1x50+2x10/5/2.5/1G */ 473 MN_OVSB_TOKEN; 474 break; 475 } 476 } 477 } 478 } 479 break; 480 case SPEED_25G: 481 if (mn_is_clport( i )) { /* Only for Falcon ports enter this processing */ 482 for (j=0, token=0; j<48;j++) { 483 if (ovs_tdm_tbl[j] == i) { 484 token++; 485 if(*is_falcon_32_40 == 1) { 486 switch (token) { 487 case 1: 488 case 5: 489 case 9: /* 25 G*/ 490 ovs_tdm_tbl[j] = i; 491 break; 492 case 2: 493 case 6: 494 case 10: /* Check for 50G first, then check for 25G */ 495 ovs_tdm_tbl[j] = ((*mn_chip).tdm_globals.speed[i+2] == SPEED_50G) ? i+2 : 496 ((*mn_chip).tdm_globals.speed[i+2] == SPEED_25G) ? i+2 : 497 ((*mn_chip).tdm_globals.speed[i+2] <= SPEED_10G && token ==2) ? i+2: /* 2x25+2x10 (P0 P2 P1 P3 -- P0,P1 25G and P2 P3 10G */ 498 ((*mn_chip).tdm_globals.speed[i+3] <= SPEED_10G && token ==6) ? i+3: /* 2x25+2x10 (P0 P2 P1 P3 -- P0,P1 25G and P2 P3 10G */ 499 MN_OVSB_TOKEN /*IDLE port*/; 500 break; 501 case 3: 502 case 7: 503 case 11: /* Say PM port 1, 2, 3, 4 are in trimode. then the mapping should be 1,3,2,3 considering port 3 as 50G port */ 504 ovs_tdm_tbl[j] = ((*mn_chip).tdm_globals.speed[i+1] == SPEED_25G) ? i+1 : MN_OVSB_TOKEN; 505 break; 506 case 4: 507 case 8: 508 case 12: /* Check for 50G first, then check for 25G */ 509 ovs_tdm_tbl[j] = ((*mn_chip).tdm_globals.speed[i+2] == SPEED_50G) ? i+2 : 510 ((*mn_chip).tdm_globals.speed[i+3] == SPEED_25G) ? i+3 : MN_OVSB_TOKEN; 511 break; 512 } 513 } else if(*is_falcon_32_40 == 0){ /* only 8 token in falcon40 */ 514 switch (token) { 515 case 1: 516 case 5: 517 ovs_tdm_tbl[j] = i; 518 break; 519 case 2: 520 case 6: 521 ovs_tdm_tbl[j] = ((*mn_chip).tdm_globals.speed[i+2] == SPEED_50G) ? i+2 : 522 ((*mn_chip).tdm_globals.speed[i+2] == SPEED_25G) ? i+2 : 523 ((*mn_chip).tdm_globals.speed[i+2] <= SPEED_10G && token ==2) ? i+2: /* 2x25+2x10 (P0 P2 P1 P3 -- P0,P1 25G and P2 P3 10G */ 524 MN_OVSB_TOKEN /*IDLE port*/; 525 break; 526 case 3: 527 case 7: 528 ovs_tdm_tbl[j] = ((*mn_chip).tdm_globals.speed[i+1] == SPEED_25G) ? i+1 : MN_OVSB_TOKEN; 529 break; 530 case 4: 531 case 8: 532 ovs_tdm_tbl[j] = ((*mn_chip).tdm_globals.speed[i+2] == SPEED_50G) ? i+2 : 533 ((*mn_chip).tdm_globals.speed[i+3] == SPEED_25G) ? i+3 : 534 ((*mn_chip).tdm_globals.speed[i+3] <= SPEED_10G && token ==4) ? i+3 : 535 MN_OVSB_TOKEN; 536 break; 537 } 538 } 539 } 540 } 541 } else { 542 /* For Eagle - insert one IDLE slot out of 4 valid slots*/ 543 /* No spacing rules applicable in OS calendar.*/ 544 for (j=0, token=0; j<48;j++) { 545 if (ovs_tdm_tbl[j] == i) { 546 ovs_tdm_tbl[j] = MN_OVSB_TOKEN; 547 break; 548 } 549 } 550 } 551 break; 552 case SPEED_20G: 553 for (j=0, token=0; j<48;j++) { 554 if (ovs_tdm_tbl[j] == i) { 555 token++; 556 if ((mn_is_clport( i )) && token>4) ovs_tdm_tbl[j] = MN_OVSB_TOKEN; /* Falcon ports when configured as 20G dont require more than 4 tokens (2x20G)*/ 557 else if (token%2) ovs_tdm_tbl[j]=i; 558 else ovs_tdm_tbl[j]=((*mn_chip).tdm_globals.speed[i+2] == SPEED_20G) ? i+2: 559 ((*mn_chip).tdm_globals.speed[i+1] <= SPEED_10G && (*mn_chip).tdm_globals.speed[i+1] != SPEED_0) ? i+1 : 560 ((*mn_chip).tdm_globals.speed[i+3] <= SPEED_10G && (*mn_chip).tdm_globals.speed[i+3] != SPEED_0) ? i+3 : MN_OVSB_TOKEN /*IDLE Port*/; 561 } 562 } 563 break; 564 case SPEED_10G: 565 case SPEED_1G: 566 case SPEED_2p5G: 567 case SPEED_5G: 568 for (j=0, token=0; j<48;j++) { 569 if (ovs_tdm_tbl[j] == i) { 570 if((*mn_chip).tdm_globals.port_rates_array[i] == PORT_STATE__LINERATE){ 571 ovs_tdm_tbl[j] = MN_OVSB_TOKEN; 572 continue; 573 } 574 token++; 575 if(*is_falcon_32_40 == 1) { 576 switch (token) { 577 case 1: 578 case 5: 579 case 9: /* 10G*/ 580 ovs_tdm_tbl[j] = ((*mn_chip).tdm_globals.speed[i] <= SPEED_10G) ? i : MN_OVSB_TOKEN; 581 break; 582 case 2: 583 case 6: 584 case 10: /* Check for 50G first, then check for 25G */ 585 ovs_tdm_tbl[j] = ((*mn_chip).tdm_globals.speed[i+2] == SPEED_50G) ? i+2 : 586 ((*mn_chip).tdm_globals.speed[i+2] == SPEED_25G) ? i+2 : 587 ((*mn_chip).tdm_globals.speed[i+2] <= SPEED_10G) ? i+2 : 588 MN_OVSB_TOKEN; 589 break; 590 case 3: 591 case 7: 592 case 11: 593 ovs_tdm_tbl[j] = ((*mn_chip).tdm_globals.speed[i+3] <= SPEED_10G) ? i+3 : MN_OVSB_TOKEN; 594 break; 595 case 4: 596 case 8: 597 case 12: /* Check for 50G first, then check for 25G */ 598 ovs_tdm_tbl[j] = 599 ((*mn_chip).tdm_globals.speed[i+3] == SPEED_50G && token != 12) ? i+3 : 600 ((*mn_chip).tdm_globals.speed[i+3] == SPEED_25G) ? i+3 : 601 ((*mn_chip).tdm_globals.speed[i+3] <= SPEED_10G) ? i+3 : 602 MN_OVSB_TOKEN; 603 break; 604 } 605 } else if(*is_falcon_32_40 == 0){ 606 switch (token) { 607 case 1: 608 case 5: 609 ovs_tdm_tbl[j] = ((*mn_chip).tdm_globals.speed[i] <= SPEED_10G && token == 1) ? i : MN_OVSB_TOKEN; 610 break; 611 case 2: 612 case 6: 613 ovs_tdm_tbl[j] = ((*mn_chip).tdm_globals.speed[i+2] == SPEED_50G) ? i+2 : 614 ((*mn_chip).tdm_globals.speed[i+2] == SPEED_25G) ? i+2 : 615 ((*mn_chip).tdm_globals.speed[i+2] <= SPEED_10G) ? i+2 : 616 MN_OVSB_TOKEN; 617 break; 618 case 3: 619 case 7: 620 ovs_tdm_tbl[j] = ((*mn_chip).tdm_globals.speed[i+1] <= SPEED_10G && token == 3) ? i+1 : MN_OVSB_TOKEN; 621 break; 622 case 4: 623 case 8: 624 ovs_tdm_tbl[j] = 625 ((*mn_chip).tdm_globals.speed[i+2] == SPEED_50G) ? i+2 : 626 ((*mn_chip).tdm_globals.speed[i+3] == SPEED_25G) ? i+3 : 627 ((*mn_chip).tdm_globals.speed[i+3] <= SPEED_10G) ? i+3 : 628 MN_OVSB_TOKEN; 629 break; 630 } 631 } 632 } 633 } 634 break; 635 case SPEED_0: 636 for (j=0; j<48;j++) { 637 if (ovs_tdm_tbl[j] == i) { 638 ovs_tdm_tbl[j] = MN_OVSB_TOKEN; 639 } 640 } 641 break; 642 default: 643 break; 644 } 645 646 } 647 } 648 649 650 void tdm_mn_ovs_tbl(tdm_mn_chip_legacy_t *mn_chip,int *ovs_tdm_tbl, unsigned int *pgw0_ovs_tbl_template, mn_pgw_os_tdm_sel_e *mn_pgw_os_tdm_sel, int pgw_num) 651 { 652 int i, j, token; 653 for(i=0; i<48; i++) { 654 ovs_tdm_tbl[i] = pgw0_ovs_tbl_template[i]; 655 } 656 for(i=1; i<= MN_NUM_PHY_PORTS; i=i+4) { 657 switch((*mn_chip).tdm_globals.speed[i]){ 658 case SPEED_100G: 659 for (j=0, token=0; j<48;j++) { 660 if (ovs_tdm_tbl[j] == i) { 661 token++; 662 if(mn_is_tscf_3_or_4(i) && token > 4) { 663 ovs_tdm_tbl[j] = MN_OVSB_TOKEN; 664 } else if(mn_is_tscf_3_or_4(i) == 0 && token > 8) { 665 ovs_tdm_tbl[j]= MN_OVSB_TOKEN; 666 } 667 } 668 } 669 break; 670 case SPEED_40G: 671 for (j=0, token=0; j<48;j++) { 672 if (ovs_tdm_tbl[j] == i) { 673 token++; 674 if (token>8) ovs_tdm_tbl[j]= MN_OVSB_TOKEN; 675 switch (token) { 676 case 1: 677 case 3: 678 ovs_tdm_tbl[j] = i; 679 break; 680 case 2: 681 case 4: 682 ovs_tdm_tbl[j] = ((*mn_chip).tdm_globals.speed[i+2] == SPEED_40G) ? i+2: 683 MN_OVSB_TOKEN; 684 break; 685 case 5: 686 case 7: 687 ovs_tdm_tbl[j] = i; 688 break; 689 case 6: 690 case 8: 691 ovs_tdm_tbl[j] = ((*mn_chip).tdm_globals.speed[i+2] == SPEED_40G) ? i+2: 692 MN_OVSB_TOKEN; 693 break; 694 } 695 } 696 } 697 break; 698 case SPEED_50G: 699 for (j=0, token=0; j<48;j++) { 700 if (ovs_tdm_tbl[j] == i) { 701 token++; 702 if (token>8) ovs_tdm_tbl[j]= MN_OVSB_TOKEN; 703 if(mn_is_tscf_3_or_4(i) == 0) { 704 switch (token) { 705 case 1: 706 case 3: 707 ovs_tdm_tbl[j] = i; 708 break; 709 case 2: 710 case 4: 711 ovs_tdm_tbl[j] = ((*mn_chip).tdm_globals.speed[i+2] == SPEED_50G) ? i+2: 712 ((*mn_chip).tdm_globals.speed[i+2] == SPEED_25G && token == 2) ? i+2: 713 ((*mn_chip).tdm_globals.speed[i+3] == SPEED_25G) ? i+3: 714 (((*mn_chip).tdm_globals.speed[i+2] <= SPEED_10G && token == 2) && ((*mn_chip).tdm_globals.speed[i+2] != SPEED_0)) ? i+2: 715 (((*mn_chip).tdm_globals.speed[i+3] <= SPEED_10G && token == 4) && ((*mn_chip).tdm_globals.speed[i+3] != SPEED_0)) ? i+3: 716 MN_OVSB_TOKEN; 717 break; 718 case 5: 719 case 7: 720 ovs_tdm_tbl[j] = i; 721 break; 722 case 6: 723 case 8: 724 ovs_tdm_tbl[j] = ((*mn_chip).tdm_globals.speed[i+2] == SPEED_50G) ? i+2: 725 ((*mn_chip).tdm_globals.speed[i+2] == SPEED_25G) ? i+2: 726 ((*mn_chip).tdm_globals.speed[i+3] == SPEED_25G) ? i+3: 727 MN_OVSB_TOKEN; 728 break; 729 } 730 } else if (mn_is_tscf_3_or_4(i) == 1) { 731 switch (token) { 732 case 1: 733 case 3: 734 ovs_tdm_tbl[j] = i; 735 break; 736 case 2: 737 ovs_tdm_tbl[j] = ((*mn_chip).tdm_globals.speed[i+2] == SPEED_50G) ? i+2 : 738 ((*mn_chip).tdm_globals.speed[i+2] == SPEED_25G) ? i+2: 739 (((*mn_chip).tdm_globals.speed[i+2] <= SPEED_10G) && ((*mn_chip).tdm_globals.speed[i+2] != SPEED_0)) ? i+2: /* 1x50+2x10/5/2.5/1G */ 740 MN_OVSB_TOKEN; 741 break; 742 case 4: 743 ovs_tdm_tbl[j] = ((*mn_chip).tdm_globals.speed[i+2] == SPEED_50G) ? i+2 : 744 ((*mn_chip).tdm_globals.speed[i+3] == SPEED_25G) ? i+3: 745 (((*mn_chip).tdm_globals.speed[i+3] <= SPEED_10G) && ((*mn_chip).tdm_globals.speed[i+3] != SPEED_0)) ? i+3: /* 1x50+2x10/5/2.5/1G */ 746 MN_OVSB_TOKEN; 747 break; 748 } 749 } 750 } 751 } 752 break; 753 case SPEED_25G: 754 /*if (mn_is_clport( i )) {*/ 755 for (j=0, token=0; j<48;j++) { 756 if (ovs_tdm_tbl[j] == i) { 757 token++; 758 if(mn_is_tscf_3_or_4(i) == 1) { 759 switch(token){ 760 case 1: 761 ovs_tdm_tbl[j] = i; 762 break; 763 case 2: 764 ovs_tdm_tbl[j] = i+2; 765 break; 766 case 3: 767 ovs_tdm_tbl[j] = i+1; 768 break; 769 case 4: 770 ovs_tdm_tbl[j] = ((*mn_chip).tdm_globals.speed[i+2] == SPEED_50G) ? i+2 : 771 ((*mn_chip).tdm_globals.speed[i+3] == SPEED_25G) ? i+3 : 772 ((*mn_chip).tdm_globals.speed[i+2] == SPEED_25G) ? i+2 : 773 ((*mn_chip).tdm_globals.speed[i] <= SPEED_10G && (*mn_chip).tdm_globals.speed[i] != SPEED_0) ? i: 774 ((*mn_chip).tdm_globals.speed[i+3] <= SPEED_10G && (*mn_chip).tdm_globals.speed[i+3] != SPEED_0) ? i+3: MN_OVSB_TOKEN; 775 break; 776 } 777 } else { 778 switch (token) { 779 case 1: 780 if(mn_is_tscf_3_or_4(i) == 0) { 781 ovs_tdm_tbl[j] = ((*mn_chip).tdm_globals.speed[i] == SPEED_25G) ? i : MN_OVSB_TOKEN; 782 } 783 break; 784 case 2: 785 if(mn_is_tscf_3_or_4(i) == 0) { 786 ovs_tdm_tbl[j] = ((*mn_chip).tdm_globals.speed[i+2] == SPEED_50G) ? i+2 : 787 ((*mn_chip).tdm_globals.speed[i+2] == SPEED_25G) ? i+2 : 788 ((*mn_chip).tdm_globals.speed[i+2] <= SPEED_10G && (*mn_chip).tdm_globals.speed[i+2] != SPEED_0) ? i+2: 789 MN_OVSB_TOKEN; 790 } 791 break; 792 case 3: 793 if(mn_is_tscf_3_or_4(i) == 0) { 794 ovs_tdm_tbl[j] = ((*mn_chip).tdm_globals.speed[i+1] == SPEED_25G) ? i+1 : 795 ((*mn_chip).tdm_globals.speed[i+1] <= SPEED_10G && (*mn_chip).tdm_globals.speed[i+1] != SPEED_0) ? i+1: MN_OVSB_TOKEN; 796 } 797 break; 798 case 4: 799 if(mn_is_tscf_3_or_4(i) == 0) { 800 ovs_tdm_tbl[j] = ((*mn_chip).tdm_globals.speed[i+2] == SPEED_50G) ? i+2 : 801 ((*mn_chip).tdm_globals.speed[i+3] == SPEED_25G) ? i+3 : 802 ((*mn_chip).tdm_globals.speed[i+3] <= SPEED_10G && (*mn_chip).tdm_globals.speed[i+3] != SPEED_0) ? i+3 : 803 MN_OVSB_TOKEN; 804 } 805 break; 806 case 5: 807 if(mn_is_tscf_3_or_4(i) == 0) { 808 ovs_tdm_tbl[j] = ((*mn_chip).tdm_globals.speed[i] == SPEED_25G) ? i : MN_OVSB_TOKEN; 809 } 810 break; 811 case 6: 812 if(mn_is_tscf_3_or_4(i) == 0) { 813 ovs_tdm_tbl[j] = ((*mn_chip).tdm_globals.speed[i+2] == SPEED_50G) ? i+2 : 814 ((*mn_chip).tdm_globals.speed[i+2] == SPEED_25G) ? i+2 : 815 MN_OVSB_TOKEN; 816 } 817 break; 818 case 7: 819 if(mn_is_tscf_3_or_4(i) == 0) { 820 ovs_tdm_tbl[j] = ((*mn_chip).tdm_globals.speed[i+1] == SPEED_25G) ? i+1 : MN_OVSB_TOKEN; 821 } 822 break; 823 case 8: 824 if(mn_is_tscf_3_or_4(i) == 0) { 825 ovs_tdm_tbl[j] = ((*mn_chip).tdm_globals.speed[i+2] == SPEED_50G) ? i+2 : 826 ((*mn_chip).tdm_globals.speed[i+3] == SPEED_25G) ? i+3 : 827 MN_OVSB_TOKEN; 828 } 829 break; 830 } 831 } 832 } 833 } 834 /*} else { 835 for (j=0, token=0; j<48;j++) { 836 if (ovs_tdm_tbl[j] == i) { 837 ovs_tdm_tbl[j] = MN_OVSB_TOKEN; 838 break; 839 } 840 } 841 }*/ 842 break; 843 case SPEED_20G: 844 for (j=0, token=0; j<48;j++) { 845 if (ovs_tdm_tbl[j] == i) { 846 token++; 847 if(mn_is_tscf_3_or_4(i) == 0) { 848 switch (token) { 849 case 1: case 3: 850 ovs_tdm_tbl[j] = ((*mn_chip).tdm_globals.speed[i] == SPEED_20G) ? i : 851 MN_OVSB_TOKEN; 852 break; 853 case 2: case 4: 854 ovs_tdm_tbl[j] = ((*mn_chip).tdm_globals.speed[i+2] == SPEED_50G) ? i+2 : 855 ((*mn_chip).tdm_globals.speed[i+2] == SPEED_25G && token == 2) ? i+2 : 856 ((*mn_chip).tdm_globals.speed[i] == SPEED_20G && token == 2) ? i+2 : 857 ((*mn_chip).tdm_globals.speed[i+3] == SPEED_25G) ? i+3 : 858 ((*mn_chip).tdm_globals.speed[i+2] <= SPEED_10G && token == 2 && (*mn_chip).tdm_globals.speed[i+2] != SPEED_0) ? i+2: 859 ((*mn_chip).tdm_globals.speed[i+3] <= SPEED_10G && (*mn_chip).tdm_globals.speed[i+3] != SPEED_0) ? i+3: 860 MN_OVSB_TOKEN; 861 break; 862 case 5: case 7: 863 ovs_tdm_tbl[j] = MN_OVSB_TOKEN; 864 break; 865 case 6: case 8: 866 ovs_tdm_tbl[j] = ((*mn_chip).tdm_globals.speed[i+2] == SPEED_50G) ? i+2 : 867 ((*mn_chip).tdm_globals.speed[i+2] == SPEED_25G && token == 6) ? i+2 : 868 ((*mn_chip).tdm_globals.speed[i+3] == SPEED_25G) ? i+3 : 869 MN_OVSB_TOKEN; 870 break; 871 } 872 } else if (mn_is_tscf_3_or_4(i) == 1) { 873 switch (token) { 874 case 1: 875 ovs_tdm_tbl[j] = ((*mn_chip).tdm_globals.speed[i] == SPEED_20G) ? i : MN_OVSB_TOKEN; 876 break; 877 case 2: 878 ovs_tdm_tbl[j] = ((*mn_chip).tdm_globals.speed[i+2] == SPEED_50G) ? i+2 : 879 ((*mn_chip).tdm_globals.speed[i+2] == SPEED_25G) ? i+2 : 880 ((*mn_chip).tdm_globals.speed[i+2] == SPEED_20G) ? i+2 : 881 ((*mn_chip).tdm_globals.speed[i+2] <= SPEED_10G && (*mn_chip).tdm_globals.speed[i+2] != SPEED_0) ? i+2: 882 MN_OVSB_TOKEN; 883 break; 884 case 3: 885 ovs_tdm_tbl[j] = ((*mn_chip).tdm_globals.speed[i] == SPEED_20G) ? i : 886 ((*mn_chip).tdm_globals.speed[i+1] == SPEED_20G) ? i+1 : 887 MN_OVSB_TOKEN; 888 break; 889 case 4: 890 ovs_tdm_tbl[j] = ((*mn_chip).tdm_globals.speed[i+2] == SPEED_50G) ? i+2 : 891 ((*mn_chip).tdm_globals.speed[i+3] == SPEED_25G) ? i+3 : 892 ((*mn_chip).tdm_globals.speed[i+2] == SPEED_20G) ? i+2 : 893 ((*mn_chip).tdm_globals.speed[i+3] <= SPEED_10G && (*mn_chip).tdm_globals.speed[i+3] != SPEED_0) ? i+3: 894 MN_OVSB_TOKEN; 895 break; 896 } 897 } 898 } 899 } 900 break; 901 case SPEED_10G: 902 case SPEED_1G: 903 case SPEED_2p5G: 904 case SPEED_5G: 905 for (j=0, token=0; j<48;j++) { 906 if (ovs_tdm_tbl[j] == i) { 907 if((*mn_chip).tdm_globals.port_rates_array[i] == PORT_STATE__LINERATE){ 908 ovs_tdm_tbl[j] = MN_OVSB_TOKEN; 909 continue; 910 } 911 token++; 912 if(mn_is_tscf_3_or_4(i) == 0) { 913 switch (token) { 914 case 1: 915 ovs_tdm_tbl[j] = ((*mn_chip).tdm_globals.speed[i] <= SPEED_10G && (*mn_chip).tdm_globals.speed[i] != SPEED_0) ? i : MN_OVSB_TOKEN; 916 break; 917 case 2: 918 ovs_tdm_tbl[j] = ((*mn_chip).tdm_globals.speed[i+2] == SPEED_50G) ? i+2 : 919 ((*mn_chip).tdm_globals.speed[i+2] == SPEED_25G) ? i+2 : 920 ((*mn_chip).tdm_globals.speed[i+2] == SPEED_20G) ? i+2 : 921 ((*mn_chip).tdm_globals.speed[i+2] <= SPEED_10G && (*mn_chip).tdm_globals.speed[i+2] != SPEED_0) ? i+2 : 922 MN_OVSB_TOKEN; 923 break; 924 case 3: 925 ovs_tdm_tbl[j] = ((*mn_chip).tdm_globals.speed[i+1] <= SPEED_25G) ? i+1 : 926 ((*mn_chip).tdm_globals.speed[i+1] <= SPEED_10G && (*mn_chip).tdm_globals.speed[i+1] != SPEED_0) ? i+1 : MN_OVSB_TOKEN; 927 break; 928 case 4: 929 ovs_tdm_tbl[j] = 930 ((*mn_chip).tdm_globals.speed[i+2] == SPEED_50G) ? i+2 : 931 ((*mn_chip).tdm_globals.speed[i+3] == SPEED_25G) ? i+3 : 932 ((*mn_chip).tdm_globals.speed[i+2] == SPEED_20G) ? i+2 : 933 ((*mn_chip).tdm_globals.speed[i+3] <= SPEED_10G && (*mn_chip).tdm_globals.speed[i+3] != SPEED_0) ? i+3 : 934 MN_OVSB_TOKEN; 935 break; 936 case 5: 937 ovs_tdm_tbl[j] = MN_OVSB_TOKEN; 938 break; 939 case 6: 940 ovs_tdm_tbl[j] = ((*mn_chip).tdm_globals.speed[i+2] == SPEED_50G) ? i+2 : 941 ((*mn_chip).tdm_globals.speed[i+2] == SPEED_25G) ? i+2 : 942 MN_OVSB_TOKEN; 943 break; 944 case 7: 945 ovs_tdm_tbl[j] = ((*mn_chip).tdm_globals.speed[i+1] == SPEED_25G) ? i+1 : 946 MN_OVSB_TOKEN; 947 break; 948 case 8: 949 ovs_tdm_tbl[j] = ((*mn_chip).tdm_globals.speed[i+2] == SPEED_50G) ? i+2 : 950 ((*mn_chip).tdm_globals.speed[i+3] == SPEED_25G) ? i+3 : 951 MN_OVSB_TOKEN; 952 break; 953 } 954 } else if(mn_is_tscf_3_or_4(i) == 1) { 955 switch (token) { 956 case 1: 957 ovs_tdm_tbl[j] = ((*mn_chip).tdm_globals.speed[i] <= SPEED_10G && (*mn_chip).tdm_globals.speed[i] != SPEED_0) ? i : MN_OVSB_TOKEN; 958 break; 959 case 2: 960 ovs_tdm_tbl[j] = ((*mn_chip).tdm_globals.speed[i+2] == SPEED_50G) ? i+2 : 961 ((*mn_chip).tdm_globals.speed[i+2] == SPEED_25G) ? i+2 : 962 ((*mn_chip).tdm_globals.speed[i+2] == SPEED_20G) ? i+2 : 963 ((*mn_chip).tdm_globals.speed[i+2] <= SPEED_10G && (*mn_chip).tdm_globals.speed[i+2] != SPEED_0) ? i+2 : 964 MN_OVSB_TOKEN; 965 break; 966 case 3: 967 ovs_tdm_tbl[j] = ((*mn_chip).tdm_globals.speed[i+1] <= SPEED_25G) ? i+1 : 968 ((*mn_chip).tdm_globals.speed[i+1] <= SPEED_10G && (*mn_chip).tdm_globals.speed[i+1] != SPEED_0) ? i+1 : MN_OVSB_TOKEN; 969 break; 970 case 4: 971 ovs_tdm_tbl[j] = 972 ((*mn_chip).tdm_globals.speed[i+2] == SPEED_50G) ? i+2 : 973 ((*mn_chip).tdm_globals.speed[i+3] == SPEED_25G) ? i+3 : 974 ((*mn_chip).tdm_globals.speed[i+2] == SPEED_20G) ? i+2 : 975 ((*mn_chip).tdm_globals.speed[i+3] <= SPEED_10G && (*mn_chip).tdm_globals.speed[i+3] != SPEED_0) ? i+3 : 976 MN_OVSB_TOKEN; 977 break; 978 } 979 } 980 } 981 } 982 break; 983 case SPEED_0: 984 for (j=0; j<48;j++) { 985 if (ovs_tdm_tbl[j] == i) { 986 ovs_tdm_tbl[j] = MN_OVSB_TOKEN; 987 } 988 } 989 break; 990 default: 991 break; 992 } 993 } 994 } 995 996 /* Process below OVS Spacing Table */ 997 998 void tdm_mn_falcon_32_40_ovs_tbl_spacing(int *ovs_tdm_tbl, int *ovs_spacing) 999 { 1000 int i, j, wrap_arnd; 1001 for (i=0; i<48; i++ ) { 1002 ovs_spacing[i] =0; 1003 for (j=i+1, wrap_arnd=0; j<=48 && wrap_arnd<2; j++ ) { /* j goes till 48 - to account for wrap-around condition. this is to take care of port slots allocated at the end of calendar*/ 1004 if (j == 48) { 1005 j = -1; 1006 wrap_arnd++; 1007 continue; 1008 } 1009 ovs_spacing[i]++; 1010 if (ovs_tdm_tbl[i] == ovs_tdm_tbl[j]) break; 1011 } 1012 } 1013 1014 } 1015 1016 1017 void tdm_mn_ovs_tbl_spacing(int *ovs_tdm_tbl, int *ovs_spacing) 1018 { 1019 int i, j, wrap_arnd; 1020 for (i=0; i<48; i++ ) { 1021 ovs_spacing[i] =0; 1022 for (j=i+1, wrap_arnd=0; j<=48 && wrap_arnd<2; j++ ) { /* j goes till 48 - to account for wrap-around condition. this is to take care of port slots allocated at the end of calendar*/ 1023 if (j == 48) { 1024 j = -1; 1025 wrap_arnd++; 1026 continue; 1027 } 1028 ovs_spacing[i]++; 1029 if (ovs_tdm_tbl[i] == ovs_tdm_tbl[j]) break; 1030 } 1031 } 1032 1033 } 1034 1035 void 1036 tdm_mn_check_mv_fb_config(mn_pgw_os_tdm_sel_e *mn_pgw_os_tdm_sel, tdm_mn_chip_legacy_t *mn_chip, tdm_mod_t *_tdm) 1037 { 1038 int port_num; 1039 unsigned int num_lr_ports = 0, num_os_ports = 0; 1040 for(port_num=0; port_num< MN_NUM_PHY_PORTS; port_num++) { 1041 if((*mn_chip).tdm_globals.port_rates_array[port_num] == PORT_STATE__OVERSUB || 1042 (*mn_chip).tdm_globals.port_rates_array[port_num] == PORT_STATE__OVERSUB_HG){ 1043 num_os_ports++; 1044 }else if((*mn_chip).tdm_globals.port_rates_array[port_num] == PORT_STATE__LINERATE || 1045 (*mn_chip).tdm_globals.port_rates_array[port_num] == PORT_STATE__LINERATE_HG){ 1046 num_lr_ports++; 1047 } 1048 } 1049 switch ((*mn_chip).tdm_globals.clk_freq) { 1050 case 862:/* with new Inline edit template from Brendan*/ 1051 if(_tdm->_chip_data.soc_pkg.soc_vars.mn.sku_core_bw == 0) { 1052 *mn_pgw_os_tdm_sel = MN_PGW_OS_FALCN_800G; 1053 } else if (_tdm->_chip_data.soc_pkg.soc_vars.mn.sku_core_bw !=0 ){ 1054 *mn_pgw_os_tdm_sel = MN_PGW_OS_1000G; /* New OS config MN_PGW_OS_1000G variable */ 1055 } 1056 break; 1057 /*case 862: 1058 *mn_pgw_os_tdm_sel = MN_PGW_OS_FALCN_1000G; 1059 break;*/ 1060 case 817: case 667: case 450: case 550: 1061 *mn_pgw_os_tdm_sel = MN_PGW_OS_1000G; /* New OS config MN_PGW_OS_1000G variable */ 1062 break; 1063 default: 1064 *mn_pgw_os_tdm_sel = MN_PGW_OS_1000G; /* New OS config MN_PGW_OS_1000G variable */ 1065 break; 1066 } 1067 1068 } 1069 /** 1070 @name: tdm_mn_pmap_transcription 1071 @param: 1072 1073 For Trident2+ BCM56850 1074 Transcription algorithm for generating port module mapping 1075 1076 40G - xxxx 1077 20G - xx 1078 xx 1079 10G - x 1080 x 1081 x 1082 x 1083 1X0G - xxxx_xxxx_xxxx 1084 */ 1085 int 1086 tdm_mn_pmap_transcription( tdm_mod_t *_tdm ) 1087 { 1088 int i, j, last_port=MN_NUM_EXT_PORTS, tsc_active; 1089 int phy_lo, phy_hi, pm_lane_num, bcm_config_check=PASS; 1090 1091 /* Regular ports */ 1092 for (i=1; i<=MN_NUM_PHY_PORTS; i+=MN_NUM_PM_LNS) { 1093 tsc_active=BOOL_FALSE; 1094 for (j=0; j<MN_NUM_PM_LNS; j++) { 1095 if ( _tdm->_chip_data.soc_pkg.state[i+j]==PORT_STATE__LINERATE || _tdm->_chip_data.soc_pkg.state[i+j]==PORT_STATE__OVERSUB || 1096 _tdm->_chip_data.soc_pkg.state[i+j]==PORT_STATE__LINERATE_HG || _tdm->_chip_data.soc_pkg.state[i+j]==PORT_STATE__OVERSUB_HG ){ 1097 tsc_active=BOOL_TRUE; 1098 break; 1099 } 1100 } 1101 if(tsc_active==BOOL_TRUE){ 1102 /*else { */ 1103 if ( _tdm->_chip_data.soc_pkg.speed[i]>SPEED_0 || _tdm->_chip_data.soc_pkg.state[i]==PORT_STATE__DISABLED ) { 1104 for (j=0; j<MN_NUM_PM_LNS; j++) { 1105 switch (_tdm->_chip_data.soc_pkg.state[i+j]) { 1106 case PORT_STATE__LINERATE: 1107 case PORT_STATE__OVERSUB: 1108 case PORT_STATE__LINERATE_HG: 1109 case PORT_STATE__OVERSUB_HG: 1110 _tdm->_chip_data.soc_pkg.pmap[(i-1)/MN_NUM_PM_LNS][j]=(i+j); 1111 last_port=(i+j); 1112 break; 1113 case PORT_STATE__COMBINE: 1114 _tdm->_chip_data.soc_pkg.pmap[(i-1)/MN_NUM_PM_LNS][j]=last_port; 1115 break; 1116 default: 1117 _tdm->_chip_data.soc_pkg.pmap[(i-1)/MN_NUM_PM_LNS][j]=MN_NUM_EXT_PORTS; 1118 break; 1119 } 1120 } 1121 if ( _tdm->_chip_data.soc_pkg.speed[i]>_tdm->_chip_data.soc_pkg.speed[i+2] && _tdm->_chip_data.soc_pkg.speed[i+2]==_tdm->_chip_data.soc_pkg.speed[i+3] && _tdm->_chip_data.soc_pkg.speed[i+2]!=SPEED_0 &&_tdm->_chip_data.soc_pkg.speed[i]>=SPEED_40G ) { 1122 /*_tdm->_chip_data.soc_pkg.pmap[(i-1)/MN_NUM_PM_LNS][1] = _tdm->_chip_data.soc_pkg.pmap[(i-1)/MN_NUM_PM_LNS][2]; 1123 _tdm->_chip_data.soc_pkg.pmap[(i-1)/MN_NUM_PM_LNS][2] = _tdm->_chip_data.soc_pkg.pmap[(i-1)/MN_NUM_PM_LNS][0];*/ 1124 } 1125 else if ( _tdm->_chip_data.soc_pkg.speed[i]==_tdm->_chip_data.soc_pkg.speed[i+1] && _tdm->_chip_data.soc_pkg.speed[i]<_tdm->_chip_data.soc_pkg.speed[i+2] && _tdm->_chip_data.soc_pkg.speed[i]!=SPEED_0 &&_tdm->_chip_data.soc_pkg.speed[i+2]>=SPEED_40G ) { 1126 /*_tdm->_chip_data.soc_pkg.pmap[(i-1)/MN_NUM_PM_LNS][2] = _tdm->_chip_data.soc_pkg.pmap[(i-1)/MN_NUM_PM_LNS][1]; 1127 _tdm->_chip_data.soc_pkg.pmap[(i-1)/MN_NUM_PM_LNS][1] = _tdm->_chip_data.soc_pkg.pmap[(i-1)/MN_NUM_PM_LNS][3]; */ 1128 } 1129 /* dual mode x_x_ */ 1130 else if (_tdm->_chip_data.soc_pkg.speed[i]!=_tdm->_chip_data.soc_pkg.speed[i+1]&&_tdm->_chip_data.soc_pkg.speed[i]==_tdm->_chip_data.soc_pkg.speed[i+2]&&_tdm->_chip_data.soc_pkg.speed[i]>=SPEED_40G) { 1131 _tdm->_chip_data.soc_pkg.pmap[(i-1)/MN_NUM_PM_LNS][1] = _tdm->_chip_data.soc_pkg.pmap[(i-1)/MN_NUM_PM_LNS][3]; 1132 _tdm->_chip_data.soc_pkg.pmap[(i-1)/MN_NUM_PM_LNS][2] = _tdm->_chip_data.soc_pkg.pmap[(i-1)/MN_NUM_PM_LNS][0]; 1133 } 1134 } 1135 } 1136 } 1137 tdm_print_stat( _tdm ); 1138 1139 /* Check if invalid port config exists */ 1140 phy_lo = _tdm->_chip_data.soc_pkg.soc_vars.fp_port_lo; 1141 phy_hi = _tdm->_chip_data.soc_pkg.soc_vars.fp_port_hi; 1142 pm_lane_num= _tdm->_chip_data.soc_pkg.pmap_num_lanes; 1143 for (i=phy_lo; i<=(phy_hi-pm_lane_num); i+=pm_lane_num) { 1144 if (_tdm->_chip_data.soc_pkg.speed[i]==SPEED_0){ 1145 for (j=1; j<pm_lane_num; j++) { 1146 if (_tdm->_chip_data.soc_pkg.speed[i+j]>SPEED_0){ 1147 bcm_config_check = FAIL; 1148 break; 1149 } 1150 } 1151 } 1152 if (bcm_config_check==FAIL){ 1153 TDM_ERROR8("Invalid port configuration, port [%3d, %3d, %3d, %3d], speed [%3dG, %3dG, %3dG, %3dG]\n", 1154 i, i+1, i+2, i+3, 1155 _tdm->_chip_data.soc_pkg.speed[i]/1000, 1156 _tdm->_chip_data.soc_pkg.speed[i+1]/1000, 1157 _tdm->_chip_data.soc_pkg.speed[i+2]/1000, 1158 _tdm->_chip_data.soc_pkg.speed[i+3]/1000); 1159 return FAIL; 1160 } 1161 } 1162 for (i=1; i<=MN_NUM_PHY_PORTS; i+=MN_NUM_PM_LNS) { 1163 if( mn_is_clport( i ) ){ 1164 if ( ( _tdm->_chip_data.soc_pkg.speed[i]>_tdm->_chip_data.soc_pkg.speed[i+2] && _tdm->_chip_data.soc_pkg.speed[i+2]==_tdm->_chip_data.soc_pkg.speed[i+3] && _tdm->_chip_data.soc_pkg.speed[i+2]!=SPEED_0 && _tdm->_chip_data.soc_pkg.speed[i]>=SPEED_40G ) || ( _tdm->_chip_data.soc_pkg.speed[i]==_tdm->_chip_data.soc_pkg.speed[i+1] && _tdm->_chip_data.soc_pkg.speed[i]<_tdm->_chip_data.soc_pkg.speed[i+2] && _tdm->_chip_data.soc_pkg.speed[i]!=SPEED_0 && _tdm->_chip_data.soc_pkg.speed[i+2]>=SPEED_40G )) { 1165 /*TDM_ERROR8("tri port configuration(25GE+50GE)on Falcon not supported in APACHE, port [%3d, %3d, %3d, %3d], speed [%3dG, %3dG, %3dG, %3dG]\n", i, i+1, i+2, i+3, _tdm->_chip_data.soc_pkg.speed[i]/1000, _tdm->_chip_data.soc_pkg.speed[i+1]/1000, _tdm->_chip_data.soc_pkg.speed[i+2]/1000, _tdm->_chip_data.soc_pkg.speed[i+3]/1000);*/ 1166 /*return FAIL; */ 1167 } 1168 } 1169 } 1170 1171 return ( _tdm->_chip_exec[TDM_CHIP_EXEC__INGRESS_WRAP]( _tdm ) ); 1172 } 1173 1174 /** 1175 @name: tdm_chip_mn_init 1176 @param: 1177 */ 1178 int tdm_mn_init( tdm_mod_t *_tdm ) 1179 { 1180 int index; 1181 1182 _tdm->_chip_data.soc_pkg.pmap_num_modules = MN_NUM_PM_MOD; 1183 _tdm->_chip_data.soc_pkg.pmap_num_lanes = MN_NUM_PM_LNS; 1184 _tdm->_chip_data.soc_pkg.pm_num_phy_modules = MN_NUM_PHY_PM; 1185 1186 _tdm->_chip_data.soc_pkg.soc_vars.ovsb_token = MN_OVSB_TOKEN; 1187 _tdm->_chip_data.soc_pkg.soc_vars.idl1_token = MN_IDL1_TOKEN; 1188 _tdm->_chip_data.soc_pkg.soc_vars.idl2_token = MN_IDL2_TOKEN; 1189 _tdm->_chip_data.soc_pkg.soc_vars.ancl_token = MN_ANCL_TOKEN; 1190 _tdm->_chip_data.soc_pkg.soc_vars.fp_port_lo = 1; 1191 _tdm->_chip_data.soc_pkg.soc_vars.fp_port_hi = MN_NUM_PHY_PORTS; 1192 1193 _tdm->_chip_data.cal_0.cal_len = MN_LR_LLS_LEN; 1194 _tdm->_chip_data.cal_0.grp_num = MN_OS_LLS_GRP_NUM; 1195 _tdm->_chip_data.cal_0.grp_len = MN_OS_LLS_GRP_LEN; 1196 _tdm->_chip_data.cal_1.cal_len = MN_LR_LLS_LEN; 1197 _tdm->_chip_data.cal_1.grp_num = MN_OS_LLS_GRP_NUM; 1198 _tdm->_chip_data.cal_1.grp_len = MN_OS_LLS_GRP_LEN; 1199 _tdm->_chip_data.cal_2.cal_len = MN_LR_VBS_LEN; 1200 _tdm->_chip_data.cal_2.grp_num = MN_OS_VBS_GRP_NUM; 1201 _tdm->_chip_data.cal_2.grp_len = MN_OS_VBS_GRP_LEN; 1202 _tdm->_chip_data.cal_3.cal_len = MN_LR_IARB_STATIC_LEN; 1203 _tdm->_chip_data.cal_3.grp_num = 0; 1204 _tdm->_chip_data.cal_3.grp_len = 0; 1205 1206 1207 _tdm->_core_data.vars_pkg.pipe = 0; 1208 _tdm->_core_data.rule__same_port_min = MN_MIN_SPACING_SAME_PORT_HSP; 1209 _tdm->_core_data.rule__prox_port_min = MN_MIN_SPACING_SISTER_PORT; 1210 _tdm->_core_data.vmap_max_wid = MN_VMAP_MAX_WID; 1211 _tdm->_core_data.vmap_max_len = MN_VMAP_MAX_LEN; 1212 1213 /* management port state */ 1214 /*if (_tdm->_chip_data.soc_pkg.speed[MN_MGMT_PORT_0] > SPEED_0 && 1215 _tdm->_chip_data.soc_pkg.speed[MN_MGMT_PORT_0]<= SPEED_10G && 1216 _tdm->_chip_data.soc_pkg.speed[MN_MGMT_PORT_1]==_tdm->_chip_data.soc_pkg.speed[MN_MGMT_PORT_2] && 1217 _tdm->_chip_data.soc_pkg.speed[MN_MGMT_PORT_2]==_tdm->_chip_data.soc_pkg.speed[MN_MGMT_PORT_3] ){ 1218 if (_tdm->_chip_data.soc_pkg.speed[MN_MGMT_PORT_0]==SPEED_10G && _tdm->_chip_data.soc_pkg.speed[MN_MGMT_PORT_1]==SPEED_0){ 1219 _tdm->_chip_data.soc_pkg.state[MN_MGMT_PORT_0] = PORT_STATE__MANAGEMENT; 1220 _tdm->_chip_data.soc_pkg.state[MN_MGMT_PORT_1] = PORT_STATE__DISABLED; 1221 _tdm->_chip_data.soc_pkg.state[MN_MGMT_PORT_2] = PORT_STATE__DISABLED; 1222 _tdm->_chip_data.soc_pkg.state[MN_MGMT_PORT_3] = PORT_STATE__DISABLED; 1223 } 1224 else if (_tdm->_chip_data.soc_pkg.speed[MN_MGMT_PORT_1]==_tdm->_chip_data.soc_pkg.speed[MN_MGMT_PORT_0] && 1225 _tdm->_chip_data.soc_pkg.speed[MN_MGMT_PORT_1]<SPEED_10G){ 1226 _tdm->_chip_data.soc_pkg.state[MN_MGMT_PORT_0] = PORT_STATE__MANAGEMENT; 1227 _tdm->_chip_data.soc_pkg.state[MN_MGMT_PORT_1] = PORT_STATE__MANAGEMENT; 1228 _tdm->_chip_data.soc_pkg.state[MN_MGMT_PORT_2] = PORT_STATE__MANAGEMENT; 1229 _tdm->_chip_data.soc_pkg.state[MN_MGMT_PORT_3] = PORT_STATE__MANAGEMENT; 1230 } 1231 }*/ 1232 /* encap */ 1233 for (index=0; index<MN_NUM_PM_MOD; index++) { 1234 _tdm->_chip_data.soc_pkg.soc_vars.mn.pm_encap_type[index] = (_tdm->_chip_data.soc_pkg.state[index*4]==PORT_STATE__LINERATE_HG||_tdm->_chip_data.soc_pkg.state[index]==PORT_STATE__OVERSUB_HG)?(PM_ENCAP__HIGIG2):(PM_ENCAP__ETHRNT); 1235 } 1236 /* pmap */ 1237 _tdm->_chip_data.soc_pkg.pmap=(int **) TDM_ALLOC((_tdm->_chip_data.soc_pkg.pmap_num_modules)*sizeof(int *), "portmod_map_l1"); 1238 for (index=0; index<(_tdm->_chip_data.soc_pkg.pmap_num_modules); index++) { 1239 _tdm->_chip_data.soc_pkg.pmap[index]=(int *) TDM_ALLOC((_tdm->_chip_data.soc_pkg.pmap_num_lanes)*sizeof(int), "portmod_map_l2"); 1240 TDM_MSET(_tdm->_chip_data.soc_pkg.pmap[index],(_tdm->_chip_data.soc_pkg.num_ext_ports),_tdm->_chip_data.soc_pkg.pmap_num_lanes); 1241 } 1242 /* PGW x0 calendar group */ 1243 _tdm->_chip_data.cal_0.cal_main=(int *) TDM_ALLOC((_tdm->_chip_data.cal_0.cal_len)*sizeof(int), "TDM inst 0 main calendar"); 1244 TDM_MSET(_tdm->_chip_data.cal_0.cal_main,(_tdm->_chip_data.soc_pkg.num_ext_ports),_tdm->_chip_data.cal_0.cal_len); 1245 _tdm->_chip_data.cal_0.cal_grp=(int **) TDM_ALLOC((_tdm->_chip_data.cal_0.grp_num)*sizeof(int *), "TDM inst 0 groups"); 1246 for (index=0; index<(_tdm->_chip_data.cal_0.grp_num); index++) { 1247 _tdm->_chip_data.cal_0.cal_grp[index]=(int *) TDM_ALLOC((_tdm->_chip_data.cal_0.grp_len)*sizeof(int), "TDM inst 0 group calendars"); 1248 TDM_MSET(_tdm->_chip_data.cal_0.cal_grp[index],(_tdm->_chip_data.soc_pkg.num_ext_ports),_tdm->_chip_data.cal_0.grp_len); 1249 } 1250 /* PGW x1 calendar group */ 1251 _tdm->_chip_data.cal_1.cal_main=(int *) TDM_ALLOC((_tdm->_chip_data.cal_1.cal_len)*sizeof(int), "TDM inst 1 main calendar"); 1252 TDM_MSET(_tdm->_chip_data.cal_1.cal_main,(_tdm->_chip_data.soc_pkg.num_ext_ports),_tdm->_chip_data.cal_1.cal_len); 1253 _tdm->_chip_data.cal_1.cal_grp=(int **) TDM_ALLOC((_tdm->_chip_data.cal_1.grp_num)*sizeof(int *), "TDM inst 1 groups"); 1254 for (index=0; index<(_tdm->_chip_data.cal_1.grp_num); index++) { 1255 _tdm->_chip_data.cal_1.cal_grp[index]=(int *) TDM_ALLOC((_tdm->_chip_data.cal_1.grp_len)*sizeof(int), "TDM inst 1 group calendars"); 1256 TDM_MSET(_tdm->_chip_data.cal_1.cal_grp[index],(_tdm->_chip_data.soc_pkg.num_ext_ports),_tdm->_chip_data.cal_1.grp_len); 1257 } 1258 1259 /* MMU x pipe calendar group */ 1260 _tdm->_chip_data.cal_2.cal_main=(int *) TDM_ALLOC((_tdm->_chip_data.cal_2.cal_len)*sizeof(int), "TDM inst 2 main calendar"); 1261 TDM_MSET(_tdm->_chip_data.cal_2.cal_main,(_tdm->_chip_data.soc_pkg.num_ext_ports),_tdm->_chip_data.cal_2.cal_len); 1262 _tdm->_chip_data.cal_2.cal_grp=(int **) TDM_ALLOC((_tdm->_chip_data.cal_2.grp_num)*sizeof(int *), "TDM inst 2 groups"); 1263 for (index=0; index<(_tdm->_chip_data.cal_2.grp_num); index++) { 1264 _tdm->_chip_data.cal_2.cal_grp[index]=(int *) TDM_ALLOC((_tdm->_chip_data.cal_2.grp_len)*sizeof(int), "TDM inst 2 group calendars"); 1265 TDM_MSET(_tdm->_chip_data.cal_2.cal_grp[index],(_tdm->_chip_data.soc_pkg.num_ext_ports),_tdm->_chip_data.cal_2.grp_len); 1266 } 1267 /* Core: VMAP */ 1268 _tdm->_core_data.vmap=(unsigned short **) TDM_ALLOC((_tdm->_core_data.vmap_max_wid)*sizeof(unsigned short *), "vector_map_l1"); 1269 for (index=0; index<(_tdm->_core_data.vmap_max_wid); index++) { 1270 _tdm->_core_data.vmap[index]=(unsigned short *) TDM_ALLOC((_tdm->_core_data.vmap_max_len)*sizeof(unsigned short), "vector_map_l2"); 1271 } 1272 1273 _tdm->_chip_data.cal_4.cal_main= NULL; 1274 _tdm->_chip_data.cal_4.cal_grp = NULL; 1275 _tdm->_chip_data.cal_5.cal_main= NULL; 1276 _tdm->_chip_data.cal_5.cal_grp = NULL; 1277 _tdm->_chip_data.cal_6.cal_main= NULL; 1278 _tdm->_chip_data.cal_6.cal_grp = NULL; 1279 _tdm->_chip_data.cal_7.cal_main= NULL; 1280 _tdm->_chip_data.cal_7.cal_grp = NULL; 1281 1282 /* IARB static calendar group */ 1283 _tdm->_chip_data.cal_3.cal_main=(int *) TDM_ALLOC((_tdm->_chip_data.cal_3.cal_len)*sizeof(int), "TDM inst 3 main calendar"); 1284 TDM_MSET(_tdm->_chip_data.cal_3.cal_main,(_tdm->_chip_data.soc_pkg.num_ext_ports),_tdm->_chip_data.cal_3.cal_len); 1285 1286 return ( _tdm->_chip_exec[TDM_CHIP_EXEC__TRANSCRIPTION]( _tdm ) ); 1287 } 1288 1289 1290 /** 1291 @name: tdm_ap_post 1292 @param: 1293 */ 1294 int 1295 tdm_mn_post( tdm_mod_t *_tdm ) 1296 { 1297 return PASS; 1298 } 1299 1300 /** 1301 @name: tdm_ap_free 1302 @param: 1303 */ 1304 int 1305 tdm_mn_free( tdm_mod_t *_tdm ) 1306 { 1307 int index; 1308 /* Chip: pmap */ 1309 for (index=0; index<(_tdm->_chip_data.soc_pkg.pmap_num_modules); index++) { 1310 TDM_FREE(_tdm->_chip_data.soc_pkg.pmap[index]); 1311 } 1312 TDM_FREE(_tdm->_chip_data.soc_pkg.pmap); 1313 /* Chip: PGW x0 calendar group */ 1314 TDM_FREE(_tdm->_chip_data.cal_0.cal_main); 1315 for (index=0; index<(_tdm->_chip_data.cal_0.grp_num); index++) { 1316 TDM_FREE(_tdm->_chip_data.cal_0.cal_grp[index]); 1317 } 1318 TDM_FREE(_tdm->_chip_data.cal_0.cal_grp); 1319 /* Chip: PGW x1 calendar group */ 1320 TDM_FREE(_tdm->_chip_data.cal_1.cal_main); 1321 for (index=0; index<(_tdm->_chip_data.cal_1.grp_num); index++) { 1322 TDM_FREE(_tdm->_chip_data.cal_1.cal_grp[index]); 1323 } 1324 TDM_FREE(_tdm->_chip_data.cal_1.cal_grp); 1325 /* Chip: MMU x pipe calendar group */ 1326 TDM_FREE(_tdm->_chip_data.cal_2.cal_main); 1327 for (index=0; index<(_tdm->_chip_data.cal_2.grp_num); index++) { 1328 TDM_FREE(_tdm->_chip_data.cal_2.cal_grp[index]); 1329 } 1330 TDM_FREE(_tdm->_chip_data.cal_2.cal_grp); 1331 /* Chip: IARB static calendar group */ 1332 TDM_FREE(_tdm->_chip_data.cal_3.cal_main); 1333 /* Core: vmap */ 1334 for (index=0; index<(_tdm->_core_data.vmap_max_wid); index++) { 1335 TDM_FREE(_tdm->_core_data.vmap[index]); 1336 } 1337 TDM_FREE(_tdm->_core_data.vmap); 1338 1339 return PASS; 1340 } 1341 /*int mn_is_clport(int pnum) { 1342 if(pnum > 64) return false; 1343 if( (pnum >=1 && pnum <=20) || (pnum >=45 && pnum <=64) 1344 return 1; 1345 else 1346 return 0; 1347 } 1348 bool mn_chk_clport_lrspeed(enum port_state_e *state, enum port_speed_e *speed ) { 1349 1350 int loop; 1351 bool flag; 1352 1353 for(loop = 0; loop < MN_NUM_PHY_PORTS; loop++) { 1354 if(state) { 1355 if(state[loop]==PORT_STATE__LINERATE && mn_is_clport((unsigned int) loop)) { 1356 flag = TRUE; 1357 } 1358 } 1359 } 1360 return flag; 1361 } */