tdm_mn_iarb.c (72948B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * $All Rights Reserved.$ 7 * 8 * TDM chip specific IARB arbitration schedules 9 */ 10 #ifdef _TDM_STANDALONE 11 #include <tdm_top.h> 12 #else 13 #include <soc/tdm/core/tdm_top.h> 14 #endif 15 16 17 18 /**NAK, AP has only 1 Iarb TDM tbl. TD2+ had lr_tbl and ovs_tbl**/ 19 20 /** 21 @name: init_iarb_tdm_lr_table 22 @param: int, int, int, int, int*, int*, int[512], int[512] 23 24 IARB TDM Linerate Schedule: 25 Input 1 => Core bandwidth - 567/480/340/300/260. 26 Input 2 => 1 if there are 4x1G management ports, 0 otherwise. 27 Input 3 => 1 if there are 4x2.5G management ports, 0 otherwise. 28 Input 4 => 1 if there are 1x10G management port, 0 otherwise. 29 Output 5 => The X-pipe TDM linerate table wrap pointer value. 30 Output 6 => The Y-pipe TDM linerate table wrap pointer value. 31 Output 7 => The X-pipe TDM linerate schedule. 32 Output 8 => The Y-pipe TDM linerate schedule. 33 */ 34 #define IARB_MAIN_TDM__TDM_SLOT_MACSEC_PORT 5 35 void 36 tdm_mn_init_iarb_tdm_table (int core_bw, int *iarb_tdm_wrap_ptr_lr_x, int *iarb_tdm_tbl_lr_x, int sku_core_bw, int os_config, int is_macsec) 37 { 38 int i; 39 40 switch (core_bw) { 41 case 450: 42 switch(sku_core_bw) { 43 case 360: 44 for(i=0; i<87; i++){ 45 if(i%2 ==0) { 46 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 47 } else { 48 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 49 } 50 } 51 for(i=0; i<87; i++){ 52 switch(i){ 53 case 0: case 10: case 20: case 30: case 40: case 50: case 60: case 70: 54 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_MACSEC_PORT; 55 break; 56 case 7: case 85: 57 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 58 break; 59 case 9: case 83 : 60 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 61 break; 62 case 13 : case 33 : case 73 : 63 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 64 break; 65 } 66 } 67 *iarb_tdm_wrap_ptr_lr_x = 87; 68 break; 69 case 460: 70 for(i=0; i<107; i++){ 71 if(i%2 ==0) { 72 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 73 } else { 74 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 75 } 76 } 77 for(i=0; i<107; i++){ 78 switch(i){ 79 case 0: case 13: case 26: case 39: case 52: case 65: case 78: case 91: 80 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_MACSEC_PORT; 81 break; 82 case 46: case 102: 83 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 84 break; 85 case 38: case 95 : 86 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 87 break; 88 case 15 : case 62 : case 99 : 89 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 90 break; 91 } 92 } 93 *iarb_tdm_wrap_ptr_lr_x = 107; 94 break; 95 case 400: 96 for(i=0; i<95; i++){ 97 if(i%2 ==0) { 98 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 99 } else { 100 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 101 } 102 } 103 for(i=0; i<95; i++){ 104 switch(i){ 105 case 0: case 11: case 22: case 33: case 44: case 55: case 66: case 77: 106 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_MACSEC_PORT; 107 break; 108 case 3: case 69: 109 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 110 break; 111 case 12: case 52: 112 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 113 break; 114 case 31 : case 62 : case 92: 115 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 116 break; 117 } 118 } 119 *iarb_tdm_wrap_ptr_lr_x = 95; 120 break; 121 case 200: 122 for(i=0; i<54; i++){ 123 if(i%2 ==0) { 124 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 125 } else { 126 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 127 } 128 } 129 for(i=0; i<54; i++){ 130 switch(i){ 131 case 0: case 6: case 12: case 18: case 24: case 30: case 35: case 42: 132 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_MACSEC_PORT; 133 break; 134 case 3: case 53: 135 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 136 break; 137 case 9: case 49 : 138 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 139 break; 140 case 13 : case 47 : 141 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 142 break; 143 } 144 } 145 *iarb_tdm_wrap_ptr_lr_x = 54; 146 break; 147 case 235: case 275: 148 if(is_macsec == 1 && os_config == 1) { 149 for(i=0; i<58; i++){ 150 if(i%2 ==0) { 151 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 152 } else { 153 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 154 } 155 } 156 for(i=0; i<58; i++){ 157 switch(i){ 158 case 1: case 8: case 15: case 22: case 29: case 36: case 41: case 48: 159 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_MACSEC_PORT; 160 break; 161 case 17: 162 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 163 break; 164 case 32: 165 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 166 break; 167 case 7 : case 56: 168 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 169 break; 170 } 171 } 172 *iarb_tdm_wrap_ptr_lr_x = 58; 173 } else if(is_macsec ==0 && os_config == 1) { 174 for(i=0; i<58; i++){ 175 if(i%2 ==0) { 176 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 177 } else { 178 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 179 } 180 } 181 for(i=0; i<58; i++){ 182 switch(i){ 183 case 17: 184 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 185 break; 186 case 32: 187 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 188 break; 189 case 7 : case 56: 190 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 191 break; 192 } 193 } 194 *iarb_tdm_wrap_ptr_lr_x = 58; 195 } 196 } 197 /*printf("---------- IARB CALENDAR --------------------\n"); 198 for(i=0 ; i<321; i++){ 199 switch(iarb_tdm_tbl_lr_x[i]) { 200 case IARB_MAIN_TDM__TDM_SLOT_PGW_0: 201 printf("IARB Calendar Slot %d allocated to PGW_0\n",i); 202 break; 203 case IARB_MAIN_TDM__TDM_SLOT_PGW_1: 204 printf("IARB Calendar Slot %d allocated to PGW_1\n",i); 205 break; 206 case IARB_MAIN_TDM__TDM_SLOT_MACSEC_PORT: 207 printf("IARB Calendar Slot %d allocated to MACSEC\n",i); 208 break; 209 case IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK: 210 printf("IARB Calendar Slot %d allocated to LOOPBACK\n",i); 211 break; 212 case IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT: 213 printf("IARB Calendar Slot %d allocated to CMIC\n",i); 214 break; 215 case IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT: 216 printf("IARB Calendar Slot %d allocated to AUX/SBUS\n",i); 217 break; 218 } 219 } 220 printf("--------------------------------------------\n");*/ 221 break; 222 case 550: 223 switch(sku_core_bw) { 224 case 0: 225 for(i=0; i<193; i++){ 226 if(i%2 ==0) { 227 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 228 } else { 229 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 230 } 231 } 232 for(i=0; i<193; i++){ 233 switch(i) { 234 case 18: case 37: case 56: case 76: case 95: case 114: case 133: case 152: 235 case 171: case 192: case 22: case 44: case 61: case 104: case 123: 236 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_MACSEC_PORT; 237 break; 238 case 5: case 21: case 39: case 67: case 97: case 117: 239 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 240 break; 241 case 0: case 120: case 177 : 242 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 243 break; 244 case 160: case 185 : 245 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 246 break; 247 case 41: case 148: case 151 : 248 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 249 break; 250 } 251 } 252 *iarb_tdm_wrap_ptr_lr_x = 193; 253 break; 254 case 580: 255 for(i=0; i<131; i++){ 256 if(i%2 ==0) { 257 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 258 } else { 259 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 260 } 261 } 262 for(i=0; i<131; i++){ 263 switch(i){ 264 case 0: case 16: case 32: case 48: case 64: case 80: case 96: case 112: 265 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_MACSEC_PORT; 266 break; 267 case 51: case 103: 268 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 269 break; 270 case 61: case 121 : 271 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 272 break; 273 case 43 : case 87 : case 127 : 274 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 275 break; 276 } 277 } 278 *iarb_tdm_wrap_ptr_lr_x = 131; 279 break; 280 case 460: 281 for(i=0; i<107; i++){ 282 if(i%2 ==0) { 283 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 284 } else { 285 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 286 } 287 } 288 for(i=0; i<107; i++){ 289 switch(i){ 290 case 0: case 13: case 26: case 39: case 52: case 65: case 78: case 91: 291 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_MACSEC_PORT; 292 break; 293 case 46: case 102: 294 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 295 break; 296 case 38: case 95 : 297 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 298 break; 299 case 15 : case 62 : case 99 : 300 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 301 break; 302 } 303 } 304 *iarb_tdm_wrap_ptr_lr_x = 107; 305 break; 306 case 280: 307 for(i=0; i<70; i++){ 308 if(i%2 ==0) { 309 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 310 } else { 311 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 312 } 313 } 314 for(i=0; i<70; i++){ 315 switch(i){ 316 case 0: case 8: case 16: case 24: case 32: case 40: case 48: case 57: 317 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_MACSEC_PORT; 318 break; 319 case 3: case 67: 320 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 321 break; 322 case 9: case 59 : 323 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 324 break; 325 case 13 : case 69 : 326 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 327 break; 328 } 329 } 330 *iarb_tdm_wrap_ptr_lr_x = 70; 331 break; 332 case 400: 333 for(i=0; i<95; i++){ 334 if(i%2 ==0) { 335 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 336 } else { 337 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 338 } 339 } 340 for(i=0; i<95; i++){ 341 switch(i){ 342 case 0: case 11: case 22: case 33: case 44: case 55: case 66: case 77: 343 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_MACSEC_PORT; 344 break; 345 case 3: case 69: 346 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 347 break; 348 case 12: case 52: 349 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 350 break; 351 case 31 : case 62 : case 92: 352 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 353 break; 354 } 355 } 356 *iarb_tdm_wrap_ptr_lr_x = 95; 357 break; 358 case 300: case 340: 359 if(is_macsec == 1 && os_config == 1) { 360 for(i=0; i<72; i++){ 361 if(i%2 ==0) { 362 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 363 } else { 364 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 365 } 366 } 367 for(i=0; i<72; i++){ 368 switch(i){ 369 case 1: case 10: case 19: case 28: case 37: case 46: case 55: case 64: 370 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_MACSEC_PORT; 371 break; 372 case 3: 373 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 374 break; 375 case 42: 376 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 377 break; 378 case 25 : case 68 : 379 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 380 break; 381 } 382 } 383 *iarb_tdm_wrap_ptr_lr_x = 72; 384 } else if(is_macsec ==0 && os_config == 1) { 385 for(i=0; i<72; i++){ 386 if(i%2 ==0) { 387 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 388 } else { 389 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 390 } 391 } 392 for(i=0; i<72; i++){ 393 switch(i){ 394 case 3: 395 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 396 break; 397 case 42: 398 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 399 break; 400 case 25 : case 68 : 401 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 402 break; 403 } 404 } 405 *iarb_tdm_wrap_ptr_lr_x = 72; 406 } 407 break; 408 } 409 /* }*/ 410 411 /*printf("---------- IARB CALENDAR --------------------\n"); 412 for(i=0 ; i<193; i++){ 413 switch(iarb_tdm_tbl_lr_x[i]) { 414 case IARB_MAIN_TDM__TDM_SLOT_PGW_0: 415 printf("IARB Calendar Slot %d allocated to PGW_0\n",i); 416 break; 417 case IARB_MAIN_TDM__TDM_SLOT_PGW_1: 418 printf("IARB Calendar Slot %d allocated to PGW_1\n",i); 419 break; 420 case IARB_MAIN_TDM__TDM_SLOT_MACSEC_PORT: 421 printf("IARB Calendar Slot %d allocated to MACSEC\n",i); 422 break; 423 case IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK: 424 printf("IARB Calendar Slot %d allocated to LOOPBACK\n",i); 425 break; 426 case IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT: 427 printf("IARB Calendar Slot %d allocated to CMIC\n",i); 428 break; 429 case IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT: 430 printf("IARB Calendar Slot %d allocated to AUX/SBUS\n",i); 431 break; 432 } 433 } 434 printf("--------------------------------------------\n");*/ 435 break; /*break*/ 436 case 815: 437 for(i=0; i<321; i++){ 438 if(i%2 ==0) { 439 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 440 } else { 441 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 442 } 443 } 444 for(i=0; i<321; i++){ 445 switch(i){ 446 case 20: case 42: case 62: case 84: case 105: case 126: case 146: case 168: 447 case 189: case 210: case 230: case 252: case 273: case 294: case 315: 448 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_MACSEC_PORT; 449 break; 450 } 451 } 452 for(i=0; i<321; i++){ 453 if(i%53 ==0 && i !=0) { 454 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 455 } 456 } 457 for(i=0; i<321; i++){ 458 switch(i){ 459 case 0: case 108: case 214 : 460 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 461 break; 462 } 463 } 464 for(i=0; i<321; i++){ 465 switch(i){ 466 case 160: case 320 : 467 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 468 break; 469 } 470 } 471 for(i=0; i<321; i++){ 472 switch(i){ 473 case 40: case 148: case 255 : 474 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 475 break; 476 } 477 } 478 *iarb_tdm_wrap_ptr_lr_x = 321; 479 /*printf("---------- IARB CALENDAR --------------------\n"); 480 for(i=0 ; i<321; i++){ 481 switch(iarb_tdm_tbl_lr_x[i]) { 482 case IARB_MAIN_TDM__TDM_SLOT_PGW_0: 483 printf("IARB Calendar Slot %d allocated to PGW_0\n",i); 484 break; 485 case IARB_MAIN_TDM__TDM_SLOT_PGW_1: 486 printf("IARB Calendar Slot %d allocated to PGW_1\n",i); 487 break; 488 case IARB_MAIN_TDM__TDM_SLOT_MACSEC_PORT: 489 printf("IARB Calendar Slot %d allocated to MACSEC\n",i); 490 break; 491 case IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK: 492 printf("IARB Calendar Slot %d allocated to LOOPBACK\n",i); 493 break; 494 case IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT: 495 printf("IARB Calendar Slot %d allocated to CMIC\n",i); 496 break; 497 case IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT: 498 printf("IARB Calendar Slot %d allocated to AUX/SBUS\n",i); 499 break; 500 } 501 } 502 printf("--------------------------------------------\n");*/ 503 break; 504 case 818: /* CPRI_25G */ 505 for(i=0; i<334; i++){ 506 if(i%2 ==0) { 507 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 508 } else { 509 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 510 } 511 } 512 for(i=0; i<334; i++){ 513 if(i%55 ==0 && i !=0) { 514 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 515 } 516 } 517 for(i=0; i<334; i++){ 518 switch(i){ 519 case 0: case 107: case 214 : 520 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 521 break; 522 } 523 } 524 for(i=0; i<334; i++){ 525 switch(i){ 526 case 166: case 333 : 527 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 528 break; 529 } 530 } 531 for(i=0; i<334; i++){ 532 switch(i){ 533 case 41: case 148: case 255 : 534 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 535 break; 536 } 537 } 538 *iarb_tdm_wrap_ptr_lr_x = 334; 539 /*printf("---------- IARB CALENDAR --------------------\n"); 540 for(i=0 ; i<334; i++){ 541 switch(iarb_tdm_tbl_lr_x[i]) { 542 case IARB_MAIN_TDM__TDM_SLOT_PGW_0: 543 printf("IARB Calendar Slot %d allocated to PGW_0\n",i); 544 break; 545 case IARB_MAIN_TDM__TDM_SLOT_PGW_1: 546 printf("IARB Calendar Slot %d allocated to PGW_1\n",i); 547 break; 548 case IARB_MAIN_TDM__TDM_SLOT_MACSEC_PORT: 549 printf("IARB Calendar Slot %d allocated to MACSEC\n",i); 550 break; 551 case IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK: 552 printf("IARB Calendar Slot %d allocated to LOOPBACK\n",i); 553 break; 554 case IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT: 555 printf("IARB Calendar Slot %d allocated to CMIC\n",i); 556 break; 557 case IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT: 558 printf("IARB Calendar Slot %d allocated to AUX/SBUS\n",i); 559 break; 560 } 561 } 562 printf("--------------------------------------------\n");*/ 563 break; 564 case 819: 565 for(i=0; i<283; i++){ 566 if(i%2 ==0) { 567 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 568 } else { 569 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 570 } 571 } 572 for(i=0; i<283; i++){ 573 switch(i){ 574 case 17: case 35: case 53: case 69: case 87: case 104: case 122: case 140: case 158: case 192: case 210: case 228: case 246: case 264: case 279: 575 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_MACSEC_PORT; 576 } 577 } 578 for(i=0; i<283; i++){ 579 switch(i){ 580 case 56: case 112 : case 168: case 224: case 282: 581 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 582 break; 583 } 584 } 585 for(i=0; i<283; i++){ 586 switch(i){ 587 case 1: case 107: case 215 : 588 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 589 break; 590 } 591 } 592 for(i=0; i<283; i++){ 593 switch(i){ 594 case 45: case 91 : case 137: case 281: 595 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 596 break; 597 } 598 } 599 *iarb_tdm_wrap_ptr_lr_x = 283; 600 /*printf("---------- IARB CALENDAR --------------------\n"); 601 for(i=0 ; i<283; i++){ 602 switch(iarb_tdm_tbl_lr_x[i]) { 603 case IARB_MAIN_TDM__TDM_SLOT_PGW_0: 604 printf("IARB Calendar Slot %d allocated to PGW_0\n",i); 605 break; 606 case IARB_MAIN_TDM__TDM_SLOT_PGW_1: 607 printf("IARB Calendar Slot %d allocated to PGW_1\n",i); 608 break; 609 case IARB_MAIN_TDM__TDM_SLOT_MACSEC_PORT: 610 printf("IARB Calendar Slot %d allocated to MACSEC\n",i); 611 break; 612 case IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK: 613 printf("IARB Calendar Slot %d allocated to LOOPBACK\n",i); 614 break; 615 case IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT: 616 printf("IARB Calendar Slot %d allocated to CMIC\n",i); 617 break; 618 case IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT: 619 printf("IARB Calendar Slot %d allocated to AUX/SBUS\n",i); 620 break; 621 } 622 } 623 printf("--------------------------------------------\n");*/ 624 break; 625 case 820: 626 for(i=0; i<335; i++){ 627 if(i%2 ==0) { 628 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 629 } else { 630 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 631 } 632 } 633 for(i=0; i<335; i++){ 634 switch(i){ 635 case 17: case 35: case 53: case 69: case 87: case 104: case 122: case 140: case 158: case 192: case 210: case 228: case 246: case 264: case 279: case 294: case 310: 636 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_MACSEC_PORT; 637 } 638 } 639 for(i=0; i<335; i++){ 640 if(i%55 ==0 && i !=0) { 641 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 642 } 643 } 644 for(i=0; i<335; i++){ 645 switch(i){ 646 case 1: case 107: case 215 : 647 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 648 break; 649 } 650 } 651 for(i=0; i<335; i++){ 652 switch(i){ 653 case 45: case 91 : case 136: case 281: case 334: 654 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 655 break; 656 } 657 } 658 *iarb_tdm_wrap_ptr_lr_x = 335; 659 660 /*printf("---------- IARB CALENDAR --------------------\n"); 661 for(i=0 ; i<335; i++){ 662 switch(iarb_tdm_tbl_lr_x[i]) { 663 case IARB_MAIN_TDM__TDM_SLOT_PGW_0: 664 printf("IARB Calendar Slot %d allocated to PGW_0\n",i); 665 break; 666 case IARB_MAIN_TDM__TDM_SLOT_PGW_1: 667 printf("IARB Calendar Slot %d allocated to PGW_1\n",i); 668 break; 669 case IARB_MAIN_TDM__TDM_SLOT_MACSEC_PORT: 670 printf("IARB Calendar Slot %d allocated to MACSEC\n",i); 671 break; 672 case IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK: 673 printf("IARB Calendar Slot %d allocated to LOOPBACK\n",i); 674 break; 675 case IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT: 676 printf("IARB Calendar Slot %d allocated to CMIC\n",i); 677 break; 678 case IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT: 679 printf("IARB Calendar Slot %d allocated to AUX/SBUS\n",i); 680 break; 681 } 682 } 683 printf("--------------------------------------------\n");*/ 684 break; 685 case 861: case 862: 686 if(sku_core_bw == 0) { /* backward compatibility */ 687 for(i=0; i<226; i++){ 688 if(i%2 ==0) { 689 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 690 } else { 691 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 692 } 693 } 694 for(i=0; i<226; i++){ 695 switch(i){ 696 case 0: 697 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 698 break; 699 case 10: case 77 : case 91: 700 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 701 break; 702 case 106: 703 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 704 break; 705 } 706 } 707 *iarb_tdm_wrap_ptr_lr_x = 226; 708 } else { 709 if(is_macsec == 1 && os_config == 1) { 710 for(i=0; i<226; i++){ 711 if(i%2 ==0) { 712 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 713 } else { 714 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 715 } 716 } 717 for(i=0; i<226; i++){ 718 switch(i){ 719 case 0: case 222: 720 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 721 break; 722 case 3: case 17: case 31: case 45: case 59: case 73: case 87: case 101: 723 case 116: case 130: case 144: case 158: case 172: case 186: case 200: case 214: 724 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_MACSEC_PORT; 725 break; 726 case 10: case 77 : case 191: case 117: 727 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 728 break; 729 case 106: case 7: 730 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 731 break; 732 } 733 } 734 *iarb_tdm_wrap_ptr_lr_x = 226; 735 } else if(is_macsec == 0 && os_config == 1) { 736 for(i=0; i<226; i++){ 737 if(i%2 ==0) { 738 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 739 } else { 740 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 741 } 742 } 743 for(i=0; i<226; i++){ 744 switch(i){ 745 case 0: case 222: 746 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 747 break; 748 case 10: case 77 : case 191: case 117: 749 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 750 break; 751 case 106: case 7: 752 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 753 break; 754 } 755 } 756 *iarb_tdm_wrap_ptr_lr_x = 226; 757 } 758 } 759 /*printf("---------- IARB CALENDAR --------------------\n"); 760 for(i=0 ; i<227; i++){ 761 switch(iarb_tdm_tbl_lr_x[i]) { 762 case IARB_MAIN_TDM__TDM_SLOT_PGW_0: 763 printf("IARB Calendar Slot %d allocated to PGW_0\n",i); 764 break; 765 case IARB_MAIN_TDM__TDM_SLOT_PGW_1: 766 printf("IARB Calendar Slot %d allocated to PGW_1\n",i); 767 break; 768 case IARB_MAIN_TDM__TDM_SLOT_MACSEC_PORT: 769 printf("IARB Calendar Slot %d allocated to MACSEC\n",i); 770 break; 771 case IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK: 772 printf("IARB Calendar Slot %d allocated to LOOPBACK\n",i); 773 break; 774 case IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT: 775 printf("IARB Calendar Slot %d allocated to CMIC\n",i); 776 break; 777 case IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT: 778 printf("IARB Calendar Slot %d allocated to AUX/SBUS\n",i); 779 break; 780 } 781 } 782 printf("--------------------------------------------\n");*/ 783 break; 784 case 816: 785 for(i=0; i<297; i++){ 786 if(i%2 ==0) { 787 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 788 } else { 789 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 790 } 791 } 792 for(i=0; i<297; i++){ 793 switch(i) { 794 case 18: case 38: case 56: case 76: case 95: case 114: case 133: case 152: 795 case 171: case 190: case 209: case 228: case 247: case 266: case 285: 796 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_MACSEC_PORT; 797 break; 798 } 799 } 800 for(i=0; i<297; i++){ 801 if(i%49 ==0 && i !=0) { 802 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 803 } 804 } 805 for(i=0; i<297; i++){ 806 switch(i){ 807 case 0: case 120: case 214 : 808 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 809 break; 810 } 811 } 812 for(i=0; i<297; i++){ 813 switch(i){ 814 case 160: case 185 : 815 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 816 break; 817 } 818 } 819 for(i=0; i<297; i++){ 820 switch(i){ 821 case 41: case 148: case 255 : 822 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 823 break; 824 } 825 } 826 *iarb_tdm_wrap_ptr_lr_x = 297; 827 828 /*printf("---------- IARB CALENDAR --------------------\n"); 829 for(i=0 ; i<297; i++){ 830 switch(iarb_tdm_tbl_lr_x[i]) { 831 case IARB_MAIN_TDM__TDM_SLOT_PGW_0: 832 printf("IARB Calendar Slot %d allocated to PGW_0\n",i); 833 break; 834 case IARB_MAIN_TDM__TDM_SLOT_PGW_1: 835 printf("IARB Calendar Slot %d allocated to PGW_1\n",i); 836 break; 837 case IARB_MAIN_TDM__TDM_SLOT_MACSEC_PORT: 838 printf("IARB Calendar Slot %d allocated to MACSEC\n",i); 839 break; 840 case IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK: 841 printf("IARB Calendar Slot %d allocated to LOOPBACK\n",i); 842 break; 843 case IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT: 844 printf("IARB Calendar Slot %d allocated to CMIC\n",i); 845 break; 846 case IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT: 847 printf("IARB Calendar Slot %d allocated to AUX/SBUS\n",i); 848 break; 849 } 850 } 851 printf("--------------------------------------------\n");*/ 852 break; /*break*/ 853 case 817: 854 switch(sku_core_bw) { 855 case 0: 856 for(i=0; i<302; i++){ 857 if(i%2 ==0) { 858 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 859 } else { 860 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 861 } 862 } 863 for(i=0; i<302; i++){ 864 if(i%50 ==0 && i !=0) { 865 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 866 } 867 } 868 for(i=0; i<302; i++){ 869 if(i%99 ==0 && i !=0) { 870 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 871 } 872 } 873 for(i=0; i<302; i++){ 874 if(i%74 ==0 && i !=0) { 875 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 876 } 877 } 878 *iarb_tdm_wrap_ptr_lr_x = 302; 879 break; 880 case 800: 881 for(i=0; i<175; i++){ 882 if(i%2 ==0) { 883 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 884 } else { 885 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 886 } 887 } 888 for(i=0; i<175; i++){ 889 switch(i){ 890 case 0: case 22: case 44: case 66: case 88: case 100: case 122: case 144: 891 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_MACSEC_PORT; 892 break; 893 case 51: case 103: 894 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 895 break; 896 case 61: case 121 : 897 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 898 break; 899 case 43 : case 87 : case 127 : 900 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 901 break; 902 } 903 } 904 *iarb_tdm_wrap_ptr_lr_x = 175; 905 break; 906 case 475: case 515: 907 if(is_macsec == 1 && os_config == 1) { 908 for(i=0; i<106; i++){ 909 if(i%2 ==0) { 910 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 911 } else { 912 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 913 } 914 } 915 for(i=0; i<106; i++){ 916 switch(i){ 917 case 1: case 14: case 27: case 40: case 53: case 66: case 79: case 92: 918 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_MACSEC_PORT; 919 break; 920 case 18: 921 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 922 break; 923 case 30: 924 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 925 break; 926 case 43 : case 87 : 927 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 928 break; 929 } 930 } 931 *iarb_tdm_wrap_ptr_lr_x = 106; 932 } else if (is_macsec == 0 && os_config == 1) { 933 for(i=0; i<106; i++){ 934 if(i%2 ==0) { 935 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 936 } else { 937 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 938 } 939 } 940 for(i=0; i<106; i++){ 941 switch(i){ 942 case 18: 943 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 944 break; 945 case 30: 946 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 947 break; 948 case 43 : case 87 : 949 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 950 break; 951 } 952 } 953 *iarb_tdm_wrap_ptr_lr_x = 106; 954 } 955 break; 956 case 720: 957 for(i=0; i<159; i++){ 958 if(i%2 ==0) { 959 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 960 } else { 961 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 962 } 963 } 964 for(i=0; i<159; i++){ 965 switch(i){ 966 case 0: case 20: case 40: case 60: case 80: case 100: case 120: case 140: 967 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_MACSEC_PORT; 968 break; 969 case 51: case 103: 970 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 971 break; 972 case 83: case 157 : 973 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 974 break; 975 case 37 : case 47 : case 57 : 976 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 977 break; 978 } 979 } 980 *iarb_tdm_wrap_ptr_lr_x = 159; 981 break; 982 case 460: 983 for(i=0; i<106; i++){ 984 if(i%2 ==0) { 985 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 986 } else { 987 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 988 } 989 } 990 for(i=0; i<106; i++){ 991 switch(i){ 992 case 0: case 13: case 26: case 39: case 52: case 65: case 78: case 91: 993 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_MACSEC_PORT; 994 break; 995 case 46: case 102: 996 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 997 break; 998 case 38: case 95 : 999 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 1000 break; 1001 case 15 : case 61 : 1002 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 1003 break; 1004 } 1005 } 1006 *iarb_tdm_wrap_ptr_lr_x = 106; 1007 break; 1008 } 1009 /*printf("---------- IARB CALENDAR --------------------\n"); 1010 for(i=0 ; i<302; i++){ 1011 switch(iarb_tdm_tbl_lr_x[i]) { 1012 case IARB_MAIN_TDM__TDM_SLOT_PGW_0: 1013 printf("IARB Calendar Slot %d allocated to PGW_0\n",i); 1014 break; 1015 case IARB_MAIN_TDM__TDM_SLOT_PGW_1: 1016 printf("IARB Calendar Slot %d allocated to PGW_1\n",i); 1017 break; 1018 case IARB_MAIN_TDM__TDM_SLOT_MACSEC_PORT: 1019 printf("IARB Calendar Slot %d allocated to MACSEC\n",i); 1020 break; 1021 case IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK: 1022 printf("IARB Calendar Slot %d allocated to LOOPBACK\n",i); 1023 break; 1024 case IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT: 1025 printf("IARB Calendar Slot %d allocated to CMIC\n",i); 1026 break; 1027 case IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT: 1028 printf("IARB Calendar Slot %d allocated to AUX/SBUS\n",i); 1029 break; 1030 } 1031 } 1032 printf("--------------------------------------------\n");*/ 1033 1034 break; 1035 case 503 : 1036 for (i = 0; i < 4; i++) { 1037 if (i%2 == 0) { 1038 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1039 } else { 1040 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1041 } 1042 } 1043 iarb_tdm_tbl_lr_x[4] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1044 iarb_tdm_tbl_lr_x[5] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 1045 for (i = 6; i < 34; i++) { 1046 if (i%2 == 0) { 1047 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1048 } else { 1049 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1050 } 1051 } 1052 iarb_tdm_tbl_lr_x[34] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1053 iarb_tdm_tbl_lr_x[35] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 1054 for (i = 36; i < 46; i++) { 1055 if (i%2 == 0) { 1056 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1057 } else { 1058 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1059 } 1060 } 1061 iarb_tdm_tbl_lr_x[46] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1062 iarb_tdm_tbl_lr_x[47] = IARB_MAIN_TDM__TDM_SLOT_MACSEC_PORT; 1063 for (i = 48; i < 82; i++) { 1064 if (i%2 == 0) { 1065 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1066 } else { 1067 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1068 } 1069 } 1070 iarb_tdm_tbl_lr_x[82] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1071 iarb_tdm_tbl_lr_x[83] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 1072 for (i = 84; i < 88; i++) { 1073 if (i%2 == 0) { 1074 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1075 } else { 1076 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1077 } 1078 } 1079 iarb_tdm_tbl_lr_x[88] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1080 iarb_tdm_tbl_lr_x[89] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 1081 for (i = 90; i < 94; i++) { 1082 if (i%2 == 0) { 1083 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1084 } else { 1085 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1086 } 1087 } 1088 iarb_tdm_tbl_lr_x[94] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1089 iarb_tdm_tbl_lr_x[95] = IARB_MAIN_TDM__TDM_SLOT_MACSEC_PORT; 1090 for (i = 96; i < 106; i++) { 1091 if (i%2 == 0) { 1092 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1093 } else { 1094 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1095 } 1096 } 1097 iarb_tdm_tbl_lr_x[106] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 1098 for (i = 107; i < 143; i++) { 1099 if (i%2 == 0) { 1100 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1101 } else { 1102 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1103 } 1104 } 1105 iarb_tdm_tbl_lr_x[143] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 1106 for (i = 144; i < 148; i++) { 1107 if (i%2 == 0) { 1108 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1109 } else { 1110 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1111 } 1112 } 1113 iarb_tdm_tbl_lr_x[148] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1114 iarb_tdm_tbl_lr_x[149] = IARB_MAIN_TDM__TDM_SLOT_MACSEC_PORT; 1115 for (i = 150; i < 154; i++) { 1116 if (i%2 == 0) { 1117 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1118 } else { 1119 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1120 } 1121 } 1122 iarb_tdm_tbl_lr_x[154] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1123 iarb_tdm_tbl_lr_x[155] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 1124 for (i = 156; i < 196; i++) { 1125 if (i%2 == 0) { 1126 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1127 } else { 1128 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1129 } 1130 } 1131 iarb_tdm_tbl_lr_x[196] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1132 iarb_tdm_tbl_lr_x[197] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 1133 for (i = 198; i < 208; i++) { 1134 if (i%2 == 0) { 1135 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1136 } else { 1137 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1138 } 1139 } 1140 iarb_tdm_tbl_lr_x[208] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1141 iarb_tdm_tbl_lr_x[209] = IARB_MAIN_TDM__TDM_SLOT_MACSEC_PORT; 1142 iarb_tdm_tbl_lr_x[210] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1143 iarb_tdm_tbl_lr_x[211] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1144 iarb_tdm_tbl_lr_x[212] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1145 iarb_tdm_tbl_lr_x[213] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1146 iarb_tdm_tbl_lr_x[214] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 1147 break; 1148 case 252 : 1149 iarb_tdm_tbl_lr_x[0] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 1150 for (i = 1; i < 16; i++) { 1151 if (i%2 == 0) { 1152 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1153 } else { 1154 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1155 } 1156 } 1157 iarb_tdm_tbl_lr_x[16] = IARB_MAIN_TDM__TDM_SLOT_MACSEC_PORT; 1158 for (i = 17; i < 26; i++) { 1159 if (i%2 == 0) { 1160 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1161 } else { 1162 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1163 } 1164 } 1165 iarb_tdm_tbl_lr_x[26] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 1166 for (i = 27; i < 35; i++) { 1167 if (i%2 == 0) { 1168 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1169 } else { 1170 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1171 } 1172 } 1173 iarb_tdm_tbl_lr_x[35] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 1174 for (i = 36; i < 45; i++) { 1175 if (i%2 == 0) { 1176 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1177 } else { 1178 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1179 } 1180 } 1181 iarb_tdm_tbl_lr_x[45] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 1182 for (i = 46; i < 53; i++) { 1183 if (i%2 == 0) { 1184 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1185 } else { 1186 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1187 } 1188 } 1189 iarb_tdm_tbl_lr_x[53] = IARB_MAIN_TDM__TDM_SLOT_MACSEC_PORT; 1190 for (i = 54; i < 65; i++) { 1191 if (i%2 == 0) { 1192 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1193 } else { 1194 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1195 } 1196 } 1197 iarb_tdm_tbl_lr_x[65] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 1198 for (i = 66; i < 71; i++) { 1199 if (i%2 == 0) { 1200 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1201 } else { 1202 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1203 } 1204 } 1205 iarb_tdm_tbl_lr_x[71] = IARB_MAIN_TDM__TDM_SLOT_MACSEC_PORT; 1206 for (i = 72; i < 91; i++) { 1207 if (i%2 == 0) { 1208 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1209 } else { 1210 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1211 } 1212 } 1213 iarb_tdm_tbl_lr_x[91] = IARB_MAIN_TDM__TDM_SLOT_MACSEC_PORT; 1214 iarb_tdm_tbl_lr_x[92] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 1215 for (i = 93; i < 110; i++) { 1216 if (i%2 == 0) { 1217 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1218 } else { 1219 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1220 } 1221 } 1222 iarb_tdm_tbl_lr_x[110] = IARB_MAIN_TDM__TDM_SLOT_MACSEC_PORT; 1223 for (i = 111; i < 119; i++) { 1224 if (i%2 == 0) { 1225 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1226 } else { 1227 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1228 } 1229 } 1230 iarb_tdm_tbl_lr_x[119] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 1231 for (i = 120; i < 129; i++) { 1232 if (i%2 == 0) { 1233 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1234 } else { 1235 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1236 } 1237 } 1238 iarb_tdm_tbl_lr_x[129] = IARB_MAIN_TDM__TDM_SLOT_MACSEC_PORT; 1239 iarb_tdm_tbl_lr_x[130] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1240 iarb_tdm_tbl_lr_x[131] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 1241 for (i = 132; i < 139; i++) { 1242 if (i%2 == 0) { 1243 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1244 } else { 1245 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1246 } 1247 } 1248 iarb_tdm_tbl_lr_x[139] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 1249 for (i = 140; i < 147; i++) { 1250 if (i%2 == 0) { 1251 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1252 } else { 1253 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1254 } 1255 } 1256 iarb_tdm_tbl_lr_x[147] = IARB_MAIN_TDM__TDM_SLOT_MACSEC_PORT; 1257 for (i = 148; i < 165; i++) { 1258 if (i%2 == 0) { 1259 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1260 } else { 1261 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1262 } 1263 } 1264 iarb_tdm_tbl_lr_x[165] = IARB_MAIN_TDM__TDM_SLOT_MACSEC_PORT; 1265 for (i = 166; i < 183; i++) { 1266 if (i%2 == 0) { 1267 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1268 } else { 1269 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1270 } 1271 } 1272 iarb_tdm_tbl_lr_x[183] = IARB_MAIN_TDM__TDM_SLOT_MACSEC_PORT; 1273 iarb_tdm_tbl_lr_x[184] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1274 iarb_tdm_tbl_lr_x[185] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 1275 break; 1276 case 567 : 1277 *iarb_tdm_wrap_ptr_lr_x = 232; 1278 for (i = 0; i < 28; i++) { 1279 if (i%2 == 0) { 1280 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1281 } else { 1282 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1283 } 1284 } 1285 iarb_tdm_tbl_lr_x[28] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 1286 for (i = 29; i < 57; i++) { 1287 if ((i-29)%2 == 0) { 1288 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1289 } else { 1290 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1291 } 1292 } 1293 iarb_tdm_tbl_lr_x[57] = IARB_MAIN_TDM__TDM_SLOT_RDB_PORT; 1294 for (i = 58; i < 86; i++) { 1295 if ((i-58)%2 == 0) { 1296 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1297 } else { 1298 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1299 } 1300 } 1301 iarb_tdm_tbl_lr_x[86] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 1302 for (i = 87; i < 115; i++) { 1303 if ((i-87)%2 == 0) { 1304 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1305 } else { 1306 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1307 } 1308 } 1309 iarb_tdm_tbl_lr_x[115] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 1310 for (i = 116; i < 144; i++) { 1311 if ((i-116)%2 == 0) { 1312 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1313 } else { 1314 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1315 } 1316 } 1317 iarb_tdm_tbl_lr_x[144] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 1318 for (i = 145; i < 173; i++) { 1319 if ((i-145)%2 == 0) { 1320 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1321 } else { 1322 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1323 } 1324 } 1325 iarb_tdm_tbl_lr_x[173] = IARB_MAIN_TDM__TDM_SLOT_RDB_PORT; 1326 for (i = 174; i < 202; i++) { 1327 if ((i-174)%2 == 0) { 1328 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1329 } else { 1330 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1331 } 1332 } 1333 iarb_tdm_tbl_lr_x[202] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 1334 for (i = 203; i < 217; i++) { 1335 if ((i-203)%2 == 0) { 1336 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1337 } else { 1338 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1339 } 1340 } 1341 iarb_tdm_tbl_lr_x[217] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 1342 for (i = 218; i < 232; i++) { 1343 if ((i-218)%2 == 0) { 1344 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1345 } else { 1346 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1347 } 1348 } 1349 iarb_tdm_tbl_lr_x[232] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 1350 1351 /* Then check for management ports. */ 1352 /* NAK, Not suppoted in AP Iarb. management ports are scheduled with regular ports in PGW".*/ 1353 break; 1354 case 511 : 1355 *iarb_tdm_wrap_ptr_lr_x = 210; 1356 for (i = 0; i < 26; i++) { 1357 if (i%2 == 0) { 1358 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1359 } else { 1360 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1361 } 1362 } 1363 iarb_tdm_tbl_lr_x[26] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 1364 for (i = 27; i < 51; i++) { 1365 if ((i-27)%2 == 0) { 1366 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1367 } else { 1368 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1369 } 1370 } 1371 iarb_tdm_tbl_lr_x[51] = IARB_MAIN_TDM__TDM_SLOT_RDB_PORT; 1372 for (i = 52; i < 78; i++) { 1373 if ((i-52)%2 == 0) { 1374 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1375 } else { 1376 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1377 } 1378 } 1379 iarb_tdm_tbl_lr_x[78] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 1380 for (i = 79; i < 103; i++) { 1381 if ((i-79)%2 == 0) { 1382 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1383 } else { 1384 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1385 } 1386 } 1387 iarb_tdm_tbl_lr_x[103] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 1388 for (i = 104; i < 130; i++) { 1389 if ((i-104)%2 == 0) { 1390 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1391 } else { 1392 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1393 } 1394 } 1395 iarb_tdm_tbl_lr_x[130] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 1396 for (i = 131; i < 155; i++) { 1397 if ((i-131)%2 == 0) { 1398 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1399 } else { 1400 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1401 } 1402 } 1403 iarb_tdm_tbl_lr_x[155] = IARB_MAIN_TDM__TDM_SLOT_RDB_PORT; 1404 for (i = 156; i < 182; i++) { 1405 if ((i-156)%2 == 0) { 1406 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1407 } else { 1408 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1409 } 1410 } 1411 iarb_tdm_tbl_lr_x[182] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 1412 for (i = 183; i < 209; i++) { 1413 if ((i-183)%2 == 0) { 1414 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1415 } else { 1416 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1417 } 1418 } 1419 iarb_tdm_tbl_lr_x[209] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 1420 iarb_tdm_tbl_lr_x[210] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 1421 break; 1422 case 480 : 1423 *iarb_tdm_wrap_ptr_lr_x = 200; 1424 for (i = 0; i < 24; i++) { 1425 if (i%2 == 0) { 1426 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1427 } else { 1428 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1429 } 1430 } 1431 iarb_tdm_tbl_lr_x[24] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 1432 for (i = 25; i < 49; i++) { 1433 if ((i-25)%2 == 0) { 1434 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1435 } else { 1436 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1437 } 1438 } 1439 iarb_tdm_tbl_lr_x[49] = IARB_MAIN_TDM__TDM_SLOT_RDB_PORT; 1440 for (i = 50; i < 74; i++) { 1441 if ((i-50)%2 == 0) { 1442 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1443 } else { 1444 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1445 } 1446 } 1447 iarb_tdm_tbl_lr_x[74] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 1448 for (i = 75; i < 99; i++) { 1449 if ((i-75)%2 == 0) { 1450 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1451 } else { 1452 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1453 } 1454 } 1455 iarb_tdm_tbl_lr_x[99] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 1456 for (i = 100; i < 124; i++) { 1457 if ((i-100)%2 == 0) { 1458 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1459 } else { 1460 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1461 } 1462 } 1463 iarb_tdm_tbl_lr_x[124] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 1464 for (i = 125; i < 149; i++) { 1465 if ((i-125)%2 == 0) { 1466 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1467 } else { 1468 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1469 } 1470 } 1471 iarb_tdm_tbl_lr_x[149] = IARB_MAIN_TDM__TDM_SLOT_RDB_PORT; 1472 for (i = 150; i < 174; i++) { 1473 if ((i-150)%2 == 0) { 1474 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1475 } else { 1476 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1477 } 1478 } 1479 iarb_tdm_tbl_lr_x[174] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 1480 for (i = 175; i < 199; i++) { 1481 if ((i-175)%2 == 0) { 1482 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1483 } else { 1484 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1485 } 1486 } 1487 iarb_tdm_tbl_lr_x[199] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 1488 iarb_tdm_tbl_lr_x[200] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 1489 1490 /* Then check for management ports. */ 1491 /* NAK, Not suppoted in AP Iarb. management ports are scheduled with regular ports in PGW".*/ 1492 break; 1493 case 340 : 1494 *iarb_tdm_wrap_ptr_lr_x = 144; 1495 for (i = 0; i < 18; i++) { 1496 if (i%2 == 0) { 1497 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1498 } else { 1499 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1500 } 1501 } 1502 iarb_tdm_tbl_lr_x[18] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 1503 for (i = 19; i < 35; i++) { 1504 if ((i-19)%2 == 0) { 1505 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1506 } else { 1507 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1508 } 1509 } 1510 iarb_tdm_tbl_lr_x[35] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 1511 for (i = 36; i < 54; i++) { 1512 if ((i-36)%2 == 0) { 1513 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1514 } else { 1515 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1516 } 1517 } 1518 iarb_tdm_tbl_lr_x[54] = IARB_MAIN_TDM__TDM_SLOT_RDB_PORT; 1519 for (i = 55; i < 71; i++) { 1520 if ((i-55)%2 == 0) { 1521 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1522 } else { 1523 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1524 } 1525 } 1526 iarb_tdm_tbl_lr_x[71] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 1527 for (i = 72; i < 90; i++) { 1528 if ((i-72)%2 == 0) { 1529 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1530 } else { 1531 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1532 } 1533 } 1534 iarb_tdm_tbl_lr_x[90] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 1535 for (i = 91; i < 107; i++) { 1536 if ((i-91)%2 == 0) { 1537 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1538 } else { 1539 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1540 } 1541 } 1542 iarb_tdm_tbl_lr_x[107] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 1543 for (i = 108; i < 126; i++) { 1544 if ((i-108)%2 == 0) { 1545 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1546 } else { 1547 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1548 } 1549 } 1550 iarb_tdm_tbl_lr_x[126] = IARB_MAIN_TDM__TDM_SLOT_RDB_PORT; 1551 for (i = 127; i < 143; i++) { 1552 if ((i-127)%2 == 0) { 1553 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1554 } else { 1555 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1556 } 1557 } 1558 iarb_tdm_tbl_lr_x[143] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 1559 iarb_tdm_tbl_lr_x[144] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 1560 1561 /* Then check for management ports. */ 1562 /* NAK, Not suppoted in AP Iarb. management ports are scheduled with regular ports in PGW".*/ 1563 break; 1564 case 300 : 1565 *iarb_tdm_wrap_ptr_lr_x = 128; 1566 for (i = 0; i < 16; i++) { 1567 if (i%2 == 0) { 1568 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1569 } else { 1570 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1571 } 1572 } 1573 iarb_tdm_tbl_lr_x[16] = IARB_MAIN_TDM__TDM_SLOT_RDB_PORT; 1574 for (i = 17; i < 31; i++) { 1575 if ((i-17)%2 == 0) { 1576 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1577 } else { 1578 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1579 } 1580 } 1581 iarb_tdm_tbl_lr_x[31] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 1582 for (i = 32; i < 48; i++) { 1583 if ((i-32)%2 == 0) { 1584 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1585 } else { 1586 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1587 } 1588 } 1589 iarb_tdm_tbl_lr_x[48] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 1590 for (i = 49; i < 63; i++) { 1591 if ((i-49)%2 == 0) { 1592 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1593 } else { 1594 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1595 } 1596 } 1597 iarb_tdm_tbl_lr_x[63] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 1598 for (i = 64; i < 80; i++) { 1599 if ((i-64)%2 == 0) { 1600 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1601 } else { 1602 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1603 } 1604 } 1605 iarb_tdm_tbl_lr_x[80] = IARB_MAIN_TDM__TDM_SLOT_RDB_PORT; 1606 for (i = 81; i < 95; i++) { 1607 if ((i-81)%2 == 0) { 1608 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1609 } else { 1610 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1611 } 1612 } 1613 iarb_tdm_tbl_lr_x[95] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 1614 for (i = 96; i < 112; i++) { 1615 if ((i-96)%2 == 0) { 1616 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1617 } else { 1618 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1619 } 1620 } 1621 iarb_tdm_tbl_lr_x[112] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 1622 for (i = 113; i < 127; i++) { 1623 if ((i-113)%2 == 0) { 1624 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1625 } else { 1626 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1627 } 1628 } 1629 iarb_tdm_tbl_lr_x[127] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 1630 iarb_tdm_tbl_lr_x[128] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 1631 1632 /* Then check for management ports. */ 1633 /* NAK, Not suppoted in AP Iarb. management ports are scheduled with regular ports in PGW".*/ 1634 break; 1635 case 260 : 1636 *iarb_tdm_wrap_ptr_lr_x = 109; 1637 1638 iarb_tdm_tbl_lr_x[0] = IARB_MAIN_TDM__TDM_SLOT_RDB_PORT; 1639 for (i = 1; i < 10; i++) { 1640 if (i%2 == 0) { 1641 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1642 } else { 1643 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1644 } 1645 } 1646 iarb_tdm_tbl_lr_x[10] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 1647 for (i = 11; i < 20; i++) { 1648 if (i%2 == 0) { 1649 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1650 } else { 1651 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1652 } 1653 } 1654 iarb_tdm_tbl_lr_x[20] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 1655 for (i = 21; i < 31; i++) { 1656 if (i%2 == 0) { 1657 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1658 } else { 1659 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1660 } 1661 } 1662 iarb_tdm_tbl_lr_x[31] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 1663 for (i = 32; i < 41; i++) { 1664 if (i%2 == 0) { 1665 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1666 } else { 1667 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1668 } 1669 } 1670 iarb_tdm_tbl_lr_x[41] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 1671 for (i = 42; i < 53; i++) { 1672 if (i%2 == 0) { 1673 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1674 } else { 1675 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1676 } 1677 } 1678 iarb_tdm_tbl_lr_x[53] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 1679 for (i = 54; i < 65; i++) { 1680 if (i%2 == 0) { 1681 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1682 } else { 1683 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1684 } 1685 } 1686 iarb_tdm_tbl_lr_x[65] = IARB_MAIN_TDM__TDM_SLOT_RDB_PORT; 1687 for (i = 66; i < 75; i++) { 1688 if (i%2 == 0) { 1689 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1690 } else { 1691 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1692 } 1693 } 1694 iarb_tdm_tbl_lr_x[75] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 1695 for (i = 76; i < 85; i++) { 1696 if (i%2 == 0) { 1697 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1698 } else { 1699 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1700 } 1701 } 1702 iarb_tdm_tbl_lr_x[85] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 1703 for (i = 86; i < 95; i++) { 1704 if (i%2 == 0) { 1705 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1706 } else { 1707 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1708 } 1709 } 1710 iarb_tdm_tbl_lr_x[95] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 1711 for (i = 96; i < 110; i++) { 1712 if (i%2 == 0) { 1713 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1714 } else { 1715 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1716 } 1717 } 1718 1719 /* Then check for management ports. */ 1720 /* NAK, Not suppoted in AP Iarb. management ports are scheduled with regular ports in PGW".*/ 1721 break; 1722 1723 case 666: 1724 for(i=0; i<160; i++){ 1725 if(i%2 ==0) { 1726 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1727 } else { 1728 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1729 } 1730 } 1731 for(i=0; i<160; i++){ 1732 switch(i){ 1733 case 21: case 41: case 61: case 81: case 101: case 121: case 141: case 1: 1734 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_MACSEC_PORT; 1735 break; 1736 } 1737 } 1738 for(i=0; i<160; i++){ 1739 switch(i){ 1740 case 51: case 103: case 153 : 1741 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 1742 } 1743 } 1744 for(i=0; i<160; i++){ 1745 switch(i){ 1746 case 83: case 157 : 1747 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 1748 break; 1749 } 1750 } 1751 for(i=0; i<160; i++){ 1752 switch(i){ 1753 case 31: case 37 : case 47 : case 57 : 1754 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 1755 break; 1756 } 1757 } 1758 for(i=0; i<160; i++){ 1759 switch(i){ 1760 case 67 : case 77 : case 87 :case 97 : case 107 : case 127 : case 147 : 1761 case 7 : case 17 : case 27 :case 117 : case 63 : case 55 : case 133 : 1762 case 75 : case 85 : case 93 :case 13 : case 123 : 1763 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 1764 break; 1765 } 1766 } 1767 *iarb_tdm_wrap_ptr_lr_x = 160; 1768 /* printf("---------- IARB CALENDAR --------------------\n"); 1769 for(i=0 ; i<160 ; i++){ 1770 switch(iarb_tdm_tbl_lr_x[i]) { 1771 case IARB_MAIN_TDM__TDM_SLOT_PGW_0: 1772 printf("IARB Calendar Slot %d allocated to PGW_0\n",i); 1773 break; 1774 case IARB_MAIN_TDM__TDM_SLOT_PGW_1: 1775 printf("IARB Calendar Slot %d allocated to PGW_1\n",i); 1776 break; 1777 case IARB_MAIN_TDM__TDM_SLOT_MACSEC_PORT: 1778 printf("IARB Calendar Slot %d allocated to MACSEC\n",i); 1779 break; 1780 case IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK: 1781 printf("IARB Calendar Slot %d allocated to LOOPBACK\n",i); 1782 break; 1783 case IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT: 1784 printf("IARB Calendar Slot %d allocated to CMIC\n",i); 1785 break; 1786 case IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT: 1787 printf("IARB Calendar Slot %d allocated to AUX/SBUS\n",i); 1788 break; 1789 } 1790 } 1791 printf("--------------------------------------------\n");*/ 1792 break; 1793 1794 case 667: 1795 switch(sku_core_bw) { 1796 case 0: 1797 for(i=0; i<160; i++){ 1798 if(i%2 ==0) { 1799 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1800 } else { 1801 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1802 } 1803 } 1804 for(i=0; i<160; i++){ 1805 switch(i){ 1806 case 21: case 41: case 61: case 81: case 101: case 121: case 141: case 1: 1807 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_MACSEC_PORT; 1808 break; 1809 case 51: case 103: case 153 : 1810 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 1811 break; 1812 case 83: case 157 : 1813 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 1814 break; 1815 case 31: case 37 : case 47 : case 57 : 1816 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 1817 break; 1818 case 67 : case 77 : case 87 :case 97 : case 107 : case 127 : case 147 : 1819 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 1820 break; 1821 } 1822 } 1823 *iarb_tdm_wrap_ptr_lr_x = 160; 1824 break; 1825 case 720: 1826 for(i=0; i<159; i++){ 1827 if(i%2 ==0) { 1828 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1829 } else { 1830 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1831 } 1832 } 1833 for(i=0; i<159; i++){ 1834 switch(i){ 1835 case 0: case 20: case 40: case 60: case 80: case 100: case 120: case 140: 1836 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_MACSEC_PORT; 1837 break; 1838 case 51: case 103: 1839 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 1840 break; 1841 case 83: case 157 : 1842 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 1843 break; 1844 case 37 : case 47 : case 57 : 1845 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 1846 break; 1847 } 1848 } 1849 *iarb_tdm_wrap_ptr_lr_x = 159; 1850 break; 1851 break; 1852 case 580: 1853 for(i=0; i<131; i++){ 1854 if(i%2 ==0) { 1855 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1856 } else { 1857 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1858 } 1859 } 1860 for(i=0; i<131; i++){ 1861 switch(i){ 1862 case 0: case 16: case 32: case 48: case 64: case 80: case 96: case 112: 1863 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_MACSEC_PORT; 1864 break; 1865 case 51: case 103: 1866 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 1867 break; 1868 case 61: case 121 : 1869 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 1870 break; 1871 case 43 : case 87 : case 127 : 1872 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 1873 break; 1874 } 1875 } 1876 *iarb_tdm_wrap_ptr_lr_x = 131; 1877 break; 1878 case 400: 1879 for(i=0; i<94; i++){ 1880 if(i%2 ==0) { 1881 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1882 } else { 1883 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1884 } 1885 } 1886 for(i=0; i<94; i++){ 1887 switch(i){ 1888 case 0: case 9: case 20: case 30: case 40: case 50: case 60: case 70: 1889 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_MACSEC_PORT; 1890 break; 1891 case 7: case 77: 1892 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 1893 break; 1894 case 3: case 83 : 1895 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 1896 break; 1897 case 43 : case 85 : 1898 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 1899 break; 1900 } 1901 } 1902 *iarb_tdm_wrap_ptr_lr_x = 94; 1903 break; 1904 case 360: 1905 for(i=0; i<86; i++){ 1906 if(i%2 ==0) { 1907 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1908 } else { 1909 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1910 } 1911 } 1912 for(i=0; i<86; i++){ 1913 switch(i){ 1914 case 0: case 9: case 20: case 30: case 40: case 50: case 60: case 70: 1915 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_MACSEC_PORT; 1916 break; 1917 case 7: case 77: 1918 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 1919 break; 1920 case 3: case 83 : 1921 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 1922 break; 1923 case 43 : case 85 : 1924 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 1925 break; 1926 } 1927 } 1928 *iarb_tdm_wrap_ptr_lr_x = 86; 1929 break; 1930 case 380: case 420: 1931 if(is_macsec == 1 && os_config == 1) { 1932 for(i=0; i<88; i++){ 1933 if(i%2 ==0) { 1934 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1935 } else { 1936 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1937 } 1938 } 1939 for(i=0; i<88; i++){ 1940 switch(i){ 1941 case 0: case 11: case 22: case 33: case 44: case 55: case 66: case 77: 1942 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_MACSEC_PORT; 1943 break; 1944 case 7: 1945 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 1946 break; 1947 case 3: 1948 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 1949 break; 1950 case 40 : case 80 : 1951 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 1952 break; 1953 } 1954 } 1955 *iarb_tdm_wrap_ptr_lr_x = 88; 1956 } else if(is_macsec ==0 && os_config == 1) { 1957 for(i=0; i<88; i++){ 1958 if(i%2 ==0) { 1959 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 1960 } else { 1961 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 1962 } 1963 } 1964 for(i=0; i<88; i++){ 1965 switch(i){ 1966 case 7: 1967 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 1968 break; 1969 case 3: 1970 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 1971 break; 1972 case 40 : case 80 : 1973 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 1974 break; 1975 } 1976 } 1977 *iarb_tdm_wrap_ptr_lr_x = 88; 1978 } 1979 break; 1980 } 1981 /*printf("---------- IARB CALENDAR --------------------\n"); 1982 for(i=0 ; i<159; i++){ 1983 switch(iarb_tdm_tbl_lr_x[i]) { 1984 case IARB_MAIN_TDM__TDM_SLOT_PGW_0: 1985 printf("IARB Calendar Slot %d allocated to PGW_0\n",i); 1986 break; 1987 case IARB_MAIN_TDM__TDM_SLOT_PGW_1: 1988 printf("IARB Calendar Slot %d allocated to PGW_1\n",i); 1989 break; 1990 case IARB_MAIN_TDM__TDM_SLOT_MACSEC_PORT: 1991 printf("IARB Calendar Slot %d allocated to MACSEC\n",i); 1992 break; 1993 case IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK: 1994 printf("IARB Calendar Slot %d allocated to LOOPBACK\n",i); 1995 break; 1996 case IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT: 1997 printf("IARB Calendar Slot %d allocated to CMIC\n",i); 1998 break; 1999 case IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT: 2000 printf("IARB Calendar Slot %d allocated to AUX/SBUS\n",i); 2001 break; 2002 } 2003 } 2004 printf("--------------------------------------------\n");*/ 2005 break; 2006 2007 2008 } 2009 } 2010 2011 2012 /** 2013 @name: set_iarb_tdm_table 2014 @param: int, int, int, int, int, int, int*, int*, int[512], int[512] 2015 2016 IARB TDM Schedule Generator: 2017 Return => 1 if error, 0 otherwise. 2018 Input 1 => Core bandwidth - 960/720/640/480. 2019 Input 2 => 1 if X-pipe is oversub, 0 otherwise. 2020 Input 3 => 1 if Y-pipe is oversub, 0 otherwise. 2021 Input 4 => 1 if there are 4x1G management ports, 0 otherwise. 2022 Input 5 => 1 if there are 4x2.5G management ports, 0 otherwise. 2023 Input 6 => 1 if there are 1x10G management port, 0 otherwise. 2024 Output 7 => The X-pipe TDM table wrap pointer value. 2025 Output 8 => The Y-pipe TDM table wrap pointer value. 2026 Output 9 => The X-pipe TDM schedule. 2027 Output 10 => The Y-pipe TDM schedule. 2028 */ 2029 int tdm_mn_set_iarb_tdm (int core_bw, int is_x_ovs, int *iarb_tdm_wrap_ptr_x, int *iarb_tdm_tbl_x, 2030 int sku_core_bw, int is_macsec) 2031 { 2032 /* #if ( defined(_SET_TDM_DV) || defined(_SET_TDM_DEV) ) */ 2033 int i; 2034 int is_succ; 2035 int iarb_tdm_wrap_ptr_lr_x; 2036 int *iarb_tdm_tbl_lr_x; 2037 iarb_tdm_tbl_lr_x = (int *) TDM_ALLOC(sizeof(int) * 512, "iarb_tdm_tbl_lr_x"); 2038 /* #else 2039 int i; 2040 int is_succ; 2041 int iarb_tdm_wrap_ptr_ovs_x, iarb_tdm_wrap_ptr_ovs_y; 2042 int iarb_tdm_wrap_ptr_lr_x, iarb_tdm_wrap_ptr_lr_y; 2043 TDM_ALLOC(iarb_tdm_tbl_ovs_x, int, 512, "iarb_tdm_tbl_ovs_x"); 2044 TDM_ALLOC(iarb_tdm_tbl_ovs_y, int, 512, "iarb_tdm_tbl_ovs_y"); 2045 TDM_ALLOC(iarb_tdm_tbl_lr_x, int, 512, "iarb_tdm_tbl_lr_x"); 2046 TDM_ALLOC(iarb_tdm_tbl_lr_y, int, 512, "iarb_tdm_tbl_lr_y"); 2047 #endif */ 2048 2049 /* 2050 Initial IARB TDM table containers - to be copied into final container based 2051 on the TDM selected. 2052 */ 2053 2054 /*if (!(!mgm4x1 && !mgm4x2p5 && !mgm1x10) && !(mgm4x1 ^ mgm4x2p5 ^ mgm1x10)) { 2055 TDM_ERROR0("Multiple management port settings specified!\n"); 2056 } */ 2057 2058 tdm_mn_init_iarb_tdm_table(core_bw, &iarb_tdm_wrap_ptr_lr_x, iarb_tdm_tbl_lr_x, sku_core_bw, is_x_ovs, is_macsec); 2059 2060 /* The following TDMs have linerate X-pipe and linerate Y-pipe. */ 2061 *iarb_tdm_wrap_ptr_x = iarb_tdm_wrap_ptr_lr_x; 2062 memcpy(iarb_tdm_tbl_x, iarb_tdm_tbl_lr_x, sizeof(int) * 512); 2063 2064 2065 2066 TDM_PRINT1("iarb_tdm_wrap_ptr_x = %d\n",*iarb_tdm_wrap_ptr_x); 2067 for (i = 0; i <= *iarb_tdm_wrap_ptr_x; i++) { 2068 TDM_PRINT2("iarb_tdm_tbl_x[%d] = %d\n",i,iarb_tdm_tbl_x[i]); 2069 } 2070 2071 2072 /* Always succeeds by definition. */ 2073 is_succ = 1; 2074 TDM_FREE(iarb_tdm_tbl_lr_x); 2075 return is_succ; 2076 }