tdm_hx5_parse.c (18761B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * $All Rights Reserved.$ 7 * 8 * TDM chip based printing and parsing functions 9 */ 10 #ifdef _TDM_STANDALONE 11 #include <tdm_top.h> 12 #else 13 #include <soc/tdm/core/tdm_top.h> 14 #endif 15 16 17 /** 18 @name: tdm_hx5_print_pipe_config 19 @param: 20 21 Parses pipe config from class structs 22 */ 23 void 24 tdm_hx5_print_pipe_config(tdm_mod_t *_tdm) 25 { 26 int port_phy; 27 int param_port_start, param_port_end, param_phy_lo, param_phy_hi, 28 param_pipe_id; 29 enum port_speed_e *param_speeds; 30 enum port_state_e *param_states; 31 32 param_port_start= _tdm->_chip_data.soc_pkg.soc_vars.hx5.pipe_start; 33 param_port_end = _tdm->_chip_data.soc_pkg.soc_vars.hx5.pipe_end; 34 param_phy_lo = _tdm->_chip_data.soc_pkg.soc_vars.fp_port_lo; 35 param_phy_hi = _tdm->_chip_data.soc_pkg.soc_vars.fp_port_hi; 36 param_pipe_id = _tdm->_core_data.vars_pkg.pipe; 37 param_speeds = _tdm->_chip_data.soc_pkg.speed; 38 param_states = _tdm->_chip_data.soc_pkg.state; 39 40 if (param_port_start >= param_phy_lo && param_port_end <= param_phy_hi){ 41 TDM_BIG_BAR 42 TDM_PRINT3("TDM: Pipe Config: Pipe %d, Port [%d - %d] \n\n", 43 param_pipe_id, param_port_start, param_port_end); 44 TDM_PRINT5("%8s%8s%8s%8s%8s\n","port", "pm", "speed", "LR/OS", "EN/HG"); 45 for (port_phy=param_port_start; port_phy<=param_port_end; port_phy++) { 46 if (param_speeds[port_phy]>0) { 47 TDM_PRINT1("%8d", port_phy); 48 TDM_PRINT1("%8d", tdm_hx5_cmn_get_port_pm(port_phy, _tdm)); 49 TDM_PRINT1("%8d", (param_speeds[port_phy]/1000)); 50 if (param_states[port_phy-1] == PORT_STATE__LINERATE || 51 param_states[port_phy-1] == PORT_STATE__LINERATE_HG) { 52 TDM_PRINT1("%8s", "LR"); 53 } else { 54 TDM_PRINT1("%8s", "OS"); 55 } 56 if (param_states[port_phy-1] == PORT_STATE__LINERATE_HG || 57 param_states[port_phy-1] == PORT_STATE__OVERSUB_HG) { 58 TDM_PRINT1("%8s", "HG"); 59 } else { 60 TDM_PRINT1("%8s", "EN"); 61 } 62 TDM_PRINT0("\n"); 63 } 64 } 65 TDM_BIG_BAR 66 } 67 } 68 69 /** 70 @name: tdm_hx5_print_lr_cal 71 @param: 72 73 Print TDM calendar content of current pipe 74 */ 75 int 76 tdm_hx5_print_lr_cal(tdm_mod_t *_tdm, int cal_id) 77 { 78 int j, token; 79 int mgmt_2nd_en = 0; 80 int param_phy_lo, param_phy_hi, 81 param_mgmt_mode, 82 param_cal_id, param_cal_len; 83 int *param_cal_main=NULL; 84 85 param_phy_lo = _tdm->_chip_data.soc_pkg.soc_vars.fp_port_lo; 86 param_phy_hi = _tdm->_chip_data.soc_pkg.soc_vars.fp_port_hi; 87 param_mgmt_mode = _tdm->_chip_data.soc_pkg.soc_vars.hx5.mgmt_mode; 88 param_cal_id = cal_id; 89 param_cal_len = tdm_hx5_cmn_get_pipe_cal_len(param_cal_id, _tdm); 90 TDM_SEL_CAL(param_cal_id, param_cal_main); 91 92 COMPILER_REFERENCE(mgmt_2nd_en); 93 if (param_mgmt_mode == HX5_MGMT_MODE_2_PORT_EN || 94 param_mgmt_mode == HX5_MGMT_MODE_2_PORT_HG) { 95 mgmt_2nd_en = 1; 96 } 97 98 if (param_cal_main != NULL && param_cal_len > 0) { 99 for (j=0; j<param_cal_len; j++) { 100 token = param_cal_main[j]; 101 TDM_PRINT2("TDM: PIPE %d, element #%0d, ", param_cal_id, j); 102 if (((token != HX5_OVSB_TOKEN) && 103 !(token >= param_phy_lo && token <= param_phy_hi)) 104 ) { 105 TDM_PRINT0("contains ACCESSORY TOKEN - "); 106 switch (token) { 107 case HX5_CMIC_TOKEN: TDM_PRINT0("CMIC/CPU\n"); break; 108 case HX5_FAE_TOKEN: TDM_PRINT0("FAE-1\n"); break; 109 case HX5_LPB0_TOKEN: TDM_PRINT0("LOOPBACK-0\n"); break; 110 case HX5_IDL1_TOKEN: TDM_PRINT0("OPPORTUNISTIC-1\n"); break; 111 case HX5_NULL_TOKEN: TDM_PRINT0("NULL\n"); break; 112 case HX5_IDL2_TOKEN: TDM_PRINT0("IDLE\n"); break; 113 default: TDM_PRINT1("UNKNOWN,%d\n",token); break; 114 } 115 } else { 116 TDM_PRINT1("contains physical port #%0d\n", token); 117 } 118 } 119 } 120 121 return PASS; 122 } 123 124 /** 125 @name: tdm_hx5_print_pipe_cal 126 @param: 127 128 Print TDM calendar content of current pipe 129 */ 130 void 131 tdm_hx5_print_pipe_cal(tdm_mod_t *_tdm) 132 { 133 int i, j, n; 134 int param_pipe_id, param_cal_id, param_num_phy_pm, 135 param_grp_num=0, param_grp_len=0; 136 int **param_cal_grp=NULL; 137 tdm_calendar_t *param_cal=NULL; 138 139 param_pipe_id = _tdm->_core_data.vars_pkg.pipe; 140 param_cal_id = _tdm->_core_data.vars_pkg.cal_id; 141 param_num_phy_pm = _tdm->_chip_data.soc_pkg.pm_num_phy_modules; 142 143 switch(param_cal_id) { 144 case 0: param_cal = (&(_tdm->_chip_data.cal_0)); break; 145 case 1: param_cal = (&(_tdm->_chip_data.cal_1)); break; 146 /* case 2: param_cal = (&(_tdm->_chip_data.cal_2)); break; 147 case 3: param_cal = (&(_tdm->_chip_data.cal_3)); break; */ 148 default: 149 break;; 150 } 151 152 if (param_cal != NULL) { 153 param_grp_num = param_cal->grp_num; 154 param_grp_len = param_cal->grp_len; 155 param_cal_grp = param_cal->cal_grp; 156 if (param_grp_num > 0 && param_grp_len > 0 && param_cal_grp != NULL) { 157 /* OVSB groups: 1-dimension */ 158 for (i=0; i<param_grp_num; i++) { 159 for (j=0; j<param_grp_len; j++) { 160 TDM_PRINT4("TDM: PIPE %d, OVSB GROUP %2d, element #%03d, port #%0d\n", 161 param_cal_id, i, j, param_cal_grp[i][j]); 162 } 163 } 164 TDM_SML_BAR 165 /* OVSB groups: 2-dimension */ 166 TDM_PRINT1("\nTDM: PIPE %d, OVSB GROUPs 0:11\n", param_pipe_id); 167 for (i=0; i< param_grp_num; i++) { 168 n = param_grp_num/2; 169 if (n>0) { 170 if ((i%n)==0) { 171 TDM_PRINT2("\n%12s%2d\t", "HALF PIPE", (i/n)); 172 for (j=0; j<param_grp_len; j++) { 173 TDM_PRINT1("%3d\t", j+1); 174 } 175 TDM_PRINT0("\n"); 176 } 177 } 178 TDM_PRINT1("OVSB_GROUP[%2d]:\t", i); 179 for (j=0; j< param_grp_len; j++) { 180 TDM_PRINT1("%3d\t", param_cal_grp[i][j]); 181 } 182 TDM_PRINT0("\n"); 183 } 184 TDM_SML_BAR 185 /* Packet Scheduler Calendar */ 186 TDM_PRINT1("\nTDM: PIPE %d, PKT SCHEDULER HALF PIPE 0\n",param_pipe_id); 187 for (j=0; j<HX5_SHAPING_GRP_LEN; j++) { 188 if (j%16==0) { 189 TDM_PRINT2("\n %3d : %3d\t", j, j+15); 190 } 191 TDM_PRINT1("\t%d", param_cal_grp[HX5_SHAPING_GRP_IDX_0][j]); 192 } 193 TDM_PRINT0("\n\n"); 194 TDM_PRINT1("\nTDM: PIPE %d, PKT SCHEDULER HALF PIPE 1\n",param_pipe_id); 195 for (j=0; j<HX5_SHAPING_GRP_LEN; j++) { 196 if (j%16==0) { TDM_PRINT2("\n %3d : %3d\t", j, j+15);} 197 TDM_PRINT1("\t%d",param_cal_grp[HX5_SHAPING_GRP_IDX_1][j]); 198 } 199 TDM_PRINT0("\n"); 200 TDM_SML_BAR 201 } 202 /* PM_number to Port_Block_number mapping table */ 203 TDM_PRINT1("\nTDM: PIPE %d, PM_NUM to PBLK_ID MAP \nPM:PBLK_ID",param_pipe_id); 204 for (j=(16*param_cal_id); j<(16*(param_cal_id+1)) && j<param_num_phy_pm; j++) { 205 TDM_PRINT2("\t %2d:%2d",j, _tdm->_chip_data.soc_pkg.soc_vars.hx5.pm_num_to_pblk[j]); 206 } 207 TDM_PRINT0("\n"); 208 TDM_SML_BAR 209 } 210 } 211 212 /** 213 @name: tdm_hx5_parse_mgmt 214 @param: 215 216 Parse MGMT/CMIC slots in IDB TDM calendar 217 */ 218 /* 219 int 220 tdm_hx5_parse_mgmt(tdm_mod_t *_tdm, int cal_id) 221 { 222 int cnt = 0, result = PASS; 223 int ave_space, idx = 0, lo, hi, idx_lo, idx_hi, found = BOOL_TRUE; 224 int mgmt_2nd_en, mgmt_slot_num; 225 int param_mgmt_mode, param_token_ancl, param_cal_id, param_cal_len; 226 int *param_cal_main=NULL; 227 228 param_mgmt_mode = _tdm->_chip_data.soc_pkg.soc_vars.hx5.mgmt_mode; 229 param_token_ancl= _tdm->_chip_data.soc_pkg.soc_vars.ancl_token; 230 param_cal_id = cal_id; 231 param_cal_len = tdm_hx5_cmn_get_pipe_cal_len(param_cal_id, _tdm); 232 TDM_SEL_CAL(param_cal_id, param_cal_main); 233 234 if (param_mgmt_mode == HX5_MGMT_MODE_2_PORT_EN || 235 param_mgmt_mode == HX5_MGMT_MODE_2_PORT_HG) { 236 mgmt_2nd_en = 1; 237 mgmt_slot_num = 8; 238 } else { 239 mgmt_2nd_en = 0; 240 mgmt_slot_num = 4; 241 } 242 243 if (mgmt_slot_num > 0) { 244 ave_space = param_cal_len / mgmt_slot_num; 245 } 246 247 if (param_cal_main != NULL && param_cal_len > 0) { 248 while (idx < param_cal_len && 249 param_cal_main[idx] != param_token_ancl) { 250 idx++; 251 } 252 253 while (cnt < mgmt_slot_num && found == BOOL_TRUE) { 254 found = BOOL_FALSE; 255 if (param_cal_main[idx] == param_token_ancl) { 256 found = BOOL_TRUE; 257 } else { 258 lo = 0; 259 hi = 0; 260 idx_lo = idx; 261 idx_hi = idx; 262 do { 263 lo++; 264 hi++; 265 idx_lo = (param_cal_len + idx_lo - 1) % param_cal_len; 266 idx_hi = (idx_hi + 1) % param_cal_len; 267 } while ((lo + hi) < param_cal_len && 268 param_cal_main[idx_lo] != param_token_ancl && 269 param_cal_main[idx_hi] != param_token_ancl); 270 if (param_cal_main[idx_lo] == param_token_ancl) { 271 idx = idx_lo; 272 found = BOOL_TRUE; 273 } else if (param_cal_main[idx_hi] == param_token_ancl) { 274 idx = idx_hi; 275 found = BOOL_TRUE; 276 } 277 } 278 if (found == BOOL_TRUE) { 279 switch (param_cal_id) { 280 case 0: 281 case 4: 282 param_cal_main[idx] = HX5_CMIC_TOKEN; 283 break; 284 case 1: 285 case 5: 286 if (mgmt_2nd_en) { 287 param_cal_main[idx] = (cnt % 2 == 0) ? 288 HX5_MGM1_TOKEN : 289 HX5_MGM2_TOKEN; 290 } else { 291 param_cal_main[idx] = HX5_MGM1_TOKEN; 292 } 293 break; 294 default : 295 break; 296 } 297 TDM_PRINT2("Allocate %0d-th MGMT/CMIC slot at index #%03d\n", 298 cnt+1, idx); 299 cnt++; 300 idx = (idx + ave_space) % param_cal_len; 301 if (cnt >= mgmt_slot_num) { 302 break; 303 } 304 } 305 } 306 307 308 if (cnt < mgmt_slot_num) { 309 result = FAIL; 310 TDM_ERROR4("%s, cal_id %0d, req_slot %0d, alloc_slot %0d\n", 311 "Failed in MGMT/CMIC slot allocation", 312 param_cal_id, mgmt_slot_num, cnt); 313 } 314 } 315 316 return (result); 317 } 318 */ 319 /** 320 @name: tdm_hx5_parse_acc_idb 321 @param: 322 323 Parse ACCESSORY slots (LOOPBACK, OPP1, OPP2, NULL, IDLE) 324 */ 325 int 326 tdm_hx5_parse_acc_idb(tdm_mod_t *_tdm, int cal_id) 327 { 328 int j, cnt = 0; 329 int param_token_lpbk, param_token_ancl, param_cal_id, param_cal_len,param_token_fae; 330 int *param_cal_main=NULL; 331 332 param_token_ancl= _tdm->_chip_data.soc_pkg.soc_vars.ancl_token; 333 param_cal_id = cal_id; 334 param_cal_len = tdm_hx5_cmn_get_pipe_cal_len(param_cal_id, _tdm); 335 TDM_SEL_CAL(param_cal_id, param_cal_main); 336 337 switch (param_cal_id) { 338 case 0: 339 param_token_lpbk = HX5_LPB0_TOKEN; 340 param_token_fae = HX5_FAE_TOKEN; 341 break; 342 /* case 1: param_token_lpbk = HX5_LPB1_TOKEN; break; */ 343 default: return FAIL; break; 344 } 345 346 if (param_cal_main != NULL && param_cal_len > 0) { 347 for (j=0; j<param_cal_len; j++) { 348 if (param_cal_main[j] == param_token_ancl) { 349 cnt++; 350 switch (cnt) { 351 case 1: case 7: case 13: case 16 : case 18 : case 20 : case 22 : case 24 : 352 param_cal_main[j] = param_token_lpbk; 353 break; 354 case 2: case 8: 355 param_cal_main[j] = HX5_IDL1_TOKEN; 356 break; 357 case 3: case 9: 358 param_cal_main[j] = HX5_NULL_TOKEN; 359 break; 360 case 4: case 10: case 21 : case 15 : 361 param_cal_main[j] = HX5_IDL2_TOKEN; 362 break; 363 case 5: case 11: case 14: case 17: 364 param_cal_main[j] = param_token_fae; 365 break; 366 case 6 : case 12: case 19: case 23 : 367 param_cal_main[j] = HX5_CMIC_TOKEN; 368 break; 369 default: 370 break; 371 } 372 } 373 } 374 } 375 376 return PASS; 377 } 378 379 /** 380 @name: tdm_hx5_parse_acc_mmu 381 @param: 382 383 Parse ACCESSORY slots (LOOPBACK, OPP1, OPP2, NULL, IDLE) 384 */ 385 int 386 tdm_hx5_parse_acc_mmu(tdm_mod_t *_tdm, int cal_id) 387 { 388 int cnt = 0, j; 389 int param_token_lpbk, param_token_ancl, param_cal_id, param_cal_len; 390 int *param_cal_main=NULL; 391 392 param_token_ancl= _tdm->_chip_data.soc_pkg.soc_vars.ancl_token; 393 param_cal_id = cal_id; 394 param_cal_len = tdm_hx5_cmn_get_pipe_cal_len(param_cal_id, _tdm); 395 TDM_SEL_CAL(param_cal_id, param_cal_main); 396 397 switch (param_cal_id) { 398 case 4: param_token_lpbk = HX5_LPB0_TOKEN; break; 399 /* case 5: param_token_lpbk = HX5_LPB1_TOKEN; break; */ 400 default: return FAIL; break; 401 } 402 403 if (param_cal_main != NULL && param_cal_len > 0) { 404 for (j=0; j<param_cal_len; j++) { 405 if (param_cal_main[j] == param_token_ancl) { 406 cnt++; 407 switch (cnt) { 408 case 1: case 4: case 8: case 12: case 16 : case 18 : case 20 : case 24: 409 param_cal_main[j] = param_token_lpbk; 410 break; 411 case 3: case 9: case 21: case 15 : 412 param_cal_main[j] = HX5_CMIC_TOKEN; 413 break; 414 case 2: case 6: case 10 : case 14 : case 11 : case 22: 415 param_cal_main[j] = HX5_NULL_TOKEN; 416 break; 417 case 5: case 7 : case 13 : case 17 : case 23: case 19 : 418 param_cal_main[j] = HX5_IDL2_TOKEN; 419 break; 420 default: 421 break; 422 } 423 } 424 } 425 } 426 427 return PASS; 428 } 429 430 /** 431 @name: tdm_hx5_parse_ancl 432 @param: 433 434 Parse ANCILLARY slots (MGMT/CMIC, LOOPBACK, OPP1, OPP2, NULL, IDLE) 435 */ 436 int 437 tdm_hx5_parse_ancl(tdm_mod_t *_tdm, int cal_id) 438 { 439 int idb_en = 0, mmu_en = 0, result = PASS; 440 441 switch (cal_id) { 442 case 0: case 1: idb_en = 1; break; 443 case 4: case 5: mmu_en = 1; break; 444 default: 445 TDM_ERROR1("Invalid calendar ID - %0d\n", cal_id); 446 return FAIL; 447 break; 448 } 449 450 /* MGMT/CMIC */ 451 /* if (tdm_hx5_parse_mgmt(_tdm, cal_id) != PASS) { */ 452 /* TDM_ERROR1("Failed in MGMT/CMIC allocation, cal_id %0d\n", cal_id); */ 453 /* result = FAIL; */ 454 /* } */ 455 456 /* LOOPBACK, OPP1, OPP2, NULL, IDLE */ 457 if (idb_en == 1) { 458 if (tdm_hx5_parse_acc_idb(_tdm, cal_id) != PASS) { 459 TDM_ERROR1("Failed in ANCL allocation, cal_id %0d\n", cal_id); 460 result = FAIL; 461 } 462 } else if (mmu_en == 1) { 463 if (tdm_hx5_parse_acc_mmu(_tdm, cal_id) != PASS) { 464 TDM_ERROR1("Failed in ANCL allocation, cal_id %0d\n", cal_id); 465 result = FAIL; 466 } 467 } 468 469 return result; 470 } 471 472 /** 473 @name: tdm_hx5_parse_tdm_tbl 474 @param: 475 476 Post-process TDM calendar tokenized entries 477 */ 478 int 479 tdm_hx5_parse_tdm_tbl(tdm_mod_t *_tdm) 480 { 481 int j, result = PASS; 482 int param_cal_id, param_cal_id_idb, param_cal_id_mmu; 483 tdm_calendar_t *cal_idb=NULL; 484 tdm_calendar_t *cal_mmu=NULL; 485 486 param_cal_id = _tdm->_core_data.vars_pkg.cal_id; 487 488 switch(param_cal_id) { 489 case 0: 490 cal_idb = (&(_tdm->_chip_data.cal_0)); 491 cal_mmu = (&(_tdm->_chip_data.cal_4)); 492 param_cal_id_idb = 0; 493 param_cal_id_mmu = 4; 494 break; 495 case 1: 496 cal_idb = (&(_tdm->_chip_data.cal_1)); 497 cal_mmu = (&(_tdm->_chip_data.cal_5)); 498 param_cal_id_idb = 1; 499 param_cal_id_mmu = 5; 500 break; 501 case 2: 502 cal_idb = (&(_tdm->_chip_data.cal_2)); 503 cal_mmu = (&(_tdm->_chip_data.cal_6)); 504 param_cal_id_idb = 2; 505 param_cal_id_mmu = 6; 506 break; 507 case 3: 508 cal_idb = (&(_tdm->_chip_data.cal_3)); 509 cal_mmu = (&(_tdm->_chip_data.cal_7)); 510 param_cal_id_idb = 3; 511 param_cal_id_mmu = 7; 512 break; 513 default: 514 TDM_PRINT1("Invalid calendar ID - %0d\n", param_cal_id); 515 return (TDM_EXEC_CORE_SIZE+1); 516 } 517 518 /* construct MMU TDM calendar by copying from IDB TDM calendar */ 519 for (j=0; j<(cal_idb->cal_len) && j<(cal_mmu->cal_len); j++) { 520 cal_mmu->cal_main[j] = cal_idb->cal_main[j]; 521 } 522 523 TDM_PRINT0("done copy \n"); 524 /* parse ancillary slots in IDB TDM calendar */ 525 if (tdm_hx5_parse_ancl(_tdm, param_cal_id_idb) != PASS) { 526 result = FAIL; 527 } 528 TDM_PRINT1("done ancy %d \n",result); 529 tdm_hx5_print_lr_cal(_tdm, param_cal_id_idb); 530 531 /* parse ancillary slots in MMU TDM calendar */ 532 if (tdm_hx5_parse_ancl(_tdm, param_cal_id_mmu) != PASS) { 533 result = FAIL; 534 } 535 TDM_PRINT1("done ancy %d \n",result); 536 tdm_hx5_print_lr_cal(_tdm, param_cal_id_mmu); 537 TDM_PRINT0("done print lr \n"); 538 539 /* construct Oversub Half Pipes */ 540 if (tdm_hx5_vbs_scheduler_ovs(_tdm) != PASS) { 541 result = FAIL; 542 } 543 544 TDM_PRINT1("done half pipe %d \n",result); 545 /* print: OVSB_HALF_PIPE, Packet_Scheduler, PORT_BLOCK_Map */ 546 tdm_hx5_print_pipe_cal(_tdm); 547 548 if (result != PASS) { 549 return (TDM_EXEC_CORE_SIZE+1); 550 } 551 return ( _tdm->_chip_exec[TDM_CHIP_EXEC__POST]( _tdm ) ); 552 }