tdm_gh2_proc.c (35291B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * $All Rights Reserved.$ 7 * 8 * TDM chip operations 9 */ 10 #ifdef _TDM_STANDALONE 11 #include <tdm_top.h> 12 #include <tdm_gh2_vec.h> 13 #else 14 #include <soc/tdm/core/tdm_top.h> 15 #include <soc/tdm/greyhound2/tdm_gh2_vec.h> 16 #endif 17 18 19 /** 20 @name: tdm_gh2_proc_cal_tdm5 21 @param: 22 */ 23 int 24 tdm_gh2_proc_cal_tdm5( tdm_mod_t *_tdm ) 25 { 26 int j, v, w; 27 unsigned short lr1[TDM_AUX_SIZE], lr10[TDM_AUX_SIZE], lr20[TDM_AUX_SIZE], lr25[TDM_AUX_SIZE], lr40[TDM_AUX_SIZE], lr50[TDM_AUX_SIZE], lr100[TDM_AUX_SIZE]; 28 int param_freq, param_lr_limit, param_vmap_wid, param_vmap_len; 29 unsigned short **param_vmap; 30 31 param_freq = _tdm->_chip_data.soc_pkg.clk_freq; 32 param_lr_limit = _tdm->_chip_data.soc_pkg.lr_idx_limit; 33 param_vmap_wid = _tdm->_core_data.vmap_max_wid; 34 param_vmap_len = _tdm->_core_data.vmap_max_len; 35 param_vmap = _tdm->_core_data.vmap; 36 37 for (j=0; j<(TDM_AUX_SIZE); j++) { 38 lr1[j] = GH2_NUM_EXT_PORTS; 39 lr10[j] = GH2_NUM_EXT_PORTS; 40 lr20[j] = GH2_NUM_EXT_PORTS; 41 lr25[j] = GH2_NUM_EXT_PORTS; 42 lr40[j] = GH2_NUM_EXT_PORTS; 43 lr50[j] = GH2_NUM_EXT_PORTS; 44 lr100[j] = GH2_NUM_EXT_PORTS; 45 _tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.os1[j] = GH2_NUM_EXT_PORTS; 46 _tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.os10[j] = GH2_NUM_EXT_PORTS; 47 _tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.os20[j] = GH2_NUM_EXT_PORTS; 48 _tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.os25[j] = GH2_NUM_EXT_PORTS; 49 _tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.os40[j] = GH2_NUM_EXT_PORTS; 50 _tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.os50[j] = GH2_NUM_EXT_PORTS; 51 _tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.os100[j]= GH2_NUM_EXT_PORTS; 52 } 53 54 for (j=0; j<TDM_AUX_SIZE; j++) { 55 if ((_tdm->_core_data.vars_pkg.lr_buffer[j] != GH2_NUM_EXT_PORTS) && ( (_tdm->_chip_data.soc_pkg.state[_tdm->_core_data.vars_pkg.lr_buffer[j]-1] == PORT_STATE__LINERATE)||(_tdm->_chip_data.soc_pkg.state[_tdm->_core_data.vars_pkg.lr_buffer[j]-1] == PORT_STATE__LINERATE_HG) )) { 56 switch (_tdm->_chip_data.soc_pkg.speed[_tdm->_core_data.vars_pkg.lr_buffer[j]]) { 57 case SPEED_1G: 58 case SPEED_2p5G: 59 tdm_core_prealloc(lr1, _tdm->_core_data.vars_pkg.lr_buffer, &(_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y8), &(_tdm->_core_data.vars_pkg.lr_1), j); 60 break; 61 case SPEED_10G: 62 case SPEED_10G_DUAL: 63 case SPEED_10G_XAUI: 64 case SPEED_11G: 65 tdm_core_prealloc(lr10, _tdm->_core_data.vars_pkg.lr_buffer, &(_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y1), &(_tdm->_core_data.vars_pkg.lr_10), j); 66 break; 67 case SPEED_20G: 68 case SPEED_21G: 69 case SPEED_21G_DUAL: 70 tdm_core_prealloc(lr20, _tdm->_core_data.vars_pkg.lr_buffer, &(_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y2), &(_tdm->_core_data.vars_pkg.lr_20), j); 71 break; 72 case SPEED_25G: 73 case SPEED_27G: 74 tdm_core_prealloc(lr25, _tdm->_core_data.vars_pkg.lr_buffer, &(_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y6), &(_tdm->_core_data.vars_pkg.lr_25), j); 75 break; 76 case SPEED_40G: 77 case SPEED_42G: 78 case SPEED_42G_HG2: 79 tdm_core_prealloc(lr40, _tdm->_core_data.vars_pkg.lr_buffer, &(_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y3), &(_tdm->_core_data.vars_pkg.lr_40), j); 80 break; 81 case SPEED_50G: 82 case SPEED_53G: 83 tdm_core_prealloc(lr50, _tdm->_core_data.vars_pkg.lr_buffer, &(_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y5), &(_tdm->_core_data.vars_pkg.lr_50), j); 84 break; 85 case SPEED_100G: 86 case SPEED_106G: 87 tdm_core_prealloc(lr100, _tdm->_core_data.vars_pkg.lr_buffer, &(_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y4), &(_tdm->_core_data.vars_pkg.lr_100), j); 88 break; 89 default: 90 TDM_ERROR2("Speed %0d port %0d was skipped in linerate preallocation\n",_tdm->_chip_data.soc_pkg.speed[_tdm->_core_data.vars_pkg.lr_buffer[j]],_tdm->_core_data.vars_pkg.lr_buffer[j]); 91 } 92 } 93 else if (_tdm->_core_data.vars_pkg.lr_buffer[j] != GH2_NUM_EXT_PORTS && _tdm->_core_data.vars_pkg.lr_buffer[j] != GH2_OVSB_TOKEN) { 94 TDM_ERROR2("Failed to presort linerate port %0d with state mapping %0d\n", _tdm->_core_data.vars_pkg.lr_buffer[j], _tdm->_chip_data.soc_pkg.state[_tdm->_core_data.vars_pkg.lr_buffer[j]-1]); 95 } 96 if ((_tdm->_core_data.vars_pkg.os_buffer[j] != GH2_NUM_EXT_PORTS) && ( (_tdm->_chip_data.soc_pkg.state[_tdm->_core_data.vars_pkg.os_buffer[j]-1] == PORT_STATE__OVERSUB)||(_tdm->_chip_data.soc_pkg.state[_tdm->_core_data.vars_pkg.os_buffer[j]-1] == PORT_STATE__OVERSUB_HG) )) { 97 switch (_tdm->_chip_data.soc_pkg.speed[_tdm->_core_data.vars_pkg.os_buffer[j]]) { 98 case SPEED_1G: 99 case SPEED_2p5G: 100 tdm_core_prealloc(_tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.os1, _tdm->_core_data.vars_pkg.os_buffer, &(_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.z8), &(_tdm->_core_data.vars_pkg.os_1), j); 101 break; 102 case SPEED_10G: 103 case SPEED_10G_DUAL: 104 case SPEED_10G_XAUI: 105 case SPEED_11G: 106 tdm_core_prealloc(_tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.os10, _tdm->_core_data.vars_pkg.os_buffer, &(_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.z1), &(_tdm->_core_data.vars_pkg.os_10), j); 107 break; 108 case SPEED_20G: 109 case SPEED_21G: 110 case SPEED_21G_DUAL: 111 tdm_core_prealloc(_tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.os20, _tdm->_core_data.vars_pkg.os_buffer, &(_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.z2), &(_tdm->_core_data.vars_pkg.os_20), j); 112 break; 113 case SPEED_25G: 114 case SPEED_27G: 115 tdm_core_prealloc(_tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.os25, _tdm->_core_data.vars_pkg.os_buffer, &(_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.z6), &(_tdm->_core_data.vars_pkg.os_25), j); 116 break; 117 case SPEED_40G: 118 case SPEED_42G: 119 case SPEED_42G_HG2: 120 tdm_core_prealloc(_tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.os40, _tdm->_core_data.vars_pkg.os_buffer, &(_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.z3), &(_tdm->_core_data.vars_pkg.os_40), j); 121 break; 122 case SPEED_50G: 123 case SPEED_53G: 124 tdm_core_prealloc(_tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.os50, _tdm->_core_data.vars_pkg.os_buffer, &(_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.z5), &(_tdm->_core_data.vars_pkg.os_50), j); 125 break; 126 case SPEED_100G: 127 case SPEED_106G: 128 tdm_core_prealloc(_tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.os100, _tdm->_core_data.vars_pkg.os_buffer, &(_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.z4), &(_tdm->_core_data.vars_pkg.os_100), j); 129 break; 130 default: 131 TDM_ERROR2("Speed %0d port %0d was skipped in oversub preallocation\n",_tdm->_chip_data.soc_pkg.speed[_tdm->_core_data.vars_pkg.os_buffer[j]],_tdm->_core_data.vars_pkg.os_buffer[j]); 132 } 133 } 134 else if (_tdm->_core_data.vars_pkg.os_buffer[j] != GH2_NUM_EXT_PORTS) { 135 TDM_ERROR2("Failed to presort oversub port %0d with state mapping %0d\n", _tdm->_core_data.vars_pkg.os_buffer[j], _tdm->_chip_data.soc_pkg.state[_tdm->_core_data.vars_pkg.os_buffer[j]-1]); 136 } 137 } 138 _tdm->_core_data.vars_pkg.os_enable = (_tdm->_core_data.vars_pkg.os_1||_tdm->_core_data.vars_pkg.os_10||_tdm->_core_data.vars_pkg.os_20||_tdm->_core_data.vars_pkg.os_25||_tdm->_core_data.vars_pkg.os_40||_tdm->_core_data.vars_pkg.os_50||_tdm->_core_data.vars_pkg.os_100||_tdm->_core_data.vars_pkg.os_120); 139 _tdm->_core_data.vars_pkg.lr_enable = (_tdm->_core_data.vars_pkg.lr_1||_tdm->_core_data.vars_pkg.lr_10||_tdm->_core_data.vars_pkg.lr_20||_tdm->_core_data.vars_pkg.lr_25||_tdm->_core_data.vars_pkg.lr_40||_tdm->_core_data.vars_pkg.lr_50||_tdm->_core_data.vars_pkg.lr_100||_tdm->_core_data.vars_pkg.lr_120); 140 _tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.num_lr = (_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y8+_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y1+_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y2+_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y3+_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y4+_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y5+_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y6+_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y7); 141 _tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.num_os = (_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.z8+_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.z1+_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.z2+_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.z3+_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.z4+_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.z5+_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.z6+_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.z7); 142 _tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.num_100g = _tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y4; 143 _tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.num_40g = _tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y3; 144 /* 4x106HG+3x40G uses a unique TDM in Tomahawk */ 145 if (_tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.num_40g==3 && _tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.num_100g==4 && _tdm->_chip_data.soc_pkg.clk_freq==GH2_CLK_850MHZ) { 146 _tdm->_chip_data.soc_pkg.tvec_size=9; 147 _tdm->_chip_data.soc_pkg.lr_idx_limit=201; 148 _tdm->_core_data.vars_pkg.HG4X106G_3X40G=BOOL_TRUE; 149 } 150 else { 151 _tdm->_core_data.vars_pkg.HG4X106G_3X40G=BOOL_FALSE; 152 } 153 /* To guarantee oversub smoothness in nonscaling 100G+40G case, algorithm must sort with a 120G port vector (bw will be reclaimed) */ 154 if ( ( (_tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.num_100g==1) && (_tdm->_core_data.vars_pkg.lr_40) && (!_tdm->_core_data.vars_pkg.lr_120) && (_tdm->_core_data.vars_pkg.os_enable) ) ) { 155 _tdm->_core_data.vars_pkg.HG1X106G_xX40G_OVERSUB=BOOL_TRUE; 156 } 157 /* To sort 120G and 100G vectors together, load a special 100G vector */ 158 if ( (_tdm->_core_data.vars_pkg.lr_100 && _tdm->_core_data.vars_pkg.lr_120) ) { 159 _tdm->_core_data.vars_pkg.HGXx120G_Xx100G=BOOL_TRUE; 160 } 161 TDM_PRINT9("(1G - %0d) (10G - %0d) (20G - %0d) (25G - %0d) (40G - %0d) (50G - %0d) (100G - %0d) (120G - %0d) (Number of Line Rate Types - %0d)\n", _tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y8, _tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y1, _tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y2, _tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y6, _tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y3, _tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y5, _tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y4, _tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y7, (_tdm->_core_data.vars_pkg.lr_1+_tdm->_core_data.vars_pkg.lr_10+_tdm->_core_data.vars_pkg.lr_20+_tdm->_core_data.vars_pkg.lr_25+_tdm->_core_data.vars_pkg.lr_40+_tdm->_core_data.vars_pkg.lr_50+_tdm->_core_data.vars_pkg.lr_100+_tdm->_core_data.vars_pkg.lr_120)); 162 TDM_BIG_BAR 163 /* 100G */ 164 if(_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y4 > 0){ 165 if (_tdm->_core_data.vars_pkg.HG4X106G_3X40G) { 166 if (tdm_core_postalloc_vmap(param_vmap, param_freq, 107, &_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.yy, &(_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y4), param_lr_limit, lr100, TOKEN_100G, "100", GH2_NUM_EXT_PORTS, param_vmap_wid, param_vmap_len)!=PASS) { 167 TDM_ERROR0("Critical error in 100G time vector preallocation\n"); 168 return 0; 169 } 170 } 171 else if (_tdm->_core_data.vars_pkg.HG1X106G_xX40G_OVERSUB) { 172 if (tdm_core_postalloc_vmap(param_vmap, param_freq, 108, &_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.yy, &(_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y4), param_lr_limit, lr100, TOKEN_100G, "100", GH2_NUM_EXT_PORTS, param_vmap_wid, param_vmap_len)!=PASS) { 173 TDM_ERROR0("Critical error in 100G time vector preallocation\n"); 174 return 0; 175 } 176 } 177 else if (_tdm->_core_data.vars_pkg.HGXx120G_Xx100G) { 178 if (tdm_core_postalloc_vmap(param_vmap, param_freq, 109, &_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.yy, &(_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y4), param_lr_limit, lr100, TOKEN_100G, "100", GH2_NUM_EXT_PORTS, param_vmap_wid, param_vmap_len)!=PASS) { 179 TDM_ERROR0("Critical error in 100G time vector preallocation\n"); 180 return 0; 181 } 182 } 183 else{ 184 if (tdm_gh2_check_pipe_ethernet(lr100[_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y4],_tdm) && _tdm->_chip_data.soc_pkg.soc_vars.gh2.higig_mgmt==BOOL_FALSE && _tdm->_chip_data.soc_pkg.soc_vars.gh2.cal_hg_en==BOOL_FALSE) { 185 if (tdm_core_postalloc_vmap(param_vmap, param_freq, 100, &_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.yy, &(_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y4), param_lr_limit, lr100, TOKEN_100G, "100", GH2_NUM_EXT_PORTS, param_vmap_wid, param_vmap_len)!=PASS) { 186 TDM_ERROR0("Critical error in 100G time vector preallocation\n"); 187 return 0; 188 } 189 } 190 else { 191 if (tdm_core_postalloc_vmap(param_vmap, param_freq, 106, &_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.yy, &(_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y4), param_lr_limit, lr100, TOKEN_100G, "100", GH2_NUM_EXT_PORTS, param_vmap_wid, param_vmap_len)!=PASS) { 192 TDM_ERROR0("Critical error in 100G time vector preallocation\n"); 193 return 0; 194 } 195 } 196 } 197 } 198 /* 50G */ 199 if(_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y5 > 0){ 200 for (v=_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y5; v>0; v--) { 201 if (tdm_gh2_legacy_which_tsc(lr50[v+1],_tdm->_chip_data.soc_pkg.pmap)==tdm_gh2_legacy_which_tsc(lr50[v],_tdm->_chip_data.soc_pkg.pmap) || 202 tdm_gh2_legacy_which_tsc(lr50[v-1],_tdm->_chip_data.soc_pkg.pmap)==tdm_gh2_legacy_which_tsc(lr50[v],_tdm->_chip_data.soc_pkg.pmap)) { 203 _tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.prox_swap=lr50[v]; 204 for (w=v; w>0; w--) { 205 lr50[w]=lr50[w-1]; 206 } 207 lr50[1]=_tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.prox_swap; 208 } 209 } 210 for (v=_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y5; v>0; v--) { 211 _tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.tri_chk = tdm_gh2_legacy_which_tsc(lr50[v],_tdm->_chip_data.soc_pkg.pmap); 212 if ((_tdm->_chip_data.soc_pkg.pmap[_tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.tri_chk][0]!=_tdm->_chip_data.soc_pkg.pmap[_tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.tri_chk][2] && _tdm->_chip_data.soc_pkg.pmap[_tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.tri_chk][1]==_tdm->_chip_data.soc_pkg.pmap[_tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.tri_chk][3]) || 213 (_tdm->_chip_data.soc_pkg.pmap[_tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.tri_chk][0]==_tdm->_chip_data.soc_pkg.pmap[_tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.tri_chk][2] && _tdm->_chip_data.soc_pkg.pmap[_tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.tri_chk][1]!=_tdm->_chip_data.soc_pkg.pmap[_tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.tri_chk][3]) ){ 214 _tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.tri_en_50=BOOL_TRUE; 215 TDM_PRINT0("50G triport detected\n"); 216 break; 217 } 218 } 219 if (tdm_gh2_check_pipe_ethernet(lr50[_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y5],_tdm) && _tdm->_chip_data.soc_pkg.soc_vars.gh2.higig_mgmt==BOOL_FALSE && _tdm->_chip_data.soc_pkg.soc_vars.gh2.cal_hg_en==BOOL_FALSE) { 220 if (tdm_core_postalloc_vmap(param_vmap, param_freq, 50, &_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.yy, &(_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y5), param_lr_limit, lr50, TOKEN_50G, "50", GH2_NUM_EXT_PORTS, param_vmap_wid, param_vmap_len)!=PASS) { 221 TDM_ERROR0("Critical error in 50G time vector preallocation\n"); 222 return 0; 223 } 224 } 225 else { 226 if (tdm_core_postalloc_vmap(param_vmap, param_freq, 53, &_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.yy, &(_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y5), param_lr_limit, lr50, TOKEN_50G, "50", GH2_NUM_EXT_PORTS, param_vmap_wid, param_vmap_len)!=PASS) { 227 TDM_ERROR0("Critical error in 50G time vector preallocation\n"); 228 return 0; 229 } 230 } 231 } 232 /* 40G */ 233 if (_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y3 > 0) { 234 for (v=_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y3; v>0; v--) { 235 if (tdm_gh2_legacy_which_tsc(lr40[v+1],_tdm->_chip_data.soc_pkg.pmap)==tdm_gh2_legacy_which_tsc(lr40[v],_tdm->_chip_data.soc_pkg.pmap) || 236 tdm_gh2_legacy_which_tsc(lr40[v-1],_tdm->_chip_data.soc_pkg.pmap)==tdm_gh2_legacy_which_tsc(lr40[v],_tdm->_chip_data.soc_pkg.pmap)) { 237 _tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.prox_swap=lr40[v]; 238 for (w=v; w>0; w--) { 239 lr40[w]=lr40[w-1]; 240 } 241 lr40[1]=_tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.prox_swap; 242 } 243 } 244 for (v=_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y3; v>0; v--) { 245 _tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.tri_chk = tdm_gh2_legacy_which_tsc(lr40[v],_tdm->_chip_data.soc_pkg.pmap); 246 if ((_tdm->_chip_data.soc_pkg.pmap[_tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.tri_chk][0]!=_tdm->_chip_data.soc_pkg.pmap[_tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.tri_chk][2] && _tdm->_chip_data.soc_pkg.pmap[_tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.tri_chk][1]==_tdm->_chip_data.soc_pkg.pmap[_tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.tri_chk][3]) || 247 (_tdm->_chip_data.soc_pkg.pmap[_tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.tri_chk][0]==_tdm->_chip_data.soc_pkg.pmap[_tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.tri_chk][2] && _tdm->_chip_data.soc_pkg.pmap[_tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.tri_chk][1]!=_tdm->_chip_data.soc_pkg.pmap[_tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.tri_chk][3]) ){ 248 _tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.tri_en_40=BOOL_TRUE; 249 TDM_PRINT0("40G triport detected\n"); 250 break; 251 } 252 } 253 if (_tdm->_core_data.vars_pkg.HG4X106G_3X40G==BOOL_TRUE) { 254 if (_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y3==3) { 255 if (tdm_core_postalloc_vmap(param_vmap, param_freq, 43, &_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.yy, &(_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y3), param_lr_limit, lr40, TOKEN_40G, "40", GH2_NUM_EXT_PORTS, param_vmap_wid, param_vmap_len)!=PASS) { 256 TDM_ERROR0("Critical error in 40G time vector preallocation\n"); 257 return 0; 258 } 259 } 260 else if (_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y3==2) { 261 if (tdm_core_postalloc_vmap(param_vmap, param_freq, 44, &_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.yy, &(_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y3), param_lr_limit, lr40, TOKEN_40G, "40", GH2_NUM_EXT_PORTS, param_vmap_wid, param_vmap_len)!=PASS) { 262 TDM_ERROR0("Critical error in 40G time vector preallocation\n"); 263 return 0; 264 } 265 } 266 else if (_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y3==1) { 267 if (tdm_core_postalloc_vmap(param_vmap, param_freq, 45, &_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.yy, &(_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y3), param_lr_limit, lr40, TOKEN_40G, "40", GH2_NUM_EXT_PORTS, param_vmap_wid, param_vmap_len)!=PASS) { 268 TDM_ERROR0("Critical error in 40G time vector preallocation\n"); 269 return 0; 270 } 271 } 272 } 273 else { 274 if (tdm_gh2_check_pipe_ethernet(lr40[_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y3],_tdm) && _tdm->_chip_data.soc_pkg.soc_vars.gh2.higig_mgmt==BOOL_FALSE && _tdm->_chip_data.soc_pkg.soc_vars.gh2.cal_hg_en==BOOL_FALSE) { 275 if (tdm_core_postalloc_vmap(param_vmap, param_freq, 40, &_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.yy, &(_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y3), param_lr_limit, lr40, TOKEN_40G, "40", GH2_NUM_EXT_PORTS, param_vmap_wid, param_vmap_len)!=PASS) { 276 TDM_ERROR0("Critical error in 40G time vector preallocation\n"); 277 return 0; 278 } 279 } 280 else { 281 if (tdm_core_postalloc_vmap(param_vmap, param_freq, 42, &_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.yy, &(_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y3), param_lr_limit, lr40, TOKEN_40G, "40", GH2_NUM_EXT_PORTS, param_vmap_wid, param_vmap_len)!=PASS) { 282 TDM_ERROR0("Critical error in 40G time vector preallocation\n"); 283 return 0; 284 } 285 } 286 } 287 } 288 /* 25G */ 289 if (_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y6 > 0) { 290 if (tdm_gh2_check_pipe_ethernet(lr25[_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y6],_tdm) && _tdm->_chip_data.soc_pkg.soc_vars.gh2.higig_mgmt==BOOL_FALSE && _tdm->_chip_data.soc_pkg.soc_vars.gh2.cal_hg_en==BOOL_FALSE) { 291 if (tdm_core_postalloc_vmap(param_vmap, param_freq, 25, &_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.yy, &(_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y6), param_lr_limit, lr25, TOKEN_25G, "25", GH2_NUM_EXT_PORTS, param_vmap_wid, param_vmap_len)!=PASS) { 292 TDM_ERROR0("Critical error in 25G time vector preallocation\n"); 293 return 0; 294 } 295 } 296 else { 297 if (tdm_core_postalloc_vmap(param_vmap, param_freq, 27, &_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.yy, &(_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y6), param_lr_limit, lr25, TOKEN_25G, "25", GH2_NUM_EXT_PORTS, param_vmap_wid, param_vmap_len)!=PASS) { 298 TDM_ERROR0("Critical error in 25G time vector preallocation\n"); 299 return 0; 300 } 301 } 302 } 303 /* 20G */ 304 if (_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y2 > 0) { 305 for (v=_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y2; v>0; v--) { 306 _tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.tri_chk = tdm_gh2_legacy_which_tsc(lr20[v],_tdm->_chip_data.soc_pkg.pmap); 307 if ((_tdm->_chip_data.soc_pkg.pmap[_tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.tri_chk][0]!=_tdm->_chip_data.soc_pkg.pmap[_tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.tri_chk][2] && _tdm->_chip_data.soc_pkg.pmap[_tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.tri_chk][1]==_tdm->_chip_data.soc_pkg.pmap[_tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.tri_chk][3]) || 308 (_tdm->_chip_data.soc_pkg.pmap[_tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.tri_chk][0]==_tdm->_chip_data.soc_pkg.pmap[_tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.tri_chk][2] && _tdm->_chip_data.soc_pkg.pmap[_tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.tri_chk][1]!=_tdm->_chip_data.soc_pkg.pmap[_tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.tri_chk][3]) ){ 309 _tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.tri_en_20=BOOL_TRUE; 310 TDM_PRINT0("20G triport detected\n"); 311 break; 312 } 313 } 314 if (tdm_gh2_check_pipe_ethernet(lr20[_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y2],_tdm) && _tdm->_chip_data.soc_pkg.soc_vars.gh2.higig_mgmt==BOOL_FALSE && _tdm->_chip_data.soc_pkg.soc_vars.gh2.cal_hg_en==BOOL_FALSE) { 315 if (tdm_core_postalloc_vmap(param_vmap, param_freq, 20, &_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.yy, &(_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y2), param_lr_limit, lr20, TOKEN_20G, "20", GH2_NUM_EXT_PORTS, param_vmap_wid, param_vmap_len)!=PASS) { 316 TDM_ERROR0("Critical error in 20G time vector preallocation\n"); 317 return 0; 318 } 319 } 320 else { 321 if (tdm_core_postalloc_vmap(param_vmap, param_freq, 21, &_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.yy, &(_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y2), param_lr_limit, lr20, TOKEN_20G, "20", GH2_NUM_EXT_PORTS, param_vmap_wid, param_vmap_len)!=PASS) { 322 TDM_ERROR0("Critical error in 20G time vector preallocation\n"); 323 return 0; 324 } 325 } 326 } 327 /* 10G */ 328 if (_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y1 > 0) { 329 if (tdm_gh2_check_pipe_ethernet(lr10[_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y1],_tdm) && _tdm->_chip_data.soc_pkg.soc_vars.gh2.higig_mgmt==BOOL_FALSE && _tdm->_chip_data.soc_pkg.soc_vars.gh2.cal_hg_en==BOOL_FALSE) { 330 if (tdm_core_postalloc_vmap(param_vmap, param_freq, 10, &_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.yy, &(_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y1), param_lr_limit, lr10, TOKEN_10G, "10", GH2_NUM_EXT_PORTS, param_vmap_wid, param_vmap_len)!=PASS) { 331 TDM_ERROR0("Critical error in 10G time vector preallocation\n"); 332 return 0; 333 } 334 } 335 else { 336 if (tdm_core_postalloc_vmap(param_vmap, param_freq, 11, &_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.yy, &(_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y1), param_lr_limit, lr10, TOKEN_10G, "10", GH2_NUM_EXT_PORTS, param_vmap_wid, param_vmap_len)!=PASS) { 337 TDM_ERROR0("Critical error in 10G time vector preallocation\n"); 338 return 0; 339 } 340 } 341 } 342 /* 1G */ 343 if (_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y8 > 0) { 344 if (tdm_core_postalloc_vmap(param_vmap, param_freq, 1, &_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.yy, &(_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y8), param_lr_limit, lr1, TOKEN_1G, "1", GH2_NUM_EXT_PORTS, param_vmap_wid, param_vmap_len)!=PASS) { 345 TDM_ERROR0("Critical error in 1G time vector preallocation\n"); 346 return 0; 347 } 348 } 349 350 return ( _tdm->_core_exec[TDM_CORE_EXEC__SCHEDULER]( _tdm ) ); 351 } 352 353 354 /** 355 @name: tdm_gh2_proc_cal_ancl 356 @param: 357 358 Allocate ancillary slots with matched speed rates accordingly 359 */ 360 int 361 tdm_gh2_proc_cal_ancl(tdm_mod_t *_tdm) 362 { 363 int i, j, k, k_prev, k_idx, idx_up, idx_dn, result=PASS; 364 int param_lr_limit, param_ancl_num, param_cal_len, 365 param_token_empty, param_token_ancl, 366 param_lr_en; 367 int *param_cal_main; 368 369 param_lr_limit = _tdm->_chip_data.soc_pkg.lr_idx_limit; 370 param_ancl_num = _tdm->_chip_data.soc_pkg.tvec_size; 371 param_cal_len = param_lr_limit + param_ancl_num; 372 param_token_empty = _tdm->_chip_data.soc_pkg.num_ext_ports; 373 param_token_ancl = _tdm->_chip_data.soc_pkg.soc_vars.ancl_token; 374 param_lr_en = _tdm->_core_data.vars_pkg.lr_enable; 375 376 /* allocate ANCL slots */ 377 TDM_SEL_CAL(_tdm->_core_data.vars_pkg.cal_id,param_cal_main); 378 if (param_ancl_num>0){ 379 TDM_PRINT1("TDM: Allocate %d ANCL slots\n\n", param_ancl_num); 380 if (param_lr_en==BOOL_TRUE){ 381 k = 0; 382 for (j=0; j<param_ancl_num; j++){ 383 idx_up = 0; 384 idx_dn = 0; 385 k_idx = 0; 386 k_prev = k; 387 if (j==(param_ancl_num-1)){ 388 k = param_cal_len - 1; 389 } 390 else { 391 k = k_prev + ((param_cal_len-k_prev)/(param_ancl_num-j)) -1; 392 } 393 for (i=k; i>0 && i<param_cal_len; i--){ 394 if (param_cal_main[i]==param_token_empty){ 395 idx_up = i; 396 break; 397 } 398 } 399 for (i=k; i<param_cal_len; i++){ 400 if (param_cal_main[i]==param_token_empty){ 401 idx_dn = i; 402 break; 403 } 404 } 405 if (idx_up>0 || idx_dn>0){ 406 if (idx_up>0 && idx_dn>0){ 407 k_idx = ((k-idx_up)<(idx_dn-k))?(idx_up):(idx_dn); 408 } 409 else if (idx_up>0){ 410 k_idx = idx_up; 411 } 412 else if (idx_dn>0){ 413 k_idx = idx_dn; 414 } 415 } 416 if (k_idx==0){ 417 for (i=(param_cal_len-1); i>0; i--){ 418 if (param_cal_main[i]==param_token_empty){ 419 k_idx = i; 420 break; 421 } 422 } 423 } 424 if (k_idx>0 && k_idx<param_cal_len){ 425 param_cal_main[k_idx] = param_token_ancl; 426 TDM_PRINT2("TDM: Allocate %d-th ANCL slot at index #%03d\n", 427 j+1, k_idx); 428 } 429 else { 430 TDM_WARN1("TDM: Failed in %d-th ANCL slot allocation\n",j); 431 result = FAIL; 432 } 433 } 434 } 435 else { 436 k_prev = 0; 437 for (j=0; j<param_ancl_num; j++){ 438 k_idx = k_prev + ((param_cal_len-k_prev)/(param_ancl_num-j)) - 1; 439 param_cal_main[k_idx] = param_token_ancl; 440 k_prev= k_idx+1; 441 TDM_PRINT1("TDM: Allocate ANCL slot at index #%03d\n", 442 k_idx); 443 } 444 } 445 TDM_SML_BAR 446 } 447 448 return result; 449 } 450 451 452 /** 453 @name: tdm_gh2_proc_cal_acc 454 @param: 455 456 Allocate accessory slots with matched speed rates accordingly 457 */ 458 int 459 tdm_gh2_proc_cal_acc(tdm_mod_t *_tdm) 460 { 461 int i, j, v, k, k_prev, k_idx, clump_size, clump_size_max, result=PASS; 462 int param_lr_limit, param_ancl_num, param_cal_len, 463 param_token_empty, param_token_ancl, 464 param_lr_en; 465 int *param_cal_main; 466 467 param_lr_limit = _tdm->_chip_data.soc_pkg.lr_idx_limit; 468 param_ancl_num = _tdm->_chip_data.soc_pkg.tvec_size; 469 param_cal_len = param_lr_limit + param_ancl_num; 470 param_token_empty = _tdm->_chip_data.soc_pkg.num_ext_ports; 471 param_token_ancl = _tdm->_chip_data.soc_pkg.soc_vars.ancl_token; 472 param_lr_en = _tdm->_core_data.vars_pkg.lr_enable; 473 474 /* allocate ANCL slots */ 475 TDM_SEL_CAL(_tdm->_core_data.vars_pkg.cal_id,param_cal_main); 476 if (param_ancl_num>0 && param_ancl_num<=param_cal_len){ 477 TDM_PRINT1("TDM: Allocate %d ANCL slots\n\n", param_ancl_num); 478 if (param_lr_en==BOOL_TRUE){ 479 k = 0; 480 for (j=0; j<param_ancl_num; j++){ 481 k_prev = k; 482 if (j==(param_ancl_num-1)){ 483 k = param_cal_len - 1; 484 } 485 else { 486 k = k_prev + ((param_cal_len-k_prev)/(param_ancl_num-j)) -1; 487 } 488 k_idx= 0; 489 clump_size = 0; 490 clump_size_max = 0; 491 for (i=k; i>=k_prev && i<param_cal_len; i--){ 492 if (param_cal_main[i]==param_token_empty){ 493 clump_size++; 494 if (i==k){ 495 for (v=k+1; v<param_cal_len; v++){ 496 if (param_cal_main[v]==param_token_empty){ 497 clump_size++; 498 } 499 else{ 500 break; 501 } 502 } 503 } 504 } 505 else{ 506 if (clump_size>clump_size_max){ 507 clump_size_max = clump_size; 508 k_idx = i + (clump_size_max/2) + 1; 509 } 510 clump_size = 0; 511 } 512 } 513 if (k_idx==0){ 514 for (i=(param_cal_len-1); i>0; i--){ 515 if (param_cal_main[i]==param_token_empty){ 516 k_idx = i; 517 break; 518 } 519 } 520 } 521 if (k_idx>0 && k_idx<param_cal_len){ 522 param_cal_main[k_idx] = param_token_ancl; 523 TDM_PRINT1("TDM: Allocate ANCL slot at index #%03d\n", 524 k_idx); 525 } 526 else { 527 TDM_WARN1("TDM: Failed in %d-th ANCL slot allocation\n",j); 528 result = FAIL; 529 } 530 } 531 } 532 else { 533 k_prev = 0; 534 for (j=0; j<param_ancl_num; j++){ 535 k_idx = k_prev + ((param_cal_len-k_prev)/(param_ancl_num-j)) - 1; 536 param_cal_main[k_idx] = param_token_ancl; 537 k_prev= k_idx+1; 538 TDM_PRINT1("TDM: Allocate ANCL slot at index #%03d\n", 539 k_idx); 540 } 541 } 542 TDM_SML_BAR 543 } 544 545 return result; 546 } 547 548 549 /** 550 @name: tdm_gh2_proc_cal_idle 551 @param: 552 553 Allocate idle slots with matched speed rates accordingly 554 */ 555 int 556 tdm_gh2_proc_cal_idle( tdm_mod_t *_tdm ) 557 { 558 int i, result=PASS; 559 int param_lr_limit, param_ancl_num, param_cal_len, 560 param_token_empty, param_token_ovsb, 561 param_token_idl1, param_token_idl2, 562 param_os_en; 563 int *param_cal_main; 564 565 param_lr_limit = _tdm->_chip_data.soc_pkg.lr_idx_limit; 566 param_ancl_num = _tdm->_chip_data.soc_pkg.tvec_size; 567 param_cal_len = param_lr_limit + param_ancl_num; 568 param_token_empty = _tdm->_chip_data.soc_pkg.num_ext_ports; 569 param_token_ovsb = _tdm->_chip_data.soc_pkg.soc_vars.ovsb_token; 570 param_token_idl1 = _tdm->_chip_data.soc_pkg.soc_vars.idl1_token; 571 param_token_idl2 = _tdm->_chip_data.soc_pkg.soc_vars.idl2_token; 572 param_os_en = _tdm->_core_data.vars_pkg.os_enable; 573 574 TDM_SEL_CAL(_tdm->_core_data.vars_pkg.cal_id,param_cal_main); 575 576 if (param_os_en==BOOL_TRUE){ 577 for (i=0; i<param_cal_len; i++){ 578 if (param_cal_main[i]==param_token_empty){ 579 param_cal_main[i] = param_token_ovsb; 580 } 581 } 582 } 583 else { 584 for (i=0; i<param_cal_len; i++){ 585 if (param_cal_main[i]==param_token_empty){ 586 if ((i%2)==0){ 587 param_cal_main[i] = param_token_idl1; 588 } 589 else { 590 param_cal_main[i] = param_token_idl2; 591 } 592 } 593 } 594 } 595 596 return result; 597 } 598 599 600 /** 601 @name: tdm_gh2_proc_cal_lr 602 @param: 603 604 Allocate linerate slots with matched speed rates accordingly 605 */ 606 int 607 tdm_gh2_proc_cal_lr( tdm_mod_t *_tdm ) 608 { 609 int *param_lr_buff=NULL, result=PASS; 610 611 /* allocate Linerate slots (step-1): vmap pre-allocation */ 612 if(_tdm->_core_exec[TDM_CORE_EXEC__VMAP_PREALLOC](_tdm)!=PASS){ 613 result = FAIL; 614 } 615 /* allocate Linerate slots (step-2): vmap allocation */ 616 else{ 617 /* SPECIAL CASE: 4x106HG+3x40G uses a unique TDM in Tomahawk */ 618 param_lr_buff = _tdm->_core_data.vars_pkg.lr_buffer; 619 _tdm->_core_data.vars_pkg.HG4X106G_3X40G = BOOL_FALSE; 620 if (_tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.num_40g==3 && 621 _tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.num_100g==4 && 622 _tdm->_chip_data.soc_pkg.clk_freq==GH2_CLK_850MHZ) { 623 if (tdm_gh2_check_pipe_ethernet(param_lr_buff[0],_tdm)!=BOOL_TRUE|| 624 _tdm->_chip_data.soc_pkg.soc_vars.gh2.higig_mgmt==BOOL_TRUE || 625 _tdm->_chip_data.soc_pkg.soc_vars.gh2.cal_hg_en==BOOL_TRUE ){ 626 _tdm->_chip_data.soc_pkg.tvec_size = 9; 627 _tdm->_chip_data.soc_pkg.lr_idx_limit= 201; 628 _tdm->_core_data.vars_pkg.HG4X106G_3X40G = BOOL_TRUE; 629 TDM_PRINT0("TDM: Special case 4x106HG_3x40HG\n"); 630 } 631 } 632 /* vmap allocation */ 633 if(_tdm->_core_exec[TDM_CORE_EXEC__VMAP_ALLOC](_tdm)!=PASS){ 634 result = FAIL; 635 } 636 } 637 638 return result; 639 } 640 641 642 /** 643 @name: tdm_gh2_proc_cal 644 @param: 645 646 Allocate slots for linerate/oversub/ancl ports with matched speed rates accordingly 647 */ 648 int 649 tdm_gh2_proc_cal( tdm_mod_t *_tdm ) 650 { 651 /* allocate LINERATE slots */ 652 if(tdm_gh2_proc_cal_lr(_tdm)!=PASS){ 653 return (TDM_EXEC_CORE_SIZE+1); 654 } 655 /* allocate ANCILLARY slots */ 656 if(tdm_gh2_proc_cal_ancl(_tdm)!=PASS){ 657 return (TDM_EXEC_CORE_SIZE+1); 658 } 659 /* allocate IDLE/OVSB slots */ 660 if(tdm_gh2_proc_cal_idle(_tdm)!=PASS){ 661 return (TDM_EXEC_CORE_SIZE+1); 662 } 663 664 return ( _tdm->_core_exec[TDM_CORE_EXEC__SCHEDULER](_tdm) ); 665 }