tdm_gh2_parse.c (14069B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * $All Rights Reserved.$ 7 * 8 * TDM chip based printing and parsing functions 9 */ 10 #ifdef _TDM_STANDALONE 11 #include <tdm_top.h> 12 #else 13 #include <soc/tdm/core/tdm_top.h> 14 #endif 15 16 17 /** 18 @name: tdm_gh2_print_tbl 19 @param: 20 21 Prints PGW TDM main calendar 22 */ 23 void 24 tdm_gh2_print_tbl(tdm_mod_t *_tdm) 25 { 26 int idx, *cal_idb, *cal_mmu, cal_idb_len=0, cal_mmu_len=0, check=PASS; 27 28 switch(_tdm->_core_data.vars_pkg.cal_id) { 29 case 0: 30 cal_idb = _tdm->_chip_data.cal_0.cal_main; 31 cal_mmu = _tdm->_chip_data.cal_4.cal_main; 32 cal_idb_len = _tdm->_chip_data.cal_0.cal_len; 33 cal_mmu_len = _tdm->_chip_data.cal_4.cal_len; 34 break; 35 case 1: 36 cal_idb = _tdm->_chip_data.cal_1.cal_main; 37 cal_mmu = _tdm->_chip_data.cal_5.cal_main; 38 cal_idb_len = _tdm->_chip_data.cal_1.cal_len; 39 cal_mmu_len = _tdm->_chip_data.cal_5.cal_len; 40 break; 41 case 2: 42 cal_idb = _tdm->_chip_data.cal_2.cal_main; 43 cal_mmu = _tdm->_chip_data.cal_6.cal_main; 44 cal_idb_len = _tdm->_chip_data.cal_2.cal_len; 45 cal_mmu_len = _tdm->_chip_data.cal_6.cal_len; 46 break; 47 case 3: 48 cal_idb = _tdm->_chip_data.cal_3.cal_main; 49 cal_mmu = _tdm->_chip_data.cal_7.cal_main; 50 cal_idb_len = _tdm->_chip_data.cal_3.cal_len; 51 cal_mmu_len = _tdm->_chip_data.cal_7.cal_len; 52 break; 53 default: 54 TDM_PRINT1("Invalid calendar ID - %0d\n",_tdm->_core_data.vars_pkg.cal_id); 55 check = FAIL; 56 break; 57 } 58 59 if (check==PASS){ 60 if (cal_idb_len==cal_mmu_len){ 61 TDM_SML_BAR 62 TDM_PRINT4("TDM: Pipe %d, IDB/MMU table, table length %d (%d+%d)\n", _tdm->_core_data.vars_pkg.cal_id, _tdm->_chip_data.soc_pkg.lr_idx_limit+_tdm->_chip_data.soc_pkg.tvec_size,_tdm->_chip_data.soc_pkg.lr_idx_limit,_tdm->_chip_data.soc_pkg.tvec_size); 63 TDM_PRINT4("TDM: Pipe %d \t %4s \t %3s \t %3s\n", _tdm->_core_data.vars_pkg.cal_id, "idx", "IDB", "MMU"); 64 for (idx=0; idx<cal_mmu_len; idx++) { 65 TDM_PRINT4("TDM: Pipe %d \t #%03d \t %3d \t %3d\n", _tdm->_core_data.vars_pkg.cal_id, idx, cal_idb[idx], cal_mmu[idx]); 66 } 67 } 68 69 } 70 } 71 72 73 /** 74 @name: tdm_gh2_print_config 75 @param: 76 77 Parses pipe config from class structs 78 */ 79 void 80 tdm_gh2_print_config( tdm_mod_t *_tdm ) 81 { 82 int i, lgc_idx=0, tsc_idx, config_pass=BOOL_TRUE; 83 TDM_SML_BAR 84 TDM_SML_BAR 85 TDM_PRINT0(" Port Info based on config.bcm\n"); 86 TDM_SML_BAR 87 TDM_PRINT6("%4s%4s%8s%8s%8s%8s\n", "lgc", "phy", "spd","state", "encap", "traffic"); 88 89 for (i=0;i<GH2_NUM_EXT_PORTS;i++){ 90 if (_tdm->_chip_data.soc_pkg.speed[i]>0) { 91 lgc_idx++; 92 TDM_PRINT1("%4d", lgc_idx); 93 } 94 else{ 95 TDM_PRINT1("%4s", ""); 96 } 97 TDM_PRINT1("%4d", i); 98 TDM_PRINT1("%8d", _tdm->_chip_data.soc_pkg.speed[i]/1000); 99 if (i>0){ 100 switch (_tdm->_chip_data.soc_pkg.state[i-1]){ 101 case PORT_STATE__LINERATE: 102 TDM_PRINT2("%8s%8s","[LNRT]","[ETHN]"); 103 break; 104 case PORT_STATE__OVERSUB: 105 TDM_PRINT2("%8s%8s","[OVSB]", "[ETHN]"); 106 break; 107 case PORT_STATE__LINERATE_HG: 108 TDM_PRINT2("%8s%8s","[LNRT]", "[HIG2]"); 109 break; 110 case PORT_STATE__OVERSUB_HG: 111 TDM_PRINT2("%8s%8s","[OVSB]", "[HIG2]"); 112 break; 113 case PORT_STATE__COMBINE: 114 TDM_PRINT2("%8s%8s","[COM]", "[----]"); 115 break; 116 case PORT_STATE__COMBINE_HG: 117 TDM_PRINT2("%8s%8s","[COM]", "[----]"); 118 break; 119 default: 120 TDM_PRINT2("%8s%8s","[----]","[----]"); 121 break; 122 } 123 124 tsc_idx = (i-1)/4; 125 if (tsc_idx < GH2_NUM_PHY_PM){ 126 switch(_tdm->_chip_data.soc_pkg.soc_vars.gh2.pm_encap_type[tsc_idx]){ 127 case PM_ENCAP__ETHRNT: 128 TDM_PRINT1("%8s", "[ETHN]"); 129 break; 130 case PM_ENCAP__HIGIG2: 131 TDM_PRINT1("%8s", "[HIG2]"); 132 break; 133 default: 134 TDM_PRINT1("%8s", "[----]"); 135 break; 136 } 137 if ( ( (_tdm->_chip_data.soc_pkg.soc_vars.gh2.pm_encap_type[tsc_idx]== PM_ENCAP__HIGIG2) && (_tdm->_chip_data.soc_pkg.state[i-1]==PORT_STATE__LINERATE || _tdm->_chip_data.soc_pkg.state[i-1]==PORT_STATE__OVERSUB) ) || 138 ( (_tdm->_chip_data.soc_pkg.soc_vars.gh2.pm_encap_type[tsc_idx]== PM_ENCAP__ETHRNT) && (_tdm->_chip_data.soc_pkg.state[i-1]==PORT_STATE__LINERATE_HG || _tdm->_chip_data.soc_pkg.state[i-1]==PORT_STATE__OVERSUB_HG) ) ){ 139 TDM_PRINT1("\t%s", "[XXXX]"); 140 config_pass = BOOL_FALSE; 141 } 142 } 143 } 144 TDM_PRINT0("\n"); 145 146 if(i>0 && i%4==0){TDM_PRINT0("\n");} 147 } 148 TDM_PRINT0("\n"); 149 if (config_pass==BOOL_FALSE){TDM_PRINT0("TDM ERROR: config.bcm failed, encap type violation\n");} 150 TDM_PRINT0("\n"); 151 TDM_BIG_BAR 152 } 153 154 155 /** 156 @name: tdm_gh2_parse_pipe 157 @param: 158 159 Parses pipe config from class structs 160 */ 161 void 162 tdm_gh2_parse_pipe( tdm_mod_t *_tdm ) 163 { 164 int iter, iter2, len, idx_start, idx_end; 165 enum port_speed_e *speed = _tdm->_chip_data.soc_pkg.speed; 166 enum port_state_e *state = _tdm->_chip_data.soc_pkg.state; 167 168 idx_start= _tdm->_chip_data.soc_pkg.soc_vars.gh2.pipe_start; 169 idx_end = _tdm->_chip_data.soc_pkg.soc_vars.gh2.pipe_end; 170 len = GH2_NUM_PHY_PORTS; 171 172 if (idx_start>0 && idx_end<=len){ 173 TDM_BIG_BAR 174 TDM_PRINT0("TDM: --- Pipe Config ---: "); 175 for (iter=idx_start; iter<=idx_end; iter++) { 176 if ((((iter-1)%16)==0)) { 177 TDM_PRINT0("\nTDM: "); 178 } 179 TDM_PRINT1("{%03d}\t",(iter)); 180 if (iter%16==0) { 181 TDM_PRINT0("\nTDM: "); 182 for (iter2=(iter-16); iter2<iter; iter2++) { 183 TDM_PRINT1(" %3d \t", speed[iter2+1]/1000); 184 } 185 TDM_PRINT0("\nTDM: "); 186 for (iter2=(iter-16); iter2<iter; iter2++) { 187 if (iter2%4==0){ 188 if(speed[iter2+1]/1000>0){ 189 switch ((PSBMP_LP_MASK & state[iter2])) { 190 case 1: 191 TDM_PRINT0("LINE \t --- \t --- \t --- \t"); 192 break; 193 case 2: 194 TDM_PRINT0("OVSB \t --- \t --- \t --- \t"); 195 break; 196 default: 197 TDM_PRINT0(" \t \t \t \t"); 198 break; 199 } 200 } 201 else{ 202 TDM_PRINT0(" \t \t \t \t"); 203 } 204 } 205 } 206 TDM_PRINT0("\nTDM: "); 207 for (iter2=(iter-16); iter2<iter; iter2++) { 208 if(iter2%4==0){ 209 if(speed[iter2+1]/1000>0){ 210 switch(( PSBMP_ENCAP_HIGIG & state[iter2])){ 211 case 0: 212 TDM_PRINT0(" EN \t --- \t --- \t --- \t"); 213 break; 214 case 4: 215 TDM_PRINT0(" HG \t --- \t --- \t --- \t"); 216 break; 217 default: 218 TDM_PRINT0(" \t \t \t \t"); 219 break; 220 } 221 } 222 else{ 223 TDM_PRINT0(" \t \t \t \t"); 224 } 225 } 226 } 227 } 228 } 229 TDM_PRINT0("\n"); 230 TDM_BIG_BAR 231 } 232 233 } 234 235 236 /** 237 @name: tdm_gh2_parse_tdm_tbl 238 @param: 239 240 Postprocesses TDM calendar tokenized entries 241 */ 242 int 243 tdm_gh2_parse_tdm_tbl( tdm_mod_t *_tdm ) 244 { 245 int i, j, m; 246 tdm_calendar_t cal_idb; 247 tdm_calendar_t cal_mmu; 248 249 switch(_tdm->_core_data.vars_pkg.cal_id) { 250 case 0: cal_idb=_tdm->_chip_data.cal_0; cal_mmu=_tdm->_chip_data.cal_4; break; 251 case 1: cal_idb=_tdm->_chip_data.cal_1; cal_mmu=_tdm->_chip_data.cal_5; break; 252 case 2: cal_idb=_tdm->_chip_data.cal_2; cal_mmu=_tdm->_chip_data.cal_6; break; 253 case 3: cal_idb=_tdm->_chip_data.cal_3; cal_mmu=_tdm->_chip_data.cal_7; break; 254 default: 255 TDM_PRINT1("Invalid calendar ID - %0d\n",_tdm->_core_data.vars_pkg.cal_id); 256 return (TDM_EXEC_CORE_SIZE+1); 257 } 258 for (j=0; j<256; j++) { 259 cal_mmu.cal_main[j]=cal_idb.cal_main[j]; 260 } 261 for (i=0; i<GH2_OS_VBS_GRP_NUM; i++) { 262 for (j=0; j<GH2_OS_VBS_GRP_LEN; j++) { 263 cal_mmu.cal_grp[i][j]=cal_idb.cal_grp[i][j]; 264 } 265 } 266 m=0; 267 for (j=0; j<256; j++) { 268 if (cal_idb.cal_main[j]!=GH2_ANCL_TOKEN) { 269 TDM_PRINT3("TDM: PIPE %d, IDB TDM TABLE, element #%0d, contains physical port #%0d\n",_tdm->_core_data.vars_pkg.pipe,j,cal_idb.cal_main[j]); 270 } 271 else { 272 TDM_PRINT2("TDM: PIPE %d, IDB TDM TABLE, element #%0d, CONTAINS ACCESSORY TOKEN - assigned as ",_tdm->_core_data.vars_pkg.pipe,j); 273 m++; 274 switch (_tdm->_core_data.vars_pkg.pipe) { 275 case 0: 276 switch (m) { 277 case 1: case 3: case 7: case 9: 278 GH2_CMIC(j,cal_idb.cal_main) 279 case 2: case 6: 280 GH2_LPB0(j,cal_idb.cal_main) 281 case 4: case 10: 282 GH2_OPRT(j,cal_idb.cal_main) 283 case 5: 284 GH2_NULL(j,cal_idb.cal_main) 285 case 8: 286 GH2_SBUS(j,cal_idb.cal_main) 287 } 288 break; 289 case 1: 290 switch (m) { 291 case 1: case 3: case 7: case 9: 292 GH2_MGM1(j,cal_idb.cal_main) 293 case 2: case 6: 294 GH2_LPB1(j,cal_idb.cal_main) 295 case 4: case 10: 296 GH2_OPRT(j,cal_idb.cal_main) 297 case 5: 298 GH2_NULL(j,cal_idb.cal_main) 299 case 8: 300 GH2_SBUS(j,cal_idb.cal_main) 301 } 302 break; 303 case 2: 304 switch (m) { 305 case 1: case 3: case 7: case 9: 306 GH2_MGM2(j,cal_idb.cal_main) 307 case 2: case 6: 308 GH2_LPB2(j,cal_idb.cal_main) 309 case 4: case 10: 310 GH2_OPRT(j,cal_idb.cal_main) 311 case 5: 312 GH2_NULL(j,cal_idb.cal_main) 313 case 8: 314 GH2_SBUS(j,cal_idb.cal_main) 315 } 316 break; 317 case 3: 318 switch (m) { 319 case 1: case 3: case 7: case 9: 320 GH2_DOT3(j,cal_idb.cal_main) 321 case 2: case 6: 322 GH2_LPB3(j,cal_idb.cal_main) 323 case 4: case 10: 324 GH2_OPRT(j,cal_idb.cal_main) 325 case 5: 326 GH2_NULL(j,cal_idb.cal_main) 327 case 8: 328 GH2_SBUS(j,cal_idb.cal_main) 329 } 330 break; 331 } 332 } 333 } 334 for (j=0; j<GH2_OS_VBS_GRP_LEN; j++) { 335 TDM_PRINT3("TDM: PIPE %d, IDB OVS BUCKET 0, element #%0d, contains physical port #%0d\n",_tdm->_core_data.vars_pkg.pipe,j,cal_idb.cal_grp[0][j]); 336 } 337 for (j=0; j<GH2_OS_VBS_GRP_LEN; j++) { 338 TDM_PRINT3("TDM: PIPE %d, IDB OVS BUCKET 1, element #%0d, contains physical port #%0d\n",_tdm->_core_data.vars_pkg.pipe,j,cal_idb.cal_grp[1][j]); 339 } 340 for (j=0; j<GH2_OS_VBS_GRP_LEN; j++) { 341 TDM_PRINT3("TDM: PIPE %d, IDB OVS BUCKET 2, element #%0d, contains physical port #%0d\n",_tdm->_core_data.vars_pkg.pipe,j,cal_idb.cal_grp[2][j]); 342 } 343 for (j=0; j<GH2_OS_VBS_GRP_LEN; j++) { 344 TDM_PRINT3("TDM: PIPE %d, IDB OVS BUCKET 3, element #%0d, contains physical port #%0d\n",_tdm->_core_data.vars_pkg.pipe,j,cal_idb.cal_grp[3][j]); 345 } 346 for (j=0; j<GH2_OS_VBS_GRP_LEN; j++) { 347 TDM_PRINT3("TDM: PIPE %d, IDB OVS BUCKET 4, element #%0d, contains physical port #%0d\n",_tdm->_core_data.vars_pkg.pipe,j,cal_idb.cal_grp[4][j]); 348 } 349 for (j=0; j<GH2_OS_VBS_GRP_LEN; j++) { 350 TDM_PRINT3("TDM: PIPE %d, IDB OVS BUCKET 5, element #%0d, contains physical port #%0d\n",_tdm->_core_data.vars_pkg.pipe,j,cal_idb.cal_grp[5][j]); 351 } 352 for (j=0; j<GH2_OS_VBS_GRP_LEN; j++) { 353 TDM_PRINT3("TDM: PIPE %d, IDB OVS BUCKET 6, element #%0d, contains physical port #%0d\n",_tdm->_core_data.vars_pkg.pipe,j,cal_idb.cal_grp[6][j]); 354 } 355 for (j=0; j<GH2_OS_VBS_GRP_LEN; j++) { 356 TDM_PRINT3("TDM: PIPE %d, IDB OVS BUCKET 7, element #%0d, contains physical port #%0d\n",_tdm->_core_data.vars_pkg.pipe,j,cal_idb.cal_grp[7][j]); 357 } 358 m=0; 359 for (j=0; j<256; j++) { 360 if (cal_mmu.cal_main[j]!=GH2_ANCL_TOKEN) { 361 TDM_PRINT3("TDM: PIPE %d, MMU TDM TABLE, element #%0d, contains physical port #%0d\n",_tdm->_core_data.vars_pkg.pipe,j,cal_mmu.cal_main[j]); 362 } 363 else { 364 TDM_PRINT2("TDM: PIPE %d, MMU TDM TABLE, element #%0d, CONTAINS ACCESSORY TOKEN - assigned as ",_tdm->_core_data.vars_pkg.pipe,j); 365 m++; 366 switch (_tdm->_core_data.vars_pkg.pipe) { 367 case 0: 368 switch (m) { 369 case 1: case 3: case 7: case 9: 370 GH2_CMIC(j,cal_mmu.cal_main) 371 case 2: case 6: 372 GH2_LPB0(j,cal_mmu.cal_main) 373 case 4: case 5: case 8: 374 GH2_NULL(j,cal_mmu.cal_main) 375 case 10: 376 GH2_OPRT(j,cal_mmu.cal_main) 377 } 378 break; 379 case 1: 380 switch (m) { 381 case 1: case 3: case 7: case 9: 382 GH2_MGM1(j,cal_mmu.cal_main) 383 case 2: case 6: 384 GH2_LPB1(j,cal_mmu.cal_main) 385 case 4: case 5: case 8: 386 GH2_NULL(j,cal_mmu.cal_main) 387 case 10: 388 GH2_OPRT(j,cal_mmu.cal_main) 389 } 390 break; 391 case 2: 392 switch (m) { 393 case 1: case 3: case 7: case 9: 394 GH2_MGM2(j,cal_mmu.cal_main) 395 case 2: case 6: 396 GH2_LPB2(j,cal_mmu.cal_main) 397 case 4: case 5: case 8: 398 GH2_NULL(j,cal_mmu.cal_main) 399 case 10: 400 GH2_OPRT(j,cal_mmu.cal_main) 401 } 402 break; 403 case 3: 404 switch (m) { 405 case 1: case 3: case 7: case 9: 406 GH2_DOT3(j,cal_mmu.cal_main) 407 case 2: case 6: 408 GH2_LPB3(j,cal_mmu.cal_main) 409 case 4: case 5: case 8: 410 GH2_NULL(j,cal_mmu.cal_main) 411 case 10: 412 GH2_OPRT(j,cal_mmu.cal_main) 413 } 414 break; 415 } 416 } 417 } 418 for (j=0; j<GH2_OS_VBS_GRP_LEN; j++) { 419 TDM_PRINT3("TDM: PIPE %d, MMU OVS BUCKET 0, element #%0d, contains physical port #%0d\n",_tdm->_core_data.vars_pkg.pipe,j,cal_mmu.cal_grp[0][j]); 420 } 421 for (j=0; j<GH2_OS_VBS_GRP_LEN; j++) { 422 TDM_PRINT3("TDM: PIPE %d, MMU OVS BUCKET 1, element #%0d, contains physical port #%0d\n",_tdm->_core_data.vars_pkg.pipe,j,cal_mmu.cal_grp[1][j]); 423 } 424 for (j=0; j<GH2_OS_VBS_GRP_LEN; j++) { 425 TDM_PRINT3("TDM: PIPE %d, MMU OVS BUCKET 2, element #%0d, contains physical port #%0d\n",_tdm->_core_data.vars_pkg.pipe,j,cal_mmu.cal_grp[2][j]); 426 } 427 for (j=0; j<GH2_OS_VBS_GRP_LEN; j++) { 428 TDM_PRINT3("TDM: PIPE %d, MMU OVS BUCKET 3, element #%0d, contains physical port #%0d\n",_tdm->_core_data.vars_pkg.pipe,j,cal_mmu.cal_grp[3][j]); 429 } 430 for (j=0; j<GH2_OS_VBS_GRP_LEN; j++) { 431 TDM_PRINT3("TDM: PIPE %d, MMU OVS BUCKET 4, element #%0d, contains physical port #%0d\n",_tdm->_core_data.vars_pkg.pipe,j,cal_mmu.cal_grp[4][j]); 432 } 433 for (j=0; j<GH2_OS_VBS_GRP_LEN; j++) { 434 TDM_PRINT3("TDM: PIPE %d, MMU OVS BUCKET 5, element #%0d, contains physical port #%0d\n",_tdm->_core_data.vars_pkg.pipe,j,cal_mmu.cal_grp[5][j]); 435 } 436 for (j=0; j<GH2_OS_VBS_GRP_LEN; j++) { 437 TDM_PRINT3("TDM: PIPE %d, MMU OVS BUCKET 6, element #%0d, contains physical port #%0d\n",_tdm->_core_data.vars_pkg.pipe,j,cal_mmu.cal_grp[6][j]); 438 } 439 for (j=0; j<GH2_OS_VBS_GRP_LEN; j++) { 440 TDM_PRINT3("TDM: PIPE %d, MMU OVS BUCKET 7, element #%0d, contains physical port #%0d\n",_tdm->_core_data.vars_pkg.pipe,j,cal_mmu.cal_grp[7][j]); 441 } 442 443 return ( _tdm->_chip_exec[TDM_CHIP_EXEC__POST]( _tdm ) ); 444 }