tdm_ap_shim.c (11498B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * $All Rights Reserved.$ 7 * 8 * TDM chip to core API shim layer 9 */ 10 #ifdef _TDM_STANDALONE 11 #include <tdm_top.h> 12 #else 13 #include <soc/tdm/core/tdm_top.h> 14 #endif 15 16 17 /** 18 @name: tdm_chip_ap_shim_core 19 @param: 20 21 Downward abstraction layer between TDM.4 and TDM.5 API core data 22 */ 23 int 24 tdm_chip_ap_shim_core( tdm_mod_t *_tdm, tdm_ap_chip_legacy_t *_tdm_ap) 25 { 26 int idx1, idx2; 27 28 if (_tdm==NULL || _tdm_ap==NULL) {return FAIL;} 29 30 /* port map */ 31 for (idx1=0; idx1<AP_NUM_PHY_PM; idx1++) { 32 for (idx2=0; idx2<AP_NUM_PM_LNS; idx2++) { 33 _tdm_ap->pmap[idx1][idx2] = _tdm->_chip_data.soc_pkg.pmap[idx1][idx2]; 34 } 35 } 36 /* speed */ 37 for (idx1=0; idx1<(AP_NUM_EXT_PORTS-56); idx1++) { 38 _tdm_ap->tdm_globals.speed[idx1] = _tdm->_chip_data.soc_pkg.speed[idx1]; 39 } 40 /* freq */ 41 _tdm_ap->tdm_globals.clk_freq = _tdm->_chip_data.soc_pkg.clk_freq; 42 /* state : Realign port state array to old specification */ 43 for (idx1=0; idx1<(AP_NUM_EXT_PORTS-56); idx1++) { 44 _tdm_ap->tdm_globals.port_rates_array[idx1] = _tdm->_chip_data.soc_pkg.state[idx1]; 45 } 46 for (idx1=0; idx1<(AP_NUM_EXT_PORTS-57); idx1++) { 47 _tdm_ap->tdm_globals.port_rates_array[idx1] = _tdm_ap->tdm_globals.port_rates_array[idx1+1]; 48 } 49 /* encap_type */ 50 for (idx1=0; idx1<(AP_NUM_EXT_PORTS-56); idx1++) { 51 if (idx1%AP_NUM_PM_LNS==0 && (idx1/AP_NUM_PM_LNS)<AP_NUM_PM_MOD) { 52 _tdm_ap->tdm_globals.pm_encap_type[idx1/AP_NUM_PM_LNS] = (_tdm->_chip_data.soc_pkg.state[idx1]==PORT_STATE__LINERATE_HG||_tdm->_chip_data.soc_pkg.state[idx1]==PORT_STATE__OVERSUB_HG)?(PM_ENCAP__HIGIG2):(PM_ENCAP__ETHRNT); 53 } 54 } 55 /*set : if clport is in 100G or 25G*/ 56 for (idx1=1; idx1<=AP_NUM_PHY_PORTS; idx1+=AP_NUM_PM_LNS) { 57 _tdm_ap->tdm_globals.cl_flag = BOOL_FALSE; 58 if( (idx1==AP_CL1_PORT || idx1==AP_CL2_PORT || idx1==AP_CL4_PORT || idx1==AP_CL5_PORT ) && ( _tdm->_chip_data.soc_pkg.speed[idx1]==SPEED_100G || _tdm->_chip_data.soc_pkg.speed[idx1]==SPEED_50G || _tdm->_chip_data.soc_pkg.speed[idx1]==SPEED_25G) ) { 59 _tdm_ap->tdm_globals.cl_flag = BOOL_TRUE; 60 break; 61 } 62 } 63 /*num_1g ports: required for f3_2 TDM*/ 64 _tdm_ap->tdm_globals.num_1g=0; 65 for (idx1=0; idx1<(AP_NUM_EXT_PORTS-56); idx1++) { 66 if(_tdm_ap->tdm_globals.speed[idx1] == SPEED_1G || _tdm_ap->tdm_globals.speed[idx1]==SPEED_2p5G) { _tdm_ap->tdm_globals.num_1g++ ;} 67 } 68 return PASS; 69 } 70 71 72 /** 73 @name: tdm_chip_ap_shim__ing_wrap 74 @param: 75 76 Downward abstraction layer between TDM.4 and TDM.5 API ingress scheduler 77 */ 78 int 79 tdm_chip_ap_shim__ing_wrap( tdm_mod_t *_tdm, tdm_ap_chip_legacy_t *_tdm_ap) 80 { 81 if (FAIL == tdm_chip_ap_shim_core(_tdm, _tdm_ap)) {return FAIL;} 82 83 TDM_MSET(_tdm_ap->tdm_pgw.pgw_tdm_tbl_x0,AP_NUM_EXT_PORTS,AP_LR_LLS_LEN); 84 TDM_MSET(_tdm_ap->tdm_pgw.ovs_tdm_tbl_x0,AP_NUM_EXT_PORTS,AP_OS_LLS_GRP_LEN); 85 TDM_MSET(_tdm_ap->tdm_pgw.ovs_spacing_x0,AP_NUM_EXT_PORTS,AP_OS_LLS_GRP_LEN); 86 TDM_MSET(_tdm_ap->tdm_pgw.pgw_tdm_tbl_x1,AP_NUM_EXT_PORTS,AP_LR_LLS_LEN); 87 TDM_MSET(_tdm_ap->tdm_pgw.ovs_tdm_tbl_x1,AP_NUM_EXT_PORTS,AP_OS_LLS_GRP_LEN); 88 TDM_MSET(_tdm_ap->tdm_pgw.ovs_spacing_x1,AP_NUM_EXT_PORTS,AP_OS_LLS_GRP_LEN); 89 90 TDM_MSET(_tdm_ap->tdm_pipe_table_x.tdm_pipe_main,AP_NUM_EXT_PORTS,AP_LR_VBS_LEN); 91 TDM_MSET(_tdm_ap->tdm_pipe_table_x.tdm_ovs_grp_0,AP_NUM_EXT_PORTS,AP_OS_VBS_GRP_LEN); 92 TDM_MSET(_tdm_ap->tdm_pipe_table_x.tdm_ovs_grp_1,AP_NUM_EXT_PORTS,AP_OS_VBS_GRP_LEN); 93 TDM_MSET(_tdm_ap->tdm_pipe_table_x.tdm_ovs_grp_2,AP_NUM_EXT_PORTS,AP_OS_VBS_GRP_LEN); 94 TDM_MSET(_tdm_ap->tdm_pipe_table_x.tdm_ovs_grp_3,AP_NUM_EXT_PORTS,AP_OS_VBS_GRP_LEN); 95 TDM_MSET(_tdm_ap->tdm_pipe_table_x.tdm_ovs_grp_4,AP_NUM_EXT_PORTS,AP_OS_VBS_GRP_LEN); 96 TDM_MSET(_tdm_ap->tdm_pipe_table_x.tdm_ovs_grp_5,AP_NUM_EXT_PORTS,AP_OS_VBS_GRP_LEN); 97 TDM_MSET(_tdm_ap->tdm_pipe_table_x.tdm_ovs_grp_6,AP_NUM_EXT_PORTS,AP_OS_VBS_GRP_LEN); 98 TDM_MSET(_tdm_ap->tdm_pipe_table_x.tdm_ovs_grp_7,AP_NUM_EXT_PORTS,AP_OS_VBS_GRP_LEN); 99 100 return PASS; 101 102 } 103 104 105 /** 106 @name: tdm_chip_ap_shim__egr_wrap 107 @param: 108 109 Downward abstraction layer between TDM.4 and TDM.5 API egress scheduler 110 */ 111 int 112 tdm_chip_ap_shim__egr_wrap( tdm_mod_t *_tdm, tdm_ap_chip_legacy_t *_tdm_ap ) 113 { 114 if (FAIL == tdm_chip_ap_shim_core(_tdm, _tdm_ap)) {return FAIL;} 115 116 TDM_COPY(_tdm_ap->tdm_pgw.pgw_tdm_tbl_x0,_tdm->_chip_data.cal_0.cal_main,sizeof(int)*AP_LR_LLS_LEN); 117 TDM_COPY(_tdm_ap->tdm_pgw.ovs_tdm_tbl_x0,_tdm->_chip_data.cal_0.cal_grp[0],sizeof(int)*AP_OS_LLS_GRP_LEN); 118 TDM_COPY(_tdm_ap->tdm_pgw.pgw_tdm_tbl_x1,_tdm->_chip_data.cal_1.cal_main,sizeof(int)*AP_LR_LLS_LEN); 119 TDM_COPY(_tdm_ap->tdm_pgw.ovs_tdm_tbl_x1,_tdm->_chip_data.cal_1.cal_grp[0],sizeof(int)*AP_OS_LLS_GRP_LEN); 120 121 TDM_MSET(_tdm_ap->tdm_pipe_table_x.tdm_pipe_main,AP_NUM_EXT_PORTS,AP_LR_VBS_LEN); 122 TDM_MSET(_tdm_ap->tdm_pipe_table_x.tdm_ovs_grp_0,AP_NUM_EXT_PORTS,AP_OS_VBS_GRP_LEN); 123 TDM_MSET(_tdm_ap->tdm_pipe_table_x.tdm_ovs_grp_1,AP_NUM_EXT_PORTS,AP_OS_VBS_GRP_LEN); 124 TDM_MSET(_tdm_ap->tdm_pipe_table_x.tdm_ovs_grp_2,AP_NUM_EXT_PORTS,AP_OS_VBS_GRP_LEN); 125 TDM_MSET(_tdm_ap->tdm_pipe_table_x.tdm_ovs_grp_3,AP_NUM_EXT_PORTS,AP_OS_VBS_GRP_LEN); 126 TDM_MSET(_tdm_ap->tdm_pipe_table_x.tdm_ovs_grp_4,AP_NUM_EXT_PORTS,AP_OS_VBS_GRP_LEN); 127 TDM_MSET(_tdm_ap->tdm_pipe_table_x.tdm_ovs_grp_5,AP_NUM_EXT_PORTS,AP_OS_VBS_GRP_LEN); 128 TDM_MSET(_tdm_ap->tdm_pipe_table_x.tdm_ovs_grp_6,AP_NUM_EXT_PORTS,AP_OS_VBS_GRP_LEN); 129 TDM_MSET(_tdm_ap->tdm_pipe_table_x.tdm_ovs_grp_7,AP_NUM_EXT_PORTS,AP_OS_VBS_GRP_LEN); 130 131 return PASS; 132 133 } 134 135 136 /** 137 @name: tdm_chip_ap_shim__which_tsc_alloc 138 @param: 139 140 Upward abstraction layer between TDM.4 and TDM.5 API 141 Only returns enough of TDM.5 style struct to drive scan functions, do not use as class 142 */ 143 tdm_mod_t* 144 tdm_chip_ap_shim__which_tsc_alloc( int port, int tsc[AP_NUM_PHY_PM][AP_NUM_PM_LNS] ) 145 { 146 int idx1, idx2; 147 tdm_mod_t *_tdm_s; 148 149 _tdm_s = TDM_ALLOC(sizeof(tdm_mod_t),"TDM shim allocation"); 150 if (!_tdm_s) { 151 return NULL; 152 } 153 154 _tdm_s->_chip_data.soc_pkg.num_ext_ports = AP_NUM_EXT_PORTS; 155 _tdm_s->_chip_data.soc_pkg.pmap_num_modules = AP_NUM_PHY_PM; 156 _tdm_s->_chip_data.soc_pkg.pmap_num_lanes = AP_NUM_PM_LNS; 157 _tdm_s->_chip_data.soc_pkg.pmap=(int **) TDM_ALLOC((_tdm_s->_chip_data.soc_pkg.pmap_num_modules)*sizeof(int *), "portmod_map_l1"); 158 for (idx1=0; idx1<(_tdm_s->_chip_data.soc_pkg.pmap_num_modules); idx1++) { 159 _tdm_s->_chip_data.soc_pkg.pmap[idx1]=(int *) TDM_ALLOC((_tdm_s->_chip_data.soc_pkg.pmap_num_lanes)*sizeof(int), "portmod_map_l2"); 160 TDM_MSET(_tdm_s->_chip_data.soc_pkg.pmap[idx1],(_tdm_s->_chip_data.soc_pkg.num_ext_ports),_tdm_s->_chip_data.soc_pkg.pmap_num_lanes); 161 } 162 for (idx1=0; idx1<AP_NUM_PHY_PM; idx1++) { 163 for (idx2=0; idx2<AP_NUM_PM_LNS; idx2++) { 164 _tdm_s->_chip_data.soc_pkg.pmap[idx1][idx2] = tsc[idx1][idx2]; 165 } 166 } 167 /* to get mapping of mngmnt ports*/ 168 for (idx1=0; idx1<AP_NUM_PHY_PM; idx1++) { 169 for (idx2=0; idx2<AP_NUM_PM_LNS; idx2++) { 170 if( (_tdm_s->_chip_data.soc_pkg.pmap[idx1][idx2]== 29 || 171 _tdm_s->_chip_data.soc_pkg.pmap[idx1][idx2]== 33 || 172 _tdm_s->_chip_data.soc_pkg.pmap[idx1][idx2]== 65 || 173 _tdm_s->_chip_data.soc_pkg.pmap[idx1][idx2]== 69) && 174 (idx1 < 7 || (idx1>8 && idx1<16)) ) { 175 _tdm_s->_chip_data.soc_pkg.pmap[idx1][idx2] = AP_NUM_EXT_PORTS; 176 } 177 } 178 } 179 180 181 182 _tdm_s->_core_data.vars_pkg.port = port; 183 184 return _tdm_s; 185 186 } 187 188 /** 189 @name: tdm_chip_ap_shim__which_tsc_free 190 @param: 191 */ 192 int 193 tdm_chip_ap_shim__which_tsc_free(tdm_mod_t *_tdm) 194 { 195 int idx1; 196 tdm_mod_t *_tdm_s=_tdm; 197 /* pmap */ 198 for(idx1=0;idx1<(_tdm_s->_chip_data.soc_pkg.pmap_num_modules); idx1++) { 199 TDM_FREE(_tdm_s->_chip_data.soc_pkg.pmap[idx1]); 200 } 201 TDM_FREE(_tdm_s->_chip_data.soc_pkg.pmap); 202 /* _tdm */ 203 TDM_FREE(_tdm_s); 204 205 return PASS; 206 207 } 208 209 210 /** 211 @name: tdm_chip_ap_shim__check_ethernet 212 @param: 213 214 Upward abstraction layer between TDM.4 and TDM.5 API 215 */ 216 tdm_mod_t* 217 tdm_chip_ap_shim__check_ethernet( int port, enum port_speed_e speed[AP_NUM_EXT_PORTS], int tsc[AP_NUM_PHY_PM][AP_NUM_PM_LNS], int traffic[AP_NUM_PM_MOD] ) 218 { 219 int idx1, idx2; 220 tdm_mod_t *_tdm_s; 221 222 _tdm_s = TDM_ALLOC(sizeof(tdm_mod_t),"TDM shim allocation"); 223 if (!_tdm_s) { 224 return NULL; 225 } 226 227 _tdm_s->_chip_data.soc_pkg.speed=TDM_ALLOC(AP_NUM_EXT_PORTS*sizeof(int *), "port speed list"); 228 for (idx1=0; idx1<AP_NUM_EXT_PORTS; idx1++) { 229 _tdm_s->_chip_data.soc_pkg.speed[idx1] = speed[idx1]; 230 } 231 _tdm_s->_chip_data.soc_pkg.pmap_num_modules = AP_NUM_PHY_PM; 232 _tdm_s->_chip_data.soc_pkg.pmap_num_lanes = AP_NUM_PM_LNS; 233 _tdm_s->_chip_data.soc_pkg.pmap=(int **) TDM_ALLOC((_tdm_s->_chip_data.soc_pkg.pmap_num_modules)*sizeof(int *), "portmod_map_l1"); 234 for (idx1=0; idx1<(_tdm_s->_chip_data.soc_pkg.pmap_num_modules); idx1++) { 235 _tdm_s->_chip_data.soc_pkg.pmap[idx1]=(int *) TDM_ALLOC((_tdm_s->_chip_data.soc_pkg.pmap_num_lanes)*sizeof(int), "portmod_map_l2"); 236 TDM_MSET(_tdm_s->_chip_data.soc_pkg.pmap[idx1],(_tdm_s->_chip_data.soc_pkg.num_ext_ports),_tdm_s->_chip_data.soc_pkg.pmap_num_lanes); 237 } 238 for (idx1=0; idx1<AP_NUM_PHY_PM; idx1++) { 239 for (idx2=0; idx2<AP_NUM_PM_LNS; idx2++) { 240 _tdm_s->_chip_data.soc_pkg.pmap[idx1][idx2] = tsc[idx1][idx2]; 241 } 242 } 243 for (idx1=0; idx1<AP_NUM_PM_MOD; idx1++) { 244 _tdm_s->_chip_data.soc_pkg.soc_vars.ap.pm_encap_type[idx1] = traffic[idx1]; 245 } 246 247 _tdm_s->_core_data.vars_pkg.port = port; 248 return _tdm_s; 249 250 } 251 252 253 /** 254 @name: tdm_chip_ap_shim__check_ethernet 255 @param: 256 257 Upward abstraction layer between TDM.4 and TDM.5 API 258 */ 259 tdm_mod_t* 260 tdm_chip_ap_shim__check_ethernet_d( int port, enum port_speed_e speed[AP_NUM_EXT_PORTS], enum port_state_e state[AP_NUM_EXT_PORTS], int **tsc, int traffic[AP_NUM_PM_MOD] ) 261 { 262 int idx1, idx2; 263 tdm_mod_t *_tdm_s; 264 265 _tdm_s = TDM_ALLOC(sizeof(tdm_mod_t),"TDM shim allocation"); 266 if (!_tdm_s) { 267 return NULL; 268 } 269 270 _tdm_s->_chip_data.soc_pkg.speed=TDM_ALLOC(AP_NUM_EXT_PORTS*sizeof(int *), "port speed list"); 271 _tdm_s->_chip_data.soc_pkg.state=TDM_ALLOC(AP_NUM_EXT_PORTS*sizeof(int *), "port state list"); 272 for (idx1=0; idx1<AP_NUM_EXT_PORTS; idx1++) { 273 _tdm_s->_chip_data.soc_pkg.speed[idx1] = speed[idx1]; 274 _tdm_s->_chip_data.soc_pkg.state[idx1] = state[idx1]; 275 } 276 _tdm_s->_chip_data.soc_pkg.pmap_num_modules = AP_NUM_PHY_PM; 277 _tdm_s->_chip_data.soc_pkg.pmap_num_lanes = AP_NUM_PM_LNS; 278 _tdm_s->_chip_data.soc_pkg.pmap=(int **) TDM_ALLOC((_tdm_s->_chip_data.soc_pkg.pmap_num_modules)*sizeof(int *), "portmod_map_l1"); 279 for (idx1=0; idx1<(_tdm_s->_chip_data.soc_pkg.pmap_num_modules); idx1++) { 280 _tdm_s->_chip_data.soc_pkg.pmap[idx1]=(int *) TDM_ALLOC((_tdm_s->_chip_data.soc_pkg.pmap_num_lanes)*sizeof(int), "portmod_map_l2"); 281 TDM_MSET(_tdm_s->_chip_data.soc_pkg.pmap[idx1],(_tdm_s->_chip_data.soc_pkg.num_ext_ports),_tdm_s->_chip_data.soc_pkg.pmap_num_lanes); 282 } 283 284 for (idx1=0; idx1<AP_NUM_PHY_PM; idx1++) { 285 for (idx2=0; idx2<AP_NUM_PM_LNS; idx2++) { 286 _tdm_s->_chip_data.soc_pkg.pmap[idx1][idx2] = tsc[idx1][idx2]; 287 } 288 } 289 for (idx1=0; idx1<AP_NUM_PM_MOD; idx1++) { 290 _tdm_s->_chip_data.soc_pkg.soc_vars.ap.pm_encap_type[idx1] = traffic[idx1]; 291 } 292 293 _tdm_s->_core_data.vars_pkg.port = port; 294 return _tdm_s; 295 296 } 297 298 299 /** 300 @name: tdm_chip_ap_shim__core_vbs_scheduler_ovs 301 @param: 302 303 Passthru function for oversub scheduling request from TD2/TD2+ 304 */ 305 int 306 tdm_chip_ap_shim__core_vbs_scheduler_ovs( tdm_mod_t *_tdm ) 307 { 308 /* TD2/TD2+ doesn't use 25G and 50G */ 309 /*_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.z5=0; 310 _tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.z6=0;*/ 311 312 return tdm_core_vbs_scheduler_ovs(_tdm); 313 }