tdm_ap_proc.c (67333B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * $All Rights Reserved.$ 7 * 8 * TDM chip operations 9 */ 10 #ifdef _TDM_STANDALONE 11 #include <tdm_top.h> 12 #include <tdm_ap_vec.h> 13 #else 14 #include <soc/tdm/core/tdm_top.h> 15 #include <soc/tdm/apache/tdm_ap_vec.h> 16 #endif 17 18 int tdm_core_vec_load(unsigned short **map, int bw, int port_speed, int yy, int len, int num_ext_ports); 19 20 /** 21 @name: tdm_ap_ovs_spacer 22 @param: 23 24 Reconfigures oversub TDM calendar into Flexport compatibility mode 25 */ 26 void 27 tdm_ap_ovs_spacer(int *ovs_tdm_tbl, int *ovs_spacing) 28 { 29 int i, j, w=0, k=0, port=0; 30 int idx=0, size=AP_OS_LLS_GRP_LEN; 31 unsigned short mirror_tdm_tbl[2*AP_OS_LLS_GRP_LEN]; 32 33 for(j=0; j<(2*AP_OS_LLS_GRP_LEN); j++) { mirror_tdm_tbl[j] = AP_NUM_EXT_PORTS;} 34 35 do { 36 idx++; 37 } while(ovs_tdm_tbl[idx] != AP_NUM_EXT_PORTS); 38 size =idx; 39 40 for (i=0; i<size; i++) { 41 mirror_tdm_tbl[i] = ovs_tdm_tbl[i]; 42 mirror_tdm_tbl[i+size] = ovs_tdm_tbl[i]; 43 } 44 /* Populate PGW spacing table by calculating min spacing for each non-empty slots */ 45 for (j=0; j<size; j++) { 46 w=size+1; 47 if(ovs_tdm_tbl[j]!=AP_NUM_EXT_PORTS){ 48 port = ovs_tdm_tbl[j]; 49 for (i=j+1; i<2*size; i++){ 50 if (mirror_tdm_tbl[i]== port){ 51 w=i-j; 52 break; 53 } 54 } 55 ovs_spacing[j] = w; 56 } 57 } 58 /* Regulate spacing values with AP_OS_LLS_GRP_LEN */ 59 for (k=0; k<AP_OS_LLS_GRP_LEN; k++) { 60 if (ovs_spacing[k] == (size+1) || ovs_tdm_tbl[k] == AP_OVSB_TOKEN){ 61 ovs_spacing[k] = size; 62 } 63 } 64 65 } 66 67 /** 68 @name: tdm_ap_lls_scheduler 69 @param: 70 71 Populate a linked list for one quad by traversing ports lane by lane, and populate the PGW oversub calendar. 72 */ 73 int 74 tdm_ap_lls_scheduler(struct ap_ll_node *pgw_tdm, tdm_ap_chip_legacy_t *ap_chip, ap_pgw_pntrs_t *pntrs_pkg, ap_pgw_scheduler_vars_t *vars_pkg, int *pgw_tdm_tbl[AP_LR_LLS_LEN], int *ovs_tdm_tbl[AP_OS_LLS_GRP_LEN], int op_flags[3], int *ap_fb_num_ovs, int *ap_fb_num_lr) 75 { 76 int ll_nodes_appended=0, p, q, r, l1_tdm_len, max_tdm_len, pgw_tdm_idx_sub, xcount, sm_iter=0, wc_array[AP_NUM_PHY_PM][AP_NUM_PM_LNS], 77 num_lr=0, num_lr_1=0, num_lr_10=0, num_lr_12=0, num_lr_20=0, num_lr_25=0, num_lr_40=0, num_lr_50=0, num_lr_100=0, num_ovs=0, num_off=0; 78 79 for (p=0; p<AP_NUM_PHY_PM; p++) { 80 for (q=0; q<4; q++) { 81 wc_array[p][q]=AP_NUM_EXT_PORTS; 82 } 83 } 84 for (p=0; p<AP_NUM_PHY_PM; p++) { 85 memcpy(&(wc_array[p][0]), &((*ap_chip).pmap[p][0]), (4*sizeof(int))); 86 } 87 /* Evenly distribute slots within one TSC */ 88 for (p=0; p<AP_NUM_PHY_PM; p++) { 89 AP_TOKEN_CHECK(wc_array[p][0]){ 90 if ((*ap_chip).tdm_globals.speed[(wc_array[p][0])]<SPEED_100G && wc_array[p][0]!=AP_NUM_EXT_PORTS && wc_array[p][0]==wc_array[p][1] && wc_array[p][1]!=wc_array[p][2]) { 91 r=wc_array[p][2]; 92 wc_array[p][2]=wc_array[p][1]; 93 wc_array[p][1]=r; 94 } 95 else if ((*ap_chip).tdm_globals.speed[(wc_array[p][0])]<SPEED_100G && wc_array[p][2]!=AP_NUM_EXT_PORTS && wc_array[p][2]==wc_array[p][3] && wc_array[p][2]!=wc_array[p][1]) { 96 r=wc_array[p][1]; 97 wc_array[p][1]=wc_array[p][2]; 98 wc_array[p][2]=r; 99 } 100 } 101 } 102 /* Set max number of TSCs in current quad */ 103 switch((*ap_chip).tdm_globals.clk_freq) { 104 case 435: 105 pgw_tdm_idx_sub = 3; 106 if (((*vars_pkg).first_port == 0) && ((*vars_pkg).last_port == 36)) {max_tdm_len = 26;} 107 else {max_tdm_len = 24;} 108 break; 109 case 510: 110 if (((*vars_pkg).first_port == 0) && ((*vars_pkg).last_port == 36)) {pgw_tdm_idx_sub = 9;} 111 else {pgw_tdm_idx_sub = 8;} 112 max_tdm_len = 30; 113 break; 114 case 575: 115 pgw_tdm_idx_sub = 4; 116 max_tdm_len = 34; 117 break; 118 /* Added 795 to 798 clk for FB config*/ 119 case 793: 120 case 794: 121 case 795: 122 case 796: 123 case 797: 124 case 798: 125 pgw_tdm_idx_sub = 6; 126 max_tdm_len = 48; 127 break; 128 case 840: 129 pgw_tdm_idx_sub = 6; 130 max_tdm_len = 48; 131 break; 132 default: 133 pgw_tdm_idx_sub = 7; 134 max_tdm_len = 56; 135 break; 136 } 137 138 /* Calculate number of linerate/oversub/disabled ports */ 139 for (p = (*vars_pkg).first_port; p < (*vars_pkg).last_port; p++) { 140 /* linerate ports */ 141 if ( (*ap_chip).tdm_globals.port_rates_array[p] == PORT_STATE__LINERATE || 142 (*ap_chip).tdm_globals.port_rates_array[p] == PORT_STATE__LINERATE_HG){ 143 num_lr++; 144 switch ((*ap_chip).tdm_globals.speed[p+1]) { 145 case SPEED_1G: 146 case SPEED_2G: 147 case SPEED_2p5G: 148 num_lr_1++; 149 break; 150 case SPEED_10G: 151 case SPEED_10G_DUAL: 152 case SPEED_10G_XAUI: 153 num_lr_10++; 154 break; 155 case SPEED_20G: 156 num_lr_20++; 157 break; 158 case SPEED_25G: 159 num_lr_25++; 160 break; 161 case SPEED_40G: 162 num_lr_40++; 163 break; 164 case SPEED_50G: 165 num_lr_50++; 166 break; 167 case SPEED_100G: 168 num_lr_100++; 169 break; 170 default: 171 break; 172 } 173 } 174 /* oversub ports */ 175 else if ((*ap_chip).tdm_globals.port_rates_array[p] == PORT_STATE__OVERSUB || 176 (*ap_chip).tdm_globals.port_rates_array[p] == PORT_STATE__OVERSUB_HG){ 177 num_ovs++; 178 } 179 /* disabled ports */ 180 else if ((*ap_chip).tdm_globals.port_rates_array[p] == PORT_STATE__DISABLED || ( (p%4==0) && ((*ap_chip).tdm_globals.port_rates_array[p]==PORT_STATE__COMBINE) ) ) { 181 num_off++; 182 } 183 } 184 /* Check length of PGW linked list for current quad */ 185 l1_tdm_len = (num_lr_1+(num_lr_10*2)+(num_lr_12*3)+(num_lr_20*4)+(num_lr_25*5)+(num_lr_40*8)+(num_lr_50*10)+(num_lr_100*20)); 186 TDM_SML_BAR 187 if ( (l1_tdm_len>max_tdm_len) && (l1_tdm_len>64) ) { 188 TDM_ERROR0("Bandwidth overloaded\n"); 189 return 0; 190 } 191 TDM_PRINT1("Base oversubscription token pool is %0d\n", pgw_tdm_idx_sub); 192 TDM_SML_BAR 193 TDM_PRINT1("1G line rate ports in this quadrant: %0d\n", num_lr_1); 194 TDM_PRINT1("10G line rate ports in this quadrant: %0d\n", num_lr_10); 195 TDM_PRINT1("12G line rate ports in this quadrant: %0d\n", num_lr_12); 196 TDM_PRINT1("20G line rate ports in this quadrant: %0d\n", num_lr_20); 197 TDM_PRINT1("25G line rate ports in this quadrant: %0d\n", num_lr_25); 198 TDM_PRINT1("40G line rate ports in this quadrant: %0d\n", num_lr_40); 199 TDM_PRINT1("50G line rate ports in this quadrant: %0d\n", num_lr_50); 200 TDM_PRINT1("100G gestalt line rate ports in this quadrant: %0d\n", num_lr_100); 201 TDM_PRINT1("Oversubscribed ports in this quadrant: %0d\n", num_ovs); 202 TDM_PRINT1("Disabled subports in this quadrant: %0d\n", num_off); 203 TDM_PRINT2("COVERAGE FROM PHYSICAL PORTS %0d to %0d\n", (*vars_pkg).first_port, (*vars_pkg).last_port); 204 (*ap_fb_num_ovs) = num_ovs; 205 (*ap_fb_num_lr) = num_lr_40; 206 207 /* CASE 1: line-rate bandwidth overflow */ 208 if ((l1_tdm_len>max_tdm_len) && (num_ovs == 0)) { 209 TDM_PRINT0("Applying obligate oversubscription correction\n"); 210 for (xcount=0; xcount<max_tdm_len; xcount++) { 211 while (((*pntrs_pkg).cur_idx < (*vars_pkg).cur_idx_max) && 212 ((wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport] == AP_NUM_EXT_PORTS) || 213 (wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport] == AP_MGMT_TOKEN) ) ){ 214 ((*pntrs_pkg).cur_idx)++; 215 } 216 if ((*pntrs_pkg).cur_idx >= (*vars_pkg).cur_idx_max) { 217 break; 218 } 219 if ( tdm_ap_ll_len(pgw_tdm) < max_tdm_len ) { 220 tdm_ap_ll_append(pgw_tdm,AP_OVSB_TOKEN,&ll_nodes_appended); 221 TDM_PRINT2("PGW %0d: PGW TDM calendar element #0%0d, content is OVSB token\n",(((*vars_pkg).cur_idx_max/9)-1),(((*vars_pkg).subport*pgw_tdm_idx_sub)+ll_nodes_appended)); 222 } 223 (*ovs_tdm_tbl)[(*pntrs_pkg).ovs_tdm_idx] = wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport]; 224 TDM_PRINT3("PGW %0d: Oversub subcalendar index %0d is %0d\n",(((*vars_pkg).cur_idx_max/9)-1),(*pntrs_pkg).ovs_tdm_idx,(*ovs_tdm_tbl)[(*pntrs_pkg).ovs_tdm_idx]); 225 ((*pntrs_pkg).ovs_tdm_idx)++; 226 ((*pntrs_pkg).cur_idx)++; 227 } 228 TDM_WARN3("PGW %0d: PGW TDM calendar, Line-rate bandwidth overflow (%d,%d). \n", (((*vars_pkg).cur_idx_max/9)-1), l1_tdm_len, max_tdm_len); 229 } 230 /* CASE 2: line-rate bandwidth is within limit */ 231 else { 232 while ( (sm_iter++) < AP_NUM_EXT_PORTS) { 233 /* Find next active port (either linerate or oversub) */ 234 while ( ((*pntrs_pkg).cur_idx < (*vars_pkg).cur_idx_max) && 235 ((wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport] == AP_MGMT_TOKEN) || 236 (wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport] == AP_NUM_EXT_PORTS) || 237 ((*ap_chip).tdm_globals.port_rates_array[(wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport])-1]==PORT_STATE__MANAGEMENT) || 238 (((*ap_chip).tdm_globals.speed[wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport]] < SPEED_10G ) && op_flags[1]==1)) ){ 239 ((*pntrs_pkg).cur_idx)++; 240 } 241 if ( ( ((*pntrs_pkg).cur_idx)>=((*vars_pkg).cur_idx_max)) ) { 242 break; 243 } 244 /* Print selected active port info */ 245 TDM_SML_BAR 246 TDM_PRINT2("Polling current index %0d subport %0d: [",(*pntrs_pkg).cur_idx,(*vars_pkg).subport); 247 for (p=0; p<4; p++) { 248 if (p==(*vars_pkg).subport) { 249 TDM_PRINT1(" >%0d< ",wc_array[(*pntrs_pkg).cur_idx][p]); 250 } 251 else { 252 TDM_PRINT1(" %0d ",wc_array[(*pntrs_pkg).cur_idx][p]); 253 } 254 } 255 TDM_PRINT0("]\n"); 256 TDM_PRINT3("[ Port=%0d, Speed=%0dG, State=%0d ]\n", wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport],(*ap_chip).tdm_globals.speed[wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport]]/1000,(*ap_chip).tdm_globals.port_rates_array[(wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport])-1]); 257 /* Allocate one slot for selected port, either in linked-list or in stack */ 258 switch((*ap_chip).tdm_globals.port_rates_array[(wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport])-1]) { 259 case PORT_STATE__DISABLED: 260 TDM_PRINT0("The current port is DISABLED\n"); 261 if (num_lr > 0 && num_ovs > 0) { 262 tdm_ap_ll_append(pgw_tdm,AP_OVSB_TOKEN,&ll_nodes_appended); 263 TDM_PRINT3("PGW %0d: PGW TDM calendar element #0%0d, content is %0d\n",(((*vars_pkg).cur_idx_max/9)-1),(((*vars_pkg).subport*pgw_tdm_idx_sub)+ll_nodes_appended),tdm_ap_ll_get(pgw_tdm,(tdm_ap_ll_len(pgw_tdm)-1))); 264 } 265 ((*pntrs_pkg).cur_idx)++; 266 break; 267 case PORT_STATE__LINERATE: 268 case PORT_STATE__LINERATE_HG: 269 TDM_PRINT0("The current port is LINE RATE\n"); 270 if (num_ovs==0) { 271 while ( (((*pntrs_pkg).tdm_stk_idx)>0) && (tdm_ap_ll_get(pgw_tdm,(tdm_ap_ll_len(pgw_tdm)-1))!=(*vars_pkg).swap_array[(*pntrs_pkg).tdm_stk_idx]) ) { 272 tdm_ap_ll_append(pgw_tdm,(*vars_pkg).swap_array[(*pntrs_pkg).tdm_stk_idx],&ll_nodes_appended); 273 TDM_PRINT4("PGW %0d: Dequeue from stack, pointer index %0d, to pgw tdm tbl element #0%0d, content is %0d\n",(((*vars_pkg).cur_idx_max/9)-1),(*pntrs_pkg).tdm_stk_idx,(((*vars_pkg).subport*pgw_tdm_idx_sub)+ll_nodes_appended),(*vars_pkg).swap_array[(*pntrs_pkg).tdm_stk_idx]); 274 ((*pntrs_pkg).tdm_stk_idx)--; 275 TDM_PRINT1("Swap stack pointer at %0d\n",(*pntrs_pkg).tdm_stk_idx); 276 } 277 if ( (wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport]!=tdm_ap_ll_get(pgw_tdm,(tdm_ap_ll_len(pgw_tdm)-1)) ) || (ll_nodes_appended==0) ) { 278 /*tdm_ap_ll_append(pgw_tdm,wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport],&ll_nodes_appended);*/ 279 if( (*ap_chip).tdm_globals.speed[wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport]] == SPEED_25G ) { 280 if(((wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport]>=1 && wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport]<=28) || 281 (wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport]>=37 && wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport]<=64)) && 282 ( (*ap_chip).tdm_globals.speed[wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport]] == SPEED_25G ) ) { 283 if(op_flags[1] ==0){ 284 tdm_ap_ll_append(pgw_tdm,wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport],&ll_nodes_appended); TDM_PRINT0("DPRT1\n"); 285 if((*vars_pkg).subport==3) { tdm_ap_ll_append(pgw_tdm,wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport],&ll_nodes_appended); TDM_PRINT0("DPRT\n");} 286 } 287 } 288 if( ((wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport]>=29 && wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport]<=36) || 289 (wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport]>=65 && wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport]<=72)) ) { 290 tdm_ap_ll_append(pgw_tdm,wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport],&ll_nodes_appended); 291 } 292 } else { 293 tdm_ap_ll_append(pgw_tdm,wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport],&ll_nodes_appended); 294 } 295 if(((wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport]>=29 && wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport]<=36) || 296 (wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport]>=65 && wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport]<=72)) && 297 ((*ap_chip).tdm_globals.speed[wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport]] == SPEED_40G || 298 (*ap_chip).tdm_globals.speed[wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport]] == SPEED_20G) ) { 299 tdm_ap_ll_append(pgw_tdm,wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport],&ll_nodes_appended); 300 } 301 /*Falcon core*/ 302 if(((wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport]>=29 && wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport]<=36) || 303 (wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport]>=65 && wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport]<=72)) && 304 ((*ap_chip).tdm_globals.speed[wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport]] == SPEED_100G || 305 (*ap_chip).tdm_globals.speed[wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport]] == SPEED_50G || 306 (*ap_chip).tdm_globals.speed[wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport]] == SPEED_25G) ) { 307 tdm_ap_ll_append(pgw_tdm,wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport],&ll_nodes_appended); 308 if(op_flags[1]==0) tdm_ap_ll_append(pgw_tdm,wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport],&ll_nodes_appended); 309 } 310 311 TDM_PRINT3("PGW %0d: PGW TDM calendar element #0%0d, content is %0d\n",(((*vars_pkg).cur_idx_max/9)-1),(((*vars_pkg).subport*pgw_tdm_idx_sub)+ll_nodes_appended),tdm_ap_ll_get(pgw_tdm,(tdm_ap_ll_len(pgw_tdm)-1))); 312 ((*pntrs_pkg).cur_idx)++; 313 } 314 else { 315 ((*pntrs_pkg).tdm_stk_idx)++; 316 (*vars_pkg).swap_array[(*pntrs_pkg).tdm_stk_idx] = wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport]; 317 TDM_PRINT3("PGW %0d: pushed port %0d at stack index %0d\n",(((*vars_pkg).cur_idx_max/9)-1),wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport],(*pntrs_pkg).tdm_stk_idx); 318 ((*pntrs_pkg).cur_idx)++; 319 } 320 } 321 else { 322 if ( (((*pntrs_pkg).tdm_stk_idx)>0) && 323 (tdm_ap_ll_get(pgw_tdm,(tdm_ap_ll_len(pgw_tdm)-2))!=(*vars_pkg).swap_array[(*pntrs_pkg).tdm_stk_idx]) && 324 (tdm_ap_ll_get(pgw_tdm,(tdm_ap_ll_len(pgw_tdm)-1))==AP_OVSB_TOKEN) ) { 325 tdm_ap_ll_append(pgw_tdm,(*vars_pkg).swap_array[(*pntrs_pkg).tdm_stk_idx],&ll_nodes_appended); 326 TDM_PRINT4("PGW %0d: Dequeue from stack, pointer index %0d, to pgw tdm tbl element #0%0d, content is %0d\n",(((*vars_pkg).cur_idx_max/9)-1),(*pntrs_pkg).tdm_stk_idx,(((*vars_pkg).subport*pgw_tdm_idx_sub)+ll_nodes_appended),(*vars_pkg).swap_array[(*pntrs_pkg).tdm_stk_idx]); 327 ((*pntrs_pkg).tdm_stk_idx)--; 328 TDM_PRINT1("Swap stack pointer at %0d\n",(*pntrs_pkg).tdm_stk_idx); 329 } 330 while ( (((*pntrs_pkg).tdm_stk_idx)>0) && 331 (tdm_ap_ll_get(pgw_tdm,(tdm_ap_ll_len(pgw_tdm)-1))!=(*vars_pkg).swap_array[(*pntrs_pkg).tdm_stk_idx]) && 332 (tdm_ap_ll_get(pgw_tdm,(tdm_ap_ll_len(pgw_tdm)-1))!=AP_OVSB_TOKEN) ) { 333 tdm_ap_ll_append(pgw_tdm,(*vars_pkg).swap_array[(*pntrs_pkg).tdm_stk_idx],&ll_nodes_appended); 334 TDM_PRINT4("PGW %0d: Dequeue from stack, pointer index %0d, to pgw tdm tbl element #0%0d, content is %0d\n",(((*vars_pkg).cur_idx_max/9)-1),(*pntrs_pkg).tdm_stk_idx,(((*vars_pkg).subport*pgw_tdm_idx_sub)+ll_nodes_appended),(*vars_pkg).swap_array[(*pntrs_pkg).tdm_stk_idx]); 335 ((*pntrs_pkg).tdm_stk_idx)--; 336 TDM_PRINT1("Swap stack pointer at %0d\n",(*pntrs_pkg).tdm_stk_idx); 337 } 338 if ( ((wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport]!=tdm_ap_ll_get(pgw_tdm,(tdm_ap_ll_len(pgw_tdm)-1))) || (ll_nodes_appended==0)) ) { 339 if( (*ap_chip).tdm_globals.speed[wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport]] == SPEED_25G ) { 340 if(((wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport]>=1 && wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport]<=28) || 341 (wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport]>=37 && wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport]<=64)) && 342 ( (*ap_chip).tdm_globals.speed[wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport]] == SPEED_25G ) ) { 343 if(op_flags[1] ==0){ 344 tdm_ap_ll_append(pgw_tdm,wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport],&ll_nodes_appended); TDM_PRINT0("DPRT1\n"); 345 if((*vars_pkg).subport==3) { tdm_ap_ll_append(pgw_tdm,wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport],&ll_nodes_appended); TDM_PRINT0("DPRT\n");} 346 } 347 } 348 if( ((wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport]>=29 && wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport]<=36) || 349 (wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport]>=65 && wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport]<=72)) ) { 350 tdm_ap_ll_append(pgw_tdm,wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport],&ll_nodes_appended); 351 } 352 } else { 353 tdm_ap_ll_append(pgw_tdm,wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport],&ll_nodes_appended); 354 } 355 356 if(((wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport]>=29 && wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport]<=35) || 357 (wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport]>=65 && wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport]<=71)) && 358 ((*ap_chip).tdm_globals.speed[wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport]] == SPEED_40G || 359 (*ap_chip).tdm_globals.speed[wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport]] == SPEED_20G) ) { 360 tdm_ap_ll_append(pgw_tdm,wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport],&ll_nodes_appended); 361 } 362 /*Falcon core*/ 363 if( ((wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport]>=29 && wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport]<=36) || 364 (wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport]>=65 && wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport]<=72)) && 365 ((*ap_chip).tdm_globals.speed[wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport]] == SPEED_100G || 366 (*ap_chip).tdm_globals.speed[wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport]] == SPEED_50G || 367 (*ap_chip).tdm_globals.speed[wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport]] == SPEED_25G) ) { 368 tdm_ap_ll_append(pgw_tdm,wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport],&ll_nodes_appended); 369 if(op_flags[1]==0) tdm_ap_ll_append(pgw_tdm,wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport],&ll_nodes_appended); 370 } 371 372 TDM_PRINT3("PGW %0d: PGW TDM calendar element #0%0d, content is %0d\n",(((*vars_pkg).cur_idx_max/9)-1),(((*vars_pkg).subport*pgw_tdm_idx_sub)+ll_nodes_appended),tdm_ap_ll_get(pgw_tdm,(tdm_ap_ll_len(pgw_tdm)-1))); 373 ((*pntrs_pkg).cur_idx)++; 374 } 375 else { 376 ((*pntrs_pkg).tdm_stk_idx)++; 377 (*vars_pkg).swap_array[(*pntrs_pkg).tdm_stk_idx] = wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport]; 378 TDM_PRINT3("PGW %0d: pushed port %0d at stack index %0d\n",(((*vars_pkg).cur_idx_max/9)-1),wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport],(*pntrs_pkg).tdm_stk_idx); 379 ((*pntrs_pkg).cur_idx)++; 380 } 381 } 382 break; 383 case PORT_STATE__OVERSUB: 384 case PORT_STATE__OVERSUB_HG: 385 TDM_PRINT0("The current port is OVERSUBSCRIBED\n"); 386 TDM_PRINT1("The oversub subcalendar index is %0d\n", (*pntrs_pkg).ovs_tdm_idx); 387 if(op_flags[1]==0) { 388 /*Apache 25.455G Eagle support (4x6.5625)*/ 389 if( (*ap_chip).tdm_globals.speed[wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport]] == SPEED_25G ) { 390 if(((wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport]>=1 && wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport]<=28) || 391 (wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport]>=37 && wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport]<=64)) && 392 ( (*ap_chip).tdm_globals.speed[wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport]] == SPEED_25G ) ) { 393 if( (*vars_pkg).subport <3) { 394 (*ovs_tdm_tbl)[(*pntrs_pkg).ovs_tdm_idx] = wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport]; 395 ((*pntrs_pkg).ovs_tdm_idx)++; 396 } 397 } 398 if( ((wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport]>=29 && wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport]<=36) || 399 (wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport]>=65 && wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport]<=72)) ) { 400 (*ovs_tdm_tbl)[(*pntrs_pkg).ovs_tdm_idx] = wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport]; 401 ((*pntrs_pkg).ovs_tdm_idx)++; 402 } 403 } else { 404 (*ovs_tdm_tbl)[(*pntrs_pkg).ovs_tdm_idx] = wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport]; 405 ((*pntrs_pkg).ovs_tdm_idx)++; 406 } 407 408 if(((wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport]>=29 && wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport]<=35) || 409 (wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport]>=65 && wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport]<=71)) && 410 ((*ap_chip).tdm_globals.speed[wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport]] == SPEED_40G || 411 (*ap_chip).tdm_globals.speed[wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport]] == SPEED_20G) ) { 412 (*ovs_tdm_tbl)[(*pntrs_pkg).ovs_tdm_idx] = wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport]; 413 ((*pntrs_pkg).ovs_tdm_idx)++; 414 } 415 416 if( ((wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport]>=29 && wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport]<=36) || 417 (wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport]>=65 && wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport]<=72)) && 418 ((*ap_chip).tdm_globals.speed[wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport]] == SPEED_100G || 419 (*ap_chip).tdm_globals.speed[wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport]] == SPEED_50G || 420 (*ap_chip).tdm_globals.speed[wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport]] == SPEED_25G) ) { 421 (*ovs_tdm_tbl)[(*pntrs_pkg).ovs_tdm_idx] = wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport]; 422 ((*pntrs_pkg).ovs_tdm_idx)++; 423 424 if((*ap_chip).tdm_globals.clk_freq!=840) { 425 if((*ap_chip).tdm_globals.speed[wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport]] == SPEED_100G || 426 (*ap_chip).tdm_globals.speed[wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport]] == SPEED_50G) { 427 if((*vars_pkg).subport <2) { 428 (*ovs_tdm_tbl)[(*pntrs_pkg).ovs_tdm_idx] = wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport]; 429 ((*pntrs_pkg).ovs_tdm_idx)++; 430 } 431 } 432 else if((*ap_chip).tdm_globals.speed[wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport]] == SPEED_25G) { 433 (*ovs_tdm_tbl)[(*pntrs_pkg).ovs_tdm_idx] = wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport]; 434 ((*pntrs_pkg).ovs_tdm_idx)++; 435 } 436 } 437 } 438 } 439 if (((*vars_pkg).subport!=0) && 440 ((*ap_chip).tdm_globals.port_rates_array[(wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport-1])-1]==PORT_STATE__LINERATE || 441 (*ap_chip).tdm_globals.port_rates_array[(wc_array[(*pntrs_pkg).cur_idx][(*vars_pkg).subport-1])-1]==PORT_STATE__LINERATE_HG) ){ 442 tdm_ap_ll_append(pgw_tdm,AP_OVSB_TOKEN,&ll_nodes_appended); 443 TDM_PRINT3("PGW %0d: PGW TDM calendar element #0%0d, content is %0d\n",(((*vars_pkg).cur_idx_max/9)-1),(((*vars_pkg).subport*pgw_tdm_idx_sub)+ll_nodes_appended),tdm_ap_ll_get(pgw_tdm,(tdm_ap_ll_len(pgw_tdm)-1))); 444 } 445 ((*pntrs_pkg).cur_idx)++; 446 break; 447 default: 448 break; 449 } 450 } 451 /* Dequeue linerate slot from stack */ 452 while ((*pntrs_pkg).tdm_stk_idx>0) { 453 tdm_ap_ll_append(pgw_tdm,(*vars_pkg).swap_array[(*pntrs_pkg).tdm_stk_idx], &ll_nodes_appended); 454 TDM_PRINT4("PGW %0d: Dequeue from stack, pointer index %0d, to pgw tdm tbl element #0%0d, content is %0d\n",(((*vars_pkg).cur_idx_max/9)-1),(*pntrs_pkg).tdm_stk_idx,(((*vars_pkg).subport*pgw_tdm_idx_sub)+ll_nodes_appended),(*vars_pkg).swap_array[(*pntrs_pkg).tdm_stk_idx]); 455 ((*pntrs_pkg).tdm_stk_idx)--; 456 TDM_PRINT1("Swap stack pointer at %0d\n",(*pntrs_pkg).tdm_stk_idx); 457 } 458 /* Extend linked-list with oversub token */ 459 if ( (ll_nodes_appended>0) || 460 (ll_nodes_appended==0 && ((*pntrs_pkg).ovs_tdm_idx)>0) ){ 461 while ( ll_nodes_appended<pgw_tdm_idx_sub ) { 462 TDM_SML_BAR 463 TDM_PRINT1("Extending current cadence at index %0d\n",tdm_ap_ll_len(pgw_tdm)); 464 tdm_ap_ll_append(pgw_tdm,AP_OVSB_TOKEN,&ll_nodes_appended); 465 TDM_PRINT3("PGW %0d: PGW TDM calendar element #0%0d, content is %0d\n",(((*vars_pkg).cur_idx_max/9)-1),(((*vars_pkg).subport*pgw_tdm_idx_sub)+ll_nodes_appended),tdm_ap_ll_get(pgw_tdm,(tdm_ap_ll_len(pgw_tdm)-1))); 466 } 467 } 468 if(op_flags[2] ==1) { 469 while ( tdm_ap_ll_len(pgw_tdm) < max_tdm_len ) { 470 tdm_ap_ll_append(pgw_tdm,AP_OVSB_TOKEN,&ll_nodes_appended); 471 TDM_PRINT2("PGW %0d: PGW TDM calendar element #0%0d, content is OVSB token\n",(((*vars_pkg).cur_idx_max/9)-1),(((*vars_pkg).subport*pgw_tdm_idx_sub)+ll_nodes_appended)); 472 } 473 } 474 } 475 476 TDM_PRINT0("\n\tCalendar dump:\n"); 477 tdm_ap_ll_print(pgw_tdm); 478 TDM_SML_BAR 479 TDM_SML_BAR 480 TDM_PRINT1("Current cycle: The PGW TDM calendar index is %0d\n",tdm_ap_ll_len(pgw_tdm)); 481 TDM_PRINT1("Current cycle: %0d ll_nodes appended to PGW TDM linked list\n",ll_nodes_appended); 482 TDM_PRINT2("Current cycle: The current index is %0d at subport %0d\n",(*pntrs_pkg).cur_idx,(*vars_pkg).subport); 483 TDM_SML_BAR 484 TDM_SML_BAR 485 486 return ll_nodes_appended; 487 } 488 489 490 /** 491 OVSB TBL RECONFIG WHEN CLPORTS in 100G 492 */ 493 void tdm_ap_reconfig_ovs_tbl(int *ovs_tdm_tbl) 494 { 495 496 int i,j,k,idx,size=AP_OS_LLS_GRP_LEN; 497 int elmnt_repeating,elmnt_repeating_cnt=0, num_elements_repeating=0, rpt_slot0, rpt_slot1, rpt_slot2; 498 int uniq_elements_cnt=0, sum_of_spacing=0, current_spacing=0; 499 int temp, spacing_idx=0, timeout=16, temp_port=130; 500 501 int spacing_tbl[AP_OS_LLS_GRP_LEN],elmnt_repeating_tbl[AP_OS_LLS_GRP_LEN],uniq_elements_tbl[AP_OS_LLS_GRP_LEN]; 502 503 504 for(j=0; j<AP_OS_LLS_GRP_LEN; j++) { spacing_tbl[j] = 0;} 505 506 for(i =0; i<AP_OS_LLS_GRP_LEN; i++) { 507 if(ovs_tdm_tbl[i] == AP_NUM_EXT_PORTS) break; 508 } 509 size = i; 510 511 for(i=0; i<size; i++) { 512 AP_TOKEN_CHECK(ovs_tdm_tbl[i]) { 513 if(ovs_tdm_tbl[i]==ovs_tdm_tbl[i+1]) { 514 elmnt_repeating_tbl[num_elements_repeating++] = ovs_tdm_tbl[i]; 515 elmnt_repeating = ovs_tdm_tbl[i]; 516 for(j=0; j<size; j++) { 517 if(ovs_tdm_tbl[j] == elmnt_repeating_tbl[num_elements_repeating-1]) { 518 for(k=j-1; k>=0; k--){ 519 ovs_tdm_tbl[k+1] = ovs_tdm_tbl[k]; 520 } 521 elmnt_repeating_cnt++; 522 ovs_tdm_tbl[0] = elmnt_repeating; 523 } 524 } 525 i = elmnt_repeating_cnt; 526 } 527 } 528 } 529 530 /* move all ovsb tokens to end */ 531 while((--timeout)>0) { 532 for (i=0; i<(size-1); i++) { 533 if (ovs_tdm_tbl[i]==AP_OVSB_TOKEN && ovs_tdm_tbl[i+1]!=AP_OVSB_TOKEN) { 534 temp_port=ovs_tdm_tbl[i+1]; 535 ovs_tdm_tbl[i+1]=ovs_tdm_tbl[i]; 536 ovs_tdm_tbl[i]=temp_port; 537 } 538 } 539 } 540 541 for(i=elmnt_repeating_cnt; i<size; i++) { 542 AP_OVS_TOKEN_CHECK(ovs_tdm_tbl[i]) { 543 uniq_elements_tbl[uniq_elements_cnt++] = ovs_tdm_tbl[i]; 544 } 545 } 546 547 /*if no unique elements*/ 548 if(uniq_elements_cnt ==0 || uniq_elements_tbl[0] ==AP_OVSB_TOKEN) { 549 if(num_elements_repeating == 3) { 550 rpt_slot0=ovs_tdm_tbl[0]; rpt_slot1=ovs_tdm_tbl[10]; rpt_slot2=ovs_tdm_tbl[20]; 551 for(i=0; i<(size-4); i=i+3) { 552 ovs_tdm_tbl[i] = rpt_slot0; 553 ovs_tdm_tbl[i+1] = rpt_slot1; 554 ovs_tdm_tbl[i+2] = rpt_slot2; 555 } 556 } 557 else if (num_elements_repeating ==2) { 558 rpt_slot0=ovs_tdm_tbl[0]; rpt_slot1=ovs_tdm_tbl[10]; 559 for(i=0; i<(size-4); i++) { 560 if(i%2==0) ovs_tdm_tbl[i] = rpt_slot0; 561 else ovs_tdm_tbl[i] = rpt_slot1; 562 } 563 } 564 } 565 else if (elmnt_repeating_cnt!=0) { 566 do { 567 for(i=0; i<elmnt_repeating_cnt/num_elements_repeating; i++) { 568 spacing_tbl[i]++; 569 sum_of_spacing++; 570 if(sum_of_spacing == uniq_elements_cnt) break; 571 } 572 } while (sum_of_spacing < uniq_elements_cnt); 573 /* make the spacing table symmetric*/ 574 do { 575 spacing_idx++; 576 } while(spacing_tbl[spacing_idx] != 0); 577 578 for(i=0; i<spacing_idx; i++) { 579 temp= spacing_tbl[spacing_idx-1]; 580 for(k=spacing_idx-1; k>i; k--) { spacing_tbl[k] = spacing_tbl[k-1];} 581 spacing_tbl[i] = temp; 582 i=i+1; 583 } 584 585 /* put the repeating elements at start of tbl*/ 586 for(k=0, j=0; k<num_elements_repeating; k++) { 587 ovs_tdm_tbl[j++] = elmnt_repeating_tbl[k]; 588 } 589 590 for(i=0, current_spacing=0, idx=0 ; i<uniq_elements_cnt; ) { 591 if(current_spacing==spacing_tbl[idx]) { 592 current_spacing = 0; 593 idx++; 594 for(k=0; k<num_elements_repeating; k++) { 595 ovs_tdm_tbl[j++] = elmnt_repeating_tbl[k]; 596 } 597 } 598 else { ovs_tdm_tbl[j++]=uniq_elements_tbl[i]; current_spacing++; i++; } 599 } 600 } 601 602 603 } 604 605 /** 606 */ 607 void tdm_ap_reconfig_ovs_8x25(int *ovs_tdm_tbl, int port1, int port2) 608 { 609 610 int i, j, idx=0, size=AP_OS_LLS_GRP_LEN; 611 612 do { 613 idx++; 614 } while(ovs_tdm_tbl[idx] != AP_NUM_EXT_PORTS); 615 616 ovs_tdm_tbl[idx] = port1; 617 ovs_tdm_tbl[idx+1] = port1; 618 ovs_tdm_tbl[idx+2] = port2; 619 ovs_tdm_tbl[idx+3] = port2; 620 621 for(i=0; i<AP_OS_LLS_GRP_LEN; i++) { 622 if(ovs_tdm_tbl[i] == AP_NUM_EXT_PORTS) break; 623 } 624 size = i; 625 626 for(i=0;i<size;i++) { 627 for(j=0;j<4;j++) { 628 if(ovs_tdm_tbl[i]==(port1+j)) { 629 ovs_tdm_tbl[i] = port1; 630 } 631 if(ovs_tdm_tbl[i]==(port2+j)) { 632 ovs_tdm_tbl[i] = port2; 633 } 634 } 635 } 636 } 637 638 /** 639 */ 640 void tdm_ap_append_ovs_8x25(int *ovs_tdm_tbl, int port1, int port2, int cxx_port, enum port_speed_e cxx_speed ) 641 { 642 643 int i, cnt=0, cnt1=0, cnt2=0; 644 int token1=port1, token2=port2; 645 646 if(cxx_speed == SPEED_100G) { 647 for (i=0; i<AP_OS_LLS_GRP_LEN; i++) { 648 if( ovs_tdm_tbl[i]>=cxx_port && ovs_tdm_tbl[i] <(cxx_port+10) ) { 649 ovs_tdm_tbl[i] = cxx_port; 650 if((cnt2++)==9) break; 651 } 652 } 653 for (i=0; i<AP_OS_LLS_GRP_LEN; i++) { 654 if( ovs_tdm_tbl[i]>cxx_port && ovs_tdm_tbl[i] <(cxx_port+10) ) { 655 ovs_tdm_tbl[i] = (ovs_tdm_tbl[i] % 2)? port2 : port1; 656 } 657 } 658 } 659 for (i=0; i<AP_OS_LLS_GRP_LEN; i++) { 660 if(ovs_tdm_tbl[i]== port1) { 661 ovs_tdm_tbl[i] = token1++; 662 if((cnt++) ==3) { 663 cnt =0; 664 token1=port1; 665 } 666 } 667 if(ovs_tdm_tbl[i]== port2) { 668 ovs_tdm_tbl[i] = token2++; 669 if((cnt1++) ==3) { 670 cnt1 =0; 671 token2=port2; 672 } 673 } 674 } 675 676 } 677 /* 678 679 680 */ 681 682 void tdm_ap_clport_ovs_scheduler(int *ovs_tdm_tbl, int port[2], enum port_speed_e speed[2], int cxx_port, enum port_speed_e cxx_speed, int clk ) 683 { 684 685 int i, j, idx=0, cnt=0, size=AP_OS_LLS_GRP_LEN; 686 int token = cxx_port; 687 688 do { 689 idx++; 690 } while(ovs_tdm_tbl[idx] != AP_NUM_EXT_PORTS); 691 692 /*append additional slots for ovs */ 693 if(clk!=840) { 694 for(i=0; i<2; i++) { 695 if(speed[i] == SPEED_100G || speed[i] == SPEED_50G) { 696 ovs_tdm_tbl[idx++] = AP_OVSB_TOKEN; 697 ovs_tdm_tbl[idx++] = AP_OVSB_TOKEN; 698 } 699 } 700 } 701 for(i=0; i<AP_OS_LLS_GRP_LEN; i++) { 702 if(ovs_tdm_tbl[i] == AP_NUM_EXT_PORTS) break; 703 } 704 size = i; 705 706 if ((speed[0] == SPEED_25G) && (speed[1]== SPEED_25G)) { 707 for(i=0;i<size;i++) { 708 for(j=0;j<4;j++) { 709 if(ovs_tdm_tbl[i]==(port[0]+j)) { 710 ovs_tdm_tbl[i] = port[0]; 711 } 712 if(ovs_tdm_tbl[i]==(port[1]+j)) { 713 ovs_tdm_tbl[i] = port[1]; 714 } 715 } 716 } 717 /* when all 3 cl ports are not in same speed */ 718 if(cxx_speed == SPEED_100G) { 719 for(i=0;i<size;i++) { 720 if(ovs_tdm_tbl[i]==cxx_port) { 721 ovs_tdm_tbl[i] = token++; 722 } 723 } 724 } 725 } 726 else if(speed[0] == SPEED_25G) { 727 for(i=0;i<size;i++) { 728 for(j=0;j<4;j++) { 729 if(ovs_tdm_tbl[i]==(port[0]+j)) { 730 ovs_tdm_tbl[i] = port[0]; 731 } 732 } 733 } 734 tdm_ap_scheduler_ovs_4x25(ovs_tdm_tbl,port[0]); /* first schedule 4x25 alone*/ 735 } 736 else if(speed[1] == SPEED_25G) { 737 for(i=0;i<size;i++) { 738 for(j=0;j<4;j++) { 739 if(ovs_tdm_tbl[i]==(port[1]+j)) { 740 ovs_tdm_tbl[i] = port[1]; 741 } 742 } 743 } 744 tdm_ap_scheduler_ovs_4x25(ovs_tdm_tbl,port[1]); 745 } 746 /*make 2x50GE as 1x100GE and the replace after scheduling*/ 747 if (speed[0] == SPEED_50G) { 748 for (i=0; i<AP_OS_LLS_GRP_LEN; i++) { 749 if(ovs_tdm_tbl[i]== port[0]+2) { 750 ovs_tdm_tbl[i] = port[0]; 751 } 752 } 753 } 754 if (speed[1] == SPEED_50G) { 755 for (i=0; i<AP_OS_LLS_GRP_LEN; i++) { 756 if(ovs_tdm_tbl[i]== port[1]+2) { 757 ovs_tdm_tbl[i] = port[1]; 758 } 759 } 760 } 761 762 /* main spacing logic */ 763 tdm_ap_reconfig_ovs_tbl(ovs_tdm_tbl); 764 765 if (speed[0] == SPEED_50G) { 766 for (i=0; i<AP_OS_LLS_GRP_LEN; i++) { 767 if(ovs_tdm_tbl[i]== port[0]) { 768 if ((cnt++)%2==0) { ovs_tdm_tbl[i] = port[0] ; } 769 else { ovs_tdm_tbl[i] = (port[0]+2); } 770 } 771 } 772 } 773 if (speed[1] == SPEED_50G) { 774 for (i=0; i<AP_OS_LLS_GRP_LEN; i++) { 775 if(ovs_tdm_tbl[i]== port[1]) { 776 if ((cnt++)%2==0) { ovs_tdm_tbl[i] = port[1] ; } 777 else { ovs_tdm_tbl[i] = (port[1]+2); } 778 } 779 } 780 } 781 if ((speed[0] == SPEED_25G) && (speed[1]== SPEED_25G)) { tdm_ap_append_ovs_8x25(ovs_tdm_tbl,port[0],port[1],cxx_port,cxx_speed);} 782 783 784 } 785 786 787 void tdm_ap_scheduler_ovs_4x25(int *ovs_tdm_tbl, int port) 788 { 789 790 int i, j, k,cnt=0,div=0, cnt1=0, size=AP_OS_LLS_GRP_LEN; 791 int uniq_elements_tbl[AP_OS_LLS_GRP_LEN]; 792 int token=port; 793 794 for(j=0; j<AP_OS_LLS_GRP_LEN; j++) { uniq_elements_tbl[j] = AP_NUM_EXT_PORTS;} 795 796 for(i=0; i<AP_OS_LLS_GRP_LEN; i++) { 797 if(ovs_tdm_tbl[i] == AP_NUM_EXT_PORTS) break; 798 } 799 size = i; 800 801 for(i=0,j=0; i<size; i++) { 802 if(ovs_tdm_tbl[i]!=port) { uniq_elements_tbl[j++] = ovs_tdm_tbl[i]; } 803 else cnt++; 804 } 805 div=cnt; 806 if (cnt != 0) { 807 for(i= ((size/div)-1); i<size; i+= (size/div) ) { 808 for(k=size-1; k>=i; k--){ 809 uniq_elements_tbl[k] = uniq_elements_tbl[k-1]; 810 } 811 uniq_elements_tbl[i]=port; 812 if ((--cnt)<=0) { 813 break; 814 } 815 } 816 817 for (i=0; i<size; i++) { 818 if(uniq_elements_tbl[i]== port) { 819 uniq_elements_tbl[i] = token++; 820 if((cnt1++) ==3) { 821 cnt1 =0; 822 token=port; 823 } 824 } 825 } 826 } 827 TDM_COPY(ovs_tdm_tbl,uniq_elements_tbl,sizeof(int)*AP_OS_LLS_GRP_LEN); 828 } 829 830 831 /** 832 @name: tdm_postalloc 833 @param: 834 835 Unless special exceptions are needed for certain port speeds, this is the standard procedure to load time vectors into TDM vector map 836 */ 837 /* 838 int 839 tdm_postalloc(unsigned short **vector_map, int freq, unsigned short spd, short *yy, short *y, int lr_idx_limit, unsigned short lr_stack[TDM_AUX_SIZE], int token, const char* speed, int num_ext_ports) 840 { 841 int v, load_status; 842 843 TDM_BIG_BAR 844 TDM_PRINT1("%sG scheduling pass\n",speed); 845 TDM_SML_BAR 846 TDM_PRINT0("Stack contains: [ "); 847 for (v=*y; v>0; v--) { 848 if (lr_stack[v]!=num_ext_ports) { 849 TDM_PRINT1(" %0d ",lr_stack[v]); 850 } 851 } 852 TDM_PRINT0(" ]\n"); 853 TDM_SML_BAR 854 while (*y > 0) { 855 load_status = tdm_ap_vec_load(vector_map, freq, spd, *yy, lr_idx_limit, num_ext_ports); 856 if (load_status==FAIL) { 857 TDM_ERROR2("Failed to load %sG vector for port %0d\n",speed,lr_stack[*y]); 858 return FAIL; 859 } 860 else { 861 for (v=0; v<VEC_MAP_LEN; v++) { 862 if (vector_map[*yy][v]==token) { 863 vector_map[*yy][v]=lr_stack[*y]; 864 } 865 } 866 TDM_PRINT4("Loaded %sG port %d vector from stack pointer %d into map at index %0d\n",speed, lr_stack[*y], *y, *yy); 867 } 868 (*y)--; (*yy)++; 869 if ((*y)>0) { 870 TDM_SML_BAR 871 TDM_PRINT2("Map pointer rolled to: %0d, stack pointer is at: %0d\n", *yy, *y); 872 TDM_SML_BAR 873 } 874 else { 875 TDM_SML_BAR 876 TDM_PRINT2("Done loading %sG vectors, map pointer floating at: %0d\n",speed, *yy); 877 TDM_SML_BAR 878 } 879 } 880 TDM_BIG_BAR 881 882 return PASS; 883 884 } 885 886 int 887 tdm_acc_alloc(unsigned short **vector_map, int freq, unsigned short spd, short *yy, int lr_idx_limit, int num_ext_ports) 888 { 889 int load_status; 890 891 TDM_BIG_BAR 892 TDM_PRINT0("ACC BW scheduling pass\n"); 893 TDM_SML_BAR 894 895 load_status = tdm_ap_vec_load(vector_map, freq, spd, *yy, lr_idx_limit, num_ext_ports); 896 if (load_status==FAIL) { 897 TDM_ERROR1("Failed to load acc_bw vectors for acc ports %0d\n",AP_ANCL_TOKEN); 898 return FAIL; 899 } 900 (*yy)++; 901 902 TDM_PRINT1("Done loading acc_bw vectors for acc ports, map pointer floating at: %0d\n",*yy); 903 TDM_BIG_BAR 904 905 return PASS; 906 907 } 908 909 */ 910 int 911 tdm_ap_actual_pmap( tdm_mod_t *_tdm ) 912 { 913 int i; 914 915 if (_tdm==NULL) {return FAIL;} 916 917 for (i=1; i<=AP_NUM_PHY_PORTS; i+=AP_NUM_PM_LNS) { 918 /* CLPORTS PM4x25 in dual port mode */ 919 if (_tdm->_chip_data.soc_pkg.speed[i]==SPEED_50G && _tdm->_chip_data.soc_pkg.speed[i+2]==SPEED_50G) { 920 _tdm->_chip_data.soc_pkg.pmap[(i-1)/AP_NUM_PM_LNS][0] = i; 921 _tdm->_chip_data.soc_pkg.pmap[(i-1)/AP_NUM_PM_LNS][1] = i; 922 _tdm->_chip_data.soc_pkg.pmap[(i-1)/AP_NUM_PM_LNS][2] = i+2; 923 _tdm->_chip_data.soc_pkg.pmap[(i-1)/AP_NUM_PM_LNS][3] = i+2; 924 } 925 /* CLPORTS PM4x25 in tri-port mode x-xx or xx-x */ 926 if(i==AP_CL1_PORT || i==AP_CL2_PORT || i==AP_CL4_PORT || i==AP_CL5_PORT ){ 927 if ( _tdm->_chip_data.soc_pkg.speed[i]>_tdm->_chip_data.soc_pkg.speed[i+2] && _tdm->_chip_data.soc_pkg.speed[i+2]==_tdm->_chip_data.soc_pkg.speed[i+3] && _tdm->_chip_data.soc_pkg.speed[i+2]!=SPEED_0 ) { 928 _tdm->_chip_data.soc_pkg.pmap[(i-1)/AP_NUM_PM_LNS][1] = _tdm->_chip_data.soc_pkg.pmap[(i-1)/AP_NUM_PM_LNS][2]; 929 _tdm->_chip_data.soc_pkg.pmap[(i-1)/AP_NUM_PM_LNS][2] = _tdm->_chip_data.soc_pkg.pmap[(i-1)/AP_NUM_PM_LNS][0]; 930 } 931 else if ( _tdm->_chip_data.soc_pkg.speed[i]==_tdm->_chip_data.soc_pkg.speed[i+1] && _tdm->_chip_data.soc_pkg.speed[i]<_tdm->_chip_data.soc_pkg.speed[i+2] && _tdm->_chip_data.soc_pkg.speed[i]!=SPEED_0 ) { 932 _tdm->_chip_data.soc_pkg.pmap[(i-1)/AP_NUM_PM_LNS][2] = _tdm->_chip_data.soc_pkg.pmap[(i-1)/AP_NUM_PM_LNS][1]; 933 _tdm->_chip_data.soc_pkg.pmap[(i-1)/AP_NUM_PM_LNS][1] = _tdm->_chip_data.soc_pkg.pmap[(i-1)/AP_NUM_PM_LNS][3]; 934 } 935 } 936 } 937 938 return PASS; 939 } 940 941 942 /** 943 @name: tdm_ap_vmap_alloc 944 @param: 945 946 Populate original vmap containing all linerate ports with matched speed rates accordingly 947 */ 948 int 949 tdm_ap_vmap_alloc( tdm_mod_t *_tdm ) 950 { 951 int j, v, w, clk_freq, vmap_port_spd, cal_length; 952 unsigned short lr1[TDM_AUX_SIZE], lr10[TDM_AUX_SIZE], lr20[TDM_AUX_SIZE], lr25[TDM_AUX_SIZE], lr40[TDM_AUX_SIZE], lr50[TDM_AUX_SIZE], lr100[TDM_AUX_SIZE]; 953 int speed_type_num, 954 num_120g, num_100g, num_50g, num_40g, 955 num_25g, num_20g, num_10g, num_1g; 956 int param_vmap_wid, param_vmap_len; 957 958 param_vmap_wid = _tdm->_core_data.vmap_max_wid; 959 param_vmap_len = _tdm->_core_data.vmap_max_len; 960 961 /* Initialize speed group arrays for both linerate and oversub */ 962 for (j=0; j<(TDM_AUX_SIZE); j++) { 963 lr1[j] = AP_NUM_EXT_PORTS; 964 lr10[j] = AP_NUM_EXT_PORTS; 965 lr20[j] = AP_NUM_EXT_PORTS; 966 lr25[j] = AP_NUM_EXT_PORTS; 967 lr40[j] = AP_NUM_EXT_PORTS; 968 lr50[j] = AP_NUM_EXT_PORTS; 969 lr100[j]= AP_NUM_EXT_PORTS; 970 971 _tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.os1[j] = AP_NUM_EXT_PORTS; 972 _tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.os10[j] = AP_NUM_EXT_PORTS; 973 _tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.os20[j] = AP_NUM_EXT_PORTS; 974 _tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.os25[j] = AP_NUM_EXT_PORTS; 975 _tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.os40[j] = AP_NUM_EXT_PORTS; 976 _tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.os50[j] = AP_NUM_EXT_PORTS; 977 _tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.os100[j]= AP_NUM_EXT_PORTS; 978 _tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.os120[j]= AP_NUM_EXT_PORTS; 979 } 980 clk_freq = _tdm->_chip_data.soc_pkg.clk_freq; 981 cal_length= _tdm->_chip_data.soc_pkg.lr_idx_limit+_tdm->_chip_data.soc_pkg.tvec_size; 982 983 for (j=0; j<TDM_AUX_SIZE; j++) { 984 /* Pre-allocate linerate ports with the same speed into the same linerate speed group */ 985 if (_tdm->_core_data.vars_pkg.lr_buffer[j] != AP_NUM_EXT_PORTS){ 986 if (_tdm->_core_data.vars_pkg.lr_buffer[j] <= AP_NUM_PHY_PORTS){ 987 if (_tdm->_chip_data.soc_pkg.state[_tdm->_core_data.vars_pkg.lr_buffer[j]-1] == PORT_STATE__LINERATE || 988 _tdm->_chip_data.soc_pkg.state[_tdm->_core_data.vars_pkg.lr_buffer[j]-1] == PORT_STATE__LINERATE_HG){ 989 switch (_tdm->_chip_data.soc_pkg.speed[_tdm->_core_data.vars_pkg.lr_buffer[j]]) { 990 case SPEED_1G: 991 case SPEED_2p5G: 992 tdm_core_prealloc(lr1, _tdm->_core_data.vars_pkg.lr_buffer, &(_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y8), &(_tdm->_core_data.vars_pkg.lr_1), j); 993 break; 994 case SPEED_10G: 995 case SPEED_11G: 996 case SPEED_10G_DUAL: 997 case SPEED_10G_XAUI: 998 tdm_core_prealloc(lr10, _tdm->_core_data.vars_pkg.lr_buffer, &(_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y1), &(_tdm->_core_data.vars_pkg.lr_10), j); 999 break; 1000 case SPEED_20G: 1001 case SPEED_21G: 1002 case SPEED_21G_DUAL: 1003 tdm_core_prealloc(lr20, _tdm->_core_data.vars_pkg.lr_buffer, &(_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y2), &(_tdm->_core_data.vars_pkg.lr_20), j); 1004 break; 1005 case SPEED_25G: 1006 case SPEED_27G: 1007 tdm_core_prealloc(lr25, _tdm->_core_data.vars_pkg.lr_buffer, &(_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y6), &(_tdm->_core_data.vars_pkg.lr_25), j); 1008 break; 1009 case SPEED_40G: 1010 case SPEED_42G: 1011 case SPEED_42G_HG2: 1012 tdm_core_prealloc(lr40, _tdm->_core_data.vars_pkg.lr_buffer, &(_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y3), &(_tdm->_core_data.vars_pkg.lr_40), j); 1013 break; 1014 case SPEED_50G: 1015 case SPEED_53G: 1016 tdm_core_prealloc(lr50, _tdm->_core_data.vars_pkg.lr_buffer, &(_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y5), &(_tdm->_core_data.vars_pkg.lr_50), j); 1017 break; 1018 case SPEED_100G: 1019 case SPEED_106G: 1020 tdm_core_prealloc(lr100, _tdm->_core_data.vars_pkg.lr_buffer, &(_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y4), &(_tdm->_core_data.vars_pkg.lr_100), j); 1021 break; 1022 default: 1023 TDM_ERROR2("Speed %0d port %0d was skipped in linerate preallocation\n",_tdm->_chip_data.soc_pkg.speed[_tdm->_core_data.vars_pkg.lr_buffer[j]],_tdm->_core_data.vars_pkg.lr_buffer[j]); 1024 break; 1025 } 1026 } 1027 else{ 1028 TDM_ERROR2("Failed to presort linerate port %0d with state mapping %0d\n", _tdm->_core_data.vars_pkg.lr_buffer[j], _tdm->_chip_data.soc_pkg.state[_tdm->_core_data.vars_pkg.lr_buffer[j]-1]); 1029 } 1030 } 1031 else{ 1032 TDM_ERROR1("Unrecognized linerate port %0d in linerate preallocation\n", _tdm->_core_data.vars_pkg.lr_buffer[j]); 1033 } 1034 } 1035 /* Pre-allocate oversub ports with the same speed into the same ovesub speed group */ 1036 if (_tdm->_core_data.vars_pkg.os_buffer[j] != AP_NUM_EXT_PORTS){ 1037 if(_tdm->_core_data.vars_pkg.os_buffer[j] <= AP_NUM_PHY_PORTS){ 1038 if (_tdm->_chip_data.soc_pkg.state[_tdm->_core_data.vars_pkg.os_buffer[j]-1] == PORT_STATE__OVERSUB || 1039 _tdm->_chip_data.soc_pkg.state[_tdm->_core_data.vars_pkg.os_buffer[j]-1] == PORT_STATE__OVERSUB_HG){ 1040 switch (_tdm->_chip_data.soc_pkg.speed[_tdm->_core_data.vars_pkg.os_buffer[j]]) { 1041 case SPEED_1G: 1042 case SPEED_2p5G: 1043 tdm_core_prealloc(_tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.os1, _tdm->_core_data.vars_pkg.os_buffer, &(_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.z8), &(_tdm->_core_data.vars_pkg.os_1), j); 1044 break; 1045 case SPEED_10G: 1046 case SPEED_11G: 1047 case SPEED_10G_DUAL: 1048 case SPEED_10G_XAUI: 1049 tdm_core_prealloc(_tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.os10, _tdm->_core_data.vars_pkg.os_buffer, &(_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.z1), &(_tdm->_core_data.vars_pkg.os_10), j); 1050 break; 1051 case SPEED_20G: 1052 case SPEED_21G: 1053 case SPEED_21G_DUAL: 1054 tdm_core_prealloc(_tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.os20, _tdm->_core_data.vars_pkg.os_buffer, &(_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.z2), &(_tdm->_core_data.vars_pkg.os_20), j); 1055 break; 1056 case SPEED_25G: 1057 case SPEED_27G: 1058 tdm_core_prealloc(_tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.os25, _tdm->_core_data.vars_pkg.os_buffer, &(_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.z6), &(_tdm->_core_data.vars_pkg.os_25), j); 1059 break; 1060 case SPEED_40G: 1061 case SPEED_42G: 1062 case SPEED_42G_HG2: 1063 tdm_core_prealloc(_tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.os40, _tdm->_core_data.vars_pkg.os_buffer, &(_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.z3), &(_tdm->_core_data.vars_pkg.os_40), j); 1064 break; 1065 case SPEED_50G: 1066 case SPEED_53G: 1067 tdm_core_prealloc(_tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.os50, _tdm->_core_data.vars_pkg.os_buffer, &(_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.z5), &(_tdm->_core_data.vars_pkg.os_50), j); 1068 break; 1069 case SPEED_100G: 1070 case SPEED_106G: 1071 tdm_core_prealloc(_tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.os100, _tdm->_core_data.vars_pkg.os_buffer, &(_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.z4), &(_tdm->_core_data.vars_pkg.os_100), j); 1072 break; 1073 default: 1074 TDM_ERROR2("Speed %0d port %0d was skipped in oversub preallocation\n",_tdm->_chip_data.soc_pkg.speed[_tdm->_core_data.vars_pkg.os_buffer[j]],_tdm->_core_data.vars_pkg.os_buffer[j]); 1075 } 1076 } 1077 else{ 1078 TDM_ERROR2("Failed to presort oversub port %0d with state mapping %0d\n", _tdm->_core_data.vars_pkg.os_buffer[j], _tdm->_chip_data.soc_pkg.state[_tdm->_core_data.vars_pkg.os_buffer[j]-1]); 1079 } 1080 } 1081 else{ 1082 TDM_ERROR1("Unrecognized oversub port %0d in oversub preallocation\n", _tdm->_core_data.vars_pkg.lr_buffer[j]); 1083 } 1084 } 1085 } 1086 /* Set part of parameters used by core execution for vmap population */ 1087 _tdm->_core_data.vars_pkg.os_enable = (_tdm->_core_data.vars_pkg.os_1||_tdm->_core_data.vars_pkg.os_10||_tdm->_core_data.vars_pkg.os_20||_tdm->_core_data.vars_pkg.os_25||_tdm->_core_data.vars_pkg.os_40||_tdm->_core_data.vars_pkg.os_50||_tdm->_core_data.vars_pkg.os_100||_tdm->_core_data.vars_pkg.os_120); 1088 _tdm->_core_data.vars_pkg.lr_enable = (_tdm->_core_data.vars_pkg.lr_1||_tdm->_core_data.vars_pkg.lr_10||_tdm->_core_data.vars_pkg.lr_20||_tdm->_core_data.vars_pkg.lr_25||_tdm->_core_data.vars_pkg.lr_40||_tdm->_core_data.vars_pkg.lr_50||_tdm->_core_data.vars_pkg.lr_100||_tdm->_core_data.vars_pkg.lr_120); 1089 _tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.num_lr = (_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y8+_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y1+_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y2+_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y3+_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y4+_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y5+_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y6+_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y7); 1090 _tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.num_os = (_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.z8+_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.z1+_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.z2+_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.z3+_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.z4+_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.z5+_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.z6+_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.z7); 1091 _tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.num_100g = _tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y4; 1092 _tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.num_40g = _tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y3; 1093 { 1094 num_120g= _tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y7; 1095 num_100g= _tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y4; 1096 num_50g = _tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y5; 1097 num_40g = _tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y3; 1098 num_25g = _tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y6; 1099 num_20g = _tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y2; 1100 num_10g = _tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y1; 1101 num_1g = _tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y8; 1102 speed_type_num = _tdm->_core_data.vars_pkg.lr_1+ 1103 _tdm->_core_data.vars_pkg.lr_10+ 1104 _tdm->_core_data.vars_pkg.lr_20+ 1105 _tdm->_core_data.vars_pkg.lr_25+ 1106 _tdm->_core_data.vars_pkg.lr_40+ 1107 _tdm->_core_data.vars_pkg.lr_50+ 1108 _tdm->_core_data.vars_pkg.lr_100+ 1109 _tdm->_core_data.vars_pkg.lr_120; 1110 TDM_PRINT2("%8s%d\n", "120G - ", num_120g); 1111 TDM_PRINT2("%8s%d\n", "100G - ", num_100g); 1112 TDM_PRINT2("%8s%d\n", " 50G - ", num_50g); 1113 TDM_PRINT2("%8s%d\n", " 40G - ", num_40g); 1114 TDM_PRINT2("%8s%d\n", " 25G - ", num_25g); 1115 TDM_PRINT2("%8s%d\n", " 20G - ", num_20g); 1116 TDM_PRINT2("%8s%d\n", " 10G - ", num_10g); 1117 TDM_PRINT2("%8s%d\n", " 1G - ", num_1g); 1118 TDM_PRINT1("\nNumber of Linerate Speed Types: %d\n\n", speed_type_num); 1119 TDM_BIG_BAR 1120 } 1121 /* Populate original vmap with pre-allocated linerate speed groups */ 1122 /* 100G */ 1123 if(_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y4 > 0){ 1124 vmap_port_spd = 100; 1125 if (tdm_core_postalloc_vmap(_tdm->_core_data.vmap, clk_freq, vmap_port_spd, &_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.yy, &(_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y4), cal_length, lr100, TOKEN_100G, "100", AP_NUM_EXT_PORTS, param_vmap_wid, param_vmap_len)!=PASS) { 1126 TDM_ERROR0("Critical error in 100G port vector preallocation\n"); 1127 } 1128 } 1129 /* 50G */ 1130 if(_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y5 > 0){ 1131 for (v=_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y5; v>0; v--) { 1132 if (tdm_ap_legacy_which_tsc(lr50[v+1],_tdm->_chip_data.soc_pkg.pmap)==tdm_ap_legacy_which_tsc(lr50[v],_tdm->_chip_data.soc_pkg.pmap) || 1133 tdm_ap_legacy_which_tsc(lr50[v-1],_tdm->_chip_data.soc_pkg.pmap)==tdm_ap_legacy_which_tsc(lr50[v],_tdm->_chip_data.soc_pkg.pmap)) { 1134 _tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.prox_swap=lr50[v]; 1135 for (w=v; w>0; w--) { 1136 lr50[w]=lr50[w-1]; 1137 } 1138 lr50[1]=_tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.prox_swap; 1139 } 1140 } 1141 for (v=_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y5; v>0; v--) { 1142 _tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.tri_chk = tdm_ap_legacy_which_tsc(lr50[v],_tdm->_chip_data.soc_pkg.pmap); 1143 for (w=0; w<4; w++) { 1144 if (_tdm->_chip_data.soc_pkg.speed[_tdm->_chip_data.soc_pkg.pmap[_tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.tri_chk][w]]!=SPEED_50G) { 1145 _tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.tri_en_50=BOOL_TRUE; 1146 TDM_PRINT0("50G triport detected\n"); 1147 break; 1148 } 1149 } 1150 } 1151 vmap_port_spd = 50; 1152 if (tdm_core_postalloc_vmap(_tdm->_core_data.vmap, clk_freq, vmap_port_spd, &_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.yy, &(_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y5), cal_length, lr50, TOKEN_50G, "50", AP_NUM_EXT_PORTS, param_vmap_wid, param_vmap_len)!=PASS) { 1153 TDM_ERROR0("Critical error in 50G port vector preallocation\n"); 1154 } 1155 } 1156 /* 40G */ 1157 if (_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y3 > 0) { 1158 for (v=_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y3; v>0; v--) { 1159 if (tdm_ap_legacy_which_tsc(lr40[v+1],_tdm->_chip_data.soc_pkg.pmap)==tdm_ap_legacy_which_tsc(lr40[v],_tdm->_chip_data.soc_pkg.pmap) || 1160 tdm_ap_legacy_which_tsc(lr40[v-1],_tdm->_chip_data.soc_pkg.pmap)==tdm_ap_legacy_which_tsc(lr40[v],_tdm->_chip_data.soc_pkg.pmap)) { 1161 _tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.prox_swap=lr40[v]; 1162 for (w=v; w>0; w--) { 1163 lr40[w]=lr40[w-1]; 1164 } 1165 lr40[1]=_tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.prox_swap; 1166 } 1167 } 1168 for (v=_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y3; v>0; v--) { 1169 _tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.tri_chk = tdm_ap_legacy_which_tsc(lr40[v],_tdm->_chip_data.soc_pkg.pmap); 1170 for (w=0; w<4; w++) { 1171 if (_tdm->_chip_data.soc_pkg.speed[_tdm->_chip_data.soc_pkg.pmap[_tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.tri_chk][w]]!=SPEED_40G && _tdm->_chip_data.soc_pkg.state[_tdm->_chip_data.soc_pkg.pmap[_tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.tri_chk][w]-1]!=PORT_STATE__DISABLED) { 1172 _tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.tri_en_40=BOOL_TRUE; 1173 TDM_PRINT0("40G triport detected\n"); 1174 break; 1175 } 1176 } 1177 } 1178 vmap_port_spd = 40; 1179 if(num_100g>0) { 1180 vmap_port_spd=41; 1181 } 1182 else if (num_100g==0 && num_50g>0){ 1183 vmap_port_spd = 44; 1184 } 1185 if (tdm_core_postalloc_vmap(_tdm->_core_data.vmap, clk_freq, vmap_port_spd, &_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.yy, &(_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y3), cal_length, lr40, TOKEN_40G, "40", AP_NUM_EXT_PORTS, param_vmap_wid, param_vmap_len)!=PASS) { 1186 TDM_ERROR0("Critical error in 40G port vector vmap allocation\n"); 1187 } 1188 } 1189 /* 25G */ 1190 if (_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y6 > 0) { 1191 for (v=_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y2; v>0; v--) { 1192 _tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.tri_chk = tdm_ap_legacy_which_tsc(lr20[v],_tdm->_chip_data.soc_pkg.pmap); 1193 for (w=0; w<4; w++) { 1194 if (_tdm->_chip_data.soc_pkg.speed[_tdm->_chip_data.soc_pkg.pmap[_tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.tri_chk][w]]!=SPEED_20G) { 1195 _tdm->_core_data.vars_pkg.m_tdm_vmap_alloc.tri_en_20=BOOL_TRUE; 1196 TDM_PRINT0("20G triport detected\n"); 1197 break; 1198 } 1199 } 1200 } 1201 vmap_port_spd = 25; 1202 if (_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y4==0 && 1203 _tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y5==0 && 1204 _tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y3>0 ){ 1205 vmap_port_spd = 26; 1206 } 1207 if (tdm_core_postalloc_vmap(_tdm->_core_data.vmap, clk_freq, vmap_port_spd, &_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.yy, &(_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y6), cal_length, lr25, TOKEN_25G, "25", AP_NUM_EXT_PORTS, param_vmap_wid, param_vmap_len)!=PASS) { 1208 TDM_ERROR0("Critical error in 25G port vector preallocation\n"); 1209 } 1210 } 1211 /* 20G */ 1212 if (_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y2 > 0) { 1213 vmap_port_spd = 20; 1214 if (tdm_core_postalloc_vmap(_tdm->_core_data.vmap, clk_freq, vmap_port_spd, &_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.yy, &(_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y2), cal_length, lr20, TOKEN_20G, "20", AP_NUM_EXT_PORTS, param_vmap_wid, param_vmap_len)!=PASS) { 1215 TDM_ERROR0("Critical error in 20G port vector preallocation\n"); 1216 } 1217 } 1218 /* 10G */ 1219 if (_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y1 > 0) { 1220 vmap_port_spd = 10; 1221 if (tdm_core_postalloc_vmap(_tdm->_core_data.vmap, clk_freq, vmap_port_spd, &_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.yy, &(_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y1), cal_length, lr10, TOKEN_10G, "10", AP_NUM_EXT_PORTS, param_vmap_wid, param_vmap_len)!=PASS) { 1222 TDM_ERROR0("Critical error in 10G port vector preallocation\n"); 1223 } 1224 } 1225 /* 1G */ 1226 if (_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y8 > 0) { 1227 vmap_port_spd = 1; 1228 if (tdm_core_postalloc_vmap(_tdm->_core_data.vmap, clk_freq, vmap_port_spd, &_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.yy, &(_tdm->_core_data.vars_pkg.m_tdm_core_vbs_scheduler.y8), cal_length, lr1, TOKEN_1G, "1", AP_NUM_EXT_PORTS, param_vmap_wid, param_vmap_len)!=PASS) { 1229 TDM_ERROR0("Critical error in 1G port vector preallocation\n"); 1230 } 1231 } 1232 1233 /* 1234 return ( _tdm->_core_exec[TDM_CORE_EXEC__SCHEDULER]( _tdm ) ); */ 1235 if(tdm_core_vmap_alloc_mix(_tdm)!=PASS){ 1236 TDM_ERROR0("VMAP Mix Allocation failed\n"); 1237 } else { 1238 TDM_PRINT0("VMAP Mix Allocation passed\n"); 1239 } 1240 return (tdm_ap_vbs_scheduler(_tdm)); 1241 } 1242 1243 1244 /** 1245 @name: tdm_ap_acc_alloc_new 1246 @param: 1247 */ 1248 int 1249 tdm_ap_acc_alloc_new( tdm_mod_t *_tdm ) 1250 { 1251 int i,j, idx, idx_opt, idx_up, idx_dn, dist_opt=0, 1252 empty_slot_cnt=0, empty_slot_token, acc_slot_cnt=0, acc_slot_token, 1253 acc_slot_num, result=PASS; 1254 1255 int *tdm_pipe_main, tdm_pipe_main_len; 1256 1257 TDM_SEL_CAL(_tdm->_core_data.vars_pkg.cal_id,tdm_pipe_main); 1258 tdm_pipe_main_len = _tdm->_chip_data.soc_pkg.lr_idx_limit + _tdm->_chip_data.soc_pkg.tvec_size; 1259 empty_slot_token = _tdm->_chip_data.soc_pkg.num_ext_ports; 1260 acc_slot_num = _tdm->_chip_data.soc_pkg.tvec_size; 1261 acc_slot_token = AP_ANCL_TOKEN; 1262 1263 /* check available slots */ 1264 for (i=0; i<tdm_pipe_main_len; i++){ 1265 if (tdm_pipe_main[i] == empty_slot_token){ 1266 empty_slot_cnt++; 1267 } 1268 } 1269 if (empty_slot_cnt<acc_slot_num){ 1270 TDM_ERROR2("FAILED in ACC bandwidth allocation, Not enough available slots for ACC, Slot_Required %d, Slot_Available %d\n",acc_slot_cnt, empty_slot_cnt); 1271 result = FAIL; 1272 } 1273 /* allocate acc slots */ 1274 if (acc_slot_num>0 && result==PASS){ 1275 dist_opt = tdm_pipe_main_len/acc_slot_num; 1276 for (i=0; i<acc_slot_num; i++){ 1277 idx_opt = i*dist_opt; 1278 if(idx_opt<tdm_pipe_main_len){ 1279 idx = tdm_pipe_main_len; 1280 idx_up = tdm_pipe_main_len; 1281 idx_dn = tdm_pipe_main_len; 1282 for (j=idx_opt; j>0; j--){ 1283 if(tdm_pipe_main[j]==empty_slot_token){ 1284 idx_up = j; 1285 break; 1286 } 1287 } 1288 for (j=idx_opt; j<tdm_pipe_main_len; j++){ 1289 if(tdm_pipe_main[j]==empty_slot_token){ 1290 idx_dn = j; 1291 break; 1292 } 1293 } 1294 if (idx_up<tdm_pipe_main_len || idx_dn<tdm_pipe_main_len){ 1295 if (idx_up==tdm_pipe_main_len){ 1296 idx = idx_dn; 1297 } 1298 else if (idx_dn==tdm_pipe_main_len){ 1299 idx = idx_up; 1300 } 1301 else{ 1302 idx = ((idx_opt-idx_up) < (idx_dn-idx_opt))? (idx_up): (idx_dn); 1303 } 1304 } 1305 1306 if (idx < tdm_pipe_main_len){ 1307 tdm_pipe_main[idx] = acc_slot_token; 1308 } 1309 } 1310 } 1311 } 1312 /* check acc slots */ 1313 if (acc_slot_num>0 && result==PASS){ 1314 for (i=0; i<tdm_pipe_main_len; i++){ 1315 if (tdm_pipe_main[i] == acc_slot_token){ 1316 acc_slot_cnt++; 1317 } 1318 } 1319 if(acc_slot_cnt != acc_slot_num){ 1320 result = FAIL; 1321 TDM_ERROR2("FAILED in ACC bandwidth allocation, Slot_Required %d, Slot_Allocated %d\n",acc_slot_num, acc_slot_cnt); 1322 } 1323 } 1324 1325 return result; 1326 } 1327 1328 /** 1329 @name: tdm_ap_vbs_scheduler 1330 @param: 1331 */ 1332 int 1333 tdm_ap_vbs_scheduler( tdm_mod_t *_tdm ) 1334 { 1335 int i, *tdm_pipe_main, tdm_cal_length, cnt=0; 1336 TDM_SEL_CAL(_tdm->_core_data.vars_pkg.cal_id,tdm_pipe_main); 1337 tdm_cal_length = _tdm->_chip_data.soc_pkg.lr_idx_limit+_tdm->_chip_data.soc_pkg.tvec_size; 1338 1339 /* Allocate slots for all linerate ports among entire TDM calendar */ 1340 if (_tdm->_core_data.vars_pkg.lr_enable) { 1341 if(FAIL==tdm_core_vbs_scheduler_lr(_tdm)){ 1342 TDM_ERROR0("FAILED in slot allocation for LINERATE ports\n"); 1343 } 1344 } 1345 /* Allocate ACC slots */ 1346 if (_tdm->_core_data.vars_pkg.os_enable || _tdm->_core_data.vars_pkg.lr_enable) { 1347 if(FAIL==tdm_ap_acc_alloc_new(_tdm)){ 1348 TDM_ERROR0("FAILED in slot allocation for ANCILLARY bandwidth\n"); 1349 } 1350 } 1351 /* Allocate OVSB and/or IDLE slots */ 1352 if (_tdm->_core_data.vars_pkg.os_enable || _tdm->_core_data.vars_pkg.lr_enable) { 1353 /* OVSB: Place the OVS token for all unallocated slots */ 1354 if (_tdm->_core_data.vars_pkg.os_enable && (!_tdm->_core_data.vars_pkg.lr_enable)) { 1355 for (i=0; i<tdm_cal_length; i++) { 1356 if (tdm_pipe_main[i]==_tdm->_chip_data.soc_pkg.num_ext_ports) { 1357 tdm_pipe_main[i] = _tdm->_chip_data.soc_pkg.soc_vars.ovsb_token; 1358 } 1359 } 1360 } 1361 /* IDLE: Place IDLE tokens for all unallocated slots */ 1362 else { 1363 for (i=0; i<tdm_cal_length; i++) { 1364 if (tdm_pipe_main[i]==_tdm->_chip_data.soc_pkg.num_ext_ports) { 1365 if (_tdm->_core_data.vars_pkg.os_enable) { 1366 tdm_pipe_main[i] = _tdm->_chip_data.soc_pkg.soc_vars.ovsb_token; 1367 } 1368 else { 1369 if ((cnt++)%2==0) { 1370 tdm_pipe_main[i] = _tdm->_chip_data.soc_pkg.soc_vars.idl1_token; 1371 } 1372 else { 1373 tdm_pipe_main[i] = _tdm->_chip_data.soc_pkg.soc_vars.idl2_token; 1374 } 1375 } 1376 } 1377 } 1378 } 1379 } 1380 1381 /* OVS grouping */ 1382 if (_tdm->_core_exec[TDM_CORE_EXEC__SCHEDULER_OVS](_tdm)==FAIL) { 1383 return (TDM_EXEC_CORE_SIZE+1); 1384 } 1385 1386 return ( _tdm->_chip_exec[TDM_CHIP_EXEC__FILTER](_tdm) ); 1387 1388 } 1389 1390 1391 /** 1392 */ 1393 void tdm_ap_ovs_20_40_clport(int *ovs_tdm_tbl, tdm_ap_chip_legacy_t *ap_chip) 1394 { 1395 1396 int i, j, idx, size=AP_OS_LLS_GRP_LEN, avg=0; 1397 int rpt_port; 1398 1399 for(idx=0; idx<AP_OS_LLS_GRP_LEN; idx++) { 1400 if(ovs_tdm_tbl[idx] == AP_NUM_EXT_PORTS) break; 1401 } 1402 size = idx; 1403 1404 for( i = 0 ; i<size; i++) { 1405 if(((ovs_tdm_tbl[i]>=29 && ovs_tdm_tbl[i]<=35) || (ovs_tdm_tbl[i]>=65 && ovs_tdm_tbl[i]<=71)) && 1406 ((*ap_chip).tdm_globals.speed[ovs_tdm_tbl[i]] == SPEED_40G || (*ap_chip).tdm_globals.speed[ovs_tdm_tbl[i]] == SPEED_20G)) { 1407 if(ovs_tdm_tbl[i]==ovs_tdm_tbl[i+1]) { 1408 rpt_port=ovs_tdm_tbl[i]; 1409 avg = ((*ap_chip).tdm_globals.speed[rpt_port]== SPEED_40G) ? (size/4) : (size/2); 1410 if( (i+avg) <size ){ 1411 for(j=i; j<(i+avg); j++) { ovs_tdm_tbl[j] = ovs_tdm_tbl[j+1]; } 1412 ovs_tdm_tbl[i+avg] = rpt_port; 1413 } 1414 else { 1415 for(j=i; j<size; j++) { ovs_tdm_tbl[j] = ovs_tdm_tbl[j+1];} 1416 ovs_tdm_tbl[size-1]= ovs_tdm_tbl[0]; 1417 for(j=0; j<(i+avg)%size; j++) {ovs_tdm_tbl[j] = ovs_tdm_tbl[j+1];} 1418 ovs_tdm_tbl[(i+avg)%size] = rpt_port; 1419 } 1420 } 1421 } 1422 } 1423 1424 } 1425 1426 1427 1428 1429 1430 1431 void tdm_ap_reconfig_pgw_tbl(int *pgw_tdm_tbl, int port[2], enum port_speed_e speed[2]) 1432 { 1433 1434 int i, j ,k, idx, num_ovs=0, avg,cnt0=0, cnt1=0, size=AP_LR_LLS_LEN; 1435 int elmnt_repeating, elmnt_repeating_cnt=0, num_elements_repeating=0; 1436 int uniq_elements_cnt=0, sum_of_spacing=0, current_spacing=0; 1437 int temp,spacing_idx=0; 1438 int temp_swap_storage = 0; 1439 1440 int spacing_tbl[AP_LR_LLS_LEN],elmnt_repeating_tbl[AP_LR_LLS_LEN],uniq_elements_tbl[AP_LR_LLS_LEN]; 1441 1442 for(j=0; j<AP_LR_LLS_LEN; j++) { spacing_tbl[j] = 0;} 1443 1444 for(i=0; i<AP_LR_LLS_LEN; i++) { 1445 if(pgw_tdm_tbl[i] == AP_NUM_EXT_PORTS) break; 1446 if(pgw_tdm_tbl[i] == AP_OVSB_TOKEN) num_ovs++; 1447 } 1448 size = i; 1449 1450 if(speed[0]==SPEED_100G || speed[0]==SPEED_50G || speed[1]==SPEED_100G || speed[1]==SPEED_50G ) { 1451 1452 for(i=0; i<2; i++) { 1453 if(speed[i]==SPEED_100G || speed[i]==SPEED_50G) { 1454 elmnt_repeating_tbl[num_elements_repeating++] = port[i]; 1455 elmnt_repeating = port[i]; 1456 for(j=0; j<size; j++) { 1457 if(pgw_tdm_tbl[j] == elmnt_repeating_tbl[num_elements_repeating-1]) { 1458 for(k=j-1; k>=0; k--){ 1459 pgw_tdm_tbl[k+1] = pgw_tdm_tbl[k]; 1460 } 1461 elmnt_repeating_cnt++; 1462 pgw_tdm_tbl[0] = elmnt_repeating; 1463 } 1464 } 1465 } 1466 } 1467 1468 for(i=elmnt_repeating_cnt; i<size; i++) { 1469 uniq_elements_tbl[uniq_elements_cnt++] = pgw_tdm_tbl[i]; 1470 } 1471 /*if one falcon in 100G*/ 1472 if(num_elements_repeating == 1) { 1473 do { 1474 for(i=0; i<elmnt_repeating_cnt/num_elements_repeating; i++) { 1475 spacing_tbl[i]++; 1476 sum_of_spacing++; 1477 if(sum_of_spacing == uniq_elements_cnt) break; 1478 } 1479 } while (sum_of_spacing < uniq_elements_cnt); 1480 /* make the spacing table symmetric*/ 1481 do { 1482 spacing_idx++; 1483 } while(spacing_tbl[spacing_idx] != 0); 1484 1485 for(i=0; i<spacing_idx; i++) { 1486 temp= spacing_tbl[spacing_idx-1]; 1487 for(k=spacing_idx-1; k>i; k--) { spacing_tbl[k] = spacing_tbl[k-1];} 1488 spacing_tbl[i] = temp; 1489 i=i+1; 1490 } 1491 /* put the repeating elements at start of tbl*/ 1492 for(k=0, j=0; k<num_elements_repeating; k++) { 1493 pgw_tdm_tbl[j++] = elmnt_repeating_tbl[k]; 1494 } 1495 1496 for(i=0, current_spacing=0, idx=0 ; i<uniq_elements_cnt; ) { 1497 if(current_spacing==spacing_tbl[idx]) { 1498 current_spacing = 0; 1499 idx++; 1500 for(k=0; k<num_elements_repeating; k++) { 1501 pgw_tdm_tbl[j++] = elmnt_repeating_tbl[k]; 1502 } 1503 } 1504 else { pgw_tdm_tbl[j++]=uniq_elements_tbl[i]; current_spacing++; i++; } 1505 } 1506 } 1507 /*if two falcons in 100G or in 40G*/ 1508 if (num_elements_repeating == 2) { 1509 for(i=0, j=0; i< elmnt_repeating_cnt/num_elements_repeating; i++ ) { 1510 for(k=0; k<num_elements_repeating; k++) { 1511 pgw_tdm_tbl[j++] = elmnt_repeating_tbl[k]; 1512 } 1513 } 1514 if (uniq_elements_cnt > 0) { 1515 avg=size/uniq_elements_cnt; /* + (size%uniq_elements_cnt>0 ? 1:0); ceil(size/uniq_elements_cnt) */ 1516 } else { 1517 TDM_ERROR0("Error: Divide by zero\n"); 1518 return; 1519 } 1520 1521 for(i=avg-1, idx=0; i<size; ) { 1522 for(k=size-1; k>=i; k--) { pgw_tdm_tbl[k] = pgw_tdm_tbl[k-1];} 1523 pgw_tdm_tbl[i] =uniq_elements_tbl[idx++]; 1524 i+=avg; 1525 if(idx ==uniq_elements_cnt) break; 1526 } 1527 } 1528 /* reconfig PGW calendar for 2x50G */ 1529 if (speed[0] == SPEED_50G) { 1530 for (i=0; i<AP_LR_LLS_LEN; i++) { 1531 if(pgw_tdm_tbl[i]== port[0]) { 1532 if ((cnt0++)%2==0) pgw_tdm_tbl[i] = port[0] ; 1533 else pgw_tdm_tbl[i] = (port[0]+2); 1534 } 1535 } 1536 } 1537 if (speed[1]== SPEED_50G) { 1538 for (i=0; i<AP_LR_LLS_LEN; i++) { 1539 if(pgw_tdm_tbl[i]== port[1]) { 1540 if ((cnt1++)%2==0) pgw_tdm_tbl[i] = port[1]; 1541 else pgw_tdm_tbl[i] = (port[1]+2); 1542 } 1543 } 1544 } 1545 1546 1547 /* Recheck if any of the ports arrive back-to-back in pgw table */ 1548 for (j=1; j<size;j++) { 1549 for (i=j;i<size;i++) { 1550 if ((pgw_tdm_tbl[i-1] == pgw_tdm_tbl[i]) || 1551 ( (i==size-1) && (pgw_tdm_tbl[i]==pgw_tdm_tbl[j]))) { /* in an array {a,b,c,...} if a==b, then swap b & c */ 1552 if (pgw_tdm_tbl[i]==AP_OVSB_TOKEN) continue; 1553 temp_swap_storage = pgw_tdm_tbl[i]; 1554 pgw_tdm_tbl[i] = pgw_tdm_tbl[i+1]; 1555 pgw_tdm_tbl[i+1] = temp_swap_storage; 1556 /* i=0; this make sure we reiterate the loop to make sure that the repetition doesnt occur */ 1557 } 1558 } 1559 } 1560 1561 } 1562 }