tdm_ap_iarb.c (19797B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * $All Rights Reserved.$ 7 * 8 * TDM chip specific IARB arbitration schedules 9 */ 10 #ifdef _TDM_STANDALONE 11 #include <tdm_top.h> 12 #else 13 #include <soc/tdm/core/tdm_top.h> 14 #endif 15 16 17 18 /**NAK, AP has only 1 Iarb TDM tbl. TD2+ had lr_tbl and ovs_tbl**/ 19 20 /** 21 @name: init_iarb_tdm_lr_table 22 @param: int, int, int, int, int*, int*, int[512], int[512] 23 24 IARB TDM Linerate Schedule: 25 Input 1 => Core bandwidth - 567/480/340/300/260. 26 Input 2 => 1 if there are 4x1G management ports, 0 otherwise. 27 Input 3 => 1 if there are 4x2.5G management ports, 0 otherwise. 28 Input 4 => 1 if there are 1x10G management port, 0 otherwise. 29 Output 5 => The X-pipe TDM linerate table wrap pointer value. 30 Output 6 => The Y-pipe TDM linerate table wrap pointer value. 31 Output 7 => The X-pipe TDM linerate schedule. 32 Output 8 => The Y-pipe TDM linerate schedule. 33 */ 34 void 35 tdm_ap_init_iarb_tdm_table (int core_bw, int *iarb_tdm_wrap_ptr_lr_x, int *iarb_tdm_tbl_lr_x) 36 { 37 int i; 38 39 switch (core_bw) { 40 case 567 : 41 *iarb_tdm_wrap_ptr_lr_x = 232; 42 for (i = 0; i < 28; i++) { 43 if (i%2 == 0) { 44 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 45 } else { 46 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 47 } 48 } 49 iarb_tdm_tbl_lr_x[28] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 50 for (i = 29; i < 57; i++) { 51 if ((i-29)%2 == 0) { 52 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 53 } else { 54 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 55 } 56 } 57 iarb_tdm_tbl_lr_x[57] = IARB_MAIN_TDM__TDM_SLOT_RDB_PORT; 58 for (i = 58; i < 86; i++) { 59 if ((i-58)%2 == 0) { 60 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 61 } else { 62 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 63 } 64 } 65 iarb_tdm_tbl_lr_x[86] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 66 for (i = 87; i < 115; i++) { 67 if ((i-87)%2 == 0) { 68 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 69 } else { 70 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 71 } 72 } 73 iarb_tdm_tbl_lr_x[115] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 74 for (i = 116; i < 144; i++) { 75 if ((i-116)%2 == 0) { 76 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 77 } else { 78 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 79 } 80 } 81 iarb_tdm_tbl_lr_x[144] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 82 for (i = 145; i < 173; i++) { 83 if ((i-145)%2 == 0) { 84 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 85 } else { 86 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 87 } 88 } 89 iarb_tdm_tbl_lr_x[173] = IARB_MAIN_TDM__TDM_SLOT_RDB_PORT; 90 for (i = 174; i < 202; i++) { 91 if ((i-174)%2 == 0) { 92 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 93 } else { 94 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 95 } 96 } 97 iarb_tdm_tbl_lr_x[202] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 98 for (i = 203; i < 217; i++) { 99 if ((i-203)%2 == 0) { 100 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 101 } else { 102 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 103 } 104 } 105 iarb_tdm_tbl_lr_x[217] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 106 for (i = 218; i < 232; i++) { 107 if ((i-218)%2 == 0) { 108 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 109 } else { 110 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 111 } 112 } 113 iarb_tdm_tbl_lr_x[232] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 114 115 /* Then check for management ports. */ 116 /* NAK, Not suppoted in AP Iarb. management ports are scheduled with regular ports in PGW".*/ 117 break; 118 case 511 : 119 *iarb_tdm_wrap_ptr_lr_x = 210; 120 for (i = 0; i < 26; i++) { 121 if (i%2 == 0) { 122 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 123 } else { 124 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 125 } 126 } 127 iarb_tdm_tbl_lr_x[26] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 128 for (i = 27; i < 51; i++) { 129 if ((i-27)%2 == 0) { 130 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 131 } else { 132 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 133 } 134 } 135 iarb_tdm_tbl_lr_x[51] = IARB_MAIN_TDM__TDM_SLOT_RDB_PORT; 136 for (i = 52; i < 78; i++) { 137 if ((i-52)%2 == 0) { 138 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 139 } else { 140 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 141 } 142 } 143 iarb_tdm_tbl_lr_x[78] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 144 for (i = 79; i < 103; i++) { 145 if ((i-79)%2 == 0) { 146 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 147 } else { 148 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 149 } 150 } 151 iarb_tdm_tbl_lr_x[103] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 152 for (i = 104; i < 130; i++) { 153 if ((i-104)%2 == 0) { 154 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 155 } else { 156 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 157 } 158 } 159 iarb_tdm_tbl_lr_x[130] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 160 for (i = 131; i < 155; i++) { 161 if ((i-131)%2 == 0) { 162 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 163 } else { 164 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 165 } 166 } 167 iarb_tdm_tbl_lr_x[155] = IARB_MAIN_TDM__TDM_SLOT_RDB_PORT; 168 for (i = 156; i < 182; i++) { 169 if ((i-156)%2 == 0) { 170 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 171 } else { 172 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 173 } 174 } 175 iarb_tdm_tbl_lr_x[182] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 176 for (i = 183; i < 209; i++) { 177 if ((i-183)%2 == 0) { 178 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 179 } else { 180 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 181 } 182 } 183 iarb_tdm_tbl_lr_x[209] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 184 iarb_tdm_tbl_lr_x[210] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 185 break; 186 case 480 : 187 *iarb_tdm_wrap_ptr_lr_x = 200; 188 for (i = 0; i < 24; i++) { 189 if (i%2 == 0) { 190 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 191 } else { 192 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 193 } 194 } 195 iarb_tdm_tbl_lr_x[24] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 196 for (i = 25; i < 49; i++) { 197 if ((i-25)%2 == 0) { 198 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 199 } else { 200 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 201 } 202 } 203 iarb_tdm_tbl_lr_x[49] = IARB_MAIN_TDM__TDM_SLOT_RDB_PORT; 204 for (i = 50; i < 74; i++) { 205 if ((i-50)%2 == 0) { 206 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 207 } else { 208 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 209 } 210 } 211 iarb_tdm_tbl_lr_x[74] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 212 for (i = 75; i < 99; i++) { 213 if ((i-75)%2 == 0) { 214 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 215 } else { 216 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 217 } 218 } 219 iarb_tdm_tbl_lr_x[99] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 220 for (i = 100; i < 124; i++) { 221 if ((i-100)%2 == 0) { 222 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 223 } else { 224 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 225 } 226 } 227 iarb_tdm_tbl_lr_x[124] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 228 for (i = 125; i < 149; i++) { 229 if ((i-125)%2 == 0) { 230 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 231 } else { 232 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 233 } 234 } 235 iarb_tdm_tbl_lr_x[149] = IARB_MAIN_TDM__TDM_SLOT_RDB_PORT; 236 for (i = 150; i < 174; i++) { 237 if ((i-150)%2 == 0) { 238 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 239 } else { 240 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 241 } 242 } 243 iarb_tdm_tbl_lr_x[174] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 244 for (i = 175; i < 199; i++) { 245 if ((i-175)%2 == 0) { 246 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 247 } else { 248 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 249 } 250 } 251 iarb_tdm_tbl_lr_x[199] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 252 iarb_tdm_tbl_lr_x[200] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 253 254 /* Then check for management ports. */ 255 /* NAK, Not suppoted in AP Iarb. management ports are scheduled with regular ports in PGW".*/ 256 break; 257 case 340 : 258 *iarb_tdm_wrap_ptr_lr_x = 144; 259 for (i = 0; i < 18; i++) { 260 if (i%2 == 0) { 261 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 262 } else { 263 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 264 } 265 } 266 iarb_tdm_tbl_lr_x[18] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 267 for (i = 19; i < 35; i++) { 268 if ((i-19)%2 == 0) { 269 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 270 } else { 271 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 272 } 273 } 274 iarb_tdm_tbl_lr_x[35] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 275 for (i = 36; i < 54; i++) { 276 if ((i-36)%2 == 0) { 277 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 278 } else { 279 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 280 } 281 } 282 iarb_tdm_tbl_lr_x[54] = IARB_MAIN_TDM__TDM_SLOT_RDB_PORT; 283 for (i = 55; i < 71; i++) { 284 if ((i-55)%2 == 0) { 285 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 286 } else { 287 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 288 } 289 } 290 iarb_tdm_tbl_lr_x[71] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 291 for (i = 72; i < 90; i++) { 292 if ((i-72)%2 == 0) { 293 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 294 } else { 295 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 296 } 297 } 298 iarb_tdm_tbl_lr_x[90] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 299 for (i = 91; i < 107; i++) { 300 if ((i-91)%2 == 0) { 301 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 302 } else { 303 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 304 } 305 } 306 iarb_tdm_tbl_lr_x[107] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 307 for (i = 108; i < 126; i++) { 308 if ((i-108)%2 == 0) { 309 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 310 } else { 311 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 312 } 313 } 314 iarb_tdm_tbl_lr_x[126] = IARB_MAIN_TDM__TDM_SLOT_RDB_PORT; 315 for (i = 127; i < 143; i++) { 316 if ((i-127)%2 == 0) { 317 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 318 } else { 319 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 320 } 321 } 322 iarb_tdm_tbl_lr_x[143] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 323 iarb_tdm_tbl_lr_x[144] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 324 325 /* Then check for management ports. */ 326 /* NAK, Not suppoted in AP Iarb. management ports are scheduled with regular ports in PGW".*/ 327 break; 328 case 300 : 329 *iarb_tdm_wrap_ptr_lr_x = 128; 330 for (i = 0; i < 16; i++) { 331 if (i%2 == 0) { 332 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 333 } else { 334 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 335 } 336 } 337 iarb_tdm_tbl_lr_x[16] = IARB_MAIN_TDM__TDM_SLOT_RDB_PORT; 338 for (i = 17; i < 31; i++) { 339 if ((i-17)%2 == 0) { 340 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 341 } else { 342 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 343 } 344 } 345 iarb_tdm_tbl_lr_x[31] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 346 for (i = 32; i < 48; i++) { 347 if ((i-32)%2 == 0) { 348 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 349 } else { 350 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 351 } 352 } 353 iarb_tdm_tbl_lr_x[48] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 354 for (i = 49; i < 63; i++) { 355 if ((i-49)%2 == 0) { 356 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 357 } else { 358 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 359 } 360 } 361 iarb_tdm_tbl_lr_x[63] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 362 for (i = 64; i < 80; i++) { 363 if ((i-64)%2 == 0) { 364 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 365 } else { 366 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 367 } 368 } 369 iarb_tdm_tbl_lr_x[80] = IARB_MAIN_TDM__TDM_SLOT_RDB_PORT; 370 for (i = 81; i < 95; i++) { 371 if ((i-81)%2 == 0) { 372 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 373 } else { 374 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 375 } 376 } 377 iarb_tdm_tbl_lr_x[95] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 378 for (i = 96; i < 112; i++) { 379 if ((i-96)%2 == 0) { 380 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 381 } else { 382 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 383 } 384 } 385 iarb_tdm_tbl_lr_x[112] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 386 for (i = 113; i < 127; i++) { 387 if ((i-113)%2 == 0) { 388 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 389 } else { 390 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 391 } 392 } 393 iarb_tdm_tbl_lr_x[127] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 394 iarb_tdm_tbl_lr_x[128] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 395 396 /* Then check for management ports. */ 397 /* NAK, Not suppoted in AP Iarb. management ports are scheduled with regular ports in PGW".*/ 398 break; 399 case 260 : 400 *iarb_tdm_wrap_ptr_lr_x = 109; 401 402 iarb_tdm_tbl_lr_x[0] = IARB_MAIN_TDM__TDM_SLOT_RDB_PORT; 403 for (i = 1; i < 10; i++) { 404 if (i%2 == 0) { 405 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 406 } else { 407 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 408 } 409 } 410 iarb_tdm_tbl_lr_x[10] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 411 for (i = 11; i < 20; i++) { 412 if (i%2 == 0) { 413 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 414 } else { 415 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 416 } 417 } 418 iarb_tdm_tbl_lr_x[20] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 419 for (i = 21; i < 31; i++) { 420 if (i%2 == 0) { 421 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 422 } else { 423 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 424 } 425 } 426 iarb_tdm_tbl_lr_x[31] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 427 for (i = 32; i < 41; i++) { 428 if (i%2 == 0) { 429 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 430 } else { 431 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 432 } 433 } 434 iarb_tdm_tbl_lr_x[41] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 435 for (i = 42; i < 53; i++) { 436 if (i%2 == 0) { 437 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 438 } else { 439 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 440 } 441 } 442 iarb_tdm_tbl_lr_x[53] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 443 for (i = 54; i < 65; i++) { 444 if (i%2 == 0) { 445 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 446 } else { 447 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 448 } 449 } 450 iarb_tdm_tbl_lr_x[65] = IARB_MAIN_TDM__TDM_SLOT_RDB_PORT; 451 for (i = 66; i < 75; i++) { 452 if (i%2 == 0) { 453 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 454 } else { 455 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 456 } 457 } 458 iarb_tdm_tbl_lr_x[75] = IARB_MAIN_TDM__TDM_SLOT_EP_LOOPBACK; 459 for (i = 76; i < 85; i++) { 460 if (i%2 == 0) { 461 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 462 } else { 463 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 464 } 465 } 466 iarb_tdm_tbl_lr_x[85] = IARB_MAIN_TDM__TDM_SLOT_AUX_OPS_SLOT; 467 for (i = 86; i < 95; i++) { 468 if (i%2 == 0) { 469 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 470 } else { 471 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 472 } 473 } 474 iarb_tdm_tbl_lr_x[95] = IARB_MAIN_TDM__TDM_SLOT_CMIC_PORT; 475 for (i = 96; i < 110; i++) { 476 if (i%2 == 0) { 477 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_0; 478 } else { 479 iarb_tdm_tbl_lr_x[i] = IARB_MAIN_TDM__TDM_SLOT_PGW_1; 480 } 481 } 482 483 /* Then check for management ports. */ 484 /* NAK, Not suppoted in AP Iarb. management ports are scheduled with regular ports in PGW".*/ 485 break; 486 } 487 } 488 489 490 /** 491 @name: set_iarb_tdm_table 492 @param: int, int, int, int, int, int, int*, int*, int[512], int[512] 493 494 IARB TDM Schedule Generator: 495 Return => 1 if error, 0 otherwise. 496 Input 1 => Core bandwidth - 960/720/640/480. 497 Input 2 => 1 if X-pipe is oversub, 0 otherwise. 498 Input 3 => 1 if Y-pipe is oversub, 0 otherwise. 499 Input 4 => 1 if there are 4x1G management ports, 0 otherwise. 500 Input 5 => 1 if there are 4x2.5G management ports, 0 otherwise. 501 Input 6 => 1 if there are 1x10G management port, 0 otherwise. 502 Output 7 => The X-pipe TDM table wrap pointer value. 503 Output 8 => The Y-pipe TDM table wrap pointer value. 504 Output 9 => The X-pipe TDM schedule. 505 Output 10 => The Y-pipe TDM schedule. 506 */ 507 int tdm_ap_set_iarb_tdm (int core_bw, int is_x_ovs, int *iarb_tdm_wrap_ptr_x, int *iarb_tdm_tbl_x) 508 { 509 /* #if ( defined(_SET_TDM_DV) || defined(_SET_TDM_DEV) ) */ 510 int i; 511 int is_succ; 512 int iarb_tdm_wrap_ptr_lr_x; 513 int *iarb_tdm_tbl_lr_x; 514 iarb_tdm_tbl_lr_x = (int *) TDM_ALLOC(sizeof(int) * 512, "iarb_tdm_tbl_lr_x"); 515 /* #else 516 int i; 517 int is_succ; 518 int iarb_tdm_wrap_ptr_ovs_x, iarb_tdm_wrap_ptr_ovs_y; 519 int iarb_tdm_wrap_ptr_lr_x, iarb_tdm_wrap_ptr_lr_y; 520 TDM_ALLOC(iarb_tdm_tbl_ovs_x, int, 512, "iarb_tdm_tbl_ovs_x"); 521 TDM_ALLOC(iarb_tdm_tbl_ovs_y, int, 512, "iarb_tdm_tbl_ovs_y"); 522 TDM_ALLOC(iarb_tdm_tbl_lr_x, int, 512, "iarb_tdm_tbl_lr_x"); 523 TDM_ALLOC(iarb_tdm_tbl_lr_y, int, 512, "iarb_tdm_tbl_lr_y"); 524 #endif */ 525 526 /* 527 Initial IARB TDM table containers - to be copied into final container based 528 on the TDM selected. 529 */ 530 531 /*if (!(!mgm4x1 && !mgm4x2p5 && !mgm1x10) && !(mgm4x1 ^ mgm4x2p5 ^ mgm1x10)) { 532 TDM_ERROR0("Multiple management port settings specified!\n"); 533 } */ 534 535 tdm_ap_init_iarb_tdm_table(core_bw, &iarb_tdm_wrap_ptr_lr_x, iarb_tdm_tbl_lr_x); 536 537 /* The following TDMs have linerate X-pipe and linerate Y-pipe. */ 538 *iarb_tdm_wrap_ptr_x = iarb_tdm_wrap_ptr_lr_x; 539 memcpy(iarb_tdm_tbl_x, iarb_tdm_tbl_lr_x, sizeof(int) * 512); 540 541 542 543 TDM_PRINT1("iarb_tdm_wrap_ptr_x = %d\n",*iarb_tdm_wrap_ptr_x); 544 for (i = 0; i <= *iarb_tdm_wrap_ptr_x; i++) { 545 TDM_PRINT2("iarb_tdm_tbl_x[%d] = %d\n",i,iarb_tdm_tbl_x[i]); 546 } 547 548 549 /* Always succeeds by definition. */ 550 is_succ = 1; 551 TDM_FREE(iarb_tdm_tbl_lr_x); 552 return is_succ; 553 }