shadow.c (261577B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: shadow.c 8 * Purpose: 9 * Requires: 10 */ 11 12 13 #include <sal/core/boot.h> 14 #include <shared/bsl.h> 15 #include <soc/drv.h> 16 #include <soc/mem.h> 17 #include <soc/lpm.h> 18 #include <soc/error.h> 19 #include <soc/debug.h> 20 21 #ifdef BCM_SHADOW_SUPPORT 22 #include <soc/shadow.h> 23 24 /* 25 * shadow chip driver functions. 26 */ 27 soc_functions_t soc_shadow_drv_funs = { 28 soc_shadow_misc_init, 29 soc_shadow_mmu_init, 30 soc_shadow_age_timer_get, 31 soc_shadow_age_timer_max_get, 32 soc_shadow_age_timer_set, 33 }; 34 35 static uint32 iptdm5[30] = {1,9,5,13,31,1,9,5,13,31, 36 1,9,5,13,0,1,9,5,13,31, 37 1,9,5,13,31,1,9,5,13,31}; 38 39 static uint32 mmutdm5[30] = {2,7680,32,122880,0,2,7680,32,122880,0, 40 2,7680,32,122880,1,2,7680,32,122880,0, 41 2,7680,32,122880,0,2,7680,32,122880,0}; 42 43 static uint32 iptdm6[30] = {1,9,5,13,0,1,9,5,13,31, 44 1,9,5,13,0,0,0,0,0,0, 45 0,0,0,0,0,0,0,0,0,0}; 46 47 static uint32 mmutdm6[30] = {2,130560,32,0,0,2,130560,32,0,0, 48 2,130560,32,0,1,2,130560,32,0,0, 49 2,130560,32,0,0,2,130560,32,0,0}; 50 51 static uint32 iptdm7[60] = {1,9,5,13,31,2,9,6,13,31, 52 3,9,7,13,0,4,9,8,13,31, 53 1,9,5,13,31,2,9,6,13,31, 54 3,9,7,13,31,4,9,8,13,31, 55 1,9,5,13,0,2,9,6,13,31, 56 3,9,7,13,31,4,9,8,13,31}; 57 58 static uint32 mmutdm7[60] = {2,7680,32,122880,0,4,7680,64,122880,0, 59 8,7680,128,122880,1,16,7680,256,122880,0, 60 2,7680,32,122880,0,4,7680,64,122880,0, 61 8,7680,128,122880,0,16,7680,256,122880,0, 62 2,7680,32,122880,1,4,7680,64,122880,0, 63 8,7680,128,122880,0,16,7680,256,122880,0}; 64 65 static uint32 iptdm8[60] = {1, 9, 5, 13, 0, 2, 9, 6, 13, 0x1f, 66 3, 9, 7, 13, 0, 4, 9, 8, 13, 0x1f, 67 1, 9, 5, 13, 0, 2, 9, 6, 13, 0x1f, 68 3, 9, 7, 13, 0, 4, 9, 8, 13, 0x1f, 69 1, 9, 5, 13, 0, 2, 9, 6, 13, 0x1f, 70 3, 9, 7, 13, 0, 4, 9, 8, 13, 0x1f}; 71 72 static uint32 mmutdm8[60] = {2,130560,32,0,0,4,130560,64,0,0, 73 8,130560,128,0,1,16,130560,256,0,0, 74 2,130560,32,0,0,4,130560,64,0,0, 75 8,130560,128,0,0,16,130560,256,0,0, 76 2,130560,32,0,1,4,130560,64,0,0, 77 8,130560,128,0,0,16,130560,256,0,0}; 78 79 static uint32 iptdm9[30] = {1,9,5,13,31,1,9,5,13,31, 80 1,9,5,13,0,1,9,5,13,31, 81 1,9,5,13,31,1,9,5,13,31}; 82 83 static uint32 mmutdm9[30] = {2,512,32,8192,0,2,512,32,8192,0, 84 2,512,32,8192,1,2,512,32,8192,0, 85 2,512,32,8192,0,2,512,32,8192,0}; 86 87 static uint32 iptdm0_xfi[43] = {1, 9, 5, 11, 13, 1, 15, 5, 10, 12, 1, 88 14, 5, 16, 9, 1, 11, 5, 13, 15, 31, 1, 89 10, 5, 12, 14, 1, 16, 5, 9, 11, 1, 13, 90 5, 15, 10, 1, 12, 5, 14, 16, 31, 0}; 91 92 static uint32 mmutdm0_xfi[60] = {2, 512, 32, 8192, 1024, 2, 16384, 32, 2048, 32768, 93 2, 4096, 32, 65536, 0, 2, 512, 32, 8192, 1024, 94 2, 16384, 32, 2048, 32768, 2, 4096, 32, 65536, 0, 95 2, 512, 32, 8192, 1024, 2, 16384, 32, 2048, 32768, 96 2, 4096, 32, 65536, 0, 2, 512, 32, 8192, 1024, 97 2, 16384, 32, 2048, 32768, 2, 4096, 32, 65536, 0}; 98 99 static uint32 iptdm1_xfi[43] = {1,9,5,11,13,2,15,6,10,12, 100 3,14,7,16,9,4,11,8,13,15, 101 31,1,10,5,12,14,2,16,6,9, 102 11,3,13,7,15,10,4,12,8,14, 103 16,31,0}; 104 105 static uint32 mmutdm1_xfi[60] = {2,512,32,8192,1024,4,16384,64,2048,32768, 106 8,4096,128,65536,1,16,512,256,8192,1024, 107 2,16384,32,2048,32768,4,4096,64,65536,0, 108 8,512,128,8192,1024,16,16384,256,2048,32768, 109 2,4096,32,65536,1,4,512,64,8192,1024, 110 8,16384,128,2048,32768,16,4096,256,65536,0}; 111 112 static uint32 iptdm18[31] = {1,9,5,13,31,1,10,5,15,11, 113 1,14,5,12,16,1,9,5,13,31, 114 1,10,5,15,11,1,14,5,12,16,0}; 115 116 static uint32 mmutdm18[30] = {2,512,32,8192,1024,2,16384,32,2048,32768, 117 2,4096,32,65536,1,2,512,32,8192,1024, 118 2,16384,32,2048,32768,2,4096,32,65536,0}; 119 120 static uint32 iptdm19[43] = {1,9,5,11,13,2,15,6,10,12, 121 3,14,7,16,9,4,11,8,13,15, 122 31,1,10,5,12,14,2,16,6,9, 123 11,3,13,7,15,10,4,12,8,14, 124 16,31,0}; 125 126 static uint32 mmutdm19[60] = {2,1536,32,0,24576,4,0,64,6144,0, 127 8,98304,128,0,1,16,1536,256,0,24576, 128 2,0,32,6144,0,4,98304,64,0,0, 129 8,1536,128,0,24576,16,0,256,6144,0, 130 2,98304,32,0,1,4,1536,64,0,24576, 131 8,0,128,6144,0,16,98304,256,0,0}; 132 133 static const soc_reg_t thermal_reg[] = { 134 CMIC_THERMAL_MON_RESULT_0r, CMIC_THERMAL_MON_RESULT_1r, 135 CMIC_THERMAL_MON_RESULT_2r, CMIC_THERMAL_MON_RESULT_3r, 136 CMIC_THERMAL_MON_RESULT_4r, CMIC_THERMAL_MON_RESULT_5r, 137 CMIC_THERMAL_MON_RESULT_6r, CMIC_THERMAL_MON_RESULT_7r 138 }; 139 140 141 static int 142 soc_shadow_pipe_mem_clear(int unit) 143 { 144 uint32 rval; 145 int pipe_init_usec; 146 soc_timeout_t to; 147 148 /* 149 * Reset the IPIPE and EPIPE block 150 */ 151 rval = 0; 152 SOC_IF_ERROR_RETURN(WRITE_ING_HW_RESET_CONTROL_1r(unit, rval)); 153 soc_reg_field_set(unit, ING_HW_RESET_CONTROL_2r, &rval, RESET_ALLf, 1); 154 soc_reg_field_set(unit, ING_HW_RESET_CONTROL_2r, &rval, VALIDf, 1); 155 soc_reg_field_set(unit, ING_HW_RESET_CONTROL_2r, &rval, COUNTf, 156 SOC_IS_SC_CQ(unit) ? 0x8000 : 0x4000); 157 SOC_IF_ERROR_RETURN(WRITE_ING_HW_RESET_CONTROL_2r(unit, rval)); 158 159 rval = 0; 160 SOC_IF_ERROR_RETURN(WRITE_EGR_HW_RESET_CONTROL_0r(unit, rval)); 161 soc_reg_field_set(unit, EGR_HW_RESET_CONTROL_1r, &rval, RESET_ALLf, 1); 162 soc_reg_field_set(unit, EGR_HW_RESET_CONTROL_1r, &rval, VALIDf, 1); 163 soc_reg_field_set(unit, EGR_HW_RESET_CONTROL_1r, &rval, COUNTf, 164 SOC_IS_SC_CQ(unit) ? 0x4000 : 0x2000); 165 SOC_IF_ERROR_RETURN(WRITE_EGR_HW_RESET_CONTROL_1r(unit, rval)); 166 167 /* For simulation, set timeout to 10 sec. Otherwise, timeout = 50 ms */ 168 if (SAL_BOOT_SIMULATION) { 169 pipe_init_usec = 10000000; 170 } else { 171 pipe_init_usec = 50000; 172 } 173 soc_timeout_init(&to, pipe_init_usec, 0); 174 175 /* Wait for IPIPE memory initialization done. */ 176 do { 177 SOC_IF_ERROR_RETURN(READ_ING_HW_RESET_CONTROL_2r(unit, &rval)); 178 if (soc_reg_field_get(unit, ING_HW_RESET_CONTROL_2r, rval, DONEf)) { 179 break; 180 } 181 if (soc_timeout_check(&to)) { 182 LOG_WARN(BSL_LS_SOC_COMMON, 183 (BSL_META_U(unit, 184 "unit %d : ING_HW_RESET timeout\n"), unit)); 185 break; 186 } 187 } while (TRUE); 188 189 /* Wait for EPIPE memory initialization done. */ 190 do { 191 SOC_IF_ERROR_RETURN(READ_EGR_HW_RESET_CONTROL_1r(unit, &rval)); 192 if (soc_reg_field_get(unit, EGR_HW_RESET_CONTROL_1r, rval, DONEf)) { 193 break; 194 } 195 if (soc_timeout_check(&to)) { 196 LOG_WARN(BSL_LS_SOC_COMMON, 197 (BSL_META_U(unit, 198 "unit %d : EGR_HW_RESET timeout\n"), unit)); 199 break; 200 } 201 } while (TRUE); 202 203 rval = 0; 204 SOC_IF_ERROR_RETURN(WRITE_EGR_HW_RESET_CONTROL_1r(unit, rval)); 205 206 return SOC_E_NONE; 207 } 208 209 int 210 soc_shadow_misc_init(int unit) 211 { 212 static const soc_field_t port_field[4] = { 213 PORT0f, PORT1f, PORT2f, PORT3f 214 }; 215 soc_info_t *si; 216 uint32 rval; 217 uint64 reg64; 218 uint32 addr; 219 soc_pbmp_t pbmp; 220 int port, divisor, dividend; 221 uint32 *iparr = NULL, *mmuarr = NULL; 222 int i, idx, ip_tdm_size = 0, mmu_tdm_size = 0; 223 uint16 dev_id; 224 uint8 rev_id; 225 arb_tdm_table_entry_t arb_tdm; 226 es_arb_tdm_table_entry_t es_arb_tdm; 227 int blk, blk_num, bindex; 228 uint32 core_mode, phy_mode; 229 uint8 port_exist[18], port_valid[18]; 230 uint8 active_il = 0; 231 uint8 en40g = 0; 232 int pipe_init_usec; 233 soc_timeout_t to; 234 il_channel_remap0_entry_t remap0; 235 egr_il_channel_map_entry_t egr_map; 236 soc_port_t p; 237 soc_field_t field_ids[1]; 238 uint32 field_values[1]; 239 int prio = 0; 240 int ext_mdio_divisor, ext_mdio_dividend, 241 int_mdio_divisor, int_mdio_dividend, 242 stdma_divisor, stdma_dividend, 243 i2c_divisor, i2c_dividend; 244 245 si = &SOC_INFO(unit); 246 soc_cm_get_id(unit, &dev_id, &rev_id); 247 248 if (!SOC_IS_RELOADING(unit) && !SOC_WARM_BOOT(unit)) { 249 /* Clear IPIPE/EPIPE Memories */ 250 SOC_IF_ERROR_RETURN(soc_shadow_pipe_mem_clear(unit)); 251 } 252 253 SOC_IF_ERROR_RETURN(READ_MISCCONFIGr(unit, &rval)); 254 soc_reg_field_set(unit, MISCCONFIGr, &rval, 255 METERING_CLK_ENf, 1); 256 SOC_IF_ERROR_RETURN(WRITE_MISCCONFIGr(unit, rval)); 257 258 #ifdef BCM_HB_GW_SUPPORT 259 if (soc_reg_field_valid(unit, CMIC_XGXS0_PLL_CONTROL_2r, 260 XGPLL_EN125f)) { 261 SOC_IF_ERROR_RETURN(READ_CMIC_XGXS0_PLL_CONTROL_2r(unit, &rval)); 262 soc_reg_field_set(unit, CMIC_XGXS0_PLL_CONTROL_2r, &rval, 263 XGPLL_EN125f, 1); 264 SOC_IF_ERROR_RETURN(WRITE_CMIC_XGXS0_PLL_CONTROL_2r(unit, rval)); 265 } 266 #endif 267 268 /* Take temp and votlage monitors out of powerdown and reset */ 269 SOC_IF_ERROR_RETURN(READ_CMIC_THERMAL_MON_CTRLr(unit, &rval)); 270 soc_reg_field_set(unit, CMIC_THERMAL_MON_CTRLr, &rval, BG_ADJf, 2); 271 soc_reg_field_set(unit, CMIC_THERMAL_MON_CTRLr, &rval, PWDNf, 0); 272 soc_reg_field_set(unit, CMIC_THERMAL_MON_CTRLr, &rval, RESETBf, 0); 273 WRITE_CMIC_THERMAL_MON_CTRLr(unit, rval); 274 soc_reg_field_set(unit, CMIC_THERMAL_MON_CTRLr, &rval, RESETBf, 1); 275 WRITE_CMIC_THERMAL_MON_CTRLr(unit, rval); 276 277 278 /* To get 125/25MHz clocks to internal MAC */ 279 SOC_IF_ERROR_RETURN(READ_CMIC_XGXS0_PLL_CONTROL_1r(unit, &rval)); 280 rval |= 1; 281 SOC_IF_ERROR_RETURN(WRITE_CMIC_XGXS0_PLL_CONTROL_1r(unit, rval)); 282 283 /* coverity[result_independent_of_operands] */ 284 SOC_IF_ERROR_RETURN(READ_CMIC_XGXS1_PLL_CONTROL_1r(unit, &rval)); 285 rval |= 1; 286 /* coverity[result_independent_of_operands] */ 287 SOC_IF_ERROR_RETURN(WRITE_CMIC_XGXS1_PLL_CONTROL_1r(unit, rval)); 288 289 if (soc_property_get(unit, spn_BCM_STAT_FLAGS, 0)) { 290 SOC_IF_ERROR_RETURN 291 (soc_reg_field32_modify(unit, IARB_HW_CONTROLr, REG_PORT_ANY, 292 XGS_COUNTER_COMPAT_MODEf, 1)); 293 SOC_IF_ERROR_RETURN 294 (soc_reg_field32_modify(unit, IPARS_HW_CONTROLr, REG_PORT_ANY, 295 XGS_COUNTER_COMPAT_MODEf, 1)); 296 SOC_IF_ERROR_RETURN 297 (soc_reg_field32_modify(unit, ISW1_HW_CONTROLr, REG_PORT_ANY, 298 XGS_COUNTER_COMPAT_MODEf, 1)); 299 SOC_IF_ERROR_RETURN 300 (soc_reg_field32_modify(unit, IFP_HW_CONTROLr, REG_PORT_ANY, 301 XGS_COUNTER_COMPAT_MODEf, 1)); 302 SOC_IF_ERROR_RETURN 303 (soc_reg_field32_modify(unit, ISW2_HW_CONTROLr, REG_PORT_ANY, 304 XGS_COUNTER_COMPAT_MODEf, 1)); 305 SOC_IF_ERROR_RETURN 306 (soc_reg_field32_modify(unit, EGR_HW_CONTROLr, REG_PORT_ANY, 307 XGS_COUNTER_COMPAT_MODEf, 1)); 308 SOC_IF_ERROR_RETURN 309 (soc_reg_field32_modify(unit, EGR_EDB_HW_CONTROLr, REG_PORT_ANY, 310 XGS_COUNTER_COMPAT_MODEf, 1)); 311 } 312 313 if (soc_property_get(unit, spn_BCM88732_2X40_2X40, 0)) { 314 ip_tdm_size = mmu_tdm_size = 30; 315 iparr = iptdm5; 316 mmuarr = mmutdm5; 317 rval = 0x5; /* SPEED = 40G, ENABLE = 1 */ 318 SOC_IF_ERROR_RETURN(WRITE_PORT_CONFIG0r(unit, rval)); 319 SOC_IF_ERROR_RETURN(WRITE_PORT_CONFIG1r(unit, rval)); 320 rval = 0x7; /* SPEED = IL50G, ENABLE = 1 */ 321 SOC_IF_ERROR_RETURN(WRITE_PORT_CONFIG2r(unit, rval)); 322 SOC_IF_ERROR_RETURN(WRITE_PORT_CONFIG3r(unit, rval)); 323 active_il = 2; 324 en40g = 1; 325 326 for (idx = 0; idx <= 7; idx ++) { 327 sal_memset(&remap0, 0, sizeof(remap0)); 328 soc_IL_CHANNEL_REMAP0m_field32_set(unit, &remap0, PORT_NUMf, 9); 329 soc_IL_CHANNEL_REMAP0m_field32_set(unit, &remap0, COSf, idx); 330 SOC_IF_ERROR_RETURN 331 (WRITE_IL_CHANNEL_REMAP0m(unit, MEM_BLOCK_ALL, idx, &remap0)); 332 } 333 for (idx = 0; idx <= 63; idx ++) { 334 sal_memset(&egr_map, 0, sizeof(egr_map)); 335 soc_EGR_IL_CHANNEL_MAPm_field32_set(unit, &egr_map, CHANNELf, idx); 336 SOC_IF_ERROR_RETURN 337 (WRITE_EGR_IL_CHANNEL_MAPm(unit, MEM_BLOCK_ALL, idx, &egr_map)); 338 } 339 /* uflow set for Xe0 -> port 10 */ 340 SOC_IF_ERROR_RETURN 341 (soc_reg_field32_modify(unit, UFLOW_PORT_CONTROLr, 1, 342 HASH_MODEf, 0)); 343 SOC_IF_ERROR_RETURN 344 (soc_reg_field32_modify(unit, UFLOW_PORT_CONTROLr, 1, 345 DEST_PORTf, 9)); 346 347 /* uflow set for Xe1 -> port 13 */ 348 SOC_IF_ERROR_RETURN 349 (soc_reg_field32_modify(unit, UFLOW_PORT_CONTROLr, 5, 350 HASH_MODEf, 0)); 351 SOC_IF_ERROR_RETURN 352 (soc_reg_field32_modify(unit, UFLOW_PORT_CONTROLr, 5, 353 DEST_PORTf, 13)); 354 355 /* Static balance for Switch ports : (1->[9,10,11,12] 5->[13,14,15,16]) */ 356 for (p = 9; p <= 16; p++) { 357 idx = ((p-8)/5)?5:1; 358 SOC_IF_ERROR_RETURN 359 (soc_reg_field32_modify(unit, UFLOW_PORT_CONTROLr, p, 360 DEST_PORTf, idx)); 361 } 362 363 } else if (soc_property_get(unit, spn_BCM88732_2X40_1X40, 0)) { 364 ip_tdm_size =15; 365 mmu_tdm_size = 30; 366 iparr = iptdm6; 367 mmuarr = mmutdm6; 368 rval = 0x5; /* SPEED = 40G, ENABLE = 1 */ 369 SOC_IF_ERROR_RETURN(WRITE_PORT_CONFIG0r(unit, rval)); 370 SOC_IF_ERROR_RETURN(WRITE_PORT_CONFIG1r(unit, rval)); 371 rval = 0x7; /* SPEED = IL50G, ENABLE = 1 */ 372 SOC_IF_ERROR_RETURN(WRITE_PORT_CONFIG2r(unit, rval)); 373 rval = 0; /* ENABLE = 0 */ 374 SOC_IF_ERROR_RETURN(WRITE_PORT_CONFIG3r(unit, rval)); 375 active_il = 1; 376 en40g = 1; 377 378 for (idx = 0; idx <= 7; idx ++) { 379 sal_memset(&remap0, 0, sizeof(remap0)); 380 soc_IL_CHANNEL_REMAP0m_field32_set(unit, &remap0, PORT_NUMf, 9); 381 soc_IL_CHANNEL_REMAP0m_field32_set(unit, &remap0, COSf, idx); 382 SOC_IF_ERROR_RETURN 383 (WRITE_IL_CHANNEL_REMAP0m(unit, MEM_BLOCK_ALL, idx, &remap0)); 384 } 385 for (idx = 8; idx <= 15; idx ++) { 386 sal_memset(&remap0, 0, sizeof(remap0)); 387 soc_IL_CHANNEL_REMAP0m_field32_set(unit, &remap0, PORT_NUMf, 13); 388 soc_IL_CHANNEL_REMAP0m_field32_set(unit, &remap0, COSf, (idx - 8)); 389 SOC_IF_ERROR_RETURN 390 (WRITE_IL_CHANNEL_REMAP0m(unit, MEM_BLOCK_ALL, idx, &remap0)); 391 } 392 for (idx = 0; idx <= 63; idx ++) { 393 sal_memset(&egr_map, 0, sizeof(egr_map)); 394 soc_EGR_IL_CHANNEL_MAPm_field32_set(unit, &egr_map, CHANNELf, idx); 395 SOC_IF_ERROR_RETURN 396 (WRITE_EGR_IL_CHANNEL_MAPm(unit, MEM_BLOCK_ALL, idx, &egr_map)); 397 } 398 /* Some XMAC related stuff: this needs to be moved to xmac.c */ 399 PBMP_XE_ITER(unit, p) { 400 SOC_IF_ERROR_RETURN(READ_XMAC_CTRLr(unit, p, ®64)); 401 soc_reg64_field32_set(unit, XMAC_CTRLr, ®64, XLGMII_ALIGN_ENBf, 1); 402 SOC_IF_ERROR_RETURN(WRITE_XMAC_CTRLr(unit, p, reg64)); 403 SOC_IF_ERROR_RETURN(READ_XMAC_TX_CTRLr(unit, p, ®64)); 404 soc_reg64_field32_set(unit, XMAC_TX_CTRLr, ®64, PAD_ENf, 1); 405 SOC_IF_ERROR_RETURN(WRITE_XMAC_TX_CTRLr(unit, p, reg64)); 406 SOC_IF_ERROR_RETURN 407 (soc_reg_field32_modify(unit, XMAC_RX_MAX_SIZEr, p, 408 RX_MAX_SIZEf, 9600)); 409 SOC_IF_ERROR_RETURN 410 (soc_reg_field32_modify(unit, GPORT_CNTMAXSIZEr, p, 411 CNTMAXSIZEf, 9600)); 412 } 413 SOC_IF_ERROR_RETURN 414 (soc_reg_field32_modify(unit, EPC_LINK_BMAPr, REG_PORT_ANY, 415 PORT_BITMAPf, 0x1ffff)); 416 417 } else if (soc_property_get(unit, spn_BCM88732_2X40_2X40E, 0)) { 418 ip_tdm_size = mmu_tdm_size = 30; 419 iparr = iptdm9; 420 mmuarr = mmutdm9; 421 rval = 0x5; /* SPEED = 40G, ENABLE = 1 */ 422 SOC_IF_ERROR_RETURN(WRITE_PORT_CONFIG0r(unit, rval)); 423 SOC_IF_ERROR_RETURN(WRITE_PORT_CONFIG1r(unit, rval)); 424 rval = 0x5; /* SPEED = 40G, ENABLE = 1 */ 425 SOC_IF_ERROR_RETURN(WRITE_PORT_CONFIG2r(unit, rval)); 426 SOC_IF_ERROR_RETURN(WRITE_PORT_CONFIG3r(unit, rval)); 427 en40g = 1; 428 } else if (soc_property_get(unit, spn_BCM88732_2X40_8X10, 0)) { 429 port_tab_entry_t ptab; 430 ip_tdm_size = 43; 431 mmu_tdm_size = 60; 432 iparr = iptdm0_xfi; 433 mmuarr = mmutdm0_xfi; 434 rval = 0x5; /* SPEED = 40G, ENABLE = 1 */ 435 SOC_IF_ERROR_RETURN(WRITE_PORT_CONFIG0r(unit, rval)); 436 SOC_IF_ERROR_RETURN(WRITE_PORT_CONFIG1r(unit, rval)); 437 rval = 0x3; /* SPEED = 20G, ENABLE = 1 */ 438 SOC_IF_ERROR_RETURN(WRITE_PORT_CONFIG2r(unit, rval)); 439 SOC_IF_ERROR_RETURN(WRITE_PORT_CONFIG3r(unit, rval)); 440 SOC_IF_ERROR_RETURN 441 (soc_reg_field32_modify(unit, EGR_PORT_MODEr, REG_PORT_ANY, 442 IX0A_PORT_MODEf, 1)); /* Dual */ 443 SOC_IF_ERROR_RETURN 444 (soc_reg_field32_modify(unit, EGR_PORT_MODEr, REG_PORT_ANY, 445 IX0B_PORT_MODEf, 1)); /* Dual */ 446 SOC_IF_ERROR_RETURN 447 (soc_reg_field32_modify(unit, EGR_PORT_MODEr, REG_PORT_ANY, 448 IX1A_PORT_MODEf, 1)); /* Dual */ 449 SOC_IF_ERROR_RETURN 450 (soc_reg_field32_modify(unit, EGR_PORT_MODEr, REG_PORT_ANY, 451 IX1B_PORT_MODEf, 1)); /* Dual */ 452 en40g = 1; 453 /* Some XMAC related stuff: this needs to be moved to xmac.c */ 454 PBMP_XE_ITER(unit, p) { 455 SOC_IF_ERROR_RETURN(READ_XMAC_CTRLr(unit, p, ®64)); 456 soc_reg64_field32_set(unit, XMAC_CTRLr, ®64, XLGMII_ALIGN_ENBf, 1); 457 SOC_IF_ERROR_RETURN(WRITE_XMAC_CTRLr(unit, p, reg64)); 458 SOC_IF_ERROR_RETURN(READ_XMAC_TX_CTRLr(unit, p, ®64)); 459 soc_reg64_field32_set(unit, XMAC_TX_CTRLr, ®64, PAD_ENf, 1); 460 SOC_IF_ERROR_RETURN(WRITE_XMAC_TX_CTRLr(unit, p, reg64)); 461 } 462 /* Setup Static load balance */ 463 field_ids[0] = DEST_PORT_OFFSETf; 464 for (i = 0; i < 65535; i+=4) { 465 field_values[0] = 8; 466 SOC_IF_ERROR_RETURN 467 (soc_mem_fields32_modify(unit, UFLOW_Am, i, 1, 468 field_ids, field_values)); 469 field_values[0] = 9; 470 SOC_IF_ERROR_RETURN 471 (soc_mem_fields32_modify(unit, UFLOW_Am, i+1, 1, 472 field_ids, field_values)); 473 field_values[0] = 10; 474 SOC_IF_ERROR_RETURN 475 (soc_mem_fields32_modify(unit, UFLOW_Am, i+2, 1, 476 field_ids, field_values)); 477 field_values[0] = 11; 478 SOC_IF_ERROR_RETURN 479 (soc_mem_fields32_modify(unit, UFLOW_Am, i+3, 1, 480 field_ids, field_values)); 481 } 482 /* Configure Port Table to use UFLOW_A */ 483 SOC_IF_ERROR_RETURN( 484 READ_PORT_TABm(unit, MEM_BLOCK_ANY, 5, &ptab)); 485 soc_PORT_TABm_field32_set(unit, &ptab, AGGREGATION_GROUP_SELECTf, 1); 486 SOC_IF_ERROR_RETURN( 487 WRITE_PORT_TABm(unit,MEM_BLOCK_ALL, 5, &ptab)); 488 489 /* UFLOW_PORT reg will use UFLOW_A for load balance */ 490 SOC_IF_ERROR_RETURN 491 (soc_reg_field32_modify(unit, UFLOW_PORT_CONTROLr, 1, 492 DEST_PORTf, 0)); 493 SOC_IF_ERROR_RETURN 494 (soc_reg_field32_modify(unit, UFLOW_PORT_CONTROLr, 1, 495 HASH_MODEf, 1)); 496 497 /* Setup Static load balance for Port 5*/ 498 field_ids[0] = DEST_PORT_OFFSETf; 499 for (i = 0; i < 65535; i+=4) { 500 field_values[0] = 12; 501 SOC_IF_ERROR_RETURN 502 (soc_mem_fields32_modify(unit, UFLOW_Bm, i, 1, 503 field_ids, field_values)); 504 field_values[0] = 13; 505 SOC_IF_ERROR_RETURN 506 (soc_mem_fields32_modify(unit, UFLOW_Bm, i+1, 1, 507 field_ids, field_values)); 508 field_values[0] = 14; 509 SOC_IF_ERROR_RETURN 510 (soc_mem_fields32_modify(unit, UFLOW_Bm, i+2, 1, 511 field_ids, field_values)); 512 field_values[0] = 15; 513 SOC_IF_ERROR_RETURN 514 (soc_mem_fields32_modify(unit, UFLOW_Bm, i+3, 1, 515 field_ids, field_values)); 516 } 517 /* port 5 (xe1) configure uflow_b for static load balancing */ 518 SOC_IF_ERROR_RETURN( 519 READ_PORT_TABm(unit, MEM_BLOCK_ANY, 5, &ptab)); 520 soc_PORT_TABm_field32_set(unit, &ptab, AGGREGATION_GROUP_SELECTf, 1); 521 SOC_IF_ERROR_RETURN( 522 WRITE_PORT_TABm(unit,MEM_BLOCK_ALL, 5, &ptab)); 523 524 /* UFLOW_PORT reg will use UFLOW_A for load balance */ 525 SOC_IF_ERROR_RETURN 526 (soc_reg_field32_modify(unit, UFLOW_PORT_CONTROLr, 5, 527 DEST_PORTf, 0)); 528 SOC_IF_ERROR_RETURN 529 (soc_reg_field32_modify(unit, UFLOW_PORT_CONTROLr, 5, 530 HASH_MODEf, 1)); 531 532 /* For switch link ports (9-12) use port 1 as the destination port */ 533 for (p = 9; p <= 12; p++) { 534 SOC_IF_ERROR_RETURN 535 (soc_reg_field32_modify(unit, UFLOW_PORT_CONTROLr, p, 536 DEST_PORTf, 1)); 537 SOC_IF_ERROR_RETURN 538 (soc_reg_field32_modify(unit, UFLOW_PORT_CONTROLr, p, 539 HASH_MODEf, 0)); 540 } 541 /* For switch link ports (13-16) use port 5 as the destination port */ 542 for (p = 13; p <= 16; p++) { 543 SOC_IF_ERROR_RETURN 544 (soc_reg_field32_modify(unit, UFLOW_PORT_CONTROLr, p, 545 DEST_PORTf, 5)); 546 SOC_IF_ERROR_RETURN 547 (soc_reg_field32_modify(unit, UFLOW_PORT_CONTROLr, p, 548 HASH_MODEf, 0)); 549 } 550 SOC_IF_ERROR_RETURN 551 (soc_reg_field32_modify(unit, EPC_LINK_BMAPr, REG_PORT_ANY, 552 PORT_BITMAPf, 0x1ffff)); 553 } else if (soc_property_get(unit, spn_BCM88732_8X10_8X10, 0)) { 554 ip_tdm_size = 43; 555 mmu_tdm_size = 60; 556 iparr = iptdm1_xfi; 557 mmuarr = mmutdm1_xfi; 558 rval = 0x1; /* SPEED = 10G, ENABLE = 1 */ 559 SOC_IF_ERROR_RETURN(WRITE_PORT_CONFIG0r(unit, rval)); 560 SOC_IF_ERROR_RETURN(WRITE_PORT_CONFIG1r(unit, rval)); 561 rval = 0x3; /* SPEED = 20G, ENABLE = 1 (dual ports) */ 562 SOC_IF_ERROR_RETURN(WRITE_PORT_CONFIG2r(unit, rval)); 563 SOC_IF_ERROR_RETURN(WRITE_PORT_CONFIG3r(unit, rval)); 564 SOC_IF_ERROR_RETURN 565 (soc_reg_field32_modify(unit, EGR_PORT_MODEr, REG_PORT_ANY, 566 IX0A_PORT_MODEf, 1)); /* Dual */ 567 SOC_IF_ERROR_RETURN 568 (soc_reg_field32_modify(unit, EGR_PORT_MODEr, REG_PORT_ANY, 569 IX0B_PORT_MODEf, 1)); /* Dual */ 570 SOC_IF_ERROR_RETURN 571 (soc_reg_field32_modify(unit, EGR_PORT_MODEr, REG_PORT_ANY, 572 IX1A_PORT_MODEf, 1)); /* Dual */ 573 SOC_IF_ERROR_RETURN 574 (soc_reg_field32_modify(unit, EGR_PORT_MODEr, REG_PORT_ANY, 575 IX1B_PORT_MODEf, 1)); /* Dual */ 576 SOC_IF_ERROR_RETURN 577 (soc_reg_field32_modify(unit, EGR_PORT_MODEr, REG_PORT_ANY, 578 MS0_PORT_MODEf, 2)); /* Quad */ 579 SOC_IF_ERROR_RETURN 580 (soc_reg_field32_modify(unit, EGR_PORT_MODEr, REG_PORT_ANY, 581 MS1_PORT_MODEf, 2)); /* Quad */ 582 en40g = 0; 583 /* Some XMAC related stuff: this needs to be moved to xmac.c */ 584 PBMP_XE_ITER(unit, p) { 585 SOC_IF_ERROR_RETURN(READ_XMAC_TX_CTRLr(unit, p, ®64)); 586 soc_reg64_field32_set(unit, XMAC_TX_CTRLr, ®64, PAD_ENf, 1); 587 SOC_IF_ERROR_RETURN(WRITE_XMAC_TX_CTRLr(unit, p, reg64)); 588 } 589 /* Setup Static load balance for Port (one to one mapping) */ 590 for (p = 1; p <= 8; p++) { 591 SOC_IF_ERROR_RETURN 592 (soc_reg_field32_modify(unit, UFLOW_PORT_CONTROLr, p, 593 DEST_PORTf, p+8)); 594 SOC_IF_ERROR_RETURN 595 (soc_reg_field32_modify(unit, UFLOW_PORT_CONTROLr, p, 596 HASH_MODEf, 0)); 597 SOC_IF_ERROR_RETURN 598 (soc_reg_field32_modify(unit, UFLOW_PORT_CONTROLr, p+8, 599 DEST_PORTf, p)); 600 SOC_IF_ERROR_RETURN 601 (soc_reg_field32_modify(unit, UFLOW_PORT_CONTROLr, p+8, 602 HASH_MODEf, 0)); 603 } 604 SOC_IF_ERROR_RETURN 605 (soc_reg_field32_modify(unit, EPC_LINK_BMAPr, REG_PORT_ANY, 606 PORT_BITMAPf, 0x1ffff)); 607 } else if (soc_property_get(unit, spn_BCM88732_8X10_1X40, 0)) { 608 /* 8x10G port-link 1x40G IL */ 609 ip_tdm_size = 60; 610 mmu_tdm_size = 60; 611 iparr = iptdm8; 612 mmuarr = mmutdm8; 613 rval = 0x1; /* SPEED = 10G, ENABLE = 1 */ 614 SOC_IF_ERROR_RETURN(WRITE_PORT_CONFIG0r(unit, rval)); 615 SOC_IF_ERROR_RETURN(WRITE_PORT_CONFIG1r(unit, rval)); 616 rval = 0x7; /* SPEED = IL50G, ENABLE = 1 */ 617 SOC_IF_ERROR_RETURN(WRITE_PORT_CONFIG2r(unit, rval)); 618 rval = 0; /* ENABLE = 0 */ 619 SOC_IF_ERROR_RETURN(WRITE_PORT_CONFIG3r(unit, rval)); 620 active_il = 1; 621 SOC_IF_ERROR_RETURN 622 (soc_reg_field32_modify(unit, EGR_PORT_MODEr, REG_PORT_ANY, 623 MS0_PORT_MODEf, 2)); /* Quad */ 624 SOC_IF_ERROR_RETURN 625 (soc_reg_field32_modify(unit, EGR_PORT_MODEr, REG_PORT_ANY, 626 MS1_PORT_MODEf, 2)); /* Quad */ 627 SOC_IF_ERROR_RETURN 628 (soc_reg_field32_modify(unit, EPC_LINK_BMAPr, REG_PORT_ANY, 629 PORT_BITMAPf, 0x1ffff)); 630 631 for (idx = 0; idx <= 63; idx ++) { 632 sal_memset(&remap0, 0, sizeof(remap0)); 633 soc_IL_CHANNEL_REMAP0m_field32_set(unit, &remap0, PORT_NUMf, 634 9 + idx % 8); 635 soc_IL_CHANNEL_REMAP0m_field32_set(unit, &remap0, COSf, idx % 8); 636 SOC_IF_ERROR_RETURN 637 (WRITE_IL_CHANNEL_REMAP0m(unit, MEM_BLOCK_ALL, idx, &remap0)); 638 } 639 for (idx = 0; idx <= 63; idx ++) { 640 sal_memset(&egr_map, 0, sizeof(egr_map)); 641 soc_EGR_IL_CHANNEL_MAPm_field32_set(unit, &egr_map, CHANNELf, idx); 642 SOC_IF_ERROR_RETURN 643 (WRITE_EGR_IL_CHANNEL_MAPm(unit, MEM_BLOCK_ALL, idx, &egr_map)); 644 } 645 /* Some XMAC related stuff: this needs to be moved to xmac.c */ 646 PBMP_XE_ITER(unit, p) { 647 SOC_IF_ERROR_RETURN(READ_XMAC_TX_CTRLr(unit, p, ®64)); 648 soc_reg64_field32_set(unit, XMAC_TX_CTRLr, ®64, PAD_ENf, 1); 649 SOC_IF_ERROR_RETURN(WRITE_XMAC_TX_CTRLr(unit, p, reg64)); 650 } 651 } else if (soc_property_get(unit, spn_BCM88732_1X40_4X10, 0)) { 652 ip_tdm_size = 31; 653 mmu_tdm_size = 30; 654 iparr = iptdm18; 655 mmuarr = mmutdm18; 656 rval = 0x5; /* SPEED = 40G, ENABLE = 1 */ 657 SOC_IF_ERROR_RETURN(WRITE_PORT_CONFIG0r(unit, rval)); 658 rval = 0x3; /* SPEED = 20G, ENABLE = 1 */ 659 SOC_IF_ERROR_RETURN(WRITE_PORT_CONFIG2r(unit, rval)); 660 SOC_IF_ERROR_RETURN(WRITE_PORT_CONFIG3r(unit, rval)); 661 SOC_IF_ERROR_RETURN 662 (soc_reg_field32_modify(unit, EGR_PORT_MODEr, REG_PORT_ANY, 663 IX0A_PORT_MODEf, 1)); /* Dual */ 664 SOC_IF_ERROR_RETURN 665 (soc_reg_field32_modify(unit, EGR_PORT_MODEr, REG_PORT_ANY, 666 IX0B_PORT_MODEf, 1)); /* Dual */ 667 SOC_IF_ERROR_RETURN 668 (soc_reg_field32_modify(unit, EGR_PORT_MODEr, REG_PORT_ANY, 669 IX1A_PORT_MODEf, 1)); /* Dual */ 670 SOC_IF_ERROR_RETURN 671 (soc_reg_field32_modify(unit, EGR_PORT_MODEr, REG_PORT_ANY, 672 IX1B_PORT_MODEf, 1)); /* Dual */ 673 en40g = 1; 674 SOC_IF_ERROR_RETURN 675 (soc_reg_field32_modify(unit, EPC_LINK_BMAPr, REG_PORT_ANY, 676 PORT_BITMAPf, 0x1ffff)); 677 678 /* Setup Static load balance */ 679 field_ids[0] = DEST_PORT_OFFSETf; 680 for (i = 0; i < 65535; i+=4) { 681 field_values[0] = 8; 682 SOC_IF_ERROR_RETURN 683 (soc_mem_fields32_modify(unit, UFLOW_Am, i, 1, 684 field_ids, field_values)); 685 field_values[0] = 10; 686 SOC_IF_ERROR_RETURN 687 (soc_mem_fields32_modify(unit, UFLOW_Am, i+1, 1, 688 field_ids, field_values)); 689 field_values[0] = 12; 690 SOC_IF_ERROR_RETURN 691 (soc_mem_fields32_modify(unit, UFLOW_Am, i+2, 1, 692 field_ids, field_values)); 693 field_values[0] = 14; 694 SOC_IF_ERROR_RETURN 695 (soc_mem_fields32_modify(unit, UFLOW_Am, i+3, 1, 696 field_ids, field_values)); 697 } 698 /* Configure Port Table to use UFLOW_A */ 699 field_ids[0] = AGGREGATION_GROUP_SELECTf; 700 field_values[0] = 0; 701 SOC_IF_ERROR_RETURN 702 (soc_mem_fields32_modify(unit, PORT_TABm, 1, 1, 703 field_ids, field_values)); 704 705 /* UFLOW_PORT reg will use UFLOW_A for load balance */ 706 SOC_IF_ERROR_RETURN 707 (soc_reg_field32_modify(unit, UFLOW_PORT_CONTROLr, 1, 708 DEST_PORTf, 0)); 709 SOC_IF_ERROR_RETURN 710 (soc_reg_field32_modify(unit, UFLOW_PORT_CONTROLr, 1, 711 HASH_MODEf, 1)); 712 713 /* For switch link ports use port 1 as the destination port */ 714 for (p = 9; p <= 16; p+=2) { 715 SOC_IF_ERROR_RETURN 716 (soc_reg_field32_modify(unit, UFLOW_PORT_CONTROLr, p, 717 DEST_PORTf, 1)); 718 SOC_IF_ERROR_RETURN 719 (soc_reg_field32_modify(unit, UFLOW_PORT_CONTROLr, p, 720 HASH_MODEf, 0)); 721 } 722 } else if (soc_property_get(unit, spn_BCM88732_4X10_4X10, 0)) { 723 ip_tdm_size = 43; 724 mmu_tdm_size = 60; 725 iparr = iptdm19; 726 mmuarr = mmutdm19; 727 rval = 0x1; /* SPEED = 10G, ENABLE = 1 */ 728 SOC_IF_ERROR_RETURN(WRITE_PORT_CONFIG0r(unit, rval)); 729 rval = 0x3; /* SPEED = 20G, ENABLE = 1 */ 730 SOC_IF_ERROR_RETURN(WRITE_PORT_CONFIG2r(unit, rval)); 731 SOC_IF_ERROR_RETURN(WRITE_PORT_CONFIG3r(unit, rval)); 732 SOC_IF_ERROR_RETURN 733 (soc_reg_field32_modify(unit, EGR_PORT_MODEr, REG_PORT_ANY, 734 MS0_PORT_MODEf, 2)); /* Quad */ 735 SOC_IF_ERROR_RETURN 736 (soc_reg_field32_modify(unit, EGR_PORT_MODEr, REG_PORT_ANY, 737 MS1_PORT_MODEf, 2)); /* Quad */ 738 SOC_IF_ERROR_RETURN 739 (soc_reg_field32_modify(unit, EGR_PORT_MODEr, REG_PORT_ANY, 740 IX0A_PORT_MODEf, 1)); /* Dual */ 741 SOC_IF_ERROR_RETURN 742 (soc_reg_field32_modify(unit, EGR_PORT_MODEr, REG_PORT_ANY, 743 IX0B_PORT_MODEf, 1)); /* Dual */ 744 SOC_IF_ERROR_RETURN 745 (soc_reg_field32_modify(unit, EGR_PORT_MODEr, REG_PORT_ANY, 746 IX1A_PORT_MODEf, 1)); /* Dual */ 747 SOC_IF_ERROR_RETURN 748 (soc_reg_field32_modify(unit, EGR_PORT_MODEr, REG_PORT_ANY, 749 IX1B_PORT_MODEf, 1)); /* Dual */ 750 /* Configure load balance */ 751 for (p = 1; p <= 4; p++) { 752 SOC_IF_ERROR_RETURN 753 (soc_reg_field32_modify(unit, UFLOW_PORT_CONTROLr, 1, 754 DEST_PORTf, (8 + (p-1)*2))); 755 SOC_IF_ERROR_RETURN 756 (soc_reg_field32_modify(unit, UFLOW_PORT_CONTROLr, 1, 757 HASH_MODEf, 0)); 758 } 759 760 /* For switch link ports use port 1-4 as the destination port */ 761 rval = 0; 762 for (p = 9; p < 16; p+=2) { 763 SOC_IF_ERROR_RETURN 764 (soc_reg_field32_modify(unit, UFLOW_PORT_CONTROLr, p, 765 DEST_PORTf, rval)); 766 SOC_IF_ERROR_RETURN 767 (soc_reg_field32_modify(unit, UFLOW_PORT_CONTROLr, p, 768 HASH_MODEf, 0)); 769 rval++; 770 } 771 } else { 772 /* 8x10G port-link 2x40G IL - default */ 773 ip_tdm_size = 60; 774 mmu_tdm_size = 60; 775 iparr = iptdm7; 776 mmuarr = mmutdm7; 777 rval = 0x1; /* SPEED = 10G, ENABLE = 1 */ 778 SOC_IF_ERROR_RETURN(WRITE_PORT_CONFIG0r(unit, rval)); 779 SOC_IF_ERROR_RETURN(WRITE_PORT_CONFIG1r(unit, rval)); 780 rval = 0x7; /* SPEED = IL50G, ENABLE = 1 */ 781 SOC_IF_ERROR_RETURN(WRITE_PORT_CONFIG2r(unit, rval)); 782 SOC_IF_ERROR_RETURN(WRITE_PORT_CONFIG3r(unit, rval)); 783 active_il = 2; 784 SOC_IF_ERROR_RETURN 785 (soc_reg_field32_modify(unit, EGR_PORT_MODEr, REG_PORT_ANY, 786 MS0_PORT_MODEf, 2)); /* Quad */ 787 SOC_IF_ERROR_RETURN 788 (soc_reg_field32_modify(unit, EGR_PORT_MODEr, REG_PORT_ANY, 789 MS1_PORT_MODEf, 2)); /* Quad */ 790 791 for (idx = 0; idx <= 31; idx ++) { 792 sal_memset(&remap0, 0, sizeof(remap0)); 793 soc_IL_CHANNEL_REMAP0m_field32_set(unit, &remap0, PORT_NUMf, 794 9 + idx % 8); 795 soc_IL_CHANNEL_REMAP0m_field32_set(unit, &remap0, COSf, idx % 8); 796 SOC_IF_ERROR_RETURN 797 (WRITE_IL_CHANNEL_REMAP0m(unit, MEM_BLOCK_ALL, idx, &remap0)); 798 } 799 for (idx = 0; idx <= 63; idx ++) { 800 sal_memset(&egr_map, 0, sizeof(egr_map)); 801 soc_EGR_IL_CHANNEL_MAPm_field32_set(unit, &egr_map, CHANNELf, idx); 802 SOC_IF_ERROR_RETURN 803 (WRITE_EGR_IL_CHANNEL_MAPm(unit, MEM_BLOCK_ALL, idx, &egr_map)); 804 } 805 } 806 807 /* Program the TDM tables */ 808 for (i = 0; (i < ip_tdm_size) && iparr; i++) { 809 sal_memset(&arb_tdm, 0, sizeof(arb_tdm_table_entry_t)); 810 soc_ARB_TDM_TABLEm_field32_set(unit, &arb_tdm, PORT_NUMf, iparr[i]); 811 if (i == (ip_tdm_size - 1)) { 812 soc_ARB_TDM_TABLEm_field32_set(unit, &arb_tdm, WRAP_ENf, 1); 813 } 814 SOC_IF_ERROR_RETURN(WRITE_ARB_TDM_TABLEm(unit, SOC_BLOCK_ALL, i, 815 &arb_tdm)); 816 } 817 SOC_IF_ERROR_RETURN(WRITE_TDM_ENr(unit, 1)); 818 819 for (i = 0; (i < mmu_tdm_size) && mmuarr; i++) { 820 sal_memset(&es_arb_tdm, 0, sizeof(es_arb_tdm_table_entry_t)); 821 soc_ES_ARB_TDM_TABLEm_field32_set(unit, &es_arb_tdm, PORT_VECTORf, 822 mmuarr[i]); 823 SOC_IF_ERROR_RETURN(WRITE_ES_ARB_TDM_TABLEm(unit, SOC_BLOCK_ALL, i, 824 &es_arb_tdm)); 825 } 826 rval = 0; 827 soc_reg_field_set(unit, ES_TDM_CAL_CFGr, &rval, END_Bf, mmu_tdm_size); 828 soc_reg_field_set(unit, ES_TDM_CAL_CFGr, &rval, END_Af, mmu_tdm_size); 829 SOC_IF_ERROR_RETURN(WRITE_ES_TDM_CAL_CFGr(unit, rval)); 830 SOC_IF_ERROR_RETURN(WRITE_ES_TDM_ENr(unit, 1)); 831 832 /* 833 * Egress Enable 834 */ 835 rval = 0; 836 PBMP_ALL_ITER(unit, port) { 837 soc_reg_field_set(unit, EGR_ENABLEr, &rval, PRT_ENABLEf, 1); 838 if (IS_IL_PORT(unit, port) && (port != 9) && (port != 13)) { 839 /* Second IL port is enabled only in few configurations */ 840 continue; 841 } 842 if ((port == 13) && 843 (soc_property_get(unit, spn_BCM88732_8X10_1X40, 0) || 844 soc_property_get(unit, spn_BCM88732_2X40_1X40, 0)) ) { 845 continue; 846 } 847 if (SOC_PBMP_MEMBER(si->port.disabled_bitmap, port)) { 848 soc_reg_field_set(unit, EGR_ENABLEr, &rval, PRT_ENABLEf, 0); 849 } 850 SOC_IF_ERROR_RETURN(WRITE_EGR_ENABLEr(unit, port, rval)); 851 } 852 853 /* QG ports only */ 854 SOC_PBMP_ASSIGN(pbmp, PBMP_GE_ALL(unit)); 855 SOC_PBMP_REMOVE(pbmp, PBMP_GX_ALL(unit)); 856 /* Clear 8 beat accumulation on QG ports only */ 857 rval = 0; 858 PBMP_ITER(pbmp, port) { 859 SOC_IF_ERROR_RETURN(WRITE_EGR_ACCU_8BEATSr(unit, port, rval)); 860 } 861 862 if (soc_feature(unit, soc_feature_ctr_xaui_activity)) { 863 PBMP_PORT_ITER(unit, port) { 864 break; 865 } 866 addr = soc_reg_addr(unit, XPORT_CONFIGr, port, 0); 867 addr &= ~(0x3F << SOC_REGIDX_BP); 868 869 rval = 0; 870 soc_reg_field_set(unit, XPORT_CONFIGr, &rval, XPORT_ENf, 1); 871 /* 872 * For correct LED operation, XPORT must be enabled also on 873 * all unused ports, however the soc_reg_addr function only 874 * works on valid ports, so the registers address must be 875 * calculated 'manually'. 876 */ 877 for (port = 0; port < 20; port++) { 878 if (!SOC_PORT_VALID(unit, port)) { 879 SOC_IF_ERROR_RETURN(soc_reg32_write(unit, 880 addr | (port << SOC_REGIDX_BP), rval)); 881 } 882 } 883 } 884 885 /* 886 * ING_CONFIG 887 */ 888 SOC_IF_ERROR_RETURN(READ_ING_CONFIG_64r(unit, ®64)); 889 soc_reg64_field32_set(unit, ING_CONFIG_64r, ®64, 890 ARP_RARP_TO_FPf, 0x3); 891 SOC_IF_ERROR_RETURN(WRITE_ING_CONFIG_64r(unit, reg64)); 892 893 rval = 0x01; /* 125KHz I2C sampling rate */ 894 SOC_IF_ERROR_RETURN(WRITE_CMIC_I2C_STATr(unit, rval)); 895 896 897 /* 898 * Premises of the calculation: 899 * 900 * Core clock speed 901 * 56820 (220 MHz) 902 * 56821/56720/56721 (225 MHz) 903 * 56822/56823/56725 (245 MHz) 904 * 56825 (290 MHz) 905 * 906 * EXT_MDIO result = INT_MDIO result = 5 MHz 907 * I2C result / (2 * 10) = 250-400 kHz 908 * I2C result = 5-8 MHz 909 * STDMA result = 25 MHz 910 * 911 * result = core * dividend / divisor 912 * ==> 913 * dividend : divisor = result : core 914 */ 915 916 switch (dev_id) { 917 case BCM88732_DEVICE_ID: 918 ext_mdio_dividend = 1; 919 ext_mdio_divisor = 44; 920 int_mdio_dividend = 1; 921 int_mdio_divisor = 44; 922 stdma_dividend = 1; 923 stdma_divisor = 9; 924 i2c_dividend = 1; 925 i2c_divisor = 40; 926 break; 927 default: 928 return SOC_E_UNAVAIL; 929 } 930 931 divisor = soc_property_get(unit, spn_RATE_EXT_MDIO_DIVISOR, 932 ext_mdio_divisor); 933 dividend = soc_property_get(unit, spn_RATE_EXT_MDIO_DIVIDEND, 934 ext_mdio_dividend); 935 rval = 0; 936 soc_reg_field_set(unit, CMIC_RATE_ADJUSTr, &rval, 937 DIVISORf, divisor); 938 soc_reg_field_set(unit, CMIC_RATE_ADJUSTr, &rval, 939 DIVIDENDf, dividend); 940 SOC_IF_ERROR_RETURN(WRITE_CMIC_RATE_ADJUSTr(unit, rval)); 941 942 divisor = soc_property_get(unit, spn_RATE_INT_MDIO_DIVISOR, 943 int_mdio_divisor); 944 dividend = soc_property_get(unit, spn_RATE_INT_MDIO_DIVIDEND, 945 int_mdio_dividend); 946 rval = 0; 947 soc_reg_field_set(unit, CMIC_RATE_ADJUST_INT_MDIOr, &rval, 948 DIVISORf, divisor); 949 soc_reg_field_set(unit, CMIC_RATE_ADJUST_INT_MDIOr, &rval, 950 DIVIDENDf, dividend); 951 SOC_IF_ERROR_RETURN(WRITE_CMIC_RATE_ADJUST_INT_MDIOr(unit, rval)); 952 953 divisor = soc_property_get(unit, spn_RATE_I2C_DIVISOR, 954 i2c_divisor); 955 dividend = soc_property_get(unit, spn_RATE_I2C_DIVIDEND, 956 i2c_dividend); 957 rval = 0; 958 soc_reg_field_set(unit, CMIC_RATE_ADJUST_I2Cr, &rval, 959 DIVISORf, divisor); 960 soc_reg_field_set(unit, CMIC_RATE_ADJUST_I2Cr, &rval, 961 DIVIDENDf, dividend); 962 SOC_IF_ERROR_RETURN(WRITE_CMIC_RATE_ADJUST_I2Cr(unit, rval)); 963 964 divisor = soc_property_get(unit, spn_RATE_STDMA_DIVISOR, 965 stdma_divisor); 966 dividend = soc_property_get(unit, spn_RATE_STDMA_DIVIDEND, 967 stdma_dividend); 968 rval = 0; 969 soc_reg_field_set(unit, CMIC_RATE_ADJUST_STDMAr, &rval, 970 DIVISORf, divisor); 971 soc_reg_field_set(unit, CMIC_RATE_ADJUST_STDMAr, &rval, 972 DIVIDENDf, dividend); 973 SOC_IF_ERROR_RETURN(WRITE_CMIC_RATE_ADJUST_STDMAr(unit, rval)); 974 975 976 SOC_IF_ERROR_RETURN(READ_MISCCONFIGr(unit, &rval)); 977 soc_reg_field_set(unit, MISCCONFIGr, &rval, PARITY_STAT_CLEARf, 1); 978 SOC_IF_ERROR_RETURN(WRITE_MISCCONFIGr(unit, rval)); 979 980 soc_reg_field_set(unit, MISCCONFIGr, &rval, PARITY_STAT_CLEARf, 0); 981 SOC_IF_ERROR_RETURN(WRITE_MISCCONFIGr(unit, rval)); 982 983 984 /* Initialize the Interlaken blocks */ 985 if (SAL_BOOT_SIMULATION) { 986 pipe_init_usec = 40000000; 987 } else { 988 pipe_init_usec = 50000; 989 } 990 soc_timeout_init(&to, pipe_init_usec, 0); 991 992 switch (active_il) { 993 case 1: 994 SOC_IF_ERROR_RETURN(READ_OP_EP_PORT_MAPPING_TABLE_1r(unit, &rval)); 995 soc_reg_field_set(unit, OP_EP_PORT_MAPPING_TABLE_1r, &rval, 996 PORT10_MAPPINGf, 0x9); 997 soc_reg_field_set(unit, OP_EP_PORT_MAPPING_TABLE_1r, &rval, 998 PORT11_MAPPINGf, 0x9); 999 soc_reg_field_set(unit, OP_EP_PORT_MAPPING_TABLE_1r, &rval, 1000 PORT12_MAPPINGf, 0x9); 1001 SOC_IF_ERROR_RETURN(WRITE_OP_EP_PORT_MAPPING_TABLE_1r(unit, rval)); 1002 1003 rval = 0; 1004 soc_reg_field_set(unit, IL_GLOBAL_CONTROLr, &rval, SOFT_RESETf, 0); 1005 soc_reg_field_set(unit, IL_GLOBAL_CONTROLr, &rval, WC_CONFIG_IL_ENf, 1); 1006 soc_reg_field_set(unit, IL_GLOBAL_CONTROLr, &rval, 1007 WC_CONFIG_IL_MODEf, 1); 1008 SOC_IF_ERROR_RETURN(WRITE_IL_GLOBAL_CONTROLr(unit, 9, rval)); 1009 /* Need to reset only after Warpcores are initialized */ 1010 SOC_IF_ERROR_RETURN 1011 (soc_reg_field32_modify(unit, IL_GLOBAL_CONTROLr, 9, SOFT_RESETf, 1)); 1012 1013 rval = 0; 1014 soc_reg_field_set(unit, IL_MEMORY_INITr, &rval, INIT_MEM0f, 1); 1015 soc_reg_field_set(unit, IL_MEMORY_INITr, &rval, INIT_MEM1f, 1); 1016 soc_reg_field_set(unit, IL_MEMORY_INITr, &rval, INIT_MEM2f, 1); 1017 soc_reg_field_set(unit, IL_MEMORY_INITr, &rval, INIT_MEM3f, 1); 1018 soc_reg_field_set(unit, IL_MEMORY_INITr, &rval, INIT_MEM4f, 1); 1019 SOC_IF_ERROR_RETURN(WRITE_IL_MEMORY_INITr(unit, 9, rval)); 1020 do { 1021 SOC_IF_ERROR_RETURN(READ_IL_MEMORY_INIT_DONEr(unit, 9, &rval)); 1022 if (soc_reg_field_get(unit, IL_MEMORY_INIT_DONEr, rval, INIT_DONE_MEM0f) && 1023 soc_reg_field_get(unit, IL_MEMORY_INIT_DONEr, rval, INIT_DONE_MEM1f) && 1024 soc_reg_field_get(unit, IL_MEMORY_INIT_DONEr, rval, INIT_DONE_MEM2f) && 1025 soc_reg_field_get(unit, IL_MEMORY_INIT_DONEr, rval, INIT_DONE_MEM3f) && 1026 soc_reg_field_get(unit, IL_MEMORY_INIT_DONEr, rval, INIT_DONE_MEM4f)) { 1027 break; 1028 } 1029 if (soc_timeout_check(&to)) { 1030 LOG_WARN(BSL_LS_SOC_COMMON, 1031 (BSL_META_U(unit, 1032 "unit %d : IL_MEMORY_INIT_DONE timeout\n"), unit)); 1033 break; 1034 } 1035 } while (TRUE); 1036 1037 /* Need to take out of reset only after Warpcores are initialized */ 1038 SOC_IF_ERROR_RETURN 1039 (soc_reg_field32_modify(unit, IL_GLOBAL_CONTROLr, 9, SOFT_RESETf, 1)); 1040 1041 SOC_IF_ERROR_RETURN 1042 (soc_reg_field32_modify(unit, EGR_PORT_MODEr, REG_PORT_ANY, 1043 IL0_ENf, 1)); 1044 SOC_IF_ERROR_RETURN 1045 (soc_reg_field32_modify(unit, IL_GLOBAL_CONFIGr, 9, 1046 CFG_TX_WC_BITFLIPf, 1)); 1047 SOC_IF_ERROR_RETURN 1048 (soc_reg_field32_modify(unit, IL_GLOBAL_CONFIGr, 9, 1049 CFG_RX_WC_BITFLIPf, 1)); 1050 1051 /* Configure IL Counters in accumulate mode;default is read on clear */ 1052 if (soc_property_get(unit, spn_BCM_STAT_FLAGS, 0)) { 1053 SOC_IF_ERROR_RETURN 1054 (soc_reg_field32_modify(unit, IL_GLOBAL_CONFIGr, 9, 1055 XGS_COUNTER_COMPAT_MODEf, 1)); 1056 } 1057 1058 /* Set Inband flow control, reset val(0x1) is OOB for shadow */ 1059 if (soc_property_get(unit, spn_BCM88732_USE_OOB, 0)) { 1060 SOC_IF_ERROR_RETURN 1061 (soc_reg_field32_modify(unit, IL_GLOBAL_CONFIGr, 9, 1062 CFG_FLOWCONTROL_TYPEf, 1)); 1063 } else { 1064 SOC_IF_ERROR_RETURN 1065 (soc_reg_field32_modify(unit, IL_GLOBAL_CONFIGr, 9, 1066 CFG_FLOWCONTROL_TYPEf, 0)); 1067 } 1068 1069 /* Set lane for 16lane support */ 1070 if (soc_property_get(unit, "IL3125", 0)) { 1071 SOC_IF_ERROR_RETURN 1072 (soc_reg_field32_modify(unit, IL_RX_CORE_CONFIG1r, 9, 1073 CTL_RX_LAST_LANEf, 15)); 1074 SOC_IF_ERROR_RETURN 1075 (soc_reg_field32_modify(unit, IL_TX_CORE_CONFIG2r, 9, 1076 CTL_TX_LAST_LANEf, 15)); 1077 /* 1078 * Need to set WC_CONFIG_IL for IL1 in 16 lane mode as SERDES MUX 1079 * is contorolled by IL1 1080 */ 1081 soc_reg_field_set(unit, IL_GLOBAL_CONTROLr, &rval, SOFT_RESETf, 0); 1082 soc_reg_field_set(unit, IL_GLOBAL_CONTROLr, &rval, WC_CONFIG_IL_ENf, 1); 1083 soc_reg_field_set(unit, IL_GLOBAL_CONTROLr, &rval, WC_CONFIG_CHANNEL_SELf, 0); 1084 soc_reg_field_set(unit, IL_GLOBAL_CONTROLr, &rval, WC_CONFIG_BROADCAST_ENf, 0); 1085 soc_reg_field_set(unit, IL_GLOBAL_CONTROLr, &rval, WC_CONFIG_IL_MODEf, 1); 1086 SOC_IF_ERROR_RETURN(WRITE_IL_GLOBAL_CONTROLr(unit, 13, rval)); 1087 1088 } 1089 break; 1090 case 2: 1091 SOC_IF_ERROR_RETURN(READ_OP_EP_PORT_MAPPING_TABLE_1r(unit, &rval)); 1092 soc_reg_field_set(unit, OP_EP_PORT_MAPPING_TABLE_1r, &rval, 1093 PORT10_MAPPINGf, 0x9); 1094 soc_reg_field_set(unit, OP_EP_PORT_MAPPING_TABLE_1r, &rval, 1095 PORT11_MAPPINGf, 0x9); 1096 soc_reg_field_set(unit, OP_EP_PORT_MAPPING_TABLE_1r, &rval, 1097 PORT12_MAPPINGf, 0x9); 1098 SOC_IF_ERROR_RETURN(WRITE_OP_EP_PORT_MAPPING_TABLE_1r(unit, rval)); 1099 SOC_IF_ERROR_RETURN(READ_OP_EP_PORT_MAPPING_TABLE_2r(unit, &rval)); 1100 soc_reg_field_set(unit, OP_EP_PORT_MAPPING_TABLE_2r, &rval, 1101 PORT14_MAPPINGf, 0xd); 1102 soc_reg_field_set(unit, OP_EP_PORT_MAPPING_TABLE_2r, &rval, 1103 PORT15_MAPPINGf, 0xd); 1104 soc_reg_field_set(unit, OP_EP_PORT_MAPPING_TABLE_2r, &rval, 1105 PORT16_MAPPINGf, 0xd); 1106 SOC_IF_ERROR_RETURN(WRITE_OP_EP_PORT_MAPPING_TABLE_2r(unit, rval)); 1107 1108 rval = 0; 1109 soc_reg_field_set(unit, IL_GLOBAL_CONTROLr, &rval, SOFT_RESETf, 1); 1110 soc_reg_field_set(unit, IL_GLOBAL_CONTROLr, &rval, WC_CONFIG_IL_ENf, 1); 1111 SOC_IF_ERROR_RETURN(WRITE_IL_GLOBAL_CONTROLr(unit, 9, rval)); 1112 SOC_IF_ERROR_RETURN(WRITE_IL_GLOBAL_CONTROLr(unit, 13, rval)); 1113 rval = 0; 1114 /* Need to take out of reset only after Warpcores are initialized */ 1115 SOC_IF_ERROR_RETURN 1116 (soc_reg_field32_modify(unit, IL_GLOBAL_CONTROLr, 9, SOFT_RESETf, 1117 0)); 1118 SOC_IF_ERROR_RETURN 1119 (soc_reg_field32_modify(unit, IL_GLOBAL_CONTROLr, 13, SOFT_RESETf, 1120 0)); 1121 1122 soc_reg_field_set(unit, IL_MEMORY_INITr, &rval, INIT_MEM0f, 1); 1123 soc_reg_field_set(unit, IL_MEMORY_INITr, &rval, INIT_MEM1f, 1); 1124 soc_reg_field_set(unit, IL_MEMORY_INITr, &rval, INIT_MEM2f, 1); 1125 soc_reg_field_set(unit, IL_MEMORY_INITr, &rval, INIT_MEM3f, 1); 1126 soc_reg_field_set(unit, IL_MEMORY_INITr, &rval, INIT_MEM4f, 1); 1127 SOC_IF_ERROR_RETURN(WRITE_IL_MEMORY_INITr(unit, 9, rval)); 1128 SOC_IF_ERROR_RETURN(WRITE_IL_MEMORY_INITr(unit, 13, rval)); 1129 do { 1130 SOC_IF_ERROR_RETURN(READ_IL_MEMORY_INIT_DONEr(unit, 9, &rval)); 1131 if (soc_reg_field_get(unit, IL_MEMORY_INIT_DONEr, rval, INIT_DONE_MEM0f) && 1132 soc_reg_field_get(unit, IL_MEMORY_INIT_DONEr, rval, INIT_DONE_MEM1f) && 1133 soc_reg_field_get(unit, IL_MEMORY_INIT_DONEr, rval, INIT_DONE_MEM2f) && 1134 soc_reg_field_get(unit, IL_MEMORY_INIT_DONEr, rval, INIT_DONE_MEM3f) && 1135 soc_reg_field_get(unit, IL_MEMORY_INIT_DONEr, rval, INIT_DONE_MEM4f)) { 1136 break; 1137 } 1138 if (soc_timeout_check(&to)) { 1139 LOG_WARN(BSL_LS_SOC_COMMON, 1140 (BSL_META_U(unit, 1141 "unit %d : IL_MEMORY_INIT_DONE timeout\n"), unit)); 1142 break; 1143 } 1144 } while (TRUE); 1145 1146 SOC_IF_ERROR_RETURN 1147 (soc_reg_field32_modify(unit, EGR_PORT_MODEr, REG_PORT_ANY, 1148 IL0_ENf, 1)); 1149 SOC_IF_ERROR_RETURN 1150 (soc_reg_field32_modify(unit, EGR_PORT_MODEr, REG_PORT_ANY, 1151 IL1_ENf, 1)); 1152 SOC_IF_ERROR_RETURN 1153 (soc_reg_field32_modify(unit, IL_GLOBAL_CONFIGr, 9, 1154 CFG_TX_WC_BITFLIPf, 1)); 1155 SOC_IF_ERROR_RETURN 1156 (soc_reg_field32_modify(unit, IL_GLOBAL_CONFIGr, 9, 1157 CFG_RX_WC_BITFLIPf, 1)); 1158 1159 /* Configure IL Counters in accumulate mode;default is read on clear */ 1160 if (soc_property_get(unit, spn_BCM_STAT_FLAGS, 0)) { 1161 SOC_IF_ERROR_RETURN 1162 (soc_reg_field32_modify(unit, IL_GLOBAL_CONFIGr, 9, 1163 XGS_COUNTER_COMPAT_MODEf, 1)); 1164 } 1165 1166 /* Set Inband flow control, reset val(0x1) is OOB for shadow */ 1167 if (soc_property_get(unit, spn_BCM88732_USE_OOB, 0)) { 1168 SOC_IF_ERROR_RETURN 1169 (soc_reg_field32_modify(unit, IL_GLOBAL_CONFIGr, 9, 1170 CFG_FLOWCONTROL_TYPEf, 1)); 1171 SOC_IF_ERROR_RETURN 1172 (soc_reg_field32_modify(unit, IL_GLOBAL_CONFIGr, 13, 1173 CFG_FLOWCONTROL_TYPEf, 1)); 1174 } else { 1175 SOC_IF_ERROR_RETURN 1176 (soc_reg_field32_modify(unit, IL_GLOBAL_CONFIGr, 9, 1177 CFG_FLOWCONTROL_TYPEf, 0)); 1178 SOC_IF_ERROR_RETURN 1179 (soc_reg_field32_modify(unit, IL_GLOBAL_CONFIGr, 13, 1180 CFG_FLOWCONTROL_TYPEf, 0)); 1181 } 1182 1183 SOC_IF_ERROR_RETURN 1184 (soc_reg_field32_modify(unit, IL_GLOBAL_CONFIGr, 13, 1185 CFG_TX_WC_BITFLIPf, 1)); 1186 SOC_IF_ERROR_RETURN 1187 (soc_reg_field32_modify(unit, IL_GLOBAL_CONFIGr, 13, 1188 CFG_RX_WC_BITFLIPf, 1)); 1189 1190 /* Configure IL Counters in accumulate mode;default is read on clear */ 1191 if (soc_property_get(unit, spn_BCM_STAT_FLAGS, 0)) { 1192 SOC_IF_ERROR_RETURN 1193 (soc_reg_field32_modify(unit, IL_GLOBAL_CONFIGr, 13, 1194 XGS_COUNTER_COMPAT_MODEf, 1)); 1195 } 1196 break; 1197 default: 1198 break; /* No action */ 1199 } 1200 1201 1202 /* Bypass ISEC and ESEC */ 1203 PBMP_PORT_ITER(unit, port) { 1204 if (port > 8) { 1205 break; 1206 } 1207 rval = 0; 1208 soc_reg_field_set(unit, ESEC_MASTER_CTRLr, &rval, SOFT_RESETf, 0); 1209 soc_reg_field_set(unit, ESEC_MASTER_CTRLr, &rval, BYPASS_ENf, 1); 1210 soc_reg_field_set(unit, ESEC_MASTER_CTRLr, &rval, ACTIVATE_PD_CREDITSf, 1); 1211 soc_reg_field_set(unit, ESEC_MASTER_CTRLr, &rval, EN_40Gf, en40g); 1212 SOC_IF_ERROR_RETURN(WRITE_ESEC_MASTER_CTRLr(unit, port, rval)); 1213 rval = 0; 1214 soc_reg_field_set(unit, ISEC_MASTER_CTRLr, &rval, SOFT_RESETf, 0); 1215 soc_reg_field_set(unit, ISEC_MASTER_CTRLr, &rval, BYPASS_ENf, 1); 1216 soc_reg_field_set(unit, ISEC_MASTER_CTRLr, &rval, EN_40Gf, en40g); 1217 SOC_IF_ERROR_RETURN(WRITE_ISEC_MASTER_CTRLr(unit, port, rval)); 1218 if ((port == 1) || (port ==5)) { 1219 rval = 0; 1220 soc_reg_field_set(unit, ISEC_GLOBAL_CTRLr, &rval, INITf, 1); 1221 SOC_IF_ERROR_RETURN 1222 (soc_reg32_write(unit, soc_reg_addr(unit, ISEC_GLOBAL_CTRLr, 1223 port, 0), rval)); 1224 rval = 0; 1225 soc_reg_field_set(unit, ESEC_GLOBAL_CTRLr, &rval, INITf, 1); 1226 SOC_IF_ERROR_RETURN 1227 (soc_reg32_write(unit, soc_reg_addr(unit, ESEC_GLOBAL_CTRLr, 1228 port, 0), rval)); 1229 } 1230 } 1231 1232 /* Deal with XLPORT block */ 1233 sal_memset(port_exist, 0, sizeof(port_exist)); 1234 sal_memset(port_valid, 0, sizeof(port_valid)); 1235 for (port = 1; port <= 16; port++) { 1236 blk = SOC_PORT_BLOCK(unit, port); 1237 bindex = SOC_PORT_BINDEX(unit, port); 1238 blk_num = SOC_BLOCK_INFO(unit, blk).number; 1239 port_exist[blk_num] |= 1 << bindex; 1240 if (!SOC_PORT_VALID(unit, port) || 1241 SOC_PBMP_MEMBER(si->port.disabled_bitmap, port)) { 1242 continue; 1243 } 1244 port_valid[blk_num] |= 1 << bindex; 1245 } 1246 1247 SOC_BLOCK_ITER(unit, blk, SOC_BLK_XLPORT) { 1248 blk_num = SOC_BLOCK_INFO(unit, blk).number; 1249 port = SOC_BLOCK_PORT(unit, blk); 1250 if ((port < 0) || IS_IL_PORT(unit, port)) { 1251 continue; 1252 } 1253 /* Program XLPORT mode */ 1254 if (((port_valid[blk_num] & 0xf) == 0xf) || 1255 ((port_valid[blk_num] & 0x7) == 0x7)) { /* for TDM 3 */ 1256 core_mode = 2; /* quad */ 1257 } else if (((port_valid[blk_num] & 0x5) == 0x5) || 1258 ((port > 8) && (port_valid[blk_num] & 0x1) == 0x1)) { 1259 core_mode = 1; /* dual */ 1260 } else { 1261 core_mode = 0; /* single */ 1262 } 1263 1264 if (si->port_speed_max[port] > 20000) { 1265 phy_mode = 0; /* 16 lanes */ 1266 } else if (si->port_speed_max[port] > 10000) { 1267 phy_mode = 1; /* 8 lanes */ 1268 } else { 1269 phy_mode = 2; /* 4 lanes */ 1270 } 1271 /* TDM18/TDM19 XAUI mode has 4 lanes */ 1272 if (((soc_property_get(unit, spn_BCM88732_4X10_4X10, 0) || 1273 soc_property_get(unit, spn_BCM88732_1X40_4X10, 0))) && (port > 8)) { 1274 core_mode = 0; /* single port mode */ 1275 phy_mode = 2; /* 4 lanes */ 1276 } 1277 if (soc_property_get(unit, spn_BCM88732_2X40_8X10, 0) && (port > 8)) { 1278 core_mode = 1; /* Xlport-XMAC dual lane mode */ 1279 phy_mode = 2; /* 4 lanes */ 1280 } 1281 rval = 0; 1282 soc_reg_field_set(unit, XLPORT_MODE_REGr, &rval, CORE_PORT_MODEf, 1283 core_mode); 1284 soc_reg_field_set(unit, XLPORT_MODE_REGr, &rval, PHY_PORT_MODEf, 1285 phy_mode); 1286 if (blk_num == 0) { /* XLPORT0 block may have GE port */ 1287 if (si->port_speed_max[port] < 10000) { 1288 soc_reg_field_set(unit, XLPORT_MODE_REGr, &rval, 1289 PORT0_MAC_MODEf, 1); 1290 soc_reg_field_set(unit, XLPORT_MODE_REGr, &rval, 1291 PORT1_MAC_MODEf, 1); 1292 soc_reg_field_set(unit, XLPORT_MODE_REGr, &rval, 1293 PORT2_MAC_MODEf, 1); 1294 soc_reg_field_set(unit, XLPORT_MODE_REGr, &rval, 1295 PORT3_MAC_MODEf, 1); 1296 } 1297 } 1298 SOC_IF_ERROR_RETURN(WRITE_XLPORT_MODE_REGr(unit, port, rval)); 1299 1300 /* Bring XMAC out of reset */ 1301 if (si->port_speed_max[port] >= 10000) { 1302 if (!SOC_PBMP_MEMBER(si->port.disabled_bitmap, port)) { 1303 SOC_IF_ERROR_RETURN(WRITE_XLPORT_XMAC_CONTROLr(unit, port, 0)); 1304 } 1305 } 1306 1307 /* Reset XLPORT MIB counter */ 1308 rval = 0; 1309 soc_reg_field_set(unit, XLPORT_MIB_RESETr, &rval, CLR_CNTf, 1310 port_valid[blk_num]); 1311 SOC_IF_ERROR_RETURN(WRITE_XLPORT_MIB_RESETr(unit, port, rval)); 1312 SOC_IF_ERROR_RETURN(WRITE_XLPORT_MIB_RESETr(unit, port, 0)); 1313 1314 /* Enable XLPORT */ 1315 rval = 0; 1316 for (bindex = 0; bindex < 4; bindex++) { 1317 if (port_valid[blk_num] & (1 << bindex)) { 1318 soc_reg_field_set(unit, XLPORT_PORT_ENABLEr, &rval, 1319 port_field[bindex], 1); 1320 } 1321 } 1322 SOC_IF_ERROR_RETURN(WRITE_XLPORT_PORT_ENABLEr(unit, port, rval)); 1323 } 1324 1325 /* Initialize additional device mode configurations */ 1326 if (soc_property_get(unit, spn_BCM88732_DEVICE_MODE, 0)) { 1327 SOC_IF_ERROR_RETURN(soc_shadow_petrab_misc_init(unit)); 1328 } 1329 1330 for (port = 1; port <= 16; port++) { 1331 if (!SOC_PORT_VALID(unit, port) || 1332 SOC_PBMP_MEMBER(si->port.disabled_bitmap, port)) { 1333 continue; 1334 } 1335 SOC_IF_ERROR_RETURN(READ_XLPORT_MODE_REGr(unit, port, &rval)); 1336 phy_mode = soc_reg_field_get(unit, XLPORT_MODE_REGr, rval, PHY_PORT_MODEf); 1337 if (phy_mode == 0 ) { /* Quad Lanes Port */ 1338 si->port_num_lanes[port] = 4; 1339 } else if (phy_mode == 1 ) { /* DUAL Lane Port */ 1340 si->port_num_lanes[port] = 2; 1341 } else { 1342 si->port_num_lanes[port] = 1; /* Independent lane port */ 1343 } 1344 } 1345 1346 1347 /* Setup internal Priority to COSQ Mapping */ 1348 for(port = 0; port <= 16; port++) { 1349 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, COS_MAP_SELr, port, 1350 SELECTf, 0)); 1351 } 1352 for(i = 0; i < 4; i++) { 1353 for (prio = 0; prio < 8; prio++) { 1354 SOC_IF_ERROR_RETURN 1355 (soc_mem_field32_modify(unit, PORT_COS_MAPm, (i*16)+prio, COSf, prio)); 1356 } 1357 } 1358 1359 /* Setup EXP_TABLE with default priorities */ 1360 for(port = 0; port <= 16; port++) { 1361 for (prio = 0; prio < 8; prio++) { 1362 SOC_IF_ERROR_RETURN 1363 (soc_mem_field32_modify(unit, EXP_TABLEm, (port*8)+prio, PRIf, prio)); 1364 } 1365 } 1366 1367 soc_intr_enable(unit, IRQ_MEM_FAIL); 1368 SOC_IF_ERROR_RETURN 1369 (soc_reg_field32_modify(unit, EPC_LINK_BMAPr, REG_PORT_ANY, 1370 PORT_BITMAPf, 0x1ffff)); 1371 return SOC_E_NONE; 1372 } 1373 1374 int 1375 soc_shadow_petrab_mmu_init(int unit) 1376 { 1377 int idx; 1378 uint32 rval; 1379 soc_port_t p; 1380 uint32 cosw[8] = {0, 127, 64, 32, 24, 16, 8, 1}; 1381 1382 /* Disable watchdog in the Shadow MMU */ 1383 PBMP_PORT_ITER(unit, p) { 1384 SOC_IF_ERROR_RETURN 1385 (soc_reg_field32_modify(unit, DEQ_AGINGMASKr, p, AGINGMASKf, 0xff)); 1386 } 1387 1388 /* Set port max pkt size */ 1389 PBMP_ALL_ITER(unit, p) { 1390 SOC_IF_ERROR_RETURN 1391 (soc_reg_field32_modify(unit, PORT_MAX_PKT_SIZEr, p, 1392 PORT_MAX_PKT_SIZEf, 128)); 1393 } 1394 1395 /* Reconcile CoS conventions used between Petra and shadow 1396 * Petra CoS=0 is highest priority traffic. 1397 */ 1398 PBMP_XE_ITER(unit, p) { 1399 SOC_IF_ERROR_RETURN 1400 (soc_reg_field32_modify(unit, ESCONFIGr, p, SCHEDULING_SELECTf, 3)); 1401 for (idx = 0; idx < 8; idx++) { 1402 SOC_IF_ERROR_RETURN(READ_COSWEIGHTSr(unit, p, idx, &rval)); 1403 soc_reg_field_set(unit, COSWEIGHTSr, &rval, COSWEIGHTSf, cosw[idx]); 1404 SOC_IF_ERROR_RETURN(WRITE_COSWEIGHTSr(unit, p, idx, rval)); 1405 } 1406 } 1407 1408 /* Enable PFC */ 1409 PBMP_XE_ITER(unit, p) { 1410 rval = 0; 1411 soc_reg_field_set(unit, PORT_PRI_XON_ENABLEr, &rval, 1412 PORT_PRI_XON_ENABLEf, 0xff); 1413 soc_reg_field_set(unit, PORT_PRI_XON_ENABLEr, &rval, 1414 PORT_XON_ENABLEf, 1); 1415 soc_reg_field_set(unit, PORT_PRI_XON_ENABLEr, &rval, 1416 PORT_PG_PAUSE_DISABLEf, 8); 1417 SOC_IF_ERROR_RETURN 1418 (WRITE_PORT_PRI_XON_ENABLEr(unit, p, rval)); 1419 } 1420 1421 return SOC_E_NONE; 1422 } 1423 1424 int 1425 soc_shadow_petrab_misc_init(int unit) 1426 { 1427 int idx; 1428 int port; 1429 uint32 rval; 1430 soc_port_t p; 1431 fp_tcam_entry_t tcam_entry; 1432 il_channel_remap0_entry_t remap0; 1433 il_channel_remap1_entry_t remap1; 1434 fp_policy_table_entry_t policy_entry; 1435 uint32 field_values[4]; 1436 1437 /* Petra uses channel numbers 0 through 7 to specify port. 1438 * CoS is determined by SCH header via the IFP 1439 */ 1440 for (idx = 0; idx <= 7; idx ++) { 1441 sal_memset(&remap0, 0, sizeof(remap0)); 1442 sal_memset(&remap1, 0, sizeof(remap1)); 1443 1444 soc_IL_CHANNEL_REMAP0m_field32_set(unit, &remap0, PORT_NUMf, 1445 9 + idx); 1446 soc_IL_CHANNEL_REMAP0m_field32_set(unit, &remap1, PORT_NUMf, 1447 13); 1448 1449 if (idx == 3) { 1450 soc_IL_CHANNEL_REMAP0m_field32_set(unit, &remap0, COSf, 3); 1451 } else { 1452 soc_IL_CHANNEL_REMAP0m_field32_set(unit, &remap0, COSf, 0); 1453 } 1454 1455 SOC_IF_ERROR_RETURN 1456 (WRITE_IL_CHANNEL_REMAP0m(unit, MEM_BLOCK_ALL, idx, &remap0)); 1457 SOC_IF_ERROR_RETURN 1458 (WRITE_IL_CHANNEL_REMAP1m(unit, MEM_BLOCK_ALL, idx, &remap1)); 1459 } 1460 1461 1462 /* setup user defined field in IPARS */ 1463 for (idx = 0; idx < 512; idx++) { 1464 SOC_IF_ERROR_RETURN 1465 (soc_mem_field32_modify(unit, UDF_OFFSETm, idx, 1466 BASE_OFFSET0f, 11)); 1467 1468 SOC_IF_ERROR_RETURN 1469 (soc_mem_field32_modify(unit, UDF_OFFSETm, idx, 1470 OFFSET_VALUE0f, 0)); 1471 } 1472 1473 /* setup FP port fields */ 1474 rval = 0; 1475 soc_reg_field_set(unit, FP_SLICE_ENABLEr, &rval, 1476 FP_LOOKUP_ENABLE_SLICE_0f, 1); 1477 soc_reg_field_set(unit, FP_SLICE_ENABLEr, &rval, 1478 FP_SLICE_ENABLE_SLICE_0f, 1); 1479 SOC_IF_ERROR_RETURN(WRITE_FP_SLICE_ENABLEr(unit, rval)); 1480 1481 for (idx = 9; idx <= 16; idx ++) { 1482 SOC_IF_ERROR_RETURN 1483 (soc_mem_field32_modify(unit, FP_PORT_FIELD_SELm, idx, 1484 SLICE0_F1f, 0)); 1485 1486 SOC_IF_ERROR_RETURN 1487 (soc_mem_field32_modify(unit, FP_PORT_FIELD_SELm, idx, 1488 SLICE0_F2f, 8)); 1489 } 1490 1491 /* setup FP_TCAM fields */ 1492 sal_memset(&tcam_entry, 0, sizeof(tcam_entry)); 1493 soc_FP_TCAMm_field32_set(unit, &tcam_entry, IPBMf, 0x1fe00); 1494 soc_FP_TCAMm_field32_set(unit, &tcam_entry, IPBM_MASKf, 0x001ff); 1495 soc_FP_TCAMm_field32_set(unit, &tcam_entry, FIXED_MASKf, 0); 1496 soc_FP_TCAMm_field32_set(unit, &tcam_entry, F4_MASKf, 0); 1497 soc_FP_TCAMm_field32_set(unit, &tcam_entry, DOUBLE_WIDE_MODE_MASKf, 0); 1498 soc_FP_TCAMm_field32_set(unit, &tcam_entry, DOUBLE_WIDE_MODEf, 0); 1499 soc_FP_TCAMm_field32_set(unit, &tcam_entry, VALIDf, 3); 1500 1501 /* Fields greater than 32bits */ 1502 sal_memset(field_values, 0, sizeof(field_values)); 1503 field_values[0] = 1; 1504 soc_FP_TCAMm_field_set(unit, &tcam_entry, F1f, field_values); 1505 field_values[0] = 1; 1506 soc_FP_TCAMm_field_set(unit, &tcam_entry, F1_MASKf, field_values); 1507 field_values[0] = 0; 1508 soc_FP_TCAMm_field_set(unit, &tcam_entry, F3_MASKf, field_values); 1509 1510 sal_memset(field_values, 0, sizeof(field_values)); 1511 field_values[3] = 0xe0; 1512 soc_FP_TCAMm_field_set(unit, &tcam_entry, F2_MASKf, field_values); 1513 1514 for (idx = 0; idx <= 7; idx++) { 1515 field_values[3] = 0x20 * idx; 1516 soc_FP_TCAMm_field_set(unit, &tcam_entry, F2f, field_values); 1517 SOC_IF_ERROR_RETURN 1518 (WRITE_FP_TCAMm(unit, MEM_BLOCK_ALL, idx, &tcam_entry)); 1519 } 1520 1521 for (idx = 0; idx <= 7; idx++) { 1522 /* setup FP policy */ 1523 sal_memset(&policy_entry, 0, sizeof(policy_entry)); 1524 soc_FP_POLICY_TABLEm_field32_set(unit, &policy_entry, 1525 G_CHANGE_COS_OR_INT_PRIf, 5); 1526 soc_FP_POLICY_TABLEm_field32_set(unit, &policy_entry, 1527 G_COS_INT_PRIf, idx); 1528 SOC_IF_ERROR_RETURN 1529 (WRITE_FP_POLICY_TABLEm(unit, MEM_BLOCK_ALL, idx, &policy_entry)); 1530 } 1531 1532 /* Set Max pkt size */ 1533 PBMP_ALL_ITER(unit, port) { 1534 SOC_IF_ERROR_RETURN 1535 (soc_reg_field32_modify(unit, EGR_L2_MTUr, port, 1536 VALUEf, 16256)); 1537 } 1538 1539 /* vlan otag set to 0 */ 1540 for (idx = 0; idx < soc_mem_index_count(unit, ING_VLAN_TAG_ACTION_PROFILEm); idx ++) { 1541 SOC_IF_ERROR_RETURN 1542 (soc_mem_field32_modify(unit, ING_VLAN_TAG_ACTION_PROFILEm, idx, 1543 SOT_OTAG_ACTIONf, 0)); 1544 } 1545 1546 /* xlport config */ 1547 rval = 0; 1548 soc_reg_field_set(unit, XLPORT_CONFIGr, &rval, PFC_ENABLEf, 1); 1549 soc_reg_field_set(unit, XLPORT_CONFIGr, &rval, XPAUSE_RX_ENf, 0); 1550 soc_reg_field_set(unit, XLPORT_CONFIGr, &rval, XPAUSE_TX_ENf, 0); 1551 PBMP_XE_ITER(unit, port) { 1552 SOC_IF_ERROR_RETURN(WRITE_XLPORT_CONFIGr(unit, port, rval)); 1553 } 1554 1555 /* Configure Static balance */ 1556 if (soc_property_get(unit, spn_BCM88732_2X40_8X10, 0)) { 1557 /* uflow set for Xe0 -> port 10 */ 1558 SOC_IF_ERROR_RETURN 1559 (soc_reg_field32_modify(unit, UFLOW_PORT_CONTROLr, 1, 1560 HASH_MODEf, 0)); 1561 SOC_IF_ERROR_RETURN 1562 (soc_reg_field32_modify(unit, UFLOW_PORT_CONTROLr, 1, 1563 DEST_PORTf, 9)); 1564 1565 /* uflow set for Xe1 -> port 13 */ 1566 SOC_IF_ERROR_RETURN 1567 (soc_reg_field32_modify(unit, UFLOW_PORT_CONTROLr, 5, 1568 HASH_MODEf, 0)); 1569 SOC_IF_ERROR_RETURN 1570 (soc_reg_field32_modify(unit, UFLOW_PORT_CONTROLr, 5, 1571 DEST_PORTf, 13)); 1572 1573 /* Static balance for Switch ports : (1->[9,10,11,12] 5->[13,14,15,16]) */ 1574 for (p = 9; p <= 16; p++) { 1575 idx = ((p-8)/5)?5:1; 1576 SOC_IF_ERROR_RETURN 1577 (soc_reg_field32_modify(unit, UFLOW_PORT_CONTROLr, p, 1578 DEST_PORTf, idx)); 1579 } 1580 } else if (soc_property_get(unit, spn_BCM88732_8X10_8X10, 0)) { 1581 for (p = 1; p <= 8; p++) { 1582 SOC_IF_ERROR_RETURN 1583 (soc_reg_field32_modify(unit, UFLOW_PORT_CONTROLr, p, 1584 DEST_PORTf, 8+p)); 1585 SOC_IF_ERROR_RETURN 1586 (soc_reg_field32_modify(unit, UFLOW_PORT_CONTROLr, 8+p, 1587 DEST_PORTf, p)); 1588 SOC_IF_ERROR_RETURN 1589 (soc_reg_field32_modify(unit, UFLOW_PORT_CONTROLr, p, 1590 HASH_MODEf, 0)); 1591 SOC_IF_ERROR_RETURN 1592 (soc_reg_field32_modify(unit, UFLOW_PORT_CONTROLr, 8+p, 1593 HASH_MODEf, 0)); 1594 } 1595 } else if ((soc_property_get(unit, spn_BCM88732_2X40_1X40, 0)) || 1596 (soc_property_get(unit, spn_BCM88732_2X40_2X40, 0))) { 1597 1598 /* uflow set for Xe0 -> port 10 */ 1599 SOC_IF_ERROR_RETURN 1600 (soc_reg_field32_modify(unit, UFLOW_PORT_CONTROLr, 1, 1601 HASH_MODEf, 0)); 1602 SOC_IF_ERROR_RETURN 1603 (soc_reg_field32_modify(unit, UFLOW_PORT_CONTROLr, 1, 1604 DEST_PORTf, 9)); 1605 1606 /* uflow set for Xe1 -> port 13 */ 1607 SOC_IF_ERROR_RETURN 1608 (soc_reg_field32_modify(unit, UFLOW_PORT_CONTROLr, 5, 1609 HASH_MODEf, 0)); 1610 SOC_IF_ERROR_RETURN 1611 (soc_reg_field32_modify(unit, UFLOW_PORT_CONTROLr, 5, 1612 DEST_PORTf, 13)); 1613 1614 /* Static balance for Switch ports : (1->[9,10,11,12] 5->[13,14,15,16]) */ 1615 for (p = 9; p <= 16; p++) { 1616 idx = ((p-8)/5)?5:1; 1617 SOC_IF_ERROR_RETURN 1618 (soc_reg_field32_modify(unit, UFLOW_PORT_CONTROLr, p, 1619 DEST_PORTf, idx)); 1620 } 1621 1622 } else if ((soc_property_get(unit, spn_BCM88732_8X10_1X40, 0)) || 1623 (!(soc_property_get(unit, spn_BCM88732_1X40_4X10, 0) || 1624 soc_property_get(unit, spn_BCM88732_4X10_4X10, 0) || 1625 soc_property_get(unit, spn_BCM88732_8X10_8X10, 0) || 1626 soc_property_get(unit, spn_BCM88732_2X40_8X10, 0)))) { 1627 /* Static balance for interlaken ports : (1->9, 2->10 ... 8->16) */ 1628 for (p = 1; p <= 8; p++) { 1629 SOC_IF_ERROR_RETURN 1630 (soc_reg_field32_modify(unit, UFLOW_PORT_CONTROLr, p, 1631 DEST_PORTf, 8+p)); 1632 SOC_IF_ERROR_RETURN 1633 (soc_reg_field32_modify(unit, UFLOW_PORT_CONTROLr, 8+p, 1634 DEST_PORTf, p)); 1635 SOC_IF_ERROR_RETURN 1636 (soc_reg_field32_modify(unit, UFLOW_PORT_CONTROLr, p, 1637 HASH_MODEf, 0)); 1638 SOC_IF_ERROR_RETURN 1639 (soc_reg_field32_modify(unit, UFLOW_PORT_CONTROLr, 8+p, 1640 HASH_MODEf, 0)); 1641 } 1642 } 1643 1644 /* Enable all ILKN channels: */ 1645 PBMP_IL_ITER(unit, p) { 1646 if ((p == 9) || (p == 13)) { 1647 SOC_IF_ERROR_RETURN 1648 (soc_reg_field32_modify(unit, IL_RX_CHAN_ENABLE0r, p, 1649 IL_RX_CHAN_ENABLE0f, 0xffffffff)); 1650 SOC_IF_ERROR_RETURN 1651 (soc_reg_field32_modify(unit, IL_TX_CHAN_ENABLE0r, p, 1652 IL_TX_CHAN_ENABLE0f, 0xffffffff)); 1653 1654 /* Set Pkt Max Size */ 1655 SOC_IF_ERROR_RETURN 1656 (soc_reg_field32_modify(unit, IL_RX_CONFIGr, p, 1657 IL_RX_MAX_PACKET_SIZEf, 16256)); 1658 SOC_IF_ERROR_RETURN 1659 (soc_reg_field32_modify(unit, IL_TX_CONFIGr, p, 1660 IL_TX_MAX_PACKET_SIZEf, 16256)); 1661 1662 /* burst shot to 64B */ 1663 SOC_IF_ERROR_RETURN 1664 (soc_reg_field32_modify(unit, IL_TX_CORE_CONFIG0r, p, 1665 CTL_TX_BURSTSHORTf, 1)); 1666 1667 /* IL MU Link Level Flow-Control */ 1668 SOC_IF_ERROR_RETURN 1669 (soc_reg_field32_modify(unit, IL_MU_LLFC_CONTROLr, p, 1670 RX_ENABLEf, 1)); 1671 SOC_IF_ERROR_RETURN 1672 (soc_reg_field32_modify(unit, IL_MU_LLFC_CONTROLr, p, 1673 RX_POLARITYf, 0)); 1674 1675 /* Turn off CRC32 check */ 1676 SOC_IF_ERROR_RETURN 1677 (soc_reg_field32_modify(unit, IL_IEEE_CRC32_CONFIGr, p, 1678 CFG_TX_IEEE_CRC32_GEN_OFFSET16f, 0)); 1679 1680 SOC_IF_ERROR_RETURN 1681 (soc_reg_field32_modify(unit, IL_IEEE_CRC32_CONFIGr, p, 1682 CFG_RX_IEEE_CRC32_CHECK_OFFSET16f, 0)); 1683 1684 SOC_IF_ERROR_RETURN 1685 (soc_reg_field32_modify(unit, IL_IEEE_CRC32_CONFIGr, p, 1686 CFG_TX_IEEE_CRC32_GEN_STRIP_ENf, 0)); 1687 1688 SOC_IF_ERROR_RETURN 1689 (soc_reg_field32_modify(unit, IL_IEEE_CRC32_CONFIGr, p, 1690 CFG_TX_IEEE_CRC32_GEN_APPEND_ENf, 0)); 1691 1692 SOC_IF_ERROR_RETURN 1693 (soc_reg_field32_modify(unit, IL_IEEE_CRC32_CONFIGr, p, 1694 CFG_RX_IEEE_CRC32_STRIP_ENf, 0)); 1695 1696 SOC_IF_ERROR_RETURN 1697 (soc_reg_field32_modify(unit, IL_IEEE_CRC32_CONFIGr, p, 1698 CFG_RX_IEEE_CRC32_CHECK_ENf, 0)); 1699 } 1700 } 1701 return SOC_E_NONE; 1702 } 1703 1704 1705 1706 /* 1707 * MMU Config for TDM0_XFI 1708 * 2x40G to 8X10G_XFI 1709 */ 1710 STATIC 1711 int _shadow_tdm0_xfi_mmu_init(int unit) 1712 { 1713 soc_port_t p; 1714 int idx; 1715 soc_field_t pg_thresh[8] = {PG0_THRESH_SELf, PG1_THRESH_SELf, 1716 PG2_THRESH_SELf, PG3_THRESH_SELf, 1717 PG4_THRESH_SELf, PG5_THRESH_SELf, 1718 PG6_THRESH_SELf, PG7_THRESH_SELf}; 1719 soc_field_t pri_grp0[7] = {PRI0_GRPf, PRI1_GRPf, PRI2_GRPf, PRI3_GRPf, 1720 PRI4_GRPf, PRI5_GRPf, PRI6_GRPf}; 1721 soc_field_t pri_grp1[7] = {PRI7_GRPf, PRI8_GRPf, PRI9_GRPf, PRI10_GRPf, 1722 PRI11_GRPf, PRI12_GRPf, PRI13_GRPf}; 1723 soc_field_t aging0_fld[8] = {AGINGLIMITPRI7f, AGINGLIMITPRI6f, 1724 AGINGLIMITPRI5f, AGINGLIMITPRI4f, 1725 AGINGLIMITPRI3f, AGINGLIMITPRI2f, 1726 AGINGLIMITPRI1f, AGINGLIMITPRI0f}; 1727 soc_field_t aging1_fld[8] = {AGINGLIMITPRI15f, AGINGLIMITPRI14f, 1728 AGINGLIMITPRI13f, AGINGLIMITPRI12f, 1729 AGINGLIMITPRI11f, AGINGLIMITPRI10f, 1730 AGINGLIMITPRI9f, AGINGLIMITPRI8f}; 1731 uint32 es_arb_tdm_table[30] = 1732 {0x2, 0x200, 0x20, 0x2000, 0x400, 0x2, 1733 0x4000, 0x20, 0x800, 0x8000, 0x2, 0x1000, 1734 0x20, 0x10000, 0x1, 0x2, 0x200, 0x20, 1735 0x2000, 0x400, 0x2, 0x4000, 0x20, 0x800, 1736 0x8000, 0x2, 0x1000, 0x20, 0x10000, 0x0}; 1737 uint32 pri_grp0_val[7] = {0, 1, 2, 3, 4, 5, 6}; 1738 uint32 pri_grp1_val[7] = {7, 7, 7, 7, 7, 7, 7}; 1739 uint32 aging0_val[8] = {1, 1, 5, 5, 5, 5, 5, 5}; 1740 uint32 aging1_val[8] = {1, 1, 1, 1, 1, 1, 1, 1}; 1741 uint32 cosw[8] = {1, 16, 32, 64, 127, 0, 0, 0}; 1742 1743 uint32 rval; 1744 uint32 val = 0; 1745 1746 /* CFAP */ 1747 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, CFAPCONFIGr, REG_PORT_ANY, 1748 START_CFAP_INITf, 1)); 1749 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, CFAPCONFIGr, REG_PORT_ANY, 1750 CFAPPOOLSIZEf, 98304)); 1751 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, CFAPFULLTHRESHOLD0r, 1752 REG_PORT_ANY, 1753 CFAPFULLSETPOINTf, 98160)); 1754 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, CFAPFULLTHRESHOLD1r, 1755 REG_PORT_ANY, 1756 CFAPFULLRESETPOINTf, 98016)); 1757 1758 /* THDO */ 1759 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, THDO_BYPASSr, REG_PORT_ANY, 1760 OUTPUT_THRESHOLD_BYPASSf, 0)); 1761 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, OP_BUFFER_SHARED_LIMITr, 1762 REG_PORT_ANY, 1763 OP_BUFFER_SHARED_LIMITf, 98304)); 1764 PBMP_ALL_ITER(unit, p) { 1765 SOC_IF_ERROR_RETURN 1766 (soc_reg_field32_modify(unit, OP_PORT_CONFIGUr, p, 1767 OP_SHARED_LIMITf, 98304)); 1768 for (idx = 0; idx <= 9; idx++) { 1769 SOC_IF_ERROR_RETURN 1770 (READ_OP_QUEUE_CONFIGUr(unit, p, idx, &rval)); 1771 soc_reg_field_set(unit, OP_QUEUE_CONFIGUr, &rval, 1772 Q_SHARED_LIMITf, 98304); 1773 SOC_IF_ERROR_RETURN 1774 (WRITE_OP_QUEUE_CONFIGUr(unit, p, idx, rval)); 1775 } 1776 } 1777 1778 /* THDI */ 1779 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, TOTAL_SHARED_LIMITr, 1780 REG_PORT_ANY, 1781 TOTAL_SHARED_LIMITf, 54728)); 1782 PBMP_XE_ITER(unit, p) { 1783 uint32 xe_val[8] = {2, 2, 2, 2, 2, 2, 2, 2}; 1784 SOC_IF_ERROR_RETURN 1785 (soc_reg_field32_modify(unit, PORT_MINr, p, PORT_MINf, 8)); 1786 SOC_IF_ERROR_RETURN 1787 (soc_reg_field32_modify(unit, PORT_MAX_PKT_SIZEr, p, 1788 PORT_MAX_PKT_SIZEf, 72)); 1789 if (p <= 8) { 1790 SOC_IF_ERROR_RETURN 1791 (soc_reg_field32_modify(unit, PORT_SHARED_LIMITr, p, 1792 PORT_SHARED_LIMITf, 62304)); 1793 } else { 1794 SOC_IF_ERROR_RETURN 1795 (soc_reg_field32_modify(unit, PORT_SHARED_LIMITr, p, 1796 PORT_SHARED_LIMITf, 3200)); 1797 } 1798 SOC_IF_ERROR_RETURN 1799 (soc_reg_fields32_modify(unit, PG_THRESH_SELr, p, 8, 1800 pg_thresh, xe_val)); 1801 SOC_IF_ERROR_RETURN 1802 (soc_reg_field32_modify(unit, PORT_RESET_OFFSETr, p, 1803 PORT_RESET_OFFSETf, 0)); 1804 SOC_IF_ERROR_RETURN 1805 (soc_reg_field32_modify(unit, PG_RESET_OFFSETr, p, 1806 PG_RESET_OFFSETf, 10)); 1807 SOC_IF_ERROR_RETURN 1808 (soc_reg_field32_modify(unit, PG_MINr, p, PG_MINf, 8)); 1809 1810 for (idx = 0; idx < 8; idx++) { 1811 SOC_IF_ERROR_RETURN(READ_PG_HDRM_LIMITr(unit, p, idx, &rval)); 1812 if (p <= 8) { 1813 val = 1133; 1814 } else { 1815 val = 275; 1816 } 1817 soc_reg_field_set(unit, PG_HDRM_LIMITr, &rval, PG_HDRM_LIMITf, val); 1818 SOC_IF_ERROR_RETURN(WRITE_PG_HDRM_LIMITr(unit, p, idx, rval)); 1819 } 1820 SOC_IF_ERROR_RETURN 1821 (soc_reg_field32_modify(unit, PORT_PRI_XON_ENABLEr, p, 1822 PORT_PRI_XON_ENABLEf, 0x3fff)); 1823 SOC_IF_ERROR_RETURN 1824 (soc_reg_field32_modify(unit, PORT_PRI_XON_ENABLEr, p, 1825 PORT_XON_ENABLEf, 1)); 1826 SOC_IF_ERROR_RETURN 1827 (soc_reg_field32_modify(unit, PORT_PRI_XON_ENABLEr, p, 1828 PORT_PG_PAUSE_DISABLEf, 8)); 1829 } 1830 SOC_IF_ERROR_RETURN 1831 (soc_reg_field32_modify(unit, PORT_MINr, 0, PORT_MINf, 8)); 1832 SOC_IF_ERROR_RETURN 1833 (soc_reg_field32_modify(unit, PORT_SHARED_LIMITr, 0, 1834 PORT_SHARED_LIMITf, 1000)); 1835 SOC_IF_ERROR_RETURN 1836 (soc_reg_field32_modify(unit, PORT_RESET_OFFSETr, 0, 1837 PORT_RESET_OFFSETf, 0)); 1838 SOC_IF_ERROR_RETURN 1839 (soc_reg_field32_modify(unit, PG_MINr, 0, PG_MINf, 0)); 1840 1841 SOC_IF_ERROR_RETURN 1842 (soc_reg_field32_modify(unit, PORT_MAX_PKT_SIZEr, 0, 1843 PORT_MAX_PKT_SIZEf, 72)); 1844 SOC_IF_ERROR_RETURN 1845 (soc_reg_field32_modify(unit, PORT_PRI_XON_ENABLEr, 0, 1846 PORT_XON_ENABLEf, 1)); 1847 PBMP_ALL_ITER(unit, p) { 1848 SOC_IF_ERROR_RETURN 1849 (soc_reg_fields32_modify(unit, PORT_PRI_GRP0r, p, 7, 1850 pri_grp0, pri_grp0_val)); 1851 SOC_IF_ERROR_RETURN 1852 (soc_reg_fields32_modify(unit, PORT_PRI_GRP1r, p, 7, 1853 pri_grp1, pri_grp1_val)); 1854 } 1855 SOC_IF_ERROR_RETURN 1856 (soc_reg_field32_modify(unit, TOTAL_SHARED_AVAIL_THRESHr, 1857 REG_PORT_ANY, TOTAL_SHARED_AVAIL_THRESHf, 54472)); 1858 1859 /* WRED */ 1860 SOC_IF_ERROR_RETURN 1861 (soc_reg_field32_modify(unit, TIME_DOMAIN_CONFIGr, REG_PORT_ANY, 1862 LB_TIME_DOMAINf, 1)); 1863 SOC_IF_ERROR_RETURN 1864 (soc_reg_field32_modify(unit, TIME_DOMAIN_CONFIGr, REG_PORT_ANY, 1865 TIME_DOMAIN1f, 1)); 1866 PBMP_XE_ITER(unit, p) { 1867 SOC_IF_ERROR_RETURN 1868 (soc_reg_field32_modify(unit, PORT_WREDCONFIG_CELLr, p, 1869 LB_WEIGHTf, 4)); 1870 if (p <= 8) { 1871 SOC_IF_ERROR_RETURN 1872 (soc_reg_field32_modify(unit, PORT_WREDCONFIG_CELLr, p, 1873 LB_ENABLEf, 1)); 1874 } 1875 } 1876 1877 /* ES */ 1878 PBMP_PORT_ITER(unit, p) { 1879 SOC_IF_ERROR_RETURN 1880 (soc_reg_field32_modify(unit, ESCONFIGr, p, MTU_QUANTA_SELECTf, 2)); 1881 SOC_IF_ERROR_RETURN 1882 (soc_reg_field32_modify(unit, ESCONFIGr, p, SCHEDULING_SELECTf, 3)); 1883 for (idx = 0; idx < 8; idx++) { 1884 SOC_IF_ERROR_RETURN(READ_COSWEIGHTSr(unit, p, idx, &rval)); 1885 soc_reg_field_set(unit, COSWEIGHTSr, &rval, COSWEIGHTSf, cosw[idx]); 1886 SOC_IF_ERROR_RETURN(WRITE_COSWEIGHTSr(unit, p, idx, rval)); 1887 } 1888 } 1889 PBMP_ALL_ITER(unit, p) { 1890 SOC_IF_ERROR_RETURN 1891 (soc_reg_field32_modify(unit, ESCONFIGr, p, MTU_QUANTA_SELECTf, 2)); 1892 } 1893 SOC_IF_ERROR_RETURN 1894 (soc_reg_field32_modify(unit, INPUT_PORT_RX_ENABLEr, REG_PORT_ANY, 1895 INPUT_PORT_RX_ENABLEf, 0x1ffff)); 1896 SOC_IF_ERROR_RETURN 1897 (soc_reg_field32_modify(unit, OUTPUT_PORT_RX_ENABLEr, REG_PORT_ANY, 1898 OUTPUT_PORT_RX_ENABLEf, 0x1ffff)); 1899 SOC_IF_ERROR_RETURN 1900 (soc_reg_field32_modify(unit, PORTGRP_WDRR_CONFIGr, REG_PORT_ANY, 1901 PG_WDRR_MTU_QUANTA_SELECTf, 2)); 1902 for (idx = 0; idx < 30; idx++) { 1903 SOC_IF_ERROR_RETURN 1904 (soc_mem_field32_modify(unit, ES_ARB_TDM_TABLEm, idx, 1905 PORT_VECTORf, es_arb_tdm_table[idx])); 1906 SOC_IF_ERROR_RETURN 1907 (soc_mem_field32_modify(unit, ES_ARB_TDM_TABLEm, idx, 1908 SHAPER_ENf, 0)); 1909 SOC_IF_ERROR_RETURN 1910 (soc_mem_field32_modify(unit, ES_ARB_TDM_TABLEm, idx, 1911 SHAPER_IDf, 0)); 1912 } 1913 SOC_IF_ERROR_RETURN 1914 (soc_reg_field32_modify(unit, ES_TDM_CAL_CFGr, REG_PORT_ANY, 1915 END_Af, 59)); 1916 SOC_IF_ERROR_RETURN 1917 (soc_reg_field32_modify(unit, ES_TDM_CAL_CFGr, REG_PORT_ANY, 1918 END_Bf, 59)); 1919 /* MTRO */ 1920 PBMP_XE_ITER(unit, p) { 1921 SOC_IF_ERROR_RETURN 1922 (soc_reg_field32_modify(unit, EGRMETERINGCONFIGr, p, 1923 THRESHOLDf, 544)); 1924 SOC_IF_ERROR_RETURN 1925 (soc_reg_field32_modify(unit, EGRMETERINGCONFIG1r, p, 1926 REFRESHf, 156250)); 1927 } 1928 1929 /* INTF */ 1930 SOC_IF_ERROR_RETURN 1931 (soc_reg_field32_modify(unit, MMU_LLFC_TX_CONFIG_1r, REG_PORT_ANY, 1932 BW_TIMER_VALUE_1_8f, 10)); 1933 SOC_IF_ERROR_RETURN 1934 (soc_reg_field32_modify(unit, MMU_LLFC_TX_CONFIG_2r, REG_PORT_ANY, 1935 XOFF_REFRESH_TIME_1_8f, 256)); 1936 SOC_IF_ERROR_RETURN 1937 (soc_reg_field32_modify(unit, MMU_LLFC_TX_CONFIG_3r, REG_PORT_ANY, 1938 BW_TIMER_VALUE_9_16f, 10)); 1939 SOC_IF_ERROR_RETURN 1940 (soc_reg_field32_modify(unit, MMU_LLFC_TX_CONFIG_4r, REG_PORT_ANY, 1941 XOFF_REFRESH_TIME_9_16f, 32)); 1942 1943 SOC_IF_ERROR_RETURN 1944 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI15r, REG_PORT_ANY, 1945 COS0_7_BMPf, 128)); 1946 SOC_IF_ERROR_RETURN 1947 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI14r, REG_PORT_ANY, 1948 COS0_7_BMPf, 128)); 1949 SOC_IF_ERROR_RETURN 1950 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI13r, REG_PORT_ANY, 1951 COS0_7_BMPf, 128)); 1952 SOC_IF_ERROR_RETURN 1953 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI12r, REG_PORT_ANY, 1954 COS0_7_BMPf, 128)); 1955 SOC_IF_ERROR_RETURN 1956 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI11r, REG_PORT_ANY, 1957 COS0_7_BMPf, 128)); 1958 SOC_IF_ERROR_RETURN 1959 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI10r, REG_PORT_ANY, 1960 COS0_7_BMPf, 128)); 1961 SOC_IF_ERROR_RETURN 1962 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI9r, REG_PORT_ANY, 1963 COS0_7_BMPf, 128)); 1964 SOC_IF_ERROR_RETURN 1965 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI8r, REG_PORT_ANY, 1966 COS0_7_BMPf, 128)); 1967 SOC_IF_ERROR_RETURN 1968 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI7r, REG_PORT_ANY, 1969 COS0_7_BMPf, 128)); 1970 SOC_IF_ERROR_RETURN 1971 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI6r, REG_PORT_ANY, 1972 COS0_7_BMPf, 64)); 1973 SOC_IF_ERROR_RETURN 1974 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI5r, REG_PORT_ANY, 1975 COS0_7_BMPf, 32)); 1976 SOC_IF_ERROR_RETURN 1977 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI4r, REG_PORT_ANY, 1978 COS0_7_BMPf, 16)); 1979 SOC_IF_ERROR_RETURN 1980 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI3r, REG_PORT_ANY, 1981 COS0_7_BMPf, 8)); 1982 SOC_IF_ERROR_RETURN 1983 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI2r, REG_PORT_ANY, 1984 COS0_7_BMPf, 4)); 1985 SOC_IF_ERROR_RETURN 1986 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI1r, REG_PORT_ANY, 1987 COS0_7_BMPf, 2)); 1988 SOC_IF_ERROR_RETURN 1989 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI0r, REG_PORT_ANY, 1990 COS0_7_BMPf, 1)); 1991 /* AGING */ 1992 SOC_IF_ERROR_RETURN 1993 (soc_reg_field32_modify(unit, PKTAGINGTIMERr, REG_PORT_ANY, 1994 DURATIONSELECTf, 4096)); 1995 SOC_IF_ERROR_RETURN 1996 (soc_reg_fields32_modify(unit, PKTAGINGLIMIT0r, REG_PORT_ANY, 8, 1997 aging0_fld, aging0_val)); 1998 SOC_IF_ERROR_RETURN 1999 (soc_reg_fields32_modify(unit, PKTAGINGLIMIT1r, REG_PORT_ANY, 8, 2000 aging1_fld, aging1_val)); 2001 2002 /* CTR */ 2003 rval = 0; 2004 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, CNGf, 7); 2005 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, COSf, 15); 2006 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, DST_PORTf, 31); 2007 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, SRC_PORTf, 31); 2008 SOC_IF_ERROR_RETURN(WRITE_TX_CNT_CONFIGr_REG32(unit, 7, rval)); 2009 2010 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, ALL_DROP_ACCEPTf, 1); 2011 SOC_IF_ERROR_RETURN(WRITE_TX_CNT_CONFIGr_REG32(unit, 6, rval)); 2012 2013 rval = 0; 2014 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, CNGf, 7); 2015 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, ENQ_DEQf, 1); 2016 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, COSf, 15); 2017 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, DST_PORTf, 31); 2018 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, SRC_PORTf, 31); 2019 SOC_IF_ERROR_RETURN(WRITE_TX_CNT_CONFIGr_REG32(unit, 5, rval)); 2020 2021 rval = 0; 2022 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, COSf, 15); 2023 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, DST_PORTf, 31); 2024 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, SRC_PORTf, 31); 2025 SOC_IF_ERROR_RETURN(WRITE_TX_CNT_CONFIGr_REG32(unit, 4, rval)); 2026 2027 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, CNGf, 1); 2028 SOC_IF_ERROR_RETURN(WRITE_TX_CNT_CONFIGr_REG32(unit, 3, rval)); 2029 2030 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, CNGf, 2); 2031 SOC_IF_ERROR_RETURN(WRITE_TX_CNT_CONFIGr_REG32(unit, 2, rval)); 2032 2033 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, CNGf, 3); 2034 SOC_IF_ERROR_RETURN(WRITE_TX_CNT_CONFIGr_REG32(unit, 1, rval)); 2035 2036 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, CNGf, 7); 2037 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, ECN_MARKEDf, 1); 2038 SOC_IF_ERROR_RETURN(WRITE_TX_CNT_CONFIGr_REG32(unit, 0, rval)); 2039 2040 return SOC_E_NONE; 2041 } 2042 2043 /* 2044 * MMU Config for TDM1-XFI 2045 * 8x10G to 8X10G 2046 */ 2047 STATIC 2048 int _shadow_tdm1_xfi_mmu_init(int unit) 2049 { 2050 soc_port_t p; 2051 int idx; 2052 soc_field_t pg_thresh[8] = {PG0_THRESH_SELf, PG1_THRESH_SELf, 2053 PG2_THRESH_SELf, PG3_THRESH_SELf, 2054 PG4_THRESH_SELf, PG5_THRESH_SELf, 2055 PG6_THRESH_SELf, PG7_THRESH_SELf}; 2056 soc_field_t pri_grp0[7] = {PRI0_GRPf, PRI1_GRPf, PRI2_GRPf, PRI3_GRPf, 2057 PRI4_GRPf, PRI5_GRPf, PRI6_GRPf}; 2058 soc_field_t pri_grp1[7] = {PRI7_GRPf, PRI8_GRPf, PRI9_GRPf, PRI10_GRPf, 2059 PRI11_GRPf, PRI12_GRPf, PRI13_GRPf}; 2060 soc_field_t aging0_fld[8] = {AGINGLIMITPRI7f, AGINGLIMITPRI6f, 2061 AGINGLIMITPRI5f, AGINGLIMITPRI4f, 2062 AGINGLIMITPRI3f, AGINGLIMITPRI2f, 2063 AGINGLIMITPRI1f, AGINGLIMITPRI0f}; 2064 soc_field_t aging1_fld[8] = {AGINGLIMITPRI15f, AGINGLIMITPRI14f, 2065 AGINGLIMITPRI13f, AGINGLIMITPRI12f, 2066 AGINGLIMITPRI11f, AGINGLIMITPRI10f, 2067 AGINGLIMITPRI9f, AGINGLIMITPRI8f}; 2068 uint32 es_arb_tdm_table[60] = 2069 {0x2, 512, 32, 8192, 1024, 0x4, 2070 16384, 64, 2048, 32768, 8, 4096, 2071 128, 65536, 1, 0x10, 512, 256, 2072 8192, 1024, 2, 16384, 0x20, 2048, 2073 32768, 4, 4096, 64, 65536, 0x0, 2074 0x8, 512, 128, 8192, 1024, 0x10, 2075 16384, 0x100, 2048, 32768, 0x2, 4096, 2076 0x20, 65536, 0x1, 0x4, 512, 0x40, 2077 8192, 1024, 0x8, 16384, 0x80, 2048, 2078 32768, 16, 4096, 256, 65536, 0x0}; 2079 2080 uint32 pri_grp0_val[7] = {0, 1, 2, 3, 4, 5, 6}; 2081 uint32 pri_grp1_val[7] = {7, 7, 7, 7, 7, 7, 7}; 2082 uint32 aging0_val[8] = {1, 1, 5, 5, 5, 5, 5, 5}; 2083 uint32 aging1_val[8] = {1, 1, 1, 1, 1, 1, 0, 1}; 2084 uint32 cosw[8] = {1, 16, 32, 64, 127, 0, 0, 0}; 2085 2086 uint32 rval; 2087 uint32 val = 0; 2088 2089 /* CFAP */ 2090 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, CFAPCONFIGr, REG_PORT_ANY, 2091 CFAPPOOLSIZEf, 98304)); 2092 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, CFAPFULLTHRESHOLD0r, 2093 REG_PORT_ANY, 2094 CFAPFULLSETPOINTf, 98160)); 2095 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, CFAPFULLTHRESHOLD1r, 2096 REG_PORT_ANY, 2097 CFAPFULLRESETPOINTf, 98016)); 2098 2099 /* THDO */ 2100 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, THDO_BYPASSr, REG_PORT_ANY, 2101 OUTPUT_THRESHOLD_BYPASSf, 0)); 2102 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, OP_BUFFER_SHARED_LIMITr, 2103 REG_PORT_ANY, 2104 OP_BUFFER_SHARED_LIMITf, 98304)); 2105 PBMP_ALL_ITER(unit, p) { 2106 SOC_IF_ERROR_RETURN 2107 (soc_reg_field32_modify(unit, OP_PORT_CONFIGUr, p, 2108 OP_SHARED_LIMITf, 98304)); 2109 for (idx = 0; idx <= 9; idx++) { 2110 SOC_IF_ERROR_RETURN 2111 (READ_OP_QUEUE_CONFIGUr(unit, p, idx, &rval)); 2112 soc_reg_field_set(unit, OP_QUEUE_CONFIGUr, &rval, 2113 Q_SHARED_LIMITf, 98304); 2114 SOC_IF_ERROR_RETURN 2115 (WRITE_OP_QUEUE_CONFIGUr(unit, p, idx, rval)); 2116 } 2117 } 2118 2119 /* THDI */ 2120 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, TOTAL_SHARED_LIMITr, 2121 REG_PORT_ANY, 2122 TOTAL_SHARED_LIMITf, 54728)); 2123 PBMP_XE_ITER(unit, p) { 2124 uint32 xe_val[8] = {2, 2, 2, 2, 2, 2, 2, 2}; 2125 SOC_IF_ERROR_RETURN 2126 (soc_reg_field32_modify(unit, PORT_MINr, p, PORT_MINf, 8)); 2127 SOC_IF_ERROR_RETURN 2128 (soc_reg_field32_modify(unit, PORT_MAX_PKT_SIZEr, p, 2129 PORT_MAX_PKT_SIZEf, 72)); 2130 2131 val = (p <= 8) ? 15576 : 3200; 2132 SOC_IF_ERROR_RETURN 2133 (soc_reg_field32_modify(unit, PORT_SHARED_LIMITr, p, 2134 PORT_SHARED_LIMITf, val)); 2135 SOC_IF_ERROR_RETURN 2136 (soc_reg_fields32_modify(unit, PG_THRESH_SELr, p, 8, 2137 pg_thresh, xe_val)); 2138 SOC_IF_ERROR_RETURN 2139 (soc_reg_field32_modify(unit, PORT_RESET_OFFSETr, p, 2140 PORT_RESET_OFFSETf, 0)); 2141 SOC_IF_ERROR_RETURN 2142 (soc_reg_field32_modify(unit, PG_RESET_OFFSETr, p, 2143 PG_RESET_OFFSETf, 10)); 2144 SOC_IF_ERROR_RETURN 2145 (soc_reg_field32_modify(unit, PG_MINr, p, PG_MINf, 8)); 2146 2147 for (idx = 0; idx < 8; idx++) { 2148 SOC_IF_ERROR_RETURN(READ_PG_HDRM_LIMITr(unit, p, idx, &rval)); 2149 val = (p <= 8) ? 283 : 275; 2150 soc_reg_field_set(unit, PG_HDRM_LIMITr, &rval, PG_HDRM_LIMITf, val); 2151 SOC_IF_ERROR_RETURN(WRITE_PG_HDRM_LIMITr(unit, p, idx, rval)); 2152 } 2153 SOC_IF_ERROR_RETURN 2154 (soc_reg_field32_modify(unit, PORT_PRI_XON_ENABLEr, p, 2155 PORT_PRI_XON_ENABLEf, 0x3fff)); 2156 SOC_IF_ERROR_RETURN 2157 (soc_reg_field32_modify(unit, PORT_PRI_XON_ENABLEr, p, 2158 PORT_XON_ENABLEf, 1)); 2159 SOC_IF_ERROR_RETURN 2160 (soc_reg_field32_modify(unit, PORT_PRI_XON_ENABLEr, p, 2161 PORT_PG_PAUSE_DISABLEf, 8)); 2162 } 2163 SOC_IF_ERROR_RETURN 2164 (soc_reg_field32_modify(unit, PORT_MINr, 0, PORT_MINf, 8)); 2165 SOC_IF_ERROR_RETURN 2166 (soc_reg_field32_modify(unit, PORT_SHARED_LIMITr, 0, 2167 PORT_SHARED_LIMITf, 1000)); 2168 SOC_IF_ERROR_RETURN 2169 (soc_reg_field32_modify(unit, PORT_RESET_OFFSETr, 0, 2170 PORT_RESET_OFFSETf, 1)); 2171 PBMP_ALL_ITER(unit, p) { 2172 SOC_IF_ERROR_RETURN 2173 (soc_reg_fields32_modify(unit, PORT_PRI_GRP0r, p, 7, 2174 pri_grp0, pri_grp0_val)); 2175 SOC_IF_ERROR_RETURN 2176 (soc_reg_fields32_modify(unit, PORT_PRI_GRP1r, p, 7, 2177 pri_grp1, pri_grp1_val)); 2178 } 2179 SOC_IF_ERROR_RETURN 2180 (soc_reg_field32_modify(unit, TOTAL_SHARED_AVAIL_THRESHr, 2181 REG_PORT_ANY, TOTAL_SHARED_AVAIL_THRESHf, 2182 54472)); 2183 2184 /* MTRO */ 2185 PBMP_XE_ITER(unit, p) { 2186 SOC_IF_ERROR_RETURN 2187 (soc_reg_field32_modify(unit, EGRMETERINGCONFIG1r, p, 2188 REFRESHf, 156250)); 2189 } 2190 2191 /* WRED */ 2192 SOC_IF_ERROR_RETURN 2193 (soc_reg_field32_modify(unit, TIME_DOMAIN_CONFIGr, REG_PORT_ANY, 2194 LB_TIME_DOMAINf, 1)); 2195 SOC_IF_ERROR_RETURN 2196 (soc_reg_field32_modify(unit, TIME_DOMAIN_CONFIGr, REG_PORT_ANY, 2197 TIME_DOMAIN1f, 1)); 2198 PBMP_XE_ITER(unit, p) { 2199 SOC_IF_ERROR_RETURN 2200 (soc_reg_field32_modify(unit, PORT_WREDCONFIG_CELLr, p, 2201 LB_WEIGHTf, 4)); 2202 if (p <= 8) { 2203 SOC_IF_ERROR_RETURN 2204 (soc_reg_field32_modify(unit, PORT_WREDCONFIG_CELLr, p, 2205 LB_ENABLEf, 1)); 2206 } 2207 } 2208 2209 /* ES */ 2210 PBMP_PORT_ITER(unit, p) { 2211 SOC_IF_ERROR_RETURN 2212 (soc_reg_field32_modify(unit, ESCONFIGr, p, MTU_QUANTA_SELECTf, 2)); 2213 SOC_IF_ERROR_RETURN 2214 (soc_reg_field32_modify(unit, ESCONFIGr, p, SCHEDULING_SELECTf, 3)); 2215 for (idx = 0; idx < 8; idx++) { 2216 SOC_IF_ERROR_RETURN(READ_COSWEIGHTSr(unit, p, idx, &rval)); 2217 soc_reg_field_set(unit, COSWEIGHTSr, &rval, COSWEIGHTSf, cosw[idx]); 2218 SOC_IF_ERROR_RETURN(WRITE_COSWEIGHTSr(unit, p, idx, rval)); 2219 } 2220 } 2221 SOC_IF_ERROR_RETURN 2222 (soc_reg_field32_modify(unit, INPUT_PORT_RX_ENABLEr, REG_PORT_ANY, 2223 INPUT_PORT_RX_ENABLEf, 0x1ffff)); 2224 SOC_IF_ERROR_RETURN 2225 (soc_reg_field32_modify(unit, OUTPUT_PORT_RX_ENABLEr, REG_PORT_ANY, 2226 OUTPUT_PORT_RX_ENABLEf, 0x1ffff)); 2227 SOC_IF_ERROR_RETURN 2228 (soc_reg_field32_modify(unit, PORTGRP_WDRR_CONFIGr, REG_PORT_ANY, 2229 PG_WDRR_MTU_QUANTA_SELECTf, 2)); 2230 for (idx = 0; idx < 60; idx++) { 2231 SOC_IF_ERROR_RETURN 2232 (soc_mem_field32_modify(unit, ES_ARB_TDM_TABLEm, idx, 2233 PORT_VECTORf, es_arb_tdm_table[idx])); 2234 SOC_IF_ERROR_RETURN 2235 (soc_mem_field32_modify(unit, ES_ARB_TDM_TABLEm, idx, 2236 SHAPER_ENf, 0)); 2237 SOC_IF_ERROR_RETURN 2238 (soc_mem_field32_modify(unit, ES_ARB_TDM_TABLEm, idx, 2239 SHAPER_IDf, 0)); 2240 } 2241 SOC_IF_ERROR_RETURN 2242 (soc_reg_field32_modify(unit, ES_TDM_CAL_CFGr, REG_PORT_ANY, 2243 CURRENT_CALENDARf, 0)); 2244 SOC_IF_ERROR_RETURN 2245 (soc_reg_field32_modify(unit, ES_TDM_CAL_CFGr, REG_PORT_ANY, 2246 END_Af, 59)); 2247 SOC_IF_ERROR_RETURN 2248 (soc_reg_field32_modify(unit, ES_TDM_CAL_CFGr, REG_PORT_ANY, 2249 END_Bf, 59)); 2250 SOC_IF_ERROR_RETURN 2251 (soc_reg_field32_modify(unit, ES_TDM_CAL_CFGr, REG_PORT_ANY, 2252 SWITCH_CALENDARf, 0)); 2253 SOC_IF_ERROR_RETURN 2254 (soc_reg_field32_modify(unit, ES_TDM_ENr, REG_PORT_ANY, 2255 ENf, 1)); 2256 2257 /* INTF */ 2258 SOC_IF_ERROR_RETURN 2259 (soc_reg_field32_modify(unit, MMU_LLFC_TX_CONFIG_1r, REG_PORT_ANY, 2260 BW_TIMER_VALUE_1_8f, 10)); 2261 SOC_IF_ERROR_RETURN 2262 (soc_reg_field32_modify(unit, MMU_LLFC_TX_CONFIG_2r, REG_PORT_ANY, 2263 XOFF_REFRESH_TIME_1_8f, 256)); 2264 SOC_IF_ERROR_RETURN 2265 (soc_reg_field32_modify(unit, MMU_LLFC_TX_CONFIG_3r, REG_PORT_ANY, 2266 BW_TIMER_VALUE_9_16f, 10)); 2267 SOC_IF_ERROR_RETURN 2268 (soc_reg_field32_modify(unit, MMU_LLFC_TX_CONFIG_4r, REG_PORT_ANY, 2269 XOFF_REFRESH_TIME_9_16f, 32)); 2270 2271 SOC_IF_ERROR_RETURN 2272 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI15r, REG_PORT_ANY, 2273 COS0_7_BMPf, 128)); 2274 SOC_IF_ERROR_RETURN 2275 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI14r, REG_PORT_ANY, 2276 COS0_7_BMPf, 128)); 2277 SOC_IF_ERROR_RETURN 2278 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI13r, REG_PORT_ANY, 2279 COS0_7_BMPf, 128)); 2280 SOC_IF_ERROR_RETURN 2281 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI12r, REG_PORT_ANY, 2282 COS0_7_BMPf, 128)); 2283 SOC_IF_ERROR_RETURN 2284 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI11r, REG_PORT_ANY, 2285 COS0_7_BMPf, 128)); 2286 SOC_IF_ERROR_RETURN 2287 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI10r, REG_PORT_ANY, 2288 COS0_7_BMPf, 128)); 2289 SOC_IF_ERROR_RETURN 2290 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI9r, REG_PORT_ANY, 2291 COS0_7_BMPf, 128)); 2292 SOC_IF_ERROR_RETURN 2293 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI8r, REG_PORT_ANY, 2294 COS0_7_BMPf, 128)); 2295 SOC_IF_ERROR_RETURN 2296 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI7r, REG_PORT_ANY, 2297 COS0_7_BMPf, 128)); 2298 SOC_IF_ERROR_RETURN 2299 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI6r, REG_PORT_ANY, 2300 COS0_7_BMPf, 64)); 2301 SOC_IF_ERROR_RETURN 2302 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI5r, REG_PORT_ANY, 2303 COS0_7_BMPf, 32)); 2304 SOC_IF_ERROR_RETURN 2305 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI4r, REG_PORT_ANY, 2306 COS0_7_BMPf, 16)); 2307 SOC_IF_ERROR_RETURN 2308 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI3r, REG_PORT_ANY, 2309 COS0_7_BMPf, 8)); 2310 SOC_IF_ERROR_RETURN 2311 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI2r, REG_PORT_ANY, 2312 COS0_7_BMPf, 4)); 2313 SOC_IF_ERROR_RETURN 2314 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI1r, REG_PORT_ANY, 2315 COS0_7_BMPf, 2)); 2316 SOC_IF_ERROR_RETURN 2317 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI0r, REG_PORT_ANY, 2318 COS0_7_BMPf, 1)); 2319 2320 /* AGING */ 2321 SOC_IF_ERROR_RETURN 2322 (soc_reg_field32_modify(unit, PKTAGINGTIMERr, REG_PORT_ANY, 2323 DURATIONSELECTf, 4096)); 2324 SOC_IF_ERROR_RETURN 2325 (soc_reg_fields32_modify(unit, PKTAGINGLIMIT0r, REG_PORT_ANY, 8, 2326 aging0_fld, aging0_val)); 2327 SOC_IF_ERROR_RETURN 2328 (soc_reg_fields32_modify(unit, PKTAGINGLIMIT1r, REG_PORT_ANY, 8, 2329 aging1_fld, aging1_val)); 2330 2331 /* CTR */ 2332 rval = 0; 2333 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, CNGf, 7); 2334 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, COSf, 15); 2335 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, DST_PORTf, 31); 2336 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, SRC_PORTf, 31); 2337 SOC_IF_ERROR_RETURN(WRITE_TX_CNT_CONFIGr_REG32(unit, 7, rval)); 2338 SOC_IF_ERROR_RETURN(WRITE_TX_CNT_CONFIGr_REG32(unit, 6, rval)); 2339 rval = 0; 2340 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, CNGf, 7); 2341 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, COSf, 15); 2342 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, DST_PORTf, 31); 2343 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, SRC_PORTf, 31); 2344 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, ENQ_DEQf, 1); 2345 SOC_IF_ERROR_RETURN(WRITE_TX_CNT_CONFIGr_REG32(unit, 5, rval)); 2346 rval = 0; 2347 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, COSf, 15); 2348 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, DST_PORTf, 31); 2349 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, SRC_PORTf, 31); 2350 SOC_IF_ERROR_RETURN(WRITE_TX_CNT_CONFIGr_REG32(unit, 4, rval)); 2351 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, CNGf, 1); 2352 SOC_IF_ERROR_RETURN(WRITE_TX_CNT_CONFIGr_REG32(unit, 3, rval)); 2353 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, CNGf, 2); 2354 SOC_IF_ERROR_RETURN(WRITE_TX_CNT_CONFIGr_REG32(unit, 2, rval)); 2355 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, CNGf, 3); 2356 SOC_IF_ERROR_RETURN(WRITE_TX_CNT_CONFIGr_REG32(unit, 1, rval)); 2357 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, CNGf, 7); 2358 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, SRC_PORTf, 1); 2359 SOC_IF_ERROR_RETURN(WRITE_TX_CNT_CONFIGr_REG32(unit, 0, rval)); 2360 2361 return SOC_E_NONE; 2362 } 2363 2364 2365 2366 /* 2367 * MMU Configurations for TDM5 2368 * 2x40G to 2x40G(Interlaken) 2369 * Refered to SOC script : radian_init_88732_2X40G+2X40G_IL.soc 2370 */ 2371 2372 STATIC 2373 int _shadow_tdm5_mmu_init(int unit) 2374 { 2375 soc_port_t p; 2376 int idx; 2377 soc_field_t pg_thresh[8] = {PG0_THRESH_SELf, PG1_THRESH_SELf, 2378 PG2_THRESH_SELf, PG3_THRESH_SELf, 2379 PG4_THRESH_SELf, PG5_THRESH_SELf, 2380 PG6_THRESH_SELf, PG7_THRESH_SELf}; 2381 soc_field_t pri_grp0[7] = {PRI0_GRPf, PRI1_GRPf, PRI2_GRPf, PRI3_GRPf, 2382 PRI4_GRPf, PRI5_GRPf, PRI6_GRPf}; 2383 soc_field_t pri_grp1[7] = {PRI7_GRPf, PRI8_GRPf, PRI9_GRPf, PRI10_GRPf, 2384 PRI11_GRPf, PRI12_GRPf, PRI13_GRPf}; 2385 soc_field_t wredcfg_cell[7] = {MAXDROPRATEf, YELLOW_MAXDROPRATEf, 2386 RED_MAXDROPRATEf, PRI0_MAXDROPRATEf, 2387 WEIGHTf, CAP_AVERAGEf, ENABLEf}; 2388 soc_field_t aging0_fld[8] = {AGINGLIMITPRI7f, AGINGLIMITPRI6f, 2389 AGINGLIMITPRI5f, AGINGLIMITPRI4f, 2390 AGINGLIMITPRI3f, AGINGLIMITPRI2f, 2391 AGINGLIMITPRI1f, AGINGLIMITPRI0f}; 2392 soc_field_t aging1_fld[8] = {AGINGLIMITPRI15f, AGINGLIMITPRI14f, 2393 AGINGLIMITPRI13f, AGINGLIMITPRI12f, 2394 AGINGLIMITPRI11f, AGINGLIMITPRI10f, 2395 AGINGLIMITPRI9f, AGINGLIMITPRI8f}; 2396 uint32 es_arb_tdm_table[30] = 2397 {0x2, 0x1e00, 0x20, 0x1e000, 0x0, 0x2, 2398 0x0, 0x20, 0x1e000, 0x0, 0x2, 0x1e00, 2399 0x20, 0x1e000, 0x1, 0x2, 0x1e00, 0x0, 2400 0x1e000, 0x0, 0x2, 0x1e00, 0x20, 0x1e000, 2401 0x0, 0x2, 0x1e00, 0x20, 0x1e000, 0x0}; 2402 2403 uint32 pri_grp0_val[7] = {0, 1, 2, 3, 4, 5, 6}; 2404 uint32 pri_grp1_val[7] = {7, 7, 7, 7, 7, 7, 7}; 2405 uint32 wredcfg_cell_val[7] = {10, 10, 10, 10, 4, 1, 1}; 2406 uint32 cosw[8] = {1, 8, 16, 24, 32, 64, 127, 0}; 2407 uint32 aging0_val[8] = {1, 1, 5, 5, 5, 5, 5, 5}; 2408 uint32 aging1_val[8] = {1, 1, 1, 1, 1, 1, 1, 1}; 2409 2410 uint32 rval; 2411 uint64 rval64; 2412 2413 2414 /* Some XMAC related stuff: this needs to be moved to xmac.c */ 2415 PBMP_XE_ITER(unit, p) { 2416 SOC_IF_ERROR_RETURN(READ_XMAC_CTRLr(unit, p, &rval64)); 2417 soc_reg64_field32_set(unit, XMAC_CTRLr, &rval64, XLGMII_ALIGN_ENBf, 1); 2418 SOC_IF_ERROR_RETURN(WRITE_XMAC_CTRLr(unit, p, rval64)); 2419 } 2420 /* CFAP */ 2421 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, CFAPCONFIGr, REG_PORT_ANY, 2422 START_CFAP_INITf, 1)); 2423 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, CFAPFULLTHRESHOLD0r, 2424 REG_PORT_ANY, 2425 CFAPFULLSETPOINTf, 98160)); 2426 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, CFAPFULLTHRESHOLD1r, 2427 REG_PORT_ANY, 2428 CFAPFULLRESETPOINTf, 98016)); 2429 2430 /* THDO */ 2431 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, THDO_BYPASSr, REG_PORT_ANY, 2432 OUTPUT_THRESHOLD_BYPASSf, 0)); 2433 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, OP_BUFFER_SHARED_LIMITr, 2434 REG_PORT_ANY, 2435 OP_BUFFER_SHARED_LIMITf, 98304)); 2436 PBMP_ALL_ITER(unit, p) { 2437 SOC_IF_ERROR_RETURN 2438 (soc_reg_field32_modify(unit, OP_PORT_CONFIGUr, p, 2439 OP_SHARED_LIMITf, 98304)); 2440 for (idx = 0; idx < 10; idx++) { 2441 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_CONFIGUr(unit, p, idx, &rval)); 2442 soc_reg_field_set(unit, OP_QUEUE_CONFIGUr, &rval, Q_SHARED_LIMITf, 98304); 2443 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_CONFIGUr(unit, p, idx, rval)); 2444 } 2445 } 2446 2447 /* THDI */ 2448 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, TOTAL_SHARED_LIMITr, 2449 REG_PORT_ANY, 2450 TOTAL_SHARED_LIMITf, 61278)); 2451 PBMP_XE_ITER(unit, p) { 2452 uint32 xe_val[8] = {4, 4, 4, 4, 4, 4, 4, 4}; 2453 SOC_IF_ERROR_RETURN 2454 (soc_reg_field32_modify(unit, PORT_MINr, p, PORT_MINf, 8)); 2455 SOC_IF_ERROR_RETURN 2456 (soc_reg_field32_modify(unit, PORT_MAX_PKT_SIZEr, p, 2457 PORT_MAX_PKT_SIZEf, 72)); 2458 SOC_IF_ERROR_RETURN 2459 (soc_reg_field32_modify(unit, PORT_SHARED_LIMITr, p, 2460 PORT_SHARED_LIMITf, 24504)); 2461 SOC_IF_ERROR_RETURN 2462 (soc_reg_fields32_modify(unit, PG_THRESH_SELr, p, 8, 2463 pg_thresh, xe_val)); 2464 SOC_IF_ERROR_RETURN 2465 (soc_reg_field32_modify(unit, PORT_RESET_OFFSETr, p, 2466 PORT_RESET_OFFSETf, 512)); 2467 for (idx = 0; idx < 8; idx++) { 2468 SOC_IF_ERROR_RETURN(READ_PG_RESET_OFFSETr(unit, p, idx, &rval)); 2469 soc_reg_field_set(unit, PG_RESET_OFFSETr, &rval, PG_RESET_OFFSETf, 128); 2470 SOC_IF_ERROR_RETURN(WRITE_PG_RESET_OFFSETr(unit, p, idx, rval)); 2471 } 2472 for (idx = 0; idx < 8; idx++) { 2473 SOC_IF_ERROR_RETURN(READ_PG_MINr(unit, p, idx, &rval)); 2474 soc_reg_field_set(unit, PG_MINr, &rval, PG_MINf, 1024); 2475 SOC_IF_ERROR_RETURN(WRITE_PG_MINr(unit, p, idx, rval)); 2476 } 2477 for (idx = 0; idx < 8; idx++) { 2478 SOC_IF_ERROR_RETURN(READ_PG_HDRM_LIMITr(unit, p, idx, &rval)); 2479 soc_reg_field_set(unit, PG_HDRM_LIMITr, &rval, PG_HDRM_LIMITf, 1024); 2480 SOC_IF_ERROR_RETURN(WRITE_PG_HDRM_LIMITr(unit, p, idx, rval)); 2481 2482 } 2483 SOC_IF_ERROR_RETURN 2484 (soc_reg_field32_modify(unit, PORT_PRI_XON_ENABLEr, p, 2485 PORT_PRI_XON_ENABLEf, 0x3fff)); 2486 SOC_IF_ERROR_RETURN 2487 (soc_reg_field32_modify(unit, PORT_PRI_XON_ENABLEr, p, 2488 PORT_XON_ENABLEf, 1)); 2489 SOC_IF_ERROR_RETURN 2490 (soc_reg_field32_modify(unit, PORT_PRI_XON_ENABLEr, p, 2491 PORT_PG_PAUSE_DISABLEf, 0)); 2492 } 2493 PBMP_IL_ITER(unit, p) { 2494 uint32 il_val[8] = {2, 2, 2, 2, 2, 2, 2, 2}; 2495 SOC_IF_ERROR_RETURN 2496 (soc_reg_field32_modify(unit, PORT_MINr, p, PORT_MINf, 8)); 2497 SOC_IF_ERROR_RETURN 2498 (soc_reg_field32_modify(unit, PORT_MAX_PKT_SIZEr, p, 2499 PORT_MAX_PKT_SIZEf, 72)); 2500 SOC_IF_ERROR_RETURN 2501 (soc_reg_field32_modify(unit, PORT_SHARED_LIMITr, p, 2502 PORT_SHARED_LIMITf, 6072)); 2503 SOC_IF_ERROR_RETURN 2504 (soc_reg_fields32_modify(unit, PG_THRESH_SELr, p, 8, 2505 pg_thresh, il_val)); 2506 SOC_IF_ERROR_RETURN 2507 (soc_reg_field32_modify(unit, PORT_RESET_OFFSETr, p, 2508 PORT_RESET_OFFSETf, 512)); 2509 for (idx = 0; idx < 8; idx++) { 2510 SOC_IF_ERROR_RETURN(READ_PG_RESET_OFFSETr(unit, p, idx, &rval)); 2511 soc_reg_field_set(unit, PG_RESET_OFFSETr, &rval, PG_RESET_OFFSETf, 128); 2512 SOC_IF_ERROR_RETURN(WRITE_PG_RESET_OFFSETr(unit, p, idx, rval)); 2513 } 2514 for (idx = 0; idx < 8; idx++) { 2515 SOC_IF_ERROR_RETURN(READ_PG_MINr(unit, p, idx, &rval)); 2516 soc_reg_field_set(unit, PG_MINr, &rval, PG_MINf, 8); 2517 SOC_IF_ERROR_RETURN(WRITE_PG_MINr(unit, p, idx, rval)); 2518 } 2519 for (idx = 0; idx < 8; idx++) { 2520 SOC_IF_ERROR_RETURN(READ_PG_HDRM_LIMITr(unit, p, idx, &rval)); 2521 soc_reg_field_set(unit, PG_HDRM_LIMITr, &rval, PG_HDRM_LIMITf, 256); 2522 SOC_IF_ERROR_RETURN(WRITE_PG_HDRM_LIMITr(unit, p, idx, rval)); 2523 2524 } 2525 SOC_IF_ERROR_RETURN 2526 (soc_reg_field32_modify(unit, PORT_PRI_XON_ENABLEr, p, 2527 PORT_PRI_XON_ENABLEf, 0x3fff)); 2528 SOC_IF_ERROR_RETURN 2529 (soc_reg_field32_modify(unit, PORT_PRI_XON_ENABLEr, p, 2530 PORT_XON_ENABLEf, 1)); 2531 } 2532 for (idx = 0; idx < 8; idx++) { 2533 SOC_IF_ERROR_RETURN(READ_PG_RESET_OFFSETr(unit, 0, idx, &rval)); 2534 soc_reg_field_set(unit, PG_RESET_OFFSETr, &rval, PG_RESET_OFFSETf, 128); 2535 SOC_IF_ERROR_RETURN(WRITE_PG_RESET_OFFSETr(unit, 0, idx, rval)); 2536 } 2537 SOC_IF_ERROR_RETURN 2538 (soc_reg_field32_modify(unit, PORT_PRI_XON_ENABLEr, 0, 2539 PORT_XON_ENABLEf, 1)); 2540 SOC_IF_ERROR_RETURN 2541 (soc_reg_field32_modify(unit, PORT_MINr, 0, PORT_MINf, 2)); 2542 SOC_IF_ERROR_RETURN 2543 (soc_reg_field32_modify(unit, PORT_SHARED_LIMITr, 0, 2544 PORT_SHARED_LIMITf, 126)); 2545 SOC_IF_ERROR_RETURN 2546 (soc_reg_field32_modify(unit, PORT_RESET_OFFSETr, 0, 2547 PORT_RESET_OFFSETf, 16)); 2548 PBMP_ALL_ITER(unit, p) { 2549 SOC_IF_ERROR_RETURN 2550 (soc_reg_fields32_modify(unit, PORT_PRI_GRP0r, p, 7, 2551 pri_grp0, pri_grp0_val)); 2552 SOC_IF_ERROR_RETURN 2553 (soc_reg_fields32_modify(unit, PORT_PRI_GRP1r, p, 7, 2554 pri_grp1, pri_grp1_val)); 2555 } 2556 SOC_IF_ERROR_RETURN 2557 (soc_reg_field32_modify(unit, TOTAL_SHARED_AVAIL_THRESHr, 0, 2558 TOTAL_SHARED_AVAIL_THRESHf, 61022)); 2559 2560 /* WRED */ 2561 SOC_IF_ERROR_RETURN 2562 (soc_reg_field32_modify(unit, TIME_DOMAIN_CONFIGr, REG_PORT_ANY, 2563 LB_TIME_DOMAINf, 0)); 2564 SOC_IF_ERROR_RETURN 2565 (soc_reg_field32_modify(unit, TIME_DOMAIN_CONFIGr, REG_PORT_ANY, 2566 TIME_DOMAIN1f, 1)); 2567 SOC_IF_ERROR_RETURN 2568 (soc_reg_field32_modify(unit, TIME_DOMAIN_CONFIGr, REG_PORT_ANY, 2569 TIME_DOMAIN0f, 1)); 2570 PBMP_IL_ITER(unit, p) { 2571 SOC_IF_ERROR_RETURN 2572 (soc_reg_field32_modify(unit, PORT_WREDCONFIG_CELLr, p, 2573 LB_WEIGHTf, 4)); 2574 SOC_IF_ERROR_RETURN 2575 (soc_reg_field32_modify(unit, PORT_WREDCONFIG_CELLr, p, 2576 LB_ENABLEf, 1)); 2577 } 2578 PBMP_XE_ITER(unit, p) { 2579 for (idx = 0; idx < 8; idx++) { 2580 int j; 2581 SOC_IF_ERROR_RETURN(READ_WREDPARAM_START_CELLr(unit, p, idx, &rval)); 2582 soc_reg_field_set(unit, WREDPARAM_START_CELLr, &rval, 2583 DROPSTARTPOINTf, 2860); 2584 SOC_IF_ERROR_RETURN(WRITE_WREDPARAM_START_CELLr(unit, p, idx, rval)); 2585 2586 SOC_IF_ERROR_RETURN(READ_WREDPARAM_END_CELLr(unit, p, idx, &rval)); 2587 soc_reg_field_set(unit, WREDPARAM_END_CELLr, &rval, 2588 DROPENDPOINTf, 7150); 2589 SOC_IF_ERROR_RETURN(WRITE_WREDPARAM_END_CELLr(unit, p, idx, rval)); 2590 SOC_IF_ERROR_RETURN(READ_WREDCONFIG_CELLr(unit, p, idx, &rval)); 2591 for (j = 0; j < 7; j++) { 2592 soc_reg_field_set(unit, WREDCONFIG_CELLr, &rval, 2593 wredcfg_cell[j], wredcfg_cell_val[j]); 2594 } 2595 SOC_IF_ERROR_RETURN(WRITE_WREDCONFIG_CELLr(unit, p, idx, rval)); 2596 2597 SOC_IF_ERROR_RETURN(READ_WREDPARAM_YELLOW_START_CELLr(unit, p, idx, &rval)); 2598 soc_reg_field_set(unit, WREDPARAM_YELLOW_START_CELLr, &rval, 2599 YELLOW_DROPSTARTPOINTf, 2043); 2600 SOC_IF_ERROR_RETURN(WRITE_WREDPARAM_YELLOW_START_CELLr(unit, p, idx, rval)); 2601 2602 SOC_IF_ERROR_RETURN(READ_WREDPARAM_YELLOW_END_CELLr(unit, p, idx, &rval)); 2603 soc_reg_field_set(unit, WREDPARAM_YELLOW_END_CELLr, &rval, 2604 YELLOW_DROPENDPOINTf, 5720); 2605 SOC_IF_ERROR_RETURN(WRITE_WREDPARAM_YELLOW_END_CELLr(unit, p, idx, rval)); 2606 SOC_IF_ERROR_RETURN(READ_WREDPARAM_RED_START_CELLr(unit, p, idx, &rval)); 2607 soc_reg_field_set(unit, WREDPARAM_RED_START_CELLr, &rval, 2608 RED_DROPSTARTPOINTf, 1226); 2609 SOC_IF_ERROR_RETURN(WRITE_WREDPARAM_RED_START_CELLr(unit, p, idx, rval)); 2610 SOC_IF_ERROR_RETURN(READ_WREDPARAM_RED_END_CELLr(unit, p, idx, &rval)); 2611 soc_reg_field_set(unit, WREDPARAM_RED_END_CELLr, &rval, 2612 RED_DROPENDPOINTf, 4290); 2613 SOC_IF_ERROR_RETURN(WRITE_WREDPARAM_RED_END_CELLr(unit, p, idx, rval)); 2614 SOC_IF_ERROR_RETURN(READ_WREDPARAM_PRI0_START_CELLr(unit, p, idx, &rval)); 2615 soc_reg_field_set(unit, WREDPARAM_PRI0_START_CELLr, &rval, 2616 PRI0_DROPSTARTPOINTf, 817); 2617 SOC_IF_ERROR_RETURN(WRITE_WREDPARAM_PRI0_START_CELLr(unit, p, idx, rval)); 2618 SOC_IF_ERROR_RETURN(READ_WREDPARAM_PRI0_END_CELLr(unit, p, idx, &rval)); 2619 soc_reg_field_set(unit, WREDPARAM_PRI0_END_CELLr, &rval, 2620 PRI0_DROPENDPOINTf, 3575); 2621 SOC_IF_ERROR_RETURN(WRITE_WREDPARAM_PRI0_END_CELLr(unit, p, idx, rval)); 2622 } 2623 } 2624 2625 /* ES */ 2626 PBMP_PORT_ITER(unit, p) { 2627 SOC_IF_ERROR_RETURN 2628 (soc_reg_field32_modify(unit, ESCONFIGr, p, MTU_QUANTA_SELECTf, 2)); 2629 SOC_IF_ERROR_RETURN 2630 (soc_reg_field32_modify(unit, ESCONFIGr, p, SCHEDULING_SELECTf, 3)); 2631 for (idx = 0; idx < 8; idx++) { 2632 SOC_IF_ERROR_RETURN(READ_COSWEIGHTSr(unit, p, idx, &rval)); 2633 soc_reg_field_set(unit, COSWEIGHTSr, &rval, COSWEIGHTSf, cosw[idx]); 2634 SOC_IF_ERROR_RETURN(WRITE_COSWEIGHTSr(unit, p, idx, rval)); 2635 } 2636 } 2637 SOC_IF_ERROR_RETURN 2638 (soc_reg_field32_modify(unit, INPUT_PORT_RX_ENABLEr, REG_PORT_ANY, 2639 INPUT_PORT_RX_ENABLEf, 0x1ffff)); 2640 SOC_IF_ERROR_RETURN 2641 (soc_reg_field32_modify(unit, OUTPUT_PORT_RX_ENABLEr, REG_PORT_ANY, 2642 OUTPUT_PORT_RX_ENABLEf, 0x1ffff)); 2643 SOC_IF_ERROR_RETURN 2644 (soc_reg_field32_modify(unit, PORTGRP_WDRR_CONFIGr, REG_PORT_ANY, 2645 PG_WDRR_MTU_QUANTA_SELECTf, 2)); 2646 for (idx = 0; idx < 30; idx++) { 2647 SOC_IF_ERROR_RETURN 2648 (soc_mem_field32_modify(unit, ES_ARB_TDM_TABLEm, idx, 2649 PORT_VECTORf, es_arb_tdm_table[idx])); 2650 SOC_IF_ERROR_RETURN 2651 (soc_mem_field32_modify(unit, ES_ARB_TDM_TABLEm, idx, 2652 SHAPER_ENf, 0)); 2653 SOC_IF_ERROR_RETURN 2654 (soc_mem_field32_modify(unit, ES_ARB_TDM_TABLEm, idx, 2655 SHAPER_IDf, 0)); 2656 } 2657 SOC_IF_ERROR_RETURN 2658 (soc_reg_field32_modify(unit, ES_TDM_CAL_CFGr, REG_PORT_ANY, 2659 CURRENT_CALENDARf, 0)); 2660 SOC_IF_ERROR_RETURN 2661 (soc_reg_field32_modify(unit, ES_TDM_CAL_CFGr, REG_PORT_ANY, 2662 END_Af, 29)); 2663 SOC_IF_ERROR_RETURN 2664 (soc_reg_field32_modify(unit, ES_TDM_CAL_CFGr, REG_PORT_ANY, 2665 END_Bf, 29)); 2666 SOC_IF_ERROR_RETURN 2667 (soc_reg_field32_modify(unit, ES_TDM_CAL_CFGr, REG_PORT_ANY, 2668 SWITCH_CALENDARf, 0)); 2669 SOC_IF_ERROR_RETURN 2670 (soc_reg_field32_modify(unit, ES_TDM_ENr, REG_PORT_ANY, 2671 ENf, 1)); 2672 PBMP_IL_ITER(unit, p) { 2673 SOC_IF_ERROR_RETURN 2674 (soc_reg_field32_modify(unit, ES_PORTGRP_WDRR_WEIGHTSr, p, 2675 PORTWEIGHTSf, 1)); 2676 } 2677 2678 /* MTRO */ 2679 PBMP_XE_ITER(unit, p) { 2680 SOC_IF_ERROR_RETURN 2681 (soc_reg_field32_modify(unit, EGRMETERINGCONFIGr, p, 2682 METER_GRANf, 5)); 2683 SOC_IF_ERROR_RETURN 2684 (soc_reg_field32_modify(unit, EGRMETERINGCONFIG1r, p, 2685 REFRESHf, 156250)); 2686 } 2687 2688 /* INTF */ 2689 SOC_IF_ERROR_RETURN 2690 (soc_reg_field32_modify(unit, MMU_LLFC_TX_CONFIG_3r, REG_PORT_ANY, 2691 BW_TIMER_VALUE_9_16f, 0)); 2692 SOC_IF_ERROR_RETURN 2693 (soc_reg_field32_modify(unit, MMU_LLFC_TX_CONFIG_4r, REG_PORT_ANY, 2694 XOFF_REFRESH_TIME_9_16f, 32)); 2695 SOC_IF_ERROR_RETURN 2696 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI15r, REG_PORT_ANY, 2697 COS0_7_BMPf, 128)); 2698 SOC_IF_ERROR_RETURN 2699 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI14r, REG_PORT_ANY, 2700 COS0_7_BMPf, 128)); 2701 SOC_IF_ERROR_RETURN 2702 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI13r, REG_PORT_ANY, 2703 COS0_7_BMPf, 128)); 2704 SOC_IF_ERROR_RETURN 2705 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI12r, REG_PORT_ANY, 2706 COS0_7_BMPf, 128)); 2707 SOC_IF_ERROR_RETURN 2708 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI11r, REG_PORT_ANY, 2709 COS0_7_BMPf, 128)); 2710 SOC_IF_ERROR_RETURN 2711 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI10r, REG_PORT_ANY, 2712 COS0_7_BMPf, 128)); 2713 SOC_IF_ERROR_RETURN 2714 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI9r, REG_PORT_ANY, 2715 COS0_7_BMPf, 128)); 2716 SOC_IF_ERROR_RETURN 2717 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI8r, REG_PORT_ANY, 2718 COS0_7_BMPf, 128)); 2719 SOC_IF_ERROR_RETURN 2720 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI7r, REG_PORT_ANY, 2721 COS0_7_BMPf, 128)); 2722 SOC_IF_ERROR_RETURN 2723 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI6r, REG_PORT_ANY, 2724 COS0_7_BMPf, 64)); 2725 SOC_IF_ERROR_RETURN 2726 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI5r, REG_PORT_ANY, 2727 COS0_7_BMPf, 32)); 2728 SOC_IF_ERROR_RETURN 2729 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI4r, REG_PORT_ANY, 2730 COS0_7_BMPf, 16)); 2731 SOC_IF_ERROR_RETURN 2732 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI3r, REG_PORT_ANY, 2733 COS0_7_BMPf, 8)); 2734 SOC_IF_ERROR_RETURN 2735 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI2r, REG_PORT_ANY, 2736 COS0_7_BMPf, 4)); 2737 SOC_IF_ERROR_RETURN 2738 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI1r, REG_PORT_ANY, 2739 COS0_7_BMPf, 2)); 2740 SOC_IF_ERROR_RETURN 2741 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI0r, REG_PORT_ANY, 2742 COS0_7_BMPf, 1)); 2743 2744 /* AGING */ 2745 SOC_IF_ERROR_RETURN 2746 (soc_reg_field32_modify(unit, PKTAGINGTIMERr, REG_PORT_ANY, 2747 DURATIONSELECTf, 4096)); 2748 SOC_IF_ERROR_RETURN 2749 (soc_reg_fields32_modify(unit, PKTAGINGLIMIT0r, REG_PORT_ANY, 8, 2750 aging0_fld, aging0_val)); 2751 SOC_IF_ERROR_RETURN 2752 (soc_reg_fields32_modify(unit, PKTAGINGLIMIT1r, REG_PORT_ANY, 8, 2753 aging1_fld, aging1_val)); 2754 2755 /* CTR */ 2756 rval = 0; 2757 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, CNGf, 7); 2758 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, COSf, 15); 2759 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, DST_PORTf, 31); 2760 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, SRC_PORTf, 31); 2761 SOC_IF_ERROR_RETURN(WRITE_TX_CNT_CONFIGr_REG32(unit, 7, rval)); 2762 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, ALL_DROP_ACCEPTf, 1); 2763 SOC_IF_ERROR_RETURN(WRITE_TX_CNT_CONFIGr_REG32(unit, 6, rval)); 2764 rval = 0; 2765 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, CNGf, 7); 2766 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, COSf, 15); 2767 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, DST_PORTf, 31); 2768 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, SRC_PORTf, 31); 2769 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, ENQ_DEQf, 1); 2770 SOC_IF_ERROR_RETURN(WRITE_TX_CNT_CONFIGr_REG32(unit, 5, rval)); 2771 rval = 0; 2772 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, COSf, 15); 2773 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, DST_PORTf, 31); 2774 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, SRC_PORTf, 31); 2775 SOC_IF_ERROR_RETURN(WRITE_TX_CNT_CONFIGr_REG32(unit, 4, rval)); 2776 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, CNGf, 1); 2777 SOC_IF_ERROR_RETURN(WRITE_TX_CNT_CONFIGr_REG32(unit, 3, rval)); 2778 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, CNGf, 2); 2779 SOC_IF_ERROR_RETURN(WRITE_TX_CNT_CONFIGr_REG32(unit, 2, rval)); 2780 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, CNGf, 3); 2781 SOC_IF_ERROR_RETURN(WRITE_TX_CNT_CONFIGr_REG32(unit, 1, rval)); 2782 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, CNGf, 7); 2783 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, ECN_MARKEDf, 1); 2784 SOC_IF_ERROR_RETURN(WRITE_TX_CNT_CONFIGr_REG32(unit, 0, rval)); 2785 rval = 0; 2786 SOC_IF_ERROR_RETURN(READ_OP_EP_PORT_MAPPING_TABLE_1r(unit, &rval)); 2787 soc_reg_field_set(unit, OP_EP_PORT_MAPPING_TABLE_1r, &rval, PORT10_MAPPINGf, 9); 2788 soc_reg_field_set(unit, OP_EP_PORT_MAPPING_TABLE_1r, &rval, PORT11_MAPPINGf, 9); 2789 soc_reg_field_set(unit, OP_EP_PORT_MAPPING_TABLE_1r, &rval, PORT12_MAPPINGf, 9); 2790 SOC_IF_ERROR_RETURN(WRITE_OP_EP_PORT_MAPPING_TABLE_1r(unit, rval)); 2791 rval = 0; 2792 SOC_IF_ERROR_RETURN(READ_OP_EP_PORT_MAPPING_TABLE_2r(unit, &rval)); 2793 soc_reg_field_set(unit, OP_EP_PORT_MAPPING_TABLE_2r, &rval, PORT14_MAPPINGf, 0xd); 2794 soc_reg_field_set(unit, OP_EP_PORT_MAPPING_TABLE_2r, &rval, PORT15_MAPPINGf, 0xd); 2795 soc_reg_field_set(unit, OP_EP_PORT_MAPPING_TABLE_2r, &rval, PORT16_MAPPINGf, 0xd); 2796 SOC_IF_ERROR_RETURN(WRITE_OP_EP_PORT_MAPPING_TABLE_2r(unit, rval)); 2797 2798 return SOC_E_NONE; 2799 } 2800 2801 /* 2802 * MMU Configurations for TDM6 2803 * 2x40G to 40G(Interlaken) 2804 * Refered to SOC script : radian_init_88732_2X40G+1X40G_IL.soc 2805 */ 2806 2807 STATIC 2808 int _shadow_tdm6_mmu_init(int unit) 2809 { 2810 soc_port_t p; 2811 int idx; 2812 soc_field_t pg_thresh[8] = {PG0_THRESH_SELf, PG1_THRESH_SELf, 2813 PG2_THRESH_SELf, PG3_THRESH_SELf, 2814 PG4_THRESH_SELf, PG5_THRESH_SELf, 2815 PG6_THRESH_SELf, PG7_THRESH_SELf}; 2816 soc_field_t pri_grp0[7] = {PRI0_GRPf, PRI1_GRPf, PRI2_GRPf, PRI3_GRPf, 2817 PRI4_GRPf, PRI5_GRPf, PRI6_GRPf}; 2818 soc_field_t pri_grp1[7] = {PRI7_GRPf, PRI8_GRPf, PRI9_GRPf, PRI10_GRPf, 2819 PRI11_GRPf, PRI12_GRPf, PRI13_GRPf}; 2820 soc_field_t wredcfg_cell[7] = {MAXDROPRATEf, YELLOW_MAXDROPRATEf, 2821 RED_MAXDROPRATEf, PRI0_MAXDROPRATEf, 2822 WEIGHTf, CAP_AVERAGEf, ENABLEf}; 2823 soc_field_t aging0_fld[8] = {AGINGLIMITPRI7f, AGINGLIMITPRI6f, 2824 AGINGLIMITPRI5f, AGINGLIMITPRI4f, 2825 AGINGLIMITPRI3f, AGINGLIMITPRI2f, 2826 AGINGLIMITPRI1f, AGINGLIMITPRI0f}; 2827 soc_field_t aging1_fld[8] = {AGINGLIMITPRI15f, AGINGLIMITPRI14f, 2828 AGINGLIMITPRI13f, AGINGLIMITPRI12f, 2829 AGINGLIMITPRI11f, AGINGLIMITPRI10f, 2830 AGINGLIMITPRI9f, AGINGLIMITPRI8f}; 2831 uint32 es_arb_tdm_table[30] = 2832 {0x2, 0x1fe00, 0x20, 0x0, 0x0, 0x2, 2833 0x1fe00, 0x20, 0x0, 0x0, 0x2, 0x1fe00, 2834 0x20, 0x0, 0x1, 0x2, 0x1fe00, 0x20, 2835 0x0, 0x0, 0x2, 0x1fe00, 0x20, 0x0, 2836 0x0, 0x2, 0x1fe00, 0x20, 0x0, 0x0}; 2837 2838 uint32 pri_grp0_val[7] = {0, 1, 2, 3, 4, 5, 6}; 2839 uint32 pri_grp1_val[7] = {7, 7, 7, 7, 7, 7, 7}; 2840 uint32 wredcfg_cell_val[7] = {10, 10, 10, 10, 4, 1, 1}; 2841 uint32 cosw[8] = {1, 8, 16, 24, 32, 64, 127, 0}; 2842 uint32 aging0_val[8] = {1, 1, 5, 5, 5, 5, 5, 5}; 2843 uint32 aging1_val[8] = {1, 1, 1, 1, 1, 1, 1, 1}; 2844 2845 uint32 rval; 2846 2847 /* CFAP */ 2848 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, CFAPCONFIGr, REG_PORT_ANY, 2849 START_CFAP_INITf, 1)); 2850 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, CFAPFULLTHRESHOLD0r, 2851 REG_PORT_ANY, 2852 CFAPFULLSETPOINTf, 98160)); 2853 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, CFAPFULLTHRESHOLD1r, 2854 REG_PORT_ANY, 2855 CFAPFULLRESETPOINTf, 98016)); 2856 2857 /* THDO */ 2858 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, THDO_BYPASSr, REG_PORT_ANY, 2859 OUTPUT_THRESHOLD_BYPASSf, 0)); 2860 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, OP_BUFFER_SHARED_LIMITr, 2861 REG_PORT_ANY, 2862 OP_BUFFER_SHARED_LIMITf, 98304)); 2863 PBMP_ALL_ITER(unit, p) { 2864 SOC_IF_ERROR_RETURN 2865 (soc_reg_field32_modify(unit, OP_PORT_CONFIGUr, p, 2866 OP_SHARED_LIMITf, 98304)); 2867 for (idx = 0; idx < 10; idx++) { 2868 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_CONFIGUr(unit, p, idx, &rval)); 2869 soc_reg_field_set(unit, OP_QUEUE_CONFIGUr, &rval, Q_SHARED_LIMITf, 98304); 2870 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_CONFIGUr(unit, p, idx, rval)); 2871 } 2872 } 2873 2874 /* THDI */ 2875 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, TOTAL_SHARED_LIMITr, 2876 REG_PORT_ANY, 2877 TOTAL_SHARED_LIMITf, 61278)); 2878 PBMP_XE_ITER(unit, p) { 2879 uint32 xe_val[8] = {4, 4, 4, 4, 4, 4, 4, 4}; 2880 SOC_IF_ERROR_RETURN 2881 (soc_reg_field32_modify(unit, PORT_MINr, p, PORT_MINf, 8)); 2882 SOC_IF_ERROR_RETURN 2883 (soc_reg_field32_modify(unit, PORT_MAX_PKT_SIZEr, p, 2884 PORT_MAX_PKT_SIZEf, 72)); 2885 SOC_IF_ERROR_RETURN 2886 (soc_reg_field32_modify(unit, PORT_SHARED_LIMITr, p, 2887 PORT_SHARED_LIMITf, 24504)); 2888 SOC_IF_ERROR_RETURN 2889 (soc_reg_fields32_modify(unit, PG_THRESH_SELr, p, 8, 2890 pg_thresh, xe_val)); 2891 SOC_IF_ERROR_RETURN 2892 (soc_reg_field32_modify(unit, PORT_RESET_OFFSETr, p, 2893 PORT_RESET_OFFSETf, 512)); 2894 for (idx = 0; idx < 8; idx++) { 2895 SOC_IF_ERROR_RETURN(READ_PG_RESET_OFFSETr(unit, p, idx, &rval)); 2896 soc_reg_field_set(unit, PG_RESET_OFFSETr, &rval, PG_RESET_OFFSETf, 128); 2897 SOC_IF_ERROR_RETURN(WRITE_PG_RESET_OFFSETr(unit, p, idx, rval)); 2898 } 2899 for (idx = 0; idx < 8; idx++) { 2900 SOC_IF_ERROR_RETURN(READ_PG_MINr(unit, p, idx, &rval)); 2901 soc_reg_field_set(unit, PG_MINr, &rval, PG_MINf, 1024); 2902 SOC_IF_ERROR_RETURN(WRITE_PG_MINr(unit, p, idx, rval)); 2903 } 2904 for (idx = 0; idx < 8; idx++) { 2905 SOC_IF_ERROR_RETURN(READ_PG_HDRM_LIMITr(unit, p, idx, &rval)); 2906 soc_reg_field_set(unit, PG_HDRM_LIMITr, &rval, PG_HDRM_LIMITf, 2907 1024); 2908 SOC_IF_ERROR_RETURN(WRITE_PG_HDRM_LIMITr(unit, p, idx, rval)); 2909 2910 } 2911 SOC_IF_ERROR_RETURN 2912 (soc_reg_field32_modify(unit, PORT_PRI_XON_ENABLEr, p, 2913 PORT_PRI_XON_ENABLEf, 0x3fff)); 2914 SOC_IF_ERROR_RETURN 2915 (soc_reg_field32_modify(unit, PORT_PRI_XON_ENABLEr, p, 2916 PORT_XON_ENABLEf, 1)); 2917 SOC_IF_ERROR_RETURN 2918 (soc_reg_field32_modify(unit, PORT_PRI_XON_ENABLEr, p, 2919 PORT_PG_PAUSE_DISABLEf, 0)); 2920 } 2921 PBMP_IL_ITER(unit, p) { 2922 uint32 il_val[8] = {2, 2, 2, 2, 2, 2, 2, 2}; 2923 SOC_IF_ERROR_RETURN 2924 (soc_reg_field32_modify(unit, PORT_MINr, p, PORT_MINf, 8)); 2925 SOC_IF_ERROR_RETURN 2926 (soc_reg_field32_modify(unit, PORT_MAX_PKT_SIZEr, p, 2927 PORT_MAX_PKT_SIZEf, 72)); 2928 SOC_IF_ERROR_RETURN 2929 (soc_reg_field32_modify(unit, PORT_SHARED_LIMITr, p, 2930 PORT_SHARED_LIMITf, 6072)); 2931 SOC_IF_ERROR_RETURN 2932 (soc_reg_fields32_modify(unit, PG_THRESH_SELr, p, 8, 2933 pg_thresh, il_val)); 2934 SOC_IF_ERROR_RETURN 2935 (soc_reg_field32_modify(unit, PORT_RESET_OFFSETr, p, 2936 PORT_RESET_OFFSETf, 512)); 2937 for (idx = 0; idx < 8; idx++) { 2938 SOC_IF_ERROR_RETURN(READ_PG_RESET_OFFSETr(unit, p, idx, &rval)); 2939 soc_reg_field_set(unit, PG_RESET_OFFSETr, &rval, PG_RESET_OFFSETf, 128); 2940 SOC_IF_ERROR_RETURN(WRITE_PG_RESET_OFFSETr(unit, p, idx, rval)); 2941 } 2942 for (idx = 0; idx < 8; idx++) { 2943 SOC_IF_ERROR_RETURN(READ_PG_MINr(unit, p, idx, &rval)); 2944 soc_reg_field_set(unit, PG_MINr, &rval, PG_MINf, 8); 2945 SOC_IF_ERROR_RETURN(WRITE_PG_MINr(unit, p, idx, rval)); 2946 } 2947 for (idx = 0; idx < 8; idx++) { 2948 SOC_IF_ERROR_RETURN(READ_PG_HDRM_LIMITr(unit, p, idx, &rval)); 2949 soc_reg_field_set(unit, PG_HDRM_LIMITr, &rval, PG_HDRM_LIMITf, 256); 2950 SOC_IF_ERROR_RETURN(WRITE_PG_HDRM_LIMITr(unit, p, idx, rval)); 2951 2952 } 2953 SOC_IF_ERROR_RETURN 2954 (soc_reg_field32_modify(unit, PORT_PRI_XON_ENABLEr, p, 2955 PORT_PRI_XON_ENABLEf, 0x3fff)); 2956 SOC_IF_ERROR_RETURN 2957 (soc_reg_field32_modify(unit, PORT_PRI_XON_ENABLEr, p, 2958 PORT_XON_ENABLEf, 1)); 2959 } 2960 SOC_IF_ERROR_RETURN 2961 (soc_reg_field32_modify(unit, PORT_MINr, 0, PORT_MINf, 2)); 2962 SOC_IF_ERROR_RETURN 2963 (soc_reg_field32_modify(unit, PORT_SHARED_LIMITr, 0, 2964 PORT_SHARED_LIMITf, 126)); 2965 SOC_IF_ERROR_RETURN 2966 (soc_reg_field32_modify(unit, PORT_RESET_OFFSETr, 0, 2967 PORT_RESET_OFFSETf, 16)); 2968 PBMP_ALL_ITER(unit, p) { 2969 SOC_IF_ERROR_RETURN 2970 (soc_reg_fields32_modify(unit, PORT_PRI_GRP0r, p, 7, 2971 pri_grp0, pri_grp0_val)); 2972 SOC_IF_ERROR_RETURN 2973 (soc_reg_fields32_modify(unit, PORT_PRI_GRP1r, p, 7, 2974 pri_grp1, pri_grp1_val)); 2975 } 2976 SOC_IF_ERROR_RETURN 2977 (soc_reg_field32_modify(unit, TOTAL_SHARED_AVAIL_THRESHr, 0, 2978 TOTAL_SHARED_AVAIL_THRESHf, 61022)); 2979 2980 /* WRED */ 2981 SOC_IF_ERROR_RETURN 2982 (soc_reg_field32_modify(unit, TIME_DOMAIN_CONFIGr, REG_PORT_ANY, 2983 LB_TIME_DOMAINf, 0)); 2984 SOC_IF_ERROR_RETURN 2985 (soc_reg_field32_modify(unit, TIME_DOMAIN_CONFIGr, REG_PORT_ANY, 2986 TIME_DOMAIN1f, 1)); 2987 SOC_IF_ERROR_RETURN 2988 (soc_reg_field32_modify(unit, TIME_DOMAIN_CONFIGr, REG_PORT_ANY, 2989 TIME_DOMAIN0f, 1)); 2990 PBMP_IL_ITER(unit, p) { 2991 SOC_IF_ERROR_RETURN 2992 (soc_reg_field32_modify(unit, PORT_WREDCONFIG_CELLr, p, 2993 LB_WEIGHTf, 4)); 2994 SOC_IF_ERROR_RETURN 2995 (soc_reg_field32_modify(unit, PORT_WREDCONFIG_CELLr, p, 2996 LB_ENABLEf, 1)); 2997 } 2998 PBMP_XE_ITER(unit, p) { 2999 for (idx = 0; idx < 8; idx++) { 3000 int j; 3001 SOC_IF_ERROR_RETURN(READ_WREDPARAM_START_CELLr(unit, p, idx, &rval)); 3002 soc_reg_field_set(unit, WREDPARAM_START_CELLr, &rval, 3003 DROPSTARTPOINTf, 2860); 3004 SOC_IF_ERROR_RETURN(WRITE_WREDPARAM_START_CELLr(unit, p, idx, rval)); 3005 3006 SOC_IF_ERROR_RETURN(READ_WREDPARAM_END_CELLr(unit, p, idx, &rval)); 3007 soc_reg_field_set(unit, WREDPARAM_END_CELLr, &rval, 3008 DROPENDPOINTf, 7150); 3009 SOC_IF_ERROR_RETURN(WRITE_WREDPARAM_END_CELLr(unit, p, idx, rval)); 3010 SOC_IF_ERROR_RETURN(READ_WREDCONFIG_CELLr(unit, p, idx, &rval)); 3011 for (j = 0; j < 7; j++) { 3012 soc_reg_field_set(unit, WREDCONFIG_CELLr, &rval, 3013 wredcfg_cell[j], wredcfg_cell_val[j]); 3014 } 3015 SOC_IF_ERROR_RETURN(WRITE_WREDCONFIG_CELLr(unit, p, idx, rval)); 3016 3017 SOC_IF_ERROR_RETURN(READ_WREDPARAM_YELLOW_START_CELLr(unit, p, idx, &rval)); 3018 soc_reg_field_set(unit, WREDPARAM_YELLOW_START_CELLr, &rval, 3019 YELLOW_DROPSTARTPOINTf, 2043); 3020 SOC_IF_ERROR_RETURN(WRITE_WREDPARAM_YELLOW_START_CELLr(unit, p, idx, rval)); 3021 3022 SOC_IF_ERROR_RETURN(READ_WREDPARAM_YELLOW_END_CELLr(unit, p, idx, &rval)); 3023 soc_reg_field_set(unit, WREDPARAM_YELLOW_END_CELLr, &rval, 3024 YELLOW_DROPENDPOINTf, 5720); 3025 SOC_IF_ERROR_RETURN(WRITE_WREDPARAM_YELLOW_END_CELLr(unit, p, idx, rval)); 3026 SOC_IF_ERROR_RETURN(READ_WREDPARAM_RED_START_CELLr(unit, p, idx, &rval)); 3027 soc_reg_field_set(unit, WREDPARAM_RED_START_CELLr, &rval, 3028 RED_DROPSTARTPOINTf, 1226); 3029 SOC_IF_ERROR_RETURN(WRITE_WREDPARAM_RED_START_CELLr(unit, p, idx, rval)); 3030 SOC_IF_ERROR_RETURN(READ_WREDPARAM_RED_END_CELLr(unit, p, idx, &rval)); 3031 soc_reg_field_set(unit, WREDPARAM_RED_END_CELLr, &rval, 3032 RED_DROPENDPOINTf, 4290); 3033 SOC_IF_ERROR_RETURN(WRITE_WREDPARAM_RED_END_CELLr(unit, p, idx, rval)); 3034 SOC_IF_ERROR_RETURN(READ_WREDPARAM_PRI0_START_CELLr(unit, p, idx, &rval)); 3035 soc_reg_field_set(unit, WREDPARAM_PRI0_START_CELLr, &rval, 3036 PRI0_DROPSTARTPOINTf, 817); 3037 SOC_IF_ERROR_RETURN(WRITE_WREDPARAM_PRI0_START_CELLr(unit, p, idx, rval)); 3038 SOC_IF_ERROR_RETURN(READ_WREDPARAM_PRI0_END_CELLr(unit, p, idx, &rval)); 3039 soc_reg_field_set(unit, WREDPARAM_PRI0_END_CELLr, &rval, 3040 PRI0_DROPENDPOINTf, 3575); 3041 SOC_IF_ERROR_RETURN(WRITE_WREDPARAM_PRI0_END_CELLr(unit, p, idx, rval)); 3042 } 3043 } 3044 3045 /* ES */ 3046 PBMP_PORT_ITER(unit, p) { 3047 SOC_IF_ERROR_RETURN 3048 (soc_reg_field32_modify(unit, ESCONFIGr, p, MTU_QUANTA_SELECTf, 2)); 3049 SOC_IF_ERROR_RETURN 3050 (soc_reg_field32_modify(unit, ESCONFIGr, p, SCHEDULING_SELECTf, 3)); 3051 for (idx = 0; idx < 8; idx++) { 3052 SOC_IF_ERROR_RETURN(READ_COSWEIGHTSr(unit, p, idx, &rval)); 3053 soc_reg_field_set(unit, COSWEIGHTSr, &rval, COSWEIGHTSf, cosw[idx]); 3054 SOC_IF_ERROR_RETURN(WRITE_COSWEIGHTSr(unit, p, idx, rval)); 3055 } 3056 } 3057 SOC_IF_ERROR_RETURN 3058 (soc_reg_field32_modify(unit, INPUT_PORT_RX_ENABLEr, REG_PORT_ANY, 3059 INPUT_PORT_RX_ENABLEf, 0x1ffff)); 3060 SOC_IF_ERROR_RETURN 3061 (soc_reg_field32_modify(unit, OUTPUT_PORT_RX_ENABLEr, REG_PORT_ANY, 3062 OUTPUT_PORT_RX_ENABLEf, 0x1ffff)); 3063 SOC_IF_ERROR_RETURN 3064 (soc_reg_field32_modify(unit, PORTGRP_WDRR_CONFIGr, REG_PORT_ANY, 3065 PG_WDRR_MTU_QUANTA_SELECTf, 2)); 3066 for (idx = 0; idx < 30; idx++) { 3067 SOC_IF_ERROR_RETURN 3068 (soc_mem_field32_modify(unit, ES_ARB_TDM_TABLEm, idx, 3069 PORT_VECTORf, es_arb_tdm_table[idx])); 3070 SOC_IF_ERROR_RETURN 3071 (soc_mem_field32_modify(unit, ES_ARB_TDM_TABLEm, idx, 3072 SHAPER_ENf, 0)); 3073 SOC_IF_ERROR_RETURN 3074 (soc_mem_field32_modify(unit, ES_ARB_TDM_TABLEm, idx, 3075 SHAPER_IDf, 0)); 3076 } 3077 SOC_IF_ERROR_RETURN 3078 (soc_reg_field32_modify(unit, ES_TDM_CAL_CFGr, REG_PORT_ANY, 3079 CURRENT_CALENDARf, 0)); 3080 SOC_IF_ERROR_RETURN 3081 (soc_reg_field32_modify(unit, ES_TDM_CAL_CFGr, REG_PORT_ANY, 3082 END_Af, 0x1d)); 3083 SOC_IF_ERROR_RETURN 3084 (soc_reg_field32_modify(unit, ES_TDM_CAL_CFGr, REG_PORT_ANY, 3085 END_Bf, 0x1d)); 3086 SOC_IF_ERROR_RETURN 3087 (soc_reg_field32_modify(unit, ES_TDM_CAL_CFGr, REG_PORT_ANY, 3088 SWITCH_CALENDARf, 0)); 3089 SOC_IF_ERROR_RETURN 3090 (soc_reg_field32_modify(unit, ES_TDM_ENr, REG_PORT_ANY, 3091 ENf, 1)); 3092 PBMP_IL_ITER(unit, p) { 3093 SOC_IF_ERROR_RETURN 3094 (soc_reg_field32_modify(unit, ES_PORTGRP_WDRR_WEIGHTSr, p, 3095 PORTWEIGHTSf, 1)); 3096 } 3097 3098 /* MTRO */ 3099 PBMP_XE_ITER(unit, p) { 3100 SOC_IF_ERROR_RETURN 3101 (soc_reg_field32_modify(unit, EGRMETERINGCONFIGr, p, 3102 METER_GRANf, 5)); 3103 SOC_IF_ERROR_RETURN 3104 (soc_reg_field32_modify(unit, EGRMETERINGCONFIG1r, p, 3105 REFRESHf, 156250)); 3106 } 3107 3108 /* INTF */ 3109 SOC_IF_ERROR_RETURN 3110 (soc_reg_field32_modify(unit, MMU_LLFC_TX_CONFIG_3r, REG_PORT_ANY, 3111 BW_TIMER_VALUE_9_16f, 0)); 3112 SOC_IF_ERROR_RETURN 3113 (soc_reg_field32_modify(unit, MMU_LLFC_TX_CONFIG_4r, REG_PORT_ANY, 3114 XOFF_REFRESH_TIME_9_16f, 32)); 3115 SOC_IF_ERROR_RETURN 3116 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI15r, REG_PORT_ANY, 3117 COS0_7_BMPf, 128)); 3118 SOC_IF_ERROR_RETURN 3119 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI14r, REG_PORT_ANY, 3120 COS0_7_BMPf, 128)); 3121 SOC_IF_ERROR_RETURN 3122 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI13r, REG_PORT_ANY, 3123 COS0_7_BMPf, 128)); 3124 SOC_IF_ERROR_RETURN 3125 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI12r, REG_PORT_ANY, 3126 COS0_7_BMPf, 128)); 3127 SOC_IF_ERROR_RETURN 3128 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI11r, REG_PORT_ANY, 3129 COS0_7_BMPf, 128)); 3130 SOC_IF_ERROR_RETURN 3131 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI10r, REG_PORT_ANY, 3132 COS0_7_BMPf, 128)); 3133 SOC_IF_ERROR_RETURN 3134 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI9r, REG_PORT_ANY, 3135 COS0_7_BMPf, 128)); 3136 SOC_IF_ERROR_RETURN 3137 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI8r, REG_PORT_ANY, 3138 COS0_7_BMPf, 128)); 3139 SOC_IF_ERROR_RETURN 3140 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI7r, REG_PORT_ANY, 3141 COS0_7_BMPf, 128)); 3142 SOC_IF_ERROR_RETURN 3143 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI6r, REG_PORT_ANY, 3144 COS0_7_BMPf, 64)); 3145 SOC_IF_ERROR_RETURN 3146 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI5r, REG_PORT_ANY, 3147 COS0_7_BMPf, 32)); 3148 SOC_IF_ERROR_RETURN 3149 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI4r, REG_PORT_ANY, 3150 COS0_7_BMPf, 16)); 3151 SOC_IF_ERROR_RETURN 3152 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI3r, REG_PORT_ANY, 3153 COS0_7_BMPf, 8)); 3154 SOC_IF_ERROR_RETURN 3155 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI2r, REG_PORT_ANY, 3156 COS0_7_BMPf, 4)); 3157 SOC_IF_ERROR_RETURN 3158 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI1r, REG_PORT_ANY, 3159 COS0_7_BMPf, 2)); 3160 SOC_IF_ERROR_RETURN 3161 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI0r, REG_PORT_ANY, 3162 COS0_7_BMPf, 1)); 3163 3164 /* AGING */ 3165 SOC_IF_ERROR_RETURN 3166 (soc_reg_field32_modify(unit, PKTAGINGTIMERr, REG_PORT_ANY, 3167 DURATIONSELECTf, 4096)); 3168 SOC_IF_ERROR_RETURN 3169 (soc_reg_fields32_modify(unit, PKTAGINGLIMIT0r, REG_PORT_ANY, 8, 3170 aging0_fld, aging0_val)); 3171 SOC_IF_ERROR_RETURN 3172 (soc_reg_fields32_modify(unit, PKTAGINGLIMIT1r, REG_PORT_ANY, 8, 3173 aging1_fld, aging1_val)); 3174 3175 /* CTR */ 3176 rval = 0; 3177 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, CNGf, 7); 3178 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, COSf, 15); 3179 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, DST_PORTf, 31); 3180 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, SRC_PORTf, 31); 3181 SOC_IF_ERROR_RETURN(WRITE_TX_CNT_CONFIGr_REG32(unit, 7, rval)); 3182 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, ALL_DROP_ACCEPTf, 1); 3183 SOC_IF_ERROR_RETURN(WRITE_TX_CNT_CONFIGr_REG32(unit, 6, rval)); 3184 rval = 0; 3185 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, CNGf, 7); 3186 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, COSf, 15); 3187 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, DST_PORTf, 31); 3188 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, SRC_PORTf, 31); 3189 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, ENQ_DEQf, 1); 3190 SOC_IF_ERROR_RETURN(WRITE_TX_CNT_CONFIGr_REG32(unit, 5, rval)); 3191 rval = 0; 3192 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, COSf, 15); 3193 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, DST_PORTf, 31); 3194 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, SRC_PORTf, 31); 3195 SOC_IF_ERROR_RETURN(WRITE_TX_CNT_CONFIGr_REG32(unit, 4, rval)); 3196 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, CNGf, 1); 3197 SOC_IF_ERROR_RETURN(WRITE_TX_CNT_CONFIGr_REG32(unit, 3, rval)); 3198 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, CNGf, 2); 3199 SOC_IF_ERROR_RETURN(WRITE_TX_CNT_CONFIGr_REG32(unit, 2, rval)); 3200 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, CNGf, 3); 3201 SOC_IF_ERROR_RETURN(WRITE_TX_CNT_CONFIGr_REG32(unit, 1, rval)); 3202 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, CNGf, 7); 3203 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, ECN_MARKEDf, 1); 3204 SOC_IF_ERROR_RETURN(WRITE_TX_CNT_CONFIGr_REG32(unit, 0, rval)); 3205 rval = 0; 3206 SOC_IF_ERROR_RETURN(READ_OP_EP_PORT_MAPPING_TABLE_1r(unit, &rval)); 3207 soc_reg_field_set(unit, OP_EP_PORT_MAPPING_TABLE_1r, &rval, PORT10_MAPPINGf, 9); 3208 soc_reg_field_set(unit, OP_EP_PORT_MAPPING_TABLE_1r, &rval, PORT11_MAPPINGf, 9); 3209 soc_reg_field_set(unit, OP_EP_PORT_MAPPING_TABLE_1r, &rval, PORT12_MAPPINGf, 9); 3210 SOC_IF_ERROR_RETURN(WRITE_OP_EP_PORT_MAPPING_TABLE_1r(unit, rval)); 3211 rval = 0; 3212 SOC_IF_ERROR_RETURN(READ_OP_EP_PORT_MAPPING_TABLE_2r(unit, &rval)); 3213 soc_reg_field_set(unit, OP_EP_PORT_MAPPING_TABLE_2r, &rval, PORT13_MAPPINGf, 9); 3214 soc_reg_field_set(unit, OP_EP_PORT_MAPPING_TABLE_2r, &rval, PORT14_MAPPINGf, 9); 3215 soc_reg_field_set(unit, OP_EP_PORT_MAPPING_TABLE_2r, &rval, PORT15_MAPPINGf, 9); 3216 soc_reg_field_set(unit, OP_EP_PORT_MAPPING_TABLE_2r, &rval, PORT16_MAPPINGf, 9); 3217 SOC_IF_ERROR_RETURN(WRITE_OP_EP_PORT_MAPPING_TABLE_2r(unit, rval)); 3218 3219 return SOC_E_NONE; 3220 } 3221 3222 /* 3223 * Shadow MMU Configuration 3224 * MMU configurations for each TDM mode 3225 */ 3226 3227 STATIC 3228 int _shadow_tdm7_mmu_init(int unit) 3229 { 3230 soc_port_t p; 3231 int idx; 3232 soc_field_t pg_thresh[8] = {PG0_THRESH_SELf, PG1_THRESH_SELf, 3233 PG2_THRESH_SELf, PG3_THRESH_SELf, 3234 PG4_THRESH_SELf, PG5_THRESH_SELf, 3235 PG6_THRESH_SELf, PG7_THRESH_SELf}; 3236 soc_field_t pri_grp0[7] = {PRI0_GRPf, PRI1_GRPf, PRI2_GRPf, PRI3_GRPf, 3237 PRI4_GRPf, PRI5_GRPf, PRI6_GRPf}; 3238 soc_field_t pri_grp1[7] = {PRI7_GRPf, PRI8_GRPf, PRI9_GRPf, PRI10_GRPf, 3239 PRI11_GRPf, PRI12_GRPf, PRI13_GRPf}; 3240 soc_field_t wredcfg_cell[7] = {MAXDROPRATEf, YELLOW_MAXDROPRATEf, 3241 RED_MAXDROPRATEf, PRI0_MAXDROPRATEf, 3242 WEIGHTf, CAP_AVERAGEf, ENABLEf}; 3243 soc_field_t aging0_fld[8] = {AGINGLIMITPRI7f, AGINGLIMITPRI6f, 3244 AGINGLIMITPRI5f, AGINGLIMITPRI4f, 3245 AGINGLIMITPRI3f, AGINGLIMITPRI2f, 3246 AGINGLIMITPRI1f, AGINGLIMITPRI0f}; 3247 soc_field_t aging1_fld[8] = {AGINGLIMITPRI15f, AGINGLIMITPRI14f, 3248 AGINGLIMITPRI13f, AGINGLIMITPRI12f, 3249 AGINGLIMITPRI11f, AGINGLIMITPRI10f, 3250 AGINGLIMITPRI9f, AGINGLIMITPRI8f}; 3251 uint32 pri_grp0_val[7] = {0, 1, 2, 3, 4, 5, 6}; 3252 uint32 pri_grp1_val[7] = {7, 7, 7, 7, 7, 7, 7}; 3253 uint32 wredcfg_cell_val[7] = {10, 10, 10, 10, 4, 1, 1}; 3254 uint32 cosw[8] = {1, 8, 16, 24, 32, 64, 127, 0}; 3255 uint32 aging0_val[8] = {1, 1, 5, 5, 5, 5, 5, 5}; 3256 uint32 aging1_val[8] = {1, 1, 1, 1, 1, 1, 1, 1}; 3257 3258 uint32 rval; 3259 3260 /* CFAP */ 3261 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, CFAPCONFIGr, REG_PORT_ANY, 3262 START_CFAP_INITf, 1)); 3263 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, CFAPFULLTHRESHOLD0r, 3264 REG_PORT_ANY, 3265 CFAPFULLSETPOINTf, 98160)); 3266 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, CFAPFULLTHRESHOLD1r, 3267 REG_PORT_ANY, 3268 CFAPFULLRESETPOINTf, 98016)); 3269 3270 /* THDO */ 3271 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, THDO_BYPASSr, REG_PORT_ANY, 3272 OUTPUT_THRESHOLD_BYPASSf, 0)); 3273 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, OP_BUFFER_SHARED_LIMITr, 3274 REG_PORT_ANY, 3275 OP_BUFFER_SHARED_LIMITf, 98304)); 3276 PBMP_ALL_ITER(unit, p) { 3277 SOC_IF_ERROR_RETURN 3278 (soc_reg_field32_modify(unit, OP_PORT_CONFIGUr, p, 3279 OP_SHARED_LIMITf, 98304)); 3280 SOC_IF_ERROR_RETURN 3281 (soc_reg_field32_modify(unit, OP_QUEUE_CONFIGUr, p, 3282 Q_SHARED_LIMITf, 98304)); 3283 } 3284 3285 /* THDI */ 3286 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, TOTAL_SHARED_LIMITr, 3287 REG_PORT_ANY, 3288 TOTAL_SHARED_LIMITf, 66222)); 3289 PBMP_XE_ITER(unit, p) { 3290 uint32 xe_val[8] = {4, 4, 4, 4, 4, 4, 4, 4}; 3291 SOC_IF_ERROR_RETURN 3292 (soc_reg_field32_modify(unit, PORT_MINr, p, PORT_MINf, 8)); 3293 SOC_IF_ERROR_RETURN 3294 (soc_reg_field32_modify(unit, PORT_MAX_PKT_SIZEr, p, 3295 PORT_MAX_PKT_SIZEf, 72)); 3296 SOC_IF_ERROR_RETURN 3297 (soc_reg_field32_modify(unit, PORT_SHARED_LIMITr, p, 3298 PORT_SHARED_LIMITf, 7150)); 3299 SOC_IF_ERROR_RETURN 3300 (soc_reg_fields32_modify(unit, PG_THRESH_SELr, p, 8, 3301 pg_thresh, xe_val)); 3302 SOC_IF_ERROR_RETURN 3303 (soc_reg_field32_modify(unit, PORT_RESET_OFFSETr, p, 3304 PORT_RESET_OFFSETf, 512)); 3305 SOC_IF_ERROR_RETURN 3306 (soc_reg_field32_modify(unit, PG_RESET_OFFSETr, p, 3307 PG_RESET_OFFSETf, 128)); 3308 for (idx = 0; idx < 8; idx++) { 3309 SOC_IF_ERROR_RETURN(READ_PG_MINr(unit, p, idx, &rval)); 3310 soc_reg_field_set(unit, PG_MINr, &rval, PG_MINf, 128); 3311 SOC_IF_ERROR_RETURN(WRITE_PG_MINr(unit, p, idx, rval)); 3312 } 3313 for (idx = 0; idx < 8; idx++) { 3314 SOC_IF_ERROR_RETURN(READ_PG_HDRM_LIMITr(unit, p, idx, &rval)); 3315 soc_reg_field_set(unit, PG_HDRM_LIMITr, &rval, PG_HDRM_LIMITf, 256); 3316 SOC_IF_ERROR_RETURN(WRITE_PG_HDRM_LIMITr(unit, p, idx, rval)); 3317 3318 } 3319 SOC_IF_ERROR_RETURN 3320 (soc_reg_field32_modify(unit, PORT_PRI_XON_ENABLEr, p, 3321 PORT_PRI_XON_ENABLEf, 0x3fff)); 3322 SOC_IF_ERROR_RETURN 3323 (soc_reg_field32_modify(unit, PORT_PRI_XON_ENABLEr, p, 3324 PORT_XON_ENABLEf, 1)); 3325 SOC_IF_ERROR_RETURN 3326 (soc_reg_field32_modify(unit, PORT_PRI_XON_ENABLEr, p, 3327 PORT_PG_PAUSE_DISABLEf, 0)); 3328 } 3329 PBMP_IL_ITER(unit, p) { 3330 uint32 il_val[8] = {2, 2, 2, 2, 2, 2, 2, 2}; 3331 SOC_IF_ERROR_RETURN 3332 (soc_reg_field32_modify(unit, PORT_MINr, p, PORT_MINf, 8)); 3333 SOC_IF_ERROR_RETURN 3334 (soc_reg_field32_modify(unit, PORT_MAX_PKT_SIZEr, p, 3335 PORT_MAX_PKT_SIZEf, 72)); 3336 SOC_IF_ERROR_RETURN 3337 (soc_reg_field32_modify(unit, PORT_SHARED_LIMITr, p, 3338 PORT_SHARED_LIMITf, 1112)); 3339 SOC_IF_ERROR_RETURN 3340 (soc_reg_fields32_modify(unit, PG_THRESH_SELr, p, 8, 3341 pg_thresh, il_val)); 3342 SOC_IF_ERROR_RETURN 3343 (soc_reg_field32_modify(unit, PORT_RESET_OFFSETr, p, 3344 PORT_RESET_OFFSETf, 256)); 3345 SOC_IF_ERROR_RETURN 3346 (soc_reg_field32_modify(unit, PG_RESET_OFFSETr, p, 3347 PG_RESET_OFFSETf, 36)); 3348 for (idx = 0; idx < 8; idx++) { 3349 SOC_IF_ERROR_RETURN(READ_PG_MINr(unit, p, idx, &rval)); 3350 soc_reg_field_set(unit, PG_MINr, &rval, PG_MINf, 8); 3351 SOC_IF_ERROR_RETURN(WRITE_PG_MINr(unit, p, idx, rval)); 3352 } 3353 for (idx = 0; idx < 8; idx++) { 3354 SOC_IF_ERROR_RETURN(READ_PG_HDRM_LIMITr(unit, p, idx, &rval)); 3355 soc_reg_field_set(unit, PG_HDRM_LIMITr, &rval, PG_HDRM_LIMITf, 108); 3356 SOC_IF_ERROR_RETURN(WRITE_PG_HDRM_LIMITr(unit, p, idx, rval)); 3357 3358 } 3359 SOC_IF_ERROR_RETURN 3360 (soc_reg_field32_modify(unit, PORT_PRI_XON_ENABLEr, p, 3361 PORT_PRI_XON_ENABLEf, 0x3fff)); 3362 SOC_IF_ERROR_RETURN 3363 (soc_reg_field32_modify(unit, PORT_PRI_XON_ENABLEr, p, 3364 PORT_XON_ENABLEf, 1)); 3365 } 3366 SOC_IF_ERROR_RETURN 3367 (soc_reg_field32_modify(unit, PORT_MINr, 0, PORT_MINf, 2)); 3368 SOC_IF_ERROR_RETURN 3369 (soc_reg_field32_modify(unit, PORT_SHARED_LIMITr, 0, 3370 PORT_SHARED_LIMITf, 126)); 3371 SOC_IF_ERROR_RETURN 3372 (soc_reg_field32_modify(unit, PORT_RESET_OFFSETr, 0, 3373 PORT_RESET_OFFSETf, 16)); 3374 PBMP_ALL_ITER(unit, p) { 3375 SOC_IF_ERROR_RETURN 3376 (soc_reg_fields32_modify(unit, PORT_PRI_GRP0r, p, 7, 3377 pri_grp0, pri_grp0_val)); 3378 SOC_IF_ERROR_RETURN 3379 (soc_reg_fields32_modify(unit, PORT_PRI_GRP1r, p, 7, 3380 pri_grp1, pri_grp1_val)); 3381 } 3382 3383 /* WRED */ 3384 SOC_IF_ERROR_RETURN 3385 (soc_reg_field32_modify(unit, TIME_DOMAIN_CONFIGr, REG_PORT_ANY, 3386 TIME_DOMAIN0f, 1)); 3387 PBMP_XE_ITER(unit, p) { 3388 for (idx = 0; idx < 8; idx++) { 3389 int j; 3390 SOC_IF_ERROR_RETURN(READ_WREDPARAM_START_CELLr(unit, p, idx, &rval)); 3391 soc_reg_field_set(unit, WREDPARAM_START_CELLr, &rval, 3392 DROPSTARTPOINTf, 715); 3393 SOC_IF_ERROR_RETURN(WRITE_WREDPARAM_START_CELLr(unit, p, idx, rval)); 3394 3395 SOC_IF_ERROR_RETURN(READ_WREDPARAM_END_CELLr(unit, p, idx, &rval)); 3396 soc_reg_field_set(unit, WREDPARAM_END_CELLr, &rval, 3397 DROPENDPOINTf, 1915); 3398 SOC_IF_ERROR_RETURN(WRITE_WREDPARAM_END_CELLr(unit, p, idx, rval)); 3399 SOC_IF_ERROR_RETURN(READ_WREDCONFIG_CELLr(unit, p, idx, &rval)); 3400 for (j = 0; j < 7; j++) { 3401 soc_reg_field_set(unit, WREDCONFIG_CELLr, &rval, 3402 wredcfg_cell[j], wredcfg_cell_val[j]); 3403 } 3404 SOC_IF_ERROR_RETURN(WRITE_WREDCONFIG_CELLr(unit, p, idx, rval)); 3405 3406 SOC_IF_ERROR_RETURN(READ_WREDPARAM_YELLOW_START_CELLr(unit, p, idx, &rval)); 3407 soc_reg_field_set(unit, WREDPARAM_YELLOW_START_CELLr, &rval, 3408 YELLOW_DROPSTARTPOINTf, 510); 3409 SOC_IF_ERROR_RETURN(WRITE_WREDPARAM_YELLOW_START_CELLr(unit, p, idx, rval)); 3410 3411 SOC_IF_ERROR_RETURN(READ_WREDPARAM_YELLOW_END_CELLr(unit, p, idx, &rval)); 3412 soc_reg_field_set(unit, WREDPARAM_YELLOW_END_CELLr, &rval, 3413 YELLOW_DROPENDPOINTf, 1532); 3414 SOC_IF_ERROR_RETURN(WRITE_WREDPARAM_YELLOW_END_CELLr(unit, p, idx, rval)); 3415 SOC_IF_ERROR_RETURN(READ_WREDPARAM_RED_START_CELLr(unit, p, idx, &rval)); 3416 soc_reg_field_set(unit, WREDPARAM_RED_START_CELLr, &rval, 3417 RED_DROPSTARTPOINTf, 306); 3418 SOC_IF_ERROR_RETURN(WRITE_WREDPARAM_RED_START_CELLr(unit, p, idx, rval)); 3419 SOC_IF_ERROR_RETURN(READ_WREDPARAM_RED_END_CELLr(unit, p, idx, &rval)); 3420 soc_reg_field_set(unit, WREDPARAM_RED_END_CELLr, &rval, 3421 RED_DROPENDPOINTf, 1149); 3422 SOC_IF_ERROR_RETURN(WRITE_WREDPARAM_RED_END_CELLr(unit, p, idx, rval)); 3423 SOC_IF_ERROR_RETURN(READ_WREDPARAM_PRI0_START_CELLr(unit, p, idx, &rval)); 3424 soc_reg_field_set(unit, WREDPARAM_PRI0_START_CELLr, &rval, 3425 PRI0_DROPSTARTPOINTf, 204); 3426 SOC_IF_ERROR_RETURN(WRITE_WREDPARAM_PRI0_START_CELLr(unit, p, idx, rval)); 3427 SOC_IF_ERROR_RETURN(READ_WREDPARAM_PRI0_END_CELLr(unit, p, idx, &rval)); 3428 soc_reg_field_set(unit, WREDPARAM_PRI0_END_CELLr, &rval, 3429 PRI0_DROPENDPOINTf, 957); 3430 SOC_IF_ERROR_RETURN(WRITE_WREDPARAM_PRI0_END_CELLr(unit, p, idx, rval)); 3431 } 3432 } 3433 3434 /* ES */ 3435 PBMP_XE_ITER(unit, p) { 3436 SOC_IF_ERROR_RETURN 3437 (soc_reg_field32_modify(unit, ESCONFIGr, p, SCHEDULING_SELECTf, 3)); 3438 for (idx = 0; idx < 8; idx++) { 3439 SOC_IF_ERROR_RETURN(READ_COSWEIGHTSr(unit, p, idx, &rval)); 3440 soc_reg_field_set(unit, COSWEIGHTSr, &rval, COSWEIGHTSf, cosw[idx]); 3441 SOC_IF_ERROR_RETURN(WRITE_COSWEIGHTSr(unit, p, idx, rval)); 3442 3443 } 3444 } 3445 PBMP_IL_ITER(unit, p) { 3446 SOC_IF_ERROR_RETURN 3447 (soc_reg_field32_modify(unit, ESCONFIGr, p, SCHEDULING_SELECTf, 3)); 3448 for (idx = 0; idx < 8; idx++) { 3449 SOC_IF_ERROR_RETURN(READ_COSWEIGHTSr(unit, p, idx, &rval)); 3450 soc_reg_field_set(unit, COSWEIGHTSr, &rval, COSWEIGHTSf, cosw[idx]); 3451 SOC_IF_ERROR_RETURN(WRITE_COSWEIGHTSr(unit, p, idx, rval)); 3452 } 3453 } 3454 SOC_IF_ERROR_RETURN 3455 (soc_reg_field32_modify(unit, INPUT_PORT_RX_ENABLEr, REG_PORT_ANY, 3456 INPUT_PORT_RX_ENABLEf, 0x1ffff)); 3457 SOC_IF_ERROR_RETURN 3458 (soc_reg_field32_modify(unit, OUTPUT_PORT_RX_ENABLEr, REG_PORT_ANY, 3459 OUTPUT_PORT_RX_ENABLEf, 0x1ffff)); 3460 SOC_IF_ERROR_RETURN 3461 (soc_reg_field32_modify(unit, PORTGRP_WDRR_CONFIGr, REG_PORT_ANY, 3462 PG_WDRR_MTU_QUANTA_SELECTf, 2)); 3463 PBMP_IL_ITER(unit, p) { 3464 SOC_IF_ERROR_RETURN 3465 (soc_reg_field32_modify(unit, ES_PORTGRP_WDRR_WEIGHTSr, p, 3466 PORTWEIGHTSf, 3)); 3467 } 3468 3469 /* MTRO */ 3470 PBMP_XE_ITER(unit, p) { 3471 SOC_IF_ERROR_RETURN 3472 (soc_reg_field32_modify(unit, EGRMETERINGCONFIGr, p, 3473 METER_GRANf, 3)); 3474 SOC_IF_ERROR_RETURN 3475 (soc_reg_field32_modify(unit, EGRMETERINGCONFIG1r, p, 3476 REFRESHf, 156250)); 3477 } 3478 3479 /* INTF */ 3480 SOC_IF_ERROR_RETURN 3481 (soc_reg_field32_modify(unit, MMU_LLFC_TX_CONFIG_3r, REG_PORT_ANY, 3482 BW_TIMER_VALUE_9_16f, 0)); 3483 SOC_IF_ERROR_RETURN 3484 (soc_reg_field32_modify(unit, MMU_LLFC_TX_CONFIG_4r, REG_PORT_ANY, 3485 XOFF_REFRESH_TIME_9_16f, 32)); 3486 SOC_IF_ERROR_RETURN 3487 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI15r, REG_PORT_ANY, 3488 COS0_7_BMPf, 128)); 3489 SOC_IF_ERROR_RETURN 3490 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI14r, REG_PORT_ANY, 3491 COS0_7_BMPf, 128)); 3492 SOC_IF_ERROR_RETURN 3493 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI13r, REG_PORT_ANY, 3494 COS0_7_BMPf, 128)); 3495 SOC_IF_ERROR_RETURN 3496 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI12r, REG_PORT_ANY, 3497 COS0_7_BMPf, 128)); 3498 SOC_IF_ERROR_RETURN 3499 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI11r, REG_PORT_ANY, 3500 COS0_7_BMPf, 128)); 3501 SOC_IF_ERROR_RETURN 3502 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI10r, REG_PORT_ANY, 3503 COS0_7_BMPf, 128)); 3504 SOC_IF_ERROR_RETURN 3505 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI9r, REG_PORT_ANY, 3506 COS0_7_BMPf, 128)); 3507 SOC_IF_ERROR_RETURN 3508 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI8r, REG_PORT_ANY, 3509 COS0_7_BMPf, 128)); 3510 SOC_IF_ERROR_RETURN 3511 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI7r, REG_PORT_ANY, 3512 COS0_7_BMPf, 128)); 3513 SOC_IF_ERROR_RETURN 3514 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI6r, REG_PORT_ANY, 3515 COS0_7_BMPf, 64)); 3516 SOC_IF_ERROR_RETURN 3517 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI5r, REG_PORT_ANY, 3518 COS0_7_BMPf, 32)); 3519 SOC_IF_ERROR_RETURN 3520 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI4r, REG_PORT_ANY, 3521 COS0_7_BMPf, 16)); 3522 SOC_IF_ERROR_RETURN 3523 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI3r, REG_PORT_ANY, 3524 COS0_7_BMPf, 8)); 3525 SOC_IF_ERROR_RETURN 3526 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI2r, REG_PORT_ANY, 3527 COS0_7_BMPf, 4)); 3528 SOC_IF_ERROR_RETURN 3529 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI1r, REG_PORT_ANY, 3530 COS0_7_BMPf, 2)); 3531 SOC_IF_ERROR_RETURN 3532 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI0r, REG_PORT_ANY, 3533 COS0_7_BMPf, 1)); 3534 3535 /* AGING */ 3536 SOC_IF_ERROR_RETURN 3537 (soc_reg_field32_modify(unit, PKTAGINGTIMERr, REG_PORT_ANY, 3538 DURATIONSELECTf, 4096)); 3539 SOC_IF_ERROR_RETURN 3540 (soc_reg_fields32_modify(unit, PKTAGINGLIMIT0r, REG_PORT_ANY, 8, 3541 aging0_fld, aging0_val)); 3542 SOC_IF_ERROR_RETURN 3543 (soc_reg_fields32_modify(unit, PKTAGINGLIMIT1r, REG_PORT_ANY, 8, 3544 aging1_fld, aging1_val)); 3545 3546 /* CTR */ 3547 rval = 0; 3548 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, CNGf, 7); 3549 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, COSf, 15); 3550 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, DST_PORTf, 31); 3551 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, SRC_PORTf, 31); 3552 SOC_IF_ERROR_RETURN(WRITE_TX_CNT_CONFIGr_REG32(unit, 7, rval)); 3553 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, ALL_DROP_ACCEPTf, 1); 3554 SOC_IF_ERROR_RETURN(WRITE_TX_CNT_CONFIGr_REG32(unit, 6, rval)); 3555 rval = 0; 3556 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, CNGf, 7); 3557 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, COSf, 15); 3558 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, DST_PORTf, 31); 3559 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, SRC_PORTf, 31); 3560 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, ENQ_DEQf, 1); 3561 SOC_IF_ERROR_RETURN(WRITE_TX_CNT_CONFIGr_REG32(unit, 5, rval)); 3562 rval = 0; 3563 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, COSf, 15); 3564 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, DST_PORTf, 31); 3565 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, SRC_PORTf, 31); 3566 SOC_IF_ERROR_RETURN(WRITE_TX_CNT_CONFIGr_REG32(unit, 4, rval)); 3567 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, CNGf, 1); 3568 SOC_IF_ERROR_RETURN(WRITE_TX_CNT_CONFIGr_REG32(unit, 3, rval)); 3569 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, CNGf, 2); 3570 SOC_IF_ERROR_RETURN(WRITE_TX_CNT_CONFIGr_REG32(unit, 2, rval)); 3571 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, CNGf, 3); 3572 SOC_IF_ERROR_RETURN(WRITE_TX_CNT_CONFIGr_REG32(unit, 1, rval)); 3573 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, CNGf, 7); 3574 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, ECN_MARKEDf, 1); 3575 SOC_IF_ERROR_RETURN(WRITE_TX_CNT_CONFIGr_REG32(unit, 0, rval)); 3576 rval = 0; 3577 SOC_IF_ERROR_RETURN(READ_OP_EP_PORT_MAPPING_TABLE_1r(unit, &rval)); 3578 soc_reg_field_set(unit, OP_EP_PORT_MAPPING_TABLE_1r, &rval, PORT10_MAPPINGf, 9); 3579 soc_reg_field_set(unit, OP_EP_PORT_MAPPING_TABLE_1r, &rval, PORT11_MAPPINGf, 9); 3580 soc_reg_field_set(unit, OP_EP_PORT_MAPPING_TABLE_1r, &rval, PORT12_MAPPINGf, 9); 3581 SOC_IF_ERROR_RETURN(WRITE_OP_EP_PORT_MAPPING_TABLE_1r(unit, rval)); 3582 rval = 0; 3583 SOC_IF_ERROR_RETURN(READ_OP_EP_PORT_MAPPING_TABLE_2r(unit, &rval)); 3584 soc_reg_field_set(unit, OP_EP_PORT_MAPPING_TABLE_2r, &rval, PORT14_MAPPINGf, 0xd); 3585 soc_reg_field_set(unit, OP_EP_PORT_MAPPING_TABLE_2r, &rval, PORT15_MAPPINGf, 0xd); 3586 soc_reg_field_set(unit, OP_EP_PORT_MAPPING_TABLE_2r, &rval, PORT16_MAPPINGf, 0xd); 3587 SOC_IF_ERROR_RETURN(WRITE_OP_EP_PORT_MAPPING_TABLE_2r(unit, rval)); 3588 3589 return SOC_E_NONE; 3590 } 3591 3592 3593 /* 3594 * MMU Configurations for TDM8 3595 * 8x10G to 40G(Interlaken) 3596 * Refered to SOC script : radian_init_88732_8X10G+1X40G_IL.soc 3597 */ 3598 3599 STATIC 3600 int _shadow_tdm8_mmu_init(int unit) 3601 { 3602 soc_port_t p; 3603 int idx; 3604 soc_field_t pg_thresh[8] = {PG0_THRESH_SELf, PG1_THRESH_SELf, 3605 PG2_THRESH_SELf, PG3_THRESH_SELf, 3606 PG4_THRESH_SELf, PG5_THRESH_SELf, 3607 PG6_THRESH_SELf, PG7_THRESH_SELf}; 3608 soc_field_t pri_grp0[7] = {PRI0_GRPf, PRI1_GRPf, PRI2_GRPf, PRI3_GRPf, 3609 PRI4_GRPf, PRI5_GRPf, PRI6_GRPf}; 3610 soc_field_t pri_grp1[7] = {PRI7_GRPf, PRI8_GRPf, PRI9_GRPf, PRI10_GRPf, 3611 PRI11_GRPf, PRI12_GRPf, PRI13_GRPf}; 3612 soc_field_t wredcfg_cell[7] = {MAXDROPRATEf, YELLOW_MAXDROPRATEf, 3613 RED_MAXDROPRATEf, PRI0_MAXDROPRATEf, 3614 WEIGHTf, CAP_AVERAGEf, ENABLEf}; 3615 soc_field_t aging0_fld[8] = {AGINGLIMITPRI7f, AGINGLIMITPRI6f, 3616 AGINGLIMITPRI5f, AGINGLIMITPRI4f, 3617 AGINGLIMITPRI3f, AGINGLIMITPRI2f, 3618 AGINGLIMITPRI1f, AGINGLIMITPRI0f}; 3619 soc_field_t aging1_fld[8] = {AGINGLIMITPRI15f, AGINGLIMITPRI14f, 3620 AGINGLIMITPRI13f, AGINGLIMITPRI12f, 3621 AGINGLIMITPRI11f, AGINGLIMITPRI10f, 3622 AGINGLIMITPRI9f, AGINGLIMITPRI8f}; 3623 uint32 es_arb_tdm_table[60] = 3624 {0x2, 0x1fe00, 0x20, 0x0, 0x0, 0x4, 3625 0x1fe00, 0x40, 0x0, 0x0, 0x8, 0x1fe00, 3626 0x80, 0x0, 0x1, 0x10, 0x1fe00, 0x100, 3627 0x0, 0x0, 0x2, 0x1fe00, 0x20, 0x0, 3628 0x0, 0x4, 0x1fe00, 0x40, 0x0, 0x0, 3629 0x8, 0x1fe00, 0x80, 0x0, 0x0, 0x10, 3630 0x1fe00, 0x100, 0x0, 0x0, 0x2, 0x1fe00, 3631 0x20, 0x0, 0x1, 0x4, 0x1fe00, 0x40, 3632 0x0, 0x0, 0x8, 0x1fe00, 0x80, 0x0, 3633 0x0, 0x10, 0x1fe00, 0x100, 0x0, 0x0}; 3634 3635 3636 uint32 pri_grp0_val[7] = {0, 1, 2, 3, 4, 5, 6}; 3637 uint32 pri_grp1_val[7] = {7, 7, 7, 7, 7, 7, 7}; 3638 uint32 wredcfg_cell_val[7] = {10, 10, 10, 10, 4, 1, 1}; 3639 uint32 cosw[8] = {1, 8, 16, 24, 32, 64, 127, 0}; 3640 uint32 aging0_val[8] = {1, 1, 5, 5, 5, 5, 5, 5}; 3641 uint32 aging1_val[8] = {1, 1, 1, 1, 1, 1, 1, 1}; 3642 3643 uint32 rval; 3644 3645 /* CFAP */ 3646 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, CFAPCONFIGr, REG_PORT_ANY, 3647 START_CFAP_INITf, 1)); 3648 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, CFAPFULLTHRESHOLD0r, 3649 REG_PORT_ANY, 3650 CFAPFULLSETPOINTf, 98160)); 3651 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, CFAPFULLTHRESHOLD1r, 3652 REG_PORT_ANY, 3653 CFAPFULLRESETPOINTf, 98016)); 3654 3655 /* THDO */ 3656 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, THDO_BYPASSr, REG_PORT_ANY, 3657 OUTPUT_THRESHOLD_BYPASSf, 0)); 3658 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, OP_BUFFER_SHARED_LIMITr, 3659 REG_PORT_ANY, 3660 OP_BUFFER_SHARED_LIMITf, 98304)); 3661 PBMP_ALL_ITER(unit, p) { 3662 SOC_IF_ERROR_RETURN 3663 (soc_reg_field32_modify(unit, OP_PORT_CONFIGUr, p, 3664 OP_SHARED_LIMITf, 98304)); 3665 for (idx = 0; idx < 10; idx++) { 3666 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_CONFIGUr(unit, p, idx, &rval)); 3667 soc_reg_field_set(unit, OP_QUEUE_CONFIGUr, &rval, Q_SHARED_LIMITf, 98304); 3668 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_CONFIGUr(unit, p, idx, rval)); 3669 } 3670 } 3671 3672 /* THDI */ 3673 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, TOTAL_SHARED_LIMITr, 3674 REG_PORT_ANY, 3675 TOTAL_SHARED_LIMITf, 66222)); 3676 PBMP_XE_ITER(unit, p) { 3677 uint32 xe_val[8] = {4, 4, 4, 4, 4, 4, 4, 4}; 3678 SOC_IF_ERROR_RETURN 3679 (soc_reg_field32_modify(unit, PORT_MINr, p, PORT_MINf, 8)); 3680 SOC_IF_ERROR_RETURN 3681 (soc_reg_field32_modify(unit, PORT_MAX_PKT_SIZEr, p, 3682 PORT_MAX_PKT_SIZEf, 72)); 3683 SOC_IF_ERROR_RETURN 3684 (soc_reg_field32_modify(unit, PORT_SHARED_LIMITr, p, 3685 PORT_SHARED_LIMITf, 7150)); 3686 SOC_IF_ERROR_RETURN 3687 (soc_reg_fields32_modify(unit, PG_THRESH_SELr, p, 8, 3688 pg_thresh, xe_val)); 3689 SOC_IF_ERROR_RETURN 3690 (soc_reg_field32_modify(unit, PORT_RESET_OFFSETr, p, 3691 PORT_RESET_OFFSETf, 512)); 3692 for (idx = 0; idx < 8; idx++) { 3693 SOC_IF_ERROR_RETURN(READ_PG_RESET_OFFSETr(unit, p, idx, &rval)); 3694 soc_reg_field_set(unit, PG_RESET_OFFSETr, &rval, PG_RESET_OFFSETf, 128); 3695 SOC_IF_ERROR_RETURN(WRITE_PG_RESET_OFFSETr(unit, p, idx, rval)); 3696 } 3697 for (idx = 0; idx < 8; idx++) { 3698 SOC_IF_ERROR_RETURN(READ_PG_MINr(unit, p, idx, &rval)); 3699 soc_reg_field_set(unit, PG_MINr, &rval, PG_MINf, 128); 3700 SOC_IF_ERROR_RETURN(WRITE_PG_MINr(unit, p, idx, rval)); 3701 } 3702 for (idx = 0; idx < 8; idx++) { 3703 SOC_IF_ERROR_RETURN(READ_PG_HDRM_LIMITr(unit, p, idx, &rval)); 3704 soc_reg_field_set(unit, PG_HDRM_LIMITr, &rval, PG_HDRM_LIMITf, 256); 3705 SOC_IF_ERROR_RETURN(WRITE_PG_HDRM_LIMITr(unit, p, idx, rval)); 3706 3707 } 3708 SOC_IF_ERROR_RETURN 3709 (soc_reg_field32_modify(unit, PORT_PRI_XON_ENABLEr, p, 3710 PORT_PRI_XON_ENABLEf, 0x3fff)); 3711 SOC_IF_ERROR_RETURN 3712 (soc_reg_field32_modify(unit, PORT_PRI_XON_ENABLEr, p, 3713 PORT_XON_ENABLEf, 1)); 3714 SOC_IF_ERROR_RETURN 3715 (soc_reg_field32_modify(unit, PORT_PRI_XON_ENABLEr, p, 3716 PORT_PG_PAUSE_DISABLEf, 0)); 3717 } 3718 PBMP_IL_ITER(unit, p) { 3719 uint32 il_val[8] = {2, 2, 2, 2, 2, 2, 2, 2}; 3720 SOC_IF_ERROR_RETURN 3721 (soc_reg_field32_modify(unit, PORT_MINr, p, PORT_MINf, 8)); 3722 SOC_IF_ERROR_RETURN 3723 (soc_reg_field32_modify(unit, PORT_MAX_PKT_SIZEr, p, 3724 PORT_MAX_PKT_SIZEf, 72)); 3725 SOC_IF_ERROR_RETURN 3726 (soc_reg_field32_modify(unit, PORT_SHARED_LIMITr, p, 3727 PORT_SHARED_LIMITf, 1112)); 3728 SOC_IF_ERROR_RETURN 3729 (soc_reg_fields32_modify(unit, PG_THRESH_SELr, p, 8, 3730 pg_thresh, il_val)); 3731 SOC_IF_ERROR_RETURN 3732 (soc_reg_field32_modify(unit, PORT_RESET_OFFSETr, p, 3733 PORT_RESET_OFFSETf, 256)); 3734 for (idx = 0; idx < 8; idx++) { 3735 SOC_IF_ERROR_RETURN(READ_PG_RESET_OFFSETr(unit, p, idx, &rval)); 3736 soc_reg_field_set(unit, PG_RESET_OFFSETr, &rval, PG_RESET_OFFSETf, 3737 36); 3738 SOC_IF_ERROR_RETURN(WRITE_PG_RESET_OFFSETr(unit, p, idx, rval)); 3739 } 3740 for (idx = 0; idx < 8; idx++) { 3741 SOC_IF_ERROR_RETURN(READ_PG_MINr(unit, p, idx, &rval)); 3742 soc_reg_field_set(unit, PG_MINr, &rval, PG_MINf, 8); 3743 SOC_IF_ERROR_RETURN(WRITE_PG_MINr(unit, p, idx, rval)); 3744 } 3745 for (idx = 0; idx < 8; idx++) { 3746 SOC_IF_ERROR_RETURN(READ_PG_HDRM_LIMITr(unit, p, idx, &rval)); 3747 soc_reg_field_set(unit, PG_HDRM_LIMITr, &rval, PG_HDRM_LIMITf, 108); 3748 SOC_IF_ERROR_RETURN(WRITE_PG_HDRM_LIMITr(unit, p, idx, rval)); 3749 3750 } 3751 SOC_IF_ERROR_RETURN 3752 (soc_reg_field32_modify(unit, PORT_PRI_XON_ENABLEr, p, 3753 PORT_PRI_XON_ENABLEf, 0x3fff)); 3754 SOC_IF_ERROR_RETURN 3755 (soc_reg_field32_modify(unit, PORT_PRI_XON_ENABLEr, p, 3756 PORT_XON_ENABLEf, 1)); 3757 } 3758 SOC_IF_ERROR_RETURN 3759 (soc_reg_field32_modify(unit, PORT_MINr, 0, PORT_MINf, 2)); 3760 SOC_IF_ERROR_RETURN 3761 (soc_reg_field32_modify(unit, PORT_SHARED_LIMITr, 0, 3762 PORT_SHARED_LIMITf, 126)); 3763 SOC_IF_ERROR_RETURN 3764 (soc_reg_field32_modify(unit, PORT_RESET_OFFSETr, 0, 3765 PORT_RESET_OFFSETf, 16)); 3766 PBMP_ALL_ITER(unit, p) { 3767 SOC_IF_ERROR_RETURN 3768 (soc_reg_fields32_modify(unit, PORT_PRI_GRP0r, p, 7, 3769 pri_grp0, pri_grp0_val)); 3770 SOC_IF_ERROR_RETURN 3771 (soc_reg_fields32_modify(unit, PORT_PRI_GRP1r, p, 7, 3772 pri_grp1, pri_grp1_val)); 3773 } 3774 SOC_IF_ERROR_RETURN 3775 (soc_reg_field32_modify(unit, TOTAL_SHARED_AVAIL_THRESHr, 0, 3776 TOTAL_SHARED_AVAIL_THRESHf, 65966)); 3777 3778 /* WRED */ 3779 SOC_IF_ERROR_RETURN 3780 (soc_reg_field32_modify(unit, TIME_DOMAIN_CONFIGr, REG_PORT_ANY, 3781 TIME_DOMAIN0f, 1)); 3782 PBMP_XE_ITER(unit, p) { 3783 for (idx = 0; idx < 8; idx++) { 3784 int j; 3785 SOC_IF_ERROR_RETURN(READ_WREDPARAM_START_CELLr(unit, p, idx, &rval)); 3786 soc_reg_field_set(unit, WREDPARAM_START_CELLr, &rval, 3787 DROPSTARTPOINTf, 715); 3788 SOC_IF_ERROR_RETURN(WRITE_WREDPARAM_START_CELLr(unit, p, idx, rval)); 3789 3790 SOC_IF_ERROR_RETURN(READ_WREDPARAM_END_CELLr(unit, p, idx, &rval)); 3791 soc_reg_field_set(unit, WREDPARAM_END_CELLr, &rval, 3792 DROPENDPOINTf, 1915); 3793 SOC_IF_ERROR_RETURN(WRITE_WREDPARAM_END_CELLr(unit, p, idx, rval)); 3794 3795 SOC_IF_ERROR_RETURN(READ_WREDCONFIG_CELLr(unit, p, idx, &rval)); 3796 for (j = 0; j < 7; j++) { 3797 soc_reg_field_set(unit, WREDCONFIG_CELLr, &rval, 3798 wredcfg_cell[j], wredcfg_cell_val[j]); 3799 } 3800 SOC_IF_ERROR_RETURN(WRITE_WREDCONFIG_CELLr(unit, p, idx, rval)); 3801 3802 SOC_IF_ERROR_RETURN(READ_WREDPARAM_YELLOW_START_CELLr(unit, p, idx, &rval)); 3803 soc_reg_field_set(unit, WREDPARAM_YELLOW_START_CELLr, &rval, 3804 YELLOW_DROPSTARTPOINTf, 510); 3805 SOC_IF_ERROR_RETURN(WRITE_WREDPARAM_YELLOW_START_CELLr(unit, p, idx, rval)); 3806 3807 SOC_IF_ERROR_RETURN(READ_WREDPARAM_YELLOW_END_CELLr(unit, p, idx, &rval)); 3808 soc_reg_field_set(unit, WREDPARAM_YELLOW_END_CELLr, &rval, 3809 YELLOW_DROPENDPOINTf, 1532); 3810 SOC_IF_ERROR_RETURN(WRITE_WREDPARAM_YELLOW_END_CELLr(unit, p, idx, rval)); 3811 SOC_IF_ERROR_RETURN(READ_WREDPARAM_RED_START_CELLr(unit, p, idx, &rval)); 3812 soc_reg_field_set(unit, WREDPARAM_RED_START_CELLr, &rval, 3813 RED_DROPSTARTPOINTf, 306); 3814 SOC_IF_ERROR_RETURN(WRITE_WREDPARAM_RED_START_CELLr(unit, p, idx, rval)); 3815 SOC_IF_ERROR_RETURN(READ_WREDPARAM_RED_END_CELLr(unit, p, idx, &rval)); 3816 soc_reg_field_set(unit, WREDPARAM_RED_END_CELLr, &rval, 3817 RED_DROPENDPOINTf, 1149); 3818 SOC_IF_ERROR_RETURN(WRITE_WREDPARAM_RED_END_CELLr(unit, p, idx, rval)); 3819 SOC_IF_ERROR_RETURN(READ_WREDPARAM_PRI0_START_CELLr(unit, p, idx, &rval)); 3820 soc_reg_field_set(unit, WREDPARAM_PRI0_START_CELLr, &rval, 3821 PRI0_DROPSTARTPOINTf, 204); 3822 SOC_IF_ERROR_RETURN(WRITE_WREDPARAM_PRI0_START_CELLr(unit, p, idx, rval)); 3823 SOC_IF_ERROR_RETURN(READ_WREDPARAM_PRI0_END_CELLr(unit, p, idx, &rval)); 3824 soc_reg_field_set(unit, WREDPARAM_PRI0_END_CELLr, &rval, 3825 PRI0_DROPENDPOINTf, 957); 3826 SOC_IF_ERROR_RETURN(WRITE_WREDPARAM_PRI0_END_CELLr(unit, p, idx, rval)); 3827 } 3828 } 3829 3830 /* ES */ 3831 PBMP_XE_ITER(unit, p) { 3832 SOC_IF_ERROR_RETURN 3833 (soc_reg_field32_modify(unit, ESCONFIGr, p, MTU_QUANTA_SELECTf, 2)); 3834 SOC_IF_ERROR_RETURN 3835 (soc_reg_field32_modify(unit, ESCONFIGr, p, SCHEDULING_SELECTf, 3)); 3836 for (idx = 0; idx < 8; idx++) { 3837 SOC_IF_ERROR_RETURN(READ_COSWEIGHTSr(unit, p, idx, &rval)); 3838 soc_reg_field_set(unit, COSWEIGHTSr, &rval, COSWEIGHTSf, cosw[idx]); 3839 SOC_IF_ERROR_RETURN(WRITE_COSWEIGHTSr(unit, p, idx, rval)); 3840 } 3841 } 3842 PBMP_IL_ITER(unit, p) { 3843 SOC_IF_ERROR_RETURN 3844 (soc_reg_field32_modify(unit, ESCONFIGr, p, MTU_QUANTA_SELECTf, 2)); 3845 SOC_IF_ERROR_RETURN 3846 (soc_reg_field32_modify(unit, ESCONFIGr, p, SCHEDULING_SELECTf, 3)); 3847 for (idx = 0; idx < 8; idx++) { 3848 SOC_IF_ERROR_RETURN(READ_COSWEIGHTSr(unit, p, idx, &rval)); 3849 soc_reg_field_set(unit, COSWEIGHTSr, &rval, COSWEIGHTSf, cosw[idx]); 3850 SOC_IF_ERROR_RETURN(WRITE_COSWEIGHTSr(unit, p, idx, rval)); 3851 } 3852 } 3853 SOC_IF_ERROR_RETURN 3854 (soc_reg_field32_modify(unit, INPUT_PORT_RX_ENABLEr, REG_PORT_ANY, 3855 INPUT_PORT_RX_ENABLEf, 0x1ffff)); 3856 SOC_IF_ERROR_RETURN 3857 (soc_reg_field32_modify(unit, OUTPUT_PORT_RX_ENABLEr, REG_PORT_ANY, 3858 OUTPUT_PORT_RX_ENABLEf, 0x1ffff)); 3859 SOC_IF_ERROR_RETURN 3860 (soc_reg_field32_modify(unit, PORTGRP_WDRR_CONFIGr, REG_PORT_ANY, 3861 PG_WDRR_MTU_QUANTA_SELECTf, 2)); 3862 for (idx = 0; idx < 30; idx++) { 3863 SOC_IF_ERROR_RETURN 3864 (soc_mem_field32_modify(unit, ES_ARB_TDM_TABLEm, idx, 3865 PORT_VECTORf, es_arb_tdm_table[idx])); 3866 SOC_IF_ERROR_RETURN 3867 (soc_mem_field32_modify(unit, ES_ARB_TDM_TABLEm, idx, 3868 SHAPER_ENf, 0)); 3869 SOC_IF_ERROR_RETURN 3870 (soc_mem_field32_modify(unit, ES_ARB_TDM_TABLEm, idx, 3871 SHAPER_IDf, 0)); 3872 } 3873 SOC_IF_ERROR_RETURN 3874 (soc_reg_field32_modify(unit, ES_TDM_CAL_CFGr, REG_PORT_ANY, 3875 CURRENT_CALENDARf, 0)); 3876 SOC_IF_ERROR_RETURN 3877 (soc_reg_field32_modify(unit, ES_TDM_CAL_CFGr, REG_PORT_ANY, 3878 END_Af, 59)); 3879 SOC_IF_ERROR_RETURN 3880 (soc_reg_field32_modify(unit, ES_TDM_CAL_CFGr, REG_PORT_ANY, 3881 END_Bf, 59)); 3882 SOC_IF_ERROR_RETURN 3883 (soc_reg_field32_modify(unit, ES_TDM_CAL_CFGr, REG_PORT_ANY, 3884 SWITCH_CALENDARf, 0)); 3885 SOC_IF_ERROR_RETURN 3886 (soc_reg_field32_modify(unit, ES_TDM_ENr, REG_PORT_ANY, 3887 ENf, 1)); 3888 PBMP_IL_ITER(unit, p) { 3889 SOC_IF_ERROR_RETURN 3890 (soc_reg_field32_modify(unit, ES_PORTGRP_WDRR_WEIGHTSr, p, 3891 PORTWEIGHTSf, 1)); 3892 } 3893 3894 /* MTRO */ 3895 PBMP_XE_ITER(unit, p) { 3896 SOC_IF_ERROR_RETURN 3897 (soc_reg_field32_modify(unit, EGRMETERINGCONFIGr, p, 3898 METER_GRANf, 3)); 3899 SOC_IF_ERROR_RETURN 3900 (soc_reg_field32_modify(unit, EGRMETERINGCONFIG1r, p, 3901 REFRESHf, 156250)); 3902 } 3903 3904 /* INTF */ 3905 SOC_IF_ERROR_RETURN 3906 (soc_reg_field32_modify(unit, MMU_LLFC_TX_CONFIG_3r, REG_PORT_ANY, 3907 BW_TIMER_VALUE_9_16f, 0)); 3908 SOC_IF_ERROR_RETURN 3909 (soc_reg_field32_modify(unit, MMU_LLFC_TX_CONFIG_4r, REG_PORT_ANY, 3910 XOFF_REFRESH_TIME_9_16f, 32)); 3911 SOC_IF_ERROR_RETURN 3912 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI15r, REG_PORT_ANY, 3913 COS0_7_BMPf, 128)); 3914 SOC_IF_ERROR_RETURN 3915 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI14r, REG_PORT_ANY, 3916 COS0_7_BMPf, 128)); 3917 SOC_IF_ERROR_RETURN 3918 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI13r, REG_PORT_ANY, 3919 COS0_7_BMPf, 128)); 3920 SOC_IF_ERROR_RETURN 3921 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI12r, REG_PORT_ANY, 3922 COS0_7_BMPf, 128)); 3923 SOC_IF_ERROR_RETURN 3924 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI11r, REG_PORT_ANY, 3925 COS0_7_BMPf, 128)); 3926 SOC_IF_ERROR_RETURN 3927 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI10r, REG_PORT_ANY, 3928 COS0_7_BMPf, 128)); 3929 SOC_IF_ERROR_RETURN 3930 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI9r, REG_PORT_ANY, 3931 COS0_7_BMPf, 128)); 3932 SOC_IF_ERROR_RETURN 3933 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI8r, REG_PORT_ANY, 3934 COS0_7_BMPf, 128)); 3935 SOC_IF_ERROR_RETURN 3936 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI7r, REG_PORT_ANY, 3937 COS0_7_BMPf, 128)); 3938 SOC_IF_ERROR_RETURN 3939 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI6r, REG_PORT_ANY, 3940 COS0_7_BMPf, 64)); 3941 SOC_IF_ERROR_RETURN 3942 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI5r, REG_PORT_ANY, 3943 COS0_7_BMPf, 32)); 3944 SOC_IF_ERROR_RETURN 3945 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI4r, REG_PORT_ANY, 3946 COS0_7_BMPf, 16)); 3947 SOC_IF_ERROR_RETURN 3948 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI3r, REG_PORT_ANY, 3949 COS0_7_BMPf, 8)); 3950 SOC_IF_ERROR_RETURN 3951 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI2r, REG_PORT_ANY, 3952 COS0_7_BMPf, 4)); 3953 SOC_IF_ERROR_RETURN 3954 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI1r, REG_PORT_ANY, 3955 COS0_7_BMPf, 2)); 3956 SOC_IF_ERROR_RETURN 3957 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI0r, REG_PORT_ANY, 3958 COS0_7_BMPf, 1)); 3959 3960 /* AGING */ 3961 SOC_IF_ERROR_RETURN 3962 (soc_reg_field32_modify(unit, PKTAGINGTIMERr, REG_PORT_ANY, 3963 DURATIONSELECTf, 4096)); 3964 SOC_IF_ERROR_RETURN 3965 (soc_reg_fields32_modify(unit, PKTAGINGLIMIT0r, REG_PORT_ANY, 8, 3966 aging0_fld, aging0_val)); 3967 SOC_IF_ERROR_RETURN 3968 (soc_reg_fields32_modify(unit, PKTAGINGLIMIT1r, REG_PORT_ANY, 8, 3969 aging1_fld, aging1_val)); 3970 3971 /* CTR */ 3972 rval = 0; 3973 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, CNGf, 7); 3974 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, COSf, 15); 3975 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, DST_PORTf, 31); 3976 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, SRC_PORTf, 31); 3977 SOC_IF_ERROR_RETURN(WRITE_TX_CNT_CONFIGr_REG32(unit, 7, rval)); 3978 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, ALL_DROP_ACCEPTf, 1); 3979 SOC_IF_ERROR_RETURN(WRITE_TX_CNT_CONFIGr_REG32(unit, 6, rval)); 3980 rval = 0; 3981 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, CNGf, 7); 3982 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, COSf, 15); 3983 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, DST_PORTf, 31); 3984 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, SRC_PORTf, 31); 3985 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, ENQ_DEQf, 1); 3986 SOC_IF_ERROR_RETURN(WRITE_TX_CNT_CONFIGr_REG32(unit, 5, rval)); 3987 rval = 0; 3988 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, COSf, 15); 3989 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, DST_PORTf, 31); 3990 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, SRC_PORTf, 31); 3991 SOC_IF_ERROR_RETURN(WRITE_TX_CNT_CONFIGr_REG32(unit, 4, rval)); 3992 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, CNGf, 1); 3993 SOC_IF_ERROR_RETURN(WRITE_TX_CNT_CONFIGr_REG32(unit, 3, rval)); 3994 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, CNGf, 2); 3995 SOC_IF_ERROR_RETURN(WRITE_TX_CNT_CONFIGr_REG32(unit, 2, rval)); 3996 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, CNGf, 3); 3997 SOC_IF_ERROR_RETURN(WRITE_TX_CNT_CONFIGr_REG32(unit, 1, rval)); 3998 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, CNGf, 7); 3999 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, ECN_MARKEDf, 1); 4000 SOC_IF_ERROR_RETURN(WRITE_TX_CNT_CONFIGr_REG32(unit, 0, rval)); 4001 rval = 0; 4002 SOC_IF_ERROR_RETURN(READ_OP_EP_PORT_MAPPING_TABLE_1r(unit, &rval)); 4003 soc_reg_field_set(unit, OP_EP_PORT_MAPPING_TABLE_1r, &rval, PORT10_MAPPINGf, 9); 4004 soc_reg_field_set(unit, OP_EP_PORT_MAPPING_TABLE_1r, &rval, PORT11_MAPPINGf, 9); 4005 soc_reg_field_set(unit, OP_EP_PORT_MAPPING_TABLE_1r, &rval, PORT12_MAPPINGf, 9); 4006 SOC_IF_ERROR_RETURN(WRITE_OP_EP_PORT_MAPPING_TABLE_1r(unit, rval)); 4007 rval = 0; 4008 SOC_IF_ERROR_RETURN(READ_OP_EP_PORT_MAPPING_TABLE_2r(unit, &rval)); 4009 soc_reg_field_set(unit, OP_EP_PORT_MAPPING_TABLE_2r, &rval, PORT13_MAPPINGf, 9); 4010 soc_reg_field_set(unit, OP_EP_PORT_MAPPING_TABLE_2r, &rval, PORT14_MAPPINGf, 9); 4011 soc_reg_field_set(unit, OP_EP_PORT_MAPPING_TABLE_2r, &rval, PORT15_MAPPINGf, 9); 4012 soc_reg_field_set(unit, OP_EP_PORT_MAPPING_TABLE_2r, &rval, PORT16_MAPPINGf, 9); 4013 SOC_IF_ERROR_RETURN(WRITE_OP_EP_PORT_MAPPING_TABLE_2r(unit, rval)); 4014 4015 return SOC_E_NONE; 4016 } 4017 4018 /* 4019 * MMU Config for TDM18 4020 * 1X40G to 4X10G 4021 */ 4022 STATIC 4023 int _shadow_tdm18_mmu_init(int unit) 4024 { 4025 soc_port_t p; 4026 int idx; 4027 soc_field_t pg_thresh[8] = {PG0_THRESH_SELf, PG1_THRESH_SELf, 4028 PG2_THRESH_SELf, PG3_THRESH_SELf, 4029 PG4_THRESH_SELf, PG5_THRESH_SELf, 4030 PG6_THRESH_SELf, PG7_THRESH_SELf}; 4031 soc_field_t pri_grp0[7] = {PRI0_GRPf, PRI1_GRPf, PRI2_GRPf, PRI3_GRPf, 4032 PRI4_GRPf, PRI5_GRPf, PRI6_GRPf}; 4033 soc_field_t pri_grp1[7] = {PRI7_GRPf, PRI8_GRPf, PRI9_GRPf, PRI10_GRPf, 4034 PRI11_GRPf, PRI12_GRPf, PRI13_GRPf}; 4035 soc_field_t aging0_fld[8] = {AGINGLIMITPRI7f, AGINGLIMITPRI6f, 4036 AGINGLIMITPRI5f, AGINGLIMITPRI4f, 4037 AGINGLIMITPRI3f, AGINGLIMITPRI2f, 4038 AGINGLIMITPRI1f, AGINGLIMITPRI0f}; 4039 soc_field_t aging1_fld[8] = {AGINGLIMITPRI15f, AGINGLIMITPRI14f, 4040 AGINGLIMITPRI13f, AGINGLIMITPRI12f, 4041 AGINGLIMITPRI11f, AGINGLIMITPRI10f, 4042 AGINGLIMITPRI9f, AGINGLIMITPRI8f}; 4043 uint32 es_arb_tdm_table[30] = 4044 {0x2, 0x200, 0x20, 0x2000, 0x400, 0x2, 4045 0x4000, 0x20, 0x800, 0x8000, 0x2, 0x1000, 4046 0x20, 0x10000, 0x1, 0x2, 0x200, 0x20, 4047 0x2000, 0x400, 0x2, 0x4000, 0x20, 0x800, 4048 0x8000, 0x2, 0x1000, 0x20, 0x10000, 0x0}; 4049 uint32 pri_grp0_val[7] = {0, 1, 2, 3, 4, 5, 6}; 4050 uint32 pri_grp1_val[7] = {7, 7, 7, 7, 7, 7, 7}; 4051 uint32 aging0_val[8] = {1, 1, 5, 5, 5, 5, 5, 5}; 4052 uint32 aging1_val[8] = {1, 1, 1, 1, 1, 1, 1, 1}; 4053 4054 uint32 rval; 4055 4056 4057 /* CFAP */ 4058 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, CFAPCONFIGr, REG_PORT_ANY, 4059 START_CFAP_INITf, 1)); 4060 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, CFAPCONFIGr, REG_PORT_ANY, 4061 CFAPPOOLSIZEf, 98304)); 4062 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, CFAPFULLTHRESHOLD0r, 4063 REG_PORT_ANY, 4064 CFAPFULLSETPOINTf, 98160)); 4065 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, CFAPFULLTHRESHOLD1r, 4066 REG_PORT_ANY, 4067 CFAPFULLRESETPOINTf, 98016)); 4068 4069 /* THDO */ 4070 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, OP_BUFFER_SHARED_LIMITr, 4071 REG_PORT_ANY, 4072 OP_BUFFER_SHARED_LIMITf, 32768)); 4073 PBMP_ALL_ITER(unit, p) { 4074 SOC_IF_ERROR_RETURN 4075 (soc_reg_field32_modify(unit, OP_PORT_CONFIGUr, p, 4076 OP_SHARED_LIMITf, 32768)); 4077 for (idx = 0; idx <= 9; idx++) { 4078 SOC_IF_ERROR_RETURN 4079 (READ_OP_QUEUE_CONFIGUr(unit, p, idx, &rval)); 4080 soc_reg_field_set(unit, OP_QUEUE_CONFIGUr, &rval, Q_SHARED_LIMITf, 4081 32768); 4082 SOC_IF_ERROR_RETURN 4083 (WRITE_OP_QUEUE_CONFIGUr(unit, p, idx, rval)); 4084 } 4085 } 4086 4087 /* THDI */ 4088 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, TOTAL_SHARED_LIMITr, 4089 REG_PORT_ANY, 4090 TOTAL_SHARED_LIMITf, 61278)); 4091 4092 PBMP_ALL_ITER(unit, p) { 4093 uint32 xe_val[8] = {15, 15, 15, 15, 15, 15, 15, 15}; 4094 SOC_IF_ERROR_RETURN 4095 (soc_reg_field32_modify(unit, PORT_MAX_PKT_SIZEr, p, 4096 PORT_MAX_PKT_SIZEf, 75)); 4097 SOC_IF_ERROR_RETURN 4098 (soc_reg_fields32_modify(unit, PG_THRESH_SELr, p, 8, 4099 pg_thresh, xe_val)); 4100 SOC_IF_ERROR_RETURN 4101 (soc_reg_field32_modify(unit, PG_HDRM_LIMITr, p, 4102 PG_HDRM_LIMITf, 0)); 4103 SOC_IF_ERROR_RETURN 4104 (soc_reg_field32_modify(unit, PORT_PRI_XON_ENABLEr, p, 4105 PORT_XON_ENABLEf, 1)); 4106 SOC_IF_ERROR_RETURN 4107 (soc_reg_field32_modify(unit, PORT_PRI_XON_ENABLEr, p, 4108 PORT_PG_PAUSE_DISABLEf, 0)); 4109 } 4110 SOC_IF_ERROR_RETURN 4111 (soc_reg_field32_modify(unit, PORT_MINr, 1, PORT_MINf, 8)); 4112 SOC_IF_ERROR_RETURN 4113 (soc_reg_field32_modify(unit, PORT_MINr, 0, PORT_MINf, 2)); 4114 4115 for (p = 9; p < 16; p+=2) { 4116 SOC_IF_ERROR_RETURN 4117 (soc_reg_field32_modify(unit, PG_HDRM_LIMITr, p, 4118 PG_HDRM_LIMITf, 216)); 4119 SOC_IF_ERROR_RETURN 4120 (soc_reg_field32_modify(unit, PORT_SHARED_LIMITr, p, 4121 PORT_SHARED_LIMITf, 8192)); 4122 } 4123 SOC_IF_ERROR_RETURN 4124 (soc_reg_field32_modify(unit, PORT_SHARED_LIMITr, 0, 4125 PORT_SHARED_LIMITf, 126)); 4126 SOC_IF_ERROR_RETURN 4127 (soc_reg_field32_modify(unit, PORT_RESET_OFFSETr, 0, 4128 PORT_RESET_OFFSETf, 16)); 4129 SOC_IF_ERROR_RETURN 4130 (soc_reg_field32_modify(unit, PORT_MAX_PKT_SIZEr, 0, 4131 PORT_MAX_PKT_SIZEf, 75)); 4132 SOC_IF_ERROR_RETURN 4133 (soc_reg_field32_modify(unit, PORT_PRI_XON_ENABLEr, 0, 4134 PORT_XON_ENABLEf, 1)); 4135 4136 SOC_IF_ERROR_RETURN 4137 (soc_reg_field32_modify(unit, PORT_RESET_OFFSETr, 1, 4138 PORT_RESET_OFFSETf, 384)); 4139 SOC_IF_ERROR_RETURN 4140 (soc_reg_field32_modify(unit, PORT_RESET_OFFSETr, 5, 4141 PORT_RESET_OFFSETf, 0)); 4142 for (idx = 0; idx < 8; idx++) { 4143 SOC_IF_ERROR_RETURN(READ_PG_HDRM_LIMITr(unit, 1, idx, &rval)); 4144 soc_reg_field_set(unit, PG_HDRM_LIMITr, &rval, PG_HDRM_LIMITf, 1024); 4145 SOC_IF_ERROR_RETURN(WRITE_PG_HDRM_LIMITr(unit, 1, idx, rval)); 4146 } 4147 4148 PBMP_ALL_ITER(unit, p) { 4149 SOC_IF_ERROR_RETURN 4150 (soc_reg_fields32_modify(unit, PORT_PRI_GRP0r, p, 7, 4151 pri_grp0, pri_grp0_val)); 4152 SOC_IF_ERROR_RETURN 4153 (soc_reg_fields32_modify(unit, PORT_PRI_GRP1r, p, 7, 4154 pri_grp1, pri_grp1_val)); 4155 } 4156 SOC_IF_ERROR_RETURN 4157 (soc_reg_field32_modify(unit, TOTAL_SHARED_AVAIL_THRESHr, 4158 REG_PORT_ANY, TOTAL_SHARED_AVAIL_THRESHf, 4159 61022)); 4160 SOC_IF_ERROR_RETURN 4161 (soc_reg_field32_modify(unit, PG0_HDRM_LIMIT_OFFSETr, 4162 REG_PORT_ANY, PG0_HDRM_LIMIT_OFFSETf, 128)); 4163 SOC_IF_ERROR_RETURN 4164 (soc_reg_field32_modify(unit, PG1_HDRM_LIMIT_OFFSETr, 4165 REG_PORT_ANY, PG1_HDRM_LIMIT_OFFSETf, 128)); 4166 SOC_IF_ERROR_RETURN 4167 (soc_reg_field32_modify(unit, PG2_HDRM_LIMIT_OFFSETr, 4168 REG_PORT_ANY, PG2_HDRM_LIMIT_OFFSETf, 128)); 4169 SOC_IF_ERROR_RETURN 4170 (soc_reg_field32_modify(unit, PG3_HDRM_LIMIT_OFFSETr, 4171 REG_PORT_ANY, PG3_HDRM_LIMIT_OFFSETf, 128)); 4172 SOC_IF_ERROR_RETURN 4173 (soc_reg_field32_modify(unit, PG4_HDRM_LIMIT_OFFSETr, 4174 REG_PORT_ANY, PG4_HDRM_LIMIT_OFFSETf, 128)); 4175 SOC_IF_ERROR_RETURN 4176 (soc_reg_field32_modify(unit, PG5_HDRM_LIMIT_OFFSETr, 4177 REG_PORT_ANY, PG5_HDRM_LIMIT_OFFSETf, 128)); 4178 SOC_IF_ERROR_RETURN 4179 (soc_reg_field32_modify(unit, PG6_HDRM_LIMIT_OFFSETr, 4180 REG_PORT_ANY, PG6_HDRM_LIMIT_OFFSETf, 128)); 4181 SOC_IF_ERROR_RETURN 4182 (soc_reg_field32_modify(unit, PG7_HDRM_LIMIT_OFFSETr, 4183 REG_PORT_ANY, PG7_HDRM_LIMIT_OFFSETf, 128)); 4184 4185 SOC_IF_ERROR_RETURN(WRITE_PORT_HDRM_ENABLEr(unit, 0)); 4186 4187 4188 /* WRED */ 4189 SOC_IF_ERROR_RETURN 4190 (soc_reg_field32_modify(unit, TIME_DOMAIN_CONFIGr, REG_PORT_ANY, 4191 LB_TIME_DOMAINf, 1)); 4192 SOC_IF_ERROR_RETURN 4193 (soc_reg_field32_modify(unit, TIME_DOMAIN_CONFIGr, REG_PORT_ANY, 4194 TIME_DOMAIN1f, 1)); 4195 PBMP_XE_ITER(unit, p) { 4196 SOC_IF_ERROR_RETURN 4197 (soc_reg_field32_modify(unit, PORT_WREDCONFIG_CELLr, p, 4198 LB_WEIGHTf, 4)); 4199 SOC_IF_ERROR_RETURN 4200 (soc_reg_field32_modify(unit, PORT_WREDCONFIG_CELLr, p, 4201 LB_ENABLEf, 1)); 4202 } 4203 4204 /* ES */ 4205 PBMP_ALL_ITER(unit, p) { 4206 SOC_IF_ERROR_RETURN 4207 (soc_reg_field32_modify(unit, ESCONFIGr, p, MTU_QUANTA_SELECTf, 2)); 4208 } 4209 SOC_IF_ERROR_RETURN 4210 (soc_reg_field32_modify(unit, INPUT_PORT_RX_ENABLEr, REG_PORT_ANY, 4211 INPUT_PORT_RX_ENABLEf, 43522)); 4212 SOC_IF_ERROR_RETURN 4213 (soc_reg_field32_modify(unit, OUTPUT_PORT_RX_ENABLEr, REG_PORT_ANY, 4214 OUTPUT_PORT_RX_ENABLEf, 43522)); 4215 SOC_IF_ERROR_RETURN 4216 (soc_reg_field32_modify(unit, PORTGRP_WDRR_CONFIGr, REG_PORT_ANY, 4217 PG_WDRR_MTU_QUANTA_SELECTf, 2)); 4218 for (idx = 0; idx < 30; idx++) { 4219 SOC_IF_ERROR_RETURN 4220 (soc_mem_field32_modify(unit, ES_ARB_TDM_TABLEm, idx, 4221 PORT_VECTORf, es_arb_tdm_table[idx])); 4222 SOC_IF_ERROR_RETURN 4223 (soc_mem_field32_modify(unit, ES_ARB_TDM_TABLEm, idx, 4224 SHAPER_ENf, 0)); 4225 SOC_IF_ERROR_RETURN 4226 (soc_mem_field32_modify(unit, ES_ARB_TDM_TABLEm, idx, 4227 SHAPER_IDf, 0)); 4228 } 4229 SOC_IF_ERROR_RETURN 4230 (soc_reg_field32_modify(unit, ES_TDM_CAL_CFGr, REG_PORT_ANY, 4231 END_Af, 29)); 4232 SOC_IF_ERROR_RETURN 4233 (soc_reg_field32_modify(unit, ES_TDM_CAL_CFGr, REG_PORT_ANY, 4234 END_Bf, 29)); 4235 SOC_IF_ERROR_RETURN 4236 (soc_reg_field32_modify(unit, ES_TDM_ENr, REG_PORT_ANY, 4237 ENf, 1)); 4238 4239 /* MTRO */ 4240 PBMP_XE_ITER(unit, p) { 4241 SOC_IF_ERROR_RETURN 4242 (soc_reg_field32_modify(unit, EGRMETERINGCONFIGr, p, 4243 METER_GRANf, 3)); 4244 SOC_IF_ERROR_RETURN 4245 (soc_reg_field32_modify(unit, EGRMETERINGCONFIGr, p, 4246 THRESHOLDf, 544)); 4247 SOC_IF_ERROR_RETURN 4248 (soc_reg_field32_modify(unit, EGRMETERINGCONFIG1r, p, 4249 REFRESHf, 156250)); 4250 } 4251 4252 /* INTF */ 4253 SOC_IF_ERROR_RETURN 4254 (soc_reg_field32_modify(unit, MMU_LLFC_TX_CONFIG_3r, REG_PORT_ANY, 4255 BW_TIMER_VALUE_9_16f, 0)); 4256 SOC_IF_ERROR_RETURN 4257 (soc_reg_field32_modify(unit, MMU_LLFC_TX_CONFIG_4r, REG_PORT_ANY, 4258 XOFF_REFRESH_TIME_9_16f, 32)); 4259 SOC_IF_ERROR_RETURN 4260 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI15r, REG_PORT_ANY, 4261 COS0_7_BMPf, 128)); 4262 SOC_IF_ERROR_RETURN 4263 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI14r, REG_PORT_ANY, 4264 COS0_7_BMPf, 128)); 4265 SOC_IF_ERROR_RETURN 4266 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI13r, REG_PORT_ANY, 4267 COS0_7_BMPf, 128)); 4268 SOC_IF_ERROR_RETURN 4269 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI12r, REG_PORT_ANY, 4270 COS0_7_BMPf, 128)); 4271 SOC_IF_ERROR_RETURN 4272 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI11r, REG_PORT_ANY, 4273 COS0_7_BMPf, 128)); 4274 SOC_IF_ERROR_RETURN 4275 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI10r, REG_PORT_ANY, 4276 COS0_7_BMPf, 128)); 4277 SOC_IF_ERROR_RETURN 4278 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI9r, REG_PORT_ANY, 4279 COS0_7_BMPf, 128)); 4280 SOC_IF_ERROR_RETURN 4281 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI8r, REG_PORT_ANY, 4282 COS0_7_BMPf, 128)); 4283 SOC_IF_ERROR_RETURN 4284 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI7r, REG_PORT_ANY, 4285 COS0_7_BMPf, 128)); 4286 SOC_IF_ERROR_RETURN 4287 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI6r, REG_PORT_ANY, 4288 COS0_7_BMPf, 64)); 4289 SOC_IF_ERROR_RETURN 4290 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI5r, REG_PORT_ANY, 4291 COS0_7_BMPf, 32)); 4292 SOC_IF_ERROR_RETURN 4293 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI4r, REG_PORT_ANY, 4294 COS0_7_BMPf, 16)); 4295 SOC_IF_ERROR_RETURN 4296 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI3r, REG_PORT_ANY, 4297 COS0_7_BMPf, 8)); 4298 SOC_IF_ERROR_RETURN 4299 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI2r, REG_PORT_ANY, 4300 COS0_7_BMPf, 4)); 4301 SOC_IF_ERROR_RETURN 4302 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI1r, REG_PORT_ANY, 4303 COS0_7_BMPf, 2)); 4304 SOC_IF_ERROR_RETURN 4305 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI0r, REG_PORT_ANY, 4306 COS0_7_BMPf, 1)); 4307 4308 /* AGING */ 4309 SOC_IF_ERROR_RETURN 4310 (soc_reg_field32_modify(unit, PKTAGINGTIMERr, REG_PORT_ANY, 4311 DURATIONSELECTf, 4096)); 4312 SOC_IF_ERROR_RETURN 4313 (soc_reg_fields32_modify(unit, PKTAGINGLIMIT0r, REG_PORT_ANY, 8, 4314 aging0_fld, aging0_val)); 4315 SOC_IF_ERROR_RETURN 4316 (soc_reg_fields32_modify(unit, PKTAGINGLIMIT1r, REG_PORT_ANY, 8, 4317 aging1_fld, aging1_val)); 4318 4319 /* CTR */ 4320 rval = 0; 4321 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, CNGf, 7); 4322 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, COSf, 15); 4323 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, DST_PORTf, 31); 4324 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, SRC_PORTf, 31); 4325 SOC_IF_ERROR_RETURN(WRITE_TX_CNT_CONFIGr_REG32(unit, 7, rval)); 4326 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, ALL_DROP_ACCEPTf, 1); 4327 SOC_IF_ERROR_RETURN(WRITE_TX_CNT_CONFIGr_REG32(unit, 6, rval)); 4328 rval = 0; 4329 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, CNGf, 7); 4330 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, COSf, 15); 4331 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, DST_PORTf, 31); 4332 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, SRC_PORTf, 31); 4333 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, ENQ_DEQf, 1); 4334 SOC_IF_ERROR_RETURN(WRITE_TX_CNT_CONFIGr_REG32(unit, 5, rval)); 4335 rval = 0; 4336 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, COSf, 15); 4337 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, DST_PORTf, 31); 4338 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, SRC_PORTf, 31); 4339 SOC_IF_ERROR_RETURN(WRITE_TX_CNT_CONFIGr_REG32(unit, 4, rval)); 4340 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, CNGf, 1); 4341 SOC_IF_ERROR_RETURN(WRITE_TX_CNT_CONFIGr_REG32(unit, 3, rval)); 4342 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, CNGf, 2); 4343 SOC_IF_ERROR_RETURN(WRITE_TX_CNT_CONFIGr_REG32(unit, 2, rval)); 4344 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, CNGf, 3); 4345 SOC_IF_ERROR_RETURN(WRITE_TX_CNT_CONFIGr_REG32(unit, 1, rval)); 4346 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, CNGf, 7); 4347 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, ECN_MARKEDf, 1); 4348 SOC_IF_ERROR_RETURN(WRITE_TX_CNT_CONFIGr_REG32(unit, 0, rval)); 4349 4350 return SOC_E_NONE; 4351 } 4352 4353 /* 4354 * MMU Config for TDM19 4355 * 4x10G to 4X10G 4356 */ 4357 STATIC 4358 int _shadow_tdm19_mmu_init(int unit) 4359 { 4360 soc_port_t p; 4361 int idx; 4362 soc_field_t pg_thresh[8] = {PG0_THRESH_SELf, PG1_THRESH_SELf, 4363 PG2_THRESH_SELf, PG3_THRESH_SELf, 4364 PG4_THRESH_SELf, PG5_THRESH_SELf, 4365 PG6_THRESH_SELf, PG7_THRESH_SELf}; 4366 soc_field_t pri_grp0[7] = {PRI0_GRPf, PRI1_GRPf, PRI2_GRPf, PRI3_GRPf, 4367 PRI4_GRPf, PRI5_GRPf, PRI6_GRPf}; 4368 soc_field_t pri_grp1[7] = {PRI7_GRPf, PRI8_GRPf, PRI9_GRPf, PRI10_GRPf, 4369 PRI11_GRPf, PRI12_GRPf, PRI13_GRPf}; 4370 soc_field_t aging0_fld[8] = {AGINGLIMITPRI7f, AGINGLIMITPRI6f, 4371 AGINGLIMITPRI5f, AGINGLIMITPRI4f, 4372 AGINGLIMITPRI3f, AGINGLIMITPRI2f, 4373 AGINGLIMITPRI1f, AGINGLIMITPRI0f}; 4374 soc_field_t aging1_fld[8] = {AGINGLIMITPRI15f, AGINGLIMITPRI14f, 4375 AGINGLIMITPRI13f, AGINGLIMITPRI12f, 4376 AGINGLIMITPRI11f, AGINGLIMITPRI10f, 4377 AGINGLIMITPRI9f, AGINGLIMITPRI8f}; 4378 uint32 es_arb_tdm_table[60] = 4379 {0x2, 0x600, 0x20, 0, 0x6000, 0x4, 4380 0, 0x40, 0x1800, 0, 0x8, 0x18000, 4381 0x80, 0, 1, 0x10, 0x600, 0x100, 4382 0, 0x6000, 2, 0, 0x20, 0x1800, 4383 0, 0x4, 0x18000, 0x40, 0, 0x0, 4384 0x8, 0x600, 0x80, 0, 0x6000, 0x10, 4385 0, 0x100, 0x1800, 0, 0x2, 0x18000, 4386 0x20, 0, 0x1, 0x4, 0x600, 0x40, 4387 0, 0x6000, 0x8, 0, 0x80, 0x1800, 4388 0, 0x10, 0x18000, 0x100, 0, 0x0}; 4389 4390 uint32 pri_grp0_val[7] = {0, 1, 2, 3, 4, 5, 6}; 4391 uint32 pri_grp1_val[7] = {7, 7, 7, 7, 7, 7, 7}; 4392 uint32 aging0_val[8] = {1, 1, 5, 5, 5, 5, 5, 5}; 4393 uint32 aging1_val[8] = {1, 1, 1, 1, 1, 1, 1, 1}; 4394 4395 uint32 rval; 4396 4397 4398 /* CFAP */ 4399 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, CFAPCONFIGr, REG_PORT_ANY, 4400 START_CFAP_INITf, 1)); 4401 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, CFAPCONFIGr, REG_PORT_ANY, 4402 CFAPPOOLSIZEf, 98304)); 4403 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, CFAPFULLTHRESHOLD0r, 4404 REG_PORT_ANY, 4405 CFAPFULLSETPOINTf, 98160)); 4406 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, CFAPFULLTHRESHOLD1r, 4407 REG_PORT_ANY, 4408 CFAPFULLRESETPOINTf, 98016)); 4409 4410 /* THDO */ 4411 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, THDO_BYPASSr, REG_PORT_ANY, 4412 OUTPUT_THRESHOLD_BYPASSf, 1)); 4413 /* THDI */ 4414 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, TOTAL_SHARED_LIMITr, 4415 REG_PORT_ANY, 4416 TOTAL_SHARED_LIMITf, 61278)); 4417 for (p = 1; p <= 4; p++) { 4418 SOC_IF_ERROR_RETURN 4419 (soc_reg_field32_modify(unit, PORT_SHARED_LIMITr, p, 4420 PORT_SHARED_LIMITf, 8192)); 4421 for (idx = 0; idx < 8; idx++) { 4422 SOC_IF_ERROR_RETURN(READ_PG_HDRM_LIMITr(unit, p, idx, &rval)); 4423 soc_reg_field_set(unit, PG_HDRM_LIMITr, &rval, PG_HDRM_LIMITf, 4424 1024); 4425 SOC_IF_ERROR_RETURN(WRITE_PG_HDRM_LIMITr(unit, p, idx, rval)); 4426 } 4427 } 4428 for (p = 1; p <= 8; p++) { 4429 SOC_IF_ERROR_RETURN 4430 (soc_reg_field32_modify(unit, PORT_RESET_OFFSETr, p, 4431 PORT_RESET_OFFSETf, 128)); 4432 } 4433 for (p = 9; p <= 16; p++) { 4434 SOC_IF_ERROR_RETURN 4435 (soc_reg_field32_modify(unit, PORT_SHARED_LIMITr, p, 4436 PORT_SHARED_LIMITf, 2048)); 4437 SOC_IF_ERROR_RETURN 4438 (soc_reg_field32_modify(unit, PORT_RESET_OFFSETr, p, 4439 PORT_RESET_OFFSETf, 72)); 4440 } 4441 for (p = 9; p < 16; p+=2) { 4442 for (idx = 0; idx < 8; idx++) { 4443 SOC_IF_ERROR_RETURN(READ_PG_HDRM_LIMITr(unit, p, idx, &rval)); 4444 soc_reg_field_set(unit, PG_HDRM_LIMITr, &rval, PG_HDRM_LIMITf, 4445 384); 4446 SOC_IF_ERROR_RETURN(WRITE_PG_HDRM_LIMITr(unit, p, idx, rval)); 4447 } 4448 } 4449 PBMP_ALL_ITER(unit, p) { 4450 uint32 xe_val[8] = {15, 15, 15, 15, 15, 15, 15, 15}; 4451 SOC_IF_ERROR_RETURN 4452 (soc_reg_field32_modify(unit, PORT_MINr, p, PORT_MINf, 32)); 4453 SOC_IF_ERROR_RETURN 4454 (soc_reg_field32_modify(unit, PORT_MAX_PKT_SIZEr, p, 4455 PORT_MAX_PKT_SIZEf, 75)); 4456 SOC_IF_ERROR_RETURN 4457 (soc_reg_fields32_modify(unit, PG_THRESH_SELr, p, 8, 4458 pg_thresh, xe_val)); 4459 SOC_IF_ERROR_RETURN 4460 (soc_reg_field32_modify(unit, PORT_PRI_XON_ENABLEr, p, 4461 PORT_XON_ENABLEf, 1)); 4462 SOC_IF_ERROR_RETURN 4463 (soc_reg_field32_modify(unit, PORT_PRI_XON_ENABLEr, p, 4464 PORT_PG_PAUSE_DISABLEf, 0)); 4465 } 4466 SOC_IF_ERROR_RETURN 4467 (soc_reg_field32_modify(unit, PORT_MINr, 0, PORT_MINf, 2)); 4468 SOC_IF_ERROR_RETURN 4469 (soc_reg_field32_modify(unit, PORT_SHARED_LIMITr, 0, 4470 PORT_SHARED_LIMITf, 126)); 4471 SOC_IF_ERROR_RETURN 4472 (soc_reg_field32_modify(unit, PORT_RESET_OFFSETr, 0, 4473 PORT_RESET_OFFSETf, 16)); 4474 PBMP_ALL_ITER(unit, p) { 4475 SOC_IF_ERROR_RETURN 4476 (soc_reg_fields32_modify(unit, PORT_PRI_GRP0r, p, 7, 4477 pri_grp0, pri_grp0_val)); 4478 SOC_IF_ERROR_RETURN 4479 (soc_reg_fields32_modify(unit, PORT_PRI_GRP1r, p, 7, 4480 pri_grp1, pri_grp1_val)); 4481 } 4482 SOC_IF_ERROR_RETURN 4483 (soc_reg_field32_modify(unit, TOTAL_SHARED_AVAIL_THRESHr, 4484 REG_PORT_ANY, TOTAL_SHARED_AVAIL_THRESHf, 4485 61022)); 4486 SOC_IF_ERROR_RETURN 4487 (soc_reg_field32_modify(unit, PG0_HDRM_LIMIT_OFFSETr, 4488 REG_PORT_ANY, PG0_HDRM_LIMIT_OFFSETf, 72)); 4489 SOC_IF_ERROR_RETURN 4490 (soc_reg_field32_modify(unit, PG1_HDRM_LIMIT_OFFSETr, 4491 REG_PORT_ANY, PG1_HDRM_LIMIT_OFFSETf, 72)); 4492 SOC_IF_ERROR_RETURN 4493 (soc_reg_field32_modify(unit, PG2_HDRM_LIMIT_OFFSETr, 4494 REG_PORT_ANY, PG2_HDRM_LIMIT_OFFSETf, 72)); 4495 SOC_IF_ERROR_RETURN 4496 (soc_reg_field32_modify(unit, PG3_HDRM_LIMIT_OFFSETr, 4497 REG_PORT_ANY, PG3_HDRM_LIMIT_OFFSETf, 72)); 4498 SOC_IF_ERROR_RETURN 4499 (soc_reg_field32_modify(unit, PG4_HDRM_LIMIT_OFFSETr, 4500 REG_PORT_ANY, PG4_HDRM_LIMIT_OFFSETf, 72)); 4501 SOC_IF_ERROR_RETURN 4502 (soc_reg_field32_modify(unit, PG5_HDRM_LIMIT_OFFSETr, 4503 REG_PORT_ANY, PG5_HDRM_LIMIT_OFFSETf, 72)); 4504 SOC_IF_ERROR_RETURN 4505 (soc_reg_field32_modify(unit, PG6_HDRM_LIMIT_OFFSETr, 4506 REG_PORT_ANY, PG6_HDRM_LIMIT_OFFSETf, 72)); 4507 SOC_IF_ERROR_RETURN 4508 (soc_reg_field32_modify(unit, PG7_HDRM_LIMIT_OFFSETr, 4509 REG_PORT_ANY, PG7_HDRM_LIMIT_OFFSETf, 72)); 4510 4511 4512 /* MTRO */ 4513 PBMP_XE_ITER(unit, p) { 4514 SOC_IF_ERROR_RETURN 4515 (soc_reg_field32_modify(unit, EGRMETERINGCONFIGr, 4516 p, METER_GRANf, 1)); 4517 SOC_IF_ERROR_RETURN 4518 (soc_reg_field32_modify(unit, EGRMETERINGCONFIGr, 4519 p, THRESHOLDf, 1056)); 4520 SOC_IF_ERROR_RETURN 4521 (soc_reg_field32_modify(unit, EGRMETERINGCONFIG1r, 4522 p, REFRESHf, 156250)); 4523 } 4524 4525 /* WRED */ 4526 for (p = 1; p <= 16; p++) { 4527 SOC_IF_ERROR_RETURN 4528 (soc_reg_field32_modify(unit, PORT_WREDCONFIG_CELLr, p, 4529 LB_ENABLEf, 1)); 4530 } 4531 4532 /* ES */ 4533 PBMP_ALL_ITER(unit, p) { 4534 SOC_IF_ERROR_RETURN 4535 (soc_reg_field32_modify(unit, ESCONFIGr, p, MTU_QUANTA_SELECTf, 2)); 4536 } 4537 SOC_IF_ERROR_RETURN 4538 (soc_reg_field32_modify(unit, INPUT_PORT_RX_ENABLEr, REG_PORT_ANY, 4539 INPUT_PORT_RX_ENABLEf, 43551)); 4540 SOC_IF_ERROR_RETURN 4541 (soc_reg_field32_modify(unit, OUTPUT_PORT_RX_ENABLEr, REG_PORT_ANY, 4542 OUTPUT_PORT_RX_ENABLEf, 43551)); 4543 SOC_IF_ERROR_RETURN 4544 (soc_reg_field32_modify(unit, PORTGRP_WDRR_CONFIGr, REG_PORT_ANY, 4545 PG_WDRR_MTU_QUANTA_SELECTf, 2)); 4546 for (idx = 0; idx < 60; idx++) { 4547 SOC_IF_ERROR_RETURN 4548 (soc_mem_field32_modify(unit, ES_ARB_TDM_TABLEm, idx, 4549 PORT_VECTORf, es_arb_tdm_table[idx])); 4550 SOC_IF_ERROR_RETURN 4551 (soc_mem_field32_modify(unit, ES_ARB_TDM_TABLEm, idx, 4552 SHAPER_ENf, 0)); 4553 SOC_IF_ERROR_RETURN 4554 (soc_mem_field32_modify(unit, ES_ARB_TDM_TABLEm, idx, 4555 SHAPER_IDf, 0)); 4556 } 4557 SOC_IF_ERROR_RETURN 4558 (soc_reg_field32_modify(unit, PORTGRP_WDRR_CONFIGr, REG_PORT_ANY, 4559 PG_WDRR_MTU_QUANTA_SELECTf, 2)); 4560 SOC_IF_ERROR_RETURN 4561 (soc_reg_field32_modify(unit, ES_TDM_CAL_CFGr, REG_PORT_ANY, 4562 END_Af, 59)); 4563 SOC_IF_ERROR_RETURN 4564 (soc_reg_field32_modify(unit, ES_TDM_CAL_CFGr, REG_PORT_ANY, 4565 END_Bf, 59)); 4566 SOC_IF_ERROR_RETURN 4567 (soc_reg_field32_modify(unit, ES_TDM_ENr, REG_PORT_ANY, 4568 ENf, 1)); 4569 4570 /* INTF */ 4571 SOC_IF_ERROR_RETURN 4572 (soc_reg_field32_modify(unit, MMU_LLFC_TX_CONFIG_3r, REG_PORT_ANY, 4573 BW_TIMER_VALUE_9_16f, 0)); 4574 SOC_IF_ERROR_RETURN 4575 (soc_reg_field32_modify(unit, MMU_LLFC_TX_CONFIG_4r, REG_PORT_ANY, 4576 XOFF_REFRESH_TIME_9_16f, 32)); 4577 SOC_IF_ERROR_RETURN 4578 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI15r, REG_PORT_ANY, 4579 COS0_7_BMPf, 128)); 4580 SOC_IF_ERROR_RETURN 4581 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI14r, REG_PORT_ANY, 4582 COS0_7_BMPf, 128)); 4583 SOC_IF_ERROR_RETURN 4584 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI13r, REG_PORT_ANY, 4585 COS0_7_BMPf, 128)); 4586 SOC_IF_ERROR_RETURN 4587 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI12r, REG_PORT_ANY, 4588 COS0_7_BMPf, 128)); 4589 SOC_IF_ERROR_RETURN 4590 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI11r, REG_PORT_ANY, 4591 COS0_7_BMPf, 128)); 4592 SOC_IF_ERROR_RETURN 4593 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI10r, REG_PORT_ANY, 4594 COS0_7_BMPf, 128)); 4595 SOC_IF_ERROR_RETURN 4596 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI9r, REG_PORT_ANY, 4597 COS0_7_BMPf, 128)); 4598 SOC_IF_ERROR_RETURN 4599 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI8r, REG_PORT_ANY, 4600 COS0_7_BMPf, 128)); 4601 SOC_IF_ERROR_RETURN 4602 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI7r, REG_PORT_ANY, 4603 COS0_7_BMPf, 128)); 4604 SOC_IF_ERROR_RETURN 4605 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI6r, REG_PORT_ANY, 4606 COS0_7_BMPf, 64)); 4607 SOC_IF_ERROR_RETURN 4608 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI5r, REG_PORT_ANY, 4609 COS0_7_BMPf, 32)); 4610 SOC_IF_ERROR_RETURN 4611 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI4r, REG_PORT_ANY, 4612 COS0_7_BMPf, 16)); 4613 SOC_IF_ERROR_RETURN 4614 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI3r, REG_PORT_ANY, 4615 COS0_7_BMPf, 8)); 4616 SOC_IF_ERROR_RETURN 4617 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI2r, REG_PORT_ANY, 4618 COS0_7_BMPf, 4)); 4619 SOC_IF_ERROR_RETURN 4620 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI1r, REG_PORT_ANY, 4621 COS0_7_BMPf, 2)); 4622 SOC_IF_ERROR_RETURN 4623 (soc_reg_field32_modify(unit, PRIO2COS_0_PRI0r, REG_PORT_ANY, 4624 COS0_7_BMPf, 1)); 4625 4626 /* AGING */ 4627 SOC_IF_ERROR_RETURN 4628 (soc_reg_field32_modify(unit, PKTAGINGTIMERr, REG_PORT_ANY, 4629 DURATIONSELECTf, 4096)); 4630 SOC_IF_ERROR_RETURN 4631 (soc_reg_fields32_modify(unit, PKTAGINGLIMIT0r, REG_PORT_ANY, 8, 4632 aging0_fld, aging0_val)); 4633 SOC_IF_ERROR_RETURN 4634 (soc_reg_fields32_modify(unit, PKTAGINGLIMIT1r, REG_PORT_ANY, 8, 4635 aging1_fld, aging1_val)); 4636 4637 /* CTR */ 4638 rval = 0; 4639 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, CNGf, 7); 4640 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, COSf, 15); 4641 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, DST_PORTf, 31); 4642 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, SRC_PORTf, 31); 4643 SOC_IF_ERROR_RETURN(WRITE_TX_CNT_CONFIGr_REG32(unit, 7, rval)); 4644 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, ALL_DROP_ACCEPTf, 1); 4645 SOC_IF_ERROR_RETURN(WRITE_TX_CNT_CONFIGr_REG32(unit, 6, rval)); 4646 rval = 0; 4647 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, CNGf, 7); 4648 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, COSf, 15); 4649 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, DST_PORTf, 31); 4650 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, SRC_PORTf, 31); 4651 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, ENQ_DEQf, 1); 4652 SOC_IF_ERROR_RETURN(WRITE_TX_CNT_CONFIGr_REG32(unit, 5, rval)); 4653 rval = 0; 4654 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, COSf, 15); 4655 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, DST_PORTf, 31); 4656 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, SRC_PORTf, 31); 4657 SOC_IF_ERROR_RETURN(WRITE_TX_CNT_CONFIGr_REG32(unit, 4, rval)); 4658 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, CNGf, 1); 4659 SOC_IF_ERROR_RETURN(WRITE_TX_CNT_CONFIGr_REG32(unit, 3, rval)); 4660 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, CNGf, 2); 4661 SOC_IF_ERROR_RETURN(WRITE_TX_CNT_CONFIGr_REG32(unit, 2, rval)); 4662 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, CNGf, 3); 4663 SOC_IF_ERROR_RETURN(WRITE_TX_CNT_CONFIGr_REG32(unit, 1, rval)); 4664 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, CNGf, 7); 4665 soc_reg_field_set(unit, TX_CNT_CONFIGr, &rval, ECN_MARKEDf, 1); 4666 SOC_IF_ERROR_RETURN(WRITE_TX_CNT_CONFIGr_REG32(unit, 0, rval)); 4667 4668 return SOC_E_NONE; 4669 } 4670 4671 4672 4673 4674 4675 4676 int 4677 soc_shadow_mmu_init(int unit) 4678 { 4679 /* Configure MMU based on the TDM */ 4680 if (soc_property_get(unit, spn_BCM88732_1X40_4X10, 0)) { 4681 SOC_IF_ERROR_RETURN(_shadow_tdm18_mmu_init(unit)); 4682 } else if (soc_property_get(unit, spn_BCM88732_4X10_4X10, 0)) { 4683 SOC_IF_ERROR_RETURN(_shadow_tdm19_mmu_init(unit)); 4684 } else if (soc_property_get(unit, spn_BCM88732_2X40_2X40, 0)) { 4685 SOC_IF_ERROR_RETURN(_shadow_tdm5_mmu_init(unit)); 4686 } else if (soc_property_get(unit, spn_BCM88732_2X40_1X40, 0)) { 4687 SOC_IF_ERROR_RETURN(_shadow_tdm6_mmu_init(unit)); 4688 } else if (soc_property_get(unit, spn_BCM88732_8X10_1X40, 0)) { 4689 SOC_IF_ERROR_RETURN(_shadow_tdm8_mmu_init(unit)); 4690 } else if (soc_property_get(unit, spn_BCM88732_8X10_2X40, 0)) { 4691 SOC_IF_ERROR_RETURN(_shadow_tdm7_mmu_init(unit)); 4692 } else if (soc_property_get(unit, spn_BCM88732_8X10_8X10, 0)) { 4693 SOC_IF_ERROR_RETURN(_shadow_tdm1_xfi_mmu_init(unit)); 4694 } else { /* if (soc_property_get(unit, spn_BCM88732_2X40_8X10, 0)) */ 4695 /* Default is 2x40 - 8x10 TDM */ 4696 SOC_IF_ERROR_RETURN(_shadow_tdm0_xfi_mmu_init(unit)); 4697 } 4698 4699 /* Initialize additional device mode MMU configurations */ 4700 if (soc_property_get(unit, spn_BCM88732_DEVICE_MODE, 0)) { 4701 SOC_IF_ERROR_RETURN(soc_shadow_petrab_mmu_init(unit)); 4702 } 4703 4704 return SOC_E_NONE; 4705 } 4706 4707 void soc_shadow_mmu_parity_error(void *unit, void *d1, void *d2, 4708 void *d3, void *d4 ) 4709 { 4710 int u = PTR_TO_INT(unit); 4711 4712 COMPILER_REFERENCE(d1); 4713 COMPILER_REFERENCE(d2); 4714 COMPILER_REFERENCE(d3); 4715 COMPILER_REFERENCE(d4); 4716 4717 soc_intr_enable(u, IRQ_MEM_FAIL); 4718 } 4719 4720 int 4721 soc_shadow_age_timer_get(int unit, int *age_seconds, int *enabled) 4722 { 4723 uint32 value; 4724 4725 SOC_IF_ERROR_RETURN(READ_L2_AGE_TIMERr(unit, &value)); 4726 *enabled = soc_reg_field_get(unit, L2_AGE_TIMERr, value, AGE_ENAf); 4727 *age_seconds = soc_reg_field_get(unit, L2_AGE_TIMERr, value, AGE_VALf); 4728 4729 return SOC_E_NONE; 4730 } 4731 4732 int 4733 soc_shadow_age_timer_max_get(int unit, int *max_seconds) 4734 { 4735 *max_seconds = 4736 soc_reg_field_get(unit, L2_AGE_TIMERr, 0xffffffff, AGE_VALf); 4737 4738 return SOC_E_NONE; 4739 } 4740 4741 int 4742 soc_shadow_age_timer_set(int unit, int age_seconds, int enable) 4743 { 4744 uint32 value; 4745 4746 value = 0; 4747 soc_reg_field_set(unit, L2_AGE_TIMERr, &value, AGE_ENAf, enable); 4748 soc_reg_field_set(unit, L2_AGE_TIMERr, &value, AGE_VALf, age_seconds); 4749 SOC_IF_ERROR_RETURN(WRITE_L2_AGE_TIMERr(unit, value)); 4750 4751 return SOC_E_NONE; 4752 } 4753 4754 /* 4755 * To support dynamic port configurations 4756 */ 4757 int 4758 _bcm_shadow_port_reconfig_40g(int unit, soc_port_t port) 4759 { 4760 uint64 mac_ctrl, rval64; 4761 uint32 rval, rval1, rval2, rval3; 4762 int count=0, i, p; 4763 soc_info_t *si; 4764 soc_field_t field_ids[1]; 4765 uint32 field_values[4]; 4766 port_tab_entry_t ptab; 4767 4768 if (port != 1 && port != 5) { 4769 return SOC_E_PARAM; 4770 } 4771 4772 si = &SOC_INFO(unit); 4773 /* Drain packets enqueued to port */ 4774 SOC_IF_ERROR_RETURN 4775 (soc_reg_field32_modify(unit, XLP_TXFIFO_PKT_DROP_CTLr, port, 4776 DROP_ENf, 1)); 4777 do { 4778 sal_usleep(10000); 4779 SOC_IF_ERROR_RETURN(READ_PORT_COUNTr(unit, port+8, &rval)); 4780 SOC_IF_ERROR_RETURN(READ_PORT_COUNTr(unit, port+9, &rval1)); 4781 SOC_IF_ERROR_RETURN(READ_PORT_COUNTr(unit, port+10, &rval2)); 4782 SOC_IF_ERROR_RETURN(READ_PORT_COUNTr(unit, port+11, &rval3)); 4783 count++; 4784 } while ((count < 5) && (rval & rval1 & rval2 & rval3)); 4785 4786 if (count >= 5) { 4787 return SOC_E_FAIL; 4788 } 4789 SOC_IF_ERROR_RETURN 4790 (soc_reg_field32_modify(unit, XLP_TXFIFO_PKT_DROP_CTLr, port, 4791 DROP_ENf, 0)); 4792 4793 /* Reconfigure the port to 40G */ 4794 /* disable transmit ports in use */ 4795 for (i = port; i < port+4; i++) { 4796 SOC_IF_ERROR_RETURN 4797 (soc_reg_field32_modify(unit, EGR_ENABLEr, i, PRT_ENABLEf, 0)); 4798 SOC_IF_ERROR_RETURN 4799 (soc_reg_field32_modify(unit, ECRCr, i, COUNTf, 0)); 4800 } 4801 4802 /* Reinitialize port in 40G mode */ 4803 if (port == 1) { 4804 SOC_IF_ERROR_RETURN 4805 (soc_reg_field32_modify(unit, EGR_EDB_DEBUG_SFT_RESETr, REG_PORT_ANY, 4806 MS0_RESETf, 1)); 4807 SOC_IF_ERROR_RETURN 4808 (soc_reg_field32_modify(unit, EGR_EDB_DEBUG_SFT_RESETr, REG_PORT_ANY, 4809 MS0_RESETf, 0)); 4810 SOC_IF_ERROR_RETURN 4811 (soc_reg_field32_modify(unit, EGR_PORT_MODEr, REG_PORT_ANY, 4812 MS0_PORT_MODEf, 0)); /* Single */ 4813 } else { /* port == 5 */ 4814 SOC_IF_ERROR_RETURN 4815 (soc_reg_field32_modify(unit, EGR_EDB_DEBUG_SFT_RESETr, REG_PORT_ANY, 4816 MS1_RESETf, 1)); 4817 SOC_IF_ERROR_RETURN 4818 (soc_reg_field32_modify(unit, EGR_EDB_DEBUG_SFT_RESETr, REG_PORT_ANY, 4819 MS1_RESETf, 0)); 4820 SOC_IF_ERROR_RETURN 4821 (soc_reg_field32_modify(unit, EGR_PORT_MODEr, REG_PORT_ANY, 4822 MS1_PORT_MODEf, 0)); /* Single */ 4823 } 4824 SOC_IF_ERROR_RETURN 4825 (soc_reg_field32_modify(unit, EGR_ENABLEr, port, PRT_ENABLEf, 1)); 4826 4827 /* Preenqueue reconfiguration */ 4828 rval = 0x4; /* SPEED = 40G, ENABLE = 1 */ 4829 if (port == 1) { 4830 int arb_tdm_index[] = {0, 5, 10, 15, 21, 26, 31, 36}; 4831 int es_arb_tdm_index[] = {0, 5, 10, 15, 20, 25, 30, 35, 40, 45, 50, 55}; 4832 arb_tdm_table_entry_t arb_tdm; 4833 es_arb_tdm_table_entry_t es_arb_tdm; 4834 4835 SOC_IF_ERROR_RETURN(WRITE_PORT_CONFIG0r(unit, rval)); 4836 rval = 0x5; /* SPEED = 40G, ENABLE = 1 */ 4837 SOC_IF_ERROR_RETURN(WRITE_PORT_CONFIG0r(unit, rval)); 4838 4839 /* Modify receive TDM table */ 4840 for (i = 0; i < 8; i++) { 4841 sal_memset(&arb_tdm, 0, sizeof(arb_tdm_table_entry_t)); 4842 soc_ARB_TDM_TABLEm_field32_set(unit, &arb_tdm, PORT_NUMf, 1); 4843 SOC_IF_ERROR_RETURN(WRITE_ARB_TDM_TABLEm(unit, SOC_BLOCK_ALL, 4844 arb_tdm_index[i], &arb_tdm)); 4845 } 4846 SOC_IF_ERROR_RETURN 4847 (soc_reg_field32_modify(unit, CMIC_SOFT_RESET_REGr, REG_PORT_ANY, 4848 MS0_SYS_RESET_Nf, 0)); 4849 SOC_IF_ERROR_RETURN 4850 (soc_reg_field32_modify(unit, CMIC_SOFT_RESET_REGr, REG_PORT_ANY, 4851 MS0_SYS_RESET_Nf, 1)); 4852 4853 for (i = 0; i < 12; i++) { 4854 sal_memset(&es_arb_tdm, 0, sizeof(es_arb_tdm_table_entry_t)); 4855 soc_ES_ARB_TDM_TABLEm_field32_set(unit, &es_arb_tdm, PORT_VECTORf, 4856 2); 4857 SOC_IF_ERROR_RETURN(WRITE_ES_ARB_TDM_TABLEm(unit, SOC_BLOCK_ALL, 4858 es_arb_tdm_index[i], 4859 &es_arb_tdm)); 4860 } 4861 4862 } else { 4863 int arb_tdm_index[] = {2, 7, 12, 17, 23, 28, 33, 38}; 4864 int es_arb_tdm_index[] = {2, 7, 12, 17, 22, 27, 32, 37, 42, 47, 52, 57}; 4865 arb_tdm_table_entry_t arb_tdm; 4866 es_arb_tdm_table_entry_t es_arb_tdm; 4867 4868 SOC_IF_ERROR_RETURN(WRITE_PORT_CONFIG1r(unit, rval)); 4869 rval = 0x5; /* SPEED = 40G, ENABLE = 1 */ 4870 SOC_IF_ERROR_RETURN(WRITE_PORT_CONFIG1r(unit, rval)); 4871 4872 /* Modify receive TDM table */ 4873 for (i = 0; i < 8; i++) { 4874 sal_memset(&arb_tdm, 0, sizeof(arb_tdm_table_entry_t)); 4875 soc_ARB_TDM_TABLEm_field32_set(unit, &arb_tdm, PORT_NUMf, 5); 4876 SOC_IF_ERROR_RETURN(WRITE_ARB_TDM_TABLEm(unit, SOC_BLOCK_ALL, 4877 arb_tdm_index[i], &arb_tdm)); 4878 } 4879 SOC_IF_ERROR_RETURN 4880 (soc_reg_field32_modify(unit, CMIC_SOFT_RESET_REGr, REG_PORT_ANY, 4881 MS1_SYS_RESET_Nf, 0)); 4882 SOC_IF_ERROR_RETURN 4883 (soc_reg_field32_modify(unit, CMIC_SOFT_RESET_REGr, REG_PORT_ANY, 4884 MS1_SYS_RESET_Nf, 1)); 4885 4886 for (i = 0; i < 12; i++) { 4887 sal_memset(&es_arb_tdm, 0, sizeof(es_arb_tdm_table_entry_t)); 4888 soc_ES_ARB_TDM_TABLEm_field32_set(unit, &es_arb_tdm, PORT_VECTORf, 4889 0x20); 4890 SOC_IF_ERROR_RETURN(WRITE_ES_ARB_TDM_TABLEm(unit, SOC_BLOCK_ALL, 4891 es_arb_tdm_index[i], 4892 &es_arb_tdm)); 4893 } 4894 } 4895 4896 rval = 0; 4897 soc_reg_field_set(unit, ESEC_GLOBAL_CTRLr, &rval, INITf, 1); 4898 SOC_IF_ERROR_RETURN 4899 (soc_reg32_write(unit, soc_reg_addr(unit, ESEC_GLOBAL_CTRLr, 4900 port, 0), rval)); 4901 for (i = port; i < port+4; i++) { 4902 rval = 0; 4903 soc_reg_field_set(unit, ESEC_MASTER_CTRLr, &rval, SOFT_RESETf, 1); 4904 SOC_IF_ERROR_RETURN(WRITE_ESEC_MASTER_CTRLr(unit, i, rval)); 4905 4906 rval = 0; 4907 soc_reg_field_set(unit, ISEC_MASTER_CTRLr, &rval, SOFT_RESETf, 1); 4908 SOC_IF_ERROR_RETURN(WRITE_ISEC_MASTER_CTRLr(unit, i, rval)); 4909 } 4910 4911 rval = 0; 4912 soc_reg_field_set(unit, ESEC_MASTER_CTRLr, &rval, SOFT_RESETf, 0); 4913 soc_reg_field_set(unit, ESEC_MASTER_CTRLr, &rval, BYPASS_ENf, 1); 4914 soc_reg_field_set(unit, ESEC_MASTER_CTRLr, &rval, ACTIVATE_PD_CREDITSf, 1); 4915 soc_reg_field_set(unit, ESEC_MASTER_CTRLr, &rval, EN_40Gf, 1); 4916 SOC_IF_ERROR_RETURN(WRITE_ESEC_MASTER_CTRLr(unit, port, rval)); 4917 4918 rval = 0; 4919 soc_reg_field_set(unit, ISEC_GLOBAL_CTRLr, &rval, INITf, 1); 4920 SOC_IF_ERROR_RETURN 4921 (soc_reg32_write(unit, soc_reg_addr(unit, ISEC_GLOBAL_CTRLr, 4922 port, 0), rval)); 4923 rval = 0; 4924 soc_reg_field_set(unit, ISEC_MASTER_CTRLr, &rval, SOFT_RESETf, 0); 4925 soc_reg_field_set(unit, ISEC_MASTER_CTRLr, &rval, BYPASS_ENf, 1); 4926 soc_reg_field_set(unit, ISEC_MASTER_CTRLr, &rval, EN_40Gf, 1); 4927 SOC_IF_ERROR_RETURN(WRITE_ISEC_MASTER_CTRLr(unit, port, rval)); 4928 4929 soc_reg_field_set(unit, XLPORT_XGXS_CTRL_REGr, &rval, TXD10G_FIFO_RSTBf, 0); 4930 soc_reg_field_set(unit, XLPORT_XGXS_CTRL_REGr, &rval, RSTB_PLLf, 0); 4931 soc_reg_field_set(unit, XLPORT_XGXS_CTRL_REGr, &rval, RSTB_MDIOREGSf, 0); 4932 soc_reg_field_set(unit, XLPORT_XGXS_CTRL_REGr, &rval, RSTB_HWf, 0); 4933 soc_reg_field_set(unit, XLPORT_XGXS_CTRL_REGr, &rval, LCREF_ENf, 1); 4934 soc_reg_field_set(unit, XLPORT_XGXS_CTRL_REGr, &rval, PLLBYPf, 0); 4935 soc_reg_field_set(unit, XLPORT_XGXS_CTRL_REGr, &rval, IDDQf, 1); 4936 soc_reg_field_set(unit, XLPORT_XGXS_CTRL_REGr, &rval, PWRDWNf, 1); 4937 soc_reg_field_set(unit, XLPORT_XGXS_CTRL_REGr, &rval, PWRDWN_PLLf, 1); 4938 SOC_IF_ERROR_RETURN(WRITE_XLPORT_XGXS_CTRL_REGr(unit, port, rval)); 4939 4940 rval = 0; 4941 soc_reg_field_set(unit, XLPORT_PORT_ENABLEr, &rval, PORT0f, 0); 4942 soc_reg_field_set(unit, XLPORT_PORT_ENABLEr, &rval, PORT1f, 0); 4943 soc_reg_field_set(unit, XLPORT_PORT_ENABLEr, &rval, PORT2f, 0); 4944 soc_reg_field_set(unit, XLPORT_PORT_ENABLEr, &rval, PORT3f, 0); 4945 SOC_IF_ERROR_RETURN(WRITE_XLPORT_PORT_ENABLEr(unit, port, rval)); 4946 4947 if (port == 1) { 4948 SOC_IF_ERROR_RETURN 4949 (soc_reg_field32_modify(unit, CMIC_SOFT_RESET_REGr, REG_PORT_ANY, 4950 XLPORT0_LOGIC_RESET_Nf, 0)); 4951 SOC_IF_ERROR_RETURN 4952 (soc_reg_field32_modify(unit, CMIC_SOFT_RESET_REGr, REG_PORT_ANY, 4953 XLPORT0_LOGIC_RESET_Nf, 1)); 4954 } else { 4955 SOC_IF_ERROR_RETURN 4956 (soc_reg_field32_modify(unit, CMIC_SOFT_RESET_REGr, REG_PORT_ANY, 4957 XLPORT1_LOGIC_RESET_Nf, 0)); 4958 SOC_IF_ERROR_RETURN 4959 (soc_reg_field32_modify(unit, CMIC_SOFT_RESET_REGr, REG_PORT_ANY, 4960 XLPORT1_LOGIC_RESET_Nf, 1)); 4961 } 4962 4963 SOC_IF_ERROR_RETURN(soc_xgxs_reset(unit, port)); 4964 4965 /* Deal with XLPORT block */ 4966 /* put XMAC in reset*/ 4967 for (i = port; i < port+4; i++) { 4968 /* toggle Reset */ 4969 SOC_IF_ERROR_RETURN(READ_XMAC_CTRLr(unit, i, &mac_ctrl)); 4970 soc_reg64_field32_set(unit, XMAC_CTRLr, &mac_ctrl, SOFT_RESETf, 1); 4971 SOC_IF_ERROR_RETURN(WRITE_XMAC_CTRLr(unit, i, mac_ctrl)); 4972 } 4973 4974 rval = 0; 4975 soc_reg_field_set(unit, XLPORT_MODE_REGr, &rval, CORE_PORT_MODEf, 0); 4976 soc_reg_field_set(unit, XLPORT_MODE_REGr, &rval, PHY_PORT_MODEf, 0); 4977 4978 /* Bring XMAC out of reset */ 4979 SOC_IF_ERROR_RETURN(READ_XMAC_CTRLr(unit, port, &mac_ctrl)); 4980 soc_reg64_field32_set(unit, XMAC_CTRLr, &mac_ctrl, SOFT_RESETf, 0); 4981 SOC_IF_ERROR_RETURN(WRITE_XMAC_CTRLr(unit, port, mac_ctrl)); 4982 4983 /* Reset XLPORT MIB counter */ 4984 rval = 0; 4985 soc_reg_field_set(unit, XLPORT_MIB_RESETr, &rval, CLR_CNTf, 0x1); 4986 SOC_IF_ERROR_RETURN(WRITE_XLPORT_MIB_RESETr(unit, port, rval)); 4987 SOC_IF_ERROR_RETURN(WRITE_XLPORT_MIB_RESETr(unit, port, 0)); 4988 4989 /* Enable XLPORT */ 4990 rval = 0; 4991 soc_reg_field_set(unit, XLPORT_PORT_ENABLEr, &rval, PORT0f, 1); 4992 soc_reg_field_set(unit, XLPORT_PORT_ENABLEr, &rval, PORT1f, 0); 4993 soc_reg_field_set(unit, XLPORT_PORT_ENABLEr, &rval, PORT2f, 0); 4994 soc_reg_field_set(unit, XLPORT_PORT_ENABLEr, &rval, PORT3f, 0); 4995 SOC_IF_ERROR_RETURN(WRITE_XLPORT_PORT_ENABLEr(unit, port, rval)); 4996 4997 /* Provide XMAC reset to ensure valid warpcore clock */ 4998 SOC_IF_ERROR_RETURN(WRITE_XLPORT_XMAC_CONTROLr(unit, port, 1)); 4999 SOC_IF_ERROR_RETURN(WRITE_XLPORT_XMAC_CONTROLr(unit, port, 0)); 5000 5001 /* Reinitialize XLPORT block */ 5002 /* Deal with XLPORT block */ 5003 /* Bring XMAC out of reset */ 5004 SOC_IF_ERROR_RETURN(READ_XMAC_CTRLr(unit, port, &mac_ctrl)); 5005 soc_reg64_field32_set(unit, XMAC_CTRLr, &mac_ctrl, SOFT_RESETf, 0); 5006 SOC_IF_ERROR_RETURN(WRITE_XMAC_CTRLr(unit, port, mac_ctrl)); 5007 5008 rval = 0; 5009 soc_reg_field_set(unit, XLPORT_MODE_REGr, &rval, CORE_PORT_MODEf, 0); 5010 soc_reg_field_set(unit, XLPORT_MODE_REGr, &rval, PHY_PORT_MODEf, 0); 5011 SOC_IF_ERROR_RETURN(WRITE_XLPORT_MODE_REGr(unit, port, rval)); 5012 5013 /* Reset XLPORT MIB counter */ 5014 rval = 0; 5015 soc_reg_field_set(unit, XLPORT_MIB_RESETr, &rval, CLR_CNTf, 0x1); 5016 SOC_IF_ERROR_RETURN(WRITE_XLPORT_MIB_RESETr(unit, port, rval)); 5017 SOC_IF_ERROR_RETURN(WRITE_XLPORT_MIB_RESETr(unit, port, 0)); 5018 5019 /* Enable XLPORT */ 5020 rval = 0; 5021 soc_reg_field_set(unit, XLPORT_PORT_ENABLEr, &rval, PORT0f, 1); 5022 soc_reg_field_set(unit, XLPORT_PORT_ENABLEr, &rval, PORT1f, 0); 5023 soc_reg_field_set(unit, XLPORT_PORT_ENABLEr, &rval, PORT2f, 0); 5024 soc_reg_field_set(unit, XLPORT_PORT_ENABLEr, &rval, PORT3f, 0); 5025 SOC_IF_ERROR_RETURN(WRITE_XLPORT_PORT_ENABLEr(unit, port, rval)); 5026 5027 5028 si->port_num_lanes[port] = 4; 5029 5030 /* Provision buffers for the newly created port */ 5031 SOC_IF_ERROR_RETURN 5032 (soc_reg_field32_modify(unit, PORT_MINr, port, PORT_MINf, 8)); 5033 SOC_IF_ERROR_RETURN 5034 (soc_reg_field32_modify(unit, PORT_SHARED_LIMITr, port, 5035 PORT_SHARED_LIMITf, 62304)); 5036 for (i = port+1; i < port+4; i++) { 5037 SOC_IF_ERROR_RETURN 5038 (soc_reg_field32_modify(unit, PORT_MINr, i, PORT_MINf, 0)); 5039 SOC_IF_ERROR_RETURN 5040 (soc_reg_field32_modify(unit, PORT_SHARED_LIMITr, i, 5041 PORT_SHARED_LIMITf, 0)); 5042 5043 } 5044 SOC_IF_ERROR_RETURN 5045 (soc_reg_field32_modify(unit, EGRMETERINGCONFIGr, port, METER_GRANf, 3)); 5046 SOC_IF_ERROR_RETURN 5047 (soc_reg_field32_modify(unit, EGRMETERINGCONFIGr, port, THRESHOLDf, 0)); 5048 SOC_IF_ERROR_RETURN 5049 (soc_reg_field32_modify(unit, EGRMETERINGCONFIG1r, port, REFRESHf, 156250)); 5050 5051 for (i = port+8; i < port+12; i++) { 5052 SOC_IF_ERROR_RETURN 5053 (soc_reg_field32_modify(unit, PORT_MINr, i, PORT_MINf, 8)); 5054 SOC_IF_ERROR_RETURN 5055 (soc_reg_field32_modify(unit, PORT_SHARED_LIMITr, i, 5056 PORT_SHARED_LIMITf, 3200)); 5057 5058 } 5059 for (i = 0; i < 8; i++) { 5060 SOC_IF_ERROR_RETURN(READ_PG_HDRM_LIMITr(unit, port, i, &rval)); 5061 soc_reg_field_set(unit, PG_HDRM_LIMITr, &rval, PG_HDRM_LIMITf, 1133); 5062 SOC_IF_ERROR_RETURN(WRITE_PG_HDRM_LIMITr(unit, port, i, rval)); 5063 } 5064 for (i = port+8; i < port+12; i++) { 5065 SOC_IF_ERROR_RETURN 5066 (soc_reg_field32_modify(unit, PORT_WREDCONFIG_CELLr, i, 5067 LB_WEIGHTf, 4)); 5068 SOC_IF_ERROR_RETURN 5069 (soc_reg_field32_modify(unit, PORT_WREDCONFIG_CELLr, i, 5070 LB_ENABLEf, 0)); 5071 } 5072 SOC_IF_ERROR_RETURN 5073 (soc_reg_field32_modify(unit, INPUT_PORT_RX_ENABLEr, REG_PORT_ANY, 5074 INPUT_PORT_RX_ENABLEf, 0x1ffff)); 5075 SOC_IF_ERROR_RETURN 5076 (soc_reg_field32_modify(unit, OUTPUT_PORT_RX_ENABLEr, REG_PORT_ANY, 5077 OUTPUT_PORT_RX_ENABLEf, 0x1ffff)); 5078 5079 /* Clear any transients */ 5080 SOC_IF_ERROR_RETURN(READ_RFRGr(unit, port, &rval64)); 5081 SOC_IF_ERROR_RETURN(READ_RFCSr(unit, port, &rval64)); 5082 SOC_IF_ERROR_RETURN(READ_RERPKTr(unit, port, &rval64)); 5083 SOC_IF_ERROR_RETURN(READ_TPKTr(unit, port, &rval64)); 5084 SOC_IF_ERROR_RETURN(READ_RUCr(unit, port, &rval64)); 5085 SOC_IF_ERROR_RETURN(READ_RDROPr(unit, port, &rval64)); 5086 5087 /* Setup Static load balance */ 5088 if (port == 1) { 5089 /* Setup Static load balance */ 5090 field_ids[0] = DEST_PORT_OFFSETf; 5091 for (i = 0; i < 65535; i+=4) { 5092 field_values[0] = 8; 5093 SOC_IF_ERROR_RETURN 5094 (soc_mem_fields32_modify(unit, UFLOW_Am, i, 1, 5095 field_ids, field_values)); 5096 field_values[0] = 9; 5097 SOC_IF_ERROR_RETURN 5098 (soc_mem_fields32_modify(unit, UFLOW_Am, i+1, 1, 5099 field_ids, field_values)); 5100 field_values[0] = 10; 5101 SOC_IF_ERROR_RETURN 5102 (soc_mem_fields32_modify(unit, UFLOW_Am, i+2, 1, 5103 field_ids, field_values)); 5104 field_values[0] = 11; 5105 SOC_IF_ERROR_RETURN 5106 (soc_mem_fields32_modify(unit, UFLOW_Am, i+3, 1, 5107 field_ids, field_values)); 5108 } 5109 /* Configure Port Table to use UFLOW_A */ 5110 SOC_IF_ERROR_RETURN( 5111 READ_PORT_TABm(unit, MEM_BLOCK_ANY, 1, &ptab)); 5112 soc_PORT_TABm_field32_set(unit, &ptab, AGGREGATION_GROUP_SELECTf, 0); 5113 SOC_IF_ERROR_RETURN( 5114 WRITE_PORT_TABm(unit,MEM_BLOCK_ALL, 1, &ptab)); 5115 5116 /* UFLOW_PORT reg will use UFLOW_A for load balance */ 5117 SOC_IF_ERROR_RETURN 5118 (soc_reg_field32_modify(unit, UFLOW_PORT_CONTROLr, 1, 5119 DEST_PORTf, 0)); 5120 SOC_IF_ERROR_RETURN 5121 (soc_reg_field32_modify(unit, UFLOW_PORT_CONTROLr, 1, 5122 HASH_MODEf, 1)); 5123 /* For switch link ports (9-12) use port 1 as the destination port */ 5124 for (p = 9; p <= 12; p++) { 5125 SOC_IF_ERROR_RETURN 5126 (soc_reg_field32_modify(unit, UFLOW_PORT_CONTROLr, p, 5127 DEST_PORTf, 1)); 5128 SOC_IF_ERROR_RETURN 5129 (soc_reg_field32_modify(unit, UFLOW_PORT_CONTROLr, p, 5130 HASH_MODEf, 0)); 5131 } 5132 } else { 5133 /* Setup Static load balance for Port 5*/ 5134 field_ids[0] = DEST_PORT_OFFSETf; 5135 for (i = 0; i < 65535; i+=4) { 5136 field_values[0] = 12; 5137 SOC_IF_ERROR_RETURN 5138 (soc_mem_fields32_modify(unit, UFLOW_Bm, i, 1, 5139 field_ids, field_values)); 5140 field_values[0] = 13; 5141 SOC_IF_ERROR_RETURN 5142 (soc_mem_fields32_modify(unit, UFLOW_Bm, i+1, 1, 5143 field_ids, field_values)); 5144 field_values[0] = 14; 5145 SOC_IF_ERROR_RETURN 5146 (soc_mem_fields32_modify(unit, UFLOW_Bm, i+2, 1, 5147 field_ids, field_values)); 5148 field_values[0] = 15; 5149 SOC_IF_ERROR_RETURN 5150 (soc_mem_fields32_modify(unit, UFLOW_Bm, i+3, 1, 5151 field_ids, field_values)); 5152 } 5153 /* port 5 configure uflow_b for static load balancing */ 5154 SOC_IF_ERROR_RETURN( 5155 READ_PORT_TABm(unit, MEM_BLOCK_ANY, 5, &ptab)); 5156 soc_PORT_TABm_field32_set(unit, &ptab, AGGREGATION_GROUP_SELECTf, 1); 5157 SOC_IF_ERROR_RETURN( 5158 WRITE_PORT_TABm(unit,MEM_BLOCK_ALL, 5, &ptab)); 5159 5160 /* UFLOW_PORT reg will use UFLOW_A for load balance */ 5161 SOC_IF_ERROR_RETURN 5162 (soc_reg_field32_modify(unit, UFLOW_PORT_CONTROLr, 5, 5163 DEST_PORTf, 0)); 5164 SOC_IF_ERROR_RETURN 5165 (soc_reg_field32_modify(unit, UFLOW_PORT_CONTROLr, 5, 5166 HASH_MODEf, 1)); 5167 5168 /* For switch link ports (13-16) use port 5 as the destination port */ 5169 for (p = 13; p <= 16; p++) { 5170 SOC_IF_ERROR_RETURN 5171 (soc_reg_field32_modify(unit, UFLOW_PORT_CONTROLr, p, 5172 DEST_PORTf, 5)); 5173 SOC_IF_ERROR_RETURN 5174 (soc_reg_field32_modify(unit, UFLOW_PORT_CONTROLr, p, 5175 HASH_MODEf, 0)); 5176 } 5177 } 5178 5179 return SOC_E_NONE; 5180 } 5181 5182 /* 5183 * To support dynamic port configurations 5184 */ 5185 int 5186 _bcm_shadow_port_reconfig_10g(int unit, soc_port_t port) 5187 { 5188 uint64 rval64; 5189 uint32 rval; 5190 int count=0, i, p; 5191 soc_info_t *si; 5192 5193 if (port != 1 && port != 5) { 5194 return SOC_E_PARAM; 5195 } 5196 5197 si = &SOC_INFO(unit); 5198 /* Drain packets enqueued to port */ 5199 SOC_IF_ERROR_RETURN 5200 (soc_reg_field32_modify(unit, XLP_TXFIFO_PKT_DROP_CTLr, port, 5201 DROP_ENf, 1)); 5202 do { 5203 sal_usleep(10000); 5204 SOC_IF_ERROR_RETURN(READ_PORT_COUNTr(unit, port+8, &rval)); 5205 count++; 5206 } while ((count < 5) && (rval)); 5207 5208 if (count >= 5) { 5209 return SOC_E_FAIL; 5210 } 5211 SOC_IF_ERROR_RETURN 5212 (soc_reg_field32_modify(unit, XLP_TXFIFO_PKT_DROP_CTLr, port, 5213 DROP_ENf, 0)); 5214 5215 /* Reconfigure the port to 10G */ 5216 /* disable transmit ports in use */ 5217 for (i = port; i < port+4; i++) { 5218 SOC_IF_ERROR_RETURN 5219 (soc_reg_field32_modify(unit, EGR_ENABLEr, i, PRT_ENABLEf, 0)); 5220 SOC_IF_ERROR_RETURN 5221 (soc_reg_field32_modify(unit, ECRCr, i, COUNTf, 0)); 5222 } 5223 5224 /* Reinitialize port in 10G mode */ 5225 if (port == 1) { 5226 SOC_IF_ERROR_RETURN 5227 (soc_reg_field32_modify(unit, EGR_EDB_DEBUG_SFT_RESETr, REG_PORT_ANY, 5228 MS0_RESETf, 1)); 5229 SOC_IF_ERROR_RETURN 5230 (soc_reg_field32_modify(unit, EGR_EDB_DEBUG_SFT_RESETr, REG_PORT_ANY, 5231 MS0_RESETf, 0)); 5232 SOC_IF_ERROR_RETURN 5233 (soc_reg_field32_modify(unit, EGR_PORT_MODEr, REG_PORT_ANY, 5234 MS0_PORT_MODEf, 2)); /* Quad */ 5235 } else { /* port == 5 */ 5236 SOC_IF_ERROR_RETURN 5237 (soc_reg_field32_modify(unit, EGR_EDB_DEBUG_SFT_RESETr, REG_PORT_ANY, 5238 MS1_RESETf, 1)); 5239 SOC_IF_ERROR_RETURN 5240 (soc_reg_field32_modify(unit, EGR_EDB_DEBUG_SFT_RESETr, REG_PORT_ANY, 5241 MS1_RESETf, 0)); 5242 SOC_IF_ERROR_RETURN 5243 (soc_reg_field32_modify(unit, EGR_PORT_MODEr, REG_PORT_ANY, 5244 MS1_PORT_MODEf, 2)); /* Quad */ 5245 } 5246 for (i = port; i < port+4; i++) { 5247 SOC_IF_ERROR_RETURN 5248 (soc_reg_field32_modify(unit, EGR_ENABLEr, i, PRT_ENABLEf, 1)); 5249 } 5250 5251 /* Preenqueue reconfiguration */ 5252 rval = 0x0; /* SPEED = 10G, ENABLE = 1 */ 5253 if (port == 1) { 5254 int arb_tdm_index[] = {0, 5, 10, 15, 21, 26, 31, 36}; 5255 int arb_tdm_ports[] = {1, 2, 3, 4, 1, 2, 3, 4}; 5256 int es_arb_tdm_index[] = {0, 5, 10, 15, 20, 25, 30, 35, 40, 45, 50, 55}; 5257 int es_arb_tdm_vector[] = {2, 4, 8, 16, 2, 4, 8, 16, 2, 4, 8, 16}; 5258 arb_tdm_table_entry_t arb_tdm; 5259 es_arb_tdm_table_entry_t es_arb_tdm; 5260 5261 SOC_IF_ERROR_RETURN(WRITE_PORT_CONFIG0r(unit, rval)); 5262 rval = 0x1; /* SPEED = 10G, ENABLE = 1 */ 5263 SOC_IF_ERROR_RETURN(WRITE_PORT_CONFIG0r(unit, rval)); 5264 5265 /* Modify receive TDM table */ 5266 for (i = 0; i < 8; i++) { 5267 sal_memset(&arb_tdm, 0, sizeof(arb_tdm_table_entry_t)); 5268 soc_ARB_TDM_TABLEm_field32_set(unit, &arb_tdm, PORT_NUMf, 5269 arb_tdm_ports[i]); 5270 SOC_IF_ERROR_RETURN(WRITE_ARB_TDM_TABLEm(unit, SOC_BLOCK_ALL, 5271 arb_tdm_index[i], &arb_tdm)); 5272 } 5273 SOC_IF_ERROR_RETURN 5274 (soc_reg_field32_modify(unit, CMIC_SOFT_RESET_REGr, REG_PORT_ANY, 5275 MS0_SYS_RESET_Nf, 0)); 5276 SOC_IF_ERROR_RETURN 5277 (soc_reg_field32_modify(unit, CMIC_SOFT_RESET_REGr, REG_PORT_ANY, 5278 MS0_SYS_RESET_Nf, 1)); 5279 5280 for (i = 0; i < 12; i++) { 5281 sal_memset(&es_arb_tdm, 0, sizeof(es_arb_tdm_table_entry_t)); 5282 soc_ES_ARB_TDM_TABLEm_field32_set(unit, &es_arb_tdm, PORT_VECTORf, 5283 es_arb_tdm_vector[i]); 5284 SOC_IF_ERROR_RETURN(WRITE_ES_ARB_TDM_TABLEm(unit, SOC_BLOCK_ALL, 5285 es_arb_tdm_index[i], 5286 &es_arb_tdm)); 5287 } 5288 5289 } else { 5290 int arb_tdm_index[] = {2, 7, 12, 17, 23, 28, 33, 38}; 5291 int arb_tdm_ports[] = {5, 6, 7, 8, 5, 6, 7, 8}; 5292 int es_arb_tdm_index[] = {2, 7, 12, 17, 22, 27, 32, 37, 42, 47, 52, 57}; 5293 int es_arb_tdm_vector[] = {0x20, 0x40, 0x80, 0x100, 5294 0x20, 0x40, 0x80, 0x100, 5295 0x20, 0x40, 0x80, 0x100}; 5296 5297 arb_tdm_table_entry_t arb_tdm; 5298 es_arb_tdm_table_entry_t es_arb_tdm; 5299 5300 SOC_IF_ERROR_RETURN(WRITE_PORT_CONFIG1r(unit, rval)); 5301 rval = 0x1; /* SPEED = 40G, ENABLE = 1 */ 5302 SOC_IF_ERROR_RETURN(WRITE_PORT_CONFIG1r(unit, rval)); 5303 5304 /* Modify receive TDM table */ 5305 for (i = 0; i < 8; i++) { 5306 sal_memset(&arb_tdm, 0, sizeof(arb_tdm_table_entry_t)); 5307 soc_ARB_TDM_TABLEm_field32_set(unit, &arb_tdm, PORT_NUMf, 5308 arb_tdm_ports[i]); 5309 SOC_IF_ERROR_RETURN(WRITE_ARB_TDM_TABLEm(unit, SOC_BLOCK_ALL, 5310 arb_tdm_index[i], &arb_tdm)); 5311 } 5312 SOC_IF_ERROR_RETURN 5313 (soc_reg_field32_modify(unit, CMIC_SOFT_RESET_REGr, REG_PORT_ANY, 5314 MS1_SYS_RESET_Nf, 0)); 5315 SOC_IF_ERROR_RETURN 5316 (soc_reg_field32_modify(unit, CMIC_SOFT_RESET_REGr, REG_PORT_ANY, 5317 MS1_SYS_RESET_Nf, 1)); 5318 5319 for (i = 0; i < 12; i++) { 5320 sal_memset(&es_arb_tdm, 0, sizeof(es_arb_tdm_table_entry_t)); 5321 soc_ES_ARB_TDM_TABLEm_field32_set(unit, &es_arb_tdm, PORT_VECTORf, 5322 es_arb_tdm_vector[i]); 5323 SOC_IF_ERROR_RETURN(WRITE_ES_ARB_TDM_TABLEm(unit, SOC_BLOCK_ALL, 5324 es_arb_tdm_index[i], 5325 &es_arb_tdm)); 5326 } 5327 } 5328 5329 rval = 0; 5330 soc_reg_field_set(unit, ESEC_GLOBAL_CTRLr, &rval, INITf, 1); 5331 SOC_IF_ERROR_RETURN 5332 (soc_reg32_write(unit, soc_reg_addr(unit, ESEC_GLOBAL_CTRLr, 5333 port, 0), rval)); 5334 rval = 0; 5335 soc_reg_field_set(unit, ISEC_GLOBAL_CTRLr, &rval, INITf, 1); 5336 SOC_IF_ERROR_RETURN 5337 (soc_reg32_write(unit, soc_reg_addr(unit, ISEC_GLOBAL_CTRLr, 5338 port, 0), rval)); 5339 for (i = port; i < port+4; i++) { 5340 rval = 0; 5341 soc_reg_field_set(unit, ESEC_MASTER_CTRLr, &rval, SOFT_RESETf, 1); 5342 SOC_IF_ERROR_RETURN(WRITE_ESEC_MASTER_CTRLr(unit, i, rval)); 5343 5344 rval = 0; 5345 soc_reg_field_set(unit, ESEC_MASTER_CTRLr, &rval, SOFT_RESETf, 0); 5346 soc_reg_field_set(unit, ESEC_MASTER_CTRLr, &rval, BYPASS_ENf, 1); 5347 soc_reg_field_set(unit, ESEC_MASTER_CTRLr, &rval, ACTIVATE_PD_CREDITSf, 1); 5348 soc_reg_field_set(unit, ESEC_MASTER_CTRLr, &rval, EN_40Gf, 0); 5349 SOC_IF_ERROR_RETURN(WRITE_ESEC_MASTER_CTRLr(unit, i, rval)); 5350 5351 rval = 0; 5352 soc_reg_field_set(unit, ISEC_MASTER_CTRLr, &rval, SOFT_RESETf, 1); 5353 SOC_IF_ERROR_RETURN(WRITE_ISEC_MASTER_CTRLr(unit, i, rval)); 5354 5355 rval = 0; 5356 soc_reg_field_set(unit, ISEC_MASTER_CTRLr, &rval, SOFT_RESETf, 0); 5357 soc_reg_field_set(unit, ISEC_MASTER_CTRLr, &rval, BYPASS_ENf, 1); 5358 soc_reg_field_set(unit, ISEC_MASTER_CTRLr, &rval, EN_40Gf, 0); 5359 SOC_IF_ERROR_RETURN(WRITE_ISEC_MASTER_CTRLr(unit, i, rval)); 5360 } 5361 5362 soc_reg_field_set(unit, XLPORT_XGXS_CTRL_REGr, &rval, TXD10G_FIFO_RSTBf, 0); 5363 soc_reg_field_set(unit, XLPORT_XGXS_CTRL_REGr, &rval, RSTB_PLLf, 0); 5364 soc_reg_field_set(unit, XLPORT_XGXS_CTRL_REGr, &rval, RSTB_MDIOREGSf, 0); 5365 soc_reg_field_set(unit, XLPORT_XGXS_CTRL_REGr, &rval, RSTB_HWf, 0); 5366 soc_reg_field_set(unit, XLPORT_XGXS_CTRL_REGr, &rval, LCREF_ENf, 1); 5367 soc_reg_field_set(unit, XLPORT_XGXS_CTRL_REGr, &rval, PLLBYPf, 0); 5368 soc_reg_field_set(unit, XLPORT_XGXS_CTRL_REGr, &rval, IDDQf, 1); 5369 soc_reg_field_set(unit, XLPORT_XGXS_CTRL_REGr, &rval, PWRDWNf, 1); 5370 soc_reg_field_set(unit, XLPORT_XGXS_CTRL_REGr, &rval, PWRDWN_PLLf, 1); 5371 SOC_IF_ERROR_RETURN(WRITE_XLPORT_XGXS_CTRL_REGr(unit, port, rval)); 5372 5373 rval = 0; 5374 soc_reg_field_set(unit, XLPORT_PORT_ENABLEr, &rval, PORT0f, 0); 5375 soc_reg_field_set(unit, XLPORT_PORT_ENABLEr, &rval, PORT1f, 0); 5376 soc_reg_field_set(unit, XLPORT_PORT_ENABLEr, &rval, PORT2f, 0); 5377 soc_reg_field_set(unit, XLPORT_PORT_ENABLEr, &rval, PORT3f, 0); 5378 SOC_IF_ERROR_RETURN(WRITE_XLPORT_PORT_ENABLEr(unit, port, rval)); 5379 5380 if (port == 1) { 5381 SOC_IF_ERROR_RETURN 5382 (soc_reg_field32_modify(unit, CMIC_SOFT_RESET_REGr, REG_PORT_ANY, 5383 XLPORT0_LOGIC_RESET_Nf, 0)); 5384 SOC_IF_ERROR_RETURN 5385 (soc_reg_field32_modify(unit, CMIC_SOFT_RESET_REGr, REG_PORT_ANY, 5386 XLPORT0_LOGIC_RESET_Nf, 1)); 5387 } else { 5388 SOC_IF_ERROR_RETURN 5389 (soc_reg_field32_modify(unit, CMIC_SOFT_RESET_REGr, REG_PORT_ANY, 5390 XLPORT1_LOGIC_RESET_Nf, 0)); 5391 SOC_IF_ERROR_RETURN 5392 (soc_reg_field32_modify(unit, CMIC_SOFT_RESET_REGr, REG_PORT_ANY, 5393 XLPORT1_LOGIC_RESET_Nf, 1)); 5394 } 5395 5396 SOC_IF_ERROR_RETURN(soc_xgxs_reset(unit, port)); 5397 /* put XMAC in reset*/ 5398 for (i = port; i < port+4; i++) { 5399 SOC_IF_ERROR_RETURN(READ_XMAC_CTRLr(unit, i, &rval64)); 5400 soc_reg64_field32_set(unit, XMAC_CTRLr, &rval64, SOFT_RESETf, 1); 5401 SOC_IF_ERROR_RETURN(WRITE_XMAC_CTRLr(unit, i, rval64)); 5402 } 5403 5404 /* Deal with XLPORT block */ 5405 rval = 0; 5406 soc_reg_field_set(unit, XLPORT_MODE_REGr, &rval, CORE_PORT_MODEf, 2); 5407 soc_reg_field_set(unit, XLPORT_MODE_REGr, &rval, PHY_PORT_MODEf, 2); 5408 SOC_IF_ERROR_RETURN(WRITE_XLPORT_MODE_REGr(unit, port, rval)); 5409 5410 /* Bring XMAC out of reset */ 5411 for (i = port; i < port+4; i++) { 5412 SOC_IF_ERROR_RETURN(READ_XMAC_CTRLr(unit, i, &rval64)); 5413 soc_reg64_field32_set(unit, XMAC_CTRLr, &rval64, SOFT_RESETf, 0); 5414 SOC_IF_ERROR_RETURN(WRITE_XMAC_CTRLr(unit, i, rval64)); 5415 } 5416 5417 /* Reset XLPORT MIB counter */ 5418 rval = 0; 5419 soc_reg_field_set(unit, XLPORT_MIB_RESETr, &rval, CLR_CNTf, 0x1); 5420 SOC_IF_ERROR_RETURN(WRITE_XLPORT_MIB_RESETr(unit, port, rval)); 5421 SOC_IF_ERROR_RETURN(WRITE_XLPORT_MIB_RESETr(unit, port, 0)); 5422 5423 /* Enable XLPORT */ 5424 rval = 0; 5425 soc_reg_field_set(unit, XLPORT_PORT_ENABLEr, &rval, PORT0f, 1); 5426 soc_reg_field_set(unit, XLPORT_PORT_ENABLEr, &rval, PORT1f, 1); 5427 soc_reg_field_set(unit, XLPORT_PORT_ENABLEr, &rval, PORT2f, 1); 5428 soc_reg_field_set(unit, XLPORT_PORT_ENABLEr, &rval, PORT3f, 1); 5429 SOC_IF_ERROR_RETURN(WRITE_XLPORT_PORT_ENABLEr(unit, port, rval)); 5430 5431 /* Provide XMAC reset to ensure valid warpcore clock */ 5432 SOC_IF_ERROR_RETURN(WRITE_XLPORT_XMAC_CONTROLr(unit, port, 1)); 5433 SOC_IF_ERROR_RETURN(WRITE_XLPORT_XMAC_CONTROLr(unit, port, 0)); 5434 5435 5436 /* Reinitialize XLPORT block */ 5437 /* Deal with XLPORT block */ 5438 rval = 0; 5439 soc_reg_field_set(unit, XLPORT_MODE_REGr, &rval, CORE_PORT_MODEf, 2); 5440 soc_reg_field_set(unit, XLPORT_MODE_REGr, &rval, PHY_PORT_MODEf, 2); 5441 SOC_IF_ERROR_RETURN(WRITE_XLPORT_MODE_REGr(unit, port, rval)); 5442 5443 /* Bring XMAC out of reset */ 5444 for (i = port; i < port+4; i++) { 5445 SOC_IF_ERROR_RETURN(READ_XMAC_CTRLr(unit, i, &rval64)); 5446 soc_reg64_field32_set(unit, XMAC_CTRLr, &rval64, SOFT_RESETf, 0); 5447 SOC_IF_ERROR_RETURN(WRITE_XMAC_CTRLr(unit, i, rval64)); 5448 } 5449 5450 /* Reset XLPORT MIB counter */ 5451 rval = 0; 5452 soc_reg_field_set(unit, XLPORT_MIB_RESETr, &rval, CLR_CNTf, 0x1); 5453 SOC_IF_ERROR_RETURN(WRITE_XLPORT_MIB_RESETr(unit, port, rval)); 5454 SOC_IF_ERROR_RETURN(WRITE_XLPORT_MIB_RESETr(unit, port, 0)); 5455 5456 /* Enable XLPORT */ 5457 rval = 0; 5458 soc_reg_field_set(unit, XLPORT_PORT_ENABLEr, &rval, PORT0f, 1); 5459 soc_reg_field_set(unit, XLPORT_PORT_ENABLEr, &rval, PORT1f, 1); 5460 soc_reg_field_set(unit, XLPORT_PORT_ENABLEr, &rval, PORT2f, 1); 5461 soc_reg_field_set(unit, XLPORT_PORT_ENABLEr, &rval, PORT3f, 1); 5462 SOC_IF_ERROR_RETURN(WRITE_XLPORT_PORT_ENABLEr(unit, port, rval)); 5463 5464 5465 for (i = port; i < port+4; i++) { 5466 si->port_num_lanes[i] = 1; 5467 } 5468 5469 /* Provision buffers for the newly created port */ 5470 for (i = port; i < port+4; i++) { 5471 SOC_IF_ERROR_RETURN 5472 (soc_reg_field32_modify(unit, PORT_MINr, i, PORT_MINf, 8)); 5473 SOC_IF_ERROR_RETURN 5474 (soc_reg_field32_modify(unit, PORT_SHARED_LIMITr, i, 5475 PORT_SHARED_LIMITf, 15576)); 5476 SOC_IF_ERROR_RETURN 5477 (soc_reg_field32_modify(unit, PORT_RESET_OFFSETr, i, 5478 PORT_RESET_OFFSETf, 0)); 5479 SOC_IF_ERROR_RETURN 5480 (soc_reg_field32_modify(unit, EGRMETERINGCONFIGr, i, METER_GRANf, 3)); 5481 SOC_IF_ERROR_RETURN 5482 (soc_reg_field32_modify(unit, EGRMETERINGCONFIGr, i, THRESHOLDf, 0)); 5483 SOC_IF_ERROR_RETURN 5484 (soc_reg_field32_modify(unit, EGRMETERINGCONFIG1r, i, REFRESHf, 156250)); 5485 } 5486 5487 for (i = port+8; i < port+12; i++) { 5488 SOC_IF_ERROR_RETURN 5489 (soc_reg_field32_modify(unit, PORT_MINr, i, PORT_MINf, 8)); 5490 SOC_IF_ERROR_RETURN 5491 (soc_reg_field32_modify(unit, PORT_SHARED_LIMITr, i, 5492 PORT_SHARED_LIMITf, 3200)); 5493 5494 } 5495 for (i = 0; i < 8; i++) { 5496 SOC_IF_ERROR_RETURN(READ_PG_HDRM_LIMITr(unit, port, i, &rval)); 5497 soc_reg_field_set(unit, PG_HDRM_LIMITr, &rval, PG_HDRM_LIMITf, 283); 5498 SOC_IF_ERROR_RETURN(WRITE_PG_HDRM_LIMITr(unit, port, i, rval)); 5499 } 5500 for (i = port+8; i < port+12; i++) { 5501 SOC_IF_ERROR_RETURN 5502 (soc_reg_field32_modify(unit, PORT_WREDCONFIG_CELLr, i, 5503 LB_WEIGHTf, 4)); 5504 SOC_IF_ERROR_RETURN 5505 (soc_reg_field32_modify(unit, PORT_WREDCONFIG_CELLr, i, 5506 LB_ENABLEf, 0)); 5507 } 5508 SOC_IF_ERROR_RETURN 5509 (soc_reg_field32_modify(unit, INPUT_PORT_RX_ENABLEr, REG_PORT_ANY, 5510 INPUT_PORT_RX_ENABLEf, 0x1ffff)); 5511 SOC_IF_ERROR_RETURN 5512 (soc_reg_field32_modify(unit, OUTPUT_PORT_RX_ENABLEr, REG_PORT_ANY, 5513 OUTPUT_PORT_RX_ENABLEf, 0x1ffff)); 5514 5515 /* Clear any transients */ 5516 SOC_IF_ERROR_RETURN(READ_RFRGr(unit, port, &rval64)); 5517 SOC_IF_ERROR_RETURN(READ_RFCSr(unit, port, &rval64)); 5518 SOC_IF_ERROR_RETURN(READ_RERPKTr(unit, port, &rval64)); 5519 SOC_IF_ERROR_RETURN(READ_TPKTr(unit, port, &rval64)); 5520 SOC_IF_ERROR_RETURN(READ_RUCr(unit, port, &rval64)); 5521 SOC_IF_ERROR_RETURN(READ_RDROPr(unit, port, &rval64)); 5522 5523 /* Apply software workaround to clear some FIFO points */ 5524 5525 SOC_IF_ERROR_RETURN 5526 (soc_reg_field32_modify(unit, XLP_TXFIFO_PKT_DROP_CTLr, port, 5527 DROP_ENf, 1)); 5528 SOC_IF_ERROR_RETURN 5529 (soc_reg_field32_modify(unit, XLP_TXFIFO_PKT_DROP_CTLr, port, 5530 DROP_ENf, 0)); 5531 5532 /* Setup Static load balance for Port (one to one mapping) */ 5533 for (p = port; p < port+4; p++) { 5534 SOC_IF_ERROR_RETURN 5535 (soc_reg_field32_modify(unit, UFLOW_PORT_CONTROLr, p, 5536 DEST_PORTf, p+8)); 5537 SOC_IF_ERROR_RETURN 5538 (soc_reg_field32_modify(unit, UFLOW_PORT_CONTROLr, p, 5539 HASH_MODEf, 0)); 5540 SOC_IF_ERROR_RETURN 5541 (soc_reg_field32_modify(unit, UFLOW_PORT_CONTROLr, p+8, 5542 DEST_PORTf, p)); 5543 SOC_IF_ERROR_RETURN 5544 (soc_reg_field32_modify(unit, UFLOW_PORT_CONTROLr, p+8, 5545 HASH_MODEf, 0)); 5546 } 5547 5548 return SOC_E_NONE; 5549 } 5550 5551 5552 /* 5553 * To support dynamic port configurations 5554 */ 5555 int 5556 _bcm_shadow_port_lanes_set(int unit, soc_port_t port, int value) 5557 { 5558 soc_port_t oport; 5559 soc_info_t *si; 5560 int rv = SOC_E_NONE; 5561 5562 si = &SOC_INFO(unit); 5563 5564 if (!SOC_PORT_VALID(unit, port)) { 5565 return SOC_E_PORT; 5566 } 5567 5568 /* Apply to only Front panel, 1 and 5 ports */ 5569 if ((port != 1) && (port != 5)) { 5570 return SOC_E_PORT; 5571 } 5572 5573 if ((value != 1) && (value != 4)) { 5574 return SOC_E_CONFIG; 5575 } 5576 5577 /* Update disabled ports */ 5578 if (value == 4) { /* modified from 1 lane to 4 lanes */ 5579 if (port == 1) { 5580 for (oport = 2; oport <= 4; oport++) { 5581 SOC_PBMP_PORT_ADD(si->ge.disabled_bitmap, oport); 5582 SOC_PBMP_PORT_ADD(si->xe.disabled_bitmap, oport); 5583 SOC_PBMP_PORT_ADD(si->ether.disabled_bitmap, oport); 5584 SOC_PBMP_PORT_ADD(si->port.disabled_bitmap, oport); 5585 SOC_PBMP_PORT_ADD(si->all.disabled_bitmap, oport); 5586 SOC_PBMP_PORT_REMOVE(si->port.bitmap, oport); 5587 si->port_num_lanes[oport] = 1; 5588 } 5589 } 5590 if (port == 5) { 5591 for (oport = 6; oport <= 8; oport++) { 5592 SOC_PBMP_PORT_ADD(si->ge.disabled_bitmap, oport); 5593 SOC_PBMP_PORT_ADD(si->xe.disabled_bitmap, oport); 5594 SOC_PBMP_PORT_ADD(si->ether.disabled_bitmap, oport); 5595 SOC_PBMP_PORT_ADD(si->port.disabled_bitmap, oport); 5596 SOC_PBMP_PORT_ADD(si->all.disabled_bitmap, oport); 5597 SOC_PBMP_PORT_REMOVE(si->port.bitmap, oport); 5598 si->port_num_lanes[oport] = 1; 5599 } 5600 } 5601 si->port_speed_max[port] = 40000; /* new max speed = 40G */ 5602 si->port_num_lanes[port] = 4; /* Quad lane port */ 5603 5604 rv = _bcm_shadow_port_reconfig_40g(unit, port); 5605 } else if (value == 1) { 5606 if (port == 1) { 5607 for (oport = 2; oport <= 4; oport++) { 5608 si->port_speed_max[oport] = 10000; 5609 SOC_PBMP_PORT_ADD(si->port.bitmap, oport); 5610 SOC_PBMP_PORT_REMOVE(si->ge.disabled_bitmap, oport); 5611 SOC_PBMP_PORT_REMOVE(si->xe.disabled_bitmap, oport); 5612 SOC_PBMP_PORT_REMOVE(si->ether.disabled_bitmap, oport); 5613 SOC_PBMP_PORT_REMOVE(si->port.disabled_bitmap, oport); 5614 SOC_PBMP_PORT_REMOVE(si->all.disabled_bitmap, oport); 5615 si->port_num_lanes[oport] = 1; /* Independent lane port */ 5616 } 5617 } 5618 if (port == 5) { 5619 for (oport = 6; oport <= 8; oport++) { 5620 SOC_PBMP_PORT_ADD(si->port.bitmap, oport); 5621 si->port_speed_max[oport] = 10000; 5622 SOC_PBMP_PORT_REMOVE(si->ge.disabled_bitmap, oport); 5623 SOC_PBMP_PORT_REMOVE(si->xe.disabled_bitmap, oport); 5624 SOC_PBMP_PORT_REMOVE(si->ether.disabled_bitmap, oport); 5625 SOC_PBMP_PORT_REMOVE(si->port.disabled_bitmap, oport); 5626 SOC_PBMP_PORT_REMOVE(si->all.disabled_bitmap, oport); 5627 si->port_num_lanes[oport] = 1; /* Independent lane port */ 5628 } 5629 } 5630 si->port_speed_max[port] = 10000; /* new max speed = 40G */ 5631 si->port_num_lanes[port] = 1; /* Single lane port */ 5632 rv = _bcm_shadow_port_reconfig_10g(unit, port); 5633 } 5634 5635 return rv; 5636 } 5637 5638 int 5639 soc_shadow_temperature_monitor_get(int unit, 5640 int temperature_max, 5641 soc_switch_temperature_monitor_t *temperature_array, 5642 int *temperature_count) 5643 { 5644 uint32 rval, addr; 5645 soc_reg_t reg; 5646 int index; 5647 int fval, cur, peak; 5648 int num_entries_out; 5649 5650 *temperature_count = 0; 5651 /* only first 5 monitors are used */ 5652 if (5 > temperature_max) { 5653 num_entries_out = temperature_max; 5654 } else { 5655 num_entries_out = 5; 5656 } 5657 5658 for (index = 0; index < num_entries_out; index++) { 5659 reg = thermal_reg[index]; 5660 addr = soc_reg_addr(unit, reg, REG_PORT_ANY, 0); 5661 soc_pci_getreg(unit, addr, &rval); 5662 fval = soc_reg_field_get(unit, reg, rval, TEMP_DATAf); 5663 cur = (4180000 - (5556 * fval)) / 1000; 5664 fval = soc_reg_field_get(unit, reg, rval, PEAK_TEMP_DATAf); 5665 peak = (4180000 - (5556 * fval)) / 1000; 5666 (temperature_array + index)->curr = cur; 5667 (temperature_array + index)->peak = peak; 5668 } 5669 READ_CMIC_SOFT_RESET_REGr(unit, &rval); 5670 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &rval, 5671 TEMP_MON_PEAK_RESET_Nf, 0); 5672 WRITE_CMIC_SOFT_RESET_REGr(unit, rval); 5673 soc_reg_field_set(unit, CMIC_SOFT_RESET_REGr, &rval, 5674 TEMP_MON_PEAK_RESET_Nf, 1); 5675 WRITE_CMIC_SOFT_RESET_REGr(unit, rval); 5676 *temperature_count=num_entries_out; 5677 5678 return SOC_E_NONE; 5679 5680 } 5681 5682 #endif /* BCM_SHADOW_SUPPORT */