ser.c (307012B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: ser.c 8 * Purpose: SER enable/detect and test functionality. 9 * Requires: sal/soc/shared layer 10 */ 11 12 #include <soc/saber2.h> 13 #include <soc/error.h> 14 #include <soc/debug.h> 15 #include <soc/mem.h> 16 #include <soc/hash.h> 17 #include <shared/bsl.h> 18 #include <soc/soc_ser_log.h> 19 20 #ifdef BCM_SABER2_SUPPORT 21 22 #define _SOC_SABER2_SER_REG 1 23 #define _SOC_SABER2_SER_MEM 0 24 #define _SOC_SABER2_SER_INVALID 0xFF 25 26 #define _SOC_SABER2_SER_FLAG_MASK ( SOC_MEM_FLAG_SER_SPECIAL | SOC_MEM_FLAG_SER_ENGINE | SOC_MEM_FLAG_SER_ENTRY_CLEAR \ 27 | SOC_MEM_FLAG_SER_SRAM_CORRECTION | SOC_MEM_FLAG_SER_CACHE_RESTORE \ 28 | SOC_MEM_FLAG_SER_ECC_CORRECTABLE | SOC_MEM_FLAG_SER_WRITE_CACHE_RESTORE ) 29 30 #define _SOC_SABER2_SAT_CMIC_BIT (1U << 2) 31 32 typedef union _soc_saber2_ser_nack_reg_mem_u { 33 soc_reg_t reg; 34 soc_mem_t mem; 35 } _soc_saber2_ser_nack_reg_mem_t; 36 37 /* ser part */ 38 typedef struct _soc_saber2_fifo_ser_info_s { 39 soc_reg_t enable_reg; 40 soc_field_t enable_field; 41 uint8 type; /* 0: mem, 1: reg, */ 42 soc_mem_t mem; 43 soc_reg_t reg; 44 char *name_str; /* Used when mem == INVALIDm or reg == INVALIDr */ 45 soc_field_t parity_field; /* used to sw inject test */ 46 } _soc_saber2_fifo_ser_info_t; 47 48 typedef struct _soc_td2_ser_block_info_s { 49 soc_block_t blocktype; 50 soc_reg_t fifo_reset_reg; 51 _soc_saber2_fifo_ser_info_t *info; 52 } _soc_saber2_fifo_ser_block_info_t; 53 54 55 typedef enum { 56 _SOC_PARITY_TYPE_NONE, 57 _SOC_PARITY_TYPE_GENERIC, 58 _SOC_PARITY_TYPE_PARITY, 59 _SOC_PARITY_TYPE_ECC, 60 _SOC_PARITY_TYPE_HASH, 61 _SOC_PARITY_TYPE_EDATABUF, 62 _SOC_PARITY_TYPE_COUNTER, 63 _SOC_PARITY_TYPE_SER, 64 _SOC_PARITY_TYPE_OAM 65 } _soc_saber2_parity_info_type_t; 66 67 68 typedef struct _soc_saber2_parity_reg_s { 69 soc_reg_t reg; 70 char *mem_str; 71 } _soc_saber2_parity_reg_t; 72 73 74 typedef struct _soc_saber2_parity_info_s { 75 _soc_saber2_parity_info_type_t type; 76 struct _soc_saber2_parity_info_s *info; 77 int id; 78 soc_field_t group_reg_enable_field; 79 soc_field_t group_reg_status_field; 80 soc_mem_t mem; 81 char *mem_str; 82 soc_reg_t enable_reg; 83 soc_field_t enable_field; 84 soc_reg_t intr_status_reg; 85 _soc_saber2_parity_reg_t *intr_status_reg_list; 86 soc_reg_t nack_status_reg; 87 _soc_saber2_parity_reg_t *nack_status_reg_list; 88 } _soc_saber2_parity_info_t; 89 90 91 typedef struct _soc_saber2_parity_route_block_s { 92 uint32 cmic_bit; 93 soc_block_t blocktype; 94 soc_reg_t enable_reg; 95 soc_reg_t status_reg; 96 soc_field_t enable_field; 97 _soc_saber2_parity_info_t *info; 98 uint8 id; 99 } _soc_saber2_parity_route_block_t; 100 101 102 typedef struct _soc_saber2_skip_mem_reg_s { 103 uint32 regmem; 104 soc_reg_t skip_reg; 105 soc_mem_t skip_mem; 106 } _soc_saber2_skip_mem_reg_t; 107 108 109 /* this enums need to modify. */ 110 typedef enum { 111 _SOC_SABER2_MMU_SUBBLOCK_IPCTR, 112 _SOC_SABER2_MMU_SUBBLOCK_ADM, 113 _SOC_SABER2_MMU_SUBBLOCK_RDE, 114 _SOC_SABER2_MMU_SUBBLOCK_INFO2, 115 _SOC_SABER2_MMU_SUBBLOCK_MEM1, 116 _SOC_SABER2_MMU_SUBBLOCK_INTFI_ECC, 117 _SOC_SABER2_MMU_SUBBLOCK_ITE_CFG, 118 _SOC_SABER2_MMU_SUBBLOCK_THDI, 119 _SOC_SABER2_MMU_SUBBLOCK_ENQ_CFG, 120 _SOC_SABER2_MMU_SUBBLOCK_ENQ_FAP, 121 _SOC_SABER2_MMU_SUBBLOCK_CI1, 122 _SOC_SABER2_MMU_SUBBLOCK_CI0, 123 _SOC_SABER2_MMU_SUBBLOCK_WRED, 124 _SOC_SABER2_MMU_SUBBLOCK_THDO_STATUS1, 125 _SOC_SABER2_MMU_SUBBLOCK_THDO_STATUS2, 126 _SOC_SABER2_MMU_SUBBLOCK_RQE_SER, 127 _SOC_SABER2_MMU_SUBBLOCK_RQE_EXTQ, 128 _SOC_SABER2_MMU_SUBBLOCK_EMC, 129 _SOC_SABER2_MMU_SUBBLOCK_DEQ, 130 _SOC_SABER2_MMU_SUBBLOCK_CTR, 131 _SOC_SABER2_MMU_SUBBLOCK_CFAPI, 132 _SOC_SABER2_MMU_SUBBLOCK_CFAPE, 133 _SOC_SABER2_MMU_SUBBLOCK_CCP, 134 _SOC_SABER2_MMU_SUBBLOCK_AGING_INT, 135 _SOC_SABER2_MMU_SUBBLOCK_AGING_EXT, 136 _SOC_SABER2_MMU_SUBBLOCK_LLS, 137 _SOC_SABER2_MMU_SUBBLOCK_LLS_PORT, 138 _SOC_SABER2_MMU_SUBBLOCK_LLS_L0_ECC, 139 _SOC_SABER2_MMU_SUBBLOCK_LLS_UPD2, 140 _SOC_SABER2_MMU_SUBBLOCK_LLS_L1_ECC, 141 _SOC_SABER2_MMU_SUBBLOCK_LLS_L2_ECC, 142 _SOC_SABER2_MMU_SUBBLOCK_LLS_MISC_ECC, 143 _SOC_SABER2_MMU_SUBBLOCK_QSTRUCT, 144 _SOC_SABER2_MMU_SUBBLOCK_TOQ, 145 _SOC_SABER2_MMU_SUBBLOCK_MAX 146 } _soc_saber2_mmu_subblock_type_t; 147 148 149 /* this enums need to modify. */ 150 typedef enum { 151 _SOC_SABER2_MMU_LVL2_SUBBLOCK_EMC_ERROR_0, 152 _SOC_SABER2_MMU_LVL2_SUBBLOCK_EMC_ERROR_1, 153 _SOC_SABER2_MMU_LVL2_SUBBLOCK_EMC_ERROR_2, 154 _SOC_SABER2_MMU_LVL2_SUBBLOCK_EMC_ERROR_3, 155 _SOC_SABER2_MMU_LVL2_SUBBLOCK_DEQ_ERROR_0, 156 _SOC_SABER2_MMU_LVL2_SUBBLOCK_DEQ_ERROR_1, 157 _SOC_SABER2_MMU_LVL2_SUBBLOCK_DEQ_ERROR_2, 158 _SOC_SABER2_MMU_LVL2_SUBBLOCK_QSTRUCT_QENTRY, 159 _SOC_SABER2_MMU_LVL2_SUBBLOCK_QSTRUCT_QBLOCK, 160 _SOC_SABER2_MMU_LVL2_SUBBLOCK_QSTRUCT_FAP, 161 _SOC_SABER2_MMU_LVL2_SUBBLOCK_TOQ_ERROR_2, 162 _SOC_SABER2_MMU_LVL2_SUBBLOCK_TOQ_ERROR_1, 163 _SOC_SABER2_MMU_LVL2_SUBBLOCK_MAX 164 } _soc_saber2_mmu_lvl2_subblock_type_t; 165 166 167 typedef struct _soc_saber2_mmu_sub_block_leaf_info_s { 168 uint32 intr_bit; /* bit position in intr register of sub block */ 169 soc_mem_t mem; 170 char *mem_str; 171 soc_field_t status_field; /* INTR field of a leaf block */ 172 soc_field_t enable_field; /* MASK field of a leaf block */ 173 soc_field_t mem_parity_field; /* used to sw inject test */ 174 soc_mem_t mem_parity_enable_reg; /* mem parity enable reg */ 175 soc_field_t mem_parity_enable_field; /* mem parity enable field */ 176 soc_mem_t mem_ecc_address_reg; /* get memory entry id for correction */ 177 soc_field_t mem_ecc_address_field; /* get memory entry id for correction */ 178 } _soc_saber2_mmu_sub_block_leaf_info_t; 179 180 181 typedef struct _soc_saber2_mmu_sub_block_internal_info_s { 182 uint32 intr_bit; /* bit position in level 1 sub block INTR and INTR_MASK */ 183 _soc_saber2_mmu_lvl2_subblock_type_t lvl2_sub_block; /* level 2 sub block */ 184 soc_field_t internal_enable_field; /* field in 1evel 1 sub block INTR MASK register */ 185 soc_field_t internal_status_field; /* field in level 1 sub block INTR register */ 186 soc_reg_t leaf_enable_reg; /* intr mask register for level 2 sub block */ 187 soc_reg_t leaf_status_reg; /* intr register for level 2 sub block */ 188 _soc_saber2_mmu_sub_block_leaf_info_t *info; 189 } _soc_saber2_mmu_sub_block_internal_info_t; 190 191 192 typedef struct _soc_saber2_mmu_sub_block_one_level_s { 193 uint32 mmu_bit; /* bit position in MMU_INTR and MMU_INTR_MASK */ 194 _soc_saber2_mmu_subblock_type_t mmu_sub_block; /* level 1 sub block */ 195 soc_field_t mmu_intr_mask_field; /* field in MMU_INTR_MASK */ 196 soc_field_t mmu_intr_status_field; /* field in MMU_INTR */ 197 soc_reg_t intr_mask_reg; /* intr mask register for sub block */ 198 soc_reg_t lntr_status_reg; /* intr register for sub block */ 199 _soc_saber2_mmu_sub_block_leaf_info_t *info; /* list of memory instances */ 200 } _soc_saber2_mmu_sub_block_one_level_t; 201 202 203 typedef struct _soc_saber2_mmu_sub_block_two_level_s { 204 uint32 mmu_bit; /* bit position in MMU_INTR and MMU_INTR_MASK */ 205 _soc_saber2_mmu_subblock_type_t mmu_sub_block; /* level 1 sub block */ 206 soc_field_t mmu_enable_field; /* field in MMU_INTR_MASK */ 207 soc_field_t mmu_status_field; /* field in MMU_INTR */ 208 soc_reg_t internal_enable_reg; /* intr mask for sub block */ 209 soc_reg_t internal_status_reg; /* intr for sub block */ 210 _soc_saber2_mmu_sub_block_internal_info_t *info; 211 } _soc_saber2_mmu_sub_block_two_level_t; 212 213 214 STATIC 215 _soc_saber2_mmu_sub_block_leaf_info_t _soc_saber2_mmu_sb_lls_l0_parity_info[] = { 216 217 /* LLS_L0_ECC_ERROR1 */ 218 { 0x00000001, LLS_L0_SHAPER_BUCKET_Cm, "", 219 DB_L0_SHAPER_BUCKET_C_UNCORRECTED_ERRORf, 220 DB_L0_SHAPER_BUCKET_C_UNCORRECTED_ERROR_DISINTf, 221 ECCf, LLS_L0_ECC_DEBUGr, DB_L0_SHAPER_BUCKET_C_ENABLE_ECCf, 222 LLS_L0_SHAPER_BUCKET_C_ECC_STATUSr, DB_L0_SHAPER_BUCKET_C_ECC_ERROR_ADDRESSf}, 223 { 0x00000002, LLS_L0_SHAPER_BUCKET_Cm, "", 224 DB_L0_SHAPER_BUCKET_C_CORRECTED_ERRORf, 225 DB_L0_SHAPER_BUCKET_C_CORRECTED_ERROR_DISINTf, 226 PARITYf, LLS_L0_ECC_DEBUGr, DB_L0_SHAPER_BUCKET_C_ENABLE_ECCf, 227 LLS_L0_SHAPER_BUCKET_C_ECC_STATUSr, DB_L0_SHAPER_BUCKET_C_ECC_ERROR_ADDRESSf}, 228 229 { 0x00000004, LLS_L0_EF_NEXTm, "", 230 DB_L0_EF_NEXT_UNCORRECTED_ERRORf, 231 DB_L0_EF_NEXT_UNCORRECTED_ERROR_DISINTf, 232 ECCf, LLS_L0_ECC_DEBUGr, DB_L0_EF_NEXT_ENABLE_ECCf, 233 LLS_L0_EF_NEXT_ECC_STATUSr, DB_L0_EF_NEXT_ECC_ERROR_ADDRESSf}, 234 { 0x00000008, LLS_L0_EF_NEXTm, "", 235 DB_L0_EF_NEXT_CORRECTED_ERRORf, 236 DB_L0_EF_NEXT_CORRECTED_ERROR_DISINTf, 237 PARITYf, LLS_L0_ECC_DEBUGr, DB_L0_EF_NEXT_ENABLE_ECCf, 238 LLS_L0_EF_NEXT_ECC_STATUSr, DB_L0_EF_NEXT_ECC_ERROR_ADDRESSf}, 239 240 { 0x00000010, LLS_L0_WERR_NEXTm, "", 241 DB_L0_WERR_NEXT_UNCORRECTED_ERRORf, 242 DB_L0_WERR_NEXT_UNCORRECTED_ERROR_DISINTf, 243 ECCf, LLS_L0_ECC_DEBUGr, DB_L0_WERR_NEXT_ENABLE_ECCf, 244 LLS_L0_WERR_NEXT_ECC_STATUSr, DB_L0_WERR_NEXT_ECC_ERROR_ADDRESSf}, 245 { 0x00000020, LLS_L0_WERR_NEXTm, "", 246 DB_L0_WERR_NEXT_CORRECTED_ERRORf, 247 DB_L0_WERR_NEXT_CORRECTED_ERROR_DISINTf, 248 PARITYf, LLS_L0_ECC_DEBUGr, DB_L0_WERR_NEXT_ENABLE_ECCf, 249 LLS_L0_WERR_NEXT_ECC_STATUSr, DB_L0_WERR_NEXT_ECC_ERROR_ADDRESSf}, 250 251 { 0x00000040, LLS_L0_CHILD_WEIGHT_CFG_CNTm, "", 252 DB_L0_CHILD_WEIGHT_CFG_CNT_UNCORRECTED_ERRORf, 253 DB_L0_CHILD_WEIGHT_CFG_CNT_UNCORRECTED_ERROR_DISINTf, 254 ECCf, LLS_L0_ECC_DEBUGr, DB_L0_CHILD_WEIGHT_CFG_CNT_ENABLE_ECCf, 255 LLS_L0_CHILD_WEIGHT_CFG_CNT_ECC_STATUSr, DB_L0_CHILD_WEIGHT_CFG_CNT_ECC_ERROR_ADDRESSf}, 256 { 0x00000080, LLS_L0_CHILD_WEIGHT_CFG_CNTm, "", 257 DB_L0_CHILD_WEIGHT_CFG_CNT_CORRECTED_ERRORf, 258 DB_L0_CHILD_WEIGHT_CFG_CNT_CORRECTED_ERROR_DISINTf, 259 PARITYf, LLS_L0_ECC_DEBUGr, DB_L0_CHILD_WEIGHT_CFG_CNT_ENABLE_ECCf, 260 LLS_L0_CHILD_WEIGHT_CFG_CNT_ECC_STATUSr, DB_L0_CHILD_WEIGHT_CFG_CNT_ECC_ERROR_ADDRESSf}, 261 262 { 0x00000100, LLS_L0_CHILD_STATE1m, "", 263 DB_L0_CHILD_STATE1_UNCORRECTED_ERRORf, 264 DB_L0_CHILD_STATE1_UNCORRECTED_ERROR_DISINTf, 265 ECCf, LLS_L0_ECC_DEBUGr, DB_L0_CHILD_STATE1_ENABLE_ECCf, 266 LLS_L0_CHILD_STATE1_ECC_STATUSr, DB_L0_CHILD_STATE1_ECC_ERROR_ADDRESSf}, 267 { 0x00000200, LLS_L0_CHILD_STATE1m, "", 268 DB_L0_CHILD_STATE1_CORRECTED_ERRORf, 269 DB_L0_CHILD_STATE1_CORRECTED_ERROR_DISINTf, 270 PARITYf, LLS_L0_ECC_DEBUGr, DB_L0_CHILD_STATE1_ENABLE_ECCf, 271 LLS_L0_CHILD_STATE1_ECC_STATUSr, DB_L0_CHILD_STATE1_ECC_ERROR_ADDRESSf}, 272 273 { 0x00000400, LLS_L0_MIN_BUCKET_Cm, "", 274 DB_L0_MIN_BUCKET_C_UNCORRECTED_ERRORf, 275 DB_L0_MIN_BUCKET_C_UNCORRECTED_ERROR_DISINTf, 276 ECCf, LLS_L0_ECC_DEBUGr, DB_L0_MIN_BUCKET_C_ENABLE_ECCf, 277 LLS_L0_MIN_BUCKET_C_ECC_STATUSr, DB_L0_MIN_BUCKET_C_ECC_ERROR_ADDRESSf}, 278 { 0x00000800, LLS_L0_MIN_BUCKET_Cm, "", 279 DB_L0_MIN_BUCKET_C_CORRECTED_ERRORf, 280 DB_L0_MIN_BUCKET_C_CORRECTED_ERROR_DISINTf, 281 PARITYf, LLS_L0_ECC_DEBUGr, DB_L0_MIN_BUCKET_C_ENABLE_ECCf, 282 LLS_L0_MIN_BUCKET_C_ECC_STATUSr, DB_L0_MIN_BUCKET_C_ECC_ERROR_ADDRESSf}, 283 284 { 0x00001000, LLS_L0_WERR_MAX_SCm, "", 285 DB_L0_WERR_MAX_SC_UNCORRECTED_ERRORf, 286 DB_L0_WERR_MAX_SC_UNCORRECTED_ERROR_DISINTf, 287 ECCf, LLS_L0_ECC_DEBUGr, DB_L0_WERR_MAX_SC_ENABLE_ECCf, 288 LLS_L0_WERR_MAX_SC_ECC_STATUSr, DB_L0_WERR_MAX_SC_ECC_ERROR_ADDRESSf}, 289 { 0x00002000, LLS_L0_WERR_MAX_SCm, "", 290 DB_L0_WERR_MAX_SC_CORRECTED_ERRORf, 291 DB_L0_WERR_MAX_SC_CORRECTED_ERROR_DISINTf, 292 PARITYf, LLS_L0_ECC_DEBUGr, DB_L0_WERR_MAX_SC_ENABLE_ECCf, 293 LLS_L0_WERR_MAX_SC_ECC_STATUSr, DB_L0_WERR_MAX_SC_ECC_ERROR_ADDRESSf}, 294 295 { 0x00004000, LLS_L0_HEADS_TAILSm, "", 296 DB_L0_HEADS_TAILS_UNCORRECTED_ERRORf, 297 DB_L0_HEADS_TAILS_UNCORRECTED_ERROR_DISINTf, 298 ECCf, LLS_L0_ECC_DEBUGr, DB_L0_HEADS_TAILS_ENABLE_ECCf, 299 LLS_L0_HEADS_TAILS_ECC_STATUSr, DB_L0_HEADS_TAILS_ECC_ERROR_ADDRESSf}, 300 { 0x00008000, LLS_L0_HEADS_TAILSm, "", 301 DB_L0_HEADS_TAILS_CORRECTED_ERRORf, 302 DB_L0_HEADS_TAILS_CORRECTED_ERROR_DISINTf, 303 PARITYf, LLS_L0_ECC_DEBUGr, DB_L0_HEADS_TAILS_ENABLE_ECCf, 304 LLS_L0_HEADS_TAILS_ECC_STATUSr, DB_L0_HEADS_TAILS_ECC_ERROR_ADDRESSf}, 305 306 { 0x00010000, LLS_L0_PARENT_STATEm, "", 307 DB_L0_PARENT_STATE_UNCORRECTED_ERRORf, 308 DB_L0_PARENT_STATE_UNCORRECTED_ERROR_DISINTf, 309 ECCf, LLS_L0_ECC_DEBUGr, DB_L0_PARENT_STATE_ENABLE_ECCf, 310 LLS_L0_PARENT_STATE_ECC_STATUSr, DB_L0_PARENT_STATE_ECC_ERROR_ADDRESSf}, 311 { 0x00020000, LLS_L0_PARENT_STATEm, "", 312 DB_L0_PARENT_STATE_CORRECTED_ERRORf, 313 DB_L0_PARENT_STATE_CORRECTED_ERROR_DISINTf, 314 PARITYf, LLS_L0_ECC_DEBUGr, DB_L0_PARENT_STATE_ENABLE_ECCf, 315 LLS_L0_PARENT_STATE_ECC_STATUSr, DB_L0_PARENT_STATE_ECC_ERROR_ADDRESSf}, 316 317 { 0x00040000, LLS_L0_MIN_CONFIG_Cm, "", 318 DB_L0_MIN_CONFIG_C_UNCORRECTED_ERRORf, 319 DB_L0_MIN_CONFIG_C_UNCORRECTED_ERROR_DISINTf, 320 ECCf, LLS_L0_ECC_DEBUG1r, DB_L0_MIN_CONFIG_C_ENABLE_ECCf, 321 LLS_L0_MIN_CONFIG_C_ECC_STATUSr, DB_L0_MIN_CONFIG_C_ECC_ERROR_ADDRESSf}, 322 { 0x00080000, LLS_L0_MIN_CONFIG_Cm, "", 323 DB_L0_MIN_CONFIG_C_CORRECTED_ERRORf, 324 DB_L0_MIN_CONFIG_C_CORRECTED_ERROR_DISINTf, 325 PARITYf, LLS_L0_ECC_DEBUG1r, DB_L0_MIN_CONFIG_C_ENABLE_ECCf, 326 LLS_L0_MIN_CONFIG_C_ECC_STATUSr, DB_L0_MIN_CONFIG_C_ECC_ERROR_ADDRESSf}, 327 328 { 0x00100000, LLS_L0_CONFIGm, "", 329 DB_L0_CONFIG_UNCORRECTED_ERRORf, 330 DB_L0_CONFIG_UNCORRECTED_ERROR_DISINTf, 331 ECCf, LLS_L0_ECC_DEBUGr, DB_L0_CONFIG_ENABLE_ECCf, 332 LLS_L0_CONFIG_ECC_STATUSr, DB_L0_CONFIG_ECC_ERROR_ADDRESSf}, 333 { 0x00200000, LLS_L0_CONFIGm, "", 334 DB_L0_CONFIG_CORRECTED_ERRORf, 335 DB_L0_CONFIG_CORRECTED_ERROR_DISINTf, 336 PARITYf, LLS_L0_ECC_DEBUGr, DB_L0_CONFIG_ENABLE_ECCf, 337 LLS_L0_CONFIG_ECC_STATUSr, DB_L0_CONFIG_ECC_ERROR_ADDRESSf}, 338 339 { 0x00400000, LLS_L0_PARENTm, "", 340 DB_L0_PARENT_UNCORRECTED_ERRORf, 341 DB_L0_PARENT_UNCORRECTED_ERROR_DISINTf, 342 ECCf, LLS_L0_ECC_DEBUGr, DB_L0_PARENT_ENABLE_ECCf, 343 LLS_L0_PARENT_ECC_STATUSr, DB_L0_PARENT_ECC_ERROR_ADDRESSf}, 344 { 0x00800000, LLS_L0_PARENTm, "", 345 DB_L0_PARENT_CORRECTED_ERRORf, 346 DB_L0_PARENT_CORRECTED_ERROR_DISINTf, 347 PARITYf, LLS_L0_ECC_DEBUGr, DB_L0_PARENT_ENABLE_ECCf, 348 LLS_L0_PARENT_ECC_STATUSr, DB_L0_PARENT_ECC_ERROR_ADDRESSf}, 349 350 { 0x01000000, LLS_L0_MIN_NEXTm, "", 351 DB_L0_MIN_NEXT_UNCORRECTED_ERRORf, 352 DB_L0_MIN_NEXT_UNCORRECTED_ERROR_DISINTf, 353 ECCf, LLS_L0_ECC_DEBUGr, DB_L0_MIN_NEXT_ENABLE_ECCf, 354 LLS_L0_MIN_NEXT_ECC_STATUSr, DB_L0_MIN_NEXT_ECC_ERROR_ADDRESSf}, 355 { 0x02000000, LLS_L0_MIN_NEXTm, "", 356 DB_L0_MIN_NEXT_CORRECTED_ERRORf, 357 DB_L0_MIN_NEXT_CORRECTED_ERROR_DISINTf, 358 PARITYf, LLS_L0_ECC_DEBUGr, DB_L0_MIN_NEXT_ENABLE_ECCf, 359 LLS_L0_MIN_NEXT_ECC_STATUSr, DB_L0_MIN_NEXT_ECC_ERROR_ADDRESSf}, 360 361 { 0x04000000, LLS_L0_SHAPER_CONFIG_Cm, "", 362 DB_L0_SHAPER_CONFIG_C_UNCORRECTED_ERRORf, 363 DB_L0_SHAPER_CONFIG_C_UNCORRECTED_ERROR_DISINTf, 364 ECCf, LLS_L0_ECC_DEBUG1r, DB_L0_SHAPER_CONFIG_C_ENABLE_ECCf, 365 LLS_L0_SHAPER_CONFIG_C_ECC_STATUSr, DB_L0_SHAPER_CONFIG_C_ECC_ERROR_ADDRESSf}, 366 { 0x08000000, LLS_L0_SHAPER_CONFIG_Cm, "", 367 DB_L0_SHAPER_CONFIG_C_CORRECTED_ERRORf, 368 DB_L0_SHAPER_CONFIG_C_CORRECTED_ERROR_DISINTf, 369 PARITYf, LLS_L0_ECC_DEBUG1r, DB_L0_SHAPER_CONFIG_C_ENABLE_ECCf, 370 LLS_L0_SHAPER_CONFIG_C_ECC_STATUSr, DB_L0_SHAPER_CONFIG_C_ECC_ERROR_ADDRESSf}, 371 372 { 0 } /* table terminator */ 373 374 }; 375 376 STATIC 377 _soc_saber2_mmu_sub_block_leaf_info_t _soc_saber2_mmu_sb_lls_l1_parity_info[] = { 378 /* LLS_L1_ECC_ERROR1 */ 379 { 0x00000001, LLS_L1_SHAPER_BUCKET_Cm, "", 380 DB_L1_SHAPER_BUCKET_C_UNCORRECTED_ERRORf, 381 DB_L1_SHAPER_BUCKET_C_UNCORRECTED_ERROR_DISINTf, 382 ECCf, LLS_L1_ECC_DEBUG1Ar, DB_L1_SHAPER_BUCKET_C_ENABLE_ECCf, 383 LLS_L1_SHAPER_BUCKET_C_ECC_STATUSr, DB_L1_SHAPER_BUCKET_C_ECC_ERROR_ADDRESSf}, 384 { 0x00000002, LLS_L1_SHAPER_BUCKET_Cm, "", 385 DB_L1_SHAPER_BUCKET_C_CORRECTED_ERRORf, 386 DB_L1_SHAPER_BUCKET_C_CORRECTED_ERROR_DISINTf, 387 PARITYf, LLS_L1_ECC_DEBUG1Ar, DB_L1_SHAPER_BUCKET_C_ENABLE_ECCf, 388 LLS_L1_SHAPER_BUCKET_C_ECC_STATUSr, DB_L1_SHAPER_BUCKET_C_ECC_ERROR_ADDRESSf}, 389 390 { 0x00000004, LLS_L1_EF_NEXTm, "", 391 DB_L1_EF_NEXT_UNCORRECTED_ERRORf, 392 DB_L1_EF_NEXT_UNCORRECTED_ERROR_DISINTf, 393 ECCf, LLS_L1_ECC_DEBUG1Ar, DB_L1_EF_NEXT_ENABLE_ECCf, 394 LLS_L1_EF_NEXT_ECC_STATUSr, DB_L1_EF_NEXT_ECC_ERROR_ADDRESSf}, 395 { 0x00000008, LLS_L1_EF_NEXTm, "", 396 DB_L1_EF_NEXT_CORRECTED_ERRORf, 397 DB_L1_EF_NEXT_CORRECTED_ERROR_DISINTf, 398 PARITYf, LLS_L1_ECC_DEBUG1Ar, DB_L1_EF_NEXT_ENABLE_ECCf, 399 LLS_L1_EF_NEXT_ECC_STATUSr, DB_L1_EF_NEXT_ECC_ERROR_ADDRESSf}, 400 401 { 0x00000010, LLS_L1_WERR_NEXTm, "", 402 DB_L1_WERR_NEXT_UNCORRECTED_ERRORf, 403 DB_L1_WERR_NEXT_UNCORRECTED_ERROR_DISINTf, 404 ECCf, LLS_L1_ECC_DEBUG1Ar, DB_L1_WERR_NEXT_ENABLE_ECCf, 405 LLS_L1_WERR_NEXT_ECC_STATUSr, DB_L1_WERR_NEXT_ECC_ERROR_ADDRESSf}, 406 { 0x00000020, LLS_L1_WERR_NEXTm, "", 407 DB_L1_WERR_NEXT_CORRECTED_ERRORf, 408 DB_L1_WERR_NEXT_CORRECTED_ERROR_DISINTf, 409 PARITYf, LLS_L1_ECC_DEBUG1Ar, DB_L1_WERR_NEXT_ENABLE_ECCf, 410 LLS_L1_WERR_NEXT_ECC_STATUSr, DB_L1_WERR_NEXT_ECC_ERROR_ADDRESSf}, 411 412 { 0x00000040, LLS_L1_CHILD_WEIGHT_CFG_CNTm, "", 413 DB_L1_CHILD_WEIGHT_CFG_CNT_UNCORRECTED_ERRORf, 414 DB_L1_CHILD_WEIGHT_CFG_CNT_UNCORRECTED_ERROR_DISINTf, 415 ECCf, LLS_L1_ECC_DEBUG1Ar, DB_L1_CHILD_WEIGHT_CFG_CNT_ENABLE_ECCf, 416 LLS_L1_CHILD_WEIGHT_CFG_CNT_ECC_STATUSr, DB_L1_CHILD_WEIGHT_CFG_CNT_ECC_ERROR_ADDRESSf}, 417 { 0x00000080, LLS_L1_CHILD_WEIGHT_CFG_CNTm, "", 418 DB_L1_CHILD_WEIGHT_CFG_CNT_CORRECTED_ERRORf, 419 DB_L1_CHILD_WEIGHT_CFG_CNT_CORRECTED_ERROR_DISINTf, 420 PARITYf, LLS_L1_ECC_DEBUG1Ar, DB_L1_CHILD_WEIGHT_CFG_CNT_ENABLE_ECCf, 421 LLS_L1_CHILD_WEIGHT_CFG_CNT_ECC_STATUSr, DB_L1_CHILD_WEIGHT_CFG_CNT_ECC_ERROR_ADDRESSf}, 422 423 { 0x00000100, LLS_L1_CHILD_STATE1m, "", 424 DB_L1_CHILD_STATE1_UNCORRECTED_ERRORf, 425 DB_L1_CHILD_STATE1_UNCORRECTED_ERROR_DISINTf, 426 ECCf, LLS_L1_ECC_DEBUG1Ar, DB_L1_CHILD_STATE1_ENABLE_ECCf, 427 LLS_L1_CHILD_STATE1_ECC_STATUSr, DB_L1_CHILD_STATE1_ECC_ERROR_ADDRESSf}, 428 { 0x00000200, LLS_L1_CHILD_STATE1m, "", 429 DB_L1_CHILD_STATE1_CORRECTED_ERRORf, 430 DB_L1_CHILD_STATE1_CORRECTED_ERROR_DISINTf, 431 PARITYf, LLS_L1_ECC_DEBUG1Ar, DB_L1_CHILD_STATE1_ENABLE_ECCf, 432 LLS_L1_CHILD_STATE1_ECC_STATUSr, DB_L1_CHILD_STATE1_ECC_ERROR_ADDRESSf}, 433 434 { 0x00000400, LLS_L1_MIN_BUCKET_Cm, "", 435 DB_L1_MIN_BUCKET_C_UNCORRECTED_ERRORf, 436 DB_L1_MIN_BUCKET_C_UNCORRECTED_ERROR_DISINTf, 437 ECCf, LLS_L1_ECC_DEBUG1Ar, DB_L1_MIN_BUCKET_C_ENABLE_ECCf, 438 LLS_L1_MIN_BUCKET_C_ECC_STATUSr, DB_L1_MIN_BUCKET_C_ECC_ERROR_ADDRESSf}, 439 { 0x00000800, LLS_L1_MIN_BUCKET_Cm, "", 440 DB_L1_MIN_BUCKET_C_CORRECTED_ERRORf, 441 DB_L1_MIN_BUCKET_C_CORRECTED_ERROR_DISINTf, 442 PARITYf, LLS_L1_ECC_DEBUG1Ar, DB_L1_MIN_BUCKET_C_ENABLE_ECCf, 443 LLS_L1_MIN_BUCKET_C_ECC_STATUSr, DB_L1_MIN_BUCKET_C_ECC_ERROR_ADDRESSf}, 444 445 { 0x00001000, LLS_L1_WERR_MAX_SCm, "", 446 DB_L1_WERR_MAX_SC_UNCORRECTED_ERRORf, 447 DB_L1_WERR_MAX_SC_UNCORRECTED_ERROR_DISINTf, 448 ECCf, LLS_L1_ECC_DEBUG1Ar, DB_L1_WERR_MAX_SC_ENABLE_ECCf, 449 LLS_L1_WERR_MAX_SC_ECC_STATUSr, DB_L1_WERR_MAX_SC_ECC_ERROR_ADDRESSf}, 450 { 0x00002000, LLS_L1_WERR_MAX_SCm, "", 451 DB_L1_WERR_MAX_SC_CORRECTED_ERRORf, 452 DB_L1_WERR_MAX_SC_CORRECTED_ERROR_DISINTf, 453 PARITYf, LLS_L1_ECC_DEBUG1Ar, DB_L1_WERR_MAX_SC_ENABLE_ECCf, 454 LLS_L1_WERR_MAX_SC_ECC_STATUSr, DB_L1_WERR_MAX_SC_ECC_ERROR_ADDRESSf}, 455 456 { 0x00004000, LLS_L1_HEADS_TAILSm, "", 457 DB_L1_HEADS_TAILS_UNCORRECTED_ERRORf, 458 DB_L1_HEADS_TAILS_UNCORRECTED_ERROR_DISINTf, 459 ECCf, LLS_L1_ECC_DEBUG1Ar, DB_L1_HEADS_TAILS_ENABLE_ECCf, 460 LLS_L1_HEADS_TAILS_ECC_STATUSr, DB_L1_HEADS_TAILS_ECC_ERROR_ADDRESSf}, 461 { 0x00008000, LLS_L1_HEADS_TAILSm, "", 462 DB_L1_HEADS_TAILS_CORRECTED_ERRORf, 463 DB_L1_HEADS_TAILS_CORRECTED_ERROR_DISINTf, 464 PARITYf, LLS_L1_ECC_DEBUG1Ar, DB_L1_HEADS_TAILS_ENABLE_ECCf, 465 LLS_L1_HEADS_TAILS_ECC_STATUSr, DB_L1_HEADS_TAILS_ECC_ERROR_ADDRESSf}, 466 467 { 0x00010000, LLS_L1_PARENT_STATEm, "", 468 DB_L1_PARENT_STATE_UNCORRECTED_ERRORf, 469 DB_L1_PARENT_STATE_UNCORRECTED_ERROR_DISINTf, 470 ECCf, LLS_L1_ECC_DEBUG1Ar, DB_L1_PARENT_STATE_ENABLE_ECCf, 471 LLS_L1_PARENT_STATE_ECC_STATUSr, DB_L1_PARENT_STATE_ECC_ERROR_ADDRESSf}, 472 { 0x00020000, LLS_L1_PARENT_STATEm, "", 473 DB_L1_PARENT_STATE_CORRECTED_ERRORf, 474 DB_L1_PARENT_STATE_CORRECTED_ERROR_DISINTf, 475 PARITYf, LLS_L1_ECC_DEBUG1Ar, DB_L1_PARENT_STATE_ENABLE_ECCf, 476 LLS_L1_PARENT_STATE_ECC_STATUSr, DB_L1_PARENT_STATE_ECC_ERROR_ADDRESSf}, 477 478 { 0x00040000, LLS_L1_MIN_CONFIG_Cm, "", 479 DB_L1_MIN_CONFIG_C_UNCORRECTED_ERRORf, 480 DB_L1_MIN_CONFIG_C_UNCORRECTED_ERROR_DISINTf, 481 ECCf, LLS_L1_ECC_DEBUG1Ar, DB_L1_MIN_CONFIG_C_ENABLE_ECCf, 482 LLS_L1_MIN_CONFIG_C_ECC_STATUSr, DB_L1_MIN_CONFIG_C_ECC_ERROR_ADDRESSf}, 483 { 0x00080000, LLS_L1_MIN_CONFIG_Cm, "", 484 DB_L1_MIN_CONFIG_C_CORRECTED_ERRORf, 485 DB_L1_MIN_CONFIG_C_CORRECTED_ERROR_DISINTf, 486 PARITYf, LLS_L1_ECC_DEBUG1Ar, DB_L1_MIN_CONFIG_C_ENABLE_ECCf, 487 LLS_L1_MIN_CONFIG_C_ECC_STATUSr, DB_L1_MIN_CONFIG_C_ECC_ERROR_ADDRESSf}, 488 489 { 0x00100000, LLS_L1_CONFIGm, "", 490 DB_L1_CONFIG_UNCORRECTED_ERRORf, 491 DB_L1_CONFIG_UNCORRECTED_ERROR_DISINTf, 492 ECCf, LLS_L1_ECC_DEBUG1r, DB_L1_CONFIG_ENABLE_ECCf, 493 LLS_L1_CONFIG_ECC_STATUSr, DB_L1_CONFIG_ECC_ERROR_ADDRESSf}, 494 { 0x00200000, LLS_L1_CONFIGm, "", 495 DB_L1_CONFIG_CORRECTED_ERRORf, 496 DB_L1_CONFIG_CORRECTED_ERROR_DISINTf, 497 PARITYf, LLS_L1_ECC_DEBUG1r, DB_L1_CONFIG_ENABLE_ECCf, 498 LLS_L1_CONFIG_ECC_STATUSr, DB_L1_CONFIG_ECC_ERROR_ADDRESSf}, 499 500 { 0x00400000, LLS_L1_PARENTm, "", 501 DB_L1_PARENT_UNCORRECTED_ERRORf, 502 DB_L1_PARENT_UNCORRECTED_ERROR_DISINTf, 503 ECCf, LLS_L1_ECC_DEBUG1r, DB_L1_PARENT_ENABLE_ECCf, 504 LLS_L1_PARENT_ECC_STATUSr, DB_L1_PARENT_ECC_ERROR_ADDRESSf}, 505 { 0x00800000, LLS_L1_PARENTm, "", 506 DB_L1_PARENT_CORRECTED_ERRORf, 507 DB_L1_PARENT_CORRECTED_ERROR_DISINTf, 508 PARITYf, LLS_L1_ECC_DEBUG1r, DB_L1_PARENT_ENABLE_ECCf, 509 LLS_L1_PARENT_ECC_STATUSr, DB_L1_PARENT_ECC_ERROR_ADDRESSf}, 510 511 { 0x01000000, LLS_L1_MIN_NEXTm, "", 512 DB_L1_MIN_NEXT_UNCORRECTED_ERRORf, 513 DB_L1_MIN_NEXT_UNCORRECTED_ERROR_DISINTf, 514 ECCf, LLS_L1_ECC_DEBUG1r, DB_L1_MIN_NEXT_ENABLE_ECCf, 515 LLS_L1_MIN_NEXT_ECC_STATUSr, DB_L1_MIN_NEXT_ECC_ERROR_ADDRESSf}, 516 { 0x02000000, LLS_L1_MIN_NEXTm, "", 517 DB_L1_MIN_NEXT_CORRECTED_ERRORf, 518 DB_L1_MIN_NEXT_CORRECTED_ERROR_DISINTf, 519 PARITYf, LLS_L1_ECC_DEBUG1r, DB_L1_MIN_NEXT_ENABLE_ECCf, 520 LLS_L1_MIN_NEXT_ECC_STATUSr, DB_L1_MIN_NEXT_ECC_ERROR_ADDRESSf}, 521 522 { 0x04000000, LLS_L1_SHAPER_CONFIG_Cm, "", 523 DB_L1_SHAPER_CONFIG_C_UNCORRECTED_ERRORf, 524 DB_L1_SHAPER_CONFIG_C_UNCORRECTED_ERROR_DISINTf, 525 ECCf, LLS_L1_ECC_DEBUG1r, DB_L1_SHAPER_CONFIG_C_ENABLE_ECCf, 526 LLS_L1_SHAPER_CONFIG_C_ECC_STATUSr, DB_L1_SHAPER_CONFIG_C_ECC_ERROR_ADDRESSf}, 527 { 0x08000000, LLS_L1_SHAPER_CONFIG_Cm, "", 528 DB_L1_SHAPER_CONFIG_C_CORRECTED_ERRORf, 529 DB_L1_SHAPER_CONFIG_C_CORRECTED_ERROR_DISINTf, 530 PARITYf, LLS_L1_ECC_DEBUG1r, DB_L1_SHAPER_CONFIG_C_ENABLE_ECCf, 531 LLS_L1_SHAPER_CONFIG_C_ECC_STATUSr, DB_L1_SHAPER_CONFIG_C_ECC_ERROR_ADDRESSf}, 532 533 { 0 } /* table terminator */ 534 535 }; 536 537 STATIC 538 _soc_saber2_mmu_sub_block_leaf_info_t _soc_saber2_mmu_sb_lls_l2_parity_info[] = { 539 /* LLS_L2_ECC_ERROR1 */ 540 { 0x00000001, LLS_L2_MIN_NEXTm, "", 541 DB_L2_MIN_NEXT_UNCORRECTED_ERRORf, 542 DB_L2_MIN_NEXT_UNCORRECTED_ERROR_DISINTf, 543 ECCf, LLS_L2_ECC_DEBUG1r, DB_L2_MIN_NEXT_ENABLE_ECCf, 544 LLS_L2_MIN_NEXT_ECC_STATUSr, DB_L2_MIN_NEXT_ECC_ERROR_ADDRESSf}, 545 { 0x00000002, LLS_L2_MIN_NEXTm, "", 546 DB_L2_MIN_NEXT_CORRECTED_ERRORf, 547 DB_L2_MIN_NEXT_CORRECTED_ERROR_DISINTf, 548 PARITYf, LLS_L2_ECC_DEBUG1r, DB_L2_MIN_NEXT_ENABLE_ECCf, 549 LLS_L2_MIN_NEXT_ECC_STATUSr, DB_L2_MIN_NEXT_ECC_ERROR_ADDRESSf}, 550 551 { 0x00000004, LLS_L2_WERR_NEXTm, "", 552 DB_L2_WERR_NEXT_UNCORRECTED_ERRORf, 553 DB_L2_WERR_NEXT_UNCORRECTED_ERROR_DISINTf, 554 ECCf, LLS_L2_ECC_DEBUG1r, DB_L2_WERR_NEXT_ENABLE_ECCf, 555 LLS_L2_WERR_NEXT_ECC_STATUSr, DB_L2_WERR_NEXT_ECC_ERROR_ADDRESSf}, 556 { 0x00000008, LLS_L2_WERR_NEXTm, "", 557 DB_L2_WERR_NEXT_CORRECTED_ERRORf, 558 DB_L2_WERR_NEXT_CORRECTED_ERROR_DISINTf, 559 PARITYf, LLS_L2_ECC_DEBUG1r, DB_L2_WERR_NEXT_ENABLE_ECCf, 560 LLS_L2_WERR_NEXT_ECC_STATUSr, DB_L2_WERR_NEXT_ECC_ERROR_ADDRESSf}, 561 562 { 0x00000010, LLS_L2_CHILD_WEIGHT_CFG_CNTm, "", 563 DB_L2_CHILD_WEIGHT_CFG_CNT_UNCORRECTED_ERRORf, 564 DB_L2_CHILD_WEIGHT_CFG_CNT_UNCORRECTED_ERROR_DISINTf, 565 ECCf, LLS_L2_ECC_DEBUG1r, DB_L2_CHILD_WEIGHT_CFG_CNT_ENABLE_ECCf, 566 LLS_L2_CHILD_WEIGHT_CFG_ECC_STATUSr, DB_L2_CHILD_WEIGHT_CFG_CNT_ECC_ERROR_ADDRESSf}, 567 { 0x00000020, LLS_L2_CHILD_WEIGHT_CFG_CNTm, "", 568 DB_L2_CHILD_WEIGHT_CFG_CNT_CORRECTED_ERRORf, 569 DB_L2_CHILD_WEIGHT_CFG_CNT_CORRECTED_ERROR_DISINTf, 570 PARITYf, LLS_L2_ECC_DEBUG1r, DB_L2_CHILD_WEIGHT_CFG_CNT_ENABLE_ECCf, 571 LLS_L2_CHILD_WEIGHT_CFG_ECC_STATUSr, DB_L2_CHILD_WEIGHT_CFG_CNT_ECC_ERROR_ADDRESSf}, 572 573 { 0x00000040, LLS_L2_PARENTm, "", 574 DB_L2_PARENT_UNCORRECTED_ERRORf, 575 DB_L2_PARENT_UNCORRECTED_ERROR_DISINTf, 576 ECCf, LLS_L2_ECC_DEBUG1r, DB_L2_PARENT_ENABLE_ECCf, 577 LLS_L2_PARENT_ECC_STATUSr, DB_L2_PARENT_ECC_ERROR_ADDRESSf}, 578 { 0x00000080, LLS_L2_PARENTm, "", 579 DB_L2_PARENT_CORRECTED_ERRORf, 580 DB_L2_PARENT_CORRECTED_ERROR_DISINTf, 581 PARITYf, LLS_L2_ECC_DEBUG1r, DB_L2_PARENT_ENABLE_ECCf, 582 LLS_L2_PARENT_ECC_STATUSr, DB_L2_PARENT_ECC_ERROR_ADDRESSf}, 583 584 { 0x00000100, LLS_L2_CHILD_STATE1m, "", 585 DB_L2_CHILD_STATE1_UNCORRECTED_ERRORf, 586 DB_L2_CHILD_STATE1_UNCORRECTED_ERROR_DISINTf, 587 ECCf, LLS_L2_ECC_DEBUG1r, DB_L2_CHILD_STATE1_ENABLE_ECCf, 588 LLS_L2_CHILD_STATE1_ECC_STATUSr, DB_L2_CHILD_STATE1_ECC_ERROR_ADDRESSf}, 589 { 0x00000200, LLS_L2_CHILD_STATE1m, "", 590 DB_L2_CHILD_STATE1_CORRECTED_ERRORf, 591 DB_L2_CHILD_STATE1_CORRECTED_ERROR_DISINTf, 592 PARITYf, LLS_L2_ECC_DEBUG1r, DB_L2_CHILD_STATE1_ENABLE_ECCf, 593 LLS_L2_CHILD_STATE1_ECC_STATUSr, DB_L2_CHILD_STATE1_ECC_ERROR_ADDRESSf}, 594 595 596 { 0x00000400, LLS_L2_SHAPER_BUCKETm, "", 597 DB_L2_SHAPER_BUCKET_C_UNCORRECTED_ERRORf, 598 DB_L2_SHAPER_BUCKET_C_UNCORRECTED_ERROR_DISINTf, 599 ECCf, LLS_L2_ECC_DEBUG2r, DB_L2_SHAPER_BUCKET_C_ENABLE_ECCf, 600 LLS_L2_SHAPER_BUCKET_C_ECC_STATUSr, DB_L2_SHAPER_BUCKET_C_ECC_ERROR_ADDRESSf}, 601 { 0x00000800, LLS_L2_SHAPER_BUCKETm, "", 602 DB_L2_SHAPER_BUCKET_C_CORRECTED_ERRORf, 603 DB_L2_SHAPER_BUCKET_C_CORRECTED_ERROR_DISINTf, 604 PARITYf, LLS_L2_ECC_DEBUG2r, DB_L2_SHAPER_BUCKET_C_ENABLE_ECCf, 605 LLS_L2_SHAPER_BUCKET_C_ECC_STATUSr, DB_L2_SHAPER_BUCKET_C_ECC_ERROR_ADDRESSf}, 606 607 { 0x00001000, LLS_L2_MIN_BUCKET_Cm, "", 608 DB_L2_MIN_BUCKET_C_UNCORRECTED_ERRORf, 609 DB_L2_MIN_BUCKET_C_UNCORRECTED_ERROR_DISINTf, 610 ECCf, LLS_L2_ECC_DEBUG2r, DB_L2_MIN_BUCKET_C_ENABLE_ECCf, 611 LLS_L2_MIN_BUCKET_C_ECC_STATUSr, DB_L2_MIN_BUCKET_C_ECC_ERROR_ADDRESSf}, 612 { 0x00002000, LLS_L2_MIN_BUCKET_Cm, "", 613 DB_L2_MIN_BUCKET_C_CORRECTED_ERRORf, 614 DB_L2_MIN_BUCKET_C_CORRECTED_ERROR_DISINTf, 615 PARITYf, LLS_L2_ECC_DEBUG2r, DB_L2_MIN_BUCKET_C_ENABLE_ECCf, 616 LLS_L2_MIN_BUCKET_C_ECC_STATUSr, DB_L2_MIN_BUCKET_C_ECC_ERROR_ADDRESSf}, 617 618 { 0x00004000, LLS_L2_MIN_CONFIG_Cm, "", 619 DB_L2_MIN_CONFIG_C_UNCORRECTED_ERRORf, 620 DB_L2_MIN_CONFIG_C_UNCORRECTED_ERROR_DISINTf, 621 ECCf, LLS_L2_ECC_DEBUG2r, DB_L2_MIN_CONFIG_C_ENABLE_ECCf, 622 LLS_L2_MIN_CONFIG_C_ECC_STATUSr, DB_L2_MIN_CONFIG_C_ECC_ERROR_ADDRESSf}, 623 { 0x00008000, LLS_L2_MIN_CONFIG_Cm, "", 624 DB_L2_MIN_CONFIG_C_CORRECTED_ERRORf, 625 DB_L2_MIN_CONFIG_C_CORRECTED_ERROR_DISINTf, 626 PARITYf, LLS_L2_ECC_DEBUG2r, DB_L2_MIN_CONFIG_C_ENABLE_ECCf, 627 LLS_L2_MIN_CONFIG_C_ECC_STATUSr, DB_L2_MIN_CONFIG_C_ECC_ERROR_ADDRESSf}, 628 629 630 { 0x00010000, LLS_L2_SHAPER_CONFIG_Cm, "", 631 DB_L2_SHAPER_CONFIG_C_UNCORRECTED_ERRORf, 632 DB_L2_SHAPER_CONFIG_C_UNCORRECTED_ERROR_DISINTf, 633 ECCf, LLS_L2_ECC_DEBUG2r, DB_L2_SHAPER_CONFIG_C_ENABLE_ECCf, 634 LLS_L2_SHAPER_CONFIG_C_ECC_STATUSr, DB_L2_SHAPER_CONFIG_C_ECC_ERROR_ADDRESSf}, 635 { 0x00020000, LLS_L2_SHAPER_CONFIG_Cm, "", 636 DB_L2_SHAPER_CONFIG_C_CORRECTED_ERRORf, 637 DB_L2_SHAPER_CONFIG_C_CORRECTED_ERROR_DISINTf, 638 PARITYf, LLS_L2_ECC_DEBUG2r, DB_L2_SHAPER_CONFIG_C_ENABLE_ECCf, 639 LLS_L2_SHAPER_CONFIG_C_ECC_STATUSr, DB_L2_SHAPER_CONFIG_C_ECC_ERROR_ADDRESSf}, 640 641 642 { 0 } /* table terminator */ 643 644 }; 645 646 647 STATIC 648 _soc_saber2_mmu_sub_block_leaf_info_t _soc_saber2_mmu_sb_lls_port_parity_info[] = { 649 /* LLS_PORT_ECC_ERRORr */ 650 { 0x00000001, LLS_PORT_TDMm, "", 651 DB_PORT_TDM_UNCORRECTED_ERRORf, 652 DB_PORT_TDM_UNCORRECTED_ERROR_DISINTf, 653 ECCf, LLS_PORT_ECC_DEBUGr, DB_PORT_TDM_ENABLE_ECCf, 654 LLS_PORT_TDM_ECC_STATUSr, DB_PORT_TDM_ECC_ERROR_ADDRESSf}, 655 { 0x00000002, LLS_PORT_TDMm, "", 656 DB_PORT_TDM_CORRECTED_ERRORf, 657 DB_PORT_TDM_CORRECTED_ERROR_DISINTf, 658 PARITYf, LLS_PORT_ECC_DEBUGr, DB_PORT_TDM_ENABLE_ECCf, 659 LLS_PORT_TDM_ECC_STATUSr, DB_PORT_TDM_ECC_ERROR_ADDRESSf}, 660 661 { 0 } /* table terminator */ 662 663 }; 664 665 STATIC 666 _soc_saber2_mmu_sub_block_leaf_info_t _soc_saber2_mmu_sb_lls_misc_parity_info[] = { 667 /* LLS_MISC_ECC_ERROR1 */ 668 { 0x00000001, LLS_L2_ERRORm, "", 669 DB_L2_ERROR_UNCORRECTED_ERRORf, 670 DB_L2_ERROR_UNCORRECTED_ERROR_DISINTf, 671 ECCf, LLS_ERROR_ECC_DEBUGr, DB_L2_ERROR_ENABLE_ECCf, 672 LLS_L2_ERROR_ECC_STATUSr, DB_L2_ERROR_ECC_ERROR_ADDRESSf}, 673 { 0x00000002, LLS_L2_ERRORm, "", 674 DB_L2_ERROR_CORRECTED_ERRORf, 675 DB_L2_ERROR_CORRECTED_ERROR_DISINTf, 676 PARITYf, LLS_ERROR_ECC_DEBUGr, DB_L2_ERROR_ENABLE_ECCf, 677 LLS_L2_ERROR_ECC_STATUSr, DB_L2_ERROR_ECC_ERROR_ADDRESSf}, 678 679 { 0x00000004, LLS_L1_ERRORm, "", 680 DB_L1_ERROR_UNCORRECTED_ERRORf, 681 DB_L1_ERROR_UNCORRECTED_ERROR_DISINTf, 682 ECCf, LLS_ERROR_ECC_DEBUGr, DB_L1_ERROR_ENABLE_ECCf, 683 LLS_L1_ERROR_ECC_STATUSr, DB_L1_ERROR_ECC_ERROR_ADDRESSf}, 684 { 0x00000008, LLS_L1_ERRORm, "", 685 DB_L1_ERROR_CORRECTED_ERRORf, 686 DB_L1_ERROR_CORRECTED_ERROR_DISINTf, 687 PARITYf, LLS_ERROR_ECC_DEBUGr, DB_L1_ERROR_ENABLE_ECCf, 688 LLS_L1_ERROR_ECC_STATUSr, DB_L1_ERROR_ECC_ERROR_ADDRESSf}, 689 690 691 { 0x00000010, LLS_L0_ERRORm, "", 692 DB_L0_ERROR_UNCORRECTED_ERRORf, 693 DB_L0_ERROR_UNCORRECTED_ERROR_DISINTf, 694 ECCf, LLS_ERROR_ECC_DEBUGr, DB_L0_ERROR_ENABLE_ECCf, 695 LLS_L0_ERROR_ECC_STATUSr, DB_L0_ERROR_ECC_ERROR_ADDRESSf}, 696 { 0x00000020, LLS_L0_ERRORm, "", 697 DB_L0_ERROR_CORRECTED_ERRORf, 698 DB_L0_ERROR_CORRECTED_ERROR_DISINTf, 699 PARITYf, LLS_ERROR_ECC_DEBUGr, DB_L0_ERROR_ENABLE_ECCf, 700 LLS_L0_ERROR_ECC_STATUSr, DB_L0_ERROR_ECC_ERROR_ADDRESSf}, 701 702 { 0 } /* table terminator */ 703 704 }; 705 STATIC _soc_saber2_mmu_sub_block_leaf_info_t 706 _soc_saber2_mmu_sb_aging_int_parity_info [] = { 707 /* AGING_ERROR_INT */ 708 { 0x0020, MMU_AGING_LMT_INTm, "", 709 LMT_CORRECTED_ERRORf, LMT_CORRECTED_ERROR_DISINTf, 710 PARITYf, AGING_LMT_ECC_CONTROL_INTr, ENABLE_ECCf, 711 ECC_ERR_PTR_LMT_INTr, PTRf}, 712 { 0x0010, MMU_AGING_LMT_INTm, "", 713 LMT_UNCORRECTED_ERRORf, LMT_UNCORRECTED_ERROR_DISINTf, 714 ECCf, AGING_LMT_ECC_CONTROL_INTr, ENABLE_ECCf, 715 ECC_ERR_PTR_LMT_INTr, PTRf}, 716 717 { 0x0008, MMU_AGING_CTR_INTm, "", 718 CTR_CORRECTED_ERRORf, CTR_CORRECTED_ERROR_DISINTf, 719 PARITYf, AGING_CTR_ECC_CONTROL_INTr, ENABLE_ECCf, 720 ECC_ERR_PTR_CTR_INTr, PTRf}, 721 { 0x0004, MMU_AGING_CTR_INTm, "", 722 CTR_UNCORRECTED_ERRORf, CTR_UNCORRECTED_ERROR_DISINTf, 723 ECCf, AGING_CTR_ECC_CONTROL_INTr, ENABLE_ECCf, 724 ECC_ERR_PTR_CTR_INTr, PTRf}, 725 726 { 0x0002, MMU_AGING_EXP_INTm, "", 727 EXP_CORRECTED_ERRORf, EXP_CORRECTED_ERROR_DISINTf, 728 PARITYf, AGING_EXP_ECC_CONTROL_INTr, ENABLE_ECCf, 729 ECC_ERR_PTR_EXP_INTr, PTRf}, 730 { 0x0001, MMU_AGING_EXP_INTm, "", 731 EXP_UNCORRECTED_ERRORf, EXP_UNCORRECTED_ERROR_DISINTf, 732 ECCf, AGING_EXP_ECC_CONTROL_INTr, ENABLE_ECCf, 733 ECC_ERR_PTR_EXP_INTr, PTRf}, 734 735 { 0 } /* table terminator */ 736 737 }; 738 739 STATIC _soc_saber2_mmu_sub_block_leaf_info_t 740 _soc_saber2_mmu_sb_aging_ext_parity_info [] = { 741 { 0x0020, MMU_AGING_LMT_EXTm, "", 742 LMT_CORRECTED_ERRORf, LMT_CORRECTED_ERROR_DISINTf, 743 PARITYf, AGING_LMT_ECC_CONTROL_EXTr, ENABLE_ECCf, 744 ECC_ERR_PTR_LMT_EXTr, PTRf}, 745 { 0x0010, MMU_AGING_LMT_EXTm, "", 746 LMT_UNCORRECTED_ERRORf, LMT_UNCORRECTED_ERROR_DISINTf, 747 ECCf, AGING_LMT_ECC_CONTROL_EXTr, ENABLE_ECCf, 748 ECC_ERR_PTR_LMT_EXTr, PTRf}, 749 750 { 0x0008, MMU_AGING_CTR_EXTm, "", 751 CTR_CORRECTED_ERRORf, CTR_CORRECTED_ERROR_DISINTf, 752 PARITYf, AGING_CTR_ECC_CONTROL_EXTr, ENABLE_ECCf, 753 ECC_ERR_PTR_CTR_EXTr, PTRf}, 754 { 0x0004, MMU_AGING_CTR_EXTm, "", 755 CTR_UNCORRECTED_ERRORf, CTR_UNCORRECTED_ERROR_DISINTf, 756 ECCf, AGING_CTR_ECC_CONTROL_EXTr, ENABLE_ECCf, 757 ECC_ERR_PTR_CTR_EXTr, PTRf}, 758 759 { 0x0002, MMU_AGING_EXP_EXTm, "", 760 EXP_CORRECTED_ERRORf, EXP_CORRECTED_ERROR_DISINTf, 761 PARITYf, AGING_EXP_ECC_CONTROL_EXTr, ENABLE_ECCf, 762 ECC_ERR_PTR_EXP_EXTr, PTRf}, 763 { 0x0001, MMU_AGING_EXP_EXTm, "", 764 EXP_UNCORRECTED_ERRORf, EXP_UNCORRECTED_ERROR_DISINTf, 765 ECCf, AGING_EXP_ECC_CONTROL_EXTr, ENABLE_ECCf, 766 ECC_ERR_PTR_EXP_EXTr, PTRf}, 767 768 { 0 } /* table terminator */ 769 770 }; 771 772 STATIC _soc_saber2_mmu_sub_block_leaf_info_t 773 _soc_saber2_mmu_sb_ccp_parity_info [] = { 774 /* CCP_ERROR */ 775 776 { 0x20000, INVALIDm, "CCPE_SOP_FIFO_TAIL_OVERFLOW", 777 CCPE_SOP_FIFO_TAIL_OVERFLOWf, CCPE_SOP_FIFO_TAIL_OVERFLOW_DISINTf, 778 INVALIDf, INVALIDr, INVALIDf, 779 INVALIDr, INVALIDf}, 780 781 { 0x10000, INVALIDm, "CCPE_SOP_FIFO_FRONT_OVERFLOW", 782 CCPE_SOP_FIFO_FRONT_OVERFLOWf, CCPE_SOP_FIFO_FRONT_OVERFLOW_DISINTf, 783 INVALIDf, INVALIDr, INVALIDf, 784 INVALIDr, INVALIDf}, 785 786 { 0x8000, INVALIDm, "CCPI_SOP_FIFO_TAIL_OVERFLOW", 787 CCPI_SOP_FIFO_TAIL_OVERFLOWf, CCPI_SOP_FIFO_TAIL_OVERFLOW_DISINTf, 788 INVALIDf, INVALIDr, INVALIDf, 789 INVALIDr, INVALIDf}, 790 791 { 0x4000, INVALIDm, "CCPI_SOP_FIFO_FRONT_OVERFLOW", 792 CCPI_SOP_FIFO_FRONT_OVERFLOWf, CCPI_SOP_FIFO_FRONT_OVERFLOW_DISINTf, 793 INVALIDf, INVALIDr, INVALIDf, 794 INVALIDr, INVALIDf}, 795 796 { 0x2000, INVALIDm, "CCPE_FIFO_TAIL_CORRECTED", 797 CCPE_FIFO_TAIL_CORRECTED_ERRORf, CCPE_FIFO_TAIL_CORRECTED_ERROR_DISINTf, 798 INVALIDf, INVALIDr, INVALIDf, 799 INVALIDr, INVALIDf}, 800 801 { 0x1000, INVALIDm, "CCPE_FIFO_TAIL_UNCORRECTED", 802 CCPE_FIFO_TAIL_UNCORRECTED_ERRORf, CCPE_FIFO_TAIL_UNCORRECTED_ERROR_DISINTf, 803 INVALIDf, INVALIDr, INVALIDf, 804 INVALIDr, INVALIDf}, 805 806 { 0x0800, INVALIDm, "CCPE_FIFO_FRONT_CORRECTED", 807 CCPE_FIFO_FRONT_CORRECTED_ERRORf, CCPE_FIFO_FRONT_CORRECTED_ERRORf, 808 INVALIDf, INVALIDr, INVALIDf, 809 INVALIDr, INVALIDf}, 810 811 { 0x0400, INVALIDm, "CCPE_FIFO_FRONT_UNCORRECTED", 812 CCPE_FIFO_FRONT_UNCORRECTED_ERRORf, CCPE_FIFO_FRONT_UNCORRECTED_ERROR_DISINTf, 813 INVALIDf, INVALIDr, INVALIDf, 814 INVALIDr, INVALIDf}, 815 816 { 0x0200, INVALIDm, "CCPI_FIFO_TAIL_CORRECTED_ERROR", 817 CCPI_FIFO_TAIL_CORRECTED_ERRORf, CCPI_FIFO_TAIL_CORRECTED_ERROR_DISINTf, 818 INVALIDf, INVALIDr, INVALIDf, 819 INVALIDr, INVALIDf}, 820 821 { 0x0100, INVALIDm, "CCPI_FIFO_TAIL_UNCORRECTED_ERROR", 822 CCPI_FIFO_TAIL_UNCORRECTED_ERRORf, CCPI_FIFO_TAIL_UNCORRECTED_ERROR_DISINTf, 823 INVALIDf, INVALIDr, INVALIDf, 824 INVALIDr, INVALIDf}, 825 826 { 0x0080, INVALIDm, "CCPI_FIFO_FRONT_CORRECTED_ERROR", 827 CCPI_FIFO_FRONT_CORRECTED_ERRORf, CCPI_FIFO_FRONT_CORRECTED_ERRORf, 828 INVALIDf, INVALIDr, INVALIDf, 829 INVALIDr, INVALIDf}, 830 831 { 0x0040, INVALIDm, "CCPI_FIFO_FRONT_UNCORRECTED_ERROR", 832 CCPI_FIFO_FRONT_UNCORRECTED_ERRORf, CCPI_FIFO_FRONT_UNCORRECTED_ERROR_DISINTf, 833 INVALIDf, INVALIDr, INVALIDf, 834 INVALIDr, INVALIDf}, 835 836 { 0x0020, INVALIDm, "CCPI_RQE_UPD_NEGATIVE", 837 CCPI_RQE_UPD_NEGATIVEf, CCPI_RQE_UPD_NEGATIVE_DISINTf, 838 INVALIDf, INVALIDr, INVALIDf, 839 INVALIDr, INVALIDf}, 840 841 { 0x0010, INVALIDm, "CCPE_RQE_UPD_NEGATIVE", 842 CCPE_RQE_UPD_NEGATIVEf, CCPE_RQE_UPD_NEGATIVE_DISINTf, 843 INVALIDf, INVALIDr, INVALIDf, 844 INVALIDr, INVALIDf}, 845 846 847 { 0x0008, MMU_CCPE_MEMm, "", 848 CCPE_CORRECTED_ERRORf, CCPE_CORRECTED_ERROR_DISINTf, 849 PARITYf, CCPE_MEMDEBUGr, ENABLE_ECCf, 850 MMU_CCPE_MEM_ECC_STATUSr, ECC_ERROR_ADDRESSf}, 851 { 0x0004, MMU_CCPE_MEMm, "", 852 CCPE_UNCORRECTED_ERRORf, CCPE_UNCORRECTED_ERROR_DISINTf, 853 ECCf, CCPE_MEMDEBUGr, ENABLE_ECCf, 854 MMU_CCPE_MEM_ECC_STATUSr, ECC_ERROR_ADDRESSf}, 855 856 { 0x0002, MMU_CCPI_MEMm, "", 857 CCPI_CORRECTED_ERRORf, CCPI_CORRECTED_ERROR_DISINTf, 858 PARITYf, CCPI_MEMDEBUGr, ENABLE_ECCf, 859 MMU_CCPI_MEM_ECC_STATUSr, ECC_ERROR_ADDRESSf}, 860 { 0x0001, MMU_CCPI_MEMm, "", 861 CCPI_UNCORRECTED_ERRORf, CCPI_UNCORRECTED_ERROR_DISINTf, 862 ECCf, CCPI_MEMDEBUGr, ENABLE_ECCf, 863 MMU_CCPI_MEM_ECC_STATUSr, ECC_ERROR_ADDRESSf}, 864 865 { 0 } /* table terminator */ 866 867 }; 868 869 870 STATIC _soc_saber2_mmu_sub_block_leaf_info_t 871 _soc_saber2_mmu_sb_cfapi_parity_info [] = { 872 /* CFAPI_ECC_ERROR */ 873 { 0x0008, MMU_CFAPI_BITMAPm, "", 874 BITMAP_CORRECTED_ERRORf, BITMAP_CORRECTED_ERROR_DISINTf, 875 PARITYf, INVALIDr, INVALIDf, 876 CFAPI_BITMAP_ECC_STATUSr, ECC_ERROR_ADDRESSf}, 877 { 0x0004, MMU_CFAPI_BITMAPm, "", 878 BITMAP_UNCORRECTED_ERRORf, BITMAP_UNCORRECTED_ERROR_DISINTf, 879 ECCf, INVALIDr, INVALIDf, 880 CFAPI_BITMAP_ECC_STATUSr, ECC_ERROR_ADDRESSf}, 881 882 { 0x0002, MMU_CFAPI_STACKm, "", 883 STACK_CORRECTED_ERRORf, STACK_CORRECTED_ERROR_DISINTf, 884 PARITYf, INVALIDr, INVALIDf, 885 CFAPI_STACK_ECC_STATUSr, ECC_ERROR_ADDRESSf}, 886 { 0x0001, MMU_CFAPI_STACKm, "", 887 STACK_UNCORRECTED_ERRORf, STACK_UNCORRECTED_ERROR_DISINTf, 888 ECCf, INVALIDr, INVALIDf, 889 CFAPI_STACK_ECC_STATUSr, ECC_ERROR_ADDRESSf}, 890 891 { 0 } /* table terminator */ 892 893 }; 894 895 896 STATIC _soc_saber2_mmu_sub_block_leaf_info_t 897 _soc_saber2_mmu_sb_cfape_parity_info [] = { 898 /* CFAPE_ECC_ERROR */ 899 { 0x0008, MMU_CFAPE_BITMAPm, "", 900 BITMAP_CORRECTED_ERRORf, BITMAP_CORRECTED_ERROR_DISINTf, 901 PARITYf, INVALIDr, INVALIDf, 902 CFAPE_BITMAP_ECC_STATUSr, ECC_ERROR_ADDRESSf}, 903 { 0x0004, MMU_CFAPE_BITMAPm, "", 904 BITMAP_UNCORRECTED_ERRORf, BITMAP_UNCORRECTED_ERROR_DISINTf, 905 ECCf, INVALIDr, INVALIDf, 906 CFAPE_BITMAP_ECC_STATUSr, ECC_ERROR_ADDRESSf}, 907 908 { 0x0002, MMU_CFAPE_STACKm, "", 909 STACK_CORRECTED_ERRORf, STACK_CORRECTED_ERROR_DISINTf, 910 PARITYf, INVALIDr, INVALIDf, 911 CFAPE_STACK_ECC_STATUSr, ECC_ERROR_ADDRESSf}, 912 { 0x0001, MMU_CFAPE_STACKm, "", 913 STACK_UNCORRECTED_ERRORf, STACK_UNCORRECTED_ERROR_DISINTf, 914 ECCf, INVALIDr, INVALIDf, 915 CFAPE_STACK_ECC_STATUSr, ECC_ERROR_ADDRESSf}, 916 917 { 0 } /* table terminator */ 918 919 }; 920 921 STATIC _soc_saber2_mmu_sub_block_leaf_info_t 922 _soc_saber2_mmu_sb_ctr_parity_info [] = { 923 /* CTR_ERROR */ 924 { 0x0002, INVALIDm, "CTR_FLEX_COUNT", 925 CTR_FLEX_CNT_CORRECTED_ERRORf, CTR_FLEX_CNT_CORRECTED_ERROR_DISINTf, 926 INVALIDf, INVALIDr, INVALIDf, 927 INVALIDr, INVALIDf}, 928 { 0x0001, INVALIDm, "CTR_FLEX_COUNT", 929 CTR_FLEX_CNT_UNCORRECTED_ERRORf, CTR_FLEX_CNT_UNCORRECTED_ERROR_DISINTf, 930 INVALIDf, INVALIDr, INVALIDf, 931 INVALIDr, INVALIDf}, 932 933 { 0 } /* table terminator */ 934 935 }; 936 937 STATIC _soc_saber2_mmu_sub_block_leaf_info_t 938 _soc_saber2_mmu_sb_rqe_parity_info [] = { 939 /* RQE_SER_STATUS */ 940 { 0x003fe00, INVALIDm, "RQE ECC_1B_BITMAP", 941 ECC_1B_BITMAPf, ECC_1B_MASKf, 942 INVALIDf, INVALIDr, INVALIDf, 943 INVALIDr, INVALIDf}, 944 945 { 0x00001ff, INVALIDm, "RQE ECC_2B_BITMAP", 946 ECC_2B_BITMAPf, ECC_2B_MASKf, 947 INVALIDf, INVALIDr, INVALIDf, 948 INVALIDr, INVALIDf}, 949 950 { 0 } /* table terminator */ 951 952 }; 953 954 STATIC _soc_saber2_mmu_sub_block_leaf_info_t 955 _soc_saber2_mmu_sb_thdo_stat1_parity_info [] = { 956 /* THDO_PARITY_ERROR_STATUS1 */ 957 { 0x003ffff, INVALIDm, "THDO ECC_1B_BITMAP", 958 ECC_1B_ERROR_STATUSf, ECC_1B_MASKf, 959 INVALIDf, INVALIDr, INVALIDf, 960 INVALIDr, INVALIDf}, 961 962 963 { 0 } /* table terminator */ 964 965 }; 966 967 STATIC _soc_saber2_mmu_sub_block_leaf_info_t 968 _soc_saber2_mmu_sb_thdo_stat2_parity_info [] = { 969 /* THDO_PARITY_ERROR_STATUS2 */ 970 { 0x003ffff, INVALIDm, "THDO ECC_2B_BITMAP", 971 ECC_2B_ERROR_STATUSf, ECC_2B_MASKf, 972 INVALIDf, INVALIDr, INVALIDf, 973 INVALIDr, INVALIDf}, 974 975 { 0 } /* table terminator */ 976 977 }; 978 979 STATIC _soc_saber2_mmu_sub_block_leaf_info_t 980 _soc_saber2_mmu_sb_wred_parity_info [] = { 981 /* WRED_PARITY_ERROR_BITMAP */ 982 { 0x3ffe000, INVALIDm, "WRED ECC_1BIT error", 983 ECC_ERROR_1Bf, ECC_1B_ERROR_MASKf, 984 INVALIDf, INVALIDr, INVALIDf, 985 INVALIDr, INVALIDf}, 986 987 { 0x1fff, INVALIDm, "WRED ECC_2BIT error", 988 ECC_ERROR_2Bf, ECC_2B_ERROR_MASKf, 989 INVALIDf, INVALIDr, INVALIDf, 990 INVALIDr, INVALIDf}, 991 992 { 0 } /* table terminator */ 993 994 }; 995 996 STATIC _soc_saber2_mmu_sub_block_leaf_info_t 997 _soc_saber2_mmu_sb_wred_profile_parity_info [] = { 998 /* WRED_PROFILE_PARITY_ERROR_BITMAP */ 999 { 0xfff000, INVALIDm, "WRED PROFILE ECC_1_BIT error", 1000 ECC_ERROR_1Bf, ECC_1B_ERROR_MASKf, 1001 INVALIDf, INVALIDr, INVALIDf, 1002 INVALIDr, INVALIDf}, 1003 1004 { 0xfff, INVALIDm, "WRED PROFILE ECC_2BIT error", 1005 ECC_ERROR_2Bf, ECC_2B_ERROR_MASKf, 1006 INVALIDf, INVALIDr, INVALIDf, 1007 INVALIDr, INVALIDf}, 1008 1009 { 0 } /* table terminator */ 1010 1011 }; 1012 1013 STATIC _soc_saber2_mmu_sub_block_leaf_info_t 1014 _soc_saber2_mmu_sb_ci_parity_info [] = { 1015 /* CI_ERROR */ 1016 { 0x0080, INVALIDm, "CI PHY_ERROR", 1017 PHY_ERROR_DETECTf, PHY_ERROR_DETECTf, 1018 INVALIDf, INVALIDr, INVALIDf, 1019 INVALIDr, INVALIDf}, 1020 1021 { 0x0040, INVALIDm, "CI PHY_READY_EVENT", 1022 PHY_READY_EVENTf, PHY_READY_EVENTf, 1023 INVALIDf, INVALIDr, INVALIDf, 1024 INVALIDr, INVALIDf}, 1025 1026 { 0x0020, INVALIDm, "CI WFIFO_CTL_CORRECTED_ERROR", 1027 WFIFO_CTL_CORRECTED_ERRORf, WFIFO_CTL_CORRECTED_ERROR_DISINTf, 1028 INVALIDf, INVALIDr, INVALIDf, 1029 INVALIDr, INVALIDf}, 1030 { 0x0010, INVALIDm, "CI WFIFO_CTL_UNCORRECTED_ERROR", 1031 WFIFO_CTL_UNCORRECTED_ERRORf, WFIFO_CTL_UNCORRECTED_ERROR_DISINTf, 1032 INVALIDf, INVALIDr, INVALIDf, 1033 INVALIDr, INVALIDf}, 1034 1035 { 0x0008, INVALIDm, "CI WFIFO_OVERFLOW", 1036 WFIFO_OVERFLOWf, WB_OVERFLOW_DISINTf, 1037 INVALIDf, INVALIDr, INVALIDf, 1038 INVALIDr, INVALIDf}, 1039 1040 { 0x0004, INVALIDm, "CI RFIFO_CTL_CORRECTED_ERROR", 1041 RFIFO_CTL_CORRECTED_ERRORf, RFIFO_CTL_CORRECTED_ERROR_DISINTf, 1042 INVALIDf, INVALIDr, INVALIDf, 1043 INVALIDr, INVALIDf}, 1044 1045 { 0x0002, INVALIDm, "CI RFIFO_CTL_UNCORRECTED_ERROR", 1046 RFIFO_CTL_UNCORRECTED_ERRORf, RFIFO_CTL_UNCORRECTED_ERROR_DISINTf, 1047 INVALIDf, INVALIDr, INVALIDf, 1048 INVALIDr, INVALIDf}, 1049 1050 { 0x0001, INVALIDm, "CI RFIFO_OVERFLOW", 1051 RFIFO_OVERFLOWf, RFIFO_OVERFLOW_DISINTf, 1052 INVALIDf, INVALIDr, INVALIDf, 1053 INVALIDr, INVALIDf}, 1054 1055 1056 { 0 } /* table terminator */ 1057 1058 }; 1059 1060 1061 STATIC _soc_saber2_mmu_sub_block_leaf_info_t 1062 _soc_saber2_mmu_sb_enq_cfg_parity_info [] = { 1063 /* MMU_ENQ_CFG_ECC_ERROR_0 */ 1064 { 0x800000, INVALIDm, "ENQ CFG CBI_CORRECTED_ERROR", 1065 CBI_CORRECTED_ERRORf, CBI_CORRECTED_ERROR_DISINTf, 1066 INVALIDf, INVALIDr, INVALIDf, 1067 INVALIDr, INVALIDf}, 1068 { 0x400000, INVALIDm, "ENQ CFG CBI_UNCORRECTED_ERROR", 1069 CBI_UNCORRECTED_ERRORf, CBI_UNCORRECTED_ERROR_DISINTf, 1070 INVALIDf, INVALIDr, INVALIDf, 1071 INVALIDr, INVALIDf}, 1072 1073 { 0x200000, INVALIDm, "ENQ CFG ITE_REORDER_FIFO_CORRECTED_ERROR", 1074 ITE_REORDER_FIFO_CORRECTED_ERRORf, ITE_REORDER_FIFO_CORRECTED_ERRORf, 1075 INVALIDf, INVALIDr, INVALIDf, 1076 INVALIDr, INVALIDf}, 1077 { 0x100000, INVALIDm, "ENQ CFG ITE_REORDER_FIFO_UNCORRECTED_ERROR", 1078 ITE_REORDER_FIFO_UNCORRECTED_ERRORf, ITE_REORDER_FIFO_UNCORRECTED_ERRORf, 1079 INVALIDf, INVALIDr, INVALIDf, 1080 INVALIDr, INVALIDf}, 1081 1082 { 0x80000, INVALIDm, "ENQ CFG PACKING_PKT_LEN_FIFOS_CORRECTED_ERROR", 1083 PACKING_PKT_LEN_FIFOS_CORRECTED_ERRORf, PACKING_PKT_LEN_FIFOS_CORRECTED_ERROR_DISINTf, 1084 INVALIDf, INVALIDr, INVALIDf, 1085 INVALIDr, INVALIDf}, 1086 { 0x40000, INVALIDm, "ENQ CFG PACKING_PKT_LEN_FIFOS_UNCORRECTED_ERROR", 1087 PACKING_PKT_LEN_FIFOS_UNCORRECTED_ERRORf, PACKING_PKT_LEN_FIFOS_UNCORRECTED_ERROR_DISINTf, 1088 INVALIDf, INVALIDr, INVALIDf, 1089 INVALIDr, INVALIDf}, 1090 1091 1092 { 0x20000, INVALIDm, "ENQ CFG PACKING_PORT_FIFOS_CORRECTED_ERROR", 1093 PACKING_PORT_FIFOS_CORRECTED_ERRORf, PACKING_PORT_FIFOS_CORRECTED_ERROR_DISINTf, 1094 INVALIDf, INVALIDr, INVALIDf, 1095 INVALIDr, INVALIDf}, 1096 { 0x10000, INVALIDm, "ENQ CFG PACKING_PORT_FIFOS_UNCORRECTED_ERROR", 1097 PACKING_PORT_FIFOS_UNCORRECTED_ERRORf, PACKING_PORT_FIFOS_UNCORRECTED_ERROR_DISINTf, 1098 INVALIDf, INVALIDr, INVALIDf, 1099 INVALIDr, INVALIDf}, 1100 1101 { 0x8000, INVALIDm, "ENQ CFG PACKING_CTXT_FIFOS_FP_LL_CORRECTED_ERROR", 1102 PACKING_CTXT_FIFOS_FP_LL_CORRECTED_ERRORf, PACKING_CTXT_FIFOS_FP_LL_CORRECTED_ERROR_DISINTf, 1103 INVALIDf, INVALIDr, INVALIDf, 1104 INVALIDr, INVALIDf}, 1105 { 0x4000, INVALIDm, "ENQ CFG PACKING_CTXT_FIFOS_FP_LL_UNCORRECTED_ERROR", 1106 PACKING_CTXT_FIFOS_FP_LL_UNCORRECTED_ERRORf, PACKING_CTXT_FIFOS_FP_LL_UNCORRECTED_ERROR_DISINTf, 1107 INVALIDf, INVALIDr, INVALIDf, 1108 INVALIDr, INVALIDf}, 1109 1110 { 0x2000, INVALIDm, "ENQ CFG PACKING_CTXT_FIFOS_CORRECTED_ERROR", 1111 PACKING_CTXT_FIFOS_CORRECTED_ERRORf, PACKING_CTXT_FIFOS_CORRECTED_ERROR_DISINTf, 1112 INVALIDf, INVALIDr, INVALIDf, 1113 INVALIDr, INVALIDf}, 1114 { 0x1000, INVALIDm, "ENQ CFG PACKING_CTXT_FIFOS_UNCORRECTED_ERROR", 1115 PACKING_CTXT_FIFOS_UNCORRECTED_ERRORf, PACKING_CTXT_FIFOS_UNCORRECTED_ERROR_DISINTf, 1116 INVALIDf, INVALIDr, INVALIDf, 1117 INVALIDr, INVALIDf}, 1118 1119 { 0x0800, INVALIDm, "ENQ CFG CFAPI_INTERNAL_RECYCLE_UNCORRECTED_ERROR", 1120 CFAPI_INTERNAL_RECYCLE_CORRECTED_ERRORf, CFAPI_INTERNAL_RECYCLE_CORRECTED_ERROR_DISINTf, 1121 INVALIDf, INVALIDr, INVALIDf, 1122 INVALIDr, INVALIDf}, 1123 { 0x0400, INVALIDm, "ENQ CFG CFAPI_INTERNAL_RECYCLE_UNCORRECTED_ERROR", 1124 CFAPI_INTERNAL_RECYCLE_UNCORRECTED_ERRORf, CFAPI_INTERNAL_RECYCLE_UNCORRECTED_ERROR_DISINTf, 1125 INVALIDf, INVALIDr, INVALIDf, 1126 INVALIDr, INVALIDf}, 1127 1128 { 0x0200, INVALIDm, "ENQ CFG SRC_PPP_TO_S1_LOOKUP_CORRECTED_ERROR", 1129 SRC_PPP_TO_S1_LOOKUP_CORRECTED_ERRORf, SRC_PPP_TO_S1_LOOKUP_CORRECTED_ERROR_DISINTf, 1130 INVALIDf, INVALIDr, INVALIDf, 1131 INVALIDr, INVALIDf}, 1132 { 0x0100, INVALIDm, "ENQ CFG SRC_PPP_TO_S1_LOOKUP_UNCORRECTED_ERROR", 1133 SRC_PPP_TO_S1_LOOKUP_UNCORRECTED_ERRORf, SRC_PPP_TO_S1_LOOKUP_UNCORRECTED_ERROR_DISINTf, 1134 INVALIDf, INVALIDr, INVALIDf, 1135 INVALIDr, INVALIDf}, 1136 1137 { 0x0080, INVALIDm, "ENQ CFG SRC_PORT_STATE_CORRECTED_ERROR", 1138 SRC_PORT_STATE_CORRECTED_ERRORf, SRC_PORT_STATE_CORRECTED_ERROR_DISINTf, 1139 INVALIDf, INVALIDr, INVALIDf, 1140 INVALIDr, INVALIDf}, 1141 { 0x0040, INVALIDm, "ENQ CFG SRC_PORT_STATE_UNCORRECTED_ERROR", 1142 SRC_PORT_STATE_UNCORRECTED_ERRORf, SRC_PORT_STATE_UNCORRECTED_ERROR_DISINTf, 1143 INVALIDf, INVALIDr, INVALIDf, 1144 INVALIDr, INVALIDf}, 1145 1146 { 0x0020, INVALIDm, "ENQ CFG SOP_STORE_CORRECTED_ERROR", 1147 SOP_STORE_CORRECTED_ERRORf, SOP_STORE_CORRECTED_ERROR_DISINTf, 1148 INVALIDf, INVALIDr, INVALIDf, 1149 INVALIDr, INVALIDf}, 1150 { 0x0010, INVALIDm, "ENQ CFG SOP_STORE_UNCORRECTED_ERROR", 1151 SOP_STORE_UNCORRECTED_ERRORf, SOP_STORE_UNCORRECTED_ERROR_DISINTf, 1152 INVALIDf, INVALIDr, INVALIDf, 1153 INVALIDr, INVALIDf}, 1154 1155 { 0x0008, INVALIDm, "ENQ CFG RQE_WR_COMPLETE_CORRECTED_ERROR", 1156 RQE_WR_COMPLETE_CORRECTED_ERRORf, RQE_WR_COMPLETE_CORRECTED_ERROR_DISINTf, 1157 INVALIDf, INVALIDr, INVALIDf, 1158 INVALIDr, INVALIDf}, 1159 { 0x0004, INVALIDm, "ENQ CFG RQE_WR_COMPLETE_UNCORRECTED_ERROR", 1160 RQE_WR_COMPLETE_UNCORRECTED_ERRORf, RQE_WR_COMPLETE_UNCORRECTED_ERROR_DISINTf, 1161 INVALIDf, INVALIDr, INVALIDf, 1162 INVALIDr, INVALIDf}, 1163 1164 { 0x0002, INVALIDm, "ENQ CFG CBP_32B_WR_STORE_CORRECTED_ERROR", 1165 CBP_32B_WR_STORE_CORRECTED_ERRORf, CBP_32B_WR_STORE_CORRECTED_ERROR_DISINTf, 1166 INVALIDf, INVALIDr, INVALIDf, 1167 INVALIDr, INVALIDf}, 1168 { 0x0001, INVALIDm, "ENQ CFG CBP_32B_WR_STORE_UNCORRECTED_ERROR", 1169 CBP_32B_WR_STORE_UNCORRECTED_ERRORf, CBP_32B_WR_STORE_UNCORRECTED_ERROR_DISINTf, 1170 INVALIDf, INVALIDr, INVALIDf, 1171 INVALIDr, INVALIDf}, 1172 1173 { 0 } /* table terminator */ 1174 1175 }; 1176 STATIC _soc_saber2_mmu_sub_block_leaf_info_t 1177 _soc_saber2_mmu_sb_enq_fap_parity_info [] = { 1178 /* MMU_ENQ_FAP_ECC_ERROR_0 */ 1179 { 0x0008, INVALIDm, "ENQ FAP_STACK_CORRECTED_ERROR", 1180 FAP_STACK_CORRECTED_ERRORf, FAP_STACK_CORRECTED_ERROR_DISINTf, 1181 INVALIDf, INVALIDr, INVALIDf, 1182 INVALIDr, INVALIDf}, 1183 { 0x0004, INVALIDm, "ENQ FAP_STACK_UNCORRECTED_ERROR", 1184 FAP_STACK_UNCORRECTED_ERRORf, FAP_STACK_UNCORRECTED_ERROR_ERROR_DISINTf, 1185 INVALIDf, INVALIDr, INVALIDf, 1186 INVALIDr, INVALIDf}, 1187 1188 { 0x0002, INVALIDm, "ENQ FAP_BITMAP_CORRECTED_ERROR", 1189 FAP_BITMAP_CORRECTED_ERRORf, FAP_BITMAP_CORRECTED_ERROR_DISINTf, 1190 INVALIDf, INVALIDr, INVALIDf, 1191 INVALIDr, INVALIDf}, 1192 { 0x0001, INVALIDm, "ENQ FAP_BITMAP_UNCORRECTED_ERROR", 1193 FAP_BITMAP_UNCORRECTED_ERRORf, FAP_BITMAP_UNCORRECTED_ERROR_DISINTf, 1194 INVALIDf, INVALIDr, INVALIDf, 1195 INVALIDr, INVALIDf}, 1196 1197 { 0 } /* table terminator */ 1198 1199 }; 1200 1201 1202 STATIC _soc_saber2_mmu_sub_block_leaf_info_t 1203 _soc_saber2_mmu_sb_thdi_parity_info [] = { 1204 /* MMU_THDI_INTR */ 1205 { 0x0010, INVALIDm, "THDI_INTR_4", 1206 THDI_INTR_4f, THDI_INTR_4_DISINTf, 1207 INVALIDf, INVALIDr, INVALIDf, 1208 INVALIDr, INVALIDf}, 1209 1210 { 0x0008, INVALIDm, "THDI_INTR_3", 1211 THDI_INTR_3f, THDI_INTR_3_DISINTf, 1212 INVALIDf, INVALIDr, INVALIDf, 1213 INVALIDr, INVALIDf}, 1214 1215 { 0x0004, INVALIDm, "THDI_INTR_2", 1216 THDI_INTR_2f, THDI_INTR_2_DISINTf, 1217 INVALIDf, INVALIDr, INVALIDf, 1218 INVALIDr, INVALIDf}, 1219 1220 { 0x0002, INVALIDm, "THDI_INTR_1", 1221 THDI_INTR_1f, THDI_INTR_1_DISINTf, 1222 INVALIDf, INVALIDr, INVALIDf, 1223 INVALIDr, INVALIDf}, 1224 1225 { 0x0001, INVALIDm, "THDI_INTR_0", 1226 THDI_INTR_0f, THDI_INTR_0_DISINTf, 1227 INVALIDf, INVALIDr, INVALIDf, 1228 INVALIDr, INVALIDf}, 1229 1230 { 0 } /* table terminator */ 1231 1232 }; 1233 1234 STATIC _soc_saber2_mmu_sub_block_leaf_info_t 1235 _soc_saber2_mmu_sb_ite_cfg_parity_info [] = { 1236 /* MMU_ITE_CFG_ECC_ERROR_0 */ 1237 { 0x0800, INVALIDm, "lTE CFG SOP_CONTROL_ECC_0_CORRECTED_ERROR", 1238 SOP_CONTROL_ECC_0_CORRECTED_ERRORf, SOP_CONTROL_ECC_0_CORRECTED_ERROR_DISINTf, 1239 INVALIDf, INVALIDr, INVALIDf, 1240 INVALIDr, INVALIDf}, 1241 { 0x0400, INVALIDm, "ITE CFG SOP_CONTROL_ECC_0_UNCORRECTED_ERROR", 1242 SOP_CONTROL_ECC_0_UNCORRECTED_ERRORf, SOP_CONTROL_ECC_0_UNCORRECTED_ERROR_DISINTf, 1243 INVALIDf, INVALIDr, INVALIDf, 1244 INVALIDr, INVALIDf}, 1245 1246 { 0x0200, MMU_ITE_PACKET_PTR_STOREm, "", 1247 PACKET_PTR_STORE_CORRECTED_ERRORf, PACKET_PTR_STORE_FORCE_CORRECTED_ERROR_DISINTf, 1248 PARITYf, MMU_ITE_CFG_ECC_DEBUG_0r, PACKET_PTR_STORE_ENABLE_ECCf, 1249 MMU_ITE_CFG_ECC_STATUS_1r, PACKET_PTR_STORE_ECC_ERROR_ADDRESSf}, 1250 { 0x0100, MMU_ITE_PACKET_PTR_STOREm, "", 1251 PACKET_PTR_STORE_UNCORRECTED_ERRORf, PACKET_PTR_STORE_FORCE_UNCORRECTED_ERROR_DISINTf, 1252 ECCf, MMU_ITE_CFG_ECC_DEBUG_0r, PACKET_PTR_STORE_ENABLE_ECCf, 1253 MMU_ITE_CFG_ECC_STATUS_1r, PACKET_PTR_STORE_ECC_ERROR_ADDRESSf}, 1254 1255 { 0x0080, INVALIDm, "ITE_WORK_QUEUE_CORRECTED_ERROR", 1256 ITE_WORK_QUEUE_CORRECTED_ERRORf, ITE_WORK_QUEUE_FORCE_CORRECTED_ERROR_DISINTf, 1257 INVALIDf, INVALIDr, INVALIDf, 1258 INVALIDr, INVALIDf}, 1259 { 0x0040, INVALIDm, "ITE_WORK_QUEUE_UNCORRECTED_ERROR", 1260 ITE_WORK_QUEUE_UNCORRECTED_ERRORf, ITE_WORK_QUEUE_FORCE_UNCORRECTED_ERROR_DISINTf, 1261 INVALIDf, INVALIDr, INVALIDf, 1262 INVALIDr, INVALIDf}, 1263 1264 { 0x0020, INVALIDm, "ITE_CTRL_CORRECTED_ERROR", 1265 ITE_CTRL_CORRECTED_ERRORf, ITE_CTRL_CORRECTED_ERROR_DISINTf, 1266 INVALIDf, INVALIDr, INVALIDf, 1267 INVALIDr, INVALIDf}, 1268 { 0x0010, INVALIDm, "ITE_CTRL_UNCORRECTED_ERROR", 1269 ITE_CTRL_UNCORRECTED_ERRORf, ITE_CTRL_UNCORRECTED_ERROR_DISINTf, 1270 INVALIDf, INVALIDr, INVALIDf, 1271 INVALIDr, INVALIDf}, 1272 1273 { 0x0008, MMU_ITE_QMGR_FLLm, "", 1274 ITE_QMGR_FLL_CORRECTED_ERRORf, ITE_QMGR_FLL_FORCE_CORRECTED_ERROR_DISINTf, 1275 PARITYf, MMU_ITE_CFG_ECC_DEBUG_0r, ITE_QMGR_FLL_ENABLE_ECCf, 1276 MMU_ITE_CFG_ECC_STATUS_0r, ITE_QMGR_FLL_ECC_ERROR_ADDRESSf}, 1277 { 0x0004, MMU_ITE_QMGR_FLLm, "", 1278 ITE_QMGR_FLL_UNCORRECTED_ERRORf, ITE_QMGR_FLL_FORCE_UNCORRECTED_ERROR_DISINTf, 1279 ECCf, MMU_ITE_CFG_ECC_DEBUG_0r, ITE_QMGR_FLL_ENABLE_ECCf, 1280 MMU_ITE_CFG_ECC_STATUS_0r, ITE_QMGR_FLL_ECC_ERROR_ADDRESSf}, 1281 1282 { 0x0002, MMU_ITE_QMGR_QLLm, "", 1283 ITE_QMGR_QLL_CORRECTED_ERRORf, ITE_QMGR_QLL_CORRECTED_ERROR_DISINTf, 1284 PARITYf, MMU_ITE_CFG_ECC_DEBUG_0r, ITE_QMGR_QLL_ENABLE_ECCf, 1285 MMU_ITE_CFG_ECC_STATUS_0r, ITE_QMGR_QLL_ECC_ERROR_ADDRESSf}, 1286 { 0x0001, MMU_ITE_QMGR_QLLm, "", 1287 ITE_QMGR_QLL_UNCORRECTED_ERRORf, ITE_QMGR_QLL_UNCORRECTED_ERROR_DISINTf, 1288 ECCf, MMU_ITE_CFG_ECC_DEBUG_0r, ITE_QMGR_QLL_ENABLE_ECCf, 1289 MMU_ITE_CFG_ECC_STATUS_0r, ITE_QMGR_QLL_ECC_ERROR_ADDRESSf}, 1290 1291 { 0 } /* table terminator */ 1292 1293 }; 1294 1295 STATIC _soc_saber2_mmu_sub_block_leaf_info_t 1296 _soc_saber2_mmu_sb_inti_1_parity_info [] = { 1297 /* ST_TRANS_TBL_ECC_ERR1r */ 1298 { 0x0001, INVALIDm, "INTI 1 BIT ECC ERROR", 1299 ERRf, ENABLE_1B_ERR_INTf, 1300 INVALIDf, INVALIDr, INVALIDf, 1301 INVALIDr, INVALIDf}, 1302 1303 { 0 } /* table terminator */ 1304 1305 }; 1306 1307 STATIC _soc_saber2_mmu_sub_block_leaf_info_t 1308 _soc_saber2_mmu_sb_inti_2_parity_info [] = { 1309 /* ST_TRANS_TBL_ECC_ERR2r */ 1310 { 0x0001, INVALIDm, "INTI 2 BIT ECC ERROR", 1311 ERRf, ENABLE_2B_ERR_INTf, 1312 INVALIDf, INVALIDr, INVALIDf, 1313 INVALIDr, INVALIDf}, 1314 1315 { 0 } /* table terminator */ 1316 1317 }; 1318 1319 STATIC _soc_saber2_mmu_sub_block_leaf_info_t 1320 _soc_saber2_mmu_sb_mem1_parity_info [] = { 1321 /* CLINK_ERROR */ 1322 { 0x0008, INVALIDm, "MEM1 CLINKE_CORRECTED_ERROR", 1323 CLINKE_CORRECTED_ERRORf, CLINKE_CORRECTED_ERROR_DISINTf, 1324 INVALIDf, INVALIDr, INVALIDf, 1325 INVALIDr, INVALIDf}, 1326 { 0x0004, INVALIDm, "MEM1 CLINKE_UNCORRECTED_ERROR", 1327 CLINKE_UNCORRECTED_ERRORf, CLINKE_UNCORRECTED_ERROR_DISINTf, 1328 INVALIDf, INVALIDr, INVALIDf, 1329 INVALIDr, INVALIDf}, 1330 1331 1332 { 0x0002, INVALIDm, "MEM1 CLINKI_CORRECTED_ERROR", 1333 CLINKI_CORRECTED_ERRORf, CLINKI_CORRECTED_ERROR_DISINTf, 1334 INVALIDf, INVALIDr, INVALIDf, 1335 INVALIDr, INVALIDf}, 1336 { 0x0001, INVALIDm, "MEM1 CLINKI_UNCORRECTED_ERROR", 1337 CLINKI_UNCORRECTED_ERRORf, CLINKI_UNCORRECTED_ERROR_DISINTf, 1338 INVALIDf, INVALIDr, INVALIDf, 1339 INVALIDr, INVALIDf}, 1340 1341 { 0 } /* table terminator */ 1342 1343 }; 1344 1345 1346 STATIC 1347 _soc_saber2_mmu_sub_block_leaf_info_t _soc_saber2_mmu_sb_info2_1_parity_info[] = { 1348 /* CHFC_TC2PRI_TBL_ECC_ERR1 1bit */ 1349 { 0x1, MMU_INTFO_TC2PRI_MAPPINGm, "", 1350 ERRf, ERR1_MASKf, 1351 PARITYf, CHFC_TC2PRI_TBL_ECC_CONFIGr, ECC_ENf, 1352 CHFC_TC2PRI_TBL_ECC_ERR1r, ENTRY_IDXf}, 1353 1354 { 0 } /* table terminator */ 1355 1356 }; 1357 1358 STATIC 1359 _soc_saber2_mmu_sub_block_leaf_info_t _soc_saber2_mmu_sb_info2_2_parity_info[] = { 1360 /* CHFC_TC2PRI_TBL_ECC_ERR2 2bits*/ 1361 { 0x1, MMU_INTFO_TC2PRI_MAPPINGm, "", 1362 ERRf, ERR2_MASKf, 1363 ECCf, CHFC_TC2PRI_TBL_ECC_CONFIGr, ECC_ENf, 1364 CHFC_TC2PRI_TBL_ECC_ERR2r, ENTRY_IDXf}, 1365 1366 { 0 } /* table terminator */ 1367 1368 }; 1369 1370 1371 STATIC 1372 _soc_saber2_mmu_sub_block_leaf_info_t _soc_saber2_mmu_sb_rde_parity_info[] = { 1373 /* RDE_SER_STATUS */ 1374 { 0xFF00, INVALIDm, "MMU RDE ECC_1B_BITMAP", 1375 ECC_1B_BITMAPf, ECC_1B_MASKf, 1376 INVALIDf, INVALIDr, INVALIDf, 1377 INVALIDr, INVALIDf}, 1378 { 0xFF, INVALIDm, "MMU RDE ECC_2B_BITMAP", 1379 ECC_2B_BITMAPf, ECC_2B_MASKf, 1380 INVALIDf, INVALIDr, INVALIDf, 1381 INVALIDr, INVALIDf}, 1382 1383 { 0 } /* table terminator */ 1384 1385 }; 1386 1387 STATIC 1388 _soc_saber2_mmu_sub_block_leaf_info_t _soc_saber2_mmu_sb_adm_parity_info[] = { 1389 /* MMU_ADM_ECC_ERROR_0 */ 1390 { 0x0008, MMU_ADM_SRC_CTXT_DBm, "", 1391 SRC_CTXT_DB_CORRECTED_ERRORf, SRC_CTXT_DB_CORRECTED_ERROR_DISINTf, 1392 PARITYf, MMU_ADM_ECC_DEBUG_0r, SRC_CTXT_DB_ENABLE_ECCf, 1393 MMU_ADM_ECC_STATUS_0r, SRC_CTXT_DB_ECC_ERROR_ADDRESSf}, 1394 { 0x0004, MMU_ADM_SRC_CTXT_DBm, "", 1395 SRC_CTXT_DB_UNCORRECTED_ERRORf, SRC_CTXT_DB_UNCORRECTED_ERROR_ERROR_DISINTf, 1396 ECCf, MMU_ADM_ECC_DEBUG_0r, SRC_CTXT_DB_ENABLE_ECCf, 1397 MMU_ADM_ECC_STATUS_0r, SRC_CTXT_DB_ECC_ERROR_ADDRESSf}, 1398 1399 { 0x0002, MMU_ADM_QUEUE_DBm, "", 1400 QUEUE_DB_CORRECTED_ERRORf, QUEUE_DB_CORRECTED_ERROR_DISINTf, 1401 PARITYf, MMU_ADM_ECC_DEBUG_0r, QUEUE_DB_ENABLE_ECCf, 1402 MMU_ADM_ECC_STATUS_0r, QUEUE_DB_ECC_ERROR_ADDRESSf}, 1403 { 0x0001, MMU_ADM_QUEUE_DBm, "", 1404 QUEUE_DB_UNCORRECTED_ERRORf, QUEUE_DB_UNCORRECTED_ERROR_DISINTf, 1405 ECCf, MMU_ADM_ECC_DEBUG_0r, QUEUE_DB_ENABLE_ECCf, 1406 MMU_ADM_ECC_STATUS_0r, QUEUE_DB_ECC_ERROR_ADDRESSf}, 1407 1408 { 0 } /* table terminator */ 1409 1410 }; 1411 1412 STATIC 1413 _soc_saber2_mmu_sub_block_leaf_info_t _soc_saber2_mmu_sb_ipctr_parity_info[] = { 1414 /* MMU_IPCTR_ECC_ERROR_0 */ 1415 { 0x0020, MMU_IPCTR_CTXT_COUNTER_0m, "", 1416 CTXT_COUNTER_0_CORRECTED_ERRORf, CTXT_COUNTER_0_CORRECTED_ERROR_DISINTf, 1417 PARITYf, MMU_IPCTR_ECC_DEBUG_0r, CTXT_COUNTER_0_ENABLE_ECCf, 1418 MMU_IPCTR_ECC_STATUS_0r, CTXT_COUNTER_0_ECC_ERROR_ADDRESSf}, 1419 { 0x0010, MMU_IPCTR_CTXT_COUNTER_0m, "", 1420 CTXT_COUNTER_0_UNCORRECTED_ERRORf, CTXT_COUNTER_0_UNCORRECTED_ERROR_DISINTf, 1421 ECCf, MMU_IPCTR_ECC_DEBUG_0r, CTXT_COUNTER_0_ENABLE_ECCf, 1422 MMU_IPCTR_ECC_STATUS_0r, CTXT_COUNTER_0_ECC_ERROR_ADDRESSf}, 1423 1424 { 0x0008, MMU_IPCTR_PG_COUNTER_1m, "", 1425 PG_COUNTER_1_CORRECTED_ERRORf, PG_COUNTER_1_CORRECTED_ERROR_DISINTf, 1426 PARITYf, MMU_IPCTR_ECC_DEBUG_0r, PG_COUNTER_1_ENABLE_ECCf, 1427 MMU_IPCTR_ECC_STATUS_0r, PG_COUNTER_1_ECC_ERROR_ADDRESSf}, 1428 { 0x0004, MMU_IPCTR_PG_COUNTER_1m, "", 1429 PG_COUNTER_1_UNCORRECTED_ERRORf, PG_COUNTER_1_UNCORRECTED_ERROR_DISINTf, 1430 ECCf, MMU_IPCTR_ECC_DEBUG_0r, PG_COUNTER_1_ENABLE_ECCf, 1431 MMU_IPCTR_ECC_STATUS_0r, PG_COUNTER_1_ECC_ERROR_ADDRESSf}, 1432 1433 { 0x0002, MMU_IPCTR_PG_COUNTER_0m, "", 1434 PG_COUNTER_0_CORRECTED_ERRORf, PG_COUNTER_0_CORRECTED_ERROR_DISINTf, 1435 PARITYf, MMU_IPCTR_ECC_DEBUG_0r, PG_COUNTER_0_ENABLE_ECCf, 1436 MMU_IPCTR_ECC_STATUS_0r, PG_COUNTER_0_ECC_ERROR_ADDRESSf}, 1437 { 0x0001, MMU_IPCTR_PG_COUNTER_0m, "", 1438 PG_COUNTER_0_UNCORRECTED_ERRORf, PG_COUNTER_0_UNCORRECTED_ERROR_DISINTf, 1439 ECCf, MMU_IPCTR_ECC_DEBUG_0r, PG_COUNTER_0_ENABLE_ECCf, 1440 MMU_IPCTR_ECC_STATUS_0r, PG_COUNTER_0_ECC_ERROR_ADDRESSf}, 1441 1442 { 0 } /* table terminator */ 1443 1444 }; 1445 1446 1447 STATIC 1448 _soc_saber2_mmu_sub_block_one_level_t _soc_saber2_mmu_sub_blocks_type_1[] = { 1449 1450 { 0x00000004, 1451 _SOC_SABER2_MMU_SUBBLOCK_LLS, 1452 LLS_INTR_DISINTf, 1453 LLS_INTRf, 1454 LLS_L0_ECC_ERROR1_MASKr, 1455 LLS_L0_ECC_ERROR1r, 1456 _soc_saber2_mmu_sb_lls_l0_parity_info}, 1457 1458 { 0x00000004, 1459 _SOC_SABER2_MMU_SUBBLOCK_LLS, 1460 LLS_INTR_DISINTf, 1461 LLS_INTRf, 1462 LLS_L1_ECC_ERROR1_MASKr, 1463 LLS_L1_ECC_ERROR1r, 1464 _soc_saber2_mmu_sb_lls_l1_parity_info}, 1465 1466 1467 { 0x00000004, 1468 _SOC_SABER2_MMU_SUBBLOCK_LLS, 1469 LLS_INTR_DISINTf, 1470 LLS_INTRf, 1471 LLS_L2_ECC_ERROR1_MASKr, 1472 LLS_L2_ECC_ERROR1r, 1473 _soc_saber2_mmu_sb_lls_l2_parity_info}, 1474 1475 { 0x00000004, 1476 _SOC_SABER2_MMU_SUBBLOCK_LLS, 1477 LLS_INTR_DISINTf, 1478 LLS_INTRf, 1479 LLS_PORT_ECC_ERROR_MASKr, 1480 LLS_PORT_ECC_ERRORr, 1481 _soc_saber2_mmu_sb_lls_port_parity_info}, 1482 1483 { 0x00000004, 1484 _SOC_SABER2_MMU_SUBBLOCK_LLS, 1485 LLS_INTR_DISINTf, 1486 LLS_INTRf, 1487 LLS_MISC_ECC_ERROR1_MASKr, 1488 LLS_MISC_ECC_ERROR1r, 1489 _soc_saber2_mmu_sb_lls_misc_parity_info}, 1490 1491 1492 { 0x00000008, 1493 _SOC_SABER2_MMU_SUBBLOCK_AGING_INT, 1494 AGING_INTR_DISINTf, 1495 AGING_INTRf, 1496 AGING_ERROR_MASK_INTr, 1497 AGING_ERROR_INTr, 1498 _soc_saber2_mmu_sb_aging_int_parity_info}, 1499 1500 { 0x00000008, 1501 _SOC_SABER2_MMU_SUBBLOCK_AGING_EXT, 1502 AGING_INTR_DISINTf, 1503 AGING_INTRf, 1504 AGING_ERROR_MASK_EXTr, 1505 AGING_ERROR_EXTr, 1506 _soc_saber2_mmu_sb_aging_ext_parity_info}, 1507 1508 { 0x00000010, 1509 _SOC_SABER2_MMU_SUBBLOCK_CCP, 1510 CCP_INTR_DISINTf, 1511 CCP_INTRf, 1512 CCP_ERROR_MASKr, 1513 CCP_ERRORr, 1514 _soc_saber2_mmu_sb_ccp_parity_info}, 1515 1516 { 0x00000020, 1517 _SOC_SABER2_MMU_SUBBLOCK_CFAPI, 1518 CFAP_INTR_DISINTf, 1519 CFAP_INTRf, 1520 CFAPI_ERROR_MASKr, 1521 CFAPI_ECC_ERRORr, 1522 _soc_saber2_mmu_sb_cfapi_parity_info}, 1523 1524 { 0x00000020, 1525 _SOC_SABER2_MMU_SUBBLOCK_CFAPI, 1526 CFAP_INTR_DISINTf, 1527 CFAP_INTRf, 1528 CFAPE_ERROR_MASKr, 1529 CFAPE_ECC_ERRORr, 1530 _soc_saber2_mmu_sb_cfape_parity_info}, 1531 1532 { 0x00000040, 1533 _SOC_SABER2_MMU_SUBBLOCK_CTR, 1534 CTR_INTR_DISINTf, 1535 CTR_INTRf, 1536 CTR_ERROR_MASKr, 1537 CTR_ERRORr, 1538 _soc_saber2_mmu_sb_ctr_parity_info}, 1539 1540 { 0x00000200, 1541 _SOC_SABER2_MMU_SUBBLOCK_RQE_EXTQ, 1542 RQE_INTR_DISINTf, 1543 RQE_INTRf, 1544 RQE_SER_MASKr, 1545 RQE_SER_STATUSr, 1546 _soc_saber2_mmu_sb_rqe_parity_info}, 1547 1548 { 0x00000400, 1549 _SOC_SABER2_MMU_SUBBLOCK_THDO_STATUS1, 1550 THDO_INTR_DISINTf, 1551 THDO_INTRf, 1552 THDO_PARITY_ERROR_MASK1r, 1553 THDO_PARITY_ERROR_STATUS1r, 1554 _soc_saber2_mmu_sb_thdo_stat1_parity_info}, 1555 1556 { 0x00000400, 1557 _SOC_SABER2_MMU_SUBBLOCK_THDO_STATUS2, 1558 THDO_INTR_DISINTf, 1559 THDO_INTRf, 1560 THDO_PARITY_ERROR_MASK2r, 1561 THDO_PARITY_ERROR_STATUS2r, 1562 _soc_saber2_mmu_sb_thdo_stat2_parity_info}, 1563 1564 { 0x00000800, 1565 _SOC_SABER2_MMU_SUBBLOCK_WRED, 1566 WRED_INTR_DISINTf, 1567 WRED_INTRf, 1568 WRED_PARITY_ERROR_MASKr, 1569 WRED_PARITY_ERROR_BITMAPr, 1570 _soc_saber2_mmu_sb_wred_parity_info}, 1571 1572 { 0x00000800, 1573 _SOC_SABER2_MMU_SUBBLOCK_WRED, 1574 WRED_INTR_DISINTf, 1575 WRED_INTRf, 1576 WRED_PROFILE_PARITY_ERROR_MASKr, 1577 WRED_PROFILE_PARITY_ERROR_BITMAPr, 1578 _soc_saber2_mmu_sb_wred_profile_parity_info}, 1579 1580 { 0x00001000, 1581 _SOC_SABER2_MMU_SUBBLOCK_CI0, 1582 CI0_INTR_DISINTf, 1583 CI0_INTRf, 1584 CI_ERROR_MASKr, 1585 CI_ERRORr, 1586 _soc_saber2_mmu_sb_ci_parity_info}, 1587 1588 { 0x00002000, 1589 _SOC_SABER2_MMU_SUBBLOCK_CI0, 1590 CI1_INTR_DISINTf, 1591 CI1_INTRf, 1592 CI_ERROR_MASKr, 1593 CI_ERRORr, 1594 _soc_saber2_mmu_sb_ci_parity_info}, 1595 1596 { 0x00004000, 1597 _SOC_SABER2_MMU_SUBBLOCK_ENQ_CFG, 1598 ENQ_INTR_DISINTf, 1599 ENQ_INTRf, 1600 MMU_ENQ_CFG_ECC_ERROR_0_MASKr, 1601 MMU_ENQ_CFG_ECC_ERROR_0r, 1602 _soc_saber2_mmu_sb_enq_cfg_parity_info}, 1603 1604 { 0x00004000, 1605 _SOC_SABER2_MMU_SUBBLOCK_ENQ_FAP, 1606 ENQ_INTR_DISINTf, 1607 ENQ_INTRf, 1608 MMU_ENQ_FAP_ECC_ERROR_0_MASKr, 1609 MMU_ENQ_FAP_ECC_ERROR_0r, 1610 _soc_saber2_mmu_sb_enq_fap_parity_info}, 1611 1612 { 0x00008000, 1613 _SOC_SABER2_MMU_SUBBLOCK_THDI, 1614 THDI_INTR_DISINTf, 1615 THDI_INTRf, 1616 MMU_THDI_INTR_MASKr, 1617 MMU_THDI_INTRr, 1618 _soc_saber2_mmu_sb_thdi_parity_info}, 1619 1620 { 0x00010000, 1621 _SOC_SABER2_MMU_SUBBLOCK_ITE_CFG, 1622 ITE_INTR_DISINTf, 1623 ITE_INTRf, 1624 MMU_ITE_CFG_ECC_ERROR_0_MASKr, 1625 MMU_ITE_CFG_ECC_ERROR_0r, 1626 _soc_saber2_mmu_sb_ite_cfg_parity_info}, 1627 1628 /* 0x00020000 1629 MMU_E2EFC_ERROR_0 is not ECC/Parity error 1630 e.g. E2EFC_INT_CNT_UNDERRUN /OVERFLOW 1631 */ 1632 1633 { 0x00040000, 1634 _SOC_SABER2_MMU_SUBBLOCK_INTFI_ECC, 1635 INTF1_INTR_DISINTf, 1636 INTFI_INTRf, 1637 INTFI_ECC_INTR_MASKr, 1638 ST_TRANS_TBL_ECC_ERR1r, 1639 _soc_saber2_mmu_sb_inti_1_parity_info}, 1640 1641 { 0x00040000, 1642 _SOC_SABER2_MMU_SUBBLOCK_INTFI_ECC, 1643 INTF1_INTR_DISINTf, 1644 INTFI_INTRf, 1645 INTFI_ECC_INTR_MASKr, 1646 ST_TRANS_TBL_ECC_ERR2r, 1647 _soc_saber2_mmu_sb_inti_2_parity_info}, 1648 1649 { 0x00080000, 1650 _SOC_SABER2_MMU_SUBBLOCK_MEM1, 1651 MEM1_INTR_DISINTf, 1652 MEM1_INTRf, 1653 CLINK_ERROR_MASKr, 1654 CLINK_ERRORr, 1655 _soc_saber2_mmu_sb_mem1_parity_info }, 1656 1657 { 0x00100000, 1658 _SOC_SABER2_MMU_SUBBLOCK_INFO2, 1659 INFO2_INTR_DISINTf, 1660 INFO2_INTRf, 1661 CHFC_TC2PRI_TBL_ECC_CONFIGr, 1662 CHFC_TC2PRI_TBL_ECC_ERR1r, 1663 _soc_saber2_mmu_sb_info2_1_parity_info }, 1664 1665 { 0x00100000, 1666 _SOC_SABER2_MMU_SUBBLOCK_INFO2, 1667 INFO2_INTR_DISINTf, 1668 INFO2_INTRf, 1669 CHFC_TC2PRI_TBL_ECC_CONFIGr, 1670 CHFC_TC2PRI_TBL_ECC_ERR2r, 1671 _soc_saber2_mmu_sb_info2_2_parity_info }, 1672 1673 1674 { 0x00200000, 1675 _SOC_SABER2_MMU_SUBBLOCK_RDE, 1676 RDE_INTR_DISINTf, 1677 RDE_INTRf, 1678 RDE_SER_MASKr, 1679 RDE_SER_STATUSr, 1680 _soc_saber2_mmu_sb_rde_parity_info }, 1681 1682 { 0x00400000, 1683 _SOC_SABER2_MMU_SUBBLOCK_ADM, 1684 ADM_INTR_DISINTf, 1685 ADM_INTRf, 1686 MMU_ADM_ECC_ERROR_0_MASKr, 1687 MMU_ADM_ECC_ERROR_0r, 1688 _soc_saber2_mmu_sb_adm_parity_info }, 1689 1690 { 0x00800000, 1691 _SOC_SABER2_MMU_SUBBLOCK_IPCTR, 1692 IPCTR_INTR_DISINTf, 1693 IPCTR_INTRf, 1694 MMU_IPCTR_ECC_ERROR_0_MASKr, 1695 MMU_IPCTR_ECC_ERROR_0r, 1696 _soc_saber2_mmu_sb_ipctr_parity_info }, 1697 1698 1699 { 0 } /* table terminator */ 1700 1701 }; 1702 1703 STATIC _soc_saber2_mmu_sub_block_leaf_info_t 1704 _soc_saber2_mmu_sb_toq1_parity_info [] = { 1705 1706 /* TOQ_ERROR1 */ 1707 { 0x20000, MMU_TOQ_EOPE_TBLm, "", 1708 EOPE_TBL_CORRECTED_ERRORf, EOPE_TBL_CORRECTED_ERROR_DISINTf, 1709 PARITYf, TOQ_ECC_DEBUGr, EOPE_TBL_ENABLE_ECCf, 1710 MMU_TOQ_EOPE_ECC_STATUSr, ECC_ERROR_ADDRESSf}, 1711 { 0x10000, MMU_TOQ_EOPE_TBLm, "", 1712 EOPE_TBL_UNCORRECTED_ERRORf, EOPE_TBL_UNCORRECTED_ERROR_DISINTf, 1713 ECCf, TOQ_ECC_DEBUGr, EOPE_TBL_ENABLE_ECCf, 1714 MMU_TOQ_EOPE_ECC_STATUSr, ECC_ERROR_ADDRESSf}, 1715 1716 { 0x8000, MMU_REPL_MAP_TBLm, "", 1717 REPL_MAP_TBL_CORRECTED_ERRORf, REPL_MAP_TBL_CORRECTED_ERROR_DISINTf, 1718 PARITYf, TOQ_ECC_DEBUGr, REPL_MAP_TBL_ENABLE_ECCf, 1719 MMU_REPL_MAP_TBL_ECC_STATUSr, ECC_ERROR_ADDRESSf}, 1720 { 0x4000, MMU_REPL_MAP_TBLm, "", 1721 REPL_MAP_TBL_UNCORRECTED_ERRORf, REPL_MAP_TBL_UNCORRECTED_ERROR_DISINTf, 1722 ECCf, TOQ_ECC_DEBUGr, REPL_MAP_TBL_ENABLE_ECCf, 1723 MMU_REPL_MAP_TBL_ECC_STATUSr, ECC_ERROR_ADDRESSf}, 1724 1725 { 0x2000, MMU_REPL_STATE_TBLm, "", 1726 REPL_STATE_TBL_CORRECTED_ERRORf, REPL_STATE_TBL_CORRECTED_ERROR_DISINTf, 1727 PARITYf, TOQ_ECC_DEBUGr, REPL_STATE_TBL_ENABLE_ECCf, 1728 MMU_REPL_STATE_TBL_ECC_STATUSr, ECC_ERROR_ADDRESSf}, 1729 { 0x1000, MMU_REPL_STATE_TBLm, "", 1730 REPL_STATE_TBL_UNCORRECTED_ERRORf, REPL_STATE_TBL_UNCORRECTED_ERROR_DISINTf, 1731 ECCf, TOQ_ECC_DEBUGr, REPL_STATE_TBL_ENABLE_ECCf, 1732 MMU_REPL_STATE_TBL_ECC_STATUSr, ECC_ERROR_ADDRESSf}, 1733 1734 { 0x0800, INVALIDm, "MMU PORT_STATE_CORRECTED_ERROR", 1735 PORT_STATE_CORRECTED_ERRORf, PORT_STATE_CORRECTED_ERROR_DISINTf, 1736 INVALIDf, INVALIDr, INVALIDf, 1737 INVALIDr, INVALIDf}, 1738 { 0x0400, INVALIDm, "MMU PORT_STATE_UNCORRECTED_ERROR", 1739 PORT_STATE_UNCORRECTED_ERRORf, PORT_STATE_UNCORRECTED_ERROR_DISINTf, 1740 INVALIDf, INVALIDr, INVALIDf, 1741 INVALIDr, INVALIDf}, 1742 1743 { 0x0200, INVALIDm, "MMU RQE_FIFO_CORRECTED_ERROR", 1744 RQE_FIFO_CORRECTED_ERRORf, RQE_FIFO_CORRECTED_ERROR_DISINTf, 1745 INVALIDf, INVALIDr, INVALIDf, 1746 INVALIDr, INVALIDf}, 1747 { 0x0100, INVALIDm, "MMU RQE_FIFO_UNCORRECTED_ERROR", 1748 RQE_FIFO_UNCORRECTED_ERRORf, RQE_FIFO_UNCORRECTED_ERROR_DISINTf, 1749 INVALIDf, INVALIDr, INVALIDf, 1750 INVALIDr, INVALIDf}, 1751 1752 { 0x0080, INVALIDm, "MMU REPL_GRP_TBL_CORRECTED_ERROR", 1753 REPL_GRP_TBL_CORRECTED_ERRORf, REPL_GRP_TBL_CORRECTED_ERROR_DISINTf, 1754 INVALIDf, INVALIDr, INVALIDf, 1755 INVALIDr, INVALIDf}, 1756 { 0x0040, INVALIDm, "MMU REPL_GRP_TBL_UNCORRECTED_ERROR", 1757 REPL_GRP_TBL_UNCORRECTED_ERRORf, REPL_GRP_TBL_UNCORRECTED_ERROR_DISINTf, 1758 INVALIDf, INVALIDr, INVALIDf, 1759 INVALIDr, INVALIDf}, 1760 1761 { 0x0020, MMU_REPL_HEAD_TBLm, "", 1762 REPL_HEAD_TBL_CORRECTED_ERRORf, REPL_HEAD_TBL_CORRECTED_ERROR_DISINTf, 1763 PARITYf, TOQ_ECC_DEBUGr, REPL_HEAD_TBL_ENABLE_ECCf, 1764 MMU_REPL_HEAD_TBL_ECC_STATUSr, ECC_ERROR_ADDRESSf}, 1765 { 0x0010, MMU_REPL_HEAD_TBLm, "", 1766 REPL_HEAD_TBL_UNCORRECTED_ERRORf, REPL_HEAD_TBL_UNCORRECTED_ERROR_DISINTf, 1767 ECCf, TOQ_ECC_DEBUGr, REPL_HEAD_TBL_ENABLE_ECCf, 1768 MMU_REPL_HEAD_TBL_ECC_STATUSr, ECC_ERROR_ADDRESSf}, 1769 1770 { 0x0008, MMU_REPL_LIST_TBLm, "", 1771 REPL_LIST_TBL_CORRECTED_ERRORf, REPL_LIST_TBL_CORRECTED_ERROR_DISINTf, 1772 PARITYf, TOQ_ECC_DEBUGr, REPL_LIST_TBL_ENABLE_ECCf, 1773 MMU_REPL_LIST_TBL_ECC_STATUSr, ECC_ERROR_ADDRESSf}, 1774 { 0x0004, MMU_REPL_LIST_TBLm, "", 1775 REPL_LIST_TBL_UNCORRECTED_ERRORf, REPL_LIST_TBL_UNCORRECTED_ERROR_DISINTf, 1776 ECCf, TOQ_ECC_DEBUGr, REPL_LIST_TBL_ENABLE_ECCf, 1777 MMU_REPL_LIST_TBL_ECC_STATUSr, ECC_ERROR_ADDRESSf}, 1778 1779 { 0x0002, INVALIDm, "MMU TOQ_STATE_CORRECTED_ERROR", 1780 TOQ_STATE_CORRECTED_ERRORf, TOQ_STATE_CORRECTED_ERROR_DISINTf, 1781 INVALIDf, INVALIDr, INVALIDf, 1782 INVALIDr, INVALIDf}, 1783 { 0x0001, INVALIDm, "MMU TOQ_STATE_UNCORRECTED_ERROR", 1784 TOQ_STATE_UNCORRECTED_ERRORf, TOQ_STATE_UNCORRECTED_ERROR_DISINTf, 1785 INVALIDf, INVALIDr, INVALIDf, 1786 INVALIDr, INVALIDf}, 1787 1788 { 0 } /* table terminator */ 1789 1790 }; 1791 1792 STATIC _soc_saber2_mmu_sub_block_leaf_info_t 1793 _soc_saber2_mmu_sb_toq2_parity_info [] = { 1794 /* TOQ_ERROR2 */ 1795 { 0x0800, INVALIDm, "MMU REPL_HEAD_WRAP", 1796 REPL_HEAD_WRAPf, REPL_HEAD_WRAP_DISINTf, 1797 INVALIDf, INVALIDr, INVALIDf, 1798 INVALIDr, INVALIDf}, 1799 1800 { 0x0400, INVALIDm, "MMU PQE_CREDIT_UNDERRUN", 1801 PQE_CREDIT_UNDERRUNf, PQE_CREDIT_UNDERRUN_DISINTf, 1802 INVALIDf, INVALIDr, INVALIDf, 1803 INVALIDr, INVALIDf}, 1804 1805 { 0x0200, INVALIDm, "MMU PQE_CREDIT_OVERFLOW", 1806 PQE_CREDIT_OVERFLOWf, PQE_CREDIT_OVERFLOW_DISINTf, 1807 INVALIDf, INVALIDr, INVALIDf, 1808 INVALIDr, INVALIDf}, 1809 1810 { 0x0100, INVALIDm, "MMU FLUSH_COMPLETE", 1811 FLUSH_COMPLETEf, FLUSH_COMPLETE_DISINTf, 1812 INVALIDf, INVALIDr, INVALIDf, 1813 INVALIDr, INVALIDf}, 1814 1815 { 0x0080, INVALIDm, "MMU QDIS_FIFO_OVERFLOW", 1816 QDIS_FIFO_OVERFLOWf, QDIS_FIFO_OVERFLOW_DISINTf, 1817 INVALIDf, INVALIDr, INVALIDf, 1818 INVALIDr, INVALIDf}, 1819 1820 { 0x0040, INVALIDm, "MMU TRACE_DEQ_EVENT", 1821 TRACE_DEQ_EVENTf, TRACE_DEQ_EVENT_DISINTf, 1822 INVALIDf, INVALIDr, INVALIDf, 1823 INVALIDr, INVALIDf}, 1824 1825 { 0x0020, INVALIDm, "MMU TRACE_ENQ_EVENT", 1826 TRACE_ENQ_EVENTf, TRACE_ENQ_EVENT_DISINTf, 1827 INVALIDf, INVALIDr, INVALIDf, 1828 INVALIDr, INVALIDf}, 1829 1830 { 0x0010, INVALIDm, "MMU DEQ_TO_EMPTY_QUEUE_ERROR", 1831 DEQ_TO_EMPTY_QUEUE_ERRORf, DEQ_TO_EMPTY_QUEUE_ERROR_DISINTf, 1832 INVALIDf, INVALIDr, INVALIDf, 1833 INVALIDr, INVALIDf}, 1834 1835 { 0x0008, INVALIDm, "MMU QSTRUCT_EMPTY_ERROR", 1836 QSTRUCT_EMPTY_ERRORf, QSTRUCT_EMPTY_ERROR_DISINTf, 1837 INVALIDf, INVALIDr, INVALIDf, 1838 INVALIDr, INVALIDf}, 1839 1840 { 0x0004, INVALIDm, "MMU QUEUE_OVELOAD_ERROR", 1841 QUEUE_OVELOAD_ERRORf, QUEUE_OVELOAD_ERROR_DISINTf, 1842 INVALIDf, INVALIDr, INVALIDf, 1843 INVALIDr, INVALIDf}, 1844 1845 { 0x0002, INVALIDm, "MMU TDM_VIOLATION_ERROR", 1846 TDM_VIOLATION_ERRORf, TDM_VIOLATION_ERROR_DISINTf, 1847 INVALIDf, INVALIDr, INVALIDf, 1848 INVALIDr, INVALIDf}, 1849 1850 { 0x0001, INVALIDm, "MMU RQE_FIFO_OVERFLOW", 1851 RQE_FIFO_OVERFLOWf, RQE_FIFO_OVERFLOW_DISINTf, 1852 INVALIDf, INVALIDr, INVALIDf, 1853 INVALIDr, INVALIDf}, 1854 { 0 } /* table terminator */ 1855 1856 }; 1857 1858 1859 STATIC 1860 _soc_saber2_mmu_sub_block_internal_info_t 1861 _soc_saber2_mmu_sb_toq_parity_info [] = { 1862 /* TOQ_ERROR2 is not ecc/parity err*/ 1863 { 0x0002, 1864 _SOC_SABER2_MMU_LVL2_SUBBLOCK_TOQ_ERROR_2, 1865 TOQ_ERROR2_DISINTf, 1866 TOQ_ERROR2f, 1867 TOQ_ERROR2_MASKr, 1868 TOQ_ERROR2r, 1869 _soc_saber2_mmu_sb_toq2_parity_info }, 1870 1871 { 0x0001, 1872 _SOC_SABER2_MMU_LVL2_SUBBLOCK_TOQ_ERROR_1, 1873 TOQ_ERROR1_DISINTf, 1874 TOQ_ERROR1_ERRORf, 1875 TOQ_ERROR1_MASKr, 1876 TOQ_ERROR1r, 1877 _soc_saber2_mmu_sb_toq1_parity_info }, 1878 1879 { 0 } /* table terminator */ 1880 1881 }; 1882 1883 STATIC _soc_saber2_mmu_sub_block_leaf_info_t 1884 _soc_saber2_mmu_sb_qstruct_qentry_qblock_nxt_parity_info [] = { 1885 /* QSTRUCT_QBLOCK_NEXT_ERROR_0 */ 1886 { 0x0002, MMU_QSTRUCT_QBLOCK_NEXTm, "", 1887 CORRECTED_ERRORf, CORRECTED_ERROR_DISINTf, 1888 PARITYf, QSTRUCT_QBLOCK_NEXT_ECC_DEBUGr, DB_QSTRUCT_QBLOCK_NEXT_0_ENABLE_ECCf, 1889 QBLOCK_NEXT_MEM_ECC_STATUS_0r, ECC_ERROR_ADDRESSf}, 1890 1891 { 0x0001, MMU_QSTRUCT_QBLOCK_NEXTm, "", 1892 UNCORRECTED_ERRORf, UNCORRECTED_ERROR_DISINTf, 1893 ECCf, QSTRUCT_QBLOCK_NEXT_ECC_DEBUGr, DB_QSTRUCT_QBLOCK_NEXT_0_ENABLE_ECCf, 1894 QBLOCK_NEXT_MEM_ECC_STATUS_0r, ECC_ERROR_ADDRESSf}, 1895 1896 { 0 } /* table terminator */ 1897 1898 }; 1899 1900 STATIC _soc_saber2_mmu_sub_block_leaf_info_t 1901 _soc_saber2_mmu_sb_qstruct_qentry_parity_info [] = { 1902 /* QSTRUCT_QENTRY_ERROR_0 */ 1903 { 0x0002, MMU_QSTRUCT_QENTRYm, "", 1904 CORRECTED_ERRORf, CORRECTED_ERROR_DISINTf, 1905 PARITYf, QSTRUCT_QENTRY_ECC_DEBUGr, DB_QSTRUCT_QENTRY_ENABLE_ECCf, 1906 INVALIDr, INVALIDf}, 1907 1908 { 0x0001, MMU_QSTRUCT_QENTRYm, "", 1909 UNCORRECTED_ERRORf, UNCORRECTED_ERROR_DISINTf, 1910 ECCf, QSTRUCT_QENTRY_ECC_DEBUGr, DB_QSTRUCT_QENTRY_ENABLE_ECCf, 1911 INVALIDr, INVALIDf}, 1912 1913 { 0 } /* table terminator */ 1914 1915 }; 1916 1917 STATIC _soc_saber2_mmu_sub_block_leaf_info_t 1918 _soc_saber2_mmu_sb_qstruct_fap_parity_info [] = { 1919 /* QSTRUCT_FAP_MEM_ERROR */ 1920 /* not ECC error */ 1921 { 0x4000, INVALIDm, "MMU FAP FAP1_VALID_LOW_NO_FULLASSERT_ERROR", 1922 FAP1_VALID_LOW_NO_FULLASSERT_ERRORf, FAP1_VALID_LOW_NO_FULLASSERT_ERROR_DISINTf, 1923 INVALIDf, INVALIDr, INVALIDf, 1924 INVALIDr, INVALIDf}, 1925 1926 { 0x2000, INVALIDm, "MMU FAP FAP0_VALID_LOW_NO_FULLASSERT_ERROR", 1927 FAP0_VALID_LOW_NO_FULLASSERT_ERRORf, FAP0_VALID_LOW_NO_FULLASSERT_ERROR_DISINTf, 1928 INVALIDf, INVALIDr, INVALIDf, 1929 INVALIDr, INVALIDf}, 1930 1931 { 0x1000, INVALIDm, "MMU FAP FAP1_INVALID_PTR_ERROR", 1932 FAP1_INVALID_PTR_ERRORf, FAP1_INVALID_PTR_ERROR_DISINTf, 1933 INVALIDf, INVALIDr, INVALIDf, 1934 INVALIDr, INVALIDf}, 1935 1936 { 0x0800, INVALIDm, "MMU FAP FAP0_INVALID_PTR_ERROR", 1937 FAP0_INVALID_PTR_ERRORf, FAP0_INVALID_PTR_ERROR_DISINTf, 1938 INVALIDf, INVALIDr, INVALIDf, 1939 INVALIDr, INVALIDf}, 1940 1941 { 0x0400, INVALIDm, "MMU FAP FAP1_DUPLICATE_PTR_ERROR", 1942 FAP1_DUPLICATE_PTR_ERRORf, FAP1_DUPLICATE_PTR_ERROR_DISINTf, 1943 INVALIDf, INVALIDr, INVALIDf, 1944 INVALIDr, INVALIDf}, 1945 1946 { 0x0200, INVALIDm, "MMU FAP FAP0_DUPLICATE_PTR_ERROR", 1947 FAP0_DUPLICATE_PTR_ERRORf, FAP0_DUPLICATE_PTR_ERROR_DISINTf, 1948 INVALIDf, INVALIDr, INVALIDf, 1949 INVALIDr, INVALIDf}, 1950 1951 { 0x0100, INVALIDm, "MMU FAP FAP_LOADING_ERROR", 1952 FAP_LOADING_ERRORf, FAP_LOADING_ERROR_DISINTf, 1953 INVALIDf, INVALIDr, INVALIDf, 1954 INVALIDr, INVALIDf}, 1955 1956 /* ECC error */ 1957 1958 { 0x0080, INVALIDm, "MMU FAP CORRECTED_BITMAP_ERROR_1", 1959 CORRECTED_BITMAP_ERROR_1f, CORRECTED_BITMAP_ERROR_1_DISINTf, 1960 INVALIDf, INVALIDr, INVALIDf, 1961 INVALIDr, INVALIDf}, 1962 { 0x0040, INVALIDm, "MMU FAP UNCORRECTED_BITMAP_ERROR_1", 1963 UNCORRECTED_BITMAP_ERROR_1f, UNCORRECTED_BITMAP_ERROR_1_DISINTf, 1964 INVALIDf, INVALIDr, INVALIDf, 1965 INVALIDr, INVALIDf}, 1966 1967 { 0x0020, INVALIDm, "MMU FAP CORRECTED_STACK_ERROR_1", 1968 CORRECTED_STACK_ERROR_1f, CORRECTED_STACK_ERROR_1_DISINTf, 1969 INVALIDf, INVALIDr, INVALIDf, 1970 INVALIDr, INVALIDf}, 1971 { 0x0010, INVALIDm, "MMU FAP UNCORRECTED_STACK_ERROR_1", 1972 UNCORRECTED_STACK_ERROR_1f, UNCORRECTED_STACK_ERROR_1_DISINTf, 1973 INVALIDf, INVALIDr, INVALIDf, 1974 INVALIDr, INVALIDf}, 1975 1976 { 0x0008, INVALIDm, "MMU FAP CORRECTED_BITMAP_ERROR_0", 1977 CORRECTED_BITMAP_ERROR_0f, CORRECTED_BITMAP_ERROR_0_DISINTf, 1978 INVALIDf, INVALIDr, INVALIDf, 1979 INVALIDr, INVALIDf}, 1980 { 0x0004, INVALIDm, "MMU FAP UNCORRECTED_BITMAP_ERROR_0", 1981 UNCORRECTED_BITMAP_ERROR_0f, UNCORRECTED_BITMAP_ERROR_0_DISINTf, 1982 INVALIDf, INVALIDr, INVALIDf, 1983 INVALIDr, INVALIDf}, 1984 1985 { 0x0002, INVALIDm, "MMU FAP CORRECTED_STACK_ERROR_0", 1986 CORRECTED_STACK_ERROR_0f, CORRECTED_STACK_ERROR_0_DISINTf, 1987 INVALIDf, INVALIDr, INVALIDf, 1988 INVALIDr, INVALIDf}, 1989 { 0x0001, INVALIDm, "MMU FAP UNCORRECTED_STACK_ERROR_0", 1990 UNCORRECTED_STACK_ERROR_0f, UNCORRECTED_STACK_ERROR_0_DISINTf, 1991 INVALIDf, INVALIDr, INVALIDf, 1992 INVALIDr, INVALIDf}, 1993 1994 { 0 } /* table terminator */ 1995 1996 }; 1997 1998 1999 STATIC _soc_saber2_mmu_sub_block_internal_info_t 2000 _soc_saber2_mmu_sb_qstruct_parity_info [] = { 2001 { 0x0004, 2002 _SOC_SABER2_MMU_LVL2_SUBBLOCK_QSTRUCT_FAP, 2003 QENTRY_FAP_ERROR_DISINTf, 2004 QENTRY_FAP_ERRORf, 2005 QSTRUCT_FAP_MEM_ERROR_MASKr, 2006 QSTRUCT_FAP_MEM_ERRORr, 2007 _soc_saber2_mmu_sb_qstruct_fap_parity_info }, 2008 2009 { 0x0002, 2010 _SOC_SABER2_MMU_LVL2_SUBBLOCK_QSTRUCT_QENTRY, 2011 QENTRY_ERROR_0_DISINTf, 2012 QENTRY_ERROR_0f, 2013 QSTRUCT_QENTRY_ERROR_MASK_0r, 2014 QSTRUCT_QENTRY_ERROR_0r, 2015 _soc_saber2_mmu_sb_qstruct_qentry_parity_info }, 2016 2017 { 0x0001, 2018 _SOC_SABER2_MMU_LVL2_SUBBLOCK_QSTRUCT_QBLOCK, 2019 QBLOCK_NEXT_ERROR_0_DISINTf, 2020 QBLOCK_NEXT_ERROR_0f, 2021 QSTRUCT_QBLOCK_NEXT_ERROR_MASK_0r, 2022 QSTRUCT_QBLOCK_NEXT_ERROR_0r, 2023 _soc_saber2_mmu_sb_qstruct_qentry_qblock_nxt_parity_info }, 2024 2025 { 0 } /* table terminator */ 2026 2027 }; 2028 2029 STATIC 2030 _soc_saber2_mmu_sub_block_leaf_info_t 2031 _soc_saber2_mmu_sb_deq0_parity_info [] = { 2032 /* Not ECC error */ 2033 { 0x0800, INVALIDm, "MMU DEQ_RDE_TRACE_EVENT", 2034 DEQ_RDE_TRACE_EVENTf, 2035 DEQ_RDE_TRACE_EVENT_DISINTf, 2036 INVALIDf, INVALIDr, INVALIDf, 2037 INVALIDr, INVALIDf}, 2038 2039 { 0x0400, INVALIDm, "MMU CCBE_CONTROL_DATA_REPLICATION_CREDIT_RETURN_2_ERROR", 2040 CCBE_CONTROL_DATA_REPLICATION_CREDIT_RETURN_2_ERRORf, 2041 CCBE_CONTROL_DATA_REPLICATION_CREDIT_RETURN_2_ERROR_DISINTf, 2042 INVALIDf, INVALIDr, INVALIDf, 2043 INVALIDr, INVALIDf}, 2044 2045 { 0x0200, INVALIDm, "MMU CCBE_CONTROL_DATA_REPLICATION_CREDIT_RETURN_1_ERROR", 2046 CCBE_CONTROL_DATA_REPLICATION_CREDIT_RETURN_1_ERRORf, 2047 CCBE_CONTROL_DATA_REPLICATION_CREDIT_RETURN_1_ERROR_DISINTf, 2048 INVALIDf, INVALIDr, INVALIDf, 2049 INVALIDr, INVALIDf}, 2050 2051 { 0x0100, INVALIDm, "MMU CCBE_CONTROL_DATA_REPLICATION_ERROR", 2052 CCBE_CONTROL_DATA_REPLICATION_ERRORf, 2053 CCBE_CONTROL_DATA_REPLICATION_ERROR_DISINTf, 2054 INVALIDf, INVALIDr, INVALIDf, 2055 INVALIDr, INVALIDf}, 2056 2057 { 0x0080, INVALIDm, "MMU CELL_CLASSIFICATION_EXT_ERROR", 2058 CELL_CLASSIFICATION_EXT_ERRORf, 2059 CELL_CLASSIFICATION_EXT_ERROR_DISINTf, 2060 INVALIDf, INVALIDr, INVALIDf, 2061 INVALIDr, INVALIDf}, 2062 2063 { 0x0040, INVALIDm, "MMU CELL_CLASSIFICATION_INT_ERROR", 2064 CELL_CLASSIFICATION_INT_ERRORf, 2065 CELL_CLASSIFICATION_INT_ERROR_DISINTf, 2066 INVALIDf, INVALIDr, INVALIDf, 2067 INVALIDr, INVALIDf}, 2068 2069 { 0x0020, INVALIDm, "MMU RD_CTRL_RD_REQ_DISCARD_ERROR", 2070 RD_CTRL_RD_REQ_DISCARD_ERRORf, 2071 RD_CTRL_RD_REQ_DISCARD_ERROR_DISINTf, 2072 INVALIDf, INVALIDr, INVALIDf, 2073 INVALIDr, INVALIDf}, 2074 2075 { 0x0010, INVALIDm, "MMU DEQ_TRACE_EVENT", 2076 DEQ_TRACE_EVENTf, 2077 DEQ_TRACE_EVENT_DISINTf, 2078 INVALIDf, INVALIDr, INVALIDf, 2079 INVALIDr, INVALIDf}, 2080 2081 { 0x0008, INVALIDm, "MMU EGRESS_FIFO_OVERFLOW_ERROR", 2082 EGRESS_FIFO_OVERFLOW_ERRORf, 2083 EGRESS_FIFO_OVERFLOW_ERROR_DISINTf, 2084 INVALIDf, INVALIDr, INVALIDf, 2085 INVALIDr, INVALIDf}, 2086 2087 { 0x0004, INVALIDm, "MMU EGRESS_FIFO_UNDERRUN_ERROR", 2088 EGRESS_FIFO_UNDERRUN_ERRORf, 2089 EGRESS_FIFO_UNDERRUN_ERROR_DISINTf, 2090 INVALIDf, INVALIDr, INVALIDf, 2091 INVALIDr, INVALIDf}, 2092 2093 { 0x0002, INVALIDm, "MMU TOQ_TO_DEQ_CELL_REP_INFO_BUFFER_RD_REQ_ERROR", 2094 TOQ_TO_DEQ_CELL_REP_INFO_BUFFER_RD_REQ_ERRORf, 2095 DEQ_TO_CFG_TOQ_TO_DEQ_CELL_REP_INFO_BUFFER_RD_REQ_ERROR_DISINTf, 2096 INVALIDf, INVALIDr, INVALIDf, 2097 INVALIDr, INVALIDf}, 2098 2099 { 0x0001, INVALIDm, "MMU TOQ_TO_DEQ_CELL_REP_INFO_BUFFER_WR_REQ_ERROR", 2100 TOQ_TO_DEQ_CELL_REP_INFO_BUFFER_WR_REQ_ERRORf, 2101 DEQ_TO_CFG_TOQ_TO_DEQ_CELL_REP_INFO_BUFFER_WR_REQ_ERROR_DISINTf, 2102 INVALIDf, INVALIDr, INVALIDf, 2103 INVALIDr, INVALIDf}, 2104 2105 2106 { 0 } /* table terminator */ 2107 2108 }; 2109 2110 STATIC 2111 _soc_saber2_mmu_sub_block_leaf_info_t 2112 _soc_saber2_mmu_sb_deq1_parity_info [] = { 2113 { 0x20000000, INVALIDm, "MMU DEQ_CELL_CLASSIFICATION_EXT_ECC0_CHECK_2_UNCORRECTED_ERRORf", 2114 DEQ_CELL_CLASSIFICATION_EXT_ECC0_CHECK_2_UNCORRECTED_ERRORf, 2115 DEQ_CELL_CLASSIFICATION_EXT_ECC0_CHECK_2_UNCORRECTED_ERROR_DISINTf, 2116 INVALIDf, INVALIDr, INVALIDf, 2117 INVALIDr, INVALIDf}, 2118 { 0x10000000, INVALIDm, "MMU DEQ_CELL_CLASSIFICATION_EXT_ECC0_CHECK_2_CORRECTED_ERRORf", 2119 DEQ_CELL_CLASSIFICATION_EXT_ECC0_CHECK_2_CORRECTED_ERRORf, 2120 DEQ_CELL_CLASSIFICATION_EXT_ECC0_CHECK_2_CORRECTED_ERROR_DISINTf, 2121 INVALIDf, INVALIDr, INVALIDf, 2122 INVALIDr, INVALIDf}, 2123 2124 { 0x08000000, INVALIDm, "MMU DEQ_CELL_CLASSIFICATION_EXT_ECC0_CHECK_1_UNCORRECTED_ERRORf", 2125 DEQ_CELL_CLASSIFICATION_EXT_ECC0_CHECK_1_UNCORRECTED_ERRORf, 2126 DEQ_CELL_CLASSIFICATION_EXT_ECC0_CHECK_1_UNCORRECTED_ERROR_DISINTf, 2127 INVALIDf, INVALIDr, INVALIDf, 2128 INVALIDr, INVALIDf}, 2129 { 0x04000000, INVALIDm, "MMU DEQ_CELL_CLASSIFICATION_EXT_ECC0_CHECK_1_CORRECTED_ERRORf", 2130 DEQ_CELL_CLASSIFICATION_EXT_ECC0_CHECK_1_CORRECTED_ERRORf, 2131 DEQ_CELL_CLASSIFICATION_EXT_ECC0_CHECK_1_CORRECTED_ERROR_DISINTf, 2132 INVALIDf, INVALIDr, INVALIDf, 2133 INVALIDr, INVALIDf}, 2134 2135 { 0x02000000, INVALIDm, "MMU DEQ_CELL_CLASSIFICATION_EXT_ECC0_CHECK_0_UNCORRECTED_ERRORf", 2136 DEQ_CELL_CLASSIFICATION_EXT_ECC0_CHECK_0_UNCORRECTED_ERRORf, 2137 DEQ_CELL_CLASSIFICATION_EXT_ECC0_CHECK_0_UNCORRECTED_ERROR_DISINTf, 2138 INVALIDf, INVALIDr, INVALIDf, 2139 INVALIDr, INVALIDf}, 2140 { 0x01000000, INVALIDm, "MMU DEQ_CELL_CLASSIFICATION_EXT_ECC0_CHECK_0_CORRECTED_ERRORf", 2141 DEQ_CELL_CLASSIFICATION_EXT_ECC0_CHECK_0_CORRECTED_ERRORf, 2142 DEQ_CELL_CLASSIFICATION_EXT_ECC0_CHECK_0_CORRECTED_ERROR_DISINTf, 2143 INVALIDf, INVALIDr, INVALIDf, 2144 INVALIDr, INVALIDf}, 2145 2146 { 0x00800000, INVALIDm, "MMU DEQ_CELL_CLASSIFICATION_INT_ECC0_CHECK_2_UNCORRECTED_ERROR", 2147 DEQ_CELL_CLASSIFICATION_INT_ECC0_CHECK_2_UNCORRECTED_ERRORf, 2148 DEQ_CELL_CLASSIFICATION_INT_ECC0_CHECK_2_UNCORRECTED_ERROR_DISINTf}, 2149 { 0x00400000, INVALIDm, "MMU DEQ_CELL_CLASSIFICATION_INT_ECC0_CHECK_2_CORRECTED_ERROR", 2150 DEQ_CELL_CLASSIFICATION_INT_ECC0_CHECK_2_CORRECTED_ERRORf, 2151 DEQ_CELL_CLASSIFICATION_INT_ECC0_CHECK_2_CORRECTED_ERROR_DISINTf}, 2152 2153 { 0x00200000, INVALIDm, "MMU DEQ_CELL_CLASSIFICATION_INT_ECC0_CHECK_1_UNCORRECTED_ERROR", 2154 DEQ_CELL_CLASSIFICATION_INT_ECC0_CHECK_1_UNCORRECTED_ERRORf, 2155 DEQ_CELL_CLASSIFICATION_INT_ECC0_CHECK_1_UNCORRECTED_ERROR_DISINTf}, 2156 { 0x00100000, INVALIDm, "MMU DEQ_CELL_CLASSIFICATION_INT_ECC0_CHECK_1_CORRECTED_ERROR", 2157 DEQ_CELL_CLASSIFICATION_INT_ECC0_CHECK_1_CORRECTED_ERRORf, 2158 DEQ_CELL_CLASSIFICATION_INT_ECC0_CHECK_1_CORRECTED_ERROR_DISINTf}, 2159 2160 { 0x00080000, INVALIDm, "MMU DEQ_CELL_CLASSIFICATION_INT_ECC0_CHECK_0_UNCORRECTED_ERROR", 2161 DEQ_CELL_CLASSIFICATION_INT_ECC0_CHECK_0_UNCORRECTED_ERRORf, 2162 DEQ_CELL_CLASSIFICATION_INT_ECC0_CHECK_0_UNCORRECTED_ERROR_DISINTf, 2163 INVALIDf, INVALIDr, INVALIDf, 2164 INVALIDr, INVALIDf}, 2165 { 0x00040000, INVALIDm, "MMU DEQ_CELL_CLASSIFICATION_INT_ECC0_CHECK_0_CORRECTED_ERROR", 2166 DEQ_CELL_CLASSIFICATION_INT_ECC0_CHECK_0_CORRECTED_ERRORf, 2167 DEQ_CELL_CLASSIFICATION_INT_ECC0_CHECK_0_CORRECTED_ERROR_DISINTf, 2168 INVALIDf, INVALIDr, INVALIDf, 2169 INVALIDr, INVALIDf}, 2170 2171 { 0x00020000, INVALIDm, "MMU DEQ_EP_REDIRECT_BUFFER_2_UNCORRECTED_ERROR", 2172 DEQ_EP_REDIRECT_BUFFER_2_UNCORRECTED_ERRORf, 2173 DEQ_EP_REDIRECT_BUFFER_2_UNCORRECTED_ERROR_DISINTf, 2174 INVALIDf, INVALIDr, INVALIDf, 2175 INVALIDr, INVALIDf}, 2176 { 0x00010000, INVALIDm, "MMU DEQ_EP_REDIRECT_BUFFER_2_CORRECTED_ERROR", 2177 DEQ_EP_REDIRECT_BUFFER_2_CORRECTED_ERRORf, 2178 DEQ_EP_REDIRECT_BUFFER_2_CORRECTED_ERROR_DISINTf, 2179 INVALIDf, INVALIDr, INVALIDf, 2180 INVALIDr, INVALIDf}, 2181 2182 { 0x00008000, INVALIDm, "MMU DEQ_EP_REDIRECT_BUFFER_1_UNCORRECTED_ERROR", 2183 DEQ_EP_REDIRECT_BUFFER_1_UNCORRECTED_ERRORf, 2184 DEQ_EP_REDIRECT_BUFFER_1_UNCORRECTED_ERROR_DISINTf, 2185 INVALIDf, INVALIDr, INVALIDf, 2186 INVALIDr, INVALIDf}, 2187 { 0x00004000, INVALIDm, "MMU DEQ_EP_REDIRECT_BUFFER_1_CORRECTED_ERROR", 2188 DEQ_EP_REDIRECT_BUFFER_1_CORRECTED_ERRORf, 2189 DEQ_EP_REDIRECT_BUFFER_1_CORRECTED_ERROR_DISINTf, 2190 INVALIDf, INVALIDr, INVALIDf, 2191 INVALIDr, INVALIDf}, 2192 2193 2194 { 0x00002000, INVALIDm, "MMU DEQ_EP_REDIRECT_BUFFER_0_UNCORRECTED_ERROR", 2195 DEQ_EP_REDIRECT_BUFFER_0_UNCORRECTED_ERRORf, 2196 DEQ_EP_REDIRECT_BUFFER_0_UNCORRECTED_ERROR_DISINTf, 2197 INVALIDf, INVALIDr, INVALIDf, 2198 INVALIDr, INVALIDf}, 2199 { 0x00001000, INVALIDm, "MMU DEQ_EP_REDIRECT_BUFFER_0_CORRECTED_ERROR", 2200 DEQ_EP_REDIRECT_BUFFER_0_CORRECTED_ERRORf, 2201 DEQ_EP_REDIRECT_BUFFER_0_CORRECTED_ERROR_DISINTf, 2202 INVALIDf, INVALIDr, INVALIDf, 2203 INVALIDr, INVALIDf}, 2204 2205 { 0x00000800, INVALIDm, "MMU DEQ_PST_EGRESS_FIFO_ECC_VERIF_EXT_1520_UNCORRECTED_ERROR", 2206 DEQ_PST_EGRESS_FIFO_ECC_VERIF_EXT_1520_UNCORRECTED_ERRORf, 2207 DEQ_PST_EGRESS_FIFO_ECC_VERIF_EXT_1520_UNCORRECTED_ERROR_DISINTf, 2208 INVALIDf, INVALIDr, INVALIDf, 2209 INVALIDr, INVALIDf}, 2210 { 0x00000400, INVALIDm, "MMU DEQ_PST_EGRESS_FIFO_ECC_VERIF_EXT_1520_CORRECTED_ERROR", 2211 DEQ_PST_EGRESS_FIFO_ECC_VERIF_EXT_1520_CORRECTED_ERRORf, 2212 DEQ_PST_EGRESS_FIFO_ECC_VERIF_EXT_1520_CORRECTED_ERROR_DISINTf, 2213 INVALIDf, INVALIDr, INVALIDf, 2214 INVALIDr, INVALIDf}, 2215 2216 { 0x00000200, INVALIDm, "MMU DEQ_PST_EGRESS_FIFO_ECC_VERIF_EXT_57_UNCORRECTED_ERROR", 2217 DEQ_PST_EGRESS_FIFO_ECC_VERIF_EXT_57_UNCORRECTED_ERRORf, 2218 DEQ_PST_EGRESS_FIFO_ECC_VERIF_EXT_57_UNCORRECTED_ERROR_DISINTf, 2219 INVALIDf, INVALIDr, INVALIDf, 2220 INVALIDr, INVALIDf}, 2221 { 0x00000100, INVALIDm, "MMU DEQ_PST_EGRESS_FIFO_ECC_VERIF_EXT_57_CORRECTED_ERROR", 2222 DEQ_PST_EGRESS_FIFO_ECC_VERIF_EXT_57_CORRECTED_ERRORf, 2223 DEQ_PST_EGRESS_FIFO_ECC_VERIF_EXT_57_CORRECTED_ERROR_DISINTf, 2224 INVALIDf, INVALIDr, INVALIDf, 2225 INVALIDr, INVALIDf}, 2226 2227 { 0x00000080, INVALIDm, "MMU DEQ_PST_EGRESS_FIFO_ECC_VERIF_INT_1520_UNCORRECTED_ERROR", 2228 DEQ_PST_EGRESS_FIFO_ECC_VERIF_INT_1520_UNCORRECTED_ERRORf, 2229 DEQ_PST_EGRESS_FIFO_ECC_VERIF_INT_1520_UNCORRECTED_ERROR_DISINTf, 2230 INVALIDf, INVALIDr, INVALIDf, 2231 INVALIDr, INVALIDf}, 2232 { 0x00000040, INVALIDm, "MMU DEQ_PST_EGRESS_FIFO_ECC_VERIF_INT_1520_CORRECTED_ERROR", 2233 DEQ_PST_EGRESS_FIFO_ECC_VERIF_INT_1520_CORRECTED_ERRORf, 2234 DEQ_PST_EGRESS_FIFO_ECC_VERIF_INT_1520_CORRECTED_ERROR_DISINTf, 2235 INVALIDf, INVALIDr, INVALIDf, 2236 INVALIDr, INVALIDf}, 2237 2238 { 0x00000020, INVALIDm, "MMU DEQ_PST_EGRESS_FIFO_ECC_VERIF_INT_57_UNCORRECTED_ERROR", 2239 DEQ_PST_EGRESS_FIFO_ECC_VERIF_INT_57_UNCORRECTED_ERRORf, 2240 DEQ_PST_EGRESS_FIFO_ECC_VERIF_INT_57_UNCORRECTED_ERROR_DISINTf, 2241 INVALIDf, INVALIDr, INVALIDf, 2242 INVALIDr, INVALIDf}, 2243 { 0x00000010, INVALIDm, "MMU DEQ_PST_EGRESS_FIFO_ECC_VERIF_INT_57_CORRECTED_ERROR", 2244 DEQ_PST_EGRESS_FIFO_ECC_VERIF_INT_57_CORRECTED_ERRORf, 2245 DEQ_PST_EGRESS_FIFO_ECC_VERIF_INT_57_CORRECTED_ERROR_DISINTf, 2246 INVALIDf, INVALIDr, INVALIDf, 2247 INVALIDr, INVALIDf}, 2248 2249 { 0x00000008, INVALIDm, "MMU DEQ_EGRESS_FIFO_CONTROL_DATA_MEMORY_UNCORRECTED_ERROR", 2250 DEQ_EGRESS_FIFO_CONTROL_DATA_MEMORY_UNCORRECTED_ERRORf, 2251 DEQ_EGRESS_FIFO_CONTROL_DATA_MEMORY_UNCORRECTED_ERROR_DISINTf, 2252 INVALIDf, INVALIDr, INVALIDf, 2253 INVALIDr, INVALIDf}, 2254 { 0x00000004, INVALIDm, "MMU DEQ_EGRESS_FIFO_CONTROL_DATA_MEMORY_CORRECTED_ERROR", 2255 DEQ_EGRESS_FIFO_CONTROL_DATA_MEMORY_CORRECTED_ERRORf, 2256 DEQ_EGRESS_FIFO_CONTROL_DATA_MEMORY_CORRECTED_ERROR_DISINTf, 2257 INVALIDf, INVALIDr, INVALIDf, 2258 INVALIDr, INVALIDf}, 2259 2260 { 0x00000002, INVALIDm, "MMU DEQ_TOQ_CELL_REP_INFO_BUFFER_UNCORRECTED_ERROR", 2261 DEQ_TOQ_CELL_REP_INFO_BUFFER_UNCORRECTED_ERRORf, 2262 DEQ_TOQ_CELL_REP_INFO_BUFFER_UNCORRECTED_ERROR_DISINTf, 2263 INVALIDf, INVALIDr, INVALIDf, 2264 INVALIDr, INVALIDf}, 2265 { 0x00000001, INVALIDm, "MMU DEQ_TOQ_CELL_REP_INFO_BUFFER_CORRECTED_ERROR", 2266 DEQ_TOQ_CELL_REP_INFO_BUFFER_CORRECTED_ERRORf, 2267 DEQ_TOQ_CELL_REP_INFO_BUFFER_CORRECTED_ERROR_DISINTf, 2268 INVALIDf, INVALIDr, INVALIDf, 2269 INVALIDr, INVALIDf}, 2270 2271 { 0 } /* table terminator */ 2272 2273 }; 2274 2275 STATIC 2276 _soc_saber2_mmu_sub_block_leaf_info_t 2277 _soc_saber2_mmu_sb_deq2_parity_info [] = { 2278 2279 { 0x00000010, INVALIDm, "MMU DEQ_CELL_RECONSTRUCTION_RESIDUAL_BUFFER_4", 2280 DEQ_CELL_RECONSTRUCTION_RESIDUAL_BUFFER_4_PARITY_ERRORf, 2281 DEQ_CELL_RECONSTRUCTION_RESIDUAL_BUFFER_4_PARITY_ERROR_DISINTf, 2282 INVALIDf, INVALIDr, INVALIDf, 2283 INVALIDr, INVALIDf}, 2284 2285 { 0x00000008, INVALIDm, "MMU DEQ_CELL_RECONSTRUCTION_RESIDUAL_BUFFER_3", 2286 DEQ_CELL_RECONSTRUCTION_RESIDUAL_BUFFER_3_PARITY_ERRORf, 2287 DEQ_CELL_RECONSTRUCTION_RESIDUAL_BUFFER_3_PARITY_ERROR_DISINTf, 2288 INVALIDf, INVALIDr, INVALIDf, 2289 INVALIDr, INVALIDf}, 2290 2291 { 0x00000004, INVALIDm, "MMU DEQ_CELL_RECONSTRUCTION_RESIDUAL_BUFFER_2", 2292 DEQ_CELL_RECONSTRUCTION_RESIDUAL_BUFFER_2_PARITY_ERRORf, 2293 DEQ_CELL_RECONSTRUCTION_RESIDUAL_BUFFER_2_PARITY_ERROR_DISINTf, 2294 INVALIDf, INVALIDr, INVALIDf, 2295 INVALIDr, INVALIDf}, 2296 2297 { 0x00000002, INVALIDm, "MMU DEQ_CELL_RECONSTRUCTION_RESIDUAL_BUFFER_1", 2298 DEQ_CELL_RECONSTRUCTION_RESIDUAL_BUFFER_1_PARITY_ERRORf, 2299 DEQ_CELL_RECONSTRUCTION_RESIDUAL_BUFFER_1_PARITY_ERROR_DISINTf, 2300 INVALIDf, INVALIDr, INVALIDf, 2301 INVALIDr, INVALIDf}, 2302 2303 { 0x00000001, INVALIDm, "MMU DEQ_CELL_RECONSTRUCTION_RESIDUAL_BUFFER_0", 2304 DEQ_CELL_RECONSTRUCTION_RESIDUAL_BUFFER_0_PARITY_ERRORf, 2305 DEQ_CELL_RECONSTRUCTION_RESIDUAL_BUFFER_0_PARITY_ERROR_DISINTf, 2306 INVALIDf, INVALIDr, INVALIDf, 2307 INVALIDr, INVALIDf}, 2308 2309 { 0 } /* table terminator */ 2310 2311 }; 2312 2313 2314 STATIC _soc_saber2_mmu_sub_block_internal_info_t 2315 _soc_saber2_mmu_sb_deq_parity_info [] = { 2316 /* DEQ_ERROR */ 2317 { 0x0004, 2318 _SOC_SABER2_MMU_LVL2_SUBBLOCK_DEQ_ERROR_2, 2319 INVALIDf, 2320 DEQ_ERROR_2f, 2321 DEQ_ERROR_MASK_2r, 2322 DEQ_ERROR_2r, 2323 _soc_saber2_mmu_sb_deq2_parity_info }, 2324 2325 { 0x0002, 2326 _SOC_SABER2_MMU_LVL2_SUBBLOCK_DEQ_ERROR_1, 2327 INVALIDf, 2328 DEQ_ERROR_1f, 2329 DEQ_ERROR_MASK_1r, 2330 DEQ_ERROR_1r, 2331 _soc_saber2_mmu_sb_deq1_parity_info }, 2332 2333 { 0x0001, 2334 _SOC_SABER2_MMU_LVL2_SUBBLOCK_DEQ_ERROR_0, 2335 INVALIDf, 2336 DEQ_ERROR_0f, 2337 DEQ_ERROR_MASK_0r, 2338 DEQ_ERROR_0r, 2339 _soc_saber2_mmu_sb_deq0_parity_info }, 2340 2341 { 0 } /* table terminator */ 2342 2343 }; 2344 2345 STATIC 2346 _soc_saber2_mmu_sub_block_leaf_info_t 2347 _soc_saber2_mmu_sb_emc0_parity_info [] = { 2348 /* EMC_ERROR_0 */ 2349 { 0x0080, INVALIDm, "MMU EMC_WTAC_WTFP_CFG_ERROR", 2350 EMC_WTAC_WTFP_CFG_ERRORf, EMC_WTAC_WTFP_CFG_ERROR_DISINTf, 2351 INVALIDf, INVALIDr, INVALIDf, 2352 INVALIDr, INVALIDf}, 2353 2354 { 0x0040, INVALIDm, "MMU EMC_RSAG_RSFP_CFG_ERROR", 2355 EMC_RSAG_RSFP_CFG_ERRORf, EMC_RSAG_RSFP_CFG_ERROR_DISINTf, 2356 INVALIDf, INVALIDr, INVALIDf, 2357 INVALIDr, INVALIDf}, 2358 2359 { 0x0020, INVALIDm, "MMU EMC_CI_WR_REQ_FULL_ERROR", 2360 EMC_CI_WR_REQ_FULL_ERRORf, EMC_CI_WR_REQ_FULL_ERROR_DISINTf, 2361 INVALIDf, INVALIDr, INVALIDf, 2362 INVALIDr, INVALIDf}, 2363 2364 { 0x0010, INVALIDm, "MMU EMC_WTAC_SPC_EMA_LOCKUP_ERRORf", 2365 EMC_WTAC_SPC_EMA_LOCKUP_ERRORf, EMC_WTAC_SPC_EMA_LOCKUP_ERROR_DISINTf, 2366 INVALIDf, INVALIDr, INVALIDf, 2367 INVALIDr, INVALIDf}, 2368 2369 { 0x0008, INVALIDm, "MMU EMC_WLCT_ERROR", 2370 EMC_WLCT_ERRORf, EMC_WLCT_ERROR_DISINTf, 2371 INVALIDf, INVALIDr, INVALIDf, 2372 INVALIDr, INVALIDf}, 2373 2374 { 0x0004, INVALIDm, "MMU EMC_WLCT_MF_BUFFER_OVERFLOW_ERROR", 2375 EMC_WLCT_MF_BUFFER_OVERFLOW_ERRORf, EMC_WLCT_MF_BUFFER_OVERFLOW_ERROR_DISINTf, 2376 INVALIDf, INVALIDr, INVALIDf, 2377 INVALIDr, INVALIDf}, 2378 2379 { 0x0002, INVALIDm, "MMU EMC_IRRB_BUFFER_OVERFLOW_ERROR", 2380 EMC_IRRB_BUFFER_OVERFLOW_ERRORf, EMC_IRRB_BUFFER_OVERFLOW_ERROR_DISINTf, 2381 INVALIDf, INVALIDr, INVALIDf, 2382 INVALIDr, INVALIDf}, 2383 2384 { 0x0001, INVALIDm, "MMU EMC_IWRB_BUFFER_OVERFLOW_ERROR", 2385 EMC_IWRB_BUFFER_OVERFLOW_ERRORf, EMC_IWRB_BUFFER_OVERFLOW_ERROR_DISINTf, 2386 INVALIDf, INVALIDr, INVALIDf, 2387 INVALIDr, INVALIDf}, 2388 2389 { 0 } /* table terminator */ 2390 2391 }; 2392 2393 STATIC 2394 _soc_saber2_mmu_sub_block_leaf_info_t 2395 _soc_saber2_mmu_sb_emc1_parity_info [] = { 2396 /* EMC_ERROR_1 */ 2397 { 0x80000, INVALIDm,"MMU EMC_CSDB_1_BUFFER_MEM_3_UNCORRECTED_ERROR", 2398 EMC_CSDB_1_BUFFER_MEM_3_UNCORRECTED_ERRORf, 2399 EMC_CSDB_1_BUFFER_MEM_3_UNCORRECTED_ERROR_DISINTf, 2400 INVALIDf, INVALIDr, INVALIDf, 2401 INVALIDr, INVALIDf}, 2402 2403 { 0x40000, INVALIDm,"MMU EMC_CSDB_1_BUFFER_MEM_2_UNCORRECTED_ERROR", 2404 EMC_CSDB_1_BUFFER_MEM_2_UNCORRECTED_ERRORf, 2405 EMC_CSDB_1_BUFFER_MEM_2_UNCORRECTED_ERROR_DISINTf, 2406 INVALIDf, INVALIDr, INVALIDf, 2407 INVALIDr, INVALIDf}, 2408 2409 { 0x20000, INVALIDm,"MMU EMC_CSDB_1_BUFFER_MEM_1_UNCORRECTED_ERROR", 2410 EMC_CSDB_1_BUFFER_MEM_1_UNCORRECTED_ERRORf, 2411 EMC_CSDB_1_BUFFER_MEM_1_UNCORRECTED_ERROR_DISINTf, 2412 INVALIDf, INVALIDr, INVALIDf, 2413 INVALIDr, INVALIDf}, 2414 2415 { 0x10000, INVALIDm,"MMU EMC_CSDB_1_BUFFER_MEM_0_UNCORRECTED_ERROR", 2416 EMC_CSDB_1_BUFFER_MEM_0_UNCORRECTED_ERRORf, 2417 EMC_CSDB_1_BUFFER_MEM_0_UNCORRECTED_ERROR_DISINTf, 2418 INVALIDf, INVALIDr, INVALIDf, 2419 INVALIDr, INVALIDf}, 2420 2421 { 0x8000, INVALIDm,"MMU EMC_CSDB_0_BUFFER_MEM_3_UNCORRECTED_ERROR", 2422 EMC_CSDB_0_BUFFER_MEM_3_UNCORRECTED_ERRORf, 2423 EMC_CSDB_0_BUFFER_MEM_3_UNCORRECTED_ERROR_DISINTf, 2424 INVALIDf, INVALIDr, INVALIDf, 2425 INVALIDr, INVALIDf}, 2426 2427 { 0x4000, INVALIDm,"MMU EMC_CSDB_0_BUFFER_MEM_2_UNCORRECTED_ERROR", 2428 EMC_CSDB_0_BUFFER_MEM_2_UNCORRECTED_ERRORf, 2429 EMC_CSDB_0_BUFFER_MEM_2_UNCORRECTED_ERROR_DISINTf, 2430 INVALIDf, INVALIDr, INVALIDf, 2431 INVALIDr, INVALIDf}, 2432 2433 { 0x2000, INVALIDm,"MMU EMC_CSDB_0_BUFFER_MEM_1_UNCORRECTED_ERROR", 2434 EMC_CSDB_0_BUFFER_MEM_1_UNCORRECTED_ERRORf, 2435 EMC_CSDB_0_BUFFER_MEM_1_UNCORRECTED_ERROR_DISINTf, 2436 INVALIDf, INVALIDr, INVALIDf, 2437 INVALIDr, INVALIDf}, 2438 2439 { 0x1000, INVALIDm,"MMU EMC_CSDB_0_BUFFER_MEM_0_UNCORRECTED_ERROR", 2440 EMC_CSDB_0_BUFFER_MEM_0_UNCORRECTED_ERRORf, 2441 EMC_CSDB_0_BUFFER_MEM_0_UNCORRECTED_ERROR_DISINTf, 2442 INVALIDf, INVALIDr, INVALIDf, 2443 INVALIDr, INVALIDf}, 2444 2445 { 0x0800, INVALIDm,"MMU EMC_RFCQ_BUFFER_UNCORRECTED_ERROR", 2446 EMC_RFCQ_BUFFER_UNCORRECTED_ERRORf, 2447 EMC_RFCQ_BUFFER_UNCORRECTED_ERROR_DISINTf, 2448 INVALIDf, INVALIDr, INVALIDf, 2449 INVALIDr, INVALIDf}, 2450 { 0x0400, INVALIDm,"MMU EMC_RFCQ_BUFFER_CORRECTED_ERROR", 2451 EMC_RFCQ_BUFFER_CORRECTED_ERRORf, 2452 EMC_RFCQ_BUFFER_CORRECTED_ERROR_DISINTf, 2453 INVALIDf, INVALIDr, INVALIDf, 2454 INVALIDr, INVALIDf}, 2455 2456 { 0x0200, INVALIDm,"MMU EMC_RSFP_BUFFER_UNCORRECTED_ERROR", 2457 EMC_RSFP_BUFFER_UNCORRECTED_ERRORf, 2458 EMC_RSFP_BUFFER_UNCORRECTED_ERROR_DISINTf, 2459 INVALIDf, INVALIDr, INVALIDf, 2460 INVALIDr, INVALIDf}, 2461 { 0x0100, INVALIDm,"MMU EMC_RSFP_BUFFER_CORRECTED_ERROR", 2462 EMC_RSFP_BUFFER_CORRECTED_ERRORf, 2463 EMC_RSFP_BUFFER_CORRECTED_ERROR_DISINTf, 2464 INVALIDf, INVALIDr, INVALIDf, 2465 INVALIDr, INVALIDf}, 2466 2467 { 0x0080, INVALIDm,"MMU EMC_IRRB_BUFFER_UNCORRECTED_ERROR", 2468 EMC_IRRB_BUFFER_UNCORRECTED_ERRORf, 2469 EMC_IRRB_BUFFER_UNCORRECTED_ERROR_DISINTf, 2470 INVALIDf, INVALIDr, INVALIDf, 2471 INVALIDr, INVALIDf}, 2472 { 0x0040, INVALIDm,"MMU EMC_IRRB_BUFFER_CORRECTED_ERROR", 2473 EMC_IRRB_BUFFER_CORRECTED_ERRORf, 2474 EMC_IRRB_BUFFER_CORRECTED_ERROR_DISINTf, 2475 INVALIDf, INVALIDr, INVALIDf, 2476 INVALIDr, INVALIDf}, 2477 2478 { 0x0020, INVALIDm,"MMU EMC_SWAT_BUFFER_UNCORRECTED_ERROR", 2479 EMC_SWAT_BUFFER_UNCORRECTED_ERRORf, 2480 EMC_SWAT_BUFFER_UNCORRECTED_ERROR_DISINTf, 2481 INVALIDf, INVALIDr, INVALIDf, 2482 INVALIDr, INVALIDf}, 2483 { 0x0010, INVALIDm,"MMU EMC_SWAT_BUFFER_CORRECTED_ERROR", 2484 EMC_SWAT_BUFFER_CORRECTED_ERRORf, 2485 EMC_SWAT_BUFFER_CORRECTED_ERROR_DISINTf, 2486 INVALIDf, INVALIDr, INVALIDf, 2487 INVALIDr, INVALIDf}, 2488 2489 { 0x0008, INVALIDm,"MMU EMC_WTOQ_BUFFER_UNCORRECTED_ERROR", 2490 EMC_WTOQ_BUFFER_UNCORRECTED_ERRORf, 2491 EMC_WTOQ_BUFFER_UNCORRECTED_ERROR_DISINTf, 2492 INVALIDf, INVALIDr, INVALIDf, 2493 INVALIDr, INVALIDf}, 2494 { 0x0004, INVALIDm,"MMU EMC_WTOQ_BUFFER_CORRECTED_ERROR", 2495 EMC_WTOQ_BUFFER_CORRECTED_ERRORf, 2496 EMC_WTOQ_BUFFER_CORRECTED_ERROR_DISINTf, 2497 INVALIDf, INVALIDr, INVALIDf, 2498 INVALIDr, INVALIDf}, 2499 2500 { 0x0002, INVALIDm,"MMU EMC_WTFP_BUFFER_UNCORRECTED_ERROR", 2501 EMC_WTFP_BUFFER_UNCORRECTED_ERRORf, 2502 EMC_WTFP_BUFFER_UNCORRECTED_ERROR_DISINTf, 2503 INVALIDf, INVALIDr, INVALIDf, 2504 INVALIDr, INVALIDf}, 2505 { 0x0001, INVALIDm,"MMU EMC_WTFP_BUFFER_CORRECTED_ERROR", 2506 EMC_WTFP_BUFFER_CORRECTED_ERRORf, 2507 EMC_WTFP_BUFFER_CORRECTED_ERROR_DISINTf, 2508 INVALIDf, INVALIDr, INVALIDf, 2509 INVALIDr, INVALIDf}, 2510 2511 { 0 } /* table terminator */ 2512 2513 }; 2514 2515 2516 STATIC 2517 _soc_saber2_mmu_sub_block_leaf_info_t 2518 _soc_saber2_mmu_sb_emc2_parity_info [] = { 2519 /* EMC_ERROR_2 */ 2520 { 0x02,INVALIDm, "MMU EMC_WLCT_BUFFER_UNCORRECTED_ERROR", 2521 EMC_WLCT_BUFFER_UNCORRECTED_ERRORf, 2522 EMC_WLCT_BUFFER_UNCORRECTED_ERROR_DISINTf, 2523 INVALIDf, INVALIDr, INVALIDf, 2524 INVALIDr, INVALIDf}, 2525 2526 { 0x01,INVALIDm, "MMU EMC_WLCT_BUFFER_CORRECTED_ERROR", 2527 EMC_WLCT_BUFFER_CORRECTED_ERRORf, 2528 EMC_WLCT_BUFFER_CORRECTED_ERROR_DISINTf, 2529 INVALIDf, INVALIDr, INVALIDf, 2530 INVALIDr, INVALIDf}, 2531 2532 { 0 } /* table terminator */ 2533 2534 }; 2535 2536 2537 STATIC 2538 _soc_saber2_mmu_sub_block_leaf_info_t 2539 _soc_saber2_mmu_sb_emc3_parity_info [] = { 2540 /* EMC_ERROR_3 */ 2541 { 0x08,INVALIDm, "MMU EMC_CI1_FIXED_PATTERN_ERROR", 2542 EMC_CI1_FIXED_PATTERN_ERRORf, 2543 EMC_CI1_FIXED_PATTERN_ERROR_DISINTf, 2544 INVALIDf, INVALIDr, INVALIDf, 2545 INVALIDr, INVALIDf}, 2546 2547 { 0x04,INVALIDm, "MMU EMC_CI0_FIXED_PATTERN_ERROR", 2548 EMC_CI0_FIXED_PATTERN_ERRORf, 2549 EMC_CI0_FIXED_PATTERN_ERROR_DISINTf, 2550 INVALIDf, INVALIDr, INVALIDf, 2551 INVALIDr, INVALIDf}, 2552 2553 { 0x02,INVALIDm, "MMU EMC_WLCT_MERGED_RETURN_WTAG_FIFO_UNCORRECTED_ERROR", 2554 EMC_WLCT_MERGED_RETURN_WTAG_FIFO_UNCORRECTED_ERRORf, 2555 EMC_WLCT_MERGED_RETURN_WTAG_FIFO_UNCORRECTED_ERROR_DISINTf, 2556 INVALIDf, INVALIDr, INVALIDf, 2557 INVALIDr, INVALIDf}, 2558 2559 { 0x01,INVALIDm, "MMU EMC_WLCT_MERGED_RETURN_WTAG_FIFO_CORRECTED_ERROR", 2560 EMC_WLCT_MERGED_RETURN_WTAG_FIFO_CORRECTED_ERRORf, 2561 EMC_WLCT_MERGED_RETURN_WTAG_FIFO_CORRECTED_ERROR_DISINTf, 2562 INVALIDf, INVALIDr, INVALIDf, 2563 INVALIDr, INVALIDf}, 2564 2565 { 0 } /* table terminator */ 2566 2567 }; 2568 2569 2570 STATIC 2571 _soc_saber2_mmu_sub_block_internal_info_t 2572 _soc_saber2_mmu_sb_emc_parity_info [] = { 2573 { 0x0008, 2574 _SOC_SABER2_MMU_LVL2_SUBBLOCK_EMC_ERROR_3, 2575 INVALIDf, 2576 EMC_ERROR_3f, 2577 EMC_ERROR_MASK_3r, 2578 EMC_ERROR_3r, 2579 _soc_saber2_mmu_sb_emc3_parity_info }, 2580 2581 { 0x0004, 2582 _SOC_SABER2_MMU_LVL2_SUBBLOCK_EMC_ERROR_2, 2583 INVALIDf, 2584 EMC_ERROR_2f, 2585 EMC_ERROR_MASK_2r, 2586 EMC_ERROR_2r, 2587 _soc_saber2_mmu_sb_emc2_parity_info }, 2588 2589 { 0x0002, 2590 _SOC_SABER2_MMU_LVL2_SUBBLOCK_EMC_ERROR_1, 2591 INVALIDf, 2592 EMC_ERROR_1f, 2593 EMC_ERROR_MASK_1r, 2594 EMC_ERROR_1r, 2595 _soc_saber2_mmu_sb_emc1_parity_info }, 2596 2597 { 0x0001, 2598 _SOC_SABER2_MMU_LVL2_SUBBLOCK_EMC_ERROR_0, 2599 INVALIDf, 2600 EMC_ERROR_0f, 2601 EMC_ERROR_MASK_0r, 2602 EMC_ERROR_0r, 2603 _soc_saber2_mmu_sb_emc0_parity_info }, 2604 2605 { 0 } /* table terminator */ 2606 2607 }; 2608 2609 2610 2611 STATIC 2612 _soc_saber2_mmu_sub_block_two_level_t _soc_saber2_mmu_sub_blocks_type_2[] = { 2613 2614 { 0x00000001, 2615 _SOC_SABER2_MMU_SUBBLOCK_TOQ, 2616 TOQ_INTR_DISINTf, 2617 TOQ_INTRf, 2618 TOQ_INTERRUPT_MASKr, 2619 TOQ_INTERRUPTr, 2620 _soc_saber2_mmu_sb_toq_parity_info}, 2621 2622 { 0x00000002, 2623 _SOC_SABER2_MMU_SUBBLOCK_QSTRUCT, 2624 QSTRUCT_INTR_DISINTf, 2625 QSTRUCT_INTRf, 2626 QSTRUCT_INTERRUPT_MASKr, 2627 QSTRUCT_INTERRUPTr, 2628 _soc_saber2_mmu_sb_qstruct_parity_info}, 2629 2630 2631 { 0x00000080, 2632 _SOC_SABER2_MMU_SUBBLOCK_DEQ, 2633 DEQ_INTR_DISINTf, 2634 DEQ_INTRf, 2635 INVALIDr, 2636 DEQ_ERRORr, 2637 _soc_saber2_mmu_sb_deq_parity_info}, 2638 2639 { 0x00000100, 2640 _SOC_SABER2_MMU_SUBBLOCK_EMC, 2641 EMC_INTR_DISINTf, 2642 EMC_INTRf, 2643 INVALIDr, 2644 EMC_ERRORr, 2645 _soc_saber2_mmu_sb_emc_parity_info}, 2646 2647 2648 { 0 } /* table terminator */ 2649 2650 }; 2651 #ifdef BCM_METROLITE_SUPPORT 2652 2653 STATIC 2654 _soc_saber2_mmu_sub_block_leaf_info_t 2655 _soc_metrolite_mmu_sb_deq1_parity_info [] = { 2656 2657 { 0x00000200, INVALIDm, "MMU EP_REDIRECT_BUFFER_2_UNCORRECTED_ERROR", 2658 EP_REDIRECT_BUFFER_2_UNCORRECTED_ERRORf, 2659 EP_REDIRECT_BUFFER_2_UNCORRECTED_ERROR_DISINTf, 2660 INVALIDf, INVALIDr, INVALIDf, 2661 INVALIDr, INVALIDf}, 2662 { 0x00000100, INVALIDm, "MMU EP_REDIRECT_BUFFER_2_CORRECTED_ERROR", 2663 EP_REDIRECT_BUFFER_1_CORRECTED_ERRORf, 2664 EP_REDIRECT_BUFFER_1_CORRECTED_ERROR_DISINTf, 2665 INVALIDf, INVALIDr, INVALIDf, 2666 INVALIDr, INVALIDf}, 2667 2668 { 0x00000080, INVALIDm, "MMU EP_REDIRECT_BUFFER_1_UNCORRECTED_ERROR", 2669 EP_REDIRECT_BUFFER_1_UNCORRECTED_ERRORf, 2670 EP_REDIRECT_BUFFER_1_UNCORRECTED_ERROR_DISINTf, 2671 INVALIDf, INVALIDr, INVALIDf, 2672 INVALIDr, INVALIDf}, 2673 { 0x00000040, INVALIDm, "MMU EP_REDIRECT_BUFFER_1_CORRECTED_ERROR", 2674 EP_REDIRECT_BUFFER_1_CORRECTED_ERRORf, 2675 EP_REDIRECT_BUFFER_1_CORRECTED_ERROR_DISINTf, 2676 INVALIDf, INVALIDr, INVALIDf, 2677 INVALIDr, INVALIDf}, 2678 2679 { 0x00000020, INVALIDm, "MMU EP_REDIRECT_BUFFER_0_UNCORRECTED_ERROR", 2680 EP_REDIRECT_BUFFER_0_UNCORRECTED_ERRORf, 2681 EP_REDIRECT_BUFFER_0_UNCORRECTED_ERROR_DISINTf, 2682 INVALIDf, INVALIDr, INVALIDf, 2683 INVALIDr, INVALIDf}, 2684 { 0x00000010, INVALIDm, "MMU EP_REDIRECT_BUFFER_0_CORRECTED_ERROR", 2685 EP_REDIRECT_BUFFER_0_CORRECTED_ERRORf, 2686 EP_REDIRECT_BUFFER_0_CORRECTED_ERROR_DISINTf, 2687 INVALIDf, INVALIDr, INVALIDf, 2688 INVALIDr, INVALIDf}, 2689 2690 { 0x00000008, INVALIDm, "MMU ECC_VERIFICATION_1520_UNCORRECTED_ERROR", 2691 ECC_VERIFICATION_1520_UNCORRECTED_ERRORf, 2692 ECC_VERIFICATION_1520_UNCORRECTED_ERROR_DISINTf, 2693 INVALIDf, INVALIDr, INVALIDf, 2694 INVALIDr, INVALIDf}, 2695 { 0x00000004, INVALIDm, "MMU ECC_VERIFICATION_1520_CORRECTED_ERROR", 2696 ECC_VERIFICATION_1520_CORRECTED_ERRORf, 2697 ECC_VERIFICATION_1520_CORRECTED_ERROR_DISINTf, 2698 INVALIDf, INVALIDr, INVALIDf, 2699 INVALIDr, INVALIDf}, 2700 2701 { 0x00000002, INVALIDm, "MMU VERIFICATION_57_CORRECTED_UNCORRECTED_ERROR", 2702 ECC_VERIFICATION_57_UNCORRECTED_ERRORf, 2703 ECC_VERIFICATION_57_UNCORRECTED_ERROR_DISINTf, 2704 INVALIDf, INVALIDr, INVALIDf, 2705 INVALIDr, INVALIDf}, 2706 { 0x00000001, INVALIDm, "MMU VERIFICATION_57_CORRECTED_ERROR", 2707 ECC_VERIFICATION_57_CORRECTED_ERRORf, 2708 ECC_VERIFICATION_57_CORRECTED_ERROR_DISINTf, 2709 INVALIDf, INVALIDr, INVALIDf, 2710 INVALIDr, INVALIDf}, 2711 2712 { 0 } /* table terminator */ 2713 2714 }; 2715 2716 STATIC _soc_saber2_mmu_sub_block_leaf_info_t 2717 _soc_metrolite_mmu_sb_enq_cfg_parity_info [] = { 2718 /* MMU_ENQ_CFG_ECC_ERROR_0 */ 2719 { 0x2000, INVALIDm, "ENQ CFG POST_PAC_SAE_FIFO_CORRECTED_ERROR", 2720 POST_PAC_SAE_FIFO_CORRECTED_ERRORf, POST_PAC_SAE_FIFO_CORRECTED_ERROR_DISINTf, 2721 INVALIDf, INVALIDr, INVALIDf, 2722 INVALIDr, INVALIDf}, 2723 { 0x1000, INVALIDm, "ENQ CFG POST_PAC_SAE_FIFO_UNCORRECTED_ERROR", 2724 POST_PAC_SAE_FIFO_UNCORRECTED_ERRORf, POST_PAC_SAE_FIFO_UNCORRECTED_ERROR_DISINTf, 2725 INVALIDf, INVALIDr, INVALIDf, 2726 INVALIDr, INVALIDf}, 2727 2728 { 0x0800, INVALIDm, "ENQ CFG CBI_CORRECTED_ERROR", 2729 CBI_CORRECTED_ERRORf, CBI_CORRECTED_ERROR_DISINTf, 2730 INVALIDf, INVALIDr, INVALIDf, 2731 INVALIDr, INVALIDf}, 2732 { 0x0400, INVALIDm, "ENQ CFG CBI_UNCORRECTED_ERROR", 2733 CBI_UNCORRECTED_ERRORf, CBI_UNCORRECTED_ERROR_DISINTf, 2734 INVALIDf, INVALIDr, INVALIDf, 2735 INVALIDr, INVALIDf}, 2736 2737 { 0x0200, INVALIDm, "ENQ CFG CFAPI_INTERNAL_RECYCLE_UNCORRECTED_ERROR", 2738 CFAPI_INTERNAL_RECYCLE_CORRECTED_ERRORf, CFAPI_INTERNAL_RECYCLE_CORRECTED_ERROR_DISINTf, 2739 INVALIDf, INVALIDr, INVALIDf, 2740 INVALIDr, INVALIDf}, 2741 { 0x0100, INVALIDm, "ENQ CFG CFAPI_INTERNAL_RECYCLE_UNCORRECTED_ERROR", 2742 CFAPI_INTERNAL_RECYCLE_UNCORRECTED_ERRORf, CFAPI_INTERNAL_RECYCLE_UNCORRECTED_ERROR_DISINTf, 2743 INVALIDf, INVALIDr, INVALIDf, 2744 INVALIDr, INVALIDf}, 2745 2746 { 0x0080, INVALIDm, "ENQ CFG SRC_PORT_STATE_CORRECTED_ERROR", 2747 SRC_PORT_STATE_CORRECTED_ERRORf, SRC_PORT_STATE_CORRECTED_ERROR_DISINTf, 2748 INVALIDf, INVALIDr, INVALIDf, 2749 INVALIDr, INVALIDf}, 2750 { 0x0040, INVALIDm, "ENQ CFG SRC_PORT_STATE_UNCORRECTED_ERROR", 2751 SRC_PORT_STATE_UNCORRECTED_ERRORf, SRC_PORT_STATE_UNCORRECTED_ERROR_DISINTf, 2752 INVALIDf, INVALIDr, INVALIDf, 2753 INVALIDr, INVALIDf}, 2754 2755 { 0x0020, INVALIDm, "ENQ CFG SOP_STORE_CORRECTED_ERROR", 2756 SOP_STORE_CORRECTED_ERRORf, SOP_STORE_CORRECTED_ERROR_DISINTf, 2757 INVALIDf, INVALIDr, INVALIDf, 2758 INVALIDr, INVALIDf}, 2759 { 0x0010, INVALIDm, "ENQ CFG SOP_STORE_UNCORRECTED_ERROR", 2760 SOP_STORE_UNCORRECTED_ERRORf, SOP_STORE_UNCORRECTED_ERROR_DISINTf, 2761 INVALIDf, INVALIDr, INVALIDf, 2762 INVALIDr, INVALIDf}, 2763 2764 { 0x0008, INVALIDm, "ENQ CFG RQE_WR_COMPLETE_CORRECTED_ERROR", 2765 RQE_WR_COMPLETE_CORRECTED_ERRORf, RQE_WR_COMPLETE_CORRECTED_ERROR_DISINTf, 2766 INVALIDf, INVALIDr, INVALIDf, 2767 INVALIDr, INVALIDf}, 2768 { 0x0004, INVALIDm, "ENQ CFG RQE_WR_COMPLETE_UNCORRECTED_ERROR", 2769 RQE_WR_COMPLETE_UNCORRECTED_ERRORf, RQE_WR_COMPLETE_UNCORRECTED_ERROR_DISINTf, 2770 INVALIDf, INVALIDr, INVALIDf, 2771 INVALIDr, INVALIDf}, 2772 2773 { 0x0002, INVALIDm, "ENQ CFG CBP_32B_WR_STORE_CORRECTED_ERROR", 2774 CBP_32B_WR_STORE_CORRECTED_ERRORf, CBP_32B_WR_STORE_CORRECTED_ERROR_DISINTf, 2775 INVALIDf, INVALIDr, INVALIDf, 2776 INVALIDr, INVALIDf}, 2777 { 0x0001, INVALIDm, "ENQ CFG CBP_32B_WR_STORE_UNCORRECTED_ERROR", 2778 CBP_32B_WR_STORE_UNCORRECTED_ERRORf, CBP_32B_WR_STORE_UNCORRECTED_ERROR_DISINTf, 2779 INVALIDf, INVALIDr, INVALIDf, 2780 INVALIDr, INVALIDf}, 2781 2782 { 0 } /* table terminator */ 2783 2784 }; 2785 2786 2787 STATIC 2788 _soc_saber2_mmu_sub_block_one_level_t _soc_metrolite_mmu_sub_blocks_type_1[] = { 2789 2790 { 0x00000004, 2791 _SOC_SABER2_MMU_SUBBLOCK_LLS, 2792 LLS_INTR_DISINTf, 2793 LLS_INTRf, 2794 LLS_L0_ECC_ERROR1_MASKr, 2795 LLS_L0_ECC_ERROR1r, 2796 _soc_saber2_mmu_sb_lls_l0_parity_info}, 2797 2798 { 0x00000004, 2799 _SOC_SABER2_MMU_SUBBLOCK_LLS, 2800 LLS_INTR_DISINTf, 2801 LLS_INTRf, 2802 LLS_L1_ECC_ERROR1_MASKr, 2803 LLS_L1_ECC_ERROR1r, 2804 _soc_saber2_mmu_sb_lls_l1_parity_info}, 2805 2806 { 0x00000004, 2807 _SOC_SABER2_MMU_SUBBLOCK_LLS, 2808 LLS_INTR_DISINTf, 2809 LLS_INTRf, 2810 LLS_L2_ECC_ERROR1_MASKr, 2811 LLS_L2_ECC_ERROR1r, 2812 _soc_saber2_mmu_sb_lls_l2_parity_info}, 2813 2814 { 0x00000004, 2815 _SOC_SABER2_MMU_SUBBLOCK_LLS, 2816 LLS_INTR_DISINTf, 2817 LLS_INTRf, 2818 LLS_PORT_ECC_ERROR_MASKr, 2819 LLS_PORT_ECC_ERRORr, 2820 _soc_saber2_mmu_sb_lls_port_parity_info}, 2821 2822 { 0x00000008, 2823 _SOC_SABER2_MMU_SUBBLOCK_AGING_INT, 2824 AGING_INTR_DISINTf, 2825 AGING_INTRf, 2826 AGING_ERROR_MASK_INTr, 2827 AGING_ERROR_INTr, 2828 _soc_saber2_mmu_sb_aging_int_parity_info}, 2829 2830 { 0x00000010, 2831 _SOC_SABER2_MMU_SUBBLOCK_CCP, 2832 CCP_INTR_DISINTf, 2833 CCP_INTRf, 2834 CCP_ERROR_MASKr, 2835 CCP_ERRORr, 2836 _soc_saber2_mmu_sb_ccp_parity_info}, 2837 2838 { 0x00000020, 2839 _SOC_SABER2_MMU_SUBBLOCK_CFAPI, 2840 CFAP_INTR_DISINTf, 2841 CFAP_INTRf, 2842 CFAPI_ERROR_MASKr, 2843 CFAPI_ECC_ERRORr, 2844 _soc_saber2_mmu_sb_cfapi_parity_info}, 2845 2846 { 0x00000040, 2847 _SOC_SABER2_MMU_SUBBLOCK_CTR, 2848 CTR_INTR_DISINTf, 2849 CTR_INTRf, 2850 CTR_ERROR_MASKr, 2851 CTR_ERRORr, 2852 _soc_saber2_mmu_sb_ctr_parity_info}, 2853 2854 { 0x00000080, 2855 _SOC_SABER2_MMU_SUBBLOCK_DEQ, 2856 DEQ_INTR_DISINTf, 2857 DEQ_INTRf, 2858 DEQ_ERROR_MASK_1r, 2859 DEQ_ERROR_1r, 2860 _soc_metrolite_mmu_sb_deq1_parity_info}, 2861 2862 { 0x00000100, 2863 _SOC_SABER2_MMU_SUBBLOCK_RQE_EXTQ, 2864 RQE_INTR_DISINTf, 2865 RQE_INTRf, 2866 RQE_SER_MASKr, 2867 RQE_SER_STATUSr, 2868 _soc_saber2_mmu_sb_rqe_parity_info}, 2869 2870 { 0x00000200, 2871 _SOC_SABER2_MMU_SUBBLOCK_THDO_STATUS1, 2872 THDO_INTR_DISINTf, 2873 THDO_INTRf, 2874 THDO_PARITY_ERROR_MASK1r, 2875 THDO_PARITY_ERROR_STATUS1r, 2876 _soc_saber2_mmu_sb_thdo_stat1_parity_info}, 2877 2878 { 0x00000200, 2879 _SOC_SABER2_MMU_SUBBLOCK_THDO_STATUS2, 2880 THDO_INTR_DISINTf, 2881 THDO_INTRf, 2882 THDO_PARITY_ERROR_MASK2r, 2883 THDO_PARITY_ERROR_STATUS2r, 2884 _soc_saber2_mmu_sb_thdo_stat2_parity_info}, 2885 2886 { 0x00000400, 2887 _SOC_SABER2_MMU_SUBBLOCK_WRED, 2888 WRED_INTR_DISINTf, 2889 WRED_INTRf, 2890 WRED_PARITY_ERROR_MASKr, 2891 WRED_PARITY_ERROR_BITMAPr, 2892 _soc_saber2_mmu_sb_wred_parity_info}, 2893 2894 { 0x00000400, 2895 _SOC_SABER2_MMU_SUBBLOCK_WRED, 2896 WRED_INTR_DISINTf, 2897 WRED_INTRf, 2898 WRED_PROFILE_PARITY_ERROR_MASKr, 2899 WRED_PROFILE_PARITY_ERROR_BITMAPr, 2900 _soc_saber2_mmu_sb_wred_profile_parity_info}, 2901 2902 { 0x00000800, 2903 _SOC_SABER2_MMU_SUBBLOCK_ENQ_CFG, 2904 ENQ_INTR_DISINTf, 2905 ENQ_INTRf, 2906 MMU_ENQ_CFG_ECC_ERROR_0_MASKr, 2907 MMU_ENQ_CFG_ECC_ERROR_0r, 2908 _soc_metrolite_mmu_sb_enq_cfg_parity_info}, 2909 2910 { 0x00000800, 2911 _SOC_SABER2_MMU_SUBBLOCK_ENQ_FAP, 2912 ENQ_INTR_DISINTf, 2913 ENQ_INTRf, 2914 MMU_ENQ_FAP_ECC_ERROR_0_MASKr, 2915 MMU_ENQ_FAP_ECC_ERROR_0r, 2916 _soc_saber2_mmu_sb_enq_fap_parity_info}, 2917 2918 { 0x00001000, 2919 _SOC_SABER2_MMU_SUBBLOCK_THDI, 2920 THDI_INTR_DISINTf, 2921 THDI_INTRf, 2922 MMU_THDI_INTR_MASKr, 2923 MMU_THDI_INTRr, 2924 _soc_saber2_mmu_sb_thdi_parity_info}, 2925 2926 { 0x00004000, 2927 _SOC_SABER2_MMU_SUBBLOCK_INTFI_ECC, 2928 INTF1_INTR_DISINTf, 2929 INTFI_INTRf, 2930 INTFI_ECC_INTR_MASKr, 2931 ST_TRANS_TBL_ECC_ERR1r, 2932 _soc_saber2_mmu_sb_inti_1_parity_info}, 2933 2934 { 0x00004000, 2935 _SOC_SABER2_MMU_SUBBLOCK_INTFI_ECC, 2936 INTF1_INTR_DISINTf, 2937 INTFI_INTRf, 2938 INTFI_ECC_INTR_MASKr, 2939 ST_TRANS_TBL_ECC_ERR2r, 2940 _soc_saber2_mmu_sb_inti_2_parity_info}, 2941 2942 { 0x00008000, 2943 _SOC_SABER2_MMU_SUBBLOCK_MEM1, 2944 MEM1_INTR_DISINTf, 2945 MEM1_INTRf, 2946 CLINK_ERROR_MASKr, 2947 CLINK_ERRORr, 2948 _soc_saber2_mmu_sb_mem1_parity_info }, 2949 2950 { 0x00010000, 2951 _SOC_SABER2_MMU_SUBBLOCK_INFO2, 2952 INFO2_INTR_DISINTf, 2953 INFO2_INTRf, 2954 CHFC_TC2PRI_TBL_ECC_CONFIGr, 2955 CHFC_TC2PRI_TBL_ECC_ERR1r, 2956 _soc_saber2_mmu_sb_info2_1_parity_info }, 2957 2958 { 0x00010000, 2959 _SOC_SABER2_MMU_SUBBLOCK_INFO2, 2960 INFO2_INTR_DISINTf, 2961 INFO2_INTRf, 2962 CHFC_TC2PRI_TBL_ECC_CONFIGr, 2963 CHFC_TC2PRI_TBL_ECC_ERR2r, 2964 _soc_saber2_mmu_sb_info2_2_parity_info }, 2965 2966 { 0x00020000, 2967 _SOC_SABER2_MMU_SUBBLOCK_RDE, 2968 RDE_INTR_DISINTf, 2969 RDE_INTRf, 2970 RDE_SER_MASKr, 2971 RDE_SER_STATUSr, 2972 _soc_saber2_mmu_sb_rde_parity_info }, 2973 2974 { 0x00040000, 2975 _SOC_SABER2_MMU_SUBBLOCK_IPCTR, 2976 IPCTR_INTR_DISINTf, 2977 IPCTR_INTRf, 2978 MMU_IPCTR_ECC_ERROR_0_MASKr, 2979 MMU_IPCTR_ECC_ERROR_0r, 2980 _soc_saber2_mmu_sb_ipctr_parity_info }, 2981 2982 { 0 } /* table terminator */ 2983 2984 }; 2985 2986 STATIC 2987 _soc_saber2_mmu_sub_block_two_level_t _soc_metrolite_mmu_sub_blocks_type_2[] = { 2988 2989 { 0x00000001, 2990 _SOC_SABER2_MMU_SUBBLOCK_TOQ, 2991 TOQ_INTR_DISINTf, 2992 TOQ_INTRf, 2993 TOQ_INTERRUPT_MASKr, 2994 TOQ_INTERRUPTr, 2995 _soc_saber2_mmu_sb_toq_parity_info}, 2996 2997 { 0x00000002, 2998 _SOC_SABER2_MMU_SUBBLOCK_QSTRUCT, 2999 QSTRUCT_INTR_DISINTf, 3000 QSTRUCT_INTRf, 3001 QSTRUCT_INTERRUPT_MASKr, 3002 QSTRUCT_INTERRUPTr, 3003 _soc_saber2_mmu_sb_qstruct_parity_info}, 3004 3005 { 0 } /* table terminator */ 3006 3007 }; 3008 3009 #endif 3010 3011 3012 /* SER processing for TCAMs */ 3013 static _soc_generic_ser_info_t *_soc_saber2_tcam_ser_info[SOC_MAX_NUM_DEVICES]; 3014 3015 3016 STATIC _soc_generic_ser_info_t _soc_saber2_tcam_ser_info_template[] = { 3017 3018 { L3_DEFIPm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_4BITS, 3019 _SOC_SER_INTERLEAVE_MOD2, 3020 { {0, 97}, {1, 97}, {98, 193}, {99, 193} }, 0, 0, 0, 0, 3021 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_SIZE_VERIFY | 3022 _SOC_SER_FLAG_NO_DMA | _SOC_SER_FLAG_REMAP_READ}, 3023 3024 { L2_USER_ENTRYm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_4BITS, 3025 _SOC_SER_INTERLEAVE_MOD2, 3026 { {0, 121}, {1, 121}, {122, 241}, {122, 241} }, 0, 0, 0, 0, 3027 _SOC_SER_FLAG_XY_READ }, 3028 3029 { CPU_COS_MAPm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_4BITS, 3030 _SOC_SER_INTERLEAVE_MOD2, 3031 { {0, 120}, {1, 120}, {121, 240}, {122, 240} }, 0, 0, 0, 0, 3032 _SOC_SER_FLAG_XY_READ }, 3033 3034 { SUBPORT_TAG_TO_PP_PORT_MAPm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_4BITS, 3035 _SOC_SER_INTERLEAVE_NONE, 3036 { {0, 121}, {1, 121}, {122, 241}, {123, 241} }, 0, 0, 0, 0, 3037 _SOC_SER_FLAG_XY_READ }, 3038 3039 { L3_TUNNELm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_4BITS, 3040 _SOC_SER_INTERLEAVE_NONE, 3041 { {0, 121}, {1, 121}, {122, 241}, {123, 241} }, 0, 0, 0, 0, 3042 _SOC_SER_FLAG_XY_READ }, 3043 3044 /* FP_GLOBAL_MASK_TCAM */ 3045 { FP_GLOBAL_MASK_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_4BITS, 3046 _SOC_SER_INTERLEAVE_MOD2, 3047 { {0, 120}, {1, 120}, {121, 240}, {122, 240} }, 0, 0, 0, 0, 3048 _SOC_SER_FLAG_XY_READ }, 3049 3050 /* EGR_SAT_SAMP_TCAM */ 3051 { EGR_SAT_SAMP_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_4BITS, 3052 _SOC_SER_INTERLEAVE_MOD2, 3053 { {0, 237}, {1, 237}, {238, 473}, {239, 473} }, 0, 0, 0, 0, 3054 _SOC_SER_FLAG_XY_READ }, 3055 3056 { EFP_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_4BITS, 3057 _SOC_SER_INTERLEAVE_MOD2, 3058 { {0, 237}, {1, 237}, {238, 473}, {239, 473} }, 0, 0, 0, 0, 3059 _SOC_SER_FLAG_XY_READ }, 3060 3061 { VFP_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_4BITS, 3062 _SOC_SER_INTERLEAVE_MOD2, 3063 { {0, 237}, {1, 237}, {238, 473}, {239, 473} }, 0, 0, 0, 0, 3064 _SOC_SER_FLAG_XY_READ }, 3065 3066 { FP_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_4BITS, 3067 _SOC_SER_INTERLEAVE_MOD2, 3068 { {0, 237}, {1, 237}, {238, 473}, {238, 473} }, 0, 0, 0, 0, 3069 _SOC_SER_FLAG_XY_READ }, 3070 3071 /* ING_SAT_SAMP_TCAM */ 3072 { ING_SAT_SAMP_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_4BITS, 3073 _SOC_SER_INTERLEAVE_MOD2, 3074 { {0, 237}, {1, 237}, {238, 473}, {239, 473} }, 0, 0, 0, 0, 3075 _SOC_SER_FLAG_XY_READ }, 3076 3077 /* VLAN_SUBNET_ONLY */ 3078 { VLAN_SUBNETm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_4BITS, 3079 _SOC_SER_INTERLEAVE_MOD2, 3080 { {0, 64}, {1, 64}, {65, 128}, {66, 128} }, 0, 0, 0, 0, 3081 _SOC_SER_FLAG_XY_READ }, 3082 3083 { MY_STATION_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_4BITS, 3084 _SOC_SER_INTERLEAVE_MOD2, 3085 { {0, 80}, {1, 80}, {81, 160}, {82, 160} }, 0, 0, 0, 0, 3086 _SOC_SER_FLAG_XY_READ }, 3087 3088 { FP_UDF_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_4BITS, 3089 _SOC_SER_INTERLEAVE_NONE, 3090 { {0, 80}, {1, 80}, {81, 160}, {82, 160} }, 0, 0, 0, 0, 3091 _SOC_SER_FLAG_XY_READ }, 3092 3093 /* end flag */ 3094 { INVALIDm }, 3095 3096 }; 3097 3098 STATIC 3099 _soc_saber2_fifo_ser_info_t _soc_saber2_ep_ser_info[] = { 3100 3101 { EFP_POLICY_PARITY_CONTROLr, PARITY_ENf, 0, EFP_POLICY_TABLEm, INVALIDr, "", EVEN_PARITYf }, 3102 { EGR_PW_INIT_COUNTERS_PARITY_CONTROLr, PARITY_ENf, 0, EGR_PW_INIT_COUNTERSm, INVALIDr, "", EVEN_PARITYf }, 3103 { EFP_METER_PARITY_CONTROLr, PARITY_ENf, 0, EFP_METER_TABLEm, INVALIDr, "", EVEN_PARITYf }, 3104 { EGR_VLAN_ECC_PARITY_CONTROLr, EGR_PCP_DE_MAPPING_PARITY_ENf, 0, EGR_PCP_DE_MAPPINGm, INVALIDr, "", EVEN_PARITYf }, 3105 { EGR_1588_SA_PARITY_CONTROLr, PARITY_ENf, 0, EGR_1588_SAm, INVALIDr, "", EVEN_PARITYf }, 3106 { EGR_EHCPM_ECC_PARITY_CONTROLr, MOD_MAP_PARITY_ENf, 0, EGR_MOD_MAP_TABLEm, INVALIDr, "", EVEN_PARITYf }, 3107 { EGR_1588_LINK_DELAY_64_PARITY_CONTROLr, PARITY_ENf, 1, INVALIDm, EGR_1588_LINK_DELAY_64r, "", PARITYf }, 3108 { EGR_EHCPM_ECC_PARITY_CONTROLr, SF_SRC_MODID_CHECK_PARITY_ENf, 1, INVALIDm, EGR_SF_SRC_MODID_CHECKr, "", PARITYf }, 3109 { EGR_SAT_SAMP_DATA_PARITY_CONTROLr, PARITY_ENf, 0, EGR_SAT_SAMP_DATAm, INVALIDr, "", EVEN_PARITYf }, 3110 /* Not support EGR_VLAN_CONTROL_1r */ 3111 { EGR_EL3_ECC_PARITY_CONTROLr, EGR_MAP_MH_PARITY_ENf, 0, EGR_MAP_MHm, INVALIDr, "", EVEN_PARITYf }, 3112 /* Not support EGR_PMOD_PKT_LEN_BUF (not defined in Allenum.h) */ 3113 { EGR_EHCPM_ECC_PARITY_CONTROLr, INITBUF_ECC_ENf, 0, INVALIDm, INVALIDr, "INIT BUFF", INVALIDf }, 3114 { EGR_VLAN_ECC_PARITY_CONTROLr, EGR_VLAN_STG_PARITY_ENf, 0, EGR_VLAN_STGm, INVALIDr, "", EVEN_PARITYf }, 3115 { EGR_EL3_ECC_PARITY_CONTROLr, EGR_L3_NEXT_HOP_ECC_ENf, 0, EGR_L3_NEXT_HOPm, INVALIDr, "", ECCf }, 3116 { EGR_EL3_ECC_PARITY_CONTROLr, EGR_MAC_DA_PROFILE_PARITY_ENf, 0, EGR_MAC_DA_PROFILEm, INVALIDr, "", EVEN_PARITYf }, 3117 { EGR_EL3_ECC_PARITY_CONTROLr, EGR_L3_INTF_ECC_ENf, 0, EGR_L3_INTFm, INVALIDr, "", ECCf }, 3118 { EGR_EL3_ECC_PARITY_CONTROLr, EGR_DVP_ATTRIBUTE_ECC_ENf, 0, EGR_DVP_ATTRIBUTEm, INVALIDr, "", ECCf }, 3119 { EGR_EL3_ECC_PARITY_CONTROLr, EGR_VFI_PARITY_ENf, 0, EGR_VFIm, INVALIDr, "", EVEN_PARITYf }, 3120 { EGR_EL3_ECC_PARITY_CONTROLr, EGR_IPMC_PARITY_ENf, 0, EGR_IPMCm, INVALIDr, "", EVEN_PARITYf }, 3121 { EGR_EL3_ECC_PARITY_CONTROLr, EGR_QUEUE_TO_PP_PORT_MAP_PARITY_ENf, 0, EGR_QUEUE_TO_PP_PORT_MAPm, INVALIDr, "", EVEN_PARITYf }, 3122 { EGR_EL3_ECC_PARITY_CONTROLr, EGR_PORT_PARITY_ENf, 0, EGR_PORTm, INVALIDr, "", EVEN_PARITYf }, 3123 { EGR_EFPMOD_PARITY_CONTROLr, FLEX_CTR_TOS_MAP_PAR_ENf, 0, EGR_FLEX_CTR_TOS_MAPm, INVALIDr, "", EVEN_PARITYf }, 3124 { EGR_EFPMOD_PARITY_CONTROLr, FLEX_CTR_PKT_PRI_MAP_PAR_ENf, 0, EGR_FLEX_CTR_PKT_PRI_MAPm, INVALIDr, "", EVEN_PARITYf }, 3125 /* The EGR_MIRROR_ENCAP_DATA_1/2 is set as SER_RESPONSE => SER_NONE, no correction */ 3126 { EGR_EPMOD_PARITY_CONTROLr, MIRROR_ENCAP_DATA_1_ENf, 0, EGR_MIRROR_ENCAP_DATA_1m, INVALIDr, "", EVEN_PARITYf }, 3127 { EGR_EPMOD_PARITY_CONTROLr, MIRROR_ENCAP_DATA_2_ENf, 0, EGR_MIRROR_ENCAP_DATA_2m, INVALIDr, "", EVEN_PARITYf }, 3128 { EGR_VLAN_ECC_PARITY_CONTROLr, EGR_PRI_CNG_MAP_PARITY_ENf, 0, EGR_PRI_CNG_MAPm, INVALIDr, "", EVEN_PARITYf }, 3129 { EGR_VLAN_ECC_PARITY_CONTROLr, EGR_IP_TUNNEL_ECC_ENf, 0, EGR_IP_TUNNELm, INVALIDr, "", ECCf }, 3130 { EGR_VLAN_ECC_PARITY_CONTROLr, EGR_IP_TUNNEL_ECC_ENf, 0, EGR_IP_TUNNEL_MPLSm, INVALIDr, "", ECCf }, 3131 { EGR_VLAN_ECC_PARITY_CONTROLr, EGR_IP_TUNNEL_ECC_ENf, 0, EGR_IP_TUNNEL_IPV6m, INVALIDr, "", EVEN_PARITY_LOWERf }, 3132 { EGR_VLAN_ECC_PARITY_CONTROLr, EGR_DSCP_TABLE_PARITY_ENf, 0, EGR_DSCP_TABLEm, INVALIDr, "", EVEN_PARITYf }, 3133 { EGR_VLAN_ECC_PARITY_CONTROLr, EGR_VLAN_XLATE_ECC_ENf, 0, EGR_VLAN_XLATEm, INVALIDr, "", ECCf }, 3134 { EGR_VLAN_ECC_PARITY_CONTROLr, EGR_MPLS_EXP_MAPPING_1_PARITY_ENf, 0, EGR_MPLS_EXP_MAPPING_1m, INVALIDr, "", EVEN_PARITYf }, 3135 { EGR_VLAN_ECC_PARITY_CONTROLr, EGR_MPLS_EXP_MAPPING_2_PARITY_ENf, 0, EGR_MPLS_EXP_MAPPING_2m, INVALIDr, "", EVEN_PARITYf }, 3136 { EGR_VLAN_ECC_PARITY_CONTROLr, EGR_FRAGMENT_ID_TABLE_PARITY_ENf, 0, EGR_FRAGMENT_ID_TABLEm, INVALIDr, "", EVEN_PARITYf }, 3137 { EGR_VLAN_ECC_PARITY_CONTROLr, EGR_GPP_ATTRIBUTES_ECC_ENf, 0, EGR_GPP_ATTRIBUTESm, INVALIDr, "", EVEN_PARITYf }, 3138 { EGR_OAM_OPCODE_GROUP_PARITY_CONTROLr, PARITY_ENf, 0, EGR_OAM_OPCODE_GROUPm, INVALIDr, "", EVEN_PARITYf }, 3139 { EGR_MA_INDEX_ECC_CONTROLr, ECC_ENf, 0, EGR_MA_INDEXm, INVALIDr, "", EVEN_PARITYf }, 3140 { EGR_MP_GROUP_ECC_CONTROLr, ECC_ENf, 0, EGR_MP_GROUPm, INVALIDr, "", EVEN_PARITYf }, 3141 { EGR_OAM_FLEXIBLE_DOMAIN_CONTROL_PARITY_CONTROLr, PARITY_ENf, 0, EGR_OAM_FLEXIBLE_DOMAIN_CONTROLm, INVALIDr, "", EVEN_PARITYf }, 3142 { EGR_OAM_OPCODE_CONTROL_PROFILE_PARITY_CONTROLr, PARITY_ENf, 0, EGR_OAM_OPCODE_CONTROL_PROFILEm, INVALIDr, "", EVEN_PARITYf }, 3143 { EGR_EDATABUF_PARITY_CONTROLr, LP_ECC_ENf, 0, INVALIDm, INVALIDr, "EP_EDATABUF_LP_MEM", INVALIDf }, 3144 { EGR_EDATABUF_PARITY_CONTROLr, EFPCTR_PAR_ENf, 0, EFP_COUNTER_TABLEm, INVALIDr, "" , EVEN_PARITYf}, 3145 { EGR_EDATABUF_PARITY_CONTROLr, STATS_PAR_ENf, 0, INVALIDm, INVALIDr, "Egress stats counter memory", INVALIDf }, 3146 { EGR_EDATABUF_PARITY_CONTROLr, RESI_ECC_ENf, 0, INVALIDm, INVALIDr, "EP_EDATABUF_RESI_MEM", INVALIDf }, 3147 { EGR_EDATABUF_PARITY_CONTROLr, CM_ECC_ENf, 0, INVALIDm, INVALIDr, "EP_EDATABUF_CM_MEM", INVALIDf }, 3148 { IARB_LEARN_FIFO_ECC_CONTROLr, ECC_ENf, 0, INVALIDm, INVALIDr, "IARB_LEARN_FIFO_PIPE_X", INVALIDf }, 3149 { EGR_VLAN_ECC_PARITY_CONTROLr, EGR_VLAN_ECC_ENf, 0, EGR_VLANm, INVALIDr, "", ECCf }, 3150 3151 { EGR_EL3_ECC_PARITY_CONTROLr, EGR_MPLS_VC_AND_SWAP_LABEL_TABLE_ECC_ENf, 0, EGR_MPLS_VC_AND_SWAP_LABEL_TABLEm, INVALIDr, "", ECCf }, 3152 3153 /* These mem/regs are removed in 56270 */ 3154 { EGR_VLAN_ECC_PARITY_CONTROLr, EGR_VLAN_CONTROL_2_PARITY_ENf, 1, INVALIDm, EGR_VLAN_CONTROL_2r, "", PARITYf }, 3155 { EGR_VLAN_ECC_PARITY_CONTROLr, EGR_VLAN_CONTROL_3_PARITY_ENf, 1, INVALIDm, EGR_VLAN_CONTROL_3r, "", PARITYf }, 3156 { EGR_VLAN_ECC_PARITY_CONTROLr, EGR_GPP_ATTRIBUTES_MODBASE_PARITY_ENf, 0, EGR_GPP_ATTRIBUTES_MODBASEm, INVALIDr, "", EVEN_PARITYf }, 3157 { EGR_VLAN_ECC_PARITY_CONTROLr, EGR_PVLAN_EPORT_CONTROL_PARITY_ENf, 1, INVALIDm, EGR_PVLAN_EPORT_CONTROLr, "", PARITYf }, 3158 3159 /* These memories have deleted the ECC or Parity field in 56270 */ 3160 { EGR_EPMOD_PARITY_CONTROLr, MTU_ENf, 1, INVALIDm, EGR_MTUr, "", PARITYf }, 3161 { EGR_EPMOD_PARITY_CONTROLr, COUNTER_CONTROL_ENf, 1, INVALIDm, EGR_COUNTER_CONTROLr, "", PARITYf }, 3162 { EGR_EHCPM_ECC_PARITY_CONTROLr, SAT_SAMP_DATA_1_ENf, 0, EGR_SAT_SAMP_DATA_1m, INVALIDr, "", EVEN_PARITYf }, 3163 { EGR_EL3_ECC_PARITY_CONTROLr, EGR_IPMC_CFG2_PARITY_ENf, 1, INVALIDm, EGR_IPMC_CFG2r, "", PARITYf }, 3164 3165 #ifdef BCM_METROLITE_SUPPORT 3166 /* These mem/regs are added in 56270 */ 3167 { EGR_EFPMOD_PARITY_CONTROLr, MCPE0_CNTXT_BUFFER_PAR_ENf, 0, INVALIDm, INVALIDr, "EGR_EFPMOD_MCPE0_CNTXT_BUFFER", INVALIDf }, 3168 { EGR_EFPMOD_PARITY_CONTROLr, MCPE1_CNTXT_BUFFER_PAR_ENf, 0, INVALIDm, INVALIDr, "EGR_EFPMOD_MCPE1_CNTXT_BUFFER", INVALIDf }, 3169 #endif 3170 3171 /* end flag */ 3172 { INVALIDr } 3173 3174 }; 3175 3176 STATIC 3177 _soc_saber2_fifo_ser_info_t _soc_saber2_ip_ser_info[] = { 3178 3179 { VLAN_SUBNET_PARITY_CONTROLr, PARITY_ENf, 0, VLAN_SUBNET_DATA_ONLYm, INVALIDr, "", EVEN_PARITYf }, 3180 { MY_STATION_DATA_PARITY_CONTROLr, PARITY_ENf, 0, MY_STATION_TCAM_DATA_ONLYm, INVALIDr, "", EVEN_PARITYf }, 3181 { VRF_PARITY_CONTROLr, PARITY_ENf, 0, VRFm, INVALIDr, "", EVEN_PARITYf }, 3182 { VLAN_STG_PARITY_CONTROLr, PARITY_ENf, 0, STG_TABm, INVALIDr, "", EVEN_PARITYf }, 3183 { RTAG7_FLOW_BASED_HASH_PARITY_CONTROLr, PARITY_ENf, 0, RTAG7_FLOW_BASED_HASHm, INVALIDr, "", EVEN_PARITYf }, 3184 { VFP_POLICY_ECC_CONTROLr, ECC_ENf, 0, VFP_POLICY_TABLEm, INVALIDr, "", ECCf }, 3185 { SOURCE_VP_ECC_CONTROLr, ECC_ENf, 0, SOURCE_VPm, INVALIDr, "", ECCf }, 3186 { L3_IIF_ECC_CONTROLr, ECC_ENf, 0, L3_IIFm, INVALIDr, "", ECCf }, 3187 { VFI_ECC_CONTROLr, ECC_ENf, 0, VFIm, INVALIDr, "", ECCf }, 3188 { VFI_1_PARITY_CONTROLr, PARITY_ENf, 0, VFI_1m, INVALIDr, "", EVEN_PARITYf }, 3189 { L2_MOD_FIFO_PARITY_CONTROLr, PARITY_ENf, 0, L2_MOD_FIFOm, INVALIDr, "", EVEN_PARITYf }, 3190 { RTAG7_PORT_BASED_HASH_PARITY_CONTROLr, PARITY_ENf, 0, RTAG7_PORT_BASED_HASHm, INVALIDr, "", EVEN_PARITYf }, 3191 { MAID_REDUCTION_PARITY_CONTROLr, PARITY_ENf, 0, MAID_REDUCTIONm, INVALIDr, "", EVEN_PARITYf }, 3192 { L3_IPMC_1_ECCP_CONTROLr, ECC_ENf, 0, L3_IPMC_1m, INVALIDr, "", PARITYf }, 3193 { INITIAL_L3_ECMP_GROUP_ECCP_CONTROLr, ECC_ENf, 0, INITIAL_L3_ECMP_GROUPm, INVALIDr, "", PARITYf }, 3194 { INITIAL_PROT_NHI_TABLE_ECCP_CONTROLr, ECC_ENf, 0, INITIAL_PROT_NHI_TABLEm, INVALIDr, "", PARITYf }, 3195 { INITIAL_ING_L3_NEXT_HOP_ECCP_CONTROLr, ECC_ENf, 0, INITIAL_ING_L3_NEXT_HOPm, INVALIDr, "", PARITYf }, 3196 { INITIAL_L3_ECMP_ECCP_CONTROLr, ECC_ENf, 0, INITIAL_L3_ECMPm, INVALIDr, "", PARITYf }, 3197 { ING_DVP_TABLE_ECCP_CONTROLr, ECC_ENf, 0, ING_DVP_TABLEm, INVALIDr, "", ECCf }, 3198 { DSCP_TABLE_PARITY_CONTROLr, PARITY_ENf, 0, DSCP_TABLEm, INVALIDr, "", EVEN_PARITYf }, 3199 { ING_PRI_CNG_MAP_PARITY_CONTROLr, PARITY_ENf, 0, ING_PRI_CNG_MAPm, INVALIDr, "", EVEN_PARITYf }, 3200 { VLAN_MPLS_PARITY_CONTROLr, PARITY_ENf, 0, VLAN_MPLSm, INVALIDr, "", EVEN_PARITYf }, 3201 { INITIAL_PROT_NHI_TABLE_1_DMA_PARITY_CONTROLr, PARITY_ENf, 0, INITIAL_PROT_NHI_TABLE_1_DMAm, INVALIDr, "", EVEN_PARITYf }, 3202 { TTL_FN_PARITY_CONTROLr, PARITY_ENf, 0, TTL_FNm, INVALIDr, "", EVEN_PARITYf }, 3203 { TOS_FN_PARITY_CONTROLr, PARITY_ENf, 0, TOS_FNm, INVALIDr, "", EVEN_PARITYf }, 3204 { ING_SVM_PKT_RES_MAP_PARITY_CONTROLr, PARITY_ENf, 0, ING_SVM_PKT_RES_MAPm, INVALIDr, "", EVEN_PARITYf }, 3205 { ING_SVM_TOS_MAP_PARITY_CONTROLr, PARITY_ENf, 0, ING_SVM_TOS_MAPm, INVALIDr, "", EVEN_PARITYf }, 3206 { ING_SVM_PKT_PRI_MAP_PARITY_CONTROLr, PARITY_ENf, 0, ING_SVM_PKT_PRI_MAPm, INVALIDr, "", EVEN_PARITYf }, 3207 { ING_1588_PROFILE_TABLE_PARITY_CONTROLr, PARITY_ENf, 0, ING_1588_TS_DISPOSITION_PROFILE_TABLEm, INVALIDr, "", EVEN_PARITYf }, 3208 { STORM_CONTROL_METER_CONFIG_PARITY_CONTROLr, PARITY_ENf, 1, INVALIDm, STORM_CONTROL_METER_CONFIGr, "", EVEN_PARITYf }, 3209 { VLAN_XLATE_ECC_CONTROLr, ECC_ENf, 0, VLAN_XLATEm, INVALIDr, "", ECCf }, 3210 { MPLS_ENTRY_ECC_CONTROLr, ECC_ENf, 0, MPLS_ENTRYm, INVALIDr, "", ECCf }, 3211 { VLAN_ECC_CONTROLr, ECC_ENf, 0, VLAN_TABm, INVALIDr, "", ECCf }, 3212 { RX_PROT_GROUP_TABLE_DMA_PARITY_CONTROLr, PARITY_ENf, 0, RX_PROT_GROUP_TABLE_DMAm, INVALIDr, "", EVEN_PARITYf }, 3213 { L2_ENTRY_ECC_CONTROLr, ECC_ENf, 0, L2Xm, INVALIDr, "", ECCf }, 3214 { VLAN_OR_VFI_MAC_COUNT_PARITY_CONTROLr, PARITY_ENf, 0, VLAN_OR_VFI_MAC_COUNTm, INVALIDr, "", EVEN_PARITYf }, 3215 { VLAN_OR_VFI_MAC_LIMIT_ECC_CONTROLr, ECC_ENf, 0, VLAN_OR_VFI_MAC_LIMITm, INVALIDr, "", EVEN_PARITYf }, 3216 { PORT_CBL_TABLE_MODBASE_PARITY_CONTROLr, PARITY_ENf, 0, PORT_CBL_TABLE_MODBASEm, INVALIDr, "", EVEN_PARITYf }, 3217 { RMEP_ECCP_CONTROLr, ECC_ENf, 0, RMEPm, INVALIDr, "", PARITYf }, 3218 { MA_STATE_ECCP_CONTROLr, ECC_ENf, 0, MA_STATEm, INVALIDr, "", PARITYf }, 3219 { PORT_CBL_TABLE_PARITY_CONTROLr, PARITY_ENf, 0, PORT_CBL_TABLEm, INVALIDr, "", EVEN_PARITYf }, 3220 { FP_FIELD_SEL_PARITY_CONTROLr, PARITY_ENf, 0, FP_PORT_FIELD_SELm, INVALIDr, "", EVEN_PARITYf }, 3221 { OAM_OPCODE_GROUP_PARITY_CONTROLr, PARITY_ENf, 0, OAM_OPCODE_GROUPm, INVALIDr, "", EVEN_PARITYf }, 3222 { MA_INDEX_ECC_CONTROLr, ECC_ENf, 0, MA_INDEXm, INVALIDr, "", EVEN_PARITYf }, 3223 { MP_GROUP_ECC_CONTROLr, ECC_ENf, 0, MP_GROUPm, INVALIDr, "", EVEN_PARITYf }, 3224 { OAM_FLEXIBLE_DOMAIN_CONTROL_PARITY_CONTROLr, PARITY_ENf, 0, OAM_FLEXIBLE_DOMAIN_CONTROLm, INVALIDr, "", EVEN_PARITYf }, 3225 { OAM_OPCODE_CONTROL_PROFILE_PARITY_CONTROLr, PARITY_ENf, 0, OAM_OPCODE_CONTROL_PROFILEm, INVALIDr, "", EVEN_PARITYf }, 3226 { IFP_STORM_CONTROL_PARITY_CONTROLr, PARITY_ENf, 0, FP_STORM_CONTROL_METERSm, INVALIDr, "", EVEN_PARITYf }, 3227 { IFP_COUNTER_PARITY_CONTROLr, PARITY_ENf, 0, FP_COUNTER_TABLEm, INVALIDr, "", EVEN_PARITYf }, 3228 { IFP_METER_PARITY_CONTROLr, PARITY_ENf, 0, FP_METER_TABLEm, INVALIDr, "", EVEN_PARITYf }, 3229 { IFP_POLICY_PARITY_CONTROLr, PARITY_ENf, 0, FP_POLICY_TABLEm, INVALIDr, "" ,EVEN_PARITY_0f }, 3230 { ICONTROL_OPCODE_BITMAP_PARITY_CONTROLr, PARITY_ENf, 0, ICONTROL_OPCODE_BITMAPm, INVALIDr, "", EVEN_PARITYf }, 3231 { PHB2_COS_MAP_PARITY_CONTROLr, PARITY_ENf, 0, PHB2_COS_MAPm, INVALIDr, "", EVEN_PARITYf }, 3232 { E2E_HOL_STATUS_PARITY_CONTROLr, PARITY_ENf, 0, E2E_HOL_STATUSm, INVALIDr, "", EVEN_PARITYf }, 3233 { E2E_HOL_STATUS_1_PARITY_CONTROLr, PARITY_ENf, 0, E2E_HOL_STATUS_1m, INVALIDr, "", EVEN_PARITYf }, 3234 { LOCAL_SW_DISABLE_DEFAULT_PBM_PARITY_CONTROLr, PARITY_ENf, 0, LOCAL_SW_DISABLE_DEFAULT_PBMm, INVALIDr, "", EVEN_PARITYf }, 3235 { LOCAL_SW_DISABLE_DEFAULT_PBM_MIRR_PARITY_CONTROLr, PARITY_ENf, 0, LOCAL_SW_DISABLE_DEFAULT_PBM_MIRRm, INVALIDr, "", EVEN_PARITYf }, 3236 { ING_EGRMSKBMAP_PARITY_CONTROLr, PARITY_ENf, 0, ING_EGRMSKBMAPm, INVALIDr, "", EVEN_PARITYf }, 3237 { EMIRROR_CONTROL_PARITY_CONTROLr, PARITY_ENf, 0, EMIRROR_CONTROLm, INVALIDr, "", EVEN_PARITYf }, 3238 { EMIRROR_CONTROL1_PARITY_CONTROLr, PARITY_ENf, 0, EMIRROR_CONTROL1m, INVALIDr, "", EVEN_PARITYf }, 3239 { EMIRROR_CONTROL2_PARITY_CONTROLr, PARITY_ENf, 0, EMIRROR_CONTROL2m, INVALIDr, "", EVEN_PARITYf }, 3240 { EMIRROR_CONTROL3_PARITY_CONTROLr, PARITY_ENf, 0, EMIRROR_CONTROL3m, INVALIDr, "", EVEN_PARITYf }, 3241 { IMIRROR_BITMAP_PARITY_CONTROLr, PARITY_ENf, 0, IMIRROR_BITMAPm, INVALIDr, "", EVEN_PARITYf }, 3242 { UNKNOWN_HGI_BITMAP_PARITY_CONTROLr, PARITY_ENf, 0, UNKNOWN_HGI_BITMAPm, INVALIDr, "", EVEN_PARITYf }, 3243 { VLAN_PROFILE_2_PARITY_CONTROLr, PARITY_ENf, 0, VLAN_PROFILE_2m, INVALIDr, "", EVEN_PARITYf }, 3244 { SW2_EOP_BUFFER_C_PARITY_CONTROLr, PARITY_ENf, 2, INVALIDm, INVALIDr, "SW2_EOP_BUFFER_C", INVALIDf }, 3245 { SRC_MODID_INGRESS_BLOCK_PARITY_CONTROLr, PARITY_ENf, 0, SRC_MODID_INGRESS_BLOCKm, INVALIDr, "", EVEN_PARITYf }, 3246 { ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROLr, PARITY_ENf, 0, ALTERNATE_EMIRROR_BITMAPm, INVALIDr, "", EVEN_PARITYf }, 3247 { NONUCAST_TRUNK_BLOCK_MASK_PARITY_CONTROLr, PARITY_ENf, 0, NONUCAST_TRUNK_BLOCK_MASKm, INVALIDr, "", EVEN_PARITYf }, 3248 { MAC_BLOCK_TABLE_PARITY_CONTROLr, PARITY_ENf, 0, MAC_BLOCKm, INVALIDr, "", EVEN_PARITYf }, 3249 { TRUNK_BITMAP_TABLE_PARITY_CONTROLr, PARITY_ENf, 0, TRUNK_BITMAPm, INVALIDr, "", EVEN_PARITYf }, 3250 /* ING_TRILL_RX_PKTS_ETC can not access */ 3251 { TRILL_RX_PKTS_PARITY_CONTROLr, PARITY_ENf, 2, INVALIDm, INVALIDr, "TRILL_RX_PKTS", INVALIDf }, 3252 /* ISC_IP can not access */ 3253 { IP_COUNTERS_PARITY_CONTROLr, PARITY_ENf, 2, INVALIDm, INVALIDr, "ISC_IP", INVALIDf }, 3254 /* ISC_MEM0/1/2 can not access */ 3255 { RDBGC_MEM_INST0_PARITY_CONTROLr, PARITY_ENf, 2, INVALIDm, INVALIDr, "ISC_MEM0", INVALIDf }, 3256 { RDBGC_MEM_INST1_PARITY_CONTROLr, PARITY_ENf, 2, INVALIDm, INVALIDr, "ISC_MEM1", INVALIDf }, 3257 { RDBGC_MEM_INST2_PARITY_CONTROLr, PARITY_ENf, 2, INVALIDm, INVALIDr, "ISC_MEM2", INVALIDf }, 3258 /* ISC_HIGIG can not access */ 3259 { HG_COUNTERS_PARITY_CONTROLr, PARITY_ENf, 2, INVALIDm, INVALIDr, "ISC_HIGIG", INVALIDf }, 3260 { ING_SERVICE_PRI_MAP_0_PARITY_CONTROLr, PARITY_ENf, 0, ING_SERVICE_PRI_MAP_0m, INVALIDr, "", EVEN_PARITYf}, 3261 { ING_SERVICE_PRI_MAP_1_PARITY_CONTROLr, PARITY_ENf, 0, ING_SERVICE_PRI_MAP_1m, INVALIDr, "", EVEN_PARITYf}, 3262 { ING_SERVICE_PRI_MAP_2_PARITY_CONTROLr, PARITY_ENf, 0, ING_SERVICE_PRI_MAP_2m, INVALIDr, "", EVEN_PARITYf }, 3263 { L3_ECMP_GROUP_ECCP_CONTROLr, ECC_ENf, 0, L3_ECMP_COUNTm, INVALIDr, "", ECC_0f }, 3264 { L3_ECMP_PARITY_CONTROLr, PARITY_ENf, 0, L3_ECMPm, INVALIDr, "", EVEN_PARITYf }, 3265 { L2MC_ECCP_CONTROLr, ECC_ENf, 0, L2MCm, INVALIDr, "", ECCf }, 3266 { L3_IPMC_REMAP_PARITY_CONTROLr, PARITY_ENf, 0, L3_IPMC_REMAPm, INVALIDr, "", EVEN_PARITYf }, 3267 { L3_IPMC_ECCP_CONTROLr, ECC_ENf, 0, L3_IPMCm, INVALIDr, "", ECCf }, 3268 { BCAST_BLOCK_MASK_PARITY_CONTROLr, PARITY_ENf, 0, BCAST_BLOCK_MASKm, INVALIDr, "", EVEN_PARITYf }, 3269 { KNOWN_MCAST_BLOCK_MASK_PARITY_CONTROLr, PARITY_ENf, 0, KNOWN_MCAST_BLOCK_MASKm, INVALIDr, "", EVEN_PARITYf }, 3270 { UNKNOWN_UCAST_BLOCK_MASK_PARITY_CONTROLr, PARITY_ENf, 0, UNKNOWN_UCAST_BLOCK_MASKm, INVALIDr, "", EVEN_PARITYf }, 3271 { UNKNOWN_MCAST_BLOCK_MASK_PARITY_CONTROLr, PARITY_ENf, 0, UNKNOWN_MCAST_BLOCK_MASKm, INVALIDr, "", EVEN_PARITYf }, 3272 { SERVICE_COS_MAP_ECC_CONTROLr, ECC_ENf, 0, SERVICE_COS_MAPm, INVALIDr, "", EVEN_PARITYf }, 3273 { TRUNK_MEMBER_PARITY_CONTROLr, PARITY_ENf, 0, TRUNK_MEMBERm, INVALIDr, "", EVEN_PARITYf }, 3274 { ING_QUEUE_MAP_PARITY_CONTROLr, PARITY_ENf, 0, ING_QUEUE_MAPm, INVALIDr, "", EVEN_PARITYf }, 3275 { ING_FLEX_CTR_PKT_RES_MAP_PARITY_CONTROLr, PARITY_ENf, 0, ING_FLEX_CTR_PKT_RES_MAPm, INVALIDr, "", EVEN_PARITYf }, 3276 /* IFP_HIGHWAY_PASSTHRU can not access by cpu */ 3277 { IFP_PKT_ECC_CONTROLr, ECC_ENf, 2, INVALIDm, INVALIDr, "IFP_HIGHWAY_PASSTHRU", INVALIDf }, 3278 { ING_FLEX_CTR_PRI_CNG_MAP_PARITY_CONTROLr, PARITY_ENf, 0, ING_FLEX_CTR_PRI_CNG_MAPm, INVALIDr, "", EVEN_PARITYf }, 3279 { ING_FLEX_CTR_PKT_PRI_MAP_PARITY_CONTROLr, PARITY_ENf, 0, ING_FLEX_CTR_PKT_PRI_MAPm, INVALIDr, "", EVEN_PARITYf }, 3280 { ING_FLEX_CTR_TOS_MAP_PARITY_CONTROLr, PARITY_ENf, 0, ING_FLEX_CTR_TOS_MAPm, INVALIDr, "", EVEN_PARITYf }, 3281 { IFP_REDIRECTION_PROFILE_PARITY_CONTROLr, PARITY_ENf, 0, IFP_REDIRECTION_PROFILEm, INVALIDr, "", EVEN_PARITYf }, 3282 { ING_PW_TERM_SEQ_NUM_PARITY_CONTROLr, PARITY_ENf, 0, ING_PW_TERM_SEQ_NUMm, INVALIDr, "", EVEN_PARITYf }, 3283 { ING_OAM_LM_COUNTERS_0_ECC_CONTROLr, ECC_ENf, 0, ING_OAM_LM_COUNTERS_0m, INVALIDr, "", EVEN_PARITYf }, 3284 { ING_OAM_LM_COUNTERS_1_ECC_CONTROLr, ECC_ENf, 0, ING_OAM_LM_COUNTERS_1m, INVALIDr, "", EVEN_PARITYf }, 3285 { UDF_OFFSET_ECC_CONTROLr, ECC_ENf, 0, FP_UDF_OFFSETm, INVALIDr, "", EVEN_PARITYf }, 3286 { L3_DEFIP_DATA_ECC_CONTROLr, ECC_ENf, 0, L3_DEFIP_DATA_ONLYm, INVALIDr, "", ECCf }, 3287 /* why has not defined OAM_LM_COUNTERS_2m in Allenum.h 3288 { ING_OAM_LM_COUNTERS_2_ECC_CONTROLr, ECC_ENf, 0, OAM_LM_COUNTERS_2m, INVALIDr, "" }, 3289 */ 3290 { IARB_LEARN_FIFO_ECC_CONTROLr, ECC_ENf, 2, INVALIDm, INVALIDr, "IARB_LEARN_FIFO_ECC_CONTROL", INVALIDf }, 3291 { MOD_MAP_PARITY_CONTROLr, PARITY_ENf, 0, ING_MOD_MAP_TABLEm, INVALIDr, "", EVEN_PARITYf }, 3292 { ING_SAT_SAMP_DATA_PARITY_CONTROLr, PARITY_ENf, 0, ING_SAT_SAMP_DATAm, INVALIDr, "", EVEN_PARITYf }, 3293 { ARB_SER_CONTROLr, LMEP_ECC_ENf, 0, LMEPm, INVALIDr, "", EVEN_PARITYf }, 3294 { ARB_SER_CONTROLr, LMEP_1_ECC_ENf, 0, LMEP_1m, INVALIDr, "", EVEN_PARITYf }, 3295 { SYSTEM_CONFIG_PARITY_CONTROLr, PARITY_ENf, 0, SYSTEM_CONFIG_TABLEm, INVALIDr, "", EVEN_PARITYf }, 3296 { L3_TUNNEL_PARITY_CONTROLr, PARITY_ENf, 0, L3_TUNNEL_DATA_ONLYm, INVALIDr, "", EVEN_PARITYf }, 3297 { DEVICE_STREAM_ID_TO_PP_PORT_MAP_PARITY_CONTROLr, PARITY_ENf, 0, DEVICE_STREAM_ID_TO_PP_PORT_MAPm, INVALIDr, "", EVEN_PARITYf }, 3298 { RX_PROT_GROUP_TABLE_1_DMA_PARITY_CONTROLr, PARITY_ENf, 0, RX_PROT_GROUP_TABLE_1_DMAm, INVALIDr, "", EVEN_PARITYf }, 3299 { VLAN_RANGE_PARITY_CONTROLr, PARITY_ENf, 0, ING_VLAN_RANGEm, INVALIDr, "", EVEN_PARITYf }, 3300 { PTP_LABEL_RANGE_PROFILE_TABLE_PARITY_CONTROLr, PARITY_ENf, 0, PTP_LABEL_RANGE_PROFILE_TABLEm, INVALIDr, "", EVEN_PARITYf }, 3301 3302 { L3_ENTRY_ECC_CONTROLr, ECC_ENf, 0, L3_ENTRY_ONLYm, INVALIDr, "", EVEN_PARITYf }, 3303 { L3_ENTRY_ECC_CONTROLr, ECC_ENf, 0, L3_ENTRY_IPV4_UNICASTm, INVALIDr, "", ECCf }, 3304 { L3_ENTRY_ECC_CONTROLr, ECC_ENf, 0, L3_ENTRY_IPV4_MULTICASTm, INVALIDr, "", ECC_0f }, 3305 { L3_ENTRY_ECC_CONTROLr, ECC_ENf, 0, L3_ENTRY_IPV6_UNICASTm, INVALIDr, "", ECC_0f }, 3306 { L3_ENTRY_ECC_CONTROLr, ECC_ENf, 0, L3_ENTRY_IPV6_MULTICASTm, INVALIDr, "", ECC_0f }, 3307 3308 { SRC_TRUNK_ECC_CONTROLr, ECC_ENf, 0, SOURCE_TRUNK_MAP_TABLEm, INVALIDr, "", ECCf }, 3309 { CPU_TS_PARITY_CONTROLr, PARITY_ENf, 0, CPU_TS_MAPm, INVALIDr, "", EVEN_PARITYf }, 3310 { LPORT_ECC_CONTROLr, ECC_ENf, 0, LPORT_TABm, INVALIDr, "", ECC_0f }, 3311 3312 { ING_L3_NEXT_HOP_ECCP_CONTROLr, ECC_ENf, 0, ING_L3_NEXT_HOPm, INVALIDr, "", ECCf }, 3313 { VLAN_PROFILE_PARITY_CONTROLr, PARITY_ENf, 0, VLAN_PROFILE_TABm, INVALIDr, "", EVEN_PARITYf }, 3314 { PORT_TABLE_ECC_CONTROLr, ECC_ENf, 0, PORT_TABm, INVALIDr, "", ECC_0f }, 3315 { VLAN_PROT_ECC_CONTROLr, ECC_ENf, 0, VLAN_PROTOCOL_DATAm, INVALIDr, "", ECCf }, 3316 3317 /* These mem/regs are removed in 56270 */ 3318 { ING_LMFC_EOP_BUFFER_0_PARITY_CONTROLr, PARITY_ENf, 2, INVALIDm, INVALIDr, "LMFC_EOP_BUFFER_0", INVALIDf }, 3319 { ING_LMFC_EOP_BUFFER_1_PARITY_CONTROLr, PARITY_ENf, 2, INVALIDm, INVALIDr, "LMFC_EOP_BUFFER_1", INVALIDf }, 3320 { ING_LMFC_EOP_BUFFER_2_PARITY_CONTROLr, PARITY_ENf, 2, INVALIDm, INVALIDr, "LMFC_EOP_BUFFER_2", INVALIDf }, 3321 { SW2_EOP_BUFFER_A_PARITY_CONTROLr, PARITY_ENf, 2, INVALIDm, INVALIDr, "SW2_EOP_BUFFER_A", INVALIDf }, 3322 { SW2_EOP_BUFFER_B_PARITY_CONTROLr, PARITY_ENf, 2, INVALIDm, INVALIDr, "SW2_EOP_BUFFER_B", INVALIDf }, 3323 { SFLOW_ING_THRESHOLD_PARITY_CONTROLr, PARITY_ENf, 1, INVALIDm, SFLOW_ING_THRESHOLDr, "", EVEN_PARITYf }, 3324 3325 /* These memories have deleted the ECC or Parity field in 56270 */ 3326 { TRUNK_GROUP_PARITY_CONTROLr, PARITY_ENf, 0, TRUNK_GROUPm, INVALIDr, "", EVEN_PARITYf }, 3327 { EGR_MASK_MODBASE_PARITY_CONTROLr, PARITY_ENf, 0, EGR_MASK_MODBASEm, INVALIDr, "", EVEN_PARITYf }, 3328 { FP_PORT_METER_MAP_PARITY_CONTROLr, PARITY_ENf, 0, FP_PORT_METER_MAPm, INVALIDr, "", EVEN_PARITYf }, 3329 { ING_PHYSICAL_PORT_TABLE_PARITY_CONTROLr, PARITY_ENf, 0, ING_PHYSICAL_PORT_TABLEm, INVALIDr, "", EVEN_PARITYf }, 3330 { SOURCE_TRUNK_MAP_MODVIEW_PARITY_CONTROLr, PARITY_ENf, 0, SOURCE_TRUNK_MAP_MODBASEm, INVALIDr, "", EVEN_PARITYf }, 3331 { SYSTEM_CONFIG_MODVIEW_PARITY_CONTROLr, PARITY_ENf, 0, SYSTEM_CONFIG_TABLE_MODBASEm, INVALIDr, "", EVEN_PARITYf }, 3332 { SUBPORT_TAG_TO_PP_PORT_MAP_DATA_ONLY_PARITY_CONTROLr, PARITY_ENf, 0, SUBPORT_TAG_TO_PP_PORT_MAP_DATA_ONLYm, INVALIDr, "", EVEN_PARITYf }, 3333 3334 /* These SER control registers have been renamed in 56270 */ 3335 { EGR_MASK_ECC_CONTROLr, ECC_ENf, 0, EGR_MASKm, INVALIDr, "", ECCf }, 3336 { L3_MTU_VALUES_ECC_CONTROLr, ECC_ENf, 0, L3_MTU_VALUESm, INVALIDr, "",EVEN_PARITYf }, 3337 { MODPORT_MAP_MIRROR_ECC_CONTROLr, ECC_ENf, 0, MODPORT_MAP_M0m, INVALIDr, "", EVEN_PARITYf }, 3338 { MODPORT_MAP_MIRROR_ECC_CONTROLr, ECC_ENf, 0, MODPORT_MAP_M1m, INVALIDr, "", EVEN_PARITYf }, 3339 { MODPORT_MAP_MIRROR_ECC_CONTROLr, ECC_ENf, 0, MODPORT_MAP_M2m, INVALIDr, "", EVEN_PARITYf }, 3340 { MODPORT_MAP_SW_ECC_CONTROLr, ECC_ENf, 0, MODPORT_MAP_SWm, INVALIDr, "", ECCf }, 3341 { SRC_MODID_EGRESS_ECC_CONTROLr, ECC_ENf, 0, SRC_MODID_EGRESSm, INVALIDr, "", EVEN_PARITYf }, 3342 3343 #ifdef BCM_METROLITE_SUPPORT 3344 /* These SER control registers have been renamed in 56270 */ 3345 { EGR_MASK_PARITY_CONTROLr, PARITY_ENf, 0, EGR_MASKm, INVALIDr, "", EVEN_PARITYf }, 3346 { L3_MTU_VALUES_PARITY_CONTROLr, PARITY_ENf, 0, L3_MTU_VALUESm, INVALIDr, "",EVEN_PARITYf }, 3347 { MODPORT_MAP_MIRROR_PARITY_CONTROLr, PARITY_ENf, 0, MODPORT_MAP_M0m, INVALIDr, "", EVEN_PARITYf }, 3348 { MODPORT_MAP_MIRROR_PARITY_CONTROLr, PARITY_ENf, 0, MODPORT_MAP_M1m, INVALIDr, "", EVEN_PARITYf }, 3349 { MODPORT_MAP_MIRROR_PARITY_CONTROLr, PARITY_ENf, 0, MODPORT_MAP_M2m, INVALIDr, "", EVEN_PARITYf }, 3350 { MODPORT_MAP_SW_PARITY_CONTROLr, PARITY_ENf, 0, MODPORT_MAP_SWm, INVALIDr, "", EVEN_PARITYf }, 3351 { SRC_MODID_EGRESS_PARITY_CONTROLr, PARITY_ENf, 0, SRC_MODID_EGRESSm, INVALIDr, "", EVEN_PARITYf }, 3352 #endif 3353 3354 /* end flag */ 3355 { INVALIDr } 3356 3357 }; 3358 3359 STATIC const 3360 _soc_saber2_fifo_ser_block_info_t _soc_saber2_fifo_ser_block_info[] = { 3361 3362 { SOC_BLK_IPIPE, ING_SER_FIFO_CTRLr, _soc_saber2_ip_ser_info }, 3363 { SOC_BLK_EPIPE, EGR_SER_FIFO_CTRLr, _soc_saber2_ep_ser_info }, 3364 3365 /* end flag */ 3366 { 0 } 3367 3368 }; 3369 3370 3371 STATIC _soc_saber2_parity_info_t _soc_saber2_xport_parity_info[] = { 3372 { _SOC_PARITY_TYPE_ECC, NULL, 0, 3373 TXFIFO_MEM_ERRf, 3374 TXFIFO_MEM_ERRf, 3375 INVALIDm, "TX FIFO", 3376 XPORT_ECC_CONTROLr, TXFIFO_MEM_ENf, 3377 XPORT_TXFIFO_MEM_ECC_STATUSr, NULL, 3378 INVALIDr, NULL }, 3379 { _SOC_PARITY_TYPE_ECC, NULL, 0, 3380 MIB_TSC_MEM0_ERRf, 3381 MIB_TSC_MEM0_ERRf, 3382 INVALIDm, "TX MIB MEM0", 3383 XPORT_ECC_CONTROLr, MIB_TSC_MEM_ENf, 3384 XPORT_MIB_TSC_MEM0_ECC_STATUSr, NULL, 3385 INVALIDr, NULL }, 3386 { _SOC_PARITY_TYPE_ECC, NULL, 0, 3387 MIB_TSC_MEM1_ERRf, 3388 MIB_TSC_MEM1_ERRf, 3389 INVALIDm, "TX MIB MEM1", 3390 XPORT_ECC_CONTROLr, MIB_TSC_MEM_ENf, 3391 XPORT_MIB_TSC_MEM1_ECC_STATUSr, NULL, 3392 INVALIDr, NULL }, 3393 { _SOC_PARITY_TYPE_ECC, NULL, 0, 3394 MIB_TSC_MEM2_ERRf, 3395 MIB_TSC_MEM2_ERRf, 3396 INVALIDm, "TX MIB MEM2", 3397 XPORT_ECC_CONTROLr, MIB_TSC_MEM_ENf, 3398 XPORT_MIB_TSC_MEM2_ECC_STATUSr, NULL, 3399 INVALIDr, NULL }, 3400 { _SOC_PARITY_TYPE_ECC, NULL, 0, 3401 MIB_TSC_MEM3_ERRf, 3402 MIB_TSC_MEM3_ERRf, 3403 INVALIDm, "TX MIB MEM3", 3404 XPORT_ECC_CONTROLr, MIB_TSC_MEM_ENf, 3405 XPORT_MIB_TSC_MEM3_ECC_STATUSr, NULL, 3406 INVALIDr, NULL }, 3407 { _SOC_PARITY_TYPE_ECC, NULL, 0, 3408 MIB_RSC_MEM0_ERRf, 3409 MIB_RSC_MEM0_ERRf, 3410 INVALIDm, "RX MIB MEM0", 3411 XPORT_ECC_CONTROLr, MIB_RSC_MEM_ENf, 3412 XPORT_MIB_RSC_MEM0_ECC_STATUSr, NULL, 3413 INVALIDr, NULL }, 3414 { _SOC_PARITY_TYPE_ECC, NULL, 0, 3415 MIB_RSC_MEM1_ERRf, 3416 MIB_RSC_MEM1_ERRf, 3417 INVALIDm, "RX MIB MEM1", 3418 XPORT_ECC_CONTROLr, MIB_RSC_MEM_ENf, 3419 XPORT_MIB_RSC_MEM1_ECC_STATUSr, NULL, 3420 INVALIDr, NULL }, 3421 { _SOC_PARITY_TYPE_ECC, NULL, 0, 3422 MIB_RSC_MEM2_ERRf, 3423 MIB_RSC_MEM2_ERRf, 3424 INVALIDm, "RX MIB MEM2", 3425 XPORT_ECC_CONTROLr, MIB_RSC_MEM_ENf, 3426 XPORT_MIB_RSC_MEM2_ECC_STATUSr, NULL, 3427 INVALIDr, NULL }, 3428 { _SOC_PARITY_TYPE_ECC, NULL, 0, 3429 MIB_RSC_MEM3_ERRf, 3430 MIB_RSC_MEM3_ERRf, 3431 INVALIDm, "RX MIB MEM3", 3432 XPORT_ECC_CONTROLr, MIB_RSC_MEM_ENf, 3433 XPORT_MIB_RSC_MEM3_ECC_STATUSr, NULL, 3434 INVALIDr, NULL }, 3435 { _SOC_PARITY_TYPE_ECC, NULL, 0, 3436 MIB_RSC_MEM4_ERRf, 3437 MIB_RSC_MEM4_ERRf, 3438 INVALIDm, "RX MIB MEM4", 3439 XPORT_ECC_CONTROLr, MIB_RSC_MEM_ENf, 3440 XPORT_MIB_RSC_MEM4_ECC_STATUSr, NULL, 3441 INVALIDr, NULL }, 3442 { _SOC_PARITY_TYPE_ECC, NULL, 0, 3443 RXFIFO_MEM_ERRf, 3444 RXFIFO_MEM_ERRf, 3445 INVALIDm, "RX FIFO MEM", 3446 XPORT_ECC_CONTROLr, RXFIFO_MEM_ENf, 3447 XPORT_RXFIFO_MEM_ECC_STATUSr, NULL, 3448 INVALIDr, NULL }, 3449 3450 { _SOC_PARITY_TYPE_NONE } /* table terminator */ 3451 3452 }; 3453 3454 STATIC _soc_saber2_parity_info_t _soc_saber2_xlport_tsc_parity_info[] = { 3455 { _SOC_PARITY_TYPE_ECC, NULL, 0, 3456 INVALIDf, 3457 ECC_ERRf, 3458 INVALIDm, "TX MIB MEM0", 3459 XLPORT_ECC_CONTROLr, MIB_TSC0_MEM_EN_COR_ERR_RPTf, 3460 XLPORT_MIB_TSC_MEM0_ECC_STATUSr, NULL, 3461 INVALIDr, NULL }, 3462 { _SOC_PARITY_TYPE_ECC, NULL, 0, 3463 INVALIDf, 3464 ECC_ERRf, 3465 INVALIDm, "TX MIB MEM1", 3466 XLPORT_ECC_CONTROLr, MIB_TSC1_MEM_EN_COR_ERR_RPTf, 3467 XLPORT_MIB_TSC_MEM1_ECC_STATUSr, NULL, 3468 INVALIDr, NULL }, 3469 3470 { _SOC_PARITY_TYPE_NONE } /* table terminator */ 3471 3472 }; 3473 3474 STATIC _soc_saber2_parity_info_t _soc_saber2_xlport_rsc_parity_info[] = { 3475 3476 { _SOC_PARITY_TYPE_ECC, NULL, 0, 3477 INVALIDf, 3478 ECC_ERRf, 3479 INVALIDm, "RX MIB MEM0", 3480 XLPORT_ECC_CONTROLr, MIB_RSC0_MEM_EN_COR_ERR_RPTf, 3481 XLPORT_MIB_RSC_MEM0_ECC_STATUSr, NULL, 3482 INVALIDr, NULL }, 3483 { _SOC_PARITY_TYPE_ECC, NULL, 0, 3484 INVALIDf, 3485 ECC_ERRf, 3486 INVALIDm, "RX MIB MEM1", 3487 XLPORT_ECC_CONTROLr, MIB_RSC1_MEM_EN_COR_ERR_RPTf, 3488 XLPORT_MIB_RSC_MEM1_ECC_STATUSr, NULL, 3489 INVALIDr, NULL }, 3490 3491 { _SOC_PARITY_TYPE_NONE } /* table terminator */ 3492 3493 }; 3494 3495 STATIC _soc_saber2_parity_info_t _soc_saber2_xlport_parity_info[] = { 3496 3497 { _SOC_PARITY_TYPE_ECC, _soc_saber2_xlport_tsc_parity_info, 0, 3498 TSC_ERRf, 3499 INVALIDf, 3500 INVALIDm, "", 3501 XLPORT_ECC_CONTROLr, INVALIDf, 3502 INVALIDr, NULL, 3503 INVALIDr, NULL }, 3504 3505 { _SOC_PARITY_TYPE_ECC, _soc_saber2_xlport_rsc_parity_info, 0, 3506 MIB_RX_MEM_ERRf, 3507 INVALIDf, 3508 INVALIDm, "", 3509 XLPORT_ECC_CONTROLr, INVALIDf, 3510 INVALIDr, NULL, 3511 INVALIDr, NULL }, 3512 3513 { _SOC_PARITY_TYPE_NONE } /* table terminator */ 3514 3515 }; 3516 3517 /* For detect IP/EP's memories don't support SER_FIFO */ 3518 STATIC _soc_saber2_parity_info_t _soc_saber2_ep_parity_info[] = { 3519 3520 /* flex counter */ 3521 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3522 EGR_FLEX_CTR_COUNTER_TABLE_0_INTR_STATUSf, 3523 EGR_FLEX_CTR_COUNTER_TABLE_0_INTR_STATUSf, 3524 EGR_FLEX_CTR_COUNTER_TABLE_0m, "", 3525 EGR_FLEX_CTR_COUNTER_TABLE_CONTROL_0r, PARITY_ENf, 3526 EGR_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_INTR_0r, NULL, 3527 EGR_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_NACK_0r, NULL }, 3528 3529 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3530 EGR_FLEX_CTR_COUNTER_TABLE_1_INTR_STATUSf, 3531 EGR_FLEX_CTR_COUNTER_TABLE_1_INTR_STATUSf, 3532 EGR_FLEX_CTR_COUNTER_TABLE_1m, "", 3533 EGR_FLEX_CTR_COUNTER_TABLE_CONTROL_1r, PARITY_ENf, 3534 EGR_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_INTR_1r, NULL, 3535 EGR_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_NACK_1r, NULL }, 3536 3537 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3538 EGR_FLEX_CTR_COUNTER_TABLE_2_INTR_STATUSf, 3539 EGR_FLEX_CTR_COUNTER_TABLE_2_INTR_STATUSf, 3540 EGR_FLEX_CTR_COUNTER_TABLE_2m, "", 3541 EGR_FLEX_CTR_COUNTER_TABLE_CONTROL_2r, PARITY_ENf, 3542 EGR_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_INTR_2r, NULL, 3543 EGR_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_NACK_2r, NULL }, 3544 3545 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3546 EGR_FLEX_CTR_COUNTER_TABLE_3_INTR_STATUSf, 3547 EGR_FLEX_CTR_COUNTER_TABLE_3_INTR_STATUSf, 3548 EGR_FLEX_CTR_COUNTER_TABLE_3m, "", 3549 EGR_FLEX_CTR_COUNTER_TABLE_CONTROL_3r, PARITY_ENf, 3550 EGR_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_INTR_3r, NULL, 3551 EGR_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_NACK_3r, NULL }, 3552 3553 /* These memories(flex ctr 4~7) have been removed in 56270 */ 3554 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3555 EGR_FLEX_CTR_COUNTER_TABLE_4_INTR_STATUSf, 3556 EGR_FLEX_CTR_COUNTER_TABLE_4_INTR_STATUSf, 3557 EGR_FLEX_CTR_COUNTER_TABLE_4m, "", 3558 EGR_FLEX_CTR_COUNTER_TABLE_CONTROL_4r, PARITY_ENf, 3559 EGR_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_INTR_4r, NULL, 3560 EGR_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_NACK_4r, NULL }, 3561 3562 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3563 EGR_FLEX_CTR_COUNTER_TABLE_5_INTR_STATUSf, 3564 EGR_FLEX_CTR_COUNTER_TABLE_5_INTR_STATUSf, 3565 EGR_FLEX_CTR_COUNTER_TABLE_5m, "", 3566 EGR_FLEX_CTR_COUNTER_TABLE_CONTROL_5r, PARITY_ENf, 3567 EGR_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_INTR_5r, NULL, 3568 EGR_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_NACK_5r, NULL }, 3569 3570 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3571 EGR_FLEX_CTR_COUNTER_TABLE_6_INTR_STATUSf, 3572 EGR_FLEX_CTR_COUNTER_TABLE_6_INTR_STATUSf, 3573 EGR_FLEX_CTR_COUNTER_TABLE_6m, "", 3574 EGR_FLEX_CTR_COUNTER_TABLE_CONTROL_6r, PARITY_ENf, 3575 EGR_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_INTR_6r, NULL, 3576 EGR_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_NACK_6r, NULL }, 3577 3578 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3579 EGR_FLEX_CTR_COUNTER_TABLE_7_INTR_STATUSf, 3580 EGR_FLEX_CTR_COUNTER_TABLE_7_INTR_STATUSf, 3581 EGR_FLEX_CTR_COUNTER_TABLE_7m, "", 3582 EGR_FLEX_CTR_COUNTER_TABLE_CONTROL_7r, PARITY_ENf, 3583 EGR_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_INTR_7r, NULL, 3584 EGR_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_NACK_7r, NULL }, 3585 3586 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3587 EGR_FLEX_CTR_OFFSET_TABLE_0_INTR_STATUSf, 3588 EGR_FLEX_CTR_OFFSET_TABLE_0_INTR_STATUSf, 3589 EGR_FLEX_CTR_OFFSET_TABLE_0m, "", 3590 EGR_FLEX_CTR_OFFSET_TABLE_CONTROL_0r, PARITY_ENf, 3591 EGR_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_INTR_0r, NULL, 3592 EGR_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_NACK_0r, NULL }, 3593 3594 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3595 EGR_FLEX_CTR_OFFSET_TABLE_1_INTR_STATUSf, 3596 EGR_FLEX_CTR_OFFSET_TABLE_1_INTR_STATUSf, 3597 EGR_FLEX_CTR_OFFSET_TABLE_1m, "", 3598 EGR_FLEX_CTR_OFFSET_TABLE_CONTROL_1r, PARITY_ENf, 3599 EGR_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_INTR_1r, NULL, 3600 EGR_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_NACK_1r, NULL }, 3601 3602 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3603 EGR_FLEX_CTR_OFFSET_TABLE_2_INTR_STATUSf, 3604 EGR_FLEX_CTR_OFFSET_TABLE_2_INTR_STATUSf, 3605 EGR_FLEX_CTR_OFFSET_TABLE_2m, "", 3606 EGR_FLEX_CTR_OFFSET_TABLE_CONTROL_2r, PARITY_ENf, 3607 EGR_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_INTR_2r, NULL, 3608 EGR_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_NACK_2r, NULL }, 3609 3610 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3611 EGR_FLEX_CTR_OFFSET_TABLE_3_INTR_STATUSf, 3612 EGR_FLEX_CTR_OFFSET_TABLE_3_INTR_STATUSf, 3613 EGR_FLEX_CTR_OFFSET_TABLE_3m, "", 3614 EGR_FLEX_CTR_OFFSET_TABLE_CONTROL_3r, PARITY_ENf, 3615 EGR_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_INTR_3r, NULL, 3616 EGR_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_NACK_3r, NULL }, 3617 3618 /* These memories(flex ctr 4~7) have been removed in 56270 */ 3619 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3620 EGR_FLEX_CTR_OFFSET_TABLE_4_INTR_STATUSf, 3621 EGR_FLEX_CTR_OFFSET_TABLE_4_INTR_STATUSf, 3622 EGR_FLEX_CTR_OFFSET_TABLE_4m, "", 3623 EGR_FLEX_CTR_OFFSET_TABLE_CONTROL_4r, PARITY_ENf, 3624 EGR_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_INTR_4r, NULL, 3625 EGR_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_NACK_4r, NULL }, 3626 3627 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3628 EGR_FLEX_CTR_OFFSET_TABLE_5_INTR_STATUSf, 3629 EGR_FLEX_CTR_OFFSET_TABLE_5_INTR_STATUSf, 3630 EGR_FLEX_CTR_OFFSET_TABLE_5m, "", 3631 EGR_FLEX_CTR_OFFSET_TABLE_CONTROL_5r, PARITY_ENf, 3632 EGR_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_INTR_5r, NULL, 3633 EGR_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_NACK_5r, NULL }, 3634 3635 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3636 EGR_FLEX_CTR_OFFSET_TABLE_6_INTR_STATUSf, 3637 EGR_FLEX_CTR_OFFSET_TABLE_6_INTR_STATUSf, 3638 EGR_FLEX_CTR_OFFSET_TABLE_6m, "", 3639 EGR_FLEX_CTR_OFFSET_TABLE_CONTROL_6r, PARITY_ENf, 3640 EGR_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_INTR_6r, NULL, 3641 EGR_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_NACK_6r, NULL }, 3642 3643 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3644 EGR_FLEX_CTR_OFFSET_TABLE_7_INTR_STATUSf, 3645 EGR_FLEX_CTR_OFFSET_TABLE_7_INTR_STATUSf, 3646 EGR_FLEX_CTR_OFFSET_TABLE_7m, "", 3647 EGR_FLEX_CTR_OFFSET_TABLE_CONTROL_7r, PARITY_ENf, 3648 EGR_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_INTR_7r, NULL, 3649 EGR_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_NACK_7r, NULL }, 3650 3651 3652 { _SOC_PARITY_TYPE_NONE } /* table terminator */ 3653 3654 }; 3655 3656 3657 3658 /* For detect IP/EP's memories don't support SER_FIFO */ 3659 STATIC _soc_saber2_parity_info_t _soc_saber2_ip_parity_info[] = { 3660 3661 /* flex counter */ 3662 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3663 ING_FLEX_CTR_POOL_0_COUNTER_TABLE_INTR_STATUSf, 3664 ING_FLEX_CTR_POOL_0_COUNTER_TABLE_INTR_STATUSf, 3665 ING_FLEX_CTR_COUNTER_TABLE_0m, "", 3666 ING_FLEX_CTR_COUNTER_TABLE_CONTROL_0r, PARITY_ENf, 3667 ING_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_INTR_0r, NULL, 3668 ING_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_NACK_0r, NULL }, 3669 3670 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3671 ING_FLEX_CTR_POOL_1_COUNTER_TABLE_INTR_STATUSf, 3672 ING_FLEX_CTR_POOL_1_COUNTER_TABLE_INTR_STATUSf, 3673 ING_FLEX_CTR_COUNTER_TABLE_1m, "", 3674 ING_FLEX_CTR_COUNTER_TABLE_CONTROL_1r, PARITY_ENf, 3675 ING_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_INTR_1r, NULL, 3676 ING_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_NACK_1r, NULL }, 3677 3678 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3679 ING_FLEX_CTR_POOL_2_COUNTER_TABLE_INTR_STATUSf, 3680 ING_FLEX_CTR_POOL_2_COUNTER_TABLE_INTR_STATUSf, 3681 ING_FLEX_CTR_COUNTER_TABLE_2m, "", 3682 ING_FLEX_CTR_COUNTER_TABLE_CONTROL_2r, PARITY_ENf, 3683 ING_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_INTR_2r, NULL, 3684 ING_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_NACK_2r, NULL }, 3685 3686 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3687 ING_FLEX_CTR_POOL_3_COUNTER_TABLE_INTR_STATUSf, 3688 ING_FLEX_CTR_POOL_3_COUNTER_TABLE_INTR_STATUSf, 3689 ING_FLEX_CTR_COUNTER_TABLE_3m, "", 3690 ING_FLEX_CTR_COUNTER_TABLE_CONTROL_3r, PARITY_ENf, 3691 ING_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_INTR_3r, NULL, 3692 ING_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_NACK_3r, NULL }, 3693 3694 /* These memories(flex ctr 4~7) have been removed in 56270 */ 3695 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3696 ING_FLEX_CTR_POOL_4_COUNTER_TABLE_INTR_STATUSf, 3697 ING_FLEX_CTR_POOL_4_COUNTER_TABLE_INTR_STATUSf, 3698 ING_FLEX_CTR_COUNTER_TABLE_4m, "", 3699 ING_FLEX_CTR_COUNTER_TABLE_CONTROL_4r, PARITY_ENf, 3700 ING_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_INTR_4r, NULL, 3701 ING_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_NACK_4r, NULL }, 3702 3703 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3704 ING_FLEX_CTR_POOL_5_COUNTER_TABLE_INTR_STATUSf, 3705 ING_FLEX_CTR_POOL_5_COUNTER_TABLE_INTR_STATUSf, 3706 ING_FLEX_CTR_COUNTER_TABLE_5m, "", 3707 ING_FLEX_CTR_COUNTER_TABLE_CONTROL_5r, PARITY_ENf, 3708 ING_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_INTR_5r, NULL, 3709 ING_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_NACK_5r, NULL }, 3710 3711 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3712 ING_FLEX_CTR_POOL_6_COUNTER_TABLE_INTR_STATUSf, 3713 ING_FLEX_CTR_POOL_6_COUNTER_TABLE_INTR_STATUSf, 3714 ING_FLEX_CTR_COUNTER_TABLE_6m, "", 3715 ING_FLEX_CTR_COUNTER_TABLE_CONTROL_6r, PARITY_ENf, 3716 ING_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_INTR_6r, NULL, 3717 ING_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_NACK_6r, NULL }, 3718 3719 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3720 ING_FLEX_CTR_POOL_7_COUNTER_TABLE_INTR_STATUSf, 3721 ING_FLEX_CTR_POOL_7_COUNTER_TABLE_INTR_STATUSf, 3722 ING_FLEX_CTR_COUNTER_TABLE_7m, "", 3723 ING_FLEX_CTR_COUNTER_TABLE_CONTROL_7r, PARITY_ENf, 3724 ING_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_INTR_7r, NULL, 3725 ING_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_NACK_7r, NULL }, 3726 3727 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3728 ING_FLEX_CTR_POOL_0_OFFSET_TABLE_INTR_STATUSf, 3729 ING_FLEX_CTR_POOL_0_OFFSET_TABLE_INTR_STATUSf, 3730 ING_FLEX_CTR_OFFSET_TABLE_0m, "", 3731 ING_FLEX_CTR_OFFSET_TABLE_CONTROL_0r, PARITY_ENf, 3732 ING_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_INTR_0r, NULL, 3733 ING_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_NACK_0r, NULL }, 3734 3735 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3736 ING_FLEX_CTR_POOL_1_OFFSET_TABLE_INTR_STATUSf, 3737 ING_FLEX_CTR_POOL_1_OFFSET_TABLE_INTR_STATUSf, 3738 ING_FLEX_CTR_OFFSET_TABLE_1m, "", 3739 ING_FLEX_CTR_OFFSET_TABLE_CONTROL_1r, PARITY_ENf, 3740 ING_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_INTR_1r, NULL, 3741 ING_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_NACK_1r, NULL }, 3742 3743 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3744 ING_FLEX_CTR_POOL_2_OFFSET_TABLE_INTR_STATUSf, 3745 ING_FLEX_CTR_POOL_2_OFFSET_TABLE_INTR_STATUSf, 3746 ING_FLEX_CTR_OFFSET_TABLE_2m, "", 3747 ING_FLEX_CTR_OFFSET_TABLE_CONTROL_2r, PARITY_ENf, 3748 ING_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_INTR_2r, NULL, 3749 ING_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_NACK_2r, NULL }, 3750 3751 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3752 ING_FLEX_CTR_POOL_3_OFFSET_TABLE_INTR_STATUSf, 3753 ING_FLEX_CTR_POOL_3_OFFSET_TABLE_INTR_STATUSf, 3754 ING_FLEX_CTR_OFFSET_TABLE_3m, "", 3755 ING_FLEX_CTR_OFFSET_TABLE_CONTROL_3r, PARITY_ENf, 3756 ING_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_INTR_3r, NULL, 3757 ING_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_NACK_3r, NULL }, 3758 3759 /* These memories(flex ctr 4~7) have been removed in 56270 */ 3760 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3761 ING_FLEX_CTR_POOL_4_OFFSET_TABLE_INTR_STATUSf, 3762 ING_FLEX_CTR_POOL_4_OFFSET_TABLE_INTR_STATUSf, 3763 ING_FLEX_CTR_OFFSET_TABLE_4m, "", 3764 ING_FLEX_CTR_OFFSET_TABLE_CONTROL_4r, PARITY_ENf, 3765 ING_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_INTR_4r, NULL, 3766 ING_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_NACK_4r, NULL }, 3767 3768 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3769 ING_FLEX_CTR_POOL_5_OFFSET_TABLE_INTR_STATUSf, 3770 ING_FLEX_CTR_POOL_5_OFFSET_TABLE_INTR_STATUSf, 3771 ING_FLEX_CTR_OFFSET_TABLE_5m, "", 3772 ING_FLEX_CTR_OFFSET_TABLE_CONTROL_5r, PARITY_ENf, 3773 ING_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_INTR_5r, NULL, 3774 ING_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_NACK_5r, NULL }, 3775 3776 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3777 ING_FLEX_CTR_POOL_6_OFFSET_TABLE_INTR_STATUSf, 3778 ING_FLEX_CTR_POOL_6_OFFSET_TABLE_INTR_STATUSf, 3779 ING_FLEX_CTR_OFFSET_TABLE_6m, "", 3780 ING_FLEX_CTR_OFFSET_TABLE_CONTROL_6r, PARITY_ENf, 3781 ING_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_INTR_6r, NULL, 3782 ING_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_NACK_6r, NULL }, 3783 3784 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3785 ING_FLEX_CTR_POOL_7_OFFSET_TABLE_INTR_STATUSf, 3786 ING_FLEX_CTR_POOL_7_OFFSET_TABLE_INTR_STATUSf, 3787 ING_FLEX_CTR_OFFSET_TABLE_7m, "", 3788 ING_FLEX_CTR_OFFSET_TABLE_CONTROL_7r, PARITY_ENf, 3789 ING_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_INTR_7r, NULL, 3790 ING_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_NACK_7r, NULL }, 3791 3792 /*SVM tables */ 3793 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3794 INVALIDf, 3795 INVALIDf, 3796 SVM_METER_TABLEm, "", 3797 ING_SVM_METER_TABLE_CONTROLr, PARITY_ENf, 3798 ING_SVM_METER_TABLE_PARITY_STATUS_INTRr, NULL, 3799 ING_SVM_METER_TABLE_PARITY_STATUS_NACKr, NULL }, 3800 3801 3802 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3803 INVALIDf, 3804 INVALIDf, 3805 SVM_MACROFLOW_INDEX_TABLEm, "", 3806 ING_SVM_MACROFLOW_INDEX_TABLE_CONTROLr, PARITY_ENf, 3807 ING_SVM_MACROFLOW_INDEX_TABLE_PARITY_STATUS_INTRr, NULL, 3808 ING_SVM_MACROFLOW_INDEX_TABLE_PARITY_STATUS_NACKr, NULL }, 3809 3810 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3811 INVALIDf, 3812 INVALIDf, 3813 SVM_POLICY_TABLEm, "", 3814 ING_SVM_POLICY_TABLE_CONTROLr, PARITY_ENf, 3815 ING_SVM_POLICY_TABLE_PARITY_STATUS_INTRr, NULL, 3816 ING_SVM_POLICY_TABLE_PARITY_STATUS_NACKr, NULL }, 3817 3818 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3819 INVALIDf, 3820 INVALIDf, 3821 SVM_OFFSET_TABLEm, "", 3822 ING_SVM_OFFSET_TABLE_CONTROLr, PARITY_ENf, 3823 ING_SVM_OFFSET_TABLE_PARITY_STATUS_INTRr, NULL, 3824 ING_SVM_OFFSET_TABLE_PARITY_STATUS_NACKr, NULL }, 3825 3826 { _SOC_PARITY_TYPE_NONE } /* table terminator */ 3827 3828 }; 3829 3830 3831 STATIC _soc_saber2_parity_info_t _soc_saber2_rxlp_parity_info[] = { 3832 { _SOC_PARITY_TYPE_ECC, NULL, 0, 3833 MAIN_BUFF_ECC_INTR_ENABLEf, 3834 MAIN_BUFF_ECC_INTR_STATUSf, 3835 INVALIDm, "main data buffer", 3836 RXLP_ECC_PARITY_CONTROLr, DATABUF_ECC_ENf, 3837 RXLP_DATABUF_ECC_STATUSr, NULL, 3838 INVALIDr, NULL }, 3839 3840 { _SOC_PARITY_TYPE_ECC, NULL, 0, 3841 CTRL_BUFFER_ECC_INTR_ENABLEf, 3842 CTRL_BUFF_ECC_INTR_STATUSf, 3843 INVALIDm, "ctrl data buffer", 3844 RXLP_ECC_PARITY_CONTROLr, CTRLBUF_ECC_ENf, 3845 RXLP_CTRLBUF_ECC_STATUSr, NULL, 3846 INVALIDr, NULL }, 3847 3848 { _SOC_PARITY_TYPE_ECC, NULL, 0, 3849 RESIDUAL_CRC_ECC_INTR_ENABLEf, 3850 RESIDUAL_CRC_ECC_INTR_STATUSf, 3851 INVALIDm, "Residual CRC Buffer ", 3852 RXLP_ECC_PARITY_CONTROLr, RESIDUALCRC_ECC_ENf, 3853 RXLP_RESIDUAL_CRC_ECC_STATUSr, NULL, 3854 INVALIDr, NULL }, 3855 3856 { _SOC_PARITY_TYPE_ECC, NULL, 0, 3857 IARB_BUF_ECC_INTR_ENABLEf, 3858 IARB_BUF_ECC_INTR_STATUSf, 3859 INVALIDm, "IARB Buffer", 3860 RXLP_ECC_PARITY_CONTROLr, IARBBUF_ECC_ENf, 3861 RXLP_IARBBUF_ECC_STATUSr, NULL, 3862 INVALIDr, NULL }, 3863 3864 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3865 TRIGGER_MEM_PARITY_ERR_INTR_ENABLEf, 3866 TRIGGER_MEM_PARITY_ERRf, 3867 INVALIDm, "IARB Buffer", 3868 RXLP_ECC_PARITY_CONTROLr, TRIGGERS_MEM_PARITY_ENf, 3869 RXLP_TRIGGER_MEM_PARITY_STATUSr, NULL, 3870 RXLP_TRIGGER_MEM_PARITY_STATUS_NACKr, NULL }, 3871 3872 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3873 COUNTER_MEM_PARITY_ERR_INTR_ENABLEf, 3874 COUNTER_MEM_PARITY_ERRf, 3875 INVALIDm, "IARB Buffer", 3876 RXLP_ECC_PARITY_CONTROLr, COUNTERS_MEM_PARITY_ENf, 3877 RXLP_COUNTER_MEM_PARITY_STATUSr, NULL, 3878 RXLP_COUNTER_MEM_PARITY_STATUS_NACKr, NULL }, 3879 3880 { _SOC_PARITY_TYPE_NONE } /* table terminator */ 3881 3882 }; 3883 3884 STATIC _soc_saber2_parity_info_t _soc_saber2_txlp_parity_info[] = { 3885 3886 { _SOC_PARITY_TYPE_ECC, NULL, 0, 3887 INT2EXT_PARITY_ERRf, 3888 INT2EXT_PARITY_ERRf, 3889 INVALIDm, "INT2EXT-MAP-TABLE", 3890 TXLP_ECC_PARITY_CONTROLr, INT2EXT_STREAM_MAP_PARITY_ENf, 3891 TXLP_DATABUF_ECC_STATUSr, NULL, 3892 INVALIDr, NULL }, 3893 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3894 RESICRCBUF_PARITY_ERRf, 3895 RESICRCBUF_PARITY_ERRf, 3896 INVALIDm, "RESIDUAL-CRC-BUFFER", 3897 TXLP_ECC_PARITY_CONTROLr, RESICRCBUF_PARITY_ENf, 3898 TXLP_RESICRCBUF_PARITY_STATUSr, NULL, 3899 INVALIDr, NULL }, 3900 { _SOC_PARITY_TYPE_ECC, NULL, 0, 3901 RESIDATABUF_ECC_ERRf, 3902 RESIDATABUF_ECC_ERRf, 3903 INVALIDm, "RESIDUAL-DATA-BUFFER", 3904 TXLP_ECC_PARITY_CONTROLr, RESIDATABUF_ECC_ENf, 3905 TXLP_RESIDATABUF_ECC_STATUSr, NULL, 3906 INVALIDr, NULL }, 3907 { _SOC_PARITY_TYPE_ECC, NULL, 0, 3908 DATABUF_ECC_ERRf, 3909 DATABUF_ECC_ERRf, 3910 INVALIDm, "MAIN-DATA-BUFFER.", 3911 TXLP_ECC_PARITY_CONTROLr, DATABUF_ECC_ENf, 3912 TXLP_DATABUF_ECC_STATUSr, NULL, 3913 INVALIDr, NULL }, 3914 { _SOC_PARITY_TYPE_ECC, NULL, 0, 3915 CSTATEBUF_PARITY_ERRf, 3916 CSTATEBUF_PARITY_ERRf, 3917 INVALIDm, "HANNEL-STATE-BUFFER.", 3918 TXLP_ECC_PARITY_CONTROLr, CSTATEBUF_PARITY_ENf, 3919 TXLP_CTRLBUF_ECC_STATUSr, NULL, 3920 INVALIDr, NULL }, 3921 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3922 TRIGGER_MEM_PARITY_ERRf, 3923 TRIGGER_MEM_PARITY_ERRf, 3924 INVALIDm, "TXLP_DEBUG_COUNTER[0-7]", 3925 TXLP_ECC_PARITY_CONTROLr, TRIGGERS_MEM_PARITY_ENf, 3926 TXLP_TRIGGER_MEM_PARITY_STATUSr, NULL, 3927 TXLP_TRIGGER_MEM_PARITY_STATUS_NACKr, NULL }, 3928 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3929 COUNTER_MEM_PARITY_ERRf, 3930 COUNTER_MEM_PARITY_ERRf, 3931 INVALIDm, "TXLP_DEBUG_COUNTER[8-11]", 3932 TXLP_ECC_PARITY_CONTROLr, COUNTERS_MEM_PARITY_ENf, 3933 TXLP_COUNTER_MEM_PARITY_STATUSr, NULL, 3934 TXLP_COUNTER_MEM_PARITY_STATUS_NACKr, NULL }, 3935 3936 { _SOC_PARITY_TYPE_NONE } /* table terminator */ 3937 3938 }; 3939 3940 3941 3942 STATIC const 3943 _soc_saber2_parity_route_block_t _soc_saber2_parity_intr_route_blocks[] = { 3944 3945 /* CMIC_CMC0_IRQ_STAT3. refer to CMIC_INTR_STATUS Format */ 3946 3947 3948 /* IP1_TO_CMIC_L2MF_INTR bit0 */ 3949 3950 /* IP1_TO_CMIC_L2_OVERFLOW_INTR bit1 */ 3951 3952 /* IP1_TO_CMIC_OAMP2ECI_C_INTR bit2 3953 Indicates ECC Error detected or SAT event pending or RX SAT done 3954 */ 3955 3956 /* unused interrupt bit3~7 */ 3957 3958 3959 /* MMU_TO_CMIC_MEMFAIL_INTR bit 8*/ 3960 { 0x00000100, SOC_BLK_MMU, 3961 MMU_INTR_MASKr, MMU_INTRr,INVALIDf, NULL, 0}, 3962 3963 /* EP1_TO_CMIC_PERR_INTR bit 9 */ 3964 { 0x00000200, SOC_BLK_EPIPE, 3965 EGR_INTR1_ENABLEr, EGR_INTR1_STATUSr, SER_FIFO_NON_EMPTYf, _soc_saber2_ep_parity_info, 0}, 3966 3967 /* EP2_TO_CMIC_PERR_INTR bit 10*/ 3968 { 0x00000400, SOC_BLK_EPIPE, 3969 EGR_INTR1_ENABLEr, EGR_INTR1_STATUSr, SER_FIFO_NON_EMPTYf, NULL, 0}, 3970 3971 /* IP0_TO_CMIC_PERR_INTR bit 11 */ 3972 { 0x00000800, SOC_BLK_IPIPE, 3973 IP3_INTR_ENABLEr, IP3_INTR_STATUSr, ING_SER_FIFO_INTR_STATUSf, NULL, 0}, 3974 3975 /* IP1_TO_CMIC_PERR_INTR bit 12 */ 3976 { 0x00001000, SOC_BLK_IPIPE, 3977 IP3_INTR_ENABLEr, IP3_INTR_STATUSr, ING_SER_FIFO_INTR_STATUSf, NULL, 0}, 3978 3979 /* IP2_TO_CMIC_PERR_INTR bit 13*/ 3980 { 0x00002000, SOC_BLK_IPIPE, 3981 IP3_INTR_ENABLEr, IP3_INTR_STATUSr, ING_SER_FIFO_INTR_STATUSf, NULL, 0}, 3982 3983 /* MXQ0_TO_CMIC_PERR_INTR bit 14*/ 3984 { 0x00004000, SOC_BLK_MXQPORT, 3985 XPORT_INTR_ENABLEr, XPORT_INTR_STATUSr, INVALIDf, _soc_saber2_xport_parity_info, 0}, 3986 3987 /* MXQ1_TO_CMIC_PERR_INTR bit 15*/ 3988 { 0x00008000, SOC_BLK_MXQPORT, 3989 XPORT_INTR_ENABLEr, XPORT_INTR_STATUSr, INVALIDf, _soc_saber2_xport_parity_info, 1}, 3990 3991 /* MXQ2_TO_CMIC_PERR_INTR bit 16*/ 3992 { 0x00010000, SOC_BLK_MXQPORT, 3993 XPORT_INTR_ENABLEr, XPORT_INTR_STATUSr, INVALIDf, _soc_saber2_xport_parity_info, 2}, 3994 3995 /* MXQ3_TO_CMIC_PERR_INTR bit 17*/ 3996 { 0x00020000, SOC_BLK_MXQPORT, 3997 XPORT_INTR_ENABLEr, XPORT_INTR_STATUSr, INVALIDf, _soc_saber2_xport_parity_info, 3}, 3998 3999 /* MXQ4_TO_CMIC_PERR_INTR bit 18*/ 4000 { 0x00040000, SOC_BLK_MXQPORT, 4001 XPORT_INTR_ENABLEr, XPORT_INTR_STATUSr, INVALIDf, _soc_saber2_xport_parity_info, 4}, 4002 4003 /* MXQ5_TO_CMIC_PERR_INTR bit 19*/ 4004 { 0x00080000, SOC_BLK_MXQPORT, 4005 XPORT_INTR_ENABLEr, XPORT_INTR_STATUSr, INVALIDf, _soc_saber2_xport_parity_info, 5}, 4006 4007 /* PM_TO_CMIC_PERR_INTR bit20 xlport */ 4008 { 0x00100000, SOC_BLK_XLPORT, 4009 XLPORT_INTR_ENABLEr, INVALIDr, INVALIDf, _soc_saber2_xlport_parity_info, 0}, 4010 4011 /* RXLP0_TO_CMIC_PERR_INTR bit 21 */ 4012 { 0x00200000, SOC_BLK_RXLP, 4013 RXLP_ECC_INTERRUPT_ENABLEr, RXLP_ECC_INTERRUPT_STATUSr, INVALIDf, _soc_saber2_rxlp_parity_info, 0}, 4014 4015 /* TXLP0_TO_CMIC_PERR_INTR bit 22 */ 4016 { 0x00400000, SOC_BLK_TXLP, 4017 TXLP_INTR_ENABLEr, TXLP_INTR_STATUSr, INVALIDf, _soc_saber2_txlp_parity_info, 0}, 4018 4019 /* IP3_TO_CMIC_PERR_INTR bit 23 */ 4020 { 0x00800000, SOC_BLK_IPIPE, 4021 IP3_INTR_ENABLEr, IP3_INTR_STATUSr, ING_SER_FIFO_INTR_STATUSf, _soc_saber2_ip_parity_info, 0}, 4022 4023 /* other interrupt bits */ 4024 4025 { 0 } /* table terminator */ 4026 4027 }; 4028 4029 #ifdef BCM_METROLITE_SUPPORT 4030 STATIC const 4031 _soc_saber2_parity_route_block_t _soc_metrolite_parity_intr_route_blocks[] = { 4032 4033 /* CMIC_CMC0_IRQ_STAT3. refer to CMIC_INTR_STATUS Format */ 4034 4035 4036 /* IP1_TO_CMIC_L2MF_INTR bit0 */ 4037 4038 /* IP1_TO_CMIC_L2_OVERFLOW_INTR bit1 */ 4039 4040 /* IP1_TO_CMIC_OAMP2ECI_C_INTR bit2 4041 Indicates ECC Error detected or SAT event pending or RX SAT done 4042 */ 4043 4044 /* PULL_DOWN0 bit3~7 */ 4045 4046 4047 /* MMU_TO_CMIC_MEMFAIL_INTR bit 8*/ 4048 { 0x00000100, SOC_BLK_MMU, 4049 MMU_INTR_MASKr, MMU_INTRr,INVALIDf, NULL, 0}, 4050 4051 /* EP1_TO_CMIC_PERR_INTR bit 9 */ 4052 { 0x00000200, SOC_BLK_EPIPE, 4053 EGR_INTR1_ENABLEr, EGR_INTR1_STATUSr, SER_FIFO_NON_EMPTYf, _soc_saber2_ep_parity_info, 0}, 4054 4055 /* EP2_TO_CMIC_PERR_INTR bit 10*/ 4056 { 0x00000400, SOC_BLK_EPIPE, 4057 EGR_INTR1_ENABLEr, EGR_INTR1_STATUSr, SER_FIFO_NON_EMPTYf, NULL, 0}, 4058 4059 /* IP0_TO_CMIC_PERR_INTR bit 11 */ 4060 { 0x00000800, SOC_BLK_IPIPE, 4061 IP3_INTR_ENABLEr, IP3_INTR_STATUSr, ING_SER_FIFO_INTR_STATUSf, NULL, 0}, 4062 4063 /* IP1_TO_CMIC_PERR_INTR bit 12 */ 4064 { 0x00001000, SOC_BLK_IPIPE, 4065 IP3_INTR_ENABLEr, IP3_INTR_STATUSr, ING_SER_FIFO_INTR_STATUSf, NULL, 0}, 4066 4067 /* IP2_TO_CMIC_PERR_INTR bit 13*/ 4068 { 0x00002000, SOC_BLK_IPIPE, 4069 IP3_INTR_ENABLEr, IP3_INTR_STATUSr, ING_SER_FIFO_INTR_STATUSf, NULL, 0}, 4070 4071 /* MXQ_TO_CMIC_PERR_INTR bit 14*/ 4072 { 0x00004000, SOC_BLK_MXQPORT, 4073 XPORT_INTR_ENABLEr, XPORT_INTR_STATUSr, INVALIDf, _soc_saber2_xport_parity_info, 0}, 4074 4075 /* PM0_TO_CMIC_PERR_INTR bit 15*/ 4076 { 0x00008000, SOC_BLK_MXQPORT, 4077 XLPORT_INTR_ENABLEr, INVALIDr, INVALIDf, _soc_saber2_xlport_parity_info, 0}, 4078 4079 /* PM1_TO_CMIC_PERR_INTR bit 16*/ 4080 { 0x00010000, SOC_BLK_MXQPORT, 4081 XLPORT_INTR_ENABLEr, INVALIDr, INVALIDf, _soc_saber2_xlport_parity_info, 1}, 4082 4083 /* RXLP0_TO_CMIC_PERR_INTR bit 17*/ 4084 { 0x00020000, SOC_BLK_RXLP, 4085 RXLP_ECC_INTERRUPT_ENABLEr, RXLP_ECC_INTERRUPT_STATUSr, INVALIDf, _soc_saber2_rxlp_parity_info, 0}, 4086 4087 /* TXLP0_TO_CMIC_PERR_INTR bit 18*/ 4088 { 0x00040000, SOC_BLK_TXLP, 4089 TXLP_INTR_ENABLEr, TXLP_INTR_STATUSr, INVALIDf, _soc_saber2_txlp_parity_info, 0}, 4090 4091 /* IP3_TO_CMIC_PERR_INTR bit 19*/ 4092 { 0x00080000, SOC_BLK_IPIPE, 4093 IP3_INTR_ENABLEr, IP3_INTR_STATUSr, ING_SER_FIFO_INTR_STATUSf, _soc_saber2_ip_parity_info, 0}, 4094 4095 /* other interrupt bits */ 4096 4097 { 0 } /* table terminator */ 4098 4099 }; 4100 #endif 4101 4102 STATIC const 4103 _soc_saber2_skip_mem_reg_t _soc_saber2_skip_memreg_table[] = { 4104 /* SER_SPECIAL type. For TR 144, it will failed in comparing entry after correction */ 4105 { _SOC_SABER2_SER_MEM, INVALIDr, VLAN_OR_VFI_MAC_COUNTm}, 4106 /* OAM ser correction */ 4107 { _SOC_SABER2_SER_MEM, INVALIDr, RMEPm}, 4108 4109 { _SOC_SABER2_SER_INVALID } /* table terminator */ 4110 4111 }; 4112 4113 STATIC 4114 uint32 _soc_saber2_mem_reg_skip(uint32 regmem, soc_mem_t mem_id, soc_reg_t reg_id) 4115 { 4116 int index; 4117 uint32 rv = 0; 4118 4119 for(index = 0; _soc_saber2_skip_memreg_table[index].regmem != _SOC_SABER2_SER_INVALID ; index ++) { 4120 if (((regmem == _SOC_SABER2_SER_MEM) && 4121 (mem_id == _soc_saber2_skip_memreg_table[index].skip_mem)) || 4122 ((regmem == _SOC_SABER2_SER_REG) && 4123 (mem_id == _soc_saber2_skip_memreg_table[index].skip_reg))) { 4124 rv = 1; 4125 break; 4126 } 4127 } 4128 4129 return rv; 4130 } 4131 4132 STATIC int soc_saber2_ser_engine_init(int unit); 4133 4134 STATIC 4135 soc_error_t soc_saber2_found_mem_in_mmu(int unit, soc_mem_t mem, 4136 _soc_saber2_mmu_sub_block_leaf_info_t * mmu_leaf_info); 4137 4138 STATIC 4139 soc_field_t soc_saber2_set_test_field(soc_mem_t memory, soc_field_t field); 4140 4141 4142 int 4143 soc_saber2_l3_defip_index_remap(int unit, soc_mem_t mem, int index) 4144 { 4145 int wide = 0; 4146 4147 if (SOC_CONTROL(unit)->l3_defip_index_remap == 0) { 4148 return index; 4149 } 4150 4151 if (mem == L3_DEFIP_PAIR_128m || 4152 mem == L3_DEFIP_PAIR_128_ONLYm || 4153 mem == L3_DEFIP_PAIR_128_DATA_ONLYm || 4154 mem == L3_DEFIP_PAIR_128_HIT_ONLYm) { 4155 wide = 1; 4156 } 4157 4158 return soc_l3_defip_index_remap(unit, wide, index); 4159 } 4160 4161 int 4162 soc_saber2_mem_index_remap(int unit, soc_mem_t mem, int index) 4163 { 4164 switch (mem) { 4165 case L3_DEFIPm: 4166 case L3_DEFIP_PAIR_128m: 4167 case L3_DEFIP_ONLYm: 4168 case L3_DEFIP_PAIR_128_ONLYm: 4169 case L3_DEFIP_DATA_ONLYm: 4170 case L3_DEFIP_PAIR_128_DATA_ONLYm: 4171 return soc_saber2_l3_defip_index_remap(unit, mem, index); 4172 default: 4173 return index; 4174 } 4175 } 4176 4177 STATIC 4178 int soc_saber2_ci_block_get(int unit, 4179 _soc_saber2_mmu_subblock_type_t sub_block, 4180 soc_block_t* block) 4181 { 4182 switch(sub_block) { 4183 case _SOC_SABER2_MMU_SUBBLOCK_CI1: 4184 *block = CI1_BLOCK(unit); 4185 break; 4186 4187 case _SOC_SABER2_MMU_SUBBLOCK_CI0: 4188 *block = CI0_BLOCK(unit); 4189 break; 4190 4191 default: 4192 break; 4193 } 4194 return SOC_E_NONE; 4195 } 4196 4197 STATIC 4198 int soc_saber2_process_sb_mmu_leaf_parity_enable(int unit, 4199 soc_port_t port, 4200 soc_reg_t leaf_enable_reg, 4201 _soc_saber2_mmu_sub_block_leaf_info_t * leaf_info, 4202 int enable) 4203 { 4204 uint32 en_rval; 4205 int index; 4206 soc_field_t enable_field; 4207 _soc_saber2_mmu_sub_block_leaf_info_t * info; 4208 soc_reg_t mem_parity_en_reg = INVALIDr; 4209 soc_field_t mem_parity_en_fld = INVALIDf; 4210 uint64 rval64; 4211 uint32 rval; 4212 int set_enable = 0; 4213 4214 /* leaf_info contains a list of leaf block, each leaf has a bit in leaf_enable_reg */ 4215 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, leaf_enable_reg, port, 0, 4216 &en_rval)); 4217 4218 for (index = 0; ; index++) { 4219 info = &leaf_info[index]; 4220 if(info->intr_bit == 0) { 4221 /* End of leaf table */ 4222 break; 4223 } 4224 enable_field = info->enable_field; 4225 mem_parity_en_reg = info->mem_parity_enable_reg; 4226 mem_parity_en_fld = info->mem_parity_enable_field; 4227 4228 set_enable = enable; 4229 if (SOC_REG_FIELD_VALID(unit, leaf_enable_reg, enable_field)) { 4230 if (enable_field == FLUSH_COMPLETE_DISINTf) { 4231 continue; 4232 } 4233 /* Don't enble if parity routing info in incomplete */ 4234 if (INVALIDm == info->mem) { 4235 set_enable = 0; 4236 } 4237 /* set corresponding field for a leaf block */ 4238 soc_reg_field_set(unit, leaf_enable_reg, &en_rval, enable_field, 4239 set_enable ? 0 : 1); 4240 if (leaf_enable_reg == CHFC_TC2PRI_TBL_ECC_CONFIGr) { 4241 soc_reg_field_set(unit, mem_parity_en_reg, &en_rval, mem_parity_en_fld, 4242 set_enable ? 1 : 0); 4243 } 4244 } 4245 4246 if (SOC_REG_FIELD_VALID(unit, mem_parity_en_reg, mem_parity_en_fld)) { 4247 if (SOC_REG_IS_64(unit, mem_parity_en_reg)) { 4248 SOC_IF_ERROR_RETURN 4249 (soc_reg_get(unit, mem_parity_en_reg, port, 0, &rval64)); 4250 soc_reg64_field32_set(unit, mem_parity_en_reg, &rval64, mem_parity_en_fld, 4251 set_enable ? 1 : 0); 4252 SOC_IF_ERROR_RETURN 4253 (soc_reg_set(unit, mem_parity_en_reg, port, 0, rval64)); 4254 } else { 4255 SOC_IF_ERROR_RETURN 4256 (soc_reg32_get(unit, mem_parity_en_reg, port, 0, &rval)); 4257 soc_reg_field_set(unit, mem_parity_en_reg, &rval, mem_parity_en_fld, 4258 set_enable ? 1 : 0); 4259 SOC_IF_ERROR_RETURN 4260 (soc_reg32_set(unit, mem_parity_en_reg, port, 0, rval)); 4261 } 4262 } 4263 } 4264 4265 /* write back enable register */ 4266 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, leaf_enable_reg, port, 0, en_rval)); 4267 return SOC_E_NONE; 4268 } 4269 4270 4271 4272 STATIC 4273 int soc_saber2_process_sb_one_level_mmu_parity_enable(int unit, 4274 soc_reg_t mmu_en_reg, 4275 _soc_saber2_mmu_sub_block_one_level_t * sub_block_info, 4276 int enable) 4277 { 4278 uint32 en_rval; 4279 soc_block_t block = SOC_BLOCK_ANY; 4280 soc_port_t port = REG_PORT_ANY; 4281 soc_reg_t leaf_enable_reg; 4282 _soc_saber2_mmu_subblock_type_t sub_block_type; 4283 _soc_saber2_mmu_sub_block_leaf_info_t * leaf_info; 4284 4285 if(sub_block_info->mmu_bit == 0) { 4286 /* reach the end of one level sub block table */ 4287 return SOC_E_NONE; 4288 } 4289 4290 /* some fields in MMU_INTR_MASK have been removed in 56270 */ 4291 if (!soc_reg_field_valid(unit, mmu_en_reg, sub_block_info->mmu_intr_mask_field)) { 4292 return SOC_E_NONE; 4293 } 4294 4295 sub_block_type = sub_block_info->mmu_sub_block; 4296 if ((sub_block_type == _SOC_SABER2_MMU_SUBBLOCK_CI1)|| 4297 (sub_block_type == _SOC_SABER2_MMU_SUBBLOCK_CI0)) { 4298 if (soc_feature(unit, soc_feature_ddr3)) { 4299 soc_saber2_ci_block_get (unit, sub_block_type, &block); 4300 port = SOC_BLOCK_PORT(unit, block); 4301 } else { 4302 return SOC_E_NONE; 4303 } 4304 } 4305 4306 leaf_info = sub_block_info->info; 4307 4308 /* enable for this sub block */ 4309 leaf_enable_reg = sub_block_info->intr_mask_reg; 4310 SOC_IF_ERROR_RETURN 4311 (soc_saber2_process_sb_mmu_leaf_parity_enable (unit, port, 4312 leaf_enable_reg, leaf_info, enable)); 4313 4314 /* set MMU_INTR_MASK. 1 for disable. */ 4315 SOC_IF_ERROR_RETURN 4316 (soc_reg32_get(unit, mmu_en_reg, REG_PORT_ANY, 0, &en_rval)); 4317 soc_reg_field_set(unit, mmu_en_reg, &en_rval, 4318 sub_block_info->mmu_intr_mask_field, enable ? 0 : 1); 4319 SOC_IF_ERROR_RETURN 4320 (soc_reg32_set(unit, mmu_en_reg, REG_PORT_ANY, 0, en_rval)); 4321 4322 4323 return SOC_E_NONE; 4324 } 4325 4326 4327 STATIC 4328 int soc_saber2_process_sb_two_level_mmu_parity_enable(int unit, 4329 soc_reg_t mmu_en_reg, 4330 _soc_saber2_mmu_sub_block_two_level_t * sub_block_info, 4331 int enable) 4332 { 4333 uint32 en_rval; 4334 soc_reg_t internal_enable_reg; 4335 soc_reg_t leaf_enable_reg; 4336 soc_field_t internal_enable_field; 4337 int internal_index; 4338 soc_port_t port = REG_PORT_ANY; 4339 _soc_saber2_mmu_sub_block_internal_info_t * internal_info; 4340 _soc_saber2_mmu_sub_block_leaf_info_t * leaf_info; 4341 4342 if(sub_block_info->mmu_bit == 0) { 4343 /* reach the end of two level sub block table */ 4344 return SOC_E_NONE; 4345 } 4346 4347 /* some fields in MMU_INTR_MASK have been removed in 56270 */ 4348 if (!soc_reg_field_valid(unit, mmu_en_reg, sub_block_info->mmu_enable_field)) { 4349 return SOC_E_NONE; 4350 } 4351 4352 internal_info = sub_block_info->info; 4353 internal_enable_reg = sub_block_info->internal_enable_reg; 4354 4355 /* get mask register of level 1 sub block */ 4356 if (internal_enable_reg != 0) { 4357 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, internal_enable_reg, 4358 REG_PORT_ANY, 0, &en_rval)); 4359 } 4360 4361 for (internal_index = 0; ; internal_index++) { 4362 internal_info = &sub_block_info->info[internal_index]; 4363 if(internal_info->intr_bit == 0) { 4364 /* End of internal_info table */ 4365 break; 4366 } 4367 4368 internal_enable_field = internal_info->internal_enable_field; 4369 4370 if ((internal_enable_reg != 0) && 4371 (SOC_REG_FIELD_VALID(unit, internal_enable_reg, 4372 internal_enable_field))) { 4373 soc_reg_field_set(unit, internal_enable_reg, &en_rval, 4374 internal_enable_field, enable ? 0 : 1); 4375 } 4376 4377 /* get mask register of level 2 sub mask */ 4378 leaf_enable_reg = internal_info->leaf_enable_reg; 4379 leaf_info = internal_info->info; 4380 4381 SOC_IF_ERROR_RETURN 4382 (soc_saber2_process_sb_mmu_leaf_parity_enable (unit, port, 4383 leaf_enable_reg, leaf_info, enable)); 4384 } 4385 4386 /* write back mask register of level 1 sub block */ 4387 if (internal_enable_reg != 0) { 4388 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, internal_enable_reg, 4389 REG_PORT_ANY, 0, en_rval)); 4390 } 4391 4392 /* set MMU_INTR_MASK */ 4393 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, mmu_en_reg, REG_PORT_ANY, 0, 4394 &en_rval)); 4395 soc_reg_field_set(unit, mmu_en_reg, &en_rval, 4396 sub_block_info->mmu_enable_field, enable ? 0 : 1); 4397 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, mmu_en_reg, REG_PORT_ANY, 0, 4398 en_rval)); 4399 4400 return SOC_E_NONE; 4401 } 4402 4403 STATIC int 4404 soc_saber2_parity_enable_mmu(int unit, soc_reg_t mmu_en_reg, int enable) 4405 { 4406 int index; 4407 uint32 sub_block_num = 0; 4408 _soc_saber2_mmu_sub_block_one_level_t * sub_block = NULL; 4409 _soc_saber2_mmu_sub_block_two_level_t * two_level_sub_block = NULL; 4410 uint32 ext_pbmp_count=0; 4411 pbmp_t ext_pbmp; 4412 4413 ext_pbmp = soc_property_get_pbmp(unit, spn_PBMP_EXT_MEM, 0); 4414 SOC_PBMP_COUNT(ext_pbmp, ext_pbmp_count); 4415 4416 #ifdef BCM_METROLITE_SUPPORT 4417 if (SOC_IS_METROLITE(unit)) { 4418 sub_block_num = COUNTOF(_soc_metrolite_mmu_sub_blocks_type_1); 4419 sub_block = &_soc_metrolite_mmu_sub_blocks_type_1[0]; 4420 }else 4421 #endif 4422 { 4423 sub_block_num = COUNTOF(_soc_saber2_mmu_sub_blocks_type_1); 4424 sub_block = &_soc_saber2_mmu_sub_blocks_type_1[0]; 4425 } 4426 for (index = 0; index < sub_block_num; index++, sub_block++) { 4427 /* coverity[overrun-local:FALSE] */ 4428 if(sub_block->mmu_bit == 0) { 4429 break; 4430 } 4431 if ((sub_block->mmu_sub_block == _SOC_SABER2_MMU_SUBBLOCK_CI1) || 4432 (sub_block->mmu_sub_block == _SOC_SABER2_MMU_SUBBLOCK_CI0)) { 4433 if ((!soc_feature(unit, soc_feature_ddr3)) || 4434 (ext_pbmp_count == 0)) { 4435 continue; 4436 } 4437 } 4438 SOC_IF_ERROR_RETURN 4439 (soc_saber2_process_sb_one_level_mmu_parity_enable(unit, 4440 mmu_en_reg, sub_block, enable)); 4441 } 4442 4443 #ifdef BCM_METROLITE_SUPPORT 4444 if (SOC_IS_METROLITE(unit)) { 4445 sub_block_num = COUNTOF(_soc_metrolite_mmu_sub_blocks_type_2); 4446 two_level_sub_block = &_soc_metrolite_mmu_sub_blocks_type_2[0]; 4447 }else 4448 #endif 4449 { 4450 sub_block_num = COUNTOF(_soc_saber2_mmu_sub_blocks_type_2); 4451 two_level_sub_block = &_soc_saber2_mmu_sub_blocks_type_2[0]; 4452 } 4453 for (index = 0; index < sub_block_num; index++, two_level_sub_block++) { 4454 /* coverity[overrun-local:FALSE] */ 4455 if(two_level_sub_block->mmu_bit == 0) { 4456 break; 4457 } 4458 if (two_level_sub_block->mmu_sub_block == _SOC_SABER2_MMU_SUBBLOCK_EMC) { 4459 if ((!soc_feature(unit, soc_feature_ddr3)) || 4460 (ext_pbmp_count == 0)) { 4461 continue; 4462 } 4463 } 4464 SOC_IF_ERROR_RETURN 4465 (soc_saber2_process_sb_two_level_mmu_parity_enable(unit, 4466 mmu_en_reg, two_level_sub_block, enable)); 4467 } 4468 return SOC_E_NONE; 4469 } 4470 4471 STATIC int 4472 soc_saber2_parity_enable_info(int unit, soc_port_t port, 4473 soc_reg_t group_reg, 4474 uint32 *group_rval, 4475 const _soc_saber2_parity_info_t *info_list, 4476 int enable) 4477 { 4478 const _soc_saber2_parity_info_t *info; 4479 int info_index; 4480 soc_reg_t reg; 4481 uint32 rval; 4482 4483 /* Loop through each info entry in the list */ 4484 for (info_index = 0; ; info_index++) { 4485 info = &info_list[info_index]; 4486 if (info->type == _SOC_PARITY_TYPE_NONE) { 4487 /* End of table */ 4488 break; 4489 } 4490 4491 /* Enable the info entry in the group register */ 4492 soc_reg_field_set(unit, group_reg, group_rval, 4493 info->group_reg_enable_field, enable ? 1 : 0); 4494 4495 /* Handle different parity error reporting style */ 4496 switch (info->type) { 4497 case _SOC_PARITY_TYPE_PARITY: 4498 case _SOC_PARITY_TYPE_ECC: 4499 reg = info->enable_reg; 4500 if ((!SOC_REG_IS_VALID(unit, reg)) || (info->enable_field == INVALIDf)) { 4501 continue; 4502 } 4503 4504 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, reg, port, 0, &rval)); 4505 soc_reg_field_set(unit, reg, &rval, info->enable_field, 4506 enable ? 1 : 0); 4507 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, reg, port, 0, rval)); 4508 break; 4509 case _SOC_PARITY_TYPE_GENERIC: 4510 default: 4511 break; 4512 } /* Handle different parity error reporting style */ 4513 } /* Loop through each info entry in the route block */ 4514 4515 return SOC_E_NONE; 4516 } 4517 4518 4519 STATIC int 4520 soc_saber2_ser_engine_init(int unit) 4521 { 4522 int alloc_size; 4523 4524 /* First, make per-unit copy of the master TCAM list */ 4525 alloc_size = sizeof(_soc_saber2_tcam_ser_info_template); 4526 if (NULL == _soc_saber2_tcam_ser_info[unit]) { 4527 if ((_soc_saber2_tcam_ser_info[unit] = 4528 sal_alloc(alloc_size, "saber2 tcam list")) == NULL) { 4529 return SOC_E_MEMORY; 4530 } 4531 } 4532 /* Make a fresh copy of the TCAM template info */ 4533 sal_memcpy(_soc_saber2_tcam_ser_info[unit], 4534 &(_soc_saber2_tcam_ser_info_template), 4535 alloc_size); 4536 return soc_generic_ser_init(unit, _soc_saber2_tcam_ser_info[unit]); 4537 4538 4539 } 4540 4541 4542 4543 STATIC int 4544 soc_saber2_ser_enable_all(int unit, int enable) 4545 { 4546 uint16 bcount, pcount; 4547 int port = REG_PORT_ANY; 4548 uint32 rval, cmic_bit, cmic_rval = 0; 4549 soc_reg_t reg; 4550 soc_field_t field; 4551 int route_block_index, block_idx; 4552 const _soc_saber2_parity_route_block_t *route_block; 4553 soc_reg_t route_block_en_reg; 4554 uint32 route_block_rval; 4555 const _soc_saber2_parity_route_block_t *parity_intr_route_block = NULL; 4556 4557 #ifdef BCM_METROLITE_SUPPORT 4558 if (SOC_IS_METROLITE(unit)) { 4559 parity_intr_route_block = &_soc_metrolite_parity_intr_route_blocks[0]; 4560 } else 4561 #endif 4562 { 4563 parity_intr_route_block = &_soc_saber2_parity_intr_route_blocks[0]; 4564 } 4565 4566 /* Init IP/EP fifo */ 4567 for (bcount = 0; SOC_BLK_NONE != _soc_saber2_fifo_ser_block_info[bcount].blocktype; bcount++) { 4568 for (pcount = 0; 4569 _soc_saber2_fifo_ser_block_info[bcount].info[pcount].enable_reg != INVALIDr; 4570 pcount++) { 4571 reg = _soc_saber2_fifo_ser_block_info[bcount].info[pcount].enable_reg; 4572 field = _soc_saber2_fifo_ser_block_info[bcount].info[pcount].enable_field; 4573 4574 /* Some memories have different parity control regs in 56270/56260 */ 4575 if (!soc_reg_field_valid(unit, reg, field)) { 4576 continue; 4577 } 4578 /* some memories have removed ecc/parity field in 56270 */ 4579 if ((_soc_saber2_fifo_ser_block_info[bcount].info[pcount].mem != INVALIDm) && 4580 !soc_mem_field_valid(unit, 4581 _soc_saber2_fifo_ser_block_info[bcount].info[pcount].mem, 4582 _soc_saber2_fifo_ser_block_info[bcount].info[pcount].parity_field)) { 4583 continue; 4584 } 4585 4586 /* NOTE: Do not use the field modify routine in the following as 4587 some regs do not return the correct value due to which the 4588 modify routine skips the write */ 4589 SOC_IF_ERROR_RETURN 4590 (soc_reg32_get(unit, reg, port, 0, &rval)); 4591 if (soc_reg_field_valid(unit, reg, field)) { 4592 soc_reg_field_set(unit, reg, &rval, field, enable ? 1 : 0); 4593 } 4594 SOC_IF_ERROR_RETURN 4595 (soc_reg32_set(unit, reg, port, 0, rval)); 4596 switch (_soc_saber2_fifo_ser_block_info[bcount].info[pcount].type) { 4597 case 0: 4598 LOG_VERBOSE(BSL_LS_SOC_SOCMEM, 4599 (BSL_META_U(unit, 4600 "SER enable for mem: %s\n"), 4601 _soc_saber2_fifo_ser_block_info[bcount].info[pcount].mem != INVALIDm ? 4602 SOC_MEM_NAME(unit, _soc_saber2_fifo_ser_block_info[bcount].info[pcount].mem) : 4603 _soc_saber2_fifo_ser_block_info[bcount].info[pcount].name_str)); 4604 break; 4605 case 1: 4606 LOG_VERBOSE(BSL_LS_SOC_SOCMEM, 4607 (BSL_META_U(unit, 4608 "SER enable for reg: %s\n"), 4609 _soc_saber2_fifo_ser_block_info[bcount].info[pcount].reg != INVALIDr ? 4610 SOC_REG_NAME(unit, _soc_saber2_fifo_ser_block_info[bcount].info[pcount].reg) : 4611 _soc_saber2_fifo_ser_block_info[bcount].info[pcount].name_str)); 4612 break; 4613 default: break; 4614 } 4615 } 4616 4617 /* Loop through each place-and-route block entry */ 4618 for (route_block_index = 0; ; route_block_index++) { 4619 route_block = parity_intr_route_block + route_block_index; 4620 cmic_bit = route_block->cmic_bit; 4621 if (cmic_bit == 0) { 4622 /* End of table */ 4623 break; 4624 } 4625 if (route_block->blocktype == _soc_saber2_fifo_ser_block_info[bcount].blocktype) { 4626 /* New SER mechanism */ 4627 cmic_rval |= cmic_bit; 4628 if (route_block->enable_reg != INVALIDr) { 4629 SOC_IF_ERROR_RETURN 4630 (soc_reg_field32_modify(unit, route_block->enable_reg, 4631 REG_PORT_ANY, route_block->enable_field, enable ? 1 : 0)); 4632 } 4633 } 4634 } 4635 4636 /* reset (toggle) fifo if applicable */ 4637 if (_soc_saber2_fifo_ser_block_info[bcount].fifo_reset_reg != INVALIDr) { 4638 SOC_IF_ERROR_RETURN 4639 (soc_reg_field32_modify(unit, 4640 _soc_saber2_fifo_ser_block_info[bcount].fifo_reset_reg, 4641 REG_PORT_ANY, FIFO_RESETf, 1)); 4642 SOC_IF_ERROR_RETURN 4643 (soc_reg_field32_modify(unit, 4644 _soc_saber2_fifo_ser_block_info[bcount].fifo_reset_reg, 4645 REG_PORT_ANY, FIFO_RESETf, 0)); 4646 } 4647 } 4648 4649 /* Init MMU route block */ 4650 soc_saber2_parity_enable_mmu(unit, MMU_INTR_MASKr, enable); 4651 4652 4653 /* Init other blocks */ 4654 port = REG_PORT_ANY; 4655 /* Loop through each place-and-route block entry */ 4656 for (route_block_index = 0; ; route_block_index++) { 4657 route_block = parity_intr_route_block + route_block_index; 4658 cmic_bit = route_block->cmic_bit; 4659 if (cmic_bit == 0) { 4660 /* End of table */ 4661 break; 4662 } 4663 /* Enable the route block entry in the CMIC register */ 4664 if (enable) { 4665 cmic_rval |= cmic_bit; 4666 } 4667 4668 route_block_en_reg = route_block->enable_reg; 4669 4670 /* Get block and port for MXQ and RXLP and TXLP */ 4671 if ((route_block->blocktype == SOC_BLK_MXQPORT) || 4672 (route_block->blocktype == SOC_BLK_TXLP) || 4673 (route_block->blocktype == SOC_BLK_RXLP)) { 4674 SOC_BLOCK_ITER(unit, block_idx, route_block->blocktype) { 4675 if (SOC_BLOCK_INFO(unit, block_idx).number == route_block->id) { 4676 port = SOC_BLOCK_PORT(unit, block_idx); 4677 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, route_block_en_reg, 4678 port, 0, &route_block_rval)); 4679 SOC_IF_ERROR_RETURN(soc_saber2_parity_enable_info( 4680 unit, port, route_block_en_reg, 4681 &route_block_rval, 4682 route_block->info, enable)); 4683 /* coverity[negative_returns : FALSE] */ 4684 /* Write per route block parity enable register */ 4685 SOC_IF_ERROR_RETURN(soc_reg32_set( 4686 unit, route_block_en_reg, 4687 port, 0, route_block_rval)); 4688 break; 4689 } 4690 } 4691 } 4692 4693 4694 /* enable SVM,Flex counter in IP/EP */ 4695 if (((route_block->blocktype == SOC_BLK_IPIPE) || 4696 (route_block->blocktype == SOC_BLK_EPIPE)) && 4697 (route_block->info != NULL)) { 4698 for(block_idx = 0; route_block->info[block_idx].type != _SOC_PARITY_TYPE_NONE; 4699 block_idx ++) { 4700 4701 /* These memories(flex ctr 4~7) have been removed in 56270 */ 4702 if (!SOC_MEM_IS_VALID(unit, route_block->info[block_idx].mem)) { 4703 continue; 4704 } 4705 4706 if (route_block->info[block_idx].group_reg_enable_field != INVALIDf) { 4707 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, 4708 route_block_en_reg, REG_PORT_ANY, 4709 route_block->info[block_idx].group_reg_enable_field, enable ? 1 : 0)); 4710 } 4711 4712 if (route_block->info[block_idx].enable_reg != INVALIDr) { 4713 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, 4714 route_block->info[block_idx].enable_reg, REG_PORT_ANY, 4715 route_block->info[block_idx].enable_field, enable ? 1 : 0)); 4716 } 4717 } 4718 4719 } 4720 4721 } /* Loop through each place-and-route block entry */ 4722 4723 /* enable interrupt mask */ 4724 4725 SOC_IF_ERROR_RETURN(READ_MISCCONFIGr(unit, &rval)); 4726 soc_reg_field_set(unit, MISCCONFIGr, &rval, PARITY_STAT_CLEARf, 1); 4727 SOC_IF_ERROR_RETURN(WRITE_MISCCONFIGr(unit, rval)); 4728 4729 SOC_IF_ERROR_RETURN(READ_THDO_MISCCONFIGr(unit, &rval)); 4730 soc_reg_field_set(unit, THDO_MISCCONFIGr, &rval, STAT_CLEARf, 1); 4731 SOC_IF_ERROR_RETURN(WRITE_THDO_MISCCONFIGr(unit, rval)); 4732 4733 SOC_IF_ERROR_RETURN(READ_WRED_MISCCONFIGr(unit, &rval)); 4734 soc_reg_field_set(unit, WRED_MISCCONFIGr, &rval, PARITY_STAT_CLRf, 1); 4735 SOC_IF_ERROR_RETURN(WRITE_WRED_MISCCONFIGr(unit, rval)); 4736 4737 SOC_IF_ERROR_RETURN(READ_RQE_GLOBAL_CONFIGr(unit, &rval)); 4738 soc_reg_field_set(unit, RQE_GLOBAL_CONFIGr, &rval, PARITY_STAT_CLRf, 1); 4739 SOC_IF_ERROR_RETURN(WRITE_RQE_GLOBAL_CONFIGr(unit, rval)); 4740 4741 SOC_IF_ERROR_RETURN(READ_MISCCONFIGr(unit, &rval)); 4742 soc_reg_field_set(unit, MISCCONFIGr, &rval, PARITY_CHK_ENf, 4743 enable ? 1 : 0); 4744 soc_reg_field_set(unit, MISCCONFIGr, &rval, PARITY_GEN_ENf, 4745 enable ? 1 : 0); 4746 soc_reg_field_set(unit, MISCCONFIGr, &rval, PARITY_STAT_CLEARf, 0); 4747 SOC_IF_ERROR_RETURN(WRITE_MISCCONFIGr(unit, rval)); 4748 4749 SOC_IF_ERROR_RETURN(READ_THDO_MISCCONFIGr(unit, &rval)); 4750 soc_reg_field_set(unit, THDO_MISCCONFIGr, &rval, PARITY_CHK_ENf, 4751 enable ? 1 : 0); 4752 soc_reg_field_set(unit, THDO_MISCCONFIGr, &rval, PARITY_GEN_ENf, 4753 enable ? 1 : 0); 4754 soc_reg_field_set(unit, THDO_MISCCONFIGr, &rval, STAT_CLEARf, 0); 4755 SOC_IF_ERROR_RETURN(WRITE_THDO_MISCCONFIGr(unit, rval)); 4756 4757 SOC_IF_ERROR_RETURN(READ_WRED_MISCCONFIGr(unit, &rval)); 4758 soc_reg_field_set(unit, WRED_MISCCONFIGr, &rval, PARITY_CHK_ENf, 4759 enable ? 1 : 0); 4760 soc_reg_field_set(unit, WRED_MISCCONFIGr, &rval, PARITY_GEN_ENf, 4761 enable ? 1 : 0); 4762 soc_reg_field_set(unit, WRED_MISCCONFIGr, &rval, PARITY_STAT_CLRf, 0); 4763 SOC_IF_ERROR_RETURN(WRITE_WRED_MISCCONFIGr(unit, rval)); 4764 4765 SOC_IF_ERROR_RETURN(READ_RQE_GLOBAL_CONFIGr(unit, &rval)); 4766 soc_reg_field_set(unit, RQE_GLOBAL_CONFIGr, &rval, PARITY_CHK_ENf, 4767 enable ? 1 : 0); 4768 soc_reg_field_set(unit, RQE_GLOBAL_CONFIGr, &rval, PARITY_GEN_ENf, 4769 enable ? 1 : 0); 4770 soc_reg_field_set(unit, RQE_GLOBAL_CONFIGr, &rval, PARITY_STAT_CLRf, 0); 4771 SOC_IF_ERROR_RETURN(WRITE_RQE_GLOBAL_CONFIGr(unit, rval)); 4772 4773 SOC_IF_ERROR_RETURN(READ_INTFI_ECC_CONTROLr(unit, &rval)); 4774 soc_reg_field_set(unit, INTFI_ECC_CONTROLr, &rval, ENABLE_ECCf, 4775 enable ? 1 : 0); 4776 SOC_IF_ERROR_RETURN(WRITE_INTFI_ECC_CONTROLr(unit, rval)); 4777 4778 4779 if (enable) 4780 { 4781 /* Write CMIC enable register */ 4782 (void)soc_cmicm_intr3_enable(unit, cmic_rval); 4783 } else { 4784 /* Write CMIC disable register */ 4785 (void)soc_cmicm_intr3_disable(unit, cmic_rval); 4786 } 4787 4788 /* Set SAT interrupt */ 4789 if (soc_feature(unit, soc_feature_sat) && 4790 soc_property_get(unit, spn_SAT_ENABLE, 0)) { 4791 if (enable) { 4792 (void)soc_cmicm_intr3_enable(unit, _SOC_SABER2_SAT_CMIC_BIT); 4793 } else { 4794 (void)soc_cmicm_intr3_disable(unit, _SOC_SABER2_SAT_CMIC_BIT); 4795 } 4796 } 4797 4798 return SOC_E_NONE; 4799 } 4800 4801 STATIC void 4802 soc_saber2_print_ser_fifo_details(int unit, uint8 regmem, soc_block_t blk, 4803 uint32 sblk, uint32 address, 4804 uint32 stage, uint32 base, uint32 index, 4805 uint32 hwmbase, uint32 type, uint8 drop, 4806 uint8 non_sbus) 4807 { 4808 4809 if (bsl_check(bslLayerSoc, bslSourceCommon, bslSeverityError, unit)) { 4810 switch (type) { 4811 case 0: 4812 LOG_ERROR(BSL_LS_SOC_COMMON, 4813 (BSL_META_U(unit, 4814 "Error in: SOP cell.\n"))); 4815 break; 4816 case 1: 4817 LOG_ERROR(BSL_LS_SOC_COMMON, 4818 (BSL_META_U(unit, 4819 "Error in: MOP cell.\n"))); 4820 break; 4821 case 2: 4822 LOG_ERROR(BSL_LS_SOC_COMMON, 4823 (BSL_META_U(unit, 4824 "Error in: EOP cell.\n"))); 4825 break; 4826 case 3: 4827 LOG_ERROR(BSL_LS_SOC_COMMON, 4828 (BSL_META_U(unit, 4829 "Error in: SBUS transaction.\n"))); 4830 break; 4831 case 4: 4832 LOG_ERROR(BSL_LS_SOC_COMMON, 4833 (BSL_META_U(unit, 4834 "Error in: miscellaneous transaction.\n"))); 4835 break; 4836 default: 4837 LOG_ERROR(BSL_LS_SOC_COMMON, 4838 (BSL_META_U(unit, 4839 "Invalid error reported !!\n"))); 4840 break; 4841 } 4842 LOG_ERROR(BSL_LS_SOC_COMMON, 4843 (BSL_META_U(unit, 4844 "Blk: %d, Address: 0x%08x, base: 0x%x, stage: %d, index: %d\n"), 4845 sblk, address, base, stage, index)); 4846 4847 if (drop) { 4848 LOG_ERROR(BSL_LS_SOC_COMMON, 4849 (BSL_META_U(unit, 4850 "SER caused packet drop.\n"))); 4851 } 4852 } 4853 } 4854 4855 STATIC void 4856 _soc_saber2_mem_rename(soc_mem_t *memory) 4857 { 4858 switch(*memory) { 4859 case L3_TUNNELm: 4860 *memory = L3_TUNNEL_DATA_ONLYm; 4861 break; 4862 default: 4863 break; 4864 } 4865 } 4866 4867 STATIC void 4868 soc_saber2_ser_control_reg_get(int unit, CONST _soc_saber2_fifo_ser_info_t *fifo_ser_list, 4869 soc_mem_t mem, 4870 soc_reg_t *ser_control_reg, 4871 soc_field_t *ser_enable_field) 4872 { 4873 int i; 4874 4875 if ((fifo_ser_list == NULL) || (ser_control_reg == NULL) || 4876 (ser_enable_field == NULL)) { 4877 return; 4878 } 4879 4880 _soc_saber2_mem_rename(&mem); 4881 4882 for (i = 0; fifo_ser_list[i].enable_reg != INVALIDr; i++) { 4883 if (fifo_ser_list[i].mem == mem) { 4884 /* Some memories have different parity control regs in 56270/56260 */ 4885 if (soc_reg_field_valid(unit, fifo_ser_list[i].enable_reg, 4886 fifo_ser_list[i].enable_field)) { 4887 *ser_control_reg = fifo_ser_list[i].enable_reg; 4888 *ser_enable_field = fifo_ser_list[i].enable_field; 4889 break; 4890 } 4891 } 4892 } 4893 4894 return; 4895 } 4896 4897 4898 STATIC int 4899 soc_saber2_populate_ser_log(int unit, soc_reg_t parity_enable_reg, 4900 soc_field_t parity_enable_field, 4901 soc_mem_t mem, 4902 int mem_block, 4903 soc_acc_type_t acc_type, 4904 int index, 4905 sal_usecs_t detect_time, 4906 uint32 sblk, 4907 uint32 address) 4908 { 4909 uint32 tmp_entry[SOC_MAX_MEM_WORDS]; 4910 int log_entry_size, id, entry_dw; 4911 uint32 *cache; 4912 uint8 *vmap; 4913 soc_ser_log_tlv_memory_t log_mem; 4914 soc_ser_log_tlv_generic_t log_generic; 4915 4916 sal_memset(&log_generic, 0, sizeof(log_generic)); 4917 sal_memset(&log_mem, 0, sizeof(log_mem)); 4918 4919 /* 4920 must be large enough for at least generic and terminator, as well as the 4921 memory type since we might decode it in soc_ser_correction. 4922 */ 4923 log_entry_size = sizeof(soc_ser_log_tlv_hdr_t)*3 + 4924 sizeof(soc_ser_log_tlv_generic_t) + 4925 sizeof(soc_ser_log_tlv_memory_t); 4926 4927 if (mem == INVALIDm) { 4928 mem = soc_addr_to_mem_extended(unit, sblk, acc_type, address); 4929 if (mem != INVALIDm) { 4930 if (sblk) { 4931 SOC_MEM_BLOCK_ITER(unit, mem, mem_block) { 4932 if (SOC_BLOCK2OFFSET(unit, mem_block) == sblk) { 4933 break; 4934 } 4935 } 4936 } else { 4937 mem_block = SOC_MEM_BLOCK_ANY(unit, mem); 4938 } 4939 } 4940 } 4941 /* 4942 If we have decoded the memory we can record its contents/cache 4943 */ 4944 if((mem != INVALIDm) && 4945 (SOC_MEM_SER_CORRECTION_TYPE(unit, mem) != SOC_MEM_FLAG_SER_SPECIAL) && 4946 (SOC_MEM_SER_CORRECTION_TYPE(unit, mem) != 0)) { 4947 entry_dw = soc_mem_entry_words(unit, mem); 4948 4949 /* Check to make sure this isn't a duplicate */ 4950 /* Search for a log entry with the same mem, and index with within the last 5 seconds */ 4951 if (soc_ser_log_find_recent(unit, mem, index, sal_time_usecs()) > 0) { 4952 return 0; 4953 } 4954 4955 log_entry_size += sizeof(soc_ser_log_tlv_hdr_t) + entry_dw*4; 4956 4957 cache = SOC_MEM_STATE(unit, mem).cache[mem_block]; 4958 vmap = SOC_MEM_STATE(unit, mem).vmap[mem_block]; 4959 if(cache != NULL && CACHE_VMAP_TST(vmap, index)) { 4960 log_entry_size += sizeof(soc_ser_log_tlv_hdr_t) + entry_dw*4; 4961 } 4962 4963 /* create the entry based on determined size, save id */ 4964 id = soc_ser_log_create_entry(unit, log_entry_size); 4965 4966 /* Add the memory information to the log now so we can detect duplicate errors */ 4967 log_generic.time = detect_time; 4968 log_mem.memory = mem; 4969 log_mem.index = index; 4970 soc_ser_log_add_tlv(unit, id, SOC_SER_LOG_TLV_MEMORY, 4971 sizeof(soc_ser_log_tlv_memory_t), &log_mem); 4972 soc_ser_log_add_tlv(unit, id, SOC_SER_LOG_TLV_GENERIC, 4973 sizeof(soc_ser_log_tlv_generic_t), &log_generic); 4974 4975 /* Disable Parity */ 4976 if ((parity_enable_reg != INVALIDr) && 4977 (parity_enable_field != INVALIDf)) { 4978 if (soc_reg_field32_modify(unit, parity_enable_reg, 4979 REG_PORT_ANY, parity_enable_field, 0) < 0) { 4980 return 0; 4981 } 4982 } 4983 4984 4985 /* read the memory into a buffer */ 4986 if (acc_type == _SOC_ACC_TYPE_PIPE_Y) { 4987 soc_mem_pipe_select_read(unit, SOC_MEM_NO_FLAGS, mem, mem_block, 4988 acc_type, index, tmp_entry); 4989 } else { 4990 /*Enable NACK on read */ 4991 soc_mem_read_extended(unit, SOC_MEM_SCHAN_ERR_RETURN, 4992 mem, 0, mem_block, 4993 index, tmp_entry); 4994 } 4995 4996 /* Enable Parity */ 4997 if ((parity_enable_reg != INVALIDr) && 4998 (parity_enable_field != INVALIDf)) { 4999 if (soc_reg_field32_modify(unit, parity_enable_reg, 5000 REG_PORT_ANY, parity_enable_field, 1) < 0) { 5001 return 0; 5002 } 5003 } 5004 5005 /* fill in the memory contents tlv */ 5006 if (soc_ser_log_add_tlv(unit, id, SOC_SER_LOG_TLV_CONTENTS, 5007 entry_dw*4, tmp_entry) < 0) { 5008 return 0; 5009 } 5010 5011 5012 if(cache != NULL && CACHE_VMAP_TST(vmap, index)) { 5013 /* fill in the memory cache tlv */ 5014 if (soc_ser_log_add_tlv(unit, id, SOC_SER_LOG_TLV_CACHE, 5015 entry_dw*4, (cache + index*entry_dw)) < 0) { 5016 return 0; 5017 } 5018 } 5019 } else { 5020 id = soc_ser_log_create_entry(unit, log_entry_size); 5021 } 5022 5023 return id; 5024 } 5025 5026 STATIC int 5027 soc_saber2_process_ser_fifo(int unit, soc_block_t blk, char *prefix_str) 5028 { 5029 int rv = SOC_E_NONE; 5030 uint8 bidx, idx_offset; 5031 soc_mem_t mem; 5032 char blk_str[10]; 5033 soc_reg_t reg = INVALIDr; 5034 _soc_ser_correct_info_t spci; 5035 _soc_saber2_fifo_ser_info_t* ser_info_table = NULL; 5036 soc_reg_t parity_enable_reg = INVALIDr; 5037 soc_field_t parity_enable_field = INVALIDf; 5038 5039 uint32 reg_val, mask, entry[SOC_MAX_MEM_WORDS] = { 0 }; 5040 uint32 stage = 0, addrbase = 0, index = 0, hwmbase = 0, type = 0, multiple = 0; 5041 uint32 sblk = 0, inst_type = 0, regmem = 0, non_sbus = 0, drop = 0, ecc_parity = 0, address = 0; 5042 5043 5044 switch (blk) { 5045 case SOC_BLK_IPIPE: 5046 mem = ING_SER_FIFOm; 5047 mask = 0x803800; /* IP0~3 bit 11,12,13,23 in CMIC_CMC0_IRQ_STAT3 */ 5048 ser_info_table = _soc_saber2_ip_ser_info; 5049 sal_sprintf(blk_str, "IPIPE"); 5050 break; 5051 case SOC_BLK_EPIPE: 5052 mem = EGR_SER_FIFOm; 5053 mask = 0x1; /*SER_FIFO_NON_EMPTY in EGR_INTR1_STATUSr */ 5054 reg = EGR_INTR1_STATUSr; 5055 ser_info_table = _soc_saber2_ep_ser_info; 5056 sal_sprintf(blk_str, "EPIPE"); 5057 break; 5058 default: 5059 return SOC_E_PARAM; 5060 } 5061 5062 do { 5063 rv = soc_mem_pop(unit, mem, MEM_BLOCK_ANY, entry); 5064 SOC_IF_ERROR_RETURN(rv); 5065 5066 /* process entry. */ 5067 if (soc_mem_field32_get(unit, mem, entry, VALIDf)) { 5068 multiple = soc_mem_field32_get(unit, mem, entry, MULTIPLEf); 5069 ecc_parity = soc_mem_field32_get(unit, mem, entry, ECC_PARITYf); 5070 regmem = soc_mem_field32_get(unit, mem, entry, MEM_TYPEf); 5071 address = soc_mem_field32_get(unit, mem, entry, ADDRESSf); 5072 stage = soc_mem_field32_get(unit, mem, entry, PIPE_STAGEf); 5073 type = soc_mem_field32_get(unit, mem, entry, INSTRUCTION_TYPEf); 5074 drop = soc_mem_field32_get(unit, mem, entry, DROPf); 5075 inst_type = soc_mem_field32_get(unit, mem, entry, INSTRUCTION_TYPEf); 5076 5077 SOC_BLOCK_ITER(unit, bidx, blk) { 5078 sblk = SOC_BLOCK2SCH(unit, bidx); 5079 break; 5080 } 5081 LOG_ERROR(BSL_LS_SOC_COMMON, 5082 (BSL_META_U(unit, 5083 "%s\n"), prefix_str)); 5084 if (multiple) { 5085 LOG_ERROR(BSL_LS_SOC_COMMON, 5086 (BSL_META_U(unit, 5087 "Multiple: "))); 5088 } 5089 if (regmem == _SOC_SABER2_SER_REG) { 5090 LOG_ERROR(BSL_LS_SOC_COMMON, 5091 (BSL_META_U(unit, 5092 "Reg: "))); 5093 } else { 5094 LOG_ERROR(BSL_LS_SOC_COMMON, 5095 (BSL_META_U(unit, 5096 "Mem: "))); 5097 } 5098 spci.double_bit = 0; 5099 switch (ecc_parity) { 5100 case 0: 5101 LOG_ERROR(BSL_LS_SOC_COMMON, 5102 (BSL_META_U(unit, 5103 "Parity error..\n"))); 5104 break; 5105 case 1: 5106 LOG_ERROR(BSL_LS_SOC_COMMON, 5107 (BSL_META_U(unit, 5108 "Corrected single bit ECC error..\n"))); 5109 break; 5110 case 2: 5111 LOG_ERROR(BSL_LS_SOC_COMMON, 5112 (BSL_META_U(unit, 5113 "Double or Multiple bit ECC error..\n"))); 5114 spci.double_bit = 1; 5115 break; 5116 default: 5117 LOG_ERROR(BSL_LS_SOC_COMMON, 5118 (BSL_META_U(unit, 5119 "Invalid SER issue !!\n"))); 5120 return SOC_E_INTERNAL; 5121 } 5122 if (regmem == _SOC_SABER2_SER_MEM) { 5123 /* process mem */ 5124 non_sbus = soc_mem_field32_get(unit, mem, entry, NON_SBUSf); 5125 addrbase = soc_mem_field32_get(unit, mem, entry, MEMBASEf); 5126 index = soc_mem_field32_get(unit, mem, entry, MEMINDEXf); 5127 hwmbase = soc_mem_field32_get(unit, mem, entry, HWMEMBASEf); 5128 5129 if (non_sbus == 0) { 5130 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 5131 ecc_parity == 0 ? 5132 SOC_SWITCH_EVENT_DATA_ERROR_PARITY : 5133 SOC_SWITCH_EVENT_DATA_ERROR_ECC, 5134 sblk | SOC_SER_ERROR_DATA_BLK_ADDR_SET, 5135 address); 5136 soc_saber2_print_ser_fifo_details(unit, 0, blk, sblk, address, 5137 stage, addrbase, index, hwmbase, 5138 type, drop, non_sbus); 5139 sal_memset(&spci, 0, sizeof(spci)); 5140 spci.flags = SOC_SER_SRC_MEM; 5141 spci.reg = INVALIDr; 5142 spci.mem = INVALIDm; 5143 spci.pipe_num = 0; 5144 spci.blk_type = blk; 5145 spci.sblk = sblk; 5146 spci.addr = address - index; 5147 spci.index = index; 5148 spci.stage = stage; 5149 spci.detect_time = sal_time_usecs(); 5150 spci.parity_type = ecc_parity ? SOC_PARITY_TYPE_ECC : SOC_PARITY_TYPE_PARITY; 5151 spci.double_bit = (ecc_parity == 2) ? 1 : 0; 5152 5153 /* Try to decode mem first */ 5154 spci.mem = soc_addr_to_mem_extended(unit, 5155 spci.sblk, SOC_MEM_ACC_TYPE(unit, mem), spci.addr); 5156 5157 if (spci.mem != INVALIDm) { 5158 spci.acc_type = SOC_MEM_ACC_TYPE(unit, mem); 5159 spci.flags |= SOC_SER_REG_MEM_KNOWN; 5160 spci.index = soc_saber2_mem_index_remap(unit, spci.mem, index); 5161 } 5162 else { 5163 /* Invalid mem, use the first acc_type_ptr*/ 5164 spci.acc_type = SOC_MEM_ACC_TYPE(unit, mem); 5165 spci.flags |= SOC_SER_REG_MEM_UNKNOWN; 5166 } 5167 5168 if (spci.mem != INVALIDm) { 5169 soc_saber2_ser_control_reg_get(unit, ser_info_table, 5170 spci.mem, 5171 &parity_enable_reg, 5172 &parity_enable_field); 5173 } 5174 if (spci.mem != INVALIDm) { 5175 MEM_LOCK(unit,spci.mem); 5176 } 5177 spci.log_id = soc_saber2_populate_ser_log(unit, 5178 parity_enable_reg, 5179 parity_enable_field, 5180 spci.mem, 5181 bidx, 5182 spci.acc_type, 5183 spci.index, 5184 spci.detect_time, 5185 spci.sblk, 5186 spci.addr); 5187 if (spci.mem != INVALIDm) { 5188 MEM_UNLOCK(unit,spci.mem); 5189 } 5190 if (spci.mem == L2_ENTRY_ONLYm ) { 5191 spci.mem = L2Xm; 5192 } 5193 5194 rv = soc_ser_correction(unit, &spci); 5195 5196 /* HW issue: SER_FIFO does not report correct 5197 * STORM_CONTROL_METER_MAPPINGm's index for packet 5198 * operation. This work-around triggers 4 times 'MEM_READ' 5199 * to get valid memory index and correct the entry. 5200 */ 5201 if ((spci.mem == FP_STORM_CONTROL_METERSm) && 5202 (inst_type == 2) && 5203 (!SOC_IS_METROLITE(unit))) { 5204 for (idx_offset = 0; idx_offset <= 3; idx_offset ++) { 5205 (void) soc_mem_read(unit, FP_STORM_CONTROL_METERSm, 5206 MEM_BLOCK_ANY, 4*index + idx_offset, entry); 5207 } 5208 } 5209 5210 if (SOC_FAILURE(rv)) { 5211 if (rv != SOC_E_NOT_FOUND) { 5212 /* Add reporting failed to correct event flag to application */ 5213 soc_event_generate(unit, 5214 SOC_SWITCH_EVENT_PARITY_ERROR, 5215 SOC_SWITCH_EVENT_DATA_ERROR_FAILEDTOCORRECT, 5216 sblk | SOC_SER_ERROR_DATA_BLK_ADDR_SET, 5217 address); 5218 return rv; 5219 } 5220 } 5221 if (spci.log_id != 0) { 5222 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 5223 SOC_SWITCH_EVENT_DATA_ERROR_LOG, 5224 spci.log_id, 0); 5225 } 5226 5227 } else { 5228 LOG_ERROR(BSL_LS_SOC_COMMON, 5229 (BSL_META_U(unit, 5230 "%s SER mem address un-accessable !!\n"), blk_str)); 5231 soc_saber2_print_ser_fifo_details(unit, 0, blk, sblk, address, 5232 stage, addrbase, index, hwmbase, 5233 type, drop, non_sbus); 5234 } 5235 } else { 5236 /* process reg */ 5237 non_sbus = soc_mem_field32_get(unit, mem, entry, NON_SBUSf); 5238 addrbase = soc_mem_field32_get(unit, mem, entry, REGBASEf); 5239 index = soc_mem_field32_get(unit, mem, entry, REGINDEXf); 5240 5241 if (non_sbus == 0) { 5242 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 5243 ecc_parity == 0 ? 5244 SOC_SWITCH_EVENT_DATA_ERROR_PARITY : 5245 SOC_SWITCH_EVENT_DATA_ERROR_ECC, 5246 sblk | SOC_SER_ERROR_DATA_BLK_ADDR_SET, 5247 address); 5248 soc_saber2_print_ser_fifo_details(unit, 1, blk, sblk, address, 5249 stage, addrbase, index, 0, type, 5250 drop, non_sbus); 5251 sal_memset(&spci, 0, sizeof(spci)); 5252 spci.flags = SOC_SER_SRC_REG | SOC_SER_REG_MEM_UNKNOWN; 5253 spci.reg = INVALIDr; 5254 spci.mem = INVALIDm; 5255 spci.blk_type = blk; 5256 spci.sblk = sblk; 5257 spci.addr = address; 5258 spci.index = index; 5259 spci.stage = stage; 5260 spci.detect_time = sal_time_usecs(); 5261 spci.parity_type = ecc_parity ? SOC_PARITY_TYPE_ECC : SOC_PARITY_TYPE_PARITY; 5262 spci.double_bit = (ecc_parity == 2) ? 1 : 0; 5263 5264 spci.acc_type = SOC_MEM_ACC_TYPE(unit, mem); 5265 spci.log_id = soc_ser_log_create_entry(unit, 5266 sizeof(soc_ser_log_tlv_generic_t) + 5267 sizeof(soc_ser_log_tlv_register_t) + 5268 sizeof(soc_ser_log_tlv_hdr_t) *3); 5269 rv = soc_ser_correction(unit, &spci); 5270 SOC_IF_ERROR_RETURN(rv); 5271 5272 /* Add reporting failed to correct event flag to application */ 5273 soc_event_generate(unit, 5274 SOC_SWITCH_EVENT_PARITY_ERROR, 5275 SOC_SWITCH_EVENT_DATA_ERROR_FAILEDTOCORRECT, 5276 sblk | SOC_SER_ERROR_DATA_BLK_ADDR_SET, 5277 address); 5278 5279 if (spci.log_id != 0) { 5280 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 5281 SOC_SWITCH_EVENT_DATA_ERROR_LOG, 5282 spci.log_id, 0); 5283 } 5284 break; 5285 5286 } else { 5287 LOG_ERROR(BSL_LS_SOC_COMMON, 5288 (BSL_META_U(unit, 5289 "%s SER reg address un-accessable !!\n"), blk_str)); 5290 soc_saber2_print_ser_fifo_details(unit, 0, blk, sblk, address, 5291 stage, addrbase, index, hwmbase, 5292 type, drop, non_sbus); 5293 } 5294 } 5295 } else { 5296 LOG_ERROR(BSL_LS_SOC_COMMON, 5297 (BSL_META_U(unit, 5298 "unit %d Got invalid mem pop from %s !!\n"), 5299 unit, SOC_MEM_NAME(unit, mem))); 5300 } 5301 /* check if any more pending */ 5302 if (reg == INVALIDr) { 5303 rv = READ_CMIC_CMC0_IRQ_STAT3r(unit, ®_val); 5304 } else { 5305 rv = soc_reg32_get(unit, reg, REG_PORT_ANY, 0, ®_val); 5306 } 5307 SOC_IF_ERROR_RETURN(rv); 5308 } while (reg_val & mask); 5309 5310 5311 return SOC_E_NONE; 5312 } 5313 5314 STATIC 5315 void soc_saber2_mem_parity_info(int unit, int block_idx, int pipe, 5316 soc_field_t field_enum, uint32 *minfo) 5317 { 5318 *minfo = (SOC_BLOCK2SCH(unit, block_idx) << SOC_ERROR_BLK_BP) 5319 | ((pipe & 0xff) << SOC_ERROR_PIPE_BP) 5320 | (field_enum & SOC_ERROR_FIELD_ENUM_MASK); 5321 } 5322 5323 5324 5325 STATIC 5326 int soc_saber2_process_sb_mmu_leaf_parity_error (int unit, 5327 _soc_saber2_mmu_subblock_type_t sub_block_type, 5328 soc_port_t port, 5329 soc_reg_t leaf_enable_reg, 5330 soc_reg_t leaf_status_reg, 5331 _soc_saber2_mmu_sub_block_leaf_info_t * leaf_info) 5332 { 5333 uint32 stat_rval, en_rval, minfo, rval, min_addr, stat_field, mask_field; 5334 uint32 intr_bit, sblk = 0; 5335 int index = 0, blk_idx; 5336 _soc_saber2_mmu_sub_block_leaf_info_t *info; 5337 char prefix_str[10]; 5338 char *reg_str; 5339 char *field_str; 5340 _soc_ser_correct_info_t spci; 5341 int rv; 5342 5343 sal_sprintf(prefix_str, "unit:%d", unit); 5344 5345 if(sub_block_type == _SOC_SABER2_MMU_SUBBLOCK_INFO2) { 5346 SOC_IF_ERROR_RETURN 5347 (soc_reg32_get(unit, leaf_status_reg, port, 0, &stat_rval)); 5348 5349 stat_field = soc_reg_field_get( 5350 unit, leaf_status_reg, stat_rval,leaf_info->status_field); 5351 5352 SOC_IF_ERROR_RETURN 5353 (soc_reg32_get(unit, leaf_status_reg, port, 0, &en_rval)); 5354 5355 mask_field = soc_reg_field_get( 5356 unit, leaf_enable_reg, en_rval,leaf_info->enable_field); 5357 5358 stat_field &= (~mask_field); 5359 5360 if(stat_field == 0) { 5361 return SOC_E_NONE; 5362 } 5363 5364 } else { 5365 SOC_IF_ERROR_RETURN 5366 (soc_reg32_get(unit, leaf_status_reg, port, 0, &stat_rval)); 5367 SOC_IF_ERROR_RETURN 5368 (soc_reg32_get(unit, leaf_enable_reg, port, 0, &en_rval)); 5369 5370 /* mask bit =0 for enable */ 5371 if (leaf_status_reg == RQE_EXTQ_REPLICATION_COUNTr) { 5372 stat_rval &= ((~en_rval) << 11); 5373 } else { 5374 stat_rval &= (~en_rval); 5375 } 5376 5377 if (stat_rval == 0) { 5378 return SOC_E_NONE; 5379 } 5380 5381 LOG_CLI((BSL_META_U(unit, 5382 "\nleaf_parity: status reg:%s value 0x:%x mask reg:%s value 0x:%x\n"), 5383 SOC_REG_NAME(unit, leaf_status_reg), stat_rval, 5384 SOC_REG_NAME(unit, leaf_enable_reg), en_rval)); 5385 5386 #ifdef BCM_METROLITE_SUPPORT 5387 if (SOC_IS_METROLITE(unit)) { 5388 /* If WRED FSM received a new update tick, while it was not done with the previous update 5389 * cycle. The UPDATE_INTRPT will be triggered. Write 1 to clear. */ 5390 if ((leaf_status_reg == WRED_PARITY_ERROR_BITMAPr) && 5391 ((stat_rval & 0x4000000) != 0)) { 5392 SOC_IF_ERROR_RETURN(READ_WRED_PARITY_ERROR_BITMAPr(unit, &rval)); 5393 soc_reg_field_set(unit, WRED_PARITY_ERROR_BITMAPr, &rval, UPDATE_INTRPT_STATUSf, 1); 5394 SOC_IF_ERROR_RETURN(WRITE_WRED_PARITY_ERROR_BITMAPr(unit, rval)); 5395 } 5396 } 5397 #endif 5398 } 5399 5400 for (index = 0; ; index++) { 5401 info = &leaf_info[index]; 5402 intr_bit = info->intr_bit; 5403 if(intr_bit == 0) { 5404 /* reach the end of leaf table */ 5405 return SOC_E_NONE; 5406 } 5407 5408 /* some fields have been removed in 56270 */ 5409 if (!soc_reg_field_valid(unit, leaf_status_reg, info->status_field)) { 5410 continue; 5411 } 5412 5413 /* get a match */ 5414 if (stat_rval & intr_bit) { 5415 field_str = SOC_FIELD_NAME(unit, info->status_field); 5416 reg_str = SOC_REG_NAME(unit, leaf_status_reg); 5417 5418 /* do ser correction */ 5419 sal_memset(&spci, 0, sizeof(spci)); 5420 spci.flags = (SOC_SER_SRC_MEM | SOC_SER_REG_MEM_KNOWN); 5421 spci.reg = INVALIDr; 5422 spci.mem = info->mem; 5423 5424 /* found block type for mem */ 5425 blk_idx = 0; 5426 SOC_MEM_BLOCK_ITER(unit, spci.mem, blk_idx) { 5427 if (SOC_MEM_BLOCK_VALID(unit, spci.mem, blk_idx)) { 5428 break; 5429 } 5430 } 5431 spci.blk_type = SOC_BLOCK_INFO(unit, blk_idx).type ; 5432 5433 SOC_BLOCK_ITER(unit, blk_idx, spci.blk_type) { 5434 sblk = SOC_BLOCK2SCH(unit, blk_idx); 5435 break; 5436 } 5437 spci.sblk = sblk; 5438 5439 spci.detect_time = sal_time_usecs(); 5440 spci.acc_type = SOC_MEM_ACC_TYPE(unit, spci.mem); 5441 5442 5443 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, info->mem_ecc_address_reg , port, 0, &rval)); 5444 spci.index = soc_reg_field_get(unit, info->mem_ecc_address_reg, rval, info->mem_ecc_address_field); 5445 5446 min_addr = SOC_MEM_INFO(unit, spci.mem).base + SOC_MEM_INFO(unit, spci.mem).index_min; 5447 spci.addr = min_addr + spci.index; 5448 5449 /* report ser event */ 5450 soc_saber2_mem_parity_info(unit, blk_idx, 0, 5451 info->status_field, &minfo); 5452 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 5453 SOC_SWITCH_EVENT_DATA_ERROR_UNCORRECTABLE, 5454 0, minfo); 5455 5456 LOG_ERROR(BSL_LS_SOC_COMMON, 5457 (BSL_META_U(unit, 5458 "mem:%s address 0x:%x index:%d has MMU parity error,correction type 0x:%x \n"), 5459 SOC_MEM_NAME(unit, spci.mem), 5460 spci.addr, spci.index, 5461 SOC_MEM_SER_CORRECTION_TYPE(unit, spci.mem))); 5462 5463 rv = soc_ser_correction(unit, &spci); 5464 5465 LOG_ERROR(BSL_LS_SOC_COMMON, 5466 (BSL_META_U(unit, 5467 "%s MMU subblock:%d parity err is detected by reg:%s.field:%s(value0x:%x), corrected result %d\n"), 5468 prefix_str, sub_block_type, reg_str, 5469 field_str, stat_rval, rv)); 5470 5471 /* clear the parity error bit */ 5472 SOC_IF_ERROR_RETURN 5473 (soc_reg32_set(unit, leaf_status_reg, port, 0, intr_bit)); 5474 } 5475 } 5476 return SOC_E_NONE; 5477 } 5478 5479 5480 5481 STATIC 5482 int soc_saber2_process_sb_one_level_mmu_parity_error(int unit, 5483 _soc_saber2_mmu_sub_block_one_level_t * sub_block_info) 5484 { 5485 soc_reg_t leaf_enable_reg; 5486 soc_reg_t leaf_status_reg; 5487 _soc_saber2_mmu_subblock_type_t sub_block_type; 5488 soc_block_t block = SOC_BLOCK_ANY; 5489 soc_port_t port = REG_PORT_ANY; 5490 _soc_saber2_mmu_sub_block_leaf_info_t * leaf_info; 5491 5492 if(sub_block_info->mmu_bit == 0) { 5493 /* reach the end of one level sub block table */ 5494 return SOC_E_NONE; 5495 } 5496 sub_block_type = sub_block_info->mmu_sub_block; 5497 5498 if ((sub_block_type == _SOC_SABER2_MMU_SUBBLOCK_CI1)|| 5499 (sub_block_type == _SOC_SABER2_MMU_SUBBLOCK_CI0)) { 5500 if (soc_feature(unit, soc_feature_ddr3)){ 5501 soc_saber2_ci_block_get (unit, sub_block_type, &block); 5502 port = SOC_BLOCK_PORT(unit, block); 5503 } else { 5504 return SOC_E_NONE; 5505 } 5506 } 5507 5508 leaf_enable_reg = sub_block_info->intr_mask_reg; 5509 leaf_status_reg = sub_block_info->lntr_status_reg; 5510 leaf_info = sub_block_info->info; 5511 5512 /* process this sub block */ 5513 SOC_IF_ERROR_RETURN 5514 (soc_saber2_process_sb_mmu_leaf_parity_error (unit, sub_block_type, 5515 port, leaf_enable_reg, leaf_status_reg, leaf_info)); 5516 5517 return SOC_E_NONE; 5518 } 5519 5520 5521 STATIC 5522 int soc_saber2_process_sb_two_level_mmu_parity_error(int unit, 5523 _soc_saber2_mmu_sub_block_two_level_t * sub_block_info) 5524 { 5525 uint32 en_rval; 5526 uint32 status_rval; 5527 soc_reg_t internal_status_reg; 5528 soc_reg_t internal_enable_reg; 5529 int internal_index; 5530 soc_port_t port = REG_PORT_ANY; 5531 _soc_saber2_mmu_subblock_type_t sub_block_type; 5532 _soc_saber2_mmu_sub_block_internal_info_t * internal_info; 5533 5534 if(sub_block_info->mmu_bit == 0) { 5535 /* reach the end of two level sub block table */ 5536 return SOC_E_NONE; 5537 } 5538 sub_block_type = sub_block_info->mmu_sub_block; 5539 5540 /* get status register of level 1 sub block */ 5541 internal_status_reg = sub_block_info->internal_status_reg; 5542 SOC_IF_ERROR_RETURN 5543 (soc_reg32_get(unit, internal_status_reg, REG_PORT_ANY, 0, 5544 &status_rval)); 5545 /* get mask register of level 1 sub block */ 5546 internal_enable_reg = sub_block_info->internal_enable_reg; 5547 if (internal_enable_reg != 0) { 5548 SOC_IF_ERROR_RETURN 5549 (soc_reg32_get(unit, internal_enable_reg, REG_PORT_ANY, 0, 5550 &en_rval)); 5551 /* remove masked */ 5552 status_rval &= (~en_rval); 5553 } 5554 5555 if (status_rval == 0) { 5556 /* How did this interrupt get asserted then??? */ 5557 return SOC_E_NONE; 5558 } 5559 5560 for (internal_index = 0; ; internal_index++) { 5561 internal_info = &sub_block_info->info[internal_index]; 5562 5563 if(internal_info->intr_bit == 0) { 5564 break; 5565 } 5566 if (status_rval & internal_info->intr_bit){ 5567 /* process this sub block */ 5568 SOC_IF_ERROR_RETURN 5569 (soc_saber2_process_sb_mmu_leaf_parity_error (unit, 5570 sub_block_type, port, internal_info->leaf_enable_reg, 5571 internal_info->leaf_status_reg, internal_info->info)); 5572 5573 /* clear the parity error bit */ 5574 SOC_IF_ERROR_RETURN 5575 (soc_reg32_set(unit, internal_status_reg, REG_PORT_ANY, 0, 5576 internal_info->intr_bit)); 5577 } 5578 } 5579 return SOC_E_NONE; 5580 } 5581 5582 5583 5584 STATIC int 5585 soc_saber2_parity_process_mmu(int unit, soc_reg_t mmu_en_reg, 5586 soc_reg_t mmu_stat_reg, char *prefix_str) 5587 { 5588 uint32 en_rval, stat_rval, mmu_bit; 5589 int index; 5590 uint32 sub_block_num = 0; 5591 _soc_saber2_mmu_sub_block_one_level_t * sub_block = NULL; 5592 _soc_saber2_mmu_sub_block_two_level_t * sub_block_2 = NULL; 5593 5594 /* get MMU INTR and MASK */ 5595 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, mmu_en_reg, REG_PORT_ANY, 0, &en_rval)); 5596 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, mmu_stat_reg, REG_PORT_ANY, 0, &stat_rval)); 5597 5598 /* remove masked */ 5599 stat_rval &= (~en_rval); 5600 if (stat_rval == 0) { 5601 /* How did this interrupt get asserted then??? */ 5602 return SOC_E_NONE; 5603 } 5604 5605 #ifdef BCM_METROLITE_SUPPORT 5606 if (SOC_IS_METROLITE(unit)) { 5607 sub_block_num = COUNTOF(_soc_metrolite_mmu_sub_blocks_type_1); 5608 sub_block = &_soc_metrolite_mmu_sub_blocks_type_1[0]; 5609 } else 5610 #endif 5611 { 5612 sub_block_num = COUNTOF(_soc_saber2_mmu_sub_blocks_type_1); 5613 sub_block = &_soc_saber2_mmu_sub_blocks_type_1[0]; 5614 } 5615 for (index = 0; index < sub_block_num; index++, sub_block++) { 5616 /* coverity[overrun-local:FALSE] */ 5617 if(sub_block->mmu_bit == 0) { 5618 /* End of table */ 5619 break; 5620 } 5621 mmu_bit = sub_block->mmu_bit; 5622 5623 if ((sub_block->mmu_bit & (stat_rval)) == 0) { 5624 /* No interrupts in this sub-block */ 5625 continue; 5626 } 5627 5628 soc_saber2_process_sb_one_level_mmu_parity_error(unit, sub_block); 5629 5630 /* clear the MMU parity error bit */ 5631 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, mmu_stat_reg, REG_PORT_ANY, 0, mmu_bit)); 5632 } 5633 5634 #ifdef BCM_METROLITE_SUPPORT 5635 if (SOC_IS_METROLITE(unit)) { 5636 sub_block_num = COUNTOF(_soc_metrolite_mmu_sub_blocks_type_2); 5637 sub_block_2 = &_soc_metrolite_mmu_sub_blocks_type_2[0]; 5638 }else 5639 #endif 5640 { 5641 sub_block_num = COUNTOF(_soc_saber2_mmu_sub_blocks_type_2); 5642 sub_block_2 = &_soc_saber2_mmu_sub_blocks_type_2[0]; 5643 } 5644 for (index = 0; index < sub_block_num; index++, sub_block_2++) { 5645 /* coverity[overrun-local:FALSE] */ 5646 if(sub_block_2->mmu_bit == 0) { 5647 /* End of table */ 5648 break; 5649 } 5650 mmu_bit = sub_block_2->mmu_bit; 5651 5652 if ((mmu_bit & (stat_rval)) == 0) { 5653 /* No interrupts in this sub-block */ 5654 continue; 5655 } 5656 5657 soc_saber2_process_sb_two_level_mmu_parity_error(unit, sub_block_2); 5658 /* clear the MMU parity error bit */ 5659 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, mmu_stat_reg, REG_PORT_ANY, 0, mmu_bit)); 5660 } 5661 5662 return SOC_E_NONE; 5663 } 5664 5665 5666 STATIC int 5667 soc_saber2_parity_ser_correction(int unit, const _soc_saber2_parity_info_t *info, 5668 char *prefix_str, char *mem_str_ptr, 5669 uint32 entry_idx, uint32 multiple, 5670 soc_block_t block_type) 5671 { 5672 int rv = SOC_E_NONE; 5673 _soc_ser_correct_info_t spci = {0}; 5674 5675 LOG_ERROR(BSL_LS_SOC_COMMON, 5676 (BSL_META_U(unit, 5677 "%s %s entry %d parity error\n"), prefix_str, 5678 mem_str_ptr, entry_idx)); 5679 if (multiple) { 5680 LOG_ERROR(BSL_LS_SOC_COMMON, 5681 (BSL_META_U(unit, 5682 "%s %s has multiple parity errors\n"), 5683 prefix_str, mem_str_ptr)); 5684 } 5685 if (info->mem != INVALIDm) { 5686 spci.flags = SOC_SER_SRC_MEM | SOC_SER_REG_MEM_KNOWN; 5687 spci.reg = INVALIDr; 5688 spci.mem = info->mem; 5689 spci.blk_type = block_type; 5690 spci.index = entry_idx; 5691 rv = soc_ser_correction(unit, &spci); 5692 } 5693 5694 return rv; 5695 } 5696 5697 5698 STATIC soc_error_t 5699 soc_saber2_parity_process_parity(int unit, soc_port_t port, 5700 const _soc_saber2_parity_info_t *info, 5701 int schan, char *prefix_str, char *mem_str, 5702 soc_block_t block_type, int block_idx) 5703 { 5704 _soc_saber2_parity_reg_t reg_entry[2], *reg_ptr; 5705 soc_reg_t reg; 5706 uint32 rval, minfo; 5707 uint32 multiple, entry_idx, idx, has_error; 5708 char *mem_str_ptr; 5709 int rv = SOC_E_NONE; 5710 5711 if (schan) { 5712 /* Some table does not have NACK register */ 5713 if (info->nack_status_reg == INVALIDr && 5714 info->nack_status_reg_list == NULL) { 5715 return rv; 5716 } 5717 reg_entry[0].reg = info->nack_status_reg; 5718 reg_entry[0].mem_str = NULL; 5719 reg_entry[1].reg = INVALIDr; 5720 reg_ptr = reg_entry; 5721 } else { 5722 if (info->intr_status_reg != INVALIDr) { 5723 reg_entry[0].reg = info->intr_status_reg; 5724 reg_entry[0].mem_str = NULL; 5725 reg_entry[1].reg = INVALIDr; 5726 reg_ptr = reg_entry; 5727 } else if (info->intr_status_reg_list != NULL) { 5728 reg_ptr = info->intr_status_reg_list; 5729 } else { 5730 return rv; 5731 } 5732 } 5733 5734 has_error = FALSE; 5735 for (idx = 0; reg_ptr[idx].reg != INVALIDr; idx++) { 5736 reg = reg_ptr[idx].reg; 5737 mem_str_ptr = reg_ptr[idx].mem_str != NULL ? 5738 reg_ptr[idx].mem_str : mem_str; 5739 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, reg, port, 0, &rval)); 5740 5741 if (soc_reg_field_valid(unit, reg, PARITY_ERRf)) { 5742 if (soc_reg_field_get(unit, reg, rval, PARITY_ERRf)) { 5743 has_error = TRUE; 5744 multiple = soc_reg_field_get(unit, reg, rval, MULTIPLE_ERRf); 5745 if (soc_reg_field_valid(unit, reg, ADDRESSf)) { 5746 entry_idx = soc_reg_field_get(unit, reg, rval, ADDRESSf); 5747 } else { 5748 entry_idx = soc_reg_field_get(unit, reg, rval, ENTRY_IDXf); 5749 } 5750 /* Convert physical index to logical index */ 5751 entry_idx = soc_saber2_mem_index_remap(unit, info->mem, entry_idx); 5752 5753 soc_saber2_mem_parity_info(unit, block_idx, 0, 5754 info->group_reg_status_field, &minfo); 5755 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 5756 SOC_SWITCH_EVENT_DATA_ERROR_PARITY, 5757 entry_idx, minfo); 5758 rv = soc_saber2_parity_ser_correction(unit, info, prefix_str, 5759 mem_str_ptr, entry_idx, 5760 multiple, block_type); 5761 if (SOC_FAILURE(rv)) { 5762 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 5763 SOC_SWITCH_EVENT_DATA_ERROR_FAILEDTOCORRECT, 5764 entry_idx, minfo); 5765 } 5766 /* Clear parity status */ 5767 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, reg, port, 0, 0)); 5768 } 5769 } else if (soc_reg_field_valid(unit, reg, PARITY_ERR_Af)) { 5770 /* For registers RX_PROT_GROUP_TABLE_DMA_PARITY_STATUS_INTR/NACK 5771 they have fileds PARITY_ERR_A and PARITY_ERR_B */ 5772 if (soc_reg_field_get(unit, reg, rval, PARITY_ERR_Af)) { 5773 has_error = TRUE; 5774 multiple = soc_reg_field_get(unit, reg, rval, MULTIPLE_ERR_Af); 5775 entry_idx = soc_reg_field_get(unit, reg, rval, ENTRY_IDX_Af); 5776 soc_saber2_mem_parity_info(unit, block_idx, 0, 5777 info->group_reg_status_field, &minfo); 5778 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 5779 SOC_SWITCH_EVENT_DATA_ERROR_PARITY, 5780 entry_idx, minfo); 5781 rv = soc_saber2_parity_ser_correction(unit, info, prefix_str, 5782 mem_str_ptr, entry_idx, 5783 multiple, block_type); 5784 if (SOC_FAILURE(rv)) { 5785 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 5786 SOC_SWITCH_EVENT_DATA_ERROR_FAILEDTOCORRECT, 5787 entry_idx, minfo); 5788 } 5789 } 5790 if (soc_reg_field_get(unit, reg, rval, PARITY_ERR_Bf)) { 5791 has_error = TRUE; 5792 multiple = soc_reg_field_get(unit, reg, rval, MULTIPLE_ERR_Bf); 5793 entry_idx = soc_reg_field_get(unit, reg, rval, ENTRY_IDX_Bf); 5794 soc_saber2_mem_parity_info(unit, block_idx, 0, 5795 info->group_reg_status_field, &minfo); 5796 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 5797 SOC_SWITCH_EVENT_DATA_ERROR_PARITY, 5798 entry_idx, minfo); 5799 rv = soc_saber2_parity_ser_correction(unit, info, prefix_str, 5800 mem_str_ptr, entry_idx, 5801 multiple, block_type); 5802 if (SOC_FAILURE(rv)) { 5803 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 5804 SOC_SWITCH_EVENT_DATA_ERROR_FAILEDTOCORRECT, 5805 entry_idx, minfo); 5806 } 5807 } 5808 if (has_error == TRUE) { 5809 /* Clear parity status */ 5810 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, reg, port, 0, 0)); 5811 } 5812 } else { 5813 return rv; 5814 } 5815 } 5816 5817 if (!has_error) { 5818 LOG_VERBOSE(BSL_LS_SOC_COMMON, 5819 (BSL_META_U(unit, 5820 "%s %s parity hardware inconsistency\n"), 5821 prefix_str, mem_str)); 5822 } 5823 5824 return rv; 5825 } /*_soc_katana_parity_process_parity*/ 5826 5827 5828 STATIC soc_error_t 5829 soc_saber2_parity_process_ecc(int unit, soc_port_t port, 5830 const _soc_saber2_parity_info_t *info, 5831 int schan, char *prefix_str, char *mem_str, 5832 soc_block_t block_type, int block_idx) 5833 { 5834 int rv = SOC_E_NONE; 5835 _soc_saber2_parity_reg_t reg_entry[2], *reg_ptr; 5836 soc_reg_t reg; 5837 uint32 rval, minfo; 5838 uint32 multiple = 0; 5839 uint32 double_bit = 0; 5840 uint32 entry_idx = 0; 5841 uint32 idx, has_error; 5842 char *mem_str_ptr; 5843 _soc_ser_correct_info_t spci = {0}; 5844 5845 if (schan) { 5846 /* Some table does not have NACK register */ 5847 if (info->nack_status_reg == INVALIDr && 5848 info->nack_status_reg_list == NULL) { 5849 return rv; 5850 } 5851 reg_entry[0].reg = info->nack_status_reg; 5852 reg_entry[0].mem_str = NULL; 5853 reg_entry[1].reg = INVALIDr; 5854 reg_ptr = reg_entry; 5855 } else { 5856 if (info->intr_status_reg != INVALIDr) { 5857 reg_entry[0].reg = info->intr_status_reg; 5858 reg_entry[0].mem_str = NULL; 5859 reg_entry[1].reg = INVALIDr; 5860 reg_ptr = reg_entry; 5861 } else if (info->intr_status_reg_list != NULL) { 5862 reg_ptr = info->intr_status_reg_list; 5863 } else { 5864 return rv; 5865 } 5866 } 5867 5868 has_error = FALSE; 5869 for (idx = 0; reg_ptr[idx].reg != INVALIDr; idx++) { 5870 reg = reg_ptr[idx].reg; 5871 mem_str_ptr = reg_ptr[idx].mem_str != NULL ? 5872 reg_ptr[idx].mem_str : mem_str; 5873 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, reg, port, 0, &rval)); 5874 5875 if (soc_reg_field_get(unit, reg, rval, ECC_ERRf)) { 5876 has_error = TRUE; 5877 if (SOC_REG_FIELD_VALID(unit, reg, MULTIPLE_ERRf)) { 5878 multiple = soc_reg_field_get(unit, reg, rval, MULTIPLE_ERRf); 5879 } else if (SOC_REG_FIELD_VALID(unit, reg, ECC_ERR_MULTIf)) { 5880 multiple = soc_reg_field_get(unit, reg, rval, ECC_ERR_MULTIf); 5881 } 5882 if (SOC_REG_FIELD_VALID(unit, reg, DOUBLE_BIT_ERRf)) { 5883 double_bit = soc_reg_field_get(unit, reg, rval, DOUBLE_BIT_ERRf); 5884 } else if (SOC_REG_FIELD_VALID(unit, reg, ECC_ERR_2Bf)) { 5885 double_bit = soc_reg_field_get(unit, reg, rval, ECC_ERR_2Bf); 5886 } 5887 if (SOC_REG_FIELD_VALID(unit, reg, ENTRY_IDXf)) { 5888 entry_idx = soc_reg_field_get(unit, reg, rval, ENTRY_IDXf); 5889 } 5890 if (double_bit) { 5891 LOG_ERROR(BSL_LS_SOC_COMMON, 5892 (BSL_META_U(unit, 5893 "%s %s entry %d double-bit ECC error\n"), 5894 prefix_str, mem_str_ptr, entry_idx)); 5895 spci.double_bit = 1; 5896 } else if (multiple) { 5897 LOG_ERROR(BSL_LS_SOC_COMMON, 5898 (BSL_META_U(unit, 5899 "%s %s has multiple ECC errors\n"), 5900 prefix_str, mem_str_ptr)); 5901 } else { 5902 LOG_ERROR(BSL_LS_SOC_COMMON, 5903 (BSL_META_U(unit, 5904 "%s %s entry %d ECC error\n"), 5905 prefix_str, mem_str_ptr, entry_idx)); 5906 } 5907 soc_saber2_mem_parity_info(unit, block_idx, 0, 5908 info->group_reg_status_field, &minfo); 5909 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 5910 SOC_SWITCH_EVENT_DATA_ERROR_ECC, 5911 entry_idx, minfo); 5912 if (info->mem != INVALIDm) { 5913 spci.flags = SOC_SER_SRC_MEM | SOC_SER_REG_MEM_KNOWN; 5914 spci.reg = INVALIDr; 5915 spci.mem = info->mem; 5916 spci.blk_type = block_type; 5917 spci.index = entry_idx; 5918 spci.parity_type = SOC_PARITY_TYPE_ECC; 5919 rv = soc_ser_correction(unit, &spci); 5920 if (SOC_FAILURE(rv)) { 5921 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 5922 SOC_SWITCH_EVENT_DATA_ERROR_FAILEDTOCORRECT, 5923 entry_idx, minfo); 5924 } 5925 } 5926 /* Clear parity status */ 5927 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, reg, port, 0, 0)); 5928 } 5929 5930 } 5931 5932 if (!has_error) { 5933 LOG_ERROR(BSL_LS_SOC_COMMON, 5934 (BSL_META_U(unit, 5935 "%s %s ECC hardware inconsistency\n"), 5936 prefix_str, mem_str)); 5937 } 5938 5939 return rv; 5940 } 5941 5942 5943 STATIC int 5944 soc_saber2_parity_process_info(int unit, soc_port_t port, 5945 soc_reg_t group_reg, 5946 uint32 group_rval, 5947 const _soc_saber2_parity_info_t *info_list, 5948 char *prefix_str, 5949 soc_block_t block_type, 5950 int block_idx) 5951 { 5952 const _soc_saber2_parity_info_t *info; 5953 int info_index; 5954 char *mem_str; 5955 5956 /* Loop through each info entry in the list */ 5957 for (info_index = 0; ; info_index++) { 5958 info = &info_list[info_index]; 5959 if (info->type == _SOC_PARITY_TYPE_NONE) { 5960 /* End of table */ 5961 break; 5962 } 5963 5964 /* This function is used for txlp/rxlp/xport parity error processing. 5965 * These blocks' memories all cannot be accessed by SW.In the parity_info 5966 * array, they are set as 'INVALIDm". If use SOC_MEM_IS_VALID() to check, 5967 * it will skip to clear all memories related interrupt status registers. 5968 */ 5969 5970 /* Check status for the info entry in the group register */ 5971 if (!soc_reg_field_get(unit, group_reg, group_rval, 5972 info->group_reg_status_field)) { 5973 continue; 5974 } 5975 5976 if (info->mem_str) { 5977 mem_str = info->mem_str; 5978 } else if (info->mem != INVALIDm) { 5979 mem_str = SOC_MEM_NAME(unit, info->mem); 5980 } else { 5981 mem_str = SOC_FIELD_NAME(unit, info->group_reg_status_field); 5982 } 5983 5984 /* Handle different parity error reporting style */ 5985 switch (info->type) { 5986 case _SOC_PARITY_TYPE_GENERIC: 5987 LOG_ERROR(BSL_LS_SOC_COMMON, 5988 (BSL_META_U(unit, 5989 "%s %s asserted\n"), prefix_str, mem_str)); 5990 break; 5991 case _SOC_PARITY_TYPE_PARITY: 5992 /* PARITY_ERRf, MULTIPLE_ERRf, ENTRY_IDXf */ 5993 SOC_IF_ERROR_RETURN 5994 (soc_saber2_parity_process_parity(unit, port, info, FALSE, 5995 prefix_str, mem_str, 5996 block_type, block_idx)); 5997 break; 5998 case _SOC_PARITY_TYPE_ECC: 5999 /* ECC_ERRf, MULTIPLE_ERRf, DOUBLE_BIT_ERRf, ENTRY_IDXf */ 6000 SOC_IF_ERROR_RETURN 6001 (soc_saber2_parity_process_ecc(unit, port, info, FALSE, 6002 prefix_str, mem_str, 6003 block_type, block_idx)); 6004 break; 6005 default: 6006 break; 6007 } /* Handle different parity error reporting style */ 6008 } /* Loop through each info entry in the list */ 6009 6010 return SOC_E_NONE; 6011 } 6012 6013 6014 6015 STATIC int 6016 soc_saber2_parity_process_err(int unit, uint32 route_block_index) 6017 { 6018 const _soc_saber2_parity_route_block_t *route_block = NULL; 6019 int block_idx = 0; 6020 soc_port_t port; 6021 soc_reg_t route_block_en_reg, route_block_status_reg; 6022 uint32 route_block_rval; 6023 uint32 route_block_enable; 6024 char prefix_str[10]; 6025 6026 port = REG_PORT_ANY; 6027 6028 #ifdef BCM_METROLITE_SUPPORT 6029 if (SOC_IS_METROLITE(unit)) { 6030 route_block = &_soc_metrolite_parity_intr_route_blocks[route_block_index]; 6031 } else 6032 #endif 6033 { 6034 route_block = &_soc_saber2_parity_intr_route_blocks[route_block_index]; 6035 } 6036 6037 /* get block and port for MXQ and RXLP and TXLP */ 6038 if ((route_block->blocktype == SOC_BLK_MXQPORT) || 6039 (route_block->blocktype == SOC_BLK_TXLP) || 6040 (route_block->blocktype == SOC_BLK_RXLP)) { 6041 SOC_BLOCK_ITER(unit, block_idx, route_block->blocktype) { 6042 if (SOC_BLOCK_INFO(unit, block_idx).number == route_block->id) { 6043 port = SOC_BLOCK_PORT(unit, block_idx); 6044 break; 6045 } 6046 } 6047 } else { 6048 SOC_BLOCK_ITER(unit, block_idx, route_block->blocktype) { 6049 if (SOC_BLOCK_INFO(unit, block_idx).number == route_block->id) { 6050 break; 6051 } 6052 } 6053 } 6054 6055 /* Read per route block parity status register */ 6056 route_block_status_reg = route_block->status_reg; 6057 route_block_en_reg = route_block->enable_reg; 6058 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, route_block_status_reg, port, 0, 6059 &route_block_rval)); 6060 if (route_block_rval == 0) { 6061 return SOC_E_NONE; 6062 } 6063 if (route_block->blocktype == SOC_BLK_MMU) { 6064 SOC_IF_ERROR_RETURN 6065 (soc_saber2_parity_process_mmu(unit, route_block_en_reg, 6066 route_block_status_reg, prefix_str)); 6067 } else { 6068 SOC_IF_ERROR_RETURN 6069 (soc_saber2_parity_process_info(unit, port, route_block_status_reg, 6070 route_block_rval, 6071 route_block->info, 6072 prefix_str, 6073 route_block->blocktype, 6074 block_idx)); 6075 6076 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, route_block_en_reg, port, 0, 6077 &route_block_enable)); 6078 route_block_enable &= ~route_block_rval; 6079 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, route_block_en_reg, port, 0, 6080 route_block_enable)); 6081 route_block_enable |= route_block_rval; 6082 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, route_block_en_reg, port, 0, 6083 route_block_enable)); 6084 } 6085 6086 return SOC_E_NONE; 6087 } 6088 extern void 6089 soc_kt2_oam_interrupt_process(int unit); 6090 6091 #define KT2_OAM_INTR_MASK 0xFF 6092 #define KT2_RXLP_INTR_MASK 0x7FFF 6093 6094 #include <soc/shared/sat.h> 6095 void soc_saber2_sat_interrupt_process(int unit) 6096 { 6097 soc_sat_handler_t handler = NULL; 6098 6099 soc_common_sat_handler_get(unit, &handler); 6100 6101 if (handler != NULL) { 6102 (void)(handler(unit)); 6103 } 6104 } 6105 6106 STATIC int 6107 soc_saber2_ser_process_all(int unit) 6108 { 6109 uint8 rbi; 6110 uint32 block_num = 0; 6111 uint32 cmic_rval, cmic_bit, rval = 0, fval; 6112 const _soc_saber2_parity_route_block_t *rb = NULL; 6113 char prefix_str[10]; 6114 soc_stat_t *stat = SOC_STAT(unit); 6115 bcm_port_t port = 0; 6116 soc_info_t *si = &SOC_INFO(unit); 6117 6118 sal_sprintf(prefix_str, "Unit: %d \n", unit); 6119 6120 /* Read CMIC parity status register */ 6121 SOC_IF_ERROR_RETURN 6122 (READ_CMIC_CMC0_IRQ_STAT3r(unit, &cmic_rval)); 6123 if (cmic_rval == 0) { 6124 return SOC_E_NONE; 6125 } 6126 6127 #ifdef BCM_METROLITE_SUPPORT 6128 if (SOC_IS_METROLITE(unit)) { 6129 rb = &_soc_metrolite_parity_intr_route_blocks[0]; 6130 block_num = COUNTOF(_soc_metrolite_parity_intr_route_blocks); 6131 } else 6132 #endif 6133 { 6134 rb = &_soc_saber2_parity_intr_route_blocks[0]; 6135 block_num = COUNTOF(_soc_saber2_parity_intr_route_blocks); 6136 } 6137 6138 /* Loop through each place-and-route block entry */ 6139 for (rbi = 0; rbi < block_num ; rbi++, rb++) { 6140 /* coverity[overrun-local:FALSE] */ 6141 cmic_bit = rb->cmic_bit; 6142 if (cmic_bit == 0) { 6143 /* End of table */ 6144 break; 6145 } 6146 if (!(cmic_rval & cmic_bit)) { 6147 /* No interrupt bit asserted for the route block */ 6148 continue; 6149 } 6150 if (rb->blocktype == SOC_BLK_IPIPE || rb->blocktype == SOC_BLK_EPIPE) { 6151 /* New fifo style processing */ 6152 (void)soc_saber2_process_ser_fifo(unit, rb->blocktype, prefix_str); 6153 stat->ser_err_fifo++; 6154 } else { 6155 /* Legacy processing */ 6156 soc_saber2_parity_process_err(unit, rbi); 6157 6158 stat->ser_err_int++; 6159 } 6160 } 6161 6162 6163 /* Handle LINK-PHY interrupt */ 6164 SOC_PBMP_ITER(si->linkphy_pbm, port) { 6165 if (SOC_REG_PORT_VALID(unit, RXLP_INTERRUPT_STATUSr, port)) { 6166 6167 if (READ_RXLP_INTERRUPT_STATUSr(unit, port, &rval)) { 6168 LOG_ERROR(BSL_LS_SOC_COMMON, 6169 (BSL_META_U(unit, 6170 "unit %d: Error reading %s reg !!\n"), 6171 unit, SOC_REG_NAME(unit, RXLP_INTERRUPT_STATUSr))); 6172 return SOC_E_INTERNAL; 6173 } 6174 if (rval & KT2_RXLP_INTR_MASK) { 6175 /* Call Linkphy interrupt handler */ 6176 soc_kt2_rxlp_interrupt_process(unit, port, rval); 6177 } 6178 } 6179 } 6180 6181 rval = 0; 6182 6183 /* Handle OAM interrupt */ 6184 if (READ_IP1_INTR_STATUS_1r(unit, &rval)) { 6185 LOG_ERROR(BSL_LS_SOC_COMMON, 6186 (BSL_META_U(unit, 6187 "unit %d: Error reading %s reg !!\n"), 6188 unit, SOC_REG_NAME(unit, IP1_INTR_STATUS_1r))); 6189 return SOC_E_INTERNAL; 6190 } 6191 if (rval & KT2_OAM_INTR_MASK) { 6192 /* Call OAM interrupt handler */ 6193 soc_kt2_oam_interrupt_process(unit); 6194 } 6195 6196 /* Handle SAT interrupt */ 6197 if (cmic_rval & _SOC_SABER2_SAT_CMIC_BIT) { 6198 SOC_IF_ERROR_RETURN(READ_OAMP_INTERRUPT_REGISTERr(unit, &rval)); 6199 fval = soc_reg_field_get(unit, OAMP_INTERRUPT_REGISTERr, rval, 6200 STAT_PENDING_EVENTf); 6201 if (fval) { 6202 soc_saber2_sat_interrupt_process(unit); 6203 } 6204 } 6205 6206 return SOC_E_NONE; 6207 } 6208 6209 6210 soc_ser_test_functions_t ser_saber2_test_fun; 6211 6212 soc_error_t 6213 soc_saber2_ser_error_injection_support (int unit, soc_mem_t mem, int pipe) 6214 { 6215 /* for check memory support "ser inject" or not */ 6216 int i,j; 6217 int rv = SOC_E_UNAVAIL; 6218 _soc_saber2_fifo_ser_info_t *fifo_parity; 6219 _soc_generic_ser_info_t *tcams = _soc_saber2_tcam_ser_info[unit]; 6220 _soc_saber2_mmu_sub_block_leaf_info_t leaf_info; 6221 6222 /* EP/IP */ 6223 for (i = 0; _soc_saber2_fifo_ser_block_info[i].blocktype != 0; i++) { 6224 fifo_parity = _soc_saber2_fifo_ser_block_info[i].info; 6225 for (j = 0; fifo_parity[j].enable_reg != INVALIDr;j++) { 6226 if (fifo_parity[j].mem != INVALIDm && fifo_parity[j].mem == mem) { 6227 return SOC_E_NONE; 6228 } 6229 } 6230 } 6231 6232 for (i = 0; _soc_saber2_ip_parity_info[i].type != _SOC_PARITY_TYPE_NONE; i++) { 6233 if (_soc_saber2_ip_parity_info[i].mem == mem && 6234 _soc_saber2_ip_parity_info[i].mem != INVALIDm) { 6235 return SOC_E_NONE; 6236 } 6237 } 6238 6239 for (i = 0; _soc_saber2_ep_parity_info[i].type != _SOC_PARITY_TYPE_NONE; i++) { 6240 if (_soc_saber2_ep_parity_info[i].mem == mem && 6241 _soc_saber2_ep_parity_info[i].mem != INVALIDm) { 6242 return SOC_E_NONE; 6243 } 6244 } 6245 6246 /* MMU*/ 6247 rv = soc_saber2_found_mem_in_mmu(unit, mem, &leaf_info); 6248 if (rv == SOC_E_NONE) { 6249 return SOC_E_NONE; 6250 } 6251 6252 /* Now xport, xlport, rxlp, txlp tables are INVAILDm */ 6253 6254 /* tcam */ 6255 for (i = 0; tcams[i].mem != INVALIDm; i++) { 6256 if (tcams[i].mem == mem) { 6257 return SOC_E_NONE; 6258 } 6259 } 6260 6261 return rv; 6262 } 6263 6264 STATIC 6265 soc_field_t soc_saber2_set_test_field(soc_mem_t memory, soc_field_t field) 6266 { 6267 soc_field_t test_field = field; 6268 6269 switch(memory) { 6270 /* TCAM fields*/ 6271 case CPU_COS_MAPm: 6272 case MY_STATION_TCAMm: 6273 case FP_UDF_TCAMm: 6274 case EFP_TCAMm: 6275 case VLAN_SUBNETm: 6276 case L2_USER_ENTRYm: 6277 case VFP_TCAMm: 6278 case L3_TUNNELm: 6279 case ING_SAT_SAMP_TCAMm: 6280 case EGR_SAT_SAMP_TCAMm: 6281 case SUBPORT_TAG_TO_PP_PORT_MAPm: 6282 test_field = MASKf; 6283 break; 6284 case FP_GLOBAL_MASK_TCAMm: 6285 test_field = FULL_MASKf; 6286 break; 6287 case FP_TCAMm: 6288 test_field = DATA_MASKf; 6289 break; 6290 case L3_DEFIPm: 6291 test_field = RESERVED_2f; 6292 break; 6293 default: 6294 break; 6295 } 6296 6297 return test_field; 6298 } 6299 6300 STATIC int 6301 soc_saber2_parity_block_port(int unit, soc_block_t block, soc_port_t *port) 6302 { 6303 *port = SOC_BLOCK_PORT(unit, block); 6304 if ((*port != REG_PORT_ANY) && !SOC_PORT_VALID(unit, *port)) { 6305 return SOC_E_PORT; 6306 } 6307 6308 return SOC_E_NONE; 6309 } 6310 6311 soc_error_t soc_saber2_ser_mmu_inject_error(int unit, 6312 uint32 flags, soc_mem_t mem, 6313 int block, int index) 6314 { 6315 _soc_saber2_mmu_sub_block_leaf_info_t leaf_info = {0}; 6316 uint32 tmp_entry[SOC_MAX_MEM_WORDS], fieldData[SOC_MAX_MEM_FIELD_WORDS]; 6317 ser_test_data_t test_data; 6318 6319 if((SOC_MEM_INFO(unit, mem).flags & SOC_MEM_FLAG_CACHABLE) == 0) { 6320 LOG_ERROR(BSL_LS_SOC_COMMON, 6321 (BSL_META_U(unit, 6322 "Uncached memory.\n"))); 6323 return SOC_E_PARAM; 6324 } 6325 6326 if (SOC_E_NONE != soc_saber2_found_mem_in_mmu(unit, mem, &leaf_info)) { 6327 LOG_ERROR(BSL_LS_SOC_COMMON, 6328 (BSL_META_U(unit, 6329 "%s is not support in Saber2.\n"), 6330 SOC_MEM_NAME(unit,mem))); 6331 6332 return SOC_E_PARAM; 6333 } 6334 6335 soc_ser_create_test_data(unit, tmp_entry, fieldData, 6336 leaf_info.mem_parity_enable_reg, 6337 SOC_INVALID_TCAM_PARITY_BIT, 6338 leaf_info.mem_parity_enable_field, 6339 mem, leaf_info.mem_parity_field, 6340 MEM_BLOCK_ANY, 6341 REG_PORT_ANY, 6342 _SOC_ACC_TYPE_PIPE_ANY, index, 6343 &test_data); 6344 6345 if (soc_mem_field_length(unit, mem, 6346 leaf_info.mem_parity_field) >= 2 ) { 6347 flags |= SOC_INJECT_ERROR_2BIT_ECC; 6348 } 6349 6350 /*Read the memory for successful injection*/ 6351 SOC_IF_ERROR_RETURN(ser_test_mem_read(unit, 0, &test_data)); 6352 /*Disable parity*/ 6353 SOC_IF_ERROR_RETURN(_ser_test_parity_control(unit, &test_data, 0)); 6354 /*Inject error*/ 6355 SOC_IF_ERROR_RETURN(soc_ser_test_inject_full(unit, flags, &test_data)); 6356 /*Enable parity*/ 6357 SOC_IF_ERROR_RETURN(_ser_test_parity_control(unit, &test_data, 1)); 6358 6359 return SOC_E_NONE; 6360 6361 } 6362 6363 soc_error_t 6364 soc_saber2_ser_inject_error (int unit, uint32 flags, soc_mem_t mem, 6365 int pipe_target, int block, int index) 6366 { 6367 /* for ser inject */ 6368 int group, table, i,j; 6369 _soc_saber2_parity_info_t *info = NULL; 6370 soc_mem_t memTable; 6371 soc_port_t block_port = 0; 6372 soc_block_t blk; 6373 ser_test_data_t test_data; 6374 soc_field_t field; 6375 uint32 tmp_entry[SOC_MAX_MEM_WORDS], fieldData[SOC_MAX_MEM_FIELD_WORDS]; 6376 const _soc_saber2_parity_route_block_t *parity_intr_route_block = NULL; 6377 sal_memset(&test_data, 0, sizeof(test_data)); 6378 6379 #ifdef BCM_METROLITE_SUPPORT 6380 if (SOC_IS_METROLITE(unit)) { 6381 parity_intr_route_block = &_soc_metrolite_parity_intr_route_blocks[0]; 6382 } else 6383 #endif 6384 { 6385 parity_intr_route_block = &_soc_saber2_parity_intr_route_blocks[0]; 6386 } 6387 6388 /* some mem/regs have been deleted in 56270 */ 6389 if (!SOC_MEM_IS_VALID(unit,mem)) { 6390 return SOC_E_FAIL; 6391 } 6392 6393 /* Check if memory needs to be skipped */ 6394 if (NULL != ser_saber2_test_fun.injection_support) { 6395 SOC_IF_ERROR_RETURN( 6396 (ser_saber2_test_fun.injection_support)(unit, mem, pipe_target)); 6397 } 6398 6399 field = soc_saber2_set_test_field(mem, INVALIDf); 6400 6401 /*TCAM ser inject*/ 6402 if (_soc_saber2_tcam_ser_info[unit] != NULL) { 6403 for (i = 0; _soc_saber2_tcam_ser_info[unit][i].mem != INVALIDm; i++) { 6404 if (_soc_saber2_tcam_ser_info[unit][i].mem == mem) { 6405 soc_ser_create_test_data(unit, tmp_entry, fieldData, 6406 SER_RANGE_ENABLEr, i, VALIDf, mem, 6407 field, MEM_BLOCK_ANY, REG_PORT_ANY, 6408 _SOC_ACC_TYPE_PIPE_ANY, index, &test_data); 6409 6410 /*Read the memory for successful injection*/ 6411 SOC_IF_ERROR_RETURN(ser_test_mem_read(unit, 0, &test_data)); 6412 /*Disable parity*/ 6413 SOC_IF_ERROR_RETURN(_ser_test_parity_control(unit, &test_data, 0)); 6414 /*Inject error*/ 6415 SOC_IF_ERROR_RETURN(soc_ser_test_inject_full(unit, flags, &test_data)); 6416 /*Enable parity*/ 6417 SOC_IF_ERROR_RETURN(_ser_test_parity_control(unit, &test_data, 1)); 6418 return SOC_E_NONE; 6419 } 6420 } 6421 } 6422 6423 6424 /*IP/EP ser inject*/ 6425 for (i = 0; _soc_saber2_fifo_ser_block_info[i].blocktype != 0; i++) { 6426 for (j = 0; _soc_saber2_fifo_ser_block_info[i].info[j].enable_reg != INVALIDr; j++) { 6427 6428 /* Some mem/regs have been removed or without ecc/parity fields in 56270. */ 6429 if ((!soc_reg_field_valid(unit, 6430 _soc_saber2_fifo_ser_block_info[i].info[j].enable_reg, 6431 _soc_saber2_fifo_ser_block_info[i].info[j].enable_field)) || 6432 (!soc_mem_field_valid(unit, mem, 6433 _soc_saber2_fifo_ser_block_info[i].info[j].parity_field))) { 6434 continue; 6435 } 6436 6437 if (_soc_saber2_fifo_ser_block_info[i].info[j].mem == mem) { 6438 soc_ser_create_test_data(unit, tmp_entry, fieldData, 6439 _soc_saber2_fifo_ser_block_info[i].info[j].enable_reg, 6440 SOC_INVALID_TCAM_PARITY_BIT, 6441 _soc_saber2_fifo_ser_block_info[i].info[j].enable_field, 6442 mem, 6443 _soc_saber2_fifo_ser_block_info[i].info[j].parity_field, 6444 block, REG_PORT_ANY, _SOC_ACC_TYPE_PIPE_ANY, 6445 index, &test_data); 6446 6447 if (soc_mem_field_length(unit, mem, 6448 _soc_saber2_fifo_ser_block_info[i].info[j].parity_field) >= 2 ) { 6449 flags |= SOC_INJECT_ERROR_2BIT_ECC; 6450 } 6451 6452 /*Read the memory for successful injection*/ 6453 SOC_IF_ERROR_RETURN(ser_test_mem_read(unit, 0, &test_data)); 6454 /*Disable parity*/ 6455 SOC_IF_ERROR_RETURN(_ser_test_parity_control(unit, &test_data, 0)); 6456 /*Inject error*/ 6457 SOC_IF_ERROR_RETURN(soc_ser_test_inject_full(unit, flags, &test_data)); 6458 /*Enable parity*/ 6459 SOC_IF_ERROR_RETURN(_ser_test_parity_control(unit, &test_data, 1)); 6460 6461 return SOC_E_NONE; 6462 } 6463 } 6464 } 6465 6466 6467 /*H/W memory ser inject. */ 6468 for (group = 0; parity_intr_route_block[group].cmic_bit; group++) { 6469 if(parity_intr_route_block[group].info == NULL) { 6470 continue; 6471 } 6472 info = parity_intr_route_block[group].info; 6473 6474 if (parity_intr_route_block[group].blocktype == SOC_BLK_MMU) { 6475 continue; 6476 } else { 6477 SOC_BLOCK_ITER(unit, blk,parity_intr_route_block[group].blocktype) { 6478 if (soc_saber2_parity_block_port(unit, blk, &block_port) < 0) { 6479 continue; 6480 } 6481 for (table = 0; info[table].type != _SOC_PARITY_TYPE_NONE; table++) { 6482 memTable = info[table].mem; 6483 if ((memTable == INVALIDm) || 6484 (!soc_reg_field_valid(unit, 6485 info[table].enable_reg, 6486 info[table].enable_field))) { 6487 continue; 6488 } 6489 if (memTable == mem) { 6490 if((blk == block) || (block == MEM_BLOCK_ANY)) { 6491 /*Inject error*/ 6492 soc_ser_create_test_data(unit, tmp_entry, fieldData, 6493 info[table].enable_reg, 6494 SOC_INVALID_TCAM_PARITY_BIT, 6495 info[table].enable_field, 6496 mem, field, blk, 6497 block_port, 6498 _SOC_ACC_TYPE_PIPE_ANY, index, 6499 &test_data); 6500 /*Read the memory for successful injection*/ 6501 SOC_IF_ERROR_RETURN(ser_test_mem_read(unit, 0, &test_data)); 6502 /*Disable parity*/ 6503 SOC_IF_ERROR_RETURN(_ser_test_parity_control(unit, &test_data, 0)); 6504 /*Inject error*/ 6505 SOC_IF_ERROR_RETURN(soc_ser_test_inject_full(unit, flags, &test_data)); 6506 /*Enable parity*/ 6507 SOC_IF_ERROR_RETURN(_ser_test_parity_control(unit, &test_data, 1)); 6508 6509 return SOC_E_NONE; 6510 } 6511 } 6512 } 6513 } 6514 } 6515 } 6516 6517 /* MMU */ 6518 SOC_IF_ERROR_RETURN(soc_saber2_ser_mmu_inject_error(unit, flags, mem, block, index)); 6519 6520 return SOC_E_NONE; 6521 } 6522 6523 soc_error_t soc_saber2_ser_mmu_test_mem(int unit, 6524 soc_mem_t mem, _soc_ser_test_t test_type, 6525 int * pTestErrors) 6526 { 6527 int rv = SOC_E_NONE; 6528 _soc_saber2_mmu_sub_block_leaf_info_t leaf_info = {0}; 6529 uint32 tmp_entry[SOC_MAX_MEM_WORDS], fieldData[SOC_MAX_MEM_FIELD_WORDS]; 6530 ser_test_data_t test_data; 6531 6532 if((SOC_MEM_INFO(unit, mem).flags & SOC_MEM_FLAG_CACHABLE) == 0) { 6533 LOG_ERROR(BSL_LS_SOC_COMMON, 6534 (BSL_META_U(unit, 6535 "Uncached memory.\n"))); 6536 return SOC_E_PARAM; 6537 } 6538 6539 soc_saber2_found_mem_in_mmu(unit, mem, &leaf_info); 6540 6541 soc_ser_create_test_data(unit, tmp_entry, fieldData, 6542 leaf_info.mem_parity_enable_reg, 6543 SOC_INVALID_TCAM_PARITY_BIT, 6544 leaf_info.mem_parity_enable_field, 6545 mem, leaf_info.mem_parity_field, 6546 MEM_BLOCK_ANY, 6547 REG_PORT_ANY, 6548 _SOC_ACC_TYPE_PIPE_ANY, 0, 6549 &test_data); 6550 6551 rv = ser_test_mem(unit, 0, &test_data, test_type, 6552 pTestErrors); 6553 6554 if (rv != SOC_E_NONE) { 6555 LOG_CLI((BSL_META_U(unit, 6556 "Error during H/W test. Aborting.\n"))); 6557 } 6558 6559 return rv; 6560 6561 } 6562 6563 int soc_saber2_ser_test_mem(int unit, soc_mem_t mem, 6564 _soc_ser_test_t test_type, int cmd) 6565 { 6566 int group, table, i, j, rv; 6567 _soc_saber2_parity_info_t *info; 6568 soc_mem_t memTable; 6569 soc_field_t field; 6570 soc_port_t block_port=0; 6571 soc_block_t blk; 6572 int testErrors = 0; 6573 ser_test_data_t test_data; 6574 uint32 tmp_entry[SOC_MAX_MEM_WORDS], field_data[SOC_MAX_MEM_FIELD_WORDS]; 6575 const _soc_saber2_parity_route_block_t *parity_intr_route_block = NULL; 6576 6577 #ifdef BCM_METROLITE_SUPPORT 6578 if (SOC_IS_METROLITE(unit)) { 6579 parity_intr_route_block = &_soc_metrolite_parity_intr_route_blocks[0]; 6580 } else 6581 #endif 6582 { 6583 parity_intr_route_block = &_soc_saber2_parity_intr_route_blocks[0]; 6584 } 6585 6586 /*Prevent compiler error for common function signature.*/ 6587 (void) cmd; 6588 sal_memset(&test_data, 0, sizeof(test_data)); 6589 6590 field = soc_saber2_set_test_field(mem, INVALIDf); 6591 6592 /*TCAM_test*/ 6593 if (_soc_saber2_tcam_ser_info[unit] != NULL) { 6594 for (i = 0; _soc_saber2_tcam_ser_info[unit][i].mem != INVALIDm; i++) { 6595 if (_soc_saber2_tcam_ser_info[unit][i].mem == mem) { 6596 soc_ser_create_test_data(unit, tmp_entry, field_data, 6597 SER_RANGE_ENABLEr, i, INVALIDf, mem, 6598 VALIDf, MEM_BLOCK_ANY, REG_PORT_ANY, 6599 _SOC_ACC_TYPE_PIPE_ANY, 0, &test_data); 6600 rv = ser_test_mem(unit, 0, &test_data, test_type, &testErrors); 6601 6602 if (rv != SOC_E_NONE) { 6603 LOG_CLI((BSL_META_U(unit, 6604 "Error during TCAM test. Aborting.\n"))); 6605 return rv; 6606 } 6607 } 6608 } 6609 } 6610 6611 /*IP/EP mem test */ 6612 for (i = 0; _soc_saber2_fifo_ser_block_info[i].blocktype != 0; i++) { 6613 for (j = 0; _soc_saber2_fifo_ser_block_info[i].info->enable_reg != INVALIDr; j++) { 6614 if (_soc_saber2_fifo_ser_block_info[i].info->mem == mem) { 6615 soc_ser_create_test_data(unit, tmp_entry, field_data, 6616 SER_RANGE_ENABLEr, i, VALIDf, mem, 6617 field, MEM_BLOCK_ANY, REG_PORT_ANY, 6618 _SOC_ACC_TYPE_PIPE_ANY, 0, &test_data); 6619 rv = ser_test_mem(unit, 0, &test_data, test_type, &testErrors); 6620 6621 if (rv != SOC_E_NONE) { 6622 LOG_CLI((BSL_META_U(unit, 6623 "Error during TCAM test. Aborting.\n"))); 6624 return rv; 6625 } 6626 } 6627 } 6628 } 6629 6630 6631 6632 /*H/W memory Test. MMU not include */ 6633 for (group = 0; parity_intr_route_block[group].cmic_bit; group++) { 6634 info = parity_intr_route_block[group].info; 6635 6636 if (parity_intr_route_block[group].blocktype == SOC_BLK_MMU) { 6637 6638 rv = soc_saber2_ser_mmu_test_mem(unit, mem, test_type, &testErrors); 6639 if (rv != SOC_E_NONE) { 6640 LOG_CLI((BSL_META_U(unit, 6641 "Error during MMU test. Aborting.\n"))); 6642 return rv; 6643 } 6644 } else { 6645 SOC_BLOCK_ITER(unit, blk,parity_intr_route_block[group].blocktype) { 6646 if (soc_saber2_parity_block_port(unit, blk, &block_port) < 0) { 6647 continue; 6648 } 6649 6650 for (table = 0; info[table].type != _SOC_PARITY_TYPE_NONE; table++) { 6651 memTable = info[table].mem; 6652 if (memTable == INVALIDm) { 6653 continue; 6654 } 6655 if (memTable == mem) { 6656 soc_ser_create_test_data(unit, tmp_entry, field_data, 6657 info[table].enable_reg, 6658 SOC_INVALID_TCAM_PARITY_BIT, 6659 info[table].enable_field, 6660 mem, EVEN_PARITYf, blk, 6661 block_port, 6662 _SOC_ACC_TYPE_PIPE_ANY, 0, 6663 &test_data); 6664 rv = ser_test_mem(unit, 0, &test_data, test_type, 6665 &testErrors); 6666 if (rv != SOC_E_NONE) { 6667 LOG_CLI((BSL_META_U(unit, 6668 "Error during H/W test. Aborting.\n"))); 6669 return rv; 6670 } 6671 } 6672 } 6673 } 6674 } 6675 } 6676 if (testErrors == 0) { 6677 LOG_CLI((BSL_META_U(unit, 6678 "SER Test passed on unit: %d for memory %s\n "), 6679 unit, SOC_MEM_NAME(unit,mem))); 6680 } else { 6681 LOG_CLI((BSL_META_U(unit, 6682 "SER Test failed on unit: %d for memory %s\n"), 6683 unit, SOC_MEM_NAME(unit,mem))); 6684 return SOC_E_MEMORY; 6685 } 6686 return SOC_E_NONE; 6687 } 6688 6689 int 6690 soc_saber2_ser_tcam_test (int unit, _soc_ser_test_t test_type, int *pNumTCAMErr) 6691 { 6692 int i, rv; 6693 int numTCAMtest = 0; 6694 soc_field_t field; 6695 6696 int numTotalTcam = (sizeof(_soc_saber2_tcam_ser_info_template) / 6697 sizeof(_soc_saber2_tcam_ser_info_template[0])) - 1; 6698 6699 if (_soc_saber2_tcam_ser_info[unit] != NULL) { 6700 for (i = 0; _soc_saber2_tcam_ser_info[unit][i].mem != INVALIDm; i++) { 6701 field = soc_saber2_set_test_field(_soc_saber2_tcam_ser_info[unit][i].mem, INVALIDf); 6702 LOG_CLI((BSL_META_U(unit, 6703 "SER TCAM test begin: %s id:%d\n"), 6704 SOC_MEM_NAME(unit, _soc_saber2_tcam_ser_info[unit][i].mem), 6705 _soc_saber2_tcam_ser_info[unit][i].mem)); 6706 6707 rv = ser_test_mem_pipe(unit, SER_RANGE_ENABLEr, i, -1, 6708 _soc_saber2_tcam_ser_info[unit][i].mem, field, 6709 test_type, MEM_BLOCK_ANY, REG_PORT_ANY, -1, 6710 pNumTCAMErr); 6711 if (rv != SOC_E_NONE) { 6712 LOG_CLI((BSL_META_U(unit, 6713 "Error during TCAM:%s SER test.\n\n"), 6714 SOC_MEM_NAME(unit, _soc_saber2_tcam_ser_info[unit][i].mem))); 6715 }else { 6716 6717 LOG_CLI((BSL_META_U(unit, 6718 "TCAM:%s SER test passsed.\n\n"), 6719 SOC_MEM_NAME(unit, _soc_saber2_tcam_ser_info[unit][i].mem))); 6720 } 6721 numTCAMtest ++; 6722 } 6723 } 6724 6725 LOG_CLI((BSL_META_U(unit, 6726 "Total TCAM num:%d, failed num:%d \n\n"), 6727 numTotalTcam, *pNumTCAMErr)); 6728 6729 return numTCAMtest; 6730 6731 } 6732 6733 int 6734 soc_saber2_ser_mmu_test(int unit, _soc_ser_test_t test_type, int *pTestErrors) 6735 { 6736 int rv = 0; 6737 int test_count = 0; 6738 uint32 sub_block_num = 0; 6739 soc_mem_t mem; 6740 int block_index, sub_block_index, node_index; 6741 _soc_saber2_mmu_sub_block_one_level_t * sub_block = NULL; 6742 _soc_saber2_mmu_sub_block_two_level_t * sub_block_2 = NULL; 6743 _soc_saber2_mmu_sub_block_internal_info_t * sub_block_internal = NULL; 6744 _soc_saber2_mmu_sub_block_leaf_info_t * leaf_info = NULL; 6745 void *null_entry = NULL; 6746 6747 if(pTestErrors == NULL) { 6748 return 0; 6749 } 6750 6751 #ifdef BCM_METROLITE_SUPPORT 6752 if (SOC_IS_METROLITE(unit)) { 6753 sub_block_num = COUNTOF(_soc_metrolite_mmu_sub_blocks_type_1); 6754 sub_block = &_soc_metrolite_mmu_sub_blocks_type_1[0]; 6755 }else 6756 #endif 6757 { 6758 sub_block_num = COUNTOF(_soc_saber2_mmu_sub_blocks_type_1); 6759 sub_block = &_soc_saber2_mmu_sub_blocks_type_1[0]; 6760 } 6761 for (block_index = 0; block_index < sub_block_num; block_index++, sub_block++) { 6762 /* coverity[overrun-local:FALSE] */ 6763 leaf_info = sub_block->info; 6764 if ((leaf_info == NULL) || (sub_block->mmu_bit == 0)) { 6765 break; 6766 } 6767 for(node_index = 0; ; node_index ++) { 6768 if(leaf_info[node_index].intr_bit == 0) { 6769 break; 6770 } 6771 mem = leaf_info[node_index].mem; 6772 if(mem == INVALIDm) { 6773 continue; 6774 } 6775 if (!SOC_MEM_IS_VALID(unit, mem)) { 6776 LOG_CLI((BSL_META_U(unit, 6777 "%s is not a valid memory for this platform. Skipping.\n"), 6778 SOC_MEM_NAME(unit, mem))); 6779 continue; 6780 } 6781 /* now test 1 bit error */ 6782 if(soc_mem_field_length(unit, mem, leaf_info[node_index].mem_parity_field) > 1) { 6783 continue; 6784 } 6785 6786 if (SOC_MEM_SER_CORRECTION_TYPE(unit, mem)) { 6787 LOG_CLI((BSL_META_U(unit, 6788 "\nMMU SER test begin: %s id:%d mem flag:0x%x field:%s\n"), 6789 SOC_MEM_NAME(unit, mem), mem, 6790 SOC_MEM_SER_CORRECTION_TYPE(unit, mem), 6791 SOC_FIELD_NAME(unit, leaf_info[node_index].mem_parity_field))); 6792 6793 null_entry = soc_mem_entry_null(unit, mem); 6794 rv = soc_mem_write(unit, mem, MEM_BLOCK_ANY, 0, null_entry); 6795 6796 if (rv != SOC_E_NONE) { 6797 LOG_CLI((BSL_META_U(unit, 6798 "mem:%s id:%d clear entry failed.\n"), 6799 SOC_MEM_NAME(unit, mem), mem)); 6800 } 6801 6802 rv = ser_test_mem_pipe(unit, 6803 leaf_info[node_index].mem_parity_enable_reg, 6804 SOC_INVALID_TCAM_PARITY_BIT, 6805 leaf_info[node_index].mem_parity_enable_field, 6806 mem, 6807 leaf_info[node_index].mem_parity_field, 6808 test_type, 6809 MEM_BLOCK_ANY, 0, 6810 _SOC_ACC_TYPE_PIPE_ANY, 6811 pTestErrors); 6812 6813 if (rv != SOC_E_NONE) { 6814 LOG_CLI((BSL_META_U(unit, 6815 "Error during MMU:%s SER test.\n"), 6816 SOC_MEM_NAME(unit, mem))); 6817 } else { 6818 LOG_CLI((BSL_META_U(unit, 6819 "MMU SER test passed: %s id:%d\n\n"), 6820 SOC_MEM_NAME(unit, mem), mem)); 6821 } 6822 6823 test_count ++; 6824 } 6825 } 6826 } 6827 6828 #ifdef BCM_METROLITE_SUPPORT 6829 if (SOC_IS_METROLITE(unit)) { 6830 sub_block_num = COUNTOF(_soc_metrolite_mmu_sub_blocks_type_2); 6831 sub_block_2 = &_soc_metrolite_mmu_sub_blocks_type_2[0]; 6832 }else 6833 #endif 6834 { 6835 sub_block_num = COUNTOF(_soc_saber2_mmu_sub_blocks_type_2); 6836 sub_block_2 = &_soc_saber2_mmu_sub_blocks_type_2[0]; 6837 } 6838 for (block_index = 0; block_index < sub_block_num; block_index++, sub_block_2++) { 6839 /* coverity[overrun-local:FALSE] */ 6840 sub_block_internal = sub_block_2->info; 6841 if ((sub_block_internal == NULL) || (sub_block_2->mmu_bit == 0)) { 6842 break; 6843 } 6844 for(sub_block_index = 0; ; sub_block_index ++) { 6845 if(sub_block_internal[sub_block_index].intr_bit == 0) { 6846 break; 6847 } 6848 leaf_info = sub_block_internal[sub_block_index].info; 6849 for(node_index = 0; ; node_index ++) { 6850 if(leaf_info[node_index].intr_bit == 0) { 6851 break; 6852 } 6853 mem = leaf_info[node_index].mem; 6854 if(mem == INVALIDm) { 6855 continue; 6856 } 6857 6858 if (!SOC_MEM_IS_VALID(unit, mem)) { 6859 LOG_CLI((BSL_META_U(unit, 6860 "%s is not a valid memory for this platform. Skipping.\n"), 6861 SOC_MEM_NAME(unit, mem))); 6862 continue; 6863 } 6864 /* now test 1 bit error */ 6865 if(soc_mem_field_length(unit, mem, leaf_info[node_index].mem_parity_field) > 1) { 6866 continue; 6867 } 6868 6869 if (SOC_MEM_SER_CORRECTION_TYPE(unit, mem)) { 6870 LOG_CLI((BSL_META_U(unit, 6871 "\nMMU SER test begin: %s id:%d flag:0x%x\n"), 6872 SOC_MEM_NAME(unit, mem), mem, 6873 SOC_MEM_INFO(unit, mem).flags & _SOC_SABER2_SER_FLAG_MASK)); 6874 6875 null_entry = soc_mem_entry_null(unit, mem); 6876 rv = soc_mem_write(unit, mem, MEM_BLOCK_ANY, 0, null_entry); 6877 6878 if (rv != SOC_E_NONE) { 6879 LOG_CLI((BSL_META_U(unit, 6880 "mem:%s id:%d clear entry failed.\n"), 6881 SOC_MEM_NAME(unit, mem), mem)); 6882 } 6883 6884 rv = ser_test_mem_pipe(unit, 6885 leaf_info[node_index].mem_parity_enable_reg, 6886 SOC_INVALID_TCAM_PARITY_BIT, 6887 leaf_info[node_index].mem_parity_enable_field, 6888 mem, INVALIDf, test_type, 6889 MEM_BLOCK_ANY, 0, 6890 _SOC_ACC_TYPE_PIPE_ANY, 6891 pTestErrors); 6892 6893 if (rv != SOC_E_NONE) { 6894 LOG_CLI((BSL_META_U(unit, 6895 "Error during MMU:%s SER test.\n"), 6896 SOC_MEM_NAME(unit, mem))); 6897 } else { 6898 LOG_CLI((BSL_META_U(unit, 6899 "MMU SER test passed: %s id:%d\n\n"), 6900 SOC_MEM_NAME(unit, mem), mem)); 6901 } 6902 6903 test_count ++; 6904 } 6905 } 6906 } 6907 } 6908 6909 LOG_CLI((BSL_META_U(unit, 6910 "MMU SER memories tested:%u failed:%u.\n\n"), test_count, *pTestErrors)); 6911 6912 6913 return test_count; 6914 } 6915 6916 6917 int 6918 soc_saber2_ser_hw_test(int unit, _soc_ser_test_t test_type, int *pTestErrors) 6919 { 6920 int group, i, j, rv, table = 0; 6921 _soc_saber2_parity_info_t *info = NULL; 6922 _soc_saber2_fifo_ser_info_t *fifo_info = NULL; 6923 soc_mem_t mem = INVALIDm; 6924 soc_port_t block_port = 0; 6925 soc_block_t blk; 6926 uint32 test_count = 0; 6927 void *null_entry = NULL; 6928 const _soc_saber2_parity_route_block_t *parity_intr_route_block = NULL; 6929 6930 #ifdef BCM_METROLITE_SUPPORT 6931 if (SOC_IS_METROLITE(unit)) { 6932 parity_intr_route_block = &_soc_metrolite_parity_intr_route_blocks[0]; 6933 } else 6934 #endif 6935 { 6936 parity_intr_route_block = &_soc_saber2_parity_intr_route_blocks[0]; 6937 } 6938 6939 /* loop through each group. not fifo mode */ 6940 for (group = 0; parity_intr_route_block[group].cmic_bit; group++) { 6941 info = parity_intr_route_block[group].info; 6942 if(NULL == info) { 6943 continue; 6944 } 6945 6946 if ((parity_intr_route_block[group].blocktype == SOC_BLK_MXQPORT) || 6947 (parity_intr_route_block[group].blocktype == SOC_BLK_XLPORT) || 6948 (parity_intr_route_block[group].blocktype == SOC_BLK_TXLP) || 6949 (parity_intr_route_block[group].blocktype == SOC_BLK_RXLP)) 6950 { 6951 continue; 6952 } 6953 6954 if (parity_intr_route_block[group].blocktype == SOC_BLK_MMU) { 6955 continue; 6956 } 6957 6958 SOC_BLOCK_ITER(unit, blk, parity_intr_route_block[group].blocktype) { 6959 if (soc_saber2_parity_block_port(unit, blk, &block_port) < 0) { 6960 continue; 6961 } 6962 6963 for (table = 0; info[table].type != _SOC_PARITY_TYPE_NONE; table++) { 6964 mem = info[table].mem; 6965 if (mem == INVALIDm) { 6966 continue; 6967 } 6968 6969 if ((info[table].enable_reg == INVALIDr) || 6970 !soc_reg_field_valid(unit, info[table].enable_reg, 6971 info[table].enable_field)) { 6972 LOG_ERROR(BSL_LS_SOC_COMMON, 6973 (BSL_META_U(unit, 6974 "unit %d %s has no parity toggle.\n"), 6975 unit, SOC_MEM_NAME(unit, mem))); 6976 continue; 6977 } 6978 6979 test_count++; 6980 LOG_CLI((BSL_META_U(unit, 6981 "SER HW test begin: %s id:%d\n"), 6982 SOC_MEM_NAME(unit, mem), mem)); 6983 6984 null_entry = soc_mem_entry_null(unit, mem); 6985 rv = soc_mem_write(unit, mem, MEM_BLOCK_ANY, 0, null_entry); 6986 6987 if (rv != SOC_E_NONE) { 6988 LOG_CLI((BSL_META_U(unit, 6989 "mem:%s id:%d clear entry failed.\n"), 6990 SOC_MEM_NAME(unit, mem), mem)); 6991 } 6992 6993 rv = ser_test_mem_pipe(unit, info[table].enable_reg, -1, 6994 info[table].enable_field, 6995 mem, INVALIDf, test_type, 6996 MEM_BLOCK_ANY, REG_PORT_ANY, 6997 _SOC_ACC_TYPE_PIPE_ANY, 6998 pTestErrors); 6999 7000 if (rv != SOC_E_NONE) { 7001 LOG_CLI((BSL_META_U(unit, 7002 "%s Error during H/W SER test.\n\n"), 7003 SOC_MEM_NAME(unit, mem))); 7004 } else { 7005 LOG_CLI((BSL_META_U(unit, 7006 "%s SER test passed.\n\n"), 7007 SOC_MEM_NAME(unit, mem))); 7008 } 7009 7010 } 7011 } 7012 } 7013 block_port = 0; 7014 7015 /* IP/EP in fifo mode */ 7016 for (i = 0; _soc_saber2_fifo_ser_block_info[i].blocktype; i++) { 7017 fifo_info = _soc_saber2_fifo_ser_block_info[i].info; 7018 7019 for (j = 0; fifo_info[j].enable_reg != INVALIDr;j++) { 7020 7021 if(_soc_saber2_mem_reg_skip(fifo_info[j].type, fifo_info[j].mem, fifo_info[j].reg)) { 7022 continue ; 7023 } 7024 7025 if ((fifo_info[j].mem != INVALIDm) && 7026 (SOC_MEM_SER_CORRECTION_TYPE(unit, fifo_info[j].mem))) { 7027 mem = fifo_info[j].mem; 7028 7029 /* Some mem/regs have been removed or without ecc/parity fields in 56270. */ 7030 if (!soc_reg_field_valid(unit, fifo_info[j].enable_reg, fifo_info[j].enable_field) 7031 || (!soc_mem_field_valid(unit, mem, fifo_info[j].parity_field))) { 7032 continue; 7033 } 7034 7035 LOG_CLI((BSL_META_U(unit, 7036 "mem:%s id:%d SER test begin, mem type 0x:%x field:%s\n"), 7037 SOC_MEM_NAME(unit, mem), mem, 7038 SOC_MEM_SER_CORRECTION_TYPE(unit, mem), 7039 SOC_FIELD_NAME(unit, fifo_info[j].parity_field))); 7040 7041 null_entry = soc_mem_entry_null(unit, mem); 7042 rv = soc_mem_write(unit, mem, MEM_BLOCK_ANY, 0, null_entry); 7043 if (rv != SOC_E_NONE) { 7044 LOG_CLI((BSL_META_U(unit, 7045 "mem:%s id:%d clear entry failed.\n"), 7046 SOC_MEM_NAME(unit, mem), mem)); 7047 } 7048 7049 rv = ser_test_mem_pipe(unit, fifo_info[j].enable_reg, -1, 7050 fifo_info[j].enable_field, 7051 mem, 7052 fifo_info[j].parity_field, 7053 test_type, 7054 MEM_BLOCK_ANY, REG_PORT_ANY, 7055 _SOC_ACC_TYPE_PIPE_ANY, 7056 pTestErrors); 7057 if (rv != SOC_E_NONE) { 7058 LOG_CLI((BSL_META_U(unit, 7059 "mem:%s id:%d Error during IP/EP SER test.\n\n"), 7060 SOC_MEM_NAME(unit, mem), mem)); 7061 } 7062 else { 7063 LOG_CLI((BSL_META_U(unit, 7064 "mem:%s id:%d SER test passed.\n\n"), 7065 SOC_MEM_NAME(unit, mem), mem)); 7066 } 7067 7068 test_count++; 7069 } 7070 } 7071 } 7072 7073 7074 LOG_CLI((BSL_META_U(unit, 7075 "Hardware SER memories tested:%u failed:%u.\n\n"), test_count, *pTestErrors)); 7076 7077 return test_count; 7078 } 7079 7080 7081 7082 soc_error_t 7083 soc_saber2_ser_test (int unit, _soc_ser_test_t test_type) 7084 { 7085 /* For TR 144*/ 7086 int numTCAMErr = 0 , numHWErr = 0, numMMUErr = 0; 7087 int numTotalErr = 0; 7088 int numTotalTest = 0; 7089 7090 /* tcam */ 7091 numTotalTest += soc_saber2_ser_tcam_test(unit, test_type, &numTCAMErr); 7092 7093 /* HW */ 7094 numTotalTest += soc_saber2_ser_hw_test(unit, test_type, &numHWErr); 7095 7096 /* MMU test*/ 7097 numTotalTest += soc_saber2_ser_mmu_test(unit, test_type, &numMMUErr); 7098 7099 numTotalErr = numTCAMErr + numHWErr + numMMUErr; 7100 7101 LOG_CLI((BSL_META_U(unit, 7102 "\nSER test:%d failed:%d passed:%d\n"), 7103 numTotalTest, numTotalErr, numTotalTest - numTotalErr)); 7104 7105 7106 return SOC_E_NONE; 7107 } 7108 7109 void soc_saber2_ser_test_function_register(int unit) 7110 { 7111 /*Initialize chip-specific functions for SER testing*/ 7112 memset(&ser_saber2_test_fun, 0, sizeof(soc_ser_test_functions_t)); 7113 ser_saber2_test_fun.inject_error_f = &soc_saber2_ser_inject_error; 7114 ser_saber2_test_fun.test_mem = &soc_saber2_ser_test_mem; 7115 ser_saber2_test_fun.test = &soc_saber2_ser_test; 7116 ser_saber2_test_fun.parity_control = &_ser_test_parity_control_reg_set; /* tcam */ 7117 ser_saber2_test_fun.injection_support = &soc_saber2_ser_error_injection_support; 7118 7119 soc_ser_test_functions_register(unit, &ser_saber2_test_fun); 7120 } 7121 7122 static soc_ser_functions_t ser_saber2_functions; 7123 static soc_oam_event_functions_t ser_sb2_oam_event_funs; 7124 7125 void 7126 soc_saber2_ser_fail(int unit) 7127 { 7128 soc_generic_ser_process_error(unit, _soc_saber2_tcam_ser_info[unit], 7129 _SOC_PARITY_TYPE_SER); 7130 return; 7131 } 7132 7133 7134 STATIC soc_error_t 7135 soc_saber2_mem_nack_process_info(int unit, int reg_mem, 7136 _soc_saber2_ser_nack_reg_mem_t nack_reg_mem, 7137 const _soc_saber2_parity_info_t *info_list, 7138 char *prefix_str, soc_block_t block_type, 7139 int block_idx) 7140 { 7141 const _soc_saber2_parity_info_t *info; 7142 int info_index; 7143 char *mem_str; 7144 soc_port_t port = REG_PORT_ANY; 7145 7146 /* Loop through each info entry in the list */ 7147 for (info_index = 0; ; info_index++) { 7148 info = &info_list[info_index]; 7149 if (info->type == _SOC_PARITY_TYPE_NONE) { 7150 /* End of table */ 7151 break; 7152 } 7153 if (reg_mem == _SOC_SABER2_SER_MEM && info->mem != nack_reg_mem.mem) { 7154 continue; 7155 } 7156 if (info->mem_str) { 7157 mem_str = info->mem_str; 7158 } else { 7159 mem_str = SOC_MEM_NAME(unit, info->mem); 7160 } 7161 7162 /* Handle different parity error reporting style */ 7163 switch (info->type) { 7164 case _SOC_PARITY_TYPE_PARITY: 7165 SOC_IF_ERROR_RETURN 7166 (soc_saber2_parity_process_parity(unit, port, info, TRUE, 7167 prefix_str, mem_str, block_type, 7168 block_idx)); 7169 break; 7170 case _SOC_PARITY_TYPE_ECC: 7171 SOC_IF_ERROR_RETURN 7172 (soc_saber2_parity_process_ecc(unit, port, info, TRUE, 7173 prefix_str, mem_str, block_type, 7174 block_idx)); 7175 break; 7176 default: 7177 break; 7178 } /* Handle different parity error reporting style */ 7179 } /* Loop through each info entry in the list */ 7180 7181 return SOC_E_NONE; 7182 } 7183 7184 STATIC soc_error_t 7185 soc_saber2_found_mem_in_mmu(int unit, soc_mem_t mem, 7186 _soc_saber2_mmu_sub_block_leaf_info_t * mmu_leaf_info) 7187 { 7188 int rv = SOC_E_UNAVAIL; 7189 uint32 sub_block_num = 0; 7190 int block_index, sub_block_index, node_index; 7191 _soc_saber2_mmu_sub_block_one_level_t * sub_block = NULL; 7192 _soc_saber2_mmu_sub_block_two_level_t * sub_block_2 = NULL; 7193 _soc_saber2_mmu_sub_block_internal_info_t * sub_block_internal = NULL; 7194 _soc_saber2_mmu_sub_block_leaf_info_t * leaf_info = NULL; 7195 7196 if(mmu_leaf_info == NULL) { 7197 return SOC_E_PARAM; 7198 } 7199 7200 #ifdef BCM_METROLITE_SUPPORT 7201 /* Exclude the last one */ 7202 if (SOC_IS_METROLITE(unit)) { 7203 sub_block_num = COUNTOF(_soc_metrolite_mmu_sub_blocks_type_1) - 1; 7204 sub_block = &_soc_metrolite_mmu_sub_blocks_type_1[0]; 7205 }else 7206 #endif 7207 { 7208 sub_block_num = COUNTOF(_soc_saber2_mmu_sub_blocks_type_1) - 1; 7209 sub_block = &_soc_saber2_mmu_sub_blocks_type_1[0]; 7210 } 7211 for (block_index = 0; block_index < sub_block_num; block_index++, sub_block++) { 7212 leaf_info = sub_block->info; 7213 if(leaf_info == NULL) { 7214 break; 7215 } 7216 for(node_index = 0; ; node_index ++) { 7217 if(leaf_info[node_index].intr_bit == 0) { 7218 break; 7219 } 7220 if(leaf_info[node_index].mem == mem) { 7221 *mmu_leaf_info = leaf_info[node_index]; 7222 return SOC_E_NONE; 7223 } 7224 } 7225 } 7226 7227 #ifdef BCM_METROLITE_SUPPORT 7228 /* Exclude the last one */ 7229 if (SOC_IS_METROLITE(unit)) { 7230 sub_block_num = COUNTOF(_soc_metrolite_mmu_sub_blocks_type_2) - 1; 7231 sub_block_2 = &_soc_metrolite_mmu_sub_blocks_type_2[0]; 7232 }else 7233 #endif 7234 { 7235 sub_block_num = COUNTOF(_soc_saber2_mmu_sub_blocks_type_2) - 1; 7236 sub_block_2 = &_soc_saber2_mmu_sub_blocks_type_2[0]; 7237 } 7238 for (block_index = 0; block_index < sub_block_num; block_index++, sub_block_2++) { 7239 sub_block_internal = sub_block_2->info; 7240 if(sub_block_internal == NULL) { 7241 break; 7242 } 7243 for(sub_block_index = 0; ; sub_block_index ++) { 7244 if(sub_block_internal[sub_block_index].intr_bit == 0) { 7245 break; 7246 } 7247 leaf_info = sub_block_internal[sub_block_index].info; 7248 if(leaf_info == NULL) { 7249 break; 7250 } 7251 for(node_index = 0; ; node_index ++) { 7252 if(leaf_info[node_index].intr_bit == 0) { 7253 break; 7254 } 7255 if(leaf_info[node_index].mem == mem) { 7256 *mmu_leaf_info = leaf_info[node_index]; 7257 return SOC_E_NONE; 7258 } 7259 } 7260 } 7261 } 7262 7263 return rv; 7264 } 7265 7266 7267 7268 STATIC int 7269 soc_saber2_mem_nack_error_process(int unit, 7270 _soc_saber2_ser_nack_reg_mem_t nack_reg_mem, 7271 int reg_mem, uint32 address) 7272 { 7273 const _soc_saber2_parity_route_block_t *route_block = NULL; 7274 int route_block_index, block_idx, block_num = 0; 7275 uint32 cmic_bit; 7276 char prefix_str[10]; 7277 7278 sal_sprintf(prefix_str, "Unit: %d \n", unit); 7279 7280 #ifdef BCM_METROLITE_SUPPORT 7281 if (SOC_IS_METROLITE(unit)) { 7282 route_block = &_soc_metrolite_parity_intr_route_blocks[0]; 7283 block_num = COUNTOF(_soc_metrolite_parity_intr_route_blocks); 7284 } else 7285 #endif 7286 { 7287 route_block = &_soc_saber2_parity_intr_route_blocks[0]; 7288 block_num = COUNTOF(_soc_saber2_parity_intr_route_blocks); 7289 } 7290 7291 /* Loop through each place-and-route block entry */ 7292 for (route_block_index = 0; route_block_index < block_num; 7293 route_block_index++, route_block++) { 7294 /* coverity[overrun-local:FALSE] */ 7295 cmic_bit = route_block->cmic_bit; 7296 7297 if(route_block->info == NULL) { 7298 continue; 7299 } 7300 7301 if (cmic_bit == 0) { 7302 /* End of table */ 7303 break; 7304 } 7305 7306 SOC_BLOCK_ITER(unit, block_idx, route_block->blocktype) { 7307 if (SOC_BLOCK_INFO(unit, block_idx).number == route_block->id) { 7308 break; 7309 } 7310 } 7311 7312 /* IP/EP none-fifo mem */ 7313 if ((route_block->blocktype == SOC_BLK_IPIPE) || 7314 (route_block->blocktype == SOC_BLK_EPIPE)) { 7315 SOC_IF_ERROR_RETURN 7316 (soc_saber2_mem_nack_process_info(unit, 7317 reg_mem, nack_reg_mem, 7318 route_block->info, 7319 prefix_str, route_block->blocktype, 7320 block_idx)); 7321 } 7322 7323 } /* Loop through each place-and-route block entry */ 7324 7325 return SOC_E_NONE; 7326 } 7327 7328 7329 void 7330 soc_saber2_mem_nack(void *unit_vp, void *addr_vp, void *blk_vp, 7331 void *d3, void *d4) 7332 { 7333 soc_mem_t mem = INVALIDm; 7334 int reg_mem = PTR_TO_INT(d3); 7335 int rv, unit = PTR_TO_INT(unit_vp); 7336 uint32 address = PTR_TO_INT(addr_vp); 7337 uint32 block = PTR_TO_INT(blk_vp); 7338 soc_regaddrinfo_t ainfo; 7339 _soc_saber2_ser_nack_reg_mem_t nack_reg_mem = { 0 }; 7340 7341 if (reg_mem == _SOC_SABER2_SER_REG) { 7342 if (address) { 7343 soc_regaddrinfo_get(unit, &ainfo, address); 7344 nack_reg_mem.reg = ainfo.reg; 7345 } 7346 LOG_ERROR(BSL_LS_SOC_COMMON, 7347 (BSL_META_U(unit, 7348 "unit %d REG SCHAN NACK analysis address 0x:%x\n"), 7349 unit, address)); 7350 } else { 7351 mem = soc_addr_to_mem_extended(unit, block, 0, address); 7352 if (mem == INVALIDm) { 7353 LOG_ERROR(BSL_LS_SOC_COMMON, 7354 (BSL_META_U(unit, 7355 "unit %d mem decode failed, " 7356 "SCHAN NACK analysis failure address 0x:%x\n"), 7357 unit, address)); 7358 return; 7359 } else { 7360 LOG_ERROR(BSL_LS_SOC_COMMON, 7361 (BSL_META_U(unit, 7362 "unit %d mem:%s decode address 0x:%x\n"), 7363 unit,SOC_MEM_NAME(unit, mem), address)); 7364 } 7365 7366 nack_reg_mem.mem = mem; 7367 } 7368 7369 if ((rv = soc_saber2_mem_nack_error_process(unit, nack_reg_mem, 7370 reg_mem, address)) < 0) { 7371 if (reg_mem == _SOC_SABER2_SER_REG) { 7372 LOG_ERROR(BSL_LS_SOC_COMMON, 7373 (BSL_META_U(unit, 7374 "unit %d REG SCHAN NACK analysis failure\n"), 7375 unit)); 7376 } else { 7377 LOG_ERROR(BSL_LS_SOC_COMMON, 7378 (BSL_META_U(unit, 7379 "unit %d mem:%s SCHAN NACK analysis failure\n"), 7380 unit, SOC_MEM_NAME(unit, mem))); 7381 } 7382 } 7383 7384 } 7385 7386 STATIC void 7387 soc_saber2_ser_error(void *unit_vp, void *d1, void *d2, void *d3, 7388 void *d4) 7389 { 7390 int unit = PTR_TO_INT(unit_vp); 7391 7392 (void)soc_saber2_ser_process_all(unit); 7393 sal_usleep(SAL_BOOT_QUICKTURN ? 100000 : 1000); /* Don't reenable too soon */ 7394 if (d2 != NULL) { 7395 (void)soc_cmicm_intr3_enable(unit, PTR_TO_INT(d2)); 7396 } 7397 7398 } 7399 7400 STATIC void 7401 soc_saber2_oam_event_process(void *unit_vp, void *d1, 7402 void *d2, void *d3, void *d4) 7403 { 7404 int unit = PTR_TO_INT(unit_vp); 7405 uint32 rval = 0; 7406 7407 /* Handle OAM interrupt */ 7408 if (READ_IP1_INTR_STATUS_1r(unit, &rval) == SOC_E_NONE) { 7409 if (rval & KT2_OAM_INTR_MASK) { 7410 /* Call OAM interrupt handler */ 7411 soc_kt2_oam_interrupt_process(unit); 7412 } 7413 } else { 7414 LOG_ERROR(BSL_LS_SOC_COMMON, 7415 (BSL_META_U(unit, 7416 "unit %d: Error reading %s reg !!\n"), 7417 unit, SOC_REG_NAME(unit, IP1_INTR_STATUS_1r))); 7418 } 7419 7420 sal_usleep(SAL_BOOT_QUICKTURN ? 100000 : 1000); /* Don't reenable too soon */ 7421 if (d2 != NULL) { 7422 (void)soc_cmicm_intr3_enable(unit, PTR_TO_INT(d2)); 7423 } 7424 7425 } 7426 7427 void soc_saber2_ser_function_register(int unit) 7428 { 7429 memset(&ser_saber2_functions, 0, sizeof(soc_ser_functions_t)); 7430 /*_soc_ser_stat_nack_f is used for counter err statistics . */ 7431 ser_saber2_functions._soc_ser_stat_nack_f = NULL; 7432 /* _soc_ser_fail_f is used to TCAM ser process*/ 7433 ser_saber2_functions._soc_ser_fail_f = &soc_saber2_ser_fail; 7434 /* schan nack process */ 7435 ser_saber2_functions._soc_ser_mem_nack_f = &soc_saber2_mem_nack; 7436 ser_saber2_functions._soc_ser_parity_error_cmicm_intr_f = 7437 &soc_saber2_ser_error; 7438 7439 soc_ser_function_register(unit, &ser_saber2_functions); 7440 7441 } 7442 7443 void soc_saber2_oam_event_function_register(int unit) 7444 { 7445 memset(&ser_sb2_oam_event_funs, 0, sizeof(soc_oam_event_functions_t)); 7446 ser_sb2_oam_event_funs._soc_oam_event_intr_f = 7447 &soc_saber2_oam_event_process; 7448 soc_oam_event_function_register(unit, &ser_sb2_oam_event_funs); 7449 7450 } 7451 7452 int soc_saber2_ser_init(int unit,int enable) 7453 { 7454 soc_ser_log_init(unit, NULL, 0); 7455 7456 if (!enable) { 7457 soc_saber2_oam_event_function_register (unit); 7458 } 7459 /* include all init process */ 7460 SOC_IF_ERROR_RETURN(soc_saber2_ser_enable_all(unit, enable ? TRUE : FALSE)); 7461 7462 if(TRUE == enable) { 7463 soc_saber2_ser_function_register(unit); 7464 7465 /* tcam */ 7466 SOC_IF_ERROR_RETURN(soc_saber2_ser_engine_init(unit)); 7467 7468 7469 #if defined(SER_TR_TEST_SUPPORT) 7470 soc_saber2_ser_test_function_register(unit); 7471 #endif 7472 } 7473 7474 #ifdef INCLUDE_MEM_SCAN 7475 soc_mem_scan_ser_list_register(unit, enable ? TRUE : FALSE, 7476 _soc_saber2_tcam_ser_info[unit]); 7477 #endif 7478 7479 return SOC_E_NONE; 7480 7481 } 7482 7483 soc_error_t 7484 soc_saber2_mem_parity_control(int unit, soc_mem_t mem, int copyno, int enable) 7485 { 7486 int i,j; 7487 int rv = SOC_E_UNAVAIL; 7488 _soc_saber2_fifo_ser_info_t *fifo_parity; 7489 _soc_saber2_mmu_sub_block_leaf_info_t leaf_info; 7490 7491 if (!soc_property_get(unit, spn_PARITY_ENABLE, FALSE)) { 7492 /* Parity checking is not enabled, nothing to do */ 7493 return SOC_E_NONE; 7494 } 7495 7496 /* EP/IP */ 7497 for (i = 0; _soc_saber2_fifo_ser_block_info[i].blocktype != 0; i++) { 7498 fifo_parity = _soc_saber2_fifo_ser_block_info[i].info; 7499 for (j = 0; fifo_parity[j].enable_reg != INVALIDr;j++) { 7500 if (fifo_parity[j].mem != INVALIDm && fifo_parity[j].mem == mem) { 7501 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, 7502 fifo_parity[j].enable_reg, REG_PORT_ANY, 7503 fifo_parity[j].enable_field, enable ? 1 : 0)); 7504 7505 return SOC_E_NONE; 7506 } 7507 } 7508 } 7509 7510 for (i = 0; _soc_saber2_ip_parity_info[i].type != _SOC_PARITY_TYPE_NONE; i++) { 7511 if (_soc_saber2_ip_parity_info[i].mem == mem && 7512 _soc_saber2_ip_parity_info[i].mem != INVALIDm) { 7513 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, 7514 _soc_saber2_ip_parity_info[i].enable_reg, REG_PORT_ANY, 7515 _soc_saber2_ip_parity_info[i].enable_field, enable ? 1 : 0)); 7516 7517 return SOC_E_NONE; 7518 } 7519 } 7520 7521 for (i = 0; _soc_saber2_ep_parity_info[i].type != _SOC_PARITY_TYPE_NONE; i++) { 7522 if (_soc_saber2_ep_parity_info[i].mem == mem && 7523 _soc_saber2_ep_parity_info[i].mem != INVALIDm) { 7524 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, 7525 _soc_saber2_ep_parity_info[i].enable_reg, REG_PORT_ANY, 7526 _soc_saber2_ep_parity_info[i].enable_field, enable ? 1 : 0)); 7527 7528 return SOC_E_NONE; 7529 } 7530 } 7531 7532 /* MMU*/ 7533 rv = soc_saber2_found_mem_in_mmu(unit, mem, &leaf_info); 7534 if (rv == SOC_E_NONE) { 7535 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, 7536 leaf_info.mem_parity_enable_reg, REG_PORT_ANY, 7537 leaf_info.mem_parity_enable_field, enable ? 1 : 0)); 7538 7539 return SOC_E_NONE; 7540 } 7541 7542 return rv; 7543 7544 } 7545 7546 soc_error_t 7547 soc_saber2_ser_mem_clear(int unit, soc_mem_t mem) 7548 { 7549 uint32 range_enable; 7550 int info_ix, i; 7551 _soc_generic_ser_info_t *cur_spi; 7552 ser_memory_entry_t ser_mem; 7553 7554 /* Check if enable */ 7555 SOC_IF_ERROR_RETURN 7556 (READ_SER_RANGE_ENABLEr(unit, &range_enable)); 7557 7558 if (!range_enable) { 7559 return SOC_E_NONE; 7560 } 7561 7562 info_ix = 0; 7563 7564 while (_soc_saber2_tcam_ser_info[unit][info_ix].mem != INVALIDm) { 7565 if (_soc_saber2_tcam_ser_info[unit][info_ix].mem == mem) { 7566 break; 7567 } 7568 info_ix++; 7569 } 7570 7571 if ((_soc_saber2_tcam_ser_info[unit][info_ix].mem != INVALIDm) && 7572 (range_enable & (1 << info_ix))) { 7573 cur_spi = &(_soc_saber2_tcam_ser_info[unit][info_ix]); 7574 7575 range_enable &= ~(1 << info_ix); 7576 /* Disable SER protection on this memory */ 7577 SOC_IF_ERROR_RETURN 7578 (WRITE_SER_RANGE_ENABLEr(unit, range_enable)); 7579 7580 7581 /* Flush SER memory segment for the table */ 7582 sal_memset(&ser_mem, 0, sizeof(ser_mem)); 7583 for (i = cur_spi->ser_section_start; 7584 i <= cur_spi->ser_section_end; 7585 i++) { 7586 SOC_IF_ERROR_RETURN 7587 (WRITE_SER_MEMORYm(unit, MEM_BLOCK_ALL, i, &ser_mem)); 7588 } 7589 7590 range_enable |= (1 << info_ix); 7591 /* Enable SER protection on this memory */ 7592 SOC_IF_ERROR_RETURN 7593 (WRITE_SER_RANGE_ENABLEr(unit, range_enable)); 7594 7595 LOG_VERBOSE(BSL_LS_SOC_COMMON, 7596 (BSL_META_U(unit, 7597 "\t%s: SER[%d-%d]\n"), 7598 SOC_MEM_NAME(unit, cur_spi->mem), 7599 cur_spi->ser_section_start, cur_spi->ser_section_end)); 7600 } 7601 7602 return SOC_E_NONE; 7603 7604 } 7605 7606 7607 #endif /* BCM_SABER_SUPPORT */