ddr_and28.c (118269B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: ddr_and28.c 8 * Purpose: 9 * Requires: 10 */ 11 12 #include <sal/core/boot.h> 13 14 #include <soc/katana2.h> 15 #include <soc/saber2.h> 16 #include <soc/trident.h> 17 #include <soc/bradley.h> 18 #include <soc/drv.h> 19 #include <soc/error.h> 20 #include <soc/debug.h> 21 #include <soc/mem.h> 22 #include <soc/hash.h> 23 #include <soc/shmoo_and28.h> 24 #include <soc/phy/ddr34.h> 25 #include <soc/mspi.h> 26 #include <soc/phyreg.h> 27 #include <shared/bsl.h> 28 #ifdef BCM_CMICM_SUPPORT 29 #include <soc/cmicm.h> 30 #endif 31 #include <soc/iproc.h> 32 #include <sal/appl/config.h> 33 #include <shared/util.h> 34 #ifdef BCM_SABER2_SUPPORT 35 36 static uint32 dram0_clamshell_enable = 0; 37 static uint32 dram1_clamshell_enable = 0; 38 39 int soc_sb2_and28_post_shmoo_dram_init(int unit, int ci); 40 41 const sb2_req_grade_mem_set_set_t SABER2fgmss[SB2_FREQ_CNT][SB2_GRADE_CNT] = 42 { 43 { /* FREQ_667 */ 44 /* GRADE_DEFAULT */ 45 {10, 5, 17, 32, 48, 5, 8, 15, 11, 17, 24, 0, 0, 2600, 14, 18, {100, 54, 37}, 272, 9, 7, 10, 16, 667, 0x1b50, 0x0210}, 46 /* GRADE_080808 */ 47 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, { -1, -1, - 1}, -1, -1, -1, -1, -1, -1, -1, -1}, 48 /* GRADE_090909 */ 49 {10, 5, 17, 32, 48, 5, 8, 15, 11, 17, 24, 0, 0, 2600, 14, 18, {100, 54, 37}, 272, 9, 7, 10, 16, 667, 0x1b50, 0x0210}, 50 /* GRADE_101010 */ 51 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, { -1, -1, - 1}, -1, -1, -1, -1, -1, -1, -1, -1}, 52 /* GRADE_111111 */ 53 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, { -1, -1, - 1}, -1, -1, -1, -1, -1, -1, -1, -1}, 54 /* GRADE_121212 */ 55 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, { -1, -1, - 1}, -1, -1, -1, -1, -1, -1, -1, -1}, 56 /* GRADE_131313 */ 57 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, { -1, -1, - 1}, -1, -1, -1, -1, -1, -1, -1, -1}, 58 /* GRADE_141414 */ 59 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, { -1, -1, - 1}, -1, -1, -1, -1, -1, -1, -1, -1} 60 }, 61 62 { /* FREQ_800 */ 63 /* GRADE_DEFAULT */ 64 {13, 12, 20, 32, 48, 8, 12, 16, 15, 20, 25, 0, 0, 3056, 18, 22, {120, 64, 44}, 272, 11, 8, 12, 21, 800, 0x1d70, 0x0218}, 65 /* GRADE_080808 */ 66 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, { -1, -1, - 1}, -1, -1, -1, -1, -1, -1, -1, -1}, 67 /* GRADE_090909 */ 68 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, { -1, -1, - 1}, -1, -1, -1, -1, -1, -1, -1, -1}, 69 /* GRADE_101010 */ 70 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, { -1, -1, - 1}, -1, -1, -1, -1, -1, -1, -1, -1}, 71 /* GRADE_111111 */ 72 {13, 12, 20, 32, 48, 8, 12, 16, 15, 20, 25, 0, 0, 3056, 18, 22, {120, 64, 44}, 272, 11, 8, 12, 21, 800, 0x1d70, 0x0218}, 73 /* GRADE_121212 */ 74 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, { -1, -1, - 1}, -1, -1, -1, -1, -1, -1, -1, -1}, 75 /* GRADE_131313 */ 76 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, { -1, -1, - 1}, -1, -1, -1, -1, -1, -1, -1, -1}, 77 /* GRADE_141414 */ 78 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, { -1, -1, - 1}, -1, -1, -1, -1, -1, -1, -1, -1} 79 } 80 }; 81 82 #define SEGMENTS_CNT 6 83 84 const static uint32 85 sb2_ite_segment_gap[SB2_FREQ_CNT][SB2_CORE_PLL_CLOCK_CNT][SEGMENTS_CNT] = 86 { 87 /* FREQ_667 */ 88 { 89 /* CLK_130 */ {2, 2, 1, 1, 0, 0}, 90 /* CLK_118 */ {2, 2, 1, 1, 0, 0}, 91 /* CLK_75 */ {2, 2, 1, 1, 0, 0}, 92 /* CLK_37 */ {0, 0, 0, 0, 0, 0}, 93 /* CLK_24 */ {0, 0, 0, 0, 0, 0} 94 }, 95 /* FREQ_800 */ 96 { 97 /* CLK_130 */ {2, 1, 1, 1, 0, 0}, 98 /* CLK_118 */ {1, 1, 1, 0, 0, 0}, 99 /* CLK_75 */ {2, 1, 1, 1, 0, 0}, 100 /* CLK_37 */ {0, 0, 0, 0, 0, 0}, 101 /* CLK_24 */ {0, 0, 0, 0, 0, 0} 102 } 103 }; 104 105 int 106 _soc_ddr_sb2_mem_gradetoloc(uint32 grade) 107 { 108 switch(grade) { 109 case SB2_MEM_GRADE_080808: 110 return SB2_GRADE_080808; 111 case SB2_MEM_GRADE_090909: 112 return SB2_GRADE_090909; 113 case SB2_MEM_GRADE_101010: 114 return SB2_GRADE_101010; 115 case SB2_MEM_GRADE_111111: 116 return SB2_GRADE_111111; 117 case SB2_MEM_GRADE_121212: 118 return SB2_GRADE_121212; 119 case SB2_MEM_GRADE_131313: 120 return SB2_GRADE_131313; 121 case SB2_MEM_GRADE_141414: 122 return SB2_GRADE_141414; 123 default: 124 return SB2_GRADE_DEFAULT; 125 } 126 } 127 128 int 129 _soc_ddr_sb2_phy_freqtoloc(uint32 freq) 130 { 131 switch(freq) { 132 case SB2_DDR_FREQ_667: 133 return SB2_FREQ_667; 134 case SB2_DDR_FREQ_800: 135 return SB2_FREQ_800; 136 default: 137 LOG_ERROR(BSL_LS_SOC_COMMON, 138 (BSL_META("Unsupported Frequency %d MHz \n"), freq)); 139 return SOC_E_PARAM; 140 } 141 } 142 143 int 144 _soc_sb2_mem_rowstoloc(uint32 rows) 145 { 146 switch(rows) { 147 case SB2_MEM_ROWS_32K: 148 return SB2_MEM_4G; 149 case SB2_MEM_ROWS_16K: 150 return SB2_MEM_2G; 151 default: 152 return SB2_MEM_1G; 153 } 154 } 155 156 int 157 _soc_sb2_clktoloc(uint32 core_clock) { 158 switch(core_clock) { 159 case CORE_PLL_CLOCK_130M: 160 return SB2_CORE_PLL_CLOCK_130M; 161 case CORE_PLL_CLOCK_118M: 162 return SB2_CORE_PLL_CLOCK_118M; 163 case CORE_PLL_CLOCK_75M: 164 return SB2_CORE_PLL_CLOCK_75M; 165 case CORE_PLL_CLOCK_37M: 166 return SB2_CORE_PLL_CLOCK_37M; 167 case CORE_PLL_CLOCK_24M: 168 return SB2_CORE_PLL_CLOCK_24M; 169 default: 170 LOG_ERROR(BSL_LS_SOC_COMMON, 171 (BSL_META("Unsupported Clock %d MHz \n"), core_clock)); 172 return SOC_E_PARAM; 173 } 174 } 175 176 void 177 _soc_ddr_sb2_phy_init_mem_set_wrapper( uint32 unit, 178 sb2_req_grade_mem_set_set_t *fgmssPtr, 179 int freq_loc, int grade_loc ) { 180 181 182 fgmssPtr->twl = SABER2fgmss[freq_loc][grade_loc].twl; 183 fgmssPtr->twr = SABER2fgmss[freq_loc][grade_loc].twr; 184 fgmssPtr->trc = SABER2fgmss[freq_loc][grade_loc].trc; 185 fgmssPtr->rfifo_afull = SABER2fgmss[freq_loc][grade_loc].rfifo_afull; 186 fgmssPtr->rfifo_full = SABER2fgmss[freq_loc][grade_loc].rfifo_full; 187 fgmssPtr->trtw = SABER2fgmss[freq_loc][grade_loc].trtw; 188 fgmssPtr->twtr = SABER2fgmss[freq_loc][grade_loc].twtr; 189 fgmssPtr->tfaw = SABER2fgmss[freq_loc][grade_loc].tfaw; 190 fgmssPtr->tread_enb = soc_property_get(unit,spn_DDR3_TREAD_ENB, 191 SABER2fgmss[freq_loc][grade_loc].tread_enb); 192 fgmssPtr->bank_unavail_rd = soc_property_get(unit, 193 spn_DDR3_BANK_UNAVAIL_RD, SABER2fgmss[freq_loc][grade_loc].bank_unavail_rd); 194 fgmssPtr->bank_unavail_wr = soc_property_get(unit, 195 spn_DDR3_BANK_UNAVAIL_WR, SABER2fgmss[freq_loc][grade_loc].bank_unavail_wr); 196 fgmssPtr->rr_read = soc_property_get(unit,spn_DDR3_ROUND_ROBIN_READ, 197 SABER2fgmss[freq_loc][grade_loc].rr_read); 198 fgmssPtr->rr_write = soc_property_get(unit,spn_DDR3_ROUND_ROBIN_WRITE, 199 SABER2fgmss[freq_loc][grade_loc].rr_write); 200 fgmssPtr->refrate = soc_property_get(unit,spn_DDR3_REFRESH_INTVL_OVERRIDE, 201 SABER2fgmss[freq_loc][grade_loc].refrate); 202 fgmssPtr->trp_read = soc_property_get(unit,spn_DDR3_TRP_READ, 203 SABER2fgmss[freq_loc][grade_loc].trp_read); 204 fgmssPtr->trp_write = soc_property_get(unit,spn_DDR3_TRP_WRITE, 205 SABER2fgmss[freq_loc][grade_loc].trp_write); 206 fgmssPtr->trfc[SB2_MEM_4G] = SABER2fgmss[freq_loc][grade_loc].trfc[SB2_MEM_4G]; 207 fgmssPtr->trfc[SB2_MEM_2G] = SABER2fgmss[freq_loc][grade_loc].trfc[SB2_MEM_2G]; 208 fgmssPtr->trfc[SB2_MEM_1G] = SABER2fgmss[freq_loc][grade_loc].trfc[SB2_MEM_1G]; 209 fgmssPtr->tzq = SABER2fgmss[freq_loc][grade_loc].tzq; 210 fgmssPtr->cl = SABER2fgmss[freq_loc][grade_loc].cl; 211 fgmssPtr->cwl = SABER2fgmss[freq_loc][grade_loc].cwl; 212 fgmssPtr->wr = SABER2fgmss[freq_loc][grade_loc].wr; 213 fgmssPtr->jedec = SABER2fgmss[freq_loc][grade_loc].jedec; 214 fgmssPtr->mhz = SABER2fgmss[freq_loc][grade_loc].mhz; 215 fgmssPtr->mr0 = SABER2fgmss[freq_loc][grade_loc].mr0; 216 fgmssPtr->mr2 = SABER2fgmss[freq_loc][grade_loc].mr2; 217 218 } 219 220 221 int soc_sb2_and28_shmoo_phy_reg_read(int unit, int ci, uint32 reg_addr, uint32 *reg_data) 222 { 223 uint32 rval; 224 soc_timeout_t to; 225 226 rval = 0; 227 soc_reg_field_set(unit, TOP_CI_DDR_PHY_REG_CTRLr, &rval, PHY_REG_ACKf, 1); 228 soc_reg_field_set(unit, TOP_CI_DDR_PHY_REG_CTRLr, &rval, PHY_REG_ERR_ACKf, 1); 229 soc_reg_field_set(unit, TOP_CI_DDR_PHY_REG_CTRLr, &rval, PHY_REG_ADDRf, reg_addr); 230 soc_reg_field_set(unit, TOP_CI_DDR_PHY_REG_CTRLr, &rval, PHY_REG_RD_WR_Nf, 1); 231 soc_reg_field_set(unit, TOP_CI_DDR_PHY_REG_CTRLr, &rval, PHY_REG_REQf, 1); 232 SOC_IF_ERROR_RETURN(WRITE_TOP_CI_DDR_PHY_REG_CTRLr(unit, rval)); 233 234 if (SAL_BOOT_SIMULATION) { 235 soc_timeout_init(&to, 10000000, 0); /* 10 Sec */ 236 } else { 237 soc_timeout_init(&to, 50000, 0); /* 50 mS */ 238 } 239 do { 240 SOC_IF_ERROR_RETURN(READ_TOP_CI_DDR_PHY_REG_CTRLr(unit, &rval)); 241 if (soc_reg_field_get(unit, TOP_CI_DDR_PHY_REG_CTRLr, rval, PHY_REG_ACKf)) { 242 break; 243 } 244 if (soc_reg_field_get 245 (unit, TOP_CI_DDR_PHY_REG_CTRLr, rval, PHY_REG_ERR_ACKf)) { 246 return SOC_E_FAIL; 247 } 248 if (soc_timeout_check(&to)) { 249 return SOC_E_TIMEOUT; 250 } 251 } while (TRUE); 252 SOC_IF_ERROR_RETURN(READ_TOP_CI_DDR_PHY_REG_DATAr(unit, reg_data)); 253 254 return SOC_E_NONE; 255 } 256 257 int soc_sb2_and28_shmoo_phy_reg_write(int unit, int ci, uint32 reg_addr, uint32 reg_data) 258 { 259 uint32 rval; 260 soc_timeout_t to; 261 262 SOC_IF_ERROR_RETURN(WRITE_TOP_CI_DDR_PHY_REG_DATAr(unit, reg_data)); 263 264 rval = 0; 265 soc_reg_field_set(unit, TOP_CI_DDR_PHY_REG_CTRLr, &rval, PHY_REG_ACKf, 1); /* write 1 to clear */ 266 soc_reg_field_set(unit, TOP_CI_DDR_PHY_REG_CTRLr, &rval, PHY_REG_ERR_ACKf, 1); /* write 1 to clear */ 267 soc_reg_field_set(unit, TOP_CI_DDR_PHY_REG_CTRLr, &rval, PHY_REG_ADDRf, 268 reg_addr); 269 soc_reg_field_set(unit, TOP_CI_DDR_PHY_REG_CTRLr, &rval, PHY_REG_RD_WR_Nf, 0); 270 soc_reg_field_set(unit, TOP_CI_DDR_PHY_REG_CTRLr, &rval, PHY_REG_REQf, 1); 271 SOC_IF_ERROR_RETURN(WRITE_TOP_CI_DDR_PHY_REG_CTRLr(unit, rval)); 272 273 if (SAL_BOOT_SIMULATION) { 274 soc_timeout_init(&to, 10000000, 0); /* 10 Sec */ 275 } else { 276 soc_timeout_init(&to, 50000, 0); /* 50 mS */ 277 } 278 279 do { 280 SOC_IF_ERROR_RETURN(READ_TOP_CI_DDR_PHY_REG_CTRLr(unit, &rval)); 281 if (soc_reg_field_get(unit, TOP_CI_DDR_PHY_REG_CTRLr, rval, PHY_REG_ACKf)) { 282 break; 283 } 284 if (soc_reg_field_get 285 (unit, TOP_CI_DDR_PHY_REG_CTRLr, rval, PHY_REG_ERR_ACKf)) { 286 return SOC_E_FAIL; 287 } 288 if (soc_timeout_check(&to)) { 289 return SOC_E_TIMEOUT; 290 } 291 } while (TRUE); 292 293 return SOC_E_NONE; 294 } 295 296 int soc_sb2_and28_shmoo_phy_reg_modify(int unit, int ci, uint32 reg_addr, uint32 data, 297 uint32 mask) 298 { 299 int rv = SOC_E_NONE; 300 uint32 tmp, otmp; 301 302 data = data & mask; 303 304 SOC_IF_ERROR_RETURN(soc_sb2_and28_shmoo_phy_reg_read(unit, ci, reg_addr, &tmp)); 305 otmp = tmp; 306 tmp &= ~(mask); 307 tmp |= data; 308 309 if (otmp != tmp) { 310 SOC_IF_ERROR_RETURN 311 (soc_sb2_and28_shmoo_phy_reg_write(unit, ci, reg_addr, tmp)); 312 } 313 314 return rv; 315 } 316 317 int sb2_and28_configure_bist( 318 int unit, 319 int ci, 320 uint32 write_weight, 321 uint32 read_weight, 322 uint32 pattern_bit_mode, 323 uint32 two_addr_mode, 324 uint32 prbs_mode, 325 uint32 address_shift_mode, 326 uint32 data_shift_mode, 327 uint32 data_addr_mode, 328 uint32 bist_num_actions, 329 uint32 bist_start_address, 330 uint32 bist_end_address, 331 uint32 bg_interleave, 332 uint32 single_bank_test, 333 uint32 address_prbs_mode, 334 uint32 bist_pattern[SB2_BIST_NUM_PATTERNS]) 335 { 336 337 uint32 rval; 338 int i; 339 const static soc_reg_t bist_pattern_word_reg_list[] = 340 {BISTPATTERNWORD0r, BISTPATTERNWORD1r, BISTPATTERNWORD2r, 341 BISTPATTERNWORD3r, BISTPATTERNWORD4r, BISTPATTERNWORD5r, 342 BISTPATTERNWORD6r, BISTPATTERNWORD7r}; 343 const static soc_field_t bist_patten_field_list[] = 344 {BISTPATTERN0f, BISTPATTERN1f, BISTPATTERN2f, 345 BISTPATTERN3f, BISTPATTERN4f, BISTPATTERN5f, 346 BISTPATTERN6f, BISTPATTERN7f}; 347 348 SOC_IF_ERROR_RETURN(READ_BISTCONFIGURATIONSr(unit, ci, &rval)); 349 soc_reg_field_set(unit, BISTCONFIGURATIONSr, &rval, WRITEWEIGHTf, write_weight); 350 soc_reg_field_set(unit, BISTCONFIGURATIONSr, &rval, READWEIGHTf, read_weight); 351 soc_reg_field_set(unit, BISTCONFIGURATIONSr, &rval, PATTERNBITMODEf, pattern_bit_mode); 352 soc_reg_field_set(unit, BISTCONFIGURATIONSr, &rval, TWOADDRMODEf, two_addr_mode); 353 soc_reg_field_set(unit, BISTCONFIGURATIONSr, &rval, PRBSMODEf, prbs_mode); 354 soc_reg_field_set(unit, BISTCONFIGURATIONSr, &rval, CONSADDR8BANKSf, 1); 355 soc_reg_field_set(unit, BISTCONFIGURATIONSr, &rval, ADDRESSSHIFTMODEf, address_shift_mode); 356 soc_reg_field_set(unit, BISTCONFIGURATIONSr, &rval, DATASHIFTMODEf, data_shift_mode); 357 soc_reg_field_set(unit, BISTCONFIGURATIONSr, &rval, DATAADDRMODEf, data_addr_mode); 358 soc_reg_field_set(unit, BISTCONFIGURATIONSr, &rval, INDWRRDADDRMODEf, 1); 359 SOC_IF_ERROR_RETURN(WRITE_BISTCONFIGURATIONSr(unit, ci, rval)); 360 361 362 SOC_IF_ERROR_RETURN(READ_BISTNUMBEROFACTIONSr(unit, ci, &rval)); 363 soc_reg_field_set(unit, BISTNUMBEROFACTIONSr, &rval, BISTNUMACTIONSf, bist_num_actions); 364 SOC_IF_ERROR_RETURN(WRITE_BISTNUMBEROFACTIONSr(unit, ci, rval)); 365 366 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, BISTSTARTADDRESSr, ci, 0, &rval)); 367 soc_reg_field_set(unit, BISTSTARTADDRESSr, &rval, BISTSTARTADDRESSf, bist_start_address); 368 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, BISTSTARTADDRESSr, ci, 0, rval)); 369 370 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, BISTENDADDRESSr, ci, 0, &rval)); 371 soc_reg_field_set(unit, BISTENDADDRESSr, &rval, BISTENDADDRESSf, bist_end_address); 372 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, BISTENDADDRESSr, ci, 0, rval)); 373 374 if(bist_pattern != NULL) { 375 for(i = 0; i < SB2_BIST_NUM_PATTERNS; i++){ 376 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, 377 bist_pattern_word_reg_list[i], REG_PORT_ANY, 0, 378 bist_patten_field_list[i])); 379 } 380 } 381 return SOC_E_NONE; 382 } 383 384 int sb2_bist_atomic_action_polling(int unit, int ci) { 385 uint32 rval; 386 soc_timeout_t to; 387 388 if (SAL_BOOT_SIMULATION) { 389 soc_timeout_init(&to, 10000000, 0); /* 10 Sec */ 390 } else { 391 soc_timeout_init(&to, 50000, 0); /* 50 mS */ 392 } 393 394 do { 395 SOC_IF_ERROR_RETURN(READ_BISTSTATUSESr(unit, ci, &rval)); 396 if (soc_reg_field_get(unit, BISTSTATUSESr, rval, BISTFINISHEDf)) { 397 break; 398 } 399 400 if (soc_timeout_check(&to)) { 401 LOG_INFO(BSL_LS_SOC_DDR, 402 (BSL_META_U(unit, 403 "BIST TIMEOUT!!!\n"))); 404 return SOC_E_TIMEOUT; 405 } 406 }while(TRUE); 407 408 return SOC_E_NONE; 409 } 410 411 int sb2_bist_atomic_action_start(int unit, int ci, uint8 start) { 412 uint32 rval; 413 414 /* Disable BIST and enable if start is set */ 415 SOC_IF_ERROR_RETURN(READ_BISTCONFIGURATIONSr(unit, ci, &rval)); 416 soc_reg_field_set(unit, BISTCONFIGURATIONSr, &rval, BISTENf, 0); 417 SOC_IF_ERROR_RETURN(WRITE_BISTCONFIGURATIONSr(unit, ci, rval)); 418 419 if (start) { 420 SOC_IF_ERROR_RETURN(READ_BISTCONFIGURATIONSr(unit, ci, &rval)); 421 soc_reg_field_set(unit, BISTCONFIGURATIONSr, &rval, BISTENf, 1); 422 SOC_IF_ERROR_RETURN(WRITE_BISTCONFIGURATIONSr(unit, ci, rval)); 423 } 424 425 return SOC_E_NONE; 426 } 427 428 int sb2_bist_atomic_action(int unit, int ci, uint8 is_infinite, uint8 stop) { 429 430 /* Start BIST */ 431 if (stop == FALSE) { 432 SOC_IF_ERROR_RETURN(sb2_bist_atomic_action_start(unit, ci, TRUE)); 433 } 434 435 if (is_infinite == FALSE && stop == FALSE) { 436 SOC_IF_ERROR_RETURN(sb2_bist_atomic_action_polling(unit, ci)); 437 } 438 439 /* Wait BIST finished */ 440 if (is_infinite == FALSE || stop == TRUE) { 441 SOC_IF_ERROR_RETURN(sb2_bist_atomic_action_start(unit, ci, FALSE)); 442 } 443 444 return SOC_E_NONE; 445 } 446 447 int sb2_bist_start_test( int unit, int ci, 448 sb2_bist_info *info) { 449 450 int i; 451 uint32 pattern_lcl[SB2_BIST_NUM_PATTERNS]; 452 uint32 bist_repeat_pattern; 453 454 if ((info->bist_flags & SB2_BIST_FLAGS_USE_RANDOM_DATA_SEED ) != 0x0) { 455 for(i=0; i < SB2_BIST_NUM_PATTERNS; ++i) { 456 pattern_lcl[i] = sal_rand(); 457 } 458 } else if (info->pattern_mode == SB2_DRAM_BIST_DATA_PATTERN_DIFF) { 459 for(i=0; i < SB2_BIST_NUM_PATTERNS; ++i) { 460 pattern_lcl[i] = 0x55555555; 461 } 462 } else if (info->pattern_mode == SB2_DRAM_BIST_DATA_PATTERN_ONE) { 463 for(i=0; i < SB2_BIST_NUM_PATTERNS; ++i) { 464 pattern_lcl[i] = 0xffffffff; 465 } 466 } else if (info->pattern_mode == SB2_DRAM_BIST_DATA_PATTERN_ZERO) { 467 for(i=0; i < SB2_BIST_NUM_PATTERNS; ++i) { 468 pattern_lcl[i] = 0x00000000; 469 } 470 } else { 471 for (i=0; i < SB2_BIST_NUM_PATTERNS; ++i) { 472 pattern_lcl[i] = info->pattern[i]; 473 } 474 } 475 /* 476 LOG_INFO(BSL_LS_SOC_DDR, 477 (BSL_META_U(unit, 478 "Bit test parameters : ci : %d\n write_weight %d\n" 479 "read weight : %d\npattern_mode: %d\n" 480 "bist flag : 0x%x\n"), ci, info->write_weight, 481 info->read_weight, info->pattern_mode, info->bist_flags)); 482 */ 483 bist_repeat_pattern = soc_property_suffix_num_get(unit, -1, 484 spn_CUSTOM_FEATURE, "bist_repeat_pattern", 0xffffffff); 485 486 if(((info->bist_flags & 487 (SB2_BIST_FLAGS_STOP | SB2_BIST_FLAGS_GET_DATA)) == 0) && 488 bist_repeat_pattern == 0xffffffff) { 489 /* Configure BIST */ 490 SOC_IF_ERROR_RETURN(sb2_and28_configure_bist( 491 unit, ci, 492 info->write_weight, info->read_weight, 493 (info->pattern_mode == SB2_DRAM_BIST_DATA_PATTERN_BIT_MODE) ? TRUE : FALSE, 494 (info->bist_flags & SB2_BIST_FLAGS_TWO_ADDRESS_MODE) ? TRUE : FALSE, 495 (info->pattern_mode == SB2_DRAM_BIST_DATA_PATTERN_RANDOM_PRBS) ? TRUE : FALSE, 496 (info->bist_flags & SB2_BIST_FLAGS_ADDRESS_SHIFT_MODE) ? TRUE : FALSE, 497 (info->pattern_mode == SB2_DRAM_BIST_DATA_PATTERN_SHIFT_MODE) ? TRUE : FALSE, 498 (info->pattern_mode == SB2_DRAM_BIST_DATA_PATTERN_ADDR_MODE) ? TRUE : FALSE, 499 (info->bist_flags & SB2_BIST_FLAGS_INFINITE) ? 0 : info->bist_num_actions, 500 info->bist_start_address, info->bist_end_address, 501 (info->bist_flags & SB2_BIST_FLAGS_BG_INTERLEAVE) ? TRUE : FALSE, 502 (info->bist_flags & SB2_BIST_FLAGS_SINGLE_BANK_TEST) ? TRUE : FALSE, 503 (info->bist_flags & SB2_BIST_FLAGS_ADDRESS_PRBS_MODE) ? TRUE : FALSE, 504 pattern_lcl)); 505 } 506 507 if((info->bist_flags & SB2_BIST_FLAGS_GET_DATA) == 0) { 508 SOC_IF_ERROR_RETURN(sb2_bist_atomic_action( 509 unit, ci, 510 (info->bist_flags & SB2_BIST_FLAGS_INFINITE) ? TRUE : FALSE, 511 (info->bist_flags & SB2_BIST_FLAGS_STOP) ? TRUE : FALSE)); 512 } 513 514 return SOC_E_NONE; 515 } 516 517 int soc_sb2_and28_shmoo_drc_bist_ci_conf_set(int unit, int ci, and28_bist_info_t info) 518 { 519 int i; 520 sb2_bist_info bist_info; 521 uint32 bist_timer_us; 522 523 sal_memset(&bist_info, 0, sizeof(bist_info)); 524 525 bist_info.write_weight = info.write_weight; 526 bist_info.read_weight = info.read_weight; 527 bist_info.bist_start_address = info.bist_start_address; 528 bist_info.bist_end_address = info.bist_end_address; 529 530 for (i = 0; i < SB2_BIST_NUM_PATTERNS; i++) { 531 bist_info.pattern[i] = info.data_pattern[i]; 532 } 533 534 bist_timer_us = soc_property_suffix_num_get(unit, -1, spn_CUSTOM_FEATURE, 535 "bist_repeat_pattern", 0xffffffff); 536 537 if(bist_timer_us != 0xffffffff) { 538 info.bist_timer_us = bist_timer_us; 539 } 540 541 if(info.bist_timer_us == 0x0) { 542 /* Run according to Number of Actions */ 543 bist_info.bist_num_actions = info.bist_num_actions; 544 545 if (info.prbs_mode == 0x1) { 546 bist_info.pattern_mode |= SB2_DRAM_BIST_DATA_PATTERN_RANDOM_PRBS; 547 bist_info.bist_flags = 548 SB2_BIST_FLAGS_USE_RANDOM_SEED | SB2_BIST_FLAGS_BG_INTERLEAVE; 549 } 550 551 SOC_IF_ERROR_RETURN(sb2_bist_start_test(unit, ci, &bist_info)); 552 } else { 553 /* Run according to timeout */ 554 bist_info.bist_flags |= SB2_BIST_FLAGS_INFINITE; 555 SOC_IF_ERROR_RETURN(sb2_bist_start_test(unit, ci, &bist_info)); 556 557 sal_usleep(info.bist_timer_us); 558 559 bist_info.bist_flags = SB2_BIST_FLAGS_STOP; 560 SOC_IF_ERROR_RETURN(sb2_bist_start_test(unit, ci, &bist_info)); 561 } 562 return SOC_E_NONE; 563 } 564 565 566 int soc_sb2_and28_shmoo_drc_bist_conf_set(int unit, int ci, and28_bist_info_t info) 567 { 568 SOC_IF_ERROR_RETURN(soc_sb2_and28_shmoo_drc_bist_ci_conf_set(unit, (2 * ci), info)); 569 SOC_IF_ERROR_RETURN(soc_sb2_and28_shmoo_drc_bist_ci_conf_set(unit, ((2 * ci) + 1), info)); 570 return SOC_E_NONE; 571 572 } 573 int soc_sb2_and28_shmoo_drc_bist_err_cnt(int unit, int ci, 574 and28_bist_err_cnt_t *info) { 575 576 uint32 rval1, rval2, temp; 577 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, BISTERROROCCURREDr, (2 * ci), 0, &rval1)); 578 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, BISTERROROCCURREDr, ((2 * ci) + 1), 0, &rval2)); 579 temp = ((rval1 & 0xFFFF) & ((rval1 >> 16) & 0xFFFF)) | 580 (((rval2 & 0xFFFF) & ((rval2 >> 16) & 0xFFFF)) << 16); 581 info->bist_err_occur = temp; 582 583 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, BISTFULLMASKERRORCOUNTERr, (2 * ci), 0, &rval1)); 584 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, BISTFULLMASKERRORCOUNTERr, ((2 * ci) + 1), 0, &rval2)); 585 temp = rval1 + rval2; 586 if ((temp < rval1) || (temp < rval2)) { 587 /* To check whether temp has overflown */ 588 temp = 0xFFFFFFFF; 589 } 590 info->bist_full_err_cnt = temp; 591 592 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, BISTSINGLEBITMASKERRORCOUNTERr, (2 * ci), 0, &rval1)); 593 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, BISTSINGLEBITMASKERRORCOUNTERr, ((2 * ci) + 1), 0, &rval2)); 594 temp = rval1 + rval2; 595 if ((temp < rval1) || (temp < rval2)) { 596 /* To check whether temp has overflown */ 597 temp = 0xFFFFFFFF; 598 } 599 info->bist_single_err_cnt = temp; 600 601 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, BISTGLOBALERRORCOUNTERr, (2 * ci), 0, &rval1)); 602 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, BISTGLOBALERRORCOUNTERr, ((2 * ci) + 1), 0, &rval2)); 603 temp = rval1 + rval2; 604 if ((temp < rval1) || (temp < rval2)) { 605 /* To check whether temp has overflown */ 606 temp = 0xFFFFFFFF; 607 } 608 info->bist_global_err_cnt = temp; 609 610 return SOC_E_NONE; 611 } 612 613 int soc_sb2_and28_shmoo_dram_init(int unit, int ci, int phase) 614 { 615 uint32 rval; 616 617 if(phase != 0) { 618 LOG_INFO(BSL_LS_SOC_DDR, 619 (BSL_META_U(unit, 620 "Phase must be 0 for DDR3\n"))); 621 return SOC_E_PARAM; 622 } 623 624 SOC_IF_ERROR_RETURN(READ_CI_PHY_CONTROLr(unit, ci, &rval)); 625 soc_reg_field_set(unit, CI_PHY_CONTROLr, &rval, CKEf, 0); 626 soc_reg_field_set(unit, CI_PHY_CONTROLr, &rval, RST_Nf, 0); 627 SOC_IF_ERROR_RETURN(WRITE_CI_PHY_CONTROLr(unit, ci, rval)); 628 sal_usleep(2000); 629 630 SOC_IF_ERROR_RETURN(READ_CI_PHY_CONTROLr(unit, ci, &rval)); 631 soc_reg_field_set(unit, CI_PHY_CONTROLr, &rval, CKEf, 0); 632 soc_reg_field_set(unit, CI_PHY_CONTROLr, &rval, RST_Nf, 3); 633 SOC_IF_ERROR_RETURN(WRITE_CI_PHY_CONTROLr(unit, ci, rval)); 634 sal_usleep(2000); 635 636 SOC_IF_ERROR_RETURN(READ_CI_PHY_CONTROLr(unit, ci, &rval)); 637 soc_reg_field_set(unit, CI_PHY_CONTROLr, &rval, CKEf, 3); 638 soc_reg_field_set(unit, CI_PHY_CONTROLr, &rval, RST_Nf, 3); 639 soc_reg_field_set(unit, CI_PHY_CONTROLr, &rval, WARMSTARTf, 1); 640 SOC_IF_ERROR_RETURN(WRITE_CI_PHY_CONTROLr(unit, ci, rval)); 641 sal_usleep(2000); 642 643 return SOC_E_NONE; 644 } 645 646 int soc_sb2_ci_config(int unit, int ci) 647 { 648 uint32 rval; 649 sb2_req_grade_mem_set_set_t T0fgmss; 650 int freq_loc, grade_loc, row_loc; 651 652 freq_loc = _soc_ddr_sb2_phy_freqtoloc(SOC_DDR3_CLOCK_MHZ(unit)); 653 grade_loc = _soc_ddr_sb2_mem_gradetoloc(SOC_DDR3_MEM_GRADE(unit)); 654 655 if (freq_loc < 0) { 656 return SOC_E_INTERNAL; /* Unsupported Frequency */ 657 } 658 659 LOG_INFO(BSL_LS_SOC_DDR, 660 (BSL_META_U(unit, 661 "B01. Bring CI out of software reset\n"))); 662 663 /* CI Config register configurations. */ 664 LOG_INFO(BSL_LS_SOC_DDR, 665 (BSL_META_U(unit, 666 "B02. Set Strap and parameter per speed and grade\n"))); 667 668 _soc_ddr_sb2_phy_init_mem_set_wrapper(unit, &T0fgmss, freq_loc, grade_loc); 669 670 SOC_IF_ERROR_RETURN(READ_CI_CONFIG0r(unit, ci, &rval)); 671 soc_reg_field_set(unit, CI_CONFIG0r, &rval, TWLf, (ci & 0x1) ? \ 672 (T0fgmss.twl) : (T0fgmss.twl - 1)); 673 soc_reg_field_set(unit, CI_CONFIG0r, &rval, TWRf, T0fgmss.twr); 674 soc_reg_field_set(unit, CI_CONFIG0r, &rval, TRCf, T0fgmss.trc); 675 SOC_IF_ERROR_RETURN(WRITE_CI_CONFIG0r(unit, ci, rval)); 676 677 SOC_IF_ERROR_RETURN(READ_CI_CONFIG1r(unit, ci, &rval)); 678 soc_reg_field_set(unit, CI_CONFIG1r, &rval, RFIFO_ALMOST_FULL_THRESHOLDf, 679 T0fgmss.rfifo_afull); 680 soc_reg_field_set(unit, CI_CONFIG1r, &rval, RFIFO_FULL_THRESHOLDf, 681 T0fgmss.rfifo_full); 682 soc_reg_field_set(unit, CI_CONFIG1r, &rval, WFIFO_ALMOST_FULL_THRESHOLDf, 683 0x82); 684 soc_reg_field_set(unit, CI_CONFIG1r, &rval, WFIFO_FULL_THRESHOLDf, 685 0xF6); 686 SOC_IF_ERROR_RETURN(WRITE_CI_CONFIG1r(unit, ci, rval)); 687 688 SOC_IF_ERROR_RETURN(READ_CI_CONFIG2r(unit, ci, &rval)); 689 soc_reg_field_set(unit, CI_CONFIG2r, &rval, TRTWf, T0fgmss.trtw); 690 soc_reg_field_set(unit, CI_CONFIG2r, &rval, TWTRf, T0fgmss.twtr); 691 soc_reg_field_set(unit, CI_CONFIG2r, &rval, TFAWf, T0fgmss.tfaw); 692 soc_reg_field_set(unit, CI_CONFIG2r, &rval, TREAD_ENBf, 693 (ci & 0x1)?(T0fgmss.tread_enb-1):T0fgmss.tread_enb); 694 SOC_IF_ERROR_RETURN(WRITE_CI_CONFIG2r(unit, ci, rval)); 695 696 SOC_IF_ERROR_RETURN(READ_CI_CONFIG3r(unit, ci, &rval)); 697 soc_reg_field_set(unit, CI_CONFIG3r, &rval, BANK_UNAVAILABLE_WRf, 698 T0fgmss.bank_unavail_wr); 699 soc_reg_field_set(unit, CI_CONFIG3r, &rval, BANK_UNAVAILABLE_RDf, 700 T0fgmss.bank_unavail_rd); 701 soc_reg_field_set(unit, CI_CONFIG3r, &rval, RR_READf, T0fgmss.rr_read); 702 soc_reg_field_set(unit, CI_CONFIG3r, &rval, RR_WRITEf, T0fgmss.rr_write); 703 SOC_IF_ERROR_RETURN(WRITE_CI_CONFIG3r(unit, ci, rval)); 704 705 SOC_IF_ERROR_RETURN(READ_CI_CONFIG6r(unit, ci, &rval)); 706 707 row_loc = _soc_sb2_mem_rowstoloc(SOC_DDR3_NUM_ROWS(unit)); 708 soc_reg_field_set(unit, CI_CONFIG6r, &rval, TRFCf, T0fgmss.trfc[row_loc]); 709 soc_reg_field_set(unit, CI_CONFIG6r, &rval, TRP_READf, T0fgmss.trp_read); 710 soc_reg_field_set(unit, CI_CONFIG6r, &rval, TRP_WRITEf, T0fgmss.trp_write); 711 SOC_IF_ERROR_RETURN(WRITE_CI_CONFIG6r(unit, ci, rval)); 712 713 SOC_IF_ERROR_RETURN(READ_CI_CONFIG7r(unit, ci, &rval)); 714 soc_reg_field_set(unit, CI_CONFIG7r, &rval, TZQf, T0fgmss.tzq); 715 SOC_IF_ERROR_RETURN(WRITE_CI_CONFIG7r(unit, ci, rval)); 716 717 LOG_INFO(BSL_LS_SOC_DDR, 718 (BSL_META_U(unit, 719 "B03. Clear DDR Reset\n"))); 720 721 LOG_INFO(BSL_LS_SOC_DDR, 722 (BSL_META_U(unit, 723 "B04. Set config MR0, MR1, and MR2 registers\n"))); 724 725 SOC_IF_ERROR_RETURN(READ_CI_DDR_MR0r(unit, ci, &rval)); 726 soc_reg_field_set(unit, CI_DDR_MR0r, &rval, Af, T0fgmss.mr0); 727 SOC_IF_ERROR_RETURN(WRITE_CI_DDR_MR0r(unit, ci, rval)); 728 729 SOC_IF_ERROR_RETURN(READ_CI_DDR_MR1r(unit, ci, &rval)); 730 soc_reg_field_set(unit, CI_DDR_MR1r, &rval, Af, 0x10); 731 SOC_IF_ERROR_RETURN(WRITE_CI_DDR_MR1r(unit, ci, rval)); 732 733 SOC_IF_ERROR_RETURN(READ_CI_DDR_MR2r(unit, ci, &rval)); 734 soc_reg_field_set(unit, CI_DDR_MR2r, &rval, Af, T0fgmss.mr2); 735 SOC_IF_ERROR_RETURN(WRITE_CI_DDR_MR2r(unit, ci, rval)); 736 737 SOC_IF_ERROR_RETURN(READ_CI_CONFIG4r(unit, ci, &rval)); 738 soc_reg_field_set(unit, CI_CONFIG4r, &rval, REFRESH_INTERVALf, 0); 739 SOC_IF_ERROR_RETURN(WRITE_CI_CONFIG4r(unit, ci, rval)); 740 741 SOC_IF_ERROR_RETURN(READ_CI_CONFIG4r(unit, ci, &rval)); 742 soc_reg_field_set(unit, CI_CONFIG4r, &rval, REFRESH_INTERVALf, T0fgmss.refrate); 743 SOC_IF_ERROR_RETURN(WRITE_CI_CONFIG4r(unit, ci, rval)); 744 745 return SOC_E_NONE; 746 747 } 748 749 int soc_sb2_and28_post_shmoo_dram_init(int unit, int ci) 750 { 751 uint32 rval; 752 int ciCS, ciCM; 753 sal_usecs_t to_val; 754 soc_timeout_t to; 755 uint32 mr0, mr1, mr2, mr3; 756 757 if (SAL_BOOT_QUICKTURN) { 758 to_val = 10000000; /* 10 Sec */ 759 } else { 760 to_val = 50000; /* 50 mS */ 761 } 762 763 SOC_IF_ERROR_RETURN(READ_CI_PHY_CONTROLr(unit, ci, &rval)); 764 soc_reg_field_set(unit, CI_PHY_CONTROLr, &rval, CKEf, 3); 765 SOC_IF_ERROR_RETURN(WRITE_CI_PHY_CONTROLr(unit, ci, rval)); 766 sal_usleep(2000); 767 768 LOG_INFO(BSL_LS_SOC_DDR, 769 (BSL_META_U(unit, 770 "C12. Wait for Phy Ready\n"))); 771 772 soc_timeout_init(&to, to_val, 0); 773 do { 774 SOC_IF_ERROR_RETURN(READ_CI_PHY_CONTROLr(unit, ci, &rval)); 775 if (soc_reg_field_get(unit, CI_PHY_CONTROLr, rval, READYf)) { 776 break; 777 } 778 if (soc_timeout_check(&to)) { 779 LOG_ERROR(BSL_LS_SOC_COMMON, 780 (BSL_META_U(unit, 781 "CI%d: Timed out waiting for PHY Ready\n"), ci)); 782 return SOC_E_TIMEOUT; 783 } 784 } while (TRUE); 785 786 /* MR0-MR2 configurations */ 787 LOG_INFO(BSL_LS_SOC_DDR, 788 (BSL_META_U(unit, 789 "C13. CI DDR Init : MR0, MR1, MR2, and MR3 command\n"))); 790 dram0_clamshell_enable = soc_property_get(unit, spn_DRAM0_CLAMSHELL_ENABLE, 0); 791 dram1_clamshell_enable = soc_property_get(unit, spn_DRAM1_CLAMSHELL_ENABLE, 0); 792 793 if(dram0_clamshell_enable || dram1_clamshell_enable) { 794 LOG_INFO(BSL_LS_SOC_DDR, 795 (BSL_META_U(unit, 796 " Manual Init\n"))); 797 798 if(dram0_clamshell_enable) { 799 if(dram1_clamshell_enable) { 800 LOG_ERROR(BSL_LS_SOC_COMMON, 801 (BSL_META_U(unit, 802 "Illegal clam shell configuration\n"))); 803 return SOC_E_FAIL; 804 } 805 806 ciCM = 0; /* Only Even CIs Mirrored */ 807 ciCS = 1; /* Only Odd CIs Straight */ 808 } else { 809 ciCM = 1; /* Only Odd CIs Mirrored */ 810 ciCS = 0; /* Only Even CIs Straight */ 811 } 812 813 if (ci == ciCM) { 814 SOC_IF_ERROR_RETURN(READ_CI_DDR_MR0r(unit, ci, &rval)); 815 mr0 = soc_reg_field_get( unit, CI_DDR_MR0r, rval, Af ); 816 mr0 = (mr0 & 0x00007E07) | ((mr0 & 0x0A8) << 1) | ((mr0 & 0x150) >> 1); 817 soc_reg_field_set( unit, CI_DDR_MR0r, &mr0, Af, mr0 ); 818 soc_reg_field_set( unit, CI_DDR_MR0r, &mr0, BAf, 0 ); 819 820 SOC_IF_ERROR_RETURN(READ_CI_DDR_MR1r(unit, ci, &rval)); 821 mr2 = soc_reg_field_get( unit, CI_DDR_MR1r, rval, Af ); 822 mr2 = (mr2 & 0x00007E07) | ((mr2 & 0x0A8) << 1) | ((mr2 & 0x150) >> 1); 823 soc_reg_field_set( unit, CI_DDR_MR2r, &mr2, Af, mr2 ); 824 soc_reg_field_set( unit, CI_DDR_MR2r, &mr2, BAf, 2 ); 825 826 SOC_IF_ERROR_RETURN(READ_CI_DDR_MR2r(unit, ci, &rval)); 827 mr1 = soc_reg_field_get( unit, CI_DDR_MR2r, rval, Af ); 828 mr1 = (mr1 & 0x00007E07) | ((mr1 & 0x0A8) << 1) | ((mr1 & 0x150) >> 1); 829 soc_reg_field_set( unit, CI_DDR_MR1r, &mr1, Af, mr1 ); 830 soc_reg_field_set( unit, CI_DDR_MR1r, &mr1, BAf, 1 ); 831 832 SOC_IF_ERROR_RETURN(READ_CI_DDR_MR3r(unit, ci, &rval)); 833 mr3 = soc_reg_field_get( unit, CI_DDR_MR3r, rval, Af ); 834 mr3 = (mr3 & 0x00007E07) | ((mr3 & 0x0A8) << 1) | ((mr3 & 0x150) >> 1); 835 soc_reg_field_set( unit, CI_DDR_MR3r, &mr3, Af, mr3 ); 836 soc_reg_field_set( unit, CI_DDR_MR3r, &mr3, BAf, 3 ); 837 838 SOC_IF_ERROR_RETURN(WRITE_CI_DDR_MR0r(unit, ci, mr0)); 839 SOC_IF_ERROR_RETURN(WRITE_CI_DDR_MR1r(unit, ci, mr1)); 840 SOC_IF_ERROR_RETURN(WRITE_CI_DDR_MR2r(unit, ci, mr2)); 841 SOC_IF_ERROR_RETURN(WRITE_CI_DDR_MR3r(unit, ci, mr3)); 842 } 843 844 rval = 0; 845 soc_reg_field_set( unit, CI_MRS_CMDr, &rval, DONEf, 1 ); 846 soc_reg_field_set( unit, CI_MRS_CMDr, &rval, REQf, 1 ); 847 soc_reg_field_set( unit, CI_MRS_CMDr, &rval, MRS_CMDf, 0x0 ); 848 849 /* MR2 */ 850 if (ci == ciCS) { 851 soc_reg_field_set( unit, CI_MRS_CMDr, &rval, DEVICE_SELECTf, 0x1 ); 852 soc_reg_field_set( unit, CI_MRS_CMDr, &rval, MRS_SELECTf, 0x22); 853 SOC_IF_ERROR_RETURN( WRITE_CI_MRS_CMDr( unit, ci, rval) ); 854 } else { 855 soc_reg_field_set( unit, CI_MRS_CMDr, &rval, DEVICE_SELECTf, 0x2 ); 856 soc_reg_field_set( unit, CI_MRS_CMDr, &rval, MRS_SELECTf, 0x1 ); 857 SOC_IF_ERROR_RETURN( WRITE_CI_MRS_CMDr( unit, ci, rval) ); 858 } 859 860 /* MR3 */ 861 if (ci == ciCS) { 862 soc_reg_field_set( unit, CI_MRS_CMDr, &rval, DEVICE_SELECTf, 0x1 ); 863 soc_reg_field_set( unit, CI_MRS_CMDr, &rval, MRS_SELECTf, 0x3 ); 864 SOC_IF_ERROR_RETURN( WRITE_CI_MRS_CMDr( unit, ci, rval) ); 865 } else { 866 soc_reg_field_set( unit, CI_MRS_CMDr, &rval, DEVICE_SELECTf, 0x2 ); 867 soc_reg_field_set( unit, CI_MRS_CMDr, &rval, MRS_SELECTf, 0x3 ); 868 SOC_IF_ERROR_RETURN( WRITE_CI_MRS_CMDr( unit, ci, rval) ); 869 } 870 871 /* MR1 */ 872 if (ci == ciCS) { 873 soc_reg_field_set( unit, CI_MRS_CMDr, &rval, DEVICE_SELECTf, 0x1 ); 874 soc_reg_field_set( unit, CI_MRS_CMDr, &rval, MRS_SELECTf, 0x1 ); 875 SOC_IF_ERROR_RETURN( WRITE_CI_MRS_CMDr( unit, ci, rval) ); 876 } else { 877 soc_reg_field_set( unit, CI_MRS_CMDr, &rval, DEVICE_SELECTf, 0x2 ); 878 soc_reg_field_set( unit, CI_MRS_CMDr, &rval, MRS_SELECTf, 0x2 ); 879 SOC_IF_ERROR_RETURN( WRITE_CI_MRS_CMDr( unit, ci, rval) ); 880 } 881 882 /* MR0 */ 883 if (ci == ciCS) { 884 soc_reg_field_set( unit, CI_MRS_CMDr, &rval, DEVICE_SELECTf, 0x1 ); 885 soc_reg_field_set( unit, CI_MRS_CMDr, &rval, MRS_SELECTf, 0 ); 886 SOC_IF_ERROR_RETURN( WRITE_CI_MRS_CMDr( unit, ci, rval) ); 887 } else { 888 soc_reg_field_set( unit, CI_MRS_CMDr, &rval, DEVICE_SELECTf, 0x2 ); 889 soc_reg_field_set( unit, CI_MRS_CMDr, &rval, MRS_SELECTf, 0); 890 SOC_IF_ERROR_RETURN( WRITE_CI_MRS_CMDr( unit, ci, rval) ); 891 } 892 893 soc_reg_field_set( unit, CI_MRS_CMDr, &rval, DEVICE_SELECTf, 0x3 ); 894 soc_reg_field_set( unit, CI_MRS_CMDr, &rval, MRS_SELECTf, 0x3); 895 soc_reg_field_set( unit, CI_MRS_CMDr, &rval, MRS_CMDf, 0x3); 896 SOC_IF_ERROR_RETURN( WRITE_CI_MRS_CMDr( unit, ci, rval) ); 897 898 } else { 899 LOG_INFO(BSL_LS_SOC_DDR, 900 (BSL_META_U(unit, 901 " Auto Init\n"))); 902 903 SOC_IF_ERROR_RETURN(READ_CI_MRS_CMDr(unit, ci, &rval)); 904 soc_reg_field_set(unit, CI_MRS_CMDr, &rval, DEVICE_SELECTf, 3); 905 SOC_IF_ERROR_RETURN(WRITE_CI_MRS_CMDr(unit, ci, rval)); 906 907 SOC_IF_ERROR_RETURN(READ_CI_DDR_AUTOINITr(unit, ci, &rval)); 908 soc_reg_field_set(unit, CI_DDR_AUTOINITr, &rval, DONEf, 1); 909 soc_reg_field_set(unit, CI_DDR_AUTOINITr, &rval, STARTf, 1); 910 SOC_IF_ERROR_RETURN(WRITE_CI_DDR_AUTOINITr(unit, ci, rval)); 911 sal_usleep(1000); 912 913 soc_timeout_init(&to, to_val, 0); 914 do { 915 SOC_IF_ERROR_RETURN(READ_CI_DDR_AUTOINITr(unit, ci, &rval)); 916 if (soc_reg_field_get(unit, CI_DDR_AUTOINITr, rval, DONEf)) { 917 break; 918 } 919 if (soc_timeout_check(&to)) { 920 LOG_ERROR(BSL_LS_SOC_COMMON, 921 (BSL_META_U(unit, 922 "CI%d: Timed out DDR Init\n"), ci)); 923 return SOC_E_TIMEOUT; 924 } 925 } while (TRUE); 926 927 /* Delay for TZQ init */ 928 sal_usleep(5000); 929 } 930 931 /* Clear CI_ERROR */ 932 LOG_INFO(BSL_LS_SOC_DDR, 933 (BSL_META_U(unit, 934 "C14. Clear Read/Write FIFO errors\n"))); 935 936 rval = 0; 937 soc_reg_field_set(unit, CI_ERRORr, &rval, WFIFO_CTL_CORRECTED_ERRORf, 1); 938 soc_reg_field_set(unit, CI_ERRORr, &rval, WFIFO_CTL_UNCORRECTED_ERRORf, 1); 939 soc_reg_field_set(unit, CI_ERRORr, &rval, RFIFO_CTL_CORRECTED_ERRORf, 1); 940 soc_reg_field_set(unit, CI_ERRORr, &rval, RFIFO_CTL_UNCORRECTED_ERRORf, 1); 941 soc_reg_field_set(unit, CI_ERRORr, &rval, RFIFO_OVERFLOWf, 1); 942 soc_reg_field_set(unit, CI_ERRORr, &rval, WFIFO_OVERFLOWf, 1); 943 soc_reg_field_set(unit, CI_ERRORr, &rval, PHY_READY_EVENTf, 1); 944 SOC_IF_ERROR_RETURN(WRITE_CI_ERRORr(unit, ci, rval)); 945 946 return SOC_E_NONE; 947 } 948 949 /* Fill shmoo CB structure */ 950 static and28_shmoo_cbi_t sb2_shmoo_cbi = { 951 soc_sb2_and28_shmoo_phy_reg_read, 952 soc_sb2_and28_shmoo_phy_reg_write, 953 soc_sb2_and28_shmoo_phy_reg_modify, 954 soc_sb2_and28_shmoo_drc_bist_conf_set, 955 soc_sb2_and28_shmoo_drc_bist_err_cnt, 956 soc_sb2_and28_shmoo_dram_init 957 }; 958 959 int soc_saber2_and28_info_config(int unit, soc_sb2_and28_info_t *drc_info, 960 and28_shmoo_dram_info_t *sdi) { 961 int i, num_dram = 0; 962 963 /* Calculate dram bitmap from number of DDR memories */ 964 num_dram = soc_property_get(unit, spn_EXT_RAM_PRESENT, 0); 965 drc_info->dram_bitmap = 0; 966 for( i = 0; i < num_dram; i++ ){ 967 drc_info->dram_bitmap |= (1 << i); 968 } 969 sdi->dram_bitmap = drc_info->dram_bitmap; 970 sdi->interface_bitwidth = 16; 971 sdi->split_bus = 1; 972 973 drc_info->enable = (drc_info->dram_num == 0) ? FALSE : TRUE; 974 drc_info->auto_tune = soc_property_get(unit, spn_DDR3_AUTO_TUNE, 0); 975 976 drc_info->ref_clk_mhz = soc_property_get(unit, spn_SYNTH_DRAM_FREQ, 50); 977 sdi->ref_clk_mhz = drc_info->ref_clk_mhz; 978 drc_info->dram_freq = soc_property_get(unit, spn_DDR3_CLOCK_MHZ, 800); 979 980 drc_info->data_rate_mbps = (2 * drc_info->dram_freq); 981 982 if( drc_info->dram_freq == 667) { 983 drc_info->data_rate_mbps = drc_info->data_rate_mbps - 1; 984 } 985 986 sdi->data_rate_mbps = drc_info->data_rate_mbps; 987 988 #if 0 989 SOC_IF_ERROR_RETURN(_soc_dpp_drc_combo28_str_prop_ext_ram_type(unit, &drc_info->dram_type)); 990 #endif 991 drc_info->nof_columns = soc_property_get(unit, spn_EXT_RAM_COLUMNS, 1024); 992 drc_info->nof_rows = soc_property_get(unit, spn_EXT_RAM_ROWS, 32768); 993 drc_info->nof_banks = soc_property_get(unit, spn_EXT_RAM_BANKS, 0x8); 994 995 sdi->num_columns = drc_info->nof_columns; 996 sdi->num_rows = drc_info->nof_rows; 997 sdi->num_banks = drc_info->nof_banks; 998 sdi->num_bank_groups = 2; 999 1000 /* dramType and ctlType are constant for SB2 */ 1001 sdi->dram_type = SHMOO_AND28_DRAM_TYPE_DDR3; 1002 sdi->ctl_type = SHMOO_AND28_CTL_TYPE_1; 1003 1004 1005 drc_info->gear_down_mode = soc_property_get(unit, spn_EXT_RAM_GEAR_DOWN_MODE, 0x0); 1006 drc_info->abi = soc_property_get(unit, spn_EXT_RAM_ABI, 0x0); 1007 drc_info->write_dbi = soc_property_get(unit, spn_EXT_RAM_WRITE_DBI, 0x0); 1008 drc_info->read_dbi = soc_property_get(unit, spn_EXT_RAM_READ_DBI, 0x0); 1009 drc_info->cmd_par_latency = soc_property_get(unit, spn_EXT_RAM_CMD_PAR_LATENCY, 0x0); 1010 drc_info->write_crc = soc_property_get(unit, spn_EXT_RAM_WRITE_CRC, 0x0); 1011 drc_info->read_crc = soc_property_get(unit, spn_EXT_RAM_READ_CRC, 0x0); 1012 1013 drc_info->bist_enable = soc_property_suffix_num_get(unit, -1, spn_BIST_ENABLE, "dram", 0x1); 1014 1015 return SOC_E_NONE; 1016 } 1017 1018 int soc_sb2_ite_segment_gap_update(int unit, and28_shmoo_dram_info_t *sdi) 1019 { 1020 uint32 rval; 1021 int freq_loc, core_clk_loc; 1022 uint32 ref_clk_freq = 50; /* in MHz */ 1023 uint32 mdiv, ndiv; 1024 uint32 core_pll_clock; /* in MHz */ 1025 1026 SOC_IF_ERROR_RETURN(READ_TOP_SWITCH_FEATURE_ENABLE_2r(unit, &rval)); 1027 mdiv = soc_reg_field_get(unit, TOP_SWITCH_FEATURE_ENABLE_2r, rval, 1028 BOND_CORE_PLL_CH0_MDIVf); 1029 ndiv = soc_reg_field_get(unit, TOP_SWITCH_FEATURE_ENABLE_2r, rval, 1030 BOND_CORE_PLL_NDIV_INTf); 1031 core_pll_clock = _shr_div32r((ref_clk_freq * ndiv), mdiv); 1032 core_clk_loc = _soc_sb2_clktoloc(core_pll_clock); 1033 freq_loc = _soc_ddr_sb2_phy_freqtoloc(SOC_DDR3_CLOCK_MHZ(unit)); 1034 if((freq_loc < 0) || (core_clk_loc < 0)) { 1035 /* Invalid frequency */ 1036 return SOC_E_PARAM; 1037 } 1038 1039 SOC_IF_ERROR_RETURN(READ_ITE_SEGMENTS_GAPr(unit, &rval)); 1040 soc_reg_field_set(unit, ITE_SEGMENTS_GAPr, &rval, 1041 SEGMENTS6_GAPf, sb2_ite_segment_gap[freq_loc][core_clk_loc][0]); 1042 soc_reg_field_set(unit, ITE_SEGMENTS_GAPr, &rval, 1043 SEGMENTS5_GAPf, sb2_ite_segment_gap[freq_loc][core_clk_loc][1]); 1044 soc_reg_field_set(unit, ITE_SEGMENTS_GAPr, &rval, 1045 SEGMENTS4_GAPf, sb2_ite_segment_gap[freq_loc][core_clk_loc][2]); 1046 soc_reg_field_set(unit, ITE_SEGMENTS_GAPr, &rval, 1047 SEGMENTS3_GAPf, sb2_ite_segment_gap[freq_loc][core_clk_loc][3]); 1048 soc_reg_field_set(unit, ITE_SEGMENTS_GAPr, &rval, 1049 SEGMENTS2_GAPf, sb2_ite_segment_gap[freq_loc][core_clk_loc][4]); 1050 soc_reg_field_set(unit, ITE_SEGMENTS_GAPr, &rval, 1051 SEGMENTS1_GAPf, sb2_ite_segment_gap[freq_loc][core_clk_loc][5]); 1052 SOC_IF_ERROR_RETURN(WRITE_ITE_SEGMENTS_GAPr(unit, rval)); 1053 1054 return SOC_E_NONE; 1055 } 1056 1057 1058 int soc_sb2_and28_dram_init_reset(int unit) 1059 { 1060 uint32 rval; 1061 int ci = 0; 1062 and28_shmoo_dram_info_t sdi; 1063 soc_sb2_and28_info_t *drc_info; 1064 1065 sal_memset(&sdi, 0, sizeof(sdi)); 1066 1067 drc_info = sal_alloc(sizeof(soc_sb2_and28_info_t),"DRC info"); 1068 sal_memset(drc_info, 0, sizeof(soc_sb2_and28_info_t)); 1069 1070 /* Get drc_info parameters */ 1071 SOC_IF_ERROR_CLEAN_RETURN( 1072 soc_saber2_and28_info_config(unit, drc_info, &sdi), 1073 sal_free(drc_info)); 1074 1075 /* DRAM info set */ 1076 SOC_IF_ERROR_CLEAN_RETURN(soc_and28_shmoo_dram_info_set(unit, &sdi), 1077 sal_free(drc_info)); 1078 1079 /* Shmoo callback function registration */ 1080 SOC_IF_ERROR_CLEAN_RETURN( 1081 soc_and28_shmoo_interface_cb_register(unit, sb2_shmoo_cbi), 1082 sal_free(drc_info)); 1083 1084 for (ci=0; ci<2; ci++) { 1085 /* initiate master DRCs */ 1086 SOC_IF_ERROR_CLEAN_RETURN(soc_and28_shmoo_phy_init(unit, ci), 1087 sal_free(drc_info)); 1088 } 1089 1090 LOG_INFO(BSL_LS_SOC_DDR, 1091 (BSL_META_U(unit, 1092 "B01. Bring CI out of software reset\n"))); 1093 1094 for (ci=0; ci<2; ci++) { 1095 SOC_IF_ERROR_CLEAN_RETURN(READ_CI_RESETr(unit,ci,&rval), 1096 sal_free(drc_info)); 1097 soc_reg_field_set(unit, CI_RESETr, &rval, TREX2_DEBUG_ENABLEf, 0); 1098 soc_reg_field_set(unit, CI_RESETr, &rval, SW_RESETf, 0); 1099 SOC_IF_ERROR_CLEAN_RETURN(WRITE_CI_RESETr(unit,ci,rval), 1100 sal_free(drc_info)); 1101 sal_usleep(2000); 1102 } 1103 1104 sal_free(drc_info); 1105 return SOC_E_NONE; 1106 } 1107 int soc_sb2_and28_dram_init_config(int unit) 1108 { 1109 uint32 rval; 1110 int ci = 0; 1111 and28_shmoo_dram_info_t sdi; 1112 and28_shmoo_config_param_t config_param; 1113 soc_sb2_and28_info_t *drc_info; 1114 1115 sal_memset(&sdi, 0, sizeof(sdi)); 1116 sal_memset(&config_param, 0, sizeof(config_param)); 1117 1118 drc_info = sal_alloc(sizeof(soc_sb2_and28_info_t),"DRC info"); 1119 sal_memset(drc_info, 0, sizeof(soc_sb2_and28_info_t)); 1120 1121 /* Get drc_info parameters */ 1122 SOC_IF_ERROR_CLEAN_RETURN( 1123 soc_saber2_and28_info_config(unit, drc_info, &sdi), 1124 sal_free(drc_info)); 1125 1126 /* DRAM info set */ 1127 SOC_IF_ERROR_CLEAN_RETURN( 1128 soc_and28_shmoo_dram_info_set(unit, &sdi), 1129 sal_free(drc_info)); 1130 1131 for (ci=0; ci<2; ci++) { 1132 SOC_IF_ERROR_CLEAN_RETURN( 1133 soc_sb2_and28_shmoo_dram_init(unit, ci, 0), 1134 sal_free(drc_info)); 1135 SOC_IF_ERROR_CLEAN_RETURN( 1136 soc_sb2_ci_config(unit, ci), 1137 sal_free(drc_info)); 1138 SOC_IF_ERROR_CLEAN_RETURN( 1139 soc_sb2_and28_post_shmoo_dram_init(unit, ci), 1140 sal_free(drc_info)); 1141 1142 /* Config and release BIST */ 1143 LOG_INFO(BSL_LS_SOC_DDR, 1144 (BSL_META_U(unit, 1145 "C15. Config and Release BIST from reset\n"))); 1146 1147 rval = 0; 1148 soc_reg_field_set(unit, BISTGENERALCONFIGURATIONSr, 1149 &rval, NUMCOLSf, 2); 1150 SOC_IF_ERROR_CLEAN_RETURN( 1151 WRITE_BISTGENERALCONFIGURATIONSr(unit, ci, rval), 1152 sal_free(drc_info)); 1153 1154 SOC_IF_ERROR_CLEAN_RETURN( 1155 READ_BISTCONFIGr(unit, ci, &rval), sal_free(drc_info)); 1156 soc_reg_field_set(unit, BISTCONFIGr, &rval, BIST_RESETBf, 1); 1157 SOC_IF_ERROR_CLEAN_RETURN( 1158 WRITE_BISTCONFIGr(unit, ci, rval), sal_free(drc_info)); 1159 1160 } 1161 1162 SOC_IF_ERROR_CLEAN_RETURN( 1163 soc_sb2_ite_segment_gap_update(unit, &sdi), sal_free(drc_info)); 1164 1165 1166 ci=0; 1167 if (drc_info->auto_tune == 0x1) { 1168 SOC_IF_ERROR_CLEAN_RETURN(soc_and28_shmoo_ctl(unit, ci, -1, 0, 1169 SHMOO_AND28_ACTION_RUN, 1170 &(drc_info->shmoo_config_param[ci])), 1171 sal_free(drc_info)); 1172 } 1173 else { 1174 rval = SOC_E_NONE; 1175 /* restore from the config variables */ 1176 rval = soc_sb2_and28_dram_restorecfg(unit, 1177 &(drc_info->shmoo_config_param[ci])); 1178 if (rval == SOC_E_NONE){ 1179 rval = soc_and28_shmoo_ctl(unit, ci, -1, 0, 1180 SHMOO_AND28_ACTION_RESTORE, 1181 &(drc_info->shmoo_config_param[ci])); 1182 1183 if (rval == SOC_E_NONE) { 1184 LOG_CLI((BSL_META_U(unit, 1185 "DDR Tune Values Restored\n"))); 1186 } else { 1187 LOG_CLI((BSL_META_U(unit, 1188 "DDR Tune Values Restore Failed\n"))); 1189 } 1190 } 1191 else{ 1192 LOG_CLI((BSL_META_U(unit, 1193 "DDR Tune Values Restore Failed\n"))); 1194 } 1195 } 1196 1197 sal_free(drc_info); 1198 return SOC_E_NONE; 1199 } 1200 /* This function is used to store the and28_shmoo_config_param_t structure 1201 * into config variables. Should be used only form diag shell*/ 1202 int soc_sb2_and28_dram_savecfg(int unit, and28_shmoo_config_param_t *config_param) 1203 { 1204 char name_str[32], val_str[96]; 1205 uint64 value64; 1206 uint32 value32_lo = 0; 1207 uint32 value32_hi = 0; 1208 uint16 value16 = 0; 1209 uint8 value8 = 0; 1210 1211 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 1212 1213 if (soc_mem_config_set == NULL) { 1214 return SOC_E_UNAVAIL; 1215 } 1216 1217 if (config_param == NULL) { 1218 return SOC_E_PARAM; 1219 } 1220 1221 /* uint16 control_regs_ad[SHMOO_AND28_PHY_NOF_AD] */ 1222 value16 = (uint16) (*config_param).control_regs_ad[0]; 1223 value32_hi |= value16; 1224 value16 = 0; 1225 value32_hi <<= 16; 1226 1227 value16 = (uint16) (*config_param).control_regs_ad[1]; 1228 value32_hi |= value16; 1229 value16 = 0; 1230 1231 value16 = (uint16) (*config_param).control_regs_ad[2]; 1232 value32_lo |= value16; 1233 value16 = 0; 1234 value32_lo <<= 16; 1235 1236 value16 = (uint16) (*config_param).control_regs_ad[3]; 1237 value32_lo |= value16; 1238 value16 = 0; 1239 1240 COMPILER_64_SET(value64, value32_hi, value32_lo); 1241 sal_sprintf(name_str, "%s", spn_DDR3_TUNE_CTRL_VDL_AD00); 1242 soc_format_uint64(val_str, value64); 1243 if (soc_mem_config_set(name_str, val_str) < 0) { 1244 return SOC_E_MEMORY; 1245 } 1246 1247 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 1248 value16 = (uint16) (*config_param).control_regs_ad[4]; 1249 value32_hi |= value16; 1250 value16 = 0; 1251 value32_hi <<= 16; 1252 1253 value16 = (uint16) (*config_param).control_regs_ad[5]; 1254 value32_hi |= value16; 1255 value16 = 0; 1256 1257 value16 = (uint16) (*config_param).control_regs_ad[6]; 1258 value32_lo |= value16; 1259 value16 = 0; 1260 value32_lo <<= 16; 1261 1262 value16 = (uint16) (*config_param).control_regs_ad[7]; 1263 value32_lo |= value16; 1264 value16 = 0; 1265 1266 COMPILER_64_SET(value64, value32_hi, value32_lo); 1267 sal_sprintf(name_str, "%s", spn_DDR3_TUNE_CTRL_VDL_AD04); 1268 soc_format_uint64(val_str, value64); 1269 if (soc_mem_config_set(name_str, val_str) < 0) { 1270 return SOC_E_MEMORY; 1271 } 1272 1273 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 1274 value16 = (uint16) (*config_param).control_regs_ad[8]; 1275 value32_hi |= value16; 1276 value16 = 0; 1277 value32_hi <<= 16; 1278 1279 value16 = (uint16) (*config_param).control_regs_ad[9]; 1280 value32_hi |= value16; 1281 value16 = 0; 1282 1283 value16 = (uint16) (*config_param).control_regs_ad[10]; 1284 value32_lo |= value16; 1285 value16 = 0; 1286 value32_lo <<= 16; 1287 1288 value16 = (uint16) (*config_param).control_regs_ad[11]; 1289 value32_lo |= value16; 1290 value16 = 0; 1291 1292 sal_sprintf(name_str, "%s", spn_DDR3_TUNE_CTRL_VDL_AD08); 1293 COMPILER_64_SET(value64, value32_hi, value32_lo); 1294 soc_format_uint64(val_str, value64); 1295 if (soc_mem_config_set(name_str, val_str) < 0) { 1296 return SOC_E_MEMORY; 1297 } 1298 1299 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 1300 value16 = (uint16) (*config_param).control_regs_ad[12]; 1301 value32_hi |= value16; 1302 value16 = 0; 1303 value32_hi <<= 16; 1304 1305 value16 = (uint16) (*config_param).control_regs_ad[13]; 1306 value32_hi |= value16; 1307 value16 = 0; 1308 1309 value16 = (uint16) (*config_param).control_regs_ad[14]; 1310 value32_lo |= value16; 1311 value16 = 0; 1312 value32_lo <<= 16; 1313 1314 value16 = (uint16) (*config_param).control_regs_ad[15]; 1315 value32_lo |= value16; 1316 value16 = 0; 1317 1318 sal_sprintf(name_str, "%s", spn_DDR3_TUNE_CTRL_VDL_AD12); 1319 COMPILER_64_SET(value64, value32_hi, value32_lo); 1320 soc_format_uint64(val_str, value64); 1321 if (soc_mem_config_set(name_str, val_str) < 0) { 1322 return SOC_E_MEMORY; 1323 } 1324 /*END of uint16 control_regs_ad[SHMOO_AND28_PHY_NOF_AD] */ 1325 1326 /* uint16 control_regs_ba[SHMOO_AND28_PHY_NOF_BA] */ 1327 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 1328 value16 = (uint16) (*config_param).control_regs_ba[0]; 1329 value32_hi |= value16; 1330 value16 = 0; 1331 value32_hi <<= 16; 1332 1333 value16 = (uint16) (*config_param).control_regs_ba[1]; 1334 value32_hi |= value16; 1335 value16 = 0; 1336 1337 value16 = (uint16) (*config_param).control_regs_ba[2]; 1338 value32_lo |= value16; 1339 value16 = 0; 1340 1341 sal_sprintf(name_str, "%s", spn_DDR3_TUNE_CTRL_VDL_BA); 1342 COMPILER_64_SET(value64, value32_hi, value32_lo); 1343 soc_format_uint64(val_str, value64); 1344 if (soc_mem_config_set(name_str, val_str) < 0) { 1345 return SOC_E_MEMORY; 1346 } 1347 /* END of uint16 control_regs_ba[SHMOO_AND28_PHY_NOF_BA] */ 1348 1349 /* uint16 control_regs_aux[SHMOO_AND28_PHY_NOF_AUX] */ 1350 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 1351 value16 = (uint16) (*config_param).control_regs_aux[0]; 1352 value32_hi |= value16; 1353 value16 = 0; 1354 value32_hi <<= 16; 1355 1356 value16 = (uint16) (*config_param).control_regs_aux[1]; 1357 value32_hi |= value16; 1358 value16 = 0; 1359 1360 value16 = (uint16) (*config_param).control_regs_aux[2]; 1361 value32_lo |= value16; 1362 value16 = 0; 1363 1364 sal_sprintf(name_str, "%s", spn_DDR3_TUNE_CTRL_VDL_AUX); 1365 COMPILER_64_SET(value64, value32_hi, value32_lo); 1366 soc_format_uint64(val_str, value64); 1367 if (soc_mem_config_set(name_str, val_str) < 0) { 1368 return SOC_E_MEMORY; 1369 } 1370 /* END of uint16 control_regs_aux[SHMOO_AND28_PHY_NOF_AUX] */ 1371 1372 /* uint16 control_regs_cs[SHMOO_AND28_PHY_NOF_CS] */ 1373 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 1374 value16 = (uint16) (*config_param).control_regs_cs[0]; 1375 value32_hi |= value16; 1376 value16 = 0; 1377 value32_hi <<= 16; 1378 1379 value16 = (uint16) (*config_param).control_regs_cs[1]; 1380 value32_hi |= value16; 1381 value16 = 0; 1382 1383 sal_sprintf(name_str, "%s", spn_DDR3_TUNE_CTRL_VDL_CS); 1384 COMPILER_64_SET(value64, value32_hi, value32_lo); 1385 soc_format_uint64(val_str, value64); 1386 if (soc_mem_config_set(name_str, val_str) < 0) { 1387 return SOC_E_MEMORY; 1388 } 1389 /* END of uint16 control_regs_cs[SHMOO_AND28_PHY_NOF_CS] */ 1390 1391 /* 1392 * uint16 control_regs_par; 1393 * uint16 control_regs_ras_n; 1394 * uint16 control_regs_cas_n; 1395 * uint16 control_regs_cke; 1396 * uint16 control_regs_rst_n; 1397 * uint16 control_regs_odt; 1398 * uint16 control_regs_we_n; 1399 * uint32 control_regs_vref_dac_control;*/ 1400 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 1401 value16 = (uint16) (*config_param).control_regs_par; 1402 value32_hi |= value16; 1403 value16 = 0; 1404 sal_sprintf(name_str, "%s", spn_DDR3_TUNE_CTRL_VDL_PAR); 1405 COMPILER_64_SET(value64, value32_hi, value32_lo); 1406 soc_format_uint64(val_str, value64); 1407 if (soc_mem_config_set(name_str, val_str) < 0) { 1408 return SOC_E_MEMORY; 1409 } 1410 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 1411 value16 = (uint16) (*config_param).control_regs_ras_n; 1412 value32_hi |= value16; 1413 value16 = 0; 1414 sal_sprintf(name_str, "%s", spn_DDR3_TUNE_CTRL_VDL_RAS_N); 1415 COMPILER_64_SET(value64, value32_hi, value32_lo); 1416 soc_format_uint64(val_str, value64); 1417 if (soc_mem_config_set(name_str, val_str) < 0) { 1418 return SOC_E_MEMORY; 1419 } 1420 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 1421 value16 = (uint16) (*config_param).control_regs_cas_n; 1422 value32_hi |= value16; 1423 value16 = 0; 1424 sal_sprintf(name_str, "%s", spn_DDR3_TUNE_CTRL_VDL_CAS_N); 1425 COMPILER_64_SET(value64, value32_hi, value32_lo); 1426 soc_format_uint64(val_str, value64); 1427 if (soc_mem_config_set(name_str, val_str) < 0) { 1428 return SOC_E_MEMORY; 1429 } 1430 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 1431 value16 = (uint16) (*config_param).control_regs_cke; 1432 value32_hi |= value16; 1433 value16 = 0; 1434 sal_sprintf(name_str, "%s", spn_DDR3_TUNE_CTRL_VDL_CKE); 1435 COMPILER_64_SET(value64, value32_hi, value32_lo); 1436 soc_format_uint64(val_str, value64); 1437 if (soc_mem_config_set(name_str, val_str) < 0) { 1438 return SOC_E_MEMORY; 1439 } 1440 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 1441 value16 = (uint16) (*config_param).control_regs_rst_n; 1442 value32_hi |= value16; 1443 value16 = 0; 1444 sal_sprintf(name_str, "%s", spn_DDR3_TUNE_CTRL_VDL_RST_N); 1445 COMPILER_64_SET(value64, value32_hi, value32_lo); 1446 soc_format_uint64(val_str, value64); 1447 if (soc_mem_config_set(name_str, val_str) < 0) { 1448 return SOC_E_MEMORY; 1449 } 1450 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 1451 value16 = (uint16) (*config_param).control_regs_odt; 1452 value32_hi |= value16; 1453 value16 = 0; 1454 sal_sprintf(name_str, "%s", spn_DDR3_TUNE_CTRL_VDL_ODT); 1455 COMPILER_64_SET(value64, value32_hi, value32_lo); 1456 soc_format_uint64(val_str, value64); 1457 if (soc_mem_config_set(name_str, val_str) < 0) { 1458 return SOC_E_MEMORY; 1459 } 1460 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 1461 value16 = (uint16) (*config_param).control_regs_we_n; 1462 value32_hi |= value16; 1463 value16 = 0; 1464 sal_sprintf(name_str, "%s", spn_DDR3_TUNE_CTRL_VDL_WE_N); 1465 COMPILER_64_SET(value64, value32_hi, value32_lo); 1466 soc_format_uint64(val_str, value64); 1467 if (soc_mem_config_set(name_str, val_str) < 0) { 1468 return SOC_E_MEMORY; 1469 } 1470 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 1471 value32_hi = (uint32) (*config_param).control_regs_vref_dac_control; 1472 sal_sprintf(name_str, "%s", spn_DDR3_TUNE_CTRL_VREF_DAC); 1473 COMPILER_64_SET(value64, value32_hi, value32_lo); 1474 soc_format_uint64(val_str, value64); 1475 if (soc_mem_config_set(name_str, val_str) < 0) { 1476 return SOC_E_MEMORY; 1477 } 1478 1479 /* END of uint16 control_regs_cs[SHMOO_AND28_PHY_NOF_CS] */ 1480 1481 /* uint16 wr_vdl_dqsp[SHMOO_AND28_BYTES_PER_INTERFACE] */ 1482 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 1483 value16 = (uint16) (*config_param).wr_vdl_dqsp[0]; 1484 value32_hi |= value16; 1485 value16 = 0; 1486 value32_hi <<= 16; 1487 1488 value16 = (uint16) (*config_param).wr_vdl_dqsp[1]; 1489 value32_hi |= value16; 1490 value16 = 0; 1491 1492 value16 = (uint16) (*config_param).wr_vdl_dqsp[2]; 1493 value32_lo |= value16; 1494 value16 = 0; 1495 value32_lo <<= 16; 1496 1497 value16 = (uint16) (*config_param).wr_vdl_dqsp[3]; 1498 value32_lo |= value16; 1499 value16 = 0; 1500 1501 sal_sprintf(name_str, "%s", spn_DDR3_TUNE_WR_VDL_DQSP); 1502 COMPILER_64_SET(value64, value32_hi, value32_lo); 1503 soc_format_uint64(val_str, value64); 1504 if (soc_mem_config_set(name_str, val_str) < 0) { 1505 return SOC_E_MEMORY; 1506 } 1507 /* END of uint16 wr_vdl_dqsp[SHMOO_AND28_BYTES_PER_INTERFACE] */ 1508 1509 /* uint16 wr_vdl_dqsn[SHMOO_AND28_BYTES_PER_INTERFACE] */ 1510 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 1511 value16 = (uint16) (*config_param).wr_vdl_dqsn[0]; 1512 value32_hi |= value16; 1513 value16 = 0; 1514 value32_hi <<= 16; 1515 1516 value16 = (uint16) (*config_param).wr_vdl_dqsn[1]; 1517 value32_hi |= value16; 1518 value16 = 0; 1519 1520 value16 = (uint16) (*config_param).wr_vdl_dqsn[2]; 1521 value32_lo |= value16; 1522 value16 = 0; 1523 value32_lo <<= 16; 1524 1525 value16 = (uint16) (*config_param).wr_vdl_dqsn[3]; 1526 value32_lo |= value16; 1527 value16 = 0; 1528 1529 sal_sprintf(name_str, "%s", spn_DDR3_TUNE_WR_VDL_DQSN); 1530 COMPILER_64_SET(value64, value32_hi, value32_lo); 1531 soc_format_uint64(val_str, value64); 1532 if (soc_mem_config_set(name_str, val_str) < 0) { 1533 return SOC_E_MEMORY; 1534 } 1535 /* END of uint16 wr_vdl_dqsn[SHMOO_AND28_BYTES_PER_INTERFACE] */ 1536 1537 /* uint16 wr_vdl_dqsn[SHMOO_AND28_BYTES_PER_INTERFACE] */ 1538 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 1539 value16 = (uint16) (*config_param).wr_vdl_dqsn[0]; 1540 value32_hi |= value16; 1541 value16 = 0; 1542 value32_hi <<= 16; 1543 1544 value16 = (uint16) (*config_param).wr_vdl_dqsn[1]; 1545 value32_hi |= value16; 1546 value16 = 0; 1547 1548 value16 = (uint16) (*config_param).wr_vdl_dqsn[2]; 1549 value32_lo |= value16; 1550 value16 = 0; 1551 value32_lo <<= 16; 1552 1553 value16 = (uint16) (*config_param).wr_vdl_dqsn[3]; 1554 value32_lo |= value16; 1555 value16 = 0; 1556 1557 sal_sprintf(name_str, "%s", spn_DDR3_TUNE_WR_VDL_DQSN); 1558 COMPILER_64_SET(value64, value32_hi, value32_lo); 1559 soc_format_uint64(val_str, value64); 1560 if (soc_mem_config_set(name_str, val_str) < 0) { 1561 return SOC_E_MEMORY; 1562 } 1563 /*END of uint16 wr_vdl_dqsn[SHMOO_AND28_BYTES_PER_INTERFACE] */ 1564 1565 /* uint16 wr_vdl_dq[SHMOO_AND28_BYTES_PER_INTERFACE][SHMOO_AND28_BYTE] */ 1566 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 1567 value16 = (uint16) (*config_param).wr_vdl_dq[0][0]; 1568 value32_hi |= value16; 1569 value16 = 0; 1570 value32_hi <<= 16; 1571 1572 value16 = (uint16) (*config_param).wr_vdl_dq[0][1]; 1573 value32_hi |= value16; 1574 value16 = 0; 1575 1576 value16 = (uint16) (*config_param).wr_vdl_dq[0][2]; 1577 value32_lo |= value16; 1578 value16 = 0; 1579 value32_lo <<= 16; 1580 1581 value16 = (uint16) (*config_param).wr_vdl_dq[0][3]; 1582 value32_lo |= value16; 1583 value16 = 0; 1584 1585 sal_sprintf(name_str, "%s", spn_DDR3_TUNE_WR_VDL_DQ0_BL0); 1586 COMPILER_64_SET(value64, value32_hi, value32_lo); 1587 soc_format_uint64(val_str, value64); 1588 if (soc_mem_config_set(name_str, val_str) < 0) { 1589 return SOC_E_MEMORY; 1590 } 1591 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 1592 value16 = (uint16) (*config_param).wr_vdl_dq[0][4]; 1593 value32_hi |= value16; 1594 value16 = 0; 1595 value32_hi <<= 16; 1596 1597 value16 = (uint16) (*config_param).wr_vdl_dq[0][5]; 1598 value32_hi |= value16; 1599 value16 = 0; 1600 1601 value16 = (uint16) (*config_param).wr_vdl_dq[0][6]; 1602 value32_lo |= value16; 1603 value16 = 0; 1604 value32_lo <<= 16; 1605 1606 value16 = (uint16) (*config_param).wr_vdl_dq[0][7]; 1607 value32_lo |= value16; 1608 value16 = 0; 1609 1610 sal_sprintf(name_str, "%s", spn_DDR3_TUNE_WR_VDL_DQ4_BL0); 1611 COMPILER_64_SET(value64, value32_hi, value32_lo); 1612 soc_format_uint64(val_str, value64); 1613 if (soc_mem_config_set(name_str, val_str) < 0) { 1614 return SOC_E_MEMORY; 1615 } 1616 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 1617 value16 = (uint16) (*config_param).wr_vdl_dq[1][0]; 1618 value32_hi |= value16; 1619 value16 = 0; 1620 value32_hi <<= 16; 1621 1622 value16 = (uint16) (*config_param).wr_vdl_dq[1][1]; 1623 value32_hi |= value16; 1624 value16 = 0; 1625 1626 value16 = (uint16) (*config_param).wr_vdl_dq[1][2]; 1627 value32_lo |= value16; 1628 value16 = 0; 1629 value32_lo <<= 16; 1630 1631 value16 = (uint16) (*config_param).wr_vdl_dq[1][3]; 1632 value32_lo |= value16; 1633 value16 = 0; 1634 1635 sal_sprintf(name_str, "%s", spn_DDR3_TUNE_WR_VDL_DQ0_BL1); 1636 COMPILER_64_SET(value64, value32_hi, value32_lo); 1637 soc_format_uint64(val_str, value64); 1638 if (soc_mem_config_set(name_str, val_str) < 0) { 1639 return SOC_E_MEMORY; 1640 } 1641 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 1642 value16 = (uint16) (*config_param).wr_vdl_dq[1][4]; 1643 value32_hi |= value16; 1644 value16 = 0; 1645 value32_hi <<= 16; 1646 1647 value16 = (uint16) (*config_param).wr_vdl_dq[1][5]; 1648 value32_hi |= value16; 1649 value16 = 0; 1650 1651 value16 = (uint16) (*config_param).wr_vdl_dq[1][6]; 1652 value32_lo |= value16; 1653 value16 = 0; 1654 value32_lo <<= 16; 1655 1656 value16 = (uint16) (*config_param).wr_vdl_dq[1][7]; 1657 value32_lo |= value16; 1658 value16 = 0; 1659 1660 sal_sprintf(name_str, "%s", spn_DDR3_TUNE_WR_VDL_DQ4_BL1); 1661 COMPILER_64_SET(value64, value32_hi, value32_lo); 1662 soc_format_uint64(val_str, value64); 1663 if (soc_mem_config_set(name_str, val_str) < 0) { 1664 return SOC_E_MEMORY; 1665 } 1666 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 1667 value16 = (uint16) (*config_param).wr_vdl_dq[2][0]; 1668 value32_hi |= value16; 1669 value16 = 0; 1670 value32_hi <<= 16; 1671 1672 value16 = (uint16) (*config_param).wr_vdl_dq[2][1]; 1673 value32_hi |= value16; 1674 value16 = 0; 1675 1676 value16 = (uint16) (*config_param).wr_vdl_dq[2][2]; 1677 value32_lo |= value16; 1678 value16 = 0; 1679 value32_lo <<= 16; 1680 1681 value16 = (uint16) (*config_param).wr_vdl_dq[2][3]; 1682 value32_lo |= value16; 1683 value16 = 0; 1684 1685 sal_sprintf(name_str, "%s", spn_DDR3_TUNE_WR_VDL_DQ0_BL2); 1686 COMPILER_64_SET(value64, value32_hi, value32_lo); 1687 soc_format_uint64(val_str, value64); 1688 if (soc_mem_config_set(name_str, val_str) < 0) { 1689 return SOC_E_MEMORY; 1690 } 1691 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 1692 value16 = (uint16) (*config_param).wr_vdl_dq[2][4]; 1693 value32_hi |= value16; 1694 value16 = 0; 1695 value32_hi <<= 16; 1696 1697 value16 = (uint16) (*config_param).wr_vdl_dq[2][5]; 1698 value32_hi |= value16; 1699 value16 = 0; 1700 1701 value16 = (uint16) (*config_param).wr_vdl_dq[2][6]; 1702 value32_lo |= value16; 1703 value16 = 0; 1704 value32_lo <<= 16; 1705 1706 value16 = (uint16) (*config_param).wr_vdl_dq[2][7]; 1707 value32_lo |= value16; 1708 value16 = 0; 1709 1710 sal_sprintf(name_str, "%s", spn_DDR3_TUNE_WR_VDL_DQ4_BL2); 1711 COMPILER_64_SET(value64, value32_hi, value32_lo); 1712 soc_format_uint64(val_str, value64); 1713 if (soc_mem_config_set(name_str, val_str) < 0) { 1714 return SOC_E_MEMORY; 1715 } 1716 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 1717 value16 = (uint16) (*config_param).wr_vdl_dq[3][0]; 1718 value32_hi |= value16; 1719 value16 = 0; 1720 value32_hi <<= 16; 1721 1722 value16 = (uint16) (*config_param).wr_vdl_dq[3][1]; 1723 value32_hi |= value16; 1724 value16 = 0; 1725 1726 value16 = (uint16) (*config_param).wr_vdl_dq[3][2]; 1727 value32_lo |= value16; 1728 value16 = 0; 1729 value32_lo <<= 16; 1730 1731 value16 = (uint16) (*config_param).wr_vdl_dq[3][3]; 1732 value32_lo |= value16; 1733 value16 = 0; 1734 1735 sal_sprintf(name_str, "%s", spn_DDR3_TUNE_WR_VDL_DQ0_BL3); 1736 COMPILER_64_SET(value64, value32_hi, value32_lo); 1737 soc_format_uint64(val_str, value64); 1738 if (soc_mem_config_set(name_str, val_str) < 0) { 1739 return SOC_E_MEMORY; 1740 } 1741 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 1742 value16 = (uint16) (*config_param).wr_vdl_dq[3][4]; 1743 value32_hi |= value16; 1744 value16 = 0; 1745 value32_hi <<= 16; 1746 1747 value16 = (uint16) (*config_param).wr_vdl_dq[3][5]; 1748 value32_hi |= value16; 1749 value16 = 0; 1750 1751 value16 = (uint16) (*config_param).wr_vdl_dq[3][6]; 1752 value32_lo |= value16; 1753 value16 = 0; 1754 value32_lo <<= 16; 1755 1756 value16 = (uint16) (*config_param).wr_vdl_dq[3][7]; 1757 value32_lo |= value16; 1758 value16 = 0; 1759 1760 sal_sprintf(name_str, "%s", spn_DDR3_TUNE_WR_VDL_DQ4_BL3); 1761 COMPILER_64_SET(value64, value32_hi, value32_lo); 1762 soc_format_uint64(val_str, value64); 1763 if (soc_mem_config_set(name_str, val_str) < 0) { 1764 return SOC_E_MEMORY; 1765 } 1766 /* END of uint16 wr_vdl_dq[SHMOO_AND28_BYTES_PER_INTERFACE][SHMOO_AND28_BYTE]; */ 1767 1768 /* uint16 wr_vdl_dm[SHMOO_AND28_BYTES_PER_INTERFACE] */ 1769 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 1770 value16 = (uint16) (*config_param).wr_vdl_dm[0]; 1771 value32_hi |= value16; 1772 value16 = 0; 1773 value32_hi <<= 16; 1774 1775 value16 = (uint16) (*config_param).wr_vdl_dm[1]; 1776 value32_hi |= value16; 1777 value16 = 0; 1778 1779 value16 = (uint16) (*config_param).wr_vdl_dm[2]; 1780 value32_lo |= value16; 1781 value16 = 0; 1782 value32_lo <<= 16; 1783 1784 value16 = (uint16) (*config_param).wr_vdl_dm[3]; 1785 value32_lo |= value16; 1786 value16 = 0; 1787 1788 sal_sprintf(name_str, "%s", spn_DDR3_TUNE_WR_VDL_DM); 1789 COMPILER_64_SET(value64, value32_hi, value32_lo); 1790 soc_format_uint64(val_str, value64); 1791 if (soc_mem_config_set(name_str, val_str) < 0) { 1792 return SOC_E_MEMORY; 1793 } 1794 /*END of uint16 .wr_vdl_dm[SHMOO_AND28_BYTES_PER_INTERFACE] */ 1795 1796 /* uint16 wr_vdl_edc[SHMOO_AND28_BYTES_PER_INTERFACE] */ 1797 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 1798 value16 = (uint16) (*config_param).wr_vdl_edc[0]; 1799 value32_hi |= value16; 1800 value16 = 0; 1801 value32_hi <<= 16; 1802 1803 value16 = (uint16) (*config_param).wr_vdl_edc[1]; 1804 value32_hi |= value16; 1805 value16 = 0; 1806 1807 value16 = (uint16) (*config_param).wr_vdl_edc[2]; 1808 value32_lo |= value16; 1809 value16 = 0; 1810 value32_lo <<= 16; 1811 1812 value16 = (uint16) (*config_param).wr_vdl_edc[3]; 1813 value32_lo |= value16; 1814 value16 = 0; 1815 1816 sal_sprintf(name_str, "%s", spn_DDR3_TUNE_WR_VDL_EDC); 1817 COMPILER_64_SET(value64, value32_hi, value32_lo); 1818 soc_format_uint64(val_str, value64); 1819 if (soc_mem_config_set(name_str, val_str) < 0) { 1820 return SOC_E_MEMORY; 1821 } 1822 /*END of uint16 wr_vdl_edc[SHMOO_AND28_BYTES_PER_INTERFACE] */ 1823 1824 /* uint8 wr_chan_dly_cyc[SHMOO_AND28_BYTES_PER_INTERFACE] */ 1825 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 1826 value8 = (uint8) (*config_param).wr_chan_dly_cyc[0]; 1827 value32_hi |= value8; 1828 value8 = 0; 1829 value32_hi <<= 8; 1830 1831 value8 = (uint8) (*config_param).wr_chan_dly_cyc[1]; 1832 value32_hi |= value8; 1833 value8 = 0; 1834 value32_hi <<= 8; 1835 1836 value8 = (uint8) (*config_param).wr_chan_dly_cyc[2]; 1837 value32_hi |= value8; 1838 value8 = 0; 1839 value32_hi <<= 8; 1840 1841 value8 = (uint8) (*config_param).wr_chan_dly_cyc[3]; 1842 value32_hi |= value8; 1843 value8 = 0; 1844 1845 sal_sprintf(name_str, "%s", spn_DDR3_TUNE_WR_CHAN_DLY_CYC); 1846 COMPILER_64_SET(value64, value32_hi, value32_lo); 1847 soc_format_uint64(val_str, value64); 1848 if (soc_mem_config_set(name_str, val_str) < 0) { 1849 return SOC_E_MEMORY; 1850 } 1851 /*END of uint16 wr_chan_dly_cyc[SHMOO_AND28_BYTES_PER_INTERFACE] */ 1852 1853 /* uint16 rd_vdl_dqsp[SHMOO_AND28_BYTES_PER_INTERFACE] */ 1854 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 1855 value16 = (uint16) (*config_param).rd_vdl_dqsp[0]; 1856 value32_hi |= value16; 1857 value16 = 0; 1858 value32_hi <<= 16; 1859 1860 value16 = (uint16) (*config_param).rd_vdl_dqsp[1]; 1861 value32_hi |= value16; 1862 value16 = 0; 1863 1864 value16 = (uint16) (*config_param).rd_vdl_dqsp[2]; 1865 value32_lo |= value16; 1866 value16 = 0; 1867 value32_lo <<= 16; 1868 1869 value16 = (uint16) (*config_param).rd_vdl_dqsp[3]; 1870 value32_lo |= value16; 1871 value16 = 0; 1872 1873 sal_sprintf(name_str, "%s", spn_DDR3_TUNE_RD_VDL_DQSP); 1874 COMPILER_64_SET(value64, value32_hi, value32_lo); 1875 soc_format_uint64(val_str, value64); 1876 if (soc_mem_config_set(name_str, val_str) < 0) { 1877 return SOC_E_MEMORY; 1878 } 1879 /*END of uint16 rd_vdl_dqsp[SHMOO_AND28_BYTES_PER_INTERFACE] */ 1880 1881 /* uint16 rd_vdl_dqsn[SHMOO_AND28_BYTES_PER_INTERFACE] */ 1882 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 1883 value16 = (uint16) (*config_param).rd_vdl_dqsn[0]; 1884 value32_hi |= value16; 1885 value16 = 0; 1886 value32_hi <<= 16; 1887 1888 value16 = (uint16) (*config_param).rd_vdl_dqsn[1]; 1889 value32_hi |= value16; 1890 value16 = 0; 1891 1892 value16 = (uint16) (*config_param).rd_vdl_dqsn[2]; 1893 value32_lo |= value16; 1894 value16 = 0; 1895 value32_lo <<= 16; 1896 1897 value16 = (uint16) (*config_param).rd_vdl_dqsn[3]; 1898 value32_lo |= value16; 1899 value16 = 0; 1900 1901 sal_sprintf(name_str, "%s", spn_DDR3_TUNE_RD_VDL_DQSN); 1902 COMPILER_64_SET(value64, value32_hi, value32_lo); 1903 soc_format_uint64(val_str, value64); 1904 if (soc_mem_config_set(name_str, val_str) < 0) { 1905 return SOC_E_MEMORY; 1906 } 1907 /*END of uint16 rd_vdl_dqsn[SHMOO_AND28_BYTES_PER_INTERFACE] */ 1908 1909 /* uint16 rd_vdl_dqp[SHMOO_AND28_BYTES_PER_INTERFACE][SHMOO_AND28_BYTE] */ 1910 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 1911 value16 = (uint16) (*config_param).rd_vdl_dqp[0][0]; 1912 value32_hi |= value16; 1913 value16 = 0; 1914 value32_hi <<= 16; 1915 1916 value16 = (uint16) (*config_param).rd_vdl_dqp[0][1]; 1917 value32_hi |= value16; 1918 value16 = 0; 1919 1920 value16 = (uint16) (*config_param).rd_vdl_dqp[0][2]; 1921 value32_lo |= value16; 1922 value16 = 0; 1923 value32_lo <<= 16; 1924 1925 value16 = (uint16) (*config_param).rd_vdl_dqp[0][3]; 1926 value32_lo |= value16; 1927 value16 = 0; 1928 1929 COMPILER_64_SET(value64, value32_hi, value32_lo); 1930 1931 sal_sprintf(name_str, "%s", spn_DDR3_TUNE_RD_VDL_DQP0_BL0); 1932 soc_format_uint64(val_str, value64); 1933 if (soc_mem_config_set(name_str, val_str) < 0) { 1934 return SOC_E_MEMORY; 1935 } 1936 1937 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 1938 value16 = (uint16) (*config_param).rd_vdl_dqp[0][4]; 1939 value32_hi |= value16; 1940 value16 = 0; 1941 value32_hi <<= 16; 1942 1943 value16 = (uint16) (*config_param).rd_vdl_dqp[0][5]; 1944 value32_hi |= value16; 1945 value16 = 0; 1946 1947 value16 = (uint16) (*config_param).rd_vdl_dqp[0][6]; 1948 value32_lo |= value16; 1949 value16 = 0; 1950 value32_lo <<= 16; 1951 1952 value16 = (uint16) (*config_param).rd_vdl_dqp[0][7]; 1953 value32_lo |= value16; 1954 value16 = 0; 1955 1956 sal_sprintf(name_str, "%s", spn_DDR3_TUNE_RD_VDL_DQP4_BL0); 1957 COMPILER_64_SET(value64, value32_hi, value32_lo); 1958 soc_format_uint64(val_str, value64); 1959 if (soc_mem_config_set(name_str, val_str) < 0) { 1960 return SOC_E_MEMORY; 1961 } 1962 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 1963 value16 = (uint16) (*config_param).rd_vdl_dqp[1][0]; 1964 value32_hi |= value16; 1965 value16 = 0; 1966 value32_hi <<= 16; 1967 1968 value16 = (uint16) (*config_param).rd_vdl_dqp[1][1]; 1969 value32_hi |= value16; 1970 value16 = 0; 1971 1972 value16 = (uint16) (*config_param).rd_vdl_dqp[1][2]; 1973 value32_lo |= value16; 1974 value16 = 0; 1975 value32_lo <<= 16; 1976 1977 value16 = (uint16) (*config_param).rd_vdl_dqp[1][3]; 1978 value32_lo |= value16; 1979 value16 = 0; 1980 1981 sal_sprintf(name_str, "%s", spn_DDR3_TUNE_RD_VDL_DQP0_BL1); 1982 COMPILER_64_SET(value64, value32_hi, value32_lo); 1983 soc_format_uint64(val_str, value64); 1984 if (soc_mem_config_set(name_str, val_str) < 0) { 1985 return SOC_E_MEMORY; 1986 } 1987 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 1988 value16 = (uint16) (*config_param).rd_vdl_dqp[1][4]; 1989 value32_hi |= value16; 1990 value16 = 0; 1991 value32_hi <<= 16; 1992 1993 value16 = (uint16) (*config_param).rd_vdl_dqp[1][5]; 1994 value32_hi |= value16; 1995 value16 = 0; 1996 1997 value16 = (uint16) (*config_param).rd_vdl_dqp[1][6]; 1998 value32_lo |= value16; 1999 value16 = 0; 2000 value32_lo <<= 16; 2001 2002 value16 = (uint16) (*config_param).rd_vdl_dqp[1][7]; 2003 value32_lo |= value16; 2004 value16 = 0; 2005 2006 sal_sprintf(name_str, "%s", spn_DDR3_TUNE_RD_VDL_DQP4_BL1); 2007 COMPILER_64_SET(value64, value32_hi, value32_lo); 2008 soc_format_uint64(val_str, value64); 2009 if (soc_mem_config_set(name_str, val_str) < 0) { 2010 return SOC_E_MEMORY; 2011 } 2012 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 2013 value16 = (uint16) (*config_param).rd_vdl_dqp[2][0]; 2014 value32_hi |= value16; 2015 value16 = 0; 2016 value32_hi <<= 16; 2017 2018 value16 = (uint16) (*config_param).rd_vdl_dqp[2][1]; 2019 value32_hi |= value16; 2020 value16 = 0; 2021 2022 value16 = (uint16) (*config_param).rd_vdl_dqp[2][2]; 2023 value32_lo |= value16; 2024 value16 = 0; 2025 value32_lo <<= 16; 2026 2027 value16 = (uint16) (*config_param).rd_vdl_dqp[2][3]; 2028 value32_lo |= value16; 2029 value16 = 0; 2030 2031 sal_sprintf(name_str, "%s", spn_DDR3_TUNE_RD_VDL_DQP0_BL2); 2032 COMPILER_64_SET(value64, value32_hi, value32_lo); 2033 soc_format_uint64(val_str, value64); 2034 if (soc_mem_config_set(name_str, val_str) < 0) { 2035 return SOC_E_MEMORY; 2036 } 2037 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 2038 value16 = (uint16) (*config_param).rd_vdl_dqp[2][4]; 2039 value32_hi |= value16; 2040 value16 = 0; 2041 value32_hi <<= 16; 2042 2043 value16 = (uint16) (*config_param).rd_vdl_dqp[2][5]; 2044 value32_hi |= value16; 2045 value16 = 0; 2046 2047 value16 = (uint16) (*config_param).rd_vdl_dqp[2][6]; 2048 value32_lo |= value16; 2049 value16 = 0; 2050 value32_lo <<= 16; 2051 2052 value16 = (uint16) (*config_param).rd_vdl_dqp[2][7]; 2053 value32_lo |= value16; 2054 value16 = 0; 2055 2056 sal_sprintf(name_str, "%s", spn_DDR3_TUNE_RD_VDL_DQP4_BL2); 2057 COMPILER_64_SET(value64, value32_hi, value32_lo); 2058 soc_format_uint64(val_str, value64); 2059 if (soc_mem_config_set(name_str, val_str) < 0) { 2060 return SOC_E_MEMORY; 2061 } 2062 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 2063 value16 = (uint16) (*config_param).rd_vdl_dqp[3][0]; 2064 value32_hi |= value16; 2065 value16 = 0; 2066 value32_hi <<= 16; 2067 2068 value16 = (uint16) (*config_param).rd_vdl_dqp[3][1]; 2069 value32_hi |= value16; 2070 value16 = 0; 2071 2072 value16 = (uint16) (*config_param).rd_vdl_dqp[3][2]; 2073 value32_lo |= value16; 2074 value16 = 0; 2075 value32_lo <<= 16; 2076 2077 value16 = (uint16) (*config_param).rd_vdl_dqp[3][3]; 2078 value32_lo |= value16; 2079 value16 = 0; 2080 2081 sal_sprintf(name_str, "%s", spn_DDR3_TUNE_RD_VDL_DQP0_BL3); 2082 COMPILER_64_SET(value64, value32_hi, value32_lo); 2083 soc_format_uint64(val_str, value64); 2084 if (soc_mem_config_set(name_str, val_str) < 0) { 2085 return SOC_E_MEMORY; 2086 } 2087 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 2088 value16 = (uint16) (*config_param).rd_vdl_dqp[3][4]; 2089 value32_hi |= value16; 2090 value16 = 0; 2091 value32_hi <<= 16; 2092 2093 value16 = (uint16) (*config_param).rd_vdl_dqp[3][5]; 2094 value32_hi |= value16; 2095 value16 = 0; 2096 2097 value16 = (uint16) (*config_param).rd_vdl_dqp[3][6]; 2098 value32_lo |= value16; 2099 value16 = 0; 2100 value32_lo <<= 16; 2101 2102 value16 = (uint16) (*config_param).rd_vdl_dqp[3][7]; 2103 value32_lo |= value16; 2104 value16 = 0; 2105 2106 sal_sprintf(name_str, "%s", spn_DDR3_TUNE_RD_VDL_DQP4_BL3); 2107 COMPILER_64_SET(value64, value32_hi, value32_lo); 2108 soc_format_uint64(val_str, value64); 2109 if (soc_mem_config_set(name_str, val_str) < 0) { 2110 return SOC_E_MEMORY; 2111 } 2112 /* END of uint16 rd_vdl_dqp[SHMOO_AND28_BYTES_PER_INTERFACE][SHMOO_AND28_BYTE]; */ 2113 2114 /* uint16 rd_vdl_dqn[SHMOO_AND28_BYTES_PER_INTERFACE][SHMOO_AND28_BYTE] */ 2115 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 2116 value16 = (uint16) (*config_param).rd_vdl_dqn[0][0]; 2117 value32_hi |= value16; 2118 value16 = 0; 2119 value32_hi <<= 16; 2120 2121 value16 = (uint16) (*config_param).rd_vdl_dqn[0][1]; 2122 value32_hi |= value16; 2123 value16 = 0; 2124 2125 value16 = (uint16) (*config_param).rd_vdl_dqn[0][2]; 2126 value32_lo |= value16; 2127 value16 = 0; 2128 value32_lo <<= 16; 2129 2130 value16 = (uint16) (*config_param).rd_vdl_dqn[0][3]; 2131 value32_lo |= value16; 2132 value16 = 0; 2133 2134 sal_sprintf(name_str, "%s", spn_DDR3_TUNE_RD_VDL_DQN0_BL0); 2135 COMPILER_64_SET(value64, value32_hi, value32_lo); 2136 soc_format_uint64(val_str, value64); 2137 if (soc_mem_config_set(name_str, val_str) < 0) { 2138 return SOC_E_MEMORY; 2139 } 2140 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 2141 value16 = (uint16) (*config_param).rd_vdl_dqn[0][4]; 2142 value32_hi |= value16; 2143 value16 = 0; 2144 value32_hi <<= 16; 2145 2146 value16 = (uint16) (*config_param).rd_vdl_dqn[0][5]; 2147 value32_hi |= value16; 2148 value16 = 0; 2149 2150 value16 = (uint16) (*config_param).rd_vdl_dqn[0][6]; 2151 value32_lo |= value16; 2152 value16 = 0; 2153 value32_lo <<= 16; 2154 2155 value16 = (uint16) (*config_param).rd_vdl_dqn[0][7]; 2156 value32_lo |= value16; 2157 value16 = 0; 2158 2159 sal_sprintf(name_str, "%s", spn_DDR3_TUNE_RD_VDL_DQN4_BL0); 2160 COMPILER_64_SET(value64, value32_hi, value32_lo); 2161 soc_format_uint64(val_str, value64); 2162 if (soc_mem_config_set(name_str, val_str) < 0) { 2163 return SOC_E_MEMORY; 2164 } 2165 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 2166 value16 = (uint16) (*config_param).rd_vdl_dqn[1][0]; 2167 value32_hi |= value16; 2168 value16 = 0; 2169 value32_hi <<= 16; 2170 2171 value16 = (uint16) (*config_param).rd_vdl_dqn[1][1]; 2172 value32_hi |= value16; 2173 value16 = 0; 2174 2175 value16 = (uint16) (*config_param).rd_vdl_dqn[1][2]; 2176 value32_lo |= value16; 2177 value16 = 0; 2178 value32_lo <<= 16; 2179 2180 value16 = (uint16) (*config_param).rd_vdl_dqn[1][3]; 2181 value32_lo |= value16; 2182 value16 = 0; 2183 2184 sal_sprintf(name_str, "%s", spn_DDR3_TUNE_RD_VDL_DQN0_BL1); 2185 COMPILER_64_SET(value64, value32_hi, value32_lo); 2186 soc_format_uint64(val_str, value64); 2187 if (soc_mem_config_set(name_str, val_str) < 0) { 2188 return SOC_E_MEMORY; 2189 } 2190 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 2191 value16 = (uint16) (*config_param).rd_vdl_dqn[1][4]; 2192 value32_hi |= value16; 2193 value16 = 0; 2194 value32_hi <<= 16; 2195 2196 value16 = (uint16) (*config_param).rd_vdl_dqn[1][5]; 2197 value32_hi |= value16; 2198 value16 = 0; 2199 2200 value16 = (uint16) (*config_param).rd_vdl_dqn[1][6]; 2201 value32_lo |= value16; 2202 value16 = 0; 2203 value32_lo <<= 16; 2204 2205 value16 = (uint16) (*config_param).rd_vdl_dqn[1][7]; 2206 value32_lo |= value16; 2207 value16 = 0; 2208 2209 sal_sprintf(name_str, "%s", spn_DDR3_TUNE_RD_VDL_DQN4_BL1); 2210 COMPILER_64_SET(value64, value32_hi, value32_lo); 2211 soc_format_uint64(val_str, value64); 2212 if (soc_mem_config_set(name_str, val_str) < 0) { 2213 return SOC_E_MEMORY; 2214 } 2215 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 2216 value16 = (uint16) (*config_param).rd_vdl_dqn[2][0]; 2217 value32_hi |= value16; 2218 value16 = 0; 2219 value32_hi <<= 16; 2220 2221 value16 = (uint16) (*config_param).rd_vdl_dqn[2][1]; 2222 value32_hi |= value16; 2223 value16 = 0; 2224 2225 value16 = (uint16) (*config_param).rd_vdl_dqn[2][2]; 2226 value32_lo |= value16; 2227 value16 = 0; 2228 value32_lo <<= 16; 2229 2230 value16 = (uint16) (*config_param).rd_vdl_dqn[2][3]; 2231 value32_lo |= value16; 2232 value16 = 0; 2233 2234 sal_sprintf(name_str, "%s", spn_DDR3_TUNE_RD_VDL_DQN0_BL2); 2235 COMPILER_64_SET(value64, value32_hi, value32_lo); 2236 soc_format_uint64(val_str, value64); 2237 if (soc_mem_config_set(name_str, val_str) < 0) { 2238 return SOC_E_MEMORY; 2239 } 2240 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 2241 value16 = (uint16) (*config_param).rd_vdl_dqn[2][4]; 2242 value32_hi |= value16; 2243 value16 = 0; 2244 value32_hi <<= 16; 2245 2246 value16 = (uint16) (*config_param).rd_vdl_dqn[2][5]; 2247 value32_hi |= value16; 2248 value16 = 0; 2249 2250 value16 = (uint16) (*config_param).rd_vdl_dqn[2][6]; 2251 value32_lo |= value16; 2252 value16 = 0; 2253 value32_lo <<= 16; 2254 2255 value16 = (uint16) (*config_param).rd_vdl_dqn[2][7]; 2256 value32_lo |= value16; 2257 value16 = 0; 2258 2259 sal_sprintf(name_str, "%s", spn_DDR3_TUNE_RD_VDL_DQN4_BL2); 2260 COMPILER_64_SET(value64, value32_hi, value32_lo); 2261 soc_format_uint64(val_str, value64); 2262 if (soc_mem_config_set(name_str, val_str) < 0) { 2263 return SOC_E_MEMORY; 2264 } 2265 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 2266 value16 = (uint16) (*config_param).rd_vdl_dqn[3][0]; 2267 value32_hi |= value16; 2268 value16 = 0; 2269 value32_hi <<= 16; 2270 2271 value16 = (uint16) (*config_param).rd_vdl_dqn[3][1]; 2272 value32_hi |= value16; 2273 value16 = 0; 2274 2275 value16 = (uint16) (*config_param).rd_vdl_dqn[3][2]; 2276 value32_lo |= value16; 2277 value16 = 0; 2278 value32_lo <<= 16; 2279 2280 value16 = (uint16) (*config_param).rd_vdl_dqn[3][3]; 2281 value32_lo |= value16; 2282 value16 = 0; 2283 2284 sal_sprintf(name_str, "%s", spn_DDR3_TUNE_RD_VDL_DQN0_BL3); 2285 COMPILER_64_SET(value64, value32_hi, value32_lo); 2286 soc_format_uint64(val_str, value64); 2287 if (soc_mem_config_set(name_str, val_str) < 0) { 2288 return SOC_E_MEMORY; 2289 } 2290 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 2291 value16 = (uint16) (*config_param).rd_vdl_dqn[3][4]; 2292 value32_hi |= value16; 2293 value16 = 0; 2294 value32_hi <<= 16; 2295 2296 value16 = (uint16) (*config_param).rd_vdl_dqn[3][5]; 2297 value32_hi |= value16; 2298 value16 = 0; 2299 2300 value16 = (uint16) (*config_param).rd_vdl_dqn[3][6]; 2301 value32_lo |= value16; 2302 value16 = 0; 2303 value32_lo <<= 16; 2304 2305 value16 = (uint16) (*config_param).rd_vdl_dqn[3][7]; 2306 value32_lo |= value16; 2307 value16 = 0; 2308 2309 sal_sprintf(name_str, "%s", spn_DDR3_TUNE_RD_VDL_DQN4_BL3); 2310 COMPILER_64_SET(value64, value32_hi, value32_lo); 2311 soc_format_uint64(val_str, value64); 2312 if (soc_mem_config_set(name_str, val_str) < 0) { 2313 return SOC_E_MEMORY; 2314 } 2315 /* END of uint16 rd_vdl_dqn[SHMOO_AND28_BYTES_PER_INTERFACE][SHMOO_AND28_BYTE]; */ 2316 2317 /* uint16 rd_vdl_dmp[SHMOO_AND28_BYTES_PER_INTERFACE] */ 2318 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 2319 value16 = (uint16) (*config_param).rd_vdl_dmp[0]; 2320 value32_hi |= value16; 2321 value16 = 0; 2322 value32_hi <<= 16; 2323 2324 value16 = (uint16) (*config_param).rd_vdl_dmp[1]; 2325 value32_hi |= value16; 2326 value16 = 0; 2327 2328 value16 = (uint16) (*config_param).rd_vdl_dmp[2]; 2329 value32_lo |= value16; 2330 value16 = 0; 2331 value32_lo <<= 16; 2332 2333 value16 = (uint16) (*config_param).rd_vdl_dmp[3]; 2334 value32_lo |= value16; 2335 value16 = 0; 2336 2337 sal_sprintf(name_str, "%s", spn_DDR3_TUNE_RD_VDL_DMP); 2338 COMPILER_64_SET(value64, value32_hi, value32_lo); 2339 soc_format_uint64(val_str, value64); 2340 if (soc_mem_config_set(name_str, val_str) < 0) { 2341 return SOC_E_MEMORY; 2342 } 2343 /*END of uint16 rd_vdl_dmp[SHMOO_AND28_BYTES_PER_INTERFACE] */ 2344 2345 /* uint16 rd_vdl_dmn[SHMOO_AND28_BYTES_PER_INTERFACE] */ 2346 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 2347 value16 = (uint16) (*config_param).rd_vdl_dmn[0]; 2348 value32_hi |= value16; 2349 value16 = 0; 2350 value32_hi <<= 16; 2351 2352 value16 = (uint16) (*config_param).rd_vdl_dmn[1]; 2353 value32_hi |= value16; 2354 value16 = 0; 2355 2356 value16 = (uint16) (*config_param).rd_vdl_dmn[2]; 2357 value32_lo |= value16; 2358 value16 = 0; 2359 value32_lo <<= 16; 2360 2361 value16 = (uint16) (*config_param).rd_vdl_dmn[3]; 2362 value32_lo |= value16; 2363 value16 = 0; 2364 2365 sal_sprintf(name_str, "%s", spn_DDR3_TUNE_RD_VDL_DMN); 2366 COMPILER_64_SET(value64, value32_hi, value32_lo); 2367 soc_format_uint64(val_str, value64); 2368 if (soc_mem_config_set(name_str, val_str) < 0) { 2369 return SOC_E_MEMORY; 2370 } 2371 /*END of uint16 rd_vdl_dmn[SHMOO_AND28_BYTES_PER_INTERFACE] */ 2372 2373 /* uint16 rd_en_vdl_cs[SHMOO_AND28_BYTES_PER_INTERFACE][SHMOO_AND28_PHY_NOF_CS] */ 2374 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 2375 value16 = (uint16) (*config_param).rd_en_vdl_cs[0][0]; 2376 value32_hi |= value16; 2377 value16 = 0; 2378 value32_hi <<= 16; 2379 2380 value16 = (uint16) (*config_param).rd_en_vdl_cs[0][1]; 2381 value32_hi |= value16; 2382 value16 = 0; 2383 2384 value16 = (uint16) (*config_param).rd_en_vdl_cs[1][0]; 2385 value32_lo |= value16; 2386 value16 = 0; 2387 value32_lo <<= 16; 2388 2389 value16 = (uint16) (*config_param).rd_en_vdl_cs[1][1]; 2390 value32_lo |= value16; 2391 value16 = 0; 2392 2393 sal_sprintf(name_str, "%s", spn_DDR3_TUNE_RD_EN_VDL_CS0); 2394 COMPILER_64_SET(value64, value32_hi, value32_lo); 2395 soc_format_uint64(val_str, value64); 2396 if (soc_mem_config_set(name_str, val_str) < 0) { 2397 return SOC_E_MEMORY; 2398 } 2399 2400 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 2401 value16 = (uint16) (*config_param).rd_en_vdl_cs[2][0]; 2402 value32_hi |= value16; 2403 value16 = 0; 2404 value32_hi <<= 16; 2405 2406 value16 = (uint16) (*config_param).rd_en_vdl_cs[2][1]; 2407 value32_hi |= value16; 2408 value16 = 0; 2409 2410 value16 = (uint16) (*config_param).rd_en_vdl_cs[3][0]; 2411 value32_lo |= value16; 2412 value16 = 0; 2413 value32_lo <<= 16; 2414 2415 value16 = (uint16) (*config_param).rd_en_vdl_cs[3][1]; 2416 value32_lo |= value16; 2417 value16 = 0; 2418 2419 sal_sprintf(name_str, "%s", spn_DDR3_TUNE_RD_EN_VDL_CS1); 2420 COMPILER_64_SET(value64, value32_hi, value32_lo); 2421 soc_format_uint64(val_str, value64); 2422 if (soc_mem_config_set(name_str, val_str) < 0) { 2423 return SOC_E_MEMORY; 2424 } 2425 /* END of uint16 rd_en_vdl_cs[SHMOO_AND28_BYTES_PER_INTERFACE][SHMOO_AND28_PHY_NOF_CS]; */ 2426 2427 /* uint16 rd_en_dly_cyc[SHMOO_AND28_BYTES_PER_INTERFACE] */ 2428 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 2429 value16 = (uint16) (*config_param).rd_en_dly_cyc[0]; 2430 value32_hi |= value16; 2431 value16 = 0; 2432 value32_hi <<= 16; 2433 2434 value16 = (uint16) (*config_param).rd_en_dly_cyc[1]; 2435 value32_hi |= value16; 2436 value16 = 0; 2437 2438 value16 = (uint16) (*config_param).rd_en_dly_cyc[2]; 2439 value32_lo |= value16; 2440 value16 = 0; 2441 value32_lo <<= 16; 2442 2443 value16 = (uint16) (*config_param).rd_en_dly_cyc[3]; 2444 value32_lo |= value16; 2445 value16 = 0; 2446 2447 sal_sprintf(name_str, "%s", spn_DDR3_TUNE_RD_EN_DLY_CYC); 2448 COMPILER_64_SET(value64, value32_hi, value32_lo); 2449 soc_format_uint64(val_str, value64); 2450 if (soc_mem_config_set(name_str, val_str) < 0) { 2451 return SOC_E_MEMORY; 2452 } 2453 /*END of uint16 rd_en_dly_cyc[SHMOO_AND28_BYTES_PER_INTERFACE] */ 2454 2455 /* uint16 rd_control[SHMOO_AND28_BYTES_PER_INTERFACE] */ 2456 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 2457 value8 = (uint8) (*config_param).rd_control[0]; 2458 value32_hi |= value8; 2459 value8 = 0; 2460 value32_hi <<= 8; 2461 2462 value8 = (uint8) (*config_param).rd_control[1]; 2463 value32_hi |= value8; 2464 value8 = 0; 2465 value32_hi <<= 8; 2466 2467 value8 = (uint8) (*config_param).rd_control[2]; 2468 value32_hi |= value8; 2469 value8 = 0; 2470 value32_hi <<= 8; 2471 2472 value8 = (uint8) (*config_param).rd_control[3]; 2473 value32_hi |= value8; 2474 value8 = 0; 2475 2476 sal_sprintf(name_str, "%s", spn_DDR3_TUNE_RD_CONTROL); 2477 COMPILER_64_SET(value64, value32_hi, value32_lo); 2478 soc_format_uint64(val_str, value64); 2479 if (soc_mem_config_set(name_str, val_str) < 0) { 2480 return SOC_E_MEMORY; 2481 } 2482 /*END of uint16 rd_control[SHMOO_AND28_BYTES_PER_INTERFACE] */ 2483 2484 return SOC_E_NONE; 2485 } 2486 2487 /* This function is used to restore the and28_shmoo_config_param_t structure 2488 * from config variables */ 2489 int soc_sb2_and28_dram_restorecfg(int unit, and28_shmoo_config_param_t *config_param) 2490 { 2491 uint64 value64; 2492 uint32 value32_lo = 0; 2493 uint32 value32_hi = 0; 2494 char* svalue = NULL; 2495 2496 2497 if (config_param == NULL) { 2498 return SOC_E_PARAM; 2499 } 2500 2501 /* uint16 control_regs_ad[SHMOO_AND28_PHY_NOF_AD] */ 2502 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 2503 svalue = soc_property_get_str(unit, spn_DDR3_TUNE_CTRL_VDL_AD00); 2504 if (svalue != NULL){ 2505 value64 = soc_parse_uint64(svalue); 2506 COMPILER_64_TO_32_LO(value32_lo,value64); 2507 COMPILER_64_TO_32_HI(value32_hi,value64); 2508 2509 (*config_param).control_regs_ad[0] = (uint16) ((value32_hi & 0xFFFF0000)>>16); 2510 (*config_param).control_regs_ad[1] = (uint16) (value32_hi & 0xFFFF); 2511 (*config_param).control_regs_ad[2] = (uint16) ((value32_lo & 0xFFFF0000)>>16); 2512 (*config_param).control_regs_ad[3] = (uint16) (value32_lo & 0xFFFF); 2513 } 2514 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 2515 svalue = soc_property_get_str(unit, spn_DDR3_TUNE_CTRL_VDL_AD04); 2516 if (svalue != NULL){ 2517 value64 = soc_parse_uint64(svalue); 2518 COMPILER_64_TO_32_LO(value32_lo,value64); 2519 COMPILER_64_TO_32_HI(value32_hi,value64); 2520 2521 (*config_param).control_regs_ad[4] = (uint16) ((value32_hi & 0xFFFF0000)>>16); 2522 (*config_param).control_regs_ad[5] = (uint16) (value32_hi & 0xFFFF); 2523 (*config_param).control_regs_ad[6] = (uint16) ((value32_lo & 0xFFFF0000)>>16); 2524 (*config_param).control_regs_ad[7] = (uint16) (value32_lo & 0xFFFF); 2525 } 2526 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 2527 svalue = soc_property_get_str(unit, spn_DDR3_TUNE_CTRL_VDL_AD08); 2528 if (svalue != NULL){ 2529 value64 = soc_parse_uint64(svalue); 2530 COMPILER_64_TO_32_LO(value32_lo,value64); 2531 COMPILER_64_TO_32_HI(value32_hi,value64); 2532 2533 (*config_param).control_regs_ad[8] = (uint16) ((value32_hi & 0xFFFF0000)>>16); 2534 (*config_param).control_regs_ad[9] = (uint16) (value32_hi & 0xFFFF); 2535 (*config_param).control_regs_ad[10] = (uint16) ((value32_lo & 0xFFFF0000)>>16); 2536 (*config_param).control_regs_ad[11] = (uint16) (value32_lo & 0xFFFF); 2537 } 2538 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 2539 svalue = soc_property_get_str(unit, spn_DDR3_TUNE_CTRL_VDL_AD12); 2540 if (svalue != NULL){ 2541 value64 = soc_parse_uint64(svalue); 2542 COMPILER_64_TO_32_LO(value32_lo,value64); 2543 COMPILER_64_TO_32_HI(value32_hi,value64); 2544 2545 (*config_param).control_regs_ad[12] = (uint16) ((value32_hi & 0xFFFF0000)>>16); 2546 (*config_param).control_regs_ad[13] = (uint16) (value32_hi & 0xFFFF); 2547 (*config_param).control_regs_ad[14] = (uint16) ((value32_lo & 0xFFFF0000)>>16); 2548 (*config_param).control_regs_ad[15] = (uint16) (value32_lo & 0xFFFF); 2549 } 2550 /*END of uint16 control_regs_ad[SHMOO_AND28_PHY_NOF_AD] */ 2551 2552 /* uint16 control_regs_ba[SHMOO_AND28_PHY_NOF_BA] */ 2553 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 2554 svalue = soc_property_get_str(unit, spn_DDR3_TUNE_CTRL_VDL_BA); 2555 if (svalue != NULL){ 2556 value64 = soc_parse_uint64(svalue); 2557 COMPILER_64_TO_32_LO(value32_lo,value64); 2558 COMPILER_64_TO_32_HI(value32_hi,value64); 2559 2560 (*config_param).control_regs_ba[0] = (uint16) ((value32_hi & 0xFFFF0000)>>16); 2561 (*config_param).control_regs_ba[1] = (uint16) (value32_hi & 0xFFFF); 2562 (*config_param).control_regs_ba[2] = (uint16) (value32_lo & 0xFFFF); 2563 } 2564 /* END of uint16 control_regs_ba[SHMOO_AND28_PHY_NOF_BA] */ 2565 2566 /* uint16 control_regs_aux[SHMOO_AND28_PHY_NOF_AUX] */ 2567 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 2568 svalue = soc_property_get_str(unit, spn_DDR3_TUNE_CTRL_VDL_AUX); 2569 if (svalue != NULL){ 2570 value64 = soc_parse_uint64(svalue); 2571 COMPILER_64_TO_32_LO(value32_lo,value64); 2572 COMPILER_64_TO_32_HI(value32_hi,value64); 2573 2574 (*config_param).control_regs_aux[0] = (uint16) ((value32_hi & 0xFFFF0000)>>16); 2575 (*config_param).control_regs_aux[1] = (uint16) (value32_hi & 0xFFFF); 2576 (*config_param).control_regs_aux[2] = (uint16) (value32_lo & 0xFFFF); 2577 } 2578 /* END of uint16 control_regs_aux[SHMOO_AND28_PHY_NOF_AUX] */ 2579 2580 /* uint16 control_regs_cs[SHMOO_AND28_PHY_NOF_CS] */ 2581 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 2582 svalue = soc_property_get_str(unit, spn_DDR3_TUNE_CTRL_VDL_CS); 2583 if (svalue != NULL){ 2584 value64 = soc_parse_uint64(svalue); 2585 COMPILER_64_TO_32_LO(value32_lo,value64); 2586 COMPILER_64_TO_32_HI(value32_hi,value64); 2587 2588 (*config_param).control_regs_cs[0] = (uint16) ((value32_hi & 0xFFFF0000)>>16); 2589 (*config_param).control_regs_cs[1] = (uint16) (value32_hi & 0xFFFF); 2590 } 2591 /* END of uint16 control_regs_cs[SHMOO_AND28_PHY_NOF_CS] */ 2592 2593 /* 2594 * uint16 control_regs_par; 2595 * uint16 control_regs_ras_n; 2596 * uint16 control_regs_cas_n; 2597 * uint16 control_regs_cke; 2598 * uint16 control_regs_rst_n; 2599 * uint16 control_regs_odt; 2600 * uint16 control_regs_we_n; 2601 * uint32 control_regs_vref_dac_control;*/ 2602 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 2603 svalue = soc_property_get_str(unit, spn_DDR3_TUNE_CTRL_VDL_PAR); 2604 if (svalue != NULL){ 2605 value64 = soc_parse_uint64(svalue); 2606 COMPILER_64_TO_32_LO(value32_lo,value64); 2607 COMPILER_64_TO_32_HI(value32_hi,value64); 2608 2609 (*config_param).control_regs_par = (uint16) (value32_hi & 0xFFFF); 2610 } 2611 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 2612 svalue = soc_property_get_str(unit, spn_DDR3_TUNE_CTRL_VDL_RAS_N); 2613 if (svalue != NULL){ 2614 value64 = soc_parse_uint64(svalue); 2615 COMPILER_64_TO_32_LO(value32_lo,value64); 2616 COMPILER_64_TO_32_HI(value32_hi,value64); 2617 2618 (*config_param).control_regs_ras_n = (uint16) (value32_hi & 0xFFFF); 2619 } 2620 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 2621 svalue = soc_property_get_str(unit, spn_DDR3_TUNE_CTRL_VDL_CAS_N); 2622 if (svalue != NULL){ 2623 value64 = soc_parse_uint64(svalue); 2624 COMPILER_64_TO_32_LO(value32_lo,value64); 2625 COMPILER_64_TO_32_HI(value32_hi,value64); 2626 2627 (*config_param).control_regs_cas_n = (uint16) (value32_hi & 0xFFFF); 2628 } 2629 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 2630 svalue = soc_property_get_str(unit, spn_DDR3_TUNE_CTRL_VDL_CKE); 2631 if (svalue != NULL){ 2632 value64 = soc_parse_uint64(svalue); 2633 COMPILER_64_TO_32_LO(value32_lo,value64); 2634 COMPILER_64_TO_32_HI(value32_hi,value64); 2635 2636 (*config_param).control_regs_cke = (uint16) (value32_hi & 0xFFFF); 2637 } 2638 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 2639 svalue = soc_property_get_str(unit, spn_DDR3_TUNE_CTRL_VDL_RST_N); 2640 if (svalue != NULL){ 2641 value64 = soc_parse_uint64(svalue); 2642 COMPILER_64_TO_32_LO(value32_lo,value64); 2643 COMPILER_64_TO_32_HI(value32_hi,value64); 2644 2645 (*config_param).control_regs_rst_n = (uint16) (value32_hi & 0xFFFF); 2646 } 2647 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 2648 svalue = soc_property_get_str(unit, spn_DDR3_TUNE_CTRL_VDL_ODT); 2649 if (svalue != NULL){ 2650 value64 = soc_parse_uint64(svalue); 2651 COMPILER_64_TO_32_LO(value32_lo,value64); 2652 COMPILER_64_TO_32_HI(value32_hi,value64); 2653 2654 (*config_param).control_regs_odt = (uint16) (value32_hi & 0xFFFF); 2655 } 2656 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 2657 svalue = soc_property_get_str(unit, spn_DDR3_TUNE_CTRL_VDL_WE_N); 2658 if (svalue != NULL){ 2659 value64 = soc_parse_uint64(svalue); 2660 COMPILER_64_TO_32_LO(value32_lo,value64); 2661 COMPILER_64_TO_32_HI(value32_hi,value64); 2662 2663 (*config_param).control_regs_we_n = (uint16) (value32_hi & 0xFFFF); 2664 } 2665 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 2666 svalue = soc_property_get_str(unit, spn_DDR3_TUNE_CTRL_VREF_DAC); 2667 if (svalue != NULL){ 2668 value64 = soc_parse_uint64(svalue); 2669 COMPILER_64_TO_32_LO(value32_lo,value64); 2670 COMPILER_64_TO_32_HI(value32_hi,value64); 2671 2672 (*config_param).control_regs_vref_dac_control = (uint32) (value32_hi); 2673 } 2674 /* END */ 2675 2676 /* uint16 wr_vdl_dqsp[SHMOO_AND28_BYTES_PER_INTERFACE] */ 2677 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 2678 svalue = soc_property_get_str(unit, spn_DDR3_TUNE_WR_VDL_DQSP); 2679 if (svalue != NULL){ 2680 value64 = soc_parse_uint64(svalue); 2681 COMPILER_64_TO_32_LO(value32_lo,value64); 2682 COMPILER_64_TO_32_HI(value32_hi,value64); 2683 2684 (*config_param).wr_vdl_dqsp[0] = (uint16) ((value32_hi & 0xFFFF0000)>>16); 2685 (*config_param).wr_vdl_dqsp[1] = (uint16) (value32_hi & 0xFFFF); 2686 (*config_param).wr_vdl_dqsp[2] = (uint16) ((value32_lo & 0xFFFF0000)>>16); 2687 (*config_param).wr_vdl_dqsp[3] = (uint16) (value32_lo & 0xFFFF); 2688 } 2689 /* END of uint16 wr_vdl_dqsp[SHMOO_AND28_BYTES_PER_INTERFACE] */ 2690 2691 /* uint16 wr_vdl_dqsn[SHMOO_AND28_BYTES_PER_INTERFACE] */ 2692 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 2693 svalue = soc_property_get_str(unit, spn_DDR3_TUNE_WR_VDL_DQSN); 2694 if (svalue != NULL){ 2695 value64 = soc_parse_uint64(svalue); 2696 COMPILER_64_TO_32_LO(value32_lo,value64); 2697 COMPILER_64_TO_32_HI(value32_hi,value64); 2698 2699 (*config_param).wr_vdl_dqsn[0] = (uint16) ((value32_hi & 0xFFFF0000)>>16); 2700 (*config_param).wr_vdl_dqsn[1] = (uint16) (value32_hi & 0xFFFF); 2701 (*config_param).wr_vdl_dqsn[2] = (uint16) ((value32_lo & 0xFFFF0000)>>16); 2702 (*config_param).wr_vdl_dqsn[3] = (uint16) (value32_lo & 0xFFFF); 2703 } 2704 /* END of uint16 wr_vdl_dqsn[SHMOO_AND28_BYTES_PER_INTERFACE] */ 2705 2706 /* uint16 wr_vdl_dq[SHMOO_AND28_BYTES_PER_INTERFACE][SHMOO_AND28_BYTE] */ 2707 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 2708 svalue = soc_property_get_str(unit, spn_DDR3_TUNE_WR_VDL_DQ0_BL0); 2709 if (svalue != NULL){ 2710 value64 = soc_parse_uint64(svalue); 2711 COMPILER_64_TO_32_LO(value32_lo,value64); 2712 COMPILER_64_TO_32_HI(value32_hi,value64); 2713 2714 (*config_param).wr_vdl_dq[0][0] = (uint16) ((value32_hi & 0xFFFF0000)>>16); 2715 (*config_param).wr_vdl_dq[0][1] = (uint16) (value32_hi & 0xFFFF); 2716 (*config_param).wr_vdl_dq[0][2] = (uint16) ((value32_lo & 0xFFFF0000)>>16); 2717 (*config_param).wr_vdl_dq[0][3] = (uint16) (value32_lo & 0xFFFF); 2718 } 2719 2720 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 2721 svalue = soc_property_get_str(unit, spn_DDR3_TUNE_WR_VDL_DQ4_BL0); 2722 if (svalue != NULL){ 2723 value64 = soc_parse_uint64(svalue); 2724 COMPILER_64_TO_32_LO(value32_lo,value64); 2725 COMPILER_64_TO_32_HI(value32_hi,value64); 2726 2727 (*config_param).wr_vdl_dq[0][4] = (uint16) ((value32_hi & 0xFFFF0000)>>16); 2728 (*config_param).wr_vdl_dq[0][5] = (uint16) (value32_hi & 0xFFFF); 2729 (*config_param).wr_vdl_dq[0][6] = (uint16) ((value32_lo & 0xFFFF0000)>>16); 2730 (*config_param).wr_vdl_dq[0][7] = (uint16) (value32_lo & 0xFFFF); 2731 } 2732 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 2733 svalue = soc_property_get_str(unit, spn_DDR3_TUNE_WR_VDL_DQ0_BL1); 2734 if (svalue != NULL){ 2735 value64 = soc_parse_uint64(svalue); 2736 COMPILER_64_TO_32_LO(value32_lo,value64); 2737 COMPILER_64_TO_32_HI(value32_hi,value64); 2738 2739 (*config_param).wr_vdl_dq[1][0] = (uint16) ((value32_hi & 0xFFFF0000)>>16); 2740 (*config_param).wr_vdl_dq[1][1] = (uint16) (value32_hi & 0xFFFF); 2741 (*config_param).wr_vdl_dq[1][2] = (uint16) ((value32_lo & 0xFFFF0000)>>16); 2742 (*config_param).wr_vdl_dq[1][3] = (uint16) (value32_lo & 0xFFFF); 2743 } 2744 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 2745 svalue = soc_property_get_str(unit, spn_DDR3_TUNE_WR_VDL_DQ4_BL1); 2746 if (svalue != NULL){ 2747 value64 = soc_parse_uint64(svalue); 2748 COMPILER_64_TO_32_LO(value32_lo,value64); 2749 COMPILER_64_TO_32_HI(value32_hi,value64); 2750 2751 (*config_param).wr_vdl_dq[1][4] = (uint16) ((value32_hi & 0xFFFF0000)>>16); 2752 (*config_param).wr_vdl_dq[1][5] = (uint16) (value32_hi & 0xFFFF); 2753 (*config_param).wr_vdl_dq[1][6] = (uint16) ((value32_lo & 0xFFFF0000)>>16); 2754 (*config_param).wr_vdl_dq[1][7] = (uint16) (value32_lo & 0xFFFF); 2755 } 2756 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 2757 svalue = soc_property_get_str(unit, spn_DDR3_TUNE_WR_VDL_DQ0_BL2); 2758 if (svalue != NULL){ 2759 value64 = soc_parse_uint64(svalue); 2760 COMPILER_64_TO_32_LO(value32_lo,value64); 2761 COMPILER_64_TO_32_HI(value32_hi,value64); 2762 2763 (*config_param).wr_vdl_dq[2][0] = (uint16) ((value32_hi & 0xFFFF0000)>>16); 2764 (*config_param).wr_vdl_dq[2][1] = (uint16) (value32_hi & 0xFFFF); 2765 (*config_param).wr_vdl_dq[2][2] = (uint16) ((value32_lo & 0xFFFF0000)>>16); 2766 (*config_param).wr_vdl_dq[2][3] = (uint16) (value32_lo & 0xFFFF); 2767 } 2768 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 2769 svalue = soc_property_get_str(unit, spn_DDR3_TUNE_WR_VDL_DQ4_BL2); 2770 if (svalue != NULL){ 2771 value64 = soc_parse_uint64(svalue); 2772 COMPILER_64_TO_32_LO(value32_lo,value64); 2773 COMPILER_64_TO_32_HI(value32_hi,value64); 2774 2775 (*config_param).wr_vdl_dq[2][4] = (uint16) ((value32_hi & 0xFFFF0000)>>16); 2776 (*config_param).wr_vdl_dq[2][5] = (uint16) (value32_hi & 0xFFFF); 2777 (*config_param).wr_vdl_dq[2][6] = (uint16) ((value32_lo & 0xFFFF0000)>>16); 2778 (*config_param).wr_vdl_dq[2][7] = (uint16) (value32_lo & 0xFFFF); 2779 } 2780 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 2781 svalue = soc_property_get_str(unit, spn_DDR3_TUNE_WR_VDL_DQ0_BL3); 2782 if (svalue != NULL){ 2783 value64 = soc_parse_uint64(svalue); 2784 COMPILER_64_TO_32_LO(value32_lo,value64); 2785 COMPILER_64_TO_32_HI(value32_hi,value64); 2786 2787 (*config_param).wr_vdl_dq[3][0] = (uint16) ((value32_hi & 0xFFFF0000)>>16); 2788 (*config_param).wr_vdl_dq[3][1] = (uint16) (value32_hi & 0xFFFF); 2789 (*config_param).wr_vdl_dq[3][2] = (uint16) ((value32_lo & 0xFFFF0000)>>16); 2790 (*config_param).wr_vdl_dq[3][3] = (uint16) (value32_lo & 0xFFFF); 2791 } 2792 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 2793 svalue = soc_property_get_str(unit, spn_DDR3_TUNE_WR_VDL_DQ4_BL3); 2794 if (svalue != NULL){ 2795 value64 = soc_parse_uint64(svalue); 2796 COMPILER_64_TO_32_LO(value32_lo,value64); 2797 COMPILER_64_TO_32_HI(value32_hi,value64); 2798 2799 (*config_param).wr_vdl_dq[3][4] = (uint16) ((value32_hi & 0xFFFF0000)>>16); 2800 (*config_param).wr_vdl_dq[3][5] = (uint16) (value32_hi & 0xFFFF); 2801 (*config_param).wr_vdl_dq[3][6] = (uint16) ((value32_lo & 0xFFFF0000)>>16); 2802 (*config_param).wr_vdl_dq[3][7] = (uint16) (value32_lo & 0xFFFF); 2803 } 2804 /* END of uint16 wr_vdl_dq[SHMOO_AND28_BYTES_PER_INTERFACE][SHMOO_AND28_BYTE]; */ 2805 2806 /* uint16 wr_vdl_dm[SHMOO_AND28_BYTES_PER_INTERFACE] */ 2807 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 2808 svalue = soc_property_get_str(unit, spn_DDR3_TUNE_WR_VDL_DM); 2809 if (svalue != NULL){ 2810 value64 = soc_parse_uint64(svalue); 2811 COMPILER_64_TO_32_LO(value32_lo,value64); 2812 COMPILER_64_TO_32_HI(value32_hi,value64); 2813 2814 (*config_param).wr_vdl_dm[0] = (uint16) ((value32_hi & 0xFFFF0000)>>16); 2815 (*config_param).wr_vdl_dm[1] = (uint16) (value32_hi & 0xFFFF); 2816 (*config_param).wr_vdl_dm[2] = (uint16) ((value32_lo & 0xFFFF0000)>>16); 2817 (*config_param).wr_vdl_dm[3] = (uint16) (value32_lo & 0xFFFF); 2818 } 2819 /*END of uint16 .wr_vdl_dm[SHMOO_AND28_BYTES_PER_INTERFACE] */ 2820 2821 /* uint16 wr_vdl_edc[SHMOO_AND28_BYTES_PER_INTERFACE] */ 2822 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 2823 svalue = soc_property_get_str(unit, spn_DDR3_TUNE_WR_VDL_EDC); 2824 if (svalue != NULL){ 2825 value64 = soc_parse_uint64(svalue); 2826 COMPILER_64_TO_32_LO(value32_lo,value64); 2827 COMPILER_64_TO_32_HI(value32_hi,value64); 2828 2829 (*config_param).wr_vdl_edc[0] = (uint16) ((value32_hi & 0xFFFF0000)>>16); 2830 (*config_param).wr_vdl_edc[1] = (uint16) (value32_hi & 0xFFFF); 2831 (*config_param).wr_vdl_edc[2] = (uint16) ((value32_lo & 0xFFFF0000)>>16); 2832 (*config_param).wr_vdl_edc[3] = (uint16) (value32_lo & 0xFFFF); 2833 } 2834 /*END of uint16 wr_vdl_edc[SHMOO_AND28_BYTES_PER_INTERFACE] */ 2835 2836 /* uint8 wr_chan_dly_cyc[SHMOO_AND28_BYTES_PER_INTERFACE] */ 2837 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 2838 svalue = soc_property_get_str(unit, spn_DDR3_TUNE_WR_CHAN_DLY_CYC); 2839 if (svalue != NULL){ 2840 value64 = soc_parse_uint64(svalue); 2841 COMPILER_64_TO_32_LO(value32_lo,value64); 2842 COMPILER_64_TO_32_HI(value32_hi,value64); 2843 2844 (*config_param).wr_chan_dly_cyc[0] = (uint16) ((value32_hi & 0xFFFF0000)>>16); 2845 (*config_param).wr_chan_dly_cyc[1] = (uint16) (value32_hi & 0xFFFF); 2846 (*config_param).wr_chan_dly_cyc[2] = (uint16) ((value32_lo & 0xFFFF0000)>>16); 2847 (*config_param).wr_chan_dly_cyc[3] = (uint16) (value32_lo & 0xFFFF); 2848 } 2849 /*END of uint16 wr_chan_dly_cyc[SHMOO_AND28_BYTES_PER_INTERFACE] */ 2850 2851 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 2852 svalue = soc_property_get_str(unit, spn_DDR3_TUNE_CTRL_VREF_DAC); 2853 if (svalue != NULL){ 2854 value64 = soc_parse_uint64(svalue); 2855 COMPILER_64_TO_32_LO(value32_lo,value64); 2856 COMPILER_64_TO_32_HI(value32_hi,value64); 2857 (*config_param).control_regs_vref_dac_control = (uint32) value32_hi; 2858 } 2859 /* uint16 rd_vdl_dqsp[SHMOO_AND28_BYTES_PER_INTERFACE] */ 2860 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 2861 svalue = soc_property_get_str(unit, spn_DDR3_TUNE_RD_VDL_DQSP); 2862 if (svalue != NULL){ 2863 value64 = soc_parse_uint64(svalue); 2864 COMPILER_64_TO_32_LO(value32_lo,value64); 2865 COMPILER_64_TO_32_HI(value32_hi,value64); 2866 2867 (*config_param).rd_vdl_dqsp[0] = (uint16) ((value32_hi & 0xFFFF0000)>>16); 2868 (*config_param).rd_vdl_dqsp[1] = (uint16) (value32_hi & 0xFFFF); 2869 (*config_param).rd_vdl_dqsp[2] = (uint16) ((value32_lo & 0xFFFF0000)>>16); 2870 (*config_param).rd_vdl_dqsp[3] = (uint16) (value32_lo & 0xFFFF); 2871 } 2872 /*END of uint16 rd_vdl_dqsp[SHMOO_AND28_BYTES_PER_INTERFACE] */ 2873 2874 /* uint16 rd_vdl_dqsn[SHMOO_AND28_BYTES_PER_INTERFACE] */ 2875 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 2876 svalue = soc_property_get_str(unit, spn_DDR3_TUNE_RD_VDL_DQSN); 2877 if (svalue != NULL){ 2878 value64 = soc_parse_uint64(svalue); 2879 COMPILER_64_TO_32_LO(value32_lo,value64); 2880 COMPILER_64_TO_32_HI(value32_hi,value64); 2881 2882 (*config_param).rd_vdl_dqsn[0] = (uint16) ((value32_hi & 0xFFFF0000)>>16); 2883 (*config_param).rd_vdl_dqsn[1] = (uint16) (value32_hi & 0xFFFF); 2884 (*config_param).rd_vdl_dqsn[2] = (uint16) ((value32_lo & 0xFFFF0000)>>16); 2885 (*config_param).rd_vdl_dqsn[3] = (uint16) (value32_lo & 0xFFFF); 2886 } 2887 /*END of uint16 rd_vdl_dqsn[SHMOO_AND28_BYTES_PER_INTERFACE] */ 2888 2889 /* uint16 rd_vdl_dqp[SHMOO_AND28_BYTES_PER_INTERFACE][SHMOO_AND28_BYTE] */ 2890 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 2891 svalue = soc_property_get_str(unit, spn_DDR3_TUNE_RD_VDL_DQP0_BL0); 2892 if (svalue != NULL){ 2893 value64 = soc_parse_uint64(svalue); 2894 COMPILER_64_TO_32_LO(value32_lo,value64); 2895 COMPILER_64_TO_32_HI(value32_hi,value64); 2896 2897 (*config_param).rd_vdl_dqp[0][0] = (uint16) ((value32_hi & 0xFFFF0000)>>16); 2898 (*config_param).rd_vdl_dqp[0][1] = (uint16) (value32_hi & 0xFFFF); 2899 (*config_param).rd_vdl_dqp[0][2] = (uint16) ((value32_lo & 0xFFFF0000)>>16); 2900 (*config_param).rd_vdl_dqp[0][3] = (uint16) (value32_lo & 0xFFFF); 2901 } 2902 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 2903 svalue = soc_property_get_str(unit, spn_DDR3_TUNE_RD_VDL_DQP4_BL0); 2904 if (svalue != NULL){ 2905 value64 = soc_parse_uint64(svalue); 2906 COMPILER_64_TO_32_LO(value32_lo,value64); 2907 COMPILER_64_TO_32_HI(value32_hi,value64); 2908 2909 (*config_param).rd_vdl_dqp[0][4] = (uint16) ((value32_hi & 0xFFFF0000)>>16); 2910 (*config_param).rd_vdl_dqp[0][5] = (uint16) (value32_hi & 0xFFFF); 2911 (*config_param).rd_vdl_dqp[0][6] = (uint16) ((value32_lo & 0xFFFF0000)>>16); 2912 (*config_param).rd_vdl_dqp[0][7] = (uint16) (value32_lo & 0xFFFF); 2913 } 2914 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 2915 svalue = soc_property_get_str(unit, spn_DDR3_TUNE_RD_VDL_DQP0_BL1); 2916 if (svalue != NULL){ 2917 value64 = soc_parse_uint64(svalue); 2918 COMPILER_64_TO_32_LO(value32_lo,value64); 2919 COMPILER_64_TO_32_HI(value32_hi,value64); 2920 2921 (*config_param).rd_vdl_dqp[1][0] = (uint16) ((value32_hi & 0xFFFF0000)>>16); 2922 (*config_param).rd_vdl_dqp[1][1] = (uint16) (value32_hi & 0xFFFF); 2923 (*config_param).rd_vdl_dqp[1][2] = (uint16) ((value32_lo & 0xFFFF0000)>>16); 2924 (*config_param).rd_vdl_dqp[1][3] = (uint16) (value32_lo & 0xFFFF); 2925 } 2926 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 2927 svalue = soc_property_get_str(unit, spn_DDR3_TUNE_RD_VDL_DQP4_BL1); 2928 if (svalue != NULL){ 2929 value64 = soc_parse_uint64(svalue); 2930 COMPILER_64_TO_32_LO(value32_lo,value64); 2931 COMPILER_64_TO_32_HI(value32_hi,value64); 2932 2933 (*config_param).rd_vdl_dqp[1][4] = (uint16) ((value32_hi & 0xFFFF0000)>>16); 2934 (*config_param).rd_vdl_dqp[1][5] = (uint16) (value32_hi & 0xFFFF); 2935 (*config_param).rd_vdl_dqp[1][6] = (uint16) ((value32_lo & 0xFFFF0000)>>16); 2936 (*config_param).rd_vdl_dqp[1][7] = (uint16) (value32_lo & 0xFFFF); 2937 } 2938 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 2939 svalue = soc_property_get_str(unit, spn_DDR3_TUNE_RD_VDL_DQP0_BL2); 2940 if (svalue != NULL){ 2941 value64 = soc_parse_uint64(svalue); 2942 COMPILER_64_TO_32_LO(value32_lo,value64); 2943 COMPILER_64_TO_32_HI(value32_hi,value64); 2944 2945 (*config_param).rd_vdl_dqp[2][0] = (uint16) ((value32_hi & 0xFFFF0000)>>16); 2946 (*config_param).rd_vdl_dqp[2][1] = (uint16) (value32_hi & 0xFFFF); 2947 (*config_param).rd_vdl_dqp[2][2] = (uint16) ((value32_lo & 0xFFFF0000)>>16); 2948 (*config_param).rd_vdl_dqp[2][3] = (uint16) (value32_lo & 0xFFFF); 2949 } 2950 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 2951 svalue = soc_property_get_str(unit, spn_DDR3_TUNE_RD_VDL_DQP4_BL2); 2952 if (svalue != NULL){ 2953 value64 = soc_parse_uint64(svalue); 2954 COMPILER_64_TO_32_LO(value32_lo,value64); 2955 COMPILER_64_TO_32_HI(value32_hi,value64); 2956 2957 (*config_param).rd_vdl_dqp[2][4] = (uint16) ((value32_hi & 0xFFFF0000)>>16); 2958 (*config_param).rd_vdl_dqp[2][5] = (uint16) (value32_hi & 0xFFFF); 2959 (*config_param).rd_vdl_dqp[2][6] = (uint16) ((value32_lo & 0xFFFF0000)>>16); 2960 (*config_param).rd_vdl_dqp[2][7] = (uint16) (value32_lo & 0xFFFF); 2961 } 2962 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 2963 svalue = soc_property_get_str(unit, spn_DDR3_TUNE_RD_VDL_DQP0_BL3); 2964 if (svalue != NULL){ 2965 value64 = soc_parse_uint64(svalue); 2966 COMPILER_64_TO_32_LO(value32_lo,value64); 2967 COMPILER_64_TO_32_HI(value32_hi,value64); 2968 2969 (*config_param).rd_vdl_dqp[3][0] = (uint16) ((value32_hi & 0xFFFF0000)>>16); 2970 (*config_param).rd_vdl_dqp[3][1] = (uint16) (value32_hi & 0xFFFF); 2971 (*config_param).rd_vdl_dqp[3][2] = (uint16) ((value32_lo & 0xFFFF0000)>>16); 2972 (*config_param).rd_vdl_dqp[3][3] = (uint16) (value32_lo & 0xFFFF); 2973 } 2974 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 2975 svalue = soc_property_get_str(unit, spn_DDR3_TUNE_RD_VDL_DQP4_BL3); 2976 if (svalue != NULL){ 2977 value64 = soc_parse_uint64(svalue); 2978 COMPILER_64_TO_32_LO(value32_lo,value64); 2979 COMPILER_64_TO_32_HI(value32_hi,value64); 2980 2981 (*config_param).rd_vdl_dqp[3][4] = (uint16) ((value32_hi & 0xFFFF0000)>>16); 2982 (*config_param).rd_vdl_dqp[3][5] = (uint16) (value32_hi & 0xFFFF); 2983 (*config_param).rd_vdl_dqp[3][6] = (uint16) ((value32_lo & 0xFFFF0000)>>16); 2984 (*config_param).rd_vdl_dqp[3][7] = (uint16) (value32_lo & 0xFFFF); 2985 } 2986 /* END of uint16 rd_vdl_dqp[SHMOO_AND28_BYTES_PER_INTERFACE][SHMOO_AND28_BYTE]; */ 2987 2988 /* uint16 rd_vdl_dqn[SHMOO_AND28_BYTES_PER_INTERFACE][SHMOO_AND28_BYTE] */ 2989 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 2990 svalue = soc_property_get_str(unit, spn_DDR3_TUNE_RD_VDL_DQN0_BL0); 2991 if (svalue != NULL){ 2992 value64 = soc_parse_uint64(svalue); 2993 COMPILER_64_TO_32_LO(value32_lo,value64); 2994 COMPILER_64_TO_32_HI(value32_hi,value64); 2995 2996 (*config_param).rd_vdl_dqn[0][0] = (uint16) ((value32_hi & 0xFFFF0000)>>16); 2997 (*config_param).rd_vdl_dqn[0][1] = (uint16) (value32_hi & 0xFFFF); 2998 (*config_param).rd_vdl_dqn[0][2] = (uint16) ((value32_lo & 0xFFFF0000)>>16); 2999 (*config_param).rd_vdl_dqn[0][3] = (uint16) (value32_lo & 0xFFFF); 3000 } 3001 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 3002 svalue = soc_property_get_str(unit, spn_DDR3_TUNE_RD_VDL_DQN4_BL0); 3003 if (svalue != NULL){ 3004 value64 = soc_parse_uint64(svalue); 3005 COMPILER_64_TO_32_LO(value32_lo,value64); 3006 COMPILER_64_TO_32_HI(value32_hi,value64); 3007 3008 (*config_param).rd_vdl_dqn[0][4] = (uint16) ((value32_hi & 0xFFFF0000)>>16); 3009 (*config_param).rd_vdl_dqn[0][5] = (uint16) (value32_hi & 0xFFFF); 3010 (*config_param).rd_vdl_dqn[0][6] = (uint16) ((value32_lo & 0xFFFF0000)>>16); 3011 (*config_param).rd_vdl_dqn[0][7] = (uint16) (value32_lo & 0xFFFF); 3012 } 3013 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 3014 svalue = soc_property_get_str(unit, spn_DDR3_TUNE_RD_VDL_DQN0_BL1); 3015 if (svalue != NULL){ 3016 value64 = soc_parse_uint64(svalue); 3017 COMPILER_64_TO_32_LO(value32_lo,value64); 3018 COMPILER_64_TO_32_HI(value32_hi,value64); 3019 3020 (*config_param).rd_vdl_dqn[1][0] = (uint16) ((value32_hi & 0xFFFF0000)>>16); 3021 (*config_param).rd_vdl_dqn[1][1] = (uint16) (value32_hi & 0xFFFF); 3022 (*config_param).rd_vdl_dqn[1][2] = (uint16) ((value32_lo & 0xFFFF0000)>>16); 3023 (*config_param).rd_vdl_dqn[1][3] = (uint16) (value32_lo & 0xFFFF); 3024 } 3025 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 3026 svalue = soc_property_get_str(unit, spn_DDR3_TUNE_RD_VDL_DQN4_BL1); 3027 if (svalue != NULL){ 3028 value64 = soc_parse_uint64(svalue); 3029 COMPILER_64_TO_32_LO(value32_lo,value64); 3030 COMPILER_64_TO_32_HI(value32_hi,value64); 3031 3032 (*config_param).rd_vdl_dqn[1][4] = (uint16) ((value32_hi & 0xFFFF0000)>>16); 3033 (*config_param).rd_vdl_dqn[1][5] = (uint16) (value32_hi & 0xFFFF); 3034 (*config_param).rd_vdl_dqn[1][6] = (uint16) ((value32_lo & 0xFFFF0000)>>16); 3035 (*config_param).rd_vdl_dqn[1][7] = (uint16) (value32_lo & 0xFFFF); 3036 } 3037 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 3038 svalue = soc_property_get_str(unit, spn_DDR3_TUNE_RD_VDL_DQN0_BL2); 3039 if (svalue != NULL){ 3040 value64 = soc_parse_uint64(svalue); 3041 COMPILER_64_TO_32_LO(value32_lo,value64); 3042 COMPILER_64_TO_32_HI(value32_hi,value64); 3043 3044 (*config_param).rd_vdl_dqn[2][0] = (uint16) ((value32_hi & 0xFFFF0000)>>16); 3045 (*config_param).rd_vdl_dqn[2][1] = (uint16) (value32_hi & 0xFFFF); 3046 (*config_param).rd_vdl_dqn[2][2] = (uint16) ((value32_lo & 0xFFFF0000)>>16); 3047 (*config_param).rd_vdl_dqn[2][3] = (uint16) (value32_lo & 0xFFFF); 3048 } 3049 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 3050 svalue = soc_property_get_str(unit, spn_DDR3_TUNE_RD_VDL_DQN4_BL2); 3051 if (svalue != NULL){ 3052 value64 = soc_parse_uint64(svalue); 3053 COMPILER_64_TO_32_LO(value32_lo,value64); 3054 COMPILER_64_TO_32_HI(value32_hi,value64); 3055 3056 (*config_param).rd_vdl_dqn[2][4] = (uint16) ((value32_hi & 0xFFFF0000)>>16); 3057 (*config_param).rd_vdl_dqn[2][5] = (uint16) (value32_hi & 0xFFFF); 3058 (*config_param).rd_vdl_dqn[2][6] = (uint16) ((value32_lo & 0xFFFF0000)>>16); 3059 (*config_param).rd_vdl_dqn[2][7] = (uint16) (value32_lo & 0xFFFF); 3060 } 3061 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 3062 svalue = soc_property_get_str(unit, spn_DDR3_TUNE_RD_VDL_DQN0_BL3); 3063 if (svalue != NULL){ 3064 value64 = soc_parse_uint64(svalue); 3065 COMPILER_64_TO_32_LO(value32_lo,value64); 3066 COMPILER_64_TO_32_HI(value32_hi,value64); 3067 3068 (*config_param).rd_vdl_dqn[3][0] = (uint16) ((value32_hi & 0xFFFF0000)>>16); 3069 (*config_param).rd_vdl_dqn[3][1] = (uint16) (value32_hi & 0xFFFF); 3070 (*config_param).rd_vdl_dqn[3][2] = (uint16) ((value32_lo & 0xFFFF0000)>>16); 3071 (*config_param).rd_vdl_dqn[3][3] = (uint16) (value32_lo & 0xFFFF); 3072 } 3073 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 3074 svalue = soc_property_get_str(unit, spn_DDR3_TUNE_RD_VDL_DQN4_BL3); 3075 if (svalue != NULL){ 3076 value64 = soc_parse_uint64(svalue); 3077 COMPILER_64_TO_32_LO(value32_lo,value64); 3078 COMPILER_64_TO_32_HI(value32_hi,value64); 3079 3080 (*config_param).rd_vdl_dqn[3][4] = (uint16) ((value32_hi & 0xFFFF0000)>>16); 3081 (*config_param).rd_vdl_dqn[3][5] = (uint16) (value32_hi & 0xFFFF); 3082 (*config_param).rd_vdl_dqn[3][6] = (uint16) ((value32_lo & 0xFFFF0000)>>16); 3083 (*config_param).rd_vdl_dqn[3][7] = (uint16) (value32_lo & 0xFFFF); 3084 } 3085 /* END of uint16 rd_vdl_dqn[SHMOO_AND28_BYTES_PER_INTERFACE][SHMOO_AND28_BYTE]; */ 3086 3087 /* uint16 rd_vdl_dmp[SHMOO_AND28_BYTES_PER_INTERFACE] */ 3088 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 3089 svalue = soc_property_get_str(unit, spn_DDR3_TUNE_RD_VDL_DMP); 3090 if (svalue != NULL){ 3091 value64 = soc_parse_uint64(svalue); 3092 COMPILER_64_TO_32_LO(value32_lo,value64); 3093 COMPILER_64_TO_32_HI(value32_hi,value64); 3094 3095 (*config_param).rd_vdl_dmp[0] = (uint16) ((value32_hi & 0xFFFF0000)>>16); 3096 (*config_param).rd_vdl_dmp[1] = (uint16) (value32_hi & 0xFFFF); 3097 (*config_param).rd_vdl_dmp[2] = (uint16) ((value32_lo & 0xFFFF0000)>>16); 3098 (*config_param).rd_vdl_dmp[3] = (uint16) (value32_lo & 0xFFFF); 3099 } 3100 /*END of uint16 rd_vdl_dmp[SHMOO_AND28_BYTES_PER_INTERFACE] */ 3101 3102 /* uint16 rd_vdl_dmn[SHMOO_AND28_BYTES_PER_INTERFACE] */ 3103 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 3104 svalue = soc_property_get_str(unit, spn_DDR3_TUNE_RD_VDL_DMN); 3105 if (svalue != NULL){ 3106 value64 = soc_parse_uint64(svalue); 3107 COMPILER_64_TO_32_LO(value32_lo,value64); 3108 COMPILER_64_TO_32_HI(value32_hi,value64); 3109 3110 (*config_param).rd_vdl_dmn[0] = (uint16) ((value32_hi & 0xFFFF0000)>>16); 3111 (*config_param).rd_vdl_dmn[1] = (uint16) (value32_hi & 0xFFFF); 3112 (*config_param).rd_vdl_dmn[2] = (uint16) ((value32_lo & 0xFFFF0000)>>16); 3113 (*config_param).rd_vdl_dmn[3] = (uint16) (value32_lo & 0xFFFF); 3114 } 3115 /*END of uint16 rd_vdl_dmn[SHMOO_AND28_BYTES_PER_INTERFACE] */ 3116 3117 /* uint16 rd_en_vdl_cs[SHMOO_AND28_BYTES_PER_INTERFACE][SHMOO_AND28_PHY_NOF_CS] */ 3118 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 3119 svalue = soc_property_get_str(unit, spn_DDR3_TUNE_RD_EN_VDL_CS0); 3120 if (svalue != NULL){ 3121 value64 = soc_parse_uint64(svalue); 3122 COMPILER_64_TO_32_LO(value32_lo,value64); 3123 COMPILER_64_TO_32_HI(value32_hi,value64); 3124 3125 (*config_param).rd_en_vdl_cs[0][0] = (uint16) ((value32_hi & 0xFFFF0000)>>16); 3126 (*config_param).rd_en_vdl_cs[0][1] = (uint16) (value32_hi & 0xFFFF); 3127 (*config_param).rd_en_vdl_cs[1][0] = (uint16) ((value32_lo & 0xFFFF0000)>>16); 3128 (*config_param).rd_en_vdl_cs[1][1] = (uint16) (value32_lo & 0xFFFF); 3129 } 3130 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 3131 svalue = soc_property_get_str(unit, spn_DDR3_TUNE_RD_EN_VDL_CS1); 3132 if (svalue != NULL){ 3133 value64 = soc_parse_uint64(svalue); 3134 COMPILER_64_TO_32_LO(value32_lo,value64); 3135 COMPILER_64_TO_32_HI(value32_hi,value64); 3136 3137 (*config_param).rd_en_vdl_cs[2][0] = (uint16) ((value32_hi & 0xFFFF0000)>>16); 3138 (*config_param).rd_en_vdl_cs[2][1] = (uint16) (value32_hi & 0xFFFF); 3139 (*config_param).rd_en_vdl_cs[3][0] = (uint16) ((value32_lo & 0xFFFF0000)>>16); 3140 (*config_param).rd_en_vdl_cs[3][1] = (uint16) (value32_lo & 0xFFFF); 3141 } 3142 /* END of uint16 rd_en_vdl_cs[SHMOO_AND28_BYTES_PER_INTERFACE][SHMOO_AND28_PHY_NOF_CS]; */ 3143 3144 /* uint16 rd_en_dly_cyc[SHMOO_AND28_BYTES_PER_INTERFACE] */ 3145 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 3146 svalue = soc_property_get_str(unit, spn_DDR3_TUNE_RD_EN_DLY_CYC); 3147 if (svalue != NULL){ 3148 value64 = soc_parse_uint64(svalue); 3149 COMPILER_64_TO_32_LO(value32_lo,value64); 3150 COMPILER_64_TO_32_HI(value32_hi,value64); 3151 3152 (*config_param).rd_en_dly_cyc[0] = (uint16) ((value32_hi & 0xFFFF0000)>>16); 3153 (*config_param).rd_en_dly_cyc[1] = (uint16) (value32_hi & 0xFFFF); 3154 (*config_param).rd_en_dly_cyc[2] = (uint16) ((value32_lo & 0xFFFF0000)>>16); 3155 (*config_param).rd_en_dly_cyc[3] = (uint16) (value32_lo & 0xFFFF); 3156 } 3157 /*END of uint16 rd_en_dly_cyc[SHMOO_AND28_BYTES_PER_INTERFACE] */ 3158 3159 /* uint16 rd_control[SHMOO_AND28_BYTES_PER_INTERFACE] */ 3160 COMPILER_64_ZERO(value64);value32_lo = 0;value32_hi = 0; 3161 svalue = soc_property_get_str(unit, spn_DDR3_TUNE_RD_CONTROL); 3162 if (svalue != NULL){ 3163 value64 = soc_parse_uint64(svalue); 3164 COMPILER_64_TO_32_LO(value32_lo,value64); 3165 COMPILER_64_TO_32_HI(value32_hi,value64); 3166 3167 (*config_param).rd_control[0] = (uint8) ((value32_hi & 0xFF000000)>>24); 3168 (*config_param).rd_control[1] = (uint8) ((value32_hi & 0xFF0000)>>16); 3169 (*config_param).rd_control[2] = (uint8) ((value32_hi & 0xFF00)>>8); 3170 (*config_param).rd_control[3] = (uint8) (value32_hi & 0xFF); 3171 } 3172 /*END of uint16 rd_control[SHMOO_AND28_BYTES_PER_INTERFACE] */ 3173 return SOC_E_NONE; 3174 } 3175 3176 #endif