saber2.c (508098B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: saber2.c 8 * Purpose: 9 * Requires: 10 */ 11 12 13 #include <stddef.h> 14 #include <sal/core/boot.h> 15 16 17 #include <soc/katana2.h> 18 #include <soc/saber2.h> 19 #include <soc/trident.h> 20 #include <soc/bradley.h> 21 #include <soc/drv.h> 22 #include <soc/error.h> 23 #include <soc/debug.h> 24 #include <soc/mem.h> 25 #include <soc/hash.h> 26 #include <soc/shmoo_and28.h> 27 #include <soc/phy/ddr34.h> 28 #include <soc/mspi.h> 29 #include <soc/phyreg.h> 30 #include <soc/iproc.h> 31 #include <shared/bsl.h> 32 #include <soc/scache.h> 33 #include <soc/uc.h> 34 35 #ifdef BCM_SABER2_SUPPORT 36 #define _SOC_SB2_DEFIP_MAX_TCAMS 2 37 #define _SOC_SB2PLUS_DEFIP_MAX_TCAMS 6 38 #define _SOC_SB2_DEFIP_TCAM_DEPTH 1024 39 40 #include <bcm_int/esw/subport.h> 41 42 #define SB2_IDLE1 31 43 #ifdef BCM_WARM_BOOT_SUPPORT 44 45 /* Basic WB version. */ 46 #define BCM_WB_VERSION_1_1 SOC_SCACHE_VERSION(1,1) 47 48 /* Fixed issue in TDM sync. */ 49 #define BCM_WB_VERSION_1_2 SOC_SCACHE_VERSION(1,2) 50 51 /* Moved from magic number based versioning to scache version based system. */ 52 /* Fix to sync XL ge ports. */ 53 #define BCM_WB_VERSION_1_3 SOC_SCACHE_VERSION(1,3) 54 55 /* Fix to sync XL ge ports with pbmp_xport_ge set. */ 56 #define BCM_WB_VERSION_1_4 SOC_SCACHE_VERSION(1,4) 57 58 /* Default Version - Latest */ 59 #define BCM_WB_DEFAULT_VERSION BCM_WB_VERSION_1_4 60 61 /* Default Scache Partition - Latest */ 62 #define BCM_FLEXIO_SCACHE_DEFAULT_PARTITION 0x1 63 64 static uint8 scache_begin_magic_number[]={0xAA,0xBB,0xCC,0xDD}; 65 static uint8 scache_end_magic_number[]={0xDD,0xCC,0xBB,0xAA}; 66 static bcm56260_tdm_info_t sb2_scache_tdm_info={0}; 67 static uint32 sb2_scache_tdm[SB2_TDM_MAX_SIZE]={0}; 68 static uint32 sb2_scache_speed[SB2_MAX_PHYSICAL_PORTS]={0}; 69 static soc_port_details_t sb2_scache_port_details[SB2_MAX_PHYSICAL_PORTS+1]={{0}}; 70 static uint8 sb2_2p5g_ports[SB2_MAX_PHYSICAL_PORTS]={0}; 71 72 int _soc_saber2_flexio_scache_retrieve_part0(int unit); 73 74 #endif 75 76 #define PORTGROUP_SINGLE_MODE 4 77 #define PORTGROUP_DUAL_MODE 2 78 #define PORTGROUP_QUAD_MODE 1 79 80 /*TDM_A : 0:130MHz: 284 (41 * 7) Cycles Used */ 81 #define SB2_TDM_A_SIZE 284 82 #define SB2_TDM_A_FREQ 130 83 #define SB2_TDM_A_ROW 41 84 #define SB2_TDM_A_COL 7 85 86 /*TDM_AA : 1:130MHz: 140 (20 * 7) Cycles Used */ 87 #define SB2_TDM_AA_SIZE 141 88 #define SB2_TDM_AA_FREQ 130 89 #define SB2_TDM_AA_ROW 21 90 #define SB2_TDM_AA_COL 7 91 92 const static uint32 sb2_tdm_56460_AA_ref[SB2_TDM_AA_SIZE] = { 93 /*Col:1*/ /*Col:2*/ /*Col:3*/ /*Col:4*/ /*Col:5*/ /*Col:6*/ /*Col:7*/ 94 /*1*/ SB2_IDLE, 9, 25, 26, 27, 28, 7, 95 /*2*/ 4, 10, 25, 26, 27, 28, 8, 96 /*3*/ 1, 11, 25, 26, 27, 28, SB2_CMIC, 97 /*4*/ SB2_LPBK, 12, 25, 26, 27, 28, 21, 98 /*5*/ 2, 13, 25, 26, 27, 28, 22, 99 /*6*/ 3, 14, 25, 26, 27, 28, 17, 100 /*7*/ 5, 15, 25, 26, 27, 28, 18, 101 /*8*/ SB2_LPBK, 16, 25, 26, 27, 28, SB2_CMIC, 102 /*9*/ 6, 23, 25, 26, 27, 28, 19, 103 /*10*/ 4, 24, 25, 26, 27, 28, 20, 104 /*11*/ 3, 9, 25, 26, 27, 28, 7, 105 /*12*/ SB2_LPBK, 10, 25, 26, 27, 28, 8, 106 /*13*/ 1, 11, 25, 26, 27, 28, SB2_CMIC, 107 /*14*/ 4, 12, 25, 26, 27, 28, 21, 108 /*15*/ 2, 13, 25, 26, 27, 28, 22, 109 /*16*/ SB2_LPBK, 14, 25, 26, 27, 28, 17, 110 /*17*/ 5, 15, 25, 26, 27, 28, 18, 111 /*18*/ 3, 16, 25, 26, 27, 28, SB2_CMIC, 112 /*19*/ 6, 23, 25, 26, 27, 28, 19, 113 /*20*/ SB2_LPBK, 24, 25, 26, 27, 28, 20, 114 /*21*/ SB2_IDLE /* ================================= EMPTY ============================== */ 115 }; 116 117 /*TDM_A1: 2:24MHz: 13 (4 * 4) Cycles Used */ 118 #define SB2_TDM_A1_SIZE 13 119 #define SB2_TDM_A1_FREQ 24 120 #define SB2_TDM_A1_ROW 4 121 #define SB2_TDM_A1_COL 4 122 const static uint32 sb2_tdm_56263_A1_ref[SB2_TDM_A1_SIZE] = { 123 /*Col:1*/ /*Col:2*/ /*Col:3*/ /*Col:4*/ 124 /*1*/ 1, 5, SB2_LPBK, SB2_CMIC, 125 /*2*/ 2, 6, SB2_LPBK, SB2_CMIC, 126 /*3*/ 3, 7, SB2_LPBK, SB2_IDLE, 127 /*4*/ SB2_IDLE /* -------- EMPTY ------------ */ 128 }; 129 130 /*TDM_F 11:75MHz: 20 (5 * 4) Cycles Used */ 131 #define SB2_TDM_F_SIZE 20 132 #define SB2_TDM_F_FREQ 75 133 #define SB2_TDM_F_ROW 5 134 #define SB2_TDM_F_COL 4 135 const static uint32 sb2_tdm_56233_F_ref[SB2_TDM_F_SIZE] = { 136 /*Col:1*/ /*Col:2*/ /*Col:3*/ /*Col:4*/ 137 /*1*/ SB2_LPBK, 1, 21, 5, 138 /*2*/ SB2_CMIC, 4, 22, 5, 139 /*3*/ SB2_LPBK, 2, 23, 5, 140 /*4*/ SB2_CMIC, 3, 24, 5, 141 /*5*/ SB2_LPBK, 4, SB2_IDLE, SB2_IDLE 142 }; 143 144 145 /*TDM_A1A: 3:37MHz: 84 (21 * 4) Cycles Used */ 146 #define SB2_TDM_A1A_SIZE 84 147 #define SB2_TDM_A1A_FREQ 37 148 #define SB2_TDM_A1A_ROW 21 149 #define SB2_TDM_A1A_COL 4 150 const static uint32 sb2_tdm_56263_A1A_ref[SB2_TDM_A1A_SIZE] = { 151 /*Col:1*/ /*Col:2*/ /*Col:3*/ /*Col:4*/ 152 /*1*/ 1, 5, 9, SB2_LPBK, 153 /*2*/ 13, 2, 6, SB2_CMIC, 154 /*3*/ 10, 14, 3, SB2_LPBK, 155 /*4*/ 7, 11, 15, SB2_CMIC, 156 /*5*/ 4, 8, 12, SB2_LPBK, 157 /*6*/ 16, 1, 5, SB2_CMIC, 158 /*7*/ 9, 13, 2, SB2_LPBK, 159 /*8*/ 6, 10, 14, SB2_CMIC, 160 /*9*/ 3, 7, 11, SB2_LPBK, 161 /*10*/ 15, 4, 8, 12, 162 /*11*/ 16, SB2_IDLE, SB2_IDLE, 1, 163 /*12*/ 5, 9, SB2_LPBK, 13, 164 /*13*/ 2, 6, SB2_CMIC, 10, 165 /*14*/ 14, 3, SB2_LPBK, 7, 166 /*15*/ 11, 15, SB2_CMIC, 4, 167 /*16*/ 8, 12, SB2_LPBK, 16, 168 /*17*/ 1, 5, SB2_CMIC, 9, 169 /*18*/ 13, 2, SB2_LPBK, 6, 170 /*19*/ 10, 14, SB2_CMIC, 3, 171 /*20*/ 7, 11, SB2_LPBK, 15, 172 /*21*/ 4, 8, 12, 16, 173 }; 174 175 /*TDM_B: 4:118MHz: 133 (23 * 6) Cycles Used */ 176 #define SB2_TDM_B_SIZE 133 177 #define SB2_TDM_B_FREQ 118 178 #define SB2_TDM_B_ROW 23 179 #define SB2_TDM_B_COL 6 180 const static uint32 sb2_tdm_56260_B_ref[SB2_TDM_B_SIZE] = { 181 /*Col:1*/ /*Col:2*/ /*Col:3*/ /*Col:4*/ /*Col:5*/ /*Col:6*/ 182 /*1*/ SB2_LPBK, 1, 27, 5, 25, 21, 183 /*2*/ SB2_LPBK, 2, 6, 27, SB2_LPBK, 25, 184 /*3*/ 22, 3, SB2_LPBK, 27, 7, 25, 185 /*4*/ 23, 4, SB2_LPBK, 27, 8, 25, 186 /*5*/ 24, SB2_CMIC, 1, SB2_LPBK, 27, 5, 187 /*6*/ 25, SB2_LPBK, 21, 2, 27, SB2_LPBK, 188 /*7*/ 25, 6, 22, SB2_LPBK, 27, 3, 189 /*8*/ 25, 7, 23, SB2_LPBK, 27, 4, 190 /*9*/ 25, 8, 24, SB2_LPBK, SB2_CMIC, 27, 191 /*10*/ 1, 25, SB2_LPBK, 5, 21, 27, 192 /*11*/ SB2_LPBK, 25, 2, 6, SB2_LPBK, 27, 193 /*12*/ 22, 25, SB2_LPBK, 3, 7, 27, 194 /*13*/ 23, 25, 4, SB2_LPBK, 8, 24, 195 /*14*/ 27, SB2_CMIC, 25, SB2_LPBK, 1, 5, 196 /*15*/ 27, SB2_LPBK, 25, 21, 2, 6, 197 /*16*/ 27, SB2_LPBK, 25, 22, 3, 7, 198 /*17*/ 27, SB2_LPBK, 25, 23, 4, 8, 199 /*18*/ SB2_LPBK, 27, 24, 25, SB2_IDLE, SB2_IDLE, 200 /*19*/ SB2_LPBK, 27, 1, 25, 5, SB2_LPBK, 201 /*20*/ 21, 27, 2, 25, 6, SB2_LPBK, 202 /*21*/ 22, 27, 3, 25, 7, 23, 203 /*22*/ SB2_LPBK, 4, 27, 8, 25, 24, 204 /*23*/ SB2_CMIC /* ------------------------- EMPTY ---------------------------- */ 205 }; 206 /*TDM_B1: 5:118MHz: 120 (20 * 6) Cycles Used */ 207 #define SB2_TDM_B1_SIZE 120 208 #define SB2_TDM_B1_FREQ 118 209 #define SB2_TDM_B1_ROW 20 210 #define SB2_TDM_B1_COL 6 211 const static uint32 sb2_tdm_56260_B1_ref[SB2_TDM_B1_SIZE] = { 212 /*Col:1*/ /*Col:2*/ /*Col:3*/ /*Col:4*/ /*Col:5*/ /*Col:6*/ 213 /*1*/ SB2_IDLE, 1, 5, 25, 27, 21, 214 /*2*/ SB2_LPBK, 1, 5, 25, 27, 22, 215 /*3*/ SB2_CMIC, 1, 5, 25, 27, 23, 216 /*4*/ 28, 1, 5, 25, 27, 24, 217 /*5*/ 26, 1, 5, 25, 27, 21, 218 /*6*/ SB2_LPBK, 1, 5, 25, 27, 22, 219 /*7*/ SB2_IDLE1, 1, 5, 25, 27, 23, 220 /*8*/ SB2_CMIC, 1, 5, 25, 27, 24, 221 /*9*/ SB2_IDLE1, 1, 5, 25, 27, 21, 222 /*10*/ SB2_LPBK, 1, 5, 25, 27, 22, 223 /*11*/ 28, 1, 5, 25, 27, 23, 224 /*12*/ SB2_IDLE1, 1, 5, 25, 27, 24, 225 /*13*/ SB2_CMIC, 1, 5, 25, 27, 21, 226 /*14*/ SB2_LPBK, 1, 5, 25, 27, 22, 227 /*15*/ 26, 1, 5, 25, 27, 23, 228 /*16*/ SB2_CMIC, 1, 5, 25, 27, 24, 229 /*17*/ 1, 5, 25, 27, 21, SB2_LPBK, 230 /*18*/ 1, 5, 25, 27, 22, SB2_CMIC, 231 /*19*/ 1, 5, 25, 27, 23, 28, 232 /*20*/ 1, 5, 25, 27, 24, SB2_IDLE 233 }; 234 235 /*TDM_B1A: 6:118MHz: 121 (21 * 6) Cycles Used */ 236 #define SB2_TDM_B1A_SIZE 121 237 #define SB2_TDM_B1A_FREQ 118 238 #define SB2_TDM_B1A_ROW 21 239 #define SB2_TDM_B1A_COL 6 240 const static uint32 sb2_tdm_56462_B1A_ref[SB2_TDM_B1A_SIZE] = { 241 /*Col:1*/ /*Col:2*/ /*Col:3*/ /*Col:4*/ /*Col:5*/ /*Col:6*/ 242 /*1*/ SB2_IDLE, 1, 5, 9, 25, 27, 243 /*2*/ SB2_LPBK, 1, 5, 10, 25, 27, 244 /*3*/ 17, 1, 5, 11, 25, 27, 245 /*4*/ SB2_CMIC, 1, 5, 12, 25, 27, 246 /*5*/ 18, 1, 5, 13, 25, 27, 247 /*6*/ SB2_LPBK, 1, 5, 14, 25, 27, 248 /*7*/ 19, 1, 5, 15, 25, 27, 249 /*8*/ SB2_CMIC, 1, 5, 16, 25, 27, 250 /*9*/ 20, 1, 5, 26, 25, 27, 251 /*10*/ SB2_LPBK, 1, 5, 28, 25, 27, 252 /*11*/ SB2_CMIC, 1, 5, 9, 25, 27, 253 /*12*/ SB2_LPBK, 1, 5, 10, 25, 27, 254 /*13*/ 17, 1, 5, 11, 25, 27, 255 /*14*/ SB2_CMIC, 1, 5, 12, 25, 27, 256 /*15*/ 18, 1, 5, 13, 25, 27, 257 /*16*/ SB2_LPBK, 1, 5, 14, 25, 27, 258 /*17*/ 19, 1, 5, 15, 25, 27, 259 /*18*/ SB2_CMIC, 1, 5, 16, 25, 27, 260 /*19*/ 20, 1, 5, 26, 25, 27, 261 /*20*/ SB2_LPBK, 1, 5, 28, 25, 27, 262 /*21*/ SB2_IDLE 263 }; 264 265 /*TDM_C,C1,C2: 7:130MHz: 141 (21 * 6) Cycles Used */ 266 #define SB2_TDM_C_SIZE 141 267 #define SB2_TDM_C_FREQ 130 268 #define SB2_TDM_C_ROW 21 269 #define SB2_TDM_C_COL 7 270 const static uint32 sb2_tdm_56460_C_ref[SB2_TDM_C_SIZE] = { 271 /*Col:1*/ /*Col:2*/ /*Col:3*/ /*Col:4*/ /*Col:5*/ /*Col:6*/ /*Col:7*/ 272 /*1*/ SB2_IDLE, 1, 5, 9, 21, 25, 27, 273 /*2*/ SB2_LPBK, 1, 5, 10, 21, 25, 27, 274 /*3*/ 17, 1, 5, 11, 21, 25, 27, 275 /*4*/ SB2_CMIC, 1, 5, 12, 21, 25, 27, 276 /*5*/ 18, 1, 5, 13, 21, 25, 27, 277 /*6*/ SB2_LPBK, 1, 5, 14, 21, 25, 27, 278 /*7*/ 19, 1, 5, 15, 21, 25, 27, 279 /*8*/ SB2_CMIC, 1, 5, 16, 21, 25, 27, 280 /*9*/ 20, 1, 5, 26, 21, 25, 27, 281 /*10*/ SB2_LPBK, 1, 5, 28, 21, 25, 27, 282 /*11*/ SB2_CMIC, 1, 5, 9, 21, 25, 27, 283 /*12*/ SB2_LPBK, 1, 5, 10, 21, 25, 27, 284 /*13*/ 17, 1, 5, 11, 21, 25, 27, 285 /*14*/ SB2_CMIC, 1, 5, 12, 21, 25, 27, 286 /*15*/ 18, 1, 5, 13, 21, 25, 27, 287 /*16*/ SB2_LPBK, 1, 5, 14, 21, 25, 27, 288 /*17*/ 19, 1, 5, 15, 21, 25, 27, 289 /*18*/ SB2_CMIC, 1, 5, 16, 21, 25, 27, 290 /*19*/ 20, 1, 5, 26, 21, 25, 27, 291 /*20*/ SB2_LPBK, 1, 5, 28, 21, 25, 27, 292 /*21*/ SB2_IDLE /* -------------------- EMPTY ------------------------- */ 293 }; 294 /*TDM_C,C1,C2: 7:130MHz: 141 (21 * 6) Cycles Used */ 295 #define SB2_TDM_C1_SIZE 141 296 #define SB2_TDM_C1_FREQ 130 297 #define SB2_TDM_C1_ROW 21 298 #define SB2_TDM_C1_COL 7 299 const static uint32 sb2_tdm_56460_C1_ref[SB2_TDM_C1_SIZE] = { 300 /*Col:1*/ /*Col:2*/ /*Col:3*/ /*Col:4*/ /*Col:5*/ /*Col:6*/ /*Col:7*/ 301 /*1*/ SB2_IDLE, 1, 5, 9, 13, 25, 27, 302 /*2*/ SB2_LPBK, 1, 5, 9, 14, 25, 27, 303 /*3*/ 17, 1, 5, 9, 15, 25, 27, 304 /*4*/ SB2_CMIC, 1, 5, 9, 16, 25, 27, 305 /*5*/ 18, 1, 5, 9, 13, 25, 27, 306 /*6*/ SB2_LPBK, 1, 5, 9, 14, 25, 27, 307 /*7*/ 26, 1, 5, 9, 15, 25, 27, 308 /*8*/ SB2_CMIC, 1, 5, 9, 16, 25, 27, 309 /*9*/ 28, 1, 5, 9, 13, 25, 27, 310 /*10*/ SB2_LPBK, 1, 5, 9, 14, 25, 27, 311 /*11*/ SB2_CMIC, 1, 5, 9, 15, 25, 27, 312 /*12*/ SB2_LPBK, 1, 5, 9, 16, 25, 27, 313 /*13*/ 17, 1, 5, 9, 13, 25, 27, 314 /*14*/ SB2_CMIC, 1, 5, 9, 14, 25, 27, 315 /*15*/ 18, 1, 5, 9, 15, 25, 27, 316 /*16*/ SB2_LPBK, 1, 5, 9, 16, 25, 27, 317 /*17*/ 26, 1, 5, 9, 13, 25, 27, 318 /*18*/ SB2_CMIC, 1, 5, 9, 14, 25, 27, 319 /*19*/ 28, 1, 5, 9, 15, 25, 27, 320 /*20*/ SB2_LPBK, 1, 5, 9, 16, 25, 27, 321 /*21*/ SB2_IDLE 322 }; 323 /*TDM_C,C1,C2: 7:130MHz: 141 (21 * 6) Cycles Used */ 324 #define SB2_TDM_C2_SIZE 141 325 #define SB2_TDM_C2_FREQ 130 326 #define SB2_TDM_C2_ROW 21 327 #define SB2_TDM_C2_COL 7 328 const static uint32 sb2_tdm_56460_C2_ref[SB2_TDM_C2_SIZE] = { 329 /*Col:1*/ /*Col:2*/ /*Col:3*/ /*Col:4*/ /*Col:5*/ /*Col:6*/ /*Col:7*/ 330 /*1*/ SB2_IDLE, 1, 5, 9, 13, 17, 21, 331 /*2*/ SB2_LPBK, 1, 5, 9, 14, 17, 21, 332 /*3*/ 25, 1, 5, 9, 15, 17, 21, 333 /*4*/ SB2_CMIC, 1, 5, 9, 16, 17, 21, 334 /*5*/ 26, 1, 5, 9, 13, 17, 21, 335 /*6*/ SB2_LPBK, 1, 5, 9, 14, 17, 21, 336 /*7*/ 27, 1, 5, 9, 15, 17, 21, 337 /*8*/ SB2_CMIC, 1, 5, 9, 16, 17, 21, 338 /*9*/ 28, 1, 5, 9, 13, 17, 21, 339 /*10*/ SB2_LPBK, 1, 5, 9, 14, 17, 21, 340 /*11*/ SB2_CMIC, 1, 5, 9, 15, 17, 21, 341 /*12*/ SB2_LPBK, 1, 5, 9, 16, 17, 21, 342 /*13*/ 25, 1, 5, 9, 13, 17, 21, 343 /*14*/ SB2_CMIC, 1, 5, 9, 14, 17, 21, 344 /*15*/ 26, 1, 5, 9, 15, 17, 21, 345 /*16*/ SB2_LPBK, 1, 5, 9, 16, 17, 21, 346 /*17*/ 27, 1, 5, 9, 13, 17, 21, 347 /*18*/ SB2_CMIC, 1, 5, 9, 14, 17, 21, 348 /*19*/ 28, 1, 5, 9, 15, 17, 21, 349 /*20*/ SB2_LPBK, 1, 5, 9, 16, 17, 21, 350 /*21*/ SB2_IDLE 351 }; 352 353 /*TDM_D 8:130MHz: 168 (28 * 6) Cycles Used */ 354 #define SB2_TDM_D_SIZE 168 355 #define SB2_TDM_D_FREQ 130 356 #define SB2_TDM_D_ROW 28 357 #define SB2_TDM_D_COL 6 358 const static uint32 sb2_tdm_56460_D_ref[SB2_TDM_D_SIZE] = { 359 /*Col:1*/ /*Col:2*/ /*Col:3*/ /*Col:4*/ /*Col:5*/ /*Col:6*/ 360 /*1*/ SB2_IDLE, 27, SB2_LPBK, 25, 21, 1, 361 /*2*/ 17, 5, SB2_LPBK, 27, 25, 21, 362 /*3*/ 1, SB2_CMIC, SB2_LPBK, 20, 27, 25, 363 /*4*/ 21, 1, SB2_LPBK, 28, 27, 25, 364 /*5*/ 21, 1, SB2_LPBK, 18, 7, 27, 365 /*6*/ 25, 21, SB2_LPBK, 1, 19, 6, 366 /*7*/ 27, 25, SB2_LPBK, 21, 1, 8, 367 /*8*/ 26, 27, SB2_LPBK, 25, 21, 1, 368 /*9*/ SB2_CMIC, SB2_IDLE1, SB2_LPBK, 27, 25, 21, 369 /*10*/ 1, SB2_IDLE1, SB2_LPBK, SB2_CMIC, 27, 25, 370 /*11*/ 21, 1, SB2_LPBK, 5, 27, 25, 371 /*12*/ 21, 1, SB2_LPBK, 20, SB2_CMIC, 27, 372 /*13*/ 25, 21, SB2_LPBK, 1, 17, 28, 373 /*14*/ 27, 25, SB2_LPBK, 21, 1, 7, 374 /*15*/ 18, 27, SB2_LPBK, 25, 21, 1, 375 /*16*/ 19, 6, SB2_LPBK, 27, 25, 21, 376 /*17*/ 1, 26, SB2_LPBK, 8, 27, 25, 377 /*18*/ 21, 1, SB2_LPBK, SB2_CMIC, 27, 25, 378 /*19*/ 21, 1, SB2_LPBK, SB2_IDLE1, SB2_CMIC, 27, 379 /*20*/ 25, 21, SB2_LPBK, 1, SB2_IDLE1, 5, 380 /*21*/ 27, 25, SB2_LPBK, 21, 1, SB2_CMIC, 381 /*22*/ 20, 27, SB2_LPBK, 25, 21, 1, 382 /*23*/ 17, 28, SB2_LPBK, 27, 25, 21, 383 /*24*/ 1, 7, SB2_LPBK, 18, 27, 25, 384 /*25*/ 21, 1, SB2_LPBK, 6, 27, 25, 385 /*26*/ 21, 1, SB2_LPBK, SB2_CMIC, 19, 27, 386 /*27*/ 25, 21, SB2_LPBK, 1, 8, 26, 387 /*28*/ 27, 25, SB2_LPBK, 21, 1, SB2_IDLE 388 }; 389 /*TDM_E,E1,E3 9:75MHz: 81 (21 * 4) Cycles Used */ 390 #define SB2_TDM_E_SIZE 81 391 #define SB2_TDM_E_FREQ 75 392 #define SB2_TDM_E_ROW 21 393 #define SB2_TDM_E_COL 4 394 const static uint32 sb2_tdm_56463_E_ref[SB2_TDM_E_SIZE] = { 395 /*Col:1*/ /*Col:2*/ /*Col:3*/ /*Col:4*/ 396 /*1*/ SB2_IDLE, 1, 25, 27, 397 /*2*/ SB2_LPBK, 2, 25, 27, 398 /*3*/ 9, 3, 25, 27, 399 /*4*/ SB2_CMIC, 4, 25, 27, 400 /*5*/ 10, 5, 25, 27, 401 /*6*/ SB2_LPBK, 6, 25, 27, 402 /*7*/ 11, 7, 25, 27, 403 /*8*/ SB2_CMIC, 8, 25, 27, 404 /*9*/ 12, 26, 25, 27, 405 /*10*/ SB2_LPBK, 28, 25, 27, 406 /*11*/ SB2_CMIC, 1, 25, 27, 407 /*12*/ SB2_LPBK, 2, 25, 27, 408 /*13*/ 9, 3, 25, 27, 409 /*14*/ SB2_CMIC, 4, 25, 27, 410 /*15*/ 10, 5, 25, 27, 411 /*16*/ SB2_LPBK, 6, 25, 27, 412 /*17*/ 11, 7, 25, 27, 413 /*18*/ SB2_CMIC, 8, 25, 27, 414 /*19*/ 12, 26, 25, 27, 415 /*20*/ SB2_LPBK, 28, 25, 27, 416 /*21*/ SB2_IDLE 417 }; 418 /*TDM_E,E1,E3 9:75MHz: 81 (21 * 4) Cycles Used */ 419 #define SB2_TDM_E1_SIZE 81 420 #define SB2_TDM_E1_FREQ 75 421 #define SB2_TDM_E1_ROW 21 422 #define SB2_TDM_E1_COL 4 423 const static uint32 sb2_tdm_56463_E1_ref[SB2_TDM_E1_SIZE] = { 424 /*Col:1*/ /*Col:2*/ /*Col:3*/ /*Col:4*/ 425 /*1*/ SB2_IDLE, 1, 11, 25, 426 /*2*/ SB2_LPBK, 2, 12, 26, 427 /*3*/ 21, 3, 13, 27, 428 /*4*/ SB2_CMIC, 4, 14, 28, 429 /*5*/ 22, 5, 15, 25, 430 /*6*/ SB2_LPBK, 6, 16, 26, 431 /*7*/ 23, 7, 17, 27, 432 /*8*/ SB2_CMIC, 8, 18, 28, 433 /*9*/ 24, 9, 19, 25, 434 /*10*/ SB2_LPBK, 10, 20, 26, 435 /*11*/ SB2_CMIC, 1, 11, 27, 436 /*12*/ SB2_LPBK, 2, 12, 28, 437 /*13*/ 21, 3, 13, 25, 438 /*14*/ SB2_CMIC, 4, 14, 26, 439 /*15*/ 22, 5, 15, 27, 440 /*16*/ SB2_LPBK, 6, 16, 28, 441 /*17*/ 23, 7, 17, 25, 442 /*18*/ SB2_CMIC, 8, 18, 26, 443 /*19*/ 24, 9, 19, 27, 444 /*20*/ SB2_LPBK, 10, 20, 28, 445 /*21*/ SB2_IDLE 446 }; 447 /*TDM_E,E1,E3 9:75MHz: 81 (21 * 4) Cycles Used */ 448 #define SB2_TDM_E3_SIZE 81 449 #define SB2_TDM_E3_FREQ 75 450 #define SB2_TDM_E3_ROW 21 451 #define SB2_TDM_E3_COL 4 452 const static uint32 sb2_tdm_56463_E3_ref[SB2_TDM_E3_SIZE] = { 453 /*Col:1*/ /*Col:2*/ /*Col:3*/ /*Col:4*/ 454 /*1*/ SB2_IDLE, 1, 5, 25, 455 /*2*/ SB2_LPBK, 1, 5, 25, 456 /*3*/ 21, 1, 5, 25, 457 /*4*/ SB2_CMIC, 1, 5, 25, 458 /*5*/ 22, 1, 5, 25, 459 /*6*/ SB2_LPBK, 1, 5, 25, 460 /*7*/ 23, 1, 5, 25, 461 /*8*/ SB2_CMIC, 1, 5, 25, 462 /*9*/ 24, 1, 5, 25, 463 /*10*/ SB2_LPBK, 1, 5, 25, 464 /*11*/ SB2_CMIC, 1, 5, 25, 465 /*12*/ SB2_LPBK, 1, 5, 25, 466 /*13*/ 21, 1, 5, 25, 467 /*14*/ SB2_CMIC, 1, 5, 25, 468 /*15*/ 22, 1, 5, 25, 469 /*16*/ SB2_LPBK, 1, 5, 25, 470 /*17*/ 23, 1, 5, 25, 471 /*18*/ SB2_CMIC, 1, 5, 25, 472 /*19*/ 24, 1, 5, 25, 473 /*20*/ SB2_LPBK, 1, 5, 25, 474 /*21*/ SB2_IDLE 475 }; 476 477 /*TDM_EA 10:75MHz: 16 (4 * 4) Cycles Used */ 478 #define SB2_TDM_EA_SIZE 16 479 #define SB2_TDM_EA_FREQ 75 480 #define SB2_TDM_EA_ROW 4 481 #define SB2_TDM_EA_COL 4 482 const static uint32 sb2_tdm_56260_EA_ref[SB2_TDM_EA_SIZE] = { 483 /*Col:1*/ /*Col:2*/ /*Col:3*/ /*Col:4*/ 484 /*1*/ SB2_IDLE, 1, 5, SB2_LPBK, 485 /*2*/ 25, 2, 6, 27, 486 /*3*/ 26, 3, 7, 28, 487 /*4*/ SB2_CMIC, 4, 8, SB2_IDLE 488 }; 489 490 uint32 sb2_current_tdm[SB2_TDM_MAX_SIZE]={0}; 491 uint32 sb2_current_tdm_size=0; 492 493 int block_max_startaddr[SB2_MAX_BLOCKS]={0}; 494 int block_max_endaddr[SB2_MAX_BLOCKS]={0}; 495 496 const static sb2_port_speeds_t sb2_port_speeds_56260_0 = {{0,0,0,0}}; 497 const static sb2_port_speeds_t sb2_port_speeds_56460_1 = { 498 {10000,2500,0,2500},{10000,2500,0,2500},{10000,2500,0,2500}, 499 {10000,2500,0,2500},{10000,2500,0,2500},{10000,2500,0,2500}, 500 {10000,10000,0,10000}}; 501 502 const static sb2_port_speeds_t sb2_port_speeds_56260_1 = { 503 {10000,2500,0,2500},{10000,2500,0,2500},{0,0,0,0}, 504 {0,0,0,0},{0,0,0,0},{10000,2500,0,2500}, 505 {10000,10000,0,2500}}; 506 507 const static sb2_port_speeds_t sb2_port_speeds_56233_1 = { 508 {1000,1000,1000,2500},{0,0,0,0},{0,0,0,0}, 509 {0,0,0,0},{0,0,0,0},{1000,1000,1000,1000}, 510 {0,0,0,0}}; 511 512 sb2_port_speeds_t *sb2_port_speeds[SOC_MAX_NUM_DEVICES]={NULL}; 513 #define SB2_QUEUE_FLUSH_RATE_MANTISSA 1023 514 #define SB2_QUEUE_FLUSH_RATE_EXP 14 515 #define SB2_QUEUE_FLUSH_BURST_MANTISSA 124 516 #define SB2_QUEUE_FLUSH_BURST_EXP 14 517 #define SB2_QUEUE_FLUSH_CYCLE_SEL 0 518 519 static uint32 sb2_tdm_A_56260_0[SB2_TDM_A_SIZE]={0}; /* Dummy */ 520 const static soc_port_details_t sb2_port_details_56260_0[]={{0,0,0,0}}; 521 const static sb2_speed_t sb2_speed_56260_0 = {0}; 522 soc_port_details_t *sb2_selected_port_details; 523 soc_port_details_t *sb2_selected_port_details_orig; 524 525 /* TDM, Port speeds and port details for all IO */ 526 527 528 /* 56460_1: bcm5626x_config = 1 */ 529 /* 24xGE + 4xHGs11 4xGE 4xGE 4xGE + 4xGE 4xGE 4xGE 4xGE N4 2.5G(LPBK) */ 530 static uint32 sb2_tdm_A_56460_1[SB2_TDM_AA_SIZE]={0}; /* Filled up Runtime */ 531 const static sb2_speed_t sb2_speed_56460_1 = { 532 1000, 1000, 1000, 1000, /* 1 - 4 */ 533 1000, 1000, 1000, 1000, /* 5 - 8 */ 534 1000, 1000, 1000, 1000, /* 9 - 12 */ 535 1000, 1000, 1000, 1000, /* 13 - 16 */ 536 1000, 1000, 1000, 1000, /* 17 - 20 */ 537 1000, 1000, 1000, 1000, /* 21 - 24 */ 538 10000, 10000, 10000, 10000 /* 25 - 28 */ 539 }; 540 const static soc_port_details_t sb2_port_details_56460_1[SB2_MAX_PHYSICAL_PORTS+1]={ 541 {1,4,1,GE_PORT,1000}, 542 {5,8,1,GE_PORT,1000}, 543 {9,12,1,GE_PORT,1000}, 544 {13,16,1,GE_PORT,1000}, 545 {17,20,1,GE_PORT,1000}, 546 {21,24,1,GE_PORT,1000}, 547 {25,28,1,HG_PORT,10000}, 548 {0,0,0,0}, 549 {0,0,0,0} /* End */ 550 }; 551 552 /* 56460_2: bcm5626x_config = 2 */ 553 /* F.XAUI F.XAUI F.XAUI F.XAUI F.XAUI F.XAUI 4xGE 2.5G(LPBK) */ 554 static uint32 sb2_tdm_C2_56460_2[SB2_TDM_C2_SIZE]={0}; /* Filled up Runtime */ 555 const static sb2_speed_t sb2_speed_56460_2 = { 556 10000, 0000, 0000, 0000, /* 1 - 4 */ 557 10000, 0000, 0000, 0000, /* 5 - 8 */ 558 10000, 0000, 0000, 0000, /* 9 - 12 */ 559 10000, 0000, 0000, 0000, /* 13 - 16 */ 560 10000, 0000, 0000, 0000, /* 17 - 20 */ 561 10000, 0000, 0000, 0000, /* 21 - 24 */ 562 1000, 1000, 1000, 1000 /* 25 - 28 */ 563 }; 564 const static soc_port_details_t sb2_port_details_56460_2[SB2_MAX_PHYSICAL_PORTS+1]={ 565 {1,4,4,XE_PORT,10000}, 566 {5,8,4,XE_PORT,10000}, 567 {9,12,4,XE_PORT,10000}, 568 {13,16,4,XE_PORT,10000}, 569 {17,20,4,XE_PORT,10000}, 570 {21,24,4,XE_PORT,10000}, 571 {25,28,1,GE_PORT,1000}, 572 {0,0,0,0}, 573 {0,0,0,0} /* End */ 574 }; 575 576 /* 56460_3: bcm5626x_config = 3 */ 577 /* 2xF.XAUI + 12xGE + 1xF.XAUI + [2xXFI + 2xGE] + LPBK-2.5G */ 578 static uint32 sb2_tdm_C_56460_3[SB2_TDM_C_SIZE]={0}; /* Filled up Runtime */ 579 const static sb2_speed_t sb2_speed_56460_3 = { 580 10000, 0000, 0000, 0000, /* 1 - 4 */ 581 10000, 0000, 0000, 0000, /* 5 - 8 */ 582 1000, 1000, 1000, 1000, /* 9 - 12 */ 583 1000, 1000, 1000, 1000, /* 13 - 16 */ 584 1000, 1000, 1000, 1000, /* 17 - 20 */ 585 10000, 0000, 0000, 0000, /* 21 - 24 */ 586 10000, 1000,10000, 1000 /* 25 - 28 */ 587 }; 588 const static soc_port_details_t sb2_port_details_56460_3[SB2_MAX_PHYSICAL_PORTS+1]={ 589 {1,4,4, XE_PORT,10000}, 590 {5,8,4, XE_PORT,10000}, 591 {9,12,1,GE_PORT,1000}, 592 {13,16,1,GE_PORT,1000}, 593 {17,20,1,GE_PORT,1000}, 594 {21,24,4,XE_PORT,10000}, 595 {25,27,2,XE_PORT,10000}, 596 {26,28,2,GE_PORT,1000}, 597 {0,0,0,0} /* End */ 598 }; 599 600 /* 56460_4: bcm5626x_config = 4 */ 601 /* 3x F.XAUI + 2x1G + .. 1xF.XAUI + [2xXFI + 2x1G] + LPBK-2.5G */ 602 static uint32 sb2_tdm_C1_56460_4[SB2_TDM_C1_SIZE]={0}; /* Filled up Runtime */ 603 const static sb2_speed_t sb2_speed_56460_4 = { 604 10000, 0000, 0000, 0000, /* 1 - 4 */ 605 10000, 0000, 0000, 0000, /* 5 - 8 */ 606 10000, 0000, 0000, 0000, /* 9 - 12 */ 607 1000, 0000, 1000, 0000, /* 13 - 16 */ 608 0000, 0000, 0000, 0000, /* 17 - 20 */ 609 10000, 0000, 0000, 0000, /* 21 - 24 */ 610 10000, 1000,10000, 1000 /* 25 - 28 */ 611 }; 612 const static soc_port_details_t sb2_port_details_56460_4[SB2_MAX_PHYSICAL_PORTS+1]={ 613 {1,4,4, XE_PORT,10000}, 614 {5,8,4, XE_PORT,10000}, 615 {9,12,4, XE_PORT,10000}, 616 {13,16,2,GE_PORT,1000}, 617 {17,20,4,0,0}, 618 {21,24,4,XE_PORT,10000}, 619 {25,27,2,XE_PORT,10000}, 620 {26,28,2,GE_PORT,1000}, 621 {0,0,0,0} /* End */ 622 }; 623 /* 56460_5: bcm5626x_config = 5 */ 624 /* F.XAUI F.XAUI F.XAUI - 4xGE F.XAUI N2 */ 625 626 static uint32 sb2_tdm_C1_56460_5[SB2_TDM_C1_SIZE]={0}; /* Filled up Runtime */ 627 const static sb2_speed_t sb2_speed_56460_5 = { 628 10000, 0000, 0000, 0000, /* 1 - 4 */ 629 10000, 0000, 0000, 0000, /* 5 - 8 */ 630 10000, 0000, 0000, 0000, /* 9 - 12 */ 631 0000, 0000, 0000, 0000, /* 13 - 16 */ 632 1000, 1000, 1000, 1000, /* 17 - 20 */ 633 10000, 0000, 0000, 0000, /* 21 - 24 */ 634 10000, 0000,10000, 0000 /* 25 - 28 */ 635 }; 636 const static soc_port_details_t sb2_port_details_56460_5[SB2_MAX_PHYSICAL_PORTS+1]={ 637 {1,4,4, XE_PORT,10000}, 638 {5,8,4, XE_PORT,10000}, 639 {9,12,4, XE_PORT,10000}, 640 {13,16,1, 0, 0}, 641 {17,20,1,GE_PORT,1000}, 642 {21,24,4,XE_PORT,10000}, 643 {25,28,2,HG_PORT,10000}, 644 {0,0,0,0}, 645 {0,0,0,0} /* End */ 646 }; 647 648 /* 56460_6: bcm5626x_config = 6 */ 649 /* F.XAUI 4xGE - - 4xGE F.XAUI N4s 12.5G */ 650 651 static uint32 sb2_tdm_D_56460_6[SB2_TDM_D_SIZE]={0}; /* Filled up Runtime */ 652 const static sb2_speed_t sb2_speed_56460_6 = { 653 10000, 0000, 0000, 0000, /* 1 - 4 */ 654 1000, 1000, 1000, 1000, /* 5 - 8 */ 655 0000, 0000, 0000, 0000, /* 9 - 12 */ 656 0000, 0000, 0000, 0000, /* 13 - 16 */ 657 1000, 1000, 1000, 1000, /* 17 - 20 */ 658 10000, 0000, 0000, 0000, /* 21 - 24 */ 659 10000, 1000,10000, 1000 /* 25 - 28 */ 660 }; 661 const static soc_port_details_t sb2_port_details_56460_6[SB2_MAX_PHYSICAL_PORTS+1]={ 662 {1,4,4, XE_PORT,10000}, 663 {5,8,1, GE_PORT,1000}, 664 {9,12,4, 0, 0}, 665 {13,16,4, 0, 0}, 666 {17,20,1, GE_PORT,1000}, 667 {21,24,4,XE_PORT,10000}, 668 {25,27,2,XE_PORT,10000}, 669 {26,28,2,GE_PORT,1000}, 670 {0,0,0,0} /* End */ 671 }; 672 /* 56462_1: bcm5626x_config = 1 */ 673 /* F.XAUI F.XAUI F.XAUI 4xGE 4xGE 4xGE F.XAUI 2.5G B1A */ 674 static uint32 sb2_tdm_B1A_56462_1[SB2_TDM_B1A_SIZE]={0}; /* Filled up Runtime */ 675 const static sb2_speed_t sb2_speed_56462_1 = { 676 10000, 0000, 0000, 0000, /* 1 - 4 */ 677 10000, 0000, 0000, 0000, /* 5 - 8 */ 678 10000, 0000, 0000, 0000, /* 9 - 12 */ 679 1000, 1000, 1000, 1000, /* 13 - 16 */ 680 1000, 1000, 1000, 1000, /* 17 - 20 */ 681 1000, 1000, 1000, 1000, /* 21 - 24 */ 682 10000, 0000, 0000, 0000 /* 25 - 28 */ 683 }; 684 const static soc_port_details_t sb2_port_details_56462_1[SB2_MAX_PHYSICAL_PORTS+1]={ 685 {1,4,4, XE_PORT,10000}, 686 {5,8,4, XE_PORT,10000}, 687 {9,12,4, XE_PORT,10000}, 688 {13,16,1, GE_PORT,1000}, 689 {17,20,1, GE_PORT,1000}, 690 {21,24,1, GE_PORT,1000}, 691 {25,26,4, XE_PORT,10000}, 692 {0,0,0,0}, 693 {0,0,0,0} /* End */ 694 }; 695 696 /* 56462_2: bcm5626x_config = 2 */ 697 /* F.XAUI F.XAUI - 4xGE 4xGE 4xGE N4s 2.5G B1A */ 698 static uint32 sb2_tdm_B1A_56462_2[SB2_TDM_B1A_SIZE]={0}; /* Filled up Runtime */ 699 const static sb2_speed_t sb2_speed_56462_2 = { 700 10000, 0000, 0000, 0000, /* 1 - 4 */ 701 10000, 0000, 0000, 0000, /* 5 - 8 */ 702 0000, 0000, 0000, 0000, /* 9 - 12 */ 703 1000, 1000, 1000, 1000, /* 13 - 16 */ 704 1000, 1000, 1000, 1000, /* 17 - 20 */ 705 1000, 1000, 1000, 1000, /* 21 - 24 */ 706 10000, 1000, 10000, 1000 /* 25 - 28 */ 707 }; 708 const static soc_port_details_t sb2_port_details_56462_2[SB2_MAX_PHYSICAL_PORTS+1]={ 709 {1,4,4, XE_PORT,10000}, 710 {5,8,4, XE_PORT,10000}, 711 {9,12,4, 0, 0}, 712 {13,16,1, GE_PORT,1000}, 713 {17,20,1, GE_PORT,1000}, 714 {20,24,1, GE_PORT,1000}, 715 {25,27,2,XE_PORT,10000}, 716 {26,28,2,GE_PORT,1000}, 717 {0,0,0,0} /* End */ 718 }; 719 720 /* 56463_1: bcm5626x_config = 1 */ 721 /* 4xGE 4xGE - - - 4xGE N4s 2.5G */ 722 static uint32 sb2_tdm_E_56463_1[SB2_TDM_E_SIZE]={0}; /* Filled up Runtime */ 723 const static sb2_speed_t sb2_speed_56463_1 = { 724 1000, 1000, 1000, 1000, /* 1 - 4 */ 725 1000, 1000, 1000, 1000, /* 5 - 8 */ 726 0000, 0000, 0000, 0000, /* 9 - 12 */ 727 0000, 0000, 0000, 0000, /* 13 - 16 */ 728 0000, 0000, 0000, 0000, /* 17 - 20 */ 729 1000, 1000, 1000, 1000, /* 21 - 24 */ 730 10000, 1000, 10000, 1000 /* 25 - 28 */ 731 }; 732 const static soc_port_details_t sb2_port_details_56463_1[SB2_MAX_PHYSICAL_PORTS+1]={ 733 {1,4,1, GE_PORT,1000}, 734 {5,8,1, GE_PORT,1000}, 735 {9,12,4, 0, 0}, 736 {13,16,4, 0, 0}, 737 {17,20,4, 0, 0}, 738 {21,24,1, GE_PORT,1000}, 739 {25,27,2,XE_PORT,10000}, 740 {26,28,2,GE_PORT,1000}, 741 {0,0,0,0} /* End */ 742 }; 743 744 745 /* 56463_2: bcm5626x_config = 2 */ 746 /* 4xGE 4xGE 4xGE 4xGE 4xGE 4xGE 4x2.5G 2.5G E1 */ 747 static uint32 sb2_tdm_E1_56463_2[SB2_TDM_E1_SIZE]={0}; /* Filled up Runtime */ 748 const static sb2_speed_t sb2_speed_56463_2 = { 749 1000, 1000, 1000, 1000, /* 1 - 4 */ 750 1000, 1000, 1000, 1000, /* 5 - 8 */ 751 1000, 1000, 1000, 1000, /* 9 - 12 */ 752 1000, 1000, 1000, 1000, /* 13 - 16 */ 753 1000, 1000, 1000, 1000, /* 17 - 20 */ 754 1000, 1000, 1000, 1000, /* 21 - 24 */ 755 2500, 2500, 2500, 2500 /* 25 - 28 */ 756 }; 757 const static soc_port_details_t sb2_port_details_56463_2[SB2_MAX_PHYSICAL_PORTS+1]={ 758 {1,4,1, GE_PORT,1000}, 759 {5,8,1, GE_PORT,1000}, 760 {9,12,1, GE_PORT,1000}, 761 {13,16,1, GE_PORT,1000}, 762 {17,20,1, GE_PORT,1000}, 763 {21,24,1, GE_PORT,1000}, 764 {25,28,1,GE_PORT,2500}, 765 {0,0,0,0}, 766 {0,0,0,0} /* End */ 767 }; 768 769 /* 56463_3: bcm5626x_config = 3 */ 770 /* 4xGE F.XAUI - - - F.XAUI F.XAUI 2.5G E3 */ 771 static uint32 sb2_tdm_E3_56463_3[SB2_TDM_E3_SIZE]={0}; /* Filled up Runtime */ 772 const static sb2_speed_t sb2_speed_56463_3 = { 773 1000, 1000, 1000, 1000, /* 1 - 4 */ 774 10000, 0000, 0000, 0000, /* 5 - 8 */ 775 0000, 0000, 0000, 0000, /* 9 - 12 */ 776 0000, 0000, 0000, 0000, /* 13 - 16 */ 777 0000, 0000, 0000, 0000, /* 17 - 20 */ 778 10000, 0000, 0000, 0000, /* 21 - 24 */ 779 10000, 0000, 0000, 0000 /* 25 - 28 */ 780 }; 781 const static soc_port_details_t sb2_port_details_56463_3[SB2_MAX_PHYSICAL_PORTS+1]={ 782 {1,4,1, GE_PORT,1000}, 783 {5,8,4,XE_PORT,10000}, 784 {9,12,4, 0, 0}, 785 {13,16,4, 0, 0}, 786 {17,20,4, 0, 0}, 787 {21,24,4, XE_PORT,10000}, 788 {25,25,1,XE_PORT,10000}, 789 {0,0,0,0}, 790 {0,0,0,0} /* End */ 791 }; 792 793 794 795 796 /* 56260_1: bcm5626x_config = 1 */ 797 /* 12x 2.5G + 2xXFI + 12.5G LPBK */ 798 static uint32 sb2_tdm_B_56260_1[SB2_TDM_B_SIZE]={0}; /* Filled up Runtime */ 799 const static sb2_speed_t sb2_speed_56260_1 = { 800 2500, 2500, 2500, 2500, /* 1 - 4 */ 801 2500, 2500, 2500, 2500, /* 5 - 8 */ 802 0, 0, 0, 0, /* 9 - 12 */ 803 0, 0, 0, 0, /* 13 - 16 */ 804 0, 0, 0, 0, /* 17 - 20 */ 805 2500, 2500, 2500, 2500, /* 21 - 24 */ 806 10000, 0, 10000, 0 /* 25 - 28 */ 807 }; 808 const static soc_port_details_t sb2_port_details_56260_1[SB2_MAX_PHYSICAL_PORTS+1]={ 809 {1, 4, 1,GE_PORT,2500}, 810 {5, 8, 1,GE_PORT,2500}, 811 {9,12,4, 0, 0}, 812 {13,16,4, 0, 0}, 813 {17,20,4, 0, 0}, 814 {21,24,1,GE_PORT,2500}, 815 {25,28,2,HG_PORT,10000}, 816 {0,0,0,0}, 817 {0,0,0,0} /* End */ 818 }; 819 820 /* 56260_2: bcm5626x_config = 2 */ 821 /* F.XAUI F.XAUI F.XAUI N4s 2.5G B1 */ 822 static uint32 sb2_tdm_B1_56260_2[SB2_TDM_B1_SIZE]={0}; /* Filled up Runtime */ 823 const static sb2_speed_t sb2_speed_56260_2 = { 824 10000, 0000, 0000, 0000, /* 1 - 4 */ 825 10000, 0000, 0000, 0000, /* 5 - 8 */ 826 0000, 0000, 0000, 0000, /* 9 - 12 */ 827 0000, 0000, 0000, 0000, /* 13 - 16 */ 828 0000, 0000, 0000, 0000, /* 17 - 20 */ 829 10000, 0000, 0000, 0000, /* 21 - 24 */ 830 10000, 1000, 10000, 1000 /* 25 - 28 */ 831 }; 832 const static soc_port_details_t sb2_port_details_56260_2[SB2_MAX_PHYSICAL_PORTS+1]={ 833 {1, 4, 4,XE_PORT,10000}, 834 {5, 8, 4,XE_PORT,10000}, 835 {9,12,4, 0, 0}, 836 {13,16,4, 0, 0}, 837 {17,20,4, 0, 0}, 838 {21,24,4,XE_PORT,10000}, 839 {25,27,2,XE_PORT,10000}, 840 {26,28,2,GE_PORT,1000}, 841 {0,0,0,0} /* End */ 842 }; 843 844 /* 56262_1: bcm5626x_config = 1 */ 845 /* 4x2.5G 4x2.5G - - - - - 2.5G EA 75 MHz */ 846 static uint32 sb2_tdm_EA_56262_1[SB2_TDM_EA_SIZE]={0}; /* Filled up Runtime */ 847 const static sb2_speed_t sb2_speed_56262_1 = { 848 2500, 2500, 2500, 2500, /* 1 - 4 */ 849 2500, 2500, 2500, 2500, /* 5 - 8 */ 850 0000, 0000, 0000, 0000, /* 9 - 12 */ 851 0000, 0000, 0000, 0000, /* 13 - 16 */ 852 0000, 0000, 0000, 0000, /* 17 - 20 */ 853 0000, 0000, 0000, 0000, /* 21 - 24 */ 854 0000, 0000, 0000, 0000 /* 25 - 28 */ 855 }; 856 const static soc_port_details_t sb2_port_details_56262_1[SB2_MAX_PHYSICAL_PORTS+1]={ 857 {1, 4, 1,GE_PORT,2500}, 858 {5, 8, 1,GE_PORT,2500}, 859 {9,12,4, 0, 0}, 860 {13,16,4, 0, 0}, 861 {17,20,4, 0, 0}, 862 {21,24,4, 0, 0}, 863 {25,28,4, 0, 0}, 864 {0,0,0,0}, 865 {0,0,0,0} /* End */ 866 }; 867 868 /* 56263_1: bcm5626x_config = 1 */ 869 /* 4xGE 4xGE - - - 4xGE 4xGE 2.5G A1A 37 MHz */ 870 static uint32 sb2_tdm_A1A_56263_1[SB2_TDM_A1A_SIZE]={0}; /* Filled up Runtime */ 871 const static sb2_speed_t sb2_speed_56263_1 = { 872 1000, 1000, 1000, 1000, /* 1 - 4 */ 873 1000, 1000, 1000, 1000, /* 5 - 8 */ 874 0000, 0000, 0000, 0000, /* 9 - 12 */ 875 0000, 0000, 0000, 0000, /* 13 - 16 */ 876 0000, 0000, 0000, 0000, /* 17 - 20 */ 877 1000, 1000, 1000, 1000, /* 21 - 24 */ 878 1000, 1000, 1000, 1000 /* 25 - 28 */ 879 }; 880 const static soc_port_details_t sb2_port_details_56263_1[SB2_MAX_PHYSICAL_PORTS+1]={ 881 {1, 4, 1,GE_PORT,1000}, 882 {5, 8, 1,GE_PORT,1000}, 883 {9,12,4, 0, 0}, 884 {13,16,4, 0, 0}, 885 {17,20,4, 0, 0}, 886 {21, 24, 1,GE_PORT,1000}, 887 {25, 28, 1,GE_PORT,1000}, 888 {0,0,0,0}, 889 {0,0,0,0} /* End */ 890 }; 891 892 /* 56263_2: bcm5626x_config = 2 */ 893 /* 3xGE 3xGE - - - - - 2.5G A1 24 MHz */ 894 static uint32 sb2_tdm_A1_56263_2[SB2_TDM_A1_SIZE]={0}; /* Filled up Runtime */ 895 const static sb2_speed_t sb2_speed_56263_2 = { 896 1000, 1000, 1000, 0000, /* 1 - 4 */ 897 1000, 1000, 1000, 0000, /* 5 - 8 */ 898 0000, 0000, 0000, 0000, /* 9 - 12 */ 899 0000, 0000, 0000, 0000, /* 13 - 16 */ 900 0000, 0000, 0000, 0000, /* 17 - 20 */ 901 0000, 0000, 0000, 0000, /* 21 - 24 */ 902 0000, 0000, 0000, 0000 /* 25 - 28 */ 903 }; 904 const static soc_port_details_t sb2_port_details_56263_2[SB2_MAX_PHYSICAL_PORTS+1]={ 905 {1, 3, 1,GE_PORT,1000}, 906 {5, 7, 1,GE_PORT,1000}, 907 {9,12,4, 0, 0}, 908 {13,16,4, 0, 0}, 909 {17,20,4, 0, 0}, 910 {21,24,4, 0, 0}, 911 {25,28,4, 0, 0}, 912 {0,0,0,0}, 913 {0,0,0,0} /* End */ 914 }; 915 916 /* 56233_1: bcm56233_config = 1 */ 917 /* 7xGE + 1x2.5GE - - - - - 2.5G F 75 MHz */ 918 static uint32 sb2_tdm_F_56233_1[SB2_TDM_F_SIZE]={0}; /* Filled up Runtime */ 919 const static sb2_speed_t sb2_speed_56233_1 = { 920 1000, 1000, 1000, 2500, /* 1 - 4 */ 921 2500, 0000, 0000, 0000, /* 5 - 8 */ 922 0000, 0000, 0000, 0000, /* 9 - 12 */ 923 0000, 0000, 0000, 0000, /* 13 - 16 */ 924 0000, 0000, 0000, 0000, /* 17 - 20 */ 925 1000, 1000, 1000, 1000, /* 21 - 24 */ 926 0000, 0000, 0000, 0000 /* 25 - 28 */ 927 }; 928 const static soc_port_details_t sb2_port_details_56233_1[SB2_MAX_PHYSICAL_PORTS+1]={ 929 {1, 3, 1,GE_PORT,1000}, 930 {4, 4, 1,GE_PORT,2500}, 931 {5, 8, 4, GE_PORT, 2500}, 932 {9,12,4, 0, 0}, 933 {13,16,4, 0, 0}, 934 {17,20,4, 0, 0}, 935 {21,24,1, GE_PORT,1000}, 936 {25,28,4, 0, 0}, 937 {0,0,0,0}, 938 {0,0,0,0} /* End */ 939 }; 940 941 942 sb2_tdm_pos_info_t sb2_tdm_pos_info[SB2_MAX_BLOCKS]={{0}}; 943 static uint8 old_tdm_no=0; 944 945 soc_field_t sb2_srcport_field_names[SB2_MAX_LOGICAL_PORTS]={ 946 SRCPORT_0f, 947 SRCPORT_1f, SRCPORT_2f, SRCPORT_3f, SRCPORT_4f, 948 SRCPORT_5f, SRCPORT_6f, SRCPORT_7f, SRCPORT_8f, 949 SRCPORT_9f, SRCPORT_10f, SRCPORT_11f, SRCPORT_12f, 950 SRCPORT_13f, SRCPORT_14f, SRCPORT_15f, SRCPORT_16f, 951 SRCPORT_17f, SRCPORT_18f, SRCPORT_19f, SRCPORT_20f, 952 SRCPORT_21f, SRCPORT_22f, SRCPORT_23f, SRCPORT_24f, 953 SRCPORT_25f, SRCPORT_26f, SRCPORT_27f, SRCPORT_28f, 954 SRCPORT_29f 955 }; 956 957 958 static sb2_port_to_block_t sb2_port_to_block_s={ 959 0,0,0,0, /* 1-4 mxq0 */ 960 1,1,1,1, /* 5-8 mxq1 */ 961 2,2,2,2, /* 9-12 mxq2 */ 962 3,3,3,3, /* 13-16 mxq3 */ 963 4,4,4,4, /* 17-20 mxq4 */ 964 5,5,5,5, /* 21-24 mxq5 */ 965 6,6,6,6 /* 25-28 xl */ 966 }; 967 static sb2_port_to_block_t *sb2_port_to_block[SOC_MAX_NUM_DEVICES]={NULL}; 968 969 sb2_port_to_block_subports_t sb2_port_to_block_subports_s={ 970 0,1,2,3, /* 1-4 mxq0*/ 971 0,1,2,3, /* 5-8 mxq1*/ 972 0,1,2,3, /* 9-12 mxq2*/ 973 0,1,2,3, /* 13-16 mxq3*/ 974 0,1,2,3, /* 17-20 mxq4*/ 975 0,1,2,3, /* 21-24 mxq5*/ 976 0,1,2,3 /* 25-28 xl */ 977 }; 978 sb2_port_to_block_subports_t 979 *sb2_port_to_block_subports[SOC_MAX_NUM_DEVICES]={NULL}; 980 981 sb2_block_ports_t sb2_block_ports_s={ 982 {1,2,3,4}, 983 {5,6,7,8}, 984 {9,10,11,12}, 985 {13,14,15,16}, 986 {17,18,19,20}, 987 {21,22,23,24}, 988 {25,26,27,28}, 989 }; 990 sb2_block_ports_t *sb2_block_ports[SOC_MAX_NUM_DEVICES]={NULL}; 991 992 typedef struct tdm_port_slots_info_s { 993 int32 position; 994 struct tdm_port_slots_info_s *prev; 995 struct tdm_port_slots_info_s *next; 996 }tdm_port_slots_info_t; 997 998 tdm_port_slots_info_t sb2_tdm_port_slots_info[SB2_MAX_LOGICAL_PORTS]; 999 1000 1001 static uint32 *bcm56260_tdm[]={ 1002 sb2_tdm_A_56260_0, /* Dummy to match cfg_num and index */ 1003 sb2_tdm_A_56460_1, /* 56460_1 Cfg=1:IntCfg=1 */ 1004 sb2_tdm_C2_56460_2, /* 56460 Cfg=2:IntCfg=2 */ 1005 sb2_tdm_C_56460_3, /* 56460 Cfg=3:IntCfg=3 */ 1006 sb2_tdm_C1_56460_4, /* 56460 Cfg=4:IntCfg=4 */ 1007 sb2_tdm_C1_56460_5, /* 56460 Cfg=5:IntCfg=5 */ 1008 sb2_tdm_D_56460_6, /* 56460 Cfg=6:IntCfg=6 */ 1009 sb2_tdm_B1A_56462_1, /* 56462 Cfg=1:IntCfg=7 */ 1010 sb2_tdm_B1A_56462_2, /* 56462 Cfg=2:IntCfg=8 */ 1011 sb2_tdm_E_56463_1, /* 56463 Cfg=1:IntCfg=9 */ 1012 sb2_tdm_E1_56463_2, /* 56463 Cfg=2:IntCfg=10 */ 1013 sb2_tdm_E3_56463_3, /* 56463 Cfg=3:IntCfg=11 */ 1014 sb2_tdm_B_56260_1, /* 56260 Cfg=1:IntCfg=12 */ 1015 sb2_tdm_B1_56260_2, /* 56260 Cfg=2:IntCfg=13 */ 1016 sb2_tdm_EA_56262_1, /* 56262 Cfg=1:IntCfg=14 */ 1017 sb2_tdm_A1A_56263_1, /* 56263 Cfg=1:IntCfg=15 */ 1018 sb2_tdm_A1_56263_2, /* 56263 Cfg=2:IntCfg=16 */ 1019 sb2_tdm_F_56233_1 /* 56233 Cfg=1:IntCfg=17 */ 1020 #ifdef BCM_WARM_BOOT_SUPPORT 1021 ,sb2_scache_tdm /*Dummy TDM reserved for WB */ 1022 #endif 1023 }; 1024 const static uint32 *bcm56260_speed_s[]={ 1025 sb2_speed_56260_0, /* Dummy */ 1026 sb2_speed_56460_1, /* 56460 Cfg=1:IntCfg=1 */ 1027 sb2_speed_56460_2, /* 56460 Cfg=2:IntCfg=2 */ 1028 sb2_speed_56460_3, /* 56460 Cfg=3:IntCfg=3 */ 1029 sb2_speed_56460_4, /* 56460 Cfg=4:IntCfg=4 */ 1030 sb2_speed_56460_5, /* 56460 Cfg=5:IntCfg=5 */ 1031 sb2_speed_56460_6, /* 56460 Cfg=6:IntCfg=6 */ 1032 sb2_speed_56462_1, /* 56462 Cfg=1:IntCfg=7 */ 1033 sb2_speed_56462_2, /* 56462 Cfg=2:IntCfg=8 */ 1034 sb2_speed_56463_1, /* 56463 Cfg=1:IntCfg=9 */ 1035 sb2_speed_56463_2, /* 56463 Cfg=2:IntCfg=10 */ 1036 sb2_speed_56463_3, /* 56463 Cfg=3:IntCfg=11 */ 1037 sb2_speed_56260_1, /* 56260 Cfg=1:IntCfg=12 */ 1038 sb2_speed_56260_2, /* 56260 Cfg=2:IntCfg=13 */ 1039 sb2_speed_56262_1, /* 56262 Cfg=1:IntCfg=14 */ 1040 sb2_speed_56263_1, /* 56263 Cfg=1:IntCfg=15 */ 1041 sb2_speed_56263_2, /* 56263 Cfg=2:IntCfg=16 */ 1042 sb2_speed_56233_1 /* 56233 Cfg=1:IntCfg=17 */ 1043 #ifdef BCM_WARM_BOOT_SUPPORT 1044 ,sb2_scache_speed /* Dummy speed reserved for WB*/ 1045 #endif 1046 }; 1047 sb2_speed_t *bcm56260_speed[SOC_MAX_NUM_DEVICES]={NULL}; 1048 1049 const static soc_port_details_t *sb2_port_details[]={ 1050 sb2_port_details_56260_0, /* Dummy */ 1051 sb2_port_details_56460_1, /* 56460 Cfg=1:IntCfg=1 */ 1052 sb2_port_details_56460_2, /* 56460 Cfg=2:IntCfg=2 */ 1053 sb2_port_details_56460_3, /* 56460 Cfg=3:IntCfg=3 */ 1054 sb2_port_details_56460_4, /* 56460 Cfg=4:IntCfg=4 */ 1055 sb2_port_details_56460_5, /* 56460 Cfg=5:IntCfg=5 */ 1056 sb2_port_details_56460_6, /* 56460 Cfg=6:IntCfg=6 */ 1057 sb2_port_details_56462_1, /* 56462 Cfg=1:IntCfg=7 */ 1058 sb2_port_details_56462_2, /* 56462 Cfg=2:IntCfg=8 */ 1059 sb2_port_details_56463_1, /* 56463 Cfg=1:IntCfg=9 */ 1060 sb2_port_details_56463_2, /* 56463 Cfg=2:IntCfg=10 */ 1061 sb2_port_details_56463_3, /* 56463 Cfg=3:IntCfg=11 */ 1062 sb2_port_details_56260_1, /* 56260 Cfg=1:IntCfg=12 */ 1063 sb2_port_details_56260_2, /* 56260 Cfg=2:IntCfg=13 */ 1064 sb2_port_details_56262_1, /* 56262 Cfg=1:IntCfg=14 */ 1065 sb2_port_details_56263_1, /* 56263 Cfg=1:IntCfg=15 */ 1066 sb2_port_details_56263_2, /* 56263 Cfg=2:IntCfg=16 */ 1067 sb2_port_details_56233_1 /* 56233 Cfg=1:IntCfg=17 */ 1068 #ifdef BCM_WARM_BOOT_SUPPORT 1069 ,sb2_scache_port_details /* Dummy port details 1070 reserved for WB*/ 1071 #endif 1072 }; 1073 1074 /* TDM related functions and structures */ 1075 static bcm56260_tdm_info_t bcm56260_tdm_info[]={ 1076 {0, 0, 0, 0}, /* Dummy */ 1077 /* 56460_1 Cfg=1:IntCfg=1 */ 1078 {SB2_TDM_AA_FREQ, SB2_TDM_AA_SIZE, SB2_TDM_AA_ROW, SB2_TDM_AA_COL}, 1079 1080 /* 56460_2 Cfg=2:IntCfg=2 */ 1081 {SB2_TDM_C2_FREQ, SB2_TDM_C2_SIZE, SB2_TDM_C2_ROW, SB2_TDM_C2_COL}, 1082 1083 /* 56460_3 Cfg=3:IntCfg=3 */ 1084 {SB2_TDM_C_FREQ, SB2_TDM_C_SIZE, SB2_TDM_C_ROW, SB2_TDM_C_COL}, 1085 1086 /* 56460_4 Cfg=4:IntCfg=4 */ 1087 {SB2_TDM_C1_FREQ, SB2_TDM_C1_SIZE, SB2_TDM_C1_ROW, SB2_TDM_C1_COL}, 1088 1089 /* 56460_5 Cfg=5:IntCfg=5 */ 1090 {SB2_TDM_C1_FREQ, SB2_TDM_C1_SIZE, SB2_TDM_C1_ROW, SB2_TDM_C1_COL}, 1091 1092 /* 56460_6 Cfg=6:IntCfg=6 */ 1093 {SB2_TDM_D_FREQ, SB2_TDM_D_SIZE, SB2_TDM_D_ROW, SB2_TDM_D_COL}, 1094 1095 /* 56462_1 Cfg=1:IntCfg=7 */ 1096 {SB2_TDM_B1A_FREQ, SB2_TDM_B1A_SIZE, SB2_TDM_B1A_ROW, SB2_TDM_B1A_COL}, 1097 /* 56462_2 Cfg=2:IntCfg=8 */ 1098 {SB2_TDM_B1A_FREQ, SB2_TDM_B1A_SIZE, SB2_TDM_B1A_ROW, SB2_TDM_B1A_COL}, 1099 1100 /* 56463_1 Cfg=1:IntCfg=9 */ 1101 {SB2_TDM_E_FREQ, SB2_TDM_E_SIZE, SB2_TDM_E_ROW, SB2_TDM_E_COL}, 1102 /* 56463_2 Cfg=2:IntCfg=10 */ 1103 {SB2_TDM_E1_FREQ, SB2_TDM_E1_SIZE, SB2_TDM_E1_ROW, SB2_TDM_E1_COL}, 1104 /* 56463_3 Cfg=3:IntCfg=11 */ 1105 {SB2_TDM_E3_FREQ, SB2_TDM_E3_SIZE, SB2_TDM_E3_ROW, SB2_TDM_E3_COL}, 1106 1107 /* 56260_1 Cfg=1:IntCfg=12 */ 1108 {SB2_TDM_B_FREQ, SB2_TDM_B_SIZE, SB2_TDM_B_ROW, SB2_TDM_B_COL}, 1109 1110 /* 56260_2 Cfg=2:IntCfg=13 */ 1111 {SB2_TDM_B1_FREQ, SB2_TDM_B1_SIZE, SB2_TDM_B1_ROW, SB2_TDM_B1_COL}, 1112 1113 /* 56262_1 Cfg=1:IntCfg=14 */ 1114 {SB2_TDM_EA_FREQ, SB2_TDM_EA_SIZE, SB2_TDM_EA_ROW, SB2_TDM_EA_COL}, 1115 1116 /* 56263_1 Cfg=1:IntCfg=15 */ 1117 {SB2_TDM_A1A_FREQ, SB2_TDM_A1A_SIZE, SB2_TDM_A1A_ROW, SB2_TDM_A1A_COL}, 1118 /* 56263_2 Cfg=1:IntCfg=16 */ 1119 {SB2_TDM_A1_FREQ, SB2_TDM_A1_SIZE, SB2_TDM_A1_ROW, SB2_TDM_A1_COL}, 1120 1121 /* 56233_1 Cfg=1:IntCfg=17 */ 1122 {SB2_TDM_F_FREQ, SB2_TDM_F_SIZE, SB2_TDM_F_ROW, SB2_TDM_F_COL} 1123 #ifdef BCM_WARM_BOOT_SUPPORT 1124 ,{0, 0, 0, 0}, 1125 #endif 1126 }; 1127 1128 typedef enum { 1129 _SOC_COUNTER_TYPE_DROP_ENQ, 1130 _SOC_COUNTER_TYPE_ACCEPT_ENQ, 1131 _SOC_COUNTER_TYPE_DROP_ENQ_GREEN, 1132 _SOC_COUNTER_TYPE_DROP_ENQ_YELLOW, 1133 _SOC_COUNTER_TYPE_DROP_ENQ_RED, 1134 _SOC_COUNTER_TYPE_ACCEPT_ENQ_GREEN, 1135 _SOC_COUNTER_TYPE_ACCEPT_ENQ_YELLOW, 1136 _SOC_COUNTER_TYPE_ACCEPT_ENQ_RED, 1137 _SOC_COUNTER_TYPE_ACCEPT_DEQ, 1138 _SOC_COUNTER_TYPE_MAX 1139 } _soc_saber2_counter_type_t; 1140 1141 typedef struct _soc_saber2_counter_info_s { 1142 _soc_saber2_counter_type_t type; 1143 int index; 1144 int segment; 1145 } _soc_saber2_counter_info_t; 1146 1147 /* Eagle port mode */ 1148 int eagle_n4s_mode = 0; 1149 int eagle_n2_mode = 0; 1150 int eagle_4ge_mode = 0; 1151 1152 STATIC int 1153 _soc_saber2_indacc_addr(uint32 phy_reg, int *target_select); 1154 STATIC int 1155 _soc_saber2_indacc_wait(int unit, soc_field_t fwait); 1156 1157 1158 STATIC _soc_saber2_counter_info_t _soc_saber2_counter_info[] = { 1159 { _SOC_COUNTER_TYPE_DROP_ENQ, 0x0, 0 }, 1160 { _SOC_COUNTER_TYPE_ACCEPT_ENQ, 0x0, 0 }, 1161 /* green pkt drops, index = ACCEPT=1'b0, COLOR=2'b00 */ 1162 { _SOC_COUNTER_TYPE_DROP_ENQ_GREEN, 0x0, 0 }, 1163 /* yellow pkt drops, index = ACCEPT=1'b0, COLOR=2'b11 */ 1164 { _SOC_COUNTER_TYPE_DROP_ENQ_YELLOW, 0x3, 0 }, 1165 /* red pkt drops, index = ACCEPT=1'b0, COLOR=2'b01 */ 1166 { _SOC_COUNTER_TYPE_DROP_ENQ_RED, 0x1, 0 }, 1167 /* green accepted pkts, index = ACCEPT=1'b1, COLOR=2'b00 */ 1168 { _SOC_COUNTER_TYPE_ACCEPT_ENQ_GREEN, 0x4, 0 }, 1169 /* yellow accepted pkts, index = ACCEPT=1'b1, COLOR=2'b11 */ 1170 { _SOC_COUNTER_TYPE_ACCEPT_ENQ_YELLOW, 0x7, 0 }, 1171 /* red accepted pkts, index = ACCEPT=1'b1, COLOR=2'b01 */ 1172 { _SOC_COUNTER_TYPE_ACCEPT_ENQ_RED, 0x5, 0 }, 1173 { _SOC_COUNTER_TYPE_ACCEPT_DEQ, 0, 0 } 1174 }; 1175 1176 int soc_saber2_hw_reset_control_init(int unit) { 1177 uint32 rval; 1178 soc_timeout_t to; 1179 int pipe_init_usec; 1180 1181 /* Reset IPITE and EPIPE block */ 1182 rval = 0; 1183 SOC_IF_ERROR_RETURN(WRITE_ING_HW_RESET_CONTROL_1r(unit, rval)); 1184 soc_reg_field_set(unit, ING_HW_RESET_CONTROL_2r, &rval, RESET_ALLf, 1); 1185 soc_reg_field_set(unit, ING_HW_RESET_CONTROL_2r, &rval, VALIDf, 1); 1186 soc_reg_field_set(unit, ING_HW_RESET_CONTROL_2r, &rval, COUNTf, 0x4000); 1187 SOC_IF_ERROR_RETURN(WRITE_ING_HW_RESET_CONTROL_2r(unit, rval)); 1188 1189 rval = 0; 1190 SOC_IF_ERROR_RETURN(WRITE_EGR_HW_RESET_CONTROL_0r(unit, rval)); 1191 1192 rval = 0; 1193 SOC_IF_ERROR_RETURN(READ_EGR_HW_RESET_CONTROL_1r (unit, &rval)); 1194 soc_reg_field_set(unit, EGR_HW_RESET_CONTROL_1r, &rval, RESET_ALLf, 1); 1195 soc_reg_field_set(unit, EGR_HW_RESET_CONTROL_1r, &rval, VALIDf, 1); 1196 /* 'EGR_VLAN_XLATE' initialization need to clear one more entry than 1197 * its max entry number(0x4000). 1198 */ 1199 soc_reg_field_set(unit, EGR_HW_RESET_CONTROL_1r, &rval, COUNTf, 0x4001); 1200 SOC_IF_ERROR_RETURN(WRITE_EGR_HW_RESET_CONTROL_1r(unit, rval)); 1201 1202 /* For simulation, set timeout to 10 sec. Otherwise, timeout = 50 ms */ 1203 if (SAL_BOOT_SIMULATION) { 1204 pipe_init_usec = 10000000; 1205 } else { 1206 pipe_init_usec = 50000; 1207 } 1208 soc_timeout_init(&to, pipe_init_usec, 0); 1209 1210 if((SAL_BOOT_BCMSIM || SAL_BOOT_PLISIM || SAL_BOOT_XGSSIM)) { 1211 SOC_IF_ERROR_RETURN(READ_ING_HW_RESET_CONTROL_2r(unit, &rval)); 1212 soc_reg_field_set(unit, ING_HW_RESET_CONTROL_2r, &rval, DONEf, 1); 1213 SOC_IF_ERROR_RETURN(WRITE_ING_HW_RESET_CONTROL_2r(unit, rval)); 1214 } 1215 1216 /* Wait for IPIPE memory initialization done. */ 1217 do { 1218 SOC_IF_ERROR_RETURN(READ_ING_HW_RESET_CONTROL_2r(unit, &rval)); 1219 if (soc_reg_field_get(unit, ING_HW_RESET_CONTROL_2r, rval, DONEf)) { 1220 break; 1221 } 1222 if (soc_timeout_check(&to)) { 1223 LOG_DEBUG(BSL_LS_SOC_COMMON, (BSL_META_U(unit, "ING_HW_RESET timeout\n"))); 1224 break; 1225 } 1226 } while (TRUE); 1227 1228 if((SAL_BOOT_BCMSIM || SAL_BOOT_PLISIM || SAL_BOOT_XGSSIM)) { 1229 SOC_IF_ERROR_RETURN(READ_EGR_HW_RESET_CONTROL_1r(unit, &rval)); 1230 soc_reg_field_set(unit, EGR_HW_RESET_CONTROL_1r, &rval, DONEf, 1); 1231 SOC_IF_ERROR_RETURN(WRITE_EGR_HW_RESET_CONTROL_1r(unit, rval)); 1232 } 1233 1234 /* Wait for EPIPE memory initialization done. */ 1235 do { 1236 SOC_IF_ERROR_RETURN(READ_EGR_HW_RESET_CONTROL_1r(unit, &rval)); 1237 if (soc_reg_field_get(unit, EGR_HW_RESET_CONTROL_1r, rval, DONEf)) { 1238 break; 1239 } 1240 if (soc_timeout_check(&to)) { 1241 LOG_WARN(BSL_LS_SOC_COMMON, (BSL_META_U(unit, "EGR_HW_RESET timeout\n"))); 1242 break; 1243 } 1244 } while (TRUE); 1245 1246 SOC_IF_ERROR_RETURN(READ_ING_HW_RESET_CONTROL_2r(unit, &rval)); 1247 soc_reg_field_set(unit, ING_HW_RESET_CONTROL_2r, &rval, RESET_ALLf, 0); 1248 soc_reg_field_set(unit, ING_HW_RESET_CONTROL_2r, &rval, 1249 CMIC_REQ_ENABLEf, 1); 1250 SOC_IF_ERROR_RETURN(WRITE_ING_HW_RESET_CONTROL_2r(unit, rval)); 1251 1252 SOC_IF_ERROR_RETURN(READ_EGR_HW_RESET_CONTROL_1r(unit, &rval)); 1253 soc_reg_field_set(unit, EGR_HW_RESET_CONTROL_1r, &rval, RESET_ALLf, 0); 1254 soc_reg_field_set(unit, EGR_HW_RESET_CONTROL_1r, &rval, DONEf, 0); 1255 SOC_IF_ERROR_RETURN(WRITE_EGR_HW_RESET_CONTROL_1r(unit, rval)); 1256 1257 return SOC_E_NONE; 1258 } 1259 1260 _soc_sb2_mmu_params_t _soc_sb2_mmu_params={0}; 1261 _soc_sb2_mmu_intermediate_results_t _soc_sb2_mmu_intermediate_results={{0}}; 1262 1263 extern int 1264 soc_tsc_xgxs_reset(int unit, soc_port_t port, int reg_idx); 1265 extern int 1266 bcm_kt2_modid_set_all(int unit, int *my_modid_list, int *my_modid_valid_list , 1267 int *base_port_ptr_list); 1268 1269 int _soc_saber2_get_cfg_num(int unit, int *new_cfg_num); 1270 int _sb2_config_id[SOC_MAX_NUM_DEVICES] = {-1}; 1271 soc_error_t 1272 soc_saber2_port_init_config(int unit, int cfg_num, soc_port_t port); 1273 1274 1275 STATIC int 1276 soc_sb2_update_ci_ddr3_phy_reg_data_ctrl(int unit, uint32 data, uint32 addr) { 1277 uint32 rval; 1278 int cnt; 1279 1280 rval = data; 1281 SOC_IF_ERROR_RETURN(WRITE_TOP_CI_DDR_PHY_REG_DATAr(unit, rval)); 1282 SOC_IF_ERROR_RETURN(READ_TOP_CI_DDR_PHY_REG_CTRLr(unit, &rval)); 1283 soc_reg_field_set(unit, TOP_CI_DDR_PHY_REG_CTRLr, &rval, PHY_REG_ACKf, 1); 1284 soc_reg_field_set(unit, TOP_CI_DDR_PHY_REG_CTRLr, &rval, 1285 PHY_REG_ADDRf, addr); 1286 soc_reg_field_set(unit, TOP_CI_DDR_PHY_REG_CTRLr, &rval, PHY_REG_REQf, 1); 1287 SOC_IF_ERROR_RETURN(WRITE_TOP_CI_DDR_PHY_REG_CTRLr(unit, rval)); 1288 1289 cnt = 3; 1290 while(cnt > 0) { 1291 SOC_IF_ERROR_RETURN(READ_TOP_CI_DDR_PHY_REG_CTRLr(unit, &rval)); 1292 1293 /* Check whether PHY_REG_ACKf or PHY_REG_ERR_ACKf is set */ 1294 if (soc_reg_field_get(unit, TOP_CI_DDR_PHY_REG_CTRLr, rval, 1295 PHY_REG_ACKf) || 1296 soc_reg_field_get(unit, TOP_CI_DDR_PHY_REG_CTRLr, rval, 1297 PHY_REG_ERR_ACKf)) { 1298 break; 1299 } 1300 LOG_ERROR(BSL_LS_SOC_COMMON, 1301 (BSL_META_U(unit, "Check count %d - 0x%x and Addr 0x%x\n"), cnt, data, addr)); 1302 cnt--; 1303 sal_usleep(1000); 1304 } 1305 1306 /* If PHY_REG_ERR_ACKf is set, then print the error */ 1307 if(soc_reg_field_get(unit, TOP_CI_DDR_PHY_REG_CTRLr, rval, 1308 PHY_REG_ERR_ACKf)) { 1309 LOG_ERROR(BSL_LS_SOC_COMMON, 1310 (BSL_META_U(unit, "Received PHY_REG_ERR_ACK for data \ 1311 0x%x and Addr 0x%x\n"), data, addr)); 1312 } 1313 1314 return SOC_E_NONE; 1315 } 1316 1317 int 1318 soc_sb2_update_ci_ddr3_phy_reg_ctrl(int unit, uint32 addr) { 1319 uint32 rval; 1320 1321 SOC_IF_ERROR_RETURN(READ_TOP_CI_DDR_PHY_REG_CTRLr(unit, &rval)); 1322 soc_reg_field_set(unit, TOP_CI_DDR_PHY_REG_CTRLr, &rval, PHY_REG_ACKf, 1); 1323 soc_reg_field_set(unit, TOP_CI_DDR_PHY_REG_CTRLr, &rval, 1324 PHY_REG_ADDRf, addr); 1325 soc_reg_field_set(unit, TOP_CI_DDR_PHY_REG_CTRLr, &rval, 1326 PHY_REG_ERR_ACKf, 1); 1327 soc_reg_field_set(unit, TOP_CI_DDR_PHY_REG_CTRLr, &rval, 1328 PHY_REG_RD_WR_Nf, 1); 1329 soc_reg_field_set(unit, TOP_CI_DDR_PHY_REG_CTRLr, &rval, PHY_REG_REQf, 1); 1330 SOC_IF_ERROR_RETURN(WRITE_TOP_CI_DDR_PHY_REG_CTRLr(unit, rval)); 1331 1332 return SOC_E_NONE; 1333 } 1334 1335 STATIC int 1336 soc_sb2_ddr3_phy_config(int unit) { 1337 uint32 rval; 1338 1339 SOC_IF_ERROR_RETURN(READ_TOP_MMU_DDR_PHY_CTRLr(unit, &rval)); 1340 soc_reg_field_set(unit, TOP_MMU_DDR_PHY_CTRLr, &rval, I_PWRONIN_PHYf, 1); 1341 SOC_IF_ERROR_RETURN(WRITE_TOP_MMU_DDR_PHY_CTRLr(unit, rval)); 1342 sal_usleep(1000); 1343 1344 SOC_IF_ERROR_RETURN(READ_TOP_MMU_DDR_PHY_CTRLr(unit, &rval)); 1345 soc_reg_field_set(unit, TOP_MMU_DDR_PHY_CTRLr, &rval, I_PWROKIN_PHYf, 1); 1346 SOC_IF_ERROR_RETURN(WRITE_TOP_MMU_DDR_PHY_CTRLr(unit, rval)); 1347 sal_usleep(1000); 1348 1349 SOC_IF_ERROR_RETURN(READ_TOP_MMU_DDR_PHY_CTRLr(unit, &rval)); 1350 soc_reg_field_set(unit, TOP_MMU_DDR_PHY_CTRLr, &rval, I_ISO_PHY_DFIf, 1); 1351 SOC_IF_ERROR_RETURN(WRITE_TOP_MMU_DDR_PHY_CTRLr(unit, rval)); 1352 sal_usleep(1000); 1353 1354 SOC_IF_ERROR_RETURN(soc_sb2_update_ci_ddr3_phy_reg_data_ctrl(unit, 0xC1, 0x1DC)); 1355 SOC_IF_ERROR_RETURN(soc_sb2_update_ci_ddr3_phy_reg_data_ctrl(unit, 0x4001530, 0x44)); 1356 SOC_IF_ERROR_RETURN(soc_sb2_update_ci_ddr3_phy_reg_ctrl(unit, 0)); 1357 1358 SOC_IF_ERROR_RETURN(soc_sb2_update_ci_ddr3_phy_reg_data_ctrl(unit, 0x1C030B0B, 0x48)); 1359 SOC_IF_ERROR_RETURN(soc_sb2_update_ci_ddr3_phy_reg_data_ctrl(unit, 0x60C080B, 0x4C)); 1360 SOC_IF_ERROR_RETURN(soc_sb2_update_ci_ddr3_phy_reg_data_ctrl(unit, 0x94C040, 0x50)); 1361 SOC_IF_ERROR_RETURN(soc_sb2_update_ci_ddr3_phy_reg_data_ctrl(unit, 0, 0x54)); 1362 1363 SOC_IF_ERROR_RETURN(soc_sb2_update_ci_ddr3_phy_reg_ctrl(unit, 0x8)); 1364 SOC_IF_ERROR_RETURN(soc_sb2_update_ci_ddr3_phy_reg_data_ctrl(unit, 0x810012, 0x8)); 1365 SOC_IF_ERROR_RETURN(soc_sb2_update_ci_ddr3_phy_reg_ctrl(unit, 0x8)); 1366 1367 SOC_IF_ERROR_RETURN(soc_sb2_update_ci_ddr3_phy_reg_ctrl(unit, 0x18)); 1368 SOC_IF_ERROR_RETURN(soc_sb2_update_ci_ddr3_phy_reg_data_ctrl(unit, 0x2030bF, 0x18)); 1369 SOC_IF_ERROR_RETURN(soc_sb2_update_ci_ddr3_phy_reg_ctrl(unit, 0x18)); 1370 1371 SOC_IF_ERROR_RETURN(soc_sb2_update_ci_ddr3_phy_reg_ctrl(unit, 0xC)); 1372 SOC_IF_ERROR_RETURN(soc_sb2_update_ci_ddr3_phy_reg_data_ctrl(unit, 0xD0, 0x0C)); 1373 1374 SOC_IF_ERROR_RETURN(soc_sb2_update_ci_ddr3_phy_reg_ctrl(unit, 0x10)); 1375 SOC_IF_ERROR_RETURN(soc_sb2_update_ci_ddr3_phy_reg_data_ctrl(unit, 0x9C000000, 0x10)); 1376 SOC_IF_ERROR_RETURN(soc_sb2_update_ci_ddr3_phy_reg_ctrl(unit, 0x10)); 1377 SOC_IF_ERROR_RETURN(soc_sb2_update_ci_ddr3_phy_reg_ctrl(unit, 0x8)); 1378 SOC_IF_ERROR_RETURN(soc_sb2_update_ci_ddr3_phy_reg_data_ctrl(unit, 0x810010, 0x8)); 1379 SOC_IF_ERROR_RETURN(soc_sb2_update_ci_ddr3_phy_reg_ctrl(unit, 0x8)); 1380 1381 SOC_IF_ERROR_RETURN(soc_sb2_update_ci_ddr3_phy_reg_ctrl(unit, 0x4)); 1382 1383 SOC_IF_ERROR_RETURN(soc_sb2_update_ci_ddr3_phy_reg_ctrl(unit, 0x8)); 1384 SOC_IF_ERROR_RETURN(soc_sb2_update_ci_ddr3_phy_reg_data_ctrl(unit, 0x810000, 0x8)); 1385 SOC_IF_ERROR_RETURN(soc_sb2_update_ci_ddr3_phy_reg_ctrl(unit, 0x8)); 1386 1387 return SOC_E_NONE; 1388 } 1389 1390 STATIC int 1391 _soc_saber2_tspll_bspll_config(int unit) 1392 { 1393 uint32 rval, to_usec; 1394 unsigned ts_ref_freq; 1395 unsigned ts_idx; 1396 /* values for 500MHz TSPLL output-f(vco)=3500, chan=0, f(out)=500*/ 1397 static const soc_pll_param_t ts_pll[] = { 1398 /* Fref, Ndiv_int, Ndiv_frac, Pdiv, Mdiv, Ka, Ki, Kp, VCO_div2 */ 1399 {12800000, 625, 0, 2, 8, 0, 2, 3, 1}, 1400 {20000000, 175, 0, 1, 7, 0, 2, 3, 1}, 1401 {25000000, 140, 0, 1, 7, 0, 2, 3, 1}, 1402 {32000000, 125, 0, 1, 8, 0, 2, 3, 1}, 1403 {50000000, 70, 0, 1, 7, 0, 2, 3, 1}, 1404 { 0, 70, 0, 1, 7, 0, 2, 3, 1} 1405 }; 1406 unsigned bs_ref_freq; 1407 unsigned bs_idx; 1408 uint32 bs_ndiv_high, bs_ndiv_low; 1409 /* values for 20MHz BS0PLL output-f(vco) = 3100,channel = 1,f(out) = 20*/ 1410 /* 25MHZ have frequency doubler on */ 1411 static const soc_pll_param_t bs_pll[] = { 1412 /* Fref, Ndiv_int, Ndiv_frac, Pdiv, Mdiv, Ka, Ki, Kp, VCO_div2 */ 1413 {12800000, 242, 3145728, 1, 155, 0, 0, 0, 0}, 1414 {20000000, 155, 0, 1, 155, 0, 0, 0, 0}, 1415 {25000000, 62, 0, 1, 155, 0, 0, 0, 0}, 1416 {32000000, 96, 14680064, 1, 155, 0, 0, 0, 0}, 1417 {50000000, 62, 0, 1, 155, 0, 0, 0, 0}, 1418 { 0, 62, 0, 1, 155, 0, 0, 0, 0} 1419 }; 1420 /* values for 20MHz BS1PLL output-f(vco) = 3000,channel = 1,f(out) = 20*/ 1421 /* BS1 PLL always driven internaly by from BS0 PLL */ 1422 static const soc_pll_param_t bs1_pll[] = { 1423 /* Fref, Ndiv_int, Ndiv_frac, Pdiv, Mdiv, Ka, Ki, Kp, VCO_div2 */ 1424 {12800000, 234, 6291456, 1, 150, 0, 0, 0, 0}, 1425 {20000000, 150, 0, 1, 150, 0, 0, 0, 0}, 1426 {25000000, 60, 0, 1, 150, 0, 0, 0, 0}, 1427 {32000000, 93, 12582912, 1, 150, 0, 0, 0, 0}, 1428 {50000000, 60, 0, 1, 150, 0, 0, 0, 0}, 1429 { 0, 60, 0, 1, 150, 0, 0, 0, 0} 1430 }; 1431 1432 #if defined(BCM_HITLESS_RESET_SUPPORT) 1433 int initialize_broadsync; 1434 #endif /* BCM_HITLESS_RESET_SUPPORT */ 1435 1436 /* TSPLL configuration: 500MHz TS_CLK from 20/25/32/50MHz refclk */ 1437 /* CMICd divides by 2 on input, so this is a 250MHz clock to TS logic */ 1438 1439 /* 50MHz is default ->internal reference */ 1440 ts_ref_freq = soc_property_get(unit, spn_PTP_TS_PLL_FREF, 0); 1441 1442 1443 /* Configure TS PLL */ 1444 for (ts_idx = 0; ts_idx < sizeof(ts_pll)/sizeof(ts_pll[0]); ++ts_idx) { 1445 if (ts_pll[ts_idx].ref_freq == ts_ref_freq) { 1446 break; 1447 } 1448 } 1449 if (ts_idx == sizeof(ts_pll)/sizeof(ts_pll[0])) { 1450 LOG_ERROR(BSL_LS_SOC_COMMON, 1451 (BSL_META_U(unit, 1452 "Invalid value for PTP_TS_PLL_REF (%u). No default PLL params. Using internal clock \n"), 1453 ts_ref_freq)); 1454 /* resetting back to internal clock */ 1455 ts_idx = ts_idx - 1; 1456 } 1457 1458 SOC_IF_ERROR_RETURN(READ_TOP_MISC_CONTROL_1r(unit,&rval)); 1459 soc_reg_field_set(unit, TOP_MISC_CONTROL_1r, &rval, TS_PLL_CLK_IN_SELf, 1460 (ts_ref_freq != 0)); 1461 WRITE_TOP_MISC_CONTROL_1r(unit, rval); 1462 1463 1464 if (SAL_BOOT_QUICKTURN) { 1465 LOG_VERBOSE(BSL_LS_SOC_COMMON, 1466 (BSL_META_U(unit, 1467 "%s:%d Skipping PLL Configuration \n"), __FUNCTION__,__LINE__)); 1468 } else { 1469 LOG_VERBOSE(BSL_LS_SOC_COMMON, 1470 (BSL_META_U(unit, 1471 "%s:%d Continuing PLL Configuration \n"), __FUNCTION__,__LINE__)); 1472 1473 if (SOC_REG_IS_VALID(unit, TOP_TIME_SYNC_PLL_CTRL_REGISTER_2r)) { 1474 SOC_IF_ERROR_RETURN(READ_TOP_TIME_SYNC_PLL_CTRL_REGISTER_2r(unit,&rval)); 1475 soc_reg_field_set(unit, TOP_TIME_SYNC_PLL_CTRL_REGISTER_2r, &rval, KAf, 1476 soc_property_get(unit, spn_PTP_TS_KA, ts_pll[ts_idx].ka)); 1477 soc_reg_field_set(unit, TOP_TIME_SYNC_PLL_CTRL_REGISTER_2r, &rval, KIf, 1478 soc_property_get(unit, spn_PTP_TS_KI, ts_pll[ts_idx].ki)); 1479 soc_reg_field_set(unit, TOP_TIME_SYNC_PLL_CTRL_REGISTER_2r, &rval, KPf, 1480 soc_property_get(unit, spn_PTP_TS_KP, ts_pll[ts_idx].kp)); 1481 soc_reg_field_set(unit, TOP_TIME_SYNC_PLL_CTRL_REGISTER_2r, &rval, 1482 NDIV_FRACf, ts_pll[ts_idx].ndiv_frac); 1483 WRITE_TOP_TIME_SYNC_PLL_CTRL_REGISTER_2r(unit, rval); 1484 } 1485 1486 if (SOC_REG_IS_VALID(unit, TOP_TIME_SYNC_PLL_CTRL_REGISTER_5r)) { 1487 SOC_IF_ERROR_RETURN(READ_TOP_TIME_SYNC_PLL_CTRL_REGISTER_5r(unit,&rval)); 1488 soc_reg_field_set(unit, TOP_TIME_SYNC_PLL_CTRL_REGISTER_5r, &rval, PDIVf, 1489 soc_property_get(unit, spn_PTP_TS_PLL_PDIV, ts_pll[ts_idx].pdiv)); 1490 WRITE_TOP_TIME_SYNC_PLL_CTRL_REGISTER_5r(unit, rval); 1491 } 1492 1493 if (SOC_REG_IS_VALID(unit, TOP_TIME_SYNC_PLL_CTRL_REGISTER_3r)) { 1494 SOC_IF_ERROR_RETURN(READ_TOP_TIME_SYNC_PLL_CTRL_REGISTER_3r(unit,&rval)); 1495 soc_reg_field_set(unit, TOP_TIME_SYNC_PLL_CTRL_REGISTER_3r, &rval, NDIV_INTf, 1496 soc_property_get(unit, spn_PTP_TS_PLL_N, 1497 ts_pll[ts_idx].ndiv_int)); 1498 WRITE_TOP_TIME_SYNC_PLL_CTRL_REGISTER_3r(unit, rval); 1499 } 1500 1501 if (SOC_REG_IS_VALID(unit, TOP_TIME_SYNC_PLL_CTRL_REGISTER_5r)) { 1502 SOC_IF_ERROR_RETURN(READ_TOP_TIME_SYNC_PLL_CTRL_REGISTER_5r(unit,&rval)); 1503 soc_reg_field_set(unit, TOP_TIME_SYNC_PLL_CTRL_REGISTER_5r, &rval, CH0_MDIVf, 1504 soc_property_get(unit, spn_PTP_TS_PLL_MNDIV, 1505 ts_pll[ts_idx].mdiv)); 1506 WRITE_TOP_TIME_SYNC_PLL_CTRL_REGISTER_5r(unit, rval); 1507 } 1508 1509 if (SOC_REG_IS_VALID(unit, TOP_TIME_SYNC_PLL_CTRL_REGISTER_5r)) { 1510 SOC_IF_ERROR_RETURN(READ_TOP_TIME_SYNC_PLL_CTRL_REGISTER_5r(unit,&rval)); 1511 soc_reg_field_set(unit, TOP_TIME_SYNC_PLL_CTRL_REGISTER_5r, &rval, CH1_MDIVf, 1512 soc_property_get(unit, spn_PTP_TS_PLL_MNDIV, 1513 ts_pll[ts_idx].mdiv)); 1514 WRITE_TOP_TIME_SYNC_PLL_CTRL_REGISTER_5r(unit, rval); 1515 } 1516 1517 } 1518 1519 /* 250Mhz TS PLL implies 4ns resolution */ 1520 SOC_TIMESYNC_PLL_CLOCK_NS(unit) = (1/250 * 1000); /* clock period in nanoseconds */ 1521 1522 #if defined(BCM_HITLESS_RESET_SUPPORT) 1523 1524 SOC_IF_ERROR_RETURN(READ_CMIC_BS0_CONFIGr(unit,&rval)); 1525 initialize_broadsync = !(soc_reg_field_get(unit, CMIC_BS0_CONFIGr, rval, 1526 BS_CLK_OUTPUT_ENABLEf)); 1527 1528 LOG_WARN(BSL_LS_SOC_COMMON, 1529 (BSL_META_U(unit, 1530 "BSPLL regs: %s\n"), initialize_broadsync ? "Default" : "Configured")); 1531 1532 if (!initialize_broadsync) { 1533 /* JIRA CMICD-110 1534 * On A0/B0, BroadSync Bitclock/Heartbeat divisors/enable registers get reset, 1535 * though the outputs themselves do not if the registers were written to an even 1536 * number of times. Workaround: when the registers are changed, the register 1537 * should be written twice, and the same value stored in SRAM. This code will 1538 * restore the register from SRAM. 1539 */ 1540 1541 /* BS0 */ 1542 uint32 reg_cache_base = soc_cmic_bs_reg_cache(unit, 0); 1543 1544 uint32 config = soc_uc_mem_read(unit, 1545 reg_cache_base + offsetof(mos_msg_bs_reg_cache_t, config)); 1546 uint32 clk_ctrl = soc_uc_mem_read(unit, 1547 reg_cache_base + offsetof(mos_msg_bs_reg_cache_t, clk_ctrl)); 1548 uint32 heartbeat_ctrl = soc_uc_mem_read(unit, 1549 reg_cache_base + offsetof(mos_msg_bs_reg_cache_t, heartbeat_ctrl)); 1550 uint32 heartbeat_down = soc_uc_mem_read(unit, 1551 reg_cache_base + offsetof(mos_msg_bs_reg_cache_t, heartbeat_down_duration)); 1552 uint32 heartbeat_up = soc_uc_mem_read(unit, 1553 reg_cache_base + offsetof(mos_msg_bs_reg_cache_t, heartbeat_up_duration)); 1554 1555 if (config == 0 && clk_ctrl == 0 && heartbeat_ctrl == 0 && heartbeat_down == 0 && heartbeat_up == 0) { 1556 /* PLL was initialized, but there is no saved state. Reset BroadSync. */ 1557 initialize_broadsync = 1; 1558 LOG_ERROR(BSL_LS_SOC_COMMON, 1559 (BSL_META_U(unit, 1560 "BSPLL Configured, but no BS state to restore\n"))); 1561 } else { 1562 /* Double-writes, per CMICD-110 WAR */ 1563 WRITE_CMIC_BS0_CONFIGr(unit, config); 1564 WRITE_CMIC_BS0_CONFIGr(unit, config); 1565 WRITE_CMIC_BS0_CLK_CTRLr(unit, clk_ctrl); 1566 WRITE_CMIC_BS0_CLK_CTRLr(unit, clk_ctrl); 1567 WRITE_CMIC_BS0_HEARTBEAT_CTRLr(unit, heartbeat_ctrl); 1568 WRITE_CMIC_BS0_HEARTBEAT_CTRLr(unit, heartbeat_ctrl); 1569 WRITE_CMIC_BS0_HEARTBEAT_DOWN_DURATIONr(unit, heartbeat_down); 1570 WRITE_CMIC_BS0_HEARTBEAT_DOWN_DURATIONr(unit, heartbeat_down); 1571 WRITE_CMIC_BS0_HEARTBEAT_UP_DURATIONr(unit, heartbeat_up); 1572 WRITE_CMIC_BS0_HEARTBEAT_UP_DURATIONr(unit, heartbeat_up); 1573 1574 LOG_WARN(BSL_LS_SOC_COMMON, 1575 (BSL_META_U(unit, 1576 "Restored BS0 regs:\n" 1577 " config: %08x clk_ctrl: %08x hb_ctrl: %08x\n" 1578 " hb_up: %08x hb_down: %08x\n"), 1579 config, clk_ctrl, heartbeat_ctrl, 1580 heartbeat_down, heartbeat_up)); 1581 1582 /* same, but for BS1 */ 1583 reg_cache_base = soc_cmic_bs_reg_cache(unit, 1); 1584 1585 config = soc_uc_mem_read(unit, 1586 reg_cache_base + offsetof(mos_msg_bs_reg_cache_t, config)); 1587 clk_ctrl = soc_uc_mem_read(unit, 1588 reg_cache_base + offsetof(mos_msg_bs_reg_cache_t, clk_ctrl)); 1589 heartbeat_ctrl = soc_uc_mem_read(unit, 1590 reg_cache_base + offsetof(mos_msg_bs_reg_cache_t, heartbeat_ctrl)); 1591 heartbeat_down = soc_uc_mem_read(unit, 1592 reg_cache_base + offsetof(mos_msg_bs_reg_cache_t, heartbeat_down_duration)); 1593 heartbeat_up = soc_uc_mem_read(unit, 1594 reg_cache_base + offsetof(mos_msg_bs_reg_cache_t, heartbeat_up_duration)); 1595 1596 WRITE_CMIC_BS1_CONFIGr(unit, config); 1597 WRITE_CMIC_BS1_CONFIGr(unit, config); 1598 WRITE_CMIC_BS1_CLK_CTRLr(unit, clk_ctrl); 1599 WRITE_CMIC_BS1_CLK_CTRLr(unit, clk_ctrl); 1600 WRITE_CMIC_BS1_HEARTBEAT_CTRLr(unit, heartbeat_ctrl); 1601 WRITE_CMIC_BS1_HEARTBEAT_CTRLr(unit, heartbeat_ctrl); 1602 WRITE_CMIC_BS1_HEARTBEAT_DOWN_DURATIONr(unit, heartbeat_down); 1603 WRITE_CMIC_BS1_HEARTBEAT_DOWN_DURATIONr(unit, heartbeat_down); 1604 WRITE_CMIC_BS1_HEARTBEAT_UP_DURATIONr(unit, heartbeat_up); 1605 WRITE_CMIC_BS1_HEARTBEAT_UP_DURATIONr(unit, heartbeat_up); 1606 1607 LOG_WARN(BSL_LS_SOC_COMMON, 1608 (BSL_META_U(unit, 1609 "Restored BS1 regs:\n" 1610 " config: %08x clk_ctrl: %08x hb_ctrl: %08x\n" 1611 " hb_up: %08x hb_down: %08x\n"), 1612 config, clk_ctrl, heartbeat_ctrl, 1613 heartbeat_down, heartbeat_up)); 1614 } 1615 } 1616 1617 if (initialize_broadsync) 1618 #endif /* BCM_HITLESS_RESET_SUPPORT */ 1619 { 1620 1621 /* Broadsync PLL initialization */ 1622 SOC_IF_ERROR_RETURN(READ_TOP_BROAD_SYNC0_PLL_CTRL_REGISTER_1r(unit,&rval)); 1623 1624 /* as a signal to upper-level code that the BroadSync is newly initialized 1625 * disable BroadSync0/1 bitclock output. Checked in time.c / 1588 firmware 1626 */ 1627 /* coverity[result_independent_of_operands] */ 1628 SOC_IF_ERROR_RETURN(READ_CMIC_BS0_CONFIGr(unit, &rval)); 1629 soc_reg_field_set(unit, CMIC_BS0_CONFIGr, &rval, BS_CLK_OUTPUT_ENABLEf, 0); 1630 WRITE_CMIC_BS0_CONFIGr(unit, rval); 1631 1632 /* coverity[result_independent_of_operands] */ 1633 SOC_IF_ERROR_RETURN(READ_CMIC_BS1_CONFIGr(unit, &rval)); 1634 soc_reg_field_set(unit, CMIC_BS1_CONFIGr, &rval, BS_CLK_OUTPUT_ENABLEf, 0); 1635 WRITE_CMIC_BS1_CONFIGr(unit, rval); 1636 1637 /* Both BSPLLs configured the same, for 20MHz output by default */ 1638 /* 50MHz is default. 0->internal reference */ 1639 bs_ref_freq = soc_property_get(unit, spn_PTP_BS_FREF, 0); 1640 /* Set BS_PLL_CLK_IN_SEL based on reference frequency. If it is 0, use the 1641 * internal reference 1642 */ 1643 for (bs_idx = 0; bs_idx < sizeof(bs_pll)/sizeof(bs_pll[0]); ++bs_idx) { 1644 if (bs_pll[bs_idx].ref_freq == bs_ref_freq) { 1645 break; 1646 } 1647 } 1648 1649 if (bs_idx == sizeof(bs_pll)/sizeof(bs_pll[0])) { 1650 LOG_ERROR(BSL_LS_SOC_COMMON, 1651 (BSL_META_U(unit, 1652 "Invalid value for PTP_BS_REF (%u). No default PLL params. Resetting to internal clock\n"), 1653 bs_ref_freq)); 1654 bs_idx = bs_idx - 1; 1655 } 1656 1657 /* bs pll - set reference clock */ 1658 1659 SOC_IF_ERROR_RETURN(READ_TOP_MISC_CONTROL_1r(unit,&rval)); 1660 soc_reg_field_set(unit, TOP_MISC_CONTROL_1r, &rval, BS0_PLL_CLK_IN_SELf, 1661 (bs_ref_freq != 0)); 1662 /* BS1 PLL to get ref clock internally routed from BS0 PLL */ 1663 soc_reg_field_set(unit, TOP_MISC_CONTROL_1r, &rval, BS1_PLL_CLK_IN_SELf,0); 1664 WRITE_TOP_MISC_CONTROL_1r(unit, rval); 1665 1666 /* bs pll - ndiv, mdiv, channel info */ 1667 bs_ndiv_high = ((soc_property_get(unit, spn_PTP_BS_NDIV_INT, bs_pll[bs_idx].ndiv_int) << 6) | 1668 ((soc_property_get(unit, spn_PTP_BS_NDIV_FRAC, bs_pll[bs_idx].ndiv_frac) >> 18) & 0x3f)); 1669 1670 bs_ndiv_low = (soc_property_get(unit, spn_PTP_BS_NDIV_FRAC, bs_pll[bs_idx].ndiv_frac) << 14); 1671 1672 /* bs pll - 0 configuration */ 1673 SOC_IF_ERROR_RETURN(READ_TOP_BROAD_SYNC0_LCPLL_FBDIV_CTRL_1r(unit,&rval)); 1674 soc_reg_field_set(unit, TOP_BROAD_SYNC0_LCPLL_FBDIV_CTRL_1r, &rval, 1675 BROAD_SYNC0_LCPLL_FBDIV_1f, bs_ndiv_high); 1676 WRITE_TOP_BROAD_SYNC0_LCPLL_FBDIV_CTRL_1r(unit, rval); 1677 1678 SOC_IF_ERROR_RETURN(READ_TOP_BROAD_SYNC0_LCPLL_FBDIV_CTRL_0r(unit,&rval)); 1679 soc_reg_field_set(unit, TOP_BROAD_SYNC0_LCPLL_FBDIV_CTRL_0r, &rval, 1680 BROAD_SYNC0_LCPLL_FBDIV_0f, bs_ndiv_low); 1681 WRITE_TOP_BROAD_SYNC0_LCPLL_FBDIV_CTRL_0r(unit, rval); 1682 1683 /* for BS , use channel 1 */ 1684 SOC_IF_ERROR_RETURN(READ_TOP_BROAD_SYNC0_PLL_CTRL_REGISTER_1r(unit,&rval)); 1685 soc_reg_field_set(unit, TOP_BROAD_SYNC0_PLL_CTRL_REGISTER_1r, &rval, 1686 CH1_MDIVf, soc_property_get(unit, spn_PTP_BS_MNDIV, 1687 bs_pll[bs_idx].mdiv)); 1688 WRITE_TOP_BROAD_SYNC0_PLL_CTRL_REGISTER_1r(unit, rval); 1689 1690 /* for 25MHz, set bit 13 to enable frequency doubler */ 1691 if (bs_ref_freq == 25000000) { 1692 SOC_IF_ERROR_RETURN(READ_TOP_BROAD_SYNC0_PLL_CTRL_REGISTER_3r(unit,&rval)); 1693 rval |= (1<<13); 1694 WRITE_TOP_BROAD_SYNC0_PLL_CTRL_REGISTER_3r(unit, rval); 1695 } 1696 1697 1698 1699 /* bs pll - 1 configuration */ 1700 SOC_IF_ERROR_RETURN(READ_TOP_BROAD_SYNC1_LCPLL_FBDIV_CTRL_1r(unit,&rval)); 1701 /*BS1 new config*/ 1702 bs_ndiv_high = ((soc_property_get(unit, spn_PTP_BS_NDIV_INT, bs1_pll[bs_idx].ndiv_int) << 6) | 1703 ((soc_property_get(unit, spn_PTP_BS_NDIV_FRAC, bs1_pll[bs_idx].ndiv_frac) >> 18) & 0x3f)); 1704 1705 bs_ndiv_low = (soc_property_get(unit, spn_PTP_BS_NDIV_FRAC, bs1_pll[bs_idx].ndiv_frac) << 14); 1706 1707 soc_reg_field_set(unit, TOP_BROAD_SYNC1_LCPLL_FBDIV_CTRL_1r, &rval, 1708 BROAD_SYNC1_LCPLL_FBDIV_1f, bs_ndiv_high); 1709 WRITE_TOP_BROAD_SYNC1_LCPLL_FBDIV_CTRL_1r(unit, rval); 1710 1711 SOC_IF_ERROR_RETURN(READ_TOP_BROAD_SYNC1_LCPLL_FBDIV_CTRL_0r(unit,&rval)); 1712 soc_reg_field_set(unit, TOP_BROAD_SYNC1_LCPLL_FBDIV_CTRL_0r, &rval, 1713 BROAD_SYNC1_LCPLL_FBDIV_0f, bs_ndiv_low); 1714 WRITE_TOP_BROAD_SYNC1_LCPLL_FBDIV_CTRL_0r(unit, rval); 1715 1716 SOC_IF_ERROR_RETURN(READ_TOP_BROAD_SYNC1_PLL_CTRL_REGISTER_1r(unit,&rval)); 1717 soc_reg_field_set(unit, TOP_BROAD_SYNC1_PLL_CTRL_REGISTER_1r, &rval, 1718 CH1_MDIVf, soc_property_get(unit, spn_PTP_BS_MNDIV, 1719 bs1_pll[bs_idx].mdiv)); 1720 WRITE_TOP_BROAD_SYNC1_PLL_CTRL_REGISTER_1r(unit, rval); 1721 1722 /* for 25MHz, set bit 13 to enable frequency doubler */ 1723 if (bs_ref_freq == 25000000) { 1724 SOC_IF_ERROR_RETURN(READ_TOP_BROAD_SYNC1_PLL_CTRL_REGISTER_3r(unit,&rval)); 1725 rval |= (1<<13); 1726 WRITE_TOP_BROAD_SYNC1_PLL_CTRL_REGISTER_3r(unit, rval); 1727 } 1728 1729 1730 /* JIRA CMICD-110: See above logic to restore BroadSync Bitclock/Heartbeat. */ 1731 /* Store default values in the SRAM, so they will be restored correctly */ 1732 /* even if SRAM is not used */ 1733 #if defined(BCM_HITLESS_RESET_SUPPORT) 1734 { 1735 /* store reset values in SRAM for BS0 */ 1736 uint32 reg_cache_base = soc_cmic_bs_reg_cache(unit, 0); 1737 READ_CMIC_BS0_CONFIGr(unit, &rval); 1738 soc_uc_mem_write(unit, reg_cache_base + 1739 offsetof(mos_msg_bs_reg_cache_t, config), rval); 1740 READ_CMIC_BS0_CLK_CTRLr(unit, &rval); 1741 soc_uc_mem_write(unit, reg_cache_base + 1742 offsetof(mos_msg_bs_reg_cache_t, clk_ctrl), rval); 1743 READ_CMIC_BS0_HEARTBEAT_CTRLr(unit, &rval); 1744 soc_uc_mem_write(unit, reg_cache_base + 1745 offsetof(mos_msg_bs_reg_cache_t, heartbeat_ctrl), rval); 1746 READ_CMIC_BS0_HEARTBEAT_DOWN_DURATIONr(unit, &rval); 1747 soc_uc_mem_write(unit, reg_cache_base + 1748 offsetof(mos_msg_bs_reg_cache_t, heartbeat_down_duration), rval); 1749 READ_CMIC_BS0_HEARTBEAT_UP_DURATIONr(unit, &rval); 1750 soc_uc_mem_write(unit, reg_cache_base + 1751 offsetof(mos_msg_bs_reg_cache_t, heartbeat_up_duration), rval); 1752 1753 /* store reset values in SRAM for BS1 */ 1754 reg_cache_base = soc_cmic_bs_reg_cache(unit, 1); 1755 READ_CMIC_BS1_CONFIGr(unit, &rval); 1756 soc_uc_mem_write(unit, reg_cache_base + 1757 offsetof(mos_msg_bs_reg_cache_t, config), rval); 1758 READ_CMIC_BS1_CLK_CTRLr(unit, &rval); 1759 soc_uc_mem_write(unit, reg_cache_base + 1760 offsetof(mos_msg_bs_reg_cache_t, clk_ctrl), rval); 1761 READ_CMIC_BS1_HEARTBEAT_CTRLr(unit, &rval); 1762 soc_uc_mem_write(unit, reg_cache_base + 1763 offsetof(mos_msg_bs_reg_cache_t, heartbeat_ctrl), rval); 1764 READ_CMIC_BS1_HEARTBEAT_DOWN_DURATIONr(unit, &rval); 1765 soc_uc_mem_write(unit, reg_cache_base + 1766 offsetof(mos_msg_bs_reg_cache_t, heartbeat_down_duration), rval); 1767 READ_CMIC_BS1_HEARTBEAT_UP_DURATIONr(unit, &rval); 1768 soc_uc_mem_write(unit, reg_cache_base + 1769 offsetof(mos_msg_bs_reg_cache_t, heartbeat_up_duration), rval); 1770 } 1771 } else { 1772 LOG_WARN(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 1773 "Leaving BroadSync in holdover\n"))); 1774 #endif /* BCM_HITLESS_RESET_SUPPORT */ 1775 } 1776 1777 /* Wait for pll lock */ 1778 to_usec = 10 * MILLISECOND_USEC; 1779 sal_usleep(to_usec); 1780 if (!SAL_BOOT_SIMULATION) { 1781 SOC_IF_ERROR_RETURN(READ_TOP_TIME_SYNC_PLL_STATUSr(unit, &rval)); 1782 if (!soc_reg_field_get(unit, TOP_TIME_SYNC_PLL_STATUSr, rval, 1783 TOP_TIME_SYNC_PLL_LOCKf)) { 1784 LOG_WARN(BSL_LS_SOC_COMMON, 1785 (BSL_META_U(unit, 1786 "TimeSync PLL not locked on unit %d " 1787 "status = 0x%08x\n"), unit, rval)); 1788 } 1789 1790 if (SOC_REG_IS_VALID(unit, TOP_BROAD_SYNC0_PLL_STATUSr)) { 1791 SOC_IF_ERROR_RETURN(READ_TOP_BROAD_SYNC0_PLL_STATUSr(unit, &rval)); 1792 if (!soc_reg_field_get(unit, TOP_BROAD_SYNC0_PLL_STATUSr, rval, 1793 TOP_BROAD_SYNC0_PLL_LOCKf)) { 1794 LOG_WARN(BSL_LS_SOC_COMMON, 1795 (BSL_META_U(unit, 1796 "BroadSync0 PLL not locked on unit %d " 1797 "status = 0x%08x\n"), unit, rval)); 1798 } 1799 } 1800 1801 if (SOC_REG_IS_VALID(unit, TOP_BROAD_SYNC1_PLL_STATUSr)) { 1802 SOC_IF_ERROR_RETURN(READ_TOP_BROAD_SYNC1_PLL_STATUSr(unit, &rval)); 1803 if (!soc_reg_field_get(unit, TOP_BROAD_SYNC1_PLL_STATUSr, rval, 1804 TOP_BROAD_SYNC1_PLL_LOCKf)) { 1805 LOG_WARN(BSL_LS_SOC_COMMON, 1806 (BSL_META_U(unit, 1807 "BroadSync1 PLL not locked on unit %d " 1808 "status = 0x%08x\n"), unit, rval)); 1809 } 1810 } 1811 } 1812 1813 return SOC_E_NONE; 1814 } 1815 1816 int _soc_saber2_hw_reset_control_init(int unit) 1817 { 1818 uint32 rval; 1819 int try_count = 0; 1820 int port = 1; 1821 int id; 1822 soc_mem_t mem[32] = { 1823 RXLP_INTERNAL_STREAM_MAP_PORT_0m, 1824 RXLP_INTERNAL_STREAM_MAP_PORT_1m, 1825 RXLP_INTERNAL_STREAM_MAP_PORT_2m, 1826 RXLP_INTERNAL_STREAM_MAP_PORT_3m, 1827 TXLP_PORT_STREAM_BITMAP_TABLEm, 1828 TXLP_INT2EXT_STREAM_MAP_TABLEm, 1829 DEVICE_STREAM_ID_TO_PP_PORT_MAPm, 1830 PP_PORT_TO_PHYSICAL_PORT_MAPm, 1831 TXLP_DEBUG_COUNTER0m, 1832 TXLP_DEBUG_COUNTER1m, 1833 TXLP_DEBUG_COUNTER2m, 1834 TXLP_DEBUG_COUNTER3m, 1835 TXLP_DEBUG_COUNTER4m, 1836 TXLP_DEBUG_COUNTER5m, 1837 TXLP_DEBUG_COUNTER6m, 1838 TXLP_DEBUG_COUNTER7m, 1839 TXLP_DEBUG_COUNTER8m, 1840 TXLP_DEBUG_COUNTER9m, 1841 TXLP_DEBUG_COUNTER10m, 1842 TXLP_DEBUG_COUNTER11m, 1843 RXLP_DEBUG_COUNTER0m, 1844 RXLP_DEBUG_COUNTER1m, 1845 RXLP_DEBUG_COUNTER2m, 1846 RXLP_DEBUG_COUNTER3m, 1847 RXLP_DEBUG_COUNTER4m, 1848 RXLP_DEBUG_COUNTER5m, 1849 RXLP_DEBUG_COUNTER6m, 1850 RXLP_DEBUG_COUNTER7m, 1851 RXLP_DEBUG_COUNTER8m, 1852 RXLP_DEBUG_COUNTER9m, 1853 RXLP_DEBUG_COUNTER10m, 1854 RXLP_DEBUG_COUNTER11m }; 1855 1856 SOC_IF_ERROR_RETURN(READ_RXLP_HW_RESET_CONTROLr(unit, port, &rval)); 1857 soc_reg_field_set(unit, RXLP_HW_RESET_CONTROLr, &rval, VALIDf, 1); 1858 soc_reg_field_set(unit, RXLP_HW_RESET_CONTROLr, &rval, START_ADDRESSf, 0); 1859 soc_reg_field_set(unit, RXLP_HW_RESET_CONTROLr, &rval, COUNTf, 0x7D0); 1860 SOC_IF_ERROR_RETURN(WRITE_RXLP_HW_RESET_CONTROLr(unit, port, rval)); 1861 1862 if((SAL_BOOT_BCMSIM || SAL_BOOT_PLISIM || SAL_BOOT_XGSSIM)) { 1863 SOC_IF_ERROR_RETURN(READ_RXLP_HW_RESET_CONTROLr(unit, port, &rval)); 1864 soc_reg_field_set(unit, RXLP_HW_RESET_CONTROLr, &rval, DONEf, 1); 1865 SOC_IF_ERROR_RETURN(WRITE_RXLP_HW_RESET_CONTROLr(unit, port, rval)); 1866 } 1867 1868 /* Now wait for HW to set DONEf */ 1869 do { 1870 SOC_IF_ERROR_RETURN(READ_RXLP_HW_RESET_CONTROLr(unit, port, &rval)); 1871 if (soc_reg_field_get(unit, RXLP_HW_RESET_CONTROLr, rval, DONEf) == 1) { 1872 break; 1873 } 1874 sal_usleep(1000); 1875 try_count++; 1876 } while(try_count < 3); 1877 1878 if (try_count == 3) { 1879 LOG_ERROR(BSL_LS_SOC_COMMON, (BSL_META_U(unit, "RXLP HW RESET Failed\n"))); 1880 return SOC_E_TIMEOUT; 1881 } 1882 1883 SOC_IF_ERROR_RETURN(READ_TXLP_HW_RESET_CONTROL_1r(unit, port, &rval)); 1884 soc_reg_field_set(unit, TXLP_HW_RESET_CONTROL_1r, &rval, VALIDf, 1); 1885 soc_reg_field_set(unit, TXLP_HW_RESET_CONTROL_1r, &rval, COUNTf, 0x84); 1886 soc_reg_field_set(unit, TXLP_HW_RESET_CONTROL_1r, &rval, RESET_ALLf, 0x1); 1887 SOC_IF_ERROR_RETURN(WRITE_TXLP_HW_RESET_CONTROL_1r(unit, port, rval)); 1888 1889 if((SAL_BOOT_BCMSIM || SAL_BOOT_PLISIM || SAL_BOOT_XGSSIM)) { 1890 SOC_IF_ERROR_RETURN(READ_TXLP_HW_RESET_CONTROL_1r(unit, port, &rval)); 1891 soc_reg_field_set(unit, TXLP_HW_RESET_CONTROL_1r, &rval, DONEf, 1); 1892 SOC_IF_ERROR_RETURN(WRITE_TXLP_HW_RESET_CONTROL_1r(unit, port, rval)); 1893 } 1894 1895 /* Now wait for HW to set DONEf */ 1896 try_count = 0; 1897 do { 1898 SOC_IF_ERROR_RETURN(READ_TXLP_HW_RESET_CONTROL_1r(unit, port, &rval)); 1899 if (soc_reg_field_get(unit, TXLP_HW_RESET_CONTROL_1r, rval, DONEf) == 1) { 1900 break; 1901 } 1902 sal_usleep(1000); 1903 try_count++; 1904 } while(try_count < 3); 1905 1906 if (try_count == 3) { 1907 LOG_ERROR(BSL_LS_SOC_COMMON, (BSL_META_U(unit, "TXLP HW RESET Failed\n"))); 1908 return SOC_E_TIMEOUT; 1909 } 1910 1911 /* Clear all the debug counters */ 1912 for (id = 0; id < 32; id++) { 1913 SOC_IF_ERROR_RETURN(soc_mem_clear(unit, mem[id], COPYNO_ALL, TRUE)); 1914 } 1915 1916 return SOC_E_NONE; 1917 } 1918 int 1919 _saber2_ledup_init(int unit, uint16 dev_id) 1920 { 1921 uint32 rval = 0; 1922 int ix; 1923 int pval1, pval2, pval3, pval4; 1924 int is_5626x = 0, ii = 0, pb = 7; 1925 int freq, cycles; 1926 int refresh_rate=30, refresh_period; 1927 struct led_remap { 1928 uint32 reg_addr; 1929 uint32 port0; 1930 uint32 port1; 1931 uint32 port2; 1932 uint32 port3; 1933 } led0_remap[] = { 1934 {CMIC_LEDUP0_PORT_ORDER_REMAP_0_3r, 1935 REMAP_PORT_0f,REMAP_PORT_1f,REMAP_PORT_2f,REMAP_PORT_3f}, 1936 {CMIC_LEDUP0_PORT_ORDER_REMAP_4_7r, 1937 REMAP_PORT_4f,REMAP_PORT_5f,REMAP_PORT_6f,REMAP_PORT_7f}, 1938 {CMIC_LEDUP0_PORT_ORDER_REMAP_8_11r, 1939 REMAP_PORT_8f,REMAP_PORT_9f,REMAP_PORT_10f,REMAP_PORT_11f}, 1940 {CMIC_LEDUP0_PORT_ORDER_REMAP_12_15r, 1941 REMAP_PORT_12f,REMAP_PORT_13f,REMAP_PORT_14f,REMAP_PORT_15f}, 1942 {CMIC_LEDUP0_PORT_ORDER_REMAP_16_19r, 1943 REMAP_PORT_16f,REMAP_PORT_17f,REMAP_PORT_18f,REMAP_PORT_19f}, 1944 {CMIC_LEDUP0_PORT_ORDER_REMAP_20_23r, 1945 REMAP_PORT_20f,REMAP_PORT_21f,REMAP_PORT_22f,REMAP_PORT_23f}, 1946 {CMIC_LEDUP0_PORT_ORDER_REMAP_24_27r, 1947 REMAP_PORT_24f,REMAP_PORT_25f,REMAP_PORT_26f,REMAP_PORT_27f} 1948 }; 1949 1950 switch(dev_id) { 1951 case BCM56260_DEVICE_ID: 1952 case BCM56261_DEVICE_ID: 1953 case BCM56262_DEVICE_ID: 1954 case BCM56263_DEVICE_ID: 1955 case BCM56265_DEVICE_ID: 1956 case BCM56266_DEVICE_ID: 1957 case BCM56267_DEVICE_ID: 1958 case BCM56268_DEVICE_ID: 1959 case BCM56233_DEVICE_ID: 1960 /* Metrolite */ 1961 case BCM56270_DEVICE_ID: 1962 case BCM56271_DEVICE_ID: 1963 case BCM56272_DEVICE_ID: 1964 is_5626x = 1; 1965 pb = 4; 1966 break; 1967 1968 default: 1969 is_5626x = 0; 1970 pb = 7; 1971 break; 1972 }; 1973 1974 1975 1976 /* initialize the led remap register settings. 1977 */ 1978 1979 for (ix = 0; ix < sizeof(led0_remap)/sizeof(led0_remap[0]); ix++) { 1980 1981 if (is_5626x == 1) 1982 { 1983 if ( ix >= 2 && ix <= 4) 1984 continue; 1985 } 1986 pval4 = ((pb-ii) * 4); 1987 pval3 = pval4 - 1; 1988 pval2 = pval4 - 2; 1989 pval1 = pval4 - 3; 1990 1991 rval = 0; 1992 soc_reg_field_set(unit, led0_remap[ix].reg_addr, &rval, 1993 led0_remap[ix].port0, pval1); 1994 soc_reg_field_set(unit, led0_remap[ix].reg_addr, &rval, 1995 led0_remap[ix].port1, pval2); 1996 soc_reg_field_set(unit, led0_remap[ix].reg_addr, &rval, 1997 led0_remap[ix].port2, pval3); 1998 soc_reg_field_set(unit, led0_remap[ix].reg_addr, &rval, 1999 led0_remap[ix].port3, pval4); 2000 /* coverity[result_independent_of_operands] */ 2001 SOC_IF_ERROR_RETURN 2002 (soc_pci_write(unit, 2003 soc_reg_addr(unit, led0_remap[ix].reg_addr, REG_PORT_ANY, 0), 2004 rval)); 2005 ii++; 2006 } 2007 2008 /* initialize the UP0 data ram */ 2009 rval = 0; 2010 for (ix = 0; ix < 256; ix++) { 2011 /* coverity[result_independent_of_operands] */ 2012 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP0_DATA_RAMr(unit,ix, rval)); 2013 } 2014 2015 /* From Top spec, Ring 0 LED chain is connected to 28 ports 2016 * Ring 1 LED chain is connected to iProc AMAC0/1 ports 2017 * Ring 2 is not connected. 2018 */ 2019 2020 /* Apply LEDUP delays. */ 2021 /* coverity[result_independent_of_operands] */ 2022 SOC_IF_ERROR_RETURN(READ_CMIC_LEDUP0_CTRLr(unit, &rval)); 2023 soc_reg_field_set(unit,CMIC_LEDUP0_CTRLr, 2024 &rval, LEDUP_SCAN_START_DELAYf, 0x6); 2025 soc_reg_field_set(unit,CMIC_LEDUP0_CTRLr, 2026 &rval, LEDUP_SCAN_INTRA_PORT_DELAYf, 0x5); 2027 /* coverity[result_independent_of_operands] */ 2028 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP0_CTRLr(unit, rval)); 2029 2030 /* Program the LED clock output frequency based on core clock */ 2031 freq = SOC_INFO(unit).frequency; 2032 2033 /* For LEDCLK_HALF_PERIOD */ 2034 /* Formula : cycles = (freq * 10^6) * (100 * 10^-9) = freq/10 */ 2035 /* Round up the value for non-integer clocks */ 2036 cycles = (freq + 9) / 10 - 1; 2037 if (cycles < 2) { 2038 cycles = 2; 2039 } 2040 2041 rval = 0; 2042 soc_reg_field_set(unit, CMIC_LEDUP0_CLK_DIVr, &rval, 2043 LEDCLK_HALF_PERIODf, cycles); 2044 /* coverity[result_independent_of_operands] */ 2045 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP0_CLK_DIVr(unit, rval)); 2046 /* coverity[result_independent_of_operands] */ 2047 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP1_CLK_DIVr(unit, rval)); 2048 2049 /* For REFRESH_CYCLE_PERIOD */ 2050 /* Formula : refresh_period = (freq * 10^6) / 30 */ 2051 refresh_period = freq * 1000000 / refresh_rate; 2052 2053 rval = 0; 2054 soc_reg_field_set(unit, CMIC_LEDUP0_CLK_PARAMSr, &rval, 2055 REFRESH_CYCLE_PERIODf, refresh_period); 2056 /* coverity[result_independent_of_operands] */ 2057 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP0_CLK_PARAMSr(unit, rval)); 2058 /* coverity[result_independent_of_operands] */ 2059 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP1_CLK_PARAMSr(unit, rval)); 2060 2061 return SOC_E_NONE; 2062 } 2063 2064 int _soc_saber2_misc_init(int unit) 2065 { 2066 soc_info_t *si; 2067 uint32 rval, rval1, rval2; 2068 uint32 entry[SOC_MAX_MEM_WORDS], ing_entry[SOC_MAX_MEM_WORDS]; 2069 soc_pbmp_t pbmp; 2070 int port; 2071 uint64 reg64; 2072 uint16 dev_id; 2073 uint8 rev_id; 2074 soc_field_t fields[3]; 2075 uint32 values[3]; 2076 int rv; 2077 int my_modid_list[4] = { 0, 0, 0, 0 }; 2078 int my_modid_valid[4] = { 1, 0, 0, 0 }; 2079 int my_modid_port_base_ptr[4] = { 0, 0, 0, 0 }; 2080 int parity_enable; 2081 int cfg_num; 2082 int start_pp_port, end_pp_port, pp_port; 2083 #ifdef BCM_WARM_BOOT_SUPPORT 2084 uint32 ddr3_clock_mhz = 0; 2085 uint32 num_rows = 32768; 2086 uint32 ddr3_mem_grade = 0; 2087 uint32 ext_pbmp_count=0; 2088 pbmp_t ext_pbmp; 2089 #endif 2090 soc_cm_get_id(unit, &dev_id, &rev_id); 2091 2092 si = &SOC_INFO(unit); 2093 2094 /* saber2 related hw reset control */ 2095 if(!SOC_WARM_BOOT(unit)) { 2096 SOC_IF_ERROR_RETURN(_soc_saber2_hw_reset_control_init(unit)); 2097 } 2098 2099 /* DDR Phy programming */ 2100 if (SAL_BOOT_QUICKTURN) { 2101 soc_sb2_ddr3_phy_config(unit); 2102 sal_usleep(1000); 2103 } 2104 /* core clock info in MHz updated from PRD 2105 * Do not modify these values until unless stated in PRD*/ 2106 switch(dev_id) { 2107 case BCM56460_DEVICE_ID: 2108 case BCM56461_DEVICE_ID: 2109 case BCM56465_DEVICE_ID: 2110 case BCM56466_DEVICE_ID: 2111 si->frequency = 130; 2112 break; 2113 case BCM56260_DEVICE_ID: 2114 case BCM56261_DEVICE_ID: 2115 case BCM56265_DEVICE_ID: 2116 case BCM56266_DEVICE_ID: 2117 case BCM56462_DEVICE_ID: 2118 case BCM56467_DEVICE_ID: 2119 si->frequency = 118; 2120 break; 2121 2122 case BCM56262_DEVICE_ID: 2123 case BCM56267_DEVICE_ID: 2124 case BCM56463_DEVICE_ID: 2125 case BCM56468_DEVICE_ID: 2126 case BCM56233_DEVICE_ID: 2127 si->frequency = 75; 2128 break; 2129 case BCM56263_DEVICE_ID: 2130 case BCM56268_DEVICE_ID: 2131 si->frequency = 37; 2132 break; 2133 } 2134 if(!(SAL_BOOT_BCMSIM || SAL_BOOT_PLISIM || SAL_BOOT_XGSSIM)) { 2135 if (soc_feature(unit, soc_feature_ddr3)) { 2136 #ifdef BCM_WARM_BOOT_SUPPORT 2137 if (SOC_WARM_BOOT(unit)) { 2138 ddr3_clock_mhz = 800; 2139 2140 SOC_DDR3_NUM_COLUMNS(unit) = soc_property_get(unit, spn_EXT_RAM_COLUMNS, 2141 1024); 2142 SOC_DDR3_NUM_BANKS(unit) = soc_property_get(unit,spn_EXT_RAM_BANKS, 8); 2143 SOC_DDR3_NUM_MEMORIES(unit) = soc_property_get(unit,spn_EXT_RAM_PRESENT, 2144 0); 2145 SOC_DDR3_NUM_ROWS(unit) = soc_property_get(unit,spn_EXT_RAM_ROWS, 2146 num_rows); 2147 SOC_DDR3_CLOCK_MHZ(unit) = soc_property_get(unit, spn_DDR3_CLOCK_MHZ, 2148 ddr3_clock_mhz); 2149 SOC_DDR3_MEM_GRADE(unit) = soc_property_get(unit, spn_DDR3_MEM_GRADE, 2150 ddr3_mem_grade); 2151 2152 ext_pbmp = soc_property_get_pbmp(unit, spn_PBMP_EXT_MEM, 0); 2153 SOC_PBMP_COUNT(ext_pbmp, ext_pbmp_count); 2154 } 2155 #endif 2156 if(!SOC_WARM_BOOT(unit) && SOC_DDR3_NUM_MEMORIES(unit)) { 2157 SOC_IF_ERROR_RETURN(soc_sb2_and28_dram_init_config(unit)); 2158 } 2159 } 2160 2161 parity_enable = soc_property_get(unit, spn_PARITY_ENABLE, TRUE); 2162 soc_saber2_ser_init(unit, parity_enable ? TRUE : FALSE); 2163 /* initialize LED UP0 */ 2164 SOC_IF_ERROR_RETURN(_saber2_ledup_init(unit, dev_id)); 2165 } 2166 2167 /* Some registers are implemented in memory, need to clear them in order 2168 * to have correct parity value */ 2169 PBMP_PP_ALL_ITER(unit, port) { 2170 SOC_IF_ERROR_RETURN(WRITE_EGR_VLAN_CONTROL_1r(unit, port, 0)); 2171 SOC_IF_ERROR_RETURN(WRITE_EGR_IPMC_CFG2r(unit, port, 0)); 2172 } 2173 if ((soc_feature(unit, soc_feature_linkphy_coe) && 2174 SOC_INFO(unit).linkphy_enabled) || 2175 (soc_feature(unit, soc_feature_subtag_coe) && 2176 SOC_INFO(unit).subtag_enabled)) { 2177 2178 my_modid_list[0] = 0; 2179 my_modid_valid[0] = 1; 2180 my_modid_port_base_ptr[0] = 0; 2181 2182 /* If not running in the stacking mode, setup the second module 2183 as the default one to host all pp_ports, else, the user will 2184 create the necessary modules with separate APIs */ 2185 if(!SOC_INFO(unit).coe_stacking_mode) { 2186 my_modid_list[1] = 1; 2187 my_modid_valid[1] = 1; 2188 my_modid_port_base_ptr[1] = SOC_SB2_MIN_SUBPORT_INDEX; 2189 } 2190 } 2191 2192 SOC_IF_ERROR_RETURN( 2193 bcm_kt2_modid_set_all(unit, my_modid_list, my_modid_valid, 2194 my_modid_port_base_ptr)); 2195 2196 SOC_IF_ERROR_RETURN(READ_TOP_MISC_CONTROL_1r( unit,&rval)); 2197 soc_reg_field_set(unit, TOP_MISC_CONTROL_1r, &rval, DDR3_PHY0_IDDQ_ENf, 0); 2198 SOC_IF_ERROR_RETURN(WRITE_TOP_MISC_CONTROL_1r(unit, rval)); 2199 2200 sal_memset(entry, 0, sizeof(cpu_pbm_entry_t)); 2201 soc_mem_pbmp_field_set(unit, CPU_PBMm, entry, BITMAPf, &PBMP_CMIC(unit)); 2202 SOC_IF_ERROR_RETURN 2203 (soc_mem_write(unit, CPU_PBMm, MEM_BLOCK_ALL, 0, entry)); 2204 2205 sal_memset(entry, 0, sizeof(cpu_pbm_2_entry_t)); 2206 soc_mem_pbmp_field_set(unit, CPU_PBM_2m, entry, BITMAPf, &PBMP_CMIC(unit)); 2207 SOC_IF_ERROR_RETURN 2208 (soc_mem_write(unit, CPU_PBM_2m, MEM_BLOCK_ALL, 0, entry)); 2209 2210 sal_memset(entry, 0, sizeof(multipass_loopback_bitmap_entry_t)); 2211 soc_mem_pbmp_field_set(unit, MULTIPASS_LOOPBACK_BITMAPm, entry, BITMAPf, 2212 &PBMP_LB(unit)); 2213 SOC_IF_ERROR_RETURN 2214 (soc_mem_write(unit, MULTIPASS_LOOPBACK_BITMAPm, MEM_BLOCK_ALL, 0, 2215 entry)); 2216 2217 SOC_PBMP_CLEAR(pbmp); 2218 for (port = 0; port < 30; port++) { 2219 if (IS_LB_PORT(unit, port) || 2220 (si->port_group[port] >= 2 && si->port_group[port] <= 3)) { 2221 SOC_PBMP_PORT_ADD(pbmp, port); 2222 } 2223 } 2224 sal_memset(entry, 0, sizeof(egr_physical_port_entry_t)); 2225 sal_memset(ing_entry, 0, sizeof(ing_physical_port_table_entry_t)); 2226 2227 soc_mem_field32_set(unit, EGR_PHYSICAL_PORTm, entry, PORT_TYPEf, 1); 2228 soc_mem_field32_set(unit, ING_PHYSICAL_PORT_TABLEm, 2229 ing_entry, PORT_TYPEf, 1); 2230 2231 /* Higig ports */ 2232 PBMP_ST_ITER(unit, port) { 2233 SOC_IF_ERROR_RETURN(soc_reg_field32_modify( 2234 unit, IECELL_CONFIGr, port, HIGIG_MODEf, 1)); 2235 SOC_IF_ERROR_RETURN(soc_reg_field32_modify( 2236 unit, XLPORT_CONFIGr, port, HIGIG_MODEf, 1)); 2237 if (IS_HL_PORT(unit,port) || 2238 soc_property_port_get(unit, port, spn_HIGIG2_HDR_MODE, 0)) { 2239 SOC_IF_ERROR_RETURN(soc_reg_field32_modify( 2240 unit,IECELL_CONFIGr, port, HIGIG2_MODEf, 1)); 2241 SOC_IF_ERROR_RETURN(soc_reg_field32_modify( 2242 unit, XLPORT_CONFIGr, port, HIGIG2_MODEf, 1)); 2243 soc_mem_field32_set(unit, ING_PHYSICAL_PORT_TABLEm,ing_entry, 2244 HIGIG2f,1); 2245 soc_mem_field32_set(unit, EGR_PHYSICAL_PORTm,entry, 2246 HIGIG2f,1); 2247 } else { 2248 SOC_IF_ERROR_RETURN(soc_reg_field32_modify( 2249 unit, IECELL_CONFIGr, port, HIGIG2_MODEf, 0)); 2250 SOC_IF_ERROR_RETURN(soc_reg_field32_modify( 2251 unit, XLPORT_CONFIGr, port, HIGIG2_MODEf, 0)); 2252 soc_mem_field32_set(unit, ING_PHYSICAL_PORT_TABLEm,ing_entry, 2253 HIGIG2f,0); 2254 soc_mem_field32_set(unit, EGR_PHYSICAL_PORTm,entry, 2255 HIGIG2f,0); 2256 } 2257 SOC_IF_ERROR_RETURN(soc_mem_write(unit, EGR_PHYSICAL_PORTm, 2258 MEM_BLOCK_ALL, port, entry)); 2259 SOC_IF_ERROR_RETURN(soc_mem_write(unit, ING_PHYSICAL_PORT_TABLEm, 2260 MEM_BLOCK_ALL, port, ing_entry)); 2261 } 2262 2263 /* CMIC higig index */ 2264 /* Setup the cpu_hg_port specifically in HG2 mode */ 2265 soc_mem_field32_set(unit, ING_PHYSICAL_PORT_TABLEm, ing_entry, 2266 HIGIG2f, 1); 2267 soc_mem_field32_set(unit, EGR_PHYSICAL_PORTm,entry, 2268 HIGIG2f, 1); 2269 SOC_IF_ERROR_RETURN(soc_mem_write( 2270 unit, EGR_PHYSICAL_PORTm, MEM_BLOCK_ALL, si->cpu_hg_index, entry)); 2271 SOC_IF_ERROR_RETURN(soc_mem_write( 2272 unit, ING_PHYSICAL_PORT_TABLEm, MEM_BLOCK_ALL, 2273 si->cpu_hg_index, ing_entry)); 2274 2275 /* Loopback port */ 2276 soc_mem_field32_set(unit, EGR_PHYSICAL_PORTm, entry, PORT_TYPEf, 2); 2277 soc_mem_field32_set(unit, ING_PHYSICAL_PORT_TABLEm, ing_entry, 2278 PORT_TYPEf, 2); 2279 SOC_IF_ERROR_RETURN(soc_mem_write( 2280 unit, EGR_PHYSICAL_PORTm, MEM_BLOCK_ALL, si->lb_port, entry)); 2281 SOC_IF_ERROR_RETURN(soc_mem_write( 2282 unit, ING_PHYSICAL_PORT_TABLEm, 2283 MEM_BLOCK_ALL, si->lb_port, ing_entry)); 2284 /* ingress physical port to pp_port mapping */ 2285 SOC_IF_ERROR_RETURN(soc_mem_field32_modify( 2286 unit, ING_PHYSICAL_PORT_TABLEm, 2287 si->lb_port, PP_PORTf, si->lb_port)); 2288 2289 /* pp_port to egress physical port mapping */ 2290 SOC_IF_ERROR_RETURN(soc_mem_field32_modify( 2291 unit, PP_PORT_TO_PHYSICAL_PORT_MAPm, 2292 si->lb_port, DESTINATIONf,si->lb_port)); 2293 2294 2295 2296 SOC_IF_ERROR_RETURN(READ_MISCCONFIGr(unit, &rval)); 2297 soc_reg_field_set(unit, MISCCONFIGr, &rval, METERING_CLK_ENf, 1); 2298 SOC_IF_ERROR_RETURN(WRITE_MISCCONFIGr(unit, rval)); 2299 2300 /* Enable dual hash on L2, L3 and MPLS_ENTRY tables */ 2301 fields[0] = ENABLEf; 2302 values[0] = 1; 2303 fields[1] = HASH_SELECTf; 2304 values[1] = FB_HASH_CRC32_LOWER; 2305 fields[2] = INSERT_LEAST_FULL_HALFf; 2306 values[2] = 1; 2307 SOC_IF_ERROR_RETURN 2308 (soc_reg_fields32_modify(unit, L2_AUX_HASH_CONTROLr, REG_PORT_ANY, 3, 2309 fields, values)); 2310 SOC_IF_ERROR_RETURN 2311 (soc_reg_fields32_modify(unit, L3_AUX_HASH_CONTROLr, REG_PORT_ANY, 3, 2312 fields, values)); 2313 SOC_IF_ERROR_RETURN 2314 (soc_reg_field32_modify(unit, MPLS_ENTRY_HASH_CONTROLr, REG_PORT_ANY, 2315 INSERT_LEAST_FULL_HALFf, 1)); 2316 /* 2317 * IPMC init 2318 */ 2319 SOC_IF_ERROR_RETURN(READ_RQE_GLOBAL_CONFIGr(unit, &rval)); 2320 soc_reg_field_set(unit,RQE_GLOBAL_CONFIGr, &rval, PARITY_GEN_ENf, 2321 1); 2322 soc_reg_field_set(unit,RQE_GLOBAL_CONFIGr, &rval, PARITY_CHK_ENf, 2323 1); 2324 SOC_IF_ERROR_RETURN(WRITE_RQE_GLOBAL_CONFIGr(unit, rval)); 2325 2326 /* Egress Disable */ 2327 sal_memset(entry, 0, sizeof(egr_enable_entry_t)); 2328 soc_mem_field32_set(unit, EGR_ENABLEm, entry, PRT_ENABLEf, 0); 2329 for (port = 0; port <= si->lb_port; port++) { 2330 rv = WRITE_EGR_ENABLEm(unit, MEM_BLOCK_ALL, port, entry); 2331 /* ****************************************************************** */ 2332 2333 /* ****************************************************************** */ 2334 if (SOC_FAILURE(rv)) { 2335 if (rv == _SHR_E_PARAM) { 2336 continue; 2337 } 2338 return rv; 2339 } 2340 } 2341 2342 SOC_IF_ERROR_RETURN(READ_DEQ_EFIFO_CFG_COMPLETEr(unit, &rval)); 2343 soc_reg_field_set(unit, DEQ_EFIFO_CFG_COMPLETEr, &rval, \ 2344 EGRESS_FIFO_CONFIGURATION_COMPLETEf, 0); 2345 SOC_IF_ERROR_RETURN(WRITE_DEQ_EFIFO_CFG_COMPLETEr(unit, rval)); 2346 2347 /* Configure MMU for the ports configured for ext mem */ 2348 for (port = 0; port < si->lb_port; port++) { 2349 if (IS_EXT_MEM_PORT(unit, port)) { 2350 2351 SOC_IF_ERROR_RETURN(READ_DEST_PORT_CFG_0r(unit, &rval)); 2352 rval |= (1 << port); 2353 SOC_IF_ERROR_RETURN(WRITE_DEST_PORT_CFG_0r(unit, rval)); 2354 2355 SOC_IF_ERROR_RETURN(READ_MMU_ENQ_DEST_PPP_CFG_0r(unit, &rval)); 2356 rval |= (1 << port); 2357 SOC_IF_ERROR_RETURN(WRITE_MMU_ENQ_DEST_PPP_CFG_0r(unit, rval)); 2358 2359 if (si->port_num_subport[port] > 0) { 2360 start_pp_port = si->port_subport_base[port]; 2361 end_pp_port = si->port_subport_base[port] + 2362 si->port_num_subport[port]; 2363 SOC_IF_ERROR_RETURN(READ_MMU_ENQ_DEST_PPP_CFG_0r(unit, &rval)); 2364 SOC_IF_ERROR_RETURN(READ_MMU_ENQ_DEST_PPP_CFG_1r(unit, &rval1)); 2365 SOC_IF_ERROR_RETURN(READ_MMU_ENQ_DEST_PPP_CFG_2r(unit, &rval2)); 2366 for (pp_port = start_pp_port; pp_port < end_pp_port; pp_port++) { 2367 if (( pp_port <= 31 )){ 2368 rval |= (1 << pp_port); 2369 } else if (( pp_port > 31 ) && (pp_port <= 63) ){ 2370 rval1 |= (1 << (pp_port - 32)); 2371 } else if (( pp_port > 63 ) && (pp_port <= 95) ){ 2372 rval2 |= (1 << (pp_port - 64)); 2373 } 2374 } 2375 2376 SOC_IF_ERROR_RETURN(WRITE_MMU_ENQ_DEST_PPP_CFG_0r(unit, rval)); 2377 SOC_IF_ERROR_RETURN(WRITE_MMU_ENQ_DEST_PPP_CFG_1r(unit, rval1)); 2378 SOC_IF_ERROR_RETURN(WRITE_MMU_ENQ_DEST_PPP_CFG_2r(unit, rval2)); 2379 } 2380 } 2381 } 2382 2383 sal_memset(entry, 0, sizeof(epc_link_bmap_entry_t)); 2384 SOC_IF_ERROR_RETURN(READ_EPC_LINK_BMAPm(unit, MEM_BLOCK_ALL, 0, 2385 &entry)); 2386 soc_mem_pbmp_field_set(unit, EPC_LINK_BMAPm, entry, PORT_BITMAPf, 2387 &PBMP_CMIC(unit)); 2388 SOC_IF_ERROR_RETURN(WRITE_EPC_LINK_BMAPm(unit, MEM_BLOCK_ALL, 0, entry)); 2389 2390 SOC_IF_ERROR_RETURN(READ_ING_CONFIG_64r(unit, ®64)); 2391 soc_reg64_field32_set(unit, ING_CONFIG_64r, ®64, 2392 L3SRC_HIT_ENABLEf, 1); 2393 soc_reg64_field32_set(unit, ING_CONFIG_64r, ®64, 2394 L2DST_HIT_ENABLEf, 1); 2395 soc_reg64_field32_set(unit, ING_CONFIG_64r, ®64, 2396 APPLY_EGR_MASK_ON_L2f, 1); 2397 soc_reg64_field32_set(unit, ING_CONFIG_64r, ®64, 2398 APPLY_EGR_MASK_ON_L3f, 1); 2399 soc_reg64_field32_set(unit, ING_CONFIG_64r, ®64, 2400 ARP_RARP_TO_FPf, 0x3); /* enable both ARP & RARP */ 2401 soc_reg64_field32_set(unit, ING_CONFIG_64r, ®64, 2402 ARP_VALIDATION_ENf, 1); 2403 soc_reg64_field32_set(unit, ING_CONFIG_64r, ®64, 2404 IGNORE_HG_HDR_LAG_FAILOVERf, 1); 2405 SOC_IF_ERROR_RETURN(WRITE_ING_CONFIG_64r(unit, reg64)); 2406 2407 /* set to allow Mirror bit in Module Header */ 2408 SOC_IF_ERROR_RETURN 2409 (soc_reg_field32_modify(unit, EGR_CONFIG_1r, REG_PORT_ANY, 2410 RING_MODEf, 1)); 2411 2412 /* The HW defaults for EGR_VLAN_CONTROL_1.VT_MISS_UNTAG == 1, which 2413 * causes the outer tag to be removed from packets that don't have 2414 * a hit in the egress vlan tranlation table. Set to 0 to disable this. 2415 */ 2416 rval = 0; 2417 soc_reg_field_set(unit, EGR_VLAN_CONTROL_1r, &rval, VT_MISS_UNTAGf, 0); 2418 2419 /* Enable pri/cfi remarking on egress ports. */ 2420 soc_reg_field_set(unit, EGR_VLAN_CONTROL_1r, &rval, REMARK_OUTER_DOT1Pf, 2421 1); 2422 PBMP_ALL_ITER(unit, port) { 2423 SOC_IF_ERROR_RETURN(WRITE_EGR_VLAN_CONTROL_1r(unit, port, rval)); 2424 } 2425 2426 SOC_PBMP_ASSIGN(pbmp, PBMP_ALL(unit)); 2427 SOC_PBMP_REMOVE(pbmp, PBMP_LB(unit)); 2428 SOC_IF_ERROR_RETURN(soc_mem_read(unit, ING_EN_EFILTER_BITMAPm, 2429 MEM_BLOCK_ANY, 0, &entry)); 2430 soc_mem_pbmp_field_set(unit, ING_EN_EFILTER_BITMAPm, &entry, BITMAPf, 2431 &pbmp); 2432 SOC_IF_ERROR_RETURN(soc_mem_write(unit, ING_EN_EFILTER_BITMAPm, 2433 MEM_BLOCK_ANY, 0, &entry)); 2434 SOC_IF_ERROR_RETURN(READ_CMIC_TXBUF_CONFIGr(unit, &rval)); 2435 soc_reg_field_set(unit, CMIC_TXBUF_CONFIGr, &rval, 2436 FIRST_SERVE_BUFFERS_WITH_EOP_CELLSf, 0); 2437 /* coverity[result_independent_of_operands] */ 2438 SOC_IF_ERROR_RETURN(WRITE_CMIC_TXBUF_CONFIGr(unit, rval)); 2439 2440 /* Multicast range initialization */ 2441 SOC_IF_ERROR_RETURN 2442 (soc_hbx_higig2_mcast_sizes_set(unit, 2443 soc_property_get(unit, spn_HIGIG2_MULTICAST_VLAN_RANGE, 2444 SOC_HBX_MULTICAST_RANGE_DEFAULT), 2445 soc_property_get(unit, spn_HIGIG2_MULTICAST_L2_RANGE, 2446 SOC_HBX_MULTICAST_RANGE_DEFAULT), 2447 soc_property_get(unit, spn_HIGIG2_MULTICAST_L3_RANGE, 2448 SOC_HBX_MULTICAST_RANGE_DEFAULT))); 2449 2450 if (soc_mspi_init(unit) != SOC_E_NONE) { 2451 LOG_ERROR(BSL_LS_SOC_COMMON, (BSL_META_U(unit, "unit %d : MSPI Init Failed\n"), unit)); 2452 } 2453 SOC_IF_ERROR_RETURN(soc_mem_clear( 2454 unit, MMU_RQE_QUEUE_OP_NODE_MAPm, COPYNO_ALL, TRUE)); 2455 SOC_IF_ERROR_RETURN(soc_mem_clear( 2456 unit, MMU_WRED_QUEUE_OP_NODE_MAPm, COPYNO_ALL, TRUE)); 2457 2458 SOC_IF_ERROR_RETURN(_soc_saber2_get_cfg_num(unit, &cfg_num)); 2459 if (cfg_num >= (sizeof(bcm56260_tdm)/sizeof(bcm56260_tdm[0]))) { 2460 LOG_WARN(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 2461 "Wrong cfg_num:%d exceeding max cfg_num: %d\n"), 2462 cfg_num, 2463 (int)(sizeof(bcm56260_tdm)/sizeof(bcm56260_tdm[0])))); 2464 return SOC_E_FAIL; 2465 } 2466 _sb2_config_id[unit] = cfg_num; 2467 2468 PBMP_ALL_ITER(unit, port) { 2469 if ((port == 0 ) || (port >= 29)) { 2470 continue; 2471 } 2472 SOC_IF_ERROR_RETURN(soc_saber2_port_init_config(unit, cfg_num, port)); 2473 } 2474 2475 SOC_IF_ERROR_RETURN(READ_AUX_ARB_CONTROL_2r(unit, &rval)); 2476 soc_reg_field_set(unit, AUX_ARB_CONTROL_2r, &rval, 2477 TCAM_ATOMIC_WRITE_ENABLEf, 1); 2478 SOC_IF_ERROR_RETURN(WRITE_AUX_ARB_CONTROL_2r(unit, rval)); 2479 2480 /* Setup SW2_FP_DST_ACTION_CONTROL */ 2481 fields[0] = HGTRUNK_RES_ENf; 2482 values[0] = 1; 2483 fields[1] = LAG_RES_ENf; 2484 values[1] = 1; 2485 SOC_IF_ERROR_RETURN(soc_reg_fields32_modify(unit, 2486 SW2_FP_DST_ACTION_CONTROLr, REG_PORT_ANY, 2, fields, values)); 2487 2488 /* In SB2, hardware logic for key/mask encoding and decoding is disabled */ 2489 SOC_IF_ERROR_RETURN(READ_EGR_BYPASS_CTRLr(unit, &rval)); 2490 soc_reg_field_set(unit, EGR_BYPASS_CTRLr, &rval, 2491 EFP_SW_ENC_DEC_TCAMf, 1); 2492 SOC_IF_ERROR_RETURN(WRITE_EGR_BYPASS_CTRLr(unit, rval)); 2493 2494 #ifdef INCLUDE_AVS 2495 soc_saber2_avs_init(unit); 2496 #endif /* INCLUDE_AVS */ 2497 2498 if (!SOC_WARM_BOOT(unit)) { 2499 /* TS-PLL and BS-PLL needs to be initialized only during cold-boot */ 2500 /* initializing ts pll and bs pll */ 2501 _soc_saber2_tspll_bspll_config(unit); 2502 } 2503 2504 /* Initializing subport configurations */ 2505 si->subport_group_max = SOC_SB2_SUBPORT_GROUP_MAX; 2506 si->pp_port_index_max = SOC_SB2_SUBPORT_PP_PORT_INDEX_MAX; 2507 si->pp_port_index_min = SOC_SB2_SUBPORT_PP_PORT_INDEX_MIN; 2508 si->subport_port_max = SOC_SB2_MAX_SUBPORTS; 2509 si->lp_tx_databuf_start_addr_max = SOC_SB2_LINKPHY_TX_DATA_BUF_START_ADDR_MAX; 2510 si->lp_tx_databuf_end_addr_min = SOC_SB2_LINKPHY_TX_DATA_BUF_END_ADDR_MIN; 2511 si->lp_tx_databuf_end_addr_max = SOC_SB2_LINKPHY_TX_DATA_BUF_END_ADDR_MAX; 2512 si->lp_tx_stream_start_addr_offset = SOC_SB2_LINKPHY_TX_STREAM_START_ADDR_OFFSET; 2513 si->lp_block_max = SOC_SB2_LINKPHY_BLOCK_MAX; 2514 si->lp_ports_max = SOC_SB2_MAX_LINKPHY_PORTS; 2515 si->lp_streams_per_slice_max = SOC_SB2_MAX_STREAMS_PER_SLICE; 2516 si->lp_streams_per_port_max = SOC_SB2_MAX_LINKPHY_STREAMS_PER_PORT; 2517 si->lp_streams_per_subport = SOC_SB2_MAX_STREAMS_PER_SUBPORT; 2518 2519 return SOC_E_NONE; 2520 } 2521 2522 tdm_cycles_info_t sb2_current_tdm_cycles_info[KT2_MAX_SPEEDS]; 2523 2524 #define SB2_MAX_TDM_FREQUENCY 16 2525 tdm_cycles_info_t sb2_tdm_cycles_info[SB2_MAX_TDM_FREQUENCY][KT2_MAX_SPEEDS]={ 2526 2527 /*TDM_A : 0:130MHz: 284 (41 * 7) Cycles Used */ 2528 {{78,71,4},{39/*60*/,35,8},{30,28,10},{7,6,41}, /*CMIC WRONG*/ 2529 {6,5,48},{0,0,0},{0,0,0}}, 2530 2531 /*TDM_AA: 1:130MHz: 140 (20 * 7) Cycles Used */ 2532 {{71,70,2},{36,35,4},{29,28,5},{7,7,20}, 2533 {6,6,24},{0,0,0},{0,0,0}}, 2534 2535 /*TDM_A1: 2:24MHz: 13 (4 * 4) Cycles Used */ 2536 {{13,13,1},{7,6,2},{5,2,3},{1,1,13}, 2537 {1,1,13},{0,0,0},{0,0,0}}, 2538 2539 /*TDM_A1A: 3:37MHz: 84 (21 * 4) Cycles Used */ 2540 {{22,21,4},{11,10,8},{10,7,9},{2,2,42}, 2541 {1,1,84},{0,0,0},{0,0,0}}, 2542 2543 /*TDM_B: 4:118MHz: 133 (23 * 6) Cycles Used */ 2544 {{70,67,2},{36/*53*/,34,4},{28,26,5},{7,7,19}, /*CMIC WRONG*/ 2545 {6,6,23},{0,0,0},{0,0,0}}, 2546 2547 /*TDM_B1: 5:118MHz: 120 (20 * 6) Cycles Used */ 2548 {{70,60,2},{35,30,4},{28,24,5},{7,7,18}, 2549 {5,5,24},{0,0,0},{0,0,0}}, 2550 2551 /*TDM_B1A: 6:118MHz: 121 (21 * 6) Cycles Used */ 2552 {{70,60,2},{35,30,4},{28,24,5},{7,7,18}, 2553 {5,5,25},{0,0,0},{0,0,0}}, 2554 2555 /*TDM_C,C1,C2: 7:130MHz: 141 (21 * 6) Cycles Used */ 2556 {{77,71,2},{38,35,4},{30,28,5},{7,7,20 /*21*/}, 2557 {6,6,24},{0,0,0},{0,0,0}}, 2558 2559 /*TDM_D 8:130MHz: 168 (28 * 6) Cycles Used */ 2560 {{77,56,3},{38,34,5},{30,28,6},{7,7,24}, 2561 {6,6,28},{0,0,0},{0,0,0}}, 2562 2563 /*TDM_E,E1,E3 9:75MHz: 81 (21 * 4) Cycles Used */ 2564 {{44,40,2},{22,20,4},{17,16,5},{4,4,20}, 2565 {3,3,27},{0,0,0},{0,0,0}}, 2566 2567 /*TDM_EA 10:75MHz: 16 (4 * 4) Cycles Used */ 2568 {{16,16,1},{16,16,1},{16,16,1},{4,4,4}, 2569 {3,3,6},{0,0,0},{0,0,0}}, 2570 2571 /*TDM_F 11:75MHz: 20 (5 * 4) Cycles Used */ 2572 {{20,20,1},{12,12,2},{12,12,2},{12,12,2}, 2573 {3,3,6},{0,0,0},{0,0,0}}, 2574 }; 2575 2576 2577 soc_error_t sb2_tdm_verify(int unit, 2578 uint32 *tdm, 2579 uint32 total_tdm_slots, 2580 uint32 tdm_freq, /* In MHHz */ 2581 uint32 *port_speed, 2582 uint32 lpbk_port_speed, 2583 uint32 *offender_port) 2584 { 2585 /* Following rules need to be met */ 2586 /* Rule1 : Each Loopback port need 2.5G bandwidth */ 2587 /* Rule2 : Each CMIC port need 2G bandwidth */ 2588 /* Rule3 : Loopback (LPBK) ports require min 3 cycle spacing among LPBK or 2589 CMIC ports */ 2590 /* Rule4 : Each subport in MXQPORT operates with 4 cycle TDM */ 2591 /* Rule5 : Each 10G-XAUI ports should be able to operate in 4x2.5G with 4 2592 slots allocated to each subport from the same MXQPORT */ 2593 soc_error_t rv=SOC_E_NONE; 2594 uint32 index=0; 2595 uint32 expected_tdm_cycles_min=0; 2596 uint32 expected_tdm_cycles_max=0; 2597 uint32 tdm_freq_index=0; 2598 uint32 speed_index=0; 2599 uint32 port=0; 2600 uint32 speed=0; 2601 uint32 worse_tdm_slot_spacing=0; 2602 uint32 prev_tdm_slot_spacing=0; 2603 uint32 next_tdm_slot_spacing=0; 2604 #if 0 2605 uint32 tdm_slot_spacing=0; 2606 #endif 2607 uint32 min_tdm_cycles=0; /* To Meet BW */ 2608 uint32 count=0; 2609 uint32 skip_count=0; 2610 uint32 mxqblock=0; 2611 uint32 outer_port=0; 2612 uint32 inner_port=0; 2613 uint32 spacing=0; 2614 uint32 loop=0; 2615 tdm_port_slots_info_t *head=NULL; 2616 tdm_port_slots_info_t *head1=NULL; 2617 tdm_port_slots_info_t *current=NULL; 2618 tdm_port_slots_info_t *current1=NULL; 2619 tdm_port_slots_info_t *prev = NULL; 2620 tdm_port_slots_info_t *temp=NULL; 2621 uint32 idle_flag=0; 2622 uint32 idle_rule=0; 2623 char base_tdm_str[80]; 2624 2625 /* Possible TDM frequencies 2626 80MHz(16Cycles) ,120MHz(20Cycles),155MHz(84Cycles), 2627 185MHz(80Cycles),185MHz(90Cycles) 2628 */ 2629 switch(tdm_freq) { 2630 case 130: 2631 if (total_tdm_slots == 284) { 2632 /*TDM_A : 0:130MHz: 284 (41 * 7) Cycles Used */ 2633 sal_strncpy(base_tdm_str, 2634 "TDM_A : 0:130MHz: 284 (41 * 7) Cycles Used", 2635 79); 2636 tdm_freq_index=0; 2637 expected_tdm_cycles_min=284; 2638 expected_tdm_cycles_max=284; 2639 } else if (total_tdm_slots == 141) { 2640 /*TDM_C,C1,C2: 7:130MHz: 141 (21 * 6) Cycles Used */ 2641 sal_strncpy(base_tdm_str, 2642 "TDM_AA,TDM_C,C1,C2: 7:130MHz:141 (21 * 6) Cycles Used", 2643 79); 2644 tdm_freq_index=7; 2645 expected_tdm_cycles_min=141; 2646 expected_tdm_cycles_max=141; 2647 } else if (total_tdm_slots == 168) { 2648 /*TDM_D: 8:130MHz: 168 (28 * 6) Cycles Used */ 2649 sal_strncpy(base_tdm_str, 2650 "TDM_D: 8:130MHz: 168 (28 * 6) Cycles Used", 2651 79); 2652 tdm_freq_index=8; 2653 expected_tdm_cycles_min=168; 2654 expected_tdm_cycles_max=168; 2655 } else { 2656 LOG_ERROR(BSL_LS_SOC_COMMON, 2657 (BSL_META_U(unit, 2658 "Unsupported tdm slots:%d\n"), 2659 total_tdm_slots)); 2660 return SOC_E_FAIL; 2661 } 2662 break; 2663 case 24: 2664 /*TDM_A1: 2:24MHz: 13 (4 * 4) Cycles Used */ 2665 sal_strncpy(base_tdm_str, 2666 "TDM_A1: 2:24MHz: 13 (4 * 4) Cycles Used ", 2667 79); 2668 tdm_freq_index=2; 2669 expected_tdm_cycles_min=13; 2670 expected_tdm_cycles_max=13; 2671 break; 2672 case 37: 2673 if (total_tdm_slots == 84) { 2674 /*TDM_A1A: 3:37MHz: 84 (21 * 4) Cycles Used */ 2675 sal_strncpy(base_tdm_str, 2676 "TDM_A1A: 3:37MHz: 84 (21 * 4) Cycles Used ", 2677 79); 2678 tdm_freq_index=3; 2679 expected_tdm_cycles_min=84; 2680 expected_tdm_cycles_max=84; 2681 } else { 2682 LOG_ERROR(BSL_LS_SOC_COMMON, 2683 (BSL_META_U(unit, 2684 "Unsupported tdm slots:%d\n"), 2685 total_tdm_slots)); 2686 return SOC_E_FAIL; 2687 } 2688 break; 2689 case 118: 2690 if (total_tdm_slots == 133) { 2691 /*TDM_B: 4:118MHz: 133 (23 * 6) Cycles Used */ 2692 sal_strncpy(base_tdm_str, 2693 "TDM_B: 4:118MHz: 133 (23 * 6) Cycles Used ", 2694 79); 2695 tdm_freq_index=4; 2696 expected_tdm_cycles_min=133; 2697 expected_tdm_cycles_max=133; 2698 } else if (total_tdm_slots == 120) { 2699 /*TDM_B1: 5:118MHz: 120 (20 * 6) Cycles Used */ 2700 sal_strncpy(base_tdm_str, 2701 "TDM_B1: 5:118MHz: 120 (20 * 6) Cycles Used ", 2702 79); 2703 tdm_freq_index=5; 2704 expected_tdm_cycles_min=120; 2705 expected_tdm_cycles_max=120; 2706 } else if (total_tdm_slots == 121) { 2707 /*TDM_B1A: 6:118MHz: 121 (21 * 6) Cycles Used */ 2708 sal_strncpy(base_tdm_str, 2709 "TDM_B1A: 6:118MHz: 121 (21 * 6) Cycles Used ", 2710 79); 2711 tdm_freq_index=6; 2712 expected_tdm_cycles_min=121; 2713 expected_tdm_cycles_max=121; 2714 } else { 2715 LOG_ERROR(BSL_LS_SOC_COMMON, 2716 (BSL_META_U(unit, 2717 "Unsupported tdm slots:%d\n"), 2718 total_tdm_slots)); 2719 return SOC_E_FAIL; 2720 } 2721 break; 2722 case 75: 2723 if (total_tdm_slots == 81) { 2724 /*TDM_E,E1,E3 9:75MHz: 81 (21 * 4) Cycles Used */ 2725 sal_strncpy(base_tdm_str, 2726 "TDM_E,E1,E3 9:75MHz: 81 (21 * 4) Cycles Used ", 2727 79); 2728 tdm_freq_index=9; 2729 expected_tdm_cycles_min=81; 2730 expected_tdm_cycles_max=81; 2731 } else if (total_tdm_slots == 16) { 2732 /*TDM_EA 10:75MHz: 16 (4 * 4) Cycles Used */ 2733 sal_strncpy(base_tdm_str, 2734 "TDM_EA 10:75MHz: 16 (4 * 4) Cycles Used ", 2735 79); 2736 tdm_freq_index=10; 2737 expected_tdm_cycles_min=16; 2738 expected_tdm_cycles_max=16; 2739 } else if (total_tdm_slots == 20) { 2740 /*TDM_F 11:75MHz: 20 (5 * 4) Cycles Used */ 2741 sal_strncpy(base_tdm_str, 2742 "TDM_F 11:75MHz: 20 (5 * 4) Cycles Used ", 2743 79); 2744 tdm_freq_index=11; 2745 expected_tdm_cycles_min=20; 2746 expected_tdm_cycles_max=20; 2747 } else { 2748 LOG_ERROR(BSL_LS_SOC_COMMON, 2749 (BSL_META_U(unit, 2750 "Unsupported tdm slots:%d\n"), 2751 total_tdm_slots)); 2752 return SOC_E_FAIL; 2753 } 2754 break; 2755 default: 2756 LOG_ERROR(BSL_LS_SOC_COMMON, 2757 (BSL_META_U(unit, 2758 "Unsupported tdm frequency:%d\n"), 2759 tdm_freq)); 2760 return SOC_E_FAIL; 2761 } 2762 LOG_VERBOSE(BSL_LS_SOC_COMMON, 2763 (BSL_META_U(unit, 2764 "\nINFO: BaseTdmStr:%s :Index %d:MinCycles%d:MaxCycle%d\n"), 2765 base_tdm_str, 2766 tdm_freq_index, expected_tdm_cycles_min, expected_tdm_cycles_max)); 2767 if (!((total_tdm_slots >= expected_tdm_cycles_min) && 2768 (total_tdm_slots <= expected_tdm_cycles_max))) { 2769 LOG_ERROR(BSL_LS_SOC_COMMON, 2770 (BSL_META_U(unit, 2771 "Unsupported tdm cycles:%d (min:%d max:%d\n"), 2772 total_tdm_slots, 2773 expected_tdm_cycles_min,expected_tdm_cycles_max)); 2774 return SOC_E_FAIL; 2775 } 2776 2777 idle_flag=0; 2778 idle_rule = 0; 2779 /* Initialize list */ 2780 for (port=0;port < SB2_MAX_LOGICAL_PORTS ; port++) { 2781 sb2_tdm_port_slots_info[port].prev=&sb2_tdm_port_slots_info[port]; 2782 sb2_tdm_port_slots_info[port].next=&sb2_tdm_port_slots_info[port]; 2783 sb2_tdm_port_slots_info[port].position = -1; 2784 } 2785 for (index=0; index < total_tdm_slots; index++) { 2786 if ((tdm[index] == SB2_IDLE1) || 2787 (tdm[index] == SB2_IDLE)) { 2788 if (tdm[index] == SB2_IDLE) { 2789 if (idle_flag == 1) { 2790 idle_rule = 1; 2791 } 2792 idle_flag=1; 2793 } 2794 skip_count++; 2795 continue; 2796 } 2797 if (((index - 1) != 0) && (index != total_tdm_slots - 1) && 2798 (idle_flag == 1) && (idle_rule == 0)) { 2799 LOG_ERROR(BSL_LS_SOC_COMMON, 2800 (BSL_META_U(unit, 2801 "### Internal Error: TDM Verification failed \n" 2802 "### Two consecutive idle not found at position:%d\n" 2803 "### TCAM Atomicity might get affected.\n"), 2804 index - 1)); 2805 *offender_port = SB2_IDLE; 2806 return SOC_E_CONFIG; 2807 } 2808 idle_flag=0; 2809 port = tdm[index]; 2810 if (sb2_tdm_port_slots_info[port].position == -1) { 2811 /* First Entry */ 2812 sb2_tdm_port_slots_info[port].position = index; 2813 skip_count++; 2814 continue; 2815 } 2816 head = current = &sb2_tdm_port_slots_info[port]; 2817 while(current->next !=head) { 2818 current = current->next; 2819 } 2820 current->next=sal_alloc(sizeof(tdm_port_slots_info_t),"TDM Pointer"); 2821 count++; 2822 LOG_VERBOSE(BSL_LS_SOC_COMMON, 2823 (BSL_META_U(unit, 2824 "Count=%d SkipCount:%d Port:%d Addr:%p\n"), 2825 count,skip_count,port,(void *)current->next)); 2826 2827 current->next->position=index; 2828 current->next->prev=current; 2829 current->next->next=head; 2830 head->prev=current->next; 2831 } 2832 if (idle_rule == 0) { 2833 /* Special case */ 2834 if (!((tdm[0] == SB2_IDLE) && 2835 (tdm[total_tdm_slots-1] == SB2_IDLE))) { 2836 LOG_ERROR(BSL_LS_SOC_COMMON, 2837 (BSL_META_U(unit, 2838 "### Internal Error: TDM Verification failed \n" 2839 "### Two consecutive idle not found at Edges \n" 2840 "### TCAM Atomicity might get affected.\n"))); 2841 *offender_port = SB2_IDLE1; 2842 return SOC_E_CONFIG; 2843 } 2844 } 2845 LOG_VERBOSE(BSL_LS_SOC_COMMON, 2846 (BSL_META_U(unit, 2847 "Final Count=%d SkipCount:%d\n"),count,skip_count)); 2848 LOG_VERBOSE(BSL_LS_SOC_COMMON, 2849 (BSL_META_U(unit, 2850 "Verifying rule \n"))); 2851 LOG_VERBOSE(BSL_LS_SOC_COMMON, 2852 (BSL_META_U(unit, 2853 "Rule3: Loopback (LPBK) ports require min 3 cycle spacing " 2854 "among LPBK or CMIC ports \n"))); 2855 if (sb2_tdm_port_slots_info[SB2_LPBK].position == -1) { 2856 LOG_CLI((BSL_META_U(unit, 2857 "Loopback port missing in configuration \n"))); 2858 return SOC_E_FAIL; 2859 } 2860 if (sb2_tdm_port_slots_info[SB2_CMIC].position == -1) { 2861 LOG_CLI((BSL_META_U(unit, 2862 "CMIC port missing in configuration \n"))); 2863 return SOC_E_FAIL; 2864 } 2865 head = current = &sb2_tdm_port_slots_info[SB2_LPBK]; 2866 do { 2867 prev = current->prev; 2868 if ( current->position != prev->position ) { 2869 prev_tdm_slot_spacing = 2870 (current->position - prev->position) > 0 ? 2871 (current->position - prev->position)-1: 2872 (total_tdm_slots - prev->position + 2873 current->position) - 1; 2874 next_tdm_slot_spacing = 2875 (current->next->position - current->position) >0 ? 2876 (current->next->position - current->position)-1: 2877 (total_tdm_slots - current->position + 2878 current->next->position) - 1; 2879 if (prev_tdm_slot_spacing < 3) { 2880 LOG_ERROR(BSL_LS_SOC_COMMON, 2881 (BSL_META_U(unit, 2882 "Loopback Ports need min 3 spacing but(prev)found" 2883 "(current:%d , prev:%d)=%d\n"), 2884 current->position,prev->position,prev_tdm_slot_spacing)); 2885 rv = SOC_E_FAIL; 2886 continue; 2887 } 2888 if (next_tdm_slot_spacing < 3) { 2889 LOG_ERROR(BSL_LS_SOC_COMMON, 2890 (BSL_META_U(unit, 2891 "Loopback Ports need min 3 spacing but(next)found" 2892 "(current:%d , prev:%d)=%d\n"), 2893 current->position,prev->position,next_tdm_slot_spacing)); 2894 rv = SOC_E_CONFIG; 2895 *offender_port = SB2_LPBK; 2896 continue; 2897 } 2898 } else { 2899 prev_tdm_slot_spacing = next_tdm_slot_spacing = 0; 2900 } 2901 #if 0 2902 head1 = current1 = &sb2_tdm_port_slots_info[SB2_CMIC]; 2903 do { 2904 tdm_slot_spacing = (current->position - current1->position) > 0 ? 2905 (current->position - current1->position)-1: 2906 (total_tdm_slots - current1->position + 2907 current->position) - 1 ; 2908 if (tdm_slot_spacing < 3) { 2909 LOG_ERROR(BSL_LS_SOC_COMMON, 2910 (BSL_META_U(unit, 2911 "Loopback and CMIC ports need min 3 spacing but " 2912 "found:%u" "(Loopack current:%d , CMIC Current:%d)\n"), 2913 tdm_slot_spacing, 2914 current->position,current1->position)); 2915 rv = SOC_E_CONFIG; 2916 *offender_port=SB2_LPBK; 2917 continue; 2918 } 2919 current1 = current1->next; 2920 }while ((current1 !=head1) && (rv == SOC_E_NONE)); 2921 #endif 2922 current = current->next; 2923 } while ((current !=head) && (rv == SOC_E_NONE)); 2924 LOG_VERBOSE(BSL_LS_SOC_COMMON, 2925 (BSL_META_U(unit, 2926 "Verifying rules \n"))); 2927 LOG_VERBOSE(BSL_LS_SOC_COMMON, 2928 (BSL_META_U(unit, 2929 "Rule1 : Each Loopback port need 2.5G bandwidth \n"))); 2930 LOG_VERBOSE(BSL_LS_SOC_COMMON, 2931 (BSL_META_U(unit, 2932 "Rule2 : Each CMIC port need 2G bandwidth \n"))); 2933 for (index=0;index < SB2_MAX_LOGICAL_PORTS && rv == SOC_E_NONE ;index++ ) { 2934 port = index ; 2935 if (sb2_tdm_port_slots_info[port].position == -1) { 2936 continue; 2937 } 2938 LOG_VERBOSE(BSL_LS_SOC_COMMON, 2939 (BSL_META_U(unit, 2940 " %d ==>\n\n"),port)); 2941 switch(port) { 2942 case SB2_CMIC: 2943 LOG_VERBOSE(BSL_LS_SOC_COMMON, 2944 (BSL_META_U(unit, 2945 "CMIM \n"))); 2946 speed =2000; 2947 break; 2948 case SB2_LPBK: 2949 LOG_VERBOSE(BSL_LS_SOC_COMMON, 2950 (BSL_META_U(unit, 2951 "LOOPBAKC \n"))); 2952 speed =lpbk_port_speed; 2953 break; 2954 default: 2955 LOG_VERBOSE(BSL_LS_SOC_COMMON, 2956 (BSL_META_U(unit, 2957 " Port:%d Speed %d ==>\n\n"), 2958 port,port_speed[port-1])); 2959 speed = port_speed[port-1]; 2960 break; 2961 } 2962 if ((speed == 0) && (!SOC_PBMP_MEMBER((PBMP_ALL(unit)), port))) { 2963 /* Eagle ports are not removed from TDM calendar 2964 * Eventhough not active after lane op. Ignore those 2965 */ 2966 continue; 2967 } 2968 2969 switch(speed) { 2970 case 1000: 2971 speed_index=0; 2972 break; 2973 case 2000: 2974 speed_index=1; 2975 break; 2976 case 2500: 2977 speed_index=2; 2978 break; 2979 case 10000: 2980 case 10500: /* Might need ut fir HG11 */ 2981 case 11000: /* Might need ut fir HG11 */ 2982 speed_index=3; 2983 break; 2984 case 12500: /* Special case for LPBK port */ 2985 case 13000: 2986 speed_index=4; 2987 break; 2988 case 20000: 2989 speed_index=5; 2990 break; 2991 case 21000: 2992 speed_index=6; 2993 break; 2994 default: 2995 LOG_ERROR(BSL_LS_SOC_COMMON, 2996 (BSL_META_U(unit, 2997 "Unsupported speed:%d \n"),speed)); 2998 return SOC_E_FAIL; 2999 } 3000 worse_tdm_slot_spacing=sb2_tdm_cycles_info[tdm_freq_index][speed_index]. 3001 worse_tdm_slot_spacing; 3002 min_tdm_cycles=sb2_tdm_cycles_info[tdm_freq_index][speed_index]. 3003 min_tdm_cycles; 3004 3005 count=0; 3006 head = current = &sb2_tdm_port_slots_info[port]; 3007 do { 3008 prev = current->prev; 3009 if (current->position != prev->position ) { 3010 prev_tdm_slot_spacing = 3011 (current->position - prev->position)> 0 ? 3012 (current->position - prev->position)-1: 3013 (total_tdm_slots - prev->position + 3014 current->position) - 1 ; 3015 next_tdm_slot_spacing = 3016 (current->next->position - current->position) > 0 ? 3017 (current->next->position - current->position)-1: 3018 (total_tdm_slots - current->position + 3019 current->next->position) - 1; 3020 } else { 3021 prev_tdm_slot_spacing = next_tdm_slot_spacing = 0; 3022 } 3023 LOG_VERBOSE(BSL_LS_SOC_COMMON, 3024 (BSL_META_U(unit, 3025 "Pos:%d Spacing (Prev %d - %d = )%d" 3026 "(Next %d - %d = )%d\n"), current->position, 3027 current->position , prev->position , 3028 prev_tdm_slot_spacing, current->next->position , 3029 current->position , next_tdm_slot_spacing)); 3030 if ((prev_tdm_slot_spacing > worse_tdm_slot_spacing) || 3031 (next_tdm_slot_spacing > worse_tdm_slot_spacing)) { 3032 if (port == SB2_CMIC) { 3033 /* Exception for worst TDM slot spacing for CMIC port */ 3034 LOG_VERBOSE(BSL_LS_SOC_COMMON, 3035 (BSL_META_U(unit, 3036 "WorseSpacing:%d (prev:%d next:%d)" 3037 "NOK !!!! port:%d\n"), 3038 worse_tdm_slot_spacing, 3039 prev_tdm_slot_spacing, next_tdm_slot_spacing, 3040 port)); 3041 LOG_VERBOSE(BSL_LS_SOC_COMMON, 3042 (BSL_META_U(unit,"**ATTN:SKIPPING FOR TIME-BEING \n"))); 3043 } else { 3044 LOG_ERROR(BSL_LS_SOC_COMMON, 3045 (BSL_META_U(unit, 3046 "WorseSpacing:%d (prev:%d next:%d)" 3047 "NOK !!!! port:%d\n"), 3048 worse_tdm_slot_spacing, 3049 prev_tdm_slot_spacing, next_tdm_slot_spacing, 3050 port)); 3051 rv = SOC_E_CONFIG; 3052 *offender_port=port; 3053 continue; 3054 } 3055 } 3056 count++; 3057 current = current->next; 3058 } while ((current !=head) && (rv == SOC_E_NONE)) ; 3059 LOG_VERBOSE(BSL_LS_SOC_COMMON, 3060 (BSL_META_U(unit, 3061 "TDM Cycles: %d \n"),count)); 3062 if (count < min_tdm_cycles) { 3063 LOG_ERROR(BSL_LS_SOC_COMMON, 3064 (BSL_META_U(unit, 3065 "min_tdm_cycles:%dNOK !!!! port:%d\n"), 3066 min_tdm_cycles,port)); 3067 rv = SOC_E_CONFIG; 3068 *offender_port=port; 3069 continue; 3070 } 3071 LOG_VERBOSE(BSL_LS_SOC_COMMON, 3072 (BSL_META_U(unit, 3073 "n== %d <==\n\n"),port)); 3074 } 3075 3076 LOG_VERBOSE(BSL_LS_SOC_COMMON, 3077 (BSL_META_U(unit, 3078 "Verifying rule \n"))); 3079 LOG_VERBOSE(BSL_LS_SOC_COMMON, 3080 (BSL_META_U(unit, 3081 "Rule4 : Each subport in MXQPORT operates with 4 cycle TDM \n"))); 3082 LOG_VERBOSE(BSL_LS_SOC_COMMON, 3083 (BSL_META_U(unit, 3084 "Verifying MXQports spacing concern\n"))); 3085 for(mxqblock=0;mxqblock<(SB2_MAX_BLOCKS-1) && rv == SOC_E_NONE ;mxqblock++) { 3086 for(index=0; 3087 index<SB2_MAX_PORTS_PER_BLOCK && rv == SOC_E_NONE; 3088 index++) { 3089 outer_port = (*sb2_block_ports[unit])[mxqblock][index]; 3090 if (outer_port == 0xFF) { 3091 if ((mxqblock == 7) && (index == 3)) { 3092 outer_port = 40; 3093 } else { 3094 continue; 3095 } 3096 } 3097 if (sb2_tdm_port_slots_info[outer_port].position == -1) { 3098 continue; 3099 } 3100 head = current = &sb2_tdm_port_slots_info[outer_port]; 3101 do { 3102 for(loop=0;loop<SB2_MAX_PORTS_PER_BLOCK; loop++) { 3103 inner_port=(*sb2_block_ports[unit])[mxqblock][loop]; 3104 if (inner_port == 0xFF) { 3105 if ((mxqblock == 7) && (loop == 3)) { 3106 inner_port = 40; 3107 } else { 3108 continue; 3109 } 3110 } 3111 if ( inner_port == outer_port) { 3112 continue; 3113 } 3114 if (sb2_tdm_port_slots_info[inner_port].position == -1) { 3115 continue; 3116 } 3117 head1 = current1 = &sb2_tdm_port_slots_info[inner_port]; 3118 do { 3119 spacing = (current->position - current1->position) > 0 ? 3120 (current->position - current1->position)-1: 3121 (total_tdm_slots - current1->position + 3122 current->position) - 1; 3123 if (spacing < 3) { 3124 LOG_ERROR(BSL_LS_SOC_COMMON, 3125 (BSL_META_U(unit, 3126 "Outer Port:%d Inner Port:%d " 3127 "MXQSpacing Issue" 3128 "Expected > 4 but observed %d\n"), 3129 outer_port,inner_port,spacing)); 3130 rv = SOC_E_CONFIG; 3131 *offender_port=outer_port; 3132 continue; 3133 } 3134 current1 = current1->next; 3135 } while ((current1 !=head1) && (rv == SOC_E_NONE)); 3136 } 3137 current = current->next; 3138 } while ((current !=head) && (rv == SOC_E_NONE)); 3139 } 3140 } 3141 3142 /* Free allocated resources */ 3143 count=0; 3144 for (port=0;port < SB2_MAX_LOGICAL_PORTS ; port++) { 3145 head = current = &sb2_tdm_port_slots_info[port]; 3146 do { 3147 temp = current->next; 3148 if (current != head) { 3149 count++; 3150 LOG_VERBOSE(BSL_LS_SOC_COMMON, 3151 (BSL_META_U(unit, 3152 "Freed count :%d\n"),count)); 3153 sal_free(current); 3154 } 3155 current = temp; 3156 } while (current != head); 3157 sb2_tdm_port_slots_info[port].prev=NULL; 3158 sb2_tdm_port_slots_info[port].next=NULL; 3159 sb2_tdm_port_slots_info[port].position = -1; 3160 } 3161 sal_memcpy(&sb2_current_tdm_cycles_info, 3162 &sb2_tdm_cycles_info[tdm_freq_index][0], 3163 sizeof(tdm_cycles_info_t)*KT2_MAX_SPEEDS); 3164 return rv; 3165 return SOC_E_NONE; 3166 } 3167 3168 void soc_saber2_save_tdm_pos(int unit, uint32 new_tdm_size,uint32 *new_tdm) { 3169 uint32 pos=0; 3170 uint8 port=0; 3171 uint8 block=0; 3172 uint8 total_slots=0; 3173 3174 sal_memset(sb2_tdm_pos_info,0,sizeof(sb2_tdm_pos_info)); 3175 for (pos = 0; pos < new_tdm_size ; pos++) { 3176 port= new_tdm[pos]; 3177 if ((port == SB2_IDLE) || (port == SB2_IDLE1) || 3178 (port == SB2_LPBK) || (port == SB2_CMIC)) { 3179 continue; 3180 } 3181 if(port > SB2_MAX_PHYSICAL_PORTS ) { 3182 LOG_ERROR(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 3183 "tdm_size %d, pos %d, port %d \n"), 3184 new_tdm_size, pos, port)); 3185 3186 } else { 3187 block = (*sb2_port_to_block[unit])[port - 1]; 3188 total_slots = sb2_tdm_pos_info[block].total_slots; 3189 sb2_tdm_pos_info[block].pos[total_slots]=pos; 3190 sb2_tdm_pos_info[block].total_slots++; 3191 } 3192 } 3193 3194 sal_memcpy(sb2_current_tdm,new_tdm,new_tdm_size*sizeof(new_tdm[0])); 3195 sb2_current_tdm_size=new_tdm_size; 3196 3197 } 3198 3199 /* This function splits the occurance of first port of the block into 4 ports */ 3200 /* Make sure that the tdm of the block is not already split */ 3201 void sb2_block_tdm_split(int unit, uint32 *tdm, 3202 uint32 total_tdm_slots, uint32 block) 3203 { 3204 uint32 index=0, count=0; 3205 uint32 first_port; 3206 3207 first_port = (*sb2_block_ports[unit])[block][0]; 3208 for (index=0; index < total_tdm_slots ; index++ ) { 3209 /* Split first port occurance in to 4 */ 3210 if (tdm[index] == first_port) { 3211 tdm[index] = first_port + (count % 4); 3212 count++; 3213 } 3214 3215 } 3216 } 3217 3218 void sb2_tdm_replace(uint32 *tdm, uint32 total_tdm_slots, 3219 uint32 src, uint32 dst,uint32 one_time) 3220 { 3221 uint32 index=0; 3222 for (index=0; index < total_tdm_slots ; index++ ) { 3223 if (tdm[index] == src) { 3224 tdm[index] = dst; 3225 if (one_time) { 3226 break; 3227 } 3228 } 3229 } 3230 } 3231 3232 void sb2_tdm_swap(uint32 *tdm, uint32 total_tdm_slots, 3233 uint32 src, uint32 dst) 3234 { 3235 uint32 index=0; 3236 uint32 temp_index=0; 3237 uint32 temp=0; 3238 for (index=0; index < total_tdm_slots ; index++ ) { 3239 if (tdm[index] == src) { 3240 temp_index=index; 3241 } 3242 if (tdm[index] == dst) { 3243 temp = tdm[temp_index]; 3244 tdm[temp_index]=dst; 3245 tdm[index]=temp; 3246 } 3247 } 3248 } 3249 3250 soc_error_t 3251 soc_saber2_reconfigure_tdm(int unit,uint32 new_tdm_size,uint32 *new_tdm) 3252 { 3253 uint8 new_tdm_no=0; 3254 soc_mem_t tdm_table[]={IARB_TDM_TABLEm , IARB_TDM_TABLE_1m}; 3255 soc_field_t wrap_ptr[]={TDM_WRAP_PTRf , TDM_1_WRAP_PTRf}; 3256 uint32 lls_tdm_size=0; 3257 lls_port_tdm_entry_t *lls_tdm=NULL; 3258 uint32 iarb_size=0; 3259 iarb_tdm_table_entry_t *iarb_tdm=NULL; 3260 int iter=0; 3261 uint32 index; 3262 uint32 rval; 3263 int cfg_num; 3264 3265 SOC_IF_ERROR_RETURN(_soc_saber2_get_cfg_num(unit, &cfg_num)); 3266 if (cfg_num >= (sizeof(bcm56260_tdm)/sizeof(bcm56260_tdm[0]))) { 3267 return SOC_E_FAIL; 3268 } 3269 3270 SOC_IF_ERROR_RETURN(READ_IARB_TDM_CONTROLr(unit, &rval)); 3271 old_tdm_no = soc_reg_field_get(unit, IARB_TDM_CONTROLr, rval, SELECT_TDMf); 3272 new_tdm_no = (old_tdm_no + 1)%2; 3273 3274 iarb_size = soc_mem_index_count(unit,IARB_TDM_TABLEm) * 3275 sizeof(iarb_tdm_table_entry_t); 3276 iarb_tdm = soc_cm_salloc(unit,iarb_size, "iarb_tdm_table_entry_t"); 3277 if (iarb_tdm == NULL) { 3278 return SOC_E_MEMORY; 3279 } 3280 sal_memset(iarb_tdm,0,iarb_size); 3281 3282 lls_tdm_size = soc_mem_index_count(unit,LLS_PORT_TDMm) * 3283 sizeof(lls_port_tdm_entry_t); 3284 lls_tdm = soc_cm_salloc(unit,lls_tdm_size, "lls_port_tdm_entry_t"); 3285 if (lls_tdm == NULL) { 3286 soc_cm_sfree(unit,iarb_tdm); 3287 return SOC_E_MEMORY; 3288 } 3289 sal_memset(lls_tdm,0,lls_tdm_size); 3290 3291 for (index = 0; index < new_tdm_size; index++) { 3292 soc_IARB_TDM_TABLEm_field32_set(unit, &iarb_tdm[index], PORT_NUMf, 3293 new_tdm[index]); 3294 } 3295 soc_mem_write_range(unit, tdm_table[new_tdm_no], MEM_BLOCK_ALL, 0, 3296 new_tdm_size, iarb_tdm); 3297 soc_cm_sfree(unit,iarb_tdm); 3298 3299 for (index = 0; index < new_tdm_size/2; index++) { 3300 soc_LLS_PORT_TDMm_field32_set(unit, &lls_tdm[index], 3301 PORT_ID_0f, new_tdm[index*2]); 3302 if ( new_tdm[index*2] < SB2_IDLE ) { 3303 soc_LLS_PORT_TDMm_field32_set(unit, &lls_tdm[index], 3304 PORT_ID_0_ENABLEf, 1); 3305 } else { 3306 LOG_VERBOSE(BSL_LS_SOC_COMMON, 3307 (BSL_META_U(unit, 3308 "IDLE SLOTs so PORT_ID_0_ENABLEf=0 \ 3309 for index=%d\n"), index)); 3310 soc_LLS_PORT_TDMm_field32_set(unit, &lls_tdm[index], 3311 PORT_ID_0_ENABLEf, 0); 3312 } 3313 3314 soc_LLS_PORT_TDMm_field32_set(unit, &lls_tdm[index], 3315 PORT_ID_1f, new_tdm[(index*2) + 1]); 3316 if ( new_tdm[(index*2)+1] < SB2_IDLE ) { 3317 soc_LLS_PORT_TDMm_field32_set(unit, &lls_tdm[index], 3318 PORT_ID_1_ENABLEf, 1); 3319 } else { 3320 LOG_VERBOSE(BSL_LS_SOC_COMMON, 3321 (BSL_META_U(unit, 3322 "IDLE SLOTs so PORT_ID_1_ENABLEf=0 \ 3323 for index=%d\n"), index)); 3324 soc_LLS_PORT_TDMm_field32_set(unit, &lls_tdm[index], 3325 PORT_ID_1_ENABLEf, 0); 3326 } 3327 } /* for index */ 3328 3329 if (new_tdm_size % 2) { 3330 LOG_CLI((BSL_META_U(unit, 3331 "ODD TDM SIZE \n"))); 3332 soc_LLS_PORT_TDMm_field32_set(unit, &lls_tdm[index*2], 3333 PORT_ID_0_ENABLEf, 1); 3334 soc_LLS_PORT_TDMm_field32_set(unit, &lls_tdm[index*2], 3335 PORT_ID_0f, new_tdm[(index*2)]); 3336 soc_LLS_PORT_TDMm_field32_set(unit, &lls_tdm[(index*2)+1], 3337 PORT_ID_1_ENABLEf, 0); 3338 soc_LLS_PORT_TDMm_field32_set(unit, &lls_tdm[(index*2)+1], 3339 PORT_ID_1f, 0); 3340 index++; 3341 } 3342 3343 soc_mem_write_range(unit, LLS_PORT_TDMm, MEM_BLOCK_ALL, 3344 new_tdm_no*256, (new_tdm_no*256) + index, 3345 lls_tdm); 3346 soc_cm_sfree(unit,lls_tdm); 3347 3348 SOC_IF_ERROR_RETURN(READ_IARB_TDM_CONTROLr(unit, &rval)); 3349 soc_reg_field_set(unit, IARB_TDM_CONTROLr, &rval, DISABLEf, 0); 3350 soc_reg_field_set(unit, IARB_TDM_CONTROLr, &rval, 3351 wrap_ptr[new_tdm_no],new_tdm_size -1); 3352 soc_reg_field_set(unit, IARB_TDM_CONTROLr, &rval, SELECT_TDMf, new_tdm_no); 3353 SOC_IF_ERROR_RETURN(WRITE_IARB_TDM_CONTROLr(unit, rval)); 3354 3355 if (bsl_check(bslLayerSoc, bslSourceCommon, bslSeverityVerbose, unit)) { 3356 kt2_tdm_display(unit,new_tdm,new_tdm_size, 3357 bcm56260_tdm_info[cfg_num].row, 3358 bcm56260_tdm_info[cfg_num].col); 3359 } 3360 3361 SOC_IF_ERROR_RETURN(WRITE_LLS_TDM_CAL_CFG_SWITCHr(unit, 1)); 3362 if ((SAL_BOOT_BCMSIM || SAL_BOOT_PLISIM)) { 3363 SOC_IF_ERROR_RETURN(READ_LLS_TDM_CAL_CFGr(unit, &rval)); 3364 soc_reg_field_set(unit, LLS_TDM_CAL_CFGr, &rval, 3365 CURRENT_CALENDARf,new_tdm_no); 3366 SOC_IF_ERROR_RETURN(WRITE_LLS_TDM_CAL_CFGr(unit, rval)); 3367 } 3368 3369 do { 3370 SOC_IF_ERROR_RETURN(READ_LLS_TDM_CAL_CFGr(unit, &rval)); 3371 sal_udelay(100); 3372 if (soc_reg_field_get(unit, LLS_TDM_CAL_CFGr, rval, 3373 CURRENT_CALENDARf) == new_tdm_no) { 3374 break; 3375 } 3376 } while (iter++ < 100000); 3377 3378 if (iter >= 100000) { 3379 LOG_ERROR(BSL_LS_SOC_COMMON, 3380 (BSL_META_U(unit, "LLS Calendar switch failed !!\n"))); 3381 return SOC_E_INTERNAL; 3382 } 3383 3384 old_tdm_no = new_tdm_no; 3385 soc_saber2_save_tdm_pos(unit, new_tdm_size,new_tdm); 3386 3387 return SOC_E_NONE; 3388 } 3389 3390 STATIC soc_error_t 3391 _soc_saber2_mmu_tdm_init(int unit) 3392 { 3393 soc_error_t rv = SOC_E_NONE; 3394 uint32 *arr=NULL; 3395 uint32 row = 0, col = 0; 3396 uint32 offender_port=0; 3397 3398 int i, tdm_size = 0,tdm_freq = 0, cfg_num; 3399 iarb_tdm_table_entry_t iarb_tdm; 3400 lls_port_tdm_entry_t lls_tdm; 3401 uint32 rval, arr_ele; 3402 uint16 dev_id; 3403 uint8 rev_id; 3404 uint32 port_enable_value=0; 3405 uint32 lpbk_port_speed=0; 3406 int loop_index, block; 3407 3408 soc_cm_get_id(unit, &dev_id, &rev_id); 3409 SOC_IF_ERROR_RETURN(_soc_saber2_get_cfg_num(unit, &cfg_num)); 3410 if (cfg_num >= (sizeof(bcm56260_tdm)/sizeof(bcm56260_tdm[0]))) { 3411 LOG_ERROR(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 3412 "Wrong cfg_num:%d exceeding max cfg_num: %d\n"), 3413 cfg_num, 3414 (int)(sizeof(bcm56260_tdm)/sizeof(bcm56260_tdm[0])))); 3415 return SOC_E_FAIL; 3416 } 3417 3418 switch(dev_id) { 3419 case BCM56260_DEVICE_ID: 3420 case BCM56261_DEVICE_ID: 3421 case BCM56265_DEVICE_ID: 3422 case BCM56266_DEVICE_ID: 3423 3424 case BCM56262_DEVICE_ID: 3425 case BCM56267_DEVICE_ID: 3426 case BCM56263_DEVICE_ID: 3427 case BCM56268_DEVICE_ID: 3428 3429 case BCM56460_DEVICE_ID: 3430 case BCM56461_DEVICE_ID: 3431 case BCM56465_DEVICE_ID: 3432 case BCM56466_DEVICE_ID: 3433 3434 case BCM56462_DEVICE_ID: 3435 case BCM56467_DEVICE_ID: 3436 3437 case BCM56463_DEVICE_ID: 3438 case BCM56468_DEVICE_ID: 3439 3440 case BCM56233_DEVICE_ID: 3441 tdm_size= bcm56260_tdm_info[cfg_num].tdm_size; 3442 tdm_freq= bcm56260_tdm_info[cfg_num].tdm_freq; 3443 row= bcm56260_tdm_info[cfg_num].row; 3444 col= bcm56260_tdm_info[cfg_num].col; 3445 LOG_DEBUG(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 3446 "Cfg=%d freq=%d size=%d raw=%d col=%d \n"), 3447 cfg_num,tdm_freq,tdm_size,row,col)); 3448 arr = bcm56260_tdm[cfg_num]; 3449 3450 switch(cfg_num) { 3451 /* ------------------- */ 3452 /* 56260 Configuration */ 3453 /* ------------------- */ 3454 case BCM56260_DEVICE_ID_OFFSET_CFG + 1: 3455 /* 56260_1 */ 3456 /* 12x 2.5G + 2xXFI + 12.5G LPBK */ 3457 sal_memcpy(arr, 3458 &sb2_tdm_56260_B_ref[0],sizeof(sb2_tdm_56260_B_ref)); 3459 lpbk_port_speed=2500; 3460 break; 3461 case BCM56260_DEVICE_ID_OFFSET_CFG + 2: 3462 /* 56260_2 */ 3463 /* F.XAUI F.XAUI F.XAUI N4s 2.5G B1 */ 3464 sal_memcpy(arr, 3465 &sb2_tdm_56260_B1_ref[0],sizeof(sb2_tdm_56260_B1_ref)); 3466 sb2_tdm_replace(arr,tdm_size, 22, 21, 0); 3467 sb2_tdm_replace(arr,tdm_size, 23, 21, 0); 3468 sb2_tdm_replace(arr,tdm_size, 24, 21, 0); 3469 lpbk_port_speed=2500; 3470 break; 3471 case BCM56262_DEVICE_ID_OFFSET_CFG + 1: 3472 /* 56262_1 */ 3473 /* 4x2.5G 4x2.5G - - - - - 2.5G EA 75 MHz */ 3474 sal_memcpy(arr, 3475 &sb2_tdm_56260_EA_ref[0],sizeof(sb2_tdm_56260_EA_ref)); 3476 sb2_tdm_replace(arr,tdm_size, 25, SB2_IDLE1, 0); 3477 sb2_tdm_replace(arr,tdm_size, 26, SB2_IDLE1, 0); 3478 sb2_tdm_replace(arr,tdm_size, 27, SB2_IDLE1, 0); 3479 sb2_tdm_replace(arr,tdm_size, 28, SB2_IDLE1, 0); 3480 lpbk_port_speed=2500; 3481 break; 3482 3483 case BCM56263_DEVICE_ID_OFFSET_CFG + 1: 3484 /* 56263_1 */ 3485 /* 4xGE 4xGE - - - 4xGE 4xGE 2.5G A1A 37 MHz */ 3486 sal_memcpy(arr, 3487 &sb2_tdm_56263_A1A_ref[0],sizeof(sb2_tdm_56263_A1A_ref)); 3488 sb2_tdm_replace(arr,tdm_size, 9 , 21, 0); 3489 sb2_tdm_replace(arr,tdm_size, 10, 22, 0); 3490 sb2_tdm_replace(arr,tdm_size, 11, 23, 0); 3491 sb2_tdm_replace(arr,tdm_size, 12, 24, 0); 3492 sb2_tdm_replace(arr,tdm_size, 13, 25, 0); 3493 sb2_tdm_replace(arr,tdm_size, 14, 26, 0); 3494 sb2_tdm_replace(arr,tdm_size, 15, 27, 0); 3495 sb2_tdm_replace(arr,tdm_size, 16, 28, 0); 3496 lpbk_port_speed=2500; 3497 break; 3498 case BCM56263_DEVICE_ID_OFFSET_CFG + 2: 3499 /* 56263_2 */ 3500 /* 3xGE 3xGE - - - - - 2.5G A1 24 MHz */ 3501 sal_memcpy(arr, 3502 &sb2_tdm_56263_A1_ref[0],sizeof(sb2_tdm_56263_A1_ref)); 3503 lpbk_port_speed=2500; 3504 break; 3505 3506 /* ------------------- */ 3507 /* 56233 Configuration */ 3508 /* ------------------- */ 3509 case BCM56233_DEVICE_ID_OFFSET_CFG + 1: 3510 /* 56233_1 */ 3511 /* 7xGE + 1x2.5GE - - - - - 2.5G F 75 MHz */ 3512 sal_memcpy(arr, 3513 &sb2_tdm_56233_F_ref[0],sizeof(sb2_tdm_56233_F_ref)); 3514 lpbk_port_speed=2500; 3515 break; 3516 3517 /* ------------------- */ 3518 /* 56460 Configuration */ 3519 /* ------------------- */ 3520 case BCM56460_DEVICE_ID_OFFSET_CFG + 1: 3521 /* 56460_1 */ 3522 /* 24xGE 4xHGs11 4xGE 4xGE 4xGE 4xGE 4xGE 4xGE 4xGE N4 2.5G(LPBK)*/ 3523 sal_memcpy(arr, 3524 &sb2_tdm_56460_AA_ref[0],sizeof(sb2_tdm_56460_AA_ref)); 3525 lpbk_port_speed=2500; 3526 break; 3527 case BCM56460_DEVICE_ID_OFFSET_CFG + 2: 3528 /* 56460_2 */ 3529 /* F.XAUI F.XAUI F.XAUI F.XAUI F.XAUI F.XAUI 4xGE 2.5G(LPBK) */ 3530 sal_memcpy(arr, 3531 &sb2_tdm_56460_C2_ref[0],sizeof(sb2_tdm_56460_C2_ref)); 3532 sb2_tdm_replace(arr,tdm_size, 14, 13, 0); 3533 sb2_tdm_replace(arr,tdm_size, 15, 13, 0); 3534 sb2_tdm_replace(arr,tdm_size, 16, 13, 0); 3535 lpbk_port_speed=2500; 3536 break; 3537 case BCM56460_DEVICE_ID_OFFSET_CFG + 3: 3538 /* 56460_3 */ 3539 /* 2xF.XAUI + 12xGE + 1xF.XAUI + [2xXFI + 2xGE] + LPBK-2.5G */ 3540 sal_memcpy(arr, 3541 &sb2_tdm_56460_C_ref[0],sizeof(sb2_tdm_56460_C_ref)); 3542 lpbk_port_speed=2500; 3543 break; 3544 case BCM56460_DEVICE_ID_OFFSET_CFG + 4: 3545 /* 56460_4 */ 3546 /* 3x F.XAUI + 2x1G + .. 1xF.XAUI + [2xXFI + 2x1G] + LPBK-2.5G */ 3547 sal_memcpy(arr, 3548 &sb2_tdm_56460_C1_ref[0],sizeof(sb2_tdm_56460_C1_ref)); 3549 sb2_tdm_replace(arr,tdm_size, 13, 21, 0); 3550 sb2_tdm_replace(arr,tdm_size, 14, 21, 0); 3551 sb2_tdm_replace(arr,tdm_size, 15, 21, 0); 3552 sb2_tdm_replace(arr,tdm_size, 16, 21, 0); 3553 sb2_tdm_replace(arr,tdm_size, 17, 13, 0); 3554 sb2_tdm_replace(arr,tdm_size, 18, 15, 0); 3555 lpbk_port_speed=2500; 3556 break; 3557 case BCM56460_DEVICE_ID_OFFSET_CFG + 5: 3558 /* 56460_5 */ 3559 /* F.XAUI F.XAUI F.XAUI - 4xGE F.XAUI N2 */ 3560 sal_memcpy(arr, 3561 &sb2_tdm_56460_C1_ref[0],sizeof(sb2_tdm_56460_C1_ref)); 3562 sb2_tdm_replace(arr,tdm_size, 13, 21, 0); 3563 sb2_tdm_replace(arr,tdm_size, 14, 21, 0); 3564 sb2_tdm_replace(arr,tdm_size, 15, 21, 0); 3565 sb2_tdm_replace(arr,tdm_size, 16, 21, 0); 3566 sb2_tdm_replace(arr,tdm_size, 26, 19, 0); 3567 sb2_tdm_replace(arr,tdm_size, 28, 20, 0); 3568 lpbk_port_speed=2500; 3569 break; 3570 case BCM56460_DEVICE_ID_OFFSET_CFG + 6: 3571 /* 56460_6 */ 3572 /* F.XAUI 4xGE - - 4xGE F.XAUI N4s 12.5G */ 3573 sal_memcpy(arr, 3574 &sb2_tdm_56460_D_ref[0],sizeof(sb2_tdm_56460_D_ref)); 3575 lpbk_port_speed=12500; 3576 break; 3577 case BCM56462_DEVICE_ID_OFFSET_CFG + 1: 3578 /* 56462_1 */ 3579 /* F.XAUI(1) F.XAUI(5) F.XAUI(9) 4xGE 4xGE 4xGE(13..24) F.XAUI(25) 2.5G(LPBK) */ 3580 sal_memcpy(arr, 3581 &sb2_tdm_56462_B1A_ref[0],sizeof(sb2_tdm_56462_B1A_ref)); 3582 sb2_tdm_replace(arr,tdm_size, 9, 21, 0); 3583 sb2_tdm_replace(arr,tdm_size, 10, 22, 0); 3584 sb2_tdm_replace(arr,tdm_size, 11, 23, 0); 3585 sb2_tdm_replace(arr,tdm_size, 12, 24, 0); 3586 sb2_tdm_replace(arr,tdm_size, 27, 9, 0); 3587 sb2_tdm_replace(arr,tdm_size, 26, SB2_IDLE1, 0); 3588 sb2_tdm_replace(arr,tdm_size, 28, SB2_IDLE1, 0); 3589 lpbk_port_speed=2500; 3590 break; 3591 case BCM56462_DEVICE_ID_OFFSET_CFG + 2: 3592 /* 56462_2 */ 3593 /* F.XAUI F.XAUI - 4xGE 4xGE 4xGE N4s 2.5G */ 3594 sal_memcpy(arr, 3595 &sb2_tdm_56462_B1A_ref[0],sizeof(sb2_tdm_56462_B1A_ref)); 3596 sb2_tdm_replace(arr,tdm_size, 9, 21, 0); 3597 sb2_tdm_replace(arr,tdm_size, 10, 22, 0); 3598 sb2_tdm_replace(arr,tdm_size, 11, 23, 0); 3599 sb2_tdm_replace(arr,tdm_size, 12, 24, 0); 3600 lpbk_port_speed=2500; 3601 break; 3602 3603 case BCM56463_DEVICE_ID_OFFSET_CFG + 1: 3604 /* 56463_1 */ 3605 /* 4xGE 4xGE - - - 4xGE N4s 2.5G */ 3606 sal_memcpy(arr, 3607 &sb2_tdm_56463_E_ref[0],sizeof(sb2_tdm_56463_E_ref)); 3608 sb2_tdm_replace(arr,tdm_size, 9, 21, 0); 3609 sb2_tdm_replace(arr,tdm_size, 10, 22, 0); 3610 sb2_tdm_replace(arr,tdm_size, 11, 23, 0); 3611 sb2_tdm_replace(arr,tdm_size, 12, 24, 0); 3612 lpbk_port_speed=2500; 3613 break; 3614 case BCM56463_DEVICE_ID_OFFSET_CFG + 2: 3615 /* 56463_2 */ 3616 /* 4xGE 4xGE 4xGE 4xGE 4xGE 4xGE 4x2.5G 2.5G E1 */ 3617 sal_memcpy(arr, 3618 &sb2_tdm_56463_E1_ref[0],sizeof(sb2_tdm_56463_E1_ref)); 3619 lpbk_port_speed=2500; 3620 break; 3621 case BCM56463_DEVICE_ID_OFFSET_CFG + 3: 3622 /* 56463_3 */ 3623 /* 4xGE F.XAUI - - - F.XAUI F.XAUI 2.5G E3 */ 3624 3625 sal_memcpy(arr, 3626 &sb2_tdm_56463_E3_ref[0],sizeof(sb2_tdm_56463_E3_ref)); 3627 sb2_tdm_replace(arr,tdm_size, 1, 9, 0); /* 1 to 9 */ 3628 sb2_tdm_replace(arr,tdm_size, 21, 1, 0); 3629 sb2_tdm_replace(arr,tdm_size, 22, 2, 0); 3630 sb2_tdm_replace(arr,tdm_size, 23, 3, 0); 3631 sb2_tdm_replace(arr,tdm_size, 24, 4, 0); 3632 sb2_tdm_replace(arr,tdm_size, 9, 21, 0); /* 9 to 21 */ 3633 lpbk_port_speed=2500; 3634 break; 3635 #ifdef BCM_WARM_BOOT_SUPPORT 3636 case COUNTOF(bcm56260_tdm_info) - 1: 3637 if (SOC_WARM_BOOT(unit)) { 3638 sal_memcpy(arr, 3639 &sb2_scache_tdm[0], sizeof(sb2_scache_tdm)); 3640 lpbk_port_speed=2500; 3641 break; 3642 } 3643 #endif 3644 /* Fall thru */ 3645 default: 3646 LOG_WARN(BSL_LS_SOC_COMMON, (BSL_META_U(unit, "Invalid cfg_num\n"))); 3647 return SOC_E_FAIL; 3648 } 3649 break; 3650 default: 3651 LOG_ERROR(BSL_LS_SOC_COMMON, (BSL_META_U(unit, "Invalid DevId\n"))); 3652 return SOC_E_FAIL; 3653 } 3654 3655 /* Reconfigure TDM based on portgroup settings */ 3656 loop_index = 0; 3657 while(sb2_selected_port_details[loop_index].start_port_no != 0) { 3658 block = loop_index; 3659 3660 /* Change TDM only if the portgroup has been modified */ 3661 if (sb2_selected_port_details[loop_index].port_incr == 3662 sb2_selected_port_details_orig[loop_index].port_incr) { 3663 loop_index++; 3664 continue; 3665 } 3666 3667 switch (sb2_selected_port_details[loop_index].port_incr){ 3668 case PORTGROUP_SINGLE_MODE: 3669 if(sb2_selected_port_details_orig[loop_index].port_incr != 3670 PORTGROUP_QUAD_MODE) { 3671 /* Exception for eagle port */ 3672 if ((sb2_selected_port_details[loop_index].start_port_no == 25) && 3673 (sb2_selected_port_details_orig[loop_index].port_incr == 2)) { 3674 break; 3675 } 3676 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 3677 "Setting TDM to Single Mode\n"))); 3678 for(i=1; i<SB2_MAX_PORTS_PER_BLOCK; i++) { 3679 sb2_tdm_replace(arr,tdm_size, 3680 (*sb2_block_ports[unit])[block][i], 3681 (*sb2_block_ports[unit])[block][0], 0); 3682 } 3683 } 3684 break; 3685 case PORTGROUP_DUAL_MODE: 3686 /* If original is quad mode, then we already have enough 3687 * TDM slots for dual mode as well */ 3688 if(sb2_selected_port_details_orig[loop_index].port_incr != 3689 PORTGROUP_QUAD_MODE) { 3690 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 3691 "Setting TDM to Dual Mode\n"))); 3692 /* Convert single to Quad mode and then split */ 3693 sb2_block_tdm_split(unit, arr, tdm_size, block); 3694 for(i=1; i<SB2_MAX_PORTS_PER_BLOCK; i+=2) { 3695 sb2_tdm_replace(arr,tdm_size, 3696 (*sb2_block_ports[unit])[block][i], 3697 (*sb2_block_ports[unit])[block][i-1], 0); 3698 } 3699 } 3700 break; 3701 case PORTGROUP_QUAD_MODE: 3702 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 3703 "Setting TDM to Quad Mode\n"))); 3704 /* Merge the slots and then split */ 3705 /* This will take care of dual to quad block */ 3706 for(i=1; i<SB2_MAX_PORTS_PER_BLOCK; i++) { 3707 sb2_tdm_replace(arr,tdm_size, 3708 (*sb2_block_ports[unit])[block][i], 3709 (*sb2_block_ports[unit])[block][0], 0); 3710 } 3711 sb2_block_tdm_split(unit, arr, tdm_size, block); 3712 break; 3713 default: 3714 return SOC_E_INTERNAL; 3715 } 3716 loop_index++; 3717 } 3718 3719 /* Verify the TDM structure */ 3720 kt2_tdm_display(unit,arr, tdm_size, row, col); 3721 rv = sb2_tdm_verify(unit, (uint32 *)bcm56260_tdm[cfg_num], tdm_size, 3722 tdm_freq, (uint32 *)bcm56260_speed[unit][cfg_num], 3723 lpbk_port_speed, &offender_port); 3724 if ((rv == SOC_E_CONFIG) && (offender_port == SB2_IDLE)) { 3725 rv = SOC_E_NONE; 3726 } 3727 SOC_IF_ERROR_RETURN(rv); 3728 3729 /* Disable IARB TDM before programming... */ 3730 SOC_IF_ERROR_RETURN(READ_IARB_TDM_CONTROLr(unit, &rval)); 3731 soc_reg_field_set(unit, IARB_TDM_CONTROLr, &rval, DISABLEf, 1); 3732 soc_reg_field_set(unit, IARB_TDM_CONTROLr, &rval, TDM_WRAP_PTRf, 3733 tdm_size -1); 3734 SOC_IF_ERROR_RETURN(WRITE_IARB_TDM_CONTROLr(unit, rval)); 3735 3736 for (i = 0; i < tdm_size; i++) { 3737 arr_ele = arr[i]; 3738 if (arr_ele < SB2_IDLE) { /* Non Idle Slots */ 3739 port_enable_value = 1; 3740 } else { 3741 port_enable_value = 0; 3742 } 3743 3744 sal_memset(&iarb_tdm, 0, sizeof(iarb_tdm_table_entry_t)); 3745 soc_IARB_TDM_TABLEm_field32_set(unit, &iarb_tdm, PORT_NUMf, 3746 arr_ele); 3747 SOC_IF_ERROR_RETURN(WRITE_IARB_TDM_TABLEm(unit, SOC_BLOCK_ALL, i, 3748 &iarb_tdm)); 3749 3750 if((i % 2) == 0) { 3751 /* Two entries per mem entry */ 3752 sal_memset(&lls_tdm, 0, sizeof(lls_port_tdm_entry_t)); 3753 3754 soc_LLS_PORT_TDMm_field32_set(unit, &lls_tdm, PORT_ID_0f, arr_ele); 3755 soc_LLS_PORT_TDMm_field32_set(unit, &lls_tdm, 3756 PORT_ID_0_ENABLEf, port_enable_value); 3757 } else { 3758 soc_LLS_PORT_TDMm_field32_set(unit, &lls_tdm, PORT_ID_1f, arr_ele); 3759 soc_LLS_PORT_TDMm_field32_set(unit, &lls_tdm, 3760 PORT_ID_1_ENABLEf, port_enable_value); 3761 3762 SOC_IF_ERROR_RETURN(WRITE_LLS_PORT_TDMm(unit, SOC_BLOCK_ALL, (i/2), 3763 &lls_tdm)); 3764 } 3765 } 3766 3767 if (tdm_size % 2) { 3768 LOG_DEBUG(BSL_LS_SOC_COMMON, (BSL_META_U(unit, "Info:Odd TDM Size%d \n"),tdm_size)); 3769 SOC_IF_ERROR_RETURN(WRITE_LLS_PORT_TDMm(unit, SOC_BLOCK_ALL, (i/2), 3770 &lls_tdm)); 3771 } 3772 3773 SOC_IF_ERROR_RETURN(READ_IARB_TDM_CONTROLr(unit, &rval)); 3774 soc_reg_field_set(unit, IARB_TDM_CONTROLr, &rval, DISABLEf, 0); 3775 soc_reg_field_set(unit, IARB_TDM_CONTROLr, &rval, TDM_WRAP_PTRf, 3776 tdm_size -1); 3777 soc_reg_field_set(unit, IARB_TDM_CONTROLr, &rval, IDLE_PORT_NUM_SELf, 1); 3778 SOC_IF_ERROR_RETURN(WRITE_IARB_TDM_CONTROLr(unit, rval)); 3779 3780 rval = 0; 3781 soc_reg_field_set(unit, LLS_TDM_CAL_CFGr, &rval, END_Af, tdm_size - 1); 3782 soc_reg_field_set(unit, LLS_TDM_CAL_CFGr, &rval, END_Bf, tdm_size - 1); 3783 soc_reg_field_set(unit, LLS_TDM_CAL_CFGr, &rval, ENABLEf, 1); 3784 SOC_IF_ERROR_RETURN(WRITE_LLS_TDM_CAL_CFGr(unit, rval)); 3785 3786 soc_saber2_save_tdm_pos(unit, tdm_size, arr); 3787 3788 return rv; 3789 } 3790 3791 soc_error_t soc_saber2_get_port_block( 3792 int unit, soc_port_t port,uint8 *block) 3793 { 3794 /* Return invalid port for all except physical port */ 3795 if (!((port > 0 ) && (port < 29))) { 3796 return SOC_E_PORT; 3797 } 3798 3799 *block = (*sb2_port_to_block[unit])[port - 1]; 3800 return SOC_E_NONE; 3801 } 3802 3803 soc_error_t soc_saber2_get_mxq_phy_port_mode( 3804 int unit, soc_port_t port,int speed, bcmMxqPhyPortMode_t *mode) { 3805 3806 soc_info_t *si = &SOC_INFO(unit); 3807 3808 if (!SOC_PBMP_MEMBER((PBMP_ALL(unit)), port)) { 3809 return SOC_E_PORT; 3810 } 3811 3812 if(!IS_MXQ_PORT(unit, port)){ 3813 return SOC_E_NONE; 3814 } 3815 3816 if (speed <= 2500) { 3817 *mode=bcmMxqPhyPortModeQuad; 3818 si->port_num_lanes[port] = 1; 3819 return SOC_E_NONE; 3820 } else if (speed >= 10000) { 3821 *mode=bcmMxqPhyPortModeSingle; 3822 si->port_num_lanes[port] = 4; 3823 return SOC_E_NONE; 3824 } else { 3825 LOG_WARN(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 3826 "Invalid speed for setting phy_port_mode\n"))); 3827 return SOC_E_CONFIG; 3828 } 3829 3830 } 3831 3832 soc_error_t soc_saber2_get_xl_phy_core_port_mode( 3833 int unit, soc_port_t port, 3834 bcmXlPhyPortMode_t *phy_mode, 3835 bcmXlCorePortMode_t *core_mode) { 3836 3837 uint8 block=0; 3838 uint8 loop=0; 3839 uint8 port_used[SB2_MAX_PORTS_PER_BLOCK]={0, 0, 0, 0}; 3840 uint8 num_ports=0; 3841 int cfg_num; 3842 char *intf_type = NULL; 3843 uint32 rxaui = 0; 3844 soc_port_t first_port; 3845 soc_info_t *si = &SOC_INFO(unit); 3846 3847 if (!SOC_PBMP_MEMBER((PBMP_ALL(unit)), port)) { 3848 return SOC_E_PORT; 3849 } 3850 3851 if(!IS_XL_PORT(unit, port)) { 3852 return SOC_E_NONE; 3853 } 3854 3855 SOC_IF_ERROR_RETURN(_soc_saber2_get_cfg_num(unit, &cfg_num)); 3856 if (cfg_num >= (sizeof(bcm56260_tdm)/sizeof(bcm56260_tdm[0]))) { 3857 return SOC_E_FAIL; 3858 } 3859 3860 SOC_IF_ERROR_RETURN(soc_saber2_get_port_block(unit,port,&block)); 3861 first_port = (*sb2_block_ports[unit])[block][0]; 3862 3863 for(loop=0;loop<SB2_MAX_PORTS_PER_BLOCK; loop++) { 3864 if ((bcm56260_speed[unit][cfg_num] 3865 [(block*SB2_MAX_PORTS_PER_BLOCK)+loop]) && 3866 (SOC_PBMP_MEMBER((PBMP_ALL(unit)), 3867 (block*SB2_MAX_PORTS_PER_BLOCK)+loop+1))){ 3868 port_used[loop] = 1; 3869 num_ports++; 3870 } 3871 } 3872 3873 switch(num_ports){ 3874 case 0: return SOC_E_PARAM; 3875 case 1: *phy_mode=bcmXlPhyPortModeSingle; 3876 *core_mode=bcmXlCorePortModeSingle; 3877 si->port_num_lanes[first_port] = 4; 3878 si->port_num_lanes[first_port + 1] = 0; 3879 si->port_num_lanes[first_port + 2] = 0; 3880 si->port_num_lanes[first_port + 3] = 0; 3881 break; 3882 case 2: 3883 *phy_mode=bcmXlPhyPortModeDual; 3884 *core_mode=bcmXlCorePortModeDual; 3885 intf_type= soc_property_port_get_str(unit, port, spn_SERDES_IF_TYPE); 3886 3887 if (intf_type != NULL) { 3888 if ((sal_strcmp(intf_type, "RXAUI") == 0) || 3889 (sal_strcmp(intf_type, "rxaui") == 0)) { 3890 /* mode : RXAUI */ 3891 si->port_num_lanes[first_port] = 2; 3892 si->port_num_lanes[first_port + 1] = 0; 3893 si->port_num_lanes[first_port + 2] = 2; 3894 si->port_num_lanes[first_port + 3] = 0; 3895 } else if ((sal_strcmp(intf_type, "XFI") == 0) || 3896 (sal_strcmp(intf_type, "xfi") == 0)) { 3897 /* mode : 2xXFI */ 3898 si->port_num_lanes[first_port] = 1; 3899 si->port_num_lanes[first_port + 1] = 0; 3900 si->port_num_lanes[first_port + 2] = 1; 3901 si->port_num_lanes[first_port + 3] = 0; 3902 } 3903 } 3904 3905 rxaui = soc_property_port_get(unit, port, 3906 spn_SERDES_RXAUI_MODE, 0xFF); 3907 if ((rxaui == 0) || (rxaui == 1)) { 3908 /* mode : RXAUI */ 3909 si->port_num_lanes[first_port] = 2; 3910 si->port_num_lanes[first_port + 1] = 0; 3911 si->port_num_lanes[first_port + 2] = 2; 3912 si->port_num_lanes[first_port + 3] = 0; 3913 } else { 3914 /* mode : 2xXFI */ 3915 si->port_num_lanes[first_port] = 1; 3916 si->port_num_lanes[first_port + 1] = 0; 3917 si->port_num_lanes[first_port + 2] = 1; 3918 si->port_num_lanes[first_port + 3] = 0; 3919 } 3920 break; 3921 case 3: if(port_used[0] && port_used[2] && port_used[3]) { 3922 *phy_mode = bcmXlPhyPortModeTri023; 3923 *core_mode = bcmXlCorePortModeTri023; 3924 si->port_num_lanes[first_port] = 2; 3925 si->port_num_lanes[first_port + 1] = 0; 3926 si->port_num_lanes[first_port + 2] = 1; 3927 si->port_num_lanes[first_port + 3] = 1; 3928 } else if (port_used[0] && port_used[1] && port_used[2]) { 3929 *phy_mode = bcmXlPhyPortModeTri012; 3930 *core_mode = bcmXlCorePortModeTri012; 3931 si->port_num_lanes[first_port] = 1; 3932 si->port_num_lanes[first_port + 1] = 1; 3933 si->port_num_lanes[first_port + 2] = 2; 3934 si->port_num_lanes[first_port + 3] = 0; 3935 } else { 3936 return SOC_E_PARAM; 3937 } 3938 break; 3939 case 4: *phy_mode=bcmXlPhyPortModeQuad; 3940 *core_mode=bcmXlCorePortModeQuad; 3941 si->port_num_lanes[first_port] = 1; 3942 si->port_num_lanes[first_port + 1] = 1; 3943 si->port_num_lanes[first_port + 2] = 1; 3944 si->port_num_lanes[first_port + 3] = 1; 3945 break; 3946 } 3947 3948 return SOC_E_NONE; 3949 } 3950 3951 3952 soc_error_t 3953 soc_saber2_port_init_config(int unit, int cfg_num, soc_port_t port) { 3954 uint32 rval, port_speed; 3955 bcmMxqPhyPortMode_t phy_mode = -1; 3956 bcmXlCorePortMode_t core_mode_xl = -1; 3957 bcmXlPhyPortMode_t phy_mode_xl = -1; 3958 3959 port_speed = bcm56260_speed[unit][cfg_num][port-1]; 3960 3961 if(IS_MXQ_PORT(unit, port)) { 3962 SOC_IF_ERROR_RETURN(soc_saber2_get_mxq_phy_port_mode( 3963 unit, port, port_speed, &phy_mode)); 3964 if(phy_mode == -1) { 3965 return SOC_E_FAIL; 3966 } 3967 } 3968 if (SOC_REG_PORT_VALID(unit, XPORT_MODE_REGr, port)) { 3969 SOC_IF_ERROR_RETURN(READ_XPORT_MODE_REGr(unit, port, &rval)); 3970 soc_reg_field_set(unit, XPORT_MODE_REGr, &rval, PHY_PORT_MODEf, phy_mode); 3971 if(port_speed < 10000) { 3972 soc_reg_field_set(unit, XPORT_MODE_REGr, &rval, 3973 PORT_GMII_MII_ENABLEf, 1); 3974 } else { 3975 soc_reg_field_set(unit, XPORT_MODE_REGr, &rval, 3976 PORT_GMII_MII_ENABLEf, 0); 3977 } 3978 SOC_IF_ERROR_RETURN(WRITE_XPORT_MODE_REGr(unit, port, rval)); 3979 } 3980 3981 if (SOC_REG_PORT_VALID(unit, XPORT_MIB_RESETr, port)) { 3982 SOC_IF_ERROR_RETURN(WRITE_XPORT_MIB_RESETr(unit, port, 0xf)); 3983 sal_usleep(1000); 3984 SOC_IF_ERROR_RETURN(WRITE_XPORT_MIB_RESETr(unit, port, 0x0)); 3985 } 3986 3987 if (SOC_REG_PORT_VALID(unit, XLPORT_CONFIGr, port)) { 3988 if (IS_ST_PORT(unit, port)) { 3989 SOC_IF_ERROR_RETURN(READ_XLPORT_CONFIGr(unit, port, &rval)); 3990 soc_reg_field_set(unit, XLPORT_CONFIGr, &rval, HIGIG_MODEf, 1); 3991 if ((soc_feature(unit, soc_feature_higig2)) && 3992 (soc_property_port_get(unit, port, 3993 spn_HIGIG2_HDR_MODE, 0))) { 3994 soc_reg_field_set(unit, XLPORT_CONFIGr, &rval, HIGIG2_MODEf, 1); 3995 } else { 3996 soc_reg_field_set(unit, XLPORT_CONFIGr, &rval, HIGIG2_MODEf, 0); 3997 } 3998 soc_reg_field_set(unit, XLPORT_CONFIGr, &rval, MY_MODIDf, 0); 3999 SOC_IF_ERROR_RETURN(WRITE_XLPORT_CONFIGr(unit, port, rval)); 4000 } else { 4001 SOC_IF_ERROR_RETURN(READ_XLPORT_CONFIGr(unit, port, &rval)); 4002 soc_reg_field_set(unit, XLPORT_CONFIGr, &rval, HIGIG_MODEf, 0); 4003 soc_reg_field_set(unit, XLPORT_CONFIGr, &rval, HIGIG2_MODEf, 0); 4004 soc_reg_field_set(unit, XLPORT_CONFIGr, &rval, MY_MODIDf, 0); 4005 SOC_IF_ERROR_RETURN(WRITE_XLPORT_CONFIGr(unit, port, rval)); 4006 } 4007 } 4008 4009 if (SOC_REG_PORT_VALID(unit, XLPORT_MODE_REGr, port)) { 4010 SOC_IF_ERROR_RETURN(WRITE_XLPORT_MODE_REGr(unit, port, 0)); 4011 } 4012 4013 if (SOC_REG_PORT_VALID(unit, XLPORT_SOFT_RESETr, port)) { 4014 SOC_IF_ERROR_RETURN(WRITE_XLPORT_SOFT_RESETr(unit, port, 0xF)); 4015 } 4016 4017 if(IS_XL_PORT(unit, port)) { 4018 SOC_IF_ERROR_RETURN(soc_saber2_get_xl_phy_core_port_mode(unit, port, 4019 &phy_mode_xl, &core_mode_xl)); 4020 if((phy_mode_xl == -1) || (core_mode_xl == -1)){ 4021 return SOC_E_FAIL; 4022 } 4023 } 4024 if (SOC_REG_PORT_VALID(unit, XLPORT_MODE_REGr, port)) { 4025 rval = 0; 4026 soc_reg_field_set(unit, XLPORT_MODE_REGr, &rval, 4027 EGR_1588_TIMESTAMPING_CMIC_48_ENf, 1); 4028 soc_reg_field_set(unit, XLPORT_MODE_REGr, &rval, 4029 XPORT0_CORE_PORT_MODEf,core_mode_xl); 4030 soc_reg_field_set(unit, XLPORT_MODE_REGr, &rval, 4031 XPORT0_PHY_PORT_MODEf, phy_mode_xl); 4032 SOC_IF_ERROR_RETURN(WRITE_XLPORT_MODE_REGr(unit, port, rval)); 4033 } 4034 4035 if (SOC_REG_PORT_VALID(unit, XLPORT_SOFT_RESETr, port)) { 4036 SOC_IF_ERROR_RETURN(WRITE_XLPORT_SOFT_RESETr(unit, port, 0x0)); 4037 } 4038 4039 if (SOC_REG_PORT_VALID(unit, XLPORT_MIB_RESETr, port)) { 4040 SOC_IF_ERROR_RETURN(WRITE_XLPORT_MIB_RESETr(unit, port, 0xf)); 4041 sal_usleep(1000); 4042 SOC_IF_ERROR_RETURN(WRITE_XLPORT_MIB_RESETr(unit, port, 0x0)); 4043 } 4044 4045 if (SOC_REG_PORT_VALID(unit, XLPORT_ECC_CONTROLr, port)) { 4046 rval = 0; 4047 soc_reg_field_set(unit, XLPORT_ECC_CONTROLr, &rval, 4048 MIB_TSC_MEM_ENf, 1); 4049 SOC_IF_ERROR_RETURN(WRITE_XLPORT_ECC_CONTROLr(unit, port, rval)); 4050 } 4051 4052 if (SOC_REG_PORT_VALID(unit, XLPORT_CNTMAXSIZEr, port)) { 4053 rval = 0; 4054 soc_reg_field_set(unit, XLPORT_CNTMAXSIZEr, &rval, CNTMAXSIZEf, 0x5F2); 4055 SOC_IF_ERROR_RETURN(WRITE_XLPORT_CNTMAXSIZEr(unit, port, rval)); 4056 } 4057 4058 if (SOC_REG_PORT_VALID(unit, X_GPORT_CNTMAXSIZEr, port)) { 4059 rval = 0; 4060 soc_reg_field_set(unit, X_GPORT_CNTMAXSIZEr, &rval, CNTMAXSIZEf, 0x5F2); 4061 SOC_IF_ERROR_RETURN(WRITE_X_GPORT_CNTMAXSIZEr(unit, port, rval)); 4062 } 4063 4064 if (SOC_REG_PORT_VALID(unit, XLPORT_FLOW_CONTROL_CONFIGr, port)) { 4065 /* enable flow control for port macro ports */ 4066 SOC_IF_ERROR_RETURN(READ_XLPORT_FLOW_CONTROL_CONFIGr(unit, port, &rval)); 4067 soc_reg_field_set(unit, XLPORT_FLOW_CONTROL_CONFIGr, &rval,MERGE_MODE_ENf, 1); 4068 SOC_IF_ERROR_RETURN(WRITE_XLPORT_FLOW_CONTROL_CONFIGr(unit, port, rval)); 4069 } 4070 4071 return SOC_E_NONE; 4072 } 4073 4074 soc_error_t 4075 soc_saber2_port_enable_set(int unit, soc_port_t port, int enable) 4076 { 4077 soc_field_t port_enable_field[SB2_MAX_PORTS_PER_BLOCK]= 4078 {PORT0f, PORT1f, PORT2f , PORT3f}; 4079 uint32 rval, rval_old; 4080 uint8 loop; 4081 uint32 port_enable; 4082 uint32 entry[SOC_MAX_MEM_WORDS]; 4083 4084 loop = (port-1) % 4; 4085 4086 if (SOC_REG_PORT_VALID(unit, TXLP_PORT_ENABLEr, port)) { 4087 SOC_IF_ERROR_RETURN(READ_TXLP_PORT_ENABLEr(unit, port, &rval)); 4088 rval_old = rval; 4089 port_enable = soc_reg_field_get(unit, TXLP_PORT_ENABLEr, 4090 rval, PORT_ENABLEf); 4091 port_enable |= (1 << loop); 4092 soc_reg_field_set(unit, TXLP_PORT_ENABLEr, &rval, 4093 PORT_ENABLEf,port_enable); 4094 if (rval_old != rval) { 4095 SOC_IF_ERROR_RETURN(WRITE_TXLP_PORT_ENABLEr(unit, port, rval)); 4096 } 4097 } 4098 4099 if (SOC_REG_PORT_VALID(unit, TXLP_MIN_STARTCNTr, port)) { 4100 SOC_IF_ERROR_RETURN(READ_TXLP_MIN_STARTCNTr(unit, port, &rval)); 4101 soc_reg_field_set(unit, TXLP_MIN_STARTCNTr, &rval, 4102 NLP_STARTCNTf, 3); 4103 SOC_IF_ERROR_RETURN(WRITE_TXLP_MIN_STARTCNTr(unit, port, rval)); 4104 } 4105 4106 /* Bring IECELL block out of reset. */ 4107 if (SOC_REG_PORT_VALID(unit, IECELL_CONFIGr, port)) { 4108 SOC_IF_ERROR_RETURN(READ_IECELL_CONFIGr(unit, port, &rval)); 4109 rval_old = rval; 4110 if (enable) 4111 soc_reg_field_set(unit, IECELL_CONFIGr, &rval, SOFT_RESETf, 0); 4112 else 4113 soc_reg_field_set(unit, IECELL_CONFIGr, &rval, SOFT_RESETf, 1); 4114 if (rval_old != rval) { 4115 SOC_IF_ERROR_RETURN(WRITE_IECELL_CONFIGr(unit, port, rval)); 4116 } 4117 } 4118 4119 if (SOC_REG_PORT_VALID(unit, XPORT_PORT_ENABLEr, port)) { 4120 SOC_IF_ERROR_RETURN(READ_XPORT_PORT_ENABLEr(unit, port, &rval)); 4121 rval_old = rval; 4122 if (enable) { 4123 soc_reg_field_set(unit, XPORT_PORT_ENABLEr, &rval, 4124 port_enable_field[loop], 1); 4125 } else { 4126 soc_reg_field_set(unit, XPORT_PORT_ENABLEr, &rval, 4127 port_enable_field[loop], 0); 4128 } 4129 if (rval_old != rval) { 4130 SOC_IF_ERROR_RETURN(WRITE_XPORT_PORT_ENABLEr(unit, port, rval)); 4131 } 4132 } 4133 4134 if (SOC_REG_PORT_VALID(unit, XLPORT_ENABLE_REGr, port)) { 4135 SOC_IF_ERROR_RETURN(READ_XLPORT_ENABLE_REGr(unit, port, &rval)); 4136 rval_old = rval; 4137 if (enable) { 4138 soc_reg_field_set(unit, XLPORT_ENABLE_REGr, &rval, 4139 port_enable_field[loop], 1); 4140 } else { 4141 soc_reg_field_set(unit, XLPORT_ENABLE_REGr, &rval, 4142 port_enable_field[loop], 0); 4143 } 4144 if (rval_old != rval) { 4145 SOC_IF_ERROR_RETURN(WRITE_XLPORT_ENABLE_REGr(unit, port, rval)); 4146 } 4147 } 4148 4149 sal_memset(entry, 0, sizeof(egr_enable_entry_t)); 4150 if (enable) { 4151 soc_mem_field32_set(unit, EGR_ENABLEm, entry, PRT_ENABLEf, 1); 4152 } else { 4153 soc_mem_field32_set(unit, EGR_ENABLEm, entry, PRT_ENABLEf, 0); 4154 } 4155 SOC_IF_ERROR_RETURN(WRITE_EGR_ENABLEm(unit, MEM_BLOCK_ALL, port, entry)); 4156 4157 return SOC_E_NONE; 4158 } 4159 4160 void soc_saber2_block_reset(int unit, uint8 block,int active_low) { 4161 uint32 rval; 4162 soc_field_t hot_swap_reset_fld[]={ 4163 TOP_MXQ0_HOTSWAP_RST_Lf,TOP_MXQ1_HOTSWAP_RST_Lf, 4164 TOP_MXQ2_HOTSWAP_RST_Lf,TOP_MXQ3_HOTSWAP_RST_Lf, 4165 TOP_MXQ4_HOTSWAP_RST_Lf,TOP_MXQ5_HOTSWAP_RST_Lf, 4166 TOP_PM_HOTSWAP_RST_Lf}; 4167 4168 if (READ_TOP_SOFT_RESET_REGr(unit, &rval) != SOC_E_NONE) { 4169 LOG_CLI((BSL_META_U(unit, 4170 "ATTN: Reading TOP_SOFT_RESET_REG failed \n"))); 4171 return; 4172 } 4173 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, 4174 hot_swap_reset_fld[block],active_low); 4175 WRITE_TOP_SOFT_RESET_REGr(unit, rval); 4176 4177 } 4178 4179 STATIC 4180 int _soc_saber2_mmu_config_extra_queue(int unit, uint32 queue, 4181 _soc_sb2_mmu_params_t *_soc_sb2_mmu_params, 4182 _sb2_output_port_threshold_t *output_port_threshold) 4183 { 4184 mmu_thdo_qconfig_cell_entry_t mmu_thdo_qconfig_cell_entry={{0}}; 4185 mmu_thdo_qoffset_cell_entry_t mmu_thdo_qoffset_cell_entry={{0}}; 4186 mmu_thdo_qconfig_qentry_entry_t mmu_thdo_qconfig_qentry_entry={{0}}; 4187 mmu_thdo_qoffset_qentry_entry_t mmu_thdo_qoffset_qentry_entry={{0}}; 4188 int temp_val; 4189 4190 /* 1. MMU_THDO_QCONFIG_CELL */ 4191 4192 SOC_IF_ERROR_RETURN(READ_MMU_THDO_QCONFIG_CELLm(unit, 4193 MEM_BLOCK_ANY,queue, 4194 &mmu_thdo_qconfig_cell_entry)); 4195 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, 4196 &mmu_thdo_qconfig_cell_entry, Q_MIN_CELLf, 4197 output_port_threshold->min_grntd_res_queue_cells_int_buff); 4198 4199 if (_soc_sb2_mmu_params->lossless_mode_d_c) { 4200 temp_val = output_port_threshold-> 4201 min_grntd_tot_shr_queue_cells_int_buff; 4202 } else { 4203 temp_val = _soc_sb2_mmu_params-> 4204 mmu_egr_queue_dyn_thd_param_baf_profile_lossy; 4205 } 4206 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, 4207 &mmu_thdo_qconfig_cell_entry, 4208 Q_SHARED_LIMIT_CELLf, 4209 temp_val); 4210 4211 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, 4212 &mmu_thdo_qconfig_cell_entry, 4213 Q_LIMIT_DYNAMIC_CELLf, 4214 _soc_sb2_mmu_params->lossless_mode_d_c ? 0 : 1); 4215 4216 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, 4217 &mmu_thdo_qconfig_cell_entry, 4218 Q_LIMIT_ENABLE_CELLf, 4219 _soc_sb2_mmu_params->lossless_mode_d_c ? 0 : 1); 4220 4221 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, 4222 &mmu_thdo_qconfig_cell_entry, 4223 Q_COLOR_ENABLE_CELLf,0); 4224 4225 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, 4226 &mmu_thdo_qconfig_cell_entry, 4227 Q_COLOR_LIMIT_DYNAMIC_CELLf, 4228 _soc_sb2_mmu_params->lossless_mode_d_c ? 0 : 1); 4229 4230 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, 4231 &mmu_thdo_qconfig_cell_entry, 4232 LIMIT_YELLOW_CELLf, 0); 4233 4234 SOC_IF_ERROR_RETURN(WRITE_MMU_THDO_QCONFIG_CELLm(unit, 4235 MEM_BLOCK_ANY,queue, 4236 &mmu_thdo_qconfig_cell_entry)); 4237 4238 /* 2. MMU_THDO_QOFFSET_CELL */ 4239 4240 SOC_IF_ERROR_RETURN(READ_MMU_THDO_QOFFSET_CELLm(unit, 4241 MEM_BLOCK_ANY,queue, 4242 &mmu_thdo_qoffset_cell_entry)); 4243 soc_mem_field32_set(unit, MMU_THDO_QOFFSET_CELLm, 4244 &mmu_thdo_qoffset_cell_entry, 4245 RESET_OFFSET_CELLf, 2); 4246 4247 soc_mem_field32_set(unit, MMU_THDO_QOFFSET_CELLm, 4248 &mmu_thdo_qoffset_cell_entry, 4249 LIMIT_RED_CELLf, 0); 4250 4251 soc_mem_field32_set(unit, MMU_THDO_QOFFSET_CELLm, 4252 &mmu_thdo_qoffset_cell_entry, 4253 RESET_OFFSET_YELLOW_CELLf,2); 4254 4255 soc_mem_field32_set(unit, MMU_THDO_QOFFSET_CELLm, 4256 &mmu_thdo_qoffset_cell_entry, 4257 RESET_OFFSET_RED_CELLf,2); 4258 4259 SOC_IF_ERROR_RETURN(WRITE_MMU_THDO_QOFFSET_CELLm(unit, 4260 MEM_BLOCK_ANY,queue, 4261 &mmu_thdo_qoffset_cell_entry)); 4262 4263 /* 3. MMU_THDO_QCONFIG_QENTRY */ 4264 4265 SOC_IF_ERROR_RETURN(READ_MMU_THDO_QCONFIG_QENTRYm(unit, 4266 MEM_BLOCK_ANY,queue, 4267 &mmu_thdo_qconfig_qentry_entry)); 4268 4269 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_QENTRYm, 4270 &mmu_thdo_qconfig_qentry_entry, Q_MIN_QENTRYf, 4271 output_port_threshold->min_grntd_res_queue_cells_EQEs); 4272 4273 if (_soc_sb2_mmu_params->lossless_mode_d_c) { 4274 temp_val = output_port_threshold-> 4275 min_grntd_tot_shr_queue_cells_EQEs; 4276 } else { 4277 temp_val = _soc_sb2_mmu_params-> 4278 mmu_egr_queue_dyn_thd_param_baf_profile_lossy; 4279 } 4280 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_QENTRYm, 4281 &mmu_thdo_qconfig_qentry_entry, 4282 Q_SHARED_LIMIT_QENTRYf, temp_val); 4283 4284 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_QENTRYm, 4285 &mmu_thdo_qconfig_qentry_entry, 4286 Q_LIMIT_DYNAMIC_QENTRYf, 4287 _soc_sb2_mmu_params->lossless_mode_d_c ? 0 : 1); 4288 4289 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_QENTRYm, 4290 &mmu_thdo_qconfig_qentry_entry, 4291 Q_LIMIT_ENABLE_QENTRYf, 4292 _soc_sb2_mmu_params->lossless_mode_d_c ? 0 : 1); 4293 4294 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_QENTRYm, 4295 &mmu_thdo_qconfig_qentry_entry, 4296 Q_COLOR_ENABLE_QENTRYf,0); 4297 4298 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_QENTRYm, 4299 &mmu_thdo_qconfig_qentry_entry, 4300 Q_COLOR_LIMIT_DYNAMIC_QENTRYf, 4301 _soc_sb2_mmu_params->lossless_mode_d_c ? 0 : 1); 4302 4303 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_QENTRYm, 4304 &mmu_thdo_qconfig_qentry_entry, 4305 LIMIT_YELLOW_QENTRYf, 0); 4306 4307 SOC_IF_ERROR_RETURN(WRITE_MMU_THDO_QCONFIG_QENTRYm(unit, 4308 MEM_BLOCK_ANY,queue, 4309 &mmu_thdo_qconfig_qentry_entry)); 4310 4311 /* 4. MMU_THDO_QOFFSET_QENTRY */ 4312 4313 SOC_IF_ERROR_RETURN(READ_MMU_THDO_QOFFSET_QENTRYm(unit, 4314 MEM_BLOCK_ANY,queue, 4315 &mmu_thdo_qoffset_qentry_entry)); 4316 4317 soc_mem_field32_set(unit, MMU_THDO_QOFFSET_QENTRYm, 4318 &mmu_thdo_qoffset_qentry_entry, 4319 RESET_OFFSET_QENTRYf, 1); 4320 4321 soc_mem_field32_set(unit, MMU_THDO_QOFFSET_QENTRYm, 4322 &mmu_thdo_qoffset_qentry_entry, 4323 LIMIT_RED_QENTRYf, 0); 4324 4325 soc_mem_field32_set(unit, MMU_THDO_QOFFSET_QENTRYm, 4326 &mmu_thdo_qoffset_qentry_entry, 4327 RESET_OFFSET_YELLOW_QENTRYf,1); 4328 4329 soc_mem_field32_set(unit, MMU_THDO_QOFFSET_QENTRYm, 4330 &mmu_thdo_qoffset_qentry_entry, 4331 RESET_OFFSET_RED_QENTRYf,1); 4332 4333 SOC_IF_ERROR_RETURN(WRITE_MMU_THDO_QOFFSET_QENTRYm(unit, 4334 MEM_BLOCK_ANY,queue, 4335 &mmu_thdo_qoffset_qentry_entry)); 4336 return SOC_E_NONE; 4337 } 4338 4339 /* Helper function for MMU settings based on 4340 * memory selection (internal/external/both) and mode (lossless/lossy) 4341 * The memory selection is done using config variable 'pbmp_ext_mem' 4342 * and the mode is selected based on config variable 'lossless_mode' 4343 */ 4344 STATIC 4345 int _soc_saber2_mmu_init_helper(int unit, int flex_port) 4346 { 4347 soc_info_t *si= &SOC_INFO(unit); 4348 uint16 dev_id=0; 4349 uint8 rev_id=0; 4350 uint32 ext_mem_port_count = 0; 4351 uint32 valid_port_count = 0; 4352 soc_pbmp_t pbmp_int_ge; 4353 uint32 pbmp_int_ge_count=0; 4354 soc_pbmp_t pbmp_int_hg; 4355 uint32 pbmp_int_hg_count=0; 4356 soc_pbmp_t pbmp_ext_ge; 4357 uint32 pbmp_ext_ge_count=0; 4358 soc_pbmp_t pbmp_ext_hg; 4359 uint32 pbmp_ext_hg_count=0; 4360 uint32 mmu_num_olp_port=0; 4361 soc_pbmp_t valid_port_cpu_pbmp; 4362 soc_port_t port=0; 4363 uint32 available_internal_buffer=100; 4364 uint32 reserve_internal_buffer=0; 4365 uint32 temp_val; 4366 uint32 rval=0; 4367 uint32 service_pool=0; 4368 uint32 priority_group=0; 4369 uint32 queue; 4370 uint32 op_node=0; 4371 uint32 op_node_offset=0; 4372 uint32 cos; 4373 uint32 idx, sub_port; 4374 uint32 val; 4375 int pg_min_configured = 0, pg_min = 0; 4376 char suffix; 4377 4378 /* Per Port Settings */ 4379 uint32 mem_idx=0; 4380 thdi_port_sp_config_entry_t thdi_port_sp_config={{0}}; 4381 /* 4382 (SB2_MAX_PHYSICAL_PORTS+2) * 4383 SB2_MAX_SERVICE_POOLS] = {{{0}}}; 4384 */ 4385 thdi_port_pg_config_entry_t thdi_port_pg_config={{0}}; 4386 /* 4387 (SB2_MAX_PHYSICAL_PORTS+2) * 4388 SB2_MAX_PRIORITY_GROUPS] = {{{0}}}; 4389 */ 4390 4391 thdiext_thdi_port_sp_config_entry_t thdiext_thdi_port_sp_config={{0}}; 4392 /* 4393 (SB2_MAX_PHYSICAL_PORTS+2) * 4394 SB2_MAX_SERVICE_POOLS] = {{{0}}}; 4395 */ 4396 thdiext_thdi_port_pg_config_entry_t thdiext_thdi_port_pg_config={{0}}; 4397 /* 4398 (SB2_MAX_PHYSICAL_PORTS+2) * 4399 SB2_MAX_PRIORITY_GROUPS] = {{{0}}}; 4400 */ 4401 thdiema_thdi_port_sp_config_entry_t thdiema_thdi_port_sp_config = {{0}}; 4402 /* 4403 (SB2_MAX_PHYSICAL_PORTS+2) * 4404 SB2_MAX_SERVICE_POOLS] = {{{0}}}; 4405 */ 4406 thdiema_thdi_port_pg_config_entry_t thdiema_thdi_port_pg_config={{0}}; 4407 /* 4408 (SB2_MAX_PHYSICAL_PORTS+2) * 4409 SB2_MAX_PRIORITY_GROUPS] = {{{0}}}; 4410 */ 4411 thdirqe_thdi_port_sp_config_entry_t thdirqe_thdi_port_sp_config={{0}}; 4412 /* 4413 (SB2_MAX_PHYSICAL_PORTS+2) * 4414 SB2_MAX_SERVICE_POOLS] = {{{0}}}; 4415 */ 4416 thdirqe_thdi_port_pg_config_entry_t thdirqe_thdi_port_pg_config={{0}}; 4417 /* 4418 (SB2_MAX_PHYSICAL_PORTS+2) * 4419 SB2_MAX_PRIORITY_GROUPS] = {{{0}}}; 4420 */ 4421 thdiqen_thdi_port_sp_config_entry_t thdiqen_thdi_port_sp_config = {{0}}; 4422 /* 4423 (SB2_MAX_PHYSICAL_PORTS+2) * 4424 SB2_MAX_SERVICE_POOLS] = {{{0}}}; 4425 */ 4426 thdiqen_thdi_port_pg_config_entry_t thdiqen_thdi_port_pg_config = {{0}}; 4427 /* 4428 (SB2_MAX_PHYSICAL_PORTS+2) * 4429 SB2_MAX_PRIORITY_GROUPS] = {{{0}}}; 4430 */ 4431 4432 mmu_thdo_opnconfig_cell_entry_t mmu_thdo_opnconfig_cell_entry={{0}}; 4433 mmu_thdo_qconfig_cell_entry_t mmu_thdo_qconfig_cell_entry={{0}}; 4434 mmu_thdo_qoffset_cell_entry_t mmu_thdo_qoffset_cell_entry={{0}}; 4435 4436 mmu_thdo_opnconfig_qentry_entry_t mmu_thdo_opnconfig_qentry_entry={{0}}; 4437 mmu_thdo_qconfig_qentry_entry_t mmu_thdo_qconfig_qentry_entry={{0}}; 4438 mmu_thdo_qoffset_qentry_entry_t mmu_thdo_qoffset_qentry_entry={{0}}; 4439 4440 _sb2_general_info_t *general_info = 4441 &_soc_sb2_mmu_intermediate_results.general_info; 4442 _sb2_input_port_threshold_t *input_port_threshold = 4443 &_soc_sb2_mmu_intermediate_results.input_port_threshold; 4444 _sb2_output_port_threshold_t *output_port_threshold = 4445 &_soc_sb2_mmu_intermediate_results.output_port_threshold; 4446 4447 sal_memset(&_soc_sb2_mmu_intermediate_results, 0, 4448 sizeof(_soc_sb2_mmu_intermediate_results_t)); 4449 sal_memset(&_soc_sb2_mmu_params,0,sizeof(_soc_sb2_mmu_params_t)); 4450 4451 /* Fixed Parameter */ 4452 _soc_sb2_mmu_params.mmu_min_pkt_size = 64; /*C5*/ 4453 _soc_sb2_mmu_params.mmu_ethernet_mtu_bytes=1536; /*C6*/ 4454 _soc_sb2_mmu_params.mmu_max_pkt_size = 12288; /*C7*/ 4455 _soc_sb2_mmu_params.mmu_jumbo_frame_size = 9216; /*C8*/ 4456 _soc_sb2_mmu_params.mmu_int_buf_cell_size = 190; /*C9*/ 4457 /* C10 = (C9+2)*15 */ 4458 _soc_sb2_mmu_params.mmu_ext_buf_cell_size = 4459 (_soc_sb2_mmu_params.mmu_int_buf_cell_size + 2) * 15; 4460 _soc_sb2_mmu_params.mmu_pkt_header_size = 62; /*C11*/ 4461 _soc_sb2_mmu_params.mmu_lossless_pg_num = 1; /*C16*/ 4462 _soc_sb2_mmu_params.mmu_line_rate_ge = 1; /*C20*/ 4463 _soc_sb2_mmu_params.mmu_line_rate_hg = 10; /*C26*/ 4464 _soc_sb2_mmu_params.mmu_num_cpu_port = 1; /*C31*/ 4465 _soc_sb2_mmu_params.mmu_num_cpu_queue = 48; /*C32*/ 4466 _soc_sb2_mmu_params.mmu_num_loopback_port = 1; /*C34*/ 4467 _soc_sb2_mmu_params.mmu_num_loopback_queue = 8; /*C35*/ 4468 _soc_sb2_mmu_params.mmu_num_ep_redirection_queue = 16; /*C36*/ 4469 _soc_sb2_mmu_params.mmu_num_olp_queue = 8; /*C38*/ 4470 _soc_sb2_mmu_params.mmu_pipeline_lat_cpap_admission = 30; /*C41*/ 4471 _soc_sb2_mmu_params.mmu_reserved_int_buf_cells = 42; /*C44*/ 4472 _soc_sb2_mmu_params.mmu_ext_buf_size = 180; /*C47*/ 4473 _soc_sb2_mmu_params.mmu_ep_redirect_queue_entries = 480;/*C50*/ 4474 _soc_sb2_mmu_params.mmu_repl_engine_work_queue_entries = 4; /*C52*/ 4475 _soc_sb2_mmu_params.mmu_resv_repl_engine_work_queue_entries = 292; /*C53*/ 4476 _soc_sb2_mmu_params.mmu_repl_engine_work_queue_in_device = 12; /*C54*/ 4477 _soc_sb2_mmu_params.mmu_ema_queues = 8; /*C55*/ 4478 _soc_sb2_mmu_params.mmu_ing_port_dyn_thd_param = 2; /*C60*/ 4479 _soc_sb2_mmu_params.mmu_ing_pg_dyn_thd_param = 7; /*C61*/ 4480 _soc_sb2_mmu_params.mmu_egr_queue_dyn_thd_param_baf = 2; /*C62*/ 4481 _soc_sb2_mmu_params.mmu_egr_queue_dyn_thd_param_baf_profile_lossy = 7; /*C63*/ 4482 _soc_sb2_mmu_params.mmu_ing_cell_buf_reduction = 0; /*C64*/ 4483 _soc_sb2_mmu_params.mmu_ing_pkt_buf_reduction = 0; /*C65*/ 4484 4485 SOC_PBMP_CLEAR (pbmp_int_ge); 4486 SOC_PBMP_CLEAR (pbmp_int_hg); 4487 SOC_PBMP_CLEAR (pbmp_ext_ge); 4488 SOC_PBMP_CLEAR (pbmp_ext_hg); 4489 4490 SOC_PBMP_CLEAR (valid_port_cpu_pbmp); 4491 SOC_PBMP_ASSIGN(valid_port_cpu_pbmp, PBMP_ALL(unit)); 4492 /* SOC_PBMP_PORT_ADD(valid_port_cpu_pbmp, si->cmic_port); */ 4493 4494 soc_cm_get_id(unit, &dev_id, &rev_id); 4495 /* C12 */ 4496 if (soc_feature(unit, soc_feature_mmu_packing)) { 4497 _soc_sb2_mmu_params.packing_mode_d_c = 1; 4498 } 4499 4500 /* C13 */ 4501 _soc_sb2_mmu_params.max_pkt_size_support_packing = 10; 4502 4503 /* C14 */ 4504 _soc_sb2_mmu_params.lossless_mode_d_c = (soc_property_get(unit, 4505 spn_LOSSLESS_MODE, 1) & 4506 soc_property_get(unit, 4507 spn_MMU_LOSSLESS, 1)); 4508 /* C15 */ 4509 _soc_sb2_mmu_params.pfc_pause_mode_d_c = soc_property_get(unit, 4510 "pfc_pause_mode", 0); 4511 4512 SOC_PBMP_COUNT(PBMP_PORT_ALL (unit), valid_port_count); 4513 SOC_PBMP_COUNT(PBMP_EXT_MEM (unit), ext_mem_port_count);/*spn_PBMP_EXT_MEM*/ 4514 4515 /* C17 */ 4516 if (ext_mem_port_count == 0) { 4517 _soc_sb2_mmu_params.extbuf_used_d_c = 0; 4518 if (SOC_DDR3_NUM_MEMORIES(unit)) { 4519 /* Support for dynamic addition of port to ext memory */ 4520 _soc_sb2_mmu_params.extbuf_used_d_c = 1; 4521 } 4522 } else { 4523 _soc_sb2_mmu_params.extbuf_used_d_c = 1; 4524 } 4525 4526 if (_soc_sb2_mmu_params.extbuf_used_d_c) { 4527 _soc_sb2_mmu_params.mmu_int_buf_size = 8192; /*C42*/ 4528 } else { 4529 if (soc_feature(unit, soc_feature_mmu_reduced_internal_buffer)) { 4530 _soc_sb2_mmu_params.mmu_int_buf_size = 5461; /*C42*/ 4531 } else { 4532 _soc_sb2_mmu_params.mmu_int_buf_size = 10922; /*C42*/ 4533 } 4534 } 4535 SOC_PBMP_ASSIGN(pbmp_int_ge,PBMP_GE_ALL(unit)); 4536 SOC_PBMP_ASSIGN(pbmp_int_hg,PBMP_HG_ALL(unit)); 4537 SOC_PBMP_OR(pbmp_int_hg,PBMP_XE_ALL(unit)); 4538 SOC_PBMP_ITER (PBMP_EXT_MEM (unit), port) { 4539 if (IS_GE_PORT(unit, port)) { 4540 SOC_PBMP_PORT_ADD(pbmp_ext_ge,port); 4541 SOC_PBMP_PORT_REMOVE(pbmp_int_ge,port); 4542 } 4543 if (IS_HG_PORT(unit, port) || IS_XE_PORT(unit, port)) { 4544 SOC_PBMP_PORT_ADD(pbmp_ext_hg,port); 4545 SOC_PBMP_PORT_REMOVE(pbmp_int_hg,port); 4546 } 4547 } 4548 SOC_PBMP_COUNT(pbmp_ext_ge,pbmp_ext_ge_count); 4549 SOC_PBMP_COUNT(pbmp_int_ge,pbmp_int_ge_count); 4550 SOC_PBMP_COUNT(pbmp_ext_hg,pbmp_ext_hg_count); 4551 SOC_PBMP_COUNT(pbmp_int_hg,pbmp_int_hg_count); 4552 4553 /* C19 */ 4554 _soc_sb2_mmu_params.num_ge_ports_d = pbmp_int_ge_count + pbmp_ext_ge_count; 4555 /* C21 */ 4556 _soc_sb2_mmu_params.num_ge_int_ports_d = pbmp_int_ge_count; 4557 /* C22 */ 4558 _soc_sb2_mmu_params.num_egr_queue_per_int_ge_port_d = pbmp_int_ge_count ? 8:0; 4559 /* C23 */ 4560 _soc_sb2_mmu_params.num_ge_ext_ports_d = pbmp_ext_ge_count; 4561 /* C24 */ 4562 _soc_sb2_mmu_params.num_egr_queue_per_ext_ge_port_d = pbmp_ext_ge_count ? 4563 (_soc_sb2_mmu_params.packing_mode_d_c ? 16:8):0; 4564 /* C25 */ 4565 _soc_sb2_mmu_params.num_hg_ports_d = pbmp_int_hg_count + pbmp_ext_hg_count; 4566 /* C27 */ 4567 _soc_sb2_mmu_params.num_hg_int_ports_d = pbmp_int_hg_count ; 4568 /* C28 */ 4569 _soc_sb2_mmu_params.num_egr_queue_per_int_hg_port_d = pbmp_int_hg_count ? 8:0; 4570 /* C29 */ 4571 _soc_sb2_mmu_params.num_hg_ext_ports_d = pbmp_ext_hg_count ; 4572 /* C30 */ 4573 _soc_sb2_mmu_params.num_egr_queue_per_ext_hg_port_d = pbmp_ext_hg_count ? 4574 (_soc_sb2_mmu_params.packing_mode_d_c ? 16:8):0; 4575 /* C33 */ 4576 _soc_sb2_mmu_params.cpu_port_int_ext_bounding_d_c = soc_property_get(unit, 4577 "cpu_port_bounding",0); 4578 /* C37 */ 4579 _soc_sb2_mmu_params.mmu_num_olp_port_d = mmu_num_olp_port; 4580 /* C39 */ 4581 _soc_sb2_mmu_params.olp_port_int_ext_bounding_d_c = soc_property_get(unit, 4582 "olp_port_bounding",0); 4583 /* C40 */ 4584 _soc_sb2_mmu_params.mmu_total_egress_queue = 1024; 4585 if ((_soc_sb2_mmu_params.lossless_mode_d_c)) { 4586 _soc_sb2_mmu_params.mmu_exp_num_of_repl_per_pkt = 10; 4587 } else { 4588 /* C51 = C19+C25-1 */ 4589 _soc_sb2_mmu_params.mmu_exp_num_of_repl_per_pkt = 4590 _soc_sb2_mmu_params.num_ge_ports_d + 4591 _soc_sb2_mmu_params.num_hg_ports_d - 1 ; 4592 } 4593 if (((_soc_sb2_mmu_params.extbuf_used_d_c) || 4594 (_soc_sb2_mmu_params.packing_mode_d_c)) && 4595 (_soc_sb2_mmu_params.lossless_mode_d_c)) { 4596 available_internal_buffer=60; 4597 reserve_internal_buffer=40; 4598 } else if (((_soc_sb2_mmu_params.extbuf_used_d_c) || 4599 (_soc_sb2_mmu_params.packing_mode_d_c)) && 4600 !(_soc_sb2_mmu_params.lossless_mode_d_c)) { 4601 available_internal_buffer=70; 4602 reserve_internal_buffer=30; 4603 } else { 4604 available_internal_buffer=100; 4605 reserve_internal_buffer=0; 4606 } 4607 /* C43 */ 4608 _soc_sb2_mmu_params.mmu_available_int_buf_size_d=available_internal_buffer; 4609 /* (_soc_sb2_mmu_params.mmu_int_buf_size*available_internal_buffer)/100; */ 4610 /* C45 */ 4611 _soc_sb2_mmu_params.mmu_reserved_int_buf_ema_pool_size_d= 4612 reserve_internal_buffer; 4613 /* (_soc_sb2_mmu_params.mmu_int_buf_size*reserve_internal_buffer)/100; */ 4614 4615 /* C46 */ 4616 _soc_sb2_mmu_params.internal_buffer_reduction_d_c = soc_property_get(unit, 4617 "internal_buffer_reduction",0); 4618 4619 /* C47 */ 4620 _soc_sb2_mmu_params.mmu_ext_buf_size = (64*1024*_soc_sb2_mmu_params.mmu_ext_buf_cell_size) >> 20 ; 4621 4622 /* C48 */ 4623 _soc_sb2_mmu_params.mmu_reserved_ext_buf_space_cfap = 64; 4624 4625 /* C49 */ 4626 _soc_sb2_mmu_params.mmu_egress_queue_entries = 64; 4627 4628 /* C58 = CEILING((C6*1024+C11)/C9, 1) */ 4629 _soc_sb2_mmu_params.per_cos_res_cells_for_int_buff_d = 4630 sal_ceil_func((_soc_sb2_mmu_params.mmu_ethernet_mtu_bytes + 4631 _soc_sb2_mmu_params.mmu_pkt_header_size), 4632 _soc_sb2_mmu_params.mmu_int_buf_cell_size); 4633 4634 /* C59 =IF(C12=0,CEILING(C58/15,1),CEILING((C6*1024+C11+2)/C10,1)) */ 4635 4636 if (_soc_sb2_mmu_params.packing_mode_d_c == 0) { 4637 _soc_sb2_mmu_params.per_cos_res_cells_for_ext_buff_d = 4638 sal_ceil_func(_soc_sb2_mmu_params.per_cos_res_cells_for_int_buff_d,15); 4639 } else { 4640 _soc_sb2_mmu_params.per_cos_res_cells_for_ext_buff_d = 4641 sal_ceil_func((_soc_sb2_mmu_params.mmu_ethernet_mtu_bytes + 4642 _soc_sb2_mmu_params.mmu_pkt_header_size + 2), 4643 _soc_sb2_mmu_params.mmu_ext_buf_cell_size); 4644 } 4645 4646 /* Intermediate Results Processing Now */ 4647 /* Fill up general info */ 4648 /* C72 = CEILING((C7+C11)/C9,1) */ 4649 general_info->max_packet_size_in_cells = sal_ceil_func( 4650 (_soc_sb2_mmu_params.mmu_max_pkt_size + 4651 _soc_sb2_mmu_params.mmu_pkt_header_size), 4652 _soc_sb2_mmu_params.mmu_int_buf_cell_size); 4653 /* C73 = CEILING((C8+C11)/C9,1) */ 4654 general_info->jumbo_frame_for_int_buff = sal_ceil_func( 4655 (_soc_sb2_mmu_params.mmu_jumbo_frame_size + 4656 _soc_sb2_mmu_params.mmu_pkt_header_size), 4657 _soc_sb2_mmu_params.mmu_int_buf_cell_size); 4658 /* C74 =IF(C12=0,CEILING(C73/15,1),CEILING((C8+C11+2)/C10,1)) */ 4659 if (_soc_sb2_mmu_params.packing_mode_d_c == 0) { 4660 general_info->jumbo_frame_for_ext_buff = sal_ceil_func( 4661 general_info->jumbo_frame_for_int_buff,15); 4662 } else { 4663 general_info->jumbo_frame_for_ext_buff = sal_ceil_func( 4664 _soc_sb2_mmu_params.mmu_jumbo_frame_size + 4665 _soc_sb2_mmu_params.mmu_pkt_header_size + 2, 4666 _soc_sb2_mmu_params.mmu_ext_buf_cell_size); 4667 } 4668 /* C76 = CEILING((C6*1024+C11)/C9, 1) */ 4669 general_info->ether_mtu_cells_for_int_buff = sal_ceil_func( 4670 (_soc_sb2_mmu_params.mmu_ethernet_mtu_bytes) + 4671 _soc_sb2_mmu_params.mmu_pkt_header_size, 4672 _soc_sb2_mmu_params.mmu_int_buf_cell_size); 4673 4674 /* C77 = IF(C12=0,CEILING(C76/15,1),CEILING((C6*1024+C11+2)/C10,1)) */ 4675 if (_soc_sb2_mmu_params.packing_mode_d_c == 0) { 4676 general_info->ether_mtu_cells_for_ext_buff = sal_ceil_func( 4677 general_info->ether_mtu_cells_for_int_buff,15); 4678 } else { 4679 general_info->ether_mtu_cells_for_ext_buff = sal_ceil_func( 4680 (_soc_sb2_mmu_params.mmu_ethernet_mtu_bytes)+ 4681 _soc_sb2_mmu_params.mmu_pkt_header_size+2, 4682 _soc_sb2_mmu_params.mmu_ext_buf_cell_size); 4683 } 4684 4685 /* C79 = C19+C25+C31+C34+C37 */ 4686 general_info->total_num_of_ports = 4687 _soc_sb2_mmu_params.num_ge_ports_d + 4688 _soc_sb2_mmu_params.num_hg_ports_d + 4689 _soc_sb2_mmu_params.mmu_num_cpu_port + 4690 _soc_sb2_mmu_params.mmu_num_loopback_port + 4691 _soc_sb2_mmu_params.mmu_num_olp_port_d; 4692 4693 /* C80 = C19+C25+C31+C37 ) */ 4694 general_info->total_num_of_ports_excl_lpbk = 4695 _soc_sb2_mmu_params.num_ge_ports_d + 4696 _soc_sb2_mmu_params.num_hg_ports_d + 4697 _soc_sb2_mmu_params.mmu_num_cpu_port + 4698 _soc_sb2_mmu_params.mmu_num_olp_port_d; 4699 4700 /* C81 = C19+C25+C31 */ 4701 general_info->total_num_of_ports_excl_lpbk_olp = 4702 _soc_sb2_mmu_params.num_ge_ports_d + 4703 _soc_sb2_mmu_params.num_hg_ports_d + 4704 _soc_sb2_mmu_params.mmu_num_cpu_port; 4705 4706 /* C82 = C19+C25 */ 4707 general_info->total_num_of_ports_excl_lpbk_olp_cpu = 4708 _soc_sb2_mmu_params.num_ge_ports_d + 4709 _soc_sb2_mmu_params.num_hg_ports_d; 4710 4711 /* C83 = C23*C20+C29*C26 */ 4712 general_info->port_bw_bound_to_ext_buff = 4713 (_soc_sb2_mmu_params.num_ge_ext_ports_d * 4714 _soc_sb2_mmu_params.mmu_line_rate_ge) + 4715 (_soc_sb2_mmu_params.num_hg_ext_ports_d * 4716 _soc_sb2_mmu_params.mmu_line_rate_hg) ; 4717 4718 /* C84 = C22*C21 */ 4719 general_info->total_egr_queues_for_a_int_ge_ports = 4720 (_soc_sb2_mmu_params.num_egr_queue_per_int_ge_port_d * 4721 _soc_sb2_mmu_params.num_ge_int_ports_d); 4722 4723 /* C85 = C24*C23 */ 4724 general_info->total_egr_queues_for_a_ext_ge_ports = 4725 (_soc_sb2_mmu_params.num_egr_queue_per_ext_ge_port_d * 4726 _soc_sb2_mmu_params.num_ge_ext_ports_d); 4727 4728 /* C86 = C28*C27 */ 4729 general_info->total_egr_queues_for_a_int_hg_ports = 4730 (_soc_sb2_mmu_params.num_egr_queue_per_int_hg_port_d * 4731 _soc_sb2_mmu_params.num_hg_int_ports_d); 4732 4733 /* C87 = C30*C29 */ 4734 general_info->total_egr_queues_for_a_ext_hg_ports = 4735 (_soc_sb2_mmu_params.num_egr_queue_per_ext_hg_port_d * 4736 _soc_sb2_mmu_params.num_hg_ext_ports_d); 4737 4738 /* C88 = C31*C32 */ 4739 general_info->total_cpu_queues = 4740 (_soc_sb2_mmu_params.mmu_num_cpu_port * 4741 _soc_sb2_mmu_params.mmu_num_cpu_queue); 4742 4743 /* C89 =$C$84+$C$86+IF(C33=0,C88,0)+IF(C39=0,C38*C37,0)+C34*C35+C34*C36/2 */ 4744 general_info->total_base_queue_int_buff = 4745 (general_info->total_egr_queues_for_a_int_ge_ports + 4746 general_info->total_egr_queues_for_a_int_hg_ports); 4747 if (_soc_sb2_mmu_params.cpu_port_int_ext_bounding_d_c == 0) { 4748 general_info->total_base_queue_int_buff += general_info->total_cpu_queues; 4749 } 4750 if (_soc_sb2_mmu_params.olp_port_int_ext_bounding_d_c == 0) { 4751 general_info->total_base_queue_int_buff += 4752 (_soc_sb2_mmu_params.mmu_num_olp_queue * 4753 _soc_sb2_mmu_params.mmu_num_olp_port_d); 4754 } 4755 general_info->total_base_queue_int_buff += 4756 (_soc_sb2_mmu_params.mmu_num_loopback_queue * 4757 _soc_sb2_mmu_params.mmu_num_loopback_port); 4758 general_info->total_base_queue_int_buff += 4759 ((_soc_sb2_mmu_params.mmu_num_ep_redirection_queue * 4760 _soc_sb2_mmu_params.mmu_num_loopback_port)/ 2); 4761 4762 /* C90 = =$C$85+$C$87+IF(C33=1,C88,0)+IF(C39=1,C37*C38,0)+IF(C17=1,C34*C36/2,0) */ 4763 general_info->total_base_queue_ext_buff = 4764 (general_info->total_egr_queues_for_a_ext_ge_ports + 4765 general_info->total_egr_queues_for_a_ext_hg_ports); 4766 if (_soc_sb2_mmu_params.cpu_port_int_ext_bounding_d_c) { 4767 general_info->total_base_queue_ext_buff += general_info->total_cpu_queues; 4768 } 4769 if (_soc_sb2_mmu_params.olp_port_int_ext_bounding_d_c) { 4770 general_info->total_base_queue_ext_buff += 4771 (_soc_sb2_mmu_params.mmu_num_olp_queue * 4772 _soc_sb2_mmu_params.mmu_num_olp_port_d); 4773 } 4774 if (_soc_sb2_mmu_params.extbuf_used_d_c) { 4775 general_info->total_base_queue_ext_buff += 4776 ((_soc_sb2_mmu_params.mmu_num_loopback_port * 4777 _soc_sb2_mmu_params.mmu_num_ep_redirection_queue)/2); 4778 } 4779 4780 /* C56 =IF(C12=0, 0, 2*C40) */ 4781 if (_soc_sb2_mmu_params.packing_mode_d_c) { 4782 _soc_sb2_mmu_params.num_cells_rsrvd_ing_ext_buf = 4783 _soc_sb2_mmu_params.mmu_total_egress_queue * 2; 4784 } 4785 4786 /* C91 = C55 */ 4787 general_info->total_ema_queues = _soc_sb2_mmu_params.mmu_ema_queues; 4788 4789 /* C93 = C89+C90 */ 4790 general_info->total_egr_base_queues_in_device = 4791 general_info->total_base_queue_int_buff + 4792 general_info->total_base_queue_ext_buff; 4793 /* C94 = C40 */ 4794 general_info->total_egr_queues_in_device = 4795 _soc_sb2_mmu_params.mmu_total_egress_queue ; 4796 4797 /* C95 = C42-C44*/ 4798 general_info->max_int_cell_buff_size = 4799 _soc_sb2_mmu_params.mmu_int_buf_size - 4800 _soc_sb2_mmu_params.mmu_reserved_int_buf_cells ; 4801 4802 /* C96 = C95 */ 4803 general_info->int_cell_buff_size_after_limitation = 4804 general_info->max_int_cell_buff_size; 4805 4806 /* C97 =IF(C12=0, 0, C79*C13) */ 4807 if (_soc_sb2_mmu_params.packing_mode_d_c) { 4808 general_info->src_packing_fifo = general_info->total_num_of_ports * 4809 _soc_sb2_mmu_params.max_pkt_size_support_packing; 4810 } 4811 4812 /* C98 =FLOOR($C$43 *( IF($C$46, $C$96, $C$95)) - C41 - C97, 1) */ 4813 if (_soc_sb2_mmu_params.internal_buffer_reduction_d_c) { 4814 temp_val = general_info->int_cell_buff_size_after_limitation; 4815 } else { 4816 temp_val = general_info->max_int_cell_buff_size; 4817 } 4818 temp_val = (_soc_sb2_mmu_params.mmu_available_int_buf_size_d * temp_val)/100; 4819 temp_val -= _soc_sb2_mmu_params.mmu_pipeline_lat_cpap_admission; 4820 temp_val -= general_info->src_packing_fifo; 4821 general_info->int_buff_pool = temp_val; 4822 4823 /* C99 =IF(C17=1,FLOOR($C$45*(IF($C$46,$C$96,$C$95))-C41,1),0) */ 4824 if (_soc_sb2_mmu_params.internal_buffer_reduction_d_c) { 4825 temp_val = general_info->int_cell_buff_size_after_limitation; 4826 } else { 4827 temp_val = general_info->max_int_cell_buff_size;; 4828 } 4829 temp_val = (temp_val * _soc_sb2_mmu_params.mmu_reserved_int_buf_ema_pool_size_d)/100; 4830 temp_val = temp_val - _soc_sb2_mmu_params.mmu_pipeline_lat_cpap_admission; 4831 if (_soc_sb2_mmu_params.extbuf_used_d_c) { 4832 general_info->ema_pool = temp_val; 4833 } 4834 4835 /* C100 =IF($C$17,$C$47*1024*1024/$C$10-C48-C41,0) */ 4836 if (_soc_sb2_mmu_params.extbuf_used_d_c) { 4837 general_info->max_ext_cell_buff_size = 4838 ((_soc_sb2_mmu_params.mmu_ext_buf_size*1024*1024)/ 4839 (_soc_sb2_mmu_params.mmu_ext_buf_cell_size)) - 4840 _soc_sb2_mmu_params.mmu_reserved_ext_buf_space_cfap - 4841 _soc_sb2_mmu_params.mmu_pipeline_lat_cpap_admission; 4842 } 4843 /* C101 =C52*1024-C53*/ 4844 general_info->repl_engine_work_queue_entries = 4845 _soc_sb2_mmu_params.mmu_repl_engine_work_queue_entries*1024 - 4846 _soc_sb2_mmu_params.mmu_resv_repl_engine_work_queue_entries; 4847 4848 /* C103 = $C$10/($C$9+2) */ 4849 general_info->ratio_of_ext_buff_to_int_buff_size = 4850 _soc_sb2_mmu_params.mmu_ext_buf_cell_size / 4851 (_soc_sb2_mmu_params.mmu_int_buf_cell_size + 2); 4852 4853 /* C104 = 1 */ 4854 general_info->int_buff_cells_per_avg_size_pkt = 1; 4855 4856 /* C105 = 1 */ 4857 general_info->ext_buff_cells_per_avg_size_pkt = 1; 4858 4859 /* C106 = 0.75 but normalized to 1 */ 4860 general_info->max_prop_of_buff_used_by_one_queue_port = 75; 4861 4862 4863 /* Fill up input threshold info */ 4864 /* C110 =CEILING(C7*2/C9, 1) */ 4865 input_port_threshold->global_hdrm_cells_for_int_buff_ingress_pool = sal_ceil_func 4866 (_soc_sb2_mmu_params.mmu_max_pkt_size * 2 , 4867 _soc_sb2_mmu_params.mmu_int_buf_cell_size); 4868 4869 /* C111 =IF(C17=1, C110, 0) */ 4870 if (_soc_sb2_mmu_params.extbuf_used_d_c) { 4871 input_port_threshold->global_hdrm_cells_for_int_buff_ema_pool 4872 = input_port_threshold->global_hdrm_cells_for_int_buff_ingress_pool ; 4873 } 4874 /* C112 =CEILING(IF($C$17, IF(C12=1, 0, $C$110/$C$103), 0), 1) */ 4875 if ( _soc_sb2_mmu_params.extbuf_used_d_c && 4876 (_soc_sb2_mmu_params.packing_mode_d_c == 0)) { 4877 input_port_threshold->global_hdrm_cells_for_ext_buff_pool = sal_ceil_func( 4878 input_port_threshold->global_hdrm_cells_for_int_buff_ingress_pool, 4879 general_info->ratio_of_ext_buff_to_int_buff_size); 4880 } 4881 /* C113 */ 4882 input_port_threshold->global_hdrm_cells_for_RE_WQEs = 0 ; 4883 /* C114 */ 4884 input_port_threshold->global_hdrm_cells_for_EQEs = 0 ; 4885 if (_soc_sb2_mmu_params.lossless_mode_d_c) { 4886 if (_soc_sb2_mmu_params.extbuf_used_d_c) { 4887 /* C115 =IF(C14=0, 0, IF(C17=0, 180, 76))*/ 4888 input_port_threshold->hdrm_int_buff_cells_for_10G_PG = 76; 4889 /* C116 =IF(C14=0,0,IF(C17=0,0,76))*/ 4890 input_port_threshold->hdrm_ema_buff_cells_for_10G_PG = 76; 4891 /* C117 =IF(C14=0,0,IF(C17=0,0,67))*/ 4892 input_port_threshold->hdrm_ext_buff_cells_for_10G_PG = 67; 4893 /* C118 =IF(C14=0, 0, IF(C17=0, 49, 21))*/ 4894 input_port_threshold->hdrm_RE_WQEs_pkts_for_10G_PG = 21; 4895 } else { 4896 /* C115*/ 4897 input_port_threshold->hdrm_int_buff_cells_for_10G_PG = 180; 4898 /* C116*/ 4899 input_port_threshold->hdrm_ema_buff_cells_for_10G_PG = 0; 4900 /* C117*/ 4901 input_port_threshold->hdrm_ext_buff_cells_for_10G_PG = 0; 4902 /* C118*/ 4903 input_port_threshold->hdrm_RE_WQEs_pkts_for_10G_PG = 49; 4904 } 4905 /* C119 =IF(C14=0, 0, C118*C51)*/ 4906 input_port_threshold->hdrm_EQEs_pkts_for_10G_PG = 4907 input_port_threshold->hdrm_RE_WQEs_pkts_for_10G_PG * 4908 _soc_sb2_mmu_params.mmu_exp_num_of_repl_per_pkt ; 4909 } else { 4910 /* C115*/ 4911 input_port_threshold->hdrm_int_buff_cells_for_10G_PG = 0; 4912 /* C116*/ 4913 input_port_threshold->hdrm_ema_buff_cells_for_10G_PG = 0; 4914 /* C117*/ 4915 input_port_threshold->hdrm_ext_buff_cells_for_10G_PG = 0; 4916 /* C118*/ 4917 input_port_threshold->hdrm_RE_WQEs_pkts_for_10G_PG = 0; 4918 /* C119*/ 4919 input_port_threshold->hdrm_EQEs_pkts_for_10G_PG = 0; 4920 } 4921 4922 /* C120 = =C25*C16*$C$115 */ 4923 input_port_threshold->hdrm_int_buff_cells_for_10G_total_PG = 4924 (_soc_sb2_mmu_params.num_hg_ports_d * 4925 _soc_sb2_mmu_params.mmu_lossless_pg_num * 4926 input_port_threshold->hdrm_int_buff_cells_for_10G_PG); 4927 4928 /* C121 = C25*C16*C116 */ 4929 input_port_threshold->hdrm_ema_buff_cells_for_10G_total_PG = 4930 (_soc_sb2_mmu_params.num_hg_ports_d * 4931 _soc_sb2_mmu_params.mmu_lossless_pg_num * 4932 input_port_threshold->hdrm_ema_buff_cells_for_10G_PG); 4933 4934 /* C122 = C25*C16*C117 */ 4935 input_port_threshold->hdrm_ext_buff_cells_for_10G_total_PG = 4936 (_soc_sb2_mmu_params.num_hg_ports_d * 4937 _soc_sb2_mmu_params.mmu_lossless_pg_num * 4938 input_port_threshold->hdrm_ext_buff_cells_for_10G_PG); 4939 4940 4941 /* C123 = C25*C16*C118 */ 4942 input_port_threshold->hdrm_RE_WQEs_pkts_for_10G_total_PG = 4943 (_soc_sb2_mmu_params.num_hg_ports_d * 4944 _soc_sb2_mmu_params.mmu_lossless_pg_num * 4945 input_port_threshold->hdrm_RE_WQEs_pkts_for_10G_PG); 4946 4947 /* C124 = C25*C16*C119 */ 4948 input_port_threshold->hdrm_EQEs_pkts_for_10G_total_PG = 4949 (_soc_sb2_mmu_params.num_hg_ports_d * 4950 _soc_sb2_mmu_params.mmu_lossless_pg_num * 4951 input_port_threshold->hdrm_EQEs_pkts_for_10G_PG); 4952 4953 if (_soc_sb2_mmu_params.lossless_mode_d_c) { 4954 if (_soc_sb2_mmu_params.extbuf_used_d_c) { 4955 /* C125 */ 4956 input_port_threshold->hdrm_int_buff_cells_for_1G_PG = 26; 4957 /* C126 */ 4958 input_port_threshold->hdrm_ema_buff_cells_for_1G_PG = 26; 4959 /* C127 */ 4960 input_port_threshold->hdrm_ext_buff_cells_for_1G_PG = 23; 4961 /* C128*/ 4962 input_port_threshold->hdrm_RE_WQEs_pkts_for_1G_PG = 7; 4963 } else { 4964 /* C125 */ 4965 input_port_threshold->hdrm_int_buff_cells_for_1G_PG = 130; 4966 /* C126 */ 4967 input_port_threshold->hdrm_ema_buff_cells_for_1G_PG = 0; 4968 /* C127 */ 4969 input_port_threshold->hdrm_ext_buff_cells_for_1G_PG = 0; 4970 /* C128*/ 4971 input_port_threshold->hdrm_RE_WQEs_pkts_for_1G_PG = 35; 4972 } 4973 /* C129 =IF(C14=0, 0, C128*C51) */ 4974 input_port_threshold->hdrm_EQEs_pkts_for_1G_PG = 4975 input_port_threshold->hdrm_RE_WQEs_pkts_for_1G_PG * 4976 _soc_sb2_mmu_params.mmu_exp_num_of_repl_per_pkt; 4977 } else { 4978 /* C125 */ 4979 input_port_threshold->hdrm_int_buff_cells_for_1G_PG = 0; 4980 /* C126 */ 4981 input_port_threshold->hdrm_ema_buff_cells_for_1G_PG = 0; 4982 /* C127 */ 4983 input_port_threshold->hdrm_ext_buff_cells_for_1G_PG = 0; 4984 /* C128*/ 4985 input_port_threshold->hdrm_RE_WQEs_pkts_for_1G_PG = 0; 4986 /* C129*/ 4987 input_port_threshold->hdrm_EQEs_pkts_for_1G_PG = 0; 4988 } 4989 4990 /* C130 =C19*C16*$C$125 */ 4991 input_port_threshold->hdrm_int_buff_cells_for_1G_total_PG = 4992 (_soc_sb2_mmu_params.num_ge_ports_d * 4993 _soc_sb2_mmu_params.mmu_lossless_pg_num * 4994 input_port_threshold->hdrm_int_buff_cells_for_1G_PG); 4995 4996 /* C131 = C19*C16*$C$126 */ 4997 input_port_threshold->hdrm_ema_buff_cells_for_1G_total_PG = 4998 (_soc_sb2_mmu_params.num_ge_ports_d * 4999 _soc_sb2_mmu_params.mmu_lossless_pg_num * 5000 input_port_threshold->hdrm_ema_buff_cells_for_1G_PG); 5001 5002 /* C132 = C19*C16*$C$127 */ 5003 input_port_threshold->hdrm_ext_buff_cells_for_1G_total_PG = 5004 (_soc_sb2_mmu_params.num_ge_ports_d * 5005 _soc_sb2_mmu_params.mmu_lossless_pg_num * 5006 input_port_threshold->hdrm_ext_buff_cells_for_1G_PG); 5007 5008 /* C133 = C19*C16*$C$128 */ 5009 input_port_threshold->hdrm_RE_WQEs_pkts_for_1G_total_PG = 5010 (_soc_sb2_mmu_params.num_ge_ports_d * 5011 _soc_sb2_mmu_params.mmu_lossless_pg_num * 5012 input_port_threshold->hdrm_RE_WQEs_pkts_for_1G_PG); 5013 5014 /* C134 = C19*C16*$C$129 */ 5015 input_port_threshold->hdrm_EQEs_pkts_for_1G_total_PG = 5016 (_soc_sb2_mmu_params.num_ge_ports_d * 5017 _soc_sb2_mmu_params.mmu_lossless_pg_num * 5018 input_port_threshold->hdrm_EQEs_pkts_for_1G_PG); 5019 5020 /* C132-C135 values are zero for lossy mode */ 5021 if (_soc_sb2_mmu_params.lossless_mode_d_c) { 5022 if (_soc_sb2_mmu_params.extbuf_used_d_c) { 5023 /* C135 */ 5024 input_port_threshold->hdrm_int_buff_cells_for_olp_port = 76; 5025 /* C136 */ 5026 input_port_threshold->hdrm_ema_buff_cells_for_olp_port = 76; 5027 /* C137 */ 5028 input_port_threshold->hdrm_ext_buff_cells_for_olp_port = 67; 5029 /* C138 */ 5030 input_port_threshold->hdrm_RE_WQEs_pkts_for_olp_port = 7; 5031 } else { 5032 /* C135 */ 5033 input_port_threshold->hdrm_int_buff_cells_for_olp_port = 180; 5034 /* C136 */ 5035 input_port_threshold->hdrm_ema_buff_cells_for_olp_port = 0; 5036 /* C137 */ 5037 input_port_threshold->hdrm_ext_buff_cells_for_olp_port = 0; 5038 /* C138 */ 5039 input_port_threshold->hdrm_RE_WQEs_pkts_for_olp_port = 35; 5040 } 5041 /* C139 = C138*C51 */ 5042 input_port_threshold->hdrm_EQEs_pkts_for_olp_port = 5043 input_port_threshold->hdrm_RE_WQEs_pkts_for_olp_port * 5044 _soc_sb2_mmu_params.mmu_exp_num_of_repl_per_pkt; 5045 } else { 5046 /* C135 */ 5047 input_port_threshold->hdrm_int_buff_cells_for_olp_port = 0; 5048 /* C136 */ 5049 input_port_threshold->hdrm_int_buff_cells_for_olp_port = 0; 5050 /* C137 */ 5051 input_port_threshold->hdrm_ext_buff_cells_for_olp_port = 0; 5052 /* C138 */ 5053 input_port_threshold->hdrm_RE_WQEs_pkts_for_olp_port = 0; 5054 /* C139 */ 5055 input_port_threshold->hdrm_EQEs_pkts_for_olp_port = 0; 5056 } 5057 5058 /* C140 = 46 */ 5059 input_port_threshold->hdrm_int_buff_cells_for_lpbk_port = 46; 5060 5061 /* C141 = 46 for external buffer */ 5062 /* C142 = 40 for external buffer */ 5063 if (_soc_sb2_mmu_params.extbuf_used_d_c) { 5064 input_port_threshold->hdrm_ema_buff_cells_for_lpbk_port = 46; 5065 input_port_threshold->hdrm_ext_buff_cells_for_lpbk_port = 40; 5066 } 5067 5068 /* C143 = =IF(C14=0, 40, 18) */ 5069 if (_soc_sb2_mmu_params.lossless_mode_d_c) { 5070 input_port_threshold->hdrm_RE_WQEs_pkts_for_lpbk_port = 18; 5071 } else { 5072 input_port_threshold->hdrm_RE_WQEs_pkts_for_lpbk_port = 40; 5073 } 5074 /* C144 = C143*C51 */ 5075 input_port_threshold->hdrm_EQEs_pkts_for_lpbk_port = 5076 input_port_threshold->hdrm_RE_WQEs_pkts_for_lpbk_port * 5077 _soc_sb2_mmu_params.mmu_exp_num_of_repl_per_pkt; 5078 5079 /* C145 = 46 */ 5080 input_port_threshold->hdrm_int_buff_cells_for_cpu_port = 46; 5081 /* C146 = =IF(C17=1,46,0) */ 5082 /* C147 = 17=1,40,0) */ 5083 if (_soc_sb2_mmu_params.extbuf_used_d_c) { 5084 input_port_threshold->hdrm_ema_buff_cells_for_cpu_port = 46; 5085 input_port_threshold->hdrm_ext_buff_cells_for_cpu_port = 40; 5086 } 5087 5088 /* C148 =IF(C14=0, 40, 18) */ 5089 if (_soc_sb2_mmu_params.lossless_mode_d_c) { 5090 input_port_threshold->hdrm_RE_WQEs_pkts_for_cpu_port = 18; 5091 } else { 5092 input_port_threshold->hdrm_RE_WQEs_pkts_for_cpu_port = 40; 5093 } 5094 5095 /* C149 = C148*C51 */ 5096 input_port_threshold->hdrm_EQEs_pkts_for_cpu_port = 5097 input_port_threshold->hdrm_RE_WQEs_pkts_for_cpu_port * 5098 _soc_sb2_mmu_params.mmu_exp_num_of_repl_per_pkt; 5099 5100 /* C150 =$C$110+$C$120+$C$130+C135+C140+C145*/ 5101 input_port_threshold->total_hdrm_int_buff_cells = 5102 input_port_threshold->global_hdrm_cells_for_int_buff_ingress_pool + 5103 input_port_threshold->hdrm_int_buff_cells_for_10G_total_PG + 5104 input_port_threshold->hdrm_int_buff_cells_for_1G_total_PG + 5105 input_port_threshold->hdrm_int_buff_cells_for_olp_port + 5106 input_port_threshold->hdrm_int_buff_cells_for_lpbk_port + 5107 input_port_threshold->hdrm_int_buff_cells_for_cpu_port; 5108 5109 /* C151 = =C111+C121+C131+C136+C141+C146*/ 5110 input_port_threshold->total_hdrm_int_buff_ema_pool_cells = 5111 input_port_threshold->global_hdrm_cells_for_int_buff_ema_pool + 5112 input_port_threshold->hdrm_ema_buff_cells_for_10G_total_PG + 5113 input_port_threshold->hdrm_ema_buff_cells_for_1G_total_PG + 5114 input_port_threshold->hdrm_ema_buff_cells_for_olp_port + 5115 input_port_threshold->hdrm_ema_buff_cells_for_lpbk_port + 5116 input_port_threshold->hdrm_ema_buff_cells_for_cpu_port; 5117 5118 /* C152 =$C$112+$C$122+$C$132++C137+C142+C147*/ 5119 input_port_threshold->total_hdrm_ext_buff_cells = 5120 input_port_threshold->global_hdrm_cells_for_ext_buff_pool+ 5121 input_port_threshold->hdrm_ext_buff_cells_for_10G_total_PG+ 5122 input_port_threshold->hdrm_ext_buff_cells_for_1G_total_PG+ 5123 input_port_threshold->hdrm_ext_buff_cells_for_olp_port+ 5124 input_port_threshold->hdrm_ext_buff_cells_for_lpbk_port+ 5125 input_port_threshold->hdrm_ext_buff_cells_for_cpu_port; 5126 5127 /* C153 = =$C$113+$C$123+$C$133+C138+C143+C148 */ 5128 input_port_threshold->total_hdrm_RE_WQEs_pkts = 5129 input_port_threshold->global_hdrm_cells_for_RE_WQEs+ 5130 input_port_threshold->hdrm_RE_WQEs_pkts_for_10G_total_PG+ 5131 input_port_threshold->hdrm_RE_WQEs_pkts_for_1G_total_PG+ 5132 input_port_threshold->hdrm_RE_WQEs_pkts_for_olp_port+ 5133 input_port_threshold->hdrm_RE_WQEs_pkts_for_lpbk_port+ 5134 input_port_threshold->hdrm_RE_WQEs_pkts_for_cpu_port; 5135 5136 /* C154 =$C$114+$C$124+$C$134+C139+C144+C149*/ 5137 input_port_threshold->total_hdrm_EQEs_pkts = 5138 input_port_threshold->global_hdrm_cells_for_EQEs+ 5139 input_port_threshold->hdrm_EQEs_pkts_for_10G_total_PG+ 5140 input_port_threshold->hdrm_EQEs_pkts_for_1G_total_PG+ 5141 input_port_threshold->hdrm_EQEs_pkts_for_olp_port+ 5142 input_port_threshold->hdrm_EQEs_pkts_for_lpbk_port+ 5143 input_port_threshold->hdrm_EQEs_pkts_for_cpu_port; 5144 5145 /* C156 = $C$73 */ 5146 5147 /* In lossy mode allow configuration of PG min to zero */ 5148 if (soc_property_get(unit, spn_MMU_CONFIG_OVERRIDE, 1) == 0) { 5149 if (_soc_sb2_mmu_params.lossless_mode_d_c == 0) { 5150 PBMP_ALL_ITER(unit, port) { 5151 for (idx = 0; idx < SB2_MAX_PRIORITY_GROUPS; idx++) { 5152 pg_min = soc_property_port_obj_attr_get 5153 (unit, port, spn_BUF, spn_PRIGROUP, 5154 idx, spn_GUARANTEE, 0, &suffix, -1); 5155 if ((pg_min_configured == 0) && (pg_min != -1)) { 5156 pg_min_configured = 1; 5157 } 5158 if (pg_min_configured && pg_min) { 5159 /* Not allow non-zero pg min configuration */ 5160 LOG_ERROR(BSL_LS_BCM_COSQ, 5161 (BSL_META_U(unit, 5162 "PG MIN configuration %d for port %d and PG %d" 5163 " is not allowed.\n"), pg_min, port, idx)); 5164 return SOC_E_CONFIG; 5165 } 5166 } 5167 } 5168 } 5169 } 5170 pg_min = pg_min_configured ? pg_min : general_info->jumbo_frame_for_int_buff; 5171 input_port_threshold->min_int_buff_cells_per_PG = pg_min; 5172 5173 /* C157 = IF($C$17, $C$156, 0) */ 5174 if (_soc_sb2_mmu_params.extbuf_used_d_c) { 5175 input_port_threshold->min_int_buff_ema_pool_cells_per_PG = 5176 input_port_threshold->min_int_buff_cells_per_PG; 5177 } 5178 5179 /* C158 =IF( $C$17,C74, 0) */ 5180 if (_soc_sb2_mmu_params.extbuf_used_d_c) { 5181 input_port_threshold->min_ext_buff_cells_per_PG = 5182 general_info->jumbo_frame_for_ext_buff; 5183 } 5184 5185 /* C159 */ 5186 input_port_threshold->min_RE_WQEs_pkt_per_PG = 9; 5187 5188 /* C160 = =$C$156/$C$104*C51 */ 5189 input_port_threshold->min_EQEs_pkt_per_PG = 5190 (input_port_threshold->min_int_buff_cells_per_PG/ 5191 general_info->int_buff_cells_per_avg_size_pkt) * 5192 _soc_sb2_mmu_params.mmu_exp_num_of_repl_per_pkt; 5193 5194 /* C162 = =C79*C16*$C$156 */ 5195 input_port_threshold->min_int_buff_cells_for_total_PG = 5196 (general_info->total_num_of_ports * 5197 _soc_sb2_mmu_params.mmu_lossless_pg_num * 5198 input_port_threshold->min_int_buff_cells_per_PG) ; 5199 5200 /* C163 = =C79*C16*$C$157 */ 5201 input_port_threshold->min_int_buff_ema_pool_cells_for_total_PG = 5202 (general_info->total_num_of_ports * 5203 _soc_sb2_mmu_params.mmu_lossless_pg_num * 5204 input_port_threshold->min_int_buff_ema_pool_cells_per_PG); 5205 5206 /* C164 = =C79*C16*$C$158 */ 5207 input_port_threshold->min_ext_buff_cells_for_total_PG = 5208 (general_info->total_num_of_ports * 5209 _soc_sb2_mmu_params.mmu_lossless_pg_num * 5210 input_port_threshold->min_ext_buff_cells_per_PG); 5211 5212 /* C165 = C75*C16*$C$159 */ 5213 input_port_threshold->min_RE_WQEs_pkts_for_total_PG = 5214 (general_info->total_num_of_ports * 5215 _soc_sb2_mmu_params.mmu_lossless_pg_num * 5216 input_port_threshold->min_RE_WQEs_pkt_per_PG) ; 5217 5218 /* C166 = C75*C16*$C$160 */ 5219 input_port_threshold->min_EQEs_pkts_for_total_PG = 5220 (general_info->total_num_of_ports * 5221 _soc_sb2_mmu_params.mmu_lossless_pg_num * 5222 input_port_threshold->min_EQEs_pkt_per_PG) ; 5223 5224 /* C168 C169 C170 C171 C172= 0 */ 5225 input_port_threshold->min_int_buff_cells_for_a_port = 0; 5226 input_port_threshold->min_int_buff_ema_pool_cells_for_a_port = 0; 5227 input_port_threshold->min_ext_buff_cells_for_a_port = 0; 5228 input_port_threshold->min_RE_WQEs_pkts_for_a_port = 0; 5229 input_port_threshold->min_EQEs_pkts_for_a_port = 0; 5230 5231 /* C174 =$C$79*$C$168 */ 5232 input_port_threshold->min_int_buff_cells_for_total_port = 5233 (general_info->total_num_of_ports * 5234 input_port_threshold->min_int_buff_cells_for_a_port); 5235 5236 /* C175 = $C$75*$C$169 */ 5237 input_port_threshold->min_int_buff_ema_pool_cells_for_total_port = 5238 (general_info->total_num_of_ports * 5239 input_port_threshold->min_int_buff_ema_pool_cells_for_a_port); 5240 5241 /* C176 = $C$75*$C$170 */ 5242 input_port_threshold->min_ext_buff_cells_for_total_port = 5243 (general_info->total_num_of_ports * 5244 input_port_threshold->min_ext_buff_cells_for_a_port); 5245 5246 /* C177 = $C$75*$C$171 */ 5247 input_port_threshold->min_RE_WQEs_pkts_for_total_port = 5248 (general_info->total_num_of_ports * 5249 input_port_threshold->min_RE_WQEs_pkts_for_a_port); 5250 5251 /* C179 = $C$75*$C$172 */ 5252 input_port_threshold->min_EQEs_pkts_for_total_port = 5253 (general_info->total_num_of_ports * 5254 input_port_threshold->min_EQEs_pkts_for_a_port); 5255 5256 /* C180 =$C$162+$C$174 */ 5257 input_port_threshold->total_min_int_buff_cells = 5258 input_port_threshold->min_int_buff_cells_for_total_PG + 5259 input_port_threshold->min_int_buff_cells_for_total_port; 5260 5261 /* C181 = $C$163+$C$175 */ 5262 input_port_threshold->total_min_int_buff_ema_pool_cells = 5263 input_port_threshold->min_int_buff_ema_pool_cells_for_total_PG + 5264 input_port_threshold->min_int_buff_ema_pool_cells_for_total_port; 5265 5266 /* C182 = $C$164+$C$176 */ 5267 input_port_threshold->total_min_ext_buff_cells = 5268 input_port_threshold->min_ext_buff_cells_for_total_PG + 5269 input_port_threshold->min_ext_buff_cells_for_total_port; 5270 5271 /* C183 = $C$165+$C$177 */ 5272 input_port_threshold->total_min_RE_WQEs_pkts = 5273 input_port_threshold->min_RE_WQEs_pkts_for_total_PG + 5274 input_port_threshold->min_RE_WQEs_pkts_for_total_port; 5275 5276 /* C184 = $C$166+$C$178 */ 5277 input_port_threshold->total_min_EQEs_pkts = 5278 input_port_threshold->min_EQEs_pkts_for_total_PG + 5279 input_port_threshold->min_EQEs_pkts_for_total_port; 5280 5281 5282 /* Fill up output threshold info */ 5283 /* C204 = =IF(C14=0, C58, 0) */ 5284 if (_soc_sb2_mmu_params.lossless_mode_d_c == 0) { 5285 output_port_threshold->min_grntd_res_queue_cells_int_buff = 5286 _soc_sb2_mmu_params.per_cos_res_cells_for_int_buff_d; 5287 } 5288 5289 /* C205 =IF(C17=1,IF(C14=0, C77, 0), 0) */ 5290 if (_soc_sb2_mmu_params.extbuf_used_d_c) { 5291 if (_soc_sb2_mmu_params.lossless_mode_d_c == 0) { 5292 output_port_threshold->min_grntd_res_queue_cells_ext_buff = 5293 general_info->ether_mtu_cells_for_ext_buff; 5294 } 5295 } 5296 5297 /* C206 = =IF(C14=0, $C$58/$C$105, 0) */ 5298 if (_soc_sb2_mmu_params.lossless_mode_d_c == 0) { 5299 output_port_threshold->min_grntd_res_queue_cells_EQEs = 5300 _soc_sb2_mmu_params.per_cos_res_cells_for_int_buff_d/ 5301 general_info->ext_buff_cells_per_avg_size_pkt; 5302 } 5303 5304 /* C207 =IF($C$14, 0, IF($C$17, $C$58, 0)) */ 5305 if (_soc_sb2_mmu_params.lossless_mode_d_c == 0) { 5306 if (_soc_sb2_mmu_params.extbuf_used_d_c) { 5307 output_port_threshold->min_grntd_res_EMA_queue_cells = 5308 _soc_sb2_mmu_params.per_cos_res_cells_for_int_buff_d; 5309 } 5310 } 5311 5312 /* C208 = C204 */ 5313 output_port_threshold->min_grntd_res_RE_WQs_cells = 5314 output_port_threshold->min_grntd_res_queue_cells_int_buff; 5315 5316 /* C209 = C204 */ 5317 output_port_threshold->min_grntd_res_RE_WQs_queue_cells_for_int_buff = 5318 output_port_threshold->min_grntd_res_queue_cells_int_buff; 5319 5320 /* C210 =IF($C$14, 0, IF($C$17,C205, 0)) */ 5321 if (_soc_sb2_mmu_params.lossless_mode_d_c == 0) { 5322 if (_soc_sb2_mmu_params.extbuf_used_d_c) { 5323 output_port_threshold-> 5324 min_grntd_res_RE_WQs_queue_cells_for_ext_buff = 5325 general_info->ext_buff_cells_per_avg_size_pkt; 5326 } 5327 } 5328 5329 /* C211 = 4 */ 5330 output_port_threshold->min_grntd_res_EP_redirect_queue_entry_cells = 4; 5331 5332 5333 /* C213 =C89*$C$204 */ 5334 output_port_threshold->min_grntd_tot_res_queue_cells_int_buff = 5335 general_info->total_base_queue_int_buff * 5336 output_port_threshold->min_grntd_res_queue_cells_int_buff; 5337 5338 /* C214 =C94*$C$205 */ 5339 output_port_threshold->min_grntd_tot_res_queue_cells_ext_buff = 5340 general_info->total_egr_queues_in_device * 5341 output_port_threshold->min_grntd_res_queue_cells_ext_buff; 5342 5343 /* C215 =C94*$C$206 */ 5344 output_port_threshold->min_grntd_tot_res_queue_cells_EQEs = 5345 general_info->total_egr_queues_in_device * 5346 output_port_threshold->min_grntd_res_queue_cells_EQEs; 5347 5348 /* C216 =$C$55*$C$207 */ 5349 output_port_threshold->min_grntd_tot_res_EMA_queue_cells = 5350 _soc_sb2_mmu_params.mmu_ema_queues * 5351 output_port_threshold->min_grntd_res_EMA_queue_cells; 5352 5353 /* C217 =$C$54*$C$208 */ 5354 output_port_threshold->min_grntd_tot_res_RE_WQs_cells = 5355 _soc_sb2_mmu_params.mmu_repl_engine_work_queue_in_device * 5356 output_port_threshold->min_grntd_res_RE_WQs_cells; 5357 5358 /* C218 =$C$54*$C$209 */ 5359 output_port_threshold->min_grntd_tot_res_RE_WQs_queue_cells_for_int_buff = 5360 _soc_sb2_mmu_params.mmu_repl_engine_work_queue_in_device * 5361 output_port_threshold->min_grntd_res_RE_WQs_queue_cells_for_int_buff; 5362 5363 /* C219 =$C$54*$C$210 */ 5364 output_port_threshold->min_grntd_tot_res_RE_WQs_queue_cells_for_ext_buff = 5365 _soc_sb2_mmu_params.mmu_repl_engine_work_queue_in_device * 5366 output_port_threshold->min_grntd_res_RE_WQs_queue_cells_for_ext_buff; 5367 5368 /* C220 =C211*(C36) */ 5369 output_port_threshold->min_grntd_tot_res_EP_redirect_queue_entry_cells = 5370 _soc_sb2_mmu_params.mmu_num_ep_redirection_queue * 5371 output_port_threshold->min_grntd_res_EP_redirect_queue_entry_cells; 5372 5373 /* C186 =$C$98-$C$150-$C$180-IF(C14=0, 0, C213)-IF(C14=0, 0, C218) */ 5374 5375 input_port_threshold->total_shared_ing_buff_pool = 5376 general_info->int_buff_pool - 5377 input_port_threshold->total_min_int_buff_cells - 5378 input_port_threshold->total_hdrm_int_buff_cells; 5379 if (_soc_sb2_mmu_params.lossless_mode_d_c) { 5380 input_port_threshold->total_shared_ing_buff_pool -= 5381 output_port_threshold->min_grntd_tot_res_queue_cells_int_buff; 5382 input_port_threshold->total_shared_ing_buff_pool -= 5383 output_port_threshold->min_grntd_tot_res_RE_WQs_queue_cells_for_int_buff; 5384 } 5385 5386 /* C187 =IF(C17,$C$99-$C$181-$C$151-IF(C14=0,0,C216), 0) */ 5387 if (_soc_sb2_mmu_params.extbuf_used_d_c) { 5388 input_port_threshold->total_shared_EMA_buff = 5389 general_info->ema_pool - 5390 input_port_threshold->total_min_int_buff_ema_pool_cells - 5391 input_port_threshold->total_hdrm_int_buff_ema_pool_cells; 5392 if (_soc_sb2_mmu_params.lossless_mode_d_c) { 5393 input_port_threshold->total_shared_EMA_buff -= 5394 output_port_threshold->min_grntd_tot_res_EMA_queue_cells; 5395 } 5396 } 5397 5398 /* C188 =$C$100-$C$152-$C$182-IF(C14=0, 0, C214) - IF(C14=0, 0, C219)-IF(C12=0, 0, C56) */ 5399 input_port_threshold->total_shared_ext_buff = 5400 general_info->max_ext_cell_buff_size - 5401 input_port_threshold->total_hdrm_ext_buff_cells - 5402 input_port_threshold->total_min_ext_buff_cells; 5403 if (_soc_sb2_mmu_params.lossless_mode_d_c) { 5404 input_port_threshold->total_shared_ext_buff -= 5405 output_port_threshold->min_grntd_tot_res_queue_cells_ext_buff; 5406 input_port_threshold->total_shared_ext_buff -= 5407 output_port_threshold->min_grntd_tot_res_RE_WQs_queue_cells_for_ext_buff; 5408 } 5409 if (_soc_sb2_mmu_params.packing_mode_d_c) { 5410 input_port_threshold->total_shared_ext_buff -= 5411 _soc_sb2_mmu_params.num_cells_rsrvd_ing_ext_buf; 5412 } 5413 5414 /* C189 =$C$101-$C$153-$C$183-IF(C14=0, C217) */ 5415 input_port_threshold->total_shared_RE_WQEs_buff = 5416 general_info->repl_engine_work_queue_entries - 5417 input_port_threshold->total_hdrm_RE_WQEs_pkts - 5418 input_port_threshold->total_min_RE_WQEs_pkts; 5419 if (!_soc_sb2_mmu_params.lossless_mode_d_c) { 5420 input_port_threshold->total_shared_RE_WQEs_buff -= 5421 output_port_threshold->min_grntd_tot_res_RE_WQs_cells; 5422 } 5423 5424 /* C190 =($C$49*1024)-$C$154-$C$184-IF(C14=0, 0, C215)-1 */ 5425 input_port_threshold->total_shared_EQEs_buff = 5426 (_soc_sb2_mmu_params.mmu_egress_queue_entries * 1024) - 5427 input_port_threshold->total_hdrm_EQEs_pkts - 5428 input_port_threshold->total_min_EQEs_pkts; 5429 if (_soc_sb2_mmu_params.lossless_mode_d_c) { 5430 input_port_threshold->total_shared_EQEs_buff -= 5431 output_port_threshold->min_grntd_tot_res_queue_cells_EQEs; 5432 } 5433 input_port_threshold->total_shared_EQEs_buff -= 1; 5434 5435 /* C192 =FLOOR(($C$60*$C$186)/(1+($C$60*1)),1) */ 5436 input_port_threshold->ingress_burst_cells_size_for_one_port = sal_floor_func( 5437 (_soc_sb2_mmu_params.mmu_ing_port_dyn_thd_param * 5438 input_port_threshold->total_shared_ing_buff_pool), 5439 (1+(_soc_sb2_mmu_params.mmu_ing_port_dyn_thd_param*1))); 5440 5441 /* C193 =FLOOR(($C$60*$C$190)/(1+($C$60*1)),1) */ 5442 input_port_threshold->ingress_burst_pkts_size_for_one_port = sal_floor_func( 5443 (_soc_sb2_mmu_params.mmu_ing_port_dyn_thd_param * 5444 input_port_threshold->total_shared_EQEs_buff), 5445 (1+(_soc_sb2_mmu_params.mmu_ing_port_dyn_thd_param*1))); 5446 5447 /* C194 =FLOOR(($C$60*$C$186)/(1+($C$60*$C$79)),1) */ 5448 input_port_threshold->ingress_burst_cells_size_for_all_ports = sal_floor_func( 5449 (_soc_sb2_mmu_params.mmu_ing_port_dyn_thd_param * 5450 input_port_threshold->total_shared_ing_buff_pool), 5451 (1+(_soc_sb2_mmu_params.mmu_ing_port_dyn_thd_param* 5452 general_info->total_num_of_ports))); 5453 5454 /* C195 =($C$194+$C$168+C156)*$C$79 */ 5455 input_port_threshold->ingress_total_shared_cells_use_for_all_port = 5456 (input_port_threshold->ingress_burst_cells_size_for_all_ports + 5457 input_port_threshold->min_int_buff_cells_for_a_port + 5458 input_port_threshold->min_int_buff_cells_per_PG) * 5459 general_info->total_num_of_ports; 5460 5461 /* C196 =FLOOR(($C$60*$C$190)/(1+($C$60*$C$79)),1) */ 5462 input_port_threshold->ingress_burst_pkts_size_for_all_port = sal_floor_func( 5463 _soc_sb2_mmu_params.mmu_ing_port_dyn_thd_param * 5464 input_port_threshold->total_shared_EQEs_buff, 5465 (1+(_soc_sb2_mmu_params.mmu_ing_port_dyn_thd_param* 5466 general_info->total_num_of_ports))); 5467 5468 /* C197 =($C$196+$C$172+C160)*$C$79 */ 5469 input_port_threshold->ingress_total_shared_pkts_use_for_all_port = 5470 (input_port_threshold->ingress_burst_pkts_size_for_all_port+ 5471 input_port_threshold->min_EQEs_pkts_for_a_port + 5472 input_port_threshold->min_EQEs_pkt_per_PG) * 5473 general_info->total_num_of_ports; 5474 5475 /* C198 = =$C$195+C150 */ 5476 input_port_threshold->ingress_total_shared_hdrm_cells_use_for_all_port = 5477 input_port_threshold->ingress_total_shared_cells_use_for_all_port + 5478 input_port_threshold->total_hdrm_int_buff_cells; 5479 5480 /* C199 = =$C$197+C154 */ 5481 input_port_threshold->ingress_total_shared_hdrm_pkts_use_for_all_port = 5482 input_port_threshold->ingress_total_shared_pkts_use_for_all_port + 5483 input_port_threshold->total_hdrm_EQEs_pkts; 5484 5485 /* C222 =C98-$C$213-C218 */ 5486 output_port_threshold->min_grntd_tot_shr_queue_cells_int_buff = 5487 general_info->int_buff_pool - 5488 output_port_threshold-> 5489 min_grntd_tot_res_queue_cells_int_buff- 5490 output_port_threshold-> 5491 min_grntd_tot_res_RE_WQs_queue_cells_for_int_buff; 5492 5493 /* C223 =$C$100-$C$214-C219 */ 5494 output_port_threshold->min_grntd_tot_shr_queue_cells_ext_buff = 5495 general_info->max_ext_cell_buff_size - 5496 output_port_threshold->min_grntd_tot_res_queue_cells_ext_buff; 5497 output_port_threshold->min_grntd_tot_shr_queue_cells_ext_buff -= 5498 output_port_threshold->min_grntd_tot_res_RE_WQs_queue_cells_for_ext_buff; 5499 5500 /* C224 =$C$49*1024-$C$215-1 */ 5501 output_port_threshold->min_grntd_tot_shr_queue_cells_EQEs = 5502 (_soc_sb2_mmu_params.mmu_egress_queue_entries*1024) - 5503 output_port_threshold->min_grntd_tot_res_queue_cells_EQEs - 1; 5504 5505 /* C225 =$C$99-$C$216 */ 5506 output_port_threshold->min_grntd_tot_shr_EMA_queue_cells = 5507 general_info->ema_pool - 5508 output_port_threshold->min_grntd_tot_res_EMA_queue_cells; 5509 5510 /* C226 =$C$101-$C$217 */ 5511 output_port_threshold->min_grntd_tot_shr_RE_WQs_cells = 5512 general_info->repl_engine_work_queue_entries - 5513 output_port_threshold->min_grntd_tot_res_RE_WQs_cells ; 5514 5515 /* C227 =C222 */ 5516 output_port_threshold->min_grntd_tot_shr_RE_WQs_queue_cells_for_int_buff = 5517 output_port_threshold->min_grntd_tot_shr_queue_cells_int_buff ; 5518 5519 /* C228 =$C$100-$C$219-C214 */ 5520 output_port_threshold-> 5521 min_grntd_tot_shr_RE_WQs_queue_cells_for_ext_buff = 5522 general_info->max_ext_cell_buff_size - 5523 output_port_threshold->min_grntd_tot_res_RE_WQs_queue_cells_for_ext_buff - 5524 output_port_threshold->min_grntd_tot_res_queue_cells_ext_buff ; 5525 5526 /* C229 =C50-C220 */ 5527 output_port_threshold->min_grntd_tot_shr_EP_redirect_queue_entry_cells = 5528 _soc_sb2_mmu_params.mmu_ep_redirect_queue_entries - 5529 output_port_threshold->min_grntd_tot_res_EP_redirect_queue_entry_cells; 5530 5531 /* C230 = 2 */ 5532 output_port_threshold->egress_queue_dynamic_threshold_parameter = 2; 5533 5534 /* C231 =FLOOR( ($C$62*$C$222)/(1+($C$62*1)), 1) */ 5535 output_port_threshold->egress_burst_cells_size_for_one_queue = sal_floor_func( 5536 (_soc_sb2_mmu_params.mmu_egr_queue_dyn_thd_param_baf * 5537 output_port_threshold->min_grntd_tot_shr_queue_cells_int_buff), 5538 (1 + (_soc_sb2_mmu_params.mmu_egr_queue_dyn_thd_param_baf*1))); 5539 5540 /* C232 =FLOOR( ($C$62*$C$224)/(1+($C$62*1)), 1) */ 5541 output_port_threshold->egress_burst_pkts_size_for_one_queue = sal_floor_func( 5542 (_soc_sb2_mmu_params.mmu_egr_queue_dyn_thd_param_baf * 5543 output_port_threshold->min_grntd_tot_shr_queue_cells_EQEs), 5544 (1 + (_soc_sb2_mmu_params.mmu_egr_queue_dyn_thd_param_baf * 1))); 5545 5546 /* C233 = =FLOOR( ($C$62*$C$222)/(1+($C$62*$C$79)), 1)*/ 5547 output_port_threshold->egress_burst_cells_size_for_all_ports = sal_floor_func( 5548 (_soc_sb2_mmu_params.mmu_egr_queue_dyn_thd_param_baf * 5549 output_port_threshold->min_grntd_tot_shr_queue_cells_int_buff), 5550 (1 + (_soc_sb2_mmu_params.mmu_egr_queue_dyn_thd_param_baf * 5551 general_info->total_num_of_ports))); 5552 5553 /* C234 =FLOOR( ($C$62*$C$224)/(1+($C$62*$C$79)), 1) */ 5554 output_port_threshold->egress_burst_pkts_size_for_all_ports = sal_floor_func( 5555 (_soc_sb2_mmu_params.mmu_egr_queue_dyn_thd_param_baf * 5556 output_port_threshold->min_grntd_tot_shr_queue_cells_EQEs), 5557 (1 + (_soc_sb2_mmu_params.mmu_egr_queue_dyn_thd_param_baf * 5558 general_info->total_num_of_ports))); 5559 5560 /* C235 =FLOOR( ($C$62*$C$222)/(1+($C$62*C93)), 1) */ 5561 output_port_threshold->egress_burst_cells_size_for_all_queues = sal_floor_func( 5562 (_soc_sb2_mmu_params.mmu_egr_queue_dyn_thd_param_baf * 5563 output_port_threshold->min_grntd_tot_shr_queue_cells_int_buff), 5564 (1 + (_soc_sb2_mmu_params.mmu_egr_queue_dyn_thd_param_baf * 5565 general_info->total_egr_base_queues_in_device))); 5566 5567 /* C236 =FLOOR( ($C$62*$C$224)/(1+($C$62*C93)), 1) */ 5568 output_port_threshold->egress_burst_pkts_size_for_all_queues = sal_floor_func( 5569 (_soc_sb2_mmu_params.mmu_egr_queue_dyn_thd_param_baf * 5570 output_port_threshold->min_grntd_tot_shr_queue_cells_EQEs), 5571 (1 + (_soc_sb2_mmu_params.mmu_egr_queue_dyn_thd_param_baf * 5572 general_info->total_egr_base_queues_in_device))); 5573 5574 /* C237 =C93*$C$235 */ 5575 output_port_threshold->egress_total_use_in_cells_for_all_queues = 5576 general_info->total_egr_base_queues_in_device * 5577 output_port_threshold->egress_burst_cells_size_for_all_queues; 5578 5579 /* C238 =C93*$C$236 */ 5580 output_port_threshold->egress_total_use_in_pkts_for_all_queues = 5581 general_info->total_egr_base_queues_in_device * 5582 output_port_threshold->egress_burst_pkts_size_for_all_queues; 5583 5584 /* C239 =$C$222-C237*/ 5585 output_port_threshold->egress_remaining_cells_for_all_queues = 5586 output_port_threshold->min_grntd_tot_shr_queue_cells_int_buff - 5587 output_port_threshold->egress_total_use_in_cells_for_all_queues; 5588 5589 /* C240 =$C$224-C238*/ 5590 output_port_threshold->egress_remaining_pkts_for_all_queues = 5591 output_port_threshold->min_grntd_tot_shr_queue_cells_EQEs - 5592 output_port_threshold->egress_total_use_in_pkts_for_all_queues; 5593 5594 5595 /* ===================== */ 5596 /* Device Wide Registers */ 5597 /* ===================== */ 5598 if (flex_port == -1) { 5599 /* This is flex operation. so no need to re-configure */ 5600 if (!_soc_sb2_mmu_params.extbuf_used_d_c) { 5601 SOC_IF_ERROR_RETURN(READ_TOP_SW_BOND_OVRD_CTRL1r(unit, &rval)); 5602 soc_reg_field_set(unit, TOP_SW_BOND_OVRD_CTRL1r, &rval, 5603 MMU_EXT_BUFFER_ENABLEf, 0); 5604 SOC_IF_ERROR_RETURN(WRITE_TOP_SW_BOND_OVRD_CTRL1r(unit, rval)); 5605 } 5606 5607 /* C244: CFAPICONFIG.CFAPIPOOLSIZE =C42+22 */ 5608 SOC_IF_ERROR_RETURN(READ_CFAPICONFIGr(unit, &rval)); 5609 soc_reg_field_set(unit, CFAPICONFIGr, &rval, CFAPIPOOLSIZEf, 5610 _soc_sb2_mmu_params.mmu_int_buf_size + 22 ); 5611 SOC_IF_ERROR_RETURN(WRITE_CFAPICONFIGr(unit, rval)); 5612 5613 5614 /* C245: CFAPIFULLSETPOINT.CFAPIFULLSETPOINT = =C96 */ 5615 SOC_IF_ERROR_RETURN(READ_CFAPIFULLSETPOINTr(unit, &rval)); 5616 soc_reg_field_set(unit, CFAPIFULLSETPOINTr, &rval, CFAPIFULLSETPOINTf, 5617 general_info->int_cell_buff_size_after_limitation); 5618 SOC_IF_ERROR_RETURN(WRITE_CFAPIFULLSETPOINTr(unit, rval)); 5619 5620 /* C246: CFAPIFULLRESETPOINT.CFAPIFULLRESETPOINT =C244-128 */ 5621 SOC_IF_ERROR_RETURN(READ_CFAPIFULLRESETPOINTr(unit, &rval)); 5622 soc_reg_field_set(unit, CFAPIFULLRESETPOINTr, &rval, CFAPIFULLRESETPOINTf, 5623 _soc_sb2_mmu_params.mmu_int_buf_size + 22 - 128 ); 5624 SOC_IF_ERROR_RETURN(WRITE_CFAPIFULLRESETPOINTr(unit, rval)); 5625 5626 /* C247: CFAPECONFIG.CFAPEPOOLSIZE =C47*1024*1024/C10-1*/ 5627 SOC_IF_ERROR_RETURN(READ_CFAPECONFIGr(unit, &rval)); 5628 soc_reg_field_set(unit, CFAPECONFIGr, &rval, CFAPEPOOLSIZEf, 5629 ((_soc_sb2_mmu_params.mmu_ext_buf_size * 1024 * 1024)/ 5630 _soc_sb2_mmu_params.mmu_ext_buf_cell_size) -1); 5631 SOC_IF_ERROR_RETURN(WRITE_CFAPECONFIGr(unit, rval)); 5632 temp_val = (((_soc_sb2_mmu_params.mmu_ext_buf_size * 1024 * 1024)/ 5633 _soc_sb2_mmu_params.mmu_ext_buf_cell_size) -1); 5634 5635 /* C248: CFAPEFULLSETPOINT.CFAPEFULLSETPOINT =C247-C48 */ 5636 SOC_IF_ERROR_RETURN(READ_CFAPEFULLSETPOINTr(unit, &rval)); 5637 soc_reg_field_set(unit, CFAPEFULLSETPOINTr, &rval, CFAPEFULLSETPOINTf, 5638 temp_val - _soc_sb2_mmu_params.mmu_reserved_ext_buf_space_cfap); 5639 SOC_IF_ERROR_RETURN(WRITE_CFAPEFULLSETPOINTr(unit, rval)); 5640 5641 /* C249: CFAPEFULLRESETPOINT.CFAPEFULLRESETPOINT =C247-128 */ 5642 SOC_IF_ERROR_RETURN(READ_CFAPEFULLRESETPOINTr(unit, &rval)); 5643 soc_reg_field_set(unit, CFAPEFULLRESETPOINTr, &rval, CFAPEFULLRESETPOINTf, 5644 temp_val - 128 ); 5645 SOC_IF_ERROR_RETURN(WRITE_CFAPEFULLRESETPOINTr(unit, rval)); 5646 5647 /* C250: MMU_ENQ_FAPCONFIG_0.FAPPOOLSIZE =C52*1024-1*/ 5648 SOC_IF_ERROR_RETURN(READ_MMU_ENQ_FAPCONFIG_0r(unit, &rval)); 5649 soc_reg_field_set(unit, MMU_ENQ_FAPCONFIG_0r, &rval, FAPPOOLSIZEf, 5650 (_soc_sb2_mmu_params.mmu_repl_engine_work_queue_entries*1024 - 1 )); 5651 SOC_IF_ERROR_RETURN(WRITE_MMU_ENQ_FAPCONFIG_0r(unit, rval)); 5652 temp_val = _soc_sb2_mmu_params.mmu_repl_engine_work_queue_entries*1024 - 1 ; 5653 5654 /* C251 MMU_ENQ_FAPFULLSETPOINT_0.FAPFULLSETPOINT =C250-64 */ 5655 SOC_IF_ERROR_RETURN(READ_MMU_ENQ_FAPFULLSETPOINT_0r(unit, &rval)); 5656 soc_reg_field_set(unit, MMU_ENQ_FAPFULLSETPOINT_0r, &rval, FAPFULLSETPOINTf, 5657 temp_val - 64); 5658 SOC_IF_ERROR_RETURN(WRITE_MMU_ENQ_FAPFULLSETPOINT_0r(unit, rval)); 5659 5660 /* C252 MMU_ENQ_FAPFULLRESETPOINT_0.FAPFULLRESETPOINT =C250-128 */ 5661 SOC_IF_ERROR_RETURN(READ_MMU_ENQ_FAPFULLRESETPOINT_0r(unit, &rval)); 5662 soc_reg_field_set(unit, MMU_ENQ_FAPFULLRESETPOINT_0r, &rval, FAPFULLRESETPOINTf, 5663 temp_val - 128 ); 5664 SOC_IF_ERROR_RETURN(WRITE_MMU_ENQ_FAPFULLRESETPOINT_0r(unit, rval)); 5665 5666 /* C253: QSTRUCT_FAPCONFIG.FAPPOOLSIZE =(C49*1024+1024*6)/4 */ 5667 temp_val = (((_soc_sb2_mmu_params.mmu_egress_queue_entries * 1024 ) + (1024 *6))/4); 5668 for (idx =0 ; idx < 1; idx++) { 5669 SOC_IF_ERROR_RETURN(READ_QSTRUCT_FAPCONFIGr(unit, idx, &rval)); 5670 soc_reg_field_set(unit, QSTRUCT_FAPCONFIGr, &rval, FAPPOOLSIZEf, 5671 temp_val); 5672 SOC_IF_ERROR_RETURN(WRITE_QSTRUCT_FAPCONFIGr(unit, idx, rval)); 5673 } 5674 5675 /* C254 QSTRUCT_FAPFULLSETPOINT.FAPFULLSETPOINT */ 5676 for (idx =0 ; idx < 1; idx++) { 5677 SOC_IF_ERROR_RETURN(READ_QSTRUCT_FAPFULLSETPOINTr(unit, idx, &rval)); 5678 soc_reg_field_set(unit, QSTRUCT_FAPFULLSETPOINTr, &rval, FAPFULLSETPOINTf, 5679 17912); 5680 SOC_IF_ERROR_RETURN(WRITE_QSTRUCT_FAPFULLSETPOINTr(unit, idx, rval)); 5681 } 5682 5683 /* C255 QSTRUCT_FAPFULLRESETPOINT.FAPFULLRESETPOINT */ 5684 for (idx =0 ; idx < 1; idx++) { 5685 SOC_IF_ERROR_RETURN(READ_QSTRUCT_FAPFULLRESETPOINTr(unit, idx, &rval)); 5686 soc_reg_field_set(unit, QSTRUCT_FAPFULLRESETPOINTr, &rval, 5687 FAPFULLRESETPOINTf, 5688 17896 ); 5689 SOC_IF_ERROR_RETURN(WRITE_QSTRUCT_FAPFULLRESETPOINTr(unit, idx, rval)); 5690 } 5691 5692 /* C258: TOP_SW_BOND_OVRD_CTRL1.MMU_PACKING_ENABLE = C12 */ 5693 SOC_IF_ERROR_RETURN(READ_TOP_SW_BOND_OVRD_CTRL1r(unit, &rval)); 5694 soc_reg_field_set(unit, TOP_SW_BOND_OVRD_CTRL1r, &rval, MMU_PACKING_ENABLEf, 5695 _soc_sb2_mmu_params.packing_mode_d_c); 5696 SOC_IF_ERROR_RETURN(WRITE_TOP_SW_BOND_OVRD_CTRL1r(unit, rval)); 5697 5698 /* C259: MMU_ENQ_PACKING_REAS_FIFO_PROFILE_THRESH.THRESH_PROFILE_[0..3] = C13 */ 5699 SOC_IF_ERROR_RETURN(READ_MMU_ENQ_PACKING_REAS_FIFO_PROFILE_THRESHr(unit, &rval)); 5700 soc_reg_field_set(unit, MMU_ENQ_PACKING_REAS_FIFO_PROFILE_THRESHr, &rval, THRESH_PROFILE_0f, 5701 _soc_sb2_mmu_params.max_pkt_size_support_packing); 5702 soc_reg_field_set(unit, MMU_ENQ_PACKING_REAS_FIFO_PROFILE_THRESHr, &rval, THRESH_PROFILE_1f, 5703 _soc_sb2_mmu_params.max_pkt_size_support_packing); 5704 soc_reg_field_set(unit, MMU_ENQ_PACKING_REAS_FIFO_PROFILE_THRESHr, &rval, THRESH_PROFILE_2f, 5705 _soc_sb2_mmu_params.max_pkt_size_support_packing); 5706 soc_reg_field_set(unit, MMU_ENQ_PACKING_REAS_FIFO_PROFILE_THRESHr, &rval, THRESH_PROFILE_3f, 5707 _soc_sb2_mmu_params.max_pkt_size_support_packing); 5708 SOC_IF_ERROR_RETURN(WRITE_MMU_ENQ_PACKING_REAS_FIFO_PROFILE_THRESHr(unit, rval)); 5709 5710 /* C260: MMU_ENQ_PACKING_REAS_FIFO_THRESH_PROFILE_[0/1/2].SRCPORT_[0..41] = 0 */ 5711 rval = 0; 5712 SOC_IF_ERROR_RETURN(WRITE_MMU_ENQ_PACKING_REAS_FIFO_THRESH_PROFILE_0r(unit, rval)); 5713 SOC_IF_ERROR_RETURN(WRITE_MMU_ENQ_PACKING_REAS_FIFO_THRESH_PROFILE_1r(unit, rval)); 5714 5715 /* C261: THDO_MISCCONFIG.UCMC_SEPARATION = 0 */ 5716 SOC_IF_ERROR_RETURN(READ_THDO_MISCCONFIGr(unit, &rval)); 5717 soc_reg_field_set(unit, THDO_MISCCONFIGr, &rval, UCMC_SEPARATIONf, 0); 5718 SOC_IF_ERROR_RETURN(WRITE_THDO_MISCCONFIGr(unit, rval)); 5719 5720 /* C262: WRED_MISCCONFIG.UCMC_SEPARATION = 0 */ 5721 SOC_IF_ERROR_RETURN(READ_WRED_MISCCONFIGr(unit, &rval)); 5722 soc_reg_field_set(unit, WRED_MISCCONFIGr, &rval, UCMC_SEPARATIONf, 0); 5723 SOC_IF_ERROR_RETURN(WRITE_WRED_MISCCONFIGr(unit, rval)); 5724 5725 /* C263: MISCCONFIG.THDI_ROLLOVER_COUNT = 0xB4 */ 5726 SOC_IF_ERROR_RETURN(READ_MISCCONFIGr(unit, &rval)); 5727 soc_reg_field_set(unit, MISCCONFIGr, &rval, THDI_ROLLOVER_COUNTf, 0xb4); 5728 SOC_IF_ERROR_RETURN(WRITE_MISCCONFIGr(unit, rval)); 5729 5730 /* C266: COLOR_AWARE.ENABLE = 0 */ 5731 SOC_IF_ERROR_RETURN(READ_COLOR_AWAREr (unit, &rval)); 5732 soc_reg_field_set(unit, COLOR_AWAREr, &rval, ENABLEf, 0); 5733 SOC_IF_ERROR_RETURN(WRITE_COLOR_AWAREr (unit, rval)); 5734 5735 /* C268: GLOBAL_HDRM_LIMIT.GLOBAL_HDRM_LIMIT = =$C$110 */ 5736 SOC_IF_ERROR_RETURN(READ_GLOBAL_HDRM_LIMITr (unit, &rval)); 5737 soc_reg_field_set(unit, GLOBAL_HDRM_LIMITr, &rval, GLOBAL_HDRM_LIMITf, 5738 input_port_threshold->global_hdrm_cells_for_int_buff_ingress_pool); 5739 SOC_IF_ERROR_RETURN(WRITE_GLOBAL_HDRM_LIMITr (unit, rval)); 5740 5741 /* C269: BUFFER_CELL_LIMIT_SP.LIMIT = =$C$186 */ 5742 SOC_IF_ERROR_RETURN(READ_BUFFER_CELL_LIMIT_SPr (unit, service_pool, &rval)); 5743 soc_reg_field_set(unit, BUFFER_CELL_LIMIT_SPr, &rval, LIMITf, 5744 input_port_threshold->total_shared_ing_buff_pool); 5745 SOC_IF_ERROR_RETURN(WRITE_BUFFER_CELL_LIMIT_SPr (unit, service_pool, rval)); 5746 5747 /* C270: CELL_RESET_LIMIT_OFFSET_SP.OFFSET =CEILING(C82/4, 1)*C76 */ 5748 SOC_IF_ERROR_RETURN(READ_CELL_RESET_LIMIT_OFFSET_SPr (unit, 5749 service_pool, &rval)); 5750 temp_val = sal_ceil_func(general_info->total_num_of_ports_excl_lpbk_olp_cpu,4) * 5751 general_info->ether_mtu_cells_for_int_buff; 5752 soc_reg_field_set(unit, CELL_RESET_LIMIT_OFFSET_SPr, &rval, 5753 OFFSETf, temp_val); 5754 SOC_IF_ERROR_RETURN(WRITE_CELL_RESET_LIMIT_OFFSET_SPr (unit, 5755 service_pool, rval)); 5756 5757 /* External Buffer */ 5758 if (_soc_sb2_mmu_params.extbuf_used_d_c) { 5759 /* C272: THDIEXT_GLOBAL_HDRM_LIMIT.GLOBAL_HDRM_LIMIT 5760 =IF(C17=0, "NA", C112)*/ 5761 SOC_IF_ERROR_RETURN(READ_THDIEXT_GLOBAL_HDRM_LIMITr (unit, &rval)); 5762 soc_reg_field_set(unit, THDIEXT_GLOBAL_HDRM_LIMITr, &rval, 5763 GLOBAL_HDRM_LIMITf, 5764 input_port_threshold->global_hdrm_cells_for_ext_buff_pool); 5765 SOC_IF_ERROR_RETURN(WRITE_THDIEXT_GLOBAL_HDRM_LIMITr (unit, rval)); 5766 5767 /* C273: THDIEXT_BUFFER_CELL_LIMIT_SP.LIMIT 5768 =IF(C17=0, "NA", C188)*/ 5769 SOC_IF_ERROR_RETURN(READ_THDIEXT_BUFFER_CELL_LIMIT_SPr ( 5770 unit, service_pool, &rval)); 5771 soc_reg_field_set(unit, THDIEXT_BUFFER_CELL_LIMIT_SPr, &rval, LIMITf, 5772 input_port_threshold->total_shared_ext_buff); 5773 SOC_IF_ERROR_RETURN(WRITE_THDIEXT_BUFFER_CELL_LIMIT_SPr (unit, 0,rval)); 5774 5775 /* C274:THDIEXT_CELL_RESET_LIMIT_OFFSET_SP.OFFSET 5776 =IF(C17=0, "NA", CEILING(C82/4, 1)*C77)*/ 5777 SOC_IF_ERROR_RETURN(READ_THDIEXT_CELL_RESET_LIMIT_OFFSET_SPr ( 5778 unit, service_pool, &rval)); 5779 temp_val = sal_ceil_func(general_info-> 5780 total_num_of_ports_excl_lpbk_olp_cpu, 5781 4) * general_info->ether_mtu_cells_for_ext_buff; 5782 soc_reg_field_set(unit, 5783 THDIEXT_CELL_RESET_LIMIT_OFFSET_SPr, &rval, OFFSETf, temp_val); 5784 SOC_IF_ERROR_RETURN(WRITE_THDIEXT_CELL_RESET_LIMIT_OFFSET_SPr ( 5785 unit, service_pool, rval)); 5786 5787 5788 /* EMA pool */ 5789 /* C276: THDIEMA_GLOBAL_HDRM_LIMIT.GLOBAL_HDRM_LIMIT 5790 =IF(C17=0, "NA", C111)*/ 5791 SOC_IF_ERROR_RETURN(READ_THDIEMA_GLOBAL_HDRM_LIMITr (unit, &rval)); 5792 soc_reg_field_set(unit, THDIEMA_GLOBAL_HDRM_LIMITr, &rval, 5793 GLOBAL_HDRM_LIMITf, 5794 input_port_threshold->global_hdrm_cells_for_int_buff_ema_pool); 5795 SOC_IF_ERROR_RETURN(WRITE_THDIEMA_GLOBAL_HDRM_LIMITr (unit, rval)); 5796 5797 /* C277: THDIEMA_BUFFER_CELL_LIMIT_SP.LIMIT =IF(C17=0, "NA", C187) */ 5798 SOC_IF_ERROR_RETURN(READ_THDIEMA_BUFFER_CELL_LIMIT_SPr ( 5799 unit, service_pool, &rval)); 5800 soc_reg_field_set(unit, THDIEMA_BUFFER_CELL_LIMIT_SPr, &rval, LIMITf, 5801 input_port_threshold->total_shared_EMA_buff); 5802 SOC_IF_ERROR_RETURN(WRITE_THDIEMA_BUFFER_CELL_LIMIT_SPr (unit, 0,rval)); 5803 5804 /* C278:THDIEMA_CELL_RESET_LIMIT_OFFSET_SP.OFFSET= 5805 =IF(C17=0, "NA", CEILING(C82/4, 1)*C76)*/ 5806 SOC_IF_ERROR_RETURN(READ_THDIEMA_CELL_RESET_LIMIT_OFFSET_SPr ( 5807 unit, service_pool, &rval)); 5808 temp_val = sal_ceil_func(general_info->total_num_of_ports_excl_lpbk_olp_cpu,4) * 5809 general_info->ether_mtu_cells_for_int_buff ; 5810 soc_reg_field_set( 5811 unit, THDIEMA_CELL_RESET_LIMIT_OFFSET_SPr, &rval, OFFSETf, 5812 temp_val); 5813 SOC_IF_ERROR_RETURN(WRITE_THDIEMA_CELL_RESET_LIMIT_OFFSET_SPr ( 5814 unit, service_pool, rval)); 5815 } 5816 5817 5818 /* C280: THDIRQE_GLOBAL_HDRM_LIMIT.GLOBAL_HDRM_LIMIT = C113 */ 5819 SOC_IF_ERROR_RETURN(READ_THDIRQE_GLOBAL_HDRM_LIMITr (unit, &rval)); 5820 soc_reg_field_set(unit, THDIRQE_GLOBAL_HDRM_LIMITr, &rval, 5821 GLOBAL_HDRM_LIMITf, 5822 input_port_threshold->global_hdrm_cells_for_RE_WQEs); 5823 SOC_IF_ERROR_RETURN(WRITE_THDIRQE_GLOBAL_HDRM_LIMITr (unit, rval)); 5824 5825 /* C281: THDIRQE_BUFFER_CELL_LIMIT_SP.LIMIT =$C$189 */ 5826 SOC_IF_ERROR_RETURN(READ_THDIRQE_BUFFER_CELL_LIMIT_SPr ( 5827 unit, service_pool, &rval)); 5828 soc_reg_field_set(unit, THDIRQE_BUFFER_CELL_LIMIT_SPr, &rval, LIMITf, 5829 input_port_threshold->total_shared_RE_WQEs_buff); 5830 SOC_IF_ERROR_RETURN(WRITE_THDIRQE_BUFFER_CELL_LIMIT_SPr ( 5831 unit, service_pool, rval)); 5832 5833 /* C282: = THDIRQE_CELL_RESET_LIMIT_OFFSET_SP.OFFSET = =CEILING(C82/4, 1) */ 5834 SOC_IF_ERROR_RETURN(READ_THDIRQE_CELL_RESET_LIMIT_OFFSET_SPr( 5835 unit,service_pool,&rval)); 5836 soc_reg_field_set(unit, THDIRQE_CELL_RESET_LIMIT_OFFSET_SPr, &rval, 5837 OFFSETf, 5838 sal_ceil_func(general_info->total_num_of_ports_excl_lpbk_olp_cpu , 4)); 5839 SOC_IF_ERROR_RETURN(WRITE_THDIRQE_CELL_RESET_LIMIT_OFFSET_SPr( 5840 unit,service_pool,rval)); 5841 5842 /* C284: THDIQEN_GLOBAL_HDRM_LIMIT.GLOBAL_HDRM_LIMIT = C114 */ 5843 SOC_IF_ERROR_RETURN(READ_THDIQEN_GLOBAL_HDRM_LIMITr (unit, &rval)); 5844 soc_reg_field_set(unit, THDIQEN_GLOBAL_HDRM_LIMITr, &rval, 5845 GLOBAL_HDRM_LIMITf, 5846 input_port_threshold->global_hdrm_cells_for_EQEs); 5847 SOC_IF_ERROR_RETURN(WRITE_THDIQEN_GLOBAL_HDRM_LIMITr (unit, rval)); 5848 5849 /* C285: THDIQEN_BUFFER_CELL_LIMIT_SP.LIMIT =$C$190 */ 5850 SOC_IF_ERROR_RETURN(READ_THDIQEN_BUFFER_CELL_LIMIT_SPr ( 5851 unit, service_pool, &rval)); 5852 soc_reg_field_set(unit, THDIQEN_BUFFER_CELL_LIMIT_SPr, &rval, LIMITf, 5853 input_port_threshold->total_shared_EQEs_buff); 5854 SOC_IF_ERROR_RETURN(WRITE_THDIQEN_BUFFER_CELL_LIMIT_SPr ( 5855 unit, service_pool, rval)); 5856 5857 /* C286: THDIQEN_CELL_RESET_LIMIT_OFFSET_SP.OFFSET= 5858 =CEILING(C82/4, 1)*C51*/ 5859 SOC_IF_ERROR_RETURN(READ_THDIQEN_CELL_RESET_LIMIT_OFFSET_SPr( 5860 unit,service_pool,&rval)); 5861 temp_val = sal_ceil_func(general_info->total_num_of_ports_excl_lpbk_olp_cpu, 4) * 5862 _soc_sb2_mmu_params.mmu_exp_num_of_repl_per_pkt; 5863 soc_reg_field_set(unit, THDIQEN_CELL_RESET_LIMIT_OFFSET_SPr, &rval, OFFSETf, 5864 temp_val); 5865 SOC_IF_ERROR_RETURN(WRITE_THDIQEN_CELL_RESET_LIMIT_OFFSET_SPr( 5866 unit,service_pool,rval)); 5867 5868 /* C289: OP_BUFFER_SHARED_LIMIT_CELLI.OP_BUFFER_SHARED_LIMIT_CELLI = C222 */ 5869 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_SHARED_LIMIT_CELLIr (unit, &rval)); 5870 soc_reg_field_set(unit, OP_BUFFER_SHARED_LIMIT_CELLIr, &rval, 5871 OP_BUFFER_SHARED_LIMIT_CELLIf, 5872 output_port_threshold->min_grntd_tot_shr_queue_cells_int_buff); 5873 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_SHARED_LIMIT_CELLIr (unit, rval)); 5874 5875 temp_val = output_port_threshold-> 5876 min_grntd_tot_shr_queue_cells_int_buff; 5877 5878 /* C290 OP_BUFFER_SHARED_LIMIT_RESUME_CELLI.OP_BUFFER_SHARED_LIMIT_RESUME_CELLI 5879 =C289-CEILING(C82/4, 1)*C76 */ 5880 5881 temp_val = temp_val - (sal_ceil_func(general_info->total_num_of_ports_excl_lpbk_olp_cpu,4) 5882 * general_info->ether_mtu_cells_for_int_buff); 5883 5884 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_SHARED_LIMIT_RESUME_CELLIr(unit, &rval)); 5885 soc_reg_field_set(unit, OP_BUFFER_SHARED_LIMIT_RESUME_CELLIr, &rval, 5886 OP_BUFFER_SHARED_LIMIT_RESUME_CELLIf, temp_val); 5887 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_SHARED_LIMIT_RESUME_CELLIr(unit, rval)); 5888 5889 /* C292 OP_BUFFER_LIMIT_RESUME_YELLOW_CELLI.OP_BUFFER_LIMIT_RESUME_YELLOW_CELLI = 5890 =CEILING(C290/8, 1) */ 5891 5892 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_LIMIT_RESUME_YELLOW_CELLIr ( 5893 unit, &rval)); 5894 soc_reg_field_set(unit, OP_BUFFER_LIMIT_RESUME_YELLOW_CELLIr, &rval, 5895 OP_BUFFER_LIMIT_RESUME_YELLOW_CELLIf, sal_ceil_func(temp_val,8)); 5896 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_RESUME_YELLOW_CELLIr ( 5897 unit, rval)); 5898 5899 /* C294 OP_BUFFER_LIMIT_RESUME_RED_CELLI.OP_BUFFER_LIMIT_RESUME_RED_CELLI 5900 =CEILING(C290/8, 1) */ 5901 5902 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_LIMIT_RESUME_RED_CELLIr (unit, &rval)); 5903 soc_reg_field_set(unit, OP_BUFFER_LIMIT_RESUME_RED_CELLIr, &rval, 5904 OP_BUFFER_LIMIT_RESUME_RED_CELLIf, sal_ceil_func(temp_val,8)); 5905 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_RESUME_RED_CELLIr (unit, rval)); 5906 5907 /* C291: OP_BUFFER_LIMIT_YELLOW_CELLI.OP_BUFFER_LIMIT_YELLOW_CELLI = 5908 =CEILING(C289/8, 1) */ 5909 temp_val = output_port_threshold-> 5910 min_grntd_tot_shr_queue_cells_int_buff; 5911 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_LIMIT_YELLOW_CELLIr (unit, &rval)); 5912 soc_reg_field_set(unit, OP_BUFFER_LIMIT_YELLOW_CELLIr, &rval, 5913 OP_BUFFER_LIMIT_YELLOW_CELLIf, sal_ceil_func(temp_val,8)); 5914 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_YELLOW_CELLIr (unit, rval)); 5915 5916 /* C293 OP_BUFFER_LIMIT_RED_CELLI.OP_BUFFER_LIMIT_RED_CELLI 5917 =CEILING(C289/8, 1) */ 5918 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_LIMIT_RED_CELLIr (unit, &rval)); 5919 soc_reg_field_set(unit, OP_BUFFER_LIMIT_RED_CELLIr, &rval, 5920 OP_BUFFER_LIMIT_RED_CELLIf, sal_ceil_func( temp_val,8)); 5921 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_RED_CELLIr (unit, rval)); 5922 5923 5924 /* External Buffer */ 5925 if (_soc_sb2_mmu_params.extbuf_used_d_c) { 5926 /* C296: 5927 OP_BUFFER_SHARED_LIMIT_CELLE.OP_BUFFER_SHARED_LIMIT_CELLE 5928 =IF(C17=0, "NA", C223)*/ 5929 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_SHARED_LIMIT_CELLE_POOL0r ( 5930 unit, &rval)); 5931 soc_reg_field_set(unit, OP_BUFFER_SHARED_LIMIT_CELLE_POOL0r, &rval, 5932 OP_BUFFER_SHARED_LIMIT_CELLEf, 5933 output_port_threshold->min_grntd_tot_shr_queue_cells_ext_buff); 5934 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_SHARED_LIMIT_CELLE_POOL0r ( 5935 unit, rval)); 5936 temp_val = output_port_threshold->min_grntd_tot_shr_queue_cells_ext_buff; 5937 5938 /* C298: OP_BUFFER_LIMIT_YELLOW_CELLE.OP_BUFFER_LIMIT_YELLOW_CELLE = 5939 =CEILING(C296/8, 1) */ 5940 /* C300: OP_BUFFER_LIMIT_RED_CELLE.OP_BUFFER_LIMIT_RED_CELLE = 5941 =CEILING(C296/8, 1) */ 5942 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_LIMIT_YELLOW_CELLE_POOL0r ( 5943 unit, &rval)); 5944 soc_reg_field_set(unit, OP_BUFFER_LIMIT_YELLOW_CELLE_POOL0r, &rval, 5945 OP_BUFFER_LIMIT_YELLOW_CELLEf, sal_ceil_func(temp_val,8)); 5946 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_YELLOW_CELLE_POOL0r ( 5947 unit, rval)); 5948 5949 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_LIMIT_RED_CELLE_POOL0r(unit, &rval)); 5950 soc_reg_field_set(unit, OP_BUFFER_LIMIT_RED_CELLE_POOL0r, &rval, 5951 OP_BUFFER_LIMIT_RED_CELLEf, sal_ceil_func( temp_val,8)); 5952 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_RED_CELLE_POOL0r(unit, rval)); 5953 5954 /* C297: OP_BUFFER_SHARED_LIMIT_RESUME_CELLE. 5955 OP_BUFFER_SHARED_LIMIT_RESUME_CELLE 5956 =IF(C17=0, "NA", C296-CEILING(C82/4, 1)*C77)*/ 5957 temp_val = ((temp_val - 5958 (sal_ceil_func(general_info->total_num_of_ports_excl_lpbk_olp_cpu ,4))) * 5959 general_info->ether_mtu_cells_for_ext_buff); 5960 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_SHARED_LIMIT_RESUME_CELLE_POOL0r( 5961 unit, &rval)); 5962 soc_reg_field_set(unit, OP_BUFFER_SHARED_LIMIT_RESUME_CELLE_POOL0r, 5963 &rval,OP_BUFFER_SHARED_LIMIT_RESUME_CELLEf, temp_val); 5964 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_SHARED_LIMIT_RESUME_CELLE_POOL0r( 5965 unit, rval)); 5966 5967 /* C299: OP_BUFFER_LIMIT_RESUME_YELLOW_CELLE. 5968 OP_BUFFER_LIMIT_RESUME_YELLOW_CELLE ==CEILING(C297/8, 1) */ 5969 /* C301: OP_BUFFER_LIMIT_RESUME_RED_CELLE. 5970 OP_BUFFER_LIMIT_RESUME_RED_CELLE ==CEILING(C297/8, 1) */ 5971 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_LIMIT_RESUME_YELLOW_CELLE_POOL0r ( 5972 unit, &rval)); 5973 soc_reg_field_set(unit, 5974 OP_BUFFER_LIMIT_RESUME_YELLOW_CELLE_POOL0r, &rval, 5975 OP_BUFFER_LIMIT_RESUME_YELLOW_CELLEf, sal_ceil_func(temp_val,8)); 5976 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_RESUME_YELLOW_CELLE_POOL0r ( 5977 unit, rval)); 5978 5979 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_LIMIT_RESUME_RED_CELLE_POOL0r ( 5980 unit, &rval)); 5981 soc_reg_field_set(unit, OP_BUFFER_LIMIT_RESUME_RED_CELLE_POOL0r, &rval, 5982 OP_BUFFER_LIMIT_RESUME_RED_CELLEf,sal_ceil_func(temp_val,8)); 5983 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_RESUME_RED_CELLE_POOL0r ( 5984 unit, rval)); 5985 5986 /* EMA pool */ 5987 /* C303: 5988 OP_BUFFER_SHARED_LIMIT_THDOEMA.OP_BUFFER_SHARED_LIMIT_CELLE 5989 =IF(C17=0, "NA", C225)*/ 5990 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_SHARED_LIMIT_THDOEMAr (unit, &rval)); 5991 soc_reg_field_set(unit, OP_BUFFER_SHARED_LIMIT_THDOEMAr, &rval, 5992 OP_BUFFER_SHARED_LIMITf, 5993 output_port_threshold->min_grntd_tot_shr_EMA_queue_cells); 5994 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_SHARED_LIMIT_THDOEMAr (unit, rval)); 5995 temp_val = output_port_threshold-> 5996 min_grntd_tot_shr_EMA_queue_cells; 5997 5998 /* C305: OP_BUFFER_LIMIT_YELLOW_THDOEMA.OP_BUFFER_LIMIT_YELLOW = 5999 =CEILING(C303/8, 1) */ 6000 /* C307: OP_BUFFER_LIMIT_RED_THDOEMA.OP_BUFFER_LIMIT_RED = 6001 =CEILING(C303/8, 1) */ 6002 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_LIMIT_YELLOW_THDOEMAr (unit, &rval)); 6003 soc_reg_field_set(unit, OP_BUFFER_LIMIT_YELLOW_THDOEMAr, &rval, 6004 OP_BUFFER_LIMIT_YELLOWf,sal_ceil_func(temp_val,8)); 6005 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_YELLOW_THDOEMAr (unit, rval)); 6006 6007 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_LIMIT_RED_THDOEMAr (unit, &rval)); 6008 soc_reg_field_set(unit, OP_BUFFER_LIMIT_RED_THDOEMAr, &rval, 6009 OP_BUFFER_LIMIT_REDf,sal_ceil_func( temp_val,8)); 6010 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_RED_THDOEMAr (unit, rval)); 6011 6012 6013 6014 /* C304: OP_BUFFER_SHARED_LIMIT_RESUME_THDOEMA. 6015 OP_BUFFER_SHARED_LIMIT_RESUME_CELLE 6016 =IF(C17=0, "NA", C303-CEILING(C82/4, 1)*C76) */ 6017 temp_val = (temp_val - (sal_ceil_func(general_info-> 6018 total_num_of_ports_excl_lpbk_olp_cpu,4)) * 6019 general_info->ether_mtu_cells_for_int_buff); 6020 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_SHARED_LIMIT_RESUME_THDOEMAr( 6021 unit, &rval)); 6022 soc_reg_field_set(unit, OP_BUFFER_SHARED_LIMIT_RESUME_THDOEMAr, &rval, 6023 OP_BUFFER_SHARED_LIMIT_RESUMEf, temp_val); 6024 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_SHARED_LIMIT_RESUME_THDOEMAr( 6025 unit, rval)); 6026 6027 6028 /* C306: OP_BUFFER_LIMIT_RESUME_YELLOW_THDOEMA. 6029 OP_BUFFER_LIMIT_RESUME_YELLOW==CEILING(C289/8, 1) */ 6030 /* C308: OP_BUFFER_LIMIT_RESUME_RED_THDOEMA. 6031 OP_BUFFER_LIMIT_RESUME_RED==CEILING(C289/8, 1) */ 6032 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_LIMIT_RESUME_YELLOW_THDOEMAr ( 6033 unit, &rval)); 6034 soc_reg_field_set(unit, OP_BUFFER_LIMIT_RESUME_YELLOW_THDOEMAr, &rval, 6035 OP_BUFFER_LIMIT_RESUME_YELLOWf,sal_ceil_func(temp_val,8)); 6036 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_RESUME_YELLOW_THDOEMAr ( 6037 unit, rval)); 6038 6039 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_LIMIT_RESUME_RED_THDOEMAr ( 6040 unit, &rval)); 6041 soc_reg_field_set(unit, OP_BUFFER_LIMIT_RESUME_RED_THDOEMAr, &rval, 6042 OP_BUFFER_LIMIT_RESUME_REDf,sal_ceil_func(temp_val,8)); 6043 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_RESUME_RED_THDOEMAr ( 6044 unit, rval)); 6045 } 6046 6047 /* C310: 6048 OP_BUFFER_SHARED_LIMIT_THDORQEQ.OP_BUFFER_SHARED_LIMIT_CELLE = C226 */ 6049 6050 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_SHARED_LIMIT_THDORQEQr (unit, &rval)); 6051 temp_val = output_port_threshold->min_grntd_tot_shr_RE_WQs_cells; 6052 soc_reg_field_set(unit, OP_BUFFER_SHARED_LIMIT_THDORQEQr, &rval, 6053 OP_BUFFER_SHARED_LIMITf, temp_val); 6054 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_SHARED_LIMIT_THDORQEQr (unit, rval)); 6055 6056 /* C312: OP_BUFFER_LIMIT_YELLOW_THDORQEQ.OP_BUFFER_LIMIT_YELLOW = 6057 =CEILING(C310/8, 1) */ 6058 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_LIMIT_YELLOW_THDORQEQr (unit, &rval)); 6059 soc_reg_field_set(unit, OP_BUFFER_LIMIT_YELLOW_THDORQEQr, &rval, 6060 OP_BUFFER_LIMIT_YELLOWf, sal_ceil_func(temp_val,8)); 6061 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_YELLOW_THDORQEQr (unit, rval)); 6062 6063 /* C314: OP_BUFFER_LIMIT_RED_THDORQEQ.OP_BUFFER_LIMIT_RED = 6064 =CEILING(C310/8, 1) */ 6065 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_LIMIT_RED_THDORQEQr (unit, &rval)); 6066 soc_reg_field_set(unit, OP_BUFFER_LIMIT_RED_THDORQEQr, &rval, 6067 OP_BUFFER_LIMIT_REDf, sal_ceil_func(temp_val,8)); 6068 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_RED_THDORQEQr (unit, rval)); 6069 6070 /* C311: OP_BUFFER_SHARED_LIMIT_RESUME_THDORQEQ. 6071 OP_BUFFER_SHARED_LIMIT_RESUME =C226-CEILING(C82/4, 1) */ 6072 temp_val -= sal_ceil_func(general_info->total_num_of_ports_excl_lpbk_olp_cpu,4); 6073 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_SHARED_LIMIT_RESUME_THDORQEQr( 6074 unit, &rval)); 6075 soc_reg_field_set(unit, OP_BUFFER_SHARED_LIMIT_RESUME_THDORQEQr, &rval, 6076 OP_BUFFER_SHARED_LIMIT_RESUMEf, temp_val); 6077 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_SHARED_LIMIT_RESUME_THDORQEQr( 6078 unit, rval)); 6079 6080 /* C313: OP_BUFFER_LIMIT_RESUME_YELLOW_THDORQEQ. 6081 OP_BUFFER_LIMIT_RESUME_YELLOW = C312-1 */ 6082 temp_val = sal_ceil_func(output_port_threshold->min_grntd_tot_shr_RE_WQs_cells , 8); 6083 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_LIMIT_RESUME_YELLOW_THDORQEQr ( 6084 unit, &rval)); 6085 soc_reg_field_set(unit, OP_BUFFER_LIMIT_RESUME_YELLOW_THDORQEQr, &rval, 6086 OP_BUFFER_LIMIT_RESUME_YELLOWf, temp_val-1); 6087 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_RESUME_YELLOW_THDORQEQr ( 6088 unit, rval)); 6089 6090 /* C315: OP_BUFFER_LIMIT_RESUME_RED_THDORQEQ. 6091 OP_BUFFER_LIMIT_RESUME_RED==C314 -1 */ 6092 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_LIMIT_RESUME_RED_THDORQEQr ( 6093 unit, &rval)); 6094 soc_reg_field_set(unit, OP_BUFFER_LIMIT_RESUME_RED_THDORQEQr, &rval, 6095 OP_BUFFER_LIMIT_RESUME_REDf, temp_val-1); 6096 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_RESUME_RED_THDORQEQr ( 6097 unit, rval)); 6098 6099 /* C317: OP_BUFFER_SHARED_LIMIT_QENTRY.OP_BUFFER_SHARED_LIMIT_QENTRY =C221*/ 6100 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_SHARED_LIMIT_QENTRYr (unit, &rval)); 6101 soc_reg_field_set(unit, OP_BUFFER_SHARED_LIMIT_QENTRYr, &rval, 6102 OP_BUFFER_SHARED_LIMIT_QENTRYf, 6103 output_port_threshold->min_grntd_tot_shr_queue_cells_EQEs); 6104 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_SHARED_LIMIT_QENTRYr (unit, rval)); 6105 6106 temp_val = output_port_threshold->min_grntd_tot_shr_queue_cells_EQEs; 6107 6108 /* C319: OP_BUFFER_LIMIT_YELLOW_QENTRY.OP_BUFFER_LIMIT_YELLOW_QENTRY 6109 = CEILING(C317/8, 1) */ 6110 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_LIMIT_YELLOW_QENTRYr(unit, &rval)); 6111 if (_soc_sb2_mmu_params.lossless_mode_d_c) { 6112 soc_reg_field_set(unit, OP_BUFFER_LIMIT_YELLOW_QENTRYr, &rval, 6113 OP_BUFFER_LIMIT_YELLOW_QENTRYf, sal_ceil_func(temp_val,8) - 1); 6114 } else { 6115 soc_reg_field_set(unit, OP_BUFFER_LIMIT_YELLOW_QENTRYr, &rval, 6116 OP_BUFFER_LIMIT_YELLOW_QENTRYf, sal_ceil_func(temp_val,8)); 6117 } 6118 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_YELLOW_QENTRYr(unit, rval)); 6119 6120 /* C321: OP_BUFFER_LIMIT_RED_QENTRY.OP_BUFFER_LIMIT_RED_QENTRY 6121 = CEILING(C317/8, 1) */ 6122 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_LIMIT_RED_QENTRYr(unit, &rval)); 6123 if (_soc_sb2_mmu_params.lossless_mode_d_c) { 6124 soc_reg_field_set(unit, OP_BUFFER_LIMIT_RED_QENTRYr, &rval, 6125 OP_BUFFER_LIMIT_RED_QENTRYf, sal_ceil_func(temp_val,8) - 1); 6126 } else { 6127 soc_reg_field_set(unit, OP_BUFFER_LIMIT_RED_QENTRYr, &rval, 6128 OP_BUFFER_LIMIT_RED_QENTRYf, sal_ceil_func(temp_val,8)); 6129 } 6130 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_RED_QENTRYr(unit, rval)); 6131 6132 /* C318: OP_BUFFER_SHARED_LIMIT_RESUME_QENTRY.OP_BUFFER_SHARED_LIMIT_RESUME_QENTRY 6133 =C224-CEILING(C82/4, 1)*C51 */ 6134 temp_val -= (sal_ceil_func(general_info->total_num_of_ports_excl_lpbk_olp_cpu,4) * 6135 _soc_sb2_mmu_params.mmu_exp_num_of_repl_per_pkt); 6136 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_SHARED_LIMIT_RESUME_QENTRYr( 6137 unit, &rval)); 6138 soc_reg_field_set(unit, OP_BUFFER_SHARED_LIMIT_RESUME_QENTRYr, 6139 &rval, 6140 OP_BUFFER_SHARED_LIMIT_RESUME_QENTRYf, temp_val); 6141 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_SHARED_LIMIT_RESUME_QENTRYr( 6142 unit, rval)); 6143 6144 /* C320 OP_BUFFER_LIMIT_RESUME_YELLOW_QENTRY.OP_BUFFER_LIMIT_RESUME_YELLOW_QENTRY 6145 =CEILING(C318/8, 1) */ 6146 SOC_IF_ERROR_RETURN( 6147 READ_OP_BUFFER_LIMIT_RESUME_YELLOW_QENTRYr(unit, &rval)); 6148 soc_reg_field_set(unit, OP_BUFFER_LIMIT_RESUME_YELLOW_QENTRYr, &rval, 6149 OP_BUFFER_LIMIT_RESUME_YELLOW_QENTRYf, 6150 sal_ceil_func(temp_val,8)); 6151 SOC_IF_ERROR_RETURN( 6152 WRITE_OP_BUFFER_LIMIT_RESUME_YELLOW_QENTRYr(unit, rval)); 6153 6154 /* C322 OP_BUFFER_LIMIT_RESUME_RED_QENTRY.OP_BUFFER_LIMIT_RESUME_RED_QENTRY 6155 =CEILING(C318/8, 1) */ 6156 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_LIMIT_RESUME_RED_QENTRYr(unit, &rval)); 6157 soc_reg_field_set(unit, OP_BUFFER_LIMIT_RESUME_RED_QENTRYr, &rval, 6158 OP_BUFFER_LIMIT_RESUME_RED_QENTRYf, 6159 sal_ceil_func(temp_val,8)); 6160 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_RESUME_RED_QENTRYr(unit, rval)); 6161 6162 /* C324 : OP_BUFFER_SHARED_LIMIT_THDORDEQ.OP_BUFFER_SHARED_LIMIT = C229 */ 6163 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_SHARED_LIMIT_THDORDEQr(unit, &rval)); 6164 soc_reg_field_set(unit,OP_BUFFER_SHARED_LIMIT_THDORDEQr,&rval, 6165 OP_BUFFER_SHARED_LIMITf, 6166 output_port_threshold->min_grntd_tot_shr_EP_redirect_queue_entry_cells); 6167 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_SHARED_LIMIT_THDORDEQr(unit, rval)); 6168 temp_val= output_port_threshold-> 6169 min_grntd_tot_shr_EP_redirect_queue_entry_cells; 6170 6171 /*C325: OP_BUFFER_SHARED_LIMIT_TRESUME_THDORDEQr. 6172 OP_BUFFER_SHARED_LIMIT_RESUMEf = =C229-4 */ 6173 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_SHARED_LIMIT_RESUME_THDORDEQr( 6174 unit, &rval)); 6175 soc_reg_field_set(unit,OP_BUFFER_SHARED_LIMIT_RESUME_THDORDEQr,&rval, 6176 OP_BUFFER_SHARED_LIMIT_RESUMEf, 6177 temp_val - 4); 6178 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_SHARED_LIMIT_RESUME_THDORDEQr( 6179 unit, rval)); 6180 6181 /* C326: OP_BUFFER_LIMIT_YELLOW_THDORDEQ.OP_BUFFER_LIMIT_YELLOW 6182 = CEILING(C324/8, 1) */ 6183 temp_val = sal_ceil_func(temp_val , 8); 6184 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_LIMIT_YELLOW_THDORDEQr(unit, &rval)); 6185 soc_reg_field_set(unit,OP_BUFFER_LIMIT_YELLOW_THDORDEQr,&rval, 6186 OP_BUFFER_LIMIT_YELLOWf, temp_val); 6187 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_YELLOW_THDORDEQr(unit, rval)); 6188 6189 /* C328: OP_BUFFER_LIMIT_RED_THDORDEQ.OP_BUFFER_LIMIT_RED 6190 = CEILING(C324/8, 1) */ 6191 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_LIMIT_RED_THDORDEQr(unit, &rval)); 6192 soc_reg_field_set(unit,OP_BUFFER_LIMIT_RED_THDORDEQr,&rval, 6193 OP_BUFFER_LIMIT_REDf, temp_val); 6194 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_RED_THDORDEQr(unit, rval)); 6195 6196 /* C327: OP_BUFFER_LIMIT_RESUME_YELLOW_THDORDEQ. 6197 OP_BUFFER_LIMIT_RESUME_YELLOW = =C326-1 */ 6198 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_LIMIT_RESUME_YELLOW_THDORDEQr( 6199 unit, &rval)); 6200 soc_reg_field_set(unit,OP_BUFFER_LIMIT_RESUME_YELLOW_THDORDEQr,&rval, 6201 OP_BUFFER_LIMIT_RESUME_YELLOWf, temp_val-1); 6202 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_RESUME_YELLOW_THDORDEQr( 6203 unit, rval)); 6204 6205 /* C329: OP_BUFFER_LIMIT_RESUME_RED_THDORDEQ. 6206 OP_BUFFER_LIMIT_RESUME_RED = =C328-1 */ 6207 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_LIMIT_RESUME_RED_THDORDEQr(unit, &rval)); 6208 soc_reg_field_set(unit,OP_BUFFER_LIMIT_RESUME_RED_THDORDEQr,&rval, 6209 OP_BUFFER_LIMIT_RESUME_REDf, temp_val-1); 6210 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_RESUME_RED_THDORDEQr(unit, rval)); 6211 } 6212 6213 SOC_PBMP_ITER (valid_port_cpu_pbmp, port) { 6214 /* 10-12, 14-16,18-20 ports have 1 PG */ 6215 if ((( port > 9) && (port < 13)) || 6216 (( port > 13) && (port < 17)) || 6217 (( port > 17) && (port < 21))) { 6218 priority_group = 0; 6219 } else { 6220 priority_group = 7; 6221 } 6222 if ((flex_port != -1) && (flex_port != port)) { 6223 continue; 6224 } 6225 sal_memset(&thdi_port_sp_config,0,sizeof(thdi_port_sp_config)); 6226 mem_idx= (port * SB2_MAX_SERVICE_POOLS) + service_pool; 6227 /* C335 : THDI_PORT_SP_CONFIG.PORT_SP_MIN_LIMIT = =$C$168 */ 6228 soc_mem_field32_set(unit, THDI_PORT_SP_CONFIGm, 6229 &thdi_port_sp_config, PORT_SP_MIN_LIMITf, 6230 input_port_threshold->min_int_buff_cells_for_a_port); 6231 6232 /* C336 : THDI_PORT_SP_CONFIG.PORT_SP_MAX_LIMIT = =$C$269 i.e. =$C$186 */ 6233 soc_mem_field32_set(unit, THDI_PORT_SP_CONFIGm, 6234 &thdi_port_sp_config, PORT_SP_MAX_LIMITf, 6235 input_port_threshold->total_shared_ing_buff_pool); 6236 6237 /* C337 : PORT_MAX_PKT_SIZE.PORT_MAX_PKT_SIZE = =$C$72 */ 6238 SOC_IF_ERROR_RETURN(READ_PORT_MAX_PKT_SIZEr (unit, port, &rval)); 6239 soc_reg_field_set(unit, PORT_MAX_PKT_SIZEr, &rval, 6240 PORT_MAX_PKT_SIZEf, 6241 general_info->max_packet_size_in_cells); 6242 SOC_IF_ERROR_RETURN(WRITE_PORT_MAX_PKT_SIZEr (unit, port, rval)); 6243 6244 /* C338: THDI_PORT_SP_CONFIG.PORT_SP_RESUME_LIMIT = =C336-2*$C$76 */ 6245 soc_mem_field32_set(unit, THDI_PORT_SP_CONFIGm, 6246 &thdi_port_sp_config, PORT_SP_RESUME_LIMITf, 6247 input_port_threshold->total_shared_ing_buff_pool - 6248 (2 * general_info->ether_mtu_cells_for_int_buff)); 6249 6250 SOC_IF_ERROR_RETURN (soc_mem_write( 6251 unit, THDI_PORT_SP_CONFIGm, MEM_BLOCK_ALL, 6252 mem_idx, &thdi_port_sp_config)); 6253 sal_memset(&thdi_port_pg_config,0,sizeof(thdi_port_pg_config)); 6254 mem_idx= (port * SB2_MAX_PRIORITY_GROUPS) + priority_group; 6255 6256 /* C339: THDI_PORT_PG_CONFIG.PG_MIN_LIMIT (PG0) = =$C$156 */ 6257 soc_mem_field32_set(unit, THDI_PORT_PG_CONFIGm, 6258 &thdi_port_pg_config, PG_MIN_LIMITf, 6259 input_port_threshold->min_int_buff_cells_per_PG); 6260 6261 /* C340: THDI_PORT_PG_CONFIG.PG_SHARED_LIMIT 6262 =IF($C$14, $C$61, $C$269)*/ 6263 if (_soc_sb2_mmu_params.lossless_mode_d_c) { 6264 temp_val = _soc_sb2_mmu_params.mmu_ing_pg_dyn_thd_param; 6265 } else { 6266 temp_val = input_port_threshold->total_shared_ing_buff_pool; 6267 } 6268 soc_mem_field32_set(unit, THDI_PORT_PG_CONFIGm, 6269 &thdi_port_pg_config, PG_SHARED_LIMITf, temp_val); 6270 6271 /* C341: THDI_PORT_PG_CONFIG.PG_RESET_OFFSET = 2*$C$76 */ 6272 soc_mem_field32_set(unit, THDI_PORT_PG_CONFIGm, 6273 &thdi_port_pg_config, PG_RESET_OFFSETf, 6274 (2 * general_info->ether_mtu_cells_for_int_buff)); 6275 6276 /* C342: THDI_PORT_PG_CONFIG.PG_RESET_FLOOR = 0 */ 6277 soc_mem_field32_set(unit, THDI_PORT_PG_CONFIGm, 6278 &thdi_port_pg_config, PG_RESET_FLOORf, 0); 6279 6280 /* C343: THDI_PORT_PG_CONFIG.PG_SHARED_DYNAMIC= =IF($C$14, 1, 0) */ 6281 if (_soc_sb2_mmu_params.lossless_mode_d_c) { 6282 temp_val = 1; 6283 } else { 6284 temp_val = 0; 6285 } 6286 soc_mem_field32_set(unit, THDI_PORT_PG_CONFIGm, 6287 &thdi_port_pg_config, PG_SHARED_DYNAMICf,temp_val); 6288 6289 /* C344: THDI_PORT_PG_CONFIG.PG_HDRM_LIMIT= 6290 For Ge:$C125 For Hg:$C115 For Cpu:$C145 */ 6291 if (IS_CPU_PORT(unit, port)) { 6292 temp_val = input_port_threshold->hdrm_int_buff_cells_for_cpu_port; 6293 } else if (IS_GE_PORT(unit, port) || IS_LB_PORT(unit,port)) { 6294 temp_val = input_port_threshold->hdrm_int_buff_cells_for_1G_PG; 6295 } else if (IS_HG_PORT(unit, port) || IS_XE_PORT(unit,port) ) { 6296 temp_val = input_port_threshold->hdrm_int_buff_cells_for_10G_PG; 6297 } 6298 soc_mem_field32_set(unit, THDI_PORT_PG_CONFIGm, 6299 &thdi_port_pg_config, PG_HDRM_LIMITf,temp_val); 6300 6301 /* C345 : THDI_PORT_PG_CONFIG.PG_GBL_HDRM_EN = for lossy=1 else 0 */ 6302 soc_mem_field32_set(unit, THDI_PORT_PG_CONFIGm, 6303 &thdi_port_pg_config, PG_GBL_HDRM_ENf ,1); 6304 6305 /* C346: THDI_PORT_PG_CONFIG.SP_SHARED_MAX_ENABLE = 6306 For Ge:1 For Hg,Cpu: Ge Value only!!! */ 6307 6308 soc_mem_field32_set(unit, THDI_PORT_PG_CONFIGm, 6309 &thdi_port_pg_config, SP_SHARED_MAX_ENABLEf ,1); 6310 6311 /* C347: THDI_PORT_PG_CONFIG.SP_MIN_PG_ENABLE = 6312 For Ge:1 For Hg,Cpu: Ge Value only!!! */ 6313 soc_mem_field32_set(unit, THDI_PORT_PG_CONFIGm, 6314 &thdi_port_pg_config, SP_MIN_PG_ENABLEf ,1); 6315 6316 SOC_IF_ERROR_RETURN (soc_mem_write( 6317 unit, THDI_PORT_PG_CONFIGm, MEM_BLOCK_ALL, 6318 mem_idx, &thdi_port_pg_config)); 6319 /* C348 PORT_PG_SPID.PG[0..7]_SPID = 0 */ 6320 6321 if (_soc_sb2_mmu_params.extbuf_used_d_c) { 6322 sal_memset(&thdiext_thdi_port_sp_config,0, 6323 sizeof(thdiext_thdi_port_sp_config)); 6324 mem_idx= (port * SB2_MAX_SERVICE_POOLS) + service_pool; 6325 /* C350: THDIEXT_THDI_PORT_SP_CONFIG.PORT_SP_MIN_LIMIT 6326 =IF(C17=0, "NA",C170) */ 6327 soc_mem_field32_set(unit, THDIEXT_THDI_PORT_SP_CONFIGm, 6328 &thdiext_thdi_port_sp_config, PORT_SP_MIN_LIMITf, 6329 input_port_threshold->min_ext_buff_cells_for_a_port); 6330 6331 /* C351: THDIEXT_THDI_PORT_SP_CONFIG.PORT_SP_MAX_LIMIT = 6332 =IF(C17=0, "NA", C188) */ 6333 soc_mem_field32_set(unit, THDIEXT_THDI_PORT_SP_CONFIGm, 6334 &thdiext_thdi_port_sp_config, PORT_SP_MAX_LIMITf, 6335 input_port_threshold->total_shared_ext_buff); 6336 6337 /* C352: THDIEXT_PORT_MAX_PKT_SIZE.PORT_MAX_PKT_SIZE 6338 =IF(C17=0, "NA", CEILING(C72/C103, 1)) */ 6339 SOC_IF_ERROR_RETURN(READ_THDIEXT_PORT_MAX_PKT_SIZEr ( 6340 unit, port, &rval)); 6341 soc_reg_field_set(unit, THDIEXT_PORT_MAX_PKT_SIZEr, &rval, 6342 PORT_MAX_PKT_SIZEf, 6343 sal_ceil_func(general_info->max_packet_size_in_cells, 6344 general_info->ratio_of_ext_buff_to_int_buff_size)); 6345 SOC_IF_ERROR_RETURN(WRITE_THDIEXT_PORT_MAX_PKT_SIZEr ( 6346 unit, port, rval)); 6347 6348 /* C353: THDIEXT_THDI_PORT_SP_CONFIG.PORT_SP_RESUME_LIMIT = 6349 =IF(C17=0, "NA", C351-2*$C$77) */ 6350 soc_mem_field32_set(unit, THDIEXT_THDI_PORT_SP_CONFIGm, 6351 &thdiext_thdi_port_sp_config, PORT_SP_RESUME_LIMITf, 6352 input_port_threshold->total_shared_ext_buff - 6353 (2 * general_info->ether_mtu_cells_for_ext_buff)); 6354 SOC_IF_ERROR_RETURN (soc_mem_write(unit, 6355 THDIEXT_THDI_PORT_SP_CONFIGm, MEM_BLOCK_ALL, 6356 mem_idx, &thdiext_thdi_port_sp_config)); 6357 sal_memset(&thdiext_thdi_port_pg_config,0, 6358 sizeof(thdiext_thdi_port_pg_config)); 6359 mem_idx= (port * SB2_MAX_PRIORITY_GROUPS) + priority_group; 6360 /* C354: THDIEXT_THDI_PORT_PG_CONFIG.PG_MIN_LIMIT(PG0) 6361 =IF(C17=0, "NA", C158) */ 6362 soc_mem_field32_set(unit, THDIEXT_THDI_PORT_PG_CONFIGm, 6363 &thdiext_thdi_port_pg_config, PG_MIN_LIMITf, 6364 input_port_threshold->min_ext_buff_cells_per_PG); 6365 6366 /* C355: THDIEXT_THDI_PORT_PG_CONFIG.PG_SHARED_LIMIT = 6367 =IF(C17=0, "NA", IF($C$14, $C$61, $C$188)) */ 6368 if (_soc_sb2_mmu_params.lossless_mode_d_c) { 6369 temp_val = _soc_sb2_mmu_params.mmu_ing_pg_dyn_thd_param; 6370 } else { 6371 temp_val = input_port_threshold->total_shared_ext_buff;; 6372 } 6373 soc_mem_field32_set(unit, THDIEXT_THDI_PORT_PG_CONFIGm, 6374 &thdiext_thdi_port_pg_config, 6375 PG_SHARED_LIMITf, temp_val); 6376 6377 /* C356: THDIEXT_THDI_PORT_PG_CONFIG.PG_RESET_OFFSET 6378 =IF(C17=0, "NA", 2*C77)*/ 6379 soc_mem_field32_set(unit, THDIEXT_THDI_PORT_PG_CONFIGm, 6380 &thdiext_thdi_port_pg_config, PG_RESET_OFFSETf, 6381 (2 * general_info->ether_mtu_cells_for_ext_buff)); 6382 6383 /* C357: THDI_PORT_PG_CONFIG.PG_RESET_FLOOR = 0 */ 6384 soc_mem_field32_set(unit, THDIEXT_THDI_PORT_PG_CONFIGm, 6385 &thdiext_thdi_port_pg_config, PG_RESET_FLOORf, 0); 6386 6387 /* C358: THDIEXT_THDI_PORT_PG_CONFIG.PG_SHARED_DYNAMIC= 6388 IF($C$14, 1, 0) */ 6389 if (_soc_sb2_mmu_params.lossless_mode_d_c) { 6390 temp_val = 1; 6391 } else { 6392 temp_val = 0; 6393 } 6394 soc_mem_field32_set(unit, THDIEXT_THDI_PORT_PG_CONFIGm, 6395 &thdiext_thdi_port_pg_config, PG_SHARED_DYNAMICf, 6396 temp_val); 6397 6398 /* C359: THDIEXT_THDI_PORT_PG_CONFIG.PG_HDRM_LIMIT 6399 For Ge:$C127 For Hg:$C117 For Cpu:$C147 */ 6400 if (IS_CPU_PORT(unit, port)) { 6401 temp_val = input_port_threshold-> 6402 hdrm_ext_buff_cells_for_cpu_port; 6403 } else if (IS_GE_PORT(unit, port) || IS_LB_PORT(unit,port)) { 6404 temp_val = input_port_threshold->hdrm_ext_buff_cells_for_1G_PG; 6405 } else if (IS_HG_PORT(unit, port) || IS_XE_PORT(unit, port)) { 6406 temp_val= input_port_threshold->hdrm_ext_buff_cells_for_10G_PG; 6407 } 6408 soc_mem_field32_set(unit, THDIEXT_THDI_PORT_PG_CONFIGm, 6409 &thdiext_thdi_port_pg_config, PG_HDRM_LIMITf,temp_val); 6410 6411 /* C360: THDIEXT_THDI_PORT_PG_CONFIG.PG_GBL_HDRM_EN = 6412 for lossy=1 else 0 6413 For Packed : 0 6414 =IF(C17=0, "NA", IF(C12=0, 1, 0))*/ 6415 if (_soc_sb2_mmu_params.packing_mode_d_c) { 6416 temp_val = 0; 6417 } else { 6418 temp_val = 1; 6419 } 6420 soc_mem_field32_set(unit, THDIEXT_THDI_PORT_PG_CONFIGm, 6421 &thdiext_thdi_port_pg_config, PG_GBL_HDRM_ENf , 6422 temp_val); 6423 /* C361: THDIEXT_THDI_PORT_PG_CONFIG.SP_SHARED_MAX_ENABLE */ 6424 soc_mem_field32_set(unit, THDIEXT_THDI_PORT_PG_CONFIGm, 6425 &thdiext_thdi_port_pg_config, SP_SHARED_MAX_ENABLEf ,1); 6426 6427 /* C362: THDIEXT_THDI_PORT_PG_CONFIG.SP_MIN_PG_ENABLE */ 6428 soc_mem_field32_set(unit, THDIEXT_THDI_PORT_PG_CONFIGm, 6429 &thdiext_thdi_port_pg_config, SP_MIN_PG_ENABLEf ,1); 6430 SOC_IF_ERROR_RETURN (soc_mem_write( 6431 unit, THDIEXT_THDI_PORT_PG_CONFIGm, MEM_BLOCK_ALL, 6432 mem_idx, &thdiext_thdi_port_pg_config)); 6433 } else { 6434 sal_memset(&thdiext_thdi_port_pg_config,0, 6435 sizeof(thdiext_thdi_port_pg_config)); 6436 mem_idx= (port * SB2_MAX_PRIORITY_GROUPS) + priority_group; 6437 6438 6439 /* C361: THDIEXT_THDI_PORT_PG_CONFIG.SP_SHARED_MAX_ENABLE */ 6440 soc_mem_field32_set(unit, THDIEXT_THDI_PORT_PG_CONFIGm, 6441 &thdiext_thdi_port_pg_config, SP_SHARED_MAX_ENABLEf ,1); 6442 6443 /* C362: THDIEXT_THDI_PORT_PG_CONFIG.SP_MIN_PG_ENABLE */ 6444 soc_mem_field32_set(unit, THDIEXT_THDI_PORT_PG_CONFIGm, 6445 &thdiext_thdi_port_pg_config, SP_MIN_PG_ENABLEf ,1); 6446 SOC_IF_ERROR_RETURN (soc_mem_write( 6447 unit, THDIEXT_THDI_PORT_PG_CONFIGm, MEM_BLOCK_ALL, 6448 mem_idx, &thdiext_thdi_port_pg_config)); 6449 } 6450 6451 if (_soc_sb2_mmu_params.extbuf_used_d_c) { 6452 sal_memset(&thdiema_thdi_port_sp_config,0, 6453 sizeof(thdiema_thdi_port_sp_config)); 6454 mem_idx= (port * SB2_MAX_SERVICE_POOLS) + service_pool; 6455 /* C365: THDIEMA_THDI_PORT_SP_CONFIG.PORT_SP_MIN_LIMIT 6456 =IF(C17=0, "NA", C169)*/ 6457 soc_mem_field32_set(unit, THDIEMA_THDI_PORT_SP_CONFIGm, 6458 &thdiema_thdi_port_sp_config, PORT_SP_MIN_LIMITf, 6459 input_port_threshold->min_int_buff_ema_pool_cells_for_a_port); 6460 6461 /* C366: THDIEMA_THDI_PORT_SP_CONFIG.PORT_SP_MAX_LIMIT = 6462 =IF(C17=0, "NA", C187) */ 6463 soc_mem_field32_set(unit, THDIEMA_THDI_PORT_SP_CONFIGm, 6464 &thdiema_thdi_port_sp_config, PORT_SP_MAX_LIMITf, 6465 input_port_threshold->total_shared_EMA_buff); 6466 6467 /* C367: THDIEMA_PORT_MAX_PKT_SIZE.PORT_MAX_PKT_SIZE 6468 =IF(C17=0, "NA", $C$72)*/ 6469 SOC_IF_ERROR_RETURN(READ_THDIEMA_PORT_MAX_PKT_SIZEr ( 6470 unit, port, &rval)); 6471 soc_reg_field_set(unit, THDIEMA_PORT_MAX_PKT_SIZEr, &rval, 6472 PORT_MAX_PKT_SIZEf, 6473 general_info->max_packet_size_in_cells); 6474 SOC_IF_ERROR_RETURN(WRITE_THDIEMA_PORT_MAX_PKT_SIZEr ( 6475 unit, port, rval)); 6476 /* C368: THDIEMA_THDI_PORT_SP_CONFIG.PORT_SP_RESUME_LIMIT = 6477 =IF(C17=0, "NA", C366-2*$C$76) */ 6478 soc_mem_field32_set(unit, THDIEMA_THDI_PORT_SP_CONFIGm, 6479 &thdiema_thdi_port_sp_config, PORT_SP_RESUME_LIMITf, 6480 input_port_threshold->total_shared_EMA_buff - 6481 (2 * general_info->ether_mtu_cells_for_int_buff)); 6482 SOC_IF_ERROR_RETURN(soc_mem_write(unit, 6483 THDIEMA_THDI_PORT_SP_CONFIGm, MEM_BLOCK_ALL, 6484 mem_idx, &thdiema_thdi_port_sp_config)); 6485 sal_memset(&thdiema_thdi_port_pg_config,0, 6486 sizeof(thdiema_thdi_port_pg_config)); 6487 mem_idx= (port * SB2_MAX_PRIORITY_GROUPS) + priority_group; 6488 6489 /* C369: THDIEMA_THDI_PORT_PG_CONFIG.PG_MIN_LIMIT(PG0) 6490 =IF(C17=0, "NA", C157) */ 6491 soc_mem_field32_set(unit, THDIEMA_THDI_PORT_PG_CONFIGm, 6492 &thdiema_thdi_port_pg_config, PG_MIN_LIMITf, 6493 input_port_threshold->min_int_buff_ema_pool_cells_per_PG); 6494 6495 /* C370: THDIEMA_THDI_PORT_PG_CONFIG.PG_SHARED_LIMIT = 6496 =IF(C17=0, "NA", C187) */ 6497 temp_val = input_port_threshold->total_shared_EMA_buff; 6498 soc_mem_field32_set(unit, THDIEMA_THDI_PORT_PG_CONFIGm, 6499 &thdiema_thdi_port_pg_config, 6500 PG_SHARED_LIMITf, temp_val); 6501 6502 /* C371: THDIEMA_THDI_PORT_PG_CONFIG.PG_RESET_OFFSET 6503 =IF(C17=0, "NA", 2*C76) */ 6504 soc_mem_field32_set(unit, THDIEMA_THDI_PORT_PG_CONFIGm, 6505 &thdiema_thdi_port_pg_config, PG_RESET_OFFSETf, 6506 (2 * general_info->ether_mtu_cells_for_int_buff)); 6507 6508 /* C372: THDIEMA_PORT_PG_CONFIG.PG_RESET_FLOOR 6509 =IF(C17=0, "NA", 0)*/ 6510 soc_mem_field32_set(unit, THDIEMA_THDI_PORT_PG_CONFIGm, 6511 &thdiema_thdi_port_pg_config, PG_RESET_FLOORf, 0); 6512 6513 /* C373: THDIEMA_THDI_PORT_PG_CONFIG.PG_SHARED_DYNAMIC= 6514 =IF(C17=0, "NA", IF($C$14, 1, 0)) */ 6515 if (_soc_sb2_mmu_params.lossless_mode_d_c) { 6516 temp_val = 1; 6517 } else { 6518 temp_val = 0; 6519 } 6520 soc_mem_field32_set(unit, THDIEMA_THDI_PORT_PG_CONFIGm, 6521 &thdiema_thdi_port_pg_config, PG_SHARED_DYNAMICf, 6522 temp_val); 6523 6524 /* C374: THDIEMA_THDI_PORT_PG_CONFIG.PG_HDRM_LIMIT 6525 For Ge:$C126 For Hg:$C116 For Cpu:$C146 */ 6526 if (IS_CPU_PORT(unit, port)) { 6527 temp_val = input_port_threshold-> 6528 hdrm_ema_buff_cells_for_cpu_port; 6529 } else if (IS_GE_PORT(unit, port) || IS_LB_PORT(unit,port)) { 6530 temp_val = input_port_threshold->hdrm_ema_buff_cells_for_1G_PG; 6531 } else if (IS_HG_PORT(unit, port) || IS_XE_PORT(unit,port)) { 6532 temp_val= input_port_threshold->hdrm_ema_buff_cells_for_10G_PG; 6533 } 6534 soc_mem_field32_set(unit, THDIEMA_THDI_PORT_PG_CONFIGm, 6535 &thdiema_thdi_port_pg_config, PG_HDRM_LIMITf,temp_val); 6536 6537 /* C375: THDIEMA_THDI_PORT_PG_CONFIG.PG_GBL_HDRM_EN = 6538 for lossy=1 else 0 */ 6539 temp_val = 1; 6540 soc_mem_field32_set(unit, THDIEMA_THDI_PORT_PG_CONFIGm, 6541 &thdiema_thdi_port_pg_config, PG_GBL_HDRM_ENf , 6542 temp_val); 6543 /* C376: THDIEMA_THDI_PORT_PG_CONFIG.SP_SHARED_MAX_ENABLE */ 6544 soc_mem_field32_set(unit, THDIEMA_THDI_PORT_PG_CONFIGm, 6545 &thdiema_thdi_port_pg_config, SP_SHARED_MAX_ENABLEf ,1); 6546 6547 /* C377: THDIEMA_THDI_PORT_PG_CONFIG.SP_MIN_PG_ENABLE */ 6548 soc_mem_field32_set(unit, THDIEMA_THDI_PORT_PG_CONFIGm, 6549 &thdiema_thdi_port_pg_config, SP_MIN_PG_ENABLEf ,1); 6550 SOC_IF_ERROR_RETURN (soc_mem_write( 6551 unit, THDIEMA_THDI_PORT_PG_CONFIGm, MEM_BLOCK_ALL, 6552 mem_idx, &thdiema_thdi_port_pg_config)); 6553 sal_memset(&thdirqe_thdi_port_sp_config , 0, 6554 sizeof(thdirqe_thdi_port_sp_config)); 6555 } else { 6556 sal_memset(&thdiema_thdi_port_pg_config,0, 6557 sizeof(thdiema_thdi_port_pg_config)); 6558 mem_idx= (port * SB2_MAX_PRIORITY_GROUPS) + priority_group; 6559 /* C376: THDIEMA_THDI_PORT_PG_CONFIG.SP_SHARED_MAX_ENABLE */ 6560 sal_memset(&thdiema_thdi_port_pg_config,0, 6561 sizeof(thdiema_thdi_port_pg_config)); 6562 soc_mem_field32_set(unit, THDIEMA_THDI_PORT_PG_CONFIGm, 6563 &thdiema_thdi_port_pg_config, SP_SHARED_MAX_ENABLEf ,1); 6564 6565 /* C377: THDIEMA_THDI_PORT_PG_CONFIG.SP_MIN_PG_ENABLE */ 6566 soc_mem_field32_set(unit, THDIEMA_THDI_PORT_PG_CONFIGm, 6567 &thdiema_thdi_port_pg_config, SP_MIN_PG_ENABLEf ,1); 6568 SOC_IF_ERROR_RETURN (soc_mem_write( 6569 unit, THDIEMA_THDI_PORT_PG_CONFIGm, MEM_BLOCK_ALL, 6570 mem_idx, &thdiema_thdi_port_pg_config)); 6571 } 6572 sal_memset(&thdirqe_thdi_port_sp_config , 0, 6573 sizeof(thdirqe_thdi_port_sp_config)); 6574 6575 mem_idx= (port * SB2_MAX_SERVICE_POOLS) + service_pool; 6576 /* C380: THDIRQE_THDI_PORT_SP_CONFIG.PORT_SP_MIN_LIMIT = $C$171 */ 6577 soc_mem_field32_set(unit, THDIRQE_THDI_PORT_SP_CONFIGm, 6578 &thdirqe_thdi_port_sp_config, PORT_SP_MIN_LIMITf, 6579 input_port_threshold->min_RE_WQEs_pkts_for_a_port); 6580 6581 /* C381: THDIRQE_THDI_PORT_SP_CONFIG.PORT_SP_MAX_LIMIT = $C$189 */ 6582 soc_mem_field32_set(unit, THDIRQE_THDI_PORT_SP_CONFIGm, 6583 &thdirqe_thdi_port_sp_config, PORT_SP_MAX_LIMITf, 6584 input_port_threshold->total_shared_RE_WQEs_buff); 6585 6586 /* C382: THDIRQE_THDI_PORT_SP_CONFIG.PORT_SP_RESUME_LIMIT = 6587 =C381-2 */ 6588 soc_mem_field32_set(unit, THDIRQE_THDI_PORT_SP_CONFIGm, 6589 &thdirqe_thdi_port_sp_config, PORT_SP_RESUME_LIMITf, 6590 input_port_threshold->total_shared_RE_WQEs_buff - 2); 6591 SOC_IF_ERROR_RETURN(soc_mem_write( 6592 unit, THDIRQE_THDI_PORT_SP_CONFIGm, MEM_BLOCK_ALL, 6593 mem_idx, &thdirqe_thdi_port_sp_config)); 6594 6595 sal_memset(&thdirqe_thdi_port_pg_config , 0, 6596 sizeof(thdirqe_thdi_port_pg_config)); 6597 mem_idx= (port * SB2_MAX_PRIORITY_GROUPS) + priority_group; 6598 /* C383: THDIRQE_THDI_PORT_PG_CONFIG.PG_MIN_LIMIT(PG0) = =$C$159 */ 6599 temp_val = input_port_threshold->min_RE_WQEs_pkt_per_PG; 6600 soc_mem_field32_set(unit, THDIRQE_THDI_PORT_PG_CONFIGm, 6601 &thdirqe_thdi_port_pg_config, PG_MIN_LIMITf,temp_val); 6602 6603 /* C384: THDIRQE_THDI_PORT_PG_CONFIG.PG_SHARED_LIMIT = 6604 =IF($C$14, $C$61, $C$189) */ 6605 if (_soc_sb2_mmu_params.lossless_mode_d_c) { 6606 temp_val = _soc_sb2_mmu_params.mmu_ing_pg_dyn_thd_param; 6607 } else { 6608 temp_val = input_port_threshold->total_shared_RE_WQEs_buff; 6609 } 6610 soc_mem_field32_set(unit, THDIRQE_THDI_PORT_PG_CONFIGm, 6611 &thdirqe_thdi_port_pg_config, 6612 PG_SHARED_LIMITf, temp_val); 6613 6614 /* C385: THDIRQE_THDI_PORT_PG_CONFIG.PG_RESET_OFFSET = 2 */ 6615 soc_mem_field32_set(unit, THDIRQE_THDI_PORT_PG_CONFIGm, 6616 &thdirqe_thdi_port_pg_config, PG_RESET_OFFSETf,2); 6617 6618 /* C386: THDIRQE_THDI_PORT_PG_CONFIG.PG_RESET_FLOOR = 0 */ 6619 soc_mem_field32_set(unit, THDIRQE_THDI_PORT_PG_CONFIGm, 6620 &thdirqe_thdi_port_pg_config, PG_RESET_FLOORf, 0); 6621 6622 /* C387: THDIRQE_THDI_PORT_PG_CONFIG.PG_SHARED_DYNAMIC= 6623 =IF($C$14, 1, 0) */ 6624 if (_soc_sb2_mmu_params.lossless_mode_d_c) { 6625 temp_val = 1; 6626 } else { 6627 temp_val = 0; 6628 } 6629 soc_mem_field32_set(unit, THDIRQE_THDI_PORT_PG_CONFIGm, 6630 &thdirqe_thdi_port_pg_config, PG_SHARED_DYNAMICf, 6631 temp_val); 6632 6633 /* C388: THDIRQE_THDI_PORT_PG_CONFIG.PG_HDRM_LIMIT 6634 For Ge:$C128 For Hg:$C118 For Cpu:$C148 */ 6635 if (IS_CPU_PORT(unit, port)) { 6636 temp_val = input_port_threshold->hdrm_RE_WQEs_pkts_for_cpu_port; 6637 } else if (IS_GE_PORT(unit, port) || IS_LB_PORT(unit,port)) { 6638 temp_val = input_port_threshold->hdrm_RE_WQEs_pkts_for_1G_PG; 6639 } else if (IS_HG_PORT(unit, port) || IS_XE_PORT(unit, port)) { 6640 temp_val= input_port_threshold->hdrm_RE_WQEs_pkts_for_10G_PG; 6641 } 6642 soc_mem_field32_set(unit, THDIRQE_THDI_PORT_PG_CONFIGm, 6643 &thdirqe_thdi_port_pg_config, PG_HDRM_LIMITf,temp_val); 6644 6645 /* C389: THDIRQE_THDI_PORT_PG_CONFIG.PG_GBL_HDRM_EN = 0 */ 6646 temp_val = 0; 6647 soc_mem_field32_set(unit, THDIRQE_THDI_PORT_PG_CONFIGm, 6648 &thdirqe_thdi_port_pg_config, PG_GBL_HDRM_ENf , 6649 temp_val); 6650 6651 /* C390: THDIRQE_THDI_PORT_PG_CONFIG.SP_SHARED_MAX_ENABLE = 6652 For Ge:1 For Hg,Cpu: Ge Value only!!! */ 6653 soc_mem_field32_set(unit, THDIRQE_THDI_PORT_PG_CONFIGm, 6654 &thdirqe_thdi_port_pg_config, SP_SHARED_MAX_ENABLEf ,1); 6655 6656 /* C391: THDIRQE_THDI_PORT_PG_CONFIG.SP_MIN_PG_ENABLE = 6657 For Ge:1 For Hg,Cpu: Ge Value only!!! */ 6658 soc_mem_field32_set(unit, THDIRQE_THDI_PORT_PG_CONFIGm, 6659 &thdirqe_thdi_port_pg_config, SP_MIN_PG_ENABLEf ,1); 6660 6661 SOC_IF_ERROR_RETURN(soc_mem_write(unit, THDIRQE_THDI_PORT_PG_CONFIGm, 6662 MEM_BLOCK_ALL, mem_idx, &thdirqe_thdi_port_pg_config)); 6663 6664 sal_memset(&thdiqen_thdi_port_sp_config,0, 6665 sizeof(thdiqen_thdi_port_sp_config)); 6666 mem_idx= (port * SB2_MAX_SERVICE_POOLS) + service_pool; 6667 6668 /* C394: THDIQEN_THDI_PORT_SP_CONFIG.PORT_SP_MIN_LIMIT = $C$172 */ 6669 soc_mem_field32_set(unit, THDIQEN_THDI_PORT_SP_CONFIGm, 6670 &thdiqen_thdi_port_sp_config, PORT_SP_MIN_LIMITf, 6671 input_port_threshold->min_EQEs_pkts_for_a_port); 6672 6673 /* C395: THDIQEN_THDI_PORT_SP_CONFIG.PORT_SP_MAX_LIMIT = $C$190 */ 6674 soc_mem_field32_set(unit, THDIQEN_THDI_PORT_SP_CONFIGm, 6675 &thdiqen_thdi_port_sp_config, PORT_SP_MAX_LIMITf, 6676 input_port_threshold->total_shared_EQEs_buff); 6677 6678 /* C396: THDIQEN_THDI_PORT_SP_CONFIG.PORT_SP_RESUME_LIMIT = 6679 ==C395-2*C51 */ 6680 soc_mem_field32_set(unit, THDIQEN_THDI_PORT_SP_CONFIGm, 6681 &thdiqen_thdi_port_sp_config, PORT_SP_RESUME_LIMITf, 6682 input_port_threshold->total_shared_EQEs_buff - 6683 (2 * _soc_sb2_mmu_params.mmu_exp_num_of_repl_per_pkt)); 6684 SOC_IF_ERROR_RETURN(soc_mem_write(unit, 6685 THDIQEN_THDI_PORT_SP_CONFIGm, MEM_BLOCK_ALL, 6686 mem_idx, &thdiqen_thdi_port_sp_config)); 6687 6688 sal_memset(&thdiqen_thdi_port_pg_config,0, 6689 sizeof(thdiqen_thdi_port_pg_config)); 6690 mem_idx= (port * SB2_MAX_PRIORITY_GROUPS) + priority_group; 6691 /* C397: THDIQEN_THDI_PORT_PG_CONFIG.PG_MIN_LIMIT(PG0) = 6692 =$C$160 */ 6693 soc_mem_field32_set(unit, THDIQEN_THDI_PORT_PG_CONFIGm, 6694 &thdiqen_thdi_port_pg_config, PG_MIN_LIMITf, 6695 input_port_threshold->min_EQEs_pkt_per_PG); 6696 6697 6698 /* C398: THDIQEN_THDI_PORT_PG_CONFIG.PG_SHARED_LIMIT = 6699 =IF($C$14, $C$61, $C$190) */ 6700 if (_soc_sb2_mmu_params.lossless_mode_d_c) { 6701 temp_val = _soc_sb2_mmu_params.mmu_ing_pg_dyn_thd_param; 6702 } else { 6703 temp_val = input_port_threshold->total_shared_EQEs_buff; 6704 } 6705 soc_mem_field32_set(unit, THDIQEN_THDI_PORT_PG_CONFIGm, 6706 &thdiqen_thdi_port_pg_config, 6707 PG_SHARED_LIMITf, temp_val); 6708 6709 /* C399: THDIQEN_THDI_PORT_PG_CONFIG.PG_RESET_OFFSET = =2*C51 */ 6710 soc_mem_field32_set(unit, THDIQEN_THDI_PORT_PG_CONFIGm, 6711 &thdiqen_thdi_port_pg_config, PG_RESET_OFFSETf, 6712 2 * _soc_sb2_mmu_params.mmu_exp_num_of_repl_per_pkt); 6713 6714 /* C400: THDIQEN_THDI_PORT_PG_CONFIG.PG_RESET_FLOOR = 0 */ 6715 soc_mem_field32_set(unit, THDIQEN_THDI_PORT_PG_CONFIGm, 6716 &thdiqen_thdi_port_pg_config, PG_RESET_FLOORf, 0); 6717 6718 /* C401: THDIQEN_THDI_PORT_PG_CONFIG.PG_SHARED_DYNAMIC= 0 */ 6719 6720 if (_soc_sb2_mmu_params.lossless_mode_d_c) { 6721 temp_val = 1; 6722 } else { 6723 temp_val = 0; 6724 } 6725 soc_mem_field32_set(unit, THDIQEN_THDI_PORT_PG_CONFIGm, 6726 &thdiqen_thdi_port_pg_config, PG_SHARED_DYNAMICf, 6727 temp_val); 6728 6729 /* C402: THDIQEN_THDI_PORT_PG_CONFIG.PG_HDRM_LIMIT 6730 For Ge:$C129 For Hg:$C119 For Cpu:$C149 */ 6731 if (IS_CPU_PORT(unit, port)) { 6732 temp_val = input_port_threshold->hdrm_EQEs_pkts_for_cpu_port; 6733 } else if (IS_GE_PORT(unit, port) || IS_LB_PORT(unit,port)) { 6734 temp_val = input_port_threshold->hdrm_EQEs_pkts_for_1G_PG; 6735 } else if (IS_HG_PORT(unit, port) || IS_XE_PORT(unit, port)) { 6736 temp_val= input_port_threshold->hdrm_EQEs_pkts_for_10G_PG; 6737 } 6738 soc_mem_field32_set(unit, THDIQEN_THDI_PORT_PG_CONFIGm, 6739 &thdiqen_thdi_port_pg_config, PG_HDRM_LIMITf,temp_val); 6740 6741 /* C403: THDIQEN_THDI_PORT_PG_CONFIG.PG_GBL_HDRM_EN =0 */ 6742 temp_val = 0; 6743 soc_mem_field32_set(unit, THDIQEN_THDI_PORT_PG_CONFIGm, 6744 &thdiqen_thdi_port_pg_config, PG_GBL_HDRM_ENf , 6745 temp_val); 6746 6747 /* C404: THDIQEN_THDI_PORT_PG_CONFIG.SP_SHARED_MAX_ENABLE = 6748 For Ge:1 For Hg,Cpu: Ge Value only!!! */ 6749 soc_mem_field32_set(unit, THDIQEN_THDI_PORT_PG_CONFIGm, 6750 &thdiqen_thdi_port_pg_config, SP_SHARED_MAX_ENABLEf ,1); 6751 6752 /* C405: THDIQEN_THDI_PORT_PG_CONFIG.SP_MIN_PG_ENABLE = 6753 For Ge:1 For Hg,Cpu: Ge Value only!!! */ 6754 soc_mem_field32_set(unit, THDIQEN_THDI_PORT_PG_CONFIGm, 6755 &thdiqen_thdi_port_pg_config, SP_MIN_PG_ENABLEf ,1); 6756 SOC_IF_ERROR_RETURN(soc_mem_write( unit, THDIQEN_THDI_PORT_PG_CONFIGm, 6757 MEM_BLOCK_ALL, mem_idx, &thdiqen_thdi_port_pg_config)); 6758 6759 if (!SOC_PBMP_MEMBER(PBMP_EXT_MEM (unit), port) && 6760 (port >= si->cmic_port) && (port <= si->lb_port)) { 6761 op_node = ( si->port_cosq_base[port] / 8); 6762 for (op_node_offset = 0; 6763 op_node_offset < sal_ceil_func(si->port_num_uc_cosq[port],8); 6764 op_node_offset++) { 6765 sal_memset(&thdiema_thdi_port_pg_config,0, 6766 sizeof(thdiema_thdi_port_pg_config)); 6767 SOC_IF_ERROR_RETURN(READ_MMU_THDO_OPNCONFIG_CELLm(unit, 6768 MEM_BLOCK_ANY,op_node + op_node_offset, 6769 &mmu_thdo_opnconfig_cell_entry)); 6770 6771 /* C409:THDO_OPNCONFIG_CELL.OPN_SHARED_LIMIT_CELL = =$C$222 */ 6772 soc_mem_field32_set(unit, MMU_THDO_OPNCONFIG_CELLm, 6773 &mmu_thdo_opnconfig_cell_entry, 6774 OPN_SHARED_LIMIT_CELLf, 6775 output_port_threshold-> 6776 min_grntd_tot_shr_queue_cells_int_buff); 6777 6778 /* C410:THDO_OPNCONFIG_CELL.OP_SHARED_RESET_VALUE_CELL 6779 = =C409-2*$C$76 */ 6780 temp_val = output_port_threshold-> 6781 min_grntd_tot_shr_queue_cells_int_buff - 6782 (2 * general_info->ether_mtu_cells_for_int_buff); 6783 soc_mem_field32_set(unit, MMU_THDO_OPNCONFIG_CELLm, 6784 &mmu_thdo_opnconfig_cell_entry, 6785 OPN_SHARED_RESET_VALUE_CELLf, temp_val); 6786 6787 /* C411:THDO_OPNCONFIG_CELL.PORT_LIMIT_ENABLE_CELL 6788 = 0 */ 6789 soc_mem_field32_set(unit, MMU_THDO_OPNCONFIG_CELLm, 6790 &mmu_thdo_opnconfig_cell_entry, 6791 PORT_LIMIT_ENABLE_CELLf, 0); 6792 soc_mem_field32_set(unit, MMU_THDO_OPNCONFIG_CELLm, 6793 &mmu_thdo_opnconfig_cell_entry, 6794 PIDf, port); 6795 SOC_IF_ERROR_RETURN(WRITE_MMU_THDO_OPNCONFIG_CELLm(unit, 6796 MEM_BLOCK_ANY,op_node + op_node_offset, 6797 &mmu_thdo_opnconfig_cell_entry)); 6798 } 6799 6800 for (queue = si->port_uc_cosq_base[port]; 6801 queue < si->port_uc_cosq_base[port] + 6802 si->port_num_uc_cosq[port]; 6803 queue++) { 6804 SOC_IF_ERROR_RETURN(READ_MMU_THDO_QCONFIG_CELLm(unit, 6805 MEM_BLOCK_ANY,queue, 6806 &mmu_thdo_qconfig_cell_entry)); 6807 /* C412:THDO_QCONFIG_CELL.Q_MIN_CELL 6808 = =$C$204 */ 6809 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, 6810 &mmu_thdo_qconfig_cell_entry, Q_MIN_CELLf, 6811 output_port_threshold->min_grntd_res_queue_cells_int_buff); 6812 6813 /* C414:THDO_QCONFIG_CELL.Q_SHARED_LIMIT_CELL 6814 =IF($C$14,$C$222,$C$63) */ 6815 if (_soc_sb2_mmu_params.lossless_mode_d_c) { 6816 temp_val = output_port_threshold-> 6817 min_grntd_tot_shr_queue_cells_int_buff; 6818 } else { 6819 temp_val = _soc_sb2_mmu_params. 6820 mmu_egr_queue_dyn_thd_param_baf_profile_lossy; 6821 } 6822 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, 6823 &mmu_thdo_qconfig_cell_entry, Q_SHARED_LIMIT_CELLf, 6824 temp_val); 6825 6826 /* C416:THDO_QCONFIG_CELL.Q_LIMIT_DYNAMIC_CELL 6827 =IF($C$14, 0, 1) */ 6828 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, 6829 &mmu_thdo_qconfig_cell_entry, Q_LIMIT_DYNAMIC_CELLf, 6830 _soc_sb2_mmu_params.lossless_mode_d_c ? 0 : 1); 6831 6832 /* C417:THDO_QCONFIG_CELL.Q_LIMIT_ENABLE_CELL 6833 =IF($C$14, 0, 1) */ 6834 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, 6835 &mmu_thdo_qconfig_cell_entry, Q_LIMIT_ENABLE_CELLf, 6836 _soc_sb2_mmu_params.lossless_mode_d_c ? 0 : 1); 6837 6838 /* C418:THDO_QCONFIG_CELL.Q_COLOR_ENABLE_CELL = 0 */ 6839 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, 6840 &mmu_thdo_qconfig_cell_entry, Q_COLOR_ENABLE_CELLf,0); 6841 6842 /* C419: THDO_QCONFIG_CELL.Q_COLOR_LIMIT_DYNAMIC_CELL 6843 =IF($C$14, 0, 1) */ 6844 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, 6845 &mmu_thdo_qconfig_cell_entry, Q_COLOR_LIMIT_DYNAMIC_CELLf, 6846 _soc_sb2_mmu_params.lossless_mode_d_c ? 0 : 1); 6847 6848 /* C420: THDO_QCONFIG_CELL.LIMIT_YELLOW_CELL= 0 */ 6849 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, 6850 &mmu_thdo_qconfig_cell_entry, LIMIT_YELLOW_CELLf, 0); 6851 6852 SOC_IF_ERROR_RETURN(WRITE_MMU_THDO_QCONFIG_CELLm(unit, 6853 MEM_BLOCK_ANY,queue, 6854 &mmu_thdo_qconfig_cell_entry)); 6855 6856 SOC_IF_ERROR_RETURN(READ_MMU_THDO_QOFFSET_CELLm(unit, 6857 MEM_BLOCK_ANY,queue, 6858 &mmu_thdo_qoffset_cell_entry)); 6859 /* C415:THDO_QOFFSET_CELL.RESET_OFFSET_CELL =2 */ 6860 soc_mem_field32_set(unit, MMU_THDO_QOFFSET_CELLm, 6861 &mmu_thdo_qoffset_cell_entry, RESET_OFFSET_CELLf, 2); 6862 6863 /* C421: THDO_QOFFSET_CELL.LIMIT_RED_CELL = */ 6864 soc_mem_field32_set(unit, MMU_THDO_QOFFSET_CELLm, 6865 &mmu_thdo_qoffset_cell_entry, LIMIT_RED_CELLf, 0); 6866 6867 /* C422: THDO_QOFFSET_CELL.RESET_OFFSET_YELLOW_CELL =2 */ 6868 soc_mem_field32_set(unit, MMU_THDO_QOFFSET_CELLm, 6869 &mmu_thdo_qoffset_cell_entry, RESET_OFFSET_YELLOW_CELLf,2); 6870 6871 /* C423: THDO_QOFFSET_CELL.RESET_OFFSET_RED_CELL =2 */ 6872 soc_mem_field32_set(unit, MMU_THDO_QOFFSET_CELLm, 6873 &mmu_thdo_qoffset_cell_entry, RESET_OFFSET_RED_CELLf,2); 6874 6875 SOC_IF_ERROR_RETURN(WRITE_MMU_THDO_QOFFSET_CELLm(unit, 6876 MEM_BLOCK_ANY,queue, 6877 &mmu_thdo_qoffset_cell_entry)); 6878 } 6879 } 6880 if (!IS_CPU_PORT(unit, port) && 6881 (port > si->cmic_port) && (port <= si->lb_port) && 6882 SOC_PBMP_MEMBER(PBMP_EXT_MEM (unit), port)) { 6883 6884 op_node = ( si->port_cosq_base[port] / 8) ; 6885 6886 SOC_IF_ERROR_RETURN(READ_MMU_THDO_OPNCONFIG_CELLm(unit, 6887 MEM_BLOCK_ANY,op_node , &mmu_thdo_opnconfig_cell_entry)); 6888 /* C425:THDO_OPNCONFIG_CELL.OPN_SHARED_LIMIT_CELL = =$C$223 */ 6889 soc_mem_field32_set(unit, MMU_THDO_OPNCONFIG_CELLm, 6890 &mmu_thdo_opnconfig_cell_entry, 6891 OPN_SHARED_LIMIT_CELLf, 6892 output_port_threshold-> 6893 min_grntd_tot_shr_queue_cells_ext_buff); 6894 6895 /* C426:THDO_OPNCONFIG_CELL.OP_SHARED_RESET_VALUE_CELL 6896 = =IF(C17=0, "NA", C425-2*C77) */ 6897 temp_val = output_port_threshold-> 6898 min_grntd_tot_shr_queue_cells_ext_buff - 6899 (2 * general_info->ether_mtu_cells_for_ext_buff); 6900 soc_mem_field32_set(unit, MMU_THDO_OPNCONFIG_CELLm, 6901 &mmu_thdo_opnconfig_cell_entry, 6902 OPN_SHARED_RESET_VALUE_CELLf, temp_val); 6903 6904 /* C427:THDO_OPNCONFIG_CELL.PORT_LIMIT_ENABLE_CELL = 0 */ 6905 soc_mem_field32_set(unit, MMU_THDO_OPNCONFIG_CELLm, 6906 &mmu_thdo_opnconfig_cell_entry, 6907 PORT_LIMIT_ENABLE_CELLf, 0); 6908 soc_mem_field32_set(unit, MMU_THDO_OPNCONFIG_CELLm, 6909 &mmu_thdo_opnconfig_cell_entry, 6910 PIDf, port); 6911 SOC_IF_ERROR_RETURN(WRITE_MMU_THDO_OPNCONFIG_CELLm(unit, 6912 MEM_BLOCK_ANY,op_node, 6913 &mmu_thdo_opnconfig_cell_entry)); 6914 6915 for (queue = si->port_uc_cosq_base[port]; 6916 queue < si->port_uc_cosq_base[port] + 6917 si->port_num_uc_cosq[port]; 6918 queue++) { 6919 SOC_IF_ERROR_RETURN(READ_MMU_THDO_QCONFIG_CELLm(unit, 6920 MEM_BLOCK_ANY,queue, 6921 &mmu_thdo_qconfig_cell_entry)); 6922 /* C428:THDO_QCONFIG_CELL.Q_MIN_CELL 6923 =IF(C17=0, "NA", C205) */ 6924 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, 6925 &mmu_thdo_qconfig_cell_entry, Q_MIN_CELLf, 6926 output_port_threshold->min_grntd_res_queue_cells_ext_buff); 6927 6928 /* C429:THDO_QCONFIG_CELL.Q_SHARED_LIMIT_CELL 6929 =IF(C17=0, "NA", IF($C$14,$C$223,$C$63)) */ 6930 if (_soc_sb2_mmu_params.lossless_mode_d_c) { 6931 temp_val = output_port_threshold-> 6932 min_grntd_tot_shr_queue_cells_ext_buff; 6933 } else { 6934 temp_val = 6935 _soc_sb2_mmu_params.mmu_egr_queue_dyn_thd_param_baf_profile_lossy; 6936 } 6937 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, 6938 &mmu_thdo_qconfig_cell_entry, Q_SHARED_LIMIT_CELLf, 6939 temp_val); 6940 6941 /* C431:THDO_QCONFIG_CELL.Q_LIMIT_DYNAMIC_CELL 6942 =IF(C17=0, "NA", IF($C$14, 0, 1)) */ 6943 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, 6944 &mmu_thdo_qconfig_cell_entry, Q_LIMIT_DYNAMIC_CELLf, 6945 _soc_sb2_mmu_params.lossless_mode_d_c ? 0 : 1); 6946 6947 /* C432:THDO_QCONFIG_CELL.Q_LIMIT_ENABLE_CELL 6948 =IF(C17=0, "NA", IF(C14=0, 1, 0)) */ 6949 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, 6950 &mmu_thdo_qconfig_cell_entry, Q_LIMIT_ENABLE_CELLf, 6951 _soc_sb2_mmu_params.lossless_mode_d_c ? 0 : 1); 6952 6953 /* C433:THDO_QCONFIG_CELL.Q_COLOR_ENABLE_CELL 6954 =IF(C17=0, "NA", 0)*/ 6955 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, 6956 &mmu_thdo_qconfig_cell_entry, Q_COLOR_ENABLE_CELLf,0); 6957 6958 /* C434: THDO_QCONFIG_CELL.Q_COLOR_LIMIT_DYNAMIC_CELL 6959 =IF(C17=0, "NA", IF(C14=0, 1, 0)) */ 6960 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, 6961 &mmu_thdo_qconfig_cell_entry, Q_COLOR_LIMIT_DYNAMIC_CELLf, 6962 _soc_sb2_mmu_params.lossless_mode_d_c ? 0 : 1); 6963 6964 /* C435: THDO_QCONFIG_CELL.LIMIT_YELLOW_CELL= 6965 =IF(C17=0, "NA", 0) */ 6966 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, 6967 &mmu_thdo_qconfig_cell_entry, LIMIT_YELLOW_CELLf, 6968 0); 6969 SOC_IF_ERROR_RETURN(WRITE_MMU_THDO_QCONFIG_CELLm(unit, 6970 MEM_BLOCK_ANY,queue, 6971 &mmu_thdo_qconfig_cell_entry)); 6972 6973 SOC_IF_ERROR_RETURN(READ_MMU_THDO_QOFFSET_CELLm(unit, 6974 MEM_BLOCK_ANY,queue, 6975 &mmu_thdo_qoffset_cell_entry)); 6976 /* C430:THDO_QOFFSET_CELL.RESET_OFFSET_CELL 6977 =IF(C17=0,"NA",1)*/ 6978 soc_mem_field32_set(unit, MMU_THDO_QOFFSET_CELLm, 6979 &mmu_thdo_qoffset_cell_entry, RESET_OFFSET_CELLf, 1); 6980 6981 /* C436: THDO_QOFFSET_CELL.LIMIT_RED_CELL = 6982 =IF(C17=0, "NA", 0) */ 6983 soc_mem_field32_set(unit, MMU_THDO_QOFFSET_CELLm, 6984 &mmu_thdo_qoffset_cell_entry, LIMIT_RED_CELLf, 6985 0); 6986 6987 /* C437: THDO_QOFFSET_CELL.RESET_OFFSET_YELLOW_CELL 6988 =IF(C17=0, "NA", 1)*/ 6989 soc_mem_field32_set(unit, MMU_THDO_QOFFSET_CELLm, 6990 &mmu_thdo_qoffset_cell_entry, RESET_OFFSET_YELLOW_CELLf,1); 6991 /* C438: THDO_QOFFSET_CELL.RESET_OFFSET_RED_CELL = 6992 =IF(C17=0, "NA", 1)*/ 6993 soc_mem_field32_set(unit, MMU_THDO_QOFFSET_CELLm, 6994 &mmu_thdo_qoffset_cell_entry, RESET_OFFSET_RED_CELLf,1); 6995 6996 SOC_IF_ERROR_RETURN(WRITE_MMU_THDO_QOFFSET_CELLm(unit, 6997 MEM_BLOCK_ANY,queue, 6998 &mmu_thdo_qoffset_cell_entry)); 6999 } 7000 } 7001 if (_soc_sb2_mmu_params.extbuf_used_d_c) { 7002 for(cos=0; cos<SOC_REG_NUMELS(unit, OP_QUEUE_CONFIG1_THDOEMAr); cos++) { 7003 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_CONFIG1_THDOEMAr( 7004 unit, cos, &rval)); 7005 /* C440:OP_QUEUE_CONFIG1_THDOEMA.Q_MIN 7006 =IF(C17=0, "NA", C207)*/ 7007 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_THDOEMAr, &rval, 7008 Q_MINf, 7009 output_port_threshold->min_grntd_res_EMA_queue_cells); 7010 7011 /* C445:OP_QUEUE_CONFIG1_THDOEMA.Q_COLOR_ENABLE 7012 =IF(C17=0, "NA", 0)*/ 7013 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_THDOEMAr, &rval, 7014 Q_COLOR_ENABLEf, 0); 7015 7016 /* C446:OP_QUEUE_CONFIG1_THDOEMA.Q_COLOR_DYNAMIC 7017 =IF(C17=0, "NA", IF(C14=0, 1, 0))*/ 7018 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_THDOEMAr, &rval, 7019 Q_COLOR_DYNAMICf, 7020 _soc_sb2_mmu_params.lossless_mode_d_c? 0 : 1); 7021 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_CONFIG1_THDOEMAr( 7022 unit, cos, rval)); 7023 } 7024 7025 for(cos=0; cos<SOC_REG_NUMELS(unit, OP_QUEUE_CONFIG_THDOEMAr); cos++) { 7026 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_CONFIG_THDOEMAr( 7027 unit, cos, &rval)); 7028 /* C441:OP_QUEUE_CONFIG_THDOEMA.Q_SHARED_LIMIT 7029 =IF(C17=0, "NA", IF($C$14,$C$225,$C$63)) */ 7030 if (_soc_sb2_mmu_params.lossless_mode_d_c) { 7031 temp_val = output_port_threshold-> 7032 min_grntd_tot_shr_EMA_queue_cells; 7033 } else { 7034 temp_val = 7035 _soc_sb2_mmu_params.mmu_egr_queue_dyn_thd_param_baf_profile_lossy; 7036 } 7037 soc_reg_field_set(unit, OP_QUEUE_CONFIG_THDOEMAr, &rval, 7038 Q_SHARED_LIMITf, temp_val); 7039 7040 /*C443: OP_QUEUE_CONFIG_THDOEMA.Q_LIMIT_DYNAMIC 7041 =IF(C17=0, "NA", IF($C$14, 0, 1))*/ 7042 7043 soc_reg_field_set(unit, OP_QUEUE_CONFIG_THDOEMAr, &rval, 7044 Q_LIMIT_DYNAMICf, 7045 _soc_sb2_mmu_params.lossless_mode_d_c? 0 : 1); 7046 7047 /*C444:OP_QUEUE_CONFIG_THDOEMA.Q_LIMIT_ENABLE: 7048 =IF(C17=0, "NA", IF(C14=0, 1, 0))*/ 7049 soc_reg_field_set(unit, OP_QUEUE_CONFIG_THDOEMAr, &rval, 7050 Q_LIMIT_ENABLEf, 7051 _soc_sb2_mmu_params.lossless_mode_d_c? 0 : 1); 7052 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_CONFIG_THDOEMAr( 7053 unit, cos, rval)); 7054 7055 } 7056 for(cos=0; 7057 cos<SOC_REG_NUMELS(unit, OP_QUEUE_RESET_OFFSET_THDOEMAr); cos++) { 7058 SOC_IF_ERROR_RETURN( 7059 READ_OP_QUEUE_RESET_OFFSET_THDOEMAr(unit, cos,&rval)); 7060 /*C442: OP_QUEUE_RESET_OFFSET_THDOEMA.Q_RESET_OFFSET 7061 =IF(C17=0,"NA",2) */ 7062 soc_reg_field_set(unit, OP_QUEUE_RESET_OFFSET_THDOEMAr, &rval, 7063 Q_RESET_OFFSETf, 2); 7064 SOC_IF_ERROR_RETURN( 7065 WRITE_OP_QUEUE_RESET_OFFSET_THDOEMAr(unit, cos,rval)); 7066 } 7067 for(cos=0; 7068 cos<SOC_REG_NUMELS(unit, OP_QUEUE_LIMIT_YELLOW_THDOEMAr); 7069 cos++) { 7070 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_LIMIT_YELLOW_THDOEMAr( 7071 unit, cos,&rval)); 7072 /* C447: OP_QUEUE_LIMIT_YELLOW_THDOEMA.Q_LIMIT_YELLOW 7073 =IF(C17=0, "NA", 0) */ 7074 soc_reg_field_set(unit, OP_QUEUE_LIMIT_YELLOW_THDOEMAr, &rval, 7075 Q_LIMIT_YELLOWf, 0); 7076 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_LIMIT_YELLOW_THDOEMAr( 7077 unit, cos,rval)); 7078 } 7079 for(cos=0; 7080 cos<SOC_REG_NUMELS(unit, OP_QUEUE_LIMIT_RED_THDOEMAr); 7081 cos++) { 7082 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_LIMIT_RED_THDOEMAr( 7083 unit, cos,&rval)); 7084 /* C448: OP_QUEUE_LIMIT_RED_THDOEMA.Q_LIMIT_REDi 7085 =IF(C17=0, "NA", 0) */ 7086 soc_reg_field_set(unit, OP_QUEUE_LIMIT_RED_THDOEMAr, &rval, 7087 Q_LIMIT_REDf, 0); 7088 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_LIMIT_RED_THDOEMAr( 7089 unit, cos,rval)); 7090 } 7091 for(cos=0; 7092 cos < SOC_REG_NUMELS(unit, OP_QUEUE_RESET_OFFSET_YELLOW_THDOEMAr); 7093 cos++) { 7094 SOC_IF_ERROR_RETURN( 7095 READ_OP_QUEUE_RESET_OFFSET_YELLOW_THDOEMAr(unit, cos,&rval)); 7096 /*C449:OP_QUEUE_RESET_OFFSET_YELLOW_THDOEMA.RESUME_OFFSET_YELLOW 7097 =IF(C17=0, "NA", 2)*/ 7098 soc_reg_field_set(unit, 7099 OP_QUEUE_RESET_OFFSET_YELLOW_THDOEMAr, &rval, 7100 RESUME_OFFSET_YELLOWf, 2); 7101 SOC_IF_ERROR_RETURN( 7102 WRITE_OP_QUEUE_RESET_OFFSET_YELLOW_THDOEMAr(unit, cos,rval)); 7103 } 7104 for(cos=0; 7105 cos < SOC_REG_NUMELS(unit, OP_QUEUE_RESET_OFFSET_RED_THDOEMAr); 7106 cos++) { 7107 SOC_IF_ERROR_RETURN( 7108 READ_OP_QUEUE_RESET_OFFSET_RED_THDOEMAr(unit, cos,&rval)); 7109 /*C450:OP_QUEUE_RESET_OFFSET_RED_THDOEMA.RESUME_OFFSET_RED= 7110 =IF(C17=0, "NA", 2)*/ 7111 soc_reg_field_set(unit, 7112 OP_QUEUE_RESET_OFFSET_RED_THDOEMAr, &rval, 7113 RESUME_OFFSET_REDf, 2); 7114 SOC_IF_ERROR_RETURN( 7115 WRITE_OP_QUEUE_RESET_OFFSET_RED_THDOEMAr(unit, cos,rval)); 7116 } 7117 } 7118 for (op_node_offset = 0; 7119 op_node_offset < sal_ceil_func(si->port_num_uc_cosq[port],8); 7120 op_node_offset++) { 7121 SOC_IF_ERROR_RETURN(READ_MMU_THDO_OPNCONFIG_QENTRYm(unit, 7122 MEM_BLOCK_ANY,op_node + op_node_offset, 7123 &mmu_thdo_opnconfig_qentry_entry)); 7124 /* C452:THDO_OPNCONFIG_QENTRY.OPN_SHARED_LIMIT_QENTRY = =$C$224 */ 7125 soc_mem_field32_set(unit, MMU_THDO_OPNCONFIG_QENTRYm, 7126 &mmu_thdo_opnconfig_qentry_entry, OPN_SHARED_LIMIT_QENTRYf, 7127 output_port_threshold->min_grntd_tot_shr_queue_cells_EQEs); 7128 7129 /* C453:THDO_OPNCONFIG_QENTRY.OP_SHARED_RESET_VALUE_QENTRY 7130 =C452-2 */ 7131 temp_val = output_port_threshold-> 7132 min_grntd_tot_shr_queue_cells_EQEs - 2; 7133 soc_mem_field32_set(unit, MMU_THDO_OPNCONFIG_QENTRYm, 7134 &mmu_thdo_opnconfig_qentry_entry, 7135 OPN_SHARED_RESET_VALUE_QENTRYf, temp_val); 7136 7137 /* C454:THDO_OPNCONFIG_QENTRY.PORT_LIMIT_ENABLE_QENTRY 7138 = 0 */ 7139 soc_mem_field32_set(unit, MMU_THDO_OPNCONFIG_QENTRYm, 7140 &mmu_thdo_opnconfig_qentry_entry, 7141 PORT_LIMIT_ENABLE_QENTRYf, 0); 7142 soc_mem_field32_set(unit, MMU_THDO_OPNCONFIG_QENTRYm, 7143 &mmu_thdo_opnconfig_qentry_entry, 7144 PIDf, port); 7145 SOC_IF_ERROR_RETURN(WRITE_MMU_THDO_OPNCONFIG_QENTRYm(unit, 7146 MEM_BLOCK_ANY,op_node + op_node_offset, 7147 &mmu_thdo_opnconfig_qentry_entry)); 7148 } 7149 for (queue = si->port_uc_cosq_base[port]; 7150 queue < si->port_uc_cosq_base[port] + si->port_num_uc_cosq[port]; 7151 queue++) { 7152 7153 7154 SOC_IF_ERROR_RETURN(READ_MMU_THDO_QCONFIG_QENTRYm(unit, 7155 MEM_BLOCK_ANY,queue, 7156 &mmu_thdo_qconfig_qentry_entry)); 7157 /* C455:THDO_QCONFIG_QENTRY.Q_MIN_QENTRY = =$C$206 */ 7158 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_QENTRYm, 7159 &mmu_thdo_qconfig_qentry_entry, Q_MIN_QENTRYf, 7160 output_port_threshold->min_grntd_res_queue_cells_EQEs); 7161 7162 /* C456:THDO_QCONFIG_QENTRY.Q_SHARED_LIMIT_QENTRY 7163 =IF($C$14,$C$224,$C$63) */ 7164 if (_soc_sb2_mmu_params.lossless_mode_d_c) { 7165 temp_val = output_port_threshold-> 7166 min_grntd_tot_shr_queue_cells_EQEs; 7167 } else { 7168 temp_val = _soc_sb2_mmu_params. 7169 mmu_egr_queue_dyn_thd_param_baf_profile_lossy; 7170 } 7171 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_QENTRYm, 7172 &mmu_thdo_qconfig_qentry_entry, Q_SHARED_LIMIT_QENTRYf, temp_val); 7173 7174 /* C458:THDO_QCONFIG_QENTRY.Q_LIMIT_DYNAMIC_QENTRY 7175 =IF($C$14, 0, 1) */ 7176 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_QENTRYm, 7177 &mmu_thdo_qconfig_qentry_entry, Q_LIMIT_DYNAMIC_QENTRYf, 7178 _soc_sb2_mmu_params.lossless_mode_d_c ? 0 : 1); 7179 7180 /* C459:THDO_QCONFIG_QENTRY.Q_LIMIT_ENABLE_QENTRY 7181 =IF($C$14, 0, 1) */ 7182 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_QENTRYm, 7183 &mmu_thdo_qconfig_qentry_entry, Q_LIMIT_ENABLE_QENTRYf, 7184 _soc_sb2_mmu_params.lossless_mode_d_c ? 0 : 1); 7185 7186 /* C460:THDO_QCONFIG_QENTRY.Q_COLOR_ENABLE_QENTRY = 0 */ 7187 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_QENTRYm, 7188 &mmu_thdo_qconfig_qentry_entry, Q_COLOR_ENABLE_QENTRYf,0); 7189 7190 /* C461: THDO_QCONFIG_QENTRY.Q_COLOR_LIMIT_DYNAMIC_QENTRY 7191 =IF($C$14, 0, 1) */ 7192 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_QENTRYm, 7193 &mmu_thdo_qconfig_qentry_entry, 7194 Q_COLOR_LIMIT_DYNAMIC_QENTRYf, 7195 _soc_sb2_mmu_params.lossless_mode_d_c ? 0 : 1); 7196 7197 /* C462: THDO_QCONFIG_QENTRY.LIMIT_YELLOW_QENTRY= 0 */ 7198 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_QENTRYm, 7199 &mmu_thdo_qconfig_qentry_entry, LIMIT_YELLOW_QENTRYf, 7200 0); 7201 SOC_IF_ERROR_RETURN(WRITE_MMU_THDO_QCONFIG_QENTRYm(unit, 7202 MEM_BLOCK_ANY,queue, 7203 &mmu_thdo_qconfig_qentry_entry)); 7204 7205 SOC_IF_ERROR_RETURN(READ_MMU_THDO_QOFFSET_QENTRYm(unit, 7206 MEM_BLOCK_ANY,queue, 7207 &mmu_thdo_qoffset_qentry_entry)); 7208 /* C457:THDO_QOFFSET_QENTRY.RESET_OFFSET_QENTRY =1 */ 7209 soc_mem_field32_set(unit, MMU_THDO_QOFFSET_QENTRYm, 7210 &mmu_thdo_qoffset_qentry_entry, RESET_OFFSET_QENTRYf, 1); 7211 7212 /* C463: THDO_QOFFSET_QENTRY.LIMIT_RED_QENTRY = 0 */ 7213 soc_mem_field32_set(unit, MMU_THDO_QOFFSET_QENTRYm, 7214 &mmu_thdo_qoffset_qentry_entry, LIMIT_RED_QENTRYf, 7215 0); 7216 7217 /* C464: THDO_QOFFSET_QENTRY.RESET_OFFSET_YELLOW_QENTRY =1 */ 7218 soc_mem_field32_set(unit, MMU_THDO_QOFFSET_QENTRYm, 7219 &mmu_thdo_qoffset_qentry_entry,RESET_OFFSET_YELLOW_QENTRYf,1); 7220 /* C465: THDO_QOFFSET_QENTRY.RESET_OFFSET_RED_QENTRY =1 */ 7221 soc_mem_field32_set(unit, MMU_THDO_QOFFSET_QENTRYm, 7222 &mmu_thdo_qoffset_qentry_entry, RESET_OFFSET_RED_QENTRYf,1); 7223 7224 SOC_IF_ERROR_RETURN(WRITE_MMU_THDO_QOFFSET_QENTRYm(unit, 7225 MEM_BLOCK_ANY,queue, 7226 &mmu_thdo_qoffset_qentry_entry)); 7227 } 7228 } 7229 for(cos=0; cos<SOC_REG_NUMELS(unit, OP_QUEUE_CONFIG1_THDORQEQr); cos++) { 7230 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_CONFIG1_THDORQEQr( 7231 unit, cos, &rval)); 7232 /* C467:OP_QUEUE_CONFIG1_THDORQEQ.Q_MIN = C208 */ 7233 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_THDORQEQr, &rval, 7234 Q_MINf, 7235 output_port_threshold->min_grntd_res_RE_WQs_cells); 7236 7237 /* C472:OP_QUEUE_CONFIG1_THDORQEQ.Q_COLOR_ENABLE = 0 */ 7238 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_THDORQEQr, &rval, 7239 Q_COLOR_ENABLEf, 0); 7240 7241 /* C473:OP_QUEUE_CONFIG1_THDORQEQ.Q_COLOR_DYNAMIC lossless=0 else 1 7242 =IF(C14=0, 1, 0) */ 7243 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_THDORQEQr, &rval, 7244 Q_COLOR_DYNAMICf, 7245 _soc_sb2_mmu_params.lossless_mode_d_c? 0 : 1); 7246 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_CONFIG1_THDORQEQr( 7247 unit, cos, rval)); 7248 } 7249 7250 for(cos=0; cos<SOC_REG_NUMELS(unit, OP_QUEUE_CONFIG_THDORQEQr); cos++) { 7251 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_CONFIG_THDORQEQr( 7252 unit, cos, &rval)); 7253 /* C468:OP_QUEUE_CONFIG_THDORQEQ.Q_SHARED_LIMIT 7254 ==IF($C$14,$C$226,$C$63) */ 7255 if (_soc_sb2_mmu_params.lossless_mode_d_c) { 7256 temp_val = output_port_threshold-> 7257 min_grntd_tot_shr_RE_WQs_cells ; 7258 } else { 7259 temp_val = 7260 _soc_sb2_mmu_params.mmu_egr_queue_dyn_thd_param_baf_profile_lossy; 7261 } 7262 7263 soc_reg_field_set(unit, OP_QUEUE_CONFIG_THDORQEQr, &rval, 7264 Q_SHARED_LIMITf, temp_val); 7265 7266 /*C470: OP_QUEUE_CONFIG_THDORQEQ.Q_LIMIT_DYNAMIC:=lossless=0 else 1 7267 =IF(C14=0, 1, 0) */ 7268 7269 soc_reg_field_set(unit, OP_QUEUE_CONFIG_THDORQEQr, &rval, 7270 Q_LIMIT_DYNAMICf, 7271 _soc_sb2_mmu_params.lossless_mode_d_c? 0 : 1); 7272 7273 /*C471:OP_QUEUE_CONFIG_THDORQEQ.Q_LIMIT_ENABLE:=lossless=0 else 1*/ 7274 soc_reg_field_set(unit, OP_QUEUE_CONFIG_THDORQEQr, &rval, 7275 Q_LIMIT_ENABLEf, 7276 _soc_sb2_mmu_params.lossless_mode_d_c? 0 : 1); 7277 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_CONFIG_THDORQEQr( 7278 unit, cos, rval)); 7279 7280 } 7281 for(cos=0; 7282 cos<SOC_REG_NUMELS(unit, OP_QUEUE_RESET_OFFSET_THDORQEQr); cos++) { 7283 SOC_IF_ERROR_RETURN( 7284 READ_OP_QUEUE_RESET_OFFSET_THDORQEQr(unit, cos,&rval)); 7285 /*C469: OP_QUEUE_RESET_OFFSET_THDORQEQ.Q_RESET_OFFSET == 1 */ 7286 soc_reg_field_set(unit, OP_QUEUE_RESET_OFFSET_THDORQEQr, &rval, 7287 Q_RESET_OFFSETf, 1); 7288 SOC_IF_ERROR_RETURN( 7289 WRITE_OP_QUEUE_RESET_OFFSET_THDORQEQr(unit, cos,rval)); 7290 } 7291 for(cos=0; 7292 cos<SOC_REG_NUMELS(unit, OP_QUEUE_LIMIT_YELLOW_THDORQEQr); 7293 cos++) { 7294 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_LIMIT_YELLOW_THDORQEQr( 7295 unit, cos,&rval)); 7296 /* C474: OP_QUEUE_LIMIT_YELLOW_THDORQEQ.Q_LIMIT_YELLOW 0 */ 7297 soc_reg_field_set(unit, OP_QUEUE_LIMIT_YELLOW_THDORQEQr, &rval, 7298 Q_LIMIT_YELLOWf, 0); 7299 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_LIMIT_YELLOW_THDORQEQr( 7300 unit, cos,rval)); 7301 } 7302 for(cos=0; 7303 cos<SOC_REG_NUMELS(unit, OP_QUEUE_LIMIT_RED_THDORQEQr); 7304 cos++) { 7305 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_LIMIT_RED_THDORQEQr( 7306 unit, cos,&rval)); 7307 /* C475: OP_QUEUE_LIMIT_RED_THDORQEQ.Q_LIMIT_RED =0 */ 7308 soc_reg_field_set(unit, OP_QUEUE_LIMIT_RED_THDORQEQr, &rval, 7309 Q_LIMIT_REDf, 0); 7310 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_LIMIT_RED_THDORQEQr( 7311 unit, cos,rval)); 7312 } 7313 for(cos=0; 7314 cos < SOC_REG_NUMELS(unit, OP_QUEUE_RESET_OFFSET_YELLOW_THDORQEQr); 7315 cos++) { 7316 SOC_IF_ERROR_RETURN( 7317 READ_OP_QUEUE_RESET_OFFSET_YELLOW_THDORQEQr(unit, cos,&rval)); 7318 /*C476:OP_QUEUE_RESET_OFFSET_YELLOW_THDORQEQ.RESUME_OFFSET_YELLOW=1*/ 7319 soc_reg_field_set(unit, 7320 OP_QUEUE_RESET_OFFSET_YELLOW_THDORQEQr, &rval, 7321 RESUME_OFFSET_YELLOWf, 1); 7322 SOC_IF_ERROR_RETURN( 7323 WRITE_OP_QUEUE_RESET_OFFSET_YELLOW_THDORQEQr(unit, cos,rval)); 7324 } 7325 for(cos=0; 7326 cos < SOC_REG_NUMELS(unit, OP_QUEUE_RESET_OFFSET_RED_THDORQEQr); 7327 cos++) { 7328 SOC_IF_ERROR_RETURN( 7329 READ_OP_QUEUE_RESET_OFFSET_RED_THDORQEQr(unit, cos,&rval)); 7330 /*C477:OP_QUEUE_RESET_OFFSET_RED_THDORQEQ.RESUME_OFFSET_RED=1*/ 7331 soc_reg_field_set(unit, 7332 OP_QUEUE_RESET_OFFSET_RED_THDORQEQr, &rval, 7333 RESUME_OFFSET_REDf, 1); 7334 SOC_IF_ERROR_RETURN( 7335 WRITE_OP_QUEUE_RESET_OFFSET_RED_THDORQEQr(unit, cos,rval)); 7336 } 7337 /* 2.4.2 RQEI */ 7338 for(cos=0; cos<SOC_REG_NUMELS(unit, OP_QUEUE_CONFIG1_THDORQEIr); cos++) { 7339 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_CONFIG1_THDORQEIr( 7340 unit, cos, &rval)); 7341 /* C478:OP_QUEUE_CONFIG1_THDORQEI.Q_MIN = C209 */ 7342 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_THDORQEIr, &rval, Q_MINf, 7343 output_port_threshold->min_grntd_res_RE_WQs_queue_cells_for_int_buff); 7344 7345 /* C483:OP_QUEUE_CONFIG1_THDORQEI.Q_COLOR_ENABLE = 0 */ 7346 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_THDORQEIr, &rval, 7347 Q_COLOR_ENABLEf, 0); 7348 7349 /* C484:OP_QUEUE_CONFIG1_THDORQEI.Q_COLOR_DYNAMIC lossless=0 else 1 7350 =IF($C$14, 0, 1)*/ 7351 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_THDORQEIr, &rval, 7352 Q_COLOR_DYNAMICf, 7353 _soc_sb2_mmu_params.lossless_mode_d_c? 0 : 1); 7354 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_CONFIG1_THDORQEIr( 7355 unit, cos, rval)); 7356 } 7357 7358 for(cos=0; cos<SOC_REG_NUMELS(unit, OP_QUEUE_CONFIG_THDORQEIr); cos++) { 7359 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_CONFIG_THDORQEIr( 7360 unit, cos, &rval)); 7361 /* C479:OP_QUEUE_CONFIG_THDORQEI.Q_SHARED_LIMIT 7362 =IF($C$14,$C$227,$C$63)..Can be put outside loop */ 7363 if (_soc_sb2_mmu_params.lossless_mode_d_c) { 7364 temp_val = output_port_threshold->min_grntd_tot_shr_RE_WQs_queue_cells_for_int_buff; 7365 } else { 7366 temp_val = _soc_sb2_mmu_params.mmu_egr_queue_dyn_thd_param_baf_profile_lossy; 7367 } 7368 soc_reg_field_set(unit, OP_QUEUE_CONFIG_THDORQEIr, &rval, 7369 Q_SHARED_LIMITf, temp_val); 7370 7371 /*C481: OP_QUEUE_CONFIG_THDORQEI.Q_LIMIT_DYNAMIC:=lossless=0 else 1 7372 =IF($C$14, 0, 1)*/ 7373 7374 soc_reg_field_set(unit, OP_QUEUE_CONFIG_THDORQEIr, &rval, 7375 Q_LIMIT_DYNAMICf, 7376 _soc_sb2_mmu_params.lossless_mode_d_c? 0 : 1); 7377 7378 /*C482:OP_QUEUE_CONFIG_THDORQEI.Q_LIMIT_ENABLE:=lossless=0 else 1 7379 =IF($C$14, 0, 1) */ 7380 soc_reg_field_set(unit, OP_QUEUE_CONFIG_THDORQEIr, &rval, 7381 Q_LIMIT_ENABLEf, 7382 _soc_sb2_mmu_params.lossless_mode_d_c? 0 : 1); 7383 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_CONFIG_THDORQEIr( 7384 unit, cos, rval)); 7385 7386 } 7387 for(cos=0; 7388 cos<SOC_REG_NUMELS(unit, OP_QUEUE_RESET_OFFSET_THDORQEIr); cos++) { 7389 SOC_IF_ERROR_RETURN( 7390 READ_OP_QUEUE_RESET_OFFSET_THDORQEIr(unit, cos,&rval)); 7391 /*C480: OP_QUEUE_RESET_OFFSET_THDORQEI.Q_RESET_OFFSET == 2 */ 7392 soc_reg_field_set(unit, OP_QUEUE_RESET_OFFSET_THDORQEIr, &rval, 7393 Q_RESET_OFFSETf, 2); 7394 SOC_IF_ERROR_RETURN( 7395 WRITE_OP_QUEUE_RESET_OFFSET_THDORQEIr(unit, cos,rval)); 7396 } 7397 for(cos=0; 7398 cos<SOC_REG_NUMELS(unit, OP_QUEUE_LIMIT_YELLOW_THDORQEIr); 7399 cos++) { 7400 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_LIMIT_YELLOW_THDORQEIr( 7401 unit, cos,&rval)); 7402 /* C485: OP_QUEUE_LIMIT_YELLOW_THDORQEI.Q_LIMIT_YELLOW =0 */ 7403 soc_reg_field_set(unit, OP_QUEUE_LIMIT_YELLOW_THDORQEIr, &rval, 7404 Q_LIMIT_YELLOWf, 0); 7405 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_LIMIT_YELLOW_THDORQEIr( 7406 unit, cos,rval)); 7407 } 7408 for(cos=0; 7409 cos<SOC_REG_NUMELS(unit, OP_QUEUE_LIMIT_RED_THDORQEIr); 7410 cos++) { 7411 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_LIMIT_RED_THDORQEIr( 7412 unit, cos,&rval)); 7413 /* C486: OP_QUEUE_LIMIT_RED_THDORQEI.Q_LIMIT_RED = 0*/ 7414 soc_reg_field_set(unit, OP_QUEUE_LIMIT_RED_THDORQEIr, &rval, 7415 Q_LIMIT_REDf, 0); 7416 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_LIMIT_RED_THDORQEIr( 7417 unit, cos,rval)); 7418 } 7419 for(cos=0; 7420 cos < SOC_REG_NUMELS(unit, OP_QUEUE_RESET_OFFSET_YELLOW_THDORQEIr); 7421 cos++) { 7422 SOC_IF_ERROR_RETURN( 7423 READ_OP_QUEUE_RESET_OFFSET_YELLOW_THDORQEIr(unit, cos,&rval)); 7424 /*C487:OP_QUEUE_RESET_OFFSET_YELLOW_THDORQEI.RESUME_OFFSET_YELLOW=2*/ 7425 soc_reg_field_set(unit, 7426 OP_QUEUE_RESET_OFFSET_YELLOW_THDORQEIr, &rval, 7427 RESUME_OFFSET_YELLOWf, 2); 7428 SOC_IF_ERROR_RETURN( 7429 WRITE_OP_QUEUE_RESET_OFFSET_YELLOW_THDORQEIr(unit, cos,rval)); 7430 } 7431 for(cos=0; 7432 cos < SOC_REG_NUMELS(unit, OP_QUEUE_RESET_OFFSET_RED_THDORQEIr); 7433 cos++) { 7434 SOC_IF_ERROR_RETURN( 7435 READ_OP_QUEUE_RESET_OFFSET_RED_THDORQEIr(unit, cos,&rval)); 7436 /*C488:OP_QUEUE_RESET_OFFSET_RED_THDORQEI.RESUME_OFFSET_RED=2*/ 7437 soc_reg_field_set(unit, 7438 OP_QUEUE_RESET_OFFSET_RED_THDORQEIr, &rval, 7439 RESUME_OFFSET_REDf, 2); 7440 SOC_IF_ERROR_RETURN( 7441 WRITE_OP_QUEUE_RESET_OFFSET_RED_THDORQEIr(unit, cos,rval)); 7442 } 7443 if (_soc_sb2_mmu_params.extbuf_used_d_c) { 7444 7445 for(cos=0; cos<SOC_REG_NUMELS(unit, OP_QUEUE_CONFIG1_THDORQEEr); cos++) { 7446 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_CONFIG1_THDORQEEr( 7447 unit, cos, &rval)); 7448 /* C489:OP_QUEUE_CONFIG1_THDORQEE.Q_MIN = 7449 =IF(C17=0, "NA", C210)*/ 7450 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_THDORQEEr, &rval, Q_MINf, 7451 output_port_threshold->min_grntd_res_RE_WQs_queue_cells_for_ext_buff); 7452 7453 /* C494:OP_QUEUE_CONFIG1_THDORQEE.Q_COLOR_ENABLE 7454 =IF(C17=0, "NA", 0)*/ 7455 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_THDORQEEr, &rval, 7456 Q_COLOR_ENABLEf, 0); 7457 7458 /* C495:OP_QUEUE_CONFIG1_THDORQEE.Q_COLOR_DYNAMIC 7459 =IF(C17=0, "NA", IF($C$14, 0, 1))*/ 7460 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_THDORQEEr, &rval, 7461 Q_COLOR_DYNAMICf, 7462 _soc_sb2_mmu_params.lossless_mode_d_c? 0 : 1); 7463 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_CONFIG1_THDORQEEr( 7464 unit, cos, rval)); 7465 } 7466 7467 for(cos=0; cos<SOC_REG_NUMELS(unit, OP_QUEUE_CONFIG_THDORQEEr); cos++) { 7468 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_CONFIG_THDORQEEr( 7469 unit, cos, &rval)); 7470 /* C490:OP_QUEUE_CONFIG_THDORQEE.Q_SHARED_LIMIT 7471 =IF(C17=0, "NA",IF($C$14,$C$228,$C$63)) */ 7472 if (_soc_sb2_mmu_params.lossless_mode_d_c) { 7473 temp_val = output_port_threshold-> 7474 min_grntd_tot_shr_RE_WQs_queue_cells_for_ext_buff; 7475 } else { 7476 temp_val = _soc_sb2_mmu_params. 7477 mmu_egr_queue_dyn_thd_param_baf_profile_lossy; 7478 } 7479 soc_reg_field_set(unit, OP_QUEUE_CONFIG_THDORQEEr, &rval, 7480 Q_SHARED_LIMITf, temp_val); 7481 7482 /*C492: OP_QUEUE_CONFIG_THDORQEE.Q_LIMIT_DYNAMIC 7483 =IF(C17=0, "NA", IF($C$14, 0, 1))*/ 7484 7485 soc_reg_field_set(unit, OP_QUEUE_CONFIG_THDORQEEr, &rval, 7486 Q_LIMIT_DYNAMICf, 7487 _soc_sb2_mmu_params.lossless_mode_d_c? 0 : 1); 7488 7489 /*C493:OP_QUEUE_CONFIG_THDORQEE.Q_LIMIT_ENABLE 7490 =IF(C17=0, "NA", IF($C$14, 0, 1))*/ 7491 soc_reg_field_set(unit, OP_QUEUE_CONFIG_THDORQEEr, &rval, 7492 Q_LIMIT_ENABLEf, 7493 _soc_sb2_mmu_params.lossless_mode_d_c? 0 : 1); 7494 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_CONFIG_THDORQEEr( 7495 unit, cos, rval)); 7496 7497 } 7498 for(cos=0; 7499 cos<SOC_REG_NUMELS(unit, OP_QUEUE_RESET_OFFSET_THDORQEEr); cos++) { 7500 SOC_IF_ERROR_RETURN( 7501 READ_OP_QUEUE_RESET_OFFSET_THDORQEEr(unit, cos,&rval)); 7502 /*C491: OP_QUEUE_RESET_OFFSET_THDORQEE.Q_RESET_OFFSET 7503 =IF(C17=0, "NA", 1)*/ 7504 soc_reg_field_set(unit, OP_QUEUE_RESET_OFFSET_THDORQEEr, &rval, 7505 Q_RESET_OFFSETf, 1); 7506 SOC_IF_ERROR_RETURN( 7507 WRITE_OP_QUEUE_RESET_OFFSET_THDORQEEr(unit, cos,rval)); 7508 } 7509 for(cos=0; 7510 cos<SOC_REG_NUMELS(unit, OP_QUEUE_LIMIT_YELLOW_THDORQEEr); 7511 cos++) { 7512 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_LIMIT_YELLOW_THDORQEEr( 7513 unit, cos,&rval)); 7514 /* C496: OP_QUEUE_LIMIT_YELLOW_THDORQEE.Q_LIMIT_YELLOW 7515 =IF(C17=0, "NA", 0) */ 7516 soc_reg_field_set(unit, OP_QUEUE_LIMIT_YELLOW_THDORQEEr, &rval, 7517 Q_LIMIT_YELLOWf, 0); 7518 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_LIMIT_YELLOW_THDORQEEr( 7519 unit, cos, rval)); 7520 } 7521 for(cos=0; 7522 cos<SOC_REG_NUMELS(unit, OP_QUEUE_LIMIT_RED_THDORQEEr); 7523 cos++) { 7524 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_LIMIT_RED_THDORQEEr( 7525 unit, cos,&rval)); 7526 /* C497: OP_QUEUE_LIMIT_RED_THDORQEE.Q_LIMIT_RED 7527 =IF(C17=0, "NA", 0) */ 7528 soc_reg_field_set(unit, OP_QUEUE_LIMIT_RED_THDORQEEr, &rval, 7529 Q_LIMIT_REDf, 0); 7530 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_LIMIT_RED_THDORQEEr( 7531 unit, cos,rval)); 7532 } 7533 for(cos=0; 7534 cos < SOC_REG_NUMELS(unit, OP_QUEUE_RESET_OFFSET_YELLOW_THDORQEEr); 7535 cos++) { 7536 SOC_IF_ERROR_RETURN( 7537 READ_OP_QUEUE_RESET_OFFSET_YELLOW_THDORQEEr(unit, cos,&rval)); 7538 /*C498:OP_QUEUE_RESET_OFFSET_YELLOW_THDORQEE.RESUME_OFFSET_YELLOW= 7539 =IF(C17=0, "NA", 1)*/ 7540 soc_reg_field_set(unit, 7541 OP_QUEUE_RESET_OFFSET_YELLOW_THDORQEEr, &rval, 7542 RESUME_OFFSET_YELLOWf, 1); 7543 SOC_IF_ERROR_RETURN( 7544 WRITE_OP_QUEUE_RESET_OFFSET_YELLOW_THDORQEEr(unit, cos,rval)); 7545 } 7546 for(cos=0; 7547 cos < SOC_REG_NUMELS(unit, OP_QUEUE_RESET_OFFSET_RED_THDORQEEr); 7548 cos++) { 7549 SOC_IF_ERROR_RETURN( 7550 READ_OP_QUEUE_RESET_OFFSET_RED_THDORQEEr(unit, cos,&rval)); 7551 /*C499:OP_QUEUE_RESET_OFFSET_RED_THDORQEE.RESUME_OFFSET_RED 7552 =IF(C17=0, "NA", 1)*/ 7553 soc_reg_field_set(unit, 7554 OP_QUEUE_RESET_OFFSET_RED_THDORQEEr, &rval, 7555 RESUME_OFFSET_REDf, 1); 7556 SOC_IF_ERROR_RETURN( 7557 WRITE_OP_QUEUE_RESET_OFFSET_RED_THDORQEEr(unit, cos,rval)); 7558 } 7559 } 7560 7561 for(cos=0; cos<SOC_REG_NUMELS(unit, OP_QUEUE_CONFIG1_THDORDEQr); cos++) { 7562 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_CONFIG1_THDORDEQr( 7563 unit, cos, &rval)); 7564 /* C501:OP_QUEUE_CONFIG1_THDORDEQ.Q_MIN = C211 */ 7565 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_THDORDEQr, &rval, Q_MINf, 7566 output_port_threshold->min_grntd_res_EP_redirect_queue_entry_cells); 7567 7568 /* C506:OP_QUEUE_CONFIG1_THDORDEQ.Q_COLOR_ENABLE = 0 */ 7569 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_THDORDEQr, &rval, 7570 Q_COLOR_ENABLEf, 0); 7571 7572 /* C507:OP_QUEUE_CONFIG1_THDORDEQ.Q_COLOR_DYNAMIC lossless=0 else 1 7573 =IF(C14=0, 1, 0)*/ 7574 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_THDORDEQr, &rval, 7575 Q_COLOR_DYNAMICf, 7576 _soc_sb2_mmu_params.lossless_mode_d_c? 0 : 1); 7577 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_CONFIG1_THDORDEQr( 7578 unit, cos, rval)); 7579 } 7580 7581 for(cos=0; cos<SOC_REG_NUMELS(unit, OP_QUEUE_CONFIG_THDORDEQr); cos++) { 7582 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_CONFIG_THDORDEQr( 7583 unit, cos, &rval)); 7584 /* C502:OP_QUEUE_CONFIG_THDORDEQ.Q_SHARED_LIMIT 7585 =IF(C14=0, C63, C229)..Can be put outside loop */ 7586 if (_soc_sb2_mmu_params.lossless_mode_d_c) { 7587 temp_val = output_port_threshold->min_grntd_tot_shr_EP_redirect_queue_entry_cells; 7588 } else { 7589 temp_val = _soc_sb2_mmu_params.mmu_egr_queue_dyn_thd_param_baf_profile_lossy; 7590 } 7591 soc_reg_field_set(unit, OP_QUEUE_CONFIG_THDORDEQr, &rval, 7592 Q_SHARED_LIMITf, temp_val); 7593 7594 /*C504: OP_QUEUE_CONFIG_THDORDEQ.Q_LIMIT_DYNAMIC:=lossless=0 else 1i 7595 =IF(C14=0, 1, 0)*/ 7596 7597 soc_reg_field_set(unit, OP_QUEUE_CONFIG_THDORDEQr, &rval, 7598 Q_LIMIT_DYNAMICf, 7599 _soc_sb2_mmu_params.lossless_mode_d_c? 0 : 1); 7600 7601 /*C505:OP_QUEUE_CONFIG_THDORDEQ.Q_LIMIT_ENABLE:=lossless=0 else 1 7602 =IF(C14=0, 1, 0)*/ 7603 soc_reg_field_set(unit, OP_QUEUE_CONFIG_THDORDEQr, &rval, 7604 Q_LIMIT_ENABLEf, 7605 _soc_sb2_mmu_params.lossless_mode_d_c? 0 : 1); 7606 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_CONFIG_THDORDEQr( 7607 unit, cos, rval)); 7608 7609 } 7610 for(cos=0; 7611 cos<SOC_REG_NUMELS(unit, OP_QUEUE_RESET_OFFSET_THDORDEQr); cos++) { 7612 SOC_IF_ERROR_RETURN( 7613 READ_OP_QUEUE_RESET_OFFSET_THDORDEQr(unit, cos,&rval)); 7614 /*C503: OP_QUEUE_RESET_OFFSET_THDORDEQ.Q_RESET_OFFSET == 1 */ 7615 soc_reg_field_set(unit, OP_QUEUE_RESET_OFFSET_THDORDEQr, &rval, 7616 Q_RESET_OFFSETf, 1); 7617 SOC_IF_ERROR_RETURN( 7618 WRITE_OP_QUEUE_RESET_OFFSET_THDORDEQr(unit, cos,rval)); 7619 } 7620 for(cos=0; 7621 cos<SOC_REG_NUMELS(unit, OP_QUEUE_LIMIT_YELLOW_THDORDEQr); 7622 cos++) { 7623 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_LIMIT_YELLOW_THDORDEQr( 7624 unit, cos,&rval)); 7625 /* C508: OP_QUEUE_LIMIT_YELLOW_THDORDEQ.Q_LIMIT_YELLOW = 0 */ 7626 soc_reg_field_set(unit, OP_QUEUE_LIMIT_YELLOW_THDORDEQr, &rval, 7627 Q_LIMIT_YELLOWf, 0); 7628 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_LIMIT_YELLOW_THDORDEQr( 7629 unit, cos,rval)); 7630 } 7631 for(cos=0; 7632 cos<SOC_REG_NUMELS(unit, OP_QUEUE_LIMIT_RED_THDORDEQr); 7633 cos++) { 7634 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_LIMIT_RED_THDORDEQr( 7635 unit, cos,&rval)); 7636 /* C509: OP_QUEUE_LIMIT_RED_THDORDEQ.Q_LIMIT_RED = 0 */ 7637 soc_reg_field_set(unit, OP_QUEUE_LIMIT_RED_THDORDEQr, &rval, 7638 Q_LIMIT_REDf, 0); 7639 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_LIMIT_RED_THDORDEQr( 7640 unit, cos,rval)); 7641 } 7642 for(cos=0; 7643 cos < SOC_REG_NUMELS(unit, OP_QUEUE_RESET_OFFSET_YELLOW_THDORDEQr); 7644 cos++) { 7645 SOC_IF_ERROR_RETURN( 7646 READ_OP_QUEUE_RESET_OFFSET_YELLOW_THDORDEQr(unit, cos,&rval)); 7647 /*C510:OP_QUEUE_RESET_OFFSET_YELLOW_THDORDEQ.RESUME_OFFSET_YELLOW=1*/ 7648 soc_reg_field_set(unit, 7649 OP_QUEUE_RESET_OFFSET_YELLOW_THDORDEQr, &rval, 7650 RESUME_OFFSET_YELLOWf, 1); 7651 SOC_IF_ERROR_RETURN( 7652 WRITE_OP_QUEUE_RESET_OFFSET_YELLOW_THDORDEQr(unit, cos,rval)); 7653 } 7654 for(cos=0; 7655 cos < SOC_REG_NUMELS(unit, OP_QUEUE_RESET_OFFSET_RED_THDORDEQr); 7656 cos++) { 7657 SOC_IF_ERROR_RETURN( 7658 READ_OP_QUEUE_RESET_OFFSET_RED_THDORDEQr(unit, cos,&rval)); 7659 /*C511:OP_QUEUE_RESET_OFFSET_RED_THDORDEQ.RESUME_OFFSET_RED=1*/ 7660 soc_reg_field_set(unit, 7661 OP_QUEUE_RESET_OFFSET_RED_THDORDEQr, &rval, 7662 RESUME_OFFSET_REDf, 1); 7663 SOC_IF_ERROR_RETURN( 7664 WRITE_OP_QUEUE_RESET_OFFSET_RED_THDORDEQr(unit, cos,rval)); 7665 } 7666 for(cos=0; cos<SOC_REG_NUMELS(unit, OP_QUEUE_CONFIG1_THDORDEIr); cos++) { 7667 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_CONFIG1_THDORDEIr( 7668 unit, cos, &rval)); 7669 /* C512:OP_QUEUE_CONFIG1_THDORDEI.Q_MIN = 9 (C204) */ 7670 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_THDORDEIr, &rval, 7671 Q_MINf, output_port_threshold->min_grntd_res_queue_cells_int_buff); 7672 7673 /* C517:OP_QUEUE_CONFIG1_THDORDEI.Q_COLOR_ENABLE = 0 */ 7674 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_THDORDEIr, &rval, 7675 Q_COLOR_ENABLEf, 0); 7676 7677 /* C518:OP_QUEUE_CONFIG1_THDORDEI.Q_COLOR_DYNAMIC = 1*/ 7678 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_THDORDEIr, &rval, 7679 Q_COLOR_DYNAMICf, _soc_sb2_mmu_params.lossless_mode_d_c? 0 :1); 7680 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_CONFIG1_THDORDEIr( 7681 unit, cos, rval)); 7682 } 7683 7684 for(cos=0; cos<SOC_REG_NUMELS(unit, OP_QUEUE_CONFIG_THDORDEIr); cos++) { 7685 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_CONFIG_THDORDEIr( 7686 unit, cos, &rval)); 7687 /* C513:OP_QUEUE_CONFIG_THDORDEI.Q_SHARED_LIMIT = 7688 =IF(C14=0, C63, C222)*/ 7689 if (_soc_sb2_mmu_params.lossless_mode_d_c) { 7690 temp_val = output_port_threshold->min_grntd_tot_shr_queue_cells_int_buff; 7691 } else { 7692 temp_val = _soc_sb2_mmu_params.mmu_egr_queue_dyn_thd_param_baf_profile_lossy; 7693 } 7694 7695 soc_reg_field_set(unit, OP_QUEUE_CONFIG_THDORDEIr, &rval, 7696 Q_SHARED_LIMITf, temp_val); 7697 7698 /*C515: OP_QUEUE_CONFIG_THDORDEI.Q_LIMIT_DYNAMIC:=1 7699 =IF(C14=0, 1, 0)*/ 7700 7701 soc_reg_field_set(unit, OP_QUEUE_CONFIG_THDORDEIr, &rval, 7702 Q_LIMIT_DYNAMICf, 7703 _soc_sb2_mmu_params.lossless_mode_d_c ? 0 :1); 7704 7705 /*C516:OP_QUEUE_CONFIG_THDORDEI.Q_LIMIT_ENABLE: 7706 =IF(C14=0, 1, 0)*/ 7707 soc_reg_field_set(unit, OP_QUEUE_CONFIG_THDORDEIr, &rval, 7708 Q_LIMIT_ENABLEf, 7709 _soc_sb2_mmu_params.lossless_mode_d_c ? 0 :1); 7710 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_CONFIG_THDORDEIr( 7711 unit, cos, rval)); 7712 } 7713 for(cos=0; 7714 cos<SOC_REG_NUMELS(unit, OP_QUEUE_RESET_OFFSET_THDORDEIr); cos++) { 7715 SOC_IF_ERROR_RETURN( 7716 READ_OP_QUEUE_RESET_OFFSET_THDORDEIr(unit, cos,&rval)); 7717 /*C514: OP_QUEUE_RESET_OFFSET_THDORDEI.Q_RESET_OFFSET == 2 */ 7718 soc_reg_field_set(unit, OP_QUEUE_RESET_OFFSET_THDORDEIr, &rval, 7719 Q_RESET_OFFSETf, 2); 7720 SOC_IF_ERROR_RETURN( 7721 WRITE_OP_QUEUE_RESET_OFFSET_THDORDEIr(unit, cos,rval)); 7722 } 7723 for(cos=0; 7724 cos<SOC_REG_NUMELS(unit, OP_QUEUE_LIMIT_YELLOW_THDORDEIr); 7725 cos++) { 7726 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_LIMIT_YELLOW_THDORDEIr( 7727 unit, cos,&rval)); 7728 /* C519: OP_QUEUE_LIMIT_YELLOW_THDORDEI.Q_LIMIT_YELLOW = 0 */ 7729 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_CONFIG_THDORDEIr( 7730 unit, cos, &rval)); 7731 temp_val = soc_reg_field_get(unit, OP_QUEUE_CONFIG_THDORDEIr, rval, 7732 Q_SHARED_LIMITf); 7733 7734 soc_reg_field_set(unit, OP_QUEUE_LIMIT_YELLOW_THDORDEIr, &rval, 7735 Q_LIMIT_YELLOWf, 0); 7736 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_LIMIT_YELLOW_THDORDEIr( 7737 unit, cos,rval)); 7738 } 7739 for(cos=0; 7740 cos<SOC_REG_NUMELS(unit, OP_QUEUE_LIMIT_RED_THDORDEIr); 7741 cos++) { 7742 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_LIMIT_RED_THDORDEIr( 7743 unit, cos,&rval)); 7744 /* C520: OP_QUEUE_LIMIT_RED_THDORDEI.Q_LIMIT_RED = C486 */ 7745 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_CONFIG_THDORDEIr( 7746 unit, cos, &rval)); 7747 temp_val = soc_reg_field_get(unit, OP_QUEUE_CONFIG_THDORDEIr, rval, 7748 Q_SHARED_LIMITf); 7749 7750 soc_reg_field_set(unit, OP_QUEUE_LIMIT_RED_THDORDEIr, &rval, 7751 Q_LIMIT_REDf, 0); 7752 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_LIMIT_RED_THDORDEIr( 7753 unit, cos,rval)); 7754 } 7755 for(cos=0; 7756 cos < SOC_REG_NUMELS(unit, OP_QUEUE_RESET_OFFSET_YELLOW_THDORDEIr); 7757 cos++) { 7758 SOC_IF_ERROR_RETURN( 7759 READ_OP_QUEUE_RESET_OFFSET_YELLOW_THDORDEIr(unit, cos,&rval)); 7760 /*C521:OP_QUEUE_RESET_OFFSET_YELLOW_THDORDEI.RESUME_OFFSET_YELLOW=2*/ 7761 soc_reg_field_set(unit, 7762 OP_QUEUE_RESET_OFFSET_YELLOW_THDORDEIr, &rval, 7763 RESUME_OFFSET_YELLOWf, 2); 7764 SOC_IF_ERROR_RETURN( 7765 WRITE_OP_QUEUE_RESET_OFFSET_YELLOW_THDORDEIr(unit, cos,rval)); 7766 } 7767 for(cos=0; 7768 cos < SOC_REG_NUMELS(unit, OP_QUEUE_RESET_OFFSET_RED_THDORDEIr); 7769 cos++) { 7770 SOC_IF_ERROR_RETURN( 7771 READ_OP_QUEUE_RESET_OFFSET_RED_THDORDEIr(unit, cos,&rval)); 7772 /*C522:OP_QUEUE_RESET_OFFSET_RED_THDORDEI.RESUME_OFFSET_RED=2*/ 7773 soc_reg_field_set(unit, 7774 OP_QUEUE_RESET_OFFSET_RED_THDORDEIr, &rval, 7775 RESUME_OFFSET_REDf, 2); 7776 SOC_IF_ERROR_RETURN( 7777 WRITE_OP_QUEUE_RESET_OFFSET_RED_THDORDEIr(unit, cos,rval)); 7778 } 7779 if (_soc_sb2_mmu_params.extbuf_used_d_c) { 7780 for(cos=0; cos<SOC_REG_NUMELS(unit, OP_QUEUE_CONFIG1_THDORDEEr); cos++) { 7781 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_CONFIG1_THDORDEEr( 7782 unit, cos, &rval)); 7783 /* C523:OP_QUEUE_CONFIG1_THDORDEE.Q_MIN 7784 =IF(C17=0, "NA", C205)*/ 7785 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_THDORDEEr, &rval, Q_MINf, 7786 output_port_threshold->min_grntd_res_queue_cells_ext_buff); 7787 7788 /* C528:OP_QUEUE_CONFIG1_THDORDEE.Q_COLOR_ENABLE = 7789 =IF(C17=0, "NA", 0)*/ 7790 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_THDORDEEr, &rval, 7791 Q_COLOR_ENABLEf, 0); 7792 7793 /* C529:OP_QUEUE_CONFIG1_THDORDEE.Q_COLOR_DYNAMIC = 7794 =IF(C17=0, "NA", IF(C14=0, 1, 0))*/ 7795 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_THDORDEEr, &rval, 7796 Q_COLOR_DYNAMICf, _soc_sb2_mmu_params.lossless_mode_d_c ? 0 :1); 7797 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_CONFIG1_THDORDEEr( 7798 unit, cos, rval)); 7799 } 7800 7801 for(cos=0; cos<SOC_REG_NUMELS(unit, OP_QUEUE_CONFIG_THDORDEEr); cos++) { 7802 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_CONFIG_THDORDEEr( 7803 unit, cos, &rval)); 7804 /* C524:OP_QUEUE_CONFIG_THDORDEE.Q_SHARED_LIMIT 7805 =IF(C17=0, "NA", IF(C14=0, C63, C223)) */ 7806 if (_soc_sb2_mmu_params.lossless_mode_d_c) { 7807 temp_val = output_port_threshold->min_grntd_tot_shr_queue_cells_ext_buff; 7808 } else { 7809 temp_val = _soc_sb2_mmu_params.mmu_egr_queue_dyn_thd_param_baf_profile_lossy ; 7810 } 7811 7812 soc_reg_field_set(unit, OP_QUEUE_CONFIG_THDORDEEr, &rval, 7813 Q_SHARED_LIMITf, temp_val); 7814 7815 /*C526: OP_QUEUE_CONFIG_THDORDEE.Q_LIMIT_DYNAMIC: 7816 =IF(C17=0, "NA", IF(C14=0, 1, 0))*/ 7817 7818 soc_reg_field_set(unit, OP_QUEUE_CONFIG_THDORDEEr, &rval, 7819 Q_LIMIT_DYNAMICf,_soc_sb2_mmu_params.lossless_mode_d_c? 0 :1); 7820 7821 /*C527:OP_QUEUE_CONFIG_THDORDEE.Q_LIMIT_ENABLE: 7822 =IF(C17=0, "NA", IF(C14=0, 1, 0))*/ 7823 soc_reg_field_set(unit, OP_QUEUE_CONFIG_THDORDEEr, &rval, 7824 Q_LIMIT_ENABLEf, _soc_sb2_mmu_params.lossless_mode_d_c? 0 :1); 7825 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_CONFIG_THDORDEEr( 7826 unit, cos, rval)); 7827 } 7828 for(cos=0; 7829 cos<SOC_REG_NUMELS(unit, OP_QUEUE_RESET_OFFSET_THDORDEEr); cos++) { 7830 SOC_IF_ERROR_RETURN( 7831 READ_OP_QUEUE_RESET_OFFSET_THDORDEEr(unit, cos,&rval)); 7832 /*C525:OP_QUEUE_RESET_OFFSET_THDORDEE.Q_RESET_OFFSET 7833 =IF(C17=0, "NA", 1) */ 7834 soc_reg_field_set(unit, OP_QUEUE_RESET_OFFSET_THDORDEEr, &rval, 7835 Q_RESET_OFFSETf, 1) ; 7836 SOC_IF_ERROR_RETURN( 7837 WRITE_OP_QUEUE_RESET_OFFSET_THDORDEEr(unit, cos,rval)); 7838 } 7839 for(cos=0; 7840 cos<SOC_REG_NUMELS(unit, OP_QUEUE_LIMIT_YELLOW_THDORDEEr); 7841 cos++) { 7842 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_LIMIT_YELLOW_THDORDEEr( 7843 unit, cos,&rval)); 7844 /* C530: OP_QUEUE_LIMIT_YELLOW_THDORDEE.Q_LIMIT_YELLOW 7845 =IF(C17=0, "NA", 0) */ 7846 7847 soc_reg_field_set(unit, OP_QUEUE_LIMIT_YELLOW_THDORDEEr, &rval, 7848 Q_LIMIT_YELLOWf, 0); 7849 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_LIMIT_YELLOW_THDORDEEr( 7850 unit, cos,rval)); 7851 } 7852 for(cos=0; 7853 cos<SOC_REG_NUMELS(unit, OP_QUEUE_LIMIT_RED_THDORDEEr); 7854 cos++) { 7855 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_LIMIT_RED_THDORDEEr( 7856 unit, cos,&rval)); 7857 /* C531: OP_QUEUE_LIMIT_RED_THDORDEE.Q_LIMIT_RED 7858 =IF(C17=0, "NA", 0)*/ 7859 soc_reg_field_set(unit, OP_QUEUE_LIMIT_RED_THDORDEEr, &rval, 7860 Q_LIMIT_REDf, 0); 7861 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_LIMIT_RED_THDORDEEr( 7862 unit, cos,rval)); 7863 } 7864 for(cos=0; 7865 cos < SOC_REG_NUMELS(unit, OP_QUEUE_RESET_OFFSET_YELLOW_THDORDEEr); 7866 cos++) { 7867 SOC_IF_ERROR_RETURN( 7868 READ_OP_QUEUE_RESET_OFFSET_YELLOW_THDORDEEr(unit, cos,&rval)); 7869 /*C532:OP_QUEUE_RESET_OFFSET_YELLOW_THDORDEE.RESUME_OFFSET_YELLOW 7870 =IF(C17=0, "NA", 1)*/ 7871 soc_reg_field_set(unit, 7872 OP_QUEUE_RESET_OFFSET_YELLOW_THDORDEEr, &rval, 7873 RESUME_OFFSET_YELLOWf, 1); 7874 SOC_IF_ERROR_RETURN( 7875 WRITE_OP_QUEUE_RESET_OFFSET_YELLOW_THDORDEEr(unit, cos,rval)); 7876 } 7877 for(cos=0; 7878 cos < SOC_REG_NUMELS(unit, OP_QUEUE_RESET_OFFSET_RED_THDORDEEr); 7879 cos++) { 7880 SOC_IF_ERROR_RETURN( 7881 READ_OP_QUEUE_RESET_OFFSET_RED_THDORDEEr(unit, cos,&rval)); 7882 /*C533:OP_QUEUE_RESET_OFFSET_RED_THDORDEE.RESUME_OFFSET_RED 7883 =IF(C17=0, "NA", 1)*/ 7884 soc_reg_field_set(unit, 7885 OP_QUEUE_RESET_OFFSET_RED_THDORDEEr, &rval, 7886 RESUME_OFFSET_REDf, 1); 7887 SOC_IF_ERROR_RETURN( 7888 WRITE_OP_QUEUE_RESET_OFFSET_RED_THDORDEEr(unit, cos,rval)); 7889 } 7890 } 7891 /* Enable back pressure status from MMU for lossless mode */ 7892 if (_soc_sb2_mmu_params.lossless_mode_d_c) { 7893 val = 0x1ffffffe; /* 0 to 29 ports */ 7894 sal_memset (&rval, 0, sizeof(rval)); 7895 soc_reg_field_set (unit, THDIEXT_PORT_PAUSE_ENABLE_64r, &rval, 7896 PORT_PAUSE_ENABLEf, val); 7897 SOC_IF_ERROR_RETURN 7898 (soc_reg32_set(unit, THDIEXT_PORT_PAUSE_ENABLE_64r,REG_PORT_ANY, 7899 0, rval)); 7900 7901 7902 sal_memset (&rval, 0, sizeof(rval)); 7903 soc_reg_field_set(unit, THDIQEN_PORT_PAUSE_ENABLE_64r, &rval, 7904 PORT_PAUSE_ENABLEf, val); 7905 SOC_IF_ERROR_RETURN 7906 (soc_reg32_set(unit, THDIQEN_PORT_PAUSE_ENABLE_64r,REG_PORT_ANY, 7907 0, rval)); 7908 7909 sal_memset (&rval, 0, sizeof(rval)); 7910 soc_reg_field_set(unit, THDIRQE_PORT_PAUSE_ENABLE_64r, &rval, 7911 PORT_PAUSE_ENABLEf, val); 7912 SOC_IF_ERROR_RETURN 7913 (soc_reg32_set(unit, THDIRQE_PORT_PAUSE_ENABLE_64r,REG_PORT_ANY, 7914 0, rval)); 7915 7916 sal_memset (&rval, 0, sizeof(rval)); 7917 soc_reg_field_set(unit, THDIEMA_PORT_PAUSE_ENABLE_64r, &rval, 7918 PORT_PAUSE_ENABLEf, val); 7919 SOC_IF_ERROR_RETURN 7920 (soc_reg32_set(unit, THDIEMA_PORT_PAUSE_ENABLE_64r,REG_PORT_ANY, 7921 0, rval)); 7922 7923 sal_memset (&rval, 0, sizeof(rval)); 7924 soc_reg_field_set(unit, PORT_PAUSE_ENABLE_64r, &rval, 7925 PORT_PAUSE_ENABLEf, val); 7926 SOC_IF_ERROR_RETURN 7927 (soc_reg32_set(unit, PORT_PAUSE_ENABLE_64r,REG_PORT_ANY, 7928 0, rval)); 7929 } 7930 /* ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ 7931 /* OpNode related config for remaining OpNodes */ 7932 /* (assuming internal memory settings) */ 7933 /* ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ 7934 for (op_node = soc_mem_index_min(unit,MMU_THDO_OPNCONFIG_CELLm); 7935 op_node <= soc_mem_index_max(unit,MMU_THDO_OPNCONFIG_CELLm); 7936 op_node++) { 7937 temp_val = 0 ; 7938 SOC_IF_ERROR_RETURN(READ_MMU_THDO_OPNCONFIG_CELLm(unit, 7939 MEM_BLOCK_ANY,op_node , 7940 &mmu_thdo_opnconfig_cell_entry)); 7941 temp_val = soc_mem_field32_get(unit, MMU_THDO_OPNCONFIG_CELLm, 7942 &mmu_thdo_opnconfig_cell_entry, 7943 OPN_SHARED_LIMIT_CELLf); 7944 if (temp_val == 0) { 7945 soc_mem_field32_set(unit, MMU_THDO_OPNCONFIG_CELLm, 7946 &mmu_thdo_opnconfig_cell_entry, 7947 OPN_SHARED_LIMIT_CELLf, 7948 output_port_threshold-> 7949 min_grntd_tot_shr_queue_cells_int_buff); 7950 temp_val = output_port_threshold-> 7951 min_grntd_tot_shr_queue_cells_int_buff - 7952 (2 * general_info->ether_mtu_cells_for_int_buff); 7953 soc_mem_field32_set(unit, MMU_THDO_OPNCONFIG_CELLm, 7954 &mmu_thdo_opnconfig_cell_entry, 7955 OPN_SHARED_RESET_VALUE_CELLf, temp_val); 7956 soc_mem_field32_set(unit, MMU_THDO_OPNCONFIG_CELLm, 7957 &mmu_thdo_opnconfig_cell_entry, 7958 PORT_LIMIT_ENABLE_CELLf, 0); 7959 SOC_IF_ERROR_RETURN(WRITE_MMU_THDO_OPNCONFIG_CELLm(unit, 7960 MEM_BLOCK_ALL,op_node, 7961 &mmu_thdo_opnconfig_cell_entry)); 7962 } 7963 } 7964 for (op_node = soc_mem_index_min(unit,MMU_THDO_OPNCONFIG_QENTRYm); 7965 op_node <= soc_mem_index_max(unit,MMU_THDO_OPNCONFIG_QENTRYm); 7966 op_node++) { 7967 temp_val = 0 ; 7968 SOC_IF_ERROR_RETURN(READ_MMU_THDO_OPNCONFIG_QENTRYm(unit, 7969 MEM_BLOCK_ANY,op_node , 7970 &mmu_thdo_opnconfig_qentry_entry)); 7971 temp_val = soc_mem_field32_get(unit, MMU_THDO_OPNCONFIG_QENTRYm, 7972 &mmu_thdo_opnconfig_qentry_entry, 7973 OPN_SHARED_LIMIT_QENTRYf); 7974 if (temp_val == 0) { 7975 soc_mem_field32_set(unit, MMU_THDO_OPNCONFIG_QENTRYm, 7976 &mmu_thdo_opnconfig_qentry_entry, OPN_SHARED_LIMIT_QENTRYf, 7977 output_port_threshold->min_grntd_tot_shr_queue_cells_EQEs); 7978 7979 temp_val = output_port_threshold-> 7980 min_grntd_tot_shr_queue_cells_EQEs - 2; 7981 soc_mem_field32_set(unit, MMU_THDO_OPNCONFIG_QENTRYm, 7982 &mmu_thdo_opnconfig_qentry_entry, 7983 OPN_SHARED_RESET_VALUE_QENTRYf, temp_val); 7984 7985 soc_mem_field32_set(unit, MMU_THDO_OPNCONFIG_QENTRYm, 7986 &mmu_thdo_opnconfig_qentry_entry, 7987 PORT_LIMIT_ENABLE_QENTRYf, 0); 7988 /* 7989 soc_mem_field32_set(unit, MMU_THDO_OPNCONFIG_QENTRYm, 7990 &mmu_thdo_opnconfig_qentry_entry, 7991 PIDf, port); 7992 */ 7993 SOC_IF_ERROR_RETURN(WRITE_MMU_THDO_OPNCONFIG_QENTRYm(unit, 7994 MEM_BLOCK_ALL,op_node , 7995 &mmu_thdo_opnconfig_qentry_entry)); 7996 } 7997 } 7998 /* ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ 7999 /* Subport queue Settings */ 8000 /* (Assuming lossless-internal memory operation) */ 8001 /* ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ 8002 for (sub_port = SOC_SB2_MIN_SUBPORT_INDEX; 8003 sub_port <= SOC_SB2_MAX_SUBPORTS; 8004 sub_port ++) { 8005 if ( si->port_uc_cosq_base[sub_port] != 0) { 8006 for (queue = si->port_uc_cosq_base[sub_port]; 8007 queue < si->port_uc_cosq_base[sub_port] + 8008 si->port_num_uc_cosq[sub_port]; 8009 queue++) { 8010 LOG_VERBOSE(BSL_LS_SOC_COMMON, 8011 (BSL_META_U(unit, 8012 "sub_port:%d queue:%d"), sub_port, queue)); 8013 SOC_IF_ERROR_RETURN( 8014 _soc_saber2_mmu_config_extra_queue(unit, queue, 8015 &_soc_sb2_mmu_params, 8016 output_port_threshold)); 8017 } 8018 } 8019 } 8020 /* ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ 8021 /* Extended Queue(BCM_COSQ_GPORT_SUBSCRIBE) Settings */ 8022 /* ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ 8023 8024 for (queue = si->port_uc_cosq_base[SB2_MAX_PHYSICAL_PORTS] + 8025 si->port_num_uc_cosq[SB2_MAX_PHYSICAL_PORTS]; 8026 queue <= soc_mem_index_max(unit,MMU_THDO_QCONFIG_CELLm); 8027 queue++) { 8028 SOC_IF_ERROR_RETURN( 8029 _soc_saber2_mmu_config_extra_queue(unit, queue, 8030 &_soc_sb2_mmu_params, 8031 output_port_threshold)); 8032 } 8033 return SOC_E_NONE; 8034 } 8035 8036 int _soc_saber2_mmu_init_extn(int unit) { 8037 int port=0; 8038 uint32 rval=0; 8039 8040 for (port = SB2_CMIC; port < SB2_LPBK; port++) { 8041 rval = 0; 8042 if (SOC_PBMP_MEMBER((PBMP_ALL(unit)), port)) { 8043 soc_reg_field_set(unit, PORT_MAX_PKT_SIZEr, &rval, 8044 PORT_MAX_PKT_SIZEf,49); 8045 } 8046 SOC_IF_ERROR_RETURN(WRITE_PORT_MAX_PKT_SIZEr(unit, port, rval)); 8047 SOC_IF_ERROR_RETURN(WRITE_THDIEXT_PORT_MAX_PKT_SIZEr(unit, port, 8048 rval)); 8049 SOC_IF_ERROR_RETURN(WRITE_THDIEMA_PORT_MAX_PKT_SIZEr(unit, port, 8050 rval)); 8051 SOC_IF_ERROR_RETURN(WRITE_THDIRQE_PORT_MAX_PKT_SIZEr(unit, port, 8052 rval)); 8053 SOC_IF_ERROR_RETURN(WRITE_THDIQEN_PORT_MAX_PKT_SIZEr(unit, port, 8054 rval)); 8055 rval = 0xffff; 8056 SOC_IF_ERROR_RETURN(WRITE_THDIEXT_PORT_PRI_XON_ENABLEr(unit, port, 8057 rval)); 8058 SOC_IF_ERROR_RETURN(WRITE_THDIEXT_PORT_PRI_XON_ENABLEr(unit, port, 8059 rval)); 8060 SOC_IF_ERROR_RETURN(WRITE_THDIEMA_PORT_PRI_XON_ENABLEr(unit, port, 8061 rval)); 8062 SOC_IF_ERROR_RETURN(WRITE_THDIRQE_PORT_PRI_XON_ENABLEr(unit, port, 8063 rval)); 8064 SOC_IF_ERROR_RETURN(WRITE_THDIQEN_PORT_PRI_XON_ENABLEr(unit, port, 8065 rval)); 8066 } 8067 8068 rval = 0; 8069 for (port = SB2_CMIC; port < SB2_LPBK; port++) { 8070 if (((*sb2_port_to_block_subports[unit])[port - 1] == 0) || 8071 (IS_HG_PORT(unit, port)) || (IS_XE_PORT(unit, port)) || 8072 (IS_LB_PORT(unit,port))) { 8073 if (soc_reg_field_valid(unit, MMU_ENQ_IP_PRI_TO_PG_PROFILE_0r, 8074 sb2_srcport_field_names[port])) { 8075 /* PRIx_GRP = 0x7 */ 8076 soc_reg_field_set(unit, MMU_ENQ_IP_PRI_TO_PG_PROFILE_0r, 8077 &rval, sb2_srcport_field_names[port], 3); 8078 } 8079 } 8080 } 8081 SOC_IF_ERROR_RETURN( 8082 WRITE_MMU_ENQ_IP_PRI_TO_PG_PROFILE_0r_REG32(unit, rval)); 8083 8084 return SOC_E_NONE; 8085 } 8086 8087 int _soc_saber2_mmu_reconfigure(int unit, int port) 8088 { 8089 SOC_IF_ERROR_RETURN(_soc_saber2_mmu_init_helper(unit, port)); 8090 LOG_CLI((BSL_META_U(unit, 8091 "MMU is reconfigured \n"))); 8092 return SOC_E_NONE; 8093 } 8094 8095 STATIC int 8096 _soc_saber2_mmu_port_init(int unit) 8097 { 8098 uint32 rval =0 ; 8099 soc_info_t *si = &SOC_INFO(unit); 8100 uint32 max_depth_limit = 512; 8101 uint32 fifo_start_addr = 0; 8102 int egr_fifo_depth, threshold, port_bw, start_threshold, padding; 8103 int block_port, first_port = -1, last_port = -1, block = 0, loop; 8104 int port, port_incr = 1; 8105 int valid = FALSE; 8106 int cfg_num = 0; /* Internal Cfg number */ 8107 8108 for (port = SB2_CMIC; port < SB2_MAX_LOGICAL_PORTS; port += port_incr) { 8109 port_incr = 1; 8110 valid = FALSE; 8111 if (!(IS_CPU_PORT(unit,port) || IS_LB_PORT(unit,port))) { 8112 /* coverity[overrun-local : FALSE] */ 8113 block = (*sb2_port_to_block[unit])[port - 1]; 8114 } 8115 8116 if (IS_CPU_PORT(unit, port)) { 8117 egr_fifo_depth = 2; 8118 threshold = 1; 8119 padding = 0; 8120 port_bw = 63; 8121 start_threshold = 1; 8122 } else if (IS_LB_PORT(unit, port)) { 8123 /* For following 2 configs LB Port B/w is 12.5G else 2.5G 8124 1) 56260 Cfg=1 (IntCfg=12) 8125 2) 56460 Cfg=6 (IntCfg=6) 8126 */ 8127 SOC_IF_ERROR_RETURN(_soc_saber2_get_cfg_num(unit, &cfg_num)); 8128 if ((12 == cfg_num) || (6 == cfg_num)) { 8129 egr_fifo_depth = (IS_EXT_MEM_PORT(unit, port)) ? 53 : 10; 8130 threshold = (IS_EXT_MEM_PORT(unit, port)) ? 49 : 1; 8131 port_bw = 325; 8132 start_threshold = 48; 8133 } else { 8134 egr_fifo_depth = (IS_EXT_MEM_PORT(unit, port)) ? 14 : 2; 8135 threshold = 1; 8136 port_bw = 63; 8137 start_threshold = 13; 8138 } 8139 padding = 0; 8140 } else if (IS_GE_PORT(unit, port)) { 8141 if (si->port_speed_max[port] == 2500) { 8142 egr_fifo_depth = (IS_EXT_MEM_PORT(unit, port)) ? 19 : 2; 8143 threshold = (IS_EXT_MEM_PORT(unit, port)) ? 15 : 1; 8144 padding = 19 - egr_fifo_depth; 8145 port_bw = 63; 8146 start_threshold = 14; 8147 } else { 8148 egr_fifo_depth = (IS_EXT_MEM_PORT(unit, port)) ? 10 : 2; 8149 threshold = (IS_EXT_MEM_PORT(unit, port)) ? 8 : 1; 8150 padding = 10 - egr_fifo_depth; 8151 port_bw = 25; 8152 start_threshold = 7; 8153 } 8154 } else if ((si->port_speed_max[port] != 0) && 8155 (si->port_speed_max[port] <= 13000)) { 8156 egr_fifo_depth = (IS_EXT_MEM_PORT(unit, port)) ? 53 : 10; 8157 threshold = (IS_EXT_MEM_PORT(unit, port)) ? 49 : 1; 8158 if (IS_XL_PORT(unit, port)) { 8159 /* Eagle core will always be initialized to worst-case 8160 * conditions, so no need for extra padding */ 8161 padding = 53 - egr_fifo_depth; 8162 } else { 8163 /* Actual required FIFO size is 53, 8164 * but padded to 76 to support 4x2.5G flex */ 8165 padding = 76 - egr_fifo_depth; 8166 port_incr = 4; 8167 } 8168 port_bw = 325; 8169 start_threshold = 48; 8170 } else if(SOC_WARM_BOOT(unit) && (block == 6) && 8171 (si->port_speed_max[port] == 0)) { 8172 if((eagle_n2_mode) && ((port == 26) || (port == 28))) { 8173 continue; 8174 } 8175 if((eagle_n4s_mode) && ((port == 26) || (port == 28))) { 8176 egr_fifo_depth = (IS_EXT_MEM_PORT(unit, port)) ? 10 : 2; 8177 threshold = (IS_EXT_MEM_PORT(unit, port)) ? 8 : 1; 8178 padding = 10 - egr_fifo_depth; 8179 port_bw = 25; 8180 start_threshold = 7; 8181 valid = TRUE; 8182 } else if(((eagle_n4s_mode) && (port == 27)) || 8183 (!eagle_n4s_mode)){ 8184 egr_fifo_depth = (IS_EXT_MEM_PORT(unit, port)) ? 53 : 10; 8185 threshold = (IS_EXT_MEM_PORT(unit, port)) ? 49 : 1; 8186 padding = 53 - egr_fifo_depth; 8187 port_bw = 325; 8188 start_threshold = 48; 8189 valid = TRUE; 8190 } else { 8191 /* Ideally should not hit this block. */ 8192 return SOC_E_INTERNAL; 8193 } 8194 } else { /* > 13G */ 8195 if (!SOC_PBMP_MEMBER((PBMP_ALL(unit)), port)) { 8196 continue; 8197 } 8198 return SOC_E_PARAM; 8199 } 8200 8201 if (SOC_PBMP_MEMBER((PBMP_ALL(unit)), port)) { 8202 SOC_IF_ERROR_RETURN(READ_DEQ_EFIFO_CFGr(unit, port, &rval)); 8203 soc_reg_field_set(unit, DEQ_EFIFO_CFGr, &rval, 8204 EGRESS_FIFO_START_ADDRESSf, fifo_start_addr); 8205 soc_reg_field_set(unit, DEQ_EFIFO_CFGr, &rval, 8206 EGRESS_FIFO_DEPTHf, egr_fifo_depth); 8207 soc_reg_field_set(unit, DEQ_EFIFO_CFGr, &rval, 8208 EGRESS_FIFO_XMIT_THRESHOLDf, threshold); 8209 } 8210 8211 if (!(IS_CPU_PORT(unit,port) || IS_LB_PORT(unit,port))) { 8212 loop = 0; first_port = -1; last_port = -1; 8213 while(loop < 4) { 8214 block_port = (*sb2_block_ports[unit])[block][loop]; 8215 if((eagle_n2_mode) && 8216 ((block_port == 26) || (block_port == 28))) { 8217 loop++; 8218 continue; 8219 } 8220 if (SOC_PBMP_MEMBER((PBMP_ALL(unit)), block_port) || 8221 (valid == TRUE)) { 8222 if(first_port == -1) { 8223 first_port = block_port; 8224 } 8225 last_port = block_port; 8226 } 8227 loop++; 8228 } 8229 if(port == first_port) { 8230 block_max_startaddr[block] = fifo_start_addr; 8231 } 8232 if (port == last_port) { 8233 block_max_endaddr[block] = 8234 fifo_start_addr + egr_fifo_depth + padding - 1; 8235 } 8236 } 8237 fifo_start_addr += egr_fifo_depth + padding; 8238 8239 if(fifo_start_addr > max_depth_limit) { 8240 LOG_ERROR(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 8241 "DEQ_EFIFO_CFG limit crossed: Available limit %d" 8242 "port:%d depth:%d fifo_start_addr=%d\n"), 8243 max_depth_limit, port, egr_fifo_depth, fifo_start_addr)); 8244 return SOC_E_RESOURCE; 8245 } 8246 8247 if (SOC_PBMP_MEMBER((PBMP_ALL(unit)), port)) { 8248 SOC_IF_ERROR_RETURN(WRITE_DEQ_EFIFO_CFGr(unit, port, rval)); 8249 8250 /* Port BW Ctrl */ 8251 SOC_IF_ERROR_RETURN(READ_TOQ_PORT_BW_CTRLr(unit, port, &rval)); 8252 soc_reg_field_set(unit, TOQ_PORT_BW_CTRLr, &rval, 8253 PORT_BWf, port_bw); 8254 soc_reg_field_set(unit, TOQ_PORT_BW_CTRLr, &rval, 8255 START_THRESHOLDf, start_threshold); 8256 SOC_IF_ERROR_RETURN(WRITE_TOQ_PORT_BW_CTRLr(unit, port, rval)); 8257 } 8258 } 8259 return SOC_E_NONE; 8260 } 8261 8262 STATIC int 8263 _soc_sb2_post_mmu_init(int unit) { 8264 8265 txlp_port_addr_map_table_entry_t txlp_port_addr_map_table_entry={{0}}; 8266 uint32 start_addr=0; 8267 uint32 end_addr=0; 8268 int port = 0; 8269 int loop; 8270 soc_info_t *si; 8271 uint32 rval; 8272 8273 si = &SOC_INFO(unit); 8274 8275 if (SAL_BOOT_QUICKTURN) { 8276 soc_pbmp_t link_pbmp; 8277 epc_link_bmap_entry_t epc_link_bmap_entry={{0}}; 8278 8279 SOC_PBMP_ASSIGN(link_pbmp, PBMP_ALL(unit)); 8280 SOC_IF_ERROR_RETURN(READ_EPC_LINK_BMAPm(unit, MEM_BLOCK_ALL, 0, 8281 &epc_link_bmap_entry)); 8282 soc_mem_pbmp_field_set(unit, EPC_LINK_BMAPm, &epc_link_bmap_entry, 8283 PORT_BITMAPf,&link_pbmp); 8284 SOC_IF_ERROR_RETURN(WRITE_EPC_LINK_BMAPm( 8285 unit, MEM_BLOCK_ALL, 0, &epc_link_bmap_entry)); 8286 } 8287 8288 if ((si->block_valid[TXLP0_BLOCK(unit)] == 0)) { 8289 /* TXLP related ports are not valid */ 8290 return SOC_E_NONE; 8291 } 8292 8293 SOC_IF_ERROR_RETURN(READ_TXLP_HW_RESET_CONTROL_1r(unit, 1, &rval)); 8294 soc_reg_field_set(unit, TXLP_HW_RESET_CONTROL_1r, &rval, COUNTf, 0x84); 8295 soc_reg_field_set(unit, TXLP_HW_RESET_CONTROL_1r, &rval, VALIDf, 1); 8296 SOC_IF_ERROR_RETURN(WRITE_TXLP_HW_RESET_CONTROL_1r(unit, 1, rval)); 8297 8298 /* TXLP_PORT_ADDR_MAP_TABLE */ 8299 for(loop=0, start_addr=0,port=1 ; loop < SB2_MAX_PORTS_PER_BLOCK; 8300 loop++, port++) { 8301 if (si->port_speed_max[port] <= 2500) { 8302 end_addr = start_addr + (( 8 * 4) - 1); /* 8 cells */ 8303 } else if(si->port_speed_max[port] <= 13000) { 8304 end_addr = start_addr + (( 16 * 4) - 1); 8305 } else { 8306 return SOC_E_PARAM; 8307 } 8308 8309 sal_memset(&txlp_port_addr_map_table_entry,0, 8310 sizeof(txlp_port_addr_map_table_entry_t)); 8311 soc_TXLP_PORT_ADDR_MAP_TABLEm_field_set(unit, 8312 &txlp_port_addr_map_table_entry,START_ADDRf,&start_addr); 8313 soc_TXLP_PORT_ADDR_MAP_TABLEm_field_set(unit, 8314 &txlp_port_addr_map_table_entry,END_ADDRf,&end_addr); 8315 start_addr = end_addr+1; 8316 8317 SOC_IF_ERROR_RETURN(WRITE_TXLP_PORT_ADDR_MAP_TABLEm( 8318 unit,SOC_INFO(unit).txlp_block[0], loop, 8319 &txlp_port_addr_map_table_entry)); 8320 } 8321 8322 return SOC_E_NONE; 8323 } 8324 8325 8326 int 8327 soc_saber2_perq_flex_counters_init(int unit, uint32 drop_mask) 8328 { 8329 _soc_saber2_counter_info_t *counter_info; 8330 uint32 rval; 8331 int index, field_index, i, j, i_max = 2, j_max = 16; 8332 int flags = 0; 8333 int counter_index = 0, total_num_elem = 6, elem_size = 2; 8334 int num_elem = 0; 8335 _soc_saber2_counter_type_t type = _SOC_COUNTER_TYPE_MAX; 8336 soc_counter_non_dma_id_t non_dma_id; 8337 int enq_stats = 0; 8338 _sb2_cosq_counter_mem_map_t *mem_map; 8339 uint16 dev_id; 8340 uint8 rev_id; 8341 soc_reg_t dtype_reg[] = { 8342 CTR_DEQ_DTYPE_TBL0r, 8343 CTR_DEQ_DTYPE_TBL1r 8344 }; 8345 soc_field_t dtype_field[] = { 8346 DTYPE0f, DTYPE1f, DTYPE2f, 8347 DTYPE3f, DTYPE4f, DTYPE5f, 8348 DTYPE6f, DTYPE7f, DTYPE8f, 8349 DTYPE9f, DTYPE10f, DTYPE11f, 8350 DTYPE12f, DTYPE13f,DTYPE14f, 8351 DTYPE15f 8352 }; 8353 soc_field_t act_field[3] = {ACTIVE0f, ACTIVE1f, ACTIVE2f}; 8354 soc_field_t seg_field[3] = {SEG0f, SEG1f, SEG2f}; 8355 8356 soc_sb2_cosq_counter_mem_map_get(unit, &num_elem, &mem_map); 8357 8358 soc_cm_get_id(unit, &dev_id, &rev_id); 8359 if ((dev_id == BCM56233_DEVICE_ID) || 8360 (SOC_IS_METROLITE(unit))) { 8361 elem_size = 1; 8362 total_num_elem = 3; 8363 } 8364 8365 /* Setup MMU counter pool segment start address, consider each 512 block 8366 as separate segment */ 8367 for (i = 0; i < total_num_elem; i++) { 8368 if ((dev_id == BCM56233_DEVICE_ID) || 8369 (SOC_IS_METROLITE(unit))) { 8370 rval = 0; 8371 soc_reg_field_set(unit, CTR_SEGMENT_STARTr, &rval, 8372 SEG_STARTf, (i * 512)); 8373 SOC_IF_ERROR_RETURN 8374 (soc_reg32_set(unit, CTR_SEGMENT_STARTr,REG_PORT_ANY, 8375 i, rval)); 8376 } else { 8377 if (!soc_feature(unit, soc_feature_cosq_gport_stat_ability) && 8378 ((i % 2) != 0)) { 8379 /* 8380 * Create 3 segments each with 1K counters 8381 * Seg0(total enq drop pkts) seg_start address 0 8382 * Seg2(red enq drop pkts) seg_start address 2 * 512 8383 * Seg4(deq stats)) seg_start_address 3 * 512 8384 */ 8385 continue; 8386 } 8387 rval = 0; 8388 soc_reg_field_set(unit, CTR_SEGMENT_STARTr, &rval, 8389 SEG_STARTf, (i * 512)); 8390 SOC_IF_ERROR_RETURN 8391 (soc_reg32_set(unit, CTR_SEGMENT_STARTr,REG_PORT_ANY, 8392 i, rval)); 8393 } 8394 } 8395 8396 /* Default configuration */ 8397 /* Cosq_stats - 8398 * CTR_FLEX_COUNT_0 = Total ENQ discarded 8399 * CTR_FLEX_COUNT_2 = Red ENQ discarded 8400 * CTR_FLEX_COUNT_4 = Total DEQ 8401 */ 8402 8403 /* Cosq_gport_stats - 8404 * CTR_FLEX_COUNT_0 = Total ENQ discarded 8405 * CTR_FLEX_COUNT_1 = Total ENQ Accepted 8406 * CTR_FLEX_COUNT_2 = Green ENQ discarded 8407 * CTR_FLEX_COUNT_3 = Yellow ENQ discarded 8408 * CTR_FLEX_COUNT_4 = Red packet ENQ discarded 8409 * CTR_FLEX_COUNT_5 = Total DEQ 8410 */ 8411 counter_info = _soc_saber2_counter_info; 8412 8413 8414 /* reset the previously configured registers*/ 8415 rval = 0; 8416 for ( i = 0; i < 3; i++) { 8417 soc_reg_field_set(unit, CTR_ENQ_STATS_CFGr, &rval, act_field[i], 0); 8418 soc_reg_field_set(unit, CTR_ENQ_STATS_CFGr, &rval, seg_field[i], 0); 8419 SOC_IF_ERROR_RETURN 8420 (soc_reg32_set(unit, CTR_ENQ_STATS_CFGr,REG_PORT_ANY,0, rval)); 8421 } 8422 8423 rval = 0; 8424 soc_reg_field_set(unit, CTR_DEQ_STATS_CFGr, &rval, ACTIVE0f, 0); 8425 soc_reg_field_set(unit, CTR_DEQ_STATS_CFGr, &rval, SEG0f, 0); 8426 SOC_IF_ERROR_RETURN 8427 (soc_reg32_set(unit, CTR_DEQ_STATS_CFGr, REG_PORT_ANY,0 , rval)); 8428 8429 SOC_IF_ERROR_RETURN (READ_CTR_SYS_CONTROLr (unit, &rval)); 8430 soc_reg_field_set (unit, CTR_SYS_CONTROLr, &rval, DEQ_FIRST_BRICKf, 0); 8431 soc_reg_field_set (unit, CTR_SYS_CONTROLr, &rval, DEQ_LAST_BRICKf, 0); 8432 SOC_IF_ERROR_RETURN (WRITE_CTR_SYS_CONTROLr (unit, rval)); 8433 8434 /*intializing the segment in counter info */ 8435 for ( i =0; i < 6; i++) { 8436 _soc_saber2_counter_info[i].segment = 0; 8437 } 8438 8439 for (counter_index = 0; counter_index < num_elem; counter_index+=elem_size) { 8440 8441 non_dma_id = mem_map[counter_index].non_dma_id; 8442 field_index = counter_index/elem_size; 8443 rval = 0; 8444 if ((non_dma_id == SOC_COUNTER_NON_DMA_COSQ_DROP_PKT)|| 8445 (non_dma_id == SOC_COUNTER_NON_DMA_COSQ_ACCEPT_PKT)) { 8446 soc_reg_field_set(unit, CTR_ENQ_STATS_CFGr, &rval, act_field[field_index], 1); 8447 soc_reg_field_set(unit, CTR_ENQ_STATS_CFGr, &rval, seg_field[field_index], counter_index); 8448 } 8449 switch (non_dma_id){ 8450 case SOC_COUNTER_NON_DMA_COSQ_DROP_PKT: 8451 type = _SOC_COUNTER_TYPE_DROP_ENQ; 8452 for ( i = _SOC_COUNTER_TYPE_DROP_ENQ_GREEN; 8453 i <= _SOC_COUNTER_TYPE_DROP_ENQ_RED; i++) { 8454 SOC_IF_ERROR_RETURN 8455 (soc_reg32_set(unit, CTR_ENQ_STATS_CFGr, 8456 REG_PORT_ANY, 8457 counter_info[i].index, 8458 rval)); 8459 flags |= (1 << i); 8460 } 8461 break; 8462 case SOC_COUNTER_NON_DMA_COSQ_ACCEPT_PKT: 8463 type = _SOC_COUNTER_TYPE_ACCEPT_ENQ; 8464 for ( i = _SOC_COUNTER_TYPE_ACCEPT_ENQ_GREEN; 8465 i <= _SOC_COUNTER_TYPE_ACCEPT_ENQ_RED; i++) { 8466 SOC_IF_ERROR_RETURN 8467 (soc_reg32_set(unit, CTR_ENQ_STATS_CFGr, 8468 REG_PORT_ANY, 8469 counter_info[i].index, 8470 rval)); 8471 flags |= (1 << i); 8472 } 8473 break; 8474 case SOC_COUNTER_NON_DMA_COSQ_DROP_PKT_GREEN: 8475 type = _SOC_COUNTER_TYPE_DROP_ENQ_GREEN; 8476 break; 8477 8478 case SOC_COUNTER_NON_DMA_COSQ_DROP_PKT_RED: 8479 type = _SOC_COUNTER_TYPE_DROP_ENQ_RED; 8480 break; 8481 8482 case SOC_COUNTER_NON_DMA_COSQ_DROP_PKT_YELLOW: 8483 type = _SOC_COUNTER_TYPE_DROP_ENQ_YELLOW; 8484 break; 8485 8486 case SOC_COUNTER_NON_DMA_COSQ_ACCEPT_PKT_GREEN: 8487 type = _SOC_COUNTER_TYPE_ACCEPT_ENQ_GREEN; 8488 break; 8489 8490 case SOC_COUNTER_NON_DMA_COSQ_ACCEPT_PKT_RED: 8491 type = _SOC_COUNTER_TYPE_ACCEPT_ENQ_RED; 8492 break; 8493 8494 case SOC_COUNTER_NON_DMA_COSQ_ACCEPT_PKT_YELLOW: 8495 type = _SOC_COUNTER_TYPE_ACCEPT_ENQ_YELLOW; 8496 break; 8497 8498 case SOC_COUNTER_NON_DMA_EGR_PERQ_XMT_PKT: 8499 type = _SOC_COUNTER_TYPE_ACCEPT_DEQ; 8500 /* enable deq stats */ 8501 if (SOC_IS_METROLITE(unit)) { 8502 i_max = 1; 8503 j_max = 14; 8504 } 8505 for (i = 0; i < i_max; i++) { 8506 rval = 0; 8507 for (j = 0; j < j_max; j++) { 8508 if ((dtype_reg[i] == CTR_DEQ_DTYPE_TBL1r) && (j > 13)) { 8509 continue; 8510 } 8511 soc_reg_field_set(unit, dtype_reg[i], &rval, dtype_field[j], 2); 8512 } 8513 SOC_IF_ERROR_RETURN 8514 (soc_reg32_set(unit, dtype_reg[i], REG_PORT_ANY, 0, rval)); 8515 } 8516 /* set deq stats config */ 8517 rval = 0; 8518 index = counter_info[type].index; 8519 soc_reg_field_set(unit, CTR_DEQ_STATS_CFGr, &rval, ACTIVE0f, 1); 8520 soc_reg_field_set(unit, CTR_DEQ_STATS_CFGr, &rval, SEG0f, counter_index); 8521 SOC_IF_ERROR_RETURN 8522 (soc_reg32_set(unit, CTR_DEQ_STATS_CFGr, REG_PORT_ANY, index, rval)); 8523 8524 SOC_IF_ERROR_RETURN (READ_CTR_SYS_CONTROLr (unit, &rval)); 8525 soc_reg_field_set (unit, CTR_SYS_CONTROLr, &rval, DEQ_FIRST_BRICKf, counter_index); 8526 soc_reg_field_set (unit, CTR_SYS_CONTROLr, &rval, DEQ_LAST_BRICKf, counter_index+ 1); 8527 SOC_IF_ERROR_RETURN (WRITE_CTR_SYS_CONTROLr (unit, rval)); 8528 enq_stats++; 8529 break; 8530 default: 8531 /*should not reach here*/ 8532 break; 8533 } 8534 8535 _soc_saber2_counter_info[type].segment = counter_index; 8536 if ((type >= _SOC_COUNTER_TYPE_DROP_ENQ_GREEN) 8537 && (type <= _SOC_COUNTER_TYPE_ACCEPT_ENQ_RED)){ 8538 8539 rval = 0; 8540 index = counter_info[type].index; 8541 if (flags & (1 << type)) { 8542 SOC_IF_ERROR_RETURN 8543 (soc_reg32_get(unit, CTR_ENQ_STATS_CFGr, 8544 REG_PORT_ANY, index, &rval)); 8545 } 8546 soc_reg_field_set(unit, CTR_ENQ_STATS_CFGr, &rval, act_field[field_index-enq_stats], 1); 8547 soc_reg_field_set(unit, CTR_ENQ_STATS_CFGr, &rval, seg_field[field_index-enq_stats], counter_index); 8548 SOC_IF_ERROR_RETURN 8549 (soc_reg32_set(unit, CTR_ENQ_STATS_CFGr, 8550 REG_PORT_ANY, 8551 counter_info[type].index, 8552 rval)); 8553 } 8554 } 8555 /* This is set to 1 so that we count only thdo drops in the out drops*/ 8556 SOC_IF_ERROR_RETURN(READ_THDO_DROP_CTR_CONFIGr(unit, &rval)); 8557 8558 /*drop mask eliminates the packet drop counts for masked out drop types.*/ 8559 soc_reg_field_set(unit, THDO_DROP_CTR_CONFIGr, &rval, OP_DROP_MASKf,drop_mask); 8560 soc_reg_field_set(unit, THDO_DROP_CTR_CONFIGr, &rval, OP_CNT_CFGf, 1); 8561 8562 SOC_IF_ERROR_RETURN(WRITE_THDO_DROP_CTR_CONFIGr(unit, rval)); 8563 8564 return SOC_E_NONE; 8565 } 8566 8567 int _soc_sb2_invalid_parent_index(int unit, int level) 8568 { 8569 int index_max = 0; 8570 8571 switch (level) { 8572 case SOC_KT2_NODE_LVL_ROOT: 8573 index_max = 0; 8574 break; 8575 case SOC_KT2_NODE_LVL_L0: 8576 index_max = (1 << soc_mem_field_length(unit, LLS_L0_PARENTm, C_PARENTf)) - 1; 8577 break; 8578 case SOC_KT2_NODE_LVL_L1: 8579 index_max = (1 << soc_mem_field_length(unit, LLS_L1_PARENTm, C_PARENTf)) - 1; 8580 break; 8581 case SOC_KT2_NODE_LVL_L2: 8582 index_max = (1 << soc_mem_field_length(unit, LLS_L2_PARENTm, C_PARENTf)) - 1; 8583 break; 8584 default: 8585 break; 8586 8587 } 8588 8589 return index_max; 8590 } 8591 8592 #define INVALID_PARENT(unit, level) _soc_sb2_invalid_parent_index((unit),(level)) 8593 8594 /* Programming all the entries with the Invalid Parent Pointer */ 8595 int 8596 _soc_saber2_mmu_set_invalid_parent(int unit) 8597 { 8598 int level, index_max, index; 8599 soc_mem_t mem; 8600 uint32 entry[SOC_MAX_MEM_WORDS]; 8601 8602 for (level = SOC_KT2_NODE_LVL_L0; level <= SOC_KT2_NODE_LVL_L2; 8603 level++) { 8604 mem = _SOC_KT2_NODE_PARENT_MEM(level); 8605 /* coverity[negative_returns : FALSE] */ 8606 index_max = soc_mem_index_max(unit, mem); 8607 for (index = 0; index <= index_max; index++) { 8608 /* During reboot, mem reinitialized. So no need to read from cache */ 8609 SOC_IF_ERROR_RETURN 8610 (soc_mem_cache_invalidate(unit, mem, MEM_BLOCK_ALL, index)); 8611 SOC_IF_ERROR_RETURN 8612 (soc_mem_read(unit, mem, MEM_BLOCK_ALL, index, &entry)); 8613 soc_mem_field32_set(unit, mem, entry, 8614 C_PARENTf, INVALID_PARENT(unit,level)); 8615 SOC_IF_ERROR_RETURN 8616 (soc_mem_write(unit, mem, MEM_BLOCK_ALL, index, &entry)); 8617 } 8618 } 8619 return SOC_E_NONE; 8620 } 8621 8622 STATIC int 8623 _soc_saber2_mmu_init(int unit) 8624 { 8625 uint32 rval; 8626 int mmu_init_usec, i; 8627 soc_info_t *si; 8628 soc_timeout_t to; 8629 mmu_aging_lmt_int_entry_t age_entry; 8630 int count; 8631 uint16 dev_id; 8632 uint8 rev_id; 8633 uint64 rval1; 8634 int port; 8635 uint32 ext_pbmp_count=0; 8636 pbmp_t ext_pbmp; 8637 int rd_phase, wr_phase , freq_loc; 8638 8639 si = &SOC_INFO(unit); 8640 soc_cm_get_id(unit, &dev_id, &rev_id); 8641 8642 /* Init Link List Scheduler */ 8643 rval = 0; 8644 soc_reg_field_set(unit, LLS_SOFT_RESETr, &rval, SOFT_RESETf, 0); 8645 SOC_IF_ERROR_RETURN(WRITE_LLS_SOFT_RESETr(unit, rval)); 8646 8647 rval = 0; 8648 soc_reg_field_set(unit, LLS_INITr, &rval, INITf, 1); 8649 SOC_IF_ERROR_RETURN(WRITE_LLS_INITr(unit, rval)); 8650 8651 /* Wait for LLS init done. */ 8652 if (SAL_BOOT_SIMULATION) { 8653 mmu_init_usec = 10000000; /* Simulation .. 10sec */ 8654 } else { 8655 mmu_init_usec = 50000; 8656 } 8657 soc_timeout_init(&to, mmu_init_usec, 0); 8658 8659 /* In sim, INIT_DONE will not be set. So manually setting it. */ 8660 if ((SAL_BOOT_BCMSIM || SAL_BOOT_PLISIM)) { 8661 SOC_IF_ERROR_RETURN(READ_LLS_INITr(unit, &rval)); 8662 soc_reg_field_set(unit, LLS_INITr, &rval, INIT_DONEf, 1); 8663 SOC_IF_ERROR_RETURN(WRITE_LLS_INITr(unit, rval)); 8664 } 8665 8666 do { 8667 SOC_IF_ERROR_RETURN(READ_LLS_INITr(unit, &rval)); 8668 if (soc_reg_field_get(unit, LLS_INITr, rval, INIT_DONEf)) { 8669 break; 8670 } 8671 if (soc_timeout_check(&to)) { 8672 LOG_WARN(BSL_LS_SOC_COMMON, (BSL_META_U(unit, "LLS INIT timeout\n"))); 8673 break; 8674 } 8675 } while (TRUE); 8676 8677 /* Enable all ports */ 8678 rval = 0xFFFFFFFF; 8679 soc_reg_field_set(unit, INPUT_PORT_RX_ENABLE_64r, &rval, 8680 INPUT_PORT_RX_ENABLEf, 0x3FFFFFFF); 8681 SOC_IF_ERROR_RETURN(WRITE_INPUT_PORT_RX_ENABLE_64r_REG32(unit, rval)); 8682 8683 SOC_IF_ERROR_RETURN(WRITE_THDIEMA_INPUT_PORT_RX_ENABLE_64r_REG32(unit, rval)); 8684 SOC_IF_ERROR_RETURN(WRITE_THDIEXT_INPUT_PORT_RX_ENABLE_64r_REG32(unit, rval)); 8685 SOC_IF_ERROR_RETURN(WRITE_THDIQEN_INPUT_PORT_RX_ENABLE_64r_REG32(unit, rval)); 8686 SOC_IF_ERROR_RETURN(WRITE_THDIRQE_INPUT_PORT_RX_ENABLE_64r_REG32(unit, rval)); 8687 8688 SOC_IF_ERROR_RETURN(WRITE_THDI_BYPASSr(unit, 0)); 8689 SOC_IF_ERROR_RETURN(WRITE_THDIQEN_THDI_BYPASSr(unit, 0)); 8690 SOC_IF_ERROR_RETURN(WRITE_THDIRQE_THDI_BYPASSr(unit, 0)); 8691 SOC_IF_ERROR_RETURN(WRITE_THDIEXT_THDI_BYPASSr(unit, 0)); 8692 SOC_IF_ERROR_RETURN(WRITE_THDIEMA_THDI_BYPASSr(unit, 0)); 8693 SOC_IF_ERROR_RETURN(WRITE_THDO_BYPASSr(unit, 0)); 8694 8695 ext_pbmp = soc_property_get_pbmp(unit, spn_PBMP_EXT_MEM, 0); 8696 SOC_PBMP_COUNT(ext_pbmp, ext_pbmp_count); 8697 if (soc_feature(unit, soc_feature_ddr3) && SOC_DDR3_NUM_MEMORIES(unit)) { 8698 /* Configure EMC */ 8699 SOC_IF_ERROR_RETURN(READ_EMC_CFGr(unit, &rval)); 8700 soc_reg_field_set(unit, EMC_CFGr, &rval, NUM_CISf, 8701 SOC_DDR3_NUM_MEMORIES(unit)); 8702 soc_reg_field_set(unit, EMC_CFGr, &rval, DRAM_SIZEf, 8703 SOC_DDR3_NUM_ROWS(unit) / 8192 - 1); 8704 SOC_IF_ERROR_RETURN(WRITE_EMC_CFGr(unit, rval)); 8705 8706 SOC_IF_ERROR_RETURN(READ_EMC_FREE_POOL_SIZESr(unit, &rval)); 8707 soc_reg_field_set(unit, EMC_FREE_POOL_SIZESr, &rval, WTFP_SIZEf, 0x200); 8708 soc_reg_field_set(unit, EMC_FREE_POOL_SIZESr, &rval, RSFP_SIZEf, 8709 (SOC_DDR3_NUM_MEMORIES(unit) == 1) ? 64 : 128); 8710 SOC_IF_ERROR_RETURN(WRITE_EMC_FREE_POOL_SIZESr(unit, rval)); 8711 8712 SOC_IF_ERROR_RETURN(READ_EMC_IRRB_THRESHOLDSr(unit, &rval)); 8713 soc_reg_field_set(unit, EMC_IRRB_THRESHOLDSr, &rval, ALL_Q_XOFF_THRESHOLDf, 0x10); 8714 soc_reg_field_set(unit, EMC_IRRB_THRESHOLDSr, &rval, ALL_UNDERRUN_Q_XOFF_THRESHOLDf, 0x28); 8715 soc_reg_field_set(unit, EMC_IRRB_THRESHOLDSr, &rval, ALL_UNDERRUN_Q_XON_THRESHOLDf, 0x18); 8716 soc_reg_field_set(unit, EMC_IRRB_THRESHOLDSr, &rval, ALL_Q_XON_THRESHOLDf, 8); 8717 SOC_IF_ERROR_RETURN(WRITE_EMC_IRRB_THRESHOLDSr(unit, rval)); 8718 } 8719 8720 rval = 0; 8721 SOC_IF_ERROR_RETURN(WRITE_DEQ_EFIFO_CFG_COMPLETEr(unit, rval)); 8722 8723 /* Setup TDM for MMU Arb & LLS */ 8724 SOC_IF_ERROR_RETURN(_soc_saber2_mmu_tdm_init(unit)); 8725 8726 /* Config DEQ_EFIFO_CFG and TOQ_PORT_BW_CTRL */ 8727 SOC_IF_ERROR_RETURN(_soc_saber2_mmu_port_init(unit)); 8728 if((soc_feature(unit, soc_feature_ddr3)) && 8729 (!(SAL_BOOT_BCMSIM || SAL_BOOT_PLISIM || SAL_BOOT_XGSSIM)) && 8730 SOC_DDR3_NUM_MEMORIES(unit)) { 8731 freq_loc = _soc_ddr_sb2_phy_freqtoloc(SOC_DDR3_CLOCK_MHZ(unit)); 8732 8733 if (freq_loc == SB2_FREQ_667) { 8734 wr_phase = 119; 8735 rd_phase = 122; 8736 } else if (freq_loc == SB2_FREQ_800) { 8737 wr_phase = 120; 8738 rd_phase = 124; 8739 } else { 8740 LOG_DEBUG(BSL_LS_SOC_MII, 8741 (BSL_META_U(unit, 8742 "_soc_ddr_sb2_phy_freqtoloc() " 8743 "returned invalid frequency"))); 8744 return SOC_E_INTERNAL; 8745 } 8746 8747 8748 for(i=0; i<16; i++) { 8749 SOC_IF_ERROR_RETURN(READ_TOQ_EXT_MEM_BW_MAP_TABLEr(unit, i, &rval)); 8750 soc_reg_field_set(unit, TOQ_EXT_MEM_BW_MAP_TABLEr, &rval, 8751 GBL_GUARENTEE_BW_LIMITf, 0x1C2); 8752 soc_reg_field_set(unit, TOQ_EXT_MEM_BW_MAP_TABLEr, &rval, 8753 WR_PHASEf, wr_phase); 8754 soc_reg_field_set(unit, TOQ_EXT_MEM_BW_MAP_TABLEr, &rval, 8755 RD_PHASEf, rd_phase); 8756 SOC_IF_ERROR_RETURN( 8757 WRITE_TOQ_EXT_MEM_BW_MAP_TABLEr(unit,i,rval)); 8758 } 8759 } 8760 8761 rval = 0; 8762 soc_reg_field_set(unit, TOQ_BW_LIMITING_MIDPKT_ENr, 8763 &rval, MIDPKT_SHAPE_ENf, 0x1FFFFFFE); 8764 SOC_IF_ERROR_RETURN(WRITE_TOQ_BW_LIMITING_MIDPKT_ENr(unit, rval)); 8765 8766 rval = 0; 8767 soc_reg_field_set(unit, DEQ_EFIFO_CFG_COMPLETEr, &rval, 8768 EGRESS_FIFO_CONFIGURATION_COMPLETEf, 1); 8769 SOC_IF_ERROR_RETURN(WRITE_DEQ_EFIFO_CFG_COMPLETEr(unit, rval)); 8770 8771 /* Enable LLS */ 8772 rval = 0; 8773 soc_reg_field_set(unit, LLS_CONFIG0r, &rval, DEQUEUE_ENABLEf, 1); 8774 soc_reg_field_set(unit, LLS_CONFIG0r, &rval, ENQUEUE_ENABLEf, 1); 8775 soc_reg_field_set(unit, LLS_CONFIG0r, &rval, FC_ENABLEf, 1); 8776 soc_reg_field_set(unit, LLS_CONFIG0r, &rval, MIN_ENABLEf, 1); 8777 soc_reg_field_set(unit, LLS_CONFIG0r, &rval, PORT_SCHEDULER_ENABLEf, 1); 8778 soc_reg_field_set(unit, LLS_CONFIG0r, &rval, SHAPER_ENABLEf, 1); 8779 if (SOC_REG_FIELD_VALID(unit, LLS_CONFIG0r, SPRI_VECT_MODE_ENABLEf)) { 8780 if (soc_feature(unit, soc_feature_vector_based_spri)) { 8781 soc_reg_field_set(unit, LLS_CONFIG0r, &rval, 8782 SPRI_VECT_MODE_ENABLEf, 1); 8783 } 8784 } 8785 SOC_IF_ERROR_RETURN(WRITE_LLS_CONFIG0r(unit, rval)); 8786 8787 /* Enable shaper background refresh */ 8788 rval = 0; 8789 soc_reg_field_set(unit, LLS_MAX_REFRESH_ENABLEr, &rval, L0_MAX_REFRESH_ENABLEf, 1); 8790 soc_reg_field_set(unit, LLS_MAX_REFRESH_ENABLEr, &rval, L1_MAX_REFRESH_ENABLEf, 1); 8791 soc_reg_field_set(unit, LLS_MAX_REFRESH_ENABLEr, &rval, L2_MAX_REFRESH_ENABLEf, 1); 8792 soc_reg_field_set(unit, LLS_MAX_REFRESH_ENABLEr, &rval, PORT_MAX_REFRESH_ENABLEf, 1); 8793 soc_reg_field_set(unit, LLS_MAX_REFRESH_ENABLEr, &rval, S0_MAX_REFRESH_ENABLEf, 1); 8794 soc_reg_field_set(unit, LLS_MAX_REFRESH_ENABLEr, &rval, S1_MAX_REFRESH_ENABLEf, 1); 8795 SOC_IF_ERROR_RETURN(WRITE_LLS_MAX_REFRESH_ENABLEr(unit, rval)); 8796 8797 rval = 0; 8798 soc_reg_field_set(unit, LLS_MIN_REFRESH_ENABLEr, &rval, L0_MIN_REFRESH_ENABLEf, 1); 8799 soc_reg_field_set(unit, LLS_MIN_REFRESH_ENABLEr, &rval, L1_MIN_REFRESH_ENABLEf, 1); 8800 soc_reg_field_set(unit, LLS_MIN_REFRESH_ENABLEr, &rval, L2_MIN_REFRESH_ENABLEf, 1); 8801 SOC_IF_ERROR_RETURN(WRITE_LLS_MIN_REFRESH_ENABLEr(unit, rval)); 8802 8803 /* RQE configuration */ 8804 rval = 0; 8805 soc_reg_field_set(unit, RQE_SCHEDULER_CONFIGr, &rval, 8806 L0_MCM_MODEf, 1); 8807 soc_reg_field_set(unit, RQE_SCHEDULER_CONFIGr, &rval, 8808 L0_CC_MODEf, 1); 8809 soc_reg_field_set(unit, RQE_SCHEDULER_CONFIGr, &rval, 8810 L0_UCM_MODEf, 1); 8811 soc_reg_field_set(unit, RQE_SCHEDULER_CONFIGr, &rval, 8812 L1_MODEf, 1); 8813 SOC_IF_ERROR_RETURN(WRITE_RQE_SCHEDULER_CONFIGr(unit, rval)); 8814 8815 rval = 0; 8816 soc_reg_field_set(unit, RQE_SCHEDULER_WEIGHT_L0_QUEUEr, &rval, 8817 WRR_WEIGHTf, 1); 8818 for(i=0; i<SOC_REG_NUMELS(unit, RQE_SCHEDULER_WEIGHT_L0_QUEUEr); i++) { 8819 SOC_IF_ERROR_RETURN(WRITE_RQE_SCHEDULER_WEIGHT_L0_QUEUEr(unit, i, 8820 rval)); 8821 } 8822 8823 rval = 0; 8824 soc_reg_field_set(unit, RQE_SCHEDULER_WEIGHT_L1_QUEUEr, &rval, 8825 WRR_WEIGHTf, 1); 8826 for(i=0; i<SOC_REG_NUMELS(unit, RQE_SCHEDULER_WEIGHT_L1_QUEUEr); i++) { 8827 SOC_IF_ERROR_RETURN(WRITE_RQE_SCHEDULER_WEIGHT_L1_QUEUEr(unit, i, 8828 rval)); 8829 } 8830 8831 if ((dev_id == BCM56268_DEVICE_ID) || (dev_id == BCM56263_DEVICE_ID)) { 8832 /* Refer the formula in the Reg file 8833 For Saber2 56268, frequency is 37MHZ 8834 Calculation is 8835 ((1024 +256)/2 * (0.027027)) + 1 = 18.29 8836 So we are programming 19 */ 8837 /* WRED Configuration */ 8838 SOC_IF_ERROR_RETURN(READ_WRED_MISCCONFIGr(unit, &rval)); 8839 soc_reg_field_set(unit, WRED_MISCCONFIGr, &rval, BASE_UPDATE_INTERVALf, 19); 8840 SOC_IF_ERROR_RETURN(WRITE_WRED_MISCCONFIGr(unit, rval)); 8841 8842 SOC_IF_ERROR_RETURN(READ_WRED_PARITY_ERROR_BITMAPr(unit, &rval)); 8843 soc_reg_field_set(unit, WRED_PARITY_ERROR_BITMAPr, &rval, UPDATE_INTRPT_STATUSf, 1); 8844 SOC_IF_ERROR_RETURN(WRITE_WRED_PARITY_ERROR_BITMAPr(unit, rval)); 8845 } else if ((dev_id == BCM56262_DEVICE_ID) || (dev_id == BCM56463_DEVICE_ID) 8846 || (dev_id == BCM56267_DEVICE_ID) || (dev_id== BCM56468_DEVICE_ID) 8847 || (dev_id == BCM56233_DEVICE_ID)) { 8848 /* Refer the formula in the Reg file 8849 For Saber2 56262, frequency is 75MHZ 8850 Calculation is 8851 ((1024 +256)/2 * (0.013)) + 1 = 9.32 8852 So we program value 10 */ 8853 /* WRED Configuration */ 8854 SOC_IF_ERROR_RETURN(READ_WRED_MISCCONFIGr(unit, &rval)); 8855 soc_reg_field_set(unit, WRED_MISCCONFIGr, &rval, BASE_UPDATE_INTERVALf, 10); 8856 SOC_IF_ERROR_RETURN(WRITE_WRED_MISCCONFIGr(unit, rval)); 8857 8858 SOC_IF_ERROR_RETURN(READ_WRED_PARITY_ERROR_BITMAPr(unit, &rval)); 8859 soc_reg_field_set(unit, WRED_PARITY_ERROR_BITMAPr, &rval, UPDATE_INTRPT_STATUSf, 1); 8860 SOC_IF_ERROR_RETURN(WRITE_WRED_PARITY_ERROR_BITMAPr(unit, rval)); 8861 } else { 8862 /* WRED Configuration */ 8863 SOC_IF_ERROR_RETURN(READ_WRED_MISCCONFIGr(unit, &rval)); 8864 soc_reg_field_set(unit, WRED_MISCCONFIGr, &rval, BASE_UPDATE_INTERVALf, 7); 8865 SOC_IF_ERROR_RETURN(WRITE_WRED_MISCCONFIGr(unit, rval)); 8866 } 8867 8868 SOC_IF_ERROR_RETURN(READ_WRED_PARITY_ERROR_MASKr(unit, &rval)); 8869 soc_reg_field_set(unit, WRED_PARITY_ERROR_MASKr, &rval, UPDATE_INTRPT_MASKf, 0); 8870 SOC_IF_ERROR_RETURN(WRITE_WRED_PARITY_ERROR_MASKr(unit, rval)); 8871 8872 SOC_IF_ERROR_RETURN(READ_MISCCONFIGr(unit, &rval)); 8873 soc_reg_field_set(unit, MISCCONFIGr, &rval, REFRESH_ENf, 1); 8874 SOC_IF_ERROR_RETURN(WRITE_MISCCONFIGr(unit, rval)); 8875 8876 /* 8877 * By default drop mask has been configured 0. It configures OP_DROP_MASK as 0 in 8878 * THDO_DROP_CTR_CONFIG thus enabling all THDO drop counters 8879 */ 8880 SOC_IF_ERROR_RETURN(soc_saber2_perq_flex_counters_init(unit,0)); 8881 8882 rval = 0xffffffff; /* PRIx_GRP = 0x7 */ 8883 8884 /* Configuring all profile 3 to use all the priority groups 0 to 7 */ 8885 8886 SOC_IF_ERROR_RETURN(WRITE_MMU_ENQ_PROFILE_3_PRI_GRP0r(unit, rval)); 8887 SOC_IF_ERROR_RETURN(WRITE_MMU_ENQ_PROFILE_3_PRI_GRP1r(unit, rval)); 8888 8889 SOC_IF_ERROR_RETURN(WRITE_PROFILE3_PRI_GRP0r(unit, rval)); 8890 SOC_IF_ERROR_RETURN(WRITE_PROFILE3_PRI_GRP1r(unit, rval)); 8891 8892 SOC_IF_ERROR_RETURN(WRITE_THDIEXT_PROFILE3_PRI_GRP0r(unit, rval)); 8893 SOC_IF_ERROR_RETURN(WRITE_THDIEXT_PROFILE3_PRI_GRP1r(unit, rval)); 8894 8895 SOC_IF_ERROR_RETURN(WRITE_THDIEMA_PROFILE3_PRI_GRP0r(unit, rval)); 8896 SOC_IF_ERROR_RETURN(WRITE_THDIEMA_PROFILE3_PRI_GRP1r(unit, rval)); 8897 8898 SOC_IF_ERROR_RETURN(WRITE_THDIRQE_PROFILE3_PRI_GRP0r(unit, rval)); 8899 SOC_IF_ERROR_RETURN(WRITE_THDIRQE_PROFILE3_PRI_GRP1r(unit, rval)); 8900 8901 SOC_IF_ERROR_RETURN(WRITE_THDIQEN_PROFILE3_PRI_GRP0r(unit, rval)); 8902 SOC_IF_ERROR_RETURN(WRITE_THDIQEN_PROFILE3_PRI_GRP1r(unit, rval)); 8903 8904 COMPILER_64_ZERO(rval1); 8905 8906 /* Setting profile ID=3 for all the ports which support 8 PG */ 8907 for (port = si->cmic_port + 1 ; port <= si->lb_port; port++) { 8908 /* 10-12, 14-16,18-20 ports have 1 PG */ 8909 if ((( port > 9) && (port < 13)) || 8910 (( port > 13) && (port < 17)) || 8911 (( port > 17) && (port < 21))) { 8912 continue; 8913 } 8914 soc_reg64_field32_set(unit, MMU_ENQ_IP_PRI_TO_PG_PROFILE_0r, 8915 &rval1 ,sb2_srcport_field_names[port], 3); 8916 } 8917 8918 WRITE_MMU_ENQ_IP_PRI_TO_PG_PROFILE_0r(unit, rval1); 8919 /* Using the same rval1 for setting the remaining registers */ 8920 WRITE_PORT_PROFILE_MAPr(unit, rval1); 8921 WRITE_THDIEXT_PORT_PROFILE_MAPr(unit, rval1); 8922 WRITE_THDIEMA_PORT_PROFILE_MAPr(unit, rval1); 8923 WRITE_THDIRQE_PORT_PROFILE_MAPr(unit, rval1); 8924 WRITE_THDIQEN_PORT_PROFILE_MAPr(unit, rval1); 8925 8926 rval = 0; 8927 SOC_IF_ERROR_RETURN(WRITE_BUFFER_CELL_LIMIT_SP_SHAREDr(unit,0)); 8928 SOC_IF_ERROR_RETURN(WRITE_THDIEXT_BUFFER_CELL_LIMIT_SP_SHAREDr(unit,0)); 8929 SOC_IF_ERROR_RETURN(WRITE_THDIEMA_BUFFER_CELL_LIMIT_SP_SHAREDr(unit,0)); 8930 SOC_IF_ERROR_RETURN(WRITE_THDIRQE_BUFFER_CELL_LIMIT_SP_SHAREDr(unit,0)); 8931 SOC_IF_ERROR_RETURN(WRITE_THDIQEN_BUFFER_CELL_LIMIT_SP_SHAREDr(unit,0)); 8932 8933 /* Input port per-device global headroom */ 8934 rval = 0; 8935 SOC_IF_ERROR_RETURN(READ_THDO_MISCCONFIGr(unit, &rval)); 8936 soc_reg_field_set(unit, THDO_MISCCONFIGr, &rval, STAT_CLEARf, 0); 8937 soc_reg_field_set(unit, THDO_MISCCONFIGr, &rval, PARITY_CHK_ENf, 1); 8938 soc_reg_field_set(unit, THDO_MISCCONFIGr, &rval, PARITY_GEN_ENf, 1); 8939 SOC_IF_ERROR_RETURN(WRITE_THDO_MISCCONFIGr(unit, rval)); 8940 8941 SOC_IF_ERROR_RETURN(READ_OP_THR_CONFIGr(unit, &rval)); 8942 soc_reg_field_set(unit, OP_THR_CONFIGr, &rval, EARLY_E2E_SELECTf, 0); 8943 SOC_IF_ERROR_RETURN(WRITE_OP_THR_CONFIGr(unit, rval)); 8944 8945 if (!SOC_WARM_BOOT(unit)) { 8946 SOC_IF_ERROR_RETURN(_soc_saber2_mmu_init_helper(unit, -1)); 8947 } 8948 8949 8950 /* Initialize MMU internal/external aging limit memory */ 8951 count = soc_mem_index_count(unit, MMU_AGING_LMT_INTm); 8952 sal_memset(&age_entry, 0, sizeof(mmu_aging_lmt_int_entry_t)); 8953 for (i=0; i < count; i++) { 8954 SOC_IF_ERROR_RETURN(WRITE_MMU_AGING_LMT_INTm(unit, 8955 MEM_BLOCK_ANY, i, &age_entry)); 8956 } 8957 8958 count = soc_mem_index_count(unit, MMU_AGING_LMT_EXTm); 8959 for (i=0; i < count; i++) { 8960 SOC_IF_ERROR_RETURN(WRITE_MMU_AGING_LMT_EXTm(unit, 8961 MEM_BLOCK_ANY, i, &age_entry)); 8962 } 8963 8964 SOC_IF_ERROR_RETURN(_soc_sb2_post_mmu_init(unit)); 8965 8966 /* RQE_QUEUE_PRI_x field is valid for all revisions of all SKUs of SB2 */ 8967 8968 if ((rev_id == BCM56260_A0_REV_ID) || (rev_id == BCM56260_B0_REV_ID)) { 8969 /* Allow the RQE to use all eight queues on B0 */ 8970 rval = 0; 8971 soc_reg_field_set(unit, MMU_ENQ_RQE_QUEUE_SELECT_0r, &rval, RQE_QUEUE_PRI_0f, 0); 8972 soc_reg_field_set(unit, MMU_ENQ_RQE_QUEUE_SELECT_0r, &rval, RQE_QUEUE_PRI_1f, 1); 8973 soc_reg_field_set(unit, MMU_ENQ_RQE_QUEUE_SELECT_0r, &rval, RQE_QUEUE_PRI_2f, 2); 8974 soc_reg_field_set(unit, MMU_ENQ_RQE_QUEUE_SELECT_0r, &rval, RQE_QUEUE_PRI_3f, 3); 8975 soc_reg_field_set(unit, MMU_ENQ_RQE_QUEUE_SELECT_0r, &rval, RQE_QUEUE_PRI_4f, 4); 8976 soc_reg_field_set(unit, MMU_ENQ_RQE_QUEUE_SELECT_0r, &rval, RQE_QUEUE_PRI_5f, 5); 8977 soc_reg_field_set(unit, MMU_ENQ_RQE_QUEUE_SELECT_0r, &rval, RQE_QUEUE_PRI_6f, 6); 8978 soc_reg_field_set(unit, MMU_ENQ_RQE_QUEUE_SELECT_0r, &rval, RQE_QUEUE_PRI_7f, 7); 8979 SOC_IF_ERROR_RETURN(WRITE_MMU_ENQ_RQE_QUEUE_SELECT_0r(unit, rval)); 8980 8981 8982 rval = 0; 8983 soc_reg_field_set(unit, MMU_ENQ_RQE_QUEUE_SELECT_1r, &rval, RQE_QUEUE_PRI_8f, 7); 8984 soc_reg_field_set(unit, MMU_ENQ_RQE_QUEUE_SELECT_1r, &rval, RQE_QUEUE_PRI_9f, 7); 8985 soc_reg_field_set(unit, MMU_ENQ_RQE_QUEUE_SELECT_1r, &rval, RQE_QUEUE_PRI_10f, 7); 8986 soc_reg_field_set(unit, MMU_ENQ_RQE_QUEUE_SELECT_1r, &rval, RQE_QUEUE_PRI_11f, 7); 8987 soc_reg_field_set(unit, MMU_ENQ_RQE_QUEUE_SELECT_1r, &rval, RQE_QUEUE_PRI_12f, 7); 8988 soc_reg_field_set(unit, MMU_ENQ_RQE_QUEUE_SELECT_1r, &rval, RQE_QUEUE_PRI_13f, 7); 8989 soc_reg_field_set(unit, MMU_ENQ_RQE_QUEUE_SELECT_1r, &rval, RQE_QUEUE_PRI_14f, 7); 8990 soc_reg_field_set(unit, MMU_ENQ_RQE_QUEUE_SELECT_1r, &rval, RQE_QUEUE_PRI_15f, 7); 8991 SOC_IF_ERROR_RETURN(WRITE_MMU_ENQ_RQE_QUEUE_SELECT_1r(unit, rval)); 8992 } 8993 8994 if (!SOC_WARM_BOOT(unit)) { 8995 SOC_IF_ERROR_RETURN(_soc_saber2_mmu_set_invalid_parent(unit)); 8996 } 8997 return SOC_E_NONE; 8998 } 8999 9000 STATIC int 9001 _soc_saber2_age_timer_get(int unit, int *age_seconds, int *enabled) 9002 { 9003 uint32 rval; 9004 9005 SOC_IF_ERROR_RETURN(READ_L2_AGE_TIMERr(unit, &rval)); 9006 *enabled = soc_reg_field_get(unit, L2_AGE_TIMERr, rval, AGE_ENAf); 9007 *age_seconds = soc_reg_field_get(unit, L2_AGE_TIMERr, rval, AGE_VALf); 9008 9009 return SOC_E_NONE; 9010 } 9011 9012 STATIC int 9013 _soc_saber2_age_timer_max_get(int unit, int *max_seconds) 9014 { 9015 *max_seconds = 9016 soc_reg_field_get(unit, L2_AGE_TIMERr, 0xffffffff, AGE_VALf); 9017 9018 return SOC_E_NONE; 9019 } 9020 9021 STATIC int 9022 _soc_saber2_age_timer_set(int unit, int age_seconds, int enable) 9023 { 9024 uint32 rval; 9025 9026 rval = 0; 9027 soc_reg_field_set(unit, L2_AGE_TIMERr, &rval, AGE_ENAf, enable); 9028 soc_reg_field_set(unit, L2_AGE_TIMERr, &rval, AGE_VALf, age_seconds); 9029 SOC_IF_ERROR_RETURN(WRITE_L2_AGE_TIMERr(unit, rval)); 9030 9031 return SOC_E_NONE; 9032 } 9033 9034 int sb2_linkphy_port[1][4] = { 9035 {1, 2, 3, 4} /* {T,R}XLP0 */ 9036 }; 9037 9038 int 9039 soc_sb2_linkphy_port_reg_blk_idx_get( 9040 int unit, int port, int blktype, int *block, int *index) 9041 { 9042 int i,j; 9043 int blk = -1; 9044 int idx = -1; 9045 9046 for (i=0; i<1; i++) { 9047 for(j=0; j<4; j++) { 9048 if(port == sb2_linkphy_port[i][j]) { 9049 blk = i; 9050 idx = j; 9051 break; 9052 } 9053 } 9054 } 9055 9056 if (blktype == SOC_BLK_TXLP) { 9057 if (blk == 0) { 9058 blk = TXLP0_BLOCK(unit); 9059 } 9060 } else if (blktype == SOC_BLK_RXLP) { 9061 if (blk == 0) { 9062 blk = RXLP0_BLOCK(unit); 9063 } 9064 } else { 9065 return SOC_E_PARAM; 9066 } 9067 9068 if (block != NULL) { 9069 *block = blk; 9070 } 9071 if (index != NULL) { 9072 *index = idx; 9073 } 9074 if ((blk == -1) || (idx == -1)) { 9075 return SOC_E_NOT_FOUND; 9076 } 9077 return SOC_E_NONE; 9078 } 9079 9080 int 9081 soc_sb2_linkphy_port_blk_idx_get( 9082 int unit, int port, int *block, int *index) 9083 { 9084 int i,j; 9085 int blk = -1; 9086 int idx = -1; 9087 9088 for (i=0; i<1; i++) { 9089 for(j=0; j<4; j++) { 9090 if(port == sb2_linkphy_port[i][j]) { 9091 blk = i; 9092 idx = j; 9093 break; 9094 } 9095 } 9096 } 9097 9098 if (block != NULL) { 9099 *block = blk; 9100 } 9101 if (index != NULL) { 9102 *index = idx; 9103 } 9104 if ((blk == -1) || (idx == -1)) { 9105 return SOC_E_NOT_FOUND; 9106 } 9107 return SOC_E_NONE; 9108 } 9109 9110 int soc_sb2_linkphy_get_portid(int unit, int block, int index) { 9111 if (index > 3) { 9112 return -1; 9113 } 9114 if ((block == TXLP0_BLOCK(unit)) || (block == RXLP0_BLOCK(unit))) { 9115 return sb2_linkphy_port[0][index]; 9116 } 9117 return -1; 9118 } 9119 9120 int sb2_iecell_port[1][4] = { 9121 {25, 26, 27, 28} /* IECELL0 */ 9122 }; 9123 9124 int 9125 soc_sb2_iecell_port_reg_blk_idx_get( 9126 int unit, int port, int blktype, int *block, int *index) 9127 { 9128 int i,j; 9129 int blk = -1; 9130 int idx = -1; 9131 9132 for (i=0; i<1; i++) { 9133 for(j=0; j<4; j++) { 9134 if(port == sb2_iecell_port[i][j]) { 9135 blk = i; 9136 idx = j; 9137 break; 9138 } 9139 } 9140 } 9141 9142 if (blktype == SOC_BLK_IECELL) { 9143 if (blk == 0) { 9144 blk = IECELL0_BLOCK(unit); 9145 } 9146 } else { 9147 return SOC_E_PARAM; 9148 } 9149 9150 if (block != NULL) { 9151 *block = blk; 9152 } 9153 if (index != NULL) { 9154 *index = idx; 9155 } 9156 if ((blk == -1) || (idx == -1)) { 9157 return SOC_E_NOT_FOUND; 9158 } 9159 return SOC_E_NONE; 9160 } 9161 9162 int 9163 soc_sb2_iecell_port_blk_idx_get( 9164 int unit, int port, int *block, int *index) 9165 { 9166 int i,j; 9167 int blk = -1; 9168 int idx = -1; 9169 9170 for (i=0; i<1; i++) { 9171 for(j=0; j<4; j++) { 9172 if(port == sb2_iecell_port[i][j]) { 9173 blk = i; 9174 idx = j; 9175 break; 9176 } 9177 } 9178 } 9179 9180 if (block != NULL) { 9181 *block = blk; 9182 } 9183 if (index != NULL) { 9184 *index = idx; 9185 } 9186 if ((blk == -1) || (idx == -1)) { 9187 return SOC_E_NOT_FOUND; 9188 } 9189 return SOC_E_NONE; 9190 } 9191 9192 int soc_sb2_iecell_get_portid(int unit, int block, int index) { 9193 if (index > 3) { 9194 return -1; 9195 } 9196 if (block == IECELL0_BLOCK(unit)) { 9197 return sb2_iecell_port[0][index]; 9198 } 9199 return -1; 9200 } 9201 int 9202 soc_saber2_port_is_unused(int unit, int port_no) 9203 { 9204 soc_port_details_t *port_details, *port_save; 9205 int count = 0, port; 9206 9207 9208 port_details = sal_alloc( 9209 sizeof(soc_port_details_t) * (SB2_MAX_PHYSICAL_PORTS+1), 9210 "sb2_block_ports_t"); 9211 9212 if (port_details == NULL) { 9213 LOG_ERROR(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 9214 "INTERNAL: Memory allocation failed for port_details\n"))); 9215 return 0; 9216 } 9217 9218 sal_memcpy(port_details, 9219 sb2_port_details[_sb2_config_id[unit]], 9220 sizeof(soc_port_details_t) * (SB2_MAX_PHYSICAL_PORTS+1)); 9221 port_save = port_details; 9222 while (count < SB2_MAX_PHYSICAL_PORTS) { 9223 if ((port_details->port_type == 0) && 9224 (port_details->port_speed == 0)) { 9225 for (port = port_details->start_port_no; 9226 port <= port_details->end_port_no; 9227 port++) { 9228 if (port == 0) { 9229 continue; 9230 } 9231 if (port == port_no) { 9232 sal_free(port_save); 9233 return 1; 9234 } 9235 } 9236 } 9237 count++; 9238 port_details++; 9239 } 9240 sal_free(port_save); 9241 return 0; 9242 } 9243 /* 9244 * cpu port (mmu port 0): 48 queues (0-47) 9245 * loopback port (48-71) 9246 * hg ports : 24 queues 9247 * other ports : 8 queues 9248 */ 9249 9250 int 9251 soc_saber2_num_cosq_init(int unit) 9252 { 9253 soc_info_t *si; 9254 int port, prev_port; 9255 int numq = 0, i; 9256 int pp_port_cos; 9257 int start_pp_port, end_pp_port; 9258 int packing_mode; 9259 int num_uc_cosq = 0; 9260 9261 si = &SOC_INFO(unit); 9262 packing_mode = soc_property_get(unit, spn_MMU_MULTI_PACKETS_PER_CELL, 0); 9263 9264 /* For CPU port it is hardcoded to zero as base queue */ 9265 si->port_cosq_base[si->cmic_port] = 0; 9266 si->port_uc_cosq_base[si->cmic_port] = 0; 9267 si->port_num_uc_cosq[si->cmic_port] = NUM_CPU_COSQ(unit); 9268 si->port_num_ext_cosq[si->cmic_port] = 0; 9269 9270 /* For Loopback port it is hardcoded as 48 as a base queue*/ 9271 si->port_cosq_base[si->lb_port] = 48; 9272 si->port_uc_cosq_base[si->lb_port] = 48; 9273 si->port_num_uc_cosq[si->lb_port] = 24; 9274 9275 /* first front panel port needs to start with 72 */ 9276 prev_port = si->cmic_port; 9277 numq = 72; 9278 for (port = si->cmic_port + 1 ; port < si->lb_port; port++) { 9279 if (soc_saber2_port_is_unused(unit, port)) { 9280 continue; 9281 } 9282 si->port_num_ext_cosq[port] = 0; 9283 si->port_num_cosq[port] = 0; 9284 9285 /* For all GE/, XE, HG Ports */ 9286 si->port_uc_cosq_base[port] = si->port_uc_cosq_base[prev_port] + 9287 numq; 9288 si->port_cosq_base[port] = si->port_uc_cosq_base[port]; 9289 9290 prev_port = port; 9291 if (IS_HG_PORT(unit, port)) { 9292 si->port_num_uc_cosq[port] = 24; 9293 } else { 9294 num_uc_cosq = soc_property_port_get(unit, port, 9295 spn_LLS_NUM_L2UC, 8); /* DEFAULT_NUM_PHYSICAL_QUEUES */ 9296 if (num_uc_cosq < 8) { 9297 num_uc_cosq = 8; 9298 } 9299 si->port_num_uc_cosq[port] = num_uc_cosq; 9300 } 9301 numq = si->port_num_uc_cosq[port]; 9302 9303 /* In Packing mode we have seperate queues for multicast and unicast 9304 So using first half of the table for unicats and second half for multicast*/ 9305 if (packing_mode) { 9306 if (!IS_CPU_PORT(unit, port)) { 9307 si->port_cosq_base[port] += 512; 9308 } 9309 si->port_num_cosq[port] = si->port_num_uc_cosq[port]; 9310 } 9311 9312 /* This need to be validated when testing COE ports */ 9313 pp_port_cos = soc_property_port_get(unit, port, 9314 spn_NUM_SUBPORT_COS, 4); 9315 if (si->port_num_subport[port] > 0) { 9316 start_pp_port = si->port_subport_base[port]; 9317 end_pp_port = si->port_subport_base[port] + 9318 si->port_num_subport[port]; 9319 for (i = start_pp_port; i < end_pp_port; i++) { 9320 si->port_uc_cosq_base[i] = si->port_uc_cosq_base[port] + numq; 9321 si->port_cosq_base[i] = si->port_uc_cosq_base[i]; 9322 si->port_num_uc_cosq[i] = pp_port_cos; 9323 numq += pp_port_cos; 9324 if (packing_mode) { 9325 si->port_cosq_base[i] += 512; 9326 if (si->port_cosq_base[i] >= 1024) { 9327 LOG_ERROR(BSL_LS_BCM_COSQ, 9328 (BSL_META_U(unit, 9329 "Packing and subport configuration together causing " 9330 "total queue allocation more than 1024.\n"))); 9331 return SOC_E_CONFIG; 9332 } 9333 si->port_num_cosq[i] = si->port_num_uc_cosq[i]; 9334 } 9335 } 9336 } 9337 9338 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 9339 "\nport num %d cosq_base %d num_cosq %d"), 9340 port, si->port_cosq_base[port], si->port_num_uc_cosq[port])); 9341 } 9342 9343 return SOC_E_NONE; 9344 } 9345 9346 /* soc_sb2_mem_config: 9347 * Over-ride the default table sizes (from regsfile) for any SKUs here 9348 */ 9349 int 9350 soc_sb2_mem_config(int unit, int dev_id) 9351 { 9352 int rv = SOC_E_NONE; 9353 int num_ipv6_128b_entries = 0; 9354 int config_v6_entries = 0; 9355 int defip_config = 0; 9356 soc_persist_t *sop = SOC_PERSIST(unit); 9357 9358 /* L3_DEFIP sizing */ 9359 9360 switch (dev_id) { 9361 case BCM56268_DEVICE_ID: 9362 case BCM56260_DEVICE_ID: 9363 case BCM56262_DEVICE_ID: 9364 case BCM56263_DEVICE_ID: 9365 case BCM56265_DEVICE_ID: 9366 case BCM56267_DEVICE_ID: 9367 case BCM56233_DEVICE_ID: 9368 SOC_CONTROL(unit)->l3_defip_max_tcams = _SOC_SB2_DEFIP_MAX_TCAMS; 9369 break; 9370 default: 9371 SOC_CONTROL(unit)->l3_defip_max_tcams = _SOC_SB2PLUS_DEFIP_MAX_TCAMS; 9372 break; 9373 9374 } 9375 SOC_CONTROL(unit)->l3_defip_tcam_size = _SOC_SB2_DEFIP_TCAM_DEPTH; 9376 if (soc_property_get(unit, "l3_defip_sizing", TRUE)) { 9377 defip_config = soc_property_get(unit, spn_IPV6_LPM_128B_ENABLE, 1); 9378 9379 if(dev_id == BCM56233_DEVICE_ID) { 9380 num_ipv6_128b_entries = 9381 soc_property_get(unit, spn_NUM_IPV6_LPM_128B_ENTRIES, 9382 (defip_config ? 512 : 0)); 9383 } else { 9384 num_ipv6_128b_entries = 9385 soc_property_get(unit, spn_NUM_IPV6_LPM_128B_ENTRIES, 9386 (defip_config ? 1024 : 0)); 9387 } 9388 9389 config_v6_entries = num_ipv6_128b_entries; 9390 9391 if (soc_feature(unit, soc_feature_l3_lpm_scaling_enable)) { 9392 9393 num_ipv6_128b_entries = 0; 9394 if (!soc_feature(unit, soc_feature_l3_lpm_128b_entries_reserved)) { 9395 config_v6_entries = SOC_CONTROL(unit)->l3_defip_tcam_size * 9396 ((config_v6_entries / 9397 SOC_CONTROL(unit)->l3_defip_tcam_size) + 9398 ((config_v6_entries % 9399 SOC_CONTROL(unit)->l3_defip_tcam_size) ? 1 : 0)); 9400 } 9401 } 9402 9403 sop->memState[L3_DEFIP_PAIR_128m].index_max = 9404 num_ipv6_128b_entries - 1; 9405 sop->memState[L3_DEFIP_PAIR_128_ONLYm].index_max = 9406 num_ipv6_128b_entries - 1; 9407 sop->memState[L3_DEFIP_PAIR_128_DATA_ONLYm].index_max = 9408 num_ipv6_128b_entries - 1; 9409 sop->memState[L3_DEFIP_PAIR_128_HIT_ONLYm].index_max = 9410 num_ipv6_128b_entries - 1; 9411 sop->memState[L3_DEFIPm].index_max = 9412 (SOC_CONTROL(unit)->l3_defip_max_tcams * 9413 SOC_CONTROL(unit)->l3_defip_tcam_size) - 9414 (num_ipv6_128b_entries * 2) - 1; 9415 sop->memState[L3_DEFIP_ONLYm].index_max = 9416 sop->memState[L3_DEFIPm].index_max; 9417 sop->memState[L3_DEFIP_DATA_ONLYm].index_max = 9418 sop->memState[L3_DEFIPm].index_max; 9419 sop->memState[L3_DEFIP_HIT_ONLYm].index_max = 9420 sop->memState[L3_DEFIPm].index_max; 9421 SOC_CONTROL(unit)->l3_defip_index_remap = num_ipv6_128b_entries; 9422 soc_l3_defip_indexes_init(unit, config_v6_entries); 9423 } 9424 9425 if (!(SAL_BOOT_BCMSIM || SAL_BOOT_PLISIM)) { 9426 switch (dev_id) { 9427 case BCM56260_DEVICE_ID: 9428 case BCM56261_DEVICE_ID: 9429 case BCM56262_DEVICE_ID: 9430 case BCM56263_DEVICE_ID: 9431 case BCM56265_DEVICE_ID: 9432 case BCM56266_DEVICE_ID: 9433 case BCM56267_DEVICE_ID: 9434 case BCM56268_DEVICE_ID: 9435 case BCM56233_DEVICE_ID: 9436 sop->memState[VLAN_MACm].index_max = 4095; 9437 sop->memState[VLAN_XLATEm].index_max = 4095; 9438 /* OAM tables scaled down for SB2 */ 9439 sop->memState[LMEPm].index_max = 511; 9440 sop->memState[LMEP_1m].index_max = 511; 9441 sop->memState[RMEPm].index_max = 2047; 9442 sop->memState[MA_INDEXm].index_max = 1535; 9443 sop->memState[EGR_MA_INDEXm].index_max = 1535; 9444 sop->memState[MA_STATEm].index_max = 511; 9445 sop->memState[MAID_REDUCTIONm].index_max = 511; 9446 sop->memState[ING_OAM_LM_COUNTERS_0m].index_max = 1023; 9447 sop->memState[EGR_OAM_LM_COUNTERS_0m].index_max = 1023; 9448 sop->memState[ING_OAM_LM_COUNTERS_1m].index_max = 511; 9449 sop->memState[EGR_OAM_LM_COUNTERS_1m].index_max = 511; 9450 sop->memState[ING_OAM_LM_COUNTERS_2m].index_max = 511; 9451 sop->memState[EGR_OAM_LM_COUNTERS_2m].index_max = 511; 9452 9453 9454 sop->memState[L3_ENTRY_ONLYm].index_max = 4095; 9455 sop->memState[L3_ENTRY_HIT_ONLYm].index_max = 255; 9456 sop->memState[L3_ENTRY_IPV4_UNICASTm].index_max = 4095; 9457 sop->memState[L3_ENTRY_IPV4_MULTICASTm].index_max = 2047; 9458 sop->memState[L3_ENTRY_IPV6_UNICASTm].index_max = 2047; 9459 sop->memState[L3_ENTRY_IPV6_MULTICASTm].index_max = 1023; 9460 if (dev_id == BCM56233_DEVICE_ID) { 9461 /* L2 MAC Address : 16K */ 9462 sop->memState[L2Xm].index_max = 16383; 9463 sop->memState[L2_ENTRY_ONLYm].index_max = 16383; 9464 sop->memState[L2_HITDA_ONLYm].index_max = 2047; 9465 sop->memState[L2_HITSA_ONLYm].index_max = 2047; 9466 9467 /* MPLS Labels : 2K */ 9468 sop->memState[MPLS_ENTRYm].index_max = 2047; 9469 9470 sop->memState[FP_TCAMm].index_max = 2047; 9471 sop->memState[FP_GLOBAL_MASK_TCAMm].index_max = 2047; 9472 sop->memState[FP_COUNTER_TABLEm].index_max = 2047; 9473 sop->memState[FP_METER_TABLEm].index_max = 2047; 9474 sop->memState[FP_POLICY_TABLEm].index_max = 2047; 9475 sop->memState[ING_QUEUE_MAPm].index_max = 511; 9476 sop->memState[LLS_L0_PARENTm].index_max = 63; 9477 sop->memState[LLS_L0_CONFIGm].index_max = 63; 9478 sop->memState[LLS_L0_MIN_CONFIG_Cm].index_max = 63; 9479 sop->memState[LLS_L0_SHAPER_CONFIG_Cm].index_max = 63; 9480 sop->memState[LLS_L1_PARENTm].index_max = 127; 9481 sop->memState[LLS_L1_CONFIGm].index_max = 127; 9482 sop->memState[LLS_L1_SHAPER_CONFIG_Cm].index_max = 127; 9483 sop->memState[LLS_L2_PARENTm].index_max = 511; 9484 sop->memState[LLS_L2_SHAPER_CONFIG_Cm].index_max = 127; 9485 } 9486 9487 sop->memState[SOURCE_VPm].index_max = 4095; 9488 sop->memState[EGR_DVP_ATTRIBUTEm].index_max = 4095; 9489 sop->memState[ING_DVP_TABLEm].index_max = 4095; 9490 9491 9492 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_0m].index_max = 1023; 9493 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_1m].index_max = 1023; 9494 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_2m].index_max = 1023; 9495 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_3m].index_max = 1023; 9496 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_4m].index_max = 1023; 9497 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_5m].index_max = 1023; 9498 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_6m].index_max = 1023; 9499 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_7m].index_max = 1023; 9500 sop->memState[EGR_FLEX_CTR_COUNTER_TABLE_0m].index_max = 511; 9501 sop->memState[EGR_FLEX_CTR_COUNTER_TABLE_1m].index_max = 511; 9502 sop->memState[EGR_FLEX_CTR_COUNTER_TABLE_2m].index_max = 511; 9503 sop->memState[EGR_FLEX_CTR_COUNTER_TABLE_3m].index_max = 511; 9504 sop->memState[EGR_FLEX_CTR_COUNTER_TABLE_4m].index_max = 511; 9505 sop->memState[EGR_FLEX_CTR_COUNTER_TABLE_5m].index_max = 511; 9506 sop->memState[EGR_FLEX_CTR_COUNTER_TABLE_6m].index_max = 511; 9507 sop->memState[EGR_FLEX_CTR_COUNTER_TABLE_7m].index_max = 511; 9508 9509 9510 sop->memState[VLAN_OR_VFI_MAC_COUNTm].index_max = 5119; 9511 sop->memState[VLAN_OR_VFI_MAC_LIMITm].index_max = 5119; 9512 sop->memState[VFIm].index_max = 1023; 9513 sop->memState[VFI_1m].index_max = 1023; 9514 sop->memState[L2MCm].index_max = 2047; 9515 9516 9517 if (dev_id == BCM56233_DEVICE_ID) { 9518 /* IPMc Groups : 256 */ 9519 sop->memState[EGR_IPMCm].index_max = 255; 9520 sop->memState[L3_IPMCm].index_max = 255; 9521 sop->memState[L3_IPMC_1m].index_max = 255; 9522 sop->memState[L3_IPMC_REMAPm].index_max = 255; 9523 sop->memState[MMU_IPMC_GROUP_TBL0m].index_max = 255; 9524 sop->memState[MMU_IPMC_GROUP_TBL1m].index_max = 255; 9525 sop->memState[MMU_IPMC_GROUP_TBL2m].index_max = 255; 9526 sop->memState[MMU_IPMC_GROUP_TBL3m].index_max = 255; 9527 sop->memState[MMU_IPMC_GROUP_TBLm].index_max = 255; 9528 } else { 9529 sop->memState[L3_IPMCm].index_max = 2047; 9530 sop->memState[L3_IPMC_1m].index_max = 2047; 9531 sop->memState[L3_IPMC_REMAPm].index_max = 2047; 9532 sop->memState[MMU_IPMC_GROUP_TBLm].index_max = 2047; 9533 } 9534 sop->memState[MMU_REPL_HEAD_TBLm].index_max = 16383; 9535 sop->memState[MMU_REPL_LIST_TBLm].index_max = 4095; 9536 if (dev_id == BCM56233_DEVICE_ID) { 9537 sop->memState[MMU_REPL_GRP_TBL0m].index_max = 256; 9538 sop->memState[MMU_REPL_GRP_TBL1m].index_max = 256; 9539 } else { 9540 sop->memState[MMU_REPL_GRP_TBL0m].index_max = 2047; 9541 sop->memState[MMU_REPL_GRP_TBL1m].index_max = 2047; 9542 } 9543 sop->memState[MMU_EXT_MC_GROUP_MAPm].index_max = 2047; 9544 sop->memState[MMU_EXT_MC_QUEUE_LIST0m].index_max = 4095; 9545 sop->memState[MMU_EXT_MC_QUEUE_LIST4m].index_max = 4095; 9546 9547 sop->memState[L3_ECMP_COUNTm].index_max = 127; 9548 sop->memState[INITIAL_L3_ECMP_GROUPm].index_max = 127; 9549 sop->memState[INITIAL_L3_ECMPm].index_max = 255; 9550 sop->memState[L3_ECMPm].index_max = 255; 9551 9552 /* L3 Next Hop : 4K */ 9553 sop->memState[EGR_L3_NEXT_HOPm].index_max = 4095; 9554 sop->memState[ING_L3_NEXT_HOPm].index_max = 4095; 9555 sop->memState[INITIAL_ING_L3_NEXT_HOPm].index_max = 4095; 9556 sop->memState[INITIAL_PROT_NHI_TABLEm].index_max = 4095; 9557 9558 break; 9559 } 9560 } 9561 return rv; 9562 } 9563 9564 int 9565 _soc_saber2_tsce_firmware_set(int unit, int port, uint8 *array, int datalen) 9566 { 9567 return soc_warpcore_firmware_set(unit, port, array, datalen, 0, 9568 XLPORT_WC_UCMEM_DATAm, 9569 XLPORT_WC_UCMEM_CTRLr); 9570 } 9571 9572 STATIC int 9573 _soc_saber2_mdio_addr_to_port(int unit, uint32 phy_addr) 9574 { 9575 #if 0 9576 if (PHY_ID_BUS_NUM(phy_addr) == 1) { 9577 return phy_addr & 0x1f; 9578 } else { 9579 return SOC_E_PARAM; 9580 } 9581 #else 9582 if(SOC_IS_METROLITE(unit)) 9583 return (phy_addr & 0x1f) + 4; 9584 else 9585 return (phy_addr & 0x1f) + 24; 9586 9587 #endif 9588 } 9589 9590 int 9591 _soc_saber2_sbus_tsc_block(int unit, 9592 int phy_port, soc_mem_t wc_ucmem_data, int *block) 9593 { 9594 int i,port_num_blktype = 0, tmp_blk=0; 9595 9596 *block= -1; 9597 port_num_blktype = SOC_DRIVER(unit)->port_num_blktype; 9598 for (i = 0; i < port_num_blktype; i++){ 9599 tmp_blk = SOC_PORT_IDX_BLOCK(unit, phy_port, i); 9600 if (SOC_MEM_BLOCK_VALID(unit, wc_ucmem_data, tmp_blk)) { 9601 *block = tmp_blk; 9602 break; 9603 } 9604 } 9605 9606 if (*block == -1){ 9607 LOG_WARN(BSL_LS_SOC_COMMON, 9608 (BSL_META_U(unit, 9609 "_soc_saber2_sbus_tsc_block(u=%d,pp=%d,mem=%d, blk=%d): " 9610 "no valid block for TSC SBUS interface!\n"), 9611 unit, phy_port, wc_ucmem_data, *block)); 9612 return SOC_E_INTERNAL; 9613 } 9614 9615 return SOC_E_NONE; 9616 } 9617 /* PHY_REG address decode : 9618 * - TSC_ADDR[31:0]={DEVICE(ADVAD)[31:27],??[26:24],TSC_ID(PHYAD)[23:19], 9619 * PORT_MODE(LANE)[18:16], IEEE_BIT[15], BLOCK[14:4], REG[3:0]} 9620 * - QSGMII_ADDR[31:0]={DEVICE(ADVAD)[31:27], LANE[26:16], REG_HI[15], 9621 * BLOCK[14:4], REG_LO[3:0]}} 9622 */ 9623 9624 #define PHY_REG_ADDR_DEVAD(_phy_reg) (((_phy_reg) >> 27) & 0x1f) 9625 #define TSC_REG_ADDR_TSCID(_phy_reg) (((_phy_reg) >> 19) & 0x1f) 9626 #define TSC_REG_ADDR_PORTMODE(_phy_reg) (((_phy_reg) >> 16) & 0x7) 9627 #define QSGMII_REG_ADDR_LANE(_phy_reg) (((_phy_reg) >> 16) & 0x7ff) 9628 #define PHY_REG_ADDR_BLOCK(_phy_reg) (((_phy_reg) >> 4) & 0xfff) 9629 #define TSC_REG_ADDR_REG(_phy_reg) ((_phy_reg) & 0xf) 9630 #define QSGMII_REG_ADDR_REG(_phy_reg) ((((_phy_reg) & 0x8000) >> 11) | \ 9631 ((_phy_reg) & 0xf)) 9632 9633 #define IS_QSGMII_REGISTER(_phy_reg) (((_phy_reg) & 0xf800f000) == 0x8000) 9634 #define TSC_REG_ADDR_TSCID_SET(_phy_reg, _phyad) \ 9635 ((_phy_reg) |= ((_phyad) & 0x1f) << 19) 9636 #define QSGMII_REG_ADDR_LANE_SET(_phy_reg_new, _phy_reg) \ 9637 ((_phy_reg_new) |= ((_phy_reg) & 0x7ff0000)) 9638 #define SABER2_PORT_IS_QSGMII(_unit, _port) \ 9639 (IS_GE_PORT((_unit), (_port)) && !IS_XL_PORT((_unit), (_port))) 9640 9641 9642 /* to check if this PHY register access sbus MDIO request is for 9643 * QSGMII register. 9644 */ 9645 STATIC int 9646 _soc_saber2_qsgmii_reg_access_check(int unit, 9647 uint32 port, uint32 phyreg, int *to_qsgmii) 9648 { 9649 *to_qsgmii = 0; 9650 if (PHY_REG_ADDR_DEVAD(phyreg) == 0){ /* DEVAD==0 for PCS */ 9651 if (IS_QSGMII_REGISTER(phyreg)) { 9652 *to_qsgmii = 1; 9653 } else if ((QSGMII_REG_ADDR_REG(phyreg) < 0x10) && 9654 SABER2_PORT_IS_QSGMII(unit, port)) { 9655 /* means QSGMII port on accessing IEEE registers */ 9656 *to_qsgmii = 1; 9657 } 9658 } 9659 9660 return SOC_E_NONE; 9661 } 9662 STATIC int 9663 _soc_saber2_indacc_read(int unit, uint32 phy_addr, 9664 uint32 phy_reg, uint32 *phy_data) 9665 { 9666 uint32 ctlsts; 9667 int ts; 9668 uint32 reg_addr = 0; 9669 9670 LOG_DEBUG(BSL_LS_SOC_MII, 9671 (BSL_META_U(unit, 9672 "_soc_saber2_indacc_read" 9673 "(%d,0x%x,0x%08x,*phy_data)..\n"), 9674 unit, phy_addr, phy_reg)); 9675 9676 SOC_IF_ERROR_RETURN( 9677 _soc_saber2_indacc_addr(phy_reg, &ts)); 9678 9679 ctlsts = 0; 9680 soc_reg_field_set(unit, CHIP_INDACC_CTLSTSr, &ctlsts, TARGET_SELECTf, ts); 9681 soc_reg_field_set(unit, CHIP_INDACC_CTLSTSr, &ctlsts, RD_REQf, 1); 9682 9683 /* assigning the reg_addr in Clause22 format */ 9684 reg_addr = phy_reg & 0x1f; 9685 soc_reg_field_set(unit, CHIP_INDACC_CTLSTSr, &ctlsts, ADDRESSf, reg_addr); 9686 9687 LOG_DEBUG(BSL_LS_SOC_MII, 9688 (BSL_META_U(unit, 9689 "_soc_saber2_indacc_read:" 9690 "INDACC_CTLSTSr=0x%08x\n"), ctlsts)); 9691 SOC_IF_ERROR_RETURN( 9692 WRITE_CHIP_INDACC_CTLSTSr(unit, REG_PORT_ANY, ctlsts)); 9693 9694 SOC_IF_ERROR_RETURN( 9695 _soc_saber2_indacc_wait(unit, RD_RDYf)); 9696 9697 SOC_IF_ERROR_RETURN( 9698 READ_CHIP_INDACC_RDATAr(unit, REG_PORT_ANY, phy_data)); 9699 9700 SOC_IF_ERROR_RETURN( 9701 WRITE_CHIP_INDACC_CTLSTSr(unit, REG_PORT_ANY, 0)); 9702 9703 return SOC_E_NONE; 9704 } 9705 9706 9707 STATIC int 9708 _soc_saber2_indacc_wait(int unit, soc_field_t fwait) 9709 { 9710 uint32 ctlsts; 9711 int poll = 1000; 9712 9713 do { 9714 SOC_IF_ERROR_RETURN( 9715 READ_CHIP_INDACC_CTLSTSr(unit, REG_PORT_ANY, &ctlsts)); 9716 if (soc_reg_field_get(unit, CHIP_INDACC_CTLSTSr, ctlsts, fwait)) { 9717 break; 9718 } 9719 } while (--poll > 0); 9720 9721 if (poll <= 0) { 9722 return SOC_E_TIMEOUT; 9723 } 9724 return SOC_E_NONE; 9725 } 9726 9727 STATIC int 9728 _soc_saber2_indacc_addr(uint32 phy_reg, int *target_select) 9729 { 9730 if (QSGMII_REG_ADDR_LANE(phy_reg) <= 15) { 9731 *target_select = (QSGMII_REG_ADDR_LANE(phy_reg) < 8) ? 0 : 1; 9732 return SOC_E_NONE; 9733 } 9734 9735 return SOC_E_INTERNAL; 9736 } 9737 9738 STATIC int 9739 _soc_saber2_indacc_write(int unit, uint32 phy_addr, 9740 uint32 phy_reg, uint32 phy_data) 9741 { 9742 uint32 ctlsts; 9743 int ts; 9744 uint32 reg_addr = 0; 9745 9746 LOG_DEBUG(BSL_LS_SOC_MII, 9747 (BSL_META_U(unit, 9748 "_soc_saber2_indacc_write" 9749 "(%d,0x%x,0x%08x,0x%04x)..\n"), 9750 unit, phy_addr, phy_reg, phy_data)); 9751 SOC_IF_ERROR_RETURN( 9752 WRITE_CHIP_INDACC_WDATAr(unit, REG_PORT_ANY, phy_data)); 9753 9754 SOC_IF_ERROR_RETURN( 9755 _soc_saber2_indacc_addr(phy_reg, &ts)); 9756 9757 ctlsts = 0; 9758 soc_reg_field_set(unit, CHIP_INDACC_CTLSTSr, &ctlsts, TARGET_SELECTf, ts); 9759 soc_reg_field_set(unit, CHIP_INDACC_CTLSTSr, &ctlsts, WR_REQf, 1); 9760 /* assigning the reg_addr in Clause22 format */ 9761 reg_addr = phy_reg & 0x1f; 9762 soc_reg_field_set(unit, CHIP_INDACC_CTLSTSr, &ctlsts, ADDRESSf, reg_addr); 9763 9764 LOG_DEBUG(BSL_LS_SOC_MII, 9765 (BSL_META_U(unit, 9766 "_soc_saber2_indacc_write:" 9767 "INDACC_CTLSTSr=0x%08x\n"), ctlsts)); 9768 SOC_IF_ERROR_RETURN( 9769 WRITE_CHIP_INDACC_CTLSTSr(unit, REG_PORT_ANY, ctlsts)); 9770 9771 SOC_IF_ERROR_RETURN( 9772 _soc_saber2_indacc_wait(unit, WR_RDYf)); 9773 9774 SOC_IF_ERROR_RETURN( 9775 WRITE_CHIP_INDACC_CTLSTSr(unit, REG_PORT_ANY, 0)); 9776 9777 return SOC_E_NONE; 9778 } 9779 9780 STATIC int 9781 _soc_saber2_sbus_qsgmii_write(int unit, 9782 uint32 phy_addr, uint32 phy_reg, uint32 phy_data) 9783 { 9784 uint32 reg_addr, reg_data; 9785 9786 LOG_DEBUG(BSL_LS_SOC_MII, 9787 (BSL_META_U(unit, 9788 "_soc_saber2_sbus_qsgmii_write" 9789 "(%d,0x%x,0x%08x,0x%04x)..\n"), 9790 unit, phy_addr, phy_reg, phy_data)); 9791 9792 /* The "phy_reg" in Sbus MDIO access is expected in 32 bits PHY address 9793 * format with AER information included. Since this interface allows 9794 * MDIO access in Claue22 only, the AER process must be applied. 9795 */ 9796 9797 /* AER process : AER block selection */ 9798 reg_addr = 0x1f; 9799 QSGMII_REG_ADDR_LANE_SET(reg_addr, phy_reg); 9800 reg_data = 0xffd0; 9801 SOC_IF_ERROR_RETURN(_soc_saber2_indacc_write(unit, 9802 phy_addr, reg_addr, reg_data)); 9803 9804 /* AER process : lane control */ 9805 reg_addr = 0x1e; 9806 QSGMII_REG_ADDR_LANE_SET(reg_addr, phy_reg); 9807 /* lane control to indicated lane 0~7 for each QSGMIMI core */ 9808 reg_data = QSGMII_REG_ADDR_LANE(phy_reg) & 0x7; 9809 SOC_IF_ERROR_RETURN(_soc_saber2_indacc_write(unit, 9810 phy_addr, reg_addr, reg_data)); 9811 9812 /* target register block selection */ 9813 reg_addr = 0x1f; 9814 QSGMII_REG_ADDR_LANE_SET(reg_addr, phy_reg); 9815 reg_data = phy_reg & 0xfff0; 9816 SOC_IF_ERROR_RETURN(_soc_saber2_indacc_write(unit, 9817 phy_addr, reg_addr, reg_data)); 9818 9819 /* write data */ 9820 reg_addr = QSGMII_REG_ADDR_REG(phy_reg); 9821 QSGMII_REG_ADDR_LANE_SET(reg_addr, phy_reg); 9822 SOC_IF_ERROR_RETURN(_soc_saber2_indacc_write(unit, 9823 phy_addr, reg_addr, phy_data)); 9824 9825 LOG_DEBUG(BSL_LS_SOC_MII, 9826 (BSL_META_U(unit, 9827 "_soc_saber2_sbus_qsgmii_write()... Done!"))); 9828 9829 return SOC_E_NONE; 9830 } 9831 9832 9833 STATIC int 9834 _soc_saber2_sbus_qsgmii_read(int unit, 9835 uint32 phy_addr, uint32 phy_reg, uint32 *phy_data) 9836 { 9837 uint32 reg_addr, reg_data; 9838 9839 *phy_data = 0; 9840 9841 LOG_DEBUG(BSL_LS_SOC_MII, 9842 (BSL_META_U(unit, 9843 "_soc_saber2_sbus_qsgmii_read" 9844 "(%d,0x%x,0x%08x,*phy_data)..\n"), 9845 unit, phy_addr, phy_reg)); 9846 9847 /* The "phy_reg" in Sbus MDIO access is expected in 32 bits PHY address 9848 * format with AER information included. Since this interface allows 9849 * MDIO access in Claue22 only, the AER process must be applied. 9850 */ 9851 9852 /* AER process : AER block selection */ 9853 reg_addr = 0x1f; 9854 QSGMII_REG_ADDR_LANE_SET(reg_addr, phy_reg); 9855 reg_data = 0xffd0; 9856 SOC_IF_ERROR_RETURN(_soc_saber2_indacc_write(unit, 9857 phy_addr, reg_addr, reg_data)); 9858 9859 /* AER process : lane control */ 9860 reg_addr = 0x1e; 9861 QSGMII_REG_ADDR_LANE_SET(reg_addr, phy_reg); 9862 /* lane control to indicated lane 0~7 for each QSGMIMI core */ 9863 reg_data = QSGMII_REG_ADDR_LANE(phy_reg) & 0x7; 9864 SOC_IF_ERROR_RETURN(_soc_saber2_indacc_write(unit, 9865 phy_addr, reg_addr, reg_data)); 9866 9867 /* target register block selection */ 9868 reg_addr = 0x1f; 9869 QSGMII_REG_ADDR_LANE_SET(reg_addr, phy_reg); 9870 reg_data = phy_reg & 0xfff0; 9871 SOC_IF_ERROR_RETURN(_soc_saber2_indacc_write(unit, 9872 phy_addr, reg_addr, reg_data)); 9873 9874 /* read data */ 9875 reg_addr = QSGMII_REG_ADDR_REG(phy_reg); 9876 QSGMII_REG_ADDR_LANE_SET(reg_addr, phy_reg); 9877 SOC_IF_ERROR_RETURN(_soc_saber2_indacc_read(unit, 9878 phy_addr, reg_addr, ®_data)); 9879 9880 *phy_data = reg_data; 9881 9882 LOG_DEBUG(BSL_LS_SOC_MII, 9883 (BSL_META_U(unit, 9884 "_soc_saber2_sbus_qsgmii_read()...data=0x%04x\n"), 9885 *phy_data)); 9886 9887 return SOC_E_NONE; 9888 } 9889 9890 int 9891 _soc_saber2_mdio_reg_write(int unit, uint32 phy_addr, 9892 uint32 phy_reg, uint32 phy_data) 9893 { 9894 int rv = SOC_E_NONE; 9895 int port, phy_port, blk; 9896 int qsgmii_reg = 0; 9897 9898 LOG_DEBUG(BSL_LS_SOC_MII, 9899 (BSL_META_U(unit, 9900 "_soc_saber2_mdio_reg_write(%d,0x%x,0x%08x,0x%04x)..\n"), 9901 unit, phy_addr, phy_reg,phy_data)); 9902 /* Physical port based on MDIO address */ 9903 phy_port = _soc_saber2_mdio_addr_to_port(unit, phy_addr); 9904 /* No Physical to Logical Port Mapping so direct 1 to 1 */ 9905 port = phy_port; 9906 SOC_IF_ERROR_RETURN(_soc_saber2_sbus_tsc_block(unit, 9907 phy_port, XLPORT_WC_UCMEM_DATAm, &blk)); 9908 9909 /* access interface selection */ 9910 SOC_IF_ERROR_RETURN(_soc_saber2_qsgmii_reg_access_check(unit, 9911 port, phy_reg, &qsgmii_reg)); 9912 if (qsgmii_reg) { 9913 MIIM_LOCK(unit); 9914 rv = _soc_saber2_sbus_qsgmii_write(unit, phy_addr, 9915 phy_reg, phy_data); 9916 MIIM_UNLOCK(unit); 9917 } else { 9918 TSC_REG_ADDR_TSCID_SET(phy_reg, phy_addr); 9919 rv = soc_sbus_tsc_reg_write(unit, port, blk, phy_addr, 9920 phy_reg, phy_data); 9921 } 9922 return rv; 9923 } 9924 9925 int 9926 _soc_saber2_mdio_reg_read(int unit, uint32 phy_addr, 9927 uint32 phy_reg, uint32 *phy_data) 9928 { 9929 int rv = SOC_E_NONE; 9930 int port, phy_port, blk; 9931 int qsgmii_reg = 0; 9932 9933 LOG_DEBUG(BSL_LS_SOC_MII, 9934 (BSL_META_U(unit, 9935 "_soc_saber2_mdio_reg_read(%d,0x%x,0x%08x,*phy_data)..\n"), 9936 unit, phy_addr, phy_reg)); 9937 /* Physical port based on MDIO address */ 9938 phy_port = _soc_saber2_mdio_addr_to_port(unit, phy_addr); 9939 /* No Physical to Logical Port Mapping so direct 1 to 1 */ 9940 port = phy_port; 9941 SOC_IF_ERROR_RETURN(_soc_saber2_sbus_tsc_block(unit, 9942 phy_port, XLPORT_WC_UCMEM_DATAm, &blk)); 9943 9944 /* access interface selection */ 9945 SOC_IF_ERROR_RETURN(_soc_saber2_qsgmii_reg_access_check(unit, 9946 port, phy_reg, &qsgmii_reg)); 9947 if (qsgmii_reg) { 9948 MIIM_LOCK(unit); 9949 #if 0 9950 /* WARMBOOT STUFF */ 9951 SOC_ALLOW_WB_WRITE(unit, _soc_saber2_sbus_qsgmii_read(unit, phy_addr, 9952 phy_reg, phy_data), rv); 9953 #endif 9954 SOC_IF_ERROR_RETURN(_soc_saber2_sbus_qsgmii_read(unit, phy_addr, 9955 phy_reg, phy_data)); 9956 MIIM_UNLOCK(unit); 9957 } else { 9958 TSC_REG_ADDR_TSCID_SET(phy_reg, phy_addr); 9959 rv = soc_sbus_tsc_reg_read(unit, port, blk, phy_addr, 9960 phy_reg, phy_data); 9961 } 9962 return rv; 9963 } 9964 9965 9966 9967 /* 9968 * Saber chip driver functions. 9969 */ 9970 soc_functions_t soc_saber2_drv_funs = { 9971 _soc_saber2_misc_init, /* soc_misc_init_f */ 9972 _soc_saber2_mmu_init, /* soc_mmu_init_f */ 9973 _soc_saber2_age_timer_get, /* soc_age_timer_get_f */ 9974 _soc_saber2_age_timer_max_get, /* soc_age_timer_max_get_f */ 9975 _soc_saber2_age_timer_set, /* soc_age_timer_set_f */ 9976 _soc_saber2_tsce_firmware_set, /* soc_phy_firmware_load_f */ 9977 _soc_saber2_mdio_reg_read, /* soc_sbus_mdio_read_f */ 9978 _soc_saber2_mdio_reg_write /* soc_sbus_mdio_write_f */ 9979 }; 9980 9981 9982 9983 /* Saber2 pbmp init sequence */ 9984 int _soc_saber2_get_cfg_num(int unit, int *new_cfg_num) 9985 { 9986 int cfg_num=-1; 9987 int max_cfg_num=0; 9988 int def_cfg_num=0; 9989 int offset_cfg_num=0; 9990 uint16 dev_id=0; 9991 uint8 rev_id=0; 9992 9993 #ifdef BCM_WARM_BOOT_SUPPORT 9994 if (SOC_WARM_BOOT(unit)) { 9995 cfg_num = COUNTOF(bcm56260_tdm_info) - 1; 9996 if (bcm56260_tdm_info[cfg_num].tdm_size != 0) { 9997 *new_cfg_num = cfg_num; 9998 return SOC_E_NONE; 9999 } 10000 /* FAll thru */ 10001 } 10002 #endif 10003 cfg_num = soc_property_get(unit, spn_BCM5626X_CONFIG,0xFF); 10004 10005 soc_cm_get_id(unit, &dev_id, &rev_id); 10006 switch(dev_id) { 10007 case BCM56260_DEVICE_ID: 10008 case BCM56261_DEVICE_ID: 10009 case BCM56265_DEVICE_ID: 10010 case BCM56266_DEVICE_ID: 10011 def_cfg_num = BCM56260_DEVICE_ID_DEFAULT_CFG; 10012 offset_cfg_num = BCM56260_DEVICE_ID_OFFSET_CFG; 10013 max_cfg_num = BCM56260_DEVICE_ID_MAX_CFG; 10014 break; 10015 case BCM56262_DEVICE_ID: 10016 case BCM56267_DEVICE_ID: 10017 def_cfg_num = BCM56262_DEVICE_ID_DEFAULT_CFG; 10018 offset_cfg_num = BCM56262_DEVICE_ID_OFFSET_CFG; 10019 max_cfg_num = BCM56262_DEVICE_ID_MAX_CFG; 10020 break; 10021 10022 case BCM56263_DEVICE_ID: 10023 case BCM56268_DEVICE_ID: 10024 def_cfg_num = BCM56263_DEVICE_ID_DEFAULT_CFG; 10025 offset_cfg_num = BCM56263_DEVICE_ID_OFFSET_CFG; 10026 max_cfg_num = BCM56263_DEVICE_ID_MAX_CFG; 10027 break; 10028 10029 case BCM56460_DEVICE_ID: 10030 case BCM56461_DEVICE_ID: 10031 case BCM56465_DEVICE_ID: 10032 case BCM56466_DEVICE_ID: 10033 def_cfg_num = BCM56460_DEVICE_ID_DEFAULT_CFG; 10034 offset_cfg_num = BCM56460_DEVICE_ID_OFFSET_CFG; 10035 max_cfg_num = BCM56460_DEVICE_ID_MAX_CFG; 10036 break; 10037 case BCM56462_DEVICE_ID: 10038 case BCM56467_DEVICE_ID: 10039 def_cfg_num = BCM56462_DEVICE_ID_DEFAULT_CFG; 10040 offset_cfg_num = BCM56462_DEVICE_ID_OFFSET_CFG; 10041 max_cfg_num = BCM56462_DEVICE_ID_MAX_CFG; 10042 break; 10043 case BCM56463_DEVICE_ID: 10044 case BCM56468_DEVICE_ID: 10045 def_cfg_num = BCM56463_DEVICE_ID_DEFAULT_CFG; 10046 offset_cfg_num = BCM56463_DEVICE_ID_OFFSET_CFG; 10047 max_cfg_num = BCM56463_DEVICE_ID_MAX_CFG; 10048 break; 10049 10050 case BCM56233_DEVICE_ID: 10051 def_cfg_num = BCM56233_DEVICE_ID_DEFAULT_CFG; 10052 offset_cfg_num = BCM56233_DEVICE_ID_OFFSET_CFG; 10053 max_cfg_num = BCM56233_DEVICE_ID_MAX_CFG; 10054 break; 10055 10056 /* Not supported yet */ 10057 return SOC_E_UNAVAIL; 10058 } 10059 10060 if (cfg_num == 0xFF) { 10061 *new_cfg_num = def_cfg_num; 10062 } else { 10063 if (cfg_num == 0) { 10064 LOG_DEBUG(BSL_LS_SOC_COMMON, (BSL_META_U(unit, "Config=0 is not allowed \n"))); 10065 return SOC_E_PARAM; 10066 } 10067 *new_cfg_num = cfg_num + offset_cfg_num; 10068 } 10069 if (*new_cfg_num > max_cfg_num) { 10070 LOG_ERROR(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 10071 "Cfg_num:%d Internal cfg_num:%d \n"),cfg_num,*new_cfg_num)); 10072 LOG_ERROR(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 10073 "Wrong %s ==> cfg_num:%d DEFAULT:%d START:%d MAX:%d \n"), 10074 spn_BCM5626X_CONFIG, cfg_num, 10075 def_cfg_num-offset_cfg_num,1,max_cfg_num-offset_cfg_num)); 10076 *new_cfg_num = def_cfg_num; 10077 return SOC_E_NONE; 10078 } 10079 LOG_VERBOSE(BSL_LS_SOC_COMMON, 10080 (BSL_META_U(unit, 10081 "Info Cfg_num:%d Internal cfg_num:%d \n"),cfg_num,*new_cfg_num)); 10082 10083 return SOC_E_NONE; 10084 } 10085 10086 #ifdef BCM_WARM_BOOT_SUPPORT 10087 10088 uint32 *iarb_tdm[SOC_MAX_NUM_DEVICES]; 10089 10090 int soc_saber2_retrieve_hw_tdm(int unit) 10091 { 10092 uint32 rval = 0; 10093 uint8 tdm_no = 0; 10094 soc_mem_t tdm_table[]={IARB_TDM_TABLEm , IARB_TDM_TABLE_1m}; 10095 iarb_tdm_table_entry_t iarb_tdm_entry; 10096 uint32 num_iarb_entry = 0, iarb_size=0; 10097 int index = 0; 10098 10099 SOC_IF_ERROR_RETURN(READ_IARB_TDM_CONTROLr(unit, &rval)); 10100 tdm_no = soc_reg_field_get(unit, IARB_TDM_CONTROLr, rval, SELECT_TDMf); 10101 10102 /* Allocate memory for TDM. Get size from IARB table. */ 10103 num_iarb_entry = soc_mem_index_count(unit,IARB_TDM_TABLEm); 10104 iarb_size = num_iarb_entry * sizeof(iarb_tdm_table_entry_t); 10105 10106 if(iarb_tdm[unit] != NULL) { 10107 sal_free(iarb_tdm[unit]); 10108 iarb_tdm[unit] = NULL; 10109 } 10110 iarb_tdm[unit] = sal_alloc(iarb_size, "iarb_tdm"); 10111 if (iarb_tdm[unit] == NULL) { 10112 return SOC_E_MEMORY; 10113 } 10114 sal_memset(iarb_tdm[unit], 0, iarb_size); 10115 10116 for (index = 0; index < num_iarb_entry; index++) { 10117 SOC_IF_ERROR_RETURN(soc_mem_read(unit, tdm_table[tdm_no], SOC_BLOCK_ALL, 10118 index, &iarb_tdm_entry)); 10119 iarb_tdm[unit][index] = soc_mem_field32_get(unit, tdm_table[tdm_no], 10120 &iarb_tdm_entry, PORT_NUMf); 10121 } 10122 return SOC_E_NONE; 10123 } 10124 10125 10126 /* Functions related to flexio scache */ 10127 int _soc_saber2_flexio_scache_allocate(int unit) 10128 { 10129 int rv=SOC_E_NONE; 10130 uint8 *flexio_scache_ptr; 10131 soc_scache_handle_t scache_handle; 10132 uint32 alloc_get=0; 10133 uint32 alloc_size = sizeof(scache_begin_magic_number) + 10134 sizeof(sb2_scache_tdm_info) + 10135 sizeof(sb2_scache_tdm) + 10136 sizeof(sb2_scache_speed) + 10137 sizeof(sb2_scache_port_details) + 10138 sizeof(scache_end_magic_number); 10139 10140 SOC_SCACHE_HANDLE_SET(scache_handle, unit, SOC_SCACHE_FLEXIO_HANDLE, 10141 BCM_FLEXIO_SCACHE_DEFAULT_PARTITION); 10142 10143 rv = soc_scache_alloc(unit, scache_handle, alloc_size); 10144 if (rv == SOC_E_CONFIG) { 10145 /* Probably Level1 */ 10146 return SOC_E_NONE; 10147 } 10148 10149 /* NotRequired but just to confirm Get the pointer for the Level 2 cache */ 10150 SOC_IF_ERROR_RETURN(soc_scache_ptr_get(unit, scache_handle, 10151 &flexio_scache_ptr, &alloc_get)); 10152 10153 if (alloc_get != alloc_size) { 10154 /* Expected size doesn't match retrieved size */ 10155 return SOC_E_INTERNAL; 10156 } 10157 if (NULL == flexio_scache_ptr) { 10158 return SOC_E_MEMORY; 10159 } 10160 10161 LOG_VERBOSE(BSL_LS_SOC_COMMON, 10162 (BSL_META_U(unit, 10163 "%s()[LINE:%d] DONE \n"),FUNCTION_NAME(), __LINE__)); 10164 return SOC_E_NONE; 10165 } 10166 10167 int _soc_saber2_flexio_scache_retrieve(int unit) 10168 { 10169 int rv, port; 10170 uint8 *flexio_scache_ptr; 10171 soc_scache_handle_t scache_handle; 10172 uint32 alloc_get=0; 10173 uint32 alloc_size = sizeof(sb2_scache_tdm_info) + 10174 sizeof(sb2_scache_tdm) + 10175 sizeof(sb2_scache_speed) + 10176 sizeof(sb2_scache_port_details) + 10177 SOC_WB_SCACHE_CONTROL_SIZE; 10178 uint32 scache_offset=0; 10179 uint16 default_ver = BCM_WB_DEFAULT_VERSION; 10180 uint16 recovered_ver; 10181 10182 SOC_SCACHE_HANDLE_SET(scache_handle, unit, SOC_SCACHE_FLEXIO_HANDLE, 10183 BCM_FLEXIO_SCACHE_DEFAULT_PARTITION); 10184 10185 rv = soc_scache_ptr_get(unit, scache_handle, 10186 &flexio_scache_ptr, &alloc_get); 10187 if (rv == SOC_E_NOT_FOUND) { 10188 /* Partition 1 is not available, fall back to old retrieve procedure */ 10189 SOC_IF_ERROR_RETURN(_soc_saber2_flexio_scache_retrieve_part0(unit)); 10190 return SOC_E_NONE; 10191 } 10192 10193 if (alloc_get != (alloc_size + SOC_WB_SCACHE_CONTROL_SIZE)) { 10194 /* Expected size doesn't match retrieved size */ 10195 return SOC_E_INTERNAL; 10196 } 10197 10198 /* Partition 1 is found. So Extract sync-ed details */ 10199 scache_offset = 0; 10200 sal_memcpy(&recovered_ver, 10201 &flexio_scache_ptr[scache_offset], sizeof(uint16)); 10202 10203 if( default_ver > recovered_ver ) { 10204 LOG_VERBOSE(BSL_LS_SOC_COMMON, 10205 (BSL_META_U(unit, "Scache Upgraded.\n"))); 10206 } 10207 10208 scache_offset += SOC_WB_SCACHE_CONTROL_SIZE; 10209 sal_memcpy(&sb2_scache_tdm_info, 10210 &flexio_scache_ptr[scache_offset], sizeof(sb2_scache_tdm_info)); 10211 10212 bcm56260_tdm_info[COUNTOF(bcm56260_tdm_info)-1] = sb2_scache_tdm_info; 10213 10214 scache_offset += sizeof(sb2_scache_tdm_info); 10215 sal_memcpy(&sb2_scache_tdm, 10216 &flexio_scache_ptr[scache_offset], sizeof(sb2_scache_tdm)); 10217 10218 scache_offset += sizeof(sb2_scache_tdm); 10219 sal_memcpy(&sb2_scache_speed, 10220 &flexio_scache_ptr[scache_offset], sizeof(sb2_scache_speed)); 10221 10222 scache_offset += sizeof(sb2_scache_speed); 10223 sal_memcpy(&sb2_scache_port_details, 10224 &flexio_scache_ptr[scache_offset], 10225 sizeof(sb2_scache_port_details)); 10226 scache_offset += sizeof(sb2_scache_port_details); 10227 10228 LOG_VERBOSE(BSL_LS_SOC_COMMON, 10229 (BSL_META_U(unit, 10230 "%s()[LINE:%d] \n"),FUNCTION_NAME(), __LINE__)); 10231 10232 if ((default_ver >= BCM_WB_VERSION_1_4) && 10233 (recovered_ver < BCM_WB_VERSION_1_4)) { 10234 for (port=25 ; port <= SB2_MAX_PHYSICAL_PORTS ; port++) { 10235 if ((sb2_scache_port_details[port-1].port_type & GE_PORT) && 10236 sb2_2p5g_ports[port-1]) { 10237 sb2_scache_speed[port - 1] = 2500; 10238 sb2_scache_port_details[port-1].port_speed = 2500; 10239 } 10240 } 10241 } 10242 10243 return SOC_E_NONE; 10244 } 10245 10246 10247 int _soc_saber2_flexio_scache_retrieve_part0(int unit) 10248 { 10249 int rv; 10250 uint8 *flexio_scache_ptr; 10251 soc_scache_handle_t scache_handle; 10252 uint32 alloc_get=0; 10253 uint32 alloc_size = sizeof(scache_begin_magic_number) + 10254 sizeof(sb2_scache_tdm_info) + 10255 sizeof(sb2_scache_tdm) + 10256 sizeof(sb2_scache_speed) + 10257 sizeof(sb2_scache_port_details) + 10258 sizeof(scache_end_magic_number); 10259 uint32 scache_offset=0; 10260 10261 SOC_SCACHE_HANDLE_SET(scache_handle, unit, SOC_SCACHE_FLEXIO_HANDLE, 0); 10262 10263 /* NotRequired but just to confirm Get the pointer for the Level 2 cache */ 10264 rv = soc_scache_ptr_get(unit, scache_handle, 10265 &flexio_scache_ptr, &alloc_get); 10266 if (rv == SOC_E_NOT_FOUND) { 10267 /* Probably Level1 */ 10268 return SOC_E_NONE; 10269 } 10270 10271 if (alloc_get != (alloc_size + SOC_WB_SCACHE_CONTROL_SIZE)) { 10272 /* Expected size doesn't match retrieved size */ 10273 return SOC_E_INTERNAL; 10274 } 10275 10276 if (NULL == flexio_scache_ptr) { 10277 return SOC_E_MEMORY; 10278 } 10279 10280 scache_offset = 0; 10281 if(sal_memcmp(&flexio_scache_ptr[scache_offset], 10282 &scache_begin_magic_number[0], 10283 sizeof(scache_begin_magic_number)) != 0) { 10284 LOG_CLI((BSL_META_U(unit, 10285 "Corrupt scache for flexio operation \n"))); 10286 return SOC_E_INTERNAL; 10287 } 10288 10289 scache_offset += sizeof(scache_begin_magic_number); 10290 sal_memcpy(&sb2_scache_tdm_info, 10291 &flexio_scache_ptr[scache_offset], sizeof(sb2_scache_tdm_info)); 10292 10293 bcm56260_tdm_info[COUNTOF(bcm56260_tdm_info)-1] = sb2_scache_tdm_info; 10294 10295 scache_offset += sizeof(sb2_scache_tdm_info); 10296 10297 /* 10298 * Part 0 Version has an issue in TDM sync. 10299 * So in part 0 version, Level 1 recovery performed to retrieve TDM. 10300 */ 10301 LOG_INFO(BSL_LS_SOC_COMMON, 10302 (BSL_META_U(unit, 10303 "Previous ver was synced with incorrect TDM," 10304 "Now LEVEL 1 recovery for TDM\n"))); 10305 10306 SOC_IF_ERROR_RETURN(soc_saber2_retrieve_hw_tdm(unit)); 10307 if(iarb_tdm[unit] == NULL) { 10308 return SOC_E_INTERNAL; 10309 } 10310 10311 sal_memcpy(&sb2_scache_tdm, iarb_tdm[unit], sizeof(sb2_scache_tdm)); 10312 10313 kt2_tdm_display(unit, (uint32 *) (&sb2_scache_tdm[0]), 10314 sb2_scache_tdm_info.tdm_size, 10315 sb2_scache_tdm_info.row, 10316 sb2_scache_tdm_info.col); 10317 10318 scache_offset += sizeof(sb2_scache_tdm); 10319 sal_memcpy(&sb2_scache_speed, 10320 &flexio_scache_ptr[scache_offset], sizeof(sb2_scache_speed)); 10321 10322 scache_offset += sizeof(sb2_scache_speed); 10323 sal_memcpy(&sb2_scache_port_details, 10324 &flexio_scache_ptr[scache_offset], 10325 sizeof(sb2_scache_port_details)); 10326 scache_offset += sizeof(sb2_scache_port_details); 10327 10328 if (sal_memcmp(&flexio_scache_ptr[scache_offset], 10329 &scache_end_magic_number[0], 10330 sizeof(scache_end_magic_number)) != 0) { 10331 LOG_CLI((BSL_META_U(unit, 10332 "Corrupt scache for flexio operation \n"))); 10333 return SOC_E_INTERNAL; 10334 } 10335 10336 /* Allocate SCACHE at part 1 Now */ 10337 SOC_IF_ERROR_RETURN(_soc_saber2_flexio_scache_allocate(unit)); 10338 10339 LOG_VERBOSE(BSL_LS_SOC_COMMON, 10340 (BSL_META_U(unit, 10341 "%s()[LINE:%d] \n"),FUNCTION_NAME(), __LINE__)); 10342 10343 return SOC_E_NONE; 10344 } 10345 10346 int _soc_saber2_flexio_scache_sync(int unit) 10347 { 10348 int rv; 10349 uint8 *flexio_scache_ptr; 10350 soc_scache_handle_t scache_handle; 10351 uint32 alloc_get=0; 10352 uint32 alloc_size = sizeof(sb2_scache_tdm_info) + 10353 sizeof(sb2_scache_tdm) + 10354 sizeof(sb2_scache_speed) + 10355 sizeof(sb2_scache_port_details) + 10356 SOC_WB_SCACHE_CONTROL_SIZE; 10357 uint32 scache_offset=0; 10358 int cfg_num=0; 10359 uint32 port=0; 10360 uint16 default_ver = BCM_WB_DEFAULT_VERSION; 10361 10362 SOC_SCACHE_HANDLE_SET(scache_handle, unit, SOC_SCACHE_FLEXIO_HANDLE, 10363 BCM_FLEXIO_SCACHE_DEFAULT_PARTITION); 10364 10365 /* NotRequired but just to confirm Get the pointer for the Level 2 cache */ 10366 rv = soc_scache_ptr_get(unit, scache_handle, 10367 &flexio_scache_ptr, &alloc_get); 10368 if (rv == SOC_E_NOT_FOUND) { 10369 /* Probably Level1 */ 10370 return SOC_E_NONE; 10371 } 10372 if (alloc_get != (alloc_size + SOC_WB_SCACHE_CONTROL_SIZE)) { 10373 /* Expected size doesn't match retrieved size */ 10374 return SOC_E_INTERNAL; 10375 } 10376 if (NULL == flexio_scache_ptr) { 10377 return SOC_E_MEMORY; 10378 } 10379 10380 SOC_IF_ERROR_RETURN(_soc_saber2_get_cfg_num(unit, &cfg_num)); 10381 _sb2_config_id[unit] = cfg_num; 10382 10383 scache_offset = 0; 10384 sal_memcpy(&flexio_scache_ptr[scache_offset], 10385 &default_ver, sizeof(uint16)); 10386 10387 scache_offset += SOC_WB_SCACHE_CONTROL_SIZE; 10388 sal_memcpy(&flexio_scache_ptr[scache_offset], 10389 &bcm56260_tdm_info[cfg_num], 10390 sizeof(sb2_scache_tdm_info)); 10391 10392 scache_offset += sizeof(sb2_scache_tdm_info); 10393 sal_memcpy(&flexio_scache_ptr[scache_offset], 10394 &sb2_current_tdm[0], 10395 sizeof(uint32)* bcm56260_tdm_info[cfg_num].tdm_size); 10396 10397 scache_offset += sizeof(sb2_scache_tdm); 10398 10399 for (port=1 ; port <= SB2_MAX_PHYSICAL_PORTS ; port++) { 10400 sb2_scache_speed[port-1] = 0; 10401 10402 if (IS_MXQ_PORT(unit,port)) { 10403 if ((bcm56260_speed[unit][cfg_num][port-1] == 0) || /*Converted */ 10404 (bcm56260_speed[unit][cfg_num][port-1] >= 2500)) { 10405 sb2_scache_speed[port - 1] = 2500; 10406 } else { 10407 sb2_scache_speed[port - 1] = 1000; 10408 } 10409 } 10410 10411 if (IS_XE_PORT(unit,port)) { 10412 sb2_scache_speed[port - 1] = 10000; 10413 } 10414 10415 if (IS_HG_PORT(unit,port)) { 10416 sb2_scache_speed[port - 1] = 10000; 10417 } 10418 10419 if (IS_XL_PORT(unit, port) && (IS_GE_PORT(unit, port))) { 10420 if (bcm56260_speed[unit][cfg_num][port-1] >= 2500) { 10421 sb2_scache_speed[port - 1] = 2500; 10422 } else { 10423 sb2_scache_speed[port - 1] = 1000; 10424 } 10425 } 10426 } 10427 10428 sal_memcpy(&flexio_scache_ptr[scache_offset], 10429 &sb2_scache_speed[0], sizeof(sb2_scache_speed)); 10430 scache_offset += sizeof(sb2_scache_speed); 10431 10432 for (port=1 ; port <= SB2_MAX_PHYSICAL_PORTS ; port++) { 10433 /* mxqblock = (*kt2_port_to_mxqblock[unit])[port-1]; */ 10434 sb2_scache_port_details[port-1].start_port_no = port; 10435 sb2_scache_port_details[port-1].end_port_no = port; 10436 sb2_scache_port_details[port-1].port_incr = 1; 10437 sb2_scache_port_details[port-1].port_type = 0; 10438 sb2_scache_port_details[port-1].port_speed = 0xFFFF; 10439 10440 if (IS_MXQ_PORT(unit,port)) { 10441 if ((bcm56260_speed[unit][cfg_num][port-1] == 0) || /*Converted */ 10442 (bcm56260_speed[unit][cfg_num][port-1] >= 2500)) { 10443 sb2_scache_port_details[port-1].port_speed = 2500; 10444 } else { 10445 sb2_scache_port_details[port-1].port_speed = 1000; 10446 } 10447 sb2_scache_port_details[port-1].port_type = GE_PORT; 10448 } 10449 10450 if (IS_XE_PORT(unit,port)) { 10451 sb2_scache_port_details[port-1].port_speed = 10000; 10452 sb2_scache_port_details[port-1].port_type |= XE_PORT; 10453 if (IS_MXQ_PORT(unit,port)) { 10454 sb2_scache_port_details[port-1].port_incr = 4; 10455 } 10456 } 10457 10458 if (IS_HG_PORT(unit,port)) { 10459 sb2_scache_port_details[port-1].port_speed = 10000; 10460 sb2_scache_port_details[port-1].port_type |= HG_PORT; 10461 sb2_scache_port_details[port-1].port_type |= STK_PORT; 10462 } 10463 10464 if (IS_XL_PORT(unit, port) && (IS_GE_PORT(unit, port))) { 10465 if (bcm56260_speed[unit][cfg_num][port-1] >= 2500) { 10466 sb2_scache_port_details[port-1].port_speed = 2500; 10467 } else { 10468 sb2_scache_port_details[port-1].port_speed = 1000; 10469 } 10470 sb2_scache_port_details[port-1].port_type |= GE_PORT; 10471 } 10472 } 10473 sal_memcpy(&flexio_scache_ptr[scache_offset], 10474 &sb2_scache_port_details, 10475 sizeof(sb2_scache_port_details)); 10476 LOG_VERBOSE(BSL_LS_SOC_COMMON, 10477 (BSL_META_U(unit, 10478 "%s()[LINE:%d] \n"),FUNCTION_NAME(), __LINE__)); 10479 return SOC_E_NONE; 10480 } 10481 #endif 10482 10483 /* Function to return the speed based on the cfg_num */ 10484 int soc_saber2_xl_port_speed_get(int unit, int port, int *speed) { 10485 int cfg_num=0, max_speed=0; 10486 soc_pbmp_t my_pbmp_xport_xe; 10487 soc_info_t *si=&SOC_INFO(unit); 10488 10489 SOC_PBMP_CLEAR(my_pbmp_xport_xe); 10490 my_pbmp_xport_xe = soc_property_get_pbmp_default(unit, spn_PBMP_XPORT_XE, 10491 my_pbmp_xport_xe); 10492 10493 SOC_IF_ERROR_RETURN(_soc_saber2_get_cfg_num(unit, &cfg_num)); 10494 max_speed = bcm56260_speed[unit][cfg_num][port-1]; 10495 10496 if (max_speed > si->port_speed_max[port]) { 10497 *speed = si->port_speed_max[port]; 10498 if (si->port_speed_max[port] == 0) { 10499 /* port_speed_max cannot be 0 for a valid port. 10500 * During warmboot sync, the port must have been merged. 10501 * Now after upgrade, the port_speed_max would be 0. 10502 * So return max speed. 10503 */ 10504 *speed = max_speed; 10505 } 10506 } 10507 10508 if ((max_speed == 10000) && !(SOC_PBMP_MEMBER(my_pbmp_xport_xe, port))) { 10509 *speed = 11000; 10510 if(eagle_n4s_mode) { 10511 /* In mixed mode, the hg ports would come up in single 10512 * or dual mode. Either way xe and hg ports would be 10G. */ 10513 *speed = 10000; 10514 } 10515 } else { 10516 *speed = (max_speed > si->port_speed_max[port]) ? max_speed : 10517 si->port_speed_max[port]; 10518 } 10519 10520 return SOC_E_NONE; 10521 } 10522 10523 /* Functions related to initlializing sb2 port bitmap */ 10524 void 10525 soc_saber2_pbmp_init(int unit, sb2_pbmp_t sb2_pbmp) 10526 { 10527 int port; 10528 soc_pbmp_t my_pbmp_xport_xe; 10529 soc_pbmp_t my_pbmp_xport_ge; 10530 uint32 loop_index=0, port_speed; 10531 int sb2_port_details_index=0; 10532 uint8 sb2_port_used_flags[32]={0}; 10533 int old_num_lanes, num_lanes, port_incr; 10534 uint16 dev_id=0; 10535 uint8 rev_id=0; 10536 10537 soc_cm_get_id(unit, &dev_id, &rev_id); 10538 10539 /* Unit Specific Allocation */ 10540 if (sb2_port_speeds[unit] != NULL) { 10541 sal_free(sb2_port_speeds[unit]); 10542 sb2_port_speeds[unit] = NULL; 10543 } 10544 sb2_port_speeds[unit] = sal_alloc(sizeof(sb2_port_speeds_t), 10545 "sb2_port_speeds_t"); 10546 if (sb2_port_speeds[unit] == NULL) { 10547 LOG_DEBUG(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 10548 "Resource issue %s:%d..Couldn't allocate memory=%d \n"), 10549 FUNCTION_NAME(), __LINE__, 10550 (int)sizeof(sb2_port_speeds_t))); 10551 return; 10552 } 10553 10554 if (bcm56260_speed[unit] != NULL) { 10555 sal_free(bcm56260_speed[unit]); 10556 bcm56260_speed[unit] = NULL; 10557 } 10558 bcm56260_speed[unit] = sal_alloc(sizeof(sb2_speed_t) * 10559 (sizeof(bcm56260_speed_s) / 10560 sizeof(bcm56260_speed_s[0])), 10561 "bcm56260_speed"); 10562 if (bcm56260_speed[unit] == NULL) { 10563 LOG_DEBUG(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 10564 "Resource issue %s:%d..Couldn't allocate memory=%d \n"), 10565 FUNCTION_NAME(), __LINE__, 10566 (int)sizeof(mxqspeeds_t))); 10567 return ; 10568 } 10569 10570 for (loop_index = 0 ; 10571 loop_index < sizeof(bcm56260_speed_s ) / 10572 sizeof(bcm56260_speed_s[0]); 10573 loop_index++) { 10574 sal_memcpy(bcm56260_speed[unit][loop_index], 10575 bcm56260_speed_s[loop_index], 10576 sizeof(sb2_speed_t)); 10577 } 10578 10579 if (sb2_port_to_block[unit] != NULL) { 10580 sal_free(sb2_port_to_block[unit]); 10581 sb2_port_to_block[unit] = NULL; 10582 } 10583 sb2_port_to_block[unit] = sal_alloc(sizeof(sb2_port_to_block_s), 10584 "sb2_port_to_block_t"); 10585 if (sb2_port_to_block[unit] == NULL) { 10586 LOG_DEBUG(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 10587 "Resource issue %s:%d..Couldn't allocate memory=%d \n"), 10588 FUNCTION_NAME(), __LINE__, 10589 (int)sizeof(sb2_port_to_block))); 10590 return ; 10591 } 10592 sal_memcpy(sb2_port_to_block[unit],sb2_port_to_block_s, 10593 sizeof(sb2_port_to_block_s)); 10594 10595 if (sb2_port_to_block_subports[unit] != NULL) { 10596 sal_free(sb2_port_to_block_subports[unit]); 10597 sb2_port_to_block_subports[unit] = NULL; 10598 } 10599 sb2_port_to_block_subports[unit] = 10600 sal_alloc(sizeof(sb2_port_to_block_subports_s), 10601 "sb2_port_to_block_t"); 10602 if (sb2_port_to_block_subports[unit] == NULL) { 10603 LOG_DEBUG(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 10604 "Resource issue %s:%d..Couldn't allocate memory=%d \n"), 10605 FUNCTION_NAME(), __LINE__, 10606 (int) sizeof(sb2_port_to_block_subports))); 10607 return ; 10608 } 10609 sal_memcpy(sb2_port_to_block_subports[unit], 10610 sb2_port_to_block_subports_s,sizeof(sb2_port_to_block_subports_s)); 10611 10612 if (sb2_block_ports[unit] != NULL) { 10613 sal_free(sb2_block_ports[unit]); 10614 sb2_block_ports[unit] = NULL; 10615 } 10616 sb2_block_ports[unit] = sal_alloc(sizeof(sb2_block_ports_s), 10617 "sb2_block_ports_t"); 10618 if (sb2_block_ports[unit] == NULL) { 10619 LOG_DEBUG(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 10620 "Resource issue %s:%d..Couldn't allocate memory=%d \n"), 10621 FUNCTION_NAME(), __LINE__, 10622 (int)sizeof(sb2_block_ports))); 10623 return ; 10624 } 10625 sal_memcpy(sb2_block_ports[unit],sb2_block_ports_s, 10626 sizeof(sb2_block_ports_s)); 10627 10628 /* Initialize PBMPs */ 10629 SOC_PBMP_CLEAR(*sb2_pbmp.pbmp_gport_stack); 10630 SOC_PBMP_CLEAR(*sb2_pbmp.pbmp_mxq); 10631 SOC_PBMP_CLEAR(*sb2_pbmp.pbmp_mxq1g); 10632 SOC_PBMP_CLEAR(*sb2_pbmp.pbmp_mxq2p5g); 10633 SOC_PBMP_CLEAR(*sb2_pbmp.pbmp_mxq10g); 10634 SOC_PBMP_CLEAR(*sb2_pbmp.pbmp_xport_xe); 10635 SOC_PBMP_CLEAR(*sb2_pbmp.pbmp_xport_ge); 10636 SOC_PBMP_CLEAR(*sb2_pbmp.pbmp_xl); 10637 SOC_PBMP_CLEAR(*sb2_pbmp.pbmp_xl1g); 10638 SOC_PBMP_CLEAR(*sb2_pbmp.pbmp_xl2p5g); 10639 SOC_PBMP_CLEAR(*sb2_pbmp.pbmp_xl10g); 10640 /* SOC_PBMP_CLEAR(*sb2_pbmp.pbmp_valid); */ 10641 SOC_PBMP_CLEAR(*sb2_pbmp.pbmp_pp); 10642 SOC_PBMP_CLEAR(*sb2_pbmp.pbmp_linkphy); 10643 10644 if (_soc_saber2_get_cfg_num(unit, &sb2_port_details_index) != SOC_E_NONE) { 10645 LOG_DEBUG(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 10646 "Retrieved WRONG CFG VALUE =%d\n"), sb2_port_details_index)); 10647 return ; 10648 } 10649 10650 if (sb2_port_details_index >= (sizeof(sb2_port_details)/ 10651 sizeof(sb2_port_details[0]))) { 10652 LOG_DEBUG(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 10653 "INTERNAL: WRONG CFG VALUE =%d\n"), sb2_port_details_index)); 10654 return ; 10655 } 10656 LOG_DEBUG(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 10657 "Internal Config Number : %d\n"), sb2_port_details_index)); 10658 10659 _sb2_config_id[unit] = sb2_port_details_index; 10660 10661 switch(dev_id) { 10662 case BCM56260_DEVICE_ID: 10663 case BCM56261_DEVICE_ID: 10664 case BCM56262_DEVICE_ID: 10665 case BCM56263_DEVICE_ID: 10666 case BCM56265_DEVICE_ID: 10667 case BCM56266_DEVICE_ID: 10668 case BCM56267_DEVICE_ID: 10669 case BCM56268_DEVICE_ID: 10670 sal_memcpy(sb2_port_speeds[unit], sb2_port_speeds_56260_1, 10671 sizeof(sb2_port_speeds_t)); 10672 break; 10673 10674 case BCM56460_DEVICE_ID: 10675 case BCM56461_DEVICE_ID: 10676 case BCM56462_DEVICE_ID: 10677 case BCM56463_DEVICE_ID: 10678 case BCM56465_DEVICE_ID: 10679 case BCM56466_DEVICE_ID: 10680 case BCM56467_DEVICE_ID: 10681 case BCM56468_DEVICE_ID: 10682 sal_memcpy(sb2_port_speeds[unit], sb2_port_speeds_56460_1, 10683 sizeof(sb2_port_speeds_t)); 10684 break; 10685 10686 case BCM56233_DEVICE_ID: 10687 sal_memcpy(sb2_port_speeds[unit], sb2_port_speeds_56233_1, 10688 sizeof(sb2_port_speeds_t)); 10689 break; 10690 10691 default: 10692 sal_memcpy(sb2_port_speeds[unit], sb2_port_speeds_56260_0, 10693 sizeof(sb2_port_speeds_t)); 10694 break; 10695 }; 10696 10697 SOC_PBMP_CLEAR(my_pbmp_xport_xe); 10698 SOC_PBMP_CLEAR(my_pbmp_xport_ge); 10699 if (!(SOC_WARM_BOOT(unit))) { 10700 eagle_n4s_mode = 0; 10701 eagle_n2_mode = 0; 10702 eagle_4ge_mode = 0; 10703 my_pbmp_xport_xe = soc_property_get_pbmp_default(unit, 10704 spn_PBMP_XPORT_XE, my_pbmp_xport_xe); 10705 my_pbmp_xport_ge = soc_property_get_pbmp_default(unit, 10706 spn_PBMP_XPORT_GE, my_pbmp_xport_ge); 10707 } 10708 10709 if (sb2_selected_port_details != NULL) { 10710 sal_free(sb2_selected_port_details); 10711 sb2_selected_port_details = NULL; 10712 sal_free(sb2_selected_port_details_orig); 10713 sb2_selected_port_details_orig = NULL; 10714 } 10715 10716 /* Note : size of sb2_port_details of all configs is same (72 bytes) */ 10717 sb2_selected_port_details = sal_alloc( 10718 sizeof(soc_port_details_t) * (SB2_MAX_PHYSICAL_PORTS+1), 10719 "sb2_block_ports_t"); 10720 10721 sb2_selected_port_details_orig = sal_alloc( 10722 sizeof(soc_port_details_t) * (SB2_MAX_PHYSICAL_PORTS+1), 10723 "sb2_block_ports_t"); 10724 10725 if ((sb2_selected_port_details == NULL) || 10726 (sb2_selected_port_details_orig == NULL)) { 10727 LOG_DEBUG(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 10728 "INTERNAL: Memory allocation failed for sb2_selected_port_details\n"))); 10729 return ; 10730 } 10731 10732 sal_memcpy(sb2_selected_port_details, 10733 sb2_port_details[sb2_port_details_index], 10734 sizeof(soc_port_details_t) * (SB2_MAX_PHYSICAL_PORTS+1)); 10735 10736 /* Keep the default config to compare later */ 10737 sal_memcpy(sb2_selected_port_details_orig, 10738 sb2_port_details[sb2_port_details_index], 10739 sizeof(soc_port_details_t) * (SB2_MAX_PHYSICAL_PORTS+1)); 10740 10741 if (!(SOC_WARM_BOOT(unit))) { 10742 /* Construct port bitmaps based on portgroup settings */ 10743 /* In case of warmboot, maintain saved settings */ 10744 loop_index=0; 10745 port_incr = 4; 10746 10747 for(port = 1; port <= SB2_MAX_PHYSICAL_PORTS; port += port_incr) { 10748 loop_index = (port / 4); 10749 10750 /* Modify only if the port is not disabled by default */ 10751 if (sb2_selected_port_details[loop_index].port_speed == 0) { 10752 continue; 10753 } 10754 10755 old_num_lanes = sb2_selected_port_details[loop_index].port_incr; 10756 num_lanes = soc_property_port_get(unit, port, spn_PORTGROUP, 0xFF); 10757 10758 if (num_lanes == 0xFF) { 10759 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 10760 "PortGroup not specified; Setting port %d -> num lanes : %d\n"), 10761 port, old_num_lanes)); 10762 num_lanes = old_num_lanes; 10763 } else if(!((num_lanes == 1) || (num_lanes == 2) || (num_lanes == 4))) { 10764 LOG_WARN(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 10765 "Invalid PortGroup config; Setting port %d -> num lanes : %d\n"), 10766 port, num_lanes)); 10767 num_lanes = old_num_lanes; 10768 } 10769 10770 if(old_num_lanes == num_lanes) { 10771 continue; 10772 } 10773 10774 if(port < 25) { 10775 /* Viper ports */ 10776 switch(num_lanes) { 10777 case PORTGROUP_SINGLE_MODE: 10778 if((old_num_lanes == 1) && 10779 (sb2_selected_port_details[loop_index].port_speed == 2500 )) { 10780 sb2_selected_port_details[loop_index].port_type = XE_PORT; 10781 sb2_selected_port_details[loop_index].port_incr = 4; 10782 sb2_selected_port_details[loop_index].port_speed = 10000; 10783 } else { 10784 /* 4 lane or 2 lane mode would not have enough bandwidth */ 10785 LOG_WARN(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 10786 "Invalid PortGroup port %d ; BW exceeds Max port speed\n"), port)); 10787 } 10788 break; 10789 case PORTGROUP_DUAL_MODE: 10790 /* Dual lane not supported for viper ports */ 10791 LOG_WARN(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 10792 "Invalid PortGroup port %d ; Dual lane not supported.\n"), port)); 10793 break; 10794 case PORTGROUP_QUAD_MODE: 10795 /* 2->4 cannot be allowed. 1->4 is possible */ 10796 if(old_num_lanes == 2) { 10797 LOG_WARN(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 10798 "Invalid PortGroup config for port %d ; BW exceeds Max port speed\n"), port)); 10799 } else { 10800 sb2_selected_port_details[loop_index].port_incr = 1; 10801 sb2_selected_port_details[loop_index].port_speed = 2500; 10802 sb2_selected_port_details[loop_index].port_type = GE_PORT; 10803 } 10804 break; 10805 default : return; /* Dummy statement */ 10806 } 10807 } else { 10808 /* Eagle ports */ 10809 port_incr = 2; 10810 if ((port == 27) || (port == 28)) { 10811 loop_index += 1; 10812 } 10813 10814 switch(num_lanes) { 10815 case PORTGROUP_SINGLE_MODE: 10816 if(sb2_selected_port_details[loop_index].port_type & GE_PORT) { 10817 LOG_WARN(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 10818 "Invalid PortGroup config for port %d ; BW exceeds Max port speed\n"), port)); 10819 break; 10820 } else if (SOC_PBMP_MEMBER(my_pbmp_xport_xe, port)) { 10821 sb2_selected_port_details[loop_index].port_type = XE_PORT; 10822 } else { 10823 sb2_selected_port_details[loop_index].port_type = HG_PORT; 10824 } 10825 sb2_selected_port_details[loop_index].port_speed = 10000; 10826 sb2_selected_port_details[loop_index].port_incr = 4; 10827 sb2_selected_port_details[loop_index].end_port_no = 28; 10828 sb2_selected_port_details[loop_index + 1].port_type = 0; 10829 port_incr = 4; /* All eagle ports are initialized */ 10830 break; 10831 case PORTGROUP_DUAL_MODE: 10832 sb2_selected_port_details[loop_index].port_type = XE_PORT; 10833 sb2_selected_port_details[loop_index].port_speed = 10000; 10834 sb2_selected_port_details[loop_index].port_incr = 2; 10835 sb2_selected_port_details[loop_index+1].port_type = XE_PORT; 10836 sb2_selected_port_details[loop_index+1].port_speed = 10000; 10837 sb2_selected_port_details[loop_index+1].port_incr = 2; 10838 port_incr = 4; /* All eagle ports are initialized */ 10839 break; 10840 case PORTGROUP_QUAD_MODE: 10841 /* In Eagle, 1->4 and 2->4 is not allowed */ 10842 LOG_WARN(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 10843 "Invalid PortGroup config for port %d\n"), port)); 10844 break; 10845 default : return; /* Dummy statement */ 10846 } 10847 } 10848 } 10849 } 10850 10851 /* Fill in pbmps */ 10852 loop_index=0; 10853 while(sb2_selected_port_details[loop_index].start_port_no != 0) { 10854 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 10855 "start:%d end:%d incr:%d type:%d speed:%d\n"), 10856 sb2_selected_port_details[loop_index].start_port_no, 10857 sb2_selected_port_details[loop_index].end_port_no, 10858 sb2_selected_port_details[loop_index].port_incr, 10859 sb2_selected_port_details[loop_index].port_type, 10860 sb2_selected_port_details[loop_index].port_speed)); 10861 10862 /* 10863 * Understanding eagle port details: 10864 * - N4 and 4xGE - port_incr = 1, 10865 * - N2 - port_incr = 2, 10866 * - N4s - 2 entries(25,27 and 26,28) each with port_incr = 2. 10867 */ 10868 for (port = sb2_selected_port_details[loop_index].start_port_no; 10869 port <= sb2_selected_port_details[loop_index].end_port_no; 10870 port += sb2_selected_port_details[loop_index].port_incr) { 10871 10872 port_speed = sb2_selected_port_details[loop_index].port_speed; 10873 if((dev_id == BCM56233_DEVICE_ID) && (port == 4)) { 10874 port_speed = 2500; 10875 } 10876 if((dev_id == BCM56233_DEVICE_ID) && 10877 (soc_property_get(unit, spn_SAT_ENABLE, 0) == 0) && 10878 (port == 5)) { 10879 /* In Dagger2, port 5 is hidden. Available only as SAT port */ 10880 sb2_selected_port_details[loop_index].port_type = 0; 10881 } 10882 10883 if (sb2_selected_port_details[loop_index].port_type == 0) { 10884 break; 10885 } 10886 10887 if(!SOC_WARM_BOOT(unit)) { 10888 if(port == 25) { 10889 if(sb2_selected_port_details[loop_index+1].port_type != 0) { 10890 /* There are 2 entries for eagle port. */ 10891 /* Refer : "Understanding eagle port details" above */ 10892 eagle_n4s_mode = 1; 10893 } else if(sb2_selected_port_details[loop_index].port_incr == 2) { 10894 /* Port incr = 2 and eagle has only one entry */ 10895 eagle_n2_mode = 1; 10896 } else if ((sb2_selected_port_details[loop_index].port_incr == 1) && 10897 (sb2_selected_port_details[loop_index].port_type & GE_PORT)) { 10898 /* Port incr = 1 and 4GE ports */ 10899 eagle_4ge_mode = 1; 10900 } 10901 } 10902 } 10903 10904 if ((port >=1) && (port <= 24)) { 10905 SOC_PBMP_PORT_ADD(*sb2_pbmp.pbmp_mxq, port); 10906 } else if (port >=25) { 10907 SOC_PBMP_PORT_ADD(*sb2_pbmp.pbmp_xl, port); 10908 } 10909 10910 if (sb2_selected_port_details[loop_index].port_type & GE_PORT) { 10911 SOC_PBMP_PORT_ADD(*sb2_pbmp.pbmp_xport_ge, port); 10912 switch(port_speed) { 10913 case 1000: 10914 if ((port >=1) && (port <= 24)) { 10915 SOC_PBMP_PORT_ADD(*sb2_pbmp.pbmp_mxq1g, port); 10916 } else { 10917 SOC_PBMP_PORT_ADD(*sb2_pbmp.pbmp_xl1g, port); 10918 } 10919 bcm56260_speed[unit][sb2_port_details_index][port-1] = 1000; 10920 break; 10921 case 2500: 10922 if ((port >=1) && (port <= 24)) { 10923 SOC_PBMP_PORT_ADD(*sb2_pbmp.pbmp_mxq2p5g, port); 10924 } else { 10925 SOC_PBMP_PORT_ADD(*sb2_pbmp.pbmp_xl2p5g, port); 10926 } 10927 bcm56260_speed[unit][sb2_port_details_index][port-1] = 2500; 10928 break; 10929 default: 10930 break; 10931 } 10932 } 10933 10934 if ((sb2_selected_port_details[loop_index].port_type & XE_PORT) || 10935 ((sb2_selected_port_details[loop_index].port_type & HG_PORT) && 10936 (SOC_PBMP_MEMBER(my_pbmp_xport_xe, port)))) { 10937 SOC_PBMP_PORT_ADD(*sb2_pbmp.pbmp_xport_xe, port); 10938 bcm56260_speed[unit][sb2_port_details_index][port-1] = 10000; 10939 if ((port >=1) && (port <= 24)) { 10940 SOC_PBMP_PORT_ADD(*sb2_pbmp.pbmp_mxq10g, port); 10941 } else { 10942 if (SOC_PBMP_MEMBER(my_pbmp_xport_ge, port)) { 10943 SOC_PBMP_PORT_ADD(*sb2_pbmp.pbmp_xl2p5g, port); 10944 SOC_PBMP_PORT_ADD(*sb2_pbmp.pbmp_xport_ge, port); 10945 SOC_PBMP_PORT_REMOVE(*sb2_pbmp.pbmp_xport_xe, port); 10946 } else if (port_speed == 2500) { 10947 SOC_PBMP_PORT_ADD(*sb2_pbmp.pbmp_xl2p5g, port); 10948 } else if (port_speed == 1000) { 10949 SOC_PBMP_PORT_ADD(*sb2_pbmp.pbmp_xl1g, port); 10950 } else { 10951 SOC_PBMP_PORT_ADD(*sb2_pbmp.pbmp_xl10g, port); 10952 } 10953 } 10954 } 10955 if ((sb2_selected_port_details[loop_index].port_type & HG_PORT) && 10956 (SOC_PBMP_MEMBER(my_pbmp_xport_ge, port))){ 10957 SOC_PBMP_PORT_ADD(*sb2_pbmp.pbmp_xl2p5g, port); 10958 SOC_PBMP_PORT_ADD(*sb2_pbmp.pbmp_xport_ge, port); 10959 SOC_PBMP_PORT_REMOVE(*sb2_pbmp.pbmp_xport_xe, port); 10960 } else { 10961 if (port >= 25) { 10962 SOC_PBMP_PORT_ADD(*sb2_pbmp.pbmp_xl10g, port); 10963 SOC_PBMP_PORT_ADD(*sb2_pbmp.pbmp_gport_stack, port); 10964 } 10965 } 10966 sb2_port_used_flags[port-1]=1; 10967 10968 } /* for port */ 10969 10970 10971 loop_index++; 10972 } /* while sb2_selected_port_details */ 10973 10974 /* Eagle port support 2.5G speed when pbmp_xport_ge is set 10975 * Prior to 1.4 version speed sync as 1G 10976 * But from 1.4 version sync function is fixed 10977 * To retrive properly for older to 1.4 version by using sb2_2p5g_ports 10978 * we are fixing the speed to 2.5G instead of 1G 10979 */ 10980 #ifdef BCM_WARM_BOOT_SUPPORT 10981 if (!(SOC_WARM_BOOT(unit))) { 10982 for(port = 25; port <= SB2_MAX_PHYSICAL_PORTS; ++port) { 10983 if (bcm56260_speed[unit][_sb2_config_id[unit]][port-1] >= 2500) { 10984 sb2_2p5g_ports[port-1] = 1; 10985 } 10986 } 10987 } 10988 #endif 10989 10990 for (port = 1; port < SB2_LPBK ; port++) { 10991 if (sb2_port_used_flags[port-1] == 0) { 10992 SOC_PBMP_PORT_REMOVE(*sb2_pbmp.pbmp_valid, port); 10993 } 10994 } 10995 10996 #if 1 10997 for (port = 29; port <= 31; port++) { 10998 SOC_PBMP_PORT_REMOVE(*sb2_pbmp.pbmp_valid, port); 10999 } 11000 #endif 11001 11002 for (port = 0; port < 96; port++) { 11003 SOC_PBMP_PORT_ADD(*sb2_pbmp.pbmp_pp, port); 11004 } 11005 } 11006 11007 void 11008 soc_saber2_subport_init(int unit) 11009 { 11010 soc_port_t port, lp_port, prev_port, pp_port; 11011 soc_pbmp_t pbmp_subport, pbmp_linkphy; 11012 soc_pbmp_t pbmp_linkphy_one_stream_per_subport; 11013 soc_info_t *si=&SOC_INFO(unit); 11014 int num_subport = 0, available_subport = 0; 11015 int available_lp_subport = 0; 11016 int port_subport_index_start = 0; 11017 int s1_xlp0_index = 0; 11018 11019 SOC_PBMP_CLEAR(pbmp_subport); 11020 SOC_PBMP_CLEAR(pbmp_linkphy); 11021 SOC_PBMP_CLEAR(pbmp_linkphy_one_stream_per_subport); 11022 SOC_PBMP_CLEAR(si->linkphy_pbm); 11023 SOC_PBMP_CLEAR(si->lp.bitmap); 11024 SOC_PBMP_CLEAR(si->linkphy_allowed_pbm); 11025 SOC_PBMP_CLEAR(si->subtag_pbm); 11026 SOC_PBMP_CLEAR(si->subtag_allowed_pbm); 11027 SOC_PBMP_CLEAR(si->subtag.bitmap); 11028 SOC_PBMP_CLEAR(si->linkphy_pp_port_pbm); 11029 SOC_PBMP_CLEAR(si->enabled_linkphy_pp_port_pbm); 11030 SOC_PBMP_CLEAR(si->subtag_pp_port_pbm); 11031 SOC_PBMP_CLEAR(si->enabled_subtag_pp_port_pbm); 11032 SOC_PBMP_CLEAR(si->general_pp_port_pbm); 11033 SOC_PBMP_CLEAR(si->enabled_general_pp_port_pbm); 11034 si->subtag_enabled = 0; 11035 si->linkphy_enabled = 0; 11036 11037 for (port = 1; port <= SB2_MAX_PHYSICAL_PORTS; port++) { 11038 si->port_num_subport[port] = 0; 11039 si->port_subport_base[port] = 0; 11040 si->port_linkphy_s1_base[port] = 0; 11041 } 11042 11043 pbmp_subport = soc_property_get_pbmp(unit, spn_PBMP_SUBPORT, 0); 11044 pbmp_linkphy = soc_property_get_pbmp(unit, spn_PBMP_LINKPHY, 0); 11045 pbmp_linkphy_one_stream_per_subport = 11046 soc_property_get_pbmp(unit, spn_PBMP_LINKPHY_ONE_STREAM_PER_SUBPORT, 0); 11047 11048 SOC_PBMP_ASSIGN(si->subtag_allowed_pbm, pbmp_subport); 11049 SOC_PBMP_ASSIGN(si->linkphy_allowed_pbm, pbmp_linkphy); 11050 11051 if (SOC_PBMP_NOT_NULL(pbmp_subport)) { 11052 /* All members of pbmp_linkphy should also be 11053 * member of pbmp_subport */ 11054 if (SOC_PBMP_NOT_NULL(pbmp_linkphy)) { 11055 /* Check if pbmp_linkphy members are valid for 11056 * supporting LinkPHY. 11057 */ 11058 SOC_PBMP_ITER(pbmp_linkphy, port) { 11059 if (!SOC_REG_PORT_VALID(unit, RXLP_PORT_ENABLEr, port)) { 11060 LOG_ERROR(BSL_LS_SOC_COMMON, (BSL_META_U(unit, "\nCONFIG ERROR\n" 11061 "pbmp_linkphy member port %d is invalid for " 11062 "LinkPHY support\n\n"), port)); 11063 SOC_PBMP_CLEAR(si->subtag_allowed_pbm); 11064 SOC_PBMP_CLEAR(si->linkphy_allowed_pbm); 11065 break; 11066 } 11067 SOC_PBMP_PORT_ADD(si->linkphy_allowed_pbm, port); 11068 } 11069 11070 SOC_PBMP_ITER(pbmp_linkphy, port) { 11071 if (!SOC_PBMP_MEMBER(pbmp_subport, port)) { 11072 LOG_ERROR(BSL_LS_SOC_COMMON, (BSL_META_U(unit, "\nCONFIG ERROR\n" 11073 "pbmp_linkphy member port %d is not member of " 11074 "pbmp_subport\n\n"), port)); 11075 SOC_PBMP_CLEAR(si->subtag_allowed_pbm); 11076 SOC_PBMP_CLEAR(si->linkphy_allowed_pbm); 11077 break; 11078 } 11079 SOC_PBMP_PORT_REMOVE(si->subtag_allowed_pbm, port); 11080 } 11081 } 11082 } else { 11083 if (SOC_PBMP_NOT_NULL(pbmp_linkphy)) { 11084 LOG_ERROR(BSL_LS_SOC_COMMON, (BSL_META_U(unit, "\nCONFIG ERROR\n" 11085 "config variable pbmp_linkphy should be sub-set of " 11086 "config variable pbmp_subport\n\n"))); 11087 } 11088 } 11089 11090 available_subport = SOC_SB2_MAX_SUBPORTS; 11091 available_lp_subport = SOC_SB2_MAX_LINKPHY_SUBPORTS; 11092 prev_port = 0; 11093 si->port_num_subport[prev_port] = 0; 11094 si->port_subport_base[prev_port] = SOC_SB2_MIN_SUBPORT_INDEX; 11095 11096 if (SOC_PBMP_NOT_NULL(si->linkphy_allowed_pbm)) { 11097 11098 /* Iterate through LinkPHY members first and reserve subport indices */ 11099 SOC_PBMP_ITER(si->linkphy_allowed_pbm, port) { 11100 if (port < SOC_MAX_NUM_PORTS) { 11101 num_subport = 11102 soc_property_port_get(unit, port, spn_NUM_SUBPORTS, 0); 11103 11104 if (num_subport > SOC_SB2_MAX_LINKPHY_SUBPORTS_PER_PORT) { 11105 num_subport = SOC_SB2_MAX_LINKPHY_SUBPORTS_PER_PORT; 11106 } 11107 11108 if (num_subport == 0) { 11109 LOG_ERROR(BSL_LS_SOC_COMMON, (BSL_META_U(unit, "\nCONFIG ERROR\n" 11110 "num_subports_%d should be non-zero for " 11111 "LinkPHY port %d\n\n"), port, port)); 11112 SOC_PBMP_PORT_REMOVE(si->linkphy_allowed_pbm, port); 11113 continue; 11114 } 11115 11116 if ((num_subport > available_subport) || 11117 (num_subport > available_lp_subport)) { 11118 LOG_ERROR(BSL_LS_SOC_COMMON, (BSL_META_U(unit, "\nCONFIG ERROR\n" 11119 "num_subports_%d=%d unavailable for LinkPHY port\n\n"), 11120 port, num_subport)); 11121 SOC_PBMP_PORT_REMOVE(si->linkphy_allowed_pbm, port); 11122 continue; 11123 } 11124 11125 port_subport_index_start = 11126 si->port_subport_base[prev_port] + 11127 si->port_num_subport[prev_port]; 11128 11129 si->port_subport_base[port] = port_subport_index_start; 11130 si->port_num_subport[port] = num_subport; 11131 si->port_linkphy_s1_base[port] = s1_xlp0_index; 11132 s1_xlp0_index += num_subport * 11133 (SOC_PBMP_MEMBER(pbmp_linkphy_one_stream_per_subport, port) ? 1 : 2); 11134 11135 available_subport -= num_subport; 11136 available_lp_subport -= num_subport; 11137 11138 prev_port = port; 11139 } 11140 } /* end SOC_PBMP_ITER(si->linkphy_allowed_pbm, port) */ 11141 } 11142 11143 prev_port = 0; 11144 if (SOC_PBMP_NOT_NULL(si->subtag_allowed_pbm)) { 11145 /* Iterate through SubTag ports and reserve subport indices */ 11146 SOC_PBMP_ITER(si->subtag_allowed_pbm, port) { 11147 num_subport = 11148 soc_property_port_get(unit, port, spn_NUM_SUBPORTS, 0); 11149 11150 if (num_subport == 0) { 11151 LOG_ERROR(BSL_LS_SOC_COMMON, (BSL_META_U(unit, "\nCONFIG ERROR\n" 11152 "num_subports_%d should be non-zero for SubTag port %d\n\n"), 11153 port, port)); 11154 SOC_PBMP_PORT_REMOVE(si->subtag_allowed_pbm, port); 11155 continue; 11156 } 11157 11158 if (num_subport > available_subport) { 11159 LOG_ERROR(BSL_LS_SOC_COMMON, (BSL_META_U(unit, "\nCONFIG ERROR\n" 11160 "num_subports_%d=%d unavailable for SubTag port\n\n"), 11161 port, num_subport)); 11162 SOC_PBMP_PORT_REMOVE(si->subtag_allowed_pbm, port); 11163 continue; 11164 } 11165 11166 port_subport_index_start = si->port_subport_base[prev_port] + 11167 si->port_num_subport[prev_port]; 11168 11169 /* Iterate the LinkPHY ports. 11170 * Skip the LinkPHY ports for which subports are allocated 11171 * until we get start index of required free subports 11172 * or reach end of LinkPHY ports. */ 11173 11174 SOC_PBMP_ITER(si->linkphy_allowed_pbm, lp_port) { 11175 if (lp_port < SOC_MAX_NUM_PORTS) { 11176 if (si->port_num_subport[lp_port]) { 11177 if (si->port_subport_base[lp_port] == 11178 port_subport_index_start) { 11179 /* skip the allocated LinkPHY ports */ 11180 port_subport_index_start = 11181 si->port_subport_base[lp_port] + 11182 si->port_num_subport[lp_port]; 11183 continue; 11184 } else if (si->port_subport_base[lp_port] > 11185 port_subport_index_start) { 11186 /* check if there is a big enough subport index 11187 * chunk unused, between 2 consecutive LinkPHY 11188 * enabled ports, to accomodate required subports */ 11189 if ((si->port_subport_base[lp_port] - 11190 port_subport_index_start) < num_subport) { 11191 /* skip the allocated LinkPHY ports */ 11192 port_subport_index_start = 11193 si->port_subport_base[lp_port] 11194 + si->port_num_subport[lp_port]; 11195 continue; 11196 } 11197 } 11198 } 11199 } 11200 } 11201 11202 if (port < SOC_MAX_NUM_PORTS) { 11203 si->port_subport_base[port] = port_subport_index_start; 11204 si->port_num_subport[port] = num_subport; 11205 11206 available_subport -= num_subport; 11207 prev_port = port; 11208 } 11209 } /* end SOC_PBMP_ITER(si->subtag_allowed_pbm, port) */ 11210 } 11211 11212 /* populate LinkPHY pp_port bitmap */ 11213 SOC_PBMP_ITER(si->linkphy_allowed_pbm, port) { 11214 if (port < SOC_MAX_NUM_PORTS) { 11215 for (pp_port = 0; pp_port < si->port_num_subport[port]; pp_port++) { 11216 SOC_PBMP_PORT_ADD(si->linkphy_pp_port_pbm, 11217 pp_port + si->port_subport_base[port]); 11218 /* Set this port in the enabled bmap by default at init */ 11219 SOC_PBMP_PORT_ADD(si->enabled_linkphy_pp_port_pbm, 11220 pp_port + si->port_subport_base[port]); 11221 } 11222 } 11223 } 11224 11225 /* populate SubTag pp_port bitmap */ 11226 SOC_PBMP_ITER(si->subtag_allowed_pbm, port) { 11227 if (port < SOC_MAX_NUM_PORTS) { 11228 for (pp_port = 0; pp_port < si->port_num_subport[port]; pp_port++) { 11229 SOC_PBMP_PORT_ADD(si->subtag_pp_port_pbm, 11230 pp_port + si->port_subport_base[port]); 11231 /* Set this port in the enabled bmap by default at init */ 11232 SOC_PBMP_PORT_ADD(si->enabled_subtag_pp_port_pbm, 11233 pp_port + si->port_subport_base[port]); 11234 } 11235 } 11236 } 11237 if (SOC_PBMP_NOT_NULL (si->subtag_pp_port_pbm)) { 11238 si->subtag_enabled = 1; 11239 } 11240 if (SOC_PBMP_NOT_NULL (si->linkphy_pp_port_pbm)) { 11241 si->linkphy_enabled = 1; 11242 } 11243 11244 /* Update General Purpose pp port bitmap */ 11245 if (soc_feature(unit, soc_feature_general_cascade)) { 11246 for (pp_port = 0; pp_port < SOC_SB2_MAX_SUBPORTS; pp_port++) { 11247 if (SOC_PBMP_MEMBER(si->subtag_pp_port_pbm, 11248 (pp_port + SOC_SB2_MIN_SUBPORT_INDEX))) { 11249 continue; 11250 } 11251 if (SOC_PBMP_MEMBER(si->linkphy_pp_port_pbm, 11252 (pp_port + SOC_SB2_MIN_SUBPORT_INDEX))) { 11253 continue; 11254 } 11255 SOC_PBMP_PORT_ADD(si->general_pp_port_pbm, 11256 (pp_port + SOC_SB2_MIN_SUBPORT_INDEX)); 11257 } 11258 } 11259 11260 /* Initialize the number of modules */ 11261 si->num_coe_modules = soc_property_get(unit, spn_MODULE_NUM_MODIDS, 1); 11262 11263 /* Check if the num_mods exceeds max allowed, if so flag an error, 11264 note that the default of '1' is reserved for front-panel physical 11265 ports */ 11266 if(si->num_coe_modules > (SOC_SB2_MAX_COE_MODULES + 1)) { 11267 LOG_WARN(BSL_LS_SOC_COMMON, 11268 (BSL_META_U(unit, 11269 "\nCONFIG ERROR\n" 11270 "Number of modules %d exceeds maximum: %d," 11271 "setting to max \n\n"), 11272 si->num_coe_modules, SOC_SB2_MAX_COE_MODULES)); 11273 si->num_coe_modules = SOC_SB2_MAX_COE_MODULES; 11274 } 11275 11276 /* If it is a non default value, note that we are in a 11277 'coe-stacking-mode', wherein we will be supporing stacking for CoE */ 11278 if(si->num_coe_modules != 1) { 11279 si->coe_stacking_mode = 1; 11280 /* Since the first module is reserved for physical-ports, reduce the 11281 num_coe_modules by 1 */ 11282 si->num_coe_modules--; 11283 } 11284 11285 } 11286 11287 int 11288 soc_sb2_cosq_min_clear (int unit, int port, 11289 int index, uint32 level) 11290 { 11291 lls_l0_shaper_config_c_entry_t l0_entry; 11292 lls_l1_shaper_config_c_entry_t l1_entry; 11293 lls_l2_shaper_config_lower_entry_t l2_entry; 11294 int idx; 11295 11296 static const soc_field_t rate_exp_fields[] = { 11297 C_MIN_REF_RATE_EXP_0f, C_MIN_REF_RATE_EXP_1f, 11298 C_MIN_REF_RATE_EXP_2f, C_MIN_REF_RATE_EXP_3f 11299 }; 11300 static const soc_field_t rate_mant_fields[] = { 11301 C_MIN_REF_RATE_MANT_0f, C_MIN_REF_RATE_MANT_1f, 11302 C_MIN_REF_RATE_MANT_2f, C_MIN_REF_RATE_MANT_3f 11303 }; 11304 int l2_queues = -1; 11305 int l2_shaper_bucket = -1; 11306 11307 l2_queues = soc_mem_index_count(unit,LLS_L2_PARENTm); 11308 l2_shaper_bucket = l2_queues / 11309 soc_mem_index_count(unit, 11310 LLS_L2_SHAPER_CONFIG_Cm); 11311 11312 switch(level){ 11313 case _SOC_KT2_COSQ_NODE_LVL_L0: 11314 sal_memset(&l0_entry, 0, 11315 sizeof(lls_l0_shaper_config_c_entry_t)); 11316 SOC_IF_ERROR_RETURN 11317 (soc_mem_read(unit, LLS_L0_MIN_CONFIG_Cm, MEM_BLOCK_ALL, 11318 index, &l0_entry)); 11319 soc_mem_field32_set(unit, LLS_L0_MIN_CONFIG_Cm , &l0_entry, 11320 C_MIN_REF_RATE_EXPf, 0); 11321 soc_mem_field32_set(unit, LLS_L0_MIN_CONFIG_Cm, &l0_entry, 11322 C_MIN_REF_RATE_MANTf, 0); 11323 SOC_IF_ERROR_RETURN 11324 (soc_mem_write(unit, LLS_L0_MIN_CONFIG_Cm, 11325 MEM_BLOCK_ALL, index, &l0_entry)); 11326 break; 11327 case _SOC_KT2_COSQ_NODE_LVL_L1: 11328 sal_memset(&l1_entry, 0, 11329 sizeof(lls_l1_shaper_config_c_entry_t)); 11330 SOC_IF_ERROR_RETURN 11331 (soc_mem_read(unit, LLS_L1_MIN_CONFIG_Cm, MEM_BLOCK_ALL, 11332 index, &l1_entry)); 11333 soc_mem_field32_set(unit, LLS_L1_MIN_CONFIG_Cm, &l1_entry, 11334 C_MIN_REF_RATE_EXPf, 0); 11335 soc_mem_field32_set(unit, LLS_L1_MIN_CONFIG_Cm, &l1_entry, 11336 C_MIN_REF_RATE_MANTf,0); 11337 SOC_IF_ERROR_RETURN 11338 (soc_mem_write(unit, LLS_L1_MIN_CONFIG_Cm, 11339 MEM_BLOCK_ALL, index, &l1_entry)); 11340 break; 11341 case _SOC_KT2_COSQ_NODE_LVL_L2: 11342 idx = (index % 4); 11343 sal_memset(&l2_entry, 0, 11344 sizeof(lls_l2_shaper_config_lower_entry_t)); 11345 SOC_IF_ERROR_RETURN 11346 (soc_mem_read(unit, LLS_L2_MIN_CONFIG_Cm, MEM_BLOCK_ALL, 11347 index/l2_shaper_bucket, &l2_entry)); 11348 soc_mem_field32_set(unit, LLS_L2_MIN_CONFIG_Cm, &l2_entry, 11349 rate_exp_fields[idx], 0); 11350 soc_mem_field32_set(unit, LLS_L2_MIN_CONFIG_Cm, &l2_entry, 11351 rate_mant_fields[idx], 0); 11352 SOC_IF_ERROR_RETURN 11353 (soc_mem_write(unit, LLS_L2_MIN_CONFIG_Cm, 11354 MEM_BLOCK_ALL, index/l2_shaper_bucket, &l2_entry)); 11355 break; 11356 11357 default: 11358 break; 11359 } 11360 return SOC_E_NONE; 11361 } 11362 11363 int 11364 soc_sb2_cosq_min_bucket_get(int unit, int port, int index, int level, 11365 uint32 *min_quantum, uint32 *mantissa, 11366 uint32 *exp, uint32 *cycle) 11367 { 11368 int rv; 11369 uint32 idx = 0; 11370 uint32 i = 0; 11371 lls_l0_shaper_config_c_entry_t l0_entry; 11372 lls_l1_shaper_config_c_entry_t l1_entry; 11373 lls_l2_shaper_config_lower_entry_t l2_entry; 11374 soc_mem_t config_mem[2]; 11375 uint32 rate_exp[2], rate_mantissa[2]; 11376 uint32 cycle_sel[2]; 11377 11378 soc_field_t rate_exp_fields[] = { 11379 C_MAX_REF_RATE_EXP_0f, C_MAX_REF_RATE_EXP_1f, 11380 C_MAX_REF_RATE_EXP_2f, C_MAX_REF_RATE_EXP_3f, 11381 C_MIN_REF_RATE_EXP_0f, C_MIN_REF_RATE_EXP_1f, 11382 C_MIN_REF_RATE_EXP_2f, C_MIN_REF_RATE_EXP_3f 11383 }; 11384 soc_field_t rate_mant_fields[] = { 11385 C_MAX_REF_RATE_MANT_0f, C_MAX_REF_RATE_MANT_1f, 11386 C_MAX_REF_RATE_MANT_2f, C_MAX_REF_RATE_MANT_3f, 11387 C_MIN_REF_RATE_MANT_0f, C_MIN_REF_RATE_MANT_1f, 11388 C_MIN_REF_RATE_MANT_2f, C_MIN_REF_RATE_MANT_3f 11389 }; 11390 soc_field_t cycle_sel_fields[] = { 11391 C_MAX_CYCLE_SEL_0f, C_MAX_CYCLE_SEL_1f, 11392 C_MAX_CYCLE_SEL_2f, C_MAX_CYCLE_SEL_3f, 11393 C_MIN_CYCLE_SEL_0f, C_MIN_CYCLE_SEL_1f, 11394 C_MIN_CYCLE_SEL_2f, C_MIN_CYCLE_SEL_3f 11395 }; 11396 11397 soc_field_t rate_exp_f[] = { 11398 C_MAX_REF_RATE_EXPf, C_MIN_REF_RATE_EXPf 11399 }; 11400 soc_field_t rate_mant_f[] = { 11401 C_MAX_REF_RATE_MANTf, C_MIN_REF_RATE_MANTf 11402 }; 11403 soc_field_t cycle_sel_f[] = { 11404 C_MAX_CYCLE_SELf, C_MIN_CYCLE_SELf 11405 }; 11406 int shaper_bucket_index = 0 ; 11407 int max_l1_shaper_bucket = 0; 11408 int max_l2_shaper_bucket = 0 ; 11409 11410 switch (level) { 11411 11412 case _SOC_KT2_COSQ_NODE_LVL_L0: 11413 config_mem[0] = LLS_L0_SHAPER_CONFIG_Cm; 11414 config_mem[1] = LLS_L0_MIN_CONFIG_Cm; 11415 11416 for (i = 1; i < 2; i++) { 11417 SOC_IF_ERROR_RETURN 11418 (soc_mem_read(unit, config_mem[i], MEM_BLOCK_ALL, 11419 index, &l0_entry)); 11420 rate_exp[i] = soc_mem_field32_get(unit, config_mem[i], 11421 &l0_entry, 11422 rate_exp_f[i]); 11423 rate_mantissa[i] = soc_mem_field32_get(unit, config_mem[i], 11424 &l0_entry, 11425 rate_mant_f[i]); 11426 cycle_sel[i] = soc_mem_field32_get(unit, config_mem[i], &l0_entry, 11427 cycle_sel_f[i]); 11428 } 11429 break; 11430 11431 case _SOC_KT2_COSQ_NODE_LVL_L1: 11432 config_mem[0] = LLS_L1_SHAPER_CONFIG_Cm; 11433 config_mem[1] = LLS_L1_MIN_CONFIG_Cm; 11434 max_l1_shaper_bucket = soc_mem_index_count(unit,LLS_L1_PARENTm) / 11435 soc_mem_index_count(unit, 11436 LLS_L1_SHAPER_CONFIG_Cm); 11437 11438 shaper_bucket_index = index % max_l1_shaper_bucket; 11439 for (i = 1; i < 2; i++) { 11440 idx = (i * 4) + shaper_bucket_index; 11441 SOC_IF_ERROR_RETURN 11442 (soc_mem_read(unit, config_mem[i], MEM_BLOCK_ALL, 11443 index / max_l1_shaper_bucket, &l1_entry)); 11444 rate_exp[i] = soc_mem_field32_get(unit, config_mem[i], 11445 &l1_entry, 11446 rate_exp_fields[idx]); 11447 rate_mantissa[i] = soc_mem_field32_get(unit, config_mem[i], 11448 &l1_entry, 11449 rate_mant_fields[idx]); 11450 cycle_sel[i] = soc_mem_field32_get(unit, config_mem[i], &l1_entry, 11451 cycle_sel_f[i]); 11452 } 11453 break; 11454 11455 case _SOC_KT2_COSQ_NODE_LVL_L2: 11456 11457 config_mem[0] = LLS_L2_SHAPER_CONFIG_Cm; 11458 config_mem[1] = LLS_L2_MIN_CONFIG_Cm; 11459 max_l2_shaper_bucket = soc_mem_index_count(unit,LLS_L2_PARENTm)/ 11460 soc_mem_index_count(unit, LLS_L2_SHAPER_CONFIG_Cm); 11461 for (i = 1; i < 2; i++) { 11462 idx = (i * 4) + (index % 4); 11463 SOC_IF_ERROR_RETURN 11464 (soc_mem_read(unit, config_mem[i], MEM_BLOCK_ALL, 11465 index/max_l2_shaper_bucket, &l2_entry)); 11466 rate_exp[i] = soc_mem_field32_get(unit, config_mem[i], 11467 &l2_entry, 11468 rate_exp_fields[idx]); 11469 rate_mantissa[i] = soc_mem_field32_get(unit, config_mem[i], 11470 &l2_entry, 11471 rate_mant_fields[idx]); 11472 cycle_sel[i] = soc_mem_field32_get(unit, config_mem[i], &l2_entry, 11473 cycle_sel_fields[idx]); 11474 } 11475 break; 11476 11477 case _SOC_KT2_COSQ_NODE_LVL_S0: 11478 case _SOC_KT2_COSQ_NODE_LVL_S1: 11479 case _SOC_KT2_COSQ_NODE_LVL_ROOT: 11480 return SOC_E_INTERNAL; 11481 default: 11482 return SOC_E_INTERNAL; 11483 } 11484 11485 11486 rv = soc_katana_compute_shaper_rate(unit, rate_mantissa[1], rate_exp[1], 11487 min_quantum); 11488 if(!rv) 11489 { 11490 return rv; 11491 } 11492 *mantissa = rate_mantissa[1]; 11493 *exp = rate_exp[1]; 11494 *cycle = cycle_sel[1]; 11495 11496 return SOC_E_NONE; 11497 11498 } 11499 11500 11501 int 11502 soc_sb2_cosq_max_bucket_set(int unit, int port, 11503 int index, uint32 level) 11504 { 11505 uint32 idx = 0; 11506 uint32 i = 0; 11507 lls_port_shaper_config_c_entry_t port_entry; 11508 lls_l0_shaper_config_c_entry_t l0_entry; 11509 lls_l1_shaper_config_c_entry_t l1_entry; 11510 lls_l2_shaper_config_lower_entry_t l2_entry; 11511 soc_mem_t config_mem[2]; 11512 lls_s0_shaper_config_c_entry_t s0_entry; 11513 soc_field_t rate_exp_fields[] = { 11514 C_MAX_REF_RATE_EXP_0f, C_MAX_REF_RATE_EXP_1f, 11515 C_MAX_REF_RATE_EXP_2f, C_MAX_REF_RATE_EXP_3f, 11516 C_MIN_REF_RATE_EXP_0f, C_MIN_REF_RATE_EXP_1f, 11517 C_MIN_REF_RATE_EXP_2f, C_MIN_REF_RATE_EXP_3f 11518 }; 11519 soc_field_t rate_mant_fields[] = { 11520 C_MAX_REF_RATE_MANT_0f, C_MAX_REF_RATE_MANT_1f, 11521 C_MAX_REF_RATE_MANT_2f, C_MAX_REF_RATE_MANT_3f, 11522 C_MIN_REF_RATE_MANT_0f, C_MIN_REF_RATE_MANT_1f, 11523 C_MIN_REF_RATE_MANT_2f, C_MIN_REF_RATE_MANT_3f 11524 }; 11525 soc_field_t burst_exp_fields[] = { 11526 C_MAX_THLD_EXP_0f, C_MAX_THLD_EXP_1f, 11527 C_MAX_THLD_EXP_2f, C_MAX_THLD_EXP_3f, 11528 C_MIN_THLD_EXP_0f, C_MIN_THLD_EXP_1f, 11529 C_MIN_THLD_EXP_2f, C_MIN_THLD_EXP_3f 11530 }; 11531 soc_field_t burst_mant_fields[] = { 11532 C_MAX_THLD_MANT_0f, C_MAX_THLD_MANT_1f, 11533 C_MAX_THLD_MANT_2f, C_MAX_THLD_MANT_3f, 11534 C_MIN_THLD_MANT_0f, C_MIN_THLD_MANT_1f, 11535 C_MIN_THLD_MANT_2f, C_MIN_THLD_MANT_3f 11536 }; 11537 soc_field_t cycle_sel_fields[] = { 11538 C_MAX_CYCLE_SEL_0f, C_MAX_CYCLE_SEL_1f, 11539 C_MAX_CYCLE_SEL_2f, C_MAX_CYCLE_SEL_3f, 11540 C_MIN_CYCLE_SEL_0f, C_MIN_CYCLE_SEL_1f, 11541 C_MIN_CYCLE_SEL_2f, C_MIN_CYCLE_SEL_3f 11542 }; 11543 11544 soc_field_t rate_exp_f[] = { 11545 C_MAX_REF_RATE_EXPf, C_MIN_REF_RATE_EXPf 11546 }; 11547 soc_field_t rate_mant_f[] = { 11548 C_MAX_REF_RATE_MANTf, C_MIN_REF_RATE_MANTf 11549 }; 11550 soc_field_t burst_exp_f[] = { 11551 C_MAX_THLD_EXPf, C_MIN_THLD_EXPf 11552 }; 11553 soc_field_t burst_mant_f[] = { 11554 C_MAX_THLD_MANTf, C_MIN_THLD_MANTf 11555 }; 11556 soc_field_t cycle_sel_f[] = { 11557 C_MAX_CYCLE_SELf, C_MIN_CYCLE_SELf 11558 }; 11559 int l2_queues = -1; 11560 int l2_shaper_bucket = -1; 11561 11562 l2_queues = soc_mem_index_count(unit,LLS_L2_PARENTm); 11563 l2_shaper_bucket = l2_queues / 11564 soc_mem_index_count(unit, 11565 LLS_L2_SHAPER_CONFIG_Cm); 11566 11567 /* set Min/Max threshold shapers to 33Gbps */ 11568 switch (level) { 11569 case _SOC_KT2_COSQ_NODE_LVL_ROOT: 11570 config_mem[0] = LLS_PORT_SHAPER_CONFIG_Cm; 11571 11572 sal_memset(&port_entry, 0, 11573 sizeof(lls_port_shaper_config_c_entry_t)); 11574 SOC_IF_ERROR_RETURN 11575 (soc_mem_read(unit, config_mem[0], MEM_BLOCK_ALL, 11576 index, &port_entry)); 11577 soc_mem_field32_set(unit, config_mem[0], &port_entry, 11578 rate_exp_f[0], 11579 SB2_QUEUE_FLUSH_RATE_EXP); 11580 soc_mem_field32_set(unit, config_mem[0], &port_entry, 11581 rate_mant_f[0], 11582 SB2_QUEUE_FLUSH_RATE_MANTISSA); 11583 soc_mem_field32_set(unit, config_mem[0], &port_entry, 11584 burst_exp_f[0], 11585 SB2_QUEUE_FLUSH_BURST_EXP); 11586 soc_mem_field32_set(unit, config_mem[0], &port_entry, 11587 burst_mant_f[0], 11588 SB2_QUEUE_FLUSH_BURST_MANTISSA); 11589 soc_mem_field32_set(unit, config_mem[0], &port_entry, 11590 cycle_sel_f[0], 11591 SB2_QUEUE_FLUSH_CYCLE_SEL); 11592 SOC_IF_ERROR_RETURN 11593 (soc_mem_write(unit, config_mem[0], 11594 MEM_BLOCK_ALL, index, &port_entry)); 11595 break; 11596 case _SOC_KT2_COSQ_NODE_LVL_S0: 11597 case _SOC_KT2_COSQ_NODE_LVL_S1: 11598 config_mem[0] = (level ==_SOC_KT2_COSQ_NODE_LVL_S0) ? 11599 LLS_S0_SHAPER_CONFIG_Cm : 11600 LLS_S1_SHAPER_CONFIG_Cm; 11601 SOC_IF_ERROR_RETURN 11602 (soc_mem_read(unit, config_mem[0], MEM_BLOCK_ALL, 11603 index, &s0_entry)); 11604 soc_mem_field32_set(unit, config_mem[0], &s0_entry, 11605 rate_exp_f[0], SB2_QUEUE_FLUSH_RATE_EXP); 11606 soc_mem_field32_set(unit, config_mem[0], &s0_entry, 11607 rate_mant_f[0], SB2_QUEUE_FLUSH_RATE_MANTISSA); 11608 soc_mem_field32_set(unit, config_mem[0], &s0_entry, 11609 burst_exp_f[0], SB2_QUEUE_FLUSH_BURST_EXP); 11610 soc_mem_field32_set(unit, config_mem[0], &s0_entry, 11611 burst_mant_f[0], SB2_QUEUE_FLUSH_BURST_MANTISSA); 11612 soc_mem_field32_set(unit, config_mem[0], &s0_entry, 11613 cycle_sel_f[0], SB2_QUEUE_FLUSH_CYCLE_SEL); 11614 SOC_IF_ERROR_RETURN 11615 (soc_mem_write(unit, config_mem[0], 11616 MEM_BLOCK_ALL, index, &s0_entry)); 11617 break; 11618 case _SOC_KT2_COSQ_NODE_LVL_L0: 11619 config_mem[0] = LLS_L0_SHAPER_CONFIG_Cm; 11620 config_mem[1] = LLS_L0_MIN_CONFIG_Cm; 11621 11622 for (i = 0; i < 2; i++) { 11623 sal_memset(&l0_entry, 0, 11624 sizeof(lls_l0_shaper_config_c_entry_t)); 11625 SOC_IF_ERROR_RETURN 11626 (soc_mem_read(unit, config_mem[i], MEM_BLOCK_ALL, 11627 index, &l0_entry)); 11628 soc_mem_field32_set(unit, config_mem[i], &l0_entry, 11629 rate_exp_f[i], 11630 SB2_QUEUE_FLUSH_RATE_EXP); 11631 soc_mem_field32_set(unit, config_mem[i], &l0_entry, 11632 rate_mant_f[i], 11633 SB2_QUEUE_FLUSH_RATE_MANTISSA); 11634 soc_mem_field32_set(unit, config_mem[i], &l0_entry, 11635 burst_exp_f[i], 11636 SB2_QUEUE_FLUSH_BURST_EXP); 11637 soc_mem_field32_set(unit, config_mem[i], &l0_entry, 11638 burst_mant_f[i], 11639 SB2_QUEUE_FLUSH_BURST_MANTISSA); 11640 soc_mem_field32_set(unit, config_mem[i], &l0_entry, 11641 cycle_sel_f[i], 11642 SB2_QUEUE_FLUSH_CYCLE_SEL); 11643 SOC_IF_ERROR_RETURN 11644 (soc_mem_write(unit, config_mem[i], 11645 MEM_BLOCK_ALL, index, &l0_entry)); 11646 } 11647 break; 11648 case _SOC_KT2_COSQ_NODE_LVL_L1: 11649 config_mem[0] = LLS_L1_SHAPER_CONFIG_Cm; 11650 config_mem[1] = LLS_L1_MIN_CONFIG_Cm; 11651 11652 for (i = 0; i < 2; i++) { 11653 sal_memset(&l1_entry, 0, 11654 sizeof(lls_l1_shaper_config_c_entry_t)); 11655 SOC_IF_ERROR_RETURN 11656 (soc_mem_read(unit, config_mem[i], MEM_BLOCK_ALL, 11657 index, &l1_entry)); 11658 soc_mem_field32_set(unit, config_mem[i], &l1_entry, 11659 rate_exp_f[i], 11660 SB2_QUEUE_FLUSH_RATE_EXP); 11661 soc_mem_field32_set(unit, config_mem[i], &l1_entry, 11662 rate_mant_f[i], 11663 SB2_QUEUE_FLUSH_RATE_MANTISSA); 11664 soc_mem_field32_set(unit, config_mem[i], &l1_entry, 11665 burst_exp_f[i], 11666 SB2_QUEUE_FLUSH_BURST_EXP); 11667 soc_mem_field32_set(unit, config_mem[i], &l1_entry, 11668 burst_mant_f[i], 11669 SB2_QUEUE_FLUSH_BURST_MANTISSA); 11670 soc_mem_field32_set(unit, config_mem[i], &l1_entry, 11671 cycle_sel_f[i], 11672 SB2_QUEUE_FLUSH_CYCLE_SEL); 11673 SOC_IF_ERROR_RETURN 11674 (soc_mem_write(unit, config_mem[i], 11675 MEM_BLOCK_ALL, 11676 index, &l1_entry)); 11677 } 11678 break; 11679 case _SOC_KT2_COSQ_NODE_LVL_L2: 11680 config_mem[0] = LLS_L2_SHAPER_CONFIG_Cm; 11681 config_mem[1] = LLS_L2_MIN_CONFIG_Cm; 11682 11683 for ( i = 0; i < 2; i++) { 11684 idx = (i * 4) + (index % 4); 11685 11686 sal_memset(&l2_entry, 0, 11687 sizeof(lls_l2_shaper_config_lower_entry_t)); 11688 SOC_IF_ERROR_RETURN 11689 (soc_mem_read(unit, config_mem[i], MEM_BLOCK_ALL, 11690 index/l2_shaper_bucket, &l2_entry)); 11691 soc_mem_field32_set(unit, config_mem[i], &l2_entry, 11692 rate_exp_fields[idx], 11693 SB2_QUEUE_FLUSH_RATE_EXP); 11694 soc_mem_field32_set(unit, config_mem[i], &l2_entry, 11695 rate_mant_fields[idx], 11696 SB2_QUEUE_FLUSH_RATE_MANTISSA); 11697 soc_mem_field32_set(unit, config_mem[i], &l2_entry, 11698 burst_exp_fields[idx], 11699 SB2_QUEUE_FLUSH_BURST_EXP); 11700 soc_mem_field32_set(unit, config_mem[i], &l2_entry, 11701 burst_mant_fields[idx], 11702 SB2_QUEUE_FLUSH_BURST_MANTISSA); 11703 soc_mem_field32_set(unit, config_mem[i], &l2_entry, 11704 cycle_sel_fields[idx], 11705 SB2_QUEUE_FLUSH_CYCLE_SEL); 11706 SOC_IF_ERROR_RETURN 11707 (soc_mem_write(unit, config_mem[i], 11708 MEM_BLOCK_ALL, 11709 index/l2_shaper_bucket, &l2_entry)); 11710 } 11711 break; 11712 default: 11713 return SOC_E_NONE; 11714 } 11715 11716 return SOC_E_NONE; 11717 11718 } 11719 11720 STATIC int 11721 _soc_sb2_mmu_config_shared_update_check(int unit, int val1, int val2, int flags) 11722 { 11723 int rv = 0; 11724 if (flags == 1) { 11725 if (val1 > val2) { 11726 rv = 1; 11727 } 11728 } else { 11729 if (val1 < val2) { 11730 rv = 1; 11731 } 11732 } 11733 return rv; 11734 } 11735 11736 int 11737 soc_sb2_mmu_config_shared_buf_recalc(int unit, int shared_size, 11738 bcm_kt2_cosq_recalc_type_t recalc_type) 11739 { 11740 soc_info_t *si= &SOC_INFO(unit); 11741 soc_pbmp_t valid_port_cpu_pbmp; 11742 soc_port_t port=0; 11743 uint32 temp_val; 11744 uint32 rval=0; 11745 uint32 op_node=0; 11746 uint32 op_node_offset=0; 11747 uint32 cos; 11748 int cur_limit, resume_limit, flags; 11749 uint32 ext_mem_type; 11750 11751 mmu_thdo_opnconfig_cell_entry_t mmu_thdo_opnconfig_cell_entry={{0}}; 11752 11753 ext_mem_type = ((recalc_type == BCM_KT2_RECALC_SHARED_EXT_DECREMENT) || 11754 (recalc_type == BCM_KT2_RECALC_SHARED_EXT_INCREMENT)) ? 1 : 0; 11755 11756 flags = ((recalc_type == BCM_KT2_RECALC_SHARED_INT_DECREMENT) || 11757 (recalc_type == BCM_KT2_RECALC_SHARED_EXT_DECREMENT)) ? 1 : 0; 11758 11759 if ((recalc_type == BCM_KT2_RECALC_SHARED_EXT_DECREMENT) || 11760 (recalc_type == BCM_KT2_RECALC_SHARED_EXT_INCREMENT)) { 11761 11762 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_SHARED_LIMIT_CELLE_POOL0r ( 11763 unit, &rval)); 11764 cur_limit = soc_reg_field_get(unit, OP_BUFFER_SHARED_LIMIT_CELLE_POOL0r, rval, 11765 OP_BUFFER_SHARED_LIMIT_CELLEf); 11766 if (_soc_sb2_mmu_config_shared_update_check(unit, cur_limit, shared_size, flags)) { 11767 if (recalc_type == BCM_KT2_RECALC_SHARED_EXT_DECREMENT) { 11768 temp_val = cur_limit - shared_size; 11769 } else { 11770 temp_val = shared_size - cur_limit; 11771 } 11772 soc_reg_field_set(unit, OP_BUFFER_SHARED_LIMIT_CELLE_POOL0r, &rval, 11773 OP_BUFFER_SHARED_LIMIT_CELLEf, shared_size); 11774 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_SHARED_LIMIT_CELLE_POOL0r ( 11775 unit, rval)); 11776 11777 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_SHARED_LIMIT_RESUME_CELLE_POOL0r( 11778 unit, &rval)); 11779 cur_limit = soc_reg_field_get(unit, OP_BUFFER_SHARED_LIMIT_RESUME_CELLE_POOL0r, 11780 rval,OP_BUFFER_SHARED_LIMIT_RESUME_CELLEf); 11781 if (recalc_type == BCM_KT2_RECALC_SHARED_EXT_DECREMENT) { 11782 resume_limit = cur_limit - temp_val; 11783 if (resume_limit < 0) { 11784 LOG_ERROR(BSL_LS_SOC_COMMON, (BSL_META_U(unit, "\nGlobal external" 11785 " shared buffer exhausted"))); 11786 return SOC_E_RESOURCE; 11787 } 11788 } else { 11789 resume_limit = cur_limit + temp_val; 11790 } 11791 11792 soc_reg_field_set(unit, OP_BUFFER_SHARED_LIMIT_RESUME_CELLE_POOL0r, 11793 &rval,OP_BUFFER_SHARED_LIMIT_RESUME_CELLEf, resume_limit); 11794 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_SHARED_LIMIT_RESUME_CELLE_POOL0r( 11795 unit, rval)); 11796 } 11797 } else { 11798 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_SHARED_LIMIT_CELLIr (unit, &rval)); 11799 cur_limit = soc_reg_field_get(unit, OP_BUFFER_SHARED_LIMIT_CELLIr, rval, 11800 OP_BUFFER_SHARED_LIMIT_CELLIf); 11801 if (_soc_sb2_mmu_config_shared_update_check(unit, cur_limit, shared_size, flags)) { 11802 if (recalc_type == BCM_KT2_RECALC_SHARED_INT_DECREMENT) { 11803 temp_val = cur_limit - shared_size; 11804 } else { 11805 temp_val = shared_size - cur_limit; 11806 } 11807 soc_reg_field_set(unit, OP_BUFFER_SHARED_LIMIT_CELLIr, &rval, 11808 OP_BUFFER_SHARED_LIMIT_CELLIf, shared_size); 11809 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_SHARED_LIMIT_CELLIr (unit, rval)); 11810 11811 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_SHARED_LIMIT_RESUME_CELLIr(unit, &rval)); 11812 cur_limit = soc_reg_field_get(unit, OP_BUFFER_SHARED_LIMIT_RESUME_CELLIr, rval, 11813 OP_BUFFER_SHARED_LIMIT_RESUME_CELLIf); 11814 if (recalc_type == BCM_KT2_RECALC_SHARED_INT_DECREMENT) { 11815 resume_limit = cur_limit - temp_val; 11816 if (resume_limit < 0) { 11817 LOG_ERROR(BSL_LS_SOC_COMMON, (BSL_META_U(unit, "\nGlobal internal" 11818 " shared buffer exhausted"))); 11819 return SOC_E_RESOURCE; 11820 } 11821 } else { 11822 resume_limit = cur_limit + temp_val; 11823 } 11824 11825 soc_reg_field_set(unit, OP_BUFFER_SHARED_LIMIT_RESUME_CELLIr, &rval, 11826 OP_BUFFER_SHARED_LIMIT_RESUME_CELLIf, resume_limit); 11827 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_SHARED_LIMIT_RESUME_CELLIr(unit, rval)); 11828 } 11829 } 11830 11831 SOC_PBMP_CLEAR (valid_port_cpu_pbmp); 11832 SOC_PBMP_ASSIGN(valid_port_cpu_pbmp, PBMP_ALL(unit)); 11833 SOC_PBMP_ITER (valid_port_cpu_pbmp, port) { 11834 /* True only when recalc type (int or ext) is same as port type */ 11835 if (((!ext_mem_type && !SOC_PBMP_MEMBER(PBMP_EXT_MEM (unit), port)) || 11836 (ext_mem_type && SOC_PBMP_MEMBER(PBMP_EXT_MEM (unit), port))) && 11837 (port >= si->cmic_port) && (port <= si->lb_port)) { 11838 11839 op_node = ( si->port_cosq_base[port] / 8); 11840 for (op_node_offset = 0; 11841 op_node_offset < sal_ceil_func(si->port_num_uc_cosq[port],8); 11842 op_node_offset++) { 11843 11844 SOC_IF_ERROR_RETURN(READ_MMU_THDO_OPNCONFIG_CELLm(unit, 11845 MEM_BLOCK_ANY,op_node + op_node_offset, 11846 &mmu_thdo_opnconfig_cell_entry)); 11847 cur_limit = soc_mem_field32_get(unit, MMU_THDO_OPNCONFIG_CELLm, 11848 &mmu_thdo_opnconfig_cell_entry, 11849 OPN_SHARED_LIMIT_CELLf); 11850 if (_soc_sb2_mmu_config_shared_update_check( 11851 unit, cur_limit, shared_size, flags)) { 11852 if ((recalc_type == BCM_KT2_RECALC_SHARED_INT_DECREMENT) || 11853 (recalc_type == BCM_KT2_RECALC_SHARED_EXT_DECREMENT)) { 11854 temp_val = cur_limit - shared_size; 11855 } else { 11856 temp_val = shared_size - cur_limit; 11857 } 11858 soc_mem_field32_set(unit, MMU_THDO_OPNCONFIG_CELLm, 11859 &mmu_thdo_opnconfig_cell_entry, 11860 OPN_SHARED_LIMIT_CELLf, shared_size); 11861 11862 cur_limit = soc_mem_field32_get(unit, MMU_THDO_OPNCONFIG_CELLm, 11863 &mmu_thdo_opnconfig_cell_entry, 11864 OPN_SHARED_RESET_VALUE_CELLf); 11865 if ((recalc_type == BCM_KT2_RECALC_SHARED_INT_DECREMENT) || 11866 (recalc_type == BCM_KT2_RECALC_SHARED_EXT_DECREMENT)) { 11867 resume_limit = cur_limit - temp_val; 11868 } else { 11869 resume_limit = cur_limit + temp_val; 11870 } 11871 11872 soc_mem_field32_set(unit, MMU_THDO_OPNCONFIG_CELLm, 11873 &mmu_thdo_opnconfig_cell_entry, 11874 OPN_SHARED_RESET_VALUE_CELLf, resume_limit); 11875 11876 SOC_IF_ERROR_RETURN(WRITE_MMU_THDO_OPNCONFIG_CELLm(unit, 11877 MEM_BLOCK_ANY,op_node + op_node_offset, 11878 &mmu_thdo_opnconfig_cell_entry)); 11879 } 11880 } 11881 } 11882 } 11883 if (ext_mem_type) { 11884 for(cos=0; cos<SOC_REG_NUMELS(unit, OP_QUEUE_CONFIG_THDORDEEr); cos++) { 11885 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_CONFIG_THDORDEEr( 11886 unit, cos, &rval)); 11887 11888 temp_val = soc_reg_field_get(unit, OP_QUEUE_CONFIG_THDORDEEr, rval, 11889 Q_LIMIT_DYNAMICf); 11890 if (!temp_val) { 11891 cur_limit = soc_reg_field_get(unit, OP_QUEUE_CONFIG_THDORDEEr, rval, 11892 Q_SHARED_LIMITf); 11893 if (_soc_sb2_mmu_config_shared_update_check( 11894 unit, cur_limit, shared_size, flags)) { 11895 soc_reg_field_set(unit, OP_QUEUE_CONFIG_THDORDEEr, &rval, 11896 Q_SHARED_LIMITf, shared_size); 11897 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_CONFIG_THDORDEEr( 11898 unit, cos, rval)); 11899 } 11900 } 11901 } 11902 } else { 11903 for(cos=0; cos<SOC_REG_NUMELS(unit, OP_QUEUE_CONFIG_THDORDEIr); cos++) { 11904 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_CONFIG_THDORDEIr( 11905 unit, cos, &rval)); 11906 11907 temp_val = soc_reg_field_get(unit, OP_QUEUE_CONFIG_THDORDEIr, rval, 11908 Q_LIMIT_DYNAMICf); 11909 if (!temp_val) { 11910 cur_limit = soc_reg_field_get(unit, OP_QUEUE_CONFIG_THDORDEIr, rval, 11911 Q_SHARED_LIMITf); 11912 if (_soc_sb2_mmu_config_shared_update_check( 11913 unit, cur_limit, shared_size, flags)) { 11914 soc_reg_field_set(unit, OP_QUEUE_CONFIG_THDORDEIr, &rval, 11915 Q_SHARED_LIMITf, shared_size); 11916 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_CONFIG_THDORDEIr( 11917 unit, cos, rval)); 11918 } 11919 } 11920 } 11921 } 11922 11923 return SOC_E_NONE; 11924 } 11925 11926 /* 11927 * Function: 11928 * soc_sb2_xport_type_update 11929 * Purpose: 11930 * Rewrite the SOC control port structures to reflect the current port 11931 * mode, and reinitialize the port 11932 * Parameters: 11933 * unit - XGS unit #. 11934 * port - XGS port # on unit. 11935 * mode - (IEEE/HG/HG2/HG2-LITE) 11936 * Returns: 11937 * None. 11938 * Notes: 11939 * Must pause linkscan and take COUNTER_LOCK before calling this. 11940 */ 11941 void 11942 soc_sb2_xport_type_update(int unit, soc_port_t port, int mode) 11943 { 11944 soc_info_t *si; 11945 soc_port_t it_port; 11946 11947 si = &SOC_INFO(unit); 11948 11949 /* We need to lock the SOC structures until we finish the update */ 11950 SOC_CONTROL_LOCK(unit); 11951 11952 if (mode != SOC_ENCAP_IEEE) { 11953 SOC_PBMP_PORT_ADD(si->st.bitmap, port); 11954 SOC_PBMP_PORT_REMOVE(si->ether.bitmap, port); 11955 SOC_PBMP_PORT_REMOVE(si->xe.bitmap, port); 11956 /* special process for HG-Lite support to avoid wrong PBMP assignment. 11957 * 11958 * Note : 11959 * the 'to_hg_port' for this special design must carry proper encap mode 11960 * instead of TRUE/FALSE only. 11961 */ 11962 if (mode == SOC_ENCAP_HIGIG2_LITE) { 11963 SOC_PBMP_PORT_ADD(si->hl.bitmap, port); 11964 } else { 11965 /* for HG/HG2 case (GE port expected not allowed here) */ 11966 SOC_PBMP_PORT_ADD(si->hg.bitmap, port); 11967 SOC_PBMP_PORT_REMOVE(si->hl.bitmap, port); 11968 } 11969 } else { 11970 /* To IEEE mode */ 11971 SOC_PBMP_PORT_ADD(si->ether.bitmap, port); 11972 SOC_PBMP_PORT_ADD(si->xe.bitmap, port); 11973 SOC_PBMP_PORT_REMOVE(si->st.bitmap, port); 11974 SOC_PBMP_PORT_REMOVE(si->hg.bitmap, port); 11975 SOC_PBMP_PORT_REMOVE(si->hl.bitmap, port); 11976 } 11977 #define RECONFIGURE_PORT_TYPE_INFO(ptype) \ 11978 si->ptype.num = 0; \ 11979 si->ptype.min = si->ptype.max = -1; \ 11980 PBMP_ITER(si->ptype.bitmap, it_port) { \ 11981 si->ptype.port[si->ptype.num++] = it_port; \ 11982 if (si->ptype.min < 0) { \ 11983 si->ptype.min = it_port; \ 11984 } \ 11985 if (it_port > si->ptype.max) { \ 11986 si->ptype.max = it_port; \ 11987 } \ 11988 } 11989 11990 /* Recalculate port type data */ 11991 RECONFIGURE_PORT_TYPE_INFO(ether); 11992 RECONFIGURE_PORT_TYPE_INFO(st); 11993 RECONFIGURE_PORT_TYPE_INFO(hg); 11994 RECONFIGURE_PORT_TYPE_INFO(xe); 11995 #undef RECONFIGURE_PORT_TYPE_INFO 11996 11997 soc_dport_map_update(unit); 11998 11999 /* Release SOC structures lock */ 12000 SOC_CONTROL_UNLOCK(unit); 12001 } 12002 12003 /* 12004 * soc_sb2_5626x_devtype 12005 * 12006 * Verify saber2 device is 5626x 12007 */ 12008 int 12009 soc_sb2_5626x_devtype (int unit) 12010 { 12011 uint16 dev_id; 12012 uint8 rev_id; 12013 soc_cm_get_id(unit, &dev_id, &rev_id); 12014 if ((dev_id == BCM56260_DEVICE_ID) 12015 || (dev_id == BCM56261_DEVICE_ID) 12016 || (dev_id == BCM56262_DEVICE_ID) 12017 || (dev_id == BCM56263_DEVICE_ID) 12018 || (dev_id == BCM56265_DEVICE_ID) 12019 || (dev_id == BCM56266_DEVICE_ID) 12020 || (dev_id == BCM56267_DEVICE_ID) 12021 || (dev_id == BCM56268_DEVICE_ID) 12022 || (dev_id == BCM56233_DEVICE_ID)) { 12023 return TRUE; 12024 } else { 12025 return FALSE; 12026 } 12027 } 12028 int 12029 soc_sb2_get_max_buffer_size(int unit, int external, int value) 12030 { 12031 int cval; 12032 cval= (external ? 12033 _soc_sb2_mmu_intermediate_results.general_info.max_ext_cell_buff_size: 12034 _soc_sb2_mmu_intermediate_results.general_info.max_int_cell_buff_size); 12035 if ((cval <= 0) || (cval >= value)) { 12036 return value; 12037 } else { 12038 return cval; 12039 } 12040 } 12041 void 12042 soc_sb2_get_queue_min_size(int unit, int *internal_size, int *external_size) 12043 { 12044 _sb2_output_port_threshold_t *output_port_threshold = 12045 &_soc_sb2_mmu_intermediate_results.output_port_threshold; 12046 if (internal_size) { 12047 *internal_size = output_port_threshold->min_grntd_res_queue_cells_int_buff; 12048 } 12049 if (external_size) { 12050 *external_size = output_port_threshold->min_grntd_res_queue_cells_ext_buff; 12051 } 12052 return; 12053 } 12054 #endif /* BCM_SABER_SUPPORT */