post.c (25457B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: post.c 8 * Purpose: Run MAC-Phy connectivity check after Reset init 9 */ 10 11 #include <soc/drv.h> 12 #include <soc/dcb.h> 13 #include <soc/pbsmh.h> 14 #include <soc/post.h> 15 #include <soc/debug.h> 16 #include <soc/phyctrl.h> 17 #include <soc/error.h> 18 #include <soc/feature.h> 19 #include <soc/mem.h> 20 #include <soc/firebolt.h> 21 #include <shared/bsl.h> 22 23 #ifdef BCM_CMICM_SUPPORT 24 #include <soc/cmicm.h> 25 #endif 26 27 #ifdef BCM_RAPTOR_SUPPORT 28 29 #define SOC_RAPTOR_POST_MAX_COUNT 25 30 31 #define SOC_RAPTOR_POST_BUF_SIZE 256 32 #define SOC_RAPTOR_POST_PKT_SIZE 64 33 34 /* microsec */ 35 #ifdef BCM_ICS 36 /* Same time on Quickturn as well */ 37 #define DMA_DONE_TIMEOUT 100000 38 #else 39 #define DMA_DONE_TIMEOUT \ 40 (SAL_BOOT_SIMULATION ? 100000000 : 100000) 41 #endif 42 43 #define SOC_DEFAULT_RCPU_TRX_PORT (4) /* GMII port */ 44 45 /* 46 * Function: 47 * _soc_dma_tx_packet_port 48 * Purpose: 49 * TX a packet 50 * Parameters: 51 * unit - Unit on which being transmitted 52 * Returns: 53 * SOC_E_XXX 54 */ 55 STATIC int 56 _soc_dma_tx_packet_port(int unit, dma_chan_t c, soc_port_t port, uint32 *tx_pkt) 57 { 58 int rv = SOC_E_NONE; 59 60 dv_t dvs; 61 uint32 ctrl; 62 dv_t *dv = &dvs; 63 dcb_t *dcb; 64 uint32 flags = 0; 65 int tx_unit = unit; 66 soc_pbsmh_hdr_t phh_s; 67 soc_pbsmh_hdr_t *pbh = &phh_s; 68 69 if (tx_pkt == NULL) { 70 return SOC_E_NONE; 71 } 72 73 #ifdef INCLUDE_RCPU 74 if (SOC_IS_RCPU_UNIT(unit)) { 75 port = soc_property_get(unit, spn_RCPU_PORT, SOC_DEFAULT_RCPU_TRX_PORT); 76 tx_unit = soc_property_get(unit, spn_RCPU_MASTER_UNIT, 0);; 77 } 78 #endif /* INCLUDE_RCPU */ 79 80 sal_memset(dv, 0, sizeof(*dv)); 81 dv->dv_unit = tx_unit; 82 dcb = dv->dv_dcb = tx_pkt; 83 84 dv->dv_op = DV_TX; 85 dv->dv_magic = 0xba5eba11; 86 dv->dv_channel = c; 87 dv->dv_cnt = 1; 88 SOC_DMA_HG_SET(flags, 1); 89 PBS_MH_W0_START_SET(pbh); 90 PBS_MH_W1_RSVD_SET(pbh); 91 PBS_MH_V2_W2_SMOD_DPORT_COS_SET(pbh, 0, port, 0, 0, 0); 92 93 rv = SOC_DCB_ADDTX(tx_unit, dv, 94 (sal_vaddr_t) SOC_DCB_IDX2PTR(dv->dv_unit, tx_pkt + 16, dv->dv_vcnt), 95 SOC_RAPTOR_POST_PKT_SIZE, /* Min packet size */ 96 PBMP_ALL(tx_unit), /* Not used */ 97 PBMP_ALL(tx_unit), /* Not used */ 98 PBMP_ALL(tx_unit), /* Not used */ 99 flags, /* SOB MH */ 100 (uint32 *)pbh /* SOB MH */ 101 ); 102 /* Mark the end of the packet */ 103 SOC_DCB_SG_SET(dv->dv_unit, dcb, 0); 104 if (rv >= 0) { 105 soc_cm_sflush(tx_unit, dv->dv_dcb, SOC_DCB_SIZE(tx_unit)); 106 if (SOC_IS_RCPU_UNIT(unit)) { 107 #ifdef INCLUDE_RCPU 108 SOC_IF_ERROR_RETURN(soc_dma_wait(tx_unit, dv)); 109 #endif /* INCLUDE_RCPU */ 110 } else { 111 sal_usecs_t start_time; 112 int diff_time; 113 uint32 dma_stat; 114 uint32 dma_state; 115 116 ctrl = soc_pci_read(unit, CMIC_DMA_CTRL); 117 soc_pci_write(unit, CMIC_DMA_CTRL, ctrl | DC_MEM_TO_SOC(c)); 118 soc_pci_write(unit, CMIC_DMA_DESC(c), 119 soc_cm_l2p(unit, dv->dv_dcb)); 120 /* Start DMA */ 121 soc_pci_write(unit, CMIC_DMA_STAT, DS_DMA_EN_SET(c)); 122 123 start_time = sal_time_usecs(); 124 diff_time = 0; 125 dma_state = (DS_DESC_DONE_TST(c) | DS_CHAIN_DONE_TST(c)); 126 do { 127 sal_udelay(SAL_BOOT_SIMULATION ? 1000 : 100); 128 dma_stat = soc_pci_read(unit, CMIC_DMA_STAT) & 129 (DS_DESC_DONE_TST(c) | DS_CHAIN_DONE_TST(c)); 130 diff_time = SAL_USECS_SUB(sal_time_usecs(), start_time); 131 if (diff_time > DMA_DONE_TIMEOUT) { /* 10 Sec(QT)/10 msec */ 132 rv = SOC_E_TIMEOUT; 133 break; 134 } else if (diff_time < 0) { 135 /* Restart in case system time changed */ 136 start_time = sal_time_usecs(); 137 } 138 } while (dma_stat != dma_state); 139 /* Clear CHAIN_DONE and DESC_DONE */ 140 soc_pci_write(unit, CMIC_DMA_STAT, DS_DMA_EN_CLR(c)); 141 soc_pci_write(unit, CMIC_DMA_STAT, DS_DESC_DONE_CLR(c)); 142 soc_pci_write(unit, CMIC_DMA_STAT, DS_CHAIN_DONE_CLR(c)); 143 soc_pci_write(unit, CMIC_DMA_CTRL, ctrl); 144 } 145 } 146 return rv; 147 } 148 /* 149 * Function: 150 * _soc_raptor_port_probe 151 * Purpose: 152 * Probe the phy and set up the phy and mac of the indicated port 153 * Parameters: 154 * unit - StrataSwitch unit number. 155 * port - Port to probe 156 * okay - Output parameter indicates port can be enabled. 157 * Returns: 158 * SOC_E_NONE 159 * SOC_E_INTERNAL - internal error. 160 * Notes: 161 * If error is returned, the port should not be enabled. 162 */ 163 164 STATIC int 165 _soc_raptor_port_probe(int unit, soc_port_t p, mac_driver_t **macdp) 166 { 167 int rv; 168 mac_driver_t *macd; 169 170 *macdp = NULL; 171 172 LOG_VERBOSE(BSL_LS_SOC_COMMON, 173 (BSL_META_U(unit, 174 "Init port %d PHY...\n"), p)); 175 176 if ((rv = soc_phyctrl_probe(unit, p)) < 0) { 177 LOG_VERBOSE(BSL_LS_SOC_COMMON, 178 (BSL_META_U(unit, 179 "Port %s: Failed to probe PHY: %s\n"), 180 SOC_PORT_NAME(unit, p), soc_errmsg(rv))); 181 return rv; 182 } 183 184 if ((rv = soc_phyctrl_init(unit, p)) < 0) { 185 LOG_VERBOSE(BSL_LS_SOC_COMMON, 186 (BSL_META_U(unit, 187 "Port %s: Failed to initialize PHY: %s\n"), 188 SOC_PORT_NAME(unit, p), soc_errmsg(rv))); 189 return rv; 190 } 191 192 LOG_VERBOSE(BSL_LS_SOC_COMMON, 193 (BSL_META_U(unit, 194 "Init port %d MAC...\n"), p)); 195 196 if ((rv = soc_mac_probe(unit, p, &macd)) < 0) { 197 LOG_VERBOSE(BSL_LS_SOC_COMMON, 198 (BSL_META_U(unit, 199 "Port %s: Failed to probe MAC: %s\n"), 200 SOC_PORT_NAME(unit, p), soc_errmsg(rv))); 201 return rv; 202 } 203 204 *macdp = macd; 205 if ((rv = MAC_INIT(macd, unit, p)) < 0) { 206 LOG_VERBOSE(BSL_LS_SOC_COMMON, 207 (BSL_META_U(unit, 208 "Port %s: Failed to initialize MAC: %s\n"), 209 SOC_PORT_NAME(unit, p), soc_errmsg(rv))); 210 return rv; 211 } 212 213 return(SOC_E_NONE); 214 } 215 216 217 STATIC int 218 _soc_raptor_port_tx_ok(int unit, soc_port_t port) 219 { 220 uint32 grpkt; 221 222 SOC_IF_ERROR_RETURN(READ_GRFCSr(unit, port, &grpkt)); 223 if (grpkt) { 224 return SOC_E_FAIL; 225 } 226 227 SOC_IF_ERROR_RETURN(READ_GRPKTr(unit, port, &grpkt)); 228 if (grpkt) { 229 return SOC_E_NONE; 230 } else { 231 return SOC_E_FAIL; 232 } 233 } 234 235 #ifdef INCLUDE_RCPU 236 237 #define TABLE_HAS_UT_BITMAP(unit, table) \ 238 ((SOC_IS_FBX(unit) && (table) == EGR_VLANm) || \ 239 (SOC_IS_KATANA2 (unit) && (table) == VLAN_TABm)) 240 241 #define TABLE_HAS_T_BITMAP(unit, table) \ 242 (((table) == VLAN_TABm) || \ 243 (soc_feature(unit, soc_feature_egr_vlan_check) && (table) == EGR_VLANm)) 244 245 #define TABLE_HAS_PFM(unit, table) \ 246 (((table) == VLAN_TABm) || \ 247 (soc_feature(unit, soc_feature_egr_vlan_pfm) && (table) == EGR_VLANm)) 248 249 #define STG_BITS_PER_PORT 2 250 #define STG_PORT_MASK ((1 << STG_BITS_PER_PORT)-1) 251 #define STG_PORTS_PER_WORD (32 / STG_BITS_PER_PORT) 252 #define STG_WORD(port) ((port) / STG_PORTS_PER_WORD) 253 #define STG_BITS_SHIFT(port) \ 254 (STG_BITS_PER_PORT * ((port) % STG_PORTS_PER_WORD)) 255 #define STG_BITS_MASK(port) (STG_PORT_MASK << (STG_BITS_SHIFT(port))) 256 257 STATIC int 258 _soc_raptor_post_create_vlan(int unit, int vid, 259 pbmp_t pbmp, pbmp_t upbmp, int table) 260 { 261 vlan_tab_entry_t vt; 262 vlan_profile_tab_entry_t vp; 263 uint32 bmval, ptr, fldval; 264 265 sal_memcpy(&vt, soc_mem_entry_null(unit, table), 266 soc_mem_entry_words(unit, table) * 4); 267 268 soc_mem_field32_set(unit, table, &vt, STGf, 1); 269 soc_mem_field32_set(unit, table, &vt, VALIDf, 1); 270 if (TABLE_HAS_PFM(unit, table)) { 271 soc_mem_field32_set(unit, table, &vt, PFMf, 1); 272 } 273 274 if (TABLE_HAS_T_BITMAP(unit, table)) { 275 bmval = SOC_PBMP_WORD_GET(pbmp, 0); 276 soc_mem_field_set(unit, table, (uint32 *) &vt, 277 PORT_BITMAP_LOf, &bmval); 278 bmval = SOC_PBMP_WORD_GET(pbmp, 1); 279 soc_mem_field_set(unit, table, (uint32 *) &vt, 280 PORT_BITMAP_HIf, &bmval); 281 } 282 283 if (TABLE_HAS_UT_BITMAP(unit, table)) { 284 bmval = SOC_PBMP_WORD_GET(upbmp, 0); 285 soc_mem_field_set(unit, table, (uint32 *) &vt, 286 UT_BITMAP_LOf, &bmval); 287 bmval = SOC_PBMP_WORD_GET(upbmp, 1); 288 soc_mem_field_set(unit, table, (uint32 *) &vt, 289 UT_BITMAP_HIf, &bmval); 290 } 291 292 if (SOC_MEM_IS_VALID(unit, VLAN_PROFILE_TABm) && table == VLAN_TABm) { 293 ptr = 7; 294 soc_mem_field_set(unit, table, (uint32 *) &vt, 295 VLAN_PROFILE_PTRf, &ptr); 296 sal_memcpy(&vp, soc_mem_entry_null(unit, VLAN_PROFILE_TABm), 297 soc_mem_entry_words(unit, VLAN_PROFILE_TABm) * 4); 298 fldval = 1; 299 soc_mem_field_set(unit, VLAN_PROFILE_TABm, (uint32 *) &vp, 300 L2_PFMf, &fldval); 301 soc_mem_field_set(unit, VLAN_PROFILE_TABm, (uint32 *) &vp, 302 IPMCV6_ENABLEf, &fldval); 303 soc_mem_field_set(unit, VLAN_PROFILE_TABm, (uint32 *) &vp, 304 IPMCV4_ENABLEf, &fldval); 305 soc_mem_field_set(unit, VLAN_PROFILE_TABm, (uint32 *) &vp, 306 IPMCV6_L2_ENABLEf, &fldval); 307 soc_mem_field_set(unit, VLAN_PROFILE_TABm, (uint32 *) &vp, 308 IPMCV4_L2_ENABLEf, &fldval); 309 soc_mem_field_set(unit, VLAN_PROFILE_TABm, (uint32 *) &vp, 310 IPV6L3_ENABLEf, &fldval); 311 soc_mem_field_set(unit, VLAN_PROFILE_TABm, (uint32 *) &vp, 312 IPV4L3_ENABLEf, &fldval); 313 soc_mem_field_set(unit, VLAN_PROFILE_TABm, (uint32 *) &vp, 314 L3_IPV6_PFMf, &fldval); 315 soc_mem_field_set(unit, VLAN_PROFILE_TABm, (uint32 *) &vp, 316 L3_IPV4_PFMf, &fldval); 317 SOC_IF_ERROR_RETURN(soc_mem_write 318 (unit, VLAN_PROFILE_TABm, MEM_BLOCK_ALL, ptr, &vp)); 319 } 320 321 return soc_mem_write(unit, table, MEM_BLOCK_ALL, (int) vid, &vt); 322 } 323 324 STATIC int 325 _soc_raptor_post_init_switch(int unit, pbmp_t pbmp) 326 { 327 mac_driver_t *macd; 328 int speed, tmo; 329 int an = TRUE, an_done = FALSE, duplex = SOC_PORT_DUPLEX_FULL; 330 port_tab_entry_t ptab; /* Port table entry. */ 331 uint32 entry[SOC_MAX_MEM_WORDS]; /* STP group ports state map. */ 332 uint32 rcpu_port, rval; 333 334 rcpu_port = soc_property_get(unit, spn_RCPU_PORT, SOC_DEFAULT_RCPU_TRX_PORT); 335 336 /* 337 * Init Port 338 */ 339 /* Write PORT_TABm memory */ 340 sal_memcpy(&ptab, soc_mem_entry_null(unit, PORT_TABm), sizeof (ptab)); 341 342 /* Set default vlan id(pvid) for port. */ 343 soc_PORT_TABm_field32_set(unit, &ptab, PORT_VIDf, 1); 344 345 if (SOC_MEM_FIELD_VALID(unit, PORT_TABm, OUTER_TPIDf)) { 346 soc_PORT_TABm_field32_set(unit, &ptab, OUTER_TPIDf, 0x8100); 347 } 348 349 /* Enable mac based vlan classification. */ 350 soc_PORT_TABm_field32_set(unit, &ptab, MAC_BASED_VID_ENABLEf, 1); 351 352 /* Enable subned based vlan classification. */ 353 soc_PORT_TABm_field32_set(unit, &ptab, SUBNET_BASED_VID_ENABLEf, 1); 354 355 /* Set port type. */ 356 soc_PORT_TABm_field32_set(unit, &ptab, HIGIG_PACKETf, 0); 357 358 SOC_IF_ERROR_RETURN( 359 soc_mem_write(unit, PORT_TABm, MEM_BLOCK_ALL, rcpu_port, &ptab)); 360 361 /* 362 * Init VLAN 363 */ 364 SOC_PBMP_PORT_ADD(pbmp, rcpu_port); 365 366 SOC_IF_ERROR_RETURN( 367 _soc_raptor_post_create_vlan(unit, 1, pbmp, pbmp, EGR_VLANm)); 368 369 SOC_IF_ERROR_RETURN( 370 _soc_raptor_post_create_vlan(unit, 1, pbmp, pbmp, VLAN_TABm)); 371 372 /* Init STG */ 373 SOC_IF_ERROR_RETURN(soc_mem_read(unit, STG_TABm, MEM_BLOCK_ANY, 1, entry)); 374 375 /* set all the ports in forwarding state. */ 376 entry[0] = 0xffffffff; 377 entry[1] = 0xffffffff; 378 entry[2] = 0xffffffff; 379 entry[3] = 0xfff; 380 381 /* Write spanning tree group port states to hw. */ 382 SOC_IF_ERROR_RETURN( 383 soc_mem_write(unit, STG_TABm, MEM_BLOCK_ALL, 1, entry)); 384 385 SOC_IF_ERROR_RETURN( 386 soc_mem_write(unit, EGR_VLAN_STGm, MEM_BLOCK_ALL, 1, entry)); 387 388 /* Init MAC/PHY */ 389 390 /* 391 * If EB is connected through HiGig port, set the port mode to 392 * ethernet 393 */ 394 SOC_IF_ERROR_RETURN(_soc_raptor_port_probe(unit, rcpu_port, &macd)); 395 SOC_IF_ERROR_RETURN(MAC_INTERFACE_SET(macd, unit, rcpu_port, 396 SOC_PORT_IF_SGMII)); 397 398 if ((speed = 399 soc_property_port_get(unit, rcpu_port, spn_PORT_INIT_SPEED, -1)) != -1) { 400 an = FALSE; 401 } 402 403 SOC_IF_ERROR_RETURN(soc_phyctrl_auto_negotiate_set(unit, rcpu_port, an)); 404 if (an == TRUE) { 405 tmo = (SAL_BOOT_SIMULATION) ? 300000000 : 3000000; 406 while ( 407 (!soc_phyctrl_auto_negotiate_get(unit, rcpu_port, &an, &an_done)) && 408 (an_done == FALSE) && (tmo > 0)) { 409 sal_udelay(100000); 410 tmo -= 100000; 411 } 412 413 if (an_done == FALSE) { 414 return SOC_E_INIT; 415 } 416 } 417 418 SOC_IF_ERROR_RETURN(MAC_ENABLE_SET(macd, unit, rcpu_port, TRUE)); 419 420 SOC_IF_ERROR_RETURN(soc_phyctrl_enable_set(unit, rcpu_port, TRUE)); 421 422 if (an == TRUE) { 423 SOC_IF_ERROR_RETURN(soc_phyctrl_speed_get(unit, rcpu_port, &speed)); 424 } 425 426 SOC_IF_ERROR_RETURN(MAC_SPEED_SET(macd, unit, rcpu_port, speed)); 427 428 if ((an == FALSE) && ((duplex = 429 soc_property_port_get(unit, rcpu_port, spn_PORT_INIT_DUPLEX, -1)) != -1)) { 430 SOC_IF_ERROR_RETURN(MAC_DUPLEX_SET(macd, unit, rcpu_port, duplex)); 431 } else { 432 SOC_IF_ERROR_RETURN 433 (MAC_DUPLEX_SET(macd, unit, rcpu_port, SOC_PORT_DUPLEX_FULL)); 434 } 435 436 /* Init EPC_LINK_MAP */ 437 rval = 0; 438 soc_reg_field_set(unit, EPC_LINK_BMAPr, &rval, PORT_BITMAPf, 439 SOC_PBMP_WORD_GET(pbmp, 0)); 440 SOC_IF_ERROR_RETURN(WRITE_EPC_LINK_BMAPr(unit, rval)); 441 if (soc_feature(unit, soc_feature_register_hi)) { 442 soc_reg_field_set(unit, EPC_LINK_BMAP_HIr, &rval, PORT_BITMAPf, 443 SOC_PBMP_WORD_GET(pbmp, 1)); 444 SOC_IF_ERROR_RETURN(WRITE_EPC_LINK_BMAP_HIr(unit, rval)); 445 } 446 447 return SOC_E_NONE; 448 } 449 #endif /* INCLUDE_RCPU */ 450 451 STATIC int 452 _soc_raptor_post_run(int unit, uint32 *tx_pkt) 453 { 454 mac_driver_t *macd = NULL; 455 soc_port_t p; 456 int rv = 0; 457 uint32 int_mask = 0; 458 int speed; 459 int count; 460 soc_pbmp_t fe_pbmp; 461 port_tab_entry_t ptab; /* Port table entry. */ 462 463 /* 464 * Self test needs to be executed only on fe12 and fe36. 465 */ 466 SOC_PBMP_CLEAR(fe_pbmp); 467 if (SOC_IS_RAVEN(unit)) { 468 SOC_PBMP_ASSIGN(fe_pbmp, PBMP_FE_ALL(unit)); 469 } else { 470 p = (12 + 6); /* fe12 */ 471 if (SOC_PBMP_MEMBER(PBMP_FE_ALL(unit), p)) { 472 SOC_PBMP_PORT_ADD(fe_pbmp, p); /* fe12 */ 473 } 474 p = (36 + 6); /* fe36 */ 475 if (SOC_PBMP_MEMBER(PBMP_FE_ALL(unit), p)) { 476 SOC_PBMP_PORT_ADD(fe_pbmp, p); /* fe36 */ 477 } 478 } 479 if (SOC_PBMP_IS_NULL(fe_pbmp)) { 480 return SOC_E_NONE; 481 } 482 LOG_VERBOSE(BSL_LS_SOC_COMMON, 483 (BSL_META_U(unit, 484 "Running post on unit %d \n"), unit)); 485 486 for(count = 0; count < SOC_RAPTOR_POST_MAX_COUNT; count++) { 487 /* 488 * Setup 489 */ 490 SOC_IF_ERROR_RETURN(soc_phy_common_init(unit)); 491 int_mask = soc_intr_disable(unit, IRQ_DESC_DONE(0) | IRQ_CHAIN_DONE(0)); 492 PBMP_ITER(fe_pbmp, p) { 493 SOC_IF_ERROR_RETURN(_soc_raptor_port_probe(unit, p, &macd)); 494 SOC_IF_ERROR_RETURN(soc_phyctrl_auto_negotiate_set(unit, p, FALSE)); 495 SOC_IF_ERROR_RETURN(soc_phyctrl_loopback_set(unit, p, TRUE, TRUE)); 496 SOC_IF_ERROR_RETURN(MAC_ENABLE_SET(macd, unit, p, TRUE)); 497 SOC_IF_ERROR_RETURN(soc_phyctrl_enable_set(unit, p, TRUE)); 498 SOC_IF_ERROR_RETURN 499 (soc_phyctrl_speed_get(unit, p, &speed)); 500 SOC_IF_ERROR_RETURN 501 (MAC_SPEED_SET(macd, unit, p, speed)); 502 SOC_IF_ERROR_RETURN 503 (MAC_DUPLEX_SET(macd, unit, p, SOC_PORT_DUPLEX_FULL)); 504 SOC_IF_ERROR_RETURN 505 (MAC_PAUSE_SET(macd, unit, p, 0, 0)); 506 507 #ifdef INCLUDE_RCPU 508 /* 509 * Setup slave device. 510 */ 511 if (SOC_IS_RCPU_UNIT(unit)) { 512 if ((rv = _soc_raptor_post_init_switch(unit, fe_pbmp)) < 0) { 513 LOG_VERBOSE(BSL_LS_SOC_COMMON, 514 (BSL_META_U(unit, 515 "Failed to init switch unit %d \n"), unit)); 516 return rv; 517 } 518 } 519 #endif /* INCLUDE_RCPU */ 520 521 /* Filter packets received on port after loopback */ 522 sal_memcpy(&ptab, soc_mem_entry_null(unit, PORT_TABm), sizeof (ptab)); 523 soc_PORT_TABm_field32_set(unit, &ptab, PORT_VIDf, 1); 524 soc_PORT_TABm_field32_set(unit, &ptab, PORT_DIS_TAGf, 1); 525 soc_PORT_TABm_field32_set(unit, &ptab, PORT_DIS_UNTAGf, 1); 526 if (SOC_MEM_FIELD_VALID(unit, PORT_TABm, TRUST_INCOMING_VIDf)) { 527 soc_PORT_TABm_field32_set(unit, &ptab, TRUST_INCOMING_VIDf, 1); 528 } 529 if (SOC_MEM_FIELD_VALID(unit, PORT_TABm, OUTER_TPIDf)) { 530 soc_PORT_TABm_field32_set(unit, &ptab, OUTER_TPIDf, 0x8100); 531 } 532 if ((rv = soc_mem_write(unit, PORT_TABm, MEM_BLOCK_ALL, 533 p, &ptab)) < 0) { 534 return rv; 535 } 536 } 537 538 /* 539 * Test Run 540 */ 541 PBMP_ITER(fe_pbmp, p) { 542 LOG_VERBOSE(BSL_LS_SOC_COMMON, 543 (BSL_META_U(unit, 544 "Port %s: Packet Send \n"), 545 SOC_PORT_NAME(unit, p))); 546 SOC_IF_ERROR_RETURN(_soc_dma_tx_packet_port(unit, 0, p, tx_pkt)); 547 } 548 549 /* 550 * Result Check 551 */ 552 sal_udelay(SAL_BOOT_SIMULATION ? 100000 : 100); 553 rv = SOC_E_NONE; 554 PBMP_ITER(fe_pbmp, p) { 555 if ((rv = _soc_raptor_port_tx_ok(unit, p)) < 0) { 556 break; 557 } 558 } 559 560 /* 561 * Need to re-init and retest ? 562 */ 563 if (rv < 0) { 564 SOC_IF_ERROR_RETURN(soc_reset_init(unit)); 565 SOC_IF_ERROR_RETURN(soc_misc_init(unit)); 566 SOC_IF_ERROR_RETURN(soc_firebolt_internal_mmu_init(unit)); 567 } else { 568 LOG_VERBOSE(BSL_LS_SOC_COMMON, 569 (BSL_META_U(unit, 570 "Post completed in %d Iterations\n"), count + 1)); 571 break; /* All clear */ 572 } 573 } 574 575 576 /* 577 * Cleanup 578 */ 579 PBMP_ITER(fe_pbmp, p) { 580 /* macd is for the last FE port. But it should be fine */ 581 if (NULL != macd) { 582 SOC_IF_ERROR_RETURN(MAC_ENABLE_SET(macd, unit, p, FALSE)); 583 } 584 SOC_IF_ERROR_RETURN(soc_phyctrl_enable_set(unit, p, FALSE)); 585 SOC_IF_ERROR_RETURN(soc_phyctrl_loopback_set(unit, p, FALSE, TRUE)); 586 } 587 soc_intr_enable(unit, int_mask); 588 589 return(SOC_E_NONE); 590 } 591 592 static int _soc_raptor_post_init(int unit) 593 { 594 uint32 *tx_pkt; 595 int rv = SOC_E_NONE; 596 597 /* 598 * Applicable only for FE ports. 599 */ 600 if ((!soc_feature(unit, soc_feature_post)) || 601 (SOC_PBMP_IS_NULL(PBMP_FE_ALL(unit)))) { 602 return SOC_E_NONE; 603 } 604 605 tx_pkt = soc_cm_salloc(unit, SOC_RAPTOR_POST_BUF_SIZE, "tx_pkt"); 606 if (tx_pkt == NULL) { 607 return SOC_E_MEMORY; 608 } 609 sal_memset(tx_pkt, 0xFF, SOC_RAPTOR_POST_BUF_SIZE); 610 soc_cm_sflush(unit, tx_pkt, SOC_RAPTOR_POST_BUF_SIZE); 611 612 rv = _soc_raptor_post_run(unit, tx_pkt); 613 614 soc_cm_sfree(unit, tx_pkt); 615 616 return rv; 617 } 618 619 #endif /* BCM_RAPTOR_SUPPORT */ 620 621 #if defined(BCM_TRIDENT2_SUPPORT) || defined(BCM_TRIUMPH3_SUPPORT) ||\ 622 defined(BCM_KATANA_SUPPORT) 623 624 STATIC int _soc_tr3_cpu_queue_xoff_disable(int unit) 625 { 626 int rv = SOC_E_NONE; 627 dv_t *dv = NULL; 628 char *pkt_data = NULL; 629 pbmp_t empty_pbm; 630 int channel = 1; 631 uint32 rval; 632 633 if (SOC_WARM_BOOT(unit)) { 634 return SOC_E_NONE; 635 } 636 637 soc_dma_init(unit); 638 639 sal_memset( &empty_pbm, 0, sizeof(empty_pbm)); 640 641 if ((pkt_data = soc_cm_salloc( unit, 1512, "flush_pkt" )) == NULL ) { 642 return SOC_E_MEMORY; 643 } 644 645 if ((dv = soc_dma_dv_alloc(unit, DV_RX, 1)) == NULL) { 646 rv = SOC_E_MEMORY; 647 goto cleanup; 648 } 649 650 sal_memset(dv->dv_dcb, 0, SOC_DCB_SIZE(unit)); 651 652 if ( soc_dma_desc_add(dv, (sal_vaddr_t) pkt_data, 1512, empty_pbm, 653 empty_pbm, empty_pbm, 0, NULL) < 0 ) { 654 goto cleanup; 655 } 656 657 soc_dma_desc_end_packet(dv); 658 #ifdef BCM_CMICM_SUPPORT 659 if (soc_feature(unit, soc_feature_cmicm)) { 660 int cmc = SOC_PCI_CMC(unit); 661 uint32 reg_addr; 662 uint32 numq, reg_val; 663 664 numq = soc_property_uc_get(unit, 0, spn_NUM_QUEUES, NUM_CPU_COSQ(unit)); 665 reg_val = 0xffffffff; 666 667 if (numq < 32) { 668 reg_val = (1 << numq) - 1; 669 } 670 reg_addr = CMIC_CMCx_CHy_COS_CTRL_RX_0_OFFSET(cmc, channel); 671 soc_pci_write(unit, reg_addr, reg_val); 672 reg_val = 0; 673 if (numq > 32 && numq < 64) { 674 reg_val = (1 << (numq - 32)) - 1; 675 } 676 reg_addr = CMIC_CMCx_CHy_COS_CTRL_RX_1_OFFSET(cmc, channel); 677 soc_pci_write(unit, reg_addr, reg_val); 678 679 /** chain end drop */ 680 reg_val = soc_pci_read(unit,CMIC_CMCx_CHy_DMA_CTRL_OFFSET(cmc, channel)); 681 reg_val |= 0x40; 682 soc_pci_write(unit, CMIC_CMCx_CHy_DMA_CTRL_OFFSET(cmc, channel), reg_val); 683 684 (void)soc_cmicm_intr0_disable(unit, 685 IRQ_CMCx_DESC_DONE(channel) | IRQ_CMCx_CHAIN_DONE(channel)); 686 } 687 #endif 688 689 if (soc_dma_start(unit, channel, dv) < 0) { 690 rv = SOC_E_INTERNAL; 691 goto cleanup; 692 } 693 694 sal_usleep(10); 695 696 if (SOC_IS_TRIUMPH3(unit) || SOC_IS_KATANAX(unit) || SOC_IS_APACHE(unit)) { 697 SOC_IF_ERROR_RETURN(READ_LLS_FC_CONFIGr(unit, &rval)); 698 soc_reg_field_set(unit, LLS_FC_CONFIGr, &rval, 699 FC_CFG_DISABLE_L2_COSMASK_XOFFf, 1); 700 SOC_IF_ERROR_RETURN(WRITE_LLS_FC_CONFIGr(unit, rval)); 701 } 702 703 if (SOC_IS_TD_TT(unit) && !SOC_IS_APACHE(unit)) { 704 SOC_IF_ERROR_RETURN(READ_ES_PIPE0_LLS_FC_CONFIGr(unit, &rval)); 705 soc_reg_field_set(unit, ES_PIPE0_LLS_FC_CONFIGr, &rval, 706 FC_CFG_DISABLE_L2_COSMASK_XOFFf, 1); 707 SOC_IF_ERROR_RETURN(WRITE_ES_PIPE0_LLS_FC_CONFIGr(unit, rval)); 708 } 709 710 cleanup: 711 if (dv) { 712 soc_dma_abort_dv(unit, dv); 713 soc_dma_dv_free(unit, dv); 714 } 715 if (pkt_data) { 716 soc_cm_sfree(unit, pkt_data); 717 } 718 719 soc_dma_init(unit); 720 721 return rv; 722 723 } 724 725 STATIC int _soc_tr3_cpu_queue_post( int unit ) 726 { 727 if (SOC_IS_TD_TT(unit) || SOC_IS_TRIUMPH3(unit) || SOC_IS_KATANAX(unit)) { 728 pbmp_t empty_pbm; 729 epc_link_bmap_entry_t entry, oentry; 730 731 sal_memset( &empty_pbm, 0, sizeof(empty_pbm)); 732 SOC_IF_ERROR_RETURN(READ_EPC_LINK_BMAPm(unit, MEM_BLOCK_ALL, 0, &oentry)); 733 SOC_IF_ERROR_RETURN(READ_EPC_LINK_BMAPm(unit, MEM_BLOCK_ALL, 0, 734 &entry)); 735 soc_mem_pbmp_field_set(unit, EPC_LINK_BMAPm, &entry, PORT_BITMAPf, 736 &empty_pbm); 737 738 SOC_IF_ERROR_RETURN(WRITE_EPC_LINK_BMAPm(unit, MEM_BLOCK_ALL, 0, 739 &entry)); 740 741 SOC_IF_ERROR_RETURN(_soc_tr3_cpu_queue_xoff_disable(unit)); 742 743 SOC_IF_ERROR_RETURN(WRITE_EPC_LINK_BMAPm(unit, MEM_BLOCK_ALL, 0, 744 &oentry)); 745 } 746 return SOC_E_NONE; 747 } 748 #endif /* BCM_TRIDENT2_SUPPORT BCM_TRIUMPH3_SUPPORT BCM_KATANA_SUPPORT */ 749 750 int 751 soc_post_init(int unit) 752 { 753 uint32 runpost = 0; 754 if (SAL_BOOT_SIMULATION) { 755 return SOC_E_NONE; 756 } 757 runpost = soc_property_get(unit, spn_POST_INIT_ENABLE, 1); 758 if (runpost) { 759 #ifdef BCM_RAPTOR_SUPPORT 760 return _soc_raptor_post_init(unit); 761 #else 762 return SOC_E_NONE; 763 #endif 764 } else { 765 return SOC_E_NONE; 766 } 767 } 768 769 int 770 soc_mmu_post_init(int unit) 771 { 772 uint32 runpost = 0; 773 774 runpost = soc_property_get(unit, spn_POST_INIT_ENABLE, 0); 775 if ((runpost) && ((SOC_IS_TD_TT(unit) || 776 SOC_IS_TRIUMPH3(unit) || 777 SOC_IS_KATANAX(unit)))) { 778 #if defined(BCM_TRIDENT2_SUPPORT) || defined(BCM_TRIUMPH3_SUPPORT) ||\ 779 defined(BCM_KATANA_SUPPORT) 780 return _soc_tr3_cpu_queue_post(unit); 781 #else 782 return SOC_E_NONE; 783 #endif 784 } else { 785 return SOC_E_NONE; 786 } 787 }