metrolite.c (340530B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: metrolite.c 8 * Purpose: 9 * Requires: 10 */ 11 12 13 #include <sal/core/boot.h> 14 15 #include <soc/katana2.h> 16 #include <soc/metrolite.h> 17 #include <soc/saber2.h> 18 #include <soc/trident.h> 19 #include <soc/bradley.h> 20 #include <soc/drv.h> 21 #include <soc/error.h> 22 #include <soc/debug.h> 23 #include <soc/mem.h> 24 #include <soc/hash.h> 25 #include <soc/shmoo_and28.h> 26 #include <soc/phy/ddr34.h> 27 #include <soc/mspi.h> 28 #include <soc/phyreg.h> 29 #include <soc/iproc.h> 30 #include <shared/bsl.h> 31 #include <soc/scache.h> 32 #include <soc/bondoptions.h> 33 34 #ifdef BCM_METROLITE_SUPPORT 35 36 #ifdef BCM_WARM_BOOT_SUPPORT 37 38 /* Basic WB version. */ 39 #define BCM_WB_VERSION_1_0 SOC_SCACHE_VERSION(1,0) 40 41 /* Default Version - Latest */ 42 #define BCM_WB_DEFAULT_VERSION BCM_WB_VERSION_1_0 43 44 /* Default Scache Partition - Latest */ 45 #define BCM_FLEXIO_SCACHE_DEFAULT_PARTITION 0x1 46 47 static uint8 scache_begin_magic_number[]={0xAA,0xBB,0xCC,0xDD}; 48 static uint8 scache_end_magic_number[]={0xDD,0xCC,0xBB,0xAA}; 49 static bcm56270_tdm_info_t ml_scache_tdm_info={0}; 50 static uint32 ml_scache_tdm[ML_TDM_MAX_SIZE]={0}; 51 static uint32 ml_scache_speed[ML_MAX_PHYSICAL_PORTS]={0}; 52 static soc_port_details_t ml_scache_port_details[ML_MAX_PHYSICAL_PORTS+1]={{0}}; 53 static uint32 ml_port_speeds_scache[ML_MAX_PHYSICAL_PORTS] = {0}; 54 int _soc_ml_flexio_scache_retrieve_part0(int unit); 55 56 #endif 57 #define _SOC_ML_DEFIP_MAX_TCAMS 4 58 #define _SOC_ML_DEFIP_TCAM_DEPTH 256 59 60 #define PORTGROUP_SINGLE_MODE 4 61 #define PORTGROUP_DUAL_MODE 2 62 #define PORTGROUP_QUAD_MODE 1 63 64 int ml_max_linkphy_subports_per_port; 65 int ml_max_linkphy_streams_per_port; 66 int ml_max_linkphy_streams_per_slice; 67 68 int block_ml_max_startaddr[ML_MAX_BLOCKS]={0}; 69 int block_ml_max_endaddr[ML_MAX_BLOCKS]={0}; 70 71 /* 56270_1: bcm5627x_config = 1 */ 72 /* 4x2.5G + 4x10G + 4x11G + 2.5G LPBK */ 73 const static ml_speed_t ml_speed_56270_1 = { 74 2500, 2500, 2500, 2500, /* 1 - 4 */ 75 10000, 10000, 10000, 10000, /* 5 - 8 */ 76 11000, 11000, 11000, 11000, /* 9 - 12 */ 77 }; 78 const static soc_port_details_t ml_port_details_56270_1[]={ 79 {1, 4, 1,GE_PORT,2500}, 80 {5, 8, 1,XE_PORT,10000}, 81 {9,12, 1,HG_PORT,11000}, 82 {0,0,0,0} /* End */ 83 }; 84 85 /* 56271_1: bcm5627x_config = 1 */ 86 /* 4x1G/2.5G + 4xXFI + 4x1G/2.5G + 2.5G LPBK */ 87 const static ml_speed_t ml_speed_56271_1 = { 88 2500, 2500, 2500, 2500, /* 1 - 4 */ 89 10000, 10000, 10000, 10000, /* 5 - 8 */ 90 2500, 2500, 2500, 2500, /* 9 - 12 */ 91 }; 92 const static soc_port_details_t ml_port_details_56271_1[]={ 93 {1, 4, 1,GE_PORT,2500}, 94 {5, 8, 1,XE_PORT,10000}, 95 {9,12, 1,GE_PORT,2500}, 96 {0,0,0,0} /* End */ 97 }; 98 99 /* 56271_2: bcm5627x_config = 2 */ 100 /* 4x1G/2.5G G.INT+ 2x1G/2.5G/10G */ 101 const static ml_speed_t ml_speed_56271_2 = { 102 2500, 2500, 2500, 2500, /* 1 - 4 */ 103 10000, 0, 0, 0, /* 5 - 8 */ 104 10000, 0, 10000, 0, /* 9 - 12 */ 105 }; 106 const static soc_port_details_t ml_port_details_56271_2[]={ 107 {1, 4, 1,GE_PORT,2500}, 108 {5,5,1,XE_PORT,10000}, 109 {9,9,1,XE_PORT,10000}, 110 {11,11,1,XE_PORT,10000}, 111 {5, 8, 1,0,0}, 112 {10, 10, 1,0,0}, 113 {0,0,0,0} /* End */ 114 }; 115 116 /* 56271_3: bcm5627x_config = 3 */ 117 /* 4x1G/2.5G G.INT + 4x1G/2.5G/10G/11G */ 118 const static ml_speed_t ml_speed_56271_3 = { 119 2500, 2500, 2500, 2500, /* 1 - 4 */ 120 10000, 0, 0, 0, /* 5 - 8 */ 121 11000, 11000, 11000, 11000, /* 9 - 12 */ 122 }; 123 const static soc_port_details_t ml_port_details_56271_3[]={ 124 {1, 4, 1,GE_PORT,2500}, 125 {5,5,1,XE_PORT,10000}, 126 {9,12,1,HG_PORT,11000}, 127 {6, 8, 1,0,0}, 128 {0,0,0,0} /* End */ 129 }; 130 131 /* 56272_1: bcm5627x_config = 1 */ 132 /* 8xGE + 1G LPBK */ 133 const static ml_speed_t ml_speed_56272_1 = { 134 1000, 1000, 1000, 1000, /* 1 - 4 */ 135 2500, 0, 0, 0, /* 5 - 8 */ 136 1000, 1000, 1000, 1000, /* 9 - 12 */ 137 }; 138 const static soc_port_details_t ml_port_details_56272_1[]={ 139 {1, 4, 1,GE_PORT,1000}, 140 {5, 5, 1,GE_PORT,2500}, 141 {9,12,1,GE_PORT,1000}, 142 {0,0,0,0} /* End */ 143 }; 144 145 /* 56272_2: bcm5627x_config = 2 */ 146 /* 4x1G G.INT + 2x1G + 1G LPBK */ 147 const static ml_speed_t ml_speed_56272_2 = { 148 1000, 1000, 1000, 1000, /* 1 - 4 */ 149 2500, 0, 0, 0, /* 5 - 8 */ 150 1000, 0, 1000, 0, /* 9 - 12 */ 151 }; 152 153 const static soc_port_details_t ml_port_details_56272_2[]={ 154 {1, 4, 1,GE_PORT,1000}, 155 {5, 5, 1,GE_PORT,2500}, 156 {9, 9, 1,GE_PORT,1000}, 157 {11,11,1,GE_PORT,1000}, 158 {6, 8, 1,0,0}, 159 {10, 10, 1,0,0}, 160 {0,0,0,0} /* End */ 161 }; 162 163 soc_port_details_t *ml_selected_port_details; 164 soc_port_details_t *ml_selected_port_details_orig; 165 const static soc_port_details_t ml_port_details_56270_0[]={{0,0,0,0}}; 166 const static soc_port_details_t *ml_port_details[]={ 167 ml_port_details_56270_0, /* Dummy */ 168 ml_port_details_56270_1, 169 ml_port_details_56271_1, 170 ml_port_details_56271_2, 171 ml_port_details_56271_3, 172 ml_port_details_56272_1, 173 ml_port_details_56272_2, 174 ml_port_details_56270_1, 175 ml_port_details_56271_1 176 #ifdef BCM_WARM_BOOT_SUPPORT 177 ,ml_scache_port_details /* Dummy port details 178 reserved for WB */ 179 #endif 180 }; 181 182 ml_speed_t *bcm56270_speed[SOC_MAX_NUM_DEVICES] = {NULL}; 183 const static ml_speed_t ml_speed_56270_0 = {0}; 184 const static uint32 *bcm56270_speed_s[]={ 185 ml_speed_56270_0, /* Dummy */ 186 ml_speed_56270_1, 187 ml_speed_56271_1, 188 ml_speed_56271_2, 189 ml_speed_56271_3, 190 ml_speed_56272_1, 191 ml_speed_56272_2, 192 ml_speed_56270_1, 193 ml_speed_56271_1 194 #ifdef BCM_WARM_BOOT_SUPPORT 195 ,ml_scache_speed /* Dummy speed reserved for WB*/ 196 #endif 197 }; 198 199 ml_port_to_block_subports_t 200 *ml_port_to_block_subports[SOC_MAX_NUM_DEVICES] = {NULL}; 201 ml_port_to_block_subports_t ml_port_to_block_subports_s = { 202 0,1,2,3, /* 1-4 mxq0 */ 203 0,1,2,3, /* 5-8 xl0 */ 204 0,1,2,3 /* 9-12 xl1 */ 205 }; 206 207 static ml_port_to_block_t *ml_port_to_block[SOC_MAX_NUM_DEVICES] = {NULL}; 208 static ml_port_to_block_t ml_port_to_block_s = { 209 0,0,0,0, /* 1-4 mxq0 */ 210 1,1,1,1, /* 5-8 xl0 */ 211 2,2,2,2 /* 9-12 xl1 */ 212 }; 213 214 ml_block_ports_t *ml_block_ports[SOC_MAX_NUM_DEVICES] = {NULL}; 215 ml_block_ports_t ml_block_ports_s = { 216 {1,2,3,4}, 217 {5,6,7,8}, 218 {9,10,11,12}, 219 }; 220 221 ml_port_speeds_t *ml_port_speeds[SOC_MAX_NUM_DEVICES] = {NULL}; 222 const static ml_port_speeds_t ml_port_speeds_56270_0 = {{0,0,0,0}}; 223 const static ml_port_speeds_t ml_port_speeds_56270_1 = { 224 {10000,0,0,2500},{10000,10000,0,10000},{11000,11000,0,11000}}; 225 const static ml_port_speeds_t ml_port_speeds_56271_1 = { 226 {10000,0,0,2500},{10000,10000,0,10000},{10000,0,0,2500}}; 227 const static ml_port_speeds_t ml_port_speeds_56271_2 = { 228 {10000,0,0,2500},{10000,0,0,0},{10000,10000,0,0}}; 229 const static ml_port_speeds_t ml_port_speeds_56271_3 = { 230 {10000,0,0,2500},{10000,0,0,0},{11000,11000,0,11000}}; 231 const static ml_port_speeds_t ml_port_speeds_56272_1 = { 232 {1000,0,0,1000},{2500,0,0,0},{1000,1000,0,1000}}; 233 const static ml_port_speeds_t ml_port_speeds_56272_2 = { 234 {1000,0,0,1000},{2500,0,0,0},{1000,1000,0,0}}; 235 236 ml_port_speeds_t *ml_port_speeds_s[] = { 237 (ml_port_speeds_t*)ml_port_speeds_56270_0, /* Dummy */ 238 (ml_port_speeds_t*)ml_port_speeds_56270_1, 239 (ml_port_speeds_t*)ml_port_speeds_56271_1, 240 (ml_port_speeds_t*)ml_port_speeds_56271_2, 241 (ml_port_speeds_t*)ml_port_speeds_56271_3, 242 (ml_port_speeds_t*)ml_port_speeds_56272_1, 243 (ml_port_speeds_t*)ml_port_speeds_56272_2, 244 (ml_port_speeds_t*)ml_port_speeds_56270_1, 245 (ml_port_speeds_t*)ml_port_speeds_56271_1 246 #ifdef BCM_WARM_BOOT_SUPPORT 247 ,(ml_port_speeds_t*)ml_port_speeds_scache 248 #endif 249 }; 250 251 ml_tdm_pos_info_t ml_tdm_pos_info[ML_MAX_BLOCKS]={{0}}; 252 253 typedef struct tdm_port_slots_info_s { 254 int32 position; 255 struct tdm_port_slots_info_s *prev; 256 struct tdm_port_slots_info_s *next; 257 }tdm_port_slots_info_t; 258 259 tdm_port_slots_info_t ml_tdm_port_slots_info[ML_MAX_LOGICAL_PORTS]; 260 261 uint32 ml_current_tdm[ML_TDM_MAX_SIZE]={0}; 262 uint32 ml_current_tdm_size=0; 263 static uint8 old_tdm_no=0; 264 265 /* TDM_A : 0:180MHz: 209 (19 * 11) Cycles Used */ 266 #define ML_TDM_A_SIZE 204 267 #define ML_TDM_A_FREQ 180 268 #define ML_TDM_A_ROW 19 269 #define ML_TDM_A_COL 11 270 const static uint32 ml_tdm_56270_A_ref[ML_TDM_A_SIZE] = { 271 /*Col:1*/ /*Col:2*/ /*Col:3*/ /*Col:4*/ /*Col:5*/ /*Col:6*/ /*Col:7*/ /*Col:8*/ /*Col:9*/ /*Col:10*/ /*Col:11*/ 272 /*1*/ 5, 6, 7, 8, 1, 9, 10, 11, 12, 5, 2, 273 /*2*/ 6, 7, 8, 9, 3, 10, 11, 12, 5, 6, 4, 274 /*3*/ 7, 8, 9, 10, ML_IDLE, ML_IDLE, 11, 12, 5, 6, 7, 275 /*4*/ 8, 9, 10, 11, 1, 12, 5, 6, 7, 8, 2, 276 /*5*/ 9, 10, 11, 12, 3, 5, 6, 7, 8, 9, 4, 277 /*6*/ 10, 11, 12, 5, ML_LPBK, 6, 7, 8, 9, 10, ML_CMIC, 278 /*7*/ 11, 12, 5, 6, ML_LPBK, 7, 8, 9, 10, 11, ML_CMIC, 279 /*8*/ 12, 5, 6, 7, 1, 8, 9, 10, 11, 12, 2, 280 /*9*/ 5, 6, 7, 8, 3, 9, 10, 11, 12, 5, 4, 281 /*10*/ 6, 7, 8, 9, ML_IDLE, ML_IDLE, 10, 11, 12, 5, 6, 282 /*11*/ 7, 8, 9, 10, 1, 11, 12, 5, 6, 7, 2, 283 /*12*/ 8, 9, 10, 11, 3, 12, 5, 6, 7, 8, 4, 284 /*13*/ 9, 10, 11, 12, ML_LPBK, 5, 6, 7, 8, 9, ML_CMIC, 285 /*14*/ 10, 11, 12, 5, ML_LPBK, 6, 7, 8, 9, 10, ML_CMIC, 286 /*15*/ 11, 12, 5, 6, 1, 7, 8, 9, 10, 11, 2, 287 /*16*/ 12, 5, 6, 7, 3, 8, 9, 10, 11, 12, 4, 288 /*17*/ 5, 6, 7, 8, ML_IDLE, ML_IDLE, 9, 10, 11, 12, 5, 289 /*18*/ 6, 7, 8, 9, ML_LPBK, 10, 11, 12, 5, 6, ML_IDLE, 290 /*19*/ 7, 8, 9, 10, 11, 12 /* ------------------ EMPTY ----------------------*/ 291 }; 292 293 /* TDM_C : 0:125MHz: 147(21 * 7) Cycles Used */ 294 #define ML_TDM_C_SIZE 140 295 #define ML_TDM_C_FREQ 125 296 #define ML_TDM_C_ROW 21 297 #define ML_TDM_C_COL 7 298 const static uint32 ml_tdm_56271_C_ref[ML_TDM_C_SIZE] = { 299 /*Col:1*/ /*Col:2*/ /*Col:3*/ /*Col:4*/ /*Col:5*/ /*Col:6*/ /*Col:7*/ 300 /*1*/ 5, 6, 7, 8, 1, 9, ML_CMIC, 301 /*2*/ 5, 6, 7, 8, 2, 10, ML_LPBK, 302 /*3*/ 5, 6, 7, 8, 3, 11, ML_IDLE, 303 /*4*/ 5, 6, 7, 8, 4, 12, /* EMPTY */ 304 /*5*/ 5, 6, 7, 8, 1, 9, /* EMPTY */ 305 /*6*/ 5, 6, 7, 8, 2, 10, ML_LPBK, 306 /*7*/ 5, 6, 7, 8, 3, 11, ML_CMIC, 307 /*8*/ 5, 6, 7, 8, 4, 12, ML_IDLE, 308 /*9*/ 5, 6, 7, 8, 1, 9, /* EMPTY */ 309 /*10*/ 5, 6, 7, 8, 2, 10, ML_LPBK, 310 /*11*/ 5, 6, 7, 8, 3, 11, ML_IDLE, 311 /*12*/ 5, 6, 7, 8, 4, 12, /* EMPTY */ 312 /*13*/ 5, 6, 7, 8, 1, 9, ML_CMIC, 313 /*14*/ 5, 6, 7, 8, 2, 10, ML_LPBK, 314 /*15*/ 5, 6, 7, 8, 3, 11, ML_IDLE, 315 /*16*/ 5, 6, 7, 8, 4, 12, /* EMPTY */ 316 /*17*/ 5, 6, 7, 8, 1, 9, /* EMPTY */ 317 /*18*/ 5, 6, 7, 8, 2, 10, ML_LPBK, 318 /*19*/ 5, 6, 7, 8, 3, 11, ML_CMIC, 319 /*20*/ 5, 6, 7, 8, 4, 12, ML_IDLE, 320 /*21*/ 5, 6, 7, 8, ML_IDLE, ML_IDLE /* EMPTY */ 321 }; 322 323 324 /* TDM_B : 0:30MHz: 16 (4 * 4) Cycles Used */ 325 #define ML_TDM_B_SIZE 16 326 #define ML_TDM_B_FREQ 30 327 #define ML_TDM_B_ROW 4 328 #define ML_TDM_B_COL 4 329 const static uint32 ml_tdm_56272_B_ref[ML_TDM_B_SIZE] = { 330 /*Col:1*/ /*Col:2*/ /*Col:3*/ /*Col:4*/ 331 /*1*/ ML_IDLE, 1, 9, 5, 332 /*2*/ ML_CMIC, 2, 10, 5, 333 /*3*/ ML_LPBK, 3, 11, 5, 334 /*4*/ ML_CMIC, 4, 12, ML_IDLE 335 }; 336 337 /* TDM related functions and structures */ 338 static bcm56270_tdm_info_t bcm56270_tdm_info[]={ 339 {0, 0, 0, 0}, /* Dummy */ 340 /* 56270_1 Cfg=1:IntCfg=1 */ 341 {ML_TDM_A_FREQ, ML_TDM_A_SIZE, ML_TDM_A_ROW, ML_TDM_A_COL}, 342 343 /* 56271_1 Cfg=1:IntCfg=2 */ 344 {ML_TDM_C_FREQ, ML_TDM_C_SIZE, ML_TDM_C_ROW, ML_TDM_C_COL}, 345 346 /* 56271_2 Cfg=2:IntCfg=3 */ 347 {ML_TDM_C_FREQ, ML_TDM_C_SIZE, ML_TDM_C_ROW, ML_TDM_C_COL}, 348 349 /* 56271_3 Cfg=3:IntCfg=4 */ 350 {ML_TDM_C_FREQ, ML_TDM_C_SIZE, ML_TDM_C_ROW, ML_TDM_C_COL}, 351 352 353 /* 56272_1 Cfg=1:IntCfg=5 */ 354 {ML_TDM_B_FREQ, ML_TDM_B_SIZE, ML_TDM_B_ROW, ML_TDM_B_COL}, 355 356 /* 56272_2 Cfg=1:IntCfg=6 */ 357 {ML_TDM_B_FREQ, ML_TDM_B_SIZE, ML_TDM_B_ROW, ML_TDM_B_COL}, 358 359 360 /* 53460_1 Cfg=1:IntCfg=1 */ 361 {ML_TDM_A_FREQ, ML_TDM_A_SIZE, ML_TDM_A_ROW, ML_TDM_A_COL}, 362 363 /* 53461_1 Cfg=1:IntCfg=2 */ 364 {ML_TDM_C_FREQ, ML_TDM_C_SIZE, ML_TDM_C_ROW, ML_TDM_C_COL} 365 #ifdef BCM_WARM_BOOT_SUPPORT 366 ,{0, 0, 0, 0}, 367 #endif 368 }; 369 370 static uint32 ml_tdm_A_56270_0[ML_TDM_A_SIZE]={0}; /* Dummy */ 371 static uint32 ml_tdm_A_56270_1[ML_TDM_A_SIZE]={0}; /* Filled up Runtime */ 372 static uint32 ml_tdm_C_56271_1[ML_TDM_C_SIZE]={0}; /* Filled up Runtime */ 373 static uint32 ml_tdm_C_56271_2[ML_TDM_C_SIZE]={0}; /* Filled up Runtime */ 374 static uint32 ml_tdm_C_56271_3[ML_TDM_C_SIZE]={0}; /* Filled up Runtime */ 375 static uint32 ml_tdm_B_56272_1[ML_TDM_B_SIZE]={0}; /* Filled up Runtime */ 376 static uint32 ml_tdm_B_56272_2[ML_TDM_B_SIZE]={0}; /* Filled up Runtime */ 377 378 static uint32 *bcm56270_tdm[]={ 379 ml_tdm_A_56270_0, /* Dummy to match cfg_num and index */ 380 ml_tdm_A_56270_1, /* 56270 Cfg=1:IntCfg=1 */ 381 ml_tdm_C_56271_1, /* 56271 Cfg=1:IntCfg=2 */ 382 ml_tdm_C_56271_2, /* 56271 Cfg=2:IntCfg=3 */ 383 ml_tdm_C_56271_3, /* 56271 Cfg=3:IntCfg=4 */ 384 ml_tdm_B_56272_1, /* 56272 Cfg=1:IntCfg=5 */ 385 ml_tdm_B_56272_2, /* 56272 Cfg=2:IntCfg=6 */ 386 ml_tdm_A_56270_1, /* 53460 Cfg=1:IntCfg=1 */ 387 ml_tdm_C_56271_1 /* 53461 Cfg=1:IntCfg=1 */ 388 #ifdef BCM_WARM_BOOT_SUPPORT 389 ,ml_scache_tdm /*Dummy TDM reserved for WB */ 390 #endif 391 }; 392 393 extern int 394 bcm_kt2_modid_set(int unit, int *my_modid_list, int *my_modid_valid_list , 395 int *base_port_ptr_list); 396 int _soc_metrolite_get_cfg_num(int unit, int skip_warmboot, int *new_cfg_num); 397 extern int 398 bcm_kt2_modid_set_all(int unit, int *my_modid_list, int *my_modid_valid_list, 399 int *base_port_ptr_list); 400 401 int _soc_metrolite_get_cfg_num(int unit, int skip_warmboot, int *new_cfg_num) 402 { 403 int cfg_num=-1; 404 int max_cfg_num=0; 405 int def_cfg_num=0; 406 int offset_cfg_num=0; 407 uint16 dev_id=0; 408 uint8 rev_id=0; 409 410 #ifdef BCM_WARM_BOOT_SUPPORT 411 if (SOC_WARM_BOOT(unit) && (!skip_warmboot)) { 412 cfg_num = COUNTOF(bcm56270_tdm_info) - 1; 413 if (bcm56270_tdm_info[cfg_num].tdm_size != 0) { 414 *new_cfg_num = cfg_num; 415 return SOC_E_NONE; 416 } 417 /* FAll thru */ 418 } 419 #endif 420 cfg_num = soc_property_get(unit, spn_BCM5627X_CONFIG,0xFF); 421 422 soc_cm_get_id(unit, &dev_id, &rev_id); 423 424 switch(dev_id) { 425 case BCM56270_DEVICE_ID: 426 def_cfg_num = BCM56270_DEVICE_ID_DEFAULT_CFG; 427 offset_cfg_num = BCM56270_DEVICE_ID_OFFSET_CFG; 428 max_cfg_num = BCM56270_DEVICE_ID_MAX_CFG; 429 break; 430 case BCM56271_DEVICE_ID: 431 def_cfg_num = BCM56271_DEVICE_ID_DEFAULT_CFG; 432 offset_cfg_num = BCM56271_DEVICE_ID_OFFSET_CFG; 433 max_cfg_num = BCM56271_DEVICE_ID_MAX_CFG; 434 break; 435 case BCM56272_DEVICE_ID: 436 def_cfg_num = BCM56272_DEVICE_ID_DEFAULT_CFG; 437 offset_cfg_num = BCM56272_DEVICE_ID_OFFSET_CFG; 438 max_cfg_num = BCM56272_DEVICE_ID_MAX_CFG; 439 break; 440 case BCM53460_DEVICE_ID: 441 def_cfg_num = BCM56270_DEVICE_ID_DEFAULT_CFG; 442 offset_cfg_num = BCM56270_DEVICE_ID_OFFSET_CFG; 443 max_cfg_num = BCM56270_DEVICE_ID_MAX_CFG; 444 break; 445 case BCM53461_DEVICE_ID: 446 def_cfg_num = BCM56271_DEVICE_ID_DEFAULT_CFG; 447 offset_cfg_num = BCM56271_DEVICE_ID_OFFSET_CFG; 448 max_cfg_num = BCM56271_DEVICE_ID_DEFAULT_CFG; 449 break; 450 451 default : 452 /* Not supported yet */ 453 return SOC_E_UNAVAIL; 454 } 455 456 if (cfg_num == 0xFF) { 457 *new_cfg_num = def_cfg_num; 458 } else { 459 if (cfg_num == 0) { 460 LOG_DEBUG(BSL_LS_SOC_COMMON, (BSL_META_U(unit, "Config=0 is not allowed\n"))); 461 return SOC_E_PARAM; 462 } 463 *new_cfg_num = cfg_num + offset_cfg_num; 464 } 465 if (*new_cfg_num > max_cfg_num) { 466 LOG_ERROR(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 467 "Cfg_num:%d Internal cfg_num:%d \n"),cfg_num,*new_cfg_num)); 468 LOG_ERROR(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 469 "Wrong %s ==> cfg_num:%d DEFAULT:%d START:%d MAX:%d \n"), 470 spn_BCM5627X_CONFIG, cfg_num, 471 def_cfg_num-offset_cfg_num,1,max_cfg_num-offset_cfg_num)); 472 *new_cfg_num = def_cfg_num; 473 return SOC_E_NONE; 474 } 475 LOG_VERBOSE(BSL_LS_SOC_COMMON, 476 (BSL_META_U(unit, 477 "Info Cfg_num:%d Internal cfg_num:%d \n"),cfg_num,*new_cfg_num)); 478 479 return SOC_E_NONE; 480 } 481 482 #if 0 483 soc_error_t ml_tdm_verify(int unit, 484 uint32 *tdm, 485 uint32 total_tdm_slots, 486 uint32 tdm_freq, /* In MHHz */ 487 uint32 *port_speed, 488 uint32 lpbk_port_speed, 489 uint32 *offender_port) 490 { 491 /* Following rules need to be met */ 492 /* Rule1 : Each Loopback port need 2.5G bandwidth */ 493 /* Rule2 : Each CMIC port need 2G bandwidth */ 494 /* Rule3 : Loopback (LPBK) ports require min 3 cycle spacing among LPBK or 495 CMIC ports */ 496 /* Rule4 : Each subport in MXQPORT operates with 4 cycle TDM */ 497 /* Rule5 : Each 10G-XAUI ports should be able to operate in 4x2.5G with 4 498 slots allocated to each subport from the same MXQPORT */ 499 soc_error_t rv=SOC_E_NONE; 500 uint32 index=0; 501 uint32 expected_tdm_cycles_min=0; 502 uint32 expected_tdm_cycles_max=0; 503 uint32 tdm_freq_index=0; 504 uint32 speed_index=0; 505 uint32 port=0; 506 uint32 speed=0; 507 uint32 worse_tdm_slot_spacing=0; 508 uint32 prev_tdm_slot_spacing=0; 509 uint32 next_tdm_slot_spacing=0; 510 #if 0 511 uint32 tdm_slot_spacing=0; 512 #endif 513 uint32 min_tdm_cycles=0; /* To Meet BW */ 514 uint32 count=0; 515 uint32 skip_count=0; 516 uint32 mxqblock=0; 517 uint32 outer_port=0; 518 uint32 inner_port=0; 519 uint32 spacing=0; 520 uint32 loop=0; 521 tdm_port_slots_info_t *head=NULL; 522 tdm_port_slots_info_t *head1=NULL; 523 tdm_port_slots_info_t *current=NULL; 524 tdm_port_slots_info_t *current1=NULL; 525 tdm_port_slots_info_t *prev = NULL; 526 tdm_port_slots_info_t *temp=NULL; 527 uint32 idle_flag=0; 528 uint32 idle_rule=0; 529 char base_tdm_str[80]; 530 531 /* Possible TDM frequencies 532 80MHz(16Cycles) ,120MHz(20Cycles),155MHz(84Cycles), 533 185MHz(80Cycles),185MHz(90Cycles) 534 */ 535 switch(tdm_freq) { 536 case 130: 537 if (total_tdm_slots == 284) { 538 /*TDM_A : 0:130MHz: 284 (41 * 7) Cycles Used */ 539 sal_strncpy(base_tdm_str, 540 "TDM_A : 0:130MHz: 284 (41 * 7) Cycles Used", 541 79); 542 tdm_freq_index=0; 543 expected_tdm_cycles_min=284; 544 expected_tdm_cycles_max=284; 545 } else if (total_tdm_slots == 141) { 546 /*TDM_C,C1,C2: 7:130MHz: 141 (21 * 6) Cycles Used */ 547 sal_strncpy(base_tdm_str, 548 "TDM_AA,TDM_C,C1,C2: 7:130MHz:141 (21 * 6) Cycles Used", 549 79); 550 tdm_freq_index=7; 551 expected_tdm_cycles_min=141; 552 expected_tdm_cycles_max=141; 553 } else if (total_tdm_slots == 168) { 554 /*TDM_D: 8:130MHz: 168 (28 * 6) Cycles Used */ 555 sal_strncpy(base_tdm_str, 556 "TDM_D: 8:130MHz: 168 (28 * 6) Cycles Used", 557 79); 558 tdm_freq_index=8; 559 expected_tdm_cycles_min=168; 560 expected_tdm_cycles_max=168; 561 } else { 562 LOG_ERROR(BSL_LS_SOC_COMMON, 563 (BSL_META_U(unit, 564 "Unsupported tdm slots:%d\n"), 565 total_tdm_slots)); 566 return SOC_E_FAIL; 567 } 568 break; 569 case 24: 570 /*TDM_A1: 2:24MHz: 13 (4 * 4) Cycles Used */ 571 sal_strncpy(base_tdm_str, 572 "TDM_A1: 2:24MHz: 13 (4 * 4) Cycles Used ", 573 79); 574 tdm_freq_index=2; 575 expected_tdm_cycles_min=13; 576 expected_tdm_cycles_max=13; 577 break; 578 case 37: 579 /*TDM_A1A: 3:37MHz: 84 (21 * 4) Cycles Used */ 580 sal_strncpy(base_tdm_str, 581 "TDM_A1A: 3:37MHz: 84 (21 * 4) Cycles Used ", 582 79); 583 tdm_freq_index=3; 584 expected_tdm_cycles_min=84; 585 expected_tdm_cycles_max=84; 586 break; 587 case 118: 588 if (total_tdm_slots == 133) { 589 /*TDM_B: 4:118MHz: 133 (23 * 6) Cycles Used */ 590 sal_strncpy(base_tdm_str, 591 "TDM_B: 4:118MHz: 133 (23 * 6) Cycles Used ", 592 79); 593 tdm_freq_index=4; 594 expected_tdm_cycles_min=133; 595 expected_tdm_cycles_max=133; 596 } else if (total_tdm_slots == 120) { 597 /*TDM_B1: 5:118MHz: 120 (20 * 6) Cycles Used */ 598 sal_strncpy(base_tdm_str, 599 "TDM_B1: 5:118MHz: 120 (20 * 6) Cycles Used ", 600 79); 601 tdm_freq_index=5; 602 expected_tdm_cycles_min=120; 603 expected_tdm_cycles_max=120; 604 } else if (total_tdm_slots == 121) { 605 /*TDM_B1A: 6:118MHz: 121 (21 * 6) Cycles Used */ 606 sal_strncpy(base_tdm_str, 607 "TDM_B1A: 6:118MHz: 121 (21 * 6) Cycles Used ", 608 79); 609 tdm_freq_index=6; 610 expected_tdm_cycles_min=121; 611 expected_tdm_cycles_max=121; 612 } else { 613 LOG_ERROR(BSL_LS_SOC_COMMON, 614 (BSL_META_U(unit, 615 "Unsupported tdm slots:%d\n"), 616 total_tdm_slots)); 617 return SOC_E_FAIL; 618 } 619 break; 620 case 75: 621 if (total_tdm_slots == 81) { 622 /*TDM_E,E1,E3 9:75MHz: 81 (21 * 4) Cycles Used */ 623 sal_strncpy(base_tdm_str, 624 "TDM_E,E1,E3 9:75MHz: 81 (21 * 4) Cycles Used ", 625 79); 626 tdm_freq_index=9; 627 expected_tdm_cycles_min=81; 628 expected_tdm_cycles_max=81; 629 } else if (total_tdm_slots == 16) { 630 /*TDM_EA 10:75MHz: 16 (4 * 4) Cycles Used */ 631 sal_strncpy(base_tdm_str, 632 "TDM_EA 10:75MHz: 16 (4 * 4) Cycles Used ", 633 79); 634 tdm_freq_index=10; 635 expected_tdm_cycles_min=16; 636 expected_tdm_cycles_max=16; 637 } else { 638 LOG_ERROR(BSL_LS_SOC_COMMON, 639 (BSL_META_U(unit, 640 "Unsupported tdm slots:%d\n"), 641 total_tdm_slots)); 642 return SOC_E_FAIL; 643 } 644 break; 645 default: 646 LOG_ERROR(BSL_LS_SOC_COMMON, 647 (BSL_META_U(unit, 648 "Unsupported tdm frequency:%d\n"), 649 tdm_freq)); 650 return SOC_E_FAIL; 651 } 652 LOG_VERBOSE(BSL_LS_SOC_COMMON, 653 (BSL_META_U(unit, 654 "\nINFO: BaseTdmStr:%s :Index %d:MinCycles%d:MaxCycle%d\n"), 655 base_tdm_str, 656 tdm_freq_index, expected_tdm_cycles_min, expected_tdm_cycles_max)); 657 if (!((total_tdm_slots >= expected_tdm_cycles_min) && 658 (total_tdm_slots <= expected_tdm_cycles_max))) { 659 LOG_ERROR(BSL_LS_SOC_COMMON, 660 (BSL_META_U(unit, 661 "Unsupported tdm cycles:%d (min:%d max:%d\n"), 662 total_tdm_slots, 663 expected_tdm_cycles_min,expected_tdm_cycles_max)); 664 return SOC_E_FAIL; 665 } 666 667 idle_flag=0; 668 idle_rule = 0; 669 /* Initialize list */ 670 for (port=0;port < ML_MAX_LOGICAL_PORTS ; port++) { 671 ml_tdm_port_slots_info[port].prev=&ml_tdm_port_slots_info[port]; 672 ml_tdm_port_slots_info[port].next=&ml_tdm_port_slots_info[port]; 673 ml_tdm_port_slots_info[port].position = -1; 674 } 675 for (index=0; index < total_tdm_slots; index++) { 676 if ((tdm[index] == ML_IDLE1) || 677 (tdm[index] == ML_IDLE)) { 678 if (tdm[index] == ML_IDLE) { 679 if (idle_flag == 1) { 680 idle_rule = 1; 681 } 682 idle_flag=1; 683 } 684 skip_count++; 685 continue; 686 } 687 if (((index - 1) != 0) && (index != total_tdm_slots - 1) && 688 (idle_flag == 1) && (idle_rule == 0)) { 689 LOG_ERROR(BSL_LS_SOC_COMMON, 690 (BSL_META_U(unit, 691 "### Internal Error: TDM Verification failed \n" 692 "### Two consecutive idle not found at position:%d\n" 693 "### TCAM Atomicity might get affected.\n"), 694 index - 1)); 695 *offender_port = ML_IDLE; 696 return SOC_E_CONFIG; 697 } 698 idle_flag=0; 699 port = tdm[index]; 700 if (ml_tdm_port_slots_info[port].position == -1) { 701 /* First Entry */ 702 ml_tdm_port_slots_info[port].position = index; 703 skip_count++; 704 continue; 705 } 706 head = current = &ml_tdm_port_slots_info[port]; 707 while(current->next !=head) { 708 current = current->next; 709 } 710 current->next=sal_alloc(sizeof(tdm_port_slots_info_t),"TDM Pointer"); 711 count++; 712 LOG_VERBOSE(BSL_LS_SOC_COMMON, 713 (BSL_META_U(unit, 714 "Count=%d SkipCount:%d Port:%d Addr:%p\n"), 715 count,skip_count,port,(void *)current->next)); 716 717 current->next->position=index; 718 current->next->prev=current; 719 current->next->next=head; 720 head->prev=current->next; 721 } 722 if (idle_rule == 0) { 723 /* Special case */ 724 if (!((tdm[0] == ML_IDLE) && 725 (tdm[total_tdm_slots-1] == ML_IDLE))) { 726 LOG_ERROR(BSL_LS_SOC_COMMON, 727 (BSL_META_U(unit, 728 "### Internal Error: TDM Verification failed \n" 729 "### Two consecutive idle not found at Edges \n" 730 "### TCAM Atomicity might get affected.\n"))); 731 *offender_port = ML_IDLE1; 732 return SOC_E_CONFIG; 733 } 734 } 735 LOG_VERBOSE(BSL_LS_SOC_COMMON, 736 (BSL_META_U(unit, 737 "Final Count=%d SkipCount:%d\n"),count,skip_count)); 738 LOG_VERBOSE(BSL_LS_SOC_COMMON, 739 (BSL_META_U(unit, 740 "Verifying rule \n"))); 741 LOG_VERBOSE(BSL_LS_SOC_COMMON, 742 (BSL_META_U(unit, 743 "Rule3: Loopback (LPBK) ports require min 3 cycle spacing " 744 "among LPBK or CMIC ports \n"))); 745 if (ml_tdm_port_slots_info[ML_LPBK].position == -1) { 746 LOG_CLI((BSL_META_U(unit, 747 "Loopback port missing in configuration \n"))); 748 return SOC_E_FAIL; 749 } 750 if (ml_tdm_port_slots_info[ML_CMIC].position == -1) { 751 LOG_CLI((BSL_META_U(unit, 752 "CMIC port missing in configuration \n"))); 753 return SOC_E_FAIL; 754 } 755 head = current = &ml_tdm_port_slots_info[ML_LPBK]; 756 do { 757 prev = current->prev; 758 if ( current->position != prev->position ) { 759 prev_tdm_slot_spacing = 760 (current->position - prev->position) > 0 ? 761 (current->position - prev->position)-1: 762 (total_tdm_slots - prev->position + 763 current->position) - 1; 764 next_tdm_slot_spacing = 765 (current->next->position - current->position) >0 ? 766 (current->next->position - current->position)-1: 767 (total_tdm_slots - current->position + 768 current->next->position) - 1; 769 if (prev_tdm_slot_spacing < 3) { 770 LOG_ERROR(BSL_LS_SOC_COMMON, 771 (BSL_META_U(unit, 772 "Loopback Ports need min 3 spacing but(prev)found" 773 "(current:%d , prev:%d)=%d\n"), 774 current->position,prev->position,prev_tdm_slot_spacing)); 775 rv = SOC_E_FAIL; 776 continue; 777 } 778 if (next_tdm_slot_spacing < 3) { 779 LOG_ERROR(BSL_LS_SOC_COMMON, 780 (BSL_META_U(unit, 781 "Loopback Ports need min 3 spacing but(next)found" 782 "(current:%d , prev:%d)=%d\n"), 783 current->position,prev->position,next_tdm_slot_spacing)); 784 rv = SOC_E_CONFIG; 785 *offender_port = ML_LPBK; 786 continue; 787 } 788 } else { 789 prev_tdm_slot_spacing = next_tdm_slot_spacing = 0; 790 } 791 #if 0 792 head1 = current1 = &ml_tdm_port_slots_info[ML_CMIC]; 793 do { 794 tdm_slot_spacing = (current->position - current1->position) > 0 ? 795 (current->position - current1->position)-1: 796 (total_tdm_slots - current1->position + 797 current->position) - 1 ; 798 if (tdm_slot_spacing < 3) { 799 LOG_ERROR(BSL_LS_SOC_COMMON, 800 (BSL_META_U(unit, 801 "Loopback and CMIC ports need min 3 spacing but " 802 "found:%u" "(Loopack current:%d , CMIC Current:%d)\n"), 803 tdm_slot_spacing, 804 current->position,current1->position)); 805 rv = SOC_E_CONFIG; 806 *offender_port=ML_LPBK; 807 continue; 808 } 809 current1 = current1->next; 810 }while ((current1 !=head1) && (rv == SOC_E_NONE)); 811 #endif 812 current = current->next; 813 } while ((current !=head) && (rv == SOC_E_NONE)); 814 LOG_VERBOSE(BSL_LS_SOC_COMMON, 815 (BSL_META_U(unit, 816 "Verifying rules \n"))); 817 LOG_VERBOSE(BSL_LS_SOC_COMMON, 818 (BSL_META_U(unit, 819 "Rule1 : Each Loopback port need 2.5G bandwidth \n"))); 820 LOG_VERBOSE(BSL_LS_SOC_COMMON, 821 (BSL_META_U(unit, 822 "Rule2 : Each CMIC port need 2G bandwidth \n"))); 823 for (index=0;index < ML_MAX_LOGICAL_PORTS && rv == SOC_E_NONE ;index++ ) { 824 port = index ; 825 if (ml_tdm_port_slots_info[port].position == -1) { 826 continue; 827 } 828 LOG_VERBOSE(BSL_LS_SOC_COMMON, 829 (BSL_META_U(unit, 830 " %d ==>\n\n"),port)); 831 switch(port) { 832 case ML_CMIC: 833 LOG_VERBOSE(BSL_LS_SOC_COMMON, 834 (BSL_META_U(unit, 835 "CMIM \n"))); 836 speed =2000; 837 break; 838 case ML_LPBK: 839 LOG_VERBOSE(BSL_LS_SOC_COMMON, 840 (BSL_META_U(unit, 841 "LOOPBAKC \n"))); 842 speed =lpbk_port_speed; 843 break; 844 default: 845 LOG_VERBOSE(BSL_LS_SOC_COMMON, 846 (BSL_META_U(unit, 847 " Port:%d Speed %d ==>\n\n"), 848 port,port_speed[port-1])); 849 speed = port_speed[port-1]; 850 break; 851 } 852 if ((speed == 0) && (!SOC_PBMP_MEMBER((PBMP_ALL(unit)), port))) { 853 /* Eagle ports are not removed from TDM calendar 854 * Eventhough not active after lane op. Ignore those 855 */ 856 continue; 857 } 858 859 switch(speed) { 860 case 1000: 861 speed_index=0; 862 break; 863 case 2000: 864 speed_index=1; 865 break; 866 case 2500: 867 speed_index=2; 868 break; 869 case 10000: 870 case 10500: /* Might need ut fir HG11 */ 871 case 11000: /* Might need ut fir HG11 */ 872 speed_index=3; 873 break; 874 case 12500: /* Special case for LPBK port */ 875 case 13000: 876 speed_index=4; 877 break; 878 case 20000: 879 speed_index=5; 880 break; 881 case 21000: 882 speed_index=6; 883 break; 884 default: 885 LOG_ERROR(BSL_LS_SOC_COMMON, 886 (BSL_META_U(unit, 887 "Unsupported speed:%d \n"),speed)); 888 return SOC_E_FAIL; 889 } 890 worse_tdm_slot_spacing=ml_tdm_cycles_info[tdm_freq_index][speed_index]. 891 worse_tdm_slot_spacing; 892 min_tdm_cycles=ml_tdm_cycles_info[tdm_freq_index][speed_index]. 893 min_tdm_cycles; 894 895 count=0; 896 head = current = &ml_tdm_port_slots_info[port]; 897 do { 898 prev = current->prev; 899 if (current->position != prev->position ) { 900 prev_tdm_slot_spacing = 901 (current->position - prev->position)> 0 ? 902 (current->position - prev->position)-1: 903 (total_tdm_slots - prev->position + 904 current->position) - 1 ; 905 next_tdm_slot_spacing = 906 (current->next->position - current->position) > 0 ? 907 (current->next->position - current->position)-1: 908 (total_tdm_slots - current->position + 909 current->next->position) - 1; 910 } else { 911 prev_tdm_slot_spacing = next_tdm_slot_spacing = 0; 912 } 913 LOG_VERBOSE(BSL_LS_SOC_COMMON, 914 (BSL_META_U(unit, 915 "Pos:%d Spacing (Prev %d - %d = )%d" 916 "(Next %d - %d = )%d\n"), current->position, 917 current->position , prev->position , 918 prev_tdm_slot_spacing, current->next->position , 919 current->position , next_tdm_slot_spacing)); 920 if ((prev_tdm_slot_spacing > worse_tdm_slot_spacing) || 921 (next_tdm_slot_spacing > worse_tdm_slot_spacing)) { 922 if (port == ML_CMIC) { 923 /* Exception for worst TDM slot spacing for CMIC port */ 924 LOG_VERBOSE(BSL_LS_SOC_COMMON, 925 (BSL_META_U(unit, 926 "WorseSpacing:%d (prev:%d next:%d)" 927 "NOK !!!! port:%d\n"), 928 worse_tdm_slot_spacing, 929 prev_tdm_slot_spacing, next_tdm_slot_spacing, 930 port)); 931 LOG_VERBOSE(BSL_LS_SOC_COMMON, 932 (BSL_META_U(unit,"**ATTN:SKIPPING FOR TIME-BEING \n"))); 933 } else { 934 LOG_ERROR(BSL_LS_SOC_COMMON, 935 (BSL_META_U(unit, 936 "WorseSpacing:%d (prev:%d next:%d)" 937 "NOK !!!! port:%d\n"), 938 worse_tdm_slot_spacing, 939 prev_tdm_slot_spacing, next_tdm_slot_spacing, 940 port)); 941 rv = SOC_E_CONFIG; 942 *offender_port=port; 943 continue; 944 } 945 } 946 count++; 947 current = current->next; 948 } while ((current !=head) && (rv == SOC_E_NONE)) ; 949 LOG_VERBOSE(BSL_LS_SOC_COMMON, 950 (BSL_META_U(unit, 951 "TDM Cycles: %d \n"),count)); 952 if (count < min_tdm_cycles) { 953 LOG_ERROR(BSL_LS_SOC_COMMON, 954 (BSL_META_U(unit, 955 "min_tdm_cycles:%dNOK !!!! port:%d\n"), 956 min_tdm_cycles,port)); 957 rv = SOC_E_CONFIG; 958 *offender_port=port; 959 continue; 960 } 961 LOG_VERBOSE(BSL_LS_SOC_COMMON, 962 (BSL_META_U(unit, 963 "n== %d <==\n\n"),port)); 964 } 965 966 LOG_VERBOSE(BSL_LS_SOC_COMMON, 967 (BSL_META_U(unit, 968 "Verifying rule \n"))); 969 LOG_VERBOSE(BSL_LS_SOC_COMMON, 970 (BSL_META_U(unit, 971 "Rule4 : Each subport in MXQPORT operates with 4 cycle TDM \n"))); 972 LOG_VERBOSE(BSL_LS_SOC_COMMON, 973 (BSL_META_U(unit, 974 "Verifying MXQports spacing concern\n"))); 975 for(mxqblock=0;mxqblock<(ML_MAX_BLOCKS-1) && rv == SOC_E_NONE ;mxqblock++) { 976 for(index=0; 977 index<ML_MAX_PORTS_PER_BLOCK && rv == SOC_E_NONE; 978 index++) { 979 outer_port = (*ml_block_ports[unit])[mxqblock][index]; 980 if (outer_port == 0xFF) { 981 if ((mxqblock == 7) && (index == 3)) { 982 outer_port = 40; 983 } else { 984 continue; 985 } 986 } 987 if (ml_tdm_port_slots_info[outer_port].position == -1) { 988 continue; 989 } 990 head = current = &ml_tdm_port_slots_info[outer_port]; 991 do { 992 for(loop=0;loop<ML_MAX_PORTS_PER_BLOCK; loop++) { 993 inner_port=(*ml_block_ports[unit])[mxqblock][loop]; 994 if (inner_port == 0xFF) { 995 if ((mxqblock == 7) && (loop == 3)) { 996 inner_port = 40; 997 } else { 998 continue; 999 } 1000 } 1001 if ( inner_port == outer_port) { 1002 continue; 1003 } 1004 if (ml_tdm_port_slots_info[inner_port].position == -1) { 1005 continue; 1006 } 1007 head1 = current1 = &ml_tdm_port_slots_info[inner_port]; 1008 do { 1009 spacing = (current->position - current1->position) > 0 ? 1010 (current->position - current1->position)-1: 1011 (total_tdm_slots - current1->position + 1012 current->position) - 1; 1013 if (spacing < 3) { 1014 LOG_ERROR(BSL_LS_SOC_COMMON, 1015 (BSL_META_U(unit, 1016 "Outer Port:%d Inner Port:%d " 1017 "MXQSpacing Issue" 1018 "Expected > 4 but observed %d\n"), 1019 outer_port,inner_port,spacing)); 1020 rv = SOC_E_CONFIG; 1021 *offender_port=outer_port; 1022 continue; 1023 } 1024 current1 = current1->next; 1025 } while ((current1 !=head1) && (rv == SOC_E_NONE)); 1026 } 1027 current = current->next; 1028 } while ((current !=head) && (rv == SOC_E_NONE)); 1029 } 1030 } 1031 1032 /* Free allocated resources */ 1033 count=0; 1034 for (port=0;port < ML_MAX_LOGICAL_PORTS ; port++) { 1035 head = current = &ml_tdm_port_slots_info[port]; 1036 do { 1037 temp = current->next; 1038 if (current != head) { 1039 count++; 1040 LOG_VERBOSE(BSL_LS_SOC_COMMON, 1041 (BSL_META_U(unit, 1042 "Freed count :%d\n"),count)); 1043 sal_free(current); 1044 } 1045 current = temp; 1046 } while (current != head); 1047 ml_tdm_port_slots_info[port].prev=NULL; 1048 ml_tdm_port_slots_info[port].next=NULL; 1049 ml_tdm_port_slots_info[port].position = -1; 1050 } 1051 sal_memcpy(&ml_current_tdm_cycles_info, 1052 &ml_tdm_cycles_info[tdm_freq_index][0], 1053 sizeof(tdm_cycles_info_t)*KT2_MAX_SPEEDS); 1054 return rv; 1055 return SOC_E_NONE; 1056 } 1057 #endif 1058 1059 #ifdef BCM_WARM_BOOT_SUPPORT 1060 1061 uint32 *iarb_tdm_ml[SOC_MAX_NUM_DEVICES]; 1062 1063 int soc_ml_retrieve_hw_tdm(int unit) 1064 { 1065 uint32 rval = 0; 1066 uint8 tdm_no = 0; 1067 soc_mem_t tdm_table[]={IARB_TDM_TABLEm , IARB_TDM_TABLE_1m}; 1068 iarb_tdm_table_entry_t iarb_tdm_entry; 1069 uint32 num_iarb_entry = 0, iarb_size=0; 1070 int index = 0; 1071 1072 SOC_IF_ERROR_RETURN(READ_IARB_TDM_CONTROLr(unit, &rval)); 1073 tdm_no = soc_reg_field_get(unit, IARB_TDM_CONTROLr, rval, SELECT_TDMf); 1074 1075 /* Allocate memory for TDM. Get size from IARB table. */ 1076 num_iarb_entry = soc_mem_index_count(unit,IARB_TDM_TABLEm); 1077 iarb_size = num_iarb_entry * sizeof(iarb_tdm_table_entry_t); 1078 1079 if(iarb_tdm_ml[unit] != NULL) { 1080 sal_free(iarb_tdm_ml[unit]); 1081 iarb_tdm_ml[unit] = NULL; 1082 } 1083 iarb_tdm_ml[unit] = sal_alloc(iarb_size, "iarb_tdm_ml"); 1084 if (iarb_tdm_ml[unit] == NULL) { 1085 return SOC_E_MEMORY; 1086 } 1087 sal_memset(iarb_tdm_ml[unit], 0, iarb_size); 1088 1089 for (index = 0; index < num_iarb_entry; index++) { 1090 SOC_IF_ERROR_RETURN(soc_mem_read(unit, tdm_table[tdm_no], SOC_BLOCK_ALL, 1091 index, &iarb_tdm_entry)); 1092 iarb_tdm_ml[unit][index] = soc_mem_field32_get(unit, tdm_table[tdm_no], 1093 &iarb_tdm_entry, PORT_NUMf); 1094 } 1095 return SOC_E_NONE; 1096 } 1097 1098 1099 /* Functions related to flexio scache */ 1100 int _soc_ml_flexio_scache_allocate(int unit) 1101 { 1102 int rv=SOC_E_NONE; 1103 uint8 *flexio_scache_ptr; 1104 soc_scache_handle_t scache_handle; 1105 uint32 alloc_get=0; 1106 uint32 alloc_size = sizeof(scache_begin_magic_number) + 1107 sizeof(ml_scache_tdm_info) + 1108 sizeof(ml_scache_tdm) + 1109 sizeof(ml_scache_speed) + 1110 sizeof(ml_port_speeds_scache) + 1111 sizeof(ml_scache_port_details) + 1112 sizeof(scache_end_magic_number); 1113 1114 SOC_SCACHE_HANDLE_SET(scache_handle, unit, SOC_SCACHE_FLEXIO_HANDLE, 1115 BCM_FLEXIO_SCACHE_DEFAULT_PARTITION); 1116 1117 rv = soc_scache_alloc(unit, scache_handle, alloc_size); 1118 if (rv == SOC_E_CONFIG) { 1119 /* Probably Level1 */ 1120 return SOC_E_NONE; 1121 } 1122 1123 /* NotRequired but just to confirm Get the pointer for the Level 2 cache */ 1124 SOC_IF_ERROR_RETURN(soc_scache_ptr_get(unit, scache_handle, 1125 &flexio_scache_ptr, &alloc_get)); 1126 1127 if (alloc_get != alloc_size) { 1128 /* Expected size doesn't match retrieved size */ 1129 return SOC_E_INTERNAL; 1130 } 1131 if (NULL == flexio_scache_ptr) { 1132 return SOC_E_MEMORY; 1133 } 1134 1135 LOG_VERBOSE(BSL_LS_SOC_COMMON, 1136 (BSL_META_U(unit, 1137 "%s()[LINE:%d] DONE \n"),FUNCTION_NAME(), __LINE__)); 1138 return SOC_E_NONE; 1139 } 1140 1141 int _soc_ml_flexio_scache_retrieve(int unit) 1142 { 1143 int rv; 1144 uint8 *flexio_scache_ptr; 1145 soc_scache_handle_t scache_handle; 1146 uint32 alloc_get=0; 1147 1148 uint32 alloc_size = sizeof(ml_scache_tdm_info) + 1149 sizeof(ml_scache_tdm) + 1150 sizeof(ml_scache_speed) + 1151 sizeof(ml_port_speeds_scache) + 1152 sizeof(ml_scache_port_details) + 1153 SOC_WB_SCACHE_CONTROL_SIZE; 1154 uint32 scache_offset=0; 1155 uint16 default_ver = BCM_WB_DEFAULT_VERSION; 1156 uint16 recovered_ver; 1157 1158 SOC_SCACHE_HANDLE_SET(scache_handle, unit, SOC_SCACHE_FLEXIO_HANDLE, 1159 BCM_FLEXIO_SCACHE_DEFAULT_PARTITION); 1160 1161 rv = soc_scache_ptr_get(unit, scache_handle, 1162 &flexio_scache_ptr, &alloc_get); 1163 if (rv == SOC_E_NOT_FOUND) { 1164 /* Partition 1 is not available, fall back to old retrieve procedure*/ 1165 SOC_IF_ERROR_RETURN(_soc_ml_flexio_scache_retrieve_part0(unit)); 1166 return SOC_E_NONE; 1167 } 1168 1169 if (alloc_get != (alloc_size + SOC_WB_SCACHE_CONTROL_SIZE)) { 1170 /* Expected size doesn't match retrieved size */ 1171 return SOC_E_INTERNAL; 1172 } 1173 1174 /* Partition 1 is found. So Extract sync-ed details */ 1175 scache_offset = 0; 1176 sal_memcpy(&recovered_ver, 1177 &flexio_scache_ptr[scache_offset], sizeof(uint16)); 1178 1179 if( default_ver > recovered_ver ) { 1180 LOG_VERBOSE(BSL_LS_SOC_COMMON, 1181 (BSL_META_U(unit, "Scache Upgraded.\n"))); 1182 } 1183 1184 scache_offset += SOC_WB_SCACHE_CONTROL_SIZE; 1185 sal_memcpy(&ml_scache_tdm_info, 1186 &flexio_scache_ptr[scache_offset], sizeof(ml_scache_tdm_info)); 1187 1188 bcm56270_tdm_info[COUNTOF(bcm56270_tdm_info)-1] = ml_scache_tdm_info; 1189 1190 scache_offset += sizeof(ml_scache_tdm_info); 1191 sal_memcpy(&ml_scache_tdm, 1192 &flexio_scache_ptr[scache_offset], sizeof(ml_scache_tdm)); 1193 1194 scache_offset += sizeof(ml_scache_tdm); 1195 sal_memcpy(&ml_scache_speed, 1196 &flexio_scache_ptr[scache_offset], sizeof(ml_scache_speed)); 1197 1198 scache_offset += sizeof(ml_scache_speed); 1199 1200 sal_memcpy(&ml_port_speeds_scache, 1201 &flexio_scache_ptr[scache_offset], sizeof(ml_port_speeds_scache)); 1202 1203 scache_offset += sizeof(ml_port_speeds_scache); 1204 1205 sal_memcpy(&ml_scache_port_details, 1206 &flexio_scache_ptr[scache_offset], 1207 sizeof(ml_scache_port_details)); 1208 scache_offset += sizeof(ml_scache_port_details); 1209 1210 LOG_VERBOSE(BSL_LS_SOC_COMMON, 1211 (BSL_META_U(unit, 1212 "%s()[LINE:%d] \n"),FUNCTION_NAME(), __LINE__)); 1213 return SOC_E_NONE; 1214 } 1215 1216 1217 int _soc_ml_flexio_scache_retrieve_part0(int unit) 1218 { 1219 int rv; 1220 uint8 *flexio_scache_ptr; 1221 soc_scache_handle_t scache_handle; 1222 uint32 alloc_get=0; 1223 uint32 alloc_size = sizeof(scache_begin_magic_number) + 1224 sizeof(ml_scache_tdm_info) + 1225 sizeof(ml_scache_tdm) + 1226 sizeof(ml_scache_speed) + 1227 sizeof(ml_port_speeds_scache) + 1228 sizeof(ml_scache_port_details) + 1229 sizeof(scache_end_magic_number); 1230 uint32 scache_offset=0; 1231 1232 SOC_SCACHE_HANDLE_SET(scache_handle, unit, SOC_SCACHE_FLEXIO_HANDLE, 0); 1233 1234 /* NotRequired but just to confirm Get the pointer for the Level 2 cache */ 1235 rv = soc_scache_ptr_get(unit, scache_handle, 1236 &flexio_scache_ptr, &alloc_get); 1237 if (rv == SOC_E_NOT_FOUND) { 1238 /* Probably Level1 */ 1239 return SOC_E_NONE; 1240 } 1241 1242 if (alloc_get != (alloc_size + SOC_WB_SCACHE_CONTROL_SIZE)) { 1243 /* Expected size doesn't match retrieved size */ 1244 return SOC_E_INTERNAL; 1245 } 1246 1247 if (NULL == flexio_scache_ptr) { 1248 return SOC_E_MEMORY; 1249 } 1250 1251 scache_offset = 0; 1252 if(sal_memcmp(&flexio_scache_ptr[scache_offset], 1253 &scache_begin_magic_number[0], 1254 sizeof(scache_begin_magic_number)) != 0) { 1255 LOG_CLI((BSL_META_U(unit, 1256 "Corrupt scache for flexio operation \n"))); 1257 return SOC_E_INTERNAL; 1258 } 1259 1260 scache_offset += sizeof(scache_begin_magic_number); 1261 sal_memcpy(&ml_scache_tdm_info, 1262 &flexio_scache_ptr[scache_offset], sizeof(ml_scache_tdm_info)); 1263 1264 bcm56270_tdm_info[COUNTOF(bcm56270_tdm_info)-1] = ml_scache_tdm_info; 1265 1266 scache_offset += sizeof(ml_scache_tdm_info); 1267 1268 /* 1269 * Part 0 Version has an issue in TDM sync. 1270 * So in part 0 version, Level 1 recovery performed to retrieve TDM. 1271 */ 1272 LOG_INFO(BSL_LS_SOC_COMMON, 1273 (BSL_META_U(unit, 1274 "Previous ver was synced with incorrect TDM," 1275 "Now LEVEL 1 recovery for TDM\n"))); 1276 1277 SOC_IF_ERROR_RETURN(soc_ml_retrieve_hw_tdm(unit)); 1278 if(iarb_tdm_ml[unit] == NULL) { 1279 return SOC_E_INTERNAL; 1280 } 1281 1282 sal_memcpy(&ml_scache_tdm, iarb_tdm_ml[unit], sizeof(ml_scache_tdm)); 1283 1284 kt2_tdm_display(unit, (uint32 *) (&ml_scache_tdm[0]), 1285 ml_scache_tdm_info.tdm_size, 1286 ml_scache_tdm_info.row, 1287 ml_scache_tdm_info.col); 1288 1289 scache_offset += sizeof(ml_scache_tdm); 1290 sal_memcpy(&ml_scache_speed, 1291 &flexio_scache_ptr[scache_offset], sizeof(ml_scache_speed)); 1292 1293 scache_offset += sizeof(ml_scache_speed); 1294 1295 sal_memcpy(&ml_port_speeds_scache, 1296 &flexio_scache_ptr[scache_offset], sizeof(ml_port_speeds_scache)); 1297 1298 scache_offset += sizeof(ml_port_speeds_scache); 1299 1300 sal_memcpy(&ml_scache_port_details, 1301 &flexio_scache_ptr[scache_offset], 1302 sizeof(ml_scache_port_details)); 1303 scache_offset += sizeof(ml_scache_port_details); 1304 1305 if (sal_memcmp(&flexio_scache_ptr[scache_offset], 1306 &scache_end_magic_number[0], 1307 sizeof(scache_end_magic_number)) != 0) { 1308 LOG_CLI((BSL_META_U(unit, 1309 "Corrupt scache for flexio operation \n"))); 1310 return SOC_E_INTERNAL; 1311 } 1312 1313 /* Allocate SCACHE at part 1 Now */ 1314 SOC_IF_ERROR_RETURN(_soc_ml_flexio_scache_allocate(unit)); 1315 1316 LOG_VERBOSE(BSL_LS_SOC_COMMON, 1317 (BSL_META_U(unit, 1318 "%s()[LINE:%d] \n"),FUNCTION_NAME(), __LINE__)); 1319 1320 return SOC_E_NONE; 1321 } 1322 1323 int _soc_ml_flexio_scache_sync(int unit) 1324 { 1325 int rv; 1326 uint8 *flexio_scache_ptr; 1327 soc_scache_handle_t scache_handle; 1328 uint32 alloc_get=0; 1329 uint32 alloc_size = sizeof(ml_scache_tdm_info) + 1330 sizeof(ml_scache_tdm) + 1331 sizeof(ml_scache_speed) + 1332 sizeof(ml_port_speeds_scache) + 1333 sizeof(ml_scache_port_details) + 1334 SOC_WB_SCACHE_CONTROL_SIZE; 1335 uint32 scache_offset=0; 1336 int cfg_num=0; 1337 uint32 port=0; 1338 uint16 default_ver = BCM_WB_DEFAULT_VERSION; 1339 1340 SOC_SCACHE_HANDLE_SET(scache_handle, unit, SOC_SCACHE_FLEXIO_HANDLE, 1341 BCM_FLEXIO_SCACHE_DEFAULT_PARTITION); 1342 1343 /* NotRequired but just to confirm Get the pointer for the Level 2 cache */ 1344 rv = soc_scache_ptr_get(unit, scache_handle, 1345 &flexio_scache_ptr, &alloc_get); 1346 if (rv == SOC_E_NOT_FOUND) { 1347 /* Probably Level1 */ 1348 return SOC_E_NONE; 1349 } 1350 if (alloc_get != (alloc_size + SOC_WB_SCACHE_CONTROL_SIZE)) { 1351 /* Expected size doesn't match retrieved size */ 1352 return SOC_E_INTERNAL; 1353 } 1354 if (NULL == flexio_scache_ptr) { 1355 return SOC_E_MEMORY; 1356 } 1357 1358 SOC_IF_ERROR_RETURN(_soc_metrolite_get_cfg_num(unit, 0, &cfg_num)); 1359 1360 scache_offset = 0; 1361 sal_memcpy(&flexio_scache_ptr[scache_offset], 1362 &default_ver, sizeof(uint16)); 1363 1364 scache_offset += SOC_WB_SCACHE_CONTROL_SIZE; 1365 sal_memcpy(&flexio_scache_ptr[scache_offset], 1366 &bcm56270_tdm_info[cfg_num], 1367 sizeof(ml_scache_tdm_info)); 1368 1369 scache_offset += sizeof(ml_scache_tdm_info); 1370 sal_memcpy(&flexio_scache_ptr[scache_offset], 1371 &ml_current_tdm[0], 1372 sizeof(uint32)* bcm56270_tdm_info[cfg_num].tdm_size); 1373 1374 scache_offset += sizeof(ml_scache_tdm); 1375 1376 for (port=1 ; port <= ML_MAX_PHYSICAL_PORTS ; port++) { 1377 ml_scache_speed[port-1] = 0; 1378 /* mxqblock = (*kt2_port_to_mxqblock[unit])[port-1]; */ 1379 ml_scache_port_details[port-1].start_port_no = port; 1380 ml_scache_port_details[port-1].end_port_no = port; 1381 ml_scache_port_details[port-1].port_incr = 1; 1382 ml_scache_port_details[port-1].port_type = 0; 1383 ml_scache_port_details[port-1].port_speed = 0xFFFF; 1384 1385 if (IS_MXQ_PORT(unit,port)) { 1386 if ((bcm56270_speed[unit][cfg_num][port-1] == 0) || /*Converted */ 1387 (bcm56270_speed[unit][cfg_num][port-1] >= 2500)) { 1388 ml_scache_speed[port - 1] = 2500; 1389 ml_scache_port_details[port-1].port_speed = 2500; 1390 } else { 1391 ml_scache_speed[port - 1] = 1000; 1392 ml_scache_port_details[port-1].port_speed = 1000; 1393 } 1394 ml_scache_port_details[port-1].port_type = GE_PORT; 1395 } 1396 1397 if (IS_XE_PORT(unit,port)) { 1398 ml_scache_speed[port - 1] = 10000; 1399 ml_scache_port_details[port-1].port_speed = 10000; 1400 ml_scache_port_details[port-1].port_type |= XE_PORT; 1401 if (IS_MXQ_PORT(unit,port)) { 1402 ml_scache_port_details[port-1].port_incr = 4; 1403 } 1404 } 1405 1406 if (IS_HG_PORT(unit,port)) { 1407 ml_scache_speed[port - 1] = 10000; 1408 ml_scache_port_details[port-1].port_speed = 10000; 1409 ml_scache_port_details[port-1].port_type |= HG_PORT; 1410 ml_scache_port_details[port-1].port_type |= STK_PORT; 1411 } 1412 1413 if (IS_XL_PORT(unit, port) && (IS_GE_PORT(unit, port))) { 1414 if (bcm56270_speed[unit][cfg_num][port-1] >= 2500) { 1415 ml_scache_speed[port - 1] = 2500; 1416 ml_scache_port_details[port-1].port_speed = 2500; 1417 } else { 1418 ml_scache_speed[port - 1] = 1000; 1419 ml_scache_port_details[port-1].port_speed = 1000; 1420 } 1421 ml_scache_port_details[port-1].port_type |= GE_PORT; 1422 } 1423 } 1424 1425 sal_memcpy(&flexio_scache_ptr[scache_offset], 1426 &ml_scache_speed, sizeof(ml_scache_speed)); 1427 scache_offset += sizeof(ml_scache_speed); 1428 1429 sal_memcpy(&flexio_scache_ptr[scache_offset], 1430 ml_port_speeds_s[cfg_num], sizeof(ml_port_speeds_scache)); 1431 scache_offset += sizeof(ml_port_speeds_scache); 1432 1433 sal_memcpy(&flexio_scache_ptr[scache_offset], 1434 &ml_scache_port_details, 1435 sizeof(ml_scache_port_details)); 1436 LOG_VERBOSE(BSL_LS_SOC_COMMON, 1437 (BSL_META_U(unit, 1438 "%s()[LINE:%d] \n"),FUNCTION_NAME(), __LINE__)); 1439 return SOC_E_NONE; 1440 } 1441 #endif /* end of BCM_WARM_BOOT_SUPPORT */ 1442 1443 void soc_metrolite_save_tdm_pos(int unit, uint32 new_tdm_size,uint32 *new_tdm) { 1444 uint32 pos=0; 1445 uint8 port=0; 1446 uint8 block=0; 1447 uint8 total_slots=0; 1448 1449 sal_memset(ml_tdm_pos_info,0,sizeof(ml_tdm_pos_info)); 1450 for (pos = 0; pos < new_tdm_size ; pos++) { 1451 port= new_tdm[pos]; 1452 if ((port == ML_IDLE) || (port == ML_LPBK) || 1453 (port == ML_CMIC)) { 1454 continue; 1455 } 1456 if(port > ML_MAX_PHYSICAL_PORTS ) { 1457 LOG_ERROR(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 1458 "tdm_size %d, pos %d, port %d \n"), 1459 new_tdm_size, pos, port)); 1460 1461 } else { 1462 block = (*ml_port_to_block[unit])[port - 1]; 1463 total_slots = ml_tdm_pos_info[block].total_slots; 1464 ml_tdm_pos_info[block].pos[total_slots]=pos; 1465 ml_tdm_pos_info[block].total_slots++; 1466 } 1467 } 1468 1469 sal_memcpy(ml_current_tdm,new_tdm,new_tdm_size*sizeof(new_tdm[0])); 1470 ml_current_tdm_size=new_tdm_size; 1471 1472 } 1473 1474 /* This function splits the occurance of first port of the block into 4 ports */ 1475 /* Make sure that the tdm of the block is not already split */ 1476 void ml_block_tdm_split(int unit, uint32 *tdm, 1477 uint32 total_tdm_slots, uint32 block) 1478 { 1479 uint32 index=0, count=0; 1480 uint32 first_port; 1481 1482 first_port = (*ml_block_ports[unit])[block][0]; 1483 for (index=0; index < total_tdm_slots ; index++ ) { 1484 /* Split first port occurance in to 4 */ 1485 if (tdm[index] == first_port) { 1486 tdm[index] = first_port + (count % 4); 1487 count++; 1488 } 1489 1490 } 1491 } 1492 1493 void ml_tdm_replace(uint32 *tdm, uint32 total_tdm_slots, 1494 uint32 src, uint32 dst,uint32 one_time) 1495 { 1496 uint32 index=0; 1497 for (index=0; index < total_tdm_slots ; index++ ) { 1498 if (tdm[index] == src) { 1499 tdm[index] = dst; 1500 if (one_time) { 1501 break; 1502 } 1503 } 1504 } 1505 } 1506 1507 void ml_tdm_swap(uint32 *tdm, uint32 total_tdm_slots, 1508 uint32 src, uint32 dst) 1509 { 1510 uint32 index=0; 1511 uint32 temp_index=0; 1512 uint32 temp=0; 1513 for (index=0; index < total_tdm_slots ; index++ ) { 1514 if (tdm[index] == src) { 1515 temp_index=index; 1516 } 1517 if (tdm[index] == dst) { 1518 temp = tdm[temp_index]; 1519 tdm[temp_index]=dst; 1520 tdm[index]=temp; 1521 } 1522 } 1523 } 1524 1525 soc_error_t 1526 soc_metrolite_reconfigure_tdm(int unit,uint32 new_tdm_size,uint32 *new_tdm) 1527 { 1528 uint8 new_tdm_no=0; 1529 soc_mem_t tdm_table[]={IARB_TDM_TABLEm , IARB_TDM_TABLE_1m}; 1530 soc_field_t wrap_ptr[]={TDM_WRAP_PTRf , TDM_1_WRAP_PTRf}; 1531 uint32 lls_tdm_size=0; 1532 lls_port_tdm_entry_t *lls_tdm=NULL; 1533 uint32 iarb_size=0; 1534 iarb_tdm_table_entry_t *iarb_tdm=NULL; 1535 int iter=0; 1536 uint32 index; 1537 uint32 rval; 1538 int cfg_num; 1539 1540 SOC_IF_ERROR_RETURN(_soc_metrolite_get_cfg_num(unit, 0, &cfg_num)); 1541 if (cfg_num >= (sizeof(bcm56270_tdm)/sizeof(bcm56270_tdm[0]))) { 1542 return SOC_E_FAIL; 1543 } 1544 1545 SOC_IF_ERROR_RETURN(READ_IARB_TDM_CONTROLr(unit, &rval)); 1546 old_tdm_no = soc_reg_field_get(unit, IARB_TDM_CONTROLr, rval, SELECT_TDMf); 1547 new_tdm_no = (old_tdm_no + 1)%2; 1548 1549 iarb_size = soc_mem_index_count(unit,IARB_TDM_TABLEm) * 1550 sizeof(iarb_tdm_table_entry_t); 1551 iarb_tdm = soc_cm_salloc(unit,iarb_size, "iarb_tdm_table_entry_t"); 1552 if (iarb_tdm == NULL) { 1553 return SOC_E_MEMORY; 1554 } 1555 sal_memset(iarb_tdm,0,iarb_size); 1556 1557 lls_tdm_size = soc_mem_index_count(unit,LLS_PORT_TDMm) * 1558 sizeof(lls_port_tdm_entry_t); 1559 lls_tdm = soc_cm_salloc(unit,lls_tdm_size, "lls_port_tdm_entry_t"); 1560 if (lls_tdm == NULL) { 1561 soc_cm_sfree(unit,iarb_tdm); 1562 return SOC_E_MEMORY; 1563 } 1564 sal_memset(lls_tdm,0,lls_tdm_size); 1565 1566 for (index = 0; index < new_tdm_size; index++) { 1567 soc_IARB_TDM_TABLEm_field32_set(unit, &iarb_tdm[index], PORT_NUMf, 1568 new_tdm[index]); 1569 } 1570 soc_mem_write_range(unit, tdm_table[new_tdm_no], MEM_BLOCK_ALL, 0, 1571 new_tdm_size, iarb_tdm); 1572 soc_cm_sfree(unit,iarb_tdm); 1573 1574 for (index = 0; index < new_tdm_size/2; index++) { 1575 soc_LLS_PORT_TDMm_field32_set(unit, &lls_tdm[index], 1576 PORT_ID_0f, new_tdm[index*2]); 1577 if ( new_tdm[index*2] < ML_IDLE ) { 1578 soc_LLS_PORT_TDMm_field32_set(unit, &lls_tdm[index], 1579 PORT_ID_0_ENABLEf, 1); 1580 } else { 1581 LOG_VERBOSE(BSL_LS_SOC_COMMON, 1582 (BSL_META_U(unit, 1583 "IDLE SLOTs so PORT_ID_0_ENABLEf=0 \ 1584 for index=%d\n"), index)); 1585 soc_LLS_PORT_TDMm_field32_set(unit, &lls_tdm[index], 1586 PORT_ID_0_ENABLEf, 0); 1587 } 1588 1589 soc_LLS_PORT_TDMm_field32_set(unit, &lls_tdm[index], 1590 PORT_ID_1f, new_tdm[(index*2) + 1]); 1591 if ( new_tdm[(index*2)+1] < ML_IDLE ) { 1592 soc_LLS_PORT_TDMm_field32_set(unit, &lls_tdm[index], 1593 PORT_ID_1_ENABLEf, 1); 1594 } else { 1595 LOG_VERBOSE(BSL_LS_SOC_COMMON, 1596 (BSL_META_U(unit, 1597 "IDLE SLOTs so PORT_ID_1_ENABLEf=0 \ 1598 for index=%d\n"), index)); 1599 soc_LLS_PORT_TDMm_field32_set(unit, &lls_tdm[index], 1600 PORT_ID_1_ENABLEf, 0); 1601 } 1602 } /* for index */ 1603 1604 if (new_tdm_size % 2) { 1605 LOG_CLI((BSL_META_U(unit, 1606 "ODD TDM SIZE \n"))); 1607 soc_LLS_PORT_TDMm_field32_set(unit, &lls_tdm[index*2], 1608 PORT_ID_0_ENABLEf, 1); 1609 soc_LLS_PORT_TDMm_field32_set(unit, &lls_tdm[index*2], 1610 PORT_ID_0f, new_tdm[(index*2)]); 1611 soc_LLS_PORT_TDMm_field32_set(unit, &lls_tdm[(index*2)+1], 1612 PORT_ID_1_ENABLEf, 0); 1613 soc_LLS_PORT_TDMm_field32_set(unit, &lls_tdm[(index*2)+1], 1614 PORT_ID_1f, 0); 1615 index++; 1616 } 1617 1618 soc_mem_write_range(unit, LLS_PORT_TDMm, MEM_BLOCK_ALL, 1619 new_tdm_no*256, (new_tdm_no*256) + index, 1620 lls_tdm); 1621 soc_cm_sfree(unit,lls_tdm); 1622 1623 SOC_IF_ERROR_RETURN(READ_IARB_TDM_CONTROLr(unit, &rval)); 1624 soc_reg_field_set(unit, IARB_TDM_CONTROLr, &rval, DISABLEf, 0); 1625 soc_reg_field_set(unit, IARB_TDM_CONTROLr, &rval, 1626 wrap_ptr[new_tdm_no],new_tdm_size -1); 1627 soc_reg_field_set(unit, IARB_TDM_CONTROLr, &rval, SELECT_TDMf, new_tdm_no); 1628 SOC_IF_ERROR_RETURN(WRITE_IARB_TDM_CONTROLr(unit, rval)); 1629 1630 if (bsl_check(bslLayerSoc, bslSourceCommon, bslSeverityVerbose, unit)) { 1631 kt2_tdm_display(unit,new_tdm,new_tdm_size, 1632 bcm56270_tdm_info[cfg_num].row, 1633 bcm56270_tdm_info[cfg_num].col); 1634 } 1635 1636 SOC_IF_ERROR_RETURN(WRITE_LLS_TDM_CAL_CFG_SWITCHr(unit, 1)); 1637 if ((SAL_BOOT_BCMSIM || SAL_BOOT_PLISIM)) { 1638 SOC_IF_ERROR_RETURN(READ_LLS_TDM_CAL_CFGr(unit, &rval)); 1639 soc_reg_field_set(unit, LLS_TDM_CAL_CFGr, &rval, 1640 CURRENT_CALENDARf,new_tdm_no); 1641 SOC_IF_ERROR_RETURN(WRITE_LLS_TDM_CAL_CFGr(unit, rval)); 1642 } 1643 1644 do { 1645 SOC_IF_ERROR_RETURN(READ_LLS_TDM_CAL_CFGr(unit, &rval)); 1646 sal_udelay(100); 1647 if (soc_reg_field_get(unit, LLS_TDM_CAL_CFGr, rval, 1648 CURRENT_CALENDARf) == new_tdm_no) { 1649 break; 1650 } 1651 } while (iter++ < 100000); 1652 1653 if (iter >= 100000) { 1654 LOG_ERROR(BSL_LS_SOC_COMMON, 1655 (BSL_META_U(unit, "LLS Calendar switch failed !!\n"))); 1656 return SOC_E_INTERNAL; 1657 } 1658 1659 old_tdm_no = new_tdm_no; 1660 soc_metrolite_save_tdm_pos(unit, new_tdm_size,new_tdm); 1661 1662 return SOC_E_NONE; 1663 } 1664 #if 0 1665 soc_error_t ml_tdm_verify(int unit, 1666 uint32 *tdm, 1667 uint32 total_tdm_slots, 1668 uint32 tdm_freq, /* In MHHz */ 1669 uint32 *port_speed, 1670 uint32 lpbk_port_speed, 1671 uint32 *offender_port) 1672 { 1673 /* Following rules need to be met */ 1674 /* Rule1 : Each Loopback port need 2.5G bandwidth */ 1675 /* Rule2 : Each CMIC port need 2G bandwidth */ 1676 /* Rule3 : Loopback (LPBK) ports require min 3 cycle spacing among LPBK or 1677 CMIC ports */ 1678 /* Rule4 : Each subport in MXQPORT operates with 4 cycle TDM */ 1679 /* Rule5 : Each 10G-XAUI ports should be able to operate in 4x2.5G with 4 1680 slots allocated to each subport from the same MXQPORT */ 1681 soc_error_t rv=SOC_E_NONE; 1682 uint32 index=0; 1683 uint32 expected_tdm_cycles_min=0; 1684 uint32 expected_tdm_cycles_max=0; 1685 uint32 tdm_freq_index=0; 1686 uint32 speed_index=0; 1687 uint32 port=0; 1688 uint32 speed=0; 1689 uint32 worse_tdm_slot_spacing=0; 1690 uint32 prev_tdm_slot_spacing=0; 1691 uint32 next_tdm_slot_spacing=0; 1692 #if 0 1693 uint32 tdm_slot_spacing=0; 1694 #endif 1695 uint32 min_tdm_cycles=0; /* To Meet BW */ 1696 uint32 count=0; 1697 uint32 skip_count=0; 1698 uint32 mxqblock=0; 1699 uint32 outer_port=0; 1700 uint32 inner_port=0; 1701 uint32 spacing=0; 1702 uint32 loop=0; 1703 tdm_port_slots_info_t *head=NULL; 1704 tdm_port_slots_info_t *head1=NULL; 1705 tdm_port_slots_info_t *current=NULL; 1706 tdm_port_slots_info_t *current1=NULL; 1707 tdm_port_slots_info_t *prev = NULL; 1708 tdm_port_slots_info_t *temp=NULL; 1709 uint32 idle_flag=0; 1710 uint32 idle_rule=0; 1711 char base_tdm_str[80]; 1712 1713 /* Possible TDM frequencies 1714 80MHz(16Cycles) ,120MHz(20Cycles),155MHz(84Cycles), 1715 185MHz(80Cycles),185MHz(90Cycles) 1716 */ 1717 switch(tdm_freq) { 1718 case 130: 1719 if (total_tdm_slots == 284) { 1720 /*TDM_A : 0:130MHz: 284 (41 * 7) Cycles Used */ 1721 sal_strncpy(base_tdm_str, 1722 "TDM_A : 0:130MHz: 284 (41 * 7) Cycles Used", 1723 79); 1724 tdm_freq_index=0; 1725 expected_tdm_cycles_min=284; 1726 expected_tdm_cycles_max=284; 1727 } else if (total_tdm_slots == 141) { 1728 /*TDM_C,C1,C2: 7:130MHz: 141 (21 * 6) Cycles Used */ 1729 sal_strncpy(base_tdm_str, 1730 "TDM_AA,TDM_C,C1,C2: 7:130MHz:141 (21 * 6) Cycles Used", 1731 79); 1732 tdm_freq_index=7; 1733 expected_tdm_cycles_min=141; 1734 expected_tdm_cycles_max=141; 1735 } else if (total_tdm_slots == 168) { 1736 /*TDM_D: 8:130MHz: 168 (28 * 6) Cycles Used */ 1737 sal_strncpy(base_tdm_str, 1738 "TDM_D: 8:130MHz: 168 (28 * 6) Cycles Used", 1739 79); 1740 tdm_freq_index=8; 1741 expected_tdm_cycles_min=168; 1742 expected_tdm_cycles_max=168; 1743 } else { 1744 LOG_ERROR(BSL_LS_SOC_COMMON, 1745 (BSL_META_U(unit, 1746 "Unsupported tdm slots:%d\n"), 1747 total_tdm_slots)); 1748 return SOC_E_FAIL; 1749 } 1750 break; 1751 case 24: 1752 /*TDM_A1: 2:24MHz: 13 (4 * 4) Cycles Used */ 1753 sal_strncpy(base_tdm_str, 1754 "TDM_A1: 2:24MHz: 13 (4 * 4) Cycles Used ", 1755 79); 1756 tdm_freq_index=2; 1757 expected_tdm_cycles_min=13; 1758 expected_tdm_cycles_max=13; 1759 break; 1760 case 37: 1761 /*TDM_A1A: 3:37MHz: 84 (21 * 4) Cycles Used */ 1762 sal_strncpy(base_tdm_str, 1763 "TDM_A1A: 3:37MHz: 84 (21 * 4) Cycles Used ", 1764 79); 1765 tdm_freq_index=3; 1766 expected_tdm_cycles_min=84; 1767 expected_tdm_cycles_max=84; 1768 break; 1769 case 118: 1770 if (total_tdm_slots == 133) { 1771 /*TDM_B: 4:118MHz: 133 (23 * 6) Cycles Used */ 1772 sal_strncpy(base_tdm_str, 1773 "TDM_B: 4:118MHz: 133 (23 * 6) Cycles Used ", 1774 79); 1775 tdm_freq_index=4; 1776 expected_tdm_cycles_min=133; 1777 expected_tdm_cycles_max=133; 1778 } else if (total_tdm_slots == 120) { 1779 /*TDM_B1: 5:118MHz: 120 (20 * 6) Cycles Used */ 1780 sal_strncpy(base_tdm_str, 1781 "TDM_B1: 5:118MHz: 120 (20 * 6) Cycles Used ", 1782 79); 1783 tdm_freq_index=5; 1784 expected_tdm_cycles_min=120; 1785 expected_tdm_cycles_max=120; 1786 } else if (total_tdm_slots == 121) { 1787 /*TDM_B1A: 6:118MHz: 121 (21 * 6) Cycles Used */ 1788 sal_strncpy(base_tdm_str, 1789 "TDM_B1A: 6:118MHz: 121 (21 * 6) Cycles Used ", 1790 79); 1791 tdm_freq_index=6; 1792 expected_tdm_cycles_min=121; 1793 expected_tdm_cycles_max=121; 1794 } else { 1795 LOG_ERROR(BSL_LS_SOC_COMMON, 1796 (BSL_META_U(unit, 1797 "Unsupported tdm slots:%d\n"), 1798 total_tdm_slots)); 1799 return SOC_E_FAIL; 1800 } 1801 break; 1802 case 75: 1803 if (total_tdm_slots == 81) { 1804 /*TDM_E,E1,E3 9:75MHz: 81 (21 * 4) Cycles Used */ 1805 sal_strncpy(base_tdm_str, 1806 "TDM_E,E1,E3 9:75MHz: 81 (21 * 4) Cycles Used ", 1807 79); 1808 tdm_freq_index=9; 1809 expected_tdm_cycles_min=81; 1810 expected_tdm_cycles_max=81; 1811 } else if (total_tdm_slots == 16) { 1812 /*TDM_EA 10:75MHz: 16 (4 * 4) Cycles Used */ 1813 sal_strncpy(base_tdm_str, 1814 "TDM_EA 10:75MHz: 16 (4 * 4) Cycles Used ", 1815 79); 1816 tdm_freq_index=10; 1817 expected_tdm_cycles_min=16; 1818 expected_tdm_cycles_max=16; 1819 } else { 1820 LOG_ERROR(BSL_LS_SOC_COMMON, 1821 (BSL_META_U(unit, 1822 "Unsupported tdm slots:%d\n"), 1823 total_tdm_slots)); 1824 return SOC_E_FAIL; 1825 } 1826 break; 1827 default: 1828 LOG_ERROR(BSL_LS_SOC_COMMON, 1829 (BSL_META_U(unit, 1830 "Unsupported tdm frequency:%d\n"), 1831 tdm_freq)); 1832 return SOC_E_FAIL; 1833 } 1834 LOG_VERBOSE(BSL_LS_SOC_COMMON, 1835 (BSL_META_U(unit, 1836 "\nINFO: BaseTdmStr:%s :Index %d:MinCycles%d:MaxCycle%d\n"), 1837 base_tdm_str, 1838 tdm_freq_index, expected_tdm_cycles_min, expected_tdm_cycles_max)); 1839 if (!((total_tdm_slots >= expected_tdm_cycles_min) && 1840 (total_tdm_slots <= expected_tdm_cycles_max))) { 1841 LOG_ERROR(BSL_LS_SOC_COMMON, 1842 (BSL_META_U(unit, 1843 "Unsupported tdm cycles:%d (min:%d max:%d\n"), 1844 total_tdm_slots, 1845 expected_tdm_cycles_min,expected_tdm_cycles_max)); 1846 return SOC_E_FAIL; 1847 } 1848 1849 idle_flag=0; 1850 idle_rule = 0; 1851 /* Initialize list */ 1852 for (port=0;port < ML_MAX_LOGICAL_PORTS ; port++) { 1853 ml_tdm_port_slots_info[port].prev=&ml_tdm_port_slots_info[port]; 1854 ml_tdm_port_slots_info[port].next=&ml_tdm_port_slots_info[port]; 1855 ml_tdm_port_slots_info[port].position = -1; 1856 } 1857 for (index=0; index < total_tdm_slots; index++) { 1858 if ((tdm[index] == ML_IDLE1) || 1859 (tdm[index] == ML_IDLE)) { 1860 if (tdm[index] == ML_IDLE) { 1861 if (idle_flag == 1) { 1862 idle_rule = 1; 1863 } 1864 idle_flag=1; 1865 } 1866 skip_count++; 1867 continue; 1868 } 1869 if (((index - 1) != 0) && (index != total_tdm_slots - 1) && 1870 (idle_flag == 1) && (idle_rule == 0)) { 1871 LOG_ERROR(BSL_LS_SOC_COMMON, 1872 (BSL_META_U(unit, 1873 "### Internal Error: TDM Verification failed \n" 1874 "### Two consecutive idle not found at position:%d\n" 1875 "### TCAM Atomicity might get affected.\n"), 1876 index - 1)); 1877 *offender_port = ML_IDLE; 1878 return SOC_E_CONFIG; 1879 } 1880 idle_flag=0; 1881 port = tdm[index]; 1882 if (ml_tdm_port_slots_info[port].position == -1) { 1883 /* First Entry */ 1884 ml_tdm_port_slots_info[port].position = index; 1885 skip_count++; 1886 continue; 1887 } 1888 head = current = &ml_tdm_port_slots_info[port]; 1889 while(current->next !=head) { 1890 current = current->next; 1891 } 1892 current->next=sal_alloc(sizeof(tdm_port_slots_info_t),"TDM Pointer"); 1893 count++; 1894 LOG_VERBOSE(BSL_LS_SOC_COMMON, 1895 (BSL_META_U(unit, 1896 "Count=%d SkipCount:%d Port:%d Addr:%p\n"), 1897 count,skip_count,port,(void *)current->next)); 1898 1899 current->next->position=index; 1900 current->next->prev=current; 1901 current->next->next=head; 1902 head->prev=current->next; 1903 } 1904 if (idle_rule == 0) { 1905 /* Special case */ 1906 if (!((tdm[0] == ML_IDLE) && 1907 (tdm[total_tdm_slots-1] == ML_IDLE))) { 1908 LOG_ERROR(BSL_LS_SOC_COMMON, 1909 (BSL_META_U(unit, 1910 "### Internal Error: TDM Verification failed \n" 1911 "### Two consecutive idle not found at Edges \n" 1912 "### TCAM Atomicity might get affected.\n"))); 1913 *offender_port = ML_IDLE1; 1914 return SOC_E_CONFIG; 1915 } 1916 } 1917 LOG_VERBOSE(BSL_LS_SOC_COMMON, 1918 (BSL_META_U(unit, 1919 "Final Count=%d SkipCount:%d\n"),count,skip_count)); 1920 LOG_VERBOSE(BSL_LS_SOC_COMMON, 1921 (BSL_META_U(unit, 1922 "Verifying rule \n"))); 1923 LOG_VERBOSE(BSL_LS_SOC_COMMON, 1924 (BSL_META_U(unit, 1925 "Rule3: Loopback (LPBK) ports require min 3 cycle spacing " 1926 "among LPBK or CMIC ports \n"))); 1927 if (ml_tdm_port_slots_info[ML_LPBK].position == -1) { 1928 LOG_CLI((BSL_META_U(unit, 1929 "Loopback port missing in configuration \n"))); 1930 return SOC_E_FAIL; 1931 } 1932 if (ml_tdm_port_slots_info[ML_CMIC].position == -1) { 1933 LOG_CLI((BSL_META_U(unit, 1934 "CMIC port missing in configuration \n"))); 1935 return SOC_E_FAIL; 1936 } 1937 head = current = &ml_tdm_port_slots_info[ML_LPBK]; 1938 do { 1939 prev = current->prev; 1940 if ( current->position != prev->position ) { 1941 prev_tdm_slot_spacing = 1942 (current->position - prev->position) > 0 ? 1943 (current->position - prev->position)-1: 1944 (total_tdm_slots - prev->position + 1945 current->position) - 1; 1946 next_tdm_slot_spacing = 1947 (current->next->position - current->position) >0 ? 1948 (current->next->position - current->position)-1: 1949 (total_tdm_slots - current->position + 1950 current->next->position) - 1; 1951 if (prev_tdm_slot_spacing < 3) { 1952 LOG_ERROR(BSL_LS_SOC_COMMON, 1953 (BSL_META_U(unit, 1954 "Loopback Ports need min 3 spacing but(prev)found" 1955 "(current:%d , prev:%d)=%d\n"), 1956 current->position,prev->position,prev_tdm_slot_spacing)); 1957 rv = SOC_E_FAIL; 1958 continue; 1959 } 1960 if (next_tdm_slot_spacing < 3) { 1961 LOG_ERROR(BSL_LS_SOC_COMMON, 1962 (BSL_META_U(unit, 1963 "Loopback Ports need min 3 spacing but(next)found" 1964 "(current:%d , prev:%d)=%d\n"), 1965 current->position,prev->position,next_tdm_slot_spacing)); 1966 rv = SOC_E_CONFIG; 1967 *offender_port = ML_LPBK; 1968 continue; 1969 } 1970 } else { 1971 prev_tdm_slot_spacing = next_tdm_slot_spacing = 0; 1972 } 1973 #if 0 1974 head1 = current1 = &ml_tdm_port_slots_info[ML_CMIC]; 1975 do { 1976 tdm_slot_spacing = (current->position - current1->position) > 0 ? 1977 (current->position - current1->position)-1: 1978 (total_tdm_slots - current1->position + 1979 current->position) - 1 ; 1980 if (tdm_slot_spacing < 3) { 1981 LOG_ERROR(BSL_LS_SOC_COMMON, 1982 (BSL_META_U(unit, 1983 "Loopback and CMIC ports need min 3 spacing but " 1984 "found:%u" "(Loopack current:%d , CMIC Current:%d)\n"), 1985 tdm_slot_spacing, 1986 current->position,current1->position)); 1987 rv = SOC_E_CONFIG; 1988 *offender_port=ML_LPBK; 1989 continue; 1990 } 1991 current1 = current1->next; 1992 }while ((current1 !=head1) && (rv == SOC_E_NONE)); 1993 #endif 1994 current = current->next; 1995 } while ((current !=head) && (rv == SOC_E_NONE)); 1996 LOG_VERBOSE(BSL_LS_SOC_COMMON, 1997 (BSL_META_U(unit, 1998 "Verifying rules \n"))); 1999 LOG_VERBOSE(BSL_LS_SOC_COMMON, 2000 (BSL_META_U(unit, 2001 "Rule1 : Each Loopback port need 2.5G bandwidth \n"))); 2002 LOG_VERBOSE(BSL_LS_SOC_COMMON, 2003 (BSL_META_U(unit, 2004 "Rule2 : Each CMIC port need 2G bandwidth \n"))); 2005 for (index=0;index < ML_MAX_LOGICAL_PORTS && rv == SOC_E_NONE ;index++ ) { 2006 port = index ; 2007 if (ml_tdm_port_slots_info[port].position == -1) { 2008 continue; 2009 } 2010 LOG_VERBOSE(BSL_LS_SOC_COMMON, 2011 (BSL_META_U(unit, 2012 " %d ==>\n\n"),port)); 2013 switch(port) { 2014 case ML_CMIC: 2015 LOG_VERBOSE(BSL_LS_SOC_COMMON, 2016 (BSL_META_U(unit, 2017 "CMIM \n"))); 2018 speed =2000; 2019 break; 2020 case ML_LPBK: 2021 LOG_VERBOSE(BSL_LS_SOC_COMMON, 2022 (BSL_META_U(unit, 2023 "LOOPBAKC \n"))); 2024 speed =lpbk_port_speed; 2025 break; 2026 default: 2027 LOG_VERBOSE(BSL_LS_SOC_COMMON, 2028 (BSL_META_U(unit, 2029 " Port:%d Speed %d ==>\n\n"), 2030 port,port_speed[port-1])); 2031 speed = port_speed[port-1]; 2032 break; 2033 } 2034 if ((speed == 0) && (!SOC_PBMP_MEMBER((PBMP_ALL(unit)), port))) { 2035 /* Eagle ports are not removed from TDM calendar 2036 * Eventhough not active after lane op. Ignore those 2037 */ 2038 continue; 2039 } 2040 2041 switch(speed) { 2042 case 1000: 2043 speed_index=0; 2044 break; 2045 case 2000: 2046 speed_index=1; 2047 break; 2048 case 2500: 2049 speed_index=2; 2050 break; 2051 case 10000: 2052 case 10500: /* Might need ut fir HG11 */ 2053 case 11000: /* Might need ut fir HG11 */ 2054 speed_index=3; 2055 break; 2056 case 12500: /* Special case for LPBK port */ 2057 case 13000: 2058 speed_index=4; 2059 break; 2060 case 20000: 2061 speed_index=5; 2062 break; 2063 case 21000: 2064 speed_index=6; 2065 break; 2066 default: 2067 LOG_ERROR(BSL_LS_SOC_COMMON, 2068 (BSL_META_U(unit, 2069 "Unsupported speed:%d \n"),speed)); 2070 return SOC_E_FAIL; 2071 } 2072 worse_tdm_slot_spacing=ml_tdm_cycles_info[tdm_freq_index][speed_index]. 2073 worse_tdm_slot_spacing; 2074 min_tdm_cycles=ml_tdm_cycles_info[tdm_freq_index][speed_index]. 2075 min_tdm_cycles; 2076 2077 count=0; 2078 head = current = &ml_tdm_port_slots_info[port]; 2079 do { 2080 prev = current->prev; 2081 if (current->position != prev->position ) { 2082 prev_tdm_slot_spacing = 2083 (current->position - prev->position)> 0 ? 2084 (current->position - prev->position)-1: 2085 (total_tdm_slots - prev->position + 2086 current->position) - 1 ; 2087 next_tdm_slot_spacing = 2088 (current->next->position - current->position) > 0 ? 2089 (current->next->position - current->position)-1: 2090 (total_tdm_slots - current->position + 2091 current->next->position) - 1; 2092 } else { 2093 prev_tdm_slot_spacing = next_tdm_slot_spacing = 0; 2094 } 2095 LOG_VERBOSE(BSL_LS_SOC_COMMON, 2096 (BSL_META_U(unit, 2097 "Pos:%d Spacing (Prev %d - %d = )%d" 2098 "(Next %d - %d = )%d\n"), current->position, 2099 current->position , prev->position , 2100 prev_tdm_slot_spacing, current->next->position , 2101 current->position , next_tdm_slot_spacing)); 2102 if ((prev_tdm_slot_spacing > worse_tdm_slot_spacing) || 2103 (next_tdm_slot_spacing > worse_tdm_slot_spacing)) { 2104 if (port == ML_CMIC) { 2105 /* Exception for worst TDM slot spacing for CMIC port */ 2106 LOG_VERBOSE(BSL_LS_SOC_COMMON, 2107 (BSL_META_U(unit, 2108 "WorseSpacing:%d (prev:%d next:%d)" 2109 "NOK !!!! port:%d\n"), 2110 worse_tdm_slot_spacing, 2111 prev_tdm_slot_spacing, next_tdm_slot_spacing, 2112 port)); 2113 LOG_VERBOSE(BSL_LS_SOC_COMMON, 2114 (BSL_META_U(unit,"**ATTN:SKIPPING FOR TIME-BEING \n"))); 2115 } else { 2116 LOG_ERROR(BSL_LS_SOC_COMMON, 2117 (BSL_META_U(unit, 2118 "WorseSpacing:%d (prev:%d next:%d)" 2119 "NOK !!!! port:%d\n"), 2120 worse_tdm_slot_spacing, 2121 prev_tdm_slot_spacing, next_tdm_slot_spacing, 2122 port)); 2123 rv = SOC_E_CONFIG; 2124 *offender_port=port; 2125 continue; 2126 } 2127 } 2128 count++; 2129 current = current->next; 2130 } while ((current !=head) && (rv == SOC_E_NONE)) ; 2131 LOG_VERBOSE(BSL_LS_SOC_COMMON, 2132 (BSL_META_U(unit, 2133 "TDM Cycles: %d \n"),count)); 2134 if (count < min_tdm_cycles) { 2135 LOG_ERROR(BSL_LS_SOC_COMMON, 2136 (BSL_META_U(unit, 2137 "min_tdm_cycles:%dNOK !!!! port:%d\n"), 2138 min_tdm_cycles,port)); 2139 rv = SOC_E_CONFIG; 2140 *offender_port=port; 2141 continue; 2142 } 2143 LOG_VERBOSE(BSL_LS_SOC_COMMON, 2144 (BSL_META_U(unit, 2145 "n== %d <==\n\n"),port)); 2146 } 2147 2148 LOG_VERBOSE(BSL_LS_SOC_COMMON, 2149 (BSL_META_U(unit, 2150 "Verifying rule \n"))); 2151 LOG_VERBOSE(BSL_LS_SOC_COMMON, 2152 (BSL_META_U(unit, 2153 "Rule4 : Each subport in MXQPORT operates with 4 cycle TDM \n"))); 2154 LOG_VERBOSE(BSL_LS_SOC_COMMON, 2155 (BSL_META_U(unit, 2156 "Verifying MXQports spacing concern\n"))); 2157 for(mxqblock=0;mxqblock<(ML_MAX_BLOCKS-1) && rv == SOC_E_NONE ;mxqblock++) { 2158 for(index=0; 2159 index<ML_MAX_PORTS_PER_BLOCK && rv == SOC_E_NONE; 2160 index++) { 2161 outer_port = (*ml_block_ports[unit])[mxqblock][index]; 2162 if (outer_port == 0xFF) { 2163 if ((mxqblock == 7) && (index == 3)) { 2164 outer_port = 40; 2165 } else { 2166 continue; 2167 } 2168 } 2169 if (ml_tdm_port_slots_info[outer_port].position == -1) { 2170 continue; 2171 } 2172 head = current = &ml_tdm_port_slots_info[outer_port]; 2173 do { 2174 for(loop=0;loop<ML_MAX_PORTS_PER_BLOCK; loop++) { 2175 inner_port=(*ml_block_ports[unit])[mxqblock][loop]; 2176 if (inner_port == 0xFF) { 2177 if ((mxqblock == 7) && (loop == 3)) { 2178 inner_port = 40; 2179 } else { 2180 continue; 2181 } 2182 } 2183 if ( inner_port == outer_port) { 2184 continue; 2185 } 2186 if (ml_tdm_port_slots_info[inner_port].position == -1) { 2187 continue; 2188 } 2189 head1 = current1 = &ml_tdm_port_slots_info[inner_port]; 2190 do { 2191 spacing = (current->position - current1->position) > 0 ? 2192 (current->position - current1->position)-1: 2193 (total_tdm_slots - current1->position + 2194 current->position) - 1; 2195 if (spacing < 3) { 2196 LOG_ERROR(BSL_LS_SOC_COMMON, 2197 (BSL_META_U(unit, 2198 "Outer Port:%d Inner Port:%d " 2199 "MXQSpacing Issue" 2200 "Expected > 4 but observed %d\n"), 2201 outer_port,inner_port,spacing)); 2202 rv = SOC_E_CONFIG; 2203 *offender_port=outer_port; 2204 continue; 2205 } 2206 current1 = current1->next; 2207 } while ((current1 !=head1) && (rv == SOC_E_NONE)); 2208 } 2209 current = current->next; 2210 } while ((current !=head) && (rv == SOC_E_NONE)); 2211 } 2212 } 2213 2214 /* Free allocated resources */ 2215 count=0; 2216 for (port=0;port < ML_MAX_LOGICAL_PORTS ; port++) { 2217 head = current = &ml_tdm_port_slots_info[port]; 2218 do { 2219 temp = current->next; 2220 if (current != head) { 2221 count++; 2222 LOG_VERBOSE(BSL_LS_SOC_COMMON, 2223 (BSL_META_U(unit, 2224 "Freed count :%d\n"),count)); 2225 sal_free(current); 2226 } 2227 current = temp; 2228 } while (current != head); 2229 ml_tdm_port_slots_info[port].prev=NULL; 2230 ml_tdm_port_slots_info[port].next=NULL; 2231 ml_tdm_port_slots_info[port].position = -1; 2232 } 2233 sal_memcpy(&ml_current_tdm_cycles_info, 2234 &ml_tdm_cycles_info[tdm_freq_index][0], 2235 sizeof(tdm_cycles_info_t)*KT2_MAX_SPEEDS); 2236 return rv; 2237 return SOC_E_NONE; 2238 } 2239 #endif 2240 #if 0 2241 void soc_metrolite_save_tdm_pos(int unit, uint32 new_tdm_size,uint32 *new_tdm) { 2242 uint32 pos=0; 2243 uint8 port=0; 2244 uint8 block=0; 2245 uint8 total_slots=0; 2246 2247 sal_memset(ml_tdm_pos_info,0,sizeof(ml_tdm_pos_info)); 2248 for (pos = 0; pos < new_tdm_size ; pos++) { 2249 port= new_tdm[pos]; 2250 if ((port == ML_IDLE) || (port == ML_LPBK) || 2251 (port == ML_CMIC)) { 2252 continue; 2253 } 2254 if(port > ML_MAX_PHYSICAL_PORTS ) { 2255 LOG_ERROR(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 2256 "tdm_size %d, pos %d, port %d \n"), 2257 new_tdm_size, pos, port)); 2258 2259 } else { 2260 block = (*ml_port_to_block[unit])[port - 1]; 2261 total_slots = ml_tdm_pos_info[block].total_slots; 2262 ml_tdm_pos_info[block].pos[total_slots]=pos; 2263 ml_tdm_pos_info[block].total_slots++; 2264 } 2265 } 2266 2267 sal_memcpy(ml_current_tdm,new_tdm,new_tdm_size*sizeof(new_tdm[0])); 2268 ml_current_tdm_size=new_tdm_size; 2269 2270 } 2271 2272 /* This function splits the occurance of first port of the block into 4 ports */ 2273 /* Make sure that the tdm of the block is not already split */ 2274 void ml_block_tdm_split(int unit, uint32 *tdm, 2275 uint32 total_tdm_slots, uint32 block) 2276 { 2277 uint32 index=0, count=0; 2278 uint32 first_port; 2279 2280 first_port = (*ml_block_ports[unit])[block][0]; 2281 for (index=0; index < total_tdm_slots ; index++ ) { 2282 /* Split first port occurance in to 4 */ 2283 if (tdm[index] == first_port) { 2284 tdm[index] = first_port + (count % 4); 2285 count++; 2286 } 2287 2288 } 2289 } 2290 2291 void ml_tdm_replace(uint32 *tdm, uint32 total_tdm_slots, 2292 uint32 src, uint32 dst,uint32 one_time) 2293 { 2294 uint32 index=0; 2295 for (index=0; index < total_tdm_slots ; index++ ) { 2296 if (tdm[index] == src) { 2297 tdm[index] = dst; 2298 if (one_time) { 2299 break; 2300 } 2301 } 2302 } 2303 } 2304 2305 void ml_tdm_swap(uint32 *tdm, uint32 total_tdm_slots, 2306 uint32 src, uint32 dst) 2307 { 2308 uint32 index=0; 2309 uint32 temp_index=0; 2310 uint32 temp=0; 2311 for (index=0; index < total_tdm_slots ; index++ ) { 2312 if (tdm[index] == src) { 2313 temp_index=index; 2314 } 2315 if (tdm[index] == dst) { 2316 temp = tdm[temp_index]; 2317 tdm[temp_index]=dst; 2318 tdm[index]=temp; 2319 } 2320 } 2321 } 2322 2323 soc_error_t 2324 soc_metrolite_reconfigure_tdm(int unit,uint32 new_tdm_size,uint32 *new_tdm) 2325 { 2326 uint8 new_tdm_no=0; 2327 soc_mem_t tdm_table[]={IARB_TDM_TABLEm , IARB_TDM_TABLE_1m}; 2328 soc_field_t wrap_ptr[]={TDM_WRAP_PTRf , TDM_1_WRAP_PTRf}; 2329 uint32 lls_tdm_size=0; 2330 lls_port_tdm_entry_t *lls_tdm=NULL; 2331 uint32 iarb_size=0; 2332 iarb_tdm_table_entry_t *iarb_tdm=NULL; 2333 int iter=0; 2334 uint32 index; 2335 uint32 rval; 2336 int cfg_num; 2337 2338 SOC_IF_ERROR_RETURN(_soc_metrolite_get_cfg_num(unit, 0, &cfg_num)); 2339 if (cfg_num >= (sizeof(bcm56270_tdm)/sizeof(bcm56270_tdm[0]))) { 2340 return SOC_E_FAIL; 2341 } 2342 2343 SOC_IF_ERROR_RETURN(READ_IARB_TDM_CONTROLr(unit, &rval)); 2344 old_tdm_no = soc_reg_field_get(unit, IARB_TDM_CONTROLr, rval, SELECT_TDMf); 2345 new_tdm_no = (old_tdm_no + 1)%2; 2346 2347 iarb_size = soc_mem_index_count(unit,IARB_TDM_TABLEm) * 2348 sizeof(iarb_tdm_table_entry_t); 2349 iarb_tdm = soc_cm_salloc(unit,iarb_size, "iarb_tdm_table_entry_t"); 2350 if (iarb_tdm == NULL) { 2351 return SOC_E_MEMORY; 2352 } 2353 sal_memset(iarb_tdm,0,iarb_size); 2354 2355 lls_tdm_size = soc_mem_index_count(unit,LLS_PORT_TDMm) * 2356 sizeof(lls_port_tdm_entry_t); 2357 lls_tdm = soc_cm_salloc(unit,lls_tdm_size, "lls_port_tdm_entry_t"); 2358 if (lls_tdm == NULL) { 2359 soc_cm_sfree(unit,iarb_tdm); 2360 return SOC_E_MEMORY; 2361 } 2362 sal_memset(lls_tdm,0,lls_tdm_size); 2363 2364 for (index = 0; index < new_tdm_size; index++) { 2365 soc_IARB_TDM_TABLEm_field32_set(unit, &iarb_tdm[index], PORT_NUMf, 2366 new_tdm[index]); 2367 } 2368 soc_mem_write_range(unit, tdm_table[new_tdm_no], MEM_BLOCK_ALL, 0, 2369 new_tdm_size, iarb_tdm); 2370 soc_cm_sfree(unit,iarb_tdm); 2371 2372 for (index = 0; index < new_tdm_size/2; index++) { 2373 soc_LLS_PORT_TDMm_field32_set(unit, &lls_tdm[index], 2374 PORT_ID_0f, new_tdm[index*2]); 2375 if ( new_tdm[index*2] < ML_IDLE ) { 2376 soc_LLS_PORT_TDMm_field32_set(unit, &lls_tdm[index], 2377 PORT_ID_0_ENABLEf, 1); 2378 } else { 2379 LOG_VERBOSE(BSL_LS_SOC_COMMON, 2380 (BSL_META_U(unit, 2381 "IDLE SLOTs so PORT_ID_0_ENABLEf=0 \ 2382 for index=%d\n"), index)); 2383 soc_LLS_PORT_TDMm_field32_set(unit, &lls_tdm[index], 2384 PORT_ID_0_ENABLEf, 0); 2385 } 2386 2387 soc_LLS_PORT_TDMm_field32_set(unit, &lls_tdm[index], 2388 PORT_ID_1f, new_tdm[(index*2) + 1]); 2389 if ( new_tdm[(index*2)+1] < ML_IDLE ) { 2390 soc_LLS_PORT_TDMm_field32_set(unit, &lls_tdm[index], 2391 PORT_ID_1_ENABLEf, 1); 2392 } else { 2393 LOG_VERBOSE(BSL_LS_SOC_COMMON, 2394 (BSL_META_U(unit, 2395 "IDLE SLOTs so PORT_ID_1_ENABLEf=0 \ 2396 for index=%d\n"), index)); 2397 soc_LLS_PORT_TDMm_field32_set(unit, &lls_tdm[index], 2398 PORT_ID_1_ENABLEf, 0); 2399 } 2400 } /* for index */ 2401 2402 if (new_tdm_size % 2) { 2403 LOG_CLI((BSL_META_U(unit, 2404 "ODD TDM SIZE \n"))); 2405 soc_LLS_PORT_TDMm_field32_set(unit, &lls_tdm[index*2], 2406 PORT_ID_0_ENABLEf, 1); 2407 soc_LLS_PORT_TDMm_field32_set(unit, &lls_tdm[index*2], 2408 PORT_ID_0f, new_tdm[(index*2)]); 2409 soc_LLS_PORT_TDMm_field32_set(unit, &lls_tdm[(index*2)+1], 2410 PORT_ID_1_ENABLEf, 0); 2411 soc_LLS_PORT_TDMm_field32_set(unit, &lls_tdm[(index*2)+1], 2412 PORT_ID_1f, 0); 2413 index++; 2414 } 2415 2416 soc_mem_write_range(unit, LLS_PORT_TDMm, MEM_BLOCK_ALL, 2417 new_tdm_no*256, (new_tdm_no*256) + index, 2418 lls_tdm); 2419 soc_cm_sfree(unit,lls_tdm); 2420 2421 SOC_IF_ERROR_RETURN(READ_IARB_TDM_CONTROLr(unit, &rval)); 2422 soc_reg_field_set(unit, IARB_TDM_CONTROLr, &rval, DISABLEf, 0); 2423 soc_reg_field_set(unit, IARB_TDM_CONTROLr, &rval, 2424 wrap_ptr[new_tdm_no],new_tdm_size -1); 2425 soc_reg_field_set(unit, IARB_TDM_CONTROLr, &rval, SELECT_TDMf, new_tdm_no); 2426 SOC_IF_ERROR_RETURN(WRITE_IARB_TDM_CONTROLr(unit, rval)); 2427 2428 if (bsl_check(bslLayerSoc, bslSourceCommon, bslSeverityVerbose, unit)) { 2429 kt2_tdm_display(unit,new_tdm,new_tdm_size, 2430 bcm56270_tdm_info[cfg_num].row, 2431 bcm56270_tdm_info[cfg_num].col); 2432 } 2433 2434 SOC_IF_ERROR_RETURN(WRITE_LLS_TDM_CAL_CFG_SWITCHr(unit, 1)); 2435 if ((SAL_BOOT_BCMSIM || SAL_BOOT_PLISIM)) { 2436 SOC_IF_ERROR_RETURN(READ_LLS_TDM_CAL_CFGr(unit, &rval)); 2437 soc_reg_field_set(unit, LLS_TDM_CAL_CFGr, &rval, 2438 CURRENT_CALENDARf,new_tdm_no); 2439 SOC_IF_ERROR_RETURN(WRITE_LLS_TDM_CAL_CFGr(unit, rval)); 2440 } 2441 2442 do { 2443 SOC_IF_ERROR_RETURN(READ_LLS_TDM_CAL_CFGr(unit, &rval)); 2444 sal_udelay(100); 2445 if (soc_reg_field_get(unit, LLS_TDM_CAL_CFGr, rval, 2446 CURRENT_CALENDARf) == new_tdm_no) { 2447 break; 2448 } 2449 } while (iter++ < 100000); 2450 2451 if (iter >= 100000) { 2452 LOG_ERROR(BSL_LS_SOC_COMMON, 2453 (BSL_META_U(unit, "LLS Calendar switch failed !!\n"))); 2454 return SOC_E_INTERNAL; 2455 } 2456 2457 old_tdm_no = new_tdm_no; 2458 soc_metrolite_save_tdm_pos(unit, new_tdm_size,new_tdm); 2459 2460 return SOC_E_NONE; 2461 } 2462 #endif 2463 2464 STATIC soc_error_t 2465 _soc_metrolite_mmu_tdm_init(int unit) 2466 { 2467 soc_error_t rv = SOC_E_NONE; 2468 uint32 *arr=NULL; 2469 uint32 row = 0, col = 0; 2470 #if 0 2471 uint32 offender_port=0; 2472 #endif 2473 2474 int i, tdm_size = 0,tdm_freq = 0, cfg_num; 2475 iarb_tdm_table_entry_t iarb_tdm; 2476 lls_port_tdm_entry_t lls_tdm; 2477 uint32 rval, arr_ele; 2478 uint16 dev_id; 2479 uint8 rev_id; 2480 uint32 port_enable_value=0; 2481 /*int loop_index, block;*/ 2482 2483 soc_cm_get_id(unit, &dev_id, &rev_id); 2484 SOC_IF_ERROR_RETURN(_soc_metrolite_get_cfg_num(unit, 0, &cfg_num)); 2485 if (cfg_num >= (sizeof(bcm56270_tdm)/sizeof(bcm56270_tdm[0]))) { 2486 LOG_ERROR(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 2487 "Wrong cfg_num:%d exceeding max cfg_num: %d\n"), 2488 cfg_num, 2489 (int)(sizeof(bcm56270_tdm)/sizeof(bcm56270_tdm[0])))); 2490 return SOC_E_FAIL; 2491 } 2492 2493 switch(dev_id) { 2494 case BCM56270_DEVICE_ID: 2495 case BCM56271_DEVICE_ID: 2496 case BCM56272_DEVICE_ID: 2497 2498 case BCM53460_DEVICE_ID: 2499 case BCM53461_DEVICE_ID: 2500 2501 tdm_size= bcm56270_tdm_info[cfg_num].tdm_size; 2502 tdm_freq= bcm56270_tdm_info[cfg_num].tdm_freq; 2503 row= bcm56270_tdm_info[cfg_num].row; 2504 col= bcm56270_tdm_info[cfg_num].col; 2505 LOG_DEBUG(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 2506 "Cfg=%d freq=%d size=%d raw=%d col=%d \n"), 2507 cfg_num,tdm_freq,tdm_size,row,col)); 2508 arr = bcm56270_tdm[cfg_num]; 2509 2510 switch(cfg_num) { 2511 /* ------------------- */ 2512 /* 56270 Configuration */ 2513 /* ------------------- */ 2514 case BCM56270_DEVICE_ID_OFFSET_CFG + 1: 2515 /* 56270 */ 2516 /* 4x 1G/2.5G + 4xXFI + 4x XFI/HGs11 + 2.5G LPBK */ 2517 sal_memcpy(arr, 2518 &ml_tdm_56270_A_ref[0],sizeof(ml_tdm_56270_A_ref)); 2519 break; 2520 2521 /* ------------------- */ 2522 /* 56271 Configuration */ 2523 /* ------------------- */ 2524 case BCM56271_DEVICE_ID_OFFSET_CFG + 1: 2525 /* 56271 */ 2526 /* 8x 1G/2.5G + 4xXFI + 2.5G LPBK */ 2527 sal_memcpy(arr, 2528 &ml_tdm_56271_C_ref[0],sizeof(ml_tdm_56271_C_ref)); 2529 break; 2530 2531 case BCM56271_DEVICE_ID_OFFSET_CFG + 2: 2532 /* 56271 */ 2533 /* 2x1G/2.5G/10G + 4x1G/2.5G G.INT */ 2534 sal_memcpy(arr, 2535 &ml_tdm_56271_C_ref[0],sizeof(ml_tdm_56271_C_ref)); 2536 2537 if(soc_property_get(unit, spn_SAT_ENABLE, 0) == 0){ 2538 ml_tdm_replace(arr,tdm_size, 6, ML_IDLE, 0); 2539 ml_tdm_replace(arr,tdm_size, 8, ML_IDLE, 0); 2540 ml_tdm_replace(arr,tdm_size, 9, ML_IDLE, 0); 2541 ml_tdm_replace(arr,tdm_size, 10, ML_IDLE, 0); 2542 ml_tdm_replace(arr,tdm_size, 11, ML_IDLE, 0); 2543 ml_tdm_replace(arr,tdm_size, 12, ML_IDLE, 0); 2544 ml_tdm_replace(arr,tdm_size, 5, 9, 0); 2545 ml_tdm_replace(arr,tdm_size, 7, 11, 0); 2546 }else{ 2547 /* SAT port (port 5) has to be enabled when SAT is enabled */ 2548 ml_tdm_replace(arr,tdm_size, 6, ML_IDLE, 0); 2549 ml_tdm_replace(arr,tdm_size, 8, ML_IDLE, 0); 2550 ml_tdm_replace(arr,tdm_size, 9, ML_IDLE_1, 0); 2551 ml_tdm_replace(arr,tdm_size, 5, 9, 0); 2552 ml_tdm_replace(arr,tdm_size, 10, 5, 0); 2553 ml_tdm_replace(arr,tdm_size, 11, 5, 0); 2554 ml_tdm_replace(arr,tdm_size, 12, 5, 0); 2555 ml_tdm_replace(arr,tdm_size, ML_IDLE_1, 5, 0); 2556 ml_tdm_replace(arr,tdm_size, 7, 11, 0); 2557 2558 } 2559 break; 2560 2561 case BCM56271_DEVICE_ID_OFFSET_CFG + 3: 2562 /* 56271 */ 2563 /* 4x1G/2.5G/10G + 4x1G/2.5G G.INT */ 2564 sal_memcpy(arr, 2565 &ml_tdm_56271_C_ref[0],sizeof(ml_tdm_56271_C_ref)); 2566 if(soc_property_get(unit, spn_SAT_ENABLE, 0) == 0){ 2567 ml_tdm_replace(arr,tdm_size, 9, ML_IDLE, 0); 2568 ml_tdm_replace(arr,tdm_size, 10, ML_IDLE, 0); 2569 ml_tdm_replace(arr,tdm_size, 11, ML_IDLE, 0); 2570 ml_tdm_replace(arr,tdm_size, 12, ML_IDLE, 0); 2571 ml_tdm_replace(arr,tdm_size, 5, 9, 0); 2572 ml_tdm_replace(arr,tdm_size, 6, 10, 0); 2573 ml_tdm_replace(arr,tdm_size, 7, 11, 0); 2574 ml_tdm_replace(arr,tdm_size, 8, 12, 0); 2575 }else { 2576 /* SAT port (port 5) has to be enabled when SAT is enabled */ 2577 ml_tdm_replace(arr,tdm_size, 9, ML_IDLE_1, 0); 2578 ml_tdm_replace(arr,tdm_size, 10, ML_IDLE_1, 0); 2579 ml_tdm_replace(arr,tdm_size, 11, ML_IDLE_1, 0); 2580 ml_tdm_replace(arr,tdm_size, 12, ML_IDLE_1, 0); 2581 2582 ml_tdm_replace(arr,tdm_size, 5, 9, 0); 2583 ml_tdm_replace(arr,tdm_size, 6, 10, 0); 2584 ml_tdm_replace(arr,tdm_size, 7, 11, 0); 2585 ml_tdm_replace(arr,tdm_size, 8, 12, 0); 2586 2587 ml_tdm_replace(arr,tdm_size, ML_IDLE_1, 5, 0); 2588 ml_tdm_replace(arr,tdm_size, ML_IDLE_1, 5, 0); 2589 ml_tdm_replace(arr,tdm_size, ML_IDLE_1, 5, 0); 2590 ml_tdm_replace(arr,tdm_size, ML_IDLE_1, 5, 0); 2591 } 2592 break; 2593 2594 2595 /* ------------------- */ 2596 /* 56272 Configuration */ 2597 /* ------------------- */ 2598 case BCM56272_DEVICE_ID_OFFSET_CFG + 1: 2599 /* 56272 */ 2600 /* 8xGE + 2.5G LPBK */ 2601 sal_memcpy(arr, 2602 &ml_tdm_56272_B_ref[0],sizeof(ml_tdm_56272_B_ref)); 2603 break; 2604 2605 case BCM56272_DEVICE_ID_OFFSET_CFG + 2: 2606 /* 56272 */ 2607 /* 2x1G + 4x1G G.INT */ 2608 sal_memcpy(arr, 2609 &ml_tdm_56272_B_ref[0],sizeof(ml_tdm_56272_B_ref)); 2610 ml_tdm_replace(arr,tdm_size, 10, ML_IDLE, 0); 2611 ml_tdm_replace(arr,tdm_size, 12, ML_IDLE, 0); 2612 break; 2613 2614 #ifdef BCM_WARM_BOOT_SUPPORT 2615 case COUNTOF(bcm56270_tdm_info) - 1: 2616 if (SOC_WARM_BOOT(unit)) { 2617 sal_memcpy(arr, 2618 &ml_scache_tdm[0], sizeof(ml_scache_tdm)); 2619 break; 2620 } 2621 #endif 2622 /* Fall thru */ 2623 default: 2624 LOG_WARN(BSL_LS_SOC_COMMON, (BSL_META_U(unit, "Invalid cfg_num\n"))); 2625 return SOC_E_FAIL; 2626 } 2627 break; 2628 default: 2629 LOG_ERROR(BSL_LS_SOC_COMMON, (BSL_META_U(unit, "Invalid DevId\n"))); 2630 return SOC_E_FAIL; 2631 } 2632 2633 /* Reconfigure TDM based on portgroup settings */ 2634 /* portgroup will be implemented later */ 2635 #if 0 2636 loop_index = 0; 2637 while(ml_selected_port_details[loop_index].start_port_no != 0) { 2638 block = loop_index; 2639 2640 /* Change TDM only if the portgroup has been modified */ 2641 if (ml_selected_port_details[loop_index].port_incr == 2642 ml_selected_port_details_orig[loop_index].port_incr) { 2643 loop_index++; 2644 continue; 2645 } 2646 2647 switch (ml_selected_port_details[loop_index].port_incr){ 2648 case PORTGROUP_SINGLE_MODE: 2649 if(ml_selected_port_details_orig[loop_index].port_incr != 2650 PORTGROUP_QUAD_MODE) { 2651 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 2652 "Setting TDM to Single Mode\n"))); 2653 for(i=1; i<ML_MAX_PORTS_PER_BLOCK; i++) { 2654 ml_tdm_replace(arr,tdm_size, 2655 (*ml_block_ports[unit])[block][i], 2656 (*ml_block_ports[unit])[block][0], 0); 2657 } 2658 } 2659 break; 2660 case PORTGROUP_DUAL_MODE: 2661 /* If original is quad mode, then we already have enough 2662 * TDM slots for dual mode as well */ 2663 if(ml_selected_port_details_orig[loop_index].port_incr != 2664 PORTGROUP_QUAD_MODE) { 2665 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 2666 "Setting TDM to Dual Mode\n"))); 2667 /* Convert single to Quad mode and then split */ 2668 ml_block_tdm_split(unit, arr, tdm_size, block); 2669 for(i=1; i<ML_MAX_PORTS_PER_BLOCK; i+=2) { 2670 ml_tdm_replace(arr,tdm_size, 2671 (*ml_block_ports[unit])[block][i], 2672 (*ml_block_ports[unit])[block][i-1], 0); 2673 } 2674 } 2675 break; 2676 case PORTGROUP_QUAD_MODE: 2677 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 2678 "Setting TDM to Quad Mode\n"))); 2679 /* Merge the slots and then split */ 2680 /* This will take care of dual to quad block */ 2681 for(i=1; i<ML_MAX_PORTS_PER_BLOCK; i++) { 2682 ml_tdm_replace(arr,tdm_size, 2683 (*ml_block_ports[unit])[block][i], 2684 (*ml_block_ports[unit])[block][0], 0); 2685 } 2686 ml_block_tdm_split(unit, arr, tdm_size, block); 2687 break; 2688 default: 2689 return SOC_E_INTERNAL; 2690 } 2691 loop_index++; 2692 } 2693 #endif 2694 /* Verify the TDM structure */ 2695 kt2_tdm_display(unit,arr, tdm_size, row, col); 2696 #if 0 2697 rv = ml_tdm_verify(unit, (uint32 *)bcm56270_tdm[cfg_num], tdm_size, 2698 tdm_freq, (uint32 *)bcm56270_speed[unit][cfg_num], 2699 lpbk_port_speed, &offender_port); 2700 if ((rv == SOC_E_CONFIG) && (offender_port == ML_IDLE)) { 2701 rv = SOC_E_NONE; 2702 } 2703 SOC_IF_ERROR_RETURN(rv); 2704 #endif 2705 2706 /* Disable IARB TDM before programming... */ 2707 SOC_IF_ERROR_RETURN(READ_IARB_TDM_CONTROLr(unit, &rval)); 2708 soc_reg_field_set(unit, IARB_TDM_CONTROLr, &rval, DISABLEf, 1); 2709 soc_reg_field_set(unit, IARB_TDM_CONTROLr, &rval, TDM_WRAP_PTRf, 2710 tdm_size -1); 2711 SOC_IF_ERROR_RETURN(WRITE_IARB_TDM_CONTROLr(unit, rval)); 2712 2713 for (i = 0; i < tdm_size; i++) { 2714 arr_ele = arr[i]; 2715 if (arr_ele < ML_IDLE) { /* Non Idle Slots */ 2716 port_enable_value = 1; 2717 } else { 2718 port_enable_value = 0; 2719 } 2720 2721 sal_memset(&iarb_tdm, 0, sizeof(iarb_tdm_table_entry_t)); 2722 soc_IARB_TDM_TABLEm_field32_set(unit, &iarb_tdm, PORT_NUMf, 2723 arr_ele); 2724 SOC_IF_ERROR_RETURN(WRITE_IARB_TDM_TABLEm(unit, SOC_BLOCK_ALL, i, 2725 &iarb_tdm)); 2726 2727 if((i % 2) == 0) { 2728 /* Two entries per mem entry */ 2729 sal_memset(&lls_tdm, 0, sizeof(lls_port_tdm_entry_t)); 2730 2731 soc_LLS_PORT_TDMm_field32_set(unit, &lls_tdm, PORT_ID_0f, arr_ele); 2732 soc_LLS_PORT_TDMm_field32_set(unit, &lls_tdm, 2733 PORT_ID_0_ENABLEf, port_enable_value); 2734 } else { 2735 soc_LLS_PORT_TDMm_field32_set(unit, &lls_tdm, PORT_ID_1f, arr_ele); 2736 soc_LLS_PORT_TDMm_field32_set(unit, &lls_tdm, 2737 PORT_ID_1_ENABLEf, port_enable_value); 2738 2739 SOC_IF_ERROR_RETURN(WRITE_LLS_PORT_TDMm(unit, SOC_BLOCK_ALL, (i/2), 2740 &lls_tdm)); 2741 } 2742 } 2743 2744 if (tdm_size % 2) { 2745 LOG_DEBUG(BSL_LS_SOC_COMMON, (BSL_META_U(unit, "Info:Odd TDM Size%d \n"),tdm_size)); 2746 SOC_IF_ERROR_RETURN(WRITE_LLS_PORT_TDMm(unit, SOC_BLOCK_ALL, (i/2), 2747 &lls_tdm)); 2748 } 2749 2750 SOC_IF_ERROR_RETURN(READ_IARB_TDM_CONTROLr(unit, &rval)); 2751 soc_reg_field_set(unit, IARB_TDM_CONTROLr, &rval, DISABLEf, 0); 2752 soc_reg_field_set(unit, IARB_TDM_CONTROLr, &rval, TDM_WRAP_PTRf, 2753 tdm_size -1); 2754 soc_reg_field_set(unit, IARB_TDM_CONTROLr, &rval, IDLE_PORT_NUM_SELf, 1); 2755 SOC_IF_ERROR_RETURN(WRITE_IARB_TDM_CONTROLr(unit, rval)); 2756 2757 rval = 0; 2758 soc_reg_field_set(unit, LLS_TDM_CAL_CFGr, &rval, END_Af, tdm_size - 1); 2759 soc_reg_field_set(unit, LLS_TDM_CAL_CFGr, &rval, END_Bf, tdm_size - 1); 2760 soc_reg_field_set(unit, LLS_TDM_CAL_CFGr, &rval, ENABLEf, 1); 2761 SOC_IF_ERROR_RETURN(WRITE_LLS_TDM_CAL_CFGr(unit, rval)); 2762 2763 soc_metrolite_save_tdm_pos(unit, tdm_size, arr); 2764 2765 return rv; 2766 } 2767 2768 soc_error_t soc_metrolite_get_port_block(int unit, 2769 soc_port_t port, uint8 *block) 2770 { 2771 /* Return invalid port for all except physical port */ 2772 if (!((port > 0 ) && (port < 13))) { 2773 return SOC_E_PORT; 2774 } 2775 2776 *block = (*ml_port_to_block[unit])[port - 1]; 2777 2778 return SOC_E_NONE; 2779 } 2780 2781 int soc_metrolite_hw_reset_control_init(int unit) { 2782 uint32 rval; 2783 soc_timeout_t to; 2784 int pipe_init_usec; 2785 2786 /* Reset IPITE and EPIPE block */ 2787 rval = 0; 2788 SOC_IF_ERROR_RETURN(WRITE_ING_HW_RESET_CONTROL_1r(unit, rval)); 2789 soc_reg_field_set(unit, ING_HW_RESET_CONTROL_2r, &rval, RESET_ALLf, 1); 2790 soc_reg_field_set(unit, ING_HW_RESET_CONTROL_2r, &rval, VALIDf, 1); 2791 soc_reg_field_set(unit, ING_HW_RESET_CONTROL_2r, &rval, COUNTf, 0x4000); 2792 SOC_IF_ERROR_RETURN(WRITE_ING_HW_RESET_CONTROL_2r(unit, rval)); 2793 2794 rval = 0; 2795 SOC_IF_ERROR_RETURN(WRITE_EGR_HW_RESET_CONTROL_0r(unit, rval)); 2796 2797 rval = 0; 2798 SOC_IF_ERROR_RETURN(READ_EGR_HW_RESET_CONTROL_1r (unit, &rval)); 2799 soc_reg_field_set(unit, EGR_HW_RESET_CONTROL_1r, &rval, RESET_ALLf, 1); 2800 soc_reg_field_set(unit, EGR_HW_RESET_CONTROL_1r, &rval, VALIDf, 1); 2801 soc_reg_field_set(unit, EGR_HW_RESET_CONTROL_1r, &rval, COUNTf, 0x4000); 2802 SOC_IF_ERROR_RETURN(WRITE_EGR_HW_RESET_CONTROL_1r(unit, rval)); 2803 2804 /* For simulation, set timeout to 10 sec. Otherwise, timeout = 50 ms */ 2805 if (SAL_BOOT_SIMULATION) { 2806 pipe_init_usec = 10000000; 2807 } else { 2808 pipe_init_usec = 50000; 2809 } 2810 soc_timeout_init(&to, pipe_init_usec, 0); 2811 2812 /* Wait for IPIPE memory initialization done. */ 2813 do { 2814 SOC_IF_ERROR_RETURN(READ_ING_HW_RESET_CONTROL_2r(unit, &rval)); 2815 if (soc_reg_field_get(unit, ING_HW_RESET_CONTROL_2r, rval, DONEf)) { 2816 break; 2817 } 2818 if (soc_timeout_check(&to)) { 2819 LOG_WARN(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 2820 "ING_HW_RESET timeout\n"))); 2821 break; 2822 } 2823 } while (TRUE); 2824 2825 /* Wait for EPIPE memory initialization done. */ 2826 do { 2827 SOC_IF_ERROR_RETURN(READ_EGR_HW_RESET_CONTROL_1r(unit, &rval)); 2828 if (soc_reg_field_get(unit, EGR_HW_RESET_CONTROL_1r, rval, DONEf)) { 2829 break; 2830 } 2831 if (soc_timeout_check(&to)) { 2832 LOG_WARN(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 2833 "EGR_HW_RESET timeout\n"))); 2834 break; 2835 } 2836 } while (TRUE); 2837 2838 SOC_IF_ERROR_RETURN(READ_ING_HW_RESET_CONTROL_2r(unit, &rval)); 2839 soc_reg_field_set(unit, ING_HW_RESET_CONTROL_2r, &rval, RESET_ALLf, 0); 2840 soc_reg_field_set(unit, ING_HW_RESET_CONTROL_2r, &rval, 2841 CMIC_REQ_ENABLEf, 1); 2842 SOC_IF_ERROR_RETURN(WRITE_ING_HW_RESET_CONTROL_2r(unit, rval)); 2843 2844 SOC_IF_ERROR_RETURN(READ_EGR_HW_RESET_CONTROL_1r(unit, &rval)); 2845 soc_reg_field_set(unit, EGR_HW_RESET_CONTROL_1r, &rval, RESET_ALLf, 0); 2846 SOC_IF_ERROR_RETURN(WRITE_EGR_HW_RESET_CONTROL_1r(unit, rval)); 2847 2848 return SOC_E_NONE; 2849 } 2850 2851 soc_error_t soc_metrolite_get_mxq_phy_port_mode( 2852 int unit, soc_port_t port,int speed, bcmMxqPhyPortMode_t *mode) { 2853 2854 soc_info_t *si = &SOC_INFO(unit); 2855 2856 if (!SOC_PBMP_MEMBER((PBMP_ALL(unit)), port)) { 2857 return SOC_E_PORT; 2858 } 2859 2860 if(!IS_MXQ_PORT(unit, port)){ 2861 return SOC_E_NONE; 2862 } 2863 2864 if (speed <= 2500) { 2865 *mode=bcmMxqPhyPortModeQuad; 2866 si->port_num_lanes[port] = 1; 2867 return SOC_E_NONE; 2868 } else if (speed >= 10000) { 2869 *mode=bcmMxqPhyPortModeSingle; 2870 si->port_num_lanes[port] = 4; 2871 return SOC_E_NONE; 2872 } else { 2873 LOG_WARN(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 2874 "Invalid speed for setting phy_port_mode\n"))); 2875 return SOC_E_CONFIG; 2876 } 2877 2878 } 2879 2880 soc_error_t soc_metrolite_get_xl_phy_core_port_mode( 2881 int unit, soc_port_t port, 2882 bcmXlPhyPortMode_t *phy_mode, 2883 bcmXlCorePortMode_t *core_mode) { 2884 2885 uint8 block=0; 2886 uint8 loop=0; 2887 uint8 port_used[ML_MAX_PORTS_PER_BLOCK]={0, 0, 0, 0}; 2888 uint8 num_ports=0; 2889 int cfg_num; 2890 char *intf_type = NULL; 2891 uint32 rxaui = 0; 2892 soc_port_t first_port; 2893 soc_info_t *si = &SOC_INFO(unit); 2894 #ifdef BCM_WARM_BOOT_SUPPORT 2895 uint32 rval = 0, oamp_status = 0; 2896 #endif 2897 2898 if (!SOC_PBMP_MEMBER((PBMP_ALL(unit)), port)) { 2899 return SOC_E_PORT; 2900 } 2901 2902 if(!IS_XL_PORT(unit, port)) { 2903 return SOC_E_NONE; 2904 } 2905 2906 SOC_IF_ERROR_RETURN(_soc_metrolite_get_cfg_num(unit, 0, &cfg_num)); 2907 if (cfg_num >= (sizeof(bcm56270_tdm)/sizeof(bcm56270_tdm[0]))) { 2908 return SOC_E_FAIL; 2909 } 2910 2911 SOC_IF_ERROR_RETURN(soc_metrolite_get_port_block(unit,port,&block)); 2912 first_port = (*ml_block_ports[unit])[block][0]; 2913 2914 for(loop=0;loop<ML_MAX_PORTS_PER_BLOCK; loop++) { 2915 2916 if ((bcm56270_speed[unit][cfg_num] 2917 [(block*ML_MAX_PORTS_PER_BLOCK)+loop]) && 2918 (SOC_PBMP_MEMBER((PBMP_ALL(unit)), 2919 (block*ML_MAX_PORTS_PER_BLOCK)+loop+1))){ 2920 port_used[loop] = 1; 2921 num_ports++; 2922 } 2923 #ifdef BCM_WARM_BOOT_SUPPORT 2924 SOC_IF_ERROR_RETURN(READ_OAMP_ENABLEr(unit, &rval)); 2925 oamp_status = soc_reg_field_get(unit, OAMP_ENABLEr, rval, ENABLEf); 2926 2927 if ((SOC_WARM_BOOT(unit) && (block == 1))) { 2928 if ((bcm56270_speed[unit][cfg_num] 2929 [(block*ML_MAX_PORTS_PER_BLOCK)+loop] == 0) && 2930 (oamp_status == 1)){ 2931 2932 port_used[loop] = 1; 2933 num_ports++; 2934 } 2935 } 2936 #endif 2937 } 2938 2939 switch(num_ports){ 2940 case 0: return SOC_E_PARAM; 2941 case 1: *phy_mode=bcmXlPhyPortModeSingle; 2942 *core_mode=bcmXlCorePortModeSingle; 2943 si->port_num_lanes[first_port] = 4; 2944 si->port_num_lanes[first_port + 1] = 0; 2945 si->port_num_lanes[first_port + 2] = 0; 2946 si->port_num_lanes[first_port + 3] = 0; 2947 break; 2948 case 2: 2949 *phy_mode=bcmXlPhyPortModeDual; 2950 *core_mode=bcmXlCorePortModeDual; 2951 intf_type= soc_property_port_get_str(unit, port, spn_SERDES_IF_TYPE); 2952 2953 if (intf_type != NULL) { 2954 if ((sal_strcmp(intf_type, "RXAUI") == 0) || 2955 (sal_strcmp(intf_type, "rxaui") == 0)) { 2956 /* mode : RXAUI */ 2957 si->port_num_lanes[first_port] = 2; 2958 si->port_num_lanes[first_port + 1] = 0; 2959 si->port_num_lanes[first_port + 2] = 2; 2960 si->port_num_lanes[first_port + 3] = 0; 2961 } else if ((sal_strcmp(intf_type, "XFI") == 0) || 2962 (sal_strcmp(intf_type, "xfi") == 0)) { 2963 /* mode : 2xXFI */ 2964 si->port_num_lanes[first_port] = 1; 2965 si->port_num_lanes[first_port + 1] = 0; 2966 si->port_num_lanes[first_port + 2] = 1; 2967 si->port_num_lanes[first_port + 3] = 0; 2968 } 2969 } 2970 2971 rxaui = soc_property_port_get(unit, port, 2972 spn_SERDES_RXAUI_MODE, 0xFF); 2973 if ((rxaui == 0) || (rxaui == 1)) { 2974 /* mode : RXAUI */ 2975 si->port_num_lanes[first_port] = 2; 2976 si->port_num_lanes[first_port + 1] = 0; 2977 si->port_num_lanes[first_port + 2] = 2; 2978 si->port_num_lanes[first_port + 3] = 0; 2979 } else { 2980 /* mode : 2xXFI */ 2981 si->port_num_lanes[first_port] = 1; 2982 si->port_num_lanes[first_port + 1] = 0; 2983 si->port_num_lanes[first_port + 2] = 1; 2984 si->port_num_lanes[first_port + 3] = 0; 2985 } 2986 break; 2987 case 3: if(port_used[0] && port_used[2] && port_used[3]) { 2988 *phy_mode = bcmXlPhyPortModeTri023; 2989 *core_mode = bcmXlCorePortModeTri023; 2990 si->port_num_lanes[first_port] = 2; 2991 si->port_num_lanes[first_port + 1] = 0; 2992 si->port_num_lanes[first_port + 2] = 1; 2993 si->port_num_lanes[first_port + 3] = 1; 2994 } else if (port_used[0] && port_used[1] && port_used[2]) { 2995 *phy_mode = bcmXlPhyPortModeTri012; 2996 *core_mode = bcmXlCorePortModeTri012; 2997 si->port_num_lanes[first_port] = 1; 2998 si->port_num_lanes[first_port + 1] = 1; 2999 si->port_num_lanes[first_port + 2] = 2; 3000 si->port_num_lanes[first_port + 3] = 0; 3001 } else { 3002 return SOC_E_PARAM; 3003 } 3004 break; 3005 case 4: *phy_mode=bcmXlPhyPortModeQuad; 3006 *core_mode=bcmXlCorePortModeQuad; 3007 si->port_num_lanes[first_port] = 1; 3008 si->port_num_lanes[first_port + 1] = 1; 3009 si->port_num_lanes[first_port + 2] = 1; 3010 si->port_num_lanes[first_port + 3] = 1; 3011 break; 3012 } 3013 3014 return SOC_E_NONE; 3015 } 3016 3017 3018 3019 soc_error_t 3020 soc_metrolite_port_init_config(int unit, int cfg_num, soc_port_t port) 3021 { 3022 uint32 rval, port_speed; 3023 bcmMxqPhyPortMode_t phy_mode = -1; 3024 bcmXlCorePortMode_t core_mode_xl = -1; 3025 bcmXlPhyPortMode_t phy_mode_xl = -1; 3026 3027 port_speed = bcm56270_speed[unit][cfg_num][port-1]; 3028 3029 if(IS_MXQ_PORT(unit, port)) { 3030 SOC_IF_ERROR_RETURN(soc_metrolite_get_mxq_phy_port_mode( 3031 unit, port, port_speed, &phy_mode)); 3032 if(phy_mode == -1) { 3033 return SOC_E_FAIL; 3034 } 3035 } 3036 if (SOC_REG_PORT_VALID(unit, XPORT_MODE_REGr, port)) { 3037 SOC_IF_ERROR_RETURN(READ_XPORT_MODE_REGr(unit, port, &rval)); 3038 soc_reg_field_set(unit, XPORT_MODE_REGr, &rval, PHY_PORT_MODEf, phy_mode); 3039 if(port_speed < 10000) { 3040 soc_reg_field_set(unit, XPORT_MODE_REGr, &rval, 3041 PORT_GMII_MII_ENABLEf, 1); 3042 } else { 3043 soc_reg_field_set(unit, XPORT_MODE_REGr, &rval, 3044 PORT_GMII_MII_ENABLEf, 0); 3045 } 3046 SOC_IF_ERROR_RETURN(WRITE_XPORT_MODE_REGr(unit, port, rval)); 3047 } 3048 3049 if (SOC_REG_PORT_VALID(unit, XPORT_MIB_RESETr, port)) { 3050 SOC_IF_ERROR_RETURN(WRITE_XPORT_MIB_RESETr(unit, port, 0xf)); 3051 sal_usleep(1000); 3052 SOC_IF_ERROR_RETURN(WRITE_XPORT_MIB_RESETr(unit, port, 0x0)); 3053 } 3054 3055 if (SOC_REG_PORT_VALID(unit, XLPORT_CONFIGr, port)) { 3056 if (IS_ST_PORT(unit, port)) { 3057 SOC_IF_ERROR_RETURN(READ_XLPORT_CONFIGr(unit, port, &rval)); 3058 soc_reg_field_set(unit, XLPORT_CONFIGr, &rval, HIGIG_MODEf, 1); 3059 if ((soc_feature(unit, soc_feature_higig2)) && 3060 (soc_property_port_get(unit, port, 3061 spn_HIGIG2_HDR_MODE, 0))) { 3062 soc_reg_field_set(unit, XLPORT_CONFIGr, &rval, HIGIG2_MODEf, 1); 3063 } else { 3064 soc_reg_field_set(unit, XLPORT_CONFIGr, &rval, HIGIG2_MODEf, 0); 3065 } 3066 soc_reg_field_set(unit, XLPORT_CONFIGr, &rval, MY_MODIDf, 0); 3067 SOC_IF_ERROR_RETURN(WRITE_XLPORT_CONFIGr(unit, port, rval)); 3068 } else { 3069 SOC_IF_ERROR_RETURN(READ_XLPORT_CONFIGr(unit, port, &rval)); 3070 soc_reg_field_set(unit, XLPORT_CONFIGr, &rval, HIGIG_MODEf, 0); 3071 soc_reg_field_set(unit, XLPORT_CONFIGr, &rval, HIGIG2_MODEf, 0); 3072 soc_reg_field_set(unit, XLPORT_CONFIGr, &rval, MY_MODIDf, 0); 3073 SOC_IF_ERROR_RETURN(WRITE_XLPORT_CONFIGr(unit, port, rval)); 3074 } 3075 } 3076 3077 if (SOC_REG_PORT_VALID(unit, XLPORT_MODE_REGr, port)) { 3078 SOC_IF_ERROR_RETURN(WRITE_XLPORT_MODE_REGr(unit, port, 0)); 3079 } 3080 3081 if (SOC_REG_PORT_VALID(unit, XLPORT_SOFT_RESETr, port)) { 3082 SOC_IF_ERROR_RETURN(WRITE_XLPORT_SOFT_RESETr(unit, port, 0xF)); 3083 } 3084 3085 if(IS_XL_PORT(unit, port)) { 3086 SOC_IF_ERROR_RETURN(soc_metrolite_get_xl_phy_core_port_mode(unit, port, 3087 &phy_mode_xl, &core_mode_xl)); 3088 if((phy_mode_xl == -1) || (core_mode_xl == -1)){ 3089 return SOC_E_FAIL; 3090 } 3091 } 3092 if (SOC_REG_PORT_VALID(unit, XLPORT_MODE_REGr, port)) { 3093 rval = 0; 3094 soc_reg_field_set(unit, XLPORT_MODE_REGr, &rval, 3095 EGR_1588_TIMESTAMPING_CMIC_48_ENf, 1); 3096 soc_reg_field_set(unit, XLPORT_MODE_REGr, &rval, 3097 XPORT0_CORE_PORT_MODEf,core_mode_xl); 3098 soc_reg_field_set(unit, XLPORT_MODE_REGr, &rval, 3099 XPORT0_PHY_PORT_MODEf, phy_mode_xl); 3100 SOC_IF_ERROR_RETURN(WRITE_XLPORT_MODE_REGr(unit, port, rval)); 3101 } 3102 3103 if (SOC_REG_PORT_VALID(unit, XLPORT_SOFT_RESETr, port)) { 3104 SOC_IF_ERROR_RETURN(WRITE_XLPORT_SOFT_RESETr(unit, port, 0x0)); 3105 } 3106 3107 if (SOC_REG_PORT_VALID(unit, XLPORT_MIB_RESETr, port)) { 3108 SOC_IF_ERROR_RETURN(WRITE_XLPORT_MIB_RESETr(unit, port, 0xf)); 3109 sal_usleep(1000); 3110 SOC_IF_ERROR_RETURN(WRITE_XLPORT_MIB_RESETr(unit, port, 0x0)); 3111 } 3112 3113 if (SOC_REG_PORT_VALID(unit, XLPORT_ECC_CONTROLr, port)) { 3114 rval = 0; 3115 soc_reg_field_set(unit, XLPORT_ECC_CONTROLr, &rval, 3116 MIB_TSC_MEM_ENf, 1); 3117 SOC_IF_ERROR_RETURN(WRITE_XLPORT_ECC_CONTROLr(unit, port, rval)); 3118 } 3119 3120 if (SOC_REG_PORT_VALID(unit, XLPORT_CNTMAXSIZEr, port)) { 3121 rval = 0; 3122 soc_reg_field_set(unit, XLPORT_CNTMAXSIZEr, &rval, CNTMAXSIZEf, 0x5F2); 3123 SOC_IF_ERROR_RETURN(WRITE_XLPORT_CNTMAXSIZEr(unit, port, rval)); 3124 } 3125 3126 if (SOC_REG_PORT_VALID(unit, X_GPORT_CNTMAXSIZEr, port)) { 3127 rval = 0; 3128 soc_reg_field_set(unit, X_GPORT_CNTMAXSIZEr, &rval, CNTMAXSIZEf, 0x5F2); 3129 SOC_IF_ERROR_RETURN(WRITE_X_GPORT_CNTMAXSIZEr(unit, port, rval)); 3130 } 3131 3132 if (SOC_REG_PORT_VALID(unit, XLPORT_FLOW_CONTROL_CONFIGr, port)) { 3133 /* enable flow control for port macro ports */ 3134 SOC_IF_ERROR_RETURN(READ_XLPORT_FLOW_CONTROL_CONFIGr(unit, port, &rval)); 3135 soc_reg_field_set(unit, XLPORT_FLOW_CONTROL_CONFIGr, &rval,MERGE_MODE_ENf, 1); 3136 SOC_IF_ERROR_RETURN(WRITE_XLPORT_FLOW_CONTROL_CONFIGr(unit, port, rval)); 3137 } 3138 3139 return SOC_E_NONE; 3140 } 3141 3142 int 3143 _ml_ledup_init(int unit, uint16 dev_id) 3144 { 3145 uint32 rval = 0; 3146 int ix; 3147 int freq, cycles; 3148 int refresh_rate=30, refresh_period; 3149 uint8 remap_value[ML_MAX_PHYSICAL_PORTS]; 3150 3151 /* Construct CMIC_LEDUP0_DATA_RAM port remapping */ 3152 for (ix = 0; ix < ML_MAX_PHYSICAL_PORTS; ix++) { 3153 remap_value[ix] = ML_MAX_PHYSICAL_PORTS - ix; 3154 } 3155 3156 /* Apply CMIC_LEDUP0_DATA_RAM port remapping */ 3157 ix = 0; 3158 rval = 0; 3159 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_0_3r, &rval, 3160 REMAP_PORT_0f, remap_value[ix++]); 3161 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_0_3r, &rval, 3162 REMAP_PORT_1f, remap_value[ix++]); 3163 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_0_3r, &rval, 3164 REMAP_PORT_2f, remap_value[ix++]); 3165 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_0_3r, &rval, 3166 REMAP_PORT_3f, remap_value[ix++]); 3167 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP0_PORT_ORDER_REMAP_0_3r(unit, rval)); 3168 3169 rval = 0; 3170 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_4_7r, &rval, 3171 REMAP_PORT_4f, remap_value[ix++]); 3172 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_4_7r, &rval, 3173 REMAP_PORT_5f, remap_value[ix++]); 3174 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_4_7r, &rval, 3175 REMAP_PORT_6f, remap_value[ix++]); 3176 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_4_7r, &rval, 3177 REMAP_PORT_7f, remap_value[ix++]); 3178 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP0_PORT_ORDER_REMAP_4_7r(unit, rval)); 3179 3180 rval = 0; 3181 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_8_11r, &rval, 3182 REMAP_PORT_8f, remap_value[ix++]); 3183 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_8_11r, &rval, 3184 REMAP_PORT_9f, remap_value[ix++]); 3185 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_8_11r, &rval, 3186 REMAP_PORT_10f, remap_value[ix++]); 3187 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_8_11r, &rval, 3188 REMAP_PORT_11f, remap_value[ix]); 3189 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP0_PORT_ORDER_REMAP_8_11r(unit, rval)); 3190 3191 3192 /* Initialize the UP0 data ram */ 3193 rval = 0; 3194 for (ix = 0; ix < 256; ix++) { 3195 /* coverity[result_independent_of_operands] */ 3196 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP0_DATA_RAMr(unit,ix, rval)); 3197 } 3198 3199 /* From Top spec, Ring 0 LED chain is connected to 28 ports 3200 * Ring 1 LED chain is connected to iProc AMAC0/1 ports 3201 * Ring 2 is not connected. 3202 */ 3203 3204 /* Apply LEDUP delays. */ 3205 /* coverity[result_independent_of_operands] */ 3206 SOC_IF_ERROR_RETURN(READ_CMIC_LEDUP0_CTRLr(unit, &rval)); 3207 soc_reg_field_set(unit,CMIC_LEDUP0_CTRLr, 3208 &rval, LEDUP_SCAN_START_DELAYf, 0x6); 3209 soc_reg_field_set(unit,CMIC_LEDUP0_CTRLr, 3210 &rval, LEDUP_SCAN_INTRA_PORT_DELAYf, 0x5); 3211 /* coverity[result_independent_of_operands] */ 3212 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP0_CTRLr(unit, rval)); 3213 3214 /* Program the LED clock output frequency based on core clock */ 3215 freq = SOC_INFO(unit).frequency; 3216 3217 /* For LEDCLK_HALF_PERIOD */ 3218 /* Formula : cycles = (freq * 10^6) * (100 * 10^-9) = freq/10 */ 3219 /* Round up the value for non-integer clocks */ 3220 cycles = (freq + 9) / 10 - 1; 3221 if (cycles < 2) { 3222 cycles = 2; 3223 } 3224 3225 rval = 0; 3226 soc_reg_field_set(unit, CMIC_LEDUP0_CLK_DIVr, &rval, 3227 LEDCLK_HALF_PERIODf, cycles); 3228 /* coverity[result_independent_of_operands] */ 3229 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP0_CLK_DIVr(unit, rval)); 3230 /* coverity[result_independent_of_operands] */ 3231 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP1_CLK_DIVr(unit, rval)); 3232 3233 /* For REFRESH_CYCLE_PERIOD */ 3234 /* Formula : refresh_period = (freq * 10^6) / 30 */ 3235 refresh_period = freq * 1000000 / refresh_rate; 3236 3237 rval = 0; 3238 soc_reg_field_set(unit, CMIC_LEDUP0_CLK_PARAMSr, &rval, 3239 REFRESH_CYCLE_PERIODf, refresh_period); 3240 /* coverity[result_independent_of_operands] */ 3241 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP0_CLK_PARAMSr(unit, rval)); 3242 /* coverity[result_independent_of_operands] */ 3243 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP1_CLK_PARAMSr(unit, rval)); 3244 3245 return SOC_E_NONE; 3246 } 3247 3248 int _soc_metrolite_misc_init(int unit) 3249 { 3250 soc_info_t *si; 3251 uint32 rval; 3252 uint32 entry[SOC_MAX_MEM_WORDS], ing_entry[SOC_MAX_MEM_WORDS]; 3253 soc_pbmp_t pbmp; 3254 int port; 3255 int blk; 3256 uint64 reg64; 3257 uint16 dev_id; 3258 uint8 rev_id; 3259 soc_field_t fields[3]; 3260 uint32 values[3]; 3261 int cfg_num; 3262 int rv; 3263 int parity_enable; 3264 int my_modid_list[4] = { 0, 0, 0, 0 }; 3265 int my_modid_valid[4] = { 1, 0, 0, 0 }; 3266 int my_modid_port_base_ptr[4] = { 0, 0, 0, 0 }; 3267 soc_cm_get_id(unit, &dev_id, &rev_id); 3268 3269 si = &SOC_INFO(unit); 3270 3271 SOC_BLOCK_ITER(unit, blk, SOC_BLK_MXQPORT) { 3272 port = SOC_BLOCK_PORT(unit, blk); 3273 3274 /* Bring XMAC out of reset */ 3275 if (SOC_IS_METROLITE(unit)) { 3276 SOC_IF_ERROR_RETURN(READ_XPORT_MODE_REGr(unit,port,&rval)); 3277 soc_reg_field_set(unit, XPORT_MODE_REGr, &rval, PORT_GMII_MII_ENABLEf, 3278 0x1); 3279 soc_reg_field_set(unit, XPORT_MODE_REGr, &rval, PHY_PORT_MODEf, 3280 0x2); 3281 SOC_IF_ERROR_RETURN(WRITE_XPORT_MODE_REGr(unit,port,rval)); 3282 } 3283 } 3284 3285 /* saber2 related hw reset control */ 3286 if(!SOC_WARM_BOOT(unit)) { 3287 SOC_IF_ERROR_RETURN(_soc_saber2_hw_reset_control_init(unit)); 3288 } 3289 3290 /* core clock info in MHz updated from PRD 3291 * Do not modify these values until unless stated in PRD*/ 3292 switch(dev_id) { 3293 case BCM56270_DEVICE_ID: 3294 si->frequency = 180; 3295 break; 3296 case BCM56271_DEVICE_ID: 3297 si->frequency = 125; 3298 break; 3299 case BCM56272_DEVICE_ID: 3300 si->frequency = 30; 3301 break; 3302 } 3303 3304 parity_enable = soc_property_get(unit, spn_PARITY_ENABLE, FALSE); 3305 3306 /* WRED Configuration */ 3307 SOC_IF_ERROR_RETURN(READ_WRED_MISCCONFIGr(unit, &rval)); 3308 switch(dev_id) { 3309 case BCM56270_DEVICE_ID: 3310 /* Refer the formula in the Reg file 3311 + * For Metrolite 56270, frequency is 180MHZ 3312 + * Calculation is 3313 + * ((512 + 128)/2 * (0.00555)) + 1 = 2.778 3314 + * So we are programming 3 */ 3315 soc_reg_field_set(unit, WRED_MISCCONFIGr, &rval, BASE_UPDATE_INTERVALf, 3); 3316 break; 3317 case BCM56271_DEVICE_ID: 3318 /* Refer the formula in the Reg file 3319 + * For Metrolite 56271, frequency is 125MHZ 3320 + * Calculation is 3321 + * ((512 + 128)/2 * (0.008)) + 1 = 3.56 3322 + * So we are programming 4 */ 3323 soc_reg_field_set(unit, WRED_MISCCONFIGr, &rval, BASE_UPDATE_INTERVALf, 4); 3324 break; 3325 case BCM56272_DEVICE_ID: 3326 /* Refer the formula in the Reg file 3327 + * For Metrolite 56272, frequency is 30MHZ 3328 + * Calculation is 3329 + * ((512 + 128)/2 * (0.0333)) + 1 = 11.667 3330 + * So we are programming 12 */ 3331 soc_reg_field_set(unit, WRED_MISCCONFIGr, &rval, BASE_UPDATE_INTERVALf, 12); 3332 break; 3333 } 3334 SOC_IF_ERROR_RETURN(WRITE_WRED_MISCCONFIGr(unit, rval)); 3335 3336 soc_saber2_ser_init(unit, parity_enable ? TRUE : FALSE); 3337 3338 /* initialize LED UP0 */ 3339 SOC_IF_ERROR_RETURN(_ml_ledup_init(unit, dev_id)); 3340 3341 /* Some registers are implemented in memory, need to clear them in order 3342 * to have correct parity value */ 3343 PBMP_PP_ALL_ITER(unit, port) { 3344 SOC_IF_ERROR_RETURN(WRITE_EGR_VLAN_CONTROL_1r(unit, port, 0)); 3345 SOC_IF_ERROR_RETURN(WRITE_EGR_IPMC_CFG2r(unit, port, 0)); 3346 } 3347 3348 SOC_IF_ERROR_RETURN( 3349 bcm_kt2_modid_set_all(unit, my_modid_list, my_modid_valid, 3350 my_modid_port_base_ptr)); 3351 3352 sal_memset(entry, 0, sizeof(cpu_pbm_entry_t)); 3353 soc_mem_pbmp_field_set(unit, CPU_PBMm, entry, BITMAPf, &PBMP_CMIC(unit)); 3354 SOC_IF_ERROR_RETURN 3355 (soc_mem_write(unit, CPU_PBMm, MEM_BLOCK_ALL, 0, entry)); 3356 3357 sal_memset(entry, 0, sizeof(cpu_pbm_2_entry_t)); 3358 soc_mem_pbmp_field_set(unit, CPU_PBM_2m, entry, BITMAPf, &PBMP_CMIC(unit)); 3359 SOC_IF_ERROR_RETURN 3360 (soc_mem_write(unit, CPU_PBM_2m, MEM_BLOCK_ALL, 0, entry)); 3361 3362 sal_memset(entry, 0, sizeof(multipass_loopback_bitmap_entry_t)); 3363 soc_mem_pbmp_field_set(unit, MULTIPASS_LOOPBACK_BITMAPm, entry, BITMAPf, 3364 &PBMP_LB(unit)); 3365 SOC_IF_ERROR_RETURN 3366 (soc_mem_write(unit, MULTIPASS_LOOPBACK_BITMAPm, MEM_BLOCK_ALL, 0, 3367 entry)); 3368 3369 sal_memset(entry, 0, sizeof(egr_physical_port_entry_t)); 3370 sal_memset(ing_entry, 0, sizeof(ing_physical_port_table_entry_t)); 3371 3372 soc_mem_field32_set(unit, EGR_PHYSICAL_PORTm, entry, PORT_TYPEf, 1); 3373 soc_mem_field32_set(unit, ING_PHYSICAL_PORT_TABLEm, 3374 ing_entry, PORT_TYPEf, 1); 3375 3376 /* Higig ports */ 3377 PBMP_ST_ITER(unit, port) { 3378 SOC_IF_ERROR_RETURN(soc_reg_field32_modify( 3379 unit, IECELL_CONFIGr, port, HIGIG_MODEf, 1)); 3380 SOC_IF_ERROR_RETURN(soc_reg_field32_modify( 3381 unit, XLPORT_CONFIGr, port, HIGIG_MODEf, 1)); 3382 if (IS_HL_PORT(unit,port) || 3383 soc_property_port_get(unit, port, spn_HIGIG2_HDR_MODE, 0)) { 3384 SOC_IF_ERROR_RETURN(soc_reg_field32_modify( 3385 unit,IECELL_CONFIGr, port, HIGIG2_MODEf, 1)); 3386 SOC_IF_ERROR_RETURN(soc_reg_field32_modify( 3387 unit, XLPORT_CONFIGr, port, HIGIG2_MODEf, 1)); 3388 soc_mem_field32_set(unit, ING_PHYSICAL_PORT_TABLEm,ing_entry, 3389 HIGIG2f,1); 3390 soc_mem_field32_set(unit, EGR_PHYSICAL_PORTm,entry, 3391 HIGIG2f,1); 3392 } else { 3393 SOC_IF_ERROR_RETURN(soc_reg_field32_modify( 3394 unit, IECELL_CONFIGr, port, HIGIG2_MODEf, 0)); 3395 SOC_IF_ERROR_RETURN(soc_reg_field32_modify( 3396 unit, XLPORT_CONFIGr, port, HIGIG2_MODEf, 0)); 3397 soc_mem_field32_set(unit, ING_PHYSICAL_PORT_TABLEm,ing_entry, 3398 HIGIG2f,0); 3399 soc_mem_field32_set(unit, EGR_PHYSICAL_PORTm,entry, 3400 HIGIG2f,0); 3401 } 3402 SOC_IF_ERROR_RETURN(soc_mem_write(unit, EGR_PHYSICAL_PORTm, 3403 MEM_BLOCK_ALL, port, entry)); 3404 SOC_IF_ERROR_RETURN(soc_mem_write(unit, ING_PHYSICAL_PORT_TABLEm, 3405 MEM_BLOCK_ALL, port, ing_entry)); 3406 } 3407 3408 /* CMIC higig index */ 3409 /* Setup the cpu_hg_port specifically in HG2 mode */ 3410 soc_mem_field32_set(unit, ING_PHYSICAL_PORT_TABLEm, ing_entry, 3411 HIGIG2f, 1); 3412 soc_mem_field32_set(unit, EGR_PHYSICAL_PORTm,entry, 3413 HIGIG2f, 1); 3414 SOC_IF_ERROR_RETURN(soc_mem_write( 3415 unit, EGR_PHYSICAL_PORTm, MEM_BLOCK_ALL, si->cpu_hg_index, entry)); 3416 SOC_IF_ERROR_RETURN(soc_mem_write( 3417 unit, ING_PHYSICAL_PORT_TABLEm, MEM_BLOCK_ALL, 3418 si->cpu_hg_index, ing_entry)); 3419 3420 /* Loopback port */ 3421 soc_mem_field32_set(unit, EGR_PHYSICAL_PORTm, entry, PORT_TYPEf, 2); 3422 soc_mem_field32_set(unit, ING_PHYSICAL_PORT_TABLEm, ing_entry, 3423 PORT_TYPEf, 2); 3424 SOC_IF_ERROR_RETURN(soc_mem_write( 3425 unit, EGR_PHYSICAL_PORTm, MEM_BLOCK_ALL, si->lb_port, entry)); 3426 SOC_IF_ERROR_RETURN(soc_mem_write( 3427 unit, ING_PHYSICAL_PORT_TABLEm, 3428 MEM_BLOCK_ALL, si->lb_port, ing_entry)); 3429 /* ingress physical port to pp_port mapping */ 3430 SOC_IF_ERROR_RETURN(soc_mem_field32_modify( 3431 unit, ING_PHYSICAL_PORT_TABLEm, 3432 si->lb_port, PP_PORTf, si->lb_port)); 3433 3434 /* pp_port to egress physical port mapping */ 3435 SOC_IF_ERROR_RETURN(soc_mem_field32_modify( 3436 unit, PP_PORT_TO_PHYSICAL_PORT_MAPm, 3437 si->lb_port, DESTINATIONf,si->lb_port)); 3438 3439 SOC_IF_ERROR_RETURN(READ_MISCCONFIGr(unit, &rval)); 3440 soc_reg_field_set(unit, MISCCONFIGr, &rval, METERING_CLK_ENf, 1); 3441 SOC_IF_ERROR_RETURN(WRITE_MISCCONFIGr(unit, rval)); 3442 3443 /* Enable dual hash on L2, L3 and MPLS_ENTRY tables */ 3444 fields[0] = ENABLEf; 3445 values[0] = 1; 3446 fields[1] = HASH_SELECTf; 3447 values[1] = FB_HASH_CRC32_LOWER; 3448 fields[2] = INSERT_LEAST_FULL_HALFf; 3449 values[2] = 1; 3450 SOC_IF_ERROR_RETURN 3451 (soc_reg_fields32_modify(unit, L2_AUX_HASH_CONTROLr, REG_PORT_ANY, 3, 3452 fields, values)); 3453 SOC_IF_ERROR_RETURN 3454 (soc_reg_fields32_modify(unit, L3_AUX_HASH_CONTROLr, REG_PORT_ANY, 3, 3455 fields, values)); 3456 SOC_IF_ERROR_RETURN 3457 (soc_reg_field32_modify(unit, MPLS_ENTRY_HASH_CONTROLr, REG_PORT_ANY, 3458 INSERT_LEAST_FULL_HALFf, 1)); 3459 /* 3460 * IPMC init 3461 */ 3462 SOC_IF_ERROR_RETURN(READ_RQE_GLOBAL_CONFIGr(unit, &rval)); 3463 soc_reg_field_set(unit,RQE_GLOBAL_CONFIGr, &rval, PARITY_GEN_ENf, 3464 1); 3465 soc_reg_field_set(unit,RQE_GLOBAL_CONFIGr, &rval, PARITY_CHK_ENf, 3466 1); 3467 SOC_IF_ERROR_RETURN(WRITE_RQE_GLOBAL_CONFIGr(unit, rval)); 3468 3469 /* Egress Disable */ 3470 sal_memset(entry, 0, sizeof(egr_enable_entry_t)); 3471 soc_mem_field32_set(unit, EGR_ENABLEm, entry, PRT_ENABLEf, 0); 3472 for (port = 0; port <= si->lb_port; port++) { 3473 rv = WRITE_EGR_ENABLEm(unit, MEM_BLOCK_ALL, port, entry); 3474 /* ****************************************************************** */ 3475 3476 /* ****************************************************************** */ 3477 if (SOC_FAILURE(rv)) { 3478 if (rv == _SHR_E_PARAM) { 3479 continue; 3480 } 3481 return rv; 3482 } 3483 } 3484 3485 #if 0 3486 SOC_IF_ERROR_RETURN(READ_DEQ_EFIFO_CFG_COMPLETEr(unit, &rval)); 3487 soc_reg_field_set(unit, DEQ_EFIFO_CFG_COMPLETEr, &rval, \ 3488 EGRESS_FIFO_CONFIGURATION_COMPLETEf, 0); 3489 SOC_IF_ERROR_RETURN(WRITE_DEQ_EFIFO_CFG_COMPLETEr(unit, rval)); 3490 #endif 3491 3492 sal_memset(entry, 0, sizeof(epc_link_bmap_entry_t)); 3493 soc_mem_pbmp_field_set(unit, EPC_LINK_BMAPm, entry, PORT_BITMAPf, 3494 &PBMP_CMIC(unit)); 3495 SOC_IF_ERROR_RETURN(WRITE_EPC_LINK_BMAPm(unit, MEM_BLOCK_ALL, 0, entry)); 3496 3497 SOC_IF_ERROR_RETURN(READ_ING_CONFIG_64r(unit, ®64)); 3498 soc_reg64_field32_set(unit, ING_CONFIG_64r, ®64, 3499 L3SRC_HIT_ENABLEf, 1); 3500 soc_reg64_field32_set(unit, ING_CONFIG_64r, ®64, 3501 L2DST_HIT_ENABLEf, 1); 3502 soc_reg64_field32_set(unit, ING_CONFIG_64r, ®64, 3503 APPLY_EGR_MASK_ON_L2f, 1); 3504 soc_reg64_field32_set(unit, ING_CONFIG_64r, ®64, 3505 APPLY_EGR_MASK_ON_L3f, 1); 3506 soc_reg64_field32_set(unit, ING_CONFIG_64r, ®64, 3507 ARP_RARP_TO_FPf, 0x3); /* enable both ARP & RARP */ 3508 soc_reg64_field32_set(unit, ING_CONFIG_64r, ®64, 3509 ARP_VALIDATION_ENf, 1); 3510 soc_reg64_field32_set(unit, ING_CONFIG_64r, ®64, 3511 IGNORE_HG_HDR_LAG_FAILOVERf, 1); 3512 SOC_IF_ERROR_RETURN(WRITE_ING_CONFIG_64r(unit, reg64)); 3513 /* The HW defaults for EGR_VLAN_CONTROL_1.VT_MISS_UNTAG == 1, which 3514 * causes the outer tag to be removed from packets that don't have 3515 * a hit in the egress vlan tranlation table. Set to 0 to disable this. 3516 */ 3517 rval = 0; 3518 soc_reg_field_set(unit, EGR_VLAN_CONTROL_1r, &rval, VT_MISS_UNTAGf, 0); 3519 3520 /* Enable pri/cfi remarking on egress ports. */ 3521 soc_reg_field_set(unit, EGR_VLAN_CONTROL_1r, &rval, REMARK_OUTER_DOT1Pf, 3522 1); 3523 PBMP_ALL_ITER(unit, port) { 3524 SOC_IF_ERROR_RETURN(WRITE_EGR_VLAN_CONTROL_1r(unit, port, rval)); 3525 } 3526 3527 SOC_PBMP_ASSIGN(pbmp, PBMP_ALL(unit)); 3528 SOC_PBMP_REMOVE(pbmp, PBMP_LB(unit)); 3529 SOC_IF_ERROR_RETURN(soc_mem_read(unit, ING_EN_EFILTER_BITMAPm, 3530 MEM_BLOCK_ANY, 0, &entry)); 3531 soc_mem_pbmp_field_set(unit, ING_EN_EFILTER_BITMAPm, &entry, BITMAPf, 3532 &pbmp); 3533 SOC_IF_ERROR_RETURN(soc_mem_write(unit, ING_EN_EFILTER_BITMAPm, 3534 MEM_BLOCK_ANY, 0, &entry)); 3535 SOC_IF_ERROR_RETURN(READ_CMIC_TXBUF_CONFIGr(unit, &rval)); 3536 soc_reg_field_set(unit, CMIC_TXBUF_CONFIGr, &rval, 3537 FIRST_SERVE_BUFFERS_WITH_EOP_CELLSf, 0); 3538 /* coverity[result_independent_of_operands] */ 3539 SOC_IF_ERROR_RETURN(WRITE_CMIC_TXBUF_CONFIGr(unit, rval)); 3540 3541 /* Multicast range initialization */ 3542 SOC_IF_ERROR_RETURN 3543 (soc_hbx_higig2_mcast_sizes_set(unit, 3544 soc_property_get(unit, spn_HIGIG2_MULTICAST_VLAN_RANGE, 3545 SOC_HBX_MULTICAST_RANGE_DEFAULT), 3546 soc_property_get(unit, spn_HIGIG2_MULTICAST_L2_RANGE, 3547 SOC_HBX_MULTICAST_RANGE_DEFAULT), 3548 soc_property_get(unit, spn_HIGIG2_MULTICAST_L3_RANGE, 3549 SOC_HBX_MULTICAST_RANGE_DEFAULT))); 3550 #if 0 3551 if (soc_mspi_init(unit) != SOC_E_NONE) { 3552 LOG_ERROR(BSL_LS_SOC_COMMON, (BSL_META_U(unit, "unit %d : MSPI Init Failed\n"), unit)); 3553 } 3554 #endif 3555 SOC_IF_ERROR_RETURN(soc_mem_clear( 3556 unit, MMU_RQE_QUEUE_OP_NODE_MAPm, COPYNO_ALL, TRUE)); 3557 SOC_IF_ERROR_RETURN(soc_mem_clear( 3558 unit, MMU_WRED_QUEUE_OP_NODE_MAPm, COPYNO_ALL, TRUE)); 3559 3560 SOC_IF_ERROR_RETURN(_soc_metrolite_get_cfg_num(unit, 0, &cfg_num)); 3561 if (cfg_num >= (sizeof(bcm56270_tdm)/sizeof(bcm56270_tdm[0]))) { 3562 LOG_WARN(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 3563 "Wrong cfg_num:%d exceeding max cfg_num: %d\n"), 3564 cfg_num, 3565 (int)(sizeof(bcm56270_tdm)/sizeof(bcm56270_tdm[0])))); 3566 return SOC_E_FAIL; 3567 } 3568 3569 PBMP_ALL_ITER(unit, port) { 3570 if ((port == 0 ) || (port >= 13)) { 3571 continue; 3572 } 3573 SOC_IF_ERROR_RETURN(soc_metrolite_port_init_config(unit, cfg_num, port)); 3574 } 3575 3576 SOC_IF_ERROR_RETURN(READ_AUX_ARB_CONTROL_2r(unit, &rval)); 3577 soc_reg_field_set(unit, AUX_ARB_CONTROL_2r, &rval, 3578 TCAM_ATOMIC_WRITE_ENABLEf, 1); 3579 SOC_IF_ERROR_RETURN(WRITE_AUX_ARB_CONTROL_2r(unit, rval)); 3580 3581 /* Setup SW2_FP_DST_ACTION_CONTROL */ 3582 fields[0] = HGTRUNK_RES_ENf; 3583 values[0] = 1; 3584 fields[1] = LAG_RES_ENf; 3585 values[1] = 1; 3586 SOC_IF_ERROR_RETURN(soc_reg_fields32_modify(unit, 3587 SW2_FP_DST_ACTION_CONTROLr, REG_PORT_ANY, 2, fields, values)); 3588 3589 /* In SB2, hardware logic for key/mask encoding and decoding is disabled */ 3590 SOC_IF_ERROR_RETURN(READ_EGR_BYPASS_CTRLr(unit, &rval)); 3591 soc_reg_field_set(unit, EGR_BYPASS_CTRLr, &rval, 3592 EFP_SW_ENC_DEC_TCAMf, 1); 3593 SOC_IF_ERROR_RETURN(WRITE_EGR_BYPASS_CTRLr(unit, rval)); 3594 #if 0 3595 #ifdef INCLUDE_AVS 3596 soc_saber2_avs_init(unit); 3597 #endif /* INCLUDE_AVS */ 3598 3599 /* initializing ts pll and bs pll */ 3600 _soc_saber2_tspll_bspll_config(unit); 3601 #endif 3602 3603 /* Initializing subport configurations */ 3604 si->subport_group_max = SOC_ML_SUBPORT_GROUP_MAX; 3605 si->subport_port_max = SOC_ML_MAX_SUBPORTS; 3606 si->pp_port_index_min = SOC_ML_SUBPORT_PP_PORT_INDEX_MIN; 3607 si->pp_port_index_max = SOC_ML_SUBPORT_PP_PORT_INDEX_MAX; 3608 si->lp_tx_databuf_start_addr_max = SOC_ML_LINKPHY_TX_DATA_BUF_START_ADDR_MAX; 3609 si->lp_tx_databuf_end_addr_min = SOC_ML_LINKPHY_TX_DATA_BUF_END_ADDR_MIN; 3610 si->lp_tx_databuf_end_addr_max = SOC_ML_LINKPHY_TX_DATA_BUF_END_ADDR_MAX; 3611 si->lp_tx_stream_start_addr_offset = SOC_ML_LINKPHY_TX_STREAM_START_ADDR_OFFSET; 3612 si->lp_block_max = SOC_ML_MAX_LINKPHY_BLOCK; 3613 si->lp_ports_max = SOC_ML_MAX_LINKPHY_PORTS; 3614 si->lp_streams_per_slice_max = SOC_ML_MAX_LINKPHY_STREAMS_PER_SLICE; 3615 si->lp_streams_per_port_max = SOC_ML_MAX_LINKPHY_STREAMS_PER_PORT; 3616 si->lp_streams_per_subport = SOC_ML_MAX_LINKPHY_STREAMS_PER_SUBPORT; 3617 3618 return SOC_E_NONE; 3619 } 3620 3621 /* *************************************************************** */ 3622 /* METROLITE MMU HELPER --- START(As per Metrolie_MMU_Settings-5.xls */ 3623 /* *************************************************************** */ 3624 /* Dynamic/SetLater Parameter */ 3625 typedef struct _soc_ml_mmu_params { 3626 uint32 mmu_min_pkt_size; /*C5*/ 3627 uint32 mmu_ethernet_mtu_bytes; /*C6*/ 3628 uint32 mmu_max_pkt_size; /*C7*/ 3629 uint32 mmu_jumbo_frame_size; /*C8*/ 3630 uint32 mmu_int_buf_cell_size; /*C9*/ 3631 uint32 mmu_pkt_header_size; /*C10*/ 3632 uint32 lossless_mode_d_c; /*C11*/ 3633 uint32 pfc_pause_mode_d_c; /*C12*/ 3634 uint32 mmu_lossless_pg_num; /*C13*/ 3635 uint32 num_ge_ports_d; /*C14*/ 3636 uint32 mmu_line_rate_ge; /*C15*/ 3637 uint32 num_ge_int_ports_d; /*C14*/ 3638 uint32 num_egr_queue_per_int_ge_port_d; /*C16*/ 3639 uint32 num_hg_ports_d; /*C17*/ 3640 uint32 mmu_line_rate_hg; /*C18*/ 3641 uint32 num_hg_int_ports_d; /*C17*/ 3642 uint32 num_egr_queue_per_int_hg_port_d; /*C19 */ 3643 uint32 mmu_num_cpu_port; /*C20*/ 3644 uint32 mmu_num_cpu_queue; /*C21*/ 3645 uint32 mmu_num_loopback_port; /*C22*/ 3646 uint32 mmu_num_loopback_queue; /*C35*/ 3647 uint32 mmu_num_ep_redirection_queue; /*C36*/ 3648 uint32 mmu_num_olp_port_d; /*C37*/ 3649 uint32 mmu_num_olp_queue; /*C38*/ 3650 uint32 olp_port_int_ext_bounding_d_c; /*C39:Dynamic*/ 3651 uint32 mmu_total_egress_queue; /*C40*/ 3652 uint32 mmu_pipeline_lat_cpap_admission; /*C41*/ 3653 uint32 mmu_int_buf_size; /*C42:2048KB=2MB*/ 3654 uint32 mmu_available_int_buf_size_d; /*C43:1434KB */ 3655 uint32 mmu_reserved_int_buf_cells; /*C44:100 Cells */ 3656 uint32 mmu_reserved_int_buf_ema_pool_size_d; /*C45:614KB */ 3657 uint32 internal_buffer_reduction_d_c; /* C46:Dynamic */ 3658 uint32 mmu_ext_buf_size; /*C47:737280KB=720MB*/ 3659 uint32 mmu_reserved_ext_buf_space_cfap; /*C48:737280KB=720MB*/ 3660 uint32 mmu_egress_queue_entries; /*C49*/ 3661 uint32 mmu_ep_redirect_queue_entries; /*C50*/ 3662 uint32 mmu_exp_num_of_repl_per_pkt; /*C51*/ 3663 uint32 mmu_repl_engine_work_queue_entries; /*C52*/ 3664 uint32 mmu_resv_repl_engine_work_queue_entries; /*C53*/ 3665 uint32 mmu_repl_engine_work_queue_in_device;/*C54*/ 3666 uint32 mmu_ema_queues; /*C55*/ 3667 uint32 num_cells_rsrvd_ing_ext_buf; /* C56:Dynamic */ 3668 uint32 per_cos_res_cells_for_int_buff_d; /* C58:Dynamic */ 3669 uint32 per_cos_res_cells_for_ext_buff_d; /* C59:Dynamic */ 3670 uint32 mmu_ing_port_dyn_thd_param; /*C60*/ 3671 uint32 mmu_ing_pg_dyn_thd_param; /*C61*/ 3672 uint32 mmu_egr_queue_dyn_thd_param_baf; /*C62*/ 3673 uint32 mmu_egr_queue_dyn_thd_param_baf_profile_lossy; /*C63*/ 3674 uint32 mmu_ing_cell_buf_reduction; /*C64 */ 3675 uint32 mmu_ing_pkt_buf_reduction; /*C65 */ 3676 } _soc_ml_mmu_params_t; 3677 3678 typedef struct _general_info { 3679 uint32 max_packet_size_in_cells; /* C72 */ 3680 uint32 jumbo_frame_for_int_buff; /* C73 */ 3681 uint32 jumbo_frame_for_ext_buff; /* C74 */ 3682 uint32 ether_mtu_cells_for_int_buff; /* C76 */ 3683 uint32 ether_mtu_cells_for_ext_buff; /* C77 */ 3684 uint32 total_num_of_ports; /* C79 */ 3685 uint32 total_num_of_ports_excl_lpbk; /* C80 */ 3686 uint32 total_num_of_ports_excl_lpbk_olp; /* C81 */ 3687 uint32 total_num_of_ports_excl_lpbk_olp_cpu; /* C82 */ 3688 uint32 port_bw_bound_to_ext_buff; /* C83 */ 3689 uint32 total_egr_queues_for_a_int_ge_ports; /* C84 */ 3690 uint32 total_egr_queues_for_a_ext_ge_ports; /* C85 */ 3691 uint32 total_egr_queues_for_a_int_hg_ports; /* C86 */ 3692 uint32 total_egr_queues_for_a_ext_hg_ports; /* C87 */ 3693 uint32 total_cpu_queues; /* C88 */ 3694 uint32 total_base_queue_int_buff; /* C89 */ 3695 uint32 total_base_queue_ext_buff; /* C90 */ 3696 uint32 total_ema_queues; /* C91 */ 3697 uint32 total_egr_base_queues_in_device; /* C93 */ 3698 uint32 total_egr_queues_in_device; /* C94 */ 3699 uint32 max_int_cell_buff_size; /* C95 */ 3700 uint32 int_cell_buff_size_after_limitation; /* C96 */ 3701 uint32 src_packing_fifo; /* C97 */ 3702 uint32 int_buff_pool; /* C98 */ 3703 uint32 ema_pool; /* C99 */ 3704 uint32 max_ext_cell_buff_size; /* C100 */ 3705 uint32 repl_engine_work_queue_entries; /* C101 */ 3706 uint32 ratio_of_ext_buff_to_int_buff_size; /* C103 */ 3707 uint32 int_buff_cells_per_avg_size_pkt; /* C104 */ 3708 uint32 ext_buff_cells_per_avg_size_pkt; /* C105 */ 3709 uint32 max_prop_of_buff_used_by_one_queue_port; /* C106 */ 3710 }_general_info_t; 3711 3712 typedef struct _input_port_threshold_t { 3713 uint32 global_hdrm_cells_for_int_buff_ingress_pool; /* C110 */ 3714 uint32 global_hdrm_cells_for_int_buff_ema_pool; /* C111 */ 3715 uint32 global_hdrm_cells_for_ext_buff_pool; /* C112 */ 3716 uint32 global_hdrm_cells_for_RE_WQEs; /* C113 */ 3717 uint32 global_hdrm_cells_for_EQEs; /* C114 */ 3718 3719 uint32 hdrm_int_buff_cells_for_10G_PG; /* C115 */ 3720 uint32 hdrm_ema_buff_cells_for_10G_PG; /* C116 */ 3721 uint32 hdrm_ext_buff_cells_for_10G_PG; /* C117 */ 3722 uint32 hdrm_RE_WQEs_pkts_for_10G_PG; /* C118 */ 3723 uint32 hdrm_EQEs_pkts_for_10G_PG; /* C119 */ 3724 3725 uint32 hdrm_int_buff_cells_for_10G_total_PG; /* C120 */ 3726 uint32 hdrm_ema_buff_cells_for_10G_total_PG; /* C121 */ 3727 uint32 hdrm_ext_buff_cells_for_10G_total_PG; /* C122 */ 3728 uint32 hdrm_RE_WQEs_pkts_for_10G_total_PG; /* C123 */ 3729 uint32 hdrm_EQEs_pkts_for_10G_total_PG; /* C124 */ 3730 3731 uint32 hdrm_int_buff_cells_for_1G_PG; /* C125 */ 3732 uint32 hdrm_ema_buff_cells_for_1G_PG; /* C126 */ 3733 uint32 hdrm_ext_buff_cells_for_1G_PG; /* C127 */ 3734 uint32 hdrm_RE_WQEs_pkts_for_1G_PG; /* C128 */ 3735 uint32 hdrm_EQEs_pkts_for_1G_PG; /* C129 */ 3736 3737 uint32 hdrm_int_buff_cells_for_1G_total_PG; /* C130 */ 3738 uint32 hdrm_ema_buff_cells_for_1G_total_PG; /* C131 */ 3739 uint32 hdrm_ext_buff_cells_for_1G_total_PG; /* C132 */ 3740 uint32 hdrm_RE_WQEs_pkts_for_1G_total_PG; /* C133 */ 3741 uint32 hdrm_EQEs_pkts_for_1G_total_PG; /* C134 */ 3742 3743 uint32 hdrm_int_buff_cells_for_olp_port; /* C135 */ 3744 uint32 hdrm_ema_buff_cells_for_olp_port; /* C136 */ 3745 uint32 hdrm_ext_buff_cells_for_olp_port; /* C137 */ 3746 uint32 hdrm_RE_WQEs_pkts_for_olp_port; /* C138 */ 3747 uint32 hdrm_EQEs_pkts_for_olp_port; /* C139 */ 3748 3749 uint32 hdrm_int_buff_cells_for_lpbk_port; /* C140 */ 3750 uint32 hdrm_ema_buff_cells_for_lpbk_port; /* C141 */ 3751 uint32 hdrm_ext_buff_cells_for_lpbk_port; /* C142 */ 3752 uint32 hdrm_RE_WQEs_pkts_for_lpbk_port; /* C143 */ 3753 uint32 hdrm_EQEs_pkts_for_lpbk_port; /* C144 */ 3754 3755 uint32 hdrm_int_buff_cells_for_cpu_port; /* C145 */ 3756 uint32 hdrm_ema_buff_cells_for_cpu_port; /* C146 */ 3757 uint32 hdrm_ext_buff_cells_for_cpu_port; /* C147 */ 3758 uint32 hdrm_RE_WQEs_pkts_for_cpu_port; /* C148 */ 3759 uint32 hdrm_EQEs_pkts_for_cpu_port; /* C149 */ 3760 3761 uint32 total_hdrm_int_buff_cells; /* C150 */ 3762 uint32 total_hdrm_int_buff_ema_pool_cells; /* C151 */ 3763 uint32 total_hdrm_ext_buff_cells; /* C152 */ 3764 uint32 total_hdrm_RE_WQEs_pkts; /* C153 */ 3765 uint32 total_hdrm_EQEs_pkts; /* C154 */ 3766 3767 uint32 min_int_buff_cells_per_PG; /* C156 */ 3768 uint32 min_int_buff_ema_pool_cells_per_PG; /* C157 */ 3769 uint32 min_ext_buff_cells_per_PG; /* C158 */ 3770 uint32 min_RE_WQEs_pkt_per_PG; /* C159 */ 3771 uint32 min_EQEs_pkt_per_PG; /* C160 */ 3772 3773 uint32 min_int_buff_cells_for_total_PG; /* C162 */ 3774 uint32 min_int_buff_ema_pool_cells_for_total_PG; /* C163 */ 3775 uint32 min_ext_buff_cells_for_total_PG; /* C164 */ 3776 uint32 min_RE_WQEs_pkts_for_total_PG; /* C165 */ 3777 uint32 min_EQEs_pkts_for_total_PG; /* C166 */ 3778 3779 uint32 min_int_buff_cells_for_a_port; /* C168 */ 3780 uint32 min_int_buff_ema_pool_cells_for_a_port; /* C169 */ 3781 uint32 min_ext_buff_cells_for_a_port; /* C170 */ 3782 uint32 min_RE_WQEs_pkts_for_a_port; /* C171 */ 3783 uint32 min_EQEs_pkts_for_a_port; /* C172 */ 3784 3785 uint32 min_int_buff_cells_for_total_port; /* C174 */ 3786 uint32 min_int_buff_ema_pool_cells_for_total_port; /* C175 */ 3787 uint32 min_ext_buff_cells_for_total_port; /* C176 */ 3788 uint32 min_RE_WQEs_pkts_for_total_port; /* C177 */ 3789 uint32 min_EQEs_pkts_for_total_port; /* C178 */ 3790 3791 uint32 total_min_int_buff_cells; /* C180 */ 3792 uint32 total_min_int_buff_ema_pool_cells; /* C181 */ 3793 uint32 total_min_ext_buff_cells; /* C182 */ 3794 uint32 total_min_RE_WQEs_pkts; /* C183 */ 3795 uint32 total_min_EQEs_pkts; /* C184 */ 3796 3797 uint32 total_shared_ing_buff_pool; /* C186 */ 3798 uint32 total_shared_EMA_buff; /* C187 */ 3799 uint32 total_shared_ext_buff; /* C188 */ 3800 uint32 total_shared_RE_WQEs_buff; /* C189 */ 3801 uint32 total_shared_EQEs_buff; /* C190 */ 3802 3803 uint32 ingress_burst_cells_size_for_one_port; /* C192 */ 3804 uint32 ingress_burst_pkts_size_for_one_port; /* C193 */ 3805 uint32 ingress_burst_cells_size_for_all_ports; /* C194 */ 3806 uint32 ingress_total_shared_cells_use_for_all_port; /* C195 */ 3807 uint32 ingress_burst_pkts_size_for_all_port; /* C196 */ 3808 uint32 ingress_total_shared_pkts_use_for_all_port; /* C197 */ 3809 uint32 ingress_total_shared_hdrm_cells_use_for_all_port; /* C198 */ 3810 uint32 ingress_total_shared_hdrm_pkts_use_for_all_port; /* C199 */ 3811 3812 }_input_port_threshold_t; 3813 3814 typedef struct _output_port_threshold_t { 3815 uint32 min_grntd_res_queue_cells_int_buff; /* C204 */ 3816 uint32 min_grntd_res_queue_cells_ext_buff; /* C205 */ 3817 uint32 min_grntd_res_queue_cells_EQEs; /* C206 */ 3818 uint32 min_grntd_res_EMA_queue_cells; /* C207 */ 3819 uint32 min_grntd_res_RE_WQs_cells; /* C208 */ 3820 uint32 min_grntd_res_RE_WQs_queue_cells_for_int_buff; /* C209 */ 3821 uint32 min_grntd_res_RE_WQs_queue_cells_for_ext_buff; /* C210 */ 3822 uint32 min_grntd_res_EP_redirect_queue_entry_cells; /* C211 */ 3823 3824 uint32 min_grntd_tot_res_queue_cells_int_buff; /* C213 */ 3825 uint32 min_grntd_tot_res_queue_cells_ext_buff; /* C214 */ 3826 uint32 min_grntd_tot_res_queue_cells_EQEs; /* C215 */ 3827 uint32 min_grntd_tot_res_EMA_queue_cells; /* C216 */ 3828 uint32 min_grntd_tot_res_RE_WQs_cells; /* C217 */ 3829 uint32 min_grntd_tot_res_RE_WQs_queue_cells_for_int_buff;/* C218 */ 3830 uint32 min_grntd_tot_res_RE_WQs_queue_cells_for_ext_buff;/* C219 */ 3831 uint32 min_grntd_tot_res_EP_redirect_queue_entry_cells; /* C220 */ 3832 3833 uint32 min_grntd_tot_shr_queue_cells_int_buff; /* C222 */ 3834 uint32 min_grntd_tot_shr_queue_cells_ext_buff; /* C223 */ 3835 uint32 min_grntd_tot_shr_queue_cells_EQEs; /* C224 */ 3836 uint32 min_grntd_tot_shr_EMA_queue_cells; /* C225 */ 3837 uint32 min_grntd_tot_shr_RE_WQs_cells; /* C226 */ 3838 uint32 min_grntd_tot_shr_RE_WQs_queue_cells_for_int_buff;/* C227 */ 3839 uint32 min_grntd_tot_shr_RE_WQs_queue_cells_for_ext_buff;/* C228 */ 3840 uint32 min_grntd_tot_shr_EP_redirect_queue_entry_cells; /* C229 */ 3841 3842 uint32 egress_queue_dynamic_threshold_parameter; /* C230 */ 3843 uint32 egress_burst_cells_size_for_one_queue; /* C231 */ 3844 uint32 egress_burst_pkts_size_for_one_queue; /* C232 */ 3845 uint32 egress_burst_cells_size_for_all_ports; /* C233 */ 3846 uint32 egress_burst_pkts_size_for_all_ports; /* C234 */ 3847 uint32 egress_burst_cells_size_for_all_queues; /* C235 */ 3848 uint32 egress_burst_pkts_size_for_all_queues; /* C236 */ 3849 uint32 egress_total_use_in_cells_for_all_queues; /* C237 */ 3850 uint32 egress_total_use_in_pkts_for_all_queues; /* C238 */ 3851 uint32 egress_remaining_cells_for_all_queues; /* C239 */ 3852 uint32 egress_remaining_pkts_for_all_queues; /* C240 */ 3853 3854 }_output_port_threshold_t; 3855 3856 typedef struct _soc_ml_mmu_intermediate_results { 3857 _general_info_t general_info; 3858 _input_port_threshold_t input_port_threshold; 3859 _output_port_threshold_t output_port_threshold; 3860 }_soc_ml_mmu_intermediate_results_t; 3861 3862 _soc_ml_mmu_intermediate_results_t _soc_ml_mmu_intermediate_results={{0}}; 3863 3864 void soc_metrolite_block_reset(int unit, uint8 block,int active_low) { 3865 uint32 rval; 3866 soc_field_t hot_swap_reset_fld[]={ 3867 TOP_MXQ_HOTSWAP_RST_Lf 3868 }; 3869 3870 if (READ_TOP_SOFT_RESET_REGr(unit, &rval) != SOC_E_NONE) { 3871 LOG_CLI((BSL_META_U(unit, 3872 "ATTN: Reading TOP_SOFT_RESET_REG failed \n"))); 3873 return; 3874 } 3875 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, 3876 hot_swap_reset_fld[block],active_low); 3877 /* coverity[check_return] */ 3878 WRITE_TOP_SOFT_RESET_REGr(unit, rval); 3879 } 3880 3881 STATIC 3882 int _soc_ml_mmu_config_extra_queue(int unit, uint32 queue, 3883 _soc_ml_mmu_params_t *_soc_ml_mmu_params, 3884 _output_port_threshold_t *output_port_threshold) 3885 { 3886 mmu_thdo_qconfig_cell_entry_t mmu_thdo_qconfig_cell_entry={{0}}; 3887 mmu_thdo_qoffset_cell_entry_t mmu_thdo_qoffset_cell_entry={{0}}; 3888 mmu_thdo_qconfig_qentry_entry_t mmu_thdo_qconfig_qentry_entry={{0}}; 3889 mmu_thdo_qoffset_qentry_entry_t mmu_thdo_qoffset_qentry_entry={{0}}; 3890 int temp_val; 3891 3892 /* 1. MMU_THDO_QCONFIG_CELL */ 3893 3894 SOC_IF_ERROR_RETURN(READ_MMU_THDO_QCONFIG_CELLm(unit, 3895 MEM_BLOCK_ANY,queue, 3896 &mmu_thdo_qconfig_cell_entry)); 3897 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, 3898 &mmu_thdo_qconfig_cell_entry, Q_MIN_CELLf, 3899 output_port_threshold->min_grntd_res_queue_cells_int_buff); 3900 3901 if (_soc_ml_mmu_params->lossless_mode_d_c) { 3902 temp_val = output_port_threshold-> 3903 min_grntd_tot_shr_queue_cells_int_buff; 3904 } else { 3905 temp_val = _soc_ml_mmu_params-> 3906 mmu_egr_queue_dyn_thd_param_baf_profile_lossy; 3907 } 3908 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, 3909 &mmu_thdo_qconfig_cell_entry, 3910 Q_SHARED_LIMIT_CELLf, 3911 temp_val); 3912 3913 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, 3914 &mmu_thdo_qconfig_cell_entry, 3915 Q_LIMIT_DYNAMIC_CELLf, 3916 _soc_ml_mmu_params->lossless_mode_d_c ? 0 : 1); 3917 3918 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, 3919 &mmu_thdo_qconfig_cell_entry, 3920 Q_LIMIT_ENABLE_CELLf, 3921 _soc_ml_mmu_params->lossless_mode_d_c ? 0 : 1); 3922 3923 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, 3924 &mmu_thdo_qconfig_cell_entry, 3925 Q_COLOR_ENABLE_CELLf,0); 3926 3927 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, 3928 &mmu_thdo_qconfig_cell_entry, 3929 Q_COLOR_LIMIT_DYNAMIC_CELLf, 3930 _soc_ml_mmu_params->lossless_mode_d_c ? 0 : 1); 3931 3932 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, 3933 &mmu_thdo_qconfig_cell_entry, 3934 LIMIT_YELLOW_CELLf, 0); 3935 3936 SOC_IF_ERROR_RETURN(WRITE_MMU_THDO_QCONFIG_CELLm(unit, 3937 MEM_BLOCK_ANY,queue, 3938 &mmu_thdo_qconfig_cell_entry)); 3939 3940 /* 2. MMU_THDO_QOFFSET_CELL */ 3941 3942 SOC_IF_ERROR_RETURN(READ_MMU_THDO_QOFFSET_CELLm(unit, 3943 MEM_BLOCK_ANY,queue, 3944 &mmu_thdo_qoffset_cell_entry)); 3945 soc_mem_field32_set(unit, MMU_THDO_QOFFSET_CELLm, 3946 &mmu_thdo_qoffset_cell_entry, 3947 RESET_OFFSET_CELLf, 2); 3948 3949 soc_mem_field32_set(unit, MMU_THDO_QOFFSET_CELLm, 3950 &mmu_thdo_qoffset_cell_entry, 3951 LIMIT_RED_CELLf, 0); 3952 3953 soc_mem_field32_set(unit, MMU_THDO_QOFFSET_CELLm, 3954 &mmu_thdo_qoffset_cell_entry, 3955 RESET_OFFSET_YELLOW_CELLf,2); 3956 3957 soc_mem_field32_set(unit, MMU_THDO_QOFFSET_CELLm, 3958 &mmu_thdo_qoffset_cell_entry, 3959 RESET_OFFSET_RED_CELLf,2); 3960 3961 SOC_IF_ERROR_RETURN(WRITE_MMU_THDO_QOFFSET_CELLm(unit, 3962 MEM_BLOCK_ANY,queue, 3963 &mmu_thdo_qoffset_cell_entry)); 3964 3965 /* 3. MMU_THDO_QCONFIG_QENTRY */ 3966 3967 SOC_IF_ERROR_RETURN(READ_MMU_THDO_QCONFIG_QENTRYm(unit, 3968 MEM_BLOCK_ANY,queue, 3969 &mmu_thdo_qconfig_qentry_entry)); 3970 3971 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_QENTRYm, 3972 &mmu_thdo_qconfig_qentry_entry, Q_MIN_QENTRYf, 3973 output_port_threshold->min_grntd_res_queue_cells_EQEs); 3974 3975 if (_soc_ml_mmu_params->lossless_mode_d_c) { 3976 temp_val = output_port_threshold-> 3977 min_grntd_tot_shr_queue_cells_EQEs; 3978 } else { 3979 temp_val = _soc_ml_mmu_params-> 3980 mmu_egr_queue_dyn_thd_param_baf_profile_lossy; 3981 } 3982 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_QENTRYm, 3983 &mmu_thdo_qconfig_qentry_entry, 3984 Q_SHARED_LIMIT_QENTRYf, temp_val); 3985 3986 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_QENTRYm, 3987 &mmu_thdo_qconfig_qentry_entry, 3988 Q_LIMIT_DYNAMIC_QENTRYf, 3989 _soc_ml_mmu_params->lossless_mode_d_c ? 0 : 1); 3990 3991 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_QENTRYm, 3992 &mmu_thdo_qconfig_qentry_entry, 3993 Q_LIMIT_ENABLE_QENTRYf, 3994 _soc_ml_mmu_params->lossless_mode_d_c ? 0 : 1); 3995 3996 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_QENTRYm, 3997 &mmu_thdo_qconfig_qentry_entry, 3998 Q_COLOR_ENABLE_QENTRYf,0); 3999 4000 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_QENTRYm, 4001 &mmu_thdo_qconfig_qentry_entry, 4002 Q_COLOR_LIMIT_DYNAMIC_QENTRYf, 4003 _soc_ml_mmu_params->lossless_mode_d_c ? 0 : 1); 4004 4005 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_QENTRYm, 4006 &mmu_thdo_qconfig_qentry_entry, 4007 LIMIT_YELLOW_QENTRYf, 0); 4008 4009 SOC_IF_ERROR_RETURN(WRITE_MMU_THDO_QCONFIG_QENTRYm(unit, 4010 MEM_BLOCK_ANY,queue, 4011 &mmu_thdo_qconfig_qentry_entry)); 4012 4013 /* 4. MMU_THDO_QOFFSET_QENTRY */ 4014 4015 SOC_IF_ERROR_RETURN(READ_MMU_THDO_QOFFSET_QENTRYm(unit, 4016 MEM_BLOCK_ANY,queue, 4017 &mmu_thdo_qoffset_qentry_entry)); 4018 4019 soc_mem_field32_set(unit, MMU_THDO_QOFFSET_QENTRYm, 4020 &mmu_thdo_qoffset_qentry_entry, 4021 RESET_OFFSET_QENTRYf, 1); 4022 4023 soc_mem_field32_set(unit, MMU_THDO_QOFFSET_QENTRYm, 4024 &mmu_thdo_qoffset_qentry_entry, 4025 LIMIT_RED_QENTRYf, 0); 4026 4027 soc_mem_field32_set(unit, MMU_THDO_QOFFSET_QENTRYm, 4028 &mmu_thdo_qoffset_qentry_entry, 4029 RESET_OFFSET_YELLOW_QENTRYf,1); 4030 4031 soc_mem_field32_set(unit, MMU_THDO_QOFFSET_QENTRYm, 4032 &mmu_thdo_qoffset_qentry_entry, 4033 RESET_OFFSET_RED_QENTRYf,1); 4034 4035 SOC_IF_ERROR_RETURN(WRITE_MMU_THDO_QOFFSET_QENTRYm(unit, 4036 MEM_BLOCK_ANY,queue, 4037 &mmu_thdo_qoffset_qentry_entry)); 4038 return SOC_E_NONE; 4039 } 4040 /* Helper function for MMU settings based on 4041 * memory mode (lossless/lossy) 4042 * mode is selected based on config variable 'lossless_mode' 4043 */ 4044 STATIC 4045 int _soc_ml_mmu_init_helper(int unit, int flex_port) 4046 { 4047 soc_info_t *si= &SOC_INFO(unit); 4048 uint16 dev_id=0; 4049 uint8 rev_id=0; 4050 uint32 valid_port_count = 0; 4051 soc_pbmp_t pbmp_int_ge; 4052 uint32 pbmp_int_ge_count=0; 4053 soc_pbmp_t pbmp_int_hg; 4054 uint32 pbmp_int_hg_count=0; 4055 uint32 mmu_num_olp_port=1; 4056 soc_pbmp_t valid_port_cpu_pbmp; 4057 soc_port_t port=0; 4058 uint32 available_internal_buffer=100; 4059 uint32 reserve_internal_buffer=0; 4060 uint32 temp_val; 4061 uint32 rval=0; 4062 uint32 service_pool=0; 4063 uint32 queue; 4064 uint32 op_node=0; 4065 uint32 op_node_offset=0; 4066 uint32 cos; 4067 uint32 idx, sub_port; 4068 uint32 val; 4069 4070 /* Per Port Settings */ 4071 uint32 mem_idx=0; 4072 thdi_port_sp_config_entry_t thdi_port_sp_config={{0}}; 4073 /* 4074 (ML_MAX_PHYSICAL_PORTS+2) * 4075 ML_MAX_SERVICE_POOLS] = {{{0}}}; 4076 */ 4077 thdi_port_pg_config_entry_t thdi_port_pg_config={{0}}; 4078 /* 4079 (ML_MAX_PHYSICAL_PORTS+2) * 4080 ML_MAX_PRIORITY_GROUPS] = {{{0}}}; 4081 */ 4082 4083 thdirqe_thdi_port_sp_config_entry_t thdirqe_thdi_port_sp_config={{0}}; 4084 /* 4085 (ML_MAX_PHYSICAL_PORTS+2) * 4086 ML_MAX_SERVICE_POOLS] = {{{0}}}; 4087 */ 4088 thdirqe_thdi_port_pg_config_entry_t thdirqe_thdi_port_pg_config={{0}}; 4089 /* 4090 (ML_MAX_PHYSICAL_PORTS+2) * 4091 ML_MAX_PRIORITY_GROUPS] = {{{0}}}; 4092 */ 4093 thdiqen_thdi_port_sp_config_entry_t thdiqen_thdi_port_sp_config = {{0}}; 4094 /* 4095 (ML_MAX_PHYSICAL_PORTS+2) * 4096 ML_MAX_SERVICE_POOLS] = {{{0}}}; 4097 */ 4098 thdiqen_thdi_port_pg_config_entry_t thdiqen_thdi_port_pg_config = {{0}}; 4099 /* 4100 (ML_MAX_PHYSICAL_PORTS+2) * 4101 ML_MAX_PRIORITY_GROUPS] = {{{0}}}; 4102 */ 4103 4104 mmu_thdo_opnconfig_cell_entry_t mmu_thdo_opnconfig_cell_entry={{0}}; 4105 mmu_thdo_qconfig_cell_entry_t mmu_thdo_qconfig_cell_entry={{0}}; 4106 mmu_thdo_qoffset_cell_entry_t mmu_thdo_qoffset_cell_entry={{0}}; 4107 4108 mmu_thdo_opnconfig_qentry_entry_t mmu_thdo_opnconfig_qentry_entry={{0}}; 4109 mmu_thdo_qconfig_qentry_entry_t mmu_thdo_qconfig_qentry_entry={{0}}; 4110 mmu_thdo_qoffset_qentry_entry_t mmu_thdo_qoffset_qentry_entry={{0}}; 4111 4112 _general_info_t *general_info = 4113 &_soc_ml_mmu_intermediate_results.general_info; 4114 _input_port_threshold_t *input_port_threshold = 4115 &_soc_ml_mmu_intermediate_results.input_port_threshold; 4116 _output_port_threshold_t *output_port_threshold = 4117 &_soc_ml_mmu_intermediate_results.output_port_threshold; 4118 4119 _soc_ml_mmu_params_t _soc_ml_mmu_params={0}; 4120 4121 /********************************************************************/ 4122 /***************** Fixed Parameter **********************************/ 4123 /********************************************************************/ 4124 _soc_ml_mmu_params.mmu_min_pkt_size = 64; /*C5*/ 4125 _soc_ml_mmu_params.mmu_ethernet_mtu_bytes=1536; /*C6*/ 4126 _soc_ml_mmu_params.mmu_max_pkt_size = 12288; /*C7*/ 4127 _soc_ml_mmu_params.mmu_jumbo_frame_size = 9216; /*C8*/ 4128 _soc_ml_mmu_params.mmu_int_buf_cell_size = 190; /*C9*/ 4129 _soc_ml_mmu_params.mmu_pkt_header_size = 62; /*C10*/ 4130 _soc_ml_mmu_params.mmu_lossless_pg_num = 1; /*C13*/ 4131 _soc_ml_mmu_params.mmu_line_rate_ge = 1; /*C15*/ 4132 _soc_ml_mmu_params.mmu_line_rate_hg = 10; /*C18*/ 4133 _soc_ml_mmu_params.mmu_num_cpu_port = 1; /*C20*/ 4134 _soc_ml_mmu_params.mmu_num_cpu_queue = 48; /*C21*/ 4135 _soc_ml_mmu_params.mmu_num_loopback_port = 1; /*C22*/ 4136 _soc_ml_mmu_params.mmu_num_loopback_queue = 8; 4137 _soc_ml_mmu_params.mmu_num_ep_redirection_queue = 16; /**/ 4138 _soc_ml_mmu_params.mmu_num_olp_queue = 8; /*C26*/ 4139 _soc_ml_mmu_params.mmu_pipeline_lat_cpap_admission = 30;/*C28*/ 4140 _soc_ml_mmu_params.mmu_reserved_int_buf_cells = 42; /*C30*/ 4141 _soc_ml_mmu_params.mmu_ep_redirect_queue_entries = 480; /*C32*/ 4142 _soc_ml_mmu_params.mmu_repl_engine_work_queue_entries = 1;/*C34*/ 4143 _soc_ml_mmu_params.mmu_resv_repl_engine_work_queue_entries = 0; /**/ 4144 _soc_ml_mmu_params.mmu_repl_engine_work_queue_in_device = 12; /*C36*/ 4145 _soc_ml_mmu_params.mmu_ing_port_dyn_thd_param = 2; /*C39*/ 4146 _soc_ml_mmu_params.mmu_ing_pg_dyn_thd_param = 7; /*C40*/ 4147 _soc_ml_mmu_params.mmu_egr_queue_dyn_thd_param_baf = 2; /*C41*/ 4148 _soc_ml_mmu_params.mmu_egr_queue_dyn_thd_param_baf_profile_lossy = 7; /*C42*/ 4149 _soc_ml_mmu_params.mmu_ing_cell_buf_reduction = 0; /*C43*/ 4150 _soc_ml_mmu_params.mmu_ing_pkt_buf_reduction = 0; /*C44*/ 4151 4152 SOC_PBMP_CLEAR (pbmp_int_ge); 4153 SOC_PBMP_CLEAR (pbmp_int_hg); 4154 4155 SOC_PBMP_CLEAR (valid_port_cpu_pbmp); 4156 SOC_PBMP_ASSIGN(valid_port_cpu_pbmp, PBMP_ALL(unit)); 4157 /* SOC_PBMP_PORT_ADD(valid_port_cpu_pbmp, si->cmic_port); */ 4158 4159 soc_cm_get_id(unit, &dev_id, &rev_id); 4160 /* C11 */ 4161 _soc_ml_mmu_params.lossless_mode_d_c = soc_property_get(unit, 4162 spn_LOSSLESS_MODE, 0); 4163 /* C12 */ 4164 _soc_ml_mmu_params.pfc_pause_mode_d_c = soc_property_get(unit, 4165 "pfc_pause_mode", 0); 4166 /* C29 */ 4167 _soc_ml_mmu_params.mmu_int_buf_size = 10922; 4168 4169 SOC_PBMP_COUNT(PBMP_PORT_ALL (unit), valid_port_count); 4170 4171 SOC_PBMP_ASSIGN(pbmp_int_ge,PBMP_GE_ALL(unit)); 4172 SOC_PBMP_ASSIGN(pbmp_int_hg,PBMP_HG_ALL(unit)); 4173 SOC_PBMP_OR(pbmp_int_hg,PBMP_XE_ALL(unit)); 4174 SOC_PBMP_COUNT(pbmp_int_ge,pbmp_int_ge_count); 4175 SOC_PBMP_COUNT(pbmp_int_hg,pbmp_int_hg_count); 4176 4177 /* C14 */ 4178 _soc_ml_mmu_params.num_ge_ports_d = pbmp_int_ge_count ; 4179 4180 /* C14 */ 4181 _soc_ml_mmu_params.num_ge_int_ports_d = pbmp_int_ge_count; 4182 /* C16 */ 4183 _soc_ml_mmu_params.num_egr_queue_per_int_ge_port_d = pbmp_int_ge_count ? 8:0; 4184 /* C17 */ 4185 _soc_ml_mmu_params.num_hg_ports_d = pbmp_int_hg_count ; 4186 /* C17 */ 4187 _soc_ml_mmu_params.num_hg_int_ports_d = pbmp_int_hg_count ; 4188 /* C19 */ 4189 _soc_ml_mmu_params.num_egr_queue_per_int_hg_port_d = pbmp_int_hg_count ? 8:0; 4190 /* C25 */ 4191 _soc_ml_mmu_params.mmu_num_olp_port_d = mmu_num_olp_port; 4192 /* */ 4193 _soc_ml_mmu_params.olp_port_int_ext_bounding_d_c = soc_property_get(unit, 4194 "olp_port_bounding",0); 4195 /* C27 */ 4196 _soc_ml_mmu_params.mmu_total_egress_queue = ML_MMU_MAX_EGRESS_QUEUE; 4197 4198 /* C33 */ 4199 /* C51 = C14+C17-1 */ 4200 _soc_ml_mmu_params.mmu_exp_num_of_repl_per_pkt = 4201 _soc_ml_mmu_params.num_ge_ports_d + 4202 _soc_ml_mmu_params.num_hg_ports_d - 1 ; 4203 4204 available_internal_buffer=100; 4205 reserve_internal_buffer=0; 4206 4207 /* */ 4208 _soc_ml_mmu_params.mmu_available_int_buf_size_d=available_internal_buffer; 4209 /* (_soc_ml_mmu_params.mmu_int_buf_size*available_internal_buffer)/100; */ 4210 /* */ 4211 _soc_ml_mmu_params.mmu_reserved_int_buf_ema_pool_size_d= 4212 reserve_internal_buffer; 4213 /* (_soc_ml_mmu_params.mmu_int_buf_size*reserve_internal_buffer)/100; */ 4214 4215 /* */ 4216 _soc_ml_mmu_params.internal_buffer_reduction_d_c = soc_property_get(unit, 4217 "internal_buffer_reduction",0); 4218 4219 /* C36 */ 4220 _soc_ml_mmu_params.mmu_egress_queue_entries = 12; 4221 4222 /* C38 = CEILING((C6*1024+C10)/C9, 1) */ 4223 _soc_ml_mmu_params.per_cos_res_cells_for_int_buff_d = 4224 sal_ceil_func((_soc_ml_mmu_params.mmu_ethernet_mtu_bytes + 4225 _soc_ml_mmu_params.mmu_pkt_header_size), 4226 _soc_ml_mmu_params.mmu_int_buf_cell_size); 4227 /***********************************************************************************/ 4228 /*********************** Intermediate Results Processing****************************/ 4229 /***********************************************************************************/ 4230 4231 /* C62 = CEILING((C7+C10)/C9,1) */ 4232 general_info->max_packet_size_in_cells = sal_ceil_func( 4233 (_soc_ml_mmu_params.mmu_max_pkt_size + 4234 _soc_ml_mmu_params.mmu_pkt_header_size), 4235 _soc_ml_mmu_params.mmu_int_buf_cell_size); 4236 4237 /* C63 = CEILING((C8+C10)/C9,1) */ 4238 general_info->jumbo_frame_for_int_buff = sal_ceil_func( 4239 (_soc_ml_mmu_params.mmu_jumbo_frame_size + 4240 _soc_ml_mmu_params.mmu_pkt_header_size), 4241 _soc_ml_mmu_params.mmu_int_buf_cell_size); 4242 4243 /* C64 =CEILING((C6*1024+C10)/C9, 1) */ 4244 general_info->ether_mtu_cells_for_int_buff = sal_ceil_func( 4245 (_soc_ml_mmu_params.mmu_ethernet_mtu_bytes) + 4246 _soc_ml_mmu_params.mmu_pkt_header_size, 4247 _soc_ml_mmu_params.mmu_int_buf_cell_size); 4248 4249 4250 /* C66 = C14+C17+C20+C22+C25 */ 4251 general_info->total_num_of_ports = 4252 _soc_ml_mmu_params.num_ge_ports_d + 4253 _soc_ml_mmu_params.num_hg_ports_d + 4254 _soc_ml_mmu_params.mmu_num_cpu_port + 4255 _soc_ml_mmu_params.mmu_num_loopback_port + 4256 _soc_ml_mmu_params.mmu_num_olp_port_d; 4257 4258 /* C67 = C14+C17+C20+C25 */ 4259 general_info->total_num_of_ports_excl_lpbk = 4260 _soc_ml_mmu_params.num_ge_ports_d + 4261 _soc_ml_mmu_params.num_hg_ports_d + 4262 _soc_ml_mmu_params.mmu_num_cpu_port + 4263 _soc_ml_mmu_params.mmu_num_olp_port_d; 4264 4265 /* C68 = C14+C17+C20 */ 4266 general_info->total_num_of_ports_excl_lpbk_olp = 4267 _soc_ml_mmu_params.num_ge_ports_d + 4268 _soc_ml_mmu_params.num_hg_ports_d + 4269 _soc_ml_mmu_params.mmu_num_cpu_port; 4270 4271 /* C69 = C14+C17 */ 4272 general_info->total_num_of_ports_excl_lpbk_olp_cpu = 4273 _soc_ml_mmu_params.num_ge_ports_d + 4274 _soc_ml_mmu_params.num_hg_ports_d; 4275 4276 4277 4278 /* C71 = C16*C14 */ 4279 general_info->total_egr_queues_for_a_int_ge_ports = 4280 (_soc_ml_mmu_params.num_egr_queue_per_int_ge_port_d * 4281 _soc_ml_mmu_params.num_ge_int_ports_d); 4282 4283 4284 /* C72 = C19*C17 */ 4285 general_info->total_egr_queues_for_a_int_hg_ports = 4286 (_soc_ml_mmu_params.num_egr_queue_per_int_hg_port_d * 4287 _soc_ml_mmu_params.num_hg_int_ports_d); 4288 4289 4290 /* C73 = C20*C21 */ 4291 general_info->total_cpu_queues = 4292 (_soc_ml_mmu_params.mmu_num_cpu_port * 4293 _soc_ml_mmu_params.mmu_num_cpu_queue); 4294 4295 /* C74 = $C$71+$C$72+C73+C26*C25+C22*C23+C22*C24 */ 4296 general_info->total_base_queue_int_buff = 4297 (general_info->total_egr_queues_for_a_int_ge_ports + 4298 general_info->total_egr_queues_for_a_int_hg_ports + 4299 general_info->total_cpu_queues); 4300 if (_soc_ml_mmu_params.olp_port_int_ext_bounding_d_c == 0) { 4301 general_info->total_base_queue_int_buff += 4302 (_soc_ml_mmu_params.mmu_num_olp_queue * 4303 _soc_ml_mmu_params.mmu_num_olp_port_d); 4304 } 4305 general_info->total_base_queue_int_buff += 4306 (_soc_ml_mmu_params.mmu_num_loopback_queue * 4307 _soc_ml_mmu_params.mmu_num_loopback_port); 4308 general_info->total_base_queue_int_buff += 4309 ((_soc_ml_mmu_params.mmu_num_ep_redirection_queue * 4310 _soc_ml_mmu_params.mmu_num_loopback_port)/ 2); 4311 4312 if (_soc_ml_mmu_params.olp_port_int_ext_bounding_d_c) { 4313 general_info->total_base_queue_ext_buff += 4314 (_soc_ml_mmu_params.mmu_num_olp_queue * 4315 _soc_ml_mmu_params.mmu_num_olp_port_d); 4316 } 4317 4318 /* C74 */ 4319 general_info->total_egr_base_queues_in_device = 4320 general_info->total_base_queue_int_buff + 4321 general_info->total_base_queue_ext_buff; 4322 /* C75 = C27 */ 4323 general_info->total_egr_queues_in_device = 4324 _soc_ml_mmu_params.mmu_total_egress_queue ; 4325 4326 /* C95 = C42-C44*/ 4327 general_info->max_int_cell_buff_size = 4328 _soc_ml_mmu_params.mmu_int_buf_size - 4329 _soc_ml_mmu_params.mmu_reserved_int_buf_cells ; 4330 4331 /* C96 = C95 */ 4332 general_info->int_cell_buff_size_after_limitation = 4333 general_info->max_int_cell_buff_size; 4334 4335 general_info->int_buff_pool = general_info->max_int_cell_buff_size; 4336 4337 /* C99 =IF(C17=1,FLOOR($C$45*(IF($C$46,$C$96,$C$95))-C41,1),0) */ 4338 if (_soc_ml_mmu_params.internal_buffer_reduction_d_c) { 4339 temp_val = general_info->int_cell_buff_size_after_limitation; 4340 } else { 4341 temp_val = general_info->max_int_cell_buff_size;; 4342 } 4343 temp_val = (temp_val * _soc_ml_mmu_params.mmu_reserved_int_buf_ema_pool_size_d)/100; 4344 temp_val = temp_val - _soc_ml_mmu_params.mmu_pipeline_lat_cpap_admission; 4345 4346 /* C101 =C52*1024-C53*/ 4347 general_info->repl_engine_work_queue_entries = 4348 _soc_ml_mmu_params.mmu_repl_engine_work_queue_entries*1024 - 4349 _soc_ml_mmu_params.mmu_resv_repl_engine_work_queue_entries; 4350 4351 4352 /* C104 = 1 */ 4353 general_info->int_buff_cells_per_avg_size_pkt = 1; 4354 4355 4356 /* C106 = 0.75 but normalized to 1 */ 4357 general_info->max_prop_of_buff_used_by_one_queue_port = 75; 4358 4359 4360 /* Fill up input threshold info */ 4361 /* C110 =CEILING(C7*2/C9, 1) */ 4362 input_port_threshold->global_hdrm_cells_for_int_buff_ingress_pool = sal_ceil_func 4363 (_soc_ml_mmu_params.mmu_max_pkt_size * 2 , 4364 _soc_ml_mmu_params.mmu_int_buf_cell_size); 4365 4366 /* C113 */ 4367 input_port_threshold->global_hdrm_cells_for_RE_WQEs = 0 ; 4368 /* C114 */ 4369 input_port_threshold->global_hdrm_cells_for_EQEs = 0 ; 4370 if (_soc_ml_mmu_params.lossless_mode_d_c) { 4371 /* C115*/ 4372 input_port_threshold->hdrm_int_buff_cells_for_10G_PG = 178; 4373 /* C116*/ 4374 input_port_threshold->hdrm_ema_buff_cells_for_10G_PG = 0; 4375 /* C117*/ 4376 input_port_threshold->hdrm_RE_WQEs_pkts_for_10G_PG = 66; 4377 /* C119 =IF(C14=0, 0, C118*C51)*/ 4378 input_port_threshold->hdrm_EQEs_pkts_for_10G_PG = 4379 input_port_threshold->hdrm_RE_WQEs_pkts_for_10G_PG * 4380 _soc_ml_mmu_params.mmu_exp_num_of_repl_per_pkt ; 4381 } else { 4382 /* C115*/ 4383 input_port_threshold->hdrm_int_buff_cells_for_10G_PG = 0; 4384 /* C116*/ 4385 input_port_threshold->hdrm_ema_buff_cells_for_10G_PG = 0; 4386 /* C118*/ 4387 input_port_threshold->hdrm_RE_WQEs_pkts_for_10G_PG = 0; 4388 /* C119*/ 4389 input_port_threshold->hdrm_EQEs_pkts_for_10G_PG = 0; 4390 } 4391 4392 /* C120 = =C25*C16*$C$115 */ 4393 input_port_threshold->hdrm_int_buff_cells_for_10G_total_PG = 4394 (_soc_ml_mmu_params.num_hg_ports_d * 4395 _soc_ml_mmu_params.mmu_lossless_pg_num * 4396 input_port_threshold->hdrm_int_buff_cells_for_10G_PG); 4397 4398 /* C121 = C25*C16*C116 */ 4399 input_port_threshold->hdrm_ema_buff_cells_for_10G_total_PG = 4400 (_soc_ml_mmu_params.num_hg_ports_d * 4401 _soc_ml_mmu_params.mmu_lossless_pg_num * 4402 input_port_threshold->hdrm_ema_buff_cells_for_10G_PG); 4403 4404 /* C123 = C25*C16*C118 */ 4405 input_port_threshold->hdrm_RE_WQEs_pkts_for_10G_total_PG = 4406 (_soc_ml_mmu_params.num_hg_ports_d * 4407 _soc_ml_mmu_params.mmu_lossless_pg_num * 4408 input_port_threshold->hdrm_RE_WQEs_pkts_for_10G_PG); 4409 4410 /* C124 = C25*C16*C119 */ 4411 input_port_threshold->hdrm_EQEs_pkts_for_10G_total_PG = 4412 (_soc_ml_mmu_params.num_hg_ports_d * 4413 _soc_ml_mmu_params.mmu_lossless_pg_num * 4414 input_port_threshold->hdrm_EQEs_pkts_for_10G_PG); 4415 4416 if (_soc_ml_mmu_params.lossless_mode_d_c) { 4417 /* C125 */ 4418 input_port_threshold->hdrm_int_buff_cells_for_1G_PG = 130; 4419 /* C126 */ 4420 input_port_threshold->hdrm_ema_buff_cells_for_1G_PG = 0; 4421 /* C128*/ 4422 input_port_threshold->hdrm_RE_WQEs_pkts_for_1G_PG = 23; 4423 /* C129 =IF(C14=0, 0, C128*C51) */ 4424 input_port_threshold->hdrm_EQEs_pkts_for_1G_PG = 4425 input_port_threshold->hdrm_RE_WQEs_pkts_for_1G_PG * 4426 _soc_ml_mmu_params.mmu_exp_num_of_repl_per_pkt; 4427 } else { 4428 /* C125 */ 4429 input_port_threshold->hdrm_int_buff_cells_for_1G_PG = 0; 4430 /* C126 */ 4431 input_port_threshold->hdrm_ema_buff_cells_for_1G_PG = 0; 4432 /* C128*/ 4433 input_port_threshold->hdrm_RE_WQEs_pkts_for_1G_PG = 0; 4434 /* C129*/ 4435 input_port_threshold->hdrm_EQEs_pkts_for_1G_PG = 0; 4436 } 4437 4438 /* C130 =C19*C16*$C$125 */ 4439 input_port_threshold->hdrm_int_buff_cells_for_1G_total_PG = 4440 (_soc_ml_mmu_params.num_ge_ports_d * 4441 _soc_ml_mmu_params.mmu_lossless_pg_num * 4442 input_port_threshold->hdrm_int_buff_cells_for_1G_PG); 4443 4444 /* C131 = C19*C16*$C$126 */ 4445 input_port_threshold->hdrm_ema_buff_cells_for_1G_total_PG = 4446 (_soc_ml_mmu_params.num_ge_ports_d * 4447 _soc_ml_mmu_params.mmu_lossless_pg_num * 4448 input_port_threshold->hdrm_ema_buff_cells_for_1G_PG); 4449 4450 /* C133 = C19*C16*$C$128 */ 4451 input_port_threshold->hdrm_RE_WQEs_pkts_for_1G_total_PG = 4452 (_soc_ml_mmu_params.num_ge_ports_d * 4453 _soc_ml_mmu_params.mmu_lossless_pg_num * 4454 input_port_threshold->hdrm_RE_WQEs_pkts_for_1G_PG); 4455 4456 /* C134 = C19*C16*$C$129 */ 4457 input_port_threshold->hdrm_EQEs_pkts_for_1G_total_PG = 4458 (_soc_ml_mmu_params.num_ge_ports_d * 4459 _soc_ml_mmu_params.mmu_lossless_pg_num * 4460 input_port_threshold->hdrm_EQEs_pkts_for_1G_PG); 4461 4462 /* C132-C135 values are zero for lossy mode */ 4463 if (_soc_ml_mmu_params.lossless_mode_d_c) { 4464 /* C135 */ 4465 input_port_threshold->hdrm_int_buff_cells_for_olp_port = 180; 4466 /* C136 */ 4467 input_port_threshold->hdrm_ema_buff_cells_for_olp_port = 0; 4468 /* C138 */ 4469 input_port_threshold->hdrm_RE_WQEs_pkts_for_olp_port = 7; 4470 /* C139 = C138*C51 */ 4471 input_port_threshold->hdrm_EQEs_pkts_for_olp_port = 4472 input_port_threshold->hdrm_RE_WQEs_pkts_for_olp_port * 4473 _soc_ml_mmu_params.mmu_exp_num_of_repl_per_pkt; 4474 } else { 4475 /* C135 */ 4476 input_port_threshold->hdrm_int_buff_cells_for_olp_port = 0; 4477 /* C136 */ 4478 input_port_threshold->hdrm_int_buff_cells_for_olp_port = 0; 4479 /* C138 */ 4480 input_port_threshold->hdrm_RE_WQEs_pkts_for_olp_port = 0; 4481 /* C139 */ 4482 input_port_threshold->hdrm_EQEs_pkts_for_olp_port = 0; 4483 } 4484 4485 /* C140 = 44 */ 4486 input_port_threshold->hdrm_int_buff_cells_for_lpbk_port = 44; 4487 4488 /* C143 = =IF(C14=0, 23, 23) */ 4489 input_port_threshold->hdrm_RE_WQEs_pkts_for_lpbk_port = 23; 4490 4491 /* C144 = C143*C51 */ 4492 input_port_threshold->hdrm_EQEs_pkts_for_lpbk_port = 4493 input_port_threshold->hdrm_RE_WQEs_pkts_for_lpbk_port * 4494 _soc_ml_mmu_params.mmu_exp_num_of_repl_per_pkt; 4495 4496 /* C145 = 44 */ 4497 input_port_threshold->hdrm_int_buff_cells_for_cpu_port = 44; 4498 4499 /* C148 =IF(C14=0, 23, 23) */ 4500 input_port_threshold->hdrm_RE_WQEs_pkts_for_cpu_port = 23; 4501 4502 /* C149 = C148*C51 */ 4503 input_port_threshold->hdrm_EQEs_pkts_for_cpu_port = 4504 input_port_threshold->hdrm_RE_WQEs_pkts_for_cpu_port * 4505 _soc_ml_mmu_params.mmu_exp_num_of_repl_per_pkt; 4506 4507 /* C150 =$C$110+$C$120+$C$130+C135+C140+C145*/ 4508 input_port_threshold->total_hdrm_int_buff_cells = 4509 input_port_threshold->global_hdrm_cells_for_int_buff_ingress_pool + 4510 input_port_threshold->hdrm_int_buff_cells_for_10G_total_PG + 4511 input_port_threshold->hdrm_int_buff_cells_for_1G_total_PG + 4512 input_port_threshold->hdrm_int_buff_cells_for_olp_port + 4513 input_port_threshold->hdrm_int_buff_cells_for_lpbk_port + 4514 input_port_threshold->hdrm_int_buff_cells_for_cpu_port; 4515 4516 /* C151 = =C111+C121+C131+C136+C141+C146*/ 4517 input_port_threshold->total_hdrm_int_buff_ema_pool_cells = 4518 input_port_threshold->global_hdrm_cells_for_int_buff_ema_pool + 4519 input_port_threshold->hdrm_ema_buff_cells_for_10G_total_PG + 4520 input_port_threshold->hdrm_ema_buff_cells_for_1G_total_PG + 4521 input_port_threshold->hdrm_ema_buff_cells_for_olp_port + 4522 input_port_threshold->hdrm_ema_buff_cells_for_lpbk_port + 4523 input_port_threshold->hdrm_ema_buff_cells_for_cpu_port; 4524 4525 4526 /* C153 = =$C$113+$C$123+$C$133+C138+C143+C148 */ 4527 input_port_threshold->total_hdrm_RE_WQEs_pkts = 4528 input_port_threshold->global_hdrm_cells_for_RE_WQEs+ 4529 input_port_threshold->hdrm_RE_WQEs_pkts_for_10G_total_PG+ 4530 input_port_threshold->hdrm_RE_WQEs_pkts_for_1G_total_PG+ 4531 input_port_threshold->hdrm_RE_WQEs_pkts_for_olp_port+ 4532 input_port_threshold->hdrm_RE_WQEs_pkts_for_lpbk_port+ 4533 input_port_threshold->hdrm_RE_WQEs_pkts_for_cpu_port; 4534 4535 /* C154 =$C$114+$C$124+$C$134+C139+C144+C149*/ 4536 input_port_threshold->total_hdrm_EQEs_pkts = 4537 input_port_threshold->global_hdrm_cells_for_EQEs+ 4538 input_port_threshold->hdrm_EQEs_pkts_for_10G_total_PG+ 4539 input_port_threshold->hdrm_EQEs_pkts_for_1G_total_PG+ 4540 input_port_threshold->hdrm_EQEs_pkts_for_olp_port+ 4541 input_port_threshold->hdrm_EQEs_pkts_for_lpbk_port+ 4542 input_port_threshold->hdrm_EQEs_pkts_for_cpu_port; 4543 4544 /* C156 = $C$73 */ 4545 input_port_threshold->min_int_buff_cells_per_PG = 4546 general_info->jumbo_frame_for_int_buff; 4547 4548 /* C159 */ 4549 input_port_threshold->min_RE_WQEs_pkt_per_PG = 9; 4550 4551 /* C160 = =$C$159*C51 */ 4552 input_port_threshold->min_EQEs_pkt_per_PG = 4553 input_port_threshold->min_RE_WQEs_pkt_per_PG * 4554 _soc_ml_mmu_params.mmu_exp_num_of_repl_per_pkt; 4555 4556 /* C162 = =C79*C16*$C$156 */ 4557 input_port_threshold->min_int_buff_cells_for_total_PG = 4558 (general_info->total_num_of_ports * 4559 _soc_ml_mmu_params.mmu_lossless_pg_num * 4560 input_port_threshold->min_int_buff_cells_per_PG) ; 4561 4562 /* C163 = =C79*C16*$C$157 */ 4563 input_port_threshold->min_int_buff_ema_pool_cells_for_total_PG = 4564 (general_info->total_num_of_ports * 4565 _soc_ml_mmu_params.mmu_lossless_pg_num * 4566 input_port_threshold->min_int_buff_ema_pool_cells_per_PG); 4567 4568 /* C165 = C75*C16*$C$159 */ 4569 input_port_threshold->min_RE_WQEs_pkts_for_total_PG = 4570 (general_info->total_num_of_ports * 4571 _soc_ml_mmu_params.mmu_lossless_pg_num * 4572 input_port_threshold->min_RE_WQEs_pkt_per_PG) ; 4573 4574 /* C166 = C75*C16*$C$160 */ 4575 input_port_threshold->min_EQEs_pkts_for_total_PG = 4576 (general_info->total_num_of_ports * 4577 _soc_ml_mmu_params.mmu_lossless_pg_num * 4578 input_port_threshold->min_EQEs_pkt_per_PG) ; 4579 4580 /* C168 C169 C170 C171 C172= 0 */ 4581 input_port_threshold->min_int_buff_cells_for_a_port = 0; 4582 input_port_threshold->min_int_buff_ema_pool_cells_for_a_port = 0; 4583 input_port_threshold->min_RE_WQEs_pkts_for_a_port = 0; 4584 input_port_threshold->min_EQEs_pkts_for_a_port = 0; 4585 4586 /* C174 =$C$79*$C$168 */ 4587 input_port_threshold->min_int_buff_cells_for_total_port = 4588 (general_info->total_num_of_ports * 4589 input_port_threshold->min_int_buff_cells_for_a_port); 4590 4591 /* C175 = $C$75*$C$169 */ 4592 input_port_threshold->min_int_buff_ema_pool_cells_for_total_port = 4593 (general_info->total_num_of_ports * 4594 input_port_threshold->min_int_buff_ema_pool_cells_for_a_port); 4595 4596 4597 /* C177 = $C$75*$C$171 */ 4598 input_port_threshold->min_RE_WQEs_pkts_for_total_port = 4599 (general_info->total_num_of_ports * 4600 input_port_threshold->min_RE_WQEs_pkts_for_a_port); 4601 4602 /* C179 = $C$75*$C$172 */ 4603 input_port_threshold->min_EQEs_pkts_for_total_port = 4604 (general_info->total_num_of_ports * 4605 input_port_threshold->min_EQEs_pkts_for_a_port); 4606 4607 /* C180 =$C$162+$C$174 */ 4608 input_port_threshold->total_min_int_buff_cells = 4609 input_port_threshold->min_int_buff_cells_for_total_PG + 4610 input_port_threshold->min_int_buff_cells_for_total_port; 4611 4612 /* C181 = $C$163+$C$175 */ 4613 input_port_threshold->total_min_int_buff_ema_pool_cells = 4614 input_port_threshold->min_int_buff_ema_pool_cells_for_total_PG + 4615 input_port_threshold->min_int_buff_ema_pool_cells_for_total_port; 4616 4617 4618 /* C183 = $C$165+$C$177 */ 4619 input_port_threshold->total_min_RE_WQEs_pkts = 4620 input_port_threshold->min_RE_WQEs_pkts_for_total_PG + 4621 input_port_threshold->min_RE_WQEs_pkts_for_total_port; 4622 4623 /* C184 = $C$166+$C$178 */ 4624 input_port_threshold->total_min_EQEs_pkts = 4625 input_port_threshold->min_EQEs_pkts_for_total_PG + 4626 input_port_threshold->min_EQEs_pkts_for_total_port; 4627 4628 4629 /* Fill up output threshold info */ 4630 /* C204 = =IF(C14=0, C58, 0) */ 4631 if (_soc_ml_mmu_params.lossless_mode_d_c == 0) { 4632 output_port_threshold->min_grntd_res_queue_cells_int_buff = 4633 _soc_ml_mmu_params.per_cos_res_cells_for_int_buff_d; 4634 } 4635 /* C206 = =IF(C14=0, $C$58/$C$105, 0) */ 4636 if (_soc_ml_mmu_params.lossless_mode_d_c == 0) { 4637 output_port_threshold->min_grntd_res_queue_cells_EQEs = 4638 _soc_ml_mmu_params.per_cos_res_cells_for_int_buff_d; 4639 } 4640 /* C208 = C204 */ 4641 output_port_threshold->min_grntd_res_RE_WQs_cells = 4642 output_port_threshold->min_grntd_res_queue_cells_int_buff; 4643 4644 /* C209 = C204 */ 4645 output_port_threshold->min_grntd_res_RE_WQs_queue_cells_for_int_buff = 4646 output_port_threshold->min_grntd_res_queue_cells_int_buff; 4647 4648 4649 /* C211 = 4 */ 4650 output_port_threshold->min_grntd_res_EP_redirect_queue_entry_cells = 4; 4651 4652 4653 /* C213 =C89*$C$204 */ 4654 output_port_threshold->min_grntd_tot_res_queue_cells_int_buff = 4655 general_info->total_base_queue_int_buff * 4656 output_port_threshold->min_grntd_res_queue_cells_int_buff; 4657 4658 4659 /* C215 =C94*$C$206 */ 4660 output_port_threshold->min_grntd_tot_res_queue_cells_EQEs = 4661 general_info->total_egr_base_queues_in_device * 4662 output_port_threshold->min_grntd_res_queue_cells_EQEs; 4663 4664 /* C216 =$C$55*$C$207 */ 4665 output_port_threshold->min_grntd_tot_res_EMA_queue_cells = 4666 _soc_ml_mmu_params.mmu_ema_queues * 4667 output_port_threshold->min_grntd_res_EMA_queue_cells; 4668 4669 /* C217 =$C$54*$C$208 */ 4670 output_port_threshold->min_grntd_tot_res_RE_WQs_cells = 4671 _soc_ml_mmu_params.mmu_repl_engine_work_queue_in_device * 4672 output_port_threshold->min_grntd_res_RE_WQs_cells; 4673 4674 /* C218 =$C$54*$C$209 */ 4675 output_port_threshold->min_grntd_tot_res_RE_WQs_queue_cells_for_int_buff = 4676 _soc_ml_mmu_params.mmu_repl_engine_work_queue_in_device * 4677 output_port_threshold->min_grntd_res_RE_WQs_queue_cells_for_int_buff; 4678 4679 4680 /* C220 =C211*(C36) */ 4681 output_port_threshold->min_grntd_tot_res_EP_redirect_queue_entry_cells = 4682 (_soc_ml_mmu_params.mmu_num_ep_redirection_queue * 4683 output_port_threshold->min_grntd_res_EP_redirect_queue_entry_cells)/2; 4684 4685 4686 /* C186 =$C$98-$C$150-$C$180-IF(C14=0, 0, C213)-IF(C14=0, 0, C218) */ 4687 4688 input_port_threshold->total_shared_ing_buff_pool = 4689 general_info->int_buff_pool - 4690 input_port_threshold->total_min_int_buff_cells - 4691 input_port_threshold->total_hdrm_int_buff_cells; 4692 if (_soc_ml_mmu_params.lossless_mode_d_c) { 4693 input_port_threshold->total_shared_ing_buff_pool -= 4694 output_port_threshold->min_grntd_tot_res_queue_cells_int_buff; 4695 input_port_threshold->total_shared_ing_buff_pool -= 4696 output_port_threshold->min_grntd_tot_res_RE_WQs_queue_cells_for_int_buff; 4697 } 4698 4699 4700 4701 /* C189 =$C$101-$C$153-$C$183-IF(C14=0, 0, C217) */ 4702 input_port_threshold->total_shared_RE_WQEs_buff = 4703 general_info->repl_engine_work_queue_entries - 4704 input_port_threshold->total_hdrm_RE_WQEs_pkts - 4705 input_port_threshold->total_min_RE_WQEs_pkts; 4706 if (_soc_ml_mmu_params.lossless_mode_d_c) { 4707 input_port_threshold->total_shared_RE_WQEs_buff -= 4708 output_port_threshold->min_grntd_tot_res_RE_WQs_cells; 4709 } 4710 4711 /* C190 =($C$49*1024)-$C$154-$C$184-IF(C14=0, 0, C215)-1 */ 4712 input_port_threshold->total_shared_EQEs_buff = 4713 (_soc_ml_mmu_params.mmu_egress_queue_entries * 1024) - 4714 input_port_threshold->total_hdrm_EQEs_pkts - 4715 input_port_threshold->total_min_EQEs_pkts; 4716 if (_soc_ml_mmu_params.lossless_mode_d_c) { 4717 input_port_threshold->total_shared_EQEs_buff -= 4718 output_port_threshold->min_grntd_tot_res_queue_cells_EQEs; 4719 } 4720 input_port_threshold->total_shared_EQEs_buff -= 1; 4721 4722 /* C192 =FLOOR(($C$60*$C$186)/(1+($C$60*1)),1) */ 4723 input_port_threshold->ingress_burst_cells_size_for_one_port = sal_floor_func( 4724 (_soc_ml_mmu_params.mmu_ing_port_dyn_thd_param * 4725 input_port_threshold->total_shared_ing_buff_pool), 4726 (1+(_soc_ml_mmu_params.mmu_ing_port_dyn_thd_param*1))); 4727 4728 /* C193 =FLOOR(($C$60*$C$190)/(1+($C$60*1)),1) */ 4729 input_port_threshold->ingress_burst_pkts_size_for_one_port = sal_floor_func( 4730 (_soc_ml_mmu_params.mmu_ing_port_dyn_thd_param * 4731 input_port_threshold->total_shared_EQEs_buff), 4732 (1+(_soc_ml_mmu_params.mmu_ing_port_dyn_thd_param*1))); 4733 4734 /* C194 =FLOOR(($C$60*$C$186)/(1+($C$60*$C$79)),1) */ 4735 input_port_threshold->ingress_burst_cells_size_for_all_ports = sal_floor_func( 4736 (_soc_ml_mmu_params.mmu_ing_port_dyn_thd_param * 4737 input_port_threshold->total_shared_ing_buff_pool), 4738 (1+(_soc_ml_mmu_params.mmu_ing_port_dyn_thd_param* 4739 general_info->total_num_of_ports))); 4740 4741 /* C195 =($C$194+$C$168+C156)*$C$79 */ 4742 input_port_threshold->ingress_total_shared_cells_use_for_all_port = 4743 (input_port_threshold->ingress_burst_cells_size_for_all_ports + 4744 input_port_threshold->min_int_buff_cells_for_a_port + 4745 input_port_threshold->min_int_buff_cells_per_PG) * 4746 general_info->total_num_of_ports; 4747 4748 /* C196 =FLOOR(($C$60*$C$190)/(1+($C$60*$C$79)),1) */ 4749 input_port_threshold->ingress_burst_pkts_size_for_all_port = sal_floor_func( 4750 _soc_ml_mmu_params.mmu_ing_port_dyn_thd_param * 4751 input_port_threshold->total_shared_EQEs_buff, 4752 (1+(_soc_ml_mmu_params.mmu_ing_port_dyn_thd_param* 4753 general_info->total_num_of_ports))); 4754 4755 /* C197 =($C$196+$C$172+C160)*$C$79 */ 4756 input_port_threshold->ingress_total_shared_pkts_use_for_all_port = 4757 (input_port_threshold->ingress_burst_pkts_size_for_all_port+ 4758 input_port_threshold->min_EQEs_pkts_for_a_port + 4759 input_port_threshold->min_EQEs_pkt_per_PG) * 4760 general_info->total_num_of_ports; 4761 4762 /* C198 = =$C$195+C150 */ 4763 input_port_threshold->ingress_total_shared_hdrm_cells_use_for_all_port = 4764 input_port_threshold->ingress_total_shared_cells_use_for_all_port + 4765 input_port_threshold->total_hdrm_int_buff_cells; 4766 4767 /* C199 = =$C$197+C154 */ 4768 input_port_threshold->ingress_total_shared_hdrm_pkts_use_for_all_port = 4769 input_port_threshold->ingress_total_shared_pkts_use_for_all_port + 4770 input_port_threshold->total_hdrm_EQEs_pkts; 4771 4772 /* C222 =C98-$C$213-C218 */ 4773 output_port_threshold->min_grntd_tot_shr_queue_cells_int_buff = 4774 general_info->int_buff_pool - 4775 output_port_threshold-> 4776 min_grntd_tot_res_queue_cells_int_buff- 4777 output_port_threshold-> 4778 min_grntd_tot_res_RE_WQs_queue_cells_for_int_buff; 4779 4780 4781 /* C224 =$C$49*1024-$C$215-1 */ 4782 output_port_threshold->min_grntd_tot_shr_queue_cells_EQEs = 4783 (_soc_ml_mmu_params.mmu_egress_queue_entries*1024) - 4784 output_port_threshold->min_grntd_tot_res_queue_cells_EQEs - 1; 4785 4786 /* C225 =$C$99-$C$216 */ 4787 output_port_threshold->min_grntd_tot_shr_EMA_queue_cells = 4788 general_info->ema_pool - 4789 output_port_threshold->min_grntd_tot_res_EMA_queue_cells; 4790 4791 /* C226 =$C$101-$C$217 */ 4792 output_port_threshold->min_grntd_tot_shr_RE_WQs_cells = 4793 general_info->repl_engine_work_queue_entries - 4794 output_port_threshold->min_grntd_tot_res_RE_WQs_cells ; 4795 4796 /* C227 =C222 */ 4797 output_port_threshold->min_grntd_tot_shr_RE_WQs_queue_cells_for_int_buff = 4798 output_port_threshold->min_grntd_tot_shr_queue_cells_int_buff ; 4799 4800 4801 /* C229 =C50-C220 */ 4802 output_port_threshold->min_grntd_tot_shr_EP_redirect_queue_entry_cells = 4803 _soc_ml_mmu_params.mmu_ep_redirect_queue_entries - 4804 output_port_threshold->min_grntd_tot_res_EP_redirect_queue_entry_cells; 4805 4806 /* C230 = 2 */ 4807 output_port_threshold->egress_queue_dynamic_threshold_parameter = 2; 4808 4809 /* C231 =FLOOR( ($C$62*$C$222)/(1+($C$62*1)), 1) */ 4810 output_port_threshold->egress_burst_cells_size_for_one_queue = sal_floor_func( 4811 (_soc_ml_mmu_params.mmu_egr_queue_dyn_thd_param_baf * 4812 output_port_threshold->min_grntd_tot_shr_queue_cells_int_buff), 4813 (1 + (_soc_ml_mmu_params.mmu_egr_queue_dyn_thd_param_baf*1))); 4814 4815 /* C232 =FLOOR( ($C$62*$C$224)/(1+($C$62*1)), 1) */ 4816 output_port_threshold->egress_burst_pkts_size_for_one_queue = sal_floor_func( 4817 (_soc_ml_mmu_params.mmu_egr_queue_dyn_thd_param_baf * 4818 output_port_threshold->min_grntd_tot_shr_queue_cells_EQEs), 4819 (1 + (_soc_ml_mmu_params.mmu_egr_queue_dyn_thd_param_baf * 1))); 4820 4821 /* C233 = =FLOOR( ($C$62*$C$222)/(1+($C$62*$C$79)), 1)*/ 4822 output_port_threshold->egress_burst_cells_size_for_all_ports = sal_floor_func( 4823 (_soc_ml_mmu_params.mmu_egr_queue_dyn_thd_param_baf * 4824 output_port_threshold->min_grntd_tot_shr_queue_cells_int_buff), 4825 (1 + (_soc_ml_mmu_params.mmu_egr_queue_dyn_thd_param_baf * 4826 general_info->total_num_of_ports))); 4827 4828 /* C234 =FLOOR( ($C$62*$C$224)/(1+($C$62*$C$79)), 1) */ 4829 output_port_threshold->egress_burst_pkts_size_for_all_ports = sal_floor_func( 4830 (_soc_ml_mmu_params.mmu_egr_queue_dyn_thd_param_baf * 4831 output_port_threshold->min_grntd_tot_shr_queue_cells_EQEs), 4832 (1 + (_soc_ml_mmu_params.mmu_egr_queue_dyn_thd_param_baf * 4833 general_info->total_num_of_ports))); 4834 4835 /* C235 =FLOOR( ($C$62*$C$222)/(1+($C$62*C93)), 1) */ 4836 output_port_threshold->egress_burst_cells_size_for_all_queues = sal_floor_func( 4837 (_soc_ml_mmu_params.mmu_egr_queue_dyn_thd_param_baf * 4838 output_port_threshold->min_grntd_tot_shr_queue_cells_int_buff), 4839 (1 + (_soc_ml_mmu_params.mmu_egr_queue_dyn_thd_param_baf * 4840 general_info->total_egr_base_queues_in_device))); 4841 4842 /* C236 =FLOOR( ($C$62*$C$224)/(1+($C$62*C93)), 1) */ 4843 output_port_threshold->egress_burst_pkts_size_for_all_queues = sal_floor_func( 4844 (_soc_ml_mmu_params.mmu_egr_queue_dyn_thd_param_baf * 4845 output_port_threshold->min_grntd_tot_shr_queue_cells_EQEs), 4846 (1 + (_soc_ml_mmu_params.mmu_egr_queue_dyn_thd_param_baf * 4847 general_info->total_egr_base_queues_in_device))); 4848 4849 /* C237 =C93*$C$235 */ 4850 output_port_threshold->egress_total_use_in_cells_for_all_queues = 4851 general_info->total_egr_base_queues_in_device * 4852 output_port_threshold->egress_burst_cells_size_for_all_queues; 4853 4854 /* C238 =C93*$C$236 */ 4855 output_port_threshold->egress_total_use_in_pkts_for_all_queues = 4856 general_info->total_egr_base_queues_in_device * 4857 output_port_threshold->egress_burst_pkts_size_for_all_queues; 4858 4859 /* C239 =$C$222-C237*/ 4860 output_port_threshold->egress_remaining_cells_for_all_queues = 4861 output_port_threshold->min_grntd_tot_shr_queue_cells_int_buff - 4862 output_port_threshold->egress_total_use_in_cells_for_all_queues; 4863 4864 /* C240 =$C$224-C238*/ 4865 output_port_threshold->egress_remaining_pkts_for_all_queues = 4866 output_port_threshold->min_grntd_tot_shr_queue_cells_EQEs - 4867 output_port_threshold->egress_total_use_in_pkts_for_all_queues; 4868 4869 4870 /*======================================================================== */ 4871 /* Device Wide Registers */ 4872 /* ======================================================================= */ 4873 4874 if (flex_port == -1) { 4875 /* This is flex operation. so no need to re-configure */ 4876 4877 /* C244: CFAPICONFIG.CFAPIPOOLSIZE =C42+22 */ 4878 SOC_IF_ERROR_RETURN(READ_CFAPICONFIGr(unit, &rval)); 4879 soc_reg_field_set(unit, CFAPICONFIGr, &rval, CFAPIPOOLSIZEf, 4880 _soc_ml_mmu_params.mmu_int_buf_size + 22 ); 4881 SOC_IF_ERROR_RETURN(WRITE_CFAPICONFIGr(unit, rval)); 4882 4883 4884 /* C245: CFAPIFULLSETPOINT.CFAPIFULLSETPOINT = =C96 */ 4885 SOC_IF_ERROR_RETURN(READ_CFAPIFULLSETPOINTr(unit, &rval)); 4886 soc_reg_field_set(unit, CFAPIFULLSETPOINTr, &rval, CFAPIFULLSETPOINTf, 4887 general_info->int_cell_buff_size_after_limitation); 4888 SOC_IF_ERROR_RETURN(WRITE_CFAPIFULLSETPOINTr(unit, rval)); 4889 4890 /* C246: CFAPIFULLRESETPOINT.CFAPIFULLRESETPOINT =C244-128 */ 4891 SOC_IF_ERROR_RETURN(READ_CFAPIFULLRESETPOINTr(unit, &rval)); 4892 soc_reg_field_set(unit, CFAPIFULLRESETPOINTr, &rval, CFAPIFULLRESETPOINTf, 4893 _soc_ml_mmu_params.mmu_int_buf_size + 22 - 128 ); 4894 SOC_IF_ERROR_RETURN(WRITE_CFAPIFULLRESETPOINTr(unit, rval)); 4895 4896 /* C250: MMU_ENQ_FAPCONFIG_0.FAPPOOLSIZE =C52*1024-1*/ 4897 SOC_IF_ERROR_RETURN(READ_MMU_ENQ_FAPCONFIG_0r(unit, &rval)); 4898 /*soc_reg_field_set(unit, MMU_ENQ_FAPCONFIG_0r, &rval, FAPPOOLSIZEf, 4899 (_soc_ml_mmu_params.mmu_repl_engine_work_queue_entries*1024 - 1 )); */ 4900 soc_reg_field_set(unit, MMU_ENQ_FAPCONFIG_0r, &rval, FAPPOOLSIZEf, 1344); 4901 SOC_IF_ERROR_RETURN(WRITE_MMU_ENQ_FAPCONFIG_0r(unit, rval)); 4902 temp_val = 1344; 4903 4904 /* C251 MMU_ENQ_FAPFULLSETPOINT_0.FAPFULLSETPOINT =C250-64 */ 4905 SOC_IF_ERROR_RETURN(READ_MMU_ENQ_FAPFULLSETPOINT_0r(unit, &rval)); 4906 soc_reg_field_set(unit, MMU_ENQ_FAPFULLSETPOINT_0r, &rval, FAPFULLSETPOINTf, 4907 temp_val - 64); 4908 SOC_IF_ERROR_RETURN(WRITE_MMU_ENQ_FAPFULLSETPOINT_0r(unit, rval)); 4909 4910 /* C252 MMU_ENQ_FAPFULLRESETPOINT_0.FAPFULLRESETPOINT =C250-128 */ 4911 SOC_IF_ERROR_RETURN(READ_MMU_ENQ_FAPFULLRESETPOINT_0r(unit, &rval)); 4912 soc_reg_field_set(unit, MMU_ENQ_FAPFULLRESETPOINT_0r, &rval, FAPFULLRESETPOINTf, 4913 temp_val - 128 ); 4914 SOC_IF_ERROR_RETURN(WRITE_MMU_ENQ_FAPFULLRESETPOINT_0r(unit, rval)); 4915 4916 /* C253: QSTRUCT_FAPCONFIG.FAPPOOLSIZE =(C49*1024+1024*3)/4 */ 4917 temp_val = (((_soc_ml_mmu_params.mmu_egress_queue_entries * 1024 ) + (1024 *3))/4); 4918 for (idx =0 ; idx < 1; idx++) { 4919 SOC_IF_ERROR_RETURN(READ_QSTRUCT_FAPCONFIGr(unit, idx, &rval)); 4920 soc_reg_field_set(unit, QSTRUCT_FAPCONFIGr, &rval, FAPPOOLSIZEf, 4921 temp_val); 4922 SOC_IF_ERROR_RETURN(WRITE_QSTRUCT_FAPCONFIGr(unit, idx, rval)); 4923 } 4924 /* C254 QSTRUCT_FAPFULLSETPOINT.FAPFULLSETPOINT = C253 - 8 */ 4925 temp_val = temp_val - 8; 4926 for (idx =0 ; idx < 1; idx++) { 4927 SOC_IF_ERROR_RETURN(READ_QSTRUCT_FAPFULLSETPOINTr(unit, idx, &rval)); 4928 soc_reg_field_set(unit, QSTRUCT_FAPFULLSETPOINTr, &rval, FAPFULLSETPOINTf, 4929 temp_val); 4930 SOC_IF_ERROR_RETURN(WRITE_QSTRUCT_FAPFULLSETPOINTr(unit, idx, rval)); 4931 } 4932 4933 /* C255 QSTRUCT_FAPFULLRESETPOINT.FAPFULLRESETPOINT = C254 - 16*/ 4934 temp_val = temp_val -16; 4935 for (idx =0 ; idx < 1; idx++) { 4936 SOC_IF_ERROR_RETURN(READ_QSTRUCT_FAPFULLRESETPOINTr(unit, idx, &rval)); 4937 soc_reg_field_set(unit, QSTRUCT_FAPFULLRESETPOINTr, &rval, 4938 FAPFULLRESETPOINTf, 4939 temp_val ); 4940 SOC_IF_ERROR_RETURN(WRITE_QSTRUCT_FAPFULLRESETPOINTr(unit, idx, rval)); 4941 } 4942 4943 /* C256: QSTRUCT_FAPOTPCONFIG.MAXFULLSET = C253*/ 4944 temp_val = (((_soc_ml_mmu_params.mmu_egress_queue_entries * 1024 ) + (1024 *3))/4); 4945 for (idx =0 ; idx < 1; idx++) { 4946 SOC_IF_ERROR_RETURN(READ_QSTRUCT_FAPOTPCONFIGr(unit, idx, &rval)); 4947 soc_reg_field_set(unit, QSTRUCT_FAPOTPCONFIGr, &rval, MAXFULLSETf, 4948 temp_val); 4949 /* Its failing on Emulator */ 4950 /* SOC_IF_ERROR_RETURN(WRITE_QSTRUCT_FAPOTPCONFIGr(unit, idx, rval)); */ 4951 } 4952 4953 /* C261: THDO_MISCCONFIG.UCMC_SEPARATION = 0 */ 4954 SOC_IF_ERROR_RETURN(READ_THDO_MISCCONFIGr(unit, &rval)); 4955 soc_reg_field_set(unit, THDO_MISCCONFIGr, &rval, UCMC_SEPARATIONf, 0); 4956 SOC_IF_ERROR_RETURN(WRITE_THDO_MISCCONFIGr(unit, rval)); 4957 4958 /* C262: WRED_MISCCONFIG.UCMC_SEPARATION = 0 */ 4959 SOC_IF_ERROR_RETURN(READ_WRED_MISCCONFIGr(unit, &rval)); 4960 soc_reg_field_set(unit, WRED_MISCCONFIGr, &rval, UCMC_SEPARATIONf, 0); 4961 SOC_IF_ERROR_RETURN(WRITE_WRED_MISCCONFIGr(unit, rval)); 4962 4963 /* C266: COLOR_AWARE.ENABLE = 0 */ 4964 SOC_IF_ERROR_RETURN(READ_COLOR_AWAREr (unit, &rval)); 4965 soc_reg_field_set(unit, COLOR_AWAREr, &rval, ENABLEf, 0); 4966 SOC_IF_ERROR_RETURN(WRITE_COLOR_AWAREr (unit, rval)); 4967 4968 /* C268: GLOBAL_HDRM_LIMIT.GLOBAL_HDRM_LIMIT = =$C$110 */ 4969 SOC_IF_ERROR_RETURN(READ_GLOBAL_HDRM_LIMITr (unit, &rval)); 4970 soc_reg_field_set(unit, GLOBAL_HDRM_LIMITr, &rval, GLOBAL_HDRM_LIMITf, 4971 input_port_threshold->global_hdrm_cells_for_int_buff_ingress_pool); 4972 SOC_IF_ERROR_RETURN(WRITE_GLOBAL_HDRM_LIMITr (unit, rval)); 4973 4974 /* C269: BUFFER_CELL_LIMIT_SP.LIMIT = =$C$186 */ 4975 SOC_IF_ERROR_RETURN(READ_BUFFER_CELL_LIMIT_SPr (unit, service_pool, &rval)); 4976 soc_reg_field_set(unit, BUFFER_CELL_LIMIT_SPr, &rval, LIMITf, 4977 input_port_threshold->total_shared_ing_buff_pool); 4978 SOC_IF_ERROR_RETURN(WRITE_BUFFER_CELL_LIMIT_SPr (unit, service_pool, rval)); 4979 4980 /* C270: CELL_RESET_LIMIT_OFFSET_SP.OFFSET =CEILING(C82/4, 1)*C76 */ 4981 SOC_IF_ERROR_RETURN(READ_CELL_RESET_LIMIT_OFFSET_SPr (unit, 4982 service_pool, &rval)); 4983 temp_val = sal_ceil_func(general_info->total_num_of_ports_excl_lpbk_olp_cpu,4) * 4984 general_info->ether_mtu_cells_for_int_buff; 4985 soc_reg_field_set(unit, CELL_RESET_LIMIT_OFFSET_SPr, &rval, 4986 OFFSETf, temp_val); 4987 SOC_IF_ERROR_RETURN(WRITE_CELL_RESET_LIMIT_OFFSET_SPr (unit, 4988 service_pool, rval)); 4989 /* C280: THDIRQE_GLOBAL_HDRM_LIMIT.GLOBAL_HDRM_LIMIT = C113 */ 4990 SOC_IF_ERROR_RETURN(READ_THDIRQE_GLOBAL_HDRM_LIMITr (unit, &rval)); 4991 soc_reg_field_set(unit, THDIRQE_GLOBAL_HDRM_LIMITr, &rval, 4992 GLOBAL_HDRM_LIMITf, 4993 input_port_threshold->global_hdrm_cells_for_RE_WQEs); 4994 SOC_IF_ERROR_RETURN(WRITE_THDIRQE_GLOBAL_HDRM_LIMITr (unit, rval)); 4995 4996 /* C227: THDIRQE_BUFFER_CELL_LIMIT_SP.LIMIT =$C$189 */ 4997 SOC_IF_ERROR_RETURN(READ_THDIRQE_BUFFER_CELL_LIMIT_SPr ( 4998 unit, service_pool, &rval)); 4999 soc_reg_field_set(unit, THDIRQE_BUFFER_CELL_LIMIT_SPr, &rval, LIMITf, 5000 input_port_threshold->total_shared_RE_WQEs_buff); 5001 SOC_IF_ERROR_RETURN(WRITE_THDIRQE_BUFFER_CELL_LIMIT_SPr ( 5002 unit, service_pool, rval)); 5003 5004 /* C282: = THDIRQE_CELL_RESET_LIMIT_OFFSET_SP.OFFSET = =CEILING(C82/4, 1) */ 5005 SOC_IF_ERROR_RETURN(READ_THDIRQE_CELL_RESET_LIMIT_OFFSET_SPr( 5006 unit,service_pool,&rval)); 5007 soc_reg_field_set(unit, THDIRQE_CELL_RESET_LIMIT_OFFSET_SPr, &rval, 5008 OFFSETf, 5009 sal_ceil_func(general_info->total_num_of_ports_excl_lpbk_olp_cpu , 4)); 5010 SOC_IF_ERROR_RETURN(WRITE_THDIRQE_CELL_RESET_LIMIT_OFFSET_SPr( 5011 unit,service_pool,rval)); 5012 5013 /* C284: THDIQEN_GLOBAL_HDRM_LIMIT.GLOBAL_HDRM_LIMIT = C114 */ 5014 SOC_IF_ERROR_RETURN(READ_THDIQEN_GLOBAL_HDRM_LIMITr (unit, &rval)); 5015 soc_reg_field_set(unit, THDIQEN_GLOBAL_HDRM_LIMITr, &rval, 5016 GLOBAL_HDRM_LIMITf, 5017 input_port_threshold->global_hdrm_cells_for_EQEs); 5018 SOC_IF_ERROR_RETURN(WRITE_THDIQEN_GLOBAL_HDRM_LIMITr (unit, rval)); 5019 5020 /* C285: THDIQEN_BUFFER_CELL_LIMIT_SP.LIMIT =$C$190 */ 5021 SOC_IF_ERROR_RETURN(READ_THDIQEN_BUFFER_CELL_LIMIT_SPr ( 5022 unit, service_pool, &rval)); 5023 soc_reg_field_set(unit, THDIQEN_BUFFER_CELL_LIMIT_SPr, &rval, LIMITf, 5024 input_port_threshold->total_shared_EQEs_buff); 5025 SOC_IF_ERROR_RETURN(WRITE_THDIQEN_BUFFER_CELL_LIMIT_SPr ( 5026 unit, service_pool, rval)); 5027 5028 /* C286: THDIQEN_CELL_RESET_LIMIT_OFFSET_SP.OFFSET= 5029 =CEILING(C82/4, 1)*C51*/ 5030 SOC_IF_ERROR_RETURN(READ_THDIQEN_CELL_RESET_LIMIT_OFFSET_SPr( 5031 unit,service_pool,&rval)); 5032 temp_val = sal_ceil_func(general_info->total_num_of_ports_excl_lpbk_olp_cpu, 4) * 5033 _soc_ml_mmu_params.mmu_exp_num_of_repl_per_pkt; 5034 soc_reg_field_set(unit, THDIQEN_CELL_RESET_LIMIT_OFFSET_SPr, &rval, OFFSETf, 5035 temp_val); 5036 SOC_IF_ERROR_RETURN(WRITE_THDIQEN_CELL_RESET_LIMIT_OFFSET_SPr( 5037 unit,service_pool,rval)); 5038 5039 /* C289: OP_BUFFER_SHARED_LIMIT_CELLI.OP_BUFFER_SHARED_LIMIT_CELLI = C222 */ 5040 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_SHARED_LIMIT_CELLIr (unit, &rval)); 5041 soc_reg_field_set(unit, OP_BUFFER_SHARED_LIMIT_CELLIr, &rval, 5042 OP_BUFFER_SHARED_LIMIT_CELLIf, 5043 output_port_threshold->min_grntd_tot_shr_queue_cells_int_buff); 5044 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_SHARED_LIMIT_CELLIr (unit, rval)); 5045 5046 temp_val = output_port_threshold-> 5047 min_grntd_tot_shr_queue_cells_int_buff; 5048 5049 /* C290 OP_BUFFER_SHARED_LIMIT_RESUME_CELLI.OP_BUFFER_SHARED_LIMIT_RESUME_CELLI 5050 =C289-CEILING(C82/4, 1)*C76 */ 5051 5052 temp_val = temp_val - (sal_ceil_func(general_info->total_num_of_ports_excl_lpbk_olp_cpu,4) 5053 * general_info->ether_mtu_cells_for_int_buff); 5054 5055 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_SHARED_LIMIT_RESUME_CELLIr(unit, &rval)); 5056 soc_reg_field_set(unit, OP_BUFFER_SHARED_LIMIT_RESUME_CELLIr, &rval, 5057 OP_BUFFER_SHARED_LIMIT_RESUME_CELLIf, temp_val); 5058 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_SHARED_LIMIT_RESUME_CELLIr(unit, rval)); 5059 5060 /* C292 OP_BUFFER_LIMIT_RESUME_YELLOW_CELLI.OP_BUFFER_LIMIT_RESUME_YELLOW_CELLI = 5061 =CEILING(C290/8, 1) */ 5062 5063 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_LIMIT_RESUME_YELLOW_CELLIr ( 5064 unit, &rval)); 5065 soc_reg_field_set(unit, OP_BUFFER_LIMIT_RESUME_YELLOW_CELLIr, &rval, 5066 OP_BUFFER_LIMIT_RESUME_YELLOW_CELLIf, sal_ceil_func(temp_val,8)); 5067 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_RESUME_YELLOW_CELLIr ( 5068 unit, rval)); 5069 5070 /* C294 OP_BUFFER_LIMIT_RESUME_RED_CELLI.OP_BUFFER_LIMIT_RESUME_RED_CELLI 5071 =CEILING(C290/8, 1) */ 5072 5073 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_LIMIT_RESUME_RED_CELLIr (unit, &rval)); 5074 soc_reg_field_set(unit, OP_BUFFER_LIMIT_RESUME_RED_CELLIr, &rval, 5075 OP_BUFFER_LIMIT_RESUME_RED_CELLIf, sal_ceil_func(temp_val,8)); 5076 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_RESUME_RED_CELLIr (unit, rval)); 5077 5078 /* C291: OP_BUFFER_LIMIT_YELLOW_CELLI.OP_BUFFER_LIMIT_YELLOW_CELLI = 5079 =CEILING(C289/8, 1) */ 5080 temp_val = output_port_threshold-> 5081 min_grntd_tot_shr_queue_cells_int_buff; 5082 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_LIMIT_YELLOW_CELLIr (unit, &rval)); 5083 soc_reg_field_set(unit, OP_BUFFER_LIMIT_YELLOW_CELLIr, &rval, 5084 OP_BUFFER_LIMIT_YELLOW_CELLIf, sal_ceil_func(temp_val,8)); 5085 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_YELLOW_CELLIr (unit, rval)); 5086 5087 /* C293 OP_BUFFER_LIMIT_RED_CELLI.OP_BUFFER_LIMIT_RED_CELLI 5088 =CEILING(C289/8, 1) */ 5089 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_LIMIT_RED_CELLIr (unit, &rval)); 5090 soc_reg_field_set(unit, OP_BUFFER_LIMIT_RED_CELLIr, &rval, 5091 OP_BUFFER_LIMIT_RED_CELLIf, sal_ceil_func( temp_val,8)); 5092 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_RED_CELLIr (unit, rval)); 5093 5094 5095 /* C310: 5096 OP_BUFFER_SHARED_LIMIT_THDORQEQ.OP_BUFFER_SHARED_LIMIT_CELLE = C226 */ 5097 5098 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_SHARED_LIMIT_THDORQEQr (unit, &rval)); 5099 temp_val = output_port_threshold->min_grntd_tot_shr_RE_WQs_cells; 5100 soc_reg_field_set(unit, OP_BUFFER_SHARED_LIMIT_THDORQEQr, &rval, 5101 OP_BUFFER_SHARED_LIMITf, temp_val); 5102 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_SHARED_LIMIT_THDORQEQr (unit, rval)); 5103 5104 /* C312: OP_BUFFER_LIMIT_YELLOW_THDORQEQ.OP_BUFFER_LIMIT_YELLOW = 5105 =CEILING(C310/8, 1) */ 5106 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_LIMIT_YELLOW_THDORQEQr (unit, &rval)); 5107 soc_reg_field_set(unit, OP_BUFFER_LIMIT_YELLOW_THDORQEQr, &rval, 5108 OP_BUFFER_LIMIT_YELLOWf, sal_ceil_func(temp_val,8)); 5109 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_YELLOW_THDORQEQr (unit, rval)); 5110 5111 /* C314: OP_BUFFER_LIMIT_RED_THDORQEQ.OP_BUFFER_LIMIT_RED = 5112 =CEILING(C310/8, 1) */ 5113 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_LIMIT_RED_THDORQEQr (unit, &rval)); 5114 soc_reg_field_set(unit, OP_BUFFER_LIMIT_RED_THDORQEQr, &rval, 5115 OP_BUFFER_LIMIT_REDf, sal_ceil_func(temp_val,8)); 5116 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_RED_THDORQEQr (unit, rval)); 5117 5118 /* C311: OP_BUFFER_SHARED_LIMIT_RESUME_THDORQEQ. 5119 OP_BUFFER_SHARED_LIMIT_RESUME =C226-CEILING(C82/4, 1) */ 5120 temp_val -= sal_ceil_func(general_info->total_num_of_ports_excl_lpbk_olp_cpu,4); 5121 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_SHARED_LIMIT_RESUME_THDORQEQr( 5122 unit, &rval)); 5123 soc_reg_field_set(unit, OP_BUFFER_SHARED_LIMIT_RESUME_THDORQEQr, &rval, 5124 OP_BUFFER_SHARED_LIMIT_RESUMEf, temp_val); 5125 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_SHARED_LIMIT_RESUME_THDORQEQr( 5126 unit, rval)); 5127 5128 /* C313: OP_BUFFER_LIMIT_RESUME_YELLOW_THDORQEQ. 5129 OP_BUFFER_LIMIT_RESUME_YELLOW = C312-1 */ 5130 temp_val = sal_ceil_func(output_port_threshold->min_grntd_tot_shr_RE_WQs_cells , 8); 5131 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_LIMIT_RESUME_YELLOW_THDORQEQr ( 5132 unit, &rval)); 5133 soc_reg_field_set(unit, OP_BUFFER_LIMIT_RESUME_YELLOW_THDORQEQr, &rval, 5134 OP_BUFFER_LIMIT_RESUME_YELLOWf, temp_val-1); 5135 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_RESUME_YELLOW_THDORQEQr ( 5136 unit, rval)); 5137 5138 /* C315: OP_BUFFER_LIMIT_RESUME_RED_THDORQEQ. 5139 OP_BUFFER_LIMIT_RESUME_RED==C314 -1 */ 5140 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_LIMIT_RESUME_RED_THDORQEQr ( 5141 unit, &rval)); 5142 soc_reg_field_set(unit, OP_BUFFER_LIMIT_RESUME_RED_THDORQEQr, &rval, 5143 OP_BUFFER_LIMIT_RESUME_REDf, temp_val-1); 5144 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_RESUME_RED_THDORQEQr ( 5145 unit, rval)); 5146 5147 /* C317: OP_BUFFER_SHARED_LIMIT_QENTRY.OP_BUFFER_SHARED_LIMIT_QENTRY =C221*/ 5148 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_SHARED_LIMIT_QENTRYr (unit, &rval)); 5149 soc_reg_field_set(unit, OP_BUFFER_SHARED_LIMIT_QENTRYr, &rval, 5150 OP_BUFFER_SHARED_LIMIT_QENTRYf, 5151 output_port_threshold->min_grntd_tot_shr_queue_cells_EQEs); 5152 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_SHARED_LIMIT_QENTRYr (unit, rval)); 5153 5154 temp_val = output_port_threshold->min_grntd_tot_shr_queue_cells_EQEs; 5155 5156 /* C319: OP_BUFFER_LIMIT_YELLOW_QENTRY.OP_BUFFER_LIMIT_YELLOW_QENTRY 5157 = CEILING(C317/8, 1) */ 5158 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_LIMIT_YELLOW_QENTRYr(unit, &rval)); 5159 soc_reg_field_set(unit, OP_BUFFER_LIMIT_YELLOW_QENTRYr, &rval, 5160 OP_BUFFER_LIMIT_YELLOW_QENTRYf, sal_ceil_func(temp_val,8)); 5161 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_YELLOW_QENTRYr(unit, rval)); 5162 5163 /* C321: OP_BUFFER_LIMIT_RED_QENTRY.OP_BUFFER_LIMIT_RED_QENTRY 5164 = CEILING(C317/8, 1) */ 5165 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_LIMIT_RED_QENTRYr(unit, &rval)); 5166 soc_reg_field_set(unit, OP_BUFFER_LIMIT_RED_QENTRYr, &rval, 5167 OP_BUFFER_LIMIT_RED_QENTRYf, sal_ceil_func(temp_val,8)); 5168 5169 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_RED_QENTRYr(unit, rval)); 5170 5171 /* C318: OP_BUFFER_SHARED_LIMIT_RESUME_QENTRY.OP_BUFFER_SHARED_LIMIT_RESUME_QENTRY 5172 =C224-CEILING(C82/4, 1)*C51 */ 5173 temp_val -= (sal_ceil_func(general_info->total_num_of_ports_excl_lpbk_olp_cpu,4) * 5174 _soc_ml_mmu_params.mmu_exp_num_of_repl_per_pkt); 5175 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_SHARED_LIMIT_RESUME_QENTRYr( 5176 unit, &rval)); 5177 soc_reg_field_set(unit, OP_BUFFER_SHARED_LIMIT_RESUME_QENTRYr, 5178 &rval, 5179 OP_BUFFER_SHARED_LIMIT_RESUME_QENTRYf, temp_val); 5180 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_SHARED_LIMIT_RESUME_QENTRYr( 5181 unit, rval)); 5182 5183 /* C320 OP_BUFFER_LIMIT_RESUME_YELLOW_QENTRY.OP_BUFFER_LIMIT_RESUME_YELLOW_QENTRY 5184 =CEILING(C318/8, 1) */ 5185 SOC_IF_ERROR_RETURN( 5186 READ_OP_BUFFER_LIMIT_RESUME_YELLOW_QENTRYr(unit, &rval)); 5187 soc_reg_field_set(unit, OP_BUFFER_LIMIT_RESUME_YELLOW_QENTRYr, &rval, 5188 OP_BUFFER_LIMIT_RESUME_YELLOW_QENTRYf, 5189 sal_ceil_func(temp_val,8)); 5190 SOC_IF_ERROR_RETURN( 5191 WRITE_OP_BUFFER_LIMIT_RESUME_YELLOW_QENTRYr(unit, rval)); 5192 5193 /* C322 OP_BUFFER_LIMIT_RESUME_RED_QENTRY.OP_BUFFER_LIMIT_RESUME_RED_QENTRY 5194 =CEILING(C318/8, 1) */ 5195 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_LIMIT_RESUME_RED_QENTRYr(unit, &rval)); 5196 soc_reg_field_set(unit, OP_BUFFER_LIMIT_RESUME_RED_QENTRYr, &rval, 5197 OP_BUFFER_LIMIT_RESUME_RED_QENTRYf, 5198 sal_ceil_func(temp_val,8)); 5199 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_RESUME_RED_QENTRYr(unit, rval)); 5200 5201 /* C324 : OP_BUFFER_SHARED_LIMIT_THDORDEQ.OP_BUFFER_SHARED_LIMIT = C229 */ 5202 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_SHARED_LIMIT_THDORDEQr(unit, &rval)); 5203 soc_reg_field_set(unit,OP_BUFFER_SHARED_LIMIT_THDORDEQr,&rval, 5204 OP_BUFFER_SHARED_LIMITf, 5205 output_port_threshold->min_grntd_tot_shr_EP_redirect_queue_entry_cells); 5206 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_SHARED_LIMIT_THDORDEQr(unit, rval)); 5207 temp_val= output_port_threshold-> 5208 min_grntd_tot_shr_EP_redirect_queue_entry_cells; 5209 5210 /*C325: OP_BUFFER_SHARED_LIMIT_TRESUME_THDORDEQr. 5211 OP_BUFFER_SHARED_LIMIT_RESUMEf = =C229-4 */ 5212 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_SHARED_LIMIT_RESUME_THDORDEQr( 5213 unit, &rval)); 5214 soc_reg_field_set(unit,OP_BUFFER_SHARED_LIMIT_RESUME_THDORDEQr,&rval, 5215 OP_BUFFER_SHARED_LIMIT_RESUMEf, 5216 temp_val - 4); 5217 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_SHARED_LIMIT_RESUME_THDORDEQr( 5218 unit, rval)); 5219 5220 /* C326: OP_BUFFER_LIMIT_YELLOW_THDORDEQ.OP_BUFFER_LIMIT_YELLOW 5221 = CEILING(C324/8, 1) */ 5222 temp_val = sal_ceil_func(temp_val , 8); 5223 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_LIMIT_YELLOW_THDORDEQr(unit, &rval)); 5224 soc_reg_field_set(unit,OP_BUFFER_LIMIT_YELLOW_THDORDEQr,&rval, 5225 OP_BUFFER_LIMIT_YELLOWf, temp_val); 5226 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_YELLOW_THDORDEQr(unit, rval)); 5227 5228 /* C328: OP_BUFFER_LIMIT_RED_THDORDEQ.OP_BUFFER_LIMIT_RED 5229 = CEILING(C324/8, 1) */ 5230 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_LIMIT_RED_THDORDEQr(unit, &rval)); 5231 soc_reg_field_set(unit,OP_BUFFER_LIMIT_RED_THDORDEQr,&rval, 5232 OP_BUFFER_LIMIT_REDf, temp_val); 5233 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_RED_THDORDEQr(unit, rval)); 5234 5235 /* C327: OP_BUFFER_LIMIT_RESUME_YELLOW_THDORDEQ. 5236 OP_BUFFER_LIMIT_RESUME_YELLOW = =C326-1 */ 5237 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_LIMIT_RESUME_YELLOW_THDORDEQr( 5238 unit, &rval)); 5239 soc_reg_field_set(unit,OP_BUFFER_LIMIT_RESUME_YELLOW_THDORDEQr,&rval, 5240 OP_BUFFER_LIMIT_RESUME_YELLOWf, temp_val-1); 5241 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_RESUME_YELLOW_THDORDEQr( 5242 unit, rval)); 5243 5244 /* C329: OP_BUFFER_LIMIT_RESUME_RED_THDORDEQ. 5245 OP_BUFFER_LIMIT_RESUME_RED = =C328-1 */ 5246 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_LIMIT_RESUME_RED_THDORDEQr(unit, &rval)); 5247 soc_reg_field_set(unit,OP_BUFFER_LIMIT_RESUME_RED_THDORDEQr,&rval, 5248 OP_BUFFER_LIMIT_RESUME_REDf, temp_val-1); 5249 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_RESUME_RED_THDORDEQr(unit, rval)); 5250 } 5251 5252 SOC_PBMP_ITER (valid_port_cpu_pbmp, port) { 5253 if (port >= ML_MAX_LOGICAL_PORTS) { 5254 continue; 5255 } 5256 if ((flex_port != -1) && (flex_port != port)) { 5257 continue; 5258 } 5259 5260 sal_memset(&thdi_port_sp_config,0,sizeof(thdi_port_sp_config)); 5261 mem_idx= ML_GET_THDI_PORT(port) * ML_MAX_SERVICE_POOLS; 5262 /* C335 : THDI_PORT_SP_CONFIG.PORT_SP_MIN_LIMIT = =$C$168 */ 5263 soc_mem_field32_set(unit, THDI_PORT_SP_CONFIGm, 5264 &thdi_port_sp_config, PORT_SP_MIN_LIMITf, 5265 input_port_threshold->min_int_buff_cells_for_a_port); 5266 5267 /* C336 : THDI_PORT_SP_CONFIG.PORT_SP_MAX_LIMIT = =$C$269 i.e. =$C$186 */ 5268 soc_mem_field32_set(unit, THDI_PORT_SP_CONFIGm, 5269 &thdi_port_sp_config, PORT_SP_MAX_LIMITf, 5270 input_port_threshold->total_shared_ing_buff_pool); 5271 5272 /* C337 : PORT_MAX_PKT_SIZE.PORT_MAX_PKT_SIZE = =$C$72 */ 5273 SOC_IF_ERROR_RETURN(READ_PORT_MAX_PKT_SIZEr (unit, port, &rval)); 5274 soc_reg_field_set(unit, PORT_MAX_PKT_SIZEr, &rval, 5275 PORT_MAX_PKT_SIZEf, 5276 general_info->max_packet_size_in_cells); 5277 SOC_IF_ERROR_RETURN(WRITE_PORT_MAX_PKT_SIZEr (unit, port, rval)); 5278 5279 /* C338: THDI_PORT_SP_CONFIG.PORT_SP_RESUME_LIMIT = =C336-2*$C$76 */ 5280 soc_mem_field32_set(unit, THDI_PORT_SP_CONFIGm, 5281 &thdi_port_sp_config, PORT_SP_RESUME_LIMITf, 5282 input_port_threshold->total_shared_ing_buff_pool - 5283 (2 * general_info->ether_mtu_cells_for_int_buff)); 5284 5285 SOC_IF_ERROR_RETURN (soc_mem_write( 5286 unit, THDI_PORT_SP_CONFIGm, MEM_BLOCK_ALL, 5287 mem_idx, &thdi_port_sp_config)); 5288 sal_memset(&thdi_port_pg_config,0,sizeof(thdi_port_pg_config)); 5289 mem_idx= ML_GET_THDI_PORT_PG(port); 5290 5291 /* C339: THDI_PORT_PG_CONFIG.PG_MIN_LIMIT (PG0) = =$C$156 */ 5292 soc_mem_field32_set(unit, THDI_PORT_PG_CONFIGm, 5293 &thdi_port_pg_config, PG_MIN_LIMITf, 5294 input_port_threshold->min_int_buff_cells_per_PG); 5295 5296 /* C340: THDI_PORT_PG_CONFIG.PG_SHARED_LIMIT 5297 =IF($C$14, $C$61, $C$269)*/ 5298 if (_soc_ml_mmu_params.lossless_mode_d_c) { 5299 temp_val = _soc_ml_mmu_params.mmu_ing_pg_dyn_thd_param; 5300 } else { 5301 temp_val = input_port_threshold->total_shared_ing_buff_pool; 5302 } 5303 soc_mem_field32_set(unit, THDI_PORT_PG_CONFIGm, 5304 &thdi_port_pg_config, PG_SHARED_LIMITf, temp_val); 5305 5306 /* C341: THDI_PORT_PG_CONFIG.PG_RESET_OFFSET = 2*$C$76 */ 5307 soc_mem_field32_set(unit, THDI_PORT_PG_CONFIGm, 5308 &thdi_port_pg_config, PG_RESET_OFFSETf, 5309 (2 * general_info->ether_mtu_cells_for_int_buff)); 5310 5311 /* C342: THDI_PORT_PG_CONFIG.PG_RESET_FLOOR = 0 */ 5312 soc_mem_field32_set(unit, THDI_PORT_PG_CONFIGm, 5313 &thdi_port_pg_config, PG_RESET_FLOORf, 0); 5314 5315 /* C343: THDI_PORT_PG_CONFIG.PG_SHARED_DYNAMIC= =IF($C$14, 1, 0) */ 5316 if (_soc_ml_mmu_params.lossless_mode_d_c) { 5317 temp_val = 1; 5318 } else { 5319 temp_val = 0; 5320 } 5321 soc_mem_field32_set(unit, THDI_PORT_PG_CONFIGm, 5322 &thdi_port_pg_config, PG_SHARED_DYNAMICf,temp_val); 5323 5324 /* C344: THDI_PORT_PG_CONFIG.PG_HDRM_LIMIT= 5325 For Ge:$C125 For Hg:$C115 For Cpu:$C145 */ 5326 if (IS_CPU_PORT(unit, port)) { 5327 temp_val = input_port_threshold->hdrm_int_buff_cells_for_cpu_port; 5328 } else if (IS_GE_PORT(unit, port) || IS_LB_PORT(unit,port)) { 5329 temp_val = input_port_threshold->hdrm_int_buff_cells_for_1G_PG; 5330 } else if (IS_HG_PORT(unit, port) || IS_XE_PORT(unit,port) ) { 5331 temp_val = input_port_threshold->hdrm_int_buff_cells_for_10G_PG; 5332 } 5333 soc_mem_field32_set(unit, THDI_PORT_PG_CONFIGm, 5334 &thdi_port_pg_config, PG_HDRM_LIMITf,temp_val); 5335 5336 /* C345 : THDI_PORT_PG_CONFIG.PG_GBL_HDRM_EN = for lossy=1 else 0 */ 5337 soc_mem_field32_set(unit, THDI_PORT_PG_CONFIGm, 5338 &thdi_port_pg_config, PG_GBL_HDRM_ENf ,1); 5339 5340 /* C346: THDI_PORT_PG_CONFIG.SP_SHARED_MAX_ENABLE = 5341 For Ge:1 For Hg,Cpu: Ge Value only!!! */ 5342 5343 soc_mem_field32_set(unit, THDI_PORT_PG_CONFIGm, 5344 &thdi_port_pg_config, SP_SHARED_MAX_ENABLEf ,1); 5345 5346 /* C347: THDI_PORT_PG_CONFIG.SP_MIN_PG_ENABLE = 5347 For Ge:1 For Hg,Cpu: Ge Value only!!! */ 5348 soc_mem_field32_set(unit, THDI_PORT_PG_CONFIGm, 5349 &thdi_port_pg_config, SP_MIN_PG_ENABLEf ,1); 5350 5351 SOC_IF_ERROR_RETURN (soc_mem_write( 5352 unit, THDI_PORT_PG_CONFIGm, MEM_BLOCK_ALL, 5353 mem_idx, &thdi_port_pg_config)); 5354 5355 sal_memset(&thdirqe_thdi_port_sp_config , 0, 5356 sizeof(thdirqe_thdi_port_sp_config)); 5357 5358 mem_idx= ML_GET_THDI_PORT(port) * ML_MAX_SERVICE_POOLS; 5359 /* C380: THDIRQE_THDI_PORT_SP_CONFIG.PORT_SP_MIN_LIMIT = $C$171 */ 5360 soc_mem_field32_set(unit, THDIRQE_THDI_PORT_SP_CONFIGm, 5361 &thdirqe_thdi_port_sp_config, PORT_SP_MIN_LIMITf, 5362 input_port_threshold->min_RE_WQEs_pkts_for_a_port); 5363 5364 /* C381: THDIRQE_THDI_PORT_SP_CONFIG.PORT_SP_MAX_LIMIT = $C$189 */ 5365 soc_mem_field32_set(unit, THDIRQE_THDI_PORT_SP_CONFIGm, 5366 &thdirqe_thdi_port_sp_config, PORT_SP_MAX_LIMITf, 5367 input_port_threshold->total_shared_RE_WQEs_buff); 5368 5369 /* C382: THDIRQE_THDI_PORT_SP_CONFIG.PORT_SP_RESUME_LIMIT = 5370 =C381-2 */ 5371 soc_mem_field32_set(unit, THDIRQE_THDI_PORT_SP_CONFIGm, 5372 &thdirqe_thdi_port_sp_config, PORT_SP_RESUME_LIMITf, 5373 input_port_threshold->total_shared_RE_WQEs_buff - 2); 5374 SOC_IF_ERROR_RETURN(soc_mem_write( 5375 unit, THDIRQE_THDI_PORT_SP_CONFIGm, MEM_BLOCK_ALL, 5376 mem_idx, &thdirqe_thdi_port_sp_config)); 5377 5378 sal_memset(&thdirqe_thdi_port_pg_config , 0, 5379 sizeof(thdirqe_thdi_port_pg_config)); 5380 mem_idx= ML_GET_THDI_PORT_PG(port); 5381 /* C383: THDIRQE_THDI_PORT_PG_CONFIG.PG_MIN_LIMIT(PG0) = =$C$159 */ 5382 temp_val = input_port_threshold->min_RE_WQEs_pkt_per_PG; 5383 soc_mem_field32_set(unit, THDIRQE_THDI_PORT_PG_CONFIGm, 5384 &thdirqe_thdi_port_pg_config, PG_MIN_LIMITf,temp_val); 5385 5386 /* C384: THDIRQE_THDI_PORT_PG_CONFIG.PG_SHARED_LIMIT = 5387 =IF($C$14, $C$61, $C$189) */ 5388 if (_soc_ml_mmu_params.lossless_mode_d_c) { 5389 temp_val = _soc_ml_mmu_params.mmu_ing_pg_dyn_thd_param; 5390 } else { 5391 temp_val = input_port_threshold->total_shared_RE_WQEs_buff; 5392 } 5393 soc_mem_field32_set(unit, THDIRQE_THDI_PORT_PG_CONFIGm, 5394 &thdirqe_thdi_port_pg_config, 5395 PG_SHARED_LIMITf, temp_val); 5396 5397 /* C385: THDIRQE_THDI_PORT_PG_CONFIG.PG_RESET_OFFSET = 2 */ 5398 soc_mem_field32_set(unit, THDIRQE_THDI_PORT_PG_CONFIGm, 5399 &thdirqe_thdi_port_pg_config, PG_RESET_OFFSETf,2); 5400 5401 /* C386: THDIRQE_THDI_PORT_PG_CONFIG.PG_RESET_FLOOR = 0 */ 5402 soc_mem_field32_set(unit, THDIRQE_THDI_PORT_PG_CONFIGm, 5403 &thdirqe_thdi_port_pg_config, PG_RESET_FLOORf, 0); 5404 5405 /* C387: THDIRQE_THDI_PORT_PG_CONFIG.PG_SHARED_DYNAMIC= 5406 =IF($C$14, 1, 0) */ 5407 if (_soc_ml_mmu_params.lossless_mode_d_c) { 5408 temp_val = 1; 5409 } else { 5410 temp_val = 0; 5411 } 5412 soc_mem_field32_set(unit, THDIRQE_THDI_PORT_PG_CONFIGm, 5413 &thdirqe_thdi_port_pg_config, PG_SHARED_DYNAMICf, 5414 temp_val); 5415 5416 /* C388: THDIRQE_THDI_PORT_PG_CONFIG.PG_HDRM_LIMIT 5417 For Ge:$C128 For Hg:$C118 For Cpu:$C148 */ 5418 if (IS_CPU_PORT(unit, port)) { 5419 temp_val = input_port_threshold->hdrm_RE_WQEs_pkts_for_cpu_port; 5420 } else if (IS_GE_PORT(unit, port) || IS_LB_PORT(unit,port)) { 5421 temp_val = input_port_threshold->hdrm_RE_WQEs_pkts_for_1G_PG; 5422 } else if (IS_HG_PORT(unit, port) || IS_XE_PORT(unit, port)) { 5423 temp_val= input_port_threshold->hdrm_RE_WQEs_pkts_for_10G_PG; 5424 } 5425 soc_mem_field32_set(unit, THDIRQE_THDI_PORT_PG_CONFIGm, 5426 &thdirqe_thdi_port_pg_config, PG_HDRM_LIMITf,temp_val); 5427 5428 /* C389: THDIRQE_THDI_PORT_PG_CONFIG.PG_GBL_HDRM_EN = 0 */ 5429 temp_val = 0; 5430 soc_mem_field32_set(unit, THDIRQE_THDI_PORT_PG_CONFIGm, 5431 &thdirqe_thdi_port_pg_config, PG_GBL_HDRM_ENf , 5432 temp_val); 5433 5434 /* C390: THDIRQE_THDI_PORT_PG_CONFIG.SP_SHARED_MAX_ENABLE = 5435 For Ge:1 For Hg,Cpu: Ge Value only!!! */ 5436 soc_mem_field32_set(unit, THDIRQE_THDI_PORT_PG_CONFIGm, 5437 &thdirqe_thdi_port_pg_config, SP_SHARED_MAX_ENABLEf ,1); 5438 5439 /* C391: THDIRQE_THDI_PORT_PG_CONFIG.SP_MIN_PG_ENABLE = 5440 For Ge:1 For Hg,Cpu: Ge Value only!!! */ 5441 soc_mem_field32_set(unit, THDIRQE_THDI_PORT_PG_CONFIGm, 5442 &thdirqe_thdi_port_pg_config, SP_MIN_PG_ENABLEf ,1); 5443 5444 SOC_IF_ERROR_RETURN(soc_mem_write(unit, THDIRQE_THDI_PORT_PG_CONFIGm, 5445 MEM_BLOCK_ALL, mem_idx, &thdirqe_thdi_port_pg_config)); 5446 5447 sal_memset(&thdiqen_thdi_port_sp_config,0, 5448 sizeof(thdiqen_thdi_port_sp_config)); 5449 mem_idx= ML_GET_THDI_PORT(port) * ML_MAX_SERVICE_POOLS; 5450 5451 /* C394: THDIQEN_THDI_PORT_SP_CONFIG.PORT_SP_MIN_LIMIT = $C$172 */ 5452 soc_mem_field32_set(unit, THDIQEN_THDI_PORT_SP_CONFIGm, 5453 &thdiqen_thdi_port_sp_config, PORT_SP_MIN_LIMITf, 5454 input_port_threshold->min_EQEs_pkts_for_a_port); 5455 5456 /* C395: THDIQEN_THDI_PORT_SP_CONFIG.PORT_SP_MAX_LIMIT = $C$190 */ 5457 soc_mem_field32_set(unit, THDIQEN_THDI_PORT_SP_CONFIGm, 5458 &thdiqen_thdi_port_sp_config, PORT_SP_MAX_LIMITf, 5459 input_port_threshold->total_shared_EQEs_buff); 5460 5461 /* C396: THDIQEN_THDI_PORT_SP_CONFIG.PORT_SP_RESUME_LIMIT = 5462 ==C395-2*C51 */ 5463 soc_mem_field32_set(unit, THDIQEN_THDI_PORT_SP_CONFIGm, 5464 &thdiqen_thdi_port_sp_config, PORT_SP_RESUME_LIMITf, 5465 input_port_threshold->total_shared_EQEs_buff - 5466 (2 * _soc_ml_mmu_params.mmu_exp_num_of_repl_per_pkt)); 5467 SOC_IF_ERROR_RETURN(soc_mem_write(unit, 5468 THDIQEN_THDI_PORT_SP_CONFIGm, MEM_BLOCK_ALL, 5469 mem_idx, &thdiqen_thdi_port_sp_config)); 5470 5471 sal_memset(&thdiqen_thdi_port_pg_config,0, 5472 sizeof(thdiqen_thdi_port_pg_config)); 5473 mem_idx= ML_GET_THDI_PORT_PG(port); 5474 /* C397: THDIQEN_THDI_PORT_PG_CONFIG.PG_MIN_LIMIT(PG0) = 5475 =$C$160 */ 5476 soc_mem_field32_set(unit, THDIQEN_THDI_PORT_PG_CONFIGm, 5477 &thdiqen_thdi_port_pg_config, PG_MIN_LIMITf, 5478 input_port_threshold->min_EQEs_pkt_per_PG); 5479 5480 5481 /* C398: THDIQEN_THDI_PORT_PG_CONFIG.PG_SHARED_LIMIT = 5482 =IF($C$14, $C$61, $C$190) */ 5483 if (_soc_ml_mmu_params.lossless_mode_d_c) { 5484 temp_val = _soc_ml_mmu_params.mmu_ing_pg_dyn_thd_param; 5485 } else { 5486 temp_val = input_port_threshold->total_shared_EQEs_buff; 5487 } 5488 soc_mem_field32_set(unit, THDIQEN_THDI_PORT_PG_CONFIGm, 5489 &thdiqen_thdi_port_pg_config, 5490 PG_SHARED_LIMITf, temp_val); 5491 5492 /* C399: THDIQEN_THDI_PORT_PG_CONFIG.PG_RESET_OFFSET = =2*C51 */ 5493 soc_mem_field32_set(unit, THDIQEN_THDI_PORT_PG_CONFIGm, 5494 &thdiqen_thdi_port_pg_config, PG_RESET_OFFSETf, 5495 2 * _soc_ml_mmu_params.mmu_exp_num_of_repl_per_pkt); 5496 5497 /* C400: THDIQEN_THDI_PORT_PG_CONFIG.PG_RESET_FLOOR = 0 */ 5498 soc_mem_field32_set(unit, THDIQEN_THDI_PORT_PG_CONFIGm, 5499 &thdiqen_thdi_port_pg_config, PG_RESET_FLOORf, 0); 5500 5501 /* C401: THDIQEN_THDI_PORT_PG_CONFIG.PG_SHARED_DYNAMIC= 0 */ 5502 if (_soc_ml_mmu_params.lossless_mode_d_c) { 5503 temp_val = 1; 5504 } else { 5505 temp_val = 0; 5506 } 5507 soc_mem_field32_set(unit, THDIQEN_THDI_PORT_PG_CONFIGm, 5508 &thdiqen_thdi_port_pg_config, PG_SHARED_DYNAMICf, 5509 temp_val); 5510 5511 /* C402: THDIQEN_THDI_PORT_PG_CONFIG.PG_HDRM_LIMIT 5512 For Ge:$C129 For Hg:$C119 For Cpu:$C149 */ 5513 if (IS_CPU_PORT(unit, port)) { 5514 temp_val = input_port_threshold->hdrm_EQEs_pkts_for_cpu_port; 5515 } else if (IS_GE_PORT(unit, port) || IS_LB_PORT(unit,port)) { 5516 temp_val = input_port_threshold->hdrm_EQEs_pkts_for_1G_PG; 5517 } else if (IS_HG_PORT(unit, port) || IS_XE_PORT(unit, port)) { 5518 temp_val= input_port_threshold->hdrm_EQEs_pkts_for_10G_PG; 5519 } 5520 soc_mem_field32_set(unit, THDIQEN_THDI_PORT_PG_CONFIGm, 5521 &thdiqen_thdi_port_pg_config, PG_HDRM_LIMITf,temp_val); 5522 5523 /* C403: THDIQEN_THDI_PORT_PG_CONFIG.PG_GBL_HDRM_EN =0 */ 5524 temp_val = 0; 5525 soc_mem_field32_set(unit, THDIQEN_THDI_PORT_PG_CONFIGm, 5526 &thdiqen_thdi_port_pg_config, PG_GBL_HDRM_ENf , 5527 temp_val); 5528 5529 /* C404: THDIQEN_THDI_PORT_PG_CONFIG.SP_SHARED_MAX_ENABLE = 5530 For Ge:1 For Hg,Cpu: Ge Value only!!! */ 5531 soc_mem_field32_set(unit, THDIQEN_THDI_PORT_PG_CONFIGm, 5532 &thdiqen_thdi_port_pg_config, SP_SHARED_MAX_ENABLEf ,1); 5533 5534 /* C405: THDIQEN_THDI_PORT_PG_CONFIG.SP_MIN_PG_ENABLE = 5535 For Ge:1 For Hg,Cpu: Ge Value only!!! */ 5536 soc_mem_field32_set(unit, THDIQEN_THDI_PORT_PG_CONFIGm, 5537 &thdiqen_thdi_port_pg_config, SP_MIN_PG_ENABLEf ,1); 5538 SOC_IF_ERROR_RETURN(soc_mem_write( unit, THDIQEN_THDI_PORT_PG_CONFIGm, 5539 MEM_BLOCK_ALL, mem_idx, &thdiqen_thdi_port_pg_config)); 5540 5541 if (!SOC_PBMP_MEMBER(PBMP_EXT_MEM (unit), port) && 5542 (port >= si->cmic_port) && (port <= si->lb_port)) { 5543 op_node = ( si->port_cosq_base[port] / 8); 5544 for (op_node_offset = 0; 5545 op_node_offset < sal_ceil_func(si->port_num_uc_cosq[port],8); 5546 op_node_offset++) { 5547 /* C409:THDO_OPNCONFIG_CELL.OPN_SHARED_LIMIT_CELL = =$C$222 */ 5548 soc_mem_field32_set(unit, MMU_THDO_OPNCONFIG_CELLm, 5549 &mmu_thdo_opnconfig_cell_entry, 5550 OPN_SHARED_LIMIT_CELLf, 5551 output_port_threshold-> 5552 min_grntd_tot_shr_queue_cells_int_buff); 5553 5554 /* C410:THDO_OPNCONFIG_CELL.OP_SHARED_RESET_VALUE_CELL 5555 = =C409-2*$C$76 */ 5556 temp_val = output_port_threshold-> 5557 min_grntd_tot_shr_queue_cells_int_buff - 5558 (2 * general_info->ether_mtu_cells_for_int_buff); 5559 soc_mem_field32_set(unit, MMU_THDO_OPNCONFIG_CELLm, 5560 &mmu_thdo_opnconfig_cell_entry, 5561 OPN_SHARED_RESET_VALUE_CELLf, temp_val); 5562 5563 /* C411:THDO_OPNCONFIG_CELL.PORT_LIMIT_ENABLE_CELL 5564 = 0 */ 5565 soc_mem_field32_set(unit, MMU_THDO_OPNCONFIG_CELLm, 5566 &mmu_thdo_opnconfig_cell_entry, 5567 PORT_LIMIT_ENABLE_CELLf, 0); 5568 soc_mem_field32_set(unit, MMU_THDO_OPNCONFIG_CELLm, 5569 &mmu_thdo_opnconfig_cell_entry, 5570 PIDf, port); 5571 SOC_IF_ERROR_RETURN(WRITE_MMU_THDO_OPNCONFIG_CELLm(unit, 5572 MEM_BLOCK_ANY,op_node + op_node_offset, 5573 &mmu_thdo_opnconfig_cell_entry)); 5574 } 5575 5576 for (queue = si->port_uc_cosq_base[port]; 5577 queue < si->port_uc_cosq_base[port] + 5578 si->port_num_uc_cosq[port]; 5579 queue++) { 5580 SOC_IF_ERROR_RETURN(READ_MMU_THDO_QCONFIG_CELLm(unit, 5581 MEM_BLOCK_ANY,queue, 5582 &mmu_thdo_qconfig_cell_entry)); 5583 /* C412:THDO_QCONFIG_CELL.Q_MIN_CELL 5584 IF(C11=0, C38, 0) for base queue*/ 5585 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, 5586 &mmu_thdo_qconfig_cell_entry, Q_MIN_CELLf, 5587 queue < general_info->total_egr_base_queues_in_device ? 5588 output_port_threshold->min_grntd_res_queue_cells_int_buff: 0); 5589 5590 /* C414:THDO_QCONFIG_CELL.Q_SHARED_LIMIT_CELL 5591 =IF($C$14,$C$222,$C$63) */ 5592 if (_soc_ml_mmu_params.lossless_mode_d_c) { 5593 temp_val = output_port_threshold-> 5594 min_grntd_tot_shr_queue_cells_int_buff; 5595 } else { 5596 temp_val = _soc_ml_mmu_params. 5597 mmu_egr_queue_dyn_thd_param_baf_profile_lossy; 5598 } 5599 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, 5600 &mmu_thdo_qconfig_cell_entry, Q_SHARED_LIMIT_CELLf, 5601 temp_val); 5602 5603 /* C416:THDO_QCONFIG_CELL.Q_LIMIT_DYNAMIC_CELL 5604 =IF($C$14, 0, 1) */ 5605 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, 5606 &mmu_thdo_qconfig_cell_entry, Q_LIMIT_DYNAMIC_CELLf, 5607 _soc_ml_mmu_params.lossless_mode_d_c ? 0 : 1); 5608 5609 /* C417:THDO_QCONFIG_CELL.Q_LIMIT_ENABLE_CELL 5610 =IF($C$14, 0, 1) */ 5611 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, 5612 &mmu_thdo_qconfig_cell_entry, Q_LIMIT_ENABLE_CELLf, 5613 _soc_ml_mmu_params.lossless_mode_d_c ? 0 : 1); 5614 5615 /* C418:THDO_QCONFIG_CELL.Q_COLOR_ENABLE_CELL = 0 */ 5616 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, 5617 &mmu_thdo_qconfig_cell_entry, Q_COLOR_ENABLE_CELLf,0); 5618 5619 /* C419: THDO_QCONFIG_CELL.Q_COLOR_LIMIT_DYNAMIC_CELL 5620 =IF($C$14, 0, 1) */ 5621 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, 5622 &mmu_thdo_qconfig_cell_entry, Q_COLOR_LIMIT_DYNAMIC_CELLf, 5623 _soc_ml_mmu_params.lossless_mode_d_c ? 0 : 1); 5624 5625 /* C420: THDO_QCONFIG_CELL.LIMIT_YELLOW_CELL= 0 */ 5626 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, 5627 &mmu_thdo_qconfig_cell_entry, LIMIT_YELLOW_CELLf, 0); 5628 5629 SOC_IF_ERROR_RETURN(WRITE_MMU_THDO_QCONFIG_CELLm(unit, 5630 MEM_BLOCK_ANY,queue, 5631 &mmu_thdo_qconfig_cell_entry)); 5632 5633 SOC_IF_ERROR_RETURN(READ_MMU_THDO_QOFFSET_CELLm(unit, 5634 MEM_BLOCK_ANY,queue, 5635 &mmu_thdo_qoffset_cell_entry)); 5636 /* C415:THDO_QOFFSET_CELL.RESET_OFFSET_CELL =2 */ 5637 soc_mem_field32_set(unit, MMU_THDO_QOFFSET_CELLm, 5638 &mmu_thdo_qoffset_cell_entry, RESET_OFFSET_CELLf, 2); 5639 5640 /* C421: THDO_QOFFSET_CELL.LIMIT_RED_CELL = */ 5641 soc_mem_field32_set(unit, MMU_THDO_QOFFSET_CELLm, 5642 &mmu_thdo_qoffset_cell_entry, LIMIT_RED_CELLf, 0); 5643 5644 /* C422: THDO_QOFFSET_CELL.RESET_OFFSET_YELLOW_CELL =2 */ 5645 soc_mem_field32_set(unit, MMU_THDO_QOFFSET_CELLm, 5646 &mmu_thdo_qoffset_cell_entry, RESET_OFFSET_YELLOW_CELLf,2); 5647 5648 /* C423: THDO_QOFFSET_CELL.RESET_OFFSET_RED_CELL =2 */ 5649 soc_mem_field32_set(unit, MMU_THDO_QOFFSET_CELLm, 5650 &mmu_thdo_qoffset_cell_entry, RESET_OFFSET_RED_CELLf,2); 5651 5652 SOC_IF_ERROR_RETURN(WRITE_MMU_THDO_QOFFSET_CELLm(unit, 5653 MEM_BLOCK_ANY,queue, 5654 &mmu_thdo_qoffset_cell_entry)); 5655 } 5656 } 5657 for (op_node_offset = 0; 5658 op_node_offset < sal_ceil_func(si->port_num_uc_cosq[port],8); 5659 op_node_offset++) { 5660 SOC_IF_ERROR_RETURN(READ_MMU_THDO_OPNCONFIG_QENTRYm(unit, 5661 MEM_BLOCK_ANY,op_node + op_node_offset, 5662 &mmu_thdo_opnconfig_qentry_entry)); 5663 /* C452:THDO_OPNCONFIG_QENTRY.OPN_SHARED_LIMIT_QENTRY = =$C$224 */ 5664 soc_mem_field32_set(unit, MMU_THDO_OPNCONFIG_QENTRYm, 5665 &mmu_thdo_opnconfig_qentry_entry, OPN_SHARED_LIMIT_QENTRYf, 5666 output_port_threshold->min_grntd_tot_shr_queue_cells_EQEs); 5667 5668 /* C453:THDO_OPNCONFIG_QENTRY.OP_SHARED_RESET_VALUE_QENTRY 5669 =C452-2 */ 5670 temp_val = output_port_threshold-> 5671 min_grntd_tot_shr_queue_cells_EQEs - 2; 5672 soc_mem_field32_set(unit, MMU_THDO_OPNCONFIG_QENTRYm, 5673 &mmu_thdo_opnconfig_qentry_entry, 5674 OPN_SHARED_RESET_VALUE_QENTRYf, temp_val); 5675 5676 /* C454:THDO_OPNCONFIG_QENTRY.PORT_LIMIT_ENABLE_QENTRY 5677 = 0 */ 5678 soc_mem_field32_set(unit, MMU_THDO_OPNCONFIG_QENTRYm, 5679 &mmu_thdo_opnconfig_qentry_entry, 5680 PORT_LIMIT_ENABLE_QENTRYf, 0); 5681 soc_mem_field32_set(unit, MMU_THDO_OPNCONFIG_QENTRYm, 5682 &mmu_thdo_opnconfig_qentry_entry, 5683 PIDf, port); 5684 SOC_IF_ERROR_RETURN(WRITE_MMU_THDO_OPNCONFIG_QENTRYm(unit, 5685 MEM_BLOCK_ANY,op_node + op_node_offset, 5686 &mmu_thdo_opnconfig_qentry_entry)); 5687 } 5688 for (queue = si->port_uc_cosq_base[port]; 5689 queue < si->port_uc_cosq_base[port] + si->port_num_uc_cosq[port]; 5690 queue++) { 5691 5692 5693 SOC_IF_ERROR_RETURN(READ_MMU_THDO_QCONFIG_QENTRYm(unit, 5694 MEM_BLOCK_ANY,queue, 5695 &mmu_thdo_qconfig_qentry_entry)); 5696 /* C455:THDO_QCONFIG_QENTRY.Q_MIN_QENTRY = =$C$206 */ 5697 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_QENTRYm, 5698 &mmu_thdo_qconfig_qentry_entry, Q_MIN_QENTRYf, 5699 queue < general_info->total_egr_base_queues_in_device ? 5700 output_port_threshold->min_grntd_res_queue_cells_EQEs : 0); 5701 5702 /* C456:THDO_QCONFIG_QENTRY.Q_SHARED_LIMIT_QENTRY 5703 =IF($C$14,$C$224,$C$63) */ 5704 if (_soc_ml_mmu_params.lossless_mode_d_c) { 5705 temp_val = output_port_threshold-> 5706 min_grntd_tot_shr_queue_cells_EQEs; 5707 } else { 5708 temp_val = _soc_ml_mmu_params. 5709 mmu_egr_queue_dyn_thd_param_baf_profile_lossy; 5710 } 5711 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_QENTRYm, 5712 &mmu_thdo_qconfig_qentry_entry, Q_SHARED_LIMIT_QENTRYf, temp_val); 5713 5714 /* C458:THDO_QCONFIG_QENTRY.Q_LIMIT_DYNAMIC_QENTRY 5715 =IF($C$14, 0, 1) */ 5716 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_QENTRYm, 5717 &mmu_thdo_qconfig_qentry_entry, Q_LIMIT_DYNAMIC_QENTRYf, 5718 _soc_ml_mmu_params.lossless_mode_d_c ? 0 : 1); 5719 5720 /* C459:THDO_QCONFIG_QENTRY.Q_LIMIT_ENABLE_QENTRY 5721 =IF($C$14, 0, 1) */ 5722 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_QENTRYm, 5723 &mmu_thdo_qconfig_qentry_entry, Q_LIMIT_ENABLE_QENTRYf, 5724 _soc_ml_mmu_params.lossless_mode_d_c ? 0 : 1); 5725 5726 /* C460:THDO_QCONFIG_QENTRY.Q_COLOR_ENABLE_QENTRY = 0 */ 5727 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_QENTRYm, 5728 &mmu_thdo_qconfig_qentry_entry, Q_COLOR_ENABLE_QENTRYf,0); 5729 5730 /* C461: THDO_QCONFIG_QENTRY.Q_COLOR_LIMIT_DYNAMIC_QENTRY 5731 =IF($C$14, 0, 1) */ 5732 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_QENTRYm, 5733 &mmu_thdo_qconfig_qentry_entry, 5734 Q_COLOR_LIMIT_DYNAMIC_QENTRYf, 5735 _soc_ml_mmu_params.lossless_mode_d_c ? 0 : 1); 5736 5737 /* C462: THDO_QCONFIG_QENTRY.LIMIT_YELLOW_QENTRY= 0 */ 5738 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_QENTRYm, 5739 &mmu_thdo_qconfig_qentry_entry, LIMIT_YELLOW_QENTRYf, 5740 0); 5741 SOC_IF_ERROR_RETURN(WRITE_MMU_THDO_QCONFIG_QENTRYm(unit, 5742 MEM_BLOCK_ANY,queue, 5743 &mmu_thdo_qconfig_qentry_entry)); 5744 5745 SOC_IF_ERROR_RETURN(READ_MMU_THDO_QOFFSET_QENTRYm(unit, 5746 MEM_BLOCK_ANY,queue, 5747 &mmu_thdo_qoffset_qentry_entry)); 5748 /* C457:THDO_QOFFSET_QENTRY.RESET_OFFSET_QENTRY =1 */ 5749 soc_mem_field32_set(unit, MMU_THDO_QOFFSET_QENTRYm, 5750 &mmu_thdo_qoffset_qentry_entry, RESET_OFFSET_QENTRYf, 1); 5751 5752 /* C463: THDO_QOFFSET_QENTRY.LIMIT_RED_QENTRY = 0 */ 5753 soc_mem_field32_set(unit, MMU_THDO_QOFFSET_QENTRYm, 5754 &mmu_thdo_qoffset_qentry_entry, LIMIT_RED_QENTRYf, 5755 0); 5756 5757 /* C464: THDO_QOFFSET_QENTRY.RESET_OFFSET_YELLOW_QENTRY =1 */ 5758 soc_mem_field32_set(unit, MMU_THDO_QOFFSET_QENTRYm, 5759 &mmu_thdo_qoffset_qentry_entry,RESET_OFFSET_YELLOW_QENTRYf,1); 5760 /* C465: THDO_QOFFSET_QENTRY.RESET_OFFSET_RED_QENTRY =1 */ 5761 soc_mem_field32_set(unit, MMU_THDO_QOFFSET_QENTRYm, 5762 &mmu_thdo_qoffset_qentry_entry, RESET_OFFSET_RED_QENTRYf,1); 5763 5764 SOC_IF_ERROR_RETURN(WRITE_MMU_THDO_QOFFSET_QENTRYm(unit, 5765 MEM_BLOCK_ANY,queue, 5766 &mmu_thdo_qoffset_qentry_entry)); 5767 } 5768 } 5769 for(cos=0; cos<SOC_REG_NUMELS(unit, OP_QUEUE_CONFIG1_THDORQEQr); cos++) { 5770 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_CONFIG1_THDORQEQr( 5771 unit, cos, &rval)); 5772 /* C467:OP_QUEUE_CONFIG1_THDORQEQ.Q_MIN = C208 */ 5773 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_THDORQEQr, &rval, 5774 Q_MINf, 5775 output_port_threshold->min_grntd_res_RE_WQs_cells); 5776 5777 /* C472:OP_QUEUE_CONFIG1_THDORQEQ.Q_COLOR_ENABLE = 0 */ 5778 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_THDORQEQr, &rval, 5779 Q_COLOR_ENABLEf, 0); 5780 5781 /* C473:OP_QUEUE_CONFIG1_THDORQEQ.Q_COLOR_DYNAMIC lossless=0 else 1 5782 =IF(C14=0, 1, 0) */ 5783 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_THDORQEQr, &rval, 5784 Q_COLOR_DYNAMICf, 5785 _soc_ml_mmu_params.lossless_mode_d_c? 0 : 1); 5786 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_CONFIG1_THDORQEQr( 5787 unit, cos, rval)); 5788 } 5789 5790 for(cos=0; cos<SOC_REG_NUMELS(unit, OP_QUEUE_CONFIG_THDORQEQr); cos++) { 5791 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_CONFIG_THDORQEQr( 5792 unit, cos, &rval)); 5793 /* C468:OP_QUEUE_CONFIG_THDORQEQ.Q_SHARED_LIMIT 5794 ==IF($C$14,$C$226,$C$63) */ 5795 if (_soc_ml_mmu_params.lossless_mode_d_c) { 5796 temp_val = output_port_threshold-> 5797 min_grntd_tot_shr_RE_WQs_cells ; 5798 } else { 5799 temp_val = 5800 _soc_ml_mmu_params.mmu_egr_queue_dyn_thd_param_baf_profile_lossy; 5801 } 5802 5803 soc_reg_field_set(unit, OP_QUEUE_CONFIG_THDORQEQr, &rval, 5804 Q_SHARED_LIMITf, temp_val); 5805 5806 /*C470: OP_QUEUE_CONFIG_THDORQEQ.Q_LIMIT_DYNAMIC:=lossless=0 else 1 5807 =IF(C14=0, 1, 0) */ 5808 5809 soc_reg_field_set(unit, OP_QUEUE_CONFIG_THDORQEQr, &rval, 5810 Q_LIMIT_DYNAMICf, 5811 _soc_ml_mmu_params.lossless_mode_d_c? 0 : 1); 5812 5813 /*C471:OP_QUEUE_CONFIG_THDORQEQ.Q_LIMIT_ENABLE:=lossless=0 else 1*/ 5814 soc_reg_field_set(unit, OP_QUEUE_CONFIG_THDORQEQr, &rval, 5815 Q_LIMIT_ENABLEf, 5816 _soc_ml_mmu_params.lossless_mode_d_c? 0 : 1); 5817 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_CONFIG_THDORQEQr( 5818 unit, cos, rval)); 5819 5820 } 5821 for(cos=0; 5822 cos<SOC_REG_NUMELS(unit, OP_QUEUE_RESET_OFFSET_THDORQEQr); cos++) { 5823 SOC_IF_ERROR_RETURN( 5824 READ_OP_QUEUE_RESET_OFFSET_THDORQEQr(unit, cos,&rval)); 5825 /*C469: OP_QUEUE_RESET_OFFSET_THDORQEQ.Q_RESET_OFFSET == 1 */ 5826 soc_reg_field_set(unit, OP_QUEUE_RESET_OFFSET_THDORQEQr, &rval, 5827 Q_RESET_OFFSETf, 1); 5828 SOC_IF_ERROR_RETURN( 5829 WRITE_OP_QUEUE_RESET_OFFSET_THDORQEQr(unit, cos,rval)); 5830 } 5831 for(cos=0; 5832 cos<SOC_REG_NUMELS(unit, OP_QUEUE_LIMIT_YELLOW_THDORQEQr); 5833 cos++) { 5834 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_LIMIT_YELLOW_THDORQEQr( 5835 unit, cos,&rval)); 5836 /* C474: OP_QUEUE_LIMIT_YELLOW_THDORQEQ.Q_LIMIT_YELLOW 0 */ 5837 soc_reg_field_set(unit, OP_QUEUE_LIMIT_YELLOW_THDORQEQr, &rval, 5838 Q_LIMIT_YELLOWf, 0); 5839 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_LIMIT_YELLOW_THDORQEQr( 5840 unit, cos,rval)); 5841 } 5842 for(cos=0; 5843 cos<SOC_REG_NUMELS(unit, OP_QUEUE_LIMIT_RED_THDORQEQr); 5844 cos++) { 5845 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_LIMIT_RED_THDORQEQr( 5846 unit, cos,&rval)); 5847 /* C475: OP_QUEUE_LIMIT_RED_THDORQEQ.Q_LIMIT_RED =0 */ 5848 soc_reg_field_set(unit, OP_QUEUE_LIMIT_RED_THDORQEQr, &rval, 5849 Q_LIMIT_REDf, 0); 5850 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_LIMIT_RED_THDORQEQr( 5851 unit, cos,rval)); 5852 } 5853 for(cos=0; 5854 cos < SOC_REG_NUMELS(unit, OP_QUEUE_RESET_OFFSET_YELLOW_THDORQEQr); 5855 cos++) { 5856 SOC_IF_ERROR_RETURN( 5857 READ_OP_QUEUE_RESET_OFFSET_YELLOW_THDORQEQr(unit, cos,&rval)); 5858 /*C476:OP_QUEUE_RESET_OFFSET_YELLOW_THDORQEQ.RESUME_OFFSET_YELLOW=1*/ 5859 soc_reg_field_set(unit, 5860 OP_QUEUE_RESET_OFFSET_YELLOW_THDORQEQr, &rval, 5861 RESUME_OFFSET_YELLOWf, 1); 5862 SOC_IF_ERROR_RETURN( 5863 WRITE_OP_QUEUE_RESET_OFFSET_YELLOW_THDORQEQr(unit, cos,rval)); 5864 } 5865 for(cos=0; 5866 cos < SOC_REG_NUMELS(unit, OP_QUEUE_RESET_OFFSET_RED_THDORQEQr); 5867 cos++) { 5868 SOC_IF_ERROR_RETURN( 5869 READ_OP_QUEUE_RESET_OFFSET_RED_THDORQEQr(unit, cos,&rval)); 5870 /*C477:OP_QUEUE_RESET_OFFSET_RED_THDORQEQ.RESUME_OFFSET_RED=1*/ 5871 soc_reg_field_set(unit, 5872 OP_QUEUE_RESET_OFFSET_RED_THDORQEQr, &rval, 5873 RESUME_OFFSET_REDf, 1); 5874 SOC_IF_ERROR_RETURN( 5875 WRITE_OP_QUEUE_RESET_OFFSET_RED_THDORQEQr(unit, cos,rval)); 5876 } 5877 /* 2.4.2 RQEI */ 5878 for(cos=0; cos<SOC_REG_NUMELS(unit, OP_QUEUE_CONFIG1_THDORQEIr); cos++) { 5879 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_CONFIG1_THDORQEIr( 5880 unit, cos, &rval)); 5881 /* C478:OP_QUEUE_CONFIG1_THDORQEI.Q_MIN = C209 */ 5882 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_THDORQEIr, &rval, Q_MINf, 5883 output_port_threshold->min_grntd_res_RE_WQs_queue_cells_for_int_buff); 5884 5885 /* C483:OP_QUEUE_CONFIG1_THDORQEI.Q_COLOR_ENABLE = 0 */ 5886 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_THDORQEIr, &rval, 5887 Q_COLOR_ENABLEf, 0); 5888 5889 /* C484:OP_QUEUE_CONFIG1_THDORQEI.Q_COLOR_DYNAMIC lossless=0 else 1 5890 =IF($C$14, 0, 1)*/ 5891 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_THDORQEIr, &rval, 5892 Q_COLOR_DYNAMICf, 5893 _soc_ml_mmu_params.lossless_mode_d_c? 0 : 1); 5894 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_CONFIG1_THDORQEIr( 5895 unit, cos, rval)); 5896 } 5897 5898 for(cos=0; cos<SOC_REG_NUMELS(unit, OP_QUEUE_CONFIG_THDORQEIr); cos++) { 5899 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_CONFIG_THDORQEIr( 5900 unit, cos, &rval)); 5901 /* C479:OP_QUEUE_CONFIG_THDORQEI.Q_SHARED_LIMIT 5902 =IF($C$14,$C$227,$C$63)..Can be put outside loop */ 5903 if (_soc_ml_mmu_params.lossless_mode_d_c) { 5904 temp_val = output_port_threshold->min_grntd_tot_shr_RE_WQs_queue_cells_for_int_buff; 5905 } else { 5906 temp_val = _soc_ml_mmu_params.mmu_egr_queue_dyn_thd_param_baf_profile_lossy; 5907 } 5908 soc_reg_field_set(unit, OP_QUEUE_CONFIG_THDORQEIr, &rval, 5909 Q_SHARED_LIMITf, temp_val); 5910 5911 /*C481: OP_QUEUE_CONFIG_THDORQEI.Q_LIMIT_DYNAMIC:=lossless=0 else 1 5912 =IF($C$14, 0, 1)*/ 5913 5914 soc_reg_field_set(unit, OP_QUEUE_CONFIG_THDORQEIr, &rval, 5915 Q_LIMIT_DYNAMICf, 5916 _soc_ml_mmu_params.lossless_mode_d_c? 0 : 1); 5917 5918 /*C482:OP_QUEUE_CONFIG_THDORQEI.Q_LIMIT_ENABLE:=lossless=0 else 1 5919 =IF($C$14, 0, 1) */ 5920 soc_reg_field_set(unit, OP_QUEUE_CONFIG_THDORQEIr, &rval, 5921 Q_LIMIT_ENABLEf, 5922 _soc_ml_mmu_params.lossless_mode_d_c? 0 : 1); 5923 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_CONFIG_THDORQEIr( 5924 unit, cos, rval)); 5925 5926 } 5927 for(cos=0; 5928 cos<SOC_REG_NUMELS(unit, OP_QUEUE_RESET_OFFSET_THDORQEIr); cos++) { 5929 SOC_IF_ERROR_RETURN( 5930 READ_OP_QUEUE_RESET_OFFSET_THDORQEIr(unit, cos,&rval)); 5931 /*C480: OP_QUEUE_RESET_OFFSET_THDORQEI.Q_RESET_OFFSET == 2 */ 5932 soc_reg_field_set(unit, OP_QUEUE_RESET_OFFSET_THDORQEIr, &rval, 5933 Q_RESET_OFFSETf, 2); 5934 SOC_IF_ERROR_RETURN( 5935 WRITE_OP_QUEUE_RESET_OFFSET_THDORQEIr(unit, cos,rval)); 5936 } 5937 for(cos=0; 5938 cos<SOC_REG_NUMELS(unit, OP_QUEUE_LIMIT_YELLOW_THDORQEIr); 5939 cos++) { 5940 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_LIMIT_YELLOW_THDORQEIr( 5941 unit, cos,&rval)); 5942 /* C485: OP_QUEUE_LIMIT_YELLOW_THDORQEI.Q_LIMIT_YELLOW =0 */ 5943 soc_reg_field_set(unit, OP_QUEUE_LIMIT_YELLOW_THDORQEIr, &rval, 5944 Q_LIMIT_YELLOWf, 0); 5945 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_LIMIT_YELLOW_THDORQEIr( 5946 unit, cos,rval)); 5947 } 5948 for(cos=0; 5949 cos<SOC_REG_NUMELS(unit, OP_QUEUE_LIMIT_RED_THDORQEIr); 5950 cos++) { 5951 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_LIMIT_RED_THDORQEIr( 5952 unit, cos,&rval)); 5953 /* C486: OP_QUEUE_LIMIT_RED_THDORQEI.Q_LIMIT_RED = 0*/ 5954 soc_reg_field_set(unit, OP_QUEUE_LIMIT_RED_THDORQEIr, &rval, 5955 Q_LIMIT_REDf, 0); 5956 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_LIMIT_RED_THDORQEIr( 5957 unit, cos,rval)); 5958 } 5959 for(cos=0; 5960 cos < SOC_REG_NUMELS(unit, OP_QUEUE_RESET_OFFSET_YELLOW_THDORQEIr); 5961 cos++) { 5962 SOC_IF_ERROR_RETURN( 5963 READ_OP_QUEUE_RESET_OFFSET_YELLOW_THDORQEIr(unit, cos,&rval)); 5964 /*C487:OP_QUEUE_RESET_OFFSET_YELLOW_THDORQEI.RESUME_OFFSET_YELLOW=2*/ 5965 soc_reg_field_set(unit, 5966 OP_QUEUE_RESET_OFFSET_YELLOW_THDORQEIr, &rval, 5967 RESUME_OFFSET_YELLOWf, 2); 5968 SOC_IF_ERROR_RETURN( 5969 WRITE_OP_QUEUE_RESET_OFFSET_YELLOW_THDORQEIr(unit, cos,rval)); 5970 } 5971 for(cos=0; 5972 cos < SOC_REG_NUMELS(unit, OP_QUEUE_RESET_OFFSET_RED_THDORQEIr); 5973 cos++) { 5974 SOC_IF_ERROR_RETURN( 5975 READ_OP_QUEUE_RESET_OFFSET_RED_THDORQEIr(unit, cos,&rval)); 5976 /*C488:OP_QUEUE_RESET_OFFSET_RED_THDORQEI.RESUME_OFFSET_RED=2*/ 5977 soc_reg_field_set(unit, 5978 OP_QUEUE_RESET_OFFSET_RED_THDORQEIr, &rval, 5979 RESUME_OFFSET_REDf, 2); 5980 SOC_IF_ERROR_RETURN( 5981 WRITE_OP_QUEUE_RESET_OFFSET_RED_THDORQEIr(unit, cos,rval)); 5982 } 5983 for(cos=0; cos<SOC_REG_NUMELS(unit, OP_QUEUE_CONFIG1_THDORDEQr); cos++) { 5984 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_CONFIG1_THDORDEQr( 5985 unit, cos, &rval)); 5986 /* C501:OP_QUEUE_CONFIG1_THDORDEQ.Q_MIN = C211 */ 5987 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_THDORDEQr, &rval, Q_MINf, 5988 output_port_threshold->min_grntd_res_EP_redirect_queue_entry_cells); 5989 5990 /* C506:OP_QUEUE_CONFIG1_THDORDEQ.Q_COLOR_ENABLE = 0 */ 5991 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_THDORDEQr, &rval, 5992 Q_COLOR_ENABLEf, 0); 5993 5994 /* C507:OP_QUEUE_CONFIG1_THDORDEQ.Q_COLOR_DYNAMIC lossless=0 else 1 5995 =IF(C14=0, 1, 0)*/ 5996 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_THDORDEQr, &rval, 5997 Q_COLOR_DYNAMICf, 5998 _soc_ml_mmu_params.lossless_mode_d_c? 0 : 1); 5999 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_CONFIG1_THDORDEQr( 6000 unit, cos, rval)); 6001 } 6002 6003 for(cos=0; cos<SOC_REG_NUMELS(unit, OP_QUEUE_CONFIG_THDORDEQr); cos++) { 6004 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_CONFIG_THDORDEQr( 6005 unit, cos, &rval)); 6006 /* C502:OP_QUEUE_CONFIG_THDORDEQ.Q_SHARED_LIMIT 6007 =IF(C14=0, C63, C229)..Can be put outside loop */ 6008 if (_soc_ml_mmu_params.lossless_mode_d_c) { 6009 temp_val = output_port_threshold->min_grntd_tot_shr_EP_redirect_queue_entry_cells; 6010 } else { 6011 temp_val = _soc_ml_mmu_params.mmu_egr_queue_dyn_thd_param_baf_profile_lossy; 6012 } 6013 soc_reg_field_set(unit, OP_QUEUE_CONFIG_THDORDEQr, &rval, 6014 Q_SHARED_LIMITf, temp_val); 6015 6016 /*C504: OP_QUEUE_CONFIG_THDORDEQ.Q_LIMIT_DYNAMIC:=lossless=0 else 1i 6017 =IF(C14=0, 1, 0)*/ 6018 6019 soc_reg_field_set(unit, OP_QUEUE_CONFIG_THDORDEQr, &rval, 6020 Q_LIMIT_DYNAMICf, 6021 _soc_ml_mmu_params.lossless_mode_d_c? 0 : 1); 6022 6023 /*C505:OP_QUEUE_CONFIG_THDORDEQ.Q_LIMIT_ENABLE:=lossless=0 else 1 6024 =IF(C14=0, 1, 0)*/ 6025 soc_reg_field_set(unit, OP_QUEUE_CONFIG_THDORDEQr, &rval, 6026 Q_LIMIT_ENABLEf, 6027 _soc_ml_mmu_params.lossless_mode_d_c? 0 : 1); 6028 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_CONFIG_THDORDEQr( 6029 unit, cos, rval)); 6030 6031 } 6032 for(cos=0; 6033 cos<SOC_REG_NUMELS(unit, OP_QUEUE_RESET_OFFSET_THDORDEQr); cos++) { 6034 SOC_IF_ERROR_RETURN( 6035 READ_OP_QUEUE_RESET_OFFSET_THDORDEQr(unit, cos,&rval)); 6036 /*C503: OP_QUEUE_RESET_OFFSET_THDORDEQ.Q_RESET_OFFSET == 1 */ 6037 soc_reg_field_set(unit, OP_QUEUE_RESET_OFFSET_THDORDEQr, &rval, 6038 Q_RESET_OFFSETf, 1); 6039 SOC_IF_ERROR_RETURN( 6040 WRITE_OP_QUEUE_RESET_OFFSET_THDORDEQr(unit, cos,rval)); 6041 } 6042 for(cos=0; 6043 cos<SOC_REG_NUMELS(unit, OP_QUEUE_LIMIT_YELLOW_THDORDEQr); 6044 cos++) { 6045 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_LIMIT_YELLOW_THDORDEQr( 6046 unit, cos,&rval)); 6047 /* C508: OP_QUEUE_LIMIT_YELLOW_THDORDEQ.Q_LIMIT_YELLOW = 0 */ 6048 soc_reg_field_set(unit, OP_QUEUE_LIMIT_YELLOW_THDORDEQr, &rval, 6049 Q_LIMIT_YELLOWf, 0); 6050 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_LIMIT_YELLOW_THDORDEQr( 6051 unit, cos,rval)); 6052 } 6053 for(cos=0; 6054 cos<SOC_REG_NUMELS(unit, OP_QUEUE_LIMIT_RED_THDORDEQr); 6055 cos++) { 6056 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_LIMIT_RED_THDORDEQr( 6057 unit, cos,&rval)); 6058 /* C509: OP_QUEUE_LIMIT_RED_THDORDEQ.Q_LIMIT_RED = 0 */ 6059 soc_reg_field_set(unit, OP_QUEUE_LIMIT_RED_THDORDEQr, &rval, 6060 Q_LIMIT_REDf, 0); 6061 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_LIMIT_RED_THDORDEQr( 6062 unit, cos,rval)); 6063 } 6064 for(cos=0; 6065 cos < SOC_REG_NUMELS(unit, OP_QUEUE_RESET_OFFSET_YELLOW_THDORDEQr); 6066 cos++) { 6067 SOC_IF_ERROR_RETURN( 6068 READ_OP_QUEUE_RESET_OFFSET_YELLOW_THDORDEQr(unit, cos,&rval)); 6069 /*C510:OP_QUEUE_RESET_OFFSET_YELLOW_THDORDEQ.RESUME_OFFSET_YELLOW=1*/ 6070 soc_reg_field_set(unit, 6071 OP_QUEUE_RESET_OFFSET_YELLOW_THDORDEQr, &rval, 6072 RESUME_OFFSET_YELLOWf, 1); 6073 SOC_IF_ERROR_RETURN( 6074 WRITE_OP_QUEUE_RESET_OFFSET_YELLOW_THDORDEQr(unit, cos,rval)); 6075 } 6076 for(cos=0; 6077 cos < SOC_REG_NUMELS(unit, OP_QUEUE_RESET_OFFSET_RED_THDORDEQr); 6078 cos++) { 6079 SOC_IF_ERROR_RETURN( 6080 READ_OP_QUEUE_RESET_OFFSET_RED_THDORDEQr(unit, cos,&rval)); 6081 /*C511:OP_QUEUE_RESET_OFFSET_RED_THDORDEQ.RESUME_OFFSET_RED=1*/ 6082 soc_reg_field_set(unit, 6083 OP_QUEUE_RESET_OFFSET_RED_THDORDEQr, &rval, 6084 RESUME_OFFSET_REDf, 1); 6085 SOC_IF_ERROR_RETURN( 6086 WRITE_OP_QUEUE_RESET_OFFSET_RED_THDORDEQr(unit, cos,rval)); 6087 } 6088 for(cos=0; cos<SOC_REG_NUMELS(unit, OP_QUEUE_CONFIG1_THDORDEIr); cos++) { 6089 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_CONFIG1_THDORDEIr( 6090 unit, cos, &rval)); 6091 /* C512:OP_QUEUE_CONFIG1_THDORDEI.Q_MIN = 9 (C204) */ 6092 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_THDORDEIr, &rval, 6093 Q_MINf, output_port_threshold->min_grntd_res_queue_cells_int_buff); 6094 6095 /* C517:OP_QUEUE_CONFIG1_THDORDEI.Q_COLOR_ENABLE = 0 */ 6096 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_THDORDEIr, &rval, 6097 Q_COLOR_ENABLEf, 0); 6098 6099 /* C518:OP_QUEUE_CONFIG1_THDORDEI.Q_COLOR_DYNAMIC = 1*/ 6100 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_THDORDEIr, &rval, 6101 Q_COLOR_DYNAMICf, _soc_ml_mmu_params.lossless_mode_d_c? 0 :1); 6102 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_CONFIG1_THDORDEIr( 6103 unit, cos, rval)); 6104 } 6105 6106 for(cos=0; cos<SOC_REG_NUMELS(unit, OP_QUEUE_CONFIG_THDORDEIr); cos++) { 6107 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_CONFIG_THDORDEIr( 6108 unit, cos, &rval)); 6109 /* C513:OP_QUEUE_CONFIG_THDORDEI.Q_SHARED_LIMIT = 6110 =IF(C14=0, C63, C222)*/ 6111 if (_soc_ml_mmu_params.lossless_mode_d_c) { 6112 temp_val = output_port_threshold->min_grntd_tot_shr_queue_cells_int_buff; 6113 } else { 6114 temp_val = _soc_ml_mmu_params.mmu_egr_queue_dyn_thd_param_baf_profile_lossy; 6115 } 6116 6117 soc_reg_field_set(unit, OP_QUEUE_CONFIG_THDORDEIr, &rval, 6118 Q_SHARED_LIMITf, temp_val); 6119 6120 /*C515: OP_QUEUE_CONFIG_THDORDEI.Q_LIMIT_DYNAMIC:=1 6121 =IF(C14=0, 1, 0)*/ 6122 6123 soc_reg_field_set(unit, OP_QUEUE_CONFIG_THDORDEIr, &rval, 6124 Q_LIMIT_DYNAMICf, 6125 _soc_ml_mmu_params.lossless_mode_d_c ? 0 :1); 6126 6127 /*C516:OP_QUEUE_CONFIG_THDORDEI.Q_LIMIT_ENABLE: 6128 =IF(C14=0, 1, 0)*/ 6129 soc_reg_field_set(unit, OP_QUEUE_CONFIG_THDORDEIr, &rval, 6130 Q_LIMIT_ENABLEf, 6131 _soc_ml_mmu_params.lossless_mode_d_c ? 0 :1); 6132 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_CONFIG_THDORDEIr( 6133 unit, cos, rval)); 6134 } 6135 for(cos=0; 6136 cos<SOC_REG_NUMELS(unit, OP_QUEUE_RESET_OFFSET_THDORDEIr); cos++) { 6137 SOC_IF_ERROR_RETURN( 6138 READ_OP_QUEUE_RESET_OFFSET_THDORDEIr(unit, cos,&rval)); 6139 /*C514: OP_QUEUE_RESET_OFFSET_THDORDEI.Q_RESET_OFFSET == 2 */ 6140 soc_reg_field_set(unit, OP_QUEUE_RESET_OFFSET_THDORDEIr, &rval, 6141 Q_RESET_OFFSETf, 2); 6142 SOC_IF_ERROR_RETURN( 6143 WRITE_OP_QUEUE_RESET_OFFSET_THDORDEIr(unit, cos,rval)); 6144 } 6145 for(cos=0; 6146 cos<SOC_REG_NUMELS(unit, OP_QUEUE_LIMIT_YELLOW_THDORDEIr); 6147 cos++) { 6148 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_LIMIT_YELLOW_THDORDEIr( 6149 unit, cos,&rval)); 6150 /* C519: OP_QUEUE_LIMIT_YELLOW_THDORDEI.Q_LIMIT_YELLOW = 0 */ 6151 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_CONFIG_THDORDEIr( 6152 unit, cos, &rval)); 6153 temp_val = soc_reg_field_get(unit, OP_QUEUE_CONFIG_THDORDEIr, rval, 6154 Q_SHARED_LIMITf); 6155 6156 soc_reg_field_set(unit, OP_QUEUE_LIMIT_YELLOW_THDORDEIr, &rval, 6157 Q_LIMIT_YELLOWf, 0); 6158 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_LIMIT_YELLOW_THDORDEIr( 6159 unit, cos,rval)); 6160 } 6161 for(cos=0; 6162 cos<SOC_REG_NUMELS(unit, OP_QUEUE_LIMIT_RED_THDORDEIr); 6163 cos++) { 6164 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_LIMIT_RED_THDORDEIr( 6165 unit, cos,&rval)); 6166 /* C520: OP_QUEUE_LIMIT_RED_THDORDEI.Q_LIMIT_RED = C486 */ 6167 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_CONFIG_THDORDEIr( 6168 unit, cos, &rval)); 6169 temp_val = soc_reg_field_get(unit, OP_QUEUE_CONFIG_THDORDEIr, rval, 6170 Q_SHARED_LIMITf); 6171 6172 soc_reg_field_set(unit, OP_QUEUE_LIMIT_RED_THDORDEIr, &rval, 6173 Q_LIMIT_REDf, 0); 6174 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_LIMIT_RED_THDORDEIr( 6175 unit, cos,rval)); 6176 } 6177 for(cos=0; 6178 cos < SOC_REG_NUMELS(unit, OP_QUEUE_RESET_OFFSET_YELLOW_THDORDEIr); 6179 cos++) { 6180 SOC_IF_ERROR_RETURN( 6181 READ_OP_QUEUE_RESET_OFFSET_YELLOW_THDORDEIr(unit, cos,&rval)); 6182 /*C521:OP_QUEUE_RESET_OFFSET_YELLOW_THDORDEI.RESUME_OFFSET_YELLOW=2*/ 6183 soc_reg_field_set(unit, 6184 OP_QUEUE_RESET_OFFSET_YELLOW_THDORDEIr, &rval, 6185 RESUME_OFFSET_YELLOWf, 2); 6186 SOC_IF_ERROR_RETURN( 6187 WRITE_OP_QUEUE_RESET_OFFSET_YELLOW_THDORDEIr(unit, cos,rval)); 6188 } 6189 for(cos=0; 6190 cos < SOC_REG_NUMELS(unit, OP_QUEUE_RESET_OFFSET_RED_THDORDEIr); 6191 cos++) { 6192 SOC_IF_ERROR_RETURN( 6193 READ_OP_QUEUE_RESET_OFFSET_RED_THDORDEIr(unit, cos,&rval)); 6194 /*C522:OP_QUEUE_RESET_OFFSET_RED_THDORDEI.RESUME_OFFSET_RED=2*/ 6195 soc_reg_field_set(unit, 6196 OP_QUEUE_RESET_OFFSET_RED_THDORDEIr, &rval, 6197 RESUME_OFFSET_REDf, 2); 6198 SOC_IF_ERROR_RETURN( 6199 WRITE_OP_QUEUE_RESET_OFFSET_RED_THDORDEIr(unit, cos,rval)); 6200 } 6201 /* Enable back pressure status from MMU for lossless mode */ 6202 if (_soc_ml_mmu_params.lossless_mode_d_c) { 6203 val = 0x3ffffffe; /* 0 to 29 ports */ 6204 sal_memset (&rval, 0, sizeof(rval)); 6205 soc_reg_field_set(unit, THDIQEN_PORT_PAUSE_ENABLE_64r, &rval, 6206 PORT_PAUSE_ENABLEf, val); 6207 SOC_IF_ERROR_RETURN 6208 (soc_reg32_set(unit, THDIQEN_PORT_PAUSE_ENABLE_64r,REG_PORT_ANY, 6209 0, rval)); 6210 6211 sal_memset (&rval, 0, sizeof(rval)); 6212 soc_reg_field_set(unit, THDIRQE_PORT_PAUSE_ENABLE_64r, &rval, 6213 PORT_PAUSE_ENABLEf, val); 6214 SOC_IF_ERROR_RETURN 6215 (soc_reg32_set(unit, THDIRQE_PORT_PAUSE_ENABLE_64r,REG_PORT_ANY, 6216 0, rval)); 6217 6218 sal_memset (&rval, 0, sizeof(rval)); 6219 soc_reg_field_set(unit, PORT_PAUSE_ENABLE_64r, &rval, 6220 PORT_PAUSE_ENABLEf, val); 6221 SOC_IF_ERROR_RETURN 6222 (soc_reg32_set(unit, PORT_PAUSE_ENABLE_64r,REG_PORT_ANY, 6223 0, rval)); 6224 } 6225 /* ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ 6226 /* OpNode related config for remaining OpNodes */ 6227 /* (assuming internal memory settings) */ 6228 /* ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ 6229 for (op_node = soc_mem_index_min(unit,MMU_THDO_OPNCONFIG_CELLm); 6230 op_node <= soc_mem_index_max(unit,MMU_THDO_OPNCONFIG_CELLm); 6231 op_node++) { 6232 temp_val = 0 ; 6233 SOC_IF_ERROR_RETURN(READ_MMU_THDO_OPNCONFIG_CELLm(unit, 6234 MEM_BLOCK_ANY,op_node , 6235 &mmu_thdo_opnconfig_cell_entry)); 6236 temp_val = soc_mem_field32_get(unit, MMU_THDO_OPNCONFIG_CELLm, 6237 &mmu_thdo_opnconfig_cell_entry, 6238 OPN_SHARED_LIMIT_CELLf); 6239 if (temp_val == 0) { 6240 soc_mem_field32_set(unit, MMU_THDO_OPNCONFIG_CELLm, 6241 &mmu_thdo_opnconfig_cell_entry, 6242 OPN_SHARED_LIMIT_CELLf, 6243 output_port_threshold-> 6244 min_grntd_tot_shr_queue_cells_int_buff); 6245 temp_val = output_port_threshold-> 6246 min_grntd_tot_shr_queue_cells_int_buff - 6247 (2 * general_info->ether_mtu_cells_for_int_buff); 6248 soc_mem_field32_set(unit, MMU_THDO_OPNCONFIG_CELLm, 6249 &mmu_thdo_opnconfig_cell_entry, 6250 OPN_SHARED_RESET_VALUE_CELLf, temp_val); 6251 soc_mem_field32_set(unit, MMU_THDO_OPNCONFIG_CELLm, 6252 &mmu_thdo_opnconfig_cell_entry, 6253 PORT_LIMIT_ENABLE_CELLf, 0); 6254 SOC_IF_ERROR_RETURN(WRITE_MMU_THDO_OPNCONFIG_CELLm(unit, 6255 MEM_BLOCK_ALL,op_node, 6256 &mmu_thdo_opnconfig_cell_entry)); 6257 } 6258 } 6259 for (op_node = soc_mem_index_min(unit,MMU_THDO_OPNCONFIG_QENTRYm); 6260 op_node <= soc_mem_index_max(unit,MMU_THDO_OPNCONFIG_QENTRYm); 6261 op_node++) { 6262 temp_val = 0 ; 6263 SOC_IF_ERROR_RETURN(READ_MMU_THDO_OPNCONFIG_QENTRYm(unit, 6264 MEM_BLOCK_ANY,op_node , 6265 &mmu_thdo_opnconfig_qentry_entry)); 6266 temp_val = soc_mem_field32_get(unit, MMU_THDO_OPNCONFIG_QENTRYm, 6267 &mmu_thdo_opnconfig_qentry_entry, 6268 OPN_SHARED_LIMIT_QENTRYf); 6269 if (temp_val == 0) { 6270 soc_mem_field32_set(unit, MMU_THDO_OPNCONFIG_QENTRYm, 6271 &mmu_thdo_opnconfig_qentry_entry, OPN_SHARED_LIMIT_QENTRYf, 6272 output_port_threshold->min_grntd_tot_shr_queue_cells_EQEs); 6273 6274 temp_val = output_port_threshold-> 6275 min_grntd_tot_shr_queue_cells_EQEs - 2; 6276 soc_mem_field32_set(unit, MMU_THDO_OPNCONFIG_QENTRYm, 6277 &mmu_thdo_opnconfig_qentry_entry, 6278 OPN_SHARED_RESET_VALUE_QENTRYf, temp_val); 6279 6280 soc_mem_field32_set(unit, MMU_THDO_OPNCONFIG_QENTRYm, 6281 &mmu_thdo_opnconfig_qentry_entry, 6282 PORT_LIMIT_ENABLE_QENTRYf, 0); 6283 /* 6284 soc_mem_field32_set(unit, MMU_THDO_OPNCONFIG_QENTRYm, 6285 &mmu_thdo_opnconfig_qentry_entry, 6286 PIDf, port); 6287 */ 6288 SOC_IF_ERROR_RETURN(WRITE_MMU_THDO_OPNCONFIG_QENTRYm(unit, 6289 MEM_BLOCK_ALL,op_node , 6290 &mmu_thdo_opnconfig_qentry_entry)); 6291 } 6292 } 6293 /* ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ 6294 /* Subport queue Settings */ 6295 /* (Assuming lossless-internal memory operation) */ 6296 /* ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ 6297 6298 for (sub_port = 0; 6299 sub_port <= SOC_ML_MAX_SUBPORTS; 6300 sub_port ++) { 6301 if (!_SOC_IS_PP_PORT_LINKPHY_SUBTAG(unit, sub_port)) { 6302 continue; 6303 } 6304 if ( si->port_uc_cosq_base[sub_port] != 0) { 6305 for (queue = si->port_uc_cosq_base[sub_port]; 6306 queue < si->port_uc_cosq_base[sub_port] + 6307 si->port_num_uc_cosq[sub_port]; 6308 queue++) { 6309 LOG_VERBOSE(BSL_LS_SOC_COMMON, 6310 (BSL_META_U(unit, 6311 "sub_port:%d queue:%d"), sub_port, queue)); 6312 SOC_IF_ERROR_RETURN( 6313 _soc_ml_mmu_config_extra_queue(unit, queue, 6314 &_soc_ml_mmu_params, 6315 output_port_threshold)); 6316 } 6317 } 6318 } 6319 /* ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ 6320 /* Extended Queue(BCM_COSQ_GPORT_SUBSCRIBE) Settings */ 6321 /* ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ 6322 6323 for (queue = si->port_uc_cosq_base[ML_MAX_PHYSICAL_PORTS] + 6324 si->port_num_uc_cosq[ML_MAX_PHYSICAL_PORTS]; 6325 queue <= soc_mem_index_max(unit,MMU_THDO_QCONFIG_CELLm); 6326 queue++) { 6327 SOC_IF_ERROR_RETURN( 6328 _soc_ml_mmu_config_extra_queue(unit, queue, 6329 &_soc_ml_mmu_params, 6330 output_port_threshold)); 6331 } 6332 return SOC_E_NONE; 6333 } 6334 6335 int _soc_ml_mmu_reconfigure(int unit, int port) 6336 { 6337 SOC_IF_ERROR_RETURN(_soc_ml_mmu_init_helper(unit, port)); 6338 LOG_CLI((BSL_META_U(unit, 6339 "MMU is reconfigured \n"))); 6340 return SOC_E_NONE; 6341 } 6342 6343 STATIC int 6344 _soc_ml_post_mmu_init(int unit) 6345 { 6346 txlp_port_addr_map_table_entry_t txlp_port_addr_map_table_entry={{0}}; 6347 uint32 start_addr=0; 6348 uint32 end_addr=0; 6349 int port = 0; 6350 int loop; 6351 soc_info_t *si; 6352 uint32 rval; 6353 6354 si = &SOC_INFO(unit); 6355 6356 if (SAL_BOOT_QUICKTURN) { 6357 soc_pbmp_t link_pbmp; 6358 epc_link_bmap_entry_t epc_link_bmap_entry={{0}}; 6359 6360 SOC_PBMP_ASSIGN(link_pbmp, PBMP_ALL(unit)); 6361 soc_mem_pbmp_field_set(unit, EPC_LINK_BMAPm, &epc_link_bmap_entry, 6362 PORT_BITMAPf,&link_pbmp); 6363 SOC_IF_ERROR_RETURN(WRITE_EPC_LINK_BMAPm( 6364 unit, MEM_BLOCK_ALL, 0, &epc_link_bmap_entry)); 6365 } 6366 6367 if ((si->block_valid[TXLP0_BLOCK(unit)] == 0)) { 6368 /* TXLP related ports are not valid */ 6369 return SOC_E_NONE; 6370 } 6371 6372 SOC_IF_ERROR_RETURN(READ_TXLP_HW_RESET_CONTROL_1r(unit, 1, &rval)); 6373 soc_reg_field_set(unit, TXLP_HW_RESET_CONTROL_1r, &rval, COUNTf, 256); 6374 soc_reg_field_set(unit, TXLP_HW_RESET_CONTROL_1r, &rval, RESET_ALLf, 1); 6375 soc_reg_field_set(unit, TXLP_HW_RESET_CONTROL_1r, &rval, VALIDf, 1); 6376 SOC_IF_ERROR_RETURN(WRITE_TXLP_HW_RESET_CONTROL_1r(unit, 1, rval)); 6377 6378 /* TXLP_PORT_ADDR_MAP_TABLE */ 6379 for(loop=0, start_addr=0,port=1 ; loop < ML_MAX_PORTS_PER_BLOCK; 6380 loop++, port++) { 6381 if (si->port_speed_max[port] <= 2500) { 6382 end_addr = start_addr + (( 8 * 4) - 1); /* 8 cells */ 6383 } else if(si->port_speed_max[port] <= 13000) { 6384 end_addr = start_addr + (( 16 * 4) - 1); 6385 } else { 6386 return SOC_E_PARAM; 6387 } 6388 6389 sal_memset(&txlp_port_addr_map_table_entry,0, 6390 sizeof(txlp_port_addr_map_table_entry_t)); 6391 soc_TXLP_PORT_ADDR_MAP_TABLEm_field_set(unit, 6392 &txlp_port_addr_map_table_entry,START_ADDRf,&start_addr); 6393 soc_TXLP_PORT_ADDR_MAP_TABLEm_field_set(unit, 6394 &txlp_port_addr_map_table_entry,END_ADDRf,&end_addr); 6395 start_addr = end_addr+1; 6396 6397 SOC_IF_ERROR_RETURN(WRITE_TXLP_PORT_ADDR_MAP_TABLEm( 6398 unit,SOC_INFO(unit).txlp_block[0], loop, 6399 &txlp_port_addr_map_table_entry)); 6400 } 6401 6402 return SOC_E_NONE; 6403 } 6404 int _soc_ml_invalid_parent_index(int unit, int level) 6405 { 6406 int index_max = 0; 6407 6408 switch (level) { 6409 case SOC_KT2_NODE_LVL_ROOT: 6410 index_max = 0; 6411 break; 6412 case SOC_KT2_NODE_LVL_L0: 6413 index_max = (1 << soc_mem_field_length(unit, LLS_L0_PARENTm, C_PARENTf)) - 1; 6414 break; 6415 case SOC_KT2_NODE_LVL_L1: 6416 index_max = (1 << soc_mem_field_length(unit, LLS_L1_PARENTm, C_PARENTf)) - 1; 6417 break; 6418 case SOC_KT2_NODE_LVL_L2: 6419 index_max = (1 << soc_mem_field_length(unit, LLS_L2_PARENTm, C_PARENTf)) - 1; 6420 break; 6421 default: 6422 break; 6423 6424 } 6425 6426 return index_max; 6427 } 6428 #define INVALID_PARENT(unit, level) _soc_ml_invalid_parent_index((unit),(level)) 6429 /* Programming all the entries with the Invalid Parent Pointer */ 6430 int 6431 _soc_ml_mmu_set_invalid_parent(int unit) 6432 { 6433 int level, index_max, index; 6434 soc_mem_t mem; 6435 uint32 entry[SOC_MAX_MEM_WORDS]; 6436 6437 for (level = SOC_KT2_NODE_LVL_L0; level <= SOC_KT2_NODE_LVL_L2; 6438 level++) { 6439 mem = _SOC_KT2_NODE_PARENT_MEM(level); 6440 /* coverity[negative_returns : FALSE] */ 6441 index_max = soc_mem_index_max(unit, mem); 6442 for (index = 0; index <= index_max; index++) { 6443 /* During reboot, mem reinitialized. So no need to read from cache */ 6444 SOC_IF_ERROR_RETURN 6445 (soc_mem_cache_invalidate(unit, mem, MEM_BLOCK_ALL, index)); 6446 SOC_IF_ERROR_RETURN 6447 (soc_mem_read(unit, mem, MEM_BLOCK_ALL, index, &entry)); 6448 soc_mem_field32_set(unit, mem, entry, 6449 C_PARENTf, INVALID_PARENT(unit,level)); 6450 SOC_IF_ERROR_RETURN 6451 (soc_mem_write(unit, mem, MEM_BLOCK_ALL, index, &entry)); 6452 } 6453 } 6454 return SOC_E_NONE; 6455 } 6456 STATIC int 6457 _soc_metrolite_mmu_init(int unit) 6458 { 6459 uint32 rval; 6460 int mmu_init_usec, i; 6461 soc_timeout_t to; 6462 mmu_aging_lmt_int_entry_t age_entry; 6463 int count; 6464 uint64 rval1; 6465 6466 /* Init Link List Scheduler */ 6467 rval = 0; 6468 soc_reg_field_set(unit, LLS_SOFT_RESETr, &rval, SOFT_RESETf, 0); 6469 SOC_IF_ERROR_RETURN(WRITE_LLS_SOFT_RESETr(unit, rval)); 6470 6471 rval = 0; 6472 soc_reg_field_set(unit, LLS_INITr, &rval, INITf, 1); 6473 SOC_IF_ERROR_RETURN(WRITE_LLS_INITr(unit, rval)); 6474 6475 /* Wait for LLS init done. */ 6476 if (SAL_BOOT_SIMULATION) { 6477 mmu_init_usec = 10000000; /* Simulation .. 10sec */ 6478 } else { 6479 mmu_init_usec = 50000; 6480 } 6481 soc_timeout_init(&to, mmu_init_usec, 0); 6482 6483 do { 6484 SOC_IF_ERROR_RETURN(READ_LLS_INITr(unit, &rval)); 6485 if (soc_reg_field_get(unit, LLS_INITr, rval, INIT_DONEf)) { 6486 break; 6487 } 6488 if (soc_timeout_check(&to)) { 6489 LOG_WARN(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 6490 "LLS INIT timeout\n"))); 6491 break; 6492 } 6493 } while (TRUE); 6494 6495 /* Enable all ports */ 6496 rval = 0xFFFFFFFF; 6497 COMPILER_64_ZERO(rval1); 6498 COMPILER_64_SET(rval1, 0, rval); 6499 soc_reg_field_set(unit, INPUT_PORT_RX_ENABLE_64r, &rval, 6500 INPUT_PORT_RX_ENABLEf, 0x3FFFFFFF); 6501 SOC_IF_ERROR_RETURN(WRITE_INPUT_PORT_RX_ENABLE_64r(unit, rval1)); 6502 6503 SOC_IF_ERROR_RETURN(WRITE_THDIQEN_INPUT_PORT_RX_ENABLE_64r(unit, rval1)); 6504 SOC_IF_ERROR_RETURN(WRITE_THDIRQE_INPUT_PORT_RX_ENABLE_64r(unit, rval1)); 6505 6506 SOC_IF_ERROR_RETURN(WRITE_THDI_BYPASSr(unit, 0)); 6507 SOC_IF_ERROR_RETURN(WRITE_THDIQEN_THDI_BYPASSr(unit, 0)); 6508 SOC_IF_ERROR_RETURN(WRITE_THDIRQE_THDI_BYPASSr(unit, 0)); 6509 SOC_IF_ERROR_RETURN(WRITE_THDO_BYPASSr(unit, 0)); 6510 6511 6512 /* Setup TDM for MMU Arb & LLS */ 6513 SOC_IF_ERROR_RETURN(_soc_metrolite_mmu_tdm_init(unit)); 6514 6515 /* Config DEQ_EFIFO_CFG and TOQ_PORT_BW_CTRL */ 6516 /* SOC_IF_ERROR_RETURN(_soc_metrolite_mmu_port_init(unit)); */ 6517 6518 /* Enable LLS */ 6519 rval = 0; 6520 soc_reg_field_set(unit, LLS_CONFIG0r, &rval, DEQUEUE_ENABLEf, 1); 6521 soc_reg_field_set(unit, LLS_CONFIG0r, &rval, ENQUEUE_ENABLEf, 1); 6522 soc_reg_field_set(unit, LLS_CONFIG0r, &rval, FC_ENABLEf, 1); 6523 soc_reg_field_set(unit, LLS_CONFIG0r, &rval, MIN_ENABLEf, 1); 6524 soc_reg_field_set(unit, LLS_CONFIG0r, &rval, PORT_SCHEDULER_ENABLEf, 1); 6525 soc_reg_field_set(unit, LLS_CONFIG0r, &rval, SHAPER_ENABLEf, 1); 6526 if (SOC_REG_FIELD_VALID(unit, LLS_CONFIG0r, SPRI_VECT_MODE_ENABLEf)) { 6527 if (soc_feature(unit, soc_feature_vector_based_spri)) { 6528 soc_reg_field_set(unit, LLS_CONFIG0r, &rval, 6529 SPRI_VECT_MODE_ENABLEf, 1); 6530 } 6531 } 6532 SOC_IF_ERROR_RETURN(WRITE_LLS_CONFIG0r(unit, rval)); 6533 6534 /* Enable shaper background refresh */ 6535 rval = 0; 6536 soc_reg_field_set(unit, LLS_MAX_REFRESH_ENABLEr, &rval, L0_MAX_REFRESH_ENABLEf, 1); 6537 soc_reg_field_set(unit, LLS_MAX_REFRESH_ENABLEr, &rval, L1_MAX_REFRESH_ENABLEf, 1); 6538 soc_reg_field_set(unit, LLS_MAX_REFRESH_ENABLEr, &rval, L2_MAX_REFRESH_ENABLEf, 1); 6539 soc_reg_field_set(unit, LLS_MAX_REFRESH_ENABLEr, &rval, PORT_MAX_REFRESH_ENABLEf, 1); 6540 soc_reg_field_set(unit, LLS_MAX_REFRESH_ENABLEr, &rval, S1_MAX_REFRESH_ENABLEf, 1); 6541 SOC_IF_ERROR_RETURN(WRITE_LLS_MAX_REFRESH_ENABLEr(unit, rval)); 6542 6543 rval = 0; 6544 soc_reg_field_set(unit, LLS_MIN_REFRESH_ENABLEr, &rval, L0_MIN_REFRESH_ENABLEf, 1); 6545 soc_reg_field_set(unit, LLS_MIN_REFRESH_ENABLEr, &rval, L1_MIN_REFRESH_ENABLEf, 1); 6546 soc_reg_field_set(unit, LLS_MIN_REFRESH_ENABLEr, &rval, L2_MIN_REFRESH_ENABLEf, 1); 6547 SOC_IF_ERROR_RETURN(WRITE_LLS_MIN_REFRESH_ENABLEr(unit, rval)); 6548 6549 /* RQE configuration */ 6550 rval = 0; 6551 soc_reg_field_set(unit, RQE_SCHEDULER_CONFIGr, &rval, 6552 L0_MCM_MODEf, 1); 6553 soc_reg_field_set(unit, RQE_SCHEDULER_CONFIGr, &rval, 6554 L0_CC_MODEf, 1); 6555 soc_reg_field_set(unit, RQE_SCHEDULER_CONFIGr, &rval, 6556 L0_UCM_MODEf, 1); 6557 soc_reg_field_set(unit, RQE_SCHEDULER_CONFIGr, &rval, 6558 L1_MODEf, 1); 6559 SOC_IF_ERROR_RETURN(WRITE_RQE_SCHEDULER_CONFIGr(unit, rval)); 6560 6561 rval = 0; 6562 soc_reg_field_set(unit, RQE_SCHEDULER_WEIGHT_L0_QUEUEr, &rval, 6563 WRR_WEIGHTf, 1); 6564 for(i=0; i<SOC_REG_NUMELS(unit, RQE_SCHEDULER_WEIGHT_L0_QUEUEr); i++) { 6565 SOC_IF_ERROR_RETURN(WRITE_RQE_SCHEDULER_WEIGHT_L0_QUEUEr(unit, i, 6566 rval)); 6567 } 6568 6569 rval = 0; 6570 soc_reg_field_set(unit, RQE_SCHEDULER_WEIGHT_L1_QUEUEr, &rval, 6571 WRR_WEIGHTf, 1); 6572 for(i=0; i<SOC_REG_NUMELS(unit, RQE_SCHEDULER_WEIGHT_L1_QUEUEr); i++) { 6573 SOC_IF_ERROR_RETURN(WRITE_RQE_SCHEDULER_WEIGHT_L1_QUEUEr(unit, i, 6574 rval)); 6575 } 6576 6577 SOC_IF_ERROR_RETURN(READ_WRED_PARITY_ERROR_MASKr(unit, &rval)); 6578 soc_reg_field_set(unit, WRED_PARITY_ERROR_MASKr, &rval, UPDATE_INTRPT_MASKf, 0); 6579 SOC_IF_ERROR_RETURN(WRITE_WRED_PARITY_ERROR_MASKr(unit, rval)); 6580 6581 SOC_IF_ERROR_RETURN(READ_MISCCONFIGr(unit, &rval)); 6582 soc_reg_field_set(unit, MISCCONFIGr, &rval, REFRESH_ENf, 1); 6583 SOC_IF_ERROR_RETURN(WRITE_MISCCONFIGr(unit, rval)); 6584 6585 SOC_IF_ERROR_RETURN(soc_saber2_perq_flex_counters_init(unit,0)); 6586 6587 rval = 0xffffffff; /* PRIx_GRP = 0x7 */ 6588 6589 /* Configuring all profile 0 to use all the priority groups 0 to 7 */ 6590 6591 SOC_IF_ERROR_RETURN(WRITE_MMU_ENQ_PROFILE_0_PRI_GRP0r(unit, rval)); 6592 SOC_IF_ERROR_RETURN(WRITE_MMU_ENQ_PROFILE_0_PRI_GRP1r(unit, rval)); 6593 6594 SOC_IF_ERROR_RETURN(WRITE_PROFILE0_PRI_GRP0r(unit, rval)); 6595 SOC_IF_ERROR_RETURN(WRITE_PROFILE0_PRI_GRP1r(unit, rval)); 6596 6597 SOC_IF_ERROR_RETURN(WRITE_THDIRQE_PROFILE0_PRI_GRP0r(unit, rval)); 6598 SOC_IF_ERROR_RETURN(WRITE_THDIRQE_PROFILE0_PRI_GRP1r(unit, rval)); 6599 6600 SOC_IF_ERROR_RETURN(WRITE_THDIQEN_PROFILE0_PRI_GRP0r(unit, rval)); 6601 SOC_IF_ERROR_RETURN(WRITE_THDIQEN_PROFILE0_PRI_GRP1r(unit, rval)); 6602 6603 COMPILER_64_ZERO(rval1); 6604 6605 6606 SOC_IF_ERROR_RETURN(WRITE_MMU_ENQ_IP_PRI_TO_PG_PROFILE_0r(unit, rval1)); 6607 /* Using the same rval1 for setting the remaining registers */ 6608 SOC_IF_ERROR_RETURN(WRITE_PORT_PROFILE_MAPr(unit, rval1)); 6609 SOC_IF_ERROR_RETURN(WRITE_THDIRQE_PORT_PROFILE_MAPr(unit, rval1)); 6610 SOC_IF_ERROR_RETURN(WRITE_THDIQEN_PORT_PROFILE_MAPr(unit, rval1)); 6611 6612 rval = 0; 6613 SOC_IF_ERROR_RETURN(WRITE_BUFFER_CELL_LIMIT_SP_SHAREDr(unit,0)); 6614 SOC_IF_ERROR_RETURN(WRITE_THDIRQE_BUFFER_CELL_LIMIT_SP_SHAREDr(unit,0)); 6615 SOC_IF_ERROR_RETURN(WRITE_THDIQEN_BUFFER_CELL_LIMIT_SP_SHAREDr(unit,0)); 6616 6617 /* Input port per-device global headroom */ 6618 rval = 0; 6619 SOC_IF_ERROR_RETURN(READ_THDO_MISCCONFIGr(unit, &rval)); 6620 soc_reg_field_set(unit, THDO_MISCCONFIGr, &rval, STAT_CLEARf, 0); 6621 soc_reg_field_set(unit, THDO_MISCCONFIGr, &rval, PARITY_CHK_ENf, 1); 6622 soc_reg_field_set(unit, THDO_MISCCONFIGr, &rval, PARITY_GEN_ENf, 1); 6623 SOC_IF_ERROR_RETURN(WRITE_THDO_MISCCONFIGr(unit, rval)); 6624 6625 SOC_IF_ERROR_RETURN(READ_OP_THR_CONFIGr(unit, &rval)); 6626 soc_reg_field_set(unit, OP_THR_CONFIGr, &rval, EARLY_E2E_SELECTf, 0); 6627 SOC_IF_ERROR_RETURN(WRITE_OP_THR_CONFIGr(unit, rval)); 6628 6629 SOC_IF_ERROR_RETURN(_soc_ml_mmu_init_helper(unit, -1)); 6630 6631 /* Initialize MMU internal/external aging limit memory */ 6632 count = soc_mem_index_count(unit, MMU_AGING_LMT_INTm); 6633 sal_memset(&age_entry, 0, sizeof(mmu_aging_lmt_int_entry_t)); 6634 for (i=0; i < count; i++) { 6635 SOC_IF_ERROR_RETURN(WRITE_MMU_AGING_LMT_INTm(unit, 6636 MEM_BLOCK_ANY, i, &age_entry)); 6637 } 6638 if (!SOC_WARM_BOOT(unit)) { 6639 SOC_IF_ERROR_RETURN(_soc_ml_mmu_set_invalid_parent(unit)); 6640 } 6641 SOC_IF_ERROR_RETURN(_soc_ml_post_mmu_init(unit)); 6642 6643 rval = 0; 6644 soc_reg_field_set(unit, MMU_ENQ_RQE_QUEUE_SELECT_0r, &rval, RQE_QUEUE_PRI_0f, 0); 6645 soc_reg_field_set(unit, MMU_ENQ_RQE_QUEUE_SELECT_0r, &rval, RQE_QUEUE_PRI_1f, 1); 6646 soc_reg_field_set(unit, MMU_ENQ_RQE_QUEUE_SELECT_0r, &rval, RQE_QUEUE_PRI_2f, 2); 6647 soc_reg_field_set(unit, MMU_ENQ_RQE_QUEUE_SELECT_0r, &rval, RQE_QUEUE_PRI_3f, 3); 6648 soc_reg_field_set(unit, MMU_ENQ_RQE_QUEUE_SELECT_0r, &rval, RQE_QUEUE_PRI_4f, 4); 6649 soc_reg_field_set(unit, MMU_ENQ_RQE_QUEUE_SELECT_0r, &rval, RQE_QUEUE_PRI_5f, 5); 6650 soc_reg_field_set(unit, MMU_ENQ_RQE_QUEUE_SELECT_0r, &rval, RQE_QUEUE_PRI_6f, 6); 6651 soc_reg_field_set(unit, MMU_ENQ_RQE_QUEUE_SELECT_0r, &rval, RQE_QUEUE_PRI_7f, 7); 6652 SOC_IF_ERROR_RETURN(WRITE_MMU_ENQ_RQE_QUEUE_SELECT_0r(unit, rval)); 6653 6654 6655 rval = 0; 6656 soc_reg_field_set(unit, MMU_ENQ_RQE_QUEUE_SELECT_1r, &rval, RQE_QUEUE_PRI_8f, 7); 6657 soc_reg_field_set(unit, MMU_ENQ_RQE_QUEUE_SELECT_1r, &rval, RQE_QUEUE_PRI_9f, 7); 6658 soc_reg_field_set(unit, MMU_ENQ_RQE_QUEUE_SELECT_1r, &rval, RQE_QUEUE_PRI_10f, 7); 6659 soc_reg_field_set(unit, MMU_ENQ_RQE_QUEUE_SELECT_1r, &rval, RQE_QUEUE_PRI_11f, 7); 6660 soc_reg_field_set(unit, MMU_ENQ_RQE_QUEUE_SELECT_1r, &rval, RQE_QUEUE_PRI_12f, 7); 6661 soc_reg_field_set(unit, MMU_ENQ_RQE_QUEUE_SELECT_1r, &rval, RQE_QUEUE_PRI_13f, 7); 6662 soc_reg_field_set(unit, MMU_ENQ_RQE_QUEUE_SELECT_1r, &rval, RQE_QUEUE_PRI_14f, 7); 6663 soc_reg_field_set(unit, MMU_ENQ_RQE_QUEUE_SELECT_1r, &rval, RQE_QUEUE_PRI_15f, 7); 6664 SOC_IF_ERROR_RETURN(WRITE_MMU_ENQ_RQE_QUEUE_SELECT_1r(unit, rval)); 6665 6666 return SOC_E_NONE; 6667 } 6668 6669 STATIC int 6670 _soc_metrolite_age_timer_get(int unit, int *age_seconds, int *enabled) 6671 { 6672 uint32 rval; 6673 6674 SOC_IF_ERROR_RETURN(READ_L2_AGE_TIMERr(unit, &rval)); 6675 *enabled = soc_reg_field_get(unit, L2_AGE_TIMERr, rval, AGE_ENAf); 6676 *age_seconds = soc_reg_field_get(unit, L2_AGE_TIMERr, rval, AGE_VALf); 6677 6678 return SOC_E_NONE; 6679 } 6680 6681 STATIC int 6682 _soc_metrolite_age_timer_max_get(int unit, int *max_seconds) 6683 { 6684 *max_seconds = 6685 soc_reg_field_get(unit, L2_AGE_TIMERr, 0xffffffff, AGE_VALf); 6686 6687 return SOC_E_NONE; 6688 } 6689 6690 STATIC int 6691 _soc_metrolite_age_timer_set(int unit, int age_seconds, int enable) 6692 { 6693 uint32 rval; 6694 6695 rval = 0; 6696 soc_reg_field_set(unit, L2_AGE_TIMERr, &rval, AGE_ENAf, enable); 6697 soc_reg_field_set(unit, L2_AGE_TIMERr, &rval, AGE_VALf, age_seconds); 6698 SOC_IF_ERROR_RETURN(WRITE_L2_AGE_TIMERr(unit, rval)); 6699 6700 return SOC_E_NONE; 6701 } 6702 6703 int ml_linkphy_port[1][4] = { 6704 {1, 2, 3, 4} /* {T,R}XLP0 */ 6705 }; 6706 6707 int 6708 soc_ml_linkphy_port_reg_blk_idx_get( 6709 int unit, int port, int blktype, int *block, int *index) 6710 { 6711 int i,j; 6712 int blk = -1; 6713 int idx = -1; 6714 6715 for (i=0; i<1; i++) { 6716 for(j=0; j<4; j++) { 6717 if(port == ml_linkphy_port[i][j]) { 6718 blk = i; 6719 idx = j; 6720 break; 6721 } 6722 } 6723 } 6724 6725 if (blktype == SOC_BLK_TXLP) { 6726 if (blk == 0) { 6727 blk = TXLP0_BLOCK(unit); 6728 } 6729 } else if (blktype == SOC_BLK_RXLP) { 6730 if (blk == 0) { 6731 blk = RXLP0_BLOCK(unit); 6732 } 6733 } else { 6734 return SOC_E_PARAM; 6735 } 6736 6737 if (block != NULL) { 6738 *block = blk; 6739 } 6740 if (index != NULL) { 6741 *index = idx; 6742 } 6743 if ((blk == -1) || (idx == -1)) { 6744 return SOC_E_NOT_FOUND; 6745 } 6746 return SOC_E_NONE; 6747 } 6748 6749 int 6750 soc_ml_linkphy_port_blk_idx_get( 6751 int unit, int port, int *block, int *index) 6752 { 6753 int i,j; 6754 int blk = -1; 6755 int idx = -1; 6756 6757 for (i=0; i<1; i++) { 6758 for(j=0; j<4; j++) { 6759 if(port == ml_linkphy_port[i][j]) { 6760 blk = i; 6761 idx = j; 6762 break; 6763 } 6764 } 6765 } 6766 6767 if (block != NULL) { 6768 *block = blk; 6769 } 6770 if (index != NULL) { 6771 *index = idx; 6772 } 6773 if ((blk == -1) || (idx == -1)) { 6774 return SOC_E_NOT_FOUND; 6775 } 6776 return SOC_E_NONE; 6777 } 6778 6779 int soc_ml_linkphy_get_portid(int unit, int block, int index) { 6780 if (index > 3) { 6781 return -1; 6782 } 6783 if ((block == TXLP0_BLOCK(unit)) || (block == RXLP0_BLOCK(unit))) { 6784 return ml_linkphy_port[0][index]; 6785 } 6786 return -1; 6787 } 6788 int 6789 soc_ml_pp_port_get_port(int unit, soc_port_t pp_port) 6790 { 6791 int port; 6792 soc_info_t *si; 6793 si = &SOC_INFO(unit); 6794 6795 if (!_SOC_IS_PP_PORT_LINKPHY_SUBTAG(unit, pp_port)) { 6796 return -1; 6797 } 6798 6799 for (port = 1; port < si->cpu_hg_index; port++) { 6800 if (SOC_PBMP_MEMBER(SOC_PORT_PP_BITMAP(unit, port), pp_port)) { 6801 return port; 6802 } 6803 } 6804 6805 return -1; 6806 } 6807 6808 /* 6809 * cpu port (mmu port 0): 48 queues (0-47) 6810 * loopback port (48-71) 6811 * hg ports : 24 queues 6812 * other ports : 8 queues 6813 */ 6814 6815 int 6816 soc_metrolite_num_cosq_init(int unit) 6817 { 6818 soc_info_t *si; 6819 int port; 6820 int numq = 0, i; 6821 int pp_port_cos; 6822 int prev_port_base = 0; 6823 soc_pbmp_t subport_pbmp; 6824 int num_uc_cosq = 0, total_used_queue = 0; 6825 6826 si = &SOC_INFO(unit); 6827 SOC_PBMP_CLEAR(subport_pbmp); 6828 6829 /* For CPU port it is hardcoded to zero as base queue */ 6830 si->port_cosq_base[si->cmic_port] = 0; 6831 si->port_uc_cosq_base[si->cmic_port] = 0; 6832 si->port_num_uc_cosq[si->cmic_port] = NUM_CPU_COSQ(unit); 6833 si->port_num_ext_cosq[si->cmic_port] = 0; 6834 total_used_queue += si->port_num_uc_cosq[si->cmic_port]; 6835 6836 /* For Loopback port it is hardcoded as 48 as a base queue*/ 6837 si->port_cosq_base[si->lb_port] = 48; 6838 si->port_uc_cosq_base[si->lb_port] = 48; 6839 si->port_num_uc_cosq[si->lb_port] = 24; 6840 total_used_queue += si->port_num_uc_cosq[si->lb_port]; 6841 6842 /* first front panel port needs to start with 72 */ 6843 numq = 72; 6844 prev_port_base = si->port_uc_cosq_base[si->cmic_port]; 6845 6846 for (port = si->cmic_port + 1 ; port < si->lb_port; port++) { 6847 if (SOC_PBMP_MEMBER(subport_pbmp, port)) { 6848 continue; 6849 } 6850 si->port_num_cosq[port] = 0; 6851 6852 /* For all GE/, XE, HG Ports */ 6853 si->port_uc_cosq_base[port] = prev_port_base + 6854 numq; 6855 si->port_cosq_base[port] = si->port_uc_cosq_base[port]; 6856 prev_port_base = si->port_uc_cosq_base[port]; 6857 6858 if (IS_HG_PORT(unit, port)) { 6859 si->port_num_uc_cosq[port] = 24; 6860 } else { 6861 num_uc_cosq = soc_property_port_get(unit, port, 6862 spn_LLS_NUM_L2UC, 8); /* DEFAULT_NUM_PHYSICAL_QUEUES */ 6863 if (num_uc_cosq < 8) { 6864 num_uc_cosq = 8; 6865 } 6866 si->port_num_uc_cosq[port] = num_uc_cosq; 6867 } 6868 numq = si->port_num_uc_cosq[port]; 6869 6870 /* This need to be validated when testing COE ports */ 6871 pp_port_cos = soc_property_port_get(unit, port, 6872 spn_NUM_SUBPORT_COS, 4); 6873 if (pp_port_cos > si->port_num_uc_cosq[port]) { 6874 si->port_num_uc_cosq[port] = pp_port_cos; 6875 numq = si->port_num_uc_cosq[port]; 6876 } 6877 total_used_queue += si->port_num_uc_cosq[port]; 6878 if (total_used_queue > ML_MMU_MAX_EGRESS_QUEUE) { 6879 LOG_ERROR(BSL_LS_SOC_COMMON, 6880 (BSL_META_U(unit, 6881 "###ATTN:Physical queue assignment" 6882 " for port:%d exceeded" 6883 " max value:%d ###\n INFO: " 6884 "Start queue:%d End Queue %d\n"), 6885 port, ML_MMU_MAX_EGRESS_QUEUE, 6886 si->port_cosq_base[port], 6887 si->port_cosq_base[port] + 6888 si->port_num_uc_cosq[port] - 1)); 6889 6890 return SOC_E_CONFIG; 6891 } 6892 6893 if (si->port_num_subport[port] > 0) { 6894 SOC_PBMP_ITER(SOC_PORT_PP_BITMAP(unit, port), i) { 6895 if (port != i) { 6896 si->port_uc_cosq_base[i] = prev_port_base + numq; 6897 si->port_cosq_base[i] = si->port_uc_cosq_base[i]; 6898 numq += pp_port_cos; 6899 } else { 6900 total_used_queue -= si->port_num_uc_cosq[i]; 6901 } 6902 si->port_num_uc_cosq[i] = pp_port_cos; 6903 SOC_PBMP_PORT_ADD(subport_pbmp, i); 6904 6905 total_used_queue += si->port_num_uc_cosq[i]; 6906 if (total_used_queue > ML_MMU_MAX_EGRESS_QUEUE) { 6907 LOG_ERROR(BSL_LS_SOC_COMMON, 6908 (BSL_META_U(unit, 6909 "###ATTN:Subport queue assignment" 6910 " for port:%d subport: %d exceeded" 6911 " max value: %d ###\n INFO: " 6912 "Start queue: %d End Queue: %d \n"), 6913 port, i, ML_MMU_MAX_EGRESS_QUEUE, 6914 si->port_cosq_base[i], 6915 si->port_cosq_base[i] + 6916 si->port_num_uc_cosq[i] - 1)); 6917 6918 return SOC_E_CONFIG; 6919 } 6920 } 6921 } 6922 LOG_VERBOSE(BSL_LS_SOC_COMMON, 6923 (BSL_META_U(unit, 6924 "\nport num %d cosq_base %d num_cosq %d"), 6925 port, si->port_cosq_base[port], si->port_num_uc_cosq[port])); 6926 } 6927 6928 return SOC_E_NONE; 6929 } 6930 6931 /* soc_ml_mem_config: 6932 * * Over-ride the default table sizes (from regsfile) for any SKUs here 6933 */ 6934 int 6935 soc_ml_mem_config(int unit, int dev_id) 6936 { 6937 int rv = SOC_E_NONE; 6938 int num_ipv6_128b_entries = 0; 6939 int config_v6_entries = 0; 6940 int defip_config = 0; 6941 soc_persist_t *sop = SOC_PERSIST(unit); 6942 6943 /* Modify max index of LLS_L0_PARENT to match number of L0 nodes. */ 6944 sop->memState[LLS_L0_PARENTm].index_max = 63; 6945 6946 /* Modification of table sizes based on OTP bond options */ 6947 if (soc_feature(unit, soc_feature_untethered_otp)) { 6948 6949 if (socBondInfoFeatureL2Entry8k) { 6950 sop->memState[L2Xm].index_max = 8191; 6951 sop->memState[L2_ENTRY_ONLYm].index_max = 8191; 6952 sop->memState[L2_HITDA_ONLYm].index_max = 1023; 6953 sop->memState[L2_HITSA_ONLYm].index_max = 1023; 6954 } else if(socBondInfoFeatureL2Entry32k) { 6955 sop->memState[L2Xm].index_max = 32767; 6956 sop->memState[L2_ENTRY_ONLYm].index_max = 32767; 6957 } else { 6958 sop->memState[L2Xm].index_max = 32767; 6959 sop->memState[L2_ENTRY_ONLYm].index_max = 32767; 6960 } 6961 6962 if (socBondInfoFeatureIpVlanXlate1k) { 6963 sop->memState[VLAN_XLATEm].index_max = 1023; 6964 sop->memState[VLAN_MACm].index_max = 1023; 6965 }else if(socBondInfoFeatureIpVlanXlate4k) { 6966 sop->memState[VLAN_XLATEm].index_max = 4095; 6967 sop->memState[VLAN_MACm].index_max = 4095; 6968 }else { 6969 sop->memState[VLAN_XLATEm].index_max = 4095; 6970 sop->memState[VLAN_MACm].index_max = 4095; 6971 } 6972 6973 if (socBondInfoFeatureMpls1k) { 6974 sop->memState[MPLS_ENTRYm].index_max = 1023; 6975 }else if(socBondInfoFeatureMpls2k) { 6976 sop->memState[MPLS_ENTRYm].index_max = 4095; 6977 }else { 6978 sop->memState[MPLS_ENTRYm].index_max = 4095; 6979 } 6980 6981 if (socBondInfoFeatureL3Entry1k) { 6982 sop->memState[L3_ENTRY_ONLYm].index_max = 1023; 6983 sop->memState[L3_ENTRY_IPV4_UNICASTm].index_max = 1023; 6984 sop->memState[L3_ENTRY_IPV4_MULTICASTm].index_max = 511; 6985 sop->memState[L3_ENTRY_IPV6_UNICASTm].index_max = 511; 6986 sop->memState[L3_ENTRY_IPV6_MULTICASTm].index_max = 255; 6987 } 6988 if (SOC_BOND_INFO_GET(unit, vfp_slice_map) == 0x0) { 6989 sop->memState[VFP_TCAMm].index_max = -1; 6990 } 6991 if (SOC_BOND_INFO_GET(unit, efp_slice_map) == 0x0) { 6992 sop->memState[EFP_TCAMm].index_max = -1; 6993 } 6994 6995 if (socBondInfoFeatureL3NextHop1k) { 6996 sop->memState[ING_L3_NEXT_HOPm].index_max = 1023; 6997 sop->memState[EGR_L3_NEXT_HOPm].index_max = 1023; 6998 sop->memState[INITIAL_ING_L3_NEXT_HOPm].index_max = 1023; 6999 }else if(socBondInfoFeatureL3NextHop2k) { 7000 sop->memState[ING_L3_NEXT_HOPm].index_max = 2047; 7001 sop->memState[EGR_L3_NEXT_HOPm].index_max = 2047; 7002 sop->memState[INITIAL_ING_L3_NEXT_HOPm].index_max = 2047; 7003 }else { 7004 sop->memState[ING_L3_NEXT_HOPm].index_max = 2047; 7005 sop->memState[EGR_L3_NEXT_HOPm].index_max = 2047; 7006 sop->memState[INITIAL_ING_L3_NEXT_HOPm].index_max = 2047; 7007 } 7008 7009 /* L3_DEFIP sizing */ 7010 if (socBondInfoFeatureL3DefIpDisable) { 7011 sop->memState[L3_DEFIP_PAIR_128m].index_max = -1; 7012 sop->memState[L3_DEFIP_PAIR_128_ONLYm].index_max = -1; 7013 sop->memState[L3_DEFIP_PAIR_128_DATA_ONLYm].index_max = -1; 7014 sop->memState[L3_DEFIP_PAIR_128_HIT_ONLYm].index_max = -1; 7015 sop->memState[L3_DEFIPm].index_max = -1; 7016 sop->memState[L3_DEFIP_ONLYm].index_max = -1; 7017 sop->memState[L3_DEFIP_DATA_ONLYm].index_max = -1 ; 7018 sop->memState[L3_DEFIP_HIT_ONLYm].index_max = -1 ; 7019 SOC_CONTROL(unit)->l3_defip_index_remap = -1 ; 7020 }else { 7021 SOC_CONTROL(unit)->l3_defip_max_tcams = _SOC_ML_DEFIP_MAX_TCAMS; 7022 SOC_CONTROL(unit)->l3_defip_tcam_size = _SOC_ML_DEFIP_TCAM_DEPTH; 7023 if (soc_property_get(unit, "l3_defip_sizing", TRUE)) { 7024 defip_config = soc_property_get(unit, spn_IPV6_LPM_128B_ENABLE, 1); 7025 7026 num_ipv6_128b_entries = 7027 soc_property_get(unit, spn_NUM_IPV6_LPM_128B_ENTRIES, 7028 (defip_config ? 256 : 0)); 7029 7030 config_v6_entries = num_ipv6_128b_entries; 7031 7032 if (soc_property_get(unit, spn_LPM_SCALING_ENABLE, 0)) { 7033 num_ipv6_128b_entries = 0; 7034 if (!soc_property_get(unit, spn_LPM_IPV6_128B_RESERVED, 1)) { 7035 config_v6_entries = SOC_CONTROL(unit)->l3_defip_tcam_size * 7036 ((config_v6_entries / 7037 SOC_CONTROL(unit)->l3_defip_tcam_size) + 7038 ((config_v6_entries % 7039 SOC_CONTROL(unit)->l3_defip_tcam_size) ? 1 : 0)); 7040 } 7041 } 7042 7043 sop->memState[L3_DEFIP_PAIR_128m].index_max = 7044 num_ipv6_128b_entries - 1; 7045 sop->memState[L3_DEFIP_PAIR_128_ONLYm].index_max = 7046 num_ipv6_128b_entries - 1; 7047 sop->memState[L3_DEFIP_PAIR_128_DATA_ONLYm].index_max = 7048 num_ipv6_128b_entries - 1; 7049 sop->memState[L3_DEFIP_PAIR_128_HIT_ONLYm].index_max = 7050 num_ipv6_128b_entries - 1; 7051 sop->memState[L3_DEFIPm].index_max = 7052 (SOC_CONTROL(unit)->l3_defip_max_tcams * 7053 SOC_CONTROL(unit)->l3_defip_tcam_size) - 7054 (num_ipv6_128b_entries * 2) - 1; 7055 sop->memState[L3_DEFIP_ONLYm].index_max = 7056 sop->memState[L3_DEFIPm].index_max; 7057 sop->memState[L3_DEFIP_DATA_ONLYm].index_max = 7058 sop->memState[L3_DEFIPm].index_max; 7059 sop->memState[L3_DEFIP_HIT_ONLYm].index_max = 7060 sop->memState[L3_DEFIPm].index_max; 7061 SOC_CONTROL(unit)->l3_defip_index_remap = num_ipv6_128b_entries; 7062 soc_l3_defip_indexes_init(unit, config_v6_entries); 7063 } 7064 } 7065 }else { 7066 /* L3_DEFIP sizing */ 7067 SOC_CONTROL(unit)->l3_defip_max_tcams = _SOC_ML_DEFIP_MAX_TCAMS; 7068 SOC_CONTROL(unit)->l3_defip_tcam_size = _SOC_ML_DEFIP_TCAM_DEPTH; 7069 if (soc_property_get(unit, "l3_defip_sizing", TRUE)) { 7070 defip_config = soc_property_get(unit, spn_IPV6_LPM_128B_ENABLE, 1); 7071 7072 num_ipv6_128b_entries = 7073 soc_property_get(unit, spn_NUM_IPV6_LPM_128B_ENTRIES, 7074 (defip_config ? 256 : 0)); 7075 7076 config_v6_entries = num_ipv6_128b_entries; 7077 7078 if (soc_property_get(unit, spn_LPM_SCALING_ENABLE, 0)) { 7079 num_ipv6_128b_entries = 0; 7080 if (!soc_property_get(unit, spn_LPM_IPV6_128B_RESERVED, 1)) { 7081 config_v6_entries = SOC_CONTROL(unit)->l3_defip_tcam_size * 7082 ((config_v6_entries / 7083 SOC_CONTROL(unit)->l3_defip_tcam_size) + 7084 ((config_v6_entries % 7085 SOC_CONTROL(unit)->l3_defip_tcam_size) ? 1 : 0)); 7086 } 7087 } 7088 7089 sop->memState[L3_DEFIP_PAIR_128m].index_max = 7090 num_ipv6_128b_entries - 1; 7091 sop->memState[L3_DEFIP_PAIR_128_ONLYm].index_max = 7092 num_ipv6_128b_entries - 1; 7093 sop->memState[L3_DEFIP_PAIR_128_DATA_ONLYm].index_max = 7094 num_ipv6_128b_entries - 1; 7095 sop->memState[L3_DEFIP_PAIR_128_HIT_ONLYm].index_max = 7096 num_ipv6_128b_entries - 1; 7097 sop->memState[L3_DEFIPm].index_max = 7098 (SOC_CONTROL(unit)->l3_defip_max_tcams * 7099 SOC_CONTROL(unit)->l3_defip_tcam_size) - 7100 (num_ipv6_128b_entries * 2) - 1; 7101 sop->memState[L3_DEFIP_ONLYm].index_max = 7102 sop->memState[L3_DEFIPm].index_max; 7103 sop->memState[L3_DEFIP_DATA_ONLYm].index_max = 7104 sop->memState[L3_DEFIPm].index_max; 7105 sop->memState[L3_DEFIP_HIT_ONLYm].index_max = 7106 sop->memState[L3_DEFIPm].index_max; 7107 SOC_CONTROL(unit)->l3_defip_index_remap = num_ipv6_128b_entries; 7108 soc_l3_defip_indexes_init(unit, config_v6_entries); 7109 } 7110 } 7111 return rv; 7112 } 7113 7114 7115 int 7116 _soc_metrolite_sbus_tsc_block(int unit, 7117 int phy_port, soc_mem_t wc_ucmem_data, int *block) 7118 { 7119 int i,port_num_blktype = 0, tmp_blk=0; 7120 7121 *block= -1; 7122 port_num_blktype = SOC_DRIVER(unit)->port_num_blktype; 7123 for (i = 0; i < port_num_blktype; i++){ 7124 tmp_blk = SOC_PORT_IDX_BLOCK(unit, phy_port, i); 7125 if (SOC_MEM_BLOCK_VALID(unit, wc_ucmem_data, tmp_blk)) { 7126 *block = tmp_blk; 7127 break; 7128 } 7129 } 7130 7131 if (*block == -1){ 7132 LOG_WARN(BSL_LS_SOC_COMMON, 7133 (BSL_META_U(unit, 7134 "_soc_metrolite_sbus_tsc_block(u=%d,pp=%d,mem=%d, blk=%d): " 7135 "no valid block for TSC SBUS interface!\n"), 7136 unit, phy_port, wc_ucmem_data, *block)); 7137 return SOC_E_INTERNAL; 7138 } 7139 7140 return SOC_E_NONE; 7141 } 7142 /* PHY_REG address decode : 7143 * - TSC_ADDR[31:0]={DEVICE(ADVAD)[31:27],??[26:24],TSC_ID(PHYAD)[23:19], 7144 * PORT_MODE(LANE)[18:16], IEEE_BIT[15], BLOCK[14:4], REG[3:0]} 7145 * - QSGMII_ADDR[31:0]={DEVICE(ADVAD)[31:27], LANE[26:16], REG_HI[15], 7146 * BLOCK[14:4], REG_LO[3:0]}} 7147 */ 7148 7149 #define PHY_REG_ADDR_DEVAD(_phy_reg) (((_phy_reg) >> 27) & 0x1f) 7150 #define TSC_REG_ADDR_TSCID(_phy_reg) (((_phy_reg) >> 19) & 0x1f) 7151 #define TSC_REG_ADDR_PORTMODE(_phy_reg) (((_phy_reg) >> 16) & 0x7) 7152 #define QSGMII_REG_ADDR_LANE(_phy_reg) (((_phy_reg) >> 16) & 0x7ff) 7153 #define PHY_REG_ADDR_BLOCK(_phy_reg) (((_phy_reg) >> 4) & 0xfff) 7154 #define TSC_REG_ADDR_REG(_phy_reg) ((_phy_reg) & 0xf) 7155 #define QSGMII_REG_ADDR_REG(_phy_reg) ((((_phy_reg) & 0x8000) >> 11) | \ 7156 ((_phy_reg) & 0xf)) 7157 7158 #define IS_QSGMII_REGISTER(_phy_reg) (((_phy_reg) & 0xf800f000) == 0x8000) 7159 #define TSC_REG_ADDR_TSCID_SET(_phy_reg, _phyad) \ 7160 ((_phy_reg) |= ((_phyad) & 0x1f) << 19) 7161 #define QSGMII_REG_ADDR_LANE_SET(_phy_reg_new, _phy_reg) \ 7162 ((_phy_reg_new) |= ((_phy_reg) & 0x7ff0000)) 7163 #define SABER2_PORT_IS_QSGMII(_unit, _port) \ 7164 (IS_GE_PORT((_unit), (_port)) && !IS_XL_PORT((_unit), (_port))) 7165 7166 7167 7168 /* Function to return the speed based on the cfg_num */ 7169 int soc_metrolite_xl_port_speed_get(int unit, int port, int *speed) { 7170 int cfg_num=0, max_speed=0; 7171 soc_pbmp_t my_pbmp_xport_xe; 7172 soc_info_t *si=&SOC_INFO(unit); 7173 7174 SOC_PBMP_CLEAR(my_pbmp_xport_xe); 7175 my_pbmp_xport_xe = soc_property_get_pbmp_default(unit, spn_PBMP_XPORT_XE, 7176 my_pbmp_xport_xe); 7177 7178 SOC_IF_ERROR_RETURN(_soc_metrolite_get_cfg_num(unit, 0, &cfg_num)); 7179 max_speed = bcm56270_speed[unit][cfg_num][port-1]; 7180 7181 if (max_speed > si->port_speed_max[port]) { 7182 *speed = si->port_speed_max[port]; 7183 if (si->port_speed_max[port] == 0) { 7184 /* port_speed_max cannot be 0 for a valid port. 7185 * During warmboot sync, the port must have been merged. 7186 * Now after upgrade, the port_speed_max would be 0. 7187 * So return max speed. 7188 */ 7189 *speed = max_speed; 7190 } 7191 } else if ((max_speed == 10000) && !(SOC_PBMP_MEMBER(my_pbmp_xport_xe, port))) { 7192 *speed = 11000; 7193 } else { 7194 *speed = (max_speed > si->port_speed_max[port]) ? max_speed : 7195 si->port_speed_max[port]; 7196 } 7197 7198 return SOC_E_NONE; 7199 } 7200 7201 int 7202 soc_metrolite_global_param_reconfigure(int unit) 7203 { 7204 uint16 dev_id = 0; 7205 uint8 rev_id = 0; 7206 int cfg_num = -1; 7207 int max_cfg_num = 0; 7208 int def_cfg_num = 0; 7209 int offset_cfg_num = 0; 7210 int int_cfg_num = 0; 7211 7212 /* Retreive system dev and revision identifier */ 7213 soc_cm_get_id(unit, &dev_id, &rev_id); 7214 7215 cfg_num = soc_property_get(unit, spn_BCM5627X_CONFIG,0xFF); 7216 7217 switch(dev_id) { 7218 case BCM56270_DEVICE_ID: 7219 def_cfg_num = BCM56270_DEVICE_ID_DEFAULT_CFG; 7220 offset_cfg_num = BCM56270_DEVICE_ID_OFFSET_CFG; 7221 max_cfg_num = BCM56270_DEVICE_ID_MAX_CFG; 7222 break; 7223 case BCM56271_DEVICE_ID: 7224 def_cfg_num = BCM56271_DEVICE_ID_DEFAULT_CFG; 7225 offset_cfg_num = BCM56271_DEVICE_ID_OFFSET_CFG; 7226 max_cfg_num = BCM56271_DEVICE_ID_MAX_CFG; 7227 break; 7228 case BCM56272_DEVICE_ID: 7229 def_cfg_num = BCM56272_DEVICE_ID_DEFAULT_CFG; 7230 offset_cfg_num = BCM56272_DEVICE_ID_OFFSET_CFG; 7231 max_cfg_num = BCM56272_DEVICE_ID_MAX_CFG; 7232 break; 7233 case BCM53460_DEVICE_ID: 7234 def_cfg_num = BCM56270_DEVICE_ID_DEFAULT_CFG; 7235 offset_cfg_num = BCM56270_DEVICE_ID_OFFSET_CFG; 7236 max_cfg_num = BCM56270_DEVICE_ID_MAX_CFG; 7237 break; 7238 case BCM53461_DEVICE_ID: 7239 def_cfg_num = BCM56271_DEVICE_ID_DEFAULT_CFG; 7240 offset_cfg_num = BCM56271_DEVICE_ID_OFFSET_CFG; 7241 max_cfg_num = BCM56271_DEVICE_ID_DEFAULT_CFG; 7242 break; 7243 default : 7244 /* Not supported yet */ 7245 return SOC_E_UNAVAIL; 7246 } 7247 7248 if (cfg_num == 0xFF) { 7249 int_cfg_num = def_cfg_num; 7250 } else { 7251 if (cfg_num == 0) { 7252 LOG_DEBUG(BSL_LS_SOC_COMMON, (BSL_META_U(unit, "Config=0 is not allowed\n"))); 7253 return SOC_E_PARAM; 7254 } 7255 int_cfg_num = cfg_num + offset_cfg_num; 7256 } 7257 if (int_cfg_num > max_cfg_num) { 7258 LOG_ERROR(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 7259 "Cfg_num:%d Internal cfg_num:%d \n"),cfg_num,int_cfg_num)); 7260 LOG_ERROR(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 7261 "Wrong %s ==> cfg_num:%d DEFAULT:%d START:%d MAX:%d \n"), 7262 spn_BCM5627X_CONFIG, cfg_num, 7263 def_cfg_num-offset_cfg_num,1,max_cfg_num-offset_cfg_num)); 7264 int_cfg_num = def_cfg_num; 7265 return SOC_E_NONE; 7266 } 7267 /* Reconfigure global param based on config */ 7268 switch(int_cfg_num) { 7269 case BCM56270_DEVICE_ID_OFFSET_CFG + 1: 7270 SOC_ML_MAX_LINKPHY_SUBPORTS_PER_PORT = 4; 7271 SOC_ML_MAX_LINKPHY_STREAMS_PER_PORT = 4; 7272 SOC_ML_MAX_LINKPHY_STREAMS_PER_SLICE = 16; 7273 break; 7274 case BCM56271_DEVICE_ID_OFFSET_CFG + 1: 7275 SOC_ML_MAX_LINKPHY_SUBPORTS_PER_PORT = 4; 7276 SOC_ML_MAX_LINKPHY_STREAMS_PER_PORT = 4; 7277 SOC_ML_MAX_LINKPHY_STREAMS_PER_SLICE = 16; 7278 break; 7279 case BCM56271_DEVICE_ID_OFFSET_CFG + 2: 7280 SOC_ML_MAX_LINKPHY_SUBPORTS_PER_PORT = 6; 7281 SOC_ML_MAX_LINKPHY_STREAMS_PER_PORT = 6; 7282 SOC_ML_MAX_LINKPHY_STREAMS_PER_SLICE = 24; 7283 break; 7284 case BCM56271_DEVICE_ID_OFFSET_CFG + 3: 7285 SOC_ML_MAX_LINKPHY_SUBPORTS_PER_PORT = 4; 7286 SOC_ML_MAX_LINKPHY_STREAMS_PER_PORT = 4; 7287 SOC_ML_MAX_LINKPHY_STREAMS_PER_SLICE = 16; 7288 break; 7289 case BCM56272_DEVICE_ID_OFFSET_CFG + 1: 7290 SOC_ML_MAX_LINKPHY_SUBPORTS_PER_PORT = 4; 7291 SOC_ML_MAX_LINKPHY_STREAMS_PER_PORT = 4; 7292 SOC_ML_MAX_LINKPHY_STREAMS_PER_SLICE = 16; 7293 break; 7294 case BCM56272_DEVICE_ID_OFFSET_CFG + 2: 7295 SOC_ML_MAX_LINKPHY_SUBPORTS_PER_PORT = 6; 7296 SOC_ML_MAX_LINKPHY_STREAMS_PER_PORT = 6; 7297 SOC_ML_MAX_LINKPHY_STREAMS_PER_SLICE = 24; 7298 break; 7299 default: 7300 LOG_WARN(BSL_LS_SOC_COMMON, (BSL_META_U(unit,"Invalid cfg_num\n"))); 7301 return SOC_E_FAIL; 7302 } 7303 return SOC_E_NONE; 7304 } 7305 STATIC 7306 int soc_metrolite_is_pp_port_reusable(int unit, int port) 7307 { 7308 int cfg_num = 0, i; 7309 soc_port_details_t *current_ml_port_details, *head; 7310 soc_pbmp_t pbmp_subport, pbmp_linkphy; 7311 7312 pbmp_subport = soc_property_get_pbmp(unit, spn_PBMP_SUBPORT, 0); 7313 pbmp_linkphy = soc_property_get_pbmp(unit, spn_PBMP_LINKPHY, 0); 7314 7315 SOC_IF_ERROR_RETURN(_soc_metrolite_get_cfg_num(unit, 1, &cfg_num)); 7316 7317 current_ml_port_details = sal_alloc( 7318 sizeof(soc_port_details_t) * (ML_MAX_PHYSICAL_PORTS+1), 7319 "ml_block_ports_t"); 7320 if (current_ml_port_details == NULL) { 7321 LOG_DEBUG(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 7322 "INTERNAL: Memory allocation failed for ml_selected_port_details\n"))); 7323 return FALSE; 7324 } 7325 head = current_ml_port_details; 7326 sal_memcpy(current_ml_port_details, 7327 ml_port_details[cfg_num], 7328 sizeof(soc_port_details_t) * (ML_MAX_PHYSICAL_PORTS+1)); 7329 7330 while (current_ml_port_details->start_port_no) { 7331 for (i = current_ml_port_details->start_port_no; 7332 i <= current_ml_port_details->end_port_no; 7333 i = i + current_ml_port_details->port_incr) { 7334 if ((port == i) && (current_ml_port_details->port_speed != 0)) { 7335 /* Check if linkphy or coe is enabled */ 7336 if ((!SOC_PBMP_MEMBER(pbmp_subport, port)) && 7337 (!SOC_PBMP_MEMBER(pbmp_linkphy, port))) { 7338 sal_free(head); 7339 return FALSE; 7340 } 7341 } 7342 } 7343 current_ml_port_details++; 7344 } 7345 sal_free(head); 7346 return TRUE; 7347 } 7348 7349 void 7350 soc_metrolite_pbmp_init(int unit, ml_pbmp_t ml_pbmp, soc_pbmp_t *pbmp_pp_unused) 7351 { 7352 int port; 7353 soc_pbmp_t my_pbmp_xport_xe; 7354 soc_pbmp_t my_pbmp_xport_ge; 7355 uint32 loop_index=0; 7356 int ml_port_details_index=0; 7357 uint8 ml_port_used_flags[14]={0}; 7358 /*int old_num_lanes, num_lanes, port_incr;*/ 7359 uint16 dev_id=0; 7360 uint8 rev_id=0; 7361 int local_cfg=0; 7362 7363 soc_cm_get_id(unit, &dev_id, &rev_id); 7364 7365 /* Unit Specific Allocation */ 7366 if (ml_port_speeds[unit] != NULL) { 7367 sal_free(ml_port_speeds[unit]); 7368 ml_port_speeds[unit] = NULL; 7369 } 7370 ml_port_speeds[unit] = sal_alloc(sizeof(ml_port_speeds_t), 7371 "ml_port_speeds_t"); 7372 if (ml_port_speeds[unit] == NULL) { 7373 LOG_ERROR(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 7374 "Resource issue %s:%d..Couldn't allocate memory=%d \n"), 7375 FUNCTION_NAME(), __LINE__, 7376 (int)sizeof(ml_port_speeds_t))); 7377 return; 7378 } 7379 7380 if (bcm56270_speed[unit] != NULL) { 7381 sal_free(bcm56270_speed[unit]); 7382 bcm56270_speed[unit] = NULL; 7383 } 7384 bcm56270_speed[unit] = sal_alloc(sizeof(ml_speed_t) * 7385 (sizeof(bcm56270_speed_s) / 7386 sizeof(bcm56270_speed_s[0])), 7387 "bcm56270_speed"); 7388 if (bcm56270_speed[unit] == NULL) { 7389 LOG_ERROR(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 7390 "Resource issue %s:%d..Couldn't allocate memory=%d \n"), 7391 FUNCTION_NAME(), __LINE__, 7392 (int)sizeof(mxqspeeds_t))); 7393 return ; 7394 } 7395 7396 for (loop_index = 0 ; 7397 loop_index < sizeof(bcm56270_speed_s ) / 7398 sizeof(bcm56270_speed_s[0]); 7399 loop_index++) { 7400 sal_memcpy(bcm56270_speed[unit][loop_index], 7401 bcm56270_speed_s[loop_index], 7402 sizeof(ml_speed_t)); 7403 } 7404 7405 if (ml_port_to_block[unit] != NULL) { 7406 sal_free(ml_port_to_block[unit]); 7407 ml_port_to_block[unit] = NULL; 7408 } 7409 ml_port_to_block[unit] = sal_alloc(sizeof(ml_port_to_block_s), 7410 "ml_port_to_block_t"); 7411 if (ml_port_to_block[unit] == NULL) { 7412 LOG_ERROR(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 7413 "Resource issue %s:%d..Couldn't allocate memory=%d \n"), 7414 FUNCTION_NAME(), __LINE__, 7415 (int)sizeof(ml_port_to_block))); 7416 return ; 7417 } 7418 sal_memcpy(ml_port_to_block[unit],ml_port_to_block_s, 7419 sizeof(ml_port_to_block_s)); 7420 7421 if (ml_port_to_block_subports[unit] != NULL) { 7422 sal_free(ml_port_to_block_subports[unit]); 7423 ml_port_to_block_subports[unit] = NULL; 7424 } 7425 ml_port_to_block_subports[unit] = 7426 sal_alloc(sizeof(ml_port_to_block_subports_s), 7427 "ml_port_to_block_t"); 7428 if (ml_port_to_block_subports[unit] == NULL) { 7429 LOG_ERROR(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 7430 "Resource issue %s:%d..Couldn't allocate memory=%d \n"), 7431 FUNCTION_NAME(), __LINE__, 7432 (int) sizeof(ml_port_to_block_subports))); 7433 return ; 7434 } 7435 sal_memcpy(ml_port_to_block_subports[unit], 7436 ml_port_to_block_subports_s,sizeof(ml_port_to_block_subports_s)); 7437 7438 if (ml_block_ports[unit] != NULL) { 7439 sal_free(ml_block_ports[unit]); 7440 ml_block_ports[unit] = NULL; 7441 } 7442 ml_block_ports[unit] = sal_alloc(sizeof(ml_block_ports_s), 7443 "ml_block_ports_t"); 7444 if (ml_block_ports[unit] == NULL) { 7445 LOG_ERROR(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 7446 "Resource issue %s:%d..Couldn't allocate memory=%d \n"), 7447 FUNCTION_NAME(), __LINE__, 7448 (int)sizeof(ml_block_ports))); 7449 return ; 7450 } 7451 sal_memcpy(ml_block_ports[unit],ml_block_ports_s, 7452 sizeof(ml_block_ports_s)); 7453 7454 /* Initialize PBMPs */ 7455 SOC_PBMP_CLEAR(*ml_pbmp.pbmp_gport_stack); 7456 SOC_PBMP_CLEAR(*ml_pbmp.pbmp_mxq); 7457 SOC_PBMP_CLEAR(*ml_pbmp.pbmp_mxq1g); 7458 SOC_PBMP_CLEAR(*ml_pbmp.pbmp_mxq2p5g); 7459 SOC_PBMP_CLEAR(*ml_pbmp.pbmp_mxq10g); 7460 SOC_PBMP_CLEAR(*ml_pbmp.pbmp_xport_xe); 7461 SOC_PBMP_CLEAR(*ml_pbmp.pbmp_xport_ge); 7462 SOC_PBMP_CLEAR(*ml_pbmp.pbmp_xl); 7463 SOC_PBMP_CLEAR(*ml_pbmp.pbmp_xl1g); 7464 SOC_PBMP_CLEAR(*ml_pbmp.pbmp_xl2p5g); 7465 SOC_PBMP_CLEAR(*ml_pbmp.pbmp_xl10g); 7466 SOC_PBMP_CLEAR(*ml_pbmp.pbmp_pp); 7467 SOC_PBMP_CLEAR(*ml_pbmp.pbmp_linkphy); 7468 7469 if (_soc_metrolite_get_cfg_num(unit, 0, &ml_port_details_index) != SOC_E_NONE) { 7470 LOG_DEBUG(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 7471 "Retrieved WRONG CFG VALUE =%d\n"), ml_port_details_index)); 7472 return ; 7473 } 7474 7475 if (ml_port_details_index >= (sizeof(ml_port_details)/ 7476 sizeof(ml_port_details[0]))) { 7477 LOG_DEBUG(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 7478 "INTERNAL: WRONG CFG VALUE =%d\n"), ml_port_details_index)); 7479 return ; 7480 } 7481 7482 LOG_DEBUG(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 7483 "Internal Config Number : %d\n"), ml_port_details_index)); 7484 7485 switch(dev_id) { 7486 case BCM56270_DEVICE_ID: 7487 case BCM56271_DEVICE_ID: 7488 case BCM56272_DEVICE_ID: 7489 sal_memcpy(ml_port_speeds[unit], (ml_port_speeds_s[ml_port_details_index]), 7490 sizeof(ml_port_speeds_t)); 7491 break; 7492 7493 default: 7494 sal_memcpy(ml_port_speeds[unit], ml_port_speeds_56270_1, 7495 sizeof(ml_port_speeds_t)); 7496 break; 7497 }; 7498 7499 SOC_PBMP_CLEAR(my_pbmp_xport_xe); 7500 SOC_PBMP_CLEAR(my_pbmp_xport_ge); 7501 my_pbmp_xport_xe = soc_property_get_pbmp_default(unit, spn_PBMP_XPORT_XE, 7502 my_pbmp_xport_xe); 7503 my_pbmp_xport_ge = soc_property_get_pbmp_default(unit, spn_PBMP_XPORT_GE, 7504 my_pbmp_xport_ge); 7505 7506 if (ml_selected_port_details != NULL) { 7507 sal_free(ml_selected_port_details); 7508 ml_selected_port_details = NULL; 7509 sal_free(ml_selected_port_details_orig); 7510 ml_selected_port_details_orig = NULL; 7511 } 7512 7513 /* Note : size of ml_port_details of all configs is same (72 bytes) */ 7514 ml_selected_port_details = sal_alloc( 7515 sizeof(soc_port_details_t) * (ML_MAX_PHYSICAL_PORTS+1), 7516 "ml_block_ports_t"); 7517 7518 ml_selected_port_details_orig = sal_alloc( 7519 sizeof(soc_port_details_t) * (ML_MAX_PHYSICAL_PORTS+1), 7520 "ml_block_ports_t"); 7521 7522 if ((ml_selected_port_details == NULL) || 7523 (ml_selected_port_details_orig == NULL)) { 7524 LOG_DEBUG(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 7525 "INTERNAL: Memory allocation failed for ml_selected_port_details\n"))); 7526 return ; 7527 } 7528 7529 sal_memcpy(ml_selected_port_details, 7530 ml_port_details[ml_port_details_index], 7531 sizeof(soc_port_details_t) * (ML_MAX_PHYSICAL_PORTS+1)); 7532 7533 /* Keep the default config to compare later */ 7534 sal_memcpy(ml_selected_port_details_orig, 7535 ml_port_details[ml_port_details_index], 7536 sizeof(soc_port_details_t) * (ML_MAX_PHYSICAL_PORTS+1)); 7537 7538 /* port group will be implemented later */ 7539 #if 0 7540 if (!(SOC_WARM_BOOT(unit))) { 7541 /* Construct port bitmaps based on portgroup settings */ 7542 /* In case of warmboot, maintain saved settings */ 7543 loop_index=0; 7544 port_incr = 4; 7545 7546 for(port = 1; port <= ML_MAX_PHYSICAL_PORTS; port += port_incr) { 7547 loop_index = (port / 4); 7548 7549 /* Modify only if the port is not disabled by default */ 7550 if (ml_selected_port_details[loop_index].port_speed == 0) { 7551 continue; 7552 } 7553 7554 old_num_lanes = ml_selected_port_details[loop_index].port_incr; 7555 num_lanes = soc_property_port_get(unit, port, spn_PORTGROUP, 0xFF); 7556 7557 if (num_lanes == 0xFF) { 7558 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 7559 "PortGroup not specified; Setting port %d -> num lanes : %d\n"), 7560 port, old_num_lanes)); 7561 num_lanes = old_num_lanes; 7562 } else if(!((num_lanes == 1) || (num_lanes == 2) || (num_lanes == 4))) { 7563 LOG_WARN(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 7564 "Invalid PortGroup config; Setting port %d -> num lanes : %d\n"), 7565 port, num_lanes)); 7566 num_lanes = old_num_lanes; 7567 } 7568 7569 if(old_num_lanes == num_lanes) { 7570 continue; 7571 } 7572 7573 if(port < 5) { 7574 /* Viper ports */ 7575 switch(num_lanes) { 7576 case PORTGROUP_SINGLE_MODE: 7577 if((old_num_lanes == 1) && 7578 (ml_selected_port_details[loop_index].port_speed == 2500 )) { 7579 ml_selected_port_details[loop_index].port_type = XE_PORT; 7580 ml_selected_port_details[loop_index].port_incr = 4; 7581 ml_selected_port_details[loop_index].port_speed = 10000; 7582 } else { 7583 /* 4 lane or 2 lane mode would not have enough bandwidth */ 7584 LOG_WARN(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 7585 "Invalid PortGroup port %d ; BW exceeds Max port speed\n"), port)); 7586 } 7587 break; 7588 case PORTGROUP_DUAL_MODE: 7589 /* Dual lane not supported for viper ports */ 7590 LOG_WARN(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 7591 "Invalid PortGroup port %d ; Dual lane not supported.\n"), port)); 7592 break; 7593 case PORTGROUP_QUAD_MODE: 7594 /* 2->4 cannot be allowed. 1->4 is possible */ 7595 if(old_num_lanes == 2) { 7596 LOG_WARN(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 7597 "Invalid PortGroup config for port %d ; BW exceeds Max port speed\n"), port)); 7598 } else { 7599 ml_selected_port_details[loop_index].port_incr = 1; 7600 ml_selected_port_details[loop_index].port_speed = 2500; 7601 ml_selected_port_details[loop_index].port_type = GE_PORT; 7602 } 7603 break; 7604 default : return; /* Dummy statement */ 7605 } 7606 } else { 7607 /* Eagle ports */ 7608 port_incr = 2; 7609 if ((port == 11) || (port == 12)) { 7610 loop_index += 1; 7611 } 7612 7613 switch(num_lanes) { 7614 case PORTGROUP_SINGLE_MODE: 7615 if(ml_selected_port_details[loop_index].port_type & GE_PORT) { 7616 LOG_WARN(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 7617 "Invalid PortGroup config for port %d ; BW exceeds Max port speed\n"), port)); 7618 } else { 7619 ml_selected_port_details[loop_index].port_type = XE_PORT; 7620 ml_selected_port_details[loop_index].port_speed = 10000; 7621 ml_selected_port_details[loop_index].port_incr = 4; 7622 ml_selected_port_details[loop_index].end_port_no = 28; 7623 ml_selected_port_details[loop_index + 1].port_type = 0; 7624 port_incr = 4; /* All eagle ports are initialized */ 7625 } 7626 break; 7627 case PORTGROUP_DUAL_MODE: 7628 ml_selected_port_details[loop_index].port_type = XE_PORT; 7629 ml_selected_port_details[loop_index].port_speed = 10000; 7630 ml_selected_port_details[loop_index].port_incr = 2; 7631 ml_selected_port_details[loop_index+1].port_type = XE_PORT; 7632 ml_selected_port_details[loop_index+1].port_speed = 10000; 7633 ml_selected_port_details[loop_index+1].port_incr = 2; 7634 port_incr = 4; /* All eagle ports are initialized */ 7635 break; 7636 case PORTGROUP_QUAD_MODE: 7637 /* In Eagle, 1->4 and 2->4 is not allowed */ 7638 LOG_WARN(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 7639 "Invalid PortGroup config for port %d\n"), port)); 7640 break; 7641 default : return; /* Dummy statement */ 7642 } 7643 } 7644 } 7645 } 7646 #endif 7647 7648 /* Fill in pbmps */ 7649 loop_index = 0; 7650 while(ml_selected_port_details[loop_index].port_speed != 0) { 7651 LOG_VERBOSE(BSL_LS_SOC_COMMON, 7652 (BSL_META_U(unit, 7653 "start:%d end:%d incr:%d type:%d speed:%d\n"), 7654 ml_selected_port_details[loop_index].start_port_no, 7655 ml_selected_port_details[loop_index].end_port_no, 7656 ml_selected_port_details[loop_index].port_incr, 7657 ml_selected_port_details[loop_index].port_type, 7658 ml_selected_port_details[loop_index].port_speed)); 7659 7660 for (port = ml_selected_port_details[loop_index].start_port_no; 7661 port <= ml_selected_port_details[loop_index].end_port_no; 7662 port += ml_selected_port_details[loop_index].port_incr) { 7663 7664 /* In 56271 config 2 and 3 port 5 is hidden. Available only as SAT port */ 7665 if(dev_id == BCM56271_DEVICE_ID){ 7666 local_cfg = soc_property_get(unit, spn_BCM5627X_CONFIG,0xFF); 7667 if ((local_cfg > (BCM56271_DEVICE_ID_OFFSET_CFG)) && (local_cfg < BCM56271_DEVICE_ID_MAX_CFG)) { 7668 if((soc_property_get(unit, spn_SAT_ENABLE, 0) == 0) && (port == 5)) { 7669 ml_selected_port_details[loop_index].port_type = 0; 7670 } 7671 } 7672 } 7673 /* In 56272 port 5 is hidden. Available only as SAT port */ 7674 if(dev_id == BCM56272_DEVICE_ID) { 7675 if((soc_property_get(unit, spn_SAT_ENABLE, 0) == 0) && (port == 5)) { 7676 ml_selected_port_details[loop_index].port_type = 0; 7677 } 7678 } 7679 7680 if (ml_selected_port_details[loop_index].port_type == 0) { 7681 break; 7682 } 7683 7684 if ((port >= 1) && (port <= 4)) { 7685 SOC_PBMP_PORT_ADD(*ml_pbmp.pbmp_mxq, port); 7686 } else if (port >= 5) { 7687 SOC_PBMP_PORT_ADD(*ml_pbmp.pbmp_xl, port); 7688 } 7689 7690 if (ml_selected_port_details[loop_index].port_type & GE_PORT) { 7691 SOC_PBMP_PORT_ADD(*ml_pbmp.pbmp_xport_ge, port); 7692 switch(ml_selected_port_details[loop_index].port_speed) { 7693 case 1000: 7694 if ((port >=1) && (port <= 4)) { 7695 SOC_PBMP_PORT_ADD(*ml_pbmp.pbmp_mxq1g, port); 7696 } else { 7697 SOC_PBMP_PORT_ADD(*ml_pbmp.pbmp_xl1g, port); 7698 } 7699 bcm56270_speed[unit][ml_port_details_index][port-1] = 1000; 7700 break; 7701 case 2500: 7702 if ((port >=1) && (port <= 4)) { 7703 SOC_PBMP_PORT_ADD(*ml_pbmp.pbmp_mxq2p5g, port); 7704 } else { 7705 SOC_PBMP_PORT_ADD(*ml_pbmp.pbmp_xl2p5g, port); 7706 } 7707 bcm56270_speed[unit][ml_port_details_index][port-1] = 2500; 7708 break; 7709 default: 7710 break; 7711 } 7712 } else if ((ml_selected_port_details[loop_index].port_type & XE_PORT) || 7713 ((ml_selected_port_details[loop_index].port_type & HG_PORT) && 7714 (SOC_PBMP_MEMBER(my_pbmp_xport_xe, port)))) { 7715 SOC_PBMP_PORT_ADD(*ml_pbmp.pbmp_xport_xe, port); 7716 if ((port >=1) && (port <= 4)) { 7717 SOC_PBMP_PORT_ADD(*ml_pbmp.pbmp_mxq10g, port); 7718 bcm56270_speed[unit][ml_port_details_index][port-1] = 10000; 7719 } else { 7720 if (SOC_PBMP_MEMBER(my_pbmp_xport_ge, port)) { 7721 SOC_PBMP_PORT_ADD(*ml_pbmp.pbmp_xl2p5g, port); 7722 SOC_PBMP_PORT_ADD(*ml_pbmp.pbmp_xport_ge, port); 7723 SOC_PBMP_PORT_REMOVE(*ml_pbmp.pbmp_xport_xe, port); 7724 bcm56270_speed[unit][ml_port_details_index][port-1] = 2500; 7725 } else { 7726 SOC_PBMP_PORT_ADD(*ml_pbmp.pbmp_xl10g, port); 7727 bcm56270_speed[unit][ml_port_details_index][port-1] = 10000; 7728 } 7729 } 7730 } else { 7731 if ((ml_selected_port_details[loop_index].port_type & HG_PORT) && 7732 (SOC_PBMP_MEMBER(my_pbmp_xport_ge, port))){ 7733 SOC_PBMP_PORT_ADD(*ml_pbmp.pbmp_xl2p5g, port); 7734 SOC_PBMP_PORT_ADD(*ml_pbmp.pbmp_xport_ge, port); 7735 SOC_PBMP_PORT_REMOVE(*ml_pbmp.pbmp_xport_xe, port); 7736 bcm56270_speed[unit][ml_port_details_index][port-1] = 2500; 7737 } else { 7738 if (port >= 5) { 7739 SOC_PBMP_PORT_ADD(*ml_pbmp.pbmp_xl10g, port); 7740 SOC_PBMP_PORT_ADD(*ml_pbmp.pbmp_gport_stack, port); 7741 bcm56270_speed[unit][ml_port_details_index][port-1] = 11000; 7742 } 7743 } 7744 } 7745 ml_port_used_flags[port-1] = 1; 7746 } /* for port */ 7747 loop_index++; 7748 } /* while ml_selected_port_details */ 7749 7750 /* Update all pp ports available in system */ 7751 for (port = 0; port < ML_MAX_PP_PORTS; port++) { 7752 SOC_PBMP_PORT_ADD(*ml_pbmp.pbmp_pp, port); 7753 SOC_PBMP_PORT_ADD(*pbmp_pp_unused, port); 7754 } 7755 7756 /* Remove disabled ports from pbmp_valid */ 7757 for (port = 1; port < ML_LPBK; port++) { 7758 SOC_PBMP_PORT_REMOVE(*pbmp_pp_unused, port); 7759 if (ml_port_used_flags[port-1] == 0) { 7760 SOC_PBMP_PORT_REMOVE(*ml_pbmp.pbmp_valid, port); 7761 if(soc_metrolite_is_pp_port_reusable(unit, port) == TRUE) { 7762 SOC_PBMP_PORT_ADD(*pbmp_pp_unused, port); 7763 } 7764 } 7765 } 7766 7767 SOC_PBMP_PORT_REMOVE(*pbmp_pp_unused, ML_CMIC); 7768 SOC_PBMP_PORT_REMOVE(*pbmp_pp_unused, ML_LPBK); 7769 } 7770 7771 void 7772 soc_metrolite_subport_init(int unit, soc_pbmp_t *pbmp_pp_unused) 7773 { 7774 soc_port_t port, prev_port; 7775 soc_pbmp_t pbmp_subport, pbmp_linkphy; 7776 soc_info_t *si = &SOC_INFO(unit); 7777 int num_subport = 0, available_subport = 0; 7778 int max_subport_available = SOC_ML_MAX_SUBPORTS; 7779 int i = 0, pp_port_free = 0; 7780 7781 /* Clear all pbmp */ 7782 SOC_PBMP_CLEAR(pbmp_subport); 7783 SOC_PBMP_CLEAR(pbmp_linkphy); 7784 SOC_PBMP_CLEAR(si->linkphy_pbm); 7785 SOC_PBMP_CLEAR(si->lp.bitmap); 7786 SOC_PBMP_CLEAR(si->linkphy_allowed_pbm); 7787 SOC_PBMP_CLEAR(si->subtag_pbm); 7788 SOC_PBMP_CLEAR(si->subtag_allowed_pbm); 7789 SOC_PBMP_CLEAR(si->subtag.bitmap); 7790 SOC_PBMP_CLEAR(si->linkphy_pp_port_pbm); 7791 SOC_PBMP_CLEAR(si->enabled_linkphy_pp_port_pbm); 7792 SOC_PBMP_CLEAR(si->subtag_pp_port_pbm); 7793 SOC_PBMP_CLEAR(si->enabled_subtag_pp_port_pbm); 7794 si->subtag_enabled = 0; 7795 si->linkphy_enabled = 0; 7796 7797 for (port = 0; port <= ML_MAX_PHYSICAL_PORTS; port++) { 7798 si->port_num_subport[port] = 0; 7799 si->port_subport_base[port] = 0; 7800 si->port_linkphy_s1_base[port] = 0; 7801 SOC_PBMP_CLEAR(SOC_PORT_PP_BITMAP(unit, port)); 7802 } 7803 7804 /* Retreive subtag/linkphy pbmp from config */ 7805 pbmp_subport = soc_property_get_pbmp(unit, spn_PBMP_SUBPORT, 0); 7806 pbmp_linkphy = soc_property_get_pbmp(unit, spn_PBMP_LINKPHY, 0); 7807 7808 /* Assign subtag/linkphy allowed pbmp */ 7809 SOC_PBMP_ASSIGN(si->subtag_allowed_pbm, pbmp_subport); 7810 SOC_PBMP_ASSIGN(si->linkphy_allowed_pbm, pbmp_linkphy); 7811 7812 if (SOC_PBMP_NOT_NULL(pbmp_subport)) { 7813 /* All members of pbmp_linkphy should also be 7814 * member of pbmp_subport */ 7815 if (SOC_PBMP_NOT_NULL(pbmp_linkphy)) { 7816 /* Check if pbmp_linkphy members are valid for 7817 * supporting LinkPHY. 7818 */ 7819 SOC_PBMP_ITER(pbmp_linkphy, port) { 7820 if (!SOC_REG_PORT_VALID(unit, RXLP_PORT_ENABLEr, port)) { 7821 LOG_ERROR(BSL_LS_SOC_COMMON, 7822 (BSL_META_U(unit, "\nCONFIG ERROR\n" 7823 "pbmp_linkphy member port %d is invalid for " 7824 "LinkPHY support\n\n"), port)); 7825 SOC_PBMP_CLEAR(si->subtag_allowed_pbm); 7826 SOC_PBMP_CLEAR(si->linkphy_allowed_pbm); 7827 break; 7828 } 7829 SOC_PBMP_PORT_ADD(si->linkphy_allowed_pbm, port); 7830 } 7831 7832 SOC_PBMP_ITER(pbmp_linkphy, port) { 7833 if (!SOC_PBMP_MEMBER(pbmp_subport, port)) { 7834 LOG_ERROR(BSL_LS_SOC_COMMON, 7835 (BSL_META_U(unit, "\nCONFIG ERROR\n" 7836 "pbmp_linkphy member port %d is not member of " 7837 "pbmp_subport\n\n"), port)); 7838 SOC_PBMP_CLEAR(si->subtag_allowed_pbm); 7839 SOC_PBMP_CLEAR(si->linkphy_allowed_pbm); 7840 break; 7841 } 7842 SOC_PBMP_PORT_REMOVE(si->subtag_allowed_pbm, port); 7843 } 7844 } 7845 } else { 7846 if (SOC_PBMP_NOT_NULL(pbmp_linkphy)) { 7847 LOG_ERROR(BSL_LS_SOC_COMMON, 7848 (BSL_META_U(unit, "\nCONFIG ERROR\n" 7849 "config variable pbmp_linkphy should be sub-set of " 7850 "config variable pbmp_subport\n\n"))); 7851 } 7852 } 7853 7854 /* Retreive available subports and max subport possible */ 7855 SOC_PBMP_ITER(*pbmp_pp_unused, port) { 7856 available_subport++; 7857 } 7858 7859 prev_port = 0; 7860 si->port_num_subport[prev_port] = 0; 7861 si->port_subport_base[prev_port] = 0; 7862 7863 if (SOC_PBMP_NOT_NULL(si->linkphy_allowed_pbm)) { 7864 7865 /* Iterate through LinkPHY members first and reserve subport indices */ 7866 SOC_PBMP_ITER(si->linkphy_allowed_pbm, port) { 7867 if (port < SOC_MAX_NUM_PORTS) { 7868 num_subport = 7869 soc_property_port_get(unit, port, spn_NUM_SUBPORTS, 0); 7870 7871 if (num_subport > SOC_ML_MAX_LINKPHY_SUBPORTS_PER_PORT) { 7872 num_subport = SOC_ML_MAX_LINKPHY_SUBPORTS_PER_PORT; 7873 } 7874 7875 if (num_subport == 0) { 7876 LOG_ERROR(BSL_LS_SOC_COMMON, 7877 (BSL_META_U(unit, "\nCONFIG ERROR\n" 7878 "num_subports_%d should be non-zero for " 7879 "LinkPHY port %d\n\n"), port, port)); 7880 SOC_PBMP_PORT_REMOVE(si->linkphy_allowed_pbm, port); 7881 continue; 7882 } 7883 7884 if ((num_subport - 1) > available_subport) { 7885 LOG_ERROR(BSL_LS_SOC_COMMON, 7886 (BSL_META_U(unit, "\nCONFIG ERROR\n" 7887 "num_subports_%d=%d unavailable for LinkPHY port\n\n"), 7888 port, num_subport)); 7889 SOC_PBMP_PORT_REMOVE(si->linkphy_allowed_pbm, port); 7890 continue; 7891 } 7892 7893 if (max_subport_available <= 0) { 7894 LOG_ERROR(BSL_LS_SOC_COMMON, 7895 (BSL_META_U(unit, "\nCONFIG ERROR\n" 7896 "maximum subports %d are consumed already\n\n"), 7897 SOC_ML_MAX_SUBPORTS)); 7898 SOC_PBMP_PORT_REMOVE(si->linkphy_allowed_pbm, port); 7899 continue; 7900 } 7901 7902 /* Allocate all pp ports */ 7903 for (i = 0; i < num_subport; i++) { 7904 if (i == 0) { 7905 /* For the first subport, reuse pp port of parent */ 7906 SOC_PBMP_PORT_ADD(SOC_PORT_PP_BITMAP(unit, port), port); 7907 SOC_PBMP_PORT_ADD(si->linkphy_pp_port_pbm, port); 7908 SOC_PBMP_PORT_ADD(si->enabled_linkphy_pp_port_pbm, port); 7909 continue; 7910 } 7911 SOC_PBMP_ITER(*pbmp_pp_unused, pp_port_free) { 7912 SOC_PBMP_PORT_ADD(SOC_PORT_PP_BITMAP(unit, port), pp_port_free); 7913 SOC_PBMP_PORT_ADD(si->linkphy_pp_port_pbm, pp_port_free); 7914 SOC_PBMP_PORT_REMOVE(*pbmp_pp_unused, pp_port_free); 7915 /* Set this port in the enabled bmap by default at init */ 7916 SOC_PBMP_PORT_ADD(si->enabled_linkphy_pp_port_pbm, 7917 pp_port_free); 7918 break; 7919 } 7920 } 7921 7922 si->port_subport_base[port] = si->port_subport_base[prev_port] + si->port_num_subport[prev_port]; 7923 si->port_num_subport[port] = num_subport; 7924 si->port_linkphy_s1_base[port] = si->port_subport_base[prev_port] + si->port_num_subport[prev_port]; 7925 7926 available_subport -= (num_subport -1); 7927 max_subport_available -= num_subport; 7928 7929 prev_port = port; 7930 } 7931 } /* end SOC_PBMP_ITER(si->linkphy_allowed_pbm, port) */ 7932 } 7933 7934 prev_port = 0; 7935 si->port_subport_base[prev_port] = SOC_ML_MAX_SUBPORTS - max_subport_available; 7936 si->port_num_subport[prev_port] = 0; 7937 7938 if (SOC_PBMP_NOT_NULL(si->subtag_allowed_pbm)) { 7939 /* Iterate through SubTag ports and reserve subport indices */ 7940 SOC_PBMP_ITER(si->subtag_allowed_pbm, port) { 7941 num_subport = 7942 soc_property_port_get(unit, port, spn_NUM_SUBPORTS, 0); 7943 7944 if (num_subport == 0) { 7945 LOG_ERROR(BSL_LS_SOC_COMMON, 7946 (BSL_META_U(unit, "\nCONFIG ERROR\n" 7947 "num_subports_%d should be non-zero for SubTag port %d\n\n"), 7948 port, port)); 7949 SOC_PBMP_PORT_REMOVE(si->subtag_allowed_pbm, port); 7950 continue; 7951 } 7952 7953 if ((num_subport - 1) > available_subport) { 7954 LOG_ERROR(BSL_LS_SOC_COMMON, 7955 (BSL_META_U(unit, "\nCONFIG ERROR\n" 7956 "num_subports_%d=%d unavailable for SubTag port\n\n"), 7957 port, num_subport)); 7958 SOC_PBMP_PORT_REMOVE(si->subtag_allowed_pbm, port); 7959 continue; 7960 } 7961 7962 if (max_subport_available <= 0) { 7963 LOG_ERROR(BSL_LS_SOC_COMMON, 7964 (BSL_META_U(unit, "\nCONFIG ERROR\n" 7965 "maximum subports %d are consumed already\n\n"), 7966 SOC_ML_MAX_SUBPORTS)); 7967 SOC_PBMP_PORT_REMOVE(si->subtag_allowed_pbm, port); 7968 continue; 7969 } 7970 7971 7972 /* Allocate all pp ports */ 7973 for (i = 0; i < num_subport; i++) { 7974 if (i == 0) { 7975 /* For the first subport, reuse pp port of parent */ 7976 SOC_PBMP_PORT_ADD(SOC_PORT_PP_BITMAP(unit, port), port); 7977 SOC_PBMP_PORT_ADD(si->subtag_pp_port_pbm, port); 7978 SOC_PBMP_PORT_ADD(si->enabled_subtag_pp_port_pbm, port); 7979 continue; 7980 } 7981 SOC_PBMP_ITER(*pbmp_pp_unused, pp_port_free) { 7982 SOC_PBMP_PORT_ADD(SOC_PORT_PP_BITMAP(unit, port), pp_port_free); 7983 SOC_PBMP_PORT_ADD(si->subtag_pp_port_pbm, pp_port_free); 7984 SOC_PBMP_PORT_REMOVE(*pbmp_pp_unused, pp_port_free); 7985 /* Set this port in the enabled bmap by default at init */ 7986 SOC_PBMP_PORT_ADD(si->enabled_subtag_pp_port_pbm, 7987 pp_port_free); 7988 break; 7989 } 7990 } 7991 7992 si->port_subport_base[port] = si->port_subport_base[prev_port] + si->port_num_subport[prev_port]; 7993 si->port_num_subport[port] = num_subport; 7994 si->port_linkphy_s1_base[port] = 0; 7995 available_subport -= (num_subport - 1); 7996 max_subport_available -= num_subport; 7997 prev_port = port; 7998 } 7999 } 8000 8001 if (SOC_PBMP_NOT_NULL (si->subtag_pp_port_pbm)) { 8002 si->subtag_enabled = 1; 8003 } 8004 if (SOC_PBMP_NOT_NULL (si->linkphy_pp_port_pbm)) { 8005 si->linkphy_enabled = 1; 8006 } 8007 } 8008 8009 int ml_iecell_port[2][4] = { 8010 {5, 6, 7, 8}, /* IECELL0 */ 8011 {9, 10, 11, 12} /* IECELL1*/ 8012 }; 8013 int 8014 soc_ml_iecell_port_reg_blk_idx_get( 8015 int unit, int port, int blktype, int *block, int *index) 8016 { 8017 int i,j; 8018 int blk = -1; 8019 int idx = -1; 8020 8021 for (i=0; i<2; i++) { 8022 for(j=0; j<4; j++) { 8023 if(port == ml_iecell_port[i][j]) { 8024 blk = i; 8025 idx = j; 8026 break; 8027 } 8028 } 8029 } 8030 8031 if (blktype == SOC_BLK_IECELL) { 8032 switch(blk) 8033 { 8034 case 0 : 8035 blk = IECELL0_BLOCK(unit); 8036 break; 8037 case 1 : 8038 blk = IECELL1_BLOCK(unit); 8039 break; 8040 default : 8041 return SOC_E_PARAM; 8042 } 8043 } else { 8044 return SOC_E_PARAM; 8045 } 8046 8047 if (block != NULL) { 8048 *block = blk; 8049 } 8050 if (index != NULL) { 8051 *index = idx; 8052 } 8053 if ((blk == -1) || (idx == -1)) { 8054 return SOC_E_NOT_FOUND; 8055 } 8056 return SOC_E_NONE; 8057 } 8058 8059 void 8060 soc_metrolite_sbus_ring_map_config(int unit) 8061 { 8062 /* 8063 * SBUS ring and block number 8064 */ 8065 WRITE_CMIC_SBUS_RING_MAP_0_7r(unit, 0x62034000); 8066 WRITE_CMIC_SBUS_RING_MAP_8_15r(unit, 0x60377531); 8067 WRITE_CMIC_SBUS_RING_MAP_16_23r(unit, 0x00000031); 8068 WRITE_CMIC_SBUS_RING_MAP_24_31r(unit, 0x0); 8069 WRITE_CMIC_SBUS_RING_MAP_32_39r(unit, 0x0); 8070 WRITE_CMIC_SBUS_RING_MAP_40_47r(unit, 0x0); 8071 WRITE_CMIC_SBUS_RING_MAP_48_55r(unit, 0x0); 8072 WRITE_CMIC_SBUS_RING_MAP_56_63r(unit, 0x0); 8073 8074 WRITE_CMIC_SBUS_TIMEOUTr(unit, 0x7d0); 8075 8076 return; 8077 } 8078 8079 /* 8080 * Metrolite chip driver functions. 8081 */ 8082 soc_functions_t soc_metrolite_drv_funs = { 8083 _soc_metrolite_misc_init, /* soc_misc_init_f */ 8084 _soc_metrolite_mmu_init, /* soc_mmu_init_f */ 8085 _soc_metrolite_age_timer_get, /* soc_age_timer_get_f */ 8086 _soc_metrolite_age_timer_max_get, /* soc_age_timer_max_get_f */ 8087 _soc_metrolite_age_timer_set, /* soc_age_timer_set_f */ 8088 _soc_saber2_tsce_firmware_set, /* soc_phy_firmware_load_f */ 8089 _soc_saber2_mdio_reg_read, /* soc_sbus_mdio_read_f */ 8090 _soc_saber2_mdio_reg_write, /* soc_sbus_mdio_write_f */ 8091 soc_metrolite_bond_info_init /* soc_bond_options_init_f */ 8092 }; 8093 8094 int 8095 soc_ml_get_max_buffer_size(int unit, int value) 8096 { 8097 int cval; 8098 cval = _soc_ml_mmu_intermediate_results.general_info.max_int_cell_buff_size; 8099 if ((cval <= 0) || (cval >= value)) { 8100 return value; 8101 } else { 8102 return cval; 8103 } 8104 } 8105 8106 #endif /* BCM_METROLITE_SUPPORT */