ser.c (66407B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: ser.c 8 * Purpose: SER enable/detect and test functionality. 9 * Requires: sal/soc/shared layer 10 */ 11 12 13 #include <shared/bsl.h> 14 #include <soc/debug.h> 15 #include <soc/iproc.h> 16 #ifdef BCM_CMICX_SUPPORT 17 #include <soc/intr_cmicx.h> 18 #endif 19 20 #ifdef BCM_MAVERICK2_SUPPORT 21 22 #include <soc/maverick2.h> 23 24 #define _SOC_MMU_BASE_INDEX_GLB 0 25 #define _SOC_MMU_BASE_INDEX_XPE 0 26 #define _SOC_MMU_BASE_INDEX_SC 0 27 #define _SOC_MMU_BASE_INDEX_SED 0 28 29 #define _SOC_MV2_IPIPE0_CEV_INTR 0x00000001 30 #define _SOC_MV2_IPIPE0_IDB_INTR 0x00000040 31 #define _SOC_MV2_IPIPE0_IP_INTR 0x00000080 32 #define _SOC_MV2_IPIPE0_ISW4_INTR 0x00000100 33 34 #if defined(BCM_56770_A0) 35 extern _soc_bus_ser_en_info_t _soc_bcm56770_a0_ip_bus_ser_info[]; 36 extern _soc_buffer_ser_en_info_t _soc_bcm56770_a0_ip_buffer_ser_info[]; 37 extern _soc_bus_ser_en_info_t _soc_bcm56770_a0_ep_bus_ser_info[]; 38 extern _soc_buffer_ser_en_info_t _soc_bcm56770_a0_ep_buffer_ser_info[]; 39 #endif 40 41 typedef struct _soc_mv2_ser_mmu_intr_info_s { 42 soc_reg_t int_statf; 43 int mmu_base_index; 44 int ser_info_index; 45 } _soc_mv2_ser_mmu_intr_info_t; 46 47 typedef _soc_td3_ser_info_type_t _soc_mv2_ser_info_type_t; 48 49 typedef struct _soc_mv2_ser_route_block_s { 50 uint8 cmic_reg; /* 3: intr3, 4: intr4, 5: intr5 */ 51 uint32 cmic_bit; 52 soc_block_t blocktype; 53 int pipe; 54 soc_reg_t enable_reg; 55 soc_reg_t status_reg; 56 soc_field_t enable_field; 57 void *info; 58 uint8 id; 59 } _soc_mv2_ser_route_block_t; 60 61 typedef struct _soc_mv2_tcam_wrapper_info_s { 62 soc_mem_t mem; 63 soc_reg_t enable_reg; 64 soc_field_t enable_field; 65 soc_field_t parity_field; /* used to sw inject test */ 66 } _soc_mv2_tcam_wrapper_info_t; 67 68 typedef _soc_td3_ser_reg_t _soc_mv2_ser_reg_t; 69 70 typedef _soc_td3_ser_info_t _soc_mv2_ser_info_t; 71 72 typedef struct _soc_mv2_tmp_ser_info_s { 73 soc_reg_t enable_reg; 74 soc_field_t enable_field; 75 uint32 value; 76 } _soc_mv2_tmp_ser_info_t; 77 78 typedef struct _soc_mv2_hash_table_ser_info_s { 79 soc_mem_t mem; 80 soc_field_t enable_field; 81 } _soc_mv2_hash_table_ser_info_t; 82 83 static soc_ser_functions_t _mv2_ser_functions; 84 85 static soc_field_t _soc_mv2_mmu_xpe_enable_fields[] = { 86 AGING_PARITY_ENf, 87 TCB_PARITY_ENf, 88 THDM_PARITY_ENf, 89 ENQX_PARITY_ENf, 90 EPRG_PARITY_ENf, 91 RQE_PARITY_ENf, 92 THDI_PARITY_ENf, 93 THDU_PARITY_ENf, 94 PQE_PARITY_ENf, 95 WRED_PARITY_ENf, 96 DQX_PARITY_ENf, 97 CCP_PARITY_ENf, 98 CTR_PARITY_ENf, 99 INVALIDf 100 }; 101 102 static soc_field_t _soc_mv2_mmu_sc_enable_fields[] = { 103 TDM_PARITY_ENf, 104 VBS_PARITY_ENf, 105 TOQ_PARITY_ENf, 106 INVALIDf 107 }; 108 109 static soc_field_t _soc_mv2_mmu_sed_enable_fields[] = { 110 MB0_PARITY_ENf, 111 MB1_PARITY_ENf, 112 ENQS_PARITY_ENf, 113 MTRO_PARITY_ENf, 114 DQS_PARITY_ENf, 115 CFAP_PARITY_ENf, 116 INVALIDf 117 }; 118 119 static _soc_mv2_ser_info_t _soc_mv2_mmu_ser_info[] = { 120 { _SOC_TD3_PARITY_TYPE_MMU_GLB, NULL, 0, 121 INVALIDf, INVALIDf, 122 INVALIDm, "MMU GLB MEM PAR", 123 MMU_GCFG_PARITY_ENr, INTFO_PARITY_ENf, NULL, 124 MMU_GCFG_GLB_CPU_INT_ENr, MEM_PAR_ERR_ENf, NULL, 125 MMU_GCFG_GLB_CPU_INT_STATr, NULL, MEM_PAR_ERR_STATf, NULL, 126 MMU_GCFG_GLB_CPU_INT_CLEARr, MEM_PAR_ERR_CLRf, NULL 127 }, 128 { _SOC_TD3_PARITY_TYPE_MMU_XPE, NULL, 0, 129 INVALIDf, INVALIDf, 130 INVALIDm, "MMU XPE MEM PAR", 131 MMU_XCFG_PARITY_ENr, INVALIDf, _soc_mv2_mmu_xpe_enable_fields, 132 MMU_XCFG_XPE_CPU_INT_ENr, MEM_PAR_ERR_ENf, NULL, 133 MMU_XCFG_XPE_CPU_INT_STATr, NULL, MEM_PAR_ERR_STATf, NULL, 134 MMU_XCFG_XPE_CPU_INT_CLEARr, MEM_PAR_ERR_CLRf, NULL 135 }, 136 { _SOC_TD3_PARITY_TYPE_MMU_SC, NULL, 0, 137 INVALIDf, INVALIDf, 138 INVALIDm, "MMU SC MEM PAR", 139 MMU_SCFG_PARITY_ENr, INVALIDf, _soc_mv2_mmu_sc_enable_fields, 140 MMU_SCFG_SC_CPU_INT_ENr, MEM_PAR_ERR_ENf, NULL, 141 MMU_SCFG_SC_CPU_INT_STATr, NULL, MEM_PAR_ERR_STATf, NULL, 142 MMU_SCFG_SC_CPU_INT_CLEARr, MEM_PAR_ERR_CLRf, NULL 143 }, 144 { _SOC_TD3_PARITY_TYPE_MMU_SED, NULL, 0, 145 INVALIDf, INVALIDf, 146 INVALIDm, "MMU SED MEM PAR", 147 MMU_SEDCFG_PARITY_ENr, INVALIDf, _soc_mv2_mmu_sed_enable_fields, 148 MMU_SEDCFG_SED_CPU_INT_ENr, MEM_PAR_ERR_ENf, NULL, 149 MMU_SEDCFG_SED_CPU_INT_STATr, NULL, MEM_PAR_ERR_STATf, NULL, 150 MMU_SEDCFG_SED_CPU_INT_CLEARr, MEM_PAR_ERR_CLRf, NULL 151 }, 152 { _SOC_TD3_PARITY_TYPE_NONE } /* table terminator */ 153 }; 154 155 static soc_field_t _soc_mv2_mmu_top_int_enable_fields[] = { 156 SED_CPU_INT_ENf, 157 SC_CPU_INT_ENf, 158 XPE_CPU_INT_ENf, 159 GLB_CPU_INT_ENf, 160 INVALIDf 161 }; 162 163 static soc_field_t _soc_mv2_mmu_top_int_status_fields[] = { 164 SED_CPU_INT_STATf, 165 SC_CPU_INT_STATf, 166 XPE_CPU_INT_STATf, 167 GLB_CPU_INT_STATf, 168 INVALIDf 169 }; 170 171 static _soc_mv2_ser_info_t _soc_mv2_mmu_top_ser_info[] = { 172 { _SOC_TD3_PARITY_TYPE_MMU_SER, _soc_mv2_mmu_ser_info, 0, 173 INVALIDf, INVALIDf, 174 INVALIDm, "MMU MEM PAR", 175 INVALIDr, INVALIDf, NULL, 176 MMU_GCFG_ALL_CPU_INT_ENr, INVALIDf, 177 _soc_mv2_mmu_top_int_enable_fields, 178 MMU_GCFG_ALL_CPU_INT_STATr, 179 NULL, INVALIDf, _soc_mv2_mmu_top_int_status_fields, 180 INVALIDr, INVALIDf, NULL 181 }, 182 { _SOC_TD3_PARITY_TYPE_NONE } /* table terminator */ 183 }; 184 185 static _soc_mv2_ser_reg_t _soc_mv2_pm_clp_rx_status_reg[] = { 186 { CLPORT_MIB_RSC0_ECC_STATUSr, "CLP MIB RSC0 ECC" }, 187 { CLPORT_MIB_RSC1_ECC_STATUSr, "CLP MIB RSC1 ECC" }, 188 { INVALIDr, "INVALIDr"} 189 }; 190 191 static _soc_mv2_ser_reg_t _soc_mv2_pm_clp_tx_status_reg[] = { 192 { CLPORT_MIB_TSC0_ECC_STATUSr, "CLP MIB TSC0 ECC" }, 193 { CLPORT_MIB_TSC1_ECC_STATUSr, "CLP MIB TSC1 ECC" }, 194 { INVALIDr, "INVALIDr"} 195 }; 196 197 static _soc_mv2_ser_reg_t _soc_mv2_pm_xlp_rx_status_reg[] = { 198 { XLPORT_MIB_RSC0_ECC_STATUSr, "XLP MIB RSC0 ECC" }, 199 { XLPORT_MIB_RSC1_ECC_STATUSr, "XLP MIB RSC1 ECC" }, 200 { INVALIDr, "INVALIDr"} 201 }; 202 203 static _soc_mv2_ser_reg_t _soc_mv2_pm_xlp_tx_status_reg[] = { 204 { XLPORT_MIB_TSC0_ECC_STATUSr, "XLP MIB TSC0 ECC" }, 205 { XLPORT_MIB_TSC1_ECC_STATUSr, "XLP MIB TSC1 ECC" }, 206 { INVALIDr, "INVALIDr"} 207 }; 208 209 static _soc_mv2_ser_info_t _soc_mv2_pm_clp_ser_info[] = { 210 { _SOC_TD3_PARITY_TYPE_CLMAC, NULL, 0, 211 MAC_ERRf, MAC_ERRf, 212 INVALIDm, "MAC RX TimeStamp CDC memory", 213 CLMAC_INTR_ENABLEr, EN_RX_TS_MEM_SINGLE_BIT_ERRf, NULL, 214 INVALIDr, INVALIDf, NULL, 215 CLMAC_INTR_STATUSr, NULL, SUM_RX_TS_MEM_SINGLE_BIT_ERRf, NULL, 216 CLMAC_CLEAR_ECC_STATUSr, CLEAR_RX_TS_MEM_SINGLE_BIT_ERRf, NULL 217 }, 218 { _SOC_TD3_PARITY_TYPE_CLMAC, NULL, 0, 219 MAC_ERRf, MAC_ERRf, 220 INVALIDm, "MAC RX TimeStamp CDC memory", 221 CLMAC_INTR_ENABLEr, EN_RX_TS_MEM_DOUBLE_BIT_ERRf, NULL, 222 INVALIDr, INVALIDf, NULL, 223 CLMAC_INTR_STATUSr, NULL, SUM_TX_CDC_DOUBLE_BIT_ERRf, NULL, 224 CLMAC_CLEAR_ECC_STATUSr, CLEAR_RX_TS_MEM_DOUBLE_BIT_ERRf, NULL 225 }, 226 { _SOC_TD3_PARITY_TYPE_CLMAC, NULL, 0, 227 MAC_ERRf, MAC_ERRf, 228 INVALIDm, "CLMAC RX CDC single bit", 229 CLMAC_INTR_ENABLEr, EN_RX_CDC_SINGLE_BIT_ERRf, NULL, 230 INVALIDr, INVALIDf, NULL, 231 CLMAC_INTR_STATUSr, NULL, SUM_RX_CDC_SINGLE_BIT_ERRf, NULL, 232 CLMAC_CLEAR_ECC_STATUSr, CLEAR_RX_CDC_SINGLE_BIT_ERRf, NULL 233 }, 234 { _SOC_TD3_PARITY_TYPE_CLMAC, NULL, 0, 235 MAC_ERRf, MAC_ERRf, 236 INVALIDm, "CLMAC RX CDC double bits", 237 CLMAC_INTR_ENABLEr, EN_RX_CDC_DOUBLE_BIT_ERRf, NULL, 238 INVALIDr, INVALIDf, NULL, 239 CLMAC_INTR_STATUSr, NULL, SUM_RX_CDC_DOUBLE_BIT_ERRf, NULL, 240 CLMAC_CLEAR_ECC_STATUSr, CLEAR_RX_CDC_DOUBLE_BIT_ERRf, NULL 241 }, 242 { _SOC_TD3_PARITY_TYPE_CLMAC, NULL, 0, 243 MAC_ERRf, MAC_ERRf, 244 INVALIDm, "CLMAC TX CDC single bit", 245 CLMAC_INTR_ENABLEr, EN_TX_CDC_SINGLE_BIT_ERRf, NULL, 246 INVALIDr, INVALIDf, NULL, 247 CLMAC_INTR_STATUSr, NULL, SUM_TX_CDC_SINGLE_BIT_ERRf, NULL, 248 CLMAC_CLEAR_ECC_STATUSr, CLEAR_TX_CDC_SINGLE_BIT_ERRf, NULL 249 }, 250 { _SOC_TD3_PARITY_TYPE_CLMAC, NULL, 0, 251 MAC_ERRf, MAC_ERRf, 252 INVALIDm, "CLMAC TX CDC double bits", 253 CLMAC_INTR_ENABLEr, EN_TX_CDC_DOUBLE_BIT_ERRf, NULL, 254 INVALIDr, INVALIDf, NULL, 255 CLMAC_INTR_STATUSr, NULL, SUM_TX_CDC_DOUBLE_BIT_ERRf, NULL, 256 CLMAC_CLEAR_ECC_STATUSr, CLEAR_TX_CDC_DOUBLE_BIT_ERRf, NULL 257 }, 258 { _SOC_TD3_PARITY_TYPE_ECC, NULL, 0, 259 MIB_RX_MEM_ERRf, MIB_RX_MEM_ERRf, 260 INVALIDm, "MIB RX Statistic Counter memory", 261 CLPORT_ECC_CONTROLr, MIB_RSC_MEM_ENf, NULL, 262 INVALIDr, INVALIDf, NULL, 263 INVALIDr, _soc_mv2_pm_clp_rx_status_reg, INVALIDf, NULL, 264 CLPORT_INTR_STATUSr, MIB_RX_MEM_ERRf, NULL 265 }, 266 { _SOC_TD3_PARITY_TYPE_ECC, NULL, 0, 267 MIB_TX_MEM_ERRf, MIB_TX_MEM_ERRf, 268 INVALIDm, "MIB TX Statistic Counter memory", 269 CLPORT_ECC_CONTROLr, MIB_TSC_MEM_ENf, NULL, 270 INVALIDr, INVALIDf, NULL, 271 INVALIDr, _soc_mv2_pm_clp_tx_status_reg, INVALIDf, NULL, 272 CLPORT_INTR_STATUSr, MIB_TX_MEM_ERRf, NULL 273 }, 274 { _SOC_TD3_PARITY_TYPE_NONE } /* table terminator */ 275 }; 276 277 static _soc_mv2_ser_info_t _soc_mv2_pm_xlp_ser_info[] = { 278 { _SOC_TD3_PARITY_TYPE_XLMAC, NULL, 0, 279 MAC_ERRf, MAC_ERRf, 280 INVALIDm, "MAC RX CDC memory", 281 XLMAC_INTR_ENABLEr, EN_RX_CDC_SINGLE_BIT_ERRf, NULL, 282 INVALIDr, INVALIDf, NULL, 283 XLMAC_INTR_STATUSr, NULL, SUM_RX_CDC_SINGLE_BIT_ERRf, NULL, 284 XLMAC_CLEAR_ECC_STATUSr, CLEAR_RX_CDC_SINGLE_BIT_ERRf, NULL 285 }, 286 { _SOC_TD3_PARITY_TYPE_XLMAC, NULL, 0, 287 MAC_ERRf, MAC_ERRf, 288 INVALIDm, "MAC RX CDC memory", 289 XLMAC_INTR_ENABLEr, EN_RX_CDC_DOUBLE_BIT_ERRf, NULL, 290 INVALIDr, INVALIDf, NULL, 291 XLMAC_INTR_STATUSr, NULL, SUM_RX_CDC_DOUBLE_BIT_ERRf, NULL, 292 XLMAC_CLEAR_ECC_STATUSr, CLEAR_RX_CDC_DOUBLE_BIT_ERRf, NULL 293 }, 294 { _SOC_TD3_PARITY_TYPE_XLMAC, NULL, 0, 295 MAC_ERRf, MAC_ERRf, 296 INVALIDm, "MAC RX CDC memory", 297 XLMAC_INTR_ENABLEr, EN_TX_CDC_SINGLE_BIT_ERRf, NULL, 298 INVALIDr, INVALIDf, NULL, 299 XLMAC_INTR_STATUSr, NULL, SUM_TX_CDC_SINGLE_BIT_ERRf, NULL, 300 XLMAC_CLEAR_ECC_STATUSr, CLEAR_TX_CDC_SINGLE_BIT_ERRf, NULL 301 }, 302 { _SOC_TD3_PARITY_TYPE_XLMAC, NULL, 0, 303 MAC_ERRf, MAC_ERRf, 304 INVALIDm, "MAC TX CDC memory", 305 XLMAC_INTR_ENABLEr, EN_TX_CDC_DOUBLE_BIT_ERRf, NULL, 306 INVALIDr, INVALIDf, NULL, 307 XLMAC_INTR_STATUSr, NULL, SUM_TX_CDC_DOUBLE_BIT_ERRf, NULL, 308 XLMAC_CLEAR_ECC_STATUSr, CLEAR_TX_CDC_DOUBLE_BIT_ERRf, NULL 309 }, 310 { _SOC_TD3_PARITY_TYPE_ECC, NULL, 0, 311 MIB_RX_MEM_ERRf, MIB_RX_MEM_ERRf, 312 INVALIDm, "MIB RX Statistic Counter memory", 313 XLPORT_ECC_CONTROLr, MIB_RSC_MEM_ENf, NULL, 314 INVALIDr, INVALIDf, NULL, 315 INVALIDr, _soc_mv2_pm_xlp_rx_status_reg, INVALIDf, NULL, 316 XLPORT_INTR_STATUSr, MIB_RX_MEM_ERRf, NULL 317 }, 318 { _SOC_TD3_PARITY_TYPE_ECC, NULL, 0, 319 MIB_TX_MEM_ERRf, MIB_TX_MEM_ERRf, 320 INVALIDm, "MIB TX Statistic Counter memory", 321 XLPORT_ECC_CONTROLr, MIB_TSC_MEM_ENf, NULL, 322 INVALIDr, INVALIDf, NULL, 323 INVALIDr, _soc_mv2_pm_xlp_tx_status_reg, INVALIDf, NULL, 324 XLPORT_INTR_STATUSr, MIB_TX_MEM_ERRf, NULL 325 }, 326 { _SOC_TD3_PARITY_TYPE_NONE } /* table terminator */ 327 }; 328 329 static _soc_mv2_ser_reg_t _soc_mv2_idb_status_reg[] = { 330 { IDB_OBM0_DATA_ECC_STATUSr, "IDB OBM0 packet data memory" }, 331 { IDB_OBM1_DATA_ECC_STATUSr, "IDB OBM1 packet data memory" }, 332 { IDB_OBM2_DATA_ECC_STATUSr, "IDB OBM2 packet data memory" }, 333 { IDB_OBM3_DATA_ECC_STATUSr, "IDB OBM3 packet data memory" }, 334 { IDB_OBM4_DATA_ECC_STATUSr, "IDB OBM4 packet data memory" }, 335 { IDB_OBM5_DATA_ECC_STATUSr, "IDB OBM5 packet data memory" }, 336 { IDB_OBM6_DATA_ECC_STATUSr, "IDB OBM6 packet data memory" }, 337 { IDB_OBM7_DATA_ECC_STATUSr, "IDB OBM7 packet data memory" }, 338 { IDB_OBM8_DATA_ECC_STATUSr, "IDB OBM8 packet data memory" }, 339 { IDB_OBM9_DATA_ECC_STATUSr, "IDB OBM9 packet data memory" }, 340 { IDB_OBM10_DATA_ECC_STATUSr, "IDB OBM10 packet data memory" }, 341 { IDB_OBM11_DATA_ECC_STATUSr, "IDB OBM11 packet data memory" }, 342 { IDB_OBM12_DATA_ECC_STATUSr, "IDB OBM12 packet data memory" }, 343 { IDB_OBM13_DATA_ECC_STATUSr, "IDB OBM13 packet data memory" }, 344 { IDB_OBM14_DATA_ECC_STATUSr, "IDB OBM14 packet data memory" }, 345 { IDB_OBM15_DATA_ECC_STATUSr, "IDB OBM15 packet data memory" }, 346 { IDB_OBM16_DATA_ECC_STATUSr, "IDB OBM16 packet data memory" }, 347 { IDB_OBM17_DATA_ECC_STATUSr, "IDB OBM17 packet data memory" }, 348 { IDB_OBM18_DATA_ECC_STATUSr, "IDB OBM18 packet data memory" }, 349 { IDB_OBM19_DATA_ECC_STATUSr, "IDB OBM19 packet data memory" }, 350 { IDB_OBM0_CA_ECC_STATUSr, "IDB OBM0 CA packet buffer memory" }, 351 { IDB_OBM1_CA_ECC_STATUSr, "IDB OBM1 CA packet buffer memory" }, 352 { IDB_OBM2_CA_ECC_STATUSr, "IDB OBM2 CA packet buffer memory" }, 353 { IDB_OBM3_CA_ECC_STATUSr, "IDB OBM3 CA packet buffer memory" }, 354 { IDB_OBM4_CA_ECC_STATUSr, "IDB OBM4 CA packet buffer memory" }, 355 { IDB_OBM5_CA_ECC_STATUSr, "IDB OBM5 CA packet buffer memory" }, 356 { IDB_OBM6_CA_ECC_STATUSr, "IDB OBM6 CA packet buffer memory" }, 357 { IDB_OBM7_CA_ECC_STATUSr, "IDB OBM7 CA packet buffer memory" }, 358 { IDB_OBM8_CA_ECC_STATUSr, "IDB OBM8 CA packet buffer memory" }, 359 { IDB_OBM9_CA_ECC_STATUSr, "IDB OBM9 CA packet buffer memory" }, 360 { IDB_OBM10_CA_ECC_STATUSr, "IDB OBM10 CA packet buffer memory" }, 361 { IDB_OBM11_CA_ECC_STATUSr, "IDB OBM11 CA packet buffer memory" }, 362 { IDB_OBM12_CA_ECC_STATUSr, "IDB OBM12 CA packet buffer memory" }, 363 { IDB_OBM13_CA_ECC_STATUSr, "IDB OBM13 CA packet buffer memory" }, 364 { IDB_OBM14_CA_ECC_STATUSr, "IDB OBM14 CA packet buffer memory" }, 365 { IDB_OBM15_CA_ECC_STATUSr, "IDB OBM15 CA packet buffer memory" }, 366 { IDB_OBM16_CA_ECC_STATUSr, "IDB OBM16 CA packet buffer memory" }, 367 { IDB_OBM17_CA_ECC_STATUSr, "IDB OBM17 CA packet buffer memory" }, 368 { IDB_OBM18_CA_ECC_STATUSr, "IDB OBM18 CA packet buffer memory" }, 369 { IDB_OBM19_CA_ECC_STATUSr, "IDB OBM19 CA packet buffer memory" }, 370 { IDB_OBM0_OVERSUB_MON_ECC_STATUSr, "IDB OBM0 oversub Monitoring memory" }, 371 { IDB_OBM1_OVERSUB_MON_ECC_STATUSr, "IDB OBM1 oversub Monitoring memory" }, 372 { IDB_OBM2_OVERSUB_MON_ECC_STATUSr, "IDB OBM2 oversub Monitoring memory" }, 373 { IDB_OBM3_OVERSUB_MON_ECC_STATUSr, "IDB OBM3 oversub Monitoring memory" }, 374 { IDB_OBM4_OVERSUB_MON_ECC_STATUSr, "IDB OBM4 oversub Monitoring memory" }, 375 { IDB_OBM5_OVERSUB_MON_ECC_STATUSr, "IDB OBM5 oversub Monitoring memory" }, 376 { IDB_OBM6_OVERSUB_MON_ECC_STATUSr, "IDB OBM6 oversub Monitoring memory" }, 377 { IDB_OBM7_OVERSUB_MON_ECC_STATUSr, "IDB OBM7 oversub Monitoring memory" }, 378 { IDB_OBM8_OVERSUB_MON_ECC_STATUSr, "IDB OBM8 oversub Monitoring memory" }, 379 { IDB_OBM9_OVERSUB_MON_ECC_STATUSr, "IDB OBM9 oversub Monitoring memory" }, 380 { IDB_OBM10_OVERSUB_MON_ECC_STATUSr, "IDB OBM10 oversub Monitoring memory" }, 381 { IDB_OBM11_OVERSUB_MON_ECC_STATUSr, "IDB OBM11 oversub Monitoring memory" }, 382 { IDB_OBM12_OVERSUB_MON_ECC_STATUSr, "IDB OBM12 oversub Monitoring memory" }, 383 { IDB_OBM13_OVERSUB_MON_ECC_STATUSr, "IDB OBM13 oversub Monitoring memory" }, 384 { IDB_OBM14_OVERSUB_MON_ECC_STATUSr, "IDB OBM14 oversub Monitoring memory" }, 385 { IDB_OBM15_OVERSUB_MON_ECC_STATUSr, "IDB OBM15 oversub Monitoring memory" }, 386 { IDB_OBM16_OVERSUB_MON_ECC_STATUSr, "IDB OBM16 oversub Monitoring memory" }, 387 { IDB_OBM17_OVERSUB_MON_ECC_STATUSr, "IDB OBM17 oversub Monitoring memory" }, 388 { IDB_OBM18_OVERSUB_MON_ECC_STATUSr, "IDB OBM18 oversub Monitoring memory" }, 389 { IDB_OBM19_OVERSUB_MON_ECC_STATUSr, "IDB OBM19 oversub Monitoring memory" }, 390 { IDB_CA_CPU_ECC_STATUSr, "CA-CPU packet buffer memory" }, 391 { IDB_CA_LPBK_ECC_STATUSr, "CA-LPBK packet buffer memory" }, 392 { IDB_CA_MGMT_ECC_STATUSr, "CA-MGMT packet buffer memory" }, 393 { IDB_SOP_EVENT_ECC_STATUSr, "IDB SOP Event Fifo ECC Status" }, 394 { IDB_EOP_EVENT_ECC_STATUSr, "IDB EOP Event Fifo ECC Status" }, 395 { INVALIDr } 396 }; 397 398 static _soc_mv2_ser_info_t _soc_mv2_idb_ser_info[] = { 399 { _SOC_TD3_PARITY_TYPE_ECC, NULL, 0, 400 MEM_ERROR_OCCURREDf, MEM_ERROR_OCCURREDf, 401 IS_TDM_CALENDAR0m, "IS_TDM CALENDAR0/1", 402 IDB_SER_CONTROLr, IS_TDM_ECC_ENf, NULL, 403 INVALIDr, INVALIDf, NULL, 404 IDB_IS_TDM_CAL_ECC_STATUSr, NULL, ECC_ERRf, NULL, 405 INVALIDr, INVALIDf, NULL 406 }, 407 408 { _SOC_TD3_PARITY_TYPE_ECC, NULL, 0, 409 MEM_ERROR_OCCURREDf, MEM_ERROR_OCCURREDf, 410 INVALIDm, "IP IDB memory", 411 INVALIDr, INVALIDf, NULL, 412 INVALIDr, INVALIDf, NULL, 413 INVALIDr, _soc_mv2_idb_status_reg, ECC_ERRf, NULL, 414 INVALIDr, INVALIDf, NULL 415 }, 416 417 { _SOC_TD3_PARITY_TYPE_NONE } /* table terminator */ 418 }; 419 420 static _soc_mv2_ser_info_t _soc_mv2_isw4_ser_info[] = { 421 { _SOC_TD3_PARITY_TYPE_ECC, NULL, 0, 422 SLOT_PIPELINE_ECC_ERRf, SLOT_PIPELINE_ECC_ERRf, 423 INVALIDm, "Slot pipeline", 424 SW4_SER_CONTROLr, SLOT_PIPELINE_ECC_ENf, NULL, 425 INVALIDr, INVALIDf, NULL, 426 SLOT_PIPELINE_ECC_STATUS_INTRr, NULL, ECC_ERRf, NULL, 427 INVALIDr, INVALIDf, NULL 428 }, 429 { _SOC_TD3_PARITY_TYPE_ECC, NULL, 0, 430 CELL_QUEUE_ECC_ERRf, CELL_QUEUE_ECC_ERRf, 431 INVALIDm, "Cell queue", 432 SW4_SER_CONTROLr, CELL_QUEUE_ECC_ENf, NULL, 433 INVALIDr, INVALIDf, NULL, 434 CELL_QUEUE_ECC_STATUS_INTRr, NULL, ECC_ERRf, NULL, 435 INVALIDr, INVALIDf, NULL 436 }, 437 { _SOC_TD3_PARITY_TYPE_ECC, NULL, 0, 438 EVENT_FIFO_ECC_ERRf, EVENT_FIFO_ECC_ERRf, 439 INVALIDm, "Event FIFO", 440 SW4_SER_CONTROLr, EVENT_FIFO_ECC_ENf, NULL, 441 INVALIDr, INVALIDf, NULL, 442 EVENT_FIFO_ECC_STATUS_INTRr, NULL, ECC_ERRf, NULL, 443 INVALIDr, INVALIDf, NULL 444 }, 445 446 { _SOC_TD3_PARITY_TYPE_NONE} /* table terminator */ 447 }; 448 449 static _soc_mv2_ser_info_t _soc_mv2_cev_ser_info[] = { 450 { _SOC_TD3_PARITY_TYPE_ECC, NULL, 0, 451 FIFO_PARITY_ERRORf, FIFO_PARITY_ERRORf, 452 CENTRAL_CTR_EVICTION_FIFOm, "CENTRAL CTR_EVICTION FIFO", 453 CENTRAL_CTR_EVICTION_FIFO_PARITY_CONTROLr, PARITY_ENf, NULL, 454 INVALIDr, INVALIDf, NULL, 455 CENTRAL_CTR_EVICTION_INTR_STATUSr, NULL, FIFO_PARITY_ERRORf, NULL, 456 INVALIDr, INVALIDf, NULL 457 }, 458 459 { _SOC_TD3_PARITY_TYPE_NONE} /* table terminator */ 460 }; 461 462 static const 463 _soc_mv2_ser_route_block_t _soc_mv2_ser_route_blocks[] = { 464 { 0, _SOC_MV2_IPIPE0_CEV_INTR, /* CEV_TO_CMIC_INTR */ 465 SOC_BLK_IPIPE, 0, CENTRAL_CTR_EVICTION_INTR_ENABLEr, 466 CENTRAL_CTR_EVICTION_INTR_STATUSr, INVALIDf, 467 _soc_mv2_cev_ser_info, 0 }, 468 { 0, 0x00000002, /* L2_MGMT_TO_CMIC_INTR */ 469 SOC_BLK_IPIPE, 0, L2_MGMT_INTR_MASKr, L2_MGMT_INTRr, SER_FIFO_NOT_EMPTYf, 470 NULL, 0 }, 471 { 0, 0x00000010, /* MMU_TO_CMIC_MEMFAIL_INTR */ 472 SOC_BLK_MMU, 0, MMU_GCFG_MISCCONFIGr, MMU_GCFG_MEM_SER_FIFO_STSr, PARITY_ENf, 473 _soc_mv2_mmu_top_ser_info, 0 }, 474 { 0, 0x00000020, /* PIPE0_EP_TO_CMIC_PERR_INTR */ 475 SOC_BLK_EPIPE, 0, EGR_INTR_ENABLEr, EGR_INTR_STATUSr, SER_FIFO_NON_EMPTYf, 476 NULL, 0 }, 477 { 0, _SOC_MV2_IPIPE0_IDB_INTR, /* PIPE0_IDB_TO_CMIC_PERR_INTR */ 478 SOC_BLK_IPIPE, 0, IP0_INTR_ENABLEr, IP0_INTR_STATUSr, INVALIDf, 479 _soc_mv2_idb_ser_info, 0 }, 480 { 0, _SOC_MV2_IPIPE0_IP_INTR, /* PIPE0_IP_TO_CMIC_PERR_INTR */ 481 SOC_BLK_IPIPE, 0, INVALIDr, INVALIDr, INVALIDf, 482 NULL, 0 }, 483 { 0, _SOC_MV2_IPIPE0_ISW4_INTR, /* PIPE0_ISW4_TO_CMIC_PERR_INTR */ 484 SOC_BLK_IPIPE, 0, ISW4_INTR_ENABLEr, ISW4_INTR_STATUSr, INVALIDf, 485 _soc_mv2_isw4_ser_info, 0 }, 486 { 1, 0x00000001, /* PM0_INTR */ 487 SOC_BLK_CLPORT, 0, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 488 _soc_mv2_pm_clp_ser_info, 0 }, 489 { 1, 0x00000002, /* PM1_INTR */ 490 SOC_BLK_CLPORT, 0, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 491 _soc_mv2_pm_clp_ser_info, 1 }, 492 { 1, 0x00000004, /* PM2_INTR */ 493 SOC_BLK_CLPORT, 0, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 494 _soc_mv2_pm_clp_ser_info, 2 }, 495 { 1, 0x00000008, /* PM3_INTR */ 496 SOC_BLK_CLPORT, 0, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 497 _soc_mv2_pm_clp_ser_info, 3 }, 498 { 1, 0x00000010, /* PM4_INTR */ 499 SOC_BLK_CLPORT, 0, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 500 _soc_mv2_pm_clp_ser_info, 4 }, 501 { 1, 0x00000020, /* PM5_INTR */ 502 SOC_BLK_CLPORT, 0, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 503 _soc_mv2_pm_clp_ser_info, 5 }, 504 { 1, 0x00000040, /* PM6_INTR */ 505 SOC_BLK_CLPORT, 0, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 506 _soc_mv2_pm_clp_ser_info, 6 }, 507 { 1, 0x00000080, /* PM7_INTR */ 508 SOC_BLK_CLPORT, 0, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 509 _soc_mv2_pm_clp_ser_info, 7 }, 510 { 1, 0x00000100, /* PM8_INTR */ 511 SOC_BLK_CLPORT, 0, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 512 _soc_mv2_pm_clp_ser_info, 8 }, 513 { 1, 0x00000200, /* PM9_INTR */ 514 SOC_BLK_CLPORT, 0, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 515 _soc_mv2_pm_clp_ser_info, 9 }, 516 { 1, 0x00000400, /* PM10_INTR */ 517 SOC_BLK_CLPORT, 0, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 518 _soc_mv2_pm_clp_ser_info, 10 }, 519 { 1, 0x00000800, /* PM11_INTR */ 520 SOC_BLK_CLPORT, 0, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 521 _soc_mv2_pm_clp_ser_info, 11 }, 522 { 1, 0x00001000, /* PM12_INTR */ 523 SOC_BLK_CLPORT, 0, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 524 _soc_mv2_pm_clp_ser_info, 12 }, 525 { 1, 0x00002000, /* PM13_INTR */ 526 SOC_BLK_CLPORT, 0, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 527 _soc_mv2_pm_clp_ser_info, 13 }, 528 { 1, 0x00004000, /* PM14_INTR */ 529 SOC_BLK_CLPORT, 0, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 530 _soc_mv2_pm_clp_ser_info, 14 }, 531 { 1, 0x00008000, /* PM15_INTR */ 532 SOC_BLK_CLPORT, 0, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 533 _soc_mv2_pm_clp_ser_info, 15 }, 534 { 1, 0x00010000, /* PM16_INTR */ 535 SOC_BLK_CLPORT, 0, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 536 _soc_mv2_pm_clp_ser_info, 16 }, 537 { 1, 0x00020000, /* PM17_INTR */ 538 SOC_BLK_CLPORT, 0, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 539 _soc_mv2_pm_clp_ser_info, 17 }, 540 { 1, 0x00040000, /* PM18_INTR */ 541 SOC_BLK_CLPORT, 0, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 542 _soc_mv2_pm_clp_ser_info, 18 }, 543 { 1, 0x00080000, /* PM19_INTR */ 544 SOC_BLK_CLPORT, 0, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 545 _soc_mv2_pm_clp_ser_info, 19 }, 546 { 1, 0x00100000, /* PM20_INTR Mgmt Port */ 547 SOC_BLK_XLPORT, 0, XLPORT_INTR_ENABLEr, XLPORT_INTR_STATUSr, INVALIDf, 548 _soc_mv2_pm_xlp_ser_info, 0 }, 549 { 0 } /* table terminator */ 550 }; 551 552 static _soc_generic_ser_info_t _soc_mv2_tcam_ser_info[] = 553 { 554 { CPU_COS_MAPm, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 555 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 556 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 557 558 /* Global view */ 559 { DST_COMPRESSIONm, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 560 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 561 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 562 563 { EFP_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 564 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 565 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 566 567 { EGR_ADAPT_1_LOGICAL_TBL_SEL_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 568 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 569 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 570 571 { EGR_ADAPT_2_LOGICAL_TBL_SEL_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 572 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 573 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 574 575 { EGR_FIELD_EXTRACTION_PROFILE_1_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 576 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 577 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 578 579 { EGR_FIELD_EXTRACTION_PROFILE_2_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 580 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 581 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 582 583 { EGR_PKT_FLOW_SELECT_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 584 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 585 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 586 587 { EGR_QOS_CTRL_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 588 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 589 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 590 591 { EGR_ZONE_0_EDITOR_CONTROL_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 592 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 593 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 594 595 { EGR_ZONE_1_EDITOR_CONTROL_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 596 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 597 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 598 599 { EGR_ZONE_2_EDITOR_CONTROL_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 600 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 601 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 602 603 { EGR_ZONE_3_EDITOR_CONTROL_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 604 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 605 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 606 607 { EGR_ZONE_4_EDITOR_CONTROL_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 608 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 609 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 610 611 { EXACT_MATCH_LOGICAL_TABLE_SELECTm, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 612 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 613 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 614 615 { FLEX_RTAG7_HASH_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 616 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 617 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 618 619 { FORWARDING_1_LOGICAL_TBL_SEL_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 620 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 621 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 622 623 { FORWARDING_2_LOGICAL_TBL_SEL_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 624 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 625 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 626 627 { FORWARDING_3_LOGICAL_TBL_SEL_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 628 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 629 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 630 631 { IFP_LOGICAL_TABLE_SELECTm, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 632 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 633 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 634 635 { IFP_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 636 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 637 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 638 639 { IFP_TCAM_WIDEm, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 640 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 641 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 642 643 { ING_SNATm, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 644 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 645 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 646 647 { IP_MULTICAST_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 648 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 649 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 650 651 { IP_PARSER0_HME_STAGE_TCAM_ONLY_0m, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 652 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 653 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 654 655 { IP_PARSER1_HME_STAGE_TCAM_ONLY_0m, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 656 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 657 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 658 659 { IP_PARSER1_HME_STAGE_TCAM_ONLY_1m, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 660 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 661 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 662 663 { IP_PARSER1_HME_STAGE_TCAM_NARROW_ONLY_2m, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 664 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 665 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 666 667 { IP_PARSER1_HME_STAGE_TCAM_ONLY_3m, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 668 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 669 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 670 671 { IP_PARSER1_HME_STAGE_TCAM_ONLY_4m, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 672 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 673 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 674 675 { IP_PARSER1_MICE_TCAM_0m, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 676 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 677 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 678 679 { IP_PARSER1_MICE_TCAM_1m, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 680 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 681 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 682 683 { IP_PARSER2_HME_STAGE_TCAM_ONLY_0m, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 684 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 685 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 686 687 { IP_PARSER2_HME_STAGE_TCAM_ONLY_1m, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 688 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 689 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 690 691 { IP_PARSER2_HME_STAGE_TCAM_NARROW_ONLY_2m, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 692 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 693 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 694 695 { IP_PARSER2_HME_STAGE_TCAM_NARROW_ONLY_3m, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 696 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 697 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 698 699 { IP_PARSER2_HME_STAGE_TCAM_ONLY_4m, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 700 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 701 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 702 703 { IP_PARSER2_MICE_TCAM_0m, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 704 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 705 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 706 707 { IP_PARSER2_MICE_TCAM_1m, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 708 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 709 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 710 711 { L2_USER_ENTRYm, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 712 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 713 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 714 715 { L3_DEFIPm, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 716 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 717 _SOC_SER_FLAG_NO_DMA | _SOC_SER_FLAG_REMAP_READ | 718 _SOC_SER_FLAG_SIZE_VERIFY | _SOC_SER_FLAG_XY_READ}, 719 720 { L3_DEFIP_PAIR_128m, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 721 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 722 _SOC_SER_FLAG_NO_DMA | _SOC_SER_FLAG_REMAP_READ | 723 _SOC_SER_FLAG_SIZE_VERIFY | _SOC_SER_FLAG_XY_READ}, 724 725 { L3_TUNNELm, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 726 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 727 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 728 729 { MY_STATION_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 730 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 731 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 732 733 { MY_STATION_TCAM_2m, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 734 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 735 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 736 737 { PHB_SELECT_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 738 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 739 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 740 741 { PKT_FLOW_SELECT_TCAM_0m, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 742 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 743 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 744 745 { PKT_FLOW_SELECT_TCAM_1m, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 746 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 747 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 748 749 { PKT_FLOW_SELECT_TCAM_2m, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 750 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 751 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 752 753 /* Global view */ 754 { SRC_COMPRESSIONm, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 755 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 756 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 757 758 { TUNNEL_ADAPT_1_LOGICAL_TBL_SEL_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 759 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 760 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 761 762 { TUNNEL_ADAPT_2_LOGICAL_TBL_SEL_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 763 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 764 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 765 766 { TUNNEL_ADAPT_3_LOGICAL_TBL_SEL_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 767 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 768 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 769 770 { TUNNEL_ADAPT_4_LOGICAL_TBL_SEL_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 771 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 772 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 773 774 { VFP_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 775 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 776 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 777 778 { VLAN_SUBNETm, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 779 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 780 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 781 782 /* End of list */ 783 { INVALIDm }, 784 }; 785 786 STATIC soc_error_t 787 _soc_mv2_ser_tcam_wrapper_enable(int unit, int enable) 788 { 789 return soc_td3_ser_tcam_wrapper_enable(unit, enable); 790 } 791 792 STATIC int 793 _soc_mv2_ser_enable_info(int unit, int block_info_idx, int inst, int port, 794 soc_reg_t group_reg, uint64 *group_rval, 795 _soc_mv2_ser_info_t *info_list, 796 soc_mem_t mem, int enable) 797 { 798 return soc_td3_ser_enable_info(unit, block_info_idx, inst, port, 799 group_reg, group_rval, 800 info_list, mem, enable); 801 } 802 803 STATIC int 804 _soc_mv2_ser_block_enable(int unit, int enable, int type, 805 soc_reg_t fifo_reset_reg, void *info) 806 { 807 uint16 pcount; 808 soc_reg_t reg, ecc1b_reg; 809 soc_field_t field, ecc1b_field; 810 soc_mem_t en_mem; 811 soc_mem_t ecc1b_en_mem; 812 int field_position = -1; 813 int ecc1b_field_position = -1; 814 uint8 flag = 0; 815 uint8 ecc1b_flag = 0; 816 _soc_reg_ser_en_info_t *reg_info; 817 _soc_mem_ser_en_info_t *mem_info; 818 _soc_bus_ser_en_info_t *bus_info; 819 _soc_buffer_ser_en_info_t *buf_info; 820 char *str_type; 821 char *str_name; 822 static char *parity_module_str[4] = {"REG", "MEM", "BUS", "BUF"}; 823 int done = 0; 824 825 reg_info = (_soc_reg_ser_en_info_t*)info; 826 mem_info = (_soc_mem_ser_en_info_t*)info; 827 bus_info = (_soc_bus_ser_en_info_t*)info; 828 buf_info = (_soc_buffer_ser_en_info_t*)info; 829 for (pcount = 0;;pcount++) { /* walk thro each entry of block_info */ 830 reg = INVALIDr; 831 ecc1b_reg = INVALIDr; 832 ecc1b_en_mem = INVALIDm; 833 en_mem = INVALIDm; 834 field = INVALIDf; 835 ecc1b_field = INVALIDf; 836 switch (type) { 837 case _SOC_SER_TYPE_REG: 838 if (reg_info[pcount].reg == INVALIDr) { 839 done = 1; 840 } else { 841 reg = reg_info[pcount].en_ctrl.ctrl_type.en_reg; 842 en_mem = reg_info[pcount].en_ctrl.ctrl_type.en_mem; 843 flag = reg_info[pcount].en_ctrl.flag_reg_mem; 844 field = reg_info[pcount].en_ctrl.en_fld; 845 field_position = reg_info[pcount].en_ctrl.en_fld_position; 846 ecc1b_reg = reg_info[pcount].ecc1b_ctrl.ctrl_type.en_reg; 847 ecc1b_en_mem = reg_info[pcount].ecc1b_ctrl.ctrl_type.en_mem; 848 ecc1b_flag = reg_info[pcount].ecc1b_ctrl.flag_reg_mem; 849 ecc1b_field = reg_info[pcount].ecc1b_ctrl.en_fld; 850 ecc1b_field_position = reg_info[pcount].ecc1b_ctrl.en_fld_position; 851 str_name = SOC_REG_NAME(unit, reg_info[pcount].reg); 852 } 853 break; 854 case _SOC_SER_TYPE_MEM: 855 if (mem_info[pcount].mem == INVALIDm) { 856 done = 1; 857 } else if (!SOC_MEM_IS_VALID(unit, mem_info[pcount].mem) || 858 (SOC_MEM_INFO(unit, mem_info[pcount].mem).flags & 859 SOC_MEM_FLAG_SER_PARITY_ENABLE_SKIP)) { 860 LOG_VERBOSE(BSL_LS_SOC_SER, (BSL_META_U(unit, 861 "skip SER enable for mem %s\n"), 862 SOC_MEM_NAME(unit, mem_info[pcount].mem))); 863 continue; 864 } else { 865 reg = mem_info[pcount].en_ctrl.ctrl_type.en_reg; 866 en_mem = mem_info[pcount].en_ctrl.ctrl_type.en_mem; 867 flag = mem_info[pcount].en_ctrl.flag_reg_mem; 868 field = mem_info[pcount].en_ctrl.en_fld; 869 field_position = mem_info[pcount].en_ctrl.en_fld_position; 870 ecc1b_reg = mem_info[pcount].ecc1b_ctrl.ctrl_type.en_reg; 871 ecc1b_en_mem = mem_info[pcount].ecc1b_ctrl.ctrl_type.en_mem; 872 ecc1b_flag = mem_info[pcount].ecc1b_ctrl.flag_reg_mem; 873 ecc1b_field = mem_info[pcount].ecc1b_ctrl.en_fld; 874 ecc1b_field_position = mem_info[pcount].ecc1b_ctrl.en_fld_position; 875 str_name = SOC_MEM_NAME(unit, mem_info[pcount].mem); 876 } 877 break; 878 case _SOC_SER_TYPE_BUS: 879 if (bus_info[pcount].en_reg == INVALIDr) { 880 done = 1; 881 } else { 882 reg = bus_info[pcount].en_reg; 883 field = bus_info[pcount].en_fld; 884 ecc1b_reg = bus_info[pcount].ecc1b_en_reg; 885 ecc1b_field = bus_info[pcount].ecc1b_en_fld; 886 ecc1b_flag = 0; 887 str_name = bus_info[pcount].bus_name; 888 flag = 0; 889 } 890 break; 891 case _SOC_SER_TYPE_BUF: 892 if (buf_info[pcount].en_reg == INVALIDr) { 893 done = 1; 894 } else { 895 reg = buf_info[pcount].en_reg; 896 field = buf_info[pcount].en_fld; 897 ecc1b_reg = buf_info[pcount].ecc1b_en_reg; 898 ecc1b_field = buf_info[pcount].ecc1b_en_fld; 899 ecc1b_flag = 0; 900 str_name = buf_info[pcount].buffer_name; 901 flag = 0; 902 } 903 break; 904 default: 905 LOG_CLI((BSL_META_U(unit, 906 "Unknown parity module " 907 "[pcount: %d].\n"), pcount)); 908 return SOC_E_INTERNAL; 909 } 910 if (done) { 911 break; 912 } else { 913 str_type = parity_module_str[type]; 914 } 915 916 en_mem = flag ? en_mem : INVALIDm; 917 reg = flag ? INVALIDr : reg; 918 ecc1b_en_mem = ecc1b_flag ? ecc1b_en_mem : INVALIDm; 919 ecc1b_reg = ecc1b_flag ? INVALIDr : ecc1b_reg; 920 921 922 SOC_IF_ERROR_RETURN(soc_td3_parity_bit_enable 923 (unit, reg, en_mem, field, field_position, enable)); 924 925 if (ecc1b_reg == ISW3_SER_CONTROL_1r && 926 ecc1b_field == HG_COUNTERS_EN_COR_ERR_RPTf) { 927 continue; 928 } 929 930 SOC_IF_ERROR_RETURN(soc_td3_parity_bit_enable 931 (unit, ecc1b_reg, ecc1b_en_mem, ecc1b_field, ecc1b_field_position, enable)); 932 933 LOG_VERBOSE(BSL_LS_SOC_SER, 934 (BSL_META_U(unit, 935 "SER enable for %s: %s\n"), 936 str_type, str_name)); 937 } /* walk through each entry of ser_info structures */ 938 939 /* reset (toggle) fifo if applicable */ 940 if (fifo_reset_reg != INVALIDr) { 941 SOC_IF_ERROR_RETURN 942 (soc_reg_field32_modify(unit, fifo_reset_reg, 943 REG_PORT_ANY, FIFO_RESETf, 1)); 944 SOC_IF_ERROR_RETURN 945 (soc_reg_field32_modify(unit, fifo_reset_reg, 946 REG_PORT_ANY, FIFO_RESETf, 0)); 947 } 948 949 return SOC_E_NONE; 950 } 951 952 int 953 soc_mv2_ser_enable_all(int unit, int enable) 954 { 955 uint8 rbi; 956 uint32 cmic_bit; 957 uint32 cmic_rval0; 958 uint32 cmic_rval1; 959 uint32 cmic_rval2; 960 int port; 961 int rv, block_info_idx; 962 uint64 rval64; 963 const _soc_mv2_ser_route_block_t *rb; 964 965 soc_iproc_getreg(unit,soc_reg_addr(unit, ICFG_CHIP_LP_INTR_ENABLE_REG0r, REG_PORT_ANY, 0), 966 &cmic_rval0); 967 soc_iproc_getreg(unit,soc_reg_addr(unit, ICFG_CHIP_LP_INTR_ENABLE_REG1r, REG_PORT_ANY, 0), 968 &cmic_rval1); 969 soc_iproc_getreg(unit,soc_reg_addr(unit, ICFG_CHIP_LP_INTR_ENABLE_REG2r, REG_PORT_ANY, 0), 970 &cmic_rval2); 971 972 soc_td3_ip_pipe_fifo_bmask[unit][0] = _SOC_MV2_IPIPE0_IP_INTR; 973 974 SOC_IF_ERROR_RETURN(_soc_mv2_ser_block_enable(unit, enable, 975 _SOC_SER_TYPE_MEM, ING_SER_FIFO_CTRLr, 976 (void*) SOC_IP_MEM_SER_INFO(unit))); 977 978 SOC_IF_ERROR_RETURN(_soc_mv2_ser_block_enable(unit, enable, 979 _SOC_SER_TYPE_MEM, EGR_SER_FIFO_CTRLr, 980 (void*) SOC_EP_MEM_SER_INFO(unit))); 981 982 SOC_IF_ERROR_RETURN(_soc_mv2_ser_block_enable(unit, enable, 983 _SOC_SER_TYPE_MEM, INVALIDr, 984 (void*) SOC_MMU_MEM_SER_INFO(unit))); 985 986 SOC_IF_ERROR_RETURN(_soc_mv2_ser_block_enable(unit, enable, 987 _SOC_SER_TYPE_REG, L2_MGMT_SER_FIFO_CTRLr, 988 (void*) SOC_IP_REG_SER_INFO(unit))); 989 990 SOC_IF_ERROR_RETURN(_soc_mv2_ser_block_enable(unit, enable, 991 _SOC_SER_TYPE_REG, INVALIDr, 992 (void*) SOC_EP_REG_SER_INFO(unit))); 993 994 #if defined(BCM_56770_A0) 995 SOC_IF_ERROR_RETURN(_soc_mv2_ser_block_enable(unit, enable, 996 _SOC_SER_TYPE_BUS, INVALIDr, 997 (void*) &_soc_bcm56770_a0_ip_bus_ser_info)); 998 999 SOC_IF_ERROR_RETURN(_soc_mv2_ser_block_enable(unit, enable, 1000 _SOC_SER_TYPE_BUS, INVALIDr, 1001 (void*) &_soc_bcm56770_a0_ep_bus_ser_info)); 1002 1003 SOC_IF_ERROR_RETURN(_soc_mv2_ser_block_enable(unit, enable, 1004 _SOC_SER_TYPE_BUF, INVALIDr, 1005 (void*) &_soc_bcm56770_a0_ip_buffer_ser_info)); 1006 1007 SOC_IF_ERROR_RETURN(_soc_mv2_ser_block_enable(unit, enable, 1008 _SOC_SER_TYPE_BUF, INVALIDr, 1009 (void*) &_soc_bcm56770_a0_ep_buffer_ser_info)); 1010 #endif 1011 1012 /* Loop through each place-and-route block entry to enable legacy 1013 style SER stuff */ 1014 for (rbi = 0; ; rbi++) { 1015 rb = &_soc_mv2_ser_route_blocks[rbi]; 1016 cmic_bit = rb->cmic_bit; 1017 port = REG_PORT_ANY; 1018 if (cmic_bit == 0) { 1019 /* End of table */ 1020 break; 1021 } 1022 1023 if (enable) { 1024 switch (rb->cmic_reg) { 1025 case 0: cmic_rval0 |= cmic_bit; break; 1026 case 1: cmic_rval1 |= cmic_bit; break; 1027 case 2: cmic_rval2 |= cmic_bit; break; 1028 default: break; 1029 } 1030 } else { 1031 switch (rb->cmic_reg) { 1032 case 0: cmic_rval0 &= ~cmic_bit; break; 1033 case 1: cmic_rval1 &= ~cmic_bit; break; 1034 case 2: cmic_rval2 &= ~cmic_bit; break; 1035 default: break; 1036 } 1037 } 1038 1039 SOC_BLOCK_ITER(unit, block_info_idx, rb->blocktype) { 1040 if (SOC_BLOCK_INFO(unit, block_info_idx).number == rb->id) { 1041 port = SOC_BLOCK_PORT(unit, block_info_idx); 1042 break; 1043 } 1044 } 1045 1046 if (rb->enable_reg != INVALIDr) { 1047 if (SOC_BLOCK_IN_LIST(SOC_REG_INFO(unit, rb->enable_reg).block, 1048 SOC_BLK_PORT) && (port == REG_PORT_ANY)) { 1049 /* This port block is not configured */ 1050 continue; 1051 } 1052 } 1053 1054 if (rb->enable_field != INVALIDf) { 1055 SOC_IF_ERROR_RETURN(soc_reg_field32_modify 1056 (unit, rb->enable_reg, port, rb->enable_field, enable)); 1057 } 1058 1059 if (rb->info != NULL) { 1060 SOC_IF_ERROR_RETURN(soc_reg_get(unit, rb->enable_reg, 1061 port, 0, &rval64)); 1062 rv = _soc_mv2_ser_enable_info(unit, block_info_idx, rb->id, port, 1063 rb->enable_reg, &rval64, 1064 rb->info, INVALIDm, enable); 1065 if (rv == SOC_E_NOT_FOUND) { 1066 continue; 1067 } else if (SOC_FAILURE(rv)) { 1068 return rv; 1069 } 1070 SOC_IF_ERROR_RETURN(soc_reg_set(unit, rb->enable_reg, 1071 port, 0, rval64)); 1072 } 1073 } 1074 1075 soc_iproc_setreg(unit, 1076 soc_reg_addr(unit, ICFG_CHIP_LP_INTR_ENABLE_REG0r, REG_PORT_ANY, 0), 1077 cmic_rval0); 1078 soc_iproc_setreg(unit, 1079 soc_reg_addr(unit, ICFG_CHIP_LP_INTR_ENABLE_REG1r, REG_PORT_ANY, 0), 1080 cmic_rval1); 1081 soc_iproc_setreg(unit, 1082 soc_reg_addr(unit, ICFG_CHIP_LP_INTR_ENABLE_REG2r, REG_PORT_ANY, 0), 1083 cmic_rval2); 1084 if (enable) { 1085 /* Write CMIC enable register */ 1086 soc_cmic_intr_enable(unit, CHIP_INTR_LOW_PRIORITY); 1087 (void)soc_ser_tcam_scan_engine_enable(unit, FALSE); 1088 (void)_soc_mv2_ser_tcam_wrapper_enable(unit, TRUE); 1089 } else { 1090 /* Write CMIC disable register */ 1091 soc_cmic_intr_disable(unit, CHIP_INTR_LOW_PRIORITY); 1092 (void)soc_ser_tcam_scan_engine_enable(unit, FALSE); 1093 (void)_soc_mv2_ser_tcam_wrapper_enable(unit, FALSE); 1094 } 1095 return SOC_E_NONE; 1096 } 1097 1098 STATIC int 1099 _soc_mv2_ser_process(int unit, int block_info_idx, int inst, int pipe, 1100 int port, soc_reg_t group_reg, uint64 group_rval, 1101 const _soc_mv2_ser_info_t *info_list, 1102 soc_block_t blocktype, 1103 char *prefix_str) 1104 { 1105 return soc_td3_ser_process(unit, block_info_idx, inst, pipe, 1106 port, group_reg, group_rval, 1107 info_list, blocktype, prefix_str); 1108 } 1109 1110 STATIC int 1111 soc_mv2_ser_process_fifo(int unit, soc_block_t blk, int pipe, 1112 char *prefix_str, int l2_mgmt_ser_fifo) 1113 { 1114 return soc_trident3_process_ser_fifo(unit, blk, pipe, 1115 prefix_str, l2_mgmt_ser_fifo); 1116 } 1117 1118 1119 STATIC int 1120 _soc_mv2_ser_process_all(int unit, int reg_type, int bit) 1121 { 1122 uint8 rbi; 1123 int port; 1124 uint32 cmic_bit; 1125 uint64 rb_rval64; 1126 const _soc_mv2_ser_route_block_t *rb; 1127 char prefix_str[10]; 1128 int block_info_idx; 1129 soc_reg_t tmp_reg; 1130 int processed_an_intr = 0; 1131 soc_stat_t *stat = SOC_STAT(unit); 1132 COMPILER_64_ZERO(rb_rval64); 1133 1134 sal_sprintf(prefix_str, "\nUnit: %d ", unit); 1135 1136 LOG_VERBOSE(BSL_LS_SOC_SER, 1137 (BSL_META_U(unit, 1138 "unit %d, _soc_mv2_ser_process_all called: reg_type %d, bit %d \n"), 1139 unit, reg_type, bit)); 1140 1141 /* Loop through each place-and-route block entry */ 1142 for (rbi = 0; ; rbi++) { 1143 port = REG_PORT_ANY; 1144 rb = &_soc_mv2_ser_route_blocks[rbi]; 1145 cmic_bit = rb->cmic_bit; 1146 if (cmic_bit == 0) { 1147 /* End of table */ 1148 break; 1149 } 1150 if (!((rb->cmic_reg == reg_type) && (cmic_bit == 1 << bit))) { 1151 continue; 1152 } 1153 if ((rb->blocktype == SOC_BLK_IPIPE || rb->blocktype == SOC_BLK_EPIPE) 1154 && (rb->cmic_bit != _SOC_MV2_IPIPE0_CEV_INTR) 1155 && (rb->cmic_bit != _SOC_MV2_IPIPE0_IDB_INTR) 1156 && (rb->cmic_bit != _SOC_MV2_IPIPE0_ISW4_INTR)) { 1157 /* New fifo style processing */ 1158 (void)soc_mv2_ser_process_fifo(unit, rb->blocktype, rb->pipe, 1159 prefix_str, 0); 1160 stat->ser_err_fifo++; 1161 processed_an_intr = 1; 1162 } else { 1163 /* Legacy processing */ 1164 SOC_BLOCK_ITER(unit, block_info_idx, rb->blocktype) { 1165 if (SOC_BLOCK_INFO(unit, block_info_idx).number == rb->id) { 1166 port = SOC_BLOCK_PORT(unit, block_info_idx); 1167 break; 1168 } 1169 } 1170 if (rb->enable_reg != INVALIDr) { 1171 if (SOC_BLOCK_IN_LIST(SOC_REG_INFO(unit, rb->enable_reg).block, 1172 SOC_BLK_PORT) && (port == REG_PORT_ANY)) { 1173 /* This port block is not configured */ 1174 LOG_ERROR(BSL_LS_SOC_SER, 1175 (BSL_META_U(unit, 1176 "unit %d SER error on disabled " 1177 "port block %d !!\n"), 1178 unit, block_info_idx)); 1179 continue; 1180 } 1181 } 1182 /* Read per route block parity status register */ 1183 if ((rb->status_reg != INVALIDr) && 1184 (rb->blocktype != SOC_BLK_MMU)){ 1185 /* Top level MMU register used to enable parity is also used 1186 * to control various other functions in MMU. 1187 * So we don't read/modify enable_reg and status_reg for MMU 1188 * It is handled in _soc_trident3_ser_process_mmu_err() 1189 */ 1190 if ((rb->blocktype == SOC_BLK_IPIPE || 1191 rb->blocktype == SOC_BLK_EPIPE) && 1192 (SOC_REG_UNIQUE_ACC(unit, rb->status_reg) != NULL)) { 1193 tmp_reg = SOC_REG_UNIQUE_ACC(unit, 1194 rb->status_reg)[rb->pipe]; 1195 } else { 1196 tmp_reg = rb->status_reg; 1197 } 1198 SOC_IF_ERROR_RETURN 1199 (soc_reg_get(unit, tmp_reg, port, 0, &rb_rval64)); 1200 1201 if (COMPILER_64_IS_ZERO(rb_rval64)) { 1202 continue; 1203 } 1204 } 1205 processed_an_intr = 1; 1206 SOC_IF_ERROR_RETURN 1207 (_soc_mv2_ser_process(unit, block_info_idx, rb->id, 1208 rb->pipe, port, rb->status_reg, 1209 rb_rval64, rb->info, rb->blocktype, 1210 prefix_str)); 1211 1212 stat->ser_err_int++; 1213 } /* legacy processing */ 1214 } 1215 if (!processed_an_intr) { 1216 LOG_WARN(BSL_LS_SOC_SER, 1217 (BSL_META_U(unit, 1218 "unit %d, reg_type %d, bit %d " 1219 "could not process interrupt !!\n"), 1220 unit, reg_type, bit)); 1221 } 1222 return SOC_E_NONE; 1223 } 1224 1225 void 1226 soc_mv2_ser_error(void *unit_vp, void *d1, void *d2, void *d3, 1227 void *d4) 1228 { 1229 int unit = PTR_TO_INT(unit_vp); 1230 1231 (void)_soc_mv2_ser_process_all(unit, PTR_TO_INT(d3), PTR_TO_INT(d4)); 1232 sal_usleep(SAL_BOOT_QUICKTURN ? 1000000 : 10000); 1233 1234 soc_ser_top_intr_reg_enable(unit, PTR_TO_INT(d3), PTR_TO_INT(d4), 1); 1235 soc_cmic_intr_enable(unit, CHIP_INTR_LOW_PRIORITY); 1236 } 1237 1238 int 1239 soc_mv2_mem_ser_control(int unit, soc_mem_t mem, int copyno, int enable) 1240 { 1241 if (enable) { 1242 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, TOP_SOFT_RESET_REGr, 1243 REG_PORT_ANY, TOP_MMU_RST_Lf, 0)); 1244 sal_usleep(1000); 1245 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, TOP_SOFT_RESET_REGr, 1246 REG_PORT_ANY, TOP_MMU_RST_Lf, 1)); 1247 sal_usleep(1000); 1248 SOC_IF_ERROR_RETURN(soc_trident3_clear_mmu_memory(unit)); 1249 } 1250 1251 if (enable) { 1252 if (soc_property_get(unit, spn_PARITY_ENABLE, TRUE)) { 1253 SOC_IF_ERROR_RETURN(soc_mv2_ser_enable_all(unit, TRUE)); 1254 } 1255 } else { 1256 SOC_IF_ERROR_RETURN(soc_mv2_ser_enable_all(unit, FALSE)); 1257 } 1258 1259 if (enable) { 1260 uint32 rval; 1261 /* Initialize MMU memory */ 1262 SOC_IF_ERROR_RETURN(WRITE_MMU_GCFG_MISCCONFIGr(unit, 0)); 1263 rval = 0; 1264 soc_reg_field_set(unit, MMU_GCFG_MISCCONFIGr, &rval, INIT_MEMf, 1); 1265 SOC_IF_ERROR_RETURN(WRITE_MMU_GCFG_MISCCONFIGr(unit, rval)); 1266 SOC_IF_ERROR_RETURN(WRITE_MMU_GCFG_MISCCONFIGr(unit, 0)); 1267 } 1268 return SOC_E_NONE; 1269 } 1270 1271 void 1272 soc_mv2_ser_register(int unit) 1273 { 1274 soc_cmic_intr_handler_t handle; 1275 1276 #ifdef INCLUDE_MEM_SCAN 1277 if (!soc_feature(unit, soc_feature_tcam_scan_engine)) { 1278 /* To access Narrow view for HME stage TCAMs */ 1279 (void)WRITE_IP_PARSER1_HME_STAGE_CONFIG_2r(unit, 0); 1280 (void)WRITE_IP_PARSER2_HME_STAGE_CONFIG_2r(unit, 0); 1281 (void)WRITE_IP_PARSER2_HME_STAGE_CONFIG_3r(unit, 0); 1282 soc_mem_scan_ser_list_register(unit, TRUE, _soc_mv2_tcam_ser_info); 1283 } 1284 #endif 1285 1286 memset(&_mv2_ser_functions, 0, sizeof(soc_ser_functions_t)); 1287 _mv2_ser_functions._soc_ser_parity_error_cmicx_intr_f = &soc_mv2_ser_error; 1288 soc_ser_function_register(unit, &_mv2_ser_functions); 1289 1290 /* Handler need to be registered for CHIP_INTR_LOW_PRIORITY */ 1291 handle.num = CHIP_INTR_LOW_PRIORITY; 1292 handle.intr_fn = soc_ser_cmicx_intr_handler; 1293 handle.intr_data = NULL; 1294 soc_cmic_intr_register(unit, &handle, 1); 1295 } 1296 1297 int 1298 soc_mv2_ser_lp_mem_info_get(int unit, soc_mem_t mem, int index, 1299 soc_mem_t *hash_mem, int *hash_index) 1300 { 1301 int bank_index, uft_index, uat_index, lp_index = 0, bank; 1302 int rv = SOC_E_NONE; 1303 1304 switch(mem) { 1305 case L2_ENTRY_LPm: 1306 hash_mem[0] = L2Xm; 1307 if (index < SOC_MV2_NUM_ENTRIES_L2_LP_BANK * SOC_MV2_NUM_BANKS_L2) { 1308 /* dedicated L2 entries(1W) */ 1309 lp_index = index; 1310 } else { 1311 /* UFT mem (1W, 2W, 4W) */ 1312 1313 /* index in uft space */ 1314 uft_index = index - (SOC_MV2_NUM_ENTRIES_L2_LP_BANK * SOC_MV2_NUM_BANKS_L2); 1315 bank = (uft_index / SOC_MV2_NUM_ENTRIES_UFT_LP_BANK); 1316 bank_index = uft_index % SOC_MV2_NUM_ENTRIES_UFT_LP_BANK; 1317 1318 if (bank_index >= 0 && bank_index < 8192) { 1319 /* 1W view - 8K entries per bank */ 1320 lp_index = bank_index + (8192 * bank) + 8192; 1321 } else if (bank_index >= 8192 && bank_index < 12288) { 1322 /* 2W view - 4K entries per bank */ 1323 return SOC_E_INTERNAL; 1324 } else if (bank_index >= 12288 && bank_index < 14336) { 1325 /* 4W view - 2K entries per bank */ 1326 return SOC_E_INTERNAL; 1327 } 1328 } 1329 hash_index[0] = lp_index * 4; 1330 break; 1331 case L3_ENTRY_LPm: 1332 if (index < SOC_MV2_NUM_ENTRIES_L3_LP_BANK * SOC_MV2_NUM_BANKS_L3) { 1333 /* dedicated L3 entries(1W, 2W, 4W) */ 1334 bank = index / SOC_MV2_NUM_ENTRIES_L3_LP_BANK; 1335 bank_index = index % SOC_MV2_NUM_ENTRIES_L3_LP_BANK; 1336 1337 if (bank_index >= 0 && bank_index < 2048) { 1338 /* 1W view - 2K entries per bank */ 1339 hash_mem[0] = L3_ENTRY_SINGLEm; 1340 lp_index = bank_index + (2048 * bank); 1341 } else if (bank_index >= 2048 && bank_index < 3072) { 1342 /* 2W view - 1K entries per bank */ 1343 hash_mem[0] = L3_ENTRY_DOUBLEm; 1344 lp_index = (bank_index - 2048) + (1024 * bank); 1345 } else if (bank_index >= 3072 && bank_index < 3584) { 1346 /* 4W view - 512 entries per bank */ 1347 hash_mem[0] = L3_ENTRY_QUADm; 1348 lp_index = (bank_index - 3072) + (512 * bank); 1349 } 1350 } else { 1351 /* UFT mem (1W, 2W, 4W) */ 1352 1353 /* index in uft space */ 1354 uft_index = index - (SOC_MV2_NUM_ENTRIES_L3_LP_BANK * SOC_MV2_NUM_BANKS_L3); 1355 bank = (uft_index / SOC_MV2_NUM_ENTRIES_UFT_LP_BANK); 1356 bank_index = uft_index % SOC_MV2_NUM_ENTRIES_UFT_LP_BANK; 1357 1358 if (bank_index >= 0 && bank_index < 8192) { 1359 /* 1W view - 8K entries per bank */ 1360 hash_mem[0] = L3_ENTRY_SINGLEm; 1361 lp_index = bank_index + (8192 * bank) + 4096; 1362 } else if (bank_index >= 8192 && bank_index < 12288) { 1363 /* 2W view - 4K entries per bank */ 1364 hash_mem[0] = L3_ENTRY_DOUBLEm; 1365 lp_index = (bank_index - 8192) + (4096 * bank) + 2048; 1366 } else if (bank_index >= 12288 && bank_index < 14336) { 1367 /* 4W view - 2K entries per bank */ 1368 hash_mem[0] = L3_ENTRY_QUADm; 1369 lp_index = (bank_index - 12288) + (2048 * bank) + 1024; 1370 } 1371 } 1372 hash_index[0] = lp_index * 4; 1373 break; 1374 case EXACT_MATCH_LPm: 1375 /* UFT mem (1W, 2W, 4W) */ 1376 bank = index / SOC_MV2_NUM_ENTRIES_UFT_LP_BANK; 1377 bank_index = index % SOC_MV2_NUM_ENTRIES_UFT_LP_BANK; 1378 1379 if (bank_index >= 0 && bank_index < 8192) { 1380 /* 1W view - 8K entries per bank */ 1381 return SOC_E_INTERNAL; 1382 } else if (bank_index >= 8192 && bank_index < 12288) { 1383 /* 2W view - 4K entries per bank */ 1384 hash_mem[0] = EXACT_MATCH_2m; 1385 lp_index = (bank_index - 8192) + (4096 * bank); 1386 } else if (bank_index >= 12288 && bank_index < 14336) { 1387 /* 4W view - 2K entries per bank */ 1388 hash_mem[0] = EXACT_MATCH_4m; 1389 lp_index = (bank_index - 12288) + (2048 * bank); 1390 } 1391 hash_index[0] = lp_index * 4; 1392 break; 1393 case MPLS_ENTRY_LPm: 1394 case VLAN_XLATE_1_LPm: 1395 case VLAN_XLATE_2_LPm: 1396 if (index < SOC_MV2_NUM_ENTRIES_UAT_16K_LP_BANK * SOC_MV2_NUM_BANKS_UAT_16K) { 1397 /* IUAT mem(1W, 2W) - 16K banks */ 1398 bank = index / SOC_MV2_NUM_ENTRIES_UAT_16K_LP_BANK; 1399 bank_index = index % SOC_MV2_NUM_ENTRIES_UAT_16K_LP_BANK; 1400 1401 if (bank_index >= 0 && bank_index < 4096) { 1402 /* 1W view - 4K entries per bank */ 1403 switch (mem) { 1404 case MPLS_ENTRY_LPm: hash_mem[0] = MPLS_ENTRY_SINGLEm; break; 1405 case VLAN_XLATE_1_LPm: hash_mem[0] = VLAN_XLATE_1_SINGLEm; break; 1406 case VLAN_XLATE_2_LPm: hash_mem[0] = VLAN_XLATE_2_SINGLEm; break; 1407 } 1408 lp_index = bank_index + (4096 * bank); 1409 } else if (bank_index >= 4096 && bank_index < 6144) { 1410 /* 2W view - 2K entries per bank */ 1411 switch (mem) { 1412 case MPLS_ENTRY_LPm: hash_mem[0] = MPLS_ENTRYm; break; 1413 case VLAN_XLATE_1_LPm: hash_mem[0] = VLAN_XLATE_1_DOUBLEm; break; 1414 case VLAN_XLATE_2_LPm: hash_mem[0] = VLAN_XLATE_2_DOUBLEm; break; 1415 } 1416 lp_index = (bank_index - 4096) + (2048 * bank); 1417 } 1418 } else { 1419 /* IUAT mem(1W, 2W) - 8K banks */ 1420 1421 /* index in 8K IUAT space */ 1422 uat_index = index - (SOC_MV2_NUM_ENTRIES_UAT_16K_LP_BANK * SOC_MV2_NUM_BANKS_UAT_16K); 1423 bank = (uat_index / SOC_MV2_NUM_ENTRIES_UAT_8K_LP_BANK); 1424 bank_index = uat_index % SOC_MV2_NUM_ENTRIES_UAT_8K_LP_BANK; 1425 1426 if (bank_index >= 0 && bank_index < 2048) { 1427 /* 1W view - 2K entries per bank */ 1428 switch (mem) { 1429 case MPLS_ENTRY_LPm: hash_mem[0] = MPLS_ENTRY_SINGLEm; break; 1430 case VLAN_XLATE_1_LPm: hash_mem[0] = VLAN_XLATE_1_SINGLEm; break; 1431 case VLAN_XLATE_2_LPm: hash_mem[0] = VLAN_XLATE_2_SINGLEm; break; 1432 } 1433 lp_index = bank_index + (2048 * bank) + 16384; 1434 } else if (bank_index >= 2048 && bank_index < 3072) { 1435 /* 2W view - 1K entries per bank */ 1436 switch (mem) { 1437 case MPLS_ENTRY_LPm: hash_mem[0] = MPLS_ENTRYm; break; 1438 case VLAN_XLATE_1_LPm: hash_mem[0] = VLAN_XLATE_1_DOUBLEm; break; 1439 case VLAN_XLATE_2_LPm: hash_mem[0] = VLAN_XLATE_2_DOUBLEm; break; 1440 } 1441 lp_index = (bank_index - 2048) + (1024 * bank) + 8192; 1442 } 1443 } 1444 hash_index[0] = lp_index * 4; 1445 break; 1446 case EGR_VLAN_XLATE_1_LPm: 1447 case EGR_VLAN_XLATE_2_LPm: 1448 /* UAT mem (1W, 2W) */ 1449 bank = index / SOC_MV2_NUM_ENTRIES_UAT_8K_LP_BANK; 1450 bank_index = index % SOC_MV2_NUM_ENTRIES_UAT_8K_LP_BANK; 1451 1452 if (bank_index >= 0 && bank_index < 2048) { 1453 /* 1W view - 2K entries per bank */ 1454 switch (mem) { 1455 case EGR_VLAN_XLATE_1_LPm: hash_mem[0] = EGR_VLAN_XLATE_1_SINGLEm; break; 1456 case EGR_VLAN_XLATE_2_LPm: hash_mem[0] = EGR_VLAN_XLATE_2_SINGLEm; break; 1457 } 1458 lp_index = bank_index + (2048 * bank); 1459 } else if (bank_index >= 2048 && bank_index < 3072) { 1460 /* 2W view - 1K entries per bank */ 1461 switch (mem) { 1462 case EGR_VLAN_XLATE_1_LPm: hash_mem[0] = EGR_VLAN_XLATE_1_DOUBLEm; break; 1463 case EGR_VLAN_XLATE_2_LPm: hash_mem[0] = EGR_VLAN_XLATE_2_DOUBLEm; break; 1464 } 1465 lp_index = (bank_index - 2048) + (1024 * bank); 1466 } 1467 hash_index[0] = lp_index * 4; 1468 break; 1469 default: 1470 rv = SOC_E_PARAM; 1471 } 1472 1473 return rv; 1474 } 1475 1476 STATIC soc_error_t 1477 _soc_mv2_ser_parity_control_reg_set(int unit, ser_test_data_t *test_data, int enable) 1478 { 1479 return soc_td3_ser_parity_control_reg_set(unit, test_data, enable); 1480 } 1481 1482 STATIC soc_error_t 1483 _soc_mv2_ser_error_injection_support(int unit, soc_mem_t mem, int pipe_target) 1484 { 1485 return soc_td3_ser_error_injection_support(unit, mem, pipe_target); 1486 } 1487 1488 STATIC soc_error_t 1489 _ser_mv2_ser_correction_info_get(int unit, ser_correction_info_t *corr_info) 1490 { 1491 return soc_td3_ser_correction_info_get(unit, corr_info); 1492 } 1493 1494 /* 1495 * Function: 1496 * soc_mv2_ser_inject_error 1497 * Purpose: 1498 * Injects an error into a single td3 memory 1499 * Parameters: 1500 * unit - (IN) Device Number 1501 * mem - (IN) The memory into which an error will be injected 1502 * pipeTarget - (IN) The pipe to use when injecting the error 1503 * index - (IN) The index into which the error will be injected. 1504 */ 1505 STATIC soc_error_t 1506 soc_mv2_ser_inject_error(int unit, uint32 flags, soc_mem_t mem, int pipe_target, 1507 int block, int index) 1508 { 1509 return soc_td3_ser_inject_or_test_mem(unit, mem, pipe_target, block, index, 1510 SER_SINGLE_INDEX, TRUE, FALSE, flags); 1511 } 1512 1513 /* 1514 * Function: 1515 * soc_mv2_ser_test_mem 1516 * Purpose: 1517 * Perform SER test on a single memory, or generate a test the user can 1518 * enter by the command line. 1519 * Parameters: 1520 * unit - (IN) Device Number 1521 * mem - (IN) The memory into which an error will be injected 1522 * test_type - (IN) How many indices to test in the passes memory 1523 * cmd - (IN) TRUE if a command-line test is desired. 1524 * Returns: 1525 * SOC_E_NONE if test passes, an error otherwise (multiple types of errors 1526 * are possible.) 1527 */ 1528 STATIC soc_error_t 1529 soc_mv2_ser_test_mem(int unit, soc_mem_t mem, _soc_ser_test_t test_type, 1530 int cmd) 1531 { 1532 return soc_td3_ser_inject_or_test_mem(unit, mem, -1, MEM_BLOCK_ANY, 0, 1533 test_type, FALSE, cmd, FALSE); 1534 } 1535 1536 STATIC void 1537 soc_mv2_ser_parity_control_check_all(int unit) 1538 { 1539 #if defined(BCM_56770_A0) 1540 (void)soc_ser_test_parity_control_check(unit, _SOC_SER_TYPE_BUS, 1541 (void*) _soc_bcm56770_a0_ip_bus_ser_info); 1542 (void)soc_ser_test_parity_control_check(unit, _SOC_SER_TYPE_BUS, 1543 (void*) _soc_bcm56770_a0_ep_bus_ser_info); 1544 (void)soc_ser_test_parity_control_check(unit, _SOC_SER_TYPE_BUF, 1545 (void*) _soc_bcm56770_a0_ip_buffer_ser_info); 1546 (void)soc_ser_test_parity_control_check(unit, _SOC_SER_TYPE_BUF, 1547 (void*) _soc_bcm56770_a0_ep_buffer_ser_info); 1548 #endif 1549 } 1550 /* 1551 * Function: 1552 * soc_mv2_ser_test 1553 * Purpose: 1554 * Tests that SER is working for all supported memories. 1555 * Parameters: 1556 * unit - (IN) Device Number 1557 * test_type - (IN) How many indices to test for each memory 1558 * Returns: 1559 * SOC_E_NONE if test passes, an error otherwise (multiple types of errors are 1560 * possible.) 1561 */ 1562 STATIC soc_error_t 1563 soc_mv2_ser_test(int unit, _soc_ser_test_t test_type) 1564 { 1565 soc_mv2_ser_parity_control_check_all(unit); 1566 return soc_td3_ser_test(unit, test_type); 1567 } 1568 1569 static soc_ser_test_functions_t _soc_mv2_ser_test_fun; 1570 1571 void 1572 soc_mv2_ser_test_register(int unit) 1573 { 1574 /*Initialize chip-specific functions for SER testing*/ 1575 memset(&_soc_mv2_ser_test_fun, 0, sizeof(soc_ser_test_functions_t)); 1576 _soc_mv2_ser_test_fun.inject_error_f = &soc_mv2_ser_inject_error; 1577 _soc_mv2_ser_test_fun.test_mem = &soc_mv2_ser_test_mem; 1578 _soc_mv2_ser_test_fun.test = &soc_mv2_ser_test; 1579 _soc_mv2_ser_test_fun.parity_control = &_soc_mv2_ser_parity_control_reg_set; 1580 _soc_mv2_ser_test_fun.injection_support = &_soc_mv2_ser_error_injection_support; 1581 _soc_mv2_ser_test_fun.correction_info_get = &_ser_mv2_ser_correction_info_get; 1582 soc_ser_test_functions_register(unit, &_soc_mv2_ser_test_fun); 1583 } 1584 1585 #endif /* BCM_MAVERICK2_SUPPORT */