katana2.c (1079985B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: katana2.c 8 * Purpose: 9 * Requires: 10 */ 11 12 13 #include <shared/bsl.h> 14 15 #include <sal/core/boot.h> 16 #include <shared/bsl.h> 17 #include <soc/katana2.h> 18 #include <soc/trident.h> 19 #include <soc/bradley.h> 20 #include <soc/drv.h> 21 #include <soc/scache.h> 22 #include <soc/error.h> 23 #include <soc/debug.h> 24 #include <soc/mem.h> 25 #include <soc/hash.h> 26 #include <soc/shmoo_ddr40.h> 27 #include <soc/phy/ddr40.h> 28 #include <soc/mspi.h> 29 #include <soc/phyreg.h> 30 #include <soc/mmu_config.h> 31 #include <soc/soc_ser_log.h> 32 #include <soc/phy/phyctrl.h> 33 34 #ifdef BCM_CMICM_SUPPORT 35 #include <soc/cmicm.h> 36 #endif 37 38 #ifdef BCM_KATANA2_SUPPORT 39 #include <bcm_int/esw/katana2.h> 40 #include <bcm_int/esw/switch.h> 41 #include <soc/katana.h> 42 /* Min/Max threshold settings - 33 Gbps */ 43 #define KT2_QUEUE_FLUSH_RATE_MANTISSA 1023 44 #define KT2_QUEUE_FLUSH_RATE_EXP 14 45 #define KT2_QUEUE_FLUSH_BURST_MANTISSA 124 46 #define KT2_QUEUE_FLUSH_BURST_EXP 14 47 #define KT2_QUEUE_FLUSH_CYCLE_SEL 0 48 49 /* Min/Max threshold settings - 2 Gbps */ 50 #define KT2_QUEUE_MIN_RATE_MANTISSA 1 51 #define KT2_QUEUE_MIN_RATE_EXP 0 52 #define KT2_QUEUE_MIN_BURST_MANTISSA 0 53 #define KT2_QUEUE_MIN_BURST_EXP 0 54 #define KT2_QUEUE_MIN_CYCLE_SEL 4 55 56 #define _SOC_KT2_DEFIP_MAX_TCAMS 16 57 #define _SOC_KT2_DEFIP_TCAM_DEPTH 1024 58 #define KT2_MAX_NUMBER_INTERLEAVED_PKTS 512 59 #ifdef BCM_KATANA2_SUPPORT 60 #include <soc/saber2.h> 61 #endif 62 #ifdef BCM_METROLITE_SUPPORT 63 #include <soc/metrolite.h> 64 #endif 65 66 #ifdef BCM_WARM_BOOT_SUPPORT 67 68 #define KT2_MAX_TDM_SLOTS_VER_1_1 128 69 #define KT2_MAX_TDM_SLOTS 256 70 #define KT2_MAX_WARPCORE_BLOCKS 2 71 #define BCM_WB_VERSION_1_1 SOC_SCACHE_VERSION(1,1) 72 #define BCM_WB_VERSION_1_2 SOC_SCACHE_VERSION(1,2) 73 #define BCM_WB_DEFAULT_VERSION BCM_WB_VERSION_1_2 74 75 static uint8 scache_begin_magic_number[]={0xAA,0xBB,0xCC,0xDD}; 76 static uint8 scache_end_magic_number[]={0xDD,0xCC,0xBB,0xAA}; 77 static bcm56450_tdm_info_t kt2_scache_tdm_info[SOC_MAX_NUM_DEVICES]={{0}}; 78 static uint32 kt2_scache_tdm[SOC_MAX_NUM_DEVICES][KT2_MAX_TDM_SLOTS]={{0}}; 79 static uint32 kt2_scache_speed[SOC_MAX_NUM_DEVICES][KT2_MAX_PHYSICAL_PORTS]={{0}}; 80 static soc_port_details_t kt2_scache_port_details[SOC_MAX_NUM_DEVICES] 81 [KT2_MAX_PHYSICAL_PORTS+1]={{{0}}}; 82 static uint8 kt2_scache_portgroup[SOC_MAX_NUM_DEVICES][KT2_MAX_MXQPORTS_PER_BLOCK * 83 KT2_MAX_WARPCORE_BLOCKS]={{0}}; 84 #endif 85 86 extern sal_mutex_t cosq_sync_lock[SOC_MAX_NUM_DEVICES]; 87 #define KT2_COSQ_LOCK(unit) do { \ 88 if (cosq_sync_lock[unit]) { \ 89 sal_mutex_take(cosq_sync_lock[unit], \ 90 sal_mutex_FOREVER); \ 91 } \ 92 } while (0) 93 #define KT2_COSQ_UNLOCK(unit) do { \ 94 if (cosq_sync_lock[unit]) { \ 95 sal_mutex_give(cosq_sync_lock[unit]); \ 96 } \ 97 } while (0) 98 99 100 extern int _bcm_kt_ipmc_port_ext_queue_count(int unit, int ipmc_id, bcm_port_t port); 101 extern int _bcm_kt2_ipmc_subscriber_egress_queue_ext_set(int unit, int port, int ipmc_id, int ext_mem_enable); 102 extern int _soc_katana2_mmu_init_phase4_port(int unit,int port); 103 104 static int flexio_lock; 105 /* 106 * STATIC Macro: 107 * SOC_FLEXIO_LOCK 108 * Purpose: 109 * Lock take the flex status mutex 110 */ 111 #define SOC_FLEXIO_LOCK flexio_lock = sal_splhi() 112 /* 113 * STATIC Macro: 114 * SOC_FLEXIO_UNLOCK 115 * Purpose: 116 * Unlock flex status mutex 117 */ 118 #define SOC_FLEXIO_UNLOCK sal_spl(flexio_lock) 119 120 int flex_io_operation_busy[SOC_MAX_NUM_DEVICES] = {0}; 121 122 int _soc_kt2_config_get(int unit, 123 soc_kt2_sku_config_info_t *conf); 124 int soc_flex_io_operation_status_set(int unit, int value); 125 STATIC int soc_flex_io_operation_status_get(int unit, 126 int *flex_io_operation_status); 127 typedef enum { 128 _SOC_PARITY_TYPE_NONE, 129 _SOC_PARITY_TYPE_GENERIC, 130 _SOC_PARITY_TYPE_PARITY, 131 _SOC_PARITY_TYPE_ECC, 132 _SOC_PARITY_TYPE_HASH, 133 _SOC_PARITY_TYPE_EDATABUF, 134 _SOC_PARITY_TYPE_COUNTER, 135 _SOC_PARITY_TYPE_SER, 136 _SOC_PARITY_INFO_TYPE_OAM 137 } _soc_kt2_parity_info_type_t; 138 139 typedef enum { 140 _SOC_KT2_MMU_SUBBLOCK_IPCTR, 141 _SOC_KT2_MMU_SUBBLOCK_ADM, 142 _SOC_KT2_MMU_SUBBLOCK_RDE, 143 _SOC_KT2_MMU_SUBBLOCK_CI5, 144 _SOC_KT2_MMU_SUBBLOCK_CI4, 145 _SOC_KT2_MMU_SUBBLOCK_CI3, 146 _SOC_KT2_MMU_SUBBLOCK_MEM1, 147 _SOC_KT2_MMU_SUBBLOCK_INTFI, 148 _SOC_KT2_MMU_SUBBLOCK_INTFI_ECC, 149 _SOC_KT2_MMU_SUBBLOCK_E2EFC, 150 _SOC_KT2_MMU_SUBBLOCK_ITE, 151 _SOC_KT2_MMU_SUBBLOCK_ITE_CFG, 152 _SOC_KT2_MMU_SUBBLOCK_THDI, 153 _SOC_KT2_MMU_SUBBLOCK_ENQ_CFG, 154 _SOC_KT2_MMU_SUBBLOCK_ENQ, 155 _SOC_KT2_MMU_SUBBLOCK_ENQ_FAP, 156 _SOC_KT2_MMU_SUBBLOCK_CI2, 157 _SOC_KT2_MMU_SUBBLOCK_CI1, 158 _SOC_KT2_MMU_SUBBLOCK_CI0, 159 _SOC_KT2_MMU_SUBBLOCK_WRED, 160 _SOC_KT2_MMU_SUBBLOCK_THDO_STATUS1, 161 _SOC_KT2_MMU_SUBBLOCK_THDO_STATUS2, 162 _SOC_KT2_MMU_SUBBLOCK_RQE_SER, 163 _SOC_KT2_MMU_SUBBLOCK_RQE_EXTQ, 164 _SOC_KT2_MMU_SUBBLOCK_EMC, 165 _SOC_KT2_MMU_SUBBLOCK_DEQ, 166 _SOC_KT2_MMU_SUBBLOCK_CTR, 167 _SOC_KT2_MMU_SUBBLOCK_CFAPI, 168 _SOC_KT2_MMU_SUBBLOCK_CFAPE, 169 _SOC_KT2_MMU_SUBBLOCK_CCP, 170 _SOC_KT2_MMU_SUBBLOCK_AGING_INT, 171 _SOC_KT2_MMU_SUBBLOCK_AGING_EXT, 172 _SOC_KT2_MMU_SUBBLOCK_LLS, 173 _SOC_KT2_MMU_SUBBLOCK_LLS_PORT, 174 _SOC_KT2_MMU_SUBBLOCK_LLS_L0_ECC, 175 _SOC_KT2_MMU_SUBBLOCK_LLS_UPD2, 176 _SOC_KT2_MMU_SUBBLOCK_LLS_L1_ECC, 177 _SOC_KT2_MMU_SUBBLOCK_LLS_L2_ECC, 178 _SOC_KT2_MMU_SUBBLOCK_LLS_MISC_ECC, 179 _SOC_KT2_MMU_SUBBLOCK_QSTRUCT, 180 _SOC_KT2_MMU_SUBBLOCK_TOQ, 181 _SOC_KT2_MMU_SUBBLOCK_MAX 182 } _soc_katana2_mmu_subblock_type_t; 183 184 typedef enum { 185 _SOC_KT2_MMU_LVL2_SUBBLOCK_EMC_ERROR_0, 186 _SOC_KT2_MMU_LVL2_SUBBLOCK_EMC_ERROR_1, 187 _SOC_KT2_MMU_LVL2_SUBBLOCK_EMC_ERROR_2, 188 _SOC_KT2_MMU_LVL2_SUBBLOCK_EMC_ERROR_3, 189 _SOC_KT2_MMU_LVL2_SUBBLOCK_DEQ_ERROR_0, 190 _SOC_KT2_MMU_LVL2_SUBBLOCK_DEQ_ERROR_1, 191 _SOC_KT2_MMU_LVL2_SUBBLOCK_DEQ_ERROR_2, 192 _SOC_KT2_MMU_LVL2_SUBBLOCK_DEQ_ERROR_3, 193 _SOC_KT2_MMU_LVL2_SUBBLOCK_DEQ_ERROR_4, 194 _SOC_KT2_MMU_LVL2_SUBBLOCK_QSTRUCT_QENTRY_U, 195 _SOC_KT2_MMU_LVL2_SUBBLOCK_QSTRUCT_QENTRY_L, 196 _SOC_KT2_MMU_LVL2_SUBBLOCK_QSTRUCT_QBLOCK, 197 _SOC_KT2_MMU_LVL2_SUBBLOCK_QSTRUCT_FAP, 198 _SOC_KT2_MMU_LVL2_SUBBLOCK_TOQ_ERROR_2, 199 _SOC_KT2_MMU_LVL2_SUBBLOCK_TOQ_ERROR_1, 200 _SOC_KT2_MMU_LVL2_SUBBLOCK_MAX 201 } _soc_katana2_mmu_lvl2_subblock_type_t; 202 203 typedef struct _soc_katana2_parity_reg_s { 204 soc_reg_t reg; 205 char *mem_str; 206 } _soc_katana2_parity_reg_t; 207 208 typedef struct _soc_katana2_parity_info_s { 209 _soc_kt2_parity_info_type_t type; 210 struct _soc_katana2_parity_info_s *info; 211 int id; 212 soc_field_t group_reg_enable_field; 213 soc_field_t group_reg_status_field; 214 soc_mem_t mem; 215 char *mem_str; 216 soc_reg_t reg; 217 soc_reg_t enable_reg; 218 soc_field_t enable_field; 219 soc_reg_t intr_status_reg; 220 _soc_katana2_parity_reg_t *intr_status_reg_list; 221 soc_reg_t nack_status_reg; 222 _soc_katana2_parity_reg_t *nack_status_reg_list; 223 } _soc_katana2_parity_info_t; 224 225 typedef struct _soc_katana2_parity_route_block_s { 226 uint32 cmic_bit; 227 soc_block_t blocktype; 228 soc_reg_t enable_reg; 229 soc_reg_t status_reg; 230 _soc_katana2_parity_info_t *info; 231 uint8 id; 232 } _soc_katana2_parity_route_block_t; 233 234 typedef struct _soc_katana2_mmu_sub_block_leaf_info_s { 235 uint32 intr_bit; /* bit position in intr register of 236 sub block */ 237 soc_field_t status_field; /* INTR field of a leaf block */ 238 soc_field_t enable_field; /* MASK field of a leaf block */ 239 } _soc_katana2_mmu_sub_block_leaf_info_t; 240 241 typedef struct _soc_katana2_mmu_sub_block_internal_info_s { 242 uint32 intr_bit; /* bit position in level 1 sub block INTR and 243 INTR_MASK */ 244 _soc_katana2_mmu_lvl2_subblock_type_t lvl2_sub_block; /* level 2 sub block 245 */ 246 soc_field_t internal_enable_field; /* field in 1evel 1 sub block INTR 247 MASK register */ 248 soc_field_t internal_status_field; /* field in level 1 sub block INTR 249 register */ 250 soc_reg_t leaf_enable_reg; /* intr mask register for level 2 sub 251 block */ 252 soc_reg_t leaf_status_reg; /* intr register for level 2 sub block 253 */ 254 _soc_katana2_mmu_sub_block_leaf_info_t *info; 255 } _soc_katana2_mmu_sub_block_internal_info_t; 256 257 typedef struct _soc_katana2_mmu_sub_block_one_level_s { 258 uint32 mmu_bit; /* bit position in MMU_INTR and MMU_INTR_MASK 259 */ 260 _soc_katana2_mmu_subblock_type_t mmu_sub_block; /* level 1 sub block */ 261 soc_field_t mmu_enable_field; /* field in MMU_INTR_MASK */ 262 soc_field_t mmu_status_field; /* field in MMU_INTR */ 263 soc_reg_t leaf_enable_reg; /* intr mask register for sub block */ 264 soc_reg_t leaf_status_reg; /* intr register for sub block */ 265 _soc_katana2_mmu_sub_block_leaf_info_t *info; /* list of memory instances */ 266 } _soc_katana2_mmu_sub_block_one_level_t; 267 268 typedef struct _soc_katana2_mmu_sub_block_two_level_s { 269 uint32 mmu_bit; /* bit position in MMU_INTR and MMU_INTR_MASK */ 270 _soc_katana2_mmu_subblock_type_t mmu_sub_block; /* level 1 sub block */ 271 soc_field_t mmu_enable_field; /* field in MMU_INTR_MASK */ 272 soc_field_t mmu_status_field; /* field in MMU_INTR */ 273 soc_reg_t internal_enable_reg; /* intr mask for sub block */ 274 soc_reg_t internal_status_reg; /* intr for sub block */ 275 _soc_katana2_mmu_sub_block_internal_info_t *info; 276 } _soc_katana2_mmu_sub_block_two_level_t; 277 278 279 STATIC _soc_katana2_parity_reg_t _soc_katana2_egr_vlan_xlate_intr_reg[] = { 280 { EGR_VLAN_XLATE_PARITY_STATUS_INTR_0r, NULL }, 281 { EGR_VLAN_XLATE_PARITY_STATUS_INTR_1r, NULL } }; 282 283 STATIC _soc_katana2_parity_reg_t _soc_katana2_egr_vlan_xlate_nack_reg[] = { 284 { EGR_VLAN_XLATE_PARITY_STATUS_NACK_0r, NULL }, 285 { EGR_VLAN_XLATE_PARITY_STATUS_NACK_1r, NULL } }; 286 287 STATIC _soc_katana2_parity_reg_t _soc_katana2_vlan_xlate_intr_reg[] = { 288 { VLAN_XLATE_PARITY_STATUS_INTR_0r, NULL }, 289 { VLAN_XLATE_PARITY_STATUS_INTR_1r, NULL } }; 290 291 STATIC _soc_katana2_parity_reg_t _soc_katana2_vlan_xlate_nack_reg[] = { 292 { VLAN_XLATE_PARITY_STATUS_NACK_0r, NULL }, 293 { VLAN_XLATE_PARITY_STATUS_NACK_1r, NULL } }; 294 295 STATIC _soc_katana2_parity_reg_t _soc_katana2_mpls_entry_intr_reg[] = { 296 { MPLS_ENTRY_PARITY_STATUS_INTR_0r, NULL }, 297 { MPLS_ENTRY_PARITY_STATUS_INTR_1r, NULL } }; 298 299 STATIC _soc_katana2_parity_reg_t _soc_katana2_mpls_entry_nack_reg[] = { 300 { MPLS_ENTRY_PARITY_STATUS_NACK_0r, NULL }, 301 { MPLS_ENTRY_PARITY_STATUS_NACK_1r, NULL } }; 302 303 STATIC _soc_katana2_parity_reg_t _soc_katana2_l3_entry_only_intr_reg[] = { 304 { L3_ENTRY_PARITY_STATUS_INTR_0r, NULL }, 305 { L3_ENTRY_PARITY_STATUS_INTR_1r, NULL } }; 306 307 STATIC _soc_katana2_parity_reg_t _soc_katana2_l3_entry_only_nack_reg[] = { 308 { L3_ENTRY_PARITY_STATUS_NACK_0r, NULL }, 309 { L3_ENTRY_PARITY_STATUS_NACK_1r, NULL } }; 310 311 STATIC _soc_katana2_parity_reg_t _soc_katana2_l2_entry_only_intr_reg[] = { 312 { L2_ENTRY_PARITY_STATUS_INTR_0r, NULL }, 313 { L2_ENTRY_PARITY_STATUS_INTR_1r, NULL } }; 314 315 STATIC _soc_katana2_parity_reg_t _soc_katana2_l2_entry_only_nack_reg[] = { 316 { L2_ENTRY_PARITY_STATUS_NACK_0r, NULL }, 317 { L2_ENTRY_PARITY_STATUS_NACK_1r, NULL } }; 318 319 STATIC _soc_katana2_parity_reg_t _soc_katana2_egr_mp_group_intr_reg[] = { 320 { EGR_MP_GROUP_PARITY_STATUS_INTR_0r, NULL }, 321 { EGR_MP_GROUP_PARITY_STATUS_INTR_1r, NULL } }; 322 323 STATIC _soc_katana2_parity_reg_t _soc_katana2_egr_mp_group_nack_reg[] = { 324 { EGR_MP_GROUP_PARITY_STATUS_NACK_0r, NULL }, 325 { EGR_MP_GROUP_PARITY_STATUS_NACK_1r, NULL } }; 326 327 STATIC _soc_katana2_parity_info_t _soc_katana2_xport_parity_info[] = { 328 { _SOC_PARITY_TYPE_ECC, NULL, 0, 329 TXFIFO_MEM_ERRf, 330 TXFIFO_MEM_ERRf, 331 INVALIDm, "TX FIFO", 332 INVALIDr, 333 INVALIDr, INVALIDf, 334 XPORT_TXFIFO_MEM_ECC_STATUSr, NULL, 335 INVALIDr, NULL }, 336 { _SOC_PARITY_TYPE_ECC, NULL, 0, 337 MIB_TSC_MEM0_ERRf, 338 MIB_TSC_MEM0_ERRf, 339 INVALIDm, "TX MIB MEM0", 340 INVALIDr, 341 INVALIDr, INVALIDf, 342 XPORT_MIB_TSC_MEM0_ECC_STATUSr, NULL, 343 INVALIDr, NULL }, 344 { _SOC_PARITY_TYPE_ECC, NULL, 0, 345 MIB_TSC_MEM1_ERRf, 346 MIB_TSC_MEM1_ERRf, 347 INVALIDm, "TX MIB MEM1", 348 INVALIDr, 349 INVALIDr, INVALIDf, 350 XPORT_MIB_TSC_MEM1_ECC_STATUSr, NULL, 351 INVALIDr, NULL }, 352 { _SOC_PARITY_TYPE_ECC, NULL, 0, 353 MIB_TSC_MEM2_ERRf, 354 MIB_TSC_MEM2_ERRf, 355 INVALIDm, "TX MIB MEM2", 356 INVALIDr, 357 INVALIDr, INVALIDf, 358 XPORT_MIB_TSC_MEM2_ECC_STATUSr, NULL, 359 INVALIDr, NULL }, 360 { _SOC_PARITY_TYPE_ECC, NULL, 0, 361 MIB_TSC_MEM3_ERRf, 362 MIB_TSC_MEM3_ERRf, 363 INVALIDm, "TX MIB MEM3", 364 INVALIDr, 365 INVALIDr, INVALIDf, 366 XPORT_MIB_TSC_MEM3_ECC_STATUSr, NULL, 367 INVALIDr, NULL }, 368 { _SOC_PARITY_TYPE_ECC, NULL, 0, 369 MIB_RSC_MEM0_ERRf, 370 MIB_RSC_MEM0_ERRf, 371 INVALIDm, "RX MIB MEM0", 372 INVALIDr, 373 INVALIDr, INVALIDf, 374 XPORT_MIB_RSC_MEM0_ECC_STATUSr, NULL, 375 INVALIDr, NULL }, 376 { _SOC_PARITY_TYPE_ECC, NULL, 0, 377 MIB_RSC_MEM1_ERRf, 378 MIB_RSC_MEM1_ERRf, 379 INVALIDm, "RX MIB MEM1", 380 INVALIDr, 381 INVALIDr, INVALIDf, 382 XPORT_MIB_RSC_MEM1_ECC_STATUSr, NULL, 383 INVALIDr, NULL }, 384 { _SOC_PARITY_TYPE_ECC, NULL, 0, 385 MIB_RSC_MEM2_ERRf, 386 MIB_RSC_MEM2_ERRf, 387 INVALIDm, "RX MIB MEM2", 388 INVALIDr, 389 INVALIDr, INVALIDf, 390 XPORT_MIB_RSC_MEM2_ECC_STATUSr, NULL, 391 INVALIDr, NULL }, 392 { _SOC_PARITY_TYPE_ECC, NULL, 0, 393 MIB_RSC_MEM3_ERRf, 394 MIB_RSC_MEM3_ERRf, 395 INVALIDm, "RX MIB MEM3", 396 INVALIDr, 397 INVALIDr, INVALIDf, 398 XPORT_MIB_RSC_MEM3_ECC_STATUSr, NULL, 399 INVALIDr, NULL }, 400 { _SOC_PARITY_TYPE_ECC, NULL, 0, 401 MIB_RSC_MEM4_ERRf, 402 MIB_RSC_MEM4_ERRf, 403 INVALIDm, "RX MIB MEM4", 404 INVALIDr, 405 INVALIDr, INVALIDf, 406 XPORT_MIB_RSC_MEM4_ECC_STATUSr, NULL, 407 INVALIDr, NULL }, 408 { _SOC_PARITY_TYPE_ECC, NULL, 0, 409 RXFIFO_MEM0_ERRf, 410 RXFIFO_MEM0_ERRf, 411 INVALIDm, "RX FIFO MEM0", 412 INVALIDr, 413 INVALIDr, INVALIDf, 414 XPORT_RXFIFO_MEM0_ECC_STATUSr, NULL, 415 INVALIDr, NULL }, 416 { _SOC_PARITY_TYPE_ECC, NULL, 0, 417 RXFIFO_MEM1_ERRf, 418 RXFIFO_MEM1_ERRf, 419 INVALIDm, "RX FIFO MEM1", 420 INVALIDr, 421 INVALIDr, INVALIDf, 422 XPORT_RXFIFO_MEM1_ECC_STATUSr, NULL, 423 INVALIDr, NULL }, 424 { _SOC_PARITY_TYPE_ECC, NULL, 0, 425 RXFIFO_MEM2_ERRf, 426 RXFIFO_MEM2_ERRf, 427 INVALIDm, "RX FIFO MEM2", 428 INVALIDr, 429 INVALIDr, INVALIDf, 430 XPORT_RXFIFO_MEM2_ECC_STATUSr, NULL, 431 INVALIDr, NULL }, 432 { _SOC_PARITY_TYPE_ECC, NULL, 0, 433 RXFIFO_MEM3_ERRf, 434 RXFIFO_MEM3_ERRf, 435 INVALIDm, "RX FIFO MEM3", 436 INVALIDr, 437 INVALIDr, INVALIDf, 438 XPORT_RXFIFO_MEM3_ECC_STATUSr, NULL, 439 INVALIDr, NULL }, 440 { _SOC_PARITY_TYPE_ECC, NULL, 0, 441 RXFIFO_MEM4_ERRf, 442 RXFIFO_MEM4_ERRf, 443 INVALIDm, "RX FIFO MEM4", 444 INVALIDr, 445 INVALIDr, INVALIDf, 446 XPORT_RXFIFO_MEM4_ECC_STATUSr, NULL, 447 INVALIDr, NULL }, 448 { _SOC_PARITY_TYPE_NONE } /* table terminator */ 449 }; 450 451 STATIC _soc_katana2_parity_info_t _soc_katana2_rxlp_parity_info[] = { 452 453 { _SOC_PARITY_TYPE_ECC, NULL, 0, 454 MAIN_BUFF_ECC_INTR_ENABLEf, 455 MAIN_BUFF_ECC_INTR_STATUSf, 456 INVALIDm, "main data buffer", 457 INVALIDr, 458 RXLP_ECC_PARITY_CONTROLr, DATABUF_ECC_ENf, 459 RXLP_DATABUF_ECC_STATUSr, NULL, 460 INVALIDr, NULL }, 461 462 { _SOC_PARITY_TYPE_ECC, NULL, 0, 463 CTRL_BUFFER_ECC_INTR_ENABLEf, 464 CTRL_BUFF_ECC_INTR_STATUSf, 465 INVALIDm, "ctrl data buffer", 466 INVALIDr, 467 RXLP_ECC_PARITY_CONTROLr, CTRLBUF_ECC_ENf, 468 RXLP_CTRLBUF_ECC_STATUSr, NULL, 469 INVALIDr, NULL }, 470 471 { _SOC_PARITY_TYPE_ECC, NULL, 0, 472 RESIDUAL_CRC_ECC_INTR_ENABLEf, 473 RESIDUAL_CRC_ECC_INTR_STATUSf, 474 INVALIDm, "Residual CRC Buffer ", 475 INVALIDr, 476 RXLP_ECC_PARITY_CONTROLr, RESIDUALCRC_ECC_ENf, 477 RXLP_RESIDUAL_CRC_ECC_STATUSr, NULL, 478 INVALIDr, NULL }, 479 480 { _SOC_PARITY_TYPE_ECC, NULL, 0, 481 IARB_BUF_ECC_INTR_ENABLEf, 482 IARB_BUF_ECC_INTR_STATUSf, 483 INVALIDm, "IARB Buffer", 484 INVALIDr, 485 RXLP_ECC_PARITY_CONTROLr, IARBBUF_ECC_ENf, 486 RXLP_IARBBUF_ECC_STATUSr, NULL, 487 INVALIDr, NULL }, 488 489 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 490 TRIGGER_MEM_PARITY_ERR_INTR_ENABLEf, 491 TRIGGER_MEM_PARITY_ERRf, 492 INVALIDm, "IARB Buffer", 493 INVALIDr, 494 RXLP_ECC_PARITY_CONTROLr, TRIGGERS_MEM_PARITY_ENf, 495 RXLP_TRIGGER_MEM_PARITY_STATUSr, NULL, 496 RXLP_TRIGGER_MEM_PARITY_STATUS_NACKr, NULL }, 497 498 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 499 COUNTER_MEM_PARITY_ERR_INTR_ENABLEf, 500 COUNTER_MEM_PARITY_ERRf, 501 INVALIDm, "IARB Buffer", 502 INVALIDr, 503 RXLP_ECC_PARITY_CONTROLr, COUNTERS_MEM_PARITY_ENf, 504 RXLP_COUNTER_MEM_PARITY_STATUSr, NULL, 505 RXLP_COUNTER_MEM_PARITY_STATUS_NACKr, NULL }, 506 { _SOC_PARITY_TYPE_NONE } /* table terminator */ 507 }; 508 509 STATIC _soc_katana2_parity_info_t _soc_katana2_txlp_parity_info[] = { 510 511 { _SOC_PARITY_TYPE_ECC, NULL, 0, 512 INT2EXT_PARITY_ERRf, 513 INT2EXT_PARITY_ERRf, 514 INVALIDm, "INT2EXT-MAP-TABLE", 515 INVALIDr, 516 TXLP_ECC_PARITY_CONTROLr, INT2EXT_STREAM_MAP_PARITY_ENf, 517 TXLP_DATABUF_ECC_STATUSr, NULL, 518 INVALIDr, NULL }, 519 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 520 RESICRCBUF_PARITY_ERRf, 521 RESICRCBUF_PARITY_ERRf, 522 INVALIDm, "RESIDUAL-CRC-BUFFER", 523 INVALIDr, 524 TXLP_ECC_PARITY_CONTROLr, RESICRCBUF_PARITY_ENf, 525 TXLP_RESICRCBUF_PARITY_STATUSr, NULL, 526 INVALIDr, NULL }, 527 { _SOC_PARITY_TYPE_ECC, NULL, 0, 528 RESIDATABUF_ECC_ERRf, 529 RESIDATABUF_ECC_ERRf, 530 INVALIDm, "RESIDUAL-DATA-BUFFER", 531 INVALIDr, 532 TXLP_ECC_PARITY_CONTROLr, RESIDATABUF_ECC_ENf, 533 TXLP_RESIDATABUF_ECC_STATUSr, NULL, 534 INVALIDr, NULL }, 535 { _SOC_PARITY_TYPE_ECC, NULL, 0, 536 DATABUF_ECC_ERRf, 537 DATABUF_ECC_ERRf, 538 INVALIDm, "MAIN-DATA-BUFFER.", 539 INVALIDr, 540 TXLP_ECC_PARITY_CONTROLr, DATABUF_ECC_ENf, 541 TXLP_DATABUF_ECC_STATUSr, NULL, 542 INVALIDr, NULL }, 543 { _SOC_PARITY_TYPE_ECC, NULL, 0, 544 CTRLBUF_ECC_ERRf, 545 CTRLBUF_ECC_ERRf, 546 INVALIDm, "MAIN-CTRL-BUFFER.", 547 INVALIDr, 548 TXLP_ECC_PARITY_CONTROLr, CTRLBUF_ECC_ENf, 549 TXLP_CTRLBUF_ECC_STATUSr, NULL, 550 INVALIDr, NULL }, 551 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 552 TRIGGER_MEM_PARITY_ERRf, 553 TRIGGER_MEM_PARITY_ERRf, 554 INVALIDm, "TXLP_DEBUG_COUNTER[0-7]", 555 INVALIDr, 556 TXLP_ECC_PARITY_CONTROLr, TRIGGERS_MEM_PARITY_ENf, 557 TXLP_TRIGGER_MEM_PARITY_STATUSr, NULL, 558 TXLP_TRIGGER_MEM_PARITY_STATUS_NACKr, NULL }, 559 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 560 COUNTER_MEM_PARITY_ERRf, 561 COUNTER_MEM_PARITY_ERRf, 562 INVALIDm, "TXLP_DEBUG_COUNTER[8-11]", 563 INVALIDr, 564 TXLP_ECC_PARITY_CONTROLr, COUNTERS_MEM_PARITY_ENf, 565 TXLP_COUNTER_MEM_PARITY_STATUSr, NULL, 566 TXLP_COUNTER_MEM_PARITY_STATUS_NACKr, NULL }, 567 { _SOC_PARITY_TYPE_NONE } /* table terminator */ 568 }; 569 570 571 STATIC 572 _soc_katana2_mmu_sub_block_leaf_info_t _soc_katana2_mmu_sb_ipctr_parity_info[] = { 573 /* MMU_IPCTR_ECC_ERROR_0 */ 574 { 0x0020, CTXT_COUNTER_0_CORRECTED_ERRORf, 575 CTXT_COUNTER_0_CORRECTED_ERROR_DISINTf}, 576 { 0x0010, CTXT_COUNTER_0_UNCORRECTED_ERRORf, 577 CTXT_COUNTER_0_UNCORRECTED_ERROR_DISINTf}, 578 { 0x0008, PG_COUNTER_1_CORRECTED_ERRORf, 579 PG_COUNTER_1_CORRECTED_ERROR_DISINTf}, 580 { 0x0004, PG_COUNTER_1_UNCORRECTED_ERRORf, 581 PG_COUNTER_1_UNCORRECTED_ERROR_DISINTf}, 582 { 0x0002, PG_COUNTER_0_CORRECTED_ERRORf, 583 PG_COUNTER_0_CORRECTED_ERROR_DISINTf}, 584 { 0x0001, PG_COUNTER_0_UNCORRECTED_ERRORf, 585 PG_COUNTER_0_UNCORRECTED_ERROR_DISINTf}, 586 { 0 } /* table terminator */ 587 }; 588 589 STATIC 590 _soc_katana2_mmu_sub_block_leaf_info_t _soc_katana2_mmu_sb_adm_parity_info[] = { 591 /* MMU_ADM_ECC_ERROR_0 */ 592 { 0x0008, SRC_CTXT_DB_CORRECTED_ERRORf, 593 SRC_CTXT_DB_CORRECTED_ERROR_DISINTf}, 594 { 0x0004, SRC_CTXT_DB_UNCORRECTED_ERRORf, 595 SRC_CTXT_DB_UNCORRECTED_ERROR_ERROR_DISINTf}, 596 { 0x0002, QUEUE_DB_CORRECTED_ERRORf, 597 QUEUE_DB_CORRECTED_ERROR_DISINTf}, 598 { 0x0001, QUEUE_DB_UNCORRECTED_ERRORf, 599 QUEUE_DB_UNCORRECTED_ERROR_DISINTf}, 600 { 0 } /* table terminator */ 601 }; 602 603 STATIC 604 _soc_katana2_mmu_sub_block_leaf_info_t _soc_katana2_mmu_sb_rde_parity_info[] = { 605 /* RDE_SER_STATUS */ 606 { 0x1000000, ITE_REL_FIFO_FULLf, 607 ITE_REL_FIFO_FULL_MASKf}, 608 { 0x800000, PQE_CELL_FIFO_FULLf, 609 PQE_CELL_FIFO_FULL_MASKf}, 610 { 0x400000, DEQ_CELL_FIFO_FULLf, 611 DEQ_CELL_FIFO_FULL_MASKf}, 612 { 0x200000, RPFAP_DUPLICATE_PTRf, 613 RPFAP_DUPLICATE_PTR_MASKf}, 614 { 0x100000, TXQ_FLL_EMPTYf, 615 TXQ_FLL_EMPTY_MASKf}, 616 { 0x0FFC00, ECC_1B_BITMAPf, 617 ECC_1B_MASKf}, 618 { 0x3FF, ECC_2B_BITMAPf, 619 ECC_2B_MASKf}, 620 { 0 } /* table terminator */ 621 }; 622 623 STATIC 624 _soc_katana2_mmu_sub_block_leaf_info_t _soc_katana2_mmu_sb_lls_parity_info[] = { 625 /* LLS_ERROR */ 626 { 0x80000000, VBS_ILLEGAL_CONFIG_INTERRUPTf, 627 VBS_ILLEGAL_CONFIG_INTERRUPT_DISINTf}, 628 { 0x40000000, S1_MAX_SHAPER_REFRESH_CYCLE_INTERRUPTf, 629 S1_MAX_SHAPER_REFRESH_CYCLE_INTERRUPT_DISINTf}, 630 { 0x20000000, ENQ_TO_ACTIVE_QUEUE_VIOL_INTERRUPTf, 631 ENQ_TO_ACTIVE_QUEUE_VIOL_INTERRUPT_DISINTf}, 632 { 0x10000000, PORT_1_IN_4_DEQ_VIOL_INTERRUPTf, 633 PORT_1_IN_4_DEQ_VIOL_INTERRUPT_DISINTf}, 634 { 0x8000000, S0_MAX_SHAPER_REFRESH_CYCLE_INTERRUPTf, 635 S0_MAX_SHAPER_REFRESH_CYCLE_INTERRUPT_DISINTf}, 636 { 0x4000000, PORT_MAX_SHAPER_REFRESH_CYCLE_INTERRUPTf, 637 PORT_MAX_SHAPER_REFRESH_CYCLE_INTERRUPT_DISINTf}, 638 { 0x2000000, L0_MAX_SHAPER_REFRESH_CYCLE_INTERRUPTf, 639 L0_MAX_SHAPER_REFRESH_CYCLE_INTERRUPT_DISINTf}, 640 { 0x1000000, L1_MAX_SHAPER_REFRESH_CYCLE_INTERRUPTf, 641 L1_MAX_SHAPER_REFRESH_CYCLE_INTERRUPT_DISINTf}, 642 { 0x800000, L2_UPPER_MAX_SHAPER_REFRESH_CYCLE_INTERRUPTf, 643 L2_UPPER_MAX_SHAPER_REFRESH_CYCLE_INTERRUPT_DISINTf}, 644 { 0x400000, L2_LOWER_MAX_SHAPER_REFRESH_CYCLE_INTERRUPTf, 645 L2_LOWER_MAX_SHAPER_REFRESH_CYCLE_INTERRUPT_DISINTf}, 646 { 0x200000, L0_MIN_SHAPER_REFRESH_CYCLE_INTERRUPTf, 647 L0_MIN_SHAPER_REFRESH_CYCLE_INTERRUPT_DISINTf}, 648 { 0x100000, L1_MIN_SHAPER_REFRESH_CYCLE_INTERRUPTf, 649 L1_MIN_SHAPER_REFRESH_CYCLE_INTERRUPT_DISINTf}, 650 { 0x80000, L2_UPPER_MIN_SHAPER_REFRESH_CYCLE_INTERRUPTf, 651 L2_UPPER_MIN_SHAPER_REFRESH_CYCLE_INTERRUPT_DISINTf}, 652 { 0x40000, L2_LOWER_MIN_SHAPER_REFRESH_CYCLE_INTERRUPTf, 653 L2_LOWER_MIN_SHAPER_REFRESH_CYCLE_INTERRUPT_DISINTf}, 654 655 /* The following fields need to be left with reset value in 656 * lls_error_mask as recommended. These fields are used only 657 * for debugging */ 658 659 /* 660 { 0x20000, MAX_SHAPER_BUCKET_UNDERFLOW_PORTf, 661 MAX_SHAPER_BUCKET_UNDERFLOW_PORT_DISINTf}, 662 { 0x10000, MAX_SHAPER_BUCKET_UNDERFLOW_L0f, 663 MAX_SHAPER_BUCKET_UNDERFLOW_L0_DISINTf}, 664 { 0x8000, MAX_SHAPER_BUCKET_UNDERFLOW_L1f, 665 MAX_SHAPER_BUCKET_UNDERFLOW_L1_DISINTf}, 666 { 0x4000, MAX_SHAPER_BUCKET_UNDERFLOW_L2_UPPERf, 667 MAX_SHAPER_BUCKET_UNDERFLOW_L2_UPPER_DISINTf}, 668 { 0x2000, MAX_SHAPER_BUCKET_UNDERFLOW_L2_LOWERf, 669 MAX_SHAPER_BUCKET_UNDERFLOW_L2_LOWER_DISINTf}, 670 { 0x1000, MIN_SHAPER_BUCKET_UNDERFLOW_L0f, 671 MIN_SHAPER_BUCKET_UNDERFLOW_L0_DISINTf}, 672 { 0x0800, MIN_SHAPER_BUCKET_UNDERFLOW_L1f, 673 MIN_SHAPER_BUCKET_UNDERFLOW_L1_DISINTf}, 674 { 0x0400, MIN_SHAPER_BUCKET_UNDERFLOW_L2_UPPERf, 675 MIN_SHAPER_BUCKET_UNDERFLOW_L2_UPPER_DISINTf}, 676 { 0x0200, MIN_SHAPER_BUCKET_UNDERFLOW_L2_LOWERf, 677 MIN_SHAPER_BUCKET_UNDERFLOW_L2_LOWER_DISINTf}, 678 */ 679 { 0x0100, MAX_SHAPER_BUCKET_OVERFLOW_PORTf, 680 MAX_SHAPER_BUCKET_OVERFLOW_PORT_DISINTf}, 681 { 0x0080, MAX_SHAPER_BUCKET_OVERFLOW_L0f, 682 MAX_SHAPER_BUCKET_OVERFLOW_L0_DISINTf}, 683 { 0x0040, MAX_SHAPER_BUCKET_OVERFLOW_L1f, 684 MAX_SHAPER_BUCKET_OVERFLOW_L1_DISINTf}, 685 { 0x0020, MAX_SHAPER_BUCKET_OVERFLOW_L2_UPPERf, 686 MAX_SHAPER_BUCKET_OVERFLOW_L2_UPPER_DISINTf}, 687 { 0x0010, MAX_SHAPER_BUCKET_OVERFLOW_L2_LOWERf, 688 MAX_SHAPER_BUCKET_OVERFLOW_L2_LOWER_DISINTf}, 689 { 0x0008, MIN_SHAPER_BUCKET_OVERFLOW_L0f, 690 MIN_SHAPER_BUCKET_OVERFLOW_L0_DISINTf}, 691 { 0x0004, MIN_SHAPER_BUCKET_OVERFLOW_L1f, 692 MIN_SHAPER_BUCKET_OVERFLOW_L1_DISINTf}, 693 { 0x0002, MIN_SHAPER_BUCKET_OVERFLOW_L2_UPPERf, 694 MIN_SHAPER_BUCKET_OVERFLOW_L2_UPPER_DISINTf}, 695 { 0x0001, MIN_SHAPER_BUCKET_OVERFLOW_L2_LOWERf, 696 MIN_SHAPER_BUCKET_OVERFLOW_L2_LOWER_DISINTf}, 697 { 0 } /* table terminator */ 698 }; 699 700 STATIC 701 _soc_katana2_mmu_sub_block_leaf_info_t _soc_katana2_mmu_sb_lls2_parity_info[] = { 702 /* LLS_ERROR2 */ 703 { 0x0080, ENQ_PORT_FROM_S1_ID_MULTIPLE_MATCH_ERRORf, 704 ENQ_PORT_FROM_S1_ID_MULTIPLE_MATCH_ERRORf}, 705 { 0x0040, ENQ_PORT_FROM_S1_ID_S1_NOT_ON_PORT_ERRORf, 706 ENQ_PORT_FROM_S1_ID_S1_NOT_ON_PORT_ERROR_DISINTf}, 707 { 0x0020, PORT_L2_COUNT_OVERFLOWf, 708 PORT_L2_COUNT_OVERFLOW_DISINTf}, 709 { 0x0010, PORT_L2_COUNT_UNDERRUNf, 710 PORT_L2_COUNT_UNDERRUN_DISINTf}, 711 { 0x0008, MAX_SHAPER_BUCKET_OVERFLOW_S1f, 712 MAX_SHAPER_BUCKET_OVERFLOW_S1f}, 713 { 0x0004, MAX_SHAPER_BUCKET_UNDERFLOW_S1f, 714 MAX_SHAPER_BUCKET_UNDERFLOW_S1f}, 715 { 0x0002, MAX_SHAPER_BUCKET_OVERFLOW_S0f, 716 MAX_SHAPER_BUCKET_OVERFLOW_S0_DISINTf}, 717 { 0x0001, MAX_SHAPER_BUCKET_UNDERFLOW_S0f, 718 MAX_SHAPER_BUCKET_UNDERFLOW_S0_DISINTf}, 719 { 0 } /* table terminator */ 720 }; 721 722 /* LLS_ERROR_UPD2 */ 723 STATIC _soc_katana2_mmu_sub_block_leaf_info_t 724 _soc_katana2_mmu_sb_lls_upd2_parity_info [] = { 725 { 0x1000, UPD2_PORT_1_IN_4_VIOLATED_INTERRUPTf, 726 UPD2_PORT_1_IN_4_VIOLATED_INTERRUPT_DISINTf}, 727 { 0x0800, UPD2_S1_ERROR_UNDERRUN_INTERRUPTf, 728 UPD2_S1_ERROR_UNDERRUN_INTERRUPT_DISINTf}, 729 { 0x0400, UPD2_S1_ERROR_OVERFLOW_INTERRUPTf, 730 UPD2_S1_ERROR_OVERFLOW_INTERRUPT_DISINTf}, 731 { 0x0200, UPD2_S0_ERROR_UNDERRUN_INTERRUPTf, 732 UPD2_S0_ERROR_UNDERRUN_INTERRUPT_DISINTf}, 733 { 0x0100, UPD2_S0_ERROR_OVERFLOW_INTERRUPTf, 734 UPD2_S0_ERROR_OVERFLOW_INTERRUPT_DISINTf}, 735 { 0x0080, UPD2_PORT_ERROR_UNDERRUN_INTERRUPTf, 736 UPD2_PORT_ERROR_UNDERRUN_INTERRUPT_DISINTf}, 737 { 0x0040, UPD2_PORT_ERROR_OVERFLOW_INTERRUPTf, 738 UPD2_PORT_ERROR_OVERFLOW_INTERRUPT_DISINTf}, 739 { 0x0020, UPD2_L0_ERROR_UNDERRUN_INTERRUPTf, 740 UPD2_L0_ERROR_UNDERRUN_INTERRUPT_DISINTf}, 741 { 0x0010, UPD2_L0_ERROR_OVERFLOW_INTERRUPTf, 742 UPD2_L0_ERROR_OVERFLOW_INTERRUPT_DISINTf}, 743 { 0x0008, UPD2_L1_ERROR_UNDERRUN_INTERRUPTf, 744 UPD2_L1_ERROR_UNDERRUN_INTERRUPT_DISINTf}, 745 { 0x0004, UPD2_L1_ERROR_OVERFLOW_INTERRUPTf, 746 UPD2_L1_ERROR_OVERFLOW_INTERRUPT_DISINTf}, 747 { 0x0002, UPD2_L2_ERROR_UNDERRUN_INTERRUPTf, 748 UPD2_L2_ERROR_UNDERRUN_INTERRUPT_DISINTf}, 749 { 0x0001, UPD2_L2_ERROR_OVERFLOW_INTERRUPTf, 750 UPD2_L2_ERROR_OVERFLOW_INTERRUPT_DISINTf}, 751 { 0 } /* table terminator */ 752 }; 753 754 STATIC _soc_katana2_mmu_sub_block_leaf_info_t 755 _soc_katana2_mmu_sb_lls_port_parity_info [] = { 756 /* LLS_PORT_ECC_ERROR */ 757 { 0x8000, DB_S1_TAILS_CORRECTED_ERRORf, 758 DB_S1_TAILS_CORRECTED_ERROR_DISINTf}, 759 { 0x4000, DB_S1_TAILS_UNCORRECTED_ERRORf, 760 DB_S1_TAILS_UNCORRECTED_ERROR_DISINTf}, 761 { 0x2000, DB_S1_SHAPER_BUCKET_CORRECTED_ERRORf, 762 DB_S1_SHAPER_BUCKET_CORRECTED_ERROR_DISINTf}, 763 { 0x1000, DB_S1_SHAPER_BUCKET_UNCORRECTED_ERRORf, 764 DB_S1_SHAPER_BUCKET_UNCORRECTED_ERROR_DISINTf}, 765 { 0x0800, DB_S1_SHAPER_CONFIG_C_CORRECTED_ERRORf, 766 DB_S1_SHAPER_CONFIG_C_CORRECTED_ERROR_DISINTf}, 767 { 0x0400, DB_S1_SHAPER_CONFIG_C_UNCORRECTED_ERRORf, 768 DB_S1_SHAPER_CONFIG_C_UNCORRECTED_ERROR_DISINTf}, 769 { 0x0200, DB_S0_SHAPER_BUCKET_CORRECTED_ERRORf, 770 DB_S0_SHAPER_BUCKET_CORRECTED_ERROR_DISINTf}, 771 { 0x0100, DB_S0_SHAPER_BUCKET_UNCORRECTED_ERRORf, 772 DB_S0_SHAPER_BUCKET_UNCORRECTED_ERROR_DISINTf}, 773 { 0x0080, DB_S0_SHAPER_CONFIG_C_CORRECTED_ERRORf, 774 DB_S0_SHAPER_CONFIG_C_CORRECTED_ERROR_DISINTf}, 775 { 0x0040, DB_S0_SHAPER_CONFIG_C_UNCORRECTED_ERRORf, 776 DB_S0_SHAPER_CONFIG_C_UNCORRECTED_ERROR_DISINTf}, 777 { 0x0020, DB_PORT_TDM_CORRECTED_ERRORf, 778 DB_PORT_TDM_CORRECTED_ERROR_DISINTf}, 779 { 0x0010, DB_PORT_TDM_UNCORRECTED_ERRORf, 780 DB_PORT_TDM_UNCORRECTED_ERROR_DISINTf}, 781 { 0x0008, DB_PORT_SHAPER_CONFIG_C_CORRECTED_ERRORf, 782 DB_PORT_SHAPER_CONFIG_C_CORRECTED_ERROR_DISINTf}, 783 { 0x0004, DB_PORT_SHAPER_CONFIG_C_UNCORRECTED_ERRORf, 784 DB_PORT_SHAPER_CONFIG_C_UNCORRECTED_ERROR_DISINTf}, 785 { 0x0002, DB_PORT_WERR_MAX_SC_CORRECTED_ERRORf, 786 DB_PORT_WERR_MAX_SC_CORRECTED_ERROR_DISINTf}, 787 { 0x0001, DB_PORT_WERR_MAX_SC_UNCORRECTED_ERRORf, 788 DB_PORT_WERR_MAX_SC_UNCORRECTED_ERROR_DISINTf}, 789 { 0 } /* table terminator */ 790 791 }; 792 793 STATIC _soc_katana2_mmu_sub_block_leaf_info_t 794 _soc_katana2_mmu_sb_lls_l0_ecc_parity_info [] = { 795 /* LLS_L0_ECC_ERROR1 */ 796 { 0x8000000, DB_L0_MIN_NEXT_CORRECTED_ERRORf, 797 DB_L0_MIN_NEXT_CORRECTED_ERROR_DISINTf}, 798 { 0x4000000, DB_L0_MIN_NEXT_UNCORRECTED_ERRORf, 799 DB_L0_MIN_NEXT_UNCORRECTED_ERROR_DISINTf}, 800 { 0x2000000, DB_L0_PARENT_CORRECTED_ERRORf, 801 DB_L0_PARENT_CORRECTED_ERROR_DISINTf}, 802 { 0x1000000, DB_L0_PARENT_UNCORRECTED_ERRORf, 803 DB_L0_PARENT_UNCORRECTED_ERROR_DISINTf}, 804 { 0x800000, DB_L0_CONFIG_CORRECTED_ERRORf, 805 DB_L0_CONFIG_CORRECTED_ERROR_DISINTf}, 806 { 0x400000, DB_L0_CONFIG_UNCORRECTED_ERRORf, 807 DB_L0_CONFIG_UNCORRECTED_ERROR_DISINTf}, 808 { 0x200000, DB_L0_MIN_CONFIG_C_CORRECTED_ERRORf, 809 DB_L0_MIN_CONFIG_C_CORRECTED_ERROR_DISINTf}, 810 { 0x100000, DB_L0_MIN_CONFIG_C_UNCORRECTED_ERRORf, 811 DB_L0_MIN_CONFIG_C_UNCORRECTED_ERROR_DISINTf}, 812 { 0x80000, DB_L0_PARENT_STATE_CORRECTED_ERRORf, 813 DB_L0_PARENT_STATE_CORRECTED_ERROR_DISINTf}, 814 { 0x40000, DB_L0_PARENT_STATE_UNCORRECTED_ERRORf, 815 DB_L0_PARENT_STATE_UNCORRECTED_ERROR_DISINTf}, 816 { 0x20000, DB_L0_HEADS_TAILS_CORRECTED_ERRORf, 817 DB_L0_HEADS_TAILS_CORRECTED_ERROR_DISINTf}, 818 { 0x10000, DB_L0_HEADS_TAILS_UNCORRECTED_ERRORf, 819 DB_L0_HEADS_TAILS_UNCORRECTED_ERROR_DISINTf}, 820 { 0x8000, DB_L0_WERR_MAX_SC_CORRECTED_ERRORf, 821 DB_L0_WERR_MAX_SC_CORRECTED_ERROR_DISINTf}, 822 { 0x4000, DB_L0_WERR_MAX_SC_UNCORRECTED_ERRORf, 823 DB_L0_WERR_MAX_SC_UNCORRECTED_ERROR_DISINTf}, 824 { 0x2000, DB_L0_MIN_BUCKET_C_CORRECTED_ERRORf, 825 DB_L0_MIN_BUCKET_C_CORRECTED_ERROR_DISINTf}, 826 { 0x1000, DB_L0_MIN_BUCKET_C_UNCORRECTED_ERRORf, 827 DB_L0_MIN_BUCKET_C_UNCORRECTED_ERROR_DISINTf}, 828 { 0x0800, DB_L0_CHILD_STATE1_CORRECTED_ERRORf, 829 DB_L0_CHILD_STATE1_CORRECTED_ERROR_DISINTf}, 830 { 0x0400, DB_L0_CHILD_STATE1_UNCORRECTED_ERRORf, 831 DB_L0_CHILD_STATE1_UNCORRECTED_ERROR_DISINTf}, 832 { 0x0200, DB_L0_CHILD_WEIGHT_CFG_CNT_CORRECTED_ERRORf, 833 DB_L0_CHILD_WEIGHT_CFG_CNT_CORRECTED_ERROR_DISINTf}, 834 { 0x0100, DB_L0_CHILD_WEIGHT_CFG_CNT_UNCORRECTED_ERRORf, 835 DB_L0_CHILD_WEIGHT_CFG_CNT_UNCORRECTED_ERROR_DISINTf}, 836 { 0x0080, DB_L0_WERR_NEXT_CORRECTED_ERRORf, 837 DB_L0_WERR_NEXT_CORRECTED_ERROR_DISINTf}, 838 { 0x0040, DB_L0_WERR_NEXT_UNCORRECTED_ERRORf, 839 DB_L0_WERR_NEXT_UNCORRECTED_ERROR_DISINTf}, 840 { 0x0020, DB_L0_EF_NEXT_CORRECTED_ERRORf, 841 DB_L0_EF_NEXT_CORRECTED_ERROR_DISINTf}, 842 { 0x0010, DB_L0_EF_NEXT_UNCORRECTED_ERRORf, 843 DB_L0_EF_NEXT_UNCORRECTED_ERROR_DISINTf}, 844 { 0x0008, DB_L0_SHAPER_CONFIG_C_CORRECTED_ERRORf, 845 DB_L0_SHAPER_CONFIG_C_CORRECTED_ERROR_DISINTf}, 846 { 0x0004, DB_L0_SHAPER_CONFIG_C_UNCORRECTED_ERRORf, 847 DB_L0_SHAPER_CONFIG_C_UNCORRECTED_ERROR_DISINTf}, 848 { 0x0002, DB_L0_SHAPER_BUCKET_C_CORRECTED_ERRORf, 849 DB_L0_SHAPER_BUCKET_C_CORRECTED_ERROR_DISINTf}, 850 { 0x0001, DB_L0_SHAPER_BUCKET_C_UNCORRECTED_ERRORf, 851 DB_L0_SHAPER_BUCKET_C_UNCORRECTED_ERROR_DISINTf}, 852 { 0 } /* table terminator */ 853 854 }; 855 856 STATIC _soc_katana2_mmu_sub_block_leaf_info_t 857 _soc_katana2_mmu_sb_lls_l1_ecc_parity_info [] = { 858 /* LLS_L1_ECC_ERROR1 */ 859 { 0x8000000, DB_L1_MIN_NEXT_CORRECTED_ERRORf, 860 DB_L1_MIN_NEXT_CORRECTED_ERROR_DISINTf}, 861 { 0x4000000, DB_L1_MIN_NEXT_UNCORRECTED_ERRORf, 862 DB_L1_MIN_NEXT_UNCORRECTED_ERROR_DISINTf}, 863 { 0x2000000, DB_L1_PARENT_CORRECTED_ERRORf, 864 DB_L1_PARENT_CORRECTED_ERROR_DISINTf}, 865 { 0x1000000, DB_L1_PARENT_UNCORRECTED_ERRORf, 866 DB_L1_PARENT_UNCORRECTED_ERROR_DISINTf}, 867 { 0x800000, DB_L1_CONFIG_CORRECTED_ERRORf, 868 DB_L1_CONFIG_CORRECTED_ERROR_DISINTf}, 869 { 0x400000, DB_L1_CONFIG_UNCORRECTED_ERRORf, 870 DB_L1_CONFIG_UNCORRECTED_ERROR_DISINTf}, 871 { 0x200000, DB_L1_MIN_CONFIG_C_CORRECTED_ERRORf, 872 DB_L1_MIN_CONFIG_C_CORRECTED_ERROR_DISINTf}, 873 { 0x100000, DB_L1_MIN_CONFIG_C_UNCORRECTED_ERRORf, 874 DB_L1_MIN_CONFIG_C_UNCORRECTED_ERROR_DISINTf}, 875 { 0x80000, DB_L1_PARENT_STATE_CORRECTED_ERRORf, 876 DB_L1_PARENT_STATE_CORRECTED_ERROR_DISINTf}, 877 { 0x40000, DB_L1_PARENT_STATE_UNCORRECTED_ERRORf, 878 DB_L1_PARENT_STATE_UNCORRECTED_ERROR_DISINTf}, 879 { 0x20000, DB_L1_HEADS_TAILS_CORRECTED_ERRORf, 880 DB_L1_HEADS_TAILS_CORRECTED_ERROR_DISINTf}, 881 { 0x10000, DB_L1_HEADS_TAILS_UNCORRECTED_ERRORf, 882 DB_L1_HEADS_TAILS_UNCORRECTED_ERROR_DISINTf}, 883 { 0x8000, DB_L1_WERR_MAX_SC_CORRECTED_ERRORf, 884 DB_L1_WERR_MAX_SC_CORRECTED_ERROR_DISINTf}, 885 { 0x4000, DB_L1_WERR_MAX_SC_UNCORRECTED_ERRORf, 886 DB_L1_WERR_MAX_SC_UNCORRECTED_ERROR_DISINTf}, 887 { 0x2000, DB_L1_MIN_BUCKET_C_CORRECTED_ERRORf, 888 DB_L1_MIN_BUCKET_C_CORRECTED_ERROR_DISINTf}, 889 { 0x1000, DB_L1_MIN_BUCKET_C_UNCORRECTED_ERRORf, 890 DB_L1_MIN_BUCKET_C_UNCORRECTED_ERROR_DISINTf}, 891 { 0x0800, DB_L1_CHILD_STATE1_CORRECTED_ERRORf, 892 DB_L1_CHILD_STATE1_CORRECTED_ERROR_DISINTf}, 893 { 0x0400, DB_L1_CHILD_STATE1_UNCORRECTED_ERRORf, 894 DB_L1_CHILD_STATE1_UNCORRECTED_ERROR_DISINTf}, 895 { 0x0200, DB_L1_CHILD_WEIGHT_CFG_CNT_CORRECTED_ERRORf, 896 DB_L1_CHILD_WEIGHT_CFG_CNT_CORRECTED_ERROR_DISINTf}, 897 { 0x0100, DB_L1_CHILD_WEIGHT_CFG_CNT_UNCORRECTED_ERRORf, 898 DB_L1_CHILD_WEIGHT_CFG_CNT_UNCORRECTED_ERROR_DISINTf}, 899 { 0x0080, DB_L1_WERR_NEXT_CORRECTED_ERRORf, 900 DB_L1_WERR_NEXT_CORRECTED_ERROR_DISINTf}, 901 { 0x0040, DB_L1_WERR_NEXT_UNCORRECTED_ERRORf, 902 DB_L1_WERR_NEXT_UNCORRECTED_ERROR_DISINTf}, 903 { 0x0020, DB_L1_EF_NEXT_CORRECTED_ERRORf, 904 DB_L1_EF_NEXT_CORRECTED_ERROR_DISINTf}, 905 { 0x0010, DB_L1_EF_NEXT_UNCORRECTED_ERRORf, 906 DB_L1_EF_NEXT_UNCORRECTED_ERROR_DISINTf}, 907 { 0x0008, DB_L1_SHAPER_CONFIG_C_CORRECTED_ERRORf, 908 DB_L1_SHAPER_CONFIG_C_CORRECTED_ERROR_DISINTf}, 909 { 0x0004, DB_L1_SHAPER_CONFIG_C_UNCORRECTED_ERRORf, 910 DB_L1_SHAPER_CONFIG_C_UNCORRECTED_ERROR_DISINTf}, 911 { 0x0002, DB_L1_SHAPER_BUCKET_C_CORRECTED_ERRORf, 912 DB_L1_SHAPER_BUCKET_C_CORRECTED_ERROR_DISINTf}, 913 { 0x0001, DB_L1_SHAPER_BUCKET_C_UNCORRECTED_ERRORf, 914 DB_L1_SHAPER_BUCKET_C_UNCORRECTED_ERROR_DISINTf}, 915 { 0 } /* table terminator */ 916 }; 917 918 STATIC _soc_katana2_mmu_sub_block_leaf_info_t 919 _soc_katana2_mmu_sb_lls_l2_ecc_parity_info [] = { 920 /* LLS_L2_ECC_ERROR1 */ 921 { 0x2000000, DB_L2_MIN_CONFIG_UPPER_C_CORRECTED_ERRORf, 922 DB_L2_MIN_CONFIG_UPPER_C_CORRECTED_ERROR_DISINTf}, 923 { 0x1000000, DB_L2_MIN_CONFIG_UPPER_C_UNCORRECTED_ERRORf, 924 DB_L2_MIN_CONFIG_UPPER_C_UNCORRECTED_ERROR_DISINTf}, 925 { 0x800000, DB_L2_MIN_BUCKET_UPPER_C_CORRECTED_ERRORf, 926 DB_L2_MIN_BUCKET_UPPER_C_CORRECTED_ERROR_DISINTf}, 927 { 0x400000, DB_L2_MIN_BUCKET_UPPER_C_UNCORRECTED_ERRORf, 928 DB_L2_MIN_BUCKET_UPPER_C_UNCORRECTED_ERROR_DISINTf}, 929 { 0x200000, DB_L2_SHAPER_CONFIG_UPPER_C_CORRECTED_ERRORf, 930 DB_L2_SHAPER_CONFIG_UPPER_C_CORRECTED_ERROR_DISINTf}, 931 { 0x100000, DB_L2_SHAPER_CONFIG_UPPER_C_UNCORRECTED_ERRORf, 932 DB_L2_SHAPER_CONFIG_UPPER_C_UNCORRECTED_ERROR_DISINTf}, 933 { 0x80000, DB_L2_SHAPER_BUCKET_UPPER_C_CORRECTED_ERRORf, 934 DB_L2_SHAPER_BUCKET_UPPER_C_CORRECTED_ERROR_DISINTf}, 935 { 0x40000, DB_L2_SHAPER_BUCKET_UPPER_C_UNCORRECTED_ERRORf, 936 DB_L2_SHAPER_BUCKET_UPPER_C_UNCORRECTED_ERROR_DISINTf}, 937 { 0x20000, DB_L2_MIN_CONFIG_LOWER_C_CORRECTED_ERRORf, 938 DB_L2_MIN_CONFIG_LOWER_C_CORRECTED_ERROR_DISINTf}, 939 { 0x10000, DB_L2_MIN_CONFIG_LOWER_C_UNCORRECTED_ERRORf, 940 DB_L2_MIN_CONFIG_LOWER_C_UNCORRECTED_ERROR_DISINTf}, 941 { 0x8000, DB_L2_MIN_BUCKET_LOWER_C_CORRECTED_ERRORf, 942 DB_L2_MIN_BUCKET_LOWER_C_CORRECTED_ERROR_DISINTf}, 943 { 0x4000, DB_L2_MIN_BUCKET_LOWER_C_UNCORRECTED_ERRORf, 944 DB_L2_MIN_BUCKET_LOWER_C_UNCORRECTED_ERROR_DISINTf}, 945 { 0x2000, DB_L2_SHAPER_CONFIG_LOWER_C_CORRECTED_ERRORf, 946 DB_L2_SHAPER_CONFIG_LOWER_C_CORRECTED_ERROR_DISINTf}, 947 { 0x1000, DB_L2_SHAPER_CONFIG_LOWER_C_UNCORRECTED_ERRORf, 948 DB_L2_SHAPER_CONFIG_LOWER_C_UNCORRECTED_ERROR_DISINTf}, 949 { 0x0800, DB_L2_SHAPER_BUCKET_LOWER_C_CORRECTED_ERRORf, 950 DB_L2_SHAPER_BUCKET_LOWER_C_CORRECTED_ERROR_DISINTf}, 951 { 0x0400, DB_L2_SHAPER_BUCKET_LOWER_C_UNCORRECTED_ERRORf, 952 DB_L2_SHAPER_BUCKET_LOWER_C_UNCORRECTED_ERROR_DISINTf}, 953 { 0x0200, DB_L2_CHILD_STATE1_CORRECTED_ERRORf, 954 DB_L2_CHILD_STATE1_CORRECTED_ERROR_DISINTf}, 955 { 0x0100, DB_L2_CHILD_STATE1_UNCORRECTED_ERRORf, 956 DB_L2_CHILD_STATE1_UNCORRECTED_ERROR_DISINTf}, 957 { 0x0080, DB_L2_PARENT_CORRECTED_ERRORf, 958 DB_L2_PARENT_CORRECTED_ERROR_DISINTf}, 959 { 0x0040, DB_L2_PARENT_UNCORRECTED_ERRORf, 960 DB_L2_PARENT_UNCORRECTED_ERROR_DISINTf}, 961 { 0x0020, DB_L2_CHILD_WEIGHT_CFG_CNT_CORRECTED_ERRORf, 962 DB_L2_CHILD_WEIGHT_CFG_CNT_CORRECTED_ERROR_DISINTf}, 963 { 0x0010, DB_L2_CHILD_WEIGHT_CFG_CNT_UNCORRECTED_ERRORf, 964 DB_L2_CHILD_WEIGHT_CFG_CNT_UNCORRECTED_ERROR_DISINTf}, 965 { 0x0008, DB_L2_WERR_NEXT_CORRECTED_ERRORf, 966 DB_L2_WERR_NEXT_CORRECTED_ERROR_DISINTf}, 967 { 0x0004, DB_L2_WERR_NEXT_UNCORRECTED_ERRORf, 968 DB_L2_WERR_NEXT_UNCORRECTED_ERROR_DISINTf}, 969 { 0x0002, DB_L2_MIN_NEXT_CORRECTED_ERRORf, 970 DB_L2_MIN_NEXT_CORRECTED_ERROR_DISINTf}, 971 { 0x0001, DB_L2_MIN_NEXT_UNCORRECTED_ERRORf, 972 DB_L2_MIN_NEXT_UNCORRECTED_ERROR_DISINTf}, 973 { 0 } /* table terminator */ 974 }; 975 976 STATIC _soc_katana2_mmu_sub_block_leaf_info_t 977 _soc_katana2_mmu_sb_lls_misc_ecc_parity_info [] = { 978 /* LLS_MISC_ECC_ERROR1 */ 979 { 0x200000, DB_S1_ERROR_CORRECTED_ERRORf, 980 DB_S1_ERROR_CORRECTED_ERROR_DISINTf}, 981 { 0x100000, DB_S1_ERROR_UNCORRECTED_ERRORf, 982 DB_S1_ERROR_UNCORRECTED_ERROR_DISINTf}, 983 { 0x80000, DB_S0_ERROR_CORRECTED_ERRORf, 984 DB_S0_ERROR_CORRECTED_ERRORf}, 985 { 0x40000, DB_S0_ERROR_UNCORRECTED_ERRORf, 986 DB_S0_ERROR_UNCORRECTED_ERROR_DISINTf}, 987 { 0x20000, DB_L0_ERROR_MIN_CORRECTED_ERRORf, 988 DB_L0_ERROR_MIN_CORRECTED_ERROR_DISINTf}, 989 { 0x10000, DB_L0_ERROR_MIN_UNCORRECTED_ERRORf, 990 DB_L0_ERROR_MIN_UNCORRECTED_ERROR_DISINTf}, 991 { 0x8000, DB_L1_ERROR_MIN_CORRECTED_ERRORf, 992 DB_L1_ERROR_MIN_CORRECTED_ERROR_DISINTf}, 993 { 0x4000, DB_L1_ERROR_MIN_UNCORRECTED_ERRORf, 994 DB_L1_ERROR_MIN_UNCORRECTED_ERROR_DISINTf}, 995 { 0x2000, DB_L2_ERROR_MIN_CORRECTED_ERRORf, 996 DB_L2_ERROR_MIN_CORRECTED_ERROR_DISINTf}, 997 { 0x1000, DB_L2_ERROR_MIN_UNCORRECTED_ERRORf, 998 DB_L2_ERROR_MIN_UNCORRECTED_ERROR_DISINTf}, 999 { 0x0800, DB_L2_ACT_XON_CORRECTED_ERRORf, 1000 DB_L2_ACT_XON_CORRECTED_ERROR_DISINTf}, 1001 { 0x0400, DB_L2_ACT_XON_UNCORRECTED_ERRORf, 1002 DB_L2_ACT_XON_UNCORRECTED_ERROR_DISINTf}, 1003 { 0x0200, DB_L2_ACT_SHAPER_CORRECTED_ERRORf, 1004 DB_L2_ACT_SHAPER_CORRECTED_ERROR_DISINTf}, 1005 { 0x0100, DB_L2_ACT_SHAPER_UNCORRECTED_ERRORf, 1006 DB_L2_ACT_SHAPER_UNCORRECTED_ERROR_DISINTf}, 1007 { 0x0080, DB_L2_ACT_MIN_CORRECTED_ERRORf, 1008 DB_L2_ACT_MIN_CORRECTED_ERROR_DISINTf}, 1009 { 0x0040, DB_L2_ACT_MIN_UNCORRECTED_ERRORf, 1010 DB_L2_ACT_MIN_UNCORRECTED_ERROR_DISINTf}, 1011 { 0x0020, DB_L0_ERROR_CORRECTED_ERRORf, 1012 DB_L0_ERROR_CORRECTED_ERROR_DISINTf}, 1013 { 0x0010, DB_L0_ERROR_UNCORRECTED_ERRORf, 1014 DB_L0_ERROR_UNCORRECTED_ERROR_DISINTf}, 1015 { 0x0008, DB_L1_ERROR_CORRECTED_ERRORf, 1016 DB_L1_ERROR_CORRECTED_ERROR_DISINTf}, 1017 { 0x0004, DB_L1_ERROR_UNCORRECTED_ERRORf, 1018 DB_L1_ERROR_UNCORRECTED_ERROR_DISINTf}, 1019 { 0x0002, DB_L2_ERROR_CORRECTED_ERRORf, 1020 DB_L2_ERROR_CORRECTED_ERROR_DISINTf}, 1021 { 0x0001, DB_L2_ERROR_UNCORRECTED_ERRORf, 1022 DB_L2_ERROR_UNCORRECTED_ERROR_DISINTf}, 1023 { 0 } /* table terminator */ 1024 1025 }; 1026 1027 STATIC _soc_katana2_mmu_sub_block_leaf_info_t 1028 _soc_katana2_mmu_sb_mem1_parity_info [] = { 1029 /* CLINK_ERROR */ 1030 { 0x0008, CLINKE_CORRECTED_ERRORf, 1031 CLINKE_CORRECTED_ERROR_DISINTf }, 1032 { 0x0004, CLINKE_UNCORRECTED_ERRORf, 1033 CLINKE_UNCORRECTED_ERROR_DISINTf }, 1034 { 0x0002, CLINKI_CORRECTED_ERRORf, 1035 CLINKI_CORRECTED_ERROR_DISINTf }, 1036 { 0x0001, CLINKI_UNCORRECTED_ERRORf, 1037 CLINKI_UNCORRECTED_ERROR_DISINTf }, 1038 { 0 } /* table terminator */ 1039 }; 1040 1041 STATIC _soc_katana2_mmu_sub_block_leaf_info_t 1042 _soc_katana2_mmu_sb_e2efc_parity_info [] = { 1043 /* MMU_E2EFC_ERROR_0 */ 1044 { 0x0200, E2EFC_QEN_CNT_UNDERRUNf, 1045 E2EFC_QEN_CNT_UNDERRUN_DISINTf}, 1046 { 0x0100, E2EFC_QEN_CNT_OVERFLOWf, 1047 E2EFC_QEN_CNT_OVERFLOW_DISINTf}, 1048 { 0x0080, E2EFC_RQE_CNT_UNDERRUNf, 1049 E2EFC_RQE_CNT_UNDERRUN_DISINTf}, 1050 { 0x0040, E2EFC_RQE_CNT_OVERFLOWf, 1051 E2EFC_RQE_CNT_OVERFLOW_DISINTf}, 1052 { 0x0020, E2EFC_EMA_CNT_UNDERRUNf, 1053 E2EFC_EMA_CNT_UNDERRUN_DISINTf}, 1054 { 0x0010, E2EFC_EMA_CNT_OVERFLOWf, 1055 E2EFC_EMA_CNT_OVERFLOW_DISINTf}, 1056 { 0x0008, E2EFC_EXT_CNT_UNDERRUNf, 1057 E2EFC_EXT_CNT_UNDERRUN_DISINTf}, 1058 { 0x0004, E2EFC_EXT_CNT_OVERFLOWf, 1059 E2EFC_EXT_CNT_OVERFLOW_DISINTf}, 1060 { 0x0002, E2EFC_INT_CNT_UNDERRUNf, 1061 E2EFC_INT_CNT_UNDERRUN_DISINTf}, 1062 { 0x0001, E2EFC_INT_CNT_OVERFLOWf, 1063 E2EFC_INT_CNT_OVERFLOW_DISINTf}, 1064 { 0 } /* table terminator */ 1065 }; 1066 1067 STATIC _soc_katana2_mmu_sub_block_leaf_info_t 1068 _soc_katana2_mmu_sb_thdi_parity_info [] = { 1069 /* MMU_THDI_INTR */ 1070 { 0x0010, THDI_INTR_4f, THDI_INTR_4_DISINTf}, 1071 { 0x0008, THDI_INTR_3f, THDI_INTR_3_DISINTf}, 1072 { 0x0004, THDI_INTR_2f, THDI_INTR_2_DISINTf}, 1073 { 0x0002, THDI_INTR_1f, THDI_INTR_1_DISINTf}, 1074 { 0x0001, THDI_INTR_0f, THDI_INTR_0_DISINTf}, 1075 { 0 } /* table terminator */ 1076 }; 1077 1078 STATIC _soc_katana2_mmu_sub_block_leaf_info_t 1079 _soc_katana2_mmu_sb_ctr_parity_info [] = { 1080 /* CTR_ERROR */ 1081 { 0x0100, CTR_RQE_FIFO_OVERFLOW_ERRORf, 1082 CTR_RQE_FIFO_OVERFLOW_ERROR_DISINTf}, 1083 { 0x0080, CTR_ENQ_WRAP_ERRORf, 1084 CTR_ENQ_WRAP_ERROR_DISINTf}, 1085 { 0x0040, CTR_DEQ_WRAP_ERRORf, 1086 CTR_DEQ_WRAP_ERROR_DISINTf}, 1087 { 0x0020, CTR_DEQ_STATUS_CORRECTED_ERRORf, 1088 CTR_DEQ_STATUS_CORRECTED_ERROR_DISINTf}, 1089 { 0x0010, CTR_DEQ_STATUS_UNCORRECTED_ERRORf, 1090 CTR_DEQ_STATUS_UNCORRECTED_ERROR_DISINTf}, 1091 { 0x0008, CTR_RQE_FIFO_CORRECTED_ERRORf, 1092 CTR_RQE_FIFO_CORRECTED_ERROR_DISINTf}, 1093 { 0x0004, CTR_RQE_FIFO_UNCORRECTED_ERRORf, 1094 CTR_RQE_FIFO_UNCORRECTED_ERROR_DISINTf}, 1095 { 0x0002, CTR_FLEX_CNT_CORRECTED_ERRORf, 1096 CTR_FLEX_CNT_CORRECTED_ERROR_DISINTf}, 1097 { 0x0001, CTR_FLEX_CNT_UNCORRECTED_ERRORf, 1098 CTR_FLEX_CNT_UNCORRECTED_ERROR_DISINTf}, 1099 { 0 } /* table terminator */ 1100 }; 1101 1102 STATIC _soc_katana2_mmu_sub_block_leaf_info_t 1103 _soc_katana2_mmu_sb_ccp_parity_info [] = { 1104 /* CCP_ERROR */ 1105 { 0x0200, CCPE_FIFO_CORRECTED_ERRORf, 1106 CCPE_FIFO_CORRECTED_ERROR_DISINTf}, 1107 { 0x0100, CCPE_FIFO_UNCORRECTED_ERRORf, 1108 CCPE_FIFO_UNCORRECTED_ERROR_DISINTf}, 1109 { 0x0080, CCPI_FIFO_CORRECTED_ERRORf, 1110 CCPI_FIFO_CORRECTED_ERROR_DISINTf}, 1111 { 0x0040, CCPI_FIFO_UNCORRECTED_ERRORf, 1112 CCPI_FIFO_UNCORRECTED_ERROR_DISINTf}, 1113 { 0x0020, CCPI_RQE_UPD_NEGATIVEf, 1114 CCPI_RQE_UPD_NEGATIVE_DISINTf}, 1115 { 0x0010, CCPE_RQE_UPD_NEGATIVEf, 1116 CCPE_RQE_UPD_NEGATIVE_DISINTf}, 1117 { 0x0008, CCPE_CORRECTED_ERRORf, 1118 CCPE_CORRECTED_ERROR_DISINTf}, 1119 { 0x0004, CCPE_UNCORRECTED_ERRORf, 1120 CCPE_UNCORRECTED_ERROR_DISINTf}, 1121 { 0x0002, CCPI_CORRECTED_ERRORf, 1122 CCPI_CORRECTED_ERROR_DISINTf}, 1123 { 0x0001, CCPI_UNCORRECTED_ERRORf, 1124 CCPI_UNCORRECTED_ERROR_DISINTf}, 1125 { 0 } /* table terminator */ 1126 }; 1127 1128 STATIC _soc_katana2_mmu_sub_block_leaf_info_t 1129 _soc_katana2_mmu_sb_toq2_parity_info [] = { 1130 /* TOQ_ERROR2 */ 1131 { 0x2000, REPL_HEAD_WRAPf, 1132 REPL_HEAD_WRAP_DISINTf}, 1133 { 0x1000, PQE_CREDIT_UNDERRUNf, 1134 PQE_CREDIT_UNDERRUN_DISINTf}, 1135 { 0x0800, PQE_CREDIT_OVERFLOWf, 1136 PQE_CREDIT_OVERFLOW_DISINTf}, 1137 { 0x0400, QEN_ALLOC_UNDERRUNf, 1138 QEN_ALLOC_UNDERRUN_DISINTf}, 1139 { 0x0200, QEN_ALLOC_OVERFLOWf, 1140 QEN_ALLOC_OVERFLOW_DISINTf}, 1141 { 0x0100, FLUSH_COMPLETEf, 1142 FLUSH_COMPLETE_DISINTf}, 1143 { 0x0080, QDIS_FIFO_OVERFLOWf, 1144 QDIS_FIFO_OVERFLOW_DISINTf}, 1145 { 0x0040, TRACE_DEQ_EVENTf, 1146 TRACE_DEQ_EVENT_DISINTf}, 1147 { 0x0020, TRACE_ENQ_EVENTf, 1148 TRACE_ENQ_EVENT_DISINTf}, 1149 { 0x0010, DEQ_TO_EMPTY_QUEUE_ERRORf, 1150 DEQ_TO_EMPTY_QUEUE_ERROR_DISINTf}, 1151 { 0x0008, QSTRUCT_EMPTY_ERRORf, 1152 QSTRUCT_EMPTY_ERROR_DISINTf}, 1153 { 0x0004, QUEUE_OVELOAD_ERRORf, 1154 QUEUE_OVELOAD_ERROR_DISINTf}, 1155 { 0x0002, TDM_VIOLATION_ERRORf, 1156 TDM_VIOLATION_ERROR_DISINTf}, 1157 { 0x0001, RQE_FIFO_OVERFLOWf, 1158 RQE_FIFO_OVERFLOW_DISINTf}, 1159 { 0 } /* table terminator */ 1160 }; 1161 1162 STATIC _soc_katana2_mmu_sub_block_leaf_info_t 1163 _soc_katana2_mmu_sb_toq1_parity_info [] = { 1164 /* TOQ_ERROR1 */ 1165 { 0x80000, QPACK_MODE_TBL_CORRECTED_ERRORf, 1166 QPACK_MODE_TBL_CORRECTED_ERROR_DISINTf}, 1167 { 0x40000, QPACK_MODE_TBL_UNCORRECTED_ERRORf, 1168 QPACK_MODE_TBL_UNCORRECTED_ERROR_DISINTf}, 1169 { 0x20000, EOPE_TBL_CORRECTED_ERRORf, 1170 EOPE_TBL_CORRECTED_ERROR_DISINTf}, 1171 { 0x10000, EOPE_TBL_UNCORRECTED_ERRORf, 1172 EOPE_TBL_UNCORRECTED_ERROR_DISINTf}, 1173 { 0x8000, REPL_MAP_TBL_CORRECTED_ERRORf, 1174 REPL_MAP_TBL_CORRECTED_ERROR_DISINTf}, 1175 { 0x4000, REPL_MAP_TBL_UNCORRECTED_ERRORf, 1176 REPL_MAP_TBL_UNCORRECTED_ERROR_DISINTf}, 1177 { 0x2000, REPL_STATE_TBL_CORRECTED_ERRORf, 1178 REPL_STATE_TBL_CORRECTED_ERROR_DISINTf}, 1179 { 0x1000, REPL_STATE_TBL_UNCORRECTED_ERRORf, 1180 REPL_STATE_TBL_UNCORRECTED_ERROR_DISINTf}, 1181 { 0x0800, PORT_STATE_CORRECTED_ERRORf, 1182 PORT_STATE_CORRECTED_ERROR_DISINTf}, 1183 { 0x0400, PORT_STATE_UNCORRECTED_ERRORf, 1184 PORT_STATE_UNCORRECTED_ERROR_DISINTf}, 1185 { 0x0200, RQE_FIFO_CORRECTED_ERRORf, 1186 RQE_FIFO_CORRECTED_ERROR_DISINTf}, 1187 { 0x0100, RQE_FIFO_UNCORRECTED_ERRORf, 1188 RQE_FIFO_UNCORRECTED_ERROR_DISINTf}, 1189 { 0x0080, REPL_GRP_TBL_CORRECTED_ERRORf, 1190 REPL_GRP_TBL_CORRECTED_ERROR_DISINTf}, 1191 { 0x0040, REPL_GRP_TBL_UNCORRECTED_ERRORf, 1192 REPL_GRP_TBL_UNCORRECTED_ERROR_DISINTf}, 1193 { 0x0020, REPL_HEAD_TBL_CORRECTED_ERRORf, 1194 REPL_HEAD_TBL_CORRECTED_ERROR_DISINTf}, 1195 { 0x0010, REPL_HEAD_TBL_UNCORRECTED_ERRORf, 1196 REPL_HEAD_TBL_UNCORRECTED_ERROR_DISINTf}, 1197 { 0x0008, REPL_LIST_TBL_CORRECTED_ERRORf, 1198 REPL_LIST_TBL_CORRECTED_ERROR_DISINTf}, 1199 { 0x0004, REPL_LIST_TBL_UNCORRECTED_ERRORf, 1200 REPL_LIST_TBL_UNCORRECTED_ERROR_DISINTf}, 1201 { 0x0002, TOQ_STATE_CORRECTED_ERRORf, 1202 TOQ_STATE_CORRECTED_ERROR_DISINTf}, 1203 { 0x0001, TOQ_STATE_UNCORRECTED_ERRORf, 1204 TOQ_STATE_UNCORRECTED_ERROR_DISINTf}, 1205 { 0 } /* table terminator */ 1206 }; 1207 1208 1209 STATIC _soc_katana2_mmu_sub_block_leaf_info_t 1210 _soc_katana2_mmu_sb_ite_parity_info [] = { 1211 /* MMU_ITE_ERROR_0 */ 1212 { 0x0008, ITE_WORK_QUEUE_RD_EMPTYf, 1213 ITE_WORK_QUEUE_RD_EMPTY_DISINTf}, 1214 { 0x0004, ITE_WORK_QUEUE_WR_FULLf, 1215 ITE_WORK_QUEUE_WR_FULL_DISINTf}, 1216 { 0x0002, ITE_CTRL_RD_EMPTYf, 1217 ITE_CTRL_RD_EMPTY_DISINTf}, 1218 { 0x0001, ITE_CTRL_WR_FULLf, 1219 ITE_CTRL_WR_FULL_DISINTf}, 1220 { 0 } /* table terminator */ 1221 }; 1222 1223 STATIC _soc_katana2_mmu_sub_block_leaf_info_t 1224 _soc_katana2_mmu_sb_ite_cfg_parity_info [] = { 1225 /* MMU_ITE_CFG_ECC_ERROR_0 */ 1226 { 0x0800, SOP_CONTROL_ECC_0_CORRECTED_ERRORf, 1227 SOP_CONTROL_ECC_0_CORRECTED_ERROR_DISINTf}, 1228 { 0x0400, SOP_CONTROL_ECC_0_UNCORRECTED_ERRORf, 1229 SOP_CONTROL_ECC_0_UNCORRECTED_ERROR_DISINTf}, 1230 { 0x0200, PACKET_PTR_STORE_CORRECTED_ERRORf, 1231 PACKET_PTR_STORE_FORCE_CORRECTED_ERROR_DISINTf}, 1232 { 0x0100, PACKET_PTR_STORE_UNCORRECTED_ERRORf, 1233 PACKET_PTR_STORE_FORCE_UNCORRECTED_ERROR_DISINTf}, 1234 { 0x0080, ITE_WORK_QUEUE_CORRECTED_ERRORf, 1235 ITE_WORK_QUEUE_FORCE_CORRECTED_ERROR_DISINTf}, 1236 { 0x0040, ITE_WORK_QUEUE_UNCORRECTED_ERRORf, 1237 ITE_WORK_QUEUE_FORCE_UNCORRECTED_ERROR_DISINTf}, 1238 { 0x0020, ITE_CTRL_CORRECTED_ERRORf, 1239 ITE_CTRL_CORRECTED_ERROR_DISINTf}, 1240 { 0x0010, ITE_CTRL_UNCORRECTED_ERRORf, 1241 ITE_CTRL_UNCORRECTED_ERROR_DISINTf}, 1242 { 0x0008, ITE_QMGR_FLL_CORRECTED_ERRORf, 1243 ITE_QMGR_FLL_FORCE_CORRECTED_ERROR_DISINTf}, 1244 { 0x0004, ITE_QMGR_FLL_UNCORRECTED_ERRORf, 1245 ITE_QMGR_FLL_FORCE_UNCORRECTED_ERROR_DISINTf}, 1246 { 0x0002, ITE_QMGR_QLL_CORRECTED_ERRORf, 1247 ITE_QMGR_QLL_CORRECTED_ERROR_DISINTf}, 1248 { 0x0001, ITE_QMGR_QLL_UNCORRECTED_ERRORf, 1249 ITE_QMGR_QLL_UNCORRECTED_ERROR_DISINTf}, 1250 { 0 } /* table terminator */ 1251 }; 1252 1253 STATIC _soc_katana2_mmu_sub_block_leaf_info_t 1254 _soc_katana2_mmu_sb_enq_cfg_parity_info [] = { 1255 /* MMU_ENQ_CFG_ECC_ERROR_0 */ 1256 { 0x800000, CBI_CORRECTED_ERRORf, 1257 CBI_CORRECTED_ERROR_DISINTf}, 1258 { 0x400000, CBI_UNCORRECTED_ERRORf, 1259 CBI_UNCORRECTED_ERROR_DISINTf}, 1260 { 0x200000, ITE_REORDER_FIFO_CORRECTED_ERRORf, 1261 ITE_REORDER_FIFO_CORRECTED_ERRORf}, 1262 { 0x100000, ITE_REORDER_FIFO_UNCORRECTED_ERRORf, 1263 ITE_REORDER_FIFO_UNCORRECTED_ERRORf}, 1264 { 0x80000, PACKING_PKT_LEN_FIFOS_CORRECTED_ERRORf, 1265 PACKING_PKT_LEN_FIFOS_CORRECTED_ERROR_DISINTf}, 1266 { 0x40000, PACKING_PKT_LEN_FIFOS_UNCORRECTED_ERRORf, 1267 PACKING_PKT_LEN_FIFOS_UNCORRECTED_ERROR_DISINTf}, 1268 { 0x20000, PACKING_PORT_FIFOS_CORRECTED_ERRORf, 1269 PACKING_PORT_FIFOS_CORRECTED_ERROR_DISINTf}, 1270 { 0x10000, PACKING_PORT_FIFOS_UNCORRECTED_ERRORf, 1271 PACKING_PORT_FIFOS_UNCORRECTED_ERROR_DISINTf}, 1272 { 0x8000, PACKING_CTXT_FIFOS_FP_LL_CORRECTED_ERRORf, 1273 PACKING_CTXT_FIFOS_FP_LL_CORRECTED_ERROR_DISINTf}, 1274 { 0x4000, PACKING_CTXT_FIFOS_FP_LL_UNCORRECTED_ERRORf, 1275 PACKING_CTXT_FIFOS_FP_LL_UNCORRECTED_ERROR_DISINTf}, 1276 { 0x2000, PACKING_CTXT_FIFOS_CORRECTED_ERRORf, 1277 PACKING_CTXT_FIFOS_CORRECTED_ERROR_DISINTf}, 1278 { 0x1000, PACKING_CTXT_FIFOS_UNCORRECTED_ERRORf, 1279 PACKING_CTXT_FIFOS_UNCORRECTED_ERROR_DISINTf}, 1280 { 0x0800, CFAPI_INTERNAL_RECYCLE_CORRECTED_ERRORf, 1281 CFAPI_INTERNAL_RECYCLE_CORRECTED_ERROR_DISINTf}, 1282 { 0x0400, CFAPI_INTERNAL_RECYCLE_UNCORRECTED_ERRORf, 1283 CFAPI_INTERNAL_RECYCLE_UNCORRECTED_ERROR_DISINTf}, 1284 { 0x0200, SRC_PPP_TO_S1_LOOKUP_CORRECTED_ERRORf, 1285 SRC_PPP_TO_S1_LOOKUP_CORRECTED_ERROR_DISINTf}, 1286 { 0x0100, SRC_PPP_TO_S1_LOOKUP_UNCORRECTED_ERRORf, 1287 SRC_PPP_TO_S1_LOOKUP_UNCORRECTED_ERROR_DISINTf}, 1288 { 0x0080, SRC_PORT_STATE_CORRECTED_ERRORf, 1289 SRC_PORT_STATE_CORRECTED_ERROR_DISINTf}, 1290 { 0x0040, SRC_PORT_STATE_UNCORRECTED_ERRORf, 1291 SRC_PORT_STATE_UNCORRECTED_ERROR_DISINTf}, 1292 { 0x0020, SOP_STORE_CORRECTED_ERRORf, 1293 SOP_STORE_CORRECTED_ERROR_DISINTf}, 1294 { 0x0010, SOP_STORE_UNCORRECTED_ERRORf, 1295 SOP_STORE_UNCORRECTED_ERROR_DISINTf}, 1296 { 0x0008, RQE_WR_COMPLETE_CORRECTED_ERRORf, 1297 RQE_WR_COMPLETE_CORRECTED_ERROR_DISINTf}, 1298 { 0x0004, RQE_WR_COMPLETE_UNCORRECTED_ERRORf, 1299 RQE_WR_COMPLETE_UNCORRECTED_ERROR_DISINTf}, 1300 { 0x0002, CBP_32B_WR_STORE_CORRECTED_ERRORf, 1301 CBP_32B_WR_STORE_CORRECTED_ERROR_DISINTf}, 1302 { 0x0001, CBP_32B_WR_STORE_UNCORRECTED_ERRORf, 1303 CBP_32B_WR_STORE_UNCORRECTED_ERROR_DISINTf}, 1304 { 0 } /* table terminator */ 1305 }; 1306 1307 STATIC _soc_katana2_mmu_sub_block_leaf_info_t 1308 _soc_katana2_mmu_sb_enq_parity_info [] = { 1309 /* MMU_ENQ_ERROR_0 */ 1310 { 0x0010, FAP_DUPLICATE_PTRf, 1311 FAP_DUPLICATE_PTR_DISINTf}, 1312 { 0x0008, ENQ_TRACE_STATUSf, 1313 ENQ_TRACE_STATUS_DISINTf}, 1314 { 0x0004, ILLEGAL_CELL_PBIf, 1315 ILLEGAL_CELL_PBI_DISINTf}, 1316 { 0x0002, MISSING_START_ERRf, 1317 MISSING_START_ERR_DISINTf}, 1318 { 0x0001, START_BY_START_ERRf, 1319 START_BY_START_ERR_DISINTf}, 1320 { 0 } /* table terminator */ 1321 }; 1322 1323 STATIC _soc_katana2_mmu_sub_block_leaf_info_t 1324 _soc_katana2_mmu_sb_enq_fap_parity_info [] = { 1325 /* MMU_ENQ_FAP_ECC_ERROR_0 */ 1326 { 0x0008, FAP_STACK_CORRECTED_ERRORf, 1327 FAP_STACK_CORRECTED_ERROR_DISINTf}, 1328 { 0x0004, FAP_STACK_UNCORRECTED_ERRORf, 1329 FAP_STACK_UNCORRECTED_ERROR_ERROR_DISINTf}, 1330 { 0x0002, FAP_BITMAP_CORRECTED_ERRORf, 1331 FAP_BITMAP_CORRECTED_ERROR_DISINTf}, 1332 { 0x0001, FAP_BITMAP_UNCORRECTED_ERRORf, 1333 FAP_BITMAP_UNCORRECTED_ERROR_DISINTf}, 1334 { 0 } /* table terminator */ 1335 }; 1336 1337 STATIC _soc_katana2_mmu_sub_block_leaf_info_t 1338 _soc_katana2_mmu_sb_thdo_stat1_parity_info [] = { 1339 /* THDO_PARITY_ERROR_STATUS1 */ 1340 { 0xfffff, ECC_1B_ERROR_STATUSf, ECC_1B_MASKf}, 1341 { 0 } /* table terminator */ 1342 }; 1343 1344 STATIC _soc_katana2_mmu_sub_block_leaf_info_t 1345 _soc_katana2_mmu_sb_thdo_stat2_parity_info [] = { 1346 /* THDO_PARITY_ERROR_STATUS2 */ 1347 { 0xfffff, ECC_2B_ERROR_STATUSf, ECC_2B_MASKf}, 1348 { 0 } /* table terminator */ 1349 }; 1350 1351 STATIC _soc_katana2_mmu_sub_block_leaf_info_t 1352 _soc_katana2_mmu_sb_cfapi_parity_info [] = { 1353 /* CFAPI_ECC_ERROR */ 1354 { 0x0010, DUPLICATE_PTRf, 1355 DUPLICATE_PTR_DISINTf}, 1356 { 0x0008, BITMAP_CORRECTED_ERRORf, 1357 BITMAP_CORRECTED_ERROR_DISINTf}, 1358 { 0x0004, BITMAP_UNCORRECTED_ERRORf, 1359 BITMAP_UNCORRECTED_ERROR_DISINTf}, 1360 { 0x0002, STACK_CORRECTED_ERRORf, 1361 STACK_CORRECTED_ERROR_DISINTf}, 1362 { 0x0001, STACK_UNCORRECTED_ERRORf, 1363 STACK_UNCORRECTED_ERROR_DISINTf}, 1364 { 0 } /* table terminator */ 1365 }; 1366 1367 STATIC _soc_katana2_mmu_sub_block_leaf_info_t 1368 _soc_katana2_mmu_sb_cfape_parity_info [] = { 1369 /* CFAPE_ECC_ERROR */ 1370 { 0x0010, DUPLICATE_PTRf, 1371 DUPLICATE_PTR_DISINTf}, 1372 { 0x0008, BITMAP_CORRECTED_ERRORf, 1373 BITMAP_CORRECTED_ERROR_DISINTf}, 1374 { 0x0004, BITMAP_UNCORRECTED_ERRORf, 1375 BITMAP_UNCORRECTED_ERROR_DISINTf}, 1376 { 0x0002, STACK_CORRECTED_ERRORf, 1377 STACK_CORRECTED_ERROR_DISINTf}, 1378 { 0x0001, STACK_UNCORRECTED_ERRORf, 1379 STACK_UNCORRECTED_ERROR_DISINTf}, 1380 { 0 } /* table terminator */ 1381 }; 1382 1383 STATIC _soc_katana2_mmu_sub_block_leaf_info_t 1384 _soc_katana2_mmu_sb_age_int_parity_info [] = { 1385 /* AGING_ERROR_INT */ 1386 { 0x0020, LMT_CORRECTED_ERRORf, LMT_CORRECTED_ERROR_DISINTf}, 1387 { 0x0010, LMT_UNCORRECTED_ERRORf, LMT_UNCORRECTED_ERROR_DISINTf}, 1388 { 0x0008, CTR_CORRECTED_ERRORf, CTR_CORRECTED_ERROR_DISINTf}, 1389 { 0x0004, CTR_UNCORRECTED_ERRORf, CTR_UNCORRECTED_ERROR_DISINTf}, 1390 { 0x0002, EXP_CORRECTED_ERRORf, EXP_CORRECTED_ERROR_DISINTf}, 1391 { 0x0001, EXP_UNCORRECTED_ERRORf, EXP_UNCORRECTED_ERROR_DISINTf}, 1392 { 0 } /* table terminator */ 1393 }; 1394 1395 STATIC _soc_katana2_mmu_sub_block_leaf_info_t 1396 _soc_katana2_mmu_sb_age_ext_parity_info [] = { 1397 { 0x0020, LMT_CORRECTED_ERRORf, LMT_CORRECTED_ERROR_DISINTf}, 1398 { 0x0010, LMT_UNCORRECTED_ERRORf, LMT_UNCORRECTED_ERROR_DISINTf}, 1399 { 0x0008, CTR_CORRECTED_ERRORf, CTR_CORRECTED_ERROR_DISINTf}, 1400 { 0x0004, CTR_UNCORRECTED_ERRORf, CTR_UNCORRECTED_ERROR_DISINTf}, 1401 { 0x0002, EXP_CORRECTED_ERRORf, EXP_CORRECTED_ERROR_DISINTf}, 1402 { 0x0001, EXP_UNCORRECTED_ERRORf, EXP_UNCORRECTED_ERROR_DISINTf}, 1403 { 0 } /* table terminator */ 1404 }; 1405 1406 STATIC _soc_katana2_mmu_sub_block_leaf_info_t 1407 _soc_katana2_mmu_sb_rqe_extq_parity_info [] = { 1408 { 0x4000000, REPLICATION_SRCH_FAILf, REPLICATION_SRCH_FAIL_MASKf }, 1409 { 0x2000000, REPLICATION_OVER_LIMITf, REPLICATION_OVER_LIMIT_MASKf}, 1410 { 0x1ffe000, REPLICATION_FAIL_MGIDf , 0 }, 1411 { 0x0001fff, REPLICATION_COUNTf, 0 }, 1412 { 0 } /* table terminator */ 1413 }; 1414 1415 STATIC _soc_katana2_mmu_sub_block_leaf_info_t 1416 _soc_katana2_mmu_sb_ci_parity_info [] = { 1417 { 0x0100, PHY_READY_EVENTf, 1418 PHY_READYf}, 1419 { 0x0080, PHY_BL1_RD_FIFO_ERRORf, 1420 PHY_BL1_RD_FIFO_ERRORf}, 1421 { 0x0040, PHY_BL0_RD_FIFO_ERRORf, 1422 PHY_BL0_RD_FIFO_ERRORf}, 1423 { 0x0020, WFIFO_CTL_CORRECTED_ERRORf, 1424 WFIFO_CTL_CORRECTED_ERROR_DISINTf}, 1425 { 0x0010, WFIFO_CTL_UNCORRECTED_ERRORf, 1426 WFIFO_CTL_UNCORRECTED_ERROR_DISINTf}, 1427 { 0x0008, WFIFO_OVERFLOWf, 1428 WB_OVERFLOW_DISINTf}, 1429 { 0x0004, RFIFO_CTL_CORRECTED_ERRORf, 1430 RFIFO_CTL_CORRECTED_ERROR_DISINTf}, 1431 { 0x0002, RFIFO_CTL_UNCORRECTED_ERRORf, 1432 RFIFO_CTL_UNCORRECTED_ERROR_DISINTf}, 1433 { 0x0001, RFIFO_OVERFLOWf, 1434 RFIFO_OVERFLOW_DISINTf}, 1435 { 0 } /* table terminator */ 1436 1437 }; 1438 1439 STATIC 1440 _soc_katana2_mmu_sub_block_leaf_info_t 1441 _soc_katana2_mmu_sb_emc0_parity_info [] = { 1442 /* EMC_ERROR_0 */ 1443 { 0x0020, EMC_WTAC_SPC_EMA_LOCKUP_ERRORf, 1444 EMC_WTAC_SPC_EMA_LOCKUP_ERROR_DISINTf }, 1445 { 0x0010, EMC_WLCT2_MF_BUFFER_OVERFLOW_ERRORf, 1446 EMC_WLCT2_MF_BUFFER_OVERFLOW_ERROR_DISINTf }, 1447 { 0x0008, EMC_WLCT1_MF_BUFFER_OVERFLOW_ERRORf, 1448 EMC_WLCT1_MF_BUFFER_OVERFLOW_ERROR_DISINTf }, 1449 { 0x0004, EMC_WLCT0_MF_BUFFER_OVERFLOW_ERRORf, 1450 EMC_WLCT0_MF_BUFFER_OVERFLOW_ERROR_DISINTf }, 1451 { 0x0002, EMC_IRRB_BUFFER_OVERFLOW_ERRORf, 1452 EMC_IRRB_BUFFER_OVERFLOW_ERROR_DISINTf }, 1453 { 0x0001, EMC_IWRB_BUFFER_OVERFLOW_ERRORf, 1454 EMC_IWRB_BUFFER_OVERFLOW_ERROR_DISINTf }, 1455 { 0 } /* table terminator */ 1456 }; 1457 1458 STATIC 1459 _soc_katana2_mmu_sub_block_leaf_info_t 1460 _soc_katana2_mmu_sb_emc1_parity_info [] = { 1461 /* EMC_ERROR_1 */ 1462 { 0x20000000, EMC_CSDB_2_UPPER_BUFFER_UNCORRECTED_ERRORf, 1463 EMC_CSDB_2_UPPER_BUFFER_UNCORRECTED_ERROR_DISINTf}, 1464 { 0x10000000, EMC_CSDB_2_LOWER_BUFFER_UNCORRECTED_ERRORf, 1465 EMC_CSDB_2_LOWER_BUFFER_UNCORRECTED_ERROR_DISINTf}, 1466 { 0x8000000, EMC_CSDB_1_UPPER_BUFFER_UNCORRECTED_ERRORf, 1467 EMC_CSDB_1_UPPER_BUFFER_UNCORRECTED_ERROR_DISINTf}, 1468 { 0x4000000, EMC_CSDB_1_LOWER_BUFFER_UNCORRECTED_ERRORf, 1469 EMC_CSDB_1_LOWER_BUFFER_UNCORRECTED_ERROR_DISINTf}, 1470 { 0x2000000, EMC_CSDB_0_UPPER_BUFFER_UNCORRECTED_ERRORf, 1471 EMC_CSDB_0_UPPER_BUFFER_UNCORRECTED_ERROR_DISINTf}, 1472 { 0x1000000, EMC_CSDB_0_LOWER_BUFFER_UNCORRECTED_ERRORf, 1473 EMC_CSDB_0_LOWER_BUFFER_UNCORRECTED_ERROR_DISINTf}, 1474 { 0x800000, EMC_ERRB_1_BUFFER_UNCORRECTED_ERRORf, 1475 EMC_ERRB_1_BUFFER_UNCORRECTED_ERROR_DISINTf}, 1476 { 0x400000, EMC_ERRB_1_BUFFER_CORRECTED_ERRORf, 1477 EMC_ERRB_1_BUFFER_CORRECTED_ERROR_DISINTf}, 1478 { 0x200000, EMC_ERRB_0_BUFFER_UNCORRECTED_ERRORf, 1479 EMC_ERRB_0_BUFFER_UNCORRECTED_ERROR_DISINTf}, 1480 { 0x100000, EMC_ERRB_0_BUFFER_CORRECTED_ERRORf, 1481 EMC_ERRB_0_BUFFER_CORRECTED_ERROR_DISINTf}, 1482 { 0x80000, EMC_RFCQ_BUFFER_UNCORRECTED_ERRORf, 1483 EMC_RFCQ_BUFFER_UNCORRECTED_ERROR_DISINTf}, 1484 { 0x40000, EMC_RFCQ_BUFFER_CORRECTED_ERRORf, 1485 EMC_RFCQ_BUFFER_CORRECTED_ERROR_DISINTf}, 1486 { 0x20000, EMC_RSFP_BUFFER_UNCORRECTED_ERRORf, 1487 EMC_RSFP_BUFFER_UNCORRECTED_ERROR_DISINTf}, 1488 { 0x10000, EMC_RSFP_BUFFER_CORRECTED_ERRORf, 1489 EMC_RSFP_BUFFER_CORRECTED_ERROR_DISINTf}, 1490 { 0x8000, EMC_IRRB_BUFFER_UNCORRECTED_ERRORf, 1491 EMC_IRRB_BUFFER_UNCORRECTED_ERROR_DISINTf}, 1492 { 0x4000, EMC_IRRB_BUFFER_CORRECTED_ERRORf, 1493 EMC_IRRB_BUFFER_CORRECTED_ERROR_DISINTf}, 1494 { 0x2000, EMC_EWRB_0_BUFFER_1_UNCORRECTED_ERRORf, 1495 EMC_EWRB_0_BUFFER_1_UNCORRECTED_ERROR_DISINTf}, 1496 { 0x1000, EMC_EWRB_0_BUFFER_1_CORRECTED_ERRORf, 1497 EMC_EWRB_0_BUFFER_1_CORRECTED_ERROR_DISINTf}, 1498 { 0x0800, EMC_EWRB_0_BUFFER_0_UNCORRECTED_ERRORf, 1499 EMC_EWRB_0_BUFFER_0_UNCORRECTED_ERROR_DISINTf}, 1500 { 0x0400, EMC_EWRB_0_BUFFER_0_CORRECTED_ERRORf, 1501 EMC_EWRB_0_BUFFER_0_CORRECTED_ERROR_DISINTf}, 1502 { 0x0200, EMC_WCMT_BUFFER_UNCORRECTED_ERRORf, 1503 EMC_WCMT_BUFFER_UNCORRECTED_ERROR_DISINTf}, 1504 { 0x0100, EMC_WCMT_BUFFER_CORRECTED_ERRORf, 1505 EMC_WCMT_BUFFER_CORRECTED_ERROR_DISINTf}, 1506 { 0x0080, EMC_SWAT_BUFFER_UNCORRECTED_ERRORf, 1507 EMC_SWAT_BUFFER_UNCORRECTED_ERROR_DISINTf}, 1508 { 0x0040, EMC_SWAT_BUFFER_CORRECTED_ERRORf, 1509 EMC_SWAT_BUFFER_CORRECTED_ERROR_DISINTf}, 1510 { 0x0020, EMC_WTOQ_BUFFER_UNCORRECTED_ERRORf, 1511 EMC_WTOQ_BUFFER_UNCORRECTED_ERROR_DISINTf}, 1512 { 0x0010, EMC_WTOQ_BUFFER_CORRECTED_ERRORf, 1513 EMC_WTOQ_BUFFER_CORRECTED_ERROR_DISINTf}, 1514 { 0x0008, EMC_WTFP_BUFFER_UNCORRECTED_ERRORf, 1515 EMC_WTFP_BUFFER_UNCORRECTED_ERROR_DISINTf}, 1516 { 0x0004, EMC_WTFP_BUFFER_CORRECTED_ERRORf, 1517 EMC_WTFP_BUFFER_CORRECTED_ERROR_DISINTf}, 1518 { 0x0002, EMC_IWRB_BUFFER_UNCORRECTED_ERRORf, 1519 EMC_IWRB_BUFFER_UNCORRECTED_ERROR_DISINTf}, 1520 { 0x0001, EMC_IWRB_BUFFER_CORRECTED_ERRORf, 1521 EMC_IWRB_BUFFER_CORRECTED_ERROR_DISINTf}, 1522 { 0 } /* table terminator */ 1523 }; 1524 1525 STATIC 1526 _soc_katana2_mmu_sub_block_leaf_info_t 1527 _soc_katana2_mmu_sb_emc2_parity_info [] = { 1528 /* EMC_ERROR_2 */ 1529 { 0x20000000, EMC_CSDB_5_UPPER_BUFFER_UNCORRECTED_ERRORf, 1530 EMC_CSDB_5_UPPER_BUFFER_UNCORRECTED_ERROR_DISINTf}, 1531 { 0x10000000, EMC_CSDB_5_LOWER_BUFFER_UNCORRECTED_ERRORf, 1532 EMC_CSDB_5_LOWER_BUFFER_UNCORRECTED_ERROR_DISINTf}, 1533 { 0x08000000, EMC_CSDB_4_UPPER_BUFFER_UNCORRECTED_ERRORf, 1534 EMC_CSDB_4_UPPER_BUFFER_UNCORRECTED_ERROR_DISINTf}, 1535 { 0x04000000, EMC_CSDB_4_LOWER_BUFFER_UNCORRECTED_ERRORf, 1536 EMC_CSDB_4_LOWER_BUFFER_UNCORRECTED_ERROR_DISINTf}, 1537 { 0x02000000, EMC_CSDB_3_UPPER_BUFFER_UNCORRECTED_ERRORf, 1538 EMC_CSDB_3_UPPER_BUFFER_UNCORRECTED_ERROR_DISINTf}, 1539 { 0x01000000, EMC_CSDB_3_LOWER_BUFFER_UNCORRECTED_ERRORf, 1540 EMC_CSDB_3_LOWER_BUFFER_UNCORRECTED_ERROR_DISINTf}, 1541 { 0x00800000, EMC_WLCT2_UPPER_B_BUFFER_UNCORRECTED_ERRORf, 1542 EMC_WLCT2_UPPER_B_BUFFER_UNCORRECTED_ERROR_DISINTf}, 1543 { 0x00400000, EMC_WLCT2_UPPER_B_BUFFER_CORRECTED_ERRORf, 1544 EMC_WLCT2_UPPER_B_BUFFER_CORRECTED_ERROR_DISINTf}, 1545 { 0x0200000, EMC_WLCT2_UPPER_A_BUFFER_UNCORRECTED_ERRORf, 1546 EMC_WLCT2_UPPER_A_BUFFER_UNCORRECTED_ERROR_DISINTf}, 1547 { 0x0100000, EMC_WLCT2_UPPER_A_BUFFER_CORRECTED_ERRORf, 1548 EMC_WLCT2_UPPER_A_BUFFER_CORRECTED_ERROR_DISINTf}, 1549 { 0x0080000, EMC_WLCT2_LOWER_B_BUFFER_UNCORRECTED_ERRORf, 1550 EMC_WLCT2_LOWER_B_BUFFER_UNCORRECTED_ERROR_DISINTf}, 1551 { 0x0040000, EMC_WLCT2_LOWER_B_BUFFER_CORRECTED_ERRORf, 1552 EMC_WLCT2_LOWER_B_BUFFER_CORRECTED_ERROR_DISINTf}, 1553 { 0x0020000, EMC_WLCT2_LOWER_A_BUFFER_UNCORRECTED_ERRORf, 1554 EMC_WLCT2_LOWER_A_BUFFER_UNCORRECTED_ERROR_DISINTf}, 1555 { 0x0010000, EMC_WLCT2_LOWER_A_BUFFER_CORRECTED_ERRORf, 1556 EMC_WLCT2_LOWER_A_BUFFER_CORRECTED_ERROR_DISINTf}, 1557 { 0x0008000, EMC_WLCT1_UPPER_B_BUFFER_UNCORRECTED_ERRORf, 1558 EMC_WLCT1_UPPER_B_BUFFER_UNCORRECTED_ERROR_DISINTf}, 1559 { 0x0004000, EMC_WLCT1_UPPER_B_BUFFER_CORRECTED_ERRORf, 1560 EMC_WLCT1_UPPER_B_BUFFER_CORRECTED_ERROR_DISINTf}, 1561 { 0x0002000, EMC_WLCT1_UPPER_A_BUFFER_UNCORRECTED_ERRORf, 1562 EMC_WLCT1_UPPER_A_BUFFER_UNCORRECTED_ERROR_DISINTf}, 1563 { 0x0001000, EMC_WLCT1_UPPER_A_BUFFER_CORRECTED_ERRORf, 1564 EMC_WLCT1_UPPER_A_BUFFER_CORRECTED_ERROR_DISINTf}, 1565 { 0x0000800, EMC_WLCT1_LOWER_B_BUFFER_UNCORRECTED_ERRORf, 1566 EMC_WLCT1_LOWER_B_BUFFER_UNCORRECTED_ERROR_DISINTf}, 1567 { 0x0000400, EMC_WLCT1_LOWER_B_BUFFER_CORRECTED_ERRORf, 1568 EMC_WLCT1_LOWER_B_BUFFER_CORRECTED_ERROR_DISINTf}, 1569 { 0x0000200, EMC_WLCT1_LOWER_A_BUFFER_UNCORRECTED_ERRORf, 1570 EMC_WLCT1_LOWER_A_BUFFER_UNCORRECTED_ERROR_DISINTf}, 1571 { 0x0000100, EMC_WLCT1_LOWER_A_BUFFER_CORRECTED_ERRORf, 1572 EMC_WLCT1_LOWER_A_BUFFER_CORRECTED_ERROR_DISINTf}, 1573 { 0x0000080, EMC_WLCT0_UPPER_B_BUFFER_UNCORRECTED_ERRORf, 1574 EMC_WLCT0_UPPER_B_BUFFER_UNCORRECTED_ERROR_DISINTf}, 1575 { 0x0000040, EMC_WLCT0_UPPER_B_BUFFER_CORRECTED_ERRORf, 1576 EMC_WLCT0_UPPER_B_BUFFER_CORRECTED_ERROR_DISINTf}, 1577 { 0x0000020, EMC_WLCT0_UPPER_A_BUFFER_UNCORRECTED_ERRORf, 1578 EMC_WLCT0_UPPER_A_BUFFER_UNCORRECTED_ERROR_DISINTf}, 1579 { 0x0000010, EMC_WLCT0_UPPER_A_BUFFER_CORRECTED_ERRORf, 1580 EMC_WLCT0_UPPER_A_BUFFER_CORRECTED_ERROR_DISINTf}, 1581 { 0x0000008, EMC_WLCT0_LOWER_B_BUFFER_UNCORRECTED_ERRORf, 1582 EMC_WLCT0_LOWER_B_BUFFER_UNCORRECTED_ERROR_DISINTf}, 1583 { 0x0000004, EMC_WLCT0_LOWER_B_BUFFER_CORRECTED_ERRORf, 1584 EMC_WLCT0_LOWER_B_BUFFER_CORRECTED_ERROR_DISINTf}, 1585 { 0x0000002, EMC_WLCT0_LOWER_A_BUFFER_UNCORRECTED_ERRORf, 1586 EMC_WLCT0_LOWER_A_BUFFER_UNCORRECTED_ERROR_DISINTf}, 1587 { 0x0000001, EMC_WLCT0_LOWER_A_BUFFER_CORRECTED_ERRORf, 1588 EMC_WLCT0_LOWER_A_BUFFER_CORRECTED_ERROR_DISINTf}, 1589 { 0 } /* table terminator */ 1590 }; 1591 1592 STATIC 1593 _soc_katana2_mmu_sub_block_leaf_info_t 1594 _soc_katana2_mmu_sb_emc3_parity_info [] = { 1595 /* EMC_ERROR_3 */ 1596 { 0x0008000, EMC_CI5_FIXED_PATTERN_ERRORf, 1597 EMC_CI5_FIXED_PATTERN_ERROR_DISINTf}, 1598 { 0x0004000, EMC_CI4_FIXED_PATTERN_ERRORf, 1599 EMC_CI4_FIXED_PATTERN_ERROR_DISINTf}, 1600 { 0x0002000, EMC_CI3_FIXED_PATTERN_ERRORf, 1601 EMC_CI3_FIXED_PATTERN_ERROR_DISINTf}, 1602 { 0x0001000, EMC_CI2_FIXED_PATTERN_ERRORf, 1603 EMC_CI2_FIXED_PATTERN_ERROR_DISINTf}, 1604 { 0x0000800, EMC_CI1_FIXED_PATTERN_ERRORf, 1605 EMC_CI1_FIXED_PATTERN_ERROR_DISINTf}, 1606 { 0x0000400, EMC_CI0_FIXED_PATTERN_ERRORf, 1607 EMC_CI0_FIXED_PATTERN_ERROR_DISINTf}, 1608 { 0x0000200, EMC_WLCT2_MERGED_RETURN_WTAG_FIFO_UNCORRECTED_ERRORf, 1609 EMC_WLCT2_MERGED_RETURN_WTAG_FIFO_UNCORRECTED_ERROR_DISINTf}, 1610 { 0x0000100, EMC_WLCT2_MERGED_RETURN_WTAG_FIFO_CORRECTED_ERRORf, 1611 EMC_WLCT2_MERGED_RETURN_WTAG_FIFO_CORRECTED_ERROR_DISINTf}, 1612 { 0x0000080, EMC_WLCT1_MERGED_RETURN_WTAG_FIFO_UNCORRECTED_ERRORf, 1613 EMC_WLCT1_MERGED_RETURN_WTAG_FIFO_UNCORRECTED_ERROR_DISINTf}, 1614 { 0x0000040, EMC_WLCT1_MERGED_RETURN_WTAG_FIFO_CORRECTED_ERRORf, 1615 EMC_WLCT1_MERGED_RETURN_WTAG_FIFO_CORRECTED_ERROR_DISINTf}, 1616 { 0x0000020, EMC_WLCT0_MERGED_RETURN_WTAG_FIFO_UNCORRECTED_ERRORf, 1617 EMC_WLCT0_MERGED_RETURN_WTAG_FIFO_UNCORRECTED_ERROR_DISINTf}, 1618 { 0x0000010, EMC_WLCT0_MERGED_RETURN_WTAG_FIFO_CORRECTED_ERRORf, 1619 EMC_WLCT0_MERGED_RETURN_WTAG_FIFO_CORRECTED_ERROR_DISINTf}, 1620 { 0x0000008, EMC_EWRB_1_BUFFER_1_UNCORRECTED_ERRORf, 1621 EMC_EWRB_1_BUFFER_1_UNCORRECTED_ERROR_DISINTf}, 1622 { 0x0000004, EMC_EWRB_1_BUFFER_1_CORRECTED_ERRORf, 1623 EMC_EWRB_1_BUFFER_1_CORRECTED_ERROR_DISINTf}, 1624 { 0x0000002, EMC_EWRB_1_BUFFER_0_UNCORRECTED_ERRORf, 1625 EMC_EWRB_1_BUFFER_0_UNCORRECTED_ERROR_DISINTf}, 1626 { 0x0000001, EMC_EWRB_1_BUFFER_0_CORRECTED_ERRORf, 1627 EMC_EWRB_1_BUFFER_0_CORRECTED_ERROR_DISINTf}, 1628 { 0 } /* table terminator */ 1629 }; 1630 1631 STATIC 1632 _soc_katana2_mmu_sub_block_internal_info_t 1633 _soc_katana2_mmu_sb_emc_parity_info [] = { 1634 { 0x0008, 1635 _SOC_KT2_MMU_LVL2_SUBBLOCK_EMC_ERROR_3, 1636 0, 1637 EMC_ERROR_3f, 1638 EMC_ERROR_MASK_3r, 1639 EMC_ERROR_3r, 1640 _soc_katana2_mmu_sb_emc3_parity_info }, 1641 1642 { 0x0004, 1643 _SOC_KT2_MMU_LVL2_SUBBLOCK_EMC_ERROR_2, 1644 0, 1645 EMC_ERROR_2f, 1646 EMC_ERROR_MASK_2r, 1647 EMC_ERROR_2r, 1648 _soc_katana2_mmu_sb_emc2_parity_info }, 1649 1650 { 0x0002, 1651 _SOC_KT2_MMU_LVL2_SUBBLOCK_EMC_ERROR_1, 1652 0, 1653 EMC_ERROR_1f, 1654 EMC_ERROR_MASK_1r, 1655 EMC_ERROR_1r, 1656 _soc_katana2_mmu_sb_emc1_parity_info }, 1657 1658 { 0x0001, 1659 _SOC_KT2_MMU_LVL2_SUBBLOCK_EMC_ERROR_0, 1660 0, 1661 EMC_ERROR_0f, 1662 EMC_ERROR_MASK_0r, 1663 EMC_ERROR_0r, 1664 _soc_katana2_mmu_sb_emc0_parity_info }, 1665 1666 { 0 } /* table terminator */ 1667 }; 1668 1669 STATIC 1670 _soc_katana2_mmu_sub_block_internal_info_t 1671 _soc_katana2_mmu_sb_toq_parity_info [] = { 1672 { 0x0002, 1673 _SOC_KT2_MMU_LVL2_SUBBLOCK_TOQ_ERROR_2, 1674 TOQ_ERROR2_DISINTf, 1675 TOQ_ERROR2f, 1676 TOQ_ERROR2_MASKr, 1677 TOQ_ERROR2r, 1678 _soc_katana2_mmu_sb_toq2_parity_info }, 1679 1680 { 0x0001, 1681 _SOC_KT2_MMU_LVL2_SUBBLOCK_TOQ_ERROR_1, 1682 TOQ_ERROR1_DISINTf, 1683 TOQ_ERROR1_ERRORf, 1684 TOQ_ERROR1_MASKr, 1685 TOQ_ERROR1r, 1686 _soc_katana2_mmu_sb_toq1_parity_info }, 1687 1688 { 0 } /* table terminator */ 1689 1690 }; 1691 1692 STATIC 1693 _soc_katana2_mmu_sub_block_leaf_info_t 1694 _soc_katana2_mmu_sb_deq0_parity_info [] = { 1695 { 0x0800, DEQ_RDE_TRACE_EVENTf, 1696 DEQ_RDE_TRACE_EVENT_DISINTf}, 1697 { 0x0400, CCBE_CONTROL_DATA_REPLICATION_CREDIT_RETURN_2_ERRORf, 1698 CCBE_CONTROL_DATA_REPLICATION_CREDIT_RETURN_2_ERROR_DISINTf}, 1699 { 0x0200, CCBE_CONTROL_DATA_REPLICATION_CREDIT_RETURN_1_ERRORf, 1700 CCBE_CONTROL_DATA_REPLICATION_CREDIT_RETURN_1_ERROR_DISINTf}, 1701 { 0x0100, CCBE_CONTROL_DATA_REPLICATION_ERRORf, 1702 CCBE_CONTROL_DATA_REPLICATION_ERROR_DISINTf}, 1703 { 0x0080, CELL_CLASSIFICATION_EXT_ERRORf, 1704 CELL_CLASSIFICATION_EXT_ERROR_DISINTf}, 1705 { 0x0040, CELL_CLASSIFICATION_INT_ERRORf, 1706 CELL_CLASSIFICATION_INT_ERROR_DISINTf}, 1707 { 0x0020, RD_CTRL_RD_REQ_DISCARD_ERRORf, 1708 RD_CTRL_RD_REQ_DISCARD_ERROR_DISINTf}, 1709 { 0x0010, DEQ_TRACE_EVENTf, 1710 DEQ_TRACE_EVENT_DISINTf}, 1711 { 0x0008, EGRESS_FIFO_OVERFLOW_ERRORf, 1712 EGRESS_FIFO_OVERFLOW_ERROR_DISINTf}, 1713 { 0x0004, EGRESS_FIFO_UNDERRUN_ERRORf, 1714 EGRESS_FIFO_UNDERRUN_ERROR_DISINTf}, 1715 { 0x0002, TOQ_TO_DEQ_CELL_REP_INFO_BUFFER_RD_REQ_ERRORf, 1716 DEQ_TO_CFG_TOQ_TO_DEQ_CELL_REP_INFO_BUFFER_RD_REQ_ERROR_DISINTf}, 1717 { 0x0001, TOQ_TO_DEQ_CELL_REP_INFO_BUFFER_WR_REQ_ERRORf, 1718 DEQ_TO_CFG_TOQ_TO_DEQ_CELL_REP_INFO_BUFFER_WR_REQ_ERROR_DISINTf}, 1719 { 0 } /* table terminator */ 1720 }; 1721 1722 STATIC 1723 _soc_katana2_mmu_sub_block_leaf_info_t 1724 _soc_katana2_mmu_sb_deq1_parity_info [] = { 1725 { 0x0200, PORT_41_EFIFO_UNDERRUN_ERRORf, 1726 PORT_41_EFIFO_UNDERRUN_ERROR_DISINTf}, 1727 { 0x0100, PORT_40_EFIFO_UNDERRUN_ERRORf, 1728 PORT_40_EFIFO_UNDERRUN_ERROR_DISINTf}, 1729 { 0x0080, PORT_39_EFIFO_UNDERRUN_ERRORf, 1730 PORT_39_EFIFO_UNDERRUN_ERROR_DISINTf}, 1731 { 0x0040, PORT_38_EFIFO_UNDERRUN_ERRORf, 1732 PORT_38_EFIFO_UNDERRUN_ERROR_DISINTf}, 1733 { 0x0020, PORT_37_EFIFO_UNDERRUN_ERRORf, 1734 PORT_37_EFIFO_UNDERRUN_ERROR_DISINTf}, 1735 { 0x0010, PORT_36_EFIFO_UNDERRUN_ERRORf, 1736 PORT_36_EFIFO_UNDERRUN_ERROR_DISINTf}, 1737 { 0x0008, PORT_35_EFIFO_UNDERRUN_ERRORf, 1738 PORT_35_EFIFO_UNDERRUN_ERROR_DISINTf}, 1739 { 0x0004, PORT_34_EFIFO_UNDERRUN_ERRORf, 1740 PORT_34_EFIFO_UNDERRUN_ERROR_DISINTf}, 1741 { 0x0002, PORT_33_EFIFO_UNDERRUN_ERRORf, 1742 PORT_33_EFIFO_UNDERRUN_ERROR_DISINTf}, 1743 { 0x0001, PORT_32_EFIFO_UNDERRUN_ERRORf, 1744 PORT_32_EFIFO_UNDERRUN_ERROR_DISINTf}, 1745 { 0 } /* table terminator */ 1746 }; 1747 1748 STATIC 1749 _soc_katana2_mmu_sub_block_leaf_info_t 1750 _soc_katana2_mmu_sb_deq2_parity_info [] = { 1751 { 0x80000000, PORT_31_EFIFO_UNDERRUN_ERRORf, 1752 PORT_31_EFIFO_UNDERRUN_ERROR_DISINTf}, 1753 { 0x40000000, PORT_30_EFIFO_UNDERRUN_ERRORf, 1754 PORT_30_EFIFO_UNDERRUN_ERROR_DISINTf}, 1755 { 0x20000000, PORT_29_EFIFO_UNDERRUN_ERRORf, 1756 PORT_29_EFIFO_UNDERRUN_ERROR_DISINTf}, 1757 { 0x10000000, PORT_28_EFIFO_UNDERRUN_ERRORf, 1758 PORT_28_EFIFO_UNDERRUN_ERROR_DISINTf}, 1759 { 0x08000000, PORT_27_EFIFO_UNDERRUN_ERRORf, 1760 PORT_27_EFIFO_UNDERRUN_ERROR_DISINTf}, 1761 { 0x04000000, PORT_26_EFIFO_UNDERRUN_ERRORf, 1762 PORT_26_EFIFO_UNDERRUN_ERROR_DISINTf}, 1763 { 0x02000000, PORT_25_EFIFO_UNDERRUN_ERRORf, 1764 PORT_25_EFIFO_UNDERRUN_ERROR_DISINTf}, 1765 { 0x01000000, PORT_24_EFIFO_UNDERRUN_ERRORf, 1766 PORT_24_EFIFO_UNDERRUN_ERROR_DISINTf}, 1767 { 0x00800000, PORT_23_EFIFO_UNDERRUN_ERRORf, 1768 PORT_23_EFIFO_UNDERRUN_ERROR_DISINTf}, 1769 { 0x00400000, PORT_22_EFIFO_UNDERRUN_ERRORf, 1770 PORT_22_EFIFO_UNDERRUN_ERROR_DISINTf}, 1771 { 0x00200000, PORT_21_EFIFO_UNDERRUN_ERRORf, 1772 PORT_21_EFIFO_UNDERRUN_ERROR_DISINTf}, 1773 { 0x00100000, PORT_20_EFIFO_UNDERRUN_ERRORf, 1774 PORT_20_EFIFO_UNDERRUN_ERROR_DISINTf}, 1775 { 0x00080000, PORT_19_EFIFO_UNDERRUN_ERRORf, 1776 PORT_19_EFIFO_UNDERRUN_ERROR_DISINTf}, 1777 { 0x00040000, PORT_18_EFIFO_UNDERRUN_ERRORf, 1778 PORT_18_EFIFO_UNDERRUN_ERROR_DISINTf}, 1779 { 0x00020000, PORT_17_EFIFO_UNDERRUN_ERRORf, 1780 PORT_17_EFIFO_UNDERRUN_ERROR_DISINTf}, 1781 { 0x00010000, PORT_16_EFIFO_UNDERRUN_ERRORf, 1782 PORT_16_EFIFO_UNDERRUN_ERROR_DISINTf}, 1783 { 0x00008000, PORT_15_EFIFO_UNDERRUN_ERRORf, 1784 PORT_15_EFIFO_UNDERRUN_ERROR_DISINTf}, 1785 { 0x00004000, PORT_14_EFIFO_UNDERRUN_ERRORf, 1786 PORT_14_EFIFO_UNDERRUN_ERROR_DISINTf}, 1787 { 0x00002000, PORT_13_EFIFO_UNDERRUN_ERRORf, 1788 PORT_13_EFIFO_UNDERRUN_ERROR_DISINTf}, 1789 { 0x00001000, PORT_12_EFIFO_UNDERRUN_ERRORf, 1790 PORT_12_EFIFO_UNDERRUN_ERROR_DISINTf}, 1791 { 0x00000800, PORT_11_EFIFO_UNDERRUN_ERRORf, 1792 PORT_11_EFIFO_UNDERRUN_ERROR_DISINTf}, 1793 { 0x00000400, PORT_10_EFIFO_UNDERRUN_ERRORf, 1794 PORT_10_EFIFO_UNDERRUN_ERROR_DISINTf}, 1795 { 0x00000200, PORT_09_EFIFO_UNDERRUN_ERRORf, 1796 PORT_09_EFIFO_UNDERRUN_ERROR_DISINTf}, 1797 { 0x00000100, PORT_08_EFIFO_UNDERRUN_ERRORf, 1798 PORT_08_EFIFO_UNDERRUN_ERROR_DISINTf}, 1799 { 0x00000080, PORT_07_EFIFO_UNDERRUN_ERRORf, 1800 PORT_07_EFIFO_UNDERRUN_ERROR_DISINTf}, 1801 { 0x00000040, PORT_06_EFIFO_UNDERRUN_ERRORf, 1802 PORT_06_EFIFO_UNDERRUN_ERROR_DISINTf}, 1803 { 0x00000020, PORT_05_EFIFO_UNDERRUN_ERRORf, 1804 PORT_05_EFIFO_UNDERRUN_ERROR_DISINTf}, 1805 { 0x00000010, PORT_04_EFIFO_UNDERRUN_ERRORf, 1806 PORT_04_EFIFO_UNDERRUN_ERROR_DISINTf}, 1807 { 0x00000008, PORT_03_EFIFO_UNDERRUN_ERRORf, 1808 PORT_03_EFIFO_UNDERRUN_ERROR_DISINTf}, 1809 { 0x00000004, PORT_02_EFIFO_UNDERRUN_ERRORf, 1810 PORT_02_EFIFO_UNDERRUN_ERROR_DISINTf}, 1811 { 0x00000002, PORT_01_EFIFO_UNDERRUN_ERRORf, 1812 PORT_01_EFIFO_UNDERRUN_ERROR_DISINTf}, 1813 { 0x00000001, PORT_00_EFIFO_UNDERRUN_ERRORf, 1814 PORT_00_EFIFO_UNDERRUN_ERROR_DISINTf}, 1815 { 0 } /* table terminator */ 1816 }; 1817 1818 STATIC 1819 _soc_katana2_mmu_sub_block_leaf_info_t 1820 _soc_katana2_mmu_sb_deq3_parity_info [] = { 1821 { 0x80000000, DEQ_CELL_CLASSIFICATION_EXT_ECC0_CHECK_2_UNCORRECTED_ERRORf, 1822 DEQ_CELL_CLASSIFICATION_EXT_ECC0_CHECK_2_UNCORRECTED_ERROR_DISINTf}, 1823 { 0x40000000, DEQ_CELL_CLASSIFICATION_EXT_ECC0_CHECK_2_CORRECTED_ERRORf, 1824 DEQ_CELL_CLASSIFICATION_EXT_ECC0_CHECK_2_CORRECTED_ERROR_DISINTf}, 1825 { 0x20000000, DEQ_CELL_CLASSIFICATION_EXT_ECC0_CHECK_1_UNCORRECTED_ERRORf, 1826 DEQ_CELL_CLASSIFICATION_EXT_ECC0_CHECK_1_UNCORRECTED_ERROR_DISINTf}, 1827 { 0x10000000, DEQ_CELL_CLASSIFICATION_EXT_ECC0_CHECK_1_CORRECTED_ERRORf, 1828 DEQ_CELL_CLASSIFICATION_EXT_ECC0_CHECK_1_CORRECTED_ERROR_DISINTf}, 1829 { 0x08000000, DEQ_CELL_CLASSIFICATION_EXT_ECC0_CHECK_0_UNCORRECTED_ERRORf, 1830 DEQ_CELL_CLASSIFICATION_EXT_ECC0_CHECK_0_UNCORRECTED_ERROR_DISINTf}, 1831 { 0x04000000, DEQ_CELL_CLASSIFICATION_EXT_ECC0_CHECK_0_CORRECTED_ERRORf, 1832 DEQ_CELL_CLASSIFICATION_EXT_ECC0_CHECK_0_CORRECTED_ERROR_DISINTf}, 1833 { 0x02000000, DEQ_CELL_CLASSIFICATION_INT_ECC0_CHECK_2_UNCORRECTED_ERRORf, 1834 DEQ_CELL_CLASSIFICATION_INT_ECC0_CHECK_2_UNCORRECTED_ERROR_DISINTf}, 1835 { 0x01000000, DEQ_CELL_CLASSIFICATION_INT_ECC0_CHECK_2_CORRECTED_ERRORf, 1836 DEQ_CELL_CLASSIFICATION_INT_ECC0_CHECK_2_CORRECTED_ERROR_DISINTf}, 1837 { 0x00800000, DEQ_CELL_CLASSIFICATION_INT_ECC0_CHECK_1_UNCORRECTED_ERRORf, 1838 DEQ_CELL_CLASSIFICATION_INT_ECC0_CHECK_1_UNCORRECTED_ERROR_DISINTf}, 1839 { 0x00400000, DEQ_CELL_CLASSIFICATION_INT_ECC0_CHECK_1_CORRECTED_ERRORf, 1840 DEQ_CELL_CLASSIFICATION_INT_ECC0_CHECK_1_CORRECTED_ERROR_DISINTf}, 1841 { 0x00200000, DEQ_CELL_CLASSIFICATION_INT_ECC0_CHECK_0_UNCORRECTED_ERRORf, 1842 DEQ_CELL_CLASSIFICATION_INT_ECC0_CHECK_0_UNCORRECTED_ERROR_DISINTf}, 1843 { 0x00100000, DEQ_CELL_CLASSIFICATION_INT_ECC0_CHECK_0_CORRECTED_ERRORf, 1844 DEQ_CELL_CLASSIFICATION_INT_ECC0_CHECK_0_CORRECTED_ERROR_DISINTf}, 1845 { 0x00080000, DEQ_EP_REDIRECT_BUFFER_2_UNCORRECTED_ERRORf, 1846 DEQ_EP_REDIRECT_BUFFER_2_UNCORRECTED_ERROR_DISINTf}, 1847 { 0x00040000, DEQ_EP_REDIRECT_BUFFER_2_CORRECTED_ERRORf, 1848 DEQ_EP_REDIRECT_BUFFER_2_CORRECTED_ERROR_DISINTf}, 1849 { 0x00020000, DEQ_EP_REDIRECT_BUFFER_1_UNCORRECTED_ERRORf, 1850 DEQ_EP_REDIRECT_BUFFER_1_UNCORRECTED_ERROR_DISINTf}, 1851 { 0x00010000, DEQ_EP_REDIRECT_BUFFER_1_CORRECTED_ERRORf, 1852 DEQ_EP_REDIRECT_BUFFER_1_CORRECTED_ERROR_DISINTf}, 1853 { 0x00008000, DEQ_EP_REDIRECT_BUFFER_0_UNCORRECTED_ERRORf, 1854 DEQ_EP_REDIRECT_BUFFER_0_UNCORRECTED_ERROR_DISINTf}, 1855 { 0x00004000, DEQ_EP_REDIRECT_BUFFER_0_CORRECTED_ERRORf, 1856 DEQ_EP_REDIRECT_BUFFER_0_CORRECTED_ERROR_DISINTf}, 1857 { 0x00002000, DEQ_PST_EGRESS_FIFO_ECC_VERIF_EXT_1520_UNCORRECTED_ERRORf, 1858 DEQ_PST_EGRESS_FIFO_ECC_VERIF_EXT_1520_UNCORRECTED_ERROR_DISINTf}, 1859 { 0x00001000, DEQ_PST_EGRESS_FIFO_ECC_VERIF_EXT_1520_CORRECTED_ERRORf, 1860 DEQ_PST_EGRESS_FIFO_ECC_VERIF_EXT_1520_CORRECTED_ERROR_DISINTf}, 1861 { 0x00000800, DEQ_PST_EGRESS_FIFO_ECC_VERIF_EXT_57_UNCORRECTED_ERRORf, 1862 DEQ_PST_EGRESS_FIFO_ECC_VERIF_EXT_57_UNCORRECTED_ERROR_DISINTf}, 1863 { 0x00000400, DEQ_PST_EGRESS_FIFO_ECC_VERIF_EXT_57_CORRECTED_ERRORf, 1864 DEQ_PST_EGRESS_FIFO_ECC_VERIF_EXT_57_CORRECTED_ERROR_DISINTf}, 1865 { 0x00000200, DEQ_PST_EGRESS_FIFO_ECC_VERIF_INT_1520_UNCORRECTED_ERRORf, 1866 DEQ_PST_EGRESS_FIFO_ECC_VERIF_INT_1520_UNCORRECTED_ERROR_DISINTf}, 1867 { 0x00000100, DEQ_PST_EGRESS_FIFO_ECC_VERIF_INT_1520_CORRECTED_ERRORf, 1868 DEQ_PST_EGRESS_FIFO_ECC_VERIF_INT_1520_CORRECTED_ERROR_DISINTf}, 1869 { 0x00000080, DEQ_PST_EGRESS_FIFO_ECC_VERIF_INT_57_UNCORRECTED_ERRORf, 1870 DEQ_PST_EGRESS_FIFO_ECC_VERIF_INT_57_UNCORRECTED_ERROR_DISINTf}, 1871 { 0x00000040, DEQ_PST_EGRESS_FIFO_ECC_VERIF_INT_57_CORRECTED_ERRORf, 1872 DEQ_PST_EGRESS_FIFO_ECC_VERIF_INT_57_CORRECTED_ERROR_DISINTf}, 1873 { 0x00000020, DEQ_EGRESS_FIFO_CONTROL_DATA_MEMORY_UNCORRECTED_ERRORf, 1874 DEQ_EGRESS_FIFO_CONTROL_DATA_MEMORY_UNCORRECTED_ERROR_DISINTf}, 1875 { 0x00000010, DEQ_EGRESS_FIFO_CONTROL_DATA_MEMORY_CORRECTED_ERRORf, 1876 DEQ_EGRESS_FIFO_CONTROL_DATA_MEMORY_CORRECTED_ERROR_DISINTf}, 1877 { 0x00000008, DEQ_AGING_MASK_MEMORY_UNCORRECTED_ERRORf, 1878 DEQ_AGING_MASK_MEMORY_UNCORRECTED_ERROR_DISINTf}, 1879 { 0x00000004, DEQ_AGING_MASK_MEMORY_CORRECTED_ERRORf, 1880 DEQ_AGING_MASK_MEMORY_CORRECTED_ERROR_DISINTf}, 1881 { 0x00000002, DEQ_TOQ_CELL_REP_INFO_BUFFER_UNCORRECTED_ERRORf, 1882 DEQ_TOQ_CELL_REP_INFO_BUFFER_UNCORRECTED_ERROR_DISINTf}, 1883 { 0x00000001, DEQ_TOQ_CELL_REP_INFO_BUFFER_CORRECTED_ERRORf, 1884 DEQ_TOQ_CELL_REP_INFO_BUFFER_CORRECTED_ERROR_DISINTf}, 1885 { 0 } /* table terminator */ 1886 }; 1887 1888 STATIC 1889 _soc_katana2_mmu_sub_block_leaf_info_t 1890 _soc_katana2_mmu_sb_deq4_parity_info [] = { 1891 { 0x00000002, DEQ_OPQ_CELL_INFO_BUFFER_UNCORRECTED_ERRORf, 1892 DEQ_OPQ_CELL_INFO_BUFFER_UNCORRECTED_ERROR_DISINTf}, 1893 { 0x00000001, DEQ_OPQ_CELL_INFO_BUFFER_CORRECTED_ERRORf, 1894 DEQ_OPQ_CELL_INFO_BUFFER_CORRECTED_ERROR_DISINTf}, 1895 { 0 } /* table terminator */ 1896 }; 1897 1898 STATIC _soc_katana2_mmu_sub_block_internal_info_t 1899 _soc_katana2_mmu_sb_deq_parity_info [] = { 1900 { 0x0010, 1901 _SOC_KT2_MMU_LVL2_SUBBLOCK_DEQ_ERROR_4, 1902 0, 1903 DEQ_ERROR_4f, 1904 DEQ_ERROR_MASK_4r, 1905 DEQ_ERROR_4r, 1906 _soc_katana2_mmu_sb_deq4_parity_info }, 1907 1908 { 0x0008, 1909 _SOC_KT2_MMU_LVL2_SUBBLOCK_DEQ_ERROR_3, 1910 0, 1911 DEQ_ERROR_3f, 1912 DEQ_ERROR_MASK_3r, 1913 DEQ_ERROR_3r, 1914 _soc_katana2_mmu_sb_deq3_parity_info }, 1915 1916 { 0x0004, 1917 _SOC_KT2_MMU_LVL2_SUBBLOCK_DEQ_ERROR_2, 1918 0, 1919 DEQ_ERROR_2f, 1920 DEQ_ERROR_MASK_2r, 1921 DEQ_ERROR_2r, 1922 _soc_katana2_mmu_sb_deq2_parity_info }, 1923 1924 { 0x0002, 1925 _SOC_KT2_MMU_LVL2_SUBBLOCK_DEQ_ERROR_1, 1926 0, 1927 DEQ_ERROR_1f, 1928 DEQ_ERROR_MASK_1r, 1929 DEQ_ERROR_1r, 1930 _soc_katana2_mmu_sb_deq1_parity_info }, 1931 1932 { 0x0001, 1933 _SOC_KT2_MMU_LVL2_SUBBLOCK_DEQ_ERROR_0, 1934 0, 1935 DEQ_ERROR_0f, 1936 DEQ_ERROR_MASK_0r, 1937 DEQ_ERROR_0r, 1938 _soc_katana2_mmu_sb_deq0_parity_info }, 1939 { 0 } /* table terminator */ 1940 }; 1941 1942 STATIC _soc_katana2_mmu_sub_block_leaf_info_t 1943 _soc_katana2_mmu_sb_qstruct_fap_parity_info [] = { 1944 { 0x100000, FAP3_DUPLICATE_PTR_ERRORf, 1945 FAP3_DUPLICATE_PTR_ERROR_DISINTf}, 1946 { 0x80000, FAP2_DUPLICATE_PTR_ERRORf, 1947 FAP2_DUPLICATE_PTR_ERROR_DISINTf}, 1948 { 0x40000, FAP1_DUPLICATE_PTR_ERRORf, 1949 FAP1_DUPLICATE_PTR_ERROR_DISINTf}, 1950 { 0x20000, FAP0_DUPLICATE_PTR_ERRORf, 1951 FAP0_DUPLICATE_PTR_ERROR_DISINTf}, 1952 { 0x10000, FAP_LOADING_ERRORf, 1953 FAP_LOADING_ERROR_DISINTf}, 1954 { 0x8000, CORRECTED_BITMAP_ERROR_3f, 1955 CORRECTED_BITMAP_ERROR_3_DISINTf}, 1956 { 0x4000, UNCORRECTED_BITMAP_ERROR_3f, 1957 UNCORRECTED_BITMAP_ERROR_3_DISINTf}, 1958 { 0x2000, CORRECTED_STACK_ERROR_3f, 1959 CORRECTED_STACK_ERROR_3_DISINTf}, 1960 { 0x1000, UNCORRECTED_STACK_ERROR_3f, 1961 UNCORRECTED_STACK_ERROR_3_DISINTf}, 1962 { 0x0800, CORRECTED_BITMAP_ERROR_2f, 1963 CORRECTED_BITMAP_ERROR_2_DISINTf}, 1964 { 0x0400, UNCORRECTED_BITMAP_ERROR_2f, 1965 UNCORRECTED_BITMAP_ERROR_2_DISINTf}, 1966 { 0x0200, CORRECTED_STACK_ERROR_2f, 1967 CORRECTED_STACK_ERROR_2_DISINTf}, 1968 { 0x0100, UNCORRECTED_STACK_ERROR_2f, 1969 UNCORRECTED_STACK_ERROR_2_DISINTf}, 1970 { 0x0080, CORRECTED_BITMAP_ERROR_1f, 1971 CORRECTED_BITMAP_ERROR_1_DISINTf}, 1972 { 0x0040, UNCORRECTED_BITMAP_ERROR_1f, 1973 UNCORRECTED_BITMAP_ERROR_1_DISINTf}, 1974 { 0x0020, CORRECTED_STACK_ERROR_1f, 1975 CORRECTED_STACK_ERROR_1_DISINTf}, 1976 { 0x0010, UNCORRECTED_STACK_ERROR_1f, 1977 UNCORRECTED_STACK_ERROR_1_DISINTf}, 1978 { 0x0008, CORRECTED_BITMAP_ERROR_0f, 1979 CORRECTED_BITMAP_ERROR_0_DISINTf}, 1980 { 0x0004, UNCORRECTED_BITMAP_ERROR_0f, 1981 UNCORRECTED_BITMAP_ERROR_0_DISINTf}, 1982 { 0x0002, CORRECTED_STACK_ERROR_0f, 1983 CORRECTED_STACK_ERROR_0_DISINTf}, 1984 { 0x0001, UNCORRECTED_STACK_ERROR_0f, 1985 UNCORRECTED_STACK_ERROR_0_DISINTf}, 1986 { 0 } /* table terminator */ 1987 }; 1988 1989 STATIC _soc_katana2_mmu_sub_block_leaf_info_t 1990 _soc_katana2_mmu_sb_qstruct_qentry_upper_parity_info [] = { 1991 { 0x8000, CORRECTED_ERROR_7f, 1992 CORRECTED_ERROR_7_DISINTf}, 1993 { 0x4000, UNCORRECTED_ERROR_7f, 1994 UNCORRECTED_ERROR_7_DISINTf}, 1995 { 0x2000, CORRECTED_ERROR_6f, 1996 CORRECTED_ERROR_6_DISINTf}, 1997 { 0x1000, UNCORRECTED_ERROR_6f, 1998 UNCORRECTED_ERROR_6_DISINTf}, 1999 { 0x0800, CORRECTED_ERROR_5f, 2000 CORRECTED_ERROR_5_DISINTf}, 2001 { 0x0400, UNCORRECTED_ERROR_5f, 2002 UNCORRECTED_ERROR_5_DISINTf}, 2003 { 0x0200, CORRECTED_ERROR_4f, 2004 CORRECTED_ERROR_4_DISINTf}, 2005 { 0x0100, UNCORRECTED_ERROR_4f, 2006 UNCORRECTED_ERROR_4_DISINTf}, 2007 { 0x0080, CORRECTED_ERROR_3f, 2008 CORRECTED_ERROR_3_DISINTf}, 2009 { 0x0040, UNCORRECTED_ERROR_3f, 2010 UNCORRECTED_ERROR_3_DISINTf}, 2011 { 0x0020, CORRECTED_ERROR_2f, 2012 CORRECTED_ERROR_2_DISINTf}, 2013 { 0x0010, UNCORRECTED_ERROR_2f, 2014 UNCORRECTED_ERROR_2_DISINTf}, 2015 { 0x0008, CORRECTED_ERROR_1f, 2016 CORRECTED_ERROR_1_DISINTf}, 2017 { 0x0004, UNCORRECTED_ERROR_1f, 2018 UNCORRECTED_ERROR_1_DISINTf}, 2019 { 0x0002, CORRECTED_ERROR_0f, 2020 CORRECTED_ERROR_0_DISINTf}, 2021 { 0x0001, UNCORRECTED_ERROR_0f, 2022 UNCORRECTED_ERROR_0_DISINTf}, 2023 { 0 } /* table terminator */ 2024 }; 2025 2026 STATIC _soc_katana2_mmu_sub_block_leaf_info_t 2027 _soc_katana2_mmu_sb_qstruct_qentry_lower_parity_info [] = { 2028 { 0x8000, CORRECTED_ERROR_7f, 2029 CORRECTED_ERROR_7_DISINTf}, 2030 { 0x4000, UNCORRECTED_ERROR_7f, 2031 UNCORRECTED_ERROR_7_DISINTf}, 2032 { 0x2000, CORRECTED_ERROR_6f, 2033 CORRECTED_ERROR_6_DISINTf}, 2034 { 0x1000, UNCORRECTED_ERROR_6f, 2035 UNCORRECTED_ERROR_6_DISINTf}, 2036 { 0x0800, CORRECTED_ERROR_5f, 2037 CORRECTED_ERROR_5_DISINTf}, 2038 { 0x0400, UNCORRECTED_ERROR_5f, 2039 UNCORRECTED_ERROR_5_DISINTf}, 2040 { 0x0200, CORRECTED_ERROR_4f, 2041 CORRECTED_ERROR_4_DISINTf}, 2042 { 0x0100, UNCORRECTED_ERROR_4f, 2043 UNCORRECTED_ERROR_4_DISINTf}, 2044 { 0x0080, CORRECTED_ERROR_3f, 2045 CORRECTED_ERROR_3_DISINTf}, 2046 { 0x0040, UNCORRECTED_ERROR_3f, 2047 UNCORRECTED_ERROR_3_DISINTf}, 2048 { 0x0020, CORRECTED_ERROR_2f, 2049 CORRECTED_ERROR_2_DISINTf}, 2050 { 0x0010, UNCORRECTED_ERROR_2f, 2051 UNCORRECTED_ERROR_2_DISINTf}, 2052 { 0x0008, CORRECTED_ERROR_1f, 2053 CORRECTED_ERROR_1_DISINTf}, 2054 { 0x0004, UNCORRECTED_ERROR_1f, 2055 UNCORRECTED_ERROR_1_DISINTf}, 2056 { 0x0002, CORRECTED_ERROR_0f, 2057 CORRECTED_ERROR_0_DISINTf}, 2058 { 0x0001, UNCORRECTED_ERROR_0f, 2059 UNCORRECTED_ERROR_0_DISINTf}, 2060 { 0 } /* table terminator */ 2061 }; 2062 2063 STATIC _soc_katana2_mmu_sub_block_leaf_info_t 2064 _soc_katana2_mmu_sb_qstruct_qentry_qblock_nxt_parity_info [] = { 2065 { 0x8000, CORRECTED_ERROR_7f, 2066 CORRECTED_ERROR_7_DISINTf}, 2067 { 0x4000, UNCORRECTED_ERROR_7f, 2068 UNCORRECTED_ERROR_7_DISINTf}, 2069 { 0x2000, CORRECTED_ERROR_6f, 2070 CORRECTED_ERROR_6_DISINTf}, 2071 { 0x1000, UNCORRECTED_ERROR_6f, 2072 UNCORRECTED_ERROR_6_DISINTf}, 2073 { 0x0800, CORRECTED_ERROR_5f, 2074 CORRECTED_ERROR_5_DISINTf}, 2075 { 0x0400, UNCORRECTED_ERROR_5f, 2076 UNCORRECTED_ERROR_5_DISINTf}, 2077 { 0x0200, CORRECTED_ERROR_4f, 2078 CORRECTED_ERROR_4_DISINTf}, 2079 { 0x0100, UNCORRECTED_ERROR_4f, 2080 UNCORRECTED_ERROR_4_DISINTf}, 2081 { 0x0080, CORRECTED_ERROR_3f, 2082 CORRECTED_ERROR_3_DISINTf}, 2083 { 0x0040, UNCORRECTED_ERROR_3f, 2084 UNCORRECTED_ERROR_3_DISINTf}, 2085 { 0x0020, CORRECTED_ERROR_2f, 2086 CORRECTED_ERROR_2_DISINTf}, 2087 { 0x0010, UNCORRECTED_ERROR_2f, 2088 UNCORRECTED_ERROR_2_DISINTf}, 2089 { 0x0008, CORRECTED_ERROR_1f, 2090 CORRECTED_ERROR_1_DISINTf}, 2091 { 0x0004, UNCORRECTED_ERROR_1f, 2092 UNCORRECTED_ERROR_1_DISINTf}, 2093 { 0x0002, CORRECTED_ERROR_0f, 2094 CORRECTED_ERROR_0_DISINTf}, 2095 { 0x0001, UNCORRECTED_ERROR_0f, 2096 UNCORRECTED_ERROR_0_DISINTf}, 2097 { 0 } /* table terminator */ 2098 }; 2099 2100 STATIC _soc_katana2_mmu_sub_block_internal_info_t 2101 _soc_katana2_mmu_sb_qstruct_parity_info [] = { 2102 { 0x0008, 2103 _SOC_KT2_MMU_LVL2_SUBBLOCK_QSTRUCT_FAP, 2104 QENTRY_FAP_ERROR_DISINTf, 2105 QENTRY_FAP_ERRORf, 2106 QSTRUCT_FAP_MEM_ERROR_MASKr, 2107 QSTRUCT_FAP_MEM_ERRORr, 2108 _soc_katana2_mmu_sb_qstruct_fap_parity_info }, 2109 2110 { 0x0004, 2111 _SOC_KT2_MMU_LVL2_SUBBLOCK_QSTRUCT_QENTRY_U, 2112 QENTRY_UPPER_ERROR_DISINTf, 2113 QENTRY_UPPER_ERRORf, 2114 QSTRUCT_QENTRY_UPPER_ERROR_MASKr, 2115 QSTRUCT_QENTRY_UPPER_ERRORr, 2116 _soc_katana2_mmu_sb_qstruct_qentry_upper_parity_info }, 2117 2118 { 0x0002, 2119 _SOC_KT2_MMU_LVL2_SUBBLOCK_QSTRUCT_QENTRY_L, 2120 QENTRY_LOWER_ERROR_DISINTf, 2121 QENTRY_LOWER_ERRORf, 2122 QSTRUCT_QENTRY_LOWER_ERROR_MASKr, 2123 QSTRUCT_QENTRY_LOWER_ERRORr, 2124 _soc_katana2_mmu_sb_qstruct_qentry_lower_parity_info }, 2125 2126 { 0x0001, 2127 _SOC_KT2_MMU_LVL2_SUBBLOCK_QSTRUCT_QBLOCK, 2128 QBLOCK_NEXT_ERROR_DISINTf, 2129 QBLOCK_NEXT_ERRORf, 2130 QSTRUCT_QBLOCK_NEXT_ERROR_MASKr, 2131 QSTRUCT_QBLOCK_NEXT_ERRORr, 2132 _soc_katana2_mmu_sb_qstruct_qentry_qblock_nxt_parity_info }, 2133 { 0 } /* table terminator */ 2134 }; 2135 2136 STATIC 2137 _soc_katana2_mmu_sub_block_leaf_info_t 2138 _soc_katana2_mmu_sb_wred_parity_info [] = { 2139 { 0x4000000, UPDATE_INTRPT_STATUSf, 2140 UPDATE_INTRPT_MASKf }, 2141 { 0x3ffe000, ECC_ERROR_1Bf, 2142 ECC_1B_ERROR_MASKf }, 2143 { 0x1fff, ECC_ERROR_2Bf, 2144 ECC_2B_ERROR_MASKf }, 2145 { 0 } /* table terminator */ 2146 2147 }; 2148 2149 STATIC _soc_katana2_mmu_sub_block_leaf_info_t 2150 _soc_katana2_mmu_sb_rqe_ser_parity_info [] = { 2151 { 0x1000000, NULL_REPL_PKTf, NULL_REPL_PKT_MASKf }, 2152 { 0x0800000, FLL_EMPTYf, FLL_EMPTY_MASKf }, 2153 { 0x0400000, EXTQ_LL_ERRORf, EXTQ_LL_ERROR_MASKf }, 2154 { 0x03ff100, ECC_1B_BITMAPf, ECC_1B_MASKf }, 2155 { 0x00007ff, ECC_2B_BITMAPf, ECC_2B_MASKf }, 2156 { 0 } /* table terminator */ 2157 }; 2158 2159 2160 STATIC 2161 _soc_katana2_mmu_sub_block_one_level_t _soc_katana2_mmu_sub_blocks_type_1[] = { 2162 { 0x08000000, 2163 _SOC_KT2_MMU_SUBBLOCK_IPCTR, 2164 IPCTR_INTR_DISINTf, 2165 IPCTR_INTRf, 2166 MMU_IPCTR_ECC_ERROR_0_MASKr, 2167 MMU_IPCTR_ECC_ERROR_0r, 2168 _soc_katana2_mmu_sb_ipctr_parity_info }, 2169 2170 { 0x04000000, 2171 _SOC_KT2_MMU_SUBBLOCK_ADM, 2172 ADM_INTR_DISINTf, 2173 ADM_INTRf, 2174 MMU_ADM_ECC_ERROR_0_MASKr, 2175 MMU_ADM_ECC_ERROR_0r, 2176 _soc_katana2_mmu_sb_adm_parity_info }, 2177 2178 { 0x02000000, 2179 _SOC_KT2_MMU_SUBBLOCK_RDE, 2180 RDE_INTR_DISINTf, 2181 RDE_INTRf, 2182 RDE_SER_MASKr, 2183 RDE_SER_STATUSr, 2184 _soc_katana2_mmu_sb_rde_parity_info }, 2185 2186 { 0x00800000, 2187 _SOC_KT2_MMU_SUBBLOCK_CI5, 2188 CI5_INTR_DISINTf, 2189 CI5_INTRf, 2190 CI_ERROR_MASKr, 2191 CI_ERRORr, 2192 _soc_katana2_mmu_sb_ci_parity_info }, 2193 2194 { 0x00400000, 2195 _SOC_KT2_MMU_SUBBLOCK_CI4, 2196 CI4_INTR_DISINTf, 2197 CI4_INTRf, 2198 CI_ERROR_MASKr, 2199 CI_ERRORr, 2200 _soc_katana2_mmu_sb_ci_parity_info }, 2201 2202 { 0x00200000, 2203 _SOC_KT2_MMU_SUBBLOCK_CI3, 2204 CI3_INTR_DISINTf, 2205 CI3_INTRf, 2206 CI_ERROR_MASKr, 2207 CI_ERRORr, 2208 _soc_katana2_mmu_sb_ci_parity_info }, 2209 2210 { 0x00100000, 2211 _SOC_KT2_MMU_SUBBLOCK_MEM1, 2212 MEM1_INTR_DISINTf, 2213 MEM1_INTRf, 2214 CLINK_ERROR_MASKr, 2215 CLINK_ERRORr, 2216 _soc_katana2_mmu_sb_mem1_parity_info }, 2217 2218 { 0x00040000, 2219 _SOC_KT2_MMU_SUBBLOCK_E2EFC, 2220 E2EFC_INTR_DISINTf, 2221 E2EFC_INTRf, 2222 MMU_E2EFC_ERROR_0_MASKr, 2223 MMU_E2EFC_ERROR_0r, 2224 _soc_katana2_mmu_sb_e2efc_parity_info}, 2225 2226 { 0x00010000, 2227 _SOC_KT2_MMU_SUBBLOCK_THDI, 2228 THDI_INTR_DISINTf, 2229 THDI_INTRf, 2230 MMU_THDI_INTR_MASKr, 2231 MMU_THDI_INTRr, 2232 _soc_katana2_mmu_sb_thdi_parity_info}, 2233 2234 { 0x00000800, 2235 _SOC_KT2_MMU_SUBBLOCK_WRED, 2236 WRED_INTR_DISINTf, 2237 WRED_INTRf, 2238 WRED_PARITY_ERROR_MASKr, 2239 WRED_PARITY_ERROR_BITMAPr, 2240 _soc_katana2_mmu_sb_wred_parity_info}, 2241 2242 { 0x00000040, 2243 _SOC_KT2_MMU_SUBBLOCK_CTR, 2244 CTR_INTR_DISINTf, 2245 CTR_INTRf, 2246 CTR_ERROR_MASKr, 2247 CTR_ERRORr, 2248 _soc_katana2_mmu_sb_ctr_parity_info}, 2249 2250 { 0x00000010, 2251 _SOC_KT2_MMU_SUBBLOCK_CCP, 2252 CCP_INTR_DISINTf, 2253 CCP_INTRf, 2254 CCP_ERROR_MASKr, 2255 CCP_ERRORr, 2256 _soc_katana2_mmu_sb_ccp_parity_info}, 2257 2258 { 0x00020000, 2259 _SOC_KT2_MMU_SUBBLOCK_ITE, 2260 ITE_INTR_DISINTf, 2261 ITE_INTRf, 2262 MMU_ITE_ERROR_0_MASKr, 2263 MMU_ITE_ERROR_0r, 2264 _soc_katana2_mmu_sb_ite_parity_info}, 2265 2266 { 0x00020000, 2267 _SOC_KT2_MMU_SUBBLOCK_ITE_CFG, 2268 ITE_INTR_DISINTf, 2269 ITE_INTRf, 2270 MMU_ITE_CFG_ECC_ERROR_0_MASKr, 2271 MMU_ITE_CFG_ECC_ERROR_0r, 2272 _soc_katana2_mmu_sb_ite_cfg_parity_info}, 2273 2274 { 0x00008000, 2275 _SOC_KT2_MMU_SUBBLOCK_ENQ_CFG, 2276 ENQ_INTR_DISINTf, 2277 ENQ_INTRf, 2278 MMU_ENQ_CFG_ECC_ERROR_0_MASKr, 2279 MMU_ENQ_CFG_ECC_ERROR_0r, 2280 _soc_katana2_mmu_sb_enq_cfg_parity_info}, 2281 2282 { 0x00008000, 2283 _SOC_KT2_MMU_SUBBLOCK_ENQ, 2284 ENQ_INTR_DISINTf, 2285 ENQ_INTRf, 2286 MMU_ENQ_ERROR_0_MASKr, 2287 MMU_ENQ_ERROR_0r, 2288 _soc_katana2_mmu_sb_enq_parity_info}, 2289 2290 { 0x00008000, 2291 _SOC_KT2_MMU_SUBBLOCK_ENQ_FAP, 2292 ENQ_INTR_DISINTf, 2293 ENQ_INTRf, 2294 MMU_ENQ_FAP_ECC_ERROR_0_MASKr, 2295 MMU_ENQ_FAP_ECC_ERROR_0r, 2296 _soc_katana2_mmu_sb_enq_fap_parity_info}, 2297 2298 { 0x00000400, 2299 _SOC_KT2_MMU_SUBBLOCK_THDO_STATUS1, 2300 THDO_INTR_DISINTf, 2301 THDO_INTRf, 2302 THDO_PARITY_ERROR_MASK1r, 2303 THDO_PARITY_ERROR_STATUS1r, 2304 _soc_katana2_mmu_sb_thdo_stat1_parity_info}, 2305 2306 { 0x00000400, 2307 _SOC_KT2_MMU_SUBBLOCK_THDO_STATUS2, 2308 THDO_INTR_DISINTf, 2309 THDO_INTRf, 2310 THDO_PARITY_ERROR_MASK2r, 2311 THDO_PARITY_ERROR_STATUS2r, 2312 _soc_katana2_mmu_sb_thdo_stat2_parity_info}, 2313 2314 { 0x00000020, 2315 _SOC_KT2_MMU_SUBBLOCK_CFAPI, 2316 CFAP_INTR_DISINTf, 2317 CFAP_INTRf, 2318 CFAPI_ERROR_MASKr, 2319 CFAPI_ECC_ERRORr, 2320 _soc_katana2_mmu_sb_cfapi_parity_info}, 2321 2322 { 0x00000020, 2323 _SOC_KT2_MMU_SUBBLOCK_CFAPE, 2324 CFAP_INTR_DISINTf, 2325 CFAP_INTRf, 2326 CFAPE_ERROR_MASKr, 2327 CFAPE_ECC_ERRORr, 2328 _soc_katana2_mmu_sb_cfape_parity_info}, 2329 2330 { 0x00000008, 2331 _SOC_KT2_MMU_SUBBLOCK_AGING_INT, 2332 AGING_INTR_DISINTf, 2333 AGING_INTRf, 2334 AGING_ERROR_MASK_INTr, 2335 AGING_ERROR_INTr, 2336 _soc_katana2_mmu_sb_age_int_parity_info}, 2337 2338 { 0x00000008, 2339 _SOC_KT2_MMU_SUBBLOCK_AGING_EXT, 2340 AGING_INTR_DISINTf, 2341 AGING_INTRf, 2342 AGING_ERROR_MASK_EXTr, 2343 AGING_ERROR_EXTr, 2344 _soc_katana2_mmu_sb_age_ext_parity_info}, 2345 2346 { 0x00004000, 2347 _SOC_KT2_MMU_SUBBLOCK_CI2, 2348 CI2_INTR_DISINTf, 2349 CI2_INTRf, 2350 CI_ERROR_MASKr, 2351 CI_ERRORr, 2352 _soc_katana2_mmu_sb_ci_parity_info}, 2353 2354 { 0x00002000, 2355 _SOC_KT2_MMU_SUBBLOCK_CI1, 2356 CI1_INTR_DISINTf, 2357 CI1_INTRf, 2358 CI_ERROR_MASKr, 2359 CI_ERRORr, 2360 _soc_katana2_mmu_sb_ci_parity_info}, 2361 2362 { 0x00001000, 2363 _SOC_KT2_MMU_SUBBLOCK_CI0, 2364 CI0_INTR_DISINTf, 2365 CI0_INTRf, 2366 CI_ERROR_MASKr, 2367 CI_ERRORr, 2368 _soc_katana2_mmu_sb_ci_parity_info}, 2369 2370 { 0x00000004, 2371 _SOC_KT2_MMU_SUBBLOCK_LLS, 2372 LLS_INTR_DISINTf, 2373 LLS_INTRf, 2374 LLS_ERROR_MASKr, 2375 LLS_ERRORr, 2376 _soc_katana2_mmu_sb_lls_parity_info}, 2377 2378 { 0x00000004, 2379 _SOC_KT2_MMU_SUBBLOCK_LLS_PORT, 2380 LLS_INTR_DISINTf, 2381 LLS_INTRf, 2382 LLS_PORT_ECC_ERROR_MASKr, 2383 LLS_PORT_ECC_ERRORr, 2384 _soc_katana2_mmu_sb_lls_port_parity_info}, 2385 2386 { 0x00000004, 2387 _SOC_KT2_MMU_SUBBLOCK_LLS, 2388 LLS_INTR_DISINTf, 2389 LLS_INTRf, 2390 LLS_ERROR2_MASKr, 2391 LLS_ERROR2r, 2392 _soc_katana2_mmu_sb_lls2_parity_info}, 2393 2394 2395 { 0x00000004, 2396 _SOC_KT2_MMU_SUBBLOCK_LLS_UPD2, 2397 LLS_INTR_DISINTf, 2398 LLS_INTRf, 2399 LLS_ERROR_UPD2_MASKr, 2400 LLS_ERROR_UPD2r, 2401 _soc_katana2_mmu_sb_lls_upd2_parity_info}, 2402 2403 { 0x00000004, 2404 _SOC_KT2_MMU_SUBBLOCK_LLS_L0_ECC, 2405 LLS_INTR_DISINTf, 2406 LLS_INTRf, 2407 LLS_L0_ECC_ERROR1_MASKr, 2408 LLS_L0_ECC_ERROR1r, 2409 _soc_katana2_mmu_sb_lls_l0_ecc_parity_info}, 2410 2411 { 0x00000004, 2412 _SOC_KT2_MMU_SUBBLOCK_LLS_L1_ECC, 2413 LLS_INTR_DISINTf, 2414 LLS_INTRf, 2415 LLS_L1_ECC_ERROR1_MASKr, 2416 LLS_L1_ECC_ERROR1r, 2417 _soc_katana2_mmu_sb_lls_l1_ecc_parity_info}, 2418 2419 { 0x00000004, 2420 _SOC_KT2_MMU_SUBBLOCK_LLS_L2_ECC, 2421 LLS_INTR_DISINTf, 2422 LLS_INTRf, 2423 LLS_L2_ECC_ERROR1_MASKr, 2424 LLS_L2_ECC_ERROR1r, 2425 _soc_katana2_mmu_sb_lls_l2_ecc_parity_info}, 2426 2427 { 0x00000004, 2428 _SOC_KT2_MMU_SUBBLOCK_LLS_MISC_ECC, 2429 LLS_INTR_DISINTf, 2430 LLS_INTRf, 2431 LLS_MISC_ECC_ERROR1_MASKr, 2432 LLS_MISC_ECC_ERROR1r, 2433 _soc_katana2_mmu_sb_lls_misc_ecc_parity_info}, 2434 2435 /* RQE Ser gives MMU parity error while accessing IPMC group 2436 tables. Hence, disabling parity for this */ 2437 { 0x00000200, 2438 _SOC_KT2_MMU_SUBBLOCK_RQE_SER, 2439 RQE_INTR_DISINTf, 2440 RQE_INTRf, 2441 RQE_SER_MASKr, 2442 RQE_SER_STATUSr, 2443 _soc_katana2_mmu_sb_rqe_ser_parity_info}, 2444 2445 { 0x00000200, 2446 _SOC_KT2_MMU_SUBBLOCK_RQE_EXTQ, 2447 RQE_INTR_DISINTf, 2448 RQE_INTRf, 2449 RQE_EXTQ_REPLICATION_LIMITr, 2450 RQE_EXTQ_REPLICATION_COUNTr, 2451 _soc_katana2_mmu_sb_rqe_extq_parity_info}, 2452 2453 { 0 } /* table terminator */ 2454 }; 2455 2456 STATIC 2457 _soc_katana2_mmu_sub_block_two_level_t _soc_katana2_mmu_sub_blocks_type_2[] = { 2458 { 0x00000100, 2459 _SOC_KT2_MMU_SUBBLOCK_EMC, 2460 EMC_INTR_DISINTf, 2461 EMC_INTRf, 2462 0, 2463 EMC_ERRORr, 2464 _soc_katana2_mmu_sb_emc_parity_info}, 2465 2466 { 0x00000080, 2467 _SOC_KT2_MMU_SUBBLOCK_DEQ, 2468 DEQ_INTR_DISINTf, 2469 DEQ_INTRf, 2470 0, 2471 DEQ_ERRORr, 2472 _soc_katana2_mmu_sb_deq_parity_info}, 2473 2474 { 0x00000002, 2475 _SOC_KT2_MMU_SUBBLOCK_QSTRUCT, 2476 QSTRUCT_INTR_DISINTf, 2477 QSTRUCT_INTRf, 2478 QSTRUCT_INTERRUPT_MASKr, 2479 QSTRUCT_INTERRUPTr, 2480 _soc_katana2_mmu_sb_qstruct_parity_info}, 2481 2482 { 0x00000001, 2483 _SOC_KT2_MMU_SUBBLOCK_TOQ, 2484 TOQ_INTR_DISINTf, 2485 TOQ_INTRf, 2486 TOQ_INTERRUPT_MASKr, 2487 TOQ_INTERRUPTr, 2488 _soc_katana2_mmu_sb_toq_parity_info}, 2489 { 0 } /* table terminator */ 2490 }; 2491 2492 STATIC _soc_katana2_parity_info_t _soc_katana2_ep0_parity_info[] = { 2493 2494 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2495 EGR_NHOP_PAR_ERRf, 2496 EGR_NHOP_PAR_ERRf, 2497 EGR_L3_NEXT_HOPm, NULL, 2498 INVALIDr, 2499 EGR_EL3_ECC_PARITY_CONTROLr, EGR_L3_NEXT_HOP_PARITY_ENf, 2500 EGR_L3_NEXT_HOP_PARITY_STATUS_INTRr, NULL, 2501 EGR_L3_NEXT_HOP_PARITY_STATUS_NACKr, NULL }, 2502 2503 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2504 EGR_L3_INTF_PAR_ERRf, 2505 EGR_L3_INTF_PAR_ERRf, 2506 EGR_L3_INTFm, NULL, 2507 INVALIDr, 2508 EGR_EL3_ECC_PARITY_CONTROLr, EGR_L3_INTF_PARITY_ENf, 2509 EGR_L3_INTF_PARITY_STATUS_INTRr, NULL, 2510 EGR_L3_INTF_PARITY_STATUS_NACKr, NULL }, 2511 2512 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2513 EGR_MPLS_VC_AND_SWAP_LABEL_TABLE_PAR_ERRf, 2514 EGR_MPLS_VC_AND_SWAP_LABEL_TABLE_PAR_ERRf, 2515 EGR_MPLS_VC_AND_SWAP_LABEL_TABLEm, NULL, 2516 INVALIDr, 2517 EGR_EL3_ECC_PARITY_CONTROLr, EGR_MPLS_VC_AND_SWAP_LABEL_TABLE_PARITY_ENf, 2518 EGR_MPLS_VC_AND_SWAP_LABEL_TABLE_PARITY_STATUS_INTRr, NULL, 2519 EGR_MPLS_VC_AND_SWAP_LABEL_TABLE_PARITY_STATUS_NACKr, NULL }, 2520 2521 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2522 EGR_VLAN_PAR_ERRf, 2523 EGR_VLAN_PAR_ERRf, 2524 EGR_VLANm, NULL, 2525 INVALIDr, 2526 EGR_VLAN_PARITY_CONTROLr, EGR_VLAN_PARITY_ENf, 2527 EGR_VLAN_PARITY_STATUS_INTRr, NULL, 2528 EGR_VLAN_PARITY_STATUS_NACKr, NULL }, 2529 2530 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2531 EGR_VLAN_STG_PAR_ERRf, 2532 EGR_VLAN_STG_PAR_ERRf, 2533 EGR_VLAN_STGm, NULL, 2534 INVALIDr, 2535 EGR_VLAN_PARITY_CONTROLr, EGR_VLAN_STG_PARITY_ENf, 2536 EGR_VLAN_STG_PARITY_STATUS_INTRr, NULL, 2537 EGR_VLAN_STG_PARITY_STATUS_NACKr, NULL }, 2538 2539 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2540 EGR_IP_TUNNEL_PAR_ERRf, 2541 EGR_IP_TUNNEL_PAR_ERRf, 2542 EGR_IP_TUNNELm, NULL, 2543 INVALIDr, 2544 EGR_VLAN_PARITY_CONTROLr, EGR_IP_TUNNEL_PARITY_ENf, 2545 EGR_IP_TUNNEL_PARITY_STATUS_INTRr, NULL, 2546 EGR_IP_TUNNEL_PARITY_STATUS_NACKr, NULL }, 2547 2548 { _SOC_PARITY_TYPE_HASH, NULL, 0, 2549 EGR_VLAN_XLATE_PAR_ERRf, 2550 EGR_VLAN_XLATE_PAR_ERRf, 2551 EGR_VLAN_XLATEm, NULL, 2552 INVALIDr, 2553 EGR_VLAN_PARITY_CONTROLr, EGR_VLAN_XLATE_PARITY_ENf, 2554 INVALIDr, _soc_katana2_egr_vlan_xlate_intr_reg, 2555 INVALIDr, _soc_katana2_egr_vlan_xlate_nack_reg }, 2556 2557 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2558 EGR_FRAGMENT_ID_TABLE_PAR_ERRf, 2559 EGR_FRAGMENT_ID_TABLE_PAR_ERRf, 2560 EGR_FRAGMENT_ID_TABLEm, NULL, 2561 INVALIDr, 2562 EGR_VLAN_PARITY_CONTROLr, EGR_FRAGMENT_ID_TABLE_PARITY_ENf, 2563 EGR_FRAGMENT_ID_TABLE_PARITY_STATUS_INTRr, NULL, 2564 EGR_FRAGMENT_ID_TABLE_PARITY_STATUS_NACKr, NULL }, 2565 2566 { _SOC_PARITY_TYPE_ECC, NULL, 0, 2567 EGR_INITBUF_ECC_ERRf, 2568 EGR_INITBUF_ECC_ERRf, 2569 INVALIDm, "EGR_INITBUF", 2570 INVALIDr, 2571 EGR_EHCPM_ECC_PARITY_CONTROLr, INITBUF_ECC_ENf, 2572 EGR_INITBUF_ECC_STATUS_INTRr, NULL, 2573 INVALIDr, NULL }, 2574 2575 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2576 EGR_PORT_PAR_ERRf, 2577 EGR_PORT_PAR_ERRf, 2578 EGR_PORTm, NULL, 2579 INVALIDr, 2580 EGR_EL3_ECC_PARITY_CONTROLr, EGR_PORT_PARITY_ENf, 2581 EGR_PORT_PARITY_STATUS_INTRr, NULL, 2582 EGR_PORT_PARITY_STATUS_NACKr, NULL }, 2583 2584 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2585 EGR_MOD_MAP_TABLE_PAR_ERRf, 2586 EGR_MOD_MAP_TABLE_PAR_ERRf, 2587 EGR_MOD_MAP_TABLEm, NULL, 2588 INVALIDr, 2589 EGR_EHCPM_ECC_PARITY_CONTROLr, MOD_MAP_PARITY_ENf, 2590 EGR_MOD_MAP_PARITY_STATUS_INTRr, NULL, 2591 EGR_MOD_MAP_PARITY_STATUS_NACKr, NULL }, 2592 2593 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2594 EGR_MAC_DA_PROFILE_PAR_ERRf, 2595 EGR_MAC_DA_PROFILE_PAR_ERRf, 2596 EGR_MAC_DA_PROFILEm, NULL, 2597 INVALIDr, 2598 EGR_EL3_ECC_PARITY_CONTROLr, EGR_MAC_DA_PROFILE_PARITY_ENf, 2599 EGR_MAC_DA_PROFILE_PARITY_STATUS_INTRr, NULL, 2600 EGR_MAC_DA_PROFILE_PARITY_STATUS_NACKr, NULL }, 2601 2602 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2603 EGR_DVP_ATTRIBUTE_PAR_ERRf, 2604 EGR_DVP_ATTRIBUTE_PAR_ERRf, 2605 EGR_DVP_ATTRIBUTEm, NULL, 2606 INVALIDr, 2607 EGR_EL3_ECC_PARITY_CONTROLr, EGR_DVP_ATTRIBUTE_PARITY_ENf, 2608 EGR_DVP_ATTRIBUTE_PARITY_STATUS_INTRr, NULL, 2609 EGR_DVP_ATTRIBUTE_PARITY_STATUS_NACKr, NULL }, 2610 2611 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2612 EGR_VFI_PAR_ERRf, 2613 EGR_VFI_PAR_ERRf, 2614 EGR_VFIm, NULL, 2615 INVALIDr, 2616 EGR_EL3_ECC_PARITY_CONTROLr, EGR_VFI_PARITY_ENf, 2617 EGR_VFI_PARITY_STATUS_INTRr, NULL, 2618 EGR_VFI_PARITY_STATUS_NACKr, NULL }, 2619 2620 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2621 EGR_IPMC_PAR_ERRf, 2622 EGR_IPMC_PAR_ERRf, 2623 EGR_IPMCm, NULL, 2624 INVALIDr, 2625 EGR_EL3_ECC_PARITY_CONTROLr, EGR_IPMC_PARITY_ENf, 2626 EGR_IPMC_PARITY_STATUS_INTRr, NULL, 2627 EGR_IPMC_PARITY_STATUS_NACKr, NULL }, 2628 2629 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2630 EGR_MPLS_EXP_MAPPING_2_PAR_ERRf, 2631 EGR_MPLS_EXP_MAPPING_2_PAR_ERRf, 2632 EGR_MPLS_EXP_MAPPING_2m, NULL, 2633 INVALIDr, 2634 EGR_VLAN_PARITY_CONTROLr, EGR_MPLS_EXP_MAPPING_2_PARITY_ENf, 2635 EGR_MPLS_EXP_MAPPING_2_PARITY_STATUS_INTRr, NULL, 2636 EGR_MPLS_EXP_MAPPING_2_PARITY_STATUS_NACKr, NULL }, 2637 2638 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2639 EGR_MPLS_PRI_MAPPING_PAR_ERRf, 2640 EGR_MPLS_PRI_MAPPING_PAR_ERRf, 2641 EGR_MPLS_PRI_MAPPINGm, NULL, 2642 INVALIDr, 2643 EGR_VLAN_PARITY_CONTROLr, EGR_MPLS_PRI_MAPPING_PARITY_ENf, 2644 EGR_MPLS_PRI_MAPPING_PARITY_STATUS_INTRr, NULL, 2645 EGR_MPLS_PRI_MAPPING_PARITY_STATUS_NACKr, NULL }, 2646 2647 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2648 EGR_PRI_CNG_MAP_PAR_ERRf, 2649 EGR_PRI_CNG_MAP_PAR_ERRf, 2650 EGR_PRI_CNG_MAPm, NULL, 2651 INVALIDr, 2652 EGR_VLAN_PARITY_CONTROLr, EGR_PRI_CNG_MAP_PARITY_ENf, 2653 EGR_PRI_CNG_MAP_PARITY_STATUS_INTRr, NULL, 2654 EGR_PRI_CNG_MAP_PARITY_STATUS_NACKr, NULL }, 2655 2656 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2657 EGR_DSCP_TABLE_PAR_ERRf, 2658 EGR_DSCP_TABLE_PAR_ERRf, 2659 EGR_DSCP_TABLEm, NULL, 2660 INVALIDr, 2661 EGR_VLAN_PARITY_CONTROLr, EGR_DSCP_TABLE_PARITY_ENf, 2662 EGR_DSCP_TABLE_PARITY_STATUS_INTRr, NULL, 2663 EGR_DSCP_TABLE_PARITY_STATUS_NACKr, NULL }, 2664 2665 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2666 EGR_MPLS_EXP_MAPPING_1_PAR_ERRf, 2667 EGR_MPLS_EXP_MAPPING_1_PAR_ERRf, 2668 EGR_MPLS_EXP_MAPPING_1m, NULL, 2669 INVALIDr, 2670 EGR_VLAN_PARITY_CONTROLr, EGR_MPLS_EXP_MAPPING_1_PARITY_ENf, 2671 EGR_MPLS_EXP_MAPPING_1_PARITY_STATUS_INTRr, NULL, 2672 EGR_MPLS_EXP_MAPPING_1_PARITY_STATUS_NACKr, NULL }, 2673 2674 { _SOC_PARITY_TYPE_ECC, NULL, 0, 2675 EGR_MPB_ECC_ERRf, 2676 EGR_MPB_ECC_ERRf, 2677 INVALIDm, "EGR_MPB", 2678 INVALIDr, 2679 EGR_EL3_ECC_PARITY_CONTROLr, EGR_MPB_ECC_ENf, 2680 EGR_MPB_ECC_STATUS_INTRr, NULL, 2681 INVALIDr, NULL }, 2682 2683 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2684 EGR_GPP_ATTRIBUTES_MODBASE_PAR_ERRf, 2685 EGR_GPP_ATTRIBUTES_MODBASE_PAR_ERRf, 2686 EGR_GPP_ATTRIBUTES_MODBASEm, NULL, 2687 INVALIDr, 2688 EGR_VLAN_PARITY_CONTROLr, EGR_GPP_ATTRIBUTES_MODBASE_PARITY_ENf, 2689 EGR_GPP_ATTRIBUTES_MODBASE_PARITY_STATUS_INTRr, NULL, 2690 EGR_GPP_ATTRIBUTES_MODBASE_PARITY_STATUS_NACKr, NULL }, 2691 2692 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2693 EGR_GPP_ATTRIBUTES_PAR_ERRf, 2694 EGR_GPP_ATTRIBUTES_PAR_ERRf, 2695 EGR_GPP_ATTRIBUTESm, NULL, 2696 INVALIDr, 2697 EGR_VLAN_PARITY_CONTROLr, EGR_GPP_ATTRIBUTES_PARITY_ENf, 2698 EGR_GPP_ATTRIBUTES_PARITY_STATUS_INTRr, NULL, 2699 EGR_GPP_ATTRIBUTES_PARITY_STATUS_NACKr, NULL }, 2700 2701 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2702 EGR_QUEUE_TO_PP_PORT_MAP_PAR_ERRf, 2703 EGR_QUEUE_TO_PP_PORT_MAP_PAR_ERRf, 2704 EGR_QUEUE_TO_PP_PORT_MAPm, NULL, 2705 INVALIDr, 2706 EGR_EL3_ECC_PARITY_CONTROLr, EGR_QUEUE_TO_PP_PORT_MAP_PARITY_ENf, 2707 EGR_QUEUE_TO_PP_PORT_MAP_PARITY_STATUS_INTRr, NULL, 2708 EGR_QUEUE_TO_PP_PORT_MAP_PARITY_STATUS_NACKr, NULL }, 2709 2710 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2711 EGR_PCP_DE_MAPPING_PAR_ERRf, 2712 EGR_PCP_DE_MAPPING_PAR_ERRf, 2713 EGR_PCP_DE_MAPPINGm, NULL, 2714 INVALIDr, 2715 EGR_VLAN_PARITY_CONTROLr, EGR_PCP_DE_MAPPING_PARITY_ENf, 2716 EGR_PCP_DE_MAPPING_PARITY_STATUS_INTRr, NULL, 2717 EGR_PCP_DE_MAPPING_PARITY_STATUS_NACKr, NULL }, 2718 2719 { _SOC_PARITY_TYPE_HASH, NULL, 0, 2720 EGR_MP_GROUP_PAR_ERRf, 2721 EGR_MP_GROUP_PAR_ERRf, 2722 EGR_MP_GROUPm, NULL, 2723 INVALIDr, 2724 EGR_EOAM_ECC_PARITY_CONTROLr, MP_GROUP_PARITY_ENf, 2725 INVALIDr, _soc_katana2_egr_mp_group_intr_reg, 2726 INVALIDr, _soc_katana2_egr_mp_group_nack_reg }, 2727 2728 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2729 EGR_MA_INDEX_PAR_ERRf, 2730 EGR_MA_INDEX_PAR_ERRf, 2731 EGR_MA_INDEXm, NULL, 2732 INVALIDr, 2733 EGR_EOAM_ECC_PARITY_CONTROLr, MA_INDEX_PARITY_ENf, 2734 EGR_MA_INDEX_PARITY_STATUS_INTRr, NULL, 2735 EGR_MA_INDEX_PARITY_STATUS_NACKr, NULL }, 2736 2737 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2738 EGR_MAP_MH_PAR_ERRf, 2739 EGR_MAP_MH_PAR_ERRf, 2740 EGR_MAP_MHm, NULL, 2741 INVALIDr, 2742 EGR_EL3_ECC_PARITY_CONTROLr, EGR_MAP_MH_PARITY_ENf, 2743 EGR_MAP_MH_PARITY_STATUS_INTRr, NULL, 2744 EGR_MAP_MH_PARITY_STATUS_NACKr, NULL }, 2745 2746 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2747 EGR_OAM_LM_COUNTERS_0_PAR_ERRf, 2748 EGR_OAM_LM_COUNTERS_0_PAR_ERRf, 2749 EGR_OAM_LM_COUNTERS_0m, NULL, 2750 INVALIDr, 2751 EGR_EOAM_ECC_PARITY_CONTROLr, OAM_LM_COUNTERS_0_PARITY_ENf, 2752 EGR_OAM_LM_COUNTERS_0_PARITY_STATUS_INTRr, NULL, 2753 EGR_OAM_LM_COUNTERS_0_PARITY_STATUS_NACKr, NULL }, 2754 2755 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2756 EGR_OAM_LM_COUNTERS_1_PAR_ERRf, 2757 EGR_OAM_LM_COUNTERS_1_PAR_ERRf, 2758 EGR_OAM_LM_COUNTERS_1m, NULL, 2759 INVALIDr, 2760 EGR_EOAM_ECC_PARITY_CONTROLr, OAM_LM_COUNTERS_1_PARITY_ENf, 2761 EGR_OAM_LM_COUNTERS_1_PARITY_STATUS_INTRr, NULL, 2762 EGR_OAM_LM_COUNTERS_1_PARITY_STATUS_NACKr, NULL }, 2763 2764 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2765 EGR_SF_SRC_MODID_CHECK_PAR_ERRf, 2766 EGR_SF_SRC_MODID_CHECK_PAR_ERRf, 2767 INVALIDm, NULL, 2768 EGR_SF_SRC_MODID_CHECKr, 2769 EGR_EHCPM_ECC_PARITY_CONTROLr, SF_SRC_MODID_CHECK_PARITY_ENf, 2770 EGR_SF_SRC_MODID_CHECK_PARITY_STATUS_INTRr, NULL, 2771 EGR_SF_SRC_MODID_CHECK_PARITY_STATUS_NACKr, NULL }, 2772 2773 { _SOC_PARITY_TYPE_NONE } /* table terminator */ 2774 }; 2775 2776 STATIC _soc_katana2_parity_info_t _soc_katana2_ep1_parity_info[] = { 2777 2778 { _SOC_PARITY_TYPE_EDATABUF, NULL, 0, 2779 CM_ECC_ERRf, 2780 CM_ECC_ERRf, 2781 INVALIDm, "EP_EDATABUF_CM_MEM", 2782 INVALIDr, 2783 EGR_EDATABUF_PARITY_CONTROLr, CM_ECC_ENf, 2784 EGR_CM_BUFFER_STATUS_INTRr, NULL, 2785 INVALIDr, NULL }, 2786 2787 { _SOC_PARITY_TYPE_EDATABUF, NULL, 0, 2788 LP_ECC_ERRf, 2789 LP_ECC_ERRf, 2790 INVALIDm, "EP_EDATABUF_LP_MEM", 2791 INVALIDr, 2792 EGR_EDATABUF_PARITY_CONTROLr, LP_ECC_ENf, 2793 EGR_LP_BUFFER_STATUS_INTRr, NULL, 2794 INVALIDr, NULL }, 2795 2796 /* Remove this due to HW issue that a false ECC is reported for the EDATABUFF on KT2*/ 2797 /*{ _SOC_PARITY_TYPE_EDATABUF, NULL, 0, 2798 RESI_ECC_ERRf, 2799 RESI_ECC_ERRf, 2800 INVALIDm, "EP_EDATABUF_RESI_MEM", 2801 EGR_EDATABUF_PARITY_CONTROLr, RESI_ECC_ENf, 2802 EGR_RESI_BUFFER_STATUS_INTRr, NULL, 2803 INVALIDr, NULL }, 2804 INVALIDr, NULL },*/ 2805 2806 { _SOC_PARITY_TYPE_COUNTER, NULL, 0, 2807 EGR_STATS_COUNTER_TABLE_PAR_ERRf, 2808 EGR_STATS_COUNTER_TABLE_PAR_ERRf, 2809 INVALIDm, "TX Debug Counter", 2810 INVALIDr, 2811 EGR_EDATABUF_PARITY_CONTROLr, STATS_PAR_ENf, 2812 EGR_STATS_COUNTER_TABLE_PARITY_STATUS_INTRr, NULL, 2813 EGR_STATS_COUNTER_TABLE_PARITY_STATUS_NACKr, NULL }, 2814 2815 2816 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2817 EGR_EFP_COUNTER_TABLE_PAR_ERRf, 2818 EGR_EFP_COUNTER_TABLE_PAR_ERRf, 2819 EFP_COUNTER_TABLEm, NULL, 2820 INVALIDr, 2821 EGR_EDATABUF_PARITY_CONTROLr, EFPCTR_PAR_ENf, 2822 EGR_EFP_COUNTER_TABLE_PARITY_STATUS_INTRr, NULL, 2823 EGR_EFP_COUNTER_TABLE_PARITY_STATUS_NACKr, NULL }, 2824 2825 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2826 EGR_EFP_METER_TABLE_PAR_ERRf, 2827 EGR_EFP_METER_TABLE_PAR_ERRf, 2828 EFP_METER_TABLEm, NULL, 2829 INVALIDr, 2830 EFP_METER_PARITY_CONTROLr, PARITY_ENf, 2831 EFP_METER_PARITY_STATUS_INTRr, NULL, 2832 EFP_METER_PARITY_STATUS_NACKr, NULL }, 2833 2834 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2835 EGR_EFP_POLICY_TABLE_PAR_ERRf, 2836 EGR_EFP_POLICY_TABLE_PAR_ERRf, 2837 EFP_POLICY_TABLEm, NULL, 2838 INVALIDr, 2839 EFP_POLICY_PARITY_CONTROLr, PARITY_ENf, 2840 EFP_POLICY_PARITY_STATUS_INTRr, NULL, 2841 EFP_POLICY_PARITY_STATUS_NACKr, NULL }, 2842 2843 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2844 EGR_EFP_PW_INIT_COUNTERS_PAR_ERRf, 2845 EGR_EFP_PW_INIT_COUNTERS_PAR_ERRf, 2846 EGR_PW_INIT_COUNTERSm, NULL, 2847 INVALIDr, 2848 EGR_PW_INIT_COUNTERS_PARITY_CONTROLr, PARITY_ENf, 2849 EGR_PW_INIT_COUNTERS_PARITY_STATUS_INTRr, NULL, 2850 EGR_PW_INIT_COUNTERS_PARITY_STATUS_NACKr, NULL }, 2851 2852 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2853 EGR_FLEX_CTR_OFFSET_TABLE_0_INTR_STATUSf, 2854 EGR_FLEX_CTR_OFFSET_TABLE_0_INTR_STATUSf, 2855 EGR_FLEX_CTR_OFFSET_TABLE_0m, NULL, 2856 INVALIDr, 2857 EGR_FLEX_CTR_OFFSET_TABLE_CONTROL_0r, PARITY_ENf, 2858 EGR_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_INTR_0r, NULL, 2859 EGR_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_NACK_0r, NULL }, 2860 2861 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2862 EGR_FLEX_CTR_OFFSET_TABLE_1_INTR_STATUSf, 2863 EGR_FLEX_CTR_OFFSET_TABLE_1_INTR_STATUSf, 2864 EGR_FLEX_CTR_OFFSET_TABLE_1m, NULL, 2865 INVALIDr, 2866 EGR_FLEX_CTR_OFFSET_TABLE_CONTROL_1r, PARITY_ENf, 2867 EGR_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_INTR_1r, NULL, 2868 EGR_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_NACK_1r, NULL }, 2869 2870 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2871 EGR_FLEX_CTR_OFFSET_TABLE_2_INTR_STATUSf, 2872 EGR_FLEX_CTR_OFFSET_TABLE_2_INTR_STATUSf, 2873 EGR_FLEX_CTR_OFFSET_TABLE_2m, NULL, 2874 INVALIDr, 2875 EGR_FLEX_CTR_OFFSET_TABLE_CONTROL_2r, PARITY_ENf, 2876 EGR_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_INTR_2r, NULL, 2877 EGR_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_NACK_2r, NULL }, 2878 2879 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2880 EGR_FLEX_CTR_OFFSET_TABLE_3_INTR_STATUSf, 2881 EGR_FLEX_CTR_OFFSET_TABLE_3_INTR_STATUSf, 2882 EGR_FLEX_CTR_OFFSET_TABLE_3m, NULL, 2883 INVALIDr, 2884 EGR_FLEX_CTR_OFFSET_TABLE_CONTROL_3r, PARITY_ENf, 2885 EGR_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_INTR_3r, NULL, 2886 EGR_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_NACK_3r, NULL }, 2887 2888 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2889 EGR_FLEX_CTR_COUNTER_TABLE_0_INTR_STATUSf, 2890 EGR_FLEX_CTR_COUNTER_TABLE_0_INTR_STATUSf, 2891 EGR_FLEX_CTR_COUNTER_TABLE_0m, NULL, 2892 INVALIDr, 2893 EGR_FLEX_CTR_COUNTER_TABLE_CONTROL_0r, PARITY_ENf, 2894 EGR_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_INTR_0r, NULL, 2895 EGR_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_NACK_0r, NULL }, 2896 2897 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2898 EGR_FLEX_CTR_COUNTER_TABLE_1_INTR_STATUSf, 2899 EGR_FLEX_CTR_COUNTER_TABLE_1_INTR_STATUSf, 2900 EGR_FLEX_CTR_COUNTER_TABLE_1m, NULL, 2901 INVALIDr, 2902 EGR_FLEX_CTR_COUNTER_TABLE_CONTROL_1r, PARITY_ENf, 2903 EGR_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_INTR_1r, NULL, 2904 EGR_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_NACK_1r, NULL }, 2905 2906 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2907 EGR_FLEX_CTR_COUNTER_TABLE_2_INTR_STATUSf, 2908 EGR_FLEX_CTR_COUNTER_TABLE_2_INTR_STATUSf, 2909 EGR_FLEX_CTR_COUNTER_TABLE_2m, NULL, 2910 INVALIDr, 2911 EGR_FLEX_CTR_COUNTER_TABLE_CONTROL_2r, PARITY_ENf, 2912 EGR_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_INTR_2r, NULL, 2913 EGR_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_NACK_2r, NULL }, 2914 2915 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2916 EGR_FLEX_CTR_COUNTER_TABLE_3_INTR_STATUSf, 2917 EGR_FLEX_CTR_COUNTER_TABLE_3_INTR_STATUSf, 2918 EGR_FLEX_CTR_COUNTER_TABLE_3m, NULL, 2919 INVALIDr, 2920 EGR_FLEX_CTR_COUNTER_TABLE_CONTROL_3r, PARITY_ENf, 2921 EGR_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_INTR_3r, NULL, 2922 EGR_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_NACK_3r, NULL }, 2923 2924 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2925 EGR_FLEX_CTR_OFFSET_TABLE_4_INTR_STATUSf, 2926 EGR_FLEX_CTR_OFFSET_TABLE_4_INTR_STATUSf, 2927 EGR_FLEX_CTR_OFFSET_TABLE_4m, NULL, 2928 INVALIDr, 2929 EGR_FLEX_CTR_OFFSET_TABLE_CONTROL_4r, PARITY_ENf, 2930 EGR_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_INTR_4r, NULL, 2931 EGR_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_NACK_4r, NULL }, 2932 2933 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2934 EGR_FLEX_CTR_OFFSET_TABLE_5_INTR_STATUSf, 2935 EGR_FLEX_CTR_OFFSET_TABLE_5_INTR_STATUSf, 2936 EGR_FLEX_CTR_OFFSET_TABLE_5m, NULL, 2937 INVALIDr, 2938 EGR_FLEX_CTR_OFFSET_TABLE_CONTROL_5r, PARITY_ENf, 2939 EGR_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_INTR_5r, NULL, 2940 EGR_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_NACK_5r, NULL }, 2941 2942 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2943 EGR_FLEX_CTR_OFFSET_TABLE_6_INTR_STATUSf, 2944 EGR_FLEX_CTR_OFFSET_TABLE_6_INTR_STATUSf, 2945 EGR_FLEX_CTR_OFFSET_TABLE_6m, NULL, 2946 INVALIDr, 2947 EGR_FLEX_CTR_OFFSET_TABLE_CONTROL_6r, PARITY_ENf, 2948 EGR_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_INTR_6r, NULL, 2949 EGR_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_NACK_6r, NULL }, 2950 2951 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2952 EGR_FLEX_CTR_OFFSET_TABLE_7_INTR_STATUSf, 2953 EGR_FLEX_CTR_OFFSET_TABLE_7_INTR_STATUSf, 2954 EGR_FLEX_CTR_OFFSET_TABLE_7m, NULL, 2955 INVALIDr, 2956 EGR_FLEX_CTR_OFFSET_TABLE_CONTROL_7r, PARITY_ENf, 2957 EGR_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_INTR_7r, NULL, 2958 EGR_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_NACK_7r, NULL }, 2959 2960 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2961 EGR_FLEX_CTR_COUNTER_TABLE_4_INTR_STATUSf, 2962 EGR_FLEX_CTR_COUNTER_TABLE_4_INTR_STATUSf, 2963 EGR_FLEX_CTR_COUNTER_TABLE_4m, NULL, 2964 INVALIDr, 2965 EGR_FLEX_CTR_COUNTER_TABLE_CONTROL_4r, PARITY_ENf, 2966 EGR_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_INTR_4r, NULL, 2967 EGR_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_NACK_4r, NULL }, 2968 2969 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2970 EGR_FLEX_CTR_COUNTER_TABLE_5_INTR_STATUSf, 2971 EGR_FLEX_CTR_COUNTER_TABLE_5_INTR_STATUSf, 2972 EGR_FLEX_CTR_COUNTER_TABLE_5m, NULL, 2973 INVALIDr, 2974 EGR_FLEX_CTR_COUNTER_TABLE_CONTROL_5r, PARITY_ENf, 2975 EGR_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_INTR_5r, NULL, 2976 EGR_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_NACK_5r, NULL }, 2977 2978 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2979 EGR_FLEX_CTR_COUNTER_TABLE_6_INTR_STATUSf, 2980 EGR_FLEX_CTR_COUNTER_TABLE_6_INTR_STATUSf, 2981 EGR_FLEX_CTR_COUNTER_TABLE_6m, NULL, 2982 INVALIDr, 2983 EGR_FLEX_CTR_COUNTER_TABLE_CONTROL_6r, PARITY_ENf, 2984 EGR_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_INTR_6r, NULL, 2985 EGR_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_NACK_6r, NULL }, 2986 2987 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2988 EGR_FLEX_CTR_COUNTER_TABLE_7_INTR_STATUSf, 2989 EGR_FLEX_CTR_COUNTER_TABLE_7_INTR_STATUSf, 2990 EGR_FLEX_CTR_COUNTER_TABLE_7m, NULL, 2991 INVALIDr, 2992 EGR_FLEX_CTR_COUNTER_TABLE_CONTROL_7r, PARITY_ENf, 2993 EGR_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_INTR_7r, NULL, 2994 EGR_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_NACK_7r, NULL }, 2995 2996 { _SOC_PARITY_TYPE_NONE } /* table terminator */ 2997 }; 2998 2999 STATIC _soc_katana2_parity_info_t _soc_katana2_ep2_parity_info[] = { 3000 3001 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3002 EGR_1588_LNK_DELAY_PAR_ERRf, 3003 EGR_1588_LNK_DELAY_PAR_ERRf, 3004 INVALIDm, NULL, 3005 EGR_1588_LINK_DELAY_64r, 3006 EGR_1588_LINK_DELAY_64_PARITY_CONTROLr, PARITY_ENf, 3007 EGR_1588_LINK_DELAY_64_PARITY_STATUS_INTRr, NULL, 3008 EGR_1588_LINK_DELAY_64_PARITY_STATUS_NACKr, NULL }, 3009 3010 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3011 EGR_1588_SA_PAR_ERRf, 3012 EGR_1588_SA_PAR_ERRf, 3013 EGR_1588_SAm, NULL, 3014 INVALIDr, 3015 EGR_1588_SA_PARITY_CONTROLr, PARITY_ENf, 3016 EGR_1588_SA_PARITY_STATUS_INTRr, NULL, 3017 EGR_1588_SA_PARITY_STATUS_NACKr, NULL }, 3018 3019 { _SOC_PARITY_TYPE_EDATABUF, NULL, 0, 3020 XQ0_ECC_ERRf, 3021 XQ0_ECC_ERRf, 3022 INVALIDm, "EP_EDATABUF_XQ0_MEM", 3023 INVALIDr, 3024 EGR_EDATABUF_PARITY_CONTROLr, XQ0_ECC_ENf, 3025 EGR_XQ0_BUFFER_STATUS_INTRr, NULL, 3026 INVALIDr, NULL }, 3027 3028 { _SOC_PARITY_TYPE_EDATABUF, NULL, 0, 3029 XQ1_ECC_ERRf, 3030 XQ1_ECC_ERRf, 3031 INVALIDm, "EP_EDATABUF_XQ1_MEM", 3032 INVALIDr, 3033 EGR_EDATABUF_PARITY_CONTROLr, XQ1_ECC_ENf, 3034 EGR_XQ1_BUFFER_STATUS_INTRr, NULL, 3035 INVALIDr, NULL }, 3036 3037 { _SOC_PARITY_TYPE_EDATABUF, NULL, 0, 3038 XQ2_ECC_ERRf, 3039 XQ2_ECC_ERRf, 3040 INVALIDm, "EP_EDATABUF_XQ2_MEM", 3041 INVALIDr, 3042 EGR_EDATABUF_PARITY_CONTROLr, XQ2_ECC_ENf, 3043 EGR_XQ2_BUFFER_STATUS_INTRr, NULL, 3044 INVALIDr, NULL }, 3045 3046 { _SOC_PARITY_TYPE_EDATABUF, NULL, 0, 3047 XQ3_ECC_ERRf, 3048 XQ3_ECC_ERRf, 3049 INVALIDm, "EP_EDATABUF_XQ3_MEM", 3050 INVALIDr, 3051 EGR_EDATABUF_PARITY_CONTROLr, XQ3_ECC_ENf, 3052 EGR_XQ3_BUFFER_STATUS_INTRr, NULL, 3053 INVALIDr, NULL }, 3054 3055 { _SOC_PARITY_TYPE_EDATABUF, NULL, 0, 3056 XQ4_ECC_ERRf, 3057 XQ4_ECC_ERRf, 3058 INVALIDm, "EP_EDATABUF_XQ4_MEM", 3059 INVALIDr, 3060 EGR_EDATABUF_PARITY_CONTROLr, XQ4_ECC_ENf, 3061 EGR_XQ4_BUFFER_STATUS_INTRr, NULL, 3062 INVALIDr, NULL }, 3063 3064 { _SOC_PARITY_TYPE_EDATABUF, NULL, 0, 3065 XQ5_ECC_ERRf, 3066 XQ5_ECC_ERRf, 3067 INVALIDm, "EP_EDATABUF_XQ5_MEM", 3068 INVALIDr, 3069 EGR_EDATABUF_PARITY_CONTROLr, XQ5_ECC_ENf, 3070 EGR_XQ5_BUFFER_STATUS_INTRr, NULL, 3071 INVALIDr, NULL }, 3072 3073 { _SOC_PARITY_TYPE_EDATABUF, NULL, 0, 3074 XQ6_ECC_ERRf, 3075 XQ6_ECC_ERRf, 3076 INVALIDm, "EP_EDATABUF_XQ6_MEM", 3077 INVALIDr, 3078 EGR_EDATABUF_PARITY_CONTROLr, XQ6_ECC_ENf, 3079 EGR_XQ6_BUFFER_STATUS_INTRr, NULL, 3080 INVALIDr, NULL }, 3081 3082 { _SOC_PARITY_TYPE_EDATABUF, NULL, 0, 3083 XQ7_ECC_ERRf, 3084 XQ7_ECC_ERRf, 3085 INVALIDm, "EP_EDATABUF_XQ7_MEM", 3086 INVALIDr, 3087 EGR_EDATABUF_PARITY_CONTROLr, XQ7_ECC_ENf, 3088 EGR_XQ7_BUFFER_STATUS_INTRr, NULL, 3089 INVALIDr, NULL }, 3090 3091 { _SOC_PARITY_TYPE_NONE } /* table terminator */ 3092 }; 3093 3094 STATIC _soc_katana2_parity_info_t _soc_katana2_ip0_parity_info[] = { 3095 /* Block-IPIPE, Stage-IARB */ 3096 3097 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3098 IARB_LMEP1_PAR_ERRf, 3099 IARB_LMEP1_PAR_ERRf, 3100 LMEP_1m, NULL, 3101 INVALIDr, 3102 LMEP_1_PARITY_CONTROLr, PARITY_ENf, 3103 LMEP_1_PARITY_STATUS_INTRr, NULL, 3104 LMEP_1_PARITY_STATUS_NACKr, NULL }, 3105 3106 { _SOC_PARITY_TYPE_ECC, NULL, 0, 3107 IARB_PIPE_X_LEARN_FIFO_ECC_ERRf, 3108 IARB_PIPE_X_LEARN_FIFO_ECC_ERRf, 3109 INVALIDm, "IARB_LEARN_FIFO_PIPE_X", 3110 INVALIDr, 3111 IARB_LEARN_FIFO_ECC_CONTROLr, ECC_ENf, 3112 IARB_PIPE_X_LERAN_FIFO_ECC_STATUS_INTRr, NULL, 3113 INVALIDr, NULL }, 3114 3115 { _SOC_PARITY_TYPE_ECC, NULL, 0, 3116 IARB_HDR_ERRf, 3117 IARB_HDR_ERRf, 3118 INVALIDm, "IARB_PKT_HDR", 3119 INVALIDr, 3120 IARB_HDR_ECC_CONTROLr, ECC_ENf, 3121 IARB_HDR_ECC_STATUS_INTRr, NULL, 3122 INVALIDr, NULL }, 3123 3124 { _SOC_PARITY_TYPE_ECC, NULL, 0, 3125 IARB_PKT_ERRf, 3126 IARB_PKT_ERRf, 3127 INVALIDm, "IARB_PKT_BUF", 3128 INVALIDr, 3129 IARB_PKT_ECC_CONTROLr, ECC_ENf, 3130 IARB_PKT_ECC_STATUS_INTRr, NULL, 3131 INVALIDr, NULL }, 3132 3133 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3134 LMEP_PAR_ERRf, 3135 LMEP_PAR_ERRf, 3136 LMEPm, NULL, 3137 INVALIDr, 3138 LMEP_PARITY_CONTROLr, PARITY_ENf, 3139 LMEP_PARITY_STATUS_INTRr, NULL, 3140 LMEP_PARITY_STATUS_NACKr, NULL }, 3141 3142 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3143 SUBPORT_TAG_TO_PP_PORT_MAP_PARITY_ERRf, 3144 SUBPORT_TAG_TO_PP_PORT_MAP_PARITY_ERRf, 3145 SUBPORT_TAG_TO_PP_PORT_MAP_DATA_ONLYm, NULL, 3146 INVALIDr, 3147 SUBPORT_TAG_TO_PP_PORT_MAP_DATA_PARITY_CONTROLr, PARITY_ENf, 3148 SUBPORT_TAG_TO_PP_PORT_MAP_DATA_PARITY_STATUS_INTRr, NULL, 3149 SUBPORT_TAG_TO_PP_PORT_MAP_DATA_PARITY_STATUS_NACKr, NULL }, 3150 3151 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3152 ING_PHYSICAL_PORT_TABLE_PARITY_ERRf, 3153 ING_PHYSICAL_PORT_TABLE_PARITY_ERRf, 3154 ING_PHYSICAL_PORT_TABLEm, NULL, 3155 INVALIDr, 3156 ING_PHYSICAL_PORT_TABLE_PARITY_CONTROLr, PARITY_ENf, 3157 ING_PHYSICAL_PORT_TABLE_PARITY_STATUS_INTRr, NULL, 3158 ING_PHYSICAL_PORT_TABLE_PARITY_STATUS_NACKr, NULL }, 3159 3160 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3161 DEVICE_STREAM_ID_TO_PP_PORT_MAP_PARITY_ERRf, 3162 DEVICE_STREAM_ID_TO_PP_PORT_MAP_PARITY_ERRf, 3163 DEVICE_STREAM_ID_TO_PP_PORT_MAPm, NULL, 3164 INVALIDr, 3165 DEVICE_STREAM_ID_TO_PP_PORT_MAP_PARITY_CONTROLr, PARITY_ENf, 3166 DEVICE_STREAM_ID_TO_PP_PORT_MAP_PARITY_STATUS_INTRr, NULL, 3167 DEVICE_STREAM_ID_TO_PP_PORT_MAP_PARITY_STATUS_NACKr, NULL }, 3168 3169 { _SOC_PARITY_TYPE_ECC, NULL, 0, 3170 SOURCE_TRUNK_MAP_PARITY_ERRf, 3171 SOURCE_TRUNK_MAP_PARITY_ERRf, 3172 SOURCE_TRUNK_MAP_TABLEm, NULL, 3173 INVALIDr, 3174 SRC_TRUNK_ECC_CONTROLr, ECC_ENf, 3175 SRC_TRUNK_ECC_STATUS_INTRr, NULL, 3176 SRC_TRUNK_ECC_STATUS_NACKr, NULL }, 3177 3178 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3179 SOURCE_TRUNK_MAP_MODVIEW_PAR_ERRf, 3180 SOURCE_TRUNK_MAP_MODVIEW_PAR_ERRf, 3181 SOURCE_TRUNK_MAP_MODBASEm, NULL, 3182 INVALIDr, 3183 SOURCE_TRUNK_MAP_MODVIEW_PARITY_CONTROLr, PARITY_ENf, 3184 SOURCE_TRUNK_MAP_MODVIEW_PARITY_STATUS_INTRr, NULL, 3185 SOURCE_TRUNK_MAP_MODVIEW_PARITY_STATUS_NACKr, NULL }, 3186 3187 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3188 SYSTEM_CONFIG_MODVIEW_PAR_ERRf, 3189 SYSTEM_CONFIG_MODVIEW_PAR_ERRf, 3190 SYSTEM_CONFIG_TABLE_MODBASEm, NULL, 3191 INVALIDr, 3192 SYSTEM_CONFIG_MODVIEW_PARITY_CONTROLr, PARITY_ENf, 3193 SYSTEM_CONFIG_MODVIEW_PARITY_STATUS_INTRr, NULL, 3194 SYSTEM_CONFIG_MODVIEW_PARITY_STATUS_NACKr, NULL }, 3195 3196 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3197 SYS_CONFIG_PAR_ERRf, 3198 SYS_CONFIG_PAR_ERRf, 3199 SYSTEM_CONFIG_TABLEm, NULL, 3200 INVALIDr, 3201 SYSTEM_CONFIG_PARITY_CONTROLr, PARITY_ENf, 3202 SYSTEM_CONFIG_PARITY_STATUS_INTRr, NULL, 3203 SYSTEM_CONFIG_PARITY_STATUS_NACKr, NULL }, 3204 3205 { _SOC_PARITY_TYPE_ECC, NULL, 0, 3206 PORT_TABLE_PAR_ERRf, 3207 PORT_TABLE_PAR_ERRf, 3208 PORT_TABm, NULL, 3209 INVALIDr, 3210 PORT_TABLE_ECC_CONTROLr, ECC_ENf, 3211 PORT_TABLE_ECC_STATUS_INTRr, NULL, 3212 PORT_TABLE_ECC_STATUS_NACKr, NULL }, 3213 3214 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3215 PTP_LABEL_RANGE_PROFILE_TABLE_PAR_ERRf, 3216 PTP_LABEL_RANGE_PROFILE_TABLE_PAR_ERRf, 3217 PTP_LABEL_RANGE_PROFILE_TABLEm, NULL, 3218 INVALIDr, 3219 PTP_LABEL_RANGE_PROFILE_TABLE_PARITY_CONTROLr, PARITY_ENf, 3220 PTP_LABEL_RANGE_PROFILE_TABLE_PARITY_STATUS_INTRr, NULL, 3221 PTP_LABEL_RANGE_PROFILE_TABLE_PARITY_STATUS_NACKr, NULL }, 3222 3223 { _SOC_PARITY_TYPE_ECC, NULL, 0, 3224 LPORT_PAR_ERRf, 3225 LPORT_PAR_ERRf, 3226 LPORT_TABm, NULL, 3227 INVALIDr, 3228 LPORT_ECC_CONTROLr, ECC_ENf, 3229 LPORT_ECC_STATUS_INTRr, NULL, 3230 LPORT_ECC_STATUS_NACKr, NULL }, 3231 3232 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3233 RX_PROT_GROUP_TABLE_1_DMA_PAR_ERRf, 3234 RX_PROT_GROUP_TABLE_1_DMA_PAR_ERRf, 3235 RX_PROT_GROUP_TABLE_1_DMAm, NULL, 3236 INVALIDr, 3237 RX_PROT_GROUP_TABLE_1_DMA_PARITY_CONTROLr, PARITY_ENf, 3238 RX_PROT_GROUP_TABLE_1_DMA_PARITY_STATUS_INTRr, NULL, 3239 RX_PROT_GROUP_TABLE_1_DMA_PARITY_STATUS_NACKr, NULL }, 3240 3241 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3242 L3_TUNNEL_PAR_ERRf, 3243 L3_TUNNEL_PAR_ERRf, 3244 L3_TUNNEL_DATA_ONLYm, NULL, 3245 INVALIDr, 3246 L3_TUNNEL_PARITY_CONTROLr, PARITY_ENf, 3247 L3_TUNNEL_PARITY_STATUS_INTRr, NULL, 3248 L3_TUNNEL_PARITY_STATUS_NACKr, NULL }, 3249 3250 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3251 FP_UDF_PAR_ERRf, 3252 FP_UDF_PAR_ERRf, 3253 FP_UDF_OFFSETm, NULL, 3254 INVALIDr, 3255 FP_UDF_PARITY_CONTROLr, PARITY_ENf, 3256 FP_UDF_PARITY_STATUS_INTRr, NULL, 3257 FP_UDF_PARITY_STATUS_NACKr, NULL }, 3258 3259 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3260 MOD_MAP_PAR_ERRf, 3261 MOD_MAP_PAR_ERRf, 3262 ING_MOD_MAP_TABLEm, NULL, 3263 INVALIDr, 3264 MOD_MAP_PARITY_CONTROLr, PARITY_ENf, 3265 MOD_MAP_PARITY_STATUS_INTRr, NULL, 3266 MOD_MAP_PARITY_STATUS_NACKr, NULL }, 3267 3268 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3269 VLAN_RANGE_PAR_ERRf, 3270 VLAN_RANGE_PAR_ERRf, 3271 ING_VLAN_RANGEm, NULL, 3272 INVALIDr, 3273 VLAN_RANGE_PARITY_CONTROLr, PARITY_ENf, 3274 VLAN_RANGE_PARITY_STATUS_INTRr, NULL, 3275 VLAN_RANGE_PARITY_STATUS_NACKr, NULL }, 3276 3277 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3278 CPU_TS_POLICY_PAR_ERRf, 3279 CPU_TS_POLICY_PAR_ERRf, 3280 CPU_TS_MAPm, NULL, 3281 INVALIDr, 3282 CPU_TS_PARITY_CONTROLr, PARITY_ENf, 3283 CPU_TS_PARITY_STATUS_INTRr, NULL, 3284 CPU_TS_PARITY_STATUS_NACKr, NULL }, 3285 3286 { _SOC_PARITY_TYPE_NONE } /* table terminator */ 3287 }; 3288 3289 STATIC _soc_katana2_parity_info_t _soc_katana2_ip1_parity_info[] = { 3290 3291 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3292 SOURCE_VP_PAR_ERRf, 3293 SOURCE_VP_PAR_ERRf, 3294 SOURCE_VPm, NULL, 3295 INVALIDr, 3296 SOURCE_VP_PARITY_CONTROLr, PARITY_ENf, 3297 SOURCE_VP_PARITY_STATUS_INTRr, NULL, 3298 SOURCE_VP_PARITY_STATUS_NACKr, NULL }, 3299 3300 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3301 VFI_1_PAR_ERRf, 3302 VFI_1_PAR_ERRf, 3303 VFI_1m, NULL, 3304 INVALIDr, 3305 VFI_1_PARITY_CONTROLr, PARITY_ENf, 3306 VFI_1_PARITY_STATUS_INTRr, NULL, 3307 VFI_1_PARITY_STATUS_NACKr, NULL }, 3308 3309 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3310 L3_IIF_PAR_ERRf, 3311 L3_IIF_PAR_ERRf, 3312 L3_IIFm, NULL, 3313 INVALIDr, 3314 L3_IIF_PARITY_CONTROLr, PARITY_ENf, 3315 L3_IIF_PARITY_STATUS_INTRr, NULL, 3316 L3_IIF_PARITY_STATUS_NACKr, NULL }, 3317 3318 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3319 VFI_PAR_ERRf, 3320 VFI_PAR_ERRf, 3321 VFIm, NULL, 3322 INVALIDr, 3323 VFI_PARITY_CONTROLr, PARITY_ENf, 3324 VFI_PARITY_STATUS_INTRr, NULL, 3325 VFI_PARITY_STATUS_NACKr, NULL }, 3326 3327 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3328 VRF_PAR_ERRf, 3329 VRF_PAR_ERRf, 3330 VRFm, NULL, 3331 INVALIDr, 3332 VRF_PARITY_CONTROLr, PARITY_ENf, 3333 VRF_PARITY_STATUS_INTRr, NULL, 3334 VRF_PARITY_STATUS_NACKr, NULL }, 3335 3336 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3337 VLAN_MPLS_PAR_ERRf, 3338 VLAN_MPLS_PAR_ERRf, 3339 VLAN_MPLSm, NULL, 3340 INVALIDr, 3341 VLAN_MPLS_PARITY_CONTROLr, PARITY_ENf, 3342 VLAN_MPLS_PARITY_STATUS_INTRr, NULL, 3343 VLAN_MPLS_PARITY_STATUS_NACKr, NULL }, 3344 3345 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3346 VLAN_PAR_ERRf, 3347 VLAN_PAR_ERRf, 3348 VLAN_TABm, NULL, 3349 INVALIDr, 3350 VLAN_PARITY_CONTROLr, PARITY_ENf, 3351 VLAN_PARITY_STATUS_INTRr, NULL, 3352 VLAN_PARITY_STATUS_NACKr, NULL }, 3353 3354 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3355 VLAN_STG_PAR_ERRf, 3356 VLAN_STG_PAR_ERRf, 3357 STG_TABm, NULL, 3358 INVALIDr, 3359 VLAN_STG_PARITY_CONTROLr, PARITY_ENf, 3360 VLAN_STG_PARITY_STATUS_INTRr, NULL, 3361 VLAN_STG_PARITY_STATUS_NACKr, NULL }, 3362 3363 { _SOC_PARITY_TYPE_HASH, NULL, 0, 3364 L3_ENTRY_PAR_ERRf, 3365 L3_ENTRY_PAR_ERRf, 3366 L3_ENTRY_ONLYm, NULL, 3367 INVALIDr, 3368 L3_ENTRY_PARITY_CONTROLr, PARITY_ENf, 3369 INVALIDr, _soc_katana2_l3_entry_only_intr_reg, 3370 INVALIDr, _soc_katana2_l3_entry_only_nack_reg }, 3371 3372 { _SOC_PARITY_TYPE_HASH, NULL, 0, 3373 L3_ENTRY_PAR_ERRf, 3374 L3_ENTRY_PAR_ERRf, 3375 L3_ENTRY_IPV4_UNICASTm, NULL, 3376 INVALIDr, 3377 L3_ENTRY_PARITY_CONTROLr, PARITY_ENf, 3378 INVALIDr, _soc_katana2_l3_entry_only_intr_reg, 3379 INVALIDr, _soc_katana2_l3_entry_only_nack_reg }, 3380 3381 { _SOC_PARITY_TYPE_HASH, NULL, 0, 3382 L3_ENTRY_PAR_ERRf, 3383 L3_ENTRY_PAR_ERRf, 3384 L3_ENTRY_IPV6_UNICASTm, NULL, 3385 INVALIDr, 3386 L3_ENTRY_PARITY_CONTROLr, PARITY_ENf, 3387 INVALIDr, _soc_katana2_l3_entry_only_intr_reg, 3388 INVALIDr, _soc_katana2_l3_entry_only_nack_reg }, 3389 3390 { _SOC_PARITY_TYPE_HASH, NULL, 0, 3391 L3_ENTRY_PAR_ERRf, 3392 L3_ENTRY_PAR_ERRf, 3393 L3_ENTRY_IPV4_MULTICASTm, NULL, 3394 INVALIDr, 3395 L3_ENTRY_PARITY_CONTROLr, PARITY_ENf, 3396 INVALIDr, _soc_katana2_l3_entry_only_intr_reg, 3397 INVALIDr, _soc_katana2_l3_entry_only_nack_reg }, 3398 3399 { _SOC_PARITY_TYPE_HASH, NULL, 0, 3400 L3_ENTRY_PAR_ERRf, 3401 L3_ENTRY_PAR_ERRf, 3402 L3_ENTRY_IPV6_MULTICASTm, NULL, 3403 INVALIDr, 3404 L3_ENTRY_PARITY_CONTROLr, PARITY_ENf, 3405 INVALIDr, _soc_katana2_l3_entry_only_intr_reg, 3406 INVALIDr, _soc_katana2_l3_entry_only_nack_reg }, 3407 3408 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3409 L3_DEFIP_PAR_ERRf, 3410 L3_DEFIP_PAR_ERRf, 3411 L3_DEFIP_DATA_ONLYm, NULL, 3412 INVALIDr, 3413 L3_DEFIP_DATA_PARITY_CONTROLr, PARITY_ENf, 3414 L3_DEFIP_DATA_PARITY_STATUS_INTRr, NULL, 3415 L3_DEFIP_DATA_PARITY_STATUS_NACKr, NULL }, 3416 3417 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3418 RTAG7_FLOW_BASED_HASH_PAR_ERRf, 3419 RTAG7_FLOW_BASED_HASH_PAR_ERRf, 3420 RTAG7_FLOW_BASED_HASHm, NULL, 3421 INVALIDr, 3422 RTAG7_FLOW_BASED_HASH_PARITY_CONTROLr, PARITY_ENf, 3423 RTAG7_FLOW_BASED_HASH_PARITY_STATUS_INTRr, NULL, 3424 RTAG7_FLOW_BASED_HASH_PARITY_STATUS_NACKr, NULL }, 3425 3426 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3427 FP_FIELD_SEL_PAR_ERRf, 3428 FP_FIELD_SEL_PAR_ERRf, 3429 FP_PORT_FIELD_SELm, NULL, 3430 INVALIDr, 3431 FP_FIELD_SEL_PARITY_CONTROLr, PARITY_ENf, 3432 FP_FIELD_SEL_PARITY_STATUS_INTRr, NULL, 3433 FP_FIELD_SEL_PARITY_STATUS_NACKr, NULL }, 3434 3435 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3436 TTL_FN_PAR_ERRf, 3437 TTL_FN_PAR_ERRf, 3438 TTL_FNm, NULL, 3439 INVALIDr, 3440 TTL_FN_PARITY_CONTROLr, PARITY_ENf, 3441 TTL_FN_PARITY_STATUS_INTRr, NULL, 3442 TTL_FN_PARITY_STATUS_NACKr, NULL }, 3443 3444 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3445 TOS_FN_PAR_ERRf, 3446 TOS_FN_PAR_ERRf, 3447 TOS_FNm, NULL, 3448 INVALIDr, 3449 TOS_FN_PARITY_CONTROLr, PARITY_ENf, 3450 TOS_FN_PARITY_STATUS_INTRr, NULL, 3451 TOS_FN_PARITY_STATUS_NACKr, NULL }, 3452 3453 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3454 ING_PRI_CNG_MAP_PAR_ERRf, 3455 ING_PRI_CNG_MAP_PAR_ERRf, 3456 ING_PRI_CNG_MAPm, NULL, 3457 INVALIDr, 3458 ING_PRI_CNG_MAP_PARITY_CONTROLr, PARITY_ENf, 3459 ING_PRI_CNG_MAP_PARITY_STATUS_INTRr, NULL, 3460 ING_PRI_CNG_MAP_PARITY_STATUS_NACKr, NULL }, 3461 3462 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3463 ING_UNTAGGED_PHB_PAR_ERRf, 3464 ING_UNTAGGED_PHB_PAR_ERRf, 3465 ING_UNTAGGED_PHBm, NULL, 3466 INVALIDr, 3467 ING_UNTAGGED_PHB_PARITY_CONTROLr, PARITY_ENf, 3468 ING_UNTAGGED_PHB_PARITY_STATUS_INTRr, NULL, 3469 ING_UNTAGGED_PHB_PARITY_STATUS_NACKr, NULL }, 3470 3471 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3472 DSCP_TABLE_PAR_ERRf, 3473 DSCP_TABLE_PAR_ERRf, 3474 DSCP_TABLEm, NULL, 3475 INVALIDr, 3476 DSCP_TABLE_PARITY_CONTROLr, PARITY_ENf, 3477 DSCP_TABLE_PARITY_STATUS_INTRr, NULL, 3478 DSCP_TABLE_PARITY_STATUS_NACKr, NULL }, 3479 3480 { _SOC_PARITY_TYPE_HASH, NULL, 0, 3481 L2_ENTRY_PAR_ERRf, 3482 L2_ENTRY_PAR_ERRf, 3483 L2_ENTRY_ONLYm, NULL, 3484 INVALIDr, 3485 L2_ENTRY_PARITY_CONTROLr, PARITY_ENf, 3486 INVALIDr, _soc_katana2_l2_entry_only_intr_reg, 3487 INVALIDr, _soc_katana2_l2_entry_only_nack_reg }, 3488 3489 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3490 NHOP_PAR_ERRf, 3491 NHOP_PAR_ERRf, 3492 INITIAL_ING_L3_NEXT_HOPm, NULL, 3493 INVALIDr, 3494 INITIAL_ING_L3_NEXT_HOP_PARITY_CONTROLr, PARITY_ENf, 3495 INITIAL_ING_L3_NEXT_HOP_PARITY_STATUS_INTRr, NULL, 3496 INITIAL_ING_L3_NEXT_HOP_PARITY_STATUS_NACKr, NULL }, 3497 3498 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3499 ECMP_GRP_PAR_ERRf, 3500 ECMP_GRP_PAR_ERRf, 3501 INITIAL_L3_ECMP_GROUPm, NULL, 3502 INVALIDr, 3503 INITIAL_L3_ECMP_GROUP_PARITY_CONTROLr, PARITY_ENf, 3504 INITIAL_L3_ECMP_GROUP_PARITY_STATUS_INTRr, NULL, 3505 INITIAL_L3_ECMP_GROUP_PARITY_STATUS_NACKr, NULL }, 3506 3507 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3508 L3_ECMP_PAR_ERRf, 3509 L3_ECMP_PAR_ERRf, 3510 INITIAL_L3_ECMPm, NULL, 3511 INVALIDr, 3512 INITIAL_L3_ECMP_PARITY_CONTROLr, PARITY_ENf, 3513 INITIAL_L3_ECMP_PARITY_STATUS_INTRr, NULL, 3514 INITIAL_L3_ECMP_PARITY_STATUS_NACKr, NULL }, 3515 3516 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3517 ING_DVP_PAR_ERRf, 3518 ING_DVP_PAR_ERRf, 3519 ING_DVP_TABLEm, NULL, 3520 INVALIDr, 3521 ING_DVP_TABLE_PARITY_CONTROLr, PARITY_ENf, 3522 ING_DVP_TABLE_PARITY_STATUS_INTRr, NULL, 3523 ING_DVP_TABLE_PARITY_STATUS_NACKr, NULL }, 3524 3525 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3526 PROT_NHI_PAR_ERRf, 3527 PROT_NHI_PAR_ERRf, 3528 INITIAL_PROT_NHI_TABLEm, NULL, 3529 INVALIDr, 3530 INITIAL_PROT_NHI_TABLE_PARITY_CONTROLr, PARITY_ENf, 3531 INITIAL_PROT_NHI_TABLE_PARITY_STATUS_INTRr, NULL, 3532 INITIAL_PROT_NHI_TABLE_PARITY_STATUS_NACKr, NULL }, 3533 3534 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3535 PORT_CBL_PAR_ERRf, 3536 PORT_CBL_PAR_ERRf, 3537 PORT_CBL_TABLEm, NULL, 3538 INVALIDr, 3539 PORT_CBL_TABLE_PARITY_CONTROLr, PARITY_ENf, 3540 PORT_CBL_TABLE_PARITY_STATUS_INTRr, NULL, 3541 PORT_CBL_TABLE_PARITY_STATUS_NACKr, NULL }, 3542 3543 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3544 PORT_CBL_MODBASE_PAR_ERRf, 3545 PORT_CBL_MODBASE_PAR_ERRf, 3546 PORT_CBL_TABLE_MODBASEm, NULL, 3547 INVALIDr, 3548 PORT_CBL_TABLE_MODBASE_PARITY_CONTROLr, PARITY_ENf, 3549 PORT_CBL_TABLE_MODBASE_PARITY_STATUS_INTRr, NULL, 3550 PORT_CBL_TABLE_MODBASE_PARITY_STATUS_NACKr, NULL }, 3551 3552 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3553 L3_IPMC_1_PAR_ERRf, 3554 L3_IPMC_1_PAR_ERRf, 3555 L3_IPMC_1m, NULL, 3556 INVALIDr, 3557 L3_IPMC_1_PARITY_CONTROLr, PARITY_ENf, 3558 L3_IPMC_1_PARITY_STATUS_INTRr, NULL, 3559 L3_IPMC_1_PARITY_STATUS_NACKr, NULL }, 3560 3561 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3562 MA_INDEX_PAR_ERRf, 3563 MA_INDEX_PAR_ERRf, 3564 MA_INDEXm, NULL, 3565 INVALIDr, 3566 MA_INDEX_PARITY_CONTROLr, PARITY_ENf, 3567 MA_INDEX_PARITY_STATUS_INTRr, NULL, 3568 MA_INDEX_PARITY_STATUS_NACKr, NULL }, 3569 3570 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3571 RMEP_PAR_ERRf, 3572 RMEP_PAR_ERRf, 3573 RMEPm, NULL, 3574 INVALIDr, 3575 RMEP_PARITY_CONTROLr, PARITY_ENf, 3576 RMEP_PARITY_STATUS_INTRr, NULL, 3577 RMEP_PARITY_STATUS_NACKr, NULL }, 3578 3579 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3580 MAID_REDUCTION_PAR_ERRf, 3581 MAID_REDUCTION_PAR_ERRf, 3582 MAID_REDUCTIONm, NULL, 3583 INVALIDr, 3584 MAID_REDUCTION_PARITY_CONTROLr, PARITY_ENf, 3585 MAID_REDUCTION_PARITY_STATUS_INTRr, NULL, 3586 MAID_REDUCTION_PARITY_STATUS_NACKr, NULL }, 3587 3588 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3589 MA_STATE_PAR_ERRf, 3590 MA_STATE_PAR_ERRf, 3591 MA_STATEm, NULL, 3592 INVALIDr, 3593 MA_STATE_PARITY_CONTROLr, PARITY_ENf, 3594 MA_STATE_PARITY_STATUS_INTRr, NULL, 3595 MA_STATE_PARITY_STATUS_NACKr, NULL }, 3596 3597 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3598 VLAN_OR_VFI_MAC_COUNT_PAR_ERRf, 3599 VLAN_OR_VFI_MAC_COUNT_PAR_ERRf, 3600 VLAN_OR_VFI_MAC_COUNTm, NULL, 3601 INVALIDr, 3602 VLAN_OR_VFI_MAC_COUNT_PARITY_CONTROLr, PARITY_ENf, 3603 VLAN_OR_VFI_MAC_COUNT_PARITY_STATUS_INTRr, NULL, 3604 VLAN_OR_VFI_MAC_COUNT_PARITY_STATUS_NACKr, NULL }, 3605 3606 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3607 VLAN_OR_VFI_MAC_LIMIT_PAR_ERRf, 3608 VLAN_OR_VFI_MAC_LIMIT_PAR_ERRf, 3609 VLAN_OR_VFI_MAC_LIMITm, NULL, 3610 INVALIDr, 3611 VLAN_OR_VFI_MAC_LIMIT_PARITY_CONTROLr, PARITY_ENf, 3612 VLAN_OR_VFI_MAC_LIMIT_PARITY_STATUS_INTRr, NULL, 3613 VLAN_OR_VFI_MAC_LIMIT_PARITY_STATUS_NACKr, NULL }, 3614 { _SOC_PARITY_TYPE_NONE } /* table terminator */ 3615 }; 3616 3617 STATIC _soc_katana2_parity_info_t _soc_katana2_ip1_1_parity_info[] = { 3618 3619 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3620 RTAG7_PORT_BASED_HASH_PAR_ERRf, 3621 RTAG7_PORT_BASED_HASH_PAR_ERRf, 3622 RTAG7_PORT_BASED_HASHm, NULL, 3623 INVALIDr, 3624 RTAG7_PORT_BASED_HASH_PARITY_CONTROLr, PARITY_ENf, 3625 RTAG7_PORT_BASED_HASH_PARITY_STATUS_INTRr, NULL, 3626 RTAG7_PORT_BASED_HASH_PARITY_STATUS_NACKr, NULL }, 3627 3628 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3629 RX_PROT_GROUP_TABLE_DMA_PAR_ERRf, 3630 RX_PROT_GROUP_TABLE_DMA_PAR_ERRf, 3631 RX_PROT_GROUP_TABLE_DMAm, NULL, 3632 INVALIDr, 3633 RX_PROT_GROUP_TABLE_DMA_PARITY_CONTROLr, PARITY_ENf, 3634 RX_PROT_GROUP_TABLE_DMA_PARITY_STATUS_INTRr, NULL, 3635 RX_PROT_GROUP_TABLE_DMA_PARITY_STATUS_NACKr, NULL }, 3636 3637 { _SOC_PARITY_TYPE_HASH, NULL, 0, 3638 MPLS_ENTRY_PAR_ERRf, 3639 MPLS_ENTRY_PAR_ERRf, 3640 MPLS_ENTRYm, NULL, 3641 INVALIDr, 3642 MPLS_ENTRY_PARITY_CONTROLr, PARITY_ENf, 3643 INVALIDr, _soc_katana2_mpls_entry_intr_reg, 3644 INVALIDr, _soc_katana2_mpls_entry_nack_reg }, 3645 3646 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3647 VLAN_SUBNET_DATA_ONLY_PAR_ERRf, 3648 VLAN_SUBNET_DATA_ONLY_PAR_ERRf, 3649 VLAN_SUBNET_DATA_ONLYm, NULL, 3650 INVALIDr, 3651 VLAN_SUBNET_PARITY_CONTROLr, PARITY_ENf, 3652 VLAN_SUBNET_PARITY_STATUS_INTRr, NULL, 3653 VLAN_SUBNET_PARITY_STATUS_NACKr, NULL }, 3654 3655 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3656 VLAN_PROTOCOL_DATA_PAR_ERRf, 3657 VLAN_PROTOCOL_DATA_PAR_ERRf, 3658 VLAN_PROTOCOL_DATAm, NULL, 3659 INVALIDr, 3660 VLAN_PROT_PARITY_CONTROLr, PARITY_ENf, 3661 VLAN_PROT_PARITY_STATUS_INTRr, NULL, 3662 VLAN_PROT_PARITY_STATUS_NACKr, NULL }, 3663 3664 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3665 VFP_POLICY_PAR_ERRf, 3666 VFP_POLICY_PAR_ERRf, 3667 VFP_POLICY_TABLEm, NULL, 3668 INVALIDr, 3669 VFP_POLICY_PARITY_CONTROLr, PARITY_ENf, 3670 VFP_POLICY_PARITY_STATUS_INTRr, NULL, 3671 VFP_POLICY_PARITY_STATUS_NACKr, NULL }, 3672 3673 { _SOC_PARITY_TYPE_HASH, NULL, 0, 3674 VLAN_XLATE_PAR_ERRf, 3675 VLAN_XLATE_PAR_ERRf, 3676 VLAN_XLATEm, NULL, 3677 INVALIDr, 3678 VLAN_XLATE_PARITY_CONTROLr, PARITY_ENf, 3679 INVALIDr, _soc_katana2_vlan_xlate_intr_reg, 3680 INVALIDr, _soc_katana2_vlan_xlate_nack_reg }, 3681 3682 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3683 INITIAL_PROT_NHI_TABLE_1_DMA_PAR_ERRf, 3684 INITIAL_PROT_NHI_TABLE_1_DMA_PAR_ERRf, 3685 INITIAL_PROT_NHI_TABLE_1_DMAm, NULL, 3686 INVALIDr, 3687 INITIAL_PROT_NHI_TABLE_1_DMA_PARITY_CONTROLr, PARITY_ENf, 3688 INITIAL_PROT_NHI_TABLE_1_DMA_PARITY_STATUS_INTRr, NULL, 3689 INITIAL_PROT_NHI_TABLE_1_DMA_PARITY_STATUS_NACKr, NULL }, 3690 3691 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3692 L2_MOD_FIFO_INTRf, 3693 L2_MOD_FIFO_INTRf, 3694 L2_MOD_FIFOm, NULL, 3695 INVALIDr, 3696 L2_MOD_FIFO_PARITY_CONTROLr, PARITY_ENf, 3697 L2_MOD_FIFO_PARITY_STATUS_INTRr, NULL, 3698 L2_MOD_FIFO_PARITY_STATUS_NACKr, NULL }, 3699 3700 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3701 MY_STATION_TCAM_DATA_ONLY_PAR_ERRf, 3702 MY_STATION_TCAM_DATA_ONLY_PAR_ERRf, 3703 MY_STATION_TCAM_DATA_ONLYm, NULL, 3704 INVALIDr, 3705 MY_STATION_DATA_PARITY_CONTROLr, PARITY_ENf, 3706 MY_STATION_TCAM_DATA_ONLY_PARITY_STATUS_INTRr, NULL, 3707 MY_STATION_TCAM_DATA_ONLY_PARITY_STATUS_NACKr, NULL }, 3708 3709 { _SOC_PARITY_TYPE_NONE } /* table terminator */ 3710 }; 3711 3712 STATIC _soc_katana2_parity_info_t _soc_katana2_ip2_parity_info[] = { 3713 3714 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3715 IFP_METER_PARITY_ERRORf, 3716 IFP_METER_PARITY_ERRORf, 3717 FP_METER_TABLEm, NULL, 3718 INVALIDr, 3719 IFP_METER_PARITY_CONTROLr, PARITY_ENf, 3720 IFP_METER_PARITY_STATUS_INTRr, NULL, 3721 IFP_METER_PARITY_STATUS_NACKr, NULL }, 3722 3723 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3724 IFP_COUNTER_PARITY_ERRORf, 3725 IFP_COUNTER_PARITY_ERRORf, 3726 FP_COUNTER_TABLEm, NULL, 3727 INVALIDr, 3728 IFP_COUNTER_PARITY_CONTROLr, PARITY_ENf, 3729 IFP_COUNTER_PARITY_STATUS_INTRr, NULL, 3730 IFP_COUNTER_PARITY_STATUS_NACKr, NULL }, 3731 3732 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3733 IFP_POLICY_PARITY_ERRORf, 3734 IFP_POLICY_PARITY_ERRORf, 3735 FP_POLICY_TABLEm, NULL, 3736 INVALIDr, 3737 IFP_POLICY_PARITY_CONTROLr, PARITY_ENf, 3738 IFP_POLICY_PARITY_STATUS_INTRr, NULL, 3739 IFP_POLICY_PARITY_STATUS_NACKr, NULL }, 3740 3741 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3742 IFP_STORM_CONTROL_PARITY_ERRORf, 3743 IFP_STORM_CONTROL_PARITY_ERRORf, 3744 FP_STORM_CONTROL_METERSm, NULL, 3745 INVALIDr, 3746 IFP_STORM_CONTROL_PARITY_CONTROLr, PARITY_ENf, 3747 IFP_STORM_CONTROL_PARITY_STATUS_INTRr, NULL, 3748 IFP_STORM_CONTROL_PARITY_STATUS_NACKr, NULL }, 3749 3750 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3751 SVC_MACROFLOW_TABLE_PARITY_ERRORf, 3752 SVC_MACROFLOW_TABLE_PARITY_ERRORf, 3753 SVM_MACROFLOW_INDEX_TABLEm, "SVM MACROFLOW", 3754 INVALIDr, 3755 ING_SVM_MACROFLOW_INDEX_TABLE_CONTROLr, PARITY_ENf, 3756 ING_SVM_MACROFLOW_INDEX_TABLE_PARITY_STATUS_INTRr, NULL, 3757 ING_SVM_MACROFLOW_INDEX_TABLE_PARITY_STATUS_NACKr, NULL }, 3758 3759 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3760 SVC_OFFSET_TABLE_PARITY_ERRORf, 3761 SVC_OFFSET_TABLE_PARITY_ERRORf, 3762 SVM_OFFSET_TABLEm, "SVM OFFSET", 3763 INVALIDr, 3764 ING_SVM_OFFSET_TABLE_CONTROLr, PARITY_ENf, 3765 ING_SVM_OFFSET_TABLE_PARITY_STATUS_INTRr, NULL, 3766 ING_SVM_OFFSET_TABLE_PARITY_STATUS_NACKr, NULL }, 3767 3768 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3769 SVC_METER_TABLE_PARITY_ERRORf, 3770 SVC_METER_TABLE_PARITY_ERRORf, 3771 SVM_METER_TABLEm, "SVM METER", 3772 INVALIDr, 3773 ING_SVM_METER_TABLE_CONTROLr, PARITY_ENf, 3774 ING_SVM_METER_TABLE_PARITY_STATUS_INTRr, NULL, 3775 ING_SVM_METER_TABLE_PARITY_STATUS_NACKr, NULL }, 3776 3777 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3778 SVC_POLICY_TABLE_PARITY_ERRORf, 3779 SVC_POLICY_TABLE_PARITY_ERRORf, 3780 SVM_POLICY_TABLEm, "SVM POLICY", 3781 INVALIDr, 3782 ING_SVM_POLICY_TABLE_CONTROLr, PARITY_ENf, 3783 ING_SVM_POLICY_TABLE_PARITY_STATUS_INTRr, NULL, 3784 ING_SVM_POLICY_TABLE_PARITY_STATUS_NACKr, NULL }, 3785 3786 { _SOC_PARITY_TYPE_NONE } /* table terminator */ 3787 }; 3788 3789 STATIC _soc_katana2_parity_info_t _soc_katana2_ip3_parity_info[] = { 3790 3791 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3792 DLB_HGT_FLOWSET_PORT_PAR_ERRf, 3793 DLB_HGT_FLOWSET_PORT_PAR_ERRf, 3794 INVALIDm, NULL, 3795 INVALIDr, 3796 DLB_HGT_FLOWSET_PORT_PARITY_CONTROLr, PARITY_ENf, 3797 DLB_HGT_FLOWSET_PORT_PARITY_STATUS_INTRr, NULL, 3798 DLB_HGT_FLOWSET_PORT_PARITY_STATUS_NACKr, NULL }, 3799 3800 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3801 DLB_HGT_FLOWSET_TIMESTAMP_PAR_ERRf, 3802 DLB_HGT_FLOWSET_TIMESTAMP_PAR_ERRf, 3803 INVALIDm, NULL, 3804 INVALIDr, 3805 DLB_HGT_FLOWSET_TIMESTAMP_PARITY_CONTROLr, PARITY_ENf, 3806 DLB_HGT_FLOWSET_TIMESTAMP_PARITY_STATUS_INTRr, NULL, 3807 DLB_HGT_FLOWSET_TIMESTAMP_PARITY_STATUS_NACKr, NULL }, 3808 3809 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3810 DLB_HGT_FLOWSET_TIMESTAMP_PAGE_PAR_ERRf, 3811 DLB_HGT_FLOWSET_TIMESTAMP_PAGE_PAR_ERRf, 3812 INVALIDm, NULL, 3813 INVALIDr, 3814 DLB_HGT_FLOWSET_TIMESTAMP_PAGE_PARITY_CONTROLr, PARITY_ENf, 3815 DLB_HGT_FLOWSET_TIMESTAMP_PAGE_PARITY_STATUS_INTRr, NULL, 3816 DLB_HGT_FLOWSET_TIMESTAMP_PAGE_PARITY_STATUS_NACKr, NULL }, 3817 3818 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3819 IRSEL2_ING_L3_NEXT_HOP_PAR_ERRf, 3820 IRSEL2_ING_L3_NEXT_HOP_PAR_ERRf, 3821 ING_L3_NEXT_HOPm, NULL, 3822 INVALIDr, 3823 ING_L3_NEXT_HOP_PARITY_CONTROLr, PARITY_ENf, 3824 ING_L3_NEXT_HOP_PARITY_STATUS_INTRr, NULL, 3825 ING_L3_NEXT_HOP_PARITY_STATUS_NACKr, NULL }, 3826 3827 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3828 IRSEL2_L3_IPMC_REMAP_PAR_ERRf, 3829 IRSEL2_L3_IPMC_REMAP_PAR_ERRf, 3830 L3_IPMC_REMAPm, NULL, 3831 INVALIDr, 3832 L3_IPMC_REMAP_PARITY_CONTROLr, PARITY_ENf, 3833 L3_IPMC_REMAP_PARITY_STATUS_INTRr, NULL, 3834 L3_IPMC_REMAP_PARITY_STATUS_NACKr, NULL }, 3835 3836 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3837 IRSEL2_L3_IPMC_PAR_ERRf, 3838 IRSEL2_L3_IPMC_PAR_ERRf, 3839 L3_IPMCm, NULL, 3840 INVALIDr, 3841 L3_IPMC_PARITY_CONTROLr, PARITY_ENf, 3842 L3_IPMC_PARITY_STATUS_INTRr, NULL, 3843 L3_IPMC_PARITY_STATUS_NACKr, NULL }, 3844 3845 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3846 IRSEL2_L2MC_PAR_ERRf, 3847 IRSEL2_L2MC_PAR_ERRf, 3848 L2MCm, NULL, 3849 INVALIDr, 3850 L2MC_PARITY_CONTROLr, PARITY_ENf, 3851 L2MC_PARITY_STATUS_INTRr, NULL, 3852 L2MC_PARITY_STATUS_NACKr, NULL }, 3853 3854 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3855 IRSEL2_IFP_REDIRECTION_PROFILE_PAR_ERRf, 3856 IRSEL2_IFP_REDIRECTION_PROFILE_PAR_ERRf, 3857 IFP_REDIRECTION_PROFILEm, NULL, 3858 INVALIDr, 3859 IFP_REDIRECTION_PROFILE_PARITY_CONTROLr, PARITY_ENf, 3860 IFP_REDIRECTION_PROFILE_PARITY_STATUS_INTRr, NULL, 3861 IFP_REDIRECTION_PROFILE_PARITY_STATUS_NACKr, NULL }, 3862 3863 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3864 IRSEL2_L3_ECMP_GROUP_PAR_ERRf, 3865 IRSEL2_L3_ECMP_GROUP_PAR_ERRf, 3866 L3_ECMP_COUNTm, NULL, 3867 INVALIDr, 3868 L3_ECMP_GROUP_PARITY_CONTROLr, PARITY_ENf, 3869 L3_ECMP_GROUP_PARITY_STATUS_INTRr, NULL, 3870 L3_ECMP_GROUP_PARITY_STATUS_NACKr, NULL }, 3871 3872 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3873 IRSEL2_L3_ECMP_PAR_ERRf, 3874 IRSEL2_L3_ECMP_PAR_ERRf, 3875 L3_ECMPm, NULL, 3876 INVALIDr, 3877 L3_ECMP_PARITY_CONTROLr, PARITY_ENf, 3878 L3_ECMP_PARITY_STATUS_INTRr, NULL, 3879 L3_ECMP_PARITY_STATUS_NACKr, NULL }, 3880 3881 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3882 IRSEL2_EGR_MASK_MODBASE_PAR_ERRf, 3883 IRSEL2_EGR_MASK_MODBASE_PAR_ERRf, 3884 EGR_MASK_MODBASEm, NULL, 3885 INVALIDr, 3886 EGR_MASK_MODBASE_PARITY_CONTROLr, PARITY_ENf, 3887 EGR_MASK_MODBASE_PARITY_STATUS_INTRr, NULL, 3888 EGR_MASK_MODBASE_PARITY_STATUS_NACKr, NULL }, 3889 3890 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3891 ICONTROL_OPCODE_BITMAP_PAR_ERRf, 3892 ICONTROL_OPCODE_BITMAP_PAR_ERRf, 3893 ICONTROL_OPCODE_BITMAPm, NULL, 3894 INVALIDr, 3895 ICONTROL_OPCODE_BITMAP_PARITY_CONTROLr, PARITY_ENf, 3896 ICONTROL_OPCODE_BITMAP_PARITY_STATUS_INTRr, NULL, 3897 ICONTROL_OPCODE_BITMAP_PARITY_STATUS_NACKr, NULL }, 3898 3899 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3900 ING_FLEX_CTR_POOL_0_OFFSET_TABLE_INTR_STATUSf, 3901 ING_FLEX_CTR_POOL_0_OFFSET_TABLE_INTR_STATUSf, 3902 ING_FLEX_CTR_OFFSET_TABLE_0m, NULL, 3903 INVALIDr, 3904 ING_FLEX_CTR_OFFSET_TABLE_CONTROL_0r, PARITY_ENf, 3905 ING_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_INTR_0r, NULL, 3906 ING_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_NACK_0r, NULL }, 3907 3908 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3909 ING_FLEX_CTR_POOL_1_OFFSET_TABLE_INTR_STATUSf, 3910 ING_FLEX_CTR_POOL_1_OFFSET_TABLE_INTR_STATUSf, 3911 ING_FLEX_CTR_OFFSET_TABLE_1m, NULL, 3912 INVALIDr, 3913 ING_FLEX_CTR_OFFSET_TABLE_CONTROL_1r, PARITY_ENf, 3914 ING_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_INTR_1r, NULL, 3915 ING_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_NACK_1r, NULL }, 3916 3917 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3918 ING_FLEX_CTR_POOL_2_OFFSET_TABLE_INTR_STATUSf, 3919 ING_FLEX_CTR_POOL_2_OFFSET_TABLE_INTR_STATUSf, 3920 ING_FLEX_CTR_OFFSET_TABLE_2m, NULL, 3921 INVALIDr, 3922 ING_FLEX_CTR_OFFSET_TABLE_CONTROL_2r, PARITY_ENf, 3923 ING_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_INTR_2r, NULL, 3924 ING_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_NACK_2r, NULL }, 3925 3926 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3927 ING_FLEX_CTR_POOL_3_OFFSET_TABLE_INTR_STATUSf, 3928 ING_FLEX_CTR_POOL_3_OFFSET_TABLE_INTR_STATUSf, 3929 ING_FLEX_CTR_OFFSET_TABLE_3m, NULL, 3930 INVALIDr, 3931 ING_FLEX_CTR_OFFSET_TABLE_CONTROL_3r, PARITY_ENf, 3932 ING_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_INTR_3r, NULL, 3933 ING_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_NACK_3r, NULL }, 3934 3935 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3936 ING_FLEX_CTR_POOL_4_OFFSET_TABLE_INTR_STATUSf, 3937 ING_FLEX_CTR_POOL_4_OFFSET_TABLE_INTR_STATUSf, 3938 ING_FLEX_CTR_OFFSET_TABLE_4m, NULL, 3939 INVALIDr, 3940 ING_FLEX_CTR_OFFSET_TABLE_CONTROL_4r, PARITY_ENf, 3941 ING_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_INTR_4r, NULL, 3942 ING_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_NACK_4r, NULL }, 3943 3944 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3945 ING_FLEX_CTR_POOL_5_OFFSET_TABLE_INTR_STATUSf, 3946 ING_FLEX_CTR_POOL_5_OFFSET_TABLE_INTR_STATUSf, 3947 ING_FLEX_CTR_OFFSET_TABLE_5m, NULL, 3948 INVALIDr, 3949 ING_FLEX_CTR_OFFSET_TABLE_CONTROL_5r, PARITY_ENf, 3950 ING_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_INTR_5r, NULL, 3951 ING_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_NACK_5r, NULL }, 3952 3953 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3954 ING_FLEX_CTR_POOL_6_OFFSET_TABLE_INTR_STATUSf, 3955 ING_FLEX_CTR_POOL_6_OFFSET_TABLE_INTR_STATUSf, 3956 ING_FLEX_CTR_OFFSET_TABLE_6m, NULL, 3957 INVALIDr, 3958 ING_FLEX_CTR_OFFSET_TABLE_CONTROL_6r, PARITY_ENf, 3959 ING_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_INTR_6r, NULL, 3960 ING_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_NACK_6r, NULL }, 3961 3962 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3963 ING_FLEX_CTR_POOL_7_OFFSET_TABLE_INTR_STATUSf, 3964 ING_FLEX_CTR_POOL_7_OFFSET_TABLE_INTR_STATUSf, 3965 ING_FLEX_CTR_OFFSET_TABLE_7m, NULL, 3966 INVALIDr, 3967 ING_FLEX_CTR_OFFSET_TABLE_CONTROL_7r, PARITY_ENf, 3968 ING_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_INTR_7r, NULL, 3969 ING_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_NACK_7r, NULL }, 3970 3971 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3972 ING_FLEX_CTR_POOL_0_COUNTER_TABLE_INTR_STATUSf, 3973 ING_FLEX_CTR_POOL_0_COUNTER_TABLE_INTR_STATUSf, 3974 ING_FLEX_CTR_COUNTER_TABLE_0m, NULL, 3975 INVALIDr, 3976 ING_FLEX_CTR_COUNTER_TABLE_CONTROL_0r, PARITY_ENf, 3977 ING_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_INTR_0r, NULL, 3978 ING_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_NACK_0r, NULL }, 3979 3980 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3981 ING_FLEX_CTR_POOL_1_COUNTER_TABLE_INTR_STATUSf, 3982 ING_FLEX_CTR_POOL_1_COUNTER_TABLE_INTR_STATUSf, 3983 ING_FLEX_CTR_COUNTER_TABLE_1m, NULL, 3984 INVALIDr, 3985 ING_FLEX_CTR_COUNTER_TABLE_CONTROL_1r, PARITY_ENf, 3986 ING_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_INTR_1r, NULL, 3987 ING_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_NACK_1r, NULL }, 3988 3989 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3990 ING_FLEX_CTR_POOL_2_COUNTER_TABLE_INTR_STATUSf, 3991 ING_FLEX_CTR_POOL_2_COUNTER_TABLE_INTR_STATUSf, 3992 ING_FLEX_CTR_COUNTER_TABLE_2m, NULL, 3993 INVALIDr, 3994 ING_FLEX_CTR_COUNTER_TABLE_CONTROL_2r, PARITY_ENf, 3995 ING_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_INTR_2r, NULL, 3996 ING_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_NACK_2r, NULL }, 3997 3998 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3999 ING_FLEX_CTR_POOL_3_COUNTER_TABLE_INTR_STATUSf, 4000 ING_FLEX_CTR_POOL_3_COUNTER_TABLE_INTR_STATUSf, 4001 ING_FLEX_CTR_COUNTER_TABLE_3m, NULL, 4002 INVALIDr, 4003 ING_FLEX_CTR_COUNTER_TABLE_CONTROL_3r, PARITY_ENf, 4004 ING_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_INTR_3r, NULL, 4005 ING_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_NACK_3r, NULL }, 4006 4007 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 4008 ING_FLEX_CTR_POOL_4_COUNTER_TABLE_INTR_STATUSf, 4009 ING_FLEX_CTR_POOL_4_COUNTER_TABLE_INTR_STATUSf, 4010 ING_FLEX_CTR_COUNTER_TABLE_4m, NULL, 4011 INVALIDr, 4012 ING_FLEX_CTR_COUNTER_TABLE_CONTROL_4r, PARITY_ENf, 4013 ING_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_INTR_4r, NULL, 4014 ING_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_NACK_4r, NULL }, 4015 4016 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 4017 ING_FLEX_CTR_POOL_5_COUNTER_TABLE_INTR_STATUSf, 4018 ING_FLEX_CTR_POOL_5_COUNTER_TABLE_INTR_STATUSf, 4019 ING_FLEX_CTR_COUNTER_TABLE_5m, NULL, 4020 INVALIDr, 4021 ING_FLEX_CTR_COUNTER_TABLE_CONTROL_5r, PARITY_ENf, 4022 ING_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_INTR_5r, NULL, 4023 ING_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_NACK_5r, NULL }, 4024 4025 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 4026 ING_FLEX_CTR_POOL_6_COUNTER_TABLE_INTR_STATUSf, 4027 ING_FLEX_CTR_POOL_6_COUNTER_TABLE_INTR_STATUSf, 4028 ING_FLEX_CTR_COUNTER_TABLE_6m, NULL, 4029 INVALIDr, 4030 ING_FLEX_CTR_COUNTER_TABLE_CONTROL_6r, PARITY_ENf, 4031 ING_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_INTR_6r, NULL, 4032 ING_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_NACK_6r, NULL }, 4033 4034 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 4035 ING_FLEX_CTR_POOL_7_COUNTER_TABLE_INTR_STATUSf, 4036 ING_FLEX_CTR_POOL_7_COUNTER_TABLE_INTR_STATUSf, 4037 ING_FLEX_CTR_COUNTER_TABLE_7m, NULL, 4038 INVALIDr, 4039 ING_FLEX_CTR_COUNTER_TABLE_CONTROL_7r, PARITY_ENf, 4040 ING_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_INTR_7r, NULL, 4041 ING_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_NACK_7r, NULL }, 4042 4043 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 4044 SFLOW_ING_THRESHOLD_PAR_ERRf, 4045 SFLOW_ING_THRESHOLD_PAR_ERRf, 4046 INVALIDm, NULL, 4047 SFLOW_ING_THRESHOLDr, 4048 SFLOW_ING_THRESHOLD_PARITY_CONTROLr, PARITY_ENf, 4049 SFLOW_ING_THRESHOLD_PARITY_STATUS_INTRr, NULL, 4050 SFLOW_ING_THRESHOLD_PARITY_STATUS_NACKr, NULL }, 4051 4052 { _SOC_PARITY_TYPE_NONE } /* table terminator */ 4053 }; 4054 4055 STATIC _soc_katana2_parity_info_t _soc_katana2_ip3_1_parity_info[] = { 4056 4057 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 4058 EGR_MASK_PAR_ERRf, 4059 EGR_MASK_PAR_ERRf, 4060 EGR_MASKm, NULL, 4061 INVALIDr, 4062 EGR_MASK_PARITY_CONTROLr, PARITY_ENf, 4063 EGR_MASK_PARITY_STATUS_INTRr, NULL, 4064 EGR_MASK_PARITY_STATUS_NACKr, NULL }, 4065 4066 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 4067 TRUNK_BITMAP_PAR_ERRf, 4068 TRUNK_BITMAP_PAR_ERRf, 4069 TRUNK_BITMAPm, NULL, 4070 INVALIDr, 4071 TRUNK_BITMAP_TABLE_PARITY_CONTROLr, PARITY_ENf, 4072 TRUNK_BITMAP_TABLE_PARITY_STATUS_INTRr, NULL, 4073 TRUNK_BITMAP_TABLE_PARITY_STATUS_NACKr, NULL }, 4074 4075 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 4076 NONUCAST_TRUNK_BLOCK_MASK_PAR_ERRf, 4077 NONUCAST_TRUNK_BLOCK_MASK_PAR_ERRf, 4078 NONUCAST_TRUNK_BLOCK_MASKm, NULL, 4079 INVALIDr, 4080 NONUCAST_TRUNK_BLOCK_MASK_PARITY_CONTROLr, PARITY_ENf, 4081 NONUCAST_TRUNK_BLOCK_MASK_PARITY_STATUS_INTRr, NULL, 4082 NONUCAST_TRUNK_BLOCK_MASK_PARITY_STATUS_NACKr, NULL }, 4083 4084 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 4085 MAC_BLOCK_TABLE_PAR_ERRf, 4086 MAC_BLOCK_TABLE_PAR_ERRf, 4087 MAC_BLOCKm, NULL, 4088 INVALIDr, 4089 MAC_BLOCK_TABLE_PARITY_CONTROLr, PARITY_ENf, 4090 MAC_BLOCK_TABLE_PARITY_STATUS_INTRr, NULL, 4091 MAC_BLOCK_TABLE_PARITY_STATUS_NACKr, NULL }, 4092 4093 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 4094 MODPORT_MAP_SW_PAR_ERRf, 4095 MODPORT_MAP_SW_PAR_ERRf, 4096 MODPORT_MAP_SWm, NULL, 4097 INVALIDr, 4098 MODPORT_MAP_SW_PARITY_CONTROLr, PARITY_ENf, 4099 MODPORT_MAP_SW_PARITY_STATUS_INTRr, NULL, 4100 MODPORT_MAP_SW_PARITY_STATUS_NACKr, NULL }, 4101 4102 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 4103 MODPORT_MAP_M0_PAR_ERRf, 4104 MODPORT_MAP_M0_PAR_ERRf, 4105 MODPORT_MAP_M0m, NULL, 4106 INVALIDr, 4107 MODPORT_MAP_MIRROR_PARITY_CONTROLr, PARITY_ENf, 4108 MODPORT_MAP_M0_PARITY_STATUS_INTRr, NULL, 4109 MODPORT_MAP_M0_PARITY_STATUS_NACKr, NULL }, 4110 4111 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 4112 MODPORT_MAP_M1_PAR_ERRf, 4113 MODPORT_MAP_M1_PAR_ERRf, 4114 MODPORT_MAP_M1m, NULL, 4115 INVALIDr, 4116 MODPORT_MAP_MIRROR_PARITY_CONTROLr, PARITY_ENf, 4117 MODPORT_MAP_M1_PARITY_STATUS_INTRr, NULL, 4118 MODPORT_MAP_M1_PARITY_STATUS_NACKr, NULL }, 4119 4120 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 4121 MODPORT_MAP_M2_PAR_ERRf, 4122 MODPORT_MAP_M2_PAR_ERRf, 4123 MODPORT_MAP_M2m, NULL, 4124 INVALIDr, 4125 MODPORT_MAP_MIRROR_PARITY_CONTROLr, PARITY_ENf, 4126 MODPORT_MAP_M2_PARITY_STATUS_INTRr, NULL, 4127 MODPORT_MAP_M2_PARITY_STATUS_NACKr, NULL }, 4128 4129 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 4130 MODPORT_MAP_M3_PAR_ERRf, 4131 MODPORT_MAP_M3_PAR_ERRf, 4132 MODPORT_MAP_M3m, NULL, 4133 INVALIDr, 4134 MODPORT_MAP_MIRROR_PARITY_CONTROLr, PARITY_ENf, 4135 MODPORT_MAP_M3_PARITY_STATUS_INTRr, NULL, 4136 MODPORT_MAP_M3_PARITY_STATUS_NACKr, NULL }, 4137 4138 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 4139 SRC_MODID_INGRESS_BLOCK_PAR_ERRf, 4140 SRC_MODID_INGRESS_BLOCK_PAR_ERRf, 4141 SRC_MODID_INGRESS_BLOCKm, NULL, 4142 INVALIDr, 4143 SRC_MODID_INGRESS_BLOCK_PARITY_CONTROLr, PARITY_ENf, 4144 SRC_MODID_INGRESS_BLOCK_PARITY_STATUS_INTRr, NULL, 4145 SRC_MODID_INGRESS_BLOCK_PARITY_STATUS_NACKr, NULL }, 4146 4147 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 4148 SRC_MODID_EGRESS_PAR_ERRf, 4149 SRC_MODID_EGRESS_PAR_ERRf, 4150 SRC_MODID_EGRESSm, NULL, 4151 INVALIDr, 4152 SRC_MODID_EGRESS_PARITY_CONTROLr, PARITY_ENf, 4153 SRC_MODID_EGRESS_PARITY_STATUS_INTRr, NULL, 4154 SRC_MODID_EGRESS_PARITY_STATUS_NACKr, NULL }, 4155 4156 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 4157 ALTERNATE_EMIRROR_BITMAP_PAR_ERRf, 4158 ALTERNATE_EMIRROR_BITMAP_PAR_ERRf, 4159 ALTERNATE_EMIRROR_BITMAPm, NULL, 4160 INVALIDr, 4161 ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROLr, PARITY_ENf, 4162 ALTERNATE_EMIRROR_BITMAP_PARITY_STATUS_INTRr, NULL, 4163 ALTERNATE_EMIRROR_BITMAP_PARITY_STATUS_NACKr, NULL }, 4164 4165 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 4166 PORT_LAG_FAILOVER_SET_PAR_ERRf, 4167 PORT_LAG_FAILOVER_SET_PAR_ERRf, 4168 PORT_LAG_FAILOVER_SETm, NULL, 4169 INVALIDr, 4170 PORT_LAG_FAILOVER_SET_PARITY_CONTROLr, PARITY_ENf, 4171 PORT_LAG_FAILOVER_SET_PARITY_STATUS_INTRr, NULL, 4172 PORT_LAG_FAILOVER_SET_PARITY_STATUS_NACKr, NULL }, 4173 4174 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 4175 VLAN_PROFILE_2_PAR_ERRf, 4176 VLAN_PROFILE_2_PAR_ERRf, 4177 VLAN_PROFILE_2m, NULL, 4178 INVALIDr, 4179 VLAN_PROFILE_2_PARITY_CONTROLr, PARITY_ENf, 4180 VLAN_PROFILE_2_PARITY_STATUS_INTRr, NULL, 4181 VLAN_PROFILE_2_PARITY_STATUS_NACKr, NULL }, 4182 4183 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 4184 L3_MTU_VALUES_PAR_ERRf, 4185 L3_MTU_VALUES_PAR_ERRf, 4186 L3_MTU_VALUESm, NULL, 4187 INVALIDr, 4188 L3_MTU_VALUES_PARITY_CONTROLr, PARITY_ENf, 4189 L3_MTU_VALUES_PARITY_STATUS_INTRr, NULL, 4190 L3_MTU_VALUES_PARITY_STATUS_NACKr, NULL }, 4191 4192 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 4193 ING_PW_TERM_SEQ_NUM_PAR_ERRf, 4194 ING_PW_TERM_SEQ_NUM_PAR_ERRf, 4195 ING_PW_TERM_SEQ_NUMm, NULL, 4196 INVALIDr, 4197 ING_PW_TERM_SEQ_NUM_PARITY_CONTROLr, PARITY_ENf, 4198 ING_PW_TERM_SEQ_NUM_PARITY_STATUS_INTRr, NULL, 4199 ING_PW_TERM_SEQ_NUM_PARITY_STATUS_NACKr, NULL }, 4200 4201 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 4202 ING_FLEX_CTR_PKT_RES_MAP_PAR_ERRf, 4203 ING_FLEX_CTR_PKT_RES_MAP_PAR_ERRf, 4204 ING_FLEX_CTR_PKT_RES_MAPm, NULL, 4205 INVALIDr, 4206 ING_FLEX_CTR_PKT_RES_MAP_PARITY_CONTROLr, PARITY_ENf, 4207 ING_FLEX_CTR_PKT_RES_MAP_PARITY_STATUS_INTRr, NULL, 4208 ING_FLEX_CTR_PKT_RES_MAP_PARITY_STATUS_NACKr, NULL }, 4209 4210 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 4211 IRSEL2_L3_IPMC_2_PAR_ERRf, 4212 IRSEL2_L3_IPMC_2_PAR_ERRf, 4213 L3_IPMC_2m, NULL, 4214 INVALIDr, 4215 L3_IPMC_2_PARITY_CONTROLr, PARITY_ENf, 4216 L3_IPMC_2_PARITY_STATUS_INTRr, NULL, 4217 L3_IPMC_2_PARITY_STATUS_NACKr, NULL }, 4218 4219 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 4220 SERVICE_COS_MAP_PAR_ERRf, 4221 SERVICE_COS_MAP_PAR_ERRf, 4222 SERVICE_COS_MAPm, NULL, 4223 INVALIDr, 4224 SERVICE_COS_MAP_PARITY_CONTROLr, PARITY_ENf, 4225 SERVICE_COS_MAP_PARITY_STATUS_INTRr, NULL, 4226 SERVICE_COS_MAP_PARITY_STATUS_NACKr, NULL }, 4227 4228 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 4229 E2E_HOL_STATUS_PAR_ERRf, 4230 E2E_HOL_STATUS_PAR_ERRf, 4231 E2E_HOL_STATUSm, NULL, 4232 INVALIDr, 4233 E2E_HOL_STATUS_PARITY_CONTROLr, PARITY_ENf, 4234 E2E_HOL_STATUS_PARITY_STATUS_INTRr, NULL, 4235 E2E_HOL_STATUS_PARITY_STATUS_NACKr, NULL }, 4236 4237 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 4238 E2E_HOL_STATUS_1_PAR_ERRf, 4239 E2E_HOL_STATUS_1_PAR_ERRf, 4240 E2E_HOL_STATUS_1m, NULL, 4241 INVALIDr, 4242 E2E_HOL_STATUS_1_PARITY_CONTROLr, PARITY_ENf, 4243 E2E_HOL_STATUS_1_PARITY_STATUS_INTRr, NULL, 4244 E2E_HOL_STATUS_1_PARITY_STATUS_NACKr, NULL }, 4245 4246 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 4247 UNKNOWN_UCAST_BLOCK_MASK_PAR_ERRf, 4248 UNKNOWN_UCAST_BLOCK_MASK_PAR_ERRf, 4249 UNKNOWN_UCAST_BLOCK_MASKm, NULL, 4250 INVALIDr, 4251 UNKNOWN_UCAST_BLOCK_MASK_PARITY_CONTROLr, PARITY_ENf, 4252 UNKNOWN_UCAST_BLOCK_MASK_PARITY_STATUS_INTRr, NULL, 4253 UNKNOWN_UCAST_BLOCK_MASK_PARITY_STATUS_NACKr, NULL }, 4254 4255 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 4256 UNKNOWN_MCAST_BLOCK_MASK_PAR_ERRf, 4257 UNKNOWN_MCAST_BLOCK_MASK_PAR_ERRf, 4258 UNKNOWN_MCAST_BLOCK_MASKm, NULL, 4259 INVALIDr, 4260 UNKNOWN_MCAST_BLOCK_MASK_PARITY_CONTROLr, PARITY_ENf, 4261 UNKNOWN_MCAST_BLOCK_MASK_PARITY_STATUS_INTRr, NULL, 4262 UNKNOWN_MCAST_BLOCK_MASK_PARITY_STATUS_NACKr, NULL }, 4263 4264 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 4265 BCAST_BLOCK_MASK_PAR_ERRf, 4266 BCAST_BLOCK_MASK_PAR_ERRf, 4267 BCAST_BLOCK_MASKm, NULL, 4268 INVALIDr, 4269 BCAST_BLOCK_MASK_PARITY_CONTROLr, PARITY_ENf, 4270 BCAST_BLOCK_MASK_PARITY_STATUS_INTRr, NULL, 4271 BCAST_BLOCK_MASK_PARITY_STATUS_NACKr, NULL }, 4272 4273 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 4274 KNOWN_MCAST_BLOCK_MASK_PAR_ERRf, 4275 KNOWN_MCAST_BLOCK_MASK_PAR_ERRf, 4276 KNOWN_MCAST_BLOCK_MASKm, NULL, 4277 INVALIDr, 4278 KNOWN_MCAST_BLOCK_MASK_PARITY_CONTROLr, PARITY_ENf, 4279 KNOWN_MCAST_BLOCK_MASK_PARITY_STATUS_INTRr, NULL, 4280 KNOWN_MCAST_BLOCK_MASK_PARITY_STATUS_NACKr, NULL }, 4281 4282 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 4283 ING_EGRMSKBMAP_PAR_ERRf, 4284 ING_EGRMSKBMAP_PAR_ERRf, 4285 ING_EGRMSKBMAPm, NULL, 4286 INVALIDr, 4287 ING_EGRMSKBMAP_PARITY_CONTROLr, PARITY_ENf, 4288 ING_EGRMSKBMAP_PARITY_STATUS_INTRr, NULL, 4289 ING_EGRMSKBMAP_PARITY_STATUS_NACKr, NULL }, 4290 4291 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 4292 LOCAL_SW_DISABLE_DEFAULT_PBM_PAR_ERRf, 4293 LOCAL_SW_DISABLE_DEFAULT_PBM_PAR_ERRf, 4294 LOCAL_SW_DISABLE_DEFAULT_PBMm, NULL, 4295 INVALIDr, 4296 LOCAL_SW_DISABLE_DEFAULT_PBM_PARITY_CONTROLr, PARITY_ENf, 4297 LOCAL_SW_DISABLE_DEFAULT_PBM_PARITY_STATUS_INTRr, NULL, 4298 LOCAL_SW_DISABLE_DEFAULT_PBM_PARITY_STATUS_NACKr, NULL }, 4299 4300 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 4301 LOCAL_SW_DISABLE_DEFAULT_PBM_MIRR_PAR_ERRf, 4302 LOCAL_SW_DISABLE_DEFAULT_PBM_MIRR_PAR_ERRf, 4303 LOCAL_SW_DISABLE_DEFAULT_PBM_MIRRm, NULL, 4304 INVALIDr, 4305 LOCAL_SW_DISABLE_DEFAULT_PBM_MIRR_PARITY_CONTROLr, PARITY_ENf, 4306 LOCAL_SW_DISABLE_DEFAULT_PBM_MIRR_PARITY_STATUS_INTRr, NULL, 4307 LOCAL_SW_DISABLE_DEFAULT_PBM_MIRR_PARITY_STATUS_NACKr, NULL }, 4308 4309 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 4310 IMIRROR_BITMAP_PAR_ERRf, 4311 IMIRROR_BITMAP_PAR_ERRf, 4312 IMIRROR_BITMAPm, NULL, 4313 INVALIDr, 4314 IMIRROR_BITMAP_PARITY_CONTROLr, PARITY_ENf, 4315 IMIRROR_BITMAP_PARITY_STATUS_INTRr, NULL, 4316 IMIRROR_BITMAP_PARITY_STATUS_NACKr, NULL }, 4317 4318 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 4319 UNKNOWN_HGI_BITMAP_PAR_ERRf, 4320 UNKNOWN_HGI_BITMAP_PAR_ERRf, 4321 UNKNOWN_HGI_BITMAPm, NULL, 4322 INVALIDr, 4323 UNKNOWN_HGI_BITMAP_PARITY_CONTROLr, PARITY_ENf, 4324 UNKNOWN_HGI_BITMAP_PARITY_STATUS_INTRr, NULL, 4325 UNKNOWN_HGI_BITMAP_PARITY_STATUS_NACKr, NULL }, 4326 4327 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 4328 TRUNK_MEMBER_PAR_ERRf, 4329 TRUNK_MEMBER_PAR_ERRf, 4330 TRUNK_MEMBERm, NULL, 4331 INVALIDr, 4332 TRUNK_MEMBER_PARITY_CONTROLr, PARITY_ENf, 4333 TRUNK_MEMBER_PARITY_STATUS_INTRr, NULL, 4334 TRUNK_MEMBER_PARITY_STATUS_NACKr, NULL }, 4335 4336 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 4337 PHB2_COS_MAP_PAR_ERRf, 4338 PHB2_COS_MAP_PAR_ERRf, 4339 PHB2_COS_MAPm, NULL, 4340 INVALIDr, 4341 PHB2_COS_MAP_PARITY_CONTROLr, PARITY_ENf, 4342 PHB2_COS_MAP_PARITY_STATUS_INTRr, NULL, 4343 PHB2_COS_MAP_PARITY_STATUS_NACKr, NULL }, 4344 4345 { _SOC_PARITY_TYPE_NONE } /* table terminator */ 4346 }; 4347 4348 STATIC _soc_katana2_parity_info_t _soc_katana2_ip3_2_parity_info[] = { 4349 4350 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 4351 EMIRROR_CONTROL_PAR_ERRf, 4352 EMIRROR_CONTROL_PAR_ERRf, 4353 EMIRROR_CONTROLm, NULL, 4354 INVALIDr, 4355 EMIRROR_CONTROL_PARITY_CONTROLr, PARITY_ENf, 4356 EMIRROR_CONTROL_PARITY_STATUS_INTRr, NULL, 4357 EMIRROR_CONTROL_PARITY_STATUS_NACKr, NULL }, 4358 4359 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 4360 EMIRROR_CONTROL1_PAR_ERRf, 4361 EMIRROR_CONTROL1_PAR_ERRf, 4362 EMIRROR_CONTROL1m, NULL, 4363 INVALIDr, 4364 EMIRROR_CONTROL1_PARITY_CONTROLr, PARITY_ENf, 4365 EMIRROR_CONTROL1_PARITY_STATUS_INTRr, NULL, 4366 EMIRROR_CONTROL1_PARITY_STATUS_NACKr, NULL }, 4367 4368 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 4369 EMIRROR_CONTROL2_PAR_ERRf, 4370 EMIRROR_CONTROL2_PAR_ERRf, 4371 EMIRROR_CONTROL2m, NULL, 4372 INVALIDr, 4373 EMIRROR_CONTROL2_PARITY_CONTROLr, PARITY_ENf, 4374 EMIRROR_CONTROL2_PARITY_STATUS_INTRr, NULL, 4375 EMIRROR_CONTROL2_PARITY_STATUS_NACKr, NULL }, 4376 4377 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 4378 EMIRROR_CONTROL3_PAR_ERRf, 4379 EMIRROR_CONTROL3_PAR_ERRf, 4380 EMIRROR_CONTROL3m, NULL, 4381 INVALIDr, 4382 EMIRROR_CONTROL3_PARITY_CONTROLr, PARITY_ENf, 4383 EMIRROR_CONTROL3_PARITY_STATUS_INTRr, NULL, 4384 EMIRROR_CONTROL3_PARITY_STATUS_NACKr, NULL }, 4385 4386 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 4387 SW2_EOP_BUFFER_A_PAR_ERRf, 4388 SW2_EOP_BUFFER_A_PAR_ERRf, 4389 INVALIDm, "SW2_EOP_BUFFER_A", 4390 INVALIDr, 4391 SW2_EOP_BUFFER_A_PARITY_CONTROLr, PARITY_ENf, 4392 SW2_EOP_BUFFER_A_PARITY_STATUS_INTRr, NULL, 4393 INVALIDr, NULL }, 4394 4395 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 4396 SW2_EOP_BUFFER_B_PAR_ERRf, 4397 SW2_EOP_BUFFER_B_PAR_ERRf, 4398 INVALIDm, "SW2_EOP_BUFFER_B", 4399 INVALIDr, 4400 SW2_EOP_BUFFER_B_PARITY_CONTROLr, PARITY_ENf, 4401 SW2_EOP_BUFFER_B_PARITY_STATUS_INTRr, NULL, 4402 INVALIDr, NULL }, 4403 4404 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 4405 OAM_LM_COUNTERS_0_PAR_ERRf, 4406 OAM_LM_COUNTERS_0_PAR_ERRf, 4407 OAM_LM_COUNTERS_0m, "OAM_LM_COUNTERS_1", 4408 INVALIDr, 4409 OAM_LM_COUNTERS_0_PARITY_CONTROLr, PARITY_ENf, 4410 OAM_LM_COUNTERS_0_PARITY_STATUS_INTRr, NULL, 4411 OAM_LM_COUNTERS_0_PARITY_STATUS_NACKr, NULL }, 4412 4413 { _SOC_PARITY_TYPE_COUNTER, NULL, 0, 4414 IP_COUNTERS_PAR_ERRf, 4415 IP_COUNTERS_PAR_ERRf, 4416 INVALIDm, "Ingress Pipeline Counter", 4417 INVALIDr, 4418 IP_COUNTERS_PARITY_CONTROLr, PARITY_ENf, 4419 IP_COUNTERS_PARITY_STATUS_INTRr, NULL, 4420 IP_COUNTERS_PARITY_STATUS_NACKr, NULL }, 4421 4422 { _SOC_PARITY_TYPE_COUNTER, NULL, 0, 4423 RDBGC_MEM_INST0_PAR_ERRf, 4424 RDBGC_MEM_INST0_PAR_ERRf, 4425 INVALIDm, "Ingress Pipeline Counter", 4426 INVALIDr, 4427 RDBGC_MEM_INST0_PARITY_CONTROLr, PARITY_ENf, 4428 RDBGC_MEM_INST0_PARITY_STATUS_INTRr, NULL, 4429 RDBGC_MEM_INST0_PARITY_STATUS_NACKr, NULL }, 4430 4431 { _SOC_PARITY_TYPE_COUNTER, NULL, 0, 4432 RDBGC_MEM_INST1_PAR_ERRf, 4433 RDBGC_MEM_INST1_PAR_ERRf, 4434 INVALIDm, "RX Debug Counter", 4435 INVALIDr, 4436 RDBGC_MEM_INST1_PARITY_CONTROLr, PARITY_ENf, 4437 RDBGC_MEM_INST1_PARITY_STATUS_INTRr, NULL, 4438 RDBGC_MEM_INST1_PARITY_STATUS_NACKr, NULL }, 4439 4440 { _SOC_PARITY_TYPE_COUNTER, NULL, 0, 4441 RDBGC_MEM_INST2_PAR_ERRf, 4442 RDBGC_MEM_INST2_PAR_ERRf, 4443 INVALIDm, "RX Debug Counter", 4444 INVALIDr, 4445 RDBGC_MEM_INST2_PARITY_CONTROLr, PARITY_ENf, 4446 RDBGC_MEM_INST2_PARITY_STATUS_INTRr, NULL, 4447 RDBGC_MEM_INST2_PARITY_STATUS_NACKr, NULL }, 4448 4449 { _SOC_PARITY_TYPE_COUNTER, NULL, 0, 4450 HG_COUNTERS_PAR_ERRf, 4451 HG_COUNTERS_PAR_ERRf, 4452 INVALIDm, "Ingress Pipeline HG Counter", 4453 INVALIDr, 4454 HG_COUNTERS_PARITY_CONTROLr, PARITY_ENf, 4455 HG_COUNTERS_PARITY_STATUS_INTRr, NULL, 4456 HG_COUNTERS_PARITY_STATUS_NACKr, NULL }, 4457 4458 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 4459 NIV_ERROR_DROP_PAR_ERRf, 4460 NIV_ERROR_DROP_PAR_ERRf, 4461 INVALIDm, "ING_NIV_RX_FRAMES_ERROR_DROP", 4462 ING_NIV_RX_FRAMES_ERROR_DROPr, 4463 NIV_ERROR_DROP_PARITY_CONTROLr, PARITY_ENf, 4464 NIV_ERROR_DROP_PARITY_STATUS_INTRr, NULL, 4465 NIV_ERROR_DROP_PARITY_STATUS_NACKr, NULL }, 4466 4467 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 4468 NIV_FORWARDING_DROP_PAR_ERRf, 4469 NIV_FORWARDING_DROP_PAR_ERRf, 4470 INVALIDm, "ING_NIV_RX_FRAMES_FORWARDING_DROP", 4471 ING_NIV_RX_FRAMES_FORWARDING_DROPr, 4472 NIV_FORWARDING_DROP_PARITY_CONTROLr, PARITY_ENf, 4473 NIV_FORWARDING_DROP_PARITY_STATUS_INTRr, NULL, 4474 NIV_FORWARDING_DROP_PARITY_STATUS_NACKr, NULL }, 4475 4476 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 4477 NIV_VLAN_TAGGED_PAR_ERRf, 4478 NIV_VLAN_TAGGED_PAR_ERRf, 4479 INVALIDm, "ING_NIV_RX_FRAMES_VLAN_TAGGED", 4480 ING_NIV_RX_FRAMES_VLAN_TAGGEDr, 4481 NIV_VLAN_TAGGED_PARITY_CONTROLr, PARITY_ENf, 4482 NIV_VLAN_TAGGED_PARITY_STATUS_INTRr, NULL, 4483 NIV_VLAN_TAGGED_PARITY_STATUS_NACKr, NULL }, 4484 4485 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 4486 TRILL_RX_PKTS_PAR_ERRf, 4487 TRILL_RX_PKTS_PAR_ERRf, 4488 INVALIDm, "ING_TRILL_RX_PKTS", 4489 ING_TRILL_RX_PKTSr, 4490 TRILL_RX_PKTS_PARITY_CONTROLr, PARITY_ENf, 4491 TRILL_RX_PKTS_PARITY_STATUS_INTRr, NULL, 4492 TRILL_RX_PKTS_PARITY_STATUS_NACKr, NULL }, 4493 4494 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 4495 TRILL_RX_ACCESS_PORT_TRILL_PKTS_DISCARDED_PAR_ERRf, 4496 TRILL_RX_ACCESS_PORT_TRILL_PKTS_DISCARDED_PAR_ERRf, 4497 INVALIDm, "ING_TRILL_RX_ACCESS_PORT_TRILL_PKTS_DISCARDED", 4498 ING_TRILL_RX_ACCESS_PORT_TRILL_PKTS_DISCARDEDr, 4499 TRILL_RX_ACCESS_PORT_TRILL_PKTS_DISCARDED_PARITY_CONTROLr, PARITY_ENf, 4500 TRILL_RX_ACCESS_PORT_TRILL_PKTS_DISCARDED_PARITY_STATUS_INTRr, NULL, 4501 TRILL_RX_ACCESS_PORT_TRILL_PKTS_DISCARDED_PARITY_STATUS_NACKr, NULL }, 4502 4503 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 4504 TRILL_RX_NETWORK_PORT_NON_TRILL_PKTS_DISCARDED_PAR_ERRf, 4505 TRILL_RX_NETWORK_PORT_NON_TRILL_PKTS_DISCARDED_PAR_ERRf, 4506 INVALIDm, "ING_TRILL_RX_NETWORK_PORT_NON_TRILL_PKTS_DISCARDED", 4507 ING_TRILL_RX_NETWORK_PORT_NON_TRILL_PKTS_DISCARDEDr, 4508 TRILL_RX_NETWORK_PORT_NON_TRILL_PKTS_DISCARDED_PARITY_CONTROLr, PARITY_ENf, 4509 TRILL_RX_NETWORK_PORT_NON_TRILL_PKTS_DISCARDED_PARITY_STATUS_INTRr, NULL, 4510 TRILL_RX_NETWORK_PORT_NON_TRILL_PKTS_DISCARDED_PARITY_STATUS_NACKr, NULL }, 4511 4512 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 4513 CPB_PAR_ERRf, 4514 CPB_PAR_ERRf, 4515 INVALIDm, "CPB", 4516 INVALIDr, 4517 CPB_PARITY_CONTROLr, PARITY_ENf, 4518 CPB_PARITY_STATUS_INTRr, NULL, 4519 INVALIDr, NULL }, 4520 4521 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 4522 ING_QUEUE_MAP_PAR_ERRf, 4523 ING_QUEUE_MAP_PAR_ERRf, 4524 ING_QUEUE_MAPm, "ING_QUEUE_MAP", 4525 INVALIDr, 4526 ING_QUEUE_MAP_PARITY_CONTROLr, PARITY_ENf, 4527 ING_QUEUE_MAP_PARITY_STATUS_INTRr, NULL, 4528 ING_QUEUE_MAP_PARITY_STATUS_NACKr, NULL }, 4529 4530 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 4531 OAM_LM_COUNTERS_1_PAR_ERRf, 4532 OAM_LM_COUNTERS_1_PAR_ERRf, 4533 OAM_LM_COUNTERS_1m, "OAM_LM_COUNTERS_1", 4534 INVALIDr, 4535 OAM_LM_COUNTERS_1_PARITY_CONTROLr, PARITY_ENf, 4536 OAM_LM_COUNTERS_1_PARITY_STATUS_INTRr, NULL, 4537 OAM_LM_COUNTERS_1_PARITY_STATUS_NACKr, NULL }, 4538 4539 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 4540 SW2_EOP_BUFFER_C_PAR_ERRf, 4541 SW2_EOP_BUFFER_C_PAR_ERRf, 4542 INVALIDm, "SW2_EOP_BUFFER_C", 4543 INVALIDr, 4544 SW2_EOP_BUFFER_C_PARITY_CONTROLr, PARITY_ENf, 4545 SW2_EOP_BUFFER_C_PARITY_STATUS_INTRr, NULL, 4546 INVALIDr, NULL }, 4547 4548 { _SOC_PARITY_TYPE_NONE } /* table terminator */ 4549 }; 4550 4551 STATIC const 4552 _soc_katana2_parity_route_block_t _soc_katana2_parity_route_blocks[] = { 4553 { 0x00000001, /* MMU_TO_CMIC_MEMFAIL_INTR */ 4554 SOC_BLK_MMU, MMU_INTR_MASKr, MMU_INTRr, 4555 NULL, 0}, 4556 4557 { 0x00000002, /* EP1_TO_CMIC_PERR_INTR */ 4558 SOC_BLK_EPIPE, EGR_INTR0_ENABLEr, EGR_INTR0_STATUSr, 4559 _soc_katana2_ep0_parity_info, 0}, 4560 4561 { 0x00000004, /* EP2_TO_CMIC_PERR_INTR */ 4562 SOC_BLK_EPIPE, EGR_INTR1_ENABLEr, EGR_INTR1_STATUSr, 4563 _soc_katana2_ep1_parity_info, 0}, 4564 4565 { 0x00000004, /* EP2_TO_CMIC_PERR_INTR */ 4566 SOC_BLK_EPIPE, EGR_INTR2_ENABLEr, EGR_INTR2_STATUSr, 4567 _soc_katana2_ep2_parity_info, 0}, 4568 4569 { 0x00000008, /* IP0_TO_CMIC_PERR_INTR */ 4570 SOC_BLK_IPIPE, IP0_INTR_ENABLEr, IP0_INTR_STATUSr, 4571 _soc_katana2_ip0_parity_info, 0}, 4572 4573 { 0x00000010, /* IP1_TO_CMIC_PERR_INTR */ 4574 SOC_BLK_IPIPE, IP1_INTR_ENABLEr, IP1_INTR_STATUSr, 4575 _soc_katana2_ip1_parity_info, 0}, 4576 4577 { 0x00000010, /* IP1_TO_CMIC_PERR_INTR */ 4578 SOC_BLK_IPIPE, IP1_INTR_ENABLE_1r, IP1_INTR_STATUS_1r, 4579 _soc_katana2_ip1_1_parity_info, 0}, 4580 4581 { 0x00000020, /* IP2_TO_CMIC_PERR_INTR */ 4582 SOC_BLK_IPIPE, IP2_INTR_ENABLEr, IP2_INTR_STATUSr, 4583 _soc_katana2_ip2_parity_info, 0}, 4584 4585 /* MXQ0_TO_CMIC_PERR_INTR */ 4586 { 0x00000080, 4587 SOC_BLK_MXQPORT, XPORT_INTR_ENABLEr, XPORT_INTR_STATUSr, 4588 _soc_katana2_xport_parity_info, 0}, 4589 4590 /* MXQ1_TO_CMIC_PERR_INTR */ 4591 { 0x00000100, 4592 SOC_BLK_MXQPORT, XPORT_INTR_ENABLEr, XPORT_INTR_STATUSr, 4593 _soc_katana2_xport_parity_info, 1}, 4594 4595 /* MXQ2_TO_CMIC_PERR_INTR */ 4596 { 0x00000200, 4597 SOC_BLK_MXQPORT, XPORT_INTR_ENABLEr, XPORT_INTR_STATUSr, 4598 _soc_katana2_xport_parity_info, 2}, 4599 4600 /* MXQ3_TO_CMIC_PERR_INTR */ 4601 { 0x00000400, 4602 SOC_BLK_MXQPORT, XPORT_INTR_ENABLEr, XPORT_INTR_STATUSr, 4603 _soc_katana2_xport_parity_info, 3}, 4604 4605 { 0x00000800, 4606 SOC_BLK_MXQPORT, XPORT_INTR_ENABLEr, XPORT_INTR_STATUSr, 4607 _soc_katana2_xport_parity_info, 4}, 4608 4609 { 0x00001000, 4610 SOC_BLK_MXQPORT, XPORT_INTR_ENABLEr, XPORT_INTR_STATUSr, 4611 _soc_katana2_xport_parity_info, 5}, 4612 4613 { 0x00002000, 4614 SOC_BLK_MXQPORT, XPORT_INTR_ENABLEr, XPORT_INTR_STATUSr, 4615 _soc_katana2_xport_parity_info, 6}, 4616 4617 { 0x00004000, 4618 SOC_BLK_MXQPORT, XPORT_INTR_ENABLEr, XPORT_INTR_STATUSr, 4619 _soc_katana2_xport_parity_info, 7}, 4620 4621 { 0x00008000, 4622 SOC_BLK_MXQPORT, XPORT_INTR_ENABLEr, XPORT_INTR_STATUSr, 4623 _soc_katana2_xport_parity_info, 8}, 4624 4625 { 0x00010000, 4626 SOC_BLK_MXQPORT, XPORT_INTR_ENABLEr, XPORT_INTR_STATUSr, 4627 _soc_katana2_xport_parity_info, 9}, 4628 4629 { 0x00020000, 4630 SOC_BLK_MXQPORT, XPORT_INTR_ENABLEr, XPORT_INTR_STATUSr, 4631 _soc_katana2_xport_parity_info, 10}, 4632 4633 { 0x00040000, 4634 SOC_BLK_RXLP, RXLP_ECC_INTERRUPT_ENABLEr, RXLP_ECC_INTERRUPT_STATUSr, 4635 _soc_katana2_rxlp_parity_info, 0}, 4636 4637 { 0x00080000, 4638 SOC_BLK_RXLP, RXLP_ECC_INTERRUPT_ENABLEr, RXLP_ECC_INTERRUPT_STATUSr, 4639 _soc_katana2_rxlp_parity_info, 1}, 4640 4641 { 0x00100000, 4642 SOC_BLK_TXLP, TXLP_INTR_ENABLEr, TXLP_INTR_STATUSr, 4643 _soc_katana2_txlp_parity_info, 0}, 4644 4645 { 0x00200000, 4646 SOC_BLK_TXLP, TXLP_INTR_ENABLEr, TXLP_INTR_STATUSr, 4647 _soc_katana2_txlp_parity_info, 1}, 4648 4649 /* IP3_TO_CMIC_PERR_INTR */ 4650 { 0x00400000, 4651 SOC_BLK_IPIPE, IP3_INTR_ENABLEr, IP3_INTR_STATUSr, 4652 _soc_katana2_ip3_parity_info, 0}, 4653 4654 /* IP3_TO_CMIC_PERR_INTR */ 4655 { 0x00400000, 4656 SOC_BLK_IPIPE, IP3_INTR_ENABLE_1r, IP3_INTR_STATUS_1r, 4657 _soc_katana2_ip3_1_parity_info, 0}, 4658 4659 /* IP3_TO_CMIC_PERR_INTR */ 4660 { 0x00400000, 4661 SOC_BLK_IPIPE, IP3_INTR_ENABLE_2r, IP3_INTR_STATUS_2r, 4662 _soc_katana2_ip3_2_parity_info, 0}, 4663 /* 0x00000800 PULL_DOWN */ 4664 4665 { 0 } /* table terminator */ 4666 }; 4667 4668 4669 #define _SOC_KT2_SER_REG 1 4670 #define _SOC_KT2_SER_MEM 0 4671 #define KT2_OAM_INTR_MASK 0xFF 4672 #define KT2_OAM_CMIC_INTR_MASK 0x00000010 4673 #define SB2_OAM_CMIC_INTR_MASK 0x00001000 4674 #define KT2_RXLP_INTR_MASK 0x7FFF 4675 4676 typedef union _kt2_ser_nack_reg_mem_u { 4677 soc_reg_t reg; 4678 soc_mem_t mem; 4679 } _kt2_ser_nack_reg_mem_t; 4680 4681 static int _stat_error_fixed[SOC_MAX_NUM_DEVICES]; 4682 4683 STATIC int 4684 _soc_katana2_parity_enable_info(int unit, soc_port_t port, 4685 soc_reg_t group_reg, 4686 uint32 *group_rval, 4687 const _soc_katana2_parity_info_t *info_list, 4688 int enable); 4689 4690 void soc_kt2_oam_interrupt_process(int unit); 4691 4692 int 4693 _bcm_kt2_is_pp_port_linkphy_subtag(int unit, int pp_port) 4694 { 4695 int pp_port_index_min = SOC_INFO(unit).pp_port_index_min; 4696 int pp_port_index_max = SOC_INFO(unit).pp_port_index_max; 4697 if (!(soc_feature(unit, soc_feature_linkphy_coe) || 4698 soc_feature(unit, soc_feature_subtag_coe))) { 4699 return FALSE; 4700 } 4701 #if defined BCM_METROLITE_SUPPORT 4702 if (soc_feature(unit, soc_feature_discontinuous_pp_port)) { 4703 if (_SOC_IS_PP_PORT_LINKPHY_SUBTAG(unit, pp_port)) { 4704 return TRUE; 4705 } 4706 } else 4707 #endif 4708 { 4709 if ((pp_port >= pp_port_index_min) && 4710 (pp_port <= pp_port_index_max)) { 4711 return TRUE; 4712 } 4713 } 4714 return FALSE; 4715 } 4716 4717 STATIC 4718 int _soc_katana2_get_max_stream_ids(int unit) 4719 { 4720 int linkphy_pbmp_count = 0; 4721 int num_of_steams = 2; 4722 int num_subport = 0; 4723 soc_pbmp_t pbmp_linkphy; 4724 pbmp_linkphy = soc_property_get_pbmp(unit, spn_PBMP_LINKPHY, 0); 4725 SOC_PBMP_COUNT(pbmp_linkphy, linkphy_pbmp_count); 4726 num_subport = 4727 soc_property_port_get(unit, 0, spn_NUM_SUBPORTS, 0); 4728 4729 return (linkphy_pbmp_count * num_of_steams * num_subport); 4730 } 4731 4732 STATIC 4733 int _soc_katana2_ci_block_get(int unit, 4734 _soc_katana2_mmu_subblock_type_t sub_block, 4735 soc_block_t* block) 4736 { 4737 switch(sub_block){ 4738 case _SOC_KT2_MMU_SUBBLOCK_CI5: 4739 *block = CI5_BLOCK(unit); 4740 break; 4741 4742 case _SOC_KT2_MMU_SUBBLOCK_CI4: 4743 *block = CI4_BLOCK(unit); 4744 break; 4745 4746 case _SOC_KT2_MMU_SUBBLOCK_CI3: 4747 *block = CI3_BLOCK(unit); 4748 break; 4749 4750 case _SOC_KT2_MMU_SUBBLOCK_CI2: 4751 *block = CI2_BLOCK(unit); 4752 break; 4753 4754 case _SOC_KT2_MMU_SUBBLOCK_CI1: 4755 *block = CI1_BLOCK(unit); 4756 break; 4757 4758 case _SOC_KT2_MMU_SUBBLOCK_CI0: 4759 *block = CI0_BLOCK(unit); 4760 break; 4761 4762 default: 4763 break; 4764 } 4765 return SOC_E_NONE; 4766 } 4767 4768 STATIC 4769 void _soc_katana2_mem_parity_info(int unit, int block_idx, int pipe, 4770 soc_field_t field_enum, uint32 *minfo) 4771 { 4772 *minfo = (SOC_BLOCK2SCH(unit, block_idx) << SOC_ERROR_BLK_BP) 4773 | ((pipe & 0xff) << SOC_ERROR_PIPE_BP) 4774 | (field_enum & SOC_ERROR_FIELD_ENUM_MASK); 4775 } 4776 4777 STATIC 4778 int _soc_katana2_process_sb_mmu_leaf_parity_enable(int unit, 4779 soc_port_t port, 4780 soc_reg_t leaf_enable_reg, 4781 _soc_katana2_mmu_sub_block_leaf_info_t * leaf_info, 4782 int enable) 4783 { 4784 uint32 en_rval; 4785 int index; 4786 soc_field_t enable_field; 4787 _soc_katana2_mmu_sub_block_leaf_info_t * info; 4788 4789 /* leaf_info contains a list of leaf block, each leaf has a bit 4790 in leaf_enable_reg */ 4791 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, leaf_enable_reg, port, 0, 4792 &en_rval)); 4793 4794 for (index = 0; ; index++) { 4795 info = &leaf_info[index]; 4796 if(info->intr_bit == 0) { 4797 /* End of leaf table */ 4798 break; 4799 } 4800 enable_field = info->enable_field; 4801 4802 if (SOC_REG_FIELD_VALID(unit, leaf_enable_reg, enable_field)) { 4803 if (enable_field == FLUSH_COMPLETE_DISINTf) { 4804 continue; 4805 } 4806 /* set corresponding field for a leaf block */ 4807 soc_reg_field_set(unit, leaf_enable_reg, &en_rval, enable_field, 4808 enable ? 0 : 1); 4809 } 4810 } 4811 4812 /* write back enable register */ 4813 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, leaf_enable_reg, port, 0, en_rval)); 4814 return SOC_E_NONE; 4815 } 4816 4817 STATIC 4818 int _soc_katana2_process_sb_one_level_mmu_parity_enable(int unit, 4819 soc_reg_t mmu_en_reg, 4820 _soc_katana2_mmu_sub_block_one_level_t * sub_block_info, 4821 int enable) 4822 { 4823 uint32 en_rval; 4824 soc_block_t block = SOC_BLOCK_ANY; 4825 soc_port_t port = REG_PORT_ANY; 4826 soc_reg_t leaf_enable_reg; 4827 _soc_katana2_mmu_subblock_type_t sub_block_type; 4828 _soc_katana2_mmu_sub_block_leaf_info_t * leaf_info; 4829 4830 if(sub_block_info->mmu_bit == 0) { 4831 /* reach the end of one level sub block table */ 4832 return SOC_E_NONE; 4833 } 4834 4835 sub_block_type = sub_block_info->mmu_sub_block; 4836 if ((sub_block_type == _SOC_KT2_MMU_SUBBLOCK_CI5)|| 4837 (sub_block_type == _SOC_KT2_MMU_SUBBLOCK_CI4)|| 4838 (sub_block_type == _SOC_KT2_MMU_SUBBLOCK_CI3)|| 4839 (sub_block_type == _SOC_KT2_MMU_SUBBLOCK_CI2)|| 4840 (sub_block_type == _SOC_KT2_MMU_SUBBLOCK_CI1)|| 4841 (sub_block_type == _SOC_KT2_MMU_SUBBLOCK_CI0)){ 4842 4843 if (soc_feature(unit, soc_feature_ddr3)){ 4844 _soc_katana2_ci_block_get (unit, sub_block_type, &block); 4845 port = SOC_BLOCK_PORT(unit, block); 4846 } else { 4847 return SOC_E_NONE; 4848 } 4849 } 4850 4851 leaf_info = sub_block_info->info; 4852 4853 /* enable for this sub block */ 4854 leaf_enable_reg = sub_block_info->leaf_enable_reg; 4855 SOC_IF_ERROR_RETURN 4856 (_soc_katana2_process_sb_mmu_leaf_parity_enable (unit, port, 4857 leaf_enable_reg, leaf_info, enable)); 4858 4859 /* set MMU_INTR_MASK */ 4860 SOC_IF_ERROR_RETURN 4861 (soc_reg32_get(unit, mmu_en_reg, REG_PORT_ANY, 0, &en_rval)); 4862 soc_reg_field_set(unit, mmu_en_reg, &en_rval, 4863 sub_block_info->mmu_enable_field, enable ? 0 : 1); 4864 SOC_IF_ERROR_RETURN 4865 (soc_reg32_set(unit, mmu_en_reg, REG_PORT_ANY, 0, en_rval)); 4866 4867 return SOC_E_NONE; 4868 } 4869 4870 STATIC 4871 int _soc_katana2_process_sb_two_level_mmu_parity_enable(int unit, 4872 soc_reg_t mmu_en_reg, 4873 _soc_katana2_mmu_sub_block_two_level_t * sub_block_info, 4874 int enable) 4875 { 4876 uint32 en_rval; 4877 soc_reg_t internal_enable_reg; 4878 soc_reg_t leaf_enable_reg; 4879 soc_field_t internal_enable_field; 4880 int internal_index; 4881 soc_port_t port = REG_PORT_ANY; 4882 _soc_katana2_mmu_sub_block_internal_info_t * internal_info; 4883 _soc_katana2_mmu_sub_block_leaf_info_t * leaf_info; 4884 4885 if(sub_block_info->mmu_bit == 0) { 4886 /* reach the end of two level sub block table */ 4887 return SOC_E_NONE; 4888 } 4889 4890 internal_info = sub_block_info->info; 4891 internal_enable_reg = sub_block_info->internal_enable_reg; 4892 4893 /* get mask register of level 1 sub block */ 4894 if (internal_enable_reg != 0) { 4895 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, internal_enable_reg, 4896 REG_PORT_ANY, 0, &en_rval)); 4897 } 4898 4899 for (internal_index = 0; ; internal_index++) { 4900 internal_info = &sub_block_info->info[internal_index]; 4901 if(internal_info->intr_bit == 0) { 4902 /* End of internal_info table */ 4903 break; 4904 } 4905 4906 internal_enable_field = internal_info->internal_enable_field; 4907 4908 if ((internal_enable_reg != 0) && 4909 (SOC_REG_FIELD_VALID(unit, internal_enable_reg, 4910 internal_enable_field))) { 4911 soc_reg_field_set(unit, internal_enable_reg, &en_rval, 4912 internal_enable_field, enable ? 0 : 1); 4913 } 4914 4915 /* get mask register of level 2 sub mask */ 4916 leaf_enable_reg = internal_info->leaf_enable_reg; 4917 leaf_info = internal_info->info; 4918 4919 SOC_IF_ERROR_RETURN 4920 (_soc_katana2_process_sb_mmu_leaf_parity_enable (unit, port, 4921 leaf_enable_reg, leaf_info, enable)); 4922 } 4923 4924 /* write back mask register of level 1 sub block */ 4925 if (internal_enable_reg != 0) { 4926 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, internal_enable_reg, 4927 REG_PORT_ANY, 0, en_rval)); 4928 } 4929 4930 /* set MMU_INTR_MASK */ 4931 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, mmu_en_reg, REG_PORT_ANY, 0, 4932 &en_rval)); 4933 soc_reg_field_set(unit, mmu_en_reg, &en_rval, 4934 sub_block_info->mmu_enable_field, enable ? 0 : 1); 4935 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, mmu_en_reg, REG_PORT_ANY, 0, 4936 en_rval)); 4937 4938 return SOC_E_NONE; 4939 } 4940 4941 STATIC int 4942 _soc_katana2_parity_enable_mmu(int unit, soc_reg_t mmu_en_reg, int enable) 4943 { 4944 int index; 4945 uint32 sub_block_num; 4946 _soc_katana2_mmu_sub_block_one_level_t * sub_block; 4947 _soc_katana2_mmu_sub_block_two_level_t * two_level_sub_block; 4948 4949 sub_block_num = SOC_DDR3_NUM_MEMORIES(unit); 4950 4951 for (index = 0; index < sub_block_num; index++) { 4952 sub_block = &_soc_katana2_mmu_sub_blocks_type_1[index]; 4953 if ((sub_block->mmu_sub_block == _SOC_KT2_MMU_SUBBLOCK_CI5) || 4954 (sub_block->mmu_sub_block == _SOC_KT2_MMU_SUBBLOCK_CI4) || 4955 (sub_block->mmu_sub_block == _SOC_KT2_MMU_SUBBLOCK_CI3) || 4956 (sub_block->mmu_sub_block == _SOC_KT2_MMU_SUBBLOCK_CI2) || 4957 (sub_block->mmu_sub_block == _SOC_KT2_MMU_SUBBLOCK_CI1) || 4958 (sub_block->mmu_sub_block == _SOC_KT2_MMU_SUBBLOCK_CI0)) { 4959 if (!soc_feature(unit, soc_feature_ddr3)) { 4960 continue; 4961 } 4962 } 4963 SOC_IF_ERROR_RETURN 4964 (_soc_katana2_process_sb_one_level_mmu_parity_enable(unit, 4965 mmu_en_reg, sub_block, enable)); 4966 } 4967 4968 sub_block_num = COUNTOF(_soc_katana2_mmu_sub_blocks_type_2); 4969 4970 for (index = 0; index < sub_block_num; index++) { 4971 two_level_sub_block = &_soc_katana2_mmu_sub_blocks_type_2[index]; 4972 if (two_level_sub_block->mmu_sub_block == _SOC_KT2_MMU_SUBBLOCK_EMC) { 4973 if (!soc_feature(unit, soc_feature_ddr3)) { 4974 continue; 4975 } 4976 } 4977 SOC_IF_ERROR_RETURN 4978 (_soc_katana2_process_sb_two_level_mmu_parity_enable(unit, 4979 mmu_en_reg, two_level_sub_block, enable)); 4980 } 4981 return SOC_E_NONE; 4982 } 4983 4984 4985 STATIC int 4986 _soc_katana2_mmu_is_parity_interrupt (int unit, soc_reg_t mmu_status_reg, soc_field_t mmu_status_field) 4987 { 4988 int retVal = 0; 4989 if ( (!SOC_REG_IS_VALID(unit, mmu_status_reg) || 4990 !soc_reg_field_valid(unit, mmu_status_reg, mmu_status_field))) { 4991 return retVal; 4992 } 4993 4994 switch(mmu_status_reg) 4995 { 4996 case RDE_SER_STATUSr: 4997 if ((ECC_1B_BITMAPf == mmu_status_field) || (ECC_2B_BITMAPf == mmu_status_field)) { 4998 retVal = 1; 4999 } 5000 break; 5001 case CI_ERRORr: 5002 if ((WFIFO_CTL_CORRECTED_ERRORf == mmu_status_field) || 5003 (WFIFO_CTL_UNCORRECTED_ERRORf == mmu_status_field) || 5004 (RFIFO_CTL_CORRECTED_ERRORf == mmu_status_field) || 5005 (RFIFO_CTL_UNCORRECTED_ERRORf == mmu_status_field)) { 5006 retVal = 1; 5007 } 5008 break; 5009 case WRED_PARITY_ERROR_BITMAPr: 5010 if (UPDATE_INTRPT_STATUSf != mmu_status_field) { 5011 retVal = 1; 5012 } 5013 break; 5014 case CTR_ERRORr: 5015 if ((CTR_RQE_FIFO_OVERFLOW_ERRORf == mmu_status_field) || 5016 (CTR_ENQ_WRAP_ERRORf == mmu_status_field) || 5017 (CTR_DEQ_WRAP_ERRORf == mmu_status_field)) { 5018 retVal = 0; 5019 } else { 5020 retVal = 1; 5021 } 5022 break; 5023 case CCP_ERRORr: 5024 if ((CCPI_RQE_UPD_NEGATIVEf != mmu_status_field) && 5025 (CCPE_RQE_UPD_NEGATIVEf != mmu_status_field)) { 5026 retVal = 1; 5027 } 5028 break; 5029 case CFAPI_ECC_ERRORr: 5030 if (DUPLICATE_PTRf != mmu_status_field) { 5031 retVal = 1; 5032 } 5033 break; 5034 case CFAPE_ECC_ERRORr: 5035 if (DUPLICATE_PTRf != mmu_status_field) { 5036 retVal = 1; 5037 } 5038 break; 5039 case RQE_SER_STATUSr: 5040 if ((ECC_1B_BITMAPf == mmu_status_field) || (ECC_2B_BITMAPf == mmu_status_field)) { 5041 retVal = 1; 5042 } 5043 break; 5044 case EMC_ERROR_3r: 5045 if ((EMC_CI0_FIXED_PATTERN_ERRORf == mmu_status_field) || 5046 (EMC_CI1_FIXED_PATTERN_ERRORf == mmu_status_field) || 5047 (EMC_CI2_FIXED_PATTERN_ERRORf == mmu_status_field) || 5048 (EMC_CI3_FIXED_PATTERN_ERRORf == mmu_status_field) || 5049 (EMC_CI4_FIXED_PATTERN_ERRORf == mmu_status_field) || 5050 (EMC_CI5_FIXED_PATTERN_ERRORf == mmu_status_field)) { 5051 retVal = 0; 5052 } else { 5053 retVal = 1; 5054 } 5055 break; 5056 case QSTRUCT_FAP_MEM_ERRORr: 5057 if ((FAP_LOADING_ERRORf == mmu_status_field) || 5058 (FAP0_DUPLICATE_PTR_ERRORf == mmu_status_field) || 5059 (FAP1_DUPLICATE_PTR_ERRORf == mmu_status_field) || 5060 (FAP2_DUPLICATE_PTR_ERRORf == mmu_status_field) || 5061 (FAP3_DUPLICATE_PTR_ERRORf == mmu_status_field)) { 5062 retVal = 0; 5063 } else { 5064 retVal = 1; 5065 } 5066 break; 5067 case MMU_ITE_CFG_ECC_ERROR_0r: 5068 case MMU_ENQ_CFG_ECC_ERROR_0r: 5069 case MMU_ENQ_FAP_ECC_ERROR_0r: 5070 case THDO_PARITY_ERROR_STATUS1r: 5071 case THDO_PARITY_ERROR_STATUS2r: 5072 case LLS_PORT_ECC_ERRORr: 5073 case LLS_L0_ECC_ERROR1r: 5074 case LLS_L1_ECC_ERROR1r: 5075 case LLS_L2_ECC_ERROR1r: 5076 case LLS_MISC_ECC_ERROR1r: 5077 case EMC_ERROR_1r: 5078 case EMC_ERROR_2r: 5079 case DEQ_ERROR_3r: 5080 case DEQ_ERROR_4r: 5081 case QSTRUCT_QENTRY_UPPER_ERRORr: 5082 case QSTRUCT_QENTRY_LOWER_ERRORr: 5083 case QSTRUCT_QBLOCK_NEXT_ERRORr: 5084 case TOQ_ERROR1r: 5085 case MMU_IPCTR_ECC_ERROR_0r: 5086 case MMU_ADM_ECC_ERROR_0r: 5087 retVal = 1; 5088 break; 5089 case MMU_E2EFC_ERROR_0r: 5090 case MMU_THDI_INTRr: 5091 case MMU_ENQ_ERROR_0r: 5092 case AGING_ERROR_INTr: 5093 case AGING_ERROR_EXTr: 5094 case LLS_ERRORr: 5095 case LLS_ERROR2r: 5096 case LLS_ERROR_UPD2r: 5097 case RQE_EXTQ_REPLICATION_COUNTr: 5098 case EMC_ERROR_0r: 5099 case DEQ_ERROR_0r: 5100 case DEQ_ERROR_1r: 5101 case DEQ_ERROR_2r: 5102 case TOQ_ERROR2r: 5103 retVal = 0; 5104 break; 5105 default: 5106 break; 5107 } 5108 5109 return retVal; 5110 } 5111 5112 STATIC 5113 int _soc_katana2_process_sb_mmu_leaf_parity_error (int unit, 5114 _soc_katana2_mmu_subblock_type_t sub_block_type, 5115 soc_port_t port, 5116 soc_reg_t leaf_enable_reg, 5117 soc_reg_t leaf_status_reg, 5118 _soc_katana2_mmu_sub_block_leaf_info_t * leaf_info) 5119 { 5120 uint32 stat_rval, en_rval, minfo; 5121 uint32 intr_bit; 5122 int index = 0, block_idx; 5123 _soc_katana2_mmu_sub_block_leaf_info_t *info; 5124 char prefix_str[10]; 5125 char *reg_str; 5126 char *field_str; 5127 5128 sal_sprintf(prefix_str, "unit %d", unit); 5129 5130 /* A _soc_katana2_mmu_sub_block_leaf_info_t object corresponds to 5131 a list of leaf blocks share the common enable and status register. 5132 each memory has a bit in enable and status register. usually, the 5133 bit position is same, but for in some case, they are not equal. 5134 in this case, we need to do specical handling. */ 5135 SOC_IF_ERROR_RETURN 5136 (soc_reg32_get(unit, leaf_status_reg, port, 0, &stat_rval)); 5137 SOC_IF_ERROR_RETURN 5138 (soc_reg32_get(unit, leaf_enable_reg, port, 0, &en_rval)); 5139 5140 if (leaf_status_reg == RQE_EXTQ_REPLICATION_COUNTr) { 5141 stat_rval &= ((~en_rval) << 11); 5142 } else { 5143 stat_rval &= (~en_rval); 5144 } 5145 5146 if (stat_rval == 0) { 5147 /* How did this interrupt get asserted then??? */ 5148 return SOC_E_NONE; 5149 } 5150 SOC_BLOCK_ITER(unit, block_idx, SOC_BLK_MMU) { 5151 if (SOC_BLOCK_INFO(unit, block_idx).number == 0) { 5152 break; 5153 } 5154 } 5155 /* We really need handle the parity, because it trigger status register and we 5156 do not mask it. Go over all the memories in the list. 5157 a _soc_katana2_mmu_sub_block_leaf_info_t corresponds to a memory instance 5158 its intr_bit specify its bit position in status register */ 5159 for (index = 0; ; index++) { 5160 info = &leaf_info[index]; 5161 intr_bit = info->intr_bit; 5162 if(intr_bit == 0) { 5163 /* reach the end of leaf table */ 5164 return SOC_E_NONE; 5165 } 5166 5167 /* get a match */ 5168 if (stat_rval & intr_bit) { 5169 field_str = SOC_FIELD_NAME(unit, info->status_field); 5170 reg_str = SOC_REG_NAME(unit, leaf_status_reg); 5171 if(_soc_katana2_mmu_is_parity_interrupt(unit, leaf_status_reg, info->status_field)) { 5172 _soc_katana2_mem_parity_info(unit, block_idx, 0, 5173 info->status_field, &minfo); 5174 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 5175 SOC_SWITCH_EVENT_DATA_ERROR_UNCORRECTABLE, 5176 0, minfo); 5177 LOG_ERROR(BSL_LS_SOC_COMMON, 5178 (BSL_META_U(unit, 5179 "%s MMU subblock %x reg %s field %s(value = 0x%x) has MMU parity error\n"), 5180 prefix_str, sub_block_type, reg_str, 5181 field_str, stat_rval)); 5182 } else { 5183 LOG_ERROR(BSL_LS_SOC_COMMON, 5184 (BSL_META_U(unit, 5185 "%s MMU subblock %x reg %s field %s(value = 0x%x) has been set.\n"), 5186 prefix_str, sub_block_type, reg_str, 5187 field_str, stat_rval)); 5188 } 5189 /* clear the parity error bit */ 5190 SOC_IF_ERROR_RETURN 5191 (soc_reg32_set(unit, leaf_status_reg, port, 0, intr_bit)); 5192 } 5193 } 5194 return SOC_E_NONE; 5195 } 5196 5197 STATIC 5198 int _soc_katana2_process_sb_one_level_mmu_parity_error(int unit, 5199 _soc_katana2_mmu_sub_block_one_level_t * sub_block_info) 5200 { 5201 soc_reg_t leaf_enable_reg; 5202 soc_reg_t leaf_status_reg; 5203 _soc_katana2_mmu_subblock_type_t sub_block_type; 5204 soc_block_t block = SOC_BLOCK_ANY; 5205 soc_port_t port = REG_PORT_ANY; 5206 _soc_katana2_mmu_sub_block_leaf_info_t * leaf_info; 5207 5208 if(sub_block_info->mmu_bit == 0) { 5209 /* reach the end of one level sub block table */ 5210 return SOC_E_NONE; 5211 } 5212 sub_block_type = sub_block_info->mmu_sub_block; 5213 5214 if ((sub_block_type == _SOC_KT2_MMU_SUBBLOCK_CI5)|| 5215 (sub_block_type == _SOC_KT2_MMU_SUBBLOCK_CI4)|| 5216 (sub_block_type == _SOC_KT2_MMU_SUBBLOCK_CI3)|| 5217 (sub_block_type == _SOC_KT2_MMU_SUBBLOCK_CI2)|| 5218 (sub_block_type == _SOC_KT2_MMU_SUBBLOCK_CI1)|| 5219 (sub_block_type == _SOC_KT2_MMU_SUBBLOCK_CI0)){ 5220 5221 if (soc_feature(unit, soc_feature_ddr3)){ 5222 _soc_katana2_ci_block_get (unit, sub_block_type, &block); 5223 port = SOC_BLOCK_PORT(unit, block); 5224 } else { 5225 return SOC_E_NONE; 5226 } 5227 } 5228 5229 leaf_enable_reg = sub_block_info->leaf_enable_reg; 5230 leaf_status_reg = sub_block_info->leaf_status_reg; 5231 leaf_info = sub_block_info->info; 5232 5233 /* process this sub block */ 5234 SOC_IF_ERROR_RETURN 5235 (_soc_katana2_process_sb_mmu_leaf_parity_error (unit, sub_block_type, 5236 port, leaf_enable_reg, leaf_status_reg, leaf_info)); 5237 5238 return SOC_E_NONE; 5239 } 5240 5241 STATIC 5242 int _soc_katana2_process_sb_two_level_mmu_parity_error(int unit, 5243 _soc_katana2_mmu_sub_block_two_level_t * sub_block_info) 5244 { 5245 uint32 en_rval; 5246 uint32 status_rval; 5247 soc_reg_t internal_status_reg; 5248 soc_reg_t internal_enable_reg; 5249 int internal_index; 5250 soc_port_t port = REG_PORT_ANY; 5251 _soc_katana2_mmu_subblock_type_t sub_block_type; 5252 _soc_katana2_mmu_sub_block_internal_info_t * internal_info; 5253 5254 if(sub_block_info->mmu_bit == 0) { 5255 /* reach the end of two level sub block table */ 5256 return SOC_E_NONE; 5257 } 5258 sub_block_type = sub_block_info->mmu_sub_block; 5259 5260 /* get status register of level 1 sub block */ 5261 internal_status_reg = sub_block_info->internal_status_reg; 5262 SOC_IF_ERROR_RETURN 5263 (soc_reg32_get(unit, internal_status_reg, REG_PORT_ANY, 0, 5264 &status_rval)); 5265 /* get mask register of level 1 sub block */ 5266 internal_enable_reg = sub_block_info->internal_enable_reg; 5267 if (internal_enable_reg != 0) { 5268 SOC_IF_ERROR_RETURN 5269 (soc_reg32_get(unit, internal_enable_reg, REG_PORT_ANY, 0, 5270 &en_rval)); 5271 /* remove masked */ 5272 status_rval &= (~en_rval); 5273 } 5274 5275 if (status_rval == 0) { 5276 /* How did this interrupt get asserted then??? */ 5277 return SOC_E_NONE; 5278 } 5279 5280 for (internal_index = 0; ; internal_index++) { 5281 internal_info = &sub_block_info->info[internal_index]; 5282 5283 if(internal_info->intr_bit == 0) { 5284 break; 5285 } 5286 if (status_rval & internal_info->intr_bit){ 5287 /* process this sub block */ 5288 SOC_IF_ERROR_RETURN 5289 (_soc_katana2_process_sb_mmu_leaf_parity_error (unit, 5290 sub_block_type, port, internal_info->leaf_enable_reg, 5291 internal_info->leaf_status_reg, internal_info->info)); 5292 5293 /* clear the parity error bit */ 5294 SOC_IF_ERROR_RETURN 5295 (soc_reg32_set(unit, internal_status_reg, REG_PORT_ANY, 0, 5296 internal_info->intr_bit)); 5297 } 5298 } 5299 return SOC_E_NONE; 5300 } 5301 5302 STATIC int 5303 _soc_katana2_parity_process_mmu(int unit, soc_reg_t mmu_en_reg, 5304 soc_reg_t mmu_stat_reg, char *prefix_str) 5305 { 5306 uint32 en_rval, stat_rval, mmu_bit; 5307 int index; 5308 uint32 sub_block_num; 5309 _soc_katana2_mmu_sub_block_one_level_t * sub_block; 5310 _soc_katana2_mmu_sub_block_two_level_t * sub_block_2; 5311 5312 /* get MMU INTR and MASK */ 5313 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, mmu_en_reg, REG_PORT_ANY, 0, &en_rval)); 5314 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, mmu_stat_reg, REG_PORT_ANY, 0, &stat_rval)); 5315 5316 /* remove masked */ 5317 stat_rval &= (~en_rval); 5318 if (stat_rval == 0) { 5319 /* How did this interrupt get asserted then??? */ 5320 return SOC_E_NONE; 5321 } 5322 5323 sub_block_num = COUNTOF(_soc_katana2_mmu_sub_blocks_type_1); 5324 for (index = 0; index < sub_block_num; index++){ 5325 sub_block = &_soc_katana2_mmu_sub_blocks_type_1[index]; 5326 if(sub_block->mmu_bit == 0) { 5327 /* End of table */ 5328 break; 5329 } 5330 mmu_bit = sub_block->mmu_bit; 5331 5332 if ((sub_block->mmu_bit & (stat_rval)) == 0) { 5333 /* No interrupts in this sub-block */ 5334 continue; 5335 } 5336 5337 _soc_katana2_process_sb_one_level_mmu_parity_error(unit, sub_block); 5338 5339 /* clear the MMU parity error bit */ 5340 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, mmu_stat_reg, REG_PORT_ANY, 0, mmu_bit)); 5341 } 5342 5343 sub_block_num = COUNTOF(_soc_katana2_mmu_sub_blocks_type_2); 5344 for (index = 0; index < sub_block_num; index++) { 5345 sub_block_2 = &_soc_katana2_mmu_sub_blocks_type_2[index]; 5346 if(sub_block_2->mmu_bit == 0) { 5347 /* End of table */ 5348 break; 5349 } 5350 mmu_bit = sub_block_2->mmu_bit; 5351 5352 if ((mmu_bit & (stat_rval)) == 0) { 5353 /* No interrupts in this sub-block */ 5354 continue; 5355 } 5356 5357 _soc_katana2_process_sb_two_level_mmu_parity_error(unit, sub_block_2); 5358 /* clear the MMU parity error bit */ 5359 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, mmu_stat_reg, REG_PORT_ANY, 0, mmu_bit)); 5360 } 5361 return SOC_E_NONE; 5362 } 5363 5364 STATIC int 5365 _soc_katana2_parity_enable_info(int unit, soc_port_t port, 5366 soc_reg_t group_reg, 5367 uint32 *group_rval, 5368 const _soc_katana2_parity_info_t *info_list, 5369 int enable) 5370 { 5371 const _soc_katana2_parity_info_t *info; 5372 int info_index; 5373 soc_reg_t reg; 5374 uint32 rval; 5375 5376 /* Loop through each info entry in the list */ 5377 for (info_index = 0; ; info_index++) { 5378 info = &info_list[info_index]; 5379 if (info->type == _SOC_PARITY_TYPE_NONE) { 5380 /* End of table */ 5381 break; 5382 } 5383 5384 /* Enable the info entry in the group register */ 5385 soc_reg_field_set(unit, group_reg, group_rval, 5386 info->group_reg_enable_field, enable ? 1 : 0); 5387 5388 /* Handle different parity error reporting style */ 5389 switch (info->type) { 5390 case _SOC_PARITY_TYPE_PARITY: 5391 case _SOC_PARITY_TYPE_ECC: 5392 case _SOC_PARITY_TYPE_HASH: 5393 case _SOC_PARITY_TYPE_EDATABUF: 5394 case _SOC_PARITY_TYPE_COUNTER: 5395 reg = info->enable_reg; 5396 if (!SOC_REG_IS_VALID(unit, reg)) { 5397 continue; 5398 } 5399 5400 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, reg, port, 0, &rval)); 5401 soc_reg_field_set(unit, reg, &rval, info->enable_field, 5402 enable ? 1 : 0); 5403 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, reg, port, 0, rval)); 5404 break; 5405 case _SOC_PARITY_TYPE_GENERIC: 5406 default: 5407 break; 5408 } /* Handle different parity error reporting style */ 5409 } /* Loop through each info entry in the route block */ 5410 5411 return SOC_E_NONE; 5412 } 5413 5414 STATIC int 5415 _soc_katana2_parity_enable_all(int unit, int enable) 5416 { 5417 const _soc_katana2_parity_route_block_t *route_block; 5418 int route_block_index, block_idx; 5419 soc_port_t port; 5420 soc_reg_t route_block_en_reg; 5421 uint32 cmic_rval, route_block_rval; 5422 uint32 cmic_bit; 5423 uint32 rval; 5424 5425 port = REG_PORT_ANY; 5426 cmic_rval = 0; 5427 /* Loop through each place-and-route block entry */ 5428 for (route_block_index = 0; ; route_block_index++) { 5429 route_block = &_soc_katana2_parity_route_blocks[route_block_index]; 5430 cmic_bit = route_block->cmic_bit; 5431 if (cmic_bit == 0) { 5432 /* End of table */ 5433 break; 5434 } 5435 /* Enable the route block entry in the CMIC register */ 5436 if (enable) { 5437 cmic_rval |= cmic_bit; 5438 } 5439 5440 route_block_en_reg = route_block->enable_reg; 5441 5442 /* Get block and port for MXQ and RXLP and TXLP */ 5443 if ((route_block->blocktype == SOC_BLK_MXQPORT) || 5444 (route_block->blocktype == SOC_BLK_TXLP) || 5445 (route_block->blocktype == SOC_BLK_RXLP)) { 5446 SOC_BLOCK_ITER(unit, block_idx, route_block->blocktype) { 5447 if (SOC_BLOCK_INFO(unit, block_idx).number == route_block->id) { 5448 port = SOC_BLOCK_PORT(unit, block_idx); 5449 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, route_block_en_reg, 5450 port, 0, &route_block_rval)); 5451 SOC_IF_ERROR_RETURN(_soc_katana2_parity_enable_info( 5452 unit, port, route_block_en_reg, 5453 &route_block_rval, 5454 route_block->info, enable)); 5455 /* Write per route block parity enable register */ 5456 SOC_IF_ERROR_RETURN(soc_reg32_set( 5457 unit, route_block_en_reg, 5458 port, 0, route_block_rval)); 5459 break; 5460 } 5461 } 5462 } else if (route_block->blocktype == SOC_BLK_MMU) { 5463 SOC_IF_ERROR_RETURN(_soc_katana2_parity_enable_mmu(unit, 5464 route_block_en_reg, enable)); 5465 5466 } else { 5467 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, route_block_en_reg, 5468 port, 0, &route_block_rval)); 5469 SOC_IF_ERROR_RETURN(_soc_katana2_parity_enable_info( 5470 unit, port, route_block_en_reg, 5471 &route_block_rval, 5472 route_block->info, enable)); 5473 /* Write per route block parity enable register */ 5474 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, route_block_en_reg, 5475 port, 0, route_block_rval)); 5476 } 5477 } /* Loop through each place-and-route block entry */ 5478 5479 SOC_IF_ERROR_RETURN(READ_MISCCONFIGr(unit, &rval)); 5480 soc_reg_field_set(unit, MISCCONFIGr, &rval, PARITY_STAT_CLEARf, 1); 5481 SOC_IF_ERROR_RETURN(WRITE_MISCCONFIGr(unit, rval)); 5482 5483 SOC_IF_ERROR_RETURN(READ_THDO_MISCCONFIGr(unit, &rval)); 5484 soc_reg_field_set(unit, THDO_MISCCONFIGr, &rval, STAT_CLEARf, 1); 5485 SOC_IF_ERROR_RETURN(WRITE_THDO_MISCCONFIGr(unit, rval)); 5486 5487 SOC_IF_ERROR_RETURN(READ_WRED_MISCCONFIGr(unit, &rval)); 5488 soc_reg_field_set(unit, WRED_MISCCONFIGr, &rval, PARITY_STAT_CLRf, 1); 5489 SOC_IF_ERROR_RETURN(WRITE_WRED_MISCCONFIGr(unit, rval)); 5490 5491 SOC_IF_ERROR_RETURN(READ_RQE_GLOBAL_CONFIGr(unit, &rval)); 5492 soc_reg_field_set(unit, RQE_GLOBAL_CONFIGr, &rval, PARITY_STAT_CLRf, 1); 5493 SOC_IF_ERROR_RETURN(WRITE_RQE_GLOBAL_CONFIGr(unit, rval)); 5494 5495 SOC_IF_ERROR_RETURN(READ_MISCCONFIGr(unit, &rval)); 5496 soc_reg_field_set(unit, MISCCONFIGr, &rval, PARITY_CHK_ENf, 5497 enable ? 1 : 0); 5498 soc_reg_field_set(unit, MISCCONFIGr, &rval, PARITY_GEN_ENf, 5499 enable ? 1 : 0); 5500 soc_reg_field_set(unit, MISCCONFIGr, &rval, PARITY_STAT_CLEARf, 0); 5501 SOC_IF_ERROR_RETURN(WRITE_MISCCONFIGr(unit, rval)); 5502 5503 SOC_IF_ERROR_RETURN(READ_THDO_MISCCONFIGr(unit, &rval)); 5504 soc_reg_field_set(unit, THDO_MISCCONFIGr, &rval, PARITY_CHK_ENf, 5505 enable ? 1 : 0); 5506 soc_reg_field_set(unit, THDO_MISCCONFIGr, &rval, PARITY_GEN_ENf, 5507 enable ? 1 : 0); 5508 soc_reg_field_set(unit, THDO_MISCCONFIGr, &rval, STAT_CLEARf, 0); 5509 SOC_IF_ERROR_RETURN(WRITE_THDO_MISCCONFIGr(unit, rval)); 5510 5511 SOC_IF_ERROR_RETURN(READ_WRED_MISCCONFIGr(unit, &rval)); 5512 soc_reg_field_set(unit, WRED_MISCCONFIGr, &rval, PARITY_CHK_ENf, 5513 enable ? 1 : 0); 5514 soc_reg_field_set(unit, WRED_MISCCONFIGr, &rval, PARITY_GEN_ENf, 5515 enable ? 1 : 0); 5516 soc_reg_field_set(unit, WRED_MISCCONFIGr, &rval, PARITY_STAT_CLRf, 0); 5517 SOC_IF_ERROR_RETURN(WRITE_WRED_MISCCONFIGr(unit, rval)); 5518 5519 SOC_IF_ERROR_RETURN(READ_RQE_GLOBAL_CONFIGr(unit, &rval)); 5520 soc_reg_field_set(unit, RQE_GLOBAL_CONFIGr, &rval, PARITY_CHK_ENf, 5521 enable ? 1 : 0); 5522 soc_reg_field_set(unit, RQE_GLOBAL_CONFIGr, &rval, PARITY_GEN_ENf, 5523 enable ? 1 : 0); 5524 soc_reg_field_set(unit, RQE_GLOBAL_CONFIGr, &rval, PARITY_STAT_CLRf, 0); 5525 SOC_IF_ERROR_RETURN(WRITE_RQE_GLOBAL_CONFIGr(unit, rval)); 5526 5527 if (enable) 5528 { 5529 /* Write CMIC enable register */ 5530 (void)soc_cmicm_intr2_enable(unit, cmic_rval); 5531 } else { 5532 /* Disabling fully SER,TXLP and RXLP parity for time-being */ 5533 SOC_IF_ERROR_RETURN(WRITE_SER_RANGE_ENABLEr(unit, 0)); 5534 if (SOC_PORT_VALID(unit, 27)) { 5535 SOC_IF_ERROR_RETURN(WRITE_TXLP_ECC_PARITY_CONTROLr(unit,27, 0)); 5536 SOC_IF_ERROR_RETURN(WRITE_RXLP_ECC_PARITY_CONTROLr(unit,27, 0)); 5537 } 5538 if (SOC_PORT_VALID(unit, 28)) { 5539 SOC_IF_ERROR_RETURN(WRITE_TXLP_ECC_PARITY_CONTROLr(unit,28, 0)); 5540 SOC_IF_ERROR_RETURN(WRITE_RXLP_ECC_PARITY_CONTROLr(unit,28, 0)); 5541 } 5542 /* Write CMIC disable register */ 5543 (void)soc_cmicm_intr2_disable(unit, cmic_rval); 5544 } 5545 return SOC_E_NONE; 5546 } 5547 5548 void 5549 _soc_katana2_mem_rename(soc_mem_t *memory) 5550 { 5551 soc_mem_t mem = *memory; 5552 5553 switch(*memory) { 5554 case VLAN_SUBNETm: 5555 mem = VLAN_SUBNET_DATA_ONLYm; 5556 break; 5557 case L2Xm: 5558 mem = L2_ENTRY_ONLYm; 5559 break; 5560 case L3_DEFIPm: 5561 mem = L3_DEFIP_DATA_ONLYm; 5562 break; 5563 case L3_DEFIP_128m: 5564 mem = L3_DEFIP_128_DATA_ONLYm; 5565 break; 5566 case EGR_IP_TUNNEL_IPV6m: 5567 case EGR_IP_TUNNEL_MPLSm: 5568 mem = EGR_IP_TUNNELm; 5569 break; 5570 case VLAN_MACm: 5571 mem = VLAN_XLATEm; 5572 break; 5573 default: 5574 /* Do nothing, keep memory as provided */ 5575 break; 5576 } 5577 *memory = mem; 5578 } 5579 5580 int 5581 _soc_katana2_mem_parity_control(int unit, soc_mem_t mem, int copyno, 5582 int enable) 5583 { 5584 const _soc_katana2_parity_route_block_t *route_block; 5585 int route_block_index; 5586 uint32 cmic_bit; 5587 int info_index; 5588 soc_reg_t reg; 5589 uint32 rval; 5590 const _soc_katana2_parity_info_t *info; 5591 5592 if (!soc_property_get(unit, spn_PARITY_ENABLE, FALSE)) { 5593 /* Parity checking is not enabled, nothing to do */ 5594 return SOC_E_NONE; 5595 } 5596 5597 /* Convert component/aggregate memories to the table for which 5598 * the parity registers correspond. */ 5599 _soc_katana2_mem_rename(&mem); 5600 5601 /* Loop through each place-and-route block entry */ 5602 for (route_block_index = 0; ; route_block_index++) { 5603 route_block = &_soc_katana2_parity_route_blocks[route_block_index]; 5604 cmic_bit = route_block->cmic_bit; 5605 if (cmic_bit == 0) { 5606 /* End of table */ 5607 break; 5608 } 5609 5610 if (route_block->blocktype == SOC_BLK_MMU) { 5611 SOC_IF_ERROR_RETURN(_soc_katana2_parity_enable_mmu(unit, 5612 route_block->enable_reg, enable)); 5613 continue; 5614 } 5615 5616 /* Loop through each info entry in the list */ 5617 for (info_index = 0; ; info_index++) { 5618 info = &route_block->info[info_index]; 5619 if (info->type == _SOC_PARITY_TYPE_NONE) { 5620 /* End of table */ 5621 break; 5622 } 5623 if (mem != INVALIDm && info->mem != mem) { 5624 continue; 5625 } 5626 5627 /* Handle different parity error reporting style */ 5628 switch (info->type) { 5629 case _SOC_PARITY_TYPE_PARITY: 5630 case _SOC_PARITY_TYPE_ECC: 5631 case _SOC_PARITY_TYPE_HASH: 5632 case _SOC_PARITY_TYPE_EDATABUF: 5633 case _SOC_PARITY_TYPE_COUNTER: 5634 reg = info->enable_reg; 5635 if (!SOC_REG_IS_VALID(unit, reg)) { 5636 continue; 5637 } 5638 5639 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, reg, REG_PORT_ANY, 0, &rval)); 5640 soc_reg_field_set(unit, reg, &rval, info->enable_field, 5641 enable ? 1 : 0); 5642 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, reg, REG_PORT_ANY, 0, rval)); 5643 break; 5644 case _SOC_PARITY_TYPE_GENERIC: 5645 default: 5646 break; 5647 } 5648 } 5649 } 5650 5651 return SOC_E_NONE; 5652 } 5653 5654 STATIC int 5655 _soc_katana2_parity_process_info(int unit, soc_port_t port, soc_reg_t reg, 5656 uint32 status, 5657 const _soc_katana2_parity_info_t *info_list, 5658 char *prefix_str, soc_block_t block_type, 5659 int block_idx); 5660 5661 STATIC int 5662 _soc_katana2_parity_ser_correction(int unit, const _soc_katana2_parity_info_t *info, 5663 char *prefix_str, char *mem_str_ptr, 5664 uint32 entry_idx, uint32 multiple, 5665 soc_block_t block_type, int schan) 5666 { 5667 int rv = SOC_E_NONE; 5668 _soc_ser_correct_info_t spci = {0}; 5669 5670 LOG_ERROR(BSL_LS_SOC_COMMON, 5671 (BSL_META_U(unit, 5672 "%s %s entry %d parity error\n"), prefix_str, 5673 mem_str_ptr, entry_idx)); 5674 if (multiple) { 5675 LOG_ERROR(BSL_LS_SOC_COMMON, 5676 (BSL_META_U(unit, 5677 "%s %s has multiple parity errors\n"), 5678 prefix_str, mem_str_ptr)); 5679 } 5680 if (info->mem != INVALIDm) { 5681 spci.flags = SOC_SER_SRC_MEM | SOC_SER_REG_MEM_KNOWN; 5682 if (schan) { 5683 spci.flags |= SOC_SER_ERR_CPU; 5684 } 5685 spci.reg = INVALIDr; 5686 spci.mem = info->mem; 5687 spci.blk_type = block_type; 5688 spci.index = entry_idx; 5689 rv = soc_ser_correction(unit, &spci); 5690 } else if (info->reg != INVALIDr) { 5691 spci.flags = SOC_SER_SRC_REG | SOC_SER_REG_MEM_KNOWN; 5692 if (schan) { 5693 spci.flags |= SOC_SER_ERR_CPU; 5694 } 5695 spci.reg = info->reg; 5696 spci.mem = INVALIDm; 5697 spci.blk_type = block_type; 5698 spci.port = entry_idx; 5699 rv = soc_ser_correction(unit, &spci); 5700 } 5701 5702 return rv; 5703 } 5704 5705 int 5706 _soc_kt2_mem_index_remap(int unit, soc_mem_t mem, int index) 5707 { 5708 switch (mem) { 5709 case L3_DEFIPm: 5710 case L3_DEFIP_PAIR_128m: 5711 case L3_DEFIP_ONLYm: 5712 case L3_DEFIP_PAIR_128_ONLYm: 5713 case L3_DEFIP_DATA_ONLYm: 5714 case L3_DEFIP_PAIR_128_DATA_ONLYm: 5715 return soc_kt2_l3_defip_index_remap(unit, mem, index); 5716 default: 5717 return index; 5718 } 5719 } 5720 5721 STATIC int 5722 _soc_katana2_parity_process_parity(int unit, soc_port_t port, 5723 const _soc_katana2_parity_info_t *info, 5724 int schan, char *prefix_str, char *mem_str, 5725 soc_block_t block_type, int block_idx) 5726 { 5727 _soc_katana2_parity_reg_t reg_entry[2], *reg_ptr; 5728 soc_reg_t reg; 5729 uint32 rval, minfo; 5730 uint32 multiple, entry_idx, idx, has_error; 5731 char *mem_str_ptr; 5732 int rv = SOC_E_NONE; 5733 5734 if (schan) { 5735 /* Some table does not have NACK register */ 5736 if (info->nack_status_reg == INVALIDr && 5737 info->nack_status_reg_list == NULL) { 5738 return rv; 5739 } 5740 reg_entry[0].reg = info->nack_status_reg; 5741 reg_entry[0].mem_str = NULL; 5742 reg_entry[1].reg = INVALIDr; 5743 reg_ptr = reg_entry; 5744 } else { 5745 if (info->intr_status_reg != INVALIDr) { 5746 reg_entry[0].reg = info->intr_status_reg; 5747 reg_entry[0].mem_str = NULL; 5748 reg_entry[1].reg = INVALIDr; 5749 reg_ptr = reg_entry; 5750 } else if (info->intr_status_reg_list != NULL) { 5751 reg_ptr = info->intr_status_reg_list; 5752 } else { 5753 return rv; 5754 } 5755 } 5756 5757 has_error = FALSE; 5758 for (idx = 0; reg_ptr[idx].reg != INVALIDr; idx++) { 5759 reg = reg_ptr[idx].reg; 5760 mem_str_ptr = reg_ptr[idx].mem_str != NULL ? 5761 reg_ptr[idx].mem_str : mem_str; 5762 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, reg, port, 0, &rval)); 5763 5764 if (soc_reg_field_valid(unit, reg, PARITY_ERRf)) { 5765 if (soc_reg_field_get(unit, reg, rval, PARITY_ERRf)) { 5766 has_error = TRUE; 5767 multiple = soc_reg_field_get(unit, reg, rval, MULTIPLE_ERRf); 5768 if (soc_reg_field_valid(unit, reg, ADDRESSf)) { 5769 entry_idx = soc_reg_field_get(unit, reg, rval, ADDRESSf); 5770 } else { 5771 entry_idx = soc_reg_field_get(unit, reg, rval, ENTRY_IDXf); 5772 } 5773 /* Convert physical index to logical index */ 5774 entry_idx = _soc_kt2_mem_index_remap(unit, info->mem, entry_idx); 5775 5776 _soc_katana2_mem_parity_info(unit, block_idx, 0, 5777 info->group_reg_status_field, &minfo); 5778 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 5779 SOC_SWITCH_EVENT_DATA_ERROR_PARITY, 5780 entry_idx, minfo); 5781 rv = _soc_katana2_parity_ser_correction(unit, info, prefix_str, 5782 mem_str_ptr, entry_idx, 5783 multiple, block_type, 5784 schan); 5785 if (SOC_FAILURE(rv)) { 5786 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 5787 SOC_SWITCH_EVENT_DATA_ERROR_FAILEDTOCORRECT, 5788 entry_idx, minfo); 5789 } 5790 /* Clear parity status */ 5791 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, reg, port, 0, 0)); 5792 } 5793 } else if (soc_reg_field_valid(unit, reg, PARITY_ERR_Af)) { 5794 /* For registers RX_PROT_GROUP_TABLE_DMA_PARITY_STATUS_INTR/NACK 5795 they have fileds PARITY_ERR_A and PARITY_ERR_B */ 5796 if (soc_reg_field_get(unit, reg, rval, PARITY_ERR_Af)) { 5797 has_error = TRUE; 5798 multiple = soc_reg_field_get(unit, reg, rval, MULTIPLE_ERR_Af); 5799 entry_idx = soc_reg_field_get(unit, reg, rval, ENTRY_IDX_Af); 5800 _soc_katana2_mem_parity_info(unit, block_idx, 0, 5801 info->group_reg_status_field, &minfo); 5802 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 5803 SOC_SWITCH_EVENT_DATA_ERROR_PARITY, 5804 entry_idx, minfo); 5805 rv = _soc_katana2_parity_ser_correction(unit, info, prefix_str, 5806 mem_str_ptr, entry_idx, 5807 multiple, block_type, 5808 schan); 5809 if (SOC_FAILURE(rv)) { 5810 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 5811 SOC_SWITCH_EVENT_DATA_ERROR_FAILEDTOCORRECT, 5812 entry_idx, minfo); 5813 } 5814 } 5815 if (soc_reg_field_get(unit, reg, rval, PARITY_ERR_Bf)) { 5816 has_error = TRUE; 5817 multiple = soc_reg_field_get(unit, reg, rval, MULTIPLE_ERR_Bf); 5818 entry_idx = soc_reg_field_get(unit, reg, rval, ENTRY_IDX_Bf); 5819 _soc_katana2_mem_parity_info(unit, block_idx, 0, 5820 info->group_reg_status_field, &minfo); 5821 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 5822 SOC_SWITCH_EVENT_DATA_ERROR_PARITY, 5823 entry_idx, minfo); 5824 rv = _soc_katana2_parity_ser_correction(unit, info, prefix_str, 5825 mem_str_ptr, entry_idx, 5826 multiple, block_type, 5827 schan); 5828 if (SOC_FAILURE(rv)) { 5829 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 5830 SOC_SWITCH_EVENT_DATA_ERROR_FAILEDTOCORRECT, 5831 entry_idx, minfo); 5832 } 5833 } 5834 if (has_error == TRUE) { 5835 /* Clear parity status */ 5836 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, reg, port, 0, 0)); 5837 } 5838 } else { 5839 return rv; 5840 } 5841 } 5842 5843 if (!has_error) { 5844 LOG_ERROR(BSL_LS_SOC_COMMON, 5845 (BSL_META_U(unit, 5846 "%s %s parity hardware inconsistency\n"), 5847 prefix_str, mem_str)); 5848 } 5849 5850 return rv; 5851 } /*_soc_katana_parity_process_parity*/ 5852 5853 STATIC int 5854 _soc_katana2_parity_process_ecc(int unit, soc_port_t port, 5855 const _soc_katana2_parity_info_t *info, 5856 int schan, char *prefix_str, char *mem_str, 5857 soc_block_t block_type, int block_idx) 5858 { 5859 int rv = SOC_E_NONE; 5860 _soc_katana2_parity_reg_t reg_entry[2], *reg_ptr; 5861 soc_reg_t reg; 5862 uint32 rval, minfo; 5863 uint32 multiple = 0; 5864 uint32 double_bit = 0; 5865 uint32 entry_idx = 0; 5866 uint32 idx, has_error; 5867 char *mem_str_ptr; 5868 _soc_ser_correct_info_t spci = {0}; 5869 5870 if (schan) { 5871 /* Some table does not have NACK register */ 5872 if (info->nack_status_reg == INVALIDr && 5873 info->nack_status_reg_list == NULL) { 5874 return rv; 5875 } 5876 reg_entry[0].reg = info->nack_status_reg; 5877 reg_entry[0].mem_str = NULL; 5878 reg_entry[1].reg = INVALIDr; 5879 reg_ptr = reg_entry; 5880 } else { 5881 if (info->intr_status_reg != INVALIDr) { 5882 reg_entry[0].reg = info->intr_status_reg; 5883 reg_entry[0].mem_str = NULL; 5884 reg_entry[1].reg = INVALIDr; 5885 reg_ptr = reg_entry; 5886 } else if (info->intr_status_reg_list != NULL) { 5887 reg_ptr = info->intr_status_reg_list; 5888 } else { 5889 return rv; 5890 } 5891 } 5892 5893 has_error = FALSE; 5894 for (idx = 0; reg_ptr[idx].reg != INVALIDr; idx++) { 5895 reg = reg_ptr[idx].reg; 5896 mem_str_ptr = reg_ptr[idx].mem_str != NULL ? 5897 reg_ptr[idx].mem_str : mem_str; 5898 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, reg, port, 0, &rval)); 5899 5900 if (soc_reg_field_get(unit, reg, rval, ECC_ERRf)) { 5901 has_error = TRUE; 5902 if (SOC_REG_FIELD_VALID(unit, reg, MULTIPLE_ERRf)) { 5903 multiple = soc_reg_field_get(unit, reg, rval, MULTIPLE_ERRf); 5904 } else if (SOC_REG_FIELD_VALID(unit, reg, ECC_ERR_MULTIf)) { 5905 multiple = soc_reg_field_get(unit, reg, rval, ECC_ERR_MULTIf); 5906 } 5907 if (SOC_REG_FIELD_VALID(unit, reg, DOUBLE_BIT_ERRf)) { 5908 double_bit = soc_reg_field_get(unit, reg, rval, DOUBLE_BIT_ERRf); 5909 } else if (SOC_REG_FIELD_VALID(unit, reg, ECC_ERR_2Bf)) { 5910 double_bit = soc_reg_field_get(unit, reg, rval, ECC_ERR_2Bf); 5911 } 5912 if (SOC_REG_FIELD_VALID(unit, reg, ENTRY_IDXf)) { 5913 entry_idx = soc_reg_field_get(unit, reg, rval, ENTRY_IDXf); 5914 } 5915 if (double_bit) { 5916 LOG_ERROR(BSL_LS_SOC_COMMON, 5917 (BSL_META_U(unit, 5918 "%s %s entry %d double-bit ECC error\n"), 5919 prefix_str, mem_str_ptr, entry_idx)); 5920 spci.double_bit = 1; 5921 } else if (multiple) { 5922 LOG_ERROR(BSL_LS_SOC_COMMON, 5923 (BSL_META_U(unit, 5924 "%s %s has multiple ECC errors\n"), 5925 prefix_str, mem_str_ptr)); 5926 } else { 5927 LOG_ERROR(BSL_LS_SOC_COMMON, 5928 (BSL_META_U(unit, 5929 "%s %s entry %d ECC error\n"), 5930 prefix_str, mem_str_ptr, entry_idx)); 5931 } 5932 _soc_katana2_mem_parity_info(unit, block_idx, 0, 5933 info->group_reg_status_field, &minfo); 5934 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 5935 SOC_SWITCH_EVENT_DATA_ERROR_ECC, 5936 entry_idx, minfo); 5937 if (info->mem != INVALIDm) { 5938 spci.flags = SOC_SER_SRC_MEM | SOC_SER_REG_MEM_KNOWN; 5939 if (schan) { 5940 spci.flags |= SOC_SER_ERR_CPU; 5941 } 5942 spci.reg = INVALIDr; 5943 spci.mem = info->mem; 5944 spci.blk_type = block_type; 5945 spci.index = entry_idx; 5946 spci.parity_type = SOC_PARITY_TYPE_ECC; 5947 rv = soc_ser_correction(unit, &spci); 5948 if (SOC_FAILURE(rv)) { 5949 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 5950 SOC_SWITCH_EVENT_DATA_ERROR_FAILEDTOCORRECT, 5951 entry_idx, minfo); 5952 } 5953 } 5954 /* Clear parity status */ 5955 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, reg, port, 0, 0)); 5956 } 5957 5958 } 5959 5960 if (!has_error) { 5961 LOG_ERROR(BSL_LS_SOC_COMMON, 5962 (BSL_META_U(unit, 5963 "%s %s ECC hardware inconsistency\n"), 5964 prefix_str, mem_str)); 5965 } 5966 5967 return rv; 5968 } 5969 5970 int 5971 _soc_katana2_l3_entry_idx_map(soc_mem_t mem, int entry_idx) 5972 { 5973 int new_id = entry_idx; 5974 5975 switch (mem) { 5976 case L3_ENTRY_IPV6_UNICASTm: 5977 case L3_ENTRY_IPV4_MULTICASTm: 5978 new_id = entry_idx/2; 5979 break; 5980 case L3_ENTRY_IPV6_MULTICASTm: 5981 new_id = entry_idx/4; 5982 break; 5983 default: 5984 break; 5985 } 5986 return new_id; 5987 } 5988 5989 STATIC int 5990 _soc_katana2_parity_process_hash(int unit, soc_port_t port, 5991 const _soc_katana2_parity_info_t *info, 5992 int schan, char *prefix_str, char *mem_str, 5993 soc_block_t block_type, int block_idx) 5994 { 5995 int rv = SOC_E_NONE; 5996 _soc_katana2_parity_reg_t *reg_ptr; 5997 soc_reg_t reg; 5998 uint32 rval, minfo; 5999 uint32 bitmap, multiple, bucket_idx; 6000 int bucket_size, entry_idx = -1, idx, bank_bkt_idx, bits, has_error; 6001 _soc_ser_correct_info_t spci = {0}; 6002 soc_field_t efield = PARITY_ERR_BMf; 6003 soc_field_t bfield = BUCKET_IDXf; 6004 soc_field_t mfield = MULTIPLE_ERRf; 6005 6006 if (schan) { 6007 reg_ptr = info->nack_status_reg_list; 6008 } else { 6009 reg_ptr = info->intr_status_reg_list; 6010 } 6011 6012 has_error = FALSE; 6013 for (idx = 0; idx < 2; idx ++) { 6014 reg = reg_ptr[idx].reg; 6015 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, reg, port, 0, &rval)); 6016 /* Some memories have this field named differently */ 6017 if (soc_reg_field_valid(unit, reg, PARITY_ERR_BMf)) { 6018 efield = PARITY_ERR_BMf; 6019 bfield = BUCKET_IDXf; 6020 mfield = MULTIPLE_ERRf; 6021 } else if (soc_reg_field_valid(unit, reg, PARITY_ERR_BM_0f)) { 6022 efield = PARITY_ERR_BM_0f; 6023 bfield = BUCKET_IDX_0f; 6024 mfield = MULTIPLE_ERR_0f; 6025 } else if (soc_reg_field_valid(unit, reg, PARITY_ERR_BM_1f)) { 6026 efield = PARITY_ERR_BM_1f; 6027 bfield = BUCKET_IDX_1f; 6028 mfield = MULTIPLE_ERR_1f; 6029 } 6030 6031 bitmap = soc_reg_field_get(unit, reg, rval, efield); 6032 if (bitmap != 0) { 6033 has_error = TRUE; 6034 multiple = soc_reg_field_get(unit, reg, rval, mfield); 6035 bucket_size = soc_reg_field_length(unit, reg, efield); 6036 bucket_idx = soc_reg_field_get(unit, reg, rval, bfield) * 6037 bucket_size * 2; 6038 bank_bkt_idx = idx * bucket_size + bucket_idx; 6039 for (bits = 0; bits < bucket_size; bits++) { 6040 if (bitmap & (1 << bits)) { 6041 entry_idx = bank_bkt_idx + bits; 6042 entry_idx = _soc_katana2_l3_entry_idx_map(info->mem, entry_idx); 6043 _soc_katana2_mem_parity_info(unit, block_idx, 0, 6044 info->group_reg_status_field, &minfo); 6045 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 6046 SOC_SWITCH_EVENT_DATA_ERROR_PARITY, 6047 entry_idx, minfo); 6048 LOG_ERROR(BSL_LS_SOC_COMMON, 6049 (BSL_META_U(unit, 6050 "%s %s entry %d parity error\n"), 6051 prefix_str, mem_str, entry_idx)); 6052 if ((info->mem != INVALIDm) && (entry_idx != -1)) { 6053 spci.flags = SOC_SER_SRC_MEM | SOC_SER_REG_MEM_KNOWN; 6054 if (schan) { 6055 spci.flags |= SOC_SER_ERR_CPU; 6056 } 6057 spci.reg = INVALIDr; 6058 spci.mem = info->mem == L2_ENTRY_ONLYm ? L2Xm : info->mem; 6059 spci.blk_type = block_type; 6060 spci.index = entry_idx; 6061 rv = soc_ser_correction(unit, &spci); 6062 if (SOC_FAILURE(rv)) { 6063 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 6064 SOC_SWITCH_EVENT_DATA_ERROR_FAILEDTOCORRECT, 6065 entry_idx, minfo); 6066 } 6067 } 6068 } 6069 } 6070 if (multiple) { 6071 LOG_ERROR(BSL_LS_SOC_COMMON, 6072 (BSL_META_U(unit, 6073 "%s %s has multiple parity errors\n"), 6074 prefix_str, mem_str)); 6075 } 6076 /* Clear parity status */ 6077 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, reg, port, 0, 0)); 6078 } 6079 } 6080 6081 if (!has_error) { 6082 LOG_ERROR(BSL_LS_SOC_COMMON, 6083 (BSL_META_U(unit, 6084 "%s %s parity hardware inconsistency\n"), 6085 prefix_str, mem_str)); 6086 } 6087 6088 return rv; 6089 } 6090 6091 STATIC int 6092 _soc_katana2_parity_process_edatabuf(int unit, soc_port_t port, 6093 const _soc_katana2_parity_info_t *info, 6094 int schan, char *prefix_str, 6095 char *mem_str, int block_idx) 6096 { 6097 soc_reg_t reg; 6098 uint32 rval, minfo; 6099 uint32 double_bit, multiple; 6100 6101 if (schan) { 6102 /* Some table may not have NACK status register */ 6103 if (info->nack_status_reg == INVALIDr) { 6104 return SOC_E_NONE; 6105 } 6106 reg = info->nack_status_reg; 6107 } else { 6108 reg = info->intr_status_reg; 6109 } 6110 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, reg, port, 0, &rval)); 6111 6112 if (soc_reg_field_get(unit, reg, rval, ECC_ERR_MGRPf)) { 6113 double_bit = soc_reg_field_get(unit, reg, rval, ECC_ERR_2B_MGRPf); 6114 multiple = soc_reg_field_get(unit, reg, rval, ECC_MULTI_MGRPf); 6115 _soc_katana2_mem_parity_info(unit, block_idx, 0, 6116 info->group_reg_status_field, &minfo); 6117 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 6118 SOC_SWITCH_EVENT_DATA_ERROR_PARITY, 0, 6119 minfo); 6120 if (double_bit) { 6121 LOG_ERROR(BSL_LS_SOC_COMMON, 6122 (BSL_META_U(unit, 6123 "%s %s double-bit ECC error\n"), 6124 prefix_str, mem_str)); 6125 } else { 6126 LOG_ERROR(BSL_LS_SOC_COMMON, 6127 (BSL_META_U(unit, 6128 "%s %s ECC error\n"), 6129 prefix_str, mem_str)); 6130 } 6131 if (multiple) { 6132 LOG_ERROR(BSL_LS_SOC_COMMON, 6133 (BSL_META_U(unit, 6134 "%s %s has multiple ECC errors\n"), 6135 prefix_str, mem_str)); 6136 } 6137 } else { 6138 LOG_ERROR(BSL_LS_SOC_COMMON, 6139 (BSL_META_U(unit, 6140 "%s %s ECC hardware inconsistency\n"), 6141 prefix_str, mem_str)); 6142 } 6143 6144 /* Clear parity status */ 6145 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, reg, port, 0, 0)); 6146 6147 return SOC_E_NONE; 6148 } 6149 6150 STATIC int 6151 _soc_katana2_parity_process_counter(int unit, soc_port_t port, 6152 const _soc_katana2_parity_info_t *info, 6153 int schan, char *prefix_str, char *mem_str, 6154 soc_block_t block_type, int block_idx) 6155 { 6156 int rv = SOC_E_NONE; 6157 soc_cmap_t *cmap = NULL; 6158 soc_reg_t reg, counter_reg; 6159 uint32 rval, minfo; 6160 uint32 multiple, counter_idx, port_idx, entry_idx; 6161 char *counter_name; 6162 _soc_ser_correct_info_t spci = {0}; 6163 6164 if (schan) { 6165 reg = info->nack_status_reg; 6166 } else { 6167 reg = info->intr_status_reg; 6168 } 6169 6170 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, reg, port, 0, &rval)); 6171 6172 if (soc_reg_field_get(unit, reg, rval, PARITY_ERRf)) { 6173 multiple = soc_reg_field_get(unit, reg, rval, MULTIPLE_ERRf); 6174 counter_idx = soc_reg_field_get(unit, reg, rval, COUNTER_IDXf); 6175 port_idx = soc_reg_field_get(unit, reg, rval, PORT_IDXf); 6176 entry_idx = soc_reg_field_get(unit, reg, rval, ENTRY_IDXf); 6177 6178 /* TDBGC starts at index 0x1A of counter DMA table */ 6179 if (info->group_reg_status_field == EGR_STATS_COUNTER_TABLE_PAR_ERRf) { 6180 counter_idx += 0x1A; 6181 } 6182 cmap = soc_port_cmap_get(unit, port_idx); 6183 6184 if (cmap != NULL) { 6185 counter_reg = cmap->cmap_base[counter_idx].reg; 6186 if (SOC_REG_IS_VALID(unit, counter_reg)) { 6187 _soc_katana2_mem_parity_info(unit, block_idx, 0, 6188 info->group_reg_status_field, &minfo); 6189 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 6190 SOC_SWITCH_EVENT_DATA_ERROR_PARITY, 6191 entry_idx, minfo); 6192 counter_name = SOC_REG_NAME(unit, counter_reg); 6193 LOG_ERROR(BSL_LS_SOC_COMMON, 6194 (BSL_META_U(unit, 6195 "%s %s port %d %s entry %d parity error\n"), 6196 prefix_str, mem_str, port_idx, counter_name, 6197 entry_idx)); 6198 if (multiple) { 6199 LOG_ERROR(BSL_LS_SOC_COMMON, 6200 (BSL_META_U(unit, 6201 "%s %s has multiple parity errors\n"), 6202 prefix_str, mem_str)); 6203 } 6204 spci.flags = SOC_SER_SRC_REG | SOC_SER_REG_MEM_KNOWN; 6205 if (schan) { 6206 spci.flags |= SOC_SER_ERR_CPU; 6207 } 6208 spci.reg = counter_reg; 6209 spci.mem = INVALIDm; 6210 spci.blk_type = block_type; 6211 spci.port = port_idx; 6212 rv = soc_ser_correction(unit, &spci); 6213 if (SOC_FAILURE(rv)) { 6214 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 6215 SOC_SWITCH_EVENT_DATA_ERROR_FAILEDTOCORRECT, 6216 entry_idx, minfo); 6217 } 6218 _stat_error_fixed[unit]++; 6219 } else { 6220 LOG_ERROR(BSL_LS_SOC_COMMON, 6221 (BSL_META_U(unit, 6222 "%s %s parity hardware inconsistency\n"), 6223 prefix_str, mem_str)); 6224 } 6225 } else { 6226 LOG_ERROR(BSL_LS_SOC_COMMON, 6227 (BSL_META_U(unit, 6228 "cmap is NULL\n"))); 6229 } 6230 } else if (!schan) { 6231 LOG_ERROR(BSL_LS_SOC_COMMON, 6232 (BSL_META_U(unit, 6233 "%s %s parity hardware inconsistency\n"), 6234 prefix_str, mem_str)); 6235 } 6236 6237 /* Clear parity status */ 6238 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, reg, port, 0, 0)); 6239 6240 return rv; 6241 } 6242 6243 STATIC int 6244 _soc_katana2_parity_process_info(int unit, soc_port_t port, 6245 soc_reg_t group_reg, 6246 uint32 group_rval, 6247 const _soc_katana2_parity_info_t *info_list, 6248 char *prefix_str, 6249 soc_block_t block_type, 6250 int block_idx) 6251 { 6252 const _soc_katana2_parity_info_t *info; 6253 int info_index; 6254 char *mem_str; 6255 6256 /* Loop through each info entry in the list */ 6257 for (info_index = 0; ; info_index++) { 6258 info = &info_list[info_index]; 6259 if (info->type == _SOC_PARITY_TYPE_NONE) { 6260 /* End of table */ 6261 break; 6262 } 6263 6264 /* Check status for the info entry in the group register */ 6265 if (!soc_reg_field_get(unit, group_reg, group_rval, 6266 info->group_reg_status_field)) { 6267 continue; 6268 } 6269 6270 if (info->mem_str) { 6271 mem_str = info->mem_str; 6272 } else if (info->mem != INVALIDm) { 6273 mem_str = SOC_MEM_NAME(unit, info->mem); 6274 } else { 6275 mem_str = SOC_FIELD_NAME(unit, info->group_reg_status_field); 6276 } 6277 6278 /* Handle different parity error reporting style */ 6279 switch (info->type) { 6280 case _SOC_PARITY_TYPE_GENERIC: 6281 LOG_ERROR(BSL_LS_SOC_COMMON, 6282 (BSL_META_U(unit, 6283 "%s %s asserted\n"), prefix_str, mem_str)); 6284 break; 6285 case _SOC_PARITY_TYPE_PARITY: 6286 /* PARITY_ERRf, MULTIPLE_ERRf, ENTRY_IDXf */ 6287 SOC_IF_ERROR_RETURN 6288 (_soc_katana2_parity_process_parity(unit, port, info, FALSE, 6289 prefix_str, mem_str, 6290 block_type, block_idx)); 6291 break; 6292 case _SOC_PARITY_TYPE_ECC: 6293 /* ECC_ERRf, MULTIPLE_ERRf, DOUBLE_BIT_ERRf, ENTRY_IDXf */ 6294 SOC_IF_ERROR_RETURN 6295 (_soc_katana2_parity_process_ecc(unit, port, info, FALSE, 6296 prefix_str, mem_str, 6297 block_type, block_idx)); 6298 break; 6299 case _SOC_PARITY_TYPE_HASH: 6300 /* PARITY_ERR_BMf, MULTIPLE_ERRf, BUCKET_IDXf */ 6301 SOC_IF_ERROR_RETURN 6302 (_soc_katana2_parity_process_hash(unit, port, info, FALSE, 6303 prefix_str, mem_str, 6304 block_type, block_idx)); 6305 break; 6306 case _SOC_PARITY_TYPE_EDATABUF: 6307 /* ECC_ERR_MGRPf, ECC_ERR_2B_MGRPf, ECC_MULTI_MGRPf */ 6308 SOC_IF_ERROR_RETURN 6309 (_soc_katana2_parity_process_edatabuf(unit, port, info, FALSE, 6310 prefix_str, mem_str, 6311 block_idx)); 6312 break; 6313 case _SOC_PARITY_TYPE_COUNTER: 6314 /* PARITY_ERRf, MULTIPLE_ERRf, COUNTER_IDXf, PORT_IDX, 6315 ENTRY_IDXf */ 6316 SOC_IF_ERROR_RETURN 6317 (_soc_katana2_parity_process_counter(unit, port, info, FALSE, 6318 prefix_str, mem_str, 6319 block_type, block_idx)); 6320 break; 6321 default: 6322 break; 6323 } /* Handle different parity error reporting style */ 6324 } /* Loop through each info entry in the list */ 6325 6326 return SOC_E_NONE; 6327 } 6328 6329 STATIC int 6330 _soc_katana2_parity_process_all(int unit) 6331 { 6332 const _soc_katana2_parity_route_block_t *route_block; 6333 int route_block_index, block_idx; 6334 soc_port_t port; 6335 soc_reg_t route_block_en_reg, route_block_reg; 6336 uint32 cmic_rval, route_block_rval, rval = 0; 6337 uint32 route_block_enable; 6338 uint32 cmic_bit; 6339 char prefix_str[10]; 6340 soc_info_t *si = &SOC_INFO(unit); 6341 6342 port = REG_PORT_ANY; 6343 sal_sprintf(prefix_str, "unit %d", unit); 6344 6345 /* Read CMIC parity status register */ 6346 /* coverity[result_independent_of_operands] */ 6347 SOC_IF_ERROR_RETURN 6348 (READ_CMIC_CMC0_IRQ_STAT2r(unit, &cmic_rval)); 6349 if (cmic_rval == 0) { 6350 return SOC_E_NONE; 6351 } 6352 6353 /* Loop through each place-and-route block entry */ 6354 for (route_block_index = 0; ; route_block_index++) { 6355 route_block = &_soc_katana2_parity_route_blocks[route_block_index]; 6356 cmic_bit = route_block->cmic_bit; 6357 if (cmic_bit == 0) { 6358 /* End of table */ 6359 break; 6360 } 6361 6362 /* Check status for the route block in the CMIC register */ 6363 if (!(cmic_rval & cmic_bit)) { 6364 /* No interrupt bit asserted for the route block */ 6365 continue; 6366 } 6367 6368 /* get block and port for MXQ and RXLP and TXLP */ 6369 if ((route_block->blocktype == SOC_BLK_MXQPORT) || 6370 (route_block->blocktype == SOC_BLK_TXLP) || 6371 (route_block->blocktype == SOC_BLK_RXLP)) { 6372 SOC_BLOCK_ITER(unit, block_idx, route_block->blocktype) { 6373 if (SOC_BLOCK_INFO(unit, block_idx).number == route_block->id) { 6374 port = SOC_BLOCK_PORT(unit, block_idx); 6375 break; 6376 } 6377 } 6378 } else { 6379 SOC_BLOCK_ITER(unit, block_idx, route_block->blocktype) { 6380 if (SOC_BLOCK_INFO(unit, block_idx).number == route_block->id) { 6381 break; 6382 } 6383 } 6384 } 6385 6386 /* Read per route block parity status register */ 6387 route_block_reg = route_block->status_reg; 6388 route_block_en_reg = route_block->enable_reg; 6389 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, route_block_reg, port, 0, 6390 &route_block_rval)); 6391 if (route_block_rval == 0) { 6392 continue; 6393 } 6394 if (route_block->blocktype == SOC_BLK_MMU) { 6395 SOC_IF_ERROR_RETURN 6396 (_soc_katana2_parity_process_mmu(unit, route_block_en_reg, 6397 route_block_reg, prefix_str)); 6398 } else { 6399 6400 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, route_block_en_reg, port, 0, 6401 &route_block_enable)); 6402 route_block_rval &= route_block_enable; 6403 route_block_enable &= ~route_block_rval; 6404 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, route_block_en_reg, port, 0, 6405 route_block_enable)); 6406 6407 SOC_IF_ERROR_RETURN 6408 (_soc_katana2_parity_process_info(unit, port, route_block_reg, 6409 route_block_rval, 6410 route_block->info, 6411 prefix_str, 6412 route_block->blocktype, 6413 block_idx)); 6414 6415 route_block_enable |= route_block_rval; 6416 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, route_block_en_reg, port, 0, 6417 route_block_enable)); 6418 } 6419 } /* Loop through each place-and-route block entry */ 6420 6421 /* Handle LINK-PHY interrupt */ 6422 SOC_PBMP_ITER(si->linkphy_pbm, port) { 6423 if (SOC_REG_PORT_VALID(unit, RXLP_INTERRUPT_STATUSr, port)) { 6424 6425 if (READ_RXLP_INTERRUPT_STATUSr(unit, port, &rval)) { 6426 LOG_ERROR(BSL_LS_SOC_COMMON, 6427 (BSL_META_U(unit, 6428 "unit %d: Error reading %s reg !!\n"), 6429 unit, SOC_REG_NAME(unit, RXLP_INTERRUPT_STATUSr))); 6430 return SOC_E_INTERNAL; 6431 } 6432 if (rval & KT2_RXLP_INTR_MASK) { 6433 /* Call Linkphy interrupt handler */ 6434 soc_kt2_rxlp_interrupt_process(unit, port, rval); 6435 } 6436 } 6437 } 6438 6439 rval = 0; 6440 6441 /* Handle OAM interrupt */ 6442 if (READ_IP1_INTR_STATUS_1r(unit, &rval)) { 6443 LOG_ERROR(BSL_LS_SOC_COMMON, 6444 (BSL_META_U(unit, 6445 "unit %d: Error reading %s reg !!\n"), 6446 unit, SOC_REG_NAME(unit, IP1_INTR_STATUS_1r))); 6447 return SOC_E_INTERNAL; 6448 } 6449 if (rval & KT2_OAM_INTR_MASK) { 6450 /* Call OAM interrupt handler */ 6451 soc_kt2_oam_interrupt_process(unit); 6452 } 6453 6454 return SOC_E_NONE; 6455 } 6456 6457 void 6458 soc_katana2_parity_error(void *unit_vp, void *d1, void *d2, void *d3, void *d4) 6459 { 6460 int unit = PTR_TO_INT(unit_vp); 6461 6462 (void)_soc_katana2_parity_process_all(unit); 6463 sal_usleep(SAL_BOOT_QUICKTURN ? 100000 : 1000); /* Don't reenable too soon */ 6464 if (d2 != NULL) { 6465 (void)soc_cmicm_intr2_enable(unit, PTR_TO_INT(d2)); 6466 } 6467 } 6468 6469 void 6470 soc_katana2_oam_event_process(void *unit_vp, void *d1, void *d2, void *d3, void *d4) 6471 { 6472 int unit = PTR_TO_INT(unit_vp); 6473 uint32 rval; 6474 /* Handle OAM interrupt */ 6475 if (READ_IP1_INTR_STATUS_1r(unit, &rval) == SOC_E_NONE) { 6476 if (rval & KT2_OAM_INTR_MASK) { 6477 /* Call OAM interrupt handler */ 6478 soc_kt2_oam_interrupt_process(unit); 6479 } 6480 } else { 6481 LOG_ERROR(BSL_LS_SOC_COMMON, 6482 (BSL_META_U(unit, 6483 "unit %d: Error reading %s reg !!\n"), 6484 unit, SOC_REG_NAME(unit, IP1_INTR_STATUS_1r))); 6485 } 6486 sal_usleep(SAL_BOOT_QUICKTURN ? 100000 : 1000); /* Don't reenable too soon */ 6487 if (d2 != NULL) { 6488 (void)soc_cmicm_intr2_enable(unit, PTR_TO_INT(d2)); 6489 } 6490 } 6491 6492 STATIC int 6493 _soc_katana2_mem_nack_process_info(int unit, int reg_mem, 6494 _kt2_ser_nack_reg_mem_t nack_reg_mem, 6495 const _soc_katana2_parity_info_t *info_list, 6496 char *prefix_str, soc_block_t block_type, 6497 int block_idx) 6498 { 6499 const _soc_katana2_parity_info_t *info; 6500 int info_index; 6501 char *mem_str; 6502 soc_port_t port = REG_PORT_ANY; 6503 6504 /* Loop through each info entry in the list */ 6505 for (info_index = 0; ; info_index++) { 6506 info = &info_list[info_index]; 6507 if (info->type == _SOC_PARITY_TYPE_NONE) { 6508 /* End of table */ 6509 break; 6510 } 6511 if (reg_mem == _SOC_KT2_SER_MEM && info->mem != nack_reg_mem.mem) { 6512 continue; 6513 } 6514 if (info->mem_str) { 6515 mem_str = info->mem_str; 6516 } else { 6517 mem_str = SOC_MEM_NAME(unit, info->mem); 6518 } 6519 6520 if (reg_mem == _SOC_KT2_SER_REG && info->reg != nack_reg_mem.reg) { 6521 continue; 6522 } 6523 6524 /* Handle different parity error reporting style */ 6525 switch (info->type) { 6526 case _SOC_PARITY_TYPE_PARITY: 6527 /* PARITY_ERRf, MULTIPLE_ERRf, ENTRY_IDXf */ 6528 SOC_IF_ERROR_RETURN 6529 (_soc_katana2_parity_process_parity(unit, port, info, TRUE, 6530 prefix_str, mem_str, block_type, 6531 block_idx)); 6532 break; 6533 case _SOC_PARITY_TYPE_ECC: 6534 /* ECC_ERRf, MULTIPLE_ERRf, DOUBLE_BIT_ERRf, ENTRY_IDXf */ 6535 SOC_IF_ERROR_RETURN 6536 (_soc_katana2_parity_process_ecc(unit, port, info, TRUE, 6537 prefix_str, mem_str, block_type, 6538 block_idx)); 6539 break; 6540 case _SOC_PARITY_TYPE_HASH: 6541 /* PARITY_ERR_BMf, MULTIPLE_ERRf, BUCKET_IDXf */ 6542 SOC_IF_ERROR_RETURN 6543 (_soc_katana2_parity_process_hash(unit, port, info, TRUE, 6544 prefix_str, mem_str, block_type, 6545 block_idx)); 6546 break; 6547 case _SOC_PARITY_TYPE_EDATABUF: 6548 /* ECC_ERR_MGRPf, ECC_ERR_2B_MGRPf, ECC_MULTI_MGRPf */ 6549 SOC_IF_ERROR_RETURN 6550 (_soc_katana2_parity_process_edatabuf(unit, port, info, TRUE, 6551 prefix_str, mem_str, 6552 block_idx)); 6553 break; 6554 case _SOC_PARITY_TYPE_COUNTER: 6555 /* PARITY_ERRf, MULTIPLE_ERRf, COUNTER_IDXf, PORT_IDX, 6556 ENTRY_IDXf */ 6557 SOC_IF_ERROR_RETURN 6558 (_soc_katana2_parity_process_counter(unit, port, info, TRUE, 6559 prefix_str, mem_str, block_type, 6560 block_idx)); 6561 break; 6562 default: 6563 break; 6564 } /* Handle different parity error reporting style */ 6565 } /* Loop through each info entry in the list */ 6566 6567 return SOC_E_NONE; 6568 } 6569 6570 6571 STATIC int 6572 _soc_katana2_mem_nack_error_process(int unit, 6573 _kt2_ser_nack_reg_mem_t nack_reg_mem, 6574 int reg_mem) 6575 { 6576 const _soc_katana2_parity_route_block_t *route_block; 6577 int route_block_index, block_idx; 6578 uint32 cmic_bit; 6579 char prefix_str[10]; 6580 6581 sal_sprintf(prefix_str, "unit %d", unit); 6582 6583 /* Loop through each place-and-route block entry */ 6584 for (route_block_index = 0; ; route_block_index++) { 6585 route_block = &_soc_katana2_parity_route_blocks[route_block_index]; 6586 cmic_bit = route_block->cmic_bit; 6587 if (cmic_bit == 0) { 6588 /* End of table */ 6589 break; 6590 } 6591 6592 if (route_block->info == NULL) { 6593 continue; 6594 } 6595 SOC_BLOCK_ITER(unit, block_idx, route_block->blocktype) { 6596 if (SOC_BLOCK_INFO(unit, block_idx).number == route_block->id) { 6597 break; 6598 } 6599 } 6600 SOC_IF_ERROR_RETURN 6601 (_soc_katana2_mem_nack_process_info(unit, 6602 reg_mem, nack_reg_mem, 6603 route_block->info, 6604 prefix_str, route_block->blocktype, 6605 block_idx)); 6606 } /* Loop through each place-and-route block entry */ 6607 6608 return SOC_E_NONE; 6609 } 6610 6611 void 6612 soc_katana2_stat_nack(int unit, int *fixed) 6613 { 6614 int rv; 6615 _kt2_ser_nack_reg_mem_t nack_reg_mem; 6616 6617 nack_reg_mem.mem = INVALIDm; 6618 nack_reg_mem.reg = INVALIDr; 6619 _stat_error_fixed[unit] = 0; 6620 6621 if ((rv = _soc_katana2_mem_nack_error_process(unit, nack_reg_mem, 6622 _SOC_KT2_SER_REG)) < 0) { 6623 LOG_ERROR(BSL_LS_SOC_COMMON, 6624 (BSL_META_U(unit, 6625 "unit %d STAT SCHAN NACK analysis failure.\n"), unit)); 6626 } 6627 *fixed = _stat_error_fixed[unit]; 6628 } 6629 6630 void 6631 soc_katana2_mem_nack(void *unit_vp, void *addr_vp, void *blk_vp, 6632 void *d3, void *d4) 6633 { 6634 soc_mem_t mem = INVALIDm; 6635 int reg_mem = PTR_TO_INT(d3); 6636 int rv, unit = PTR_TO_INT(unit_vp); 6637 uint32 address = PTR_TO_INT(addr_vp); 6638 uint32 block = PTR_TO_INT(blk_vp); 6639 uint32 offset = 0, min_addr = 0, max_addr = 0; 6640 soc_regaddrinfo_t ainfo; 6641 _kt2_ser_nack_reg_mem_t nack_reg_mem; 6642 nack_reg_mem.mem = INVALIDm; 6643 nack_reg_mem.reg = INVALIDr; 6644 6645 if (reg_mem == _SOC_KT2_SER_REG) { 6646 if (address) { 6647 soc_regaddrinfo_get(unit, &ainfo, address); 6648 nack_reg_mem.reg = ainfo.reg; 6649 } 6650 } else { 6651 offset = address & ~0xC0f00000; /* Strip block ID */ 6652 mem = soc_addr_to_mem_extended(unit, block, 0, address); 6653 if (mem == INVALIDm) { 6654 LOG_ERROR(BSL_LS_SOC_COMMON, 6655 (BSL_META_U(unit, 6656 "unit %d mem decode failed, " 6657 "SCHAN NACK analysis failure\n"), unit)); 6658 return; 6659 } 6660 6661 _soc_katana2_mem_rename(&mem); 6662 6663 /* If reading a 'L3_TUNNEL_DATA_ONLY' entry has parity error, 6664 * 'L3_TUNNEL_PARITY_STATUS_NACK' will not report correct information 6665 * <PARITY_ERR=0,MULTIPLE_ERR=0,ENTRY_IDX=0> and SBUS NACK can reply to cpu. 6666 * If read this entry with 'L3_TUNNEL" view, 'L3_TUNNEL_PARITY_STATUS_NACK' can 6667 * report correct value. So create test data with 'L3_TUNNEL' for tr 144. 6668 * In nack processing, rename 'L3_TUNNEL' to 'L3_TUNNEL_DATA_ONLY' for get 6669 * correct ser control information in _soc_katana2_ip0_parity_info. 6670 */ 6671 if (mem == L3_TUNNELm) { 6672 mem = L3_TUNNEL_DATA_ONLYm; 6673 } 6674 6675 nack_reg_mem.mem = mem; 6676 6677 min_addr = max_addr = SOC_MEM_INFO(unit, mem).base; 6678 min_addr += SOC_MEM_INFO(unit, mem).index_min; 6679 max_addr += SOC_MEM_INFO(unit, mem).index_max; 6680 } 6681 6682 if ((rv = _soc_katana2_mem_nack_error_process(unit, nack_reg_mem, 6683 reg_mem)) < 0) { 6684 if (reg_mem == _SOC_KT2_SER_REG) { 6685 LOG_ERROR(BSL_LS_SOC_COMMON, 6686 (BSL_META_U(unit, 6687 "unit %d REG SCHAN NACK analysis failure\n"), 6688 unit)); 6689 } else { 6690 LOG_ERROR(BSL_LS_SOC_COMMON, 6691 (BSL_META_U(unit, 6692 "unit %d %s entry %d SCHAN NACK analysis failure\n"), 6693 unit, SOC_MEM_NAME(unit, mem), 6694 min_addr - offset)); 6695 } 6696 } 6697 6698 if (reg_mem == _SOC_KT2_SER_REG) { 6699 LOG_ERROR(BSL_LS_SOC_COMMON, 6700 (BSL_META_U(unit, 6701 "unit %d REG SCHAN NACK analysis\n"), 6702 unit)); 6703 } else { 6704 LOG_INFO(BSL_LS_SOC_SCHAN, 6705 (BSL_META_U(unit, 6706 "unit %d %s entry %d SCHAN NACK analysis\n"), 6707 unit, SOC_MEM_NAME(unit, mem), 6708 min_addr - offset)); 6709 } 6710 } 6711 6712 /* SER processing for TCAMs */ 6713 STATIC _soc_generic_ser_info_t _soc_kt2_tcam_ser_info_template[] = { 6714 6715 { MY_STATION_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_4BITS, 6716 _SOC_SER_INTERLEAVE_MOD2, 6717 { {0, 80}, {1, 80}, {81, 160}, {82, 160} }, 0, 0, 0, 0, 6718 _SOC_SER_FLAG_XY_READ }, 6719 { L2_USER_ENTRYm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_4BITS, 6720 _SOC_SER_INTERLEAVE_MOD2, 6721 { {0, 61}, {1, 61}, {62, 122}, {63, 122} }, 0, 0, 0, 0, 6722 _SOC_SER_FLAG_XY_READ }, 6723 { VLAN_SUBNETm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_4BITS, 6724 _SOC_SER_INTERLEAVE_MOD2, 6725 { {0, 64}, {1, 64}, {65, 128}, {66, 128} }, 0, 0, 0, 0, 6726 _SOC_SER_FLAG_XY_READ }, 6727 { L3_DEFIPm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_4BITS, 6728 _SOC_SER_INTERLEAVE_MOD2, 6729 { {0, 95}, {1, 95}, {96, 189}, {97, 189} }, 0, 0, 0, 0, 6730 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_SIZE_VERIFY | 6731 _SOC_SER_FLAG_NO_DMA | _SOC_SER_FLAG_REMAP_READ}, 6732 { L3_DEFIP_PAIR_128m, INVALIDm, _SOC_SER_TYPE_PARITY, 6733 _SOC_SER_PARITY_8BITS, 6734 _SOC_SER_INTERLEAVE_NONE, 6735 { {0, 95}, {96, 189}, {190, 285}, {286, 379} }, 0, 0, 0, 0, 6736 _SOC_SER_FLAG_XY_READ | 6737 _SOC_SER_FLAG_NO_DMA | _SOC_SER_FLAG_REMAP_READ | 6738 _SOC_SER_FLAG_SIZE_VERIFY}, 6739 { CPU_COS_MAPm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_4BITS, 6740 _SOC_SER_INTERLEAVE_MOD2, 6741 { {0, 140}, {1, 140}, {141, 280}, {142, 280} }, 0, 0, 0, 0, 6742 _SOC_SER_FLAG_XY_READ }, 6743 { EFP_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_4BITS, 6744 _SOC_SER_INTERLEAVE_MOD2, 6745 { {0, 235}, {1, 235}, {236, 469}, {237, 469} }, 0, 0, 0, 0, 6746 _SOC_SER_FLAG_XY_READ }, 6747 { FP_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_1BIT, 6748 _SOC_SER_INTERLEAVE_NONE, 6749 { {0, 235}, {1, 235}, {236, 469}, {237, 469} }, 0, 0, 0, 0, 6750 _SOC_SER_FLAG_XY_READ }, 6751 { VFP_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_4BITS, 6752 _SOC_SER_INTERLEAVE_MOD2, 6753 { {0, 235}, {1, 235}, {236, 469}, {237, 469} }, 0, 0, 0, 0, 6754 _SOC_SER_FLAG_XY_READ }, 6755 { FP_UDF_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_4BITS, 6756 _SOC_SER_INTERLEAVE_NONE, 6757 { {0, 69}, {1, 69}, {70, 138}, {71, 160} }, 0, 0, 0, 0, 6758 _SOC_SER_FLAG_XY_READ }, 6759 { SUBPORT_TAG_TO_PP_PORT_MAPm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_4BITS, 6760 _SOC_SER_INTERLEAVE_NONE, 6761 { {0, 64}, {1, 64}, {65, 128}, {66, 128} }, 0, 0, 0, 0, 6762 _SOC_SER_FLAG_XY_READ }, 6763 { L3_TUNNELm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_4BITS, 6764 _SOC_SER_INTERLEAVE_NONE, 6765 { {0, 106}, {1, 106}, {107, 212}, {108, 212} }, 0, 0, 0, 0, 6766 _SOC_SER_FLAG_XY_READ }, 6767 { FP_GLOBAL_MASK_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_4BITS, 6768 _SOC_SER_INTERLEAVE_NONE, 6769 { {0, 197}, {1, 197}, {198, 393}, {199, 393} }, 0, 0, 0, 0, 6770 _SOC_SER_FLAG_XY_READ }, 6771 { INVALIDm }, 6772 }; 6773 6774 #define SOC_KT2_SER_MEM_AVAILABLE (4096 * 32) /* bits */ 6775 static _soc_generic_ser_info_t *_soc_kt2_tcam_ser_info[SOC_MAX_NUM_DEVICES]; 6776 6777 #if defined (SER_TR_TEST_SUPPORT) 6778 soc_ser_test_functions_t ser_katana2_test_fun; 6779 #endif 6780 6781 STATIC int 6782 _soc_katana2_ser_init(int unit) 6783 { 6784 int alloc_size; 6785 6786 /* First, make per-unit copy of the master TCAM list */ 6787 alloc_size = sizeof(_soc_kt2_tcam_ser_info_template); 6788 if (NULL == _soc_kt2_tcam_ser_info[unit]) { 6789 if ((_soc_kt2_tcam_ser_info[unit] = 6790 sal_alloc(alloc_size, "kt2 tcam list")) == NULL) { 6791 return SOC_E_MEMORY; 6792 } 6793 } 6794 /* Make a fresh copy of the TCAM template info */ 6795 sal_memcpy(_soc_kt2_tcam_ser_info[unit], 6796 &(_soc_kt2_tcam_ser_info_template), 6797 alloc_size); 6798 return soc_generic_ser_init(unit, _soc_kt2_tcam_ser_info[unit]); 6799 } 6800 6801 void 6802 soc_kt2_ser_fail(int unit) 6803 { 6804 soc_generic_ser_process_error(unit, _soc_kt2_tcam_ser_info[unit], 6805 _SOC_PARITY_TYPE_SER); 6806 return; 6807 } 6808 6809 STATIC int 6810 _soc_katana2_parity_block_port(int unit, soc_block_t block, soc_port_t *port) 6811 { 6812 *port = SOC_BLOCK_PORT(unit, block); 6813 if ((*port != REG_PORT_ANY) && !SOC_PORT_VALID(unit, *port)) { 6814 return SOC_E_PORT; 6815 } 6816 6817 return SOC_E_NONE; 6818 } 6819 6820 int 6821 _soc_katana2_mem_nack_error_test(int unit, _soc_ser_test_t test_type, int *testErrors) 6822 { 6823 int group, table, rv; 6824 _soc_katana2_parity_info_t *info; 6825 soc_mem_t mem; 6826 soc_port_t block_port = 0; 6827 soc_block_t blk; 6828 uint32 test_count = 0; 6829 ser_test_data_t test_data; 6830 uint32 tmp_entry[SOC_MAX_MEM_WORDS], field_data[SOC_MAX_MEM_FIELD_WORDS]; 6831 6832 /* loop through each group */ 6833 for (group = 0; _soc_katana2_parity_route_blocks[group].cmic_bit; group++) { 6834 info = _soc_katana2_parity_route_blocks[group].info; 6835 6836 if (_soc_katana2_parity_route_blocks[group].blocktype == SOC_BLK_MMU) { 6837 continue; 6838 } else { 6839 SOC_BLOCK_ITER(unit, blk,_soc_katana2_parity_route_blocks[group].blocktype) { 6840 if (_soc_katana2_parity_block_port(unit, blk, &block_port) < 0) { 6841 continue; 6842 } 6843 6844 for (table = 0; info[table].type != _SOC_PARITY_TYPE_NONE; table++) { 6845 mem = info[table].mem; 6846 if (mem == INVALIDm) { 6847 continue; 6848 } 6849 if (SOC_MEM_INFO(unit, mem).flags & SOC_MEM_FLAG_SER_SPECIAL) { 6850 continue; 6851 } 6852 6853 if ((info[table].enable_reg == INVALIDr) || 6854 !soc_reg_field_valid(unit, info[table].enable_reg, 6855 info[table].enable_field)) { 6856 LOG_ERROR(BSL_LS_SOC_COMMON, 6857 (BSL_META_U(unit, 6858 "unit %d %s has no parity toggle\n"), 6859 unit, SOC_MEM_NAME(unit, mem))); 6860 continue; 6861 } 6862 switch (info[table].type) { 6863 case _SOC_PARITY_TYPE_PARITY: 6864 case _SOC_PARITY_TYPE_COUNTER: 6865 break; 6866 6867 default: 6868 /* No field to check. */ 6869 continue; 6870 } 6871 test_count++; 6872 LOG_CLI((BSL_META_U(unit, 6873 " nack test mem: %s); %d\n"), 6874 SOC_MEM_NAME(unit, mem), mem)); 6875 /* If reading a 'L3_TUNNEL_DATA_ONLY' entry has parity error, 6876 * 'L3_TUNNEL_PARITY_STATUS_NACK' canot report correct information 6877 * <PARITY_ERR=0,MULTIPLE_ERR=0,ENTRY_IDX=0> and SBUS NACK 6878 * can reply to cpu. If read this entry with 'L3_TUNNEL" view, 6879 * 'L3_TUNNEL_PARITY_STATUS_NACK' can report correct value. 6880 * So create test data with 'L3_TUNNEL' for tr 144. 6881 */ 6882 if (mem == L3_TUNNEL_DATA_ONLYm) { 6883 soc_ser_create_test_data(unit, tmp_entry, field_data, 6884 info[table].enable_reg, 6885 SOC_INVALID_TCAM_PARITY_BIT, 6886 info[table].enable_field, 6887 L3_TUNNELm, EVEN_PARITYf, 6888 MEM_BLOCK_ANY, 6889 REG_PORT_ANY, 6890 _SOC_ACC_TYPE_PIPE_ANY, 0, 6891 &test_data); 6892 } else { 6893 soc_ser_create_test_data(unit, tmp_entry, field_data, 6894 info[table].enable_reg, 6895 SOC_INVALID_TCAM_PARITY_BIT, 6896 info[table].enable_field, 6897 mem, INVALIDf, 6898 MEM_BLOCK_ANY, 6899 block_port, 6900 _SOC_ACC_TYPE_PIPE_ANY, 0, 6901 &test_data); 6902 } 6903 6904 rv = ser_test_mem(unit, 0, &test_data, test_type, 6905 testErrors); 6906 6907 if (rv != SOC_E_NONE) { 6908 LOG_CLI((BSL_META_U(unit, 6909 "Error during H/W test. Aborting.\n"))); 6910 return rv; 6911 } 6912 } 6913 } 6914 } 6915 } 6916 LOG_CLI((BSL_META_U(unit, 6917 "Hardware SER memories tested: %u\n"),test_count)); 6918 return SOC_E_NONE; 6919 } 6920 6921 /* 6922 * Function: 6923 * soc_katana2_ser_mem_test 6924 * Purpose: 6925 * Performs a SER test on a single TR2 memory 6926 * Parameters: 6927 * unit - (IN) Device Number 6928 * mem - (IN) The memory to test 6929 * test_type - (IN) How many indices in the memory to test 6930 */ 6931 int soc_katana2_ser_mem_test(int unit, soc_mem_t mem, _soc_ser_test_t test_type, 6932 int cmd) 6933 { 6934 int group, table, i, rv; 6935 _soc_katana2_parity_info_t *info; 6936 soc_mem_t memTable; 6937 soc_port_t block_port=0; 6938 soc_block_t blk; 6939 int testErrors = 0; 6940 ser_test_data_t test_data; 6941 soc_field_t test_field; 6942 uint32 tmp_entry[SOC_MAX_MEM_WORDS], field_data[SOC_MAX_MEM_FIELD_WORDS]; 6943 /*Prevent compiler error for common function signature.*/ 6944 (void) cmd; 6945 sal_memset(&test_data, 0, sizeof(test_data)); 6946 _soc_katana2_mem_rename(&mem); 6947 /*TCAM_test*/ 6948 if (_soc_kt2_tcam_ser_info[unit] != NULL) { 6949 for (i = 0; _soc_kt2_tcam_ser_info[unit][i].mem != INVALIDm; i++) { 6950 if (_soc_kt2_tcam_ser_info[unit][i].mem == mem) { 6951 if (mem == L3_DEFIPm) { 6952 test_field = VALID0f; 6953 } else if (mem == L3_DEFIP_PAIR_128m) { 6954 test_field = VALID0_LWRf; 6955 } else { 6956 test_field = VALIDf; 6957 } 6958 soc_ser_create_test_data(unit, tmp_entry, field_data, 6959 SER_RANGE_ENABLEr, i, INVALIDf, mem, 6960 test_field, MEM_BLOCK_ANY, REG_PORT_ANY, 6961 _SOC_ACC_TYPE_PIPE_ANY, 0, &test_data); 6962 rv = ser_test_mem(unit, 0, &test_data, test_type, &testErrors); 6963 6964 if (rv != SOC_E_NONE) { 6965 LOG_CLI((BSL_META_U(unit, 6966 "Error during TCAM test. Aborting.\n"))); 6967 return rv; 6968 } 6969 } 6970 } 6971 } 6972 6973 /*H/W memory Test*/ 6974 for (group = 0; _soc_katana2_parity_route_blocks[group].cmic_bit; group++) { 6975 info = _soc_katana2_parity_route_blocks[group].info; 6976 6977 if (_soc_katana2_parity_route_blocks[group].blocktype == SOC_BLK_MMU) { 6978 continue; 6979 } else { 6980 SOC_BLOCK_ITER(unit, blk,_soc_katana2_parity_route_blocks[group].blocktype) { 6981 if (_soc_katana2_parity_block_port(unit, blk, &block_port) < 0) { 6982 continue; 6983 } 6984 6985 for (table = 0; info[table].type != _SOC_PARITY_TYPE_NONE; table++) { 6986 memTable = info[table].mem; 6987 if (memTable == INVALIDm) { 6988 continue; 6989 } 6990 if (memTable == mem) { 6991 soc_ser_create_test_data(unit, tmp_entry, field_data, 6992 info[table].enable_reg, 6993 SOC_INVALID_TCAM_PARITY_BIT, 6994 info[table].enable_field, 6995 mem, EVEN_PARITYf, blk, 6996 block_port, 6997 _SOC_ACC_TYPE_PIPE_ANY, 0, 6998 &test_data); 6999 rv = ser_test_mem(unit, 0, &test_data, test_type, 7000 &testErrors); 7001 if (rv != SOC_E_NONE) { 7002 LOG_CLI((BSL_META_U(unit, 7003 "Error during H/W test. Aborting.\n"))); 7004 return rv; 7005 } 7006 } 7007 } 7008 } 7009 } 7010 } 7011 if (testErrors == 0) { 7012 LOG_CLI((BSL_META_U(unit, 7013 "SER Test passed on unit: %d for memory %s\n "), 7014 unit, SOC_MEM_NAME(unit,mem))); 7015 } else { 7016 LOG_CLI((BSL_META_U(unit, 7017 "SER Test failed on unit: %d for memory %s\n"), 7018 unit, SOC_MEM_NAME(unit,mem))); 7019 return SOC_E_MEMORY; 7020 } 7021 return SOC_E_NONE; 7022 } 7023 7024 /* 7025 * Function: 7026 * soc_katana2_set_test_field 7027 * Purpose: 7028 * Specified the field of a memory . It is used to inject a parity error in the entry. 7029 * Parameters: 7030 * memory - (IN) The memory id 7031 * field - (IN) The field id of the memory 7032 */ 7033 STATIC 7034 soc_field_t soc_katana2_set_test_field(soc_mem_t memory, soc_field_t field) 7035 { 7036 soc_field_t test_field = field; 7037 7038 switch(memory) { 7039 /* TCAM fields*/ 7040 case MY_STATION_TCAMm: 7041 case L2_USER_ENTRYm: 7042 case VLAN_SUBNETm: 7043 case CPU_COS_MAPm: 7044 case EFP_TCAMm: 7045 case VFP_TCAMm: 7046 case FP_UDF_TCAMm: 7047 case SUBPORT_TAG_TO_PP_PORT_MAPm: 7048 case L3_TUNNELm: 7049 test_field = MASKf; 7050 break; 7051 case L3_DEFIPm: 7052 test_field = MASK0f; 7053 break; 7054 case L3_DEFIP_PAIR_128m: 7055 test_field = MASK0_LWRf; 7056 break; 7057 case FP_TCAMm: 7058 case FP_GLOBAL_MASK_TCAMm: 7059 test_field = VALIDf; 7060 break; 7061 default: 7062 break; 7063 } 7064 7065 return test_field; 7066 } 7067 7068 7069 /* 7070 * Function: 7071 * soc_katana2_ser_test 7072 * Purpose: 7073 * Performs a SER test on all TR2 Memories 7074 * Parameters: 7075 * unit - (IN) Device Number 7076 * test_type - (IN) Determines how comprehensive of a test to run 7077 */ 7078 int soc_katana2_ser_test(int unit, _soc_ser_test_t test_type) { 7079 int i, rv; 7080 int numTCAMErr = 0; 7081 int numNACKErr = 0; 7082 soc_field_t tcam_field; 7083 7084 /*This is a NACK test for hardware-monitored memories*/ 7085 rv = _soc_katana2_mem_nack_error_test(unit, test_type, &numNACKErr); 7086 if (rv != SOC_E_NONE) { 7087 LOG_CLI((BSL_META_U(unit, 7088 "TR 144 test failed. Error during H/W test. Aborting.\n"))); 7089 return rv; 7090 } 7091 /*This is a NACK test for TCAM memories*/ 7092 /*Test each TCAM memory*/ 7093 if (_soc_kt2_tcam_ser_info[unit] != NULL) { 7094 for (i = 0; _soc_kt2_tcam_ser_info[unit][i].mem != INVALIDm; i++) { 7095 7096 tcam_field = soc_katana2_set_test_field(_soc_kt2_tcam_ser_info[unit][i].mem,INVALIDf); 7097 7098 /* coverity[negative_returns : FALSE] */ 7099 rv = ser_test_mem_pipe(unit, SER_RANGE_ENABLEr, i, -1, 7100 _soc_kt2_tcam_ser_info[unit][i].mem, tcam_field, 7101 test_type, MEM_BLOCK_ANY, REG_PORT_ANY, -1, 7102 &numTCAMErr); 7103 if (rv != SOC_E_NONE) { 7104 LOG_CLI((BSL_META_U(unit, 7105 "TR 144 test failed. Error during TCAM test. Aborting.\n"))); 7106 return rv; 7107 } 7108 } 7109 } 7110 7111 if((numTCAMErr != 0) || (numNACKErr != 0)) { 7112 LOG_CLI((BSL_META_U(unit, 7113 "TR 144 test failed.\n"))); 7114 } 7115 7116 LOG_CLI((BSL_META_U(unit, 7117 "Total H/W parity errors on unit %d: %d\n"),unit, numNACKErr)); 7118 LOG_CLI((BSL_META_U(unit, 7119 "Total TCAM errors on unit %d: %d\n"), unit, numTCAMErr)); 7120 return SOC_E_NONE; 7121 } 7122 7123 STATIC soc_error_t 7124 _soc_katana2_ser_mem_info_get(int unit, soc_mem_t mem, 7125 void** ser_mem_info) 7126 { 7127 int i, j; 7128 _soc_katana2_parity_info_t *info = NULL; 7129 7130 for (i = 0; _soc_katana2_parity_route_blocks[i].cmic_bit != 0; i++) { 7131 info = _soc_katana2_parity_route_blocks[i].info; 7132 if (_soc_katana2_parity_route_blocks[i].blocktype == SOC_BLK_MMU) { 7133 continue; 7134 } 7135 for (j = 0; info[j].type != _SOC_PARITY_TYPE_NONE; j++) { 7136 if (info[j].mem != INVALIDm && info[j].mem == mem) { 7137 *ser_mem_info = &info[j]; 7138 return SOC_E_NONE; 7139 } 7140 } 7141 } 7142 return SOC_E_UNAVAIL; 7143 } 7144 7145 STATIC soc_error_t 7146 _soc_katana2_tcam_ser_mem_info_get(int unit, soc_mem_t mem, 7147 int * index_p) 7148 { 7149 int i; 7150 _soc_generic_ser_info_t *tcams = _soc_kt2_tcam_ser_info[unit]; 7151 7152 for (i = 0; tcams[i].mem != INVALIDm; i++) { 7153 if (tcams[i].mem == mem) { 7154 *index_p = i; 7155 return SOC_E_NONE; 7156 } 7157 } 7158 return SOC_E_UNAVAIL; 7159 } 7160 7161 /* 7162 * Function: 7163 * soc_katana2_ser_error_injection_support 7164 * Purpose: 7165 * Checks if a memory is supported by error injection interface 7166 * 7167 * Parameters: 7168 * unit - (IN) Device Number 7169 * memory - (IN) Test data required for SER test 7170 * pipe - (IN) How many indices to test for each memory 7171 * 7172 * Returns: 7173 * SOC_E_NONE if memory / reg is supported, SOC_E_UNAVAIL if unsupported 7174 */ 7175 soc_error_t 7176 soc_katana2_ser_error_injection_support(int unit, soc_mem_t mem, 7177 int pipe) 7178 { 7179 int rv = SOC_E_UNAVAIL; 7180 void * ser_mem_info = NULL; 7181 int tcam_idx = 0; 7182 7183 rv = _soc_katana2_ser_mem_info_get(unit, mem, &ser_mem_info); 7184 if (rv == SOC_E_NONE) { 7185 return rv; 7186 } 7187 7188 rv = _soc_katana2_tcam_ser_mem_info_get(unit, mem, &tcam_idx); 7189 if (rv == SOC_E_NONE) { 7190 return rv; 7191 } 7192 7193 return rv; 7194 } 7195 7196 /* 7197 * Function: 7198 * soc_katana2_ser_inject_error 7199 * Purpose: 7200 * Performs a SER test on a single TR2 memory 7201 * Parameters: 7202 * unit - (IN) Device Number 7203 * mem - (IN) The memory to test 7204 * test_type - (IN) How many indices in the memory to test 7205 */ 7206 int soc_katana2_ser_inject_error(int unit, uint32 flags, 7207 soc_mem_t mem, int pipeTarget, 7208 int block, int index) 7209 { 7210 int group, table, i; 7211 _soc_katana2_parity_info_t *info; 7212 soc_mem_t memTable; 7213 soc_port_t block_port = 0; 7214 soc_block_t blk; 7215 ser_test_data_t test_data; 7216 soc_field_t field; 7217 uint32 tmp_entry[SOC_MAX_MEM_WORDS], fieldData[SOC_MAX_MEM_FIELD_WORDS]; 7218 sal_memset(&test_data, 0, sizeof(test_data)); 7219 _soc_katana2_mem_rename(&mem); 7220 7221 /* Check if memory support ser inject operation */ 7222 if (ser_katana2_test_fun.injection_support) { 7223 SOC_IF_ERROR_RETURN( 7224 soc_katana2_ser_error_injection_support(unit, mem, pipeTarget)); 7225 } 7226 7227 /*TCAM_test*/ 7228 if (_soc_kt2_tcam_ser_info[unit] != NULL) { 7229 for (i = 0; _soc_kt2_tcam_ser_info[unit][i].mem != INVALIDm; i++) { 7230 if (_soc_kt2_tcam_ser_info[unit][i].mem == mem) { 7231 if (mem == L3_DEFIPm) { 7232 field = VALID0f; 7233 } else if (mem == L3_DEFIP_PAIR_128m) { 7234 field = VALID0_LWRf; 7235 } else { 7236 field = VALIDf; 7237 } 7238 soc_ser_create_test_data(unit, tmp_entry, fieldData, 7239 SER_RANGE_ENABLEr, i, VALIDf, mem, 7240 field, MEM_BLOCK_ANY, REG_PORT_ANY, 7241 _SOC_ACC_TYPE_PIPE_ANY, index, &test_data); 7242 /*Read the memory for successful injection*/ 7243 SOC_IF_ERROR_RETURN(ser_test_mem_read(unit, 0, &test_data)); 7244 /*Disable parity*/ 7245 SOC_IF_ERROR_RETURN(_ser_test_parity_control(unit, &test_data, 0)); 7246 /*Inject error*/ 7247 SOC_IF_ERROR_RETURN(soc_ser_test_inject_full(unit, flags, &test_data)); 7248 /*Enable parity*/ 7249 SOC_IF_ERROR_RETURN(_ser_test_parity_control(unit, &test_data, 1)); 7250 return SOC_E_NONE; 7251 } 7252 } 7253 } 7254 7255 /*H/W memory Test*/ 7256 for (group = 0; _soc_katana2_parity_route_blocks[group].cmic_bit; group++) { 7257 info = _soc_katana2_parity_route_blocks[group].info; 7258 if (_soc_katana2_parity_route_blocks[group].blocktype == SOC_BLK_MMU) { 7259 continue; 7260 } else { 7261 SOC_BLOCK_ITER(unit, blk,_soc_katana2_parity_route_blocks[group].blocktype) { 7262 if (_soc_katana2_parity_block_port(unit, blk, &block_port) < 0) { 7263 continue; 7264 } 7265 for (table = 0; info[table].type != _SOC_PARITY_TYPE_NONE; table++) { 7266 memTable = info[table].mem; 7267 if (memTable == INVALIDm) { 7268 continue; 7269 } 7270 if (memTable == mem) { 7271 if((blk == block) || (block == MEM_BLOCK_ANY)) { 7272 /*Inject error*/ 7273 if (mem == SOURCE_TRUNK_MAP_TABLEm) { 7274 field = ECCf; 7275 flags |= SOC_INJECT_ERROR_2BIT_ECC; 7276 } else if (mem == PORT_TABm || mem == LPORT_TABm) { 7277 field = ECC_0f; 7278 flags |= SOC_INJECT_ERROR_2BIT_ECC; 7279 } else { 7280 field = EVEN_PARITYf; 7281 } 7282 soc_ser_create_test_data(unit, tmp_entry, fieldData, 7283 info[table].enable_reg, 7284 SOC_INVALID_TCAM_PARITY_BIT, 7285 info[table].enable_field, 7286 mem, field, blk, 7287 block_port, 7288 _SOC_ACC_TYPE_PIPE_ANY, index, 7289 &test_data); 7290 /*Read the memory for successful injection*/ 7291 SOC_IF_ERROR_RETURN(ser_test_mem_read(unit, 0, &test_data)); 7292 /*Disable parity*/ 7293 SOC_IF_ERROR_RETURN(_ser_test_parity_control(unit, &test_data, 0)); 7294 /*Inject error*/ 7295 SOC_IF_ERROR_RETURN(soc_ser_test_inject_full(unit, flags, &test_data)); 7296 /*Enable parity*/ 7297 SOC_IF_ERROR_RETURN(_ser_test_parity_control(unit, &test_data, 1)); 7298 } 7299 } 7300 } 7301 } 7302 } 7303 } 7304 return SOC_E_NONE; 7305 } 7306 7307 STATIC soc_kt2_oam_handler_t kt2_oam_handler[SOC_MAX_NUM_DEVICES] = {NULL}; 7308 STATIC soc_kt2_linkphy_handler_t kt2_linkphy_handler[SOC_MAX_NUM_DEVICES] = {NULL}; 7309 STATIC soc_kt2_oam_ser_handler_t kt2_oam_ser_handler[SOC_MAX_NUM_DEVICES] = {NULL}; 7310 7311 extern int _soc_ddr_shmoo_prepare_for_shmoo(int unit, int ci); 7312 typedef struct _soc_katana2_ci_parama_s { 7313 uint32 speed; 7314 uint32 grade; 7315 } _soc_katana2_ci_parama_t; 7316 7317 /* 56450 TDM sequence */ 7318 7319 /* Same for 56456,55450,55455 */ 7320 /* Cfg 0 is not advertised: Total 16(Actually 17 0..16) Configs */ 7321 #define BCM56450_DEVICE_ID_OFFSET_CFG 0 7322 #define BCM56450_DEVICE_ID_DEFAULT_CFG 4 7323 #define BCM56450_DEVICE_ID_MAX_CFG 16 7324 7325 /* Same for 56457 Total 10 Configs(1..10 <== 16+1=17..26) */ 7326 #define BCM56452_DEVICE_ID_OFFSET_CFG 16 7327 #define BCM56452_DEVICE_ID_DEFAULT_CFG 17 7328 #define BCM56452_DEVICE_ID_MAX_CFG 26 7329 7330 /* Same for 56458 Total 2 Configs(1..2) 26+1=27..28 */ 7331 #define BCM56454_DEVICE_ID_OFFSET_CFG 26 7332 #define BCM56454_DEVICE_ID_DEFAULT_CFG 27 7333 #define BCM56454_DEVICE_ID_MAX_CFG 28 7334 7335 /* Total 1 Configs(1..1) 28+1=29..29 */ 7336 #define BCM56455_DEVICE_ID_OFFSET_CFG 28 7337 #define BCM56455_DEVICE_ID_DEFAULT_CFG 29 7338 #define BCM56455_DEVICE_ID_MAX_CFG 30 7339 7340 /* Same for 56450(First 16(0..15) ) Total 18(0..17) <== 30+0=30..47 Configs */ 7341 #define BCM56248_DEVICE_ID_OFFSET_CFG 31 7342 #define BCM56248_DEVICE_ID_DEFAULT_CFG 35 7343 #define BCM56248_DEVICE_ID_MAX_CFG 48 7344 7345 /* typedef uint32 mxqspeeds_t[KT2_MAX_MXQBLOCKS][KT2_MAX_MXQPORTS_PER_BLOCK]; */ 7346 7347 const static mxqspeeds_t mxqspeeds_s = { 7348 {10000,2500,0,2500},{10000,2500,0,2500},{10000,2500,0,2500}, 7349 {10000,2500,0,2500},{10000,2500,0,2500},{10000,2500,0,2500}, 7350 {13000,2500,0,2500},{13000,2500,0,2500}, 7351 {21000,10000,0,2500},{21000,10000,0,2500}, 7352 {2500,0,0,0}}; 7353 mxqspeeds_t *mxqspeeds[SOC_MAX_NUM_DEVICES]={NULL}; 7354 7355 uint32 kt2_current_tdm[256]={0}; 7356 uint32 kt2_current_tdm_size=0; 7357 7358 int mxqblock_max_startaddr[KT2_MAX_MXQBLOCKS]={0}; 7359 int mxqblock_max_endaddr[KT2_MAX_MXQBLOCKS]={0}; 7360 7361 static uint8 old_tdm_no[SOC_MAX_NUM_DEVICES]={0}; 7362 7363 /* bcm5645x_config=0 */ 7364 /* Deprecated=0 24x GE + 16*2.5GE(HG-LIT) */ 7365 /* 24xGE(1..24) + 16*2.5GE(HG-LIT)(25..40) */ 7366 static uint32 kt2_tdm_56450config_deprecated0[88]= { 7367 1, 5, 9, 13, 17, 21,25,26,27,28,KT2_LPBK_PORT, 7368 2, 6, 10, 14, 18, 22,35,38,32,29,KT2_CMIC_PORT, 7369 3, 7, 11, 15, 19, 23,36,39,33,30,KT2_IDLE, 7370 4, 8, 12, 16, 20, 24,37,40,34,31,KT2_IDLE1, 7371 KT2_IDLE1, KT2_IDLE,KT2_IDLE,KT2_IDLE,KT2_IDLE,KT2_IDLE,KT2_IDLE,25,26,27,28, 7372 KT2_LPBK_PORT,KT2_IDLE,KT2_IDLE,KT2_IDLE,KT2_IDLE,KT2_IDLE,KT2_IDLE,35,38,32,29, 7373 KT2_CMIC_PORT,KT2_IDLE,KT2_IDLE,KT2_IDLE,KT2_IDLE,KT2_IDLE,KT2_IDLE,36,39,33,30, 7374 KT2_IDLE, KT2_IDLE,KT2_IDLE,KT2_IDLE,KT2_IDLE,KT2_IDLE,KT2_IDLE,37,40,34,31 7375 }; 7376 7377 /* 24xGE(1..24) + 16*2.5GE(HG-LIT)(25..40) */ 7378 /* typedef uint32 kt2_speed_t[KT2_MAX_PHYSICAL_PORTS]; */ 7379 const static kt2_speed_t kt2_tdm_56450speed_deprecated0= { 7380 2500,2500,2500,2500, /* 1 - 4 */ 7381 2500,2500,2500,2500, /* 5 - 8 */ 7382 2500,2500,2500,2500, /* 9 - 12 */ 7383 2500,2500,2500,2500, /* 13 - 16 */ 7384 2500,2500,2500,2500, /* 17 - 20 */ 7385 2500,2500,2500,2500, /* 21 - 24 */ 7386 2500,2500,2500,2500, /* 25 - 28 */ 7387 2500,2500,2500,2500, /* 29 - 32 */ 7388 2500,2500,2500,2500, /* 33 - 36 */ 7389 2500,2500,2500,2500}; /* 37 - 40 */ 7390 const static soc_port_details_t kt2_port_details_deprecated0[]={ 7391 {1,24,1,GE_PORT,2500}, 7392 {25,40,1,HGL_PORT|STK_PORT,2500}, 7393 {0,0,0,0} /* End */ 7394 }; 7395 7396 const static uint32 kt2_tdm_56450AA_ref[88]= { 7397 1, 5, 9, 13, 17, 21,25,26,27,28,KT2_LPBK_PORT, 7398 2, 6, 10, 14, 18, 22,35,38,32,29,KT2_CMIC_PORT, 7399 3, 7, 11, 15, 19, 23,36,39,33,30,KT2_IDLE, 7400 4, 8, 12, 16, 20, 24,37,40,34,31,KT2_IDLE1, 7401 KT2_IDLE1, 1, 5, 9, 13, 17,21,25,26,27,28, 7402 KT2_LPBK_PORT, 2, 6, 10, 14, 18,22,35,38,32,29, 7403 KT2_CMIC_PORT, 3, 7, 11, 15, 19,23,36,39,33,30, 7404 KT2_IDLE, 4, 8, 12, 16, 20,24,37,40,34,31 7405 }; 7406 7407 7408 const static uint32 kt2_tdm_56450A_ref[88]= { 7409 1, 5, 9, 27, 30, 13,17,21,33,28,KT2_LPBK_PORT, 7410 1, 5, 9, 27, 30, 13,17,21,33,28,KT2_CMIC_PORT, 7411 1, 5, 9, 27, 30, 13,17,21,33,28,KT2_OLP_PORT, 7412 1, 5, 9, 27, 30, 13,17,21,33,28,KT2_IDLE1, 7413 KT2_IDLE1, 1, 5, 9, 27, 30,13,17,21,33,28, 7414 KT2_LPBK_PORT, 1, 5, 9, 27, 30,13,17,21,33,28, 7415 KT2_CMIC_PORT, 1, 5, 9, 27, 30,13,17,21,33,28, 7416 KT2_OLP_PORT, 1, 5, 9, 27, 30,13,17,21,33,28 7417 }; 7418 7419 #define BCM_KT2_TDM_A1_NUM_SLOTS 176 7420 const static uint32 kt2_tdm_56450A1_ref[BCM_KT2_TDM_A1_NUM_SLOTS]= { 7421 26, 9, 27, 28, 5, 13, 25, 28, 27, 26, KT2_LPBK_PORT, 7422 1, 9, 27, 28, 25, 13, 26, 28, 27, KT2_CMIC_PORT, KT2_OLP_PORT, 7423 28, 27, 9, 25, 26, 13, 28, 27, KT2_IDLE1, KT2_IDLE1, 28, 7424 25, 27, 9, 26, 28, 13, 3, 27, 7, 25, 28, 7425 26, 9, 27, 28, 6, 13, 25, 28, 27, 26, KT2_LPBK_PORT, 7426 2, 9, 27, 28, 25, 13, 26, 28, 27, KT2_CMIC_PORT, KT2_OLP_PORT, 7427 28, 27, 9, 25, 26, 13, 28, 27, KT2_IDLE, KT2_IDLE, 28, 7428 25, 27, 9, 26, 28, 13, 4, 27, 8, 25, 28, 7429 26, 9, 27, 28, 5, 13, 25, 28, 27, 26, KT2_LPBK_PORT, 7430 1, 9, 27, 28, 25, 13, 26, 28, 27, KT2_CMIC_PORT, KT2_OLP_PORT, 7431 28, 27, 9, 25, 26, 13, 28, 27, KT2_IDLE, KT2_IDLE, 28, 7432 25, 27, 9, 26, 28, 13, 3, 27, 7, 25, 28, 7433 26, 9, 27, 28, 6, 13, 25, 28, 27, 26, KT2_LPBK_PORT, 7434 2, 9, 27, 28, 25, 13, 26, 28, 27, KT2_CMIC_PORT, KT2_OLP_PORT, 7435 28, 27, 9, 25, 26, 13, 28, 27, KT2_IDLE, KT2_IDLE, 28, 7436 25, 27, 9, 26, 28, 13, 4, 27, 8, 25, 28 7437 }; 7438 7439 #define BCM_KT2_TDM_A1A_NUM_SLOTS 108 7440 const static uint32 kt2_tdm_56450A1A_ref[BCM_KT2_TDM_A1A_NUM_SLOTS]= { 7441 1, 25, 27, 28, 11, 26, KT2_IDLE, 27, 28, 7442 KT2_OLP_PORT, 25, KT2_CMIC_PORT, 27, 28, 26, 15, 19, 27, 7443 28, 25, KT2_IDLE1, KT2_IDLE1, 27, 26, 28, 20, 23, 7444 27, 25, 28, 8, KT2_CMIC_PORT, 26, 27, 28, KT2_LPBK_PORT, 7445 2, 25, 27, 28, 12, 26, 16, 27, 28, 7446 KT2_OLP_PORT, 25, 4, 27, 28, 26, 17, 21, 27, 7447 28, 25, 5, 9, 27, 26, 28, KT2_IDLE1, KT2_IDLE1, 7448 27, 25, 28, KT2_CMIC_PORT, 13, 26, 27, 28, KT2_LPBK_PORT, 7449 3, 25, 27, 28, 14, 26, 18, 27, 28, 7450 KT2_OLP_PORT, 25, 6, 27, 28, 26, KT2_CMIC_PORT, 22, 27, 7451 28, 25, 7, KT2_IDLE, 27, 26, 28, KT2_IDLE, 24, 7452 27, 25, 28, 10, KT2_IDLE, 26, 27, 28, KT2_LPBK_PORT 7453 }; 7454 7455 const static uint32 kt2_tdm_56450A2_ref[216]= { 7456 KT2_IDLE1, 28, 9, 25, 21, 26, 17, 27, 13, 7457 KT2_CMIC_PORT, 28, 1, 25, 9, 26, 21, 27, 17, 7458 KT2_OLP_PORT, 28, 13, 25, KT2_LPBK_PORT, 26, 9, 27, 21, 7459 2, 28, 17, 25, 13, 26, KT2_CMIC_PORT, 27, 9, 7460 3, 28, 21, 25, 17, 26, 13, 27, 7, 7461 9, 28, 4, 25, 21, 26, 17, 27, 13, 7462 KT2_OLP_PORT, 28, 9, 25, KT2_LPBK_PORT, 26, 21, 27, 17, 7463 13, 28, 5, 25, 9, 26, KT2_CMIC_PORT, 27, 21, 7464 17, 28, 13, 25, 6, 26, 9, 27, KT2_IDLE, 7465 21, 28, 17, 25, 13, 26, KT2_LPBK_PORT, 27, 9, 7466 KT2_OLP_PORT, 28, 21, 25, 17, 26, 13, 27, 8, 7467 9, 28, 21, 25, 17, 26, 13, 27, KT2_IDLE, 7468 KT2_IDLE, 28, 9, 25, 21, 26, 17, 27, 13, 7469 KT2_CMIC_PORT, 28, 1, 25, 9, 26, 21, 27, 17, 7470 KT2_OLP_PORT, 28, 13, 25, KT2_LPBK_PORT, 26, 9, 27, 21, 7471 2, 28, 17, 25, 13, 26, KT2_CMIC_PORT, 27, 9, 7472 3, 28, 21, 25, 17, 26, 13, 27, 7, 7473 9, 28, 4, 25, 21, 26, 17, 27, 13, 7474 KT2_OLP_PORT, 28, 9, 25, KT2_LPBK_PORT, 26, 21, 27, 17, 7475 13, 28, 5, 25, 9, 26, KT2_CMIC_PORT, 27, 21, 7476 17, 28, 13, 25, 6, 26, 9, 27, KT2_IDLE, 7477 21, 28, 17, 25, 13, 26, KT2_LPBK_PORT, 27, 9, 7478 KT2_OLP_PORT, 28, 21, 25, 17, 26, 13, 27, 8, 7479 9, 28, 21, 25, 17, 26, 13, 27, KT2_IDLE1 7480 }; 7481 7482 const static uint32 kt2_tdm_56450A3_ref[88] = { 7483 KT2_IDLE1, 9, 28, 13, 25, 17, 5, 21, 28, 27, KT2_LPBK_PORT, 7484 25, 9, 28, 13, 1, 17, 25, 21, 28, 27, KT2_OLP_PORT, 7485 KT2_CMIC_PORT, 9, 28, 13, 25, 17, 6, 21, 28, 27, KT2_IDLE, 7486 25, 9, 28, 13, 2, 17, 25, 21, 28, 27, KT2_LPBK_PORT, 7487 KT2_OLP_PORT, 9, 28, 13, 25, 17, 7, 21, 28, 27, KT2_IDLE, 7488 25, 9, 28, 13, 3, 17, 25, 21, 28, 27, KT2_LPBK_PORT, 7489 KT2_CMIC_PORT, 9, 28, 13, 25, 17, 8, 21, 28, 27, KT2_OLP_PORT, 7490 25, 9, 28, 13, 4, 17, 25, 21, 28, 27, KT2_IDLE1 7491 }; 7492 7493 #define BCM_KT2_TDM_A4_NUM_SLOTS 88 7494 const static uint32 kt2_tdm_56450A4_ref[88] = { 7495 KT2_IDLE1, 1, 28, 27, 25, 17, 26, 13, 28, 27, KT2_OLP_PORT, 7496 KT2_LPBK_PORT, 25, 28, 27, 26, 17, 9, 14, 28, 27, 25, 7497 KT2_IDLE, 26, 28, 27, 5, 17, 10, 25, 28, 27, 26, 7498 KT2_CMIC_PORT, 2, 28, 27, 6, 17, 25, 26, 28, 27, KT2_LPBK_PORT, 7499 KT2_IDLE, 3, 28, 27, 25, 17, 26, 15, 28, 27, KT2_OLP_PORT, 7500 KT2_IDLE, 25, 28, 27, 26, 17, 11, 16, 28, 27, 25, 7501 KT2_LPBK_PORT, 26, 28, 27, 7, 17, 12, 25, 28, 27, 26, 7502 KT2_CMIC_PORT, 4, 28, 27, 8, 17, 25, 26, 28, 27, KT2_IDLE1 7503 }; 7504 7505 const static uint32 kt2_tdm_56450F_ref[88]= { 7506 KT2_IDLE, 25, KT2_IDLE, 1, KT2_IDLE, 5, KT2_IDLE, 26, 27, 28, KT2_LPBK_PORT, 7507 KT2_IDLE, 35, KT2_IDLE, 2, KT2_IDLE, 6, KT2_IDLE, 38, KT2_IDLE, 28, KT2_CMIC_PORT, 7508 KT2_IDLE, 36, KT2_IDLE, 3, KT2_IDLE, 7, KT2_IDLE, 39, KT2_IDLE, 28, KT2_IDLE, 7509 KT2_IDLE, 37, KT2_IDLE, 4, KT2_IDLE, 8, KT2_IDLE, 40, KT2_IDLE, 28, KT2_IDLE1, 7510 KT2_IDLE1, KT2_IDLE, 25, KT2_IDLE, 1, KT2_IDLE, 5, KT2_IDLE, 26, 27, 28, 7511 KT2_LPBK_PORT, KT2_IDLE, 35, KT2_IDLE, 2, KT2_IDLE, 6, KT2_IDLE, 38, KT2_IDLE, 28, 7512 KT2_CMIC_PORT, KT2_IDLE, 36, KT2_IDLE, 3, KT2_IDLE, 7, KT2_IDLE, 39, KT2_IDLE, 28, 7513 KT2_IDLE, KT2_IDLE, 37, KT2_IDLE, 4, KT2_IDLE, 8, KT2_IDLE, 40, KT2_IDLE, 28, 7514 }; 7515 7516 const static uint32 kt2_tdm_56452B_new_ref[90]= { 7517 KT2_CMIC_PORT,1,27, 28,5, KT2_LPBK_PORT, 25, 26, 28, 7518 27, 2,KT2_IDLE, 28,6, 25, KT2_CMIC_PORT, 38, 27, 7519 28, 3,KT2_LPBK_PORT,25,7, 28, 27, 39, KT2_IDLE, 7520 28, 4,25, 40,8, 27, 28, 26, 5, 7521 25, 1,28, 27,6, 2, 28, 38, 25, 7522 KT2_CMIC_PORT,3,27, 28,7, KT2_LPBK_PORT, 25, 39, 28, 7523 27, 4,KT2_IDLE1, KT2_IDLE1,28,8, 25, 40, 27, 7524 28, 1,KT2_IDLE, 25,5,28, 27, 26, 6, 7525 28, 2,25, 38,7,27, 28,39, KT2_LPBK_PORT, 7526 25, 3,28, 27,8,4, 28, 40, 25 7527 }; 7528 7529 const static uint32 kt2_tdm_56452B1_ref[60]= { 7530 1, 27, 25, 28, 5, 1, 27, KT2_IDLE, 28, KT2_IDLE, 7531 25, 27, 5, 28, 1, KT2_CMIC_PORT, 27, 25, 28, KT2_LPBK_PORT, 7532 5, 27, 1, 28, KT2_IDLE, 25, 27, KT2_OLP_PORT, 28, 5, 7533 1, 27, 25, 28, KT2_IDLE1, KT2_IDLE1, 27, 5, 28, 1, 7534 25, 27, KT2_CMIC_PORT, 28, 5, 1, 27, 25, 28, KT2_LPBK_PORT, 7535 KT2_IDLE, 27, 5, 28, 1, 25, 27, KT2_OLP_PORT, 28, 5 7536 }; 7537 7538 const static uint32 kt2_tdm_56452B2_ref[72]= { 7539 KT2_IDLE1, 9, 13, 28, 26, 21, 17, 30, KT2_LPBK_PORT, 7540 1, 10, 14, 28, 26, 21, 17, 30, KT2_CMIC_PORT, 7541 2, 11, 15, 28, 26, 21, 17, 30, KT2_OLP_PORT, 7542 3, 12, 16, 28, 26, 21, 17, 30, 4, 7543 5, 9, 13, 28, 26, 21, 17, 30, KT2_LPBK_PORT, 7544 6, 10, 14, 28, 26, 21, 17, 30, KT2_CMIC_PORT, 7545 7, 11, 15, 28, 26, 21, 17, 30, KT2_OLP_PORT, 7546 8, 12, 16, 28, 26, 21, 17, 30, KT2_IDLE1 7547 }; 7548 7549 7550 const static uint32 kt2_tdm_56455C_ref[84]= { 7551 KT2_LPBK_PORT, 9, 17, 25, 26, 27, 28, 7552 KT2_CMIC_PORT, 10, 18, 25, 26, 27, 28, 7553 1, KT2_LPBK_PORT, 19, 25, 26, 27, 28, 7554 2, 11, 20, 25, 26, 27, 28, 7555 3, 12, KT2_LPBK_PORT, 25, 26, 27, 28, 7556 4, 13, KT2_CMIC_PORT, 25, 26, 27, 28, 7557 KT2_LPBK_PORT, 14, 21, 25, 26, 27, 28, 7558 KT2_IDLE, 15, 22, 25, 26, 27, 28, 7559 5, KT2_LPBK_PORT, 23, 25, 26, 27, 28, 7560 6, KT2_CMIC_PORT, 24, 25, 26, 27, 28, 7561 7, 16, KT2_LPBK_PORT, 25, 26, 27, 28, 7562 8, KT2_IDLE1, KT2_IDLE1, 25, 26, 27, 28 7563 }; 7564 7565 const static uint32 kt2_tdm_56452C1_ref[64]= { 7566 1, 9, KT2_LPBK_PORT, 20, 27, 28, 25, 26, 7567 2, 10, 17, KT2_OLP_PORT, 27, 28, 25, 26, 7568 3, 11, KT2_CMIC_PORT, 21, 27, 28, 25, 26, 7569 4, 12, 18, 22, 27, 28, 25, 26, 7570 5, 13, KT2_LPBK_PORT, 23, 27, 28, 25, 26, 7571 6, 14, 19, KT2_OLP_PORT, 27, 28, 25, 26, 7572 7, 15, KT2_CMIC_PORT, 24, 27, 28, 25, 26, 7573 8, 16, KT2_IDLE1, KT2_IDLE1, 27, 28, 25, 26 7574 }; 7575 7576 #if 0 7577 const static uint32 kt2_tdm_56454D_ref[20] = { 7578 KT2_IDLE1, 1, 5, 27, 28, 7579 2, 6, 27, 28, KT2_LPBK_PORT, 7580 3, 7, 27, 28, KT2_CMIC_PORT, 7581 4, 8, 27, 28, KT2_IDLE1, 7582 }; 7583 #endif 7584 7585 const static uint32 kt2_tdm_56454D1_ref[40] = { 7586 1, 5, 27, 28, KT2_LPBK_PORT, 7587 1, 5, 27, 28, KT2_CMIC_PORT, 7588 1, 5, 27, 28, KT2_OLP_PORT, 7589 1, 5, 27, 28, KT2_IDLE1, 7590 KT2_IDLE1, 1, 5, 27, 28, 7591 KT2_LPBK_PORT, 1, 5, 27, 28, 7592 KT2_CMIC_PORT, 1, 5, 27, 28, 7593 KT2_OLP_PORT, 1, 5, 27, 28 7594 }; 7595 const static uint32 kt2_tdm_56248D2_ref[40] = { 7596 1, 9, 13, 27, KT2_LPBK_PORT, 7597 2, 10, 17, 28, KT2_CMIC_PORT, 7598 3, 11, 21, 29, KT2_OLP_PORT, 7599 4, 12, 25, KT2_IDLE, KT2_IDLE1, 7600 KT2_IDLE1, 9, 13, 27, 5, 7601 KT2_LPBK_PORT, 10, 17, 28, 6, 7602 KT2_CMIC_PORT, 11, 21, 29, 7, 7603 KT2_OLP_PORT, 12, 25, KT2_IDLE, 8 7604 }; 7605 7606 7607 7608 7609 /* bcm5645x_config=1 */ 7610 7611 /* 8 x F.XAUI(1,,5,9,13,17,21,25,26) 2 x W10G = 2 x XFI (27,28) */ 7612 static uint32 kt2_tdm_A_56450_1[88]={0}; /* Will be filled-up at run time */ 7613 const static kt2_speed_t kt2_speed_56450_1 = { 7614 10000,0000,0000,0000, /* 1 - 4 */ 7615 10000,0000,0000,0000, /* 5 - 8 */ 7616 10000,0000,0000,0000, /* 9 - 12 */ 7617 10000,0000,0000,0000, /* 13 - 16 */ 7618 10000,0000,0000,0000, /* 17 - 20 */ 7619 10000,0000,0000,0000, /* 21 - 24 */ 7620 10000,10000,10000,10000, /* 25 - 28 */ 7621 0000,0000,0000,0000, /* 29 - 32 */ 7622 0000,0000,0000,0000, /* 33 - 36 */ 7623 0000,0000,0000,0000}; /* 37 - 40 */ 7624 7625 /* Config=1 8xF.XAUI 2xW10G */ 7626 /* 2 XFI */ 7627 const static soc_port_details_t kt2_port_details_56450_1[]={ 7628 {1,25,4,XE_PORT,10000}, /* 7 F.XAUI */ 7629 {26,28,1,XE_PORT,10000},/* 1 F.XAUI + 2 XFI */ 7630 {0,0,0,0} /* End */ 7631 }; 7632 7633 /* bcm5645x_config=2 */ 7634 7635 /* 7 x F.XAUI + 1 x XAUI(1,5,9,13,17,21,25,26) 2 x W10G = 2 x XFI (27,28) */ 7636 static uint32 kt2_tdm_A_56450_2[88]={0}; /* Will be filled-up at run time */ 7637 const static kt2_speed_t kt2_speed_56450_2 = { 7638 10000,0000,0000,0000, /* 1 - 4 */ 7639 10000,0000,0000,0000, /* 5 - 8 */ 7640 10000,0000,0000,0000, /* 9 - 12 */ 7641 10000,0000,0000,0000, /* 13 - 16 */ 7642 10000,0000,0000,0000, /* 17 - 20 */ 7643 10000,0000,0000,0000, /* 21 - 24 */ 7644 10000,10000,10000,10000, /* 25 - 28 */ 7645 0000,0000,0000,0000, /* 29 - 32 */ 7646 0000,0000,0000,0000, /* 33 - 36 */ 7647 0000,0000,0000,2500}; /* 37 - 40 */ 7648 /* Config=2 7 x F.XAUI + 1 x XAUI + 2 x W10G */ 7649 /* 2XFI + OLP */ 7650 const static soc_port_details_t kt2_port_details_56450_2[]={ 7651 {1,25,4,XE_PORT,10000}, /* 7 F.XAUI */ 7652 {26,28,1,XE_PORT,10000},/* 1 XAUI Fixed + 2 XFI*/ 7653 {40,40,1,OLP_PORT,2500},/* OLP */ 7654 {0,0,0,0} /* End */ 7655 }; 7656 7657 /* bcm5645x_config=3 */ 7658 7659 /* 7 x F.XAUI(1,5,9,13,17,21,25) 1xW10G + 1xW20G (3 x XFI)(27,28,30) */ 7660 static uint32 kt2_tdm_A_56450_3[88]={0}; /* Will be filled-up at run time */ 7661 const static kt2_speed_t kt2_speed_56450_3= { 7662 10000,0000,0000,0000, /* 1 - 4 */ 7663 10000,0000,0000,0000, /* 5 - 8 */ 7664 10000,0000,0000,0000, /* 9 - 12 */ 7665 10000,0000,0000,0000, /* 13 - 16 */ 7666 10000,0000,0000,0000, /* 17 - 20 */ 7667 10000,0000,0000,0000, /* 21 - 24 */ 7668 10000,0000,10000,10000, /* 25 - 28 */ 7669 0000,10000,0000,0000, /* 29 - 32 */ 7670 0000,0000,0000,0000, /* 33 - 36 */ 7671 0000,0000,0000,2500}; /* 37 - 40 */ 7672 /* Config=3 7 x F.XAUI 1 x W10G + 1 x W20G */ 7673 /* 3XFI + OLP */ 7674 const static soc_port_details_t kt2_port_details_56450_3[]={ 7675 {1,25,4,XE_PORT,10000}, /* 7 F.XAUI */ 7676 {27,28,1,XE_PORT,10000},/* 2 XFI */ 7677 {30,30,1,XE_PORT,10000},/* 1 XFI */ 7678 {40,40,1,OLP_PORT,2500},/* OLP */ 7679 {0,0,0,0} /* End */ 7680 }; 7681 7682 /* bcm5645x_config=4 */ 7683 7684 /* 6 x F.XAUI(1,5,9,13,17,21) 2 x W20G (4 x XFI) 27,33,28,30 */ 7685 static uint32 kt2_tdm_A_56450_4[88]={0}; 7686 const static kt2_speed_t kt2_speed_56450_4= { 7687 10000,0000,0000,0000, /* 1 - 4 */ 7688 10000,0000,0000,0000, /* 5 - 8 */ 7689 10000,0000,0000,0000, /* 9 - 12 */ 7690 10000,0000,0000,0000, /* 13 - 16 */ 7691 10000,0000,0000,0000, /* 17 - 20 */ 7692 10000,0000,0000,0000, /* 21 - 24 */ 7693 0000,0000,10000,10000, /* 25 - 28 */ 7694 0000,10000,0000,0000, /* 29 - 32 */ 7695 10000,0000,0000,0000, /* 33 - 36 */ 7696 0000,0000,0000,2500}; /* 37 - 40 */ 7697 /* Config=4 6 x F.XAUI 2 x W20G */ 7698 /* 4XFI + OLP */ 7699 const static soc_port_details_t kt2_port_details_56450_4[]={ 7700 {1,21,4,XE_PORT,10000}, /* 6 F.XAUI */ 7701 {27,28,1,XE_PORT,10000},/* 2 XFI */ 7702 {30,33,3,XE_PORT,10000}, /* 2 XFI */ 7703 {40,40,1,OLP_PORT,2500},/* OLP */ 7704 {0,0,0,0} /* End */ 7705 }; 7706 7707 /* bcm5645x_config=5 */ 7708 7709 /* 4 x F.XAUI(1,5,9,13) 1 x W40G(27,25,36,33) + 1 x W20G (28,30) */ 7710 /* MXQ8:27,33 MXQ9:28,30 */ 7711 /* ##MXQ7:26,39 Indirectly used */ 7712 /* ##MXQ6(25,36) Not used */ 7713 static uint32 kt2_tdm_A_56450_5[88]={0}; 7714 const static kt2_speed_t kt2_speed_56450_5= { 7715 10000,0000,0000,0000, /* 1 - 4 */ 7716 10000,0000,0000,0000, /* 5 - 8 */ 7717 10000,0000,0000,0000, /* 9 - 12 */ 7718 10000,0000,0000,0000, /* 13 - 16 */ 7719 0000,0000,0000,0000, /* 17 - 20 */ 7720 0000,0000,0000,0000, /* 21 - 24 */ 7721 10000,0000,10000,10000, /* 25 - 28 */ 7722 0000,10000,0000,0000, /* 29 - 32 */ 7723 10000,0000,0000,10000, /* 33 - 36 */ 7724 0000,0000,10000,2500}; /* 37 - 40 */ 7725 /* Config=5 4 x F.XAUI 1 x W20G + 1 x W40G */ 7726 /* 6XFI + OLP */ 7727 const static soc_port_details_t kt2_port_details_56450_5[]={ 7728 {1,13,4,XE_PORT,10000}, /* 4 F.XAUI */ 7729 {25,36,11,XE_PORT,10000}, /* 2 XFI */ 7730 {27,33,6,XE_PORT,10000}, /* 2 XFI */ 7731 {28,30,2,XE_PORT,10000}, /* 4 XFI */ 7732 {40,40,1,OLP_PORT,2500}, /* OLP */ 7733 {0,0,0,0} /* End */ 7734 }; 7735 7736 /* bcm5645x_config=6 */ 7737 7738 /* 2 x F.XAUI (1,5) 2 x W40G=8 XFI (25,36,26,39,27,33,28,30) */ 7739 /* MXQ6=25,36 MXQ7=26,39 MXQ8=27,33 MXQ9=28,30 */ 7740 static uint32 kt2_tdm_A_56450_6[88]={0}; 7741 const static kt2_speed_t kt2_speed_56450_6= { 7742 10000,0000,0000,0000, /* 1 - 4 */ 7743 10000,0000,0000,0000, /* 5 - 8 */ 7744 0000,0000,0000,0000, /* 9 - 12 */ 7745 0000,0000,0000,0000, /* 13 - 16 */ 7746 0000,0000,0000,0000, /* 17 - 20 */ 7747 0000,0000,0000,0000, /* 21 - 24 */ 7748 10000,10000,10000,10000, /* 25 - 28 */ 7749 0000,10000,0000,0000, /* 29 - 32 */ 7750 10000,0000,0000,10000, /* 33 - 36 */ 7751 0000,0000,10000,/* 2500 */ 0000}; /* 37 - 40 */ 7752 /* Config=6 2 x F.XAUI 2 x W40G */ 7753 /* 8XFI + OLP */ 7754 /* ##MXQ7:26,39 Indirectly used */ 7755 /* ##MXQ6(25,36) Indirectly used */ 7756 const static soc_port_details_t kt2_port_details_56450_6[]={ 7757 {1,5,4,XE_PORT,10000}, 7758 {25,28,1,XE_PORT,10000}, 7759 {30,39,3,XE_PORT,10000}, 7760 /* {40,40,1,OLP_PORT,2500}, */ /* OLP */ 7761 {0,0,0,0} /* End */ 7762 }; 7763 7764 /* bcm5645x_config=7 */ 7765 7766 /* 24GE + 1 F.XAUI W20G(27,33) + W20G (28,30, 26, 39) */ 7767 7768 static uint32 kt2_tdm_A_56450_7[88]={0}; 7769 const static kt2_speed_t kt2_speed_56450_7= { 7770 1000,1000,1000,1000, /* 1 - 4 */ 7771 1000,1000,1000,1000, /* 5 - 8 */ 7772 1000,1000,1000,1000, /* 9 - 12 */ 7773 1000,1000,1000,1000, /* 13 - 16 */ 7774 1000,1000,1000,1000, /* 17 - 20 */ 7775 1000,1000,1000,1000, /* 21 - 24 */ 7776 10000,10000,10000,10000, /* 25 - 28 */ 7777 0000,10000,0000,0000, /* 29 - 32 */ 7778 10000,0000,0000,0000, /* 33 - 36 */ 7779 0000,0000,10000,0000}; /* 37 - 40 */ 7780 /* Config=7 24 x GE 1 x F.XAUI 1 x W40G 1 x W20G */ 7781 /* SP3 */ 7782 /* Assuming 6 XFI + OLP */ 7783 /* MXQ6:25,36 MXQ8:27,33 MXQ9:28,30 ##MXQ7(26,39) Not used*/ 7784 const static soc_port_details_t kt2_port_details_56450_7[]={ 7785 {1,24,1,GE_PORT,1000}, 7786 {25,25,1,XE_PORT,10000} , /* 1 F.XAUI */ 7787 {27,33,6,XE_PORT,10000}, /* 1 F.XAUI */ 7788 {28,30,2,XE_PORT,10000}, /* 2 XFI */ 7789 {26,39,13,XE_PORT,10000}, /* 1 XFI */ 7790 {0,0,0,0} /* End */ 7791 }; 7792 7793 /* bcm5645x_config=8 */ 7794 7795 /* 8x GE + 2x F-XAUI + 2x HG13 + 2x HG21 + OLP */ 7796 static uint32 kt2_tdm_A1_56450_8[BCM_KT2_TDM_A1_NUM_SLOTS]={0}; 7797 const static kt2_speed_t kt2_speed_56450_8= { 7798 1000,1000,1000,1000, /* 1 - 4 */ 7799 1000,1000,1000,1000, /* 5 - 8 */ 7800 10000,0000,0000,0000, /* 9 - 12 */ 7801 10000,0000,0000,0000, /* 13 - 16 */ 7802 0000,0000,0000,0000, /* 17 - 20 */ 7803 0000,0000,0000,0000, /* 21 - 24 */ 7804 13000,13000,21000,21000, /* 25 - 28 */ 7805 0000,0000,0000,0000, /* 29 - 32 */ 7806 0000,0000,0000,0000, /* 33 - 36 */ 7807 0000,0000,0000,2500}; /* 37 - 40 */ 7808 /* Config=8 8 x GE 2 x F.XAUI 1 x F.HG13 1 x X.HG13 2 x W21G */ 7809 const static soc_port_details_t kt2_port_details_56450_8[]={ 7810 {1,8,1,GE_PORT,1000}, 7811 {9,13,4,XE_PORT,10000}, /* 2 F.XAUI */ 7812 {25,26,1,HG_PORT|STK_PORT,13000}, /* 26 Fixed XAUI */ 7813 {27,28,1,HG_PORT|STK_PORT,21000}, 7814 {40,40,1,OLP_PORT,2500},/* OLP */ 7815 {0,0,0,0} /* End */ 7816 }; 7817 7818 /* bcm5645x_config=9 */ 7819 7820 /* 24x GE + 2x HG13 + 2x HG21 + OLP */ 7821 static uint32 kt2_tdm_A1A_56450_9[108]={0}; 7822 const static kt2_speed_t kt2_speed_56450_9= { 7823 1000,1000,1000,1000, /* 1 - 4 */ 7824 1000,1000,1000,1000, /* 5 - 8 */ 7825 1000,1000,1000,1000, /* 9 - 12 */ 7826 1000,1000,1000,1000, /* 13 - 16 */ 7827 1000,1000,1000,1000, /* 17 - 20 */ 7828 1000,1000,1000,1000, /* 21 - 24 */ 7829 13000,13000,21000,21000, /* 25 - 28 */ 7830 0000,0000,0000,0000, /* 29 - 32 */ 7831 0000,0000,0000,0000, /* 33 - 36 */ 7832 0000,0000,0000,2500}; /* 37 - 40 */ 7833 /* Config=9 24 x GE 1 x F.HG13 1 x X.HG13 2 x W21G */ 7834 const static soc_port_details_t kt2_port_details_56450_9[]={ 7835 {1,24,1,GE_PORT,1000}, 7836 {25,26,1,HG_PORT|STK_PORT,13000}, /* 26 Fixed XAUI */ 7837 {27,28,1,HG_PORT|STK_PORT,21000}, 7838 {40,40,1,OLP_PORT,2500},/* OLP */ 7839 {0,0,0,0} /* End */ 7840 }; 7841 7842 7843 /* bcm5645x_config=10 */ 7844 7845 /* 8 x 1GbE(1..8) + 4 x F.XAUI(9,13,17,21) + 7846 1 x HG[13] + 1 x F.HG[13](25,26) 2 x W13G(27,28)(NO OLP) */ 7847 static uint32 kt2_tdm_A2_56450_10[216]={0}; 7848 const static kt2_speed_t kt2_speed_56450_10= { 7849 1000,1000,1000,1000, /* 1 - 4 */ 7850 1000,1000,1000,1000, /* 5 - 8 */ 7851 10000,0000,0000,0000, /* 9 - 12 */ 7852 10000,0000,0000,0000, /* 13 - 16 */ 7853 10000,0000,0000,0000, /* 17 - 20 */ 7854 10000,0000,0000,0000, /* 21 - 24 */ 7855 13000,13000,13000,13000, /* 25 - 28 */ 7856 0000,0000,0000,0000, /* 29 - 32 */ 7857 0000,0000,0000,0000, /* 33 - 36 */ 7858 0000,0000,0000,0000}; /* 37 - 40 */ 7859 /* Config=10 8 x GE 4 x F.XAUI 2 x F.HG13 2 x W13G */ 7860 const static soc_port_details_t kt2_port_details_56450_10[]={ 7861 {1,8,1,GE_PORT,1000}, 7862 {9,21,4,XE_PORT,10000}, /* 4 F.XAUI */ 7863 {25,28,1,HG_PORT|STK_PORT,13000}, 7864 {0,0,0,0} /* End */ 7865 }; 7866 7867 /* bcm5645x_config=11 */ 7868 7869 /* 8 x 1GbE(1..8) + 4 x F.XAUI(9,13,17,21) + 1 x HG[13] + */ 7870 /* 1 x F.HG[13](25,26) 2 x W13G(27,28) */ 7871 static uint32 kt2_tdm_A2_56450_11[216]={0}; 7872 const static kt2_speed_t kt2_speed_56450_11= { 7873 1000,1000,1000,1000, /* 1 - 4 */ 7874 1000,1000,1000,1000, /* 5 - 8 */ 7875 10000,0000,0000,0000, /* 9 - 12 */ 7876 10000,0000,0000,0000, /* 13 - 16 */ 7877 10000,0000,0000,0000, /* 17 - 20 */ 7878 10000,0000,0000,0000, /* 21 - 24 */ 7879 13000,13000,13000,13000, /* 25 - 28 */ 7880 0000,0000,0000,0000, /* 29 - 32 */ 7881 0000,0000,0000,0000, /* 33 - 36 */ 7882 0000,0000,0000,2500}; /* 37 - 40 */ 7883 /* Config=11 8 x 1GbE + 4 x F.XAUI + 1 x F.HG[13] + 1 x X.HG[13] 2 x W13G */ 7884 const static soc_port_details_t kt2_port_details_56450_11[]={ 7885 {1,8,1,GE_PORT,1000}, 7886 {9,21,4,XE_PORT,10000}, /* 4 F.XAUI */ 7887 {25,28,1,HG_PORT|STK_PORT,13000}, 7888 {40,40,1,OLP_PORT,2500},/* OLP */ 7889 {0,0,0,0} /* End */ 7890 }; 7891 7892 /* bcm5645x_config=12 */ 7893 7894 /* 8 x 1GbE(1..8) + 4 x F.XAUI(9,13,17,21) + 1 x HG[13](25) */ 7895 /* 1x W13G(27) 1xW21G(28) */ 7896 static uint32 kt2_tdm_A3_56450_12[88]={0}; 7897 const static kt2_speed_t kt2_speed_56450_12= { 7898 1000,1000,1000,1000, /* 1 - 4 */ 7899 1000,1000,1000,1000, /* 5 - 8 */ 7900 10000,0000,0000,0000, /* 9 - 12 */ 7901 10000,0000,0000,0000, /* 13 - 16 */ 7902 10000,0000,0000,0000, /* 17 - 20 */ 7903 10000,0000,0000,0000, /* 21 - 24 */ 7904 13000,0000,13000,21000, /* 25 - 28 */ 7905 0000,0000,0000,0000, /* 29 - 32 */ 7906 0000,0000,0000,0000, /* 33 - 36 */ 7907 0000,0000,0000,2500}; /* 37 - 40 */ 7908 /* Config=12 8 x 1GbE + 4 x F.XAUI + 1 x F.HG[13] 1 x W13G 1 x W21G*/ 7909 /* 2xHG13 + 1xHG21 */ 7910 const static soc_port_details_t kt2_port_details_56450_12[]={ 7911 {1,8,1,GE_PORT,1000}, 7912 {9,21,4,XE_PORT,10000}, /* 4 F.XAUI */ 7913 {25,27,2,HG_PORT|STK_PORT,13000}, 7914 {28,28,1,HG_PORT|STK_PORT,21000}, 7915 {40,40,1,OLP_PORT,2500},/* OLP */ 7916 {0,0,0,0} /* End */ 7917 }; 7918 7919 /* bcm5645x_config=13 */ 7920 7921 /* 8 x 1GbE(1..8) + 4 x F.XAUI(9,13,17,21) + 2 x W21G(27,28) */ 7922 static uint32 kt2_tdm_A2_56450_13[216]={0}; 7923 const static kt2_speed_t kt2_speed_56450_13= { 7924 1000,1000,1000,1000, /* 1 - 4 */ 7925 1000,1000,1000,1000, /* 5 - 8 */ 7926 10000,0000,0000,0000, /* 9 - 12 */ 7927 10000,0000,0000,0000, /* 13 - 16 */ 7928 10000,0000,0000,0000, /* 17 - 20 */ 7929 10000,0000,0000,0000, /* 21 - 24 */ 7930 0000,0000,21000,21000, /* 25 - 28 */ 7931 0000,0000,0000,0000, /* 29 - 32 */ 7932 0000,0000,0000,0000, /* 33 - 36 */ 7933 0000,0000,0000,2500}; /* 37 - 40 */ 7934 /* Config=13 8 x 1GbE + 4 x F.XAUI + 2 x W21G*/ 7935 const static soc_port_details_t kt2_port_details_56450_13[]={ 7936 {1,8,1,GE_PORT,1000}, 7937 {9,21,4,XE_PORT,10000}, 7938 {27,28,1,HG_PORT|STK_PORT,21000}, 7939 {40,40,1,OLP_PORT,2500},/* OLP */ 7940 {0,0,0,0} /* End */ 7941 }; 7942 7943 7944 /* bcm5645x_config=14 */ 7945 7946 /* 8 x 1GbE(1..8) + 2 x F.XAUI(9,13) + 2xHG13(25,26) 2 x W20G(27,28) */ 7947 static uint32 kt2_tdm_A1_56450_14[BCM_KT2_TDM_A1_NUM_SLOTS]={0}; 7948 const static kt2_speed_t kt2_speed_56450_14= { 7949 1000,1000,1000,1000, /* 1 - 4 */ 7950 1000,1000,1000,1000, /* 5 - 8 */ 7951 10000,0000,0000,0000, /* 9 - 12 */ 7952 10000,0000,0000,0000, /* 13 - 16 */ 7953 0000,0000,0000,0000, /* 17 - 20 */ 7954 0000,0000,0000,0000, /* 21 - 24 */ 7955 13000,13000,21000,21000, /* 25 - 28 */ 7956 0000,0000,0000,0000, /* 29 - 32 */ 7957 0000,0000,0000,0000, /* 33 - 36 */ 7958 0000,0000,0000,2500}; /* 37 - 40 */ 7959 /* Config=14 8 x 1GbE + 2 x F.XAUI + 1 x F.HG[13] + 1 x X.HG[13] 2 x W20G */ 7960 /* TN2 */ 7961 /* Actually 4 XFI but treating as 2HG13 only!! */ 7962 const static soc_port_details_t kt2_port_details_56450_14[]={ 7963 {1,8,1,GE_PORT,1000}, 7964 {9,13,4,XE_PORT,10000}, /* 2 F.XAUI */ 7965 {25,26,1,HG_PORT|STK_PORT,13000}, 7966 {27,28,1,HG_PORT|STK_PORT,21000}, 7967 {40,40,1,OLP_PORT,2500},/* OLP */ 7968 {0,0,0,0} /* End */ 7969 }; 7970 7971 /* bcm5645x_config=15 */ 7972 7973 /* 16 x 1GbE(1..16) + 1 x F.XAUI(17) + 2xHG13(25,26) 2 x W21G(27,28) */ 7974 static uint32 kt2_tdm_A4_56450_15[216]={0}; 7975 const static kt2_speed_t kt2_speed_56450_15= { 7976 1000,1000,1000,1000, /* 1 .- 4 */ 7977 1000,1000,1000,1000, /* 5 - 8 */ 7978 1000,1000,1000,1000, /* 9 - 12 */ 7979 1000,1000,1000,1000, /* 13 - 16 */ 7980 10000,0000,0000,0000, /* 17 - 20 */ 7981 0000,0000,0000,0000, /* 21 - 24 */ 7982 13000,13000,13000,13000, /* 25 - 28 */ 7983 0000,0000,0000,0000, /* 29 - 32 */ 7984 0000,0000,0000,0000, /* 33 - 36 */ 7985 0000,0000,0000,2500}; /* 37 - 40 */ 7986 /* Config=15 16 x 1GbE + 1 x F.XAUI + 1 x F.HG[13] + 1 x X.HG[13] 2 x W20G */ 7987 /* TN2 */ 7988 /* Assuming 4 XFI */ 7989 const static soc_port_details_t kt2_port_details_56450_15[]={ 7990 {1,16,1,GE_PORT,1000}, 7991 {17,17,1,XE_PORT,10000}, 7992 {25,28,1,HG_PORT|STK_PORT,13000}, 7993 {40,40,1,OLP_PORT,2500},/* OLP */ 7994 {0,0,0,0} /* End */ 7995 }; 7996 7997 /* bcm5645x_config=16 */ 7998 7999 /* 16x2.5G(1..8, 25.35,36,37 26,38,39,40) + 1xXAUI(28) */ 8000 static uint32 kt2_tdm_F_56450_16[88]={0}; 8001 const static kt2_speed_t kt2_speed_56450_16= { 8002 2500,2500,2500,2500, /* 1 .- 4 */ 8003 2500,2500,2500,2500, /* 5 - 8 */ 8004 0000,0000,0000,0000, /* 9 - 12 */ 8005 0000,0000,0000,0000, /* 13 - 16 */ 8006 0000,0000,0000,0000, /* 17 - 20 */ 8007 0000,0000,0000,0000, /* 21 - 24 */ 8008 2500,2500,1000,10000, /* 25 - 28 */ 8009 0000,0000,0000,0000, /* 29 - 32 */ 8010 0000,0000,2500,2500, /* 33 - 36 */ 8011 2500,2500,2500,2500}; /* 37 - 40 */ 8012 8013 const static soc_port_details_t kt2_port_details_56450_16[]={ 8014 {1,8,1,GE_PORT,2500}, 8015 {25,26,1,GE_PORT,2500}, 8016 {27,27,1,GE_PORT,1000}, 8017 {35,40,1,GE_PORT,2500}, 8018 {28,28,1,XE_PORT,10000}, 8019 {0,0,0,0} /* End */ 8020 }; 8021 8022 /* 24x GE + 4x HG[13] /4x XAUI / 16x 2.5G */ 8023 static uint32 kt2_tdm_C_56452_1[84]={0}; 8024 const static kt2_speed_t kt2_speed_56452_1= { 8025 1000,1000,1000,1000, /* 1 .- 4 */ 8026 1000,1000,1000,1000, /* 5 - 8 */ 8027 1000,1000,1000,1000, /* 9 - 12 */ 8028 1000,1000,1000,1000, /* 13 - 16 */ 8029 1000,1000,1000,1000, /* 17 - 20 */ 8030 1000,1000,1000,1000, /* 21 - 24 */ 8031 13000,13000,13000,13000, /* 25 - 28 */ 8032 0000,0000,0000,0000, /* 29 - 32 */ 8033 0000,0000,0000,0000, /* 33 - 36 */ 8034 0000,0000,0000,0000}; /* 37 - 40 */ 8035 const static soc_port_details_t kt2_port_details_56452_1[]={ 8036 {1,24,1,GE_PORT,1000}, 8037 {25,28,1,HG_PORT|STK_PORT,13000}, 8038 {0,0,0,0} /* End */ 8039 }; 8040 /* 24x GE + 4x HG[13] /4x XAUI / 16x 2.5G + OLP */ 8041 static uint32 kt2_tdm_C1_56452_2[64]={0}; 8042 const static kt2_speed_t kt2_speed_56452_2= { 8043 1000,1000,1000,1000, /* 1 .- 4 */ 8044 1000,1000,1000,1000, /* 5 - 8 */ 8045 1000,1000,1000,1000, /* 9 - 12 */ 8046 1000,1000,1000,1000, /* 13 - 16 */ 8047 1000,1000,1000,1000, /* 17 - 20 */ 8048 1000,1000,1000,1000, /* 21 - 24 */ 8049 13000,13000,13000,13000, /* 25 - 28 */ 8050 0000,0000,0000,0000, /* 29 - 32 */ 8051 0000,0000,0000,0000, /* 33 - 36 */ 8052 0000,0000,0000,2500}; /* 37 - 40 */ 8053 const static soc_port_details_t kt2_port_details_56452_2[]={ 8054 {1,24,1,GE_PORT,1000}, 8055 {25,28,1,HG_PORT|STK_PORT,13000}, 8056 {40,40,1,OLP_PORT,2500},/* OLP */ 8057 {0,0,0,0} /* End */ 8058 }; 8059 8060 /* 2x XE + 4x HG[13] /4x XAUI / 16x 2.5G */ 8061 static uint32 kt2_tdm_C1_56452_3[64]={0}; 8062 const static kt2_speed_t kt2_speed_56452_3= { 8063 10000,0000,0000,0000, /* 1 .- 4 */ 8064 10000,0000,0000,0000, /* 5 - 8 */ 8065 0000,0000,0000,0000, /* 9 - 12 */ 8066 0000,0000,0000,0000, /* 13 - 16 */ 8067 0000,0000,0000,0000, /* 17 - 20 */ 8068 0000,0000,0000,0000, /* 21 - 24 */ 8069 13000,13000,13000,13000, /* 25 - 28 */ 8070 0000,0000,0000,0000, /* 29 - 32 */ 8071 0000,0000,0000,0000, /* 33 - 36 */ 8072 0000,0000,0000,0000}; /* 37 - 40 */ 8073 const static soc_port_details_t kt2_port_details_56452_3[]={ 8074 {1,5,4,XE_PORT,10000}, 8075 {25,28,1,HG_PORT|STK_PORT,13000}, 8076 {0,0,0,0} /* End */ 8077 }; 8078 8079 /* 2x XE + 4x HG[13] /4x XAUI / 16x 2.5G + OLP*/ 8080 static uint32 kt2_tdm_C1_56452_4[64]={0}; 8081 const static kt2_speed_t kt2_speed_56452_4= { 8082 10000,0000,0000,0000, /* 1 .- 4 */ 8083 10000,0000,0000,0000, /* 5 - 8 */ 8084 0000,0000,0000,0000, /* 9 - 12 */ 8085 0000,0000,0000,0000, /* 13 - 16 */ 8086 0000,0000,0000,0000, /* 17 - 20 */ 8087 0000,0000,0000,0000, /* 21 - 24 */ 8088 13000,13000,13000,13000, /* 25 - 28 */ 8089 0000,0000,0000,0000, /* 29 - 32 */ 8090 0000,0000,0000,0000, /* 33 - 36 */ 8091 0000,0000,0000,2500}; /* 37 - 40 */ 8092 const static soc_port_details_t kt2_port_details_56452_4[]={ 8093 {1,5,4,XE_PORT,10000}, 8094 {25,28,1,HG_PORT|STK_PORT,13000}, 8095 {40,40,1,OLP_PORT,2500},/* OLP */ 8096 {0,0,0,0} /* End */ 8097 }; 8098 8099 /* 24x GE + HG[13] - HG[13] HG[21] + OLP */ 8100 static uint32 kt2_tdm_B_56452_5[90]={0}; 8101 const static kt2_speed_t kt2_speed_56452_5= { 8102 1000,1000,1000,1000, /* 1 .- 4 */ 8103 1000,1000,1000,1000, /* 5 - 8 */ 8104 1000,1000,1000,1000, /* 9 - 12 */ 8105 1000,1000,1000,1000, /* 13 - 16 */ 8106 1000,1000,1000,1000, /* 17 - 20 */ 8107 1000,1000,1000,1000, /* 21 - 24 */ 8108 13000,0000,13000,21000, /* 25 - 28 */ 8109 0000,0000,0000,0000, /* 29 - 32 */ 8110 0000,0000,0000,0000, /* 33 - 36 */ 8111 0000,0000,0000,2500}; /* 37 - 40 */ 8112 const static soc_port_details_t kt2_port_details_56452_5[]={ 8113 {1,24,1,GE_PORT,1000}, 8114 {25,27,2,HG_PORT|STK_PORT,13000}, 8115 {28,28,1,HG_PORT|STK_PORT,21000}, 8116 {40,40,1,OLP_PORT,2500},/* OLP */ 8117 {0,0,0,0} /* End */ 8118 }; 8119 /* 24x GE + - - HG[21] HG[21] + OLP */ 8120 static uint32 kt2_tdm_B1_56452_6[60]={0}; 8121 const static kt2_speed_t kt2_speed_56452_6= { 8122 1000,1000,1000,1000, /* 1 .- 4 */ 8123 1000,1000,1000,1000, /* 5 - 8 */ 8124 1000,1000,1000,1000, /* 9 - 12 */ 8125 1000,1000,1000,1000, /* 13 - 16 */ 8126 1000,1000,1000,1000, /* 17 - 20 */ 8127 1000,1000,1000,1000, /* 21 - 24 */ 8128 0000,0000,21000,21000, /* 25 - 28 */ 8129 0000,0000,0000,0000, /* 29 - 32 */ 8130 0000,0000,0000,0000, /* 33 - 36 */ 8131 0000,0000,0000,2500}; /* 37 - 40 */ 8132 const static soc_port_details_t kt2_port_details_56452_6[]={ 8133 {1,24,1,GE_PORT,1000}, 8134 {27,28,1,HG_PORT|STK_PORT,21000}, 8135 {40,40,1,OLP_PORT,2500},/* OLP */ 8136 {0,0,0,0} /* End */ 8137 }; 8138 8139 /* 24x GE + - - HG[13] HG[21] + OLP */ 8140 static uint32 kt2_tdm_B_56452_7[90]={0}; 8141 const static kt2_speed_t kt2_speed_56452_7= { 8142 1000,1000,1000,1000, /* 1 .- 4 */ 8143 1000,1000,1000,1000, /* 5 - 8 */ 8144 1000,1000,1000,1000, /* 9 - 12 */ 8145 1000,1000,1000,1000, /* 13 - 16 */ 8146 1000,1000,1000,1000, /* 17 - 20 */ 8147 1000,1000,1000,1000, /* 21 - 24 */ 8148 0000,0000,13000,21000, /* 25 - 28 */ 8149 0000,0000,0000,0000, /* 29 - 32 */ 8150 0000,0000,0000,0000, /* 33 - 36 */ 8151 0000,0000,0000,0000}; /* 37 - 40 */ 8152 const static soc_port_details_t kt2_port_details_56452_7[]={ 8153 {1,24,1,GE_PORT,1000}, 8154 {27,27,1,HG_PORT|STK_PORT,13000}, 8155 {28,28,1,HG_PORT|STK_PORT,21000}, 8156 {0,0,0,0} /* End */ 8157 }; 8158 8159 /* 16*2.5G(XC0,XC1,XC6,XC7) + 1*1G debug port(WC0) +1*10G/20G DXAUI port(WC1)*/ 8160 static uint32 kt2_tdm_B_56452_8[90]={0}; 8161 const static kt2_speed_t kt2_speed_56452_8= { 8162 2500,2500,2500,2500, /* 1 .- 4 */ 8163 2500,2500,2500,2500, /* 5 - 8 */ 8164 0000,0000,0000,0000, /* 9 - 12 */ 8165 0000,0000,0000,0000, /* 13 - 16 */ 8166 0000,0000,0000,0000, /* 17 - 20 */ 8167 0000,0000,0000,0000, /* 21 - 24 */ 8168 2500,2500,13000,20000, /* 25 - 28 */ 8169 0000,0000,0000,0000, /* 29 - 32 */ 8170 0000,0000,2500,2500, /* 33 - 36 */ 8171 2500,2500,2500,2500}; /* 37 - 40 */ 8172 const static soc_port_details_t kt2_port_details_56452_8[]={ 8173 {1,8,1,GE_PORT,2500}, 8174 {25,26,1,GE_PORT,2500}, 8175 {27,27,1,HG_PORT|STK_PORT,13000}, 8176 {28,28,1,XE_PORT,20000}, 8177 {35,40,1,GE_PORT,2500}, 8178 {0,0,0,0} /* End */ 8179 }; 8180 8181 /* 2x XE + HG[13] - HG[21] HG[21] + OLP */ 8182 static uint32 kt2_tdm_B1_56452_9[60]={0}; 8183 const static kt2_speed_t kt2_speed_56452_9= { 8184 10000,0000,0000,0000, /* 1 .- 4 */ 8185 10000,0000,0000,0000, /* 5 - 8 */ 8186 0000,0000,0000,0000, /* 9 - 12 */ 8187 0000,0000,0000,0000, /* 13 - 16 */ 8188 0000,0000,0000,0000, /* 17 - 20 */ 8189 0000,0000,0000,0000, /* 21 - 24 */ 8190 13000,0000,21000,21000, /* 25 - 28 */ 8191 0000,0000,0000,0000, /* 29 - 32 */ 8192 0000,0000,0000,0000, /* 33 - 36 */ 8193 0000,0000,0000,2500}; /* 37 - 40 */ 8194 const static soc_port_details_t kt2_port_details_56452_9[]={ 8195 {1,5,4,XE_PORT,10000}, 8196 {25,25,1,HG_PORT|STK_PORT,13000}, 8197 {27,28,1,HG_PORT|STK_PORT,21000}, 8198 {40,40,1,OLP_PORT,2500},/* OLP */ 8199 {0,0,0,0} /* End */ 8200 }; 8201 8202 /* 8x GE + 8x2.5GE + 2xXAUI - XAUI + 2xXFI + OLP */ 8203 static uint32 kt2_tdm_B2_56452_10[72]={0}; 8204 const static kt2_speed_t kt2_speed_56452_10= { 8205 1000,1000,1000,1000, /* 1 .- 4 */ 8206 1000,1000,1000,1000, /* 5 - 8 */ 8207 2500,2500,2500,2500, /* 9 - 12 */ 8208 2500,2500,2500,2500, /* 13 - 16 */ 8209 10000,0000,0000,0000, /* 17 - 20 */ 8210 10000,0000,0000,0000, /* 21 - 24 */ 8211 0000,10000,0000,10000, /* 25 - 28 */ 8212 0000,10000,0000,0000, /* 29 - 32 */ 8213 0000,0000,0000,0000, /* 33 - 36 */ 8214 0000,0000,0000,2500}; /* 37 - 40 */ 8215 const static soc_port_details_t kt2_port_details_56452_10[]={ 8216 {1,8,1,GE_PORT,1000}, 8217 {9,16,1,GE_PORT,2500}, 8218 {17,21,4,XE_PORT,10000}, 8219 {26,26,1,XE_PORT,10000}, 8220 {28,30,2,XE_PORT,10000}, 8221 {40,40,1,OLP_PORT,2500},/* OLP */ 8222 {0,0,0,0} /* End */ 8223 }; 8224 8225 8226 8227 /* 2xF.XAUI + 2xHG13 */ 8228 static uint32 kt2_tdm_D1_56454_1[20]={0}; 8229 const static kt2_speed_t kt2_speed_56454_1= { 8230 10000,0000,0000,0000, /* 1 .- 4 */ 8231 10000,0000,0000,0000, /* 5 - 8 */ 8232 0000,0000,0000,0000, /* 9 - 12 */ 8233 0000,0000,0000,0000, /* 13 - 16 */ 8234 0000,0000,0000,0000, /* 17 - 20 */ 8235 0000,0000,0000,0000, /* 21 - 24 */ 8236 0000,0000,13000,13000, /* 25 - 28 */ 8237 0000,0000,0000,0000, /* 29 - 32 */ 8238 0000,0000,0000,0000, /* 33 - 36 */ 8239 0000,0000,0000,2500}; /* 37 - 40 */ 8240 const static soc_port_details_t kt2_port_details_56454_1[]={ 8241 {1,5,4,XE_PORT,10000}, 8242 {27,28,1,HG_PORT|STK_PORT,13000}, 8243 {40,40,1,OLP_PORT,2500},/* OLP */ 8244 {0,0,0,0} /* End */ 8245 }; 8246 8247 /* 2xF.XAUI + 2xHG13 */ 8248 static uint32 kt2_tdm_D1_56454_2[20]={0}; 8249 const static kt2_speed_t kt2_speed_56454_2= { 8250 10000,0000,0000,0000, /* 1 .- 4 */ 8251 10000,0000,0000,0000, /* 5 - 8 */ 8252 0000,0000,0000,0000, /* 9 - 12 */ 8253 0000,0000,0000,0000, /* 13 - 16 */ 8254 0000,0000,0000,0000, /* 17 - 20 */ 8255 0000,0000,0000,0000, /* 21 - 24 */ 8256 13000,13000,0000,0000, /* 25 - 28 */ 8257 0000,0000,0000,0000, /* 29 - 32 */ 8258 0000,0000,0000,0000, /* 33 - 36 */ 8259 0000,0000,0000,0000}; /* 37 - 40 */ 8260 const static soc_port_details_t kt2_port_details_56454_2[]={ 8261 {1,5,4,XE_PORT,10000}, 8262 {25,26,1,HG_PORT|STK_PORT,13000}, 8263 {0,0,0,0} /* End */ 8264 }; 8265 8266 8267 /* 24x GE + 4x HG[13] /4x XAUI / 16x 2.5G */ 8268 static uint32 kt2_tdm_C_56455_1[84]={0}; 8269 const static kt2_speed_t kt2_speed_56455_1= { 8270 1000,1000,1000,1000, /* 1 .- 4 */ 8271 1000,1000,1000,1000, /* 5 - 8 */ 8272 1000,1000,1000,1000, /* 9 - 12 */ 8273 1000,1000,1000,1000, /* 13 - 16 */ 8274 1000,1000,1000,1000, /* 17 - 20 */ 8275 1000,1000,1000,1000, /* 21 - 24 */ 8276 13000,13000,13000,13000, /* 25 - 28 */ 8277 0000,0000,0000,0000, /* 29 - 32 */ 8278 0000,0000,0000,0000, /* 33 - 36 */ 8279 0000,0000,0000,0000}; /* 37 - 40 */ 8280 const static soc_port_details_t kt2_port_details_56455_1[]={ 8281 {1,24,1,GE_PORT,1000}, 8282 {25,28,1,HG_PORT|STK_PORT,13000}, 8283 {0,0,0,0} /* End */ 8284 }; 8285 8286 static uint32 kt2_tdm_C_56455_2[84]={0}; 8287 const static kt2_speed_t kt2_speed_56455_2= { 8288 0000,0000,0000,0000, /* 1 .- 4 */ 8289 0000,0000,0000,0000, /* 5 - 8 */ 8290 1000,1000,1000,1000, /* 9 - 12 */ 8291 1000,1000,1000,1000, /* 13 - 16 */ 8292 0000,0000,0000,0000, /* 17 - 20 */ 8293 0000,0000,0000,0000, /* 21 - 24 */ 8294 13000,13000,0000,0000, /* 25 - 28 */ 8295 0000,0000,0000,0000, /* 29 - 32 */ 8296 0000,0000,0000,0000, /* 33 - 36 */ 8297 0000,0000,0000,0000}; /* 37 - 40 */ 8298 const static soc_port_details_t kt2_port_details_56455_2[]={ 8299 {9,16,1,GE_PORT,1000}, 8300 {25,26,1,HG_PORT|STK_PORT,13000}, 8301 {0,0,0,0} /* End */ 8302 }; 8303 8304 static uint32 kt2_tdm_A3_56248_16[88]={0}; 8305 const static kt2_speed_t kt2_speed_56248_16= { 8306 1000,1000,1000,1000, /* 1 .- 4 */ 8307 1000,1000,1000,1000, /* 5 - 8 */ 8308 10000,0000,0000,0000, /* 9 - 12 */ 8309 10000,0000,0000,0000, /* 13 - 16 */ 8310 10000,0000,0000,0000, /* 17 - 20 */ 8311 10000,0000,0000,0000, /* 21 - 24 */ 8312 10000,0000,10000,21000, /* 25 - 28 */ 8313 0000,0000,0000,0000, /* 29 - 32 */ 8314 0000,0000,0000,0000, /* 33 - 36 */ 8315 0000,0000,0000,2500 /* 37 - 40 */ 8316 }; 8317 const static soc_port_details_t kt2_port_details_56248_16[]={ 8318 {1,8,1,GE_PORT,1000}, 8319 {9,21,4,XE_PORT,1000}, 8320 {25,27,2,XE_PORT,10000}, 8321 {28,28,1,HG_PORT|STK_PORT,21000}, 8322 {40,40,1,OLP_PORT,2500},/* OLP */ 8323 {0,0,0,0} /* End */ 8324 }; 8325 8326 static uint32 kt2_tdm_D2_56248_17[40]={0}; 8327 const static kt2_speed_t kt2_speed_56248_17= { 8328 1000,1000,1000,1000, /* 1 .- 4 */ 8329 1000,1000,1000,1000, /* 5 - 8 */ 8330 1000,2500,2500,2500, /* 9 - 12 */ 8331 2500,0000,0000,0000, /* 13 - 16 */ 8332 2500,0000,0000,0000, /* 17 - 20 */ 8333 2500,0000,0000,0000, /* 21 - 24 */ 8334 2500,0000,2500,1000, /* 25 - 28 */ 8335 0000,1000,0000,0000, /* 29 - 32 */ 8336 0000,0000,0000,0000, /* 33 - 36 */ 8337 0000,0000,0000,2500 /* 37 - 40 */ 8338 }; 8339 const static soc_port_details_t kt2_port_details_56248_17[]={ 8340 {1,8,1,GE_PORT,1000}, 8341 {9,9,1,GE_PORT,1000}, 8342 {10,12,1,GE_PORT,2500}, 8343 {13,25,4,GE_PORT,2500}, 8344 {27,27,1,GE_PORT,2500}, 8345 {28,30,2,GE_PORT,1000}, 8346 {40,40,1,OLP_PORT,2500},/* OLP */ 8347 {0,0,0,0} /* End */ 8348 }; 8349 8350 8351 static uint32 kt2_tdm_mxqblock_ports_used[KT2_MAX_MXQBLOCKS]={0}; 8352 static uint32 kt2_tdm_position_mxq_mask[90]={0}; 8353 /* typedef uint32 kt2_port_to_mxqblock_t[KT2_MAX_PHYSICAL_PORTS]; */ 8354 static kt2_port_to_mxqblock_t kt2_port_to_mxqblock_s={0,0,0,0, /* 1-4 mxq0*/ 8355 1,1,1,1, /* 5-8 mxq1*/ 8356 2,2,2,2, /* 9-12 mxq2*/ 8357 3,3,3,3, /* 13-16 mxq3*/ 8358 4,4,4,4, /* 17-20 mxq4*/ 8359 5,5,5,5, /* 21-24 mxq5*/ 8360 6,7,8,9, /* 25-28 mxq6-9 */ 8361 9,9,9,8, /* 29-32 mxq9,9,9-8 */ 8362 8,8,6,6, /* 33-36 mxq8,8,6-6 */ 8363 6,7,7,7 /* 37-40 mxq6,7,7,7 */ 8364 }; 8365 static kt2_port_to_mxqblock_t *kt2_port_to_mxqblock[SOC_MAX_NUM_DEVICES]={NULL}; 8366 8367 kt2_tdm_pos_info_t kt2_tdm_pos_info[KT2_MAX_MXQBLOCKS]={{0}}; 8368 8369 /* typedef uint32 kt2_port_to_mxqblock_subports_t[KT2_MAX_PHYSICAL_PORTS]; */ 8370 kt2_port_to_mxqblock_subports_t kt2_port_to_mxqblock_subports_s={ 8371 0,1,2,3, /* 1-4 mxq0*/ 8372 0,1,2,3, /* 5-8 mxq1*/ 8373 0,1,2,3, /* 9-12 mxq2*/ 8374 0,1,2,3, /* 13-16 mxq3*/ 8375 0,1,2,3, /* 17-20 mxq4*/ 8376 0,1,2,3, /* 21-24 mxq5*/ 8377 0,0,0,0, /* 25-28 mxq6-9 */ 8378 1,2,3,1, /* 29-32 mxq9,9,9-8 */ 8379 2,3,1,2, /* 33-36 mxq8,8,6-6 */ 8380 3,1,2,3 /* 37-40 mxq6,7,7,7 */ 8381 }; 8382 kt2_port_to_mxqblock_subports_t *kt2_port_to_mxqblock_subports[SOC_MAX_NUM_DEVICES]={NULL}; 8383 8384 soc_field_t kt2_srcport_field_names[KT2_MAX_LOGICAL_PORTS]={ 8385 SRCPORT_0f, 8386 SRCPORT_1f, SRCPORT_2f, SRCPORT_3f, SRCPORT_4f, 8387 SRCPORT_5f, SRCPORT_6f, SRCPORT_7f, SRCPORT_8f, 8388 SRCPORT_9f, SRCPORT_10f, SRCPORT_11f, SRCPORT_12f, 8389 SRCPORT_13f, SRCPORT_14f, SRCPORT_15f, SRCPORT_16f, 8390 SRCPORT_17f, SRCPORT_18f, SRCPORT_19f, SRCPORT_20f, 8391 SRCPORT_21f, SRCPORT_22f, SRCPORT_23f, SRCPORT_24f, 8392 SRCPORT_25f, SRCPORT_26f, SRCPORT_27f, SRCPORT_28f, 8393 SRCPORT_29f, SRCPORT_30f, SRCPORT_31f, SRCPORT_32f, 8394 SRCPORT_33f, SRCPORT_34f, SRCPORT_35f, SRCPORT_36f, 8395 SRCPORT_37f, SRCPORT_38f, SRCPORT_39f, SRCPORT_40f, 8396 SRCPORT_41f 8397 }; 8398 uint8 kt2_tdm_update_flag=1; 8399 8400 8401 8402 uint32 kt2_tdm_0[78] = { 1,9,25,26,27,28, 8403 17,2,25,26,27,28, 8404 0,10,18,25,26,27, 8405 28,3,11,25,26,27, 8406 28,35,19,4,25,26, 8407 27,28,12,20,25,26, 8408 27,28,63,5,13,25, 8409 26,27,28,21,6,25, 8410 26,27,28,0,14,22, 8411 25,26,27,28,7,15, 8412 25,26,27,28,35,23, 8413 8,25,26,27,28,16, 8414 24,25,26,27,28,35 8415 }; 8416 8417 8418 /* typedef uint32 kt2_mxqblock_ports_t[KT2_MAX_MXQBLOCKS] 8419 [KT2_MAX_MXQPORTS_PER_BLOCK]; */ 8420 kt2_mxqblock_ports_t kt2_mxqblock_ports_s= 8421 {{1,2,3,4}, 8422 {5,6,7,8}, 8423 {9,10,11,12}, 8424 {13,14,15,16}, 8425 {17,18,19,20}, 8426 {21,22,23,24}, 8427 {25,35,36,37}, 8428 {26,38,39,40}, 8429 {27,32,33,34}, 8430 {28,29,30,31}, 8431 {0xFF,0xFF,0xFF,0xFF}, 8432 }; 8433 kt2_mxqblock_ports_t *kt2_mxqblock_ports[SOC_MAX_NUM_DEVICES]={NULL}; 8434 8435 tdm_cycles_info_t kt2_tdm_cycles_info[KT2_MAX_TDM_FREQUENCY][KT2_MAX_SPEEDS]={ 8436 /*0:205MHz: 216 Used */ 8437 {{108,108,2},{56,54,4},{44,43,5},{11,11,20}, 8438 {9,9,24},{6,4,44},{6,4,44}}, 8439 8440 /*1:123MHz: 40Cycles Used*/ 8441 {{40,40,1},{33,20,2},{26,20,2},{6,6,6}, 8442 {5,4,8},{3,2,14},{3,2,14}}, 8443 8444 /*2:176MHz: 72 Used*/ 8445 {{84,84,1},{48,36,2},{39,36,2},{10,8,8}, 8446 {8,7,9},{5,3,15},{5,3,15}}, 8447 8448 /*3:176MHz: 60Cycles Used */ 8449 {{80,80,1},{48,30,2},{38,30 ,2 },{10,9,6}, 8450 {8,7,8},{5,4,12},{5,4,12}}, 8451 8452 /*4:176MHz: 90Cycles Used*/ 8453 {{90,90,1},{48,45,2},{38,30,3},{10,9,9}, 8454 {8,7,12},{5,4,18},{5,4,18}}, 8455 /*5:205MHz: 108 Used */ 8456 {{108,108,1},{56,52,2},{44,34,3},{11,10,10}, 8457 {9,9,12},{5,4,21},{5,4,21}}, 8458 /*6:205MHz: 88 Used */ 8459 {{88,88,1},{56,42,2},{44,42,2},{11,10,8}, 8460 {10,10,8},{5,4,16},{5,4,16}}, 8461 /*7:176MHz:64 Used */ 8462 {{64,64,1},{52,32,2},{41,32,2},{10,9,7}, 8463 {8,7,8},{5,4,13},{5,4,13}}, 8464 /*8:166MHz: 84 Used */ 8465 {{84,84,1},{52,42,2},{41,28,3},{10,9,9}, 8466 {8,6,12},{5,4,17},{5,4,17}}, 8467 /*9:205MHz: 176 Used */ 8468 {{88, 88, 2}, 8469 {44, 44, 4},{44, 44, 4},{11, 11, 16}, 8470 {9, 8, 20},{6, 4, 32},{6, 4, 32}}, 8471 /*10:205MHz: 88 Used */ 8472 {{88,88,1},{52,34,2},{52,34,2},{10,10,8}, 8473 {9,7,10},{5,4,16},{5,4,16}}, 8474 }; 8475 8476 tdm_cycles_info_t kt2_current_tdm_cycles_info[KT2_MAX_SPEEDS]={{0}}; 8477 8478 typedef struct tdm_port_slots_info_s { 8479 int32 position; 8480 struct tdm_port_slots_info_s *prev; 8481 struct tdm_port_slots_info_s *next; 8482 }tdm_port_slots_info_t; 8483 8484 tdm_port_slots_info_t kt2_tdm_port_slots_info[KT2_MAX_LOGICAL_PORTS]; 8485 8486 static uint32 *bcm56450_tdm[]={ 8487 kt2_tdm_56450config_deprecated0, /*56450 Cfg=0:IntCfg=0 */ 8488 kt2_tdm_A_56450_1, /*56450 Cfg=1:IntCfg=1 */ 8489 kt2_tdm_A_56450_2, /*56450 Cfg=2:IntCfg=2 */ 8490 kt2_tdm_A_56450_3, /*56450 Cfg=3:IntCfg=3 */ 8491 kt2_tdm_A_56450_4, /*56450 Cfg=4:IntCfg=4 */ 8492 kt2_tdm_A_56450_5, /*56450 Cfg=5:IntCfg=5 */ 8493 kt2_tdm_A_56450_6, /*56450 Cfg=6:IntCfg=6 */ 8494 kt2_tdm_A_56450_7, /*56450 Cfg=7:IntCfg=7 */ 8495 kt2_tdm_A1_56450_8, /*56450 Cfg=8:IntCfg=8 */ 8496 kt2_tdm_A1A_56450_9, /*56450 Cfg=9:IntCfg=9 */ 8497 kt2_tdm_A2_56450_10, /*56450 Cfg=10:IntCfg=10 */ 8498 kt2_tdm_A2_56450_11, /*56450 Cfg=11:IntCfg=11 */ 8499 kt2_tdm_A3_56450_12, /*56450 Cfg=12:IntCfg=12 */ 8500 kt2_tdm_A2_56450_13, /*56450 Cfg=13:IntCfg=13 */ 8501 kt2_tdm_A1_56450_14, /*56450 Cfg=14:IntCfg=14 */ 8502 kt2_tdm_A4_56450_15, /*56450 Cfg=15:IntCfg=15 */ 8503 kt2_tdm_F_56450_16, /*56450 Cfg=16:IntCfg=16 */ 8504 kt2_tdm_C_56452_1, /*56452 Cfg=1:IntCfg=17 */ 8505 kt2_tdm_C1_56452_2, /*56452 Cfg=2:IntCfg=18 */ 8506 kt2_tdm_C1_56452_3, /*56452 Cfg=3:IntCfg=19 */ 8507 kt2_tdm_C1_56452_4, /*56452 Cfg=4:IntCfg=20 */ 8508 kt2_tdm_B_56452_5, /*56452 Cfg=5:IntCfg=21 */ 8509 kt2_tdm_B1_56452_6, /*56452 Cfg=6:IntCfg=22 */ 8510 kt2_tdm_B_56452_7, /*56452 Cfg=7:IntCfg=23 */ 8511 kt2_tdm_B_56452_8, /*56452 Cfg=8:IntCfg=24 */ 8512 kt2_tdm_B1_56452_9, /*56452 Cfg=9:IntCfg=25 */ 8513 kt2_tdm_B2_56452_10, /*56452 Cfg=10:IntCfg=26 */ 8514 kt2_tdm_D1_56454_1, /*56454 Cfg=1:IntCfg=27 */ 8515 kt2_tdm_D1_56454_2, /*56454 Cfg=2:IntCfg=28 */ 8516 kt2_tdm_C_56455_1, /*56455 Cfg=1:IntCfg=29 */ 8517 kt2_tdm_C_56455_2, /*56455 Cfg=2:IntCfg=30 */ 8518 kt2_tdm_56450config_deprecated0, /*56248 Cfg=0:IntCfg=31 */ 8519 kt2_tdm_A_56450_1, /*56248 Cfg=1:IntCfg=32 */ 8520 kt2_tdm_A_56450_2, /*56248 Cfg=2:IntCfg=33 */ 8521 kt2_tdm_A_56450_3, /*56248 Cfg=3:IntCfg=34 */ 8522 kt2_tdm_A_56450_4, /*56248 Cfg=4:IntCfg=35 */ 8523 kt2_tdm_A_56450_5, /*56248 Cfg=5:IntCfg=36 */ 8524 kt2_tdm_A_56450_6, /*56248 Cfg=6:IntCfg=37 */ 8525 kt2_tdm_A_56450_7, /*56248 Cfg=7:IntCfg=38 */ 8526 kt2_tdm_A1_56450_8, /*56248 Cfg=8:IntCfg=39 */ 8527 kt2_tdm_A1A_56450_9, /*56248 Cfg=9:IntCfg=40 */ 8528 kt2_tdm_A2_56450_10, /*56248 Cfg=10:IntCfg=41 */ 8529 kt2_tdm_A2_56450_11, /*56248 Cfg=11:IntCfg=42 */ 8530 kt2_tdm_A3_56450_12, /*56248 Cfg=12:IntCfg=43 */ 8531 kt2_tdm_A2_56450_13, /*56248 Cfg=13:IntCfg=44 */ 8532 kt2_tdm_A1_56450_14, /*56248 Cfg=14:IntCfg=45 */ 8533 kt2_tdm_A4_56450_15, /*56248 Cfg=15:IntCfg=46 */ 8534 kt2_tdm_A3_56248_16, /*56248 Cfg=16:IntCfg=47 */ 8535 kt2_tdm_D2_56248_17 /*56248 Cfg=17:IntCfg=48 */ 8536 #ifdef BCM_WARM_BOOT_SUPPORT 8537 ,kt2_scache_tdm[0] /*Dummy TDM reserved for WB */ 8538 #endif 8539 }; 8540 const static uint32 *bcm56450_speed_s[]={ 8541 kt2_tdm_56450speed_deprecated0, /*56450 Cfg=0:IntCfg=0 */ 8542 kt2_speed_56450_1, /*56450 Cfg=1:IntCfg=1 */ 8543 kt2_speed_56450_2, /*56450 Cfg=2:IntCfg=2 */ 8544 kt2_speed_56450_3, /*56450 Cfg=3:IntCfg=3 */ 8545 kt2_speed_56450_4, /*56450 Cfg=4:IntCfg=4 */ 8546 kt2_speed_56450_5, /*56450 Cfg=5:IntCfg=5 */ 8547 kt2_speed_56450_6, /*56450 Cfg=6:IntCfg=6 */ 8548 kt2_speed_56450_7, /*56450 Cfg=7:IntCfg=7 */ 8549 kt2_speed_56450_8, /*56450 Cfg=8:IntCfg=8 */ 8550 kt2_speed_56450_9, /*56450 Cfg=9:IntCfg=9 */ 8551 kt2_speed_56450_10, /*56450 Cfg=10:IntCfg=10 */ 8552 kt2_speed_56450_11, /*56450 Cfg=11:IntCfg=11 */ 8553 kt2_speed_56450_12, /*56450 Cfg=12:IntCfg=12 */ 8554 kt2_speed_56450_13, /*56450 Cfg=13:IntCfg=13 */ 8555 kt2_speed_56450_14, /*56450 Cfg=14:IntCfg=14 */ 8556 kt2_speed_56450_15, /*56450 Cfg=15:IntCfg=15 */ 8557 kt2_speed_56450_16, /*56450 Cfg=16:IntCfg=16 */ 8558 kt2_speed_56452_1, /*56452 Cfg=1:IntCfg=17 */ 8559 kt2_speed_56452_2, /*56452 Cfg=2:IntCfg=18 */ 8560 kt2_speed_56452_3, /*56452 Cfg=3:IntCfg=19 */ 8561 kt2_speed_56452_4, /*56452 Cfg=4:IntCfg=20 */ 8562 kt2_speed_56452_5, /*56452 Cfg=5:IntCfg=20 */ 8563 kt2_speed_56452_6, /*56452 Cfg=6:IntCfg=22 */ 8564 kt2_speed_56452_7, /*56452 Cfg=7:IntCfg=23 */ 8565 kt2_speed_56452_8, /*56452 Cfg=8:IntCfg=24 */ 8566 kt2_speed_56452_9, /*56452 Cfg=9:IntCfg=25 */ 8567 kt2_speed_56452_10, /*56452 Cfg=10:IntCfg=26 */ 8568 kt2_speed_56454_1, /*56454 Cfg=1:IntCfg=27 */ 8569 kt2_speed_56454_2, /*56454 Cfg=2:IntCfg=28 */ 8570 kt2_speed_56455_1, /*56455 Cfg=1:IntCfg=29 */ 8571 kt2_speed_56455_2, /*56455 Cfg=2:IntCfg=30 */ 8572 kt2_tdm_56450speed_deprecated0, /*56248 Cfg=0:IntCfg=31 */ 8573 kt2_speed_56450_1, /*56248 Cfg=1:IntCfg=32 */ 8574 kt2_speed_56450_2, /*56248 Cfg=2:IntCfg=33 */ 8575 kt2_speed_56450_3, /*56248 Cfg=3:IntCfg=34 */ 8576 kt2_speed_56450_4, /*56248 Cfg=4:IntCfg=35 */ 8577 kt2_speed_56450_5, /*56248 Cfg=5:IntCfg=36 */ 8578 kt2_speed_56450_6, /*56248 Cfg=6:IntCfg=37 */ 8579 kt2_speed_56450_7, /*56248 Cfg=7:IntCfg=38 */ 8580 kt2_speed_56450_8, /*56248 Cfg=8:IntCfg=39 */ 8581 kt2_speed_56450_9, /*56248 Cfg=9:IntCfg=40 */ 8582 kt2_speed_56450_10, /*56248 Cfg=10:IntCfg=41 */ 8583 kt2_speed_56450_11, /*56248 Cfg=11:IntCfg=42 */ 8584 kt2_speed_56450_12, /*56248 Cfg=12:IntCfg=43 */ 8585 kt2_speed_56450_13, /*56248 Cfg=13:IntCfg=44 */ 8586 kt2_speed_56450_14, /*56248 Cfg=14:IntCfg=45 */ 8587 kt2_speed_56450_15, /*56248 Cfg=15:IntCfg=46 */ 8588 kt2_speed_56248_16, /*56248 Cfg=16:IntCfg=47 */ 8589 kt2_speed_56248_17 /*56248 Cfg=17:IntCfg=48 */ 8590 #ifdef BCM_WARM_BOOT_SUPPORT 8591 ,kt2_scache_speed[0] /* Dummy speed reserved for WB*/ 8592 #endif 8593 }; 8594 static kt2_speed_t *bcm56450_speed[SOC_MAX_NUM_DEVICES]={NULL}; 8595 8596 const static soc_port_details_t *kt2_port_details[]={ 8597 kt2_port_details_deprecated0, /*56450 Cfg=0:IntCfg=0 */ 8598 kt2_port_details_56450_1, /*56450 Cfg=1:IntCfg=1 */ 8599 kt2_port_details_56450_2, /*56450 Cfg=2:IntCfg=2 */ 8600 kt2_port_details_56450_3, /*56450 Cfg=3:IntCfg=3 */ 8601 kt2_port_details_56450_4, /*56450 Cfg=4:IntCfg=4 */ 8602 kt2_port_details_56450_5, /*56450 Cfg=5:IntCfg=5 */ 8603 kt2_port_details_56450_6, /*56450 Cfg=6:IntCfg=6 */ 8604 kt2_port_details_56450_7, /*56450 Cfg=7:IntCfg=7 */ 8605 kt2_port_details_56450_8, /*56450 Cfg=8:IntCfg=8 */ 8606 kt2_port_details_56450_9, /*56450 Cfg=9:IntCfg=9 */ 8607 kt2_port_details_56450_10, /*56450 Cfg=10:IntCfg=10 */ 8608 kt2_port_details_56450_11, /*56450 Cfg=11:IntCfg=11 */ 8609 kt2_port_details_56450_12, /*56450 Cfg=12:IntCfg=12 */ 8610 kt2_port_details_56450_13, /*56450 Cfg=13:IntCfg=13 */ 8611 kt2_port_details_56450_14, /*56450 Cfg=14:IntCfg=14 */ 8612 kt2_port_details_56450_15, /*56450 Cfg=15:IntCfg=15 */ 8613 kt2_port_details_56450_16, /*56450 Cfg=16:IntCfg=16 */ 8614 kt2_port_details_56452_1, /*56452 Cfg=1:IntCfg=17 */ 8615 kt2_port_details_56452_2, /*56452 Cfg=2:IntCfg=18 */ 8616 kt2_port_details_56452_3, /*56452 Cfg=3:IntCfg=19 */ 8617 kt2_port_details_56452_4, /*56452 Cfg=4:IntCfg=20 */ 8618 kt2_port_details_56452_5, /*56452 Cfg=5:IntCfg=21 */ 8619 kt2_port_details_56452_6, /*56452 Cfg=6:IntCfg=22 */ 8620 kt2_port_details_56452_7, /*56452 Cfg=7:IntCfg=23 */ 8621 kt2_port_details_56452_8, /*56452 Cfg=8:IntCfg=24 */ 8622 kt2_port_details_56452_9, /*56452 Cfg=9:IntCfg=25 */ 8623 kt2_port_details_56452_10, /*56452 Cfg=10:IntCfg=26 */ 8624 kt2_port_details_56454_1, /*56454 Cfg=1:IntCfg=27 */ 8625 kt2_port_details_56454_2, /*56454 Cfg=2:IntCfg=28 */ 8626 kt2_port_details_56455_1, /*56455 Cfg=1:IntCfg=29 */ 8627 kt2_port_details_56455_2, /*56455 Cfg=2:IntCfg=30 */ 8628 kt2_port_details_deprecated0, /*56248 Cfg=0:IntCfg=31 */ 8629 kt2_port_details_56450_1, /*56248 Cfg=1:IntCfg=32 */ 8630 kt2_port_details_56450_2, /*56248 Cfg=2:IntCfg=33 */ 8631 kt2_port_details_56450_3, /*56248 Cfg=3:IntCfg=34 */ 8632 kt2_port_details_56450_4, /*56248 Cfg=4:IntCfg=35 */ 8633 kt2_port_details_56450_5, /*56248 Cfg=5:IntCfg=36 */ 8634 kt2_port_details_56450_6, /*56248 Cfg=6:IntCfg=37 */ 8635 kt2_port_details_56450_7, /*56248 Cfg=7:IntCfg=38 */ 8636 kt2_port_details_56450_8, /*56248 Cfg=8:IntCfg=39 */ 8637 kt2_port_details_56450_9, /*56248 Cfg=9:IntCfg=40 */ 8638 kt2_port_details_56450_10, /*56248 Cfg=10:IntCfg=41 */ 8639 kt2_port_details_56450_11, /*56248 Cfg=11:IntCfg=42 */ 8640 kt2_port_details_56450_12, /*56248 Cfg=12:IntCfg=43 */ 8641 kt2_port_details_56450_13, /*56248 Cfg=13:IntCfg=44 */ 8642 kt2_port_details_56450_14, /*56248 Cfg=14:IntCfg=45 */ 8643 kt2_port_details_56450_15, /*56248 Cfg=15:IntCfg=46 */ 8644 kt2_port_details_56248_16, /*56248 Cfg=16:IntCfg=47 */ 8645 kt2_port_details_56248_17 /*56248 Cfg=17:IntCfg=48 */ 8646 #ifdef BCM_WARM_BOOT_SUPPORT 8647 /* Dummy port details reserved for WB */ 8648 ,kt2_scache_port_details[0] 8649 #endif 8650 }; 8651 static bcm56450_tdm_info_t bcm56450_tdm_info[]={ 8652 {205, 88, 8, 11}, /*56450 Cfg=0:IntCfg=0 */ 8653 {205, 88, 8, 11}, /*56450 Cfg=1:IntCfg=1 */ 8654 {205, 88, 8, 11}, /*56450 Cfg=2:IntCfg=2 */ 8655 {205, 88, 8, 11}, /*56450 Cfg=3:IntCfg=3 */ 8656 {205, 88, 8, 11}, /*56450 Cfg=4:IntCfg=4 */ 8657 {205, 88, 8, 11}, /*56450 Cfg=5:IntCfg=5 */ 8658 {205, 88, 8, 11}, /*56450 Cfg=6:IntCfg=6 */ 8659 {205, 88, 8, 11}, /*56450 Cfg=7:IntCfg=7 */ 8660 {205, BCM_KT2_TDM_A1_NUM_SLOTS, 16, 11},/*56450 Cfg=8:IntCfg=8 */ 8661 {205, 108, 12, 9}, /*56450 Cfg=9:IntCfg=9 */ 8662 {205, 216, 24, 9}, /*56450 Cfg=10:IntCfg=10 */ 8663 {205, 216, 24, 9}, /*56450 Cfg=11:IntCfg=11 */ 8664 {205, 88, 8, 11}, /*56450 Cfg=12:IntCfg=12 */ 8665 {205, 216, 24, 9}, /*56450 Cfg=13:IntCfg=13 */ 8666 {205, BCM_KT2_TDM_A1_NUM_SLOTS, 16, 11},/*56450 Cfg=14:IntCfg=14 */ 8667 {205, BCM_KT2_TDM_A4_NUM_SLOTS, 8, 11}, /*56450 Cfg=15:IntCfg=15 */ 8668 {205, 88, 8, 11}, /*56450 Cfg=16:IntCfg=16 */ 8669 {166, 84, 12, 7}, /*56452 Cfg=1:IntCfg=17 */ 8670 {176, 64, 8, 8}, /*56452 Cfg=2:IntCfg=18 */ 8671 {176, 64, 8, 8}, /*56452 Cfg=3:IntCfg=19 */ 8672 {176, 64, 8, 8}, /*56452 Cfg=4:IntCfg=20 */ 8673 {176, 90, 10, 9}, /*56452 Cfg=5:IntCfg=21 */ 8674 {176, 60, 6, 10}, /*56452 Cfg=6:IntCfg=22 */ 8675 {176, 90, 10, 9}, /*56452 Cfg=7:IntCfg=23 */ 8676 {176, 90, 10, 9}, /*56452 Cfg=8:IntCfg=24 */ 8677 {176, 60, 6, 10}, /*56452 Cfg=9:IntCfg=25 */ 8678 {176, 72, 8, 9}, /*56452 Cfg=10:IntCfg=26 */ 8679 {123, 40, 8, 5}, /*56454 Cfg=1:IntCfg=27 */ 8680 {123, 40, 8, 5}, /*56454 Cfg=2:IntCfg=28 */ 8681 {166, 84, 12, 7}, /*56455 Cfg=1:IntCfg=29 */ 8682 {166, 84, 12, 7}, /*56455 Cfg=2:IntCfg=30 */ 8683 {205, 88, 8, 11}, /*56248 Cfg=0:IntCfg=31 */ 8684 {205, 88, 8, 11}, /*56248 Cfg=1:IntCfg=32 */ 8685 {205, 88, 8, 11}, /*56248 Cfg=2:IntCfg=33 */ 8686 {205, 88, 8, 11}, /*56248 Cfg=3:IntCfg=34 */ 8687 {205, 88, 8, 11}, /*56248 Cfg=4:IntCfg=35 */ 8688 {205, 88, 8, 11}, /*56248 Cfg=5:IntCfg=36 */ 8689 {205, 88, 8, 11}, /*56248 Cfg=6:IntCfg=37 */ 8690 {205, 88, 8, 11}, /*56248 Cfg=7:IntCfg=38 */ 8691 {205, BCM_KT2_TDM_A1_NUM_SLOTS, 16, 11},/*56248 Cfg=8:IntCfg=39 */ 8692 {205, 108, 12, 9}, /*56248 Cfg=9:IntCfg=40 */ 8693 {205, 216, 24, 9}, /*56248 Cfg=10:IntCfg=41 */ 8694 {205, 216, 24, 9}, /*56248 Cfg=11:IntCfg=42 */ 8695 {205, 88, 12, 9}, /*56248 Cfg=12:IntCfg=43 */ 8696 {205, 216, 24, 9}, /*56248 Cfg=13:IntCfg=44 */ 8697 {205, BCM_KT2_TDM_A1_NUM_SLOTS, 16, 11},/*56450 Cfg=14:IntCfg=14 */ 8698 {205, BCM_KT2_TDM_A4_NUM_SLOTS, 8, 11}, /*56248 Cfg=15:IntCfg=46 */ 8699 {205, 88, 8, 11}, /*56248 Cfg=16:IntCfg=47 */ 8700 {123, 40, 8, 5} /*56248 Cfg=16:IntCfg=48 */ 8701 #ifdef BCM_WARM_BOOT_SUPPORT 8702 ,{0,0,0,0} /*kt2_scache_tdm_info *//*Dummy:Reserved for WB */ 8703 #endif 8704 }; 8705 8706 #ifdef UNDER_TESTING 8707 char tdm_config_string[80]={0}; 8708 /* 4xGE(1..4) 2xF-XAUI(5,9) 2xF-HG[13](25,26) 2x21G[G.INT](27,28) */ 8709 uint32 kt2_tdm_56450_test_speed0[40]= { 8710 1000 ,1000 ,1000 ,1000, /* 1 - 4 */ 8711 10000,0000 ,0000 ,0000, /* 5 - 8 */ 8712 10000,0000 ,0000 ,0000, /* 9 - 12 */ 8713 0000 ,0000 ,0000 ,0000, /* 13 - 16 */ 8714 0000 ,0000 ,0000 ,0000, /* 17 - 20 */ 8715 0000 ,0000 ,0000 ,0000, /* 21 - 24 */ 8716 13000,13000,21000,21000, /* 25 - 28 */ 8717 0, 0, 0, 0, /* 29 - 32 */ 8718 0, 0, 0, 0, /* 33 - 36 */ 8719 0, 0, 0, 0}; /* 37 - 40 */ 8720 8721 /* 24xGE(1..24) 2xF-HG[13](25,26) 2x21G[G.INT](27,28) */ 8722 uint32 kt2_tdm_56450_test_speed1[40]= { 8723 1000 ,1000 ,1000 ,1000, /* 1 - 4 */ 8724 1000 ,1000 ,1000 ,1000, /* 5 - 8 */ 8725 1000 ,1000 ,1000 ,1000, /* 9 - 12 */ 8726 1000 ,1000 ,1000 ,1000, /* 13 - 16 */ 8727 1000 ,1000 ,1000 ,1000, /* 17 - 20 */ 8728 1000 ,1000 ,1000 ,1000, /* 21 - 24 */ 8729 13000,13000,21000,21000, /* 25 - 28 */ 8730 0, 0, 0, 0, /* 29 - 32 */ 8731 0, 0, 0, 0, /* 33 - 36 */ 8732 0, 0, 0, 0}; /* 37 - 40 */ 8733 8734 /* 16x 2.5G(1..8 25,26,35..40) + 2x HG21(27..28) */ 8735 uint32 kt2_tdm_56450_test_speed2[40]= { 8736 2500,2500,2500 ,2500 , /* 1 - 4 */ 8737 2500,2500,2500 ,2500 , /* 5 - 8 */ 8738 0000,0000,0000 ,0000 , /* 9 - 12 */ 8739 0000,0000,0000 ,0000 , /* 13 - 16 */ 8740 0000,0000,0000 ,0000 , /* 17 - 20 */ 8741 0000,0000,0000 ,0000 , /* 21 - 24 */ 8742 2500,2500,21000,21000, /* 25 - 28 */ 8743 0000,0000,0000 ,0000 , /* 29 - 32 */ 8744 0000,0000,2500 ,2500 , /* 33 - 36 */ 8745 2500,2500,2500 ,2500 }; /* 37 - 40 */ 8746 8747 /* 24x GE(1..24) 8*2.5GE (25..26,35..40) + 2x HG21(27..28) */ 8748 uint32 kt2_tdm_56450_test_speed3[40]= { 8749 1000,1000,1000 ,1000 , /* 1 - 4 */ 8750 1000,1000,1000 ,1000 , /* 5 - 8 */ 8751 1000,1000,1000 ,1000 , /* 9 - 12 */ 8752 1000,1000,1000 ,1000 , /* 13 - 16 */ 8753 1000,1000,1000 ,1000 , /* 17 - 20 */ 8754 1000,1000,1000 ,1000 , /* 21 - 24 */ 8755 2500,2500,21000,21000, /* 25 - 28 */ 8756 0000,0000,0000 ,0000 , /* 29 - 32 */ 8757 0000,0000,2500 ,2500 , /* 33 - 36 */ 8758 2500,2500,2500 ,2500 }; /* 37 - 40 */ 8759 8760 /* 24x GE(1..24) 16*2.5GE (25..40) */ 8761 uint32 kt2_tdm_56450_test_speed4[40]= { 8762 1000,1000,1000,1000, /* 1 - 4 */ 8763 1000,1000,1000,1000, /* 5 - 8 */ 8764 1000,1000,1000,1000, /* 9 - 12 */ 8765 1000,1000,1000,1000, /* 13 - 16 */ 8766 1000,1000,1000,1000, /* 17 - 20 */ 8767 1000,1000,1000,1000, /* 21 - 24 */ 8768 2500,2500,2500,2500, /* 25 - 28 */ 8769 2500,2500,2500,2500, /* 29 - 32 */ 8770 2500,2500,2500,2500, /* 33 - 36 */ 8771 2500,2500,2500,2500}; /* 37 - 40 */ 8772 8773 /* 12x GE(1..4,5..8,17..20) 12*2.5GE (5..8,13..16,21..24),4*10G(25..28) */ 8774 uint32 kt2_tdm_56450_test_speed5[40]= { 8775 1000,1000,1000,1000, /* 1 - 4 */ 8776 2500,2500,2500,2500, /* 5 - 8 */ 8777 1000,1000,1000,1000, /* 9 - 12 */ 8778 2500,2500,2500,2500, /* 13 - 16 */ 8779 1000,1000,1000,1000, /* 17 - 20 */ 8780 2500,2500,2500,2500, /* 21 - 24 */ 8781 10000,10000,10000,10000, /* 25 - 28 */ 8782 0000,0000,0000,0000, /* 29 - 32 */ 8783 0000,0000,0000,0000, /* 33 - 36 */ 8784 0000,0000,0000,0000}; /* 37 - 40 */ 8785 8786 /* 8*10G(1,5,9,13,17,21,25,26) */ 8787 uint32 kt2_tdm_56450_test_speed6[40]= { 8788 10000,0000,0000,0000, /* 1 - 4 */ 8789 10000,0000,0000,0000, /* 5 - 8 */ 8790 10000,0000,0000,0000, /* 9 - 12 */ 8791 10000,0000,0000,0000, /* 13 - 16 */ 8792 10000,0000,0000,0000, /* 17 - 20 */ 8793 10000,0000,0000,0000, /* 21 - 24 */ 8794 10000,10000,0000,0000, /* 25 - 28 */ 8795 0000,0000,0000,0000, /* 29 - 32 */ 8796 0000,0000,0000,0000, /* 33 - 36 */ 8797 0000,0000,0000,0000}; /* 37 - 40 */ 8798 8799 /* 24* 2G(1..24) 4*10G(25..28) */ 8800 uint32 kt2_tdm_56450_test_speed7[40]= { 8801 2000,2000,2000,2000, /* 1 - 4 */ 8802 2000,2000,2000,2000, /* 5 - 8 */ 8803 2000,2000,2000,2000, /* 9 - 12 */ 8804 2000,2000,2000,2000, /* 13 - 16 */ 8805 2000,2000,2000,2000, /* 17 - 20 */ 8806 2000,2000,2000,2000, /* 21 - 24 */ 8807 10000,10000,10000,10000, /* 25 - 28 */ 8808 0000,0000,0000,0000, /* 29 - 32 */ 8809 0000,0000,0000,0000, /* 33 - 36 */ 8810 0000,0000,0000,0000}; /* 37 - 40 */ 8811 8812 /* 24*GE(1..24) 4*13G(25..28) */ 8813 uint32 kt2_tdm_56450_test_speed8[40]= { 8814 1000,1000,1000,1000, /* 1 - 4 */ 8815 1000,1000,1000,1000, /* 5 - 8 */ 8816 1000,1000,1000,1000, /* 9 - 12 */ 8817 1000,1000,1000,1000, /* 13 - 16 */ 8818 1000,1000,1000,1000, /* 17 - 20 */ 8819 1000,1000,1000,1000, /* 21 - 24 */ 8820 13000,13000,13000,13000, /* 25- 28 */ 8821 00,00,00,00, /* 29 - 32 */ 8822 00,00,00,00, /* 33 - 36 */ 8823 00,00,00,00}; /* 37 - 40 */ 8824 8825 /* 18*GE(1..18) 6*2.5G(19..24) 4*13G(25..28) */ 8826 uint32 kt2_tdm_56450_test_speed9[40]= { 8827 1000,1000,1000,1000, /* 1 - 4 */ 8828 1000,1000,1000,1000, /* 5 - 8 */ 8829 1000,1000,1000,1000, /* 9 - 12 */ 8830 1000,1000,1000,1000, /* 13 - 16 */ 8831 1000,1000,2500,2500, /* 17 - 20 */ 8832 2500,2500,2500,2500, /* 21 - 24 */ 8833 13000,13000,13000,13000, /* 25- 28 */ 8834 00,00,00,00, /* 29 - 32 */ 8835 00,00,00,00, /* 33 - 36 */ 8836 00,00,00,00}; /* 37 - 40 */ 8837 8838 8839 /* 4xGE + 2x F-XAUI + 2x F-HG[13] + 2x F-HG[21] */ 8840 uint32 kt2_tdm_56450_test_speed10[40]= { 8841 1000 ,1000 ,1000 ,1000, /* 1 - 4 */ 8842 10000,0000 ,0000 ,0000, /* 5 - 8 */ 8843 10000,0000 ,0000 ,0000, /* 9 - 12 */ 8844 0000 ,0000 ,0000 ,0000, /* 13 - 16 */ 8845 0000 ,0000 ,0000 ,0000, /* 17 - 20 */ 8846 0000 ,0000 ,0000 ,0000, /* 21 - 24 */ 8847 13000,13000,21000,21000, /* 25- 28 */ 8848 00,00,00,00, /* 29 - 32 */ 8849 00,00,00,00, /* 33 - 36 */ 8850 00,00,00,00}; /* 37 - 40 */ 8851 8852 /* 8xGE + 16x 2.5GE + 8x2.5G-HGL + 8x2.5G[G.INT] */ 8853 uint32 kt2_tdm_56450_test_speed11[40]= { 8854 1000 ,1000 ,2500 ,2500, /* 1 - 4 */ 8855 1000 ,1000 ,2500 ,2500, /* 5 - 8 */ 8856 1000 ,1000 ,2500 ,2500, /* 9 - 12 */ 8857 1000 ,1000 ,2500 ,2500, /* 13 - 16 */ 8858 2500 ,2500 ,2500 ,2500, /* 17 - 20 */ 8859 2500 ,2500 ,2500 ,2500, /* 21 - 24 */ 8860 2500 ,2500 ,2500 ,2500, /* 25- 28 */ 8861 2500 ,2500 ,2500 ,2500, /* 29 - 32 */ 8862 2500 ,2500 ,2500 ,2500, /* 33 - 36 */ 8863 2500 ,2500 ,2500 ,2500}; /* 37 - 40 */ 8864 8865 /* 8xGE + 8x XFI / 8x F-XAUI / 4x F-XAUI + 4x XFI */ 8866 uint32 kt2_tdm_56450_test_speed12[40]= { 8867 1000 ,1000 ,1000 ,1000, /* 1 - 4 */ 8868 1000 ,1000 ,1000 ,1000, /* 5 - 8 */ 8869 10000 ,0000 ,0000 ,0000, /* 9 - 12 */ 8870 10000 ,0000 ,0000 ,0000, /* 13- 16 */ 8871 10000 ,0000 ,0000 ,0000, /* 17 - 20 */ 8872 10000 ,0000 ,0000 ,0000, /* 21 - 24 */ 8873 10000 ,10000 ,10000 ,10000, /* 25 - 28 */ 8874 0000 ,0000 ,0000 ,0000, /* 29 - 32 */ 8875 0000 ,0000 ,0000 ,0000, /* 33 - 36 */ 8876 0000 ,0000 ,0000 ,0000}; /* 37 - 40 */ 8877 8878 /* 2*13G + 2*21G + 24*G */ 8879 uint32 kt2_tdm_56450_test_speed13[40]= { 8880 1000 ,1000 ,1000 ,1000, /* 1 - 4 */ 8881 1000 ,1000 ,1000 ,1000, /* 5 - 8 */ 8882 1000 ,1000 ,1000 ,0000, /* 9 - 12 */ 8883 1000 ,1000 ,1000 ,0000, /* 13- 16 */ 8884 1000 ,1000 ,1000 ,0000, /* 17 - 20 */ 8885 1000 ,1000 ,1000 ,0000, /* 21 - 24 */ 8886 13000 ,13000 ,21000 ,21000, /* 25 - 28 */ 8887 0000 ,0000 ,0000 ,0000, /* 29 - 32 */ 8888 0000 ,0000 ,0000 ,0000, /* 33 - 36 */ 8889 0000 ,0000 ,0000 ,0000}; /* 37 - 40 */ 8890 8891 /* 24x GE + 4x HG[13] */ 8892 uint32 kt2_tdm_56450_test_speed14[40]= { 8893 1000 ,1000 ,1000 ,1000, /* 1 - 4 */ 8894 1000 ,1000 ,1000 ,1000, /* 5 - 8 */ 8895 1000 ,1000 ,1000 ,1000, /* 9 - 12 */ 8896 1000 ,1000 ,1000 ,1000, /* 13- 16 */ 8897 1000 ,1000 ,1000 ,1000, /* 17 - 20 */ 8898 1000 ,1000 ,1000 ,1000, /* 21 - 24 */ 8899 13000 ,13000 ,13000 ,13000, /* 25 - 28 */ 8900 0000 ,0000 ,0000 ,0000, /* 29 - 32 */ 8901 0000 ,0000 ,0000 ,0000, /* 33 - 36 */ 8902 0000 ,0000 ,0000 ,0000}; /* 37 - 40 */ 8903 8904 /* 24x GE + 4x XAUI / 16x 2.5G */ 8905 uint32 kt2_tdm_56450_test_speed15[40]= { 8906 1000 ,1000 ,1000 ,1000, /* 1 - 4 */ 8907 1000 ,1000 ,1000 ,1000, /* 5 - 8 */ 8908 1000 ,1000 ,1000 ,1000, /* 9 - 12 */ 8909 1000 ,1000 ,1000 ,1000, /* 13- 16 */ 8910 1000 ,1000 ,1000 ,1000, /* 17 - 20 */ 8911 1000 ,1000 ,1000 ,1000, /* 21 - 24 */ 8912 10000 ,10000 ,10000 ,10000, /* 25 - 28 */ 8913 0000 ,0000 ,0000 ,0000, /* 29 - 32 */ 8914 0000 ,0000 ,0000 ,0000, /* 33 - 36 */ 8915 0000 ,0000 ,0000 ,0000}; /* 37 - 40 */ 8916 8917 /* 24x GE + 16x 2.5G */ 8918 uint32 kt2_tdm_56450_test_speed16[40]= { 8919 1000 ,1000 ,1000 ,1000, /* 1 - 4 */ 8920 1000 ,1000 ,1000 ,1000, /* 5 - 8 */ 8921 1000 ,1000 ,1000 ,1000, /* 9 - 12 */ 8922 1000 ,1000 ,1000 ,1000, /* 13- 16 */ 8923 1000 ,1000 ,1000 ,1000, /* 17 - 20 */ 8924 1000 ,1000 ,1000 ,1000, /* 21 - 24 */ 8925 2500 ,2500 ,2500 ,2500, /* 25 - 28 */ 8926 2500 ,2500 ,2500 ,2500, /* 29 - 32 */ 8927 2500 ,2500 ,2500 ,2500, /* 33 - 36 */ 8928 2500 ,2500 ,2500 ,2500}; /* 37 - 40 */ 8929 8930 /* 8x GE + 2 * 10G */ 8931 uint32 kt2_tdm_56450_test_speed17[40]= { 8932 1000 ,1000 ,1000 ,1000, /* 1 - 4 */ 8933 1000 ,1000 ,1000 ,1000, /* 5 - 8 */ 8934 0000 ,0000 ,0000 ,0000, /* 9 - 12 */ 8935 0000 ,0000 ,0000 ,0000, /* 13- 16 */ 8936 0000 ,0000 ,0000 ,0000, /* 17 - 20 */ 8937 0000 ,0000 ,0000 ,0000, /* 21 - 24 */ 8938 10000 ,10000 ,0000 ,0000, /* 25 - 28 */ 8939 0000 ,0000 ,0000 ,0000, /* 29 - 32 */ 8940 0000 ,0000 ,0000 ,0000, /* 33 - 36 */ 8941 0000 ,0000 ,0000 ,0000}; /* 37 - 40 */ 8942 8943 /* 4x 2.5GE + 1 * 13G 1 * 10G */ 8944 uint32 kt2_tdm_56450_test_speed18[40]= { 8945 2500 ,2500 ,2500 ,0000, /* 1 - 4 */ 8946 0000 ,0000 ,0000 ,0000, /* 5 - 8 */ 8947 0000 ,0000 ,0000 ,0000, /* 9 - 12 */ 8948 0000 ,0000 ,0000 ,0000, /* 13- 16 */ 8949 0000 ,0000 ,0000 ,0000, /* 17 - 20 */ 8950 0000 ,0000 ,0000 ,0000, /* 21 - 24 */ 8951 13000 ,10000 ,0000 ,0000, /* 25 - 28 */ 8952 0000 ,0000 ,0000 ,0000, /* 29 - 32 */ 8953 0000 ,0000 ,0000 ,0000, /* 33 - 36 */ 8954 0000 ,0000 ,0000 ,0000}; /* 37 - 40 */ 8955 8956 /* 4x 2.5GE + 4 * 1g */ 8957 uint32 kt2_tdm_56450_test_speed19[40]= { 8958 2500 ,0000 ,0000 ,0000, /* 1 - 4 */ 8959 2500 ,0000 ,0000 ,0000, /* 5 - 8 */ 8960 2500 ,0000 ,0000 ,0000, /* 9 - 12 */ 8961 2500 ,0000 ,0000 ,0000, /* 13- 16 */ 8962 1000 ,0000 ,0000 ,0000, /* 17 - 20 */ 8963 1000 ,0000 ,0000 ,0000, /* 21 - 24 */ 8964 1000 ,0000 ,0000 ,0000, /* 25 - 28 */ 8965 1000 ,0000 ,0000 ,0000, /* 29 - 32 */ 8966 0000 ,0000 ,0000 ,0000, /* 33 - 36 */ 8967 0000 ,0000 ,0000 ,0000}; /* 37 - 40 */ 8968 8969 8970 8971 8972 8973 8974 8975 8976 8977 8978 uint32 kt2_tdm_under_testing[90]= {KT2_IDLE}; 8979 uint32 kt2_tdm_under_testing_idle[180]= {KT2_IDLE}; 8980 #endif 8981 8982 /* *************************************************************** */ 8983 /* KATANA2 MMU HELPER --- START(As per Katana2_MMU_Setting_v8.xls */ 8984 /* *************************************************************** */ 8985 /* Dynamic/SetLater Parameter */ 8986 typedef struct _soc_kt2_mmu_params { 8987 uint32 mmu_min_pkt_size; /*C5*/ 8988 uint32 mmu_ethernet_mtu_bytes; /*C6*/ 8989 uint32 mmu_max_pkt_size; /*C7*/ 8990 uint32 mmu_jumbo_frame_size; /*C8*/ 8991 uint32 mmu_int_buf_cell_size; /*C9*/ 8992 /* mmu_ext_buf_cell_size = (mmu_int_buf_cell_size+2)*15; */ 8993 uint32 mmu_ext_buf_cell_size; /*C10=2880*/ 8994 uint32 mmu_pkt_header_size; /*C11*/ 8995 uint32 packing_mode_d_c; /* C12:Dynamic */ 8996 uint32 max_pkt_size_support_packing; /* C13:Dynamic */ 8997 uint32 lossless_mode_d_c; /* C14:Dynamic */ 8998 uint32 pfc_pause_mode_d_c; /* C15:Dynamic */ 8999 uint32 mmu_lossless_pg_num; /*C16*/ 9000 uint32 extbuf_used_d_c; /* C17:Dynamic */ 9001 uint32 num_ge_ports_d; /* C19:Dynamic */ 9002 uint32 mmu_line_rate_ge; /*C20*/ 9003 uint32 num_ge_int_ports_d; /* C21:Dynamic */ 9004 uint32 num_egr_queue_per_int_ge_port_d; /* C22:Dynamic */ 9005 uint32 num_ge_ext_ports_d; /* C23:Dynamic */ 9006 uint32 num_egr_queue_per_ext_ge_port_d; /* C24:Dynamic */ 9007 uint32 num_hg_ports_d; /* C25:Dynamic */ 9008 uint32 mmu_line_rate_hg; /*C26*/ 9009 uint32 num_hg_int_ports_d; /* C27:Dynamic */ 9010 uint32 num_egr_queue_per_int_hg_port_d; /* C28:Dynamic */ 9011 uint32 num_hg_ext_ports_d; /* C29:Dynamic */ 9012 uint32 num_egr_queue_per_ext_hg_port_d; /* C30:Dynamic */ 9013 uint32 mmu_num_cpu_port; /*C31*/ 9014 uint32 mmu_num_cpu_queue; /*C32*/ 9015 uint32 cpu_port_int_ext_bounding_d_c; /* C33:Dynamic */ 9016 uint32 mmu_num_loopback_port; /*C34*/ 9017 uint32 mmu_num_loopback_queue; /*C35*/ 9018 uint32 mmu_num_ep_redirection_queue; /*C36*/ 9019 uint32 mmu_num_olp_port_d; /*C37*/ 9020 uint32 mmu_num_olp_queue; /*C38*/ 9021 uint32 olp_port_int_ext_bounding_d_c; /* C39:Dynamic */ 9022 uint32 mmu_int_buf_size; /*C41:2048KB=2MB*/ 9023 uint32 mmu_available_int_buf_size_d; /*C42:1434KB */ 9024 uint32 mmu_reserved_int_buf_cells; /*C43:100 Cells */ 9025 uint32 mmu_reserved_int_buf_ema_pool_size_d; /*C44:614KB */ 9026 uint32 internal_buffer_reduction_d_c; /* C45:Dynamic */ 9027 uint32 mmu_ext_buf_size; /*C46*/ 9028 uint32 mmu_egress_queue_entries; /*C47*/ 9029 uint32 mmu_ep_redirect_queue_entries; /*C48*/ 9030 uint32 mmu_exp_num_of_repl_per_pkt; /*C49*/ 9031 uint32 mmu_repl_engine_work_queue_entries; /*C50*/ 9032 uint32 mmu_repl_engine_work_queue_in_device;/*C51*/ 9033 uint32 mmu_ema_queues; /*C52*/ 9034 /* 9035 float kt2_baf_profile_indexes[]={0.015625,0.03125,0.0625, 9036 0.125,0.25,0.5,1.0,2.0,4.0,8.0}; 9037 */ 9038 uint32 num_cells_rsrvd_ing_ext_buf; /* C54:Dynamic */ 9039 uint32 per_cos_res_cells_for_int_buff_d; /* C55:Dynamic */ 9040 uint32 per_cos_res_cells_for_ext_buff_d; /* C56:Dynamic */ 9041 uint32 mmu_ing_port_dyn_thd_param; /*C57*/ 9042 uint32 mmu_ing_pg_dyn_thd_param; /*C58*/ 9043 uint32 mmu_egr_queue_dyn_thd_param; /*C59*/ 9044 uint32 mmu_egr_pg_dyn_thd_param; /*C60*/ 9045 uint32 mmu_ing_cell_buf_reduction; /*C61 */ 9046 uint32 mmu_ing_pkt_buf_reduction; /*C62 */ 9047 } _soc_kt2_mmu_params_t; 9048 _soc_kt2_mmu_params_t _soc_kt2_mmu_params={0}; 9049 9050 typedef struct _general_info { 9051 uint32 max_packet_size_in_cells; /* C68 */ 9052 uint32 jumbo_frame_for_int_buff; /* C69 */ 9053 uint32 jumbo_frame_for_ext_buff; /* C70 */ 9054 uint32 ether_mtu_cells_for_int_buff; /* C72 */ 9055 uint32 ether_mtu_cells_for_ext_buff; /* C73 */ 9056 uint32 total_num_of_ports; /* C75 */ 9057 uint32 total_num_of_ports_excl_lpbk; /* C76 */ 9058 uint32 total_num_of_ports_excl_lpbk_olp; /* C77 */ 9059 uint32 total_num_of_ports_excl_lpbk_olp_cpu; /* C78 */ 9060 uint32 port_bw_bound_to_ext_buff; /* C79 */ 9061 uint32 total_egr_queues_for_a_int_ge_ports; /* C80 */ 9062 uint32 total_egr_queues_for_a_ext_ge_ports; /* C81 */ 9063 uint32 total_egr_queues_for_a_int_hg_ports; /* C82 */ 9064 uint32 total_egr_queues_for_a_ext_hg_ports; /* C83 */ 9065 uint32 total_cpu_queues; /* C84 */ 9066 uint32 total_int_buff_queues; /* C85 */ 9067 uint32 total_ext_buff_queues; /* C86 */ 9068 uint32 total_ema_queues; /* C87 */ 9069 uint32 total_egr_queues_in_device; /* C90 */ 9070 uint32 max_int_cell_buff_size; /* C91 */ 9071 uint32 int_cell_buff_size_after_limitation; /* C92 */ 9072 uint32 src_packing_fifo; /* C93 */ 9073 uint32 int_buff_pool; /* C94 */ 9074 uint32 ema_pool; /* C95 */ 9075 uint32 max_ext_cell_buff_size; /* C96 */ 9076 uint32 ratio_of_ext_buff_to_int_buff_size; /* C99 */ 9077 uint32 int_buff_cells_per_avg_size_pkt; /* C100 */ 9078 uint32 ext_buff_cells_per_avg_size_pkt; /* C101 */ 9079 uint32 max_prop_of_buff_used_by_one_queue_port; /* C102*/ 9080 }_general_info_t; 9081 9082 typedef struct _input_port_threshold_t { 9083 uint32 global_hdrm_cells_for_int_buff_pool; /* C107 */ 9084 uint32 global_hdrm_cells_for_ext_buff_pool; /* C108 */ 9085 uint32 global_hdrm_cells_for_RE_WQEs; /* C109 */ 9086 uint32 global_hdrm_cells_for_EQEs; /* C110 */ 9087 9088 uint32 hdrm_int_buff_cells_for_10G_PG; /* C112 */ 9089 uint32 hdrm_ext_buff_cells_for_10G_PG; /* C113 */ 9090 uint32 hdrm_RE_WQEs_pkts_for_10G_PG; /* C114 */ 9091 uint32 hdrm_EQEs_pkts_for_10G_PG; /* C115 */ 9092 9093 uint32 hdrm_int_buff_cells_for_10G_total_PG; /* C117 */ 9094 uint32 hdrm_ext_buff_cells_for_10G_total_PG; /* C118 */ 9095 uint32 hdrm_RE_WQEs_pkts_for_10G_total_PG; /* C119 */ 9096 uint32 hdrm_EQEs_pkts_for_10G_total_PG; /* C120 */ 9097 9098 uint32 hdrm_int_buff_cells_for_1G_PG; /* C122 */ 9099 uint32 hdrm_ext_buff_cells_for_1G_PG; /* C123 */ 9100 uint32 hdrm_RE_WQEs_pkts_for_1G_PG; /* C124 */ 9101 uint32 hdrm_EQEs_pkts_for_1G_PG; /* C125 */ 9102 9103 uint32 hdrm_int_buff_cells_for_1G_total_PG; /* C127 */ 9104 uint32 hdrm_ext_buff_cells_for_1G_total_PG; /* C128 */ 9105 uint32 hdrm_RE_WQEs_pkts_for_1G_total_PG; /* C129 */ 9106 uint32 hdrm_EQEs_pkts_for_1G_total_PG; /* C130 */ 9107 9108 uint32 hdrm_int_buff_cells_for_olp_port; /* C132 */ 9109 uint32 hdrm_ext_buff_cells_for_olp_port; /* C133 */ 9110 uint32 hdrm_RE_WQEs_pkts_for_olp_port; /* C134 */ 9111 uint32 hdrm_EQEs_pkts_for_olp_port; /* C135 */ 9112 9113 uint32 hdrm_int_buff_cells_for_lpbk_port; /* C137 */ 9114 uint32 hdrm_ext_buff_cells_for_lpbk_port; /* C138 */ 9115 uint32 hdrm_RE_WQEs_pkts_for_lpbk_port; /* C139 */ 9116 uint32 hdrm_EQEs_pkts_for_lpbk_port; /* C140 */ 9117 9118 uint32 hdrm_int_buff_cells_for_cpu_port; /* C142 */ 9119 uint32 hdrm_ext_buff_cells_for_cpu_port; /* C143 */ 9120 uint32 hdrm_RE_WQEs_pkts_for_cpu_port; /* C144 */ 9121 uint32 hdrm_EQEs_pkts_for_cpu_port; /* C145 */ 9122 9123 uint32 total_hdrm_int_buff_cells; /* C147 */ 9124 uint32 total_hdrm_int_buff_ema_pool_cells; /* C148 */ 9125 uint32 total_hdrm_ext_buff_cells; /* C149 */ 9126 uint32 total_hdrm_RE_WQEs_pkts; /* C150 */ 9127 uint32 total_hdrm_EQEs_pkts; /* C151 */ 9128 9129 uint32 min_int_buff_cells_per_PG; /* C153 */ 9130 uint32 min_int_buff_ema_pool_cells_per_PG; /* C154 */ 9131 uint32 min_ext_buff_cells_per_PG; /* C155 */ 9132 uint32 min_RE_WQEs_pkt_per_PG; /* C156 */ 9133 uint32 min_EQEs_pkt_per_PG; /* C157 */ 9134 9135 uint32 min_int_buff_cells_for_total_PG; /* C159 */ 9136 uint32 min_int_buff_ema_pool_cells_for_total_PG; /* C160 */ 9137 uint32 min_ext_buff_cells_for_total_PG; /* C161 */ 9138 uint32 min_RE_WQEs_pkts_for_total_PG; /* C162 */ 9139 uint32 min_EQEs_pkts_for_total_PG; /* C163 */ 9140 9141 uint32 min_int_buff_cells_for_a_port; /* C165 */ 9142 uint32 min_int_buff_ema_pool_cells_for_a_port; /* C166 */ 9143 uint32 min_ext_buff_cells_for_a_port; /* C167 */ 9144 uint32 min_RE_WQEs_pkts_for_a_port; /* C168 */ 9145 uint32 min_EQEs_pkts_for_a_port; /* C169 */ 9146 9147 uint32 min_int_buff_cells_for_total_port; /* C171 */ 9148 uint32 min_int_buff_ema_pool_cells_for_total_port; /* C172 */ 9149 uint32 min_ext_buff_cells_for_total_port; /* C173 */ 9150 uint32 min_RE_WQEs_pkts_for_total_port; /* C174 */ 9151 uint32 min_EQEs_pkts_for_total_port; /* C175 */ 9152 9153 uint32 total_min_int_buff_cells; /* C177 */ 9154 uint32 total_min_int_buff_ema_pool_cells; /* C178 */ 9155 uint32 total_min_ext_buff_cells; /* C179 */ 9156 uint32 total_min_RE_WQEs_pkts; /* C180 */ 9157 uint32 total_min_EQEs_pkts; /* C181 */ 9158 9159 uint32 total_shared_ing_buff_pool; /* C183 */ 9160 uint32 total_shared_EMA_buff; /* C184 */ 9161 uint32 total_shared_ext_buff; /* C185 */ 9162 uint32 total_shared_RE_WQEs_buff; /* C186 */ 9163 uint32 total_shared_EQEs_buff; /* C187 */ 9164 9165 uint32 ingress_burst_cells_size_for_one_port; /* C189 */ 9166 uint32 ingress_burst_pkts_size_for_one_port; /* C190 */ 9167 uint32 ingress_burst_cells_size_for_all_ports; /* C191 */ 9168 uint32 ingress_total_shared_cells_use_for_all_port; /* C192 */ 9169 uint32 ingress_burst_pkts_size_for_all_port; /* C193 */ 9170 uint32 ingress_total_shared_pkts_use_for_all_port; /* C194 */ 9171 uint32 ingress_total_shared_hdrm_cells_use_for_all_port; /* C195 */ 9172 uint32 ingress_total_shared_hdrm_pkts_use_for_all_port; /* C196 */ 9173 9174 }_input_port_threshold_t; 9175 9176 typedef struct _output_port_threshold_t { 9177 uint32 min_grntd_res_queue_cells_int_buff; /* C201 */ 9178 uint32 min_grntd_res_queue_cells_ext_buff; /* C202 */ 9179 uint32 min_grntd_res_queue_cells_EQEs; /* C203 */ 9180 uint32 min_grntd_res_EMA_queue_cells; /* C204 */ 9181 uint32 min_grntd_res_RE_WQs_cells; /* C205 */ 9182 uint32 min_grntd_res_RE_WQs_queue_cells_for_int_buff; /* C206 */ 9183 uint32 min_grntd_res_RE_WQs_queue_cells_for_ext_buff; /* C207 */ 9184 uint32 min_grntd_res_EP_redirect_queue_entry_cells; /* C208 */ 9185 9186 uint32 min_grntd_tot_res_queue_cells_int_buff; /* C210 */ 9187 uint32 min_grntd_tot_res_queue_cells_ext_buff; /* C211 */ 9188 uint32 min_grntd_tot_res_queue_cells_EQEs; /* C212 */ 9189 uint32 min_grntd_tot_res_EMA_queue_cells; /* C213 */ 9190 uint32 min_grntd_tot_res_RE_WQs_cells; /* C214 */ 9191 uint32 min_grntd_tot_res_RE_WQs_queue_cells_for_int_buff;/* C215 */ 9192 uint32 min_grntd_tot_res_RE_WQs_queue_cells_for_ext_buff;/* C216 */ 9193 uint32 min_grntd_tot_res_EP_redirect_queue_entry_cells; /* C217 */ 9194 9195 uint32 min_grntd_tot_shr_queue_cells_int_buff; /* C219 */ 9196 uint32 min_grntd_tot_shr_queue_cells_ext_buff; /* C220 */ 9197 uint32 min_grntd_tot_shr_queue_cells_EQEs; /* C221 */ 9198 uint32 min_grntd_tot_shr_EMA_queue_cells; /* C222 */ 9199 uint32 min_grntd_tot_shr_RE_WQs_cells; /* C223 */ 9200 uint32 min_grntd_tot_shr_RE_WQs_queue_cells_for_int_buff;/* C224 */ 9201 uint32 min_grntd_tot_shr_RE_WQs_queue_cells_for_ext_buff;/* C225 */ 9202 uint32 min_grntd_tot_shr_EP_redirect_queue_entry_cells; /* C226 */ 9203 9204 uint32 egress_queue_dynamic_threshold_parameter; /* C227 */ 9205 uint32 egress_burst_cells_size_for_one_queue; /* C228 */ 9206 uint32 egress_burst_pkts_size_for_one_queue; /* C229 */ 9207 uint32 egress_burst_cells_size_for_all_ports; /* C230 */ 9208 uint32 egress_burst_pkts_size_for_all_ports; /* C231 */ 9209 uint32 egress_burst_cells_size_for_all_queues; /* C232 */ 9210 uint32 egress_burst_pkts_size_for_all_queues; /* C233 */ 9211 uint32 egress_total_use_in_cells_for_all_queues; /* C234 */ 9212 uint32 egress_total_use_in_pkts_for_all_queues; /* C235 */ 9213 uint32 egress_remaining_cells_for_all_queues; /* C236 */ 9214 uint32 egress_remaining_pkts_for_all_queues; /* C237 */ 9215 9216 }_output_port_threshold_t; 9217 9218 typedef struct _soc_kt2_mmu_intermediate_results { 9219 _general_info_t general_info; 9220 _input_port_threshold_t input_port_threshold; 9221 _output_port_threshold_t output_port_threshold; 9222 }_soc_kt2_mmu_intermediate_results_t; 9223 _soc_kt2_mmu_intermediate_results_t _soc_kt2_mmu_intermediate_results={{0}}; 9224 9225 static soc_ser_functions_t _kt2_ser_functions; 9226 static soc_oam_event_functions_t _kt2_oam_event_functions; 9227 9228 #ifdef BCM_WARM_BOOT_SUPPORT 9229 static 9230 void _soc_kt2_mem_config_set(int unit, char *config_str, char *config_value); 9231 #endif 9232 void _soc_kt2_mem_config(int unit); 9233 9234 typedef enum { 9235 _SOC_COUNTER_TYPE_DROP_ENQ, 9236 _SOC_COUNTER_TYPE_ACCEPT_ENQ, 9237 _SOC_COUNTER_TYPE_DROP_ENQ_GREEN, 9238 _SOC_COUNTER_TYPE_DROP_ENQ_YELLOW, 9239 _SOC_COUNTER_TYPE_DROP_ENQ_RED, 9240 _SOC_COUNTER_TYPE_ACCEPT_ENQ_GREEN, 9241 _SOC_COUNTER_TYPE_ACCEPT_ENQ_YELLOW, 9242 _SOC_COUNTER_TYPE_ACCEPT_ENQ_RED, 9243 _SOC_COUNTER_TYPE_ACCEPT_DEQ, 9244 _SOC_COUNTER_TYPE_MAX 9245 } _soc_katana2_counter_type_t; 9246 9247 typedef struct _soc_katana2_counter_info_s { 9248 _soc_katana2_counter_type_t type; 9249 int index; 9250 int segment; 9251 } _soc_katana2_counter_info_t; 9252 9253 STATIC _soc_katana2_counter_info_t _soc_katana2_counter_info[] = { 9254 { _SOC_COUNTER_TYPE_DROP_ENQ, 0x0, 0 }, 9255 { _SOC_COUNTER_TYPE_ACCEPT_ENQ, 0x0, 0 }, 9256 /* green pkt drops, index = ACCEPT=1'b0, COLOR=2'b00 */ 9257 { _SOC_COUNTER_TYPE_DROP_ENQ_GREEN, 0x0, 0 }, 9258 /* yellow pkt drops, index = ACCEPT=1'b0, COLOR=2'b11 */ 9259 { _SOC_COUNTER_TYPE_DROP_ENQ_YELLOW, 0x3, 0 }, 9260 /* red pkt drops, index = ACCEPT=1'b0, COLOR=2'b01 */ 9261 { _SOC_COUNTER_TYPE_DROP_ENQ_RED, 0x1, 0 }, 9262 /* green accepted pkts, index = ACCEPT=1'b1, COLOR=2'b00 */ 9263 { _SOC_COUNTER_TYPE_ACCEPT_ENQ_GREEN, 0x4, 0 }, 9264 /* yellow accepted pkts, index = ACCEPT=1'b1, COLOR=2'b11 */ 9265 { _SOC_COUNTER_TYPE_ACCEPT_ENQ_YELLOW, 0x7, 0 }, 9266 /* red accepted pkts, index = ACCEPT=1'b1, COLOR=2'b01 */ 9267 { _SOC_COUNTER_TYPE_ACCEPT_ENQ_RED, 0x5, 0 }, 9268 { _SOC_COUNTER_TYPE_ACCEPT_DEQ, 0, 0 } 9269 }; 9270 9271 #define _SOC_WC40_RX_LANE_MAP_DEFAULT 0x3210 9272 #define _SOC_UNICORE_RX_LANE_MAP_DEFAULT 0x0123 9273 9274 int 9275 _soc_kt2_l1_port_mx_lane_map_init(int unit) 9276 { 9277 bcm_port_t port; 9278 uint32 default_lane_map, lane_map; 9279 int mxqblk_update[KT2_MAX_MXQBLOCKS] = {0,0,0,0,0,0,0,0,0,0}; 9280 9281 for (port = 1; port < COUNTOF(_kt2_l1_port_mx_lane_map); port++) { 9282 uint32 i, mxqblock, mxqblock_i, lane[4]; 9283 9284 mxqblock = (*kt2_port_to_mxqblock[unit])[port-1]; 9285 if (mxqblk_update[mxqblock] == 1) { 9286 continue; 9287 } 9288 /* Get lane map, if it is default value, then go to next */ 9289 default_lane_map = _kt2_l1_port_mx_lane_map[port].unicore_or_warpcore ? 9290 _SOC_WC40_RX_LANE_MAP_DEFAULT : _SOC_UNICORE_RX_LANE_MAP_DEFAULT; 9291 lane_map = soc_property_port_get(unit, port, 9292 spn_XGXS_RX_LANE_MAP, default_lane_map); 9293 if (lane_map == default_lane_map) { 9294 continue; 9295 } 9296 9297 /* Decouple the lane number for lane map */ 9298 for (i = 0; i < 4; i++) { 9299 if (_kt2_l1_port_mx_lane_map[port].unicore_or_warpcore) { 9300 lane[i] = (lane_map >> (i*4)) & 0xf; 9301 } else { 9302 lane[i] = (lane_map >> ((3-i)*4)) & 0xf; 9303 } 9304 } 9305 9306 /* set _kt2_l1_port_mx_lane_map based on lane map */ 9307 for (i = 0; i < 4; i++) { 9308 /* coverity[overrun-local : FALSE] */ 9309 mxqblock_i = (*kt2_port_to_mxqblock[unit])[port+i-1]; 9310 if (mxqblock_i != mxqblock) { 9311 /*Don't remap if port+i belongs to different block*/ 9312 break; 9313 } 9314 9315 /* coverity[overrun-local : FALSE] */ 9316 _kt2_l1_port_mx_lane_map[port+i].lane_num = lane[i]; 9317 } 9318 /*Update each block only once*/ 9319 mxqblk_update[mxqblock] = 1; 9320 } 9321 return BCM_E_NONE; 9322 } 9323 9324 #define KT2_MAX_SERVICE_POOLS 4 9325 #define KT2_MAX_PRIORITY_GROUPS 8 9326 9327 soc_error_t _katana2_get_wc_phy_info(int unit, 9328 soc_port_t port, 9329 uint8 *phy_mode) 9330 { 9331 bcmMxqCorePortMode_t mode = bcmMxqCorePortModeSingle; 9332 char *intf_type = NULL; 9333 uint32 rxaui = 0; 9334 soc_info_t *si; 9335 bcmMxqPhyPortMode_t p_mode = bcmMxqPhyPortModeSingle; 9336 9337 *phy_mode = PHYCTRL_QUAD_LANE_PORT; /* XAUI */ 9338 si = &SOC_INFO(unit); 9339 9340 if (IS_GE_PORT(unit, port)) { 9341 LOG_VERBOSE(BSL_LS_SOC_COMMON, 9342 (BSL_META_U(unit,"\n GE port so forced Single Lane GMII\n"))); 9343 if (si->port_speed_max[port] == 2500) { 9344 SOC_IF_ERROR_RETURN( 9345 soc_katana2_get_phy_port_mode(unit, port, 2500, &p_mode)); 9346 *phy_mode = (p_mode == bcmMxqPhyPortModeDual)? PHYCTRL_SINGLE_LANE_IN_DUAL_PORT_MODE : PHYCTRL_ONE_LANE_PORT; 9347 } else { 9348 *phy_mode = PHYCTRL_ONE_LANE_PORT; 9349 } 9350 return SOC_E_NONE; 9351 } 9352 if (IS_HG_PORT(unit, port)) { 9353 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 9354 "\n HG port so Forced Four Lanes XGMII \n"))); 9355 *phy_mode = PHYCTRL_QUAD_LANE_PORT; 9356 return SOC_E_NONE; 9357 } 9358 if (IS_XE_PORT(unit, port)) { 9359 SOC_IF_ERROR_RETURN( 9360 soc_katana2_get_core_port_mode(unit, port, &mode)); 9361 if (mode == bcmMxqCorePortModeQuad) { 9362 LOG_WARN(BSL_LS_SOC_COMMON, 9363 (BSL_META_U(unit, 9364 "\n Internal Error. 4 XE ports not possible \n"))); 9365 return SOC_E_INTERNAL; 9366 } 9367 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 9368 "\n Checking %s config setting \n"), spn_SERDES_IF_TYPE)); 9369 intf_type= soc_property_port_get_str(unit, port, spn_SERDES_IF_TYPE); 9370 9371 if (intf_type != NULL) { 9372 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 9373 "\n As per %s config setting \n"), spn_SERDES_IF_TYPE)); 9374 if ((sal_strcmp(intf_type, "XAUI") == 0) || 9375 (sal_strcmp(intf_type, "xaui") == 0)) { 9376 if (mode == bcmMxqCorePortModeSingle) { 9377 *phy_mode = PHYCTRL_QUAD_LANE_PORT; 9378 return SOC_E_NONE; 9379 } else { 9380 LOG_WARN(BSL_LS_SOC_COMMON, 9381 (BSL_META_U(unit, 9382 "Discarded XAUI setting.Faliing through\n"))); 9383 } 9384 } 9385 if ((sal_strcmp(intf_type, "RXAUI") == 0) || 9386 (sal_strcmp(intf_type, "rxaui") == 0)) { 9387 *phy_mode = PHYCTRL_DUAL_LANE_PORT; 9388 return SOC_E_NONE; 9389 } 9390 if ((sal_strcmp(intf_type, "XFI") == 0) || 9391 (sal_strcmp(intf_type, "xfi") == 0)) { 9392 *phy_mode = PHYCTRL_ONE_LANE_PORT; 9393 return SOC_E_NONE; 9394 } 9395 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 9396 "\n Interface Type: %s " 9397 "Supports only XAUI,RXAUI & XFI so falling through"), 9398 intf_type)); 9399 } 9400 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 9401 "\n Checking %s config setting \n"), spn_SERDES_RXAUI_MODE)); 9402 rxaui = soc_property_port_get(unit, port, 9403 spn_SERDES_RXAUI_MODE, 0xFF); 9404 if ((rxaui == 0) || (rxaui == 1)) { 9405 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 9406 "\nAs per %s config setting\n"), spn_SERDES_RXAUI_MODE)); 9407 if (rxaui == 1) { 9408 *phy_mode = PHYCTRL_DUAL_LANE_PORT; /* Reduced XAUI */ 9409 } else { 9410 *phy_mode = PHYCTRL_QUAD_LANE_PORT; /* XAUI */ 9411 } 9412 return SOC_E_NONE; 9413 } 9414 if (rxaui == 0xFF) { /* Not defined */ 9415 if (mode == bcmMxqCorePortModeDual) { 9416 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 9417 "\n Two XE ports so Could be either RXAUI/XFI" 9418 "\n so assuing XFI \n"))); 9419 *phy_mode = PHYCTRL_ONE_LANE_PORT; /* XFI */ 9420 return SOC_E_NONE; 9421 } 9422 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 9423 "\nOne XE ports so decision as per original config=%s setting\n"), 9424 spn_PORTGROUP)); 9425 return SOC_E_EMPTY; /* Not Sure what to do */ 9426 9427 /* if (mode == bcmMxqCorePortModeSingle) */ 9428 /* Fall through and go as per original setting */ 9429 } 9430 } 9431 return SOC_E_NONE; 9432 } 9433 9434 STATIC int 9435 soc_flex_io_operation_status_get(int unit, int *flex_io_operation_ongoing) 9436 { 9437 9438 SOC_FLEXIO_LOCK; 9439 *flex_io_operation_ongoing = flex_io_operation_busy[unit]; 9440 SOC_FLEXIO_UNLOCK; 9441 return SOC_E_NONE; 9442 } 9443 9444 int soc_flex_io_operation_status_set(int unit, int value) 9445 { 9446 SOC_FLEXIO_LOCK; 9447 flex_io_operation_busy[unit] = value; 9448 SOC_FLEXIO_UNLOCK; 9449 return SOC_E_NONE; 9450 } 9451 9452 soc_error_t katana2_get_wc_phy_info(int unit, 9453 soc_port_t port, 9454 uint8 *lane_num, 9455 uint8 *phy_mode, 9456 uint8 *chip_num) 9457 { 9458 uint32 mxqblock=0; 9459 uint32 num_lanes=0; 9460 bcmMxqConnection_t connection=bcmMqxConnectionUniCore; 9461 soc_error_t rv = SOC_E_NONE; 9462 int flex_io_operation_ongoing = 0; 9463 9464 /* 9465 pc->chip_num = 0; 9466 pc->lane_num = 0; 9467 pc->phy_mode = PHYCTRL_ONE_LANE_PORT | 9468 PHYCTRL_DUAL_LANE_PORT | 9469 PHYCTRL_QUAD_LANE_PORT; 9470 */ 9471 mxqblock = (*kt2_port_to_mxqblock[unit])[port-1]; 9472 if ((mxqblock == 6) || (mxqblock == 7)) { 9473 /* Check XFI mode then */ 9474 SOC_IF_ERROR_RETURN(soc_katana2_get_phy_connection_mode( 9475 unit,port,mxqblock,&connection)); 9476 if (connection == bcmMqxConnectionUniCore) { 9477 return SOC_E_PARAM; 9478 } 9479 if (mxqblock == 6) { 9480 *chip_num = 0; 9481 } else { 9482 *chip_num = 1; 9483 } 9484 *lane_num = (((*kt2_port_to_mxqblock_subports[unit])[port-1])+1); 9485 } else { 9486 if (!((mxqblock == 8) || (mxqblock == 9))) { 9487 return SOC_E_PARAM; 9488 } 9489 if (mxqblock == 8) { 9490 *chip_num = 0; 9491 } else { 9492 *chip_num = 1; 9493 } 9494 *lane_num = (*kt2_port_to_mxqblock_subports[unit])[port-1]; 9495 } 9496 soc_flex_io_operation_status_get(unit, &flex_io_operation_ongoing); 9497 if (flex_io_operation_ongoing) { 9498 rv = _katana2_get_wc_phy_info(unit, port, phy_mode); 9499 if (rv != SOC_E_EMPTY) { 9500 return rv; 9501 } 9502 } 9503 9504 9505 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 9506 "Checking config %s settings \n"), spn_PORTGROUP)); 9507 num_lanes = soc_property_port_get(unit, port, spn_PORTGROUP, 0); 9508 switch(num_lanes) { 9509 case 1: *phy_mode = PHYCTRL_ONE_LANE_PORT; 9510 break; 9511 case 2: *phy_mode = PHYCTRL_DUAL_LANE_PORT; 9512 break; 9513 case 4: *phy_mode = PHYCTRL_QUAD_LANE_PORT; 9514 break; 9515 default: 9516 if (!flex_io_operation_ongoing) { 9517 rv = _katana2_get_wc_phy_info(unit, port, phy_mode); 9518 if (rv == SOC_E_EMPTY) { 9519 LOG_WARN(BSL_LS_SOC_COMMON, 9520 (BSL_META_U(unit, 9521 "\nWARN:Unpredictable results could be observed " 9522 "\nPlease use below serdes config variables for WC port:%d\n" 9523 "either serdes_rxaui_mode, portgroup or serdes_if_type\n"), 9524 port)); 9525 } 9526 } 9527 } 9528 return SOC_E_NONE; 9529 } 9530 9531 /* kt2_mmu_ext_buf_cell_size = (kt2_mmu_int_buf_cell_size+2)*15;*/ 9532 STATIC 9533 uint32 ceil_func(uint32 numerators , uint32 denominator) 9534 { 9535 uint32 result; 9536 if (denominator == 0) { 9537 return 0xFFFFFFFF; 9538 } 9539 result = numerators / denominator; 9540 if (numerators % denominator != 0) { 9541 result++; 9542 } 9543 return result; 9544 } 9545 STATIC 9546 uint32 floor_func(uint32 numerators , uint32 denominator) 9547 { 9548 uint32 result; 9549 if (denominator == 0) { 9550 return 0xFFFFFFFF; 9551 } 9552 result = numerators / denominator; 9553 /* 9554 if (numerators % denominator != 0) { 9555 result--; 9556 } 9557 */ 9558 return result; 9559 } 9560 STATIC 9561 int _soc_katana2_mmu_config_extra_queue(int unit, uint32 queue) 9562 { 9563 mmu_thdo_qconfig_cell_entry_t mmu_thdo_qconfig_cell_entry={{0}}; 9564 mmu_thdo_qoffset_cell_entry_t mmu_thdo_qoffset_cell_entry={{0}}; 9565 mmu_thdo_qconfig_qentry_entry_t mmu_thdo_qconfig_qentry_entry={{0}}; 9566 mmu_thdo_qoffset_qentry_entry_t mmu_thdo_qoffset_qentry_entry={{0}}; 9567 /* 1. MMU_THDO_QCONFIG_CELL */ 9568 SOC_IF_ERROR_RETURN(READ_MMU_THDO_QCONFIG_CELLm(unit, 9569 MEM_BLOCK_ANY, queue, 9570 &mmu_thdo_qconfig_cell_entry)); 9571 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, 9572 &mmu_thdo_qconfig_cell_entry, 9573 Q_MIN_CELLf, 0); 9574 /* output_port_threshold->min_grntd_res_queue_cells_int_buff);*/ 9575 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, 9576 &mmu_thdo_qconfig_cell_entry, 9577 Q_SHARED_LIMIT_CELLf, 7); 9578 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, 9579 &mmu_thdo_qconfig_cell_entry, 9580 Q_LIMIT_DYNAMIC_CELLf, 1); 9581 /* _soc_kt2_mmu_params.lossless_mode_d_c ? 0 : 1); */ 9582 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, 9583 &mmu_thdo_qconfig_cell_entry, 9584 Q_LIMIT_ENABLE_CELLf, 1); 9585 /* _soc_kt2_mmu_params.lossless_mode_d_c ? 0 : 1); */ 9586 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, 9587 &mmu_thdo_qconfig_cell_entry, 9588 Q_COLOR_ENABLE_CELLf,0); 9589 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, 9590 &mmu_thdo_qconfig_cell_entry, 9591 Q_COLOR_LIMIT_DYNAMIC_CELLf, 1); 9592 /* _soc_kt2_mmu_params.lossless_mode_d_c ? 0 : 1); */ 9593 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, 9594 &mmu_thdo_qconfig_cell_entry, 9595 LIMIT_YELLOW_CELLf, 0); 9596 SOC_IF_ERROR_RETURN(WRITE_MMU_THDO_QCONFIG_CELLm(unit, 9597 MEM_BLOCK_ALL, queue, 9598 &mmu_thdo_qconfig_cell_entry)); 9599 9600 /* 2. MMU_THDO_QOFFSET_CELL */ 9601 SOC_IF_ERROR_RETURN(READ_MMU_THDO_QOFFSET_CELLm(unit, 9602 MEM_BLOCK_ANY,queue, &mmu_thdo_qoffset_cell_entry)); 9603 soc_mem_field32_set(unit, MMU_THDO_QOFFSET_CELLm, 9604 &mmu_thdo_qoffset_cell_entry, 9605 RESET_OFFSET_CELLf,2); 9606 soc_mem_field32_set(unit, MMU_THDO_QOFFSET_CELLm, 9607 &mmu_thdo_qoffset_cell_entry, 9608 RESET_OFFSET_YELLOW_CELLf, 2); 9609 soc_mem_field32_set(unit, MMU_THDO_QOFFSET_CELLm, 9610 &mmu_thdo_qoffset_cell_entry, 9611 RESET_OFFSET_RED_CELLf, 2); 9612 SOC_IF_ERROR_RETURN(WRITE_MMU_THDO_QOFFSET_CELLm(unit, 9613 MEM_BLOCK_ALL,queue, &mmu_thdo_qoffset_cell_entry)); 9614 9615 /* 3. MMU_THDO_QCONFIG_QENTRY */ 9616 SOC_IF_ERROR_RETURN(READ_MMU_THDO_QCONFIG_QENTRYm(unit, 9617 MEM_BLOCK_ANY,queue, &mmu_thdo_qconfig_qentry_entry)); 9618 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_QENTRYm, 9619 &mmu_thdo_qconfig_qentry_entry, 9620 Q_MIN_QENTRYf, 0); 9621 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_QENTRYm, 9622 &mmu_thdo_qconfig_qentry_entry, 9623 Q_SHARED_LIMIT_QENTRYf, 7); 9624 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_QENTRYm, 9625 &mmu_thdo_qconfig_qentry_entry, 9626 Q_LIMIT_DYNAMIC_QENTRYf, 1); 9627 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_QENTRYm, 9628 &mmu_thdo_qconfig_qentry_entry, 9629 Q_LIMIT_ENABLE_QENTRYf, 1); 9630 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_QENTRYm, 9631 &mmu_thdo_qconfig_qentry_entry, 9632 Q_COLOR_ENABLE_QENTRYf, 0); 9633 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_QENTRYm, 9634 &mmu_thdo_qconfig_qentry_entry, 9635 Q_COLOR_LIMIT_DYNAMIC_QENTRYf, 1); 9636 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_QENTRYm, 9637 &mmu_thdo_qconfig_qentry_entry, 9638 LIMIT_YELLOW_QENTRYf, 1); 9639 SOC_IF_ERROR_RETURN(WRITE_MMU_THDO_QCONFIG_QENTRYm(unit, 9640 MEM_BLOCK_ALL,queue, &mmu_thdo_qconfig_qentry_entry)); 9641 9642 /* 4. MMU_THDO_QOFFSET_QENTRY */ 9643 SOC_IF_ERROR_RETURN(READ_MMU_THDO_QOFFSET_QENTRYm(unit, 9644 MEM_BLOCK_ANY,queue, &mmu_thdo_qoffset_qentry_entry)); 9645 soc_mem_field32_set(unit, MMU_THDO_QOFFSET_QENTRYm, 9646 &mmu_thdo_qoffset_qentry_entry, 9647 RESET_OFFSET_QENTRYf, 1); 9648 soc_mem_field32_set(unit, MMU_THDO_QOFFSET_QENTRYm, 9649 &mmu_thdo_qoffset_qentry_entry, 9650 RESET_OFFSET_YELLOW_QENTRYf, 1); 9651 soc_mem_field32_set(unit, MMU_THDO_QOFFSET_QENTRYm, 9652 &mmu_thdo_qoffset_qentry_entry, 9653 RESET_OFFSET_RED_QENTRYf, 1); 9654 SOC_IF_ERROR_RETURN(WRITE_MMU_THDO_QOFFSET_QENTRYm(unit, 9655 MEM_BLOCK_ALL,queue, &mmu_thdo_qoffset_qentry_entry)); 9656 return SOC_E_NONE; 9657 } 9658 9659 int 9660 _soc_kt2_packing_port_config_set(int unit, bcm_port_t port, int set) 9661 { 9662 uint32 mode = 0; 9663 mmu_toq_qpack_mode_entry_t qpack_entry; 9664 pbmp_t ext_pbmp; 9665 uint32 *bmap; 9666 int word, word_count, bit; 9667 int index = 0; 9668 9669 ext_pbmp = soc_property_get_pbmp(unit, spn_PBMP_EXT_MEM, 0); 9670 if (SOC_PBMP_MEMBER(ext_pbmp, port)) { 9671 bmap = SOC_CONTROL(unit)->port_lls_l2_bmap[port]; 9672 word_count = _SHR_BITDCLSIZE(soc_mem_index_count(unit, LLS_L2_PARENTm)); 9673 for (word = 0; word < word_count; word++) { 9674 if (bmap[word] == 0) { 9675 continue; 9676 } 9677 for (bit = 0; bit < SHR_BITWID; bit++) { 9678 if (!(bmap[word] & (1 << bit))) { 9679 continue; 9680 } 9681 index = word * SHR_BITWID + bit; 9682 SOC_IF_ERROR_RETURN 9683 (READ_MMU_TOQ_QPACK_MODEm(unit, MEM_BLOCK_ALL, 9684 index/16, &qpack_entry)); 9685 soc_mem_field_get(unit, MMU_TOQ_QPACK_MODEm, 9686 (uint32 *)&qpack_entry, 9687 QMODEf, &mode); 9688 9689 if (set) { 9690 mode |= (1 << (index % 16)); 9691 } else { 9692 mode &= ~(1 << (index % 16)); 9693 } 9694 9695 soc_mem_field32_set(unit, MMU_TOQ_QPACK_MODEm, 9696 &qpack_entry, QMODEf, mode); 9697 SOC_IF_ERROR_RETURN 9698 (WRITE_MMU_TOQ_QPACK_MODEm(unit, MEM_BLOCK_ALL, 9699 index/16, &qpack_entry)); 9700 } 9701 } 9702 } 9703 return BCM_E_NONE; 9704 } 9705 9706 int 9707 _soc_katana2_mmu_init_ext_mem_dyn_port(int unit,int port) 9708 { 9709 uint32 rval=0; 9710 soc_info_t *si= &SOC_INFO(unit); 9711 int depth = 0; 9712 int thereshold = 0; 9713 uint8 mxqblock=0; 9714 soc_pbmp_t my_pbmp_xport_xe; 9715 int num_lanes = 0; 9716 int speed = 0; 9717 uint8 loop; 9718 uint8 try_loop; 9719 int mxqblock_port; 9720 uint32 rval1 = 0; 9721 uint32 rval2 = 0; 9722 uint32 start_addr = 0; 9723 uint32 end_addr = 0; 9724 txlp_port_addr_map_table_entry_t txlp_port_addr_map_table_entry={{0}}; 9725 soc_field_t mmu_intf_reset_fld[] = { 9726 XQ0_MMU_INTF_RESETf, XQ1_MMU_INTF_RESETf, 9727 XQ2_MMU_INTF_RESETf, XQ3_MMU_INTF_RESETf, 9728 XQ4_MMU_INTF_RESETf, XQ5_MMU_INTF_RESETf, 9729 XQ6_MMU_INTF_RESETf, XQ7_MMU_INTF_RESETf}; 9730 uint32 try_count = 0; 9731 soc_timeout_t to = {0}; 9732 sal_usecs_t timeout_usec = 100000; 9733 int min_polls = 100; 9734 9735 SOC_IF_ERROR_RETURN(soc_katana2_get_port_mxqblock( 9736 unit,port,&mxqblock)); 9737 for (loop=0;loop<KT2_MAX_MXQPORTS_PER_BLOCK;loop++) { 9738 mxqblock_port=(*kt2_mxqblock_ports[unit])[mxqblock][loop]; 9739 if (SOC_PBMP_MEMBER((PBMP_ALL(unit)), mxqblock_port)) { 9740 if (!(IS_CPU_PORT(unit,mxqblock_port) || IS_LB_PORT(unit, 9741 mxqblock_port))) { 9742 SOC_PBMP_CLEAR(my_pbmp_xport_xe); 9743 my_pbmp_xport_xe = soc_property_get_pbmp_default(unit, 9744 spn_PBMP_XPORT_XE, my_pbmp_xport_xe); 9745 SOC_IF_ERROR_RETURN(_bcm_kt2_port_lanes_get(unit, 9746 mxqblock_port, &num_lanes)); 9747 if((SOC_PBMP_MEMBER(my_pbmp_xport_xe, mxqblock_port)) && 9748 ((mxqblock == 8) || (mxqblock == 9))) { 9749 speed = (*mxqspeeds[unit])[mxqblock][num_lanes - 1]; 9750 } 9751 } 9752 if (speed == 0) { 9753 speed = si->port_speed_max[mxqblock_port]; 9754 } 9755 SOC_IF_ERROR_RETURN(READ_DEQ_EFIFO_CFGr(unit, mxqblock_port, 9756 &rval)); 9757 if (speed <= 1000) { 9758 depth = (IS_EXT_MEM_PORT(unit, mxqblock_port)) ? 10 : 2; 9759 thereshold = (IS_EXT_MEM_PORT(unit, mxqblock_port)) ? 8 : 0; 9760 } else if (speed <= 2500) { 9761 depth = (IS_EXT_MEM_PORT(unit, mxqblock_port)) ? 14 : 2; 9762 thereshold = (IS_EXT_MEM_PORT(unit, mxqblock_port)) ? 12 : 0; 9763 } else if (speed <= 13000) { 9764 depth = (IS_EXT_MEM_PORT(unit, mxqblock_port)) ? 56 : 10; 9765 thereshold = (IS_EXT_MEM_PORT(unit, mxqblock_port)) ? 49 : 0; 9766 } else { /* > 13G */ 9767 depth = (IS_EXT_MEM_PORT(unit, mxqblock_port)) ? 112 : 16; 9768 thereshold = (IS_EXT_MEM_PORT(unit, mxqblock_port)) ? 85 : 0; 9769 } 9770 if ((IS_EXT_MEM_PORT(unit, mxqblock_port)) && 9771 !(PBMP_MEMBER(si->linkphy_pbm, mxqblock_port))) { 9772 soc_reg_field_set(unit, DEQ_EFIFO_CFGr, &rval, 9773 EGRESS_FIFO_XMIT_OVERSPEED_RATE_LIMITERf, 1); 9774 } else { 9775 soc_reg_field_set(unit, DEQ_EFIFO_CFGr, &rval, 9776 EGRESS_FIFO_XMIT_OVERSPEED_RATE_LIMITERf, 0); 9777 } 9778 soc_reg_field_set(unit, DEQ_EFIFO_CFGr, &rval, 9779 EGRESS_FIFO_XMIT_THRESHOLDf, thereshold); 9780 soc_reg_field_set(unit, DEQ_EFIFO_CFGr, &rval, 9781 EGRESS_FIFO_DEPTHf, depth); 9782 if (SOC_PBMP_MEMBER(si->linkphy_pbm, mxqblock_port)) { 9783 soc_reg_field_set(unit, DEQ_EFIFO_CFGr, &rval, 9784 EGRESS_FIFO_LINK_PHYf, 1); 9785 } 9786 SOC_IF_ERROR_RETURN(WRITE_DEQ_EFIFO_CFGr(unit, mxqblock_port, 9787 rval)); 9788 SOC_IF_ERROR_RETURN(_soc_katana2_mmu_init_phase4_port(unit, 9789 mxqblock_port)); 9790 /* Port BW Ctrl */ 9791 SOC_IF_ERROR_RETURN(READ_TOQ_PORT_BW_CTRLr(unit, mxqblock_port, 9792 &rval)); 9793 if (IS_CPU_PORT(unit,mxqblock_port) || IS_LB_PORT(unit, 9794 mxqblock_port)) { 9795 soc_reg_field_set(unit, TOQ_PORT_BW_CTRLr, &rval, 9796 PORT_BWf, 50); 9797 soc_reg_field_set(unit, TOQ_PORT_BW_CTRLr, &rval, 9798 START_THRESHOLDf, 127); 9799 } else if (speed >= 10000) { 9800 soc_reg_field_set(unit, TOQ_PORT_BW_CTRLr, &rval, 9801 PORT_BWf, 500); 9802 soc_reg_field_set(unit, TOQ_PORT_BW_CTRLr, &rval, 9803 START_THRESHOLDf, 34); 9804 } else if (speed == 2500) { 9805 soc_reg_field_set(unit, TOQ_PORT_BW_CTRLr, &rval, 9806 PORT_BWf, 125); 9807 soc_reg_field_set(unit, TOQ_PORT_BW_CTRLr, &rval, 9808 START_THRESHOLDf, 19); 9809 } else { 9810 soc_reg_field_set(unit, TOQ_PORT_BW_CTRLr, &rval, 9811 PORT_BWf, 50); 9812 soc_reg_field_set(unit, TOQ_PORT_BW_CTRLr, &rval, 9813 START_THRESHOLDf, 7); 9814 } 9815 SOC_IF_ERROR_RETURN(WRITE_TOQ_PORT_BW_CTRLr(unit, mxqblock_port, 9816 rval)); 9817 } else { 9818 if (SOC_PORT_VALID(unit, mxqblock_port)) { 9819 SOC_IF_ERROR_RETURN(WRITE_DEQ_EFIFO_CFGr(unit, mxqblock_port, 9820 0)); 9821 SOC_IF_ERROR_RETURN(WRITE_TOQ_PORT_BW_CTRLr(unit, 9822 mxqblock_port, 0)); 9823 } 9824 } 9825 } 9826 /* WORK-AROUND for port-flushing i.e. need to repeat below step twice */ 9827 for (try_loop = 0; try_loop < 2; try_loop++) { 9828 /* EP Reset */ 9829 if (SAL_BOOT_SIMULATION) { 9830 BCM_IF_ERROR_RETURN(WRITE_DYNAMIC_PORT_RECFG_VECTOR_CFG_31_00r( 9831 unit, 0)); 9832 BCM_IF_ERROR_RETURN(WRITE_DYNAMIC_PORT_RECFG_VECTOR_CFG_41_32r( 9833 unit, 0)); 9834 } 9835 for (loop=0;loop<KT2_MAX_MXQPORTS_PER_BLOCK;loop++) { 9836 mxqblock_port=(*kt2_mxqblock_ports[unit])[mxqblock][loop]; 9837 if (SOC_PBMP_MEMBER((PBMP_ALL(unit)), mxqblock_port)) { 9838 if (mxqblock_port <= 31) { 9839 rval1 |= (1 << mxqblock_port); 9840 } else { 9841 rval2 |= (1 << (mxqblock_port-32)); 9842 } 9843 } 9844 } 9845 BCM_IF_ERROR_RETURN(WRITE_DYNAMIC_PORT_RECFG_VECTOR_CFG_31_00r( 9846 unit, rval1)); 9847 BCM_IF_ERROR_RETURN(WRITE_DYNAMIC_PORT_RECFG_VECTOR_CFG_41_32r( 9848 unit, rval2)); 9849 if (SAL_BOOT_SIMULATION) { 9850 BCM_IF_ERROR_RETURN(WRITE_DYNAMIC_PORT_RECFG_VECTOR_CFG_31_00r( 9851 unit, 0)); 9852 BCM_IF_ERROR_RETURN(WRITE_DYNAMIC_PORT_RECFG_VECTOR_CFG_41_32r( 9853 unit, 0)); 9854 } 9855 try_count = 0; 9856 do { 9857 soc_timeout_init(&to, timeout_usec, min_polls); 9858 if(soc_timeout_check(&to)) { 9859 LOG_ERROR(BSL_LS_BCM_PORT, 9860 (BSL_META_U(unit, 9861 "TimeOut InternalError\n"))); 9862 return BCM_E_INTERNAL; 9863 } 9864 try_count++; 9865 BCM_IF_ERROR_RETURN(READ_DYNAMIC_PORT_RECFG_VECTOR_CFG_31_00r( 9866 unit, &rval1)); 9867 BCM_IF_ERROR_RETURN(READ_DYNAMIC_PORT_RECFG_VECTOR_CFG_41_32r( 9868 unit, &rval2)); 9869 if ((rval1 == 0) && (rval2 == 0)) { 9870 break; 9871 } 9872 } while (try_count != 3); 9873 if (try_count == 3) { 9874 return BCM_E_TIMEOUT; 9875 } 9876 } 9877 9878 if (mxqblock <= 7) { 9879 READ_EDATABUF_DBG_MMU_INTF_RESETr(unit, &rval); 9880 soc_reg_field_set(unit, EDATABUF_DBG_MMU_INTF_RESETr, 9881 &rval, mmu_intf_reset_fld[mxqblock], 1); 9882 WRITE_EDATABUF_DBG_MMU_INTF_RESETr(unit, rval); 9883 READ_EDATABUF_DBG_MMU_INTF_RESETr(unit, &rval); 9884 soc_reg_field_set(unit, EDATABUF_DBG_MMU_INTF_RESETr, 9885 &rval, mmu_intf_reset_fld[mxqblock], 0); 9886 WRITE_EDATABUF_DBG_MMU_INTF_RESETr(unit, rval); 9887 } 9888 if ((mxqblock >= 8) && (mxqblock <= 9)) { 9889 for (loop=0;loop<KT2_MAX_MXQPORTS_PER_BLOCK;loop++) { 9890 sal_memset(&txlp_port_addr_map_table_entry,0, 9891 sizeof(txlp_port_addr_map_table_entry_t)); 9892 mxqblock_port=(*kt2_mxqblock_ports[unit])[mxqblock][loop]; 9893 if (SOC_PBMP_MEMBER((PBMP_ALL(unit)), mxqblock_port)) { 9894 /* As each cell-occupies "4" lines in buffer, [end-start+1] 9895 must be a integral multiple of "4". */ 9896 if (si->port_speed_max[mxqblock_port]<= 2500) { 9897 end_addr = start_addr + (( 6 * 4) - 1); /* 6 Cells */ 9898 } else if (si->port_speed_max[mxqblock_port] <= 10000) { 9899 end_addr = start_addr + ((12 * 4) - 1); /* 12 Cells */ 9900 } else if (si->port_speed_max[mxqblock_port] <= 13000) { 9901 end_addr = start_addr + ((16 * 4) - 1); /* 16 Cells */ 9902 } else if (si->port_speed_max[mxqblock_port] <= 21000) { 9903 end_addr = start_addr + ((20 * 4) - 1); /* 20 Cells */ 9904 } 9905 soc_TXLP_PORT_ADDR_MAP_TABLEm_field_set(unit, 9906 &txlp_port_addr_map_table_entry,START_ADDRf,&start_addr); 9907 soc_TXLP_PORT_ADDR_MAP_TABLEm_field_set(unit, 9908 &txlp_port_addr_map_table_entry,END_ADDRf,&end_addr); 9909 start_addr = end_addr+1; 9910 } 9911 BCM_IF_ERROR_RETURN(WRITE_TXLP_PORT_ADDR_MAP_TABLEm( 9912 unit,SOC_INFO(unit).txlp_block[mxqblock-8], 9913 loop, &txlp_port_addr_map_table_entry)); 9914 } 9915 } 9916 return SOC_E_NONE; 9917 } 9918 9919 9920 /* Dynamic Helper function for MMU settings based on 9921 * memory selection (internal/external) 9922 * The memory selection is done using port config property bcmPortControlBufferExternalEnable 9923 */ 9924 int _soc_katana2_mmu_init_helper_dyn(int unit, int port, int ext_mem_enable) 9925 { 9926 uint32 op_node=0; 9927 uint32 port_max_opnodes = 0; 9928 uint8 port_index = 0; 9929 soc_pbmp_t valid_port_cpu_pbmp; 9930 uint8 port_list[]={KT2_CMIC_PORT, KT2_LPBK_PORT , 9931 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 9932 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 9933 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 9934 31, 32, 33, 34, 35, 36, 37, 38, 39, 40}; 9935 soc_port_t port_iter=0; 9936 soc_info_t *si= &SOC_INFO(unit); 9937 uint32 op_node_offset=0; 9938 mmu_thdo_opnconfig_cell_entry_t mmu_thdo_opnconfig_cell_entry={{0}}; 9939 uint32 temp_val; 9940 uint32 queue; 9941 mmu_thdo_qconfig_cell_entry_t mmu_thdo_qconfig_cell_entry={{0}}; 9942 mmu_thdo_qoffset_cell_entry_t mmu_thdo_qoffset_cell_entry={{0}}; 9943 _output_port_threshold_t *output_port_threshold = 9944 &_soc_kt2_mmu_intermediate_results.output_port_threshold; 9945 _general_info_t *general_info = 9946 &_soc_kt2_mmu_intermediate_results.general_info; 9947 #if defined (INCLUDE_L3) 9948 uint32 entry[SOC_MAX_MEM_FIELD_WORDS]; 9949 int ipmc_id; 9950 #endif 9951 uint32 *bmap; 9952 int word, word_count, bit; 9953 9954 SOC_PBMP_CLEAR (valid_port_cpu_pbmp); 9955 SOC_PBMP_ASSIGN(valid_port_cpu_pbmp, PBMP_ALL(unit)); 9956 9957 /* 2.1 Internal Buffer */ 9958 if (!ext_mem_enable) { 9959 if (SOC_PBMP_MEMBER(PBMP_EXT_MEM (unit), port)) { 9960 SOC_PBMP_PORT_REMOVE(PBMP_EXT_MEM (unit), port); 9961 } else { 9962 return SOC_E_NONE; 9963 } 9964 9965 op_node = 0; 9966 port_max_opnodes = 0; 9967 for(port_index = 0, op_node = 0 ; 9968 port_index < COUNTOF(port_list); 9969 port_index++, op_node += port_max_opnodes ) { 9970 9971 port_iter = port_list[port_index]; 9972 port_max_opnodes = ceil_func(si->port_num_uc_cosq[port_iter],8); 9973 9974 if (!SOC_PBMP_MEMBER(valid_port_cpu_pbmp, port_iter)) { 9975 continue; 9976 } 9977 if (port != port_iter) { 9978 continue; 9979 } 9980 9981 if (!SOC_PBMP_MEMBER(PBMP_EXT_MEM (unit), port_iter) && 9982 (port_iter >= KT2_CMIC_PORT) && (port_iter <= KT2_LPBK_PORT)) { 9983 for (op_node_offset = 0; 9984 op_node_offset < port_max_opnodes ; 9985 op_node_offset++) { 9986 SOC_IF_ERROR_RETURN(READ_MMU_THDO_OPNCONFIG_CELLm(unit, 9987 MEM_BLOCK_ANY,op_node + op_node_offset, 9988 &mmu_thdo_opnconfig_cell_entry)); 9989 /* C394:THDO_OPNCONFIG_CELL.OPN_SHARED_LIMIT_CELL = =$C$219 */ 9990 soc_mem_field32_set(unit, MMU_THDO_OPNCONFIG_CELLm, 9991 &mmu_thdo_opnconfig_cell_entry, 9992 OPN_SHARED_LIMIT_CELLf, 9993 output_port_threshold-> 9994 min_grntd_tot_shr_queue_cells_int_buff); 9995 9996 /* C395:THDO_OPNCONFIG_CELL.OP_SHARED_RESET_VALUE_CELL 9997 = C394-2*$C$72 */ 9998 temp_val = output_port_threshold-> 9999 min_grntd_tot_shr_queue_cells_int_buff - 10000 (2 * general_info->ether_mtu_cells_for_int_buff); 10001 soc_mem_field32_set(unit, MMU_THDO_OPNCONFIG_CELLm, 10002 &mmu_thdo_opnconfig_cell_entry, 10003 OPN_SHARED_RESET_VALUE_CELLf, temp_val); 10004 10005 /* C396:THDO_OPNCONFIG_CELL.PORT_LIMIT_ENABLE_CELL 10006 = 0 */ 10007 soc_mem_field32_set(unit, MMU_THDO_OPNCONFIG_CELLm, 10008 &mmu_thdo_opnconfig_cell_entry, 10009 PORT_LIMIT_ENABLE_CELLf, 0); 10010 /* PIDf :Updated by cosq scheduler code while attaching node */ 10011 /* 10012 soc_mem_field32_set(unit, MMU_THDO_OPNCONFIG_CELLm, 10013 &mmu_thdo_opnconfig_cell_entry, 10014 PIDf, port_iter); 10015 */ 10016 SOC_IF_ERROR_RETURN(WRITE_MMU_THDO_OPNCONFIG_CELLm(unit, 10017 MEM_BLOCK_ALL,op_node + op_node_offset, 10018 &mmu_thdo_opnconfig_cell_entry)); 10019 } 10020 10021 bmap = SOC_CONTROL(unit)->port_lls_l2_bmap[port_iter]; 10022 word_count = _SHR_BITDCLSIZE(soc_mem_index_count(unit, LLS_L2_PARENTm)); 10023 for (word = 0; word < word_count; word++) { 10024 if (bmap[word] == 0) { 10025 continue; 10026 } 10027 for (bit = 0; bit < SHR_BITWID; bit++) { 10028 if (!(bmap[word] & (1 << bit))) { 10029 continue; 10030 } 10031 queue = word * SHR_BITWID + bit; 10032 SOC_IF_ERROR_RETURN(READ_MMU_THDO_QCONFIG_CELLm(unit, 10033 MEM_BLOCK_ANY,queue, 10034 &mmu_thdo_qconfig_cell_entry)); 10035 /* C397:THDO_QCONFIG_CELL.Q_MIN_CELL 10036 = =$C$201 */ 10037 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, 10038 &mmu_thdo_qconfig_cell_entry, Q_MIN_CELLf, 10039 output_port_threshold->min_grntd_res_queue_cells_int_buff); 10040 10041 /* C398:THDO_QCONFIG_CELL.Q_SHARED_LIMIT_CELL 10042 =IF($C$14,$C$219,$C$60) */ 10043 if (_soc_kt2_mmu_params.lossless_mode_d_c) { 10044 temp_val = output_port_threshold-> 10045 min_grntd_tot_shr_queue_cells_int_buff; 10046 } else { 10047 temp_val = _soc_kt2_mmu_params.mmu_egr_pg_dyn_thd_param; 10048 } 10049 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, 10050 &mmu_thdo_qconfig_cell_entry, Q_SHARED_LIMIT_CELLf, 10051 temp_val); 10052 10053 /* C400:THDO_QCONFIG_CELL.Q_LIMIT_DYNAMIC_CELL 10054 =IF($C$14, 0, 1) */ 10055 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, 10056 &mmu_thdo_qconfig_cell_entry, Q_LIMIT_DYNAMIC_CELLf, 10057 _soc_kt2_mmu_params.lossless_mode_d_c ? 0 : 1); 10058 10059 /* C401:THDO_QCONFIG_CELL.Q_LIMIT_ENABLE_CELL 10060 =IF($C$14, 0, 1) */ 10061 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, 10062 &mmu_thdo_qconfig_cell_entry, Q_LIMIT_ENABLE_CELLf, 10063 _soc_kt2_mmu_params.lossless_mode_d_c ? 0 : 1); 10064 10065 /* C402:THDO_QCONFIG_CELL.Q_COLOR_ENABLE_CELL = 0 */ 10066 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, 10067 &mmu_thdo_qconfig_cell_entry, Q_COLOR_ENABLE_CELLf,0); 10068 10069 /* C403: THDO_QCONFIG_CELL.Q_COLOR_LIMIT_DYNAMIC_CELL 10070 =IF($C$14, 0, 1) */ 10071 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, 10072 &mmu_thdo_qconfig_cell_entry, Q_COLOR_LIMIT_DYNAMIC_CELLf, 10073 _soc_kt2_mmu_params.lossless_mode_d_c ? 0 : 1); 10074 10075 /* C404: THDO_QCONFIG_CELL.LIMIT_YELLOW_CELL= 10076 if lossless= C398/8 else C398 */ 10077 temp_val = soc_mem_field32_get(unit, MMU_THDO_QCONFIG_CELLm, 10078 &mmu_thdo_qconfig_cell_entry, Q_SHARED_LIMIT_CELLf); 10079 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, 10080 &mmu_thdo_qconfig_cell_entry, LIMIT_YELLOW_CELLf, 10081 _soc_kt2_mmu_params.lossless_mode_d_c ? 10082 ceil_func(temp_val, 8) : temp_val); 10083 SOC_IF_ERROR_RETURN(WRITE_MMU_THDO_QCONFIG_CELLm(unit, 10084 MEM_BLOCK_ALL,queue, 10085 &mmu_thdo_qconfig_cell_entry)); 10086 10087 SOC_IF_ERROR_RETURN(READ_MMU_THDO_QOFFSET_CELLm(unit, 10088 MEM_BLOCK_ANY,queue, 10089 &mmu_thdo_qoffset_cell_entry)); 10090 /* C399:THDO_QOFFSET_CELL.RESET_OFFSET_CELL =2 */ 10091 soc_mem_field32_set(unit, MMU_THDO_QOFFSET_CELLm, 10092 &mmu_thdo_qoffset_cell_entry, RESET_OFFSET_CELLf, 2); 10093 10094 /* C405: THDO_QOFFSET_CELL.LIMIT_RED_CELL = 10095 if lossless= C398/8 else C398 */ 10096 temp_val = soc_mem_field32_get(unit, MMU_THDO_QCONFIG_CELLm, 10097 &mmu_thdo_qconfig_cell_entry, Q_SHARED_LIMIT_CELLf); 10098 soc_mem_field32_set(unit, MMU_THDO_QOFFSET_CELLm, 10099 &mmu_thdo_qoffset_cell_entry, LIMIT_RED_CELLf, 10100 _soc_kt2_mmu_params.lossless_mode_d_c ? 10101 ceil_func(temp_val, 8) : temp_val); 10102 10103 /* C406: THDO_QOFFSET_CELL.RESET_OFFSET_YELLOW_CELL =2 */ 10104 soc_mem_field32_set(unit, MMU_THDO_QOFFSET_CELLm, 10105 &mmu_thdo_qoffset_cell_entry, RESET_OFFSET_YELLOW_CELLf,2); 10106 /* C407: THDO_QOFFSET_CELL.RESET_OFFSET_RED_CELL =2 */ 10107 soc_mem_field32_set(unit, MMU_THDO_QOFFSET_CELLm, 10108 &mmu_thdo_qoffset_cell_entry, RESET_OFFSET_RED_CELLf,2); 10109 10110 SOC_IF_ERROR_RETURN(WRITE_MMU_THDO_QOFFSET_CELLm(unit, 10111 MEM_BLOCK_ALL,queue, 10112 &mmu_thdo_qoffset_cell_entry)); 10113 } 10114 } 10115 } 10116 } 10117 if (_soc_kt2_mmu_params.packing_mode_d_c) { 10118 SOC_IF_ERROR_RETURN(_soc_kt2_packing_port_config_set(unit, port, 0)); 10119 } 10120 SOC_IF_ERROR_RETURN(_soc_katana2_mmu_init_ext_mem_dyn_port(unit, port)); 10121 } else { 10122 /* 2.2 External Buffer */ 10123 if (SOC_PBMP_MEMBER(PBMP_EXT_MEM (unit), port)) { 10124 return SOC_E_NONE; 10125 } 10126 SOC_PBMP_PORT_ADD(PBMP_EXT_MEM (unit), port); 10127 for(port_index = 0, op_node = 0 ; 10128 port_index < COUNTOF(port_list); 10129 port_index++, op_node += port_max_opnodes ) { 10130 10131 port_iter = port_list[port_index]; 10132 port_max_opnodes = ceil_func(si->port_num_uc_cosq[port_iter],8); 10133 10134 if (!SOC_PBMP_MEMBER(valid_port_cpu_pbmp, port_iter)) { 10135 continue; 10136 } 10137 if (port != port_iter) { 10138 continue; 10139 } 10140 10141 if (!IS_CPU_PORT(unit, port_iter) && 10142 (port_iter > KT2_CMIC_PORT) && (port_iter <= KT2_LPBK_PORT) && 10143 SOC_PBMP_MEMBER(PBMP_EXT_MEM (unit), port_iter)) { 10144 10145 SOC_IF_ERROR_RETURN(READ_MMU_THDO_OPNCONFIG_CELLm(unit, 10146 MEM_BLOCK_ANY,op_node , &mmu_thdo_opnconfig_cell_entry)); 10147 /* C409:THDO_OPNCONFIG_CELL.OPN_SHARED_LIMIT_CELL = =$C$220 */ 10148 soc_mem_field32_set(unit, MMU_THDO_OPNCONFIG_CELLm, 10149 &mmu_thdo_opnconfig_cell_entry, 10150 OPN_SHARED_LIMIT_CELLf, 10151 output_port_threshold-> 10152 min_grntd_tot_shr_queue_cells_ext_buff); 10153 10154 /* C410:THDO_OPNCONFIG_CELL.OP_SHARED_RESET_VALUE_CELL 10155 = =$C$409-2*$C$73 */ 10156 temp_val = output_port_threshold-> 10157 min_grntd_tot_shr_queue_cells_ext_buff - 10158 (2 * general_info->ether_mtu_cells_for_ext_buff); 10159 soc_mem_field32_set(unit, MMU_THDO_OPNCONFIG_CELLm, 10160 &mmu_thdo_opnconfig_cell_entry, 10161 OPN_SHARED_RESET_VALUE_CELLf, temp_val); 10162 10163 /* C411:THDO_OPNCONFIG_CELL.PORT_LIMIT_ENABLE_CELL = 0 */ 10164 soc_mem_field32_set(unit, MMU_THDO_OPNCONFIG_CELLm, 10165 &mmu_thdo_opnconfig_cell_entry, 10166 PORT_LIMIT_ENABLE_CELLf, 0); 10167 /* PIDf :Updated by cosq scheduler code while attaching node */ 10168 /* 10169 soc_mem_field32_set(unit, MMU_THDO_OPNCONFIG_CELLm, 10170 &mmu_thdo_opnconfig_cell_entry, 10171 PIDf, port_iter); 10172 */ 10173 SOC_IF_ERROR_RETURN(WRITE_MMU_THDO_OPNCONFIG_CELLm(unit, 10174 MEM_BLOCK_ALL,op_node, 10175 &mmu_thdo_opnconfig_cell_entry)); 10176 10177 bmap = SOC_CONTROL(unit)->port_lls_l2_bmap[port_iter]; 10178 word_count = _SHR_BITDCLSIZE(soc_mem_index_count(unit, LLS_L2_PARENTm)); 10179 for (word = 0; word < word_count; word++) { 10180 if (bmap[word] == 0) { 10181 continue; 10182 } 10183 for (bit = 0; bit < SHR_BITWID; bit++) { 10184 if (!(bmap[word] & (1 << bit))) { 10185 continue; 10186 } 10187 queue = word * SHR_BITWID + bit; 10188 SOC_IF_ERROR_RETURN(READ_MMU_THDO_QCONFIG_CELLm(unit, 10189 MEM_BLOCK_ANY,queue, 10190 &mmu_thdo_qconfig_cell_entry)); 10191 /* C412:THDO_QCONFIG_CELL.Q_MIN_CELL 10192 = =$C$202 */ 10193 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, 10194 &mmu_thdo_qconfig_cell_entry, Q_MIN_CELLf, 10195 output_port_threshold->min_grntd_res_queue_cells_ext_buff); 10196 10197 /* C413:THDO_QCONFIG_CELL.Q_SHARED_LIMIT_CELL 10198 =IF($C$14,$C$220,$C$60) */ 10199 if (_soc_kt2_mmu_params.lossless_mode_d_c) { 10200 temp_val = output_port_threshold-> 10201 min_grntd_tot_shr_queue_cells_ext_buff; 10202 } else { 10203 temp_val = _soc_kt2_mmu_params.mmu_egr_pg_dyn_thd_param; 10204 } 10205 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, 10206 &mmu_thdo_qconfig_cell_entry, Q_SHARED_LIMIT_CELLf, 10207 temp_val); 10208 10209 /* C415:THDO_QCONFIG_CELL.Q_LIMIT_DYNAMIC_CELL 10210 =IF($C$14, 0, 1) */ 10211 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, 10212 &mmu_thdo_qconfig_cell_entry, Q_LIMIT_DYNAMIC_CELLf, 10213 _soc_kt2_mmu_params.lossless_mode_d_c ? 0 : 1); 10214 10215 /* C416:THDO_QCONFIG_CELL.Q_LIMIT_ENABLE_CELL 10216 =IF($C$14, 0, 1) */ 10217 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, 10218 &mmu_thdo_qconfig_cell_entry, Q_LIMIT_ENABLE_CELLf, 10219 _soc_kt2_mmu_params.lossless_mode_d_c ? 0 : 1); 10220 10221 /* C417:THDO_QCONFIG_CELL.Q_COLOR_ENABLE_CELL = 0 */ 10222 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, 10223 &mmu_thdo_qconfig_cell_entry, Q_COLOR_ENABLE_CELLf,0); 10224 10225 /* C418: THDO_QCONFIG_CELL.Q_COLOR_LIMIT_DYNAMIC_CELL 10226 =IF($C$14, 0, 1) */ 10227 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, 10228 &mmu_thdo_qconfig_cell_entry, Q_COLOR_LIMIT_DYNAMIC_CELLf, 10229 _soc_kt2_mmu_params.lossless_mode_d_c ? 0 : 1); 10230 10231 /* C419: THDO_QCONFIG_CELL.LIMIT_YELLOW_CELL= 10232 if lossless= CEILING(C413/8) else C413 */ 10233 temp_val = soc_mem_field32_get(unit, MMU_THDO_QCONFIG_CELLm, 10234 &mmu_thdo_qconfig_cell_entry, Q_SHARED_LIMIT_CELLf); 10235 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, 10236 &mmu_thdo_qconfig_cell_entry, LIMIT_YELLOW_CELLf, 10237 _soc_kt2_mmu_params.lossless_mode_d_c ? 10238 ceil_func(temp_val, 8) : temp_val); 10239 SOC_IF_ERROR_RETURN(WRITE_MMU_THDO_QCONFIG_CELLm(unit, 10240 MEM_BLOCK_ALL,queue, 10241 &mmu_thdo_qconfig_cell_entry)); 10242 10243 SOC_IF_ERROR_RETURN(READ_MMU_THDO_QOFFSET_CELLm(unit, 10244 MEM_BLOCK_ANY,queue, 10245 &mmu_thdo_qoffset_cell_entry)); 10246 /* C414:THDO_QOFFSET_CELL.RESET_OFFSET_CELL =2 */ 10247 soc_mem_field32_set(unit, MMU_THDO_QOFFSET_CELLm, 10248 &mmu_thdo_qoffset_cell_entry, RESET_OFFSET_CELLf, 2); 10249 10250 /* C420: THDO_QOFFSET_CELL.LIMIT_RED_CELL = 10251 if lossless= CEILING(C413/8) else C413 */ 10252 temp_val = soc_mem_field32_get(unit, MMU_THDO_QCONFIG_CELLm, 10253 &mmu_thdo_qconfig_cell_entry, Q_SHARED_LIMIT_CELLf); 10254 soc_mem_field32_set(unit, MMU_THDO_QOFFSET_CELLm, 10255 &mmu_thdo_qoffset_cell_entry, LIMIT_RED_CELLf, 10256 _soc_kt2_mmu_params.lossless_mode_d_c ? 10257 ceil_func(temp_val, 8) : temp_val); 10258 10259 /* C421: THDO_QOFFSET_CELL.RESET_OFFSET_YELLOW_CELL =2 */ 10260 soc_mem_field32_set(unit, MMU_THDO_QOFFSET_CELLm, 10261 &mmu_thdo_qoffset_cell_entry, RESET_OFFSET_YELLOW_CELLf,2); 10262 /* C422: THDO_QOFFSET_CELL.RESET_OFFSET_RED_CELL =2 */ 10263 soc_mem_field32_set(unit, MMU_THDO_QOFFSET_CELLm, 10264 &mmu_thdo_qoffset_cell_entry, RESET_OFFSET_RED_CELLf,2); 10265 10266 SOC_IF_ERROR_RETURN(WRITE_MMU_THDO_QOFFSET_CELLm(unit, 10267 MEM_BLOCK_ALL,queue, 10268 &mmu_thdo_qoffset_cell_entry)); 10269 } 10270 } 10271 } 10272 } 10273 if (_soc_kt2_mmu_params.packing_mode_d_c) { 10274 SOC_IF_ERROR_RETURN(_soc_kt2_packing_port_config_set(unit, port, 1)); 10275 } 10276 SOC_IF_ERROR_RETURN(_soc_katana2_mmu_init_ext_mem_dyn_port(unit, port)); 10277 } 10278 10279 10280 #if defined (INCLUDE_L3) 10281 /* IPMC configuration */ 10282 soc_mem_lock(unit, L3_IPMCm); 10283 for (ipmc_id = soc_mem_index_min(unit, L3_IPMCm); 10284 ipmc_id <= soc_mem_index_max(unit, L3_IPMCm); 10285 ipmc_id++) { 10286 if (_bcm_kt_ipmc_port_ext_queue_count(unit, ipmc_id, port)) { 10287 BCM_IF_ERROR_RETURN(soc_mem_read(unit, L3_IPMCm, MEM_BLOCK_ANY, 10288 ipmc_id, entry)); 10289 soc_mem_field32_set(unit, L3_IPMCm, entry, EXT_Q_INTERNALf, 0); 10290 soc_mem_field32_set(unit, L3_IPMCm, entry, EXT_Q_EXTERNALf, 0); 10291 if (!ext_mem_enable) { 10292 SOC_PBMP_ITER (PBMP_EXT_MEM (unit), port_iter) { 10293 if (_bcm_kt_ipmc_port_ext_queue_count(unit, ipmc_id, port_iter)) { 10294 soc_mem_field32_set(unit, L3_IPMCm, entry, EXT_Q_EXTERNALf, 1); 10295 } 10296 } 10297 soc_mem_field32_set(unit, L3_IPMCm, entry, EXT_Q_INTERNALf, 1); 10298 } else { 10299 PBMP_ITER(PBMP_PORT_ALL(unit), port_iter){ 10300 if (!SOC_PBMP_MEMBER(PBMP_EXT_MEM (unit), port_iter) && 10301 _bcm_kt_ipmc_port_ext_queue_count(unit, ipmc_id, port_iter)) 10302 soc_mem_field32_set(unit, L3_IPMCm, entry, EXT_Q_INTERNALf, 1); 10303 } 10304 soc_mem_field32_set(unit, L3_IPMCm, entry, EXT_Q_EXTERNALf, 1); 10305 } 10306 BCM_IF_ERROR_RETURN(soc_mem_write(unit, L3_IPMCm, 10307 MEM_BLOCK_ALL, ipmc_id, &entry)); 10308 BCM_IF_ERROR_RETURN(_bcm_kt2_ipmc_subscriber_egress_queue_ext_set 10309 (unit, port, ipmc_id, ext_mem_enable)); 10310 } 10311 } 10312 soc_mem_unlock(unit, L3_IPMCm); 10313 #endif 10314 return BCM_E_NONE; 10315 } 10316 10317 /* Helper function for MMU settings based on 10318 * memory selection (internal/external/both) and mode (lossless/lossy) 10319 * The memory selection is done using config variable 'pbmp_ext_mem' 10320 * and the mode is selected based on config variable 'lossless_mode' 10321 */ 10322 STATIC 10323 int _soc_katana2_mmu_init_helper(int unit, soc_port_t flex_port) 10324 { 10325 soc_info_t *si= &SOC_INFO(unit); 10326 int idx; 10327 uint16 dev_id=0; 10328 uint8 rev_id=0; 10329 uint32 ext_mem_port_count = 0; 10330 uint32 valid_port_count = 0; 10331 soc_pbmp_t pbmp_int_ge; 10332 uint32 pbmp_int_ge_count=0; 10333 soc_pbmp_t pbmp_int_hg; 10334 uint32 pbmp_int_hg_count=0; 10335 soc_pbmp_t pbmp_ext_ge; 10336 uint32 pbmp_ext_ge_count=0; 10337 soc_pbmp_t pbmp_ext_hg; 10338 uint32 pbmp_ext_hg_count=0; 10339 uint32 mmu_num_olp_port=0; 10340 soc_pbmp_t valid_port_cpu_pbmp; 10341 soc_port_t sub_port=0; 10342 soc_port_t port=0; 10343 uint32 available_internal_buffer=100; 10344 uint32 reserve_internal_buffer=0; 10345 uint32 temp_val; 10346 uint32 rval=0; 10347 uint32 service_pool=0; 10348 uint32 priority_group=0; 10349 uint32 op_buffer_shared_limit_celli; 10350 uint32 op_buffer_shared_limit_resume_celli; 10351 uint32 op_buffer_shared_limit_celle; 10352 uint32 op_buffer_shared_limit_resume_celle; 10353 uint32 op_buffer_shared_limit; 10354 uint32 op_buffer_shared_limit_resume; 10355 soc_field_info_t *fieldp; 10356 uint32 queue; 10357 uint32 op_node=0; 10358 uint32 op_node_offset=0; 10359 uint32 cos; 10360 uint64 r64val; 10361 uint64 val64; 10362 int adjust_min_grntd; 10363 _soc_mmu_cfg_buf_t *buf; 10364 _soc_mmu_device_info_t devcfg; 10365 _soc_mmu_cfg_buf_port_t *buf_port; 10366 _soc_mmu_cfg_buf_queue_t *buf_queue; 10367 _soc_mmu_cfg_buf_mcengine_queue_t *buf_rqe_queue; 10368 10369 /* soc_reg_info_t *regp; */ 10370 10371 /* Per Port Settings */ 10372 uint32 mem_idx=0; 10373 thdi_port_sp_config_entry_t thdi_port_sp_config={{0}}; 10374 /* 10375 (KT2_MAX_PHYSICAL_PORTS+2) * 10376 KT2_MAX_SERVICE_POOLS] = {{{0}}}; 10377 */ 10378 thdi_port_pg_config_entry_t thdi_port_pg_config={{0}}; 10379 /* 10380 (KT2_MAX_PHYSICAL_PORTS+2) * 10381 KT2_MAX_PRIORITY_GROUPS] = {{{0}}}; 10382 */ 10383 10384 thdiext_thdi_port_sp_config_entry_t thdiext_thdi_port_sp_config={{0}}; 10385 /* 10386 (KT2_MAX_PHYSICAL_PORTS+2) * 10387 KT2_MAX_SERVICE_POOLS] = {{{0}}}; 10388 */ 10389 thdiext_thdi_port_pg_config_entry_t thdiext_thdi_port_pg_config={{0}}; 10390 /* 10391 (KT2_MAX_PHYSICAL_PORTS+2) * 10392 KT2_MAX_PRIORITY_GROUPS] = {{{0}}}; 10393 */ 10394 thdiema_thdi_port_sp_config_entry_t thdiema_thdi_port_sp_config = {{0}}; 10395 /* 10396 (KT2_MAX_PHYSICAL_PORTS+2) * 10397 KT2_MAX_SERVICE_POOLS] = {{{0}}}; 10398 */ 10399 thdiema_thdi_port_pg_config_entry_t thdiema_thdi_port_pg_config={{0}}; 10400 /* 10401 (KT2_MAX_PHYSICAL_PORTS+2) * 10402 KT2_MAX_PRIORITY_GROUPS] = {{{0}}}; 10403 */ 10404 thdirqe_thdi_port_sp_config_entry_t thdirqe_thdi_port_sp_config={{0}}; 10405 /* 10406 (KT2_MAX_PHYSICAL_PORTS+2) * 10407 KT2_MAX_SERVICE_POOLS] = {{{0}}}; 10408 */ 10409 thdirqe_thdi_port_pg_config_entry_t thdirqe_thdi_port_pg_config={{0}}; 10410 /* 10411 (KT2_MAX_PHYSICAL_PORTS+2) * 10412 KT2_MAX_PRIORITY_GROUPS] = {{{0}}}; 10413 */ 10414 thdiqen_thdi_port_sp_config_entry_t thdiqen_thdi_port_sp_config = {{0}}; 10415 /* 10416 (KT2_MAX_PHYSICAL_PORTS+2) * 10417 KT2_MAX_SERVICE_POOLS] = {{{0}}}; 10418 */ 10419 thdiqen_thdi_port_pg_config_entry_t thdiqen_thdi_port_pg_config = {{0}}; 10420 /* 10421 (KT2_MAX_PHYSICAL_PORTS+2) * 10422 KT2_MAX_PRIORITY_GROUPS] = {{{0}}}; 10423 */ 10424 10425 mmu_thdo_opnconfig_cell_entry_t mmu_thdo_opnconfig_cell_entry={{0}}; 10426 mmu_thdo_qconfig_cell_entry_t mmu_thdo_qconfig_cell_entry={{0}}; 10427 mmu_thdo_qoffset_cell_entry_t mmu_thdo_qoffset_cell_entry={{0}}; 10428 10429 mmu_thdo_opnconfig_qentry_entry_t mmu_thdo_opnconfig_qentry_entry={{0}}; 10430 mmu_thdo_qconfig_qentry_entry_t mmu_thdo_qconfig_qentry_entry={{0}}; 10431 mmu_thdo_qoffset_qentry_entry_t mmu_thdo_qoffset_qentry_entry={{0}}; 10432 10433 _general_info_t *general_info = 10434 &_soc_kt2_mmu_intermediate_results.general_info; 10435 _input_port_threshold_t *input_port_threshold = 10436 &_soc_kt2_mmu_intermediate_results.input_port_threshold; 10437 _output_port_threshold_t *output_port_threshold = 10438 &_soc_kt2_mmu_intermediate_results.output_port_threshold; 10439 10440 uint8 port_list[]={KT2_CMIC_PORT, KT2_LPBK_PORT , 10441 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 10442 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 10443 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 10444 31, 32, 33, 34, 35, 36, 37, 38, 39, 40}; 10445 uint32 port_max_opnodes = 0; 10446 uint8 port_index = 0; 10447 int mmu_config_enabled = 0; 10448 10449 buf = soc_mmu_cfg_alloc(unit); 10450 if (!buf) { 10451 return SOC_E_MEMORY; 10452 } 10453 sal_memset(&devcfg, 0, sizeof(_soc_mmu_device_info_t)); 10454 10455 if (soc_property_get(unit, spn_MMU_CONFIG_OVERRIDE, 1) == 0) { 10456 _soc_mmu_cfg_buf_read(unit, buf, &devcfg); 10457 mmu_config_enabled = 1; 10458 } else { 10459 mmu_config_enabled = 0; 10460 } 10461 10462 sal_memset(&_soc_kt2_mmu_intermediate_results,0,sizeof(_soc_kt2_mmu_intermediate_results_t)); 10463 sal_memset(&_soc_kt2_mmu_params,0,sizeof(_soc_kt2_mmu_params_t)); 10464 10465 /* Fixed Parameter */ 10466 _soc_kt2_mmu_params.mmu_min_pkt_size = 64; /*C5*/ 10467 _soc_kt2_mmu_params.mmu_ethernet_mtu_bytes=1536; /*C6*/ 10468 _soc_kt2_mmu_params.mmu_max_pkt_size = 9216; /*C7*/ 10469 _soc_kt2_mmu_params.mmu_jumbo_frame_size = 9216; /*C8*/ 10470 _soc_kt2_mmu_params.mmu_int_buf_cell_size = 190; /*C9*/ 10471 /* C10 = (C9+2)*15 */ 10472 _soc_kt2_mmu_params.mmu_pkt_header_size = 62; /*C11*/ 10473 _soc_kt2_mmu_params.mmu_lossless_pg_num = 1; /*C16*/ 10474 _soc_kt2_mmu_params.mmu_line_rate_ge = 1; /*C20*/ 10475 _soc_kt2_mmu_params.mmu_line_rate_hg = 13; /*C26*/ 10476 _soc_kt2_mmu_params.mmu_num_cpu_port = 1; /*C31*/ 10477 _soc_kt2_mmu_params.mmu_num_cpu_queue = 48; /*C32*/ 10478 _soc_kt2_mmu_params.mmu_num_loopback_port = 1; /*C34*/ 10479 _soc_kt2_mmu_params.mmu_num_loopback_queue = 8; /*C35*/ 10480 _soc_kt2_mmu_params.mmu_num_ep_redirection_queue = 16; /*C36*/ 10481 _soc_kt2_mmu_params.mmu_num_olp_queue = 8; /*C38*/ 10482 _soc_kt2_mmu_params.mmu_int_buf_size = 2; /*C41:2048KB=2MB*/ 10483 _soc_kt2_mmu_params.mmu_reserved_int_buf_cells = 100; /*C43:100 Cells */ 10484 _soc_kt2_mmu_params.mmu_ext_buf_size = 10485 SOC_DDR3_NUM_MEMORIES(unit) * 10486 SOC_DDR3_NUM_ROWS(unit) * 10487 SOC_DDR3_NUM_COLUMNS(unit) * 10488 SOC_DDR3_NUM_BANKS(unit) / 10489 (1024 * 1024); 10490 if (_soc_kt2_mmu_params.mmu_ext_buf_size > 720) { 10491 /* Maximum external buffer size is 720MB. 10492 * 256K pointers * 2880 byte cells = 720MB */ 10493 _soc_kt2_mmu_params.mmu_ext_buf_size = 720; 10494 } 10495 if (_soc_kt2_mmu_params.mmu_ext_buf_size <= 192) { 10496 /* For small packet buffer configurations, use smaller cell size 10497 * to reduce cell quantization loss */ 10498 _soc_kt2_mmu_params.mmu_ext_buf_cell_size = 768; 10499 } else { 10500 _soc_kt2_mmu_params.mmu_ext_buf_cell_size = 2880; 10501 } 10502 _soc_kt2_mmu_params.mmu_ep_redirect_queue_entries = 1000;/*C48*/ 10503 _soc_kt2_mmu_params.mmu_exp_num_of_repl_per_pkt = 27; /*C49*/ 10504 _soc_kt2_mmu_params.mmu_repl_engine_work_queue_entries = 8; /*C50*/ 10505 _soc_kt2_mmu_params.mmu_repl_engine_work_queue_in_device = 12; /*C51*/ 10506 _soc_kt2_mmu_params.mmu_ema_queues = 8; /*C52*/ 10507 /* 10508 static const float kt2_baf_profile_indexes[]={0.015625,0.03125,0.0625, 10509 0.125,0.25,0.5,1.0,2.0,4.0,8.0}; 10510 */ 10511 _soc_kt2_mmu_params.mmu_ing_port_dyn_thd_param = 2; /*C57*/ 10512 _soc_kt2_mmu_params.mmu_ing_pg_dyn_thd_param = 7; /*C58*/ 10513 _soc_kt2_mmu_params.mmu_egr_queue_dyn_thd_param = 2; /*C59*/ 10514 _soc_kt2_mmu_params.mmu_egr_pg_dyn_thd_param = 7; /*C60*/ 10515 _soc_kt2_mmu_params.mmu_ing_cell_buf_reduction = 0; /*C61 */ 10516 _soc_kt2_mmu_params.mmu_ing_pkt_buf_reduction = 0; /*C62 */ 10517 10518 SOC_PBMP_CLEAR (pbmp_int_ge); 10519 SOC_PBMP_CLEAR (pbmp_int_hg); 10520 SOC_PBMP_CLEAR (pbmp_ext_ge); 10521 SOC_PBMP_CLEAR (pbmp_ext_hg); 10522 10523 SOC_PBMP_CLEAR (valid_port_cpu_pbmp); 10524 SOC_PBMP_ASSIGN(valid_port_cpu_pbmp, PBMP_ALL(unit)); 10525 /* SOC_PBMP_PORT_ADD(valid_port_cpu_pbmp, KT2_CMIC_PORT); */ 10526 10527 soc_cm_get_id(unit, &dev_id, &rev_id); 10528 /* C12 */ 10529 if (soc_feature(unit, soc_feature_mmu_packing)) { 10530 _soc_kt2_mmu_params.packing_mode_d_c = 1; 10531 /* soc_property_get(unit, spn_MMU_MULTI_PACKETS_PER_CELL, 0); */ 10532 } 10533 10534 /* C13 */ 10535 if (_soc_kt2_mmu_params.packing_mode_d_c) { 10536 LOG_VERBOSE(BSL_LS_SOC_COMMON, 10537 (BSL_META_U(unit, 10538 "Packing mode enabled \n"))); 10539 _soc_kt2_mmu_params.max_pkt_size_support_packing = 10; 10540 } else { 10541 LOG_VERBOSE(BSL_LS_SOC_COMMON, 10542 (BSL_META_U(unit, 10543 "Packing mode disabled \n"))); 10544 } 10545 10546 /* C14 */ 10547 _soc_kt2_mmu_params.lossless_mode_d_c = (soc_property_get(unit, 10548 spn_LOSSLESS_MODE, 1) & 10549 soc_property_get(unit, 10550 spn_MMU_LOSSLESS, 1)); 10551 /* C15 */ 10552 _soc_kt2_mmu_params.pfc_pause_mode_d_c = soc_property_get(unit, 10553 "pfc_pause_mode", 0); 10554 10555 SOC_PBMP_COUNT(PBMP_PORT_ALL (unit), valid_port_count); 10556 SOC_PBMP_COUNT(PBMP_EXT_MEM (unit), ext_mem_port_count);/*spn_PBMP_EXT_MEM*/ 10557 10558 if (!ext_mem_port_count) { 10559 if (SOC_DDR3_NUM_MEMORIES(unit)) { 10560 ext_mem_port_count = 1; 10561 } 10562 } 10563 10564 /* C17 */ 10565 if (ext_mem_port_count == 0) { 10566 _soc_kt2_mmu_params.extbuf_used_d_c = 0; 10567 } else { 10568 _soc_kt2_mmu_params.extbuf_used_d_c = 1; 10569 } 10570 10571 SOC_PBMP_ASSIGN(pbmp_int_ge,PBMP_GE_ALL(unit)); 10572 if (SOC_INFO(unit).olp_port[0]) { 10573 SOC_PBMP_PORT_REMOVE(pbmp_int_ge,KT2_OLP_PORT); 10574 mmu_num_olp_port=1; 10575 } 10576 SOC_PBMP_ASSIGN(pbmp_int_hg,PBMP_HG_ALL(unit)); 10577 SOC_PBMP_OR(pbmp_int_hg,PBMP_XE_ALL(unit)); 10578 SOC_PBMP_ITER (PBMP_EXT_MEM (unit), port) { 10579 if (IS_GE_PORT(unit, port)) { 10580 SOC_PBMP_PORT_ADD(pbmp_ext_ge,port); 10581 SOC_PBMP_PORT_REMOVE(pbmp_int_ge,port); 10582 } 10583 if (IS_HG_PORT(unit, port) || IS_XE_PORT(unit, port)) { 10584 SOC_PBMP_PORT_ADD(pbmp_ext_hg,port); 10585 SOC_PBMP_PORT_REMOVE(pbmp_int_hg,port); 10586 } 10587 } 10588 SOC_PBMP_COUNT(pbmp_ext_ge,pbmp_ext_ge_count); 10589 SOC_PBMP_COUNT(pbmp_int_ge,pbmp_int_ge_count); 10590 SOC_PBMP_COUNT(pbmp_ext_hg,pbmp_ext_hg_count); 10591 SOC_PBMP_COUNT(pbmp_int_hg,pbmp_int_hg_count); 10592 10593 /* C19 */ 10594 _soc_kt2_mmu_params.num_ge_ports_d = pbmp_int_ge_count + pbmp_ext_ge_count; 10595 /* C21 */ 10596 _soc_kt2_mmu_params.num_ge_int_ports_d = pbmp_int_ge_count; 10597 /* C22 */ 10598 _soc_kt2_mmu_params.num_egr_queue_per_int_ge_port_d = pbmp_int_ge_count ? 8:0; 10599 /* C23 */ 10600 _soc_kt2_mmu_params.num_ge_ext_ports_d = pbmp_ext_ge_count; 10601 /* C24 */ 10602 _soc_kt2_mmu_params.num_egr_queue_per_ext_ge_port_d = pbmp_ext_ge_count ? 10603 (_soc_kt2_mmu_params.packing_mode_d_c ? 16:8):0; 10604 /* C25 */ 10605 _soc_kt2_mmu_params.num_hg_ports_d = pbmp_int_hg_count + pbmp_ext_hg_count; 10606 /* C27 */ 10607 _soc_kt2_mmu_params.num_hg_int_ports_d = pbmp_int_hg_count ; 10608 /* C28 */ 10609 _soc_kt2_mmu_params.num_egr_queue_per_int_hg_port_d = pbmp_int_hg_count ? 8:0; 10610 /* C29 */ 10611 _soc_kt2_mmu_params.num_hg_ext_ports_d = pbmp_ext_hg_count ; 10612 /* C30 */ 10613 _soc_kt2_mmu_params.num_egr_queue_per_ext_hg_port_d = pbmp_ext_hg_count ? 10614 (_soc_kt2_mmu_params.packing_mode_d_c ? 16:8):0; 10615 /* C33 */ 10616 _soc_kt2_mmu_params.cpu_port_int_ext_bounding_d_c = soc_property_get(unit, 10617 "cpu_port_bounding",0); 10618 /* C37 */ 10619 _soc_kt2_mmu_params.mmu_num_olp_port_d = mmu_num_olp_port; 10620 /* C39 */ 10621 _soc_kt2_mmu_params.olp_port_int_ext_bounding_d_c = soc_property_get(unit, 10622 "olp_port_bounding",0); 10623 10624 if ((ext_mem_port_count) || (_soc_kt2_mmu_params.packing_mode_d_c)) { 10625 available_internal_buffer=70; 10626 reserve_internal_buffer=30; 10627 } else { 10628 available_internal_buffer=100; 10629 reserve_internal_buffer=0; 10630 } 10631 /* C42 */ 10632 _soc_kt2_mmu_params.mmu_available_int_buf_size_d=available_internal_buffer; 10633 /* (_soc_kt2_mmu_params.mmu_int_buf_size*available_internal_buffer)/100; */ 10634 /* C44 */ 10635 _soc_kt2_mmu_params.mmu_reserved_int_buf_ema_pool_size_d= 10636 reserve_internal_buffer; 10637 /* (_soc_kt2_mmu_params.mmu_int_buf_size*reserve_internal_buffer)/100; */ 10638 10639 /* C45 */ 10640 _soc_kt2_mmu_params.internal_buffer_reduction_d_c = soc_property_get(unit, 10641 "internal_buffer_reduction",0); 10642 10643 /* C46 */ /* Reduce for KT packing mode only..*/ 10644 if ((dev_id == BCM56454_DEVICE_ID) || (dev_id == BCM56455_DEVICE_ID)) { 10645 if (_soc_kt2_mmu_params.packing_mode_d_c) { 10646 _soc_kt2_mmu_params.mmu_ext_buf_size = 360; 10647 } 10648 } 10649 10650 /* C47 */ 10651 _soc_kt2_mmu_params.mmu_egress_queue_entries = 10652 _soc_kt2_mmu_params.packing_mode_d_c ? 128:256; 10653 10654 /* C55 = CEILING((C6*1024+C11)/C9, 1) */ 10655 _soc_kt2_mmu_params.per_cos_res_cells_for_int_buff_d = 10656 ceil_func((_soc_kt2_mmu_params.mmu_ethernet_mtu_bytes + 10657 _soc_kt2_mmu_params.mmu_pkt_header_size), 10658 _soc_kt2_mmu_params.mmu_int_buf_cell_size); 10659 10660 /* C56 = =IF(C12=0,CEILING(C53/15,1),CEILING((C6*1024+C11+2)/C10,1)) */ 10661 if (_soc_kt2_mmu_params.packing_mode_d_c == 0) { 10662 _soc_kt2_mmu_params.per_cos_res_cells_for_ext_buff_d = 10663 ceil_func(_soc_kt2_mmu_params.per_cos_res_cells_for_int_buff_d,15); 10664 } else { 10665 _soc_kt2_mmu_params.per_cos_res_cells_for_ext_buff_d = 10666 ceil_func((_soc_kt2_mmu_params.mmu_ethernet_mtu_bytes + 10667 _soc_kt2_mmu_params.mmu_pkt_header_size + 2), 10668 _soc_kt2_mmu_params.mmu_ext_buf_cell_size); 10669 } 10670 10671 /* Intermediate Results Processing Now */ 10672 /* Fill up general info */ 10673 /* C68 = CEILING((C7+C11)/C9,1) */ 10674 general_info->max_packet_size_in_cells = ceil_func( 10675 (_soc_kt2_mmu_params.mmu_max_pkt_size + 10676 _soc_kt2_mmu_params.mmu_pkt_header_size), 10677 _soc_kt2_mmu_params.mmu_int_buf_cell_size); 10678 /* C69 = CEILING((C8+C11)/C9,1) */ 10679 general_info->jumbo_frame_for_int_buff = ceil_func( 10680 (_soc_kt2_mmu_params.mmu_jumbo_frame_size + 10681 _soc_kt2_mmu_params.mmu_pkt_header_size), 10682 _soc_kt2_mmu_params.mmu_int_buf_cell_size); 10683 /* C70 = IF(C12=0,CEILING(C69/15,1),CEILING((C8+C11+2)/C10,1)) */ 10684 if (_soc_kt2_mmu_params.packing_mode_d_c == 0) { 10685 general_info->jumbo_frame_for_ext_buff = ceil_func( 10686 general_info->jumbo_frame_for_int_buff,15); 10687 } else { 10688 general_info->jumbo_frame_for_ext_buff = ceil_func( 10689 _soc_kt2_mmu_params.mmu_jumbo_frame_size + 10690 _soc_kt2_mmu_params.mmu_pkt_header_size + 2, 10691 _soc_kt2_mmu_params.mmu_ext_buf_cell_size); 10692 } 10693 /* C72 = CEILING((C6*1024+C11)/C9, 1) */ 10694 general_info->ether_mtu_cells_for_int_buff = ceil_func( 10695 (_soc_kt2_mmu_params.mmu_ethernet_mtu_bytes) + 10696 _soc_kt2_mmu_params.mmu_pkt_header_size, 10697 _soc_kt2_mmu_params.mmu_int_buf_cell_size); 10698 10699 /* C73 = IF(C12=0,CEILING(C72/15,1),CEILING((C6*1024+C11+2)/C10,1)) */ 10700 if (_soc_kt2_mmu_params.packing_mode_d_c == 0) { 10701 general_info->ether_mtu_cells_for_ext_buff = ceil_func( 10702 general_info->ether_mtu_cells_for_int_buff,15); 10703 } else { 10704 general_info->ether_mtu_cells_for_ext_buff = ceil_func( 10705 (_soc_kt2_mmu_params.mmu_ethernet_mtu_bytes)+ 10706 _soc_kt2_mmu_params.mmu_pkt_header_size+2, 10707 _soc_kt2_mmu_params.mmu_ext_buf_cell_size); 10708 } 10709 10710 /* C75 = C19+C25+C31+C34+C37 */ 10711 general_info->total_num_of_ports = 10712 _soc_kt2_mmu_params.num_ge_ports_d + 10713 _soc_kt2_mmu_params.num_hg_ports_d + 10714 _soc_kt2_mmu_params.mmu_num_cpu_port + 10715 _soc_kt2_mmu_params.mmu_num_loopback_port + 10716 _soc_kt2_mmu_params.mmu_num_olp_port_d; 10717 10718 /* C76 = C19+C25+C31+C37 ) */ 10719 general_info->total_num_of_ports_excl_lpbk = 10720 _soc_kt2_mmu_params.num_ge_ports_d + 10721 _soc_kt2_mmu_params.num_hg_ports_d + 10722 _soc_kt2_mmu_params.mmu_num_cpu_port + 10723 _soc_kt2_mmu_params.mmu_num_olp_port_d; 10724 10725 /* C77 = C19+C25+C31 */ 10726 general_info->total_num_of_ports_excl_lpbk_olp = 10727 _soc_kt2_mmu_params.num_ge_ports_d + 10728 _soc_kt2_mmu_params.num_hg_ports_d + 10729 _soc_kt2_mmu_params.mmu_num_cpu_port; 10730 10731 /* C78 = C19+C25 */ 10732 general_info->total_num_of_ports_excl_lpbk_olp_cpu = 10733 _soc_kt2_mmu_params.num_ge_ports_d + 10734 _soc_kt2_mmu_params.num_hg_ports_d; 10735 10736 /* C79 = C23*C20+C29*C26 */ 10737 general_info->port_bw_bound_to_ext_buff = 10738 (_soc_kt2_mmu_params.num_ge_ext_ports_d * 10739 _soc_kt2_mmu_params.mmu_line_rate_ge) + 10740 (_soc_kt2_mmu_params.num_hg_ext_ports_d * 10741 _soc_kt2_mmu_params.mmu_line_rate_hg) ; 10742 10743 /* C80 = C22*C21 */ 10744 general_info->total_egr_queues_for_a_int_ge_ports = 10745 (_soc_kt2_mmu_params.num_egr_queue_per_int_ge_port_d * 10746 _soc_kt2_mmu_params.num_ge_int_ports_d); 10747 10748 /* C81 = C24*C23 */ 10749 general_info->total_egr_queues_for_a_ext_ge_ports = 10750 (_soc_kt2_mmu_params.num_egr_queue_per_ext_ge_port_d * 10751 _soc_kt2_mmu_params.num_ge_ext_ports_d); 10752 10753 /* C82 = C28*C27 */ 10754 general_info->total_egr_queues_for_a_int_hg_ports = 10755 (_soc_kt2_mmu_params.num_egr_queue_per_int_hg_port_d * 10756 _soc_kt2_mmu_params.num_hg_int_ports_d); 10757 10758 /* C83 = C30*C29 */ 10759 general_info->total_egr_queues_for_a_ext_hg_ports = 10760 (_soc_kt2_mmu_params.num_egr_queue_per_ext_hg_port_d * 10761 _soc_kt2_mmu_params.num_hg_ext_ports_d); 10762 10763 /* C84 = C31*C32 */ 10764 general_info->total_cpu_queues = 10765 (_soc_kt2_mmu_params.mmu_num_cpu_port * 10766 _soc_kt2_mmu_params.mmu_num_cpu_queue); 10767 10768 /* C85 = $C$80+$C$82+IF(C33=0,C84,0)+IF(C39=0,C38,0)+C35+C36/2 */ 10769 general_info->total_int_buff_queues = 10770 (general_info->total_egr_queues_for_a_int_ge_ports + 10771 general_info->total_egr_queues_for_a_int_hg_ports); 10772 if (_soc_kt2_mmu_params.cpu_port_int_ext_bounding_d_c == 0) { 10773 general_info->total_int_buff_queues += general_info->total_cpu_queues; 10774 } 10775 if (_soc_kt2_mmu_params.olp_port_int_ext_bounding_d_c == 0) { 10776 general_info->total_int_buff_queues += 10777 _soc_kt2_mmu_params.mmu_num_olp_queue; 10778 } 10779 general_info->total_int_buff_queues += 10780 _soc_kt2_mmu_params.mmu_num_loopback_queue; 10781 general_info->total_int_buff_queues += 10782 (_soc_kt2_mmu_params.mmu_num_ep_redirection_queue / 2); 10783 10784 /* C86 = $C$81+$C$83+IF(C33=1,C84,0)+IF(C39=1,C38,0)+IF(C17=1,C36/2,0) */ 10785 general_info->total_ext_buff_queues = 10786 (general_info->total_egr_queues_for_a_ext_ge_ports + 10787 general_info->total_egr_queues_for_a_ext_hg_ports); 10788 if (_soc_kt2_mmu_params.cpu_port_int_ext_bounding_d_c) { 10789 general_info->total_ext_buff_queues += general_info->total_cpu_queues; 10790 } 10791 if (_soc_kt2_mmu_params.olp_port_int_ext_bounding_d_c) { 10792 general_info->total_ext_buff_queues += 10793 _soc_kt2_mmu_params.mmu_num_olp_queue; 10794 } 10795 if (_soc_kt2_mmu_params.extbuf_used_d_c) { 10796 general_info->total_ext_buff_queues += 10797 (_soc_kt2_mmu_params.mmu_num_ep_redirection_queue/2); 10798 } 10799 10800 /* C54 = =($C$81+$C$83+IF(C33=1,C84,0)+IF(C39=1,C38,0)+IF(C17=1,C36/2,0))*2 */ 10801 /* = C86 * 2 */ 10802 if (_soc_kt2_mmu_params.packing_mode_d_c) { 10803 _soc_kt2_mmu_params.num_cells_rsrvd_ing_ext_buf = 10804 general_info->total_ext_buff_queues * 2; 10805 } 10806 10807 /* C87 = C52 */ 10808 general_info->total_ema_queues = _soc_kt2_mmu_params.mmu_ema_queues; 10809 10810 /* C90 = C85+C86 */ 10811 general_info->total_egr_queues_in_device = 10812 general_info->total_int_buff_queues + 10813 general_info->total_ext_buff_queues; 10814 10815 /* C91 = FLOOR($C$41*1024*1024/($C$9+2),1)-C43 */ 10816 general_info->max_int_cell_buff_size = floor_func( 10817 _soc_kt2_mmu_params.mmu_int_buf_size*1024*1024, 10818 _soc_kt2_mmu_params.mmu_int_buf_cell_size+2) ; 10819 general_info->max_int_cell_buff_size -= 10820 _soc_kt2_mmu_params.mmu_reserved_int_buf_cells; 10821 10822 /* C92 = C91 */ 10823 general_info->int_cell_buff_size_after_limitation = 10824 general_info->max_int_cell_buff_size; 10825 10826 /* C93 = C75*C13 */ 10827 if (_soc_kt2_mmu_params.packing_mode_d_c) { 10828 general_info->src_packing_fifo = general_info->total_num_of_ports * 10829 _soc_kt2_mmu_params.max_pkt_size_support_packing; 10830 } 10831 10832 /* C94 = FLOOR($C$42 *( IF($C$45, $C$92, $C$91) , 1) */ 10833 if (_soc_kt2_mmu_params.internal_buffer_reduction_d_c) { 10834 temp_val = general_info->int_cell_buff_size_after_limitation; 10835 } else { 10836 temp_val = general_info->max_int_cell_buff_size; 10837 } 10838 /* temp_val -= input_port_threshold->total_hdrm_int_buff_cells; */ 10839 temp_val = (_soc_kt2_mmu_params.mmu_available_int_buf_size_d * temp_val)/100; 10840 /* Packed : C94 = FLOOR($C$42 *( IF($C$45, $C$92, $C$91) , 1) - C93 */ 10841 if (_soc_kt2_mmu_params.packing_mode_d_c) { 10842 temp_val -= general_info->src_packing_fifo; 10843 } 10844 general_info->int_buff_pool = temp_val; 10845 10846 /* C95 = IF($C$45,$C$92,$C$91)-C94 */ 10847 if (_soc_kt2_mmu_params.internal_buffer_reduction_d_c) { 10848 temp_val = general_info->int_cell_buff_size_after_limitation; 10849 } else { 10850 temp_val = general_info->max_int_cell_buff_size;; 10851 } 10852 temp_val = temp_val - general_info->int_buff_pool; 10853 /* Packed : C95 = IF($C$45,$C$92,$C$91)-C94-C93 */ 10854 if (_soc_kt2_mmu_params.packing_mode_d_c) { 10855 temp_val -= general_info->src_packing_fifo; 10856 } 10857 general_info->ema_pool = temp_val; 10858 10859 /* C96 = IF($C$17,$C$46*1024*1024/$C$10,0) */ 10860 if (_soc_kt2_mmu_params.extbuf_used_d_c) { 10861 general_info->max_ext_cell_buff_size = 10862 (_soc_kt2_mmu_params.mmu_ext_buf_size*1024*1024)/ 10863 (_soc_kt2_mmu_params.mmu_ext_buf_cell_size); 10864 } 10865 10866 /* C99 = $C$10/($C$9+2) */ 10867 general_info->ratio_of_ext_buff_to_int_buff_size = 10868 _soc_kt2_mmu_params.mmu_ext_buf_cell_size / 10869 (_soc_kt2_mmu_params.mmu_int_buf_cell_size + 2); 10870 10871 /* C100 = 1 */ 10872 general_info->int_buff_cells_per_avg_size_pkt = 1; 10873 10874 /* C101 = 1 */ 10875 general_info->ext_buff_cells_per_avg_size_pkt = 1; 10876 10877 /* C102 = 0.75 but normalized to 1 */ 10878 general_info->max_prop_of_buff_used_by_one_queue_port = 75; 10879 10880 10881 /* Fill up input threshold info */ 10882 /* C107 = CEILING(20*1024/C9, 1) */ 10883 input_port_threshold->global_hdrm_cells_for_int_buff_pool = ceil_func( 10884 (20*1024),_soc_kt2_mmu_params.mmu_int_buf_cell_size); 10885 10886 /* C108 = CEILING( IF($C$17, $C$107/$C$99, 0),1) */ 10887 if ( _soc_kt2_mmu_params.extbuf_used_d_c && 10888 (_soc_kt2_mmu_params.packing_mode_d_c == 0)) { 10889 input_port_threshold->global_hdrm_cells_for_ext_buff_pool = ceil_func( 10890 input_port_threshold->global_hdrm_cells_for_int_buff_pool, 10891 general_info->ratio_of_ext_buff_to_int_buff_size); 10892 } 10893 /* C109,110 = 0 */ 10894 /* C112-C115 values are zero for lossy mode */ 10895 if (_soc_kt2_mmu_params.lossless_mode_d_c) { 10896 if ((ext_mem_port_count) || (_soc_kt2_mmu_params.packing_mode_d_c)) { 10897 /* C112*/ 10898 input_port_threshold->hdrm_int_buff_cells_for_10G_PG = 76; 10899 /* C113*/ 10900 input_port_threshold->hdrm_ext_buff_cells_for_10G_PG = 67; 10901 /* C114*/ 10902 input_port_threshold->hdrm_RE_WQEs_pkts_for_10G_PG = 67; 10903 } else { 10904 /* C112*/ 10905 input_port_threshold->hdrm_int_buff_cells_for_10G_PG = 180; 10906 /* C113*/ 10907 input_port_threshold->hdrm_ext_buff_cells_for_10G_PG = 0; 10908 /* C114*/ 10909 input_port_threshold->hdrm_RE_WQEs_pkts_for_10G_PG = 159; 10910 } 10911 /* C115 = C114*C49 */ 10912 input_port_threshold->hdrm_EQEs_pkts_for_10G_PG = 10913 input_port_threshold->hdrm_RE_WQEs_pkts_for_10G_PG * 10914 _soc_kt2_mmu_params.mmu_exp_num_of_repl_per_pkt; 10915 } 10916 10917 /* C117 = C25*C16*$C$112 */ 10918 input_port_threshold->hdrm_int_buff_cells_for_10G_total_PG = 10919 (_soc_kt2_mmu_params.num_hg_ports_d * 10920 _soc_kt2_mmu_params.mmu_lossless_pg_num * 10921 input_port_threshold->hdrm_int_buff_cells_for_10G_PG); 10922 10923 /* C118 = C25*C16*C113 */ 10924 input_port_threshold->hdrm_ext_buff_cells_for_10G_total_PG = 10925 (_soc_kt2_mmu_params.num_hg_ports_d * 10926 _soc_kt2_mmu_params.mmu_lossless_pg_num * 10927 input_port_threshold->hdrm_ext_buff_cells_for_10G_PG); 10928 10929 /* C119 = C25*C16*C114 */ 10930 input_port_threshold->hdrm_RE_WQEs_pkts_for_10G_total_PG = 10931 (_soc_kt2_mmu_params.num_hg_ports_d * 10932 _soc_kt2_mmu_params.mmu_lossless_pg_num * 10933 input_port_threshold->hdrm_RE_WQEs_pkts_for_10G_PG); 10934 10935 /* C120 = C25*C16*C115 */ 10936 input_port_threshold->hdrm_EQEs_pkts_for_10G_total_PG = 10937 (_soc_kt2_mmu_params.num_hg_ports_d * 10938 _soc_kt2_mmu_params.mmu_lossless_pg_num * 10939 input_port_threshold->hdrm_EQEs_pkts_for_10G_PG); 10940 10941 /* C122-C125 values are zero for lossy mode */ 10942 if (_soc_kt2_mmu_params.lossless_mode_d_c) { 10943 if ((ext_mem_port_count) || (_soc_kt2_mmu_params.packing_mode_d_c)) { 10944 /* C122 */ 10945 input_port_threshold->hdrm_int_buff_cells_for_1G_PG = 26; 10946 /* C123 */ 10947 input_port_threshold->hdrm_ext_buff_cells_for_1G_PG = 23; 10948 /* C124 */ 10949 input_port_threshold->hdrm_RE_WQEs_pkts_for_1G_PG = 23; 10950 } else { 10951 /* C122 */ 10952 input_port_threshold->hdrm_int_buff_cells_for_1G_PG = 130; 10953 /* C123 */ 10954 input_port_threshold->hdrm_ext_buff_cells_for_1G_PG = 0; 10955 /* C124 */ 10956 input_port_threshold->hdrm_RE_WQEs_pkts_for_1G_PG = 115; 10957 } 10958 /* C125 = C124*C49 */ 10959 input_port_threshold->hdrm_EQEs_pkts_for_1G_PG = 10960 input_port_threshold->hdrm_RE_WQEs_pkts_for_1G_PG * 10961 _soc_kt2_mmu_params.mmu_exp_num_of_repl_per_pkt; 10962 } 10963 10964 /* C127 = C19*C16*$C$122 */ 10965 input_port_threshold->hdrm_int_buff_cells_for_1G_total_PG = 10966 (_soc_kt2_mmu_params.num_ge_ports_d * 10967 _soc_kt2_mmu_params.mmu_lossless_pg_num * 10968 input_port_threshold->hdrm_int_buff_cells_for_1G_PG); 10969 10970 /* C128 = C19*C16*$C$123 */ 10971 input_port_threshold->hdrm_ext_buff_cells_for_1G_total_PG = 10972 (_soc_kt2_mmu_params.num_ge_ports_d * 10973 _soc_kt2_mmu_params.mmu_lossless_pg_num * 10974 input_port_threshold->hdrm_ext_buff_cells_for_1G_PG); 10975 10976 /* C129 = C19*C16*$C$124 */ 10977 input_port_threshold->hdrm_RE_WQEs_pkts_for_1G_total_PG = 10978 (_soc_kt2_mmu_params.num_ge_ports_d * 10979 _soc_kt2_mmu_params.mmu_lossless_pg_num * 10980 input_port_threshold->hdrm_RE_WQEs_pkts_for_1G_PG); 10981 10982 /* C130 = C19*C16*$C$125 */ 10983 input_port_threshold->hdrm_EQEs_pkts_for_1G_total_PG = 10984 (_soc_kt2_mmu_params.num_ge_ports_d * 10985 _soc_kt2_mmu_params.mmu_lossless_pg_num * 10986 input_port_threshold->hdrm_EQEs_pkts_for_1G_PG); 10987 10988 /* C132-C135 values are zero for lossy mode */ 10989 if (_soc_kt2_mmu_params.lossless_mode_d_c) { 10990 if ((ext_mem_port_count) || (_soc_kt2_mmu_params.packing_mode_d_c)) { 10991 /* C132 */ 10992 input_port_threshold->hdrm_int_buff_cells_for_olp_port = 76; 10993 /* C133 */ 10994 input_port_threshold->hdrm_ext_buff_cells_for_olp_port = 67; 10995 /* C134 */ 10996 input_port_threshold->hdrm_RE_WQEs_pkts_for_olp_port = 67; 10997 } else { 10998 /* C132 */ 10999 input_port_threshold->hdrm_int_buff_cells_for_olp_port = 180; 11000 /* C133 */ 11001 input_port_threshold->hdrm_ext_buff_cells_for_olp_port = 0; 11002 /* C134 */ 11003 input_port_threshold->hdrm_RE_WQEs_pkts_for_olp_port = 159; 11004 } 11005 /* C135 = C134*C49 */ 11006 input_port_threshold->hdrm_EQEs_pkts_for_olp_port = 11007 input_port_threshold->hdrm_RE_WQEs_pkts_for_olp_port * 11008 _soc_kt2_mmu_params.mmu_exp_num_of_repl_per_pkt; 11009 } 11010 11011 /* C137 = 46 */ 11012 input_port_threshold->hdrm_int_buff_cells_for_lpbk_port = 46; 11013 11014 /* C138 = 40 for external buffer */ 11015 if ((ext_mem_port_count) || (_soc_kt2_mmu_params.packing_mode_d_c)) { 11016 input_port_threshold->hdrm_ext_buff_cells_for_lpbk_port = 40; 11017 } 11018 11019 /* C139 = 40 */ 11020 input_port_threshold->hdrm_RE_WQEs_pkts_for_lpbk_port = 40; 11021 11022 /* C140 = C139*C49 */ 11023 input_port_threshold->hdrm_EQEs_pkts_for_lpbk_port = 11024 input_port_threshold->hdrm_RE_WQEs_pkts_for_lpbk_port * 11025 _soc_kt2_mmu_params.mmu_exp_num_of_repl_per_pkt; 11026 11027 /* C142 = 46 */ 11028 input_port_threshold->hdrm_int_buff_cells_for_cpu_port = 46; 11029 11030 /* C143 = 40 for external buffer */ 11031 if ((ext_mem_port_count) || (_soc_kt2_mmu_params.packing_mode_d_c)) { 11032 input_port_threshold->hdrm_ext_buff_cells_for_cpu_port = 40; 11033 } 11034 11035 /* C144 = 40 */ 11036 input_port_threshold->hdrm_RE_WQEs_pkts_for_cpu_port = 40; 11037 11038 /* C145 = C144*C49 */ 11039 input_port_threshold->hdrm_EQEs_pkts_for_cpu_port = 11040 input_port_threshold->hdrm_RE_WQEs_pkts_for_cpu_port * 11041 _soc_kt2_mmu_params.mmu_exp_num_of_repl_per_pkt; 11042 11043 /* C147 = $C$107+$C$117+$C$127+C132+C137+C142 */ 11044 input_port_threshold->total_hdrm_int_buff_cells = 11045 input_port_threshold->global_hdrm_cells_for_int_buff_pool + 11046 input_port_threshold->hdrm_int_buff_cells_for_10G_total_PG + 11047 input_port_threshold->hdrm_int_buff_cells_for_1G_total_PG + 11048 input_port_threshold->hdrm_int_buff_cells_for_olp_port + 11049 input_port_threshold->hdrm_int_buff_cells_for_lpbk_port + 11050 input_port_threshold->hdrm_int_buff_cells_for_cpu_port; 11051 11052 /* C148 = $C$107+$C$117+$C$127+C132+C137+C142. For internal memory=0*/ 11053 if ((ext_mem_port_count) || (_soc_kt2_mmu_params.packing_mode_d_c)) { 11054 input_port_threshold->total_hdrm_int_buff_ema_pool_cells = 11055 input_port_threshold->global_hdrm_cells_for_int_buff_pool + 11056 input_port_threshold->hdrm_int_buff_cells_for_10G_total_PG + 11057 input_port_threshold->hdrm_int_buff_cells_for_1G_total_PG + 11058 input_port_threshold->hdrm_int_buff_cells_for_olp_port + 11059 input_port_threshold->hdrm_int_buff_cells_for_lpbk_port + 11060 input_port_threshold->hdrm_int_buff_cells_for_cpu_port; 11061 } 11062 11063 /* C149 = $C$108+$C$118+$C$128++C133+C138+C143 */ 11064 input_port_threshold->total_hdrm_ext_buff_cells = 11065 input_port_threshold->global_hdrm_cells_for_ext_buff_pool+ 11066 input_port_threshold->hdrm_ext_buff_cells_for_10G_total_PG+ 11067 input_port_threshold->hdrm_ext_buff_cells_for_1G_total_PG+ 11068 input_port_threshold->hdrm_ext_buff_cells_for_olp_port+ 11069 input_port_threshold->hdrm_ext_buff_cells_for_lpbk_port+ 11070 input_port_threshold->hdrm_ext_buff_cells_for_cpu_port; 11071 11072 /* C150 = $C$109+$C$119+$C$129+C134+C139+C144 */ 11073 input_port_threshold->total_hdrm_RE_WQEs_pkts = 11074 input_port_threshold->global_hdrm_cells_for_RE_WQEs+ 11075 input_port_threshold->hdrm_RE_WQEs_pkts_for_10G_total_PG+ 11076 input_port_threshold->hdrm_RE_WQEs_pkts_for_1G_total_PG+ 11077 input_port_threshold->hdrm_RE_WQEs_pkts_for_olp_port+ 11078 input_port_threshold->hdrm_RE_WQEs_pkts_for_lpbk_port+ 11079 input_port_threshold->hdrm_RE_WQEs_pkts_for_cpu_port; 11080 11081 /* C151 = $C$110+$C$120+$C$130+C135+C140+C145 */ 11082 input_port_threshold->total_hdrm_EQEs_pkts = 11083 input_port_threshold->global_hdrm_cells_for_EQEs+ 11084 input_port_threshold->hdrm_EQEs_pkts_for_10G_total_PG+ 11085 input_port_threshold->hdrm_EQEs_pkts_for_1G_total_PG+ 11086 input_port_threshold->hdrm_EQEs_pkts_for_olp_port+ 11087 input_port_threshold->hdrm_EQEs_pkts_for_lpbk_port+ 11088 input_port_threshold->hdrm_EQEs_pkts_for_cpu_port; 11089 11090 /* C153 = $C$69 */ 11091 if (_soc_kt2_mmu_params.lossless_mode_d_c && 11092 (_soc_kt2_mmu_params.packing_mode_d_c || 11093 _soc_kt2_mmu_params.extbuf_used_d_c) ) { 11094 /* As per MMU team's suggestion for avoiding #crash# */ 11095 input_port_threshold->min_int_buff_cells_per_PG = 9; 11096 } else { 11097 input_port_threshold->min_int_buff_cells_per_PG = 11098 general_info->jumbo_frame_for_int_buff; 11099 } 11100 11101 /* C154 = IF($C$17, $C$153, 0) */ 11102 if (_soc_kt2_mmu_params.extbuf_used_d_c) { 11103 input_port_threshold->min_int_buff_ema_pool_cells_per_PG = 11104 input_port_threshold->min_int_buff_cells_per_PG; 11105 } 11106 11107 /* C155 = CEILING(IF($C$17, $C$153/$C$99, 0), 1) */ 11108 if (_soc_kt2_mmu_params.extbuf_used_d_c) { 11109 input_port_threshold->min_ext_buff_cells_per_PG = ceil_func( 11110 input_port_threshold->min_int_buff_cells_per_PG, 11111 general_info->ratio_of_ext_buff_to_int_buff_size); 11112 } 11113 11114 /* C156 = $C$153/$C$100 */ 11115 input_port_threshold->min_RE_WQEs_pkt_per_PG = 11116 input_port_threshold->min_int_buff_cells_per_PG/ 11117 general_info->int_buff_cells_per_avg_size_pkt; 11118 11119 /* C157 = $C$153/$C$100*C49 */ 11120 input_port_threshold->min_EQEs_pkt_per_PG = 11121 (input_port_threshold->min_int_buff_cells_per_PG/ 11122 general_info->int_buff_cells_per_avg_size_pkt) * 11123 _soc_kt2_mmu_params.mmu_exp_num_of_repl_per_pkt; 11124 11125 /* C159 = C75*C16*$C$153 */ 11126 input_port_threshold->min_int_buff_cells_for_total_PG = 11127 (general_info->total_num_of_ports * 11128 _soc_kt2_mmu_params.mmu_lossless_pg_num * 11129 input_port_threshold->min_int_buff_cells_per_PG) ; 11130 11131 /* C160 = C75*C16*$C$154 */ 11132 input_port_threshold->min_int_buff_ema_pool_cells_for_total_PG = 11133 (general_info->total_num_of_ports * 11134 _soc_kt2_mmu_params.mmu_lossless_pg_num * 11135 input_port_threshold->min_int_buff_ema_pool_cells_per_PG); 11136 11137 /* C161 = C75*C16*$C$155 */ 11138 input_port_threshold->min_ext_buff_cells_for_total_PG = 11139 (general_info->total_num_of_ports * 11140 _soc_kt2_mmu_params.mmu_lossless_pg_num * 11141 input_port_threshold->min_ext_buff_cells_per_PG); 11142 11143 /* C162 = C75*C16*$C$156 */ 11144 input_port_threshold->min_RE_WQEs_pkts_for_total_PG = 11145 (general_info->total_num_of_ports * 11146 _soc_kt2_mmu_params.mmu_lossless_pg_num * 11147 input_port_threshold->min_RE_WQEs_pkt_per_PG) ; 11148 11149 /* C163 = C75*C16*$C$157 */ 11150 input_port_threshold->min_EQEs_pkts_for_total_PG = 11151 (general_info->total_num_of_ports * 11152 _soc_kt2_mmu_params.mmu_lossless_pg_num * 11153 input_port_threshold->min_EQEs_pkt_per_PG) ; 11154 11155 /* C165 = 0 */ 11156 input_port_threshold->min_int_buff_cells_for_a_port = 0; 11157 11158 /* C166 = IF($C$17, $C$165, 0) */ 11159 if (_soc_kt2_mmu_params.extbuf_used_d_c) { 11160 input_port_threshold->min_int_buff_ema_pool_cells_for_a_port = 11161 input_port_threshold->min_int_buff_cells_for_a_port ; 11162 } 11163 11164 /* C167 = CEILING(IF($C$17, $C$165/$C$99, 0),1) */ 11165 if (_soc_kt2_mmu_params.extbuf_used_d_c) { 11166 input_port_threshold->min_ext_buff_cells_for_a_port = 11167 input_port_threshold->min_int_buff_cells_for_a_port/ 11168 general_info->ratio_of_ext_buff_to_int_buff_size; 11169 } 11170 11171 /* C168 = $C$165/$C$100 */ 11172 input_port_threshold->min_RE_WQEs_pkts_for_a_port = 11173 input_port_threshold->min_int_buff_cells_for_a_port / 11174 general_info->int_buff_cells_per_avg_size_pkt; 11175 11176 /* C169 = $C$165/$C$100*C49 */ 11177 input_port_threshold->min_EQEs_pkts_for_a_port = 11178 (input_port_threshold->min_int_buff_cells_for_a_port / 11179 general_info->int_buff_cells_per_avg_size_pkt) * 11180 _soc_kt2_mmu_params.mmu_exp_num_of_repl_per_pkt; 11181 11182 11183 /* C171 = $C$75*$C$165 */ 11184 input_port_threshold->min_int_buff_cells_for_total_port = 11185 (general_info->total_num_of_ports * 11186 input_port_threshold->min_int_buff_cells_for_a_port); 11187 11188 /* C172 = $C$75*$C$166 */ 11189 input_port_threshold->min_int_buff_ema_pool_cells_for_total_port = 11190 (general_info->total_num_of_ports * 11191 input_port_threshold->min_int_buff_ema_pool_cells_for_a_port); 11192 11193 /* C173 = $C$75*$C$167 */ 11194 input_port_threshold->min_ext_buff_cells_for_total_port = 11195 (general_info->total_num_of_ports * 11196 input_port_threshold->min_ext_buff_cells_for_a_port); 11197 11198 /* C174 = $C$75*$C$168 */ 11199 input_port_threshold->min_RE_WQEs_pkts_for_total_port = 11200 (general_info->total_num_of_ports * 11201 input_port_threshold->min_RE_WQEs_pkts_for_a_port); 11202 11203 /* C175 = $C$75*$C$169 */ 11204 input_port_threshold->min_EQEs_pkts_for_total_port = 11205 (general_info->total_num_of_ports * 11206 input_port_threshold->min_EQEs_pkts_for_a_port); 11207 11208 /* C177 = $C$159+$C$171 */ 11209 input_port_threshold->total_min_int_buff_cells = 11210 input_port_threshold->min_int_buff_cells_for_total_PG + 11211 input_port_threshold->min_int_buff_cells_for_total_port; 11212 11213 /* C178 = $C$160+$C$172 */ 11214 input_port_threshold->total_min_int_buff_ema_pool_cells = 11215 input_port_threshold->min_int_buff_ema_pool_cells_for_total_PG + 11216 input_port_threshold->min_int_buff_ema_pool_cells_for_total_port; 11217 11218 /* C179 = $C$161+$C$173 */ 11219 input_port_threshold->total_min_ext_buff_cells = 11220 input_port_threshold->min_ext_buff_cells_for_total_PG + 11221 input_port_threshold->min_ext_buff_cells_for_total_port; 11222 11223 /* C180 = $C$162+$C$174 */ 11224 input_port_threshold->total_min_RE_WQEs_pkts = 11225 input_port_threshold->min_RE_WQEs_pkts_for_total_PG + 11226 input_port_threshold->min_RE_WQEs_pkts_for_total_port; 11227 11228 /* C181 = $C$163+$C$175 */ 11229 input_port_threshold->total_min_EQEs_pkts = 11230 input_port_threshold->min_EQEs_pkts_for_total_PG + 11231 input_port_threshold->min_EQEs_pkts_for_total_port; 11232 11233 /* Need to Defer as C183-C196 value depend on C208,C211,C209,C212,C210 values */ 11234 11235 /* Fill up output threshold info */ 11236 /* C201 = C55 for lossy mode */ 11237 if (_soc_kt2_mmu_params.lossless_mode_d_c == 0) { 11238 output_port_threshold->min_grntd_res_queue_cells_int_buff = 11239 _soc_kt2_mmu_params.per_cos_res_cells_for_int_buff_d; 11240 } 11241 11242 /* C202 = CEILING(IF($C$14, 0, IF($C$17, $C$201/$C$99, 0)),1) */ 11243 if ((_soc_kt2_mmu_params.lossless_mode_d_c == 0) || 11244 _soc_kt2_mmu_params.packing_mode_d_c) { 11245 if (_soc_kt2_mmu_params.extbuf_used_d_c) { 11246 output_port_threshold->min_grntd_res_queue_cells_ext_buff = 11247 _soc_kt2_mmu_params.mmu_ext_buf_cell_size == 2880 ? 11248 12 : /* LCM of all possible cell usage */ 11249 ceil_func((output_port_threshold-> 11250 min_grntd_res_queue_cells_int_buff), 11251 (general_info->ratio_of_ext_buff_to_int_buff_size)); 11252 } 11253 } 11254 11255 /* C203 = $C$55/$C$100(for lossy:external), $C$55/$C$101(for lossy:internal */ 11256 if (_soc_kt2_mmu_params.lossless_mode_d_c == 0) { 11257 if (_soc_kt2_mmu_params.extbuf_used_d_c) { 11258 output_port_threshold->min_grntd_res_queue_cells_EQEs = 11259 _soc_kt2_mmu_params.per_cos_res_cells_for_int_buff_d/ 11260 general_info->int_buff_cells_per_avg_size_pkt; 11261 } else { 11262 output_port_threshold->min_grntd_res_queue_cells_EQEs = 11263 _soc_kt2_mmu_params.per_cos_res_cells_for_int_buff_d/ 11264 general_info->ext_buff_cells_per_avg_size_pkt; 11265 11266 } 11267 } 11268 11269 /* C204 = IF($C$14, 0, IF($C$17, $C$55, 0)) */ 11270 if (_soc_kt2_mmu_params.lossless_mode_d_c == 0) { 11271 if (_soc_kt2_mmu_params.extbuf_used_d_c) { 11272 output_port_threshold->min_grntd_res_EMA_queue_cells = 11273 _soc_kt2_mmu_params.per_cos_res_cells_for_int_buff_d; 11274 } 11275 } 11276 11277 /* C205 = C201 */ 11278 output_port_threshold->min_grntd_res_RE_WQs_cells = 11279 output_port_threshold->min_grntd_res_queue_cells_int_buff; 11280 11281 /* C206 = C201 */ 11282 output_port_threshold->min_grntd_res_RE_WQs_queue_cells_for_int_buff = 11283 output_port_threshold->min_grntd_res_queue_cells_int_buff; 11284 11285 /* C207 = CEILING(IF($C$14, 0, IF($C$17, C206/$C$99, 0)),1) */ 11286 /* Raj: if (_soc_kt2_mmu_params.lossless_mode_d_c == 0) { */ 11287 if (_soc_kt2_mmu_params.extbuf_used_d_c) { 11288 output_port_threshold-> 11289 min_grntd_res_RE_WQs_queue_cells_for_ext_buff = ceil_func( 11290 output_port_threshold-> 11291 min_grntd_res_RE_WQs_queue_cells_for_int_buff, 11292 general_info->ratio_of_ext_buff_to_int_buff_size); 11293 } 11294 /* } */ 11295 11296 /* C208 = 4 */ 11297 output_port_threshold->min_grntd_res_EP_redirect_queue_entry_cells = 4; 11298 adjust_min_grntd = 0; 11299 for(port_index = 0 ; 11300 port_index < COUNTOF(port_list); 11301 port_index++) { 11302 11303 port = port_list[port_index]; 11304 11305 if (!SOC_PBMP_MEMBER(valid_port_cpu_pbmp, port)) { 11306 continue; 11307 } 11308 11309 buf_port = &buf->ports[port]; 11310 11311 for (queue = si->port_uc_cosq_base[port]; 11312 queue < si->port_uc_cosq_base[port] + 11313 si->port_num_uc_cosq[port]; 11314 queue++) { 11315 /* caluculating idx as per the mmu_config tool*/ 11316 idx = si->port_num_cosq[port] + queue - si->port_uc_cosq_base[port]; 11317 buf_queue = &buf_port->queues[idx]; 11318 if (buf_queue->guarantee) { 11319 adjust_min_grntd += 11320 (buf_queue->guarantee - 11321 output_port_threshold->min_grntd_res_queue_cells_int_buff); 11322 } 11323 11324 } 11325 } 11326 11327 if (_soc_kt2_mmu_params.lossless_mode_d_c == 0) { 11328 /* C210 = C85*$C$201 */ 11329 output_port_threshold->min_grntd_tot_res_queue_cells_int_buff = 11330 general_info->total_int_buff_queues * 11331 output_port_threshold->min_grntd_res_queue_cells_int_buff; 11332 } else { 11333 /* C210 = ($C$80+C82)*$C$201+IF(C33=0,C32*C31*C72)+(C35+C36/2)*C72 */ 11334 output_port_threshold->min_grntd_tot_res_queue_cells_int_buff = 11335 (general_info->total_egr_queues_for_a_int_ge_ports + 11336 general_info->total_egr_queues_for_a_int_hg_ports) * 11337 output_port_threshold->min_grntd_res_queue_cells_int_buff; 11338 if (_soc_kt2_mmu_params.cpu_port_int_ext_bounding_d_c == 0) { 11339 output_port_threshold->min_grntd_tot_res_queue_cells_int_buff += 11340 _soc_kt2_mmu_params.mmu_num_cpu_queue * 11341 _soc_kt2_mmu_params.mmu_num_cpu_port * 11342 general_info->ether_mtu_cells_for_int_buff; 11343 } 11344 output_port_threshold->min_grntd_tot_res_queue_cells_int_buff += 11345 (_soc_kt2_mmu_params.mmu_num_loopback_queue + 11346 (_soc_kt2_mmu_params.mmu_num_ep_redirection_queue/2)) * 11347 general_info->ether_mtu_cells_for_int_buff; 11348 } 11349 11350 output_port_threshold->min_grntd_tot_res_queue_cells_int_buff += adjust_min_grntd; 11351 11352 if (_soc_kt2_mmu_params.lossless_mode_d_c == 0) { 11353 /* C211 = $C$86*$C$202 */ 11354 output_port_threshold->min_grntd_tot_res_queue_cells_ext_buff = 11355 general_info->total_ext_buff_queues * 11356 output_port_threshold->min_grntd_res_queue_cells_ext_buff; 11357 } else { 11358 /* C211 = ($C$81+C83)*$C$202+IF(C33=1,C32*C31, 0)*C72+IF(C17=1, (C36/2)*C72, 0) */ 11359 /* Packed Lossless : C211 = ($C$81+C83-C19*8)*$C$202+IF(C33=1,C32*C31, 0)*C72+IF(C17=1, (C36/2)*C72, 0) */ 11360 output_port_threshold->min_grntd_tot_res_queue_cells_ext_buff = 11361 (general_info->total_egr_queues_for_a_ext_ge_ports + 11362 general_info->total_egr_queues_for_a_ext_hg_ports); 11363 output_port_threshold->min_grntd_tot_res_queue_cells_ext_buff *= 11364 output_port_threshold->min_grntd_res_queue_cells_ext_buff; 11365 if (_soc_kt2_mmu_params.cpu_port_int_ext_bounding_d_c) { 11366 output_port_threshold->min_grntd_tot_res_queue_cells_ext_buff += 11367 (_soc_kt2_mmu_params.mmu_num_cpu_queue * 11368 _soc_kt2_mmu_params.mmu_num_cpu_port * 11369 general_info->ether_mtu_cells_for_int_buff); 11370 } 11371 if (_soc_kt2_mmu_params.extbuf_used_d_c) { 11372 output_port_threshold->min_grntd_tot_res_queue_cells_ext_buff += 11373 (_soc_kt2_mmu_params.mmu_num_ep_redirection_queue/2)* 11374 general_info->ether_mtu_cells_for_int_buff; 11375 } 11376 } 11377 adjust_min_grntd = 0; 11378 for(port_index = 0 ; 11379 port_index < COUNTOF(port_list); 11380 port_index++ ) { 11381 11382 port = port_list[port_index]; 11383 11384 if (!SOC_PBMP_MEMBER(valid_port_cpu_pbmp, port)) { 11385 continue; 11386 } 11387 11388 buf_port = &buf->ports[port]; 11389 for (queue = si->port_uc_cosq_base[port]; 11390 queue < si->port_uc_cosq_base[port] + si->port_num_uc_cosq[port]; 11391 queue++) { 11392 idx = si->port_num_cosq[port] + queue - si->port_uc_cosq_base[port]; 11393 buf_queue = &buf_port->queues[idx]; 11394 if (buf_queue->pkt_guarantee) { 11395 adjust_min_grntd += 11396 (buf_queue->pkt_guarantee - 11397 output_port_threshold->min_grntd_res_queue_cells_EQEs); 11398 } 11399 11400 } 11401 } 11402 11403 if (_soc_kt2_mmu_params.lossless_mode_d_c == 0) { 11404 /* C212 = C90*$C$203 */ 11405 /* Packed Lossy : C212 = (C90-C19*8)*$C$203 */ 11406 output_port_threshold->min_grntd_tot_res_queue_cells_EQEs = 11407 general_info->total_egr_queues_in_device; 11408 if (_soc_kt2_mmu_params.packing_mode_d_c) { 11409 output_port_threshold->min_grntd_tot_res_queue_cells_EQEs -= 11410 _soc_kt2_mmu_params.num_ge_ports_d * 8; 11411 } 11412 output_port_threshold->min_grntd_tot_res_queue_cells_EQEs *= 11413 output_port_threshold->min_grntd_res_queue_cells_EQEs; 11414 } else { 11415 /* C212 = =SUM(C80:C83)*$C$203+C32*C31*C72+C37*C38*C203+(C35+C36)*C72 */ 11416 output_port_threshold->min_grntd_tot_res_queue_cells_EQEs = 11417 (general_info->total_egr_queues_for_a_int_ge_ports + 11418 general_info->total_egr_queues_for_a_ext_ge_ports + 11419 general_info->total_egr_queues_for_a_int_hg_ports + 11420 general_info->total_egr_queues_for_a_int_hg_ports) * 11421 output_port_threshold->min_grntd_res_queue_cells_EQEs; 11422 output_port_threshold->min_grntd_tot_res_queue_cells_EQEs += 11423 (_soc_kt2_mmu_params.mmu_num_cpu_queue * 11424 _soc_kt2_mmu_params.mmu_num_cpu_port * 11425 general_info->ether_mtu_cells_for_int_buff); 11426 output_port_threshold->min_grntd_tot_res_queue_cells_EQEs += 11427 _soc_kt2_mmu_params.mmu_num_olp_port_d * 11428 _soc_kt2_mmu_params.mmu_num_olp_queue * 11429 output_port_threshold->min_grntd_res_queue_cells_EQEs; 11430 output_port_threshold->min_grntd_tot_res_queue_cells_EQEs += 11431 (_soc_kt2_mmu_params.mmu_num_loopback_queue + 11432 _soc_kt2_mmu_params.mmu_num_ep_redirection_queue) * 11433 general_info->ether_mtu_cells_for_int_buff; 11434 } 11435 output_port_threshold->min_grntd_tot_res_queue_cells_EQEs += adjust_min_grntd; 11436 11437 /* C213 = $C$52*$C$204 */ 11438 output_port_threshold->min_grntd_tot_res_EMA_queue_cells = 11439 _soc_kt2_mmu_params.mmu_ema_queues * 11440 output_port_threshold->min_grntd_res_EMA_queue_cells; 11441 11442 adjust_min_grntd = 0; 11443 for(cos=0; cos<SOC_REG_NUMELS(unit, OP_QUEUE_CONFIG1_THDORQEQr); cos++) { 11444 buf_rqe_queue = &buf->rqe_queues[cos]; 11445 if (buf_rqe_queue->pkt_guarantee) { 11446 adjust_min_grntd += (buf_rqe_queue->pkt_guarantee - 11447 output_port_threshold->min_grntd_res_RE_WQs_cells); 11448 } 11449 } 11450 /* C214 = $C$51*$C$205 */ 11451 output_port_threshold->min_grntd_tot_res_RE_WQs_cells = 11452 _soc_kt2_mmu_params.mmu_repl_engine_work_queue_in_device * 11453 output_port_threshold->min_grntd_res_RE_WQs_cells; 11454 output_port_threshold->min_grntd_tot_res_RE_WQs_cells += adjust_min_grntd; 11455 11456 adjust_min_grntd = 0; 11457 for(cos=0; cos<SOC_REG_NUMELS(unit, OP_QUEUE_CONFIG1_THDORQEIr); cos++) { 11458 buf_rqe_queue = &buf->rqe_queues[cos]; 11459 11460 if (buf_rqe_queue->guarantee) { 11461 adjust_min_grntd += (buf_rqe_queue->guarantee - 11462 output_port_threshold->min_grntd_res_RE_WQs_queue_cells_for_int_buff); 11463 } 11464 } 11465 /* C215 = $C$51*$C$206 */ 11466 output_port_threshold->min_grntd_tot_res_RE_WQs_queue_cells_for_int_buff = 11467 _soc_kt2_mmu_params.mmu_repl_engine_work_queue_in_device * 11468 output_port_threshold->min_grntd_res_RE_WQs_queue_cells_for_int_buff; 11469 11470 output_port_threshold->min_grntd_tot_res_RE_WQs_queue_cells_for_int_buff += adjust_min_grntd; 11471 11472 adjust_min_grntd = 0; 11473 for(cos=0; cos<SOC_REG_NUMELS(unit, OP_QUEUE_CONFIG1_THDORQEEr); cos++) { 11474 buf_rqe_queue = &buf->rqe_queues[cos]; 11475 if (buf_rqe_queue->ext_guarantee) { 11476 adjust_min_grntd += (buf_rqe_queue->ext_guarantee - 11477 output_port_threshold->min_grntd_res_RE_WQs_queue_cells_for_ext_buff); 11478 } 11479 } 11480 11481 /* C216 = $C$51*$C$207 */ 11482 output_port_threshold->min_grntd_tot_res_RE_WQs_queue_cells_for_ext_buff = 11483 _soc_kt2_mmu_params.mmu_repl_engine_work_queue_in_device * 11484 output_port_threshold->min_grntd_res_RE_WQs_queue_cells_for_ext_buff; 11485 11486 output_port_threshold-> 11487 min_grntd_tot_res_RE_WQs_queue_cells_for_ext_buff += adjust_min_grntd; 11488 11489 /* C217 = C208*(C36) */ 11490 output_port_threshold->min_grntd_tot_res_EP_redirect_queue_entry_cells = 11491 _soc_kt2_mmu_params.mmu_num_ep_redirection_queue * 11492 output_port_threshold->min_grntd_res_EP_redirect_queue_entry_cells; 11493 11494 /* Resuming C183-C196 values as C210,C213,C211,C214,C212 values are 11495 available now*/ 11496 11497 /* For Lossless : C183 = $C$94-$C$177 -$C$147 -$C$210 */ 11498 /* For Lossy : C183 = $C$94-$C$177 -$C$147 */ 11499 input_port_threshold->total_shared_ing_buff_pool = 11500 general_info->int_buff_pool - 11501 input_port_threshold->total_min_int_buff_cells - 11502 input_port_threshold->total_hdrm_int_buff_cells; 11503 if (_soc_kt2_mmu_params.lossless_mode_d_c) { 11504 if ( input_port_threshold->total_shared_ing_buff_pool < 11505 output_port_threshold->min_grntd_tot_res_queue_cells_int_buff) { 11506 return BCM_E_RESOURCE; 11507 } 11508 input_port_threshold->total_shared_ing_buff_pool -= 11509 output_port_threshold->min_grntd_tot_res_queue_cells_int_buff; 11510 } 11511 11512 /* C184 = $C$95-$C$178-$C$213 */ 11513 /* IntMemLossy = =IF(C17,$C$95-$C$178-$C$148,0) */ 11514 /* IntMemLossless =IF(C17,$C$95-$C$178-$C$148 -$C$213,0) */ 11515 /* IntExtMemLossy == $C$95-$C$178-$C$148 */ 11516 /* IntExtMemLossless == $C$95-$C$178-$C$148 -$C$213 */ 11517 if (_soc_kt2_mmu_params.extbuf_used_d_c) { 11518 input_port_threshold->total_shared_EMA_buff = 11519 general_info->ema_pool - 11520 input_port_threshold->total_min_int_buff_ema_pool_cells - 11521 input_port_threshold->total_hdrm_int_buff_ema_pool_cells; 11522 if (_soc_kt2_mmu_params.lossless_mode_d_c) { 11523 input_port_threshold->total_shared_EMA_buff -= 11524 output_port_threshold->min_grntd_tot_res_EMA_queue_cells; 11525 } 11526 } 11527 11528 /* C185 = if (lossless) $C$96-$C$149-$C$179-$C$211 11529 if (lossy) $C$96-$C$149-$C$179 11530 Packed Lossless $C$96-$C$149-$C$179-$C$211-C54 11531 Packed Lossy $C$96-$C$149-$C$179-C54 */ 11532 input_port_threshold->total_shared_ext_buff = 11533 general_info->max_ext_cell_buff_size - 11534 input_port_threshold->total_hdrm_ext_buff_cells - 11535 input_port_threshold->total_min_ext_buff_cells; 11536 if (_soc_kt2_mmu_params.lossless_mode_d_c) { 11537 input_port_threshold->total_shared_ext_buff -= 11538 output_port_threshold->min_grntd_tot_res_queue_cells_ext_buff; 11539 } 11540 if (_soc_kt2_mmu_params.packing_mode_d_c) { 11541 input_port_threshold->total_shared_ext_buff -= 11542 _soc_kt2_mmu_params.num_cells_rsrvd_ing_ext_buf; 11543 } 11544 11545 /* C186 = if (lossless) ($C$50*1024)-$C$150-$C$180-$C$214 11546 if (lossy) ($C$50*1024)-$C$150-$C$180 */ 11547 input_port_threshold->total_shared_RE_WQEs_buff = 11548 (_soc_kt2_mmu_params.mmu_repl_engine_work_queue_entries*1024) - 11549 input_port_threshold->total_hdrm_RE_WQEs_pkts - 11550 input_port_threshold->total_min_RE_WQEs_pkts; 11551 if (_soc_kt2_mmu_params.lossless_mode_d_c) { 11552 if (input_port_threshold->total_shared_RE_WQEs_buff < 11553 output_port_threshold->min_grntd_tot_res_RE_WQs_cells) { 11554 return SOC_E_RESOURCE; 11555 } 11556 input_port_threshold->total_shared_RE_WQEs_buff -= 11557 output_port_threshold->min_grntd_tot_res_RE_WQs_cells; 11558 } 11559 11560 /* C187 = if (lossless) ($C$47*1024)-$C$151-$C$181-$C$212 11561 if (lossy) ($C$47*1024)-$C$151-$C$181 */ 11562 input_port_threshold->total_shared_EQEs_buff = 11563 (_soc_kt2_mmu_params.mmu_egress_queue_entries * 1024) - 11564 input_port_threshold->total_hdrm_EQEs_pkts - 11565 input_port_threshold->total_min_EQEs_pkts; 11566 if (_soc_kt2_mmu_params.lossless_mode_d_c) { 11567 if (input_port_threshold->total_shared_EQEs_buff < 11568 output_port_threshold->min_grntd_tot_res_queue_cells_EQEs) { 11569 return BCM_E_RESOURCE; 11570 } 11571 input_port_threshold->total_shared_EQEs_buff -= 11572 output_port_threshold->min_grntd_tot_res_queue_cells_EQEs; 11573 } 11574 11575 /* C189 = FLOOR(($C$57*$C$183)/(1+($C$57*1)),1) */ 11576 input_port_threshold->ingress_burst_cells_size_for_one_port = floor_func( 11577 (_soc_kt2_mmu_params.mmu_ing_port_dyn_thd_param * 11578 input_port_threshold->total_shared_ing_buff_pool), 11579 (1+(_soc_kt2_mmu_params.mmu_ing_port_dyn_thd_param*1))); 11580 11581 /* C190 = FLOOR(($C$57*$C$187)/(1+($C$57*1)),1) */ 11582 input_port_threshold->ingress_burst_pkts_size_for_one_port = floor_func( 11583 (_soc_kt2_mmu_params.mmu_ing_port_dyn_thd_param * 11584 input_port_threshold->total_shared_EQEs_buff), 11585 (1+(_soc_kt2_mmu_params.mmu_ing_port_dyn_thd_param*1))); 11586 11587 /* C191 = FLOOR(($C$57*$C$183)/(1+($C$57*$C$75)),1) */ 11588 input_port_threshold->ingress_burst_cells_size_for_all_ports = floor_func( 11589 (_soc_kt2_mmu_params.mmu_ing_port_dyn_thd_param * 11590 input_port_threshold->total_shared_ing_buff_pool), 11591 (1+(_soc_kt2_mmu_params.mmu_ing_port_dyn_thd_param* 11592 general_info->total_num_of_ports))); 11593 11594 /* C192 = ($C$191+$C$165)*$C$75 */ 11595 input_port_threshold->ingress_total_shared_cells_use_for_all_port = 11596 (input_port_threshold->ingress_burst_cells_size_for_all_ports + 11597 input_port_threshold->min_int_buff_cells_for_a_port) * 11598 general_info->total_num_of_ports; 11599 11600 /* C193 = FLOOR(($C$57*$C$187)/(1+($C$57*$C$75)),1) */ 11601 input_port_threshold->ingress_burst_pkts_size_for_all_port = floor_func( 11602 _soc_kt2_mmu_params.mmu_ing_port_dyn_thd_param * 11603 input_port_threshold->total_shared_EQEs_buff, 11604 (1+(_soc_kt2_mmu_params.mmu_ing_port_dyn_thd_param* 11605 general_info->total_num_of_ports))); 11606 11607 /* C194 = ($C$193+$C$169)*$C$75 */ 11608 input_port_threshold->ingress_total_shared_pkts_use_for_all_port = 11609 (input_port_threshold->ingress_burst_pkts_size_for_all_port+ 11610 input_port_threshold->min_EQEs_pkts_for_a_port) * 11611 general_info->total_num_of_ports; 11612 11613 if ((ext_mem_port_count == 0) && 11614 (_soc_kt2_mmu_params.lossless_mode_d_c == 0) && 11615 (_soc_kt2_mmu_params.packing_mode_d_c == 0)) { 11616 /* C195 = $C$192+C147 */ 11617 input_port_threshold->ingress_total_shared_hdrm_cells_use_for_all_port = 11618 input_port_threshold->ingress_total_shared_cells_use_for_all_port + 11619 input_port_threshold->total_hdrm_int_buff_cells; 11620 } else { 11621 /* C195 = $C$192+C132 */ 11622 input_port_threshold->ingress_total_shared_hdrm_cells_use_for_all_port = 11623 input_port_threshold->ingress_total_shared_cells_use_for_all_port + 11624 input_port_threshold->hdrm_int_buff_cells_for_olp_port; 11625 } 11626 11627 if ((ext_mem_port_count == 0) && 11628 (_soc_kt2_mmu_params.lossless_mode_d_c == 0) && 11629 (_soc_kt2_mmu_params.packing_mode_d_c == 0)) { 11630 /* C196 = $C$194+C151 */ 11631 input_port_threshold->ingress_total_shared_hdrm_pkts_use_for_all_port = 11632 input_port_threshold->ingress_total_shared_pkts_use_for_all_port + 11633 input_port_threshold->total_hdrm_EQEs_pkts; 11634 } else { 11635 /* C196 = $C$194+C135 */ 11636 input_port_threshold->ingress_total_shared_hdrm_pkts_use_for_all_port = 11637 input_port_threshold->ingress_total_shared_pkts_use_for_all_port + 11638 input_port_threshold->hdrm_EQEs_pkts_for_olp_port; 11639 } 11640 11641 if ((_soc_kt2_mmu_params.lossless_mode_d_c == 0) && 11642 (_soc_kt2_mmu_params.extbuf_used_d_c)) { 11643 /* C219 = =$C$94-$C$210-C215 */ 11644 if ( general_info->int_buff_pool < ( output_port_threshold-> 11645 min_grntd_tot_res_queue_cells_int_buff + 11646 output_port_threshold-> 11647 min_grntd_tot_res_RE_WQs_queue_cells_for_int_buff)) { 11648 return BCM_E_RESOURCE; 11649 } 11650 output_port_threshold->min_grntd_tot_shr_queue_cells_int_buff = 11651 general_info->int_buff_pool - 11652 output_port_threshold-> 11653 min_grntd_tot_res_queue_cells_int_buff- 11654 output_port_threshold-> 11655 min_grntd_tot_res_RE_WQs_queue_cells_for_int_buff; 11656 } else { 11657 /* C219 = IF($C$45, $C$92, $C$91)-$C$210-C215 */ 11658 if (_soc_kt2_mmu_params.internal_buffer_reduction_d_c ) { 11659 output_port_threshold->min_grntd_tot_shr_queue_cells_int_buff = 11660 general_info->int_cell_buff_size_after_limitation; 11661 } else { 11662 output_port_threshold->min_grntd_tot_shr_queue_cells_int_buff = 11663 general_info->max_int_cell_buff_size ; 11664 } 11665 if ( output_port_threshold->min_grntd_tot_shr_queue_cells_int_buff < 11666 (output_port_threshold->min_grntd_tot_res_queue_cells_int_buff + 11667 output_port_threshold-> 11668 min_grntd_tot_res_RE_WQs_queue_cells_for_int_buff)) { 11669 return BCM_E_RESOURCE; 11670 } 11671 output_port_threshold->min_grntd_tot_shr_queue_cells_int_buff -= 11672 output_port_threshold->min_grntd_tot_res_queue_cells_int_buff ; 11673 output_port_threshold->min_grntd_tot_shr_queue_cells_int_buff -= 11674 output_port_threshold-> 11675 min_grntd_tot_res_RE_WQs_queue_cells_for_int_buff; 11676 } 11677 11678 /* C220 = $C$96-$C$211-C216 */ 11679 output_port_threshold->min_grntd_tot_shr_queue_cells_ext_buff = 11680 general_info->max_ext_cell_buff_size - 11681 output_port_threshold->min_grntd_tot_res_queue_cells_ext_buff; 11682 if (_soc_kt2_mmu_params.extbuf_used_d_c) { 11683 if (output_port_threshold->min_grntd_tot_shr_queue_cells_ext_buff < 11684 output_port_threshold->min_grntd_tot_res_RE_WQs_queue_cells_for_ext_buff) { 11685 return SOC_E_RESOURCE; 11686 } 11687 output_port_threshold->min_grntd_tot_shr_queue_cells_ext_buff -= 11688 output_port_threshold->min_grntd_tot_res_RE_WQs_queue_cells_for_ext_buff; 11689 } 11690 11691 if ((_soc_kt2_mmu_params.mmu_egress_queue_entries*1024) < 11692 output_port_threshold->min_grntd_tot_res_queue_cells_EQEs) { 11693 return SOC_E_RESOURCE; 11694 } 11695 /* C221 = $C$47*1024-$C$212 */ 11696 output_port_threshold->min_grntd_tot_shr_queue_cells_EQEs = 11697 (_soc_kt2_mmu_params.mmu_egress_queue_entries*1024) - 11698 output_port_threshold->min_grntd_tot_res_queue_cells_EQEs; 11699 11700 if ((_soc_kt2_mmu_params.lossless_mode_d_c) && 11701 (_soc_kt2_mmu_params.extbuf_used_d_c)) { 11702 /* C222 = IF($C$45,$C$92,$C$91)-$C$213 */ 11703 if (_soc_kt2_mmu_params.internal_buffer_reduction_d_c ) { 11704 output_port_threshold->min_grntd_tot_shr_EMA_queue_cells = 11705 general_info->int_cell_buff_size_after_limitation; 11706 } else { 11707 output_port_threshold->min_grntd_tot_shr_EMA_queue_cells = 11708 general_info->max_int_cell_buff_size; 11709 } 11710 output_port_threshold->min_grntd_tot_shr_EMA_queue_cells -= 11711 output_port_threshold->min_grntd_tot_res_EMA_queue_cells; 11712 } else { 11713 /* C222 = =$C$95-$C$213 */ 11714 output_port_threshold->min_grntd_tot_shr_EMA_queue_cells = 11715 general_info->ema_pool - 11716 output_port_threshold->min_grntd_tot_res_EMA_queue_cells; 11717 } 11718 if ((_soc_kt2_mmu_params.mmu_repl_engine_work_queue_entries * 1024) < 11719 output_port_threshold->min_grntd_tot_res_RE_WQs_cells) { 11720 return SOC_E_RESOURCE; 11721 } 11722 /* C223 = =$C$50*1024-$C$214 */ 11723 output_port_threshold->min_grntd_tot_shr_RE_WQs_cells = 11724 (_soc_kt2_mmu_params.mmu_repl_engine_work_queue_entries * 1024)- 11725 output_port_threshold->min_grntd_tot_res_RE_WQs_cells; 11726 11727 /* C224 = =C219 */ 11728 output_port_threshold->min_grntd_tot_shr_RE_WQs_queue_cells_for_int_buff = 11729 output_port_threshold->min_grntd_tot_shr_queue_cells_int_buff ; 11730 11731 /* C225 = =C220*/ 11732 if (_soc_kt2_mmu_params.extbuf_used_d_c) { 11733 output_port_threshold-> 11734 min_grntd_tot_shr_RE_WQs_queue_cells_for_ext_buff = 11735 output_port_threshold->min_grntd_tot_shr_queue_cells_ext_buff ; 11736 } else { 11737 /* C225 = =$C$95-$C$216 */ 11738 output_port_threshold-> 11739 min_grntd_tot_shr_RE_WQs_queue_cells_for_ext_buff = 11740 general_info->ema_pool - 11741 output_port_threshold-> 11742 min_grntd_tot_res_RE_WQs_queue_cells_for_ext_buff; 11743 11744 } 11745 11746 /* C226 = =C48-C217 */ 11747 output_port_threshold->min_grntd_tot_shr_EP_redirect_queue_entry_cells = 11748 _soc_kt2_mmu_params.mmu_ep_redirect_queue_entries - 11749 output_port_threshold->min_grntd_tot_res_EP_redirect_queue_entry_cells; 11750 /* C227 = 2 */ 11751 output_port_threshold->egress_queue_dynamic_threshold_parameter = 2; 11752 11753 /* C228 = =FLOOR( ($C$59*$C$219)/(1+($C$59*1)), 1) */ 11754 output_port_threshold->egress_burst_cells_size_for_one_queue = floor_func( 11755 (_soc_kt2_mmu_params.mmu_egr_queue_dyn_thd_param * 11756 output_port_threshold->min_grntd_tot_shr_queue_cells_int_buff), 11757 (1 + (_soc_kt2_mmu_params.mmu_egr_queue_dyn_thd_param*1))); 11758 11759 /* C229 = =FLOOR( ($C$59*$C$221)/(1+($C$59*1)), 1) */ 11760 output_port_threshold->egress_burst_pkts_size_for_one_queue = floor_func( 11761 (_soc_kt2_mmu_params.mmu_egr_queue_dyn_thd_param * 11762 output_port_threshold->min_grntd_tot_shr_queue_cells_EQEs), 11763 (1 + (_soc_kt2_mmu_params.mmu_egr_queue_dyn_thd_param * 1))); 11764 11765 /* C230 = =FLOOR( ($C$59*$C$219)/(1+($C$59*$C$75)), 1) */ 11766 output_port_threshold->egress_burst_cells_size_for_all_ports = floor_func( 11767 (_soc_kt2_mmu_params.mmu_egr_queue_dyn_thd_param * 11768 output_port_threshold->min_grntd_tot_shr_queue_cells_int_buff), 11769 (1 + (_soc_kt2_mmu_params.mmu_egr_queue_dyn_thd_param * 11770 general_info->total_num_of_ports))); 11771 11772 /* C231 = =FLOOR( ($C$59*$C$221)/(1+($C$59*$C$75)), 1) */ 11773 output_port_threshold->egress_burst_pkts_size_for_all_ports = floor_func( 11774 (_soc_kt2_mmu_params.mmu_egr_queue_dyn_thd_param * 11775 output_port_threshold->min_grntd_tot_shr_queue_cells_EQEs), 11776 (1 + (_soc_kt2_mmu_params.mmu_egr_queue_dyn_thd_param * 11777 general_info->total_num_of_ports))); 11778 11779 /* C232 = =FLOOR( ($C$59*$C$219)/(1+($C$59*C90)), 1) */ 11780 output_port_threshold->egress_burst_cells_size_for_all_queues = floor_func( 11781 (_soc_kt2_mmu_params.mmu_egr_queue_dyn_thd_param * 11782 output_port_threshold->min_grntd_tot_shr_queue_cells_int_buff), 11783 (1 + (_soc_kt2_mmu_params.mmu_egr_queue_dyn_thd_param * 11784 general_info->total_egr_queues_in_device))); 11785 11786 /* C233 = =FLOOR( ($C$59*$C$221)/(1+($C$59*C90)), 1) */ 11787 output_port_threshold->egress_burst_pkts_size_for_all_queues = floor_func( 11788 (_soc_kt2_mmu_params.mmu_egr_queue_dyn_thd_param * 11789 output_port_threshold->min_grntd_tot_shr_queue_cells_EQEs), 11790 (1 + (_soc_kt2_mmu_params.mmu_egr_queue_dyn_thd_param * 11791 general_info->total_egr_queues_in_device))); 11792 11793 /* C234 = =C90*$C$232 */ 11794 output_port_threshold->egress_total_use_in_cells_for_all_queues = 11795 general_info->total_egr_queues_in_device * 11796 output_port_threshold->egress_burst_cells_size_for_all_queues; 11797 11798 /* C235 = =C90*$C$233 */ 11799 output_port_threshold->egress_total_use_in_pkts_for_all_queues = 11800 general_info->total_egr_queues_in_device * 11801 output_port_threshold->egress_burst_pkts_size_for_all_queues; 11802 11803 /* C236 =$C$219-C234 */ 11804 output_port_threshold->egress_remaining_cells_for_all_queues = 11805 output_port_threshold->min_grntd_tot_shr_queue_cells_int_buff - 11806 output_port_threshold->egress_total_use_in_cells_for_all_queues; 11807 11808 /* C237 = =$C$221-C235 */ 11809 output_port_threshold->egress_remaining_pkts_for_all_queues = 11810 output_port_threshold->min_grntd_tot_shr_queue_cells_EQEs - 11811 output_port_threshold->egress_total_use_in_pkts_for_all_queues; 11812 11813 #if 0 11814 LOG_CLI((BSL_META_U(unit, 11815 "C5 %d\n"), _soc_kt2_mmu_params.mmu_min_pkt_size)); /*C5*/ 11816 LOG_CLI((BSL_META_U(unit, 11817 "C6 %d\n"), _soc_kt2_mmu_params.mmu_ethernet_mtu_bytes)); /*C6*/ 11818 LOG_CLI((BSL_META_U(unit, 11819 "C7 %d\n"), _soc_kt2_mmu_params.mmu_max_pkt_size)); /*C7*/ 11820 LOG_CLI((BSL_META_U(unit, 11821 "C8 %d\n"), _soc_kt2_mmu_params.mmu_jumbo_frame_size)); /*C8*/ 11822 LOG_CLI((BSL_META_U(unit, 11823 "C9 %d\n"), _soc_kt2_mmu_params.mmu_int_buf_cell_size)); /*C9*/ 11824 LOG_CLI((BSL_META_U(unit, 11825 "C10 %d\n"), _soc_kt2_mmu_params.mmu_ext_buf_cell_size)); /*C10=2880*/ 11826 LOG_CLI((BSL_META_U(unit, 11827 "C11 %d\n"), _soc_kt2_mmu_params.mmu_pkt_header_size)); /*C11*/ 11828 LOG_CLI((BSL_META_U(unit, 11829 "C12 %d\n"), _soc_kt2_mmu_params.packing_mode_d_c)); /* C12:Dynamic */ 11830 LOG_CLI((BSL_META_U(unit, 11831 "C13 %d\n"), _soc_kt2_mmu_params.max_pkt_size_support_packing)); /* C13:Dynamic */ 11832 LOG_CLI((BSL_META_U(unit, 11833 "C14 %d\n"), _soc_kt2_mmu_params.lossless_mode_d_c)); /* C14:Dynamic */ 11834 LOG_CLI((BSL_META_U(unit, 11835 "C15 %d\n"), _soc_kt2_mmu_params.pfc_pause_mode_d_c)); /* C15:Dynamic */ 11836 LOG_CLI((BSL_META_U(unit, 11837 "C16 %d\n"), _soc_kt2_mmu_params.mmu_lossless_pg_num)); /*C16*/ 11838 LOG_CLI((BSL_META_U(unit, 11839 "C17 %d\n"), _soc_kt2_mmu_params.extbuf_used_d_c)); /* C17:Dynamic */ 11840 LOG_CLI((BSL_META_U(unit, 11841 "C19 %d\n"), _soc_kt2_mmu_params.num_ge_ports_d)); /* C19:Dynamic */ 11842 LOG_CLI((BSL_META_U(unit, 11843 "C20 %d\n"), _soc_kt2_mmu_params.mmu_line_rate_ge)); /*C20*/ 11844 LOG_CLI((BSL_META_U(unit, 11845 "C21 %d\n"), _soc_kt2_mmu_params.num_ge_int_ports_d)); /* C21:Dynamic */ 11846 LOG_CLI((BSL_META_U(unit, 11847 "C22 %d\n"), _soc_kt2_mmu_params.num_egr_queue_per_int_ge_port_d)); /* C22:Dynamic */ 11848 LOG_CLI((BSL_META_U(unit, 11849 "C23 %d\n"), _soc_kt2_mmu_params.num_ge_ext_ports_d)); /* C23:Dynamic */ 11850 LOG_CLI((BSL_META_U(unit, 11851 "C25 %d\n"), _soc_kt2_mmu_params.num_egr_queue_per_ext_ge_port_d)); /* C24:Dynamic */ 11852 LOG_CLI((BSL_META_U(unit, 11853 "C25 %d\n"), _soc_kt2_mmu_params.num_hg_ports_d)); /* C25:Dynamic */ 11854 LOG_CLI((BSL_META_U(unit, 11855 "C26 %d\n"), _soc_kt2_mmu_params.mmu_line_rate_hg)); /*C26*/ 11856 LOG_CLI((BSL_META_U(unit, 11857 "C27 %d\n"), _soc_kt2_mmu_params.num_hg_int_ports_d)); /* C27:Dynamic */ 11858 LOG_CLI((BSL_META_U(unit, 11859 "C28 %d\n"), _soc_kt2_mmu_params.num_egr_queue_per_int_hg_port_d)); /* C28:Dynamic */ 11860 LOG_CLI((BSL_META_U(unit, 11861 "C29 %d\n"), _soc_kt2_mmu_params.num_hg_ext_ports_d)); /* C29:Dynamic */ 11862 LOG_CLI((BSL_META_U(unit, 11863 "C30 %d\n"), _soc_kt2_mmu_params.num_egr_queue_per_ext_hg_port_d)); /* C30:Dynamic */ 11864 LOG_CLI((BSL_META_U(unit, 11865 "C31 %d\n"), _soc_kt2_mmu_params.mmu_num_cpu_port)); /*C31*/ 11866 LOG_CLI((BSL_META_U(unit, 11867 "C32 %d\n"), _soc_kt2_mmu_params.mmu_num_cpu_queue)); /*C32*/ 11868 LOG_CLI((BSL_META_U(unit, 11869 "C33 %d\n"), _soc_kt2_mmu_params.cpu_port_int_ext_bounding_d_c)); /* C33:Dynamic */ 11870 LOG_CLI((BSL_META_U(unit, 11871 "C34 %d\n"), _soc_kt2_mmu_params.mmu_num_loopback_port)); /*C34*/ 11872 LOG_CLI((BSL_META_U(unit, 11873 "C35 %d\n"), _soc_kt2_mmu_params.mmu_num_loopback_queue)); /*C35*/ 11874 LOG_CLI((BSL_META_U(unit, 11875 "C36 %d\n"), _soc_kt2_mmu_params.mmu_num_ep_redirection_queue)); /*C36*/ 11876 LOG_CLI((BSL_META_U(unit, 11877 "C37 %d\n"), _soc_kt2_mmu_params.mmu_num_olp_port_d)); /*C37*/ 11878 LOG_CLI((BSL_META_U(unit, 11879 "C38 %d\n"), _soc_kt2_mmu_params.mmu_num_olp_queue)); /*C38*/ 11880 LOG_CLI((BSL_META_U(unit, 11881 "C39 %d\n"), _soc_kt2_mmu_params.olp_port_int_ext_bounding_d_c)); /* C39:Dynamic */ 11882 LOG_CLI((BSL_META_U(unit, 11883 "C41 %d\n"), _soc_kt2_mmu_params.mmu_int_buf_size)); /*C41:2048KB=2MB*/ 11884 LOG_CLI((BSL_META_U(unit, 11885 "C42 %d\n"), _soc_kt2_mmu_params.mmu_available_int_buf_size_d)); /*C42:1434KB */ 11886 LOG_CLI((BSL_META_U(unit, 11887 "C43 %d\n"), _soc_kt2_mmu_params.mmu_reserved_int_buf_cells)); /*C43:100 Cells */ 11888 LOG_CLI((BSL_META_U(unit, 11889 "C44 %d\n"), _soc_kt2_mmu_params.mmu_reserved_int_buf_ema_pool_size_d)); /*C44:614KB */ 11890 LOG_CLI((BSL_META_U(unit, 11891 "C45 %d\n"), _soc_kt2_mmu_params.internal_buffer_reduction_d_c)); /* C45:Dynamic */ 11892 LOG_CLI((BSL_META_U(unit, 11893 "C46 %d\n"), _soc_kt2_mmu_params.mmu_ext_buf_size)); /*C46:737280KB=720MB*/ 11894 LOG_CLI((BSL_META_U(unit, 11895 "C47 %d\n"), _soc_kt2_mmu_params.mmu_egress_queue_entries)); /*C47*/ 11896 LOG_CLI((BSL_META_U(unit, 11897 "C48 %d\n"), _soc_kt2_mmu_params.mmu_ep_redirect_queue_entries)); /*C48*/ 11898 LOG_CLI((BSL_META_U(unit, 11899 "C49 %d\n"), _soc_kt2_mmu_params.mmu_exp_num_of_repl_per_pkt)); /*C49*/ 11900 LOG_CLI((BSL_META_U(unit, 11901 "C50 %d\n"), _soc_kt2_mmu_params.mmu_repl_engine_work_queue_entries)); /*C50*/ 11902 LOG_CLI((BSL_META_U(unit, 11903 "C51 %d\n"), _soc_kt2_mmu_params.mmu_repl_engine_work_queue_in_device));/*C51*/ 11904 LOG_CLI((BSL_META_U(unit, 11905 "C52 %d\n"), _soc_kt2_mmu_params.mmu_ema_queues)); /*C52*/ 11906 LOG_CLI((BSL_META_U(unit, 11907 "C54 %d\n"), _soc_kt2_mmu_params.num_cells_rsrvd_ing_ext_buf)); /* C54:Dynamic */ 11908 LOG_CLI((BSL_META_U(unit, 11909 "C55 %d\n"), _soc_kt2_mmu_params.per_cos_res_cells_for_int_buff_d)); /* C55:Dynamic */ 11910 LOG_CLI((BSL_META_U(unit, 11911 "C56 %d\n"), _soc_kt2_mmu_params.per_cos_res_cells_for_ext_buff_d)); /* C56:Dynamic */ 11912 LOG_CLI((BSL_META_U(unit, 11913 "C57 %d\n"), _soc_kt2_mmu_params.mmu_ing_port_dyn_thd_param)); /*C57*/ 11914 LOG_CLI((BSL_META_U(unit, 11915 "C58 %d\n"), _soc_kt2_mmu_params.mmu_ing_pg_dyn_thd_param)); /*C58*/ 11916 LOG_CLI((BSL_META_U(unit, 11917 "C59 %d\n"), _soc_kt2_mmu_params.mmu_egr_queue_dyn_thd_param)); /*C59*/ 11918 LOG_CLI((BSL_META_U(unit, 11919 "C60 %d\n"), _soc_kt2_mmu_params.mmu_egr_pg_dyn_thd_param)); /*C60*/ 11920 LOG_CLI((BSL_META_U(unit, 11921 "C61 %d\n"), _soc_kt2_mmu_params.mmu_ing_cell_buf_reduction)); /*C61 */ 11922 LOG_CLI((BSL_META_U(unit, 11923 "C62 %d\n"), _soc_kt2_mmu_params.mmu_ing_pkt_buf_reduction)); /*C62 */ 11924 11925 LOG_CLI((BSL_META_U(unit, 11926 "C68 %d\n"), general_info->max_packet_size_in_cells)); /* C68 */ 11927 LOG_CLI((BSL_META_U(unit, 11928 "C69 %d\n"), general_info->jumbo_frame_for_int_buff)); /* C69 */ 11929 LOG_CLI((BSL_META_U(unit, 11930 "C70 %d\n"), general_info->jumbo_frame_for_ext_buff)); /* C70 */ 11931 LOG_CLI((BSL_META_U(unit, 11932 "C72 %d\n"), general_info->ether_mtu_cells_for_int_buff)); /* C72 */ 11933 LOG_CLI((BSL_META_U(unit, 11934 "C73 %d\n"), general_info->ether_mtu_cells_for_ext_buff)); /* C73 */ 11935 LOG_CLI((BSL_META_U(unit, 11936 "C75 %d\n"), general_info->total_num_of_ports)); /* C75 */ 11937 LOG_CLI((BSL_META_U(unit, 11938 "C76 %d\n"), general_info->total_num_of_ports_excl_lpbk)); /* C76 */ 11939 LOG_CLI((BSL_META_U(unit, 11940 "C77 %d\n"), general_info->total_num_of_ports_excl_lpbk_olp)); /* C77 */ 11941 LOG_CLI((BSL_META_U(unit, 11942 "C78 %d\n"), general_info->total_num_of_ports_excl_lpbk_olp_cpu)); /* C78 */ 11943 LOG_CLI((BSL_META_U(unit, 11944 "C79 %d\n"), general_info->port_bw_bound_to_ext_buff)); /* C79 */ 11945 LOG_CLI((BSL_META_U(unit, 11946 "C80 %d\n"), general_info->total_egr_queues_for_a_int_ge_ports)); /* C80 */ 11947 LOG_CLI((BSL_META_U(unit, 11948 "C81 %d\n"), general_info->total_egr_queues_for_a_ext_ge_ports)); /* C81 */ 11949 LOG_CLI((BSL_META_U(unit, 11950 "C82 %d\n"), general_info->total_egr_queues_for_a_int_hg_ports)); /* C82 */ 11951 LOG_CLI((BSL_META_U(unit, 11952 "C83 %d\n"), general_info->total_egr_queues_for_a_ext_hg_ports)); /* C83 */ 11953 LOG_CLI((BSL_META_U(unit, 11954 "C84 %d\n"), general_info->total_cpu_queues)); /* C84 */ 11955 LOG_CLI((BSL_META_U(unit, 11956 "C85 %d\n"), general_info->total_int_buff_queues)); /* C85 */ 11957 LOG_CLI((BSL_META_U(unit, 11958 "C86 %d\n"), general_info->total_ext_buff_queues)); /* C86 */ 11959 LOG_CLI((BSL_META_U(unit, 11960 "C87 %d\n"), general_info->total_ema_queues)); /* C87 */ 11961 LOG_CLI((BSL_META_U(unit, 11962 "C90 %d\n"), general_info->total_egr_queues_in_device)); /* C90 */ 11963 LOG_CLI((BSL_META_U(unit, 11964 "C91 %d\n"), general_info->max_int_cell_buff_size)); /* C91 */ 11965 LOG_CLI((BSL_META_U(unit, 11966 "C92 %d\n"), general_info->int_cell_buff_size_after_limitation)); /* C92 */ 11967 LOG_CLI((BSL_META_U(unit, 11968 "C93 %d\n"), general_info->src_packing_fifo)); /* C93 */ 11969 LOG_CLI((BSL_META_U(unit, 11970 "C94 %d\n"), general_info->int_buff_pool)); /* C94 */ 11971 LOG_CLI((BSL_META_U(unit, 11972 "C95 %d\n"), general_info->ema_pool)); /* C95 */ 11973 LOG_CLI((BSL_META_U(unit, 11974 "C96 %d\n"), general_info->max_ext_cell_buff_size)); /* C96 */ 11975 LOG_CLI((BSL_META_U(unit, 11976 "C99 %d\n"), general_info->ratio_of_ext_buff_to_int_buff_size)); /* C99 */ 11977 LOG_CLI((BSL_META_U(unit, 11978 "C100 %d\n"), general_info->int_buff_cells_per_avg_size_pkt)); /* C100 */ 11979 LOG_CLI((BSL_META_U(unit, 11980 "C101 %d\n"), general_info->ext_buff_cells_per_avg_size_pkt)); /* C101 */ 11981 LOG_CLI((BSL_META_U(unit, 11982 "C102 %d\n"), general_info->max_prop_of_buff_used_by_one_queue_port)); /* C102*/ 11983 11984 LOG_CLI((BSL_META_U(unit, 11985 "C107 %d\n"), input_port_threshold->global_hdrm_cells_for_int_buff_pool)); /* C107 */ 11986 LOG_CLI((BSL_META_U(unit, 11987 "C108 %d\n"), input_port_threshold->global_hdrm_cells_for_ext_buff_pool)); /* C108 */ 11988 LOG_CLI((BSL_META_U(unit, 11989 "C109 %d\n"), input_port_threshold->global_hdrm_cells_for_RE_WQEs)); /* C109 */ 11990 LOG_CLI((BSL_META_U(unit, 11991 "C110 %d\n"), input_port_threshold->global_hdrm_cells_for_EQEs)); /* C110 */ 11992 11993 LOG_CLI((BSL_META_U(unit, 11994 "C112 %d\n"), input_port_threshold->hdrm_int_buff_cells_for_10G_PG)); /* C112 */ 11995 LOG_CLI((BSL_META_U(unit, 11996 "C113 %d\n"), input_port_threshold->hdrm_ext_buff_cells_for_10G_PG)); /* C113 */ 11997 LOG_CLI((BSL_META_U(unit, 11998 "C114 %d\n"), input_port_threshold->hdrm_RE_WQEs_pkts_for_10G_PG)); /* C114 */ 11999 LOG_CLI((BSL_META_U(unit, 12000 "C115 %d\n"), input_port_threshold->hdrm_EQEs_pkts_for_10G_PG)); /* C115 */ 12001 12002 LOG_CLI((BSL_META_U(unit, 12003 "C117 %d\n"), input_port_threshold->hdrm_int_buff_cells_for_10G_total_PG)); /* C117 */ 12004 LOG_CLI((BSL_META_U(unit, 12005 "C118 %d\n"), input_port_threshold->hdrm_ext_buff_cells_for_10G_total_PG)); /* C118 */ 12006 LOG_CLI((BSL_META_U(unit, 12007 "C119 %d\n"), input_port_threshold->hdrm_RE_WQEs_pkts_for_10G_total_PG)); /* C119 */ 12008 LOG_CLI((BSL_META_U(unit, 12009 "C120 %d\n"), input_port_threshold->hdrm_EQEs_pkts_for_10G_total_PG)); /* C120 */ 12010 12011 LOG_CLI((BSL_META_U(unit, 12012 "C122 %d\n"), input_port_threshold->hdrm_int_buff_cells_for_1G_PG)); /* C122 */ 12013 LOG_CLI((BSL_META_U(unit, 12014 "C123 %d\n"), input_port_threshold->hdrm_ext_buff_cells_for_1G_PG)); /* C123 */ 12015 LOG_CLI((BSL_META_U(unit, 12016 "C124 %d\n"), input_port_threshold->hdrm_RE_WQEs_pkts_for_1G_PG)); /* C124 */ 12017 LOG_CLI((BSL_META_U(unit, 12018 "C125 %d\n"), input_port_threshold->hdrm_EQEs_pkts_for_1G_PG)); /* C125 */ 12019 12020 LOG_CLI((BSL_META_U(unit, 12021 "C127 %d\n"), input_port_threshold->hdrm_int_buff_cells_for_1G_total_PG)); /* C127 */ 12022 LOG_CLI((BSL_META_U(unit, 12023 "C128 %d\n"), input_port_threshold->hdrm_ext_buff_cells_for_1G_total_PG)); /* C128 */ 12024 LOG_CLI((BSL_META_U(unit, 12025 "C129 %d\n"), input_port_threshold->hdrm_RE_WQEs_pkts_for_1G_total_PG)); /* C129 */ 12026 LOG_CLI((BSL_META_U(unit, 12027 "C130 %d\n"), input_port_threshold->hdrm_EQEs_pkts_for_1G_total_PG)); /* C130 */ 12028 12029 LOG_CLI((BSL_META_U(unit, 12030 "C132 %d\n"), input_port_threshold->hdrm_int_buff_cells_for_olp_port)); /* C132 */ 12031 LOG_CLI((BSL_META_U(unit, 12032 "C133 %d\n"), input_port_threshold->hdrm_ext_buff_cells_for_olp_port)); /* C133 */ 12033 LOG_CLI((BSL_META_U(unit, 12034 "C134 %d\n"), input_port_threshold->hdrm_RE_WQEs_pkts_for_olp_port)); /* C134 */ 12035 LOG_CLI((BSL_META_U(unit, 12036 "C135 %d\n"), input_port_threshold->hdrm_EQEs_pkts_for_olp_port)); /* C135 */ 12037 12038 LOG_CLI((BSL_META_U(unit, 12039 "C137 %d\n"), input_port_threshold->hdrm_int_buff_cells_for_lpbk_port)); /* C137 */ 12040 LOG_CLI((BSL_META_U(unit, 12041 "C138 %d\n"), input_port_threshold->hdrm_ext_buff_cells_for_lpbk_port)); /* C138 */ 12042 LOG_CLI((BSL_META_U(unit, 12043 "C139 %d\n"), input_port_threshold->hdrm_RE_WQEs_pkts_for_lpbk_port)); /* C139 */ 12044 LOG_CLI((BSL_META_U(unit, 12045 "C140 %d\n"), input_port_threshold->hdrm_EQEs_pkts_for_lpbk_port)); /* C140 */ 12046 12047 LOG_CLI((BSL_META_U(unit, 12048 "C142 %d\n"), input_port_threshold->hdrm_int_buff_cells_for_cpu_port)); /* C142 */ 12049 LOG_CLI((BSL_META_U(unit, 12050 "C143 %d\n"), input_port_threshold->hdrm_ext_buff_cells_for_cpu_port)); /* C143 */ 12051 LOG_CLI((BSL_META_U(unit, 12052 "C144 %d\n"), input_port_threshold->hdrm_RE_WQEs_pkts_for_cpu_port)); /* C144 */ 12053 LOG_CLI((BSL_META_U(unit, 12054 "C145 %d\n"), input_port_threshold->hdrm_EQEs_pkts_for_cpu_port)); /* C145 */ 12055 12056 LOG_CLI((BSL_META_U(unit, 12057 "C147 %d\n"), input_port_threshold->total_hdrm_int_buff_cells)); /* C147 */ 12058 LOG_CLI((BSL_META_U(unit, 12059 "C148 %d\n"), input_port_threshold->total_hdrm_int_buff_ema_pool_cells)); /* C148 */ 12060 LOG_CLI((BSL_META_U(unit, 12061 "C149 %d\n"), input_port_threshold->total_hdrm_ext_buff_cells)); /* C149 */ 12062 LOG_CLI((BSL_META_U(unit, 12063 "C150 %d\n"), input_port_threshold->total_hdrm_RE_WQEs_pkts)); /* C150 */ 12064 LOG_CLI((BSL_META_U(unit, 12065 "C151 %d\n"), input_port_threshold->total_hdrm_EQEs_pkts)); /* C151 */ 12066 12067 LOG_CLI((BSL_META_U(unit, 12068 "C153 %d\n"), input_port_threshold->min_int_buff_cells_per_PG)); /* C153 */ 12069 LOG_CLI((BSL_META_U(unit, 12070 "C154 %d\n"), input_port_threshold->min_int_buff_ema_pool_cells_per_PG)); /* C154 */ 12071 LOG_CLI((BSL_META_U(unit, 12072 "C155 %d\n"), input_port_threshold->min_ext_buff_cells_per_PG)); /* C155 */ 12073 LOG_CLI((BSL_META_U(unit, 12074 "C156 %d\n"), input_port_threshold->min_RE_WQEs_pkt_per_PG)); /* C156 */ 12075 LOG_CLI((BSL_META_U(unit, 12076 "C157 %d\n"), input_port_threshold->min_EQEs_pkt_per_PG)); /* C157 */ 12077 12078 LOG_CLI((BSL_META_U(unit, 12079 "C159 %d\n"), input_port_threshold->min_int_buff_cells_for_total_PG)); /* C159 */ 12080 LOG_CLI((BSL_META_U(unit, 12081 "C160 %d\n"), input_port_threshold->min_int_buff_ema_pool_cells_for_total_PG)); /* C160 */ 12082 LOG_CLI((BSL_META_U(unit, 12083 "C161 %d\n"), input_port_threshold->min_ext_buff_cells_for_total_PG)); /* C161 */ 12084 LOG_CLI((BSL_META_U(unit, 12085 "C162 %d\n"), input_port_threshold->min_RE_WQEs_pkts_for_total_PG)); /* C162 */ 12086 LOG_CLI((BSL_META_U(unit, 12087 "C163 %d\n"), input_port_threshold->min_EQEs_pkts_for_total_PG)); /* C163 */ 12088 12089 LOG_CLI((BSL_META_U(unit, 12090 "C165 %d\n"), input_port_threshold->min_int_buff_cells_for_a_port)); /* C165 */ 12091 LOG_CLI((BSL_META_U(unit, 12092 "C166 %d\n"), input_port_threshold->min_int_buff_ema_pool_cells_for_a_port)); /* C166 */ 12093 LOG_CLI((BSL_META_U(unit, 12094 "C167 %d\n"), input_port_threshold->min_ext_buff_cells_for_a_port)); /* C167 */ 12095 LOG_CLI((BSL_META_U(unit, 12096 "C168 %d\n"), input_port_threshold->min_RE_WQEs_pkts_for_a_port)); /* C168 */ 12097 LOG_CLI((BSL_META_U(unit, 12098 "C169 %d\n"), input_port_threshold->min_EQEs_pkts_for_a_port)); /* C169 */ 12099 12100 LOG_CLI((BSL_META_U(unit, 12101 "C171 %d\n"), input_port_threshold->min_int_buff_cells_for_total_port)); /* C171 */ 12102 LOG_CLI((BSL_META_U(unit, 12103 "C172 %d\n"), input_port_threshold->min_int_buff_ema_pool_cells_for_total_port)); /* C172 */ 12104 LOG_CLI((BSL_META_U(unit, 12105 "C173 %d\n"), input_port_threshold->min_ext_buff_cells_for_total_port)); /* C173 */ 12106 LOG_CLI((BSL_META_U(unit, 12107 "C174 %d\n"), input_port_threshold->min_RE_WQEs_pkts_for_total_port)); /* C174 */ 12108 LOG_CLI((BSL_META_U(unit, 12109 "C175 %d\n"), input_port_threshold->min_EQEs_pkts_for_total_port)); /* C175 */ 12110 12111 LOG_CLI((BSL_META_U(unit, 12112 "C177 %d\n"), input_port_threshold->total_min_int_buff_cells)); /* C177 */ 12113 LOG_CLI((BSL_META_U(unit, 12114 "C178 %d\n"), input_port_threshold->total_min_int_buff_ema_pool_cells)); /* C178 */ 12115 LOG_CLI((BSL_META_U(unit, 12116 "C179 %d\n"), input_port_threshold->total_min_ext_buff_cells)); /* C179 */ 12117 LOG_CLI((BSL_META_U(unit, 12118 "C180 %d\n"), input_port_threshold->total_min_RE_WQEs_pkts)); /* C180 */ 12119 LOG_CLI((BSL_META_U(unit, 12120 "C181 %d\n"), input_port_threshold->total_min_EQEs_pkts)); /* C181 */ 12121 12122 LOG_CLI((BSL_META_U(unit, 12123 "C183 %d\n"), input_port_threshold->total_shared_ing_buff_pool)); /* C183 */ 12124 LOG_CLI((BSL_META_U(unit, 12125 "C184 %d\n"), input_port_threshold->total_shared_EMA_buff)); /* C184 */ 12126 LOG_CLI((BSL_META_U(unit, 12127 "C185 %d\n"), input_port_threshold->total_shared_ext_buff)); /* C185 */ 12128 LOG_CLI((BSL_META_U(unit, 12129 "C186 %d\n"), input_port_threshold->total_shared_RE_WQEs_buff)); /* C186 */ 12130 LOG_CLI((BSL_META_U(unit, 12131 "C187 %d\n"), input_port_threshold->total_shared_EQEs_buff)); /* C187 */ 12132 12133 LOG_CLI((BSL_META_U(unit, 12134 "C189 %d\n"), input_port_threshold->ingress_burst_cells_size_for_one_port)); /* C189 */ 12135 LOG_CLI((BSL_META_U(unit, 12136 "C190 %d\n"), input_port_threshold->ingress_burst_pkts_size_for_one_port)); /* C190 */ 12137 LOG_CLI((BSL_META_U(unit, 12138 "C191 %d\n"), input_port_threshold->ingress_burst_cells_size_for_all_ports)); /* C191 */ 12139 LOG_CLI((BSL_META_U(unit, 12140 "C192 %d\n"), input_port_threshold->ingress_total_shared_cells_use_for_all_port)); /* C192 */ 12141 LOG_CLI((BSL_META_U(unit, 12142 "C193 %d\n"), input_port_threshold->ingress_burst_pkts_size_for_all_port)); /* C193 */ 12143 LOG_CLI((BSL_META_U(unit, 12144 "C194 %d\n"), input_port_threshold->ingress_total_shared_pkts_use_for_all_port)); /* C194 */ 12145 LOG_CLI((BSL_META_U(unit, 12146 "C195 %d\n"), input_port_threshold->ingress_total_shared_hdrm_cells_use_for_all_port)); /* C195 */ 12147 LOG_CLI((BSL_META_U(unit, 12148 "C196 %d\n"), input_port_threshold->ingress_total_shared_hdrm_pkts_use_for_all_port)); /* C196 */ 12149 12150 LOG_CLI((BSL_META_U(unit, 12151 "C201 %d\n"), output_port_threshold->min_grntd_res_queue_cells_int_buff)); /* C201 */ 12152 LOG_CLI((BSL_META_U(unit, 12153 "C202 %d\n"), output_port_threshold->min_grntd_res_queue_cells_ext_buff)); /* C202 */ 12154 LOG_CLI((BSL_META_U(unit, 12155 "C203 %d\n"), output_port_threshold->min_grntd_res_queue_cells_EQEs)); /* C203 */ 12156 LOG_CLI((BSL_META_U(unit, 12157 "C204 %d\n"), output_port_threshold->min_grntd_res_EMA_queue_cells)); /* C204 */ 12158 LOG_CLI((BSL_META_U(unit, 12159 "C205 %d\n"), output_port_threshold->min_grntd_res_RE_WQs_cells)); /* C205 */ 12160 LOG_CLI((BSL_META_U(unit, 12161 "C206 %d\n"), output_port_threshold->min_grntd_res_RE_WQs_queue_cells_for_int_buff)); /* C206 */ 12162 LOG_CLI((BSL_META_U(unit, 12163 "C207 %d\n"), output_port_threshold->min_grntd_res_RE_WQs_queue_cells_for_ext_buff)); /* C207 */ 12164 LOG_CLI((BSL_META_U(unit, 12165 "C208 %d\n"), output_port_threshold->min_grntd_res_EP_redirect_queue_entry_cells)); /* C208 */ 12166 12167 LOG_CLI((BSL_META_U(unit, 12168 "C210 %d\n"), output_port_threshold->min_grntd_tot_res_queue_cells_int_buff)); /* C210 */ 12169 LOG_CLI((BSL_META_U(unit, 12170 "C211 %d\n"), output_port_threshold->min_grntd_tot_res_queue_cells_ext_buff)); /* C211 */ 12171 LOG_CLI((BSL_META_U(unit, 12172 "C212 %d\n"), output_port_threshold->min_grntd_tot_res_queue_cells_EQEs)); /* C212 */ 12173 LOG_CLI((BSL_META_U(unit, 12174 "C213 %d\n"), output_port_threshold->min_grntd_tot_res_EMA_queue_cells)); /* C213 */ 12175 LOG_CLI((BSL_META_U(unit, 12176 "C214 %d\n"), output_port_threshold->min_grntd_tot_res_RE_WQs_cells)); /* C214 */ 12177 LOG_CLI((BSL_META_U(unit, 12178 "C215 %d\n"), output_port_threshold->min_grntd_tot_res_RE_WQs_queue_cells_for_int_buff));/* C215 */ 12179 LOG_CLI((BSL_META_U(unit, 12180 "C216 %d\n"), output_port_threshold->min_grntd_tot_res_RE_WQs_queue_cells_for_ext_buff));/* C216 */ 12181 LOG_CLI((BSL_META_U(unit, 12182 "C217 %d\n"), output_port_threshold->min_grntd_tot_res_EP_redirect_queue_entry_cells)); /* C217 */ 12183 12184 LOG_CLI((BSL_META_U(unit, 12185 "C219 %d\n"), output_port_threshold->min_grntd_tot_shr_queue_cells_int_buff)); /* C219 */ 12186 LOG_CLI((BSL_META_U(unit, 12187 "C220 %d\n"), output_port_threshold->min_grntd_tot_shr_queue_cells_ext_buff)); /* C220 */ 12188 LOG_CLI((BSL_META_U(unit, 12189 "C221 %d\n"), output_port_threshold->min_grntd_tot_shr_queue_cells_EQEs)); /* C221 */ 12190 LOG_CLI((BSL_META_U(unit, 12191 "C222 %d\n"), output_port_threshold->min_grntd_tot_shr_EMA_queue_cells)); /* C222 */ 12192 LOG_CLI((BSL_META_U(unit, 12193 "C223 %d\n"), output_port_threshold->min_grntd_tot_shr_RE_WQs_cells)); /* C223 */ 12194 LOG_CLI((BSL_META_U(unit, 12195 "C224 %d\n"), output_port_threshold->min_grntd_tot_shr_RE_WQs_queue_cells_for_int_buff));/* C224 */ 12196 LOG_CLI((BSL_META_U(unit, 12197 "C225 %d\n"), output_port_threshold->min_grntd_tot_shr_RE_WQs_queue_cells_for_ext_buff));/* C225 */ 12198 LOG_CLI((BSL_META_U(unit, 12199 "C226 %d\n"), output_port_threshold->min_grntd_tot_shr_EP_redirect_queue_entry_cells)); /* C226 */ 12200 12201 LOG_CLI((BSL_META_U(unit, 12202 "C227 %d\n"), output_port_threshold->egress_queue_dynamic_threshold_parameter)); /* C227 */ 12203 LOG_CLI((BSL_META_U(unit, 12204 "C228 %d\n"), output_port_threshold->egress_burst_cells_size_for_one_queue)); /* C228 */ 12205 LOG_CLI((BSL_META_U(unit, 12206 "C229 %d\n"), output_port_threshold->egress_burst_pkts_size_for_one_queue)); /* C229 */ 12207 LOG_CLI((BSL_META_U(unit, 12208 "C230 %d\n"), output_port_threshold->egress_burst_cells_size_for_all_ports)); /* C230 */ 12209 LOG_CLI((BSL_META_U(unit, 12210 "C231 %d\n"), output_port_threshold->egress_burst_pkts_size_for_all_ports)); /* C231 */ 12211 LOG_CLI((BSL_META_U(unit, 12212 "C232 %d\n"), output_port_threshold->egress_burst_cells_size_for_all_queues)); /* C232 */ 12213 LOG_CLI((BSL_META_U(unit, 12214 "C233 %d\n"), output_port_threshold->egress_burst_pkts_size_for_all_queues)); /* C233 */ 12215 LOG_CLI((BSL_META_U(unit, 12216 "C234 %d\n"), output_port_threshold->egress_total_use_in_cells_for_all_queues)); /* C234 */ 12217 LOG_CLI((BSL_META_U(unit, 12218 "C235 %d\n"), output_port_threshold->egress_total_use_in_pkts_for_all_queues)); /* C235 */ 12219 LOG_CLI((BSL_META_U(unit, 12220 "C236 %d\n"), output_port_threshold->egress_remaining_cells_for_all_queues)); /* C236 */ 12221 LOG_CLI((BSL_META_U(unit, 12222 "C237 %d\n"), output_port_threshold->egress_remaining_pkts_for_all_queues)); /* C237 */ 12223 #endif 12224 12225 if(flex_port == -1) { 12226 /* ===================== */ 12227 /* Device Wide Registers */ 12228 /* ===================== */ 12229 12230 /* C241: CFAPIFULLSETPOINT.CFAPIFULLSETPOINT = =C92 */ 12231 SOC_IF_ERROR_RETURN(READ_CFAPIFULLSETPOINTr(unit, &rval)); 12232 soc_reg_field_set(unit, CFAPIFULLSETPOINTr, &rval, CFAPIFULLSETPOINTf, 12233 general_info->int_cell_buff_size_after_limitation); 12234 SOC_IF_ERROR_RETURN(WRITE_CFAPIFULLSETPOINTr(unit, rval)); 12235 12236 /* C242: CFAPIFULLRESETPOINT.CFAPIFULLRESETPOINT = =C241-C69*2 */ 12237 SOC_IF_ERROR_RETURN(READ_CFAPIFULLRESETPOINTr(unit, &rval)); 12238 soc_reg_field_set(unit, CFAPIFULLRESETPOINTr, &rval, CFAPIFULLRESETPOINTf, 12239 general_info->int_cell_buff_size_after_limitation - 12240 (2* general_info->jumbo_frame_for_int_buff)); 12241 SOC_IF_ERROR_RETURN(WRITE_CFAPIFULLRESETPOINTr(unit, rval)); 12242 12243 assert(_soc_kt2_mmu_params.mmu_ext_buf_cell_size == 2880 || 12244 _soc_kt2_mmu_params.mmu_ext_buf_cell_size == 768); 12245 12246 /* C243: MISCCONFIG.BUFFER_SIZE based on external cell size */ 12247 SOC_IF_ERROR_RETURN(READ_MISCCONFIGr(unit, &rval)); 12248 soc_reg_field_set(unit, MISCCONFIGr, &rval, BUFFER_SIZEf, 12249 _soc_kt2_mmu_params.mmu_ext_buf_cell_size == 2880 ? 1 : 0); 12250 SOC_IF_ERROR_RETURN(WRITE_MISCCONFIGr(unit, rval)); 12251 12252 if (_soc_kt2_mmu_params.packing_mode_d_c) { 12253 /* C243: MISCCONFIG.BUFFER_SIZE = 0x01 */ 12254 SOC_IF_ERROR_RETURN(READ_MISCCONFIGr(unit, &rval)); 12255 soc_reg_field_set(unit, MISCCONFIGr, &rval, BUFFER_SIZEf, 1); 12256 SOC_IF_ERROR_RETURN(WRITE_MISCCONFIGr(unit, rval)); 12257 12258 /* C244: TOP_SW_BOND_OVRD_CTRL1.MMU_PACKING_ENABLE = 0x01 */ 12259 SOC_IF_ERROR_RETURN(READ_TOP_SW_BOND_OVRD_CTRL1r(unit, &rval)); 12260 soc_reg_field_set(unit, TOP_SW_BOND_OVRD_CTRL1r, &rval, MMU_PACKING_ENABLEf, 1); 12261 SOC_IF_ERROR_RETURN(WRITE_TOP_SW_BOND_OVRD_CTRL1r(unit, rval)); 12262 12263 /* C245: MMU_ENQ_PACKING_REAS_FIFO_PROFILE_THRESH.THRESH_PROFILE_[0..3] = 0x0A */ 12264 SOC_IF_ERROR_RETURN(READ_MMU_ENQ_PACKING_REAS_FIFO_PROFILE_THRESHr(unit, &rval)); 12265 soc_reg_field_set(unit, MMU_ENQ_PACKING_REAS_FIFO_PROFILE_THRESHr, &rval, THRESH_PROFILE_0f, 0x0a); 12266 soc_reg_field_set(unit, MMU_ENQ_PACKING_REAS_FIFO_PROFILE_THRESHr, &rval, THRESH_PROFILE_1f, 0x0a); 12267 soc_reg_field_set(unit, MMU_ENQ_PACKING_REAS_FIFO_PROFILE_THRESHr, &rval, THRESH_PROFILE_2f, 0x0a); 12268 soc_reg_field_set(unit, MMU_ENQ_PACKING_REAS_FIFO_PROFILE_THRESHr, &rval, THRESH_PROFILE_3f, 0x0a); 12269 SOC_IF_ERROR_RETURN(WRITE_MMU_ENQ_PACKING_REAS_FIFO_PROFILE_THRESHr(unit, rval)); 12270 12271 /* C246: MMU_ENQ_PACKING_REAS_FIFO_THRESH_PROFILE_[0/1/2].SRCPORT_[0..41] = 0 */ 12272 rval = 0; 12273 SOC_IF_ERROR_RETURN(WRITE_MMU_ENQ_PACKING_REAS_FIFO_THRESH_PROFILE_0r(unit, rval)); 12274 SOC_IF_ERROR_RETURN(WRITE_MMU_ENQ_PACKING_REAS_FIFO_THRESH_PROFILE_1r(unit, rval)); 12275 SOC_IF_ERROR_RETURN(WRITE_MMU_ENQ_PACKING_REAS_FIFO_THRESH_PROFILE_2r(unit, rval)); 12276 12277 /* C247: THDO_MISCCONFIG.UCMC_SEPARATION = 0 */ 12278 SOC_IF_ERROR_RETURN(READ_THDO_MISCCONFIGr(unit, &rval)); 12279 soc_reg_field_set(unit, THDO_MISCCONFIGr, &rval, UCMC_SEPARATIONf, 0); 12280 SOC_IF_ERROR_RETURN(WRITE_THDO_MISCCONFIGr(unit, rval)); 12281 12282 /* C248: WRED_MISCCONFIG.UCMC_SEPARATION = 0 */ 12283 SOC_IF_ERROR_RETURN(READ_WRED_MISCCONFIGr(unit, &rval)); 12284 soc_reg_field_set(unit, WRED_MISCCONFIGr, &rval, UCMC_SEPARATIONf, 0); 12285 SOC_IF_ERROR_RETURN(WRITE_WRED_MISCCONFIGr(unit, rval)); 12286 12287 /* C249: MISCCONFIG.THDI_ROLLOVER_COUNT = 0xB4 */ 12288 SOC_IF_ERROR_RETURN(READ_MISCCONFIGr(unit, &rval)); 12289 soc_reg_field_set(unit, MISCCONFIGr, &rval, THDI_ROLLOVER_COUNTf, 0xb4); 12290 SOC_IF_ERROR_RETURN(WRITE_MISCCONFIGr(unit, rval)); 12291 } 12292 12293 /* Input port thresholds */ 12294 /* C251: COLOR_AWARE.ENABLE = 0 */ 12295 SOC_IF_ERROR_RETURN(READ_COLOR_AWAREr (unit, &rval)); 12296 soc_reg_field_set(unit, COLOR_AWAREr, &rval, ENABLEf, 0); 12297 SOC_IF_ERROR_RETURN(WRITE_COLOR_AWAREr (unit, rval)); 12298 12299 12300 /* Internal Buffer Ingress Pool */ 12301 /* C253: GLOBAL_HDRM_LIMIT.GLOBAL_HDRM_LIMIT = =$C$107 */ 12302 12303 SOC_IF_ERROR_RETURN(READ_GLOBAL_HDRM_LIMITr (unit, &rval)); 12304 soc_reg_field_set(unit, GLOBAL_HDRM_LIMITr, &rval, GLOBAL_HDRM_LIMITf, 12305 input_port_threshold->global_hdrm_cells_for_int_buff_pool); 12306 SOC_IF_ERROR_RETURN(WRITE_GLOBAL_HDRM_LIMITr (unit, rval)); 12307 12308 /* C254: BUFFER_CELL_LIMIT_SP.LIMIT = =$C$183 */ 12309 SOC_IF_ERROR_RETURN(READ_BUFFER_CELL_LIMIT_SPr (unit, service_pool, &rval)); 12310 soc_reg_field_set(unit, BUFFER_CELL_LIMIT_SPr, &rval, LIMITf, 12311 input_port_threshold->total_shared_ing_buff_pool); 12312 SOC_IF_ERROR_RETURN(WRITE_BUFFER_CELL_LIMIT_SPr (unit, service_pool, rval)); 12313 12314 /* C255: CELL_RESET_LIMIT_OFFSET_SP.OFFSET = CEILING(C75/4*C71, 1) */ 12315 SOC_IF_ERROR_RETURN(READ_CELL_RESET_LIMIT_OFFSET_SPr (unit, 12316 service_pool, &rval)); 12317 temp_val = ceil_func(general_info->total_num_of_ports,4) * 12318 general_info->ether_mtu_cells_for_int_buff; 12319 soc_reg_field_set(unit, CELL_RESET_LIMIT_OFFSET_SPr, &rval, 12320 OFFSETf, temp_val); 12321 SOC_IF_ERROR_RETURN(WRITE_CELL_RESET_LIMIT_OFFSET_SPr (unit, 12322 service_pool, rval)); 12323 12324 /* External Buffer */ 12325 if ((ext_mem_port_count) || (_soc_kt2_mmu_params.packing_mode_d_c)) { 12326 /* C257: THDIEXT_GLOBAL_HDRM_LIMIT.GLOBAL_HDRM_LIMIT = =C108 */ 12327 SOC_IF_ERROR_RETURN(READ_THDIEXT_GLOBAL_HDRM_LIMITr (unit, &rval)); 12328 soc_reg_field_set(unit, THDIEXT_GLOBAL_HDRM_LIMITr, &rval, 12329 GLOBAL_HDRM_LIMITf, 12330 input_port_threshold->global_hdrm_cells_for_ext_buff_pool); 12331 SOC_IF_ERROR_RETURN(WRITE_THDIEXT_GLOBAL_HDRM_LIMITr (unit, rval)); 12332 12333 /* C258: THDIEXT_BUFFER_CELL_LIMIT_SP.LIMIT =C185*/ 12334 SOC_IF_ERROR_RETURN(READ_THDIEXT_BUFFER_CELL_LIMIT_SPr ( 12335 unit, service_pool, &rval)); 12336 soc_reg_field_set(unit, THDIEXT_BUFFER_CELL_LIMIT_SPr, &rval, LIMITf, 12337 input_port_threshold->total_shared_ext_buff); 12338 SOC_IF_ERROR_RETURN(WRITE_THDIEXT_BUFFER_CELL_LIMIT_SPr (unit, 0,rval)); 12339 12340 /* C259:THDIEXT_CELL_RESET_LIMIT_OFFSET_SP.OFFSET=CEILING(C75/4*C73,1)*/ 12341 SOC_IF_ERROR_RETURN(READ_THDIEXT_CELL_RESET_LIMIT_OFFSET_SPr ( 12342 unit, service_pool, &rval)); 12343 temp_val = (general_info->total_num_of_ports * 12344 general_info->ether_mtu_cells_for_ext_buff) / 4; 12345 if (general_info->total_num_of_ports % 4) { 12346 temp_val++; 12347 } 12348 soc_reg_field_set(unit, 12349 THDIEXT_CELL_RESET_LIMIT_OFFSET_SPr, &rval, OFFSETf, temp_val); 12350 SOC_IF_ERROR_RETURN(WRITE_THDIEXT_CELL_RESET_LIMIT_OFFSET_SPr ( 12351 unit, service_pool, rval)); 12352 12353 12354 /* EMA pool */ 12355 /* C261: THDIEMA_GLOBAL_HDRM_LIMIT.GLOBAL_HDRM_LIMIT==C107 */ 12356 SOC_IF_ERROR_RETURN(READ_THDIEMA_GLOBAL_HDRM_LIMITr (unit, &rval)); 12357 soc_reg_field_set(unit, THDIEMA_GLOBAL_HDRM_LIMITr, &rval, 12358 GLOBAL_HDRM_LIMITf, 12359 input_port_threshold->global_hdrm_cells_for_int_buff_pool); 12360 SOC_IF_ERROR_RETURN(WRITE_THDIEMA_GLOBAL_HDRM_LIMITr (unit, rval)); 12361 12362 /* C262: THDIEMA_BUFFER_CELL_LIMIT_SP.LIMIT = =C184 */ 12363 SOC_IF_ERROR_RETURN(READ_THDIEMA_BUFFER_CELL_LIMIT_SPr ( 12364 unit, service_pool, &rval)); 12365 soc_reg_field_set(unit, THDIEMA_BUFFER_CELL_LIMIT_SPr, &rval, LIMITf, 12366 input_port_threshold->total_shared_EMA_buff); 12367 SOC_IF_ERROR_RETURN(WRITE_THDIEMA_BUFFER_CELL_LIMIT_SPr (unit, 0,rval)); 12368 12369 /* C263:THDIEMA_CELL_RESET_LIMIT_OFFSET_SP.OFFSET=CEILING(C75/4*C72,1)*/ 12370 SOC_IF_ERROR_RETURN(READ_THDIEMA_CELL_RESET_LIMIT_OFFSET_SPr ( 12371 unit, service_pool, &rval)); 12372 temp_val = ceil_func(general_info->total_num_of_ports,4) * 12373 general_info->ether_mtu_cells_for_int_buff ; 12374 soc_reg_field_set( 12375 unit, THDIEMA_CELL_RESET_LIMIT_OFFSET_SPr, &rval, OFFSETf, 12376 temp_val); 12377 SOC_IF_ERROR_RETURN(WRITE_THDIEMA_CELL_RESET_LIMIT_OFFSET_SPr ( 12378 unit, service_pool, rval)); 12379 } 12380 12381 /* RE WQEs */ 12382 /* C265: THDIRQE_GLOBAL_HDRM_LIMIT.GLOBAL_HDRM_LIMIT = C109 */ 12383 SOC_IF_ERROR_RETURN(READ_THDIRQE_GLOBAL_HDRM_LIMITr (unit, &rval)); 12384 soc_reg_field_set(unit, THDIRQE_GLOBAL_HDRM_LIMITr, &rval, 12385 GLOBAL_HDRM_LIMITf, 12386 input_port_threshold->global_hdrm_cells_for_RE_WQEs); 12387 SOC_IF_ERROR_RETURN(WRITE_THDIRQE_GLOBAL_HDRM_LIMITr (unit, rval)); 12388 12389 /* C266: THDIRQE_BUFFER_CELL_LIMIT_SP.LIMIT =$C$186 */ 12390 SOC_IF_ERROR_RETURN(READ_THDIRQE_BUFFER_CELL_LIMIT_SPr ( 12391 unit, service_pool, &rval)); 12392 soc_reg_field_set(unit, THDIRQE_BUFFER_CELL_LIMIT_SPr, &rval, LIMITf, 12393 input_port_threshold->total_shared_RE_WQEs_buff); 12394 SOC_IF_ERROR_RETURN(WRITE_THDIRQE_BUFFER_CELL_LIMIT_SPr ( 12395 unit, service_pool, rval)); 12396 12397 /* C267: = THDIRQE_CELL_RESET_LIMIT_OFFSET_SP.OFFSET = CEILING(C75/4, 1) */ 12398 SOC_IF_ERROR_RETURN(READ_THDIRQE_CELL_RESET_LIMIT_OFFSET_SPr( 12399 unit,service_pool,&rval)); 12400 soc_reg_field_set(unit, THDIRQE_CELL_RESET_LIMIT_OFFSET_SPr, &rval, 12401 OFFSETf, ceil_func(general_info->total_num_of_ports , 4)); 12402 SOC_IF_ERROR_RETURN(WRITE_THDIRQE_CELL_RESET_LIMIT_OFFSET_SPr( 12403 unit,service_pool,rval)); 12404 12405 /* EQEs */ 12406 /* C269: THDIQEN_GLOBAL_HDRM_LIMIT.GLOBAL_HDRM_LIMIT = C110 */ 12407 SOC_IF_ERROR_RETURN(READ_THDIQEN_GLOBAL_HDRM_LIMITr (unit, &rval)); 12408 soc_reg_field_set(unit, THDIQEN_GLOBAL_HDRM_LIMITr, &rval, 12409 GLOBAL_HDRM_LIMITf, 12410 input_port_threshold->global_hdrm_cells_for_EQEs); 12411 SOC_IF_ERROR_RETURN(WRITE_THDIQEN_GLOBAL_HDRM_LIMITr (unit, rval)); 12412 12413 /* C270: THDIQEN_BUFFER_CELL_LIMIT_SP.LIMIT =$C$187 */ 12414 SOC_IF_ERROR_RETURN(READ_THDIQEN_BUFFER_CELL_LIMIT_SPr ( 12415 unit, service_pool, &rval)); 12416 soc_reg_field_set(unit, THDIQEN_BUFFER_CELL_LIMIT_SPr, &rval, LIMITf, 12417 input_port_threshold->total_shared_EQEs_buff); 12418 SOC_IF_ERROR_RETURN(WRITE_THDIQEN_BUFFER_CELL_LIMIT_SPr ( 12419 unit, service_pool, rval)); 12420 12421 /* C271: THDIQEN_CELL_RESET_LIMIT_OFFSET_SP.OFFSET= CEILING(C75/4*C49, 1)*/ 12422 SOC_IF_ERROR_RETURN(READ_THDIQEN_CELL_RESET_LIMIT_OFFSET_SPr( 12423 unit,service_pool,&rval)); 12424 temp_val = ceil_func(general_info->total_num_of_ports, 4) * 12425 _soc_kt2_mmu_params.mmu_exp_num_of_repl_per_pkt; 12426 soc_reg_field_set(unit, THDIQEN_CELL_RESET_LIMIT_OFFSET_SPr, &rval, OFFSETf, 12427 temp_val); 12428 SOC_IF_ERROR_RETURN(WRITE_THDIQEN_CELL_RESET_LIMIT_OFFSET_SPr( 12429 unit,service_pool,rval)); 12430 12431 /* Ouput port thresholds */ 12432 /* Internal buffer Egress pool */ 12433 /* C274: OP_BUFFER_SHARED_LIMIT_CELLI.OP_BUFFER_SHARED_LIMIT_CELLI = C219 */ 12434 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_SHARED_LIMIT_CELLIr (unit, &rval)); 12435 soc_reg_field_set(unit, OP_BUFFER_SHARED_LIMIT_CELLIr, &rval, 12436 OP_BUFFER_SHARED_LIMIT_CELLIf, 12437 output_port_threshold->min_grntd_tot_shr_queue_cells_int_buff); 12438 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_SHARED_LIMIT_CELLIr (unit, rval)); 12439 op_buffer_shared_limit_celli = output_port_threshold-> 12440 min_grntd_tot_shr_queue_cells_int_buff; 12441 12442 /* C275: OP_BUFFER_SHARED_LIMIT_RESUME_CELLI. 12443 OP_BUFFER_SHARED_LIMIT_RESUME_CELLI */ 12444 temp_val = op_buffer_shared_limit_celli; 12445 if ((ext_mem_port_count) || (_soc_kt2_mmu_params.packing_mode_d_c)) { 12446 /* C275 = =C274-CEILING(C75/4,1)*C72 */ 12447 temp_val = temp_val - (ceil_func(general_info->total_num_of_ports,4) 12448 * general_info->ether_mtu_cells_for_int_buff); 12449 } else { 12450 if (_soc_kt2_mmu_params.lossless_mode_d_c == 0) { 12451 /* C275 = =C274-CEILING(C78/4, 1)*C72 */ 12452 temp_val = temp_val - 12453 (ceil_func(general_info-> 12454 total_num_of_ports_excl_lpbk_olp_cpu,4) 12455 * general_info->ether_mtu_cells_for_int_buff); 12456 } else { 12457 /* C275 = =C274-CEILING(C76/4, 1)*C72 */ 12458 temp_val = temp_val - 12459 (ceil_func(general_info->total_num_of_ports_excl_lpbk,4) 12460 * general_info->ether_mtu_cells_for_int_buff); 12461 } 12462 } 12463 12464 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_SHARED_LIMIT_RESUME_CELLIr(unit, &rval)); 12465 soc_reg_field_set(unit, OP_BUFFER_SHARED_LIMIT_RESUME_CELLIr, &rval, 12466 OP_BUFFER_SHARED_LIMIT_RESUME_CELLIf, temp_val); 12467 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_SHARED_LIMIT_RESUME_CELLIr(unit, rval)); 12468 op_buffer_shared_limit_resume_celli = temp_val; 12469 12470 /* C276: OP_BUFFER_LIMIT_YELLOW_CELLI.OP_BUFFER_LIMIT_YELLOW_CELLI = 12471 =CEILING(C274/8, 1) */ 12472 /* C278: OP_BUFFER_LIMIT_RED_CELLI.OP_BUFFER_LIMIT_RED_CELLI = 12473 =CEILING(C274/8, 1) */ 12474 temp_val = op_buffer_shared_limit_celli; 12475 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_LIMIT_YELLOW_CELLIr (unit, &rval)); 12476 soc_reg_field_set(unit, OP_BUFFER_LIMIT_YELLOW_CELLIr, &rval, 12477 OP_BUFFER_LIMIT_YELLOW_CELLIf, ceil_func(temp_val,8)); 12478 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_YELLOW_CELLIr (unit, rval)); 12479 12480 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_LIMIT_RED_CELLIr (unit, &rval)); 12481 soc_reg_field_set(unit, OP_BUFFER_LIMIT_RED_CELLIr, &rval, 12482 OP_BUFFER_LIMIT_RED_CELLIf, ceil_func( temp_val,8)); 12483 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_RED_CELLIr (unit, rval)); 12484 12485 12486 /* C277: OP_BUFFER_LIMIT_RESUME_YELLOW_CELLI. 12487 OP_BUFFER_LIMIT_RESUME_YELLOW_CELLI =CEILING(C275/8, 1) */ 12488 /* C279: OP_BUFFER_LIMIT_RESUME_RED_CELLI. 12489 OP_BUFFER_LIMIT_RESUME_RED_CELLI =CEILING(C275/8, 1) */ 12490 temp_val = op_buffer_shared_limit_resume_celli; 12491 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_LIMIT_RESUME_YELLOW_CELLIr ( 12492 unit, &rval)); 12493 soc_reg_field_set(unit, OP_BUFFER_LIMIT_RESUME_YELLOW_CELLIr, &rval, 12494 OP_BUFFER_LIMIT_RESUME_YELLOW_CELLIf, ceil_func(temp_val,8)); 12495 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_RESUME_YELLOW_CELLIr ( 12496 unit, rval)); 12497 12498 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_LIMIT_RESUME_RED_CELLIr (unit, &rval)); 12499 soc_reg_field_set(unit, OP_BUFFER_LIMIT_RESUME_RED_CELLIr, &rval, 12500 OP_BUFFER_LIMIT_RESUME_RED_CELLIf, ceil_func(temp_val,8)); 12501 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_RESUME_RED_CELLIr (unit, rval)); 12502 12503 /* External Buffer */ 12504 if ((ext_mem_port_count) || (_soc_kt2_mmu_params.packing_mode_d_c)) { 12505 /* C281: 12506 OP_BUFFER_SHARED_LIMIT_CELLE.OP_BUFFER_SHARED_LIMIT_CELLE = C220 */ 12507 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_SHARED_LIMIT_CELLE_POOL0r ( 12508 unit, &rval)); 12509 soc_reg_field_set(unit, OP_BUFFER_SHARED_LIMIT_CELLE_POOL0r, &rval, 12510 OP_BUFFER_SHARED_LIMIT_CELLEf, 12511 output_port_threshold->min_grntd_tot_shr_queue_cells_ext_buff); 12512 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_SHARED_LIMIT_CELLE_POOL0r ( 12513 unit, rval)); 12514 op_buffer_shared_limit_celle = output_port_threshold-> 12515 min_grntd_tot_shr_queue_cells_ext_buff; 12516 12517 /* C282: OP_BUFFER_SHARED_LIMIT_RESUME_CELLE. 12518 OP_BUFFER_SHARED_LIMIT_RESUME_CELLE =C281-CEILING(C75/4, 1)*C73 */ 12519 temp_val = op_buffer_shared_limit_celle - 12520 (ceil_func(general_info->total_num_of_ports ,4) * 12521 general_info->ether_mtu_cells_for_ext_buff); 12522 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_SHARED_LIMIT_RESUME_CELLE_POOL0r( 12523 unit, &rval)); 12524 soc_reg_field_set(unit, OP_BUFFER_SHARED_LIMIT_RESUME_CELLE_POOL0r, 12525 &rval,OP_BUFFER_SHARED_LIMIT_RESUME_CELLEf, temp_val); 12526 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_SHARED_LIMIT_RESUME_CELLE_POOL0r( 12527 unit, rval)); 12528 op_buffer_shared_limit_resume_celle = temp_val; 12529 12530 /* C283: OP_BUFFER_LIMIT_YELLOW_CELLE.OP_BUFFER_LIMIT_YELLOW_CELLE = 12531 =CEILING(C281/8, 1) */ 12532 /* C285: OP_BUFFER_LIMIT_RED_CELLE.OP_BUFFER_LIMIT_RED_CELLE = 12533 =CEILING(C281/8, 1) */ 12534 temp_val = op_buffer_shared_limit_celle; 12535 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_LIMIT_YELLOW_CELLE_POOL0r ( 12536 unit, &rval)); 12537 soc_reg_field_set(unit, OP_BUFFER_LIMIT_YELLOW_CELLE_POOL0r, &rval, 12538 OP_BUFFER_LIMIT_YELLOW_CELLEf, ceil_func(temp_val,8)); 12539 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_YELLOW_CELLE_POOL0r ( 12540 unit, rval)); 12541 12542 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_LIMIT_RED_CELLE_POOL0r(unit, &rval)); 12543 soc_reg_field_set(unit, OP_BUFFER_LIMIT_RED_CELLE_POOL0r, &rval, 12544 OP_BUFFER_LIMIT_RED_CELLEf, ceil_func( temp_val,8)); 12545 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_RED_CELLE_POOL0r(unit, rval)); 12546 12547 12548 /* C284: OP_BUFFER_LIMIT_RESUME_YELLOW_CELLE. 12549 OP_BUFFER_LIMIT_RESUME_YELLOW_CELLE ==CEILING(C282/8, 1) */ 12550 /* C286: OP_BUFFER_LIMIT_RESUME_RED_CELLE. 12551 OP_BUFFER_LIMIT_RESUME_RED_CELLE ==CEILING(C282/8, 1) */ 12552 temp_val = op_buffer_shared_limit_resume_celle; 12553 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_LIMIT_RESUME_YELLOW_CELLE_POOL0r ( 12554 unit, &rval)); 12555 soc_reg_field_set(unit, 12556 OP_BUFFER_LIMIT_RESUME_YELLOW_CELLE_POOL0r, &rval, 12557 OP_BUFFER_LIMIT_RESUME_YELLOW_CELLEf, ceil_func(temp_val,8)); 12558 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_RESUME_YELLOW_CELLE_POOL0r ( 12559 unit, rval)); 12560 12561 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_LIMIT_RESUME_RED_CELLE_POOL0r ( 12562 unit, &rval)); 12563 soc_reg_field_set(unit, OP_BUFFER_LIMIT_RESUME_RED_CELLE_POOL0r, &rval, 12564 OP_BUFFER_LIMIT_RESUME_RED_CELLEf, ceil_func(temp_val,8)); 12565 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_RESUME_RED_CELLE_POOL0r ( 12566 unit, rval)); 12567 12568 /* EMA pool */ 12569 /* C288: 12570 OP_BUFFER_SHARED_LIMIT_THDOEMA.OP_BUFFER_SHARED_LIMIT_CELLE = C222 */ 12571 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_SHARED_LIMIT_THDOEMAr (unit, &rval)); 12572 soc_reg_field_set(unit, OP_BUFFER_SHARED_LIMIT_THDOEMAr, &rval, 12573 OP_BUFFER_SHARED_LIMITf, 12574 output_port_threshold->min_grntd_tot_shr_EMA_queue_cells); 12575 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_SHARED_LIMIT_THDOEMAr (unit, rval)); 12576 op_buffer_shared_limit = output_port_threshold-> 12577 min_grntd_tot_shr_EMA_queue_cells; 12578 12579 /* C289: OP_BUFFER_SHARED_LIMIT_RESUME_THDOEMA. 12580 OP_BUFFER_SHARED_LIMIT_RESUME_CELLE = C288-CEILING(C75/4,1)*C72 */ 12581 temp_val = op_buffer_shared_limit; 12582 temp_val = temp_val - (ceil_func(general_info->total_num_of_ports,4) * 12583 general_info->ether_mtu_cells_for_int_buff); 12584 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_SHARED_LIMIT_RESUME_THDOEMAr( 12585 unit, &rval)); 12586 soc_reg_field_set(unit, OP_BUFFER_SHARED_LIMIT_RESUME_THDOEMAr, &rval, 12587 OP_BUFFER_SHARED_LIMIT_RESUMEf, temp_val); 12588 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_SHARED_LIMIT_RESUME_THDOEMAr( 12589 unit, rval)); 12590 op_buffer_shared_limit_resume = temp_val; 12591 12592 /* C290: OP_BUFFER_LIMIT_YELLOW_THDOEMA.OP_BUFFER_LIMIT_YELLOW = 12593 =CEILING(C288/8, 1) */ 12594 /* C292: OP_BUFFER_LIMIT_RED_THDOEMA.OP_BUFFER_LIMIT_RED = 12595 =CEILING(C288/8, 1) */ 12596 temp_val = op_buffer_shared_limit; 12597 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_LIMIT_YELLOW_THDOEMAr (unit, &rval)); 12598 soc_reg_field_set(unit, OP_BUFFER_LIMIT_YELLOW_THDOEMAr, &rval, 12599 OP_BUFFER_LIMIT_YELLOWf, ceil_func(temp_val,8)); 12600 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_YELLOW_THDOEMAr (unit, rval)); 12601 12602 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_LIMIT_RED_THDOEMAr (unit, &rval)); 12603 soc_reg_field_set(unit, OP_BUFFER_LIMIT_RED_THDOEMAr, &rval, 12604 OP_BUFFER_LIMIT_REDf, ceil_func( temp_val,8)); 12605 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_RED_THDOEMAr (unit, rval)); 12606 12607 12608 /* C291: OP_BUFFER_LIMIT_RESUME_YELLOW_THDOEMA. 12609 OP_BUFFER_LIMIT_RESUME_YELLOW==CEILING(C289/8, 1) */ 12610 /* C293: OP_BUFFER_LIMIT_RESUME_RED_THDOEMA. 12611 OP_BUFFER_LIMIT_RESUME_RED==CEILING(C289/8, 1) */ 12612 temp_val = op_buffer_shared_limit_resume; 12613 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_LIMIT_RESUME_YELLOW_THDOEMAr ( 12614 unit, &rval)); 12615 soc_reg_field_set(unit, OP_BUFFER_LIMIT_RESUME_YELLOW_THDOEMAr, &rval, 12616 OP_BUFFER_LIMIT_RESUME_YELLOWf, ceil_func(temp_val,8)); 12617 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_RESUME_YELLOW_THDOEMAr ( 12618 unit, rval)); 12619 12620 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_LIMIT_RESUME_RED_THDOEMAr ( 12621 unit, &rval)); 12622 soc_reg_field_set(unit, OP_BUFFER_LIMIT_RESUME_RED_THDOEMAr, &rval, 12623 OP_BUFFER_LIMIT_RESUME_REDf, ceil_func(temp_val,8)); 12624 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_RESUME_RED_THDOEMAr ( 12625 unit, rval)); 12626 } 12627 /* RE WQEs*/ 12628 /* C295: 12629 OP_BUFFER_SHARED_LIMIT_THDORQEQ.OP_BUFFER_SHARED_LIMIT_CELLE = C223 */ 12630 12631 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_SHARED_LIMIT_THDORQEQr (unit, &rval)); 12632 SOC_FIND_FIELD(OP_BUFFER_SHARED_LIMITf, 12633 SOC_REG_INFO(unit, OP_BUFFER_SHARED_LIMIT_THDORQEQr).fields, 12634 SOC_REG_INFO(unit, OP_BUFFER_SHARED_LIMIT_THDORQEQr).nFields, 12635 fieldp); 12636 temp_val = output_port_threshold->min_grntd_tot_shr_RE_WQs_cells; 12637 if (temp_val >= (1 << fieldp->len)) { 12638 temp_val = (1 << fieldp->len) - 1; 12639 } 12640 soc_reg_field_set(unit, OP_BUFFER_SHARED_LIMIT_THDORQEQr, &rval, 12641 OP_BUFFER_SHARED_LIMITf, temp_val); 12642 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_SHARED_LIMIT_THDORQEQr (unit, rval)); 12643 op_buffer_shared_limit = temp_val; 12644 12645 /* C296: OP_BUFFER_SHARED_LIMIT_RESUME_THDORQEQ. 12646 OP_BUFFER_SHARED_LIMIT_RESUME = CEILING(C223-C75/4, 1) */ 12647 temp_val = output_port_threshold->min_grntd_tot_shr_RE_WQs_cells; 12648 if ((ext_mem_port_count) || (_soc_kt2_mmu_params.packing_mode_d_c)) { 12649 /* =C223-CEILING(C75/4, 1) */ 12650 temp_val -= ceil_func(general_info->total_num_of_ports,4); 12651 } else { 12652 if (_soc_kt2_mmu_params.lossless_mode_d_c) { 12653 /* =C223-CEILING(C76/4, 1) */ 12654 temp_val -= ceil_func(general_info->total_num_of_ports_excl_lpbk,4); 12655 } else { 12656 /* =C223-CEILING(C78/4, 1) */ 12657 temp_val -= ceil_func( 12658 general_info->total_num_of_ports_excl_lpbk_olp_cpu,4); 12659 } 12660 } 12661 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_SHARED_LIMIT_RESUME_THDORQEQr( 12662 unit, &rval)); 12663 soc_reg_field_set(unit, OP_BUFFER_SHARED_LIMIT_RESUME_THDORQEQr, &rval, 12664 OP_BUFFER_SHARED_LIMIT_RESUMEf, temp_val); 12665 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_SHARED_LIMIT_RESUME_THDORQEQr( 12666 unit, rval)); 12667 op_buffer_shared_limit_resume = temp_val; 12668 12669 /* C297: OP_BUFFER_LIMIT_YELLOW_THDORQEQ.OP_BUFFER_LIMIT_YELLOW = 12670 =CEILING(C295/8, 1)-1 */ 12671 temp_val = ceil_func(op_buffer_shared_limit,8) ; 12672 if (_soc_kt2_mmu_params.lossless_mode_d_c) { 12673 temp_val -= 1; 12674 } 12675 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_LIMIT_YELLOW_THDORQEQr (unit, &rval)); 12676 soc_reg_field_set(unit, OP_BUFFER_LIMIT_YELLOW_THDORQEQr, &rval, 12677 OP_BUFFER_LIMIT_YELLOWf, temp_val); 12678 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_YELLOW_THDORQEQr (unit, rval)); 12679 12680 /* C298: OP_BUFFER_LIMIT_RESUME_YELLOW_THDORQEQ. 12681 OP_BUFFER_LIMIT_RESUME_YELLOW = C297-1 */ 12682 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_LIMIT_RESUME_YELLOW_THDORQEQr ( 12683 unit, &rval)); 12684 soc_reg_field_set(unit, OP_BUFFER_LIMIT_RESUME_YELLOW_THDORQEQr, &rval, 12685 OP_BUFFER_LIMIT_RESUME_YELLOWf, temp_val-1); 12686 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_RESUME_YELLOW_THDORQEQr ( 12687 unit, rval)); 12688 12689 /* C299: OP_BUFFER_LIMIT_RED_THDORQEQ.OP_BUFFER_LIMIT_RED = 12690 =CEILING(C295/8, 1) */ 12691 temp_val = ceil_func(op_buffer_shared_limit,8); 12692 if (_soc_kt2_mmu_params.lossless_mode_d_c) { 12693 temp_val -= 1; 12694 } 12695 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_LIMIT_RED_THDORQEQr (unit, &rval)); 12696 soc_reg_field_set(unit, OP_BUFFER_LIMIT_RED_THDORQEQr, &rval, 12697 OP_BUFFER_LIMIT_REDf, temp_val); 12698 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_RED_THDORQEQr (unit, rval)); 12699 12700 12701 /* C300: OP_BUFFER_LIMIT_RESUME_RED_THDORQEQ. 12702 OP_BUFFER_LIMIT_RESUME_RED==C299 -1 */ 12703 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_LIMIT_RESUME_RED_THDORQEQr ( 12704 unit, &rval)); 12705 soc_reg_field_set(unit, OP_BUFFER_LIMIT_RESUME_RED_THDORQEQr, &rval, 12706 OP_BUFFER_LIMIT_RESUME_REDf, temp_val-1); 12707 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_RESUME_RED_THDORQEQr ( 12708 unit, rval)); 12709 12710 /* EQEs */ 12711 /* C302: OP_BUFFER_SHARED_LIMIT_QENTRY.OP_BUFFER_SHARED_LIMIT_QENTRY =C221*/ 12712 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_SHARED_LIMIT_QENTRYr (unit, &rval)); 12713 soc_reg_field_set(unit, OP_BUFFER_SHARED_LIMIT_QENTRYr, &rval, 12714 OP_BUFFER_SHARED_LIMIT_QENTRYf, 12715 output_port_threshold->min_grntd_tot_shr_queue_cells_EQEs); 12716 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_SHARED_LIMIT_QENTRYr (unit, rval)); 12717 12718 temp_val = output_port_threshold->min_grntd_tot_shr_queue_cells_EQEs; 12719 12720 /* C304: OP_BUFFER_LIMIT_YELLOW_QENTRY.OP_BUFFER_LIMIT_YELLOW_QENTRY 12721 = CEILING(C302/8, 1) */ 12722 /* C306: OP_BUFFER_LIMIT_RED_QENTRY.OP_BUFFER_LIMIT_RED_QENTRY 12723 = CEILING(C302/8, 1) */ 12724 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_LIMIT_RED_QENTRYr(unit, &rval)); 12725 soc_reg_field_set(unit, OP_BUFFER_LIMIT_RED_QENTRYr, &rval, 12726 OP_BUFFER_LIMIT_RED_QENTRYf, ceil_func(temp_val,8)); 12727 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_RED_QENTRYr(unit, rval)); 12728 12729 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_LIMIT_YELLOW_QENTRYr(unit, &rval)); 12730 soc_reg_field_set(unit, OP_BUFFER_LIMIT_YELLOW_QENTRYr, &rval, 12731 OP_BUFFER_LIMIT_YELLOW_QENTRYf, ceil_func(temp_val,8)); 12732 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_YELLOW_QENTRYr(unit, rval)); 12733 /* C303: OP_BUFFER_SHARED_LIMIT_RESUME_QENTRY = 12734 =C221-CEILING(C78/4, 1)*C49 12735 =C221-CEILING(C76/4, 1)*C49 12736 =C221-CEILING(C75/4, 1)*C49 */ 12737 temp_val= output_port_threshold->min_grntd_tot_shr_queue_cells_EQEs; 12738 if ((ext_mem_port_count) || (_soc_kt2_mmu_params.packing_mode_d_c)) { 12739 /* C303 =C221-CEILING(C75/4, 1)*C49 */ 12740 temp_val = temp_val - (ceil_func(general_info->total_num_of_ports,4) * 12741 _soc_kt2_mmu_params.mmu_exp_num_of_repl_per_pkt); 12742 } else { 12743 if (_soc_kt2_mmu_params.lossless_mode_d_c) { 12744 /* =C221-CEILING(C76/4, 1)*C49 */ 12745 temp_val = temp_val - 12746 (ceil_func( 12747 general_info->total_num_of_ports_excl_lpbk,4) * 12748 _soc_kt2_mmu_params.mmu_exp_num_of_repl_per_pkt); 12749 } else { 12750 /* =C221-CEILING(C78/4, 1)*C49 */ 12751 temp_val = temp_val - 12752 (ceil_func( 12753 general_info->total_num_of_ports_excl_lpbk_olp_cpu,4) * 12754 _soc_kt2_mmu_params.mmu_exp_num_of_repl_per_pkt); 12755 } 12756 } 12757 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_SHARED_LIMIT_RESUME_QENTRYr( 12758 unit, &rval)); 12759 soc_reg_field_set(unit, OP_BUFFER_SHARED_LIMIT_RESUME_QENTRYr, 12760 &rval, 12761 OP_BUFFER_SHARED_LIMIT_RESUME_QENTRYf, temp_val); 12762 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_SHARED_LIMIT_RESUME_QENTRYr( 12763 unit, rval)); 12764 12765 /* C305: OP_BUFFER_LIMIT_RESUME_YELLOW_QENTRY. 12766 OP_BUFFER_LIMIT_RESUME_YELLOW_QENTRY = =CEILING(C303/8, 1) */ 12767 /* C307: OP_BUFFER_LIMIT_RESUME_RED_QENTRY. 12768 OP_BUFFER_LIMIT_RESUME_RED_QENTRY = =CEILING(C303/8, 1) */ 12769 SOC_IF_ERROR_RETURN( 12770 READ_OP_BUFFER_LIMIT_RESUME_YELLOW_QENTRYr(unit, &rval)); 12771 soc_reg_field_set(unit, OP_BUFFER_LIMIT_RESUME_YELLOW_QENTRYr, &rval, 12772 OP_BUFFER_LIMIT_RESUME_YELLOW_QENTRYf, 12773 ceil_func(temp_val,8)); 12774 SOC_IF_ERROR_RETURN( 12775 WRITE_OP_BUFFER_LIMIT_RESUME_YELLOW_QENTRYr(unit, rval)); 12776 12777 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_LIMIT_RESUME_RED_QENTRYr(unit, &rval)); 12778 soc_reg_field_set(unit, OP_BUFFER_LIMIT_RESUME_RED_QENTRYr, &rval, 12779 OP_BUFFER_LIMIT_RESUME_RED_QENTRYf, 12780 ceil_func(temp_val,8)); 12781 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_RESUME_RED_QENTRYr(unit, rval)); 12782 12783 /* EP Redirection Packets */ 12784 /* C309 : OP_BUFFER_SHARED_LIMIT_THDORDEQ.OP_BUFFER_SHARED_LIMIT = C226 */ 12785 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_SHARED_LIMIT_THDORDEQr(unit, &rval)); 12786 soc_reg_field_set(unit,OP_BUFFER_SHARED_LIMIT_THDORDEQr,&rval, 12787 OP_BUFFER_SHARED_LIMITf, 12788 output_port_threshold->min_grntd_tot_shr_EP_redirect_queue_entry_cells); 12789 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_SHARED_LIMIT_THDORDEQr(unit, rval)); 12790 op_buffer_shared_limit= output_port_threshold-> 12791 min_grntd_tot_shr_EP_redirect_queue_entry_cells; 12792 12793 /* C311: OP_BUFFER_LIMIT_YELLOW_THDORDEQ.OP_BUFFER_LIMIT_YELLOW 12794 = CEILING(C309/8, 1) */ 12795 /* C313: OP_BUFFER_LIMIT_RED_THDORDEQ.OP_BUFFER_LIMIT_RED 12796 = CEILING(C309/8, 1) */ 12797 temp_val = ceil_func(op_buffer_shared_limit,8); 12798 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_LIMIT_YELLOW_THDORDEQr(unit, &rval)); 12799 soc_reg_field_set(unit,OP_BUFFER_LIMIT_YELLOW_THDORDEQr,&rval, 12800 OP_BUFFER_LIMIT_YELLOWf, temp_val); 12801 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_YELLOW_THDORDEQr(unit, rval)); 12802 12803 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_LIMIT_RED_THDORDEQr(unit, &rval)); 12804 soc_reg_field_set(unit,OP_BUFFER_LIMIT_RED_THDORDEQr,&rval, 12805 OP_BUFFER_LIMIT_REDf, temp_val); 12806 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_RED_THDORDEQr(unit, rval)); 12807 12808 /* C312: OP_BUFFER_LIMIT_RESUME_YELLOW_THDORDEQ. 12809 OP_BUFFER_LIMIT_RESUME_YELLOW = =C311-1 */ 12810 /* C314: OP_BUFFER_LIMIT_RESUME_RED_THDORDEQ. 12811 OP_BUFFER_LIMIT_RESUME_RED = =C313-1 */ 12812 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_LIMIT_RESUME_YELLOW_THDORDEQr( 12813 unit, &rval)); 12814 soc_reg_field_set(unit,OP_BUFFER_LIMIT_RESUME_YELLOW_THDORDEQr,&rval, 12815 OP_BUFFER_LIMIT_RESUME_YELLOWf, temp_val-1); 12816 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_RESUME_YELLOW_THDORDEQr( 12817 unit, rval)); 12818 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_LIMIT_RESUME_RED_THDORDEQr(unit, &rval)); 12819 soc_reg_field_set(unit,OP_BUFFER_LIMIT_RESUME_RED_THDORDEQr,&rval, 12820 OP_BUFFER_LIMIT_RESUME_REDf, temp_val-1); 12821 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_RESUME_RED_THDORDEQr(unit, rval)); 12822 12823 /*C310: OP_BUFFER_SHARED_LIMIT_TRESUME_THDORDEQr. 12824 OP_BUFFER_SHARED_LIMIT_RESUMEf = =C226-4 */ 12825 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_SHARED_LIMIT_RESUME_THDORDEQr( 12826 unit, &rval)); 12827 soc_reg_field_set(unit,OP_BUFFER_SHARED_LIMIT_RESUME_THDORDEQr,&rval, 12828 OP_BUFFER_SHARED_LIMIT_RESUMEf, 12829 output_port_threshold-> 12830 min_grntd_tot_shr_EP_redirect_queue_entry_cells - 4); 12831 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_SHARED_LIMIT_RESUME_THDORDEQr( 12832 unit, rval)); 12833 /* C312: OP_BUFFER_LIMIT_RESUME_YELLOW_THDORDEQ. 12834 OP_BUFFER_LIMIT_RESUME_YELLOW = =C302-1 */ 12835 /* C314: OP_BUFFER_LIMIT_RESUME_RED_THDORDEQ. 12836 OP_BUFFER_LIMIT_RESUME_RED = =C302-1 */ 12837 12838 } 12839 12840 /* Per Port Registers */ 12841 /* ######################## */ 12842 /* 1. Input Port Thresholds */ 12843 /* ######################## */ 12844 12845 /* 1.1 Internal Buffer Ingress Pool */ 12846 /* Assuming only service_pool = 0 is used */ 12847 /* Assuming only priority_group = 0 is used on single PG ports */ 12848 /* Assuming only priority_group = 7 is used on eight PG ports */ 12849 SOC_PBMP_ITER (valid_port_cpu_pbmp, port) { 12850 if (((port > KT2_CMIC_PORT) && (port < KT2_LPBK_PORT) && 12851 (((*kt2_port_to_mxqblock_subports[unit])[port-1] == 0) || 12852 (port == 30) || (port == 33) || 12853 (port == 36) || (port == 39))) || (IS_LB_PORT(unit,port))) { 12854 priority_group = 7; 12855 } else { 12856 priority_group = 0; 12857 } 12858 if( (flex_port != -1) && (flex_port != port) ) { 12859 continue; 12860 } 12861 sal_memset(&thdi_port_sp_config,0,sizeof(thdi_port_sp_config)); 12862 mem_idx= (port * KT2_MAX_SERVICE_POOLS) + service_pool; 12863 /* C320 : THDI_PORT_SP_CONFIG.PORT_SP_MIN_LIMIT = =$C$165 */ 12864 soc_mem_field32_set(unit, THDI_PORT_SP_CONFIGm, 12865 &thdi_port_sp_config, PORT_SP_MIN_LIMITf, 12866 input_port_threshold->min_int_buff_cells_for_a_port); 12867 /* C321 : THDI_PORT_SP_CONFIG.PORT_SP_MAX_LIMIT = =$C$254 <==C183 */ 12868 soc_mem_field32_set(unit, THDI_PORT_SP_CONFIGm, 12869 &thdi_port_sp_config, PORT_SP_MAX_LIMITf, 12870 input_port_threshold->total_shared_ing_buff_pool); 12871 /* C322 : PORT_MAX_PKT_SIZE.PORT_MAX_PKT_SIZE = =$C$68 */ 12872 SOC_IF_ERROR_RETURN(READ_PORT_MAX_PKT_SIZEr (unit, port, &rval)); 12873 soc_reg_field_set(unit, PORT_MAX_PKT_SIZEr, &rval, 12874 PORT_MAX_PKT_SIZEf, 12875 general_info->max_packet_size_in_cells); 12876 SOC_IF_ERROR_RETURN(WRITE_PORT_MAX_PKT_SIZEr (unit, port, rval)); 12877 12878 /* C323: THDI_PORT_SP_CONFIG.PORT_SP_RESUME_LIMIT = =$C$321-2*C72 */ 12879 soc_mem_field32_set(unit, THDI_PORT_SP_CONFIGm, 12880 &thdi_port_sp_config, PORT_SP_RESUME_LIMITf, 12881 input_port_threshold->total_shared_ing_buff_pool - 12882 (2 * general_info->ether_mtu_cells_for_int_buff)); 12883 12884 SOC_IF_ERROR_RETURN (soc_mem_write( 12885 unit, THDI_PORT_SP_CONFIGm, MEM_BLOCK_ALL, 12886 mem_idx, &thdi_port_sp_config)); 12887 12888 sal_memset(&thdi_port_pg_config,0,sizeof(thdi_port_pg_config)); 12889 mem_idx= (port * KT2_MAX_PRIORITY_GROUPS) + priority_group; 12890 /* C324: THDI_PORT_PG_CONFIG.PG_MIN_LIMIT (PG0) = =$C$153 */ 12891 soc_mem_field32_set(unit, THDI_PORT_PG_CONFIGm, 12892 &thdi_port_pg_config, PG_MIN_LIMITf, 12893 input_port_threshold->min_int_buff_cells_per_PG); 12894 12895 /* C325: THDI_PORT_PG_CONFIG.PG_SHARED_LIMIT=IF($C$14, $C$58, $C$254)*/ 12896 if (_soc_kt2_mmu_params.lossless_mode_d_c) { 12897 temp_val = _soc_kt2_mmu_params.mmu_ing_pg_dyn_thd_param; 12898 } else { 12899 /* $C$254 = =$C$183 */ 12900 temp_val = input_port_threshold->total_shared_ing_buff_pool; 12901 } 12902 soc_mem_field32_set(unit, THDI_PORT_PG_CONFIGm, 12903 &thdi_port_pg_config, PG_SHARED_LIMITf, temp_val); 12904 12905 /* C326: THDI_PORT_PG_CONFIG.PG_RESET_OFFSET = 2*$C$72 */ 12906 soc_mem_field32_set(unit, THDI_PORT_PG_CONFIGm, 12907 &thdi_port_pg_config, PG_RESET_OFFSETf, 12908 (2 * general_info->ether_mtu_cells_for_int_buff)); 12909 12910 /* C327: THDI_PORT_PG_CONFIG.PG_RESET_FLOOR = 0 */ 12911 soc_mem_field32_set(unit, THDI_PORT_PG_CONFIGm, 12912 &thdi_port_pg_config, PG_RESET_FLOORf, 0); 12913 12914 /* C328: THDI_PORT_PG_CONFIG.PG_SHARED_DYNAMIC= =IF($C$14, 1, 0) */ 12915 if (_soc_kt2_mmu_params.lossless_mode_d_c) { 12916 temp_val = 1; 12917 } else { 12918 temp_val = 0; 12919 } 12920 soc_mem_field32_set(unit, THDI_PORT_PG_CONFIGm, 12921 &thdi_port_pg_config, PG_SHARED_DYNAMICf,temp_val); 12922 12923 /* C329: THDI_PORT_PG_CONFIG.PG_HDRM_LIMIT= 12924 For Ge:$C122 For Hg:$C112 For Cpu:$C142 */ 12925 if (IS_CPU_PORT(unit, port)) { 12926 temp_val = input_port_threshold->hdrm_int_buff_cells_for_cpu_port; 12927 } else if (IS_GE_PORT(unit, port) || IS_LB_PORT(unit,port)) { 12928 temp_val = input_port_threshold->hdrm_int_buff_cells_for_1G_PG; 12929 } else if (IS_HG_PORT(unit, port) || IS_XE_PORT(unit,port) ) { 12930 temp_val = input_port_threshold->hdrm_int_buff_cells_for_10G_PG; 12931 } 12932 soc_mem_field32_set(unit, THDI_PORT_PG_CONFIGm, 12933 &thdi_port_pg_config, PG_HDRM_LIMITf,temp_val); 12934 12935 /* C330 : THDI_PORT_PG_CONFIG.PG_GBL_HDRM_EN = for lossy=1 else 0 */ 12936 if (_soc_kt2_mmu_params.lossless_mode_d_c) { 12937 temp_val = 0; 12938 } else { 12939 temp_val = 1; 12940 } 12941 soc_mem_field32_set(unit, THDI_PORT_PG_CONFIGm, 12942 &thdi_port_pg_config, PG_GBL_HDRM_ENf ,temp_val); 12943 12944 /* C331: THDI_PORT_PG_CONFIG.SP_SHARED_MAX_ENABLE = 12945 For Ge:1 For Hg,Cpu: Ge Value only!!! */ 12946 12947 soc_mem_field32_set(unit, THDI_PORT_PG_CONFIGm, 12948 &thdi_port_pg_config, SP_SHARED_MAX_ENABLEf ,1); 12949 12950 /* C332: THDI_PORT_PG_CONFIG.SP_MIN_PG_ENABLE = 12951 For Ge:1 For Hg,Cpu: Ge Value only!!! */ 12952 soc_mem_field32_set(unit, THDI_PORT_PG_CONFIGm, 12953 &thdi_port_pg_config, SP_MIN_PG_ENABLEf ,1); 12954 12955 SOC_IF_ERROR_RETURN (soc_mem_write( 12956 unit, THDI_PORT_PG_CONFIGm, MEM_BLOCK_ALL, 12957 mem_idx, &thdi_port_pg_config)); 12958 } 12959 12960 /* 1.2 External Buffer */ 12961 /* Assuming only service_pool = 0 is used */ 12962 /* Assuming only priority_group = 0 is used on single PG ports */ 12963 /* Assuming only priority_group = 7 is used on eight PG ports */ 12964 SOC_PBMP_ITER (valid_port_cpu_pbmp, port) { 12965 if ((ext_mem_port_count) || (_soc_kt2_mmu_params.packing_mode_d_c)) { 12966 if (((port > KT2_CMIC_PORT) && (port < KT2_LPBK_PORT) && 12967 (((*kt2_port_to_mxqblock_subports[unit])[port-1] == 0) || 12968 (port == 30) || (port == 33) || 12969 (port == 36) || (port == 39))) || (IS_LB_PORT(unit,port))) { 12970 priority_group = 7; 12971 } else { 12972 priority_group = 0; 12973 } 12974 if( (flex_port != -1) && (flex_port != port) ) { 12975 continue; 12976 } 12977 sal_memset(&thdiext_thdi_port_sp_config,0, 12978 sizeof(thdiext_thdi_port_sp_config)); 12979 mem_idx= (port * KT2_MAX_SERVICE_POOLS) + service_pool; 12980 /* C335: THDIEXT_THDI_PORT_SP_CONFIG.PORT_SP_MIN_LIMIT = $C$167 */ 12981 soc_mem_field32_set(unit, THDIEXT_THDI_PORT_SP_CONFIGm, 12982 &thdiext_thdi_port_sp_config, PORT_SP_MIN_LIMITf, 12983 input_port_threshold->min_ext_buff_cells_for_a_port); 12984 12985 /* C336: THDIEXT_THDI_PORT_SP_CONFIG.PORT_SP_MAX_LIMIT = 12986 $C$258 <== =C185 */ 12987 soc_mem_field32_set(unit, THDIEXT_THDI_PORT_SP_CONFIGm, 12988 &thdiext_thdi_port_sp_config, PORT_SP_MAX_LIMITf, 12989 input_port_threshold->total_shared_ext_buff); 12990 12991 /* C337: THDIEXT_PORT_MAX_PKT_SIZE.PORT_MAX_PKT_SIZE = =$C$70 */ 12992 SOC_IF_ERROR_RETURN(READ_THDIEXT_PORT_MAX_PKT_SIZEr ( 12993 unit, port, &rval)); 12994 soc_reg_field_set(unit, THDIEXT_PORT_MAX_PKT_SIZEr, &rval, 12995 PORT_MAX_PKT_SIZEf, 12996 general_info->jumbo_frame_for_ext_buff); 12997 SOC_IF_ERROR_RETURN(WRITE_THDIEXT_PORT_MAX_PKT_SIZEr ( 12998 unit, port, rval)); 12999 /* C338: THDIEXT_THDI_PORT_SP_CONFIG.PORT_SP_RESUME_LIMIT = 13000 =$C$336-2*$C$73 */ 13001 soc_mem_field32_set(unit, THDIEXT_THDI_PORT_SP_CONFIGm, 13002 &thdiext_thdi_port_sp_config, PORT_SP_RESUME_LIMITf, 13003 input_port_threshold->total_shared_ext_buff - 13004 (2 * general_info->ether_mtu_cells_for_ext_buff)); 13005 SOC_IF_ERROR_RETURN (soc_mem_write(unit, 13006 THDIEXT_THDI_PORT_SP_CONFIGm, MEM_BLOCK_ALL, 13007 mem_idx, &thdiext_thdi_port_sp_config)); 13008 } 13009 sal_memset(&thdiext_thdi_port_pg_config,0, 13010 sizeof(thdiext_thdi_port_pg_config)); 13011 mem_idx= (port * KT2_MAX_PRIORITY_GROUPS) + priority_group; 13012 if ((ext_mem_port_count) || (_soc_kt2_mmu_params.packing_mode_d_c)) { 13013 /* C339: THDIEXT_THDI_PORT_PG_CONFIG.PG_MIN_LIMIT(PG0) = =$C$155 */ 13014 soc_mem_field32_set(unit, THDIEXT_THDI_PORT_PG_CONFIGm, 13015 &thdiext_thdi_port_pg_config, PG_MIN_LIMITf, 13016 input_port_threshold->min_ext_buff_cells_per_PG); 13017 13018 13019 /* C340: THDIEXT_THDI_PORT_PG_CONFIG.PG_SHARED_LIMIT = 13020 IF($C$14, $C$58, $C$258) */ 13021 if (_soc_kt2_mmu_params.lossless_mode_d_c) { 13022 temp_val = _soc_kt2_mmu_params.mmu_ing_pg_dyn_thd_param; 13023 } else { 13024 /* $C$258 = =$C$185 */ 13025 temp_val = input_port_threshold->total_shared_ext_buff;; 13026 } 13027 soc_mem_field32_set(unit, THDIEXT_THDI_PORT_PG_CONFIGm, 13028 &thdiext_thdi_port_pg_config, 13029 PG_SHARED_LIMITf, temp_val); 13030 13031 /* C341: THDIEXT_THDI_PORT_PG_CONFIG.PG_RESET_OFFSET = =2*$C$72 */ 13032 soc_mem_field32_set(unit, THDIEXT_THDI_PORT_PG_CONFIGm, 13033 &thdiext_thdi_port_pg_config, PG_RESET_OFFSETf, 13034 (2 * general_info->ether_mtu_cells_for_ext_buff)); 13035 13036 /* C342: THDI_PORT_PG_CONFIG.PG_RESET_FLOOR = 0 */ 13037 soc_mem_field32_set(unit, THDIEXT_THDI_PORT_PG_CONFIGm, 13038 &thdiext_thdi_port_pg_config, PG_RESET_FLOORf, 0); 13039 13040 /* C343: THDIEXT_THDI_PORT_PG_CONFIG.PG_SHARED_DYNAMIC= 13041 IF($C$14, 1, 0) */ 13042 if (_soc_kt2_mmu_params.lossless_mode_d_c) { 13043 temp_val = 1; 13044 } else { 13045 temp_val = 0; 13046 } 13047 soc_mem_field32_set(unit, THDIEXT_THDI_PORT_PG_CONFIGm, 13048 &thdiext_thdi_port_pg_config, PG_SHARED_DYNAMICf, 13049 temp_val); 13050 13051 /* C344: THDIEXT_THDI_PORT_PG_CONFIG.PG_HDRM_LIMIT 13052 For Ge:$C123 For Hg:$C113 For Cpu:$C143 */ 13053 if (IS_CPU_PORT(unit, port)) { 13054 temp_val = input_port_threshold-> 13055 hdrm_ext_buff_cells_for_cpu_port; 13056 } else if (IS_GE_PORT(unit, port) || IS_LB_PORT(unit,port)) { 13057 temp_val = input_port_threshold->hdrm_ext_buff_cells_for_1G_PG; 13058 } else if (IS_HG_PORT(unit, port) || IS_XE_PORT(unit, port)) { 13059 temp_val= input_port_threshold->hdrm_ext_buff_cells_for_10G_PG; 13060 } 13061 soc_mem_field32_set(unit, THDIEXT_THDI_PORT_PG_CONFIGm, 13062 &thdiext_thdi_port_pg_config, PG_HDRM_LIMITf,temp_val); 13063 13064 /* C345: THDIEXT_THDI_PORT_PG_CONFIG.PG_GBL_HDRM_EN = 13065 for lossy=1 else 0 13066 For Packed : 0 */ 13067 if (_soc_kt2_mmu_params.lossless_mode_d_c || 13068 _soc_kt2_mmu_params.packing_mode_d_c) { 13069 temp_val = 0; 13070 } else { 13071 temp_val = 1; 13072 } 13073 soc_mem_field32_set(unit, THDIEXT_THDI_PORT_PG_CONFIGm, 13074 &thdiext_thdi_port_pg_config, PG_GBL_HDRM_ENf , 13075 temp_val); 13076 } 13077 /* C346: THDIEXT_THDI_PORT_PG_CONFIG.SP_SHARED_MAX_ENABLE = 13078 For Ge:1 For Hg,Cpu: Ge Value only!!! */ 13079 soc_mem_field32_set(unit, THDIEXT_THDI_PORT_PG_CONFIGm, 13080 &thdiext_thdi_port_pg_config, SP_SHARED_MAX_ENABLEf ,1); 13081 13082 /* C347: THDIEXT_THDI_PORT_PG_CONFIG.SP_MIN_PG_ENABLE = 13083 For Ge:1 For Hg,Cpu: Ge Value only!!! */ 13084 soc_mem_field32_set(unit, THDIEXT_THDI_PORT_PG_CONFIGm, 13085 &thdiext_thdi_port_pg_config, SP_MIN_PG_ENABLEf ,1); 13086 13087 SOC_IF_ERROR_RETURN (soc_mem_write(unit, 13088 THDIEXT_THDI_PORT_PG_CONFIGm, MEM_BLOCK_ALL, 13089 mem_idx, &thdiext_thdi_port_pg_config)); 13090 } 13091 /* 1.3 EMA Pool */ 13092 /* Assuming only service_pool = 0 is used */ 13093 /* Assuming only priority_group = 0 is used on single PG ports */ 13094 /* Assuming only priority_group = 7 is used on eight PG ports */ 13095 SOC_PBMP_ITER (valid_port_cpu_pbmp, port) { 13096 if ((ext_mem_port_count) || (_soc_kt2_mmu_params.packing_mode_d_c)) { 13097 if (((port > KT2_CMIC_PORT) && (port < KT2_LPBK_PORT) && 13098 (((*kt2_port_to_mxqblock_subports[unit])[port-1] == 0) || 13099 (port == 30) || (port == 33) || 13100 (port == 36) || (port == 39))) || (IS_LB_PORT(unit,port))) { 13101 priority_group = 7; 13102 } else { 13103 priority_group = 0; 13104 } 13105 if( (flex_port != -1) && (flex_port != port) ) { 13106 continue; 13107 } 13108 sal_memset(&thdiema_thdi_port_sp_config,0, 13109 sizeof(thdiema_thdi_port_sp_config)); 13110 mem_idx= (port * KT2_MAX_SERVICE_POOLS) + service_pool; 13111 /* C350: THDIEMA_THDI_PORT_SP_CONFIG.PORT_SP_MIN_LIMIT = $C$166 */ 13112 soc_mem_field32_set(unit, THDIEMA_THDI_PORT_SP_CONFIGm, 13113 &thdiema_thdi_port_sp_config, PORT_SP_MIN_LIMITf, 13114 input_port_threshold->min_int_buff_ema_pool_cells_for_a_port); 13115 13116 /* C351: THDIEMA_THDI_PORT_SP_CONFIG.PORT_SP_MAX_LIMIT = 13117 $C$262 <== =C184 */ 13118 soc_mem_field32_set(unit, THDIEMA_THDI_PORT_SP_CONFIGm, 13119 &thdiema_thdi_port_sp_config, PORT_SP_MAX_LIMITf, 13120 input_port_threshold->total_shared_EMA_buff); 13121 13122 /* C352: THDIEMA_PORT_MAX_PKT_SIZE.PORT_MAX_PKT_SIZE = =$C$68 */ 13123 SOC_IF_ERROR_RETURN(READ_THDIEMA_PORT_MAX_PKT_SIZEr ( 13124 unit, port, &rval)); 13125 soc_reg_field_set(unit, THDIEMA_PORT_MAX_PKT_SIZEr, &rval, 13126 PORT_MAX_PKT_SIZEf, 13127 general_info->max_packet_size_in_cells); 13128 SOC_IF_ERROR_RETURN(WRITE_THDIEMA_PORT_MAX_PKT_SIZEr ( 13129 unit, port, rval)); 13130 /* C353: THDIEMA_THDI_PORT_SP_CONFIG.PORT_SP_RESUME_LIMIT = 13131 =$C$351-2*$C$72 */ 13132 soc_mem_field32_set(unit, THDIEMA_THDI_PORT_SP_CONFIGm, 13133 &thdiema_thdi_port_sp_config, PORT_SP_RESUME_LIMITf, 13134 input_port_threshold->total_shared_EMA_buff - 13135 (2 * general_info->ether_mtu_cells_for_int_buff)); 13136 SOC_IF_ERROR_RETURN(soc_mem_write(unit, 13137 THDIEMA_THDI_PORT_SP_CONFIGm, MEM_BLOCK_ALL, 13138 mem_idx, &thdiema_thdi_port_sp_config)); 13139 } 13140 sal_memset(&thdiema_thdi_port_pg_config,0, 13141 sizeof(thdiema_thdi_port_pg_config)); 13142 mem_idx= (port * KT2_MAX_PRIORITY_GROUPS) + priority_group; 13143 if ((ext_mem_port_count) || (_soc_kt2_mmu_params.packing_mode_d_c)) { 13144 /* C354: THDIEMA_THDI_PORT_PG_CONFIG.PG_MIN_LIMIT(PG0) = =$C$154 */ 13145 soc_mem_field32_set(unit, THDIEMA_THDI_PORT_PG_CONFIGm, 13146 &thdiema_thdi_port_pg_config, PG_MIN_LIMITf, 13147 input_port_threshold->min_int_buff_ema_pool_cells_per_PG); 13148 13149 13150 /* C355: THDIEMA_THDI_PORT_PG_CONFIG.PG_SHARED_LIMIT = 13151 IF($C$14, $C$58, $C$262) */ 13152 if (_soc_kt2_mmu_params.lossless_mode_d_c) { 13153 temp_val = _soc_kt2_mmu_params.mmu_ing_pg_dyn_thd_param; 13154 } else { 13155 /* $C$262 = =$C$184 */ 13156 temp_val = input_port_threshold->total_shared_EMA_buff; 13157 } 13158 soc_mem_field32_set(unit, THDIEMA_THDI_PORT_PG_CONFIGm, 13159 &thdiema_thdi_port_pg_config, 13160 PG_SHARED_LIMITf, temp_val); 13161 13162 /* C356: THDIEMA_THDI_PORT_PG_CONFIG.PG_RESET_OFFSET = =2*$C$72 */ 13163 soc_mem_field32_set(unit, THDIEMA_THDI_PORT_PG_CONFIGm, 13164 &thdiema_thdi_port_pg_config, PG_RESET_OFFSETf, 13165 (2 * general_info->ether_mtu_cells_for_int_buff)); 13166 13167 /* C357: THDIEMA_PORT_PG_CONFIG.PG_RESET_FLOOR = 0 */ 13168 soc_mem_field32_set(unit, THDIEMA_THDI_PORT_PG_CONFIGm, 13169 &thdiema_thdi_port_pg_config, PG_RESET_FLOORf, 0); 13170 13171 /* C358: THDIEMA_THDI_PORT_PG_CONFIG.PG_SHARED_DYNAMIC= 13172 IF($C$14, 1, 0) */ 13173 if (_soc_kt2_mmu_params.lossless_mode_d_c) { 13174 temp_val = 1; 13175 } else { 13176 temp_val = 0; 13177 } 13178 soc_mem_field32_set(unit, THDIEMA_THDI_PORT_PG_CONFIGm, 13179 &thdiema_thdi_port_pg_config, PG_SHARED_DYNAMICf, 13180 temp_val); 13181 13182 /* C359: THDIEMA_THDI_PORT_PG_CONFIG.PG_HDRM_LIMIT 13183 For Ge:$C122 For Hg:$C112 For Cpu:$C142 */ 13184 if (IS_CPU_PORT(unit, port)) { 13185 temp_val = input_port_threshold-> 13186 hdrm_int_buff_cells_for_cpu_port; 13187 } else if (IS_GE_PORT(unit, port) || IS_LB_PORT(unit,port)) { 13188 temp_val = input_port_threshold->hdrm_int_buff_cells_for_1G_PG; 13189 } else if (IS_HG_PORT(unit, port) || IS_XE_PORT(unit,port)) { 13190 temp_val= input_port_threshold->hdrm_int_buff_cells_for_10G_PG; 13191 } 13192 soc_mem_field32_set(unit, THDIEMA_THDI_PORT_PG_CONFIGm, 13193 &thdiema_thdi_port_pg_config, PG_HDRM_LIMITf,temp_val); 13194 13195 /* C360: THDIEMA_THDI_PORT_PG_CONFIG.PG_GBL_HDRM_EN = 13196 for lossy=1 else 0 */ 13197 if (_soc_kt2_mmu_params.lossless_mode_d_c) { 13198 temp_val = 0; 13199 } else { 13200 temp_val = 1; 13201 } 13202 soc_mem_field32_set(unit, THDIEMA_THDI_PORT_PG_CONFIGm, 13203 &thdiema_thdi_port_pg_config, PG_GBL_HDRM_ENf , 13204 temp_val); 13205 } 13206 /* C361: THDIEMA_THDI_PORT_PG_CONFIG.SP_SHARED_MAX_ENABLE = 13207 For Ge:1 For Hg,Cpu: Ge Value only!!! */ 13208 soc_mem_field32_set(unit, THDIEMA_THDI_PORT_PG_CONFIGm, 13209 &thdiema_thdi_port_pg_config, SP_SHARED_MAX_ENABLEf ,1); 13210 13211 /* C362: THDIEMA_THDI_PORT_PG_CONFIG.SP_MIN_PG_ENABLE = 13212 For Ge:1 For Hg,Cpu: Ge Value only!!! */ 13213 soc_mem_field32_set(unit, THDIEMA_THDI_PORT_PG_CONFIGm, 13214 &thdiema_thdi_port_pg_config, SP_MIN_PG_ENABLEf ,1); 13215 SOC_IF_ERROR_RETURN(soc_mem_write( 13216 unit, THDIEMA_THDI_PORT_PG_CONFIGm, 13217 MEM_BLOCK_ALL, mem_idx, 13218 &thdiema_thdi_port_pg_config)); 13219 } 13220 /* 1.4 RE WQEs */ 13221 /* Assuming only service_pool = 0 is used */ 13222 /* Assuming only priority_group = 0 is used on single PG ports */ 13223 /* Assuming only priority_group = 7 is used on eight PG ports */ 13224 SOC_PBMP_ITER (valid_port_cpu_pbmp, port) { 13225 if (((port > KT2_CMIC_PORT) && (port < KT2_LPBK_PORT) && 13226 (((*kt2_port_to_mxqblock_subports[unit])[port-1] == 0) || 13227 (port == 30) || (port == 33) || 13228 (port == 36) || (port == 39))) || (IS_LB_PORT(unit,port))) { 13229 priority_group = 7; 13230 } else { 13231 priority_group = 0; 13232 } 13233 if( (flex_port != -1) && (flex_port != port) ) { 13234 continue; 13235 } 13236 sal_memset(&thdirqe_thdi_port_sp_config , 0, 13237 sizeof(thdirqe_thdi_port_sp_config)); 13238 13239 mem_idx= (port * KT2_MAX_SERVICE_POOLS) + service_pool; 13240 /* C365: THDIRQE_THDI_PORT_SP_CONFIG.PORT_SP_MIN_LIMIT = $C$168 */ 13241 soc_mem_field32_set(unit, THDIRQE_THDI_PORT_SP_CONFIGm, 13242 &thdirqe_thdi_port_sp_config, PORT_SP_MIN_LIMITf, 13243 input_port_threshold->min_RE_WQEs_pkts_for_a_port); 13244 13245 /* C366: THDIRQE_THDI_PORT_SP_CONFIG.PORT_SP_MAX_LIMIT = $C$186 */ 13246 soc_mem_field32_set(unit, THDIRQE_THDI_PORT_SP_CONFIGm, 13247 &thdirqe_thdi_port_sp_config, PORT_SP_MAX_LIMITf, 13248 input_port_threshold->total_shared_RE_WQEs_buff); 13249 13250 /* C367: THDIRQE_THDI_PORT_SP_CONFIG.PORT_SP_RESUME_LIMIT = 13251 =$C$366 -2 */ 13252 soc_mem_field32_set(unit, THDIRQE_THDI_PORT_SP_CONFIGm, 13253 &thdirqe_thdi_port_sp_config, PORT_SP_RESUME_LIMITf, 13254 input_port_threshold->total_shared_RE_WQEs_buff - 2); 13255 SOC_IF_ERROR_RETURN(soc_mem_write( 13256 unit, THDIRQE_THDI_PORT_SP_CONFIGm, MEM_BLOCK_ALL, 13257 mem_idx, &thdirqe_thdi_port_sp_config)); 13258 13259 sal_memset(&thdirqe_thdi_port_pg_config , 0, 13260 sizeof(thdirqe_thdi_port_pg_config)); 13261 mem_idx= (port * KT2_MAX_PRIORITY_GROUPS) + priority_group; 13262 /* C368: THDIRQE_THDI_PORT_PG_CONFIG.PG_MIN_LIMIT(PG0) = =$C$156 */ 13263 temp_val = input_port_threshold->min_RE_WQEs_pkt_per_PG; 13264 soc_mem_field32_set(unit, THDIRQE_THDI_PORT_PG_CONFIGm, 13265 &thdirqe_thdi_port_pg_config, PG_MIN_LIMITf,temp_val); 13266 13267 /* C369: THDIRQE_THDI_PORT_PG_CONFIG.PG_SHARED_LIMIT = 13268 IF($C$14, $C$58, $C$186) */ 13269 if (_soc_kt2_mmu_params.lossless_mode_d_c) { 13270 temp_val = _soc_kt2_mmu_params.mmu_ing_pg_dyn_thd_param; 13271 } else { 13272 temp_val = input_port_threshold->total_shared_RE_WQEs_buff; 13273 } 13274 soc_mem_field32_set(unit, THDIRQE_THDI_PORT_PG_CONFIGm, 13275 &thdirqe_thdi_port_pg_config, 13276 PG_SHARED_LIMITf, temp_val); 13277 13278 /* C370: THDIRQE_THDI_PORT_PG_CONFIG.PG_RESET_OFFSET = 2 */ 13279 soc_mem_field32_set(unit, THDIRQE_THDI_PORT_PG_CONFIGm, 13280 &thdirqe_thdi_port_pg_config, PG_RESET_OFFSETf,2); 13281 13282 /* C371: THDIRQE_THDI_PORT_PG_CONFIG.PG_RESET_FLOOR = 0 */ 13283 soc_mem_field32_set(unit, THDIRQE_THDI_PORT_PG_CONFIGm, 13284 &thdirqe_thdi_port_pg_config, PG_RESET_FLOORf, 0); 13285 13286 /* C372: THDIRQE_THDI_PORT_PG_CONFIG.PG_SHARED_DYNAMIC= 13287 IF($C$14, 1, 0) */ 13288 if (_soc_kt2_mmu_params.lossless_mode_d_c) { 13289 temp_val = 1; 13290 } else { 13291 temp_val = 0; 13292 } 13293 soc_mem_field32_set(unit, THDIRQE_THDI_PORT_PG_CONFIGm, 13294 &thdirqe_thdi_port_pg_config, PG_SHARED_DYNAMICf, 13295 temp_val); 13296 13297 /* C373: THDIRQE_THDI_PORT_PG_CONFIG.PG_HDRM_LIMIT 13298 For Ge:$C124 For Hg:$C114 For Cpu:$C144 */ 13299 if (IS_CPU_PORT(unit, port)) { 13300 temp_val = input_port_threshold->hdrm_RE_WQEs_pkts_for_cpu_port; 13301 } else if (IS_GE_PORT(unit, port) || IS_LB_PORT(unit,port)) { 13302 temp_val = input_port_threshold->hdrm_RE_WQEs_pkts_for_1G_PG; 13303 } else if (IS_HG_PORT(unit, port) || IS_XE_PORT(unit, port)) { 13304 temp_val= input_port_threshold->hdrm_RE_WQEs_pkts_for_10G_PG; 13305 } 13306 soc_mem_field32_set(unit, THDIRQE_THDI_PORT_PG_CONFIGm, 13307 &thdirqe_thdi_port_pg_config, PG_HDRM_LIMITf,temp_val); 13308 13309 /* C374: THDIRQE_THDI_PORT_PG_CONFIG.PG_GBL_HDRM_EN = 13310 for lossy=1 else 0 13311 Packed : 0 */ 13312 if (_soc_kt2_mmu_params.lossless_mode_d_c || 13313 _soc_kt2_mmu_params.packing_mode_d_c) { 13314 temp_val = 0; 13315 } else { 13316 temp_val = 1; 13317 } 13318 soc_mem_field32_set(unit, THDIRQE_THDI_PORT_PG_CONFIGm, 13319 &thdirqe_thdi_port_pg_config, PG_GBL_HDRM_ENf , 13320 temp_val); 13321 13322 /* C375: THDIRQE_THDI_PORT_PG_CONFIG.SP_SHARED_MAX_ENABLE = 13323 For Ge:1 For Hg,Cpu: Ge Value only!!! */ 13324 soc_mem_field32_set(unit, THDIRQE_THDI_PORT_PG_CONFIGm, 13325 &thdirqe_thdi_port_pg_config, SP_SHARED_MAX_ENABLEf ,1); 13326 13327 /* C376: THDIRQE_THDI_PORT_PG_CONFIG.SP_MIN_PG_ENABLE = 13328 For Ge:1 For Hg,Cpu: Ge Value only!!! */ 13329 soc_mem_field32_set(unit, THDIRQE_THDI_PORT_PG_CONFIGm, 13330 &thdirqe_thdi_port_pg_config, SP_MIN_PG_ENABLEf ,1); 13331 13332 SOC_IF_ERROR_RETURN(soc_mem_write(unit, THDIRQE_THDI_PORT_PG_CONFIGm, 13333 MEM_BLOCK_ALL, mem_idx, &thdirqe_thdi_port_pg_config)); 13334 13335 } 13336 /* 1.5 EQEs */ 13337 /* Assuming only service_pool = 0 is used */ 13338 /* Assuming only priority_group = 0 is used on single PG ports */ 13339 /* Assuming only priority_group = 7 is used on eight PG ports */ 13340 SOC_PBMP_ITER (valid_port_cpu_pbmp, port) { 13341 if (((port > KT2_CMIC_PORT) && (port < KT2_LPBK_PORT) && 13342 (((*kt2_port_to_mxqblock_subports[unit])[port-1] == 0) || 13343 (port == 30) || (port == 33) || 13344 (port == 36) || (port == 39))) || (IS_LB_PORT(unit,port))) { 13345 priority_group = 7; 13346 } else { 13347 priority_group = 0; 13348 } 13349 if( (flex_port != -1) && (flex_port != port) ) { 13350 continue; 13351 } 13352 sal_memset(&thdiqen_thdi_port_sp_config,0, 13353 sizeof(thdiqen_thdi_port_sp_config)); 13354 mem_idx= (port * KT2_MAX_SERVICE_POOLS) + service_pool; 13355 /* C379: THDIQEN_THDI_PORT_SP_CONFIG.PORT_SP_MIN_LIMIT = $C$169 */ 13356 soc_mem_field32_set(unit, THDIQEN_THDI_PORT_SP_CONFIGm, 13357 &thdiqen_thdi_port_sp_config, PORT_SP_MIN_LIMITf, 13358 input_port_threshold->min_EQEs_pkts_for_a_port); 13359 13360 /* C380: THDIQEN_THDI_PORT_SP_CONFIG.PORT_SP_MAX_LIMIT = $C$187 */ 13361 soc_mem_field32_set(unit, THDIQEN_THDI_PORT_SP_CONFIGm, 13362 &thdiqen_thdi_port_sp_config, PORT_SP_MAX_LIMITf, 13363 input_port_threshold->total_shared_EQEs_buff); 13364 13365 /* C381: THDIQEN_THDI_PORT_SP_CONFIG.PORT_SP_RESUME_LIMIT = 13366 =C380-2*C49 */ 13367 soc_mem_field32_set(unit, THDIQEN_THDI_PORT_SP_CONFIGm, 13368 &thdiqen_thdi_port_sp_config, PORT_SP_RESUME_LIMITf, 13369 input_port_threshold->total_shared_EQEs_buff - 13370 (2 * _soc_kt2_mmu_params.mmu_exp_num_of_repl_per_pkt)); 13371 SOC_IF_ERROR_RETURN(soc_mem_write(unit, 13372 THDIQEN_THDI_PORT_SP_CONFIGm, MEM_BLOCK_ALL, 13373 mem_idx, &thdiqen_thdi_port_sp_config)); 13374 sal_memset(&thdiqen_thdi_port_pg_config,0, 13375 sizeof(thdiqen_thdi_port_pg_config)); 13376 mem_idx= (port * KT2_MAX_PRIORITY_GROUPS) + priority_group; 13377 /* C382: THDIQEN_THDI_PORT_PG_CONFIG.PG_MIN_LIMIT(PG0) = 13378 =$C$157 */ 13379 soc_mem_field32_set(unit, THDIQEN_THDI_PORT_PG_CONFIGm, 13380 &thdiqen_thdi_port_pg_config, PG_MIN_LIMITf, 13381 input_port_threshold->min_EQEs_pkt_per_PG); 13382 13383 13384 /* C383: THDIQEN_THDI_PORT_PG_CONFIG.PG_SHARED_LIMIT = 13385 =IF($C$14, $C$58, $C$187) */ 13386 if (_soc_kt2_mmu_params.lossless_mode_d_c) { 13387 temp_val = _soc_kt2_mmu_params.mmu_ing_pg_dyn_thd_param; 13388 } else { 13389 temp_val = input_port_threshold->total_shared_EQEs_buff; 13390 } 13391 soc_mem_field32_set(unit, THDIQEN_THDI_PORT_PG_CONFIGm, 13392 &thdiqen_thdi_port_pg_config, 13393 PG_SHARED_LIMITf, temp_val); 13394 13395 /* C384: THDIQEN_THDI_PORT_PG_CONFIG.PG_RESET_OFFSET = =2*C49 */ 13396 soc_mem_field32_set(unit, THDIQEN_THDI_PORT_PG_CONFIGm, 13397 &thdiqen_thdi_port_pg_config, PG_RESET_OFFSETf, 13398 2 * _soc_kt2_mmu_params.mmu_exp_num_of_repl_per_pkt); 13399 13400 /* C385: THDIQEN_THDI_PORT_PG_CONFIG.PG_RESET_FLOOR = 0 */ 13401 soc_mem_field32_set(unit, THDIQEN_THDI_PORT_PG_CONFIGm, 13402 &thdiqen_thdi_port_pg_config, PG_RESET_FLOORf, 0); 13403 13404 /* C386: THDIQEN_THDI_PORT_PG_CONFIG.PG_SHARED_DYNAMIC= 13405 IF($C$14, 1, 0) */ 13406 if (_soc_kt2_mmu_params.lossless_mode_d_c) { 13407 temp_val = 1; 13408 } else { 13409 temp_val = 0; 13410 } 13411 soc_mem_field32_set(unit, THDIQEN_THDI_PORT_PG_CONFIGm, 13412 &thdiqen_thdi_port_pg_config, PG_SHARED_DYNAMICf, 13413 temp_val); 13414 13415 /* C387: THDIQEN_THDI_PORT_PG_CONFIG.PG_HDRM_LIMIT 13416 For Ge:$C125 For Hg:$C115 For Cpu:$C145 */ 13417 if (IS_CPU_PORT(unit, port)) { 13418 temp_val = input_port_threshold->hdrm_EQEs_pkts_for_cpu_port; 13419 } else if (IS_GE_PORT(unit, port) || IS_LB_PORT(unit,port)) { 13420 temp_val = input_port_threshold->hdrm_EQEs_pkts_for_1G_PG; 13421 } else if (IS_HG_PORT(unit, port) || IS_XE_PORT(unit, port)) { 13422 temp_val= input_port_threshold->hdrm_EQEs_pkts_for_10G_PG; 13423 } 13424 soc_mem_field32_set(unit, THDIQEN_THDI_PORT_PG_CONFIGm, 13425 &thdiqen_thdi_port_pg_config, PG_HDRM_LIMITf,temp_val); 13426 13427 /* C388: THDIQEN_THDI_PORT_PG_CONFIG.PG_GBL_HDRM_EN = 13428 for lossy=1 else 0 13429 Packed : 0 */ 13430 if (_soc_kt2_mmu_params.lossless_mode_d_c || 13431 _soc_kt2_mmu_params.packing_mode_d_c) { 13432 temp_val = 0; 13433 } else { 13434 temp_val = 1; 13435 } 13436 soc_mem_field32_set(unit, THDIQEN_THDI_PORT_PG_CONFIGm, 13437 &thdiqen_thdi_port_pg_config, PG_GBL_HDRM_ENf , 13438 temp_val); 13439 13440 /* C389: THDIQEN_THDI_PORT_PG_CONFIG.SP_SHARED_MAX_ENABLE = 13441 For Ge:1 For Hg,Cpu: Ge Value only!!! */ 13442 soc_mem_field32_set(unit, THDIQEN_THDI_PORT_PG_CONFIGm, 13443 &thdiqen_thdi_port_pg_config, SP_SHARED_MAX_ENABLEf ,1); 13444 13445 /* C390: THDIQEN_THDI_PORT_PG_CONFIG.SP_MIN_PG_ENABLE = 13446 For Ge:1 For Hg,Cpu: Ge Value only!!! */ 13447 soc_mem_field32_set(unit, THDIQEN_THDI_PORT_PG_CONFIGm, 13448 &thdiqen_thdi_port_pg_config, SP_MIN_PG_ENABLEf ,1); 13449 SOC_IF_ERROR_RETURN(soc_mem_write( unit, THDIQEN_THDI_PORT_PG_CONFIGm, 13450 MEM_BLOCK_ALL, mem_idx, &thdiqen_thdi_port_pg_config)); 13451 13452 } 13453 13454 /* ######################## */ 13455 /* 2. Output Port Thresholds */ 13456 /* ######################## */ 13457 /* 2.1 Internal Buffer */ 13458 op_node = 0; 13459 port_max_opnodes = 0; 13460 for(port_index = 0, op_node = 0 ; 13461 port_index < COUNTOF(port_list); 13462 port_index++, op_node += port_max_opnodes ) { 13463 13464 port = port_list[port_index]; 13465 port_max_opnodes = ceil_func(si->port_num_uc_cosq[port],8); 13466 13467 if (!SOC_PBMP_MEMBER(valid_port_cpu_pbmp, port)) { 13468 continue; 13469 } 13470 if( (flex_port != -1) && (flex_port != port) ) { 13471 continue; 13472 } 13473 13474 if (!SOC_PBMP_MEMBER(PBMP_EXT_MEM (unit), port) && 13475 (port >= KT2_CMIC_PORT) && (port <= KT2_LPBK_PORT)) { 13476 for (op_node_offset = 0; 13477 op_node_offset < port_max_opnodes ; 13478 op_node_offset++) { 13479 SOC_IF_ERROR_RETURN(READ_MMU_THDO_OPNCONFIG_CELLm(unit, 13480 MEM_BLOCK_ANY,op_node + op_node_offset, 13481 &mmu_thdo_opnconfig_cell_entry)); 13482 /* C394:THDO_OPNCONFIG_CELL.OPN_SHARED_LIMIT_CELL = =$C$219 */ 13483 soc_mem_field32_set(unit, MMU_THDO_OPNCONFIG_CELLm, 13484 &mmu_thdo_opnconfig_cell_entry, 13485 OPN_SHARED_LIMIT_CELLf, 13486 output_port_threshold-> 13487 min_grntd_tot_shr_queue_cells_int_buff); 13488 13489 /* C395:THDO_OPNCONFIG_CELL.OP_SHARED_RESET_VALUE_CELL 13490 = C394-2*$C$72 */ 13491 temp_val = output_port_threshold-> 13492 min_grntd_tot_shr_queue_cells_int_buff - 13493 (2 * general_info->ether_mtu_cells_for_int_buff); 13494 soc_mem_field32_set(unit, MMU_THDO_OPNCONFIG_CELLm, 13495 &mmu_thdo_opnconfig_cell_entry, 13496 OPN_SHARED_RESET_VALUE_CELLf, temp_val); 13497 13498 /* C396:THDO_OPNCONFIG_CELL.PORT_LIMIT_ENABLE_CELL 13499 = 0 */ 13500 soc_mem_field32_set(unit, MMU_THDO_OPNCONFIG_CELLm, 13501 &mmu_thdo_opnconfig_cell_entry, 13502 PORT_LIMIT_ENABLE_CELLf, 0); 13503 /* PIDf :Updated by cosq scheduler code while attaching node */ 13504 /* 13505 soc_mem_field32_set(unit, MMU_THDO_OPNCONFIG_CELLm, 13506 &mmu_thdo_opnconfig_cell_entry, 13507 PIDf, port); 13508 */ 13509 SOC_IF_ERROR_RETURN(WRITE_MMU_THDO_OPNCONFIG_CELLm(unit, 13510 MEM_BLOCK_ALL,op_node + op_node_offset, 13511 &mmu_thdo_opnconfig_cell_entry)); 13512 } 13513 13514 buf_port = &buf->ports[port]; 13515 13516 for (queue = si->port_uc_cosq_base[port]; 13517 queue < si->port_uc_cosq_base[port] + 13518 si->port_num_uc_cosq[port]; 13519 queue++) { 13520 /* caluculating idx as per the mmu_config tool*/ 13521 idx = si->port_num_cosq[port] + queue - si->port_uc_cosq_base[port]; 13522 buf_queue = &buf_port->queues[idx]; 13523 SOC_IF_ERROR_RETURN(READ_MMU_THDO_QCONFIG_CELLm(unit, 13524 MEM_BLOCK_ANY,queue, 13525 &mmu_thdo_qconfig_cell_entry)); 13526 /* C397:THDO_QCONFIG_CELL.Q_MIN_CELL 13527 = =$C$201 */ 13528 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, 13529 &mmu_thdo_qconfig_cell_entry, Q_MIN_CELLf, 13530 buf_queue->guarantee > 0 ? buf_queue->guarantee : 13531 output_port_threshold->min_grntd_res_queue_cells_int_buff); 13532 13533 /* C398:THDO_QCONFIG_CELL.Q_SHARED_LIMIT_CELL 13534 =IF($C$14,$C$219,$C$60) */ 13535 if (_soc_kt2_mmu_params.lossless_mode_d_c) { 13536 temp_val = output_port_threshold-> 13537 min_grntd_tot_shr_queue_cells_int_buff; 13538 } else { 13539 temp_val = _soc_kt2_mmu_params.mmu_egr_pg_dyn_thd_param; 13540 } 13541 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, 13542 &mmu_thdo_qconfig_cell_entry, Q_SHARED_LIMIT_CELLf, 13543 temp_val); 13544 13545 if ((buf_queue->pool_scale != -1) && 13546 mmu_config_enabled) { 13547 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, 13548 &mmu_thdo_qconfig_cell_entry, Q_LIMIT_DYNAMIC_CELLf, 13549 1); 13550 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, 13551 &mmu_thdo_qconfig_cell_entry, Q_SHARED_LIMIT_CELLf, 13552 buf_queue->pool_scale); 13553 } else { 13554 /* C400:THDO_QCONFIG_CELL.Q_LIMIT_DYNAMIC_CELL 13555 =IF($C$14, 0, 1) */ 13556 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, 13557 &mmu_thdo_qconfig_cell_entry, Q_LIMIT_DYNAMIC_CELLf, 13558 _soc_kt2_mmu_params.lossless_mode_d_c ? 0 : 1); 13559 } 13560 13561 /* C401:THDO_QCONFIG_CELL.Q_LIMIT_ENABLE_CELL 13562 =IF($C$14, 0, 1) */ 13563 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, 13564 &mmu_thdo_qconfig_cell_entry, Q_LIMIT_ENABLE_CELLf, 13565 _soc_kt2_mmu_params.lossless_mode_d_c ? 0 : 1); 13566 13567 /* C402:THDO_QCONFIG_CELL.Q_COLOR_ENABLE_CELL = 0 */ 13568 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, 13569 &mmu_thdo_qconfig_cell_entry, Q_COLOR_ENABLE_CELLf,0); 13570 13571 /* C403: THDO_QCONFIG_CELL.Q_COLOR_LIMIT_DYNAMIC_CELL 13572 =IF($C$14, 0, 1) */ 13573 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, 13574 &mmu_thdo_qconfig_cell_entry, Q_COLOR_LIMIT_DYNAMIC_CELLf, 13575 _soc_kt2_mmu_params.lossless_mode_d_c ? 0 : 1); 13576 13577 /* C404: THDO_QCONFIG_CELL.LIMIT_YELLOW_CELL= 13578 if lossless= C398/8 else C398 */ 13579 temp_val = soc_mem_field32_get(unit, MMU_THDO_QCONFIG_CELLm, 13580 &mmu_thdo_qconfig_cell_entry, Q_SHARED_LIMIT_CELLf); 13581 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, 13582 &mmu_thdo_qconfig_cell_entry, LIMIT_YELLOW_CELLf, 13583 _soc_kt2_mmu_params.lossless_mode_d_c ? 13584 ceil_func(temp_val, 8) : temp_val); 13585 SOC_IF_ERROR_RETURN(WRITE_MMU_THDO_QCONFIG_CELLm(unit, 13586 MEM_BLOCK_ALL,queue, 13587 &mmu_thdo_qconfig_cell_entry)); 13588 13589 SOC_IF_ERROR_RETURN(READ_MMU_THDO_QOFFSET_CELLm(unit, 13590 MEM_BLOCK_ANY,queue, 13591 &mmu_thdo_qoffset_cell_entry)); 13592 /* C399:THDO_QOFFSET_CELL.RESET_OFFSET_CELL =2 */ 13593 soc_mem_field32_set(unit, MMU_THDO_QOFFSET_CELLm, 13594 &mmu_thdo_qoffset_cell_entry, RESET_OFFSET_CELLf, 2); 13595 13596 /* C405: THDO_QOFFSET_CELL.LIMIT_RED_CELL = 13597 if lossless= C398/8 else C398 */ 13598 temp_val = soc_mem_field32_get(unit, MMU_THDO_QCONFIG_CELLm, 13599 &mmu_thdo_qconfig_cell_entry, Q_SHARED_LIMIT_CELLf); 13600 soc_mem_field32_set(unit, MMU_THDO_QOFFSET_CELLm, 13601 &mmu_thdo_qoffset_cell_entry, LIMIT_RED_CELLf, 13602 _soc_kt2_mmu_params.lossless_mode_d_c ? 13603 ceil_func(temp_val, 8) : temp_val); 13604 13605 /* C406: THDO_QOFFSET_CELL.RESET_OFFSET_YELLOW_CELL =2 */ 13606 soc_mem_field32_set(unit, MMU_THDO_QOFFSET_CELLm, 13607 &mmu_thdo_qoffset_cell_entry, RESET_OFFSET_YELLOW_CELLf,2); 13608 /* C407: THDO_QOFFSET_CELL.RESET_OFFSET_RED_CELL =2 */ 13609 soc_mem_field32_set(unit, MMU_THDO_QOFFSET_CELLm, 13610 &mmu_thdo_qoffset_cell_entry, RESET_OFFSET_RED_CELLf,2); 13611 13612 SOC_IF_ERROR_RETURN(WRITE_MMU_THDO_QOFFSET_CELLm(unit, 13613 MEM_BLOCK_ALL,queue, 13614 &mmu_thdo_qoffset_cell_entry)); 13615 } 13616 } 13617 } 13618 /* 2.2 External Buffer */ 13619 for(port_index = 0, op_node = 0 ; 13620 port_index < COUNTOF(port_list); 13621 port_index++, op_node += port_max_opnodes ) { 13622 13623 port = port_list[port_index]; 13624 port_max_opnodes = ceil_func(si->port_num_uc_cosq[port],8); 13625 13626 if (!SOC_PBMP_MEMBER(valid_port_cpu_pbmp, port)) { 13627 continue; 13628 } 13629 if( (flex_port != -1) && (flex_port != port) ) { 13630 continue; 13631 } 13632 13633 if (!IS_CPU_PORT(unit, port) && 13634 (port > KT2_CMIC_PORT) && (port <= KT2_LPBK_PORT) && 13635 SOC_PBMP_MEMBER(PBMP_EXT_MEM (unit), port)) { 13636 13637 SOC_IF_ERROR_RETURN(READ_MMU_THDO_OPNCONFIG_CELLm(unit, 13638 MEM_BLOCK_ANY,op_node , &mmu_thdo_opnconfig_cell_entry)); 13639 /* C409:THDO_OPNCONFIG_CELL.OPN_SHARED_LIMIT_CELL = =$C$220 */ 13640 soc_mem_field32_set(unit, MMU_THDO_OPNCONFIG_CELLm, 13641 &mmu_thdo_opnconfig_cell_entry, 13642 OPN_SHARED_LIMIT_CELLf, 13643 output_port_threshold-> 13644 min_grntd_tot_shr_queue_cells_ext_buff); 13645 13646 /* C410:THDO_OPNCONFIG_CELL.OP_SHARED_RESET_VALUE_CELL 13647 = =$C$409-2*$C$73 */ 13648 temp_val = output_port_threshold-> 13649 min_grntd_tot_shr_queue_cells_ext_buff - 13650 (2 * general_info->ether_mtu_cells_for_ext_buff); 13651 soc_mem_field32_set(unit, MMU_THDO_OPNCONFIG_CELLm, 13652 &mmu_thdo_opnconfig_cell_entry, 13653 OPN_SHARED_RESET_VALUE_CELLf, temp_val); 13654 13655 /* C411:THDO_OPNCONFIG_CELL.PORT_LIMIT_ENABLE_CELL = 0 */ 13656 soc_mem_field32_set(unit, MMU_THDO_OPNCONFIG_CELLm, 13657 &mmu_thdo_opnconfig_cell_entry, 13658 PORT_LIMIT_ENABLE_CELLf, 0); 13659 /* PIDf :Updated by cosq scheduler code while attaching node */ 13660 /* 13661 soc_mem_field32_set(unit, MMU_THDO_OPNCONFIG_CELLm, 13662 &mmu_thdo_opnconfig_cell_entry, 13663 PIDf, port); 13664 */ 13665 SOC_IF_ERROR_RETURN(WRITE_MMU_THDO_OPNCONFIG_CELLm(unit, 13666 MEM_BLOCK_ALL,op_node, 13667 &mmu_thdo_opnconfig_cell_entry)); 13668 13669 for (queue = si->port_uc_cosq_base[port]; 13670 queue < si->port_uc_cosq_base[port] + 13671 si->port_num_uc_cosq[port]; 13672 queue++) { 13673 SOC_IF_ERROR_RETURN(READ_MMU_THDO_QCONFIG_CELLm(unit, 13674 MEM_BLOCK_ANY,queue, 13675 &mmu_thdo_qconfig_cell_entry)); 13676 /* C412:THDO_QCONFIG_CELL.Q_MIN_CELL 13677 = =$C$202 */ 13678 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, 13679 &mmu_thdo_qconfig_cell_entry, Q_MIN_CELLf, 13680 output_port_threshold->min_grntd_res_queue_cells_ext_buff); 13681 13682 /* C413:THDO_QCONFIG_CELL.Q_SHARED_LIMIT_CELL 13683 =IF($C$14,$C$220,$C$60) */ 13684 if (_soc_kt2_mmu_params.lossless_mode_d_c) { 13685 temp_val = output_port_threshold-> 13686 min_grntd_tot_shr_queue_cells_ext_buff; 13687 } else { 13688 temp_val = _soc_kt2_mmu_params.mmu_egr_pg_dyn_thd_param; 13689 } 13690 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, 13691 &mmu_thdo_qconfig_cell_entry, Q_SHARED_LIMIT_CELLf, 13692 temp_val); 13693 13694 /* C415:THDO_QCONFIG_CELL.Q_LIMIT_DYNAMIC_CELL 13695 =IF($C$14, 0, 1) */ 13696 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, 13697 &mmu_thdo_qconfig_cell_entry, Q_LIMIT_DYNAMIC_CELLf, 13698 _soc_kt2_mmu_params.lossless_mode_d_c ? 0 : 1); 13699 13700 /* C416:THDO_QCONFIG_CELL.Q_LIMIT_ENABLE_CELL 13701 =IF($C$14, 0, 1) */ 13702 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, 13703 &mmu_thdo_qconfig_cell_entry, Q_LIMIT_ENABLE_CELLf, 13704 _soc_kt2_mmu_params.lossless_mode_d_c ? 0 : 1); 13705 13706 /* C417:THDO_QCONFIG_CELL.Q_COLOR_ENABLE_CELL = 0 */ 13707 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, 13708 &mmu_thdo_qconfig_cell_entry, Q_COLOR_ENABLE_CELLf,0); 13709 13710 /* C418: THDO_QCONFIG_CELL.Q_COLOR_LIMIT_DYNAMIC_CELL 13711 =IF($C$14, 0, 1) */ 13712 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, 13713 &mmu_thdo_qconfig_cell_entry, Q_COLOR_LIMIT_DYNAMIC_CELLf, 13714 _soc_kt2_mmu_params.lossless_mode_d_c ? 0 : 1); 13715 13716 /* C419: THDO_QCONFIG_CELL.LIMIT_YELLOW_CELL= 13717 if lossless= CEILING(C413/8) else C413 */ 13718 temp_val = soc_mem_field32_get(unit, MMU_THDO_QCONFIG_CELLm, 13719 &mmu_thdo_qconfig_cell_entry, Q_SHARED_LIMIT_CELLf); 13720 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, 13721 &mmu_thdo_qconfig_cell_entry, LIMIT_YELLOW_CELLf, 13722 _soc_kt2_mmu_params.lossless_mode_d_c ? 13723 ceil_func(temp_val, 8) : temp_val); 13724 SOC_IF_ERROR_RETURN(WRITE_MMU_THDO_QCONFIG_CELLm(unit, 13725 MEM_BLOCK_ALL,queue, 13726 &mmu_thdo_qconfig_cell_entry)); 13727 13728 SOC_IF_ERROR_RETURN(READ_MMU_THDO_QOFFSET_CELLm(unit, 13729 MEM_BLOCK_ANY,queue, 13730 &mmu_thdo_qoffset_cell_entry)); 13731 /* C414:THDO_QOFFSET_CELL.RESET_OFFSET_CELL =2 */ 13732 soc_mem_field32_set(unit, MMU_THDO_QOFFSET_CELLm, 13733 &mmu_thdo_qoffset_cell_entry, RESET_OFFSET_CELLf, 2); 13734 13735 /* C420: THDO_QOFFSET_CELL.LIMIT_RED_CELL = 13736 if lossless= CEILING(C413/8) else C413 */ 13737 temp_val = soc_mem_field32_get(unit, MMU_THDO_QCONFIG_CELLm, 13738 &mmu_thdo_qconfig_cell_entry, Q_SHARED_LIMIT_CELLf); 13739 soc_mem_field32_set(unit, MMU_THDO_QOFFSET_CELLm, 13740 &mmu_thdo_qoffset_cell_entry, LIMIT_RED_CELLf, 13741 _soc_kt2_mmu_params.lossless_mode_d_c ? 13742 ceil_func(temp_val, 8) : temp_val); 13743 13744 /* C421: THDO_QOFFSET_CELL.RESET_OFFSET_YELLOW_CELL =2 */ 13745 soc_mem_field32_set(unit, MMU_THDO_QOFFSET_CELLm, 13746 &mmu_thdo_qoffset_cell_entry, RESET_OFFSET_YELLOW_CELLf,2); 13747 /* C422: THDO_QOFFSET_CELL.RESET_OFFSET_RED_CELL =2 */ 13748 soc_mem_field32_set(unit, MMU_THDO_QOFFSET_CELLm, 13749 &mmu_thdo_qoffset_cell_entry, RESET_OFFSET_RED_CELLf,2); 13750 13751 SOC_IF_ERROR_RETURN(WRITE_MMU_THDO_QOFFSET_CELLm(unit, 13752 MEM_BLOCK_ALL,queue, 13753 &mmu_thdo_qoffset_cell_entry)); 13754 } 13755 } 13756 } 13757 /* 2.3 EMA Pool */ 13758 if ((ext_mem_port_count) || (_soc_kt2_mmu_params.packing_mode_d_c)) { 13759 for(cos=0; cos<SOC_REG_NUMELS(unit, OP_QUEUE_CONFIG1_THDOEMAr); cos++) { 13760 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_CONFIG1_THDOEMAr( 13761 unit, cos, &rval)); 13762 /* C424:OP_QUEUE_CONFIG1_THDOEMA.Q_MIN = C204 */ 13763 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_THDOEMAr, &rval, 13764 Q_MINf, 13765 output_port_threshold->min_grntd_res_EMA_queue_cells); 13766 13767 /* C429:OP_QUEUE_CONFIG1_THDOEMA.Q_COLOR_ENABLE = 0 */ 13768 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_THDOEMAr, &rval, 13769 Q_COLOR_ENABLEf, 0); 13770 13771 /* C430:OP_QUEUE_CONFIG1_THDOEMA.Q_COLOR_DYNAMIC lossless=0 else 1*/ 13772 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_THDOEMAr, &rval, 13773 Q_COLOR_DYNAMICf, 13774 _soc_kt2_mmu_params.lossless_mode_d_c? 0 : 1); 13775 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_CONFIG1_THDOEMAr( 13776 unit, cos, rval)); 13777 } 13778 13779 for(cos=0; cos<SOC_REG_NUMELS(unit, OP_QUEUE_CONFIG_THDOEMAr); cos++) { 13780 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_CONFIG_THDOEMAr( 13781 unit, cos, &rval)); 13782 /* C425:OP_QUEUE_CONFIG_THDOEMA.Q_SHARED_LIMIT 13783 =IF($C$14,$C$222,$C$60)..Can be put outside loop */ 13784 if (_soc_kt2_mmu_params.lossless_mode_d_c) { 13785 temp_val = output_port_threshold-> 13786 min_grntd_tot_shr_EMA_queue_cells; 13787 } else { 13788 temp_val = _soc_kt2_mmu_params.mmu_egr_pg_dyn_thd_param; 13789 } 13790 soc_reg_field_set(unit, OP_QUEUE_CONFIG_THDOEMAr, &rval, 13791 Q_SHARED_LIMITf, temp_val); 13792 13793 /*C427: OP_QUEUE_CONFIG_THDOEMA.Q_LIMIT_DYNAMIC:=lossless=0 else 1*/ 13794 13795 soc_reg_field_set(unit, OP_QUEUE_CONFIG_THDOEMAr, &rval, 13796 Q_LIMIT_DYNAMICf, 13797 _soc_kt2_mmu_params.lossless_mode_d_c? 0 : 1); 13798 13799 /*C428:OP_QUEUE_CONFIG_THDOEMA.Q_LIMIT_ENABLE:=lossless=0 else 1*/ 13800 soc_reg_field_set(unit, OP_QUEUE_CONFIG_THDOEMAr, &rval, 13801 Q_LIMIT_ENABLEf, 13802 _soc_kt2_mmu_params.lossless_mode_d_c? 0 : 1); 13803 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_CONFIG_THDOEMAr( 13804 unit, cos, rval)); 13805 13806 } 13807 for(cos=0; 13808 cos<SOC_REG_NUMELS(unit, OP_QUEUE_RESET_OFFSET_THDOEMAr); cos++) { 13809 SOC_IF_ERROR_RETURN( 13810 READ_OP_QUEUE_RESET_OFFSET_THDOEMAr(unit, cos,&rval)); 13811 /*C422: OP_QUEUE_RESET_OFFSET_THDOEMA.Q_RESET_OFFSET == 2 */ 13812 soc_reg_field_set(unit, OP_QUEUE_RESET_OFFSET_THDOEMAr, &rval, 13813 Q_RESET_OFFSETf, 2); 13814 SOC_IF_ERROR_RETURN( 13815 WRITE_OP_QUEUE_RESET_OFFSET_THDOEMAr(unit, cos,rval)); 13816 } 13817 for(cos=0; 13818 cos<SOC_REG_NUMELS(unit, OP_QUEUE_LIMIT_YELLOW_THDOEMAr); 13819 cos++) { 13820 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_LIMIT_YELLOW_THDOEMAr( 13821 unit, cos,&rval)); 13822 /* C431: OP_QUEUE_LIMIT_YELLOW_THDOEMA.Q_LIMIT_YELLOW 13823 for lossless =CEILING(C425/8, 1) else C425 */ 13824 /* HG Port has temp_val/8++ !! */ 13825 if (_soc_kt2_mmu_params.lossless_mode_d_c) { 13826 temp_val = output_port_threshold-> 13827 min_grntd_tot_shr_EMA_queue_cells; 13828 } else { 13829 temp_val = _soc_kt2_mmu_params.mmu_egr_pg_dyn_thd_param; 13830 } 13831 soc_reg_field_set(unit, OP_QUEUE_LIMIT_YELLOW_THDOEMAr, &rval, 13832 Q_LIMIT_YELLOWf, _soc_kt2_mmu_params.lossless_mode_d_c? 13833 ceil_func(temp_val,8): temp_val); 13834 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_LIMIT_YELLOW_THDOEMAr( 13835 unit, cos,rval)); 13836 } 13837 for(cos=0; 13838 cos<SOC_REG_NUMELS(unit, OP_QUEUE_LIMIT_RED_THDOEMAr); 13839 cos++) { 13840 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_LIMIT_RED_THDOEMAr( 13841 unit, cos,&rval)); 13842 /* C432: OP_QUEUE_LIMIT_RED_THDOEMA.Q_LIMIT_RED 13843 for lossless =CEILING(C425/8, 1) else C425 */ 13844 /* HG Port has temp_val/8++ !! */ 13845 if (_soc_kt2_mmu_params.lossless_mode_d_c) { 13846 temp_val = output_port_threshold-> 13847 min_grntd_tot_shr_EMA_queue_cells; 13848 } else { 13849 temp_val = _soc_kt2_mmu_params.mmu_egr_pg_dyn_thd_param; 13850 } 13851 soc_reg_field_set(unit, OP_QUEUE_LIMIT_RED_THDOEMAr, &rval, 13852 Q_LIMIT_REDf, _soc_kt2_mmu_params.lossless_mode_d_c? 13853 ceil_func(temp_val,8): temp_val); 13854 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_LIMIT_RED_THDOEMAr( 13855 unit, cos,rval)); 13856 } 13857 for(cos=0; 13858 cos < SOC_REG_NUMELS(unit, OP_QUEUE_RESET_OFFSET_YELLOW_THDOEMAr); 13859 cos++) { 13860 SOC_IF_ERROR_RETURN( 13861 READ_OP_QUEUE_RESET_OFFSET_YELLOW_THDOEMAr(unit, cos,&rval)); 13862 /*C433:OP_QUEUE_RESET_OFFSET_YELLOW_THDOEMA.RESUME_OFFSET_YELLOW=2*/ 13863 soc_reg_field_set(unit, 13864 OP_QUEUE_RESET_OFFSET_YELLOW_THDOEMAr, &rval, 13865 RESUME_OFFSET_YELLOWf, 2); 13866 SOC_IF_ERROR_RETURN( 13867 WRITE_OP_QUEUE_RESET_OFFSET_YELLOW_THDOEMAr(unit, cos,rval)); 13868 } 13869 for(cos=0; 13870 cos < SOC_REG_NUMELS(unit, OP_QUEUE_RESET_OFFSET_RED_THDOEMAr); 13871 cos++) { 13872 SOC_IF_ERROR_RETURN( 13873 READ_OP_QUEUE_RESET_OFFSET_RED_THDOEMAr(unit, cos,&rval)); 13874 /*C434:OP_QUEUE_RESET_OFFSET_RED_THDOEMA.RESUME_OFFSET_RED=2*/ 13875 soc_reg_field_set(unit, 13876 OP_QUEUE_RESET_OFFSET_RED_THDOEMAr, &rval, 13877 RESUME_OFFSET_REDf, 2); 13878 SOC_IF_ERROR_RETURN( 13879 WRITE_OP_QUEUE_RESET_OFFSET_RED_THDOEMAr(unit, cos,rval)); 13880 } 13881 } 13882 /* 2.4 RE WQEs */ 13883 /* 2.4.1 RQEQ */ 13884 for(cos=0; cos<SOC_REG_NUMELS(unit, OP_QUEUE_CONFIG1_THDORQEQr); cos++) { 13885 buf_rqe_queue = &buf->rqe_queues[cos]; 13886 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_CONFIG1_THDORQEQr( 13887 unit, cos, &rval)); 13888 if (buf_rqe_queue->pkt_guarantee) { 13889 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_THDORQEQr, &rval, 13890 Q_MINf, 13891 buf_rqe_queue->pkt_guarantee); 13892 } else { 13893 /* C436:OP_QUEUE_CONFIG1_THDORQEQ.Q_MIN = C205 */ 13894 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_THDORQEQr, &rval, 13895 Q_MINf, 13896 output_port_threshold->min_grntd_res_RE_WQs_cells); 13897 } 13898 13899 /* C441:OP_QUEUE_CONFIG1_THDORQEQ.Q_COLOR_ENABLE = 0 */ 13900 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_THDORQEQr, &rval, 13901 Q_COLOR_ENABLEf, 0); 13902 13903 /* C442:OP_QUEUE_CONFIG1_THDORQEQ.Q_COLOR_DYNAMIC lossless=0 else 1*/ 13904 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_THDORQEQr, &rval, 13905 Q_COLOR_DYNAMICf, 13906 _soc_kt2_mmu_params.lossless_mode_d_c? 0 : 1); 13907 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_CONFIG1_THDORQEQr( 13908 unit, cos, rval)); 13909 } 13910 13911 for(cos=0; cos<SOC_REG_NUMELS(unit, OP_QUEUE_CONFIG_THDORQEQr); cos++) { 13912 buf_rqe_queue = &buf->rqe_queues[cos]; 13913 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_CONFIG_THDORQEQr( 13914 unit, cos, &rval)); 13915 /* C437:OP_QUEUE_CONFIG_THDORQEQ.Q_SHARED_LIMIT 13916 =IF($C$14,$C$223-1,$C$60)..Can be put outside loop */ 13917 if (_soc_kt2_mmu_params.lossless_mode_d_c) { 13918 temp_val = output_port_threshold-> 13919 min_grntd_tot_shr_RE_WQs_cells - 1; 13920 } else { 13921 temp_val = _soc_kt2_mmu_params.mmu_egr_pg_dyn_thd_param; 13922 } 13923 13924 if ((buf_rqe_queue->pkt_pool_scale != -1) && 13925 mmu_config_enabled) { 13926 soc_reg_field_set(unit, OP_QUEUE_CONFIG_THDORQEQr, &rval, 13927 Q_SHARED_LIMITf, buf_rqe_queue->pkt_pool_scale); 13928 soc_reg_field_set(unit, OP_QUEUE_CONFIG_THDORQEQr, &rval, 13929 Q_LIMIT_DYNAMICf, 1); 13930 13931 } else { 13932 soc_reg_field_set(unit, OP_QUEUE_CONFIG_THDORQEQr, &rval, 13933 Q_SHARED_LIMITf, temp_val); 13934 /*C439: OP_QUEUE_CONFIG_THDORQEQ.Q_LIMIT_DYNAMIC:=lossless=0 else 1*/ 13935 13936 soc_reg_field_set(unit, OP_QUEUE_CONFIG_THDORQEQr, &rval, 13937 Q_LIMIT_DYNAMICf, 13938 _soc_kt2_mmu_params.lossless_mode_d_c? 0 : 1); 13939 } 13940 /*C440:OP_QUEUE_CONFIG_THDORQEQ.Q_LIMIT_ENABLE:=lossless=0 else 1*/ 13941 soc_reg_field_set(unit, OP_QUEUE_CONFIG_THDORQEQr, &rval, 13942 Q_LIMIT_ENABLEf, 13943 _soc_kt2_mmu_params.lossless_mode_d_c? 0 : 1); 13944 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_CONFIG_THDORQEQr( 13945 unit, cos, rval)); 13946 13947 } 13948 for(cos=0; 13949 cos<SOC_REG_NUMELS(unit, OP_QUEUE_RESET_OFFSET_THDORQEQr); cos++) { 13950 SOC_IF_ERROR_RETURN( 13951 READ_OP_QUEUE_RESET_OFFSET_THDORQEQr(unit, cos,&rval)); 13952 /*C438: OP_QUEUE_RESET_OFFSET_THDORQEQ.Q_RESET_OFFSET == 1 */ 13953 soc_reg_field_set(unit, OP_QUEUE_RESET_OFFSET_THDORQEQr, &rval, 13954 Q_RESET_OFFSETf, 1); 13955 SOC_IF_ERROR_RETURN( 13956 WRITE_OP_QUEUE_RESET_OFFSET_THDORQEQr(unit, cos,rval)); 13957 } 13958 for(cos=0; 13959 cos<SOC_REG_NUMELS(unit, OP_QUEUE_LIMIT_YELLOW_THDORQEQr); 13960 cos++) { 13961 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_LIMIT_YELLOW_THDORQEQr( 13962 unit, cos,&rval)); 13963 /* C443: OP_QUEUE_LIMIT_YELLOW_THDORQEQ.Q_LIMIT_YELLOW 13964 for lossless =CEILING(C437/8, 1)-1 else C437 */ 13965 if (_soc_kt2_mmu_params.lossless_mode_d_c) { 13966 temp_val = ceil_func(output_port_threshold-> 13967 min_grntd_tot_shr_RE_WQs_cells,8) - 1; 13968 } else { 13969 temp_val = _soc_kt2_mmu_params.mmu_egr_pg_dyn_thd_param; 13970 } 13971 soc_reg_field_set(unit, OP_QUEUE_LIMIT_YELLOW_THDORQEQr, &rval, 13972 Q_LIMIT_YELLOWf, temp_val); 13973 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_LIMIT_YELLOW_THDORQEQr( 13974 unit, cos,rval)); 13975 } 13976 for(cos=0; 13977 cos<SOC_REG_NUMELS(unit, OP_QUEUE_LIMIT_RED_THDORQEQr); 13978 cos++) { 13979 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_LIMIT_RED_THDORQEQr( 13980 unit, cos,&rval)); 13981 /* C444: OP_QUEUE_LIMIT_RED_THDORQEQ.Q_LIMIT_RED 13982 for lossless =CEILING(C437/8, 1)-1 else C437 */ 13983 if (_soc_kt2_mmu_params.lossless_mode_d_c) { 13984 temp_val = ceil_func(output_port_threshold-> 13985 min_grntd_tot_shr_RE_WQs_cells,8) - 1; 13986 } else { 13987 temp_val = _soc_kt2_mmu_params.mmu_egr_pg_dyn_thd_param; 13988 } 13989 soc_reg_field_set(unit, OP_QUEUE_LIMIT_RED_THDORQEQr, &rval, 13990 Q_LIMIT_REDf, temp_val); 13991 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_LIMIT_RED_THDORQEQr( 13992 unit, cos,rval)); 13993 } 13994 for(cos=0; 13995 cos < SOC_REG_NUMELS(unit, OP_QUEUE_RESET_OFFSET_YELLOW_THDORQEQr); 13996 cos++) { 13997 SOC_IF_ERROR_RETURN( 13998 READ_OP_QUEUE_RESET_OFFSET_YELLOW_THDORQEQr(unit, cos,&rval)); 13999 /*C445:OP_QUEUE_RESET_OFFSET_YELLOW_THDORQEQ.RESUME_OFFSET_YELLOW=1*/ 14000 soc_reg_field_set(unit, 14001 OP_QUEUE_RESET_OFFSET_YELLOW_THDORQEQr, &rval, 14002 RESUME_OFFSET_YELLOWf, 1); 14003 SOC_IF_ERROR_RETURN( 14004 WRITE_OP_QUEUE_RESET_OFFSET_YELLOW_THDORQEQr(unit, cos,rval)); 14005 } 14006 for(cos=0; 14007 cos < SOC_REG_NUMELS(unit, OP_QUEUE_RESET_OFFSET_RED_THDORQEQr); 14008 cos++) { 14009 SOC_IF_ERROR_RETURN( 14010 READ_OP_QUEUE_RESET_OFFSET_RED_THDORQEQr(unit, cos,&rval)); 14011 /*C446:OP_QUEUE_RESET_OFFSET_RED_THDORQEQ.RESUME_OFFSET_RED=1*/ 14012 soc_reg_field_set(unit, 14013 OP_QUEUE_RESET_OFFSET_RED_THDORQEQr, &rval, 14014 RESUME_OFFSET_REDf, 1); 14015 SOC_IF_ERROR_RETURN( 14016 WRITE_OP_QUEUE_RESET_OFFSET_RED_THDORQEQr(unit, cos,rval)); 14017 } 14018 /* 2.4.2 RQEI */ 14019 for(cos=0; cos<SOC_REG_NUMELS(unit, OP_QUEUE_CONFIG1_THDORQEIr); cos++) { 14020 buf_rqe_queue = &buf->rqe_queues[cos]; 14021 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_CONFIG1_THDORQEIr( 14022 unit, cos, &rval)); 14023 if (buf_rqe_queue->guarantee) { 14024 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_THDORQEIr, &rval, Q_MINf, 14025 buf_rqe_queue->guarantee); 14026 14027 } else { 14028 /* C447:OP_QUEUE_CONFIG1_THDORQEI.Q_MIN = C206 */ 14029 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_THDORQEIr, &rval, Q_MINf, 14030 output_port_threshold->min_grntd_res_RE_WQs_queue_cells_for_int_buff); 14031 } 14032 14033 /* C452:OP_QUEUE_CONFIG1_THDORQEI.Q_COLOR_ENABLE = 0 */ 14034 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_THDORQEIr, &rval, 14035 Q_COLOR_ENABLEf, 0); 14036 14037 /* C453:OP_QUEUE_CONFIG1_THDORQEI.Q_COLOR_DYNAMIC lossless=0 else 1*/ 14038 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_THDORQEIr, &rval, 14039 Q_COLOR_DYNAMICf, 14040 _soc_kt2_mmu_params.lossless_mode_d_c? 0 : 1); 14041 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_CONFIG1_THDORQEIr( 14042 unit, cos, rval)); 14043 } 14044 14045 for(cos=0; cos<SOC_REG_NUMELS(unit, OP_QUEUE_CONFIG_THDORQEIr); cos++) { 14046 buf_rqe_queue = &buf->rqe_queues[cos]; 14047 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_CONFIG_THDORQEIr( 14048 unit, cos, &rval)); 14049 /* C448:OP_QUEUE_CONFIG_THDORQEI.Q_SHARED_LIMIT 14050 =IF($C$14,$C$224,$C$60)..Can be put outside loop */ 14051 if (_soc_kt2_mmu_params.lossless_mode_d_c) { 14052 temp_val = output_port_threshold->min_grntd_tot_shr_RE_WQs_queue_cells_for_int_buff; 14053 } else { 14054 temp_val = _soc_kt2_mmu_params.mmu_egr_pg_dyn_thd_param; 14055 } 14056 /* 14057 SOC_FIND_FIELD(Q_SHARED_LIMITf, 14058 SOC_REG_INFO(unit, OP_QUEUE_CONFIG_THDORQEIr).fields, 14059 SOC_REG_INFO(unit, OP_QUEUE_CONFIG_THDORQEIr).nFields, 14060 fieldp); 14061 if (temp_val >= (1 << fieldp->len)) { 14062 temp_val = (1 << fieldp->len) - 1; 14063 } 14064 */ 14065 if ((buf_rqe_queue->pool_scale != -1 ) && 14066 mmu_config_enabled) { 14067 soc_reg_field_set(unit, OP_QUEUE_CONFIG_THDORQEIr, &rval, 14068 Q_SHARED_LIMITf, buf_rqe_queue->pool_scale); 14069 soc_reg_field_set(unit, OP_QUEUE_CONFIG_THDORQEIr, &rval, 14070 Q_LIMIT_DYNAMICf, 14071 1); 14072 14073 } else { 14074 soc_reg_field_set(unit, OP_QUEUE_CONFIG_THDORQEIr, &rval, 14075 Q_SHARED_LIMITf, temp_val); 14076 14077 /*C450: OP_QUEUE_CONFIG_THDORQEI.Q_LIMIT_DYNAMIC:=lossless=0 else 1*/ 14078 soc_reg_field_set(unit, OP_QUEUE_CONFIG_THDORQEIr, &rval, 14079 Q_LIMIT_DYNAMICf, 14080 _soc_kt2_mmu_params.lossless_mode_d_c? 0 : 1); 14081 } 14082 14083 /*C451:OP_QUEUE_CONFIG_THDORQEI.Q_LIMIT_ENABLE:=lossless=0 else 1*/ 14084 soc_reg_field_set(unit, OP_QUEUE_CONFIG_THDORQEIr, &rval, 14085 Q_LIMIT_ENABLEf, 14086 _soc_kt2_mmu_params.lossless_mode_d_c? 0 : 1); 14087 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_CONFIG_THDORQEIr( 14088 unit, cos, rval)); 14089 14090 } 14091 for(cos=0; 14092 cos<SOC_REG_NUMELS(unit, OP_QUEUE_RESET_OFFSET_THDORQEIr); cos++) { 14093 SOC_IF_ERROR_RETURN( 14094 READ_OP_QUEUE_RESET_OFFSET_THDORQEIr(unit, cos,&rval)); 14095 /*C449: OP_QUEUE_RESET_OFFSET_THDORQEI.Q_RESET_OFFSET == 2 */ 14096 soc_reg_field_set(unit, OP_QUEUE_RESET_OFFSET_THDORQEIr, &rval, 14097 Q_RESET_OFFSETf, 2); 14098 SOC_IF_ERROR_RETURN( 14099 WRITE_OP_QUEUE_RESET_OFFSET_THDORQEIr(unit, cos,rval)); 14100 } 14101 for(cos=0; 14102 cos<SOC_REG_NUMELS(unit, OP_QUEUE_LIMIT_YELLOW_THDORQEIr); 14103 cos++) { 14104 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_LIMIT_YELLOW_THDORQEIr( 14105 unit, cos,&rval)); 14106 /* C454: OP_QUEUE_LIMIT_YELLOW_THDORQEI.Q_LIMIT_YELLOW 14107 for lossless =CEILING(C448/8, 1) else C448 */ 14108 if (_soc_kt2_mmu_params.lossless_mode_d_c) { 14109 temp_val = ceil_func(output_port_threshold->min_grntd_tot_shr_RE_WQs_queue_cells_for_int_buff,8); 14110 } else { 14111 temp_val = _soc_kt2_mmu_params.mmu_egr_pg_dyn_thd_param; 14112 } 14113 /* 14114 SOC_FIND_FIELD(Q_LIMIT_YELLOWf, 14115 SOC_REG_INFO(unit, OP_QUEUE_LIMIT_YELLOW_THDORQEIr).fields, 14116 SOC_REG_INFO(unit, OP_QUEUE_LIMIT_YELLOW_THDORQEIr).nFields, 14117 fieldp); 14118 if (temp_val >= (1 << fieldp->len)) { 14119 temp_val = (1 << fieldp->len) - 1; 14120 } 14121 */ 14122 soc_reg_field_set(unit, OP_QUEUE_LIMIT_YELLOW_THDORQEIr, &rval, 14123 Q_LIMIT_YELLOWf, temp_val); 14124 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_LIMIT_YELLOW_THDORQEIr( 14125 unit, cos,rval)); 14126 } 14127 for(cos=0; 14128 cos<SOC_REG_NUMELS(unit, OP_QUEUE_LIMIT_RED_THDORQEIr); 14129 cos++) { 14130 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_LIMIT_RED_THDORQEIr( 14131 unit, cos,&rval)); 14132 /* C455: OP_QUEUE_LIMIT_RED_THDORQEI.Q_LIMIT_RED 14133 for lossless =CEILING(C448/8, 1) else C448 */ 14134 if (_soc_kt2_mmu_params.lossless_mode_d_c) { 14135 temp_val = ceil_func(output_port_threshold->min_grntd_tot_shr_RE_WQs_queue_cells_for_int_buff,8); 14136 } else { 14137 temp_val = _soc_kt2_mmu_params.mmu_egr_pg_dyn_thd_param; 14138 } 14139 /* 14140 SOC_FIND_FIELD(Q_LIMIT_REDf, 14141 SOC_REG_INFO(unit, OP_QUEUE_LIMIT_RED_THDORQEIr).fields, 14142 SOC_REG_INFO(unit, OP_QUEUE_LIMIT_RED_THDORQEIr).nFields, 14143 fieldp); 14144 if (temp_val >= (1 << fieldp->len)) { 14145 temp_val = (1 << fieldp->len) - 1; 14146 } 14147 */ 14148 soc_reg_field_set(unit, OP_QUEUE_LIMIT_RED_THDORQEIr, &rval, 14149 Q_LIMIT_REDf, temp_val); 14150 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_LIMIT_RED_THDORQEIr( 14151 unit, cos,rval)); 14152 } 14153 for(cos=0; 14154 cos < SOC_REG_NUMELS(unit, OP_QUEUE_RESET_OFFSET_YELLOW_THDORQEIr); 14155 cos++) { 14156 SOC_IF_ERROR_RETURN( 14157 READ_OP_QUEUE_RESET_OFFSET_YELLOW_THDORQEIr(unit, cos,&rval)); 14158 /*C456:OP_QUEUE_RESET_OFFSET_YELLOW_THDORQEI.RESUME_OFFSET_YELLOW=2*/ 14159 soc_reg_field_set(unit, 14160 OP_QUEUE_RESET_OFFSET_YELLOW_THDORQEIr, &rval, 14161 RESUME_OFFSET_YELLOWf, 2); 14162 SOC_IF_ERROR_RETURN( 14163 WRITE_OP_QUEUE_RESET_OFFSET_YELLOW_THDORQEIr(unit, cos,rval)); 14164 } 14165 for(cos=0; 14166 cos < SOC_REG_NUMELS(unit, OP_QUEUE_RESET_OFFSET_RED_THDORQEIr); 14167 cos++) { 14168 SOC_IF_ERROR_RETURN( 14169 READ_OP_QUEUE_RESET_OFFSET_RED_THDORQEIr(unit, cos,&rval)); 14170 /*C457:OP_QUEUE_RESET_OFFSET_RED_THDORQEI.RESUME_OFFSET_RED=2*/ 14171 soc_reg_field_set(unit, 14172 OP_QUEUE_RESET_OFFSET_RED_THDORQEIr, &rval, 14173 RESUME_OFFSET_REDf, 2); 14174 SOC_IF_ERROR_RETURN( 14175 WRITE_OP_QUEUE_RESET_OFFSET_RED_THDORQEIr(unit, cos,rval)); 14176 } 14177 /* 2.4.3 RQEE */ 14178 if ((ext_mem_port_count) || (_soc_kt2_mmu_params.packing_mode_d_c)) { 14179 for(cos=0; cos<SOC_REG_NUMELS(unit, OP_QUEUE_CONFIG1_THDORQEEr); cos++) { 14180 buf_rqe_queue = &buf->rqe_queues[cos]; 14181 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_CONFIG1_THDORQEEr( 14182 unit, cos, &rval)); 14183 /* C458:OP_QUEUE_CONFIG1_THDORQEE.Q_MIN = C207 */ 14184 if (buf_rqe_queue->ext_guarantee) { 14185 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_THDORQEEr, &rval, Q_MINf, 14186 buf_rqe_queue->ext_guarantee); 14187 } else { 14188 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_THDORQEEr, &rval, Q_MINf, 14189 output_port_threshold->min_grntd_res_RE_WQs_queue_cells_for_ext_buff); 14190 } 14191 /* C463:OP_QUEUE_CONFIG1_THDORQEE.Q_COLOR_ENABLE = 0 */ 14192 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_THDORQEEr, &rval, 14193 Q_COLOR_ENABLEf, 0); 14194 14195 /* C464:OP_QUEUE_CONFIG1_THDORQEE.Q_COLOR_DYNAMIC lossless=0 else 1*/ 14196 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_THDORQEEr, &rval, 14197 Q_COLOR_DYNAMICf, 14198 _soc_kt2_mmu_params.lossless_mode_d_c? 0 : 1); 14199 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_CONFIG1_THDORQEEr( 14200 unit, cos, rval)); 14201 } 14202 14203 for(cos=0; cos<SOC_REG_NUMELS(unit, OP_QUEUE_CONFIG_THDORQEEr); cos++) { 14204 buf_rqe_queue = &buf->rqe_queues[cos]; 14205 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_CONFIG_THDORQEEr( 14206 unit, cos, &rval)); 14207 /* C459:OP_QUEUE_CONFIG_THDORQEE.Q_SHARED_LIMIT 14208 =IF($C$14,$C$225,$C$60)..Can be put outside loop */ 14209 if (_soc_kt2_mmu_params.lossless_mode_d_c) { 14210 temp_val = output_port_threshold->min_grntd_tot_shr_RE_WQs_queue_cells_for_ext_buff; 14211 } else { 14212 temp_val = _soc_kt2_mmu_params.mmu_egr_pg_dyn_thd_param; 14213 } 14214 /* 14215 SOC_FIND_FIELD(Q_SHARED_LIMITf, 14216 SOC_REG_INFO(unit, OP_QUEUE_CONFIG_THDORQEEr).fields, 14217 SOC_REG_INFO(unit, OP_QUEUE_CONFIG_THDORQEEr).nFields, 14218 fieldp); 14219 if (temp_val >= (1 << fieldp->len)) { 14220 temp_val = (1 << fieldp->len) - 1; 14221 } 14222 */ 14223 14224 if ((buf_rqe_queue->ext_pool_scale != -1) && 14225 mmu_config_enabled) { 14226 soc_reg_field_set(unit, OP_QUEUE_CONFIG_THDORQEEr, &rval, 14227 Q_SHARED_LIMITf, buf_rqe_queue->ext_pool_scale); 14228 soc_reg_field_set(unit, OP_QUEUE_CONFIG_THDORQEEr, &rval, 14229 Q_LIMIT_DYNAMICf, 14230 1); 14231 } else { 14232 soc_reg_field_set(unit, OP_QUEUE_CONFIG_THDORQEEr, &rval, 14233 Q_SHARED_LIMITf, temp_val); 14234 /*C461: OP_QUEUE_CONFIG_THDORQEE.Q_LIMIT_DYNAMIC:=lossless=0 else 1*/ 14235 soc_reg_field_set(unit, OP_QUEUE_CONFIG_THDORQEEr, &rval, 14236 Q_LIMIT_DYNAMICf, 14237 _soc_kt2_mmu_params.lossless_mode_d_c? 0 : 1); 14238 } 14239 /*C462:OP_QUEUE_CONFIG_THDORQEE.Q_LIMIT_ENABLE:=lossless=0 else 1*/ 14240 soc_reg_field_set(unit, OP_QUEUE_CONFIG_THDORQEEr, &rval, 14241 Q_LIMIT_ENABLEf, 14242 _soc_kt2_mmu_params.lossless_mode_d_c? 0 : 1); 14243 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_CONFIG_THDORQEEr( 14244 unit, cos, rval)); 14245 14246 } 14247 for(cos=0; 14248 cos<SOC_REG_NUMELS(unit, OP_QUEUE_RESET_OFFSET_THDORQEEr); cos++) { 14249 SOC_IF_ERROR_RETURN( 14250 READ_OP_QUEUE_RESET_OFFSET_THDORQEEr(unit, cos,&rval)); 14251 /*C460: OP_QUEUE_RESET_OFFSET_THDORQEE.Q_RESET_OFFSET == 2 */ 14252 soc_reg_field_set(unit, OP_QUEUE_RESET_OFFSET_THDORQEEr, &rval, 14253 Q_RESET_OFFSETf, 2); 14254 SOC_IF_ERROR_RETURN( 14255 WRITE_OP_QUEUE_RESET_OFFSET_THDORQEEr(unit, cos,rval)); 14256 } 14257 for(cos=0; 14258 cos<SOC_REG_NUMELS(unit, OP_QUEUE_LIMIT_YELLOW_THDORQEEr); 14259 cos++) { 14260 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_LIMIT_YELLOW_THDORQEEr( 14261 unit, cos,&rval)); 14262 /* C465: OP_QUEUE_LIMIT_YELLOW_THDORQEE.Q_LIMIT_YELLOW 14263 for lossless =CEILING(C459/8, 1) else C459*/ 14264 if (_soc_kt2_mmu_params.lossless_mode_d_c) { 14265 temp_val = ceil_func(output_port_threshold->min_grntd_tot_shr_RE_WQs_queue_cells_for_ext_buff,8); 14266 } else { 14267 temp_val = _soc_kt2_mmu_params.mmu_egr_pg_dyn_thd_param; 14268 } 14269 /* 14270 SOC_FIND_FIELD(Q_LIMIT_YELLOWf, 14271 SOC_REG_INFO(unit, OP_QUEUE_LIMIT_YELLOW_THDORQEEr).fields, 14272 SOC_REG_INFO(unit, OP_QUEUE_LIMIT_YELLOW_THDORQEEr).nFields, 14273 fieldp); 14274 if (temp_val >= (1 << fieldp->len)) { 14275 temp_val = (1 << fieldp->len) - 1; 14276 } 14277 */ 14278 soc_reg_field_set(unit, OP_QUEUE_LIMIT_YELLOW_THDORQEEr, &rval, 14279 Q_LIMIT_YELLOWf, temp_val); 14280 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_LIMIT_YELLOW_THDORQEEr( 14281 unit, cos,rval)); 14282 } 14283 for(cos=0; 14284 cos<SOC_REG_NUMELS(unit, OP_QUEUE_LIMIT_RED_THDORQEEr); 14285 cos++) { 14286 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_LIMIT_RED_THDORQEEr( 14287 unit, cos,&rval)); 14288 /* C466: OP_QUEUE_LIMIT_RED_THDORQEE.Q_LIMIT_RED 14289 for lossless =CEILING(C459/8, 1) else C459 */ 14290 if (_soc_kt2_mmu_params.lossless_mode_d_c) { 14291 temp_val = ceil_func(output_port_threshold->min_grntd_tot_shr_RE_WQs_queue_cells_for_ext_buff,8); 14292 } else { 14293 temp_val = _soc_kt2_mmu_params.mmu_egr_pg_dyn_thd_param; 14294 } 14295 /* 14296 SOC_FIND_FIELD(Q_LIMIT_REDf, 14297 SOC_REG_INFO(unit, OP_QUEUE_LIMIT_RED_THDORQEEr).fields, 14298 SOC_REG_INFO(unit, OP_QUEUE_LIMIT_RED_THDORQEEr).nFields, 14299 fieldp); 14300 if (temp_val >= (1 << fieldp->len)) { 14301 temp_val = (1 << fieldp->len) - 1; 14302 } 14303 */ 14304 soc_reg_field_set(unit, OP_QUEUE_LIMIT_RED_THDORQEEr, &rval, 14305 Q_LIMIT_REDf, temp_val); 14306 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_LIMIT_RED_THDORQEEr( 14307 unit, cos,rval)); 14308 } 14309 for(cos=0; 14310 cos < SOC_REG_NUMELS(unit, OP_QUEUE_RESET_OFFSET_YELLOW_THDORQEEr); 14311 cos++) { 14312 SOC_IF_ERROR_RETURN( 14313 READ_OP_QUEUE_RESET_OFFSET_YELLOW_THDORQEEr(unit, cos,&rval)); 14314 /*C467:OP_QUEUE_RESET_OFFSET_YELLOW_THDORQEE.RESUME_OFFSET_YELLOW=2*/ 14315 soc_reg_field_set(unit, 14316 OP_QUEUE_RESET_OFFSET_YELLOW_THDORQEEr, &rval, 14317 RESUME_OFFSET_YELLOWf, 2); 14318 SOC_IF_ERROR_RETURN( 14319 WRITE_OP_QUEUE_RESET_OFFSET_YELLOW_THDORQEEr(unit, cos,rval)); 14320 } 14321 for(cos=0; 14322 cos < SOC_REG_NUMELS(unit, OP_QUEUE_RESET_OFFSET_RED_THDORQEEr); 14323 cos++) { 14324 SOC_IF_ERROR_RETURN( 14325 READ_OP_QUEUE_RESET_OFFSET_RED_THDORQEEr(unit, cos,&rval)); 14326 /*C468:OP_QUEUE_RESET_OFFSET_RED_THDORQEE.RESUME_OFFSET_RED=2*/ 14327 soc_reg_field_set(unit, 14328 OP_QUEUE_RESET_OFFSET_RED_THDORQEEr, &rval, 14329 RESUME_OFFSET_REDf, 2); 14330 SOC_IF_ERROR_RETURN( 14331 WRITE_OP_QUEUE_RESET_OFFSET_RED_THDORQEEr(unit, cos,rval)); 14332 } 14333 } 14334 /* 2.5 EQEs */ 14335 port_max_opnodes = 0; 14336 for(port_index = 0, op_node = 0 ; 14337 port_index < COUNTOF(port_list); 14338 port_index++, op_node += port_max_opnodes ) { 14339 14340 port = port_list[port_index]; 14341 port_max_opnodes = ceil_func(si->port_num_uc_cosq[port],8); 14342 14343 if (!SOC_PBMP_MEMBER(valid_port_cpu_pbmp, port)) { 14344 continue; 14345 } 14346 if( (flex_port != -1) && (flex_port != port) ) { 14347 continue; 14348 } 14349 14350 for (op_node_offset = 0; 14351 op_node_offset < port_max_opnodes; 14352 op_node_offset++) { 14353 SOC_IF_ERROR_RETURN(READ_MMU_THDO_OPNCONFIG_QENTRYm(unit, 14354 MEM_BLOCK_ANY,op_node + op_node_offset, 14355 &mmu_thdo_opnconfig_qentry_entry)); 14356 /* C470:THDO_OPNCONFIG_QENTRY.OPN_SHARED_LIMIT_QENTRY = =$C$221 */ 14357 soc_mem_field32_set(unit, MMU_THDO_OPNCONFIG_QENTRYm, 14358 &mmu_thdo_opnconfig_qentry_entry, OPN_SHARED_LIMIT_QENTRYf, 14359 output_port_threshold->min_grntd_tot_shr_queue_cells_EQEs); 14360 14361 /* C471:THDO_OPNCONFIG_QENTRY.OP_SHARED_RESET_VALUE_QENTRY 14362 = =$C$470 -2 */ 14363 temp_val = output_port_threshold-> 14364 min_grntd_tot_shr_queue_cells_EQEs - 2; 14365 soc_mem_field32_set(unit, MMU_THDO_OPNCONFIG_QENTRYm, 14366 &mmu_thdo_opnconfig_qentry_entry, 14367 OPN_SHARED_RESET_VALUE_QENTRYf, temp_val); 14368 14369 /* C472:THDO_OPNCONFIG_QENTRY.PORT_LIMIT_ENABLE_QENTRY 14370 = 0 */ 14371 soc_mem_field32_set(unit, MMU_THDO_OPNCONFIG_QENTRYm, 14372 &mmu_thdo_opnconfig_qentry_entry, 14373 PORT_LIMIT_ENABLE_QENTRYf, 0); 14374 /* PIDf :Updated by cosq scheduler code while attaching node */ 14375 /* 14376 soc_mem_field32_set(unit, MMU_THDO_OPNCONFIG_QENTRYm, 14377 &mmu_thdo_opnconfig_qentry_entry, 14378 PIDf, port); 14379 */ 14380 SOC_IF_ERROR_RETURN(WRITE_MMU_THDO_OPNCONFIG_QENTRYm(unit, 14381 MEM_BLOCK_ALL,op_node + op_node_offset, 14382 &mmu_thdo_opnconfig_qentry_entry)); 14383 } 14384 14385 buf_port = &buf->ports[port]; 14386 for (queue = si->port_uc_cosq_base[port]; 14387 queue < si->port_uc_cosq_base[port] + si->port_num_uc_cosq[port]; 14388 queue++) { 14389 idx = si->port_num_cosq[port] + queue - si->port_uc_cosq_base[port]; 14390 buf_queue = &buf_port->queues[idx]; 14391 14392 SOC_IF_ERROR_RETURN(READ_MMU_THDO_QCONFIG_QENTRYm(unit, 14393 MEM_BLOCK_ANY,queue, 14394 &mmu_thdo_qconfig_qentry_entry)); 14395 /* C473:THDO_QCONFIG_QENTRY.Q_MIN_QENTRY = =$C$203 */ 14396 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_QENTRYm, 14397 &mmu_thdo_qconfig_qentry_entry, Q_MIN_QENTRYf, 14398 buf_queue->pkt_guarantee > 0 ? buf_queue->pkt_guarantee : 14399 output_port_threshold->min_grntd_res_queue_cells_EQEs); 14400 14401 /* C474:THDO_QCONFIG_QENTRY.Q_SHARED_LIMIT_QENTRY 14402 =IF($C$14,$C$221,$C$60) */ 14403 if (_soc_kt2_mmu_params.lossless_mode_d_c) { 14404 temp_val = output_port_threshold-> 14405 min_grntd_tot_shr_queue_cells_EQEs; 14406 } else { 14407 temp_val = _soc_kt2_mmu_params.mmu_egr_pg_dyn_thd_param; 14408 } 14409 if ((buf_queue->pkt_pool_scale != -1) && 14410 mmu_config_enabled) { 14411 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_QENTRYm, 14412 &mmu_thdo_qconfig_qentry_entry, Q_LIMIT_DYNAMIC_QENTRYf, 14413 1); 14414 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_QENTRYm, 14415 &mmu_thdo_qconfig_qentry_entry, Q_SHARED_LIMIT_QENTRYf, 14416 buf_queue->pkt_pool_scale); 14417 } else { 14418 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_QENTRYm, 14419 &mmu_thdo_qconfig_qentry_entry, Q_SHARED_LIMIT_QENTRYf, temp_val); 14420 14421 /* C476:THDO_QCONFIG_QENTRY.Q_LIMIT_DYNAMIC_QENTRY 14422 =IF($C$14, 0, 1) */ 14423 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_QENTRYm, 14424 &mmu_thdo_qconfig_qentry_entry, Q_LIMIT_DYNAMIC_QENTRYf, 14425 _soc_kt2_mmu_params.lossless_mode_d_c ? 0 : 1); 14426 } 14427 14428 /* C477:THDO_QCONFIG_QENTRY.Q_LIMIT_ENABLE_QENTRY 14429 =IF($C$14, 0, 1) */ 14430 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_QENTRYm, 14431 &mmu_thdo_qconfig_qentry_entry, Q_LIMIT_ENABLE_QENTRYf, 14432 _soc_kt2_mmu_params.lossless_mode_d_c ? 0 : 1); 14433 14434 /* C478:THDO_QCONFIG_QENTRY.Q_COLOR_ENABLE_QENTRY = 0 */ 14435 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_QENTRYm, 14436 &mmu_thdo_qconfig_qentry_entry, Q_COLOR_ENABLE_QENTRYf,0); 14437 14438 /* C479: THDO_QCONFIG_QENTRY.Q_COLOR_LIMIT_DYNAMIC_QENTRY 14439 =IF($C$14, 0, 1) */ 14440 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_QENTRYm, 14441 &mmu_thdo_qconfig_qentry_entry, 14442 Q_COLOR_LIMIT_DYNAMIC_QENTRYf, 14443 _soc_kt2_mmu_params.lossless_mode_d_c ? 0 : 1); 14444 14445 /* C480: THDO_QCONFIG_QENTRY.LIMIT_YELLOW_QENTRY= 14446 if lossless= C474/8 else C474 */ 14447 temp_val = soc_mem_field32_get(unit, MMU_THDO_QCONFIG_QENTRYm, 14448 &mmu_thdo_qconfig_qentry_entry, Q_SHARED_LIMIT_QENTRYf); 14449 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_QENTRYm, 14450 &mmu_thdo_qconfig_qentry_entry, LIMIT_YELLOW_QENTRYf, 14451 _soc_kt2_mmu_params.lossless_mode_d_c ? 14452 ceil_func(temp_val, 8) : temp_val); 14453 SOC_IF_ERROR_RETURN(WRITE_MMU_THDO_QCONFIG_QENTRYm(unit, 14454 MEM_BLOCK_ALL,queue, 14455 &mmu_thdo_qconfig_qentry_entry)); 14456 14457 SOC_IF_ERROR_RETURN(READ_MMU_THDO_QOFFSET_QENTRYm(unit, 14458 MEM_BLOCK_ANY,queue, 14459 &mmu_thdo_qoffset_qentry_entry)); 14460 /* C475:THDO_QOFFSET_QENTRY.RESET_OFFSET_QENTRY =1 */ 14461 soc_mem_field32_set(unit, MMU_THDO_QOFFSET_QENTRYm, 14462 &mmu_thdo_qoffset_qentry_entry, RESET_OFFSET_QENTRYf, 1); 14463 14464 /* C481: THDO_QOFFSET_QENTRY.LIMIT_RED_QENTRY = 14465 if lossless= C474/8 else C474 */ 14466 temp_val = soc_mem_field32_get(unit, MMU_THDO_QCONFIG_QENTRYm, 14467 &mmu_thdo_qconfig_qentry_entry, Q_SHARED_LIMIT_QENTRYf); 14468 soc_mem_field32_set(unit, MMU_THDO_QOFFSET_QENTRYm, 14469 &mmu_thdo_qoffset_qentry_entry, LIMIT_RED_QENTRYf, 14470 _soc_kt2_mmu_params.lossless_mode_d_c ? 14471 ceil_func(temp_val, 8) : temp_val); 14472 14473 /* C482: THDO_QOFFSET_QENTRY.RESET_OFFSET_YELLOW_QENTRY =1 */ 14474 soc_mem_field32_set(unit, MMU_THDO_QOFFSET_QENTRYm, 14475 &mmu_thdo_qoffset_qentry_entry,RESET_OFFSET_YELLOW_QENTRYf,1); 14476 /* C483: THDO_QOFFSET_QENTRY.RESET_OFFSET_RED_QENTRY =1 */ 14477 soc_mem_field32_set(unit, MMU_THDO_QOFFSET_QENTRYm, 14478 &mmu_thdo_qoffset_qentry_entry, RESET_OFFSET_RED_QENTRYf,1); 14479 14480 SOC_IF_ERROR_RETURN(WRITE_MMU_THDO_QOFFSET_QENTRYm(unit, 14481 MEM_BLOCK_ALL,queue, 14482 &mmu_thdo_qoffset_qentry_entry)); 14483 } 14484 } 14485 /* 2.5 Redirect Port */ 14486 /* 2.5.1 RDEQ */ 14487 for(cos=0; cos<SOC_REG_NUMELS(unit, OP_QUEUE_CONFIG1_THDORDEQr); cos++) { 14488 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_CONFIG1_THDORDEQr( 14489 unit, cos, &rval)); 14490 /* C485:OP_QUEUE_CONFIG1_THDORDEQ.Q_MIN = 9 (C205) */ 14491 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_THDORDEQr, &rval, 14492 Q_MINf, 9); 14493 /* output_port_threshold->min_grntd_res_RE_WQs_cells); */ 14494 14495 /* C490:OP_QUEUE_CONFIG1_THDORDEQ.Q_COLOR_ENABLE = 0 */ 14496 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_THDORDEQr, &rval, 14497 Q_COLOR_ENABLEf, 0); 14498 14499 /* C491:OP_QUEUE_CONFIG1_THDORDEQ.Q_COLOR_DYNAMIC = 1*/ 14500 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_THDORDEQr, &rval, 14501 Q_COLOR_DYNAMICf, 1); 14502 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_CONFIG1_THDORDEQr( 14503 unit, cos, rval)); 14504 } 14505 14506 for(cos=0; cos<SOC_REG_NUMELS(unit, OP_QUEUE_CONFIG_THDORDEQr); cos++) { 14507 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_CONFIG_THDORDEQr( 14508 unit, cos, &rval)); 14509 /* C486:OP_QUEUE_CONFIG_THDORDEQ.Q_SHARED_LIMIT = 7 */ 14510 soc_reg_field_set(unit, OP_QUEUE_CONFIG_THDORDEQr, &rval, 14511 Q_SHARED_LIMITf, 7); 14512 14513 /*C488: OP_QUEUE_CONFIG_THDORDEQ.Q_LIMIT_DYNAMIC:=1 */ 14514 14515 soc_reg_field_set(unit, OP_QUEUE_CONFIG_THDORDEQr, &rval, 14516 Q_LIMIT_DYNAMICf,1); 14517 14518 /*C489:OP_QUEUE_CONFIG_THDORDEQ.Q_LIMIT_ENABLE:=0 */ 14519 soc_reg_field_set(unit, OP_QUEUE_CONFIG_THDORDEQr, &rval, 14520 Q_LIMIT_ENABLEf, 0); 14521 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_CONFIG_THDORDEQr( 14522 unit, cos, rval)); 14523 } 14524 for(cos=0; 14525 cos<SOC_REG_NUMELS(unit, OP_QUEUE_RESET_OFFSET_THDORDEQr); cos++) { 14526 SOC_IF_ERROR_RETURN( 14527 READ_OP_QUEUE_RESET_OFFSET_THDORDEQr(unit, cos,&rval)); 14528 /*C487: OP_QUEUE_RESET_OFFSET_THDORDEQ.Q_RESET_OFFSET == 1 */ 14529 soc_reg_field_set(unit, OP_QUEUE_RESET_OFFSET_THDORDEQr, &rval, 14530 Q_RESET_OFFSETf, 1); 14531 SOC_IF_ERROR_RETURN( 14532 WRITE_OP_QUEUE_RESET_OFFSET_THDORDEQr(unit, cos,rval)); 14533 } 14534 for(cos=0; 14535 cos<SOC_REG_NUMELS(unit, OP_QUEUE_LIMIT_YELLOW_THDORDEQr); 14536 cos++) { 14537 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_LIMIT_YELLOW_THDORDEQr( 14538 unit, cos,&rval)); 14539 /* C492: OP_QUEUE_LIMIT_YELLOW_THDORDEQ.Q_LIMIT_YELLOW = C486 ==>7 */ 14540 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_CONFIG_THDORDEQr( 14541 unit, cos, &rval)); 14542 temp_val = soc_reg_field_get(unit, OP_QUEUE_CONFIG_THDORDEQr, rval, 14543 Q_SHARED_LIMITf); 14544 14545 soc_reg_field_set(unit, OP_QUEUE_LIMIT_YELLOW_THDORDEQr, &rval, 14546 Q_LIMIT_YELLOWf, temp_val); 14547 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_LIMIT_YELLOW_THDORDEQr( 14548 unit, cos,rval)); 14549 } 14550 for(cos=0; 14551 cos<SOC_REG_NUMELS(unit, OP_QUEUE_LIMIT_RED_THDORDEQr); 14552 cos++) { 14553 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_LIMIT_RED_THDORDEQr( 14554 unit, cos,&rval)); 14555 /* C493: OP_QUEUE_LIMIT_RED_THDORDEQ.Q_LIMIT_RED = C486 */ 14556 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_CONFIG_THDORDEQr( 14557 unit, cos, &rval)); 14558 temp_val = soc_reg_field_get(unit, OP_QUEUE_CONFIG_THDORDEQr, rval, 14559 Q_SHARED_LIMITf); 14560 14561 soc_reg_field_set(unit, OP_QUEUE_LIMIT_RED_THDORDEQr, &rval, 14562 Q_LIMIT_REDf, temp_val); 14563 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_LIMIT_RED_THDORDEQr( 14564 unit, cos,rval)); 14565 } 14566 for(cos=0; 14567 cos < SOC_REG_NUMELS(unit, OP_QUEUE_RESET_OFFSET_YELLOW_THDORDEQr); 14568 cos++) { 14569 SOC_IF_ERROR_RETURN( 14570 READ_OP_QUEUE_RESET_OFFSET_YELLOW_THDORDEQr(unit, cos,&rval)); 14571 /*C494:OP_QUEUE_RESET_OFFSET_YELLOW_THDORDEQ.RESUME_OFFSET_YELLOW=1*/ 14572 soc_reg_field_set(unit, 14573 OP_QUEUE_RESET_OFFSET_YELLOW_THDORDEQr, &rval, 14574 RESUME_OFFSET_YELLOWf, 1); 14575 SOC_IF_ERROR_RETURN( 14576 WRITE_OP_QUEUE_RESET_OFFSET_YELLOW_THDORDEQr(unit, cos,rval)); 14577 } 14578 for(cos=0; 14579 cos < SOC_REG_NUMELS(unit, OP_QUEUE_RESET_OFFSET_RED_THDORDEQr); 14580 cos++) { 14581 SOC_IF_ERROR_RETURN( 14582 READ_OP_QUEUE_RESET_OFFSET_RED_THDORDEQr(unit, cos,&rval)); 14583 /*C495:OP_QUEUE_RESET_OFFSET_RED_THDORDEQ.RESUME_OFFSET_RED=1*/ 14584 soc_reg_field_set(unit, 14585 OP_QUEUE_RESET_OFFSET_RED_THDORDEQr, &rval, 14586 RESUME_OFFSET_REDf, 1); 14587 SOC_IF_ERROR_RETURN( 14588 WRITE_OP_QUEUE_RESET_OFFSET_RED_THDORDEQr(unit, cos,rval)); 14589 } 14590 /* 2.5.2 RDEI */ 14591 for(cos=0; cos<SOC_REG_NUMELS(unit, OP_QUEUE_CONFIG1_THDORDEIr); cos++) { 14592 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_CONFIG1_THDORDEIr( 14593 unit, cos, &rval)); 14594 /* C496:OP_QUEUE_CONFIG1_THDORDEI.Q_MIN = 9 (C206) */ 14595 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_THDORDEIr, &rval, Q_MINf, 14596 _soc_kt2_mmu_params.lossless_mode_d_c? 9 : 14597 output_port_threshold->min_grntd_res_RE_WQs_queue_cells_for_int_buff); 14598 14599 /* C501:OP_QUEUE_CONFIG1_THDORDEI.Q_COLOR_ENABLE = 0 */ 14600 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_THDORDEIr, &rval, 14601 Q_COLOR_ENABLEf, 0); 14602 14603 /* C491:OP_QUEUE_CONFIG1_THDORDEI.Q_COLOR_DYNAMIC = 1*/ 14604 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_THDORDEIr, &rval, 14605 Q_COLOR_DYNAMICf, 1); 14606 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_CONFIG1_THDORDEIr( 14607 unit, cos, rval)); 14608 } 14609 14610 for(cos=0; cos<SOC_REG_NUMELS(unit, OP_QUEUE_CONFIG_THDORDEIr); cos++) { 14611 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_CONFIG_THDORDEIr( 14612 unit, cos, &rval)); 14613 /* C497:OP_QUEUE_CONFIG_THDORDEI.Q_SHARED_LIMIT = 7 */ 14614 soc_reg_field_set(unit, OP_QUEUE_CONFIG_THDORDEIr, &rval, 14615 Q_SHARED_LIMITf, 7); 14616 14617 /*C499: OP_QUEUE_CONFIG_THDORDEI.Q_LIMIT_DYNAMIC:=1 */ 14618 14619 soc_reg_field_set(unit, OP_QUEUE_CONFIG_THDORDEIr, &rval, 14620 Q_LIMIT_DYNAMICf,1); 14621 14622 /*C500:OP_QUEUE_CONFIG_THDORDEI.Q_LIMIT_ENABLE:=0 */ 14623 soc_reg_field_set(unit, OP_QUEUE_CONFIG_THDORDEIr, &rval, 14624 Q_LIMIT_ENABLEf, 0); 14625 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_CONFIG_THDORDEIr( 14626 unit, cos, rval)); 14627 } 14628 for(cos=0; 14629 cos<SOC_REG_NUMELS(unit, OP_QUEUE_RESET_OFFSET_THDORDEIr); cos++) { 14630 SOC_IF_ERROR_RETURN( 14631 READ_OP_QUEUE_RESET_OFFSET_THDORDEIr(unit, cos,&rval)); 14632 /*C498: OP_QUEUE_RESET_OFFSET_THDORDEI.Q_RESET_OFFSET == 2 */ 14633 soc_reg_field_set(unit, OP_QUEUE_RESET_OFFSET_THDORDEIr, &rval, 14634 Q_RESET_OFFSETf, 2); 14635 SOC_IF_ERROR_RETURN( 14636 WRITE_OP_QUEUE_RESET_OFFSET_THDORDEIr(unit, cos,rval)); 14637 } 14638 for(cos=0; 14639 cos<SOC_REG_NUMELS(unit, OP_QUEUE_LIMIT_YELLOW_THDORDEIr); 14640 cos++) { 14641 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_LIMIT_YELLOW_THDORDEIr( 14642 unit, cos,&rval)); 14643 /* C503: OP_QUEUE_LIMIT_YELLOW_THDORDEI.Q_LIMIT_YELLOW = C497 ==>7 */ 14644 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_CONFIG_THDORDEIr( 14645 unit, cos, &rval)); 14646 temp_val = soc_reg_field_get(unit, OP_QUEUE_CONFIG_THDORDEIr, rval, 14647 Q_SHARED_LIMITf); 14648 14649 soc_reg_field_set(unit, OP_QUEUE_LIMIT_YELLOW_THDORDEIr, &rval, 14650 Q_LIMIT_YELLOWf, temp_val); 14651 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_LIMIT_YELLOW_THDORDEIr( 14652 unit, cos,rval)); 14653 } 14654 for(cos=0; 14655 cos<SOC_REG_NUMELS(unit, OP_QUEUE_LIMIT_RED_THDORDEIr); 14656 cos++) { 14657 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_LIMIT_RED_THDORDEIr( 14658 unit, cos,&rval)); 14659 /* C504: OP_QUEUE_LIMIT_RED_THDORDEI.Q_LIMIT_RED = C497 */ 14660 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_CONFIG_THDORDEIr( 14661 unit, cos, &rval)); 14662 temp_val = soc_reg_field_get(unit, OP_QUEUE_CONFIG_THDORDEIr, rval, 14663 Q_SHARED_LIMITf); 14664 14665 soc_reg_field_set(unit, OP_QUEUE_LIMIT_RED_THDORDEIr, &rval, 14666 Q_LIMIT_REDf, temp_val); 14667 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_LIMIT_RED_THDORDEIr( 14668 unit, cos,rval)); 14669 } 14670 for(cos=0; 14671 cos < SOC_REG_NUMELS(unit, OP_QUEUE_RESET_OFFSET_YELLOW_THDORDEIr); 14672 cos++) { 14673 SOC_IF_ERROR_RETURN( 14674 READ_OP_QUEUE_RESET_OFFSET_YELLOW_THDORDEIr(unit, cos,&rval)); 14675 /*C505:OP_QUEUE_RESET_OFFSET_YELLOW_THDORDEI.RESUME_OFFSET_YELLOW=2*/ 14676 soc_reg_field_set(unit, 14677 OP_QUEUE_RESET_OFFSET_YELLOW_THDORDEIr, &rval, 14678 RESUME_OFFSET_YELLOWf, 2); 14679 SOC_IF_ERROR_RETURN( 14680 WRITE_OP_QUEUE_RESET_OFFSET_YELLOW_THDORDEIr(unit, cos,rval)); 14681 } 14682 for(cos=0; 14683 cos < SOC_REG_NUMELS(unit, OP_QUEUE_RESET_OFFSET_RED_THDORDEIr); 14684 cos++) { 14685 SOC_IF_ERROR_RETURN( 14686 READ_OP_QUEUE_RESET_OFFSET_RED_THDORDEIr(unit, cos,&rval)); 14687 /*C506:OP_QUEUE_RESET_OFFSET_RED_THDORDEI.RESUME_OFFSET_RED=2*/ 14688 soc_reg_field_set(unit, 14689 OP_QUEUE_RESET_OFFSET_RED_THDORDEIr, &rval, 14690 RESUME_OFFSET_REDf, 2); 14691 SOC_IF_ERROR_RETURN( 14692 WRITE_OP_QUEUE_RESET_OFFSET_RED_THDORDEIr(unit, cos,rval)); 14693 } 14694 14695 /* 2.5.2 RDEE */ 14696 if ((ext_mem_port_count) || (_soc_kt2_mmu_params.packing_mode_d_c)) { 14697 for(cos=0; cos<SOC_REG_NUMELS(unit, OP_QUEUE_CONFIG1_THDORDEEr); cos++) { 14698 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_CONFIG1_THDORDEEr( 14699 unit, cos, &rval)); 14700 /* C507:OP_QUEUE_CONFIG1_THDORDEE.Q_MIN = lossless=9 lossy:C485*/ 14701 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_THDORDEEr, &rval, Q_MINf, 14702 _soc_kt2_mmu_params.lossless_mode_d_c? 9 : 14703 output_port_threshold->min_grntd_res_RE_WQs_cells); 14704 14705 /* C512:OP_QUEUE_CONFIG1_THDORDEE.Q_COLOR_ENABLE = 0 */ 14706 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_THDORDEEr, &rval, 14707 Q_COLOR_ENABLEf, 0); 14708 14709 /* C513:OP_QUEUE_CONFIG1_THDORDEE.Q_COLOR_DYNAMIC = 1*/ 14710 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_THDORDEEr, &rval, 14711 Q_COLOR_DYNAMICf, 1); 14712 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_CONFIG1_THDORDEEr( 14713 unit, cos, rval)); 14714 } 14715 14716 for(cos=0; cos<SOC_REG_NUMELS(unit, OP_QUEUE_CONFIG_THDORDEEr); cos++) { 14717 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_CONFIG_THDORDEEr( 14718 unit, cos, &rval)); 14719 /* C508:OP_QUEUE_CONFIG_THDORDEE.Q_SHARED_LIMIT = 7 */ 14720 soc_reg_field_set(unit, OP_QUEUE_CONFIG_THDORDEEr, &rval, 14721 Q_SHARED_LIMITf, 7); 14722 14723 /*C510: OP_QUEUE_CONFIG_THDORDEE.Q_LIMIT_DYNAMIC:=1 */ 14724 14725 soc_reg_field_set(unit, OP_QUEUE_CONFIG_THDORDEEr, &rval, 14726 Q_LIMIT_DYNAMICf,1); 14727 14728 /*C511:OP_QUEUE_CONFIG_THDORDEE.Q_LIMIT_ENABLE:=0 */ 14729 soc_reg_field_set(unit, OP_QUEUE_CONFIG_THDORDEEr, &rval, 14730 Q_LIMIT_ENABLEf, 0); 14731 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_CONFIG_THDORDEEr( 14732 unit, cos, rval)); 14733 } 14734 for(cos=0; 14735 cos<SOC_REG_NUMELS(unit, OP_QUEUE_RESET_OFFSET_THDORDEEr); cos++) { 14736 SOC_IF_ERROR_RETURN( 14737 READ_OP_QUEUE_RESET_OFFSET_THDORDEEr(unit, cos,&rval)); 14738 /*C509:OP_QUEUE_RESET_OFFSET_THDORDEE.Q_RESET_OFFSETlossless=2 else 1 */ 14739 soc_reg_field_set(unit, OP_QUEUE_RESET_OFFSET_THDORDEEr, &rval, 14740 Q_RESET_OFFSETf, 14741 _soc_kt2_mmu_params.lossless_mode_d_c? 2 : 1); 14742 SOC_IF_ERROR_RETURN( 14743 WRITE_OP_QUEUE_RESET_OFFSET_THDORDEEr(unit, cos,rval)); 14744 } 14745 for(cos=0; 14746 cos<SOC_REG_NUMELS(unit, OP_QUEUE_LIMIT_YELLOW_THDORDEEr); 14747 cos++) { 14748 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_LIMIT_YELLOW_THDORDEEr( 14749 unit, cos,&rval)); 14750 /* C514: OP_QUEUE_LIMIT_YELLOW_THDORDEE.Q_LIMIT_YELLOW = 7 */ 14751 14752 soc_reg_field_set(unit, OP_QUEUE_LIMIT_YELLOW_THDORDEEr, &rval, 14753 Q_LIMIT_YELLOWf, 7); 14754 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_LIMIT_YELLOW_THDORDEEr( 14755 unit, cos,rval)); 14756 } 14757 for(cos=0; 14758 cos<SOC_REG_NUMELS(unit, OP_QUEUE_LIMIT_RED_THDORDEEr); 14759 cos++) { 14760 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_LIMIT_RED_THDORDEEr( 14761 unit, cos,&rval)); 14762 /* C515: OP_QUEUE_LIMIT_RED_THDORDEE.Q_LIMIT_RED = 7 */ 14763 soc_reg_field_set(unit, OP_QUEUE_LIMIT_RED_THDORDEEr, &rval, 14764 Q_LIMIT_REDf, 7); 14765 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_LIMIT_RED_THDORDEEr( 14766 unit, cos,rval)); 14767 } 14768 for(cos=0; 14769 cos < SOC_REG_NUMELS(unit, OP_QUEUE_RESET_OFFSET_YELLOW_THDORDEEr); 14770 cos++) { 14771 SOC_IF_ERROR_RETURN( 14772 READ_OP_QUEUE_RESET_OFFSET_YELLOW_THDORDEEr(unit, cos,&rval)); 14773 /*C516:OP_QUEUE_RESET_OFFSET_YELLOW_THDORDEE.RESUME_OFFSET_YELLOW=2*/ 14774 soc_reg_field_set(unit, 14775 OP_QUEUE_RESET_OFFSET_YELLOW_THDORDEEr, &rval, 14776 RESUME_OFFSET_YELLOWf, 2); 14777 SOC_IF_ERROR_RETURN( 14778 WRITE_OP_QUEUE_RESET_OFFSET_YELLOW_THDORDEEr(unit, cos,rval)); 14779 } 14780 for(cos=0; 14781 cos < SOC_REG_NUMELS(unit, OP_QUEUE_RESET_OFFSET_RED_THDORDEEr); 14782 cos++) { 14783 SOC_IF_ERROR_RETURN( 14784 READ_OP_QUEUE_RESET_OFFSET_RED_THDORDEEr(unit, cos,&rval)); 14785 /*C517:OP_QUEUE_RESET_OFFSET_RED_THDORDEE.RESUME_OFFSET_RED=2*/ 14786 soc_reg_field_set(unit, 14787 OP_QUEUE_RESET_OFFSET_RED_THDORDEEr, &rval, 14788 RESUME_OFFSET_REDf, 2); 14789 SOC_IF_ERROR_RETURN( 14790 WRITE_OP_QUEUE_RESET_OFFSET_RED_THDORDEEr(unit, cos,rval)); 14791 } 14792 } 14793 /* Enable back pressure status from MMU for lossless mode */ 14794 if (_soc_kt2_mmu_params.lossless_mode_d_c) { 14795 COMPILER_64_SET(val64, 0x3ff, 0xfffffffe); /* 0 to 41 ports */ 14796 COMPILER_64_ZERO(r64val); 14797 soc_reg64_field_set(unit, THDIEXT_PORT_PAUSE_ENABLE_64r, &r64val, 14798 PORT_PAUSE_ENABLEf, val64); 14799 SOC_IF_ERROR_RETURN(WRITE_THDIEXT_PORT_PAUSE_ENABLE_64r( 14800 unit, r64val)); 14801 14802 COMPILER_64_ZERO(r64val); 14803 soc_reg64_field_set(unit, THDIQEN_PORT_PAUSE_ENABLE_64r, &r64val, 14804 PORT_PAUSE_ENABLEf, val64); 14805 SOC_IF_ERROR_RETURN(WRITE_THDIQEN_PORT_PAUSE_ENABLE_64r(unit, r64val)); 14806 14807 COMPILER_64_ZERO(r64val); 14808 soc_reg64_field_set(unit, THDIRQE_PORT_PAUSE_ENABLE_64r, &r64val, 14809 PORT_PAUSE_ENABLEf, val64); 14810 SOC_IF_ERROR_RETURN(WRITE_THDIRQE_PORT_PAUSE_ENABLE_64r(unit, r64val)); 14811 14812 COMPILER_64_ZERO(r64val); 14813 soc_reg64_field_set(unit, THDIEMA_PORT_PAUSE_ENABLE_64r, &r64val, 14814 PORT_PAUSE_ENABLEf, val64); 14815 SOC_IF_ERROR_RETURN(WRITE_THDIEMA_PORT_PAUSE_ENABLE_64r(unit, r64val)); 14816 14817 COMPILER_64_ZERO(r64val); 14818 soc_reg64_field_set(unit, PORT_PAUSE_ENABLE_64r, &r64val, 14819 PORT_PAUSE_ENABLEf, val64); 14820 SOC_IF_ERROR_RETURN(WRITE_PORT_PAUSE_ENABLE_64r(unit, r64val)); 14821 } 14822 14823 /* ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ 14824 /* OpNode related config for remaining OpNodes */ 14825 /* (assuming internal memory settings) */ 14826 /* ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ 14827 for (op_node = soc_mem_index_min(unit,MMU_THDO_OPNCONFIG_CELLm); 14828 op_node <= soc_mem_index_max(unit,MMU_THDO_OPNCONFIG_CELLm); 14829 op_node++) { 14830 temp_val = 0 ; /* Not required but */ 14831 SOC_IF_ERROR_RETURN(READ_MMU_THDO_OPNCONFIG_CELLm(unit, 14832 MEM_BLOCK_ANY,op_node , 14833 &mmu_thdo_opnconfig_cell_entry)); 14834 temp_val = soc_mem_field32_get(unit, MMU_THDO_OPNCONFIG_CELLm, 14835 &mmu_thdo_opnconfig_cell_entry, 14836 OPN_SHARED_LIMIT_CELLf); 14837 if (temp_val == 0) { 14838 /* Empty Entry */ 14839 /* C394:THDO_OPNCONFIG_CELL.OPN_SHARED_LIMIT_CELL = =$C$219 */ 14840 soc_mem_field32_set(unit, MMU_THDO_OPNCONFIG_CELLm, 14841 &mmu_thdo_opnconfig_cell_entry, 14842 OPN_SHARED_LIMIT_CELLf, 14843 output_port_threshold-> 14844 min_grntd_tot_shr_queue_cells_int_buff); 14845 /* C395:THDO_OPNCONFIG_CELL.OP_SHARED_RESET_VALUE_CELL 14846 = C394-2*$C$72 */ 14847 temp_val = output_port_threshold-> 14848 min_grntd_tot_shr_queue_cells_int_buff - 14849 (2 * general_info->ether_mtu_cells_for_int_buff); 14850 soc_mem_field32_set(unit, MMU_THDO_OPNCONFIG_CELLm, 14851 &mmu_thdo_opnconfig_cell_entry, 14852 OPN_SHARED_RESET_VALUE_CELLf, temp_val); 14853 /* C396:THDO_OPNCONFIG_CELL.PORT_LIMIT_ENABLE_CELL 14854 = 0 */ 14855 soc_mem_field32_set(unit, MMU_THDO_OPNCONFIG_CELLm, 14856 &mmu_thdo_opnconfig_cell_entry, 14857 PORT_LIMIT_ENABLE_CELLf, 0); 14858 /* 14859 soc_mem_field32_set(unit, MMU_THDO_OPNCONFIG_CELLm, 14860 &mmu_thdo_opnconfig_cell_entry, 14861 PIDf, port); 14862 */ 14863 SOC_IF_ERROR_RETURN(WRITE_MMU_THDO_OPNCONFIG_CELLm(unit, 14864 MEM_BLOCK_ALL,op_node, 14865 &mmu_thdo_opnconfig_cell_entry)); 14866 } 14867 } 14868 for (op_node = soc_mem_index_min(unit,MMU_THDO_OPNCONFIG_QENTRYm); 14869 op_node <= soc_mem_index_max(unit,MMU_THDO_OPNCONFIG_QENTRYm); 14870 op_node++) { 14871 temp_val = 0 ; /* Not required but */ 14872 SOC_IF_ERROR_RETURN(READ_MMU_THDO_OPNCONFIG_QENTRYm(unit, 14873 MEM_BLOCK_ANY,op_node , 14874 &mmu_thdo_opnconfig_qentry_entry)); 14875 /* C470:THDO_OPNCONFIG_QENTRY.OPN_SHARED_LIMIT_QENTRY = =$C$221 */ 14876 temp_val = soc_mem_field32_get(unit, MMU_THDO_OPNCONFIG_QENTRYm, 14877 &mmu_thdo_opnconfig_qentry_entry, 14878 OPN_SHARED_LIMIT_QENTRYf); 14879 if (temp_val == 0) { 14880 /* Empty Entry */ 14881 /* C470:THDO_OPNCONFIG_QENTRY.OPN_SHARED_LIMIT_QENTRY = =$C$221 */ 14882 soc_mem_field32_set(unit, MMU_THDO_OPNCONFIG_QENTRYm, 14883 &mmu_thdo_opnconfig_qentry_entry, OPN_SHARED_LIMIT_QENTRYf, 14884 output_port_threshold->min_grntd_tot_shr_queue_cells_EQEs); 14885 14886 /* C471:THDO_OPNCONFIG_QENTRY.OP_SHARED_RESET_VALUE_QENTRY 14887 = =$C$470 -2 */ 14888 temp_val = output_port_threshold-> 14889 min_grntd_tot_shr_queue_cells_EQEs - 2; 14890 soc_mem_field32_set(unit, MMU_THDO_OPNCONFIG_QENTRYm, 14891 &mmu_thdo_opnconfig_qentry_entry, 14892 OPN_SHARED_RESET_VALUE_QENTRYf, temp_val); 14893 14894 /* C472:THDO_OPNCONFIG_QENTRY.PORT_LIMIT_ENABLE_QENTRY 14895 = 0 */ 14896 soc_mem_field32_set(unit, MMU_THDO_OPNCONFIG_QENTRYm, 14897 &mmu_thdo_opnconfig_qentry_entry, 14898 PORT_LIMIT_ENABLE_QENTRYf, 0); 14899 /* 14900 soc_mem_field32_set(unit, MMU_THDO_OPNCONFIG_QENTRYm, 14901 &mmu_thdo_opnconfig_qentry_entry, 14902 PIDf, port); 14903 */ 14904 SOC_IF_ERROR_RETURN(WRITE_MMU_THDO_OPNCONFIG_QENTRYm(unit, 14905 MEM_BLOCK_ALL,op_node , 14906 &mmu_thdo_opnconfig_qentry_entry)); 14907 } 14908 } 14909 /* ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ 14910 /* Subport queue Settings */ 14911 /* (Assuming lossless-internal memory operation) */ 14912 /* ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ 14913 for (sub_port = SOC_KT2_MIN_SUBPORT_INDEX; 14914 sub_port <= SOC_KT2_MAX_SUBPORT_INDEX; 14915 sub_port ++) { 14916 if ( si->port_uc_cosq_base[sub_port] != 0) { 14917 for (queue = si->port_uc_cosq_base[sub_port]; 14918 queue < si->port_uc_cosq_base[sub_port] + 14919 si->port_num_uc_cosq[sub_port]; 14920 queue++) { 14921 LOG_VERBOSE(BSL_LS_SOC_COMMON, 14922 (BSL_META_U(unit, 14923 "sub_port:%d queue:%d"), sub_port, queue)); 14924 SOC_IF_ERROR_RETURN(_soc_katana2_mmu_config_extra_queue( 14925 unit, queue)); 14926 } 14927 } 14928 } 14929 /* ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ 14930 /* Extended Queue(BCM_COSQ_GPORT_SUBSCRIBE) Settings */ 14931 /* (Assuming lossless-internal memory operation) */ 14932 /* ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ 14933 for (queue = si->port_uc_cosq_base[KT2_MAX_PHYSICAL_PORTS] + 14934 si->port_num_uc_cosq[KT2_MAX_PHYSICAL_PORTS]; 14935 queue <= soc_mem_index_max(unit,MMU_THDO_QCONFIG_CELLm); 14936 queue++) { 14937 SOC_IF_ERROR_RETURN(_soc_katana2_mmu_config_extra_queue(unit, queue)); 14938 } 14939 soc_mmu_cfg_free(unit, buf); 14940 14941 return SOC_E_NONE; 14942 } 14943 14944 14945 static 14946 void soc_katana2_save_tdm_pos(int unit, uint8 new_tdm_size,uint32 *new_tdm); 14947 void kt2_tdm_replace(uint32 *tdm, uint32 total_tdm_slots, 14948 uint32 src, uint32 dst,uint32 one_time) 14949 { 14950 uint32 index=0; 14951 for (index=0; index < total_tdm_slots ; index++ ) { 14952 if (tdm[index] == src) { 14953 tdm[index] = dst; 14954 if (one_time) { 14955 break; 14956 } 14957 } 14958 } 14959 } 14960 14961 void kt2_tdm_swap(uint32 *tdm, uint32 total_tdm_slots, 14962 uint32 src, uint32 dst) 14963 { 14964 uint32 index=0; 14965 uint32 temp_index=0; 14966 uint32 temp=0; 14967 for (index=0; index < total_tdm_slots ; index++ ) { 14968 if (tdm[index] == src) { 14969 temp_index=index; 14970 } 14971 if (tdm[index] == dst) { 14972 temp = tdm[temp_index]; 14973 tdm[temp_index]=dst; 14974 tdm[index]=temp; 14975 } 14976 } 14977 } 14978 14979 int 14980 soc_katana2_pipe_mem_clear(int unit) 14981 { 14982 uint32 rval; 14983 int index, pipe_init_usec; 14984 soc_timeout_t to; 14985 14986 static const soc_mem_t cam[] = { 14987 MY_STATION_TCAMm, 14988 L2_USER_ENTRYm, 14989 VLAN_SUBNETm, 14990 L3_DEFIP_PAIR_128m, 14991 L3_DEFIPm, 14992 CPU_COS_MAPm, 14993 EFP_TCAMm, 14994 FP_TCAMm, 14995 VFP_TCAMm, 14996 FP_UDF_TCAMm, 14997 SUBPORT_TAG_TO_PP_PORT_MAPm, 14998 L3_TUNNELm, 14999 FP_GLOBAL_MASK_TCAMm, 15000 }; 15001 /* 15002 * Reset the IPIPE and EPIPE block 15003 */ 15004 rval = 0; 15005 SOC_IF_ERROR_RETURN(WRITE_ING_HW_RESET_CONTROL_1r(unit, rval)); 15006 soc_reg_field_set(unit, ING_HW_RESET_CONTROL_2r, &rval, RESET_ALLf, 1); 15007 soc_reg_field_set(unit, ING_HW_RESET_CONTROL_2r, &rval, VALIDf, 1); 15008 /* Set count to # entries in largest IPIPE table (L2X) */ 15009 soc_reg_field_set(unit, ING_HW_RESET_CONTROL_2r, &rval, COUNTf, 32768); 15010 SOC_IF_ERROR_RETURN(WRITE_ING_HW_RESET_CONTROL_2r(unit, rval)); 15011 15012 rval = 0; 15013 SOC_IF_ERROR_RETURN(WRITE_EGR_HW_RESET_CONTROL_0r(unit, rval)); 15014 15015 rval = 0; 15016 SOC_IF_ERROR_RETURN(READ_EGR_HW_RESET_CONTROL_1r (unit, &rval)); 15017 soc_reg_field_set(unit, EGR_HW_RESET_CONTROL_1r, &rval, RESET_ALLf, 1); 15018 soc_reg_field_set(unit, EGR_HW_RESET_CONTROL_1r, &rval, VALIDf, 1); 15019 SOC_IF_ERROR_RETURN(WRITE_EGR_HW_RESET_CONTROL_1r(unit, rval)); 15020 15021 /* For simulation, set timeout to 10 sec. Otherwise, timeout = 50 ms */ 15022 if (SAL_BOOT_SIMULATION) { 15023 pipe_init_usec = 10000000; 15024 } else { 15025 pipe_init_usec = 50000; 15026 } 15027 soc_timeout_init(&to, pipe_init_usec, 0); 15028 15029 /* Wait for IPIPE memory initialization done. */ 15030 do { 15031 SOC_IF_ERROR_RETURN(READ_ING_HW_RESET_CONTROL_2r(unit, &rval)); 15032 if (soc_reg_field_get(unit, ING_HW_RESET_CONTROL_2r, rval, DONEf)) { 15033 break; 15034 } 15035 if (soc_timeout_check(&to)) { 15036 LOG_WARN(BSL_LS_SOC_COMMON, 15037 (BSL_META_U(unit, 15038 "unit %d : ING_HW_RESET timeout\n"), unit)); 15039 break; 15040 } 15041 } while (TRUE); 15042 15043 /* Wait for EPIPE memory initialization done. */ 15044 do { 15045 SOC_IF_ERROR_RETURN(READ_EGR_HW_RESET_CONTROL_1r(unit, &rval)); 15046 if (soc_reg_field_get(unit, EGR_HW_RESET_CONTROL_1r, rval, DONEf)) { 15047 break; 15048 } 15049 if (soc_timeout_check(&to)) { 15050 LOG_WARN(BSL_LS_SOC_COMMON, 15051 (BSL_META_U(unit, 15052 "unit %d : EGR_HW_RESET timeout\n"), unit)); 15053 break; 15054 } 15055 } while (TRUE); 15056 15057 SOC_IF_ERROR_RETURN(READ_ING_HW_RESET_CONTROL_2r(unit, &rval)); 15058 soc_reg_field_set(unit, ING_HW_RESET_CONTROL_2r, &rval, RESET_ALLf, 0); 15059 soc_reg_field_set(unit, ING_HW_RESET_CONTROL_2r, &rval, CMIC_REQ_ENABLEf, 1); 15060 SOC_IF_ERROR_RETURN(WRITE_ING_HW_RESET_CONTROL_2r(unit, rval)); 15061 15062 SOC_IF_ERROR_RETURN(READ_EGR_HW_RESET_CONTROL_1r(unit, &rval)); 15063 soc_reg_field_set(unit, EGR_HW_RESET_CONTROL_1r, &rval, RESET_ALLf, 0); 15064 SOC_IF_ERROR_RETURN(WRITE_EGR_HW_RESET_CONTROL_1r(unit, rval)); 15065 15066 for (index = 0; index < COUNTOF(cam); index++) { 15067 SOC_IF_ERROR_RETURN(soc_mem_clear(unit, cam[index], COPYNO_ALL, TRUE)); 15068 } 15069 return SOC_E_NONE; 15070 } 15071 15072 int soc_katana2_linkphy_mem_clear(int unit) 15073 { 15074 uint32 rval; 15075 int try_count = 0; 15076 int port = 1; 15077 int id; 15078 int block_idx; 15079 15080 soc_mem_t mem[32] = { 15081 RXLP_INTERNAL_STREAM_MAP_PORT_0m, 15082 RXLP_INTERNAL_STREAM_MAP_PORT_1m, 15083 RXLP_INTERNAL_STREAM_MAP_PORT_2m, 15084 RXLP_INTERNAL_STREAM_MAP_PORT_3m, 15085 TXLP_PORT_STREAM_BITMAP_TABLEm, 15086 TXLP_INT2EXT_STREAM_MAP_TABLEm, 15087 DEVICE_STREAM_ID_TO_PP_PORT_MAPm, 15088 PP_PORT_TO_PHYSICAL_PORT_MAPm, 15089 TXLP_DEBUG_COUNTER0m, 15090 TXLP_DEBUG_COUNTER1m, 15091 TXLP_DEBUG_COUNTER2m, 15092 TXLP_DEBUG_COUNTER3m, 15093 TXLP_DEBUG_COUNTER4m, 15094 TXLP_DEBUG_COUNTER5m, 15095 TXLP_DEBUG_COUNTER6m, 15096 TXLP_DEBUG_COUNTER7m, 15097 TXLP_DEBUG_COUNTER8m, 15098 TXLP_DEBUG_COUNTER9m, 15099 TXLP_DEBUG_COUNTER10m, 15100 TXLP_DEBUG_COUNTER11m, 15101 RXLP_DEBUG_COUNTER0m, 15102 RXLP_DEBUG_COUNTER1m, 15103 RXLP_DEBUG_COUNTER2m, 15104 RXLP_DEBUG_COUNTER3m, 15105 RXLP_DEBUG_COUNTER4m, 15106 RXLP_DEBUG_COUNTER5m, 15107 RXLP_DEBUG_COUNTER6m, 15108 RXLP_DEBUG_COUNTER7m, 15109 RXLP_DEBUG_COUNTER8m, 15110 RXLP_DEBUG_COUNTER9m, 15111 RXLP_DEBUG_COUNTER10m, 15112 RXLP_DEBUG_COUNTER11m}; 15113 15114 SOC_BLOCK_ITER(unit, block_idx, SOC_BLK_RXLP) { 15115 port = SOC_BLOCK_PORT(unit, block_idx); 15116 15117 SOC_IF_ERROR_RETURN(READ_RXLP_HW_RESET_CONTROLr(unit, port, &rval)); 15118 soc_reg_field_set(unit, RXLP_HW_RESET_CONTROLr, &rval, VALIDf, 1); 15119 soc_reg_field_set(unit, RXLP_HW_RESET_CONTROLr, &rval, START_ADDRESSf, 0); 15120 soc_reg_field_set(unit, RXLP_HW_RESET_CONTROLr, &rval, COUNTf, 0x7D0); 15121 SOC_IF_ERROR_RETURN(WRITE_RXLP_HW_RESET_CONTROLr(unit, port, rval)); 15122 15123 if((SAL_BOOT_BCMSIM || SAL_BOOT_PLISIM || SAL_BOOT_XGSSIM)) { 15124 SOC_IF_ERROR_RETURN(READ_RXLP_HW_RESET_CONTROLr(unit, port, &rval)); 15125 soc_reg_field_set(unit, RXLP_HW_RESET_CONTROLr, &rval, DONEf, 1); 15126 SOC_IF_ERROR_RETURN(WRITE_RXLP_HW_RESET_CONTROLr(unit, port, rval)); 15127 } 15128 15129 /* Now wait for HW to set DONEf */ 15130 do { 15131 SOC_IF_ERROR_RETURN(READ_RXLP_HW_RESET_CONTROLr(unit, port, &rval)); 15132 if (soc_reg_field_get(unit, RXLP_HW_RESET_CONTROLr, rval, DONEf) == 1) { 15133 break; 15134 } 15135 sal_usleep(1000); 15136 try_count++; 15137 } while(try_count < 3); 15138 15139 if (try_count == 3) { 15140 LOG_ERROR(BSL_LS_SOC_COMMON, (BSL_META_U(unit, "RXLP HW RESET Failed\n"))); 15141 return SOC_E_TIMEOUT; 15142 } 15143 } 15144 15145 SOC_BLOCK_ITER(unit, block_idx, SOC_BLK_TXLP) { 15146 port = SOC_BLOCK_PORT(unit, block_idx); 15147 SOC_IF_ERROR_RETURN(READ_TXLP_HW_RESET_CONTROL_1r(unit, port, &rval)); 15148 soc_reg_field_set(unit, TXLP_HW_RESET_CONTROL_1r, &rval, VALIDf, 1); 15149 soc_reg_field_set(unit, TXLP_HW_RESET_CONTROL_1r, &rval, COUNTf, 0x84); 15150 soc_reg_field_set(unit, TXLP_HW_RESET_CONTROL_1r, &rval, RESET_ALLf, 0x1); 15151 SOC_IF_ERROR_RETURN(WRITE_TXLP_HW_RESET_CONTROL_1r(unit, port, rval)); 15152 15153 if((SAL_BOOT_BCMSIM || SAL_BOOT_PLISIM || SAL_BOOT_XGSSIM)) { 15154 SOC_IF_ERROR_RETURN(READ_TXLP_HW_RESET_CONTROL_1r(unit, port, &rval)); 15155 soc_reg_field_set(unit, TXLP_HW_RESET_CONTROL_1r, &rval, DONEf, 1); 15156 SOC_IF_ERROR_RETURN(WRITE_TXLP_HW_RESET_CONTROL_1r(unit, port, rval)); 15157 } 15158 15159 /* Now wait for HW to set DONEf */ 15160 try_count = 0; 15161 do { 15162 SOC_IF_ERROR_RETURN(READ_TXLP_HW_RESET_CONTROL_1r(unit, port, &rval)); 15163 if (soc_reg_field_get(unit, TXLP_HW_RESET_CONTROL_1r, rval, DONEf) == 1) { 15164 break; 15165 } 15166 sal_usleep(1000); 15167 try_count++; 15168 } while(try_count < 3); 15169 15170 if (try_count == 3) { 15171 LOG_ERROR(BSL_LS_SOC_COMMON, (BSL_META_U(unit, "TXLP HW RESET Failed\n"))); 15172 return SOC_E_TIMEOUT; 15173 } 15174 } 15175 15176 for (id = 0; id < 32; id++) { 15177 SOC_IF_ERROR_RETURN(soc_mem_clear(unit, mem[id], COPYNO_ALL, TRUE)); 15178 } 15179 15180 return SOC_E_NONE; 15181 } 15182 soc_error_t kt2_tdm_verify(int unit, 15183 uint32 *tdm, 15184 uint32 total_tdm_slots, 15185 uint32 tdm_freq, /* In MHHz */ 15186 uint32 *port_speed, 15187 uint32 olp_port_flag, 15188 uint32 *offender_port) 15189 { 15190 /* Following rules need to be met */ 15191 /* Rule1 : Each Loopback port need 2.5G bandwidth */ 15192 /* Rule2 : Each CMIC port need 2G bandwidth */ 15193 /* Rule3 : Loopback (LPBK) ports require min 3 cycle spacing among LPBK or 15194 CMIC ports */ 15195 /* Rule4 : Each subport in MXQPORT operates with 4 cycle TDM */ 15196 /* Rule5 : Each 10G-XAUI ports should be able to operate in 4x2.5G with 4 15197 slots allocated to each subport from the same MXQPORT */ 15198 soc_error_t rv=SOC_E_NONE; 15199 uint32 index=0; 15200 uint32 expected_tdm_cycles_min=0; 15201 uint32 expected_tdm_cycles_max=0; 15202 uint32 tdm_freq_index=0; 15203 uint32 speed_index=0; 15204 uint32 port=0; 15205 uint32 speed=0; 15206 uint32 worse_tdm_slot_spacing=0; 15207 uint32 prev_tdm_slot_spacing=0; 15208 uint32 next_tdm_slot_spacing=0; 15209 uint32 tdm_slot_spacing=0; 15210 uint32 min_tdm_cycles=0; /* To Meet BW */ 15211 uint32 count=0; 15212 uint32 skip_count=0; 15213 uint32 mxqblock=0; 15214 uint32 outer_port=0; 15215 uint32 inner_port=0; 15216 uint32 spacing=0; 15217 uint32 loop=0; 15218 tdm_port_slots_info_t *head=NULL; 15219 tdm_port_slots_info_t *head1=NULL; 15220 tdm_port_slots_info_t *current=NULL; 15221 tdm_port_slots_info_t *current1=NULL; 15222 tdm_port_slots_info_t *prev = NULL; 15223 tdm_port_slots_info_t *temp=NULL; 15224 uint32 idle_flag=0; 15225 uint32 idle_rule=0; 15226 int cfg_num = -1; 15227 15228 15229 /* Possible TDM frequencies 15230 80MHz(16Cycles) ,120MHz(20Cycles),155MHz(84Cycles), 15231 185MHz(80Cycles),185MHz(90Cycles) 15232 */ 15233 switch(tdm_freq) { 15234 case 123: 15235 tdm_freq_index=1; 15236 expected_tdm_cycles_min=40; 15237 expected_tdm_cycles_max=40; 15238 break; 15239 case 155: 15240 tdm_freq_index=2; 15241 expected_tdm_cycles_min=84; 15242 expected_tdm_cycles_max=168; 15243 break; 15244 case 176: 15245 expected_tdm_cycles_min=60; 15246 expected_tdm_cycles_max=90; 15247 if (total_tdm_slots == 64) { 15248 tdm_freq_index=7; 15249 } 15250 if (total_tdm_slots == 90) { 15251 tdm_freq_index=4; 15252 } 15253 if (total_tdm_slots == 60) { 15254 tdm_freq_index=3; 15255 } 15256 if (total_tdm_slots == 72) { 15257 tdm_freq_index=2; 15258 } 15259 15260 /* 15261 * Index to be used in kt2_tdm_cycles_info 15262 * for TDM slots spacing information. 15263 */ 15264 if (total_tdm_slots == BCM_KT2_TDM_A1_NUM_SLOTS) { 15265 tdm_freq_index = 9; 15266 } 15267 break; 15268 case 205: 15269 expected_tdm_cycles_min=88; 15270 expected_tdm_cycles_max=216; 15271 if (total_tdm_slots == 108 ) { 15272 tdm_freq_index=5; 15273 } 15274 if (total_tdm_slots == 88 ) { 15275 cfg_num = soc_property_get(unit, spn_BCM5645X_CONFIG,0xFF); 15276 if (cfg_num == 15) { 15277 tdm_freq_index=10; 15278 } else { 15279 tdm_freq_index=6; 15280 } 15281 } 15282 if (total_tdm_slots == 216 ) { 15283 tdm_freq_index=0; 15284 } 15285 15286 /* 15287 * Index to be used in kt2_tdm_cycles_info 15288 * for TDM slots spacing information. 15289 */ 15290 if (total_tdm_slots == BCM_KT2_TDM_A1_NUM_SLOTS ) { 15291 tdm_freq_index = 9; 15292 } 15293 break; 15294 case 166: 15295 tdm_freq_index=8; 15296 expected_tdm_cycles_min=84; 15297 expected_tdm_cycles_max=84; 15298 break; 15299 default: 15300 LOG_ERROR(BSL_LS_SOC_COMMON, 15301 (BSL_META_U(unit, 15302 "Unsupported tdm frequency:%d\n"), 15303 tdm_freq)); 15304 return SOC_E_FAIL; 15305 } 15306 if (!((total_tdm_slots >= expected_tdm_cycles_min) && 15307 (total_tdm_slots <= expected_tdm_cycles_max))) { 15308 LOG_ERROR(BSL_LS_SOC_COMMON, 15309 (BSL_META_U(unit, 15310 "Unsupported tdm cycles:%d (min:%d max:%d\n"), 15311 total_tdm_slots, 15312 expected_tdm_cycles_min,expected_tdm_cycles_max)); 15313 return SOC_E_FAIL; 15314 } 15315 15316 idle_flag=0; 15317 idle_rule = 0; 15318 /* Initialize list */ 15319 for (port=0;port < KT2_MAX_LOGICAL_PORTS ; port++) { 15320 kt2_tdm_port_slots_info[port].prev=&kt2_tdm_port_slots_info[port]; 15321 kt2_tdm_port_slots_info[port].next=&kt2_tdm_port_slots_info[port]; 15322 kt2_tdm_port_slots_info[port].position = -1; 15323 } 15324 for (index=0; index < total_tdm_slots; index++) { 15325 if ((tdm[index] == KT2_IDLE1) || 15326 (tdm[index] == KT2_IDLE)) { 15327 if (tdm[index] == KT2_IDLE1) { 15328 if (idle_flag == 1) { 15329 idle_rule = 1; 15330 } 15331 idle_flag=1; 15332 } 15333 skip_count++; 15334 continue; 15335 } 15336 if (((index - 1) != 0) && (index != total_tdm_slots - 1) && 15337 (idle_flag == 1) && (idle_rule == 0)) { 15338 LOG_ERROR(BSL_LS_SOC_COMMON, 15339 (BSL_META_U(unit, 15340 "### Internal Error: TDM Verification failed \n" 15341 "### Two consecutive idle not found at position:%d\n" 15342 "### TCAM Atomicity might get affected.\n"), 15343 index - 1)); 15344 *offender_port = KT2_IDLE1; 15345 return SOC_E_CONFIG; 15346 } 15347 idle_flag=0; 15348 port = tdm[index]; 15349 if (kt2_tdm_port_slots_info[port].position == -1) { 15350 /* First Entry */ 15351 kt2_tdm_port_slots_info[port].position = index; 15352 skip_count++; 15353 continue; 15354 } 15355 head = current = &kt2_tdm_port_slots_info[port]; 15356 while(current->next !=head) { 15357 current = current->next; 15358 } 15359 current->next=sal_alloc(sizeof(tdm_port_slots_info_t),"TDM Pointer"); 15360 count++; 15361 LOG_VERBOSE(BSL_LS_SOC_COMMON, 15362 (BSL_META_U(unit, 15363 "Count=%d SkipCount:%d Port:%d Addr:%p\n"), 15364 count,skip_count,port,(void *)current->next)); 15365 15366 current->next->position=index; 15367 current->next->prev=current; 15368 current->next->next=head; 15369 head->prev=current->next; 15370 } 15371 if (idle_rule == 0) { 15372 /* Special case */ 15373 if (!((tdm[0] == KT2_IDLE1) && 15374 (tdm[total_tdm_slots-1] == KT2_IDLE1))) { 15375 LOG_ERROR(BSL_LS_SOC_COMMON, 15376 (BSL_META_U(unit, 15377 "### Internal Error: TDM Verification failed \n" 15378 "### Two consecutive idle not found at Edges \n" 15379 "### TCAM Atomicity might get affected.\n"))); 15380 *offender_port = KT2_IDLE1; 15381 return SOC_E_CONFIG; 15382 } 15383 } 15384 LOG_VERBOSE(BSL_LS_SOC_COMMON, 15385 (BSL_META_U(unit, 15386 "Final Count=%d SkipCount:%d\n"),count,skip_count)); 15387 LOG_VERBOSE(BSL_LS_SOC_COMMON, 15388 (BSL_META_U(unit, 15389 "Verifying rule \n"))); 15390 LOG_VERBOSE(BSL_LS_SOC_COMMON, 15391 (BSL_META_U(unit, 15392 "Rule3: Loopback (LPBK) ports require min 3 cycle spacing " 15393 "among LPBK or CMIC ports \n"))); 15394 if (kt2_tdm_port_slots_info[KT2_LPBK_PORT].position == -1) { 15395 LOG_CLI((BSL_META_U(unit, 15396 "Loopback port missing in configuration \n"))); 15397 return SOC_E_FAIL; 15398 } 15399 if (kt2_tdm_port_slots_info[KT2_CMIC_PORT].position == -1) { 15400 LOG_CLI((BSL_META_U(unit, 15401 "CMIC port missing in configuration \n"))); 15402 return SOC_E_FAIL; 15403 } 15404 if (olp_port_flag) { 15405 if (kt2_tdm_port_slots_info[KT2_OLP_PORT].position == -1) { 15406 LOG_CLI((BSL_META_U(unit, 15407 "OLP port missing in configuration \n"))); 15408 return SOC_E_FAIL; 15409 } 15410 } 15411 head = current = &kt2_tdm_port_slots_info[KT2_LPBK_PORT]; 15412 do { 15413 prev = current->prev; 15414 if ( current->position != prev->position ) { 15415 prev_tdm_slot_spacing = 15416 (current->position - prev->position) > 0 ? 15417 (current->position - prev->position)-1: 15418 (total_tdm_slots - prev->position + 15419 current->position) - 1; 15420 next_tdm_slot_spacing = 15421 (current->next->position - current->position) >0 ? 15422 (current->next->position - current->position)-1: 15423 (total_tdm_slots - current->position + 15424 current->next->position) - 1; 15425 if (prev_tdm_slot_spacing <= 3) { 15426 LOG_ERROR(BSL_LS_SOC_COMMON, 15427 (BSL_META_U(unit, 15428 "Loopback Ports need min 3 spacing but(prev)found" 15429 "(current:%d , prev:%d)=%d\n"), 15430 current->position,prev->position,prev_tdm_slot_spacing)); 15431 rv = SOC_E_FAIL; 15432 continue; 15433 } 15434 if (next_tdm_slot_spacing < 3) { 15435 LOG_ERROR(BSL_LS_SOC_COMMON, 15436 (BSL_META_U(unit, 15437 "Loopback Ports need min 3 spacing but(next)found" 15438 "(current:%d , prev:%d)=%d\n"), 15439 current->position,prev->position,next_tdm_slot_spacing)); 15440 rv = SOC_E_CONFIG; 15441 *offender_port = KT2_LPBK_PORT; 15442 continue; 15443 } 15444 } else { 15445 prev_tdm_slot_spacing = next_tdm_slot_spacing = 0; 15446 } 15447 head1 = current1 = &kt2_tdm_port_slots_info[KT2_CMIC_PORT]; 15448 do { 15449 tdm_slot_spacing = (current->position - current1->position) > 0 ? 15450 (current->position - current1->position)-1: 15451 (total_tdm_slots - current1->position + 15452 current->position) - 1 ; 15453 if (tdm_slot_spacing < 3) { 15454 LOG_ERROR(BSL_LS_SOC_COMMON, 15455 (BSL_META_U(unit, 15456 "Loopback and CMIC ports need min 3 spacing but " 15457 "found:%u" "(Loopack current:%d , CMIC Current:%d)\n"), 15458 tdm_slot_spacing, 15459 current->position,current1->position)); 15460 rv = SOC_E_CONFIG; 15461 *offender_port=KT2_LPBK_PORT; 15462 continue; 15463 } 15464 current1 = current1->next; 15465 }while ((current1 !=head1) && (rv == SOC_E_NONE)); 15466 current = current->next; 15467 } while ((current !=head) && (rv == SOC_E_NONE)); 15468 LOG_VERBOSE(BSL_LS_SOC_COMMON, 15469 (BSL_META_U(unit, 15470 "Verifying rules \n"))); 15471 LOG_VERBOSE(BSL_LS_SOC_COMMON, 15472 (BSL_META_U(unit, 15473 "Rule1 : Each Loopback port need 2.5G bandwidth \n"))); 15474 LOG_VERBOSE(BSL_LS_SOC_COMMON, 15475 (BSL_META_U(unit, 15476 "Rule2 : Each CMIC port need 2G bandwidth \n"))); 15477 for (index=0;index < KT2_MAX_LOGICAL_PORTS && rv == SOC_E_NONE ;index++ ) { 15478 port = index ; 15479 if (kt2_tdm_port_slots_info[port].position == -1) { 15480 continue; 15481 } 15482 LOG_VERBOSE(BSL_LS_SOC_COMMON, 15483 (BSL_META_U(unit, 15484 " %d ==>\n\n"),port)); 15485 switch(port) { 15486 case KT2_CMIC_PORT: 15487 LOG_VERBOSE(BSL_LS_SOC_COMMON, 15488 (BSL_META_U(unit, 15489 "CMIM \n"))); 15490 speed =2000; 15491 break; 15492 case KT2_LPBK_PORT: 15493 LOG_VERBOSE(BSL_LS_SOC_COMMON, 15494 (BSL_META_U(unit, 15495 "LOOPBAKC \n"))); 15496 speed =2500; 15497 break; 15498 default: 15499 LOG_VERBOSE(BSL_LS_SOC_COMMON, 15500 (BSL_META_U(unit, 15501 " Port:%d Speed %d ==>\n\n"), 15502 port,port_speed[port-1])); 15503 speed = port_speed[port-1]; 15504 break; 15505 } 15506 switch(speed) { 15507 case 1000: 15508 speed_index=0; 15509 break; 15510 case 2000: 15511 speed_index=1; 15512 break; 15513 case 2500: 15514 speed_index=2; 15515 break; 15516 case 10000: 15517 speed_index=3; 15518 break; 15519 case 13000: 15520 speed_index=4; 15521 break; 15522 case 20000: 15523 speed_index=5; 15524 break; 15525 case 21000: 15526 speed_index=6; 15527 break; 15528 default: 15529 LOG_ERROR(BSL_LS_SOC_COMMON, 15530 (BSL_META_U(unit, 15531 "Unsupported speed:%d \n"),speed)); 15532 return SOC_E_FAIL; 15533 } 15534 worse_tdm_slot_spacing=kt2_tdm_cycles_info[tdm_freq_index][speed_index]. 15535 worse_tdm_slot_spacing; 15536 min_tdm_cycles=kt2_tdm_cycles_info[tdm_freq_index][speed_index]. 15537 min_tdm_cycles; 15538 15539 count=0; 15540 head = current = &kt2_tdm_port_slots_info[port]; 15541 do { 15542 prev = current->prev; 15543 if (current->position != prev->position ) { 15544 prev_tdm_slot_spacing = 15545 (current->position - prev->position)> 0 ? 15546 (current->position - prev->position)-1: 15547 (total_tdm_slots - prev->position + 15548 current->position) - 1 ; 15549 next_tdm_slot_spacing = 15550 (current->next->position - current->position) > 0 ? 15551 (current->next->position - current->position)-1: 15552 (total_tdm_slots - current->position + 15553 current->next->position) - 1; 15554 } else { 15555 prev_tdm_slot_spacing = next_tdm_slot_spacing = 0; 15556 } 15557 LOG_VERBOSE(BSL_LS_SOC_COMMON, 15558 (BSL_META_U(unit, 15559 "Pos:%d Spacing (Prev %d - %d = )%d" 15560 "(Next %d - %d = )%d\n"), current->position, 15561 current->position , prev->position , 15562 prev_tdm_slot_spacing, current->next->position , 15563 current->position , next_tdm_slot_spacing)); 15564 if ((prev_tdm_slot_spacing > worse_tdm_slot_spacing) || 15565 (next_tdm_slot_spacing > worse_tdm_slot_spacing)) { 15566 LOG_ERROR(BSL_LS_SOC_COMMON, 15567 (BSL_META_U(unit, 15568 "WorseSpacing:%d NOK !!!! port:%d\n"), 15569 worse_tdm_slot_spacing,port)); 15570 rv = SOC_E_CONFIG; 15571 *offender_port=port; 15572 continue; 15573 } 15574 count++; 15575 current = current->next; 15576 } while ((current !=head) && (rv == SOC_E_NONE)) ; 15577 LOG_VERBOSE(BSL_LS_SOC_COMMON, 15578 (BSL_META_U(unit, 15579 "TDM Cycles: %d \n"),count)); 15580 if (count < min_tdm_cycles) { 15581 LOG_ERROR(BSL_LS_SOC_COMMON, 15582 (BSL_META_U(unit, 15583 "min_tdm_cycles:%dNOK !!!! port:%d\n"), 15584 min_tdm_cycles,port)); 15585 rv = SOC_E_CONFIG; 15586 *offender_port=port; 15587 continue; 15588 } 15589 LOG_VERBOSE(BSL_LS_SOC_COMMON, 15590 (BSL_META_U(unit, 15591 "n== %d <==\n\n"),port)); 15592 } 15593 15594 LOG_VERBOSE(BSL_LS_SOC_COMMON, 15595 (BSL_META_U(unit, 15596 "Verifying rule \n"))); 15597 LOG_VERBOSE(BSL_LS_SOC_COMMON, 15598 (BSL_META_U(unit, 15599 "Rule4 : Each subport in MXQPORT operates with 4 cycle TDM \n"))); 15600 LOG_VERBOSE(BSL_LS_SOC_COMMON, 15601 (BSL_META_U(unit, 15602 "Verifying MXQports spacing concern\n"))); 15603 for(mxqblock=0;mxqblock<(KT2_MAX_MXQBLOCKS-1) && rv == SOC_E_NONE ;mxqblock++) { 15604 for(index=0; 15605 index<KT2_MAX_MXQPORTS_PER_BLOCK && rv == SOC_E_NONE; 15606 index++) { 15607 outer_port = (*kt2_mxqblock_ports[unit])[mxqblock][index]; 15608 if (outer_port == 0xFF) { 15609 if ((mxqblock == 7) && (index == 3)) { 15610 outer_port = 40; 15611 } else { 15612 continue; 15613 } 15614 } 15615 #if 0 15616 /* Ignore MXQSpacing issue for OLP Port */ 15617 if ((outer_port == KT2_OLP_PORT) && (olp_port_flag)) { 15618 continue; 15619 } 15620 #endif 15621 if (kt2_tdm_port_slots_info[outer_port].position == -1) { 15622 continue; 15623 } 15624 head = current = &kt2_tdm_port_slots_info[outer_port]; 15625 do { 15626 for(loop=0;loop<KT2_MAX_MXQPORTS_PER_BLOCK; loop++) { 15627 inner_port=(*kt2_mxqblock_ports[unit])[mxqblock][loop]; 15628 if (inner_port == 0xFF) { 15629 if ((mxqblock == 7) && (loop == 3)) { 15630 inner_port = 40; 15631 } else { 15632 continue; 15633 } 15634 } 15635 #if 0 15636 /* Ignore MXQSpacing issue for OLP Port */ 15637 if ((inner_port == KT2_OLP_PORT) && (olp_port_flag)) { 15638 continue; 15639 } 15640 #endif 15641 if ( inner_port == outer_port) { 15642 continue; 15643 } 15644 if (kt2_tdm_port_slots_info[inner_port].position == -1) { 15645 continue; 15646 } 15647 head1 = current1 = &kt2_tdm_port_slots_info[inner_port]; 15648 do { 15649 spacing = (current->position - current1->position) > 0 ? 15650 (current->position - current1->position)-1: 15651 (total_tdm_slots - current1->position + 15652 current->position) - 1; 15653 if (spacing < 3) { 15654 LOG_ERROR(BSL_LS_SOC_COMMON, 15655 (BSL_META_U(unit, 15656 "Outer Port:%d Inner Port:%d " 15657 "MXQSpacing Issue" 15658 "Expected > 4 but observed %d\n"), 15659 outer_port,inner_port,spacing)); 15660 rv = SOC_E_CONFIG; 15661 *offender_port=outer_port; 15662 continue; 15663 } 15664 current1 = current1->next; 15665 } while ((current1 !=head1) && (rv == SOC_E_NONE)); 15666 } 15667 current = current->next; 15668 } while ((current !=head) && (rv == SOC_E_NONE)); 15669 } 15670 } 15671 15672 /* Free allocated resources */ 15673 count=0; 15674 for (port=0;port < KT2_MAX_LOGICAL_PORTS ; port++) { 15675 head = current = &kt2_tdm_port_slots_info[port]; 15676 do { 15677 temp = current->next; 15678 if (current != head) { 15679 count++; 15680 LOG_VERBOSE(BSL_LS_SOC_COMMON, 15681 (BSL_META_U(unit, 15682 "Freed count :%d\n"),count)); 15683 sal_free(current); 15684 } 15685 current = temp; 15686 } while (current != head); 15687 kt2_tdm_port_slots_info[port].prev=NULL; 15688 kt2_tdm_port_slots_info[port].next=NULL; 15689 kt2_tdm_port_slots_info[port].position = -1; 15690 } 15691 sal_memcpy(&kt2_current_tdm_cycles_info, 15692 &kt2_tdm_cycles_info[tdm_freq_index][0], 15693 sizeof(tdm_cycles_info_t)*KT2_MAX_SPEEDS); 15694 return rv; 15695 } 15696 static soc_error_t 15697 kt2_tdm_position_mask(int unit, 15698 uint32 port, 15699 int32 pos, 15700 uint32 total_tdm_slots, 15701 uint32 *tdm_position_mask) 15702 { 15703 uint32 count=0; 15704 uint32 mxqblock=0; 15705 int32 pos1=0; 15706 int32 pos2=0; 15707 15708 if (!((port >= 1) && (port <= KT2_MAX_PHYSICAL_PORTS))) { 15709 return SOC_E_PORT; 15710 } 15711 mxqblock=(*kt2_port_to_mxqblock[unit])[port-1]; 15712 for (count=0;count < 4; count++) { 15713 pos1 = (pos + count+1)%total_tdm_slots; 15714 tdm_position_mask[pos1] |= (1 << mxqblock); 15715 pos2 = (int32)(pos - (count+1)); 15716 if (pos2 < 0) { 15717 pos2 = pos2 + total_tdm_slots; 15718 } 15719 tdm_position_mask[pos2] |= (1 << mxqblock); 15720 } 15721 return SOC_E_NONE; 15722 } 15723 void kt2_fill_pos(int unit, 15724 uint32 *tdm, 15725 uint32 total_tdm_slots, 15726 int32 pos, 15727 uint32 port, 15728 uint32 port_type, 15729 uint32 min_tdm_cycles, 15730 uint32 worse_tdm_slot_spacing, 15731 uint32 optimal_tdm_slot_spacing) 15732 { 15733 uint32 negative_flag=0; 15734 uint32 fill_count=0; 15735 uint32 optimal_pos=pos; 15736 uint32 no_optimal_flag=0; 15737 int32 mxqblock=0; 15738 static uint32 last_port_type; 15739 static uint32 previous_position[18]={0}; 15740 15741 if ((port != KT2_LPBK_PORT) && (port != KT2_CMIC_PORT)) { 15742 mxqblock=(*kt2_port_to_mxqblock[unit])[port-1]; 15743 } 15744 if (pos == -1) { 15745 no_optimal_flag=1; 15746 pos = 0; 15747 if (last_port_type != port_type) { 15748 for(fill_count=0;fill_count<18;fill_count++) { 15749 previous_position[fill_count]=0; 15750 } 15751 } 15752 } 15753 last_port_type=port_type; 15754 15755 for(fill_count=0;fill_count<min_tdm_cycles;fill_count++) { 15756 if (no_optimal_flag == 1) { 15757 if ( previous_position[fill_count] != 0) { 15758 pos = previous_position[fill_count]+1; 15759 } 15760 } 15761 while (1) { 15762 if (tdm[pos] == KT2_IDLE) { 15763 if ((port == KT2_LPBK_PORT) || (port == KT2_CMIC_PORT)) { 15764 break; 15765 } 15766 if ((kt2_tdm_position_mxq_mask[pos] & (1<<mxqblock))==0) { 15767 break; 15768 } 15769 if (kt2_tdm_mxqblock_ports_used[(*kt2_port_to_mxqblock[unit])[port]] 15770 == 1) { 15771 break; 15772 } 15773 } 15774 if (no_optimal_flag == 0) { 15775 if ((negative_flag == 0) && (fill_count != 0)) { 15776 pos--; 15777 } else { 15778 pos++; 15779 negative_flag=0; 15780 } 15781 } else { 15782 pos++; 15783 } 15784 } 15785 if (pos < optimal_pos) { 15786 negative_flag=1; 15787 } 15788 tdm[pos]=port; 15789 previous_position[fill_count]=pos; 15790 if (!((port == KT2_LPBK_PORT) || (port == KT2_CMIC_PORT))) { 15791 kt2_tdm_position_mask(unit, 15792 port, 15793 pos, 15794 total_tdm_slots, 15795 kt2_tdm_position_mxq_mask); 15796 } 15797 pos = optimal_pos = pos + optimal_tdm_slot_spacing + 1; 15798 if (pos >= total_tdm_slots) { 15799 pos = total_tdm_slots -1; 15800 negative_flag = 0; /* forced too */ 15801 } 15802 } 15803 if (no_optimal_flag == 0) { 15804 for(fill_count=0;fill_count<18;fill_count++) { 15805 previous_position[fill_count]=0; 15806 } 15807 } 15808 } 15809 15810 void kt2_tdm_display(int unit, 15811 uint32 *tdm, 15812 uint32 total_tdm_slots, 15813 uint32 row, uint32 col) 15814 { 15815 uint32 inner_index=0; 15816 uint32 outer_index=0; 15817 15818 LOG_VERBOSE(BSL_LS_SOC_COMMON, 15819 (BSL_META_U(unit, 15820 "\n"))); 15821 LOG_VERBOSE(BSL_LS_SOC_COMMON, 15822 (BSL_META_U(unit, 15823 "\t\t\t\t======TDM======\n"))); 15824 for (outer_index=0;outer_index < col ; outer_index ++ ) { 15825 LOG_VERBOSE(BSL_LS_SOC_COMMON, 15826 (BSL_META_U(unit, 15827 "\t%d"),outer_index)); 15828 } 15829 LOG_VERBOSE(BSL_LS_SOC_COMMON, 15830 (BSL_META_U(unit, 15831 "\n"))); 15832 for (outer_index=0;outer_index < col ; outer_index ++ ) { 15833 LOG_VERBOSE(BSL_LS_SOC_COMMON, 15834 (BSL_META_U(unit, 15835 "\t%d#"),outer_index)); 15836 } 15837 LOG_VERBOSE(BSL_LS_SOC_COMMON, 15838 (BSL_META_U(unit, 15839 "\n"))); 15840 15841 for (outer_index=0; outer_index < total_tdm_slots ; outer_index +=col ) { 15842 LOG_VERBOSE(BSL_LS_SOC_COMMON, 15843 (BSL_META_U(unit, 15844 "%d==>\t"),outer_index/col)); 15845 for (inner_index=0; 15846 (inner_index < col) && 15847 ((outer_index+inner_index) < total_tdm_slots) ; 15848 inner_index++ ) { 15849 switch(tdm[outer_index+inner_index]) { 15850 case KT2_IDLE : 15851 LOG_VERBOSE(BSL_LS_SOC_COMMON, 15852 (BSL_META_U(unit, 15853 "IDLE\t"))); 15854 break; 15855 case KT2_IDLE1 : 15856 LOG_VERBOSE(BSL_LS_SOC_COMMON, 15857 (BSL_META_U(unit, 15858 "IDLE1\t"))); 15859 break; 15860 case KT2_LPBK_PORT : 15861 LOG_VERBOSE(BSL_LS_SOC_COMMON, 15862 (BSL_META_U(unit, 15863 "LPBK\t"))); 15864 break; 15865 case KT2_CMIC_PORT : 15866 LOG_VERBOSE(BSL_LS_SOC_COMMON, 15867 (BSL_META_U(unit, 15868 "CMIC\t"))); 15869 break; 15870 case KT2_OLP_PORT : 15871 if (SOC_INFO(unit).olp_port[0]) { 15872 LOG_VERBOSE(BSL_LS_SOC_COMMON, 15873 (BSL_META_U(unit, 15874 "OLP\t"))); 15875 break; 15876 } 15877 default : 15878 LOG_VERBOSE(BSL_LS_SOC_COMMON, 15879 (BSL_META_U(unit, 15880 "%d\t"), 15881 tdm[outer_index+inner_index])); 15882 break; 15883 } 15884 } 15885 LOG_VERBOSE(BSL_LS_SOC_COMMON, 15886 (BSL_META_U(unit, 15887 "\n"))); 15888 } 15889 } 15890 soc_error_t kt2_tdm_generate( 15891 int unit, 15892 uint32 *port_speed, 15893 uint32 total_ports, 15894 uint32 tdm_freq , /* In MHHz */ 15895 uint32 total_tdm_slots, 15896 uint32 *tdm, 15897 char *tdm_config_string) 15898 { 15899 char temp_string[80]; 15900 uint32 reserved_flag=0; 15901 uint32 optimal_pos=0; 15902 uint32 mxqblock; 15903 uint32 next_mxqblock; 15904 uint32 temp; 15905 uint32 total_bw=0; 15906 uint32 port=0; 15907 uint32 count=0; 15908 uint32 index=0; 15909 uint32 index1=0; 15910 15911 int32 pos=0; 15912 15913 uint32 kt2_1g_ports=0; 15914 uint32 kt2_1g_ports_array[40]={0}; 15915 uint32 kt2_1g_ports_mxqflags[10]={0}; 15916 /* int kt2_1g_ports_pos[2]={0}; */ 15917 uint32 kt2_2g_ports=0; 15918 uint32 kt2_2g_ports_array[40]={0}; 15919 uint32 kt2_2g_ports_mxqflags[10]={0}; 15920 15921 uint32 kt2_2_5g_ports=0; 15922 uint32 kt2_2_5g_ports_array[40]={0}; 15923 uint32 kt2_2_5g_ports_mxqflags[10]={0}; 15924 15925 uint32 kt2_10g_ports=0; 15926 uint32 kt2_10g_ports_array[40]={0}; 15927 uint32 kt2_13g_ports=0; 15928 uint32 kt2_13g_ports_array[40]={0}; 15929 /* 15930 uint32 kt2_20g_ports=0; 15931 uint32 kt2_20g_ports_array[40]={0}; 15932 */ 15933 uint32 kt2_21g_ports=0; 15934 uint32 kt2_21g_ports_array[40]={0}; 15935 15936 uint32 kt2_21g_reserved_position[2]={0,2}; 15937 /* uint32 kt2_20g_reserved_position[2]={0,2}; */ 15938 uint32 kt2_13g_reserved_position[2]={1,4}; 15939 uint32 kt2_10g_reserved_position[2]={3,8}; 15940 uint32 tdm_freq_index=0; 15941 uint32 min_tdm_cycles=0; 15942 uint32 lpbk_min_tdm_cycles=0; 15943 uint32 cmic_min_tdm_cycles=0; 15944 uint32 worse_tdm_slot_spacing=0; 15945 uint32 optimal_tdm_slot_spacing=0; 15946 /* uint32 min_tdm_slot_spacing=0; */ 15947 uint32 speed_index=0; 15948 uint32 speed_index_1g=0; 15949 uint32 speed_index_2g=1; 15950 uint32 speed_index_2_5g=2; 15951 uint32 speed_index_10g=3; 15952 uint32 speed_index_13g=4; 15953 /* uint32 speed_index_20g=5; */ 15954 uint32 speed_index_21g=6; 15955 uint32 total_slots=0; 15956 /* Keeping row variable for future reference but unused 15957 unsigned int row=0; */ 15958 unsigned int col=0; 15959 15960 for(index=0;index<10;index++) { 15961 kt2_tdm_mxqblock_ports_used[index]=0; 15962 } 15963 switch(tdm_freq) { 15964 case 80: 15965 tdm_freq_index=0; 15966 /* row=4; */ 15967 col=4; 15968 break; 15969 case 120: 15970 tdm_freq_index=1; 15971 /* row=4; */ 15972 col=5; 15973 break; 15974 case 155: 15975 tdm_freq_index=2; 15976 /* row=12; */ 15977 col=7; 15978 break; 15979 case 185: 15980 if (total_tdm_slots == 80 ) { 15981 /* row=16; */ 15982 col=5; 15983 tdm_freq_index=3; 15984 } else { 15985 tdm_freq_index=4; 15986 /* row=18; */ 15987 col=5; 15988 } 15989 reserved_flag=1; 15990 break; 15991 default: 15992 LOG_ERROR(BSL_LS_SOC_COMMON, 15993 (BSL_META_U(unit, 15994 "Unsupported tdm frequency:%d \n"), 15995 tdm_freq)); 15996 return SOC_E_FAIL; 15997 } 15998 15999 for (port=0;port<total_ports;port++) { 16000 switch(port_speed[port]) { 16001 case 1000: 16002 kt2_1g_ports_array[kt2_1g_ports]=port+1; 16003 kt2_1g_ports++; 16004 kt2_1g_ports_mxqflags[(*kt2_port_to_mxqblock[unit])[port]]=1; 16005 total_slots += kt2_tdm_cycles_info[tdm_freq_index] 16006 [speed_index_1g].min_tdm_cycles; 16007 break; 16008 case 2000: 16009 kt2_2g_ports_array[kt2_2g_ports]=port+1; 16010 kt2_2g_ports++; 16011 kt2_2g_ports_mxqflags[(*kt2_port_to_mxqblock[unit])[port]]=1; 16012 total_slots += kt2_tdm_cycles_info[tdm_freq_index] 16013 [speed_index_2g].min_tdm_cycles; 16014 break; 16015 case 2500: 16016 kt2_2_5g_ports_array[kt2_2_5g_ports]=port+1; 16017 kt2_2_5g_ports++; 16018 kt2_2_5g_ports_mxqflags[(*kt2_port_to_mxqblock[unit])[port]]=1; 16019 total_slots += kt2_tdm_cycles_info[tdm_freq_index] 16020 [speed_index_2_5g].min_tdm_cycles; 16021 break; 16022 case 10000: 16023 kt2_10g_ports_array[kt2_10g_ports]=port+1;kt2_10g_ports++; 16024 total_slots += kt2_tdm_cycles_info[tdm_freq_index] 16025 [speed_index_10g].min_tdm_cycles; 16026 break; 16027 case 13000: 16028 kt2_13g_ports_array[kt2_13g_ports]=port+1;kt2_13g_ports++; 16029 total_slots += kt2_tdm_cycles_info[tdm_freq_index] 16030 [speed_index_13g].min_tdm_cycles; 16031 break; 16032 case 20000: 16033 case 21000: 16034 kt2_21g_ports_array[kt2_21g_ports]=port+1;kt2_21g_ports++; 16035 total_slots += kt2_tdm_cycles_info[tdm_freq_index] 16036 [speed_index_21g].min_tdm_cycles; 16037 break; 16038 case 0: 16039 continue; 16040 default: 16041 LOG_ERROR(BSL_LS_SOC_COMMON, 16042 (BSL_META_U(unit, 16043 "Unsupported speed%d\n"),port_speed[port])); 16044 return SOC_E_FAIL; 16045 } 16046 kt2_tdm_mxqblock_ports_used[(*kt2_port_to_mxqblock[unit])[port]]++; 16047 } 16048 /* 16049 * Multiply each base speed by 10 and then divide the total 16050 * bandwidth by 10 in order to avoid floating point (2.5G). 16051 */ 16052 total_bw = (10 * kt2_1g_ports + 16053 20 * kt2_2g_ports + 16054 25 * kt2_2_5g_ports + 16055 100 * kt2_10g_ports + 16056 130 * kt2_13g_ports + 16057 210 * kt2_21g_ports) / 10; 16058 if (total_bw > 92) { 16059 LOG_ERROR(BSL_LS_SOC_COMMON, 16060 (BSL_META_U(unit, 16061 "Exceeded max bw:92 %d \n"),total_bw)); 16062 return SOC_E_FAIL; 16063 } 16064 speed_index=speed_index_2_5g; 16065 lpbk_min_tdm_cycles=kt2_tdm_cycles_info[tdm_freq_index][speed_index]. 16066 min_tdm_cycles; 16067 speed_index=speed_index_2g; 16068 cmic_min_tdm_cycles=kt2_tdm_cycles_info[tdm_freq_index][speed_index]. 16069 min_tdm_cycles; 16070 if (total_slots > (total_tdm_slots - 16071 lpbk_min_tdm_cycles - cmic_min_tdm_cycles)) { 16072 LOG_ERROR(BSL_LS_SOC_COMMON, 16073 (BSL_META_U(unit, 16074 "Exceeded max slots:%d %d \n"), 16075 (total_tdm_slots- 16076 lpbk_min_tdm_cycles-cmic_min_tdm_cycles),total_slots)); 16077 return SOC_E_FAIL; 16078 } 16079 if (tdm_config_string == NULL) { 16080 return SOC_E_INTERNAL; 16081 } 16082 tdm_config_string[0] = '\0'; 16083 if(kt2_21g_ports) { 16084 sal_sprintf(temp_string," %d*21HG ",kt2_21g_ports); 16085 sal_sprintf(tdm_config_string,"%s%s",tdm_config_string,temp_string); 16086 } 16087 if(kt2_13g_ports) { 16088 sal_sprintf(temp_string," %d*13HG ",kt2_13g_ports); 16089 sal_sprintf(tdm_config_string,"%s%s",tdm_config_string,temp_string); 16090 } 16091 if(kt2_10g_ports) { 16092 sal_sprintf(temp_string," %d*10HG ",kt2_10g_ports); 16093 sal_sprintf(tdm_config_string,"%s%s",tdm_config_string,temp_string); 16094 } 16095 if(kt2_2_5g_ports) { 16096 sal_sprintf(temp_string," %d*2.5G ",kt2_2_5g_ports); 16097 sal_sprintf(tdm_config_string,"%s%s",tdm_config_string,temp_string); 16098 } 16099 if(kt2_2g_ports) { 16100 sal_sprintf(temp_string," %d*2G ",kt2_2g_ports); 16101 sal_sprintf(tdm_config_string,"%s%s",tdm_config_string,temp_string); 16102 } 16103 if(kt2_1g_ports) { 16104 sal_sprintf(temp_string," %d*1G ",kt2_1g_ports); 16105 sal_sprintf(tdm_config_string,"%s%s",tdm_config_string,temp_string); 16106 } 16107 sal_sprintf(temp_string,"TotalBw=%d",total_bw); 16108 sal_sprintf(tdm_config_string,"%s%s",tdm_config_string,temp_string); 16109 16110 for(pos=0;pos<total_tdm_slots;pos++) { 16111 tdm[pos]=KT2_IDLE; 16112 kt2_tdm_position_mxq_mask[pos]=0; 16113 } 16114 /* kt2_tdm_display(unit,tdm,total_tdm_slots,row,col); */ 16115 /* 1. First fill-up 10G ports */ 16116 speed_index=speed_index_10g; 16117 min_tdm_cycles=kt2_tdm_cycles_info[tdm_freq_index][speed_index]. 16118 min_tdm_cycles; 16119 worse_tdm_slot_spacing=kt2_tdm_cycles_info[tdm_freq_index][speed_index]. 16120 worse_tdm_slot_spacing; 16121 optimal_tdm_slot_spacing=kt2_tdm_cycles_info[tdm_freq_index][speed_index]. 16122 optimal_tdm_slot_spacing; 16123 16124 count=0; 16125 /* MAX 4 (2HG*2) 10G ports can be filled-up over here */ 16126 for(index=kt2_21g_ports;index<2;index++) { 16127 for(index1=0;index1<2 && count<kt2_10g_ports;index1++,count++) { 16128 if (reserved_flag == 1) { 16129 /* 5=(9+1)/2 */ 16130 pos = kt2_21g_reserved_position[index] + col*index1; 16131 } else { 16132 pos = optimal_pos= 0; 16133 } 16134 kt2_fill_pos(unit,tdm, total_tdm_slots, 16135 pos, kt2_10g_ports_array[index],10000,min_tdm_cycles, 16136 worse_tdm_slot_spacing,optimal_tdm_slot_spacing); 16137 /* kt2_tdm_display(unit,tdm,total_tdm_slots,row,col); */ 16138 } 16139 } 16140 /* MAX 2 10G ports can be filled-up over here */ 16141 for(index1=0;count<kt2_10g_ports;index1++,count++) { 16142 if (reserved_flag == 1) { 16143 if (index1 == 2) { 16144 break; 16145 } 16146 pos = kt2_10g_reserved_position[index1] ; 16147 } else { 16148 pos = optimal_pos = 0; 16149 } 16150 kt2_fill_pos(unit,tdm, total_tdm_slots, pos, 16151 kt2_10g_ports_array[count],10000,min_tdm_cycles, 16152 worse_tdm_slot_spacing,optimal_tdm_slot_spacing); 16153 /* kt2_tdm_display(unit,tdm,total_tdm_slots,row,col); */ 16154 } 16155 /* 10G ports can still be used(2 more) if 13G ports are not used !! */ 16156 if (count < kt2_10g_ports) { 16157 if (kt2_13g_ports != 0) { 16158 LOG_ERROR(BSL_LS_SOC_COMMON, 16159 (BSL_META_U(unit, 16160 "13G ports being used.." 16161 "max 10G port can be 6 only\n"))); 16162 return SOC_E_FAIL; 16163 } 16164 for(index1=0; index1<2 && count<kt2_10g_ports; index1++,count++) { 16165 if (reserved_flag == 1) { 16166 pos = kt2_13g_reserved_position[0] + col*index1;/*5=(9+1)/2*/ 16167 } else { 16168 pos = 0; 16169 } 16170 kt2_fill_pos(unit,tdm, total_tdm_slots, pos, 16171 kt2_10g_ports_array[count],10000,min_tdm_cycles, 16172 worse_tdm_slot_spacing,optimal_tdm_slot_spacing); 16173 /* kt2_tdm_display(unit,tdm,total_tdm_slots,row,col); */ 16174 } 16175 } 16176 speed_index=speed_index_21g; 16177 min_tdm_cycles=kt2_tdm_cycles_info[tdm_freq_index][speed_index]. 16178 min_tdm_cycles; 16179 worse_tdm_slot_spacing=kt2_tdm_cycles_info[tdm_freq_index][speed_index]. 16180 worse_tdm_slot_spacing; 16181 optimal_tdm_slot_spacing=kt2_tdm_cycles_info[tdm_freq_index][speed_index]. 16182 optimal_tdm_slot_spacing; 16183 16184 /* 2. Fill-up 21,20G ports now */ 16185 for(index=0;index<kt2_21g_ports;index++) { 16186 if (reserved_flag == 1) { 16187 pos = kt2_21g_reserved_position[index] ; 16188 } else { 16189 pos = 0; 16190 } 16191 kt2_fill_pos(unit,tdm, total_tdm_slots, pos, 16192 kt2_21g_ports_array[index],21000,min_tdm_cycles, 16193 worse_tdm_slot_spacing,optimal_tdm_slot_spacing); 16194 /* kt2_tdm_display(unit,tdm,total_tdm_slots,row,col); */ 16195 } 16196 speed_index=speed_index_13g; 16197 min_tdm_cycles=kt2_tdm_cycles_info[tdm_freq_index][speed_index]. 16198 min_tdm_cycles; 16199 worse_tdm_slot_spacing=kt2_tdm_cycles_info[tdm_freq_index][speed_index]. 16200 worse_tdm_slot_spacing; 16201 optimal_tdm_slot_spacing=kt2_tdm_cycles_info[tdm_freq_index][speed_index]. 16202 optimal_tdm_slot_spacing; 16203 16204 /* 3. Fill-up 13G ports now */ 16205 for(index=0;index<kt2_13g_ports;index++) { 16206 if (reserved_flag == 1) { 16207 switch(index) { 16208 case 0: 16209 case 1: pos = kt2_13g_reserved_position[index] ; break; 16210 case 2: 16211 case 3: if (tdm[kt2_21g_reserved_position[0]] == KT2_IDLE) { 16212 pos = kt2_21g_reserved_position[0] ; break; 16213 } 16214 if (tdm[kt2_10g_reserved_position[0]] == KT2_IDLE) { 16215 pos = kt2_10g_reserved_position[0] ; break; 16216 } 16217 LOG_ERROR(BSL_LS_SOC_COMMON, 16218 (BSL_META_U(unit, 16219 "21G and 10G ports Slots are not free :%d \n"), 16220 index)); 16221 return SOC_E_FAIL; 16222 } 16223 } else { 16224 pos = 0; 16225 } 16226 kt2_fill_pos(unit,tdm, total_tdm_slots, pos, 16227 kt2_13g_ports_array[index],13000,min_tdm_cycles, 16228 worse_tdm_slot_spacing,optimal_tdm_slot_spacing); 16229 /* kt2_tdm_display(unit,tdm,total_tdm_slots,row,col); */ 16230 } 16231 /* 3. Fill-up Loopback ports now */ 16232 speed_index=speed_index_2_5g; 16233 min_tdm_cycles=kt2_tdm_cycles_info[tdm_freq_index][speed_index]. 16234 min_tdm_cycles; 16235 worse_tdm_slot_spacing=kt2_tdm_cycles_info[tdm_freq_index][speed_index]. 16236 worse_tdm_slot_spacing; 16237 optimal_tdm_slot_spacing=kt2_tdm_cycles_info[tdm_freq_index][speed_index]. 16238 optimal_tdm_slot_spacing; 16239 16240 kt2_fill_pos(unit,tdm, total_tdm_slots, -1, KT2_LPBK_PORT,2500, min_tdm_cycles, 16241 worse_tdm_slot_spacing,optimal_tdm_slot_spacing); 16242 /* 4. Fill-up CMIC ports now */ 16243 speed_index=speed_index_2g; 16244 min_tdm_cycles=kt2_tdm_cycles_info[tdm_freq_index][speed_index]. 16245 min_tdm_cycles; 16246 worse_tdm_slot_spacing=kt2_tdm_cycles_info[tdm_freq_index][speed_index]. 16247 worse_tdm_slot_spacing; 16248 optimal_tdm_slot_spacing=kt2_tdm_cycles_info[tdm_freq_index][speed_index]. 16249 optimal_tdm_slot_spacing; 16250 /* min_tdm_slot_spacing=optimal_tdm_slot_spacing-(worse_tdm_slot_spacing);*/ 16251 pos = 0; 16252 while (tdm[pos] != KT2_LPBK_PORT) { 16253 pos++; 16254 } 16255 pos = pos + 3 + 1; /* Minimum 3 spacing */ 16256 while (tdm[pos] != KT2_IDLE) { 16257 pos++; 16258 } 16259 tdm[pos] = KT2_CMIC_PORT; 16260 /* kt2_tdm_display(unit,tdm,total_tdm_slots,row,col); */ 16261 kt2_fill_pos(unit,tdm, total_tdm_slots, pos+optimal_tdm_slot_spacing+1, 16262 KT2_CMIC_PORT,2000, min_tdm_cycles-1, 16263 worse_tdm_slot_spacing,optimal_tdm_slot_spacing); 16264 /* kt2_tdm_display(unit,tdm,total_tdm_slots,row,col); */ 16265 16266 /* 5. Fill-up remaining 2.5G ports now */ 16267 16268 /* 5.1 First Re-arrange 2.5g ports */ 16269 port = kt2_2_5g_ports_array[0]; 16270 for (index=1;index < kt2_2_5g_ports;index++) { 16271 mxqblock = (*kt2_port_to_mxqblock[unit])[port-1]; 16272 next_mxqblock=mxqblock; 16273 do { 16274 next_mxqblock=(next_mxqblock+1)%10; 16275 if (kt2_2_5g_ports_mxqflags[next_mxqblock] == 1) { 16276 break; 16277 } 16278 }while (next_mxqblock != mxqblock); 16279 /* Swap entry with next mxqblock */ 16280 index1=index; 16281 do { 16282 port = kt2_2_5g_ports_array[index1]; 16283 if ( (*kt2_port_to_mxqblock[unit])[port-1] == next_mxqblock) { 16284 break; 16285 } 16286 index1=(index1+1)%kt2_2_5g_ports; 16287 } while ( index1 != index); 16288 temp = kt2_2_5g_ports_array[index1]; 16289 kt2_2_5g_ports_array[index1]= kt2_2_5g_ports_array[index]; 16290 kt2_2_5g_ports_array[index]= temp; 16291 } 16292 16293 /* 5.2 Now update tdm for 2.5g ports */ 16294 speed_index=speed_index_2_5g; 16295 min_tdm_cycles=kt2_tdm_cycles_info[tdm_freq_index][speed_index]. 16296 min_tdm_cycles; 16297 worse_tdm_slot_spacing=kt2_tdm_cycles_info[tdm_freq_index][speed_index]. 16298 worse_tdm_slot_spacing; 16299 optimal_tdm_slot_spacing=kt2_tdm_cycles_info[tdm_freq_index][speed_index]. 16300 optimal_tdm_slot_spacing; 16301 16302 for(index=0;index<kt2_2_5g_ports;index++) { 16303 port = kt2_2_5g_ports_array[index]; 16304 kt2_fill_pos(unit,tdm, total_tdm_slots, -1, 16305 port,2500, min_tdm_cycles, 16306 worse_tdm_slot_spacing,optimal_tdm_slot_spacing); 16307 /* kt2_tdm_display(unit,tdm,total_tdm_slots,row,col); */ 16308 } 16309 16310 /* 6. Fill-up 2G ports now */ 16311 16312 /* 6.1 Re-arrange 2g ports first */ 16313 port = kt2_2g_ports_array[0]; 16314 for (index=1;index < kt2_2g_ports;index++) { 16315 mxqblock = (*kt2_port_to_mxqblock[unit])[port-1]; 16316 next_mxqblock=mxqblock; 16317 do { 16318 next_mxqblock=(next_mxqblock+1)%10; 16319 if (kt2_2g_ports_mxqflags[next_mxqblock] == 1) { 16320 break; 16321 } 16322 }while (next_mxqblock != mxqblock); 16323 /* Swap entry with next mxqblock */ 16324 index1=index; 16325 do { 16326 port = kt2_2g_ports_array[index1]; 16327 if ( (*kt2_port_to_mxqblock[unit])[port-1] == next_mxqblock) { 16328 break; 16329 } 16330 index1=(index1+1)%kt2_2g_ports; 16331 } while ( index1 != index); 16332 temp = kt2_2g_ports_array[index1]; 16333 kt2_2g_ports_array[index1]= kt2_2g_ports_array[index]; 16334 kt2_2g_ports_array[index]= temp; 16335 } 16336 16337 /* 6.2 Now update tdm for 2g ports */ 16338 speed_index=speed_index_2g; 16339 min_tdm_cycles=kt2_tdm_cycles_info[tdm_freq_index][speed_index]. 16340 min_tdm_cycles; 16341 worse_tdm_slot_spacing=kt2_tdm_cycles_info[tdm_freq_index][speed_index]. 16342 worse_tdm_slot_spacing; 16343 optimal_tdm_slot_spacing=kt2_tdm_cycles_info[tdm_freq_index][speed_index]. 16344 optimal_tdm_slot_spacing; 16345 16346 for(index=0;index<kt2_2g_ports;index++) { 16347 port = kt2_2g_ports_array[index]; 16348 kt2_fill_pos(unit,tdm, total_tdm_slots, -1, 16349 port,2000, min_tdm_cycles, 16350 worse_tdm_slot_spacing,optimal_tdm_slot_spacing); 16351 /* kt2_tdm_display(unit,tdm,total_tdm_slots,row,col); */ 16352 } 16353 16354 /* Re-arrange 1g ports */ 16355 port = kt2_1g_ports_array[0]; 16356 for (index=1;index < kt2_1g_ports;index++) { 16357 mxqblock = (*kt2_port_to_mxqblock[unit])[port-1]; 16358 next_mxqblock=mxqblock; 16359 do { 16360 next_mxqblock=(next_mxqblock+1)%10; 16361 if (kt2_1g_ports_mxqflags[next_mxqblock] == 1) { 16362 break; 16363 } 16364 }while (next_mxqblock != mxqblock); 16365 /* Swap entry with next mxqblock */ 16366 index1=index; 16367 do { 16368 port = kt2_1g_ports_array[index1]; 16369 if ( (*kt2_port_to_mxqblock[unit])[port-1] == next_mxqblock) { 16370 break; 16371 } 16372 index1=(index1+1)%kt2_1g_ports; 16373 } while ( index1 != index); 16374 temp = kt2_1g_ports_array[index1]; 16375 kt2_1g_ports_array[index1]= kt2_1g_ports_array[index]; 16376 kt2_1g_ports_array[index]= temp; 16377 } 16378 speed_index=speed_index_1g; 16379 min_tdm_cycles=kt2_tdm_cycles_info[tdm_freq_index][speed_index]. 16380 min_tdm_cycles; 16381 worse_tdm_slot_spacing=kt2_tdm_cycles_info[tdm_freq_index][speed_index]. 16382 worse_tdm_slot_spacing; 16383 optimal_tdm_slot_spacing=kt2_tdm_cycles_info[tdm_freq_index][speed_index]. 16384 optimal_tdm_slot_spacing; 16385 /* 6. Fill-up 1G ports now */ 16386 for(index=0;index<kt2_1g_ports;index++) { 16387 port = kt2_1g_ports_array[index]; 16388 kt2_fill_pos(unit,tdm, total_tdm_slots, 0, port,1000, min_tdm_cycles, 16389 worse_tdm_slot_spacing,optimal_tdm_slot_spacing); 16390 /* kt2_tdm_display(unit,tdm,total_tdm_slots,row,col); */ 16391 } 16392 return SOC_E_NONE; 16393 } 16394 16395 16396 16397 STATIC soc_error_t 16398 _soc_katana2_mmu_tdm_init(int unit) 16399 { 16400 uint32 *arr; 16401 uint32 olp_port_flag=0; 16402 uint32 offender_port=0; 16403 soc_error_t retVal=SOC_E_NONE; 16404 uint32 port=0; 16405 uint32 outer_index=0; 16406 uint32 inner_index=0; 16407 uint32 tdm_index=0; 16408 uint32 row=18; 16409 uint32 col=5; 16410 uint8 mxqblock=0; 16411 int num_lanes = 0; 16412 bcmMxqCorePortMode_t mode = bcmMxqCorePortModeSingle; 16413 16414 #ifdef UNDER_TESTING 16415 uint32 bcm56450_test_selection=0; 16416 uint32 *bcm56450_test_speed[]={kt2_tdm_56450_test_speed0, 16417 kt2_tdm_56450_test_speed1, 16418 kt2_tdm_56450_test_speed2, 16419 kt2_tdm_56450_test_speed3, 16420 kt2_tdm_56450_test_speed4, 16421 kt2_tdm_56450_test_speed5, 16422 kt2_tdm_56450_test_speed6, 16423 kt2_tdm_56450_test_speed7, 16424 kt2_tdm_56450_test_speed8, 16425 kt2_tdm_56450_test_speed9, 16426 kt2_tdm_56450_test_speed10, 16427 kt2_tdm_56450_test_speed11, 16428 kt2_tdm_56450_test_speed12, 16429 kt2_tdm_56450_test_speed13, 16430 kt2_tdm_56450_test_speed14, 16431 kt2_tdm_56450_test_speed15, 16432 kt2_tdm_56450_test_speed16, 16433 kt2_tdm_56450_test_speed17, 16434 kt2_tdm_56450_test_speed18, 16435 kt2_tdm_56450_test_speed19, 16436 }; 16437 uint32 pos=0; 16438 uint32 index=0; 16439 uint32 freq=0; 16440 16441 16442 #endif 16443 int i, tdm_size,tdm_freq, cfg_num, cfg_offset = 0, temp_cfg_num = 0; 16444 iarb_tdm_table_entry_t iarb_tdm; 16445 lls_port_tdm_entry_t lls_tdm; 16446 uint32 rval, arr_ele; 16447 uint16 dev_id; 16448 uint8 rev_id; 16449 uint32 port_enable_value=0; 16450 16451 soc_cm_get_id(unit, &dev_id, &rev_id); 16452 SOC_IF_ERROR_RETURN(_soc_katana2_get_cfg_num(unit, &cfg_num)); 16453 if (cfg_num >= (sizeof(bcm56450_tdm)/sizeof(bcm56450_tdm[0]))) { 16454 LOG_CLI((BSL_META_U(unit, 16455 "Wrong cfg_num:%d exceeding max cfg_num: %d\n"), 16456 cfg_num, 16457 (int)(sizeof(bcm56450_tdm)/sizeof(bcm56450_tdm[0])))); 16458 return SOC_E_FAIL; 16459 } 16460 16461 switch(dev_id) { 16462 case BCM55450_DEVICE_ID: 16463 case BCM55455_DEVICE_ID: 16464 case BCM56248_DEVICE_ID: 16465 case BCM56450_DEVICE_ID: 16466 case BCM56452_DEVICE_ID: 16467 case BCM56454_DEVICE_ID: 16468 case BCM56455_DEVICE_ID: 16469 case BCM56456_DEVICE_ID: 16470 case BCM56457_DEVICE_ID: 16471 case BCM56458_DEVICE_ID: 16472 tdm_size= bcm56450_tdm_info[cfg_num].tdm_size; 16473 tdm_freq= bcm56450_tdm_info[cfg_num].tdm_freq; 16474 row= bcm56450_tdm_info[cfg_num].row; 16475 col= bcm56450_tdm_info[cfg_num].col; 16476 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 16477 "Cfg=%d freq=%d size=%d raw=%d col=%d \n"), 16478 cfg_num,tdm_freq,tdm_size,row,col)); 16479 arr = bcm56450_tdm[cfg_num]; 16480 switch(cfg_num) { /* Will be later changed to switch(cfg_num) */ 16481 case BCM56248_DEVICE_ID_OFFSET_CFG + 0: 16482 case BCM56450_DEVICE_ID_OFFSET_CFG + 0: 16483 /* kt2_tdm_56450config_deprecated0 */ 16484 LOG_CLI((BSL_META_U(unit, 16485 "kt2_tdm_56450speed_deprecated0\n"))); 16486 sal_memcpy(arr, 16487 &kt2_tdm_56450AA_ref[0], sizeof(kt2_tdm_56450AA_ref)); 16488 olp_port_flag=0; 16489 break; 16490 case BCM56248_DEVICE_ID_OFFSET_CFG + 1: 16491 case BCM56450_DEVICE_ID_OFFSET_CFG + 1:/* kt2_tdm_A_56450_1 */ 16492 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 16493 "kt2_tdm_A_56450_1 \n"))); 16494 sal_memcpy(arr, 16495 &kt2_tdm_56450A_ref[0],sizeof(kt2_tdm_56450A_ref)); 16496 kt2_tdm_replace(arr,88,KT2_OLP_PORT,KT2_IDLE,0); 16497 kt2_tdm_replace(arr,tdm_size,33,25,0); 16498 kt2_tdm_replace(arr,tdm_size,30,26,0); 16499 olp_port_flag=0; 16500 break; 16501 case BCM56248_DEVICE_ID_OFFSET_CFG + 2: 16502 case BCM56450_DEVICE_ID_OFFSET_CFG + 2:/* kt2_tdm_A_56450_2 */ 16503 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 16504 "kt2_tdm_A_56450_2 \n"))); 16505 sal_memcpy(arr, 16506 &kt2_tdm_56450A_ref[0], sizeof(kt2_tdm_56450A_ref)); 16507 kt2_tdm_replace(arr,88,33,25,0); 16508 kt2_tdm_replace(arr,88,30,26,0); 16509 olp_port_flag=1; 16510 break; 16511 case BCM56248_DEVICE_ID_OFFSET_CFG + 3: 16512 case BCM56450_DEVICE_ID_OFFSET_CFG + 3:/* kt2_tdm_A_56450_3 */ 16513 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 16514 "kt2_tdm_A_56450_3 \n"))); 16515 sal_memcpy(arr, 16516 &kt2_tdm_56450A_ref[0],sizeof(kt2_tdm_56450A_ref)); 16517 kt2_tdm_replace(arr,88,33,25,0); 16518 olp_port_flag=1; 16519 break; 16520 case BCM56248_DEVICE_ID_OFFSET_CFG + 4: 16521 case BCM56450_DEVICE_ID_OFFSET_CFG + 4:/* kt2_tdm_A_56450_4 */ 16522 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 16523 "kt2_tdm_A_56450_4 \n"))); 16524 sal_memcpy(arr, 16525 &kt2_tdm_56450A_ref[0], sizeof(kt2_tdm_56450A_ref)); 16526 olp_port_flag=1; 16527 break; 16528 case BCM56248_DEVICE_ID_OFFSET_CFG + 5: 16529 case BCM56450_DEVICE_ID_OFFSET_CFG + 5:/* kt2_tdm_A_56450_5 */ 16530 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 16531 "kt2_tdm_A_56450_5 \n"))); 16532 sal_memcpy(arr, 16533 &kt2_tdm_56450A_ref[0], sizeof(kt2_tdm_56450A_ref)); 16534 kt2_tdm_display(unit,arr, tdm_size, row, col); 16535 kt2_tdm_swap(arr,88,21,33); 16536 kt2_tdm_display(unit,arr, tdm_size, row, col); 16537 kt2_tdm_swap(arr,88,30,13); 16538 kt2_tdm_display(unit,arr, tdm_size, row, col); 16539 kt2_tdm_replace(arr,88,13,25,0); 16540 kt2_tdm_display(unit,arr, tdm_size, row, col); 16541 kt2_tdm_replace(arr,88,21,36,0); 16542 kt2_tdm_display(unit,arr, tdm_size, row, col); 16543 kt2_tdm_replace(arr,88,17,13,0); 16544 kt2_tdm_display(unit,arr, tdm_size, row, col); 16545 olp_port_flag=1; 16546 break; 16547 case BCM56248_DEVICE_ID_OFFSET_CFG + 6: 16548 case BCM56450_DEVICE_ID_OFFSET_CFG + 6:/* kt2_tdm_A_56450_6 */ 16549 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 16550 "kt2_tdm_A_56450_6 \n"))); 16551 sal_memcpy(arr, 16552 &kt2_tdm_56450A_ref[0], sizeof(kt2_tdm_56450A_ref)); 16553 kt2_tdm_swap(arr,88,1,17); 16554 kt2_tdm_swap(arr,88,13,21); 16555 kt2_tdm_replace(arr,88,17,39,0); 16556 kt2_tdm_replace(arr,88,21,26,0); 16557 kt2_tdm_replace(arr,88,9,25,0); 16558 kt2_tdm_replace(arr,88,13,36,0); 16559 kt2_tdm_replace(arr,88,40,KT2_IDLE,0); 16560 olp_port_flag=0; 16561 break; 16562 case BCM56248_DEVICE_ID_OFFSET_CFG + 7: 16563 case BCM56450_DEVICE_ID_OFFSET_CFG + 7:/* kt2_tdm_A_56450_7 */ 16564 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 16565 "kt2_tdm_A_56450_7 \n"))); 16566 sal_memcpy(arr, 16567 &kt2_tdm_56450A_ref[0], sizeof(kt2_tdm_56450A_ref)); 16568 kt2_tdm_swap(arr,88,9,17); 16569 kt2_tdm_replace(arr,88,17,26,0); 16570 kt2_tdm_replace(arr,88,21,39,0); 16571 kt2_tdm_replace(arr,88,13,25,0); 16572 16573 kt2_tdm_replace(arr,88,13,KT2_IDLE,0); 16574 kt2_tdm_replace(arr,88,1,KT2_IDLE,0); 16575 kt2_tdm_replace(arr,88,5,KT2_IDLE,0); 16576 kt2_tdm_replace(arr,88,9,KT2_IDLE,0); 16577 kt2_tdm_replace(arr,88,40,KT2_IDLE,0); 16578 tdm_index=0; 16579 for (outer_index=1;outer_index<=4;outer_index++) { 16580 for (inner_index=0;inner_index < 6;inner_index++) { 16581 port = outer_index + inner_index*4; 16582 while(arr[tdm_index] != KT2_IDLE) { 16583 tdm_index++; 16584 } 16585 arr[tdm_index]=port; 16586 } 16587 } 16588 olp_port_flag=0; 16589 break; 16590 case BCM56248_DEVICE_ID_OFFSET_CFG + 8: 16591 case BCM56450_DEVICE_ID_OFFSET_CFG + 8:/* kt2_tdm_A1_56450_8 */ 16592 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 16593 "kt2_tdm_A1_56450_8 \n"))); 16594 sal_memcpy(arr, 16595 &kt2_tdm_56450A1_ref[0], 16596 sizeof(kt2_tdm_56450A1_ref)); 16597 olp_port_flag=1; 16598 break; 16599 case BCM56248_DEVICE_ID_OFFSET_CFG + 9: 16600 case BCM56450_DEVICE_ID_OFFSET_CFG + 9:/* kt2_tdm_A1A_56450_9 */ 16601 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 16602 "kt2_tdm_A1A_56450_9 \n"))); 16603 sal_memcpy(arr, 16604 &kt2_tdm_56450A1A_ref[0], 16605 sizeof(kt2_tdm_56450A1A_ref)); 16606 olp_port_flag=1; 16607 break; 16608 case BCM56248_DEVICE_ID_OFFSET_CFG + 10: 16609 case BCM56450_DEVICE_ID_OFFSET_CFG + 10: /* kt2_tdm_A2_56450_10 */ 16610 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 16611 "kt2_tdm_A2_56450_10 \n"))); 16612 sal_memcpy(arr, 16613 &kt2_tdm_56450A2_ref[0], 16614 sizeof(kt2_tdm_56450A2_ref)); 16615 kt2_tdm_replace(arr,tdm_size,KT2_OLP_PORT,KT2_IDLE,0); 16616 olp_port_flag=0; 16617 break; 16618 case BCM56248_DEVICE_ID_OFFSET_CFG + 11: 16619 case BCM56450_DEVICE_ID_OFFSET_CFG + 11: /* kt2_tdm_A2_56450_11 */ 16620 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 16621 "kt2_tdm_A2_56450_11 \n"))); 16622 sal_memcpy(arr, 16623 &kt2_tdm_56450A2_ref[0], 16624 sizeof(kt2_tdm_56450A2_ref)); 16625 olp_port_flag=1; 16626 break; 16627 case BCM56248_DEVICE_ID_OFFSET_CFG + 12: 16628 case BCM56450_DEVICE_ID_OFFSET_CFG + 12: /* kt2_tdm_A3_56450_12 */ 16629 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 16630 "kt2_tdm_A3_56450_12 \n"))); 16631 sal_memcpy(arr, 16632 &kt2_tdm_56450A3_ref[0], 16633 sizeof(kt2_tdm_56450A3_ref)); 16634 olp_port_flag=1; 16635 break; 16636 case BCM56248_DEVICE_ID_OFFSET_CFG + 13: 16637 case BCM56450_DEVICE_ID_OFFSET_CFG + 13: /* kt2_tdm_A2_56450_13 */ 16638 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 16639 "kt2_tdm_A2_56450_13 \n"))); 16640 sal_memcpy(arr, 16641 &kt2_tdm_56450A2_ref[0], 16642 sizeof(kt2_tdm_56450A2_ref)); 16643 kt2_tdm_replace(arr,tdm_size,26,28,0); 16644 kt2_tdm_replace(arr,tdm_size,25,27,0); 16645 olp_port_flag=1; 16646 break; 16647 case BCM56248_DEVICE_ID_OFFSET_CFG + 14: 16648 case BCM56450_DEVICE_ID_OFFSET_CFG + 14: /* kt2_tdm_A1_56450_14 */ 16649 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 16650 "kt2_tdm_A1_56450_14 \n"))); 16651 sal_memcpy(arr, 16652 &kt2_tdm_56450A1_ref[0], 16653 sizeof(kt2_tdm_56450A1_ref)); 16654 olp_port_flag=1; 16655 break; 16656 case BCM56248_DEVICE_ID_OFFSET_CFG + 15: 16657 case BCM56450_DEVICE_ID_OFFSET_CFG + 15: /* kt2_tdm_A4_56450_15 */ 16658 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 16659 "kt2_tdm_A4_56450_15 \n"))); 16660 memcpy(arr, 16661 &kt2_tdm_56450A4_ref[0], 16662 sizeof(kt2_tdm_56450A4_ref)); 16663 olp_port_flag=1; 16664 break; 16665 case BCM56450_DEVICE_ID_OFFSET_CFG + 16: /* kt2_tdm_F_56450_16 */ 16666 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 16667 "kt2_tdm_F_56450_16 \n"))); 16668 sal_memcpy(arr, 16669 &kt2_tdm_56450F_ref[0], sizeof(kt2_tdm_56450F_ref)); 16670 olp_port_flag=0; 16671 break; 16672 case BCM56452_DEVICE_ID_OFFSET_CFG + 1: 16673 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 16674 "kt2_tdm_C_56452_1 \n"))); 16675 sal_memcpy(arr, 16676 &kt2_tdm_56455C_ref[0], sizeof(kt2_tdm_56455C_ref)); 16677 olp_port_flag=0; 16678 break; 16679 case BCM56452_DEVICE_ID_OFFSET_CFG + 2: 16680 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 16681 "kt2_tdm_C1_56452_2 \n"))); 16682 sal_memcpy(arr, 16683 &kt2_tdm_56452C1_ref[0], sizeof(kt2_tdm_56452C1_ref)); 16684 olp_port_flag=1; 16685 break; 16686 case BCM56452_DEVICE_ID_OFFSET_CFG + 3: 16687 case BCM56452_DEVICE_ID_OFFSET_CFG + 4: 16688 sal_memcpy(arr, 16689 &kt2_tdm_56452C1_ref[0], sizeof(kt2_tdm_56452C1_ref)); 16690 for(port=2;port<=8;port++) { 16691 kt2_tdm_replace(arr,64,port,1,0); 16692 } 16693 for(port=9;port<=16;port++) { 16694 kt2_tdm_replace(arr,64,port,5,0); 16695 } 16696 for(port=17;port<=24;port++) { 16697 kt2_tdm_replace(arr,64,port,KT2_IDLE,0); 16698 } 16699 if (cfg_num == BCM56452_DEVICE_ID_OFFSET_CFG + 3) { 16700 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 16701 "kt2_tdm_C1_56452_3 \n"))); 16702 olp_port_flag=0; 16703 kt2_tdm_replace(arr,64,KT2_OLP_PORT,KT2_IDLE,0); 16704 } else { 16705 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 16706 "kt2_tdm_C1_56452_4 \n"))); 16707 olp_port_flag=1; 16708 } 16709 break; 16710 case BCM56452_DEVICE_ID_OFFSET_CFG + 5: 16711 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 16712 "kt2_tdm_B_56452_5 \n"))); 16713 sal_memcpy(arr, 16714 &kt2_tdm_56452B_new_ref[0], 16715 sizeof(kt2_tdm_56452B_new_ref)); 16716 for(port=1;port<=8;port++) { 16717 kt2_tdm_replace(arr,90,port,KT2_IDLE,0); 16718 } 16719 tdm_index=0; 16720 for (outer_index=1;outer_index<=4;outer_index++) { 16721 for (inner_index=0;inner_index < 6;inner_index++) { 16722 port = outer_index + inner_index*4;/* 1,5,9,13,17,21 16723 2,6,10,14,18,22, 16724 3,7,11,15,19,23, 16725 4,8,12,16,20,24 16726 */ 16727 while(arr[tdm_index] != KT2_IDLE) { 16728 tdm_index++; 16729 } 16730 arr[tdm_index]=port; 16731 } 16732 } 16733 16734 kt2_tdm_replace(arr,90,26,KT2_IDLE,0); 16735 kt2_tdm_replace(arr,90,38,KT2_IDLE,0); 16736 kt2_tdm_replace(arr,90,39,KT2_IDLE,0); 16737 olp_port_flag=1; 16738 break; 16739 case BCM56452_DEVICE_ID_OFFSET_CFG + 6: 16740 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 16741 "kt2_tdm_B1_56452_6 \n"))); 16742 sal_memcpy(arr, 16743 &kt2_tdm_56452B1_ref[0], sizeof(kt2_tdm_56452B1_ref)); 16744 kt2_tdm_replace(arr,60,1,60,0); 16745 kt2_tdm_replace(arr,60,5,60,0); 16746 kt2_tdm_replace(arr,60,25,60,0); 16747 for (inner_index=1;inner_index <= 4;inner_index++) { 16748 for (outer_index=0;outer_index< 6;outer_index++) { 16749 port = inner_index + outer_index*4; 16750 kt2_tdm_replace(arr,60,60,port,1); 16751 } 16752 } 16753 kt2_tdm_replace(arr,60,60,KT2_IDLE,0); 16754 olp_port_flag=1; 16755 break; 16756 case BCM56452_DEVICE_ID_OFFSET_CFG + 7: 16757 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 16758 "kt2_tdm_B_56452_7 \n"))); 16759 sal_memcpy(arr, 16760 &kt2_tdm_56452B_new_ref[0], 16761 sizeof(kt2_tdm_56452B_new_ref)); 16762 for(port=1;port<=8;port++) { 16763 kt2_tdm_replace(arr,90,port,KT2_IDLE,0); 16764 } 16765 tdm_index=0; 16766 for (outer_index=1;outer_index<=4;outer_index++) { 16767 for (inner_index=0;inner_index < 6;inner_index++) { 16768 port = outer_index + inner_index*4;/* 1,5,9,13,17,21 16769 2,6,10,14,18,22, 16770 3,7,11,15,19,23, 16771 4,8,12,16,20,24 16772 */ 16773 while(arr[tdm_index] != KT2_IDLE) { 16774 tdm_index++; 16775 } 16776 arr[tdm_index]=port; 16777 } 16778 } 16779 16780 kt2_tdm_replace(arr,90,25,KT2_IDLE,0); 16781 kt2_tdm_replace(arr,90,35,KT2_IDLE,0); 16782 kt2_tdm_replace(arr,90,36,KT2_IDLE,0); 16783 kt2_tdm_replace(arr,90,37,KT2_IDLE,0); 16784 kt2_tdm_replace(arr,90,26,KT2_IDLE,0); 16785 kt2_tdm_replace(arr,90,38,KT2_IDLE,0); 16786 kt2_tdm_replace(arr,90,39,KT2_IDLE,0); 16787 kt2_tdm_replace(arr,90,40,KT2_IDLE,0); 16788 olp_port_flag=0; 16789 break; 16790 case BCM56452_DEVICE_ID_OFFSET_CFG + 8: 16791 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 16792 "kt2_tdm_B_56452_8 \n"))); 16793 sal_memcpy(arr, 16794 &kt2_tdm_56452B_new_ref[0], 16795 sizeof(kt2_tdm_56452B_new_ref)); 16796 mxqblock = 6; 16797 outer_index= 0; 16798 for (inner_index=0; inner_index < 90; inner_index++) { 16799 if (arr[inner_index] == 25) { 16800 arr[inner_index] = (*kt2_mxqblock_ports[unit]) 16801 [mxqblock][outer_index]; 16802 outer_index = (outer_index + 1) % 4; 16803 } 16804 } 16805 olp_port_flag=0; 16806 break; 16807 case BCM56452_DEVICE_ID_OFFSET_CFG + 9: 16808 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 16809 "kt2_tdm_B1_56452_9 \n"))); 16810 sal_memcpy(arr, 16811 &kt2_tdm_56452B1_ref[0], sizeof(kt2_tdm_56452B1_ref)); 16812 olp_port_flag=1; 16813 break; 16814 case BCM56452_DEVICE_ID_OFFSET_CFG + 10: 16815 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 16816 "kt2_tdm_B2_56452_10 \n"))); 16817 sal_memcpy(arr, 16818 &kt2_tdm_56452B2_ref[0], sizeof(kt2_tdm_56452B2_ref)); 16819 olp_port_flag=1; 16820 break; 16821 case BCM56454_DEVICE_ID_OFFSET_CFG + 1: /* kt2_tdm_D_56454_1 */ 16822 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 16823 "kt2_tdm_D1_56454_1 \n"))); 16824 sal_memcpy(arr, 16825 &kt2_tdm_56454D1_ref[0], sizeof(kt2_tdm_56454D1_ref)); 16826 olp_port_flag=1; 16827 break; 16828 case BCM56454_DEVICE_ID_OFFSET_CFG + 2: /* kt2_tdm_D_56454_2 */ 16829 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 16830 "kt2_tdm_D2_56454_2 \n"))); 16831 sal_memcpy(arr, 16832 &kt2_tdm_56454D1_ref[0], sizeof(kt2_tdm_56454D1_ref)); 16833 kt2_tdm_replace(arr,40,27,25,0); 16834 kt2_tdm_replace(arr,40,28,26,0); 16835 kt2_tdm_replace(arr,40,KT2_OLP_PORT,KT2_IDLE,0); 16836 olp_port_flag=0; 16837 break; 16838 case BCM56455_DEVICE_ID_OFFSET_CFG + 1: 16839 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 16840 "kt2_tdm_C_56455_1 \n"))); 16841 sal_memcpy(arr, 16842 &kt2_tdm_56455C_ref[0], sizeof(kt2_tdm_56455C_ref)); 16843 olp_port_flag = 0; 16844 break; 16845 case BCM56455_DEVICE_ID_OFFSET_CFG + 2: 16846 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 16847 "kt2_tdm_C_56455_2 \n"))); 16848 sal_memcpy(arr, 16849 &kt2_tdm_56455C_ref[0], sizeof(kt2_tdm_56455C_ref)); 16850 kt2_tdm_swap(arr, 84, 26, 28); 16851 kt2_tdm_replace(arr, 84, 27, KT2_IDLE, 0); 16852 kt2_tdm_replace(arr, 84, 28, KT2_IDLE, 0); 16853 for (port = 1; port <= 8; port++) { 16854 kt2_tdm_replace(arr, 84, port, KT2_IDLE, 0); 16855 kt2_tdm_replace(arr, 84, port + 16, KT2_IDLE, 0); 16856 } 16857 olp_port_flag = 0; 16858 break; 16859 case BCM56248_DEVICE_ID_OFFSET_CFG + 16: 16860 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 16861 "kt2_tdm_A3_56450_16 \n"))); 16862 sal_memcpy(arr, 16863 &kt2_tdm_56450A3_ref[0], sizeof(kt2_tdm_56450A3_ref)); 16864 olp_port_flag=1; 16865 break; 16866 case BCM56248_DEVICE_ID_OFFSET_CFG + 17: 16867 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 16868 "kt2_tdm_D2_56248_17 \n"))); 16869 sal_memcpy(arr, 16870 &kt2_tdm_56248D2_ref[0], sizeof(kt2_tdm_56248D2_ref)); 16871 kt2_tdm_replace(arr,40,9,KT2_IDLE,1); 16872 kt2_tdm_replace(arr,40,28,KT2_IDLE,1); 16873 kt2_tdm_replace(arr,40,29,KT2_IDLE,1); 16874 kt2_tdm_replace(arr,40,29,30,1); 16875 olp_port_flag=1; 16876 break; 16877 #ifdef BCM_WARM_BOOT_SUPPORT 16878 case COUNTOF(bcm56450_tdm_info) - 1: 16879 if (SOC_WARM_BOOT(unit)) { 16880 tdm_size = kt2_scache_tdm_info[unit].tdm_size; 16881 tdm_freq = kt2_scache_tdm_info[unit].tdm_freq; 16882 row = kt2_scache_tdm_info[unit].row; 16883 col = kt2_scache_tdm_info[unit].col; 16884 arr = kt2_scache_tdm[unit]; 16885 sal_memcpy(arr, &kt2_scache_tdm[unit][0], 16886 sizeof(kt2_scache_tdm[unit])); 16887 break; 16888 } 16889 #endif 16890 default: olp_port_flag=0; 16891 LOG_CLI((BSL_META_U(unit, 16892 "Not Supported Cfg Value%d \n"),cfg_num)); 16893 return SOC_E_FAIL; 16894 } 16895 kt2_tdm_display(unit, arr, tdm_size, row, col); 16896 /* speed = bcm56450_speed[cfg_num]; */ 16897 retVal=kt2_tdm_verify(unit, arr, tdm_size, tdm_freq, 16898 (uint32 *)bcm56450_speed[unit][cfg_num], 16899 olp_port_flag,&offender_port); 16900 SOC_IF_ERROR_RETURN(retVal); 16901 /* ######################## */ 16902 /* Just for testing purpose */ 16903 /* ######################## */ 16904 #ifdef UNDER_TESTING 16905 for(bcm56450_test_selection=0; 16906 bcm56450_test_selection < sizeof(bcm56450_test_speed)/ 16907 sizeof(bcm56450_test_speed[0]); 16908 bcm56450_test_selection++) { 16909 if ((bcm56450_test_selection >=0) && 16910 (bcm56450_test_selection <=10)) { 16911 pos = 90; row = 18; col = 5;freq=185; 16912 } 16913 if ((bcm56450_test_selection >=11) && 16914 (bcm56450_test_selection <=13)) { 16915 pos = 80; row = 16; col = 5;freq=185; 16916 } 16917 if ((bcm56450_test_selection >=14) && 16918 (bcm56450_test_selection <=16)) { 16919 pos = 84; row = 12; col = 7;freq=155; 16920 } 16921 if ((bcm56450_test_selection >=17) && 16922 (bcm56450_test_selection <=18)) { 16923 pos = 20; row = 4; col = 5;freq=120; 16924 } 16925 if ((bcm56450_test_selection >=19) && 16926 (bcm56450_test_selection <=19)) { 16927 pos = 16; row = 4; col = 4;freq=80; 16928 } 16929 LOG_WARN(BSL_LS_SOC_COMMON, 16930 (BSL_META_U(unit, 16931 "\n###############\n"))); 16932 SOC_IF_ERROR_RETURN(kt2_tdm_generate( 16933 bcm56450_test_speed[bcm56450_test_selection], 16934 40,freq,pos, 16935 kt2_tdm_under_testing,tdm_config_string)); 16936 retVal = kt2_tdm_verify( 16937 unit, 16938 kt2_tdm_under_testing,pos,freq, 16939 bcm56450_test_speed[bcm56450_test_selection], 16940 olp_port_flag,&offender_port); 16941 for(index=0;index<180;index++) { 16942 kt2_tdm_under_testing_idle[index]=KT2_IDLE; 16943 } 16944 sal_memcpy(kt2_tdm_under_testing_idle,kt2_tdm_under_testing, 16945 sizeof(uint32)*pos); 16946 if ((retVal == SOC_E_CONFIG) && (offender_port == KT2_IDLE)) { 16947 do { 16948 switch(offender_port) { 16949 case KT2_IDLE: 16950 if (kt2_tdm_under_testing_idle[pos-1] == KT2_IDLE) { 16951 pos++; 16952 } else { 16953 pos+=2; 16954 } 16955 break; 16956 default:kt2_tdm_under_testing_idle[pos-2]=offender_port; 16957 pos++; 16958 break; 16959 } 16960 if (pos == 180) { 16961 break; 16962 } 16963 retVal = kt2_tdm_verify( 16964 unit, 16965 kt2_tdm_under_testing_idle,pos, freq, 16966 bcm56450_test_speed[bcm56450_test_selection], 16967 olp_port_flag,&offender_port); 16968 }while(retVal == SOC_E_CONFIG); 16969 } 16970 SOC_IF_ERROR_RETURN(retVal); 16971 LOG_WARN(BSL_LS_SOC_COMMON, 16972 (BSL_META_U(unit, 16973 "Configuration:%d:(freq:%d Cycles:%d) %s"), 16974 bcm56450_test_selection,freq,pos, 16975 tdm_config_string)); 16976 kt2_tdm_display(unit,kt2_tdm_under_testing_idle,pos,row,col); 16977 LOG_WARN(BSL_LS_SOC_COMMON, 16978 (BSL_META_U(unit, 16979 "###############\n"))); 16980 } 16981 #endif 16982 break; 16983 default: 16984 return SOC_E_FAIL; 16985 } 16986 16987 /* Disable IARB TDM before programming... */ 16988 SOC_IF_ERROR_RETURN(READ_IARB_TDM_CONTROLr(unit, &rval)); 16989 soc_reg_field_set(unit, IARB_TDM_CONTROLr, &rval, DISABLEf, 1); 16990 soc_reg_field_set(unit, IARB_TDM_CONTROLr, &rval, TDM_WRAP_PTRf, 16991 tdm_size -1); 16992 SOC_IF_ERROR_RETURN(WRITE_IARB_TDM_CONTROLr(unit, rval)); 16993 16994 for (i = 0; i < tdm_size; i++) { 16995 arr_ele = arr[i]; 16996 if (arr_ele <= 41) { /* Non Idle Slots */ 16997 port_enable_value = 1; 16998 } else { 16999 port_enable_value = 0; 17000 } 17001 17002 sal_memset(&iarb_tdm, 0, sizeof(iarb_tdm_table_entry_t)); 17003 soc_IARB_TDM_TABLEm_field32_set(unit, &iarb_tdm, PORT_NUMf, 17004 arr_ele); 17005 SOC_IF_ERROR_RETURN(WRITE_IARB_TDM_TABLEm(unit, SOC_BLOCK_ALL, i, 17006 &iarb_tdm)); 17007 17008 if (0 == (i%2)) { 17009 /* Two entries per mem entry */ 17010 sal_memset(&lls_tdm, 0, sizeof(lls_port_tdm_entry_t)); 17011 soc_LLS_PORT_TDMm_field32_set(unit, &lls_tdm, PORT_ID_0f, arr_ele); 17012 soc_LLS_PORT_TDMm_field32_set(unit, &lls_tdm, 17013 PORT_ID_0_ENABLEf, port_enable_value); 17014 } else { 17015 soc_LLS_PORT_TDMm_field32_set(unit, &lls_tdm, PORT_ID_1f, arr_ele); 17016 soc_LLS_PORT_TDMm_field32_set(unit, &lls_tdm, 17017 PORT_ID_1_ENABLEf, port_enable_value); 17018 SOC_IF_ERROR_RETURN(WRITE_LLS_PORT_TDMm(unit, SOC_BLOCK_ALL, (i/2), 17019 &lls_tdm)); 17020 SOC_IF_ERROR_RETURN(WRITE_LLS_PORT_TDMm(unit, SOC_BLOCK_ALL, 128+(i/2), 17021 &lls_tdm)); 17022 } 17023 } 17024 if (tdm_size % 2) { 17025 LOG_CLI((BSL_META_U(unit, 17026 "Info:Odd TDM Size%d \n"),tdm_size)); 17027 SOC_IF_ERROR_RETURN(WRITE_LLS_PORT_TDMm(unit, SOC_BLOCK_ALL, (i/2), 17028 &lls_tdm)); 17029 SOC_IF_ERROR_RETURN(WRITE_LLS_PORT_TDMm(unit, SOC_BLOCK_ALL, 128+(i/2), 17030 &lls_tdm)); 17031 } 17032 SOC_IF_ERROR_RETURN(READ_IARB_TDM_CONTROLr(unit, &rval)); 17033 soc_reg_field_set(unit, IARB_TDM_CONTROLr, &rval, DISABLEf, 0); 17034 soc_reg_field_set(unit, IARB_TDM_CONTROLr, &rval, TDM_WRAP_PTRf, 17035 tdm_size -1); 17036 SOC_IF_ERROR_RETURN(WRITE_IARB_TDM_CONTROLr(unit, rval)); 17037 17038 17039 rval = 0; 17040 soc_reg_field_set(unit, LLS_TDM_CAL_CFGr, &rval, END_Af, tdm_size - 1); 17041 soc_reg_field_set(unit, LLS_TDM_CAL_CFGr, &rval, END_Bf, tdm_size - 1); 17042 soc_reg_field_set(unit, LLS_TDM_CAL_CFGr, &rval, ENABLEf, 1); 17043 SOC_IF_ERROR_RETURN(WRITE_LLS_TDM_CAL_CFGr(unit, rval)); 17044 soc_katana2_save_tdm_pos(unit, tdm_size,arr); 17045 temp_cfg_num = soc_property_get(unit, spn_BCM5645X_CONFIG,0xFF); 17046 if (temp_cfg_num == 0xFF) { 17047 (*mxqspeeds[unit])[6][0]= bcm56450_speed[unit][cfg_num][25-1]; 17048 (*mxqspeeds[unit])[7][0]= bcm56450_speed[unit][cfg_num][26-1]; 17049 (*mxqspeeds[unit])[8][0]= bcm56450_speed[unit][cfg_num][27-1]; 17050 (*mxqspeeds[unit])[9][0]= bcm56450_speed[unit][cfg_num][28-1]; 17051 } else { 17052 switch(dev_id) { 17053 case BCM55450_DEVICE_ID: 17054 case BCM55455_DEVICE_ID: 17055 case BCM56450_DEVICE_ID: 17056 case BCM56456_DEVICE_ID: 17057 cfg_offset = BCM56450_DEVICE_ID_OFFSET_CFG + temp_cfg_num; 17058 break; 17059 case BCM56452_DEVICE_ID: 17060 case BCM56457_DEVICE_ID: 17061 cfg_offset = BCM56452_DEVICE_ID_OFFSET_CFG + temp_cfg_num; 17062 break; 17063 case BCM56454_DEVICE_ID: 17064 case BCM56458_DEVICE_ID: 17065 cfg_offset = BCM56454_DEVICE_ID_OFFSET_CFG + temp_cfg_num; 17066 break; 17067 case BCM56455_DEVICE_ID: 17068 cfg_offset = BCM56455_DEVICE_ID_OFFSET_CFG + temp_cfg_num; 17069 break; 17070 case BCM56248_DEVICE_ID: 17071 cfg_offset = BCM56248_DEVICE_ID_OFFSET_CFG + temp_cfg_num; 17072 break; 17073 default: 17074 break; 17075 } 17076 17077 (*mxqspeeds[unit])[6][0]= bcm56450_speed[unit][cfg_offset][25-1]; 17078 (*mxqspeeds[unit])[7][0]= bcm56450_speed[unit][cfg_offset][26-1]; 17079 (*mxqspeeds[unit])[8][0]= bcm56450_speed[unit][cfg_offset][27-1]; 17080 (*mxqspeeds[unit])[9][0]= bcm56450_speed[unit][cfg_offset][28-1]; 17081 } 17082 17083 /* In few bcm5645x_configs, WC ports interface type is XFI. In those 17084 * configs, if the phy mode and core mode of the port is operating in single 17085 * port mode, then port can operate at 13g speed. 17086 */ 17087 soc_katana2_get_core_port_mode(unit, 27, &mode); 17088 num_lanes = soc_property_port_get(unit, 27, spn_PORTGROUP, 0); 17089 if ((mode == bcmMxqCorePortModeSingle) && (num_lanes == 4) && 17090 ((*mxqspeeds[unit])[8][0] == 10000)) { 17091 (*mxqspeeds[unit])[8][0] = 13000; 17092 } 17093 17094 soc_katana2_get_core_port_mode(unit, 28, &mode); 17095 num_lanes = soc_property_port_get(unit, 28, spn_PORTGROUP, 0); 17096 if ((mode == bcmMxqCorePortModeSingle) && (num_lanes == 4) && 17097 ((*mxqspeeds[unit])[9][0] == 10000)) { 17098 (*mxqspeeds[unit])[9][0] = 13000; 17099 } 17100 17101 switch((*mxqspeeds[unit])[8][0]) { 17102 case 21000: 17103 (*mxqspeeds[unit])[8][1]= 10000; 17104 (*mxqspeeds[unit])[8][3]= 2500; 17105 break; 17106 case 13000: 17107 (*mxqspeeds[unit])[8][1]= 2500; 17108 (*mxqspeeds[unit])[8][3]= 2500; 17109 break; 17110 case 10000: 17111 if (bcm56450_speed[unit][cfg_num][33-1] == 10000) { 17112 /* We can handle but doubt about TDM mxqspeeds[8][0]= 21000; */ 17113 (*mxqspeeds[unit])[8][1]= 10000; 17114 (*mxqspeeds[unit])[8][3]= 2500; 17115 } else { 17116 (*mxqspeeds[unit])[8][1]= 2500; 17117 (*mxqspeeds[unit])[8][3]= 2500; 17118 } 17119 break; 17120 } 17121 switch((*mxqspeeds[unit])[9][0]) { 17122 case 21000: 17123 (*mxqspeeds[unit])[9][1]= 10000; 17124 (*mxqspeeds[unit])[9][3]= 2500; 17125 break; 17126 case 13000: 17127 (*mxqspeeds[unit])[9][1]= 2500; 17128 (*mxqspeeds[unit])[9][3]= 2500; 17129 break; 17130 case 10000: 17131 if (bcm56450_speed[unit][cfg_num][30-1] == 10000) { 17132 /* We can handle but doubt about TDM mxqspeeds[9][0]= 21000; */ 17133 (*mxqspeeds[unit])[9][1]= 10000; 17134 (*mxqspeeds[unit])[9][3]= 2500; 17135 } else { 17136 (*mxqspeeds[unit])[9][1]= 2500; 17137 (*mxqspeeds[unit])[9][3]= 2500; 17138 } 17139 break; 17140 } 17141 return SOC_E_NONE; 17142 } 17143 soc_error_t 17144 soc_katana2_port_enable_set(int unit, soc_port_t port, int enable) 17145 { 17146 uint8 mxqblock ; 17147 uint8 loop ; 17148 uint32 entry[SOC_MAX_MEM_WORDS]; 17149 soc_info_t *si= &SOC_INFO(unit); 17150 uint32 port_enable = 0; 17151 uint32 regval=0; 17152 17153 SOC_IF_ERROR_RETURN(soc_katana2_get_port_mxqblock(unit,port,&mxqblock)); 17154 if (!SOC_PBMP_MEMBER((PBMP_ALL(unit)), port)) { 17155 return SOC_E_PORT; 17156 } 17157 for(loop=0;loop<KT2_MAX_MXQPORTS_PER_BLOCK; loop++) { 17158 if ((*kt2_mxqblock_ports[unit])[mxqblock][loop] == port) { 17159 break; 17160 } 17161 } 17162 if (loop == KT2_MAX_MXQPORTS_PER_BLOCK) { 17163 return SOC_E_PORT; 17164 } 17165 17166 /* 17167 * For MXQ blocks 8 and 9, PORT_ENABLEf in TXLP_PORT_ENABLEr has to 17168 * be set to enable TXLP-2_MMU requests. LP_ENABLEf is set if 17169 * the port is set linkphy_pbm and config property LINKPHY_ENABLE 17170 * is set. 17171 */ 17172 if (SOC_REG_PORT_VALID(unit, TXLP_PORT_ENABLEr, port)) { 17173 SOC_IF_ERROR_RETURN(READ_TXLP_PORT_ENABLEr(unit, port, ®val)); 17174 port_enable = soc_reg_field_get(unit, TXLP_PORT_ENABLEr, 17175 regval, PORT_ENABLEf); 17176 port_enable |= (1 << loop); 17177 soc_reg_field_set(unit, TXLP_PORT_ENABLEr, ®val, 17178 PORT_ENABLEf,port_enable); 17179 LOG_VERBOSE(BSL_LS_SOC_COMMON, 17180 (BSL_META_U(unit, 17181 "TXLP port_enable=%d\n"), 17182 port_enable)); 17183 SOC_IF_ERROR_RETURN(WRITE_TXLP_PORT_ENABLEr(unit, port, regval)); 17184 } 17185 17186 sal_memset(entry, 0, sizeof(egr_enable_entry_t)); 17187 if ((port == KT2_OLP_PORT) && (si->olp_port[0] == 1) ) { 17188 /* 17189 LOG_CLI((BSL_META_U(unit, 17190 "QUICKTURN:ATTN:Olp Trick Continue" 17191 "Need RegfileChange MXQ:%d:\n"),mxqblock)); 17192 */ 17193 loop = 0; /* Port 0 Field */ 17194 } 17195 if (enable) { 17196 soc_mem_field32_set(unit, EGR_ENABLEm, entry, PRT_ENABLEf, 1); 17197 SOC_IF_ERROR_RETURN 17198 (WRITE_EGR_ENABLEm(unit, MEM_BLOCK_ALL, port, entry)); 17199 17200 } else { 17201 soc_mem_field32_set(unit, EGR_ENABLEm, entry, PRT_ENABLEf, 0); 17202 SOC_IF_ERROR_RETURN 17203 (WRITE_EGR_ENABLEm(unit, MEM_BLOCK_ALL, port, entry)); 17204 } 17205 17206 return SOC_E_NONE; 17207 } 17208 void soc_katana2_mxqblock_reset(int unit, uint8 mxqblock,int active_low) 17209 { 17210 uint32 rval; 17211 soc_field_t hot_swap_reset_fld[]={ 17212 TOP_MXQ0_HOTSWAP_RST_Lf,TOP_MXQ1_HOTSWAP_RST_Lf, 17213 TOP_MXQ2_HOTSWAP_RST_Lf,TOP_MXQ3_HOTSWAP_RST_Lf, 17214 TOP_MXQ4_HOTSWAP_RST_Lf,TOP_MXQ5_HOTSWAP_RST_Lf, 17215 TOP_MXQ6_HOTSWAP_RST_Lf,TOP_MXQ7_HOTSWAP_RST_Lf, 17216 TOP_MXQ8_HOTSWAP_RST_Lf,TOP_MXQ9_HOTSWAP_RST_Lf}; 17217 17218 if (READ_TOP_SOFT_RESET_REGr(unit, &rval) != SOC_E_NONE) { 17219 LOG_CLI((BSL_META_U(unit, 17220 "ATTN: Reading TOP_SOFT_RESET_REG failed \n"))); 17221 return; 17222 } 17223 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, 17224 hot_swap_reset_fld[mxqblock],active_low); 17225 WRITE_TOP_SOFT_RESET_REGr(unit, rval); 17226 17227 } 17228 soc_error_t 17229 soc_katana2_reconfigure_tdm(int unit,uint32 new_tdm_size,uint32 *new_tdm) 17230 { 17231 uint8 new_tdm_no=0; 17232 soc_mem_t tdm_table[]={IARB_TDM_TABLEm , IARB_TDM_TABLE_1m}; 17233 soc_field_t wrap_ptr[]={TDM_WRAP_PTRf , TDM_1_WRAP_PTRf}; 17234 /* 17235 lls_port_tdm_entry_t lls_tdm[128]={{{0}}}; 17236 iarb_tdm_table_entry_t iarb_tdm[256]={{{0}}}; 17237 */ 17238 uint32 lls_tdm_size=0; 17239 lls_port_tdm_entry_t *lls_tdm=NULL; 17240 uint32 iarb_size=0; 17241 iarb_tdm_table_entry_t *iarb_tdm=NULL; 17242 int cfg_num=0; 17243 int iter=0; 17244 17245 uint8 index; 17246 uint32 rval; 17247 17248 if (new_tdm_size > 216) { 17249 return SOC_E_PARAM; 17250 } 17251 /* 17252 if (sal_memcmp(&kt2_current_tdm[0],&new_tdm[0], 17253 sizeof(kt2_current_tdm[0])) == 0) { 17254 return SOC_E_NONE; 17255 } 17256 */ 17257 SOC_IF_ERROR_RETURN(_soc_katana2_get_cfg_num(unit, &cfg_num)); 17258 if (cfg_num >= (sizeof(bcm56450_tdm)/sizeof(bcm56450_tdm[0]))) { 17259 return SOC_E_FAIL; 17260 } 17261 17262 SOC_IF_ERROR_RETURN(READ_IARB_TDM_CONTROLr(unit, &rval)); 17263 old_tdm_no[unit] = soc_reg_field_get(unit, IARB_TDM_CONTROLr, rval, SELECT_TDMf); 17264 new_tdm_no = (old_tdm_no[unit] + 1)%2; 17265 17266 #if 0 17267 /* Disable IARB TDM before programming... */ 17268 SOC_IF_ERROR_RETURN(READ_IARB_TDM_CONTROLr(unit, &rval)); 17269 soc_reg_field_set(unit, IARB_TDM_CONTROLr, &rval, DISABLEf, 1); 17270 SOC_IF_ERROR_RETURN(WRITE_IARB_TDM_CONTROLr(unit, rval)); 17271 #endif 17272 iarb_size = soc_mem_index_count(unit,IARB_TDM_TABLEm) * 17273 sizeof(iarb_tdm_table_entry_t); 17274 iarb_tdm = soc_cm_salloc(unit,iarb_size, "iarb_tdm_table_entry_t"); 17275 if (iarb_tdm == NULL) { 17276 return SOC_E_MEMORY; 17277 } 17278 sal_memset(iarb_tdm,0,iarb_size); 17279 lls_tdm_size = soc_mem_index_count(unit,LLS_PORT_TDMm) * 17280 sizeof(lls_port_tdm_entry_t); 17281 lls_tdm = soc_cm_salloc(unit,lls_tdm_size, "lls_port_tdm_entry_t"); 17282 if (lls_tdm == NULL) { 17283 soc_cm_sfree(unit,iarb_tdm); 17284 return SOC_E_MEMORY; 17285 } 17286 sal_memset(lls_tdm,0,lls_tdm_size); 17287 17288 for (index = 0; index < new_tdm_size; index++) { 17289 soc_IARB_TDM_TABLEm_field32_set(unit, &iarb_tdm[index], PORT_NUMf, 17290 new_tdm[index]); 17291 } 17292 SOC_IF_ERROR_RETURN(soc_mem_write_range(unit, tdm_table[new_tdm_no], MEM_BLOCK_ALL, 0, 17293 new_tdm_size, iarb_tdm)); 17294 soc_cm_sfree(unit,iarb_tdm); 17295 17296 for (index = 0; index < new_tdm_size/2; index++) { 17297 soc_LLS_PORT_TDMm_field32_set(unit, &lls_tdm[index], 17298 PORT_ID_0f, new_tdm[index*2]); 17299 if ( new_tdm[index*2] <= 41) { 17300 soc_LLS_PORT_TDMm_field32_set(unit, &lls_tdm[index], 17301 PORT_ID_0_ENABLEf, 1); 17302 } else { 17303 LOG_VERBOSE(BSL_LS_SOC_COMMON, 17304 (BSL_META_U(unit, 17305 "IDLE SLOTs so PORT_ID_0_ENABLEf=0 for index=%d\n"), 17306 index)); 17307 soc_LLS_PORT_TDMm_field32_set(unit, &lls_tdm[index], 17308 PORT_ID_0_ENABLEf, 0); 17309 } 17310 soc_LLS_PORT_TDMm_field32_set(unit, &lls_tdm[index], 17311 PORT_ID_1f, new_tdm[(index*2) + 1]); 17312 if ( new_tdm[(index*2)+1] <= 41) { 17313 soc_LLS_PORT_TDMm_field32_set(unit, &lls_tdm[index], 17314 PORT_ID_1_ENABLEf, 1); 17315 } else { 17316 LOG_VERBOSE(BSL_LS_SOC_COMMON, 17317 (BSL_META_U(unit, 17318 "IDLE SLOTs so PORT_ID_1_ENABLEf=0 for index=%d\n"), 17319 index)); 17320 soc_LLS_PORT_TDMm_field32_set(unit, &lls_tdm[index], 17321 PORT_ID_1_ENABLEf, 0); 17322 } 17323 } 17324 if (new_tdm_size % 2) { 17325 LOG_CLI((BSL_META_U(unit, 17326 "ODD TDM SIZE \n"))); 17327 soc_LLS_PORT_TDMm_field32_set(unit, &lls_tdm[index*2], 17328 PORT_ID_0_ENABLEf, 1); 17329 soc_LLS_PORT_TDMm_field32_set(unit, &lls_tdm[index*2], 17330 PORT_ID_0f, new_tdm[(index*2)]); 17331 soc_LLS_PORT_TDMm_field32_set(unit, &lls_tdm[(index*2)+1], 17332 PORT_ID_1_ENABLEf, 0); 17333 soc_LLS_PORT_TDMm_field32_set(unit, &lls_tdm[(index*2)+1], 17334 PORT_ID_1f, 0); 17335 index++; 17336 } 17337 SOC_IF_ERROR_RETURN(soc_mem_write_range(unit, LLS_PORT_TDMm, MEM_BLOCK_ALL, 17338 new_tdm_no*128, (new_tdm_no*128) + index, 17339 lls_tdm)); 17340 soc_cm_sfree(unit,lls_tdm); 17341 17342 17343 SOC_IF_ERROR_RETURN(READ_IARB_TDM_CONTROLr(unit, &rval)); 17344 soc_reg_field_set(unit, IARB_TDM_CONTROLr, &rval, DISABLEf, 0); 17345 soc_reg_field_set(unit, IARB_TDM_CONTROLr, &rval, 17346 wrap_ptr[new_tdm_no],new_tdm_size -1); 17347 soc_reg_field_set(unit, IARB_TDM_CONTROLr, &rval, SELECT_TDMf, new_tdm_no); 17348 SOC_IF_ERROR_RETURN(WRITE_IARB_TDM_CONTROLr(unit, rval)); 17349 if (bsl_check(bslLayerSoc, bslSourceCommon, bslSeverityVerbose, unit)) { 17350 kt2_tdm_display(unit,new_tdm,new_tdm_size, 17351 bcm56450_tdm_info[cfg_num].row, 17352 bcm56450_tdm_info[cfg_num].col); 17353 } 17354 SOC_IF_ERROR_RETURN(WRITE_LLS_TDM_CAL_CFG_SWITCHr(unit, 1)); 17355 if ((SAL_BOOT_BCMSIM || SAL_BOOT_PLISIM)) { 17356 SOC_IF_ERROR_RETURN(READ_LLS_TDM_CAL_CFGr(unit, &rval)); 17357 soc_reg_field_set(unit, LLS_TDM_CAL_CFGr, &rval, 17358 CURRENT_CALENDARf,new_tdm_no); 17359 SOC_IF_ERROR_RETURN(WRITE_LLS_TDM_CAL_CFGr(unit, rval)); 17360 } 17361 do { 17362 SOC_IF_ERROR_RETURN(READ_LLS_TDM_CAL_CFGr(unit, &rval)); 17363 sal_udelay(100); 17364 if (soc_reg_field_get(unit, LLS_TDM_CAL_CFGr, rval, 17365 CURRENT_CALENDARf) == new_tdm_no) { 17366 break; 17367 } 17368 } while (iter++ < 100000); 17369 if (iter >= 100000) { 17370 LOG_ERROR(BSL_LS_SOC_COMMON, 17371 (BSL_META_U(unit, 17372 "LLS Calendar switch failed !!\n"))); 17373 return SOC_E_INTERNAL; 17374 } 17375 old_tdm_no[unit] = new_tdm_no; 17376 #if 1 17377 soc_katana2_save_tdm_pos(unit, new_tdm_size,new_tdm); 17378 #endif 17379 17380 return SOC_E_NONE; 17381 } 17382 static 17383 void soc_katana2_save_tdm_pos(int unit, uint8 new_tdm_size,uint32 *new_tdm) 17384 { 17385 uint8 pos=0; 17386 uint8 port=0; 17387 uint8 mxqblock=0; 17388 uint8 total_slots=0; 17389 sal_memset(kt2_tdm_pos_info,0,sizeof(kt2_tdm_pos_info)); 17390 for (pos=0;pos < new_tdm_size ; pos++) { 17391 port= new_tdm[pos]; 17392 if ((port == KT2_IDLE) || (port == KT2_IDLE1) || 17393 (port == KT2_LPBK_PORT) || (port == KT2_CMIC_PORT) /* || 17394 (port == KT2_OLP_PORT) */) { /* QUICKTURN:ATTN */ 17395 continue; 17396 } 17397 mxqblock = (*kt2_port_to_mxqblock[unit])[port-1]; 17398 total_slots = kt2_tdm_pos_info[mxqblock].total_slots; 17399 kt2_tdm_pos_info[mxqblock].pos[total_slots]=pos; 17400 kt2_tdm_pos_info[mxqblock].total_slots++; 17401 } 17402 sal_memcpy(kt2_current_tdm,new_tdm,new_tdm_size*sizeof(new_tdm[0])); 17403 old_tdm_no[unit]=0; 17404 kt2_current_tdm_size=new_tdm_size; 17405 } 17406 17407 static soc_error_t 17408 _soc_katana2_tdm_feasibility_check(int unit, soc_port_t port, int speed, 17409 uint8 *mxqblock, uint8 *sub_port, 17410 uint8 *min_tdm_cycles) 17411 { 17412 uint8 mxqblock_local=0; 17413 uint8 sub_port_local=0; 17414 uint32 speed_index=0; 17415 soc_field_t wc_xfi_mode_sel_fld[]={WC0_8_XFI_MODE_SELf,WC1_8_XFI_MODE_SELf}; 17416 uint32 wc_8_xfi_mode_sel_val = 0; 17417 uint32 top_misc_control_1_val = 0; 17418 if (kt2_tdm_update_flag == 0) { 17419 return SOC_E_NONE; 17420 } 17421 SOC_IF_ERROR_RETURN(soc_katana2_get_port_mxqblock(unit,port, 17422 &mxqblock_local)); 17423 sub_port_local = (*kt2_port_to_mxqblock_subports[unit])[port-1]; 17424 switch(speed) { 17425 case 1000: 17426 speed_index=0; 17427 break; 17428 case 2500: 17429 speed_index=2; 17430 break; 17431 case 10000: 17432 speed_index=3; 17433 break; 17434 case 13000: 17435 speed_index=4; 17436 break; 17437 case 21000: 17438 speed_index=6; 17439 break; 17440 default: 17441 LOG_CLI((BSL_META_U(unit, 17442 "Check:Invalid Speed:%d \n"), speed)); 17443 return SOC_E_CONFIG; 17444 } 17445 if (kt2_current_tdm_cycles_info[speed_index].min_tdm_cycles == 0) { 17446 LOG_CLI((BSL_META_U(unit, 17447 "Check:Invalid Minimum TDM Cycles=0 \n"))); 17448 return SOC_E_CONFIG; 17449 } 17450 if (kt2_tdm_pos_info[mxqblock_local].total_slots == 0) { 17451 if (((mxqblock_local == 8) || (mxqblock_local == 9)) && 17452 ((sub_port_local == 1) || (sub_port_local == 3))) { 17453 /*Need To Check XFI Mode then */ 17454 SOC_IF_ERROR_RETURN(READ_TOP_MISC_CONTROL_1r( 17455 unit,&top_misc_control_1_val)); 17456 wc_8_xfi_mode_sel_val = soc_reg_field_get( 17457 unit, TOP_MISC_CONTROL_1r, 17458 top_misc_control_1_val, 17459 wc_xfi_mode_sel_fld[mxqblock_local-8]); 17460 if (wc_8_xfi_mode_sel_val == 0) { 17461 LOG_CLI((BSL_META_U(unit, 17462 "Check:Total Slots in corresponding" 17463 " MXQBlock=%d is zero \n"), mxqblock_local)); 17464 return SOC_E_CONFIG; 17465 } 17466 mxqblock_local -= 2; 17467 sub_port_local -= 1; 17468 if (kt2_tdm_pos_info[mxqblock_local].total_slots ==0) { 17469 LOG_CLI((BSL_META_U(unit, 17470 "Check:Total Slots in corresponding" 17471 " MXQBlock=%d is zero \n"), mxqblock_local)); 17472 return SOC_E_CONFIG; 17473 } 17474 } else { 17475 LOG_CLI((BSL_META_U(unit, 17476 "Check: Total Slots in corresponding MXQBlock=%d" 17477 " is zero \n"), mxqblock_local)); 17478 return SOC_E_CONFIG; 17479 } 17480 } 17481 if(mxqblock != NULL) { 17482 *mxqblock = mxqblock_local; 17483 } 17484 if(sub_port != NULL) { 17485 *sub_port = sub_port_local; 17486 } 17487 if(min_tdm_cycles != NULL) { 17488 *min_tdm_cycles = kt2_current_tdm_cycles_info[speed_index]. 17489 min_tdm_cycles; 17490 } 17491 return SOC_E_NONE; 17492 } 17493 17494 int 17495 _soc_katana2_perq_flex_counters_init(int unit, uint32 drop_mask) 17496 { 17497 _soc_katana2_counter_info_t *counter_info; 17498 uint32 rval; 17499 int index, field_index, i, j, i_max = 3, j_max = 16; 17500 int flags = 0, num_elem = 0, enq_stats = 0; 17501 int counter_index = 0, elem_size = 4, size = 0; 17502 _soc_katana2_counter_type_t type = _SOC_COUNTER_TYPE_MAX; 17503 soc_counter_non_dma_id_t non_dma_id; 17504 _sb2_cosq_counter_mem_map_t *mem_map; 17505 soc_reg_t dtype_reg[] = { 17506 CTR_DEQ_DTYPE_TBL0r, 17507 CTR_DEQ_DTYPE_TBL1r, 17508 CTR_DEQ_DTYPE_TBL2r 17509 }; 17510 soc_field_t dtype_field[] = { 17511 DTYPE0f, DTYPE1f, DTYPE2f, 17512 DTYPE3f, DTYPE4f, DTYPE5f, 17513 DTYPE6f, DTYPE7f, DTYPE8f, 17514 DTYPE9f, DTYPE10f, DTYPE11f, 17515 DTYPE12f, DTYPE13f,DTYPE14f, 17516 DTYPE15f 17517 }; 17518 soc_field_t act_field[3] = {ACTIVE0f, ACTIVE1f, ACTIVE2f}; 17519 soc_field_t seg_field[3] = {SEG0f, SEG1f, SEG2f}; 17520 soc_sb2_cosq_counter_mem_map_get(unit, &num_elem, &mem_map); 17521 17522 /* Setup MMU counter pool segment start address, consider each 1K block 17523 as separate segment */ 17524 for (i = 0; i < 12; i++) { 17525 if ((!soc_feature(unit, soc_feature_cosq_gport_stat_ability) && 17526 ((i % 4) != 0)) || 17527 ((soc_feature(unit, soc_feature_counter_toggled_read) && 17528 (i == 8)))) { 17529 /* 17530 * Create 3 segments each with 4K counters 17531 * Seg0(total enq drop pkts) seg_start address 0 17532 * Seg4(red enq drop pkts) seg_start address 4 * 1024 17533 * Seg8(deq stats)) seg_start_address 8 * 1024 17534 */ 17535 continue; 17536 } 17537 rval = 0; 17538 soc_reg_field_set(unit, CTR_SEGMENT_STARTr, &rval, SEG_STARTf, (i * 1024)); 17539 SOC_IF_ERROR_RETURN 17540 (soc_reg32_set(unit, CTR_SEGMENT_STARTr,REG_PORT_ANY, i, rval)); 17541 } 17542 17543 /* Default Configuration */ 17544 /* Cosq_stats - 17545 * CTR_FLEX_COUNT_0 = Total ENQ discarded 17546 * CTR_FLEX_COUNT_4 = Red ENQ discarded 17547 * CTR_FLEX_COUNT_8 = Total DEQ 17548 */ 17549 17550 /* Cosq_gport_stats - 17551 * CTR_FLEX_COUNT_1 = Total ENQ Accepted 17552 * CTR_FLEX_COUNT_2 = Green ENQ discarded 17553 * CTR_FLEX_COUNT_3 = Yellow ENQ discarded 17554 * CTR_FLEX_COUNT_5 = Green ENQ Accepted 17555 * CTR_FLEX_COUNT_6 = Yellow ENQ Accepted 17556 * CTR_FLEX_COUNT_7 = Red ENQ Accepted 17557 */ 17558 17559 counter_info = _soc_katana2_counter_info; 17560 17561 /* reset the previously configured registers*/ 17562 rval = 0; 17563 for ( i = 0; i < 3; i++) { 17564 soc_reg_field_set(unit, CTR_ENQ_STATS_CFGr, &rval, act_field[i], 0); 17565 soc_reg_field_set(unit, CTR_ENQ_STATS_CFGr, &rval, seg_field[i], 0); 17566 SOC_IF_ERROR_RETURN 17567 (soc_reg32_set(unit, CTR_ENQ_STATS_CFGr,REG_PORT_ANY,0, rval)); 17568 if (i < 2) { 17569 soc_reg_field_set(unit, CTR_DEQ_STATS_CFGr, &rval, act_field[i], 0); 17570 soc_reg_field_set(unit, CTR_DEQ_STATS_CFGr, &rval, seg_field[i], 0); 17571 SOC_IF_ERROR_RETURN 17572 (soc_reg32_set(unit, CTR_DEQ_STATS_CFGr, REG_PORT_ANY,0 , rval)); 17573 } 17574 } 17575 17576 size = (sizeof(_soc_katana2_counter_info) / sizeof(_soc_katana2_counter_info[0])); 17577 /*intializing the segment in counter info */ 17578 for ( i = 0; i < size; i++) { 17579 _soc_katana2_counter_info[i].segment = 0; 17580 } 17581 17582 for (counter_index = 0; counter_index < num_elem; counter_index+=elem_size) { 17583 17584 non_dma_id = mem_map[counter_index].non_dma_id; 17585 field_index = counter_index/elem_size; 17586 rval = 0; 17587 if ((non_dma_id == SOC_COUNTER_NON_DMA_COSQ_DROP_PKT)|| 17588 (non_dma_id == SOC_COUNTER_NON_DMA_COSQ_ACCEPT_PKT)) { 17589 soc_reg_field_set(unit, CTR_ENQ_STATS_CFGr, &rval, act_field[field_index], 1); 17590 soc_reg_field_set(unit, CTR_ENQ_STATS_CFGr, &rval, seg_field[field_index], counter_index); 17591 } 17592 switch (non_dma_id){ 17593 case SOC_COUNTER_NON_DMA_COSQ_DROP_PKT: 17594 type = _SOC_COUNTER_TYPE_DROP_ENQ; 17595 for ( i = _SOC_COUNTER_TYPE_DROP_ENQ_GREEN; 17596 i <= _SOC_COUNTER_TYPE_DROP_ENQ_RED; i++) { 17597 SOC_IF_ERROR_RETURN 17598 (soc_reg32_set(unit, CTR_ENQ_STATS_CFGr, 17599 REG_PORT_ANY, 17600 counter_info[i].index, 17601 rval)); 17602 flags |= (1 << i); 17603 } 17604 break; 17605 case SOC_COUNTER_NON_DMA_COSQ_ACCEPT_PKT: 17606 type = _SOC_COUNTER_TYPE_ACCEPT_ENQ; 17607 for ( i = _SOC_COUNTER_TYPE_ACCEPT_ENQ_GREEN; 17608 i <= _SOC_COUNTER_TYPE_ACCEPT_ENQ_RED; i++) { 17609 SOC_IF_ERROR_RETURN 17610 (soc_reg32_set(unit, CTR_ENQ_STATS_CFGr, 17611 REG_PORT_ANY, 17612 counter_info[i].index, 17613 rval)); 17614 flags |= (1 << i); 17615 } 17616 break; 17617 case SOC_COUNTER_NON_DMA_COSQ_DROP_PKT_GREEN: 17618 type = _SOC_COUNTER_TYPE_DROP_ENQ_GREEN; 17619 break; 17620 17621 case SOC_COUNTER_NON_DMA_COSQ_DROP_PKT_RED: 17622 type = _SOC_COUNTER_TYPE_DROP_ENQ_RED; 17623 break; 17624 17625 case SOC_COUNTER_NON_DMA_COSQ_DROP_PKT_YELLOW: 17626 type = _SOC_COUNTER_TYPE_DROP_ENQ_YELLOW; 17627 break; 17628 17629 case SOC_COUNTER_NON_DMA_COSQ_ACCEPT_PKT_GREEN: 17630 type = _SOC_COUNTER_TYPE_ACCEPT_ENQ_GREEN; 17631 break; 17632 17633 case SOC_COUNTER_NON_DMA_COSQ_ACCEPT_PKT_RED: 17634 type = _SOC_COUNTER_TYPE_ACCEPT_ENQ_RED; 17635 break; 17636 17637 case SOC_COUNTER_NON_DMA_COSQ_ACCEPT_PKT_YELLOW: 17638 type = _SOC_COUNTER_TYPE_ACCEPT_ENQ_YELLOW; 17639 break; 17640 17641 case SOC_COUNTER_NON_DMA_EGR_PERQ_XMT_PKT: 17642 type = _SOC_COUNTER_TYPE_ACCEPT_DEQ; 17643 /* enable deq stats */ 17644 for (i = 0; i < i_max; i++) { 17645 rval = 0; 17646 for (j = 0; j < j_max; j++) { 17647 if ((dtype_reg[i] == CTR_DEQ_DTYPE_TBL2r) && (j > 9)) { 17648 continue; 17649 } 17650 soc_reg_field_set(unit, dtype_reg[i], &rval, dtype_field[j], 2); 17651 } 17652 SOC_IF_ERROR_RETURN 17653 (soc_reg32_set(unit, dtype_reg[i], REG_PORT_ANY, 0, rval)); 17654 } 17655 /* set deq stats config */ 17656 rval = 0; 17657 index = counter_info[type].index; 17658 soc_reg_field_set(unit, CTR_DEQ_STATS_CFGr, &rval, ACTIVE0f, 1); 17659 soc_reg_field_set(unit, CTR_DEQ_STATS_CFGr, &rval, SEG0f, counter_index); 17660 SOC_IF_ERROR_RETURN 17661 (soc_reg32_set(unit, CTR_DEQ_STATS_CFGr, REG_PORT_ANY, index, rval)); 17662 17663 enq_stats++; 17664 break; 17665 default: 17666 /*should not reach here*/ 17667 break; 17668 } 17669 17670 if (type < size) { 17671 _soc_katana2_counter_info[type].segment = counter_index; 17672 } 17673 if ((type >= _SOC_COUNTER_TYPE_DROP_ENQ_GREEN) 17674 && (type <= _SOC_COUNTER_TYPE_ACCEPT_ENQ_RED)){ 17675 17676 rval = 0; 17677 index = counter_info[type].index; 17678 if (flags & (1 << type)) { 17679 SOC_IF_ERROR_RETURN 17680 (soc_reg32_get(unit, CTR_ENQ_STATS_CFGr, 17681 REG_PORT_ANY, index, &rval)); 17682 } 17683 soc_reg_field_set(unit, CTR_ENQ_STATS_CFGr, &rval, act_field[field_index-enq_stats], 1); 17684 soc_reg_field_set(unit, CTR_ENQ_STATS_CFGr, &rval, seg_field[field_index-enq_stats], counter_index); 17685 SOC_IF_ERROR_RETURN 17686 (soc_reg32_set(unit, CTR_ENQ_STATS_CFGr, 17687 REG_PORT_ANY, 17688 counter_info[type].index, 17689 rval)); 17690 } 17691 } 17692 /* This is set to 1 so that we count only thdo drops in the out drops*/ 17693 SOC_IF_ERROR_RETURN(READ_THDO_DROP_CTR_CONFIGr(unit, &rval)); 17694 17695 /*drop mask eliminates the packet drop counts for masked out drop types.*/ 17696 soc_reg_field_set(unit, THDO_DROP_CTR_CONFIGr, &rval, OP_DROP_MASKf,drop_mask); 17697 soc_reg_field_set(unit, THDO_DROP_CTR_CONFIGr, &rval, OP_CNT_CFGf, 1); 17698 17699 SOC_IF_ERROR_RETURN(WRITE_THDO_DROP_CTR_CONFIGr(unit, rval)); 17700 17701 return SOC_E_NONE; 17702 } 17703 17704 soc_error_t 17705 soc_katana2_tdm_feasibility_check(int unit, soc_port_t port, int speed) 17706 { 17707 return _soc_katana2_tdm_feasibility_check(unit, port, speed,NULL,NULL,NULL); 17708 } 17709 soc_error_t 17710 soc_katana2_update_tdm(int unit, soc_port_t port, int speed) 17711 { 17712 uint8 mxqblock=0; 17713 uint8 sub_port=0; 17714 uint8 min_tdm_cycles=0; 17715 uint8 available_tdm_slots=0; 17716 uint32 *new_tdm = NULL; 17717 uint8 spacing=0; 17718 uint8 loop=0; 17719 uint8 pos=0; 17720 if (kt2_tdm_update_flag == 0) { 17721 return SOC_E_NONE; 17722 } 17723 SOC_IF_ERROR_RETURN(_soc_katana2_tdm_feasibility_check( 17724 unit, port, speed, 17725 &mxqblock , &sub_port,&min_tdm_cycles)); 17726 if (min_tdm_cycles == 0) { 17727 /*Shouldn't have been here.. */ 17728 return SOC_E_INTERNAL; 17729 } 17730 new_tdm = soc_cm_salloc(unit, 256 * sizeof(uint32), 17731 "oob new_tdm"); 17732 if (new_tdm == NULL) { 17733 return BCM_E_MEMORY; 17734 } 17735 17736 available_tdm_slots=kt2_tdm_pos_info[mxqblock].total_slots; 17737 sal_memcpy(&new_tdm[0],&kt2_current_tdm[0], 17738 kt2_current_tdm_size *sizeof(kt2_current_tdm[0])); 17739 spacing = available_tdm_slots / min_tdm_cycles; 17740 for (loop=0; loop < available_tdm_slots; loop++) { 17741 pos = kt2_tdm_pos_info[mxqblock].pos[loop]; 17742 if (loop % spacing == 0) { 17743 new_tdm[pos]= port; 17744 } else { 17745 new_tdm[pos]= KT2_IDLE; 17746 } 17747 } 17748 soc_katana2_reconfigure_tdm(unit,kt2_current_tdm_size,new_tdm); 17749 sal_memcpy(kt2_current_tdm,new_tdm, 17750 kt2_current_tdm_size*sizeof(new_tdm[0])); 17751 soc_cm_sfree(unit, new_tdm); 17752 return SOC_E_NONE; 17753 } 17754 soc_error_t soc_katana2_get_port_mxqblock( 17755 int unit, soc_port_t port,uint8 *mxqblock) 17756 { 17757 if (!((port >=1) && (port <= 40))) { 17758 return SOC_E_PORT; 17759 } 17760 *mxqblock = (*kt2_port_to_mxqblock[unit])[port-1]; 17761 return SOC_E_NONE; 17762 } 17763 soc_error_t soc_katana2_get_core_port_mode( 17764 int unit,soc_port_t port,bcmMxqCorePortMode_t *mode) 17765 { 17766 uint8 mxqblock = 0; 17767 uint8 loop =0; 17768 uint8 mxqport_used = 0; 17769 17770 SOC_IF_ERROR_RETURN(soc_katana2_get_port_mxqblock(unit,port,&mxqblock)); 17771 for(loop=0;loop<KT2_MAX_MXQPORTS_PER_BLOCK; loop++) { 17772 if (SOC_PBMP_MEMBER((PBMP_ALL(unit)), 17773 (*kt2_mxqblock_ports[unit])[mxqblock][loop])) { 17774 mxqport_used++; 17775 } 17776 } 17777 switch(mxqport_used){ 17778 case 0: return SOC_E_PARAM; 17779 case 1: *mode=bcmMxqCorePortModeSingle; /* 0=SINGLE */ 17780 break; 17781 case 2: *mode=bcmMxqCorePortModeDual; /* 1=DUAL */ 17782 break; 17783 case 3: 17784 case 4: *mode=bcmMxqCorePortModeQuad; /* 2=QUAD */ 17785 break; 17786 } 17787 return SOC_E_NONE; 17788 } 17789 soc_error_t 17790 soc_katana2_get_phy_connection_mode(int unit,soc_port_t port,int mxqblock, 17791 bcmMxqConnection_t *connection) 17792 { 17793 /* port is not being used..Might remove it later */ 17794 17795 soc_field_t wc_xfi_mode_sel_fld[]={WC0_8_XFI_MODE_SELf,WC1_8_XFI_MODE_SELf}; 17796 uint32 wc_8_xfi_mode_sel_val = 0; 17797 uint32 top_misc_control_1_val = 0; 17798 17799 17800 if (mxqblock <= 5) { /* MXQPORT is connected to Unicore */ 17801 *connection=bcmMqxConnectionUniCore; 17802 return SOC_E_NONE; 17803 } 17804 if ((mxqblock >= 6) && (mxqblock <= 7)) { 17805 /*Need To Check XFI Mode then */ 17806 if (!(SOC_CONTROL(unit)->soc_flags & SOC_F_INITED)) { 17807 /* Not Initialized yet so OK to return UNICORE */ 17808 *connection=bcmMqxConnectionUniCore; 17809 return SOC_E_NONE; 17810 } 17811 SOC_IF_ERROR_RETURN(READ_TOP_MISC_CONTROL_1r( 17812 unit,&top_misc_control_1_val)); 17813 wc_8_xfi_mode_sel_val = soc_reg_field_get( 17814 unit, TOP_MISC_CONTROL_1r, 17815 top_misc_control_1_val, 17816 wc_xfi_mode_sel_fld[mxqblock-6]); 17817 if (wc_8_xfi_mode_sel_val) { 17818 *connection=bcmMqxConnectionWarpCore; 17819 } else { 17820 *connection=bcmMqxConnectionUniCore; 17821 } 17822 return SOC_E_NONE; 17823 } 17824 if ((mxqblock >= 8) && (mxqblock <= 9)) {/*MXQPORT is connected to Warpcore*/ 17825 *connection=bcmMqxConnectionWarpCore; 17826 return SOC_E_NONE; 17827 } 17828 return SOC_E_PARAM; 17829 } 17830 soc_error_t soc_katana2_get_phy_port_mode( 17831 int unit, soc_port_t port,int speed, bcmMxqPhyPortMode_t *mode) 17832 { 17833 int mxqblock=0; 17834 bcmMxqConnection_t connection; 17835 soc_info_t *si=&SOC_INFO(unit); 17836 int lanes = 0; 17837 phy_ctrl_t *int_pc; 17838 17839 if (!((port >=1) && (port <= 40))) { 17840 return SOC_E_PORT; 17841 } 17842 if (!SOC_PBMP_MEMBER((PBMP_ALL(unit)), port)) { 17843 return SOC_E_PORT; 17844 } 17845 si = &SOC_INFO(unit); 17846 SOC_IF_ERROR_RETURN(_bcm_kt2_port_lanes_get(unit, port, &lanes)); 17847 int_pc = INT_PHY_SW_STATE(unit, port); 17848 /* If speed is less than 2.5G, irrespective of unicore,warpcore,phy_mode 17849 will be zero */ 17850 if (speed <= 2500) { 17851 /* Set PHY_PORT_MODE to dual port mode when dual port speed is 1G or 2.5G at 6.25G VCO */ 17852 if ((lanes == 2) && soc_property_port_get(unit, port, spn_SERDES_1000X_AT_6250_VCO, 0)) { 17853 *mode = bcmMxqPhyPortModeDual; 17854 if (int_pc) { 17855 int_pc->phy_mode = PHYCTRL_SINGLE_LANE_IN_DUAL_PORT_MODE; 17856 } 17857 } else { 17858 *mode = bcmMxqPhyPortModeQuad; 17859 if (int_pc) { 17860 int_pc->phy_mode = PHYCTRL_ONE_LANE_PORT; 17861 } 17862 } 17863 17864 return SOC_E_NONE; 17865 } 17866 17867 mxqblock = (*kt2_port_to_mxqblock[unit])[port-1]; 17868 SOC_IF_ERROR_RETURN(soc_katana2_get_phy_connection_mode( 17869 unit,port,mxqblock,&connection)); 17870 switch(connection) { 17871 case bcmMqxConnectionUniCore: 17872 if ((speed == 10000) || (speed==12000) || (speed==13000)) { 17873 *mode=bcmMxqPhyPortModeSingle; 17874 return SOC_E_NONE; 17875 } 17876 break; 17877 case bcmMqxConnectionWarpCore: 17878 if (SOC_IS_KATANA2(unit) && SAL_BOOT_QUICKTURN) { 17879 if ((speed == 10000)) { 17880 if (SOC_PBMP_MEMBER(si->linkphy_pbm, port)) { 17881 LOG_CLI((BSL_META_U(unit, 17882 "QUICKTURN:ATTN:LinkPhyPortDualMode"))); 17883 } else { 17884 LOG_CLI((BSL_META_U(unit, 17885 "QUICKTURN:ATTN:NonLinkPhyPortDualMode"))); 17886 } 17887 *mode=bcmMxqPhyPortModeDual; 17888 if (int_pc) { 17889 int_pc->phy_mode = PHYCTRL_DUAL_LANE_PORT; 17890 } 17891 return SOC_E_NONE; 17892 } 17893 /* } */ 17894 } 17895 if ((speed == 12000) || (speed==13000) || (speed==15000) || (speed==16000) || 17896 (speed == 20000) || (speed==21000)) { 17897 *mode=bcmMxqPhyPortModeSingle; 17898 if (int_pc) { 17899 int_pc->phy_mode = PHYCTRL_QUAD_LANE_PORT; 17900 } 17901 return SOC_E_NONE; 17902 } 17903 if ((speed == 10000)) { 17904 *mode=bcmMxqPhyPortModeQuad; 17905 if (int_pc) { 17906 int_pc->phy_mode = PHYCTRL_ONE_LANE_PORT; 17907 } 17908 return SOC_E_NONE; 17909 } 17910 break; 17911 } 17912 return SOC_E_CONFIG; 17913 } 17914 void 17915 soc_katana2_pbmp_init(int unit, kt2_pbmp_t kt2_pbmp) 17916 { 17917 int port; 17918 soc_pbmp_t my_pbmp_xport_xe; 17919 soc_pbmp_t my_pbmp_xport_ge; 17920 soc_port_details_t *kt2_selected_port_details=NULL; 17921 int kt2_port_details_index=0; 17922 uint32 loop_index=0; 17923 uint8 kt2_port_used_flags[40]={0}; 17924 int mxqblock = 0, num_lanes = 0, lane_num = 0; 17925 bcmMxqCorePortMode_t mode = bcmMxqCorePortModeSingle; 17926 /* =============================== */ 17927 /* Begin: Unit Specific Allocation */ 17928 /* =============================== */ 17929 if (mxqspeeds[unit] != NULL) { 17930 sal_free(mxqspeeds[unit]); 17931 mxqspeeds[unit] = NULL; 17932 } 17933 mxqspeeds[unit] = sal_alloc(sizeof(mxqspeeds_s), "mxqspeed_t"); 17934 if (mxqspeeds[unit] == NULL) { 17935 LOG_ERROR(BSL_LS_SOC_COMMON, 17936 (BSL_META_U(unit, 17937 "Resource issue: Couldn't allocate memory=%d \n"), 17938 (int)sizeof(mxqspeeds_t))); 17939 return ; 17940 } 17941 sal_memcpy(mxqspeeds[unit],mxqspeeds_s,sizeof(mxqspeeds_s)); 17942 17943 if (bcm56450_speed[unit] != NULL) { 17944 sal_free(bcm56450_speed[unit]); 17945 bcm56450_speed[unit] = NULL; 17946 } 17947 bcm56450_speed[unit] = sal_alloc(sizeof(kt2_speed_t) * 17948 (sizeof(bcm56450_speed_s) / 17949 sizeof(bcm56450_speed_s[0])), 17950 "bcm56450_speed"); 17951 if (bcm56450_speed[unit] == NULL) { 17952 LOG_ERROR(BSL_LS_SOC_COMMON, 17953 (BSL_META_U(unit, 17954 "Resource issue: Couldn't allocate memory=%d \n"), 17955 (int)sizeof(mxqspeeds_t))); 17956 return ; 17957 } 17958 for (loop_index = 0 ; 17959 loop_index < sizeof(bcm56450_speed_s ) / 17960 sizeof(bcm56450_speed_s[0]); 17961 loop_index++) { 17962 sal_memcpy(bcm56450_speed[unit][loop_index], 17963 bcm56450_speed_s[loop_index], 17964 sizeof(kt2_speed_t)); 17965 17966 } 17967 if (kt2_port_to_mxqblock[unit] != NULL) { 17968 sal_free(kt2_port_to_mxqblock[unit]); 17969 kt2_port_to_mxqblock[unit] = NULL; 17970 } 17971 kt2_port_to_mxqblock[unit] = sal_alloc(sizeof(kt2_port_to_mxqblock_s), "kt2_port_to_mxqblock_t"); 17972 if (kt2_port_to_mxqblock[unit] == NULL) { 17973 LOG_ERROR(BSL_LS_SOC_COMMON, 17974 (BSL_META_U(unit, 17975 "Resource issue: Couldn't allocate memory=%d \n"), 17976 (int)sizeof(kt2_port_to_mxqblock))); 17977 return ; 17978 } 17979 sal_memcpy(kt2_port_to_mxqblock[unit],kt2_port_to_mxqblock_s,sizeof(kt2_port_to_mxqblock_s)); 17980 if (kt2_port_to_mxqblock_subports[unit] != NULL) { 17981 sal_free(kt2_port_to_mxqblock_subports[unit]); 17982 kt2_port_to_mxqblock_subports[unit] = NULL; 17983 } 17984 kt2_port_to_mxqblock_subports[unit] = sal_alloc(sizeof(kt2_port_to_mxqblock_subports_s), "kt2_port_to_mxqblock_t"); 17985 if (kt2_port_to_mxqblock_subports[unit] == NULL) { 17986 LOG_ERROR(BSL_LS_SOC_COMMON, 17987 (BSL_META_U(unit, 17988 "Resource issue: Couldn't allocate memory=%d \n"), 17989 (int)sizeof(kt2_port_to_mxqblock_subports))); 17990 return ; 17991 } 17992 sal_memcpy(kt2_port_to_mxqblock_subports[unit],kt2_port_to_mxqblock_subports_s,sizeof(kt2_port_to_mxqblock_subports_s)); 17993 if (kt2_mxqblock_ports[unit] != NULL) { 17994 sal_free(kt2_mxqblock_ports[unit]); 17995 kt2_mxqblock_ports[unit] = NULL; 17996 } 17997 kt2_mxqblock_ports[unit] = sal_alloc(sizeof(kt2_mxqblock_ports_s), "kt2_mxqblock_ports_t"); 17998 if (kt2_mxqblock_ports[unit] == NULL) { 17999 LOG_ERROR(BSL_LS_SOC_COMMON, 18000 (BSL_META_U(unit, 18001 "Resource issue: Couldn't allocate memory=%d \n"), 18002 (int)sizeof(kt2_mxqblock_ports))); 18003 return ; 18004 } 18005 sal_memcpy(kt2_mxqblock_ports[unit],kt2_mxqblock_ports_s,sizeof(kt2_mxqblock_ports_s)); 18006 18007 /* =============================== */ 18008 /* End: Unit Specific Allocation */ 18009 /* =============================== */ 18010 18011 SOC_PBMP_CLEAR(*kt2_pbmp.pbmp_gport_stack); 18012 SOC_PBMP_CLEAR(*kt2_pbmp.pbmp_mxq); 18013 SOC_PBMP_CLEAR(*kt2_pbmp.pbmp_mxq1g); 18014 SOC_PBMP_CLEAR(*kt2_pbmp.pbmp_mxq2p5g); 18015 SOC_PBMP_CLEAR(*kt2_pbmp.pbmp_mxq10g); 18016 SOC_PBMP_CLEAR(*kt2_pbmp.pbmp_mxq13g); 18017 SOC_PBMP_CLEAR(*kt2_pbmp.pbmp_mxq21g); 18018 SOC_PBMP_CLEAR(*kt2_pbmp.pbmp_xport_xe); 18019 /* SOC_PBMP_CLEAR(*kt2_pbmp.pbmp_valid); */ 18020 SOC_PBMP_CLEAR(*kt2_pbmp.pbmp_pp); 18021 SOC_PBMP_CLEAR(*kt2_pbmp.pbmp_linkphy); 18022 if (_soc_katana2_get_cfg_num(unit,&kt2_port_details_index) != BCM_E_NONE) { 18023 LOG_CLI((BSL_META_U(unit, 18024 "Retrieved WRONG CFG VALUE =%d\n"), kt2_port_details_index)); 18025 return ; 18026 } 18027 if (kt2_port_details_index >= (sizeof(bcm56450_tdm)/ 18028 sizeof(bcm56450_tdm[0]))) { 18029 LOG_CLI((BSL_META_U(unit, 18030 "INTERNAL: WRONG CFG VALUE =%d\n"), kt2_port_details_index)); 18031 return ; 18032 } 18033 SOC_INFO(unit).olp_port[0] = 0; 18034 /* ### NonOLP Port=40 is on MXQ7:Lane3 ### */ 18035 (*kt2_port_to_mxqblock[unit])[40-1]=7; 18036 (*kt2_port_to_mxqblock_subports[unit])[40-1]=3; 18037 (*kt2_mxqblock_ports[unit])[7][3]=40; 18038 /* Make it unavailable for MXQ10:Lane2 */ 18039 (*kt2_mxqblock_ports[unit])[10][2]=0xFF; 18040 18041 SOC_PBMP_CLEAR(my_pbmp_xport_xe); 18042 SOC_PBMP_CLEAR(my_pbmp_xport_ge); 18043 my_pbmp_xport_xe = soc_property_get_pbmp_default(unit, spn_PBMP_XPORT_XE, 18044 my_pbmp_xport_xe); 18045 my_pbmp_xport_ge = soc_property_get_pbmp_default(unit, spn_PBMP_XPORT_GE, 18046 my_pbmp_xport_ge); 18047 18048 kt2_selected_port_details = (soc_port_details_t *) 18049 kt2_port_details[kt2_port_details_index]; 18050 18051 18052 if (kt2_selected_port_details == NULL) { 18053 LOG_CLI((BSL_META_U(unit, 18054 "INTERNAL: Not Supported CFG VALUE =%d\n"), 18055 kt2_port_details_index)); 18056 return ; 18057 } 18058 loop_index=0; 18059 while(kt2_selected_port_details[loop_index].port_speed != 0) { 18060 LOG_VERBOSE(BSL_LS_SOC_COMMON, 18061 (BSL_META_U(unit, 18062 "start:%d end:%d incr:%d type:%d speed:%d\n"), 18063 kt2_selected_port_details[loop_index].start_port_no, 18064 kt2_selected_port_details[loop_index].end_port_no, 18065 kt2_selected_port_details[loop_index].port_incr, 18066 kt2_selected_port_details[loop_index].port_type, 18067 kt2_selected_port_details[loop_index].port_speed)); 18068 for (port = kt2_selected_port_details[loop_index].start_port_no; 18069 port <= kt2_selected_port_details[loop_index].end_port_no; 18070 port += kt2_selected_port_details[loop_index].port_incr) { 18071 if (kt2_selected_port_details[loop_index].port_type == 0) { 18072 break; 18073 } 18074 if (kt2_selected_port_details[loop_index].port_type & 18075 GE_PORT) { 18076 switch(kt2_selected_port_details[loop_index].port_speed) { 18077 case 1000: SOC_PBMP_PORT_ADD(*kt2_pbmp.pbmp_mxq1g, port); break; 18078 case 2500: SOC_PBMP_PORT_ADD(*kt2_pbmp.pbmp_mxq2p5g, port); break; 18079 default:break;/*error */ 18080 } 18081 } 18082 if (kt2_selected_port_details[loop_index].port_type & XE_PORT) { 18083 SOC_PBMP_PORT_ADD(*kt2_pbmp.pbmp_mxq10g, port); 18084 SOC_PBMP_PORT_ADD(*kt2_pbmp.pbmp_xport_xe, port); 18085 18086 /* In BCM56452 config 8, 20G DXAUI WC1 ethernet port is used. 18087 * It has been configured to XE with 20G speed support. Though 18088 * it is conventional to use XE only upto 10G, this is treated 18089 * as a special case. */ 18090 if(kt2_selected_port_details[loop_index].port_speed == 20000) { 18091 SOC_PBMP_PORT_ADD(*kt2_pbmp.pbmp_mxq21g, port); 18092 } 18093 /* In few bcm5645x_configs, WC ports interface type is XFI. 18094 * In those configs, if the phy mode and core mode of the 18095 * port is operating in single port mode, then port can 18096 * operate at 13g speed. 18097 */ 18098 mxqblock = (*kt2_port_to_mxqblock[unit])[port-1]; 18099 if ((mxqblock == 8) || (mxqblock == 9)) { 18100 soc_katana2_get_core_port_mode(unit, port, &mode); 18101 num_lanes = soc_property_port_get(unit, port, 18102 spn_PORTGROUP, 0); 18103 lane_num = ((*kt2_port_to_mxqblock_subports[unit]) 18104 [port-1]); 18105 if ((mode == bcmMxqCorePortModeSingle) && 18106 (num_lanes == 4) && 18107 (lane_num == 0)) { 18108 SOC_PBMP_PORT_ADD(*kt2_pbmp.pbmp_mxq13g, port); 18109 } 18110 } 18111 } 18112 if (kt2_selected_port_details[loop_index].port_type & HG_PORT) { 18113 if (SOC_PBMP_MEMBER(my_pbmp_xport_xe, port)) { 18114 SOC_PBMP_PORT_ADD(*kt2_pbmp.pbmp_xport_xe, port); 18115 } 18116 switch(kt2_selected_port_details[loop_index].port_speed) { 18117 case 10000: SOC_PBMP_PORT_ADD(*kt2_pbmp.pbmp_mxq10g, port);break; 18118 case 13000: SOC_PBMP_PORT_ADD(*kt2_pbmp.pbmp_mxq13g, port);break; 18119 case 20000: 18120 case 21000: SOC_PBMP_PORT_ADD(*kt2_pbmp.pbmp_mxq21g, port);break; 18121 default:break;/*error */ 18122 } 18123 } 18124 if (kt2_selected_port_details[loop_index].port_type & HGL_PORT) { 18125 if (SOC_PBMP_MEMBER(my_pbmp_xport_ge, port)) { 18126 SOC_PBMP_PORT_ADD(*kt2_pbmp.pbmp_mxq2p5g, port); 18127 } else { 18128 SOC_PBMP_PORT_ADD(*kt2_pbmp.pbmp_mxq2p5g, port); 18129 SOC_PBMP_PORT_ADD(*kt2_pbmp.pbmp_gport_stack, port); 18130 } 18131 } 18132 if (kt2_selected_port_details[loop_index].port_type & STK_PORT) { 18133 if (!(SOC_PBMP_MEMBER(my_pbmp_xport_xe, port) || 18134 SOC_PBMP_MEMBER(my_pbmp_xport_ge, port))) { 18135 SOC_PBMP_PORT_ADD(*kt2_pbmp.pbmp_gport_stack, port); 18136 } 18137 } 18138 /* Currently not taking action on CES,OLP */ 18139 if (kt2_selected_port_details[loop_index].port_type & 18140 LPHY_PORT) { 18141 SOC_PBMP_PORT_ADD(*kt2_pbmp.pbmp_linkphy, port); 18142 } 18143 if (kt2_selected_port_details[loop_index].port_type & OLP_PORT) { 18144 SOC_INFO(unit).olp_port[0] = 1; 18145 /* ### OLP Port=40 is on MXQ10:Lane2 ### */ 18146 (*kt2_port_to_mxqblock[unit])[40-1]=10; 18147 (*kt2_port_to_mxqblock_subports[unit])[40-1]=2; 18148 /* Make it unavailable for MXQ7:Lane3 */ 18149 (*kt2_mxqblock_ports[unit])[7][3]=0xFF; 18150 /* ### OLP Port is on MXQ10:Lane2 ### */ 18151 (*kt2_mxqblock_ports[unit])[10][2]=40; 18152 SOC_PBMP_PORT_ADD(*kt2_pbmp.pbmp_mxq2p5g, port); 18153 } 18154 SOC_PBMP_PORT_ADD(*kt2_pbmp.pbmp_mxq, port); 18155 kt2_port_used_flags[port-1]=1; 18156 } 18157 loop_index++; 18158 } 18159 for (port = 1; port <= 40; port++) { 18160 if (kt2_port_used_flags[port-1] == 0) { 18161 SOC_PBMP_PORT_REMOVE(*kt2_pbmp.pbmp_valid, port); 18162 } 18163 } 18164 for (port = 0; port < 170; port++) { 18165 SOC_PBMP_PORT_ADD(*kt2_pbmp.pbmp_pp, port); 18166 } 18167 } 18168 18169 void 18170 soc_katana2_subport_init(int unit) 18171 { 18172 soc_port_t port, lp_port, prev_port, pp_port; 18173 soc_pbmp_t pbmp_subport, pbmp_linkphy; 18174 soc_pbmp_t pbmp_linkphy_xlp0; 18175 soc_info_t *si=&SOC_INFO(unit); 18176 int num_subport = 0, available_subport = 0; 18177 int port_subport_index_start = 0; 18178 int port_subport_index_end = 0; 18179 int first_half_subport_index_max = 0; 18180 int second_half_subport_index_max = 0; 18181 int lp_index = 0, lp_block = 0; 18182 int num_subports_valid = 0; 18183 int s1_xlp0_index = 0; 18184 int s1_xlp1_index = 0; 18185 int num_subports_first_half = 0; 18186 int num_subports_second_half = 0; 18187 int rv = SOC_E_NONE; 18188 18189 SOC_PBMP_CLEAR(pbmp_subport); 18190 SOC_PBMP_CLEAR(pbmp_linkphy); 18191 SOC_PBMP_CLEAR(pbmp_linkphy_xlp0); 18192 /*SOC_PBMP_CLEAR(pbmp_linkphy_xlp1);*/ 18193 SOC_PBMP_CLEAR(si->linkphy_pbm); 18194 SOC_PBMP_CLEAR(si->lp.bitmap); 18195 SOC_PBMP_CLEAR(si->linkphy_allowed_pbm); 18196 SOC_PBMP_CLEAR(si->subtag_pbm); 18197 SOC_PBMP_CLEAR(si->subtag_allowed_pbm); 18198 SOC_PBMP_CLEAR(si->subtag.bitmap); 18199 SOC_PBMP_CLEAR(si->linkphy_pp_port_pbm); 18200 SOC_PBMP_CLEAR(si->enabled_linkphy_pp_port_pbm); 18201 SOC_PBMP_CLEAR(si->subtag_pp_port_pbm); 18202 SOC_PBMP_CLEAR(si->enabled_subtag_pp_port_pbm); 18203 si->subtag_enabled = 0; 18204 si->linkphy_enabled = 0; 18205 18206 for (port = 1; port <= KT2_MAX_PHYSICAL_PORTS; port++) { 18207 si->port_num_subport[port] = 0; 18208 si->port_subport_base[port] = 0; 18209 si->port_linkphy_s1_base[port] = 0; 18210 } 18211 18212 pbmp_subport = soc_property_get_pbmp(unit, spn_PBMP_SUBPORT, 0); 18213 pbmp_linkphy = soc_property_get_pbmp(unit, spn_PBMP_LINKPHY, 0); 18214 18215 SOC_PBMP_ASSIGN(si->subtag_allowed_pbm, pbmp_subport); 18216 SOC_PBMP_ASSIGN(si->linkphy_allowed_pbm, pbmp_linkphy); 18217 18218 if (SOC_PBMP_NOT_NULL(pbmp_subport)) { 18219 /* All members of pbmp_linkphy should also be 18220 * member of pbmp_subport */ 18221 if (SOC_PBMP_NOT_NULL(pbmp_linkphy)) { 18222 /* 18223 * Check if pbmp_linkphy members are valid for 18224 * supporting LinkPHY. 18225 * For Katana2(BCM56450) port 27 to 34 only support LinkPHY 18226 */ 18227 SOC_PBMP_ITER(pbmp_linkphy, port) { 18228 if (!SOC_REG_PORT_VALID(unit, RXLP_PORT_ENABLEr, port)) { 18229 LOG_ERROR(BSL_LS_SOC_COMMON, 18230 (BSL_META_U(unit, 18231 "\nCONFIG ERROR\n" 18232 "pbmp_linkphy member port %d is invalid for " 18233 "LinkPHY support - invalidating " 18234 "subtag, linkphy pbmp\n\n"), port)); 18235 18236 SOC_PBMP_CLEAR(si->subtag_allowed_pbm); 18237 SOC_PBMP_CLEAR(si->linkphy_allowed_pbm); 18238 return; 18239 } 18240 SOC_PBMP_PORT_ADD(si->linkphy_allowed_pbm, port); 18241 } 18242 18243 SOC_PBMP_ITER(pbmp_linkphy, port) { 18244 if (!SOC_PBMP_MEMBER(pbmp_subport, port)) { 18245 LOG_ERROR(BSL_LS_SOC_COMMON, 18246 (BSL_META_U(unit, 18247 "\nCONFIG ERROR\n" 18248 "pbmp_linkphy member port %d is not member of " 18249 "pbmp_subport support - invalidating " 18250 "subtag, linkphy pbmp\n\n"), port)); 18251 18252 SOC_PBMP_CLEAR(si->subtag_allowed_pbm); 18253 SOC_PBMP_CLEAR(si->linkphy_allowed_pbm); 18254 return; 18255 } 18256 SOC_PBMP_PORT_REMOVE(si->subtag_allowed_pbm, port); 18257 } 18258 } 18259 } else { 18260 if (SOC_PBMP_NOT_NULL(pbmp_linkphy)) { 18261 LOG_ERROR(BSL_LS_SOC_COMMON, 18262 (BSL_META_U(unit, 18263 "\nCONFIG ERROR\n" 18264 "config variable pbmp_linkphy should be sub-set of " 18265 "config variable pbmp_subport\n\n"))); 18266 } 18267 } 18268 18269 available_subport = SOC_KT2_MAX_SUBPORTS; 18270 prev_port = 0; 18271 si->port_num_subport[prev_port] = 0; 18272 si->port_subport_base[prev_port] = SOC_KT2_MIN_SUBPORT_INDEX; 18273 18274 if (SOC_PBMP_NOT_NULL(si->linkphy_allowed_pbm)) { 18275 18276 /* Constraint: 18277 * If physical port type is LinkPHY then both the 18278 * subport base and subport end indices should entirely be 18279 * either in first half or second half. 18280 * KT2 can support max 128 subports. 18281 * So a single LinkPHY port can support maximum 64 subports. 18282 */ 18283 first_half_subport_index_max = 18284 SOC_KT2_MIN_SUBPORT_INDEX + SOC_KT2_MAX_LINKPHY_SUBPORTS_PER_PORT - 1; 18285 18286 second_half_subport_index_max = 18287 SOC_KT2_MIN_SUBPORT_INDEX + SOC_KT2_MAX_SUBPORTS - 1; 18288 18289 s1_xlp0_index = 0; 18290 s1_xlp1_index = SOC_KT2_MAX_SUBPORTS; 18291 18292 /* Iterate through LinkPHY members first and reserve subport indices */ 18293 SOC_PBMP_ITER(si->linkphy_allowed_pbm, port) { 18294 if (port < SOC_MAX_NUM_PORTS) { 18295 num_subport = 18296 soc_property_port_get(unit, port, spn_NUM_SUBPORTS, 0); 18297 18298 if (num_subport > SOC_KT2_MAX_LINKPHY_SUBPORTS_PER_PORT) { 18299 num_subport = SOC_KT2_MAX_LINKPHY_SUBPORTS_PER_PORT; 18300 } 18301 18302 if (num_subport == 0) { 18303 LOG_ERROR(BSL_LS_SOC_COMMON, 18304 (BSL_META_U(unit, 18305 "\nCONFIG ERROR\n" 18306 "num_subports_%d should be non-zero for " 18307 "LinkPHY port %d\n\n"), port, port)); 18308 SOC_PBMP_PORT_REMOVE(si->linkphy_allowed_pbm, port); 18309 continue; 18310 } 18311 /* 18312 * get the MXQ block for the linkphy port 18313 */ 18314 rv = soc_kt2_linkphy_port_blk_idx_get(unit, port, 18315 &lp_block, 18316 &lp_index); 18317 if (SOC_FAILURE(rv)) { 18318 LOG_ERROR(BSL_LS_BCM_SUBPORT, 18319 (BSL_META_U(unit, 18320 "ERROR: LinkPHY block, " 18321 "index get failed for port %d\n"), port)); 18322 return; 18323 } 18324 18325 18326 if (num_subport > available_subport) { 18327 LOG_ERROR(BSL_LS_SOC_COMMON, 18328 (BSL_META_U(unit, 18329 "\nCONFIG ERROR\n" 18330 "num_subports_%d=%d unavailable for " 18331 "LinkPHY port\n\n"), port, num_subport)); 18332 SOC_PBMP_PORT_REMOVE(si->linkphy_allowed_pbm, port); 18333 return; 18334 } 18335 18336 /* 18337 * Assigning PP_PORT for the subports 18338 * range is from 42 to 169, which is the 18339 * maximum number of logical ports supported. 18340 */ 18341 port_subport_index_start = 18342 (si->port_subport_base[prev_port] + 18343 si->port_num_subport[prev_port]); 18344 18345 port_subport_index_end = 18346 port_subport_index_start + num_subport - 1; 18347 18348 /* 18349 * Maximum number of subports per MXQ block is 64. 18350 */ 18351 if (lp_block) { 18352 if ((num_subports_second_half + num_subport) <= 18353 SOC_KT2_MAX_LINKPHY_SUBPORTS_PER_PORT) { 18354 num_subports_second_half += num_subport; 18355 num_subports_valid = 1; 18356 } 18357 } else { 18358 if ((num_subports_first_half + num_subport) <= 18359 SOC_KT2_MAX_LINKPHY_SUBPORTS_PER_PORT) { 18360 num_subports_first_half += num_subport; 18361 num_subports_valid = 1; 18362 } 18363 } 18364 18365 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 18366 "prevport[%d] num_subport[%d] base[%d]\n" 18367 "port[%d] - %d->%d max- f[%d]s[%d]\n" 18368 "num_subports_first_half[%d] - num_subport[%d\n" 18369 "num_subports_second_half[%d] - num_subport[%d\n"), 18370 prev_port, si->port_num_subport[prev_port], 18371 si->port_subport_base[prev_port], 18372 port, 18373 port_subport_index_start, 18374 port_subport_index_end, 18375 first_half_subport_index_max, 18376 second_half_subport_index_max, 18377 num_subports_first_half, num_subport, 18378 num_subports_second_half, num_subport)); 18379 18380 if (num_subports_valid) { 18381 si->port_subport_base[port] = port_subport_index_start; 18382 si->port_num_subport[port] = num_subport; 18383 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 18384 "port_subport_base[%d] - %d->%d " 18385 "max[%d]\n"),port, port_subport_index_start, 18386 port_subport_index_end, 18387 first_half_subport_index_max)); 18388 18389 available_subport -= num_subport; 18390 num_subports_valid = 0; 18391 18392 /* For block0 - MXQ8 s1 nodes 0..127 is used 18393 * for block1 - MXQ9 s1 nodes 128..255 is used */ 18394 if (lp_block) { /* XLP1 (MXQ9) */ 18395 si->port_linkphy_s1_base[port] = s1_xlp1_index; 18396 s1_xlp1_index += si->port_num_subport[port] * 18397 BCM_SUBPORT_CONFIG_MAX_STREAMS; 18398 } else { /* XLP0 (MXQ8) */ 18399 SOC_PBMP_PORT_ADD(pbmp_linkphy_xlp0, port); 18400 si->port_linkphy_s1_base[port] = s1_xlp0_index; 18401 s1_xlp0_index += si->port_num_subport[port] * 18402 BCM_SUBPORT_CONFIG_MAX_STREAMS; 18403 } 18404 18405 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 18406 "\nport[%d] s1_b[%d] num_s[%d] " 18407 "xlp0[%d] xlp1[%d]\n\n\n"), 18408 port, si->port_linkphy_s1_base[port], 18409 si->port_num_subport[port], s1_xlp0_index, 18410 s1_xlp1_index)); 18411 } else { 18412 LOG_ERROR(BSL_LS_SOC_COMMON, 18413 (BSL_META_U(unit, 18414 "\nCONFIG ERROR\n" 18415 "contiguous num_subport=%d unavailable " 18416 "for linkphy port %d\n\n"), num_subport, port)); 18417 SOC_PBMP_PORT_REMOVE(si->linkphy_allowed_pbm, port); 18418 continue; 18419 } 18420 prev_port = port; 18421 } 18422 } /* end SOC_PBMP_ITER(si->linkphy_allowed_pbm, port) */ 18423 } 18424 18425 prev_port = 0; 18426 if (SOC_PBMP_NOT_NULL(si->subtag_allowed_pbm)) { 18427 /* Iterate through SubTag ports and reserve subport indices */ 18428 SOC_PBMP_ITER(si->subtag_allowed_pbm, port) { 18429 num_subport = 18430 soc_property_port_get(unit, port, spn_NUM_SUBPORTS, 0); 18431 18432 if (num_subport == 0) { 18433 LOG_ERROR(BSL_LS_SOC_COMMON, 18434 (BSL_META_U(unit, 18435 "\nCONFIG ERROR\n" 18436 "num_subports_%d should be non-zero for " 18437 "SubTag port %d\n\n"), port, port)); 18438 SOC_PBMP_PORT_REMOVE(si->subtag_allowed_pbm, port); 18439 continue; 18440 } 18441 18442 if (num_subport > available_subport) { 18443 LOG_ERROR(BSL_LS_SOC_COMMON, 18444 (BSL_META_U(unit, 18445 "\nCONFIG ERROR\n" 18446 "num_subports_%d=%d unavailable for SubTag port\n\n"), 18447 port, num_subport)); 18448 SOC_PBMP_PORT_REMOVE(si->subtag_allowed_pbm, port); 18449 continue; 18450 } 18451 18452 port_subport_index_start = si->port_subport_base[prev_port] + 18453 si->port_num_subport[prev_port]; 18454 18455 /* Iterate the LinkPHY ports. 18456 * Skip the LinkPHY ports for which subports are allocated 18457 * until we get start index of required free subports 18458 * or reach end of LinkPHY ports. */ 18459 18460 SOC_PBMP_ITER(si->linkphy_allowed_pbm, lp_port) { 18461 if (lp_port < SOC_MAX_NUM_PORTS) { 18462 if (si->port_num_subport[lp_port]) { 18463 if (si->port_subport_base[lp_port] == 18464 port_subport_index_start) { 18465 /* skip the allocated LinkPHY ports */ 18466 port_subport_index_start = 18467 si->port_subport_base[lp_port] + 18468 si->port_num_subport[lp_port]; 18469 continue; 18470 } else if (si->port_subport_base[lp_port] > 18471 port_subport_index_start) { 18472 /* check if there is a big enough subport index 18473 * chunk unused, between 2 consecutive LinkPHY 18474 * enabled ports, to accomodate required subports */ 18475 if ((si->port_subport_base[lp_port] - 18476 port_subport_index_start) < num_subport) { 18477 /* skip the allocated LinkPHY ports */ 18478 port_subport_index_start = 18479 si->port_subport_base[lp_port] 18480 + si->port_num_subport[lp_port]; 18481 continue; 18482 } 18483 } 18484 } 18485 } 18486 } 18487 18488 if (port < SOC_MAX_NUM_PORTS) { 18489 si->port_subport_base[port] = port_subport_index_start; 18490 si->port_num_subport[port] = num_subport; 18491 18492 available_subport -= num_subport; 18493 prev_port = port; 18494 } 18495 } /* end SOC_PBMP_ITER(si->subtag_allowed_pbm, port) */ 18496 } 18497 18498 /* populate LinkPHY pp_port bitmap */ 18499 SOC_PBMP_ITER(si->linkphy_allowed_pbm, port) { 18500 if (port < SOC_MAX_NUM_PORTS) { 18501 for (pp_port = 0; pp_port < si->port_num_subport[port]; pp_port++) { 18502 SOC_PBMP_PORT_ADD(si->linkphy_pp_port_pbm, 18503 pp_port + si->port_subport_base[port]); 18504 /* Set this port in the enabled bmap by default at init */ 18505 SOC_PBMP_PORT_ADD(si->enabled_linkphy_pp_port_pbm, 18506 pp_port + si->port_subport_base[port]); 18507 } 18508 } 18509 } 18510 /* populate SubTag pp_port bitmap */ 18511 SOC_PBMP_ITER(si->subtag_allowed_pbm, port) { 18512 if (port < SOC_MAX_NUM_PORTS) { 18513 for (pp_port = 0; pp_port < si->port_num_subport[port]; pp_port++) { 18514 SOC_PBMP_PORT_ADD(si->subtag_pp_port_pbm, 18515 pp_port + si->port_subport_base[port]); 18516 /* Set this port in the enabled bmap by default at init */ 18517 SOC_PBMP_PORT_ADD(si->enabled_subtag_pp_port_pbm, 18518 pp_port + si->port_subport_base[port]); 18519 } 18520 } 18521 } 18522 if (SOC_PBMP_NOT_NULL (si->subtag_pp_port_pbm)) { 18523 si->subtag_enabled = 1; 18524 } 18525 if (SOC_PBMP_NOT_NULL (si->linkphy_pp_port_pbm)) { 18526 si->linkphy_enabled = 1; 18527 } 18528 18529 /* Initialize the number of modules */ 18530 si->num_coe_modules = soc_property_get(unit, spn_MODULE_NUM_MODIDS, 1); 18531 18532 /* Check if the num_mods exceeds max allowed, if so flag an error, 18533 note that the default of '1' is reserved for front-panel physical 18534 ports */ 18535 if(si->num_coe_modules > (_BCMI_KT2_MAX_COE_MODULES + 1)) { 18536 LOG_ERROR(BSL_LS_SOC_COMMON, 18537 (BSL_META_U(unit, 18538 "\nCONFIG ERROR\n" 18539 "Number of modules %d exceeds maximum: %d," 18540 "setting to max \n\n"), 18541 si->num_coe_modules, _BCMI_KT2_MAX_COE_MODULES)); 18542 si->num_coe_modules = _BCMI_KT2_MAX_COE_MODULES; 18543 } 18544 18545 /* If it is a non default value, note that we are in a 18546 'coe-stacking-mode', wherein we will be supporing stacking for CoE */ 18547 if(si->num_coe_modules != 1) { 18548 si->coe_stacking_mode = 1; 18549 /* Since the first module is reserved for physical-ports, reduce the 18550 num_coe_modules by 1 */ 18551 si->num_coe_modules--; 18552 } 18553 } 18554 18555 void 18556 _soc_katana2_ci_init(int unit) 18557 { 18558 uint32 rval; 18559 LOG_CLI((BSL_META_U(unit, 18560 "QUICKTURN:ATTN \n"))); 18561 18562 WRITE_CI_CONFIG1r(unit, 0, 0xf0dcf0dc); 18563 WRITE_CI_CONFIG1r(unit,.0, 0xf0dcf0dc); 18564 WRITE_CI_CONFIG1r(unit,.1, 0xf0dcf0dc); 18565 WRITE_CI_CONFIG1r(unit,.1, 0xf0dcf0dc); 18566 WRITE_CI_CONFIG1r(unit,.2, 0xf0dcf0dc); 18567 WRITE_CI_CONFIG1r(unit,.2, 0xf0dcf0dc); 18568 WRITE_CI_CONFIG1r(unit,.3, 0xf0dcf0dc); 18569 WRITE_CI_CONFIG1r(unit,.3, 0xf0dcf0dc); 18570 WRITE_CI_CONFIG1r(unit,.4, 0xf0dcf0dc); 18571 WRITE_CI_CONFIG1r(unit,.4, 0xf0dcf0dc); 18572 WRITE_CI_CONFIG1r(unit,.5, 0xf0dcf0dc); 18573 WRITE_CI_CONFIG1r(unit,.5, 0xf0dcf0dc); 18574 WRITE_CI_RESETr(unit,.0, 0x00000004); 18575 WRITE_CI_RESETr(unit,.0, 0x00000002); 18576 WRITE_CI_RESETr(unit,.1, 0x00000004); 18577 WRITE_CI_RESETr(unit,.1, 0x00000002); 18578 WRITE_CI_RESETr(unit,.2, 0x00000004); 18579 WRITE_CI_RESETr(unit,.2, 0x00000002); 18580 WRITE_CI_RESETr(unit,.3, 0x00000004); 18581 WRITE_CI_RESETr(unit,.3, 0x00000002); 18582 WRITE_CI_RESETr(unit,.4, 0x00000004); 18583 WRITE_CI_RESETr(unit,.4, 0x00000002); 18584 WRITE_CI_RESETr(unit,.5, 0x00000004); 18585 WRITE_CI_RESETr(unit,.5, 0x00000002); 18586 WRITE_CI_CONFIG0r(unit,.0, 0x0324ab03); 18587 WRITE_CI_CONFIG0r(unit,.0, 0x0324ab03); 18588 WRITE_CI_CONFIG0r(unit,.1, 0x0324aa03); 18589 WRITE_CI_CONFIG0r(unit,.1, 0x0324aa03); 18590 WRITE_CI_CONFIG0r(unit,.2, 0x0324ab03); 18591 WRITE_CI_CONFIG0r(unit,.2, 0x0324ab03); 18592 WRITE_CI_CONFIG0r(unit,.3, 0x0324aa03); 18593 WRITE_CI_CONFIG0r(unit,.3, 0x0324ab03); 18594 WRITE_CI_CONFIG0r(unit,.4, 0x0324ab03); 18595 WRITE_CI_CONFIG0r(unit,.4, 0x0324ab03); 18596 WRITE_CI_CONFIG0r(unit,.5, 0x0324aa03); 18597 WRITE_CI_CONFIG0r(unit,.5, 0x0324ab03); 18598 WRITE_CI_CONFIG2r(unit,.0, 0x0d4860f0); 18599 WRITE_CI_CONFIG2r(unit,.0, 0x0d4860f0); 18600 WRITE_CI_CONFIG2r(unit,.1, 0x0c4860f0); 18601 WRITE_CI_CONFIG2r(unit,.1, 0x0c4860f0); 18602 WRITE_CI_CONFIG2r(unit,.2, 0x0d4860f0); 18603 WRITE_CI_CONFIG2r(unit,.2, 0x0d4860f0); 18604 WRITE_CI_CONFIG2r(unit,.3, 0x0c4860f0); 18605 WRITE_CI_CONFIG2r(unit,.3, 0x0d4860f0); 18606 WRITE_CI_CONFIG2r(unit,.4, 0x0d4860f0); 18607 WRITE_CI_CONFIG2r(unit,.4, 0x0d4860f0); 18608 WRITE_CI_CONFIG2r(unit,.5, 0x0c4860f0); 18609 WRITE_CI_CONFIG2r(unit,.5, 0x0d4860f0); 18610 WRITE_CI_CONFIG3r(unit,.0, 0x00003451); 18611 WRITE_CI_CONFIG3r(unit,.0, 0x00003451); 18612 WRITE_CI_CONFIG3r(unit,.1, 0x00003451); 18613 WRITE_CI_CONFIG3r(unit,.1, 0x00003451); 18614 WRITE_CI_CONFIG3r(unit,.2, 0x00003451); 18615 WRITE_CI_CONFIG3r(unit,.2, 0x00003451); 18616 WRITE_CI_CONFIG3r(unit,.3, 0x00003451); 18617 WRITE_CI_CONFIG3r(unit,.3, 0x00003451); 18618 WRITE_CI_CONFIG3r(unit,.4, 0x00003451); 18619 WRITE_CI_CONFIG3r(unit,.4, 0x00003451); 18620 WRITE_CI_CONFIG3r(unit,.5, 0x00003451); 18621 WRITE_CI_CONFIG3r(unit,.5, 0x00003451); 18622 WRITE_CI_CONFIG6r(unit,.0, 0x36000214); 18623 WRITE_CI_CONFIG6r(unit,.0, 0x36000214); 18624 WRITE_CI_CONFIG6r(unit,.1, 0x36000214); 18625 WRITE_CI_CONFIG6r(unit,.1, 0x36000214); 18626 WRITE_CI_CONFIG6r(unit,.2, 0x36000214); 18627 WRITE_CI_CONFIG6r(unit,.2, 0x36000214); 18628 WRITE_CI_CONFIG6r(unit,.3, 0x36000214); 18629 WRITE_CI_CONFIG6r(unit,.3, 0x36000214); 18630 WRITE_CI_CONFIG6r(unit,.4, 0x36000214); 18631 WRITE_CI_CONFIG6r(unit,.4, 0x36000214); 18632 WRITE_CI_CONFIG6r(unit,.5, 0x36000214); 18633 WRITE_CI_CONFIG6r(unit,.5, 0x36000214); 18634 WRITE_CI_PHY_STRAPS1r(unit,.0, 0x0004129b); 18635 WRITE_CI_PHY_STRAPS1r(unit,.0, 0x0004129b); 18636 WRITE_CI_PHY_STRAPS1r(unit,.1, 0x0004129b); 18637 WRITE_CI_PHY_STRAPS1r(unit,.1, 0x0004129b); 18638 WRITE_CI_PHY_STRAPS1r(unit,.2, 0x0004129b); 18639 WRITE_CI_PHY_STRAPS1r(unit,.2, 0x0004129b); 18640 WRITE_CI_PHY_STRAPS1r(unit,.3, 0x0004129b); 18641 WRITE_CI_PHY_STRAPS1r(unit,.3, 0x0004129b); 18642 WRITE_CI_PHY_STRAPS1r(unit,.4, 0x0004129b); 18643 WRITE_CI_PHY_STRAPS1r(unit,.4, 0x0004129b); 18644 WRITE_CI_PHY_STRAPS1r(unit,.5, 0x0004129b); 18645 WRITE_CI_PHY_STRAPS1r(unit,.5, 0x0004129b); 18646 WRITE_CI_RESETr(unit,.0, 0x00000002); 18647 WRITE_CI_RESETr(unit,.0, 0x00000000); 18648 WRITE_CI_RESETr(unit,.1, 0x00000002); 18649 WRITE_CI_RESETr(unit,.1, 0x00000000); 18650 WRITE_CI_RESETr(unit,.2, 0x00000002); 18651 WRITE_CI_RESETr(unit,.2, 0x00000000); 18652 WRITE_CI_RESETr(unit,.3, 0x00000002); 18653 WRITE_CI_RESETr(unit,.3, 0x00000000); 18654 WRITE_CI_RESETr(unit,.4, 0x00000002); 18655 WRITE_CI_RESETr(unit,.4, 0x00000000); 18656 WRITE_CI_RESETr(unit,.5, 0x00000002); 18657 WRITE_CI_RESETr(unit,.5, 0x00000000); 18658 WRITE_CI_DDR_MR0r(unit,.0, 0x00001b60); 18659 WRITE_CI_DDR_MR0r(unit,.0, 0x00001b60); 18660 WRITE_CI_DDR_MR0r(unit,.0, 0x00001b60); 18661 WRITE_CI_DDR_MR1r(unit,.0, 0x00008010); 18662 WRITE_CI_DDR_MR1r(unit,.0, 0x00008010); 18663 WRITE_CI_DDR_MR1r(unit,.0, 0x00008010); 18664 WRITE_CI_DDR_MR2r(unit,.0, 0x00010210); 18665 WRITE_CI_DDR_MR2r(unit,.0, 0x00010210); 18666 WRITE_CI_DDR_MR2r(unit,.0, 0x00010210); 18667 WRITE_CI_DDR_MR0r(unit,.1, 0x00001b60); 18668 WRITE_CI_DDR_MR0r(unit,.1, 0x00001b60); 18669 WRITE_CI_DDR_MR0r(unit,.1, 0x00001b60); 18670 WRITE_CI_DDR_MR1r(unit,.1, 0x00008010); 18671 WRITE_CI_DDR_MR1r(unit,.1, 0x00008010); 18672 WRITE_CI_DDR_MR1r(unit,.1, 0x00008010); 18673 WRITE_CI_DDR_MR2r(unit,.0, 0x00010210); 18674 WRITE_CI_DDR_MR2r(unit,.1, 0x00010210); 18675 WRITE_CI_DDR_MR2r(unit,.1, 0x00010210); 18676 WRITE_CI_DDR_MR0r(unit,.2, 0x00001b60); 18677 WRITE_CI_DDR_MR0r(unit,.2, 0x00001b60); 18678 WRITE_CI_DDR_MR0r(unit,.2, 0x00001b60); 18679 WRITE_CI_DDR_MR1r(unit,.2, 0x00008010); 18680 WRITE_CI_DDR_MR1r(unit,.2, 0x00008010); 18681 WRITE_CI_DDR_MR1r(unit,.2, 0x00008010); 18682 WRITE_CI_DDR_MR2r(unit,.0, 0x00010210); 18683 WRITE_CI_DDR_MR2r(unit,.2, 0x00010210); 18684 WRITE_CI_DDR_MR2r(unit,.2, 0x00010210); 18685 WRITE_CI_DDR_MR0r(unit,.3, 0x00001b60); 18686 WRITE_CI_DDR_MR0r(unit,.3, 0x00001b60); 18687 WRITE_CI_DDR_MR0r(unit,.3, 0x00001b60); 18688 WRITE_CI_DDR_MR1r(unit,.3, 0x00008010); 18689 WRITE_CI_DDR_MR1r(unit,.3, 0x00008010); 18690 WRITE_CI_DDR_MR1r(unit,.3, 0x00008010); 18691 WRITE_CI_DDR_MR2r(unit,.0, 0x00010210); 18692 WRITE_CI_DDR_MR2r(unit,.3, 0x00010210); 18693 WRITE_CI_DDR_MR2r(unit,.3, 0x00010210); 18694 WRITE_CI_DDR_MR0r(unit,.4, 0x00001b60); 18695 WRITE_CI_DDR_MR0r(unit,.4, 0x00001b60); 18696 WRITE_CI_DDR_MR0r(unit,.4, 0x00001b60); 18697 WRITE_CI_DDR_MR1r(unit,.4, 0x00008010); 18698 WRITE_CI_DDR_MR1r(unit,.4, 0x00008010); 18699 WRITE_CI_DDR_MR1r(unit,.4, 0x00008010); 18700 WRITE_CI_DDR_MR2r(unit,.0, 0x00010210); 18701 WRITE_CI_DDR_MR2r(unit,.4, 0x00010210); 18702 WRITE_CI_DDR_MR2r(unit,.4, 0x00010210); 18703 WRITE_CI_DDR_MR0r(unit,.5, 0x00001b60); 18704 WRITE_CI_DDR_MR0r(unit,.5, 0x00001b60); 18705 WRITE_CI_DDR_MR0r(unit,.5, 0x00001b60); 18706 WRITE_CI_DDR_MR1r(unit,.5, 0x00008010); 18707 WRITE_CI_DDR_MR1r(unit,.5, 0x00008010); 18708 WRITE_CI_DDR_MR1r(unit,.5, 0x00008010); 18709 WRITE_CI_DDR_MR2r(unit,.0, 0x00010210); 18710 WRITE_CI_DDR_MR2r(unit,.5, 0x00010210); 18711 WRITE_CI_DDR_MR2r(unit,.5, 0x00010210); 18712 WRITE_CI_RESETr(unit,.0, 0x00000000); 18713 WRITE_CI_RESETr(unit,.0, 0x00000004); 18714 WRITE_CI_RESETr(unit,.1, 0x00000000); 18715 WRITE_CI_RESETr(unit,.1, 0x00000004); 18716 WRITE_CI_RESETr(unit,.2, 0x00000000); 18717 WRITE_CI_RESETr(unit,.2, 0x00000004); 18718 WRITE_CI_RESETr(unit,.3, 0x00000000); 18719 WRITE_CI_RESETr(unit,.3, 0x00000004); 18720 WRITE_CI_RESETr(unit,.4, 0x00000000); 18721 WRITE_CI_RESETr(unit,.4, 0x00000004); 18722 WRITE_CI_RESETr(unit,.5, 0x00000000); 18723 WRITE_CI_RESETr(unit,.5, 0x00000004); 18724 sal_sleep( 2); 18725 WRITE_CI_PHY_CONTROLr(unit,.0, 0x04a5360f); 18726 WRITE_CI_PHY_CONTROLr(unit,.0, 0x04a5360f); 18727 WRITE_CI_PHY_CONTROLr(unit,.1, 0x0425360f); 18728 WRITE_CI_PHY_CONTROLr(unit,.1, 0x0425360f); 18729 WRITE_CI_PHY_CONTROLr(unit,.2, 0x04a5360f); 18730 WRITE_CI_PHY_CONTROLr(unit,.2, 0x04a5360f); 18731 WRITE_CI_PHY_CONTROLr(unit,.3, 0x0425360f); 18732 WRITE_CI_PHY_CONTROLr(unit,.3, 0x0425360f); 18733 WRITE_CI_PHY_CONTROLr(unit,.4, 0x04a5360f); 18734 WRITE_CI_PHY_CONTROLr(unit,.4, 0x04a5360f); 18735 WRITE_CI_PHY_CONTROLr(unit,.5, 0x0425360f); 18736 WRITE_CI_PHY_CONTROLr(unit,.5, 0x0425360f); 18737 sal_sleep( 2); 18738 WRITE_CI_PHY_CONTROLr(unit,.0, 0x04a5360f); 18739 WRITE_CI_PHY_CONTROLr(unit,.0, 0x04a53603); 18740 WRITE_CI_PHY_CONTROLr(unit,.1, 0x0425360f); 18741 WRITE_CI_PHY_CONTROLr(unit,.1, 0x04253603); 18742 WRITE_CI_PHY_CONTROLr(unit,.2, 0x04a5360f); 18743 WRITE_CI_PHY_CONTROLr(unit,.2, 0x04a53603); 18744 WRITE_CI_PHY_CONTROLr(unit,.3, 0x0425360f); 18745 WRITE_CI_PHY_CONTROLr(unit,.3, 0x04253603); 18746 WRITE_CI_PHY_CONTROLr(unit,.4, 0x04a5360f); 18747 WRITE_CI_PHY_CONTROLr(unit,.4, 0x04a53603); 18748 WRITE_CI_PHY_CONTROLr(unit,.5, 0x0425360f); 18749 WRITE_CI_PHY_CONTROLr(unit,.5, 0x04253603); 18750 sal_sleep( 2); 18751 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.0, 0x80000438); 18752 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.0, 0xe000001c); 18753 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.0, 0xa000001c); 18754 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x00001420); 18755 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x00001420); 18756 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x00001810); 18757 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.0, 0xa000001c); 18758 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.0, 0xc000001c); 18759 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.0, 0x8000001c); 18760 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x00001810); 18761 WRITE_CI_DDR_PHY_REG_DATAr(unit,.1, 0x00000000); 18762 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x00300000); 18763 WRITE_CI_DDR_PHY_REG_DATAr(unit,.3, 0x00000000); 18764 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x00300000); 18765 WRITE_CI_DDR_PHY_REG_DATAr(unit,.5, 0x00000000); 18766 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.0, 0x8000001c); 18767 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.0, 0xe0000014); 18768 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.0, 0xa0000014); 18769 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x00000012); 18770 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x00000012); 18771 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x00000002); 18772 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.0, 0xa0000014); 18773 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.0, 0xc0000014); 18774 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.0, 0x80000014); 18775 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x00000002); 18776 WRITE_CI_DDR_PHY_REG_DATAr(unit,.1, 0x00000000); 18777 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x00300000); 18778 WRITE_CI_DDR_PHY_REG_DATAr(unit,.3, 0x00000000); 18779 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x00300000); 18780 WRITE_CI_DDR_PHY_REG_DATAr(unit,.5, 0x00000000); 18781 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.0, 0x80000014); 18782 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.0, 0xe0000014); 18783 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.0, 0xa0000014); 18784 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x00000002); 18785 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x00000002); 18786 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x00000002); 18787 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.0, 0xa0000014); 18788 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.0, 0xc0000014); 18789 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.0, 0x80000014); 18790 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x00000002); 18791 WRITE_CI_DDR_PHY_REG_DATAr(unit,.1, 0x00000000); 18792 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x00300000); 18793 WRITE_CI_DDR_PHY_REG_DATAr(unit,.3, 0x00000000); 18794 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x00300000); 18795 WRITE_CI_DDR_PHY_REG_DATAr(unit,.5, 0x00000000); 18796 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.0, 0x80000014); 18797 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.0, 0xe0000014); 18798 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.0, 0xa0000014); 18799 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x00000002); 18800 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x00000002); 18801 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x00000002); 18802 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.0, 0xa0000014); 18803 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.0, 0xc0000014); 18804 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.0, 0x80000014); 18805 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x00000002); 18806 WRITE_CI_DDR_PHY_REG_DATAr(unit,.1, 0x00000000); 18807 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x00300000); 18808 WRITE_CI_DDR_PHY_REG_DATAr(unit,.3, 0x00000000); 18809 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x00300000); 18810 WRITE_CI_DDR_PHY_REG_DATAr(unit,.5, 0x00000000); 18811 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.2, 0x80000438); 18812 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.2, 0xe000001c); 18813 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.2, 0xa000001c); 18814 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x00001420); 18815 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x00001420); 18816 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x00001810); 18817 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.2, 0xa000001c); 18818 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.2, 0xc000001c); 18819 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.2, 0x8000001c); 18820 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x00000002); 18821 WRITE_CI_DDR_PHY_REG_DATAr(unit,.1, 0x00000000); 18822 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x00001810); 18823 WRITE_CI_DDR_PHY_REG_DATAr(unit,.3, 0x00000000); 18824 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x00300000); 18825 WRITE_CI_DDR_PHY_REG_DATAr(unit,.5, 0x00000000); 18826 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.2, 0x8000001c); 18827 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.2, 0xe0000014); 18828 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.2, 0xa0000014); 18829 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x00000012); 18830 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x00000012); 18831 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x00000002); 18832 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.2, 0xa0000014); 18833 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.2, 0xc0000014); 18834 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.2, 0x80000014); 18835 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x00000002); 18836 WRITE_CI_DDR_PHY_REG_DATAr(unit,.1, 0x00000000); 18837 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x00000002); 18838 WRITE_CI_DDR_PHY_REG_DATAr(unit,.3, 0x00000000); 18839 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x00300000); 18840 WRITE_CI_DDR_PHY_REG_DATAr(unit,.5, 0x00000000); 18841 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.2, 0x80000014); 18842 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.2, 0xe0000014); 18843 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.2, 0xa0000014); 18844 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x00000002); 18845 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x00000002); 18846 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x00000002); 18847 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.2, 0xa0000014); 18848 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.2, 0xc0000014); 18849 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.2, 0x80000014); 18850 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x00000002); 18851 WRITE_CI_DDR_PHY_REG_DATAr(unit,.1, 0x00000000); 18852 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x00000002); 18853 WRITE_CI_DDR_PHY_REG_DATAr(unit,.3, 0x00000000); 18854 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x00300000); 18855 WRITE_CI_DDR_PHY_REG_DATAr(unit,.5, 0x00000000); 18856 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.2, 0x80000014); 18857 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.2, 0xe0000014); 18858 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.2, 0xa0000014); 18859 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x00000002); 18860 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x00000002); 18861 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x00000002); 18862 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.2, 0xa0000014); 18863 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.2, 0xc0000014); 18864 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.2, 0x80000014); 18865 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x00000002); 18866 WRITE_CI_DDR_PHY_REG_DATAr(unit,.1, 0x00000000); 18867 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x00000002); 18868 WRITE_CI_DDR_PHY_REG_DATAr(unit,.3, 0x00000000); 18869 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x00300000); 18870 WRITE_CI_DDR_PHY_REG_DATAr(unit,.5, 0x00000000); 18871 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.4, 0x80000438); 18872 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.4, 0xe000001c); 18873 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.4, 0xa000001c); 18874 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x00001420); 18875 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x00001420); 18876 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x00001810); 18877 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.4, 0xa000001c); 18878 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.4, 0xc000001c); 18879 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.4, 0x8000001c); 18880 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x00000002); 18881 WRITE_CI_DDR_PHY_REG_DATAr(unit,.1, 0x00000000); 18882 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x00000002); 18883 WRITE_CI_DDR_PHY_REG_DATAr(unit,.3, 0x00000000); 18884 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x00001810); 18885 WRITE_CI_DDR_PHY_REG_DATAr(unit,.5, 0x00000000); 18886 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.4, 0x8000001c); 18887 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.4, 0xe0000014); 18888 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.4, 0xa0000014); 18889 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x00000012); 18890 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x00000012); 18891 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x00000002); 18892 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.4, 0xa0000014); 18893 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.4, 0xc0000014); 18894 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.4, 0x80000014); 18895 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x00000002); 18896 WRITE_CI_DDR_PHY_REG_DATAr(unit,.1, 0x00000000); 18897 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x00000002); 18898 WRITE_CI_DDR_PHY_REG_DATAr(unit,.3, 0x00000000); 18899 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x00000002); 18900 WRITE_CI_DDR_PHY_REG_DATAr(unit,.5, 0x00000000); 18901 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.4, 0x80000014); 18902 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.4, 0xe0000014); 18903 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.4, 0xa0000014); 18904 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x00000002); 18905 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x00000002); 18906 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x00000002); 18907 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.4, 0xa0000014); 18908 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.4, 0xc0000014); 18909 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.4, 0x80000014); 18910 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x00000002); 18911 WRITE_CI_DDR_PHY_REG_DATAr(unit,.1, 0x00000000); 18912 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x00000002); 18913 WRITE_CI_DDR_PHY_REG_DATAr(unit,.3, 0x00000000); 18914 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x00000002); 18915 WRITE_CI_DDR_PHY_REG_DATAr(unit,.5, 0x00000000); 18916 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.4, 0x80000014); 18917 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.4, 0xe0000014); 18918 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.4, 0xa0000014); 18919 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x00000002); 18920 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x00000002); 18921 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x00000002); 18922 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.4, 0xa0000014); 18923 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.4, 0xc0000014); 18924 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.4, 0x80000014); 18925 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x00000002); 18926 WRITE_CI_DDR_PHY_REG_DATAr(unit,.1, 0x00000000); 18927 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x00000002); 18928 WRITE_CI_DDR_PHY_REG_DATAr(unit,.3, 0x00000000); 18929 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x00000002); 18930 WRITE_CI_DDR_PHY_REG_DATAr(unit,.5, 0x00000000); 18931 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.0, 0x80000014); 18932 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.0, 0xe0000010); 18933 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.0, 0xa0000010); 18934 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x00a6e001); 18935 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.2, 0x80000014); 18936 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.2, 0xe0000010); 18937 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.2, 0xa0000010); 18938 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x00a6e001); 18939 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.4, 0x80000014); 18940 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.4, 0xe0000010); 18941 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.4, 0xa0000010); 18942 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x00a6e001); 18943 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x00a6e001); 18944 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x03f1ffff); 18945 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.0, 0xa0000010); 18946 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.0, 0xc0000064); 18947 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.0, 0x80000064); 18948 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x03f1ffff); 18949 WRITE_CI_DDR_PHY_REG_DATAr(unit,.1, 0x00000000); 18950 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x00a6e001); 18951 WRITE_CI_DDR_PHY_REG_DATAr(unit,.3, 0x00000000); 18952 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x00a6e001); 18953 WRITE_CI_DDR_PHY_REG_DATAr(unit,.5, 0x00000000); 18954 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x03f1ffff); 18955 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x0001ffff); 18956 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.0, 0x80000064); 18957 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.0, 0xc0000068); 18958 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.0, 0x80000068); 18959 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x0001ffff); 18960 WRITE_CI_DDR_PHY_REG_DATAr(unit,.1, 0x00000000); 18961 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x00a6e001); 18962 WRITE_CI_DDR_PHY_REG_DATAr(unit,.3, 0x00000000); 18963 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x00a6e001); 18964 WRITE_CI_DDR_PHY_REG_DATAr(unit,.5, 0x00000000); 18965 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x0001ffff); 18966 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x00000004); 18967 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.0, 0x80000068); 18968 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.0, 0xc000005c); 18969 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.0, 0x8000005c); 18970 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x00000004); 18971 WRITE_CI_DDR_PHY_REG_DATAr(unit,.1, 0x00000000); 18972 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x00a6e001); 18973 WRITE_CI_DDR_PHY_REG_DATAr(unit,.3, 0x00000000); 18974 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x00a6e001); 18975 WRITE_CI_DDR_PHY_REG_DATAr(unit,.5, 0x00000000); 18976 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x00a6e001); 18977 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x03f1ffff); 18978 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.2, 0xa0000010); 18979 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.2, 0xc0000064); 18980 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.2, 0x80000064); 18981 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x00000004); 18982 WRITE_CI_DDR_PHY_REG_DATAr(unit,.1, 0x00000000); 18983 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x03f1ffff); 18984 WRITE_CI_DDR_PHY_REG_DATAr(unit,.3, 0x00000000); 18985 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x00a6e001); 18986 WRITE_CI_DDR_PHY_REG_DATAr(unit,.5, 0x00000000); 18987 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x03f1ffff); 18988 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x0001ffff); 18989 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.2, 0x80000064); 18990 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.2, 0xc0000068); 18991 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.2, 0x80000068); 18992 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x00000004); 18993 WRITE_CI_DDR_PHY_REG_DATAr(unit,.1, 0x00000000); 18994 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x0001ffff); 18995 WRITE_CI_DDR_PHY_REG_DATAr(unit,.3, 0x00000000); 18996 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x00a6e001); 18997 WRITE_CI_DDR_PHY_REG_DATAr(unit,.5, 0x00000000); 18998 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x0001ffff); 18999 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x00000004); 19000 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.2, 0x80000068); 19001 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.2, 0xc000005c); 19002 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.2, 0x8000005c); 19003 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x00000004); 19004 WRITE_CI_DDR_PHY_REG_DATAr(unit,.1, 0x00000000); 19005 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x00000004); 19006 WRITE_CI_DDR_PHY_REG_DATAr(unit,.3, 0x00000000); 19007 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x00a6e001); 19008 WRITE_CI_DDR_PHY_REG_DATAr(unit,.5, 0x00000000); 19009 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x00a6e001); 19010 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x03f1ffff); 19011 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.4, 0xa0000010); 19012 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.4, 0xc0000064); 19013 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.4, 0x80000064); 19014 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x00000004); 19015 WRITE_CI_DDR_PHY_REG_DATAr(unit,.1, 0x00000000); 19016 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x00000004); 19017 WRITE_CI_DDR_PHY_REG_DATAr(unit,.3, 0x00000000); 19018 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x03f1ffff); 19019 WRITE_CI_DDR_PHY_REG_DATAr(unit,.5, 0x00000000); 19020 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x03f1ffff); 19021 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x0001ffff); 19022 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.4, 0x80000064); 19023 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.4, 0xc0000068); 19024 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.4, 0x80000068); 19025 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x00000004); 19026 WRITE_CI_DDR_PHY_REG_DATAr(unit,.1, 0x00000000); 19027 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x00000004); 19028 WRITE_CI_DDR_PHY_REG_DATAr(unit,.3, 0x00000000); 19029 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x0001ffff); 19030 WRITE_CI_DDR_PHY_REG_DATAr(unit,.5, 0x00000000); 19031 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x0001ffff); 19032 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x00000004); 19033 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.4, 0x80000068); 19034 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.4, 0xc000005c); 19035 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.4, 0x8000005c); 19036 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x00000004); 19037 WRITE_CI_DDR_PHY_REG_DATAr(unit,.1, 0x00000000); 19038 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x00000004); 19039 WRITE_CI_DDR_PHY_REG_DATAr(unit,.3, 0x00000000); 19040 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x00000004); 19041 WRITE_CI_DDR_PHY_REG_DATAr(unit,.5, 0x00000000); 19042 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x00000004); 19043 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x00000000); 19044 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.0, 0x8000005c); 19045 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.0, 0xc000003c); 19046 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.0, 0x8000003c); 19047 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x00000000); 19048 WRITE_CI_DDR_PHY_REG_DATAr(unit,.1, 0x00000000); 19049 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x00000004); 19050 WRITE_CI_DDR_PHY_REG_DATAr(unit,.3, 0x00000000); 19051 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x00000004); 19052 WRITE_CI_DDR_PHY_REG_DATAr(unit,.5, 0x00000000); 19053 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x00000000); 19054 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x00100000); 19055 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.0, 0x8000003c); 19056 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.0, 0xc000003c); 19057 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.0, 0x8000003c); 19058 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x00100000); 19059 WRITE_CI_DDR_PHY_REG_DATAr(unit,.1, 0x00000000); 19060 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x00000004); 19061 WRITE_CI_DDR_PHY_REG_DATAr(unit,.3, 0x00000000); 19062 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x00000004); 19063 WRITE_CI_DDR_PHY_REG_DATAr(unit,.5, 0x00000000); 19064 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x00000004); 19065 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x00000000); 19066 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.2, 0x8000005c); 19067 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.2, 0xc000003c); 19068 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.2, 0x8000003c); 19069 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x00100000); 19070 WRITE_CI_DDR_PHY_REG_DATAr(unit,.1, 0x00000000); 19071 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x00000000); 19072 WRITE_CI_DDR_PHY_REG_DATAr(unit,.3, 0x00000000); 19073 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x00000004); 19074 WRITE_CI_DDR_PHY_REG_DATAr(unit,.5, 0x00000000); 19075 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x00000000); 19076 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x00100000); 19077 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.2, 0x8000003c); 19078 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.2, 0xc000003c); 19079 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.2, 0x8000003c); 19080 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x00100000); 19081 WRITE_CI_DDR_PHY_REG_DATAr(unit,.1, 0x00000000); 19082 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x00100000); 19083 WRITE_CI_DDR_PHY_REG_DATAr(unit,.3, 0x00000000); 19084 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x00000004); 19085 WRITE_CI_DDR_PHY_REG_DATAr(unit,.5, 0x00000000); 19086 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x00000004); 19087 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x00000000); 19088 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.4, 0x8000005c); 19089 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.4, 0xc000003c); 19090 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.4, 0x8000003c); 19091 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x00100000); 19092 WRITE_CI_DDR_PHY_REG_DATAr(unit,.1, 0x00000000); 19093 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x00100000); 19094 WRITE_CI_DDR_PHY_REG_DATAr(unit,.3, 0x00000000); 19095 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x00000000); 19096 WRITE_CI_DDR_PHY_REG_DATAr(unit,.5, 0x00000000); 19097 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x00000000); 19098 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x00100000); 19099 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.4, 0x8000003c); 19100 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.4, 0xc000003c); 19101 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.4, 0x8000003c); 19102 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x00100000); 19103 WRITE_CI_DDR_PHY_REG_DATAr(unit,.1, 0x00000000); 19104 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x00100000); 19105 WRITE_CI_DDR_PHY_REG_DATAr(unit,.3, 0x00000000); 19106 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x00100000); 19107 WRITE_CI_DDR_PHY_REG_DATAr(unit,.5, 0x00000000); 19108 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.0, 0x8000003c); 19109 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.0, 0xe000003c); 19110 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.0, 0xa000003c); 19111 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x0043f000); 19112 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.2, 0x8000003c); 19113 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.2, 0xe000003c); 19114 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.2, 0xa000003c); 19115 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x0043f000); 19116 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.4, 0x8000003c); 19117 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.4, 0xe000003c); 19118 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.4, 0xa000003c); 19119 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x0043f000); 19120 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x0043f000); 19121 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x0000000a); 19122 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.0, 0xa000003c); 19123 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.0, 0xc0000040); 19124 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.0, 0x80000040); 19125 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x0000000a); 19126 WRITE_CI_DDR_PHY_REG_DATAr(unit,.1, 0x00000000); 19127 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x0043f000); 19128 WRITE_CI_DDR_PHY_REG_DATAr(unit,.3, 0x00000000); 19129 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x0043f000); 19130 WRITE_CI_DDR_PHY_REG_DATAr(unit,.5, 0x00000000); 19131 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x0000000a); 19132 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x0000000a); 19133 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.0, 0x80000040); 19134 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.0, 0xc00003a4); 19135 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.0, 0x800003a4); 19136 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x0000000a); 19137 WRITE_CI_DDR_PHY_REG_DATAr(unit,.1, 0x00000000); 19138 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x0043f000); 19139 WRITE_CI_DDR_PHY_REG_DATAr(unit,.3, 0x00000000); 19140 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x0043f000); 19141 WRITE_CI_DDR_PHY_REG_DATAr(unit,.5, 0x00000000); 19142 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x0000000a); 19143 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x0000000a); 19144 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.0, 0x800003a4); 19145 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.0, 0xc00005a4); 19146 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.0, 0x800005a4); 19147 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x0000000a); 19148 WRITE_CI_DDR_PHY_REG_DATAr(unit,.1, 0x00000000); 19149 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x0043f000); 19150 WRITE_CI_DDR_PHY_REG_DATAr(unit,.3, 0x00000000); 19151 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x0043f000); 19152 WRITE_CI_DDR_PHY_REG_DATAr(unit,.5, 0x00000000); 19153 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x0043f000); 19154 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x0000000a); 19155 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.2, 0xa000003c); 19156 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.2, 0xc0000040); 19157 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.2, 0x80000040); 19158 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x0000000a); 19159 WRITE_CI_DDR_PHY_REG_DATAr(unit,.1, 0x00000000); 19160 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x0000000a); 19161 WRITE_CI_DDR_PHY_REG_DATAr(unit,.3, 0x00000000); 19162 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x0043f000); 19163 WRITE_CI_DDR_PHY_REG_DATAr(unit,.5, 0x00000000); 19164 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x0000000a); 19165 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x0000000a); 19166 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.2, 0x80000040); 19167 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.2, 0xc00003a4); 19168 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.2, 0x800003a4); 19169 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x0000000a); 19170 WRITE_CI_DDR_PHY_REG_DATAr(unit,.1, 0x00000000); 19171 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x0000000a); 19172 WRITE_CI_DDR_PHY_REG_DATAr(unit,.3, 0x00000000); 19173 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x0043f000); 19174 WRITE_CI_DDR_PHY_REG_DATAr(unit,.5, 0x00000000); 19175 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x0000000a); 19176 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x0000000a); 19177 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.2, 0x800003a4); 19178 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.2, 0xc00005a4); 19179 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.2, 0x800005a4); 19180 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x0000000a); 19181 WRITE_CI_DDR_PHY_REG_DATAr(unit,.1, 0x00000000); 19182 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x0000000a); 19183 WRITE_CI_DDR_PHY_REG_DATAr(unit,.3, 0x00000000); 19184 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x0043f000); 19185 WRITE_CI_DDR_PHY_REG_DATAr(unit,.5, 0x00000000); 19186 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x0043f000); 19187 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x0000000a); 19188 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.4, 0xa000003c); 19189 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.4, 0xc0000040); 19190 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.4, 0x80000040); 19191 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x0000000a); 19192 WRITE_CI_DDR_PHY_REG_DATAr(unit,.1, 0x00000000); 19193 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x0000000a); 19194 WRITE_CI_DDR_PHY_REG_DATAr(unit,.3, 0x00000000); 19195 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x0000000a); 19196 WRITE_CI_DDR_PHY_REG_DATAr(unit,.5, 0x00000000); 19197 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x0000000a); 19198 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x0000000a); 19199 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.4, 0x80000040); 19200 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.4, 0xc00003a4); 19201 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.4, 0x800003a4); 19202 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x0000000a); 19203 WRITE_CI_DDR_PHY_REG_DATAr(unit,.1, 0x00000000); 19204 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x0000000a); 19205 WRITE_CI_DDR_PHY_REG_DATAr(unit,.3, 0x00000000); 19206 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x0000000a); 19207 WRITE_CI_DDR_PHY_REG_DATAr(unit,.5, 0x00000000); 19208 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x0000000a); 19209 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x0000000a); 19210 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.4, 0x800003a4); 19211 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.4, 0xc00005a4); 19212 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.4, 0x800005a4); 19213 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x0000000a); 19214 WRITE_CI_DDR_PHY_REG_DATAr(unit,.1, 0x00000000); 19215 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x0000000a); 19216 WRITE_CI_DDR_PHY_REG_DATAr(unit,.3, 0x00000000); 19217 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x0000000a); 19218 WRITE_CI_DDR_PHY_REG_DATAr(unit,.5, 0x00000000); 19219 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x0000000a); 19220 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x00000003); 19221 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.0, 0x800005a4); 19222 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.0, 0xc0000360); 19223 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.0, 0x80000360); 19224 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x00000003); 19225 WRITE_CI_DDR_PHY_REG_DATAr(unit,.1, 0x00000000); 19226 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x0000000a); 19227 WRITE_CI_DDR_PHY_REG_DATAr(unit,.3, 0x00000000); 19228 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x0000000a); 19229 WRITE_CI_DDR_PHY_REG_DATAr(unit,.5, 0x00000000); 19230 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x00000003); 19231 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x00000003); 19232 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.0, 0x80000360); 19233 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.0, 0xc0000560); 19234 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.0, 0x80000560); 19235 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x00000003); 19236 WRITE_CI_DDR_PHY_REG_DATAr(unit,.1, 0x00000000); 19237 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x0000000a); 19238 WRITE_CI_DDR_PHY_REG_DATAr(unit,.3, 0x00000000); 19239 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x0000000a); 19240 WRITE_CI_DDR_PHY_REG_DATAr(unit,.5, 0x00000000); 19241 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x00000003); 19242 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x00000007); 19243 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.0, 0x80000560); 19244 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.0, 0xc0000364); 19245 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.0, 0x80000364); 19246 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x00000007); 19247 WRITE_CI_DDR_PHY_REG_DATAr(unit,.1, 0x00000000); 19248 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x0000000a); 19249 WRITE_CI_DDR_PHY_REG_DATAr(unit,.3, 0x00000000); 19250 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x0000000a); 19251 WRITE_CI_DDR_PHY_REG_DATAr(unit,.5, 0x00000000); 19252 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x00000007); 19253 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x00000007); 19254 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.0, 0x80000364); 19255 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.0, 0xc0000564); 19256 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.0, 0x80000564); 19257 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x00000007); 19258 WRITE_CI_DDR_PHY_REG_DATAr(unit,.1, 0x00000000); 19259 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x0000000a); 19260 WRITE_CI_DDR_PHY_REG_DATAr(unit,.3, 0x00000000); 19261 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x0000000a); 19262 WRITE_CI_DDR_PHY_REG_DATAr(unit,.5, 0x00000000); 19263 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x00000007); 19264 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x00000001); 19265 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.0, 0x80000564); 19266 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.0, 0xc00003ac); 19267 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.0, 0x800003ac); 19268 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x00000001); 19269 WRITE_CI_DDR_PHY_REG_DATAr(unit,.1, 0x00000000); 19270 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x0000000a); 19271 WRITE_CI_DDR_PHY_REG_DATAr(unit,.3, 0x00000000); 19272 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x0000000a); 19273 WRITE_CI_DDR_PHY_REG_DATAr(unit,.5, 0x00000000); 19274 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x00000001); 19275 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x00000001); 19276 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.0, 0x800003ac); 19277 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.0, 0xc00005ac); 19278 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.0, 0x800005ac); 19279 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x00000001); 19280 WRITE_CI_DDR_PHY_REG_DATAr(unit,.1, 0x00000000); 19281 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x0000000a); 19282 WRITE_CI_DDR_PHY_REG_DATAr(unit,.3, 0x00000000); 19283 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x0000000a); 19284 WRITE_CI_DDR_PHY_REG_DATAr(unit,.5, 0x00000000); 19285 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x0000000a); 19286 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x00000003); 19287 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.2, 0x800005a4); 19288 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.2, 0xc0000360); 19289 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.2, 0x80000360); 19290 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x00000001); 19291 WRITE_CI_DDR_PHY_REG_DATAr(unit,.1, 0x00000000); 19292 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x00000003); 19293 WRITE_CI_DDR_PHY_REG_DATAr(unit,.3, 0x00000000); 19294 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x0000000a); 19295 WRITE_CI_DDR_PHY_REG_DATAr(unit,.5, 0x00000000); 19296 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x00000003); 19297 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x00000003); 19298 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.2, 0x80000360); 19299 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.2, 0xc0000560); 19300 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.2, 0x80000560); 19301 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x00000001); 19302 WRITE_CI_DDR_PHY_REG_DATAr(unit,.1, 0x00000000); 19303 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x00000003); 19304 WRITE_CI_DDR_PHY_REG_DATAr(unit,.3, 0x00000000); 19305 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x0000000a); 19306 WRITE_CI_DDR_PHY_REG_DATAr(unit,.5, 0x00000000); 19307 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x00000003); 19308 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x00000007); 19309 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.2, 0x80000560); 19310 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.2, 0xc0000364); 19311 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.2, 0x80000364); 19312 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x00000001); 19313 WRITE_CI_DDR_PHY_REG_DATAr(unit,.1, 0x00000000); 19314 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x00000007); 19315 WRITE_CI_DDR_PHY_REG_DATAr(unit,.3, 0x00000000); 19316 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x0000000a); 19317 WRITE_CI_DDR_PHY_REG_DATAr(unit,.5, 0x00000000); 19318 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x00000007); 19319 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x00000007); 19320 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.2, 0x80000364); 19321 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.2, 0xc0000564); 19322 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.2, 0x80000564); 19323 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x00000001); 19324 WRITE_CI_DDR_PHY_REG_DATAr(unit,.1, 0x00000000); 19325 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x00000007); 19326 WRITE_CI_DDR_PHY_REG_DATAr(unit,.3, 0x00000000); 19327 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x0000000a); 19328 WRITE_CI_DDR_PHY_REG_DATAr(unit,.5, 0x00000000); 19329 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x00000007); 19330 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x00000001); 19331 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.2, 0x80000564); 19332 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.2, 0xc00003ac); 19333 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.2, 0x800003ac); 19334 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x00000001); 19335 WRITE_CI_DDR_PHY_REG_DATAr(unit,.1, 0x00000000); 19336 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x00000001); 19337 WRITE_CI_DDR_PHY_REG_DATAr(unit,.3, 0x00000000); 19338 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x0000000a); 19339 WRITE_CI_DDR_PHY_REG_DATAr(unit,.5, 0x00000000); 19340 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x00000001); 19341 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x00000001); 19342 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.2, 0x800003ac); 19343 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.2, 0xc00005ac); 19344 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.2, 0x800005ac); 19345 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x00000001); 19346 WRITE_CI_DDR_PHY_REG_DATAr(unit,.1, 0x00000000); 19347 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x00000001); 19348 WRITE_CI_DDR_PHY_REG_DATAr(unit,.3, 0x00000000); 19349 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x0000000a); 19350 WRITE_CI_DDR_PHY_REG_DATAr(unit,.5, 0x00000000); 19351 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x0000000a); 19352 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x00000003); 19353 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.4, 0x800005a4); 19354 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.4, 0xc0000360); 19355 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.4, 0x80000360); 19356 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x00000001); 19357 WRITE_CI_DDR_PHY_REG_DATAr(unit,.1, 0x00000000); 19358 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x00000001); 19359 WRITE_CI_DDR_PHY_REG_DATAr(unit,.3, 0x00000000); 19360 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x00000003); 19361 WRITE_CI_DDR_PHY_REG_DATAr(unit,.5, 0x00000000); 19362 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x00000003); 19363 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x00000003); 19364 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.4, 0x80000360); 19365 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.4, 0xc0000560); 19366 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.4, 0x80000560); 19367 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x00000001); 19368 WRITE_CI_DDR_PHY_REG_DATAr(unit,.1, 0x00000000); 19369 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x00000001); 19370 WRITE_CI_DDR_PHY_REG_DATAr(unit,.3, 0x00000000); 19371 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x00000003); 19372 WRITE_CI_DDR_PHY_REG_DATAr(unit,.5, 0x00000000); 19373 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x00000003); 19374 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x00000007); 19375 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.4, 0x80000560); 19376 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.4, 0xc0000364); 19377 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.4, 0x80000364); 19378 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x00000001); 19379 WRITE_CI_DDR_PHY_REG_DATAr(unit,.1, 0x00000000); 19380 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x00000001); 19381 WRITE_CI_DDR_PHY_REG_DATAr(unit,.3, 0x00000000); 19382 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x00000007); 19383 WRITE_CI_DDR_PHY_REG_DATAr(unit,.5, 0x00000000); 19384 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x00000007); 19385 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x00000007); 19386 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.4, 0x80000364); 19387 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.4, 0xc0000564); 19388 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.4, 0x80000564); 19389 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x00000001); 19390 WRITE_CI_DDR_PHY_REG_DATAr(unit,.1, 0x00000000); 19391 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x00000001); 19392 WRITE_CI_DDR_PHY_REG_DATAr(unit,.3, 0x00000000); 19393 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x00000007); 19394 WRITE_CI_DDR_PHY_REG_DATAr(unit,.5, 0x00000000); 19395 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x00000007); 19396 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x00000001); 19397 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.4, 0x80000564); 19398 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.4, 0xc00003ac); 19399 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.4, 0x800003ac); 19400 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x00000001); 19401 WRITE_CI_DDR_PHY_REG_DATAr(unit,.1, 0x00000000); 19402 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x00000001); 19403 WRITE_CI_DDR_PHY_REG_DATAr(unit,.3, 0x00000000); 19404 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x00000001); 19405 WRITE_CI_DDR_PHY_REG_DATAr(unit,.5, 0x00000000); 19406 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x00000001); 19407 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x00000001); 19408 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.4, 0x800003ac); 19409 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.4, 0xc00005ac); 19410 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.4, 0x800005ac); 19411 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x00000001); 19412 WRITE_CI_DDR_PHY_REG_DATAr(unit,.1, 0x00000000); 19413 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x00000001); 19414 WRITE_CI_DDR_PHY_REG_DATAr(unit,.3, 0x00000000); 19415 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x00000001); 19416 WRITE_CI_DDR_PHY_REG_DATAr(unit,.5, 0x00000000); 19417 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x00000001); 19418 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x00300000); 19419 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.0, 0x800005ac); 19420 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.0, 0xc0000238); 19421 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.0, 0x80000238); 19422 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x00300000); 19423 WRITE_CI_DDR_PHY_REG_DATAr(unit,.1, 0x00000000); 19424 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x00000001); 19425 WRITE_CI_DDR_PHY_REG_DATAr(unit,.3, 0x00000000); 19426 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x00000001); 19427 WRITE_CI_DDR_PHY_REG_DATAr(unit,.5, 0x00000000); 19428 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x00300000); 19429 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x00300000); 19430 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.0, 0x80000238); 19431 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.0, 0xc0000438); 19432 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.0, 0x80000438); 19433 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x00300000); 19434 WRITE_CI_DDR_PHY_REG_DATAr(unit,.1, 0x00000000); 19435 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x00000001); 19436 WRITE_CI_DDR_PHY_REG_DATAr(unit,.3, 0x00000000); 19437 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x00000001); 19438 WRITE_CI_DDR_PHY_REG_DATAr(unit,.5, 0x00000000); 19439 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x00000001); 19440 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x00300000); 19441 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.2, 0x800005ac); 19442 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.2, 0xc0000238); 19443 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.2, 0x80000238); 19444 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x00300000); 19445 WRITE_CI_DDR_PHY_REG_DATAr(unit,.1, 0x00000000); 19446 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x00300000); 19447 WRITE_CI_DDR_PHY_REG_DATAr(unit,.3, 0x00000000); 19448 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x00000001); 19449 WRITE_CI_DDR_PHY_REG_DATAr(unit,.5, 0x00000000); 19450 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x00300000); 19451 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x00300000); 19452 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.2, 0x80000238); 19453 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.2, 0xc0000438); 19454 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.2, 0x80000438); 19455 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x00300000); 19456 WRITE_CI_DDR_PHY_REG_DATAr(unit,.1, 0x00000000); 19457 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x00300000); 19458 WRITE_CI_DDR_PHY_REG_DATAr(unit,.3, 0x00000000); 19459 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x00000001); 19460 WRITE_CI_DDR_PHY_REG_DATAr(unit,.5, 0x00000000); 19461 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x00000001); 19462 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x00300000); 19463 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.4, 0x800005ac); 19464 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.4, 0xc0000238); 19465 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.4, 0x80000238); 19466 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x00300000); 19467 WRITE_CI_DDR_PHY_REG_DATAr(unit,.1, 0x00000000); 19468 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x00300000); 19469 WRITE_CI_DDR_PHY_REG_DATAr(unit,.3, 0x00000000); 19470 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x00300000); 19471 WRITE_CI_DDR_PHY_REG_DATAr(unit,.5, 0x00000000); 19472 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x00300000); 19473 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x00300000); 19474 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.4, 0x80000238); 19475 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.4, 0xc0000438); 19476 WRITE_CI_DDR_PHY_REG_CTRLr(unit,.4, 0x80000438); 19477 WRITE_CI_DDR_PHY_REG_DATAr(unit,.0, 0x00300000); 19478 WRITE_CI_DDR_PHY_REG_DATAr(unit,.1, 0x00000000); 19479 WRITE_CI_DDR_PHY_REG_DATAr(unit,.2, 0x00300000); 19480 WRITE_CI_DDR_PHY_REG_DATAr(unit,.3, 0x00000000); 19481 WRITE_CI_DDR_PHY_REG_DATAr(unit,.4, 0x00300000); 19482 WRITE_CI_DDR_PHY_REG_DATAr(unit,.5, 0x00000000); 19483 sal_sleep( 2); 19484 WRITE_CI_PHY_CONTROLr(unit,.0, 0x05a53603); 19485 WRITE_CI_PHY_CONTROLr(unit,.0, 0x05a5360f); 19486 WRITE_CI_PHY_CONTROLr(unit,.1, 0x04253603); 19487 WRITE_CI_PHY_CONTROLr(unit,.1, 0x0425360f); 19488 WRITE_CI_PHY_CONTROLr(unit,.2, 0x05a53603); 19489 WRITE_CI_PHY_CONTROLr(unit,.2, 0x05a5360f); 19490 WRITE_CI_PHY_CONTROLr(unit,.3, 0x04253603); 19491 WRITE_CI_PHY_CONTROLr(unit,.3, 0x0425360f); 19492 WRITE_CI_PHY_CONTROLr(unit,.4, 0x05a53603); 19493 WRITE_CI_PHY_CONTROLr(unit,.4, 0x05a5360f); 19494 WRITE_CI_PHY_CONTROLr(unit,.5, 0x04253603); 19495 WRITE_CI_PHY_CONTROLr(unit,.5, 0x0425360f); 19496 sal_sleep( 2); 19497 WRITE_CI_MRS_CMDr(unit,.0, 0x000000bc); 19498 WRITE_CI_MRS_CMDr(unit,.0, 0x000000ce); 19499 WRITE_CI_MRS_CMDr(unit,.1, 0x000000bc); 19500 WRITE_CI_MRS_CMDr(unit,.1, 0x000000ce); 19501 WRITE_CI_MRS_CMDr(unit,.2, 0x000000bc); 19502 WRITE_CI_MRS_CMDr(unit,.2, 0x000000ce); 19503 WRITE_CI_MRS_CMDr(unit,.3, 0x000000bc); 19504 WRITE_CI_MRS_CMDr(unit,.3, 0x000000ce); 19505 WRITE_CI_MRS_CMDr(unit,.4, 0x000000bc); 19506 WRITE_CI_MRS_CMDr(unit,.4, 0x000000ce); 19507 WRITE_CI_MRS_CMDr(unit,.5, 0x000000bc); 19508 WRITE_CI_MRS_CMDr(unit,.5, 0x000000ce); 19509 sal_sleep( 2); 19510 WRITE_CI_MRS_CMDr(unit,.0, 0x0000008e); 19511 WRITE_CI_MRS_CMDr(unit,.0, 0x000000cf); 19512 WRITE_CI_MRS_CMDr(unit,.1, 0x0000008e); 19513 WRITE_CI_MRS_CMDr(unit,.1, 0x000000cf); 19514 WRITE_CI_MRS_CMDr(unit,.2, 0x0000008e); 19515 WRITE_CI_MRS_CMDr(unit,.2, 0x000000cf); 19516 WRITE_CI_MRS_CMDr(unit,.3, 0x0000008e); 19517 WRITE_CI_MRS_CMDr(unit,.3, 0x000000cf); 19518 WRITE_CI_MRS_CMDr(unit,.4, 0x0000008e); 19519 WRITE_CI_MRS_CMDr(unit,.4, 0x000000cf); 19520 WRITE_CI_MRS_CMDr(unit,.5, 0x0000008e); 19521 WRITE_CI_MRS_CMDr(unit,.5, 0x000000cf); 19522 sal_sleep( 2); 19523 WRITE_CI_MRS_CMDr(unit,.0, 0x0000008f); 19524 WRITE_CI_MRS_CMDr(unit,.0, 0x000000cd); 19525 WRITE_CI_MRS_CMDr(unit,.1, 0x0000008f); 19526 WRITE_CI_MRS_CMDr(unit,.1, 0x000000cd); 19527 WRITE_CI_MRS_CMDr(unit,.2, 0x0000008f); 19528 WRITE_CI_MRS_CMDr(unit,.2, 0x000000cd); 19529 WRITE_CI_MRS_CMDr(unit,.3, 0x0000008f); 19530 WRITE_CI_MRS_CMDr(unit,.3, 0x000000cd); 19531 WRITE_CI_MRS_CMDr(unit,.4, 0x0000008f); 19532 WRITE_CI_MRS_CMDr(unit,.4, 0x000000cd); 19533 WRITE_CI_MRS_CMDr(unit,.5, 0x0000008f); 19534 WRITE_CI_MRS_CMDr(unit,.5, 0x000000cd); 19535 sal_sleep( 2); 19536 WRITE_CI_MRS_CMDr(unit,.0, 0x0000008d); 19537 WRITE_CI_MRS_CMDr(unit,.0, 0x000000cc); 19538 WRITE_CI_MRS_CMDr(unit,.1, 0x0000008d); 19539 WRITE_CI_MRS_CMDr(unit,.1, 0x000000cc); 19540 WRITE_CI_MRS_CMDr(unit,.2, 0x0000008d); 19541 WRITE_CI_MRS_CMDr(unit,.2, 0x000000cc); 19542 WRITE_CI_MRS_CMDr(unit,.3, 0x0000008d); 19543 WRITE_CI_MRS_CMDr(unit,.3, 0x000000cc); 19544 WRITE_CI_MRS_CMDr(unit,.4, 0x0000008d); 19545 WRITE_CI_MRS_CMDr(unit,.4, 0x000000cc); 19546 WRITE_CI_MRS_CMDr(unit,.5, 0x0000008d); 19547 WRITE_CI_MRS_CMDr(unit,.5, 0x000000cc); 19548 sal_sleep( 2); 19549 WRITE_CI_MRS_CMDr(unit,.0, 0x0000008c); 19550 WRITE_CI_MRS_CMDr(unit,.0, 0x000000fc); 19551 WRITE_CI_MRS_CMDr(unit,.1, 0x0000008c); 19552 WRITE_CI_MRS_CMDr(unit,.1, 0x000000fc); 19553 WRITE_CI_MRS_CMDr(unit,.2, 0x0000008c); 19554 WRITE_CI_MRS_CMDr(unit,.2, 0x000000fc); 19555 WRITE_CI_MRS_CMDr(unit,.3, 0x0000008c); 19556 WRITE_CI_MRS_CMDr(unit,.3, 0x000000fc); 19557 WRITE_CI_MRS_CMDr(unit,.4, 0x0000008c); 19558 WRITE_CI_MRS_CMDr(unit,.4, 0x000000fc); 19559 WRITE_CI_MRS_CMDr(unit,.5, 0x0000008c); 19560 WRITE_CI_MRS_CMDr(unit,.5, 0x000000fc); 19561 sal_sleep( 2); 19562 WRITE_CI_CONFIG0r(unit,.3, 0x0324ab03); 19563 WRITE_CI_CONFIG0r(unit,.3, 0x0324aa03); 19564 WRITE_CI_CONFIG0r(unit,.5, 0x0324ab03); 19565 WRITE_CI_CONFIG0r(unit,.5, 0x0324aa03); 19566 WRITE_CI_CONFIG2r(unit,.3, 0x0d4860f0); 19567 WRITE_CI_CONFIG2r(unit,.3, 0x0c4860f0); 19568 WRITE_CI_CONFIG2r(unit,.5, 0x0d4860f0); 19569 WRITE_CI_CONFIG2r(unit,.5, 0x0c4860f0); 19570 sal_sleep( 2); 19571 if (READ_CI_CONFIG0r(unit, 3, &rval) != SOC_E_NONE) { 19572 return; 19573 } 19574 soc_reg_field_set(unit, CI_CONFIG0r, &rval, TWLf, 0xa); 19575 WRITE_CI_CONFIG0r(unit, 3, rval); 19576 if (READ_CI_CONFIG0r(unit, 5, &rval) != SOC_E_NONE) { 19577 return; 19578 } 19579 soc_reg_field_set(unit, CI_CONFIG0r, &rval, TWLf, 0xa); 19580 WRITE_CI_CONFIG0r(unit, 5, rval); 19581 if (READ_CI_CONFIG2r(unit, 3, &rval) != SOC_E_NONE) { 19582 return; 19583 } 19584 soc_reg_field_set(unit, CI_CONFIG2r, &rval, TREAD_ENBf, 0xc); 19585 WRITE_CI_CONFIG2r(unit, 3, rval); 19586 if (READ_CI_CONFIG2r(unit, 3, &rval) != SOC_E_NONE) { 19587 return; 19588 } 19589 soc_reg_field_set(unit, CI_CONFIG2r, &rval, TREAD_ENBf, 0xc); 19590 WRITE_CI_CONFIG2r(unit, 3, rval); 19591 sal_sleep( 2); 19592 19593 } 19594 19595 STATIC int 19596 _katana2_ledup_init(int unit) 19597 { 19598 uint32 rval = 0; 19599 int ix; 19600 int pval1, pval2, pval3, pval4; 19601 struct led_remap { 19602 uint32 reg_addr; 19603 uint32 port0; 19604 uint32 port1; 19605 uint32 port2; 19606 uint32 port3; 19607 } led0_remap[] = { 19608 {CMIC_LEDUP0_PORT_ORDER_REMAP_0_3r, 19609 REMAP_PORT_0f,REMAP_PORT_1f,REMAP_PORT_2f,REMAP_PORT_3f}, 19610 {CMIC_LEDUP0_PORT_ORDER_REMAP_4_7r, 19611 REMAP_PORT_4f,REMAP_PORT_5f,REMAP_PORT_6f,REMAP_PORT_7f}, 19612 {CMIC_LEDUP0_PORT_ORDER_REMAP_8_11r, 19613 REMAP_PORT_8f,REMAP_PORT_9f,REMAP_PORT_10f,REMAP_PORT_11f}, 19614 {CMIC_LEDUP0_PORT_ORDER_REMAP_12_15r, 19615 REMAP_PORT_12f,REMAP_PORT_13f,REMAP_PORT_14f,REMAP_PORT_15f}, 19616 {CMIC_LEDUP0_PORT_ORDER_REMAP_16_19r, 19617 REMAP_PORT_16f,REMAP_PORT_17f,REMAP_PORT_18f,REMAP_PORT_19f}, 19618 {CMIC_LEDUP0_PORT_ORDER_REMAP_20_23r, 19619 REMAP_PORT_20f,REMAP_PORT_21f,REMAP_PORT_22f,REMAP_PORT_23f}, 19620 {CMIC_LEDUP0_PORT_ORDER_REMAP_24_27r, 19621 REMAP_PORT_24f,REMAP_PORT_25f,REMAP_PORT_26f,REMAP_PORT_27f}, 19622 {CMIC_LEDUP0_PORT_ORDER_REMAP_28_31r, 19623 REMAP_PORT_28f,REMAP_PORT_29f,REMAP_PORT_30f,REMAP_PORT_31f}, 19624 {CMIC_LEDUP0_PORT_ORDER_REMAP_32_35r, 19625 REMAP_PORT_32f,REMAP_PORT_33f,REMAP_PORT_34f,REMAP_PORT_35f}, 19626 {CMIC_LEDUP0_PORT_ORDER_REMAP_36_39r, 19627 REMAP_PORT_36f,REMAP_PORT_37f,REMAP_PORT_38f,REMAP_PORT_39f}/*, 19628 {CMIC_LEDUP0_PORT_ORDER_REMAP_40_43r, 19629 REMAP_PORT_40f,REMAP_PORT_41f,REMAP_PORT_42f,REMAP_PORT_43f}, 19630 {CMIC_LEDUP0_PORT_ORDER_REMAP_44_47r, 19631 REMAP_PORT_44f,REMAP_PORT_45f,REMAP_PORT_46f,REMAP_PORT_47f}, 19632 {CMIC_LEDUP0_PORT_ORDER_REMAP_48_51r, 19633 REMAP_PORT_48f,REMAP_PORT_49f,REMAP_PORT_50f,REMAP_PORT_51f}, 19634 {CMIC_LEDUP0_PORT_ORDER_REMAP_52_55r, 19635 REMAP_PORT_52f,REMAP_PORT_53f,REMAP_PORT_54f,REMAP_PORT_55f}, 19636 {CMIC_LEDUP0_PORT_ORDER_REMAP_56_59r, 19637 REMAP_PORT_56f,REMAP_PORT_57f,REMAP_PORT_58f,REMAP_PORT_59f}, 19638 {CMIC_LEDUP0_PORT_ORDER_REMAP_60_63r, 19639 REMAP_PORT_60f,REMAP_PORT_61f,REMAP_PORT_62f,REMAP_PORT_63f}*/ 19640 }; 19641 19642 /* initialize the led remap register settings. 19643 * port 0 entry will not be used for easy index of the physical port starting 1 19644 */ 19645 19646 for (ix = 0; ix < sizeof(led0_remap)/sizeof(led0_remap[0]); ix++) { 19647 pval1 = ((10-ix) * 4); 19648 pval2 = pval1 - 1; 19649 pval3 = pval1 - 2; 19650 pval4 = pval1 - 3; 19651 19652 rval = 0; 19653 soc_reg_field_set(unit, led0_remap[ix].reg_addr, &rval, 19654 led0_remap[ix].port0, pval1); 19655 soc_reg_field_set(unit, led0_remap[ix].reg_addr, &rval, 19656 led0_remap[ix].port1, pval2); 19657 soc_reg_field_set(unit, led0_remap[ix].reg_addr, &rval, 19658 led0_remap[ix].port2, pval3); 19659 soc_reg_field_set(unit, led0_remap[ix].reg_addr, &rval, 19660 led0_remap[ix].port3, pval4); 19661 /* coverity[result_independent_of_operands] */ 19662 SOC_IF_ERROR_RETURN 19663 (soc_pci_write(unit, 19664 soc_reg_addr(unit, led0_remap[ix].reg_addr, REG_PORT_ANY, 0), 19665 rval)); 19666 } 19667 19668 /* Do Raw schan ops because Not all ports may be enabled */ 19669 { 19670 /* XLPORT_LED_CHAIN_CONFIGr */ 19671 if (!SAL_BOOT_BCMSIM) { 19672 _soc_reg32_set(unit, 5, 0, (0x2022b00), (0x00000006)); 19673 } 19674 _soc_reg32_set(unit, 6, 0, (0x2022b00), (0x00000006)); 19675 } 19676 19677 /* initialize the UP0 data ram */ 19678 rval = 0; 19679 for (ix = 0; ix < 256; ix++) { 19680 /* coverity[result_independent_of_operands] */ 19681 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP0_DATA_RAMr(unit,ix, rval)); 19682 } 19683 19684 /* Apply LEDUP delays. */ 19685 /* coverity[result_independent_of_operands] */ 19686 SOC_IF_ERROR_RETURN(READ_CMIC_LEDUP0_CTRLr(unit, &rval)); 19687 soc_reg_field_set(unit,CMIC_LEDUP0_CTRLr, 19688 &rval, LEDUP_SCAN_START_DELAYf, 0x6); 19689 soc_reg_field_set(unit,CMIC_LEDUP0_CTRLr, 19690 &rval, LEDUP_SCAN_INTRA_PORT_DELAYf, 0x5); 19691 /* coverity[result_independent_of_operands] */ 19692 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP0_CTRLr(unit, rval)); 19693 19694 return SOC_E_NONE; 19695 } 19696 19697 int _soc_katana2_misc_init(int unit) 19698 { 19699 soc_info_t *si; 19700 uint32 rval; 19701 uint32 xport_port_enable_reg=0; 19702 uint32 ext_pbmp_count=0; 19703 pbmp_t ext_pbmp; 19704 #if 0 19705 uint32 mxq6_7_rval=0; 19706 #endif 19707 uint32 entry[SOC_MAX_MEM_WORDS], ing_entry[SOC_MAX_MEM_WORDS]; 19708 txlp_port_addr_map_table_entry_t txlp_port_addr_map_table_entry={{0}}; 19709 uint32 start_addr=0; 19710 uint32 end_addr=0; 19711 uint8 mxqblock_port = 0; 19712 soc_pbmp_t pbmp, my_pbmp_xport_xe; 19713 int port, blk_port, blk; 19714 int count; 19715 uint64 reg64; 19716 uint16 dev_id; 19717 uint8 rev_id; 19718 int i, val = 0; 19719 soc_field_t fields[3]; 19720 uint32 values[3]; 19721 int rv; 19722 int phy_speed = 0; 19723 bcmMxqCorePortMode_t core_mode = 0; 19724 bcmMxqPhyPortMode_t phy_mode; 19725 int any_phy_port=0; 19726 uint8 loop=0; 19727 int cfg_num=0; 19728 uint8 mxqblock=0; 19729 uint8 port_count=0; 19730 uint32 xfi_mode[2]={0}; 19731 uint8 wc_10g_21g_sel=0; 19732 uint32 port_speed=0; 19733 uint32 any_port_speed=0; 19734 uint32 num_cis = 0; 19735 uint32 ddr3_clock_mhz = 0; 19736 uint32 num_rows = 32768; 19737 uint32 ddr3_mem_grade = 0; 19738 int my_modid_list[KT2_MAX_MODIDS_PER_TRANSLATION_TABLE] = 19739 { 0, 0, 0, 0 }; 19740 int my_modid_valid[KT2_MAX_MODIDS_PER_TRANSLATION_TABLE] = 19741 { 1, 0, 0, 0 }; 19742 int my_modid_port_base_ptr[KT2_MAX_MODIDS_PER_TRANSLATION_TABLE] = 19743 { 0, 0, 0, 0 }; 19744 19745 soc_field_t port_enable_field[KT2_MAX_MXQPORTS_PER_BLOCK]= 19746 {PORT0f, PORT1f, PORT2f , PORT3f}; 19747 soc_field_t wc_xfi_mode_sel_fld[]={WC0_8_XFI_MODE_SELf,WC1_8_XFI_MODE_SELf}; 19748 uint32 top_misc_control_1_val = 0; 19749 int parity_enable; 19750 19751 soc_cm_get_id(unit, &dev_id, &rev_id); 19752 19753 si = &SOC_INFO(unit); 19754 19755 if (!SOC_IS_RELOADING(unit) && !SOC_WARM_BOOT(unit)) { 19756 /* Clear IPIPE/EIPIE Memories */ 19757 SOC_IF_ERROR_RETURN(soc_katana2_pipe_mem_clear(unit)); 19758 SOC_IF_ERROR_RETURN(soc_katana2_linkphy_mem_clear(unit)); 19759 } 19760 19761 /* Some registers are implemented in memory, need to clear them in order 19762 * to have correct parity value */ 19763 PBMP_PP_ALL_ITER(unit, port) { 19764 SOC_IF_ERROR_RETURN(WRITE_EGR_VLAN_CONTROL_1r(unit, port, 0)); 19765 SOC_IF_ERROR_RETURN(WRITE_EGR_IPMC_CFG2r(unit, port, 0)); 19766 } 19767 19768 /* PP_PORT_GPP_TRANSLATION_x 19769 * 4 instances one each for icfg, il2lu, isw2 and ipars stages of ipipe 19770 * EGR_PP_PORT_GPP_TRANSLATION_x 19771 * 2 instances one each for evlan and ehcpm stages of epipe */ 19772 /* If LinkPHY/SubTag CoE is enabled then all 170 pp_ports cannot be accomodated 19773 * insingle modid. We will use 2 mod_ids. 19774 * All pp_port mapped to front_panel port in one module and 19775 * remaining pp_ports in another module */ 19776 if ((soc_feature(unit, soc_feature_linkphy_coe) && 19777 SOC_INFO(unit).linkphy_enabled) || 19778 (soc_feature(unit, soc_feature_subtag_coe) && 19779 SOC_INFO(unit).subtag_enabled)) { 19780 19781 my_modid_list[0] = 0; 19782 my_modid_valid[0] = 1; 19783 my_modid_port_base_ptr[0] = 0; 19784 19785 /* If not running in the stacking mode, setup the second module 19786 as the default one to host all pp_ports, else, the user will 19787 create the necessary modules with separate APIs */ 19788 if(!SOC_INFO(unit).coe_stacking_mode) { 19789 my_modid_list[1] = 1; 19790 my_modid_valid[1] = 1; 19791 my_modid_port_base_ptr[1] = SOC_KT2_SUBPORT_PP_PORT_INDEX_MIN; 19792 } 19793 } 19794 19795 BCM_IF_ERROR_RETURN( 19796 bcm_kt2_modid_set_all(unit, my_modid_list, my_modid_valid, 19797 my_modid_port_base_ptr)); 19798 19799 #if 0 19800 if (SOC_IS_KATANA2(unit) && SAL_BOOT_QUICKTURN) { 19801 if (soc_property_get(unit, spn_DDR3_AUTO_TUNE, FALSE)) { 19802 LOG_CLI((BSL_META_U(unit, 19803 "QUICKTURN:ATTN \n"))); 19804 _soc_katana2_ci_init(unit); 19805 } 19806 } 19807 #endif 19808 19809 /* default DDR3 Configuration */ 19810 /* 32K Rows * 1k Col * 8 Banks * 16 bits = 4Gb */ 19811 SOC_DDR3_NUM_COLUMNS(unit) = soc_property_get(unit, spn_EXT_RAM_COLUMNS, 19812 1024); 19813 SOC_DDR3_NUM_BANKS(unit) = soc_property_get(unit,spn_EXT_RAM_BANKS, 8); 19814 19815 switch(dev_id) { 19816 case BCM56454_DEVICE_ID: 19817 num_cis = 3; 19818 ddr3_clock_mhz = 800; 19819 si->frequency = 123; 19820 break; 19821 case BCM56455_DEVICE_ID: 19822 num_cis = 3; 19823 ddr3_clock_mhz = 800; 19824 si->frequency = 166; 19825 break; 19826 case BCM55455_DEVICE_ID: 19827 case BCM56456_DEVICE_ID: /* Need to check si->frequency */ 19828 case BCM56457_DEVICE_ID: 19829 case BCM56458_DEVICE_ID: 19830 num_cis = 0; 19831 ddr3_clock_mhz = 0; 19832 if (dev_id == BCM56458_DEVICE_ID) { 19833 si->frequency = 120; 19834 } else { 19835 si->frequency = 205; 19836 } 19837 break; 19838 case BCM55450_DEVICE_ID: 19839 case BCM56248_DEVICE_ID: 19840 case BCM56450_DEVICE_ID: 19841 case BCM56452_DEVICE_ID: 19842 default: /* 56450 */ 19843 num_cis = 6; 19844 ddr3_clock_mhz = 933; /* 933 MHz */ 19845 si->frequency = 205; 19846 break; 19847 } 19848 SOC_DDR3_NUM_MEMORIES(unit) = soc_property_get(unit,spn_EXT_RAM_PRESENT, 19849 num_cis); 19850 SOC_DDR3_NUM_ROWS(unit) = soc_property_get(unit,spn_EXT_RAM_ROWS, 19851 num_rows); 19852 SOC_DDR3_CLOCK_MHZ(unit) = soc_property_get(unit, spn_DDR3_CLOCK_MHZ, 19853 ddr3_clock_mhz); 19854 SOC_DDR3_MEM_GRADE(unit) = soc_property_get(unit, spn_DDR3_MEM_GRADE, 19855 ddr3_mem_grade); 19856 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 19857 "num_cis=%d num_rows=%d ddr3_clock_mhz=%d ddr3_mem_grade=%d " 19858 "num_col=%d num_banks=%d \n"), 19859 SOC_DDR3_NUM_MEMORIES(unit), 19860 SOC_DDR3_NUM_ROWS(unit), 19861 SOC_DDR3_CLOCK_MHZ(unit), 19862 SOC_DDR3_MEM_GRADE(unit), 19863 SOC_DDR3_NUM_COLUMNS(unit), 19864 SOC_DDR3_NUM_BANKS(unit))); 19865 19866 ext_pbmp = soc_property_get_pbmp(unit, spn_PBMP_EXT_MEM, 0); 19867 SOC_PBMP_COUNT(ext_pbmp, ext_pbmp_count); 19868 if (!ext_pbmp_count) { 19869 if (SOC_DDR3_NUM_MEMORIES(unit)) { 19870 ext_pbmp_count=1; 19871 } 19872 } 19873 19874 if (soc_feature(unit, soc_feature_ddr3) && (ext_pbmp_count != 0)) { 19875 /* CI Init */ 19876 soc_ddr40_set_shmoo_dram_config(unit, ((uint32) 0xFFFFFFFF) >> (32 - SOC_DDR3_NUM_MEMORIES(unit))); 19877 if ((soc_ddr40_phy_pll_ctl(unit, 0, SOC_DDR3_CLOCK_MHZ(unit), 1, 0) == SOC_E_NONE) && 19878 (soc_ddr40_ctlr_ctl(unit, 0, 1, 0) == SOC_E_NONE) && 19879 (soc_ddr40_phy_calibrate(unit, 0, 1, 0) == SOC_E_NONE)) { 19880 19881 if (soc_property_get(unit, spn_DDR3_AUTO_TUNE, FALSE)) { 19882 for(i = 0; i < SOC_DDR3_NUM_MEMORIES(unit); i += 2) { 19883 soc_ddr40_shmoo_ctl(unit, i, 1, 1, 0, 0); 19884 } 19885 LOG_CLI((BSL_META_U(unit, 19886 "DDR Tune Completed\n"))); 19887 } else { 19888 rval = SOC_E_NONE; 19889 for(i = 0; i < SOC_DDR3_NUM_MEMORIES(unit); i += 2) { 19890 rval |= soc_ddr40_shmoo_restorecfg(unit, i); 19891 } 19892 if (rval == SOC_E_NONE) { 19893 LOG_CLI((BSL_META_U(unit, 19894 "DDR Tune Values Restored\n"))); 19895 } else { 19896 LOG_CLI((BSL_META_U(unit, 19897 "DDR Tune Values Restore FAILED\n"))); 19898 } 19899 } 19900 } 19901 } 19902 19903 /* Reset MXQPORT MIB counter (registers implemented in memory) */ 19904 SOC_BLOCK_ITER(unit, blk, SOC_BLK_MXQPORT) { 19905 blk_port = SOC_BLOCK_PORT(unit, blk); 19906 if (blk_port < 0) { 19907 continue; 19908 } 19909 rval = 0; 19910 soc_reg_field_set(unit, XPORT_MIB_RESETr, &rval, CLR_CNTf, 0xf); /* All Ports */ 19911 SOC_IF_ERROR_RETURN(WRITE_XPORT_MIB_RESETr(unit, blk_port, rval)); 19912 SOC_IF_ERROR_RETURN(WRITE_XPORT_MIB_RESETr(unit, blk_port, 0)); 19913 } 19914 19915 parity_enable = soc_property_get(unit, spn_PARITY_ENABLE, TRUE); 19916 if (parity_enable) { 19917 (void)_soc_katana2_ser_init(unit); 19918 #ifdef INCLUDE_MEM_SCAN 19919 soc_mem_scan_ser_list_register(unit, TRUE, 19920 _soc_kt2_tcam_ser_info[unit]); 19921 #endif 19922 memset(&_kt2_ser_functions, 0, sizeof(soc_ser_functions_t)); 19923 _kt2_ser_functions._soc_ser_stat_nack_f = &soc_katana2_stat_nack; 19924 _kt2_ser_functions._soc_ser_fail_f = &soc_kt2_ser_fail; 19925 _kt2_ser_functions._soc_ser_mem_nack_f = &soc_katana2_mem_nack; 19926 _kt2_ser_functions._soc_ser_parity_error_cmicm_intr_f = 19927 &soc_katana2_parity_error; 19928 soc_ser_function_register(unit, &_kt2_ser_functions); 19929 } else { 19930 memset(&_kt2_oam_event_functions, 0, sizeof(soc_oam_event_functions_t)); 19931 _kt2_oam_event_functions._soc_oam_event_intr_f = 19932 &soc_katana2_oam_event_process; 19933 soc_oam_event_function_register (unit, &_kt2_oam_event_functions); 19934 } 19935 19936 _soc_katana2_parity_enable_all(unit, parity_enable ? TRUE : FALSE); 19937 #if defined(SER_TR_TEST_SUPPORT) 19938 /*Initialize chip-specific functions for SER testing*/ 19939 memset(&ser_katana2_test_fun, 0, sizeof(soc_ser_test_functions_t)); 19940 ser_katana2_test_fun.inject_error_f = &soc_katana2_ser_inject_error; 19941 ser_katana2_test_fun.test_mem = &soc_katana2_ser_mem_test; 19942 ser_katana2_test_fun.test = &soc_katana2_ser_test; 19943 ser_katana2_test_fun.parity_control = &_ser_test_parity_control_reg_set; 19944 ser_katana2_test_fun.injection_support = &soc_katana2_ser_error_injection_support; 19945 soc_ser_test_functions_register(unit, &ser_katana2_test_fun); 19946 #endif /*defined(SER_TR_TEST_SUPPORT*/ 19947 19948 sal_memset(entry, 0, sizeof(cpu_pbm_entry_t)); 19949 soc_mem_pbmp_field_set(unit, CPU_PBMm, entry, BITMAPf, &PBMP_CMIC(unit)); 19950 SOC_IF_ERROR_RETURN 19951 (soc_mem_write(unit, CPU_PBMm, MEM_BLOCK_ALL, 0, entry)); 19952 19953 sal_memset(entry, 0, sizeof(cpu_pbm_2_entry_t)); 19954 soc_mem_pbmp_field_set(unit, CPU_PBM_2m, entry, BITMAPf, &PBMP_CMIC(unit)); 19955 SOC_IF_ERROR_RETURN 19956 (soc_mem_write(unit, CPU_PBM_2m, MEM_BLOCK_ALL, 0, entry)); 19957 19958 sal_memset(entry, 0, sizeof(multipass_loopback_bitmap_entry_t)); 19959 soc_mem_pbmp_field_set(unit, MULTIPASS_LOOPBACK_BITMAPm, entry, BITMAPf, 19960 &PBMP_LB(unit)); 19961 SOC_IF_ERROR_RETURN 19962 (soc_mem_write(unit, MULTIPASS_LOOPBACK_BITMAPm, MEM_BLOCK_ALL, 0, 19963 entry)); 19964 19965 SOC_PBMP_CLEAR(pbmp); 19966 for (port = 0; port < 42; port++) { 19967 if (IS_LB_PORT(unit, port) || 19968 (si->port_group[port] >= 2 && si->port_group[port] <= 3)) { 19969 SOC_PBMP_PORT_ADD(pbmp, port); 19970 } 19971 } 19972 19973 sal_memset(entry, 0, sizeof(egr_physical_port_entry_t)); 19974 sal_memset(ing_entry, 0, sizeof(ing_physical_port_table_entry_t)); 19975 19976 soc_mem_field32_set(unit, EGR_PHYSICAL_PORTm, entry, PORT_TYPEf, 1); 19977 soc_mem_field32_set(unit, ING_PHYSICAL_PORT_TABLEm, 19978 ing_entry, PORT_TYPEf, 1); 19979 /* Higig ports */ 19980 PBMP_ST_ITER(unit, port) { 19981 if (soc_feature(unit, soc_feature_higig2) && (IS_HL_PORT(unit,port) 19982 || soc_property_port_get(unit, port, spn_HIGIG2_HDR_MODE, 0))) { 19983 SOC_IF_ERROR_RETURN(soc_reg_field32_modify( 19984 unit, XPORT_CONFIGr, port, HIGIG2_MODEf, 1)); 19985 SOC_IF_ERROR_RETURN(soc_reg_field32_modify( 19986 unit, XPORT_CONFIGr, port, HIGIG_MODEf, 0)); 19987 soc_mem_field32_set(unit, ING_PHYSICAL_PORT_TABLEm,ing_entry, 19988 HIGIG2f,1); 19989 soc_mem_field32_set(unit, EGR_PHYSICAL_PORTm,entry, 19990 HIGIG2f,1); 19991 } else { 19992 SOC_IF_ERROR_RETURN(soc_reg_field32_modify( 19993 unit, XPORT_CONFIGr, port, HIGIG_MODEf, 1)); 19994 SOC_IF_ERROR_RETURN(soc_reg_field32_modify( 19995 unit, XPORT_CONFIGr, port, HIGIG2_MODEf, 0)); 19996 soc_mem_field32_set(unit, ING_PHYSICAL_PORT_TABLEm,ing_entry, 19997 HIGIG2f,0); 19998 soc_mem_field32_set(unit, EGR_PHYSICAL_PORTm,entry, 19999 HIGIG2f,0); 20000 } 20001 SOC_IF_ERROR_RETURN(soc_mem_write(unit, EGR_PHYSICAL_PORTm, 20002 MEM_BLOCK_ALL, port, entry)); 20003 SOC_IF_ERROR_RETURN(soc_mem_write(unit, ING_PHYSICAL_PORT_TABLEm, 20004 MEM_BLOCK_ALL, port, ing_entry)); 20005 } 20006 20007 /* CMIC higig index */ 20008 /* Setup the cpu_hg_port specifically in HG2 mode */ 20009 soc_mem_field32_set(unit, ING_PHYSICAL_PORT_TABLEm, ing_entry, 20010 HIGIG2f, 1); 20011 soc_mem_field32_set(unit, EGR_PHYSICAL_PORTm,entry, 20012 HIGIG2f, 1); 20013 SOC_IF_ERROR_RETURN(soc_mem_write( 20014 unit, EGR_PHYSICAL_PORTm, MEM_BLOCK_ALL, si->cpu_hg_index, entry)); 20015 SOC_IF_ERROR_RETURN(soc_mem_write( 20016 unit, ING_PHYSICAL_PORT_TABLEm, MEM_BLOCK_ALL, 20017 si->cpu_hg_index, ing_entry)); 20018 20019 /* Loopback port */ 20020 soc_mem_field32_set(unit, EGR_PHYSICAL_PORTm, entry, PORT_TYPEf, 2); 20021 soc_mem_field32_set(unit, ING_PHYSICAL_PORT_TABLEm, ing_entry, 20022 PORT_TYPEf, 2); 20023 SOC_IF_ERROR_RETURN(soc_mem_write( 20024 unit, EGR_PHYSICAL_PORTm, MEM_BLOCK_ALL, LB_PORT(unit), entry)); 20025 SOC_IF_ERROR_RETURN(soc_mem_write( 20026 unit, ING_PHYSICAL_PORT_TABLEm, 20027 MEM_BLOCK_ALL, LB_PORT(unit), ing_entry)); 20028 /* ingress physical port to pp_port mapping */ 20029 SOC_IF_ERROR_RETURN(soc_mem_field32_modify( 20030 unit, ING_PHYSICAL_PORT_TABLEm, 20031 LB_PORT(unit), PP_PORTf, LB_PORT(unit))); 20032 20033 /* pp_port to egress physical port mapping */ 20034 SOC_IF_ERROR_RETURN(soc_mem_field32_modify( 20035 unit, PP_PORT_TO_PHYSICAL_PORT_MAPm, 20036 LB_PORT(unit), DESTINATIONf,LB_PORT(unit))); 20037 20038 /* All quad ports in default config */ 20039 20040 SOC_IF_ERROR_RETURN(_soc_katana2_get_cfg_num(unit, &cfg_num)); 20041 if (cfg_num >= (sizeof(bcm56450_tdm)/sizeof(bcm56450_tdm[0]))) { 20042 return SOC_E_FAIL; 20043 } 20044 if (bcm56450_tdm[cfg_num] == NULL ) { 20045 LOG_CLI((BSL_META_U(unit, 20046 "Internal: Not implemented Cfg => %d \n"),cfg_num)); 20047 return SOC_E_FAIL; 20048 } 20049 /* Check whether MXQ8,9 are in XFI mode or not */ 20050 for (mxqblock=8; mxqblock <=9 ; mxqblock++) { 20051 port_count=0; 20052 xfi_mode[mxqblock-8] = 0; 20053 if ((mxqblock == 8) || (mxqblock == 9)) { 20054 for (loop=0;loop<KT2_MAX_MXQPORTS_PER_BLOCK; loop+=2) { 20055 if (SOC_PBMP_MEMBER((PBMP_ALL(unit)), 20056 (*kt2_mxqblock_ports[unit])[mxqblock][loop])) { 20057 if (bcm56450_speed[unit][cfg_num] 20058 [(*kt2_mxqblock_ports[unit])[mxqblock][loop]-1] == 10000) { 20059 port_count++; 20060 } 20061 } 20062 } 20063 for (loop=0;loop<KT2_MAX_MXQPORTS_PER_BLOCK; loop+=2) { 20064 if (SOC_PBMP_MEMBER((PBMP_ALL(unit)), 20065 (*kt2_mxqblock_ports[unit])[mxqblock-2][loop])) { 20066 if (bcm56450_speed[unit][cfg_num] 20067 [(*kt2_mxqblock_ports[unit])[mxqblock-2][loop]-1] == 10000) { 20068 port_count++; 20069 } 20070 } 20071 } 20072 if (port_count == KT2_MAX_MXQPORTS_PER_BLOCK) { 20073 /*Need To Set XFI Mode then */ 20074 xfi_mode[mxqblock-8] = 1; 20075 } 20076 SOC_IF_ERROR_RETURN(READ_TOP_MISC_CONTROL_1r( 20077 unit,&top_misc_control_1_val)); 20078 soc_reg_field_set(unit, TOP_MISC_CONTROL_1r, 20079 &top_misc_control_1_val, 20080 wc_xfi_mode_sel_fld[mxqblock-8], 20081 xfi_mode[mxqblock-8]); 20082 SOC_IF_ERROR_RETURN(WRITE_TOP_MISC_CONTROL_1r( 20083 unit,top_misc_control_1_val)); 20084 } 20085 } 20086 if ((xfi_mode[0] == 1) || (xfi_mode[1] == 1)) { 20087 /* Reinitialize katana2 phy addresses */ 20088 SOC_IF_ERROR_RETURN(soc_phyctrl_software_init(unit)); 20089 } 20090 20091 SOC_PBMP_CLEAR(my_pbmp_xport_xe); 20092 my_pbmp_xport_xe = soc_property_get_pbmp_default(unit, spn_PBMP_XPORT_XE, 20093 my_pbmp_xport_xe); 20094 SOC_BLOCK_ITER(unit, blk, SOC_BLK_MXQPORT) { 20095 blk_port = SOC_BLOCK_PORT(unit, blk); 20096 if (blk_port < 0) { 20097 continue; 20098 } 20099 SOC_IF_ERROR_RETURN(soc_katana2_get_port_mxqblock( 20100 unit,blk_port,&mxqblock)); 20101 xport_port_enable_reg = 0; 20102 any_phy_port=0; 20103 any_port_speed=0; 20104 for (loop=0;loop<KT2_MAX_MXQPORTS_PER_BLOCK; loop++) { 20105 if (SOC_PBMP_MEMBER((PBMP_ALL(unit)), 20106 (*kt2_mxqblock_ports[unit])[mxqblock][loop])) { 20107 if (((*kt2_mxqblock_ports[unit])[mxqblock][loop] == KT2_OLP_PORT) && 20108 (si->olp_port[0] == 1) ) { 20109 /* 20110 LOG_CLI((BSL_META_U(unit, 20111 "QUICKTURN:ATTN:Olp Trick" 20112 "Need RegfileChange MXQ:%d:\n"),mxqblock)); 20113 */ 20114 soc_reg_field_set(unit, XPORT_PORT_ENABLEr, 20115 &xport_port_enable_reg, 20116 port_enable_field[0], 1); /*Enable port */ 20117 } else { 20118 soc_reg_field_set(unit, XPORT_PORT_ENABLEr, 20119 &xport_port_enable_reg, 20120 port_enable_field[loop], 1); /*Enable port */ 20121 } 20122 if (any_phy_port == 0) { 20123 any_phy_port= (*kt2_mxqblock_ports[unit])[mxqblock][loop]; 20124 any_port_speed= bcm56450_speed[unit][cfg_num] 20125 [(*kt2_mxqblock_ports[unit])[mxqblock][loop]-1]; 20126 } 20127 } else { 20128 soc_reg_field_set(unit, XPORT_PORT_ENABLEr, 20129 &xport_port_enable_reg, 20130 port_enable_field[loop], 0);/*Disable port */ 20131 } 20132 } 20133 20134 rval = 0; 20135 phy_speed = bcm56450_speed[unit][cfg_num][any_phy_port-1]; 20136 if (SOC_PBMP_MEMBER(my_pbmp_xport_xe, any_phy_port)) { 20137 if (phy_speed == 21000) { 20138 /* 21G HG ports support IEEE encapsulation to speed upto 20G */ 20139 phy_speed = 20000; 20140 } else { 20141 phy_speed = 10000; 20142 } 20143 } 20144 SOC_IF_ERROR_RETURN(soc_katana2_get_phy_port_mode( 20145 unit, any_phy_port, 20146 phy_speed, 20147 &phy_mode)); 20148 soc_reg_field_set(unit, XPORT_MODE_REGr, &rval, 20149 PHY_PORT_MODEf, phy_mode); 20150 20151 SOC_IF_ERROR_RETURN(soc_katana2_get_core_port_mode( 20152 unit,blk_port,&core_mode)); 20153 soc_reg_field_set(unit, XPORT_MODE_REGr, &rval, 20154 CORE_PORT_MODEf, core_mode); 20155 wc_10g_21g_sel = 0; 20156 if ((mxqblock>=6) && (mxqblock<=9)) { 20157 for (loop=0;loop<KT2_MAX_MXQPORTS_PER_BLOCK; loop++) { 20158 port_speed= bcm56450_speed[unit][cfg_num] 20159 [(*kt2_mxqblock_ports[unit])[mxqblock][loop]-1]; 20160 if ((mxqblock==8) || (mxqblock==9)) { 20161 if ((SAL_BOOT_QUICKTURN) && 20162 (core_mode == bcmMxqCorePortModeSingle) && 20163 (SOC_PBMP_MEMBER(si->linkphy_pbm, 20164 (*kt2_mxqblock_ports[unit])[mxqblock][loop]))) { 20165 LOG_CLI((BSL_META_U(unit, 20166 "QUICKTURN: ATTN : 10G_21G_SEL=0 \n"))); 20167 wc_10g_21g_sel = 0; 20168 break; 20169 } 20170 if ((port_speed == 10000) || (port_speed == 21000)) { 20171 wc_10g_21g_sel = 1; 20172 break; 20173 } 20174 } 20175 if ((mxqblock==6) || (mxqblock==7)) { 20176 if ((port_speed == 10000) && (xfi_mode[mxqblock-6] ==1)) { 20177 wc_10g_21g_sel = 1; 20178 break; 20179 } 20180 } 20181 } 20182 #if 0 20183 if (xfi_mode) { /* so obvious 10g speed */ 20184 mxq6_7_rval=0; 20185 soc_reg_field_set(unit, XPORT_MODE_REGr, &mxq6_7_rval, 20186 WC_10G_21G_SELf, wc_10g_21g_sel); 20187 SOC_IF_ERROR_RETURN(WRITE_XPORT_MODE_REGr(unit, 20188 (*kt2_mxqblock_ports[unit])[mxqblock-2][0], mxq6_7_rval)); 20189 } 20190 #endif 20191 soc_reg_field_set(unit, XPORT_MODE_REGr, &rval, 20192 WC_10G_21G_SELf, wc_10g_21g_sel); 20193 20194 } 20195 if ((any_port_speed != 0 ) && 20196 (any_port_speed < 10000)) { 20197 soc_reg_field_set(unit, XPORT_MODE_REGr, &rval, 20198 PORT_GMII_MII_ENABLEf, 1); 20199 } else { 20200 soc_reg_field_set(unit, XPORT_MODE_REGr, &rval, 20201 PORT_GMII_MII_ENABLEf, 0); 20202 } 20203 SOC_IF_ERROR_RETURN(WRITE_XPORT_MODE_REGr(unit, blk_port, rval)); 20204 SOC_IF_ERROR_RETURN(WRITE_XPORT_PORT_ENABLEr(unit, blk_port, 20205 xport_port_enable_reg)); 20206 } 20207 20208 count = 32; 20209 20210 /* Setup main TDM control */ 20211 SOC_IF_ERROR_RETURN(READ_IARB_TDM_CONTROLr(unit, &rval)); 20212 /* BCMSIM handles Single Cell packets */ 20213 if (SAL_BOOT_BCMSIM) { 20214 soc_reg_field_set(unit, IARB_TDM_CONTROLr, &rval, DISABLEf, 1); 20215 } else { 20216 soc_reg_field_set(unit, IARB_TDM_CONTROLr, &rval, DISABLEf, 0); 20217 } 20218 soc_reg_field_set(unit, IARB_TDM_CONTROLr, &rval, TDM_WRAP_PTRf, count); 20219 SOC_IF_ERROR_RETURN(WRITE_IARB_TDM_CONTROLr(unit, rval)); 20220 20221 SOC_IF_ERROR_RETURN(READ_MISCCONFIGr(unit, &rval)); 20222 soc_reg_field_set(unit, MISCCONFIGr, &rval, METERING_CLK_ENf, 1); 20223 SOC_IF_ERROR_RETURN(WRITE_MISCCONFIGr(unit, rval)); 20224 20225 if (0) { 20226 rval = 0; 20227 soc_reg_field_set(unit, ING_BYPASS_CTRLr, &rval, IFP_BYPASS_ENABLEf, 20228 1); 20229 SOC_IF_ERROR_RETURN(WRITE_ING_BYPASS_CTRLr(unit, rval)); 20230 20231 rval = 0; 20232 soc_reg_field_set(unit, EGR_BYPASS_CTRLr, &rval, EFP_BYPASSf, 1); 20233 SOC_IF_ERROR_RETURN(WRITE_EGR_BYPASS_CTRLr(unit, rval)); 20234 } 20235 20236 SOC_IF_ERROR_RETURN(_soc_kt2_l1_port_mx_lane_map_init(unit)); 20237 20238 /* Enable dual hash on L2, L3 and MPLS_ENTRY tables */ 20239 fields[0] = ENABLEf; 20240 values[0] = 1; 20241 fields[1] = HASH_SELECTf; 20242 values[1] = FB_HASH_CRC32_LOWER; 20243 fields[2] = INSERT_LEAST_FULL_HALFf; 20244 values[2] = 1; 20245 SOC_IF_ERROR_RETURN 20246 (soc_reg_fields32_modify(unit, L2_AUX_HASH_CONTROLr, REG_PORT_ANY, 3, 20247 fields, values)); 20248 SOC_IF_ERROR_RETURN 20249 (soc_reg_fields32_modify(unit, L3_AUX_HASH_CONTROLr, REG_PORT_ANY, 3, 20250 fields, values)); 20251 SOC_IF_ERROR_RETURN 20252 (soc_reg_field32_modify(unit, MPLS_ENTRY_HASH_CONTROLr, REG_PORT_ANY, 20253 INSERT_LEAST_FULL_HALFf, 1)); 20254 20255 /* 20256 * IPMC init 20257 */ 20258 20259 /* 20260 * Egress Enable 20261 */ 20262 sal_memset(entry, 0, sizeof(egr_enable_entry_t)); 20263 soc_mem_field32_set(unit, EGR_ENABLEm, entry, PRT_ENABLEf, 0); 20264 for (port = 0; port < 42; port++) { 20265 rv = WRITE_EGR_ENABLEm(unit, MEM_BLOCK_ALL, port, entry); 20266 /* ****************************************************************** */ 20267 20268 /* ****************************************************************** */ 20269 if (SOC_FAILURE(rv)) { 20270 if (SOC_IS_KATANA2(unit) && (rv == _SHR_E_PARAM)) { 20271 continue; 20272 } 20273 return rv; 20274 } 20275 } 20276 20277 sal_memset(entry, 0, sizeof(epc_link_bmap_entry_t)); 20278 SOC_IF_ERROR_RETURN(READ_EPC_LINK_BMAPm(unit, MEM_BLOCK_ALL, 0, 20279 &entry)); 20280 soc_mem_pbmp_field_set(unit, EPC_LINK_BMAPm, entry, PORT_BITMAPf, 20281 &PBMP_CMIC(unit)); 20282 SOC_IF_ERROR_RETURN(WRITE_EPC_LINK_BMAPm(unit, MEM_BLOCK_ALL, 0, entry)); 20283 20284 SOC_IF_ERROR_RETURN(READ_ING_CONFIG_64r(unit, ®64)); 20285 soc_reg64_field32_set(unit, ING_CONFIG_64r, ®64, 20286 L3SRC_HIT_ENABLEf, 1); 20287 soc_reg64_field32_set(unit, ING_CONFIG_64r, ®64, 20288 L2DST_HIT_ENABLEf, 1); 20289 soc_reg64_field32_set(unit, ING_CONFIG_64r, ®64, 20290 APPLY_EGR_MASK_ON_L2f, 1); 20291 soc_reg64_field32_set(unit, ING_CONFIG_64r, ®64, 20292 APPLY_EGR_MASK_ON_L3f, 1); 20293 soc_reg64_field32_set(unit, ING_CONFIG_64r, ®64, 20294 ARP_RARP_TO_FPf, 0x3); /* enable both ARP & RARP */ 20295 soc_reg64_field32_set(unit, ING_CONFIG_64r, ®64, 20296 ARP_VALIDATION_ENf, 1); 20297 soc_reg64_field32_set(unit, ING_CONFIG_64r, ®64, 20298 IGNORE_HG_HDR_LAG_FAILOVERf, 1); 20299 SOC_IF_ERROR_RETURN(WRITE_ING_CONFIG_64r(unit, reg64)); 20300 20301 /* set to allow Mirror bit in Module Header */ 20302 SOC_IF_ERROR_RETURN 20303 (soc_reg_field32_modify(unit, EGR_CONFIG_1r, REG_PORT_ANY, 20304 RING_MODEf, 1)); 20305 20306 SOC_PBMP_ASSIGN(pbmp, PBMP_ALL(unit)); 20307 SOC_PBMP_REMOVE(pbmp, PBMP_LB(unit)); 20308 SOC_IF_ERROR_RETURN(soc_mem_read(unit, ING_EN_EFILTER_BITMAPm, 20309 MEM_BLOCK_ANY, 0, &entry)); 20310 soc_mem_pbmp_field_set(unit, ING_EN_EFILTER_BITMAPm, &entry, BITMAPf, 20311 &pbmp); 20312 SOC_IF_ERROR_RETURN(soc_mem_write(unit, ING_EN_EFILTER_BITMAPm, 20313 MEM_BLOCK_ALL, 0, &entry)); 20314 20315 /* coverity[result_independent_of_operands] */ 20316 SOC_IF_ERROR_RETURN(READ_CMIC_TXBUF_CONFIGr(unit, &rval)); 20317 soc_reg_field_set(unit, CMIC_TXBUF_CONFIGr, &rval, 20318 FIRST_SERVE_BUFFERS_WITH_EOP_CELLSf, 0); 20319 /* coverity[result_independent_of_operands] */ 20320 SOC_IF_ERROR_RETURN(WRITE_CMIC_TXBUF_CONFIGr(unit, rval)); 20321 20322 /* Multicast range initialization */ 20323 SOC_IF_ERROR_RETURN 20324 (soc_hbx_higig2_mcast_sizes_set(unit, 20325 soc_property_get(unit, spn_HIGIG2_MULTICAST_VLAN_RANGE, 20326 SOC_HBX_MULTICAST_RANGE_DEFAULT), 20327 soc_property_get(unit, spn_HIGIG2_MULTICAST_L2_RANGE, 20328 SOC_HBX_MULTICAST_RANGE_DEFAULT), 20329 soc_property_get(unit, spn_HIGIG2_MULTICAST_L3_RANGE, 20330 SOC_HBX_MULTICAST_RANGE_DEFAULT))); 20331 20332 if (soc_mspi_init(unit) != SOC_E_NONE) { 20333 LOG_WARN(BSL_LS_SOC_COMMON, 20334 (BSL_META_U(unit, 20335 "unit %d : MSPI Init Failed\n"), unit)); 20336 } 20337 20338 if (soc_feature(unit, soc_feature_ces)) { 20339 /* 20340 * Add CES TDM ports 20341 */ 20342 for (i = 0;i < 16;i++) { 20343 int port = 39 + i; 20344 SOC_PBMP_PORT_ADD(si->tdm_pbm, port); 20345 si->tdm.port[si->tdm.num++] = port; 20346 if (si->tdm.min > port || si->tdm.min < 0) { 20347 si->tdm.min = port; 20348 } 20349 if (si->tdm.max < port) { 20350 si->tdm.max = port; 20351 } 20352 SOC_PBMP_PORT_ADD(si->tdm.bitmap, port); 20353 } 20354 } 20355 /* TXLP_PORT_ADDR_MAP_TABLE */ 20356 for (mxqblock=8;mxqblock<=9;mxqblock++) { 20357 for (loop=0,start_addr=0;loop<KT2_MAX_MXQPORTS_PER_BLOCK;loop++) { 20358 sal_memset(&txlp_port_addr_map_table_entry,0, 20359 sizeof(txlp_port_addr_map_table_entry_t)); 20360 mxqblock_port=(*kt2_mxqblock_ports[unit])[mxqblock][loop]; 20361 if (SOC_PBMP_MEMBER((PBMP_ALL(unit)), mxqblock_port)) { 20362 if (!SOC_PBMP_MEMBER(si->linkphy_pbm, mxqblock_port)) { 20363 /* 5. As each cell-occupies "4" lines in buffer, [end-start+1] must be a integral 20364 multiple of "4". */ 20365 if (si->port_speed_max[mxqblock_port] <= 2500) { 20366 end_addr = start_addr + (( 6 * 4) - 1); /* 6 Cells */ 20367 } else if (si->port_speed_max[mxqblock_port] <= 10000) { 20368 end_addr = start_addr + ((12 * 4) - 1); /* 12 Cells */ 20369 } else if (si->port_speed_max[mxqblock_port] <= 13000) { 20370 end_addr = start_addr + ((16 * 4) - 1); /* 16 Cells */ 20371 } else if (si->port_speed_max[mxqblock_port] <= 21000) { 20372 end_addr = start_addr + ((20 * 4) - 1); /* 20 Cells */ 20373 } 20374 soc_TXLP_PORT_ADDR_MAP_TABLEm_field_set(unit, 20375 &txlp_port_addr_map_table_entry,START_ADDRf,&start_addr); 20376 soc_TXLP_PORT_ADDR_MAP_TABLEm_field_set(unit, 20377 &txlp_port_addr_map_table_entry,END_ADDRf,&end_addr); 20378 start_addr = end_addr+1; 20379 SOC_IF_ERROR_RETURN(WRITE_TXLP_PORT_ADDR_MAP_TABLEm( 20380 unit,SOC_INFO(unit).txlp_block[mxqblock-8], 20381 loop, &txlp_port_addr_map_table_entry)); 20382 } 20383 } 20384 } 20385 } 20386 SOC_IF_ERROR_RETURN(soc_mem_clear( 20387 unit, MMU_RQE_QUEUE_OP_NODE_MAPm, COPYNO_ALL, TRUE)); 20388 SOC_IF_ERROR_RETURN(soc_mem_clear( 20389 unit, MMU_WRED_QUEUE_OP_NODE_MAPm, COPYNO_ALL, TRUE)); 20390 20391 /* Setup SW2_FP_DST_ACTION_CONTROL */ 20392 fields[0] = HGTRUNK_RES_ENf; 20393 values[0] = 1; 20394 fields[1] = LAG_RES_ENf; 20395 values[1] = 1; 20396 SOC_IF_ERROR_RETURN(soc_reg_fields32_modify(unit, 20397 SW2_FP_DST_ACTION_CONTROLr, REG_PORT_ANY, 2, fields, values)); 20398 20399 /* initialize LED UP0 */ 20400 if (!SOC_WARM_BOOT(unit)) { 20401 SOC_IF_ERROR_RETURN(_katana2_ledup_init(unit)); 20402 } 20403 20404 if (parity_enable) { 20405 SOC_IF_ERROR_RETURN(soc_generic_ser_mem_scan_start(unit)); 20406 } 20407 /* Updating TM setting for FP and VFP TCAMs to improve yield. 20408 * This is NOT needed for B0 revision.*/ 20409 val = ((rev_id == BCM56450_B0_REV_ID) || (rev_id == BCM56450_B1_REV_ID)) ? 20410 0 : 0x30; 20411 if (SOC_REG_IS_VALID(unit, FP_CAM_CONTROL_TM_13_THRU_0r)) { 20412 SOC_IF_ERROR_RETURN(READ_FP_CAM_CONTROL_TM_13_THRU_0r_REG32(unit, &rval)); 20413 soc_reg_field_set(unit, FP_CAM_CONTROL_TM_13_THRU_0r, 20414 &rval, ALL_TCAMS_TM_13_0f, val); 20415 soc_reg_field_set(unit, FP_CAM_CONTROL_TM_13_THRU_0r, 20416 &rval, ALL_GLOBAL_MASK_TCAMS_TM_13_0f, val); 20417 SOC_IF_ERROR_RETURN(WRITE_FP_CAM_CONTROL_TM_13_THRU_0r_REG32(unit, rval)); 20418 } 20419 if (SOC_REG_IS_VALID(unit, VFP_CAM_CONTROL_SLICE_3_0r)) { 20420 SOC_IF_ERROR_RETURN(READ_VFP_CAM_CONTROL_SLICE_3_0r(unit, &rval)); 20421 soc_reg_field_set(unit, VFP_CAM_CONTROL_SLICE_3_0r, 20422 &rval, TMf, val); 20423 SOC_IF_ERROR_RETURN(WRITE_VFP_CAM_CONTROL_SLICE_3_0r(unit, rval)); 20424 } 20425 SOC_IF_ERROR_RETURN(READ_AUX_ARB_CONTROL_2r(unit, &rval)); 20426 soc_reg_field_set(unit, AUX_ARB_CONTROL_2r, &rval, 20427 TCAM_ATOMIC_WRITE_ENABLEf, 1); 20428 SOC_IF_ERROR_RETURN(WRITE_AUX_ARB_CONTROL_2r(unit, rval)); 20429 20430 /* Initializing subport configurations */ 20431 si->subport_group_max = SOC_KT2_SUBPORT_GROUP_MAX; 20432 si->pp_port_index_max = SOC_KT2_SUBPORT_PP_PORT_INDEX_MAX; 20433 si->pp_port_index_min = SOC_KT2_SUBPORT_PP_PORT_INDEX_MIN; 20434 si->subport_port_max = SOC_KT2_MAX_SUBPORTS; 20435 si->lp_tx_databuf_start_addr_max = SOC_KT2_LINKPHY_TX_DATA_BUF_START_ADDR_MAX; 20436 si->lp_tx_databuf_end_addr_min = SOC_KT2_LINKPHY_TX_DATA_BUF_END_ADDR_MIN; 20437 si->lp_tx_databuf_end_addr_max = SOC_KT2_LINKPHY_TX_DATA_BUF_END_ADDR_MAX; 20438 si->lp_tx_stream_start_addr_offset = SOC_KT2_LINKPHY_TX_STREAM_START_ADDR_OFFSET; 20439 si->lp_block_max = SOC_KT2_LINKPHY_BLOCK_MAX; 20440 si->lp_ports_max = SOC_KT2_MAX_LINKPHY_PORTS; 20441 si->lp_streams_per_subport = SOC_KT2_MAX_STREAMS_PER_SUBPORT; 20442 20443 return SOC_E_NONE; 20444 } 20445 20446 #define KA2_MMU_EFIFO_DEPTH 10 20447 #define KA2_MMU_EFIFO_XMIT_THERESHOLD 4 20448 20449 20450 /* Have spilt mmu_init1_port and formed a new funtion to program 20451 * requird parts in case of flex io operation. 20452 * This configures DEST_PORT_CFG_0 and MMU_ENQ_DEST_PPP_CFG_0 registers . 20453 */ 20454 int _soc_katana2_mmu_init_phase4_port(int unit,int port) 20455 { 20456 20457 soc_info_t *si= &SOC_INFO(unit); 20458 uint32 port_cfg0 = 0; 20459 uint32 port_cfg1 = 0; 20460 uint32 port_cfg2 = 0; 20461 uint32 port_cfg3 = 0; 20462 uint32 port_cfg4 = 0; 20463 uint32 port_cfg5 = 0; 20464 uint32 rval; 20465 int pp_port; 20466 int start_pp_port, end_pp_port; 20467 if (SOC_PBMP_MEMBER((PBMP_ALL(unit)), port)) { 20468 if (IS_EXT_MEM_PORT(unit, port)) { 20469 SOC_IF_ERROR_RETURN(READ_DEST_PORT_CFG_0r(unit, &port_cfg0)); 20470 SOC_IF_ERROR_RETURN(READ_DEST_PORT_CFG_1r(unit, &port_cfg1)); 20471 if (port <= 31) { 20472 port_cfg0 |= (1 << port); 20473 } else { 20474 port_cfg1 |= (1 << (port - 32)); 20475 } 20476 20477 SOC_IF_ERROR_RETURN(WRITE_DEST_PORT_CFG_0r(unit, port_cfg0)); 20478 SOC_IF_ERROR_RETURN(WRITE_DEST_PORT_CFG_1r(unit, port_cfg1)); 20479 SOC_IF_ERROR_RETURN(READ_MMU_ENQ_DEST_PPP_CFG_0r(unit, &port_cfg0)); 20480 SOC_IF_ERROR_RETURN(READ_MMU_ENQ_DEST_PPP_CFG_1r(unit, &port_cfg1)); 20481 20482 if (port <= 31) { 20483 port_cfg0 |= (1 << port); 20484 } else { 20485 port_cfg1 |= (1 << (port - 32)); 20486 } 20487 20488 20489 SOC_IF_ERROR_RETURN(WRITE_MMU_ENQ_DEST_PPP_CFG_0r(unit, port_cfg0)); 20490 SOC_IF_ERROR_RETURN(WRITE_MMU_ENQ_DEST_PPP_CFG_1r(unit, port_cfg1)); 20491 20492 SOC_IF_ERROR_RETURN(READ_RQE_PP_PORT_CONFIGr(unit, port, &rval)); 20493 soc_reg_field_set(unit, RQE_PP_PORT_CONFIGr, &rval, BUFF_TYPEf, 1); 20494 SOC_IF_ERROR_RETURN(WRITE_RQE_PP_PORT_CONFIGr(unit, port, rval)); 20495 20496 if (si->port_num_subport[port] > 0) { 20497 start_pp_port = si->port_subport_base[port]; 20498 end_pp_port = si->port_subport_base[port] + 20499 si->port_num_subport[port]; 20500 SOC_IF_ERROR_RETURN(READ_MMU_ENQ_DEST_PPP_CFG_2r(unit, &port_cfg2)); 20501 SOC_IF_ERROR_RETURN(READ_MMU_ENQ_DEST_PPP_CFG_3r(unit, &port_cfg3)); 20502 SOC_IF_ERROR_RETURN(READ_MMU_ENQ_DEST_PPP_CFG_4r(unit, &port_cfg4)); 20503 SOC_IF_ERROR_RETURN(READ_MMU_ENQ_DEST_PPP_CFG_5r(unit, &port_cfg5)); 20504 20505 for (pp_port = start_pp_port; pp_port < end_pp_port; pp_port++) { 20506 if (pp_port <= 31) { 20507 port_cfg0 |= (1 << pp_port); 20508 } else if (pp_port <= 63) { 20509 port_cfg1 |= (1 << (pp_port - 32)); 20510 } else if (pp_port <= 95) { 20511 port_cfg2 |= (1 << (pp_port - 64)); 20512 20513 } else if (pp_port <= 127) { 20514 port_cfg3 |= (1 << (pp_port - 96)); 20515 20516 } else if (pp_port <= 159) { 20517 port_cfg4 |= (1 << (pp_port - 128)); 20518 20519 } else if (pp_port <= 169) { 20520 port_cfg5 |= (1 << (pp_port - 160)); 20521 } 20522 20523 SOC_IF_ERROR_RETURN(READ_RQE_PP_PORT_CONFIGr(unit, pp_port, &rval)); 20524 soc_reg_field_set(unit, RQE_PP_PORT_CONFIGr, &rval, BUFF_TYPEf, 1); 20525 SOC_IF_ERROR_RETURN(WRITE_RQE_PP_PORT_CONFIGr(unit, pp_port, rval)); 20526 /* Add subport in ext_pbmp */ 20527 SOC_PBMP_PORT_ADD(PBMP_EXT_MEM(unit), pp_port); 20528 } 20529 SOC_IF_ERROR_RETURN(WRITE_MMU_ENQ_DEST_PPP_CFG_0r(unit, port_cfg0)); 20530 SOC_IF_ERROR_RETURN(WRITE_MMU_ENQ_DEST_PPP_CFG_1r(unit, port_cfg1)); 20531 SOC_IF_ERROR_RETURN(WRITE_MMU_ENQ_DEST_PPP_CFG_2r(unit, port_cfg2)); 20532 SOC_IF_ERROR_RETURN(WRITE_MMU_ENQ_DEST_PPP_CFG_3r(unit, port_cfg3)); 20533 SOC_IF_ERROR_RETURN(WRITE_MMU_ENQ_DEST_PPP_CFG_4r(unit, port_cfg4)); 20534 SOC_IF_ERROR_RETURN(WRITE_MMU_ENQ_DEST_PPP_CFG_5r(unit, port_cfg5)); 20535 20536 } 20537 } else { 20538 SOC_IF_ERROR_RETURN(READ_DEST_PORT_CFG_0r(unit, &port_cfg0)); 20539 SOC_IF_ERROR_RETURN(READ_DEST_PORT_CFG_1r(unit, &port_cfg1)); 20540 if (port <= 31) { 20541 port_cfg0 &= ~(1 << port); 20542 } else { 20543 port_cfg1 &= ~(1 << (port - 32)); 20544 } 20545 20546 SOC_IF_ERROR_RETURN(WRITE_DEST_PORT_CFG_0r(unit, port_cfg0)); 20547 SOC_IF_ERROR_RETURN(WRITE_DEST_PORT_CFG_1r(unit, port_cfg1)); 20548 SOC_IF_ERROR_RETURN(READ_MMU_ENQ_DEST_PPP_CFG_0r(unit, &port_cfg0)); 20549 SOC_IF_ERROR_RETURN(READ_MMU_ENQ_DEST_PPP_CFG_1r(unit, &port_cfg1)); 20550 20551 if (port <= 31) { 20552 port_cfg0 &= ~(1 << port); 20553 } else { 20554 port_cfg1 &= ~(1 << (port - 32)); 20555 } 20556 20557 SOC_IF_ERROR_RETURN(WRITE_MMU_ENQ_DEST_PPP_CFG_0r(unit, port_cfg0)); 20558 SOC_IF_ERROR_RETURN(WRITE_MMU_ENQ_DEST_PPP_CFG_1r(unit, port_cfg1)); 20559 20560 SOC_IF_ERROR_RETURN(READ_RQE_PP_PORT_CONFIGr(unit, port, &rval)); 20561 soc_reg_field_set(unit, RQE_PP_PORT_CONFIGr, &rval, BUFF_TYPEf, 0); 20562 SOC_IF_ERROR_RETURN(WRITE_RQE_PP_PORT_CONFIGr(unit, port, rval)); 20563 20564 if (si->port_num_subport[port] > 0) { 20565 start_pp_port = si->port_subport_base[port]; 20566 end_pp_port = si->port_subport_base[port] + 20567 si->port_num_subport[port]; 20568 SOC_IF_ERROR_RETURN(READ_MMU_ENQ_DEST_PPP_CFG_2r(unit, &port_cfg2)); 20569 SOC_IF_ERROR_RETURN(READ_MMU_ENQ_DEST_PPP_CFG_3r(unit, &port_cfg3)); 20570 SOC_IF_ERROR_RETURN(READ_MMU_ENQ_DEST_PPP_CFG_4r(unit, &port_cfg4)); 20571 SOC_IF_ERROR_RETURN(READ_MMU_ENQ_DEST_PPP_CFG_5r(unit, &port_cfg5)); 20572 20573 for (pp_port = start_pp_port; pp_port < end_pp_port; pp_port++) { 20574 if (pp_port <= 31) { 20575 port_cfg0 &= ~(1 << pp_port); 20576 } else if (pp_port <= 63) { 20577 port_cfg1 &= ~(1 << (pp_port - 32)); 20578 } else if (pp_port <= 95) { 20579 port_cfg2 &= ~(1 << (pp_port - 64)); 20580 20581 } else if (pp_port <= 127) { 20582 port_cfg3 &= ~(1 << (pp_port - 96)); 20583 20584 } else if (pp_port <= 159) { 20585 port_cfg4 &= ~(1 << (pp_port - 128)); 20586 20587 } else if (pp_port <= 169) { 20588 port_cfg5 &= ~(1 << (pp_port - 160)); 20589 } 20590 20591 SOC_IF_ERROR_RETURN(READ_RQE_PP_PORT_CONFIGr(unit, pp_port, &rval)); 20592 soc_reg_field_set(unit, RQE_PP_PORT_CONFIGr, &rval, BUFF_TYPEf, 0); 20593 SOC_IF_ERROR_RETURN(WRITE_RQE_PP_PORT_CONFIGr(unit, pp_port, rval)); 20594 /* Remove subport from ext_pbmp */ 20595 SOC_PBMP_PORT_REMOVE(PBMP_EXT_MEM(unit), pp_port); 20596 } 20597 SOC_IF_ERROR_RETURN(WRITE_MMU_ENQ_DEST_PPP_CFG_0r(unit, port_cfg0)); 20598 SOC_IF_ERROR_RETURN(WRITE_MMU_ENQ_DEST_PPP_CFG_1r(unit, port_cfg1)); 20599 SOC_IF_ERROR_RETURN(WRITE_MMU_ENQ_DEST_PPP_CFG_2r(unit, port_cfg2)); 20600 SOC_IF_ERROR_RETURN(WRITE_MMU_ENQ_DEST_PPP_CFG_3r(unit, port_cfg3)); 20601 SOC_IF_ERROR_RETURN(WRITE_MMU_ENQ_DEST_PPP_CFG_4r(unit, port_cfg4)); 20602 SOC_IF_ERROR_RETURN(WRITE_MMU_ENQ_DEST_PPP_CFG_5r(unit, port_cfg5)); 20603 } 20604 } 20605 } 20606 20607 return SOC_E_NONE; 20608 } 20609 /* Just splitted _soc_katana2_mmu_init() for flex IO feature */ 20610 /* Configure Egress Fifo */ 20611 /* Port BW Ctrl */ 20612 STATIC int 20613 _soc_katana2_mmu_init_phase1_port(int unit,int port,uint32 *nxtaddr) 20614 { 20615 uint32 rval=0; 20616 soc_info_t *si= &SOC_INFO(unit); 20617 int depth = 0; 20618 int thereshold = 0; 20619 int mxqblock=0; 20620 uint32 max_depth_limit=672; 20621 soc_pbmp_t my_pbmp_xport_xe; 20622 int num_lanes = 0; 20623 int speed = 0; 20624 int port_temp, padding = 0; 20625 20626 if (SOC_PBMP_MEMBER((PBMP_ALL(unit)), port)) { 20627 if (!(IS_CPU_PORT(unit,port) || IS_LB_PORT(unit,port))) { 20628 port_temp = (port-1); 20629 mxqblock = (*kt2_port_to_mxqblock[unit])[port_temp]; 20630 /* Configure Egress Fifo */ 20631 if(mxqblock_max_startaddr[mxqblock] == 0) { 20632 mxqblock_max_startaddr[mxqblock]= *nxtaddr; 20633 } 20634 SOC_PBMP_CLEAR(my_pbmp_xport_xe); 20635 my_pbmp_xport_xe = soc_property_get_pbmp_default(unit, spn_PBMP_XPORT_XE, 20636 my_pbmp_xport_xe); 20637 SOC_IF_ERROR_RETURN(_bcm_kt2_port_lanes_get(unit, port, 20638 &num_lanes)); 20639 if((SOC_PBMP_MEMBER(my_pbmp_xport_xe, port)) && 20640 ((mxqblock == 8) || (mxqblock == 9))) { 20641 speed = (*mxqspeeds[unit])[mxqblock][num_lanes - 1]; 20642 } 20643 } 20644 if (speed == 0) { 20645 speed = si->port_speed_max[port]; 20646 } 20647 rval = 0; 20648 soc_reg_field_set(unit, DEQ_EFIFO_CFGr, &rval, 20649 EGRESS_FIFO_START_ADDRESSf, *nxtaddr); 20650 LOG_VERBOSE(BSL_LS_SOC_COMMON, 20651 (BSL_META_U(unit, 20652 "port=%d nxtaddr=%d \n"),port,*nxtaddr)); 20653 if (speed <= 1000) { 20654 depth = (IS_EXT_MEM_PORT(unit, port)) ? 10 : 2; 20655 thereshold = (IS_EXT_MEM_PORT(unit, port)) ? 8 : 0; 20656 padding = 10 - depth; 20657 } else if (speed <= 2500) { 20658 depth = (IS_EXT_MEM_PORT(unit, port)) ? 14 : 2; 20659 thereshold = (IS_EXT_MEM_PORT(unit, port)) ? 12 : 0; 20660 padding = 14 - depth; 20661 } else if (speed <= 13000) { 20662 depth = (IS_EXT_MEM_PORT(unit, port)) ? 56 : 10; 20663 thereshold = (IS_EXT_MEM_PORT(unit, port)) ? 49 : 0; 20664 padding = 56 - depth; 20665 } else { /* > 13G */ 20666 depth = (IS_EXT_MEM_PORT(unit, port)) ? 112 : 16; 20667 thereshold = (IS_EXT_MEM_PORT(unit, port)) ? 85 : 0; 20668 padding = 112 - depth; 20669 } 20670 if ((IS_EXT_MEM_PORT(unit, port)) && !(PBMP_MEMBER(si->linkphy_pbm, port))) { 20671 soc_reg_field_set(unit, DEQ_EFIFO_CFGr, &rval, 20672 EGRESS_FIFO_XMIT_OVERSPEED_RATE_LIMITERf, 1); 20673 } else { 20674 soc_reg_field_set(unit, DEQ_EFIFO_CFGr, &rval, 20675 EGRESS_FIFO_XMIT_OVERSPEED_RATE_LIMITERf, 0); 20676 } 20677 20678 soc_reg_field_set(unit, DEQ_EFIFO_CFGr, &rval, 20679 EGRESS_FIFO_XMIT_THRESHOLDf, thereshold); 20680 soc_reg_field_set(unit, DEQ_EFIFO_CFGr, &rval, 20681 EGRESS_FIFO_DEPTHf, depth); 20682 if (SOC_PBMP_MEMBER(si->linkphy_pbm, port)) { 20683 soc_reg_field_set(unit, DEQ_EFIFO_CFGr, &rval, 20684 EGRESS_FIFO_LINK_PHYf, 1); 20685 } 20686 *nxtaddr += depth + padding; 20687 if (*nxtaddr > max_depth_limit) { 20688 LOG_CLI((BSL_META_U(unit, 20689 "FATAL: Internal Error: Limit=%d crossed " 20690 "port:%d depth:%d nxtaddr=%d\n"), 20691 max_depth_limit, port, depth, *nxtaddr)); 20692 return SOC_E_RESOURCE; 20693 } 20694 SOC_IF_ERROR_RETURN(WRITE_DEQ_EFIFO_CFGr(unit, port, rval)); 20695 20696 SOC_IF_ERROR_RETURN(_soc_katana2_mmu_init_phase4_port(unit, port)) ; 20697 20698 /* Port BW Ctrl */ 20699 SOC_IF_ERROR_RETURN(READ_TOQ_PORT_BW_CTRLr(unit, port, &rval)); 20700 if (IS_CPU_PORT(unit,port) || IS_LB_PORT(unit,port)) { 20701 soc_reg_field_set(unit, TOQ_PORT_BW_CTRLr, &rval, 20702 PORT_BWf, 50); 20703 soc_reg_field_set(unit, TOQ_PORT_BW_CTRLr, &rval, 20704 START_THRESHOLDf, 127); 20705 } else if (speed >= 10000) { 20706 soc_reg_field_set(unit, TOQ_PORT_BW_CTRLr, &rval, 20707 PORT_BWf, 500); 20708 soc_reg_field_set(unit, TOQ_PORT_BW_CTRLr, &rval, 20709 START_THRESHOLDf, 34); 20710 } else if (speed == 2500) { 20711 soc_reg_field_set(unit, TOQ_PORT_BW_CTRLr, &rval, 20712 PORT_BWf, 125); 20713 soc_reg_field_set(unit, TOQ_PORT_BW_CTRLr, &rval, 20714 START_THRESHOLDf, 19); 20715 } else { 20716 soc_reg_field_set(unit, TOQ_PORT_BW_CTRLr, &rval, 20717 PORT_BWf, 50); 20718 soc_reg_field_set(unit, TOQ_PORT_BW_CTRLr, &rval, 20719 START_THRESHOLDf, 7); 20720 } 20721 SOC_IF_ERROR_RETURN(WRITE_TOQ_PORT_BW_CTRLr(unit, port, rval)); 20722 if (!(IS_CPU_PORT(unit,port) || IS_LB_PORT(unit,port))) { 20723 mxqblock_max_endaddr[mxqblock]=(*nxtaddr)-1; 20724 } 20725 } else { 20726 if (SOC_PORT_VALID(unit, port)) { 20727 SOC_IF_ERROR_RETURN(WRITE_DEQ_EFIFO_CFGr(unit, port, 0)); 20728 SOC_IF_ERROR_RETURN(WRITE_TOQ_PORT_BW_CTRLr(unit, port, 0)); 20729 } 20730 } 20731 return SOC_E_NONE; 20732 } 20733 STATIC int 20734 _soc_katana2_mmu_init_phase1(int unit) 20735 { 20736 uint32 nxtaddr=0; 20737 int port=0; 20738 int mxqblock=0; 20739 int subport=0; 20740 20741 for (mxqblock=0;mxqblock<KT2_MAX_MXQBLOCKS ; mxqblock++) { 20742 mxqblock_max_startaddr[mxqblock]=0; 20743 mxqblock_max_endaddr[mxqblock]=0; 20744 } 20745 20746 /* cpu port */ 20747 SOC_IF_ERROR_RETURN(_soc_katana2_mmu_init_phase1_port(unit,0,&nxtaddr)); 20748 /* lb port */ 20749 SOC_IF_ERROR_RETURN(_soc_katana2_mmu_init_phase1_port(unit,41,&nxtaddr)); 20750 for (mxqblock=0;mxqblock<KT2_MAX_MXQBLOCKS ; mxqblock++) { 20751 for (subport=0;subport<KT2_MAX_MXQPORTS_PER_BLOCK; subport++) { 20752 port = (*kt2_mxqblock_ports[unit])[mxqblock][subport]; 20753 SOC_IF_ERROR_RETURN(_soc_katana2_mmu_init_phase1_port( 20754 unit,port,&nxtaddr)); 20755 } 20756 } 20757 for (mxqblock=0;mxqblock<KT2_MAX_MXQBLOCKS ; mxqblock++) { 20758 LOG_VERBOSE(BSL_LS_SOC_COMMON, 20759 (BSL_META_U(unit, 20760 "start=%d end=%d \n"), 20761 mxqblock_max_startaddr[mxqblock], 20762 mxqblock_max_endaddr[mxqblock])); 20763 } 20764 return SOC_E_NONE; 20765 } 20766 20767 /* Just splitted _soc_katana2_mmu_init() for flex IO feature */ 20768 STATIC int 20769 _soc_katana2_mmu_init_phase3(int unit, int port) 20770 { 20771 uint32 rval=0; 20772 if (SOC_PBMP_MEMBER((PBMP_ALL(unit)), port)) { 20773 soc_reg_field_set(unit, PORT_MAX_PKT_SIZEr, &rval, 20774 PORT_MAX_PKT_SIZEf,49); 20775 } 20776 SOC_IF_ERROR_RETURN(WRITE_PORT_MAX_PKT_SIZEr(unit, port, rval)); 20777 SOC_IF_ERROR_RETURN(WRITE_THDIEXT_PORT_MAX_PKT_SIZEr(unit, port, 20778 rval)); 20779 SOC_IF_ERROR_RETURN(WRITE_THDIEMA_PORT_MAX_PKT_SIZEr(unit, port, 20780 rval)); 20781 SOC_IF_ERROR_RETURN(WRITE_THDIRQE_PORT_MAX_PKT_SIZEr(unit, port, 20782 rval)); 20783 SOC_IF_ERROR_RETURN(WRITE_THDIQEN_PORT_MAX_PKT_SIZEr(unit, port, 20784 rval)); 20785 20786 rval = 0xffff; 20787 SOC_IF_ERROR_RETURN(WRITE_THDIEXT_PORT_PRI_XON_ENABLEr(unit, port, 20788 rval)); 20789 SOC_IF_ERROR_RETURN(WRITE_THDIEXT_PORT_PRI_XON_ENABLEr(unit, port, 20790 rval)); 20791 SOC_IF_ERROR_RETURN(WRITE_THDIEMA_PORT_PRI_XON_ENABLEr(unit, port, 20792 rval)); 20793 SOC_IF_ERROR_RETURN(WRITE_THDIRQE_PORT_PRI_XON_ENABLEr(unit, port, 20794 rval)); 20795 SOC_IF_ERROR_RETURN(WRITE_THDIQEN_PORT_PRI_XON_ENABLEr(unit, port, 20796 rval)); 20797 20798 /* MXQ Ports */ 20799 rval = 0; 20800 if (((port > KT2_CMIC_PORT) && (port < KT2_LPBK_PORT) && 20801 (((*kt2_port_to_mxqblock_subports[unit])[port-1] == 0) || 20802 (port == 30) || (port == 33) || 20803 (port == 36) || (port == 39))) || (IS_LB_PORT(unit,port))) { 20804 rval = 0xffffffff; /* PRIx_GRP = 0x7 */ 20805 } 20806 SOC_IF_ERROR_RETURN(WRITE_PORT_PRI_GRP0r(unit, port, rval)); 20807 SOC_IF_ERROR_RETURN(WRITE_PORT_PRI_GRP1r(unit, port, rval)); 20808 SOC_IF_ERROR_RETURN(WRITE_THDIEXT_PORT_PRI_GRP0r(unit, port, rval)); 20809 SOC_IF_ERROR_RETURN(WRITE_THDIEXT_PORT_PRI_GRP1r(unit, port, rval)); 20810 SOC_IF_ERROR_RETURN(WRITE_THDIEMA_PORT_PRI_GRP0r(unit, port, rval)); 20811 SOC_IF_ERROR_RETURN(WRITE_THDIEMA_PORT_PRI_GRP1r(unit, port, rval)); 20812 SOC_IF_ERROR_RETURN(WRITE_THDIRQE_PORT_PRI_GRP0r(unit, port, rval)); 20813 SOC_IF_ERROR_RETURN(WRITE_THDIRQE_PORT_PRI_GRP1r(unit, port, rval)); 20814 SOC_IF_ERROR_RETURN(WRITE_THDIQEN_PORT_PRI_GRP0r(unit, port, rval)); 20815 SOC_IF_ERROR_RETURN(WRITE_THDIQEN_PORT_PRI_GRP1r(unit, port, rval)); 20816 20817 /* READ_MMU_ENQ_IP_PRI_TO_PG_PROFILE_0r(unit, rval); */ 20818 rval = 0; 20819 if (((port > KT2_CMIC_PORT) && (port < KT2_LPBK_PORT) && 20820 (((*kt2_port_to_mxqblock_subports[unit])[port-1] == 0) || 20821 (port == 30) || (port == 33) || 20822 (port == 36) || (port == 39))) || (IS_LB_PORT(unit,port))) { 20823 if (soc_reg_field_valid(unit, MMU_ENQ_IP_PRI_TO_PG_PROFILE_0r, 20824 kt2_srcport_field_names[port])) { 20825 /* PRIx_GRP = 0x7 */ 20826 soc_reg_field_set(unit, MMU_ENQ_IP_PRI_TO_PG_PROFILE_0r, 20827 &rval,kt2_srcport_field_names[port], 3); 20828 } else { 20829 if (!((port == KT2_OLP_PORT) && 20830 (SOC_INFO(unit).olp_port[0] == 1))) { 20831 LOG_WARN(BSL_LS_SOC_COMMON, 20832 (BSL_META_U(unit, 20833 "WARN: Suspicious Config: Port=%d\n"), 20834 port)); 20835 } 20836 } 20837 } 20838 WRITE_MMU_ENQ_IP_PRI_TO_PG_PROFILE_0r_REG32(unit, rval); 20839 return SOC_E_NONE; 20840 } 20841 20842 STATIC int 20843 _soc_katana2_mmu_init(int unit) 20844 { 20845 uint32 rval; 20846 uint64 r64val, rval64; 20847 int mmu_init_usec, i; 20848 soc_timeout_t to; 20849 /* uint32 entry[SOC_MAX_MEM_WORDS]; */ 20850 mmu_aging_lmt_int_entry_t age_entry; 20851 int count; 20852 int port; 20853 uint16 dev_id; 20854 uint8 rev_id; 20855 uint32 ext_pbmp_count=0; 20856 pbmp_t ext_pbmp; 20857 int num_source_contexts, max_queues; 20858 soc_info_t *si; 20859 uint8 ema_mapping[][8] = { 20860 {0,0,0,0,0,0,0,0} /* Should never be used */ 20861 , 20862 {0,0,0,0,0,0,0,0} 20863 20864 , /* Max queues = 1 */ 20865 {0,0,0,0,1,1,1,1} 20866 20867 , /* Max queues = 2 */ 20868 {0,0,0,1,1,1,2,2} 20869 20870 , /* Max queues = 3 */ 20871 {0,0,1,1,2,2,3,3} 20872 20873 , /* Max queues = 4 */ 20874 {0,0,1,1,2,2,3,4} 20875 20876 , /* Max queues = 5 */ 20877 {0,0,1,1,2,3,4,5} 20878 20879 , /* Max queues = 6 */ 20880 {0,0,1,2,3,4,5,6} 20881 20882 , /* Max queues = 7 */ 20883 {0,1,2,3,4,5,6,7} 20884 /* Max queues = 8 */ 20885 20886 }; 20887 20888 si = &SOC_INFO(unit); 20889 soc_cm_get_id(unit, &dev_id, &rev_id); 20890 20891 /* Init Link List Scheduler */ 20892 rval = 0; 20893 soc_reg_field_set(unit, LLS_SOFT_RESETr, &rval, SOFT_RESETf, 0); 20894 SOC_IF_ERROR_RETURN(WRITE_LLS_SOFT_RESETr(unit, rval)); 20895 20896 rval = 0; 20897 soc_reg_field_set(unit, LLS_INITr, &rval, INITf, 1); 20898 SOC_IF_ERROR_RETURN(WRITE_LLS_INITr(unit, rval)); 20899 20900 /* Wait for LLS init done. */ 20901 if (SAL_BOOT_SIMULATION) { 20902 mmu_init_usec = 10000000; /* Simulation .. 10sec */ 20903 } else { 20904 mmu_init_usec = 50000; 20905 } 20906 soc_timeout_init(&to, mmu_init_usec, 0); 20907 do { 20908 SOC_IF_ERROR_RETURN(READ_LLS_INITr(unit, &rval)); 20909 if (soc_reg_field_get(unit, LLS_INITr, rval, INIT_DONEf)) { 20910 break; 20911 } 20912 if (soc_timeout_check(&to)) { 20913 LOG_WARN(BSL_LS_SOC_COMMON, 20914 (BSL_META_U(unit, 20915 "unit %d : LLS INIT timeout\n"), unit)); 20916 break; 20917 } 20918 } while (TRUE); 20919 20920 /* Setup TDM for MMU Arb & LLS */ 20921 SOC_IF_ERROR_RETURN(_soc_katana2_mmu_tdm_init(unit)); 20922 20923 for(i=0; i<16; i++) { 20924 SOC_IF_ERROR_RETURN(READ_TOQ_EXT_MEM_BW_MAP_TABLEr(unit, i, &rval)); 20925 20926 soc_reg_field_set(unit, TOQ_EXT_MEM_BW_MAP_TABLEr, &rval, 20927 GBL_GUARENTEE_BW_LIMITf, 1450); 20928 soc_reg_field_set(unit, TOQ_EXT_MEM_BW_MAP_TABLEr, &rval, 20929 WR_PHASEf, 142);/* KT2 */ 20930 soc_reg_field_set(unit, TOQ_EXT_MEM_BW_MAP_TABLEr, &rval, 20931 RD_PHASEf, 138);/* KT2 */ 20932 SOC_IF_ERROR_RETURN( 20933 WRITE_TOQ_EXT_MEM_BW_MAP_TABLEr(unit,i,rval)); 20934 } 20935 20936 SOC_IF_ERROR_RETURN(_soc_katana2_mmu_init_phase1(unit)); 20937 20938 rval = 0; 20939 soc_reg_field_set(unit, DEQ_EFIFO_CFG_COMPLETEr, &rval, EGRESS_FIFO_CONFIGURATION_COMPLETEf, 1); 20940 SOC_IF_ERROR_RETURN(WRITE_DEQ_EFIFO_CFG_COMPLETEr(unit, rval)); 20941 20942 /* Enable LLS */ 20943 rval = 0; 20944 soc_reg_field_set(unit, LLS_CONFIG0r, &rval, DEQUEUE_ENABLEf, 1); 20945 soc_reg_field_set(unit, LLS_CONFIG0r, &rval, ENQUEUE_ENABLEf, 1); 20946 soc_reg_field_set(unit, LLS_CONFIG0r, &rval, FC_ENABLEf, 1); 20947 soc_reg_field_set(unit, LLS_CONFIG0r, &rval, MIN_ENABLEf, 1); 20948 soc_reg_field_set(unit, LLS_CONFIG0r, &rval, PORT_SCHEDULER_ENABLEf, 1); 20949 soc_reg_field_set(unit, LLS_CONFIG0r, &rval, SHAPER_ENABLEf, 1); 20950 if (SOC_REG_FIELD_VALID(unit, LLS_CONFIG0r, SPRI_VECT_MODE_ENABLEf)) { 20951 if (soc_feature(unit, soc_feature_vector_based_spri)) { 20952 soc_reg_field_set(unit, LLS_CONFIG0r, &rval, 20953 SPRI_VECT_MODE_ENABLEf, 1); 20954 } 20955 } 20956 SOC_IF_ERROR_RETURN(WRITE_LLS_CONFIG0r(unit, rval)); 20957 20958 /* Enable shaper background refresh */ 20959 rval = 0; 20960 soc_reg_field_set(unit, LLS_MAX_REFRESH_ENABLEr, &rval, L0_MAX_REFRESH_ENABLEf, 1); 20961 soc_reg_field_set(unit, LLS_MAX_REFRESH_ENABLEr, &rval, L1_MAX_REFRESH_ENABLEf, 1); 20962 soc_reg_field_set(unit, LLS_MAX_REFRESH_ENABLEr, &rval, L2_MAX_REFRESH_ENABLEf, 1); 20963 soc_reg_field_set(unit, LLS_MAX_REFRESH_ENABLEr, &rval, PORT_MAX_REFRESH_ENABLEf, 1); 20964 soc_reg_field_set(unit, LLS_MAX_REFRESH_ENABLEr, &rval, S0_MAX_REFRESH_ENABLEf, 1); 20965 soc_reg_field_set(unit, LLS_MAX_REFRESH_ENABLEr, &rval, S1_MAX_REFRESH_ENABLEf, 1); 20966 SOC_IF_ERROR_RETURN(WRITE_LLS_MAX_REFRESH_ENABLEr(unit, rval)); 20967 20968 rval = 0; 20969 soc_reg_field_set(unit, LLS_MIN_REFRESH_ENABLEr, &rval, L0_MIN_REFRESH_ENABLEf, 1); 20970 soc_reg_field_set(unit, LLS_MIN_REFRESH_ENABLEr, &rval, L1_MIN_REFRESH_ENABLEf, 1); 20971 soc_reg_field_set(unit, LLS_MIN_REFRESH_ENABLEr, &rval, L2_MIN_REFRESH_ENABLEf, 1); 20972 SOC_IF_ERROR_RETURN(WRITE_LLS_MIN_REFRESH_ENABLEr(unit, rval)); 20973 20974 /* RQE configuration */ 20975 rval = 0; 20976 soc_reg_field_set(unit, RQE_SCHEDULER_CONFIGr, &rval, 20977 L0_MCM_MODEf, 1); 20978 soc_reg_field_set(unit, RQE_SCHEDULER_CONFIGr, &rval, 20979 L0_CC_MODEf, 1); 20980 soc_reg_field_set(unit, RQE_SCHEDULER_CONFIGr, &rval, 20981 L0_UCM_MODEf, 1); 20982 soc_reg_field_set(unit, RQE_SCHEDULER_CONFIGr, &rval, 20983 L1_MODEf, 1); 20984 SOC_IF_ERROR_RETURN(WRITE_RQE_SCHEDULER_CONFIGr(unit, rval)); 20985 20986 rval = 0; 20987 soc_reg_field_set(unit, RQE_SCHEDULER_WEIGHT_L0_QUEUEr, &rval, 20988 WRR_WEIGHTf, 1); 20989 for(i=0; i<SOC_REG_NUMELS(unit, RQE_SCHEDULER_WEIGHT_L0_QUEUEr); i++) { 20990 SOC_IF_ERROR_RETURN(WRITE_RQE_SCHEDULER_WEIGHT_L0_QUEUEr(unit, i, 20991 rval)); 20992 } 20993 20994 rval = 0; 20995 soc_reg_field_set(unit, RQE_SCHEDULER_WEIGHT_L1_QUEUEr, &rval, 20996 WRR_WEIGHTf, 1); 20997 for(i=0; i<SOC_REG_NUMELS(unit, RQE_SCHEDULER_WEIGHT_L1_QUEUEr); i++) { 20998 SOC_IF_ERROR_RETURN(WRITE_RQE_SCHEDULER_WEIGHT_L1_QUEUEr(unit, i, 20999 rval)); 21000 } 21001 21002 /* Enable all ports */ 21003 COMPILER_64_ZERO(r64val); 21004 COMPILER_64_SET(rval64, 0x3ff, 0xffffffff); /*Bits 0..41 */ 21005 soc_reg64_field_set(unit, INPUT_PORT_RX_ENABLE_64r, &r64val, 21006 INPUT_PORT_RX_ENABLEf, rval64); 21007 SOC_IF_ERROR_RETURN(WRITE_INPUT_PORT_RX_ENABLE_64r(unit, r64val)); 21008 SOC_IF_ERROR_RETURN(WRITE_THDIEMA_INPUT_PORT_RX_ENABLE_64r(unit, r64val)); 21009 SOC_IF_ERROR_RETURN(WRITE_THDIEXT_INPUT_PORT_RX_ENABLE_64r(unit, r64val)); 21010 SOC_IF_ERROR_RETURN(WRITE_THDIQEN_INPUT_PORT_RX_ENABLE_64r(unit, r64val)); 21011 SOC_IF_ERROR_RETURN(WRITE_THDIRQE_INPUT_PORT_RX_ENABLE_64r(unit, r64val)); 21012 21013 SOC_IF_ERROR_RETURN(WRITE_THDI_BYPASSr(unit, 0)); 21014 SOC_IF_ERROR_RETURN(WRITE_THDIQEN_THDI_BYPASSr(unit, 0)); 21015 SOC_IF_ERROR_RETURN(WRITE_THDIRQE_THDI_BYPASSr(unit, 0)); 21016 SOC_IF_ERROR_RETURN(WRITE_THDIEXT_THDI_BYPASSr(unit, 0)); 21017 SOC_IF_ERROR_RETURN(WRITE_THDIEMA_THDI_BYPASSr(unit, 0)); 21018 SOC_IF_ERROR_RETURN(WRITE_THDO_BYPASSr(unit, 0)); 21019 21020 ext_pbmp = soc_property_get_pbmp(unit, spn_PBMP_EXT_MEM, 0); 21021 SOC_PBMP_COUNT(ext_pbmp, ext_pbmp_count); 21022 if (!ext_pbmp_count) { 21023 if (SOC_DDR3_NUM_MEMORIES(unit)) { 21024 ext_pbmp_count=1; 21025 } 21026 } 21027 if (soc_feature(unit, soc_feature_ddr3) && (ext_pbmp_count != 0)) { 21028 /* Configure EMC */ 21029 SOC_IF_ERROR_RETURN(READ_EMC_CFGr(unit, &rval)); 21030 soc_reg_field_set(unit, EMC_CFGr, &rval, NUM_CISf, 21031 SOC_DDR3_NUM_MEMORIES(unit)); /* Number of CIs attached to EMC */ 21032 soc_reg_field_set(unit, EMC_CFGr, &rval, DRAM_SIZEf, 2); 21033 SOC_IF_ERROR_RETURN(WRITE_EMC_CFGr(unit, rval)); 21034 21035 SOC_IF_ERROR_RETURN(READ_EMC_FREE_POOL_SIZESr(unit, &rval)); 21036 soc_reg_field_set(unit, EMC_FREE_POOL_SIZESr, &rval, WTFP_SIZEf, 240); 21037 soc_reg_field_set(unit, EMC_FREE_POOL_SIZESr, &rval, RSFP_SIZEf, 128); 21038 SOC_IF_ERROR_RETURN(WRITE_EMC_FREE_POOL_SIZESr(unit, rval)); 21039 21040 SOC_IF_ERROR_RETURN(READ_EMC_IWRB_SIZEr(unit, &rval)); 21041 soc_reg_field_set(unit, EMC_IWRB_SIZEr, &rval, IWRB_SIZEf, 2); 21042 SOC_IF_ERROR_RETURN(WRITE_EMC_IWRB_SIZEr(unit, rval)); 21043 21044 SOC_IF_ERROR_RETURN(READ_EMC_IRRB_THRESHOLDSr(unit, &rval)); 21045 soc_reg_field_set(unit, EMC_IRRB_THRESHOLDSr, &rval, ALL_Q_XOFF_THRESHOLDf, 0x10); 21046 soc_reg_field_set(unit, EMC_IRRB_THRESHOLDSr, &rval, ALL_UNDERRUN_Q_XOFF_THRESHOLDf, 0x28); 21047 soc_reg_field_set(unit, EMC_IRRB_THRESHOLDSr, &rval, ALL_UNDERRUN_Q_XON_THRESHOLDf, 0x18); 21048 soc_reg_field_set(unit, EMC_IRRB_THRESHOLDSr, &rval, ALL_Q_XON_THRESHOLDf, 8); 21049 SOC_IF_ERROR_RETURN(WRITE_EMC_IRRB_THRESHOLDSr(unit, rval)); 21050 } 21051 21052 /* WRED Configuration */ 21053 if (dev_id != BCM56450_DEVICE_ID) { /* And all other 90MHz variants */ 21054 SOC_IF_ERROR_RETURN(READ_WRED_MISCCONFIGr(unit, &rval)); 21055 soc_reg_field_set(unit, WRED_MISCCONFIGr, &rval, BASE_UPDATE_INTERVALf, 7); 21056 SOC_IF_ERROR_RETURN(WRITE_WRED_MISCCONFIGr(unit, rval)); 21057 21058 SOC_IF_ERROR_RETURN(READ_WRED_PARITY_ERROR_MASKr(unit, &rval)); 21059 soc_reg_field_set(unit, WRED_PARITY_ERROR_MASKr, &rval, UPDATE_INTRPT_MASKf, 0); 21060 SOC_IF_ERROR_RETURN(WRITE_WRED_PARITY_ERROR_MASKr(unit, rval)); 21061 21062 SOC_IF_ERROR_RETURN(READ_MISCCONFIGr(unit, &rval)); 21063 soc_reg_field_set(unit, MISCCONFIGr, &rval, REFRESH_ENf, 1); 21064 SOC_IF_ERROR_RETURN(WRITE_MISCCONFIGr(unit, rval)); 21065 } 21066 for(port = 0; port < 42; port++) { 21067 SOC_IF_ERROR_RETURN(_soc_katana2_mmu_init_phase3(unit, port)); 21068 } 21069 21070 SOC_IF_ERROR_RETURN(_soc_katana2_perq_flex_counters_init(unit, 0)); 21071 21072 rval = 0xffffffff; /* PRIx_GRP = 0x7 */ 21073 SOC_IF_ERROR_RETURN(WRITE_MMU_ENQ_PROFILE_0_PRI_GRP0r(unit, rval)); 21074 SOC_IF_ERROR_RETURN(WRITE_MMU_ENQ_PROFILE_0_PRI_GRP1r(unit, rval)); 21075 SOC_IF_ERROR_RETURN(WRITE_MMU_ENQ_PROFILE_1_PRI_GRP0r(unit, rval)); 21076 SOC_IF_ERROR_RETURN(WRITE_MMU_ENQ_PROFILE_1_PRI_GRP1r(unit, rval)); 21077 SOC_IF_ERROR_RETURN(WRITE_MMU_ENQ_PROFILE_2_PRI_GRP0r(unit, rval)); 21078 SOC_IF_ERROR_RETURN(WRITE_MMU_ENQ_PROFILE_2_PRI_GRP1r(unit, rval)); 21079 SOC_IF_ERROR_RETURN(WRITE_MMU_ENQ_PROFILE_3_PRI_GRP0r(unit, rval)); 21080 SOC_IF_ERROR_RETURN(WRITE_MMU_ENQ_PROFILE_3_PRI_GRP1r(unit, rval)); 21081 21082 /* Input port shared space */ 21083 /* rval = 0; 21084 soc_reg_field_set(unit, USE_SP_SHAREDr, &rval, ENABLEf, 1); 21085 SOC_IF_ERROR_RETURN(WRITE_USE_SP_SHAREDr(unit, rval)); 21086 */ 21087 rval = 0; 21088 SOC_IF_ERROR_RETURN(WRITE_BUFFER_CELL_LIMIT_SP_SHAREDr(unit,0)); 21089 SOC_IF_ERROR_RETURN(WRITE_THDIEXT_BUFFER_CELL_LIMIT_SP_SHAREDr(unit,0)); 21090 SOC_IF_ERROR_RETURN(WRITE_THDIEMA_BUFFER_CELL_LIMIT_SP_SHAREDr(unit,0)); 21091 SOC_IF_ERROR_RETURN(WRITE_THDIRQE_BUFFER_CELL_LIMIT_SP_SHAREDr(unit,0)); 21092 SOC_IF_ERROR_RETURN(WRITE_THDIQEN_BUFFER_CELL_LIMIT_SP_SHAREDr(unit,0)); 21093 21094 /* Input port per-device global headroom */ 21095 rval = 0; 21096 SOC_IF_ERROR_RETURN(READ_OP_THR_CONFIGr(unit, &rval)); 21097 soc_reg_field_set(unit, OP_THR_CONFIGr, &rval, EARLY_E2E_SELECTf, 0); 21098 SOC_IF_ERROR_RETURN(WRITE_OP_THR_CONFIGr(unit, rval)); 21099 21100 /* Helper function for MMU settings based on 21101 memory selection (internal/external/both) and mode (lossless/lossy) */ 21102 21103 if (!SOC_WARM_BOOT(unit)) { 21104 SOC_IF_ERROR_RETURN(_soc_katana2_mmu_init_helper(unit, -1)); 21105 } 21106 21107 21108 /* Initialize MMU internal/external aging limit memory */ 21109 count = soc_mem_index_count(unit, MMU_AGING_LMT_INTm); 21110 sal_memset(&age_entry, 0, sizeof(mmu_aging_lmt_int_entry_t)); 21111 for (i=0; i < count; i++) { 21112 SOC_IF_ERROR_RETURN(WRITE_MMU_AGING_LMT_INTm(unit, 21113 MEM_BLOCK_ALL, i, &age_entry)); 21114 } 21115 21116 count = soc_mem_index_count(unit, MMU_AGING_LMT_EXTm); 21117 for (i=0; i < count; i++) { 21118 SOC_IF_ERROR_RETURN(WRITE_MMU_AGING_LMT_EXTm(unit, 21119 MEM_BLOCK_ALL, i, &age_entry)); 21120 } 21121 21122 SOC_IF_ERROR_RETURN(READ_THDO_DROP_CTR_CONFIGr(unit, &rval)); 21123 soc_reg_field_set(unit, THDO_DROP_CTR_CONFIGr, &rval, OP_CNT_CFGf, 1); 21124 SOC_IF_ERROR_RETURN(WRITE_THDO_DROP_CTR_CONFIGr(unit, rval)); 21125 21126 _soc_kt2_mem_config(unit); 21127 21128 SOC_IF_ERROR_RETURN(_soc_katana2_mmu_set_invalid_parent(unit)); 21129 21130 rval = 0; 21131 soc_reg_field_set(unit, MMU_ENQ_RQE_QUEUE_SELECT_0r, &rval, RQE_QUEUE_PRI_0f, 0); 21132 soc_reg_field_set(unit, MMU_ENQ_RQE_QUEUE_SELECT_0r, &rval, RQE_QUEUE_PRI_1f, 1); 21133 soc_reg_field_set(unit, MMU_ENQ_RQE_QUEUE_SELECT_0r, &rval, RQE_QUEUE_PRI_2f, 2); 21134 soc_reg_field_set(unit, MMU_ENQ_RQE_QUEUE_SELECT_0r, &rval, RQE_QUEUE_PRI_3f, 3); 21135 soc_reg_field_set(unit, MMU_ENQ_RQE_QUEUE_SELECT_0r, &rval, RQE_QUEUE_PRI_4f, 4); 21136 soc_reg_field_set(unit, MMU_ENQ_RQE_QUEUE_SELECT_0r, &rval, RQE_QUEUE_PRI_5f, 5); 21137 soc_reg_field_set(unit, MMU_ENQ_RQE_QUEUE_SELECT_0r, &rval, RQE_QUEUE_PRI_6f, 6); 21138 soc_reg_field_set(unit, MMU_ENQ_RQE_QUEUE_SELECT_0r, &rval, RQE_QUEUE_PRI_7f, 7); 21139 SOC_IF_ERROR_RETURN(WRITE_MMU_ENQ_RQE_QUEUE_SELECT_0r(unit, rval)); 21140 21141 21142 rval = 0; 21143 soc_reg_field_set(unit, MMU_ENQ_RQE_QUEUE_SELECT_1r, &rval, RQE_QUEUE_PRI_8f, 7); 21144 soc_reg_field_set(unit, MMU_ENQ_RQE_QUEUE_SELECT_1r, &rval, RQE_QUEUE_PRI_9f, 7); 21145 soc_reg_field_set(unit, MMU_ENQ_RQE_QUEUE_SELECT_1r, &rval, RQE_QUEUE_PRI_10f, 7); 21146 soc_reg_field_set(unit, MMU_ENQ_RQE_QUEUE_SELECT_1r, &rval, RQE_QUEUE_PRI_11f, 7); 21147 soc_reg_field_set(unit, MMU_ENQ_RQE_QUEUE_SELECT_1r, &rval, RQE_QUEUE_PRI_12f, 7); 21148 soc_reg_field_set(unit, MMU_ENQ_RQE_QUEUE_SELECT_1r, &rval, RQE_QUEUE_PRI_13f, 7); 21149 soc_reg_field_set(unit, MMU_ENQ_RQE_QUEUE_SELECT_1r, &rval, RQE_QUEUE_PRI_14f, 7); 21150 soc_reg_field_set(unit, MMU_ENQ_RQE_QUEUE_SELECT_1r, &rval, RQE_QUEUE_PRI_15f, 7); 21151 SOC_IF_ERROR_RETURN(WRITE_MMU_ENQ_RQE_QUEUE_SELECT_1r(unit, rval)); 21152 21153 21154 /* Configure the internal priority to EMA queue mapping 21155 0 to 7 use an identity mapping. All other priorities use queue 7*/ 21156 /* Refer point number 1.3.3 in KT2 micro arch doc */ 21157 num_source_contexts = _soc_katana2_get_max_stream_ids(unit); 21158 num_source_contexts += si->lb_port; 21159 21160 max_queues = KT2_MAX_NUMBER_INTERLEAVED_PKTS / num_source_contexts; 21161 21162 if (max_queues == 0) { 21163 return SOC_E_INTERNAL; 21164 } 21165 21166 if (max_queues > 8 ) { 21167 max_queues = 8; 21168 } 21169 21170 rval = 0; 21171 soc_reg_field_set(unit, MMU_ENQ_EMA_QUEUE_SELECT_0r, &rval, 21172 EMA_QUEUE_PRI_0f, ema_mapping[max_queues][0]); 21173 soc_reg_field_set(unit, MMU_ENQ_EMA_QUEUE_SELECT_0r, &rval, 21174 EMA_QUEUE_PRI_1f, ema_mapping[max_queues][1]); 21175 soc_reg_field_set(unit, MMU_ENQ_EMA_QUEUE_SELECT_0r, &rval, 21176 EMA_QUEUE_PRI_2f, ema_mapping[max_queues][2]); 21177 soc_reg_field_set(unit, MMU_ENQ_EMA_QUEUE_SELECT_0r, &rval, 21178 EMA_QUEUE_PRI_3f, ema_mapping[max_queues][3]); 21179 soc_reg_field_set(unit, MMU_ENQ_EMA_QUEUE_SELECT_0r, &rval, 21180 EMA_QUEUE_PRI_4f, ema_mapping[max_queues][4]); 21181 soc_reg_field_set(unit, MMU_ENQ_EMA_QUEUE_SELECT_0r, &rval, 21182 EMA_QUEUE_PRI_5f, ema_mapping[max_queues][5]); 21183 soc_reg_field_set(unit, MMU_ENQ_EMA_QUEUE_SELECT_0r, &rval, 21184 EMA_QUEUE_PRI_6f, ema_mapping[max_queues][6]); 21185 soc_reg_field_set(unit, MMU_ENQ_EMA_QUEUE_SELECT_0r, &rval, 21186 EMA_QUEUE_PRI_7f, ema_mapping[max_queues][7]); 21187 SOC_IF_ERROR_RETURN(WRITE_MMU_ENQ_EMA_QUEUE_SELECT_0r(unit, rval)); 21188 21189 rval = 0; 21190 soc_reg_field_set(unit, MMU_ENQ_EMA_QUEUE_SELECT_1r, &rval, 21191 EMA_QUEUE_PRI_8f, max_queues - 1); 21192 soc_reg_field_set(unit, MMU_ENQ_EMA_QUEUE_SELECT_1r, &rval, 21193 EMA_QUEUE_PRI_9f, max_queues - 1); 21194 soc_reg_field_set(unit, MMU_ENQ_EMA_QUEUE_SELECT_1r, &rval, 21195 EMA_QUEUE_PRI_10f, max_queues - 1); 21196 soc_reg_field_set(unit, MMU_ENQ_EMA_QUEUE_SELECT_1r, &rval, 21197 EMA_QUEUE_PRI_11f, max_queues - 1); 21198 soc_reg_field_set(unit, MMU_ENQ_EMA_QUEUE_SELECT_1r, &rval, 21199 EMA_QUEUE_PRI_12f, max_queues - 1); 21200 soc_reg_field_set(unit, MMU_ENQ_EMA_QUEUE_SELECT_1r, &rval, 21201 EMA_QUEUE_PRI_13f, max_queues - 1); 21202 soc_reg_field_set(unit, MMU_ENQ_EMA_QUEUE_SELECT_1r, &rval, 21203 EMA_QUEUE_PRI_14f, max_queues - 1); 21204 soc_reg_field_set(unit, MMU_ENQ_EMA_QUEUE_SELECT_1r, &rval, 21205 EMA_QUEUE_PRI_15f, max_queues - 1); 21206 SOC_IF_ERROR_RETURN(WRITE_MMU_ENQ_EMA_QUEUE_SELECT_1r(unit, rval)); 21207 21208 return SOC_E_NONE; 21209 } 21210 int _soc_katana2_mmu_reconfigure(int unit, int port) 21211 { 21212 SOC_IF_ERROR_RETURN(_soc_katana2_mmu_init_phase4_port(unit, port)); 21213 SOC_IF_ERROR_RETURN(_soc_katana2_mmu_init_phase3(unit, port)); 21214 SOC_IF_ERROR_RETURN(_soc_katana2_mmu_init_helper(unit, port)); 21215 return SOC_E_NONE; 21216 } 21217 21218 STATIC int 21219 _soc_katana2_age_timer_get(int unit, int *age_seconds, int *enabled) 21220 { 21221 uint32 rval; 21222 21223 SOC_IF_ERROR_RETURN(READ_L2_AGE_TIMERr(unit, &rval)); 21224 *enabled = soc_reg_field_get(unit, L2_AGE_TIMERr, rval, AGE_ENAf); 21225 *age_seconds = soc_reg_field_get(unit, L2_AGE_TIMERr, rval, AGE_VALf); 21226 21227 return SOC_E_NONE; 21228 } 21229 21230 STATIC int 21231 _soc_katana2_age_timer_max_get(int unit, int *max_seconds) 21232 { 21233 *max_seconds = 21234 soc_reg_field_get(unit, L2_AGE_TIMERr, 0xffffffff, AGE_VALf); 21235 21236 return SOC_E_NONE; 21237 } 21238 21239 STATIC int 21240 _soc_katana2_age_timer_set(int unit, int age_seconds, int enable) 21241 { 21242 uint32 rval; 21243 21244 rval = 0; 21245 soc_reg_field_set(unit, L2_AGE_TIMERr, &rval, AGE_ENAf, enable); 21246 soc_reg_field_set(unit, L2_AGE_TIMERr, &rval, AGE_VALf, age_seconds); 21247 SOC_IF_ERROR_RETURN(WRITE_L2_AGE_TIMERr(unit, rval)); 21248 21249 return SOC_E_NONE; 21250 } 21251 21252 int kt2_linkphy_port[2][4] = { 21253 {27, 32, 33, 34}, /* {T,R}XLP0 */ 21254 {28, 29, 30, 31} /* {T,R}XLP1 */ 21255 }; 21256 21257 int 21258 soc_kt2_linkphy_port_reg_blk_idx_get( 21259 int unit, int port, int blktype, int *block, int *index) 21260 { 21261 int i,j; 21262 int blk = -1; 21263 int idx = -1; 21264 21265 #ifdef BCM_METROLITE_SUPPORT 21266 if (SOC_IS_METROLITE(unit)) { 21267 return soc_ml_linkphy_port_reg_blk_idx_get(unit, port, 21268 blktype,block,index); 21269 } else 21270 #endif 21271 #ifdef BCM_SABER2_SUPPORT 21272 if (SOC_IS_SABER2(unit)) { 21273 return soc_sb2_linkphy_port_reg_blk_idx_get(unit, port, 21274 blktype,block,index); 21275 } 21276 #endif 21277 21278 for (i=0; i<2; i++) { 21279 for(j=0; j<4; j++) { 21280 if(port == kt2_linkphy_port[i][j]) { 21281 blk = i; 21282 idx = j; 21283 break; 21284 } 21285 } 21286 } 21287 21288 if (blktype == SOC_BLK_TXLP) { 21289 if (blk == 0) { 21290 blk = TXLP0_BLOCK(unit); 21291 } else if (blk == 1) { 21292 blk = TXLP1_BLOCK(unit); 21293 } 21294 } else if (blktype == SOC_BLK_RXLP) { 21295 if (blk == 0) { 21296 blk = RXLP0_BLOCK(unit); 21297 } else if (blk == 1) { 21298 blk = RXLP1_BLOCK(unit); 21299 } 21300 } else { 21301 return SOC_E_PARAM; 21302 } 21303 21304 if (block != NULL) { 21305 *block = blk; 21306 } 21307 if (index != NULL) { 21308 *index = idx; 21309 } 21310 if ((blk == -1) || (idx == -1)) { 21311 return SOC_E_NOT_FOUND; 21312 } 21313 return SOC_E_NONE; 21314 } 21315 21316 int 21317 soc_kt2_linkphy_port_blk_idx_get( 21318 int unit, int port, int *block, int *index) 21319 { 21320 int i,j; 21321 int blk = -1; 21322 int idx = -1; 21323 21324 for (i=0; i<2; i++) { 21325 for(j=0; j<4; j++) { 21326 if(port == kt2_linkphy_port[i][j]) { 21327 blk = i; 21328 idx = j; 21329 break; 21330 } 21331 } 21332 } 21333 21334 if (block != NULL) { 21335 *block = blk; 21336 } 21337 if (index != NULL) { 21338 *index = idx; 21339 } 21340 if ((blk == -1) || (idx == -1)) { 21341 return SOC_E_NOT_FOUND; 21342 } 21343 return SOC_E_NONE; 21344 } 21345 21346 int soc_kt2_linkphy_get_portid(int unit, int block, int index) { 21347 if (index > 3) { 21348 return -1; 21349 } 21350 if ((block == TXLP0_BLOCK(unit)) || (block == RXLP0_BLOCK(unit))) { 21351 return kt2_linkphy_port[0][index]; 21352 } else if ((block == TXLP1_BLOCK(unit)) || (block == RXLP1_BLOCK(unit))) { 21353 return kt2_linkphy_port[1][index]; 21354 } 21355 return -1; 21356 } 21357 21358 21359 /* 21360 * cpu port (mmu port 0): 48 queues (0-47) 21361 * loopback port (48-71) 21362 * hg ports : 24 queues 21363 * other ports : 8 queues 21364 */ 21365 21366 int 21367 soc_katana2_num_cosq_init(int unit) 21368 { 21369 soc_info_t *si; 21370 int port, prev_port; 21371 int numq = 0, i; 21372 int pp_port_cos; 21373 int start_pp_port, end_pp_port; 21374 int packing_mode; 21375 int max_queue_num = -1; 21376 int max_port = -1; 21377 int num_uc_cosq = 0; 21378 21379 si = &SOC_INFO(unit); 21380 prev_port = 0; 21381 packing_mode = soc_property_get(unit, spn_MMU_MULTI_PACKETS_PER_CELL, 0); 21382 21383 21384 max_queue_num = soc_mem_index_max(unit, MMU_THDO_QCONFIG_CELLm); 21385 if (max_queue_num == 0) { 21386 /* Possible with first time in soc_init() call */ 21387 /* coverity[dead_error_line:FALSE] */ 21388 return SOC_E_NONE; 21389 } 21390 21391 max_port = LB_PORT(unit) + 1; 21392 for (port = 0; port < max_port; port++) { 21393 si->port_num_ext_cosq[port] = 0; 21394 si->port_num_cosq[port] = 0; 21395 21396 if (IS_CPU_PORT(unit, port)) { 21397 si->port_cosq_base[port] = 0; 21398 si->port_uc_cosq_base[port] = 0; 21399 si->port_num_uc_cosq[port] = NUM_CPU_COSQ(unit); 21400 si->port_num_ext_cosq[port] = 0; 21401 } else if (IS_LB_PORT(unit, port)) { 21402 si->port_cosq_base[port] = 48; 21403 si->port_uc_cosq_base[port] = 48; 21404 si->port_num_uc_cosq[port] = 24; 21405 } else { 21406 si->port_uc_cosq_base[port] = si->port_uc_cosq_base[prev_port] + 21407 numq; 21408 si->port_cosq_base[port] = si->port_uc_cosq_base[port]; 21409 if (IS_HG_PORT(unit, port)) { 21410 si->port_num_uc_cosq[port] = 24; 21411 } else { 21412 num_uc_cosq = soc_property_port_get(unit, port, 21413 spn_LLS_NUM_L2UC, 8); /* KT2_DEFAULT_NUM_PHYSICAL_QUEUES */ 21414 if (num_uc_cosq < 8) { 21415 num_uc_cosq = 8; 21416 } 21417 si->port_num_uc_cosq[port] = num_uc_cosq; 21418 } 21419 } 21420 prev_port = port; 21421 21422 if (IS_CPU_PORT(unit, port)) { 21423 /* first front panel port needs to start with 72 */ 21424 numq = 72; 21425 } else { 21426 numq = si->port_num_uc_cosq[port]; 21427 } 21428 if (si->port_cosq_base[port] + si->port_num_uc_cosq[port] > 21429 max_queue_num) { 21430 LOG_ERROR(BSL_LS_SOC_COMMON, 21431 (BSL_META_U(unit, 21432 "###ATTN:Physical queue assignment for port:%d exceeded" 21433 " max value:%d###\n INFO: Start queue:%d End Queue %d\n"), 21434 port, max_queue_num, 21435 si->port_cosq_base[port], 21436 si->port_cosq_base[port] + si->port_num_uc_cosq[port])); 21437 return SOC_E_CONFIG; 21438 } 21439 21440 21441 pp_port_cos = soc_property_port_get(unit, port, 21442 spn_NUM_SUBPORT_COS, 4); 21443 21444 if (si->port_num_subport[port] > 0) { 21445 start_pp_port = si->port_subport_base[port]; 21446 end_pp_port = si->port_subport_base[port] + 21447 si->port_num_subport[port]; 21448 LOG_VERBOSE(BSL_LS_SOC_COMMON, 21449 (BSL_META_U(unit, 21450 "start_pp_port:%d end_pp_port:%d \n"), 21451 start_pp_port, end_pp_port)); 21452 21453 for (i = start_pp_port; i < end_pp_port; i++) { 21454 si->port_uc_cosq_base[i] = si->port_uc_cosq_base[port] + numq; 21455 si->port_cosq_base[i] = si->port_uc_cosq_base[i]; 21456 si->port_num_uc_cosq[i] = pp_port_cos; 21457 numq += pp_port_cos; 21458 LOG_VERBOSE(BSL_LS_SOC_COMMON, 21459 (BSL_META_U(unit, 21460 "port:%d port_uc_cosq_base[pp_port%d]:%d:End:%d \n"), 21461 port, i, si->port_uc_cosq_base[i], 21462 si->port_uc_cosq_base[i] + 21463 si->port_num_uc_cosq[i] - 1)); 21464 if (si->port_cosq_base[i] + si->port_num_uc_cosq[i] > 21465 max_queue_num) { 21466 LOG_ERROR(BSL_LS_SOC_COMMON, 21467 (BSL_META_U(unit, 21468 "###ATTN:Subport queue assignment for port:%d exceeded" 21469 " max value:%d###\n INFO: Start queue:%d End Queue %d \n"), 21470 port, max_queue_num, 21471 si->port_cosq_base[i], 21472 si->port_cosq_base[i] + 21473 si->port_num_uc_cosq[i] - 1)); 21474 return SOC_E_CONFIG; 21475 } 21476 /*if (soc_feature(unit, soc_feature_mmu_packing)) { */ 21477 if (packing_mode) { 21478 si->port_cosq_base[i] += (soc_mem_index_count(unit,LLS_L2_PARENTm) >> 1); 21479 si->port_num_cosq[i] = si->port_num_uc_cosq[i]; 21480 LOG_VERBOSE(BSL_LS_SOC_COMMON, 21481 (BSL_META_U(unit, 21482 "Packing Cosq Base:%d Num Cosq:%d \n"), 21483 si->port_cosq_base[i], si->port_num_cosq[i])); 21484 if (si->port_cosq_base[i] + si->port_num_cosq[i] > 21485 max_queue_num) { 21486 LOG_ERROR(BSL_LS_SOC_COMMON, 21487 (BSL_META_U(unit, 21488 "###ATTN:Packing queue assignment for " 21489 "port:%d exceeded max value:%d###\n" 21490 "INFO:Start queue:%d End Queue %d\n"), 21491 port, max_queue_num, 21492 si->port_cosq_base[i], 21493 si->port_cosq_base[i] + si->port_num_cosq[i])); 21494 return SOC_E_CONFIG; 21495 } 21496 } 21497 } 21498 } 21499 21500 /*if (soc_feature(unit, soc_feature_mmu_packing)) { */ 21501 if (packing_mode) { 21502 if (!IS_CPU_PORT(unit, port)) { 21503 si->port_cosq_base[port] += 2048; 21504 } 21505 si->port_num_cosq[port] = si->port_num_uc_cosq[port]; 21506 } 21507 21508 LOG_VERBOSE(BSL_LS_SOC_COMMON, 21509 (BSL_META_U(unit, 21510 "\nport num %d cosq_base %d num_cosq %d"), 21511 port, si->port_cosq_base[port], si->port_num_uc_cosq[port])); 21512 } 21513 21514 return SOC_E_NONE; 21515 } 21516 21517 soc_blk_ctr_reg_desc_t _soc_kt2_blk_ctr_reg_desc[] = 21518 { 21519 { 21520 SOC_BLK_RXLP, 21521 { 21522 {RXLP_UNEXPECTED_ETHERTYPEr, 1, 1, 0}, 21523 {RXLP_UNKNOWN_STREAM_IDr, 1, 1, 0}, 21524 {RXLP_DFC_FRAMESr, 1, 1, 0}, 21525 {RXLP_DFC_FRAME_UNEXPECTED_MACDAr, 1, 1, 0}, 21526 {RXLP_DFC_FRAME_UNEXPECTED_MACSAr, 1, 1, 0}, 21527 {RXLP_DFC_HEADER_OPCODE_ERRORr, 1, 1, 0}, 21528 {RXLP_DFC_HEADER_TIME_ERRORr, 1, 1, 0}, 21529 {RXLP_DFC_LENGTH_ERRORr, 1, 1, 0}, 21530 {INVALIDr, 0, 0} 21531 } 21532 } 21533 }; 21534 21535 void 21536 soc_kt2_blk_counter_config(int unit) 21537 { 21538 soc_control_t *soc = SOC_CONTROL(unit); 21539 /* TimeBeing Skipping it due to some NACK issue */ 21540 if (!(SAL_BOOT_BCMSIM || SAL_BOOT_PLISIM)) { 21541 LOG_CLI((BSL_META_U(unit, 21542 "QUICKTURN|BOARD:ATTN:Skipping RXLP Counter(NACK-issue)\n"))); 21543 soc->blk_ctr_desc_count = 0; 21544 } else { 21545 soc->blk_ctr_desc_count = COUNTOF(_soc_kt2_blk_ctr_reg_desc); 21546 } 21547 soc->blk_ctr_desc = _soc_kt2_blk_ctr_reg_desc; 21548 } 21549 21550 /* 21551 * Katana chip driver functions. 21552 */ 21553 soc_functions_t soc_katana2_drv_funs = { 21554 _soc_katana2_misc_init, 21555 _soc_katana2_mmu_init, 21556 _soc_katana2_age_timer_get, 21557 _soc_katana2_age_timer_max_get, 21558 _soc_katana2_age_timer_set, 21559 }; 21560 21561 /* KT2 OAM */ 21562 STATIC 21563 soc_field_t _soc_kt2_oam_interrupt_fields[] = { 21564 SOME_RMEP_CCM_DEFECTf, 21565 SOME_RDI_DEFECTf, 21566 ERROR_CCM_DEFECTf, 21567 XCON_CCM_DEFECTf, 21568 ANY_RMEP_TLV_INTERFACE_UPf, 21569 ANY_RMEP_TLV_INTERFACE_DOWNf, 21570 ANY_RMEP_TLV_PORT_UPf, 21571 ANY_RMEP_TLV_PORT_DOWNf, 21572 INVALIDf 21573 }; 21574 21575 void 21576 soc_kt2_oam_interrupt_process(int unit) 21577 { 21578 uint32 rval; 21579 int rv, found = 0, fidx = 0; 21580 soc_kt2_oam_handler_t oam_handler_snapshot = kt2_oam_handler[unit]; 21581 21582 rv = READ_IP1_INTR_ENABLE_1r(unit, &rval); 21583 while (_soc_kt2_oam_interrupt_fields[fidx] != INVALIDf) { 21584 if (soc_reg_field_get(unit, IP1_INTR_ENABLE_1r, rval, 21585 _soc_kt2_oam_interrupt_fields[fidx])) { 21586 found++; 21587 } 21588 fidx++; 21589 } 21590 if (!found) { 21591 LOG_ERROR(BSL_LS_SOC_COMMON, \ 21592 (BSL_META_U(unit, \ 21593 "Unexpected interrupt \ 21594 received for OAM rv=0x%x!!\n"), rv)); 21595 } else { 21596 if (oam_handler_snapshot != NULL) { 21597 (void)(oam_handler_snapshot(unit, 21598 _soc_kt2_oam_interrupt_fields[fidx])); 21599 } 21600 } 21601 } 21602 21603 void 21604 soc_kt2_rxlp_interrupt_process(int unit, bcm_port_t port, uint32 rval) 21605 { 21606 soc_kt2_linkphy_handler_t lp_handler_snapshot = kt2_linkphy_handler[unit]; 21607 int rv = SOC_E_NONE; 21608 /* Call the registered handler */ 21609 if (lp_handler_snapshot != NULL) { 21610 rv = lp_handler_snapshot(unit, port, rval); 21611 if (rv < 0) { 21612 LOG_ERROR(BSL_LS_SOC_COMMON, \ 21613 (BSL_META_U(unit, \ 21614 "Interrupt \ 21615 handler error for LINK PHY rv=0x%x!!\n"), rv)); 21616 } 21617 } 21618 } 21619 21620 void 21621 soc_kt2_oam_handler_register(int unit, soc_kt2_oam_handler_t handler) 21622 { 21623 int rv, fidx = 0; 21624 uint32 rval; 21625 21626 kt2_oam_handler[unit] = handler; 21627 21628 rv = READ_IP1_INTR_ENABLE_1r(unit, &rval); 21629 if (rv) { 21630 LOG_ERROR(BSL_LS_SOC_COMMON, 21631 (BSL_META_U(unit, 21632 "unit %d: Error reading %s reg !!\n"), 21633 unit, SOC_REG_NAME(unit, IP1_INTR_ENABLE_1r))); 21634 } 21635 while (_soc_kt2_oam_interrupt_fields[fidx] != INVALIDf) { 21636 soc_reg_field_set(unit, IP1_INTR_ENABLE_1r, &rval, 21637 _soc_kt2_oam_interrupt_fields[fidx], 1); 21638 fidx++; 21639 } 21640 rv = WRITE_IP1_INTR_ENABLE_1r(unit, rval); 21641 if (rv) { 21642 LOG_ERROR(BSL_LS_SOC_COMMON, 21643 (BSL_META_U(unit, 21644 "unit %d: Error writing %s reg !!\n"), 21645 unit, SOC_REG_NAME(unit, IP1_INTR_ENABLE_1r))); 21646 } 21647 /* Write CMIC enable register for oam event*/ 21648 if (SOC_IS_SABER2(unit)) { 21649 /* For Saber2 */ 21650 (void)soc_cmicm_intr3_enable(unit, SB2_OAM_CMIC_INTR_MASK); 21651 } else { 21652 (void)soc_cmicm_intr2_enable(unit, KT2_OAM_CMIC_INTR_MASK); 21653 } 21654 } 21655 21656 21657 void 21658 soc_kt2_linkphy_handler_register(int unit, soc_kt2_linkphy_handler_t handler) 21659 { 21660 kt2_linkphy_handler[unit] = handler; 21661 } 21662 21663 21664 void 21665 soc_kt2_oam_ser_handler_register(int unit, soc_kt2_oam_ser_handler_t handler) 21666 { 21667 kt2_oam_ser_handler[unit] = handler; 21668 } 21669 21670 int 21671 soc_kt2_oam_ser_process(int unit, soc_mem_t mem, int index) 21672 { 21673 if (kt2_oam_ser_handler[unit]) { 21674 return kt2_oam_ser_handler[unit](unit, mem, index); 21675 } else { 21676 return SOC_E_UNAVAIL; 21677 } 21678 } 21679 21680 21681 21682 /* soc_kt2_mem_config: 21683 * Over-ride the default table sizes (from regsfile) for any SKUs here 21684 */ 21685 int 21686 soc_kt2_mem_config(int unit, int dev_id) 21687 { 21688 int rv = SOC_E_NONE; 21689 int num_ipv6_128b_entries = 0; 21690 int config_v6_entries = 0; 21691 int defip_config = 0; 21692 soc_persist_t *sop = SOC_PERSIST(unit); 21693 21694 switch (dev_id) { 21695 case BCM56248_DEVICE_ID: 21696 case BCM56456_DEVICE_ID: 21697 sop->memState[LLS_L2_PARENTm].index_max = 1023; 21698 sop->memState[LLS_L2_SHAPER_CONFIG_LOWERm].index_max=127; 21699 sop->memState[LLS_L2_SHAPER_CONFIG_UPPERm].index_max=127; 21700 sop->memState[MMU_THDO_QCONFIG_CELLm].index_max = 1023; 21701 sop->memState[MMU_THDO_QCONFIG_QENTRYm].index_max = 1023; 21702 sop->memState[MMU_THDO_QCOUNT_CELL_0m].index_max = 1023; 21703 sop->memState[MMU_THDO_QOFFSET_CELLm].index_max = 1023; 21704 sop->memState[MMU_THDO_QOFFSET_QENTRYm].index_max = 1023; 21705 sop->memState[MMU_THDO_QRESET_VALUE_CELL_0m].index_max = 1023; 21706 sop->memState[MMU_THDO_QRESET_VALUE_QENTRY_0m].index_max = 1023; 21707 sop->memState[MMU_THDO_QSTATUS_CELL_0m].index_max = 1023; 21708 sop->memState[MMU_THDO_QSTATUS_QENTRY_0m].index_max = 1023; 21709 sop->memState[MMU_TOQ_STATE_MEM0m].index_max = 1023; 21710 sop->memState[MMU_TOQ_STATE_MEM1m].index_max = 1023; 21711 sop->memState[MMU_WRED_QUEUE_AVG_QSIZE_BUFFERm].index_max = 1023; 21712 sop->memState[MMU_WRED_QUEUE_AVG_QSIZE_QENTRYm].index_max = 1023; 21713 sop->memState[MMU_WRED_QUEUE_CONFIG_BUFFERm].index_max = 1023; 21714 sop->memState[MMU_WRED_QUEUE_CONFIG_QENTRYm].index_max = 1023; 21715 sop->memState[MMU_WRED_QUEUE_DROP_THD_DEQm].index_max = 1023; 21716 sop->memState[MMU_WRED_QUEUE_DROP_THD_ENQ_0m].index_max = 1023; 21717 sop->memState[MMU_WRED_QUEUE_OP_NODE_MAPm].index_max = 1023; 21718 sop->memState[THDO_QCOUNT_QENTRY_0m].index_max = 1023; 21719 if (dev_id == BCM56248_DEVICE_ID) { 21720 sop->memState[L2Xm].index_max = 32767; 21721 sop->memState[L2_ENTRY_ONLYm].index_max = 32767; 21722 sop->memState[L2_HITDA_ONLYm].index_max = 4095; 21723 sop->memState[L2_HITSA_ONLYm].index_max = 4095; 21724 } 21725 break; 21726 case BCM56457_DEVICE_ID: 21727 case BCM56458_DEVICE_ID: 21728 sop->memState[MMU_THDO_QCONFIG_CELLm].index_max = 1023; 21729 break; 21730 default: 21731 break; 21732 } 21733 /* L3_DEFIP sizing */ 21734 if (dev_id == BCM55455_DEVICE_ID || dev_id == BCM55450_DEVICE_ID) { 21735 SOC_CONTROL(unit)->l3_defip_max_tcams = 0; 21736 SOC_CONTROL(unit)->l3_defip_tcam_size = 0; 21737 sop->memState[L3_DEFIP_PAIR_128m].index_max = 0; 21738 sop->memState[L3_DEFIP_PAIR_128_ONLYm].index_max = 0; 21739 sop->memState[L3_DEFIP_PAIR_128_DATA_ONLYm].index_max = 0; 21740 sop->memState[L3_DEFIP_PAIR_128_HIT_ONLYm].index_max = 0; 21741 sop->memState[L3_DEFIPm].index_max = 0; 21742 sop->memState[L3_DEFIP_ONLYm].index_max = 0; 21743 sop->memState[L3_DEFIP_DATA_ONLYm].index_max = 0; 21744 sop->memState[L3_DEFIP_HIT_ONLYm].index_max = 0; 21745 SOC_CONTROL(unit)->l3_defip_index_remap = 0; 21746 } else { 21747 SOC_CONTROL(unit)->l3_defip_max_tcams = _SOC_KT2_DEFIP_MAX_TCAMS; 21748 SOC_CONTROL(unit)->l3_defip_tcam_size = _SOC_KT2_DEFIP_TCAM_DEPTH; 21749 21750 if (soc_property_get(unit, "l3_defip_sizing", TRUE)) { 21751 defip_config = soc_property_get(unit, spn_IPV6_LPM_128B_ENABLE, 1); 21752 21753 num_ipv6_128b_entries = 21754 soc_property_get(unit, spn_NUM_IPV6_LPM_128B_ENTRIES, 21755 (defip_config ? 1024 : 0)); 21756 21757 config_v6_entries = num_ipv6_128b_entries; 21758 21759 if (soc_property_get(unit, spn_LPM_SCALING_ENABLE, 0)) { 21760 num_ipv6_128b_entries = 0; 21761 if (!soc_property_get(unit, spn_LPM_IPV6_128B_RESERVED, 1)) { 21762 config_v6_entries = SOC_CONTROL(unit)->l3_defip_tcam_size * 21763 ((config_v6_entries / 21764 SOC_CONTROL(unit)->l3_defip_tcam_size) + 21765 ((config_v6_entries % 21766 SOC_CONTROL(unit)->l3_defip_tcam_size) ? 1 : 0)); 21767 } 21768 } 21769 21770 sop->memState[L3_DEFIP_PAIR_128m].index_max = 21771 num_ipv6_128b_entries - 1; 21772 sop->memState[L3_DEFIP_PAIR_128_ONLYm].index_max = 21773 num_ipv6_128b_entries - 1; 21774 sop->memState[L3_DEFIP_PAIR_128_DATA_ONLYm].index_max = 21775 num_ipv6_128b_entries - 1; 21776 sop->memState[L3_DEFIP_PAIR_128_HIT_ONLYm].index_max = 21777 num_ipv6_128b_entries - 1; 21778 sop->memState[L3_DEFIPm].index_max = 21779 (SOC_CONTROL(unit)->l3_defip_max_tcams * 21780 SOC_CONTROL(unit)->l3_defip_tcam_size) - 21781 (num_ipv6_128b_entries * 2) - 1; 21782 sop->memState[L3_DEFIP_ONLYm].index_max = 21783 sop->memState[L3_DEFIPm].index_max; 21784 sop->memState[L3_DEFIP_DATA_ONLYm].index_max = 21785 sop->memState[L3_DEFIPm].index_max; 21786 sop->memState[L3_DEFIP_HIT_ONLYm].index_max = 21787 sop->memState[L3_DEFIPm].index_max; 21788 SOC_CONTROL(unit)->l3_defip_index_remap = num_ipv6_128b_entries; 21789 21790 soc_l3_defip_indexes_init(unit, config_v6_entries); 21791 } 21792 } 21793 return rv; 21794 } 21795 21796 static const soc_reg_t pvtmon_result_reg[] = { 21797 TOP_PVTMON_RESULT_0r, TOP_PVTMON_RESULT_1r, 21798 TOP_PVTMON_RESULT_2r, TOP_PVTMON_RESULT_3r 21799 }; 21800 21801 int 21802 _soc_katana2_temperature_monitor_init(int unit) { 21803 uint32 rval; 21804 21805 SOC_IF_ERROR_RETURN(READ_TOP_PVTMON_CTRL_1r(unit, &rval)); 21806 soc_reg_field_set(unit, TOP_PVTMON_CTRL_1r, &rval, PVTMON_RSTBf, 1); 21807 SOC_IF_ERROR_RETURN(WRITE_TOP_PVTMON_CTRL_1r(unit, rval)); 21808 21809 SOC_IF_ERROR_RETURN(READ_TOP_PVTMON_CTRL_0r(unit, &rval)); 21810 soc_reg_field_set(unit, TOP_PVTMON_CTRL_0r, &rval, PROG_RESISTERf, 3); 21811 soc_reg_field_set(unit, TOP_PVTMON_CTRL_0r, &rval, BG_ADJf, 3); 21812 soc_reg_field_set(unit, TOP_PVTMON_CTRL_0r, &rval, MEASUREMENT_CALLIBRATIONf, 5); 21813 SOC_IF_ERROR_RETURN(WRITE_TOP_PVTMON_CTRL_0r(unit, rval)); 21814 21815 SOC_IF_ERROR_RETURN(READ_TOP_PVTMON_CTRL_1r(unit, &rval)); 21816 soc_reg_field_set(unit, TOP_PVTMON_CTRL_1r, &rval, PVTMON_SELECTf, 0); 21817 soc_reg_field_set(unit, TOP_PVTMON_CTRL_1r, &rval, PVTMON_RSTBf, 0); 21818 SOC_IF_ERROR_RETURN(WRITE_TOP_PVTMON_CTRL_1r(unit, rval)); 21819 21820 SOC_IF_ERROR_RETURN(READ_TOP_PVTMON_CTRL_1r(unit, &rval)); 21821 soc_reg_field_set(unit, TOP_PVTMON_CTRL_1r, &rval, PVTMON_RSTBf, 1); 21822 SOC_IF_ERROR_RETURN(WRITE_TOP_PVTMON_CTRL_1r(unit, rval)); 21823 21824 sal_usleep(1000); 21825 21826 return SOC_E_NONE; 21827 } 21828 21829 int 21830 soc_kt2_temperature_monitor_get(int unit, 21831 int temperature_max, 21832 soc_switch_temperature_monitor_t *temperature_array, 21833 int *temperature_count) 21834 { 21835 uint32 rval; 21836 soc_reg_t reg; 21837 int index; 21838 int fval, cur, peak; 21839 int num_entries_out; 21840 21841 *temperature_count = 0; 21842 if (COUNTOF(pvtmon_result_reg) > temperature_max) { 21843 num_entries_out = temperature_max; 21844 } else { 21845 num_entries_out = COUNTOF(pvtmon_result_reg); 21846 } 21847 /* Check to see if the thermal monitor is initialized */ 21848 SOC_IF_ERROR_RETURN(READ_TOP_PVTMON_CTRL_1r(unit, &rval)); 21849 if ((soc_reg_field_get(unit, TOP_PVTMON_CTRL_1r, rval, PVTMON_RSTBf) == 0) || 21850 (soc_reg_field_get(unit, TOP_PVTMON_CTRL_1r, rval, PVTMON_SELECTf) != 0)) { 21851 SOC_IF_ERROR_RETURN(_soc_katana2_temperature_monitor_init(unit)); 21852 } 21853 21854 for (index = 0; index < num_entries_out; index++) { 21855 reg = pvtmon_result_reg[index]; 21856 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, reg, REG_PORT_ANY, 0, &rval)); 21857 fval = soc_reg_field_get(unit, reg, rval, TEMP_DATAf); 21858 cur = (4180000 - (5556 * fval)) / 1000; 21859 fval = soc_reg_field_get(unit, reg, rval, PEAK_TEMP_DATAf); 21860 peak = (4180000 - (5556 * fval)) / 1000; 21861 (temperature_array + index)->curr = cur; 21862 (temperature_array + index)->peak = peak; 21863 } 21864 SOC_IF_ERROR_RETURN(READ_TOP_MISC_CONTROL_0r(unit, &rval)); 21865 soc_reg_field_set(unit, TOP_MISC_CONTROL_0r, &rval, 21866 THERMAL_PVTMON0_PEAK_DATA_RST_Lf, 1); 21867 soc_reg_field_set(unit, TOP_MISC_CONTROL_0r, &rval, 21868 THERMAL_PVTMON1_PEAK_DATA_RST_Lf, 1); 21869 soc_reg_field_set(unit, TOP_MISC_CONTROL_0r, &rval, 21870 THERMAL_PVTMON2_PEAK_DATA_RST_Lf, 1); 21871 soc_reg_field_set(unit, TOP_MISC_CONTROL_0r, &rval, 21872 THERMAL_PVTMON3_PEAK_DATA_RST_Lf, 1); 21873 SOC_IF_ERROR_RETURN(WRITE_TOP_MISC_CONTROL_0r(unit, rval)); 21874 soc_reg_field_set(unit, TOP_MISC_CONTROL_0r, &rval, 21875 THERMAL_PVTMON0_PEAK_DATA_RST_Lf, 0); 21876 soc_reg_field_set(unit, TOP_MISC_CONTROL_0r, &rval, 21877 THERMAL_PVTMON1_PEAK_DATA_RST_Lf, 0); 21878 soc_reg_field_set(unit, TOP_MISC_CONTROL_0r, &rval, 21879 THERMAL_PVTMON2_PEAK_DATA_RST_Lf, 0); 21880 soc_reg_field_set(unit, TOP_MISC_CONTROL_0r, &rval, 21881 THERMAL_PVTMON3_PEAK_DATA_RST_Lf, 0); 21882 SOC_IF_ERROR_RETURN(WRITE_TOP_MISC_CONTROL_0r(unit, rval)); 21883 *temperature_count=num_entries_out; 21884 21885 return SOC_E_NONE; 21886 } 21887 21888 int 21889 soc_kt2_show_ring_osc(int unit) 21890 { 21891 soc_reg_t ctrl_reg; 21892 uint32 rval, fval; 21893 int core_clk, quo, rem, frac; 21894 int ring_osc, ring_sel; 21895 int cmc = SOC_PCI_CMC(unit); 21896 21897 core_clk = SOC_INFO(unit).frequency * 1024; 21898 ctrl_reg = TOP_MISC_CONTROL_2r; 21899 21900 for (ring_osc = 2; ring_osc < 4; ring_osc++) { 21901 for (ring_sel = 0; ring_sel < 2; ring_sel++) { 21902 rval = 0; 21903 SOC_IF_ERROR_RETURN(READ_TOP_MISC_CONTROL_2r(unit, &rval)); 21904 soc_reg_field_set(unit, ctrl_reg, &rval, OSC_ENABLEf, 1); 21905 SOC_IF_ERROR_RETURN(WRITE_TOP_MISC_CONTROL_2r(unit, rval)); 21906 soc_reg_field_set(unit, ctrl_reg, &rval, IROSC_ENf, 1); 21907 SOC_IF_ERROR_RETURN(WRITE_TOP_MISC_CONTROL_2r(unit, rval)); 21908 21909 soc_reg_field_set(unit, ctrl_reg, &rval, IROSC_0_SELf, ring_sel); 21910 SOC_IF_ERROR_RETURN(WRITE_TOP_MISC_CONTROL_2r(unit, rval)); 21911 soc_reg_field_set(unit, ctrl_reg, &rval, IROSC_1_SELf, ring_sel); 21912 SOC_IF_ERROR_RETURN(WRITE_TOP_MISC_CONTROL_2r(unit, rval)); 21913 21914 soc_reg_field_set(unit, ctrl_reg, &rval, OSC_1_SELf, ring_osc); 21915 SOC_IF_ERROR_RETURN(WRITE_TOP_MISC_CONTROL_2r(unit, rval)); 21916 soc_reg_field_set(unit, ctrl_reg, &rval, OSC_0_SELf, 1); 21917 SOC_IF_ERROR_RETURN(WRITE_TOP_MISC_CONTROL_2r(unit, rval)); 21918 soc_reg_field_set(unit, ctrl_reg, &rval, OSC_0_SELf, 3); 21919 SOC_IF_ERROR_RETURN(WRITE_TOP_MISC_CONTROL_2r(unit, rval)); 21920 21921 sal_usleep(1000); 21922 21923 rval = soc_pci_read(unit, CMIC_CMCx_IRQ_STAT3_OFFSET(cmc)); 21924 /* SOC_IF_ERROR_RETURN(READ_CMIC_CMC0_IRQ_STAT3r(unit, &rval)); */ 21925 fval = rval & 0xffff; 21926 if (0 == fval) { 21927 quo = 0; 21928 frac = 0; 21929 } else { 21930 quo = core_clk / fval; 21931 rem = core_clk - quo * fval; 21932 frac = (rem * 10000) / fval; 21933 } 21934 LOG_CLI((BSL_META_U(unit, 21935 "%d: %d.%04d Mhz\n"), 21936 ring_osc, quo, frac)); 21937 } 21938 } 21939 return SOC_E_NONE; 21940 } 21941 21942 int 21943 soc_kt2_show_material_process(int unit) 21944 { 21945 soc_reg_t reg; 21946 int index; 21947 uint32 rval, fval, nmos[COUNTOF(pvtmon_result_reg)], n_avg, p_avg; 21948 21949 SOC_IF_ERROR_RETURN(READ_TOP_PVTMON_CTRL_0r(unit, &rval)); 21950 soc_reg_field_set(unit, TOP_PVTMON_CTRL_0r, &rval, FUNC_MODE_SELf, 0); 21951 SOC_IF_ERROR_RETURN(WRITE_TOP_PVTMON_CTRL_0r(unit, rval)); 21952 soc_reg_field_set(unit, TOP_PVTMON_CTRL_0r, &rval, MEASUREMENT_CALLIBRATIONf, 0x5); 21953 SOC_IF_ERROR_RETURN(WRITE_TOP_PVTMON_CTRL_0r(unit, rval)); 21954 soc_reg_field_set(unit, TOP_PVTMON_CTRL_0r, &rval, PROG_RESISTERf, 0x3); 21955 SOC_IF_ERROR_RETURN(WRITE_TOP_PVTMON_CTRL_0r(unit, rval)); 21956 21957 SOC_IF_ERROR_RETURN(READ_TOP_PVTMON_CTRL_1r(unit, &rval)); 21958 soc_reg_field_set(unit, TOP_PVTMON_CTRL_1r, &rval, PVTMON_RSTBf, 0); 21959 SOC_IF_ERROR_RETURN(WRITE_TOP_PVTMON_CTRL_1r(unit, rval)); 21960 soc_reg_field_set(unit, TOP_PVTMON_CTRL_1r, &rval, PVTMON_SELECTf, 0x1); 21961 SOC_IF_ERROR_RETURN(WRITE_TOP_PVTMON_CTRL_1r(unit, rval)); 21962 soc_reg_field_set(unit, TOP_PVTMON_CTRL_1r, &rval, PVTMON_RSTBf, 1); 21963 SOC_IF_ERROR_RETURN(WRITE_TOP_PVTMON_CTRL_1r(unit, rval)); 21964 21965 sal_usleep(1000); 21966 21967 /* Read NMOS information */ 21968 n_avg = 0; 21969 for (index = 0; index < COUNTOF(pvtmon_result_reg); index++) { 21970 reg = pvtmon_result_reg[index]; 21971 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, reg, REG_PORT_ANY, 0, &rval)); 21972 nmos[index] = soc_reg_field_get(unit, reg, rval, TEMP_DATAf); 21973 n_avg += nmos[index]; 21974 } 21975 21976 /* Read PMOS information and print both NMOS and PMOS value */ 21977 SOC_IF_ERROR_RETURN 21978 (soc_reg_field32_modify(unit, TOP_PVTMON_CTRL_0r, REG_PORT_ANY, 21979 MEASUREMENT_CALLIBRATIONf, 7)); 21980 21981 sal_usleep(1000); 21982 21983 p_avg = 0; 21984 for (index = 0; index < COUNTOF(pvtmon_result_reg); index++) { 21985 reg = pvtmon_result_reg[index]; 21986 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, reg, REG_PORT_ANY, 0, &rval)); 21987 fval = soc_reg_field_get(unit, reg, rval, TEMP_DATAf); 21988 p_avg += fval; 21989 21990 LOG_CLI((BSL_META_U(unit, 21991 "Material process location %d: NMOS = %3d PMOS = %3d\n"), 21992 index, nmos[index], fval)); 21993 } 21994 21995 LOG_CLI((BSL_META_U(unit, 21996 "Average: NMOS = %3d PMOS = %3d\n"), 21997 n_avg / COUNTOF(pvtmon_result_reg), 21998 p_avg / COUNTOF(pvtmon_result_reg))); 21999 22000 return SOC_E_NONE; 22001 } 22002 22003 int 22004 soc_kt2_show_voltage(int unit) 22005 { 22006 soc_reg_t reg; 22007 int index; 22008 uint32 rval, fval, avg; 22009 22010 SOC_IF_ERROR_RETURN(READ_TOP_PVTMON_CTRL_0r(unit, &rval)); 22011 soc_reg_field_set(unit, TOP_PVTMON_CTRL_0r, &rval, FUNC_MODE_SELf, 0); 22012 SOC_IF_ERROR_RETURN(WRITE_TOP_PVTMON_CTRL_0r(unit, rval)); 22013 soc_reg_field_set(unit, TOP_PVTMON_CTRL_0r, &rval, MEASUREMENT_CALLIBRATIONf, 0x5); 22014 SOC_IF_ERROR_RETURN(WRITE_TOP_PVTMON_CTRL_0r(unit, rval)); 22015 soc_reg_field_set(unit, TOP_PVTMON_CTRL_0r, &rval, PROG_RESISTERf, 0x3); 22016 SOC_IF_ERROR_RETURN(WRITE_TOP_PVTMON_CTRL_0r(unit, rval)); 22017 22018 SOC_IF_ERROR_RETURN(READ_TOP_PVTMON_CTRL_1r(unit, &rval)); 22019 soc_reg_field_set(unit, TOP_PVTMON_CTRL_1r, &rval, PVTMON_RSTBf, 0); 22020 SOC_IF_ERROR_RETURN(WRITE_TOP_PVTMON_CTRL_1r(unit, rval)); 22021 soc_reg_field_set(unit, TOP_PVTMON_CTRL_1r, &rval, PVTMON_SELECTf, 0x3); 22022 SOC_IF_ERROR_RETURN(WRITE_TOP_PVTMON_CTRL_1r(unit, rval)); 22023 soc_reg_field_set(unit, TOP_PVTMON_CTRL_1r, &rval, PVTMON_RSTBf, 1); 22024 SOC_IF_ERROR_RETURN(WRITE_TOP_PVTMON_CTRL_1r(unit, rval)); 22025 22026 sal_usleep(1000); 22027 avg = 0; 22028 /* Read Voltages */ 22029 for (index = 0; index < COUNTOF(pvtmon_result_reg); index++) { 22030 reg = pvtmon_result_reg[index]; 22031 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, reg, REG_PORT_ANY, 0, &rval)); 22032 fval = soc_reg_field_get(unit, reg, rval, TEMP_DATAf); 22033 /* (0.99/1024) * 8/7 * TEMP_DATA */ 22034 fval = (fval * 8 * 990) / (1024 * 7); 22035 avg += fval; 22036 LOG_CLI((BSL_META_U(unit, 22037 "Voltage @ location %d: = %d.%03dV\n"), 22038 index, (fval/1000), (fval %1000))); 22039 } 22040 avg /= COUNTOF(pvtmon_result_reg); 22041 LOG_CLI((BSL_META_U(unit, 22042 "Average: = %d.%03dV\n"), 22043 (avg/1000), (avg %1000))); 22044 22045 return SOC_E_NONE; 22046 } 22047 #ifdef BCM_WARM_BOOT_SUPPORT 22048 static 22049 void _soc_kt2_mem_config_set(int unit, char *config_str, char *config_value) 22050 { 22051 /* Calling Wrapper function. */ 22052 /* Can update config.bcm or suggest config variable settings on terminal */ 22053 soc_mem_config_save(unit, config_str, config_value); 22054 } 22055 #endif 22056 int _soc_katana2_get_cfg_num(int unit, int *new_cfg_num) 22057 { 22058 int cfg_num=-1; 22059 int max_cfg_num=0; 22060 int def_cfg_num=0; 22061 int offset_cfg_num=0; 22062 uint16 dev_id=0; 22063 uint8 rev_id=0; 22064 22065 #ifdef BCM_WARM_BOOT_SUPPORT 22066 if (SOC_WARM_BOOT(unit)) { 22067 cfg_num = COUNTOF(bcm56450_tdm_info) - 1; 22068 if (kt2_scache_tdm_info[unit].tdm_size != 0) { 22069 *new_cfg_num = cfg_num; 22070 return SOC_E_NONE; 22071 } 22072 /* FAll through */ 22073 } 22074 #endif 22075 22076 cfg_num = soc_property_get(unit, spn_BCM5645X_CONFIG,0xFF); 22077 22078 soc_cm_get_id(unit, &dev_id, &rev_id); 22079 switch(dev_id) { 22080 case BCM55450_DEVICE_ID: 22081 case BCM55455_DEVICE_ID: 22082 case BCM56248_DEVICE_ID: 22083 if ((SAL_BOOT_BCMSIM || SAL_BOOT_PLISIM)) { 22084 def_cfg_num = 0; 22085 } else { 22086 def_cfg_num = BCM56248_DEVICE_ID_DEFAULT_CFG; 22087 } 22088 offset_cfg_num = BCM56248_DEVICE_ID_OFFSET_CFG; 22089 max_cfg_num = BCM56248_DEVICE_ID_MAX_CFG; 22090 break; 22091 case BCM56450_DEVICE_ID: 22092 case BCM56456_DEVICE_ID: 22093 if ((SAL_BOOT_BCMSIM || SAL_BOOT_PLISIM)) { 22094 def_cfg_num = 0; 22095 } else { 22096 def_cfg_num = BCM56450_DEVICE_ID_DEFAULT_CFG; 22097 } 22098 offset_cfg_num = BCM56450_DEVICE_ID_OFFSET_CFG; 22099 max_cfg_num = BCM56450_DEVICE_ID_MAX_CFG; 22100 break; 22101 case BCM56452_DEVICE_ID: 22102 case BCM56457_DEVICE_ID: 22103 def_cfg_num = BCM56452_DEVICE_ID_DEFAULT_CFG; 22104 offset_cfg_num = BCM56452_DEVICE_ID_OFFSET_CFG; 22105 max_cfg_num = BCM56452_DEVICE_ID_MAX_CFG; 22106 break; 22107 case BCM56454_DEVICE_ID: 22108 case BCM56458_DEVICE_ID: 22109 def_cfg_num = BCM56454_DEVICE_ID_DEFAULT_CFG; 22110 offset_cfg_num = BCM56454_DEVICE_ID_OFFSET_CFG; 22111 max_cfg_num = BCM56454_DEVICE_ID_MAX_CFG; 22112 break; 22113 case BCM56455_DEVICE_ID: 22114 def_cfg_num = BCM56455_DEVICE_ID_DEFAULT_CFG; 22115 offset_cfg_num = BCM56455_DEVICE_ID_OFFSET_CFG; 22116 max_cfg_num = BCM56455_DEVICE_ID_MAX_CFG; 22117 break; 22118 } 22119 if (cfg_num == 0xFF) { 22120 *new_cfg_num = def_cfg_num; 22121 } else { 22122 if (cfg_num == 0) { 22123 if (offset_cfg_num != 0) { 22124 LOG_CLI((BSL_META_U(unit, 22125 "Config=0 is not allowed \n"))); 22126 return BCM_E_PARAM; 22127 } 22128 } 22129 *new_cfg_num = cfg_num + offset_cfg_num; 22130 } 22131 if (*new_cfg_num > max_cfg_num) { 22132 LOG_CLI((BSL_META_U(unit, 22133 "Cfg_num:%d Internal cfg_num:%d \n"),cfg_num,*new_cfg_num)); 22134 LOG_CLI((BSL_META_U(unit, 22135 "Wrong %s ==> cfg_num:%d DEFAULT:%d START:%d MAX:%d \n"), 22136 spn_BCM5645X_CONFIG, cfg_num, 22137 def_cfg_num-offset_cfg_num,1,max_cfg_num-offset_cfg_num)); 22138 return BCM_E_PARAM; 22139 } 22140 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 22141 "Info Cfg_num:%d Internal cfg_num:%d \n"),cfg_num,*new_cfg_num)); 22142 return BCM_E_NONE; 22143 } 22144 22145 int _soc_kt2_config_get(int unit, 22146 soc_kt2_sku_config_info_t *conf) 22147 { 22148 uint16 dev_id=0; 22149 uint8 rev_id=0; 22150 int cfg_num=0; 22151 soc_field_t wc_xfi_mode_sel_fld[]={WC0_8_XFI_MODE_SELf,WC1_8_XFI_MODE_SELf}; 22152 uint32 top_misc_control_1_val = 0; 22153 22154 soc_cm_get_id(unit, &dev_id, &rev_id); 22155 if (_soc_katana2_get_cfg_num(unit, &cfg_num) != BCM_E_NONE) { 22156 return SOC_E_FAIL; 22157 } 22158 conf->config = cfg_num; 22159 conf->bcm56450_cfg_offset = BCM56450_DEVICE_ID_OFFSET_CFG; 22160 conf->bcm56452_cfg_offset = BCM56452_DEVICE_ID_OFFSET_CFG; 22161 conf->bcm56454_cfg_offset = BCM56454_DEVICE_ID_OFFSET_CFG; 22162 conf->bcm56455_cfg_offset = BCM56455_DEVICE_ID_OFFSET_CFG; 22163 conf->bcm56248_cfg_offset = BCM56248_DEVICE_ID_OFFSET_CFG; 22164 conf->xfi_0 = soc_reg_field_get(unit, TOP_MISC_CONTROL_1r, 22165 top_misc_control_1_val, 22166 wc_xfi_mode_sel_fld[0]); 22167 conf->xfi_1 = soc_reg_field_get(unit, TOP_MISC_CONTROL_1r, 22168 top_misc_control_1_val, 22169 wc_xfi_mode_sel_fld[1]); 22170 conf->olp_port = SOC_INFO(unit).olp_port[0]; 22171 return SOC_E_NONE; 22172 } 22173 22174 void 22175 _soc_kt2_mem_config(int unit) 22176 { 22177 /* #ifdef BROADCOM_SVK */ 22178 /* For first 4(UC0-UC3) mxqblock , tx polarity is changed */ 22179 /* For next 4(UC4-UC7) mxqblock , rx polarity is changed */ 22180 uint16 dev_id=0; 22181 uint8 rev_id=0; 22182 int cfg_num=0; 22183 22184 soc_cm_get_id(unit, &dev_id, &rev_id); 22185 if (_soc_katana2_get_cfg_num(unit, &cfg_num) != BCM_E_NONE) { 22186 return ; 22187 } 22188 22189 LOG_CLI((BSL_META_U(unit, 22190 "\n=================================================\n"))); 22191 LOG_CLI((BSL_META_U(unit, 22192 "INFO:XAUI need all 4 lanes;R-XAUI need 2 & XFI need 1 lane\n"))); 22193 LOG_CLI((BSL_META_U(unit, 22194 "Cfg:%d IntCfg:%d Recommended PortGroup Config Setting for WC ports\n"), 22195 soc_property_get(unit, spn_BCM5645X_CONFIG,0xFF), cfg_num)); 22196 LOG_CLI((BSL_META_U(unit, 22197 "=================================================\n"))); 22198 switch(cfg_num) { 22199 case BCM56248_DEVICE_ID_OFFSET_CFG + 0: 22200 case BCM56450_DEVICE_ID_OFFSET_CFG + 0: 22201 LOG_CLI((BSL_META_U(unit, 22202 "portgroup_27.%d=1 \n"), unit)); 22203 LOG_CLI((BSL_META_U(unit, 22204 "portgroup_28.%d=1 \n"), unit)); 22205 LOG_CLI((BSL_META_U(unit, 22206 "portgroup_29.%d=1 \n"), unit)); 22207 LOG_CLI((BSL_META_U(unit, 22208 "portgroup_30.%d=1 \n"), unit)); 22209 LOG_CLI((BSL_META_U(unit, 22210 "portgroup_31.%d=1 \n"), unit)); 22211 LOG_CLI((BSL_META_U(unit, 22212 "portgroup_32.%d=1 \n"), unit)); 22213 LOG_CLI((BSL_META_U(unit, 22214 "portgroup_33.%d=1 \n"), unit)); 22215 LOG_CLI((BSL_META_U(unit, 22216 "portgroup_34.%d=1 \n"), unit)); 22217 break; 22218 case BCM56248_DEVICE_ID_OFFSET_CFG + 1: 22219 case BCM56248_DEVICE_ID_OFFSET_CFG + 2: 22220 case BCM56450_DEVICE_ID_OFFSET_CFG + 1: 22221 case BCM56450_DEVICE_ID_OFFSET_CFG + 2: 22222 LOG_CLI((BSL_META_U(unit, 22223 "portgroup_27.%d=1 \n"), unit)); 22224 LOG_CLI((BSL_META_U(unit, 22225 "portgroup_28.%d=1 \n"), unit)); 22226 break; 22227 case BCM56248_DEVICE_ID_OFFSET_CFG + 3: 22228 case BCM56450_DEVICE_ID_OFFSET_CFG + 3: 22229 LOG_CLI((BSL_META_U(unit, 22230 "portgroup_27.%d=1 \n"), unit)); 22231 LOG_CLI((BSL_META_U(unit, 22232 "portgroup_28.%d=1 \n"), unit)); 22233 LOG_CLI((BSL_META_U(unit, 22234 "portgroup_30.%d=1 \n"), unit)); 22235 break; 22236 case BCM56248_DEVICE_ID_OFFSET_CFG + 4: 22237 case BCM56450_DEVICE_ID_OFFSET_CFG + 4: 22238 LOG_CLI((BSL_META_U(unit, 22239 "portgroup_27.%d=1 \n"), unit)); 22240 LOG_CLI((BSL_META_U(unit, 22241 "portgroup_33.%d=1 \n"), unit)); 22242 LOG_CLI((BSL_META_U(unit, 22243 "portgroup_28.%d=1 \n"), unit)); 22244 LOG_CLI((BSL_META_U(unit, 22245 "portgroup_30.%d=1 \n"), unit)); 22246 break; 22247 case BCM56248_DEVICE_ID_OFFSET_CFG + 5: 22248 case BCM56450_DEVICE_ID_OFFSET_CFG + 5: 22249 LOG_CLI((BSL_META_U(unit, 22250 "portgroup_27.%d=1 \n"), unit)); 22251 LOG_CLI((BSL_META_U(unit, 22252 "portgroup_33.%d=1 \n"), unit)); 22253 LOG_CLI((BSL_META_U(unit, 22254 "portgroup_25.%d=1 \n"), unit)); 22255 LOG_CLI((BSL_META_U(unit, 22256 "portgroup_36.%d=1 \n"), unit)); 22257 22258 LOG_CLI((BSL_META_U(unit, 22259 "portgroup_28.%d=1 \n"), unit)); 22260 LOG_CLI((BSL_META_U(unit, 22261 "portgroup_30.%d=1 \n"), unit)); 22262 break; 22263 case BCM56248_DEVICE_ID_OFFSET_CFG + 7: 22264 case BCM56450_DEVICE_ID_OFFSET_CFG + 7: 22265 LOG_CLI((BSL_META_U(unit, 22266 "portgroup_27.%d=1 \n"), unit)); 22267 LOG_CLI((BSL_META_U(unit, 22268 "portgroup_33.%d=1 \n"), unit)); 22269 22270 LOG_CLI((BSL_META_U(unit, 22271 "portgroup_28.%d=1 \n"), unit)); 22272 LOG_CLI((BSL_META_U(unit, 22273 "portgroup_30.%d=1 \n"), unit)); 22274 LOG_CLI((BSL_META_U(unit, 22275 "portgroup_26.%d=1 \n"), unit)); 22276 LOG_CLI((BSL_META_U(unit, 22277 "portgroup_39.%d=1 \n"), unit)); 22278 break; 22279 case BCM56248_DEVICE_ID_OFFSET_CFG + 6: 22280 case BCM56450_DEVICE_ID_OFFSET_CFG + 6: 22281 LOG_CLI((BSL_META_U(unit, 22282 "portgroup_27.%d=1 \n"), unit)); 22283 LOG_CLI((BSL_META_U(unit, 22284 "portgroup_33.%d=1 \n"), unit)); 22285 LOG_CLI((BSL_META_U(unit, 22286 "portgroup_25.%d=1 \n"), unit)); 22287 LOG_CLI((BSL_META_U(unit, 22288 "portgroup_36.%d=1 \n"), unit)); 22289 22290 LOG_CLI((BSL_META_U(unit, 22291 "portgroup_28.%d=1 \n"), unit)); 22292 LOG_CLI((BSL_META_U(unit, 22293 "portgroup_30.%d=1 \n"), unit)); 22294 LOG_CLI((BSL_META_U(unit, 22295 "portgroup_26.%d=1 \n"), unit)); 22296 LOG_CLI((BSL_META_U(unit, 22297 "portgroup_39.%d=1 \n"), unit)); 22298 break; 22299 case BCM56248_DEVICE_ID_OFFSET_CFG + 8: 22300 case BCM56450_DEVICE_ID_OFFSET_CFG + 8: 22301 case BCM56248_DEVICE_ID_OFFSET_CFG + 9: 22302 case BCM56450_DEVICE_ID_OFFSET_CFG + 9: 22303 case BCM56248_DEVICE_ID_OFFSET_CFG + 10: 22304 case BCM56450_DEVICE_ID_OFFSET_CFG + 10: 22305 case BCM56248_DEVICE_ID_OFFSET_CFG + 11: 22306 case BCM56450_DEVICE_ID_OFFSET_CFG + 11: 22307 case BCM56248_DEVICE_ID_OFFSET_CFG + 12: 22308 case BCM56450_DEVICE_ID_OFFSET_CFG + 12: 22309 case BCM56248_DEVICE_ID_OFFSET_CFG + 13: 22310 case BCM56450_DEVICE_ID_OFFSET_CFG + 13: 22311 case BCM56248_DEVICE_ID_OFFSET_CFG + 14: 22312 case BCM56450_DEVICE_ID_OFFSET_CFG + 14: 22313 case BCM56248_DEVICE_ID_OFFSET_CFG + 15: 22314 case BCM56450_DEVICE_ID_OFFSET_CFG + 15: 22315 LOG_CLI((BSL_META_U(unit, 22316 "portgroup_27.%d=4 \n"), unit)); 22317 LOG_CLI((BSL_META_U(unit, 22318 "portgroup_28.%d=4 \n"), unit)); 22319 break; 22320 case BCM56248_DEVICE_ID_OFFSET_CFG + 16: 22321 LOG_CLI((BSL_META_U(unit, 22322 "portgroup_27.%d=4 \n"), unit)); 22323 LOG_CLI((BSL_META_U(unit, 22324 "portgroup_28.%d=4 \n"), unit)); 22325 break; 22326 case BCM56450_DEVICE_ID_OFFSET_CFG + 16: 22327 LOG_CLI((BSL_META_U(unit, 22328 "portgroup_27.%d=1 \n"), unit)); 22329 LOG_CLI((BSL_META_U(unit, 22330 "portgroup_28.%d=4 \n"), unit)); 22331 break; 22332 case BCM56248_DEVICE_ID_OFFSET_CFG + 17: 22333 LOG_CLI((BSL_META_U(unit, 22334 "portgroup_27.%d=1 \n"), unit)); 22335 LOG_CLI((BSL_META_U(unit, 22336 "portgroup_28.%d=1 \n"), unit)); 22337 LOG_CLI((BSL_META_U(unit, 22338 "portgroup_30.%d=1 \n"), unit)); 22339 break; 22340 case BCM56452_DEVICE_ID_OFFSET_CFG + 1: 22341 case BCM56452_DEVICE_ID_OFFSET_CFG + 2: 22342 case BCM56452_DEVICE_ID_OFFSET_CFG + 3: 22343 case BCM56452_DEVICE_ID_OFFSET_CFG + 4: 22344 LOG_CLI((BSL_META_U(unit, 22345 "portgroup_25.%d=4 \n"), unit)); 22346 LOG_CLI((BSL_META_U(unit, 22347 "portgroup_26.%d=4 \n"), unit)); 22348 LOG_CLI((BSL_META_U(unit, 22349 "portgroup_27.%d=4 \n"), unit)); 22350 LOG_CLI((BSL_META_U(unit, 22351 "portgroup_28.%d=4 \n"), unit)); 22352 break; 22353 case BCM56452_DEVICE_ID_OFFSET_CFG + 5: 22354 LOG_CLI((BSL_META_U(unit, 22355 "portgroup_25.%d=4 \n"), unit)); 22356 LOG_CLI((BSL_META_U(unit, 22357 "portgroup_27.%d=4 \n"), unit)); 22358 LOG_CLI((BSL_META_U(unit, 22359 "portgroup_28.%d=4 \n"), unit)); 22360 break; 22361 case BCM56452_DEVICE_ID_OFFSET_CFG + 6: 22362 LOG_CLI((BSL_META_U(unit, 22363 "portgroup_27.%d=4 \n"), unit)); 22364 LOG_CLI((BSL_META_U(unit, 22365 "portgroup_28.%d=4 \n"), unit)); 22366 break; 22367 case BCM56452_DEVICE_ID_OFFSET_CFG + 7: 22368 LOG_CLI((BSL_META_U(unit, 22369 "portgroup_28.%d=4 \n"), unit)); 22370 LOG_CLI((BSL_META_U(unit, 22371 "portgroup_28.%d=4 \n"), unit)); 22372 break; 22373 case BCM56452_DEVICE_ID_OFFSET_CFG + 8: 22374 LOG_CLI((BSL_META_U(unit, 22375 "portgroup_25.%d=4 \n"), unit)); 22376 LOG_CLI((BSL_META_U(unit, 22377 "portgroup_26.%d=4 \n"), unit)); 22378 LOG_CLI((BSL_META_U(unit, 22379 "portgroup_27.%d=4 \n"), unit)); 22380 LOG_CLI((BSL_META_U(unit, 22381 "portgroup_28.%d=4 \n"), unit)); 22382 break; 22383 case BCM56452_DEVICE_ID_OFFSET_CFG + 9: 22384 LOG_CLI((BSL_META_U(unit, 22385 "portgroup_27.%d=4 \n"), unit)); 22386 LOG_CLI((BSL_META_U(unit, 22387 "portgroup_28.%d=4 \n"), unit)); 22388 break; 22389 case BCM56452_DEVICE_ID_OFFSET_CFG + 10: 22390 LOG_CLI((BSL_META_U(unit, 22391 "portgroup_28.%d=4 \n"), unit)); 22392 LOG_CLI((BSL_META_U(unit, 22393 "portgroup_30.%d=1 \n"), unit)); 22394 break; 22395 case BCM56454_DEVICE_ID_OFFSET_CFG + 1: 22396 LOG_CLI((BSL_META_U(unit, 22397 "portgroup_27.%d=4 \n"), unit)); 22398 LOG_CLI((BSL_META_U(unit, 22399 "portgroup_28.%d=4 \n"), unit)); 22400 break; 22401 case BCM56454_DEVICE_ID_OFFSET_CFG + 2: 22402 LOG_CLI((BSL_META_U(unit, 22403 "portgroup_25.%d=4 \n"), unit)); 22404 LOG_CLI((BSL_META_U(unit, 22405 "portgroup_26.%d=4 \n"), unit)); 22406 break; 22407 default : break; 22408 } 22409 LOG_CLI((BSL_META_U(unit, 22410 "=================================================\n"))); 22411 22412 return; 22413 } 22414 22415 /* Map logical (always starts from 0 and contiguous) index to physical index 22416 which can have a starting offset and/or holes. 22417 Input : logical index 22418 Returns: physical index */ 22419 int 22420 soc_kt2_l3_defip_index_map(int unit, soc_mem_t mem, int index) 22421 { 22422 int wide = 0; 22423 22424 if (SOC_CONTROL(unit)->l3_defip_index_remap == 0) { 22425 return index; 22426 } 22427 22428 if (mem == L3_DEFIP_PAIR_128m || 22429 mem == L3_DEFIP_PAIR_128_ONLYm || 22430 mem == L3_DEFIP_PAIR_128_DATA_ONLYm || 22431 mem == L3_DEFIP_PAIR_128_HIT_ONLYm) { 22432 wide = 1; 22433 } 22434 22435 return soc_l3_defip_index_map(unit, wide, index); 22436 } 22437 22438 /* Reverse map physical index to logical index. 22439 Input : physical index 22440 Returns: logical index */ 22441 int 22442 soc_kt2_l3_defip_index_remap(int unit, soc_mem_t mem, int index) 22443 { 22444 int wide = 0; 22445 22446 if (SOC_CONTROL(unit)->l3_defip_index_remap == 0) { 22447 return index; 22448 } 22449 22450 if (mem == L3_DEFIP_PAIR_128m || 22451 mem == L3_DEFIP_PAIR_128_ONLYm || 22452 mem == L3_DEFIP_PAIR_128_DATA_ONLYm || 22453 mem == L3_DEFIP_PAIR_128_HIT_ONLYm) { 22454 wide = 1; 22455 } 22456 22457 return soc_l3_defip_index_remap(unit, wide, index); 22458 } 22459 22460 /* Given a physical index (always in terms of the narrow entry) 22461 return the logical index and memory type */ 22462 int 22463 soc_kt2_l3_defip_mem_index_get(int unit, int pindex, soc_mem_t *mem) 22464 { 22465 return soc_l3_defip_index_mem_map(unit, pindex, mem); 22466 } 22467 22468 #ifdef BCM_WARM_BOOT_SUPPORT 22469 22470 /* 22471 * Function: 22472 * _soc_katana2_default_tdm_recover 22473 * Description: 22474 * This function is called during warmboot to recover the 22475 * default tdm settings for the config being used if an 22476 * upgrade is detected and tdm settings changed. 22477 * Parameters: 22478 * unit - PCI device unit number (driver internal) 22479 * tdm - (OUT)tdm settings for the config id used. 22480 * Returns: 22481 * SOC_E_NONE - Success. 22482 * SOC_E_FAIL - Failure 22483 */ 22484 22485 int _soc_katana2_default_tdm_recover(int unit, uint32 *tdm) 22486 { 22487 uint32 port = 0; 22488 uint32 outer_index=0; 22489 uint32 inner_index=0; 22490 uint32 tdm_index=0; 22491 uint32 row=18; 22492 uint32 col=5; 22493 uint8 mxqblock=0; 22494 int tdm_size, tdm_freq, cfg_num; 22495 uint16 dev_id; 22496 uint8 rev_id; 22497 22498 soc_cm_get_id(unit, &dev_id, &rev_id); 22499 22500 /* Get the value of "bcm5645x_config" from the config file */ 22501 cfg_num = soc_property_get(unit, spn_BCM5645X_CONFIG,0xFF); 22502 22503 if (cfg_num >= (sizeof(bcm56450_tdm)/sizeof(bcm56450_tdm[0]))) { 22504 LOG_CLI((BSL_META_U(unit, 22505 "Wrong cfg_num:%d exceeding max cfg_num: %d\n"), 22506 cfg_num, 22507 (int)(sizeof(bcm56450_tdm)/sizeof(bcm56450_tdm[0])))); 22508 return SOC_E_FAIL; 22509 } 22510 22511 switch(dev_id) { 22512 case BCM55450_DEVICE_ID: 22513 case BCM55455_DEVICE_ID: 22514 case BCM56248_DEVICE_ID: 22515 case BCM56450_DEVICE_ID: 22516 case BCM56452_DEVICE_ID: 22517 case BCM56454_DEVICE_ID: 22518 case BCM56455_DEVICE_ID: 22519 case BCM56456_DEVICE_ID: 22520 case BCM56457_DEVICE_ID: 22521 case BCM56458_DEVICE_ID: 22522 tdm_size= bcm56450_tdm_info[cfg_num].tdm_size; 22523 tdm_freq= bcm56450_tdm_info[cfg_num].tdm_freq; 22524 row= bcm56450_tdm_info[cfg_num].row; 22525 col= bcm56450_tdm_info[cfg_num].col; 22526 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 22527 "Recover default TDM for " 22528 "Cfg=%d freq=%d size=%d raw=%d col=%d\n"), 22529 cfg_num, tdm_freq, tdm_size, row,col)); 22530 22531 switch(cfg_num) { 22532 case BCM56248_DEVICE_ID_OFFSET_CFG + 0: 22533 case BCM56450_DEVICE_ID_OFFSET_CFG + 0: 22534 LOG_CLI((BSL_META_U(unit, 22535 "kt2_tdm_56450speed_deprecated0\n"))); 22536 sal_memcpy(tdm, 22537 &kt2_tdm_56450AA_ref[0], 22538 sizeof(kt2_tdm_56450AA_ref)); 22539 break; 22540 22541 case BCM56248_DEVICE_ID_OFFSET_CFG + 1: 22542 case BCM56450_DEVICE_ID_OFFSET_CFG + 1:/* kt2_tdm_A_56450_1 */ 22543 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 22544 "kt2_tdm_A_56450_1 \n"))); 22545 sal_memcpy(tdm, 22546 &kt2_tdm_56450A_ref[0], 22547 sizeof(kt2_tdm_56450A_ref)); 22548 kt2_tdm_replace(tdm, 88, KT2_OLP_PORT, KT2_IDLE, 0); 22549 kt2_tdm_replace(tdm, tdm_size, 33, 25, 0); 22550 kt2_tdm_replace(tdm, tdm_size, 30, 26, 0); 22551 break; 22552 22553 case BCM56248_DEVICE_ID_OFFSET_CFG + 2: 22554 case BCM56450_DEVICE_ID_OFFSET_CFG + 2:/* kt2_tdm_A_56450_2 */ 22555 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 22556 "kt2_tdm_A_56450_2 \n"))); 22557 sal_memcpy(tdm, 22558 &kt2_tdm_56450A_ref[0], 22559 sizeof(kt2_tdm_56450A_ref)); 22560 kt2_tdm_replace(tdm, 88, 33, 25, 0); 22561 kt2_tdm_replace(tdm, 88, 30, 26, 0); 22562 break; 22563 22564 case BCM56248_DEVICE_ID_OFFSET_CFG + 3: 22565 case BCM56450_DEVICE_ID_OFFSET_CFG + 3:/* kt2_tdm_A_56450_3 */ 22566 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 22567 "kt2_tdm_A_56450_3 \n"))); 22568 sal_memcpy(tdm, 22569 &kt2_tdm_56450A_ref[0], 22570 sizeof(kt2_tdm_56450A_ref)); 22571 kt2_tdm_replace(tdm, 88, 33, 25, 0); 22572 break; 22573 22574 case BCM56248_DEVICE_ID_OFFSET_CFG + 4: 22575 case BCM56450_DEVICE_ID_OFFSET_CFG + 4:/* kt2_tdm_A_56450_4 */ 22576 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 22577 "kt2_tdm_A_56450_4 \n"))); 22578 sal_memcpy(tdm, 22579 &kt2_tdm_56450A_ref[0], 22580 sizeof(kt2_tdm_56450A_ref)); 22581 break; 22582 22583 case BCM56248_DEVICE_ID_OFFSET_CFG + 5: 22584 case BCM56450_DEVICE_ID_OFFSET_CFG + 5:/* kt2_tdm_A_56450_5 */ 22585 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 22586 "kt2_tdm_A_56450_5 \n"))); 22587 sal_memcpy(tdm, 22588 &kt2_tdm_56450A_ref[0], 22589 sizeof(kt2_tdm_56450A_ref)); 22590 kt2_tdm_display(unit, tdm, tdm_size, row, col); 22591 kt2_tdm_swap(tdm, 88, 21, 33); 22592 kt2_tdm_display(unit,tdm, tdm_size, row, col); 22593 kt2_tdm_swap(tdm, 88, 30, 13); 22594 kt2_tdm_display(unit, tdm, tdm_size, row, col); 22595 kt2_tdm_replace(tdm, 88, 13, 25, 0); 22596 kt2_tdm_display(unit, tdm, tdm_size, row, col); 22597 kt2_tdm_replace(tdm, 88, 21, 36, 0); 22598 kt2_tdm_display(unit, tdm, tdm_size, row, col); 22599 kt2_tdm_replace(tdm, 88, 17, 13, 0); 22600 kt2_tdm_display(unit, tdm, tdm_size, row, col); 22601 break; 22602 22603 case BCM56248_DEVICE_ID_OFFSET_CFG + 6: 22604 case BCM56450_DEVICE_ID_OFFSET_CFG + 6:/* kt2_tdm_A_56450_6 */ 22605 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 22606 "kt2_tdm_A_56450_6 \n"))); 22607 sal_memcpy(tdm, 22608 &kt2_tdm_56450A_ref[0], 22609 sizeof(kt2_tdm_56450A_ref)); 22610 kt2_tdm_swap(tdm, 88, 1, 17); 22611 kt2_tdm_swap(tdm, 88, 13, 21); 22612 kt2_tdm_replace(tdm, 88, 17, 39, 0); 22613 kt2_tdm_replace(tdm, 88, 21, 26, 0); 22614 kt2_tdm_replace(tdm, 88, 9, 25, 0); 22615 kt2_tdm_replace(tdm, 88, 13, 36, 0); 22616 kt2_tdm_replace(tdm, 88, 40, KT2_IDLE, 0); 22617 break; 22618 22619 case BCM56248_DEVICE_ID_OFFSET_CFG + 7: 22620 case BCM56450_DEVICE_ID_OFFSET_CFG + 7:/* kt2_tdm_A_56450_7 */ 22621 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 22622 "kt2_tdm_A_56450_7 \n"))); 22623 sal_memcpy(tdm, 22624 &kt2_tdm_56450A_ref[0], 22625 sizeof(kt2_tdm_56450A_ref)); 22626 kt2_tdm_swap(tdm, 88, 9, 17); 22627 kt2_tdm_replace(tdm, 88, 17, 26, 0); 22628 kt2_tdm_replace(tdm, 88, 21, 39, 0); 22629 kt2_tdm_replace(tdm, 88, 13, 25, 0); 22630 22631 kt2_tdm_replace(tdm, 88, 13, KT2_IDLE, 0); 22632 kt2_tdm_replace(tdm, 88, 1, KT2_IDLE, 0); 22633 kt2_tdm_replace(tdm, 88, 5, KT2_IDLE, 0); 22634 kt2_tdm_replace(tdm, 88, 9, KT2_IDLE, 0); 22635 kt2_tdm_replace(tdm, 88, 40, KT2_IDLE, 0); 22636 tdm_index = 0; 22637 for (outer_index = 1; outer_index <= 4; outer_index++) { 22638 for (inner_index= 0; inner_index < 6; 22639 inner_index++) { 22640 port = outer_index + inner_index*4; 22641 while(tdm[tdm_index] != KT2_IDLE) { 22642 tdm_index++; 22643 } 22644 tdm[tdm_index]=port; 22645 } 22646 } 22647 break; 22648 22649 case BCM56248_DEVICE_ID_OFFSET_CFG + 8: 22650 case BCM56450_DEVICE_ID_OFFSET_CFG + 8:/* kt2_tdm_A1_56450_8 */ 22651 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 22652 "kt2_tdm_A1_56450_8 \n"))); 22653 sal_memcpy(tdm, 22654 &kt2_tdm_56450A1_ref[0], 22655 sizeof(kt2_tdm_56450A1_ref)); 22656 break; 22657 22658 case BCM56248_DEVICE_ID_OFFSET_CFG + 9: 22659 case BCM56450_DEVICE_ID_OFFSET_CFG + 9:/* kt2_tdm_A1_56450_9 */ 22660 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 22661 "kt2_tdm_A1A_56450_9 \n"))); 22662 sal_memcpy(tdm, 22663 &kt2_tdm_56450A1A_ref[0], 22664 sizeof(kt2_tdm_56450A1A_ref)); 22665 break; 22666 22667 case BCM56248_DEVICE_ID_OFFSET_CFG + 10: 22668 /* kt2_tdm_A2_56450_10 */ 22669 case BCM56450_DEVICE_ID_OFFSET_CFG + 10: 22670 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 22671 "kt2_tdm_A2_56450_10 \n"))); 22672 sal_memcpy(tdm, 22673 &kt2_tdm_56450A2_ref[0], 22674 sizeof(kt2_tdm_56450A2_ref)); 22675 kt2_tdm_replace(tdm, tdm_size, KT2_OLP_PORT, 22676 KT2_IDLE, 0); 22677 break; 22678 22679 case BCM56248_DEVICE_ID_OFFSET_CFG + 11: 22680 /* kt2_tdm_A2_56450_11 */ 22681 case BCM56450_DEVICE_ID_OFFSET_CFG + 11: 22682 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 22683 "kt2_tdm_A2_56450_11 \n"))); 22684 sal_memcpy(tdm, 22685 &kt2_tdm_56450A2_ref[0], 22686 sizeof(kt2_tdm_56450A2_ref)); 22687 break; 22688 22689 case BCM56248_DEVICE_ID_OFFSET_CFG + 12: 22690 /* kt2_tdm_A3_56450_12 */ 22691 case BCM56450_DEVICE_ID_OFFSET_CFG + 12: 22692 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 22693 "kt2_tdm_A3_56450_12 \n"))); 22694 sal_memcpy(tdm, 22695 &kt2_tdm_56450A3_ref[0], 22696 sizeof(kt2_tdm_56450A3_ref)); 22697 break; 22698 22699 case BCM56248_DEVICE_ID_OFFSET_CFG + 13: 22700 /* kt2_tdm_A2_56450_13 */ 22701 case BCM56450_DEVICE_ID_OFFSET_CFG + 13: 22702 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 22703 "kt2_tdm_A2_56450_13 \n"))); 22704 sal_memcpy(tdm, 22705 &kt2_tdm_56450A2_ref[0], 22706 sizeof(kt2_tdm_56450A2_ref)); 22707 kt2_tdm_replace(tdm, tdm_size, 26, 28, 0); 22708 kt2_tdm_replace(tdm, tdm_size, 25, 27, 0); 22709 break; 22710 22711 case BCM56248_DEVICE_ID_OFFSET_CFG + 14: 22712 /* kt2_tdm_A2_56450_14 */ 22713 case BCM56450_DEVICE_ID_OFFSET_CFG + 14: 22714 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 22715 "kt2_tdm_A1_56450_14 \n"))); 22716 sal_memcpy(tdm, 22717 &kt2_tdm_56450A1_ref[0], 22718 sizeof(kt2_tdm_56450A1_ref)); 22719 break; 22720 22721 case BCM56248_DEVICE_ID_OFFSET_CFG + 15: 22722 /* kt2_tdm_A4_56450_15 */ 22723 case BCM56450_DEVICE_ID_OFFSET_CFG + 15: 22724 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 22725 "kt2_tdm_A4_56450_15 \n"))); 22726 memcpy(tdm, 22727 &kt2_tdm_56450A4_ref[0], 22728 sizeof(kt2_tdm_56450A4_ref)); 22729 break; 22730 /* kt2_tdm_F_56450_16 */ 22731 case BCM56450_DEVICE_ID_OFFSET_CFG + 16: 22732 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 22733 "kt2_tdm_F_56450_16 \n"))); 22734 sal_memcpy(tdm, 22735 &kt2_tdm_56450F_ref[0], 22736 sizeof(kt2_tdm_56450F_ref)); 22737 break; 22738 22739 case BCM56452_DEVICE_ID_OFFSET_CFG + 1: 22740 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 22741 "kt2_tdm_C_56452_1 \n"))); 22742 sal_memcpy(tdm, 22743 &kt2_tdm_56455C_ref[0], 22744 sizeof(kt2_tdm_56455C_ref)); 22745 break; 22746 22747 case BCM56452_DEVICE_ID_OFFSET_CFG + 2: 22748 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 22749 "kt2_tdm_C1_56452_2 \n"))); 22750 sal_memcpy(tdm, 22751 &kt2_tdm_56452C1_ref[0], 22752 sizeof(kt2_tdm_56452C1_ref)); 22753 break; 22754 22755 case BCM56452_DEVICE_ID_OFFSET_CFG + 3: 22756 case BCM56452_DEVICE_ID_OFFSET_CFG + 4: 22757 sal_memcpy(tdm, 22758 &kt2_tdm_56452C1_ref[0], 22759 sizeof(kt2_tdm_56452C1_ref)); 22760 for(port = 2; port <= 8; port++) { 22761 kt2_tdm_replace(tdm, 64, port, 1, 0); 22762 } 22763 for(port = 9; port <=16 ; port++) { 22764 kt2_tdm_replace(tdm, 64, port, 5, 0); 22765 } 22766 for(port = 17; port <= 24; port++) { 22767 kt2_tdm_replace(tdm, 64, port, KT2_IDLE, 0); 22768 } 22769 if (cfg_num == BCM56452_DEVICE_ID_OFFSET_CFG + 3) { 22770 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 22771 "kt2_tdm_C1_56452_3 \n"))); 22772 kt2_tdm_replace(tdm, 64, KT2_OLP_PORT, KT2_IDLE, 0); 22773 } else { 22774 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 22775 "kt2_tdm_C1_56452_4 \n"))); 22776 } 22777 break; 22778 case BCM56452_DEVICE_ID_OFFSET_CFG + 5: 22779 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 22780 "kt2_tdm_B_56452_5 \n"))); 22781 sal_memcpy(tdm, 22782 &kt2_tdm_56452B_new_ref[0], 22783 sizeof(kt2_tdm_56452B_new_ref)); 22784 for(port=1;port<=8;port++) { 22785 kt2_tdm_replace(tdm,90,port,KT2_IDLE,0); 22786 } 22787 tdm_index=0; 22788 for (outer_index=1;outer_index<=4;outer_index++) { 22789 for (inner_index=0;inner_index < 6;inner_index++) { 22790 port = outer_index + inner_index*4;/* 1,5,9,13,17,21 22791 2,6,10,14,18,22, 22792 3,7,11,15,19,23, 22793 4,8,12,16,20,24 22794 */ 22795 while(tdm[tdm_index] != KT2_IDLE) { 22796 tdm_index++; 22797 } 22798 tdm[tdm_index]=port; 22799 } 22800 } 22801 kt2_tdm_replace(tdm,90,26,KT2_IDLE,0); 22802 kt2_tdm_replace(tdm,90,38,KT2_IDLE,0); 22803 kt2_tdm_replace(tdm,90,39,KT2_IDLE,0); 22804 break; 22805 22806 case BCM56452_DEVICE_ID_OFFSET_CFG + 6: 22807 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 22808 "kt2_tdm_B1_56452_6 \n"))); 22809 sal_memcpy(tdm, 22810 &kt2_tdm_56452B1_ref[0], 22811 sizeof(kt2_tdm_56452B1_ref)); 22812 kt2_tdm_replace(tdm,60,1,60,0); 22813 kt2_tdm_replace(tdm,60,5,60,0); 22814 kt2_tdm_replace(tdm,60,25,60,0); 22815 for (inner_index=1;inner_index <= 4;inner_index++) { 22816 for (outer_index=0;outer_index< 6;outer_index++) { 22817 port = inner_index + outer_index*4; 22818 kt2_tdm_replace(tdm,60,60,port,1); 22819 } 22820 } 22821 kt2_tdm_replace(tdm,60,60,KT2_IDLE,0); 22822 break; 22823 22824 case BCM56452_DEVICE_ID_OFFSET_CFG + 7: 22825 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 22826 "kt2_tdm_B_56452_7 \n"))); 22827 sal_memcpy(tdm, 22828 &kt2_tdm_56452B_new_ref[0], 22829 sizeof(kt2_tdm_56452B_new_ref)); 22830 for(port=1;port<=8;port++) { 22831 kt2_tdm_replace(tdm,90,port,KT2_IDLE,0); 22832 } 22833 tdm_index=0; 22834 for (outer_index=1;outer_index<=4;outer_index++) { 22835 for (inner_index=0;inner_index < 6;inner_index++) { 22836 port = outer_index + inner_index*4;/* 1,5,9,13,17,21 22837 2,6,10,14,18,22, 22838 3,7,11,15,19,23, 22839 4,8,12,16,20,24 22840 */ 22841 while(tdm[tdm_index] != KT2_IDLE) { 22842 tdm_index++; 22843 } 22844 tdm[tdm_index]=port; 22845 } 22846 } 22847 22848 kt2_tdm_replace(tdm,90,25,KT2_IDLE,0); 22849 kt2_tdm_replace(tdm,90,35,KT2_IDLE,0); 22850 kt2_tdm_replace(tdm,90,36,KT2_IDLE,0); 22851 kt2_tdm_replace(tdm,90,37,KT2_IDLE,0); 22852 kt2_tdm_replace(tdm,90,26,KT2_IDLE,0); 22853 kt2_tdm_replace(tdm,90,38,KT2_IDLE,0); 22854 kt2_tdm_replace(tdm,90,39,KT2_IDLE,0); 22855 kt2_tdm_replace(tdm,90,40,KT2_IDLE,0); 22856 break; 22857 22858 case BCM56452_DEVICE_ID_OFFSET_CFG + 8: 22859 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 22860 "kt2_tdm_B_56452_8 \n"))); 22861 sal_memcpy(tdm, 22862 &kt2_tdm_56452B_new_ref[0], 22863 sizeof(kt2_tdm_56452B_new_ref)); 22864 mxqblock = 6; 22865 outer_index= 0; 22866 for (inner_index=0; inner_index < 90; inner_index++) { 22867 if (tdm[inner_index] == 25) { 22868 tdm[inner_index] = (*kt2_mxqblock_ports[unit]) 22869 [mxqblock][outer_index]; 22870 outer_index = (outer_index + 1) % 4; 22871 } 22872 } 22873 break; 22874 case BCM56452_DEVICE_ID_OFFSET_CFG + 9: 22875 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 22876 "kt2_tdm_B1_56452_9 \n"))); 22877 sal_memcpy(tdm, 22878 &kt2_tdm_56452B1_ref[0], 22879 sizeof(kt2_tdm_56452B1_ref)); 22880 break; 22881 22882 case BCM56452_DEVICE_ID_OFFSET_CFG + 10: 22883 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 22884 "kt2_tdm_B2_56452_10 \n"))); 22885 sal_memcpy(tdm, 22886 &kt2_tdm_56452B2_ref[0], 22887 sizeof(kt2_tdm_56452B2_ref)); 22888 break; 22889 22890 case BCM56454_DEVICE_ID_OFFSET_CFG + 1: /* kt2_tdm_D_56454_1 */ 22891 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 22892 "kt2_tdm_D1_56454_1 \n"))); 22893 sal_memcpy(tdm, 22894 &kt2_tdm_56454D1_ref[0], 22895 sizeof(kt2_tdm_56454D1_ref)); 22896 break; 22897 22898 case BCM56454_DEVICE_ID_OFFSET_CFG + 2: /* kt2_tdm_D_56454_2 */ 22899 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 22900 "kt2_tdm_D2_56454_2 \n"))); 22901 sal_memcpy(tdm, 22902 &kt2_tdm_56454D1_ref[0], 22903 sizeof(kt2_tdm_56454D1_ref)); 22904 kt2_tdm_replace(tdm,40,27,25,0); 22905 kt2_tdm_replace(tdm,40,28,26,0); 22906 kt2_tdm_replace(tdm,40,KT2_OLP_PORT,KT2_IDLE,0); 22907 break; 22908 case BCM56455_DEVICE_ID_OFFSET_CFG + 1: 22909 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 22910 "kt2_tdm_C_56455_1 \n"))); 22911 sal_memcpy(tdm, 22912 &kt2_tdm_56455C_ref[0], 22913 sizeof(kt2_tdm_56455C_ref)); 22914 break; 22915 case BCM56455_DEVICE_ID_OFFSET_CFG + 2: 22916 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 22917 "kt2_tdm_C_56455_2 \n"))); 22918 sal_memcpy(tdm, 22919 &kt2_tdm_56455C_ref[0], 22920 sizeof(kt2_tdm_56455C_ref)); 22921 kt2_tdm_swap(tdm, 84, 26, 28); 22922 kt2_tdm_replace(tdm, 84, 27, KT2_IDLE, 0); 22923 kt2_tdm_replace(tdm, 84, 28, KT2_IDLE, 0); 22924 for (port = 1; port <= 8; port++) { 22925 kt2_tdm_replace(tdm, 84, port, KT2_IDLE, 0); 22926 kt2_tdm_replace(tdm, 84, port + 16, KT2_IDLE, 0); 22927 } 22928 break; 22929 case BCM56248_DEVICE_ID_OFFSET_CFG + 16: 22930 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 22931 "kt2_tdm_A3_56450_16 \n"))); 22932 sal_memcpy(tdm, 22933 &kt2_tdm_56450A3_ref[0], sizeof(kt2_tdm_56450A3_ref)); 22934 break; 22935 case BCM56248_DEVICE_ID_OFFSET_CFG + 17: 22936 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 22937 "kt2_tdm_D2_56248_17 \n"))); 22938 sal_memcpy(tdm, 22939 &kt2_tdm_56248D2_ref[0], 22940 sizeof(kt2_tdm_56248D2_ref)); 22941 kt2_tdm_replace(tdm,40,9,KT2_IDLE,1); 22942 kt2_tdm_replace(tdm,40,28,KT2_IDLE,1); 22943 kt2_tdm_replace(tdm,40,29,KT2_IDLE,1); 22944 kt2_tdm_replace(tdm,40,29,30,1); 22945 break; 22946 22947 default: 22948 LOG_CLI((BSL_META_U(unit, 22949 "Not Supported Cfg Value%d \n"),cfg_num)); 22950 return SOC_E_FAIL; 22951 } 22952 break; 22953 22954 default: 22955 return SOC_E_FAIL; 22956 } 22957 return SOC_E_NONE; 22958 } 22959 22960 int _soc_katana2_flexio_scache_allocate(int unit) 22961 { 22962 int rv=SOC_E_NONE; 22963 uint8 *flexio_scache_ptr; 22964 soc_scache_handle_t scache_handle; 22965 uint32 alloc_get=0; 22966 uint32 alloc_size = sizeof(scache_begin_magic_number) + 22967 sizeof(kt2_scache_tdm_info[unit]) + 22968 sizeof(kt2_scache_tdm[unit]) + 22969 sizeof(kt2_scache_speed[unit]) + 22970 sizeof(kt2_scache_port_details[unit]) + 22971 sizeof(kt2_scache_portgroup[unit]) + 22972 sizeof(scache_end_magic_number); 22973 22974 SOC_SCACHE_HANDLE_SET(scache_handle, unit, SOC_SCACHE_FLEXIO_HANDLE, 0); 22975 rv = soc_scache_alloc(unit, scache_handle, 22976 alloc_size + SOC_WB_SCACHE_CONTROL_SIZE); 22977 if (rv == SOC_E_CONFIG) { 22978 /* Probably Level1 */ 22979 return SOC_E_NONE; 22980 } 22981 /* NotRequired but just to confirm Get the pointer for the Level 2 cache */ 22982 SOC_IF_ERROR_RETURN(soc_scache_ptr_get(unit, scache_handle, 22983 &flexio_scache_ptr, &alloc_get)); 22984 if (alloc_get != (alloc_size + SOC_WB_SCACHE_CONTROL_SIZE)) { 22985 /* Expected size doesn't match retrieved size */ 22986 return SOC_E_INTERNAL; 22987 } 22988 if (NULL == flexio_scache_ptr) { 22989 return SOC_E_MEMORY; 22990 } 22991 LOG_VERBOSE(BSL_LS_SOC_COMMON, 22992 (BSL_META_U(unit, 22993 "%s()[LINE:%d] DONE \n"),FUNCTION_NAME(), __LINE__)); 22994 return SOC_E_NONE; 22995 } 22996 22997 int _soc_katana2_flexio_scache_retrieve(int unit) 22998 { 22999 int rv = SOC_E_NONE; 23000 uint8 *flexio_scache_ptr = NULL; 23001 soc_scache_handle_t scache_handle; 23002 uint32 alloc_get=0; 23003 uint32 alloc_size = sizeof(scache_begin_magic_number) + 23004 sizeof(kt2_scache_tdm_info[unit]) + 23005 sizeof(kt2_scache_tdm[unit]) + 23006 sizeof(kt2_scache_speed[unit]) + 23007 sizeof(kt2_scache_port_details[unit]) + 23008 sizeof(kt2_scache_portgroup[unit]) + 23009 sizeof(scache_end_magic_number); 23010 uint32 realloc_size = 0; 23011 uint32 offset=0; 23012 uint32 scache_offset=0; 23013 uint16 recovered_ver = 0; 23014 uint16 default_ver = BCM_WB_DEFAULT_VERSION; 23015 uint32 is_upgrade = 0; 23016 uint32 recover_default_tdm = 0; 23017 uint32 scache_tdm_size = 0; 23018 char config_str[80]; 23019 char config_value[10]; 23020 int cfg_num = 0; 23021 23022 SOC_SCACHE_HANDLE_SET(scache_handle, unit, SOC_SCACHE_FLEXIO_HANDLE, 0); 23023 /* NotRequired but just to confirm Get the pointer for the Level 2 cache */ 23024 rv = soc_scache_ptr_get(unit, scache_handle, 23025 &flexio_scache_ptr, &alloc_get); 23026 23027 if (SOC_FAILURE(rv)) { 23028 if (rv == SOC_E_NOT_FOUND) { 23029 /* Probably Level1 */ 23030 LOG_ERROR(BSL_LS_SOC_COMMON, 23031 (BSL_META_U(unit, 23032 "No scache data available(Level1 WarmBoot) - %s\n"), 23033 soc_errmsg(rv))); 23034 return SOC_E_NONE; 23035 } else { 23036 LOG_ERROR(BSL_LS_SOC_COMMON, 23037 (BSL_META_U(unit, 23038 "Failed to recover scache data - %s\n"),soc_errmsg(rv))); 23039 return rv; 23040 } 23041 } 23042 23043 if (NULL == flexio_scache_ptr) { 23044 LOG_ERROR(BSL_LS_SOC_COMMON, 23045 (BSL_META_U(unit, 23046 "No scache data recovered!!\n"))); 23047 return SOC_E_MEMORY; 23048 } 23049 23050 23051 /* 23052 * Check the magic number present at the start of the 23053 * scache data. 23054 */ 23055 23056 scache_offset = 0; 23057 if (sal_memcmp(&flexio_scache_ptr[scache_offset], 23058 &scache_begin_magic_number[0], 23059 sizeof(scache_begin_magic_number)) != 0) { 23060 23061 LOG_ERROR(BSL_LS_SOC_COMMON, 23062 (BSL_META_U(unit, 23063 "Corrupt scache for flexio operation - " 23064 "Magic number missing at start\n"))); 23065 return SOC_E_INTERNAL; 23066 } 23067 23068 scache_offset += sizeof(scache_begin_magic_number); 23069 23070 23071 /* 23072 * If allocated scache size and recovered scache size 23073 * are not equal, more data was added to scache data. 23074 * Set upgrade to true. 23075 */ 23076 if (alloc_get != (alloc_size + SOC_WB_SCACHE_CONTROL_SIZE)) { 23077 is_upgrade = 1; 23078 if (default_ver == BCM_WB_VERSION_1_2) { 23079 /* Expected size doesn't match retrieved size */ 23080 LOG_INFO(BSL_LS_SOC_COMMON, 23081 (BSL_META_U(unit, 23082 "Upgrade detected - " 23083 "Scache for flexio size mismatch. " 23084 "Expected size[%d], recovered size[%d]\n"), 23085 (int) (alloc_size + SOC_WB_SCACHE_CONTROL_SIZE), 23086 alloc_get)); 23087 recovered_ver = BCM_WB_VERSION_1_1; 23088 } 23089 23090 /* 23091 * reallocate scache space for upgrades and downgrades 23092 */ 23093 realloc_size = ((alloc_size > (alloc_get - SOC_WB_SCACHE_CONTROL_SIZE))? 23094 (alloc_size - alloc_get): (alloc_get - alloc_size)) + 23095 SOC_WB_SCACHE_CONTROL_SIZE; 23096 LOG_VERBOSE(BSL_LS_SOC_COMMON, 23097 (BSL_META_U(unit, 23098 "scache reallocate failed for size(%d) - %s\n"), 23099 realloc_size, soc_errmsg(rv))); 23100 } else { 23101 recovered_ver = BCM_WB_DEFAULT_VERSION; 23102 } 23103 23104 if (recovered_ver > default_ver) { 23105 LOG_VERBOSE(BSL_LS_SOC_COMMON, 23106 (BSL_META_U(unit, 23107 "Downgrade detected - " 23108 "Current version %d.%d found %d.%d\n"), 23109 SOC_SCACHE_VERSION_MAJOR(default_ver), 23110 SOC_SCACHE_VERSION_MINOR(default_ver), 23111 SOC_SCACHE_VERSION_MAJOR(recovered_ver), 23112 SOC_SCACHE_VERSION_MINOR(recovered_ver))); 23113 } else if (recovered_ver < default_ver) { 23114 LOG_VERBOSE(BSL_LS_SOC_COMMON, 23115 (BSL_META_U(unit, 23116 "Upgrade detected - " 23117 "Current version %d.%d found %d.%d\n"), 23118 SOC_SCACHE_VERSION_MAJOR(default_ver), 23119 SOC_SCACHE_VERSION_MINOR(default_ver), 23120 SOC_SCACHE_VERSION_MAJOR(recovered_ver), 23121 SOC_SCACHE_VERSION_MINOR(recovered_ver))); 23122 } 23123 23124 /* 23125 * If upgrade detected get the config num 23126 */ 23127 if (is_upgrade) { 23128 SOC_IF_ERROR_RETURN(_soc_katana2_get_cfg_num(unit, &cfg_num)); 23129 LOG_INFO(BSL_LS_SOC_COMMON, 23130 (BSL_META_U(unit, 23131 "config: %d\n"), cfg_num)); 23132 } 23133 23134 /* recover the tdm info from the scache data */ 23135 sal_memcpy(&kt2_scache_tdm_info[unit], 23136 &flexio_scache_ptr[scache_offset], 23137 sizeof(kt2_scache_tdm_info[unit])); 23138 23139 /* 23140 * if upgrade check TDM size of the current config 23141 * and the recovered config. If not equal, new TDM 23142 * settings were added for the config. Overwrite 23143 * the scache_tdm_info with the default tdm_info 23144 * of the current config. 23145 */ 23146 if (is_upgrade) { 23147 if ((bcm56450_tdm_info[cfg_num].tdm_size != 23148 kt2_scache_tdm_info[unit].tdm_size) || 23149 (bcm56450_tdm_info[cfg_num].row != kt2_scache_tdm_info[unit].row) || 23150 (bcm56450_tdm_info[cfg_num].col != kt2_scache_tdm_info[unit].col)) { 23151 LOG_WARN(BSL_LS_SOC_COMMON, 23152 (BSL_META_U(unit, 23153 "Upgrade detected - Overwrite TDM info\n"))); 23154 23155 sal_memcpy(&kt2_scache_tdm_info[unit], 23156 &bcm56450_tdm_info[cfg_num], 23157 sizeof(bcm56450_tdm_info_t)); 23158 recover_default_tdm = 1; 23159 } else if ((cfg_num == BCM56450_DEVICE_ID_OFFSET_CFG + 10) || 23160 (cfg_num == BCM56450_DEVICE_ID_OFFSET_CFG + 11) || 23161 (cfg_num == BCM56450_DEVICE_ID_OFFSET_CFG + 13)) { 23162 recover_default_tdm = 1; 23163 } 23164 } 23165 23166 scache_offset += sizeof(kt2_scache_tdm_info[unit]); 23167 23168 /* 23169 * Upgrade with new TDM settings detected, recover the default 23170 * tdm settings of the current config. 23171 */ 23172 if (recover_default_tdm) { 23173 LOG_WARN(BSL_LS_SOC_COMMON, 23174 (BSL_META_U(unit, 23175 "Recovering default TDM for config %d\n"), cfg_num)); 23176 _soc_katana2_default_tdm_recover(unit, (uint32 *) kt2_scache_tdm[unit]); 23177 kt2_tdm_display(unit, (uint32 *) (&kt2_scache_tdm[unit][0]), 23178 kt2_scache_tdm_info[unit].tdm_size, 23179 kt2_scache_tdm_info[unit].row, 23180 kt2_scache_tdm_info[unit].col); 23181 23182 if (recovered_ver <= BCM_WB_VERSION_1_1) { 23183 LOG_VERBOSE(BSL_LS_SOC_COMMON, 23184 (BSL_META_U(unit, 23185 "cfg: %d ver:%d %d\n"), cfg_num, 23186 recovered_ver, (int)sizeof(bcm56450_tdm[cfg_num]))); 23187 } 23188 } else { 23189 sal_memcpy(&kt2_scache_tdm[unit], 23190 &flexio_scache_ptr[scache_offset], sizeof(kt2_scache_tdm[unit])); 23191 } 23192 23193 /* move the scache offset based on the recovered_ver */ 23194 if (recovered_ver <= BCM_WB_VERSION_1_1) { 23195 scache_tdm_size = KT2_MAX_TDM_SLOTS_VER_1_1; 23196 } else if (recovered_ver == BCM_WB_DEFAULT_VERSION) { 23197 scache_tdm_size = KT2_MAX_TDM_SLOTS; 23198 } 23199 23200 scache_offset += (sizeof(kt2_scache_tdm[unit][0]) * scache_tdm_size); 23201 23202 sal_memcpy(&kt2_scache_speed[unit], &flexio_scache_ptr[scache_offset], 23203 sizeof(kt2_scache_speed[unit])); 23204 23205 scache_offset += sizeof(kt2_scache_speed[unit]); 23206 sal_memcpy(&kt2_scache_port_details[unit], 23207 &flexio_scache_ptr[scache_offset], 23208 sizeof(kt2_scache_port_details[unit])); 23209 23210 scache_offset += sizeof(kt2_scache_port_details[unit]); 23211 for (offset=0; offset < sizeof(kt2_scache_portgroup[unit]);offset++) { 23212 kt2_scache_portgroup[unit][offset] = flexio_scache_ptr[scache_offset]; 23213 sal_sprintf(config_value,"%d",kt2_scache_portgroup[unit][offset]); 23214 sal_sprintf(config_str,"portgroup_%d",offset + 27); 23215 if (kt2_scache_portgroup[unit][offset]) { 23216 _soc_kt2_mem_config_set(unit,config_str,config_value); 23217 } 23218 scache_offset += 1; 23219 } 23220 if (sal_memcmp(&flexio_scache_ptr[scache_offset], 23221 &scache_end_magic_number[0], 23222 sizeof(scache_end_magic_number)) != 0) { 23223 LOG_CLI((BSL_META_U(unit, 23224 "Corrupt scache for flexio operation - " 23225 "Magic number check at the end of scache data failed\n"))); 23226 return SOC_E_INTERNAL; 23227 } 23228 LOG_VERBOSE(BSL_LS_SOC_COMMON, 23229 (BSL_META_U(unit, 23230 "%s()[LINE:%d] \n"),FUNCTION_NAME(), __LINE__)); 23231 23232 if (realloc_size > 0) { 23233 rv = soc_scache_realloc(unit, scache_handle, realloc_size); 23234 if (SOC_FAILURE(rv)) { 23235 LOG_ERROR(BSL_LS_SOC_COMMON, 23236 (BSL_META_U(unit, 23237 "scache reallocate failed for size(%d) - %s\n"), 23238 realloc_size, soc_errmsg(rv))); 23239 return rv; 23240 } 23241 } 23242 return SOC_E_NONE; 23243 } 23244 23245 int _soc_katana2_flexio_scache_sync(int unit) 23246 { 23247 int rv; 23248 uint8 *flexio_scache_ptr; 23249 uint8 mxqblock = 0; 23250 soc_scache_handle_t scache_handle; 23251 uint32 alloc_get=0; 23252 uint32 alloc_size = sizeof(scache_begin_magic_number) + 23253 sizeof(kt2_scache_tdm_info[unit]) + 23254 sizeof(kt2_scache_tdm[unit]) + 23255 sizeof(kt2_scache_speed[unit]) + 23256 sizeof(kt2_scache_port_details[unit]) + 23257 sizeof(kt2_scache_portgroup[unit]) + 23258 sizeof(scache_end_magic_number); 23259 uint32 scache_offset=0; 23260 uint32 offset=0; 23261 int cfg_num=0; 23262 char config_str[80]; 23263 uint32 port=0; 23264 23265 /* uint32 num_cfg; */ 23266 /* uint32 num_cfg; */ 23267 SOC_SCACHE_HANDLE_SET(scache_handle, unit, SOC_SCACHE_FLEXIO_HANDLE, 0); 23268 /* NotRequired but just to confirm Get the pointer for the Level 2 cache */ 23269 rv = soc_scache_ptr_get(unit, scache_handle, 23270 &flexio_scache_ptr, &alloc_get); 23271 if (rv == SOC_E_NOT_FOUND) { 23272 /* Probably Level1 */ 23273 return SOC_E_NONE; 23274 } 23275 if (alloc_get != (alloc_size + SOC_WB_SCACHE_CONTROL_SIZE)) { 23276 /* Expected size doesn't match retrieved size */ 23277 return SOC_E_INTERNAL; 23278 } 23279 if (NULL == flexio_scache_ptr) { 23280 return SOC_E_MEMORY; 23281 } 23282 SOC_IF_ERROR_RETURN(_soc_katana2_get_cfg_num(unit, &cfg_num)); 23283 if (cfg_num >= (sizeof(bcm56450_tdm)/sizeof(bcm56450_tdm[0]))) { 23284 return SOC_E_FAIL; 23285 } 23286 23287 scache_offset = 0; 23288 sal_memcpy(&flexio_scache_ptr[scache_offset], 23289 &scache_begin_magic_number[0], 23290 sizeof(scache_begin_magic_number)); 23291 23292 scache_offset += sizeof(scache_begin_magic_number); 23293 sal_memcpy(&flexio_scache_ptr[scache_offset], 23294 &bcm56450_tdm_info[cfg_num], 23295 sizeof(kt2_scache_tdm_info[unit])); 23296 23297 scache_offset += sizeof(kt2_scache_tdm_info[unit]); 23298 sal_memcpy(&flexio_scache_ptr[scache_offset], 23299 &kt2_current_tdm[0], 23300 sizeof(uint32)* bcm56450_tdm_info[cfg_num].tdm_size); 23301 23302 scache_offset += sizeof(kt2_scache_tdm[unit]); 23303 23304 23305 for (port=1 ; port <= KT2_MAX_PHYSICAL_PORTS ; port++) { 23306 mxqblock = (*kt2_port_to_mxqblock[unit])[port-1]; 23307 kt2_scache_speed[unit][port-1] = 0; 23308 if (IS_GE_PORT(unit,port)) { 23309 if ((bcm56450_speed[unit][cfg_num][port-1] == 0) || /*Converted */ 23310 (bcm56450_speed[unit][cfg_num][port-1] >= 2500)) { 23311 kt2_scache_speed[unit][port - 1] = 2500; 23312 } else { 23313 kt2_scache_speed[unit][port - 1] = 1000; 23314 } 23315 } 23316 if ((port == KT2_OLP_PORT) && (SOC_INFO(unit).olp_port[0])) { 23317 kt2_scache_speed[unit][port - 1] = 2500; 23318 } 23319 if (IS_XE_PORT(unit,port)) { 23320 kt2_scache_speed[unit][port - 1] = 10000; 23321 } 23322 if (IS_HG_PORT(unit,port)) { 23323 if (bcm56450_speed[unit][cfg_num][port-1] > 13000) { 23324 kt2_scache_speed[unit][port - 1] = 21000; 23325 } else if (bcm56450_speed[unit][cfg_num][port-1] == 10000) { 23326 /* Assuming the HG port has been created 23327 * via encapsulation 23328 */ 23329 kt2_scache_speed[unit][port - 1] = 10000; 23330 } else { 23331 kt2_scache_speed[unit][port - 1] = 13000; 23332 } 23333 } 23334 if (IS_HG2_ENABLED_PORT(unit,port) && 23335 ((mxqblock == 8) || (mxqblock == 9))) { 23336 /* 21G supported only in WC0/WC1 */ 23337 if (bcm56450_speed[unit][cfg_num][port-1] > 13000) { 23338 kt2_scache_speed[unit][port - 1] = 21000; 23339 } else if (bcm56450_speed[unit][cfg_num][port-1] == 10000) { 23340 /* Assuming the HG port has been created 23341 * via encapsulation 23342 */ 23343 kt2_scache_speed[unit][port - 1] = 10000; 23344 } else { 23345 kt2_scache_speed[unit][port - 1] = 13000; 23346 } 23347 } 23348 if (IS_HL_PORT(unit,port)) { 23349 kt2_scache_speed[unit][port - 1] = 2500; 23350 } 23351 } 23352 sal_memcpy(&flexio_scache_ptr[scache_offset], 23353 &kt2_scache_speed[unit][0], sizeof(kt2_scache_speed[unit])); 23354 23355 scache_offset += sizeof(kt2_scache_speed[unit]); 23356 for (port=1 ; port <= KT2_MAX_PHYSICAL_PORTS ; port++) { 23357 /* mxqblock = (*kt2_port_to_mxqblock[unit])[port-1]; */ 23358 kt2_scache_port_details[unit][port-1].start_port_no = port; 23359 kt2_scache_port_details[unit][port-1].end_port_no = port; 23360 kt2_scache_port_details[unit][port-1].port_incr = 1; 23361 kt2_scache_port_details[unit][port-1].port_type = 0; 23362 kt2_scache_port_details[unit][port-1].port_speed = 0xFFFF; 23363 if (IS_GE_PORT(unit,port)) { 23364 if ((bcm56450_speed[unit][cfg_num][port-1] == 0) || /*Converted */ 23365 (bcm56450_speed[unit][cfg_num][port-1] >= 2500)) { 23366 kt2_scache_port_details[unit][port-1].port_speed = 2500; 23367 } else { 23368 kt2_scache_port_details[unit][port-1].port_speed = 1000; 23369 } 23370 kt2_scache_port_details[unit][port-1].port_type = GE_PORT; 23371 } 23372 if ((port == KT2_OLP_PORT) && (SOC_INFO(unit).olp_port[0])) { 23373 kt2_scache_port_details[unit][port-1].port_speed = 2500; 23374 kt2_scache_port_details[unit][port-1].port_type |= OLP_PORT; 23375 } 23376 if (IS_XE_PORT(unit,port)) { 23377 kt2_scache_port_details[unit][port-1].port_speed = 10000; 23378 kt2_scache_port_details[unit][port - 1].port_type |= XE_PORT; 23379 } 23380 if (IS_HG_PORT(unit,port)) { 23381 if (bcm56450_speed[unit][cfg_num][port-1] > 13000) { 23382 kt2_scache_port_details[unit][port-1].port_speed = 21000; 23383 } else { 23384 kt2_scache_port_details[unit][port-1].port_speed = 13000; 23385 } 23386 kt2_scache_port_details[unit][port - 1].port_type |= HG_PORT; 23387 kt2_scache_port_details[unit][port - 1].port_type |= STK_PORT; 23388 } 23389 if (IS_HG2_ENABLED_PORT(unit,port)) { 23390 kt2_scache_port_details[unit][port-1].port_speed = 21000; 23391 kt2_scache_port_details[unit][port - 1].port_type |= HG_PORT; 23392 kt2_scache_port_details[unit][port - 1].port_type |= STK_PORT; 23393 } 23394 if (IS_HL_PORT(unit,port)) { 23395 kt2_scache_port_details[unit][port-1].port_speed = 2500; 23396 kt2_scache_port_details[unit][port-1].port_type |= HGL_PORT; 23397 kt2_scache_port_details[unit][port-1].port_type |= STK_PORT; 23398 } 23399 } 23400 sal_memcpy(&flexio_scache_ptr[scache_offset], 23401 &kt2_scache_port_details[unit], 23402 sizeof(kt2_scache_port_details[unit])); 23403 23404 scache_offset += sizeof(kt2_scache_port_details[unit]); 23405 for (offset=0; offset < sizeof(kt2_scache_portgroup[unit]);offset++) { 23406 sal_sprintf(config_str,"portgroup_%d",offset + 27); 23407 flexio_scache_ptr[scache_offset] = soc_property_get(unit, 23408 config_str,0); 23409 scache_offset += 1; 23410 } 23411 23412 23413 /* num_cfg = COUNTOF(bcm56450_tdm_info); */ 23414 sal_memcpy(&flexio_scache_ptr[scache_offset], 23415 &scache_end_magic_number[0], 23416 sizeof(scache_end_magic_number)); 23417 LOG_VERBOSE(BSL_LS_SOC_COMMON, 23418 (BSL_META_U(unit, 23419 "%s()[LINE:%d] \n"),FUNCTION_NAME(), __LINE__)); 23420 return SOC_E_NONE; 23421 } 23422 #endif 23423 23424 int 23425 soc_kt2_lls_bmap_alloc(int unit) 23426 { 23427 soc_control_t *soc; 23428 int rv = SOC_E_NONE; 23429 int port; 23430 int alloc_size_l0; 23431 int alloc_size_l1; 23432 int alloc_size_l2; 23433 soc_info_t *si; 23434 23435 si = &SOC_INFO(unit); 23436 soc = SOC_CONTROL(unit); 23437 23438 /* First cleanup if any allocation was done earlier. 23439 * This is needed to make sure that on subsequent rc 23440 * there is no memory leak due to MMU LLS usage bitmap 23441 * allocation. 23442 */ 23443 for (port = 0; port < ((si->lb_port)+1); port++) { 23444 if (soc->port_lls_s0_bmap[port] != NULL) { 23445 sal_free(soc->port_lls_s0_bmap[port]); 23446 } 23447 if (soc->port_lls_s1_bmap[port] != NULL) { 23448 sal_free(soc->port_lls_s1_bmap[port]); 23449 } 23450 if (soc->port_lls_l0_bmap[port] != NULL) { 23451 sal_free(soc->port_lls_l0_bmap[port]); 23452 } 23453 if (soc->port_lls_l1_bmap[port] != NULL) { 23454 sal_free(soc->port_lls_l1_bmap[port]); 23455 } 23456 if (soc->port_lls_l2_bmap[port] != NULL) { 23457 sal_free(soc->port_lls_l2_bmap[port]); 23458 } 23459 } 23460 23461 alloc_size_l0 = 23462 SHR_BITALLOCSIZE(soc_mem_index_count(unit, LLS_L0_PARENTm)); 23463 alloc_size_l1 = 23464 SHR_BITALLOCSIZE(soc_mem_index_count(unit, LLS_L1_PARENTm)); 23465 alloc_size_l2 = 23466 SHR_BITALLOCSIZE(soc_mem_index_count(unit, LLS_L2_PARENTm)); 23467 23468 for (port = 0; port < ((si->lb_port)+1); port++) { 23469 soc->port_lls_s0_bmap[port] = sal_alloc(alloc_size_l0, "LLS_S0_BMAP"); 23470 if (soc->port_lls_s0_bmap[port] == NULL) { 23471 rv = SOC_E_MEMORY; 23472 goto clean_up; 23473 } 23474 soc->port_lls_s1_bmap[port] = sal_alloc(alloc_size_l0, "LLS_S1_BMAP"); 23475 if (soc->port_lls_s1_bmap[port] == NULL) { 23476 rv = SOC_E_MEMORY; 23477 goto clean_up; 23478 } 23479 soc->port_lls_l0_bmap[port] = sal_alloc(alloc_size_l0, "LLS_L0_BMAP"); 23480 if (soc->port_lls_l0_bmap[port] == NULL) { 23481 rv = SOC_E_MEMORY; 23482 goto clean_up; 23483 } 23484 soc->port_lls_l1_bmap[port] = sal_alloc(alloc_size_l1, "LLS_L1_BMAP"); 23485 if (soc->port_lls_l1_bmap[port] == NULL) { 23486 rv = SOC_E_MEMORY; 23487 goto clean_up; 23488 } 23489 soc->port_lls_l2_bmap[port] = sal_alloc(alloc_size_l2, "LLS_L2_BMAP"); 23490 if (soc->port_lls_l2_bmap[port] == NULL) { 23491 rv = SOC_E_MEMORY; 23492 goto clean_up; 23493 } 23494 sal_memset(soc->port_lls_s0_bmap[port], 0, alloc_size_l0); 23495 sal_memset(soc->port_lls_s1_bmap[port], 0, alloc_size_l0); 23496 sal_memset(soc->port_lls_l0_bmap[port], 0, alloc_size_l0); 23497 sal_memset(soc->port_lls_l1_bmap[port], 0, alloc_size_l1); 23498 sal_memset(soc->port_lls_l2_bmap[port], 0, alloc_size_l2); 23499 23500 } 23501 23502 clean_up: 23503 if (SOC_FAILURE(rv)) { 23504 for (port = 0; port < ((si->lb_port)+1) ; port++) { 23505 if (soc->port_lls_s0_bmap[port] != NULL) { 23506 sal_free(soc->port_lls_s0_bmap[port]); 23507 } 23508 if (soc->port_lls_s1_bmap[port] != NULL) { 23509 sal_free(soc->port_lls_s1_bmap[port]); 23510 } 23511 if (soc->port_lls_l0_bmap[port] != NULL) { 23512 sal_free(soc->port_lls_l0_bmap[port]); 23513 } 23514 if (soc->port_lls_l1_bmap[port] != NULL) { 23515 sal_free(soc->port_lls_l1_bmap[port]); 23516 } 23517 if (soc->port_lls_l2_bmap[port] != NULL) { 23518 sal_free(soc->port_lls_l2_bmap[port]); 23519 } 23520 } 23521 } 23522 return rv; 23523 } 23524 23525 int 23526 _soc_kt2_cosq_min_bucket_get(int unit, int port, int index, int level, 23527 uint32 *min_quantum, uint32 *mantissa, 23528 uint32 *exp, uint32 *cycle) 23529 { 23530 int rv; 23531 soc_mem_t config_mem[2]; 23532 lls_l0_shaper_config_c_entry_t l0_entry; 23533 lls_l1_shaper_config_c_entry_t l1_entry; 23534 lls_l2_shaper_config_lower_entry_t l2_entry; 23535 uint32 rate_exp[2], rate_mantissa[2]; 23536 uint32 cycle_sel[2]; 23537 int i, idx; 23538 soc_field_t rate_exp_f[] = { 23539 C_MAX_REF_RATE_EXPf, C_MIN_REF_RATE_EXPf 23540 }; 23541 soc_field_t rate_mant_f[] = { 23542 C_MAX_REF_RATE_MANTf, C_MIN_REF_RATE_MANTf 23543 }; 23544 soc_field_t rate_exp_fields[] = { 23545 C_MAX_REF_RATE_EXP_0f, C_MAX_REF_RATE_EXP_1f, 23546 C_MAX_REF_RATE_EXP_2f, C_MAX_REF_RATE_EXP_3f, 23547 C_MIN_REF_RATE_EXP_0f, C_MIN_REF_RATE_EXP_1f, 23548 C_MIN_REF_RATE_EXP_2f, C_MIN_REF_RATE_EXP_3f 23549 }; 23550 soc_field_t rate_mant_fields[] = { 23551 C_MAX_REF_RATE_MANT_0f, C_MAX_REF_RATE_MANT_1f, 23552 C_MAX_REF_RATE_MANT_2f, C_MAX_REF_RATE_MANT_3f, 23553 C_MIN_REF_RATE_MANT_0f, C_MIN_REF_RATE_MANT_1f, 23554 C_MIN_REF_RATE_MANT_2f, C_MIN_REF_RATE_MANT_3f 23555 }; 23556 static const soc_field_t cycle_sel_fields[] = { 23557 C_MAX_CYCLE_SEL_0f, C_MAX_CYCLE_SEL_1f, 23558 C_MAX_CYCLE_SEL_2f, C_MAX_CYCLE_SEL_3f, 23559 C_MIN_CYCLE_SEL_0f, C_MIN_CYCLE_SEL_1f, 23560 C_MIN_CYCLE_SEL_2f, C_MIN_CYCLE_SEL_3f 23561 }; 23562 soc_field_t cycle_sel_f[] = { 23563 C_MAX_CYCLE_SELf, C_MIN_CYCLE_SELf 23564 }; 23565 int shaper_bucket_index = 0 ; 23566 int max_l1_shaper_bucket = 0; 23567 int max_l2_shaper_bucket = 0 ; 23568 23569 if (min_quantum == NULL ) 23570 { 23571 return BCM_E_INTERNAL; 23572 } 23573 23574 23575 switch (level) { 23576 23577 case _SOC_KT2_COSQ_NODE_LVL_L0: 23578 config_mem[0] = LLS_L0_SHAPER_CONFIG_Cm; 23579 config_mem[1] = LLS_L0_MIN_CONFIG_Cm; 23580 23581 for (i = 1; i < 2; i++) { 23582 SOC_IF_ERROR_RETURN 23583 (soc_mem_read(unit, config_mem[i], MEM_BLOCK_ALL, 23584 index, &l0_entry)); 23585 rate_exp[i] = soc_mem_field32_get(unit, config_mem[i], 23586 &l0_entry, 23587 rate_exp_f[i]); 23588 rate_mantissa[i] = soc_mem_field32_get(unit, config_mem[i], 23589 &l0_entry, 23590 rate_mant_f[i]); 23591 cycle_sel[i] = soc_mem_field32_get(unit, config_mem[i], &l0_entry, 23592 cycle_sel_f[i]); 23593 } 23594 break; 23595 23596 case _SOC_KT2_COSQ_NODE_LVL_L1: 23597 config_mem[0] = LLS_L1_SHAPER_CONFIG_Cm; 23598 config_mem[1] = LLS_L1_MIN_CONFIG_Cm; 23599 max_l1_shaper_bucket = soc_mem_index_count(unit,LLS_L1_PARENTm) / 23600 soc_mem_index_count(unit, 23601 LLS_L1_SHAPER_CONFIG_Cm); 23602 23603 shaper_bucket_index = index % max_l1_shaper_bucket; 23604 for (i = 1; i < 2; i++) { 23605 idx = (i * 4) + shaper_bucket_index; 23606 SOC_IF_ERROR_RETURN 23607 (soc_mem_read(unit, config_mem[i], MEM_BLOCK_ALL, 23608 index / max_l1_shaper_bucket, &l1_entry)); 23609 rate_exp[i] = soc_mem_field32_get(unit, config_mem[i], 23610 &l1_entry, 23611 rate_exp_fields[idx]); 23612 rate_mantissa[i] = soc_mem_field32_get(unit, config_mem[i], 23613 &l1_entry, 23614 rate_mant_fields[idx]); 23615 cycle_sel[i] = soc_mem_field32_get(unit, config_mem[i], &l1_entry, 23616 cycle_sel_f[i]); 23617 } 23618 break; 23619 23620 case _SOC_KT2_COSQ_NODE_LVL_L2: 23621 23622 if ((index % 8) < 4) { 23623 config_mem[0] = LLS_L2_SHAPER_CONFIG_LOWERm; 23624 config_mem[1] = LLS_L2_MIN_CONFIG_LOWER_Cm; 23625 } else { 23626 config_mem[0] = LLS_L2_SHAPER_CONFIG_UPPERm; 23627 config_mem[1] = LLS_L2_MIN_CONFIG_UPPER_Cm; 23628 } 23629 max_l2_shaper_bucket = soc_mem_index_count(unit,LLS_L2_PARENTm)/ 23630 soc_mem_index_count(unit, LLS_L2_SHAPER_CONFIG_LOWERm); 23631 for (i = 1; i < 2; i++) { 23632 idx = (i * 4) + (index % 4); 23633 SOC_IF_ERROR_RETURN 23634 (soc_mem_read(unit, config_mem[i], MEM_BLOCK_ALL, 23635 index/max_l2_shaper_bucket, &l2_entry)); 23636 rate_exp[i] = soc_mem_field32_get(unit, config_mem[i], 23637 &l2_entry, 23638 rate_exp_fields[idx]); 23639 rate_mantissa[i] = soc_mem_field32_get(unit, config_mem[i], 23640 &l2_entry, 23641 rate_mant_fields[idx]); 23642 cycle_sel[i] = soc_mem_field32_get(unit, config_mem[i], &l2_entry, 23643 cycle_sel_fields[idx]); 23644 } 23645 break; 23646 23647 case _SOC_KT2_COSQ_NODE_LVL_S0: 23648 case _SOC_KT2_COSQ_NODE_LVL_S1: 23649 case _SOC_KT2_COSQ_NODE_LVL_ROOT: 23650 return BCM_E_INTERNAL ; 23651 default: 23652 return BCM_E_INTERNAL; 23653 } 23654 23655 23656 rv = soc_katana_compute_shaper_rate(unit, rate_mantissa[1], rate_exp[1], 23657 min_quantum); 23658 if(rv) 23659 { 23660 return rv; 23661 } 23662 *mantissa = rate_mantissa[1]; 23663 *exp = rate_exp[1]; 23664 *cycle = cycle_sel[1]; 23665 23666 return BCM_E_NONE; 23667 } 23668 23669 int 23670 soc_kt2_cosq_min_clear(int unit, int port, int index, uint32 level) 23671 { 23672 lls_l0_shaper_config_c_entry_t l0_entry; 23673 lls_l1_shaper_config_c_entry_t l1_entry; 23674 lls_l2_shaper_config_lower_entry_t l2_entry; 23675 soc_mem_t config_mem; 23676 int idx; 23677 23678 static const soc_field_t rate_exp_fields[] = { 23679 C_MIN_REF_RATE_EXP_0f, C_MIN_REF_RATE_EXP_1f, 23680 C_MIN_REF_RATE_EXP_2f, C_MIN_REF_RATE_EXP_3f 23681 }; 23682 static const soc_field_t rate_mant_fields[] = { 23683 C_MIN_REF_RATE_MANT_0f, C_MIN_REF_RATE_MANT_1f, 23684 C_MIN_REF_RATE_MANT_2f, C_MIN_REF_RATE_MANT_3f 23685 }; 23686 switch(level){ 23687 case _SOC_KT2_COSQ_NODE_LVL_L0: 23688 sal_memset(&l0_entry, 0, 23689 sizeof(lls_l0_shaper_config_c_entry_t)); 23690 SOC_IF_ERROR_RETURN 23691 (soc_mem_read(unit, LLS_L0_MIN_CONFIG_Cm, MEM_BLOCK_ALL, 23692 index, &l0_entry)); 23693 soc_mem_field32_set(unit, LLS_L0_MIN_CONFIG_Cm , &l0_entry, 23694 C_MIN_REF_RATE_EXPf, 0); 23695 soc_mem_field32_set(unit, LLS_L0_MIN_CONFIG_Cm, &l0_entry, 23696 C_MIN_REF_RATE_MANTf, 0); 23697 SOC_IF_ERROR_RETURN 23698 (soc_mem_write(unit, LLS_L0_MIN_CONFIG_Cm, 23699 MEM_BLOCK_ALL, index, &l0_entry)); 23700 break; 23701 case _SOC_KT2_COSQ_NODE_LVL_L1: 23702 sal_memset(&l1_entry, 0, 23703 sizeof(lls_l1_shaper_config_c_entry_t)); 23704 idx = index % 4; 23705 SOC_IF_ERROR_RETURN 23706 (soc_mem_read(unit, LLS_L1_MIN_CONFIG_Cm, MEM_BLOCK_ALL, 23707 index/4, &l1_entry)); 23708 soc_mem_field32_set(unit, LLS_L1_MIN_CONFIG_Cm, &l1_entry, 23709 rate_exp_fields[idx], 0); 23710 soc_mem_field32_set(unit, LLS_L1_MIN_CONFIG_Cm, &l1_entry, 23711 rate_mant_fields[idx], 0); 23712 SOC_IF_ERROR_RETURN 23713 (soc_mem_write(unit, LLS_L1_MIN_CONFIG_Cm, 23714 MEM_BLOCK_ALL, index/4, &l1_entry)); 23715 break; 23716 case _SOC_KT2_COSQ_NODE_LVL_L2: 23717 if ((index % 8) < 4) { 23718 config_mem = LLS_L2_MIN_CONFIG_LOWER_Cm; 23719 } else { 23720 config_mem = LLS_L2_MIN_CONFIG_UPPER_Cm; 23721 } 23722 23723 idx = (index % 4); 23724 sal_memset(&l2_entry, 0, 23725 sizeof(lls_l2_shaper_config_lower_entry_t)); 23726 SOC_IF_ERROR_RETURN 23727 (soc_mem_read(unit, config_mem, MEM_BLOCK_ALL, 23728 index/8, &l2_entry)); 23729 soc_mem_field32_set(unit, config_mem, &l2_entry, 23730 rate_exp_fields[idx], 0); 23731 soc_mem_field32_set(unit, config_mem, &l2_entry, 23732 rate_mant_fields[idx], 0); 23733 SOC_IF_ERROR_RETURN 23734 (soc_mem_write(unit, config_mem, 23735 MEM_BLOCK_ALL, index/8, &l2_entry)); 23736 break; 23737 23738 default: 23739 break; 23740 } 23741 return SOC_E_NONE; 23742 } 23743 23744 int 23745 soc_kt2_cosq_max_bucket_set(int unit, int port, 23746 int index, uint32 level) 23747 { 23748 uint32 idx = 0; 23749 uint32 i = 0; 23750 lls_port_shaper_config_c_entry_t port_entry; 23751 lls_l0_shaper_config_c_entry_t l0_entry; 23752 lls_l1_shaper_config_c_entry_t l1_entry; 23753 lls_l2_shaper_config_lower_entry_t l2_entry; 23754 soc_mem_t config_mem[2]; 23755 lls_s0_shaper_config_c_entry_t s0_entry; 23756 23757 static const soc_field_t rate_exp_fields[] = { 23758 C_MAX_REF_RATE_EXP_0f, C_MAX_REF_RATE_EXP_1f, 23759 C_MAX_REF_RATE_EXP_2f, C_MAX_REF_RATE_EXP_3f, 23760 C_MIN_REF_RATE_EXP_0f, C_MIN_REF_RATE_EXP_1f, 23761 C_MIN_REF_RATE_EXP_2f, C_MIN_REF_RATE_EXP_3f 23762 }; 23763 static const soc_field_t rate_mant_fields[] = { 23764 C_MAX_REF_RATE_MANT_0f, C_MAX_REF_RATE_MANT_1f, 23765 C_MAX_REF_RATE_MANT_2f, C_MAX_REF_RATE_MANT_3f, 23766 C_MIN_REF_RATE_MANT_0f, C_MIN_REF_RATE_MANT_1f, 23767 C_MIN_REF_RATE_MANT_2f, C_MIN_REF_RATE_MANT_3f 23768 }; 23769 static const soc_field_t burst_exp_fields[] = { 23770 C_MAX_THLD_EXP_0f, C_MAX_THLD_EXP_1f, 23771 C_MAX_THLD_EXP_2f, C_MAX_THLD_EXP_3f, 23772 C_MIN_THLD_EXP_0f, C_MIN_THLD_EXP_1f, 23773 C_MIN_THLD_EXP_2f, C_MIN_THLD_EXP_3f 23774 }; 23775 static const soc_field_t burst_mant_fields[] = { 23776 C_MAX_THLD_MANT_0f, C_MAX_THLD_MANT_1f, 23777 C_MAX_THLD_MANT_2f, C_MAX_THLD_MANT_3f, 23778 C_MIN_THLD_MANT_0f, C_MIN_THLD_MANT_1f, 23779 C_MIN_THLD_MANT_2f, C_MIN_THLD_MANT_3f 23780 }; 23781 static const soc_field_t cycle_sel_fields[] = { 23782 C_MAX_CYCLE_SEL_0f, C_MAX_CYCLE_SEL_1f, 23783 C_MAX_CYCLE_SEL_2f, C_MAX_CYCLE_SEL_3f, 23784 C_MIN_CYCLE_SEL_0f, C_MIN_CYCLE_SEL_1f, 23785 C_MIN_CYCLE_SEL_2f, C_MIN_CYCLE_SEL_3f 23786 }; 23787 23788 soc_field_t rate_exp_f[] = { 23789 C_MAX_REF_RATE_EXPf, C_MIN_REF_RATE_EXPf 23790 }; 23791 soc_field_t rate_mant_f[] = { 23792 C_MAX_REF_RATE_MANTf, C_MIN_REF_RATE_MANTf 23793 }; 23794 soc_field_t burst_exp_f[] = { 23795 C_MAX_THLD_EXPf, C_MIN_THLD_EXPf 23796 }; 23797 soc_field_t burst_mant_f[] = { 23798 C_MAX_THLD_MANTf, C_MIN_THLD_MANTf 23799 }; 23800 soc_field_t cycle_sel_f[] = { 23801 C_MAX_CYCLE_SELf, C_MIN_CYCLE_SELf 23802 }; 23803 23804 /* set Min/Max threshold shapers to 33Gbps */ 23805 switch (level) { 23806 case _SOC_KT2_COSQ_NODE_LVL_ROOT: 23807 config_mem[0] = LLS_PORT_SHAPER_CONFIG_Cm; 23808 23809 sal_memset(&port_entry, 0, 23810 sizeof(lls_port_shaper_config_c_entry_t)); 23811 SOC_IF_ERROR_RETURN 23812 (soc_mem_read(unit, config_mem[0], MEM_BLOCK_ALL, 23813 index, &port_entry)); 23814 soc_mem_field32_set(unit, config_mem[0], &port_entry, 23815 rate_exp_f[0], 23816 KT2_QUEUE_FLUSH_RATE_EXP); 23817 soc_mem_field32_set(unit, config_mem[0], &port_entry, 23818 rate_mant_f[0], 23819 KT2_QUEUE_FLUSH_RATE_MANTISSA); 23820 soc_mem_field32_set(unit, config_mem[0], &port_entry, 23821 burst_exp_f[0], 23822 KT2_QUEUE_FLUSH_BURST_EXP); 23823 soc_mem_field32_set(unit, config_mem[0], &port_entry, 23824 burst_mant_f[0], 23825 KT2_QUEUE_FLUSH_BURST_MANTISSA); 23826 soc_mem_field32_set(unit, config_mem[0], &port_entry, 23827 cycle_sel_f[0], 23828 KT2_QUEUE_FLUSH_CYCLE_SEL); 23829 SOC_IF_ERROR_RETURN 23830 (soc_mem_write(unit, config_mem[0], 23831 MEM_BLOCK_ALL, index, &port_entry)); 23832 break; 23833 case _SOC_KT2_COSQ_NODE_LVL_S0: 23834 case _SOC_KT2_COSQ_NODE_LVL_S1: 23835 config_mem[0] = (level ==_SOC_KT2_COSQ_NODE_LVL_S0) ? 23836 LLS_S0_SHAPER_CONFIG_Cm : 23837 LLS_S1_SHAPER_CONFIG_Cm; 23838 SOC_IF_ERROR_RETURN 23839 (soc_mem_read(unit, config_mem[0], MEM_BLOCK_ALL, 23840 index, &s0_entry)); 23841 soc_mem_field32_set(unit, config_mem[0], &s0_entry, 23842 rate_exp_f[0], KT2_QUEUE_FLUSH_RATE_EXP); 23843 soc_mem_field32_set(unit, config_mem[0], &s0_entry, 23844 rate_mant_f[0], KT2_QUEUE_FLUSH_RATE_MANTISSA); 23845 soc_mem_field32_set(unit, config_mem[0], &s0_entry, 23846 burst_exp_f[0], KT2_QUEUE_FLUSH_BURST_EXP); 23847 soc_mem_field32_set(unit, config_mem[0], &s0_entry, 23848 burst_mant_f[0], KT2_QUEUE_FLUSH_BURST_MANTISSA); 23849 soc_mem_field32_set(unit, config_mem[0], &s0_entry, 23850 cycle_sel_f[0], KT2_QUEUE_FLUSH_CYCLE_SEL); 23851 SOC_IF_ERROR_RETURN 23852 (soc_mem_write(unit, config_mem[0], 23853 MEM_BLOCK_ALL, index, &s0_entry)); 23854 break; 23855 case _SOC_KT2_COSQ_NODE_LVL_L0: 23856 config_mem[0] = LLS_L0_SHAPER_CONFIG_Cm; 23857 config_mem[1] = LLS_L0_MIN_CONFIG_Cm; 23858 23859 for (i = 0; i < 2; i++) { 23860 sal_memset(&l0_entry, 0, 23861 sizeof(lls_l0_shaper_config_c_entry_t)); 23862 SOC_IF_ERROR_RETURN 23863 (soc_mem_read(unit, config_mem[i], MEM_BLOCK_ALL, 23864 index, &l0_entry)); 23865 soc_mem_field32_set(unit, config_mem[i], &l0_entry, 23866 rate_exp_f[i], 23867 KT2_QUEUE_FLUSH_RATE_EXP); 23868 soc_mem_field32_set(unit, config_mem[i], &l0_entry, 23869 rate_mant_f[i], 23870 KT2_QUEUE_FLUSH_RATE_MANTISSA); 23871 soc_mem_field32_set(unit, config_mem[i], &l0_entry, 23872 burst_exp_f[i], 23873 KT2_QUEUE_FLUSH_BURST_EXP); 23874 soc_mem_field32_set(unit, config_mem[i], &l0_entry, 23875 burst_mant_f[i], 23876 KT2_QUEUE_FLUSH_BURST_MANTISSA); 23877 soc_mem_field32_set(unit, config_mem[i], &l0_entry, 23878 cycle_sel_f[i], 23879 KT2_QUEUE_FLUSH_CYCLE_SEL); 23880 SOC_IF_ERROR_RETURN 23881 (soc_mem_write(unit, config_mem[i], 23882 MEM_BLOCK_ALL, index, &l0_entry)); 23883 } 23884 break; 23885 case _SOC_KT2_COSQ_NODE_LVL_L1: 23886 config_mem[0] = LLS_L1_SHAPER_CONFIG_Cm; 23887 config_mem[1] = LLS_L1_MIN_CONFIG_Cm; 23888 23889 for (i = 0; i < 2; i++) { 23890 sal_memset(&l1_entry, 0, 23891 sizeof(lls_l1_shaper_config_c_entry_t)); 23892 idx = (i * 4) + (index % 4); 23893 SOC_IF_ERROR_RETURN 23894 (soc_mem_read(unit, config_mem[i], MEM_BLOCK_ALL, 23895 index/4, &l1_entry)); 23896 soc_mem_field32_set(unit, config_mem[i], &l1_entry, 23897 rate_exp_fields[idx], 23898 KT2_QUEUE_FLUSH_RATE_EXP); 23899 soc_mem_field32_set(unit, config_mem[i], &l1_entry, 23900 rate_mant_fields[idx], 23901 KT2_QUEUE_FLUSH_RATE_MANTISSA); 23902 soc_mem_field32_set(unit, config_mem[i], &l1_entry, 23903 burst_exp_fields[idx], 23904 KT2_QUEUE_FLUSH_BURST_EXP); 23905 soc_mem_field32_set(unit, config_mem[i], &l1_entry, 23906 burst_mant_fields[idx], 23907 KT2_QUEUE_FLUSH_BURST_MANTISSA); 23908 soc_mem_field32_set(unit, config_mem[i], &l1_entry, 23909 cycle_sel_fields[idx], 23910 KT2_QUEUE_FLUSH_CYCLE_SEL); 23911 SOC_IF_ERROR_RETURN 23912 (soc_mem_write(unit, config_mem[i], 23913 MEM_BLOCK_ALL, index/4, &l1_entry)); 23914 } 23915 break; 23916 case _SOC_KT2_COSQ_NODE_LVL_L2: 23917 if ((index % 8) < 4) { 23918 config_mem[0] = LLS_L2_SHAPER_CONFIG_LOWERm; 23919 config_mem[1] = LLS_L2_MIN_CONFIG_LOWER_Cm; 23920 } else { 23921 config_mem[0] = LLS_L2_SHAPER_CONFIG_UPPERm; 23922 config_mem[1] = LLS_L2_MIN_CONFIG_UPPER_Cm; 23923 } 23924 23925 for ( i = 0; i < 2; i++) { 23926 idx = (i * 4) + (index % 4); 23927 23928 sal_memset(&l2_entry, 0, 23929 sizeof(lls_l2_shaper_config_lower_entry_t)); 23930 SOC_IF_ERROR_RETURN 23931 (soc_mem_read(unit, config_mem[i], MEM_BLOCK_ALL, 23932 index/8, &l2_entry)); 23933 soc_mem_field32_set(unit, config_mem[i], &l2_entry, 23934 rate_exp_fields[idx], 23935 KT2_QUEUE_FLUSH_RATE_EXP); 23936 soc_mem_field32_set(unit, config_mem[i], &l2_entry, 23937 rate_mant_fields[idx], 23938 KT2_QUEUE_FLUSH_RATE_MANTISSA); 23939 soc_mem_field32_set(unit, config_mem[i], &l2_entry, 23940 burst_exp_fields[idx], 23941 KT2_QUEUE_FLUSH_BURST_EXP); 23942 soc_mem_field32_set(unit, config_mem[i], &l2_entry, 23943 burst_mant_fields[idx], 23944 KT2_QUEUE_FLUSH_BURST_MANTISSA); 23945 soc_mem_field32_set(unit, config_mem[i], &l2_entry, 23946 cycle_sel_fields[idx], 23947 KT2_QUEUE_FLUSH_CYCLE_SEL); 23948 SOC_IF_ERROR_RETURN 23949 (soc_mem_write(unit, config_mem[i], 23950 MEM_BLOCK_ALL, index/8, &l2_entry)); 23951 } 23952 break; 23953 default: 23954 return SOC_E_NONE; 23955 } 23956 23957 return SOC_E_NONE; 23958 23959 } 23960 23961 int 23962 soc_kt2_cosq_min_bucket_set(int unit, int port, 23963 int index, uint32 level) 23964 { 23965 uint32 idx = 0; 23966 uint32 i = 0; 23967 lls_port_shaper_config_c_entry_t port_entry; 23968 lls_l0_shaper_config_c_entry_t l0_entry; 23969 lls_l1_shaper_config_c_entry_t l1_entry; 23970 lls_l2_shaper_config_lower_entry_t l2_entry; 23971 soc_mem_t config_mem[2]; 23972 lls_s0_shaper_config_c_entry_t s0_entry; 23973 23974 static const soc_field_t rate_exp_fields[] = { 23975 C_MAX_REF_RATE_EXP_0f, C_MAX_REF_RATE_EXP_1f, 23976 C_MAX_REF_RATE_EXP_2f, C_MAX_REF_RATE_EXP_3f, 23977 C_MIN_REF_RATE_EXP_0f, C_MIN_REF_RATE_EXP_1f, 23978 C_MIN_REF_RATE_EXP_2f, C_MIN_REF_RATE_EXP_3f 23979 }; 23980 static const soc_field_t rate_mant_fields[] = { 23981 C_MAX_REF_RATE_MANT_0f, C_MAX_REF_RATE_MANT_1f, 23982 C_MAX_REF_RATE_MANT_2f, C_MAX_REF_RATE_MANT_3f, 23983 C_MIN_REF_RATE_MANT_0f, C_MIN_REF_RATE_MANT_1f, 23984 C_MIN_REF_RATE_MANT_2f, C_MIN_REF_RATE_MANT_3f 23985 }; 23986 static const soc_field_t burst_exp_fields[] = { 23987 C_MAX_THLD_EXP_0f, C_MAX_THLD_EXP_1f, 23988 C_MAX_THLD_EXP_2f, C_MAX_THLD_EXP_3f, 23989 C_MIN_THLD_EXP_0f, C_MIN_THLD_EXP_1f, 23990 C_MIN_THLD_EXP_2f, C_MIN_THLD_EXP_3f 23991 }; 23992 static const soc_field_t burst_mant_fields[] = { 23993 C_MAX_THLD_MANT_0f, C_MAX_THLD_MANT_1f, 23994 C_MAX_THLD_MANT_2f, C_MAX_THLD_MANT_3f, 23995 C_MIN_THLD_MANT_0f, C_MIN_THLD_MANT_1f, 23996 C_MIN_THLD_MANT_2f, C_MIN_THLD_MANT_3f 23997 }; 23998 static const soc_field_t cycle_sel_fields[] = { 23999 C_MAX_CYCLE_SEL_0f, C_MAX_CYCLE_SEL_1f, 24000 C_MAX_CYCLE_SEL_2f, C_MAX_CYCLE_SEL_3f, 24001 C_MIN_CYCLE_SEL_0f, C_MIN_CYCLE_SEL_1f, 24002 C_MIN_CYCLE_SEL_2f, C_MIN_CYCLE_SEL_3f 24003 }; 24004 24005 soc_field_t rate_exp_f[] = { 24006 C_MAX_REF_RATE_EXPf, C_MIN_REF_RATE_EXPf 24007 }; 24008 soc_field_t rate_mant_f[] = { 24009 C_MAX_REF_RATE_MANTf, C_MIN_REF_RATE_MANTf 24010 }; 24011 soc_field_t burst_exp_f[] = { 24012 C_MAX_THLD_EXPf, C_MIN_THLD_EXPf 24013 }; 24014 soc_field_t burst_mant_f[] = { 24015 C_MAX_THLD_MANTf, C_MIN_THLD_MANTf 24016 }; 24017 soc_field_t cycle_sel_f[] = { 24018 C_MAX_CYCLE_SELf, C_MIN_CYCLE_SELf 24019 }; 24020 24021 /* set Min/Max threshold shapers to 33Gbps */ 24022 switch (level) { 24023 case _SOC_KT2_COSQ_NODE_LVL_ROOT: 24024 config_mem[0] = LLS_PORT_SHAPER_CONFIG_Cm; 24025 24026 sal_memset(&port_entry, 0, 24027 sizeof(lls_port_shaper_config_c_entry_t)); 24028 SOC_IF_ERROR_RETURN 24029 (soc_mem_read(unit, config_mem[0], MEM_BLOCK_ALL, 24030 index, &port_entry)); 24031 soc_mem_field32_set(unit, config_mem[0], &port_entry, 24032 rate_exp_f[0], 24033 KT2_QUEUE_MIN_RATE_EXP); 24034 soc_mem_field32_set(unit, config_mem[0], &port_entry, 24035 rate_mant_f[0], 24036 KT2_QUEUE_MIN_RATE_MANTISSA); 24037 soc_mem_field32_set(unit, config_mem[0], &port_entry, 24038 burst_exp_f[0], 24039 KT2_QUEUE_MIN_BURST_EXP); 24040 soc_mem_field32_set(unit, config_mem[0], &port_entry, 24041 burst_mant_f[0], 24042 KT2_QUEUE_MIN_BURST_MANTISSA); 24043 soc_mem_field32_set(unit, config_mem[0], &port_entry, 24044 cycle_sel_f[0], 24045 KT2_QUEUE_MIN_CYCLE_SEL); 24046 SOC_IF_ERROR_RETURN 24047 (soc_mem_write(unit, config_mem[0], 24048 MEM_BLOCK_ALL, index, &port_entry)); 24049 break; 24050 case _SOC_KT2_COSQ_NODE_LVL_S0: 24051 case _SOC_KT2_COSQ_NODE_LVL_S1: 24052 config_mem[0] = (level ==_SOC_KT2_COSQ_NODE_LVL_S0) ? 24053 LLS_S0_SHAPER_CONFIG_Cm : 24054 LLS_S1_SHAPER_CONFIG_Cm; 24055 SOC_IF_ERROR_RETURN 24056 (soc_mem_read(unit, config_mem[0], MEM_BLOCK_ALL, 24057 index, &s0_entry)); 24058 soc_mem_field32_set(unit, config_mem[0], &s0_entry, 24059 rate_exp_f[0], KT2_QUEUE_MIN_RATE_EXP); 24060 soc_mem_field32_set(unit, config_mem[0], &s0_entry, 24061 rate_mant_f[0], KT2_QUEUE_MIN_RATE_MANTISSA); 24062 soc_mem_field32_set(unit, config_mem[0], &s0_entry, 24063 burst_exp_f[0], KT2_QUEUE_MIN_BURST_EXP); 24064 soc_mem_field32_set(unit, config_mem[0], &s0_entry, 24065 burst_mant_f[0], KT2_QUEUE_MIN_BURST_MANTISSA); 24066 soc_mem_field32_set(unit, config_mem[0], &s0_entry, 24067 cycle_sel_f[0], KT2_QUEUE_MIN_CYCLE_SEL); 24068 SOC_IF_ERROR_RETURN 24069 (soc_mem_write(unit, config_mem[0], 24070 MEM_BLOCK_ALL, index, &s0_entry)); 24071 break; 24072 case _SOC_KT2_COSQ_NODE_LVL_L0: 24073 config_mem[0] = LLS_L0_SHAPER_CONFIG_Cm; 24074 config_mem[1] = LLS_L0_MIN_CONFIG_Cm; 24075 24076 for (i = 0; i < 2; i++) { 24077 sal_memset(&l0_entry, 0, 24078 sizeof(lls_l0_shaper_config_c_entry_t)); 24079 SOC_IF_ERROR_RETURN 24080 (soc_mem_read(unit, config_mem[i], MEM_BLOCK_ALL, 24081 index, &l0_entry)); 24082 soc_mem_field32_set(unit, config_mem[i], &l0_entry, 24083 rate_exp_f[i], 24084 KT2_QUEUE_MIN_RATE_EXP); 24085 soc_mem_field32_set(unit, config_mem[i], &l0_entry, 24086 rate_mant_f[i], 24087 KT2_QUEUE_MIN_RATE_MANTISSA); 24088 soc_mem_field32_set(unit, config_mem[i], &l0_entry, 24089 burst_exp_f[i], 24090 KT2_QUEUE_MIN_BURST_EXP); 24091 soc_mem_field32_set(unit, config_mem[i], &l0_entry, 24092 burst_mant_f[i], 24093 KT2_QUEUE_MIN_BURST_MANTISSA); 24094 soc_mem_field32_set(unit, config_mem[i], &l0_entry, 24095 cycle_sel_f[i], 24096 KT2_QUEUE_MIN_CYCLE_SEL); 24097 SOC_IF_ERROR_RETURN 24098 (soc_mem_write(unit, config_mem[i], 24099 MEM_BLOCK_ALL, index, &l0_entry)); 24100 } 24101 break; 24102 case _SOC_KT2_COSQ_NODE_LVL_L1: 24103 config_mem[0] = LLS_L1_SHAPER_CONFIG_Cm; 24104 config_mem[1] = LLS_L1_MIN_CONFIG_Cm; 24105 24106 for (i = 0; i < 2; i++) { 24107 sal_memset(&l1_entry, 0, 24108 sizeof(lls_l1_shaper_config_c_entry_t)); 24109 idx = (i * 4) + (index % 4); 24110 SOC_IF_ERROR_RETURN 24111 (soc_mem_read(unit, config_mem[i], MEM_BLOCK_ALL, 24112 index/4, &l1_entry)); 24113 soc_mem_field32_set(unit, config_mem[i], &l1_entry, 24114 rate_exp_fields[idx], 24115 KT2_QUEUE_MIN_RATE_EXP); 24116 soc_mem_field32_set(unit, config_mem[i], &l1_entry, 24117 rate_mant_fields[idx], 24118 KT2_QUEUE_MIN_RATE_MANTISSA); 24119 soc_mem_field32_set(unit, config_mem[i], &l1_entry, 24120 burst_exp_fields[idx], 24121 KT2_QUEUE_MIN_BURST_EXP); 24122 soc_mem_field32_set(unit, config_mem[i], &l1_entry, 24123 burst_mant_fields[idx], 24124 KT2_QUEUE_MIN_BURST_MANTISSA); 24125 soc_mem_field32_set(unit, config_mem[i], &l1_entry, 24126 cycle_sel_fields[idx], 24127 KT2_QUEUE_MIN_CYCLE_SEL); 24128 SOC_IF_ERROR_RETURN 24129 (soc_mem_write(unit, config_mem[i], 24130 MEM_BLOCK_ALL, index/4, &l1_entry)); 24131 } 24132 break; 24133 case _SOC_KT2_COSQ_NODE_LVL_L2: 24134 if ((index % 8) < 4) { 24135 config_mem[0] = LLS_L2_SHAPER_CONFIG_LOWERm; 24136 config_mem[1] = LLS_L2_MIN_CONFIG_LOWER_Cm; 24137 } else { 24138 config_mem[0] = LLS_L2_SHAPER_CONFIG_UPPERm; 24139 config_mem[1] = LLS_L2_MIN_CONFIG_UPPER_Cm; 24140 } 24141 24142 for ( i = 0; i < 2; i++) { 24143 idx = (i * 4) + (index % 4); 24144 24145 sal_memset(&l2_entry, 0, 24146 sizeof(lls_l2_shaper_config_lower_entry_t)); 24147 SOC_IF_ERROR_RETURN 24148 (soc_mem_read(unit, config_mem[i], MEM_BLOCK_ALL, 24149 index/8, &l2_entry)); 24150 soc_mem_field32_set(unit, config_mem[i], &l2_entry, 24151 rate_exp_fields[idx], 24152 KT2_QUEUE_MIN_RATE_EXP); 24153 soc_mem_field32_set(unit, config_mem[i], &l2_entry, 24154 rate_mant_fields[idx], 24155 KT2_QUEUE_MIN_RATE_MANTISSA); 24156 soc_mem_field32_set(unit, config_mem[i], &l2_entry, 24157 burst_exp_fields[idx], 24158 KT2_QUEUE_MIN_BURST_EXP); 24159 soc_mem_field32_set(unit, config_mem[i], &l2_entry, 24160 burst_mant_fields[idx], 24161 KT2_QUEUE_MIN_BURST_MANTISSA); 24162 soc_mem_field32_set(unit, config_mem[i], &l2_entry, 24163 cycle_sel_fields[idx], 24164 KT2_QUEUE_MIN_CYCLE_SEL); 24165 SOC_IF_ERROR_RETURN 24166 (soc_mem_write(unit, config_mem[i], 24167 MEM_BLOCK_ALL, index/8, &l2_entry)); 24168 } 24169 break; 24170 default: 24171 return SOC_E_NONE; 24172 } 24173 24174 return SOC_E_NONE; 24175 24176 } 24177 24178 STATIC 24179 int _soc_kt2_is_bit64_set(uint64 dst, int n) 24180 { 24181 uint64 temp64; 24182 COMPILER_64_SET(temp64, 0, 1); 24183 COMPILER_64_SHL(temp64, n); 24184 COMPILER_64_AND(temp64, dst); 24185 return (!COMPILER_64_IS_ZERO(temp64)); 24186 } 24187 STATIC 24188 int _soc_kt2_dfc_status_get(int unit, int port, int hw_index, 24189 int *dfc_restore_needed, 24190 int *sid) 24191 { 24192 soc_pbmp_t pbmp_linkphy; 24193 soc_reg_t reg_dfc; 24194 uint64 rval_dfc, data_dfc; 24195 int stream_id; 24196 egr_queue_to_pp_port_map_entry_t pp_port_map; 24197 24198 /* Check if port is not linkphy then return */ 24199 pbmp_linkphy = soc_property_get_pbmp(unit, spn_PBMP_LINKPHY, 0); 24200 24201 if (!SOC_PBMP_MEMBER(pbmp_linkphy, port)) { 24202 return SOC_E_NONE; 24203 } 24204 SOC_IF_ERROR_RETURN(READ_EGR_QUEUE_TO_PP_PORT_MAPm(unit, MEM_BLOCK_ALL, 24205 hw_index, 24206 &pp_port_map)); 24207 stream_id = soc_mem_field32_get(unit, EGR_QUEUE_TO_PP_PORT_MAPm, 24208 &pp_port_map, DEVICE_STREAM_IDf); 24209 stream_id = stream_id % 128; 24210 *sid = stream_id; 24211 if (stream_id < 64) { 24212 reg_dfc = RXLP_DFC_STATUS_LOr; 24213 } else { 24214 reg_dfc = RXLP_DFC_STATUS_HIr; 24215 stream_id = stream_id % 64; 24216 } 24217 24218 SOC_IF_ERROR_RETURN( 24219 soc_reg_get(unit, reg_dfc, port, 0, &rval_dfc)); 24220 data_dfc = soc_reg64_field_get(unit, reg_dfc, rval_dfc, DFC_STATUSf); 24221 if (!_soc_kt2_is_bit64_set(data_dfc, stream_id)) { 24222 return SOC_E_NONE; 24223 } 24224 *dfc_restore_needed = 1; 24225 return SOC_E_NONE; 24226 } 24227 24228 24229 int _soc_kt2_dfc_status_clear(int unit, int port, int stream_id) 24230 { 24231 soc_reg_t reg_dfc, reg_cpu; 24232 uint64 rval_dfc, rval_cpu, rval_cpu_save, data_dfc, data_cpu; 24233 24234 if (stream_id < 64) { 24235 reg_dfc = RXLP_DFC_STATUS_LOr; 24236 reg_cpu = RXLP_DFC_STATUS_CPU_UPDATE_ENABLE_LOr; 24237 } else { 24238 reg_dfc = RXLP_DFC_STATUS_HIr; 24239 reg_cpu = RXLP_DFC_STATUS_CPU_UPDATE_ENABLE_HIr; 24240 stream_id = stream_id % 64; 24241 } 24242 24243 SOC_IF_ERROR_RETURN( 24244 soc_reg_get(unit, reg_dfc, port, 0, &rval_dfc)); 24245 data_dfc = soc_reg64_field_get(unit, reg_dfc, rval_dfc, DFC_STATUSf); 24246 COMPILER_64_BITCLR(data_dfc, stream_id); 24247 24248 SOC_IF_ERROR_RETURN( 24249 soc_reg_get(unit,reg_cpu, port, 0, &rval_cpu)); 24250 rval_cpu_save = rval_cpu; 24251 data_cpu = soc_reg64_field_get(unit, reg_cpu, rval_cpu, DFC_STATUS_CPU_WRITE_ENf); 24252 COMPILER_64_BITSET(data_cpu, stream_id); 24253 soc_reg64_field_set(unit, reg_cpu, &rval_cpu, DFC_STATUS_CPU_WRITE_ENf, data_cpu); 24254 SOC_IF_ERROR_RETURN( 24255 soc_reg_set(unit, reg_cpu, port, 0, rval_cpu)); 24256 24257 WRITE_RXLP_DFC_CPU_UPDATE_REFRESHr(unit, port, 1); 24258 24259 soc_reg64_field_set(unit, reg_dfc, &rval_dfc, DFC_STATUSf, data_dfc); 24260 SOC_IF_ERROR_RETURN( 24261 soc_reg_set(unit, reg_dfc, port, 0, rval_dfc)); 24262 24263 SOC_IF_ERROR_RETURN( 24264 soc_reg_set(unit,reg_cpu, port, 0, rval_cpu_save)); 24265 24266 return SOC_E_NONE; 24267 24268 } 24269 24270 STATIC 24271 int _soc_kt2_dfc_status_set(int unit, int port, int stream_id) 24272 { 24273 soc_reg_t reg_dfc, reg_cpu; 24274 uint64 rval_dfc, rval_cpu, rval_cpu_save, data_dfc, data_cpu; 24275 24276 if (stream_id < 64) { 24277 reg_dfc = RXLP_DFC_STATUS_LOr; 24278 reg_cpu = RXLP_DFC_STATUS_CPU_UPDATE_ENABLE_LOr; 24279 } else { 24280 reg_dfc = RXLP_DFC_STATUS_HIr; 24281 reg_cpu = RXLP_DFC_STATUS_CPU_UPDATE_ENABLE_HIr; 24282 stream_id = stream_id % 64; 24283 } 24284 24285 SOC_IF_ERROR_RETURN( 24286 soc_reg_get(unit, reg_dfc, port, 0, &rval_dfc)); 24287 data_dfc = soc_reg64_field_get(unit, reg_dfc, rval_dfc, DFC_STATUSf); 24288 COMPILER_64_BITSET(data_dfc, stream_id); 24289 SOC_IF_ERROR_RETURN( 24290 soc_reg_get(unit,reg_cpu, port, 0, &rval_cpu)); 24291 rval_cpu_save = rval_cpu; 24292 data_cpu = soc_reg64_field_get(unit, reg_cpu, rval_cpu, DFC_STATUS_CPU_WRITE_ENf); 24293 COMPILER_64_BITSET(data_cpu, stream_id); 24294 soc_reg64_field_set(unit, reg_cpu, &rval_cpu, DFC_STATUS_CPU_WRITE_ENf, data_cpu); 24295 SOC_IF_ERROR_RETURN( 24296 soc_reg_set(unit, reg_cpu, port, 0, rval_cpu)); 24297 WRITE_RXLP_DFC_CPU_UPDATE_REFRESHr(unit, port, 1); 24298 soc_reg64_field_set(unit, reg_dfc, &rval_dfc, DFC_STATUSf, data_dfc); 24299 SOC_IF_ERROR_RETURN( 24300 soc_reg_set(unit, reg_dfc, port, 0, rval_dfc)); 24301 SOC_IF_ERROR_RETURN( 24302 soc_reg_set(unit,reg_cpu, port, 0, rval_cpu_save)); 24303 24304 return SOC_E_NONE; 24305 24306 } 24307 STATIC 24308 int _soc_kt2_cosq_pp_port_and_s1_index_get(int unit, 24309 int queue_id, 24310 int *pp_port, 24311 int *s1_index) 24312 { 24313 lls_l0_parent_entry_t l0_parent; 24314 lls_l1_parent_entry_t l1_parent; 24315 lls_l2_parent_entry_t l2_parent; 24316 egr_queue_to_pp_port_map_entry_t pp_port_map; 24317 int index; 24318 int ctype; 24319 24320 24321 SOC_IF_ERROR_RETURN 24322 (READ_LLS_L2_PARENTm(unit, MEM_BLOCK_ALL, queue_id, &l2_parent)); 24323 index = soc_mem_field32_get(unit, LLS_L2_PARENTm, &l2_parent, C_PARENTf); 24324 24325 SOC_IF_ERROR_RETURN 24326 (READ_LLS_L1_PARENTm(unit, MEM_BLOCK_ALL, index, &l1_parent)); 24327 index = soc_mem_field32_get(unit, LLS_L1_PARENTm, &l1_parent, C_PARENTf); 24328 24329 SOC_IF_ERROR_RETURN 24330 (READ_LLS_L0_PARENTm(unit, MEM_BLOCK_ALL, index, &l0_parent)); 24331 24332 /* 24333 * Ctype 1 indicates parent is a port, 0 indicates parent is an s1. 24334 */ 24335 ctype = soc_mem_field32_get(unit, LLS_L0_PARENTm, &l0_parent, C_TYPEf);; 24336 if (!ctype) { 24337 if (s1_index != NULL) { 24338 *s1_index = soc_mem_field32_get(unit, LLS_L0_PARENTm, 24339 &l0_parent, C_PARENTf); 24340 } 24341 if (pp_port != NULL) { 24342 SOC_IF_ERROR_RETURN 24343 (READ_EGR_QUEUE_TO_PP_PORT_MAPm(unit, MEM_BLOCK_ALL, 24344 queue_id, &pp_port_map)); 24345 *pp_port = soc_mem_field32_get(unit, EGR_QUEUE_TO_PP_PORT_MAPm, 24346 &pp_port_map, PP_PORTf); 24347 } 24348 } 24349 return SOC_E_NONE; 24350 24351 } 24352 STATIC 24353 int _soc_kt2_coe_pause_status_get(int unit, int port, int hw_index, 24354 int *coe_pause_restore_needed) 24355 { 24356 soc_pbmp_t pbmp_linkphy, pbmp_coe; 24357 24358 /* Check if port is not coe then return */ 24359 pbmp_coe = soc_property_get_pbmp(unit, spn_PBMP_SUBPORT, 0); 24360 24361 if (!SOC_PBMP_MEMBER(pbmp_coe, port)) { 24362 return SOC_E_NONE; 24363 } 24364 24365 /* Check if port is linkphy then return */ 24366 pbmp_linkphy = soc_property_get_pbmp(unit, spn_PBMP_LINKPHY, 0); 24367 24368 if (SOC_PBMP_MEMBER(pbmp_linkphy, port)) { 24369 return SOC_E_NONE; 24370 } 24371 #ifdef BCM_SABER2_SUPPORT 24372 if (SOC_IS_SABER2(unit)) { 24373 *coe_pause_restore_needed = 1; 24374 } 24375 #endif 24376 return SOC_E_NONE; 24377 } 24378 #define KT2_LLS_CLEAR_CREDIT_COE_BASE 64 24379 #define KT2_LLS_CLEAR_CREDIT_MAX_S1 64 24380 STATIC 24381 int _soc_kt2_coe_pause_status_clear(int unit, int hw_index) 24382 { 24383 uint32 rval; 24384 mmu_enq_src_ppp_to_s1_lookup_entry_t ppp_to_s1; 24385 int pp_port = -1, s1_index = -1, max_count; 24386 24387 SOC_IF_ERROR_RETURN( 24388 _soc_kt2_cosq_pp_port_and_s1_index_get(unit, hw_index, &pp_port, &s1_index)); 24389 max_count = soc_mem_index_count(unit, MMU_ENQ_SRC_PPP_TO_S1_LOOKUPm); 24390 if ((pp_port < 0) || (pp_port >= max_count)) { 24391 return SOC_E_NONE; 24392 } 24393 if ((s1_index < 0) || (s1_index >= KT2_LLS_CLEAR_CREDIT_MAX_S1)) { 24394 return SOC_E_NONE; 24395 } 24396 /*clear channel mapping */ 24397 memset(&ppp_to_s1, 0, sizeof(ppp_to_s1)); 24398 SOC_IF_ERROR_RETURN( 24399 READ_MMU_ENQ_SRC_PPP_TO_S1_LOOKUPm(unit, MEM_BLOCK_ALL, 24400 pp_port, &ppp_to_s1)); 24401 soc_mem_field32_set(unit, MMU_ENQ_SRC_PPP_TO_S1_LOOKUPm, 24402 &ppp_to_s1, S1_VLDf, 0); 24403 SOC_IF_ERROR_RETURN( 24404 WRITE_MMU_ENQ_SRC_PPP_TO_S1_LOOKUPm(unit, 24405 MEM_BLOCK_ALL, 24406 pp_port, &ppp_to_s1)); 24407 /* Clear coe pause */ 24408 SOC_IF_ERROR_RETURN( 24409 READ_LLS_CLEAR_S1_CREDITSr(unit, &rval)); 24410 soc_reg_field_set(unit, LLS_CLEAR_S1_CREDITSr, &rval, VALIDf, 1); 24411 soc_reg_field_set(unit, LLS_CLEAR_S1_CREDITSr, &rval, ADDRESSf, 24412 KT2_LLS_CLEAR_CREDIT_COE_BASE + s1_index); 24413 SOC_IF_ERROR_RETURN( 24414 WRITE_LLS_CLEAR_S1_CREDITSr(unit, rval)); 24415 return SOC_E_NONE; 24416 24417 } 24418 24419 STATIC 24420 int _soc_kt2_coe_pause_status_set(int unit, int hw_index) 24421 { 24422 mmu_enq_src_ppp_to_s1_lookup_entry_t ppp_to_s1; 24423 int pp_port, max_count; 24424 24425 SOC_IF_ERROR_RETURN( 24426 _soc_kt2_cosq_pp_port_and_s1_index_get(unit, hw_index, &pp_port, NULL)); 24427 max_count = soc_mem_index_count(unit, MMU_ENQ_SRC_PPP_TO_S1_LOOKUPm); 24428 if ((pp_port < 0) || (pp_port >= max_count)) { 24429 return SOC_E_NONE; 24430 } 24431 /*set channel mapping */ 24432 memset(&ppp_to_s1, 0, sizeof(ppp_to_s1)); 24433 SOC_IF_ERROR_RETURN( 24434 READ_MMU_ENQ_SRC_PPP_TO_S1_LOOKUPm(unit, MEM_BLOCK_ALL, 24435 pp_port, &ppp_to_s1)); 24436 soc_mem_field32_set(unit, MMU_ENQ_SRC_PPP_TO_S1_LOOKUPm, 24437 &ppp_to_s1, S1_VLDf, 1); 24438 SOC_IF_ERROR_RETURN( 24439 WRITE_MMU_ENQ_SRC_PPP_TO_S1_LOOKUPm(unit, 24440 MEM_BLOCK_ALL, 24441 pp_port, &ppp_to_s1)); 24442 return SOC_E_NONE; 24443 24444 } 24445 24446 int 24447 _soc_kt2_cosq_begin_port_flush(int unit, int port, int hw_index) 24448 { 24449 uint32 map_entry[SOC_MAX_MEM_WORDS]; 24450 int index =0 , eindex = 0; 24451 static const soc_field_t indexf[] = { 24452 INDEX0f, INDEX1f 24453 }; 24454 int map_offset = 0, dfc_restore_needed = 0, stream_id = 0; 24455 int packing_mode = 0, coe_pause_restore_needed = 0; 24456 uint32 rval = 0; 24457 uint32 ext_mem = 0; 24458 int flush_active = 0; 24459 uint32 timeout_val; 24460 soc_timeout_t timeout; 24461 24462 if (IS_EXT_MEM_PORT(unit, port)) { 24463 ext_mem = 1; 24464 } 24465 24466 24467 if(soc_feature(unit, soc_feature_mmu_packing)) { 24468 packing_mode = soc_property_get(unit, spn_MMU_MULTI_PACKETS_PER_CELL, 0); 24469 } 24470 if (packing_mode == 1) { 24471 /* default time - packing mode 24472 */ 24473 timeout_val = soc_property_get(unit, spn_MMU_QUEUE_FLUSH_TIMEOUT, 24474 _SOC_COSQ_QUEUE_FLUSH_TIMEOUT_PACKING_DEFAULT); 24475 } else { 24476 24477 /* default time - non packing mode 24478 */ 24479 timeout_val = soc_property_get(unit, spn_MMU_QUEUE_FLUSH_TIMEOUT, 24480 _SOC_COSQ_QUEUE_FLUSH_TIMEOUT_DEFAULT); 24481 } 24482 24483 SOC_IF_ERROR_RETURN(READ_TOQ_FLUSH0r(unit, &rval)); 24484 24485 soc_reg_field_set(unit, TOQ_FLUSH0r, &rval, FLUSH_NUMf,1); 24486 soc_reg_field_set(unit, TOQ_FLUSH0r, &rval, FLUSH_ID0f, hw_index); 24487 if (soc_reg_field_valid(unit, TOQ_FLUSH0r, FLUSH_EXTERNALf)){ 24488 soc_reg_field_set(unit, TOQ_FLUSH0r, &rval, FLUSH_EXTERNALf, 24489 ext_mem); 24490 } 24491 soc_reg_field_set(unit, TOQ_FLUSH0r, &rval, FLUSH_ACTIVEf, 1); 24492 soc_reg_field_set(unit, TOQ_FLUSH0r, &rval, FLUSH_TYPEf, 0); 24493 24494 SOC_IF_ERROR_RETURN(WRITE_TOQ_FLUSH0r(unit, rval)); 24495 if (hw_index > 0) { 24496 index = hw_index / 16 ; 24497 eindex = (hw_index % 16) / 8; 24498 SOC_IF_ERROR_RETURN 24499 (soc_mem_read(unit, MMU_INTFI_FC_MAP_TBL2m, 24500 MEM_BLOCK_ALL, index, &map_entry)); 24501 map_offset = soc_mem_field32_get(unit, MMU_INTFI_FC_MAP_TBL2m, &map_entry, 24502 indexf[eindex]); 24503 if (map_offset) { 24504 soc_mem_field32_set(unit, MMU_INTFI_FC_MAP_TBL2m, &map_entry, 24505 indexf[eindex], 0); 24506 SOC_IF_ERROR_RETURN(soc_mem_write(unit, MMU_INTFI_FC_MAP_TBL2m, 24507 MEM_BLOCK_ALL, index, &map_entry)); 24508 24509 } 24510 } 24511 /* 24512 * Check if queue belongs to linkphy port and corresponding 24513 * stream (S1 node) is paused because of received DFC frame. 24514 * Then clear DFC_STATUS and save the original value to 24515 * restore it again.In similar manner clear CoE pause too. 24516 */ 24517 SOC_IF_ERROR_RETURN(_soc_kt2_dfc_status_get(unit, port, hw_index, 24518 &dfc_restore_needed, &stream_id)); 24519 if (dfc_restore_needed) { 24520 SOC_IF_ERROR_RETURN(_soc_kt2_dfc_status_clear(unit, port, 24521 stream_id)); 24522 } 24523 SOC_IF_ERROR_RETURN(_soc_kt2_coe_pause_status_get(unit, port, hw_index, 24524 &coe_pause_restore_needed)); 24525 if (coe_pause_restore_needed) { 24526 SOC_IF_ERROR_RETURN(_soc_kt2_coe_pause_status_clear(unit, hw_index)); 24527 } 24528 24529 24530 /* Wait for flush completion */ 24531 flush_active = 1; 24532 soc_timeout_init(&timeout, timeout_val, 0); 24533 24534 while (flush_active) { 24535 if (SOC_REG_IS_VALID(unit, TOQ_FLUSH0r)) { 24536 SOC_IF_ERROR_RETURN(READ_TOQ_FLUSH0r(unit, &rval)); 24537 flush_active = soc_reg_field_get(unit, TOQ_FLUSH0r, rval, 24538 FLUSH_ACTIVEf); 24539 } 24540 24541 if (soc_timeout_check(&timeout)) { 24542 LOG_ERROR(BSL_LS_SOC_COMMON, 24543 (BSL_META_U(unit, 24544 "ERROR: Port %d Queue flush operation failed for queue %d \n"), 24545 port, hw_index)); 24546 if (map_offset) { 24547 soc_mem_field32_set(unit, MMU_INTFI_FC_MAP_TBL2m, &map_entry, 24548 indexf[eindex], map_offset); 24549 SOC_IF_ERROR_RETURN(soc_mem_write(unit, MMU_INTFI_FC_MAP_TBL2m, 24550 MEM_BLOCK_ALL, index, &map_entry)); 24551 24552 } 24553 return (SOC_E_TIMEOUT); 24554 24555 } 24556 } 24557 24558 if (map_offset) { 24559 soc_mem_field32_set(unit, MMU_INTFI_FC_MAP_TBL2m, &map_entry, 24560 indexf[eindex], map_offset); 24561 SOC_IF_ERROR_RETURN(soc_mem_write(unit, MMU_INTFI_FC_MAP_TBL2m, 24562 MEM_BLOCK_ALL, index, &map_entry)); 24563 24564 } 24565 24566 if (dfc_restore_needed) { 24567 SOC_IF_ERROR_RETURN(_soc_kt2_dfc_status_set(unit, port, 24568 stream_id)); 24569 } 24570 if (coe_pause_restore_needed) { 24571 SOC_IF_ERROR_RETURN(_soc_kt2_coe_pause_status_set(unit, hw_index)); 24572 } 24573 24574 return SOC_E_NONE; 24575 } 24576 24577 int 24578 _soc_kt2_cosq_end_port_flush(int unit, int hw_index) 24579 { 24580 uint32 rval = 0, q_bmp; 24581 24582 KT2_COSQ_LOCK(unit); 24583 24584 soc_reg_field_set(unit, THDO_QUEUE_DISABLE_CFG2r, &rval, QUEUE_NUMf, 24585 (hw_index & 0xfe0)); 24586 SOC_IF_ERROR_RETURN(WRITE_THDO_QUEUE_DISABLE_CFG2r(unit, rval)); 24587 24588 SOC_IF_ERROR_RETURN(READ_THDO_QUEUE_DISABLE_CFG1r(unit, &rval)); 24589 soc_reg_field_set(unit, THDO_QUEUE_DISABLE_CFG1r, &rval, QUEUE_RDf, 1); 24590 SOC_IF_ERROR_RETURN(WRITE_THDO_QUEUE_DISABLE_CFG1r(unit, rval)); 24591 24592 SOC_IF_ERROR_RETURN(READ_THDO_QUEUE_DISABLE_STATUSr(unit, &rval)); 24593 q_bmp = soc_reg_field_get(unit, THDO_QUEUE_DISABLE_STATUSr, rval, 24594 QUEUE_BITMAPf); 24595 24596 if (q_bmp & (1 << (hw_index % 32))) { 24597 SOC_IF_ERROR_RETURN(READ_THDO_QUEUE_DISABLE_CFG2r(unit, &rval)); 24598 soc_reg_field_set(unit, THDO_QUEUE_DISABLE_CFG2r, &rval, QUEUE_NUMf, 24599 hw_index ); 24600 SOC_IF_ERROR_RETURN(WRITE_THDO_QUEUE_DISABLE_CFG2r(unit, rval)); 24601 24602 SOC_IF_ERROR_RETURN(READ_THDO_QUEUE_DISABLE_CFG1r(unit, &rval)); 24603 soc_reg_field_set(unit, THDO_QUEUE_DISABLE_CFG1r, &rval, QUEUE_WRf, 1); 24604 SOC_IF_ERROR_RETURN(WRITE_THDO_QUEUE_DISABLE_CFG1r(unit, rval)); 24605 } 24606 24607 KT2_COSQ_UNLOCK(unit); 24608 24609 return SOC_E_NONE; 24610 } 24611 24612 int 24613 soc_kt2_cosq_queue_enable(int unit, int hw_index, int enable) 24614 { 24615 uint32 rval = 0, rval1 = 0, q_bmp, disable_bit, wr_type = 0; 24616 soc_timeout_t to; 24617 sal_usecs_t timeout; 24618 24619 soc_reg_field_set(unit, THDO_QUEUE_DISABLE_CFG1r, &rval, STAT_CLRf, 1); 24620 SOC_IF_ERROR_RETURN(WRITE_THDO_QUEUE_DISABLE_CFG1r(unit, rval)); 24621 24622 rval = 0; 24623 soc_reg_field_set(unit, THDO_QUEUE_DISABLE_CFG2r, &rval, QUEUE_NUMf, 24624 hw_index); 24625 SOC_IF_ERROR_RETURN(WRITE_THDO_QUEUE_DISABLE_CFG2r(unit, rval)); 24626 24627 SOC_IF_ERROR_RETURN(READ_THDO_QUEUE_DISABLE_CFG1r(unit, &rval)); 24628 wr_type = soc_reg_field_get(unit, THDO_QUEUE_DISABLE_CFG1r, rval, QUEUE_WR_TYPEf); 24629 if (enable) { 24630 soc_reg_field_set(unit, THDO_QUEUE_DISABLE_CFG1r, &rval, QUEUE_WR_TYPEf, 0); 24631 } else { 24632 soc_reg_field_set(unit, THDO_QUEUE_DISABLE_CFG1r, &rval, QUEUE_WR_TYPEf, 1); 24633 } 24634 soc_reg_field_set(unit, THDO_QUEUE_DISABLE_CFG1r, &rval, QUEUE_WRf, 1); 24635 SOC_IF_ERROR_RETURN(WRITE_THDO_QUEUE_DISABLE_CFG1r(unit, rval)); 24636 24637 timeout = 20000; 24638 soc_timeout_init(&to, timeout, 0); 24639 do { 24640 24641 SOC_IF_ERROR_RETURN(READ_THDO_QUEUE_DISABLE_CFG1r(unit, &rval1)); 24642 soc_reg_field_set(unit, THDO_QUEUE_DISABLE_CFG1r, &rval1, QUEUE_RDf, 1); 24643 SOC_IF_ERROR_RETURN(WRITE_THDO_QUEUE_DISABLE_CFG1r(unit, rval1)); 24644 24645 SOC_IF_ERROR_RETURN(READ_THDO_QUEUE_DISABLE_STATUSr(unit, &rval1)); 24646 q_bmp = soc_reg_field_get(unit, THDO_QUEUE_DISABLE_STATUSr, rval1, 24647 QUEUE_BITMAPf); 24648 24649 disable_bit = (q_bmp & (1 << (hw_index % 32))); 24650 24651 if ((enable && !disable_bit) || 24652 (!enable && disable_bit)) { 24653 SOC_IF_ERROR_RETURN(READ_THDO_QUEUE_DISABLE_CFG1r(unit, &rval)); 24654 soc_reg_field_set(unit, THDO_QUEUE_DISABLE_CFG1r, &rval, QUEUE_WR_TYPEf, wr_type); 24655 SOC_IF_ERROR_RETURN(WRITE_THDO_QUEUE_DISABLE_CFG1r(unit, rval)); 24656 return SOC_E_NONE; 24657 } 24658 if (soc_timeout_check(&to)) { 24659 LOG_WARN(BSL_LS_SOC_COMMON, 24660 (BSL_META_U(unit, 24661 "unit %d : Queue %d enable timeout\n"), unit, hw_index)); 24662 break; 24663 } 24664 } while (TRUE); 24665 SOC_IF_ERROR_RETURN(READ_THDO_QUEUE_DISABLE_CFG1r(unit, &rval)); 24666 soc_reg_field_set(unit, THDO_QUEUE_DISABLE_CFG1r, &rval, QUEUE_WR_TYPEf, wr_type); 24667 SOC_IF_ERROR_RETURN(WRITE_THDO_QUEUE_DISABLE_CFG1r(unit, rval)); 24668 return SOC_E_TIMEOUT; 24669 } 24670 24671 soc_error_t 24672 soc_katana2_mmu_port_enable_set(int unit, soc_port_t port, int enable) 24673 { 24674 uint32 rval; 24675 uint64 rval64, p_bmp; 24676 soc_timeout_t to; 24677 sal_usecs_t timeout; 24678 24679 rval = 0; 24680 soc_reg_field_set(unit, THDO_PORT_DISABLE_CFG1r, &rval, STAT_CLRf, 1); 24681 SOC_IF_ERROR_RETURN(WRITE_THDO_PORT_DISABLE_CFG1r(unit, rval)); 24682 24683 rval = 0; 24684 COMPILER_64_ZERO(rval64); 24685 soc_reg_field_set(unit, THDO_PORT_DISABLE_CFG1r, &rval, 24686 PORT_IDf, port); 24687 24688 if (enable) { 24689 soc_reg_field_set(unit, THDO_PORT_DISABLE_CFG1r, &rval, 24690 PORT_WR_TYPEf,0); 24691 } else { 24692 soc_reg_field_set(unit, THDO_PORT_DISABLE_CFG1r, &rval, 24693 PORT_WR_TYPEf,1); 24694 } 24695 SOC_IF_ERROR_RETURN(WRITE_THDO_PORT_DISABLE_CFG1r(unit,rval)); 24696 soc_reg_field_set(unit, THDO_PORT_DISABLE_CFG1r, &rval, 24697 PORT_WRf,1); 24698 SOC_IF_ERROR_RETURN(WRITE_THDO_PORT_DISABLE_CFG1r(unit,rval)); 24699 24700 timeout = 20000; 24701 soc_timeout_init(&to, timeout, 0); 24702 do { 24703 SOC_IF_ERROR_RETURN(READ_THDO_PORT_DISABLE_CFG1r(unit, &rval)); 24704 soc_reg_field_set(unit, THDO_PORT_DISABLE_CFG1r, &rval, PORT_RDf, 1); 24705 SOC_IF_ERROR_RETURN(WRITE_THDO_PORT_DISABLE_CFG1r(unit, rval)); 24706 24707 SOC_IF_ERROR_RETURN(READ_THDO_PORT_DISABLE_STATUSr(unit, &rval64)); 24708 p_bmp = soc_reg64_field_get(unit, THDO_PORT_DISABLE_STATUSr, rval64, 24709 QUEUE_BITMAPf); 24710 24711 if ((enable && !COMPILER_64_BITTEST(p_bmp, port)) || 24712 (!enable && COMPILER_64_BITTEST(p_bmp, port))) { 24713 return SOC_E_NONE; 24714 } 24715 if (soc_timeout_check(&to)) { 24716 LOG_WARN(BSL_LS_SOC_COMMON, 24717 (BSL_META_U(unit, 24718 "unit %d : Port %d enable timeout\n"), unit, port)); 24719 break; 24720 } 24721 } while (TRUE); 24722 24723 return SOC_E_TIMEOUT; 24724 } 24725 STATIC int 24726 _soc_kt2_mmu_config_shared_update_check(int unit, int val1, int val2, int flags) 24727 { 24728 int rv = 0; 24729 if (flags == 1) { 24730 if (val1 > val2) { 24731 rv = 1; 24732 } 24733 } else { 24734 if (val1 < val2) { 24735 rv = 1; 24736 } 24737 } 24738 return rv; 24739 } 24740 24741 int 24742 soc_kt2_mmu_config_shared_buf_recalc(int unit, int shared_size, 24743 bcm_kt2_cosq_recalc_type_t recalc_type) 24744 { 24745 uint8 port_index = 0; 24746 uint32 op_node=0; 24747 uint32 port_max_opnodes = 0; 24748 uint8 port_list[]={KT2_CMIC_PORT, KT2_LPBK_PORT , 24749 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 24750 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 24751 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 24752 31, 32, 33, 34, 35, 36, 37, 38, 39, 40}; 24753 soc_port_t port_iter=0; 24754 soc_info_t *si= &SOC_INFO(unit); 24755 mmu_thdo_opnconfig_cell_entry_t mmu_thdo_opnconfig_cell_entry={{0}}; 24756 uint32 op_node_offset=0; 24757 uint32 temp_val; 24758 uint32 rval = 0; 24759 uint32 ext_mem_type; 24760 int cur_limit, resume_limit, flags; 24761 24762 ext_mem_type = ((recalc_type == BCM_KT2_RECALC_SHARED_EXT_DECREMENT) || 24763 (recalc_type == BCM_KT2_RECALC_SHARED_EXT_INCREMENT)) ? 1 : 0; 24764 24765 flags = ((recalc_type == BCM_KT2_RECALC_SHARED_INT_DECREMENT) || 24766 (recalc_type == BCM_KT2_RECALC_SHARED_EXT_DECREMENT)) ? 1 : 0; 24767 24768 if ((recalc_type == BCM_KT2_RECALC_SHARED_EXT_DECREMENT) || 24769 (recalc_type == BCM_KT2_RECALC_SHARED_EXT_INCREMENT)) { 24770 24771 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_SHARED_LIMIT_CELLE_POOL0r ( 24772 unit, &rval)); 24773 cur_limit = soc_reg_field_get(unit, OP_BUFFER_SHARED_LIMIT_CELLE_POOL0r, rval, 24774 OP_BUFFER_SHARED_LIMIT_CELLEf); 24775 if (_soc_kt2_mmu_config_shared_update_check(unit, cur_limit, shared_size, flags)) { 24776 if (recalc_type == BCM_KT2_RECALC_SHARED_EXT_DECREMENT) { 24777 temp_val = cur_limit - shared_size; 24778 } else { 24779 temp_val = shared_size - cur_limit; 24780 } 24781 24782 soc_reg_field_set(unit, OP_BUFFER_SHARED_LIMIT_CELLE_POOL0r, &rval, 24783 OP_BUFFER_SHARED_LIMIT_CELLEf, shared_size); 24784 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_SHARED_LIMIT_CELLE_POOL0r ( 24785 unit, rval)); 24786 24787 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_SHARED_LIMIT_RESUME_CELLE_POOL0r( 24788 unit, &rval)); 24789 cur_limit = soc_reg_field_get(unit, OP_BUFFER_SHARED_LIMIT_RESUME_CELLE_POOL0r, 24790 rval,OP_BUFFER_SHARED_LIMIT_RESUME_CELLEf); 24791 if (recalc_type == BCM_KT2_RECALC_SHARED_EXT_DECREMENT) { 24792 resume_limit = cur_limit - temp_val; 24793 } else { 24794 resume_limit = cur_limit + temp_val; 24795 } 24796 soc_reg_field_set(unit, OP_BUFFER_SHARED_LIMIT_RESUME_CELLE_POOL0r, 24797 &rval,OP_BUFFER_SHARED_LIMIT_RESUME_CELLEf, resume_limit); 24798 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_SHARED_LIMIT_RESUME_CELLE_POOL0r( 24799 unit, rval)); 24800 } 24801 } else { 24802 /* Ouput port thresholds */ 24803 /* Internal buffer Egress pool */ 24804 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_SHARED_LIMIT_CELLIr (unit, &rval)); 24805 cur_limit = soc_reg_field_get(unit, OP_BUFFER_SHARED_LIMIT_CELLIr, rval, 24806 OP_BUFFER_SHARED_LIMIT_CELLIf); 24807 if (_soc_kt2_mmu_config_shared_update_check(unit, cur_limit, shared_size, flags)) { 24808 if (recalc_type == BCM_KT2_RECALC_SHARED_INT_DECREMENT) { 24809 temp_val = cur_limit - shared_size; 24810 } else { 24811 temp_val = shared_size - cur_limit; 24812 } 24813 soc_reg_field_set(unit, OP_BUFFER_SHARED_LIMIT_CELLIr, &rval, 24814 OP_BUFFER_SHARED_LIMIT_CELLIf, shared_size); 24815 24816 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_SHARED_LIMIT_CELLIr (unit, rval)); 24817 24818 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_SHARED_LIMIT_RESUME_CELLIr(unit, &rval)); 24819 cur_limit = soc_reg_field_get(unit, OP_BUFFER_SHARED_LIMIT_RESUME_CELLIr, rval, 24820 OP_BUFFER_SHARED_LIMIT_RESUME_CELLIf); 24821 if (recalc_type == BCM_KT2_RECALC_SHARED_INT_DECREMENT) { 24822 resume_limit = cur_limit - temp_val; 24823 } else { 24824 resume_limit = cur_limit + temp_val; 24825 } 24826 soc_reg_field_set(unit, OP_BUFFER_SHARED_LIMIT_RESUME_CELLIr, &rval, 24827 OP_BUFFER_SHARED_LIMIT_RESUME_CELLIf, resume_limit); 24828 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_SHARED_LIMIT_RESUME_CELLIr(unit, rval)); 24829 } 24830 } 24831 24832 op_node = 0; 24833 port_max_opnodes = 0; 24834 for(port_index = 0, op_node = 0 ; 24835 port_index < COUNTOF(port_list); 24836 port_index++, op_node += port_max_opnodes ) { 24837 24838 port_iter = port_list[port_index]; 24839 port_max_opnodes = ceil_func(si->port_num_uc_cosq[port_iter],8); 24840 24841 if (((!ext_mem_type && !SOC_PBMP_MEMBER(PBMP_EXT_MEM (unit), port_iter)) || 24842 (ext_mem_type && SOC_PBMP_MEMBER(PBMP_EXT_MEM (unit), port_iter))) && 24843 (port_iter >= KT2_CMIC_PORT) && (port_iter <= KT2_LPBK_PORT)) { 24844 for (op_node_offset = 0; 24845 op_node_offset < port_max_opnodes ; 24846 op_node_offset++) { 24847 SOC_IF_ERROR_RETURN(READ_MMU_THDO_OPNCONFIG_CELLm(unit, 24848 MEM_BLOCK_ANY,op_node + op_node_offset, 24849 &mmu_thdo_opnconfig_cell_entry)); 24850 24851 cur_limit = soc_mem_field32_get(unit, MMU_THDO_OPNCONFIG_CELLm, 24852 &mmu_thdo_opnconfig_cell_entry, 24853 OPN_SHARED_LIMIT_CELLf); 24854 if (_soc_kt2_mmu_config_shared_update_check( 24855 unit, cur_limit, shared_size, flags)) { 24856 if ((recalc_type == BCM_KT2_RECALC_SHARED_INT_DECREMENT) || 24857 (recalc_type == BCM_KT2_RECALC_SHARED_EXT_DECREMENT)) { 24858 temp_val = cur_limit - shared_size; 24859 } else { 24860 temp_val = shared_size - cur_limit; 24861 } 24862 soc_mem_field32_set(unit, MMU_THDO_OPNCONFIG_CELLm, 24863 &mmu_thdo_opnconfig_cell_entry, 24864 OPN_SHARED_LIMIT_CELLf, 24865 shared_size); 24866 24867 cur_limit = soc_mem_field32_get(unit, MMU_THDO_OPNCONFIG_CELLm, 24868 &mmu_thdo_opnconfig_cell_entry, 24869 OPN_SHARED_RESET_VALUE_CELLf); 24870 if ((recalc_type == BCM_KT2_RECALC_SHARED_INT_DECREMENT) || 24871 (recalc_type == BCM_KT2_RECALC_SHARED_EXT_DECREMENT)) { 24872 resume_limit = cur_limit - temp_val; 24873 } else { 24874 resume_limit = cur_limit + temp_val; 24875 } 24876 soc_mem_field32_set(unit, MMU_THDO_OPNCONFIG_CELLm, 24877 &mmu_thdo_opnconfig_cell_entry, 24878 OPN_SHARED_RESET_VALUE_CELLf, resume_limit); 24879 SOC_IF_ERROR_RETURN(WRITE_MMU_THDO_OPNCONFIG_CELLm(unit, 24880 MEM_BLOCK_ANY,op_node + op_node_offset, 24881 &mmu_thdo_opnconfig_cell_entry)); 24882 } 24883 } 24884 } 24885 } 24886 return SOC_E_NONE; 24887 } 24888 24889 int soc_kt2_mmu_get_shared_size(int unit, int *shared_size, 24890 int *shared_size_external) 24891 { 24892 uint32 rval = 0; 24893 24894 if (shared_size) { 24895 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_SHARED_LIMIT_CELLIr (unit, &rval)); 24896 *shared_size = soc_reg_field_get(unit, OP_BUFFER_SHARED_LIMIT_CELLIr, rval, 24897 OP_BUFFER_SHARED_LIMIT_CELLIf); 24898 } 24899 if (shared_size_external) { 24900 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_SHARED_LIMIT_CELLE_POOL0r ( 24901 unit, &rval)); 24902 *shared_size_external = soc_reg_field_get(unit, 24903 OP_BUFFER_SHARED_LIMIT_CELLE_POOL0r, rval, 24904 OP_BUFFER_SHARED_LIMIT_CELLEf); 24905 } 24906 return 1; 24907 } 24908 24909 void 24910 soc_kt2_xport_type_update(int unit, soc_port_t port, int mode) 24911 { 24912 soc_info_t *si; 24913 soc_port_t it_port; 24914 24915 si = &SOC_INFO(unit); 24916 24917 /* We need to lock the SOC structures until we finish the update */ 24918 SOC_CONTROL_LOCK(unit); 24919 24920 if (mode != SOC_ENCAP_IEEE) { 24921 SOC_PBMP_PORT_ADD(si->st.bitmap, port); 24922 SOC_PBMP_PORT_REMOVE(si->ether.bitmap, port); 24923 SOC_PBMP_PORT_REMOVE(si->xe.bitmap, port); 24924 /* special process for HG-Lite support to avoid wrong PBMP assignment. 24925 * 24926 * Note : 24927 * the 'to_hg_port' for this special design must carry proper encap mode 24928 * instead of TRUE/FALSE only. 24929 */ 24930 if ((mode == SOC_ENCAP_HIGIG2) || (mode == SOC_ENCAP_HIGIG2_LITE)) { 24931 if (mode == SOC_ENCAP_HIGIG2_LITE) { 24932 SOC_PBMP_PORT_ADD(si->hl.bitmap, port); 24933 } 24934 SOC_PBMP_PORT_ADD(si->hg.bitmap, port); 24935 } 24936 } else { 24937 /* To IEEE mode */ 24938 SOC_PBMP_PORT_ADD(si->ether.bitmap, port); 24939 SOC_PBMP_PORT_ADD(si->xe.bitmap, port); 24940 SOC_PBMP_PORT_REMOVE(si->st.bitmap, port); 24941 SOC_PBMP_PORT_REMOVE(si->hg.bitmap, port); 24942 SOC_PBMP_PORT_REMOVE(si->hl.bitmap, port); 24943 } 24944 #define RECONFIGURE_PORT_TYPE_INFO(ptype) \ 24945 si->ptype.num = 0; \ 24946 si->ptype.min = si->ptype.max = -1; \ 24947 PBMP_ITER(si->ptype.bitmap, it_port) { \ 24948 si->ptype.port[si->ptype.num++] = it_port; \ 24949 if (si->ptype.min < 0) { \ 24950 si->ptype.min = it_port; \ 24951 } \ 24952 if (it_port > si->ptype.max) { \ 24953 si->ptype.max = it_port; \ 24954 } \ 24955 } 24956 24957 /* Recalculate port type data */ 24958 RECONFIGURE_PORT_TYPE_INFO(ether); 24959 RECONFIGURE_PORT_TYPE_INFO(st); 24960 RECONFIGURE_PORT_TYPE_INFO(hg); 24961 RECONFIGURE_PORT_TYPE_INFO(xe); 24962 #undef RECONFIGURE_PORT_TYPE_INFO 24963 24964 soc_dport_map_update(unit); 24965 24966 /* Release SOC structures lock */ 24967 SOC_CONTROL_UNLOCK(unit); 24968 } 24969 24970 int soc_kt2_get_max_buffer_size(int unit, int external, int value) 24971 { 24972 int cval; 24973 #ifdef BCM_SABER2_SUPPORT 24974 if (SOC_IS_SABER2(unit)) { 24975 #ifdef BCM_METROLITE_SUPPORT 24976 if (SOC_IS_METROLITE(unit)) { 24977 return soc_ml_get_max_buffer_size(unit, value); 24978 } else 24979 #endif 24980 { 24981 return soc_sb2_get_max_buffer_size(unit, external, value); 24982 } 24983 } else 24984 #endif 24985 { 24986 cval= (external ? 24987 _soc_kt2_mmu_intermediate_results.general_info.max_ext_cell_buff_size: 24988 _soc_kt2_mmu_intermediate_results.general_info.max_int_cell_buff_size); 24989 if ((cval <= 0) || (cval >= value)) { 24990 return value; 24991 } else { 24992 return cval; 24993 } 24994 } 24995 } 24996 #endif /* BCM_KATANA2_SUPPORT */