katana.c (526264B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: katana.c 8 * Purpose: 9 * Requires: 10 */ 11 12 13 #include <shared/bsl.h> 14 15 #include <sal/core/boot.h> 16 #include <soc/katana.h> 17 #include <soc/katana2.h> 18 #include <soc/saber2.h> 19 #include <soc/trident.h> 20 #include <soc/bradley.h> 21 #include <soc/enduro.h> 22 #include <soc/drv.h> 23 #include <soc/error.h> 24 #include <soc/mem.h> 25 #include <soc/hash.h> 26 #include <soc/shmoo_ddr40.h> 27 #include <soc/phy/ddr40.h> 28 #include <soc/mspi.h> 29 #include <soc/post.h> 30 #include <soc/soc_ser_log.h> 31 32 #ifdef BCM_CMICM_SUPPORT 33 #include <soc/cmicm.h> 34 #endif 35 36 #ifdef BCM_KATANA_SUPPORT 37 38 #ifdef _ERR_MSG_MODULE_NAME 39 #error "_ERR_MSG_MODULE_NAME redefined" 40 #endif 41 42 #define _ERR_MSG_MODULE_NAME SOC_DBG_COSQ 43 44 /* Min/Max threshold settings - 33 Gbps */ 45 #define KT_QUEUE_FLUSH_RATE_MANTISSA 1023 46 #define KT_QUEUE_FLUSH_RATE_EXP 14 47 #define KT_QUEUE_FLUSH_BURST_MANTISSA 124 48 #define KT_QUEUE_FLUSH_BURST_EXP 14 49 #define KT_QUEUE_FLUSH_CYCLE_SEL 0 50 51 #define KT_OAM_INTR_MASK 0xFF 52 #define KT_OAM_CMIC_INTR_MASK 0x00000010 53 54 #define MAX_BUCKET_VAL 0x1fffff 55 static katanaShaperInfo_t *shaper_info[SOC_MAX_NUM_DEVICES]; 56 extern soc_kt_oam_handler_t en_oam_handler[SOC_MAX_NUM_DEVICES]; 57 58 typedef struct _soc_katana_ci_parama_s { 59 uint32 speed; 60 uint32 grade; 61 } _soc_katana_ci_parama_t; 62 63 typedef enum { 64 _SOC_PARITY_TYPE_NONE, 65 _SOC_PARITY_TYPE_GENERIC, 66 _SOC_PARITY_TYPE_PARITY, 67 _SOC_PARITY_TYPE_ECC, 68 _SOC_PARITY_TYPE_HASH, 69 _SOC_PARITY_TYPE_EDATABUF, 70 _SOC_PARITY_TYPE_COUNTER, 71 _SOC_PARITY_TYPE_MXQPORT, 72 _SOC_PARITY_TYPE_SER 73 } _soc_katana_parity_info_type_t; 74 75 typedef enum { 76 _SOC_KT_MMU_SUBBLOCK_MEM1, 77 _SOC_KT_MMU_SUBBLOCK_INTFI, 78 _SOC_KT_MMU_SUBBLOCK_INTFI_ECC, 79 _SOC_KT_MMU_SUBBLOCK_E2EFC, 80 _SOC_KT_MMU_SUBBLOCK_ITE, 81 _SOC_KT_MMU_SUBBLOCK_ITE_CFG, 82 _SOC_KT_MMU_SUBBLOCK_THDI, 83 _SOC_KT_MMU_SUBBLOCK_ENQ_CFG, 84 _SOC_KT_MMU_SUBBLOCK_ENQ, 85 _SOC_KT_MMU_SUBBLOCK_ENQ_FAP, 86 _SOC_KT_MMU_SUBBLOCK_CI2, 87 _SOC_KT_MMU_SUBBLOCK_CI1, 88 _SOC_KT_MMU_SUBBLOCK_CI0, 89 _SOC_KT_MMU_SUBBLOCK_WRED, 90 _SOC_KT_MMU_SUBBLOCK_THDO_STATUS1, 91 _SOC_KT_MMU_SUBBLOCK_THDO_STATUS2, 92 _SOC_KT_MMU_SUBBLOCK_RQE_SER, 93 _SOC_KT_MMU_SUBBLOCK_RQE_EXTQ, 94 _SOC_KT_MMU_SUBBLOCK_EMC, 95 _SOC_KT_MMU_SUBBLOCK_DEQ, 96 _SOC_KT_MMU_SUBBLOCK_CTR, 97 _SOC_KT_MMU_SUBBLOCK_CFAPI, 98 _SOC_KT_MMU_SUBBLOCK_CFAPE, 99 _SOC_KT_MMU_SUBBLOCK_CCP, 100 _SOC_KT_MMU_SUBBLOCK_AGING_INT, 101 _SOC_KT_MMU_SUBBLOCK_AGING_EXT, 102 _SOC_KT_MMU_SUBBLOCK_LLS, 103 _SOC_KT_MMU_SUBBLOCK_LLS_PORT, 104 _SOC_KT_MMU_SUBBLOCK_LLS_L0_ECC, 105 _SOC_KT_MMU_SUBBLOCK_LLS_UPD2, 106 _SOC_KT_MMU_SUBBLOCK_LLS_L1_ECC, 107 _SOC_KT_MMU_SUBBLOCK_LLS_L2_ECC, 108 _SOC_KT_MMU_SUBBLOCK_LLS_MISC_ECC, 109 _SOC_KT_MMU_SUBBLOCK_QSTRUCT, 110 _SOC_KT_MMU_SUBBLOCK_TOQ, 111 _SOC_KT_MMU_SUBBLOCK_MAX 112 } _soc_katana_mmu_subblock_type_t; 113 114 115 typedef enum { 116 _SOC_KT_MMU_LVL2_SUBBLOCK_EMC_ERROR_0, 117 _SOC_KT_MMU_LVL2_SUBBLOCK_EMC_ERROR_1, 118 _SOC_KT_MMU_LVL2_SUBBLOCK_EMC_ERROR_2, 119 _SOC_KT_MMU_LVL2_SUBBLOCK_DEQ_ERROR_0, 120 _SOC_KT_MMU_LVL2_SUBBLOCK_DEQ_ERROR_1, 121 _SOC_KT_MMU_LVL2_SUBBLOCK_DEQ_ERROR_2, 122 _SOC_KT_MMU_LVL2_SUBBLOCK_DEQ_ERROR_3, 123 _SOC_KT_MMU_LVL2_SUBBLOCK_QSTRUCT_QENTRY_U, 124 _SOC_KT_MMU_LVL2_SUBBLOCK_QSTRUCT_QENTRY_L, 125 _SOC_KT_MMU_LVL2_SUBBLOCK_QSTRUCT_QBLOCK, 126 _SOC_KT_MMU_LVL2_SUBBLOCK_QSTRUCT_FAP, 127 _SOC_KT_MMU_LVL2_SUBBLOCK_MAX 128 } _soc_katana_mmu_lvl2_subblock_type_t; 129 130 typedef struct _soc_katana_parity_reg_s { 131 soc_reg_t reg; 132 char *mem_str; 133 } _soc_katana_parity_reg_t; 134 135 typedef struct _soc_katana_parity_info_s { 136 _soc_katana_parity_info_type_t type; 137 struct _soc_katana_parity_info_s *info; 138 int id; 139 soc_field_t group_reg_enable_field; 140 soc_field_t group_reg_status_field; 141 soc_mem_t mem; 142 char *mem_str; 143 soc_reg_t enable_reg; 144 soc_field_t enable_field; 145 soc_reg_t intr_status_reg; 146 _soc_katana_parity_reg_t *intr_status_reg_list; 147 soc_reg_t nack_status_reg; 148 _soc_katana_parity_reg_t *nack_status_reg_list; 149 } _soc_katana_parity_info_t; 150 151 typedef struct _soc_katana_parity_route_block_s { 152 uint32 cmic_bit; 153 soc_block_t blocktype; 154 soc_reg_t enable_reg; 155 soc_reg_t status_reg; 156 _soc_katana_parity_info_t *info; 157 uint8 id; 158 } _soc_katana_parity_route_block_t; 159 160 typedef struct _soc_katana_parity_mmu_route_block_s { 161 uint32 intr_bit; 162 _soc_katana_mmu_subblock_type_t sub_block; 163 soc_reg_t enable_reg; 164 soc_reg_t status_reg; 165 _soc_katana_parity_info_t *info; 166 } _soc_katana_parity_mmu_route_block_t; 167 168 typedef struct _soc_katana_mmu_sub_block_type_1_info_s { 169 uint32 intr_bit; 170 soc_field_t sub_block_field; 171 soc_field_t sub_block_en_field; 172 } _soc_katana_mmu_sub_block_type_1_info_t; 173 174 typedef struct _soc_katana_mmu_sub_block_type_2_info_s { 175 uint32 intr_bit; 176 uint32 en_bit; 177 soc_field_t sub_block_field; 178 soc_field_t sub_block_en_field; 179 } _soc_katana_mmu_sub_block_type_2_info_t; 180 181 typedef struct _soc_katana_mmu_sub_block_info_s { 182 uint32 intr_bit; 183 soc_reg_t sub_block_reg; 184 soc_reg_t sub_block_en_reg; 185 soc_field_t sub_block_field; 186 soc_field_t sub_block_en_field; 187 _soc_katana_mmu_sub_block_type_2_info_t *info; 188 } _soc_katana_mmu_sub_block_info_t; 189 190 typedef struct _soc_katana_mmu_sub_block_type_3_info_s { 191 uint32 intr_bit; 192 _soc_katana_mmu_lvl2_subblock_type_t lvl2_sub_block; 193 soc_reg_t sub_block_reg; 194 soc_reg_t sub_block_en_reg; 195 soc_field_t sub_block_field; 196 soc_field_t sub_block_en_field; 197 _soc_katana_mmu_sub_block_type_1_info_t *info; 198 } _soc_katana_mmu_sub_block_type_3_info_t; 199 200 201 typedef struct _soc_katana_mmu_sub_block_type_1_s { 202 uint32 mmu_bit; 203 _soc_katana_mmu_subblock_type_t mmu_sub_block; 204 soc_reg_t sub_block_en_reg; 205 soc_reg_t sub_block_reg; 206 _soc_katana_mmu_sub_block_type_1_info_t *info; 207 } _soc_katana_mmu_sub_block_type_1_t; 208 209 typedef struct _soc_katana_mmu_sub_block_type_2_s { 210 uint32 mmu_bit; 211 _soc_katana_mmu_subblock_type_t mmu_sub_block; 212 soc_reg_t sub_block_en_reg; 213 soc_reg_t sub_block_reg; 214 _soc_katana_mmu_sub_block_type_2_info_t *info; 215 } _soc_katana_mmu_sub_block_type_2_t; 216 217 typedef struct _soc_katana_mmu_sub_block_type_3_s { 218 uint32 mmu_bit; 219 _soc_katana_mmu_subblock_type_t mmu_sub_block; 220 soc_reg_t sub_block_en_reg; 221 soc_reg_t sub_block_reg; 222 _soc_katana_mmu_sub_block_type_3_info_t *info; 223 } _soc_katana_mmu_sub_block_type_3_t; 224 225 typedef struct _soc_katana_mmu_sub_block_s { 226 uint32 mmu_bit; 227 _soc_katana_mmu_subblock_type_t mmu_sub_block; 228 soc_reg_t sub_block_reg; 229 soc_reg_t sub_block_en_reg; 230 _soc_katana_mmu_sub_block_info_t *info; 231 } _soc_katana_mmu_sub_block_t; 232 233 234 typedef enum { 235 _SOC_COUNTER_TYPE_DROP_ENQ, 236 _SOC_COUNTER_TYPE_ACCEPT_ENQ, 237 _SOC_COUNTER_TYPE_DROP_ENQ_GREEN, 238 _SOC_COUNTER_TYPE_DROP_ENQ_YELLOW, 239 _SOC_COUNTER_TYPE_DROP_ENQ_RED, 240 _SOC_COUNTER_TYPE_ACCEPT_ENQ_GREEN, 241 _SOC_COUNTER_TYPE_ACCEPT_ENQ_YELLOW, 242 _SOC_COUNTER_TYPE_ACCEPT_ENQ_RED, 243 _SOC_COUNTER_TYPE_ACCEPT_DEQ, 244 _SOC_COUNTER_TYPE_MAX 245 } _soc_katana_counter_type_t; 246 247 typedef struct _soc_katana_counter_info_s { 248 _soc_katana_counter_type_t type; 249 int index; 250 int segment; 251 }_soc_katana_counter_info_t; 252 253 STATIC _soc_katana_parity_reg_t _soc_katana_egr_vlan_xlate_intr_reg[] = { 254 { EGR_VLAN_XLATE_PARITY_STATUS_INTR_0r, NULL }, 255 { EGR_VLAN_XLATE_PARITY_STATUS_INTR_1r, NULL } }; 256 STATIC _soc_katana_parity_reg_t _soc_katana_egr_vlan_xlate_nack_reg[] = { 257 { EGR_VLAN_XLATE_PARITY_STATUS_NACK_0r, NULL }, 258 { EGR_VLAN_XLATE_PARITY_STATUS_NACK_1r, NULL } }; 259 STATIC _soc_katana_parity_reg_t _soc_katana_vlan_xlate_intr_reg[] = { 260 { VLAN_XLATE_PARITY_STATUS_INTR_0r, NULL }, 261 { VLAN_XLATE_PARITY_STATUS_INTR_1r, NULL } }; 262 STATIC _soc_katana_parity_reg_t _soc_katana_vlan_xlate_nack_reg[] = { 263 { VLAN_XLATE_PARITY_STATUS_NACK_0r, NULL }, 264 { VLAN_XLATE_PARITY_STATUS_NACK_1r, NULL } }; 265 STATIC _soc_katana_parity_reg_t _soc_katana_mpls_entry_intr_reg[] = { 266 { MPLS_ENTRY_PARITY_STATUS_INTR_0r, NULL }, 267 { MPLS_ENTRY_PARITY_STATUS_INTR_1r, NULL } }; 268 STATIC _soc_katana_parity_reg_t _soc_katana_mpls_entry_nack_reg[] = { 269 { MPLS_ENTRY_PARITY_STATUS_NACK_0r, NULL }, 270 { MPLS_ENTRY_PARITY_STATUS_NACK_1r, NULL } }; 271 STATIC _soc_katana_parity_reg_t _soc_katana_l3_entry_ipv6_unicast_intr_reg[] = { 272 { L3_ENTRY_PARITY_STATUS_INTR_0r, NULL }, 273 { L3_ENTRY_PARITY_STATUS_INTR_1r, NULL } }; 274 STATIC _soc_katana_parity_reg_t _soc_katana_l3_entry_ipv6_unicast_nack_reg[] = { 275 { L3_ENTRY_PARITY_STATUS_NACK_0r, NULL }, 276 { L3_ENTRY_PARITY_STATUS_NACK_1r, NULL } }; 277 STATIC _soc_katana_parity_reg_t _soc_katana_l2_entry_only_intr_reg[] = { 278 { L2_ENTRY_PARITY_STATUS_INTR_0r, NULL }, 279 { L2_ENTRY_PARITY_STATUS_INTR_1r, NULL } }; 280 STATIC _soc_katana_parity_reg_t _soc_katana_l2_entry_only_nack_reg[] = { 281 { L2_ENTRY_PARITY_STATUS_NACK_0r, NULL }, 282 { L2_ENTRY_PARITY_STATUS_NACK_1r, NULL } }; 283 284 #ifdef _KATANA_DEBUG 285 STATIC _soc_katana_parity_info_t _soc_katana_xport_parity_info[] = { 286 { _SOC_PARITY_TYPE_ECC, NULL, 0, 287 TXFIFO_MEM_ERRf, 288 TXFIFO_MEM_ERRf, 289 INVALIDm, "TX FIFO", 290 INVALIDr, INVALIDf, 291 XPORT_TXFIFO_MEM_ECC_STATUSr, NULL, 292 INVALIDr, NULL }, 293 { _SOC_PARITY_TYPE_ECC, NULL, 0, 294 MIB_TSC_MEM0_ERRf, 295 MIB_TSC_MEM0_ERRf, 296 INVALIDm, "TX MIB MEM0", 297 INVALIDr, INVALIDf, 298 XPORT_MIB_TSC_MEM0_ECC_STATUSr, NULL, 299 INVALIDr, NULL }, 300 { _SOC_PARITY_TYPE_ECC, NULL, 0, 301 MIB_TSC_MEM1_ERRf, 302 MIB_TSC_MEM1_ERRf, 303 INVALIDm, "TX MIB MEM1", 304 INVALIDr, INVALIDf, 305 XPORT_MIB_TSC_MEM1_ECC_STATUSr, NULL, 306 INVALIDr, NULL }, 307 { _SOC_PARITY_TYPE_ECC, NULL, 0, 308 MIB_TSC_MEM2_ERRf, 309 MIB_TSC_MEM2_ERRf, 310 INVALIDm, "TX MIB MEM2", 311 INVALIDr, INVALIDf, 312 XPORT_MIB_TSC_MEM2_ECC_STATUSr, NULL, 313 INVALIDr, NULL }, 314 { _SOC_PARITY_TYPE_ECC, NULL, 0, 315 MIB_TSC_MEM3_ERRf, 316 MIB_TSC_MEM3_ERRf, 317 INVALIDm, "TX MIB MEM3", 318 INVALIDr, INVALIDf, 319 XPORT_MIB_TSC_MEM3_ECC_STATUSr, NULL, 320 INVALIDr, NULL }, 321 { _SOC_PARITY_TYPE_ECC, NULL, 0, 322 MIB_RSC_MEM0_ERRf, 323 MIB_RSC_MEM0_ERRf, 324 INVALIDm, "RX MIB MEM0", 325 INVALIDr, INVALIDf, 326 XPORT_MIB_RSC_MEM0_ECC_STATUSr, NULL, 327 INVALIDr, NULL }, 328 { _SOC_PARITY_TYPE_ECC, NULL, 0, 329 MIB_RSC_MEM1_ERRf, 330 MIB_RSC_MEM1_ERRf, 331 INVALIDm, "RX MIB MEM1", 332 INVALIDr, INVALIDf, 333 XPORT_MIB_RSC_MEM1_ECC_STATUSr, NULL, 334 INVALIDr, NULL }, 335 { _SOC_PARITY_TYPE_ECC, NULL, 0, 336 MIB_RSC_MEM2_ERRf, 337 MIB_RSC_MEM2_ERRf, 338 INVALIDm, "RX MIB MEM2", 339 INVALIDr, INVALIDf, 340 XPORT_MIB_RSC_MEM2_ECC_STATUSr, NULL, 341 INVALIDr, NULL }, 342 { _SOC_PARITY_TYPE_ECC, NULL, 0, 343 MIB_RSC_MEM3_ERRf, 344 MIB_RSC_MEM3_ERRf, 345 INVALIDm, "RX MIB MEM3", 346 INVALIDr, INVALIDf, 347 XPORT_MIB_RSC_MEM3_ECC_STATUSr, NULL, 348 INVALIDr, NULL }, 349 { _SOC_PARITY_TYPE_ECC, NULL, 0, 350 MIB_RSC_MEM4_ERRf, 351 MIB_RSC_MEM4_ERRf, 352 INVALIDm, "RX MIB MEM4", 353 INVALIDr, INVALIDf, 354 XPORT_MIB_RSC_MEM4_ECC_STATUSr, NULL, 355 INVALIDr, NULL }, 356 { _SOC_PARITY_TYPE_ECC, NULL, 0, 357 RXFIFO_MEM0_ERRf, 358 RXFIFO_MEM0_ERRf, 359 INVALIDm, "RX FIFO MEM0", 360 INVALIDr, INVALIDf, 361 XPORT_RXFIFO_MEM0_ECC_STATUSr, NULL, 362 INVALIDr, NULL }, 363 { _SOC_PARITY_TYPE_ECC, NULL, 0, 364 RXFIFO_MEM1_ERRf, 365 RXFIFO_MEM1_ERRf, 366 INVALIDm, "RX FIFO MEM1", 367 INVALIDr, INVALIDf, 368 XPORT_RXFIFO_MEM1_ECC_STATUSr, NULL, 369 INVALIDr, NULL }, 370 { _SOC_PARITY_TYPE_ECC, NULL, 0, 371 RXFIFO_MEM2_ERRf, 372 RXFIFO_MEM2_ERRf, 373 INVALIDm, "RX FIFO MEM2", 374 INVALIDr, INVALIDf, 375 XPORT_RXFIFO_MEM2_ECC_STATUSr, NULL, 376 INVALIDr, NULL }, 377 { _SOC_PARITY_TYPE_ECC, NULL, 0, 378 RXFIFO_MEM3_ERRf, 379 RXFIFO_MEM3_ERRf, 380 INVALIDm, "RX FIFO MEM3", 381 INVALIDr, INVALIDf, 382 XPORT_RXFIFO_MEM3_ECC_STATUSr, NULL, 383 INVALIDr, NULL }, 384 { _SOC_PARITY_TYPE_NONE } /* table terminator */ 385 }; 386 #endif 387 388 #ifdef _KATANA_DEBUG 389 STATIC _soc_katana_parity_info_t _soc_katana_mmu_parity_info[] = { 390 { _SOC_PARITY_TYPE_GENERIC, NULL, 0, 391 AGING_CTR_PAR_ERR_ENf, 392 AGING_CTR_PAR_ERRf, 393 INVALIDm, "", 394 INVALIDr, INVALIDf, 395 INVALIDr, NULL, 396 INVALIDr, NULL }, 397 { _SOC_PARITY_TYPE_GENERIC, NULL, 0, 398 AGING_EXP_PAR_ERR_ENf, 399 AGING_EXP_PAR_ERRf, 400 INVALIDm, "", 401 INVALIDr, INVALIDf, 402 INVALIDr, NULL, 403 INVALIDr, NULL }, 404 { _SOC_PARITY_TYPE_GENERIC, NULL, 0, 405 CCP_PAR_ERR_ENf, 406 CCP_PAR_ERRf, 407 INVALIDm, "", 408 INVALIDr, INVALIDf, 409 INVALIDr, NULL, 410 INVALIDr, NULL }, 411 { _SOC_PARITY_TYPE_GENERIC, NULL, 0, 412 CFAP_PAR_ERR_ENf, 413 CFAP_PAR_ERRf, 414 INVALIDm, "", 415 INVALIDr, INVALIDf, 416 INVALIDr, NULL, 417 INVALIDr, NULL }, 418 { _SOC_PARITY_TYPE_GENERIC, NULL, 0, 419 CFAP_MEM_FAIL_ENf, 420 CFAP_MEM_FAILf, 421 INVALIDm, "", 422 INVALIDr, INVALIDf, 423 INVALIDr, NULL, 424 INVALIDr, NULL }, 425 { _SOC_PARITY_TYPE_GENERIC, NULL, 0, 426 DEQ_MPB_ERR_ENf, 427 DEQ_MPB_ERRf, 428 INVALIDm, "", 429 MEM_FAIL_INT_ENr, DEQ_MPB_ERR_ENf, 430 INVALIDr, NULL, 431 INVALIDr, NULL }, 432 { _SOC_PARITY_TYPE_GENERIC, NULL, 0, 433 DEQ_PKTHDR_ERR_ENf, 434 DEQ_PKTHDR_ERRf, 435 INVALIDm, "", 436 INVALIDr, INVALIDf, 437 INVALIDr, NULL, 438 INVALIDr, NULL }, 439 { _SOC_PARITY_TYPE_GENERIC, NULL, 0, 440 DEQ_NOT_IP_ERR_ENf, 441 DEQ_NOT_IP_ERRf, 442 INVALIDm, "", 443 INVALIDr, INVALIDf, 444 INVALIDr, NULL, 445 INVALIDr, NULL }, 446 { _SOC_PARITY_TYPE_GENERIC, NULL, 0, 447 CTR_UC_CNT_ENf, 448 CTR_UC_CNTf, 449 INVALIDm, "", 450 INVALIDr, INVALIDf, 451 INVALIDr, NULL, 452 INVALIDr, NULL }, 453 { _SOC_PARITY_TYPE_GENERIC, NULL, 0, 454 START_BY_START_ERR_ENf, 455 START_BY_START_ERRf, 456 INVALIDm, "", 457 INVALIDr, INVALIDf, 458 INVALIDr, NULL, 459 INVALIDr, NULL }, 460 { _SOC_PARITY_TYPE_GENERIC, NULL, 0, 461 CTR_MC_CNT_ENf, 462 CTR_MC_CNTf, 463 INVALIDm, "", 464 INVALIDr, INVALIDf, 465 INVALIDr, NULL, 466 INVALIDr, NULL }, 467 { _SOC_PARITY_TYPE_GENERIC, NULL, 0, 468 CTR_COLOR_CNT_ERR_ENf, 469 CTR_COLOR_CNT_ERRf, 470 INVALIDm, "", 471 INVALIDr, INVALIDf, 472 INVALIDr, NULL, 473 INVALIDr, NULL }, 474 { _SOC_PARITY_TYPE_GENERIC, NULL, 0, 475 TOQ0_UCQ_RP_PAR_ERR_ENf, 476 TOQ0_UCQ_RP_PAR_ERRf, 477 INVALIDm, "", 478 INVALIDr, INVALIDf, 479 INVALIDr, NULL, 480 INVALIDr, NULL }, 481 { _SOC_PARITY_TYPE_GENERIC, NULL, 0, 482 TOQ0_UCQ_WP_PAR_ERR_ENf, 483 TOQ0_UCQ_WP_PAR_ERRf, 484 INVALIDm, "", 485 INVALIDr, INVALIDf, 486 INVALIDr, NULL, 487 INVALIDr, NULL }, 488 { _SOC_PARITY_TYPE_GENERIC, NULL, 0, 489 TOQ0_PKTLINK_PAR_ERR_ENf, 490 TOQ0_PKTLINK_PAR_ERRf, 491 INVALIDm, "", 492 INVALIDr, INVALIDf, 493 INVALIDr, NULL, 494 INVALIDr, NULL }, 495 { _SOC_PARITY_TYPE_GENERIC, NULL, 0, 496 TOQ0_CELLLINK_PAR_ERR_ENf, 497 TOQ0_CELLLINK_PAR_ERRf, 498 INVALIDm, "", 499 INVALIDr, INVALIDf, 500 INVALIDr, NULL, 501 INVALIDr, NULL }, 502 { _SOC_PARITY_TYPE_GENERIC, NULL, 0, 503 TOQ0_CPQLINK_PAR_ERR_ENf, 504 TOQ0_CPQLINK_PAR_ERRf, 505 INVALIDm, "", 506 INVALIDr, INVALIDf, 507 INVALIDr, NULL, 508 INVALIDr, NULL }, 509 { _SOC_PARITY_TYPE_GENERIC, NULL, 0, 510 TOQ0_IPMC_MC_FIFO_PAR_ERR_ENf, 511 TOQ0_IPMC_MC_FIFO_PAR_ERRf, 512 INVALIDm, "", 513 INVALIDr, INVALIDf, 514 INVALIDr, NULL, 515 INVALIDr, NULL }, 516 { _SOC_PARITY_TYPE_GENERIC, NULL, 0, 517 TOQ0_IPMC_TBL_PAR_ERR_ENf, 518 TOQ0_IPMC_TBL_PAR_ERRf, 519 INVALIDm, "", 520 INVALIDr, INVALIDf, 521 INVALIDr, NULL, 522 INVALIDr, NULL }, 523 { _SOC_PARITY_TYPE_GENERIC, NULL, 0, 524 TOQ0_VLAN_TBL_PAR_ERR_ENf, 525 TOQ0_VLAN_TBL_PAR_ERRf, 526 INVALIDm, "", 527 INVALIDr, INVALIDf, 528 INVALIDr, NULL, 529 INVALIDr, NULL }, 530 { _SOC_PARITY_TYPE_GENERIC, NULL, 0, 531 MTRO_PAR_ERR_ENf, 532 MTRO_PAR_ERRf, 533 INVALIDm, "", 534 INVALIDr, INVALIDf, 535 INVALIDr, NULL, 536 INVALIDr, NULL }, 537 { _SOC_PARITY_TYPE_GENERIC, NULL, 0, 538 WRED_PAR_ERR_ENf, 539 WRED_PAR_ERRf, 540 INVALIDm, "", 541 INVALIDr, INVALIDf, 542 INVALIDr, NULL, 543 INVALIDr, NULL }, 544 { _SOC_PARITY_TYPE_GENERIC, NULL, 0, 545 OVQ_PAR_ERR_ENf, 546 OVQ_PAR_ERRf, 547 INVALIDm, "", 548 INVALIDr, INVALIDf, 549 INVALIDr, NULL, 550 INVALIDr, NULL }, 551 { _SOC_PARITY_TYPE_GENERIC, NULL, 0, 552 PQE_PAR_ERR_ENf, 553 PQE_PAR_ERRf, 554 INVALIDm, "", 555 INVALIDr, INVALIDf, 556 INVALIDr, NULL, 557 INVALIDr, NULL }, 558 { _SOC_PARITY_TYPE_GENERIC, NULL, 0, 559 QCN_PAR_ERR_ENf, 560 QCN_PAR_ERRf, 561 INVALIDm, "", 562 INVALIDr, INVALIDf, 563 INVALIDr, NULL, 564 INVALIDr, NULL }, 565 { _SOC_PARITY_TYPE_GENERIC, NULL, 0, 566 THDO_PAR_ERR_ENf, 567 THDO_PAR_ERRf, 568 INVALIDm, "", 569 INVALIDr, INVALIDf, 570 INVALIDr, NULL, 571 INVALIDr, NULL }, 572 { _SOC_PARITY_TYPE_GENERIC, NULL, 0, 573 THDI_PAR_ERR_ENf, 574 THDI_PAR_ERRf, 575 INVALIDm, "", 576 INVALIDr, INVALIDf, 577 INVALIDr, NULL, 578 INVALIDr, NULL }, 579 { _SOC_PARITY_TYPE_GENERIC, NULL, 0, 580 ES_PAR_ERR_ENf, 581 ES_PAR_ERRf, 582 INVALIDm, "", 583 INVALIDr, INVALIDf, 584 INVALIDr, NULL, 585 INVALIDr, NULL }, 586 { _SOC_PARITY_TYPE_NONE } /* table terminator */ 587 }; 588 #endif 589 590 591 STATIC 592 _soc_katana_mmu_sub_block_type_1_info_t _soc_katana_mmu_sb_lls_parity_info[] = { 593 /* LLS_ERROR */ 594 { 0x10000000, ENQ_TO_ACTIVE_QUEUE_VIOL_INTERRUPTf, 595 ENQ_TO_ACTIVE_QUEUE_VIOL_INTERRUPT_DISINTf}, 596 { 0x8000000, PORT_1_IN_4_DEQ_VIOL_INTERRUPTf, 597 PORT_1_IN_4_DEQ_VIOL_INTERRUPT_DISINTf}, 598 { 0x4000000, PORT_MAX_SHAPER_REFRESH_CYCLE_INTERRUPTf, 599 PORT_MAX_SHAPER_REFRESH_CYCLE_INTERRUPT_DISINTf}, 600 { 0x2000000, L0_MAX_SHAPER_REFRESH_CYCLE_INTERRUPTf, 601 L0_MAX_SHAPER_REFRESH_CYCLE_INTERRUPT_DISINTf}, 602 { 0x1000000, L1_MAX_SHAPER_REFRESH_CYCLE_INTERRUPTf, 603 L1_MAX_SHAPER_REFRESH_CYCLE_INTERRUPT_DISINTf}, 604 { 0x800000, L2_UPPER_MAX_SHAPER_REFRESH_CYCLE_INTERRUPTf, 605 L2_UPPER_MAX_SHAPER_REFRESH_CYCLE_INTERRUPT_DISINTf}, 606 { 0x400000, L2_LOWER_MAX_SHAPER_REFRESH_CYCLE_INTERRUPTf, 607 L2_LOWER_MAX_SHAPER_REFRESH_CYCLE_INTERRUPT_DISINTf}, 608 { 0x200000, L0_MIN_SHAPER_REFRESH_CYCLE_INTERRUPTf, 609 L0_MIN_SHAPER_REFRESH_CYCLE_INTERRUPT_DISINTf}, 610 { 0x100000, L1_MIN_SHAPER_REFRESH_CYCLE_INTERRUPTf, 611 L1_MIN_SHAPER_REFRESH_CYCLE_INTERRUPT_DISINTf}, 612 { 0x80000, L2_UPPER_MIN_SHAPER_REFRESH_CYCLE_INTERRUPTf, 613 L2_UPPER_MIN_SHAPER_REFRESH_CYCLE_INTERRUPT_DISINTf}, 614 { 0x40000, L2_LOWER_MIN_SHAPER_REFRESH_CYCLE_INTERRUPTf, 615 L2_LOWER_MIN_SHAPER_REFRESH_CYCLE_INTERRUPT_DISINTf}, 616 617 /* The following fields need to be left with reset value in 618 * lls_error_mask as recommended. These fields are used only 619 * for debugging */ 620 621 /* 622 { 0x20000, MAX_SHAPER_BUCKET_UNDERFLOW_PORTf, 623 MAX_SHAPER_BUCKET_UNDERFLOW_PORT_DISINTf}, 624 { 0x10000, MAX_SHAPER_BUCKET_UNDERFLOW_L0f, 625 MAX_SHAPER_BUCKET_UNDERFLOW_L0_DISINTf}, 626 { 0x8000, MAX_SHAPER_BUCKET_UNDERFLOW_L1f, 627 MAX_SHAPER_BUCKET_UNDERFLOW_L1_DISINTf}, 628 { 0x4000, MAX_SHAPER_BUCKET_UNDERFLOW_L2_UPPERf, 629 MAX_SHAPER_BUCKET_UNDERFLOW_L2_UPPER_DISINTf}, 630 { 0x2000, MAX_SHAPER_BUCKET_UNDERFLOW_L2_LOWERf, 631 MAX_SHAPER_BUCKET_UNDERFLOW_L2_LOWER_DISINTf}, 632 { 0x1000, MIN_SHAPER_BUCKET_UNDERFLOW_L0f, 633 MIN_SHAPER_BUCKET_UNDERFLOW_L0_DISINTf}, 634 { 0x0800, MIN_SHAPER_BUCKET_UNDERFLOW_L1f, 635 MIN_SHAPER_BUCKET_UNDERFLOW_L1_DISINTf}, 636 { 0x0400, MIN_SHAPER_BUCKET_UNDERFLOW_L2_UPPERf, 637 MIN_SHAPER_BUCKET_UNDERFLOW_L2_UPPER_DISINTf}, 638 { 0x0200, MIN_SHAPER_BUCKET_UNDERFLOW_L2_LOWERf, 639 MIN_SHAPER_BUCKET_UNDERFLOW_L2_LOWER_DISINTf}, 640 */ 641 { 0x0100, MAX_SHAPER_BUCKET_OVERFLOW_PORTf, 642 MAX_SHAPER_BUCKET_OVERFLOW_PORT_DISINTf}, 643 { 0x0080, MAX_SHAPER_BUCKET_OVERFLOW_L0f, 644 MAX_SHAPER_BUCKET_OVERFLOW_L0_DISINTf}, 645 { 0x0040, MAX_SHAPER_BUCKET_OVERFLOW_L1f, 646 MAX_SHAPER_BUCKET_OVERFLOW_L1_DISINTf}, 647 { 0x0020, MAX_SHAPER_BUCKET_OVERFLOW_L2_UPPERf, 648 MAX_SHAPER_BUCKET_OVERFLOW_L2_UPPER_DISINTf}, 649 { 0x0010, MAX_SHAPER_BUCKET_OVERFLOW_L2_LOWERf, 650 MAX_SHAPER_BUCKET_OVERFLOW_L2_LOWER_DISINTf}, 651 { 0x0008, MIN_SHAPER_BUCKET_OVERFLOW_L0f, 652 MIN_SHAPER_BUCKET_OVERFLOW_L0_DISINTf}, 653 { 0x0004, MIN_SHAPER_BUCKET_OVERFLOW_L1f, 654 MIN_SHAPER_BUCKET_OVERFLOW_L1_DISINTf}, 655 { 0x0002, MIN_SHAPER_BUCKET_OVERFLOW_L2_UPPERf, 656 MIN_SHAPER_BUCKET_OVERFLOW_L2_UPPER_DISINTf}, 657 { 0x0001, MIN_SHAPER_BUCKET_OVERFLOW_L2_LOWERf, 658 MIN_SHAPER_BUCKET_OVERFLOW_L2_LOWER_DISINTf}, 659 { 0 } /* table terminator */ 660 }; 661 /* LLS_ERROR_UPD2 */ 662 STATIC _soc_katana_mmu_sub_block_type_1_info_t 663 _soc_katana_mmu_sb_lls_upd2_parity_info [] = { 664 { 0x0100, UPD2_PORT_1_IN_4_VIOLATED_INTERRUPTf, 665 UPD2_PORT_1_IN_4_VIOLATED_INTERRUPT_DISINTf}, 666 667 /* The following fields need to be left with reset value in 668 * lls_error_upd2_mask as recommended. These fields are used only 669 * for debugging */ 670 671 /* 672 { 0x0080, UPD2_PORT_ERROR_UNDERRUN_INTERRUPTf, 673 UPD2_PORT_ERROR_UNDERRUN_INTERRUPT_DISINTf}, 674 { 0x0040, UPD2_PORT_ERROR_OVERFLOW_INTERRUPTf, 675 UPD2_PORT_ERROR_OVERFLOW_INTERRUPT_DISINTf}, 676 { 0x0020, UPD2_L0_ERROR_UNDERRUN_INTERRUPTf, 677 UPD2_L0_ERROR_UNDERRUN_INTERRUPT_DISINTf}, 678 { 0x0010, UPD2_L0_ERROR_OVERFLOW_INTERRUPTf, 679 UPD2_L0_ERROR_OVERFLOW_INTERRUPT_DISINTf}, 680 { 0x0008, UPD2_L1_ERROR_UNDERRUN_INTERRUPTf, 681 UPD2_L1_ERROR_UNDERRUN_INTERRUPT_DISINTf}, 682 { 0x0004, UPD2_L1_ERROR_OVERFLOW_INTERRUPTf, 683 UPD2_L1_ERROR_OVERFLOW_INTERRUPT_DISINTf}, 684 { 0x0002, UPD2_L2_ERROR_UNDERRUN_INTERRUPTf, 685 UPD2_L2_ERROR_UNDERRUN_INTERRUPT_DISINTf}, 686 { 0x0001, UPD2_L2_ERROR_OVERFLOW_INTERRUPTf, 687 UPD2_L2_ERROR_OVERFLOW_INTERRUPT_DISINTf}, 688 */ 689 { 0 } /* table terminator */ 690 691 }; 692 STATIC _soc_katana_mmu_sub_block_type_1_info_t 693 _soc_katana_mmu_sb_lls_port_parity_info [] = { 694 /* LLS_PORT_ECC_ERROR */ 695 { 0x0020, DB_PORT_TDM_CORRECTED_ERRORf, 696 DB_PORT_TDM_CORRECTED_ERROR_DISINTf}, 697 { 0x0010, DB_PORT_TDM_UNCORRECTED_ERRORf, 698 DB_PORT_TDM_UNCORRECTED_ERROR_DISINTf}, 699 { 0x0008, DB_PORT_SHAPER_CONFIG_C_CORRECTED_ERRORf, 700 DB_PORT_SHAPER_CONFIG_C_CORRECTED_ERROR_DISINTf}, 701 { 0x0004, DB_PORT_SHAPER_CONFIG_C_UNCORRECTED_ERRORf, 702 DB_PORT_SHAPER_CONFIG_C_UNCORRECTED_ERROR_DISINTf}, 703 { 0x0002, DB_PORT_WERR_MAX_SC_CORRECTED_ERRORf, 704 DB_PORT_WERR_MAX_SC_CORRECTED_ERROR_DISINTf}, 705 { 0x0001, DB_PORT_WERR_MAX_SC_UNCORRECTED_ERRORf, 706 DB_PORT_WERR_MAX_SC_UNCORRECTED_ERROR_DISINTf}, 707 { 0 } /* table terminator */ 708 709 }; 710 STATIC _soc_katana_mmu_sub_block_type_1_info_t 711 _soc_katana_mmu_sb_lls_l0_ecc_parity_info [] = { 712 /* LLS_L0_ECC_ERROR1 */ 713 { 0x8000000, DB_L0_MIN_NEXT_CORRECTED_ERRORf, 714 DB_L0_MIN_NEXT_CORRECTED_ERROR_DISINTf}, 715 { 0x4000000, DB_L0_MIN_NEXT_UNCORRECTED_ERRORf, 716 DB_L0_MIN_NEXT_UNCORRECTED_ERROR_DISINTf}, 717 { 0x2000000, DB_L0_PARENT_CORRECTED_ERRORf, 718 DB_L0_PARENT_CORRECTED_ERROR_DISINTf}, 719 { 0x1000000, DB_L0_PARENT_UNCORRECTED_ERRORf, 720 DB_L0_PARENT_UNCORRECTED_ERROR_DISINTf}, 721 { 0x800000, DB_L0_CONFIG_CORRECTED_ERRORf, 722 DB_L0_CONFIG_CORRECTED_ERROR_DISINTf}, 723 { 0x400000, DB_L0_CONFIG_UNCORRECTED_ERRORf, 724 DB_L0_CONFIG_UNCORRECTED_ERROR_DISINTf}, 725 { 0x200000, DB_L0_MIN_CONFIG_C_CORRECTED_ERRORf, 726 DB_L0_MIN_CONFIG_C_CORRECTED_ERROR_DISINTf}, 727 { 0x100000, DB_L0_MIN_CONFIG_C_UNCORRECTED_ERRORf, 728 DB_L0_MIN_CONFIG_C_UNCORRECTED_ERROR_DISINTf}, 729 { 0x80000, DB_L0_PARENT_STATE_CORRECTED_ERRORf, 730 DB_L0_PARENT_STATE_CORRECTED_ERROR_DISINTf}, 731 { 0x40000, DB_L0_PARENT_STATE_UNCORRECTED_ERRORf, 732 DB_L0_PARENT_STATE_UNCORRECTED_ERROR_DISINTf}, 733 { 0x20000, DB_L0_HEADS_TAILS_CORRECTED_ERRORf, 734 DB_L0_HEADS_TAILS_CORRECTED_ERROR_DISINTf}, 735 { 0x10000, DB_L0_HEADS_TAILS_UNCORRECTED_ERRORf, 736 DB_L0_HEADS_TAILS_UNCORRECTED_ERROR_DISINTf}, 737 { 0x8000, DB_L0_WERR_MAX_SC_CORRECTED_ERRORf, 738 DB_L0_WERR_MAX_SC_CORRECTED_ERROR_DISINTf}, 739 { 0x4000, DB_L0_WERR_MAX_SC_UNCORRECTED_ERRORf, 740 DB_L0_WERR_MAX_SC_UNCORRECTED_ERROR_DISINTf}, 741 { 0x2000, DB_L0_MIN_BUCKET_C_CORRECTED_ERRORf, 742 DB_L0_MIN_BUCKET_C_CORRECTED_ERROR_DISINTf}, 743 { 0x1000, DB_L0_MIN_BUCKET_C_UNCORRECTED_ERRORf, 744 DB_L0_MIN_BUCKET_C_UNCORRECTED_ERROR_DISINTf}, 745 { 0x0800, DB_L0_CHILD_STATE1_CORRECTED_ERRORf, 746 DB_L0_CHILD_STATE1_CORRECTED_ERROR_DISINTf}, 747 { 0x0400, DB_L0_CHILD_STATE1_UNCORRECTED_ERRORf, 748 DB_L0_CHILD_STATE1_UNCORRECTED_ERROR_DISINTf}, 749 { 0x0200, DB_L0_CHILD_WEIGHT_CFG_CNT_CORRECTED_ERRORf, 750 DB_L0_CHILD_WEIGHT_CFG_CNT_CORRECTED_ERROR_DISINTf}, 751 { 0x0100, DB_L0_CHILD_WEIGHT_CFG_CNT_UNCORRECTED_ERRORf, 752 DB_L0_CHILD_WEIGHT_CFG_CNT_UNCORRECTED_ERROR_DISINTf}, 753 { 0x0080, DB_L0_WERR_NEXT_CORRECTED_ERRORf, 754 DB_L0_WERR_NEXT_CORRECTED_ERROR_DISINTf}, 755 { 0x0040, DB_L0_WERR_NEXT_UNCORRECTED_ERRORf, 756 DB_L0_WERR_NEXT_UNCORRECTED_ERROR_DISINTf}, 757 { 0x0020, DB_L0_EF_NEXT_CORRECTED_ERRORf, 758 DB_L0_EF_NEXT_CORRECTED_ERROR_DISINTf}, 759 { 0x0010, DB_L0_EF_NEXT_UNCORRECTED_ERRORf, 760 DB_L0_EF_NEXT_UNCORRECTED_ERROR_DISINTf}, 761 { 0x0008, DB_L0_SHAPER_CONFIG_C_CORRECTED_ERRORf, 762 DB_L0_SHAPER_CONFIG_C_CORRECTED_ERROR_DISINTf}, 763 { 0x0004, DB_L0_SHAPER_CONFIG_C_UNCORRECTED_ERRORf, 764 DB_L0_SHAPER_CONFIG_C_UNCORRECTED_ERROR_DISINTf}, 765 { 0x0002, DB_L0_SHAPER_BUCKET_C_CORRECTED_ERRORf, 766 DB_L0_SHAPER_BUCKET_C_CORRECTED_ERROR_DISINTf}, 767 { 0x0001, DB_L0_SHAPER_BUCKET_C_UNCORRECTED_ERRORf, 768 DB_L0_SHAPER_BUCKET_C_UNCORRECTED_ERROR_DISINTf}, 769 { 0 } /* table terminator */ 770 771 }; 772 STATIC _soc_katana_mmu_sub_block_type_1_info_t 773 _soc_katana_mmu_sb_lls_l1_ecc_parity_info [] = { 774 /* LLS_L1_ECC_ERROR1 */ 775 { 0x8000000, DB_L1_MIN_NEXT_CORRECTED_ERRORf, 776 DB_L1_MIN_NEXT_CORRECTED_ERROR_DISINTf}, 777 { 0x4000000, DB_L1_MIN_NEXT_UNCORRECTED_ERRORf, 778 DB_L1_MIN_NEXT_UNCORRECTED_ERROR_DISINTf}, 779 { 0x2000000, DB_L1_PARENT_CORRECTED_ERRORf, 780 DB_L1_PARENT_CORRECTED_ERROR_DISINTf}, 781 { 0x1000000, DB_L1_PARENT_UNCORRECTED_ERRORf, 782 DB_L1_PARENT_UNCORRECTED_ERROR_DISINTf}, 783 { 0x800000, DB_L1_CONFIG_CORRECTED_ERRORf, 784 DB_L1_CONFIG_CORRECTED_ERROR_DISINTf}, 785 { 0x400000, DB_L1_CONFIG_UNCORRECTED_ERRORf, 786 DB_L1_CONFIG_UNCORRECTED_ERROR_DISINTf}, 787 { 0x200000, DB_L1_MIN_CONFIG_C_CORRECTED_ERRORf, 788 DB_L1_MIN_CONFIG_C_CORRECTED_ERROR_DISINTf}, 789 { 0x100000, DB_L1_MIN_CONFIG_C_UNCORRECTED_ERRORf, 790 DB_L1_MIN_CONFIG_C_UNCORRECTED_ERROR_DISINTf}, 791 { 0x80000, DB_L1_PARENT_STATE_CORRECTED_ERRORf, 792 DB_L1_PARENT_STATE_CORRECTED_ERROR_DISINTf}, 793 { 0x40000, DB_L1_PARENT_STATE_UNCORRECTED_ERRORf, 794 DB_L1_PARENT_STATE_UNCORRECTED_ERROR_DISINTf}, 795 { 0x20000, DB_L1_HEADS_TAILS_CORRECTED_ERRORf, 796 DB_L1_HEADS_TAILS_CORRECTED_ERROR_DISINTf}, 797 { 0x10000, DB_L1_HEADS_TAILS_UNCORRECTED_ERRORf, 798 DB_L1_HEADS_TAILS_UNCORRECTED_ERROR_DISINTf}, 799 { 0x8000, DB_L1_WERR_MAX_SC_CORRECTED_ERRORf, 800 DB_L1_WERR_MAX_SC_CORRECTED_ERROR_DISINTf}, 801 { 0x4000, DB_L1_WERR_MAX_SC_UNCORRECTED_ERRORf, 802 DB_L1_WERR_MAX_SC_UNCORRECTED_ERROR_DISINTf}, 803 { 0x2000, DB_L1_MIN_BUCKET_C_CORRECTED_ERRORf, 804 DB_L1_MIN_BUCKET_C_CORRECTED_ERROR_DISINTf}, 805 { 0x1000, DB_L1_MIN_BUCKET_C_UNCORRECTED_ERRORf, 806 DB_L1_MIN_BUCKET_C_UNCORRECTED_ERROR_DISINTf}, 807 { 0x0800, DB_L1_CHILD_STATE1_CORRECTED_ERRORf, 808 DB_L1_CHILD_STATE1_CORRECTED_ERROR_DISINTf}, 809 { 0x0400, DB_L1_CHILD_STATE1_UNCORRECTED_ERRORf, 810 DB_L1_CHILD_STATE1_UNCORRECTED_ERROR_DISINTf}, 811 { 0x0200, DB_L1_CHILD_WEIGHT_CFG_CNT_CORRECTED_ERRORf, 812 DB_L1_CHILD_WEIGHT_CFG_CNT_CORRECTED_ERROR_DISINTf}, 813 { 0x0100, DB_L1_CHILD_WEIGHT_CFG_CNT_UNCORRECTED_ERRORf, 814 DB_L1_CHILD_WEIGHT_CFG_CNT_UNCORRECTED_ERROR_DISINTf}, 815 { 0x0080, DB_L1_WERR_NEXT_CORRECTED_ERRORf, 816 DB_L1_WERR_NEXT_CORRECTED_ERROR_DISINTf}, 817 { 0x0040, DB_L1_WERR_NEXT_UNCORRECTED_ERRORf, 818 DB_L1_WERR_NEXT_UNCORRECTED_ERROR_DISINTf}, 819 { 0x0020, DB_L1_EF_NEXT_CORRECTED_ERRORf, 820 DB_L1_EF_NEXT_CORRECTED_ERROR_DISINTf}, 821 { 0x0010, DB_L1_EF_NEXT_UNCORRECTED_ERRORf, 822 DB_L1_EF_NEXT_UNCORRECTED_ERROR_DISINTf}, 823 { 0x0008, DB_L1_SHAPER_CONFIG_C_CORRECTED_ERRORf, 824 DB_L1_SHAPER_CONFIG_C_CORRECTED_ERROR_DISINTf}, 825 { 0x0004, DB_L1_SHAPER_CONFIG_C_UNCORRECTED_ERRORf, 826 DB_L1_SHAPER_CONFIG_C_UNCORRECTED_ERROR_DISINTf}, 827 { 0x0002, DB_L1_SHAPER_BUCKET_C_CORRECTED_ERRORf, 828 DB_L1_SHAPER_BUCKET_C_CORRECTED_ERROR_DISINTf}, 829 { 0x0001, DB_L1_SHAPER_BUCKET_C_UNCORRECTED_ERRORf, 830 DB_L1_SHAPER_BUCKET_C_UNCORRECTED_ERROR_DISINTf}, 831 { 0 } /* table terminator */ 832 }; 833 834 STATIC _soc_katana_mmu_sub_block_type_1_info_t 835 _soc_katana_mmu_sb_lls_l2_ecc_parity_info [] = { 836 /* LLS_L2_ECC_ERROR1 */ 837 { 0x2000000, DB_L2_MIN_CONFIG_UPPER_C_CORRECTED_ERRORf, 838 DB_L2_MIN_CONFIG_UPPER_C_CORRECTED_ERROR_DISINTf}, 839 { 0x1000000, DB_L2_MIN_CONFIG_UPPER_C_UNCORRECTED_ERRORf, 840 DB_L2_MIN_CONFIG_UPPER_C_UNCORRECTED_ERROR_DISINTf}, 841 { 0x800000, DB_L2_MIN_BUCKET_UPPER_C_CORRECTED_ERRORf, 842 DB_L2_MIN_BUCKET_UPPER_C_CORRECTED_ERROR_DISINTf}, 843 { 0x400000, DB_L2_MIN_BUCKET_UPPER_C_UNCORRECTED_ERRORf, 844 DB_L2_MIN_BUCKET_UPPER_C_UNCORRECTED_ERROR_DISINTf}, 845 { 0x200000, DB_L2_SHAPER_CONFIG_UPPER_C_CORRECTED_ERRORf, 846 DB_L2_SHAPER_CONFIG_UPPER_C_CORRECTED_ERROR_DISINTf}, 847 { 0x100000, DB_L2_SHAPER_CONFIG_UPPER_C_UNCORRECTED_ERRORf, 848 DB_L2_SHAPER_CONFIG_UPPER_C_UNCORRECTED_ERROR_DISINTf}, 849 { 0x80000, DB_L2_SHAPER_BUCKET_UPPER_C_CORRECTED_ERRORf, 850 DB_L2_SHAPER_BUCKET_UPPER_C_CORRECTED_ERROR_DISINTf}, 851 { 0x40000, DB_L2_SHAPER_BUCKET_UPPER_C_UNCORRECTED_ERRORf, 852 DB_L2_SHAPER_BUCKET_UPPER_C_UNCORRECTED_ERROR_DISINTf}, 853 { 0x20000, DB_L2_MIN_CONFIG_LOWER_C_CORRECTED_ERRORf, 854 DB_L2_MIN_CONFIG_LOWER_C_CORRECTED_ERROR_DISINTf}, 855 { 0x10000, DB_L2_MIN_CONFIG_LOWER_C_UNCORRECTED_ERRORf, 856 DB_L2_MIN_CONFIG_LOWER_C_UNCORRECTED_ERROR_DISINTf}, 857 { 0x8000, DB_L2_MIN_BUCKET_LOWER_C_CORRECTED_ERRORf, 858 DB_L2_MIN_BUCKET_LOWER_C_CORRECTED_ERROR_DISINTf}, 859 { 0x4000, DB_L2_MIN_BUCKET_LOWER_C_UNCORRECTED_ERRORf, 860 DB_L2_MIN_BUCKET_LOWER_C_UNCORRECTED_ERROR_DISINTf}, 861 { 0x2000, DB_L2_SHAPER_CONFIG_LOWER_C_CORRECTED_ERRORf, 862 DB_L2_SHAPER_CONFIG_LOWER_C_CORRECTED_ERROR_DISINTf}, 863 { 0x1000, DB_L2_SHAPER_CONFIG_LOWER_C_UNCORRECTED_ERRORf, 864 DB_L2_SHAPER_CONFIG_LOWER_C_UNCORRECTED_ERROR_DISINTf}, 865 { 0x0800, DB_L2_SHAPER_BUCKET_LOWER_C_CORRECTED_ERRORf, 866 DB_L2_SHAPER_BUCKET_LOWER_C_CORRECTED_ERROR_DISINTf}, 867 { 0x0400, DB_L2_SHAPER_BUCKET_LOWER_C_UNCORRECTED_ERRORf, 868 DB_L2_SHAPER_BUCKET_LOWER_C_UNCORRECTED_ERROR_DISINTf}, 869 { 0x0200, DB_L2_CHILD_STATE1_CORRECTED_ERRORf, 870 DB_L2_CHILD_STATE1_CORRECTED_ERROR_DISINTf}, 871 { 0x0100, DB_L2_CHILD_STATE1_UNCORRECTED_ERRORf, 872 DB_L2_CHILD_STATE1_UNCORRECTED_ERROR_DISINTf}, 873 { 0x0080, DB_L2_PARENT_CORRECTED_ERRORf, 874 DB_L2_PARENT_CORRECTED_ERROR_DISINTf}, 875 { 0x0040, DB_L2_PARENT_UNCORRECTED_ERRORf, 876 DB_L2_PARENT_UNCORRECTED_ERROR_DISINTf}, 877 { 0x0020, DB_L2_CHILD_WEIGHT_CFG_CNT_CORRECTED_ERRORf, 878 DB_L2_CHILD_WEIGHT_CFG_CNT_CORRECTED_ERROR_DISINTf}, 879 { 0x0010, DB_L2_CHILD_WEIGHT_CFG_CNT_UNCORRECTED_ERRORf, 880 DB_L2_CHILD_WEIGHT_CFG_CNT_UNCORRECTED_ERROR_DISINTf}, 881 { 0x0008, DB_L2_WERR_NEXT_CORRECTED_ERRORf, 882 DB_L2_WERR_NEXT_CORRECTED_ERROR_DISINTf}, 883 { 0x0004, DB_L2_WERR_NEXT_UNCORRECTED_ERRORf, 884 DB_L2_WERR_NEXT_UNCORRECTED_ERROR_DISINTf}, 885 { 0x0002, DB_L2_MIN_NEXT_CORRECTED_ERRORf, 886 DB_L2_MIN_NEXT_CORRECTED_ERROR_DISINTf}, 887 { 0x0001, DB_L2_MIN_NEXT_UNCORRECTED_ERRORf, 888 DB_L2_MIN_NEXT_UNCORRECTED_ERROR_DISINTf}, 889 { 0 } /* table terminator */ 890 }; 891 892 STATIC _soc_katana_mmu_sub_block_type_1_info_t 893 _soc_katana_mmu_sb_lls_misc_ecc_parity_info [] = { 894 /* LLS_MISC_ECC_ERROR1 */ 895 { 0x0800, DB_L2_ACT_XON_CORRECTED_ERRORf, 896 DB_L2_ACT_XON_CORRECTED_ERROR_DISINTf}, 897 { 0x0400, DB_L2_ACT_XON_UNCORRECTED_ERRORf, 898 DB_L2_ACT_XON_UNCORRECTED_ERROR_DISINTf}, 899 { 0x0200, DB_L2_ACT_SHAPER_CORRECTED_ERRORf, 900 DB_L2_ACT_SHAPER_CORRECTED_ERROR_DISINTf}, 901 { 0x0100, DB_L2_ACT_SHAPER_UNCORRECTED_ERRORf, 902 DB_L2_ACT_SHAPER_UNCORRECTED_ERROR_DISINTf}, 903 { 0x0080, DB_L2_ACT_MIN_CORRECTED_ERRORf, 904 DB_L2_ACT_MIN_CORRECTED_ERROR_DISINTf}, 905 { 0x0040, DB_L2_ACT_MIN_UNCORRECTED_ERRORf, 906 DB_L2_ACT_MIN_UNCORRECTED_ERROR_DISINTf}, 907 { 0x0020, DB_L0_ERROR_CORRECTED_ERRORf, 908 DB_L0_ERROR_CORRECTED_ERROR_DISINTf}, 909 { 0x0010, DB_L0_ERROR_UNCORRECTED_ERRORf, 910 DB_L0_ERROR_UNCORRECTED_ERROR_DISINTf}, 911 { 0x0008, DB_L1_ERROR_CORRECTED_ERRORf, 912 DB_L1_ERROR_CORRECTED_ERROR_DISINTf}, 913 { 0x0004, DB_L1_ERROR_UNCORRECTED_ERRORf, 914 DB_L1_ERROR_UNCORRECTED_ERROR_DISINTf}, 915 { 0x0002, DB_L2_ERROR_CORRECTED_ERRORf, 916 DB_L2_ERROR_CORRECTED_ERROR_DISINTf}, 917 { 0x0001, DB_L2_ERROR_UNCORRECTED_ERRORf, 918 DB_L2_ERROR_UNCORRECTED_ERROR_DISINTf}, 919 { 0 } /* table terminator */ 920 921 }; 922 923 924 STATIC _soc_katana_mmu_sub_block_type_1_info_t 925 _soc_katana_mmu_sb_mem1_parity_info [] = { 926 { 0x0008, CLINKE_CORRECTED_ERRORf, 927 CLINKE_CORRECTED_ERROR_DISINTf }, 928 { 0x0004, CLINKE_UNCORRECTED_ERRORf, 929 CLINKE_UNCORRECTED_ERROR_DISINTf }, 930 { 0x0002, CLINKI_CORRECTED_ERRORf, 931 CLINKI_CORRECTED_ERROR_DISINTf }, 932 { 0x0001, CLINKI_UNCORRECTED_ERRORf, 933 CLINKI_UNCORRECTED_ERROR_DISINTf }, 934 { 0 } /* table terminator */ 935 }; 936 937 STATIC _soc_katana_mmu_sub_block_type_1_info_t 938 _soc_katana_mmu_sb_e2efc_parity_info [] = { 939 { 0x0200, E2EFC_QEN_CNT_UNDERRUNf, 940 E2EFC_QEN_CNT_UNDERRUN_DISINTf}, 941 { 0x0100, E2EFC_QEN_CNT_OVERFLOWf, 942 E2EFC_QEN_CNT_OVERFLOW_DISINTf}, 943 { 0x0080, E2EFC_RQE_CNT_UNDERRUNf, 944 E2EFC_RQE_CNT_UNDERRUN_DISINTf}, 945 { 0x0040, E2EFC_RQE_CNT_OVERFLOWf, 946 E2EFC_RQE_CNT_OVERFLOW_DISINTf}, 947 { 0x0020, E2EFC_EMA_CNT_UNDERRUNf, 948 E2EFC_EMA_CNT_UNDERRUN_DISINTf}, 949 { 0x0010, E2EFC_EMA_CNT_OVERFLOWf, 950 E2EFC_EMA_CNT_OVERFLOW_DISINTf}, 951 { 0x0008, E2EFC_EXT_CNT_UNDERRUNf, 952 E2EFC_EXT_CNT_UNDERRUN_DISINTf}, 953 { 0x0004, E2EFC_EXT_CNT_OVERFLOWf, 954 E2EFC_EXT_CNT_OVERFLOW_DISINTf}, 955 { 0x0002, E2EFC_INT_CNT_UNDERRUNf, 956 E2EFC_INT_CNT_UNDERRUN_DISINTf}, 957 { 0x0001, E2EFC_INT_CNT_OVERFLOWf, 958 E2EFC_INT_CNT_OVERFLOW_DISINTf}, 959 { 0 } /* table terminator */ 960 }; 961 962 STATIC _soc_katana_mmu_sub_block_type_1_info_t 963 _soc_katana_mmu_sb_thdi_parity_info [] = { 964 { 0x0010, THDI_INTR_4f, THDI_INTR_4_DISINTf}, 965 { 0x0008, THDI_INTR_3f, THDI_INTR_3_DISINTf}, 966 { 0x0004, THDI_INTR_2f, THDI_INTR_2_DISINTf}, 967 { 0x0002, THDI_INTR_1f, THDI_INTR_1_DISINTf}, 968 { 0x0001, THDI_INTR_0f, THDI_INTR_0_DISINTf}, 969 { 0 } /* table terminator */ 970 }; 971 972 STATIC _soc_katana_mmu_sub_block_type_1_info_t 973 _soc_katana_mmu_sb_ctr_parity_info [] = { 974 { 0x0008, CTR_ENQ_WRAP_ERRORf, 975 CTR_ENQ_WRAP_ERROR_DISINTf}, 976 { 0x0004, CTR_DEQ_WRAP_ERRORf, 977 CTR_DEQ_WRAP_ERROR_DISINTf}, 978 { 0x0002, CTR_FLEX_CNT_CORRECTED_ERRORf, 979 CTR_FLEX_CNT_CORRECTED_ERROR_DISINTf}, 980 { 0x0001, CTR_FLEX_CNT_UNCORRECTED_ERRORf, 981 CTR_FLEX_CNT_UNCORRECTED_ERROR_DISINTf}, 982 { 0 } /* table terminator */ 983 }; 984 985 STATIC _soc_katana_mmu_sub_block_type_1_info_t 986 _soc_katana_mmu_sb_ccp_parity_info [] = { 987 { 0x0800, CCPE_SOP_HOLDUP_OVERLOADf, 988 CCPE_SOP_HOLDUP_OVERLOAD_DISINTf}, 989 { 0x0400, CCPI_SOP_HOLDUP_OVERLOADf, 990 CCPI_SOP_HOLDUP_OVERLOAD_DISINTf}, 991 { 0x0200, CCPE_BUFFER_TRACK_OVERLOADf, 992 CCPE_BUFFER_TRACK_OVERLOAD_DISINTf}, 993 { 0x0100, CCPI_BUFFER_TRACK_OVERLOADf, 994 CCPI_BUFFER_TRACK_OVERLOAD_DISINTf}, 995 { 0x0080, CCPI_ILLEGAL_SRCPG_INTRf, 996 CCPI_ILLEGAL_SRCPG_INTR_DISINTf}, 997 { 0x0040, CCPI_RQE_UPD_NEGATIVEf, 998 CCPI_RQE_UPD_NEGATIVE_DISINTf}, 999 { 0x0020, CCPE_ILLEGAL_SRCPG_INTRf, 1000 CCPE_ILLEGAL_SRCPG_INTR_DISINTf}, 1001 { 0x0010, CCPE_RQE_UPD_NEGATIVEf, 1002 CCPE_RQE_UPD_NEGATIVE_DISINTf}, 1003 { 0x0008, CCPE_CORRECTED_ERRORf, 1004 CCPE_CORRECTED_ERROR_DISINTf}, 1005 { 0x0004, CCPE_UNCORRECTED_ERRORf, 1006 CCPE_UNCORRECTED_ERROR_DISINTf}, 1007 { 0x0002, CCPI_CORRECTED_ERRORf, 1008 CCPI_CORRECTED_ERROR_DISINTf}, 1009 { 0x0001, CCPI_UNCORRECTED_ERRORf, 1010 CCPI_UNCORRECTED_ERROR_DISINTf}, 1011 { 0 } /* table terminator */ 1012 }; 1013 1014 STATIC _soc_katana_mmu_sub_block_type_1_info_t 1015 _soc_katana_mmu_sb_toq_parity_info [] = { 1016 { 0x10000, QEN_ALLOC_UNDERRUNf, 1017 QEN_ALLOC_UNDERRUN_DISINTf}, 1018 { 0x8000, QEN_ALLOC_OVERFLOWf, 1019 QEN_ALLOC_OVERFLOW_DISINTf}, 1020 { 0x4000, FLUSH_COMPLETEf, 1021 FLUSH_COMPLETE_DISINTf}, 1022 { 0x2000, QDIS_FIFO_OVERFLOWf, 1023 QDIS_FIFO_OVERFLOW_DISINTf}, 1024 { 0x1000, TRACE_DEQ_EVENTf, 1025 TRACE_DEQ_EVENT_DISINTf}, 1026 { 0x0800, TRACE_ENQ_EVENTf, 1027 TRACE_ENQ_EVENT_DISINTf}, 1028 { 0x0400, DEQ_TO_EMPTY_QUEUE_ERRORf, 1029 DEQ_TO_EMPTY_QUEUE_ERROR_DISINTf}, 1030 { 0x0200, QSTRUCT_EMPTY_ERRORf, 1031 QSTRUCT_EMPTY_ERROR_DISINTf}, 1032 { 0x0100, QUEUE_OVELOAD_ERRORf, 1033 QUEUE_OVELOAD_ERROR_DISINTf}, 1034 { 0x0080, TDM_VIOLATION_ERRORf, 1035 TDM_VIOLATION_ERROR_DISINTf}, 1036 { 0x0040, RQE_FIFO_OVERFLOWf, 1037 RQE_FIFO_OVERFLOW_DISINTf}, 1038 { 0x0020, RQE_FIFO_CORRECTED_ERRORf, 1039 RQE_FIFO_CORRECTED_ERROR_DISINTf}, 1040 { 0x0010, RQE_FIFO_UNCORRECTED_ERRORf, 1041 RQE_FIFO_UNCORRECTED_ERROR_DISINTf}, 1042 { 0x0008, IPMC_VLAN_TBL_CORRECTED_ERRORf, 1043 IPMC_VLAN_TBL_CORRECTED_ERROR_DISINTf}, 1044 { 0x0004, IPMC_VLAN_TBL_UNCORRECTED_ERRORf, 1045 IPMC_VLAN_TBL_UNCORRECTED_ERROR_DISINTf}, 1046 { 0x0002, TOQ_STATE_CORRECTED_ERRORf, 1047 TOQ_STATE_CORRECTED_ERROR_DISINTf}, 1048 { 0x0001, TOQ_STATE_UNCORRECTED_ERRORf, 1049 TOQ_STATE_UNCORRECTED_ERROR_DISINTf}, 1050 { 0 } /* table terminator */ 1051 }; 1052 1053 STATIC _soc_katana_mmu_sub_block_type_1_info_t 1054 _soc_katana_mmu_sb_ite_parity_info [] = { 1055 { 0x0008, ITE_WORK_QUEUE_RD_EMPTYf, 1056 ITE_WORK_QUEUE_RD_EMPTY_DISINTf}, 1057 { 0x0004, ITE_WORK_QUEUE_WR_FULLf, 1058 ITE_WORK_QUEUE_WR_FULL_DISINTf}, 1059 { 0x0002, ITE_CTRL_RD_EMPTYf, 1060 ITE_CTRL_RD_EMPTY_DISINTf}, 1061 { 0x0001, ITE_CTRL_WR_FULLf, 1062 ITE_CTRL_WR_FULL_DISINTf}, 1063 { 0 } /* table terminator */ 1064 }; 1065 1066 STATIC _soc_katana_mmu_sub_block_type_1_info_t 1067 _soc_katana_mmu_sb_ite_cfg_parity_info [] = { 1068 { 0x0200, PACKET_PTR_STORE_CORRECTED_ERRORf, 1069 PACKET_PTR_STORE_FORCE_CORRECTED_ERROR_DISINTf}, 1070 { 0x0100, PACKET_PTR_STORE_UNCORRECTED_ERRORf, 1071 PACKET_PTR_STORE_FORCE_UNCORRECTED_ERROR_DISINTf}, 1072 { 0x0080, ITE_WORK_QUEUE_CORRECTED_ERRORf, 1073 ITE_WORK_QUEUE_FORCE_CORRECTED_ERROR_DISINTf}, 1074 { 0x0040, ITE_WORK_QUEUE_UNCORRECTED_ERRORf, 1075 ITE_WORK_QUEUE_FORCE_UNCORRECTED_ERROR_DISINTf}, 1076 { 0x0020, ITE_CTRL_CORRECTED_ERRORf, 1077 ITE_CTRL_CORRECTED_ERROR_DISINTf}, 1078 { 0x0010, ITE_CTRL_UNCORRECTED_ERRORf, 1079 ITE_CTRL_UNCORRECTED_ERROR_DISINTf}, 1080 { 0x0008, ITE_QMGR_FLL_CORRECTED_ERRORf, 1081 ITE_QMGR_FLL_FORCE_CORRECTED_ERROR_DISINTf}, 1082 { 0x0004, ITE_QMGR_FLL_UNCORRECTED_ERRORf, 1083 ITE_QMGR_FLL_FORCE_UNCORRECTED_ERROR_DISINTf}, 1084 { 0x0002, ITE_QMGR_QLL_CORRECTED_ERRORf, 1085 ITE_QMGR_QLL_CORRECTED_ERROR_DISINTf}, 1086 { 0x0001, ITE_QMGR_QLL_UNCORRECTED_ERRORf, 1087 ITE_QMGR_QLL_UNCORRECTED_ERROR_DISINTf}, 1088 { 0 } /* table terminator */ 1089 }; 1090 1091 STATIC _soc_katana_mmu_sub_block_type_1_info_t 1092 _soc_katana_mmu_sb_enq_cfg_parity_info [] = { 1093 { 0x0020, CBI_CORRECTED_ERRORf, 1094 CBI_CORRECTED_ERROR_DISINTf}, 1095 { 0x0010, CBI_UNCORRECTED_ERRORf, 1096 CBI_UNCORRECTED_ERROR_DISINTf}, 1097 { 0x0008, RQE_WR_COMPLETE_CORRECTED_ERRORf, 1098 RQE_WR_COMPLETE_CORRECTED_ERROR_DISINTf}, 1099 { 0x0004, RQE_WR_COMPLETE_UNCORRECTED_ERRORf, 1100 RQE_WR_COMPLETE_UNCORRECTED_ERROR_DISINTf}, 1101 { 0x0002, CBP_32B_WR_STORE_CORRECTED_ERRORf, 1102 CBP_32B_WR_STORE_CORRECTED_ERROR_DISINTf}, 1103 { 0x0001, CBP_32B_WR_STORE_UNCORRECTED_ERRORf, 1104 CBP_32B_WR_STORE_UNCORRECTED_ERROR_DISINTf}, 1105 { 0 } /* table terminator */ 1106 }; 1107 1108 STATIC _soc_katana_mmu_sub_block_type_1_info_t 1109 _soc_katana_mmu_sb_enq_parity_info [] = { 1110 { 0x0010, FAP_DUPLICATE_PTRf, 1111 FAP_DUPLICATE_PTR_DISINTf}, 1112 { 0x0008, ENQ_TRACE_STATUSf, 1113 ENQ_TRACE_STATUS_DISINTf}, 1114 { 0x0004, ILLEGAL_CELL_PBIf, 1115 ILLEGAL_CELL_PBI_DISINTf}, 1116 { 0x0002, MISSING_START_ERRf, 1117 MISSING_START_ERR_DISINTf}, 1118 { 0x0001, START_BY_START_ERRf, 1119 START_BY_START_ERR_DISINTf}, 1120 { 0 } /* table terminator */ 1121 }; 1122 1123 1124 STATIC _soc_katana_mmu_sub_block_type_1_info_t 1125 _soc_katana_mmu_sb_enq_fap_parity_info [] = { 1126 { 0x0008, FAP_STACK_CORRECTED_ERRORf, 1127 FAP_STACK_CORRECTED_ERROR_DISINTf}, 1128 { 0x0004, FAP_STACK_UNCORRECTED_ERRORf, 1129 FAP_STACK_UNCORRECTED_ERROR_ERROR_DISINTf}, 1130 { 0x0002, FAP_BITMAP_CORRECTED_ERRORf, 1131 FAP_BITMAP_CORRECTED_ERROR_DISINTf}, 1132 { 0x0001, FAP_BITMAP_UNCORRECTED_ERRORf, 1133 FAP_BITMAP_UNCORRECTED_ERROR_DISINTf}, 1134 { 0 } /* table terminator */ 1135 }; 1136 1137 STATIC _soc_katana_mmu_sub_block_type_1_info_t 1138 _soc_katana_mmu_sb_thdo_stat1_parity_info [] = { 1139 { 0x3ffff, ECC_1B_ERROR_STATUSf, ECC_1B_MASKf}, 1140 { 0 } /* table terminator */ 1141 }; 1142 STATIC _soc_katana_mmu_sub_block_type_1_info_t 1143 _soc_katana_mmu_sb_thdo_stat2_parity_info [] = { 1144 { 0x3ffff, ECC_2B_ERROR_STATUSf, ECC_2B_MASKf}, 1145 { 0 } /* table terminator */ 1146 }; 1147 1148 STATIC _soc_katana_mmu_sub_block_type_1_info_t 1149 _soc_katana_mmu_sb_cfapi_parity_info [] = { 1150 { 0x0010, DUPLICATE_PTRf, 1151 DUPLICATE_PTR_DISINTf}, 1152 { 0x0008, BITMAP_CORRECTED_ERRORf, 1153 BITMAP_CORRECTED_ERROR_DISINTf}, 1154 { 0x0004, BITMAP_UNCORRECTED_ERRORf, 1155 BITMAP_UNCORRECTED_ERROR_DISINTf}, 1156 { 0x0002, STACK_CORRECTED_ERRORf, 1157 STACK_CORRECTED_ERROR_DISINTf}, 1158 { 0x0001, STACK_UNCORRECTED_ERRORf, 1159 STACK_UNCORRECTED_ERROR_DISINTf}, 1160 { 0 } /* table terminator */ 1161 }; 1162 1163 STATIC _soc_katana_mmu_sub_block_type_1_info_t 1164 _soc_katana_mmu_sb_cfape_parity_info [] = { 1165 { 0x0010, DUPLICATE_PTRf, 1166 DUPLICATE_PTR_DISINTf}, 1167 { 0x0008, BITMAP_CORRECTED_ERRORf, 1168 BITMAP_CORRECTED_ERROR_DISINTf}, 1169 { 0x0004, BITMAP_UNCORRECTED_ERRORf, 1170 BITMAP_UNCORRECTED_ERROR_DISINTf}, 1171 { 0x0002, STACK_CORRECTED_ERRORf, 1172 STACK_CORRECTED_ERROR_DISINTf}, 1173 { 0x0001, STACK_UNCORRECTED_ERRORf, 1174 STACK_UNCORRECTED_ERROR_DISINTf}, 1175 { 0 } /* table terminator */ 1176 }; 1177 1178 STATIC _soc_katana_mmu_sub_block_type_1_info_t 1179 _soc_katana_mmu_sb_age_int_parity_info [] = { 1180 { 0x0020, LMT_CORRECTED_ERRORf, LMT_CORRECTED_ERROR_DISINTf}, 1181 { 0x0010, LMT_UNCORRECTED_ERRORf, LMT_UNCORRECTED_ERROR_DISINTf}, 1182 { 0x0008, CTR_CORRECTED_ERRORf, CTR_CORRECTED_ERROR_DISINTf}, 1183 { 0x0004, CTR_UNCORRECTED_ERRORf, CTR_UNCORRECTED_ERROR_DISINTf}, 1184 { 0x0002, EXP_CORRECTED_ERRORf, EXP_CORRECTED_ERROR_DISINTf}, 1185 { 0x0001, EXP_UNCORRECTED_ERRORf, EXP_UNCORRECTED_ERROR_DISINTf}, 1186 { 0 } /* table terminator */ 1187 }; 1188 1189 STATIC _soc_katana_mmu_sub_block_type_1_info_t 1190 _soc_katana_mmu_sb_age_ext_parity_info [] = { 1191 { 0x0020, LMT_CORRECTED_ERRORf, LMT_CORRECTED_ERROR_DISINTf}, 1192 { 0x0010, LMT_UNCORRECTED_ERRORf, LMT_UNCORRECTED_ERROR_DISINTf}, 1193 { 0x0008, CTR_CORRECTED_ERRORf, CTR_CORRECTED_ERROR_DISINTf}, 1194 { 0x0004, CTR_UNCORRECTED_ERRORf, CTR_UNCORRECTED_ERROR_DISINTf}, 1195 { 0x0002, EXP_CORRECTED_ERRORf, EXP_CORRECTED_ERROR_DISINTf}, 1196 { 0x0001, EXP_UNCORRECTED_ERRORf, EXP_UNCORRECTED_ERROR_DISINTf}, 1197 { 0 } /* table terminator */ 1198 }; 1199 1200 STATIC _soc_katana_mmu_sub_block_type_1_info_t 1201 _soc_katana_mmu_sb_intfi_parity_info [] = { 1202 { 0x0004, HCFC_EARLY_SYNC_DETECTf, 1203 HCFC_EARLY_SYNC_DETECT_DISINTf}, 1204 { 0x0002, HCFC_MSG_DROPPEDf, 1205 HCFC_MSG_DROPPED_DISINTf}, 1206 { 0x0001, HCFC_CRC_DROP_VALIDf, 1207 HCFC_CRC_DROP_VALID_DISINTf}, 1208 { 0 } /* table terminator */ 1209 }; 1210 1211 STATIC _soc_katana_mmu_sub_block_type_2_info_t 1212 _soc_katana_mmu_sb_intfi_ecc_parity_info [] = { 1213 /* error status mask is actually at bit positon 4 */ 1214 { 0x0002, 0x0010, FC_BASE_CORRECTED_ERRORf, 1215 FC_BASE_CORRECTED_ERROR_DISINTf}, 1216 /* error status mask is actually at bit positon 3 */ 1217 { 0x0001, 0x0008, FC_BASE_UNCORRECTED_ERRORf, 1218 FC_BASE_UNCORRECTED_ERROR_DISINTf}, 1219 { 0 } /* table terminator */ 1220 1221 }; 1222 1223 STATIC _soc_katana_mmu_sub_block_type_1_info_t 1224 _soc_katana_mmu_sb_ci2_parity_info [] = { 1225 { 0x0100, PHY_READY_EVENTf, 1226 PHY_READYf}, 1227 { 0x0080, PHY_BL1_RD_FIFO_ERRORf, 1228 PHY_BL1_RD_FIFO_ERRORf}, 1229 { 0x0040, PHY_BL0_RD_FIFO_ERRORf, 1230 PHY_BL0_RD_FIFO_ERRORf}, 1231 { 0x0020, WFIFO_CTL_CORRECTED_ERRORf, 1232 WFIFO_CTL_CORRECTED_ERROR_DISINTf}, 1233 { 0x0010, WFIFO_CTL_UNCORRECTED_ERRORf, 1234 WFIFO_CTL_UNCORRECTED_ERROR_DISINTf}, 1235 { 0x0008, WFIFO_OVERFLOWf, 1236 WB_OVERFLOW_DISINTf}, 1237 { 0x0004, RFIFO_CTL_CORRECTED_ERRORf, 1238 RFIFO_CTL_CORRECTED_ERROR_DISINTf}, 1239 { 0x0002, RFIFO_CTL_UNCORRECTED_ERRORf, 1240 RFIFO_CTL_UNCORRECTED_ERROR_DISINTf}, 1241 { 0x0001, RFIFO_OVERFLOWf, 1242 RFIFO_OVERFLOW_DISINTf}, 1243 { 0 } /* table terminator */ 1244 1245 }; 1246 1247 STATIC _soc_katana_mmu_sub_block_type_1_info_t 1248 _soc_katana_mmu_sb_ci1_parity_info [] = { 1249 { 0x0100, PHY_READY_EVENTf, 1250 PHY_READYf}, 1251 { 0x0080, PHY_BL1_RD_FIFO_ERRORf, 1252 PHY_BL1_RD_FIFO_ERRORf}, 1253 { 0x0040, PHY_BL0_RD_FIFO_ERRORf, 1254 PHY_BL0_RD_FIFO_ERRORf}, 1255 { 0x0020, WFIFO_CTL_CORRECTED_ERRORf, 1256 WFIFO_CTL_CORRECTED_ERROR_DISINTf}, 1257 { 0x0010, WFIFO_CTL_UNCORRECTED_ERRORf, 1258 WFIFO_CTL_UNCORRECTED_ERROR_DISINTf}, 1259 { 0x0008, WFIFO_OVERFLOWf, 1260 WB_OVERFLOW_DISINTf}, 1261 { 0x0004, RFIFO_CTL_CORRECTED_ERRORf, 1262 RFIFO_CTL_CORRECTED_ERROR_DISINTf}, 1263 { 0x0002, RFIFO_CTL_UNCORRECTED_ERRORf, 1264 RFIFO_CTL_UNCORRECTED_ERROR_DISINTf}, 1265 { 0x0001, RFIFO_OVERFLOWf, 1266 RFIFO_OVERFLOW_DISINTf}, 1267 { 0 } /* table terminator */ 1268 1269 }; 1270 1271 STATIC _soc_katana_mmu_sub_block_type_1_info_t 1272 _soc_katana_mmu_sb_ci0_parity_info [] = { 1273 { 0x0100, PHY_READY_EVENTf, 1274 PHY_READYf}, 1275 { 0x0080, PHY_BL1_RD_FIFO_ERRORf, 1276 PHY_BL1_RD_FIFO_ERRORf}, 1277 { 0x0040, PHY_BL0_RD_FIFO_ERRORf, 1278 PHY_BL0_RD_FIFO_ERRORf}, 1279 { 0x0020, WFIFO_CTL_CORRECTED_ERRORf, 1280 WFIFO_CTL_CORRECTED_ERROR_DISINTf}, 1281 { 0x0010, WFIFO_CTL_UNCORRECTED_ERRORf, 1282 WFIFO_CTL_UNCORRECTED_ERROR_DISINTf}, 1283 { 0x0008, WFIFO_OVERFLOWf, 1284 WB_OVERFLOW_DISINTf}, 1285 { 0x0004, RFIFO_CTL_CORRECTED_ERRORf, 1286 RFIFO_CTL_CORRECTED_ERROR_DISINTf}, 1287 { 0x0002, RFIFO_CTL_UNCORRECTED_ERRORf, 1288 RFIFO_CTL_UNCORRECTED_ERROR_DISINTf}, 1289 { 0x0001, RFIFO_OVERFLOWf, 1290 RFIFO_OVERFLOW_DISINTf}, 1291 { 0 } /* table terminator */ 1292 }; 1293 1294 1295 STATIC 1296 _soc_katana_mmu_sub_block_type_1_info_t 1297 _soc_katana_mmu_sb_emc0_parity_info [] = { 1298 { 0x0004, EMC_WTAC_ILLEGAL_SRCPG_ERRORf, 1299 EMC_WTAC_ILLEGAL_SRCPG_ERROR_DISINTf }, 1300 { 0x0002, EMC_IRRB_BUFFER_OVERFLOW_ERRORf, 1301 EMC_IRRB_BUFFER_OVERFLOW_ERROR_DISINTf }, 1302 { 0x0001, EMC_IWRB_BUFFER_OVERFLOW_ERRORf, 1303 EMC_IWRB_BUFFER_OVERFLOW_ERROR_DISINTf }, 1304 { 0 } /* table terminator */ 1305 }; 1306 1307 STATIC 1308 _soc_katana_mmu_sub_block_type_1_info_t 1309 _soc_katana_mmu_sb_emc1_parity_info [] = { 1310 { 0x8000000, EMC_CSDB_2_UPPER_BUFFER_UNCORRECTED_ERRORf, 1311 EMC_CSDB_2_UPPER_BUFFER_UNCORRECTED_ERROR_DISINTf}, 1312 { 0x4000000, EMC_CSDB_2_LOWER_BUFFER_UNCORRECTED_ERRORf, 1313 EMC_CSDB_2_LOWER_BUFFER_UNCORRECTED_ERROR_DISINTf}, 1314 { 0x2000000, EMC_CSDB_1_UPPER_BUFFER_UNCORRECTED_ERRORf, 1315 EMC_CSDB_1_UPPER_BUFFER_UNCORRECTED_ERROR_DISINTf}, 1316 { 0x1000000, EMC_CSDB_1_LOWER_BUFFER_UNCORRECTED_ERRORf, 1317 EMC_CSDB_1_LOWER_BUFFER_UNCORRECTED_ERROR_DISINTf}, 1318 { 0x800000, EMC_CSDB_0_UPPER_BUFFER_UNCORRECTED_ERRORf, 1319 EMC_CSDB_0_UPPER_BUFFER_UNCORRECTED_ERROR_DISINTf}, 1320 { 0x400000, EMC_CSDB_0_LOWER_BUFFER_UNCORRECTED_ERRORf, 1321 EMC_CSDB_0_LOWER_BUFFER_UNCORRECTED_ERROR_DISINTf}, 1322 { 0x200000, EMC_ERRB_BUFFER_UNCORRECTED_ERRORf, 1323 EMC_ERRB_BUFFER_UNCORRECTED_ERROR_DISINTf}, 1324 { 0x100000, EMC_ERRB_BUFFER_CORRECTED_ERRORf, 1325 EMC_ERRB_BUFFER_CORRECTED_ERROR_DISINTf}, 1326 { 0x80000, EMC_RFCQ_BUFFER_UNCORRECTED_ERRORf, 1327 EMC_RFCQ_BUFFER_UNCORRECTED_ERROR_DISINTf}, 1328 { 0x40000, EMC_RFCQ_BUFFER_CORRECTED_ERRORf, 1329 EMC_RFCQ_BUFFER_CORRECTED_ERROR_DISINTf}, 1330 { 0x20000, EMC_RSFP_BUFFER_UNCORRECTED_ERRORf, 1331 EMC_RSFP_BUFFER_UNCORRECTED_ERROR_DISINTf}, 1332 { 0x10000, EMC_RSFP_BUFFER_CORRECTED_ERRORf, 1333 EMC_RSFP_BUFFER_CORRECTED_ERROR_DISINTf}, 1334 { 0x8000, EMC_IRRB_BUFFER_UNCORRECTED_ERRORf, 1335 EMC_IRRB_BUFFER_UNCORRECTED_ERROR_DISINTf}, 1336 { 0x4000, EMC_IRRB_BUFFER_CORRECTED_ERRORf, 1337 EMC_IRRB_BUFFER_CORRECTED_ERROR_DISINTf}, 1338 { 0x2000, EMC_EWRB_BUFFER_1_UNCORRECTED_ERRORf, 1339 EMC_EWRB_BUFFER_1_UNCORRECTED_ERROR_DISINTf}, 1340 { 0x1000, EMC_EWRB_BUFFER_1_CORRECTED_ERRORf, 1341 EMC_EWRB_BUFFER_1_CORRECTED_ERROR_DISINTf}, 1342 { 0x0800, EMC_EWRB_BUFFER_0_UNCORRECTED_ERRORf, 1343 EMC_EWRB_BUFFER_0_UNCORRECTED_ERROR_DISINTf}, 1344 { 0x0400, EMC_EWRB_BUFFER_0_CORRECTED_ERRORf, 1345 EMC_EWRB_BUFFER_0_CORRECTED_ERROR_DISINTf}, 1346 { 0x0200, EMC_WCMT_BUFFER_UNCORRECTED_ERRORf, 1347 EMC_WCMT_BUFFER_UNCORRECTED_ERROR_DISINTf}, 1348 { 0x0100, EMC_WCMT_BUFFER_CORRECTED_ERRORf, 1349 EMC_WCMT_BUFFER_CORRECTED_ERROR_DISINTf}, 1350 { 0x0080, EMC_SWAT_BUFFER_UNCORRECTED_ERRORf, 1351 EMC_SWAT_BUFFER_UNCORRECTED_ERROR_DISINTf}, 1352 { 0x0040, EMC_SWAT_BUFFER_CORRECTED_ERRORf, 1353 EMC_SWAT_BUFFER_CORRECTED_ERROR_DISINTf}, 1354 { 0x0020, EMC_WTOQ_BUFFER_UNCORRECTED_ERRORf, 1355 EMC_WTOQ_BUFFER_UNCORRECTED_ERROR_DISINTf}, 1356 { 0x0010, EMC_WTOQ_BUFFER_CORRECTED_ERRORf, 1357 EMC_WTOQ_BUFFER_CORRECTED_ERROR_DISINTf}, 1358 { 0x0008, EMC_WTFP_BUFFER_UNCORRECTED_ERRORf, 1359 EMC_WTFP_BUFFER_UNCORRECTED_ERROR_DISINTf}, 1360 { 0x0004, EMC_WTFP_BUFFER_CORRECTED_ERRORf, 1361 EMC_WTFP_BUFFER_CORRECTED_ERROR_DISINTf}, 1362 { 0x0002, EMC_IWRB_BUFFER_UNCORRECTED_ERRORf, 1363 EMC_IWRB_BUFFER_UNCORRECTED_ERROR_DISINTf}, 1364 { 0x0001, EMC_IWRB_BUFFER_CORRECTED_ERRORf, 1365 EMC_IWRB_BUFFER_CORRECTED_ERROR_DISINTf}, 1366 { 0 } /* table terminator */ 1367 }; 1368 1369 STATIC 1370 _soc_katana_mmu_sub_block_type_1_info_t 1371 _soc_katana_mmu_sb_emc2_parity_info [] = { 1372 { 0x0800000, EMC_WLCT2_UPPER_B_BUFFER_UNCORRECTED_ERRORf, 1373 EMC_WLCT2_UPPER_B_BUFFER_UNCORRECTED_ERROR_DISINTf}, 1374 { 0x0400000, EMC_WLCT2_UPPER_B_BUFFER_CORRECTED_ERRORf, 1375 EMC_WLCT2_UPPER_B_BUFFER_CORRECTED_ERROR_DISINTf}, 1376 { 0x0200000, EMC_WLCT2_UPPER_A_BUFFER_UNCORRECTED_ERRORf, 1377 EMC_WLCT2_UPPER_A_BUFFER_UNCORRECTED_ERROR_DISINTf}, 1378 { 0x0100000, EMC_WLCT2_UPPER_A_BUFFER_CORRECTED_ERRORf, 1379 EMC_WLCT2_UPPER_A_BUFFER_CORRECTED_ERROR_DISINTf}, 1380 { 0x0080000, EMC_WLCT2_LOWER_B_BUFFER_UNCORRECTED_ERRORf, 1381 EMC_WLCT2_LOWER_B_BUFFER_UNCORRECTED_ERROR_DISINTf}, 1382 { 0x0040000, EMC_WLCT2_LOWER_B_BUFFER_CORRECTED_ERRORf, 1383 EMC_WLCT2_LOWER_B_BUFFER_CORRECTED_ERROR_DISINTf}, 1384 { 0x0020000, EMC_WLCT2_LOWER_A_BUFFER_UNCORRECTED_ERRORf, 1385 EMC_WLCT2_LOWER_A_BUFFER_UNCORRECTED_ERROR_DISINTf}, 1386 { 0x0010000, EMC_WLCT2_LOWER_A_BUFFER_CORRECTED_ERRORf, 1387 EMC_WLCT2_LOWER_A_BUFFER_CORRECTED_ERROR_DISINTf}, 1388 { 0x0008000, EMC_WLCT1_UPPER_B_BUFFER_UNCORRECTED_ERRORf, 1389 EMC_WLCT1_UPPER_B_BUFFER_UNCORRECTED_ERROR_DISINTf}, 1390 { 0x0004000, EMC_WLCT1_UPPER_B_BUFFER_CORRECTED_ERRORf, 1391 EMC_WLCT1_UPPER_B_BUFFER_CORRECTED_ERROR_DISINTf}, 1392 { 0x0002000, EMC_WLCT1_UPPER_A_BUFFER_UNCORRECTED_ERRORf, 1393 EMC_WLCT1_UPPER_A_BUFFER_UNCORRECTED_ERROR_DISINTf}, 1394 { 0x0001000, EMC_WLCT1_UPPER_A_BUFFER_CORRECTED_ERRORf, 1395 EMC_WLCT1_UPPER_A_BUFFER_CORRECTED_ERROR_DISINTf}, 1396 { 0x0000800, EMC_WLCT1_LOWER_B_BUFFER_UNCORRECTED_ERRORf, 1397 EMC_WLCT1_LOWER_B_BUFFER_UNCORRECTED_ERROR_DISINTf}, 1398 { 0x0000400, EMC_WLCT1_LOWER_B_BUFFER_CORRECTED_ERRORf, 1399 EMC_WLCT1_LOWER_B_BUFFER_CORRECTED_ERROR_DISINTf}, 1400 { 0x0000200, EMC_WLCT1_LOWER_A_BUFFER_UNCORRECTED_ERRORf, 1401 EMC_WLCT1_LOWER_A_BUFFER_UNCORRECTED_ERROR_DISINTf}, 1402 { 0x0000100, EMC_WLCT1_LOWER_A_BUFFER_CORRECTED_ERRORf, 1403 EMC_WLCT1_LOWER_A_BUFFER_CORRECTED_ERROR_DISINTf}, 1404 { 0x0000080, EMC_WLCT0_UPPER_B_BUFFER_UNCORRECTED_ERRORf, 1405 EMC_WLCT0_UPPER_B_BUFFER_UNCORRECTED_ERROR_DISINTf}, 1406 { 0x0000040, EMC_WLCT0_UPPER_B_BUFFER_CORRECTED_ERRORf, 1407 EMC_WLCT0_UPPER_B_BUFFER_CORRECTED_ERROR_DISINTf}, 1408 { 0x0000020, EMC_WLCT0_UPPER_A_BUFFER_UNCORRECTED_ERRORf, 1409 EMC_WLCT0_UPPER_A_BUFFER_UNCORRECTED_ERROR_DISINTf}, 1410 { 0x0000010, EMC_WLCT0_UPPER_A_BUFFER_CORRECTED_ERRORf, 1411 EMC_WLCT0_UPPER_A_BUFFER_CORRECTED_ERROR_DISINTf}, 1412 { 0x0000008, EMC_WLCT0_LOWER_B_BUFFER_UNCORRECTED_ERRORf, 1413 EMC_WLCT0_LOWER_B_BUFFER_UNCORRECTED_ERROR_DISINTf}, 1414 { 0x0000004, EMC_WLCT0_LOWER_B_BUFFER_CORRECTED_ERRORf, 1415 EMC_WLCT0_LOWER_B_BUFFER_CORRECTED_ERROR_DISINTf}, 1416 { 0x0000002, EMC_WLCT0_LOWER_A_BUFFER_UNCORRECTED_ERRORf, 1417 EMC_WLCT0_LOWER_A_BUFFER_UNCORRECTED_ERROR_DISINTf}, 1418 { 0x0000001, EMC_WLCT0_LOWER_A_BUFFER_CORRECTED_ERRORf, 1419 EMC_WLCT0_LOWER_A_BUFFER_CORRECTED_ERROR_DISINTf}, 1420 { 0 } /* table terminator */ 1421 }; 1422 1423 STATIC 1424 _soc_katana_mmu_sub_block_type_3_info_t 1425 _soc_katana_mmu_sb_emc_parity_info [] = { 1426 { 0x0004, _SOC_KT_MMU_LVL2_SUBBLOCK_EMC_ERROR_2, EMC_ERRORr, 0, 1427 EMC_ERROR_2f, 0, _soc_katana_mmu_sb_emc2_parity_info }, 1428 { 0x0002, _SOC_KT_MMU_LVL2_SUBBLOCK_EMC_ERROR_1, EMC_ERRORr, 0, 1429 EMC_ERROR_1f, 0, _soc_katana_mmu_sb_emc1_parity_info }, 1430 { 0x0001, _SOC_KT_MMU_LVL2_SUBBLOCK_EMC_ERROR_0, EMC_ERRORr, 0, 1431 EMC_ERROR_0f, 0, _soc_katana_mmu_sb_emc0_parity_info }, 1432 { 0 } /* table terminator */ 1433 }; 1434 1435 STATIC 1436 _soc_katana_mmu_sub_block_type_1_info_t 1437 _soc_katana_mmu_sb_deq0_parity_info [] = { 1438 { 0x0020, DEQ_TRACE_EVENTf, DEQ_TRACE_EVENT_DISINTf}, 1439 { 0x0010, CCPE_BUFFER_OVERFLOW_ERRORf, CCPE_BUFFER_OVERFLOW_ERROR_DISINTf}, 1440 { 0x0008, EGRESS_FIFO_OVERFLOW_ERRORf, 1441 EGRESS_FIFO_OVERFLOW_ERROR_DISINTf}, 1442 { 0x0004, EGRESS_FIFO_UNDERRUN_ERRORf, 1443 EGRESS_FIFO_UNDERRUN_ERROR_DISINTf}, 1444 { 0x0002, TOQ_TO_DEQ_CELL_REP_INFO_BUFFER_RD_REQ_ERRORf, 1445 DEQ_TO_CFG_TOQ_TO_DEQ_CELL_REP_INFO_BUFFER_RD_REQ_ERROR_DISINTf}, 1446 { 0x0001, TOQ_TO_DEQ_CELL_REP_INFO_BUFFER_WR_REQ_ERRORf, 1447 DEQ_TO_CFG_TOQ_TO_DEQ_CELL_REP_INFO_BUFFER_WR_REQ_ERROR_DISINTf}, 1448 { 0 } /* table terminator */ 1449 }; 1450 1451 STATIC 1452 _soc_katana_mmu_sub_block_type_1_info_t 1453 _soc_katana_mmu_sb_deq1_parity_info [] = { 1454 { 0x0008, PORT_35_EFIFO_UNDERRUN_ERRORf, 1455 PORT_35_EFIFO_UNDERRUN_ERROR_DISINTf}, 1456 { 0x0004, PORT_34_EFIFO_UNDERRUN_ERRORf, 1457 PORT_34_EFIFO_UNDERRUN_ERROR_DISINTf}, 1458 { 0x0002, PORT_33_EFIFO_UNDERRUN_ERRORf, 1459 PORT_33_EFIFO_UNDERRUN_ERROR_DISINTf}, 1460 { 0x0001, PORT_32_EFIFO_UNDERRUN_ERRORf, 1461 PORT_32_EFIFO_UNDERRUN_ERROR_DISINTf}, 1462 { 0 } /* table terminator */ 1463 }; 1464 1465 STATIC 1466 _soc_katana_mmu_sub_block_type_1_info_t 1467 _soc_katana_mmu_sb_deq2_parity_info [] = { 1468 { 0x80000000, PORT_31_EFIFO_UNDERRUN_ERRORf, 1469 PORT_31_EFIFO_UNDERRUN_ERROR_DISINTf}, 1470 { 0x40000000, PORT_30_EFIFO_UNDERRUN_ERRORf, 1471 PORT_30_EFIFO_UNDERRUN_ERROR_DISINTf}, 1472 { 0x20000000, PORT_29_EFIFO_UNDERRUN_ERRORf, 1473 PORT_29_EFIFO_UNDERRUN_ERROR_DISINTf}, 1474 { 0x10000000, PORT_28_EFIFO_UNDERRUN_ERRORf, 1475 PORT_28_EFIFO_UNDERRUN_ERROR_DISINTf}, 1476 { 0x08000000, PORT_27_EFIFO_UNDERRUN_ERRORf, 1477 PORT_27_EFIFO_UNDERRUN_ERROR_DISINTf}, 1478 { 0x04000000, PORT_26_EFIFO_UNDERRUN_ERRORf, 1479 PORT_26_EFIFO_UNDERRUN_ERROR_DISINTf}, 1480 { 0x02000000, PORT_25_EFIFO_UNDERRUN_ERRORf, 1481 PORT_25_EFIFO_UNDERRUN_ERROR_DISINTf}, 1482 { 0x01000000, PORT_24_EFIFO_UNDERRUN_ERRORf, 1483 PORT_24_EFIFO_UNDERRUN_ERROR_DISINTf}, 1484 { 0x00800000, PORT_23_EFIFO_UNDERRUN_ERRORf, 1485 PORT_23_EFIFO_UNDERRUN_ERROR_DISINTf}, 1486 { 0x00400000, PORT_22_EFIFO_UNDERRUN_ERRORf, 1487 PORT_22_EFIFO_UNDERRUN_ERROR_DISINTf}, 1488 { 0x00200000, PORT_21_EFIFO_UNDERRUN_ERRORf, 1489 PORT_21_EFIFO_UNDERRUN_ERROR_DISINTf}, 1490 { 0x00100000, PORT_20_EFIFO_UNDERRUN_ERRORf, 1491 PORT_20_EFIFO_UNDERRUN_ERROR_DISINTf}, 1492 { 0x00080000, PORT_19_EFIFO_UNDERRUN_ERRORf, 1493 PORT_19_EFIFO_UNDERRUN_ERROR_DISINTf}, 1494 { 0x00040000, PORT_18_EFIFO_UNDERRUN_ERRORf, 1495 PORT_18_EFIFO_UNDERRUN_ERROR_DISINTf}, 1496 { 0x00020000, PORT_17_EFIFO_UNDERRUN_ERRORf, 1497 PORT_17_EFIFO_UNDERRUN_ERROR_DISINTf}, 1498 { 0x00010000, PORT_16_EFIFO_UNDERRUN_ERRORf, 1499 PORT_16_EFIFO_UNDERRUN_ERROR_DISINTf}, 1500 { 0x00008000, PORT_15_EFIFO_UNDERRUN_ERRORf, 1501 PORT_15_EFIFO_UNDERRUN_ERROR_DISINTf}, 1502 { 0x00004000, PORT_14_EFIFO_UNDERRUN_ERRORf, 1503 PORT_14_EFIFO_UNDERRUN_ERROR_DISINTf}, 1504 { 0x00002000, PORT_13_EFIFO_UNDERRUN_ERRORf, 1505 PORT_13_EFIFO_UNDERRUN_ERROR_DISINTf}, 1506 { 0x00001000, PORT_12_EFIFO_UNDERRUN_ERRORf, 1507 PORT_12_EFIFO_UNDERRUN_ERROR_DISINTf}, 1508 { 0x00000800, PORT_11_EFIFO_UNDERRUN_ERRORf, 1509 PORT_11_EFIFO_UNDERRUN_ERROR_DISINTf}, 1510 { 0x00000400, PORT_10_EFIFO_UNDERRUN_ERRORf, 1511 PORT_10_EFIFO_UNDERRUN_ERROR_DISINTf}, 1512 { 0x00000200, PORT_09_EFIFO_UNDERRUN_ERRORf, 1513 PORT_09_EFIFO_UNDERRUN_ERROR_DISINTf}, 1514 { 0x00000100, PORT_08_EFIFO_UNDERRUN_ERRORf, 1515 PORT_08_EFIFO_UNDERRUN_ERROR_DISINTf}, 1516 { 0x00000080, PORT_07_EFIFO_UNDERRUN_ERRORf, 1517 PORT_07_EFIFO_UNDERRUN_ERROR_DISINTf}, 1518 { 0x00000040, PORT_06_EFIFO_UNDERRUN_ERRORf, 1519 PORT_06_EFIFO_UNDERRUN_ERROR_DISINTf}, 1520 { 0x00000020, PORT_05_EFIFO_UNDERRUN_ERRORf, 1521 PORT_05_EFIFO_UNDERRUN_ERROR_DISINTf}, 1522 { 0x00000010, PORT_04_EFIFO_UNDERRUN_ERRORf, 1523 PORT_04_EFIFO_UNDERRUN_ERROR_DISINTf}, 1524 { 0x00000008, PORT_03_EFIFO_UNDERRUN_ERRORf, 1525 PORT_03_EFIFO_UNDERRUN_ERROR_DISINTf}, 1526 { 0x00000004, PORT_02_EFIFO_UNDERRUN_ERRORf, 1527 PORT_02_EFIFO_UNDERRUN_ERROR_DISINTf}, 1528 { 0x00000002, PORT_01_EFIFO_UNDERRUN_ERRORf, 1529 PORT_01_EFIFO_UNDERRUN_ERROR_DISINTf}, 1530 { 0x00000001, PORT_00_EFIFO_UNDERRUN_ERRORf, 1531 PORT_00_EFIFO_UNDERRUN_ERROR_DISINTf}, 1532 { 0 } /* table terminator */ 1533 }; 1534 1535 STATIC 1536 _soc_katana_mmu_sub_block_type_1_info_t 1537 _soc_katana_mmu_sb_deq3_parity_info [] = { 1538 { 0x00020000, DEQ_EGRESS_FIFO_ECC_VERIFICATION_400_UNCORRECTED_ERRORf, 1539 DEQ_EGRESS_FIFO_ECC_VERIFICATION_400_UNCORRECTED_ERROR_DISINTf}, 1540 { 0x00010000, DEQ_EGRESS_FIFO_ECC_VERIFICATION_400_CORRECTED_ERRORf, 1541 DEQ_EGRESS_FIFO_ECC_VERIFICATION_400_CORRECTED_ERROR_DISINTf}, 1542 { 0x00008000, DEQ_PRE_EGRESS_FIFO_ECC_VERIF_EXT_1520_UNCORRECTED_ERRORf, 1543 DEQ_PRE_EGRESS_FIFO_ECC_VERIF_EXT_1520_UNCORRECTED_ERROR_DISINTf}, 1544 { 0x00004000, DEQ_PRE_EGRESS_FIFO_ECC_VERIF_EXT_1520_CORRECTED_ERRORf, 1545 DEQ_PRE_EGRESS_FIFO_ECC_VERIF_EXT_1520_CORRECTED_ERROR_DISINTf}, 1546 { 0x00002000, DEQ_PRE_EGRESS_FIFO_ECC_VERIF_EXT_247_UNCORRECTED_ERRORf, 1547 DEQ_PRE_EGRESS_FIFO_ECC_VERIF_EXT_247_UNCORRECTED_ERROR_DISINTf}, 1548 { 0x00001000, DEQ_PRE_EGRESS_FIFO_ECC_VERIF_EXT_247_CORRECTED_ERRORf, 1549 DEQ_PRE_EGRESS_FIFO_ECC_VERIF_EXT_247_CORRECTED_ERROR_DISINTf}, 1550 { 0x00000800, DEQ_PRE_EGRESS_FIFO_ECC_VERIF_INT_1520_UNCORRECTED_ERRORf, 1551 DEQ_PRE_EGRESS_FIFO_ECC_VERIF_INT_1520_UNCORRECTED_ERROR_DISINTf}, 1552 { 0x00000400, DEQ_PRE_EGRESS_FIFO_ECC_VERIF_INT_1520_CORRECTED_ERRORf, 1553 DEQ_PRE_EGRESS_FIFO_ECC_VERIF_INT_1520_CORRECTED_ERROR_DISINTf}, 1554 { 0x00000200, DEQ_PRE_EGRESS_FIFO_ECC_VERIF_INT_247_UNCORRECTED_ERRORf, 1555 DEQ_PRE_EGRESS_FIFO_ECC_VERIF_INT_247_UNCORRECTED_ERROR_DISINTf}, 1556 { 0x00000100, DEQ_PRE_EGRESS_FIFO_ECC_VERIF_INT_247_CORRECTED_ERRORf, 1557 DEQ_PRE_EGRESS_FIFO_ECC_VERIF_INT_247_CORRECTED_ERROR_DISINTf}, 1558 { 0x00000080, DEQ_EGRESS_FIFO_CONTROL_DATA_MEMORY_UNCORRECTED_ERRORf, 1559 DEQ_EGRESS_FIFO_CONTROL_DATA_MEMORY_UNCORRECTED_ERROR_DISINTf}, 1560 { 0x00000040, DEQ_EGRESS_FIFO_CONTROL_DATA_MEMORY_CORRECTED_ERRORf, 1561 DEQ_EGRESS_FIFO_CONTROL_DATA_MEMORY_CORRECTED_ERROR_DISINTf}, 1562 { 0x00000020, DEQ_EGRESS_FIFO_AGING_WRED_MEMORY_UNCORRECTED_ERRORf, 1563 DEQ_EGRESS_FIFO_AGING_WRED_MEMORY_UNCORRECTED_ERROR_DISINTf}, 1564 { 0x00000010, DEQ_EGRESS_FIFO_AGING_WRED_MEMORY_CORRECTED_ERRORf, 1565 DEQ_EGRESS_FIFO_AGING_WRED_MEMORY_CORRECTED_ERROR_DISINTf}, 1566 { 0x00000008, DEQ_AGING_MASK_MEMORY_UNCORRECTED_ERRORf, 1567 DEQ_AGING_MASK_MEMORY_UNCORRECTED_ERROR_DISINTf}, 1568 { 0x00000004, DEQ_AGING_MASK_MEMORY_CORRECTED_ERRORf, 1569 DEQ_AGING_MASK_MEMORY_CORRECTED_ERROR_DISINTf}, 1570 { 0x00000002, DEQ_TOQ_CELL_REP_INFO_BUFFER_UNCORRECTED_ERRORf, 1571 DEQ_TOQ_CELL_REP_INFO_BUFFER_UNCORRECTED_ERROR_DISINTf}, 1572 { 0x00000001, DEQ_TOQ_CELL_REP_INFO_BUFFER_CORRECTED_ERRORf, 1573 DEQ_TOQ_CELL_REP_INFO_BUFFER_CORRECTED_ERROR_DISINTf}, 1574 { 0 } /* table terminator */ 1575 }; 1576 1577 STATIC _soc_katana_mmu_sub_block_type_3_info_t 1578 _soc_katana_mmu_sb_deq_parity_info [] = { 1579 { 0x0008, _SOC_KT_MMU_LVL2_SUBBLOCK_DEQ_ERROR_3, DEQ_ERRORr, 0, 1580 DEQ_ERROR_2f, 0, _soc_katana_mmu_sb_deq3_parity_info }, 1581 { 0x0004, _SOC_KT_MMU_LVL2_SUBBLOCK_DEQ_ERROR_2, DEQ_ERRORr, 0, 1582 DEQ_ERROR_2f, 0, _soc_katana_mmu_sb_deq2_parity_info }, 1583 { 0x0002, _SOC_KT_MMU_LVL2_SUBBLOCK_DEQ_ERROR_1, DEQ_ERRORr, 0, 1584 DEQ_ERROR_1f, 0, _soc_katana_mmu_sb_deq1_parity_info }, 1585 { 0x0001, _SOC_KT_MMU_LVL2_SUBBLOCK_DEQ_ERROR_0, DEQ_ERRORr, 0, 1586 DEQ_ERROR_0f, 0, _soc_katana_mmu_sb_deq0_parity_info }, 1587 { 0 } /* table terminator */ 1588 }; 1589 1590 STATIC _soc_katana_mmu_sub_block_type_1_info_t 1591 _soc_katana_mmu_sb_qstruct_fap_parity_info [] = { 1592 { 0x100000, FAP3_DUPLICATE_PTR_ERRORf, 1593 FAP3_DUPLICATE_PTR_ERROR_DISINTf}, 1594 { 0x80000, FAP2_DUPLICATE_PTR_ERRORf, 1595 FAP2_DUPLICATE_PTR_ERROR_DISINTf}, 1596 { 0x40000, FAP1_DUPLICATE_PTR_ERRORf, 1597 FAP1_DUPLICATE_PTR_ERROR_DISINTf}, 1598 { 0x20000, FAP0_DUPLICATE_PTR_ERRORf, 1599 FAP0_DUPLICATE_PTR_ERROR_DISINTf}, 1600 { 0x10000, FAP_LOADING_ERRORf, 1601 FAP_LOADING_ERROR_DISINTf}, 1602 { 0x8000, CORRECTED_BITMAP_ERROR_3f, 1603 CORRECTED_BITMAP_ERROR_3_DISINTf}, 1604 { 0x4000, UNCORRECTED_BITMAP_ERROR_3f, 1605 UNCORRECTED_BITMAP_ERROR_3_DISINTf}, 1606 { 0x2000, CORRECTED_STACK_ERROR_3f, 1607 CORRECTED_STACK_ERROR_3_DISINTf}, 1608 { 0x1000, UNCORRECTED_STACK_ERROR_3f, 1609 UNCORRECTED_STACK_ERROR_3_DISINTf}, 1610 { 0x0800, CORRECTED_BITMAP_ERROR_2f, 1611 CORRECTED_BITMAP_ERROR_2_DISINTf}, 1612 { 0x0400, UNCORRECTED_BITMAP_ERROR_2f, 1613 UNCORRECTED_BITMAP_ERROR_2_DISINTf}, 1614 { 0x0200, CORRECTED_STACK_ERROR_2f, 1615 CORRECTED_STACK_ERROR_2_DISINTf}, 1616 { 0x0100, UNCORRECTED_STACK_ERROR_2f, 1617 UNCORRECTED_STACK_ERROR_2_DISINTf}, 1618 { 0x0080, CORRECTED_BITMAP_ERROR_1f, 1619 CORRECTED_BITMAP_ERROR_1_DISINTf}, 1620 { 0x0040, UNCORRECTED_BITMAP_ERROR_1f, 1621 UNCORRECTED_BITMAP_ERROR_1_DISINTf}, 1622 { 0x0020, CORRECTED_STACK_ERROR_1f, 1623 CORRECTED_STACK_ERROR_1_DISINTf}, 1624 { 0x0010, UNCORRECTED_STACK_ERROR_1f, 1625 UNCORRECTED_STACK_ERROR_1_DISINTf}, 1626 { 0x0008, CORRECTED_BITMAP_ERROR_0f, 1627 CORRECTED_BITMAP_ERROR_0_DISINTf}, 1628 { 0x0004, UNCORRECTED_BITMAP_ERROR_0f, 1629 UNCORRECTED_BITMAP_ERROR_0_DISINTf}, 1630 { 0x0002, CORRECTED_STACK_ERROR_0f, 1631 CORRECTED_STACK_ERROR_0_DISINTf}, 1632 { 0x0001, UNCORRECTED_STACK_ERROR_0f, 1633 UNCORRECTED_STACK_ERROR_0_DISINTf}, 1634 { 0 } /* table terminator */ 1635 }; 1636 1637 STATIC _soc_katana_mmu_sub_block_type_1_info_t 1638 _soc_katana_mmu_sb_qstruct_qentry_upper_parity_info [] = { 1639 { 0x8000, CORRECTED_ERROR_7f, 1640 CORRECTED_ERROR_7_DISINTf}, 1641 { 0x4000, UNCORRECTED_ERROR_7f, 1642 UNCORRECTED_ERROR_7_DISINTf}, 1643 { 0x2000, CORRECTED_ERROR_6f, 1644 CORRECTED_ERROR_6_DISINTf}, 1645 { 0x1000, UNCORRECTED_ERROR_6f, 1646 UNCORRECTED_ERROR_6_DISINTf}, 1647 { 0x0800, CORRECTED_ERROR_5f, 1648 CORRECTED_ERROR_5_DISINTf}, 1649 { 0x0400, UNCORRECTED_ERROR_5f, 1650 UNCORRECTED_ERROR_5_DISINTf}, 1651 { 0x0200, CORRECTED_ERROR_4f, 1652 CORRECTED_ERROR_4_DISINTf}, 1653 { 0x0100, UNCORRECTED_ERROR_4f, 1654 UNCORRECTED_ERROR_4_DISINTf}, 1655 { 0x0080, CORRECTED_ERROR_3f, 1656 CORRECTED_ERROR_3_DISINTf}, 1657 { 0x0040, UNCORRECTED_ERROR_3f, 1658 UNCORRECTED_ERROR_3_DISINTf}, 1659 { 0x0020, CORRECTED_ERROR_2f, 1660 CORRECTED_ERROR_2_DISINTf}, 1661 { 0x0010, UNCORRECTED_ERROR_2f, 1662 UNCORRECTED_ERROR_2_DISINTf}, 1663 { 0x0008, CORRECTED_ERROR_1f, 1664 CORRECTED_ERROR_1_DISINTf}, 1665 { 0x0004, UNCORRECTED_ERROR_1f, 1666 UNCORRECTED_ERROR_1_DISINTf}, 1667 { 0x0002, CORRECTED_ERROR_0f, 1668 CORRECTED_ERROR_0_DISINTf}, 1669 { 0x0001, UNCORRECTED_ERROR_0f, 1670 UNCORRECTED_ERROR_0_DISINTf}, 1671 { 0 } /* table terminator */ 1672 }; 1673 1674 STATIC _soc_katana_mmu_sub_block_type_1_info_t 1675 _soc_katana_mmu_sb_qstruct_qentry_lower_parity_info [] = { 1676 { 0x8000, CORRECTED_ERROR_7f, 1677 CORRECTED_ERROR_7_DISINTf}, 1678 { 0x4000, UNCORRECTED_ERROR_7f, 1679 UNCORRECTED_ERROR_7_DISINTf}, 1680 { 0x2000, CORRECTED_ERROR_6f, 1681 CORRECTED_ERROR_6_DISINTf}, 1682 { 0x1000, UNCORRECTED_ERROR_6f, 1683 UNCORRECTED_ERROR_6_DISINTf}, 1684 { 0x0800, CORRECTED_ERROR_5f, 1685 CORRECTED_ERROR_5_DISINTf}, 1686 { 0x0400, UNCORRECTED_ERROR_5f, 1687 UNCORRECTED_ERROR_5_DISINTf}, 1688 { 0x0200, CORRECTED_ERROR_4f, 1689 CORRECTED_ERROR_4_DISINTf}, 1690 { 0x0100, UNCORRECTED_ERROR_4f, 1691 UNCORRECTED_ERROR_4_DISINTf}, 1692 { 0x0080, CORRECTED_ERROR_3f, 1693 CORRECTED_ERROR_3_DISINTf}, 1694 { 0x0040, UNCORRECTED_ERROR_3f, 1695 UNCORRECTED_ERROR_3_DISINTf}, 1696 { 0x0020, CORRECTED_ERROR_2f, 1697 CORRECTED_ERROR_2_DISINTf}, 1698 { 0x0010, UNCORRECTED_ERROR_2f, 1699 UNCORRECTED_ERROR_2_DISINTf}, 1700 { 0x0008, CORRECTED_ERROR_1f, 1701 CORRECTED_ERROR_1_DISINTf}, 1702 { 0x0004, UNCORRECTED_ERROR_1f, 1703 UNCORRECTED_ERROR_1_DISINTf}, 1704 { 0x0002, CORRECTED_ERROR_0f, 1705 CORRECTED_ERROR_0_DISINTf}, 1706 { 0x0001, UNCORRECTED_ERROR_0f, 1707 UNCORRECTED_ERROR_0_DISINTf}, 1708 { 0 } /* table terminator */ 1709 }; 1710 1711 STATIC _soc_katana_mmu_sub_block_type_1_info_t 1712 _soc_katana_mmu_sb_qstruct_qentry_qblock_nxt_parity_info [] = { 1713 { 0x8000, CORRECTED_ERROR_7f, 1714 CORRECTED_ERROR_7_DISINTf}, 1715 { 0x4000, UNCORRECTED_ERROR_7f, 1716 UNCORRECTED_ERROR_7_DISINTf}, 1717 { 0x2000, CORRECTED_ERROR_6f, 1718 CORRECTED_ERROR_6_DISINTf}, 1719 { 0x1000, UNCORRECTED_ERROR_6f, 1720 UNCORRECTED_ERROR_6_DISINTf}, 1721 { 0x0800, CORRECTED_ERROR_5f, 1722 CORRECTED_ERROR_5_DISINTf}, 1723 { 0x0400, UNCORRECTED_ERROR_5f, 1724 UNCORRECTED_ERROR_5_DISINTf}, 1725 { 0x0200, CORRECTED_ERROR_4f, 1726 CORRECTED_ERROR_4_DISINTf}, 1727 { 0x0100, UNCORRECTED_ERROR_4f, 1728 UNCORRECTED_ERROR_4_DISINTf}, 1729 { 0x0080, CORRECTED_ERROR_3f, 1730 CORRECTED_ERROR_3_DISINTf}, 1731 { 0x0040, UNCORRECTED_ERROR_3f, 1732 UNCORRECTED_ERROR_3_DISINTf}, 1733 { 0x0020, CORRECTED_ERROR_2f, 1734 CORRECTED_ERROR_2_DISINTf}, 1735 { 0x0010, UNCORRECTED_ERROR_2f, 1736 UNCORRECTED_ERROR_2_DISINTf}, 1737 { 0x0008, CORRECTED_ERROR_1f, 1738 CORRECTED_ERROR_1_DISINTf}, 1739 { 0x0004, UNCORRECTED_ERROR_1f, 1740 UNCORRECTED_ERROR_1_DISINTf}, 1741 { 0x0002, CORRECTED_ERROR_0f, 1742 CORRECTED_ERROR_0_DISINTf}, 1743 { 0x0001, UNCORRECTED_ERROR_0f, 1744 UNCORRECTED_ERROR_0_DISINTf}, 1745 { 0 } /* table terminator */ 1746 }; 1747 1748 STATIC _soc_katana_mmu_sub_block_type_3_info_t 1749 _soc_katana_mmu_sb_qstruct_parity_info [] = { 1750 { 0x0008, _SOC_KT_MMU_LVL2_SUBBLOCK_QSTRUCT_FAP, 1751 QSTRUCT_INTERRUPTr, QSTRUCT_INTERRUPT_MASKr, 1752 QENTRY_FAP_ERRORf, QENTRY_FAP_ERROR_DISINTf, 1753 _soc_katana_mmu_sb_qstruct_fap_parity_info }, 1754 { 0x0004, _SOC_KT_MMU_LVL2_SUBBLOCK_QSTRUCT_QENTRY_U, 1755 QSTRUCT_INTERRUPTr, QSTRUCT_INTERRUPT_MASKr, 1756 QENTRY_UPPER_ERRORf, QENTRY_UPPER_ERROR_DISINTf, 1757 _soc_katana_mmu_sb_qstruct_qentry_upper_parity_info }, 1758 { 0x0002, _SOC_KT_MMU_LVL2_SUBBLOCK_QSTRUCT_QENTRY_L, 1759 QSTRUCT_INTERRUPTr, QSTRUCT_INTERRUPT_MASKr, 1760 QENTRY_LOWER_ERRORf, QENTRY_LOWER_ERROR_DISINTf, 1761 _soc_katana_mmu_sb_qstruct_qentry_lower_parity_info }, 1762 { 0x0001, _SOC_KT_MMU_LVL2_SUBBLOCK_QSTRUCT_QBLOCK, 1763 QSTRUCT_INTERRUPTr, QSTRUCT_INTERRUPT_MASKr, 1764 QBLOCK_NEXT_ERRORf, QBLOCK_NEXT_ERROR_DISINTf, 1765 _soc_katana_mmu_sb_qstruct_qentry_qblock_nxt_parity_info }, 1766 { 0 } /* table terminator */ 1767 }; 1768 1769 STATIC 1770 _soc_katana_mmu_sub_block_type_1_info_t 1771 _soc_katana_mmu_sb_wred_parity_info [] = { 1772 { 0x4000000, UPDATE_INTRPT_STATUSf, 1773 UPDATE_INTRPT_MASKf }, 1774 { 0x3ffe000, ECC_ERROR_1Bf, 1775 ECC_1B_ERROR_MASKf }, 1776 { 0x1fff, ECC_ERROR_2Bf, 1777 ECC_2B_ERROR_MASKf }, 1778 { 0 } /* table terminator */ 1779 1780 }; 1781 1782 1783 STATIC _soc_katana_mmu_sub_block_type_1_info_t 1784 _soc_katana_mmu_sb_rqe_ser_parity_info [] = { 1785 { 0x4000000, NULL_REPL_PKTf, NULL_REPL_PKT_MASKf }, 1786 { 0x2000000, FLL_EMPTYf, FLL_EMPTY_MASKf }, 1787 { 0x1000000, THDIRQE_SRCPG_ILLEGALf , THDIRQE_SRCPG_ILLEGAL_MASKf }, 1788 { 0x0800000, THDIQEN_SRCPG_ILLEGALf, THDIQEN_SRCPG_ILLEGAL_MASKf }, 1789 { 0x0400000, EXTQ_LL_ERRORf, EXTQ_LL_ERROR_MASKf }, 1790 { 0x03ff100, ECC_1B_BITMAPf, ECC_1B_MASKf }, 1791 { 0x00007ff, ECC_2B_BITMAPf, ECC_2B_MASKf }, 1792 { 0 } /* table terminator */ 1793 }; 1794 1795 STATIC _soc_katana_mmu_sub_block_type_2_info_t 1796 _soc_katana_mmu_sb_rqe_extq_parity_info [] = { 1797 { 0x4000000, 0x8000, REPLICATION_SRCH_FAILf, REPLICATION_SRCH_FAIL_MASKf }, 1798 { 0x2000000, 0x4000, REPLICATION_OVER_LIMITf, REPLICATION_OVER_LIMIT_MASKf}, 1799 { 0x1ffe000, 0, REPLICATION_FAIL_MGIDf , 0 }, 1800 { 0x0001fff, 0, REPLICATION_COUNTf, 0 }, 1801 { 0 } /* table terminator */ 1802 }; 1803 1804 STATIC const 1805 _soc_katana_mmu_sub_block_type_1_t _soc_katana_mmu_sub_blocks_type_1[] = { 1806 { 0x00100000, _SOC_KT_MMU_SUBBLOCK_MEM1, 1807 MEM1_INTR_DISINTf, MEM1_INTRf, 1808 _soc_katana_mmu_sb_mem1_parity_info }, 1809 1810 { 0x00040000, _SOC_KT_MMU_SUBBLOCK_E2EFC, 1811 E2EFC_INTR_DISINTf, E2EFC_INTRf, 1812 _soc_katana_mmu_sb_e2efc_parity_info}, 1813 1814 { 0x00010000, _SOC_KT_MMU_SUBBLOCK_THDI, 1815 THDI_INTR_DISINTf, THDI_INTRf, 1816 _soc_katana_mmu_sb_thdi_parity_info}, 1817 1818 { 0x00000800, _SOC_KT_MMU_SUBBLOCK_WRED, 1819 WRED_INTR_DISINTf, WRED_INTRf, 1820 _soc_katana_mmu_sb_wred_parity_info}, 1821 1822 { 0x00000040, _SOC_KT_MMU_SUBBLOCK_CTR, 1823 CTR_INTR_DISINTf, CTR_INTRf, 1824 _soc_katana_mmu_sb_ctr_parity_info}, 1825 1826 { 0x00000010, _SOC_KT_MMU_SUBBLOCK_CCP, 1827 CCP_INTR_DISINTf, CCP_INTRf, 1828 _soc_katana_mmu_sb_ccp_parity_info}, 1829 1830 { 0x00000001, _SOC_KT_MMU_SUBBLOCK_TOQ, 1831 TOQ_INTR_DISINTf, TOQ_INTRf, 1832 _soc_katana_mmu_sb_toq_parity_info}, 1833 1834 /* interrupt is OR of 2 or more registers */ 1835 { 0x00020000, _SOC_KT_MMU_SUBBLOCK_ITE, 1836 ITE_INTR_DISINTf, ITE_INTRf, 1837 _soc_katana_mmu_sb_ite_parity_info}, 1838 1839 { 0x00020000, _SOC_KT_MMU_SUBBLOCK_ITE_CFG, 1840 ITE_INTR_DISINTf, ITE_INTRf, 1841 _soc_katana_mmu_sb_ite_cfg_parity_info}, 1842 1843 { 0x00008000, _SOC_KT_MMU_SUBBLOCK_ENQ_CFG, 1844 ENQ_INTR_DISINTf, ENQ_INTRf, 1845 _soc_katana_mmu_sb_enq_cfg_parity_info}, 1846 1847 { 0x00008000, _SOC_KT_MMU_SUBBLOCK_ENQ, 1848 ENQ_INTR_DISINTf, ENQ_INTRf, 1849 _soc_katana_mmu_sb_enq_parity_info}, 1850 1851 { 0x00008000, _SOC_KT_MMU_SUBBLOCK_ENQ_FAP, 1852 ENQ_INTR_DISINTf, ENQ_INTRf, 1853 _soc_katana_mmu_sb_enq_fap_parity_info}, 1854 1855 { 0x00000400, _SOC_KT_MMU_SUBBLOCK_THDO_STATUS1, 1856 THDO_INTR_DISINTf, THDO_INTRf, 1857 _soc_katana_mmu_sb_thdo_stat1_parity_info}, 1858 1859 { 0x00000400, _SOC_KT_MMU_SUBBLOCK_THDO_STATUS2, 1860 THDO_INTR_DISINTf, THDO_INTRf, 1861 _soc_katana_mmu_sb_thdo_stat2_parity_info}, 1862 1863 { 0x00000020, _SOC_KT_MMU_SUBBLOCK_CFAPI, 1864 CFAP_INTR_DISINTf, CFAP_INTRf, 1865 _soc_katana_mmu_sb_cfapi_parity_info}, 1866 1867 { 0x00000020, _SOC_KT_MMU_SUBBLOCK_CFAPE, 1868 CFAP_INTR_DISINTf, CFAP_INTRf, 1869 _soc_katana_mmu_sb_cfape_parity_info}, 1870 1871 { 0x00000008, _SOC_KT_MMU_SUBBLOCK_AGING_INT, 1872 AGING_INTR_DISINTf, AGING_INTRf, 1873 _soc_katana_mmu_sb_age_int_parity_info}, 1874 1875 { 0x00000008, _SOC_KT_MMU_SUBBLOCK_AGING_EXT, 1876 AGING_INTR_DISINTf, AGING_INTRf, 1877 _soc_katana_mmu_sb_age_ext_parity_info}, 1878 1879 { 0x00004000, _SOC_KT_MMU_SUBBLOCK_CI2, 1880 CI2_INTR_DISINTf, CI2_INTRf, 1881 _soc_katana_mmu_sb_ci2_parity_info}, 1882 1883 { 0x00002000, _SOC_KT_MMU_SUBBLOCK_CI1, 1884 CI1_INTR_DISINTf, CI1_INTRf, 1885 _soc_katana_mmu_sb_ci1_parity_info}, 1886 1887 { 0x00001000, _SOC_KT_MMU_SUBBLOCK_CI0, 1888 CI0_INTR_DISINTf, CI0_INTRf, 1889 _soc_katana_mmu_sb_ci0_parity_info}, 1890 1891 { 0x00000004, _SOC_KT_MMU_SUBBLOCK_LLS, 1892 LLS_INTR_DISINTf, LLS_INTRf, 1893 _soc_katana_mmu_sb_lls_parity_info}, 1894 1895 { 0x00000004, _SOC_KT_MMU_SUBBLOCK_LLS_PORT, 1896 LLS_INTR_DISINTf, LLS_INTRf, 1897 _soc_katana_mmu_sb_lls_port_parity_info}, 1898 1899 { 0x00000004, _SOC_KT_MMU_SUBBLOCK_LLS_UPD2, 1900 LLS_INTR_DISINTf, LLS_INTRf, 1901 _soc_katana_mmu_sb_lls_upd2_parity_info}, 1902 1903 { 0x00000004, _SOC_KT_MMU_SUBBLOCK_LLS_L0_ECC, 1904 LLS_INTR_DISINTf, LLS_INTRf, 1905 _soc_katana_mmu_sb_lls_l0_ecc_parity_info}, 1906 1907 { 0x00000004, _SOC_KT_MMU_SUBBLOCK_LLS_L1_ECC, 1908 LLS_INTR_DISINTf, LLS_INTRf, 1909 _soc_katana_mmu_sb_lls_l1_ecc_parity_info}, 1910 1911 { 0x00000004, _SOC_KT_MMU_SUBBLOCK_LLS_L2_ECC, 1912 LLS_INTR_DISINTf, LLS_INTRf, 1913 _soc_katana_mmu_sb_lls_l2_ecc_parity_info}, 1914 1915 { 0x00000004, _SOC_KT_MMU_SUBBLOCK_LLS_MISC_ECC, 1916 LLS_INTR_DISINTf, LLS_INTRf, 1917 _soc_katana_mmu_sb_lls_misc_ecc_parity_info}, 1918 1919 { 0x00000200, _SOC_KT_MMU_SUBBLOCK_RQE_SER, 1920 RQE_INTR_DISINTf, RQE_INTRf, 1921 _soc_katana_mmu_sb_rqe_ser_parity_info}, 1922 1923 { 0x00080000, _SOC_KT_MMU_SUBBLOCK_INTFI, 1924 INTF1_INTR_DISINTf, INTFI_INTRf, 1925 _soc_katana_mmu_sb_intfi_parity_info}, 1926 { 0 } /* table terminator */ 1927 }; 1928 1929 STATIC const 1930 _soc_katana_mmu_sub_block_type_2_t _soc_katana_mmu_sub_blocks_type_2[] = { 1931 { 0x00080000, _SOC_KT_MMU_SUBBLOCK_INTFI_ECC, 1932 INTF1_INTR_DISINTf, INTFI_INTRf, 1933 _soc_katana_mmu_sb_intfi_ecc_parity_info}, 1934 { 0x00000200, _SOC_KT_MMU_SUBBLOCK_RQE_EXTQ, 1935 RQE_INTR_DISINTf, RQE_INTRf, 1936 _soc_katana_mmu_sb_rqe_extq_parity_info}, 1937 { 0 } /* table terminator */ 1938 }; 1939 1940 STATIC const 1941 _soc_katana_mmu_sub_block_type_3_t _soc_katana_mmu_sub_blocks_type_3[] = { 1942 { 0x00000100, _SOC_KT_MMU_SUBBLOCK_EMC, 1943 EMC_INTR_DISINTf, EMC_INTRf, 1944 _soc_katana_mmu_sb_emc_parity_info}, 1945 1946 { 0x00000080, _SOC_KT_MMU_SUBBLOCK_DEQ, 1947 DEQ_INTR_DISINTf, DEQ_INTRf, 1948 _soc_katana_mmu_sb_deq_parity_info}, 1949 1950 { 0x00000002, _SOC_KT_MMU_SUBBLOCK_QSTRUCT, 1951 QSTRUCT_INTR_DISINTf, QSTRUCT_INTRf, 1952 _soc_katana_mmu_sb_qstruct_parity_info}, 1953 { 0 } /* table terminator */ 1954 }; 1955 1956 STATIC _soc_katana_parity_info_t _soc_katana_ep0_parity_info[] = { 1957 /* EGR_EL3_ECC_PARITY_CONTROLr */ 1958 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 1959 EGR_NHOP_PAR_ERRf, 1960 EGR_NHOP_PAR_ERRf, 1961 EGR_L3_NEXT_HOPm, NULL, 1962 EGR_EL3_ECC_PARITY_CONTROLr, EGR_L3_NEXT_HOP_PARITY_ENf, 1963 EGR_L3_NEXT_HOP_PARITY_STATUS_INTRr, NULL, 1964 EGR_L3_NEXT_HOP_PARITY_STATUS_NACKr, NULL }, 1965 /* EGR_EL3_ECC_PARITY_CONTROLr */ 1966 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 1967 EGR_L3_INTF_PAR_ERRf, 1968 EGR_L3_INTF_PAR_ERRf, 1969 EGR_L3_INTFm, NULL, 1970 EGR_EL3_ECC_PARITY_CONTROLr, EGR_L3_INTF_PARITY_ENf, 1971 EGR_L3_INTF_PARITY_STATUS_INTRr, NULL, 1972 EGR_L3_INTF_PARITY_STATUS_NACKr, NULL }, 1973 /* EGR_EL3_ECC_PARITY_CONTROLr */ 1974 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 1975 EGR_MPLS_VC_AND_SWAP_LABEL_TABLE_PAR_ERRf, 1976 EGR_MPLS_VC_AND_SWAP_LABEL_TABLE_PAR_ERRf, 1977 EGR_MPLS_VC_AND_SWAP_LABEL_TABLEm, NULL, 1978 EGR_EL3_ECC_PARITY_CONTROLr, EGR_MPLS_VC_AND_SWAP_LABEL_TABLE_PARITY_ENf, 1979 EGR_MPLS_VC_AND_SWAP_LABEL_TABLE_PARITY_STATUS_INTRr, NULL, 1980 EGR_MPLS_VC_AND_SWAP_LABEL_TABLE_PARITY_STATUS_NACKr, NULL }, 1981 /* EGR_EL3_ECC_PARITY_CONTROLr */ 1982 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 1983 EGR_MAC_DA_PROFILE_PAR_ERRf, 1984 EGR_MAC_DA_PROFILE_PAR_ERRf, 1985 EGR_MAC_DA_PROFILEm, NULL, 1986 EGR_EL3_ECC_PARITY_CONTROLr, EGR_MAC_DA_PROFILE_PARITY_ENf, 1987 EGR_MAC_DA_PROFILE_PARITY_STATUS_INTRr, NULL, 1988 EGR_MAC_DA_PROFILE_PARITY_STATUS_NACKr, NULL }, 1989 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 1990 EGR_DVP_ATTRIBUTE_PAR_ERRf, 1991 EGR_DVP_ATTRIBUTE_PAR_ERRf, 1992 EGR_DVP_ATTRIBUTEm, NULL, 1993 EGR_EL3_ECC_PARITY_CONTROLr, EGR_DVP_ATTRIBUTE_PARITY_ENf, 1994 EGR_DVP_ATTRIBUTE_PARITY_STATUS_INTRr, NULL, 1995 EGR_DVP_ATTRIBUTE_PARITY_STATUS_NACKr, NULL }, 1996 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 1997 EGR_VFI_PAR_ERRf, 1998 EGR_VFI_PAR_ERRf, 1999 EGR_VFIm, NULL, 2000 EGR_EL3_ECC_PARITY_CONTROLr, EGR_VFI_PARITY_ENf, 2001 EGR_VFI_PARITY_STATUS_INTRr, NULL, 2002 EGR_VFI_PARITY_STATUS_NACKr, NULL }, 2003 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2004 EGR_IPMC_PAR_ERRf, 2005 EGR_IPMC_PAR_ERRf, 2006 EGR_IPMCm, NULL, 2007 EGR_EL3_ECC_PARITY_CONTROLr, EGR_IPMC_PARITY_ENf, 2008 EGR_IPMC_PARITY_STATUS_INTRr, NULL, 2009 EGR_IPMC_PARITY_STATUS_NACKr, NULL }, 2010 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2011 EGR_PORT_PAR_ERRf, 2012 EGR_PORT_PAR_ERRf, 2013 EGR_PORTm, NULL, 2014 EGR_EL3_ECC_PARITY_CONTROLr, EGR_PORT_PARITY_ENf, 2015 EGR_PORT_PARITY_STATUS_INTRr, NULL, 2016 EGR_PORT_PARITY_STATUS_NACKr, NULL }, 2017 { _SOC_PARITY_TYPE_ECC, NULL, 0, 2018 EGR_MPB_ECC_ERRf, 2019 EGR_MPB_ECC_ERRf, 2020 INVALIDm, "EGR_MPB", 2021 EGR_EL3_ECC_PARITY_CONTROLr, EGR_MPB_ECC_ENf, 2022 EGR_MPB_ECC_STATUS_INTRr, NULL, 2023 INVALIDr, NULL }, 2024 /* EGR_VLAN_PARITY_CONTROLr */ 2025 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2026 EGR_VLAN_PAR_ERRf, 2027 EGR_VLAN_PAR_ERRf, 2028 EGR_VLANm, NULL, 2029 EGR_VLAN_PARITY_CONTROLr, EGR_VLAN_PARITY_ENf, 2030 EGR_VLAN_PARITY_STATUS_INTRr, NULL, 2031 EGR_VLAN_PARITY_STATUS_NACKr, NULL }, 2032 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2033 EGR_VLAN_STG_PAR_ERRf, 2034 EGR_VLAN_STG_PAR_ERRf, 2035 EGR_VLAN_STGm, NULL, 2036 EGR_VLAN_PARITY_CONTROLr, EGR_VLAN_STG_PARITY_ENf, 2037 EGR_VLAN_STG_PARITY_STATUS_INTRr, NULL, 2038 EGR_VLAN_STG_PARITY_STATUS_NACKr, NULL }, 2039 { _SOC_PARITY_TYPE_HASH, NULL, 0, 2040 EGR_VLAN_XLATE_PAR_ERRf, 2041 EGR_VLAN_XLATE_PAR_ERRf, 2042 EGR_VLAN_XLATEm, NULL, 2043 EGR_VLAN_PARITY_CONTROLr, EGR_VLAN_XLATE_PARITY_ENf, 2044 INVALIDr, _soc_katana_egr_vlan_xlate_intr_reg, 2045 INVALIDr, _soc_katana_egr_vlan_xlate_nack_reg }, 2046 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2047 EGR_IP_TUNNEL_PAR_ERRf, 2048 EGR_IP_TUNNEL_PAR_ERRf, 2049 EGR_IP_TUNNELm, NULL, 2050 EGR_VLAN_PARITY_CONTROLr, EGR_IP_TUNNEL_PARITY_ENf, 2051 EGR_IP_TUNNEL_PARITY_STATUS_INTRr, NULL, 2052 EGR_IP_TUNNEL_PARITY_STATUS_NACKr, NULL }, 2053 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2054 EGR_MPLS_EXP_MAPPING_2_PAR_ERRf, 2055 EGR_MPLS_EXP_MAPPING_2_PAR_ERRf, 2056 EGR_MPLS_EXP_MAPPING_2m, NULL, 2057 EGR_VLAN_PARITY_CONTROLr, EGR_MPLS_EXP_MAPPING_2_PARITY_ENf, 2058 EGR_MPLS_EXP_MAPPING_2_PARITY_STATUS_INTRr, NULL, 2059 EGR_MPLS_EXP_MAPPING_2_PARITY_STATUS_NACKr, NULL }, 2060 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2061 EGR_MPLS_PRI_MAPPING_PAR_ERRf, 2062 EGR_MPLS_PRI_MAPPING_PAR_ERRf, 2063 EGR_MPLS_PRI_MAPPINGm, NULL, 2064 EGR_VLAN_PARITY_CONTROLr, EGR_MPLS_PRI_MAPPING_PARITY_ENf, 2065 EGR_MPLS_PRI_MAPPING_PARITY_STATUS_INTRr, NULL, 2066 EGR_MPLS_PRI_MAPPING_PARITY_STATUS_NACKr, NULL }, 2067 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2068 EGR_PRI_CNG_MAP_PAR_ERRf, 2069 EGR_PRI_CNG_MAP_PAR_ERRf, 2070 EGR_PRI_CNG_MAPm, NULL, 2071 EGR_VLAN_PARITY_CONTROLr, EGR_PRI_CNG_MAP_PARITY_ENf, 2072 EGR_PRI_CNG_MAP_PARITY_STATUS_INTRr, NULL, 2073 EGR_PRI_CNG_MAP_PARITY_STATUS_NACKr, NULL }, 2074 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2075 EGR_DSCP_TABLE_PAR_ERRf, 2076 EGR_DSCP_TABLE_PAR_ERRf, 2077 EGR_DSCP_TABLEm, NULL, 2078 EGR_VLAN_PARITY_CONTROLr, EGR_DSCP_TABLE_PARITY_ENf, 2079 EGR_DSCP_TABLE_PARITY_STATUS_INTRr, NULL, 2080 EGR_DSCP_TABLE_PARITY_STATUS_NACKr, NULL }, 2081 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2082 EGR_FRAGMENT_ID_TABLE_PAR_ERRf, 2083 EGR_FRAGMENT_ID_TABLE_PAR_ERRf, 2084 EGR_FRAGMENT_ID_TABLEm, NULL, 2085 EGR_VLAN_PARITY_CONTROLr, EGR_FRAGMENT_ID_TABLE_PARITY_ENf, 2086 EGR_FRAGMENT_ID_TABLE_PARITY_STATUS_INTRr, NULL, 2087 EGR_FRAGMENT_ID_TABLE_PARITY_STATUS_NACKr, NULL }, 2088 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2089 EGR_MPLS_EXP_MAPPING_1_PAR_ERRf, 2090 EGR_MPLS_EXP_MAPPING_1_PAR_ERRf, 2091 EGR_MPLS_EXP_MAPPING_1m, NULL, 2092 EGR_VLAN_PARITY_CONTROLr, EGR_MPLS_EXP_MAPPING_1_PARITY_ENf, 2093 EGR_MPLS_EXP_MAPPING_1_PARITY_STATUS_INTRr, NULL, 2094 EGR_MPLS_EXP_MAPPING_1_PARITY_STATUS_NACKr, NULL }, 2095 /* EGR_EHCPM_ECC_PARITY_CONTROLr */ 2096 { _SOC_PARITY_TYPE_ECC, NULL, 0, 2097 EGR_INITBUF_ECC_ERRf, 2098 EGR_INITBUF_ECC_ERRf, 2099 INVALIDm, "EGR_INITBUF", 2100 EGR_EHCPM_ECC_PARITY_CONTROLr, INITBUF_ECC_ENf, 2101 EGR_INITBUF_ECC_STATUS_INTRr, NULL, 2102 INVALIDr, NULL }, 2103 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2104 EGR_MOD_MAP_TABLE_PAR_ERRf, 2105 EGR_MOD_MAP_TABLE_PAR_ERRf, 2106 EGR_MOD_MAP_TABLEm, NULL, 2107 EGR_EHCPM_ECC_PARITY_CONTROLr, MOD_MAP_PARITY_ENf, 2108 EGR_MOD_MAP_PARITY_STATUS_INTRr, NULL, 2109 EGR_MOD_MAP_PARITY_STATUS_NACKr, NULL }, 2110 { _SOC_PARITY_TYPE_NONE } /* table terminator */ 2111 }; 2112 2113 STATIC _soc_katana_parity_info_t _soc_katana_ep1_parity_info[] = { 2114 /* EGR_EDATABUF_PARITY_CONTROLr */ 2115 { _SOC_PARITY_TYPE_EDATABUF, NULL, 0, 2116 CM_ECC_ERRf, 2117 CM_ECC_ERRf, 2118 INVALIDm, "EP_EDATABUF_CM_MEM", 2119 EGR_EDATABUF_PARITY_CONTROLr, CM_ECC_ENf, 2120 EGR_CM_BUFFER_STATUS_INTRr, NULL, 2121 INVALIDr, NULL }, 2122 { _SOC_PARITY_TYPE_EDATABUF, NULL, 0, 2123 GP0_ECC_ERRf, 2124 GP0_ECC_ERRf, 2125 INVALIDm, "EP_EDATABUF_GP0_MEM", 2126 EGR_EDATABUF_PARITY_CONTROLr, GP0_ECC_ENf, 2127 EGR_GP0_BUFFER_STATUS_INTRr, NULL, 2128 INVALIDr, NULL }, 2129 { _SOC_PARITY_TYPE_EDATABUF, NULL, 0, 2130 GP1_ECC_ERRf, 2131 GP1_ECC_ERRf, 2132 INVALIDm, "EP_EDATABUF_GP1_MEM", 2133 EGR_EDATABUF_PARITY_CONTROLr, GP1_ECC_ENf, 2134 EGR_GP1_BUFFER_STATUS_INTRr, NULL, 2135 INVALIDr, NULL }, 2136 { _SOC_PARITY_TYPE_EDATABUF, NULL, 0, 2137 GP2_ECC_ERRf, 2138 GP2_ECC_ERRf, 2139 INVALIDm, "EP_EDATABUF_GP2_MEM", 2140 EGR_EDATABUF_PARITY_CONTROLr, GP2_ECC_ENf, 2141 EGR_GP2_BUFFER_STATUS_INTRr, NULL, 2142 INVALIDr, NULL }, 2143 { _SOC_PARITY_TYPE_EDATABUF, NULL, 0, 2144 XQ0_ECC_ERRf, 2145 XQ0_ECC_ERRf, 2146 INVALIDm, "EP_EDATABUF_XQ0_MEM", 2147 EGR_EDATABUF_PARITY_CONTROLr, XQ0_ECC_ENf, 2148 EGR_XQ0_BUFFER_STATUS_INTRr, NULL, 2149 INVALIDr, NULL }, 2150 { _SOC_PARITY_TYPE_EDATABUF, NULL, 0, 2151 XQ1_ECC_ERRf, 2152 XQ1_ECC_ERRf, 2153 INVALIDm, "EP_EDATABUF_XQ1_MEM", 2154 EGR_EDATABUF_PARITY_CONTROLr, XQ1_ECC_ENf, 2155 EGR_XQ1_BUFFER_STATUS_INTRr, NULL, 2156 INVALIDr, NULL }, 2157 { _SOC_PARITY_TYPE_EDATABUF, NULL, 0, 2158 XQ2_ECC_ERRf, 2159 XQ2_ECC_ERRf, 2160 INVALIDm, "EP_EDATABUF_XQ2_MEM", 2161 EGR_EDATABUF_PARITY_CONTROLr, XQ2_ECC_ENf, 2162 EGR_XQ2_BUFFER_STATUS_INTRr, NULL, 2163 INVALIDr, NULL }, 2164 { _SOC_PARITY_TYPE_EDATABUF, NULL, 0, 2165 XQ3_ECC_ERRf, 2166 XQ3_ECC_ERRf, 2167 INVALIDm, "EP_EDATABUF_XQ3_MEM", 2168 EGR_EDATABUF_PARITY_CONTROLr, XQ3_ECC_ENf, 2169 EGR_XQ3_BUFFER_STATUS_INTRr, NULL, 2170 INVALIDr, NULL }, 2171 #ifdef _KATANA_DEBUG 2172 { _SOC_PARITY_TYPE_EDATABUF, NULL, 0, 2173 RESI_ECC_ERRf, 2174 RESI_ECC_ERRf, 2175 INVALIDm, "EP_EDATABUF_RESI_MEM", 2176 EGR_EDATABUF_PARITY_CONTROLr, RESI_ECC_ENf, 2177 EGR_RESI_BUFFER_STATUS_INTRr, NULL, 2178 INVALIDr, NULL }, 2179 #endif 2180 { _SOC_PARITY_TYPE_EDATABUF, NULL, 0, 2181 LP_ECC_ERRf, 2182 LP_ECC_ERRf, 2183 INVALIDm, "EP_EDATABUF_LP_MEM", 2184 EGR_EDATABUF_PARITY_CONTROLr, LP_ECC_ENf, 2185 EGR_LP_BUFFER_STATUS_INTRr, NULL, 2186 INVALIDr, NULL }, 2187 { _SOC_PARITY_TYPE_COUNTER, NULL, 0, 2188 EGR_STATS_COUNTER_TABLE_PAR_ERRf, 2189 EGR_STATS_COUNTER_TABLE_PAR_ERRf, 2190 INVALIDm, "TX Debug Counter", 2191 EGR_EDATABUF_PARITY_CONTROLr, STATS_PAR_ENf, 2192 EGR_STATS_COUNTER_TABLE_PARITY_STATUS_INTRr, NULL, 2193 EGR_STATS_COUNTER_TABLE_PARITY_STATUS_NACKr, NULL }, 2194 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2195 EGR_EFP_COUNTER_TABLE_PAR_ERRf, 2196 EGR_EFP_COUNTER_TABLE_PAR_ERRf, 2197 EFP_COUNTER_TABLEm, NULL, 2198 EGR_EDATABUF_PARITY_CONTROLr, EFPCTR_PAR_ENf, 2199 EGR_EFP_COUNTER_TABLE_PARITY_STATUS_INTRr, NULL, 2200 EGR_EFP_COUNTER_TABLE_PARITY_STATUS_NACKr, NULL }, 2201 /* EFP_METER_PARITY_CONTROLr */ 2202 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2203 EGR_EFP_METER_TABLE_PAR_ERRf, 2204 EGR_EFP_METER_TABLE_PAR_ERRf, 2205 EFP_METER_TABLEm, NULL, 2206 EFP_METER_PARITY_CONTROLr, PARITY_ENf, 2207 EFP_METER_PARITY_STATUS_INTRr, NULL, 2208 EFP_METER_PARITY_STATUS_NACKr, NULL }, 2209 /* EFP_POLICY_PARITY_CONTROLr */ 2210 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2211 EGR_EFP_POLICY_TABLE_PAR_ERRf, 2212 EGR_EFP_POLICY_TABLE_PAR_ERRf, 2213 EFP_POLICY_TABLEm, NULL, 2214 EFP_POLICY_PARITY_CONTROLr, PARITY_ENf, 2215 EFP_POLICY_PARITY_STATUS_INTRr, NULL, 2216 EFP_POLICY_PARITY_STATUS_NACKr, NULL }, 2217 /* EGR_PW_INIT_COUNTERS_PARITY_CONTROLr */ 2218 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2219 EGR_EFP_PW_INIT_COUNTERS_PAR_ERRf, 2220 EGR_EFP_PW_INIT_COUNTERS_PAR_ERRf, 2221 EGR_PW_INIT_COUNTERSm, NULL, 2222 EGR_PW_INIT_COUNTERS_PARITY_CONTROLr, PARITY_ENf, 2223 EGR_PW_INIT_COUNTERS_PARITY_STATUS_INTRr, NULL, 2224 EGR_PW_INIT_COUNTERS_PARITY_STATUS_NACKr, NULL }, 2225 { _SOC_PARITY_TYPE_NONE } /* table terminator */ 2226 }; 2227 2228 STATIC _soc_katana_parity_info_t _soc_katana_ip0_parity_info[] = { 2229 /* Block-IPIPE, Stage-IARB */ 2230 /* LMEP_PARITY_CONTROLr */ 2231 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2232 LMEP_PAR_ERRf, 2233 LMEP_PAR_ERRf, 2234 LMEPm, NULL, 2235 LMEP_PARITY_CONTROLr, PARITY_ENf, 2236 LMEP_PARITY_STATUS_INTRr, NULL, 2237 LMEP_PARITY_STATUS_NACKr, NULL }, 2238 /* LMEP_1_PARITY_CONTROLr */ 2239 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2240 IARB_LMEP1_PAR_ERRf, 2241 IARB_LMEP1_PAR_ERRf, 2242 LMEP_1m, NULL, 2243 LMEP_1_PARITY_CONTROLr, PARITY_ENf, 2244 LMEP_1_PARITY_STATUS_INTRr, NULL, 2245 LMEP_1_PARITY_STATUS_NACKr, NULL }, 2246 /* IARB_PKT_ECC_CONTROLr */ 2247 { _SOC_PARITY_TYPE_ECC, NULL, 0, 2248 IARB_PKT_ERRf, 2249 IARB_PKT_ERRf, 2250 INVALIDm, "IARB_PKT_BUF", 2251 IARB_PKT_ECC_CONTROLr, ECC_ENf, 2252 IARB_PKT_ECC_STATUS_INTRr, NULL, 2253 INVALIDr, NULL }, 2254 /* IARB_HDR_ECC_CONTROLr */ 2255 { _SOC_PARITY_TYPE_ECC, NULL, 0, 2256 IARB_HDR_ERRf, 2257 IARB_HDR_ERRf, 2258 INVALIDm, "IARB_PKT_HDR", 2259 IARB_HDR_ECC_CONTROLr, ECC_ENf, 2260 IARB_HDR_ECC_STATUS_INTRr, NULL, 2261 INVALIDr, NULL }, 2262 { _SOC_PARITY_TYPE_ECC, NULL, 0, 2263 IARB_PIPE_X_LEARN_FIFO_ECC_ERRf, 2264 IARB_PIPE_X_LEARN_FIFO_ECC_ERRf, 2265 INVALIDm, "IARB_LEARN_FIFO_PIPE_X", 2266 IARB_LEARN_FIFO_ECC_CONTROLr, ECC_ENf, 2267 IARB_PIPE_X_LERAN_FIFO_ECC_STATUS_INTRr, NULL, 2268 INVALIDr, NULL }, 2269 2270 /* Block-IPIPE; Stage-IVXLT */ 2271 2272 /* VLAN_XLATE_PARITY_CONTROLr */ 2273 { _SOC_PARITY_TYPE_HASH, NULL, 0, 2274 VXLT_PAR_ERRf, 2275 VXLT_PAR_ERRf, 2276 VLAN_XLATEm, NULL, 2277 VLAN_XLATE_PARITY_CONTROLr, PARITY_ENf, 2278 INVALIDr, _soc_katana_vlan_xlate_intr_reg, 2279 INVALIDr, _soc_katana_vlan_xlate_nack_reg }, 2280 /* VFP_POLICY_PARITY_CONTROLr */ 2281 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2282 VFP_POLICY_PAR_ERRf, 2283 VFP_POLICY_PAR_ERRf, 2284 VFP_POLICY_TABLEm, NULL, 2285 VFP_POLICY_PARITY_CONTROLr, PARITY_ENf, 2286 VFP_POLICY_PARITY_STATUS_INTRr, NULL, 2287 VFP_POLICY_PARITY_STATUS_NACKr, NULL }, 2288 /* VLAN_PROT_PARITY_CONTROLr */ 2289 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2290 VLAN_PROT_PAR_ERRf, 2291 VLAN_PROT_PAR_ERRf, 2292 VLAN_PROTOCOL_DATAm, NULL, 2293 VLAN_PROT_PARITY_CONTROLr, PARITY_ENf, 2294 VLAN_PROT_PARITY_STATUS_INTRr, NULL, 2295 VLAN_PROT_PARITY_STATUS_NACKr, NULL }, 2296 /* VLAN_SUBNET_PARITY_CONTROLr */ 2297 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2298 VLAN_SUBNET_PAR_ERRf, 2299 VLAN_SUBNET_PAR_ERRf, 2300 VLAN_SUBNETm, NULL, 2301 VLAN_SUBNET_PARITY_CONTROLr, PARITY_ENf, 2302 VLAN_SUBNET_PARITY_STATUS_INTRr, NULL, 2303 VLAN_SUBNET_PARITY_STATUS_NACKr, NULL }, 2304 /* MPLS_ENTRY_PARITY_CONTROLr */ 2305 { _SOC_PARITY_TYPE_HASH, NULL, 0, 2306 MPLS_ENTRY_PAR_ERRf, 2307 MPLS_ENTRY_PAR_ERRf, 2308 MPLS_ENTRYm, NULL, 2309 MPLS_ENTRY_PARITY_CONTROLr, PARITY_ENf, 2310 INVALIDr, _soc_katana_mpls_entry_intr_reg, 2311 INVALIDr, _soc_katana_mpls_entry_nack_reg }, 2312 2313 /* Block-IPIPE; Stage-IPARS */ 2314 2315 /* CPU_TS_PARITY_CONTROLr */ 2316 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2317 CPU_TS_POLICY_PAR_ERRf, 2318 CPU_TS_POLICY_PAR_ERRf, 2319 CPU_TS_MAPm, NULL, 2320 CPU_TS_PARITY_CONTROLr, PARITY_ENf, 2321 CPU_TS_PARITY_STATUS_INTRr, NULL, 2322 CPU_TS_PARITY_STATUS_NACKr, NULL }, 2323 /* VLAN_RANGE_PARITY_CONTROLr */ 2324 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2325 VLAN_RANGE_PAR_ERRf, 2326 VLAN_RANGE_PAR_ERRf, 2327 ING_VLAN_RANGEm, NULL, 2328 VLAN_RANGE_PARITY_CONTROLr, PARITY_ENf, 2329 VLAN_RANGE_PARITY_STATUS_INTRr, NULL, 2330 VLAN_RANGE_PARITY_STATUS_NACKr, NULL }, 2331 /* MOD_MAP_PARITY_CONTROLr */ 2332 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2333 MOD_MAP_PAR_ERRf, 2334 MOD_MAP_PAR_ERRf, 2335 ING_MOD_MAP_TABLEm, NULL, 2336 MOD_MAP_PARITY_CONTROLr, PARITY_ENf, 2337 MOD_MAP_PARITY_STATUS_INTRr, NULL, 2338 MOD_MAP_PARITY_STATUS_NACKr, NULL }, 2339 /* FP_UDF_PARITY_CONTROLr */ 2340 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2341 FP_UDF_PAR_ERRf, 2342 FP_UDF_PAR_ERRf, 2343 FP_UDF_OFFSETm, NULL, 2344 FP_UDF_PARITY_CONTROLr, PARITY_ENf, 2345 FP_UDF_PARITY_STATUS_INTRr, NULL, 2346 FP_UDF_PARITY_STATUS_NACKr, NULL }, 2347 /* L3_TUNNEL_PARITY_CONTROLr */ 2348 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2349 L3_TUNNEL_PAR_ERRf, 2350 L3_TUNNEL_PAR_ERRf, 2351 L3_TUNNELm, NULL, 2352 L3_TUNNEL_PARITY_CONTROLr, PARITY_ENf, 2353 L3_TUNNEL_PARITY_STATUS_INTRr, NULL, 2354 L3_TUNNEL_PARITY_STATUS_NACKr, NULL }, 2355 /* SRC_TRUNK_ECC_CONTROLr */ 2356 { _SOC_PARITY_TYPE_ECC, NULL, 0, 2357 SOURCE_TRUNK_MAP_PARITY_ERRf, 2358 SOURCE_TRUNK_MAP_PARITY_ERRf, 2359 SOURCE_TRUNK_MAP_TABLEm, NULL, 2360 SRC_TRUNK_ECC_CONTROLr, ECC_ENf, 2361 SRC_TRUNK_ECC_STATUS_INTRr, NULL, 2362 SRC_TRUNK_ECC_STATUS_NACKr, NULL }, 2363 /* LPORT_ECC_CONTROLr */ 2364 { _SOC_PARITY_TYPE_ECC, NULL, 0, 2365 LPORT_PAR_ERRf, 2366 LPORT_PAR_ERRf, 2367 LPORT_TABm, NULL, 2368 LPORT_ECC_CONTROLr, ECC_ENf, 2369 LPORT_ECC_STATUS_INTRr, NULL, 2370 LPORT_ECC_STATUS_NACKr, NULL }, 2371 2372 /* Block-IPIPE; Stage-ICFG */ 2373 2374 /* PORT_TABLE_ECC_CONTROLr */ 2375 { _SOC_PARITY_TYPE_ECC, NULL, 0, 2376 PORT_TABLE_PAR_ERRf, 2377 PORT_TABLE_PAR_ERRf, 2378 PORT_TABm, NULL, 2379 PORT_TABLE_ECC_CONTROLr, ECC_ENf, 2380 PORT_TABLE_ECC_STATUS_INTRr, NULL, 2381 PORT_TABLE_ECC_STATUS_NACKr, NULL }, 2382 /* SYSTEM_CONFIG_PARITY_CONTROLr */ 2383 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2384 SYS_CONFIG_PAR_ERRf, 2385 SYS_CONFIG_PAR_ERRf, 2386 SYSTEM_CONFIG_TABLEm, NULL, 2387 SYSTEM_CONFIG_PARITY_CONTROLr, PARITY_ENf, 2388 SYSTEM_CONFIG_PARITY_STATUS_INTRr, NULL, 2389 SYSTEM_CONFIG_PARITY_STATUS_NACKr, NULL }, 2390 /* SYSTEM_CONFIG_MODVIEW_PARITY_CONTROLr */ 2391 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2392 SYSTEM_CONFIG_MODVIEW_PAR_ERRf, 2393 SYSTEM_CONFIG_MODVIEW_PAR_ERRf, 2394 SYSTEM_CONFIG_TABLE_MODBASEm, NULL, 2395 SYSTEM_CONFIG_MODVIEW_PARITY_CONTROLr, PARITY_ENf, 2396 SYSTEM_CONFIG_MODVIEW_PARITY_STATUS_INTRr, NULL, 2397 SYSTEM_CONFIG_MODVIEW_PARITY_STATUS_NACKr, NULL }, 2398 /* SOURCE_TRUNK_MAP_MODVIEW_PARITY_CONTROLr */ 2399 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2400 SOURCE_TRUNK_MAP_MODVIEW_PAR_ERRf, 2401 SOURCE_TRUNK_MAP_MODVIEW_PAR_ERRf, 2402 SOURCE_TRUNK_MAP_MODBASEm, NULL, 2403 SOURCE_TRUNK_MAP_MODVIEW_PARITY_CONTROLr, PARITY_ENf, 2404 SOURCE_TRUNK_MAP_MODVIEW_PARITY_STATUS_INTRr, NULL, 2405 SOURCE_TRUNK_MAP_MODVIEW_PARITY_STATUS_NACKr, NULL }, 2406 { _SOC_PARITY_TYPE_NONE } /* table terminator */ 2407 }; 2408 2409 STATIC _soc_katana_parity_info_t _soc_katana_ip1_parity_info[] = { 2410 /* Block-IPIPE; Stage- IPMLS */ 2411 /* SOURCE_VP_PARITY_CONTROLr */ 2412 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2413 SOURCE_VP_PAR_ERRf, 2414 SOURCE_VP_PAR_ERRf, 2415 SOURCE_VPm, NULL, 2416 SOURCE_VP_PARITY_CONTROLr, PARITY_ENf, 2417 SOURCE_VP_PARITY_STATUS_INTRr, NULL, 2418 SOURCE_VP_PARITY_STATUS_NACKr, NULL }, 2419 /* VFI_1_PARITY_CONTROLr */ 2420 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2421 VFI_1_PAR_ERRf, 2422 VFI_1_PAR_ERRf, 2423 VFI_1m, NULL, 2424 VFI_1_PARITY_CONTROLr, PARITY_ENf, 2425 VFI_1_PARITY_STATUS_INTRr, NULL, 2426 VFI_1_PARITY_STATUS_NACKr, NULL }, 2427 /* L3_IIF_PARITY_CONTROLr */ 2428 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2429 L3_IIF_PAR_ERRf, 2430 L3_IIF_PAR_ERRf, 2431 L3_IIFm, NULL, 2432 L3_IIF_PARITY_CONTROLr, PARITY_ENf, 2433 L3_IIF_PARITY_STATUS_INTRr, NULL, 2434 L3_IIF_PARITY_STATUS_NACKr, NULL }, 2435 /* VFI_PARITY_CONTROLr */ 2436 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2437 VFI_PAR_ERRf, 2438 VFI_PAR_ERRf, 2439 VFIm, NULL, 2440 VFI_PARITY_CONTROLr, PARITY_ENf, 2441 VFI_PARITY_STATUS_INTRr, NULL, 2442 VFI_PARITY_STATUS_NACKr, NULL }, 2443 /* VRF_PARITY_CONTROLr */ 2444 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2445 VRF_PAR_ERRf, 2446 VRF_PAR_ERRf, 2447 VRFm, NULL, 2448 VRF_PARITY_CONTROLr, PARITY_ENf, 2449 VRF_PARITY_STATUS_INTRr, NULL, 2450 VRF_PARITY_STATUS_NACKr, NULL }, 2451 /* VLAN_MPLS_PARITY_CONTROLr */ 2452 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2453 VLAN_MPLS_PAR_ERRf, 2454 VLAN_MPLS_PAR_ERRf, 2455 VLAN_MPLSm, NULL, 2456 VLAN_MPLS_PARITY_CONTROLr, PARITY_ENf, 2457 VLAN_MPLS_PARITY_STATUS_INTRr, NULL, 2458 VLAN_MPLS_PARITY_STATUS_NACKr, NULL }, 2459 /* VLAN_PARITY_CONTROLr */ 2460 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2461 VLAN_PAR_ERRf, 2462 VLAN_PAR_ERRf, 2463 VLAN_TABm, NULL, 2464 VLAN_PARITY_CONTROLr, PARITY_ENf, 2465 VLAN_PARITY_STATUS_INTRr, NULL, 2466 VLAN_PARITY_STATUS_NACKr, NULL }, 2467 /* VLAN_STG_PARITY_CONTROLr */ 2468 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2469 VLAN_STG_PAR_ERRf, 2470 VLAN_STG_PAR_ERRf, 2471 STG_TABm, NULL, 2472 VLAN_STG_PARITY_CONTROLr, PARITY_ENf, 2473 VLAN_STG_PARITY_STATUS_INTRr, NULL, 2474 VLAN_STG_PARITY_STATUS_NACKr, NULL }, 2475 2476 /* Block-IPIPE; Stage-IL3LU */ 2477 /* L3_ENTRY_PARITY_CONTROLr */ 2478 { _SOC_PARITY_TYPE_HASH, NULL, 0, 2479 L3_ENTRY_PAR_ERRf, 2480 L3_ENTRY_PAR_ERRf, 2481 L3_ENTRY_IPV6_UNICASTm, NULL, 2482 L3_ENTRY_PARITY_CONTROLr, PARITY_ENf, 2483 INVALIDr, _soc_katana_l3_entry_ipv6_unicast_intr_reg, 2484 INVALIDr, _soc_katana_l3_entry_ipv6_unicast_nack_reg }, 2485 2486 2487 /* Block-IPIPE; Stage-ILPM */ 2488 /* L3_DEFIP_DATA_PARITY_CONTROLr */ 2489 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2490 L3_DEFIP_PAR_ERRf, 2491 L3_DEFIP_PAR_ERRf, 2492 L3_DEFIPm, NULL, 2493 L3_DEFIP_DATA_PARITY_CONTROLr, PARITY_ENf, 2494 L3_DEFIP_DATA_PARITY_STATUS_INTRr, NULL, 2495 L3_DEFIP_DATA_PARITY_STATUS_NACKr, NULL }, 2496 /* L3_DEFIP_128_DATA_PARITY_CONTROLr */ 2497 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2498 L3_DEFIP_128_PAR_ERRf, 2499 L3_DEFIP_128_PAR_ERRf, 2500 L3_DEFIP_128m, NULL, 2501 L3_DEFIP_128_DATA_PARITY_CONTROLr, PARITY_ENf, 2502 L3_DEFIP_128_DATA_PARITY_STATUS_INTRr, NULL, 2503 L3_DEFIP_128_DATA_PARITY_STATUS_NACKr, NULL }, 2504 2505 /* Block-IPIPE; Stage-ISW1 */ 2506 2507 /* FP_FIELD_SEL_PARITY_CONTROLr */ 2508 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2509 FP_FIELD_SEL_PAR_ERRf, 2510 FP_FIELD_SEL_PAR_ERRf, 2511 FP_PORT_FIELD_SELm, NULL, 2512 FP_FIELD_SEL_PARITY_CONTROLr, PARITY_ENf, 2513 FP_FIELD_SEL_PARITY_STATUS_INTRr, NULL, 2514 FP_FIELD_SEL_PARITY_STATUS_NACKr, NULL }, 2515 /* TTL_FN_PARITY_CONTROLr */ 2516 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2517 TTL_FN_PAR_ERRf, 2518 TTL_FN_PAR_ERRf, 2519 TTL_FNm, NULL, 2520 TTL_FN_PARITY_CONTROLr, PARITY_ENf, 2521 TTL_FN_PARITY_STATUS_INTRr, NULL, 2522 TTL_FN_PARITY_STATUS_NACKr, NULL }, 2523 /* TOS_FN_PARITY_CONTROLr */ 2524 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2525 TOS_FN_PAR_ERRf, 2526 TOS_FN_PAR_ERRf, 2527 TOS_FNm, NULL, 2528 TOS_FN_PARITY_CONTROLr, PARITY_ENf, 2529 TOS_FN_PARITY_STATUS_INTRr, NULL, 2530 TOS_FN_PARITY_STATUS_NACKr, NULL }, 2531 /* ING_PRI_CNG_MAP_PARITY_CONTROLr */ 2532 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2533 ING_PRI_CNG_MAP_PAR_ERRf, 2534 ING_PRI_CNG_MAP_PAR_ERRf, 2535 ING_PRI_CNG_MAPm, NULL, 2536 ING_PRI_CNG_MAP_PARITY_CONTROLr, PARITY_ENf, 2537 ING_PRI_CNG_MAP_PARITY_STATUS_INTRr, NULL, 2538 ING_PRI_CNG_MAP_PARITY_STATUS_NACKr, NULL }, 2539 /* ING_UNTAGGED_PHB_PARITY_CONTROLr */ 2540 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2541 ING_UNTAGGED_PHB_PAR_ERRf, 2542 ING_UNTAGGED_PHB_PAR_ERRf, 2543 ING_UNTAGGED_PHBm, NULL, 2544 ING_UNTAGGED_PHB_PARITY_CONTROLr, PARITY_ENf, 2545 ING_UNTAGGED_PHB_PARITY_STATUS_INTRr, NULL, 2546 ING_UNTAGGED_PHB_PARITY_STATUS_NACKr, NULL }, 2547 /* DSCP_TABLE_PARITY_CONTROLr */ 2548 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2549 DSCP_TABLE_PAR_ERRf, 2550 DSCP_TABLE_PAR_ERRf, 2551 DSCP_TABLEm, NULL, 2552 DSCP_TABLE_PARITY_CONTROLr, PARITY_ENf, 2553 DSCP_TABLE_PARITY_STATUS_INTRr, NULL, 2554 DSCP_TABLE_PARITY_STATUS_NACKr, NULL }, 2555 2556 /* Block-IPIPE; Stage-IL2LU */ 2557 /* L2_ENTRY_PARITY_CONTROLr */ 2558 { _SOC_PARITY_TYPE_HASH, NULL, 0, 2559 L2_ENTRY_PAR_ERRf, 2560 L2_ENTRY_PAR_ERRf, 2561 L2Xm, NULL, 2562 L2_ENTRY_PARITY_CONTROLr, PARITY_ENf, 2563 INVALIDr, _soc_katana_l2_entry_only_intr_reg, 2564 INVALIDr, _soc_katana_l2_entry_only_nack_reg }, 2565 2566 /* Block-IPIPE; Stage-ISREL1 */ 2567 /* INITIAL_ING_L3_NEXT_HOP_PARITY_CONTROLr */ 2568 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2569 NHOP_PAR_ERRf, 2570 NHOP_PAR_ERRf, 2571 INITIAL_ING_L3_NEXT_HOPm, NULL, 2572 INITIAL_ING_L3_NEXT_HOP_PARITY_CONTROLr, PARITY_ENf, 2573 INITIAL_ING_L3_NEXT_HOP_PARITY_STATUS_INTRr, NULL, 2574 INITIAL_ING_L3_NEXT_HOP_PARITY_STATUS_NACKr, NULL }, 2575 /* INITIAL_L3_ECMP_GROUP_PARITY_CONTROLr */ 2576 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2577 ECMP_GRP_PAR_ERRf, 2578 ECMP_GRP_PAR_ERRf, 2579 INITIAL_L3_ECMP_GROUPm, NULL, 2580 INITIAL_L3_ECMP_GROUP_PARITY_CONTROLr, PARITY_ENf, 2581 INITIAL_L3_ECMP_GROUP_PARITY_STATUS_INTRr, NULL, 2582 INITIAL_L3_ECMP_GROUP_PARITY_STATUS_NACKr, NULL }, 2583 /* INITIAL_L3_ECMP_PARITY_CONTROLr */ 2584 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2585 L3_ECMP_PAR_ERRf, 2586 L3_ECMP_PAR_ERRf, 2587 INITIAL_L3_ECMPm, NULL, 2588 INITIAL_L3_ECMP_PARITY_CONTROLr, PARITY_ENf, 2589 INITIAL_L3_ECMP_PARITY_STATUS_INTRr, NULL, 2590 INITIAL_L3_ECMP_PARITY_STATUS_NACKr, NULL }, 2591 /* ING_DVP_TABLE_PARITY_STATUS_INTRr */ 2592 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2593 ING_DVP_PAR_ERRf, 2594 ING_DVP_PAR_ERRf, 2595 ING_DVP_TABLEm, NULL, 2596 ING_DVP_TABLE_PARITY_CONTROLr, PARITY_ENf, 2597 ING_DVP_TABLE_PARITY_STATUS_INTRr, NULL, 2598 ING_DVP_TABLE_PARITY_STATUS_NACKr, NULL }, 2599 /* INITIAL_PROT_NHI_TABLE_PARITY_CONTROLr */ 2600 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2601 PROT_NHI_PAR_ERRf, 2602 PROT_NHI_PAR_ERRf, 2603 INITIAL_PROT_NHI_TABLEm, NULL, 2604 INITIAL_PROT_NHI_TABLE_PARITY_CONTROLr, PARITY_ENf, 2605 INITIAL_PROT_NHI_TABLE_PARITY_STATUS_INTRr, NULL, 2606 INITIAL_PROT_NHI_TABLE_PARITY_STATUS_NACKr, NULL }, 2607 /* PORT_CBL_TABLE_PARITY_CONTROLr */ 2608 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2609 PORT_CBL_PAR_ERRf, 2610 PORT_CBL_PAR_ERRf, 2611 PORT_CBL_TABLEm, NULL, 2612 PORT_CBL_TABLE_PARITY_CONTROLr, PARITY_ENf, 2613 PORT_CBL_TABLE_PARITY_STATUS_INTRr, NULL, 2614 PORT_CBL_TABLE_PARITY_STATUS_NACKr, NULL }, 2615 /* PORT_CBL_TABLE_MODBASE_PARITY_CONTROLr */ 2616 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2617 PORT_CBL_MODBASE_PAR_ERRf, 2618 PORT_CBL_MODBASE_PAR_ERRf, 2619 PORT_CBL_TABLE_MODBASEm, NULL, 2620 PORT_CBL_TABLE_MODBASE_PARITY_CONTROLr, PARITY_ENf, 2621 PORT_CBL_TABLE_MODBASE_PARITY_STATUS_INTRr, NULL, 2622 PORT_CBL_TABLE_MODBASE_PARITY_STATUS_NACKr, NULL }, 2623 /* L3_IPMC_1_PARITY_CONTROLr */ 2624 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2625 L3_IPMC_1_PAR_ERRf, 2626 L3_IPMC_1_PAR_ERRf, 2627 L3_IPMC_1m, NULL, 2628 L3_IPMC_1_PARITY_CONTROLr, PARITY_ENf, 2629 L3_IPMC_1_PARITY_STATUS_INTRr, NULL, 2630 L3_IPMC_1_PARITY_STATUS_NACKr, NULL }, 2631 /* MA_INDEX_PARITY_CONTROLr */ 2632 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2633 MA_INDEX_PAR_ERRf, 2634 MA_INDEX_PAR_ERRf, 2635 MA_INDEXm, NULL, 2636 MA_INDEX_PARITY_CONTROLr, PARITY_ENf, 2637 MA_INDEX_PARITY_STATUS_INTRr, NULL, 2638 MA_INDEX_PARITY_STATUS_NACKr, NULL }, 2639 /* RMEP_PARITY_CONTROLr */ 2640 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2641 RMEP_PAR_ERRf, 2642 RMEP_PAR_ERRf, 2643 RMEPm, NULL, 2644 RMEP_PARITY_CONTROLr, PARITY_ENf, 2645 RMEP_PARITY_STATUS_INTRr, NULL, 2646 RMEP_PARITY_STATUS_NACKr, NULL }, 2647 /* MAID_REDUCTION_PARITY_CONTROLr */ 2648 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2649 MAID_REDUCTION_PAR_ERRf, 2650 MAID_REDUCTION_PAR_ERRf, 2651 MAID_REDUCTIONm, NULL, 2652 MAID_REDUCTION_PARITY_CONTROLr, PARITY_ENf, 2653 MAID_REDUCTION_PARITY_STATUS_INTRr, NULL, 2654 MAID_REDUCTION_PARITY_STATUS_NACKr, NULL }, 2655 /* MA_STATE_PARITY_CONTROLr */ 2656 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2657 MA_STATE_PAR_ERRf, 2658 MA_STATE_PAR_ERRf, 2659 MA_STATEm, NULL, 2660 MA_STATE_PARITY_CONTROLr, PARITY_ENf, 2661 MA_STATE_PARITY_STATUS_INTRr, NULL, 2662 MA_STATE_PARITY_STATUS_NACKr, NULL }, 2663 2664 2665 /* Block-IPIPE; Stage-IL2LU */ 2666 /* VLAN_OR_VFI_MAC_COUNT_PARITY_CONTROLr */ 2667 { _SOC_PARITY_TYPE_HASH, NULL, 0, 2668 VLAN_OR_VFI_MAC_COUNT_PAR_ERRf, 2669 VLAN_OR_VFI_MAC_COUNT_PAR_ERRf, 2670 VLAN_OR_VFI_MAC_COUNTm, NULL, 2671 VLAN_OR_VFI_MAC_COUNT_PARITY_CONTROLr, PARITY_ENf, 2672 VLAN_OR_VFI_MAC_COUNT_PARITY_STATUS_INTRr, NULL, 2673 VLAN_OR_VFI_MAC_COUNT_PARITY_STATUS_INTRr, NULL }, 2674 /* VLAN_OR_VFI_MAC_LIMIT_PARITY_CONTROLr */ 2675 { _SOC_PARITY_TYPE_HASH, NULL, 0, 2676 VLAN_OR_VFI_MAC_LIMIT_PAR_ERRf, 2677 VLAN_OR_VFI_MAC_LIMIT_PAR_ERRf, 2678 VLAN_OR_VFI_MAC_LIMITm, NULL, 2679 VLAN_OR_VFI_MAC_LIMIT_PARITY_CONTROLr, PARITY_ENf, 2680 VLAN_OR_VFI_MAC_LIMIT_PARITY_STATUS_INTRr, NULL, 2681 VLAN_OR_VFI_MAC_LIMIT_PARITY_STATUS_INTRr, NULL }, 2682 { _SOC_PARITY_TYPE_NONE } /* table terminator */ 2683 }; 2684 2685 STATIC _soc_katana_parity_info_t _soc_katana_ip1_1_parity_info[] = { 2686 /* Block-IPIPE; Stage-IL2LU */ 2687 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2688 L2_MOD_FIFO_INTRf, 2689 L2_MOD_FIFO_INTRf, 2690 L2_MOD_FIFOm, NULL, 2691 L2_MOD_FIFO_PARITY_CONTROLr, PARITY_ENf, 2692 L2_MOD_FIFO_PARITY_STATUS_INTRr, NULL, 2693 L2_MOD_FIFO_PARITY_STATUS_NACKr, NULL }, 2694 /* Block-IPIPE; Stage-IMPLS */ 2695 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2696 MY_STATION_TCAM_DATA_ONLY_PAR_ERRf, 2697 MY_STATION_TCAM_DATA_ONLY_PAR_ERRf, 2698 MY_STATION_TCAM_DATA_ONLYm, NULL, 2699 MY_STATION_DATA_PARITY_CONTROLr, PARITY_ENf, 2700 MY_STATION_DATA_PARITY_STATUS_INTRr, NULL, 2701 MY_STATION_DATA_PARITY_STATUS_NACKr, NULL }, 2702 { _SOC_PARITY_TYPE_NONE } /* table terminator */ 2703 }; 2704 2705 2706 STATIC _soc_katana_parity_info_t _soc_katana_ip2_parity_info[] = { 2707 /* Block-IPIPE; Stage-IDLB */ 2708 /* DLB_HGT_FLOWSET_PORT_PARITY_CONTROLr */ 2709 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2710 DLB_HGT_FLOWSET_PORT_PAR_ERRf, 2711 DLB_HGT_FLOWSET_PORT_PAR_ERRf, 2712 DLB_HGT_FLOWSET_PORTm, NULL, 2713 DLB_HGT_FLOWSET_PORT_PARITY_CONTROLr, PARITY_ENf, 2714 DLB_HGT_FLOWSET_PORT_PARITY_STATUS_INTRr, NULL, 2715 DLB_HGT_FLOWSET_PORT_PARITY_STATUS_NACKr, NULL }, 2716 /* DLB_HGT_FLOWSET_TIMESTAMP_PARITY_CONTROLr */ 2717 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2718 DLB_HGT_FLOWSET_TIMESTAMP_PAR_ERRf, 2719 DLB_HGT_FLOWSET_TIMESTAMP_PAR_ERRf, 2720 DLB_HGT_FLOWSET_TIMESTAMPm, NULL, 2721 DLB_HGT_FLOWSET_TIMESTAMP_PARITY_CONTROLr, PARITY_ENf, 2722 DLB_HGT_FLOWSET_TIMESTAMP_PARITY_STATUS_INTRr, NULL, 2723 DLB_HGT_FLOWSET_TIMESTAMP_PARITY_STATUS_NACKr, NULL }, 2724 /* DLB_HGT_FLOWSET_TIMESTAMP_PAGE_PARITY_CONTROLr */ 2725 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2726 DLB_HGT_FLOWSET_TIMESTAMP_PAGE_PAR_ERRf, 2727 DLB_HGT_FLOWSET_TIMESTAMP_PAGE_PAR_ERRf, 2728 DLB_HGT_FLOWSET_TIMESTAMP_PAGEm, NULL, 2729 DLB_HGT_FLOWSET_TIMESTAMP_PAGE_PARITY_CONTROLr, PARITY_ENf, 2730 DLB_HGT_FLOWSET_TIMESTAMP_PAGE_PARITY_STATUS_INTRr, NULL, 2731 DLB_HGT_FLOWSET_TIMESTAMP_PAGE_PARITY_STATUS_NACKr, NULL }, 2732 2733 2734 /* Block-IPIPE; Stage-ISREL2 */ 2735 /* ING_L3_NEXT_HOP_PARITY_CONTROLr */ 2736 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2737 IRSEL2_ING_L3_NEXT_HOP_PAR_ERRf, 2738 IRSEL2_ING_L3_NEXT_HOP_PAR_ERRf, 2739 ING_L3_NEXT_HOPm, NULL, 2740 ING_L3_NEXT_HOP_PARITY_CONTROLr, PARITY_ENf, 2741 ING_L3_NEXT_HOP_PARITY_STATUS_INTRr, NULL, 2742 ING_L3_NEXT_HOP_PARITY_STATUS_NACKr, NULL }, 2743 /* L3_IPMC_REMAP_PARITY_CONTROLr */ 2744 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2745 IRSEL2_L3_IPMC_REMAP_PAR_ERRf, 2746 IRSEL2_L3_IPMC_REMAP_PAR_ERRf, 2747 L3_IPMC_REMAPm, NULL, 2748 L3_IPMC_REMAP_PARITY_CONTROLr, PARITY_ENf, 2749 L3_IPMC_REMAP_PARITY_STATUS_INTRr, NULL, 2750 L3_IPMC_REMAP_PARITY_STATUS_NACKr, NULL }, 2751 /* L3_IPMC_PARITY_CONTROLr */ 2752 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2753 IRSEL2_L3_IPMC_PAR_ERRf, 2754 IRSEL2_L3_IPMC_PAR_ERRf, 2755 L3_IPMCm, NULL, 2756 L3_IPMC_PARITY_CONTROLr, PARITY_ENf, 2757 L3_IPMC_PARITY_STATUS_INTRr, NULL, 2758 L3_IPMC_PARITY_STATUS_NACKr, NULL }, 2759 /* L2MC_PARITY_CONTROLr */ 2760 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2761 IRSEL2_L2MC_PAR_ERRf, 2762 IRSEL2_L2MC_PAR_ERRf, 2763 L2MCm, NULL, 2764 L2MC_PARITY_CONTROLr, PARITY_ENf, 2765 L2MC_PARITY_STATUS_INTRr, NULL, 2766 L2MC_PARITY_STATUS_NACKr, NULL }, 2767 /* IFP_REDIRECTION_PROFILE_PARITY_CONTROLr */ 2768 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2769 IRSEL2_IFP_REDIRECTION_PROFILE_PAR_ERRf, 2770 IRSEL2_IFP_REDIRECTION_PROFILE_PAR_ERRf, 2771 IFP_REDIRECTION_PROFILEm, NULL, 2772 IFP_REDIRECTION_PROFILE_PARITY_CONTROLr, PARITY_ENf, 2773 IFP_REDIRECTION_PROFILE_PARITY_STATUS_INTRr, NULL, 2774 IFP_REDIRECTION_PROFILE_PARITY_STATUS_NACKr, NULL }, 2775 /* L3_ECMP_GROUP_PARITY_CONTROLr */ 2776 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2777 IRSEL2_L3_ECMP_GROUP_PAR_ERRf, 2778 IRSEL2_L3_ECMP_GROUP_PAR_ERRf, 2779 L3_ECMP_COUNTm, NULL, 2780 L3_ECMP_GROUP_PARITY_CONTROLr, PARITY_ENf, 2781 L3_ECMP_GROUP_PARITY_STATUS_INTRr, NULL, 2782 L3_ECMP_GROUP_PARITY_STATUS_NACKr, NULL }, 2783 /* L3_ECMP_PARITY_CONTROLr */ 2784 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2785 IRSEL2_L3_ECMP_PAR_ERRf, 2786 IRSEL2_L3_ECMP_PAR_ERRf, 2787 L3_ECMPm, NULL, 2788 L3_ECMP_PARITY_CONTROLr, PARITY_ENf, 2789 L3_ECMP_PARITY_STATUS_INTRr, NULL, 2790 L3_ECMP_PARITY_STATUS_NACKr, NULL }, 2791 /* EGR_MASK_MODBASE_PARITY_CONTROLr */ 2792 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2793 IRSEL2_EGR_MASK_MODBASE_PAR_ERRf, 2794 IRSEL2_EGR_MASK_MODBASE_PAR_ERRf, 2795 EGR_MASK_MODBASEm, NULL, 2796 EGR_MASK_MODBASE_PARITY_CONTROLr, PARITY_ENf, 2797 EGR_MASK_MODBASE_PARITY_STATUS_INTRr, NULL, 2798 EGR_MASK_MODBASE_PARITY_STATUS_NACKr, NULL }, 2799 2800 /* Block-IPIPE; Stage-IFP */ 2801 2802 /* IFP_COUNTER_PARITY_CONTROLr */ 2803 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2804 IFP_COUNTER_PAR_ERRf, 2805 IFP_COUNTER_PAR_ERRf, 2806 FP_COUNTER_TABLEm, NULL, 2807 IFP_COUNTER_PARITY_CONTROLr, PARITY_ENf, 2808 IFP_COUNTER_PARITY_STATUS_INTRr, NULL, 2809 IFP_COUNTER_PARITY_STATUS_NACKr, NULL }, 2810 /* IFP_METER_PARITY_CONTROLr */ 2811 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2812 IFP_METER_PAR_ERRf, 2813 IFP_METER_PAR_ERRf, 2814 FP_METER_TABLEm, NULL, 2815 IFP_METER_PARITY_CONTROLr, PARITY_ENf, 2816 IFP_METER_PARITY_STATUS_INTRr, NULL, 2817 IFP_METER_PARITY_STATUS_NACKr, NULL }, 2818 /* IFP_POLICY_PARITY_CONTROLr */ 2819 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2820 IFP_POLICY_PAR_ERRf, 2821 IFP_POLICY_PAR_ERRf, 2822 FP_POLICY_TABLEm, NULL, 2823 IFP_POLICY_PARITY_CONTROLr, PARITY_ENf, 2824 IFP_POLICY_PARITY_STATUS_INTRr, NULL, 2825 IFP_POLICY_PARITY_STATUS_NACKr, NULL }, 2826 /* IFP_STORM_CONTROL_PARITY_CONTROLr */ 2827 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2828 IFP_STORM_CONTROL_PAR_ERRf, 2829 IFP_STORM_CONTROL_PAR_ERRf, 2830 FP_STORM_CONTROL_METERSm, NULL, 2831 IFP_STORM_CONTROL_PARITY_CONTROLr, PARITY_ENf, 2832 IFP_STORM_CONTROL_PARITY_STATUS_INTRr, NULL, 2833 IFP_STORM_CONTROL_PARITY_STATUS_NACKr, NULL }, 2834 2835 /* Block-ING_FLEX_CTR_BLOCKS; Stage-FLEX_CTR */ 2836 2837 /* ING_FLEX_CTR_OFFSET_TABLE_CONTROL_Xr */ 2838 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2839 ING_FLEX_CTR_POOL_0_OFFSET_TABLE_INTR_STATUSf, 2840 ING_FLEX_CTR_POOL_0_OFFSET_TABLE_INTR_STATUSf, 2841 ING_FLEX_CTR_OFFSET_TABLE_0m, NULL, 2842 ING_FLEX_CTR_OFFSET_TABLE_CONTROL_0r, PARITY_ENf, 2843 ING_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_INTR_0r, NULL, 2844 ING_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_NACK_0r, NULL }, 2845 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2846 ING_FLEX_CTR_POOL_1_OFFSET_TABLE_INTR_STATUSf, 2847 ING_FLEX_CTR_POOL_1_OFFSET_TABLE_INTR_STATUSf, 2848 ING_FLEX_CTR_OFFSET_TABLE_1m, NULL, 2849 ING_FLEX_CTR_OFFSET_TABLE_CONTROL_1r, PARITY_ENf, 2850 ING_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_INTR_1r, NULL, 2851 ING_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_NACK_1r, NULL }, 2852 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2853 ING_FLEX_CTR_POOL_2_OFFSET_TABLE_INTR_STATUSf, 2854 ING_FLEX_CTR_POOL_2_OFFSET_TABLE_INTR_STATUSf, 2855 ING_FLEX_CTR_OFFSET_TABLE_2m, NULL, 2856 ING_FLEX_CTR_OFFSET_TABLE_CONTROL_2r, PARITY_ENf, 2857 ING_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_INTR_2r, NULL, 2858 ING_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_NACK_2r, NULL }, 2859 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2860 ING_FLEX_CTR_POOL_3_OFFSET_TABLE_INTR_STATUSf, 2861 ING_FLEX_CTR_POOL_3_OFFSET_TABLE_INTR_STATUSf, 2862 ING_FLEX_CTR_OFFSET_TABLE_3m, NULL, 2863 ING_FLEX_CTR_OFFSET_TABLE_CONTROL_3r, PARITY_ENf, 2864 ING_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_INTR_3r, NULL, 2865 ING_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_NACK_3r, NULL }, 2866 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2867 ING_FLEX_CTR_POOL_4_OFFSET_TABLE_INTR_STATUSf, 2868 ING_FLEX_CTR_POOL_4_OFFSET_TABLE_INTR_STATUSf, 2869 ING_FLEX_CTR_OFFSET_TABLE_4m, NULL, 2870 ING_FLEX_CTR_OFFSET_TABLE_CONTROL_4r, PARITY_ENf, 2871 ING_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_INTR_4r, NULL, 2872 ING_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_NACK_4r, NULL }, 2873 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2874 ING_FLEX_CTR_POOL_5_OFFSET_TABLE_INTR_STATUSf, 2875 ING_FLEX_CTR_POOL_5_OFFSET_TABLE_INTR_STATUSf, 2876 ING_FLEX_CTR_OFFSET_TABLE_5m, NULL, 2877 ING_FLEX_CTR_OFFSET_TABLE_CONTROL_5r, PARITY_ENf, 2878 ING_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_INTR_5r, NULL, 2879 ING_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_NACK_5r, NULL }, 2880 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2881 ING_FLEX_CTR_POOL_6_OFFSET_TABLE_INTR_STATUSf, 2882 ING_FLEX_CTR_POOL_6_OFFSET_TABLE_INTR_STATUSf, 2883 ING_FLEX_CTR_OFFSET_TABLE_6m, NULL, 2884 ING_FLEX_CTR_OFFSET_TABLE_CONTROL_6r, PARITY_ENf, 2885 ING_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_INTR_6r, NULL, 2886 ING_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_NACK_6r, NULL }, 2887 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2888 ING_FLEX_CTR_POOL_7_OFFSET_TABLE_INTR_STATUSf, 2889 ING_FLEX_CTR_POOL_7_OFFSET_TABLE_INTR_STATUSf, 2890 ING_FLEX_CTR_OFFSET_TABLE_7m, NULL, 2891 ING_FLEX_CTR_OFFSET_TABLE_CONTROL_7r, PARITY_ENf, 2892 ING_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_INTR_7r, NULL, 2893 ING_FLEX_CTR_OFFSET_TABLE_PARITY_STATUS_NACK_7r, NULL }, 2894 /* ING_FLEX_CTR_COUNTER_TABLE_CONTROL_Xr */ 2895 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2896 ING_FLEX_CTR_POOL_0_COUNTER_TABLE_INTR_STATUSf, 2897 ING_FLEX_CTR_POOL_0_COUNTER_TABLE_INTR_STATUSf, 2898 ING_FLEX_CTR_COUNTER_TABLE_0m, NULL, 2899 ING_FLEX_CTR_COUNTER_TABLE_CONTROL_0r, PARITY_ENf, 2900 ING_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_INTR_0r, NULL, 2901 ING_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_NACK_0r, NULL }, 2902 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2903 ING_FLEX_CTR_POOL_1_COUNTER_TABLE_INTR_STATUSf, 2904 ING_FLEX_CTR_POOL_1_COUNTER_TABLE_INTR_STATUSf, 2905 ING_FLEX_CTR_COUNTER_TABLE_1m, NULL, 2906 ING_FLEX_CTR_COUNTER_TABLE_CONTROL_1r, PARITY_ENf, 2907 ING_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_INTR_1r, NULL, 2908 ING_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_NACK_1r, NULL }, 2909 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2910 ING_FLEX_CTR_POOL_2_COUNTER_TABLE_INTR_STATUSf, 2911 ING_FLEX_CTR_POOL_2_COUNTER_TABLE_INTR_STATUSf, 2912 ING_FLEX_CTR_COUNTER_TABLE_2m, NULL, 2913 ING_FLEX_CTR_COUNTER_TABLE_CONTROL_2r, PARITY_ENf, 2914 ING_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_INTR_2r, NULL, 2915 ING_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_NACK_2r, NULL }, 2916 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2917 ING_FLEX_CTR_POOL_3_COUNTER_TABLE_INTR_STATUSf, 2918 ING_FLEX_CTR_POOL_3_COUNTER_TABLE_INTR_STATUSf, 2919 ING_FLEX_CTR_COUNTER_TABLE_3m, NULL, 2920 ING_FLEX_CTR_COUNTER_TABLE_CONTROL_3r, PARITY_ENf, 2921 ING_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_INTR_3r, NULL, 2922 ING_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_NACK_3r, NULL }, 2923 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2924 ING_FLEX_CTR_POOL_4_COUNTER_TABLE_INTR_STATUSf, 2925 ING_FLEX_CTR_POOL_4_COUNTER_TABLE_INTR_STATUSf, 2926 ING_FLEX_CTR_COUNTER_TABLE_4m, NULL, 2927 ING_FLEX_CTR_COUNTER_TABLE_CONTROL_4r, PARITY_ENf, 2928 ING_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_INTR_4r, NULL, 2929 ING_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_NACK_4r, NULL }, 2930 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2931 ING_FLEX_CTR_POOL_5_COUNTER_TABLE_INTR_STATUSf, 2932 ING_FLEX_CTR_POOL_5_COUNTER_TABLE_INTR_STATUSf, 2933 ING_FLEX_CTR_COUNTER_TABLE_5m, NULL, 2934 ING_FLEX_CTR_COUNTER_TABLE_CONTROL_5r, PARITY_ENf, 2935 ING_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_INTR_5r, NULL, 2936 ING_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_NACK_5r, NULL }, 2937 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2938 ING_FLEX_CTR_POOL_6_COUNTER_TABLE_INTR_STATUSf, 2939 ING_FLEX_CTR_POOL_6_COUNTER_TABLE_INTR_STATUSf, 2940 ING_FLEX_CTR_COUNTER_TABLE_6m, NULL, 2941 ING_FLEX_CTR_COUNTER_TABLE_CONTROL_6r, PARITY_ENf, 2942 ING_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_INTR_6r, NULL, 2943 ING_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_NACK_6r, NULL }, 2944 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2945 ING_FLEX_CTR_POOL_7_COUNTER_TABLE_INTR_STATUSf, 2946 ING_FLEX_CTR_POOL_7_COUNTER_TABLE_INTR_STATUSf, 2947 ING_FLEX_CTR_COUNTER_TABLE_7m, NULL, 2948 ING_FLEX_CTR_COUNTER_TABLE_CONTROL_7r, PARITY_ENf, 2949 ING_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_INTR_7r, NULL, 2950 ING_FLEX_CTR_COUNTER_TABLE_PARITY_STATUS_NACK_7r, NULL }, 2951 { _SOC_PARITY_TYPE_NONE } /* table terminator */ 2952 }; 2953 2954 STATIC _soc_katana_parity_info_t _soc_katana_ip2_1_parity_info[] = { 2955 /* Block-IPIPE; Stage-ISW2 */ 2956 /* EGR_MASK_PARITY_CONTROLr */ 2957 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2958 EGR_MASK_PAR_ERRf, 2959 EGR_MASK_PAR_ERRf, 2960 EGR_MASKm, NULL, 2961 EGR_MASK_PARITY_CONTROLr, PARITY_ENf, 2962 EGR_MASK_PARITY_STATUS_INTRr, NULL, 2963 EGR_MASK_PARITY_STATUS_NACKr, NULL }, 2964 /* TRUNK_BITMAP_TABLE_PARITY_CONTROLr */ 2965 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2966 TRUNK_BITMAP_PAR_ERRf, 2967 TRUNK_BITMAP_PAR_ERRf, 2968 TRUNK_BITMAPm, NULL, 2969 TRUNK_BITMAP_TABLE_PARITY_CONTROLr, PARITY_ENf, 2970 TRUNK_BITMAP_TABLE_PARITY_STATUS_INTRr, NULL, 2971 TRUNK_BITMAP_TABLE_PARITY_STATUS_NACKr, NULL }, 2972 /* NONUCAST_TRUNK_BLOCK_MASK_PARITY_CONTROLr */ 2973 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2974 NONUCAST_TRUNK_BLOCK_MASK_PAR_ERRf, 2975 NONUCAST_TRUNK_BLOCK_MASK_PAR_ERRf, 2976 NONUCAST_TRUNK_BLOCK_MASKm, NULL, 2977 NONUCAST_TRUNK_BLOCK_MASK_PARITY_CONTROLr, PARITY_ENf, 2978 NONUCAST_TRUNK_BLOCK_MASK_PARITY_STATUS_INTRr, NULL, 2979 NONUCAST_TRUNK_BLOCK_MASK_PARITY_STATUS_NACKr, NULL }, 2980 /* MAC_BLOCK_TABLE_PARITY_CONTROLr */ 2981 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2982 MAC_BLOCK_TABLE_PAR_ERRf, 2983 MAC_BLOCK_TABLE_PAR_ERRf, 2984 MAC_BLOCKm, NULL, 2985 MAC_BLOCK_TABLE_PARITY_CONTROLr, PARITY_ENf, 2986 MAC_BLOCK_TABLE_PARITY_STATUS_INTRr, NULL, 2987 MAC_BLOCK_TABLE_PARITY_STATUS_NACKr, NULL }, 2988 /* MODPORT_MAP_SW_PARITY_CONTROLr */ 2989 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2990 MODPORT_MAP_SW_PAR_ERRf, 2991 MODPORT_MAP_SW_PAR_ERRf, 2992 MODPORT_MAP_SWm, NULL, 2993 MODPORT_MAP_SW_PARITY_CONTROLr, PARITY_ENf, 2994 MODPORT_MAP_SW_PARITY_STATUS_INTRr, NULL, 2995 MODPORT_MAP_SW_PARITY_STATUS_NACKr, NULL }, 2996 /* MODPORT_MAP_MIRROR_PARITY_CONTROLr */ 2997 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 2998 MODPORT_MAP_M0_PAR_ERRf, 2999 MODPORT_MAP_M0_PAR_ERRf, 3000 MODPORT_MAP_M0m, NULL, 3001 MODPORT_MAP_MIRROR_PARITY_CONTROLr, PARITY_ENf, 3002 MODPORT_MAP_M0_PARITY_STATUS_INTRr, NULL, 3003 MODPORT_MAP_M0_PARITY_STATUS_NACKr, NULL }, 3004 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3005 MODPORT_MAP_M1_PAR_ERRf, 3006 MODPORT_MAP_M1_PAR_ERRf, 3007 MODPORT_MAP_M1m, NULL, 3008 MODPORT_MAP_MIRROR_PARITY_CONTROLr, PARITY_ENf, 3009 MODPORT_MAP_M1_PARITY_STATUS_INTRr, NULL, 3010 MODPORT_MAP_M1_PARITY_STATUS_NACKr, NULL }, 3011 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3012 MODPORT_MAP_M2_PAR_ERRf, 3013 MODPORT_MAP_M2_PAR_ERRf, 3014 MODPORT_MAP_M2m, NULL, 3015 MODPORT_MAP_MIRROR_PARITY_CONTROLr, PARITY_ENf, 3016 MODPORT_MAP_M2_PARITY_STATUS_INTRr, NULL, 3017 MODPORT_MAP_M2_PARITY_STATUS_NACKr, NULL }, 3018 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3019 MODPORT_MAP_M3_PAR_ERRf, 3020 MODPORT_MAP_M3_PAR_ERRf, 3021 MODPORT_MAP_M3m, NULL, 3022 MODPORT_MAP_MIRROR_PARITY_CONTROLr, PARITY_ENf, 3023 MODPORT_MAP_M3_PARITY_STATUS_INTRr, NULL, 3024 MODPORT_MAP_M3_PARITY_STATUS_NACKr, NULL }, 3025 /* SRC_MODID_INGRESS_BLOCK_PARITY_CONTROLr */ 3026 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3027 SRC_MODID_INGRESS_BLOCK_PAR_ERRf, 3028 SRC_MODID_INGRESS_BLOCK_PAR_ERRf, 3029 SRC_MODID_INGRESS_BLOCKm, NULL, 3030 SRC_MODID_INGRESS_BLOCK_PARITY_CONTROLr, PARITY_ENf, 3031 SRC_MODID_INGRESS_BLOCK_PARITY_STATUS_INTRr, NULL, 3032 SRC_MODID_INGRESS_BLOCK_PARITY_STATUS_NACKr, NULL }, 3033 /* SRC_MODID_EGRESS_PARITY_CONTROLr */ 3034 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3035 SRC_MODID_EGRESS_PAR_ERRf, 3036 SRC_MODID_EGRESS_PAR_ERRf, 3037 SRC_MODID_EGRESSm, NULL, 3038 SRC_MODID_EGRESS_PARITY_CONTROLr, PARITY_ENf, 3039 SRC_MODID_EGRESS_PARITY_STATUS_INTRr, NULL, 3040 SRC_MODID_EGRESS_PARITY_STATUS_NACKr, NULL }, 3041 /* ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROLr */ 3042 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3043 ALTERNATE_EMIRROR_BITMAP_PAR_ERRf, 3044 ALTERNATE_EMIRROR_BITMAP_PAR_ERRf, 3045 ALTERNATE_EMIRROR_BITMAPm, NULL, 3046 ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROLr, PARITY_ENf, 3047 ALTERNATE_EMIRROR_BITMAP_PARITY_STATUS_INTRr, NULL, 3048 ALTERNATE_EMIRROR_BITMAP_PARITY_STATUS_NACKr, NULL }, 3049 /* PORT_LAG_FAILOVER_SET_PARITY_CONTROLr */ 3050 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3051 PORT_LAG_FAILOVER_SET_PAR_ERRf, 3052 PORT_LAG_FAILOVER_SET_PAR_ERRf, 3053 PORT_LAG_FAILOVER_SETm, NULL, 3054 PORT_LAG_FAILOVER_SET_PARITY_CONTROLr, PARITY_ENf, 3055 PORT_LAG_FAILOVER_SET_PARITY_STATUS_INTRr, NULL, 3056 PORT_LAG_FAILOVER_SET_PARITY_STATUS_NACKr, NULL }, 3057 /* VLAN_PROFILE_2_PARITY_CONTROLr */ 3058 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3059 VLAN_PROFILE_2_PAR_ERRf, 3060 VLAN_PROFILE_2_PAR_ERRf, 3061 VLAN_PROFILE_2m, NULL, 3062 VLAN_PROFILE_2_PARITY_CONTROLr, PARITY_ENf, 3063 VLAN_PROFILE_2_PARITY_STATUS_INTRr, NULL, 3064 VLAN_PROFILE_2_PARITY_STATUS_NACKr, NULL }, 3065 /* L3_MTU_VALUES_PARITY_CONTROLr */ 3066 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3067 L3_MTU_VALUES_PAR_ERRf, 3068 L3_MTU_VALUES_PAR_ERRf, 3069 L3_MTU_VALUESm, NULL, 3070 L3_MTU_VALUES_PARITY_CONTROLr, PARITY_ENf, 3071 L3_MTU_VALUES_PARITY_STATUS_INTRr, NULL, 3072 L3_MTU_VALUES_PARITY_STATUS_NACKr, NULL }, 3073 /* ING_PW_TERM_SEQ_NUM_PARITY_CONTROLr */ 3074 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3075 ING_PW_TERM_SEQ_NUM_PAR_ERRf, 3076 ING_PW_TERM_SEQ_NUM_PAR_ERRf, 3077 ING_PW_TERM_SEQ_NUMm, NULL, 3078 ING_PW_TERM_SEQ_NUM_PARITY_CONTROLr, PARITY_ENf, 3079 ING_PW_TERM_SEQ_NUM_PARITY_STATUS_INTRr, NULL, 3080 ING_PW_TERM_SEQ_NUM_PARITY_STATUS_NACKr, NULL }, 3081 /* VLAN_COS_MAP_PARITY_CONTROLr */ 3082 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3083 VLAN_COS_MAP_PAR_ERRf, 3084 VLAN_COS_MAP_PAR_ERRf, 3085 VLAN_COS_MAPm, NULL, 3086 VLAN_COS_MAP_PARITY_CONTROLr, PARITY_ENf, 3087 VLAN_COS_MAP_PARITY_STATUS_INTRr, NULL, 3088 VLAN_COS_MAP_PARITY_STATUS_NACKr, NULL }, 3089 /* E2E_HOL_STATUS_PARITY_CONTROLr */ 3090 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3091 E2E_HOL_STATUS_PAR_ERRf, 3092 E2E_HOL_STATUS_PAR_ERRf, 3093 E2E_HOL_STATUSm, NULL, 3094 E2E_HOL_STATUS_PARITY_CONTROLr, PARITY_ENf, 3095 E2E_HOL_STATUS_PARITY_STATUS_INTRr, NULL, 3096 E2E_HOL_STATUS_PARITY_STATUS_NACKr, NULL }, 3097 /* E2E_HOL_STATUS_1_PARITY_CONTROLr */ 3098 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3099 E2E_HOL_STATUS_1_PAR_ERRf, 3100 E2E_HOL_STATUS_1_PAR_ERRf, 3101 E2E_HOL_STATUS_1m, NULL, 3102 E2E_HOL_STATUS_1_PARITY_CONTROLr, PARITY_ENf, 3103 E2E_HOL_STATUS_1_PARITY_STATUS_INTRr, NULL, 3104 E2E_HOL_STATUS_1_PARITY_STATUS_NACKr, NULL }, 3105 /* UNKNOWN_UCAST_BLOCK_MASK_PARITY_CONTROLr */ 3106 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3107 UNKNOWN_UCAST_BLOCK_MASK_PAR_ERRf, 3108 UNKNOWN_UCAST_BLOCK_MASK_PAR_ERRf, 3109 UNKNOWN_UCAST_BLOCK_MASKm, NULL, 3110 UNKNOWN_UCAST_BLOCK_MASK_PARITY_CONTROLr, PARITY_ENf, 3111 UNKNOWN_UCAST_BLOCK_MASK_PARITY_STATUS_INTRr, NULL, 3112 UNKNOWN_UCAST_BLOCK_MASK_PARITY_STATUS_NACKr, NULL }, 3113 /* UNKNOWN_MCAST_BLOCK_MASK_PARITY_CONTROLr */ 3114 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3115 UNKNOWN_MCAST_BLOCK_MASK_PAR_ERRf, 3116 UNKNOWN_MCAST_BLOCK_MASK_PAR_ERRf, 3117 UNKNOWN_MCAST_BLOCK_MASKm, NULL, 3118 UNKNOWN_MCAST_BLOCK_MASK_PARITY_CONTROLr, PARITY_ENf, 3119 UNKNOWN_MCAST_BLOCK_MASK_PARITY_STATUS_INTRr, NULL, 3120 UNKNOWN_MCAST_BLOCK_MASK_PARITY_STATUS_NACKr, NULL }, 3121 /* BCAST_BLOCK_MASK_PARITY_CONTROLr */ 3122 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3123 BCAST_BLOCK_MASK_PAR_ERRf, 3124 BCAST_BLOCK_MASK_PAR_ERRf, 3125 BCAST_BLOCK_MASKm, NULL, 3126 BCAST_BLOCK_MASK_PARITY_CONTROLr, PARITY_ENf, 3127 BCAST_BLOCK_MASK_PARITY_STATUS_INTRr, NULL, 3128 BCAST_BLOCK_MASK_PARITY_STATUS_NACKr, NULL }, 3129 /* KNOWN_MCAST_BLOCK_MASKm */ 3130 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3131 KNOWN_MCAST_BLOCK_MASK_PAR_ERRf, 3132 KNOWN_MCAST_BLOCK_MASK_PAR_ERRf, 3133 KNOWN_MCAST_BLOCK_MASKm, NULL, 3134 KNOWN_MCAST_BLOCK_MASK_PARITY_CONTROLr, PARITY_ENf, 3135 KNOWN_MCAST_BLOCK_MASK_PARITY_STATUS_INTRr, NULL, 3136 KNOWN_MCAST_BLOCK_MASK_PARITY_STATUS_NACKr, NULL }, 3137 /* ING_EGRMSKBMAP_PARITY_CONTROLr */ 3138 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3139 ING_EGRMSKBMAP_PAR_ERRf, 3140 ING_EGRMSKBMAP_PAR_ERRf, 3141 ING_EGRMSKBMAPm, NULL, 3142 ING_EGRMSKBMAP_PARITY_CONTROLr, PARITY_ENf, 3143 ING_EGRMSKBMAP_PARITY_STATUS_INTRr, NULL, 3144 ING_EGRMSKBMAP_PARITY_STATUS_NACKr, NULL }, 3145 /* LOCAL_SW_DISABLE_DEFAULT_PBM_PARITY_CONTROLr */ 3146 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3147 LOCAL_SW_DISABLE_DEFAULT_PBM_PAR_ERRf, 3148 LOCAL_SW_DISABLE_DEFAULT_PBM_PAR_ERRf, 3149 LOCAL_SW_DISABLE_DEFAULT_PBMm, NULL, 3150 LOCAL_SW_DISABLE_DEFAULT_PBM_PARITY_CONTROLr, PARITY_ENf, 3151 LOCAL_SW_DISABLE_DEFAULT_PBM_PARITY_STATUS_INTRr, NULL, 3152 LOCAL_SW_DISABLE_DEFAULT_PBM_PARITY_STATUS_NACKr, NULL }, 3153 /* LOCAL_SW_DISABLE_DEFAULT_PBM_MIRR_PARITY_CONTROLr */ 3154 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3155 LOCAL_SW_DISABLE_DEFAULT_PBM_MIRR_PAR_ERRf, 3156 LOCAL_SW_DISABLE_DEFAULT_PBM_MIRR_PAR_ERRf, 3157 LOCAL_SW_DISABLE_DEFAULT_PBM_MIRRm, NULL, 3158 LOCAL_SW_DISABLE_DEFAULT_PBM_MIRR_PARITY_CONTROLr, PARITY_ENf, 3159 LOCAL_SW_DISABLE_DEFAULT_PBM_MIRR_PARITY_STATUS_INTRr, NULL, 3160 LOCAL_SW_DISABLE_DEFAULT_PBM_MIRR_PARITY_STATUS_NACKr, NULL }, 3161 /* IMIRROR_BITMAP_PARITY_CONTROLr */ 3162 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3163 IMIRROR_BITMAP_PAR_ERRf, 3164 IMIRROR_BITMAP_PAR_ERRf, 3165 IMIRROR_BITMAPm, NULL, 3166 IMIRROR_BITMAP_PARITY_CONTROLr, PARITY_ENf, 3167 IMIRROR_BITMAP_PARITY_STATUS_INTRr, NULL, 3168 IMIRROR_BITMAP_PARITY_STATUS_NACKr, NULL }, 3169 /* UNKNOWN_HGI_BITMAP_PARITY_CONTROLr */ 3170 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3171 UNKNOWN_HGI_BITMAP_PAR_ERRf, 3172 UNKNOWN_HGI_BITMAP_PAR_ERRf, 3173 UNKNOWN_HGI_BITMAPm, NULL, 3174 UNKNOWN_HGI_BITMAP_PARITY_CONTROLr, PARITY_ENf, 3175 UNKNOWN_HGI_BITMAP_PARITY_STATUS_INTRr, NULL, 3176 UNKNOWN_HGI_BITMAP_PARITY_STATUS_NACKr, NULL }, 3177 /* TRUNK_MEMBER_PARITY_CONTROLr */ 3178 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3179 TRUNK_MEMBER_PAR_ERRf, 3180 TRUNK_MEMBER_PAR_ERRf, 3181 TRUNK_MEMBERm, NULL, 3182 TRUNK_MEMBER_PARITY_CONTROLr, PARITY_ENf, 3183 TRUNK_MEMBER_PARITY_STATUS_INTRr, NULL, 3184 TRUNK_MEMBER_PARITY_STATUS_NACKr, NULL }, 3185 /* PHB2_COS_MAP_PARITY_CONTROLr */ 3186 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3187 PHB2_COS_MAP_PAR_ERRf, 3188 PHB2_COS_MAP_PAR_ERRf, 3189 PHB2_COS_MAPm, NULL, 3190 PHB2_COS_MAP_PARITY_CONTROLr, PARITY_ENf, 3191 PHB2_COS_MAP_PARITY_STATUS_INTRr, NULL, 3192 PHB2_COS_MAP_PARITY_STATUS_NACKr, NULL }, 3193 { _SOC_PARITY_TYPE_NONE } /* table terminator */ 3194 }; 3195 3196 STATIC _soc_katana_parity_info_t _soc_katana_ip2_2_parity_info[] = { 3197 /* Block-IPIPE; Stage-ISW2 */ 3198 3199 /* EMIRROR_CONTROL_PARITY_CONTROLr */ 3200 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3201 EMIRROR_CONTROL_PAR_ERRf, 3202 EMIRROR_CONTROL_PAR_ERRf, 3203 EMIRROR_CONTROLm, NULL, 3204 EMIRROR_CONTROL_PARITY_CONTROLr, PARITY_ENf, 3205 EMIRROR_CONTROL_PARITY_STATUS_INTRr, NULL, 3206 EMIRROR_CONTROL_PARITY_STATUS_NACKr, NULL }, 3207 /* EMIRROR_CONTROL1_PARITY_CONTROLr */ 3208 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3209 EMIRROR_CONTROL1_PAR_ERRf, 3210 EMIRROR_CONTROL1_PAR_ERRf, 3211 EMIRROR_CONTROL1m, NULL, 3212 EMIRROR_CONTROL1_PARITY_CONTROLr, PARITY_ENf, 3213 EMIRROR_CONTROL1_PARITY_STATUS_INTRr, NULL, 3214 EMIRROR_CONTROL1_PARITY_STATUS_NACKr, NULL }, 3215 /* EMIRROR_CONTROL2_PARITY_CONTROLr */ 3216 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3217 EMIRROR_CONTROL2_PAR_ERRf, 3218 EMIRROR_CONTROL2_PAR_ERRf, 3219 EMIRROR_CONTROL2m, NULL, 3220 EMIRROR_CONTROL2_PARITY_CONTROLr, PARITY_ENf, 3221 EMIRROR_CONTROL2_PARITY_STATUS_INTRr, NULL, 3222 EMIRROR_CONTROL2_PARITY_STATUS_NACKr, NULL }, 3223 /* EMIRROR_CONTROL3_PARITY_CONTROLr */ 3224 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3225 EMIRROR_CONTROL3_PAR_ERRf, 3226 EMIRROR_CONTROL3_PAR_ERRf, 3227 EMIRROR_CONTROL3m, NULL, 3228 EMIRROR_CONTROL3_PARITY_CONTROLr, PARITY_ENf, 3229 EMIRROR_CONTROL3_PARITY_STATUS_INTRr, NULL, 3230 EMIRROR_CONTROL3_PARITY_STATUS_NACKr, NULL }, 3231 /* SW2_EOP_BUFFER_A_PARITY_CONTROLr */ 3232 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3233 SW2_EOP_BUFFER_A_PAR_ERRf, 3234 SW2_EOP_BUFFER_A_PAR_ERRf, 3235 INVALIDm, "SW2_EOP_BUFFER_A", 3236 SW2_EOP_BUFFER_A_PARITY_CONTROLr, PARITY_ENf, 3237 SW2_EOP_BUFFER_A_PARITY_STATUS_INTRr, NULL, 3238 INVALIDr, NULL }, 3239 /* SW2_EOP_BUFFER_B_PARITY_CONTROLr */ 3240 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3241 SW2_EOP_BUFFER_B_PAR_ERRf, 3242 SW2_EOP_BUFFER_B_PAR_ERRf, 3243 INVALIDm, "SW2_EOP_BUFFER_B", 3244 SW2_EOP_BUFFER_B_PARITY_CONTROLr, PARITY_ENf, 3245 SW2_EOP_BUFFER_B_PARITY_STATUS_INTRr, NULL, 3246 INVALIDr, NULL }, 3247 /* OAM_LM_COUNTERS_PARITY_CONTROLr */ 3248 { _SOC_PARITY_TYPE_COUNTER, NULL, 0, 3249 OAM_LM_COUNTERS_PAR_ERRf, 3250 OAM_LM_COUNTERS_PAR_ERRf, 3251 OAM_LM_COUNTERSm, "Ingress Pipeline Counter", 3252 OAM_LM_COUNTERS_PARITY_CONTROLr, PARITY_ENf, 3253 OAM_LM_COUNTERS_PARITY_STATUS_INTRr, NULL, 3254 OAM_LM_COUNTERS_PARITY_STATUS_NACKr, NULL }, 3255 /* IP_COUNTERS_PARITY_CONTROLr */ 3256 { _SOC_PARITY_TYPE_COUNTER, NULL, 0, 3257 IP_COUNTERS_PAR_ERRf, 3258 IP_COUNTERS_PAR_ERRf, 3259 INVALIDm, "Ingress Pipeline Counter", 3260 IP_COUNTERS_PARITY_CONTROLr, PARITY_ENf, 3261 IP_COUNTERS_PARITY_STATUS_INTRr, NULL, 3262 IP_COUNTERS_PARITY_STATUS_NACKr, NULL }, 3263 /* RDBGC_MEM_INST0_PARITY_CONTROLr */ 3264 { _SOC_PARITY_TYPE_COUNTER, NULL, 0, 3265 RDBGC_MEM_INST0_PAR_ERRf, 3266 RDBGC_MEM_INST0_PAR_ERRf, 3267 INVALIDm, "Ingress Pipeline Counter", 3268 RDBGC_MEM_INST0_PARITY_CONTROLr, PARITY_ENf, 3269 RDBGC_MEM_INST0_PARITY_STATUS_INTRr, NULL, 3270 RDBGC_MEM_INST0_PARITY_STATUS_NACKr, NULL }, 3271 /* RDBGC_MEM_INST1_PARITY_STATUS_INTRr */ 3272 { _SOC_PARITY_TYPE_COUNTER, NULL, 0, 3273 RDBGC_MEM_INST1_PAR_ERRf, 3274 RDBGC_MEM_INST1_PAR_ERRf, 3275 INVALIDm, "RX Debug Counter", 3276 RDBGC_MEM_INST1_PARITY_CONTROLr, PARITY_ENf, 3277 RDBGC_MEM_INST1_PARITY_STATUS_INTRr, NULL, 3278 RDBGC_MEM_INST1_PARITY_STATUS_NACKr, NULL }, 3279 /* RDBGC_MEM_INST2_PARITY_CONTROLr */ 3280 { _SOC_PARITY_TYPE_COUNTER, NULL, 0, 3281 RDBGC_MEM_INST2_PAR_ERRf, 3282 RDBGC_MEM_INST2_PAR_ERRf, 3283 INVALIDm, "RX Debug Counter", 3284 RDBGC_MEM_INST2_PARITY_CONTROLr, PARITY_ENf, 3285 RDBGC_MEM_INST2_PARITY_STATUS_INTRr, NULL, 3286 RDBGC_MEM_INST2_PARITY_STATUS_NACKr, NULL }, 3287 /* HG_COUNTERS_PARITY_CONTROLr */ 3288 { _SOC_PARITY_TYPE_COUNTER, NULL, 0, 3289 HG_COUNTERS_PAR_ERRf, 3290 HG_COUNTERS_PAR_ERRf, 3291 INVALIDm, "Ingress Pipeline HG Counter", 3292 HG_COUNTERS_PARITY_CONTROLr, PARITY_ENf, 3293 HG_COUNTERS_PARITY_STATUS_INTRr, NULL, 3294 HG_COUNTERS_PARITY_STATUS_NACKr, NULL }, 3295 /* NIV_ERROR_DROP_PARITY_CONTROLr */ 3296 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3297 NIV_ERROR_DROP_PAR_ERRf, 3298 NIV_ERROR_DROP_PAR_ERRf, 3299 INVALIDm, "ING_NIV_RX_FRAMES_ERROR_DROP", 3300 NIV_ERROR_DROP_PARITY_CONTROLr, PARITY_ENf, 3301 NIV_ERROR_DROP_PARITY_STATUS_INTRr, NULL, 3302 NIV_ERROR_DROP_PARITY_STATUS_NACKr, NULL }, 3303 /* NIV_FORWARDING_DROP_PARITY_CONTROLr */ 3304 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3305 NIV_FORWARDING_DROP_PAR_ERRf, 3306 NIV_FORWARDING_DROP_PAR_ERRf, 3307 INVALIDm, "ING_NIV_RX_FRAMES_FORWARDING_DROP", 3308 NIV_FORWARDING_DROP_PARITY_CONTROLr, PARITY_ENf, 3309 NIV_FORWARDING_DROP_PARITY_STATUS_INTRr, NULL, 3310 NIV_FORWARDING_DROP_PARITY_STATUS_NACKr, NULL }, 3311 /* NIV_VLAN_TAGGED_PARITY_CONTROLr */ 3312 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3313 NIV_VLAN_TAGGED_PAR_ERRf, 3314 NIV_VLAN_TAGGED_PAR_ERRf, 3315 INVALIDm, "ING_NIV_RX_FRAMES_VLAN_TAGGED", 3316 NIV_VLAN_TAGGED_PARITY_CONTROLr, PARITY_ENf, 3317 NIV_VLAN_TAGGED_PARITY_STATUS_INTRr, NULL, 3318 NIV_VLAN_TAGGED_PARITY_STATUS_NACKr, NULL }, 3319 /* TRILL_RX_PKTS_PARITY_CONTROLr */ 3320 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3321 TRILL_RX_PKTS_PAR_ERRf, 3322 TRILL_RX_PKTS_PAR_ERRf, 3323 INVALIDm, "ING_TRILL_RX_PKTS", 3324 TRILL_RX_PKTS_PARITY_CONTROLr, PARITY_ENf, 3325 TRILL_RX_PKTS_PARITY_STATUS_INTRr, NULL, 3326 TRILL_RX_PKTS_PARITY_STATUS_NACKr, NULL }, 3327 /* TRILL_RX_ACCESS_PORT_TRILL_PKTS_DISCARDED_PARITY_CONTROLr */ 3328 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3329 TRILL_RX_ACCESS_PORT_TRILL_PKTS_DISCARDED_PAR_ERRf, 3330 TRILL_RX_ACCESS_PORT_TRILL_PKTS_DISCARDED_PAR_ERRf, 3331 INVALIDm, "ING_TRILL_RX_ACCESS_PORT_TRILL_PKTS_DISCARDED", 3332 TRILL_RX_ACCESS_PORT_TRILL_PKTS_DISCARDED_PARITY_CONTROLr, PARITY_ENf, 3333 TRILL_RX_ACCESS_PORT_TRILL_PKTS_DISCARDED_PARITY_STATUS_INTRr, NULL, 3334 TRILL_RX_ACCESS_PORT_TRILL_PKTS_DISCARDED_PARITY_STATUS_NACKr, NULL }, 3335 /* TRILL_RX_NETWORK_PORT_NON_TRILL_PKTS_DISCARDED_PARITY_CONTROLr */ 3336 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3337 TRILL_RX_NETWORK_PORT_NON_TRILL_PKTS_DISCARDED_PAR_ERRf, 3338 TRILL_RX_NETWORK_PORT_NON_TRILL_PKTS_DISCARDED_PAR_ERRf, 3339 INVALIDm, "ING_TRILL_RX_NETWORK_PORT_NON_TRILL_PKTS_DISCARDED", 3340 TRILL_RX_NETWORK_PORT_NON_TRILL_PKTS_DISCARDED_PARITY_CONTROLr, PARITY_ENf, 3341 TRILL_RX_NETWORK_PORT_NON_TRILL_PKTS_DISCARDED_PARITY_STATUS_INTRr, NULL, 3342 TRILL_RX_NETWORK_PORT_NON_TRILL_PKTS_DISCARDED_PARITY_STATUS_NACKr, NULL }, 3343 /* CPB_PARITY_CONTROLr */ 3344 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3345 CPB_PAR_ERRf, 3346 CPB_PAR_ERRf, 3347 INVALIDm, "CPB", 3348 CPB_PARITY_CONTROLr, PARITY_ENf, 3349 CPB_PARITY_STATUS_INTRr, NULL, 3350 INVALIDr, NULL }, 3351 /* ING_QUEUE_MAP_PARITY_CONTROLr */ 3352 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3353 ING_QUEUE_MAP_PAR_ERRf, 3354 ING_QUEUE_MAP_PAR_ERRf, 3355 ING_QUEUE_MAPm, "ING_QUEUE_MAP", 3356 ING_QUEUE_MAP_PARITY_CONTROLr, PARITY_ENf, 3357 ING_QUEUE_MAP_PARITY_STATUS_INTRr, NULL, 3358 ING_QUEUE_MAP_PARITY_STATUS_NACKr, NULL }, 3359 /* ING_SVM_MACROFLOW_INDEX_TABLE_CONTROLr */ 3360 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3361 SVC_MACROFLOW_TABLE_PAR_ERRf, 3362 SVC_MACROFLOW_TABLE_PAR_ERRf, 3363 SVM_MACROFLOW_INDEX_TABLEm, "SVM MACROFLOW", 3364 ING_SVM_MACROFLOW_INDEX_TABLE_CONTROLr, PARITY_ENf, 3365 ING_SVM_MACROFLOW_INDEX_TABLE_PARITY_STATUS_INTRr, NULL, 3366 ING_SVM_MACROFLOW_INDEX_TABLE_PARITY_STATUS_NACKr, NULL }, 3367 /* ING_SVM_OFFSET_TABLE_CONTROLr */ 3368 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3369 SVC_OFFSET_TABLE_PAR_ERRf, 3370 SVC_OFFSET_TABLE_PAR_ERRf, 3371 SVM_OFFSET_TABLEm, "SVM OFFSET", 3372 ING_SVM_OFFSET_TABLE_CONTROLr, PARITY_ENf, 3373 ING_SVM_OFFSET_TABLE_PARITY_STATUS_INTRr, NULL, 3374 ING_SVM_OFFSET_TABLE_PARITY_STATUS_NACKr, NULL }, 3375 /* ING_SVM_OFFSET_TABLE_CONTROLr */ 3376 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3377 SVC_METER_TABLE_PAR_ERRf, 3378 SVC_METER_TABLE_PAR_ERRf, 3379 SVM_METER_TABLEm, "SVM METER", 3380 ING_SVM_METER_TABLE_CONTROLr, PARITY_ENf, 3381 ING_SVM_METER_TABLE_PARITY_STATUS_INTRr, NULL, 3382 ING_SVM_METER_TABLE_PARITY_STATUS_NACKr, NULL }, 3383 /* ING_SVM_OFFSET_TABLE_CONTROLr */ 3384 { _SOC_PARITY_TYPE_PARITY, NULL, 0, 3385 SVC_POLICY_TABLE_PAR_ERRf, 3386 SVC_POLICY_TABLE_PAR_ERRf, 3387 SVM_POLICY_TABLEm, "SVM POLICY", 3388 ING_SVM_POLICY_TABLE_CONTROLr, PARITY_ENf, 3389 ING_SVM_POLICY_TABLE_PARITY_STATUS_INTRr, NULL, 3390 ING_SVM_POLICY_TABLE_PARITY_STATUS_NACKr, NULL }, 3391 { _SOC_PARITY_TYPE_NONE } /* table terminator */ 3392 }; 3393 3394 STATIC const 3395 _soc_katana_parity_route_block_t _soc_katana_parity_route_blocks[] = { 3396 { 0x00000001, /* MMU_TO_CMIC_MEMFAIL_INTR */ 3397 SOC_BLK_MMU, MMU_INTR_MASKr, MMU_INTRr, 3398 NULL, 0}, 3399 { 0x00000002, /* EP1_TO_CMIC_PERR_INTR */ 3400 SOC_BLK_EPIPE, EGR_INTR0_ENABLEr, EGR_INTR0_STATUSr, 3401 _soc_katana_ep0_parity_info }, 3402 { 0x00000004, /* EP2_TO_CMIC_PERR_INTR */ 3403 SOC_BLK_EPIPE, EGR_INTR1_ENABLEr, EGR_INTR1_STATUSr, 3404 _soc_katana_ep1_parity_info, 0}, 3405 { 0x00000008, /* IP0_TO_CMIC_PERR_INTR */ 3406 SOC_BLK_IPIPE, IP0_INTR_ENABLEr, IP0_INTR_STATUSr, 3407 _soc_katana_ip0_parity_info, 0}, 3408 { 0x00000010, /* IP1_TO_CMIC_PERR_INTR */ 3409 SOC_BLK_IPIPE, IP1_INTR_ENABLEr, IP1_INTR_STATUSr, 3410 _soc_katana_ip1_parity_info, 0}, 3411 { 0x00000010, /* IP1_TO_CMIC_PERR_INTR */ 3412 SOC_BLK_IPIPE, IP1_INTR_ENABLE_1r, IP1_INTR_STATUS_1r, 3413 _soc_katana_ip1_1_parity_info, 0}, 3414 { 0x00000020, /* IP2_TO_CMIC_PERR_INTR */ 3415 SOC_BLK_IPIPE, IP2_INTR_ENABLEr, IP2_INTR_STATUSr, 3416 _soc_katana_ip2_parity_info, 0}, 3417 { 0x00000020, /* IP2_TO_CMIC_PERR_INTR */ 3418 SOC_BLK_IPIPE, IP2_INTR_ENABLE_1r, IP2_INTR_STATUS_1r, 3419 _soc_katana_ip2_1_parity_info, 0}, 3420 { 0x00000020, /* IP2_TO_CMIC_PERR_INTR */ 3421 SOC_BLK_IPIPE, IP2_INTR_ENABLE_2r, IP2_INTR_STATUS_2r, 3422 _soc_katana_ip2_2_parity_info, 0}, 3423 /* 0x00000040 PCIE_REPLAY_PERR */ 3424 #ifdef _KATANA_DEBUG 3425 /* MXQ0_TO_CMIC_PERR_INTR */ 3426 { 0x00000080, 3427 SOC_BLK_MXQPORT, XPORT_INTR_ENABLEr, XPORT_INTR_STATUSr, 3428 _soc_katana_xport_parity_info, 0}, 3429 /* MXQ1_TO_CMIC_PERR_INTR */ 3430 { 0x00000100, 3431 SOC_BLK_MXQPORT, XPORT_INTR_ENABLEr, XPORT_INTR_STATUSr, 3432 _soc_katana_xport_parity_info, 1}, 3433 /* MXQ2_TO_CMIC_PERR_INTR */ 3434 { 0x00000200, 3435 SOC_BLK_MXQPORT, XPORT_INTR_ENABLEr, XPORT_INTR_STATUSr, 3436 _soc_katana_xport_parity_info, 2}, 3437 /* MXQ3_TO_CMIC_PERR_INTR */ 3438 { 0x00000400, 3439 SOC_BLK_MXQPORT, XPORT_INTR_ENABLEr, XPORT_INTR_STATUSr, 3440 _soc_katana_xport_parity_info, 3}, 3441 /* 0x00000800 PULL_DOWN */ 3442 #endif 3443 { 0 } /* table terminator */ 3444 }; 3445 3446 STATIC _soc_katana_counter_info_t _soc_katana_counter_info[] = { 3447 { _SOC_COUNTER_TYPE_DROP_ENQ, 0x0, 0 }, 3448 { _SOC_COUNTER_TYPE_ACCEPT_ENQ, 0x0, 1 }, 3449 /* green pkt drops, index = ACCEPT=1'b0, COLOR=2'b00 */ 3450 { _SOC_COUNTER_TYPE_DROP_ENQ_GREEN, 0x0, 2 }, 3451 /* yellow pkt drops, index = ACCEPT=1'b0, COLOR=2'b11 */ 3452 { _SOC_COUNTER_TYPE_DROP_ENQ_YELLOW, 0x3, 3 }, 3453 /* red pkt drops, index = ACCEPT=1'b0, COLOR=2'b01 */ 3454 { _SOC_COUNTER_TYPE_DROP_ENQ_RED, 0x1, 4 }, 3455 /* green accepted pkts, index = ACCEPT=1'b1, COLOR=2'b00 */ 3456 { _SOC_COUNTER_TYPE_ACCEPT_ENQ_GREEN, 0x4, 5 }, 3457 /* yellow accepted pkts, index = ACCEPT=1'b1, COLOR=2'b11 */ 3458 { _SOC_COUNTER_TYPE_ACCEPT_ENQ_YELLOW, 0x7, 6 }, 3459 /* red accepted pkts, index = ACCEPT=1'b1, COLOR=2'b01 */ 3460 { _SOC_COUNTER_TYPE_ACCEPT_ENQ_RED, 0x5, 7 }, 3461 { _SOC_COUNTER_TYPE_ACCEPT_DEQ, 0, 8 } 3462 }; 3463 3464 /* KT OAM */ 3465 STATIC 3466 soc_field_t _soc_kt_oam_interrupt_fields[] = { 3467 SOME_RMEP_CCM_DEFECTf, 3468 SOME_RDI_DEFECTf, 3469 ERROR_CCM_DEFECTf, 3470 XCON_CCM_DEFECTf, 3471 ANY_RMEP_TLV_INTERFACE_UPf, 3472 ANY_RMEP_TLV_INTERFACE_DOWNf, 3473 ANY_RMEP_TLV_PORT_UPf, 3474 ANY_RMEP_TLV_PORT_DOWNf, 3475 INVALIDf 3476 }; 3477 3478 static soc_ser_functions_t _kt_ser_functions; 3479 static soc_oam_event_functions_t _kt_oam_event_functions; 3480 3481 3482 #define _SOC_KT_SER_REG 1 3483 #define _SOC_KT_SER_MEM 0 3484 3485 typedef union _kt_ser_nack_reg_mem_u { 3486 soc_reg_t reg; 3487 soc_mem_t mem; 3488 } _kt_ser_nack_reg_mem_t; 3489 3490 static int _stat_error_fixed[SOC_MAX_NUM_DEVICES]; 3491 3492 STATIC int 3493 soc_kt_oam_interrupt_process(int unit); 3494 3495 STATIC int 3496 _soc_katana_parity_enable_info(int unit, uint8 id, 3497 soc_reg_t group_reg, 3498 uint32 *group_rval, 3499 const _soc_katana_parity_info_t *info_list, 3500 int enable); 3501 3502 extern sal_mutex_t cosq_sync_lock[SOC_MAX_NUM_DEVICES]; 3503 #define KT_COSQ_LOCK(unit) do { \ 3504 if (cosq_sync_lock[unit]) { \ 3505 sal_mutex_take(cosq_sync_lock[unit], \ 3506 sal_mutex_FOREVER); \ 3507 } \ 3508 } while (0) 3509 #define KT_COSQ_UNLOCK(unit) do { \ 3510 if (cosq_sync_lock[unit]) { \ 3511 sal_mutex_give(cosq_sync_lock[unit]); \ 3512 } \ 3513 } while (0) 3514 void 3515 soc_kt_oam_handler_register(int unit, soc_kt_oam_handler_t handler) 3516 { 3517 int rv, fidx = 0; 3518 uint32 rval; 3519 3520 en_oam_handler[unit] = handler; 3521 3522 rv = READ_IP1_INTR_ENABLE_1r(unit, &rval); 3523 if (rv) { 3524 LOG_ERROR(BSL_LS_SOC_COMMON, 3525 (BSL_META_U(unit, 3526 "unit %d: Error reading %s reg !!\n"), 3527 unit, SOC_REG_NAME(unit, IP1_INTR_ENABLE_1r))); 3528 } 3529 while (_soc_kt_oam_interrupt_fields[fidx] != INVALIDf) { 3530 soc_reg_field_set(unit, IP1_INTR_ENABLE_1r, &rval, 3531 _soc_kt_oam_interrupt_fields[fidx], 1); 3532 fidx++; 3533 } 3534 rv = WRITE_IP1_INTR_ENABLE_1r(unit, rval); 3535 if (rv) { 3536 LOG_ERROR(BSL_LS_SOC_COMMON, 3537 (BSL_META_U(unit, 3538 "unit %d: Error writing %s reg !!\n"), 3539 unit, SOC_REG_NAME(unit, IP1_INTR_ENABLE_1r))); 3540 } 3541 /* Write CMIC enable register for oam event*/ 3542 (void)soc_cmicm_intr2_enable(unit, KT_OAM_CMIC_INTR_MASK); 3543 } 3544 3545 STATIC 3546 int _soc_katana_process_sb_type_1_ci_mmu_parity_enable(int unit, 3547 soc_block_t block, 3548 soc_reg_t en_reg, 3549 int enable, 3550 _soc_katana_mmu_sub_block_type_1_info_t * sub_block_info) 3551 { 3552 uint32 en_rval; 3553 uint32 intr_bit; 3554 int sb_index = 0; 3555 soc_port_t port = 0; 3556 _soc_katana_mmu_sub_block_type_1_info_t *sub_block; 3557 3558 port = SOC_BLOCK_PORT(unit, block); 3559 SOC_IF_ERROR_RETURN(READ_CI_ERROR_MASKr(unit, port, &en_rval)); 3560 3561 for (sb_index = 0; ; sb_index++) { 3562 sub_block = &sub_block_info[sb_index]; 3563 intr_bit = sub_block->intr_bit; 3564 if(intr_bit == 0) { 3565 /* End of table */ 3566 break; 3567 } 3568 soc_reg_field_set(unit, en_reg, &en_rval, sub_block->sub_block_en_field, 3569 enable ? 0 : 1); 3570 SOC_IF_ERROR_RETURN(WRITE_CI_ERROR_MASKr(unit, port, en_rval)); 3571 } 3572 return SOC_E_NONE; 3573 } 3574 3575 STATIC 3576 int _soc_katana_process_sb_type_1_mmu_parity_enable(int unit, 3577 soc_reg_t en_reg, 3578 int enable, 3579 _soc_katana_mmu_sub_block_type_1_info_t * sub_block_info) 3580 { 3581 uint32 addr, en_rval; 3582 uint32 intr_bit; 3583 int sb_index = 0; 3584 _soc_katana_mmu_sub_block_type_1_info_t *sub_block; 3585 3586 addr = soc_reg_addr(unit, en_reg, REG_PORT_ANY, 0); 3587 SOC_IF_ERROR_RETURN(soc_reg32_read(unit, addr, &en_rval)); 3588 3589 for (sb_index = 0; ; sb_index++) { 3590 sub_block = &sub_block_info[sb_index]; 3591 intr_bit = sub_block->intr_bit; 3592 if(intr_bit == 0) { 3593 /* End of table */ 3594 break; 3595 } 3596 if (sub_block->sub_block_en_field == FLUSH_COMPLETE_DISINTf) { 3597 continue; 3598 } 3599 soc_reg_field_set(unit, en_reg, &en_rval, sub_block->sub_block_en_field, 3600 enable ? 0 : 1); 3601 SOC_IF_ERROR_RETURN(soc_reg32_write(unit, addr, en_rval)); 3602 } 3603 return SOC_E_NONE; 3604 } 3605 3606 STATIC 3607 int _soc_katana_process_sb_type_2_mmu_parity_enable(int unit, 3608 soc_reg_t en_reg, 3609 int enable, 3610 _soc_katana_mmu_sub_block_type_2_info_t * sub_block_info) 3611 { 3612 uint32 addr, en_rval; 3613 uint32 intr_bit; 3614 int sb_index = 0; 3615 _soc_katana_mmu_sub_block_type_2_info_t *sub_block; 3616 3617 addr = soc_reg_addr(unit, en_reg, REG_PORT_ANY, 0); 3618 SOC_IF_ERROR_RETURN(soc_reg32_read(unit, addr, &en_rval)); 3619 3620 for (sb_index = 0; ; sb_index++) { 3621 sub_block = &sub_block_info[sb_index]; 3622 intr_bit = sub_block->intr_bit; 3623 if(intr_bit == 0) { 3624 /* End of table */ 3625 break; 3626 } 3627 if (SOC_REG_FIELD_VALID(unit, en_reg, sub_block->sub_block_en_field)) { 3628 soc_reg_field_set(unit, en_reg, &en_rval, 3629 sub_block->sub_block_en_field, enable ? 0 : 1); 3630 SOC_IF_ERROR_RETURN(soc_reg32_write(unit, addr, en_rval)); 3631 } 3632 } 3633 return SOC_E_NONE; 3634 } 3635 3636 STATIC 3637 int _soc_katana_process_sb_mmu_lvl1_parity_enable(int unit, 3638 soc_reg_t en_reg, 3639 int enable, 3640 _soc_katana_mmu_sub_block_type_3_info_t * sub_block_info) 3641 { 3642 uint32 addr = 0; 3643 uint32 en_rval; 3644 uint32 intr_bit; 3645 int sb_index = 0; 3646 _soc_katana_mmu_sub_block_type_3_info_t *sub_block; 3647 _soc_katana_mmu_lvl2_subblock_type_t lvl2_sub_block; 3648 3649 if (en_reg != 0) { 3650 addr = soc_reg_addr(unit, en_reg, REG_PORT_ANY, 0); 3651 SOC_IF_ERROR_RETURN(soc_reg32_read(unit, addr, &en_rval)); 3652 } 3653 3654 for (sb_index = 0; ; sb_index++) { 3655 sub_block = &sub_block_info[sb_index]; 3656 intr_bit = sub_block->intr_bit; 3657 if(intr_bit == 0) { 3658 /* End of table */ 3659 return SOC_E_NONE; 3660 } 3661 if ((en_reg != 0) && (sub_block->sub_block_en_field != 0)) { 3662 soc_reg_field_set(unit, en_reg, &en_rval, 3663 sub_block->sub_block_en_field, enable ? 0 : 1); 3664 SOC_IF_ERROR_RETURN(soc_reg32_write(unit, addr, en_rval)); 3665 } 3666 lvl2_sub_block = sub_block->lvl2_sub_block; 3667 switch (lvl2_sub_block) { 3668 case _SOC_KT_MMU_LVL2_SUBBLOCK_EMC_ERROR_2: 3669 _soc_katana_process_sb_type_1_mmu_parity_enable(unit, 3670 EMC_ERROR_MASK_2r, 3671 enable, 3672 sub_block->info); 3673 break; 3674 3675 case _SOC_KT_MMU_LVL2_SUBBLOCK_EMC_ERROR_1: 3676 _soc_katana_process_sb_type_1_mmu_parity_enable(unit, 3677 EMC_ERROR_MASK_1r, 3678 enable, 3679 sub_block->info); 3680 break; 3681 case _SOC_KT_MMU_LVL2_SUBBLOCK_EMC_ERROR_0: 3682 _soc_katana_process_sb_type_1_mmu_parity_enable(unit, 3683 EMC_ERROR_MASK_0r, 3684 enable, 3685 sub_block->info); 3686 break; 3687 3688 case _SOC_KT_MMU_LVL2_SUBBLOCK_DEQ_ERROR_3: 3689 _soc_katana_process_sb_type_1_mmu_parity_enable(unit, 3690 DEQ_ERROR_MASK_3r, 3691 enable, 3692 sub_block->info); 3693 break; 3694 3695 case _SOC_KT_MMU_LVL2_SUBBLOCK_DEQ_ERROR_2: 3696 _soc_katana_process_sb_type_1_mmu_parity_enable(unit, 3697 DEQ_ERROR_MASK_2r, 3698 enable, 3699 sub_block->info); 3700 break; 3701 3702 case _SOC_KT_MMU_LVL2_SUBBLOCK_DEQ_ERROR_1: 3703 _soc_katana_process_sb_type_1_mmu_parity_enable(unit, 3704 DEQ_ERROR_MASK_1r, 3705 enable, 3706 sub_block->info); 3707 break; 3708 3709 case _SOC_KT_MMU_LVL2_SUBBLOCK_DEQ_ERROR_0: 3710 _soc_katana_process_sb_type_1_mmu_parity_enable(unit, 3711 DEQ_ERROR_MASK_0r, 3712 enable, 3713 sub_block->info); 3714 break; 3715 3716 case _SOC_KT_MMU_LVL2_SUBBLOCK_QSTRUCT_QENTRY_U: 3717 _soc_katana_process_sb_type_1_mmu_parity_enable(unit, 3718 QSTRUCT_QENTRY_UPPER_ERROR_MASKr, 3719 enable, 3720 sub_block->info); 3721 break; 3722 3723 case _SOC_KT_MMU_LVL2_SUBBLOCK_QSTRUCT_QENTRY_L: 3724 _soc_katana_process_sb_type_1_mmu_parity_enable(unit, 3725 QSTRUCT_QENTRY_LOWER_ERROR_MASKr, 3726 enable, 3727 sub_block->info); 3728 break; 3729 3730 case _SOC_KT_MMU_LVL2_SUBBLOCK_QSTRUCT_QBLOCK: 3731 _soc_katana_process_sb_type_1_mmu_parity_enable(unit, 3732 QSTRUCT_QBLOCK_NEXT_ERROR_MASKr, 3733 enable, 3734 sub_block->info); 3735 break; 3736 3737 case _SOC_KT_MMU_LVL2_SUBBLOCK_QSTRUCT_FAP: 3738 _soc_katana_process_sb_type_1_mmu_parity_enable(unit, 3739 QSTRUCT_FAP_MEM_ERROR_MASKr, 3740 enable, 3741 sub_block->info); 3742 break; 3743 3744 default: 3745 break; 3746 } 3747 } 3748 return SOC_E_NONE; 3749 } 3750 3751 STATIC int 3752 _soc_katana_parity_enable_mmu(int unit, soc_reg_t mmu_en_reg, int enable) 3753 { 3754 /* Go through each sub-block and enable the interrupt */ 3755 3756 uint32 addr, en_rval; 3757 int sub_block_index; 3758 uint32 mmu_bit; 3759 const _soc_katana_mmu_sub_block_type_1_t *sub_block; 3760 const _soc_katana_mmu_sub_block_type_2_t *sub_block_type2; 3761 const _soc_katana_mmu_sub_block_type_3_t *lvl1_sub_block; 3762 _soc_katana_mmu_subblock_type_t sub_block_type; 3763 3764 for (sub_block_index = 0; ; sub_block_index++) { 3765 sub_block = &_soc_katana_mmu_sub_blocks_type_1[sub_block_index]; 3766 sub_block_type = sub_block->mmu_sub_block; 3767 mmu_bit = sub_block->mmu_bit; 3768 if(mmu_bit == 0) { 3769 /* End of table */ 3770 break; 3771 } 3772 addr = soc_reg_addr(unit, mmu_en_reg, REG_PORT_ANY, 0); 3773 SOC_IF_ERROR_RETURN(soc_reg32_read(unit, addr, &en_rval)); 3774 soc_reg_field_set(unit, mmu_en_reg, &en_rval, 3775 sub_block->sub_block_en_reg, enable ? 0 : 1); 3776 SOC_IF_ERROR_RETURN(soc_reg32_write(unit, addr, en_rval)); 3777 3778 switch (sub_block_type) { 3779 3780 case _SOC_KT_MMU_SUBBLOCK_MEM1: 3781 _soc_katana_process_sb_type_1_mmu_parity_enable(unit, 3782 CLINK_ERROR_MASKr, 3783 enable, 3784 sub_block->info); 3785 break; 3786 3787 case _SOC_KT_MMU_SUBBLOCK_E2EFC: 3788 _soc_katana_process_sb_type_1_mmu_parity_enable(unit, 3789 MMU_E2EFC_ERROR_0_MASKr, 3790 enable, 3791 sub_block->info); 3792 break; 3793 3794 case _SOC_KT_MMU_SUBBLOCK_THDI: 3795 _soc_katana_process_sb_type_1_mmu_parity_enable(unit, 3796 MMU_THDI_INTR_MASKr, 3797 enable, 3798 sub_block->info); 3799 break; 3800 3801 3802 case _SOC_KT_MMU_SUBBLOCK_CTR: 3803 _soc_katana_process_sb_type_1_mmu_parity_enable(unit, 3804 CTR_ERROR_MASKr, 3805 enable, 3806 sub_block->info); 3807 break; 3808 3809 case _SOC_KT_MMU_SUBBLOCK_CCP: 3810 _soc_katana_process_sb_type_1_mmu_parity_enable(unit, 3811 CCP_ERROR_MASKr, 3812 enable, 3813 sub_block->info); 3814 break; 3815 3816 case _SOC_KT_MMU_SUBBLOCK_TOQ: 3817 _soc_katana_process_sb_type_1_mmu_parity_enable(unit, 3818 TOQ_ERROR_MASKr, 3819 enable, 3820 sub_block->info); 3821 break; 3822 3823 3824 case _SOC_KT_MMU_SUBBLOCK_CFAPI: 3825 _soc_katana_process_sb_type_1_mmu_parity_enable(unit, 3826 CFAPI_ERROR_MASKr, 3827 enable, 3828 sub_block->info); 3829 break; 3830 3831 case _SOC_KT_MMU_SUBBLOCK_CFAPE: 3832 _soc_katana_process_sb_type_1_mmu_parity_enable(unit, 3833 CFAPE_ERROR_MASKr, 3834 enable, 3835 sub_block->info); 3836 break; 3837 3838 case _SOC_KT_MMU_SUBBLOCK_ITE: 3839 _soc_katana_process_sb_type_1_mmu_parity_enable(unit, 3840 MMU_ITE_ERROR_0_MASKr, 3841 enable, 3842 sub_block->info); 3843 break; 3844 3845 case _SOC_KT_MMU_SUBBLOCK_ITE_CFG: 3846 _soc_katana_process_sb_type_1_mmu_parity_enable(unit, 3847 MMU_ITE_CFG_ECC_ERROR_0_MASKr, 3848 enable, 3849 sub_block->info); 3850 break; 3851 3852 case _SOC_KT_MMU_SUBBLOCK_ENQ_CFG: 3853 _soc_katana_process_sb_type_1_mmu_parity_enable(unit, 3854 MMU_ENQ_CFG_ECC_ERROR_0_MASKr, 3855 enable, 3856 sub_block->info); 3857 break; 3858 3859 case _SOC_KT_MMU_SUBBLOCK_ENQ: 3860 _soc_katana_process_sb_type_1_mmu_parity_enable(unit, 3861 MMU_ENQ_ERROR_0_MASKr, 3862 enable, 3863 sub_block->info); 3864 break; 3865 3866 case _SOC_KT_MMU_SUBBLOCK_ENQ_FAP: 3867 _soc_katana_process_sb_type_1_mmu_parity_enable(unit, 3868 MMU_ENQ_FAP_ECC_ERROR_0_MASKr, 3869 enable, 3870 sub_block->info); 3871 break; 3872 3873 case _SOC_KT_MMU_SUBBLOCK_THDO_STATUS1: 3874 _soc_katana_process_sb_type_1_mmu_parity_enable(unit, 3875 THDO_PARITY_ERROR_MASK1r, 3876 enable, 3877 sub_block->info); 3878 break; 3879 3880 case _SOC_KT_MMU_SUBBLOCK_THDO_STATUS2: 3881 _soc_katana_process_sb_type_1_mmu_parity_enable(unit, 3882 THDO_PARITY_ERROR_MASK2r, 3883 enable, 3884 sub_block->info); 3885 break; 3886 3887 3888 case _SOC_KT_MMU_SUBBLOCK_AGING_INT: 3889 _soc_katana_process_sb_type_1_mmu_parity_enable(unit, 3890 AGING_ERROR_MASK_INTr, 3891 enable, 3892 sub_block->info); 3893 break; 3894 3895 case _SOC_KT_MMU_SUBBLOCK_AGING_EXT: 3896 _soc_katana_process_sb_type_1_mmu_parity_enable(unit, 3897 AGING_ERROR_MASK_EXTr, 3898 enable, 3899 sub_block->info); 3900 break; 3901 3902 case _SOC_KT_MMU_SUBBLOCK_WRED: 3903 _soc_katana_process_sb_type_1_mmu_parity_enable(unit, 3904 WRED_PARITY_ERROR_MASKr, 3905 enable, 3906 sub_block->info); 3907 break; 3908 3909 case _SOC_KT_MMU_SUBBLOCK_INTFI: 3910 _soc_katana_process_sb_type_1_mmu_parity_enable(unit, 3911 INTFI_ERROR_MASKr, 3912 enable, 3913 sub_block->info); 3914 break; 3915 3916 /* Access to CI_ERROR_MASK register is resulting in S-Chan timeout on 3917 some KATANA devices which do not have ddr3 memory */ 3918 /* for the 'i'th memory bank mask it if the bank is not present 3919 setting the bit of MMU_INTR_MASK register masks interrupts coming 3920 for CI'i' bank. 3921 We hence do that when all parity is being enabled through this 3922 function and that bank does not exist */ 3923 case _SOC_KT_MMU_SUBBLOCK_CI2: 3924 if (soc_feature(unit, soc_feature_ddr3)) { 3925 if ((SOC_DDR3_NUM_MEMORIES(unit) >= 3)) { 3926 _soc_katana_process_sb_type_1_ci_mmu_parity_enable(unit, 3927 CI2_BLOCK(unit), 3928 CI_ERROR_MASKr, 3929 enable, 3930 sub_block->info); 3931 } else if (enable) { 3932 soc_reg_field_set(unit, mmu_en_reg, &en_rval, 3933 sub_block->sub_block_en_reg, 1); 3934 SOC_IF_ERROR_RETURN(soc_reg32_write(unit, addr, en_rval)); 3935 } 3936 } 3937 break; 3938 case _SOC_KT_MMU_SUBBLOCK_CI1: 3939 if (soc_feature(unit, soc_feature_ddr3)) { 3940 if ((SOC_DDR3_NUM_MEMORIES(unit) >= 2)) { 3941 _soc_katana_process_sb_type_1_ci_mmu_parity_enable(unit, 3942 CI1_BLOCK(unit), 3943 CI_ERROR_MASKr, 3944 enable, 3945 sub_block->info); 3946 } else if (enable) { 3947 soc_reg_field_set(unit, mmu_en_reg, &en_rval, 3948 sub_block->sub_block_en_reg, 1); 3949 SOC_IF_ERROR_RETURN(soc_reg32_write(unit, addr, en_rval)); 3950 } 3951 } 3952 break; 3953 case _SOC_KT_MMU_SUBBLOCK_CI0: 3954 if (soc_feature(unit, soc_feature_ddr3)) { 3955 if ((SOC_DDR3_NUM_MEMORIES(unit) >= 1)) { 3956 _soc_katana_process_sb_type_1_ci_mmu_parity_enable(unit, 3957 CI0_BLOCK(unit), 3958 CI_ERROR_MASKr, 3959 enable, 3960 sub_block->info); 3961 } else if (enable) { 3962 soc_reg_field_set(unit, mmu_en_reg, &en_rval, 3963 sub_block->sub_block_en_reg, 1); 3964 SOC_IF_ERROR_RETURN(soc_reg32_write(unit, addr, en_rval)); 3965 } 3966 } 3967 break; 3968 case _SOC_KT_MMU_SUBBLOCK_LLS: 3969 _soc_katana_process_sb_type_1_mmu_parity_enable(unit, 3970 LLS_ERROR_MASKr, 3971 enable, 3972 sub_block->info); 3973 break; 3974 case _SOC_KT_MMU_SUBBLOCK_LLS_PORT: 3975 _soc_katana_process_sb_type_1_mmu_parity_enable(unit, 3976 LLS_PORT_ECC_ERROR_MASKr, 3977 enable, 3978 sub_block->info); 3979 break; 3980 case _SOC_KT_MMU_SUBBLOCK_LLS_L0_ECC: 3981 _soc_katana_process_sb_type_1_mmu_parity_enable(unit, 3982 LLS_L0_ECC_ERROR1_MASKr, 3983 enable, 3984 sub_block->info); 3985 break; 3986 case _SOC_KT_MMU_SUBBLOCK_LLS_UPD2: 3987 _soc_katana_process_sb_type_1_mmu_parity_enable(unit, 3988 LLS_ERROR_UPD2_MASKr, 3989 enable, 3990 sub_block->info); 3991 break; 3992 case _SOC_KT_MMU_SUBBLOCK_LLS_L1_ECC: 3993 _soc_katana_process_sb_type_1_mmu_parity_enable(unit, 3994 LLS_L1_ECC_ERROR1_MASKr, 3995 enable, 3996 sub_block->info); 3997 break; 3998 case _SOC_KT_MMU_SUBBLOCK_LLS_L2_ECC: 3999 _soc_katana_process_sb_type_1_mmu_parity_enable(unit, 4000 LLS_L2_ECC_ERROR1_MASKr, 4001 enable, 4002 sub_block->info); 4003 break; 4004 4005 case _SOC_KT_MMU_SUBBLOCK_LLS_MISC_ECC: 4006 _soc_katana_process_sb_type_1_mmu_parity_enable(unit, 4007 LLS_MISC_ECC_ERROR1_MASKr, 4008 enable, 4009 sub_block->info); 4010 break; 4011 #ifdef _KATANA_DEBUG 4012 /* RQE Ser gives MMU parity error while accessing IPMC group 4013 tables. Hence, disabling parity for this */ 4014 case _SOC_KT_MMU_SUBBLOCK_RQE_SER: 4015 _soc_katana_process_sb_type_1_mmu_parity_enable(unit, 4016 RQE_SER_MASKr, 4017 enable, 4018 sub_block->info); 4019 break; 4020 #endif /* _KATANA_DEBUG */ 4021 4022 default: 4023 break; 4024 4025 } 4026 } 4027 for (sub_block_index = 0; ; sub_block_index++) { 4028 sub_block_type2 = &_soc_katana_mmu_sub_blocks_type_2[sub_block_index]; 4029 mmu_bit = sub_block_type2->mmu_bit; 4030 sub_block_type = sub_block_type2->mmu_sub_block; 4031 if(mmu_bit == 0) { 4032 /* End of table */ 4033 break; 4034 } 4035 switch (sub_block_type) { 4036 case _SOC_KT_MMU_SUBBLOCK_RQE_EXTQ: 4037 _soc_katana_process_sb_type_2_mmu_parity_enable(unit, 4038 RQE_EXTQ_REPLICATION_LIMITr, 4039 enable, 4040 sub_block_type2->info); 4041 break; 4042 case _SOC_KT_MMU_SUBBLOCK_INTFI_ECC: 4043 _soc_katana_process_sb_type_2_mmu_parity_enable(unit, 4044 INTFI_ERROR_MASKr, 4045 enable, 4046 sub_block_type2->info); 4047 break; 4048 4049 default: 4050 break; 4051 4052 } 4053 } 4054 4055 for (sub_block_index = 0; ; sub_block_index++) { 4056 lvl1_sub_block = &_soc_katana_mmu_sub_blocks_type_3[sub_block_index]; 4057 mmu_bit = lvl1_sub_block->mmu_bit; 4058 sub_block_type = lvl1_sub_block->mmu_sub_block; 4059 if(mmu_bit == 0) { 4060 /* End of table */ 4061 break; 4062 } 4063 4064 addr = soc_reg_addr(unit, mmu_en_reg, REG_PORT_ANY, 0); 4065 SOC_IF_ERROR_RETURN(soc_reg32_read(unit, addr, &en_rval)); 4066 soc_reg_field_set(unit, mmu_en_reg, &en_rval, 4067 lvl1_sub_block->sub_block_en_reg, enable ? 0 : 1); 4068 SOC_IF_ERROR_RETURN(soc_reg32_write(unit, addr, en_rval)); 4069 4070 switch (sub_block_type) { 4071 /* Access to EMC_ERROR_X_MASK register is resulting is S-Chan timeout on 4072 some KATANA devices which do not have ddr3 memory */ 4073 case _SOC_KT_MMU_SUBBLOCK_EMC: 4074 if (soc_feature(unit, soc_feature_ddr3)) { 4075 _soc_katana_process_sb_mmu_lvl1_parity_enable(unit, 4076 0, 4077 enable, 4078 lvl1_sub_block->info); 4079 } 4080 break; 4081 case _SOC_KT_MMU_SUBBLOCK_DEQ: 4082 _soc_katana_process_sb_mmu_lvl1_parity_enable(unit, 4083 0, 4084 enable, 4085 lvl1_sub_block->info); 4086 break; 4087 case _SOC_KT_MMU_SUBBLOCK_QSTRUCT: 4088 _soc_katana_process_sb_mmu_lvl1_parity_enable(unit, 4089 QSTRUCT_INTERRUPT_MASKr, 4090 enable, 4091 lvl1_sub_block->info); 4092 break; 4093 4094 default: 4095 break; 4096 4097 } 4098 } 4099 return SOC_E_NONE; 4100 } 4101 4102 STATIC int 4103 _soc_katana_parity_enable_mxqport(int unit, uint8 id, 4104 const _soc_katana_parity_info_t *info, 4105 int enable) 4106 { 4107 soc_reg_t mxqport_reg; 4108 uint32 addr, mxqport_rval; 4109 int blk, port; 4110 4111 port = -1; 4112 SOC_BLOCK_ITER(unit, blk, SOC_BLK_MXQPORT) { 4113 if (SOC_BLOCK_INFO(unit, blk).number == id) { 4114 port = SOC_BLOCK_PORT(unit, blk); 4115 break; 4116 } 4117 } 4118 if (port < 0) { 4119 return SOC_E_NONE; 4120 } 4121 4122 mxqport_reg = info->enable_reg; 4123 addr = soc_reg_addr(unit, mxqport_reg, port, 0); 4124 SOC_IF_ERROR_RETURN(soc_reg32_read(unit, addr, &mxqport_rval)); 4125 4126 SOC_IF_ERROR_RETURN 4127 (_soc_katana_parity_enable_info(unit, id, mxqport_reg, &mxqport_rval, 4128 info->info, enable)); 4129 4130 addr = soc_reg_addr(unit, mxqport_reg, port, 0); 4131 SOC_IF_ERROR_RETURN(soc_reg32_write(unit, addr, mxqport_rval)); 4132 4133 return SOC_E_NONE; 4134 } 4135 4136 STATIC int 4137 _soc_katana_parity_enable_info(int unit, uint8 id, 4138 soc_reg_t group_reg, 4139 uint32 *group_rval, 4140 const _soc_katana_parity_info_t *info_list, 4141 int enable) 4142 { 4143 const _soc_katana_parity_info_t *info; 4144 int info_index; 4145 soc_reg_t reg; 4146 uint32 addr, rval; 4147 4148 /* Loop through each info entry in the list */ 4149 for (info_index = 0; ; info_index++) { 4150 info = &info_list[info_index]; 4151 if (info->type == _SOC_PARITY_TYPE_NONE) { 4152 /* End of table */ 4153 break; 4154 } 4155 4156 /* Enable the info entry in the group register */ 4157 soc_reg_field_set(unit, group_reg, group_rval, 4158 info->group_reg_enable_field, enable ? 1 : 0); 4159 4160 /* Handle different parity error reporting style */ 4161 switch (info->type) { 4162 case _SOC_PARITY_TYPE_PARITY: 4163 case _SOC_PARITY_TYPE_ECC: 4164 case _SOC_PARITY_TYPE_HASH: 4165 case _SOC_PARITY_TYPE_EDATABUF: 4166 case _SOC_PARITY_TYPE_COUNTER: 4167 reg = info->enable_reg; 4168 if (!SOC_REG_IS_VALID(unit, reg)) { 4169 continue; 4170 } 4171 addr = soc_reg_addr(unit, reg, REG_PORT_ANY, 0); 4172 SOC_IF_ERROR_RETURN(soc_reg32_read(unit, addr, &rval)); 4173 soc_reg_field_set(unit, reg, &rval, info->enable_field, 4174 enable ? 1 : 0); 4175 SOC_IF_ERROR_RETURN(soc_reg32_write(unit, addr, rval)); 4176 break; 4177 case _SOC_PARITY_TYPE_MXQPORT: 4178 /* One more level of report tree structure */ 4179 SOC_IF_ERROR_RETURN 4180 (_soc_katana_parity_enable_mxqport(unit, id, info, enable)); 4181 break; 4182 case _SOC_PARITY_TYPE_GENERIC: 4183 default: 4184 break; 4185 } /* Handle different parity error reporting style */ 4186 } /* Loop through each info entry in the route block */ 4187 4188 return SOC_E_NONE; 4189 } 4190 4191 STATIC int 4192 _soc_katana_parity_enable_all(int unit, int enable) 4193 { 4194 const _soc_katana_parity_route_block_t *route_block; 4195 int route_block_index; 4196 soc_reg_t route_block_en_reg; 4197 uint32 cmic_rval, route_block_rval; 4198 uint32 addr, cmic_bit; 4199 uint32 rval; 4200 4201 cmic_rval = 0; 4202 /* Loop through each place-and-route block entry */ 4203 for (route_block_index = 0; ; route_block_index++) { 4204 route_block = &_soc_katana_parity_route_blocks[route_block_index]; 4205 cmic_bit = route_block->cmic_bit; 4206 if (cmic_bit == 0) { 4207 /* End of table */ 4208 break; 4209 } 4210 /* Enable the route block entry in the CMIC register */ 4211 if (enable) { 4212 cmic_rval |= cmic_bit; 4213 } 4214 4215 route_block_en_reg = route_block->enable_reg; 4216 addr = soc_reg_addr(unit, route_block_en_reg, REG_PORT_ANY, 0); 4217 SOC_IF_ERROR_RETURN(soc_reg32_read(unit, addr, &route_block_rval)); 4218 4219 if (route_block->blocktype == SOC_BLK_MMU) { 4220 SOC_IF_ERROR_RETURN 4221 (_soc_katana_parity_enable_mmu(unit, route_block_en_reg, enable)); 4222 } else { 4223 SOC_IF_ERROR_RETURN 4224 (_soc_katana_parity_enable_info(unit, 4225 route_block->id, 4226 route_block_en_reg, 4227 &route_block_rval, 4228 route_block->info, enable)); 4229 4230 /* Write per route block parity enable register */ 4231 addr = soc_reg_addr(unit, route_block_en_reg, REG_PORT_ANY, 0); 4232 SOC_IF_ERROR_RETURN(soc_reg32_write(unit, addr, route_block_rval)); 4233 } 4234 } /* Loop through each place-and-route block entry */ 4235 4236 SOC_IF_ERROR_RETURN(READ_MISCCONFIGr(unit, &rval)); 4237 soc_reg_field_set(unit, MISCCONFIGr, &rval, PARITY_STAT_CLEARf, 1); 4238 SOC_IF_ERROR_RETURN(WRITE_MISCCONFIGr(unit, rval)); 4239 if (enable) { 4240 /* MMU enables */ 4241 soc_reg_field_set(unit, MISCCONFIGr, &rval, PARITY_CHK_ENf, 1); 4242 soc_reg_field_set(unit, MISCCONFIGr, &rval, PARITY_GEN_ENf, 1); 4243 soc_reg_field_set(unit, MISCCONFIGr, &rval, PARITY_STAT_CLEARf, 0); 4244 SOC_IF_ERROR_RETURN(WRITE_MISCCONFIGr(unit, rval)); 4245 /* Write CMIC enable register */ 4246 (void)soc_cmicm_intr2_enable(unit, cmic_rval); 4247 } else { 4248 /* MMU disables */ 4249 soc_reg_field_set(unit, MISCCONFIGr, &rval, PARITY_CHK_ENf, 0); 4250 soc_reg_field_set(unit, MISCCONFIGr, &rval, PARITY_GEN_ENf, 0); 4251 soc_reg_field_set(unit, MISCCONFIGr, &rval, PARITY_STAT_CLEARf, 0); 4252 SOC_IF_ERROR_RETURN(WRITE_MISCCONFIGr(unit, rval)); 4253 /* Write CMIC disable register */ 4254 (void)soc_cmicm_intr2_disable(unit, cmic_rval); 4255 } 4256 return SOC_E_NONE; 4257 } 4258 4259 void 4260 _soc_katana_mem_rename(soc_mem_t *memory) 4261 { 4262 soc_mem_t mem = *memory; 4263 4264 switch(*memory) { 4265 case VLAN_SUBNET_DATA_ONLYm: 4266 mem = VLAN_SUBNETm; 4267 break; 4268 case L2_ENTRY_ONLYm: 4269 mem = L2Xm; 4270 break; 4271 case L2_USER_ENTRY_ONLYm: 4272 case L2_USER_ENTRY_DATA_ONLYm: 4273 mem = L2_USER_ENTRYm; 4274 break; 4275 case L3_DEFIP_DATA_ONLYm: 4276 case L3_DEFIP_HIT_ONLYm: 4277 mem = L3_DEFIPm; 4278 break; 4279 case L3_DEFIP_128_DATA_ONLYm: 4280 mem = L3_DEFIP_128m; 4281 break; 4282 case EGR_IP_TUNNEL_IPV6m: 4283 case EGR_IP_TUNNEL_MPLSm: 4284 mem = EGR_IP_TUNNELm; 4285 break; 4286 case L3_ENTRY_IPV4_UNICASTm: 4287 case L3_ENTRY_IPV6_UNICASTm: 4288 case L3_ENTRY_IPV4_MULTICASTm: 4289 case L3_ENTRY_IPV6_MULTICASTm: 4290 mem = L3_ENTRY_ONLYm; 4291 break; 4292 case VLAN_MACm: 4293 mem = VLAN_XLATEm; 4294 break; 4295 default: 4296 /* Do nothing, keep memory as provided */ 4297 break; 4298 } 4299 *memory = mem; 4300 } 4301 4302 int 4303 _soc_katana_mem_parity_control(int unit, soc_mem_t mem, int copyno, 4304 int enable) 4305 { 4306 const _soc_katana_parity_route_block_t *route_block; 4307 int route_block_index; 4308 uint32 cmic_bit; 4309 int info_index; 4310 soc_reg_t reg; 4311 uint32 addr, rval; 4312 const _soc_katana_parity_info_t *info; 4313 4314 if (!soc_property_get(unit, spn_PARITY_ENABLE, FALSE)) { 4315 /* Parity checking is not enabled, nothing to do */ 4316 return SOC_E_NONE; 4317 } 4318 4319 /* Convert component/aggregate memories to the table for which 4320 * the parity registers correspond. */ 4321 _soc_katana_mem_rename(&mem); 4322 4323 /* Loop through each place-and-route block entry */ 4324 for (route_block_index = 0; ; route_block_index++) { 4325 route_block = &_soc_katana_parity_route_blocks[route_block_index]; 4326 cmic_bit = route_block->cmic_bit; 4327 if (cmic_bit == 0) { 4328 /* End of table */ 4329 break; 4330 } 4331 4332 if (route_block->blocktype == SOC_BLK_MMU) { 4333 SOC_IF_ERROR_RETURN(_soc_katana_parity_enable_mmu(unit, 4334 route_block->enable_reg, enable)); 4335 continue; 4336 } 4337 4338 /* Loop through each info entry in the list */ 4339 for (info_index = 0; ; info_index++) { 4340 info = &route_block->info[info_index]; 4341 if (info->type == _SOC_PARITY_TYPE_NONE) { 4342 /* End of table */ 4343 break; 4344 } 4345 if (mem != INVALIDm && info->mem != mem) { 4346 continue; 4347 } 4348 4349 /* Handle different parity error reporting style */ 4350 switch (info->type) { 4351 case _SOC_PARITY_TYPE_PARITY: 4352 case _SOC_PARITY_TYPE_ECC: 4353 case _SOC_PARITY_TYPE_HASH: 4354 case _SOC_PARITY_TYPE_EDATABUF: 4355 case _SOC_PARITY_TYPE_COUNTER: 4356 reg = info->enable_reg; 4357 if (!SOC_REG_IS_VALID(unit, reg)) { 4358 continue; 4359 } 4360 addr = soc_reg_addr(unit, reg, REG_PORT_ANY, 0); 4361 SOC_IF_ERROR_RETURN(soc_reg32_read(unit, addr, &rval)); 4362 soc_reg_field_set(unit, reg, &rval, info->enable_field, 4363 enable ? 1 : 0); 4364 SOC_IF_ERROR_RETURN(soc_reg32_write(unit, addr, rval)); 4365 break; 4366 case _SOC_PARITY_TYPE_MXQPORT: 4367 /* One more level of report tree structure */ 4368 SOC_IF_ERROR_RETURN 4369 (_soc_katana_parity_enable_mxqport(unit, 4370 route_block->id, info, enable)); 4371 break; 4372 case _SOC_PARITY_TYPE_GENERIC: 4373 default: 4374 break; 4375 } 4376 } 4377 } 4378 4379 return SOC_E_NONE; 4380 } 4381 4382 4383 STATIC int 4384 _soc_katana_parity_process_info(int unit, uint8 id, soc_reg_t reg, 4385 uint32 status, 4386 uint32 *handled_status, 4387 const _soc_katana_parity_info_t *info_list, 4388 char *prefix_str, soc_block_t block); 4389 4390 STATIC int 4391 _soc_katana_parity_process_parity(int unit, 4392 const _soc_katana_parity_info_t *info, 4393 int schan, char *prefix_str, char *mem_str, 4394 soc_block_t block) 4395 { 4396 _soc_katana_parity_reg_t reg_entry[2], *reg_ptr; 4397 soc_reg_t reg; 4398 uint32 addr, rval; 4399 uint32 multiple, entry_idx, idx, has_error; 4400 char *mem_str_ptr; 4401 _soc_ser_correct_info_t spci = {0}; 4402 4403 if (schan) { 4404 /* Some table does not have NACK register */ 4405 if (info->nack_status_reg == INVALIDr && 4406 info->nack_status_reg_list == NULL) { 4407 return SOC_E_NONE; 4408 } 4409 reg_entry[0].reg = info->nack_status_reg; 4410 reg_entry[0].mem_str = NULL; 4411 reg_entry[1].reg = INVALIDr; 4412 reg_ptr = reg_entry; 4413 } else { 4414 if (info->intr_status_reg != INVALIDr) { 4415 reg_entry[0].reg = info->intr_status_reg; 4416 reg_entry[0].mem_str = NULL; 4417 reg_entry[1].reg = INVALIDr; 4418 reg_ptr = reg_entry; 4419 } else if (info->intr_status_reg_list != NULL) { 4420 reg_ptr = info->intr_status_reg_list; 4421 } else { 4422 return SOC_E_NONE; 4423 } 4424 } 4425 4426 has_error = FALSE; 4427 for (idx = 0; reg_ptr[idx].reg != INVALIDr; idx++) { 4428 reg = reg_ptr[idx].reg; 4429 mem_str_ptr = reg_ptr[idx].mem_str != NULL ? 4430 reg_ptr[idx].mem_str : mem_str; 4431 addr = soc_reg_addr(unit, reg, REG_PORT_ANY, 0); 4432 SOC_IF_ERROR_RETURN(soc_reg32_read(unit, addr, &rval)); 4433 4434 if (soc_reg_field_get(unit, reg, rval, PARITY_ERRf)) { 4435 has_error = TRUE; 4436 multiple = soc_reg_field_get(unit, reg, rval, MULTIPLE_ERRf); 4437 entry_idx = soc_reg_field_get(unit, reg, rval, ENTRY_IDXf); 4438 LOG_ERROR(BSL_LS_SOC_COMMON, 4439 (BSL_META_U(unit, 4440 "%s %s entry %d parity error\n"), 4441 prefix_str, mem_str_ptr, entry_idx)); 4442 if (multiple) { 4443 LOG_ERROR(BSL_LS_SOC_COMMON, 4444 (BSL_META_U(unit, 4445 "%s %s has multiple parity errors\n"), 4446 prefix_str, mem_str_ptr)); 4447 } 4448 if (info->mem != INVALIDm) { 4449 spci.flags = SOC_SER_SRC_MEM | SOC_SER_REG_MEM_KNOWN; 4450 spci.reg = INVALIDr; 4451 spci.mem = info->mem; 4452 spci.blk_type = block; 4453 spci.index = entry_idx; 4454 (void)soc_ser_correction(unit, &spci); 4455 } 4456 /* Clear parity status */ 4457 SOC_IF_ERROR_RETURN(soc_reg32_write(unit, addr, 0)); 4458 } 4459 4460 } 4461 4462 if (!has_error) { 4463 LOG_ERROR(BSL_LS_SOC_COMMON, 4464 (BSL_META_U(unit, 4465 "%s %s parity hardware inconsistency\n"), 4466 prefix_str, mem_str)); 4467 } 4468 4469 return SOC_E_NONE; 4470 } /*_soc_katana_parity_process_parity*/ 4471 4472 STATIC int 4473 _soc_katana_parity_process_ecc(int unit, 4474 const _soc_katana_parity_info_t *info, 4475 int schan, char *prefix_str, char *mem_str, 4476 soc_block_t block) 4477 { 4478 _soc_katana_parity_reg_t reg_entry[2], *reg_ptr; 4479 soc_reg_t reg; 4480 uint32 addr, rval; 4481 uint32 multiple, double_bit, entry_idx, idx, has_error; 4482 char *mem_str_ptr; 4483 _soc_ser_correct_info_t spci = {0}; 4484 4485 if (schan) { 4486 /* Some table does not have NACK register */ 4487 if (info->nack_status_reg == INVALIDr && 4488 info->nack_status_reg_list == NULL) { 4489 return SOC_E_NONE; 4490 } 4491 reg_entry[0].reg = info->nack_status_reg; 4492 reg_entry[0].mem_str = NULL; 4493 reg_entry[1].reg = INVALIDr; 4494 reg_ptr = reg_entry; 4495 } else { 4496 if (info->intr_status_reg != INVALIDr) { 4497 reg_entry[0].reg = info->intr_status_reg; 4498 reg_entry[0].mem_str = NULL; 4499 reg_entry[1].reg = INVALIDr; 4500 reg_ptr = reg_entry; 4501 } else if (info->intr_status_reg_list != NULL) { 4502 reg_ptr = info->intr_status_reg_list; 4503 } else { 4504 return SOC_E_NONE; 4505 } 4506 } 4507 4508 has_error = FALSE; 4509 for (idx = 0; reg_ptr[idx].reg != INVALIDr; idx++) { 4510 reg = reg_ptr[idx].reg; 4511 mem_str_ptr = reg_ptr[idx].mem_str != NULL ? 4512 reg_ptr[idx].mem_str : mem_str; 4513 addr = soc_reg_addr(unit, reg, REG_PORT_ANY, 0); 4514 SOC_IF_ERROR_RETURN(soc_reg32_read(unit, addr, &rval)); 4515 4516 multiple = 0; 4517 double_bit = 0; 4518 entry_idx = 0; 4519 4520 if (soc_reg_field_get(unit, reg, rval, ECC_ERRf)) { 4521 has_error = TRUE; 4522 if (SOC_REG_FIELD_VALID(unit, reg, MULTIPLE_ERRf)) { 4523 multiple = soc_reg_field_get(unit, reg, rval, MULTIPLE_ERRf); 4524 } 4525 if (SOC_REG_FIELD_VALID(unit, reg, DOUBLE_BIT_ERRf)) { 4526 double_bit = soc_reg_field_get(unit, reg, rval, DOUBLE_BIT_ERRf); 4527 } 4528 if (SOC_REG_FIELD_VALID(unit, reg, ENTRY_IDXf)) { 4529 entry_idx = soc_reg_field_get(unit, reg, rval, ENTRY_IDXf); 4530 } 4531 if (double_bit) { 4532 LOG_ERROR(BSL_LS_SOC_COMMON, 4533 (BSL_META_U(unit, 4534 "%s %s entry %d double-bit ECC error\n"), 4535 prefix_str, mem_str_ptr, entry_idx)); 4536 spci.double_bit = 1; 4537 } else { 4538 LOG_ERROR(BSL_LS_SOC_COMMON, 4539 (BSL_META_U(unit, 4540 "%s %s entry %d ECC error\n"), 4541 prefix_str, mem_str_ptr, entry_idx)); 4542 } 4543 4544 if (multiple) { 4545 LOG_ERROR(BSL_LS_SOC_COMMON, 4546 (BSL_META_U(unit, 4547 "%s %s has multiple ECC errors\n"), 4548 prefix_str, mem_str_ptr)); 4549 } 4550 4551 if (info->mem != INVALIDm) { 4552 spci.flags = SOC_SER_SRC_MEM | SOC_SER_REG_MEM_KNOWN; 4553 spci.reg = INVALIDr; 4554 spci.mem = info->mem; 4555 spci.blk_type = block; 4556 spci.index = entry_idx; 4557 spci.parity_type = SOC_PARITY_TYPE_ECC; 4558 (void)soc_ser_correction(unit, &spci); 4559 } 4560 /* Clear parity status */ 4561 SOC_IF_ERROR_RETURN(soc_reg32_write(unit, addr, 0)); 4562 } 4563 4564 } 4565 4566 if (!has_error) { 4567 LOG_ERROR(BSL_LS_SOC_COMMON, 4568 (BSL_META_U(unit, 4569 "%s %s ECC hardware inconsistency\n"), 4570 prefix_str, mem_str)); 4571 } 4572 4573 return SOC_E_NONE; 4574 } 4575 4576 STATIC int 4577 _soc_katana_parity_process_hash(int unit, 4578 const _soc_katana_parity_info_t *info, 4579 int schan, char *prefix_str, char *mem_str, 4580 soc_block_t block) 4581 { 4582 _soc_katana_parity_reg_t *reg_ptr; 4583 soc_reg_t reg; 4584 uint32 addr, rval; 4585 uint32 bitmap, multiple, bucket_idx; 4586 int bucket_size, entry_idx = -1, idx, bank_bkt_idx, bits, has_error; 4587 _soc_ser_correct_info_t spci = {0}; 4588 soc_field_t efield = PARITY_ERR_BMf; 4589 soc_field_t bfield = BUCKET_IDXf; 4590 soc_field_t mfield = MULTIPLE_ERRf; 4591 4592 if (schan) { 4593 reg_ptr = info->nack_status_reg_list; 4594 } else { 4595 reg_ptr = info->intr_status_reg_list; 4596 } 4597 4598 has_error = FALSE; 4599 for (idx = 0; idx < 2; idx ++) { 4600 reg = reg_ptr[idx].reg; 4601 addr = soc_reg_addr(unit, reg, REG_PORT_ANY, 0); 4602 SOC_IF_ERROR_RETURN(soc_reg32_read(unit, addr, &rval)); 4603 4604 /* Some memories have this field named differently */ 4605 if (soc_reg_field_valid(unit, reg, PARITY_ERR_BMf)) { 4606 efield = PARITY_ERR_BMf; 4607 bfield = BUCKET_IDXf; 4608 mfield = MULTIPLE_ERRf; 4609 } else if (soc_reg_field_valid(unit, reg, PARITY_ERR_BM_0f)) { 4610 efield = PARITY_ERR_BM_0f; 4611 bfield = BUCKET_IDX_0f; 4612 mfield = MULTIPLE_ERR_0f; 4613 } else if (soc_reg_field_valid(unit, reg, PARITY_ERR_BM_1f)) { 4614 efield = PARITY_ERR_BM_1f; 4615 bfield = BUCKET_IDX_1f; 4616 mfield = MULTIPLE_ERR_1f; 4617 } 4618 4619 bitmap = soc_reg_field_get(unit, reg, rval, efield); 4620 if (bitmap != 0) { 4621 has_error = TRUE; 4622 multiple = soc_reg_field_get(unit, reg, rval, mfield); 4623 bucket_size = soc_reg_field_length(unit, reg, efield); 4624 bucket_idx = soc_reg_field_get(unit, reg, rval, bfield) * 4625 bucket_size * 2; 4626 bank_bkt_idx = idx * bucket_size + bucket_idx; 4627 for (bits = 0; bits < bucket_size; bits++) { 4628 if (bitmap & (1 << bits)) { 4629 entry_idx = bank_bkt_idx + bits; 4630 LOG_ERROR(BSL_LS_SOC_COMMON, 4631 (BSL_META_U(unit, 4632 "%s %s entry %d parity error\n"), 4633 prefix_str, mem_str, entry_idx)); 4634 } 4635 } 4636 if (multiple) { 4637 LOG_ERROR(BSL_LS_SOC_COMMON, 4638 (BSL_META_U(unit, 4639 "%s %s has multiple parity errors\n"), 4640 prefix_str, mem_str)); 4641 } 4642 4643 if ((info->mem != INVALIDm) && (entry_idx != -1)) { 4644 spci.flags = SOC_SER_SRC_MEM | SOC_SER_REG_MEM_KNOWN; 4645 spci.reg = INVALIDr; 4646 spci.mem = info->mem; 4647 spci.blk_type = block; 4648 spci.index = entry_idx; 4649 (void)soc_ser_correction(unit, &spci); 4650 } 4651 4652 /* Clear parity status */ 4653 SOC_IF_ERROR_RETURN(soc_reg32_write(unit, addr, 0)); 4654 } 4655 } 4656 4657 if (!has_error) { 4658 LOG_ERROR(BSL_LS_SOC_COMMON, 4659 (BSL_META_U(unit, 4660 "%s %s parity hardware inconsistency\n"), 4661 prefix_str, mem_str)); 4662 } 4663 4664 return SOC_E_NONE; 4665 } 4666 4667 STATIC int 4668 _soc_katana_parity_process_edatabuf(int unit, 4669 const _soc_katana_parity_info_t *info, 4670 int schan, char *prefix_str, 4671 char *mem_str) 4672 { 4673 soc_reg_t reg; 4674 uint32 addr, rval; 4675 uint32 double_bit, multiple; 4676 4677 if (schan) { 4678 /* Some table may not have NACK status register */ 4679 if (info->nack_status_reg == INVALIDr) { 4680 return SOC_E_NONE; 4681 } 4682 reg = info->nack_status_reg; 4683 } else { 4684 reg = info->intr_status_reg; 4685 } 4686 addr = soc_reg_addr(unit, reg, REG_PORT_ANY, 0); 4687 SOC_IF_ERROR_RETURN(soc_reg32_read(unit, addr, &rval)); 4688 4689 if (soc_reg_field_get(unit, reg, rval, ECC_ERR_MGRPf)) { 4690 double_bit = soc_reg_field_get(unit, reg, rval, ECC_ERR_2B_MGRPf); 4691 multiple = soc_reg_field_get(unit, reg, rval, ECC_MULTI_MGRPf); 4692 if (double_bit) { 4693 LOG_ERROR(BSL_LS_SOC_COMMON, 4694 (BSL_META_U(unit, 4695 "%s %s double-bit ECC error\n"), 4696 prefix_str, mem_str)); 4697 } else { 4698 LOG_ERROR(BSL_LS_SOC_COMMON, 4699 (BSL_META_U(unit, 4700 "%s %s ECC error\n"), 4701 prefix_str, mem_str)); 4702 } 4703 if (multiple) { 4704 LOG_ERROR(BSL_LS_SOC_COMMON, 4705 (BSL_META_U(unit, 4706 "%s %s has multiple ECC errors\n"), 4707 prefix_str, mem_str)); 4708 } 4709 } else { 4710 LOG_ERROR(BSL_LS_SOC_COMMON, 4711 (BSL_META_U(unit, 4712 "%s %s ECC hardware inconsistency\n"), 4713 prefix_str, mem_str)); 4714 } 4715 4716 /* Clear parity status */ 4717 SOC_IF_ERROR_RETURN(soc_reg32_write(unit, addr, 0)); 4718 4719 return SOC_E_NONE; 4720 } 4721 4722 STATIC int 4723 _soc_katana_parity_process_counter(int unit, 4724 const _soc_katana_parity_info_t *info, 4725 int schan, char *prefix_str, char *mem_str, 4726 soc_block_t block) 4727 { 4728 soc_cmap_t *cmap; 4729 soc_reg_t reg, counter_reg; 4730 uint32 addr, rval; 4731 uint32 multiple, counter_idx, port_idx, entry_idx; 4732 char *counter_name; 4733 _soc_ser_correct_info_t spci = {0}; 4734 4735 if (schan) { 4736 reg = info->nack_status_reg; 4737 } else { 4738 reg = info->intr_status_reg; 4739 } 4740 addr = soc_reg_addr(unit, reg, REG_PORT_ANY, 0); 4741 SOC_IF_ERROR_RETURN(soc_reg32_read(unit, addr, &rval)); 4742 4743 if (soc_reg_field_get(unit, reg, rval, PARITY_ERRf)) { 4744 multiple = soc_reg_field_get(unit, reg, rval, MULTIPLE_ERRf); 4745 counter_idx = soc_reg_field_get(unit, reg, rval, COUNTER_IDXf); 4746 port_idx = soc_reg_field_get(unit, reg, rval, PORT_IDXf); 4747 entry_idx = soc_reg_field_get(unit, reg, rval, ENTRY_IDXf); 4748 4749 /* TDBGC starts at index 0x1A of counter DMA table */ 4750 if (info->group_reg_status_field == EGR_STATS_COUNTER_TABLE_PAR_ERRf) { 4751 counter_idx += 0x1A; 4752 } 4753 cmap = soc_port_cmap_get(unit, port_idx); 4754 counter_reg = cmap->cmap_base[counter_idx].reg; 4755 if (SOC_REG_IS_VALID(unit, counter_reg)) { 4756 counter_name = SOC_REG_NAME(unit, counter_reg); 4757 LOG_ERROR(BSL_LS_SOC_COMMON, 4758 (BSL_META_U(unit, 4759 "%s %s port %d %s entry %d parity error\n"), 4760 prefix_str, mem_str, port_idx, counter_name, 4761 entry_idx)); 4762 if (multiple) { 4763 LOG_ERROR(BSL_LS_SOC_COMMON, 4764 (BSL_META_U(unit, 4765 "%s %s has multiple parity errors\n"), 4766 prefix_str, mem_str)); 4767 } 4768 spci.flags = SOC_SER_SRC_REG | SOC_SER_REG_MEM_KNOWN; 4769 spci.reg = counter_reg; 4770 spci.mem = INVALIDm; 4771 spci.blk_type = block; 4772 spci.port = port_idx; 4773 (void)soc_ser_correction(unit, &spci); 4774 _stat_error_fixed[unit]++; 4775 } else { 4776 LOG_ERROR(BSL_LS_SOC_COMMON, 4777 (BSL_META_U(unit, 4778 "%s %s parity hardware inconsistency\n"), 4779 prefix_str, mem_str)); 4780 } 4781 } else if (!schan) { 4782 LOG_ERROR(BSL_LS_SOC_COMMON, 4783 (BSL_META_U(unit, 4784 "%s %s parity hardware inconsistency\n"), 4785 prefix_str, mem_str)); 4786 } 4787 4788 /* Clear parity status */ 4789 SOC_IF_ERROR_RETURN(soc_reg32_write(unit, addr, 0)); 4790 4791 return SOC_E_NONE; 4792 } 4793 4794 4795 STATIC 4796 int _soc_katana_process_sb_type_1_mmu_parity_error(int unit, 4797 _soc_katana_mmu_subblock_type_t sub_block_type, 4798 soc_reg_t stat_reg, soc_reg_t en_reg, 4799 _soc_katana_mmu_sub_block_type_1_info_t * sub_block_info) 4800 { 4801 uint32 addr, stat_rval, en_rval; 4802 uint32 intr_bit; 4803 int sb_index = 0; 4804 _soc_katana_mmu_sub_block_type_1_info_t *sub_block; 4805 char prefix_str[10]; 4806 char *reg_str; 4807 char *field_str; 4808 4809 sal_sprintf(prefix_str, "unit %d", unit); 4810 addr = soc_reg_addr(unit, stat_reg, REG_PORT_ANY, 0); 4811 SOC_IF_ERROR_RETURN(soc_reg32_read(unit, addr, &stat_rval)); 4812 4813 addr = soc_reg_addr(unit, en_reg, REG_PORT_ANY, 0); 4814 SOC_IF_ERROR_RETURN(soc_reg32_read(unit, addr, &en_rval)); 4815 stat_rval &= (~en_rval); 4816 if (stat_rval == 0) { 4817 /* How did this interrupt get asserted then??? */ 4818 return SOC_E_NONE; 4819 } 4820 for (sb_index = 0; ; sb_index++) { 4821 sub_block = &sub_block_info[sb_index]; 4822 intr_bit = sub_block->intr_bit; 4823 if(intr_bit == 0) { 4824 /* End of table */ 4825 return SOC_E_NONE; 4826 } 4827 if (stat_rval & intr_bit) { 4828 field_str = SOC_FIELD_NAME(unit, sub_block->sub_block_field); 4829 reg_str = SOC_REG_NAME(unit, stat_reg); 4830 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 4831 SOC_SWITCH_EVENT_DATA_ERROR_PARITY, 4832 stat_reg, sub_block->sub_block_field); 4833 LOG_ERROR(BSL_LS_SOC_COMMON, 4834 (BSL_META_U(unit, 4835 "%s MMU subblock %x reg %s field %s(value = 0x%x) has \ 4836 MMU parity error\n"), 4837 prefix_str, sub_block_type, reg_str, 4838 field_str, stat_rval)); 4839 /* clear the parity error bit */ 4840 addr = soc_reg_addr(unit, stat_reg, REG_PORT_ANY, 0); 4841 SOC_IF_ERROR_RETURN(soc_reg32_write(unit, addr, intr_bit)); 4842 } 4843 } 4844 return SOC_E_NONE; 4845 } 4846 4847 STATIC 4848 int _soc_katana_process_sb_type_1_ci_mmu_parity_error(int unit, 4849 soc_block_t block, 4850 _soc_katana_mmu_subblock_type_t sub_block_type, 4851 soc_reg_t stat_reg, soc_reg_t en_reg, 4852 _soc_katana_mmu_sub_block_type_1_info_t * sub_block_info) 4853 { 4854 uint32 stat_rval, en_rval; 4855 uint32 intr_bit; 4856 int sb_index = 0; 4857 _soc_katana_mmu_sub_block_type_1_info_t *sub_block; 4858 char prefix_str[10]; 4859 char *reg_str; 4860 char *field_str; 4861 soc_port_t port = 0; 4862 4863 sal_sprintf(prefix_str, "unit %d", unit); 4864 port = SOC_BLOCK_PORT(unit, block); 4865 SOC_IF_ERROR_RETURN(READ_CI_ERRORr(unit, port, &stat_rval)); 4866 4867 SOC_IF_ERROR_RETURN(READ_CI_ERROR_MASKr(unit, port, &en_rval)); 4868 stat_rval &= (~en_rval); 4869 if (stat_rval == 0) { 4870 /* How did this interrupt get asserted then??? */ 4871 return SOC_E_NONE; 4872 } 4873 for (sb_index = 0; ; sb_index++) { 4874 sub_block = &sub_block_info[sb_index]; 4875 intr_bit = sub_block->intr_bit; 4876 if(intr_bit == 0) { 4877 /* End of table */ 4878 return SOC_E_NONE; 4879 } 4880 if (stat_rval & intr_bit) { 4881 field_str = SOC_FIELD_NAME(unit, sub_block->sub_block_field); 4882 reg_str = SOC_REG_NAME(unit, stat_reg); 4883 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 4884 SOC_SWITCH_EVENT_DATA_ERROR_PARITY, 4885 stat_reg, sub_block->sub_block_field); 4886 LOG_ERROR(BSL_LS_SOC_COMMON, 4887 (BSL_META_U(unit, 4888 "%s MMU subblock %x reg %s field %s (value = 0x%x) has \ 4889 MMU parity error\n"), 4890 prefix_str, sub_block_type, reg_str, 4891 field_str, stat_rval)); 4892 /* clear the parity error bit */ 4893 SOC_IF_ERROR_RETURN(WRITE_CI_ERRORr(unit, port, intr_bit)); 4894 } 4895 } 4896 return SOC_E_NONE; 4897 } 4898 4899 STATIC 4900 int _soc_katana_process_sb_type_2_mmu_parity_error(int unit, 4901 _soc_katana_mmu_subblock_type_t sub_block_type, 4902 soc_reg_t stat_reg, soc_reg_t en_reg, 4903 _soc_katana_mmu_sub_block_type_2_info_t * sub_block_info) 4904 { 4905 uint32 addr, stat_rval, en_rval; 4906 uint32 intr_bit; 4907 int sb_index = 0; 4908 _soc_katana_mmu_sub_block_type_2_info_t *sub_block; 4909 char prefix_str[10]; 4910 char *reg_str; 4911 char *field_str; 4912 4913 sal_sprintf(prefix_str, "unit %d", unit); 4914 addr = soc_reg_addr(unit, stat_reg, REG_PORT_ANY, 0); 4915 SOC_IF_ERROR_RETURN(soc_reg32_read(unit, addr, &stat_rval)); 4916 4917 addr = soc_reg_addr(unit, en_reg, REG_PORT_ANY, 0); 4918 SOC_IF_ERROR_RETURN(soc_reg32_read(unit, addr, &en_rval)); 4919 if (stat_reg == INTFI_ECC_STATUSr) { 4920 stat_rval &= ((~en_rval) >> 3); 4921 } else if (stat_reg == RQE_EXTQ_REPLICATION_COUNTr) { 4922 stat_rval &= ((~en_rval) << 11); 4923 } 4924 if (stat_rval == 0) { 4925 /* How did this interrupt get asserted then??? */ 4926 return SOC_E_NONE; 4927 } 4928 for (sb_index = 0; ; sb_index++) { 4929 sub_block = &sub_block_info[sb_index]; 4930 intr_bit = sub_block->intr_bit; 4931 if(intr_bit == 0) { 4932 /* End of table */ 4933 return SOC_E_NONE; 4934 } 4935 if (stat_rval & intr_bit) { 4936 field_str = SOC_FIELD_NAME(unit, sub_block->sub_block_field); 4937 reg_str = SOC_REG_NAME(unit, stat_reg); 4938 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 4939 SOC_SWITCH_EVENT_DATA_ERROR_PARITY, 4940 stat_reg, sub_block->sub_block_field); 4941 LOG_ERROR(BSL_LS_SOC_COMMON, 4942 (BSL_META_U(unit, 4943 "%s MMU subblock %x reg %s field %s (value=0x%x) has \ 4944 MMU parity error\n"), 4945 prefix_str, sub_block_type, reg_str, 4946 field_str, stat_rval)); 4947 /* clear the parity error bit */ 4948 addr = soc_reg_addr(unit, stat_reg, REG_PORT_ANY, 0); 4949 SOC_IF_ERROR_RETURN(soc_reg32_write(unit, addr, intr_bit)); 4950 } 4951 } 4952 return SOC_E_NONE; 4953 } 4954 4955 STATIC 4956 int _soc_katana_process_sb_mmu_lvl1_parity_error(int unit, 4957 soc_reg_t stat_reg, soc_reg_t en_reg, 4958 _soc_katana_mmu_sub_block_type_3_info_t * sub_block_info) 4959 { 4960 uint32 addr, stat_rval, en_rval, lvl1_stat_rval, lvl1_en_rval ; 4961 uint32 intr_bit; 4962 int sb_index = 0; 4963 _soc_katana_mmu_sub_block_type_3_info_t *sub_block; 4964 4965 addr = soc_reg_addr(unit, stat_reg, REG_PORT_ANY, 0); 4966 SOC_IF_ERROR_RETURN(soc_reg32_read(unit, addr, &stat_rval)); 4967 4968 if (en_reg != 0) { 4969 addr = soc_reg_addr(unit, en_reg, REG_PORT_ANY, 0); 4970 SOC_IF_ERROR_RETURN(soc_reg32_read(unit, addr, &en_rval)); 4971 stat_rval &= (~en_rval); 4972 } 4973 if (stat_rval == 0) { 4974 /* How did this interrupt get asserted then??? */ 4975 return SOC_E_NONE; 4976 } 4977 4978 for (sb_index = 0; ; sb_index++) { 4979 sub_block = &sub_block_info[sb_index]; 4980 intr_bit = sub_block->intr_bit; 4981 if(intr_bit == 0) { 4982 /* End of table */ 4983 return SOC_E_NONE; 4984 } 4985 addr = soc_reg_addr(unit, sub_block->sub_block_reg, REG_PORT_ANY, 0); 4986 SOC_IF_ERROR_RETURN(soc_reg32_read(unit, addr, &lvl1_stat_rval)); 4987 4988 if (sub_block->sub_block_en_reg != 0) { 4989 addr = soc_reg_addr(unit, sub_block->sub_block_en_reg, 4990 REG_PORT_ANY, 0); 4991 SOC_IF_ERROR_RETURN(soc_reg32_read(unit, addr, &lvl1_en_rval)); 4992 lvl1_stat_rval &= (~lvl1_en_rval); 4993 } 4994 if (lvl1_stat_rval == 0) { 4995 /* How did this interrupt get asserted then??? */ 4996 return SOC_E_NONE; 4997 } 4998 if (lvl1_stat_rval & intr_bit) { 4999 switch (sub_block->lvl2_sub_block) { 5000 case _SOC_KT_MMU_LVL2_SUBBLOCK_EMC_ERROR_2: 5001 _soc_katana_process_sb_type_1_mmu_parity_error(unit, 5002 _SOC_KT_MMU_SUBBLOCK_EMC, 5003 EMC_ERROR_2r, EMC_ERROR_MASK_2r, 5004 sub_block->info); 5005 break; 5006 5007 case _SOC_KT_MMU_LVL2_SUBBLOCK_EMC_ERROR_1: 5008 _soc_katana_process_sb_type_1_mmu_parity_error(unit, 5009 _SOC_KT_MMU_SUBBLOCK_EMC, 5010 EMC_ERROR_1r, EMC_ERROR_MASK_1r, 5011 sub_block->info); 5012 break; 5013 case _SOC_KT_MMU_LVL2_SUBBLOCK_EMC_ERROR_0: 5014 _soc_katana_process_sb_type_1_mmu_parity_error(unit, 5015 _SOC_KT_MMU_SUBBLOCK_EMC, 5016 EMC_ERROR_0r, EMC_ERROR_MASK_0r, 5017 sub_block->info); 5018 break; 5019 5020 case _SOC_KT_MMU_LVL2_SUBBLOCK_DEQ_ERROR_3: 5021 _soc_katana_process_sb_type_1_mmu_parity_error(unit, 5022 _SOC_KT_MMU_SUBBLOCK_DEQ, 5023 DEQ_ERROR_3r, DEQ_ERROR_MASK_3r, 5024 sub_block->info); 5025 break; 5026 5027 case _SOC_KT_MMU_LVL2_SUBBLOCK_DEQ_ERROR_2: 5028 _soc_katana_process_sb_type_1_mmu_parity_error(unit, 5029 _SOC_KT_MMU_SUBBLOCK_DEQ, 5030 DEQ_ERROR_2r, DEQ_ERROR_MASK_2r, 5031 sub_block->info); 5032 break; 5033 5034 case _SOC_KT_MMU_LVL2_SUBBLOCK_DEQ_ERROR_1: 5035 _soc_katana_process_sb_type_1_mmu_parity_error(unit, 5036 _SOC_KT_MMU_SUBBLOCK_DEQ, 5037 DEQ_ERROR_1r, DEQ_ERROR_MASK_1r, 5038 sub_block->info); 5039 break; 5040 5041 case _SOC_KT_MMU_LVL2_SUBBLOCK_DEQ_ERROR_0: 5042 _soc_katana_process_sb_type_1_mmu_parity_error(unit, 5043 _SOC_KT_MMU_SUBBLOCK_DEQ, 5044 DEQ_ERROR_0r, DEQ_ERROR_MASK_0r, 5045 sub_block->info); 5046 break; 5047 5048 case _SOC_KT_MMU_LVL2_SUBBLOCK_QSTRUCT_QENTRY_U: 5049 _soc_katana_process_sb_type_1_mmu_parity_error(unit, 5050 _SOC_KT_MMU_SUBBLOCK_QSTRUCT, 5051 QSTRUCT_QENTRY_UPPER_ERRORr, 5052 QSTRUCT_QENTRY_UPPER_ERROR_MASKr, 5053 sub_block->info); 5054 break; 5055 5056 case _SOC_KT_MMU_LVL2_SUBBLOCK_QSTRUCT_QENTRY_L: 5057 _soc_katana_process_sb_type_1_mmu_parity_error(unit, 5058 _SOC_KT_MMU_SUBBLOCK_QSTRUCT, 5059 QSTRUCT_QENTRY_LOWER_ERRORr, 5060 QSTRUCT_QENTRY_LOWER_ERROR_MASKr, 5061 sub_block->info); 5062 break; 5063 5064 case _SOC_KT_MMU_LVL2_SUBBLOCK_QSTRUCT_QBLOCK: 5065 _soc_katana_process_sb_type_1_mmu_parity_error(unit, 5066 _SOC_KT_MMU_SUBBLOCK_QSTRUCT, 5067 QSTRUCT_QBLOCK_NEXT_ERRORr, 5068 QSTRUCT_QBLOCK_NEXT_ERROR_MASKr, 5069 sub_block->info); 5070 break; 5071 5072 case _SOC_KT_MMU_LVL2_SUBBLOCK_QSTRUCT_FAP: 5073 _soc_katana_process_sb_type_1_mmu_parity_error(unit, 5074 _SOC_KT_MMU_SUBBLOCK_QSTRUCT, 5075 QSTRUCT_FAP_MEM_ERRORr, 5076 QSTRUCT_FAP_MEM_ERROR_MASKr, 5077 sub_block->info); 5078 break; 5079 5080 default: 5081 break; 5082 } 5083 /* stat_reg and sub_block->sub_block_reg is the same register */ 5084 /* EMC_ERRORr and DEQ_ERRORr are read only, cannot be cleared */ 5085 if (sub_block->lvl2_sub_block == _SOC_KT_MMU_LVL2_SUBBLOCK_QSTRUCT_QENTRY_U || 5086 sub_block->lvl2_sub_block == _SOC_KT_MMU_LVL2_SUBBLOCK_QSTRUCT_QENTRY_L || 5087 sub_block->lvl2_sub_block == _SOC_KT_MMU_LVL2_SUBBLOCK_QSTRUCT_QBLOCK || 5088 sub_block->lvl2_sub_block == _SOC_KT_MMU_LVL2_SUBBLOCK_QSTRUCT_FAP) { 5089 /* clear the Level1 error bit */ 5090 addr = soc_reg_addr(unit, sub_block->sub_block_reg, REG_PORT_ANY, 0); 5091 SOC_IF_ERROR_RETURN(soc_reg32_write(unit, addr, intr_bit)); 5092 } 5093 5094 } 5095 } 5096 return SOC_E_NONE; 5097 } 5098 5099 STATIC int 5100 _soc_katana_parity_process_mmu(int unit, soc_reg_t mmu_en_reg, 5101 soc_reg_t mmu_stat_reg, char *prefix_str) 5102 { 5103 uint32 addr, en_rval, stat_rval; 5104 int sub_block_index; 5105 uint32 mmu_bit; 5106 const _soc_katana_mmu_sub_block_type_1_t *sub_block; 5107 const _soc_katana_mmu_sub_block_type_2_t *sub_block_type2; 5108 const _soc_katana_mmu_sub_block_type_3_t *lvl1_sub_block; 5109 _soc_katana_mmu_subblock_type_t sub_block_type; 5110 5111 addr = soc_reg_addr(unit, mmu_en_reg, REG_PORT_ANY, 0); 5112 SOC_IF_ERROR_RETURN(soc_reg32_read(unit, addr, &en_rval)); 5113 5114 addr = soc_reg_addr(unit, mmu_stat_reg, REG_PORT_ANY, 0); 5115 SOC_IF_ERROR_RETURN(soc_reg32_read(unit, addr, &stat_rval)); 5116 5117 stat_rval &= (~en_rval); 5118 5119 if (stat_rval == 0) { 5120 /* How did this interrupt get asserted then??? */ 5121 return SOC_E_NONE; 5122 } 5123 5124 for (sub_block_index = 0; ; sub_block_index++) { 5125 sub_block = &_soc_katana_mmu_sub_blocks_type_1[sub_block_index]; 5126 mmu_bit = sub_block->mmu_bit; 5127 sub_block_type = sub_block->mmu_sub_block; 5128 if(mmu_bit == 0) { 5129 /* End of table */ 5130 break; 5131 } 5132 if ((mmu_bit & (stat_rval)) == 0) { 5133 /* No interrupts in this sub-block */ 5134 continue; 5135 } 5136 switch (sub_block_type) { 5137 5138 case _SOC_KT_MMU_SUBBLOCK_MEM1: 5139 _soc_katana_process_sb_type_1_mmu_parity_error(unit, 5140 sub_block_type, 5141 CLINK_ERRORr, 5142 CLINK_ERROR_MASKr, 5143 sub_block->info); 5144 break; 5145 5146 case _SOC_KT_MMU_SUBBLOCK_E2EFC: 5147 _soc_katana_process_sb_type_1_mmu_parity_error(unit, 5148 sub_block_type, 5149 MMU_E2EFC_ERROR_0r, 5150 MMU_E2EFC_ERROR_0_MASKr, 5151 sub_block->info); 5152 break; 5153 5154 case _SOC_KT_MMU_SUBBLOCK_THDI: 5155 _soc_katana_process_sb_type_1_mmu_parity_error(unit, 5156 sub_block_type, 5157 MMU_THDI_INTRr, 5158 MMU_THDI_INTR_MASKr, 5159 sub_block->info); 5160 break; 5161 5162 5163 case _SOC_KT_MMU_SUBBLOCK_CTR: 5164 _soc_katana_process_sb_type_1_mmu_parity_error(unit, 5165 sub_block_type, 5166 CTR_ERRORr, 5167 CTR_ERROR_MASKr, 5168 sub_block->info); 5169 break; 5170 5171 case _SOC_KT_MMU_SUBBLOCK_CCP: 5172 _soc_katana_process_sb_type_1_mmu_parity_error(unit, 5173 sub_block_type, 5174 CCP_ERRORr, 5175 CCP_ERROR_MASKr, 5176 sub_block->info); 5177 break; 5178 5179 case _SOC_KT_MMU_SUBBLOCK_TOQ: 5180 _soc_katana_process_sb_type_1_mmu_parity_error(unit, 5181 sub_block_type, 5182 TOQ_ERRORr, 5183 TOQ_ERROR_MASKr, 5184 sub_block->info); 5185 break; 5186 5187 5188 case _SOC_KT_MMU_SUBBLOCK_CFAPI: 5189 _soc_katana_process_sb_type_1_mmu_parity_error(unit, 5190 sub_block_type, 5191 CFAPI_ECC_ERRORr, 5192 CFAPI_ERROR_MASKr, 5193 sub_block->info); 5194 break; 5195 5196 case _SOC_KT_MMU_SUBBLOCK_CFAPE: 5197 _soc_katana_process_sb_type_1_mmu_parity_error(unit, 5198 sub_block_type, 5199 CFAPE_ECC_ERRORr, 5200 CFAPE_ERROR_MASKr, 5201 sub_block->info); 5202 break; 5203 5204 case _SOC_KT_MMU_SUBBLOCK_ITE: 5205 _soc_katana_process_sb_type_1_mmu_parity_error(unit, 5206 sub_block_type, 5207 MMU_ITE_ERROR_0r, 5208 MMU_ITE_ERROR_0_MASKr, 5209 sub_block->info); 5210 break; 5211 5212 case _SOC_KT_MMU_SUBBLOCK_ITE_CFG: 5213 _soc_katana_process_sb_type_1_mmu_parity_error(unit, 5214 sub_block_type, 5215 MMU_ITE_CFG_ECC_ERROR_0r, 5216 MMU_ITE_CFG_ECC_ERROR_0_MASKr, 5217 sub_block->info); 5218 break; 5219 5220 case _SOC_KT_MMU_SUBBLOCK_ENQ_CFG: 5221 _soc_katana_process_sb_type_1_mmu_parity_error(unit, 5222 sub_block_type, 5223 MMU_ENQ_CFG_ECC_ERROR_0r, 5224 MMU_ENQ_CFG_ECC_ERROR_0_MASKr, 5225 sub_block->info); 5226 break; 5227 5228 case _SOC_KT_MMU_SUBBLOCK_ENQ: 5229 _soc_katana_process_sb_type_1_mmu_parity_error(unit, 5230 sub_block_type, 5231 MMU_ENQ_ERROR_0r, 5232 MMU_ENQ_ERROR_0_MASKr, 5233 sub_block->info); 5234 break; 5235 5236 case _SOC_KT_MMU_SUBBLOCK_ENQ_FAP: 5237 _soc_katana_process_sb_type_1_mmu_parity_error(unit, 5238 sub_block_type, 5239 MMU_ENQ_FAP_ECC_ERROR_0r, 5240 MMU_ENQ_FAP_ECC_ERROR_0_MASKr, 5241 sub_block->info); 5242 break; 5243 5244 case _SOC_KT_MMU_SUBBLOCK_THDO_STATUS1: 5245 _soc_katana_process_sb_type_1_mmu_parity_error(unit, 5246 sub_block_type, 5247 THDO_PARITY_ERROR_STATUS1r, 5248 THDO_PARITY_ERROR_MASK1r, 5249 sub_block->info); 5250 break; 5251 5252 case _SOC_KT_MMU_SUBBLOCK_THDO_STATUS2: 5253 _soc_katana_process_sb_type_1_mmu_parity_error(unit, 5254 sub_block_type, 5255 THDO_PARITY_ERROR_STATUS2r, 5256 THDO_PARITY_ERROR_MASK2r, 5257 sub_block->info); 5258 break; 5259 5260 5261 case _SOC_KT_MMU_SUBBLOCK_AGING_INT: 5262 _soc_katana_process_sb_type_1_mmu_parity_error(unit, 5263 sub_block_type, 5264 AGING_ERROR_INTr, 5265 AGING_ERROR_MASK_INTr, 5266 sub_block->info); 5267 break; 5268 5269 case _SOC_KT_MMU_SUBBLOCK_AGING_EXT: 5270 _soc_katana_process_sb_type_1_mmu_parity_error(unit, 5271 sub_block_type, 5272 AGING_ERROR_EXTr, 5273 AGING_ERROR_MASK_EXTr, 5274 sub_block->info); 5275 break; 5276 5277 case _SOC_KT_MMU_SUBBLOCK_WRED: 5278 _soc_katana_process_sb_type_1_mmu_parity_error(unit, 5279 sub_block_type, 5280 WRED_PARITY_ERROR_BITMAPr, 5281 WRED_PARITY_ERROR_MASKr, 5282 sub_block->info); 5283 break; 5284 5285 case _SOC_KT_MMU_SUBBLOCK_INTFI: 5286 _soc_katana_process_sb_type_1_mmu_parity_error(unit, 5287 sub_block_type, 5288 INTFI_ERROR_STATUSr, 5289 INTFI_ERROR_MASKr, 5290 sub_block->info); 5291 break; 5292 5293 5294 case _SOC_KT_MMU_SUBBLOCK_CI2: 5295 /* Access to CI_ERROR and CI_ERROR_MASK register is resulting is S-Chan 5296 timeout on some KATANA devices which do not have ddr3 memory */ 5297 if (soc_feature(unit, soc_feature_ddr3)) { 5298 _soc_katana_process_sb_type_1_ci_mmu_parity_error(unit, 5299 CI2_BLOCK(unit), 5300 sub_block_type, 5301 CI_ERRORr, 5302 CI_ERROR_MASKr, 5303 sub_block->info); 5304 } 5305 break; 5306 case _SOC_KT_MMU_SUBBLOCK_CI1: 5307 if (soc_feature(unit, soc_feature_ddr3)) { 5308 _soc_katana_process_sb_type_1_ci_mmu_parity_error(unit, 5309 CI1_BLOCK(unit), 5310 sub_block_type, 5311 CI_ERRORr, 5312 CI_ERROR_MASKr, 5313 sub_block->info); 5314 } 5315 break; 5316 case _SOC_KT_MMU_SUBBLOCK_CI0: 5317 if (soc_feature(unit, soc_feature_ddr3)) { 5318 _soc_katana_process_sb_type_1_ci_mmu_parity_error(unit, 5319 CI0_BLOCK(unit), 5320 sub_block_type, 5321 CI_ERRORr, 5322 CI_ERROR_MASKr, 5323 sub_block->info); 5324 } 5325 break; 5326 5327 case _SOC_KT_MMU_SUBBLOCK_LLS: 5328 _soc_katana_process_sb_type_1_mmu_parity_error(unit, 5329 sub_block_type, 5330 LLS_ERRORr, 5331 LLS_ERROR_MASKr, 5332 sub_block->info); 5333 break; 5334 case _SOC_KT_MMU_SUBBLOCK_LLS_PORT: 5335 _soc_katana_process_sb_type_1_mmu_parity_error(unit, 5336 sub_block_type, 5337 LLS_PORT_ECC_ERRORr, 5338 LLS_PORT_ECC_ERROR_MASKr, 5339 sub_block->info); 5340 break; 5341 case _SOC_KT_MMU_SUBBLOCK_LLS_L0_ECC: 5342 _soc_katana_process_sb_type_1_mmu_parity_error(unit, 5343 sub_block_type, 5344 LLS_L0_ECC_ERROR1r, 5345 LLS_L0_ECC_ERROR1_MASKr, 5346 sub_block->info); 5347 break; 5348 case _SOC_KT_MMU_SUBBLOCK_LLS_UPD2: 5349 _soc_katana_process_sb_type_1_mmu_parity_error(unit, 5350 sub_block_type, 5351 LLS_ERROR_UPD2r, 5352 LLS_ERROR_UPD2_MASKr, 5353 sub_block->info); 5354 break; 5355 case _SOC_KT_MMU_SUBBLOCK_LLS_L1_ECC: 5356 _soc_katana_process_sb_type_1_mmu_parity_error(unit, 5357 sub_block_type, 5358 LLS_L1_ECC_ERROR1r, 5359 LLS_L1_ECC_ERROR1_MASKr, 5360 sub_block->info); 5361 break; 5362 case _SOC_KT_MMU_SUBBLOCK_LLS_L2_ECC: 5363 _soc_katana_process_sb_type_1_mmu_parity_error(unit, 5364 sub_block_type, 5365 LLS_L2_ECC_ERROR1r, 5366 LLS_L2_ECC_ERROR1_MASKr, 5367 sub_block->info); 5368 break; 5369 5370 case _SOC_KT_MMU_SUBBLOCK_LLS_MISC_ECC: 5371 _soc_katana_process_sb_type_1_mmu_parity_error(unit, 5372 sub_block_type, 5373 LLS_MISC_ECC_ERROR1r, 5374 LLS_MISC_ECC_ERROR1_MASKr, 5375 sub_block->info); 5376 break; 5377 5378 case _SOC_KT_MMU_SUBBLOCK_RQE_SER: 5379 _soc_katana_process_sb_type_1_mmu_parity_error(unit, 5380 sub_block_type, 5381 RQE_SER_STATUSr, 5382 RQE_SER_MASKr, 5383 sub_block->info); 5384 break; 5385 5386 default: 5387 break; 5388 5389 } 5390 /* clear the MMU parity error bit */ 5391 addr = soc_reg_addr(unit, mmu_stat_reg, REG_PORT_ANY, 0); 5392 SOC_IF_ERROR_RETURN(soc_reg32_write(unit, addr, mmu_bit)); 5393 } 5394 5395 for (sub_block_index = 0; ; sub_block_index++) { 5396 sub_block_type2 = &_soc_katana_mmu_sub_blocks_type_2[sub_block_index]; 5397 mmu_bit = sub_block_type2->mmu_bit; 5398 sub_block_type = sub_block_type2->mmu_sub_block; 5399 if(mmu_bit == 0) { 5400 /* End of table */ 5401 break; 5402 } 5403 if ((mmu_bit & stat_rval) == 0) { 5404 /* No interrupts in this sub-block */ 5405 continue; 5406 } 5407 switch (sub_block_type) { 5408 case _SOC_KT_MMU_SUBBLOCK_RQE_EXTQ: 5409 _soc_katana_process_sb_type_2_mmu_parity_error(unit, 5410 sub_block_type, 5411 RQE_EXTQ_REPLICATION_COUNTr, 5412 RQE_EXTQ_REPLICATION_LIMITr, 5413 sub_block_type2->info); 5414 break; 5415 5416 case _SOC_KT_MMU_SUBBLOCK_INTFI_ECC: 5417 _soc_katana_process_sb_type_2_mmu_parity_error(unit, 5418 sub_block_type, 5419 INTFI_ECC_STATUSr, 5420 INTFI_ERROR_MASKr, 5421 sub_block_type2->info); 5422 break; 5423 5424 default: 5425 break; 5426 5427 } 5428 /* clear the MMU parity error bit */ 5429 addr = soc_reg_addr(unit, mmu_stat_reg, REG_PORT_ANY, 0); 5430 SOC_IF_ERROR_RETURN(soc_reg32_write(unit, addr, mmu_bit)); 5431 } 5432 5433 for (sub_block_index = 0; ; sub_block_index++) { 5434 lvl1_sub_block = &_soc_katana_mmu_sub_blocks_type_3[sub_block_index]; 5435 mmu_bit = lvl1_sub_block->mmu_bit; 5436 sub_block_type = lvl1_sub_block->mmu_sub_block; 5437 if(mmu_bit == 0) { 5438 /* End of table */ 5439 break; 5440 } 5441 if ((mmu_bit & stat_rval) == 0) { 5442 /* No interrupts in this sub-block */ 5443 continue; 5444 } 5445 5446 switch (sub_block_type) { 5447 case _SOC_KT_MMU_SUBBLOCK_EMC: 5448 /* Access to EMC_ERROR register is resulting is S-Chan timeout on some 5449 KATANA devices which do not have ddr3 memory */ 5450 if (soc_feature(unit, soc_feature_ddr3)) { 5451 _soc_katana_process_sb_mmu_lvl1_parity_error(unit, 5452 EMC_ERRORr, 0, 5453 lvl1_sub_block->info); 5454 } 5455 break; 5456 case _SOC_KT_MMU_SUBBLOCK_DEQ: 5457 _soc_katana_process_sb_mmu_lvl1_parity_error(unit, 5458 DEQ_ERRORr, 0, 5459 lvl1_sub_block->info); 5460 break; 5461 case _SOC_KT_MMU_SUBBLOCK_QSTRUCT: 5462 _soc_katana_process_sb_mmu_lvl1_parity_error(unit, 5463 QSTRUCT_INTERRUPTr, 5464 QSTRUCT_INTERRUPT_MASKr, 5465 lvl1_sub_block->info); 5466 break; 5467 5468 default: 5469 break; 5470 5471 } 5472 /* clear the MMU parity error bit */ 5473 addr = soc_reg_addr(unit, mmu_stat_reg, REG_PORT_ANY, 0); 5474 SOC_IF_ERROR_RETURN(soc_reg32_write(unit, addr, mmu_bit)); 5475 } 5476 return SOC_E_NONE; 5477 } 5478 5479 5480 5481 5482 STATIC int 5483 _soc_katana_parity_process_mxqport(int unit, uint8 id, 5484 const _soc_katana_parity_info_t *info, 5485 soc_block_t block) 5486 { 5487 soc_reg_t mxqport_reg; 5488 uint32 addr, mxqport_rval; 5489 int blk, port; 5490 char prefix_str[24]; 5491 uint32 handled_status = 0; 5492 5493 if (info->intr_status_reg == INVALIDr) { 5494 return SOC_E_NONE; 5495 } 5496 5497 port = -1; 5498 SOC_BLOCK_ITER(unit, blk, SOC_BLK_MXQPORT) { 5499 if (SOC_BLOCK_INFO(unit, blk).number == id) { 5500 port = SOC_BLOCK_PORT(unit, blk); 5501 break; 5502 } 5503 } 5504 if (port < 0) { 5505 return SOC_E_NONE; 5506 } 5507 5508 mxqport_reg = info->intr_status_reg; 5509 addr = soc_reg_addr(unit, mxqport_reg, port, 0); 5510 SOC_IF_ERROR_RETURN(soc_reg32_read(unit, addr, &mxqport_rval)); 5511 if (mxqport_rval == 0) { 5512 return SOC_E_NONE; 5513 } 5514 5515 sal_sprintf(prefix_str, "unit %d MXQPORT%d", unit, id); 5516 SOC_IF_ERROR_RETURN 5517 (_soc_katana_parity_process_info(unit, id, mxqport_reg, mxqport_rval, 5518 &handled_status, info->info, prefix_str, 5519 block)); 5520 5521 return SOC_E_NONE; 5522 } 5523 5524 STATIC int 5525 _soc_katana_parity_process_info(int unit, uint8 id, 5526 soc_reg_t group_reg, 5527 uint32 group_rval, 5528 uint32 *handled_group_rval, 5529 const _soc_katana_parity_info_t *info_list, 5530 char *prefix_str, 5531 soc_block_t block) 5532 { 5533 const _soc_katana_parity_info_t *info; 5534 int info_index; 5535 char *mem_str; 5536 5537 /* Loop through each info entry in the list */ 5538 for (info_index = 0; ; info_index++) { 5539 info = &info_list[info_index]; 5540 if (info->type == _SOC_PARITY_TYPE_NONE) { 5541 /* End of table */ 5542 break; 5543 } 5544 5545 /* Check status for the info entry in the group register */ 5546 if (!soc_reg_field_get(unit, group_reg, group_rval, 5547 info->group_reg_status_field)) { 5548 continue; 5549 } else { 5550 /* Mark this as handled */ 5551 soc_reg_field_set(unit, group_reg, handled_group_rval, 5552 info->group_reg_status_field, 1); 5553 } 5554 5555 if (info->mem_str) { 5556 mem_str = info->mem_str; 5557 } else if (info->mem != INVALIDm) { 5558 mem_str = SOC_MEM_NAME(unit, info->mem); 5559 } else { 5560 mem_str = SOC_FIELD_NAME(unit, info->group_reg_status_field); 5561 } 5562 5563 switch (info->type) { 5564 case _SOC_PARITY_TYPE_GENERIC: 5565 case _SOC_PARITY_TYPE_PARITY: 5566 case _SOC_PARITY_TYPE_HASH: 5567 case _SOC_PARITY_TYPE_COUNTER: 5568 case _SOC_PARITY_TYPE_SER: 5569 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, SOC_SWITCH_EVENT_DATA_ERROR_PARITY, 5570 info->mem, info->group_reg_status_field); 5571 break; 5572 case _SOC_PARITY_TYPE_ECC: 5573 case _SOC_PARITY_TYPE_EDATABUF: 5574 case _SOC_PARITY_TYPE_MXQPORT: 5575 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, SOC_SWITCH_EVENT_DATA_ERROR_ECC, 5576 info->mem, info->group_reg_status_field); 5577 break; 5578 default: 5579 break; 5580 } 5581 5582 /* Handle different parity error reporting style */ 5583 switch (info->type) { 5584 case _SOC_PARITY_TYPE_GENERIC: 5585 LOG_ERROR(BSL_LS_SOC_COMMON, 5586 (BSL_META_U(unit, 5587 "%s %s asserted\n"), prefix_str, mem_str)); 5588 break; 5589 case _SOC_PARITY_TYPE_PARITY: 5590 /* PARITY_ERRf, MULTIPLE_ERRf, ENTRY_IDXf */ 5591 SOC_IF_ERROR_RETURN 5592 (_soc_katana_parity_process_parity(unit, info, FALSE, 5593 prefix_str, mem_str, block)); 5594 break; 5595 case _SOC_PARITY_TYPE_ECC: 5596 /* ECC_ERRf, MULTIPLE_ERRf, DOUBLE_BIT_ERRf, ENTRY_IDXf */ 5597 SOC_IF_ERROR_RETURN 5598 (_soc_katana_parity_process_ecc(unit, info, FALSE, 5599 prefix_str, mem_str, block)); 5600 break; 5601 case _SOC_PARITY_TYPE_HASH: 5602 /* PARITY_ERR_BMf, MULTIPLE_ERRf, BUCKET_IDXf */ 5603 SOC_IF_ERROR_RETURN 5604 (_soc_katana_parity_process_hash(unit, info, FALSE, 5605 prefix_str, mem_str, block)); 5606 break; 5607 case _SOC_PARITY_TYPE_EDATABUF: 5608 /* ECC_ERR_MGRPf, ECC_ERR_2B_MGRPf, ECC_MULTI_MGRPf */ 5609 SOC_IF_ERROR_RETURN 5610 (_soc_katana_parity_process_edatabuf(unit, info, FALSE, 5611 prefix_str, mem_str)); 5612 break; 5613 case _SOC_PARITY_TYPE_COUNTER: 5614 /* PARITY_ERRf, MULTIPLE_ERRf, COUNTER_IDXf, PORT_IDX, 5615 ENTRY_IDXf */ 5616 SOC_IF_ERROR_RETURN 5617 (_soc_katana_parity_process_counter(unit, info, FALSE, 5618 prefix_str, mem_str, block)); 5619 break; 5620 case _SOC_PARITY_TYPE_MXQPORT: 5621 /* One more level of report tree structure */ 5622 SOC_IF_ERROR_RETURN 5623 (_soc_katana_parity_process_mxqport(unit, id, info, block)); 5624 break; 5625 default: 5626 break; 5627 } /* Handle different parity error reporting style */ 5628 } /* Loop through each info entry in the list */ 5629 5630 return SOC_E_NONE; 5631 } 5632 5633 STATIC int 5634 _soc_katana_parity_process_all(int unit) 5635 { 5636 const _soc_katana_parity_route_block_t *route_block; 5637 int route_block_index; 5638 soc_reg_t route_block_en_reg, route_block_reg; 5639 uint32 cmic_rval, route_block_rval, rval; 5640 uint32 addr, cmic_bit; 5641 char prefix_str[10]; 5642 5643 sal_sprintf(prefix_str, "unit %d", unit); 5644 5645 /* Read CMIC parity status register */ 5646 /* coverity[result_independent_of_operands] */ 5647 SOC_IF_ERROR_RETURN 5648 (READ_CMIC_CMC0_IRQ_STAT2r(unit, &cmic_rval)); 5649 if (cmic_rval == 0) { 5650 return SOC_E_NONE; 5651 } 5652 5653 /* Loop through each place-and-route block entry */ 5654 for (route_block_index = 0; ; route_block_index++) { 5655 route_block = &_soc_katana_parity_route_blocks[route_block_index]; 5656 cmic_bit = route_block->cmic_bit; 5657 if (cmic_bit == 0) { 5658 /* End of table */ 5659 break; 5660 } 5661 5662 /* Check status for the route block in the CMIC register */ 5663 if (!(cmic_rval & cmic_bit)) { 5664 /* No interrupt bit asserted for the route block */ 5665 continue; 5666 } 5667 5668 /* Read per route block parity status register */ 5669 route_block_reg = route_block->status_reg; 5670 route_block_en_reg = route_block->enable_reg; 5671 addr = soc_reg_addr(unit, route_block_reg, REG_PORT_ANY, 0); 5672 SOC_IF_ERROR_RETURN(soc_reg32_read(unit, addr, &route_block_rval)); 5673 if (route_block_rval == 0) { 5674 continue; 5675 } 5676 if (route_block->blocktype == SOC_BLK_MMU) { 5677 SOC_IF_ERROR_RETURN 5678 (_soc_katana_parity_process_mmu(unit, route_block_en_reg, 5679 route_block_reg, prefix_str)); 5680 } else { 5681 uint32 handled_route_block_rval = 0; 5682 SOC_IF_ERROR_RETURN 5683 (_soc_katana_parity_process_info(unit, 5684 route_block->id, 5685 route_block_reg, 5686 route_block_rval, 5687 &handled_route_block_rval, 5688 route_block->info, 5689 prefix_str, 5690 route_block->blocktype)); 5691 /* Get the current route block status value */ 5692 SOC_IF_ERROR_RETURN(soc_reg32_read(unit, addr, 5693 &route_block_rval)); 5694 /* Reset the status bits we just handled as a part of parity correction */ 5695 route_block_rval &= ~handled_route_block_rval; 5696 SOC_IF_ERROR_RETURN(soc_reg32_write(unit, addr, route_block_rval)); 5697 } 5698 } /* Loop through each place-and-route block entry */ 5699 /* Handle OAM interrupt */ 5700 if (READ_IP1_INTR_STATUS_1r(unit, &rval)) { 5701 LOG_ERROR(BSL_LS_SOC_COMMON, 5702 (BSL_META_U(unit, 5703 "unit %d: Error reading %s reg !!\n"), 5704 unit, SOC_REG_NAME(unit, IP1_INTR_STATUS_1r))); 5705 return SOC_E_INTERNAL; 5706 } 5707 /* Handle OAM interrupt */ 5708 if (rval & KT_OAM_INTR_MASK) { 5709 SOC_IF_ERROR_RETURN(soc_kt_oam_interrupt_process(unit)); 5710 } 5711 5712 return SOC_E_NONE; 5713 } 5714 5715 void 5716 soc_katana_parity_error(void *unit_vp, void *d1, void *d2, void *d3, void *d4) 5717 { 5718 int unit = PTR_TO_INT(unit_vp); 5719 5720 (void)_soc_katana_parity_process_all(unit); 5721 sal_usleep(SAL_BOOT_QUICKTURN ? 100000 : 1000); /* Don't reenable too soon */ 5722 if (d2 != NULL) { 5723 (void)soc_cmicm_intr2_enable(unit, PTR_TO_INT(d2)); 5724 } 5725 } 5726 5727 void 5728 soc_katana_oam_event_process(void *unit_vp, void *d1, void *d2, void *d3, void *d4) 5729 { 5730 int unit = PTR_TO_INT(unit_vp); 5731 uint32 rval; 5732 /* Handle OAM interrupt */ 5733 if (READ_IP1_INTR_STATUS_1r(unit, &rval) == SOC_E_NONE) { 5734 /* Handle OAM interrupt */ 5735 if (rval & KT_OAM_INTR_MASK) { 5736 (void) soc_kt_oam_interrupt_process(unit); 5737 } 5738 } else { 5739 LOG_ERROR(BSL_LS_SOC_COMMON, 5740 (BSL_META_U(unit, 5741 "unit %d: Error reading %s reg !!\n"), 5742 unit, SOC_REG_NAME(unit, IP1_INTR_STATUS_1r))); 5743 } 5744 5745 sal_usleep(SAL_BOOT_QUICKTURN ? 100000 : 1000); /* Don't reenable too soon */ 5746 if (d2 != NULL) { 5747 (void)soc_cmicm_intr2_enable(unit, PTR_TO_INT(d2)); 5748 } 5749 } 5750 5751 5752 STATIC int 5753 _soc_katana_mem_nack_process_info(int unit, int reg_mem, 5754 _kt_ser_nack_reg_mem_t nack_reg_mem, 5755 soc_block_t block, 5756 const _soc_katana_parity_info_t *info_list, 5757 char *prefix_str) 5758 { 5759 const _soc_katana_parity_info_t *info; 5760 int info_index; 5761 char *mem_str; 5762 5763 /* Loop through each info entry in the list */ 5764 for (info_index = 0; ; info_index++) { 5765 info = &info_list[info_index]; 5766 if (info->type == _SOC_PARITY_TYPE_NONE) { 5767 /* End of table */ 5768 break; 5769 } 5770 if (reg_mem == _SOC_KT_SER_MEM && info->mem != nack_reg_mem.mem) { 5771 continue; 5772 } 5773 if (info->mem_str) { 5774 mem_str = info->mem_str; 5775 } else { 5776 mem_str = SOC_MEM_NAME(unit, info->mem); 5777 } 5778 5779 if (reg_mem == _SOC_KT_SER_REG && info->type != _SOC_PARITY_TYPE_COUNTER) { 5780 continue; 5781 } 5782 5783 /* Handle different parity error reporting style */ 5784 switch (info->type) { 5785 case _SOC_PARITY_TYPE_PARITY: 5786 /* PARITY_ERRf, MULTIPLE_ERRf, ENTRY_IDXf */ 5787 SOC_IF_ERROR_RETURN 5788 (_soc_katana_parity_process_parity(unit, info, TRUE, 5789 prefix_str, mem_str, block)); 5790 break; 5791 case _SOC_PARITY_TYPE_ECC: 5792 /* ECC_ERRf, MULTIPLE_ERRf, DOUBLE_BIT_ERRf, ENTRY_IDXf */ 5793 SOC_IF_ERROR_RETURN 5794 (_soc_katana_parity_process_ecc(unit, info, TRUE, 5795 prefix_str, mem_str, block)); 5796 break; 5797 case _SOC_PARITY_TYPE_HASH: 5798 /* PARITY_ERR_BMf, MULTIPLE_ERRf, BUCKET_IDXf */ 5799 SOC_IF_ERROR_RETURN 5800 (_soc_katana_parity_process_hash(unit, info, TRUE, 5801 prefix_str, mem_str, block)); 5802 break; 5803 case _SOC_PARITY_TYPE_EDATABUF: 5804 /* ECC_ERR_MGRPf, ECC_ERR_2B_MGRPf, ECC_MULTI_MGRPf */ 5805 SOC_IF_ERROR_RETURN 5806 (_soc_katana_parity_process_edatabuf(unit, info, TRUE, 5807 prefix_str, mem_str)); 5808 break; 5809 case _SOC_PARITY_TYPE_COUNTER: 5810 /* PARITY_ERRf, MULTIPLE_ERRf, COUNTER_IDXf, PORT_IDX, 5811 ENTRY_IDXf */ 5812 SOC_IF_ERROR_RETURN 5813 (_soc_katana_parity_process_counter(unit, info, TRUE, 5814 prefix_str, mem_str, block)); 5815 break; 5816 default: 5817 break; 5818 } /* Handle different parity error reporting style */ 5819 } /* Loop through each info entry in the list */ 5820 5821 return SOC_E_NONE; 5822 } 5823 5824 5825 STATIC int 5826 _soc_katana_mem_nack_error_process(int unit, 5827 _kt_ser_nack_reg_mem_t nack_reg_mem, 5828 soc_block_t block, 5829 int reg_mem) 5830 { 5831 const _soc_katana_parity_route_block_t *route_block; 5832 int route_block_index; 5833 uint32 cmic_bit; 5834 char prefix_str[10]; 5835 5836 sal_sprintf(prefix_str, "unit %d", unit); 5837 5838 /* Loop through each place-and-route block entry */ 5839 for (route_block_index = 0; ; route_block_index++) { 5840 route_block = &_soc_katana_parity_route_blocks[route_block_index]; 5841 cmic_bit = route_block->cmic_bit; 5842 if (cmic_bit == 0) { 5843 /* End of table */ 5844 break; 5845 } 5846 5847 if (route_block->info == NULL) { 5848 continue; 5849 } 5850 SOC_IF_ERROR_RETURN 5851 (_soc_katana_mem_nack_process_info(unit, 5852 reg_mem, nack_reg_mem, block, 5853 route_block->info, 5854 prefix_str)); 5855 } /* Loop through each place-and-route block entry */ 5856 5857 return SOC_E_NONE; 5858 } 5859 5860 void 5861 soc_katana_stat_nack(int unit, int *fixed) 5862 { 5863 int rv; 5864 _kt_ser_nack_reg_mem_t nack_reg_mem; 5865 5866 nack_reg_mem.mem = -1; 5867 nack_reg_mem.reg = -1; 5868 _stat_error_fixed[unit] = 0; 5869 5870 if ((rv = _soc_katana_mem_nack_error_process(unit, nack_reg_mem, 0, 5871 _SOC_KT_SER_REG)) < 0) { 5872 LOG_ERROR(BSL_LS_SOC_COMMON, 5873 (BSL_META_U(unit, 5874 "unit %d STAT SCHAN NACK analysis failure.\n"), unit)); 5875 } 5876 *fixed = _stat_error_fixed[unit]; 5877 } 5878 5879 void 5880 soc_katana_mem_nack(void *unit_vp, void *addr_vp, void *blk_vp, 5881 void *d3, void *d4) 5882 { 5883 soc_mem_t mem = INVALIDm; 5884 int reg_mem = PTR_TO_INT(d3); 5885 int rv, unit = PTR_TO_INT(unit_vp); 5886 uint32 address = PTR_TO_INT(addr_vp); 5887 uint32 block = PTR_TO_INT(blk_vp); 5888 uint32 offset = 0, min_addr = 0, max_addr = 0; 5889 soc_regaddrinfo_t ainfo; 5890 _kt_ser_nack_reg_mem_t nack_reg_mem; 5891 5892 nack_reg_mem.reg = INVALIDr; 5893 nack_reg_mem.mem = INVALIDm; 5894 5895 if (reg_mem == _SOC_KT_SER_REG) { 5896 if (address) { 5897 soc_regaddrinfo_get(unit, &ainfo, address); 5898 nack_reg_mem.reg = ainfo.reg; 5899 } 5900 } else { 5901 offset = address & ~0xC0f00000; /* Strip block ID */ 5902 mem = soc_addr_to_mem(unit, address, &block); 5903 if (mem == INVALIDm) { 5904 LOG_ERROR(BSL_LS_SOC_COMMON, 5905 (BSL_META_U(unit, 5906 "unit %d mem decode failed, " 5907 "SCHAN NACK analysis failure\n"), unit)); 5908 return; 5909 } 5910 5911 _soc_katana_mem_rename(&mem); 5912 nack_reg_mem.mem = mem; 5913 5914 min_addr = max_addr = SOC_MEM_INFO(unit, mem).base; 5915 min_addr += SOC_MEM_INFO(unit, mem).index_min; 5916 max_addr += SOC_MEM_INFO(unit, mem).index_max; 5917 } 5918 5919 if ((rv = _soc_katana_mem_nack_error_process(unit, nack_reg_mem, block, 5920 reg_mem)) < 0) { 5921 if (reg_mem == _SOC_KT_SER_REG) { 5922 LOG_ERROR(BSL_LS_SOC_COMMON, 5923 (BSL_META_U(unit, 5924 "unit %d REG SCHAN NACK analysis failure\n"), 5925 unit)); 5926 } else { 5927 LOG_ERROR(BSL_LS_SOC_COMMON, 5928 (BSL_META_U(unit, 5929 "unit %d %s entry %d SCHAN NACK analysis failure\n"), 5930 unit, SOC_MEM_NAME(unit, mem), 5931 min_addr - offset)); 5932 } 5933 } 5934 if (reg_mem == _SOC_KT_SER_REG) { 5935 LOG_ERROR(BSL_LS_SOC_COMMON, 5936 (BSL_META_U(unit, 5937 "unit %d REG SCHAN NACK analysis\n"), 5938 unit)); 5939 } else { 5940 LOG_INFO(BSL_LS_SOC_SCHAN, 5941 (BSL_META_U(unit, 5942 "unit %d %s entry %d SCHAN NACK analysis\n"), 5943 unit, SOC_MEM_NAME(unit, mem), 5944 min_addr - offset)); 5945 } 5946 } 5947 5948 /* SER processing for TCAMs */ 5949 STATIC _soc_ser_parity_info_t _soc_kt_ser_parity_info_template[] = { 5950 { EFP_TCAMm, _SOC_SER_PARITY_MODE_2BITS, 5951 CMIC_SER_START_ADDR_0r, CMIC_SER_END_ADDR_0r, 5952 CMIC_SER_MEM_ADDR_0r, CMIC_SER_PARITY_MODE_SEL_15_0r, 5953 RANGE_0_PARITY_BITSf, 430, CMIC_SER_RANGE0_DATAENTRY_LENr, 0, 0, 0, 5954 _SOC_SER_FLAG_XY_READ}, 5955 { VFP_TCAMm, _SOC_SER_PARITY_MODE_2BITS, 5956 CMIC_SER_START_ADDR_1r, CMIC_SER_END_ADDR_1r, 5957 CMIC_SER_MEM_ADDR_1r, CMIC_SER_PARITY_MODE_SEL_15_0r, 5958 RANGE_1_PARITY_BITSf, 470, CMIC_SER_RANGE1_DATAENTRY_LENr, 0, 0, 0, 5959 _SOC_SER_FLAG_XY_READ}, 5960 { FP_UDF_TCAMm, _SOC_SER_PARITY_MODE_2BITS, 5961 CMIC_SER_START_ADDR_2r, CMIC_SER_END_ADDR_2r, 5962 CMIC_SER_MEM_ADDR_2r, CMIC_SER_PARITY_MODE_SEL_15_0r, 5963 RANGE_2_PARITY_BITSf, 139, CMIC_SER_RANGE2_DATAENTRY_LENr, 0, 0, 0, 5964 _SOC_SER_FLAG_XY_READ}, 5965 { CPU_COS_MAPm, _SOC_SER_PARITY_MODE_2BITS, 5966 CMIC_SER_START_ADDR_3r, CMIC_SER_END_ADDR_3r, 5967 CMIC_SER_MEM_ADDR_3r, CMIC_SER_PARITY_MODE_SEL_15_0r, 5968 RANGE_3_PARITY_BITSf, 288, CMIC_SER_RANGE3_DATAENTRY_LENr, 0, 0, 0, 5969 _SOC_SER_FLAG_XY_READ}, 5970 { L3_TUNNELm, _SOC_SER_PARITY_MODE_2BITS, 5971 CMIC_SER_START_ADDR_4r, CMIC_SER_END_ADDR_4r, 5972 CMIC_SER_MEM_ADDR_4r, CMIC_SER_PARITY_MODE_SEL_15_0r, 5973 RANGE_4_PARITY_BITSf, 211, CMIC_SER_RANGE4_DATAENTRY_LENr, 0, 0, 0, 5974 _SOC_SER_FLAG_XY_READ}, 5975 { VLAN_SUBNETm, _SOC_SER_PARITY_MODE_2BITS, 5976 CMIC_SER_START_ADDR_5r, CMIC_SER_END_ADDR_5r, 5977 CMIC_SER_MEM_ADDR_5r, CMIC_SER_PARITY_MODE_SEL_15_0r, 5978 RANGE_5_PARITY_BITSf, 129, CMIC_SER_RANGE5_DATAENTRY_LENr, 0, 0, 0, 5979 _SOC_SER_FLAG_XY_READ}, 5980 { MY_STATION_TCAMm, _SOC_SER_PARITY_MODE_2BITS, 5981 CMIC_SER_START_ADDR_6r, CMIC_SER_END_ADDR_6r, 5982 CMIC_SER_MEM_ADDR_6r, CMIC_SER_PARITY_MODE_SEL_15_0r, 5983 RANGE_6_PARITY_BITSf, 161, CMIC_SER_RANGE6_DATAENTRY_LENr, 0, 0, 0, 5984 _SOC_SER_FLAG_XY_READ}, 5985 { L3_DEFIPm, _SOC_SER_PARITY_MODE_2BITS, 5986 CMIC_SER_START_ADDR_7r, CMIC_SER_END_ADDR_7r, 5987 CMIC_SER_MEM_ADDR_7r, CMIC_SER_PARITY_MODE_SEL_15_0r, 5988 RANGE_7_PARITY_BITSf, 190, CMIC_SER_RANGE7_DATAENTRY_LENr, 0, 0, 0, 5989 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_SIZE_VERIFY | 5990 _SOC_SER_FLAG_NO_DMA | _SOC_SER_FLAG_REMAP_READ}, 5991 { L3_DEFIP_PAIR_128m, _SOC_SER_PARITY_MODE_2BITS, 5992 CMIC_SER_START_ADDR_8r, CMIC_SER_END_ADDR_8r, 5993 CMIC_SER_MEM_ADDR_8r, CMIC_SER_PARITY_MODE_SEL_15_0r, 5994 RANGE_8_PARITY_BITSf, 380, CMIC_SER_RANGE8_DATAENTRY_LENr, 0, 0, 0, 5995 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_SIZE_VERIFY | 5996 _SOC_SER_FLAG_NO_DMA | _SOC_SER_FLAG_REMAP_READ}, 5997 { L2_USER_ENTRYm, _SOC_SER_PARITY_MODE_2BITS, 5998 CMIC_SER_START_ADDR_9r, CMIC_SER_END_ADDR_9r, 5999 CMIC_SER_MEM_ADDR_9r, CMIC_SER_PARITY_MODE_SEL_15_0r, 6000 RANGE_9_PARITY_BITSf, 123, CMIC_SER_RANGE9_DATAENTRY_LENr, 0, 0, 0, 6001 _SOC_SER_FLAG_XY_READ}, 6002 { FP_GLOBAL_MASK_TCAMm, _SOC_SER_PARITY_MODE_2BITS, 6003 CMIC_SER_START_ADDR_10r, CMIC_SER_END_ADDR_10r, 6004 CMIC_SER_MEM_ADDR_10r, CMIC_SER_PARITY_MODE_SEL_15_0r, 6005 RANGE_10_PARITY_BITSf, 81, CMIC_SER_RANGE10_DATAENTRY_LENr, 0, 0, 0, 6006 _SOC_SER_FLAG_XY_READ}, 6007 { FP_TCAMm, _SOC_SER_PARITY_MODE_2BITS, 6008 CMIC_SER_START_ADDR_11r, CMIC_SER_END_ADDR_11r, 6009 CMIC_SER_MEM_ADDR_11r, CMIC_SER_PARITY_MODE_SEL_15_0r, 6010 RANGE_11_PARITY_BITSf, 470, CMIC_SER_RANGE11_DATAENTRY_LENr, 0, 0, 0, 6011 _SOC_SER_FLAG_XY_READ}, 6012 { INVALIDm, _SOC_SER_PARITY_MODE_NUM}, 6013 }; 6014 6015 static _soc_ser_parity_info_t *_soc_kt_ser_parity_info[SOC_MAX_NUM_DEVICES]; 6016 6017 #define SOC_KT_SER_MEM_AVAILABLE (2048 * 32) /* bits */ 6018 6019 STATIC int 6020 _soc_katana_ser_init(int unit) 6021 { 6022 int alloc_size; 6023 6024 /* First, make per-unit copy of the master TCAM list */ 6025 alloc_size = sizeof(_soc_kt_ser_parity_info_template); 6026 if (NULL == _soc_kt_ser_parity_info[unit]) { 6027 if ((_soc_kt_ser_parity_info[unit] = 6028 sal_alloc(alloc_size, "kt tcam list")) == NULL) { 6029 return SOC_E_MEMORY; 6030 } 6031 } 6032 /* Make a fresh copy of the TCAM template info */ 6033 sal_memcpy(_soc_kt_ser_parity_info[unit], 6034 &(_soc_kt_ser_parity_info_template), 6035 alloc_size); 6036 return soc_ser_init(unit, _soc_kt_ser_parity_info[unit], 6037 SOC_KT_SER_MEM_AVAILABLE); 6038 } 6039 6040 int 6041 soc_katana_ser_mem_clear(int unit, soc_mem_t mem) 6042 { 6043 return soc_ser_mem_clear(unit, _soc_kt_ser_parity_info[unit], mem); 6044 } 6045 6046 void 6047 soc_katana_ser_fail(int unit) 6048 6049 { 6050 soc_process_ser_parity_error(unit, _soc_kt_ser_parity_info[unit], 6051 _SOC_PARITY_TYPE_SER); 6052 return; 6053 } 6054 6055 int 6056 soc_katana_pipe_mem_clear(int unit) 6057 { 6058 uint32 rval; 6059 int index, pipe_init_usec; 6060 soc_timeout_t to; 6061 static const soc_mem_t cam[] = { 6062 EFP_TCAMm, 6063 VFP_TCAMm, 6064 FP_UDF_TCAMm, 6065 CPU_COS_MAPm, 6066 L3_TUNNELm, 6067 VLAN_SUBNETm, 6068 MY_STATION_TCAMm, 6069 L3_DEFIPm, 6070 L3_DEFIP_PAIR_128m, 6071 L2_USER_ENTRYm, 6072 FP_GLOBAL_MASK_TCAMm, 6073 FP_TCAMm 6074 }; 6075 6076 /* 6077 * Reset the IPIPE and EPIPE block 6078 */ 6079 rval = 0; 6080 SOC_IF_ERROR_RETURN(WRITE_ING_HW_RESET_CONTROL_1r(unit, rval)); 6081 soc_reg_field_set(unit, ING_HW_RESET_CONTROL_2r, &rval, RESET_ALLf, 1); 6082 soc_reg_field_set(unit, ING_HW_RESET_CONTROL_2r, &rval, VALIDf, 1); 6083 /* Set count to # entries in largest IPIPE table (L2X) */ 6084 soc_reg_field_set(unit, ING_HW_RESET_CONTROL_2r, &rval, COUNTf, 32768); 6085 SOC_IF_ERROR_RETURN(WRITE_ING_HW_RESET_CONTROL_2r(unit, rval)); 6086 6087 rval = 0; 6088 SOC_IF_ERROR_RETURN(WRITE_EGR_HW_RESET_CONTROL_0r(unit, rval)); 6089 soc_reg_field_set(unit, EGR_HW_RESET_CONTROL_1r, &rval, RESET_ALLf, 1); 6090 soc_reg_field_set(unit, EGR_HW_RESET_CONTROL_1r, &rval, VALIDf, 1); 6091 /* Set count to # entries in largest EPIPE table (EGR_VLAN_XLATE) */ 6092 soc_reg_field_set(unit, EGR_HW_RESET_CONTROL_1r, &rval, COUNTf, 16384); 6093 SOC_IF_ERROR_RETURN(WRITE_EGR_HW_RESET_CONTROL_1r(unit, rval)); 6094 6095 /* For simulation, set timeout to 10 sec. Otherwise, timeout = 50 ms */ 6096 if (SAL_BOOT_SIMULATION) { 6097 pipe_init_usec = 10000000; 6098 } else { 6099 pipe_init_usec = 50000; 6100 } 6101 soc_timeout_init(&to, pipe_init_usec, 0); 6102 6103 /* Wait for IPIPE memory initialization done. */ 6104 do { 6105 SOC_IF_ERROR_RETURN(READ_ING_HW_RESET_CONTROL_2r(unit, &rval)); 6106 if (soc_reg_field_get(unit, ING_HW_RESET_CONTROL_2r, rval, DONEf)) { 6107 break; 6108 } 6109 if (soc_timeout_check(&to)) { 6110 LOG_WARN(BSL_LS_SOC_COMMON, 6111 (BSL_META_U(unit, 6112 "unit %d : ING_HW_RESET timeout\n"), unit)); 6113 break; 6114 } 6115 } while (TRUE); 6116 6117 /* Wait for EPIPE memory initialization done. */ 6118 do { 6119 SOC_IF_ERROR_RETURN(READ_EGR_HW_RESET_CONTROL_1r(unit, &rval)); 6120 if (soc_reg_field_get(unit, EGR_HW_RESET_CONTROL_1r, rval, DONEf)) { 6121 break; 6122 } 6123 if (soc_timeout_check(&to)) { 6124 LOG_WARN(BSL_LS_SOC_COMMON, 6125 (BSL_META_U(unit, 6126 "unit %d : EGR_HW_RESET timeout\n"), unit)); 6127 break; 6128 } 6129 } while (TRUE); 6130 6131 SOC_IF_ERROR_RETURN(READ_ING_HW_RESET_CONTROL_2r(unit, &rval)); 6132 soc_reg_field_set(unit, ING_HW_RESET_CONTROL_2r, &rval, RESET_ALLf, 0); 6133 soc_reg_field_set(unit, ING_HW_RESET_CONTROL_2r, &rval, CMIC_REQ_ENABLEf, 1); 6134 SOC_IF_ERROR_RETURN(WRITE_ING_HW_RESET_CONTROL_2r(unit, rval)); 6135 6136 SOC_IF_ERROR_RETURN(READ_EGR_HW_RESET_CONTROL_1r(unit, &rval)); 6137 soc_reg_field_set(unit, EGR_HW_RESET_CONTROL_1r, &rval, RESET_ALLf, 0); 6138 SOC_IF_ERROR_RETURN(WRITE_EGR_HW_RESET_CONTROL_1r(unit, rval)); 6139 6140 for (index = 0; index < sizeof(cam) / sizeof(soc_mem_t); index++) { 6141 SOC_IF_ERROR_RETURN(soc_mem_clear(unit, cam[index], COPYNO_ALL, TRUE)); 6142 } 6143 return SOC_E_NONE; 6144 } 6145 6146 /* 6147 * cpu port (mmu port 0): 48 queues (0-47) 6148 * loopback port (mmu port 35): 8 queues (0-7) 6149 * hg ports : 24 queues 6150 * other ports : 8 queues, vlan levels : 64 6151 */ 6152 6153 int 6154 soc_katana_num_cosq_init(int unit) 6155 { 6156 soc_info_t *si; 6157 int port, prev_port, vlan_queue_enable = 0; 6158 int num_base_queues = 0; 6159 6160 si = &SOC_INFO(unit); 6161 prev_port = 0; 6162 6163 PBMP_ALL_ITER(unit, port) { 6164 6165 si->port_num_ext_cosq[port] = 0; 6166 si->port_num_cosq[port] = 0; 6167 /* Supports max 8 ports for vlan queues */ 6168 vlan_queue_enable = 6169 soc_property_port_get(unit, port, spn_VLAN_QUEUE_ENABLE, 0); 6170 6171 if (vlan_queue_enable != 0) { 6172 si->port_num_ext_cosq[port] = soc_property_get(unit, 6173 spn_VLAN_QUEUE_LEVELS_MAX, 32); 6174 if (si->port_num_ext_cosq[port] > 64) { 6175 si->port_num_ext_cosq[port] = 64; 6176 } 6177 } 6178 if (IS_CPU_PORT(unit, port)) { 6179 si->port_cosq_base[port] = 0; 6180 si->port_uc_cosq_base[port] = 0; 6181 si->port_num_uc_cosq[port] = 48; 6182 si->port_num_ext_cosq[port] = 0; 6183 } else { 6184 si->port_cosq_base[port] = si->port_cosq_base[prev_port] + 6185 si->port_num_uc_cosq[prev_port]; 6186 si->port_uc_cosq_base[port] = si->port_cosq_base[port]; 6187 if (IS_HG_PORT(unit, port)) { 6188 si->port_num_uc_cosq[port] = 6189 (si->port_num_ext_cosq[port] < 24) ? \ 6190 24 : si->port_num_ext_cosq[port]; 6191 } else { 6192 si->port_num_uc_cosq[port] = 6193 (si->port_num_ext_cosq[port] < 8) ? \ 6194 8 : si->port_num_ext_cosq[port]; 6195 } 6196 } 6197 prev_port = port; 6198 num_base_queues += si->port_num_uc_cosq[port]; 6199 6200 if (num_base_queues > KATANA_BASE_QUEUES_MAX) { 6201 LOG_ERROR(BSL_LS_SOC_COMMON, 6202 (BSL_META_U(unit, 6203 "Base queue allocation failed: num_queues %d \n"), 6204 num_base_queues)); 6205 return SOC_E_PARAM; 6206 } 6207 6208 if (bsl_check(bslLayerSoc, bslSourceCommon, bslSeverityVerbose, unit)) { 6209 LOG_CLI((BSL_META_U(unit, 6210 "\nport num %d cosq_base %d num_cosq %d"), 6211 port, si->port_cosq_base[port], 6212 si->port_num_uc_cosq[port])); 6213 } 6214 } 6215 si->num_mmu_base_cosq = num_base_queues; 6216 6217 return SOC_E_NONE; 6218 } 6219 6220 STATIC int 6221 _soc_katana_shaper_rate_info_dealloc(int unit) 6222 { 6223 int rv = SOC_E_NONE; 6224 6225 if (shaper_info[unit] == NULL) { 6226 return(rv); 6227 } 6228 if (shaper_info[unit]->basic_rate_info != NULL) { 6229 sal_free(shaper_info[unit]->basic_rate_info); 6230 } 6231 if (shaper_info[unit]->burst_size_info != NULL) { 6232 sal_free(shaper_info[unit]->burst_size_info); 6233 } 6234 sal_free(shaper_info[unit]); 6235 6236 return(rv); 6237 } 6238 6239 STATIC int 6240 _soc_katana_shaper_rate_info_alloc(int unit) 6241 { 6242 int rv = SOC_E_NONE; 6243 uint32 exponent, mantissa, denominator = 1; 6244 uint64 numerator; 6245 uint32 uRate = 0; 6246 int i, temp; 6247 6248 /* allocate shaper info */ 6249 shaper_info[unit] = sal_alloc(sizeof(katanaShaperInfo_t), 6250 "Katana_Shaper"); 6251 if (shaper_info[unit] == NULL) { 6252 return(SOC_E_MEMORY); 6253 } 6254 sal_memset(shaper_info[unit], 0, sizeof(katanaShaperInfo_t)); 6255 6256 /* allocate rate info */ 6257 shaper_info[unit]->basic_rate_info = sal_alloc( 6258 sizeof(katanaRateInfo_t) * (KATANA_SHAPER_RATE_MAX_EXPONENT + 1), 6259 "Katana_Rate"); 6260 if (shaper_info[unit]->basic_rate_info == NULL) { 6261 rv = SOC_E_MEMORY; 6262 goto err; 6263 } 6264 6265 /* allocate burst info */ 6266 shaper_info[unit]->burst_size_info = sal_alloc( 6267 sizeof(katanaRateInfo_t) * (KATANA_SHAPER_BURST_MAX_EXPONENT + 1), 6268 "Katana_Burst"); 6269 if (shaper_info[unit]->burst_size_info == NULL) { 6270 rv = SOC_E_MEMORY; 6271 goto err; 6272 } 6273 6274 /* initialize rate info */ 6275 for (i = 0, mantissa = KATANA_SHAPER_RATE_MIN_MANTISSA; 6276 mantissa <= KATANA_SHAPER_RATE_MIN_MANTISSA; mantissa++) { 6277 for (exponent = KATANA_SHAPER_RATE_MIN_EXPONENT; 6278 exponent <= KATANA_SHAPER_RATE_MAX_EXPONENT; exponent++) { 6279 if (exponent == 0) { 6280 /* (2^r_e+4) * (r_m/1024) / ref_cycle based on 7.8125uS(128KHz) */ 6281 COMPILER_64_ZERO(numerator); 6282 } else { 6283 /* (2^(r_e+3)) * (1+(r_m / 1024)) / ref_cycle 6284 r_m = 0 => (1 << exponent + 3 + 7) */ 6285 6286 COMPILER_64_SET(numerator, 0, 1); 6287 temp = exponent + 10 + 10; 6288 COMPILER_64_SHL(numerator, temp); 6289 } 6290 6291 denominator = 1024; 6292 6293 if (soc_esw_div64(numerator, denominator, &uRate) == -1) { 6294 rv = SOC_E_INTERNAL; 6295 goto err; 6296 } 6297 /* the rate is stored in kbps */ 6298 shaper_info[unit]->basic_rate_info[i].rate = uRate; 6299 shaper_info[unit]->basic_rate_info[i].exponent = exponent; 6300 shaper_info[unit]->basic_rate_info[i].mantissa = mantissa; 6301 i++; 6302 } 6303 } 6304 6305 /* initialize burst info */ 6306 for (i = 0, mantissa = KATANA_SHAPER_BURST_MIN_MANTISSA; 6307 mantissa <= KATANA_SHAPER_BURST_MIN_MANTISSA; mantissa++) { 6308 for (exponent = KATANA_SHAPER_BURST_MIN_EXPONENT; 6309 exponent <= KATANA_SHAPER_BURST_MAX_EXPONENT; exponent++) { 6310 6311 /* rate = 2^(t_e+9) * (1+(t_m/128)) */ 6312 shaper_info[unit]->burst_size_info[i].rate = (1 << (exponent + 9)); 6313 shaper_info[unit]->burst_size_info[i].exponent = exponent; 6314 shaper_info[unit]->burst_size_info[i].mantissa = mantissa; 6315 i++; 6316 } 6317 } 6318 6319 return(rv); 6320 6321 err: 6322 _soc_katana_shaper_rate_info_dealloc(unit); 6323 return(rv); 6324 } 6325 6326 STATIC int 6327 _soc_katana_get_shaper_rate(int unit, uint32 rate, int *index, 6328 uint32 *rate_mantissa, uint32 *rate_exponent) 6329 { 6330 int rv = SOC_E_NONE; 6331 int i; 6332 int delta_rate_diff = 0; 6333 uint32 last_mantissa = -1, last_exponent = -1, cur_mantissa = -1, cur_exponent; 6334 uint32 last_rate_diff = -1, cur_rate_diff; 6335 6336 if (rate < 2) { 6337 *index = 0; 6338 /* set minimum granularity of 2kbps for non zero rate */ 6339 *rate_mantissa = (rate != 0) ? 1 : 0; 6340 *rate_exponent = 0; 6341 return rv; 6342 } 6343 /* As basic rate is stored in 32-bit kbps, diff will be in 32-bit */ 6344 for (i = 0; i < (KATANA_SHAPER_RATE_MAX_EXPONENT + 1); i++) { 6345 cur_exponent = shaper_info[unit]->basic_rate_info[i].exponent; 6346 if (cur_exponent == 0) { 6347 cur_mantissa = (rate - shaper_info[unit]->basic_rate_info[i].rate) / 6348 (1 << (cur_exponent + 1)); 6349 } else { 6350 cur_mantissa = (rate - shaper_info[unit]->basic_rate_info[i].rate) / 6351 (1 << cur_exponent); 6352 } 6353 if (cur_mantissa > KATANA_SHAPER_RATE_MAX_MANTISSA) { 6354 continue; 6355 } 6356 6357 if (cur_exponent == 0) { 6358 cur_rate_diff = rate - (shaper_info[unit]->basic_rate_info[i].rate + 6359 (cur_mantissa * (1 << (cur_exponent+1)))); 6360 } else { 6361 cur_rate_diff = rate - (shaper_info[unit]->basic_rate_info[i].rate + 6362 (cur_mantissa * (1 << cur_exponent))); 6363 } 6364 6365 if (last_mantissa == -1) { 6366 last_mantissa = cur_mantissa; 6367 last_exponent = cur_exponent; 6368 last_rate_diff = cur_rate_diff; 6369 } 6370 else if (cur_rate_diff < last_rate_diff) { 6371 last_mantissa = cur_mantissa; 6372 last_exponent = cur_exponent; 6373 last_rate_diff = cur_rate_diff; 6374 } 6375 6376 if (cur_rate_diff == 0) { 6377 break; 6378 } 6379 } 6380 if (last_mantissa == -1) { 6381 rv = SOC_E_PARAM; 6382 LOG_ERROR(BSL_LS_SOC_COMMON, 6383 (BSL_META_U(unit, 6384 "unit %d Ingress Shaper Rate not found\n"), unit)); 6385 return(rv); 6386 } 6387 else { 6388 /* Compute the delta rate between requested rate and hw rate. */ 6389 if (last_exponent == 0) { 6390 delta_rate_diff = rate - (shaper_info[unit]-> 6391 basic_rate_info[last_exponent].rate + 6392 (last_mantissa * (1 << (last_exponent+1)))); 6393 } else { 6394 delta_rate_diff = rate - (shaper_info[unit]-> 6395 basic_rate_info[last_exponent].rate + 6396 (last_mantissa * (1 << last_exponent))); 6397 } 6398 6399 /* If the delta rate is +ve then only adjust the rate to next higher slot */ 6400 if (delta_rate_diff > 0) { 6401 if ((last_mantissa == KATANA_SHAPER_RATE_MAX_MANTISSA) && 6402 (last_exponent != KATANA_SHAPER_RATE_MAX_EXPONENT)) { 6403 /* Mantissa is at its max, move to next EXPONENT */ 6404 /* provided we are not at max rate already */ 6405 last_mantissa = 0; 6406 last_exponent++; 6407 } else if (last_mantissa != KATANA_SHAPER_RATE_MAX_MANTISSA) { 6408 /* Move the mantissa to next higher slot */ 6409 last_mantissa++; 6410 } 6411 } 6412 6413 (*index) = i; 6414 (*rate_mantissa) = last_mantissa; 6415 (*rate_exponent) = last_exponent; 6416 LOG_VERBOSE(BSL_LS_SOC_COMMON, 6417 (BSL_META_U(unit, 6418 "Closest Rate: %d Kbps, mantissa: %d, exponent: %d\n"), 6419 rate, last_mantissa, last_exponent)); 6420 } 6421 6422 return(rv); 6423 } 6424 6425 STATIC int 6426 _soc_katana_get_shaper_burst_size(int unit, uint32 rate, 6427 uint32 *burst_mantissa, uint32 *burst_exponent) 6428 { 6429 int rv = SOC_E_NONE; 6430 int i; 6431 int delta_rate_diff = 0; 6432 uint32 last_mantissa = -1, last_exponent = -1, cur_mantissa = -1, cur_exponent; 6433 uint32 last_rate_diff = -1, cur_rate_diff; 6434 6435 LOG_VERBOSE(BSL_LS_SOC_COMMON, 6436 (BSL_META_U(unit, 6437 "\n\nCalculating default burst size, rate: %d\n"), (unsigned int)rate)); 6438 6439 if (rate == 0) { 6440 *burst_mantissa = 0; 6441 *burst_exponent = 0; 6442 return rv; 6443 } 6444 6445 for (i = 0; i < (KATANA_SHAPER_BURST_MAX_EXPONENT + 1); i++) { 6446 cur_exponent = shaper_info[unit]->burst_size_info[i].exponent; 6447 6448 if (shaper_info[unit]->burst_size_info[i].rate <= rate) { 6449 cur_mantissa = (rate - shaper_info[unit]->burst_size_info[i].rate) / 6450 (1 << (cur_exponent + 2)); 6451 } else { 6452 break; 6453 } 6454 6455 if (cur_mantissa > KATANA_SHAPER_BURST_MAX_MANTISSA) { 6456 continue; 6457 } 6458 6459 cur_rate_diff = rate - (shaper_info[unit]->burst_size_info[i].rate + 6460 (cur_mantissa * (1 << (cur_exponent + 2)))); 6461 6462 if (last_mantissa == -1) { 6463 last_mantissa = cur_mantissa; 6464 last_exponent = cur_exponent; 6465 last_rate_diff = cur_rate_diff; 6466 } 6467 else if (cur_rate_diff < last_rate_diff) { 6468 last_mantissa = cur_mantissa; 6469 last_exponent = cur_exponent; 6470 last_rate_diff = cur_rate_diff; 6471 } 6472 6473 if (cur_rate_diff == 0) { 6474 break; 6475 } 6476 } 6477 if (last_mantissa == -1) { 6478 rv = SOC_E_PARAM; 6479 LOG_ERROR(BSL_LS_SOC_COMMON, 6480 (BSL_META_U(unit, 6481 "unit %d Ingress Burst Size not found\n"), unit)); 6482 return(rv); 6483 } 6484 else { 6485 /* Compute the delta rate between requested rate and hw rate. */ 6486 delta_rate_diff = rate - (shaper_info[unit]-> 6487 burst_size_info[last_exponent].rate + 6488 (last_mantissa * (1 << (last_exponent + 2)))); 6489 6490 /* If the delta rate is +ve then only adjust the rate to next higher slot */ 6491 if (delta_rate_diff > 0) { 6492 if ((last_mantissa == KATANA_SHAPER_BURST_MAX_MANTISSA) && 6493 (last_exponent != KATANA_SHAPER_BURST_MAX_EXPONENT)) { 6494 /* Mantissa is at its max, move to next EXPONENT */ 6495 /* provided we are not at max rate already */ 6496 last_mantissa = 0; 6497 last_exponent++; 6498 } else if (last_mantissa != KATANA_SHAPER_BURST_MAX_MANTISSA) { 6499 /* Move the mantissa to next higher slot */ 6500 last_mantissa++; 6501 } 6502 } 6503 6504 (*burst_mantissa) = last_mantissa; 6505 (*burst_exponent) = last_exponent; 6506 6507 LOG_VERBOSE(BSL_LS_SOC_COMMON, 6508 (BSL_META_U(unit, 6509 "Closest BurstSize: %d kbps burstSize: %d kbps, mantissa: %d, exponent: %d\n"), 6510 rate, 6511 (shaper_info[unit]->burst_size_info[i].rate + 6512 (last_mantissa * (1 << (last_exponent + 2)))), 6513 last_mantissa, last_exponent)); 6514 } 6515 6516 return(rv); 6517 } 6518 6519 STATIC int 6520 _soc_katana_perq_flex_counters_init(int unit) 6521 { 6522 _soc_katana_counter_info_t *counter_info; 6523 uint32 rval, addr; 6524 int index, seg, i; 6525 6526 /* Setup MMU counter pool segment start address, consider each 1K block 6527 as separate segment */ 6528 for (i = 0; i < 12; i++) { 6529 if ((!soc_feature(unit, soc_feature_cosq_gport_stat_ability) && 6530 ((i % 4) != 0)) || 6531 ((soc_feature(unit, soc_feature_counter_toggled_read) && 6532 (i == 8)))) { 6533 /* 6534 * Create 3 segments each with 4K counters 6535 * Seg0(total enq drop pkts) seg_start address 0 6536 * Seg4(red enq drop pkts) seg_start address 4 * 1024 6537 * Seg8(deq stats)) seg_start_address 8 * 1024 6538 */ 6539 continue; 6540 } 6541 rval = 0; 6542 soc_reg_field_set(unit, CTR_SEGMENT_STARTr, &rval, SEG_STARTf, (i * 1024)); 6543 SOC_IF_ERROR_RETURN 6544 (soc_reg32_write(unit, soc_reg_addr(unit, CTR_SEGMENT_STARTr, 6545 REG_PORT_ANY, i), rval)); 6546 } 6547 6548 /* Cosq_stats - 6549 * CTR_FLEX_COUNT_0 = Total ENQ discarded 6550 * CTR_FLEX_COUNT_4 = Red ENQ discarded 6551 * CTR_FLEX_COUNT_8 = Total DEQ 6552 */ 6553 6554 /* Cosq_gport_stats - 6555 * CTR_FLEX_COUNT_1 = Total ENQ Accepted 6556 * CTR_FLEX_COUNT_2 = Green ENQ discarded 6557 * CTR_FLEX_COUNT_3 = Yellow ENQ discarded 6558 * CTR_FLEX_COUNT_5 = Green ENQ Accepted 6559 * CTR_FLEX_COUNT_6 = Yellow ENQ Accepted 6560 * CTR_FLEX_COUNT_7 = Red ENQ Accepted 6561 */ 6562 6563 counter_info = _soc_katana_counter_info; 6564 6565 /* set deq stats config */ 6566 rval = 0; 6567 seg = counter_info[_SOC_COUNTER_TYPE_ACCEPT_DEQ].segment; 6568 if (!soc_feature(unit, soc_feature_cosq_gport_stat_ability) && 6569 soc_feature(unit, soc_feature_counter_toggled_read)) { 6570 seg = counter_info[_SOC_COUNTER_TYPE_ACCEPT_DEQ].segment - 4; 6571 } 6572 index = counter_info[_SOC_COUNTER_TYPE_ACCEPT_DEQ].index; 6573 addr = soc_reg_addr(unit, CTR_DEQ_STATS_CFGr, REG_PORT_ANY, index); 6574 soc_reg_field_set(unit, CTR_DEQ_STATS_CFGr, &rval, ACTIVE0f, 1); 6575 soc_reg_field_set(unit, CTR_DEQ_STATS_CFGr, &rval, SEG0f, seg); 6576 SOC_IF_ERROR_RETURN(soc_reg32_write(unit, addr, rval)); 6577 6578 /* set enq stats config */ 6579 for (i = _SOC_COUNTER_TYPE_DROP_ENQ_GREEN; 6580 i < _SOC_COUNTER_TYPE_ACCEPT_DEQ; i++) { 6581 6582 if (!soc_feature(unit, soc_feature_cosq_gport_stat_ability) && 6583 (i >= _SOC_COUNTER_TYPE_ACCEPT_ENQ_GREEN)) { 6584 continue; 6585 } 6586 rval = 0; 6587 index = counter_info[i].index; 6588 addr = soc_reg_addr(unit, CTR_ENQ_STATS_CFGr, REG_PORT_ANY, index); 6589 if (i < _SOC_COUNTER_TYPE_ACCEPT_ENQ_GREEN) { 6590 seg = counter_info[_SOC_COUNTER_TYPE_DROP_ENQ].segment; 6591 } else { 6592 seg = counter_info[_SOC_COUNTER_TYPE_ACCEPT_ENQ].segment; 6593 } 6594 6595 if (!soc_feature(unit, soc_feature_counter_toggled_read) || 6596 !soc_feature(unit, soc_feature_cosq_gport_stat_ability)) { 6597 soc_reg_field_set(unit, CTR_ENQ_STATS_CFGr, &rval, ACTIVE0f, 1); 6598 soc_reg_field_set(unit, CTR_ENQ_STATS_CFGr, &rval, SEG0f, seg); 6599 } else { 6600 soc_reg_field_set(unit, CTR_ENQ_STATS_CFGr, &rval, ACTIVE0f, 1); 6601 seg = counter_info[i].segment; 6602 soc_reg_field_set(unit, CTR_ENQ_STATS_CFGr, &rval, SEG0f, seg); 6603 } 6604 6605 if (!soc_feature(unit, soc_feature_counter_toggled_read) && 6606 (soc_feature(unit, soc_feature_cosq_gport_stat_ability) || 6607 (i == _SOC_COUNTER_TYPE_DROP_ENQ_RED))) { 6608 soc_reg_field_set(unit, CTR_ENQ_STATS_CFGr, &rval, ACTIVE1f, 1); 6609 seg = counter_info[i].segment; 6610 soc_reg_field_set(unit, CTR_ENQ_STATS_CFGr, &rval, SEG1f, seg); 6611 } 6612 SOC_IF_ERROR_RETURN(soc_reg32_write(unit, addr, rval)); 6613 6614 } 6615 6616 return SOC_E_NONE; 6617 } 6618 6619 int 6620 soc_katana_get_shaper_rate_info(int unit, uint32 rate, 6621 uint32 *rate_mantissa, uint32 *rate_exponent) 6622 { 6623 int rv = SOC_E_NONE; 6624 int index; 6625 6626 if (shaper_info[unit] == NULL) { 6627 rv = _soc_katana_shaper_rate_info_alloc(unit); 6628 if (rv != SOC_E_NONE) { 6629 return(rv); 6630 } 6631 } 6632 6633 rv = _soc_katana_get_shaper_rate(unit, rate, &index, rate_mantissa, rate_exponent); 6634 if (rv != SOC_E_NONE) { 6635 return(rv); 6636 } 6637 6638 return(rv); 6639 } 6640 6641 int 6642 soc_katana_get_shaper_burst_info(int unit, uint32 rate, 6643 uint32 *burst_mantissa, uint32 *burst_exponent, 6644 uint32 flags) 6645 { 6646 int rv = SOC_E_NONE; 6647 uint32 burst_bps; 6648 6649 if (shaper_info[unit] == NULL) { 6650 rv = _soc_katana_shaper_rate_info_alloc(unit); 6651 if (rv != SOC_E_NONE) { 6652 return(rv); 6653 } 6654 } 6655 6656 /* convert kbps to bps */ 6657 burst_bps = rate * 1000; 6658 6659 if (burst_bps > 0xFF0000) { 6660 burst_bps = 0xFF0000; 6661 } 6662 6663 rv = _soc_katana_get_shaper_burst_size(unit, 6664 burst_bps, burst_mantissa, burst_exponent); 6665 if (rv != SOC_E_NONE) { 6666 return(rv); 6667 } 6668 6669 if ((rate > 0) && (*burst_exponent < 5)) { 6670 *burst_exponent = 5; 6671 *burst_mantissa = 0; 6672 } 6673 6674 return(rv); 6675 } 6676 6677 int 6678 soc_katana_compute_shaper_rate(int unit, uint32 rate_mantissa, 6679 uint32 rate_exponent, uint32 *rate) 6680 { 6681 int rv = SOC_E_NONE; 6682 uint64 numerator; 6683 uint32 denominator; 6684 uint32 temp; 6685 6686 if (rate_exponent == 0) { 6687 /* (2^r_e+4) * (r_m/1024) / ref_cycle based on 7.8125uS(128KHz) */ 6688 COMPILER_64_SET(numerator, 0, rate_mantissa); 6689 COMPILER_64_SHL(numerator, 11); 6690 } else { 6691 /* (2^(r_e+3)) * (1+(r_m / 1024)) / ref_cycle */ 6692 temp = 1024 + rate_mantissa; 6693 COMPILER_64_SET(numerator, 0, temp); 6694 temp = rate_exponent + 3 + 7; 6695 COMPILER_64_SHL(numerator, temp); 6696 } 6697 6698 denominator = 1024; 6699 6700 if (soc_esw_div64(numerator, denominator, rate) == -1) { 6701 rv = SOC_E_INTERNAL; 6702 } 6703 6704 return(rv); 6705 } 6706 6707 int 6708 soc_katana_compute_shaper_burst(int unit, uint32 burst_mantissa, 6709 uint32 burst_exponent, uint32 *rate) 6710 { 6711 int rv = SOC_E_NONE; 6712 /* rate = 2^(t_e+9) * (1+(t_m/128)) */ 6713 *rate = ((1 << (burst_exponent + 9)) * (128 + burst_mantissa)) / 128; 6714 6715 /* convert bps to kbps */ 6716 *rate = *rate / 1000; 6717 6718 return(rv); 6719 } 6720 6721 int 6722 soc_katana_compute_refresh_rate(int unit, uint32 rate_exp, 6723 uint32 rate_mant, 6724 uint32 burst_exp, 6725 uint32 burst_mant, 6726 uint32 *cycle_sel) 6727 { 6728 int rv = SOC_E_NONE; 6729 int temp_cyc; 6730 int deq_max_temp, deq_max_length_shift, headroom; 6731 int rfh_max_temp, rfh_max_padded_threshold; 6732 int rfh_max_temp_threshold, rfh_max_fnl_threshold; 6733 6734 if (cycle_sel == NULL) { 6735 return SOC_E_INTERNAL; 6736 } 6737 *cycle_sel = 0; 6738 6739 rfh_max_padded_threshold = (128 + burst_mant) * (1 << (burst_exp + 9)); 6740 6741 rfh_max_temp_threshold = (128 + burst_mant) * (1 << burst_exp); 6742 6743 for (temp_cyc = 0 ; temp_cyc < 10 ; temp_cyc++) { 6744 if (rate_exp < 1) { 6745 rfh_max_temp = rate_exp + temp_cyc + 1; 6746 } else { 6747 rfh_max_temp = rate_exp + temp_cyc; 6748 } 6749 6750 deq_max_temp = rfh_max_temp; 6751 if (deq_max_temp <= 10) { 6752 deq_max_length_shift = 10 - deq_max_temp; 6753 } else { 6754 deq_max_length_shift = deq_max_temp - 10; 6755 } 6756 6757 if (rate_exp < 10) { 6758 rfh_max_fnl_threshold = rfh_max_padded_threshold / (1 << rfh_max_temp); 6759 } else { 6760 rfh_max_fnl_threshold = rfh_max_temp_threshold / 2; 6761 } 6762 6763 headroom = 0x1fffff - rfh_max_fnl_threshold; 6764 6765 /* It is expected that the bucket did not go negative after subtracting the 6766 * threshold. It is also expected that there is still enough headroom to 6767 * dequeue and account for two 16K packets */ 6768 6769 if ((headroom > 0) && (headroom / (1 << deq_max_length_shift)) >= 32768) { 6770 *cycle_sel = temp_cyc; 6771 break; 6772 } 6773 } 6774 6775 return(rv); 6776 } 6777 6778 6779 int 6780 soc_katana_compute_burst_rate_check(int unit, uint32 rate_exp, 6781 uint32 rate_mant, 6782 uint32 burst_exp, 6783 uint32 burst_mant, 6784 uint32 cycle_sel) 6785 { 6786 int rv = SOC_E_NONE; 6787 uint32 expected_rate_kbps, expected_burst; 6788 uint32 deq_max_temp, deq_max_length_shift, max_length; 6789 uint32 max_credit_pre_shift, max_credit; 6790 uint32 rfh_max_temp, rfh_max_padded_threshold; 6791 uint32 rfh_max_temp_threshold, rfh_max_fnl_threshold; 6792 uint32 deq_bytes = 1; 6793 6794 /* Calculate the expected rate and burst for error checking later */ 6795 if (!rate_exp) { 6796 expected_rate_kbps = (1 << 4) * 128 * rate_mant / 1024; 6797 } else if (rate_exp >= 10) { 6798 /* Avoid uint32 overflow */ 6799 expected_rate_kbps = (1 << (rate_exp + 3)) * 128; 6800 expected_rate_kbps += expected_rate_kbps / 1024 * rate_mant; 6801 } else { 6802 expected_rate_kbps = (1 << (rate_exp + 3)) * 128; 6803 expected_rate_kbps += expected_rate_kbps * rate_mant / 1024; 6804 } 6805 6806 expected_burst = (1 << (burst_exp + 9)); 6807 expected_burst += expected_burst * burst_mant / 128; 6808 6809 /* Compute values that remain constant regardless of cycle_sel */ 6810 if (!rate_exp) { 6811 max_credit_pre_shift = rate_mant; 6812 } else { 6813 max_credit_pre_shift = rate_mant + 1024; 6814 } 6815 6816 if (rate_exp < 11) { 6817 max_credit = max_credit_pre_shift; 6818 } else { 6819 max_credit = max_credit_pre_shift * (1 << (rate_exp - 10)); 6820 } 6821 6822 rfh_max_padded_threshold = (128 + burst_mant) * (1 << (burst_exp + 9)); 6823 6824 rfh_max_temp_threshold = (128 + burst_mant) * (1 << burst_exp); 6825 6826 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, "Shaper inputs:\n"))); 6827 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, " rate_exp = %u\n"), rate_exp)); 6828 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, " rate_mant = %u\n"), rate_mant)); 6829 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, " burst_exp = %u\n"), burst_exp)); 6830 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, " burst_mant = %u\n"), burst_mant)); 6831 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, " cycle_sel = %u\n"), cycle_sel)); 6832 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, " expected_rate_kbps = %u\n"), expected_rate_kbps)); 6833 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, " expected_burst = %u\n"), expected_burst)); 6834 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, " max_credit_pre_shift = %u\n"), max_credit_pre_shift)); 6835 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, " max_credit = %u\n"), max_credit)); 6836 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, " rfh_max_padded_threshold = %u\n"), rfh_max_padded_threshold)); 6837 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, " rfh_max_temp_threshold = %u\n"), rfh_max_temp_threshold)); 6838 6839 /* Compute values */ 6840 if (rate_exp) { 6841 deq_max_temp = rate_exp + cycle_sel; 6842 } else { 6843 deq_max_temp = rate_exp + cycle_sel + 1; 6844 } 6845 6846 if (deq_max_temp <= 10) { 6847 deq_max_length_shift = 10 - deq_max_temp; 6848 } else { 6849 deq_max_length_shift = deq_max_temp - 10; 6850 } 6851 6852 if (rate_exp < 10) { 6853 max_length = deq_bytes * (1 << deq_max_length_shift); 6854 } else { 6855 max_length = deq_bytes; 6856 } 6857 6858 if (rate_exp < 1) { 6859 rfh_max_temp = rate_exp + cycle_sel + 1; 6860 } else { 6861 rfh_max_temp = rate_exp + cycle_sel; 6862 } 6863 6864 if (rate_exp < 10) { 6865 rfh_max_fnl_threshold = rfh_max_padded_threshold / (1 << rfh_max_temp); 6866 } else { 6867 rfh_max_fnl_threshold = rfh_max_temp_threshold / 2; 6868 } 6869 6870 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, " cycle_sel = %d:\n"), cycle_sel)); 6871 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, " deq_max_temp = %u\n"), deq_max_temp)); 6872 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, " deq_max_length_shift = %u\n"), deq_max_length_shift)); 6873 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, " max_length = %u\n"), max_length)); 6874 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, " rfh_max_temp = %u\n"), rfh_max_temp)); 6875 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, " rfh_max_fnl_threshold = %u\n"), rfh_max_fnl_threshold)); 6876 6877 /* Check to ensure that all requirements are satisfied */ 6878 if (max_length > MAX_BUCKET_VAL) { 6879 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, " Failed due to DEQUEUE_ADD check\n"))); 6880 return SOC_E_PARAM; 6881 } 6882 6883 if (rfh_max_fnl_threshold > MAX_BUCKET_VAL) { 6884 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, " Failed due to THRESHOLD check\n"))); 6885 return SOC_E_PARAM; 6886 } 6887 6888 if (max_credit > MAX_BUCKET_VAL) { 6889 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, " Failed due to REFRESH check\n"))); 6890 return SOC_E_PARAM; 6891 } 6892 6893 6894 if (8 * 128 / max_length * max_credit / (1 << cycle_sel) != expected_rate_kbps) { 6895 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, " Failed due to rate mismatch check\n"))); 6896 return SOC_E_PARAM; 6897 } 6898 6899 if (rfh_max_fnl_threshold / max_length * 8 != expected_burst) { 6900 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, " Failed due to burst mismatch check\n"))); 6901 return SOC_E_PARAM; 6902 } 6903 return(rv); 6904 } 6905 6906 /* 56440/56445/55440 TDM sequence */ 6907 uint32 kt_tdm_0[78] = { 1,9,25,26,27,28, 6908 17,2,25,26,27,28, 6909 0,10,18,25,26,27, 6910 28,3,11,25,26,27, 6911 28,35,19,4,25,26, 6912 27,28,12,20,25,26, 6913 27,28,63,5,13,25, 6914 26,27,28,21,6,25, 6915 26,27,28,0,14,22, 6916 25,26,27,28,7,15, 6917 25,26,27,28,35,23, 6918 8,25,26,27,28,16, 6919 24,25,26,27,28,35 6920 }; 6921 /* 56441 TDM sequence */ 6922 uint32 kt_tdm_1[48] = { 9,28,1,27, 6923 63,28,10,27, 6924 63,28,0,27, 6925 11,28,63,27, 6926 63,28,12,27, 6927 35,28,63,27, 6928 13,28,63,27, 6929 63,28,14,27, 6930 35,28,63,27, 6931 15,28,63,27, 6932 63,28,16,27, 6933 35,28,0,27 6934 }; 6935 /* 56442 TDM sequence */ 6936 uint32 kt_tdm_2[48] = { 9,17,1,35, 6937 63,0,10,18, 6938 63,63,63,63, 6939 11,19,35,63, 6940 63,63,12,20, 6941 63,0,63,63, 6942 13,21,35,63, 6943 63,63,14,22, 6944 63,63,63,63, 6945 15,23,35,63, 6946 63,63,16,24, 6947 63,63,0,63 6948 }; 6949 /* 56443 TDM sequence */ 6950 uint32 kt_tdm_3[78] = { 9,1,25,26,28,27, 6951 63,10,25,26,29,32, 6952 63,0,25,26,30,33, 6953 11,63,25,26,31,34, 6954 63,12,25,26,28,27, 6955 35,63,25,26,29,32, 6956 13,63,25,26,30,33, 6957 63,14,25,26,31,34, 6958 63,63,25,26,28,27, 6959 15,35,25,26,29,32, 6960 63,16,25,26,30,33, 6961 0,63,25,26,31,34, 6962 63,63,25,26,63,63 6963 }; 6964 /* 56440/56445/55440 config-1 TDM sequence */ 6965 uint32 kt_tdm_4[78] = { 1,9,25,26,28,27, 6966 17,2,25,26,29,32, 6967 10,18,25,26,30,33, 6968 3,11,25,26,31,34, 6969 19,4,25,26,28,35, 6970 12,20,25,26,29,27, 6971 5,13,25,26,30,32, 6972 21,6,25,26,31,33, 6973 14,22,25,26,28,34, 6974 7,15,25,26,29,27, 6975 23,8,25,26,30,32, 6976 16,24,25,26,31,33, 6977 63,0,25,26,63,34 6978 }; 6979 /* 56449 config-1 TDM sequence */ 6980 uint32 kt_tdm_5[48] = { 1,9,17,25, 6981 26,27,2,10, 6982 18,28,35,63, 6983 3,11,19,0, 6984 25,26,4,12, 6985 20,27,28,35, 6986 5,13,21,63, 6987 63,0,6,14, 6988 22,25,26,35, 6989 7,15,23,27, 6990 63,28,8,16, 6991 24,63,0,63 6992 }; 6993 /* 56243 TDM sequence */ 6994 uint32 kt_tdm_6[16] = { 27,28,63,35, 6995 32,29,0,35, 6996 33,30,63,35, 6997 34,31,0,63 6998 }; 6999 7000 /* 240/242/245/246 TDM sequence */ 7001 uint32 kt_tdm_7[40] = { 27,35,26,25, 7002 32,28,26,25, 7003 33,29,26,25, 7004 34,30,26,25, 7005 35,31,26,25, 7006 27,28,26,25, 7007 32,29,26,25, 7008 33,30,26,25, 7009 34,31,26,25, 7010 0,1,26,25 7011 }; 7012 7013 uint32 kt_tdm_8[78] = { 1,9,25,26,27,28, 7014 17,2,25,26,27,29, 7015 0,10,18,25,26,27, 7016 30,3,11,25,26,27, 7017 31,35,19,4,25,26, 7018 27,28,12,20,25,26, 7019 27,29,63,5,13,25, 7020 26,27,30,21,6,25, 7021 26,27,31,0,14,22, 7022 25,26,27,28,7,15, 7023 25,26,27,29,35,23, 7024 8,25,26,27,30,16, 7025 24,25,26,27,31,35 7026 }; 7027 7028 uint32 kt_tdm_9[78] = { 1,9,25,26,27,28, 7029 17,2,25,26,32,28, 7030 0,10,18,25,26,33, 7031 28,3,11,25,26,34, 7032 28,35,19,4,25,26, 7033 27,28,12,20,25,26, 7034 32,28,63,5,13,25, 7035 26,33,28,21,6,25, 7036 26,34,28,0,14,22, 7037 25,26,27,28,7,15, 7038 25,26,32,28,35,23, 7039 8,25,26,33,28,16, 7040 24,25,26,34,28,35 7041 }; 7042 7043 static uint32 7044 _soc_katana_mmu_tdm_var(uint32 *arr, uint16 dev_id, int cfg_num, int pos) 7045 { 7046 uint32 retval; 7047 7048 retval = arr[pos]; 7049 7050 switch (dev_id) { 7051 case BCM56441_DEVICE_ID: 7052 case BCM56446_DEVICE_ID: 7053 if (cfg_num == 1) { 7054 switch (pos) { 7055 case 5: case 21: case 37: 7056 retval = 29; 7057 break; 7058 case 9: case 25: case 41: 7059 retval = 30; 7060 break; 7061 case 13: case 29: case 45: 7062 retval = 31; 7063 break; 7064 case 7: case 23: case 39: 7065 retval = 32; 7066 break; 7067 case 11: case 27: case 43: 7068 retval = 33; 7069 break; 7070 case 15: case 31: case 47: 7071 retval = 34; 7072 break; 7073 } 7074 } else if (cfg_num == 2) { 7075 switch (pos) { 7076 case 24 : 7077 retval = 9; 7078 break; 7079 case 30: 7080 retval = 10; 7081 break; 7082 case 36: 7083 retval = 11; 7084 break; 7085 case 42: 7086 retval = 12; 7087 break; 7088 case 5: case 21: case 37: 7089 retval = 29; 7090 break; 7091 case 9: case 25: case 41: 7092 retval = 30; 7093 break; 7094 case 13: case 29: case 45: 7095 retval = 31; 7096 break; 7097 } 7098 } 7099 if (dev_id == BCM56446_DEVICE_ID) { 7100 if ((retval >= 9) && (retval <= 16)) { 7101 retval -= 8; 7102 } else if (retval == 1) { 7103 retval = 63; 7104 } 7105 } 7106 break; 7107 7108 7109 case BCM56442_DEVICE_ID: 7110 case BCM56447_DEVICE_ID: 7111 if (dev_id == BCM56447_DEVICE_ID) { 7112 if ((retval >= 17) && (retval <= 24)) { 7113 retval -= 16; 7114 } else if (retval == 1) { 7115 retval = 63; 7116 } 7117 } 7118 break; 7119 7120 case BCM56242_DEVICE_ID: 7121 case BCM56246_DEVICE_ID: 7122 switch (pos) { 7123 case 7: case 11: 7124 case 15: case 19: 7125 case 27: case 31: 7126 case 35: case 39: 7127 retval = 63; 7128 break; 7129 case 6: case 10: 7130 case 14: case 18: 7131 case 26: case 30: 7132 case 34: case 38: 7133 retval = 63; 7134 break; 7135 } 7136 break; 7137 7138 case BCM56243_DEVICE_ID: 7139 switch (pos) { 7140 case 0: case 4: 7141 case 8: case 12: 7142 retval = 63; 7143 break; 7144 } 7145 break; 7146 7147 case BCM56240_DEVICE_ID: 7148 case BCM56245_DEVICE_ID: 7149 if (cfg_num == 0) { 7150 switch (pos) { 7151 case 4: case 8: case 12: 7152 case 24: case 28: case 32: 7153 retval = 27; 7154 break; 7155 case 9: case 13: case 17: 7156 case 25: case 29: case 38: 7157 retval = 28; 7158 break; 7159 } 7160 } 7161 break; 7162 7163 default: 7164 break; 7165 } 7166 7167 return retval; 7168 } 7169 7170 STATIC int 7171 _soc_katana_mmu_tdm_init(int unit) 7172 { 7173 uint32 *arr; 7174 int i, tdm_size, cfg_num; 7175 iarb_tdm_table_entry_t iarb_tdm; 7176 lls_port_tdm_entry_t lls_tdm; 7177 uint32 rval, arr_ele; 7178 uint16 dev_id; 7179 uint8 rev_id; 7180 7181 soc_cm_get_id(unit, &dev_id, &rev_id); 7182 cfg_num = soc_property_get(unit, spn_BCM5644X_CONFIG, 0); 7183 7184 if ((dev_id == BCM56440_DEVICE_ID) || (dev_id == BCM56445_DEVICE_ID) || 7185 (dev_id == BCM55440_DEVICE_ID) || (dev_id == BCM55441_DEVICE_ID)) { 7186 tdm_size = 78; 7187 if (cfg_num == 1) { 7188 arr = kt_tdm_4; 7189 } else if (cfg_num == 3) { 7190 arr = kt_tdm_8; 7191 } else if (cfg_num == 4) { 7192 arr = kt_tdm_9; 7193 } else { 7194 arr = kt_tdm_0; 7195 } 7196 } else if (dev_id == BCM56448_DEVICE_ID) { 7197 tdm_size = 78; 7198 arr = kt_tdm_0; 7199 } else if ((dev_id == BCM56441_DEVICE_ID) || (dev_id == BCM56446_DEVICE_ID)) { 7200 tdm_size = 48; 7201 arr = kt_tdm_1; 7202 } else if ((dev_id == BCM56442_DEVICE_ID) || (dev_id == BCM56447_DEVICE_ID)) { 7203 tdm_size = 48; 7204 arr = kt_tdm_2; 7205 } else if (dev_id == BCM56443_DEVICE_ID) { 7206 tdm_size = 78; 7207 arr = kt_tdm_3; 7208 } else if (dev_id == BCM56243_DEVICE_ID) { 7209 tdm_size = 16; 7210 arr = kt_tdm_6; 7211 } else if ((dev_id == BCM56240_DEVICE_ID) || (dev_id == BCM56241_DEVICE_ID) || 7212 (dev_id == BCM56242_DEVICE_ID) || (dev_id == BCM56245_DEVICE_ID) || 7213 (dev_id == BCM56246_DEVICE_ID)) { 7214 tdm_size = 40; 7215 arr = kt_tdm_7; 7216 } else if (dev_id == BCM56449_DEVICE_ID) { 7217 if (cfg_num == 0) { 7218 tdm_size = 78; 7219 arr = kt_tdm_0; 7220 } else if (cfg_num == 1) { 7221 tdm_size = 48; 7222 arr = kt_tdm_5; 7223 } else { 7224 return SOC_E_FAIL; 7225 } 7226 } else { 7227 return SOC_E_FAIL; 7228 } 7229 7230 /* Disable IARB TDM before programming... */ 7231 SOC_IF_ERROR_RETURN(READ_IARB_TDM_CONTROLr(unit, &rval)); 7232 soc_reg_field_set(unit, IARB_TDM_CONTROLr, &rval, DISABLEf, 1); 7233 soc_reg_field_set(unit, IARB_TDM_CONTROLr, &rval, TDM_WRAP_PTRf, 7234 tdm_size -1); 7235 SOC_IF_ERROR_RETURN(WRITE_IARB_TDM_CONTROLr(unit, rval)); 7236 7237 for (i = 0; i < tdm_size; i++) { 7238 arr_ele = _soc_katana_mmu_tdm_var(arr, dev_id, cfg_num, i); 7239 7240 sal_memset(&iarb_tdm, 0, sizeof(iarb_tdm_table_entry_t)); 7241 soc_IARB_TDM_TABLEm_field32_set(unit, &iarb_tdm, PORT_NUMf, 7242 arr_ele); 7243 SOC_IF_ERROR_RETURN(WRITE_IARB_TDM_TABLEm(unit, SOC_BLOCK_ALL, i, 7244 &iarb_tdm)); 7245 7246 if (0 == (i%2)) { 7247 /* Two entries per mem entry */ 7248 sal_memset(&lls_tdm, 0, sizeof(lls_port_tdm_entry_t)); 7249 soc_LLS_PORT_TDMm_field32_set(unit, &lls_tdm, PORT_ID_0f, arr_ele); 7250 soc_LLS_PORT_TDMm_field32_set(unit, &lls_tdm, PORT_ID_0_ENABLEf, 1); 7251 } else { 7252 soc_LLS_PORT_TDMm_field32_set(unit, &lls_tdm, PORT_ID_1f, arr_ele); 7253 soc_LLS_PORT_TDMm_field32_set(unit, &lls_tdm, PORT_ID_1_ENABLEf, 1); 7254 SOC_IF_ERROR_RETURN(WRITE_LLS_PORT_TDMm(unit, SOC_BLOCK_ALL, (i/2), 7255 &lls_tdm)); 7256 } 7257 } 7258 SOC_IF_ERROR_RETURN(READ_IARB_TDM_CONTROLr(unit, &rval)); 7259 soc_reg_field_set(unit, IARB_TDM_CONTROLr, &rval, DISABLEf, 0); 7260 soc_reg_field_set(unit, IARB_TDM_CONTROLr, &rval, TDM_WRAP_PTRf, 7261 tdm_size -1); 7262 SOC_IF_ERROR_RETURN(WRITE_IARB_TDM_CONTROLr(unit, rval)); 7263 7264 7265 rval = 0; 7266 soc_reg_field_set(unit, LLS_TDM_CAL_CFGr, &rval, END_Af, tdm_size - 1); 7267 soc_reg_field_set(unit, LLS_TDM_CAL_CFGr, &rval, END_Bf, tdm_size - 1); 7268 soc_reg_field_set(unit, LLS_TDM_CAL_CFGr, &rval, ENABLEf, 1); 7269 SOC_IF_ERROR_RETURN(WRITE_LLS_TDM_CAL_CFGr(unit, rval)); 7270 7271 return SOC_E_NONE; 7272 } 7273 7274 STATIC int 7275 _katana_ledup_init(int unit) 7276 { 7277 int ix; 7278 uint32 rval = 0; 7279 struct led_remap { 7280 uint32 reg_addr; 7281 uint32 port0; 7282 uint32 port1; 7283 uint32 port2; 7284 uint32 port3; 7285 } led0_remap[] = { 7286 {CMIC_LEDUP0_PORT_ORDER_REMAP_32_35r, 7287 REMAP_PORT_32f,REMAP_PORT_33f,REMAP_PORT_34f,REMAP_PORT_35f}, 7288 {CMIC_LEDUP0_PORT_ORDER_REMAP_36_39r, 7289 REMAP_PORT_36f,REMAP_PORT_37f,REMAP_PORT_38f,REMAP_PORT_39f}, 7290 {CMIC_LEDUP0_PORT_ORDER_REMAP_24_27r, 7291 REMAP_PORT_24f,REMAP_PORT_25f,REMAP_PORT_26f,REMAP_PORT_27f}, 7292 {CMIC_LEDUP0_PORT_ORDER_REMAP_28_31r, 7293 REMAP_PORT_28f,REMAP_PORT_29f,REMAP_PORT_30f,REMAP_PORT_31f}, 7294 {CMIC_LEDUP0_PORT_ORDER_REMAP_16_19r, 7295 REMAP_PORT_16f,REMAP_PORT_17f,REMAP_PORT_18f,REMAP_PORT_19f}, 7296 {CMIC_LEDUP0_PORT_ORDER_REMAP_20_23r, 7297 REMAP_PORT_20f,REMAP_PORT_21f,REMAP_PORT_22f,REMAP_PORT_23f}, 7298 {CMIC_LEDUP0_PORT_ORDER_REMAP_12_15r, 7299 REMAP_PORT_12f,REMAP_PORT_13f,REMAP_PORT_14f,REMAP_PORT_15f}, 7300 {CMIC_LEDUP0_PORT_ORDER_REMAP_8_11r, 7301 REMAP_PORT_8f,REMAP_PORT_9f,REMAP_PORT_10f,REMAP_PORT_11f}, 7302 {CMIC_LEDUP0_PORT_ORDER_REMAP_4_7r, 7303 REMAP_PORT_4f,REMAP_PORT_5f,REMAP_PORT_6f,REMAP_PORT_7f}, 7304 {CMIC_LEDUP0_PORT_ORDER_REMAP_0_3r, 7305 REMAP_PORT_0f,REMAP_PORT_1f,REMAP_PORT_2f,REMAP_PORT_3f} 7306 }; 7307 7308 7309 int led_data[40] = { 7310 1, 2, 3, 4, 7311 5, 6, 7, 8, 7312 9, 10, 11, 12, 7313 13, 14, 15, 16, 7314 17, 18, 19, 20, 7315 21, 22, 23, 24, 7316 38, 38, 38, 25, 7317 26, 38, 38, 26, 7318 34, 33, 32, 27, 7319 31, 30, 29, 28 7320 }; 7321 /* initialize the led remap register settings. 7322 * port 0 entry will not be used for easy index of the physical port starting 1 7323 */ 7324 for (ix = 0; ix < sizeof(led0_remap)/sizeof(led0_remap[0]); ix++) { 7325 rval = 0; 7326 soc_reg_field_set(unit, led0_remap[ix].reg_addr, &rval, 7327 led0_remap[ix].port0, led_data[ix * 4]); 7328 soc_reg_field_set(unit, led0_remap[ix].reg_addr, &rval, 7329 led0_remap[ix].port1, led_data[(ix * 4) + 1]); 7330 soc_reg_field_set(unit, led0_remap[ix].reg_addr, &rval, 7331 led0_remap[ix].port2, led_data[(ix * 4) + 2]); 7332 soc_reg_field_set(unit, led0_remap[ix].reg_addr, &rval, 7333 led0_remap[ix].port3, led_data[(ix * 4) + 3]); 7334 /* coverity[result_independent_of_operands] */ 7335 SOC_IF_ERROR_RETURN 7336 (soc_pci_write(unit, 7337 soc_reg_addr(unit, led0_remap[ix].reg_addr, REG_PORT_ANY, 0), 7338 rval)); 7339 } 7340 7341 /* initialize the UP0 data ram */ 7342 rval = 0; 7343 for (ix = 0; ix < 256; ix++) { 7344 /* coverity[result_independent_of_operands] */ 7345 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP0_DATA_RAMr(unit,ix, rval)); 7346 } 7347 return SOC_E_NONE; 7348 } 7349 7350 STATIC int 7351 _soc_katana_misc_init(int unit) 7352 { 7353 static const soc_field_t port_field[4] = { 7354 PORT0f, PORT1f, PORT2f, PORT3f 7355 }; 7356 soc_info_t *si; 7357 uint32 rval, rval1; 7358 uint32 entry[SOC_MAX_MEM_WORDS]; 7359 soc_pbmp_t pbmp; 7360 int port, blk_port, blk, pindex; 7361 int count; 7362 uint64 reg64; 7363 uint16 dev_id; 7364 uint8 rev_id; 7365 int i, parity_enable; 7366 mmu_ipmc_group_tbl0_entry_t ipmc_entry; 7367 mmu_rqe_queue_op_node_map_entry_t rqe_entry; 7368 mmu_wred_queue_op_node_map_entry_t wred_entry; 7369 mmu_ext_mc_group_map_entry_t mc_group_entry; 7370 mmu_ext_mc_queue_list0_entry_t mc_list0_entry; 7371 mmu_ext_mc_queue_list1_entry_t mc_list1_entry; 7372 mmu_ext_mc_queue_list4_entry_t mc_list4_entry; 7373 soc_field_t fields[3]; 7374 uint32 values[3]; 7375 soc_port_t it_port; 7376 uint32 mxq = 0; 7377 int last_two_mxqblock_ports[2][4] = {{27, 32, 33, 34},{28, 29, 30, 31}}; 7378 soc_port_t any_port=0; 7379 soc_field_t xport_field[2] = { XPORT2_MULTI_PORTf, XPORT3_MULTI_PORTf }; 7380 uint8 mxqport_used = 0; 7381 svm_policy_table_entry_t meter_action; 7382 svm_macroflow_index_table_entry_t macro_flow_entry; 7383 7384 soc_cm_get_id(unit, &dev_id, &rev_id); 7385 7386 si = &SOC_INFO(unit); 7387 7388 parity_enable = soc_property_get(unit, spn_PARITY_ENABLE, TRUE); 7389 if (parity_enable) { 7390 (void) _soc_katana_ser_init(unit); 7391 #ifdef INCLUDE_MEM_SCAN 7392 soc_mem_scan_ser_list_register(unit, FALSE, 7393 _soc_kt_ser_parity_info[unit]); 7394 #endif 7395 memset(&_kt_ser_functions, 0, sizeof(soc_ser_functions_t)); 7396 _kt_ser_functions._soc_ser_stat_nack_f = &soc_katana_stat_nack; 7397 _kt_ser_functions._soc_ser_fail_f = &soc_katana_ser_fail; 7398 _kt_ser_functions._soc_ser_mem_nack_f = &soc_katana_mem_nack; 7399 _kt_ser_functions._soc_ser_parity_error_cmicm_intr_f = 7400 &soc_katana_parity_error; 7401 soc_ser_function_register(unit, &_kt_ser_functions); 7402 } else { 7403 memset(&_kt_oam_event_functions, 0, sizeof(soc_oam_event_functions_t)); 7404 _kt_oam_event_functions._soc_oam_event_intr_f = &soc_katana_oam_event_process; 7405 soc_oam_event_function_register (unit, &_kt_oam_event_functions); 7406 } 7407 7408 7409 if (!SOC_IS_RELOADING(unit) && !SOC_WARM_BOOT(unit)) { 7410 /* Clear IPIPE/EIPIE Memories */ 7411 SOC_IF_ERROR_RETURN(soc_katana_pipe_mem_clear(unit)); 7412 } 7413 7414 /* Some registers are implemented in memory, need to clear them in order 7415 * to have correct parity value */ 7416 PBMP_ALL_ITER(unit, port) { 7417 SOC_IF_ERROR_RETURN(WRITE_EGR_VLAN_CONTROL_1r(unit, port, 0)); 7418 SOC_IF_ERROR_RETURN(WRITE_EGR_IPMC_CFG2r(unit, port, 0)); 7419 } 7420 7421 /* default DDR3 Configuration */ 7422 /* 16k Col * 1k Row * 8 Banks * 16 bits = 2Gb */ 7423 #if 0 /* Katana Only supports 1k Cols and 8 banks */ 7424 SOC_DDR3_NUM_COLUMNS(unit) = soc_property_get(unit,spn_EXT_RAM_COLUMNS, 1024); 7425 SOC_DDR3_NUM_BANKS(unit) = soc_property_get(unit,spn_EXT_RAM_BANKS, 8); 7426 #else 7427 SOC_DDR3_NUM_COLUMNS(unit) = 1024; 7428 SOC_DDR3_NUM_BANKS(unit) = 8; 7429 #endif 7430 SOC_DDR3_NUM_MEMORIES(unit) = soc_property_get(unit,spn_EXT_RAM_PRESENT, 3); 7431 SOC_DDR3_NUM_ROWS(unit) = soc_property_get(unit,spn_EXT_RAM_ROWS, 8192); 7432 SOC_DDR3_CLOCK_MHZ(unit) = soc_property_get(unit, spn_DDR3_CLOCK_MHZ, 800); 7433 SOC_DDR3_MEM_GRADE(unit) = soc_property_get(unit, spn_DDR3_MEM_GRADE, 0); 7434 7435 if (soc_feature(unit, soc_feature_ddr3)) { 7436 /* CI Init */ 7437 soc_ddr40_set_shmoo_dram_config(unit, ((uint32) 0xFFFFFFFF) >> (32 - SOC_DDR3_NUM_MEMORIES(unit))); 7438 if ((soc_ddr40_phy_pll_ctl(unit, 0, SOC_DDR3_CLOCK_MHZ(unit), 1, 0) == SOC_E_NONE) && 7439 (soc_ddr40_ctlr_ctl(unit, 0, 1, 0) == SOC_E_NONE) && 7440 (soc_ddr40_phy_calibrate(unit, 0, 1, 0) == SOC_E_NONE)) { 7441 7442 if (soc_property_get(unit, spn_DDR3_AUTO_TUNE, FALSE)) { 7443 soc_ddr40_shmoo_ctl(unit, 0, 1, 1, 0, 0); 7444 if (SOC_DDR3_NUM_MEMORIES(unit) == 3) { 7445 soc_ddr40_shmoo_ctl(unit, 2, 1, 1, 0, 0); 7446 } 7447 LOG_CLI((BSL_META_U(unit, 7448 "DDR Tune Completed\n"))); 7449 } else { 7450 if ((soc_ddr40_shmoo_restorecfg(unit, 0) == SOC_E_NONE) && 7451 ((SOC_DDR3_NUM_MEMORIES(unit) != 3) || 7452 (soc_ddr40_shmoo_restorecfg(unit, 2) == SOC_E_NONE))) { 7453 LOG_CLI((BSL_META_U(unit, 7454 "DDR Tune Values Restored\n"))); 7455 } 7456 } 7457 } 7458 } 7459 /* SW WAR for avoiding continuous parity errors coming from 7460 SVM_POLICY_TABLE and SVM_MACROFLOW_INDEX_TABLE entry 0 */ 7461 SOC_IF_ERROR_RETURN 7462 (soc_mem_read(unit, SVM_POLICY_TABLEm, MEM_BLOCK_ANY, 7463 0, &meter_action)); 7464 SOC_IF_ERROR_RETURN 7465 (soc_mem_read(unit, SVM_MACROFLOW_INDEX_TABLEm, MEM_BLOCK_ANY, 7466 0, ¯o_flow_entry)); 7467 SOC_IF_ERROR_RETURN 7468 (soc_mem_write(unit, SVM_POLICY_TABLEm, MEM_BLOCK_ANY, 7469 0, &meter_action)); 7470 SOC_IF_ERROR_RETURN 7471 (soc_mem_write(unit, SVM_MACROFLOW_INDEX_TABLEm, MEM_BLOCK_ANY, 7472 0, ¯o_flow_entry)); 7473 /* Reset MXQPORT MIB counter (registers implemented in memory) */ 7474 SOC_BLOCK_ITER(unit, blk, SOC_BLK_MXQPORT) { 7475 blk_port = SOC_BLOCK_PORT(unit, blk); 7476 if (blk_port < 0) { 7477 continue; 7478 } 7479 rval = 0; 7480 soc_reg_field_set(unit, XPORT_MIB_RESETr, &rval, CLR_CNTf, 0xf); /* All Ports */ 7481 SOC_IF_ERROR_RETURN(WRITE_XPORT_MIB_RESETr(unit, blk_port, rval)); 7482 SOC_IF_ERROR_RETURN(WRITE_XPORT_MIB_RESETr(unit, blk_port, 0)); 7483 } 7484 /* WRED Configuration */ 7485 if ((dev_id != BCM56440_DEVICE_ID) && (dev_id != BCM56445_DEVICE_ID) && 7486 (dev_id != BCM56448_DEVICE_ID) && (dev_id != BCM55440_DEVICE_ID)) { /* And all other 90MHz variants */ 7487 SOC_IF_ERROR_RETURN(READ_WRED_MISCCONFIGr(unit, &rval)); 7488 soc_reg_field_set(unit, WRED_MISCCONFIGr, &rval, BASE_UPDATE_INTERVALf, 7); 7489 SOC_IF_ERROR_RETURN(WRITE_WRED_MISCCONFIGr(unit, rval)); 7490 7491 SOC_IF_ERROR_RETURN(READ_WRED_PARITY_ERROR_MASKr(unit, &rval)); 7492 soc_reg_field_set(unit, WRED_PARITY_ERROR_MASKr, &rval, UPDATE_INTRPT_MASKf, 0); 7493 SOC_IF_ERROR_RETURN(WRITE_WRED_PARITY_ERROR_MASKr(unit, rval)); 7494 7495 SOC_IF_ERROR_RETURN(READ_MISCCONFIGr(unit, &rval)); 7496 soc_reg_field_set(unit, MISCCONFIGr, &rval, REFRESH_ENf, 1); 7497 SOC_IF_ERROR_RETURN(WRITE_MISCCONFIGr(unit, rval)); 7498 } 7499 7500 if (parity_enable) { 7501 _soc_katana_parity_enable_all(unit, TRUE); 7502 } 7503 7504 /* Egress Logical to physical port map. 7505 For KT logical-port and physical-port are the same */ 7506 PBMP_ALL_ITER(unit, port) { 7507 rval = 0; 7508 soc_reg_field_set(unit, EGR_VLAN_LOGICAL_TO_PHYSICAL_MAPPINGr, &rval, 7509 PHYSICAL_PORT_NUMf, port); 7510 SOC_IF_ERROR_RETURN 7511 (WRITE_EGR_VLAN_LOGICAL_TO_PHYSICAL_MAPPINGr(unit, port, rval)); 7512 } 7513 7514 sal_memset(entry, 0, sizeof(cpu_pbm_entry_t)); 7515 soc_mem_pbmp_field_set(unit, CPU_PBMm, entry, BITMAPf, &PBMP_CMIC(unit)); 7516 SOC_IF_ERROR_RETURN 7517 (soc_mem_write(unit, CPU_PBMm, MEM_BLOCK_ALL, 0, entry)); 7518 7519 sal_memset(entry, 0, sizeof(cpu_pbm_2_entry_t)); 7520 soc_mem_pbmp_field_set(unit, CPU_PBM_2m, entry, BITMAPf, &PBMP_CMIC(unit)); 7521 SOC_IF_ERROR_RETURN 7522 (soc_mem_write(unit, CPU_PBM_2m, MEM_BLOCK_ALL, 0, entry)); 7523 7524 SOC_PBMP_CLEAR(pbmp); 7525 PBMP_ALL_ITER(unit, port) { 7526 if (IS_LB_PORT(unit, port) || 7527 (si->port_group[port] >= 2 && si->port_group[port] <= 3)) { 7528 SOC_PBMP_PORT_ADD(pbmp, port); 7529 } 7530 } 7531 7532 sal_memset(entry, 0, sizeof(egr_ing_port_entry_t)); 7533 soc_mem_field32_set(unit, EGR_ING_PORTm, entry, PORT_TYPEf, 1); 7534 PBMP_HG_ITER(unit, port) { 7535 SOC_IF_ERROR_RETURN 7536 (soc_reg_field32_modify(unit, XPORT_CONFIGr, port, HIGIG_MODEf, 7537 1)); 7538 SOC_IF_ERROR_RETURN 7539 (soc_mem_write(unit, EGR_ING_PORTm, MEM_BLOCK_ALL, port, entry)); 7540 } 7541 SOC_IF_ERROR_RETURN 7542 (soc_mem_write(unit, EGR_ING_PORTm, MEM_BLOCK_ALL, si->cpu_hg_index, 7543 entry)); 7544 soc_mem_field32_set(unit, EGR_ING_PORTm, entry, PORT_TYPEf, 2); 7545 SOC_IF_ERROR_RETURN 7546 (soc_mem_write(unit, EGR_ING_PORTm, MEM_BLOCK_ALL, LB_PORT(unit), 7547 entry)); 7548 7549 /* MXQPORT0 - 25 */ 7550 rval = 0; 7551 rval1 = 0; 7552 soc_reg_field_set(unit, XPORT_PORT_ENABLEr, &rval1, 7553 PORT0f, 1); /* Enable 1 port */ 7554 if (SOC_PORT_VALID(unit, 25)) { 7555 if (si->port_speed_max[25] < 10000) { 7556 soc_reg_field_set(unit, XPORT_MODE_REGr, &rval, 7557 PHY_PORT_MODEf, 2); 7558 /* No Quad Core port mode, since only one port is used */ 7559 soc_reg_field_set(unit, XPORT_MODE_REGr, &rval, 7560 CORE_PORT_MODEf, 0); 7561 soc_reg_field_set(unit, XPORT_MODE_REGr, &rval, 7562 PORT_GMII_MII_ENABLEf, 1); 7563 } 7564 SOC_IF_ERROR_RETURN(WRITE_XPORT_MODE_REGr(unit, 25, rval)); 7565 SOC_IF_ERROR_RETURN(WRITE_XPORT_PORT_ENABLEr(unit, 25, rval1)); 7566 } 7567 7568 /* MXQPORT1 - 26 */ 7569 rval = 0; 7570 rval1 = 0; 7571 soc_reg_field_set(unit, XPORT_PORT_ENABLEr, &rval1, 7572 PORT0f, 1); /* Enable 1 port */ 7573 if (SOC_PORT_VALID(unit, 26)) { 7574 if (si->port_speed_max[26] < 10000) { 7575 soc_reg_field_set(unit, XPORT_MODE_REGr, &rval, 7576 PHY_PORT_MODEf, 2); 7577 /* No Quad Core port mode, since only one port is used */ 7578 soc_reg_field_set(unit, XPORT_MODE_REGr, &rval, 7579 CORE_PORT_MODEf, 0); 7580 soc_reg_field_set(unit, XPORT_MODE_REGr, &rval, 7581 PORT_GMII_MII_ENABLEf, 1); 7582 } 7583 SOC_IF_ERROR_RETURN(WRITE_XPORT_MODE_REGr(unit, 26, rval)); 7584 SOC_IF_ERROR_RETURN(WRITE_XPORT_PORT_ENABLEr(unit, 26, rval1)); 7585 } 7586 7587 /* MXQPORT2 = 27,32,33,34 */ 7588 /* MXQPORT3 = 28,29,30,31 */ 7589 rval = 0; 7590 rval1 = 0; 7591 7592 for(mxq=2;mxq<=3;mxq++) { 7593 mxqport_used = 0; 7594 rval = 0; 7595 rval1 = 0; 7596 any_port = 0; 7597 7598 for (pindex = 0; pindex < 4; pindex++) { 7599 if (SOC_PORT_VALID(unit,last_two_mxqblock_ports[mxq-2][pindex])) { 7600 mxqport_used++; 7601 any_port = last_two_mxqblock_ports[mxq-2][pindex]; 7602 if (mxqport_used == 1) { 7603 SOC_IF_ERROR_RETURN(READ_XPORT_PORT_ENABLEr( 7604 unit, any_port, &rval1)); 7605 } 7606 soc_reg_field_set(unit, XPORT_PORT_ENABLEr, &rval1, 7607 port_field[pindex], 1); 7608 } 7609 } 7610 if (any_port != 0) { 7611 SOC_IF_ERROR_RETURN(READ_XPORT_MODE_REGr(unit, any_port, &rval)); 7612 if (mxqport_used == 1) { 7613 soc_reg_field_set(unit, XPORT_MODE_REGr, &rval, 7614 CORE_PORT_MODEf, 0); /* Single */ 7615 } else { /* Dual=1 is not valid for Katana device */ 7616 soc_reg_field_set(unit, XPORT_MODE_REGr, &rval, 7617 CORE_PORT_MODEf, 2); /* Quad */ 7618 } 7619 if (si->port_speed_max[any_port] < 10000) { /* Actually <=2500 */ 7620 soc_reg_field_set(unit, XPORT_MODE_REGr, &rval, 7621 PHY_PORT_MODEf, 2); /* Quad */ 7622 soc_reg_field_set(unit, XPORT_MODE_REGr, &rval, 7623 PORT_GMII_MII_ENABLEf, 1); 7624 } else { 7625 soc_reg_field_set(unit, XPORT_MODE_REGr, &rval, 7626 PHY_PORT_MODEf, 0); /* Single */ 7627 } 7628 SOC_IF_ERROR_RETURN(WRITE_XPORT_MODE_REGr(unit, any_port, rval)); 7629 SOC_IF_ERROR_RETURN(WRITE_XPORT_PORT_ENABLEr( 7630 unit, any_port, rval1)); 7631 if (mxqport_used > 0) { 7632 SOC_IF_ERROR_RETURN(READ_MISCCONFIGr(unit, &rval)); 7633 soc_reg_field_set(unit, MISCCONFIGr, &rval, 7634 xport_field[mxq-2], 1); 7635 SOC_IF_ERROR_RETURN(WRITE_MISCCONFIGr(unit, rval)); 7636 } 7637 } 7638 } 7639 7640 7641 count = 32; 7642 7643 /* Setup main TDM control */ 7644 SOC_IF_ERROR_RETURN(READ_IARB_TDM_CONTROLr(unit, &rval)); 7645 /* BCMSIM handles Single Cell packets */ 7646 if (SAL_BOOT_BCMSIM) { 7647 soc_reg_field_set(unit, IARB_TDM_CONTROLr, &rval, DISABLEf, 1); 7648 } else { 7649 soc_reg_field_set(unit, IARB_TDM_CONTROLr, &rval, DISABLEf, 0); 7650 } 7651 soc_reg_field_set(unit, IARB_TDM_CONTROLr, &rval, TDM_WRAP_PTRf, count); 7652 SOC_IF_ERROR_RETURN(WRITE_IARB_TDM_CONTROLr(unit, rval)); 7653 7654 _soc_katana_perq_flex_counters_init(unit); 7655 7656 SOC_IF_ERROR_RETURN(READ_MISCCONFIGr(unit, &rval)); 7657 soc_reg_field_set(unit, MISCCONFIGr, &rval, METERING_CLK_ENf, 1); 7658 SOC_IF_ERROR_RETURN(WRITE_MISCCONFIGr(unit, rval)); 7659 7660 if (0) { 7661 rval = 0; 7662 soc_reg_field_set(unit, ING_BYPASS_CTRLr, &rval, IFP_BYPASS_ENABLEf, 7663 1); 7664 SOC_IF_ERROR_RETURN(WRITE_ING_BYPASS_CTRLr(unit, rval)); 7665 7666 rval = 0; 7667 soc_reg_field_set(unit, EGR_BYPASS_CTRLr, &rval, EFP_BYPASSf, 1); 7668 SOC_IF_ERROR_RETURN(WRITE_EGR_BYPASS_CTRLr(unit, rval)); 7669 } 7670 7671 /* Enable dual hash on L2, L3 and MPLS_ENTRY tables */ 7672 fields[0] = ENABLEf; 7673 values[0] = 1; 7674 fields[1] = HASH_SELECTf; 7675 values[1] = FB_HASH_CRC32_LOWER; 7676 fields[2] = INSERT_LEAST_FULL_HALFf; 7677 values[2] = 1; 7678 SOC_IF_ERROR_RETURN 7679 (soc_reg_fields32_modify(unit, L2_AUX_HASH_CONTROLr, REG_PORT_ANY, 3, 7680 fields, values)); 7681 SOC_IF_ERROR_RETURN 7682 (soc_reg_fields32_modify(unit, L3_AUX_HASH_CONTROLr, REG_PORT_ANY, 3, 7683 fields, values)); 7684 SOC_IF_ERROR_RETURN 7685 (soc_reg_field32_modify(unit, MPLS_ENTRY_HASH_CONTROLr, REG_PORT_ANY, 7686 INSERT_LEAST_FULL_HALFf, 1)); 7687 7688 /* 7689 * IPMC init 7690 */ 7691 SOC_IF_ERROR_RETURN(READ_RQE_GLOBAL_CONFIGr(unit, &rval)); 7692 soc_reg_field_set(unit,RQE_GLOBAL_CONFIGr, &rval, PARITY_GEN_ENf, 7693 1); 7694 soc_reg_field_set(unit,RQE_GLOBAL_CONFIGr, &rval, PARITY_CHK_ENf, 7695 1); 7696 SOC_IF_ERROR_RETURN(WRITE_RQE_GLOBAL_CONFIGr(unit, rval)); 7697 7698 sal_memset(&ipmc_entry, 0, sizeof(mmu_ipmc_group_tbl0_entry_t)); 7699 count = soc_mem_index_count(unit, MMU_IPMC_GROUP_TBL0m); 7700 for (i=0; i < count; i++) { 7701 SOC_IF_ERROR_RETURN(WRITE_MMU_IPMC_GROUP_TBL0m(unit, 7702 MEM_BLOCK_ANY, i, &ipmc_entry)); 7703 } 7704 count = soc_mem_index_count(unit, MMU_IPMC_GROUP_TBL1m); 7705 for (i=0; i < count; i++) { 7706 SOC_IF_ERROR_RETURN(WRITE_MMU_IPMC_GROUP_TBL1m(unit, 7707 MEM_BLOCK_ANY, i, &ipmc_entry)); 7708 } 7709 count = soc_mem_index_count(unit, MMU_IPMC_GROUP_TBL2m); 7710 for (i=0; i < count; i++) { 7711 SOC_IF_ERROR_RETURN(WRITE_MMU_IPMC_GROUP_TBL2m(unit, 7712 MEM_BLOCK_ANY, i, &ipmc_entry)); 7713 } 7714 count = soc_mem_index_count(unit, MMU_IPMC_GROUP_TBL3m); 7715 for (i=0; i < count; i++) { 7716 SOC_IF_ERROR_RETURN(WRITE_MMU_IPMC_GROUP_TBL3m(unit, 7717 MEM_BLOCK_ANY, i, &ipmc_entry)); 7718 } 7719 count = soc_mem_index_count(unit, MMU_IPMC_GROUP_TBL4m); 7720 for (i=0; i < count; i++) { 7721 SOC_IF_ERROR_RETURN(WRITE_MMU_IPMC_GROUP_TBL4m(unit, 7722 MEM_BLOCK_ANY, i, &ipmc_entry)); 7723 } 7724 7725 sal_memset(&rqe_entry, 0, sizeof(mmu_rqe_queue_op_node_map_entry_t)); 7726 count = soc_mem_index_count(unit, MMU_RQE_QUEUE_OP_NODE_MAPm); 7727 for (i=0; i < count; i++) { 7728 SOC_IF_ERROR_RETURN(WRITE_MMU_RQE_QUEUE_OP_NODE_MAPm(unit, 7729 MEM_BLOCK_ANY, i, &rqe_entry)); 7730 } 7731 7732 sal_memset(&wred_entry, 0, sizeof(mmu_wred_queue_op_node_map_entry_t)); 7733 count = soc_mem_index_count(unit, MMU_WRED_QUEUE_OP_NODE_MAPm); 7734 for (i=0; i < count; i++) { 7735 SOC_IF_ERROR_RETURN(WRITE_MMU_WRED_QUEUE_OP_NODE_MAPm(unit, 7736 MEM_BLOCK_ANY, i, &wred_entry)); 7737 } 7738 7739 sal_memset(&mc_group_entry, 0, sizeof(mmu_ext_mc_group_map_entry_t)); 7740 count = soc_mem_index_count(unit, MMU_EXT_MC_GROUP_MAPm); 7741 for (i=0; i < count; i++) { 7742 SOC_IF_ERROR_RETURN(WRITE_MMU_EXT_MC_GROUP_MAPm(unit, 7743 MEM_BLOCK_ANY, i, &mc_group_entry)); 7744 } 7745 7746 sal_memset(&mc_list0_entry, 0, sizeof(mmu_ext_mc_queue_list0_entry_t)); 7747 count = soc_mem_index_count(unit, MMU_EXT_MC_QUEUE_LIST0m); 7748 for (i=0; i < count; i++) { 7749 SOC_IF_ERROR_RETURN(WRITE_MMU_EXT_MC_QUEUE_LIST0m(unit, 7750 MEM_BLOCK_ANY, i, &mc_list0_entry)); 7751 } 7752 7753 sal_memset(&mc_list1_entry, 0, sizeof(mmu_ext_mc_queue_list1_entry_t)); 7754 count = soc_mem_index_count(unit, MMU_EXT_MC_QUEUE_LIST1m); 7755 for (i=0; i < count; i++) { 7756 SOC_IF_ERROR_RETURN(WRITE_MMU_EXT_MC_QUEUE_LIST1m(unit, 7757 MEM_BLOCK_ANY, i, &mc_list1_entry)); 7758 } 7759 7760 sal_memset(&mc_list4_entry, 0, sizeof(mmu_ext_mc_queue_list4_entry_t)); 7761 count = soc_mem_index_count(unit, MMU_EXT_MC_QUEUE_LIST4m); 7762 for (i=0; i < count; i++) { 7763 SOC_IF_ERROR_RETURN(WRITE_MMU_EXT_MC_QUEUE_LIST4m(unit, 7764 MEM_BLOCK_ANY, i, &mc_list4_entry)); 7765 } 7766 7767 /* 7768 * Egress Enable 7769 */ 7770 sal_memset(entry, 0, sizeof(egr_enable_entry_t)); 7771 soc_mem_field32_set(unit, EGR_ENABLEm, entry, PRT_ENABLEf, 1); 7772 PBMP_ALL_ITER(unit, port) { 7773 SOC_IF_ERROR_RETURN 7774 (WRITE_EGR_ENABLEm(unit, MEM_BLOCK_ALL, port, entry)); 7775 } 7776 7777 /* GMAC init should be moved to mac */ 7778 rval = 0; 7779 soc_reg_field_set(unit, GPORT_CONFIGr, &rval, CLR_CNTf, 1); 7780 soc_reg_field_set(unit, GPORT_CONFIGr, &rval, GPORT_ENf, 1); 7781 PBMP_E_ITER(unit, port) { 7782 if (IS_MXQ_PORT(unit, port)) { 7783 continue; 7784 } 7785 SOC_IF_ERROR_RETURN(WRITE_GPORT_CONFIGr(unit, port, rval)); 7786 } 7787 soc_reg_field_set(unit, GPORT_CONFIGr, &rval, CLR_CNTf, 0); 7788 PBMP_E_ITER(unit, port) { 7789 if (IS_MXQ_PORT(unit, port)) { 7790 continue; 7791 } 7792 SOC_IF_ERROR_RETURN(WRITE_GPORT_CONFIGr(unit, port, rval)); 7793 } 7794 7795 sal_memset(entry, 0, sizeof(epc_link_bmap_entry_t)); 7796 soc_mem_pbmp_field_set(unit, EPC_LINK_BMAPm, entry, PORT_BITMAPf, 7797 &PBMP_CMIC(unit)); 7798 SOC_IF_ERROR_RETURN(WRITE_EPC_LINK_BMAPm(unit, MEM_BLOCK_ALL, 0, entry)); 7799 7800 SOC_IF_ERROR_RETURN(READ_ING_CONFIG_64r(unit, ®64)); 7801 soc_reg64_field32_set(unit, ING_CONFIG_64r, ®64, 7802 L3SRC_HIT_ENABLEf, 1); 7803 soc_reg64_field32_set(unit, ING_CONFIG_64r, ®64, 7804 L2DST_HIT_ENABLEf, 1); 7805 soc_reg64_field32_set(unit, ING_CONFIG_64r, ®64, 7806 APPLY_EGR_MASK_ON_L2f, 1); 7807 soc_reg64_field32_set(unit, ING_CONFIG_64r, ®64, 7808 APPLY_EGR_MASK_ON_L3f, 1); 7809 soc_reg64_field32_set(unit, ING_CONFIG_64r, ®64, 7810 ARP_RARP_TO_FPf, 0x3); /* enable both ARP & RARP */ 7811 soc_reg64_field32_set(unit, ING_CONFIG_64r, ®64, 7812 ARP_VALIDATION_ENf, 1); 7813 soc_reg64_field32_set(unit, ING_CONFIG_64r, ®64, 7814 IGNORE_HG_HDR_LAG_FAILOVERf, 1); 7815 SOC_IF_ERROR_RETURN(WRITE_ING_CONFIG_64r(unit, reg64)); 7816 7817 /* set to allow Mirror bit in Module Header */ 7818 SOC_IF_ERROR_RETURN 7819 (soc_reg_field32_modify(unit, EGR_CONFIG_1r, REG_PORT_ANY, 7820 RING_MODEf, 1)); 7821 7822 7823 /* The HW defaults for EGR_VLAN_CONTROL_1.VT_MISS_UNTAG == 1, which 7824 * causes the outer tag to be removed from packets that don't have 7825 * a hit in the egress vlan tranlation table. Set to 0 to disable this. 7826 */ 7827 rval = 0; 7828 soc_reg_field_set(unit, EGR_VLAN_CONTROL_1r, &rval, VT_MISS_UNTAGf, 0); 7829 7830 /* Enable pri/cfi remarking on egress ports. */ 7831 soc_reg_field_set(unit, EGR_VLAN_CONTROL_1r, &rval, REMARK_OUTER_DOT1Pf, 7832 1); 7833 PBMP_ALL_ITER(unit, port) { 7834 SOC_IF_ERROR_RETURN(WRITE_EGR_VLAN_CONTROL_1r(unit, port, rval)); 7835 } 7836 7837 SOC_PBMP_ASSIGN(pbmp, PBMP_ALL(unit)); 7838 SOC_PBMP_REMOVE(pbmp, PBMP_LB(unit)); 7839 SOC_IF_ERROR_RETURN(soc_mem_read(unit, ING_EN_EFILTER_BITMAPm, 7840 MEM_BLOCK_ANY, 0, &entry)); 7841 soc_mem_pbmp_field_set(unit, ING_EN_EFILTER_BITMAPm, &entry, BITMAPf, 7842 &pbmp); 7843 SOC_IF_ERROR_RETURN(soc_mem_write(unit, ING_EN_EFILTER_BITMAPm, 7844 MEM_BLOCK_ANY, 0, &entry)); 7845 7846 /* coverity[result_independent_of_operands] */ 7847 SOC_IF_ERROR_RETURN(READ_CMIC_TXBUF_CONFIGr(unit, &rval)); 7848 soc_reg_field_set(unit, CMIC_TXBUF_CONFIGr, &rval, 7849 FIRST_SERVE_BUFFERS_WITH_EOP_CELLSf, 0); 7850 /* coverity[result_independent_of_operands] */ 7851 SOC_IF_ERROR_RETURN(WRITE_CMIC_TXBUF_CONFIGr(unit, rval)); 7852 7853 /* Multicast range initialization */ 7854 SOC_IF_ERROR_RETURN 7855 (soc_hbx_higig2_mcast_sizes_set(unit, 7856 soc_property_get(unit, spn_HIGIG2_MULTICAST_VLAN_RANGE, 7857 SOC_HBX_MULTICAST_RANGE_DEFAULT), 7858 soc_property_get(unit, spn_HIGIG2_MULTICAST_L2_RANGE, 7859 SOC_HBX_MULTICAST_RANGE_DEFAULT), 7860 soc_property_get(unit, spn_HIGIG2_MULTICAST_L3_RANGE, 7861 SOC_HBX_MULTICAST_RANGE_DEFAULT))); 7862 7863 /* 7864 * Set the per-chip STORM_CONTROL_METER_MAPPING register for now: 7865 * 0th meter - BCAST 7866 * 1st meter - MCAST (including UNKNOWN/KNOWN and IPMC/L2MC); 7867 * 2rd meter - DLF. 7868 * The rate APIs rely on above setting. 7869 */ 7870 { 7871 soc_field_t fields[] = { BCAST_METER_INDEXf, KNOWN_L2MC_METER_INDEXf, 7872 UNKNOWN_L2MC_METER_INDEXf, KNOWN_IPMC_METER_INDEXf, 7873 UNKNOWN_IPMC_METER_INDEXf, DLFBC_METER_INDEXf }; 7874 uint32 values[] = { 0, 1, 1, 1, 1, 2 }; 7875 7876 7877 SOC_IF_ERROR_RETURN 7878 (soc_reg_fields32_modify(unit, STORM_CONTROL_METER_MAPPINGr, 7879 REG_PORT_ANY, COUNTOF(values), fields, values)); 7880 7881 /* Enable vrf based l3 lookup by default. */ 7882 SOC_IF_ERROR_RETURN 7883 (soc_reg_field32_modify(unit, VRF_MASKr, REG_PORT_ANY, MASKf, 0)); 7884 7885 /* Setup SW2_FP_DST_ACTION_CONTROL */ 7886 fields[0] = HGTRUNK_RES_ENf; 7887 fields[1] = LAG_RES_ENf; 7888 values[0] = values[1] = 1; 7889 SOC_IF_ERROR_RETURN(soc_reg_fields32_modify(unit, 7890 SW2_FP_DST_ACTION_CONTROLr, REG_PORT_ANY, 2, fields, values)); 7891 } 7892 7893 /* initialize LED UP0 */ 7894 if (!SOC_WARM_BOOT(unit)) { 7895 SOC_IF_ERROR_RETURN(_katana_ledup_init(unit)); 7896 } 7897 7898 if (soc_mspi_init(unit) != SOC_E_NONE) { 7899 LOG_WARN(BSL_LS_SOC_COMMON, 7900 (BSL_META_U(unit, 7901 "unit %d : MSPI Init Failed\n"), unit)); 7902 } 7903 7904 #define RECONFIGURE_PORT_TYPE_INFO(ptype) \ 7905 si->ptype.num = 0; \ 7906 si->ptype.min = si->ptype.max = -1; \ 7907 PBMP_ITER(si->ptype.bitmap, it_port) { \ 7908 si->ptype.port[si->ptype.num++] = it_port; \ 7909 if (si->ptype.min < 0) { \ 7910 si->ptype.min = it_port; \ 7911 } \ 7912 if (it_port > si->ptype.max) { \ 7913 si->ptype.max = it_port; \ 7914 } \ 7915 } 7916 7917 if (soc_feature(unit, soc_feature_ces)) { 7918 /* 7919 * Add CES TDM ports 7920 */ 7921 for (i = 0;i < 16;i++) { 7922 int port = 39 + i; 7923 SOC_PBMP_PORT_ADD(si->tdm_pbm, port); 7924 si->tdm.port[si->tdm.num++] = port; 7925 if (si->tdm.min > port || si->tdm.min < 0) { 7926 si->tdm.min = port; 7927 } 7928 if (si->tdm.max < port) { 7929 si->tdm.max = port; 7930 } 7931 SOC_PBMP_PORT_ADD(si->tdm.bitmap, port); 7932 } 7933 } else { 7934 /* 7935 * If there is no CES then remove port 1 from the bitmaps 7936 */ 7937 if (dev_id == BCM56441_DEVICE_ID || 7938 dev_id == BCM56442_DEVICE_ID || 7939 dev_id == BCM56443_DEVICE_ID) { 7940 SOC_PBMP_PORT_REMOVE(si->ge.bitmap, 1); 7941 SOC_PBMP_PORT_REMOVE(si->ether.bitmap, 1); 7942 SOC_PBMP_PORT_REMOVE(si->port.bitmap, 1); 7943 SOC_PBMP_PORT_REMOVE(si->all.bitmap, 1); 7944 RECONFIGURE_PORT_TYPE_INFO(ether); 7945 RECONFIGURE_PORT_TYPE_INFO(ge); 7946 RECONFIGURE_PORT_TYPE_INFO(port); 7947 RECONFIGURE_PORT_TYPE_INFO(all); 7948 soc_dport_map_update(unit); 7949 } 7950 } 7951 7952 if (parity_enable) { 7953 SOC_IF_ERROR_RETURN(soc_generic_ser_mem_scan_start(unit)); 7954 } 7955 7956 /* LED Scan operation needs all GPORT_UMAC_CONTROLr out of reset. 7957 * Irrespective of the block has a valid port. So, use raw addresses 7958 */ 7959 { 7960 /* GPORT_UMAC_CONTROL.gport0 */ 7961 SOC_IF_ERROR_RETURN(soc_reg32_write(unit, 0x680049, 0xff)); 7962 /* GPORT_UMAC_CONTROL.gport1 */ 7963 SOC_IF_ERROR_RETURN(soc_reg32_write(unit, 0x780049, 0xff)); 7964 /* GPORT_UMAC_CONTROL.gport2 */ 7965 SOC_IF_ERROR_RETURN(soc_reg32_write(unit, 0x880049, 0xff)); 7966 sal_udelay(10); 7967 SOC_IF_ERROR_RETURN(soc_reg32_write(unit, 0x680049, 0x0)); 7968 SOC_IF_ERROR_RETURN(soc_reg32_write(unit, 0x780049, 0x0)); 7969 SOC_IF_ERROR_RETURN(soc_reg32_write(unit, 0x880049, 0x0)); 7970 } 7971 7972 return SOC_E_NONE; 7973 } 7974 7975 #define KT_MMU_EFIFO_DEPTH 10 7976 #define KT_MMU_EFIFO_XMIT_THERESHOLD 4 7977 7978 /********************************************************* 7979 * KATANA MMU HELPER --- START 7980 */ 7981 7982 /* Based on Katana_MMU_Settings-v7.xls */ 7983 7984 #define KA_MMU_MIN_PKT_SIZE 64 /*(bytes) c5*/ 7985 #define KA_MMU_ETHERNET_MTU_BYTES 1536 /*(bytes) c6*/ 7986 #define KA_MMU_MAX_PKT_SIZE 9216/*(bytes) c7*/ 7987 #define KA_MMU_JUMBO_FRAME 9216/*(bytes) c8*/ 7988 #define KA_MMU_INT_BUF_CELL_SIZE 192/*(bytes) c9*/ 7989 #define KA_MMU_EXT_BUF_CELL_SIZE 768/*(bytes) c10*/ 7990 #define KA_MMU_PKT_HEADER_SIZE 52/*(bytes) c11*/ 7991 #define KA_MMU_LOSSLESS_PG_NUM 1/*c15*/ 7992 #define KA_MMU_NUM_CPU_PORT 1/*c30*/ 7993 #define KA_MMU_NUM_CPU_QUEUE 48/*c31*/ 7994 #define KA_MMU_NUM_LB_PORT 1/*c33*/ 7995 #define KA_MMU_NUM_LB_QUEUE 8/*c34*/ 7996 #define KA_MMU_NUM_EGRESS_QUEUE_IN_DEVICE 4096/*c36*/ 7997 #define SB_MMU_INT_BUF_SIZE 512/*(MB)*/ 7998 #define KA_MMU_INT_BUF_SIZE 2048/*(MB) c37 "10924cells*192/1024"*/ 7999 #define KA_MMU_RESERVED_INT_BUF_SPACE_CFAP 8 /*(MB) c38 "44cells*192/1024" */ 8000 #define SB_MMU_EXT_BUF_SIZE 96/*(MB)*/ 8001 #define KA_MMU_EXT_BUF_SIZE 192/*(MB) c42*/ 8002 #define KA_MMU_RESERVED_EXT_BUF_SPACE_CFAP 1535 /*cells c43*/ 8003 #define SB_MMU_EGRESS_QUEUE_ENTRIES 128/*(K)*/ 8004 #define KA_MMU_EGRESS_QUEUE_ENTRIES 256/*(K)c44*/ 8005 #define KA_MMU_RE_WORK_QUEUE_ENTRIES 8/*(K)c46*/ 8006 #define KA_MMU_RESERVED_RE_WORK_QUEUE_ENTRIES 292 /*c47*/ 8007 #define KA_MMU_RE_WORK_QUEUES_IN_DEVICE 3/*c48*/ 8008 #define KA_MMU_EMA_QUEUES 8/*c49*/ 8009 #define KA_MMU_ING_PORT_DYN_THD_PARAM 2 /*c53*/ 8010 #define KA_MMU_ING_PG_DYN_THD_PARAM 7 /*c54*/ 8011 #define KA_MMU_EGR_QUEUE_DYN_THD_PARAM (0.25) /*c55*/ 8012 #define KA_MMU_EGR_QUEUE_DYN_THD_PARAM_LOSSY 4 /*c56*/ 8013 #define KA_MMU_ING_CELL_BUF_REDUCTION 0/*c57*/ 8014 #define KA_MMU_ING_PKT_BUF_REDUCTION 0/*c58*/ 8015 #define SB_MMU_CFAP_THDIO_LATENCY 20 8016 8017 /* Intermediate Results */ 8018 #define KA_MMU_MAX_PKT_SIZE_IN_CELLS (((KA_MMU_MAX_PKT_SIZE + \ 8019 KA_MMU_PKT_HEADER_SIZE) / \ 8020 KA_MMU_INT_BUF_CELL_SIZE) + 1)/*c67*/ 8021 #define KA_MMU_JUMBO_FRAME_INT_BUF (((KA_MMU_JUMBO_FRAME + \ 8022 KA_MMU_PKT_HEADER_SIZE) / \ 8023 KA_MMU_INT_BUF_CELL_SIZE) + 1)/*c68*/ 8024 #define KA_MMU_JUMBO_FRAME_EXT_BUF (((KA_MMU_JUMBO_FRAME + \ 8025 KA_MMU_PKT_HEADER_SIZE) / \ 8026 KA_MMU_EXT_BUF_CELL_SIZE) + 1)/*c69*/ 8027 8028 #define KA_MMU_EXT_BUF_TO_INT_BUF_RATIO (KA_MMU_EXT_BUF_CELL_SIZE / \ 8029 KA_MMU_INT_BUF_CELL_SIZE) /*c95*/ 8030 8031 #define KA_MMU_CELL_PER_AVG_PKT_INT_BUF 1 /*c96*/ 8032 #define KA_MMU_CELL_PER_AVG_PKT_EXT_BUF 1 /*c97*/ 8033 8034 typedef struct _soc_ka_mmu_params { 8035 uint32 lossless_mode; 8036 uint32 extbuf_used; /*c16*/ 8037 uint32 num_ge_ports;/*c18*/ 8038 uint32 num_hg_ports;/*c24*/ 8039 uint32 available_intbuf; /*c39 portion of total internal buffer */ 8040 uint32 available_emapool; /*c40 portion of total internal buffer */ 8041 uint32 num_replication_per_pkt; /*c45*/ 8042 /* Input Port Thresholds */ 8043 uint32 hg_pg_hdrm_intbuf;/*108*/ 8044 uint32 hg_pg_hdrm_ema;/*109*/ 8045 uint32 hg_pg_hdrm_extbuf;/*110*/ 8046 uint32 hg_pg_hdrm_rewqe;/*111*/ 8047 uint32 ge_pg_hdrm_intbuf;/*118*/ 8048 uint32 ge_pg_hdrm_ema;/*119*/ 8049 uint32 ge_pg_hdrm_extbuf;/*120*/ 8050 uint32 ge_pg_hdrm_rewqe;/*121*/ 8051 uint32 cpu_pg_hdrm_intbuf;/*128*/ 8052 uint32 cpu_pg_hdrm_ema;/*129*/ 8053 uint32 cpu_pg_hdrm_extbuf;/*130*/ 8054 uint32 cpu_pg_hdrm_rewqe;/*131*/ 8055 uint32 cpu_pg_hdrm_eqe;/*132*/ 8056 uint32 lb_pg_hdrm_intbuf;/*133*/ 8057 uint32 lb_pg_hdrm_ema;/*134*/ 8058 uint32 lb_pg_hdrm_extbuf;/*135*/ 8059 uint32 lb_pg_hdrm_rewqe;/*136*/ 8060 uint32 lb_pg_hdrm_eqe;/*137*/ 8061 } _soc_ka_mmu_params_t; 8062 8063 /* Helper function for MMU settings based on 8064 * memory selection (internal/external/both) and mode (lossless/lossy) 8065 * The memory selection is done using config variable 'pbmp_ext_mem' 8066 * and the mode is selected based on config variable 'lossless_mode' 8067 */ 8068 STATIC int 8069 _soc_katana_mmu_init_helper(int unit) 8070 { 8071 _soc_ka_mmu_params_t ka_mmu_params; 8072 uint32 mmu_egr_queue_dyn_thd_param_lossy = 0; /*c56 */ 8073 /* Intermediate Results */ 8074 uint32 ethernet_mtu_cells_intbuf = 0;/*c71*/ 8075 uint32 ethernet_mtu_cells_extbuf = 0;/*c72*/ 8076 uint32 num_ports = 0; /*data ports+cpu+loopback, c74*/ 8077 uint32 num_data_ports = 0; /*data ports only, c75*/ 8078 uint32 num_eqe_geports_intbuf_bound = 0;/*c77*/ 8079 uint32 num_eqe_geports_extbuf_bound = 0;/*c78*/ 8080 uint32 num_eqe_hgports_intbuf_bound = 0;/*c79*/ 8081 uint32 num_eqe_hgports_extbuf_bound = 0;/*c80*/ 8082 uint32 total_queue_intbuf_bound = 0;/*c83*/ 8083 uint32 total_queue_extbuf_bound = 0;/*c84*/ 8084 uint32 num_ema_queue = 0;/*c85*/ 8085 uint32 total_eqe_device = 0;/*c87*/ 8086 uint32 max_intbuf_size;/*(cells)c88*/ 8087 uint32 intbuf_pool_size = 0;/*(cells)c90 for both ingress and egress buffer */ 8088 uint32 emapool_size = 0; /*(cells) c91*/ 8089 uint32 extbuf_size = 0;/*(cells) c92*/ 8090 uint32 rewqe_entries_admission = 0; /*c93*/ 8091 /* Input port thresholds */ 8092 uint32 ipthd_global_hdrm_intbuf = 0;/*c103*/ 8093 uint32 ipthd_global_hdrm_extbuf = 0;/*c105*/ 8094 uint32 ipthd_global_hdrm_ema = 0;/*c104*/ 8095 uint32 ipthd_global_hdrm_rewqe = 0;/*c106*/ 8096 uint32 ipthd_global_hdrm_eqe = 0; /*c107*/ 8097 8098 uint32 ipthd_hg_pg_hdrm_eqe = 0;/*c112*/ 8099 8100 uint32 ipthd_hg_total_hdrm_intbuf = 0;/*c113*/ 8101 uint32 ipthd_hg_total_hdrm_extbuf = 0;/*c115*/ 8102 uint32 ipthd_hg_total_hdrm_ema = 0;/*c114*/ 8103 uint32 ipthd_hg_total_hdrm_rewqe = 0;/*c116*/ 8104 uint32 ipthd_hg_total_hdrm_eqe = 0;/*c117*/ 8105 8106 uint32 ipthd_ge_pg_hdrm_eqe = 0;/*c122*/ 8107 8108 uint32 ipthd_ge_total_hdrm_intbuf = 0;/*c123*/ 8109 uint32 ipthd_ge_total_hdrm_extbuf = 0;/*c125*/ 8110 uint32 ipthd_ge_total_hdrm_ema = 0;/*c124*/ 8111 uint32 ipthd_ge_total_hdrm_rewqe = 0;/*c126*/ 8112 uint32 ipthd_ge_total_hdrm_eqe = 0;/*c127*/ 8113 8114 uint32 ipthd_total_hdrm_intbuf = 0;/*c138*/ 8115 uint32 ipthd_total_hdrm_extbuf = 0;/*c140*/ 8116 uint32 ipthd_total_hdrm_ema = 0;/*c139*/ 8117 uint32 ipthd_total_hdrm_rewqe = 0;/*c141*/ 8118 uint32 ipthd_total_hdrm_eqe = 0;/*142*/ 8119 8120 uint32 ipthd_per_pg_min_intbuf_ingpool = 0;/*c144*/ 8121 uint32 ipthd_per_pg_min_intbuf_ingpool_pg_0_6 = 0;/*c145*/ 8122 uint32 ipthd_per_pg_min_intbuf_emapool = 0;/*c146*/ 8123 uint32 ipthd_per_pg_min_extbuf = 0;/*c147*/ 8124 uint32 ipthd_per_pg_min_rewqe = 0;/*c148*/ 8125 uint32 ipthd_per_pg_min_eqe = 0;/*c149*/ 8126 8127 uint32 ipthd_total_pg_min_intbuf_ingpool = 0;/*c151*/ 8128 uint32 ipthd_total_pg_min_intbuf_emapool = 0;/*c152*/ 8129 uint32 ipthd_total_pg_min_extbuf = 0;/*c153*/ 8130 uint32 ipthd_total_pg_min_rewqe = 0;/*c154*/ 8131 uint32 ipthd_total_pg_min_eqe = 0;/*c155*/ 8132 8133 uint32 ipthd_per_port_min_intbuf_ingpool = 0;/*c157*/ 8134 uint32 ipthd_per_port_min_intbuf_emapool = 0;/*c158*/ 8135 uint32 ipthd_per_port_min_extbuf = 0;/*c159*/ 8136 uint32 ipthd_per_port_min_rewqe = 0;/*c160*/ 8137 uint32 ipthd_per_port_min_eqe = 0;/*c161*/ 8138 8139 uint32 ipthd_total_port_min_intbuf_ingpool = 0;/*c163*/ 8140 uint32 ipthd_total_port_min_intbuf_emapool = 0;/*c164*/ 8141 uint32 ipthd_total_port_min_extbuf = 0;/*c165*/ 8142 uint32 ipthd_total_port_min_rewqe = 0;/*c166*/ 8143 uint32 ipthd_total_port_min_eqe = 0;/*c167*/ 8144 8145 uint32 ipthd_total_min_intbuf_ingpool = 0;/*c169*/ 8146 uint32 ipthd_total_min_intbuf_emapool = 0;/*c170*/ 8147 uint32 ipthd_total_min_extbuf = 0;/*c171*/ 8148 uint32 ipthd_total_min_rewqe = 0;/*c172*/ 8149 uint32 ipthd_total_min_eqe = 0;/*c173*/ 8150 8151 uint32 ipthd_total_shared_intbuf_ingpool = 0;/*c175*/ 8152 uint32 ipthd_total_shared_intbuf_emapool = 0;/*c176*/ 8153 uint32 ipthd_total_shared_extbuf = 0;/*c177*/ 8154 uint32 ipthd_total_shared_rewqe = 0;/*c178*/ 8155 uint32 ipthd_total_shared_eqe = 0;/*c179*/ 8156 8157 /* output port thresholds */ 8158 uint32 opthd_port_min_grntee_queue_intbuf = 0;/*c193*/ 8159 uint32 opthd_port_min_grntee_queue_extbuf = 0;/*c194*/ 8160 uint32 opthd_port_min_grntee_eqe = 0;/*c195*/ 8161 uint32 opthd_port_min_grntee_ema_queue = 0; /*c196*/ 8162 uint32 opthd_port_min_grntee_rewqe = 0;/*c197*/ 8163 uint32 opthd_port_min_grntee_rewqe_intbuf_mc = 0;/*c198*/ 8164 uint32 opthd_port_min_grntee_rewqe_intbuf_tocpu = 0;/*c199*/ 8165 uint32 opthd_port_min_grntee_rewqe_intbuf_mirror = 0;/*c200*/ 8166 uint32 opthd_port_min_grntee_rewqe_extbuf = 0;/*c201*/ 8167 8168 uint32 opthd_total_min_grntee_queue_intbuff = 0;/*c204*/ 8169 uint32 opthd_total_min_grntee_queue_extbuff = 0;/*c205*/ 8170 uint32 opthd_total_min_grntee_eqe = 0;/*c206*/ 8171 uint32 opthd_total_min_grntee_ema_queue = 0;/*c207*/ 8172 uint32 opthd_total_min_grntee_rewqe = 0;/*c208*/ 8173 uint32 opthd_total_min_grntee_rewqe_intbuf = 0;/*c209*/ 8174 uint32 opthd_total_min_grntee_rewqe_extbuf = 0;/*c210*/ 8175 8176 uint32 opthd_total_shared_queue_intbuff = 0;/*c213*/ 8177 uint32 opthd_total_shared_queue_extbuff = 0;/*c214*/ 8178 uint32 opthd_total_shared_queue_eqe = 0;/*c215*/ 8179 uint32 opthd_total_shared_queue_ema_queue = 0;/*c216*/ 8180 uint32 opthd_total_shared_queue_rewqe = 0;/*c217*/ 8181 uint32 opthd_total_shared_queue_rewqe_intbuf = 0;/*c218*/ 8182 uint32 opthd_total_shared_queue_rewqe_extbuf = 0;/*c219*/ 8183 8184 uint32 mmu_egress_queue_entries = 0; 8185 uint32 ext_mem_port_count = 0; 8186 uint32 valid_port_count = 0; 8187 uint32 all_int_mem_port = 0; 8188 uint32 all_ext_mem_port = 0; 8189 uint32 int_ext_mem_port = 0; 8190 uint32 lossless = 0; 8191 uint32 rval = 0, val = 0; 8192 uint32 i = 0, j = 0, pg_num = 0, opn_index = 0; 8193 uint32 q_min = 0, q_color_dyn = 0; 8194 uint32 entry[SOC_MAX_MEM_WORDS]; 8195 uint64 r64val, val64; 8196 soc_port_t port; 8197 soc_info_t *si; 8198 soc_pbmp_t temp_pbmp; 8199 int saber_mmu_ext_buf_size = 0; 8200 uint16 dev_id = 0; 8201 uint8 rev_id = 0; 8202 8203 soc_cm_get_id(unit, &dev_id, &rev_id); 8204 8205 mmu_egress_queue_entries = KA_MMU_EGRESS_QUEUE_ENTRIES; /*256K */ 8206 if ((dev_id == BCM56240_DEVICE_ID) || 8207 (dev_id == BCM56241_DEVICE_ID) || 8208 (dev_id == BCM56242_DEVICE_ID) || 8209 (dev_id == BCM56243_DEVICE_ID)) { 8210 saber_mmu_ext_buf_size = SB_MMU_EXT_BUF_SIZE; /* 96 MB */ 8211 mmu_egress_queue_entries = SB_MMU_EGRESS_QUEUE_ENTRIES; /*128K */ 8212 } 8213 8214 if ((dev_id == BCM56245_DEVICE_ID) || 8215 (dev_id == BCM56246_DEVICE_ID)) { 8216 saber_mmu_ext_buf_size = KA_MMU_EXT_BUF_SIZE; /* 192 MB */ 8217 } 8218 8219 COMPILER_64_ZERO(r64val); 8220 COMPILER_64_ZERO(val64); 8221 8222 si = &SOC_INFO(unit); 8223 sal_memset(&ka_mmu_params, 0, sizeof(_soc_ka_mmu_params_t)); 8224 ka_mmu_params.lossless_mode = (soc_property_get(unit, spn_LOSSLESS_MODE, 0) | 8225 soc_property_get(unit, spn_MMU_LOSSLESS, 0)); 8226 lossless = ka_mmu_params.lossless_mode; 8227 SOC_PBMP_COUNT(PBMP_EXT_MEM (unit), ext_mem_port_count); 8228 SOC_PBMP_COUNT(PBMP_PORT_ALL (unit), valid_port_count); 8229 8230 all_int_mem_port = (ext_mem_port_count == 0) ? 1 : 0; 8231 all_ext_mem_port = (ext_mem_port_count >= valid_port_count) ? 1 : 0; 8232 8233 if ((all_int_mem_port == 0) && (all_ext_mem_port == 0)) { 8234 int_ext_mem_port = 1; 8235 } 8236 8237 /* In lossless mode Katana is cnfigured to accept packets 8238 * only if sufficient processing resources are guaranteed for all ports. 8239 * This may decrease overall throughput, 8240 * but no accepted packets will be dropped. 8241 * In Lossy mode Katana is configured to accept the maximum number of 8242 * packets per port, but may drop them if resources are oversubscribed 8243 * due to activity from other ports. 8244 */ 8245 8246 ka_mmu_params.num_ge_ports = si->ge.num + si->fe.num; /* c18*/ 8247 ka_mmu_params.num_hg_ports = si->hg.num + si->xe.num;/*c24*/ 8248 8249 ka_mmu_params.num_replication_per_pkt = 8250 ka_mmu_params.num_ge_ports + ka_mmu_params.num_hg_ports - 1; /*c45, c46-SBv7*/ 8251 8252 mmu_egr_queue_dyn_thd_param_lossy = KA_MMU_EGR_QUEUE_DYN_THD_PARAM_LOSSY; 8253 8254 if (all_int_mem_port) { 8255 ka_mmu_params.extbuf_used = 0;/*c16*/ 8256 ka_mmu_params.available_intbuf = 100;/*c39*/ 8257 ka_mmu_params.hg_pg_hdrm_intbuf = (lossless) ? 172 : 0; /*(cells)c108 */ 8258 ka_mmu_params.hg_pg_hdrm_ema = 0; /*c109 */ 8259 ka_mmu_params.hg_pg_hdrm_extbuf = 0;/*c110*/ 8260 ka_mmu_params.hg_pg_hdrm_rewqe = (lossless) ? 157: 0;/*(pkts)c111*/ 8261 8262 ka_mmu_params.ge_pg_hdrm_intbuf = (lossless) ? 127 : 0;/*(cells)c118*/ 8263 ka_mmu_params.ge_pg_hdrm_ema = 0;/*c119*/ 8264 ka_mmu_params.ge_pg_hdrm_extbuf = 0;/*c120*/ 8265 ka_mmu_params.ge_pg_hdrm_rewqe = (lossless) ? 114 : 0;/*(pkts)c121*/ 8266 } else if (all_ext_mem_port) { 8267 ka_mmu_params.extbuf_used = 1;/*c16*/ 8268 8269 if (soc_feature(unit, soc_feature_mmu_reduced_internal_buffer)) { 8270 /*Saber*/ 8271 ka_mmu_params.available_intbuf = 50; /*c40-SBv7*/ 8272 } else { 8273 /* Katana */ 8274 ka_mmu_params.available_intbuf = (lossless) ? 8275 ((si->ether.num > 8) ? 30 : 25) : 20;/*c39*/ 8276 } 8277 ka_mmu_params.hg_pg_hdrm_intbuf = (lossless) ? 76 : 0; /*(cells)c108*/ 8278 if (soc_feature(unit, soc_feature_mmu_reduced_internal_buffer)) { 8279 /*Saber*/ 8280 ka_mmu_params.hg_pg_hdrm_ema = (lossless) ? 76 : 0; /*(cells)c109*/ 8281 } else { 8282 ka_mmu_params.hg_pg_hdrm_ema = (lossless) ? 172 : 0; /*(cells)c109*/ 8283 } 8284 ka_mmu_params.hg_pg_hdrm_extbuf = (lossless) ? 159 : 0;/*(cells)c110*/ 8285 ka_mmu_params.hg_pg_hdrm_rewqe= (lossless) ? 157 : 0;/*(pkts)c111*/ 8286 8287 ka_mmu_params.ge_pg_hdrm_intbuf = (lossless) ? 32 : 0; /*(cells)c118*/ 8288 if (soc_feature(unit, soc_feature_mmu_reduced_internal_buffer)) { 8289 /*Saber*/ 8290 ka_mmu_params.ge_pg_hdrm_ema = (lossless) ? 32 : 0; /*(cells)c119*/ 8291 } else { 8292 ka_mmu_params.ge_pg_hdrm_ema = (lossless) ? 127 : 0; /*(cells)c119*/ 8293 } 8294 ka_mmu_params.ge_pg_hdrm_extbuf = (lossless) ? 116 : 0;/*(cells)c120*/ 8295 ka_mmu_params.ge_pg_hdrm_rewqe= (lossless) ? 114 : 0;/*(cells)c121*/ 8296 } else { 8297 ka_mmu_params.extbuf_used = 1; /*C16*/ 8298 ka_mmu_params.available_intbuf = 70;/*c39*/ 8299 ka_mmu_params.hg_pg_hdrm_intbuf = (lossless) ? 76 : 0;/*(cells)c108*/ 8300 ka_mmu_params.hg_pg_hdrm_ema = (lossless) ? 76 : 0;/*(cells)c109*/ 8301 ka_mmu_params.hg_pg_hdrm_extbuf = (lossless) ? 68 : 0;/*(cells)c110*/ 8302 ka_mmu_params.hg_pg_hdrm_rewqe = (lossless) ? 66 : 0;/*(pkts)c111*/ 8303 8304 ka_mmu_params.ge_pg_hdrm_intbuf = (lossless) ? 32 : 0;/*(cells)118*/ 8305 ka_mmu_params.ge_pg_hdrm_ema = (lossless) ? 32 : 0;/*(cells)c119*/ 8306 ka_mmu_params.ge_pg_hdrm_extbuf = (lossless) ? 25 : 0;/*(cells)120*/ 8307 ka_mmu_params.ge_pg_hdrm_rewqe= (lossless) ? 23 : 0;/*(pkts)120*/ 8308 } 8309 ka_mmu_params.available_emapool = 8310 (100 - ka_mmu_params.available_intbuf); /*c40, c41-SBv7*/ 8311 ka_mmu_params.cpu_pg_hdrm_intbuf = (lossless) ? 46 : 0; 8312 ka_mmu_params.cpu_pg_hdrm_ema = (lossless) ? 46 : 0; 8313 ka_mmu_params.cpu_pg_hdrm_extbuf = 0; 8314 ka_mmu_params.cpu_pg_hdrm_rewqe = (lossless) ? 40 : 0; 8315 ka_mmu_params.cpu_pg_hdrm_eqe = ka_mmu_params.cpu_pg_hdrm_rewqe * 8316 ka_mmu_params.num_replication_per_pkt; 8317 8318 ka_mmu_params.lb_pg_hdrm_intbuf = (lossless) ? 46 : 0; 8319 ka_mmu_params.lb_pg_hdrm_ema = (lossless) ? 46 : 0; 8320 ka_mmu_params.lb_pg_hdrm_extbuf = 0; 8321 ka_mmu_params.lb_pg_hdrm_rewqe = (lossless) ? 40 : 0; 8322 ka_mmu_params.lb_pg_hdrm_eqe = ka_mmu_params.lb_pg_hdrm_rewqe * 8323 ka_mmu_params.num_replication_per_pkt; 8324 8325 /*Intermediate Results calculation */ 8326 ethernet_mtu_cells_intbuf = 8327 ((KA_MMU_ETHERNET_MTU_BYTES + KA_MMU_PKT_HEADER_SIZE)/ 8328 KA_MMU_INT_BUF_CELL_SIZE) + 1; /*c71*/ 8329 8330 ethernet_mtu_cells_extbuf = 8331 ((KA_MMU_ETHERNET_MTU_BYTES + KA_MMU_PKT_HEADER_SIZE)/ 8332 KA_MMU_EXT_BUF_CELL_SIZE) + 1; /*c72*/ 8333 8334 num_ports = ka_mmu_params.num_ge_ports + 8335 ka_mmu_params.num_hg_ports + 8336 KA_MMU_NUM_LB_PORT + 8337 KA_MMU_NUM_CPU_PORT; /*c74 data ports+cpu+loopback*/ 8338 8339 num_data_ports = ka_mmu_params.num_ge_ports + 8340 ka_mmu_params.num_hg_ports; /*c75 data ports only */ 8341 8342 if (SOC_PBMP_MEMBER (PBMP_EXT_MEM (unit), CMIC_PORT(unit))) { 8343 total_queue_extbuf_bound += KA_MMU_NUM_CPU_PORT * 8344 KA_MMU_NUM_CPU_QUEUE; /*c81*/ 8345 } else { 8346 total_queue_intbuf_bound += KA_MMU_NUM_CPU_PORT * 8347 KA_MMU_NUM_CPU_QUEUE; /*c81*/ 8348 } 8349 8350 if (SOC_PBMP_MEMBER (PBMP_EXT_MEM (unit), LB_PORT(unit))) { 8351 total_queue_extbuf_bound += KA_MMU_NUM_LB_PORT * 8352 KA_MMU_NUM_LB_QUEUE;/*c82*/ 8353 } else { 8354 total_queue_intbuf_bound += KA_MMU_NUM_LB_PORT * 8355 KA_MMU_NUM_LB_QUEUE;/*c82*/ 8356 } 8357 8358 SOC_PBMP_CLEAR (temp_pbmp); 8359 SOC_PBMP_ASSIGN (temp_pbmp, si->ge.bitmap); 8360 SOC_PBMP_OR (temp_pbmp, si->fe.bitmap); 8361 SOC_PBMP_OR (temp_pbmp, si->xe.bitmap); 8362 SOC_PBMP_OR (temp_pbmp, si->hg.bitmap); 8363 8364 SOC_PBMP_ITER (temp_pbmp, port) { 8365 if (port < SOC_MAX_NUM_PORTS) { 8366 if (SOC_PBMP_MEMBER (PBMP_EXT_MEM (unit), port)) { 8367 total_queue_extbuf_bound += si->port_num_uc_cosq[port]; /*c84*/ 8368 if (IS_HG_PORT(unit, port) || IS_XE_PORT(unit, port)) { 8369 num_eqe_hgports_extbuf_bound += si->port_num_uc_cosq[port];/*c80*/ 8370 } else { 8371 num_eqe_geports_extbuf_bound += si->port_num_uc_cosq[port];/*c78*/ 8372 } 8373 } else { 8374 total_queue_intbuf_bound += si->port_num_uc_cosq[port]; /*c85*/ 8375 if (IS_HG_PORT(unit, port) || IS_XE_PORT(unit, port)) { 8376 num_eqe_hgports_intbuf_bound += si->port_num_uc_cosq[port];/*c79*/ 8377 } else { 8378 num_eqe_geports_intbuf_bound += si->port_num_uc_cosq[port];/*c77*/ 8379 } 8380 } 8381 } 8382 } 8383 8384 num_ema_queue = KA_MMU_EMA_QUEUES; /*c85*/ 8385 total_eqe_device = KA_MMU_NUM_EGRESS_QUEUE_IN_DEVICE; /*c87*/ 8386 8387 if (soc_feature(unit, soc_feature_mmu_reduced_internal_buffer)) { 8388 /* Saber */ 8389 max_intbuf_size = ((SB_MMU_INT_BUF_SIZE - 8390 KA_MMU_RESERVED_INT_BUF_SPACE_CFAP) * 1024) / 8391 KA_MMU_INT_BUF_CELL_SIZE; /*c88*/ 8392 intbuf_pool_size = ((ka_mmu_params.available_intbuf * 8393 max_intbuf_size) / 100) - 8394 SB_MMU_CFAP_THDIO_LATENCY; /*c90*/ 8395 emapool_size = ka_mmu_params.available_emapool ? 8396 (((ka_mmu_params.available_emapool * 8397 max_intbuf_size) / 100) - 8398 SB_MMU_CFAP_THDIO_LATENCY) : 0; /*c91*/ 8399 extbuf_size = ka_mmu_params.extbuf_used ? 8400 (1024 * 1024 * saber_mmu_ext_buf_size / 8401 KA_MMU_EXT_BUF_CELL_SIZE - 1 - 8402 KA_MMU_RESERVED_EXT_BUF_SPACE_CFAP - 8403 SB_MMU_CFAP_THDIO_LATENCY) : 0; /*c92*/ 8404 } else { 8405 /* Katana */ 8406 max_intbuf_size = ((KA_MMU_INT_BUF_SIZE - 8407 KA_MMU_RESERVED_INT_BUF_SPACE_CFAP)* 1024) / 8408 KA_MMU_INT_BUF_CELL_SIZE; /*c88*/ 8409 intbuf_pool_size = 8410 (ka_mmu_params.available_intbuf * max_intbuf_size) / 100; /*c90*/ 8411 emapool_size = ka_mmu_params.available_intbuf ? 8412 ((ka_mmu_params.available_emapool * max_intbuf_size) / 100) : 0; /*c91*/ 8413 extbuf_size = ka_mmu_params.extbuf_used ? 8414 (1024 * 1024 * KA_MMU_EXT_BUF_SIZE / 8415 KA_MMU_EXT_BUF_CELL_SIZE - 1 - 8416 KA_MMU_RESERVED_EXT_BUF_SPACE_CFAP) : 0; /*c92*/ 8417 } 8418 8419 rewqe_entries_admission = KA_MMU_RE_WORK_QUEUE_ENTRIES * 1024 - 8420 KA_MMU_RESERVED_RE_WORK_QUEUE_ENTRIES; /*c93 */ 8421 8422 /* Input Port threshold calculations */ 8423 ipthd_global_hdrm_intbuf = (20 * 1024) / 8424 KA_MMU_INT_BUF_CELL_SIZE + 1; /*c103*/ 8425 ipthd_global_hdrm_ema = (ka_mmu_params.extbuf_used) ? 8426 ipthd_global_hdrm_intbuf : 0; /*c104*/ 8427 ipthd_global_hdrm_extbuf = (ka_mmu_params.extbuf_used) ? 8428 (ipthd_global_hdrm_intbuf / 8429 KA_MMU_EXT_BUF_TO_INT_BUF_RATIO + 1) : 0;/*c105*/ 8430 ipthd_global_hdrm_rewqe = 0; /*c106*/ 8431 ipthd_global_hdrm_eqe = 0; /* c107 v7 */ 8432 8433 ipthd_hg_pg_hdrm_eqe = ka_mmu_params.num_replication_per_pkt * 8434 ka_mmu_params.hg_pg_hdrm_rewqe;/*c112*/ 8435 8436 ipthd_hg_total_hdrm_intbuf = KA_MMU_LOSSLESS_PG_NUM * 8437 ka_mmu_params.num_hg_ports * 8438 ka_mmu_params.hg_pg_hdrm_intbuf;/*c113*/ 8439 ipthd_hg_total_hdrm_ema = KA_MMU_LOSSLESS_PG_NUM * 8440 ka_mmu_params.num_hg_ports * 8441 ka_mmu_params.hg_pg_hdrm_ema;/*c114*/ 8442 ipthd_hg_total_hdrm_extbuf = KA_MMU_LOSSLESS_PG_NUM * 8443 ka_mmu_params.num_hg_ports * 8444 ka_mmu_params.hg_pg_hdrm_extbuf;/*c115*/ 8445 ipthd_hg_total_hdrm_rewqe = KA_MMU_LOSSLESS_PG_NUM * 8446 ka_mmu_params.num_hg_ports * 8447 ka_mmu_params.hg_pg_hdrm_rewqe;/*c116*/ 8448 ipthd_hg_total_hdrm_eqe = KA_MMU_LOSSLESS_PG_NUM * 8449 ka_mmu_params.num_hg_ports * 8450 ipthd_hg_pg_hdrm_eqe;/*c117*/ 8451 8452 ipthd_ge_pg_hdrm_eqe = ka_mmu_params.num_replication_per_pkt * 8453 ka_mmu_params.ge_pg_hdrm_rewqe;/*c122*/ 8454 8455 ipthd_ge_total_hdrm_intbuf = KA_MMU_LOSSLESS_PG_NUM * 8456 ka_mmu_params.num_ge_ports * 8457 ka_mmu_params.ge_pg_hdrm_intbuf;/*c123*/ 8458 ipthd_ge_total_hdrm_ema = KA_MMU_LOSSLESS_PG_NUM * 8459 ka_mmu_params.num_ge_ports * 8460 ka_mmu_params.ge_pg_hdrm_ema;/*c124*/ 8461 ipthd_ge_total_hdrm_extbuf = KA_MMU_LOSSLESS_PG_NUM * 8462 ka_mmu_params.num_ge_ports * 8463 ka_mmu_params.ge_pg_hdrm_extbuf;/*c125*/ 8464 ipthd_ge_total_hdrm_rewqe = KA_MMU_LOSSLESS_PG_NUM * 8465 ka_mmu_params.num_ge_ports * 8466 ka_mmu_params.ge_pg_hdrm_rewqe;/*c126*/ 8467 ipthd_ge_total_hdrm_eqe = KA_MMU_LOSSLESS_PG_NUM * 8468 ka_mmu_params.num_ge_ports * 8469 ipthd_ge_pg_hdrm_eqe;/*c127*/ 8470 8471 ipthd_total_hdrm_intbuf = ipthd_global_hdrm_intbuf + 8472 ipthd_hg_total_hdrm_intbuf + 8473 ipthd_ge_total_hdrm_intbuf + 8474 ka_mmu_params.cpu_pg_hdrm_intbuf + 8475 ka_mmu_params.lb_pg_hdrm_intbuf;/*c138*/ 8476 ipthd_total_hdrm_ema = ipthd_global_hdrm_ema + 8477 ipthd_hg_total_hdrm_ema + 8478 ipthd_ge_total_hdrm_ema + 8479 ka_mmu_params.cpu_pg_hdrm_ema + 8480 ka_mmu_params.lb_pg_hdrm_ema;/*c139*/ 8481 ipthd_total_hdrm_extbuf = ipthd_global_hdrm_extbuf + 8482 ipthd_hg_total_hdrm_extbuf + 8483 ipthd_ge_total_hdrm_extbuf + 8484 ka_mmu_params.cpu_pg_hdrm_extbuf + 8485 ka_mmu_params.lb_pg_hdrm_extbuf;/*c140*/ 8486 ipthd_total_hdrm_rewqe = ipthd_global_hdrm_rewqe+ 8487 ipthd_hg_total_hdrm_rewqe+ 8488 ipthd_ge_total_hdrm_rewqe + 8489 ka_mmu_params.cpu_pg_hdrm_rewqe + 8490 ka_mmu_params.lb_pg_hdrm_rewqe;/*c141*/ 8491 ipthd_total_hdrm_eqe = ipthd_global_hdrm_eqe + 8492 ipthd_hg_total_hdrm_eqe + 8493 ipthd_ge_total_hdrm_eqe + 8494 ka_mmu_params.cpu_pg_hdrm_eqe + 8495 ka_mmu_params.lb_pg_hdrm_eqe;/*c142*/ 8496 8497 ipthd_per_pg_min_intbuf_ingpool = (all_ext_mem_port && lossless) ? 8498 ethernet_mtu_cells_intbuf : 8499 KA_MMU_JUMBO_FRAME_INT_BUF; /*c144*/ 8500 8501 ipthd_per_pg_min_intbuf_ingpool_pg_0_6 = 1; /*c145*/ 8502 8503 ipthd_per_pg_min_intbuf_emapool = ka_mmu_params.extbuf_used ? 8504 KA_MMU_JUMBO_FRAME_INT_BUF : 0;/*c146*/ 8505 ipthd_per_pg_min_extbuf = ka_mmu_params.extbuf_used ? 8506 ((KA_MMU_JUMBO_FRAME_INT_BUF / 8507 KA_MMU_EXT_BUF_TO_INT_BUF_RATIO) + 1) : 0;/*c147*/ 8508 8509 ipthd_per_pg_min_rewqe = KA_MMU_JUMBO_FRAME_INT_BUF / 8510 KA_MMU_CELL_PER_AVG_PKT_INT_BUF;/*c148*/ 8511 8512 if (soc_feature(unit, soc_feature_mmu_reduced_internal_buffer) && 8513 (ka_mmu_params.extbuf_used)) { 8514 ipthd_per_pg_min_intbuf_ingpool = ethernet_mtu_cells_intbuf;/*c144*/ 8515 ipthd_per_pg_min_intbuf_emapool = ipthd_per_pg_min_intbuf_ingpool; 8516 if (!all_ext_mem_port) { 8517 ipthd_per_pg_min_extbuf = (ipthd_per_pg_min_intbuf_ingpool / 8518 KA_MMU_EXT_BUF_TO_INT_BUF_RATIO) + 1; 8519 ipthd_per_pg_min_rewqe = ipthd_per_pg_min_intbuf_ingpool; 8520 } 8521 } 8522 8523 ipthd_per_pg_min_eqe = ipthd_per_pg_min_rewqe * 8524 ka_mmu_params.num_replication_per_pkt;/*c149*/ 8525 8526 ipthd_total_pg_min_intbuf_ingpool = KA_MMU_LOSSLESS_PG_NUM * num_ports * 8527 ipthd_per_pg_min_intbuf_ingpool + 8528 ipthd_per_pg_min_intbuf_ingpool_pg_0_6 * 8529 ka_mmu_params.num_hg_ports * 7;/*c151*/ 8530 ipthd_total_pg_min_intbuf_emapool = KA_MMU_LOSSLESS_PG_NUM * num_ports * 8531 ipthd_per_pg_min_intbuf_emapool;/*c152*/ 8532 ipthd_total_pg_min_extbuf = KA_MMU_LOSSLESS_PG_NUM * num_ports * 8533 ipthd_per_pg_min_extbuf;/*c153*/ 8534 ipthd_total_pg_min_rewqe = KA_MMU_LOSSLESS_PG_NUM * num_ports * 8535 ipthd_per_pg_min_rewqe;/*c154*/ 8536 ipthd_total_pg_min_eqe = KA_MMU_LOSSLESS_PG_NUM * num_ports * 8537 ipthd_per_pg_min_eqe;/*c155*/ 8538 8539 ipthd_per_port_min_intbuf_ingpool = 0;/*c157*/ 8540 ipthd_per_port_min_intbuf_emapool = 0;/*c158*/ 8541 ipthd_per_port_min_extbuf = 0;/*c159*/ 8542 ipthd_per_port_min_rewqe = 0;/*c160*/ 8543 ipthd_per_port_min_eqe = 0;/*c161*/ 8544 8545 ipthd_total_port_min_intbuf_ingpool = 8546 num_ports * ipthd_per_port_min_intbuf_ingpool;/*163*/ 8547 ipthd_total_port_min_intbuf_emapool = 8548 num_ports * ipthd_per_port_min_intbuf_emapool;/*164*/ 8549 ipthd_total_port_min_extbuf = num_ports * ipthd_per_port_min_extbuf;/*165*/ 8550 ipthd_total_port_min_rewqe = num_ports * ipthd_per_port_min_rewqe;/*166*/ 8551 ipthd_total_port_min_eqe = num_ports * ipthd_per_port_min_eqe;/*167*/ 8552 8553 ipthd_total_min_intbuf_ingpool = ipthd_total_pg_min_intbuf_ingpool + 8554 ipthd_total_port_min_intbuf_ingpool;/*c169*/ 8555 ipthd_total_min_intbuf_emapool = ipthd_total_pg_min_intbuf_emapool+ 8556 ipthd_total_port_min_intbuf_emapool;/*c170*/ 8557 ipthd_total_min_extbuf = ipthd_total_pg_min_extbuf + 8558 ipthd_total_port_min_extbuf;/*c171*/ 8559 ipthd_total_min_rewqe = ipthd_total_pg_min_rewqe+ 8560 ipthd_total_port_min_rewqe;/*c172*/ 8561 ipthd_total_min_eqe = ipthd_total_pg_min_eqe + ipthd_total_port_min_eqe;/*173*/ 8562 8563 /* Output port thresholds calculations*/ 8564 opthd_port_min_grntee_queue_intbuf = lossless ? 8565 0 : ethernet_mtu_cells_intbuf;/*c193*/ 8566 8567 opthd_port_min_grntee_queue_extbuf = lossless ? 0 : 8568 (ka_mmu_params.extbuf_used ? ethernet_mtu_cells_extbuf : 0);/*c194*/ 8569 8570 opthd_port_min_grntee_eqe = lossless ? 0 : 8571 ethernet_mtu_cells_intbuf / 8572 KA_MMU_CELL_PER_AVG_PKT_EXT_BUF;/*c195*/ 8573 8574 opthd_port_min_grntee_ema_queue = lossless ? 0 : 8575 (ka_mmu_params.extbuf_used ? ethernet_mtu_cells_intbuf : 0);/*c196*/ 8576 8577 opthd_port_min_grntee_rewqe = opthd_port_min_grntee_queue_intbuf;/*197*/ 8578 opthd_port_min_grntee_rewqe_intbuf_mc = lossless ? 0: 150;/*198*/ 8579 opthd_port_min_grntee_rewqe_intbuf_tocpu= lossless ? 0: 50;/*199*/ 8580 opthd_port_min_grntee_rewqe_intbuf_mirror= lossless ? 0: 50;/*200*/ 8581 opthd_port_min_grntee_rewqe_extbuf = lossless ? 0 : 8582 (ka_mmu_params.extbuf_used ? 8583 num_ports * KA_MMU_JUMBO_FRAME_EXT_BUF : 0);/*201*/ 8584 8585 opthd_total_min_grntee_queue_intbuff = total_queue_intbuf_bound * 8586 opthd_port_min_grntee_queue_intbuf; /*204*/ 8587 opthd_total_min_grntee_queue_extbuff = total_eqe_device * 8588 opthd_port_min_grntee_queue_extbuf;/*205*/ 8589 opthd_total_min_grntee_eqe = total_eqe_device * 8590 opthd_port_min_grntee_eqe; /*206*/ 8591 opthd_total_min_grntee_ema_queue = KA_MMU_EMA_QUEUES * 8592 opthd_port_min_grntee_ema_queue;/*207*/ 8593 opthd_total_min_grntee_rewqe = KA_MMU_RE_WORK_QUEUES_IN_DEVICE * 8594 opthd_port_min_grntee_rewqe;/*208*/ 8595 opthd_total_min_grntee_rewqe_intbuf = 8596 opthd_port_min_grntee_rewqe_intbuf_mc + 8597 opthd_port_min_grntee_rewqe_intbuf_tocpu+ 8598 opthd_port_min_grntee_rewqe_intbuf_mirror;/*209*/ 8599 opthd_total_min_grntee_rewqe_extbuf = 8600 KA_MMU_RE_WORK_QUEUES_IN_DEVICE * 8601 opthd_port_min_grntee_rewqe_extbuf;/*210*/ 8602 8603 /* Input threshold total shared calculations*/ 8604 ipthd_total_shared_intbuf_ingpool = intbuf_pool_size - 8605 ipthd_total_hdrm_intbuf - 8606 ipthd_total_min_intbuf_ingpool - 8607 (lossless ? 8608 opthd_total_min_grntee_queue_intbuff : 8609 0);/*c175*/ 8610 ipthd_total_shared_intbuf_emapool = ka_mmu_params.extbuf_used ? 8611 (emapool_size - ipthd_total_hdrm_ema - 8612 ipthd_total_min_intbuf_emapool - 8613 (lossless ? 8614 opthd_total_min_grntee_ema_queue : 8615 0)) : 0;/*c176*/ 8616 ipthd_total_shared_extbuf = extbuf_size - 8617 ipthd_total_min_extbuf - 8618 ipthd_total_hdrm_extbuf - 8619 (lossless ? 8620 opthd_total_min_grntee_queue_extbuff : 0);/*177*/ 8621 ipthd_total_shared_rewqe = rewqe_entries_admission - 8622 ipthd_total_hdrm_rewqe - 8623 ipthd_total_min_rewqe - 8624 (lossless ? opthd_total_min_grntee_rewqe : 0);/*178*/ 8625 ipthd_total_shared_eqe = mmu_egress_queue_entries * 1024 - 8626 ipthd_total_hdrm_eqe - 8627 ipthd_total_min_eqe - 8628 (lossless ? opthd_total_min_grntee_eqe : 0);/*179*/ 8629 8630 /* Output port thresholds calculations .. continued*/ 8631 opthd_total_shared_queue_intbuff = intbuf_pool_size - 8632 opthd_total_min_grntee_queue_intbuff - 8633 opthd_total_min_grntee_rewqe_intbuf;/*c213*/ 8634 opthd_total_shared_queue_extbuff = extbuf_size - 8635 opthd_total_min_grntee_queue_extbuff - 8636 opthd_total_min_grntee_rewqe_extbuf;/*c214*/ 8637 opthd_total_shared_queue_eqe = mmu_egress_queue_entries * 8638 1024 - opthd_total_min_grntee_eqe;/*c215*/ 8639 opthd_total_shared_queue_ema_queue = emapool_size - 8640 opthd_total_min_grntee_ema_queue;/*c216*/ 8641 opthd_total_shared_queue_rewqe = rewqe_entries_admission - 8642 opthd_total_min_grntee_rewqe;/*c217*/ 8643 opthd_total_shared_queue_rewqe_intbuf = intbuf_pool_size - 8644 opthd_total_min_grntee_queue_intbuff - 8645 opthd_total_min_grntee_rewqe_intbuf;/*c218*/ 8646 opthd_total_shared_queue_rewqe_extbuf = extbuf_size - 8647 opthd_total_min_grntee_queue_extbuff - 8648 opthd_total_min_grntee_rewqe_extbuf;/*c219*/ 8649 8650 if (bsl_check(bslLayerSoc, bslSourceCommon, bslSeverityVerbose, unit)) { 8651 LOG_CLI((BSL_META_U(unit, 8652 "\npbmp all count =%d pbmp ext mem count =%d"), 8653 valid_port_count, ext_mem_port_count)); 8654 LOG_CLI((BSL_META_U(unit, 8655 "\n Katana MMU config:= %s : %s"), 8656 ((all_int_mem_port) ? "all internal mem" : 8657 ((all_ext_mem_port) ? "all external mem" : 8658 "both internal and external mem")), 8659 ((lossless) ? "lossless" : "lossy"))); 8660 LOG_CLI((BSL_META_U(unit, 8661 "\nnum_ge_ports %d"), 8662 ka_mmu_params.num_ge_ports)); 8663 LOG_CLI((BSL_META_U(unit, 8664 "\nnum_hg_ports %d"), 8665 ka_mmu_params.num_hg_ports)); 8666 LOG_CLI((BSL_META_U(unit, 8667 "\navailable_intbuf %d"), 8668 ka_mmu_params.available_intbuf)); 8669 8670 LOG_CLI((BSL_META_U(unit, 8671 "\nmax_pkt_size %d"), 8672 KA_MMU_MAX_PKT_SIZE_IN_CELLS)); 8673 LOG_CLI((BSL_META_U(unit, 8674 "\njumbo_frame_intbuf %d"), 8675 KA_MMU_JUMBO_FRAME_INT_BUF)); 8676 LOG_CLI((BSL_META_U(unit, 8677 "\njumbo_frame_extbuf %d"), 8678 KA_MMU_JUMBO_FRAME_EXT_BUF)); 8679 LOG_CLI((BSL_META_U(unit, 8680 "\nethernet_mtu_cells_intbuf %d"), 8681 ethernet_mtu_cells_intbuf)); 8682 LOG_CLI((BSL_META_U(unit, 8683 "\nethernet_mtu_cells_extbuf %d"), 8684 ethernet_mtu_cells_extbuf)); 8685 LOG_CLI((BSL_META_U(unit, 8686 "\nnum_ports %d"), num_ports)); 8687 LOG_CLI((BSL_META_U(unit, 8688 "\nnum_data_ports %d"), num_data_ports)); 8689 LOG_CLI((BSL_META_U(unit, 8690 "\nnum_eqe_geports_intbuf_bound %d"), 8691 num_eqe_geports_intbuf_bound)); 8692 LOG_CLI((BSL_META_U(unit, 8693 "\nnum_eqe_geports_extbuf_bound %d"), 8694 num_eqe_geports_extbuf_bound)); 8695 LOG_CLI((BSL_META_U(unit, 8696 "\nnum_eqe_hgports_intbuf_bound %d"), 8697 num_eqe_hgports_intbuf_bound)); 8698 LOG_CLI((BSL_META_U(unit, 8699 "\nnum_eqe_hgports_extbuf_bound %d"), 8700 num_eqe_hgports_extbuf_bound)); 8701 8702 LOG_CLI((BSL_META_U(unit, 8703 "\nnum_cpu_queue %d"), 8704 KA_MMU_NUM_CPU_PORT * KA_MMU_NUM_CPU_QUEUE)); 8705 LOG_CLI((BSL_META_U(unit, 8706 "\ntotal_queue_intbuf_bound %d"), 8707 total_queue_intbuf_bound)); 8708 LOG_CLI((BSL_META_U(unit, 8709 "\ntotal_queue_extbuf_bound %d"), 8710 total_queue_extbuf_bound)); 8711 LOG_CLI((BSL_META_U(unit, 8712 "\nnum_ema_queue %d"), num_ema_queue)); 8713 LOG_CLI((BSL_META_U(unit, 8714 "\ntotal_eqe_device %d"), 8715 total_eqe_device)); 8716 LOG_CLI((BSL_META_U(unit, 8717 "\nmax_intbuf_size %d"), 8718 max_intbuf_size)); 8719 8720 LOG_CLI((BSL_META_U(unit, 8721 "\nintbuf_pool_size %d"), 8722 intbuf_pool_size)); 8723 LOG_CLI((BSL_META_U(unit, 8724 "\nemapool_size %d"), emapool_size)); 8725 LOG_CLI((BSL_META_U(unit, 8726 "\nextbuf_size %d"), extbuf_size)); 8727 8728 LOG_CLI((BSL_META_U(unit, 8729 "\nglobal_hdrm_intbuf %d"), 8730 ipthd_global_hdrm_intbuf)); 8731 LOG_CLI((BSL_META_U(unit, 8732 "\nglobal_hdrm_extbuf %d"), 8733 ipthd_global_hdrm_extbuf)); 8734 LOG_CLI((BSL_META_U(unit, 8735 "\nglobal_hdrm_rewqe %d"), 8736 ipthd_global_hdrm_rewqe)); 8737 LOG_CLI((BSL_META_U(unit, 8738 "\nglobal_hdrm_eqe %d"), 8739 ipthd_global_hdrm_eqe)); 8740 LOG_CLI((BSL_META_U(unit, 8741 "\nhg_pg_hdrm_intbuf %d"), 8742 ka_mmu_params.hg_pg_hdrm_intbuf)); 8743 LOG_CLI((BSL_META_U(unit, 8744 "\nhg_pg_hdrm_extbuf %d"), 8745 ka_mmu_params.hg_pg_hdrm_extbuf)); 8746 LOG_CLI((BSL_META_U(unit, 8747 "\nhg_pg_hdrm_rewqe %d"), 8748 ka_mmu_params.hg_pg_hdrm_rewqe)); 8749 LOG_CLI((BSL_META_U(unit, 8750 "\nhg_pg_hdrm_eqe %d"), 8751 ipthd_hg_pg_hdrm_eqe)); 8752 LOG_CLI((BSL_META_U(unit, 8753 "\nhg_ipthd_total_hdrm_intbuf %d"), 8754 ipthd_hg_total_hdrm_intbuf)); 8755 LOG_CLI((BSL_META_U(unit, 8756 "\nhg_ipthd_total_hdrm_extbuf %d"), 8757 ipthd_hg_total_hdrm_extbuf)); 8758 LOG_CLI((BSL_META_U(unit, 8759 "\nhg_ipthd_total_hdrm_rewqe %d"), 8760 ipthd_hg_total_hdrm_rewqe)); 8761 LOG_CLI((BSL_META_U(unit, 8762 "\nhg_ipthd_total_hdrm_eqe %d"), 8763 ipthd_hg_total_hdrm_eqe)); 8764 LOG_CLI((BSL_META_U(unit, 8765 "\nge_pg_hdrm_intbuf %d"), 8766 ka_mmu_params.ge_pg_hdrm_intbuf)); 8767 LOG_CLI((BSL_META_U(unit, 8768 "\nge_pg_hdrm_extbuf %d"), 8769 ka_mmu_params.ge_pg_hdrm_extbuf)); 8770 LOG_CLI((BSL_META_U(unit, 8771 "\nge_pg_hdrm_rewqe %d"), 8772 ka_mmu_params.ge_pg_hdrm_rewqe)); 8773 LOG_CLI((BSL_META_U(unit, 8774 "\nipthd_ge_pg_hdrm_eqe %d"), 8775 ipthd_ge_pg_hdrm_eqe)); 8776 LOG_CLI((BSL_META_U(unit, 8777 "\nipthd_ge_total_hdrm_intbuf %d"), 8778 ipthd_ge_total_hdrm_intbuf)); 8779 LOG_CLI((BSL_META_U(unit, 8780 "\nipthd_ge_total_hdrm_extbuf %d"), 8781 ipthd_ge_total_hdrm_extbuf)); 8782 LOG_CLI((BSL_META_U(unit, 8783 "\nipthd_ge_total_hdrm_rewqe %d"), 8784 ipthd_ge_total_hdrm_rewqe)); 8785 LOG_CLI((BSL_META_U(unit, 8786 "\nipthd_ge_total_hdrm_eqe %d"), 8787 ipthd_ge_total_hdrm_eqe)); 8788 LOG_CLI((BSL_META_U(unit, 8789 "\nipthd_total_hdrm_intbuf %d"), 8790 ipthd_total_hdrm_intbuf)); 8791 LOG_CLI((BSL_META_U(unit, 8792 "\nipthd_total_hdrm_ema %d"), 8793 ipthd_total_hdrm_ema)); 8794 LOG_CLI((BSL_META_U(unit, 8795 "\nipthd_total_hdrm_extbuf %d"), 8796 ipthd_total_hdrm_extbuf)); 8797 LOG_CLI((BSL_META_U(unit, 8798 "\nipthd_total_hdrm_rewqe %d"), 8799 ipthd_total_hdrm_rewqe)); 8800 LOG_CLI((BSL_META_U(unit, 8801 "\nipthd_total_hdrm_eqe %d"), 8802 ipthd_total_hdrm_eqe)); 8803 8804 LOG_CLI((BSL_META_U(unit, 8805 "\nipthd_per_pg_min_intbuf_ingpool %d"), 8806 ipthd_per_pg_min_intbuf_ingpool)); 8807 LOG_CLI((BSL_META_U(unit, 8808 "\nipthd_per_pg_min_intbuf_emapool %d"), 8809 ipthd_per_pg_min_intbuf_emapool)); 8810 LOG_CLI((BSL_META_U(unit, 8811 "\nipthd_per_pg_min_extbuf %d"), 8812 ipthd_per_pg_min_extbuf)); 8813 LOG_CLI((BSL_META_U(unit, 8814 "\nipthd_per_pg_min_rewqe %d"), 8815 ipthd_per_pg_min_rewqe)); 8816 LOG_CLI((BSL_META_U(unit, 8817 "\nipthd_per_pg_min_eqe %d"), 8818 ipthd_per_pg_min_eqe)); 8819 8820 LOG_CLI((BSL_META_U(unit, 8821 "\nipthd_total_pg_min_intbuf_ingpool %d"), 8822 ipthd_total_pg_min_intbuf_ingpool)); 8823 LOG_CLI((BSL_META_U(unit, 8824 "\nipthd_total_pg_min_intbuf_emapool %d"), 8825 ipthd_total_pg_min_intbuf_emapool)); 8826 LOG_CLI((BSL_META_U(unit, 8827 "\nipthd_total_pg_min_extbuf %d"), 8828 ipthd_total_pg_min_extbuf)); 8829 LOG_CLI((BSL_META_U(unit, 8830 "\nipthd_total_pg_min_rewqe %d"), 8831 ipthd_total_pg_min_rewqe)); 8832 LOG_CLI((BSL_META_U(unit, 8833 "\nipthd_total_pg_min_eqe %d"), 8834 ipthd_total_pg_min_eqe)); 8835 8836 LOG_CLI((BSL_META_U(unit, 8837 "\nipthd_per_port_min_intbuf_ingpool %d"), 8838 ipthd_per_port_min_intbuf_ingpool)); 8839 LOG_CLI((BSL_META_U(unit, 8840 "\nipthd_per_port_min_intbuf_emapool %d"), 8841 ipthd_per_port_min_intbuf_emapool)); 8842 LOG_CLI((BSL_META_U(unit, 8843 "\nipthd_per_port_min_extbuf %d"), 8844 ipthd_per_port_min_extbuf)); 8845 LOG_CLI((BSL_META_U(unit, 8846 "\nipthd_per_port_min_rewqe %d"), 8847 ipthd_per_port_min_rewqe)); 8848 LOG_CLI((BSL_META_U(unit, 8849 "\nipthd_per_port_min_eqe %d"), 8850 ipthd_per_port_min_eqe)); 8851 8852 LOG_CLI((BSL_META_U(unit, 8853 "\nipthd_total_port_min_intbuf_ingpool %d"), 8854 ipthd_total_port_min_intbuf_ingpool)); 8855 LOG_CLI((BSL_META_U(unit, 8856 "\nipthd_total_port_min_intbuf_emapool %d"), 8857 ipthd_total_port_min_intbuf_emapool)); 8858 LOG_CLI((BSL_META_U(unit, 8859 "\nipthd_total_port_min_extbuf %d"), 8860 ipthd_total_port_min_extbuf)); 8861 LOG_CLI((BSL_META_U(unit, 8862 "\nipthd_total_port_min_rewqe %d"), 8863 ipthd_total_port_min_rewqe)); 8864 LOG_CLI((BSL_META_U(unit, 8865 "\nipthd_total_port_min_eqe %d"), 8866 ipthd_total_port_min_eqe)); 8867 8868 LOG_CLI((BSL_META_U(unit, 8869 "\nipthd_total_min_intbuf_ingpool %d"), 8870 ipthd_total_min_intbuf_ingpool)); 8871 LOG_CLI((BSL_META_U(unit, 8872 "\nipthd_total_min_intbuf_emapool %d"), 8873 ipthd_total_min_intbuf_emapool)); 8874 LOG_CLI((BSL_META_U(unit, 8875 "\nipthd_total_min_extbuf %d"), 8876 ipthd_total_min_extbuf)); 8877 LOG_CLI((BSL_META_U(unit, 8878 "\nipthd_total_min_rewqe %d"), 8879 ipthd_total_min_rewqe)); 8880 LOG_CLI((BSL_META_U(unit, 8881 "\nipthd_total_min_eqe %d"), 8882 ipthd_total_min_eqe)); 8883 8884 LOG_CLI((BSL_META_U(unit, 8885 "\nipthd_total_shared_intbuf_ingpool %d"), 8886 ipthd_total_shared_intbuf_ingpool)); 8887 LOG_CLI((BSL_META_U(unit, 8888 "\nipthd_total_shared_intbuf_emapool %d"), 8889 ipthd_total_shared_intbuf_emapool)); 8890 LOG_CLI((BSL_META_U(unit, 8891 "\nipthd_total_shared_extbuf %d"), 8892 ipthd_total_shared_extbuf)); 8893 LOG_CLI((BSL_META_U(unit, 8894 "\nipthd_total_shared_rewqe %d"), 8895 ipthd_total_shared_rewqe)); 8896 LOG_CLI((BSL_META_U(unit, 8897 "\nipthd_total_shared_eqe %d"), 8898 ipthd_total_shared_eqe)); 8899 8900 LOG_CLI((BSL_META_U(unit, 8901 "\nopthd_port_min_grntee_queue_intbuf %d"), 8902 opthd_port_min_grntee_queue_intbuf)); 8903 LOG_CLI((BSL_META_U(unit, 8904 "\nopthd_port_min_grntee_queue_extbuf %d"), 8905 opthd_port_min_grntee_queue_extbuf)); 8906 LOG_CLI((BSL_META_U(unit, 8907 "\nopthd_port_min_grntee_eqe %d"), 8908 opthd_port_min_grntee_eqe)); 8909 LOG_CLI((BSL_META_U(unit, 8910 "\nopthd_port_min_grntee_ema_queue %d"), 8911 opthd_port_min_grntee_ema_queue)); 8912 LOG_CLI((BSL_META_U(unit, 8913 "\nopthd_port_min_grntee_rewqe %d"), 8914 opthd_port_min_grntee_rewqe)); 8915 LOG_CLI((BSL_META_U(unit, 8916 "\nopthd_port_min_grntee_rewqe_intbuf_mc %d"), 8917 opthd_port_min_grntee_rewqe_intbuf_mc)); 8918 LOG_CLI((BSL_META_U(unit, 8919 "\nopthd_port_min_grntee_rewqe_intbuf_topcu %d"), 8920 opthd_port_min_grntee_rewqe_intbuf_tocpu)); 8921 LOG_CLI((BSL_META_U(unit, 8922 "\nopthd_port_min_grntee_rewqe_intbuf_mirror %d"), 8923 opthd_port_min_grntee_rewqe_intbuf_mirror)); 8924 LOG_CLI((BSL_META_U(unit, 8925 "\nopthd_port_min_grntee_rewqe_extbuf %d"), 8926 opthd_port_min_grntee_rewqe_extbuf)); 8927 8928 LOG_CLI((BSL_META_U(unit, 8929 "\nopthd_total_min_grntee_queue_intbuff %d"), 8930 opthd_total_min_grntee_queue_intbuff)); 8931 LOG_CLI((BSL_META_U(unit, 8932 "\nopthd_total_min_grntee_queue_extbuff %d"), 8933 opthd_total_min_grntee_queue_extbuff)); 8934 LOG_CLI((BSL_META_U(unit, 8935 "\nopthd_total_min_grntee_eqe %d"), 8936 opthd_total_min_grntee_eqe)); 8937 LOG_CLI((BSL_META_U(unit, 8938 "\nopthd_total_min_grntee_ema_queue %d"), 8939 opthd_total_min_grntee_ema_queue)); 8940 LOG_CLI((BSL_META_U(unit, 8941 "\nopthd_total_min_grntee_rewqe %d"), 8942 opthd_total_min_grntee_rewqe)); 8943 LOG_CLI((BSL_META_U(unit, 8944 "\nopthd_total_min_grntee_rewqe_intbuf %d"), 8945 opthd_total_min_grntee_rewqe_intbuf)); 8946 LOG_CLI((BSL_META_U(unit, 8947 "\nopthd_total_min_grntee_rewqe_extbuf %d"), 8948 opthd_total_min_grntee_rewqe_extbuf)); 8949 8950 LOG_CLI((BSL_META_U(unit, 8951 "\nopthd_total_shared_queue_intbuff %d"), 8952 opthd_total_shared_queue_intbuff)); 8953 LOG_CLI((BSL_META_U(unit, 8954 "\nopthd_total_shared_queue_extbuff %d"), 8955 opthd_total_shared_queue_extbuff)); 8956 LOG_CLI((BSL_META_U(unit, 8957 "\nopthd_total_shared_queue_eqe %d"), 8958 opthd_total_shared_queue_eqe)); 8959 LOG_CLI((BSL_META_U(unit, 8960 "\nopthd_total_shared_queue_ema_queue %d"), 8961 opthd_total_shared_queue_ema_queue)); 8962 LOG_CLI((BSL_META_U(unit, 8963 "\nopthd_total_shared_queue_rewqe %d"), 8964 opthd_total_shared_queue_rewqe)); 8965 LOG_CLI((BSL_META_U(unit, 8966 "\nopthd_total_shared_queue_rewqe_intbuf %d"), 8967 opthd_total_shared_queue_rewqe_intbuf)); 8968 LOG_CLI((BSL_META_U(unit, 8969 "\nopthd_total_shared_queue_rewqe_extbuf %d\n"), 8970 opthd_total_shared_queue_rewqe_extbuf)); 8971 } 8972 8973 /* Input port thresholds register/table setting*/ 8974 rval = 0; 8975 soc_reg_field_set(unit, COLOR_AWAREr, &rval, ENABLEf, 0); 8976 SOC_IF_ERROR_RETURN(WRITE_COLOR_AWAREr (unit, rval)); 8977 8978 /* Internal Buffer Ingress Pool */ 8979 rval = 0; 8980 soc_reg_field_set(unit, GLOBAL_HDRM_LIMITr, &rval, GLOBAL_HDRM_LIMITf, 8981 ipthd_global_hdrm_intbuf); 8982 SOC_IF_ERROR_RETURN(WRITE_GLOBAL_HDRM_LIMITr (unit, rval)); 8983 rval = 0; 8984 soc_reg_field_set(unit, BUFFER_CELL_LIMIT_SPr, &rval, LIMITf, 8985 ipthd_total_shared_intbuf_ingpool); 8986 SOC_IF_ERROR_RETURN(WRITE_BUFFER_CELL_LIMIT_SPr (unit, 0, rval)); 8987 rval = 0; 8988 soc_reg_field_set(unit, CELL_RESET_LIMIT_OFFSET_SPr, &rval, 8989 OFFSETf, (num_ports / 4 * ethernet_mtu_cells_intbuf)); 8990 SOC_IF_ERROR_RETURN(WRITE_CELL_RESET_LIMIT_OFFSET_SPr (unit, 0, rval)); 8991 8992 if (!all_int_mem_port) { /* not applicable for all internal mem port */ 8993 /* External Buffer */ 8994 rval = 0; 8995 soc_reg_field_set(unit, THDIEXT_GLOBAL_HDRM_LIMITr, &rval, 8996 GLOBAL_HDRM_LIMITf, ipthd_global_hdrm_extbuf); 8997 SOC_IF_ERROR_RETURN(WRITE_THDIEXT_GLOBAL_HDRM_LIMITr (unit, rval)); 8998 rval = 0; 8999 soc_reg_field_set(unit, THDIEXT_BUFFER_CELL_LIMIT_SPr, &rval, LIMITf, 9000 ipthd_total_shared_extbuf ); 9001 SOC_IF_ERROR_RETURN(WRITE_THDIEXT_BUFFER_CELL_LIMIT_SPr (unit, 0,rval)); 9002 rval = 0; 9003 soc_reg_field_set(unit, THDIEXT_CELL_RESET_LIMIT_OFFSET_SPr, &rval, 9004 OFFSETf, (num_ports /4 * ethernet_mtu_cells_extbuf)); 9005 SOC_IF_ERROR_RETURN( 9006 WRITE_THDIEXT_CELL_RESET_LIMIT_OFFSET_SPr (unit, 0, rval)); 9007 9008 /* EMA pool */ 9009 rval = 0; 9010 soc_reg_field_set(unit, THDIEMA_GLOBAL_HDRM_LIMITr, &rval, 9011 GLOBAL_HDRM_LIMITf, ipthd_global_hdrm_ema);/*c253*/ 9012 SOC_IF_ERROR_RETURN(WRITE_THDIEMA_GLOBAL_HDRM_LIMITr (unit, rval)); 9013 rval = 0; 9014 soc_reg_field_set(unit, THDIEMA_BUFFER_CELL_LIMIT_SPr, &rval, LIMITf, 9015 ipthd_total_shared_intbuf_emapool);/*c254*/ 9016 SOC_IF_ERROR_RETURN(WRITE_THDIEMA_BUFFER_CELL_LIMIT_SPr (unit, 0,rval)); 9017 rval = 0; 9018 soc_reg_field_set(unit, THDIEMA_CELL_RESET_LIMIT_OFFSET_SPr, &rval, 9019 OFFSETf, (num_ports /4 * ethernet_mtu_cells_intbuf));/*c255*/ 9020 SOC_IF_ERROR_RETURN( 9021 WRITE_THDIEMA_CELL_RESET_LIMIT_OFFSET_SPr (unit, 0, rval)); 9022 } 9023 9024 /* RE WQEs */ 9025 rval = 0; 9026 soc_reg_field_set(unit, THDIRQE_GLOBAL_HDRM_LIMITr, &rval, 9027 GLOBAL_HDRM_LIMITf, ipthd_global_hdrm_rewqe);/*c257*/ 9028 SOC_IF_ERROR_RETURN(WRITE_THDIRQE_GLOBAL_HDRM_LIMITr (unit, rval)); 9029 rval = 0; 9030 soc_reg_field_set(unit, THDIRQE_BUFFER_CELL_LIMIT_SPr, &rval, LIMITf, 9031 ipthd_total_shared_rewqe);/*c258*/ 9032 SOC_IF_ERROR_RETURN(WRITE_THDIRQE_BUFFER_CELL_LIMIT_SPr (unit, 0, rval)); 9033 rval = 0; 9034 soc_reg_field_set(unit, THDIRQE_CELL_RESET_LIMIT_OFFSET_SPr, &rval, 9035 OFFSETf, (num_ports / 4));/*c259*/ 9036 SOC_IF_ERROR_RETURN(WRITE_THDIRQE_CELL_RESET_LIMIT_OFFSET_SPr(unit,0,rval)); 9037 9038 /* EQEs */ 9039 rval = 0; 9040 soc_reg_field_set(unit, THDIQEN_GLOBAL_HDRM_LIMITr, &rval, 9041 GLOBAL_HDRM_LIMITf, ipthd_global_hdrm_eqe);/*c261*/ 9042 SOC_IF_ERROR_RETURN(WRITE_THDIQEN_GLOBAL_HDRM_LIMITr (unit, rval)); 9043 rval = 0; 9044 soc_reg_field_set(unit, THDIQEN_BUFFER_CELL_LIMIT_SPr, &rval, LIMITf, 9045 ipthd_total_shared_eqe);/*c262*/ 9046 SOC_IF_ERROR_RETURN(WRITE_THDIQEN_BUFFER_CELL_LIMIT_SPr (unit, 0, rval)); 9047 rval = 0; 9048 soc_reg_field_set(unit, THDIQEN_CELL_RESET_LIMIT_OFFSET_SPr, &rval, 9049 OFFSETf, (num_ports / 4 * ka_mmu_params.num_replication_per_pkt));/*263*/ 9050 SOC_IF_ERROR_RETURN(WRITE_THDIQEN_CELL_RESET_LIMIT_OFFSET_SPr(unit,0,rval)); 9051 9052 /* Ouput port thresholds setting*/ 9053 9054 /* Internal buffer Egress pool */ 9055 rval = 0; 9056 soc_reg_field_set(unit, OP_BUFFER_SHARED_LIMIT_CELLIr, &rval, 9057 OP_BUFFER_SHARED_LIMIT_CELLIf, opthd_total_shared_queue_intbuff); 9058 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_SHARED_LIMIT_CELLIr (unit, rval));/*c268*/ 9059 rval = 0; 9060 soc_reg_field_set(unit, OP_BUFFER_LIMIT_YELLOW_CELLIr, &rval, 9061 OP_BUFFER_LIMIT_YELLOW_CELLIf, opthd_total_shared_queue_intbuff / 8); 9062 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_YELLOW_CELLIr (unit, rval));/*c270*/ 9063 rval = 0; 9064 soc_reg_field_set(unit, OP_BUFFER_LIMIT_RED_CELLIr, &rval, 9065 OP_BUFFER_LIMIT_RED_CELLIf, opthd_total_shared_queue_intbuff / 8); 9066 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_RED_CELLIr (unit, rval));/*272*/ 9067 rval = 0; 9068 if ((lossless == 0) && (all_int_mem_port || 9069 (int_ext_mem_port && (si->fe.num == 0)))) { 9070 /*all_internal lossy and int-ext lossy c213-448*/ 9071 val = opthd_total_shared_queue_intbuff - 448; 9072 } else { 9073 val = opthd_total_shared_queue_intbuff - 9074 (num_ports / 4 * ethernet_mtu_cells_intbuf); 9075 } 9076 soc_reg_field_set(unit, OP_BUFFER_SHARED_LIMIT_RESUME_CELLIr, &rval, 9077 OP_BUFFER_SHARED_LIMIT_RESUME_CELLIf, val);/*c269*/ 9078 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_SHARED_LIMIT_RESUME_CELLIr (unit,rval)); 9079 rval = 0; 9080 soc_reg_field_set(unit, OP_BUFFER_LIMIT_RESUME_YELLOW_CELLIr, &rval, 9081 OP_BUFFER_LIMIT_RESUME_YELLOW_CELLIf, val / 8);/*c271*/ 9082 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_RESUME_YELLOW_CELLIr(unit, rval)); 9083 rval = 0; 9084 soc_reg_field_set(unit, OP_BUFFER_LIMIT_RESUME_RED_CELLIr, &rval, 9085 OP_BUFFER_LIMIT_RESUME_RED_CELLIf, val / 8); 9086 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_RESUME_RED_CELLIr(unit, rval));/*c273*/ 9087 9088 if (!all_int_mem_port) { /* not applicable for all internal mem port */ 9089 /* Ouput port thresholds */ 9090 /* External Buffer */ 9091 rval = 0;/*c275*/ 9092 soc_reg_field_set(unit, OP_BUFFER_SHARED_LIMIT_CELLEr, &rval, 9093 OP_BUFFER_SHARED_LIMIT_CELLEf, opthd_total_shared_queue_extbuff); 9094 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_SHARED_LIMIT_CELLEr (unit, rval)); 9095 rval = 0;/*c277*/ 9096 soc_reg_field_set(unit, OP_BUFFER_LIMIT_YELLOW_CELLEr, &rval, 9097 OP_BUFFER_LIMIT_YELLOW_CELLEf, opthd_total_shared_queue_extbuff / 8); 9098 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_YELLOW_CELLEr(unit, rval)); 9099 rval = 0;/*c279*/ 9100 soc_reg_field_set(unit, OP_BUFFER_LIMIT_RED_CELLEr, &rval, 9101 OP_BUFFER_LIMIT_RED_CELLEf, opthd_total_shared_queue_extbuff / 8); 9102 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_RED_CELLEr(unit, rval)); 9103 rval = 0;/*c276*/ 9104 val = opthd_total_shared_queue_extbuff - 9105 (num_ports /4 * ethernet_mtu_cells_extbuf); 9106 soc_reg_field_set(unit, OP_BUFFER_SHARED_LIMIT_RESUME_CELLEr, &rval, 9107 OP_BUFFER_SHARED_LIMIT_RESUME_CELLEf, val); 9108 SOC_IF_ERROR_RETURN( 9109 WRITE_OP_BUFFER_SHARED_LIMIT_RESUME_CELLEr(unit, rval)); 9110 rval = 0;/*c278*/ 9111 soc_reg_field_set(unit, OP_BUFFER_LIMIT_RESUME_YELLOW_CELLEr, &rval, 9112 OP_BUFFER_LIMIT_RESUME_YELLOW_CELLEf, val / 8); 9113 SOC_IF_ERROR_RETURN( 9114 WRITE_OP_BUFFER_LIMIT_RESUME_YELLOW_CELLEr(unit, rval)); 9115 rval = 0;/*c280*/ 9116 soc_reg_field_set(unit, OP_BUFFER_LIMIT_RESUME_RED_CELLEr, &rval, 9117 OP_BUFFER_LIMIT_RESUME_RED_CELLEf, val / 8); 9118 SOC_IF_ERROR_RETURN( 9119 WRITE_OP_BUFFER_LIMIT_RESUME_RED_CELLEr(unit, rval)); 9120 9121 /* Ouput port thresholds */ 9122 /* EMA pool */ 9123 rval = 0;/*c282*/ 9124 soc_reg_field_set(unit, OP_BUFFER_SHARED_LIMIT_THDOEMAr, &rval, 9125 OP_BUFFER_SHARED_LIMITf, opthd_total_shared_queue_ema_queue); 9126 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_SHARED_LIMIT_THDOEMAr (unit, rval)); 9127 rval = 0;/*c284*/ 9128 soc_reg_field_set(unit, OP_BUFFER_LIMIT_YELLOW_THDOEMAr, &rval, 9129 OP_BUFFER_LIMIT_YELLOWf, opthd_total_shared_queue_ema_queue / 8); 9130 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_YELLOW_THDOEMAr(unit, rval)); 9131 rval = 0;/*c286*/ 9132 soc_reg_field_set(unit, OP_BUFFER_LIMIT_RED_THDOEMAr, &rval, 9133 OP_BUFFER_LIMIT_REDf, opthd_total_shared_queue_ema_queue / 8); 9134 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_RED_THDOEMAr(unit, rval)); 9135 rval = 0;/*c283*/ 9136 val = opthd_total_shared_queue_ema_queue - 9137 (num_ports /4 * ethernet_mtu_cells_intbuf); 9138 soc_reg_field_set(unit, OP_BUFFER_SHARED_LIMIT_RESUME_THDOEMAr, &rval, 9139 OP_BUFFER_SHARED_LIMIT_RESUMEf, val); 9140 SOC_IF_ERROR_RETURN( 9141 WRITE_OP_BUFFER_SHARED_LIMIT_RESUME_THDOEMAr (unit, rval)); 9142 rval = 0;/*c285*/ 9143 soc_reg_field_set(unit, OP_BUFFER_LIMIT_RESUME_YELLOW_THDOEMAr, &rval, 9144 OP_BUFFER_LIMIT_RESUME_YELLOWf, val / 8); 9145 SOC_IF_ERROR_RETURN( 9146 WRITE_OP_BUFFER_LIMIT_RESUME_YELLOW_THDOEMAr(unit, rval)); 9147 rval = 0;/*c287*/ 9148 soc_reg_field_set(unit, OP_BUFFER_LIMIT_RESUME_RED_THDOEMAr, &rval, 9149 OP_BUFFER_LIMIT_RESUME_REDf, val / 8); 9150 SOC_IF_ERROR_RETURN( 9151 WRITE_OP_BUFFER_LIMIT_RESUME_RED_THDOEMAr(unit, rval)); 9152 } 9153 9154 /* Ouput port thresholds */ 9155 /* RE WQEs*/ 9156 if (opthd_total_shared_queue_rewqe > 8191) { 9157 opthd_total_shared_queue_rewqe = 8191; 9158 } 9159 rval = 0;/*c289*/ 9160 soc_reg_field_set(unit, OP_BUFFER_SHARED_LIMIT_THDORQEQr, &rval, 9161 OP_BUFFER_SHARED_LIMITf, opthd_total_shared_queue_rewqe); 9162 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_SHARED_LIMIT_THDORQEQr (unit, rval)); 9163 rval = 0;/*c291*/ 9164 soc_reg_field_set(unit, OP_BUFFER_LIMIT_YELLOW_THDORQEQr, &rval, 9165 OP_BUFFER_LIMIT_YELLOWf, opthd_total_shared_queue_rewqe / 8); 9166 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_YELLOW_THDORQEQr(unit, rval)); 9167 rval = 0;/*c293*/ 9168 soc_reg_field_set(unit, OP_BUFFER_LIMIT_RED_THDORQEQr, &rval, 9169 OP_BUFFER_LIMIT_REDf, opthd_total_shared_queue_rewqe / 8); 9170 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_RED_THDORQEQr(unit, rval)); 9171 rval = 0;/*c290*/ 9172 val = opthd_total_shared_queue_rewqe - (num_data_ports / 4); 9173 soc_reg_field_set(unit, OP_BUFFER_SHARED_LIMIT_RESUME_THDORQEQr, &rval, 9174 OP_BUFFER_SHARED_LIMIT_RESUMEf, val); 9175 SOC_IF_ERROR_RETURN( 9176 WRITE_OP_BUFFER_SHARED_LIMIT_RESUME_THDORQEQr (unit, rval)); 9177 rval = 0;/*c292*/ 9178 soc_reg_field_set(unit, OP_BUFFER_LIMIT_RESUME_YELLOW_THDORQEQr, &rval, 9179 OP_BUFFER_LIMIT_RESUME_YELLOWf, 9180 opthd_total_shared_queue_rewqe / 8 - 1); 9181 SOC_IF_ERROR_RETURN( 9182 WRITE_OP_BUFFER_LIMIT_RESUME_YELLOW_THDORQEQr(unit, rval)); 9183 rval = 0;/*c294*/ 9184 soc_reg_field_set(unit, OP_BUFFER_LIMIT_RESUME_RED_THDORQEQr, &rval, 9185 OP_BUFFER_LIMIT_RESUME_REDf, 9186 opthd_total_shared_queue_rewqe / 8 - 1); 9187 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_RESUME_RED_THDORQEQr(unit, rval)); 9188 9189 /* Ouput port thresholds */ 9190 /*EQEs*/ 9191 if (opthd_total_shared_queue_eqe > 262143) { 9192 opthd_total_shared_queue_eqe = 262143; 9193 } 9194 rval = 0;/*c296*/ 9195 soc_reg_field_set(unit, OP_BUFFER_SHARED_LIMIT_QENTRYr, &rval, 9196 OP_BUFFER_SHARED_LIMIT_QENTRYf, opthd_total_shared_queue_eqe); 9197 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_SHARED_LIMIT_QENTRYr (unit, rval)); 9198 rval = 0;/*c298*/ 9199 soc_reg_field_set(unit, OP_BUFFER_LIMIT_YELLOW_QENTRYr, &rval, 9200 OP_BUFFER_LIMIT_YELLOW_QENTRYf, opthd_total_shared_queue_eqe / 8); 9201 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_YELLOW_QENTRYr(unit, rval)); 9202 rval = 0;/*c300*/ 9203 soc_reg_field_set(unit, OP_BUFFER_LIMIT_RED_QENTRYr, &rval, 9204 OP_BUFFER_LIMIT_RED_QENTRYf, opthd_total_shared_queue_eqe / 8); 9205 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_RED_QENTRYr(unit, rval)); 9206 rval = 0;/*c297*/ 9207 val = opthd_total_shared_queue_eqe - 9208 (num_data_ports / 4 * ka_mmu_params.num_replication_per_pkt); 9209 soc_reg_field_set(unit, OP_BUFFER_SHARED_LIMIT_RESUME_QENTRYr, &rval, 9210 OP_BUFFER_SHARED_LIMIT_RESUME_QENTRYf, val); 9211 SOC_IF_ERROR_RETURN( 9212 WRITE_OP_BUFFER_SHARED_LIMIT_RESUME_QENTRYr (unit, rval)); 9213 rval = 0;/*c299*/ 9214 soc_reg_field_set(unit, OP_BUFFER_LIMIT_RESUME_YELLOW_QENTRYr, &rval, 9215 OP_BUFFER_LIMIT_RESUME_YELLOW_QENTRYf, val / 8); 9216 SOC_IF_ERROR_RETURN( 9217 WRITE_OP_BUFFER_LIMIT_RESUME_YELLOW_QENTRYr(unit, rval)); 9218 rval = 0;/*c301*/ 9219 soc_reg_field_set(unit, OP_BUFFER_LIMIT_RESUME_RED_QENTRYr, &rval, 9220 OP_BUFFER_LIMIT_RESUME_RED_QENTRYf, val / 8); 9221 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_RESUME_RED_QENTRYr(unit, rval)); 9222 9223 /* Per Port Registers */ 9224 PBMP_ALL_ITER(unit, port) { 9225 pg_num = (port >= 25 && port <= 28) ? 7 : 0; 9226 9227 /* Ports 27,32,33,34 are ports in one MXQ block. 9228 * If more than 2 lanes are enabled then pg_num = 0. 9229 * Same with ports 28,29,30,31. 9230 */ 9231 if ((port == 27) && (SOC_PORT_VALID(unit, 32) || 9232 SOC_PORT_VALID(unit, 33) || SOC_PORT_VALID(unit, 34))) { 9233 pg_num = 0; 9234 } else if ((port == 28) && (SOC_PORT_VALID(unit, 29) || 9235 SOC_PORT_VALID(unit, 30) || SOC_PORT_VALID(unit, 31))) { 9236 pg_num = 0; 9237 } 9238 9239 /* Input Port Thresholds */ 9240 /* Internal Buffer Ingress Pool */ 9241 rval = 0;/*c307*/ 9242 soc_reg_field_set(unit, PORT_MIN_CELLr, &rval, 9243 PORT_MINf, ipthd_per_port_min_intbuf_ingpool); 9244 SOC_IF_ERROR_RETURN(WRITE_PORT_MIN_CELLr (unit, port, rval)); 9245 rval = 0;/*c308*/ 9246 soc_reg_field_set(unit, PORT_MAX_SHARED_CELLr, &rval, 9247 PORT_MAXf, ipthd_total_shared_intbuf_ingpool); 9248 SOC_IF_ERROR_RETURN(WRITE_PORT_MAX_SHARED_CELLr (unit, port, rval)); 9249 rval = 0;/*c309*/ 9250 soc_reg_field_set(unit, PORT_MAX_PKT_SIZEr, &rval, 9251 PORT_MAX_PKT_SIZEf, KA_MMU_MAX_PKT_SIZE_IN_CELLS); 9252 SOC_IF_ERROR_RETURN(WRITE_PORT_MAX_PKT_SIZEr (unit, port, rval)); 9253 rval = 0;/*c310*/ 9254 val = ipthd_total_shared_intbuf_ingpool - 2 * ethernet_mtu_cells_intbuf; 9255 soc_reg_field_set(unit, PORT_RESUME_LIMIT_CELLr, &rval, CELLSf, val); 9256 SOC_IF_ERROR_RETURN(WRITE_PORT_RESUME_LIMIT_CELLr (unit, port, rval)); 9257 rval = 0;/*c311*/ 9258 soc_reg_field_set(unit, PG_MIN_CELLr, &rval, PG_MINf, 9259 ipthd_per_pg_min_intbuf_ingpool); 9260 SOC_IF_ERROR_RETURN(WRITE_PG_MIN_CELLr (unit, port, pg_num, rval)); 9261 if (pg_num) { /*other PGs for port with 8 PGs */ 9262 rval = 0; /*c312*/ 9263 soc_reg_field_set(unit, PG_MIN_CELLr, &rval, PG_MINf, 1); 9264 for (j = 0; j < pg_num; j++) { 9265 SOC_IF_ERROR_RETURN( 9266 WRITE_PG_MIN_CELLr(unit, port, j, rval)); 9267 } 9268 } 9269 rval = 0;/*c313, c316*/ 9270 val = lossless ? KA_MMU_ING_PG_DYN_THD_PARAM : 9271 ipthd_total_shared_intbuf_ingpool; 9272 soc_reg_field_set(unit, PG_SHARED_LIMIT_CELLr, &rval, 9273 PG_SHARED_LIMITf, val); 9274 soc_reg_field_set(unit, PG_SHARED_LIMIT_CELLr, &rval, 9275 PG_SHARED_DYNAMICf, lossless ? 1 : 0); 9276 SOC_IF_ERROR_RETURN( 9277 WRITE_PG_SHARED_LIMIT_CELLr (unit, port, pg_num, rval)); 9278 rval = 0;/*c314*/ 9279 soc_reg_field_set(unit, PG_RESET_OFFSET_CELLr, &rval, 9280 PG_RESET_OFFSETf, 2 * ethernet_mtu_cells_intbuf); 9281 SOC_IF_ERROR_RETURN(WRITE_PG_RESET_OFFSET_CELLr (unit, port, pg_num, rval)); 9282 rval = 0;/*c315*/ 9283 soc_reg_field_set(unit, PG_RESET_FLOOR_CELLr, &rval, PG_RESET_FLOORf,0); 9284 SOC_IF_ERROR_RETURN(WRITE_PG_RESET_FLOOR_CELLr (unit, port, pg_num, rval)); 9285 rval = 0;/*c317*/ 9286 val = (IS_CPU_PORT (unit, port)) ? 0 : 9287 ((IS_HG_PORT (unit, port) || IS_XE_PORT (unit, port)) ? 9288 ka_mmu_params.hg_pg_hdrm_intbuf : 9289 ka_mmu_params.ge_pg_hdrm_intbuf); 9290 soc_reg_field_set(unit, PG_HDRM_LIMIT_CELLr, &rval, 9291 PG_HDRM_LIMITf, val); 9292 SOC_IF_ERROR_RETURN(WRITE_PG_HDRM_LIMIT_CELLr (unit, port, pg_num, rval)); 9293 9294 if (!all_int_mem_port) { /* not applicable for all internal mem port */ 9295 /* Input Port Thresholds */ 9296 /* External Buffer */ 9297 rval = 0;/*c319*/ 9298 soc_reg_field_set(unit, THDIEXT_PORT_MIN_CELLr, &rval, 9299 PORT_MINf, ipthd_per_port_min_extbuf); 9300 SOC_IF_ERROR_RETURN(WRITE_THDIEXT_PORT_MIN_CELLr (unit, port, rval)); 9301 rval = 0;/*c320*/ 9302 soc_reg_field_set(unit, THDIEXT_PORT_MAX_SHARED_CELLr, &rval, 9303 PORT_MAXf, ipthd_total_shared_extbuf); 9304 SOC_IF_ERROR_RETURN( 9305 WRITE_THDIEXT_PORT_MAX_SHARED_CELLr (unit, port, rval)); 9306 rval = 0;/*c321*/ 9307 soc_reg_field_set(unit, THDIEXT_PORT_MAX_PKT_SIZEr, &rval, 9308 PORT_MAX_PKT_SIZEf, KA_MMU_JUMBO_FRAME_EXT_BUF); 9309 SOC_IF_ERROR_RETURN(WRITE_THDIEXT_PORT_MAX_PKT_SIZEr (unit, port,rval)); 9310 rval = 0;/*c322*/ 9311 val = ipthd_total_shared_extbuf - 2 * ethernet_mtu_cells_extbuf; 9312 soc_reg_field_set(unit, THDIEXT_PORT_RESUME_LIMIT_CELLr, &rval, 9313 CELLSf, val); 9314 SOC_IF_ERROR_RETURN( 9315 WRITE_THDIEXT_PORT_RESUME_LIMIT_CELLr (unit, port, rval)); 9316 rval = 0;/*c323*/ 9317 soc_reg_field_set(unit, THDIEXT_PG_MIN_CELLr, &rval, 9318 PG_MINf, ipthd_per_pg_min_extbuf); 9319 SOC_IF_ERROR_RETURN(WRITE_THDIEXT_PG_MIN_CELLr (unit, port, pg_num, rval)); 9320 rval = 0;/*c324, c327*/ 9321 val = lossless ? KA_MMU_ING_PG_DYN_THD_PARAM : 9322 ipthd_total_shared_extbuf; 9323 soc_reg_field_set(unit, THDIEXT_PG_SHARED_LIMIT_CELLr, &rval, 9324 PG_SHARED_LIMITf, val); 9325 soc_reg_field_set(unit, THDIEXT_PG_SHARED_LIMIT_CELLr, &rval, 9326 PG_SHARED_DYNAMICf, lossless ? 1 : 0); 9327 SOC_IF_ERROR_RETURN( 9328 WRITE_THDIEXT_PG_SHARED_LIMIT_CELLr (unit, port, pg_num, rval)); 9329 rval = 0;/*c325*/ 9330 soc_reg_field_set(unit, THDIEXT_PG_RESET_OFFSET_CELLr, &rval, 9331 PG_RESET_OFFSETf, 2 * ethernet_mtu_cells_extbuf); 9332 SOC_IF_ERROR_RETURN( 9333 WRITE_THDIEXT_PG_RESET_OFFSET_CELLr (unit, port, pg_num, rval)); 9334 rval = 0;/*c326*/ 9335 soc_reg_field_set(unit, THDIEXT_PG_RESET_FLOOR_CELLr, &rval, 9336 PG_RESET_FLOORf, 0); 9337 SOC_IF_ERROR_RETURN( 9338 WRITE_THDIEXT_PG_RESET_FLOOR_CELLr(unit,port, pg_num, rval)); 9339 rval = 0;/*c328*/ 9340 val = (IS_CPU_PORT (unit, port)) ? 0 : 9341 ((IS_HG_PORT (unit, port) || IS_XE_PORT (unit, port)) ? 9342 ka_mmu_params.hg_pg_hdrm_extbuf : 9343 ka_mmu_params.ge_pg_hdrm_extbuf); 9344 soc_reg_field_set(unit, THDIEXT_PG_HDRM_LIMIT_CELLr, &rval, 9345 PG_HDRM_LIMITf, val); 9346 SOC_IF_ERROR_RETURN( 9347 WRITE_THDIEXT_PG_HDRM_LIMIT_CELLr (unit, port, pg_num, rval)); 9348 9349 9350 /* Input Port Thresholds */ 9351 /*EMA Pool */ 9352 rval = 0;/*c330*/ 9353 soc_reg_field_set(unit, THDIEMA_PORT_MIN_CELLr, &rval, 9354 PORT_MINf, ipthd_per_port_min_intbuf_emapool); 9355 SOC_IF_ERROR_RETURN(WRITE_THDIEMA_PORT_MIN_CELLr (unit, port, rval)); 9356 rval = 0;/*c331*/ 9357 soc_reg_field_set(unit, THDIEMA_PORT_MAX_SHARED_CELLr, &rval, 9358 PORT_MAXf, ipthd_total_shared_intbuf_emapool); 9359 SOC_IF_ERROR_RETURN( 9360 WRITE_THDIEMA_PORT_MAX_SHARED_CELLr (unit, port, rval)); 9361 rval = 0;/*c332*/ 9362 soc_reg_field_set(unit, THDIEMA_PORT_MAX_PKT_SIZEr, &rval, 9363 PORT_MAX_PKT_SIZEf, KA_MMU_JUMBO_FRAME_INT_BUF); 9364 SOC_IF_ERROR_RETURN(WRITE_THDIEMA_PORT_MAX_PKT_SIZEr (unit, port,rval)); 9365 rval = 0;/*c333*/ 9366 val = ipthd_total_shared_intbuf_emapool - 2 * ethernet_mtu_cells_intbuf; 9367 soc_reg_field_set(unit, THDIEMA_PORT_RESUME_LIMIT_CELLr, &rval, 9368 CELLSf, val); 9369 SOC_IF_ERROR_RETURN( 9370 WRITE_THDIEMA_PORT_RESUME_LIMIT_CELLr (unit, port, rval)); 9371 rval = 0;/*c334*/ 9372 soc_reg_field_set(unit, THDIEMA_PG_MIN_CELLr, &rval, 9373 PG_MINf, ipthd_per_pg_min_intbuf_emapool); 9374 SOC_IF_ERROR_RETURN( 9375 WRITE_THDIEMA_PG_MIN_CELLr (unit, port, pg_num, rval)); 9376 rval = 0;/*c335, c338*/ 9377 val = lossless ? KA_MMU_ING_PG_DYN_THD_PARAM : 9378 ipthd_total_shared_intbuf_emapool; 9379 soc_reg_field_set(unit, THDIEMA_PG_SHARED_LIMIT_CELLr, &rval, 9380 PG_SHARED_LIMITf, val); 9381 soc_reg_field_set(unit, THDIEMA_PG_SHARED_LIMIT_CELLr, &rval, 9382 PG_SHARED_DYNAMICf, lossless ? 1 : 0); 9383 SOC_IF_ERROR_RETURN(WRITE_THDIEMA_PG_SHARED_LIMIT_CELLr (unit, port, 9384 pg_num, rval)); 9385 rval = 0;/*c336*/ 9386 soc_reg_field_set(unit, THDIEMA_PG_RESET_OFFSET_CELLr, &rval, 9387 PG_RESET_OFFSETf, 2 * ethernet_mtu_cells_intbuf); 9388 SOC_IF_ERROR_RETURN(WRITE_THDIEMA_PG_RESET_OFFSET_CELLr (unit, port, 9389 pg_num, rval)); 9390 rval = 0;/*c337*/ 9391 soc_reg_field_set(unit, THDIEMA_PG_RESET_FLOOR_CELLr, &rval, 9392 PG_RESET_FLOORf, 0); 9393 SOC_IF_ERROR_RETURN(WRITE_THDIEMA_PG_RESET_FLOOR_CELLr (unit, port, 9394 pg_num, rval)); 9395 rval = 0;/*c339*/ 9396 val = (IS_CPU_PORT (unit, port)) ? 0 : 9397 ((IS_HG_PORT (unit, port) || IS_XE_PORT (unit, port)) ? 9398 ka_mmu_params.hg_pg_hdrm_ema : 9399 ka_mmu_params.ge_pg_hdrm_ema); 9400 soc_reg_field_set(unit, THDIEMA_PG_HDRM_LIMIT_CELLr, &rval, 9401 PG_HDRM_LIMITf, val); 9402 SOC_IF_ERROR_RETURN( 9403 WRITE_THDIEMA_PG_HDRM_LIMIT_CELLr (unit, port, pg_num, rval)); 9404 9405 }/* if (!all_int_mem_port)*/ 9406 9407 /* Input Port Thresholds */ 9408 /* RE WQEs */ 9409 rval = 0;/*c341*/ 9410 soc_reg_field_set(unit, THDIRQE_PORT_MIN_CELLr, &rval, 9411 PORT_MINf, ipthd_per_port_min_rewqe); 9412 SOC_IF_ERROR_RETURN(WRITE_THDIRQE_PORT_MIN_CELLr (unit, port, rval)); 9413 rval = 0;/*c342*/ 9414 soc_reg_field_set(unit, THDIRQE_PORT_MAX_SHARED_CELLr, &rval, 9415 PORT_MAXf, ipthd_total_shared_rewqe); 9416 SOC_IF_ERROR_RETURN( 9417 WRITE_THDIRQE_PORT_MAX_SHARED_CELLr (unit, port, rval)); 9418 rval = 0;/*c343*/ 9419 soc_reg_field_set(unit, THDIRQE_PORT_RESUME_LIMIT_CELLr, &rval, 9420 CELLSf, ipthd_total_shared_rewqe - 2); 9421 SOC_IF_ERROR_RETURN( 9422 WRITE_THDIRQE_PORT_RESUME_LIMIT_CELLr (unit, port, rval)); 9423 rval = 0;/*c344*/ 9424 soc_reg_field_set(unit, THDIRQE_PG_MIN_CELLr, &rval, 9425 PG_MINf, ipthd_per_pg_min_rewqe); 9426 SOC_IF_ERROR_RETURN(WRITE_THDIRQE_PG_MIN_CELLr (unit, port, 9427 pg_num, rval)); 9428 rval = 0;/*c345, c348*/ 9429 val = lossless ? KA_MMU_ING_PG_DYN_THD_PARAM : ipthd_total_shared_rewqe; 9430 soc_reg_field_set(unit, THDIRQE_PG_SHARED_LIMIT_CELLr, &rval, 9431 PG_SHARED_LIMITf, val); 9432 soc_reg_field_set(unit, THDIRQE_PG_SHARED_LIMIT_CELLr, &rval, 9433 PG_SHARED_DYNAMICf, lossless ? 1 : 0); 9434 SOC_IF_ERROR_RETURN(WRITE_THDIRQE_PG_SHARED_LIMIT_CELLr (unit, port, 9435 pg_num, rval)); 9436 rval = 0;/*c346*/ 9437 soc_reg_field_set(unit, THDIRQE_PG_RESET_OFFSET_CELLr, &rval, 9438 PG_RESET_OFFSETf, 2); 9439 SOC_IF_ERROR_RETURN(WRITE_THDIRQE_PG_RESET_OFFSET_CELLr (unit, port, pg_num, rval)); 9440 rval = 0;/*c347*/ 9441 soc_reg_field_set(unit, THDIRQE_PG_RESET_FLOOR_CELLr, &rval, 9442 PG_RESET_FLOORf, 0); 9443 SOC_IF_ERROR_RETURN(WRITE_THDIRQE_PG_RESET_FLOOR_CELLr (unit, port, 9444 pg_num, rval)); 9445 rval = 0;/*c349*/ 9446 val = (IS_CPU_PORT (unit, port)) ? 0 : 9447 ((IS_HG_PORT (unit, port) || IS_XE_PORT (unit, port)) ? 9448 ka_mmu_params.hg_pg_hdrm_rewqe : 9449 ka_mmu_params.ge_pg_hdrm_rewqe); 9450 soc_reg_field_set(unit, THDIRQE_PG_HDRM_LIMIT_CELLr, &rval, 9451 PG_HDRM_LIMITf, val); 9452 SOC_IF_ERROR_RETURN(WRITE_THDIRQE_PG_HDRM_LIMIT_CELLr (unit, port, 9453 pg_num, rval)); 9454 9455 9456 /* Input Port Thresholds */ 9457 /* EQEs */ 9458 rval = 0;/*c351*/ 9459 soc_reg_field_set(unit, THDIQEN_PORT_MIN_CELLr, &rval, 9460 PORT_MINf, ipthd_per_port_min_eqe); 9461 SOC_IF_ERROR_RETURN(WRITE_THDIQEN_PORT_MIN_CELLr (unit, port, rval)); 9462 rval = 0;/*c352*/ 9463 soc_reg_field_set(unit, THDIQEN_PORT_MAX_SHARED_CELLr, &rval, 9464 PORT_MAXf, ipthd_total_shared_eqe); 9465 SOC_IF_ERROR_RETURN( 9466 WRITE_THDIQEN_PORT_MAX_SHARED_CELLr (unit, port, rval)); 9467 rval = 0;/*c353*/ 9468 val = ipthd_total_shared_eqe - 2 *ka_mmu_params.num_replication_per_pkt; 9469 soc_reg_field_set(unit, THDIQEN_PORT_RESUME_LIMIT_CELLr, &rval, 9470 CELLSf, val); 9471 SOC_IF_ERROR_RETURN( 9472 WRITE_THDIQEN_PORT_RESUME_LIMIT_CELLr (unit, port, rval)); 9473 rval = 0;/*c354*/ 9474 soc_reg_field_set(unit, THDIQEN_PG_MIN_CELLr, &rval, 9475 PG_MINf, ipthd_per_pg_min_eqe); 9476 SOC_IF_ERROR_RETURN(WRITE_THDIQEN_PG_MIN_CELLr (unit, port, 9477 pg_num, rval)); 9478 rval = 0;/*c355, c358*/ 9479 val = lossless ? KA_MMU_ING_PG_DYN_THD_PARAM : ipthd_total_shared_eqe; 9480 soc_reg_field_set(unit, THDIQEN_PG_SHARED_LIMIT_CELLr, &rval, 9481 PG_SHARED_LIMITf, val); 9482 soc_reg_field_set(unit, THDIQEN_PG_SHARED_LIMIT_CELLr, &rval, 9483 PG_SHARED_DYNAMICf, lossless ? 1 : 0); 9484 SOC_IF_ERROR_RETURN(WRITE_THDIQEN_PG_SHARED_LIMIT_CELLr (unit, port, 9485 pg_num, rval)); 9486 rval = 0;/*c356*/ 9487 soc_reg_field_set(unit, THDIQEN_PG_RESET_OFFSET_CELLr, &rval, 9488 PG_RESET_OFFSETf, 2 * ka_mmu_params.num_replication_per_pkt); 9489 SOC_IF_ERROR_RETURN(WRITE_THDIQEN_PG_RESET_OFFSET_CELLr (unit, port, 9490 pg_num, rval)); 9491 rval = 0;/*c357*/ 9492 soc_reg_field_set(unit, THDIQEN_PG_RESET_FLOOR_CELLr, &rval, 9493 PG_RESET_FLOORf, 0); 9494 SOC_IF_ERROR_RETURN(WRITE_THDIQEN_PG_RESET_FLOOR_CELLr (unit, port, 9495 pg_num, rval)); 9496 rval = 0;/*c359*/ 9497 val = (IS_CPU_PORT (unit, port)) ? 0 : 9498 ((IS_HG_PORT (unit, port) || IS_XE_PORT (unit, port)) ? 9499 ipthd_hg_pg_hdrm_eqe : ipthd_ge_pg_hdrm_eqe); 9500 soc_reg_field_set(unit, THDIQEN_PG_HDRM_LIMIT_CELLr, &rval, 9501 PG_HDRM_LIMITf, val); 9502 SOC_IF_ERROR_RETURN(WRITE_THDIQEN_PG_HDRM_LIMIT_CELLr (unit, port, 9503 pg_num, rval)); 9504 } 9505 9506 /* Output port Thresholds */ 9507 opn_index = 0; 9508 PBMP_ALL_ITER(unit, port) { 9509 /* Internal Buffer Egress pool and External Buffer*/ 9510 for (i = 0; i < (IS_CPU_PORT(unit, port) ? 9511 (si->port_num_uc_cosq[port] / 8) : 1); i++) { 9512 SOC_IF_ERROR_RETURN(READ_MMU_THDO_OPNCONFIG_CELLm(unit, 9513 MEM_BLOCK_ANY, opn_index + i, &entry)); 9514 soc_mem_field32_set(unit, MMU_THDO_OPNCONFIG_CELLm, &entry, 9515 OPN_SHARED_LIMIT_CELLf, 9516 (SOC_PBMP_MEMBER(PBMP_EXT_MEM (unit), port) ? 9517 opthd_total_shared_queue_extbuff : 9518 opthd_total_shared_queue_intbuff));/*c363, c379*/ 9519 val = SOC_PBMP_MEMBER(PBMP_EXT_MEM (unit), port) ? 9520 (opthd_total_shared_queue_extbuff - 9521 2 * ethernet_mtu_cells_extbuf) : 9522 (opthd_total_shared_queue_intbuff - 9523 2 * ethernet_mtu_cells_intbuf); 9524 soc_mem_field32_set(unit, MMU_THDO_OPNCONFIG_CELLm, &entry, 9525 OPN_SHARED_RESET_VALUE_CELLf, val);/*c364, c380*/ 9526 soc_mem_field32_set(unit, MMU_THDO_OPNCONFIG_CELLm, &entry, 9527 PORT_LIMIT_ENABLE_CELLf, 0);/*c365*/ 9528 SOC_IF_ERROR_RETURN(WRITE_MMU_THDO_OPNCONFIG_CELLm(unit, 9529 MEM_BLOCK_ANY, opn_index + i, &entry)); 9530 } 9531 opn_index += (IS_CPU_PORT(unit, port) ? 9532 (si->port_num_uc_cosq[port] / 8) : 1); 9533 9534 /* Base COS queues */ 9535 for (i = si->port_cosq_base[port]; 9536 i < si->port_cosq_base[port] + si->port_num_uc_cosq[port]; i++) { 9537 9538 val = lossless ? (SOC_PBMP_MEMBER(PBMP_EXT_MEM (unit), port) ? 9539 opthd_total_shared_queue_extbuff : 9540 opthd_total_shared_queue_intbuff) : 9541 mmu_egr_queue_dyn_thd_param_lossy; 9542 SOC_IF_ERROR_RETURN(READ_MMU_THDO_QOFFSET_CELLm(unit, 9543 MEM_BLOCK_ANY,i,&entry)); 9544 soc_mem_field32_set(unit, MMU_THDO_QOFFSET_CELLm, &entry, 9545 RESET_OFFSET_CELLf, 2);/*c369, 384*/ 9546 soc_mem_field32_set(unit, MMU_THDO_QOFFSET_CELLm, &entry, 9547 LIMIT_RED_CELLf, lossless ? (val / 8) : 0);/*c375, 390*/ 9548 soc_mem_field32_set(unit, MMU_THDO_QOFFSET_CELLm, &entry, 9549 RESET_OFFSET_YELLOW_CELLf, 2);/*c376, 391*/ 9550 soc_mem_field32_set(unit, MMU_THDO_QOFFSET_CELLm, &entry, 9551 RESET_OFFSET_RED_CELLf, 2);/*c377, 392*/ 9552 SOC_IF_ERROR_RETURN(WRITE_MMU_THDO_QOFFSET_CELLm(unit, 9553 MEM_BLOCK_ANY,i,&entry)); 9554 9555 SOC_IF_ERROR_RETURN(READ_MMU_THDO_QCONFIG_CELLm(unit, 9556 MEM_BLOCK_ANY,i,&entry)); 9557 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, &entry, 9558 Q_MIN_CELLf, 9559 (SOC_PBMP_MEMBER(PBMP_EXT_MEM (unit), port) ? 9560 opthd_port_min_grntee_queue_extbuf : 9561 opthd_port_min_grntee_queue_intbuf));/*c366, 382*/ 9562 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, &entry, 9563 Q_SHARED_LIMIT_CELLf, val);/*c368, 383*/ 9564 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, &entry, 9565 Q_LIMIT_DYNAMIC_CELLf, lossless ? 0 : 1);/*c370, 385*/ 9566 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, &entry, 9567 Q_LIMIT_ENABLE_CELLf, lossless ? 0 : 1);/*c371, 386*/ 9568 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, &entry, 9569 Q_COLOR_ENABLE_CELLf, 0);/*c372, 387*/ 9570 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, &entry, 9571 Q_COLOR_LIMIT_DYNAMIC_CELLf, lossless ? 0 : 1);/*c373, 388*/ 9572 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, &entry, 9573 LIMIT_YELLOW_CELLf, lossless ? (val / 8) : 0);/*c374, 389*/ 9574 SOC_IF_ERROR_RETURN(WRITE_MMU_THDO_QCONFIG_CELLm(unit, 9575 MEM_BLOCK_ANY,i,&entry)); 9576 } 9577 } 9578 9579 /* Output port Thresholds */ 9580 /* EMA Pool */ 9581 if (!all_int_mem_port) { /* not applicable for all internal mem port */ 9582 for(i = 0; i < SOC_REG_NUMELS(unit, OP_QUEUE_CONFIG1_THDOEMAr); i++) { 9583 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_CONFIG1_THDOEMAr(unit, i, &rval)); 9584 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_THDOEMAr, &rval, 9585 Q_MINf, opthd_port_min_grntee_ema_queue);/*c409*/ 9586 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_THDOEMAr, &rval, 9587 Q_COLOR_ENABLEf, 0);/*c414*/ 9588 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_THDOEMAr, &rval, 9589 Q_COLOR_DYNAMICf, lossless ? 0 : 1);/*c415*/ 9590 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_CONFIG1_THDOEMAr(unit, i, rval)); 9591 } 9592 9593 for(i = 0; i < SOC_REG_NUMELS(unit, OP_QUEUE_RESET_OFFSET_THDOEMAr); 9594 i++) { 9595 SOC_IF_ERROR_RETURN( 9596 READ_OP_QUEUE_RESET_OFFSET_THDOEMAr(unit, i,&rval)); 9597 soc_reg_field_set(unit, OP_QUEUE_RESET_OFFSET_THDOEMAr, &rval, 9598 Q_RESET_OFFSETf, 2);/*c411*/ 9599 SOC_IF_ERROR_RETURN( 9600 WRITE_OP_QUEUE_RESET_OFFSET_THDOEMAr(unit, i,rval)); 9601 } 9602 for(i = 0; i < SOC_REG_NUMELS(unit, 9603 OP_QUEUE_RESET_OFFSET_YELLOW_THDOEMAr); i++) { 9604 SOC_IF_ERROR_RETURN( 9605 READ_OP_QUEUE_RESET_OFFSET_YELLOW_THDOEMAr(unit, i,&rval)); 9606 soc_reg_field_set(unit, 9607 OP_QUEUE_RESET_OFFSET_YELLOW_THDOEMAr, &rval, 9608 RESUME_OFFSET_YELLOWf, 2);/*c418*/ 9609 SOC_IF_ERROR_RETURN( 9610 WRITE_OP_QUEUE_RESET_OFFSET_YELLOW_THDOEMAr(unit, i,rval)); 9611 } 9612 for(i = 0; i < SOC_REG_NUMELS(unit, 9613 OP_QUEUE_RESET_OFFSET_RED_THDOEMAr); i++) { 9614 SOC_IF_ERROR_RETURN( 9615 READ_OP_QUEUE_RESET_OFFSET_RED_THDOEMAr(unit, i,&rval)); 9616 soc_reg_field_set(unit, OP_QUEUE_RESET_OFFSET_RED_THDOEMAr, &rval, 9617 RESUME_OFFSET_REDf, 2);/*c419*/ 9618 SOC_IF_ERROR_RETURN( 9619 WRITE_OP_QUEUE_RESET_OFFSET_RED_THDOEMAr(unit, i,rval)); 9620 } 9621 9622 val = lossless ? opthd_total_shared_queue_ema_queue : 9623 mmu_egr_queue_dyn_thd_param_lossy; 9624 for(i = 0; i < SOC_REG_NUMELS(unit, OP_QUEUE_CONFIG_THDOEMAr); i++) { 9625 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_CONFIG_THDOEMAr(unit, i, &rval)); 9626 soc_reg_field_set(unit, OP_QUEUE_CONFIG_THDOEMAr, &rval, 9627 Q_SHARED_LIMITf, val);/*c410*/ 9628 soc_reg_field_set(unit, OP_QUEUE_CONFIG_THDOEMAr, &rval, 9629 Q_LIMIT_DYNAMICf, lossless ? 0 : 1);/*c412*/ 9630 soc_reg_field_set(unit, OP_QUEUE_CONFIG_THDOEMAr, &rval, 9631 Q_LIMIT_ENABLEf, lossless ? 0 : 1);/*c413*/ 9632 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_CONFIG_THDOEMAr(unit, i, rval)); 9633 } 9634 for(i = 0; i < SOC_REG_NUMELS(unit, 9635 OP_QUEUE_LIMIT_YELLOW_THDOEMAr); i++) { 9636 SOC_IF_ERROR_RETURN( 9637 READ_OP_QUEUE_LIMIT_YELLOW_THDOEMAr(unit, i,&rval)); 9638 soc_reg_field_set(unit, OP_QUEUE_LIMIT_YELLOW_THDOEMAr, &rval, 9639 Q_LIMIT_YELLOWf, lossless ? (val / 8) : 0);/*c416*/ 9640 SOC_IF_ERROR_RETURN( 9641 WRITE_OP_QUEUE_LIMIT_YELLOW_THDOEMAr(unit, i,rval)); 9642 } 9643 for(i = 0; i < SOC_REG_NUMELS(unit, 9644 OP_QUEUE_LIMIT_RED_THDOEMAr); i++) { 9645 SOC_IF_ERROR_RETURN( 9646 READ_OP_QUEUE_LIMIT_RED_THDOEMAr(unit, i,&rval)); 9647 soc_reg_field_set(unit, OP_QUEUE_LIMIT_RED_THDOEMAr, &rval, 9648 Q_LIMIT_REDf, lossless ? (val / 8) : 0);/*c417*/ 9649 SOC_IF_ERROR_RETURN( 9650 WRITE_OP_QUEUE_LIMIT_RED_THDOEMAr(unit, i,rval)); 9651 } 9652 } /* if (!all_int_mem_port) */ 9653 9654 /* Output port Thresholds */ 9655 /* RE WQs - RQEQ */ 9656 for(i = 0; i < SOC_REG_NUMELS(unit, OP_QUEUE_CONFIG1_THDORQEQr); i++) { 9657 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_CONFIG1_THDORQEQr(unit, i, &rval)); 9658 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_THDORQEQr, &rval, 9659 Q_MINf, opthd_port_min_grntee_rewqe);/*c421*/ 9660 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_THDORQEQr, &rval, 9661 Q_COLOR_ENABLEf, 0);/*c426*/ 9662 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_THDORQEQr, &rval, 9663 Q_COLOR_DYNAMICf, lossless ? 0 : 1);/*c427*/ 9664 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_CONFIG1_THDORQEQr(unit, i, rval)); 9665 } 9666 for(i = 0; i < SOC_REG_NUMELS(unit, OP_QUEUE_RESET_OFFSET_THDORQEQr); i++) { 9667 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_RESET_OFFSET_THDORQEQr(unit,i,&rval)); 9668 soc_reg_field_set(unit, OP_QUEUE_RESET_OFFSET_THDORQEQr, &rval, 9669 Q_RESET_OFFSETf, 1);/*c423*/ 9670 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_RESET_OFFSET_THDORQEQr(unit,i,rval)); 9671 } 9672 for(i = 0; i < SOC_REG_NUMELS(unit, 9673 OP_QUEUE_RESET_OFFSET_YELLOW_THDORQEQr); i++) { 9674 SOC_IF_ERROR_RETURN( 9675 READ_OP_QUEUE_RESET_OFFSET_YELLOW_THDORQEQr(unit, i,&rval)); 9676 soc_reg_field_set(unit, 9677 OP_QUEUE_RESET_OFFSET_YELLOW_THDORQEQr, &rval, 9678 RESUME_OFFSET_YELLOWf, 1);/*c430*/ 9679 SOC_IF_ERROR_RETURN( 9680 WRITE_OP_QUEUE_RESET_OFFSET_YELLOW_THDORQEQr(unit, i,rval)); 9681 } 9682 for(i = 0; i < SOC_REG_NUMELS(unit, 9683 OP_QUEUE_RESET_OFFSET_RED_THDORQEQr); i++) { 9684 SOC_IF_ERROR_RETURN( 9685 READ_OP_QUEUE_RESET_OFFSET_RED_THDORQEQr(unit, i,&rval)); 9686 soc_reg_field_set(unit, OP_QUEUE_RESET_OFFSET_RED_THDORQEQr, &rval, 9687 RESUME_OFFSET_REDf, 1);/*c431*/ 9688 SOC_IF_ERROR_RETURN( 9689 WRITE_OP_QUEUE_RESET_OFFSET_RED_THDORQEQr(unit, i,rval)); 9690 } 9691 9692 val = lossless ? opthd_total_shared_queue_rewqe : 9693 mmu_egr_queue_dyn_thd_param_lossy; 9694 for(i = 0; i < SOC_REG_NUMELS(unit, OP_QUEUE_CONFIG_THDORQEQr); i++) { 9695 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_CONFIG_THDORQEQr(unit, i, &rval)); 9696 soc_reg_field_set(unit, OP_QUEUE_CONFIG_THDORQEQr, &rval, 9697 Q_SHARED_LIMITf, val);/*c422*/ 9698 soc_reg_field_set(unit, OP_QUEUE_CONFIG_THDORQEQr, &rval, 9699 Q_LIMIT_DYNAMICf, lossless ? 0 : 1);/*c424*/ 9700 soc_reg_field_set(unit, OP_QUEUE_CONFIG_THDORQEQr, &rval, 9701 Q_LIMIT_ENABLEf, lossless ? 0 : 1);/*c425*/ 9702 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_CONFIG_THDORQEQr(unit, i, rval)); 9703 } 9704 for(i = 0; i < SOC_REG_NUMELS(unit, OP_QUEUE_LIMIT_RED_THDORQEQr); i++) { 9705 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_LIMIT_RED_THDORQEQr(unit, i,&rval)); 9706 soc_reg_field_set(unit, OP_QUEUE_LIMIT_RED_THDORQEQr, &rval, 9707 Q_LIMIT_REDf, lossless ? (val / 8) : 0);/*c428*/ 9708 SOC_IF_ERROR_RETURN( 9709 WRITE_OP_QUEUE_LIMIT_RED_THDORQEQr(unit, i,rval)); 9710 } 9711 for(i = 0; i < SOC_REG_NUMELS(unit, OP_QUEUE_LIMIT_YELLOW_THDORQEQr); i++) { 9712 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_LIMIT_YELLOW_THDORQEQr(unit,i,&rval)); 9713 soc_reg_field_set(unit, OP_QUEUE_LIMIT_YELLOW_THDORQEQr, &rval, 9714 Q_LIMIT_YELLOWf, lossless ? (val / 8) : 0);/*c429*/ 9715 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_LIMIT_YELLOW_THDORQEQr(unit,i,rval)); 9716 } 9717 9718 /* RE WQs - RQEI */ 9719 for(i = 0; i < SOC_REG_NUMELS(unit, OP_QUEUE_CONFIG1_THDORQEIr); i++) { 9720 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_CONFIG1_THDORQEIr(unit, i, &rval)); 9721 9722 if (i < 8) { /*MC traffic queue 0 to 7*/ 9723 q_min = opthd_port_min_grntee_rewqe_intbuf_mc;/*c432*/ 9724 q_color_dyn = lossless ? 1 : (all_ext_mem_port ? 1 : 0);/*c446*/ 9725 } else if ((i >= 8) && (i < 10)) { /*copy-to-cpu traffic queue 8 and 9*/ 9726 q_min = opthd_port_min_grntee_rewqe_intbuf_tocpu;/*c433*/ 9727 q_color_dyn = 1;/*c447*/ 9728 } else if (i >= 10) { /* Mirror traffic queue 10 and 11*/ 9729 q_min = opthd_port_min_grntee_rewqe_intbuf_mirror;/*c434*/ 9730 q_color_dyn = 1;/*c448*/ 9731 } 9732 9733 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_THDORQEIr, &rval, 9734 Q_MINf, q_min);/*c432,433,434*/ 9735 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_THDORQEIr, &rval, 9736 Q_COLOR_ENABLEf, 0); 9737 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_THDORQEIr, &rval, 9738 Q_COLOR_DYNAMICf, q_color_dyn);/*c446,447,448*/ 9739 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_CONFIG1_THDORQEIr(unit, i, rval)); 9740 } 9741 9742 for(i = 0; i < SOC_REG_NUMELS(unit, OP_QUEUE_RESET_OFFSET_THDORQEIr); i++) { 9743 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_RESET_OFFSET_THDORQEIr(unit,i,&rval)); 9744 soc_reg_field_set(unit, OP_QUEUE_RESET_OFFSET_THDORQEIr, &rval, 9745 Q_RESET_OFFSETf, lossless ? 2 : 9746 (all_ext_mem_port ? 2 : 9747 ((i < 8) ? 9748 (448 / 8) : 2)));/*c438,439,440*/ 9749 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_RESET_OFFSET_THDORQEIr(unit,i,rval)); 9750 } 9751 9752 for(i = 0; i < SOC_REG_NUMELS(unit, 9753 OP_QUEUE_RESET_OFFSET_YELLOW_THDORQEIr); i++) { 9754 SOC_IF_ERROR_RETURN( 9755 READ_OP_QUEUE_RESET_OFFSET_YELLOW_THDORQEIr(unit, i,&rval)); 9756 soc_reg_field_set(unit, 9757 OP_QUEUE_RESET_OFFSET_YELLOW_THDORQEIr, &rval, 9758 RESUME_OFFSET_YELLOWf, lossless ? 2 : 9759 (all_ext_mem_port ? 2 : 9760 ((i < 8) ? 9761 (448 / 8) : 2)));/*c455,456,457*/ 9762 SOC_IF_ERROR_RETURN( 9763 WRITE_OP_QUEUE_RESET_OFFSET_YELLOW_THDORQEIr(unit, i,rval)); 9764 } 9765 9766 for(i = 0; i < SOC_REG_NUMELS(unit, 9767 OP_QUEUE_RESET_OFFSET_RED_THDORQEIr); i++) { 9768 SOC_IF_ERROR_RETURN( 9769 READ_OP_QUEUE_RESET_OFFSET_RED_THDORQEIr(unit, i,&rval)); 9770 soc_reg_field_set(unit, OP_QUEUE_RESET_OFFSET_RED_THDORQEIr, &rval, 9771 RESUME_OFFSET_REDf, lossless ? 2 : 9772 (all_ext_mem_port ? 2 : 9773 ((i < 8) ? 9774 (448 / 8) : 2)));/*c458,459,460*/ 9775 SOC_IF_ERROR_RETURN( 9776 WRITE_OP_QUEUE_RESET_OFFSET_RED_THDORQEIr(unit, i,rval)); 9777 } 9778 9779 val = lossless ? opthd_total_shared_queue_rewqe_intbuf : 9780 mmu_egr_queue_dyn_thd_param_lossy; 9781 for(i = 0; i < SOC_REG_NUMELS(unit, OP_QUEUE_CONFIG_THDORQEIr); i++) { 9782 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_CONFIG_THDORQEIr(unit, i, &rval)); 9783 soc_reg_field_set(unit, OP_QUEUE_CONFIG_THDORQEIr, &rval, 9784 Q_SHARED_LIMITf, lossless ? 7 : 9785 (all_ext_mem_port ? 7 : 9786 ((i < 8) ? 9787 896 : 7)));/*c435,436,437*/ 9788 soc_reg_field_set(unit, OP_QUEUE_CONFIG_THDORQEIr, &rval, 9789 Q_LIMIT_DYNAMICf, lossless ? 1 : 9790 (all_ext_mem_port ? 1 : 9791 ((i < 8) ? 9792 0 : 1)));/*c441,442,443*/ 9793 soc_reg_field_set(unit, OP_QUEUE_CONFIG_THDORQEIr, &rval, 9794 Q_LIMIT_ENABLEf, lossless ? 0 : 1);/*c444*/ 9795 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_CONFIG_THDORQEIr(unit, i, rval)); 9796 } 9797 9798 for(i = 0; i < SOC_REG_NUMELS(unit, OP_QUEUE_LIMIT_RED_THDORQEIr); i++) { 9799 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_LIMIT_RED_THDORQEIr(unit, i,&rval)); 9800 soc_reg_field_set(unit, OP_QUEUE_LIMIT_RED_THDORQEIr, &rval, 9801 Q_LIMIT_REDf, lossless ? 0 : 9802 (all_ext_mem_port ? 0 : 9803 ((i < 8) ? 9804 896 : 0)));/*c452,453,545*/ 9805 SOC_IF_ERROR_RETURN( 9806 WRITE_OP_QUEUE_LIMIT_RED_THDORQEIr(unit, i,rval)); 9807 } 9808 9809 for(i = 0; i < SOC_REG_NUMELS(unit, OP_QUEUE_LIMIT_YELLOW_THDORQEIr); i++) { 9810 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_LIMIT_YELLOW_THDORQEIr(unit,i,&rval)); 9811 soc_reg_field_set(unit, OP_QUEUE_LIMIT_YELLOW_THDORQEIr, &rval, 9812 Q_LIMIT_YELLOWf, lossless ? 0 : 9813 (all_ext_mem_port ? 0 : 9814 ((i < 8) ? 9815 896 : 0)));/*c449,450,451*/ 9816 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_LIMIT_YELLOW_THDORQEIr(unit,i,rval)); 9817 } 9818 9819 /* RE WQs - RQEE */ 9820 if (!all_int_mem_port) { /* not applicable for all internal mem port */ 9821 for(i = 0; i < SOC_REG_NUMELS(unit, OP_QUEUE_CONFIG1_THDORQEEr); i++) { 9822 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_CONFIG1_THDORQEEr(unit, i,&rval)); 9823 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_THDORQEEr, &rval, 9824 Q_MINf, opthd_port_min_grntee_rewqe_extbuf);/*c461*/ 9825 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_THDORQEEr, &rval, 9826 Q_COLOR_ENABLEf, 0);/*c466*/ 9827 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_THDORQEEr, &rval, 9828 Q_COLOR_DYNAMICf, lossless ? 0 : 1);/*c467*/ 9829 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_CONFIG1_THDORQEEr(unit, i,rval)); 9830 } 9831 9832 for(i = 0; 9833 i < SOC_REG_NUMELS(unit, OP_QUEUE_RESET_OFFSET_THDORQEEr); i++) { 9834 SOC_IF_ERROR_RETURN( 9835 READ_OP_QUEUE_RESET_OFFSET_THDORQEEr(unit, i, &rval)); 9836 soc_reg_field_set(unit, OP_QUEUE_RESET_OFFSET_THDORQEEr, &rval, 9837 Q_RESET_OFFSETf, 2);/*c463*/ 9838 SOC_IF_ERROR_RETURN( 9839 WRITE_OP_QUEUE_RESET_OFFSET_THDORQEEr(unit, i, rval)); 9840 } 9841 9842 for(i = 0; i < SOC_REG_NUMELS(unit, 9843 OP_QUEUE_RESET_OFFSET_YELLOW_THDORQEEr); i++) { 9844 SOC_IF_ERROR_RETURN( 9845 READ_OP_QUEUE_RESET_OFFSET_YELLOW_THDORQEEr(unit, i,&rval)); 9846 soc_reg_field_set(unit, 9847 OP_QUEUE_RESET_OFFSET_YELLOW_THDORQEEr, &rval, 9848 RESUME_OFFSET_YELLOWf, 2);/*c470*/ 9849 SOC_IF_ERROR_RETURN( 9850 WRITE_OP_QUEUE_RESET_OFFSET_YELLOW_THDORQEEr(unit, i,rval)); 9851 } 9852 9853 for(i = 0; i < SOC_REG_NUMELS(unit, 9854 OP_QUEUE_RESET_OFFSET_RED_THDORQEEr); i++) { 9855 SOC_IF_ERROR_RETURN( 9856 READ_OP_QUEUE_RESET_OFFSET_RED_THDORQEEr(unit, i,&rval)); 9857 soc_reg_field_set(unit, OP_QUEUE_RESET_OFFSET_RED_THDORQEEr, &rval, 9858 RESUME_OFFSET_REDf, 2);/*c471*/ 9859 SOC_IF_ERROR_RETURN( 9860 WRITE_OP_QUEUE_RESET_OFFSET_RED_THDORQEEr(unit, i,rval)); 9861 } 9862 9863 val = lossless ? opthd_total_shared_queue_rewqe_extbuf : 9864 mmu_egr_queue_dyn_thd_param_lossy; 9865 for(i = 0; i < SOC_REG_NUMELS(unit, OP_QUEUE_CONFIG_THDORQEEr); i++) { 9866 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_CONFIG_THDORQEEr(unit, i, &rval)); 9867 soc_reg_field_set(unit, OP_QUEUE_CONFIG_THDORQEEr, &rval, 9868 Q_SHARED_LIMITf, val);/*c462*/ 9869 soc_reg_field_set(unit, OP_QUEUE_CONFIG_THDORQEEr, &rval, 9870 Q_LIMIT_DYNAMICf, lossless ? 0 : 1);/*c464*/ 9871 soc_reg_field_set(unit, OP_QUEUE_CONFIG_THDORQEEr, &rval, 9872 Q_LIMIT_ENABLEf, lossless ? 0 : 1);/*c465*/ 9873 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_CONFIG_THDORQEEr(unit, i, rval)); 9874 } 9875 9876 for(i = 0; i < SOC_REG_NUMELS(unit, OP_QUEUE_LIMIT_RED_THDORQEEr); i++) { 9877 SOC_IF_ERROR_RETURN( 9878 READ_OP_QUEUE_LIMIT_RED_THDORQEEr(unit, i,&rval)); 9879 soc_reg_field_set(unit, OP_QUEUE_LIMIT_RED_THDORQEEr, &rval, 9880 Q_LIMIT_REDf, lossless ? (val / 8) : 0);/*c469*/ 9881 SOC_IF_ERROR_RETURN( 9882 WRITE_OP_QUEUE_LIMIT_RED_THDORQEEr(unit, i,rval)); 9883 } 9884 9885 for(i = 0; i < SOC_REG_NUMELS(unit, 9886 OP_QUEUE_LIMIT_YELLOW_THDORQEEr); i++) { 9887 SOC_IF_ERROR_RETURN( 9888 READ_OP_QUEUE_LIMIT_YELLOW_THDORQEEr(unit,i,&rval)); 9889 soc_reg_field_set(unit, OP_QUEUE_LIMIT_YELLOW_THDORQEEr, &rval, 9890 Q_LIMIT_YELLOWf, lossless ? (val / 8) : 0);/*c468*/ 9891 SOC_IF_ERROR_RETURN( 9892 WRITE_OP_QUEUE_LIMIT_YELLOW_THDORQEEr(unit,i,rval)); 9893 } 9894 } /* if (!all_int_mem_port) */ 9895 9896 /* Output port Thresholds */ 9897 opn_index = 0; 9898 PBMP_ALL_ITER(unit, port) { 9899 /* EQEs */ 9900 for (i = 0; i < (IS_CPU_PORT(unit, port) ? 9901 (si->port_num_uc_cosq[port] / 8) : 1); i++) { 9902 9903 SOC_IF_ERROR_RETURN(READ_MMU_THDO_OPNCONFIG_QENTRYm(unit, 9904 MEM_BLOCK_ANY, opn_index + i, &entry)); 9905 soc_mem_field32_set(unit, MMU_THDO_OPNCONFIG_QENTRYm, &entry, 9906 OPN_SHARED_LIMIT_QENTRYf,opthd_total_shared_queue_eqe);/*c394*/ 9907 soc_mem_field32_set(unit, MMU_THDO_OPNCONFIG_QENTRYm, &entry, 9908 OPN_SHARED_RESET_VALUE_QENTRYf, 9909 opthd_total_shared_queue_eqe - 2);/*c395*/ 9910 soc_mem_field32_set(unit, MMU_THDO_OPNCONFIG_QENTRYm, &entry, 9911 PORT_LIMIT_ENABLE_QENTRYf, 0);/*c396*/ 9912 SOC_IF_ERROR_RETURN(WRITE_MMU_THDO_OPNCONFIG_QENTRYm(unit, 9913 MEM_BLOCK_ANY,opn_index + i, &entry)); 9914 } 9915 opn_index += (IS_CPU_PORT(unit, port) ? 9916 (si->port_num_uc_cosq[port] / 8) : 1); 9917 9918 for (i = si->port_cosq_base[port]; 9919 i < si->port_cosq_base[port] + si->port_num_uc_cosq[port]; i++) { 9920 9921 val = lossless ? opthd_total_shared_queue_eqe : 9922 mmu_egr_queue_dyn_thd_param_lossy; 9923 9924 SOC_IF_ERROR_RETURN(READ_MMU_THDO_QOFFSET_QENTRYm(unit, 9925 MEM_BLOCK_ANY,i,&entry)); 9926 soc_mem_field32_set(unit, MMU_THDO_QOFFSET_QENTRYm, &entry, 9927 RESET_OFFSET_QENTRYf, 1);/*c399*/ 9928 soc_mem_field32_set(unit, MMU_THDO_QOFFSET_QENTRYm, &entry, 9929 LIMIT_RED_QENTRYf, lossless ? (val/8) : 0);/*c405*/ 9930 soc_mem_field32_set(unit, MMU_THDO_QOFFSET_QENTRYm, &entry, 9931 RESET_OFFSET_YELLOW_QENTRYf, 1);/*c406*/ 9932 soc_mem_field32_set(unit, MMU_THDO_QOFFSET_QENTRYm, &entry, 9933 RESET_OFFSET_RED_QENTRYf, 1);/*c407*/ 9934 SOC_IF_ERROR_RETURN(WRITE_MMU_THDO_QOFFSET_QENTRYm(unit, 9935 MEM_BLOCK_ANY,i,&entry)); 9936 9937 SOC_IF_ERROR_RETURN(READ_MMU_THDO_QCONFIG_QENTRYm(unit, 9938 MEM_BLOCK_ANY,i,&entry)); 9939 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_QENTRYm, &entry, 9940 Q_MIN_QENTRYf, opthd_port_min_grntee_eqe);/*c397*/ 9941 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_QENTRYm, &entry, 9942 Q_SHARED_LIMIT_QENTRYf, val);/*c398*/ 9943 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_QENTRYm, &entry, 9944 Q_LIMIT_DYNAMIC_QENTRYf, lossless ? 0 : 1);/*c400*/ 9945 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_QENTRYm, &entry, 9946 Q_LIMIT_ENABLE_QENTRYf, lossless ? 0 : 1);/*c401*/ 9947 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_QENTRYm, &entry, 9948 Q_COLOR_ENABLE_QENTRYf, 0);/*c402*/ 9949 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_QENTRYm, &entry, 9950 Q_COLOR_LIMIT_DYNAMIC_QENTRYf, lossless ? 0 : 1);/*c403*/ 9951 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_QENTRYm, &entry, 9952 LIMIT_YELLOW_QENTRYf, lossless ? (val/8) : 0);/*c404*/ 9953 SOC_IF_ERROR_RETURN(WRITE_MMU_THDO_QCONFIG_QENTRYm(unit, 9954 MEM_BLOCK_ANY,i,&entry)); 9955 } 9956 9957 /* Enable back pressure status from MMU for lossless mode */ 9958 if (lossless) { 9959 COMPILER_64_SET(val64, 0xf, 0xffffffff); 9960 COMPILER_64_ZERO(r64val); 9961 soc_reg64_field_set(unit, THDIEXT_PORT_PAUSE_ENABLE0_64r, &r64val, 9962 PORT_PAUSE_ENABLEf, val64); 9963 SOC_IF_ERROR_RETURN( 9964 WRITE_THDIEXT_PORT_PAUSE_ENABLE0_64r(unit, r64val)); 9965 9966 COMPILER_64_ZERO(r64val); 9967 soc_reg64_field_set(unit, THDIQEN_PORT_PAUSE_ENABLE0_64r, &r64val, 9968 PORT_PAUSE_ENABLEf, val64); 9969 SOC_IF_ERROR_RETURN( 9970 WRITE_THDIQEN_PORT_PAUSE_ENABLE0_64r(unit, r64val)); 9971 9972 COMPILER_64_ZERO(r64val); 9973 soc_reg64_field_set(unit, THDIRQE_PORT_PAUSE_ENABLE0_64r, &r64val, 9974 PORT_PAUSE_ENABLEf, val64); 9975 SOC_IF_ERROR_RETURN( 9976 WRITE_THDIRQE_PORT_PAUSE_ENABLE0_64r(unit, r64val)); 9977 9978 COMPILER_64_ZERO(r64val); 9979 soc_reg64_field_set(unit, THDIEMA_PORT_PAUSE_ENABLE0_64r, &r64val, 9980 PORT_PAUSE_ENABLEf, val64); 9981 SOC_IF_ERROR_RETURN( 9982 WRITE_THDIEMA_PORT_PAUSE_ENABLE0_64r(unit, r64val)); 9983 9984 COMPILER_64_ZERO(r64val); 9985 soc_reg64_field_set(unit, PORT_PAUSE_ENABLE0_64r, &r64val, 9986 PORT_PAUSE_ENABLEf, val64); 9987 SOC_IF_ERROR_RETURN( 9988 WRITE_PORT_PAUSE_ENABLE0_64r(unit, r64val)); 9989 9990 COMPILER_64_SET(val64, 0x1, 0xffffffff); 9991 COMPILER_64_ZERO(r64val); 9992 soc_reg64_field_set(unit, THDIEXT_PORT_PAUSE_ENABLE1_64r, &r64val, 9993 PORT_PAUSE_ENABLEf, val64); 9994 SOC_IF_ERROR_RETURN( 9995 WRITE_THDIEXT_PORT_PAUSE_ENABLE1_64r(unit, r64val)); 9996 9997 COMPILER_64_ZERO(r64val); 9998 soc_reg64_field_set(unit, THDIQEN_PORT_PAUSE_ENABLE1_64r, &r64val, 9999 PORT_PAUSE_ENABLEf, val64); 10000 SOC_IF_ERROR_RETURN( 10001 WRITE_THDIQEN_PORT_PAUSE_ENABLE1_64r(unit, r64val)); 10002 10003 COMPILER_64_ZERO(r64val); 10004 soc_reg64_field_set(unit, THDIRQE_PORT_PAUSE_ENABLE1_64r, &r64val, 10005 PORT_PAUSE_ENABLEf, val64); 10006 SOC_IF_ERROR_RETURN( 10007 WRITE_THDIRQE_PORT_PAUSE_ENABLE1_64r(unit, r64val)); 10008 10009 COMPILER_64_ZERO(r64val); 10010 soc_reg64_field_set(unit, THDIEMA_PORT_PAUSE_ENABLE1_64r, &r64val, 10011 PORT_PAUSE_ENABLEf, val64); 10012 SOC_IF_ERROR_RETURN( 10013 WRITE_THDIEMA_PORT_PAUSE_ENABLE1_64r(unit, r64val)); 10014 10015 COMPILER_64_ZERO(r64val); 10016 soc_reg64_field_set(unit, PORT_PAUSE_ENABLE1_64r, &r64val, 10017 PORT_PAUSE_ENABLEf, val64); 10018 SOC_IF_ERROR_RETURN( 10019 WRITE_PORT_PAUSE_ENABLE1_64r(unit, r64val)); 10020 } 10021 } 10022 10023 /* Extended COS Queues */ 10024 val = lossless ? (all_ext_mem_port ? 10025 opthd_total_shared_queue_extbuff : 10026 opthd_total_shared_queue_intbuff) : 10027 mmu_egr_queue_dyn_thd_param_lossy; 10028 for (j = si->num_mmu_base_cosq; 10029 j < soc_mem_index_max(unit,MMU_THDO_QCONFIG_CELLm); j++) { 10030 /* Output port threshold Internal/External Buffer*/ 10031 10032 SOC_IF_ERROR_RETURN(READ_MMU_THDO_QCONFIG_CELLm(unit, 10033 MEM_BLOCK_ANY, j, &entry)); 10034 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, &entry, 10035 Q_MIN_CELLf, all_int_mem_port ? 10036 0 : opthd_port_min_grntee_queue_extbuf);/*c367, c382*/ 10037 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, &entry, 10038 Q_SHARED_LIMIT_CELLf, val);/*c368, 383*/ 10039 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, &entry, 10040 Q_LIMIT_DYNAMIC_CELLf, lossless ? 0 : 1);/*c370, 385*/ 10041 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, &entry, 10042 Q_LIMIT_ENABLE_CELLf, lossless ? 0 : 1);/*c371, 386*/ 10043 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, &entry, 10044 Q_COLOR_ENABLE_CELLf, 0);/*c372, 387*/ 10045 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, &entry, 10046 Q_COLOR_LIMIT_DYNAMIC_CELLf, lossless ? 0 : 1);/*c373, 388*/ 10047 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, &entry, 10048 LIMIT_YELLOW_CELLf, lossless ? (val / 8) : 0);/*c374, 389*/ 10049 SOC_IF_ERROR_RETURN(WRITE_MMU_THDO_QCONFIG_CELLm(unit, 10050 MEM_BLOCK_ANY, j, &entry)); 10051 10052 SOC_IF_ERROR_RETURN(READ_MMU_THDO_QOFFSET_CELLm(unit, 10053 MEM_BLOCK_ANY, j, &entry)); 10054 soc_mem_field32_set(unit, MMU_THDO_QOFFSET_CELLm, &entry, 10055 RESET_OFFSET_CELLf, 2);/*c369, 384*/ 10056 soc_mem_field32_set(unit, MMU_THDO_QOFFSET_CELLm, &entry, 10057 RESET_OFFSET_YELLOW_CELLf, 2);/*c376, 391*/ 10058 soc_mem_field32_set(unit, MMU_THDO_QOFFSET_CELLm, &entry, 10059 RESET_OFFSET_RED_CELLf, 2);/*c377, 392*/ 10060 soc_mem_field32_set(unit, MMU_THDO_QOFFSET_CELLm, &entry, 10061 LIMIT_RED_CELLf, lossless ? (val / 8) : 0);/*c375, 390*/ 10062 SOC_IF_ERROR_RETURN(WRITE_MMU_THDO_QOFFSET_CELLm(unit, 10063 MEM_BLOCK_ANY, j, &entry)); 10064 } 10065 10066 val = lossless ? opthd_total_shared_queue_eqe : 10067 mmu_egr_queue_dyn_thd_param_lossy; 10068 for (j = si->num_mmu_base_cosq; 10069 j < soc_mem_index_max(unit,MMU_THDO_QCONFIG_QENTRYm); j++) { 10070 /* Output port threshold EQEs*/ 10071 10072 SOC_IF_ERROR_RETURN(READ_MMU_THDO_QCONFIG_QENTRYm(unit, 10073 MEM_BLOCK_ANY, j, &entry)); 10074 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_QENTRYm, &entry, 10075 Q_MIN_QENTRYf, opthd_port_min_grntee_eqe);/*c397*/ 10076 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_QENTRYm, &entry, 10077 Q_SHARED_LIMIT_QENTRYf, val);/*c398*/ 10078 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_QENTRYm, &entry, 10079 Q_LIMIT_DYNAMIC_QENTRYf, lossless ? 0 : 1);/*c400*/ 10080 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_QENTRYm, &entry, 10081 Q_LIMIT_ENABLE_QENTRYf, lossless ? 0 : 1);/*c401*/ 10082 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_QENTRYm, &entry, 10083 Q_COLOR_ENABLE_QENTRYf, 0);/*c402*/ 10084 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_QENTRYm, &entry, 10085 Q_COLOR_LIMIT_DYNAMIC_QENTRYf, lossless ? 0 : 1);/*c403*/ 10086 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_QENTRYm, &entry, 10087 LIMIT_YELLOW_QENTRYf, lossless ? (val/8) : 0);/*c404*/ 10088 SOC_IF_ERROR_RETURN(WRITE_MMU_THDO_QCONFIG_QENTRYm(unit, 10089 MEM_BLOCK_ANY, j, &entry)); 10090 10091 SOC_IF_ERROR_RETURN(READ_MMU_THDO_QOFFSET_QENTRYm(unit, 10092 MEM_BLOCK_ANY, j, &entry)); 10093 soc_mem_field32_set(unit, MMU_THDO_QOFFSET_QENTRYm, &entry, 10094 RESET_OFFSET_QENTRYf, 1);/*c399*/ 10095 soc_mem_field32_set(unit, MMU_THDO_QOFFSET_QENTRYm, &entry, 10096 LIMIT_RED_QENTRYf, lossless ? (val/8) : 0);/*c405*/ 10097 soc_mem_field32_set(unit, MMU_THDO_QOFFSET_QENTRYm, &entry, 10098 RESET_OFFSET_YELLOW_QENTRYf, 1);/*c406*/ 10099 soc_mem_field32_set(unit, MMU_THDO_QOFFSET_QENTRYm, &entry, 10100 RESET_OFFSET_RED_QENTRYf, 1);/*c407*/ 10101 SOC_IF_ERROR_RETURN(WRITE_MMU_THDO_QOFFSET_QENTRYm(unit, 10102 MEM_BLOCK_ANY, j, &entry)); 10103 10104 } 10105 10106 return SOC_E_NONE; 10107 } 10108 10109 /********************************************************* 10110 * KATANA MMU HELPER --- END 10111 */ 10112 10113 STATIC int 10114 _soc_katana_mmu_init(int unit) 10115 { 10116 uint32 rval, nxtaddr; 10117 uint64 r64val; 10118 int port, mmu_init_usec, i; 10119 soc_timeout_t to; 10120 uint32 entry[SOC_MAX_MEM_WORDS]; 10121 mmu_aging_lmt_int_entry_t age_entry; 10122 int count, pg_num; 10123 uint16 dev_id; 10124 uint8 rev_id; 10125 soc_info_t *si; 10126 uint32 port_cfg0, port_cfg1; 10127 uint32 ext_mem_bw; 10128 lls_l2_xoff_entry_t lls_l2_xoff_state; 10129 int parity_enable; 10130 10131 soc_cm_get_id(unit, &dev_id, &rev_id); 10132 10133 si = &SOC_INFO(unit); 10134 10135 /* Init Link List Scheduler */ 10136 rval = 0; 10137 soc_reg_field_set(unit, LLS_SOFT_RESETr, &rval, SOFT_RESETf, 0); 10138 SOC_IF_ERROR_RETURN(WRITE_LLS_SOFT_RESETr(unit, rval)); 10139 10140 rval = 0; 10141 soc_reg_field_set(unit, LLS_INITr, &rval, INITf, 1); 10142 SOC_IF_ERROR_RETURN(WRITE_LLS_INITr(unit, rval)); 10143 10144 /* Wait for LLS init done. */ 10145 if (SAL_BOOT_SIMULATION) { 10146 mmu_init_usec = 10000000; /* Simulation .. 10sec */ 10147 } else { 10148 mmu_init_usec = 50000; 10149 } 10150 soc_timeout_init(&to, mmu_init_usec, 0); 10151 do { 10152 SOC_IF_ERROR_RETURN(READ_LLS_INITr(unit, &rval)); 10153 if (soc_reg_field_get(unit, LLS_INITr, rval, INIT_DONEf)) { 10154 break; 10155 } 10156 if (soc_timeout_check(&to)) { 10157 LOG_WARN(BSL_LS_SOC_COMMON, 10158 (BSL_META_U(unit, 10159 "unit %d : LLS INIT timeout\n"), unit)); 10160 break; 10161 } 10162 } while (TRUE); 10163 10164 /* Setup TDM for MMU Arb & LLS */ 10165 _soc_katana_mmu_tdm_init(unit); 10166 10167 /* Calculate raw BW and round down to the nearest gig */ 10168 ext_mem_bw = SOC_DDR3_CLOCK_MHZ(unit) * SOC_DDR3_NUM_MEMORIES(unit) * 2 * 16 / 1000 * 1000; 10169 /* Factor in refresh, bank collision, and turnaround. Also round down */ 10170 if (SOC_DDR3_NUM_MEMORIES(unit) == 1) { 10171 ext_mem_bw = (ext_mem_bw * 86 / 100) / 1000 * 1000; 10172 } else { 10173 ext_mem_bw = (ext_mem_bw * 88 / 100) / 1000 * 1000; 10174 } 10175 /* Calculate full duplex bandwidth for 492B packet (17 32B accesses) */ 10176 ext_mem_bw = ext_mem_bw * 8 / 17; 10177 /* Favor DRAM writes over DRAM reads */ 10178 ext_mem_bw = ext_mem_bw * 9 / 10; 10179 for(i=0; i<16; i++) { 10180 SOC_IF_ERROR_RETURN(READ_TOQ_EXT_MEM_BW_MAP_TABLEr(unit, i, &rval)); 10181 10182 soc_reg_field_set(unit, TOQ_EXT_MEM_BW_MAP_TABLEr, &rval, 10183 GBL_GUARENTEE_BW_LIMITf, ext_mem_bw / 20); 10184 soc_reg_field_set(unit, TOQ_EXT_MEM_BW_MAP_TABLEr, &rval, 10185 WR_PHASEf, 120); 10186 soc_reg_field_set(unit, TOQ_EXT_MEM_BW_MAP_TABLEr, &rval, 10187 RD_PHASEf, 120); 10188 SOC_IF_ERROR_RETURN( 10189 WRITE_TOQ_EXT_MEM_BW_MAP_TABLEr(unit,i,rval)); 10190 } 10191 SOC_IF_ERROR_RETURN(READ_TOQ_EXT_MEM_BW_TIMER_CFGr(unit, &rval)); 10192 soc_reg_field_set(unit, TOQ_EXT_MEM_BW_TIMER_CFGr, &rval, MIDPKT_SHAPE_ENABLEf,0); 10193 SOC_IF_ERROR_RETURN(WRITE_TOQ_EXT_MEM_BW_TIMER_CFGr(unit, rval)); 10194 10195 nxtaddr = 0; 10196 port_cfg0 = port_cfg1 = 0; 10197 10198 PBMP_ALL_ITER(unit, port) { 10199 /* Configure Egress Fifo */ 10200 rval = 0; 10201 soc_reg_field_set(unit, DEQ_EFIFO_CFGr, &rval, EGRESS_FIFO_START_ADDRESSf, 10202 nxtaddr); 10203 if (IS_EXT_MEM_PORT(unit, port)) { 10204 if (si->port_speed_max[port] >= 10000) { 10205 soc_reg_field_set(unit, DEQ_EFIFO_CFGr, &rval, EGRESS_FIFO_XMIT_THRESHOLDf, 35); 10206 soc_reg_field_set(unit, DEQ_EFIFO_CFGr, &rval, EGRESS_FIFO_DEPTHf, 60); 10207 nxtaddr += 60; 10208 } else if (si->port_speed_max[port] == 2500) { 10209 soc_reg_field_set(unit, DEQ_EFIFO_CFGr, &rval, EGRESS_FIFO_XMIT_THRESHOLDf, 20); 10210 soc_reg_field_set(unit, DEQ_EFIFO_CFGr, &rval, EGRESS_FIFO_DEPTHf, 28); 10211 nxtaddr += 28; 10212 } else { 10213 soc_reg_field_set(unit, DEQ_EFIFO_CFGr, &rval, EGRESS_FIFO_XMIT_THRESHOLDf, 8); 10214 soc_reg_field_set(unit, DEQ_EFIFO_CFGr, &rval, EGRESS_FIFO_DEPTHf, 11); 10215 nxtaddr += 11; 10216 } 10217 if (port <= 31) { 10218 port_cfg0 |= (1 << port); 10219 } else { 10220 port_cfg1 |= (1 << (port - 32)); 10221 } 10222 } else { 10223 soc_reg_field_set(unit, DEQ_EFIFO_CFGr, &rval, EGRESS_FIFO_XMIT_THRESHOLDf, 1); 10224 if ((dev_id == BCM56440_DEVICE_ID) || (dev_id == BCM56441_DEVICE_ID) || 10225 (dev_id == BCM56445_DEVICE_ID) || (dev_id == BCM56448_DEVICE_ID) || 10226 (dev_id == BCM56449_DEVICE_ID) || (dev_id == BCM55440_DEVICE_ID)) { /* 133MHz */ 10227 soc_reg_field_set(unit, DEQ_EFIFO_CFGr, &rval, EGRESS_FIFO_DEPTHf, 10228 (si->port_speed_max[port] >= 10000) ? 6 : 2); 10229 nxtaddr += ((si->port_speed_max[port] >= 10000) ? 6 : 2); 10230 } else { /* 90MHz */ 10231 soc_reg_field_set(unit, DEQ_EFIFO_CFGr, &rval, EGRESS_FIFO_DEPTHf, 10232 (si->port_speed_max[port] >= 10000) ? 9 : 3); 10233 nxtaddr += ((si->port_speed_max[port] >= 10000) ? 9 : 3); 10234 } 10235 } 10236 SOC_IF_ERROR_RETURN(WRITE_DEQ_EFIFO_CFGr(unit, port, rval)); 10237 10238 SOC_IF_ERROR_RETURN(WRITE_DEST_PORT_CFG_0r(unit, port_cfg0)); 10239 SOC_IF_ERROR_RETURN(WRITE_DEST_PORT_CFG_1r(unit, port_cfg1)); 10240 10241 /* Port BW Ctrl */ 10242 SOC_IF_ERROR_RETURN(READ_TOQ_PORT_BW_CTRLr(unit, port, &rval)); 10243 if (IS_CPU_PORT(unit,port) || IS_LB_PORT(unit,port)) { 10244 if ((dev_id == BCM56443_DEVICE_ID) ||(dev_id == BCM56241_DEVICE_ID)) { /* And all other 2.5G variants */ 10245 soc_reg_field_set(unit, TOQ_PORT_BW_CTRLr, &rval, PORT_BWf, 125); 10246 } else { 10247 soc_reg_field_set(unit, TOQ_PORT_BW_CTRLr, &rval, PORT_BWf, 50); 10248 } 10249 soc_reg_field_set(unit, TOQ_PORT_BW_CTRLr, &rval, START_THRESHOLDf, 127); 10250 } else if (si->port_speed_max[port] >= 10000) { 10251 soc_reg_field_set(unit, TOQ_PORT_BW_CTRLr, &rval, PORT_BWf, si->port_speed_max[port] / 20); 10252 soc_reg_field_set(unit, TOQ_PORT_BW_CTRLr, &rval, START_THRESHOLDf, 34); 10253 } else if (si->port_speed_max[port] == 2500) { 10254 soc_reg_field_set(unit, TOQ_PORT_BW_CTRLr, &rval, PORT_BWf, 125); 10255 soc_reg_field_set(unit, TOQ_PORT_BW_CTRLr, &rval, START_THRESHOLDf, 19); 10256 } else { 10257 soc_reg_field_set(unit, TOQ_PORT_BW_CTRLr, &rval, PORT_BWf, 50); 10258 soc_reg_field_set(unit, TOQ_PORT_BW_CTRLr, &rval, START_THRESHOLDf, 7); 10259 } 10260 SOC_IF_ERROR_RETURN(WRITE_TOQ_PORT_BW_CTRLr(unit, port, rval)); 10261 } 10262 rval = 0; 10263 soc_reg_field_set(unit, DEQ_EFIFO_CFG_COMPLETEr, &rval, EGRESS_FIFO_CONFIGURATION_COMPLETEf, 1); 10264 SOC_IF_ERROR_RETURN(WRITE_DEQ_EFIFO_CFG_COMPLETEr(unit, rval)); 10265 10266 /* Enable LLS */ 10267 rval = 0; 10268 soc_reg_field_set(unit, LLS_CONFIG0r, &rval, DEQUEUE_ENABLEf, 1); 10269 soc_reg_field_set(unit, LLS_CONFIG0r, &rval, ENQUEUE_ENABLEf, 1); 10270 soc_reg_field_set(unit, LLS_CONFIG0r, &rval, FC_ENABLEf, 1); 10271 soc_reg_field_set(unit, LLS_CONFIG0r, &rval, MIN_ENABLEf, 1); 10272 soc_reg_field_set(unit, LLS_CONFIG0r, &rval, PORT_SCHEDULER_ENABLEf, 1); 10273 soc_reg_field_set(unit, LLS_CONFIG0r, &rval, SHAPER_ENABLEf, 1); 10274 if (SOC_REG_FIELD_VALID(unit, LLS_CONFIG0r, SPRI_VECT_MODE_ENABLEf)) { 10275 if (soc_feature(unit, soc_feature_vector_based_spri)) { 10276 soc_reg_field_set(unit, LLS_CONFIG0r, &rval, 10277 SPRI_VECT_MODE_ENABLEf, 1); 10278 } 10279 } 10280 SOC_IF_ERROR_RETURN(WRITE_LLS_CONFIG0r(unit, rval)); 10281 10282 /* Enable shaper background refresh */ 10283 rval = 0; 10284 soc_reg_field_set(unit, LLS_MAX_REFRESH_ENABLEr, &rval, L0_MAX_REFRESH_ENABLEf, 1); 10285 soc_reg_field_set(unit, LLS_MAX_REFRESH_ENABLEr, &rval, L1_MAX_REFRESH_ENABLEf, 1); 10286 soc_reg_field_set(unit, LLS_MAX_REFRESH_ENABLEr, &rval, L2_MAX_REFRESH_ENABLEf, 1); 10287 soc_reg_field_set(unit, LLS_MAX_REFRESH_ENABLEr, &rval, PORT_MAX_REFRESH_ENABLEf, 1); 10288 SOC_IF_ERROR_RETURN(WRITE_LLS_MAX_REFRESH_ENABLEr(unit, rval)); 10289 10290 rval = 0; 10291 soc_reg_field_set(unit, LLS_MIN_REFRESH_ENABLEr, &rval, L0_MIN_REFRESH_ENABLEf, 1); 10292 soc_reg_field_set(unit, LLS_MIN_REFRESH_ENABLEr, &rval, L1_MIN_REFRESH_ENABLEf, 1); 10293 soc_reg_field_set(unit, LLS_MIN_REFRESH_ENABLEr, &rval, L2_MIN_REFRESH_ENABLEf, 1); 10294 SOC_IF_ERROR_RETURN(WRITE_LLS_MIN_REFRESH_ENABLEr(unit, rval)); 10295 10296 SOC_IF_ERROR_RETURN(READ_LLS_MIN_CAP_CONFIGr(unit, &rval)); 10297 soc_reg_field_set(unit, LLS_MIN_CAP_CONFIGr, &rval, SPARE1f, 1); 10298 SOC_IF_ERROR_RETURN(WRITE_LLS_MIN_CAP_CONFIGr(unit, rval)); 10299 10300 /* 10301 * Disable per queue backpressure from CMIC and clear XOFF state. The 10302 * queue back pressure mechanism for Katana (and possibliy other devices) 10303 * causes the round robin scheduling mechanism to restart when the queues 10304 * are full. In this scenario, the programmed weights are not correctly 10305 * applied. The solution is to disable the hardwired backpressure 10306 * mechanism and let the queue credit backpressue scheme control things. 10307 */ 10308 10309 /* Step 1: Disable the hardwired queue backpressure mechanism */ 10310 SOC_IF_ERROR_RETURN(READ_LLS_FC_CONFIGr(unit, &rval)); 10311 /* Set the LLS_FC_CONFIGr - FC_DROP_DEQUEUEf=1 for 10312 * Katana B0 onwards 10313 */ 10314 if ((SOC_IS_KATANA(unit)) && (rev_id >= BCM56440_B0_REV_ID)) { 10315 soc_reg_field_set(unit, LLS_FC_CONFIGr, &rval, FC_DROP_DEQUEUEf, 1); 10316 } 10317 soc_reg_field_set(unit, LLS_FC_CONFIGr, &rval, FC_CFG_DISABLE_L2_COSMASK_XOFFf, 1); 10318 SOC_IF_ERROR_RETURN(WRITE_LLS_FC_CONFIGr(unit, rval)); 10319 10320 /* Step 2: Clear the XOFF State */ 10321 sal_memset(&lls_l2_xoff_state, 0, sizeof(lls_l2_xoff_entry_t)); 10322 SOC_IF_ERROR_RETURN(WRITE_LLS_L2_XOFFm(unit, MEM_BLOCK_ALL, 0, &lls_l2_xoff_state)); 10323 10324 /* Configure the FAP sizes */ 10325 #define RQE_WQE_HEADROOM 64 10326 #define RQE_WQE_OFFSET 64 10327 #define CFAPI_HEADROOM 64 10328 #define CFAPI_OFFSET 64 10329 #define CFAPE_HEADROOM 1535 10330 #define CFAPE_OFFSET 96 10331 #define QENTRY_HEADROOM 8 10332 #define QENTRY_OFFSET 64 10333 10334 /* Configure the RQE Work Queue Entry FAP */ 10335 SOC_IF_ERROR_RETURN(READ_MMU_ENQ_FAPCONFIG_0r(unit, &rval)); 10336 count = soc_reg_field_get(unit, MMU_ENQ_FAPCONFIG_0r, rval, FAPPOOLSIZEf); 10337 count -= RQE_WQE_HEADROOM; 10338 rval = 0; 10339 soc_reg_field_set(unit, MMU_ENQ_FAPFULLSETPOINT_0r, &rval, FAPFULLSETPOINTf, count); 10340 SOC_IF_ERROR_RETURN(WRITE_MMU_ENQ_FAPFULLSETPOINT_0r(unit, rval)); 10341 count -= RQE_WQE_OFFSET; 10342 rval = 0; 10343 soc_reg_field_set(unit, MMU_ENQ_FAPFULLRESETPOINT_0r, &rval, FAPFULLRESETPOINTf, count); 10344 SOC_IF_ERROR_RETURN(WRITE_MMU_ENQ_FAPFULLRESETPOINT_0r(unit, rval)); 10345 10346 /* Configure the internal cell FAP */ 10347 SOC_IF_ERROR_RETURN(READ_CFAPIOTPCONFIGr(unit, &rval)); 10348 count = soc_reg_field_get(unit, CFAPIOTPCONFIGr, rval, MAXFULLSETf); 10349 rval = 0; 10350 soc_reg_field_set(unit, CFAPICONFIGr, &rval, CFAPIPOOLSIZEf, count); 10351 SOC_IF_ERROR_RETURN(WRITE_CFAPICONFIGr(unit, rval)); 10352 count -= CFAPI_HEADROOM; 10353 rval = 0; 10354 soc_reg_field_set(unit, CFAPIFULLSETPOINTr, &rval, CFAPIFULLSETPOINTf, count); 10355 SOC_IF_ERROR_RETURN(WRITE_CFAPIFULLSETPOINTr(unit, rval)); 10356 count -= CFAPI_OFFSET; 10357 rval = 0; 10358 soc_reg_field_set(unit, CFAPIFULLRESETPOINTr, &rval, CFAPIFULLRESETPOINTf, count); 10359 SOC_IF_ERROR_RETURN(WRITE_CFAPIFULLRESETPOINTr(unit, rval)); 10360 10361 /* Configure the external cell FAP */ 10362 SOC_IF_ERROR_RETURN(READ_CFAPEOTPCONFIGr(unit, &rval)); 10363 count = soc_reg_field_get(unit, CFAPEOTPCONFIGr, rval, MAXFULLSETf); 10364 rval = 0; 10365 soc_reg_field_set(unit, CFAPECONFIGr, &rval, CFAPEPOOLSIZEf, count); 10366 SOC_IF_ERROR_RETURN(WRITE_CFAPECONFIGr(unit, rval)); 10367 count -= CFAPE_HEADROOM; 10368 rval = 0; 10369 soc_reg_field_set(unit, CFAPEFULLSETPOINTr, &rval, CFAPEFULLSETPOINTf, count); 10370 SOC_IF_ERROR_RETURN(WRITE_CFAPEFULLSETPOINTr(unit, rval)); 10371 count -= CFAPE_OFFSET; 10372 rval = 0; 10373 soc_reg_field_set(unit, CFAPEFULLRESETPOINTr, &rval, CFAPEFULLRESETPOINTf, count); 10374 SOC_IF_ERROR_RETURN(WRITE_CFAPEFULLRESETPOINTr(unit, rval)); 10375 10376 /* Configure the Qentry FAPs */ 10377 SOC_IF_ERROR_RETURN(READ_QSTRUCT_FAPOTPCONFIG_0r(unit, &rval)); 10378 count = soc_reg_field_get(unit, QSTRUCT_FAPOTPCONFIG_0r, rval, MAXFULLSETf); 10379 rval = 0; 10380 soc_reg_field_set(unit, QSTRUCT_FAPCONFIG_0r, &rval, FAPPOOLSIZEf, 4 * count); 10381 SOC_IF_ERROR_RETURN(WRITE_QSTRUCT_FAPCONFIG_0r(unit, rval)); 10382 count -= QENTRY_HEADROOM; 10383 rval = 0; 10384 soc_reg_field_set(unit, QSTRUCT_FAPFULLSETPOINT_0r, &rval, FAPFULLSETPOINTf, count); 10385 SOC_IF_ERROR_RETURN(WRITE_QSTRUCT_FAPFULLSETPOINT_0r(unit, rval)); 10386 count -= QENTRY_OFFSET; 10387 rval = 0; 10388 soc_reg_field_set(unit, QSTRUCT_FAPFULLRESETPOINT_0r, &rval, FAPFULLRESETPOINTf, count); 10389 SOC_IF_ERROR_RETURN(WRITE_QSTRUCT_FAPFULLRESETPOINT_0r(unit, rval)); 10390 10391 SOC_IF_ERROR_RETURN(READ_QSTRUCT_FAPOTPCONFIG_1r(unit, &rval)); 10392 count = soc_reg_field_get(unit, QSTRUCT_FAPOTPCONFIG_1r, rval, MAXFULLSETf); 10393 rval = 0; 10394 soc_reg_field_set(unit, QSTRUCT_FAPCONFIG_1r, &rval, FAPPOOLSIZEf, 4 * count); 10395 SOC_IF_ERROR_RETURN(WRITE_QSTRUCT_FAPCONFIG_1r(unit, rval)); 10396 count -= QENTRY_HEADROOM; 10397 rval = 0; 10398 soc_reg_field_set(unit, QSTRUCT_FAPFULLSETPOINT_1r, &rval, FAPFULLSETPOINTf, count); 10399 SOC_IF_ERROR_RETURN(WRITE_QSTRUCT_FAPFULLSETPOINT_1r(unit, rval)); 10400 count -= QENTRY_OFFSET; 10401 rval = 0; 10402 soc_reg_field_set(unit, QSTRUCT_FAPFULLRESETPOINT_1r, &rval, FAPFULLRESETPOINTf, count); 10403 SOC_IF_ERROR_RETURN(WRITE_QSTRUCT_FAPFULLRESETPOINT_1r(unit, rval)); 10404 10405 SOC_IF_ERROR_RETURN(READ_QSTRUCT_FAPOTPCONFIG_2r(unit, &rval)); 10406 count = soc_reg_field_get(unit, QSTRUCT_FAPOTPCONFIG_2r, rval, MAXFULLSETf); 10407 rval = 0; 10408 soc_reg_field_set(unit, QSTRUCT_FAPCONFIG_2r, &rval, FAPPOOLSIZEf, 4 * count); 10409 SOC_IF_ERROR_RETURN(WRITE_QSTRUCT_FAPCONFIG_2r(unit, rval)); 10410 count -= QENTRY_HEADROOM; 10411 rval = 0; 10412 soc_reg_field_set(unit, QSTRUCT_FAPFULLSETPOINT_2r, &rval, FAPFULLSETPOINTf, count); 10413 SOC_IF_ERROR_RETURN(WRITE_QSTRUCT_FAPFULLSETPOINT_2r(unit, rval)); 10414 count -= QENTRY_OFFSET; 10415 rval = 0; 10416 soc_reg_field_set(unit, QSTRUCT_FAPFULLRESETPOINT_2r, &rval, FAPFULLRESETPOINTf, count); 10417 SOC_IF_ERROR_RETURN(WRITE_QSTRUCT_FAPFULLRESETPOINT_2r(unit, rval)); 10418 10419 SOC_IF_ERROR_RETURN(READ_QSTRUCT_FAPOTPCONFIG_3r(unit, &rval)); 10420 count = soc_reg_field_get(unit, QSTRUCT_FAPOTPCONFIG_3r, rval, MAXFULLSETf); 10421 rval = 0; 10422 soc_reg_field_set(unit, QSTRUCT_FAPCONFIG_3r, &rval, FAPPOOLSIZEf, 4 * count); 10423 SOC_IF_ERROR_RETURN(WRITE_QSTRUCT_FAPCONFIG_3r(unit, rval)); 10424 count -= QENTRY_HEADROOM; 10425 rval = 0; 10426 soc_reg_field_set(unit, QSTRUCT_FAPFULLSETPOINT_3r, &rval, FAPFULLSETPOINTf, count); 10427 SOC_IF_ERROR_RETURN(WRITE_QSTRUCT_FAPFULLSETPOINT_3r(unit, rval)); 10428 count -= QENTRY_OFFSET; 10429 rval = 0; 10430 soc_reg_field_set(unit, QSTRUCT_FAPFULLRESETPOINT_3r, &rval, FAPFULLRESETPOINTf, count); 10431 SOC_IF_ERROR_RETURN(WRITE_QSTRUCT_FAPFULLRESETPOINT_3r(unit, rval)); 10432 10433 /* Initialize the FAPs */ 10434 rval = 0; 10435 soc_reg_field_set(unit, CFAPIINITr, &rval, START_CFAPI_INITf, 1); 10436 SOC_IF_ERROR_RETURN(WRITE_CFAPIINITr(unit, rval)); 10437 rval = 0; 10438 soc_reg_field_set(unit, CFAPEINITr, &rval, START_CFAPE_INITf, 1); 10439 SOC_IF_ERROR_RETURN(WRITE_CFAPEINITr(unit, rval)); 10440 rval = 0; 10441 soc_reg_field_set(unit, QSTRUCT_FAPINIT_0r, &rval, START_FAP_INITf, 1); 10442 SOC_IF_ERROR_RETURN(WRITE_QSTRUCT_FAPINIT_0r(unit, rval)); 10443 rval = 0; 10444 soc_reg_field_set(unit, QSTRUCT_FAPINIT_1r, &rval, START_FAP_INITf, 1); 10445 SOC_IF_ERROR_RETURN(WRITE_QSTRUCT_FAPINIT_1r(unit, rval)); 10446 rval = 0; 10447 soc_reg_field_set(unit, QSTRUCT_FAPINIT_2r, &rval, START_FAP_INITf, 1); 10448 SOC_IF_ERROR_RETURN(WRITE_QSTRUCT_FAPINIT_2r(unit, rval)); 10449 rval = 0; 10450 soc_reg_field_set(unit, QSTRUCT_FAPINIT_3r, &rval, START_FAP_INITf, 1); 10451 SOC_IF_ERROR_RETURN(WRITE_QSTRUCT_FAPINIT_3r(unit, rval)); 10452 10453 sal_usleep(10000); 10454 10455 rval = 0; 10456 SOC_IF_ERROR_RETURN(WRITE_CFAPIINITr(unit, rval)); 10457 SOC_IF_ERROR_RETURN(WRITE_CFAPEINITr(unit, rval)); 10458 SOC_IF_ERROR_RETURN(WRITE_QSTRUCT_FAPINIT_0r(unit, rval)); 10459 SOC_IF_ERROR_RETURN(WRITE_QSTRUCT_FAPINIT_1r(unit, rval)); 10460 SOC_IF_ERROR_RETURN(WRITE_QSTRUCT_FAPINIT_2r(unit, rval)); 10461 SOC_IF_ERROR_RETURN(WRITE_QSTRUCT_FAPINIT_3r(unit, rval)); 10462 10463 /* Enable all ports */ 10464 COMPILER_64_ZERO(r64val); 10465 soc_reg64_field32_set(unit, INPUT_PORT_RX_ENABLE0_64r, &r64val, 10466 INPUT_PORT_RX_ENABLE_LOf, 0xffffffff); 10467 soc_reg64_field32_set(unit, INPUT_PORT_RX_ENABLE0_64r, &r64val, 10468 INPUT_PORT_RX_ENABLE_HIf, 0x1f); /* ports 0..36 */ 10469 SOC_IF_ERROR_RETURN(WRITE_INPUT_PORT_RX_ENABLE0_64r(unit, r64val)); 10470 SOC_IF_ERROR_RETURN(WRITE_THDIEMA_INPUT_PORT_RX_ENABLE0_64r(unit, r64val)); 10471 SOC_IF_ERROR_RETURN(WRITE_THDIEXT_INPUT_PORT_RX_ENABLE0_64r(unit, r64val)); 10472 SOC_IF_ERROR_RETURN(WRITE_THDIQEN_INPUT_PORT_RX_ENABLE0_64r(unit, r64val)); 10473 SOC_IF_ERROR_RETURN(WRITE_THDIRQE_INPUT_PORT_RX_ENABLE0_64r(unit, r64val)); 10474 10475 COMPILER_64_ZERO(r64val); 10476 soc_reg64_field32_set(unit, INPUT_PORT_RX_ENABLE1_64r, &r64val, 10477 INPUT_PORT_RX_ENABLE_LOf, 0xffffffff); 10478 soc_reg64_field32_set(unit, INPUT_PORT_RX_ENABLE1_64r, &r64val, 10479 INPUT_PORT_RX_ENABLE_HIf, 0x1); /* ports 37..69 */ 10480 SOC_IF_ERROR_RETURN(WRITE_INPUT_PORT_RX_ENABLE1_64r(unit, r64val)); 10481 SOC_IF_ERROR_RETURN(WRITE_THDIEMA_INPUT_PORT_RX_ENABLE1_64r(unit, r64val)); 10482 SOC_IF_ERROR_RETURN(WRITE_THDIEXT_INPUT_PORT_RX_ENABLE1_64r(unit, r64val)); 10483 SOC_IF_ERROR_RETURN(WRITE_THDIQEN_INPUT_PORT_RX_ENABLE1_64r(unit, r64val)); 10484 SOC_IF_ERROR_RETURN(WRITE_THDIRQE_INPUT_PORT_RX_ENABLE1_64r(unit, r64val)); 10485 10486 SOC_IF_ERROR_RETURN(WRITE_THDI_BYPASSr(unit, 0)); 10487 SOC_IF_ERROR_RETURN(WRITE_THDIQEN_THDI_BYPASSr(unit, 0)); 10488 SOC_IF_ERROR_RETURN(WRITE_THDIRQE_THDI_BYPASSr(unit, 0)); 10489 SOC_IF_ERROR_RETURN(WRITE_THDIEXT_THDI_BYPASSr(unit, 0)); 10490 SOC_IF_ERROR_RETURN(WRITE_THDIEMA_THDI_BYPASSr(unit, 0)); 10491 SOC_IF_ERROR_RETURN(WRITE_THDO_BYPASSr(unit, 0)); 10492 10493 if (soc_feature(unit, soc_feature_ddr3)) { 10494 /* Configure EMC */ 10495 SOC_IF_ERROR_RETURN(READ_EMC_CFGr(unit, &rval)); 10496 soc_reg_field_set(unit, EMC_CFGr, &rval, NUM_CISf, SOC_DDR3_NUM_MEMORIES(unit)); 10497 soc_reg_field_set(unit, EMC_CFGr, &rval, DRAM_SIZEf, SOC_DDR3_NUM_ROWS(unit) / 8192 - 1); 10498 SOC_IF_ERROR_RETURN(WRITE_EMC_CFGr(unit, rval)); 10499 10500 SOC_IF_ERROR_RETURN(READ_EMC_FREE_POOL_SIZESr(unit, &rval)); 10501 soc_reg_field_set(unit, EMC_FREE_POOL_SIZESr, &rval, WTFP_SIZEf, 240); 10502 soc_reg_field_set(unit, EMC_FREE_POOL_SIZESr, &rval, RSFP_SIZEf, 10503 SOC_DDR3_NUM_MEMORIES(unit) == 1 ? 64 : 128); 10504 SOC_IF_ERROR_RETURN(WRITE_EMC_FREE_POOL_SIZESr(unit, rval)); 10505 10506 SOC_IF_ERROR_RETURN(READ_EMC_IWRB_SIZEr(unit, &rval)); 10507 soc_reg_field_set(unit, EMC_IWRB_SIZEr, &rval, IWRB_SIZEf, 0); 10508 SOC_IF_ERROR_RETURN(WRITE_EMC_IWRB_SIZEr(unit, rval)); 10509 10510 SOC_IF_ERROR_RETURN(READ_EMC_IRRB_THRESHOLDSr(unit, &rval)); 10511 soc_reg_field_set(unit, EMC_IRRB_THRESHOLDSr, &rval, ALL_Q_XOFF_THRESHOLDf, 112); 10512 soc_reg_field_set(unit, EMC_IRRB_THRESHOLDSr, &rval, ALL_UNDERRUN_Q_XON_THRESHOLDf, 112); 10513 soc_reg_field_set(unit, EMC_IRRB_THRESHOLDSr, &rval, ALL_Q_XON_THRESHOLDf, 78); 10514 SOC_IF_ERROR_RETURN(WRITE_EMC_IRRB_THRESHOLDSr(unit, rval)); 10515 } 10516 10517 PBMP_ALL_ITER(unit, port) { 10518 pg_num = (port >= 25 && port <= 28) ? 7 : 0; 10519 10520 /* Ports 27,32,33,34 are ports in one MXQ block. 10521 * If more than 2 lanes are enabled then pg_num = 0. 10522 * Same with ports 28,29,30,31. 10523 */ 10524 if ((port == 27) && (SOC_PORT_VALID(unit, 32) || 10525 SOC_PORT_VALID(unit, 33) || SOC_PORT_VALID(unit, 34))) { 10526 pg_num = 0; 10527 } else if ((port == 28) && (SOC_PORT_VALID(unit, 29) || 10528 SOC_PORT_VALID(unit, 30) || SOC_PORT_VALID(unit, 31))) { 10529 pg_num = 0; 10530 } 10531 10532 rval = 0; 10533 soc_reg_field_set(unit, PORT_MAX_PKT_SIZEr, &rval, PORT_MAX_PKT_SIZEf,49); 10534 SOC_IF_ERROR_RETURN(WRITE_PORT_MAX_PKT_SIZEr(unit, port, rval)); 10535 SOC_IF_ERROR_RETURN(WRITE_THDIEXT_PORT_MAX_PKT_SIZEr(unit, port, rval)); 10536 SOC_IF_ERROR_RETURN(WRITE_THDIEMA_PORT_MAX_PKT_SIZEr(unit, port, rval)); 10537 SOC_IF_ERROR_RETURN(WRITE_THDIRQE_PORT_MAX_PKT_SIZEr(unit, port, rval)); 10538 SOC_IF_ERROR_RETURN(WRITE_THDIQEN_PORT_MAX_PKT_SIZEr(unit, port, rval)); 10539 10540 rval = 0; 10541 SOC_IF_ERROR_RETURN(WRITE_THDIEXT_PORT_MIN_CELLr(unit, port, rval)); 10542 SOC_IF_ERROR_RETURN(WRITE_THDIEMA_PORT_MIN_CELLr(unit, port, rval)); 10543 SOC_IF_ERROR_RETURN(WRITE_PORT_MIN_CELLr(unit, port, rval)); 10544 SOC_IF_ERROR_RETURN(WRITE_THDIRQE_PORT_MIN_CELLr(unit, port, rval)); 10545 SOC_IF_ERROR_RETURN(WRITE_THDIQEN_PORT_MIN_CELLr(unit, port, rval)); 10546 10547 rval = 0; 10548 SOC_IF_ERROR_RETURN(WRITE_THDIEXT_PORT_MAX_SHARED_CELLr(unit, port, rval)); 10549 SOC_IF_ERROR_RETURN(WRITE_THDIEMA_PORT_MAX_SHARED_CELLr(unit, port, rval)); 10550 soc_reg_field_set(unit, PORT_MAX_SHARED_CELLr, &rval, PORT_MAXf,5226); 10551 SOC_IF_ERROR_RETURN(WRITE_PORT_MAX_SHARED_CELLr(unit, port, rval)); 10552 soc_reg_field_set(unit, PORT_MAX_SHARED_CELLr, &rval, PORT_MAXf,3300); 10553 SOC_IF_ERROR_RETURN(WRITE_THDIRQE_PORT_MAX_SHARED_CELLr(unit, port, rval)); 10554 soc_reg_field_set(unit, PORT_MAX_SHARED_CELLr, &rval, PORT_MAXf,129628); 10555 SOC_IF_ERROR_RETURN(WRITE_THDIQEN_PORT_MAX_SHARED_CELLr(unit, port, rval)); 10556 10557 rval = 0; 10558 SOC_IF_ERROR_RETURN(WRITE_THDIEXT_PORT_RESUME_LIMIT_CELLr(unit, port, rval)); 10559 SOC_IF_ERROR_RETURN(WRITE_THDIEMA_PORT_RESUME_LIMIT_CELLr(unit, port, rval)); 10560 soc_reg_field_set(unit, PORT_RESUME_LIMIT_CELLr, &rval, CELLSf,5208); 10561 SOC_IF_ERROR_RETURN(WRITE_PORT_RESUME_LIMIT_CELLr(unit, port, rval)); 10562 soc_reg_field_set(unit, PORT_RESUME_LIMIT_CELLr, &rval, CELLSf,3298); 10563 SOC_IF_ERROR_RETURN(WRITE_THDIRQE_PORT_RESUME_LIMIT_CELLr(unit, port, rval)); 10564 soc_reg_field_set(unit, PORT_RESUME_LIMIT_CELLr, &rval, CELLSf,129574); 10565 SOC_IF_ERROR_RETURN(WRITE_THDIQEN_PORT_RESUME_LIMIT_CELLr(unit, port, rval)); 10566 10567 rval = 0; 10568 SOC_IF_ERROR_RETURN(WRITE_THDIEXT_PORT_PRI_XON_ENABLEr(unit, port, rval)); 10569 SOC_IF_ERROR_RETURN(WRITE_THDIEXT_PORT_PRI_XON_ENABLEr(unit, port, rval)); 10570 SOC_IF_ERROR_RETURN(WRITE_THDIEMA_PORT_PRI_XON_ENABLEr(unit, port, rval)); 10571 SOC_IF_ERROR_RETURN(WRITE_THDIRQE_PORT_PRI_XON_ENABLEr(unit, port, rval)); 10572 SOC_IF_ERROR_RETURN(WRITE_THDIQEN_PORT_PRI_XON_ENABLEr(unit, port, rval)); 10573 10574 rval = 0; 10575 soc_reg_field_set(unit, PORT_SHARED_MAX_PG_ENABLEr, &rval, PG_BMPf,0xff); 10576 SOC_IF_ERROR_RETURN(WRITE_PORT_SHARED_MAX_PG_ENABLEr(unit, port, rval)); 10577 SOC_IF_ERROR_RETURN(WRITE_THDIEXT_PORT_SHARED_MAX_PG_ENABLEr(unit, port, rval)); 10578 SOC_IF_ERROR_RETURN(WRITE_THDIEMA_PORT_SHARED_MAX_PG_ENABLEr(unit, port, rval)); 10579 SOC_IF_ERROR_RETURN(WRITE_THDIRQE_PORT_SHARED_MAX_PG_ENABLEr(unit, port, rval)); 10580 SOC_IF_ERROR_RETURN(WRITE_THDIQEN_PORT_SHARED_MAX_PG_ENABLEr(unit, port, rval)); 10581 10582 rval = 0; 10583 soc_reg_field_set(unit, PORT_MIN_PG_ENABLEr, &rval, PG_BMPf,0xff); 10584 SOC_IF_ERROR_RETURN(WRITE_PORT_MIN_PG_ENABLEr(unit, port, rval)); 10585 SOC_IF_ERROR_RETURN(WRITE_THDIEXT_PORT_MIN_PG_ENABLEr(unit, port, rval)); 10586 SOC_IF_ERROR_RETURN(WRITE_THDIEMA_PORT_MIN_PG_ENABLEr(unit, port, rval)); 10587 SOC_IF_ERROR_RETURN(WRITE_THDIRQE_PORT_MIN_PG_ENABLEr(unit, port, rval)); 10588 SOC_IF_ERROR_RETURN(WRITE_THDIQEN_PORT_MIN_PG_ENABLEr(unit, port, rval)); 10589 10590 rval = 0; 10591 SOC_IF_ERROR_RETURN(WRITE_THDIEXT_PG_MIN_CELLr(unit, port, pg_num, rval)); 10592 SOC_IF_ERROR_RETURN(WRITE_THDIEMA_PG_MIN_CELLr(unit, port, pg_num, rval)); 10593 soc_reg_field_set(unit, PG_MIN_CELLr, &rval, PG_MINf, 0x31); 10594 SOC_IF_ERROR_RETURN(WRITE_PG_MIN_CELLr(unit, port, pg_num, rval)); 10595 SOC_IF_ERROR_RETURN(WRITE_THDIRQE_PG_MIN_CELLr(unit, port, pg_num, rval)); 10596 SOC_IF_ERROR_RETURN(WRITE_THDIQEN_PG_MIN_CELLr(unit, port, pg_num, rval)); 10597 10598 rval = 0; 10599 soc_reg_field_set(unit, PG_SHARED_LIMIT_CELLr, &rval, PG_SHARED_DYNAMICf, 1); 10600 SOC_IF_ERROR_RETURN(WRITE_THDIEXT_PG_SHARED_LIMIT_CELLr(unit, port, pg_num, rval)); 10601 SOC_IF_ERROR_RETURN(WRITE_THDIEMA_PG_SHARED_LIMIT_CELLr(unit, port, pg_num, rval)); 10602 soc_reg_field_set(unit, PG_SHARED_LIMIT_CELLr, &rval, PG_SHARED_LIMITf, 7); 10603 SOC_IF_ERROR_RETURN(WRITE_PG_SHARED_LIMIT_CELLr(unit, port, pg_num, rval)); 10604 SOC_IF_ERROR_RETURN(WRITE_THDIRQE_PG_SHARED_LIMIT_CELLr(unit, port, pg_num, rval)); 10605 SOC_IF_ERROR_RETURN(WRITE_THDIQEN_PG_SHARED_LIMIT_CELLr(unit, port, pg_num, rval)); 10606 10607 rval = 0; 10608 soc_reg_field_set(unit, PG_HDRM_LIMIT_CELLr, &rval, PG_GEf, 1); 10609 SOC_IF_ERROR_RETURN(WRITE_THDIEXT_PG_HDRM_LIMIT_CELLr(unit, port, pg_num, rval)); 10610 SOC_IF_ERROR_RETURN(WRITE_THDIEMA_PG_HDRM_LIMIT_CELLr(unit, port, pg_num, rval)); 10611 soc_reg_field_set(unit, PG_HDRM_LIMIT_CELLr, &rval, PG_HDRM_LIMITf, 127); 10612 SOC_IF_ERROR_RETURN(WRITE_PG_HDRM_LIMIT_CELLr(unit, port, pg_num, rval)); 10613 soc_reg_field_set(unit, PG_HDRM_LIMIT_CELLr, &rval, PG_HDRM_LIMITf, 114); 10614 soc_reg_field_set(unit, PG_HDRM_LIMIT_CELLr, &rval, PG_GEf, 0); 10615 SOC_IF_ERROR_RETURN(WRITE_THDIRQE_PG_HDRM_LIMIT_CELLr(unit, port, pg_num, rval)); 10616 soc_reg_field_set(unit, PG_HDRM_LIMIT_CELLr, &rval, PG_HDRM_LIMITf, 3078); 10617 SOC_IF_ERROR_RETURN(WRITE_THDIQEN_PG_HDRM_LIMIT_CELLr(unit, port, pg_num, rval)); 10618 10619 rval = 0; 10620 SOC_IF_ERROR_RETURN(WRITE_THDIEXT_PG_RESET_OFFSET_CELLr(unit, port, pg_num, rval)); 10621 SOC_IF_ERROR_RETURN(WRITE_THDIEMA_PG_RESET_OFFSET_CELLr(unit, port, pg_num, rval)); 10622 soc_reg_field_set(unit, PG_RESET_OFFSET_CELLr, &rval, PG_RESET_OFFSETf, 18); 10623 SOC_IF_ERROR_RETURN(WRITE_PG_RESET_OFFSET_CELLr(unit, port, pg_num, rval)); 10624 soc_reg_field_set(unit, PG_RESET_OFFSET_CELLr, &rval, PG_RESET_OFFSETf, 2); 10625 SOC_IF_ERROR_RETURN(WRITE_THDIRQE_PG_RESET_OFFSET_CELLr(unit, port, pg_num, rval)); 10626 soc_reg_field_set(unit, PG_RESET_OFFSET_CELLr, &rval, PG_RESET_OFFSETf, 54); 10627 SOC_IF_ERROR_RETURN(WRITE_THDIQEN_PG_RESET_OFFSET_CELLr(unit, port, pg_num, rval)); 10628 10629 rval = 0; 10630 SOC_IF_ERROR_RETURN(WRITE_THDIEXT_PG_RESET_FLOOR_CELLr(unit, port, pg_num, rval)); 10631 SOC_IF_ERROR_RETURN(WRITE_THDIEMA_PG_RESET_FLOOR_CELLr(unit, port, pg_num, rval)); 10632 SOC_IF_ERROR_RETURN(WRITE_PG_RESET_FLOOR_CELLr(unit, port, pg_num, rval)); 10633 SOC_IF_ERROR_RETURN(WRITE_THDIRQE_PG_RESET_FLOOR_CELLr(unit, port, pg_num, rval)); 10634 SOC_IF_ERROR_RETURN(WRITE_THDIQEN_PG_RESET_FLOOR_CELLr(unit, port, pg_num, rval)); 10635 } 10636 10637 /* CPU Port */ 10638 rval = 0; 10639 SOC_IF_ERROR_RETURN(WRITE_THDIRQE_PG_HDRM_LIMIT_CELLr(unit, 0, 0, rval)); 10640 SOC_IF_ERROR_RETURN(WRITE_THDIQEN_PG_HDRM_LIMIT_CELLr(unit, 0, 0, rval)); 10641 soc_reg_field_set(unit, PG_HDRM_LIMIT_CELLr, &rval, PG_GEf, 1); 10642 SOC_IF_ERROR_RETURN(WRITE_PG_HDRM_LIMIT_CELLr(unit,0,0,rval)); 10643 SOC_IF_ERROR_RETURN(WRITE_THDIEXT_PG_HDRM_LIMIT_CELLr(unit, 0, 0, rval)); 10644 SOC_IF_ERROR_RETURN(WRITE_THDIEMA_PG_HDRM_LIMIT_CELLr(unit, 0, 0, rval)); 10645 10646 10647 /* MXQ Ports */ 10648 PBMP_MXQ_ITER(unit, port) { 10649 pg_num = (port >= 25 && port <= 28) ? 7 : 0; 10650 rval = (port >= 25 && port <= 28) ? 0xffffff : 0; /* PRIx_GRP = 0x7 */ 10651 10652 /* Ports 27,32,33,34 are ports in one MXQ block. 10653 * If more than 2 lanes are enabled then pg_num = 0. 10654 * Same with ports 28,29,30,31. 10655 */ 10656 if ((port == 27) && (SOC_PORT_VALID(unit, 32) || 10657 SOC_PORT_VALID(unit, 33) || SOC_PORT_VALID(unit, 34))) { 10658 pg_num = 0; 10659 rval = 0; 10660 } else if ((port == 28) && (SOC_PORT_VALID(unit, 29) || 10661 SOC_PORT_VALID(unit, 30) || SOC_PORT_VALID(unit, 31))) { 10662 pg_num = 0; 10663 rval = 0; 10664 } 10665 SOC_IF_ERROR_RETURN(WRITE_PORT_PRI_GRP0r(unit, port, rval)); 10666 SOC_IF_ERROR_RETURN(WRITE_PORT_PRI_GRP1r(unit, port, rval)); 10667 SOC_IF_ERROR_RETURN(WRITE_THDIEXT_PORT_PRI_GRP0r(unit, port, rval)); 10668 SOC_IF_ERROR_RETURN(WRITE_THDIEXT_PORT_PRI_GRP1r(unit, port, rval)); 10669 SOC_IF_ERROR_RETURN(WRITE_THDIEMA_PORT_PRI_GRP0r(unit, port, rval)); 10670 SOC_IF_ERROR_RETURN(WRITE_THDIEMA_PORT_PRI_GRP1r(unit, port, rval)); 10671 SOC_IF_ERROR_RETURN(WRITE_THDIRQE_PORT_PRI_GRP0r(unit, port, rval)); 10672 SOC_IF_ERROR_RETURN(WRITE_THDIRQE_PORT_PRI_GRP1r(unit, port, rval)); 10673 SOC_IF_ERROR_RETURN(WRITE_THDIQEN_PORT_PRI_GRP0r(unit, port, rval)); 10674 SOC_IF_ERROR_RETURN(WRITE_THDIQEN_PORT_PRI_GRP1r(unit, port, rval)); 10675 10676 switch (port) { 10677 case 25: 10678 SOC_IF_ERROR_RETURN(WRITE_MMU_ENQ_HIGIG_25_PRI_GRP0r(unit, rval)); 10679 SOC_IF_ERROR_RETURN(WRITE_MMU_ENQ_HIGIG_25_PRI_GRP1r(unit, rval)); 10680 break; 10681 case 26: 10682 SOC_IF_ERROR_RETURN(WRITE_MMU_ENQ_HIGIG_26_PRI_GRP0r(unit, rval)); 10683 SOC_IF_ERROR_RETURN(WRITE_MMU_ENQ_HIGIG_26_PRI_GRP1r(unit, rval)); 10684 break; 10685 case 27: 10686 SOC_IF_ERROR_RETURN(WRITE_MMU_ENQ_HIGIG_27_PRI_GRP0r(unit, rval)); 10687 SOC_IF_ERROR_RETURN(WRITE_MMU_ENQ_HIGIG_27_PRI_GRP1r(unit, rval)); 10688 break; 10689 case 28: 10690 SOC_IF_ERROR_RETURN(WRITE_MMU_ENQ_HIGIG_28_PRI_GRP0r(unit, rval)); 10691 SOC_IF_ERROR_RETURN(WRITE_MMU_ENQ_HIGIG_28_PRI_GRP1r(unit, rval)); 10692 break; 10693 default: 10694 break; 10695 } 10696 10697 rval = 0; 10698 soc_reg_field_set(unit, PG_SHARED_LIMIT_CELLr, &rval, PG_SHARED_DYNAMICf, 1); 10699 SOC_IF_ERROR_RETURN(WRITE_THDIEXT_PG_SHARED_LIMIT_CELLr(unit, port, pg_num, rval)); 10700 SOC_IF_ERROR_RETURN(WRITE_THDIEMA_PG_SHARED_LIMIT_CELLr(unit, port, pg_num, rval)); 10701 soc_reg_field_set(unit, PG_SHARED_LIMIT_CELLr, &rval, PG_SHARED_LIMITf, pg_num); 10702 SOC_IF_ERROR_RETURN(WRITE_PG_SHARED_LIMIT_CELLr(unit,port,pg_num,rval)); 10703 SOC_IF_ERROR_RETURN(WRITE_THDIRQE_PG_SHARED_LIMIT_CELLr(unit, port, pg_num, rval)); 10704 SOC_IF_ERROR_RETURN(WRITE_THDIQEN_PG_SHARED_LIMIT_CELLr(unit, port, pg_num, rval)); 10705 10706 rval = 0; 10707 soc_reg_field_set(unit, PG_HDRM_LIMIT_CELLr, &rval, PG_GEf, 1); 10708 SOC_IF_ERROR_RETURN(WRITE_THDIEXT_PG_HDRM_LIMIT_CELLr(unit, port, pg_num, rval)); 10709 SOC_IF_ERROR_RETURN(WRITE_THDIEMA_PG_HDRM_LIMIT_CELLr(unit, port, pg_num, rval)); 10710 soc_reg_field_set(unit, PG_HDRM_LIMIT_CELLr, &rval, PG_HDRM_LIMITf, 172); 10711 SOC_IF_ERROR_RETURN(WRITE_PG_HDRM_LIMIT_CELLr(unit,port,pg_num,rval)); 10712 soc_reg_field_set(unit, PG_HDRM_LIMIT_CELLr, &rval, PG_HDRM_LIMITf, 157); 10713 soc_reg_field_set(unit, PG_HDRM_LIMIT_CELLr, &rval, PG_GEf, 0); 10714 SOC_IF_ERROR_RETURN(WRITE_THDIRQE_PG_HDRM_LIMIT_CELLr(unit, port, pg_num, rval)); 10715 soc_reg_field_set(unit, PG_HDRM_LIMIT_CELLr, &rval, PG_HDRM_LIMITf, 4239); 10716 SOC_IF_ERROR_RETURN(WRITE_THDIQEN_PG_HDRM_LIMIT_CELLr(unit, port, pg_num, rval)); 10717 10718 rval = 0; 10719 SOC_IF_ERROR_RETURN(WRITE_THDIEXT_PG_RESET_OFFSET_CELLr(unit, port, pg_num, rval)); 10720 SOC_IF_ERROR_RETURN(WRITE_THDIEMA_PG_RESET_OFFSET_CELLr(unit, port, pg_num, rval)); 10721 soc_reg_field_set(unit, PG_RESET_OFFSET_CELLr, &rval, PG_RESET_OFFSETf, 18); 10722 SOC_IF_ERROR_RETURN(WRITE_PG_RESET_OFFSET_CELLr(unit,port,pg_num,rval)); 10723 soc_reg_field_set(unit, PG_RESET_OFFSET_CELLr, &rval, PG_RESET_OFFSETf, 2); 10724 SOC_IF_ERROR_RETURN(WRITE_THDIRQE_PG_RESET_OFFSET_CELLr(unit, port, pg_num, rval)); 10725 soc_reg_field_set(unit, PG_RESET_OFFSET_CELLr, &rval, PG_RESET_OFFSETf, 54); 10726 SOC_IF_ERROR_RETURN(WRITE_THDIQEN_PG_RESET_OFFSET_CELLr(unit, port, pg_num, rval)); 10727 10728 rval = 0; 10729 SOC_IF_ERROR_RETURN(WRITE_THDIEXT_PG_RESET_FLOOR_CELLr(unit, port, pg_num, rval)); 10730 SOC_IF_ERROR_RETURN(WRITE_THDIEMA_PG_RESET_FLOOR_CELLr(unit, port, pg_num, rval)); 10731 SOC_IF_ERROR_RETURN(WRITE_PG_RESET_FLOOR_CELLr(unit,port,pg_num,rval)); 10732 SOC_IF_ERROR_RETURN(WRITE_THDIRQE_PG_RESET_FLOOR_CELLr(unit, port, pg_num, rval)); 10733 SOC_IF_ERROR_RETURN(WRITE_THDIQEN_PG_RESET_FLOOR_CELLr(unit, port, pg_num, rval)); 10734 10735 rval = 0; 10736 SOC_IF_ERROR_RETURN(WRITE_THDIEXT_PG_MIN_CELLr(unit, port, pg_num, rval)); 10737 SOC_IF_ERROR_RETURN(WRITE_THDIEMA_PG_MIN_CELLr(unit, port, pg_num, rval)); 10738 soc_reg_field_set(unit, PG_MIN_CELLr, &rval, PG_MINf, 0x31); 10739 SOC_IF_ERROR_RETURN(WRITE_PG_MIN_CELLr(unit,port,pg_num,rval)); 10740 SOC_IF_ERROR_RETURN(WRITE_THDIRQE_PG_MIN_CELLr(unit, port, pg_num, rval)); 10741 SOC_IF_ERROR_RETURN(WRITE_THDIQEN_PG_MIN_CELLr(unit, port, pg_num, rval)); 10742 10743 } 10744 10745 /* Input port shared space */ 10746 /* rval = 0; 10747 soc_reg_field_set(unit, USE_SP_SHAREDr, &rval, ENABLEf, 1); 10748 SOC_IF_ERROR_RETURN(WRITE_USE_SP_SHAREDr(unit, rval)); 10749 */ 10750 rval = 0; 10751 SOC_IF_ERROR_RETURN(WRITE_THDIEXT_BUFFER_CELL_LIMIT_SPr(unit,0,rval)); 10752 SOC_IF_ERROR_RETURN(WRITE_THDIEMA_BUFFER_CELL_LIMIT_SPr(unit,0,rval)); 10753 soc_reg_field_set(unit, BUFFER_CELL_LIMIT_SPr, &rval, LIMITf, 5226); 10754 SOC_IF_ERROR_RETURN(WRITE_BUFFER_CELL_LIMIT_SPr(unit,0,rval)); 10755 soc_reg_field_set(unit, BUFFER_CELL_LIMIT_SPr, &rval, LIMITf, 3300); 10756 SOC_IF_ERROR_RETURN(WRITE_THDIRQE_BUFFER_CELL_LIMIT_SPr(unit,0,rval)); 10757 soc_reg_field_set(unit, BUFFER_CELL_LIMIT_SPr, &rval, LIMITf, 129628); 10758 SOC_IF_ERROR_RETURN(WRITE_THDIQEN_BUFFER_CELL_LIMIT_SPr(unit,0,rval)); 10759 10760 SOC_IF_ERROR_RETURN(WRITE_BUFFER_CELL_LIMIT_SP_SHAREDr(unit,0)); 10761 SOC_IF_ERROR_RETURN(WRITE_THDIEXT_BUFFER_CELL_LIMIT_SP_SHAREDr(unit,0)); 10762 SOC_IF_ERROR_RETURN(WRITE_THDIEMA_BUFFER_CELL_LIMIT_SP_SHAREDr(unit,0)); 10763 SOC_IF_ERROR_RETURN(WRITE_THDIRQE_BUFFER_CELL_LIMIT_SP_SHAREDr(unit,0)); 10764 SOC_IF_ERROR_RETURN(WRITE_THDIQEN_BUFFER_CELL_LIMIT_SP_SHAREDr(unit,0)); 10765 10766 rval = 0; 10767 SOC_IF_ERROR_RETURN(WRITE_THDIEXT_CELL_RESET_LIMIT_OFFSET_SPr(unit, 0, rval)); 10768 SOC_IF_ERROR_RETURN(WRITE_THDIEMA_CELL_RESET_LIMIT_OFFSET_SPr(unit, 0, rval)); 10769 soc_reg_field_set(unit, CELL_RESET_LIMIT_OFFSET_SPr, &rval, OFFSETf, 7); 10770 SOC_IF_ERROR_RETURN(WRITE_THDIRQE_CELL_RESET_LIMIT_OFFSET_SPr(unit, 0, rval)); 10771 soc_reg_field_set(unit, CELL_RESET_LIMIT_OFFSET_SPr, &rval, OFFSETf, 63); 10772 SOC_IF_ERROR_RETURN(WRITE_CELL_RESET_LIMIT_OFFSET_SPr(unit, 0, rval)); 10773 soc_reg_field_set(unit, CELL_RESET_LIMIT_OFFSET_SPr, &rval, OFFSETf, 189); 10774 SOC_IF_ERROR_RETURN(WRITE_THDIQEN_CELL_RESET_LIMIT_OFFSET_SPr(unit, 0, rval)); 10775 10776 /* Input port per-device global headroom */ 10777 rval = 0; 10778 SOC_IF_ERROR_RETURN(WRITE_THDIEXT_GLOBAL_HDRM_LIMITr(unit, rval)); 10779 SOC_IF_ERROR_RETURN(WRITE_THDIEMA_GLOBAL_HDRM_LIMITr(unit, rval)); 10780 soc_reg_field_set(unit, GLOBAL_HDRM_LIMITr, &rval, GLOBAL_HDRM_LIMITf, 107); 10781 SOC_IF_ERROR_RETURN(WRITE_GLOBAL_HDRM_LIMITr(unit, rval)); 10782 SOC_IF_ERROR_RETURN(WRITE_THDIRQE_GLOBAL_HDRM_LIMITr(unit, rval)); 10783 soc_reg_field_set(unit, GLOBAL_HDRM_LIMITr, &rval, GLOBAL_HDRM_LIMITf, 2889); 10784 SOC_IF_ERROR_RETURN(WRITE_THDIQEN_GLOBAL_HDRM_LIMITr(unit, rval)); 10785 10786 parity_enable = soc_property_get(unit, spn_PARITY_ENABLE, TRUE); 10787 10788 SOC_IF_ERROR_RETURN(READ_THDO_MISCCONFIGr(unit, &rval)); 10789 soc_reg_field_set(unit, THDO_MISCCONFIGr, &rval, STAT_CLEARf, 0); 10790 soc_reg_field_set(unit, THDO_MISCCONFIGr, &rval, PARITY_CHK_ENf, 10791 parity_enable ? 1 : 0); 10792 soc_reg_field_set(unit, THDO_MISCCONFIGr, &rval, PARITY_GEN_ENf, 10793 parity_enable ? 1 : 0); 10794 SOC_IF_ERROR_RETURN(WRITE_THDO_MISCCONFIGr(unit, rval)); 10795 10796 SOC_IF_ERROR_RETURN(READ_WRED_MISCCONFIGr(unit, &rval)); 10797 soc_reg_field_set(unit, WRED_MISCCONFIGr, &rval, PARITY_STAT_CLRf, 0); 10798 soc_reg_field_set(unit, WRED_MISCCONFIGr, &rval, PARITY_CHK_ENf, 10799 parity_enable ? 1 : 0); 10800 soc_reg_field_set(unit, WRED_MISCCONFIGr, &rval, PARITY_GEN_ENf, 10801 parity_enable ? 1 : 0); 10802 SOC_IF_ERROR_RETURN(WRITE_WRED_MISCCONFIGr(unit, rval)); 10803 10804 SOC_IF_ERROR_RETURN(READ_OP_THR_CONFIGr(unit, &rval)); 10805 soc_reg_field_set(unit, OP_THR_CONFIGr, &rval, EARLY_E2E_SELECTf, 0); 10806 SOC_IF_ERROR_RETURN(WRITE_OP_THR_CONFIGr(unit, rval)); 10807 10808 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_SHARED_LIMIT_CELLIr(unit, &rval)); 10809 soc_reg_field_set(unit, OP_BUFFER_SHARED_LIMIT_CELLIr, &rval, 10810 OP_BUFFER_SHARED_LIMIT_CELLIf, 10490); 10811 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_SHARED_LIMIT_CELLIr(unit, rval)); 10812 10813 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_SHARED_LIMIT_CELLEr(unit, &rval)); 10814 soc_reg_field_set(unit, OP_BUFFER_SHARED_LIMIT_CELLEr, &rval, 10815 OP_BUFFER_SHARED_LIMIT_CELLEf, 0); 10816 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_SHARED_LIMIT_CELLEr(unit, rval)); 10817 10818 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_SHARED_LIMIT_QENTRYr(unit, &rval)); 10819 soc_reg_field_set(unit, OP_BUFFER_SHARED_LIMIT_QENTRYr, &rval, 10820 OP_BUFFER_SHARED_LIMIT_QENTRYf, 261712); 10821 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_SHARED_LIMIT_QENTRYr(unit, rval)); 10822 10823 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_SHARED_LIMIT_THDORQEQr(unit, &rval)); 10824 soc_reg_field_set(unit, OP_BUFFER_SHARED_LIMIT_THDORQEQr, &rval, 10825 OP_BUFFER_SHARED_LIMITf, 8191); 10826 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_SHARED_LIMIT_THDORQEQr(unit, rval)); 10827 10828 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_SHARED_LIMIT_THDOEMAr(unit, &rval)); 10829 soc_reg_field_set(unit, OP_BUFFER_SHARED_LIMIT_THDOEMAr, &rval, 10830 OP_BUFFER_SHARED_LIMITf, 0); 10831 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_SHARED_LIMIT_THDOEMAr(unit, rval)); 10832 10833 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_SHARED_LIMIT_RESUME_CELLIr(unit, &rval)); 10834 soc_reg_field_set(unit, OP_BUFFER_SHARED_LIMIT_RESUME_CELLIr, &rval, 10835 OP_BUFFER_SHARED_LIMIT_RESUME_CELLIf, 10427); 10836 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_SHARED_LIMIT_RESUME_CELLIr(unit, rval)); 10837 10838 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_SHARED_LIMIT_RESUME_CELLEr(unit, &rval)); 10839 soc_reg_field_set(unit, OP_BUFFER_SHARED_LIMIT_RESUME_CELLEr, &rval, 10840 OP_BUFFER_SHARED_LIMIT_RESUME_CELLEf, 0); 10841 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_SHARED_LIMIT_RESUME_CELLEr(unit, rval)); 10842 10843 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_SHARED_LIMIT_RESUME_QENTRYr(unit, &rval)); 10844 soc_reg_field_set(unit, OP_BUFFER_SHARED_LIMIT_RESUME_QENTRYr, &rval, 10845 OP_BUFFER_SHARED_LIMIT_RESUME_QENTRYf, 261523); 10846 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_SHARED_LIMIT_RESUME_QENTRYr(unit, rval)); 10847 10848 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_SHARED_LIMIT_RESUME_THDORQEQr(unit, &rval)); 10849 soc_reg_field_set(unit, OP_BUFFER_SHARED_LIMIT_RESUME_THDORQEQr, &rval, 10850 OP_BUFFER_SHARED_LIMIT_RESUMEf, 8185); 10851 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_SHARED_LIMIT_RESUME_THDORQEQr(unit, rval)); 10852 10853 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_SHARED_LIMIT_RESUME_THDOEMAr(unit, &rval)); 10854 soc_reg_field_set(unit, OP_BUFFER_SHARED_LIMIT_RESUME_THDOEMAr, &rval, 10855 OP_BUFFER_SHARED_LIMIT_RESUMEf, 0); 10856 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_SHARED_LIMIT_RESUME_THDOEMAr(unit, rval)); 10857 10858 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_LIMIT_YELLOW_CELLIr(unit, &rval)); 10859 soc_reg_field_set(unit, OP_BUFFER_LIMIT_YELLOW_CELLIr, &rval, 10860 OP_BUFFER_LIMIT_YELLOW_CELLIf, 1311); 10861 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_YELLOW_CELLIr(unit, rval)); 10862 10863 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_LIMIT_YELLOW_CELLEr(unit, &rval)); 10864 soc_reg_field_set(unit, OP_BUFFER_LIMIT_YELLOW_CELLEr, &rval, 10865 OP_BUFFER_LIMIT_YELLOW_CELLEf, 0); 10866 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_YELLOW_CELLEr(unit, rval)); 10867 10868 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_LIMIT_YELLOW_QENTRYr(unit, &rval)); 10869 soc_reg_field_set(unit, OP_BUFFER_LIMIT_YELLOW_QENTRYr, &rval, 10870 OP_BUFFER_LIMIT_YELLOW_QENTRYf, 32714); 10871 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_YELLOW_QENTRYr(unit, rval)); 10872 10873 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_LIMIT_YELLOW_THDORQEQr(unit, &rval)); 10874 soc_reg_field_set(unit, OP_BUFFER_LIMIT_YELLOW_THDORQEQr, &rval, 10875 OP_BUFFER_LIMIT_YELLOWf, 1023); 10876 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_YELLOW_THDORQEQr(unit, rval)); 10877 10878 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_LIMIT_YELLOW_THDOEMAr(unit, &rval)); 10879 soc_reg_field_set(unit, OP_BUFFER_LIMIT_YELLOW_THDOEMAr, &rval, 10880 OP_BUFFER_LIMIT_YELLOWf, 0); 10881 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_YELLOW_THDOEMAr(unit, rval)); 10882 10883 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_LIMIT_RESUME_YELLOW_CELLIr(unit, &rval)); 10884 soc_reg_field_set(unit, OP_BUFFER_LIMIT_RESUME_YELLOW_CELLIr, &rval, 10885 OP_BUFFER_LIMIT_RESUME_YELLOW_CELLIf, 1303); 10886 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_RESUME_YELLOW_CELLIr(unit, rval)); 10887 10888 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_LIMIT_RESUME_YELLOW_CELLEr(unit, &rval)); 10889 soc_reg_field_set(unit, OP_BUFFER_LIMIT_RESUME_YELLOW_CELLEr, &rval, 10890 OP_BUFFER_LIMIT_RESUME_YELLOW_CELLEf, 0); 10891 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_RESUME_YELLOW_CELLEr(unit, rval)); 10892 10893 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_LIMIT_RESUME_YELLOW_QENTRYr(unit, &rval)); 10894 soc_reg_field_set(unit, OP_BUFFER_LIMIT_RESUME_YELLOW_QENTRYr, &rval, 10895 OP_BUFFER_LIMIT_RESUME_YELLOW_QENTRYf, 32690); 10896 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_RESUME_YELLOW_QENTRYr(unit, rval)); 10897 10898 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_LIMIT_RESUME_YELLOW_THDORQEQr(unit, &rval)); 10899 soc_reg_field_set(unit, OP_BUFFER_LIMIT_RESUME_YELLOW_THDORQEQr, &rval, 10900 OP_BUFFER_LIMIT_RESUME_YELLOWf, 1022); 10901 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_RESUME_YELLOW_THDORQEQr(unit, rval)); 10902 10903 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_LIMIT_RESUME_YELLOW_THDOEMAr(unit, &rval)); 10904 soc_reg_field_set(unit, OP_BUFFER_LIMIT_RESUME_YELLOW_THDOEMAr, &rval, 10905 OP_BUFFER_LIMIT_RESUME_YELLOWf, 0); 10906 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_RESUME_YELLOW_THDOEMAr(unit, rval)); 10907 10908 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_LIMIT_RED_CELLIr(unit, &rval)); 10909 soc_reg_field_set(unit, OP_BUFFER_LIMIT_RED_CELLIr, &rval, 10910 OP_BUFFER_LIMIT_RED_CELLIf, 1311); 10911 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_RED_CELLIr(unit, rval)); 10912 10913 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_LIMIT_RED_CELLEr(unit, &rval)); 10914 soc_reg_field_set(unit, OP_BUFFER_LIMIT_RED_CELLEr, &rval, 10915 OP_BUFFER_LIMIT_RED_CELLEf, 0); 10916 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_RED_CELLEr(unit, rval)); 10917 10918 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_LIMIT_RED_QENTRYr(unit, &rval)); 10919 soc_reg_field_set(unit, OP_BUFFER_LIMIT_RED_QENTRYr, &rval, 10920 OP_BUFFER_LIMIT_RED_QENTRYf, 32714); 10921 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_RED_QENTRYr(unit, rval)); 10922 10923 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_LIMIT_RED_THDORQEQr(unit, &rval)); 10924 soc_reg_field_set(unit, OP_BUFFER_LIMIT_RED_THDORQEQr, &rval, 10925 OP_BUFFER_LIMIT_REDf, 1023); 10926 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_RED_THDORQEQr(unit, rval)); 10927 10928 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_LIMIT_RED_THDOEMAr(unit, &rval)); 10929 soc_reg_field_set(unit, OP_BUFFER_LIMIT_RED_THDOEMAr, &rval, 10930 OP_BUFFER_LIMIT_REDf, 0); 10931 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_RED_THDOEMAr(unit, rval)); 10932 10933 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_LIMIT_RESUME_RED_CELLIr(unit, &rval)); 10934 soc_reg_field_set(unit, OP_BUFFER_LIMIT_RESUME_RED_CELLIr, &rval, 10935 OP_BUFFER_LIMIT_RESUME_RED_CELLIf, 1303); 10936 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_RESUME_RED_CELLIr(unit, rval)); 10937 10938 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_LIMIT_RESUME_RED_CELLEr(unit, &rval)); 10939 soc_reg_field_set(unit, OP_BUFFER_LIMIT_RESUME_RED_CELLEr, &rval, 10940 OP_BUFFER_LIMIT_RESUME_RED_CELLEf, 0); 10941 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_RESUME_RED_CELLEr(unit, rval)); 10942 10943 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_LIMIT_RESUME_RED_QENTRYr(unit, &rval)); 10944 soc_reg_field_set(unit, OP_BUFFER_LIMIT_RESUME_RED_QENTRYr, &rval, 10945 OP_BUFFER_LIMIT_RESUME_RED_QENTRYf, 32690); 10946 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_RESUME_RED_QENTRYr(unit, rval)); 10947 10948 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_LIMIT_RESUME_RED_THDORQEQr(unit, &rval)); 10949 soc_reg_field_set(unit, OP_BUFFER_LIMIT_RESUME_RED_THDORQEQr, &rval, 10950 OP_BUFFER_LIMIT_RESUME_REDf, 1022); 10951 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_RESUME_RED_THDORQEQr(unit, rval)); 10952 10953 SOC_IF_ERROR_RETURN(READ_OP_BUFFER_LIMIT_RESUME_RED_THDOEMAr(unit, &rval)); 10954 soc_reg_field_set(unit, OP_BUFFER_LIMIT_RESUME_RED_THDOEMAr, &rval, 10955 OP_BUFFER_LIMIT_RESUME_REDf, 0); 10956 SOC_IF_ERROR_RETURN(WRITE_OP_BUFFER_LIMIT_RESUME_RED_THDOEMAr(unit, rval)); 10957 10958 for(i=0; i<SOC_REG_NUMELS(unit, OP_QUEUE_CONFIG_THDORQEIr); i++) { 10959 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_CONFIG_THDORQEIr(unit, i, &rval)); 10960 soc_reg_field_set(unit, OP_QUEUE_CONFIG_THDORQEIr, &rval, Q_LIMIT_ENABLEf, 0); 10961 soc_reg_field_set(unit, OP_QUEUE_CONFIG_THDORQEIr, &rval, Q_LIMIT_DYNAMICf, 0); 10962 soc_reg_field_set(unit, OP_QUEUE_CONFIG_THDORQEIr, &rval, Q_SHARED_LIMITf, 7079); 10963 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_CONFIG_THDORQEIr(unit, i, rval)); 10964 } 10965 for(i=0; i<SOC_REG_NUMELS(unit, OP_QUEUE_CONFIG_THDORQEEr); i++) { 10966 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_CONFIG_THDORQEEr(unit, i, &rval)); 10967 soc_reg_field_set(unit, OP_QUEUE_CONFIG_THDORQEEr, &rval, Q_LIMIT_ENABLEf, 0); 10968 soc_reg_field_set(unit, OP_QUEUE_CONFIG_THDORQEEr, &rval, Q_LIMIT_DYNAMICf, 0); 10969 soc_reg_field_set(unit, OP_QUEUE_CONFIG_THDORQEEr, &rval, Q_SHARED_LIMITf, 0); 10970 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_CONFIG_THDORQEEr(unit, i, rval)); 10971 } 10972 for(i=0; i<SOC_REG_NUMELS(unit, OP_QUEUE_CONFIG_THDORQEQr); i++) { 10973 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_CONFIG_THDORQEQr(unit, i, &rval)); 10974 soc_reg_field_set(unit, OP_QUEUE_CONFIG_THDORQEQr, &rval, Q_LIMIT_ENABLEf, 0); 10975 soc_reg_field_set(unit, OP_QUEUE_CONFIG_THDORQEQr, &rval, Q_LIMIT_DYNAMICf, 0); 10976 soc_reg_field_set(unit, OP_QUEUE_CONFIG_THDORQEQr, &rval, Q_SHARED_LIMITf, 8191); 10977 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_CONFIG_THDORQEQr(unit, i, rval)); 10978 } 10979 for(i=0; i<SOC_REG_NUMELS(unit, OP_QUEUE_CONFIG_THDOEMAr); i++) { 10980 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_CONFIG_THDOEMAr(unit, i, &rval)); 10981 soc_reg_field_set(unit, OP_QUEUE_CONFIG_THDOEMAr, &rval, Q_LIMIT_ENABLEf, 0); 10982 soc_reg_field_set(unit, OP_QUEUE_CONFIG_THDOEMAr, &rval, Q_LIMIT_DYNAMICf, 0); 10983 soc_reg_field_set(unit, OP_QUEUE_CONFIG_THDOEMAr, &rval, Q_SHARED_LIMITf, 0); 10984 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_CONFIG_THDOEMAr(unit, i, rval)); 10985 } 10986 10987 for(i=0; i<SOC_REG_NUMELS(unit, OP_QUEUE_CONFIG1_THDORQEIr); i++) { 10988 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_CONFIG1_THDORQEIr(unit, i, &rval)); 10989 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_THDORQEIr, &rval, Q_COLOR_ENABLEf, 0); 10990 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_THDORQEIr, &rval, Q_COLOR_DYNAMICf, 0); 10991 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_THDORQEIr, &rval, Q_MINf, 0); 10992 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_CONFIG1_THDORQEIr(unit, i, rval)); 10993 } 10994 for(i=0; i<SOC_REG_NUMELS(unit, OP_QUEUE_CONFIG1_THDORQEEr); i++) { 10995 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_CONFIG1_THDORQEEr(unit, i, &rval)); 10996 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_THDORQEEr, &rval, Q_COLOR_ENABLEf, 0); 10997 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_THDORQEEr, &rval, Q_COLOR_DYNAMICf, 0); 10998 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_THDORQEEr, &rval, Q_MINf, 0); 10999 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_CONFIG1_THDORQEEr(unit, i, rval)); 11000 } 11001 for(i=0; i<SOC_REG_NUMELS(unit, OP_QUEUE_CONFIG1_THDORQEQr); i++) { 11002 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_CONFIG1_THDORQEQr(unit, i, &rval)); 11003 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_THDORQEQr, &rval, Q_COLOR_ENABLEf, 0); 11004 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_THDORQEQr, &rval, Q_COLOR_DYNAMICf, 0); 11005 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_THDORQEQr, &rval, Q_MINf, 0); 11006 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_CONFIG1_THDORQEQr(unit, i, rval)); 11007 } 11008 for(i=0; i<SOC_REG_NUMELS(unit, OP_QUEUE_CONFIG1_THDOEMAr); i++) { 11009 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_CONFIG1_THDOEMAr(unit, i, &rval)); 11010 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_THDOEMAr, &rval, Q_COLOR_ENABLEf, 0); 11011 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_THDOEMAr, &rval, Q_COLOR_DYNAMICf, 0); 11012 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_THDOEMAr, &rval, Q_MINf, 0); 11013 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_CONFIG1_THDOEMAr(unit, i, rval)); 11014 } 11015 11016 for(i=0; i<SOC_REG_NUMELS(unit, OP_QUEUE_RESET_OFFSET_THDORQEIr); i++) { 11017 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_RESET_OFFSET_THDORQEIr(unit, i, &rval)); 11018 soc_reg_field_set(unit, OP_QUEUE_RESET_OFFSET_THDORQEIr, &rval, Q_RESET_OFFSETf, 2); 11019 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_RESET_OFFSET_THDORQEIr(unit, i, rval)); 11020 } 11021 for(i=0; i<SOC_REG_NUMELS(unit, OP_QUEUE_RESET_OFFSET_THDORQEEr); i++) { 11022 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_RESET_OFFSET_THDORQEEr(unit, i, &rval)); 11023 soc_reg_field_set(unit, OP_QUEUE_RESET_OFFSET_THDORQEEr, &rval, Q_RESET_OFFSETf, 0); 11024 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_RESET_OFFSET_THDORQEEr(unit, i, rval)); 11025 } 11026 for(i=0; i<SOC_REG_NUMELS(unit, OP_QUEUE_RESET_OFFSET_THDORQEQr); i++) { 11027 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_RESET_OFFSET_THDORQEQr(unit, i, &rval)); 11028 soc_reg_field_set(unit, OP_QUEUE_RESET_OFFSET_THDORQEQr, &rval, Q_RESET_OFFSETf, 1); 11029 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_RESET_OFFSET_THDORQEQr(unit, i, rval)); 11030 } 11031 for(i=0; i<SOC_REG_NUMELS(unit, OP_QUEUE_RESET_OFFSET_THDOEMAr); i++) { 11032 SOC_IF_ERROR_RETURN(READ_OP_QUEUE_RESET_OFFSET_THDOEMAr(unit, i, &rval)); 11033 soc_reg_field_set(unit, OP_QUEUE_RESET_OFFSET_THDOEMAr, &rval, Q_RESET_OFFSETf, 0); 11034 SOC_IF_ERROR_RETURN(WRITE_OP_QUEUE_RESET_OFFSET_THDOEMAr(unit, i, rval)); 11035 } 11036 for(i=0; i<272; i++) { /* 8 x 28 ports + 48 CPU */ 11037 SOC_IF_ERROR_RETURN(READ_MMU_THDO_QCONFIG_CELLm(unit,MEM_BLOCK_ANY,i,&entry)); 11038 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, &entry, 11039 Q_SHARED_LIMIT_CELLf, 10490); 11040 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, &entry, 11041 Q_MIN_CELLf, 0); 11042 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, &entry, 11043 Q_LIMIT_ENABLE_CELLf, 0); 11044 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, &entry, 11045 Q_LIMIT_DYNAMIC_CELLf, 0); 11046 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_CELLm, &entry, 11047 Q_COLOR_ENABLE_CELLf, 0); 11048 SOC_IF_ERROR_RETURN(WRITE_MMU_THDO_QCONFIG_CELLm(unit,MEM_BLOCK_ANY,i,&entry)); 11049 11050 SOC_IF_ERROR_RETURN(READ_MMU_THDO_QOFFSET_CELLm(unit,MEM_BLOCK_ANY,i,&entry)); 11051 soc_mem_field32_set(unit, MMU_THDO_QOFFSET_CELLm, &entry, 11052 RESET_OFFSET_CELLf, 2); 11053 SOC_IF_ERROR_RETURN(WRITE_MMU_THDO_QOFFSET_CELLm(unit,MEM_BLOCK_ANY,i,&entry)); 11054 11055 SOC_IF_ERROR_RETURN(READ_MMU_THDO_QCONFIG_QENTRYm(unit,MEM_BLOCK_ANY,i,&entry)); 11056 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_QENTRYm, &entry, 11057 Q_SHARED_LIMIT_QENTRYf, 261712); 11058 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_QENTRYm, &entry, 11059 Q_MIN_QENTRYf, 0); 11060 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_QENTRYm, &entry, 11061 Q_LIMIT_ENABLE_QENTRYf, 0); 11062 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_QENTRYm, &entry, 11063 Q_LIMIT_DYNAMIC_QENTRYf, 0); 11064 soc_mem_field32_set(unit, MMU_THDO_QCONFIG_QENTRYm, &entry, 11065 Q_COLOR_ENABLE_QENTRYf, 0); 11066 SOC_IF_ERROR_RETURN(WRITE_MMU_THDO_QCONFIG_QENTRYm(unit,MEM_BLOCK_ANY,i,&entry)); 11067 11068 SOC_IF_ERROR_RETURN(READ_MMU_THDO_QOFFSET_QENTRYm(unit,MEM_BLOCK_ANY,i,&entry)); 11069 soc_mem_field32_set(unit, MMU_THDO_QOFFSET_QENTRYm, &entry, 11070 RESET_OFFSET_QENTRYf, 1); 11071 SOC_IF_ERROR_RETURN(WRITE_MMU_THDO_QOFFSET_QENTRYm(unit,MEM_BLOCK_ANY,i,&entry)); 11072 } 11073 11074 /* Helper function for MMU settings based on 11075 memory selection (internal/external/both) and mode (lossless/lossy) */ 11076 SOC_IF_ERROR_RETURN(_soc_katana_mmu_init_helper(unit)); 11077 11078 /* Initialize MMU internal/external aging limit memory */ 11079 count = soc_mem_index_count(unit, MMU_AGING_LMT_INTm); 11080 sal_memset(&age_entry, 0, sizeof(mmu_aging_lmt_int_entry_t)); 11081 for (i=0; i < count; i++) { 11082 SOC_IF_ERROR_RETURN(WRITE_MMU_AGING_LMT_INTm(unit, 11083 MEM_BLOCK_ANY, i, &age_entry)); 11084 } 11085 11086 count = soc_mem_index_count(unit, MMU_AGING_LMT_EXTm); 11087 for (i=0; i < count; i++) { 11088 SOC_IF_ERROR_RETURN(WRITE_MMU_AGING_LMT_EXTm(unit, 11089 MEM_BLOCK_ANY, i, &age_entry)); 11090 } 11091 11092 SOC_IF_ERROR_RETURN(READ_THDO_DROP_CTR_CONFIGr(unit, &rval)); 11093 soc_reg_field_set(unit, THDO_DROP_CTR_CONFIGr, &rval, OP_CNT_CFGf, 1); 11094 SOC_IF_ERROR_RETURN(WRITE_THDO_DROP_CTR_CONFIGr(unit, rval)); 11095 11096 if (soc_feature(unit, soc_feature_post)) { 11097 SOC_IF_ERROR_RETURN(soc_mmu_post_init(unit)); 11098 } 11099 11100 return SOC_E_NONE; 11101 } 11102 11103 STATIC int 11104 _soc_katana_age_timer_get(int unit, int *age_seconds, int *enabled) 11105 { 11106 uint32 rval; 11107 11108 SOC_IF_ERROR_RETURN(READ_L2_AGE_TIMERr(unit, &rval)); 11109 *enabled = soc_reg_field_get(unit, L2_AGE_TIMERr, rval, AGE_ENAf); 11110 *age_seconds = soc_reg_field_get(unit, L2_AGE_TIMERr, rval, AGE_VALf); 11111 11112 return SOC_E_NONE; 11113 } 11114 11115 STATIC int 11116 _soc_katana_age_timer_max_get(int unit, int *max_seconds) 11117 { 11118 *max_seconds = 11119 soc_reg_field_get(unit, L2_AGE_TIMERr, 0xffffffff, AGE_VALf); 11120 11121 return SOC_E_NONE; 11122 } 11123 11124 STATIC int 11125 _soc_katana_age_timer_set(int unit, int age_seconds, int enable) 11126 { 11127 uint32 rval; 11128 11129 rval = 0; 11130 soc_reg_field_set(unit, L2_AGE_TIMERr, &rval, AGE_ENAf, enable); 11131 soc_reg_field_set(unit, L2_AGE_TIMERr, &rval, AGE_VALf, age_seconds); 11132 SOC_IF_ERROR_RETURN(WRITE_L2_AGE_TIMERr(unit, rval)); 11133 11134 return SOC_E_NONE; 11135 } 11136 11137 /* *************** WORKAROUND *********************************************** 11138 * In Enduro-2 Variant, Access to LLS is inhibited by CI blocks, which share the 11139 * sbus ring. DDR clock is not present in this variant. So, the WAR is to use the 11140 * TAP Interface to propagate coreclk to flops that were on DDR clock so that 11141 * even if DDR clock is not running, the reset sync flops can get some clock pulses 11142 * *** DO NOT CHANGE THIS SEQUENCE UNLESS YOU KNOW WHAT YOU ARE DOING *** 11143 */ 11144 #define TAP_SEQ_1(_i, _j) do { \ 11145 WRITE_TOP_TAP_CONTROLr(unit,0xc); \ 11146 for (i=0; i<(_i); i++) { \ 11147 WRITE_TOP_TAP_CONTROLr(unit,0xd); \ 11148 WRITE_TOP_TAP_CONTROLr(unit,0x9); \ 11149 } \ 11150 WRITE_TOP_TAP_CONTROLr(unit,0xd); \ 11151 for (i=0; i<(_j); i++) { \ 11152 WRITE_TOP_TAP_CONTROLr(unit,0xc); \ 11153 WRITE_TOP_TAP_CONTROLr(unit,0x8); \ 11154 }\ 11155 } while(0) 11156 11157 #define TAP_SEQ_2(_i) do { \ 11158 WRITE_TOP_TAP_CONTROLr(unit,0xe); \ 11159 WRITE_TOP_TAP_CONTROLr(unit,0xa); \ 11160 WRITE_TOP_TAP_CONTROLr(unit,0xe); \ 11161 for (i=0; i<(_i); i++) { \ 11162 WRITE_TOP_TAP_CONTROLr(unit,0xc); \ 11163 WRITE_TOP_TAP_CONTROLr(unit,0x8); \ 11164 } \ 11165 } while(0) 11166 11167 void 11168 _kt_lls_workaround(int unit) 11169 { 11170 int i,j; 11171 11172 WRITE_TOP_TAP_CONTROLr(unit,0xc); 11173 WRITE_TOP_TAP_CONTROLr(unit,0xe); 11174 WRITE_TOP_TAP_CONTROLr(unit,0xa); 11175 WRITE_TOP_TAP_CONTROLr(unit,0xe); 11176 WRITE_TOP_TAP_CONTROLr(unit,0xe); 11177 WRITE_TOP_TAP_CONTROLr(unit,0xa); 11178 WRITE_TOP_TAP_CONTROLr(unit,0xe); 11179 WRITE_TOP_TAP_CONTROLr(unit,0xa); 11180 WRITE_TOP_TAP_CONTROLr(unit,0xe); 11181 WRITE_TOP_TAP_CONTROLr(unit,0xa); 11182 WRITE_TOP_TAP_CONTROLr(unit,0xe); 11183 WRITE_TOP_TAP_CONTROLr(unit,0xa); 11184 WRITE_TOP_TAP_CONTROLr(unit,0xe); 11185 WRITE_TOP_TAP_CONTROLr(unit,0xa); 11186 WRITE_TOP_TAP_CONTROLr(unit,0xe); 11187 WRITE_TOP_TAP_CONTROLr(unit,0xa); 11188 WRITE_TOP_TAP_CONTROLr(unit,0xe); 11189 WRITE_TOP_TAP_CONTROLr(unit,0xc); 11190 WRITE_TOP_TAP_CONTROLr(unit,0x8); 11191 WRITE_TOP_TAP_CONTROLr(unit,0xc); 11192 WRITE_TOP_TAP_CONTROLr(unit,0x8); 11193 WRITE_TOP_TAP_CONTROLr(unit,0xc); 11194 11195 WRITE_TOP_TAP_CONTROLr(unit,0xc); 11196 WRITE_TOP_TAP_CONTROLr(unit,0xe); 11197 WRITE_TOP_TAP_CONTROLr(unit,0xa); 11198 11199 TAP_SEQ_2(3); 11200 TAP_SEQ_1(1,1); 11201 TAP_SEQ_1(6,3); 11202 TAP_SEQ_1(8,1); 11203 TAP_SEQ_1(9,0); 11204 WRITE_TOP_TAP_CONTROLr(unit,0x9); 11205 WRITE_TOP_TAP_CONTROLr(unit,0xd); 11206 WRITE_TOP_TAP_CONTROLr(unit,0xf); 11207 WRITE_TOP_TAP_CONTROLr(unit,0xb); 11208 WRITE_TOP_TAP_CONTROLr(unit,0xf); 11209 TAP_SEQ_2(1); 11210 WRITE_TOP_TAP_CONTROLr(unit,0xc); 11211 TAP_SEQ_2(21); 11212 TAP_SEQ_1(1,341); 11213 TAP_SEQ_1(2,13); 11214 WRITE_TOP_TAP_CONTROLr(unit,0xc); 11215 WRITE_TOP_TAP_CONTROLr(unit,0xe); 11216 WRITE_TOP_TAP_CONTROLr(unit,0xa); 11217 TAP_SEQ_2(2); 11218 WRITE_TOP_TAP_CONTROLr(unit,0xc); 11219 11220 sal_usleep(1); 11221 11222 WRITE_TOP_TAP_CONTROLr(unit,0xe); 11223 WRITE_TOP_TAP_CONTROLr(unit,0xa); 11224 TAP_SEQ_2(3); 11225 TAP_SEQ_1(1,1); 11226 TAP_SEQ_1(6,3); 11227 TAP_SEQ_1(8,1); 11228 TAP_SEQ_1(9,0); 11229 WRITE_TOP_TAP_CONTROLr(unit,0x9); 11230 WRITE_TOP_TAP_CONTROLr(unit,0xd); 11231 WRITE_TOP_TAP_CONTROLr(unit,0xf); 11232 WRITE_TOP_TAP_CONTROLr(unit,0xb); 11233 WRITE_TOP_TAP_CONTROLr(unit,0xf); 11234 TAP_SEQ_2(1); 11235 WRITE_TOP_TAP_CONTROLr(unit,0xc); 11236 TAP_SEQ_2(14); 11237 TAP_SEQ_1(2,5); 11238 TAP_SEQ_1(1,2); 11239 TAP_SEQ_1(1,338); 11240 TAP_SEQ_1(2,13); 11241 WRITE_TOP_TAP_CONTROLr(unit,0xc); 11242 WRITE_TOP_TAP_CONTROLr(unit,0xe); 11243 WRITE_TOP_TAP_CONTROLr(unit,0xa); 11244 TAP_SEQ_2(1); 11245 WRITE_TOP_TAP_CONTROLr(unit,0xc); 11246 WRITE_TOP_TAP_CONTROLr(unit,0xe); 11247 WRITE_TOP_TAP_CONTROLr(unit,0xa); 11248 TAP_SEQ_2(3); 11249 TAP_SEQ_1(1,1); 11250 TAP_SEQ_1(3,1); 11251 TAP_SEQ_1(2,1); 11252 TAP_SEQ_1(10,1); 11253 TAP_SEQ_1(9,0); 11254 WRITE_TOP_TAP_CONTROLr(unit,0x9); 11255 WRITE_TOP_TAP_CONTROLr(unit,0xd); 11256 WRITE_TOP_TAP_CONTROLr(unit,0xf); 11257 WRITE_TOP_TAP_CONTROLr(unit,0xb); 11258 WRITE_TOP_TAP_CONTROLr(unit,0xf); 11259 TAP_SEQ_2(1); 11260 WRITE_TOP_TAP_CONTROLr(unit,0xc); 11261 TAP_SEQ_2(4); 11262 TAP_SEQ_1(1,703); 11263 TAP_SEQ_1(22,1); 11264 for (j=0; j<9; j++) { 11265 TAP_SEQ_1(32,1);; 11266 } 11267 TAP_SEQ_1(32,17); 11268 TAP_SEQ_1(1,3); 11269 TAP_SEQ_1(1,3); 11270 TAP_SEQ_1(3,7); 11271 TAP_SEQ_1(1,10); 11272 TAP_SEQ_1(1,5); 11273 TAP_SEQ_1(1,2); 11274 TAP_SEQ_1(1,2); 11275 WRITE_TOP_TAP_CONTROLr(unit,0xc); 11276 WRITE_TOP_TAP_CONTROLr(unit,0xe); 11277 WRITE_TOP_TAP_CONTROLr(unit,0xa); 11278 TAP_SEQ_2(1); 11279 WRITE_TOP_TAP_CONTROLr(unit,0xc); 11280 WRITE_TOP_TAP_CONTROLr(unit,0xe); 11281 WRITE_TOP_TAP_CONTROLr(unit,0xa); 11282 TAP_SEQ_2(3); 11283 TAP_SEQ_1(1,1); 11284 TAP_SEQ_1(6,3); 11285 TAP_SEQ_1(8,1); 11286 TAP_SEQ_1(9,0); 11287 WRITE_TOP_TAP_CONTROLr(unit,0x9); 11288 WRITE_TOP_TAP_CONTROLr(unit,0xd); 11289 WRITE_TOP_TAP_CONTROLr(unit,0xf); 11290 WRITE_TOP_TAP_CONTROLr(unit,0xb); 11291 WRITE_TOP_TAP_CONTROLr(unit,0xf); 11292 TAP_SEQ_2(1); 11293 WRITE_TOP_TAP_CONTROLr(unit,0xc); 11294 TAP_SEQ_2(14); 11295 TAP_SEQ_1(2,2); 11296 TAP_SEQ_1(1,2); 11297 TAP_SEQ_1(1,2); 11298 TAP_SEQ_1(1,338); 11299 TAP_SEQ_1(2,13); 11300 WRITE_TOP_TAP_CONTROLr(unit,0xc); 11301 WRITE_TOP_TAP_CONTROLr(unit,0xe); 11302 WRITE_TOP_TAP_CONTROLr(unit,0xa); 11303 TAP_SEQ_2(1); 11304 WRITE_TOP_TAP_CONTROLr(unit,0xc); 11305 WRITE_TOP_TAP_CONTROLr(unit,0xe); 11306 WRITE_TOP_TAP_CONTROLr(unit,0xa); 11307 TAP_SEQ_2(3); 11308 TAP_SEQ_1(1,1); 11309 TAP_SEQ_1(6,3); 11310 TAP_SEQ_1(8,1); 11311 TAP_SEQ_1(9,0); 11312 WRITE_TOP_TAP_CONTROLr(unit,0x9); 11313 WRITE_TOP_TAP_CONTROLr(unit,0xd); 11314 WRITE_TOP_TAP_CONTROLr(unit,0xf); 11315 WRITE_TOP_TAP_CONTROLr(unit,0xb); 11316 WRITE_TOP_TAP_CONTROLr(unit,0xf); 11317 TAP_SEQ_2(1); 11318 WRITE_TOP_TAP_CONTROLr(unit,0xc); 11319 TAP_SEQ_2(5); 11320 WRITE_TOP_TAP_CONTROLr(unit,0xc); 11321 11322 sal_usleep(4); 11323 11324 WRITE_TOP_TAP_CONTROLr(unit,0x8); 11325 11326 for (j=0; j<9; j++) { 11327 WRITE_TOP_TAP_CONTROLr(unit,0xc); 11328 WRITE_TOP_TAP_CONTROLr(unit,0x8); 11329 } 11330 TAP_SEQ_1(1,2); 11331 TAP_SEQ_1(1,2); 11332 TAP_SEQ_1(1,2); 11333 TAP_SEQ_1(1,338); 11334 TAP_SEQ_1(2,13); 11335 WRITE_TOP_TAP_CONTROLr(unit,0xc); 11336 WRITE_TOP_TAP_CONTROLr(unit,0xe); 11337 WRITE_TOP_TAP_CONTROLr(unit,0xa); 11338 TAP_SEQ_2(1); 11339 WRITE_TOP_TAP_CONTROLr(unit,0xc); 11340 TAP_SEQ_2(5); 11341 WRITE_TOP_TAP_CONTROLr(unit,0xc); 11342 11343 sal_usleep(4); 11344 11345 WRITE_TOP_TAP_CONTROLr(unit,0x8); 11346 for (j=0; j<9; j++) { 11347 WRITE_TOP_TAP_CONTROLr(unit,0xc); 11348 WRITE_TOP_TAP_CONTROLr(unit,0x8); 11349 } 11350 TAP_SEQ_1(2,1); 11351 TAP_SEQ_1(1,2); 11352 TAP_SEQ_1(1,2); 11353 TAP_SEQ_1(1,338); 11354 TAP_SEQ_1(2,13); 11355 WRITE_TOP_TAP_CONTROLr(unit,0xc); 11356 WRITE_TOP_TAP_CONTROLr(unit,0xe); 11357 WRITE_TOP_TAP_CONTROLr(unit,0xa); 11358 TAP_SEQ_2(1); 11359 WRITE_TOP_TAP_CONTROLr(unit,0xc); 11360 TAP_SEQ_2(15); 11361 TAP_SEQ_1(2,1); 11362 TAP_SEQ_1(1,1); 11363 TAP_SEQ_1(2,2); 11364 TAP_SEQ_1(1,338); 11365 TAP_SEQ_1(2,13); 11366 WRITE_TOP_TAP_CONTROLr(unit,0xc); 11367 WRITE_TOP_TAP_CONTROLr(unit,0xe); 11368 WRITE_TOP_TAP_CONTROLr(unit,0xa); 11369 TAP_SEQ_2(1); 11370 WRITE_TOP_TAP_CONTROLr(unit,0xc); 11371 TAP_SEQ_2(15); 11372 TAP_SEQ_1(2,3); 11373 TAP_SEQ_1(2,2); 11374 TAP_SEQ_1(1,338); 11375 TAP_SEQ_1(2,13); 11376 WRITE_TOP_TAP_CONTROLr(unit,0xc); 11377 WRITE_TOP_TAP_CONTROLr(unit,0xe); 11378 WRITE_TOP_TAP_CONTROLr(unit,0xa); 11379 TAP_SEQ_2(1); 11380 WRITE_TOP_TAP_CONTROLr(unit,0xc); 11381 11382 sal_usleep(15); 11383 11384 WRITE_TOP_TAP_CONTROLr(unit,0x8); 11385 WRITE_TOP_TAP_CONTROLr(unit,0xc); 11386 11387 sal_usleep(1200); 11388 11389 WRITE_TOP_TAP_CONTROLr(unit,0x8); 11390 WRITE_TOP_TAP_CONTROLr(unit,0xc); 11391 WRITE_TOP_TAP_CONTROLr(unit,0xe); 11392 WRITE_TOP_TAP_CONTROLr(unit,0xa); 11393 TAP_SEQ_2(3); 11394 TAP_SEQ_1(1,1); 11395 TAP_SEQ_1(6,3); 11396 TAP_SEQ_1(8,1); 11397 TAP_SEQ_1(9,0); 11398 WRITE_TOP_TAP_CONTROLr(unit,0x9); 11399 WRITE_TOP_TAP_CONTROLr(unit,0xd); 11400 WRITE_TOP_TAP_CONTROLr(unit,0xf); 11401 WRITE_TOP_TAP_CONTROLr(unit,0xb); 11402 WRITE_TOP_TAP_CONTROLr(unit,0xf); 11403 TAP_SEQ_2(1); 11404 WRITE_TOP_TAP_CONTROLr(unit,0xc); 11405 TAP_SEQ_2(15); 11406 TAP_SEQ_1(2,1); 11407 TAP_SEQ_1(1,1); 11408 TAP_SEQ_1(2,2); 11409 TAP_SEQ_1(1,338); 11410 TAP_SEQ_1(2,13); 11411 WRITE_TOP_TAP_CONTROLr(unit,0xc); 11412 WRITE_TOP_TAP_CONTROLr(unit,0xe); 11413 WRITE_TOP_TAP_CONTROLr(unit,0xa); 11414 TAP_SEQ_2(1); 11415 WRITE_TOP_TAP_CONTROLr(unit,0xc); 11416 TAP_SEQ_2(5); 11417 WRITE_TOP_TAP_CONTROLr(unit,0xc); 11418 11419 sal_usleep(4); 11420 11421 WRITE_TOP_TAP_CONTROLr(unit,0x8); 11422 for (j=0; j<9; j++) { 11423 WRITE_TOP_TAP_CONTROLr(unit,0xc); 11424 WRITE_TOP_TAP_CONTROLr(unit,0x8); 11425 } 11426 TAP_SEQ_1(1,2); 11427 TAP_SEQ_1(1,1); 11428 TAP_SEQ_1(2,2); 11429 TAP_SEQ_1(1,14); 11430 WRITE_TOP_TAP_CONTROLr(unit,0xe); 11431 WRITE_TOP_TAP_CONTROLr(unit,0xa); 11432 TAP_SEQ_2(1); 11433 WRITE_TOP_TAP_CONTROLr(unit,0xc); 11434 for (i=0; i<6; i++) { 11435 WRITE_TOP_TAP_CONTROLr(unit,0x0); 11436 } 11437 } 11438 11439 11440 /* 11441 * Katana chip driver functions. 11442 */ 11443 soc_functions_t soc_katana_drv_funs = { 11444 _soc_katana_misc_init, 11445 _soc_katana_mmu_init, 11446 _soc_katana_age_timer_get, 11447 _soc_katana_age_timer_max_get, 11448 _soc_katana_age_timer_set, 11449 }; 11450 11451 11452 static const soc_reg_t thermal_reg[] = { 11453 TOP_THERMAL_PVTMON_RESULT_0r, TOP_THERMAL_PVTMON_RESULT_1r, 11454 TOP_THERMAL_PVTMON_RESULT_2r, TOP_THERMAL_PVTMON_RESULT_3r 11455 }; 11456 11457 int 11458 _soc_katana_temperature_monitor_init(int unit) { 11459 uint32 rval; 11460 11461 SOC_IF_ERROR_RETURN(READ_TOP_THERMAL_PVTMON_CTRL_2r(unit, &rval)); 11462 soc_reg_field_set(unit, TOP_THERMAL_PVTMON_CTRL_2r, &rval, PVTMON_RSTBf, 1); 11463 SOC_IF_ERROR_RETURN(WRITE_TOP_THERMAL_PVTMON_CTRL_2r(unit, rval)); 11464 11465 SOC_IF_ERROR_RETURN(READ_TOP_THERMAL_PVTMON_CTRLr(unit, &rval)); 11466 soc_reg_field_set(unit, TOP_THERMAL_PVTMON_CTRLr, &rval, PROG_RESISTERf, 3); 11467 soc_reg_field_set(unit, TOP_THERMAL_PVTMON_CTRLr, &rval, BG_ADJf, 3); 11468 soc_reg_field_set(unit, TOP_THERMAL_PVTMON_CTRLr, &rval, MEASUREMENT_CALLIBRATIONf, 5); 11469 SOC_IF_ERROR_RETURN(WRITE_TOP_THERMAL_PVTMON_CTRLr(unit, rval)); 11470 11471 SOC_IF_ERROR_RETURN(READ_TOP_THERMAL_PVTMON_CTRL_2r(unit, &rval)); 11472 soc_reg_field_set(unit, TOP_THERMAL_PVTMON_CTRL_2r, &rval, PVTMON_SELECTf, 0); 11473 soc_reg_field_set(unit, TOP_THERMAL_PVTMON_CTRL_2r, &rval, PVTMON_RSTBf, 0); 11474 SOC_IF_ERROR_RETURN(WRITE_TOP_THERMAL_PVTMON_CTRL_2r(unit, rval)); 11475 11476 SOC_IF_ERROR_RETURN(READ_TOP_THERMAL_PVTMON_CTRL_2r(unit, &rval)); 11477 soc_reg_field_set(unit, TOP_THERMAL_PVTMON_CTRL_2r, &rval, PVTMON_RSTBf, 1); 11478 SOC_IF_ERROR_RETURN(WRITE_TOP_THERMAL_PVTMON_CTRL_2r(unit, rval)); 11479 11480 sal_usleep(1000); 11481 11482 return SOC_E_NONE; 11483 } 11484 11485 int 11486 soc_katana_temperature_monitor_get(int unit, 11487 int temperature_max, 11488 soc_switch_temperature_monitor_t *temperature_array, 11489 int *temperature_count) 11490 { 11491 uint32 rval; 11492 soc_reg_t reg; 11493 int index; 11494 int fval, cur, peak; 11495 int num_entries_out; 11496 11497 *temperature_count = 0; 11498 if (COUNTOF(thermal_reg) > temperature_max) { 11499 num_entries_out = temperature_max; 11500 } else { 11501 num_entries_out = COUNTOF(thermal_reg); 11502 } 11503 /* Check to see if the thermal monitor is initialized */ 11504 SOC_IF_ERROR_RETURN(READ_TOP_THERMAL_PVTMON_CTRL_2r(unit, &rval)); 11505 if ((soc_reg_field_get(unit, TOP_THERMAL_PVTMON_CTRL_2r, rval, PVTMON_RSTBf) == 0) || 11506 (soc_reg_field_get(unit, TOP_THERMAL_PVTMON_CTRL_2r, rval, PVTMON_SELECTf) != 0)) { 11507 SOC_IF_ERROR_RETURN(_soc_katana_temperature_monitor_init(unit)); 11508 } 11509 11510 for (index = 0; index < num_entries_out; index++) { 11511 reg = thermal_reg[index]; 11512 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, reg, REG_PORT_ANY, 0, &rval)); 11513 if (soc_reg_field_valid(unit, reg, PVTTEMP_DATAf)) { 11514 fval = soc_reg_field_get(unit, reg, rval, PVTTEMP_DATAf); 11515 } else { 11516 fval = soc_reg_field_get(unit, reg, rval, TEMP_DATAf); 11517 } 11518 cur = (4180000 - (5556 * fval)) / 1000; 11519 if (soc_reg_field_valid(unit, reg, PEAK_PVTTEMP_DATAf)) { 11520 fval = soc_reg_field_get(unit, reg, rval, PEAK_PVTTEMP_DATAf); 11521 } else { 11522 fval = soc_reg_field_get(unit, reg, rval, PEAK_TEMP_DATAf); 11523 } 11524 peak = (4180000 - (5556 * fval)) / 1000; 11525 (temperature_array + index)->curr = cur; 11526 (temperature_array + index)->peak = peak; 11527 } 11528 SOC_IF_ERROR_RETURN(READ_TOP_MISC_CONTROLr(unit, &rval)); 11529 soc_reg_field_set(unit, TOP_MISC_CONTROLr, &rval, 11530 THERMAL_PVTMON0_PEAK_DATA_RST_Lf, 1); 11531 soc_reg_field_set(unit, TOP_MISC_CONTROLr, &rval, 11532 THERMAL_PVTMON1_PEAK_DATA_RST_Lf, 1); 11533 soc_reg_field_set(unit, TOP_MISC_CONTROLr, &rval, 11534 THERMAL_PVTMON2_PEAK_DATA_RST_Lf, 1); 11535 soc_reg_field_set(unit, TOP_MISC_CONTROLr, &rval, 11536 THERMAL_PVTMON3_PEAK_DATA_RST_Lf, 1); 11537 SOC_IF_ERROR_RETURN(WRITE_TOP_MISC_CONTROLr(unit, rval)); 11538 soc_reg_field_set(unit, TOP_MISC_CONTROLr, &rval, 11539 THERMAL_PVTMON0_PEAK_DATA_RST_Lf, 0); 11540 soc_reg_field_set(unit, TOP_MISC_CONTROLr, &rval, 11541 THERMAL_PVTMON1_PEAK_DATA_RST_Lf, 0); 11542 soc_reg_field_set(unit, TOP_MISC_CONTROLr, &rval, 11543 THERMAL_PVTMON2_PEAK_DATA_RST_Lf, 0); 11544 soc_reg_field_set(unit, TOP_MISC_CONTROLr, &rval, 11545 THERMAL_PVTMON3_PEAK_DATA_RST_Lf, 0); 11546 SOC_IF_ERROR_RETURN(WRITE_TOP_MISC_CONTROLr(unit, rval)); 11547 *temperature_count=num_entries_out; 11548 11549 return SOC_E_NONE; 11550 } 11551 11552 int 11553 soc_katana_show_ring_osc(int unit) 11554 { 11555 static char *names[] = { 11556 "IO ring 0", "IO ring 1", "Core ring 0", "Core ring 1" 11557 }; 11558 uint32 rval; 11559 int ring, div, quo, rem, frac; 11560 int cmc = SOC_PCI_CMC(unit); 11561 int core_clk = 133 * 1024; 11562 11563 for (ring = 0; ring < 4; ring++) { 11564 SOC_IF_ERROR_RETURN(READ_TOP_MISC_CONTROL_3r(unit, &rval)); 11565 soc_reg_field_set(unit, TOP_MISC_CONTROL_3r, &rval, OSC_ENABLEf, 1); 11566 soc_reg_field_set(unit, TOP_MISC_CONTROL_3r, &rval, OSC_SELf, ring); 11567 SOC_IF_ERROR_RETURN(WRITE_TOP_MISC_CONTROL_3r(unit, rval)); 11568 soc_reg_field_set(unit, TOP_MISC_CONTROL_3r, &rval, OSC_CNT_RSTBf, 1); 11569 SOC_IF_ERROR_RETURN(WRITE_TOP_MISC_CONTROL_3r(unit, rval)); 11570 soc_reg_field_set(unit, TOP_MISC_CONTROL_3r, &rval, OSC_CNT_STARTf, 1); 11571 SOC_IF_ERROR_RETURN(WRITE_TOP_MISC_CONTROL_3r(unit, rval)); 11572 11573 sal_usleep(1000); 11574 11575 rval = soc_pci_read(unit, CMIC_CMCx_IRQ_STAT3_OFFSET(cmc)); 11576 /* SOC_IF_ERROR_RETURN(READ_CMIC_CMC0_IRQ_STAT3r(unit, &rval)); */ 11577 div = rval & 0xffff; 11578 if (0 == div) { 11579 quo = 0; 11580 frac = 0; 11581 } else { 11582 quo = core_clk / div; 11583 rem = core_clk - quo * div; 11584 frac = (rem * 10000) / div; 11585 } 11586 LOG_CLI((BSL_META_U(unit, 11587 "%s: %d.%04d Mhz\n"), 11588 names[ring], quo, frac)); 11589 } 11590 11591 return SOC_E_NONE; 11592 } 11593 11594 STATIC int 11595 soc_kt_oam_interrupt_process(int unit) 11596 { 11597 uint32 irqStat; 11598 int rv = SOC_E_NONE; 11599 soc_field_t fault_field = 0; 11600 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, IP1_INTR_STATUS_1r, 11601 REG_PORT_ANY, 0, &irqStat)); 11602 if ((irqStat & KT_OAM_INTR_MASK) != 0) { 11603 if (en_oam_handler[unit] != NULL) { 11604 rv = en_oam_handler[unit](unit, fault_field); 11605 } 11606 } 11607 return rv; 11608 } 11609 11610 int 11611 soc_kt_lls_bmap_alloc(int unit) 11612 { 11613 soc_control_t *soc; 11614 int rv = SOC_E_NONE; 11615 int port; 11616 int alloc_size_l0, alloc_size_l1, alloc_size_l2; 11617 11618 soc = SOC_CONTROL(unit); 11619 11620 /* First cleanup if any allocation was done earlier. 11621 * This is needed to make sure that on subsequent rc 11622 * there is no memory leak due to MMU LLS usage bitmap 11623 * allocation. 11624 */ 11625 for (port = 0; port < SOC_MAX_NUM_PORTS; port++) { 11626 if (soc->port_lls_l0_bmap[port] != NULL) { 11627 sal_free(soc->port_lls_l0_bmap[port]); 11628 soc->port_lls_l0_bmap[port] = NULL; 11629 } 11630 if (soc->port_lls_l1_bmap[port] != NULL) { 11631 sal_free(soc->port_lls_l1_bmap[port]); 11632 soc->port_lls_l1_bmap[port] = NULL; 11633 } 11634 if (soc->port_lls_l2_bmap[port] != NULL) { 11635 sal_free(soc->port_lls_l2_bmap[port]); 11636 soc->port_lls_l2_bmap[port] = NULL; 11637 } 11638 } 11639 11640 alloc_size_l0 = 11641 SHR_BITALLOCSIZE(soc_mem_index_count(unit, LLS_L0_PARENTm)); 11642 alloc_size_l1 = 11643 SHR_BITALLOCSIZE(soc_mem_index_count(unit, LLS_L1_PARENTm)); 11644 alloc_size_l2 = 11645 SHR_BITALLOCSIZE(soc_mem_index_count(unit, LLS_L2_PARENTm)); 11646 11647 PBMP_ALL_ITER(unit, port) { 11648 soc->port_lls_l0_bmap[port] = sal_alloc(alloc_size_l0, "LLS_L0_BMAP"); 11649 if (soc->port_lls_l0_bmap[port] == NULL) { 11650 rv = SOC_E_MEMORY; 11651 goto clean_up; 11652 } 11653 soc->port_lls_l1_bmap[port] = sal_alloc(alloc_size_l1, "LLS_L1_BMAP"); 11654 if (soc->port_lls_l1_bmap[port] == NULL) { 11655 rv = SOC_E_MEMORY; 11656 goto clean_up; 11657 } 11658 soc->port_lls_l2_bmap[port] = sal_alloc(alloc_size_l2, "LLS_L2_BMAP"); 11659 if (soc->port_lls_l2_bmap[port] == NULL) { 11660 rv = SOC_E_MEMORY; 11661 goto clean_up; 11662 } 11663 sal_memset(soc->port_lls_l0_bmap[port], 0, alloc_size_l0); 11664 sal_memset(soc->port_lls_l1_bmap[port], 0, alloc_size_l1); 11665 sal_memset(soc->port_lls_l2_bmap[port], 0, alloc_size_l2); 11666 } 11667 11668 clean_up: 11669 if (SOC_FAILURE(rv)) { 11670 PBMP_ALL_ITER(unit, port) { 11671 if (soc->port_lls_l1_bmap[port] != NULL) { 11672 sal_free(soc->port_lls_l1_bmap[port]); 11673 soc->port_lls_l1_bmap[port] = NULL; 11674 } 11675 if (soc->port_lls_l0_bmap[port] != NULL) { 11676 sal_free(soc->port_lls_l0_bmap[port]); 11677 soc->port_lls_l0_bmap[port] = NULL; 11678 } 11679 if (soc->port_lls_l2_bmap[port] != NULL) { 11680 sal_free(soc->port_lls_l2_bmap[port]); 11681 soc->port_lls_l2_bmap[port] = NULL; 11682 } 11683 } 11684 } 11685 return rv; 11686 } 11687 11688 int 11689 soc_kt_port_flush_state_set(int unit, int port, int enable) 11690 { 11691 soc_pbmp_t port_flush_pbmp; 11692 11693 SOC_PBMP_CLEAR(port_flush_pbmp); 11694 if (enable) { 11695 SOC_LLS_SCHEDULER_LOCK(unit); 11696 port_flush_pbmp = SOC_CONTROL(unit)->port_flush_pbmp; 11697 SOC_PBMP_PORT_ADD(port_flush_pbmp, port); 11698 SOC_LLS_SCHEDULER_UNLOCK(unit); 11699 } else { 11700 SOC_LLS_SCHEDULER_LOCK(unit); 11701 SOC_PBMP_PORT_REMOVE(port_flush_pbmp, port); 11702 SOC_LLS_SCHEDULER_UNLOCK(unit); 11703 } 11704 return SOC_E_NONE; 11705 } 11706 11707 int soc_kt_port_flush_state_get(int unit, int port, int *mode) 11708 { 11709 soc_pbmp_t port_flush_pbmp; 11710 11711 SOC_PBMP_CLEAR(port_flush_pbmp); 11712 11713 port_flush_pbmp = SOC_CONTROL(unit)->port_flush_pbmp; 11714 if (SOC_PBMP_MEMBER(port_flush_pbmp, port)) { 11715 /* Port is in flush state */ 11716 *mode = 1; 11717 } else { 11718 /* Port is not in flush state */ 11719 *mode = 0; 11720 } 11721 return SOC_E_NONE; 11722 } 11723 11724 int 11725 soc_kt_cosq_max_bucket_set(int unit, int port, 11726 int index, uint32 level) 11727 { 11728 uint32 idx = 0; 11729 uint32 i = 0; 11730 lls_port_shaper_config_c_entry_t port_entry; 11731 lls_l0_shaper_config_c_entry_t l0_entry; 11732 lls_l1_shaper_config_c_entry_t l1_entry; 11733 lls_l2_shaper_config_lower_entry_t l2_entry; 11734 soc_mem_t config_mem[2]; 11735 static const soc_field_t rate_exp_fields[] = { 11736 C_MAX_REF_RATE_EXP_0f, C_MAX_REF_RATE_EXP_1f, 11737 C_MAX_REF_RATE_EXP_2f, C_MAX_REF_RATE_EXP_3f, 11738 C_MIN_REF_RATE_EXP_0f, C_MIN_REF_RATE_EXP_1f, 11739 C_MIN_REF_RATE_EXP_2f, C_MIN_REF_RATE_EXP_3f 11740 }; 11741 static const soc_field_t rate_mant_fields[] = { 11742 C_MAX_REF_RATE_MANT_0f, C_MAX_REF_RATE_MANT_1f, 11743 C_MAX_REF_RATE_MANT_2f, C_MAX_REF_RATE_MANT_3f, 11744 C_MIN_REF_RATE_MANT_0f, C_MIN_REF_RATE_MANT_1f, 11745 C_MIN_REF_RATE_MANT_2f, C_MIN_REF_RATE_MANT_3f 11746 }; 11747 static const soc_field_t burst_exp_fields[] = { 11748 C_MAX_THLD_EXP_0f, C_MAX_THLD_EXP_1f, 11749 C_MAX_THLD_EXP_2f, C_MAX_THLD_EXP_3f, 11750 C_MIN_THLD_EXP_0f, C_MIN_THLD_EXP_1f, 11751 C_MIN_THLD_EXP_2f, C_MIN_THLD_EXP_3f 11752 }; 11753 static const soc_field_t burst_mant_fields[] = { 11754 C_MAX_THLD_MANT_0f, C_MAX_THLD_MANT_1f, 11755 C_MAX_THLD_MANT_2f, C_MAX_THLD_MANT_3f, 11756 C_MIN_THLD_MANT_0f, C_MIN_THLD_MANT_1f, 11757 C_MIN_THLD_MANT_2f, C_MIN_THLD_MANT_3f 11758 }; 11759 static const soc_field_t cycle_sel_fields[] = { 11760 C_MAX_CYCLE_SEL_0f, C_MAX_CYCLE_SEL_1f, 11761 C_MAX_CYCLE_SEL_2f, C_MAX_CYCLE_SEL_3f, 11762 C_MIN_CYCLE_SEL_0f, C_MIN_CYCLE_SEL_1f, 11763 C_MIN_CYCLE_SEL_2f, C_MIN_CYCLE_SEL_3f 11764 }; 11765 11766 soc_field_t rate_exp_f[] = { 11767 C_MAX_REF_RATE_EXPf, C_MIN_REF_RATE_EXPf 11768 }; 11769 soc_field_t rate_mant_f[] = { 11770 C_MAX_REF_RATE_MANTf, C_MIN_REF_RATE_MANTf 11771 }; 11772 soc_field_t burst_exp_f[] = { 11773 C_MAX_THLD_EXPf, C_MIN_THLD_EXPf 11774 }; 11775 soc_field_t burst_mant_f[] = { 11776 C_MAX_THLD_MANTf, C_MIN_THLD_MANTf 11777 }; 11778 soc_field_t cycle_sel_f[] = { 11779 C_MAX_CYCLE_SELf, C_MIN_CYCLE_SELf 11780 }; 11781 11782 /* set Min/Max threshold shapers to 33Gbps */ 11783 switch (level) { 11784 case _SOC_KT_COSQ_NODE_LEVEL_ROOT: 11785 config_mem[0] = LLS_PORT_SHAPER_CONFIG_Cm; 11786 11787 sal_memset(&port_entry, 0, 11788 sizeof(lls_port_shaper_config_c_entry_t)); 11789 SOC_IF_ERROR_RETURN 11790 (soc_mem_read(unit, config_mem[0], MEM_BLOCK_ALL, 11791 index, &port_entry)); 11792 soc_mem_field32_set(unit, config_mem[0], &port_entry, 11793 rate_exp_f[0], KT_QUEUE_FLUSH_RATE_EXP); 11794 soc_mem_field32_set(unit, config_mem[0], &port_entry, 11795 rate_mant_f[0], KT_QUEUE_FLUSH_RATE_MANTISSA); 11796 soc_mem_field32_set(unit, config_mem[0], &port_entry, 11797 burst_exp_f[0], KT_QUEUE_FLUSH_BURST_EXP); 11798 soc_mem_field32_set(unit, config_mem[0], &port_entry, 11799 burst_mant_f[0], KT_QUEUE_FLUSH_BURST_MANTISSA); 11800 soc_mem_field32_set(unit, config_mem[0], &port_entry, 11801 cycle_sel_f[0], KT_QUEUE_FLUSH_CYCLE_SEL); 11802 SOC_IF_ERROR_RETURN 11803 (soc_mem_write(unit, config_mem[0], 11804 MEM_BLOCK_ALL, index, &port_entry)); 11805 break; 11806 case _SOC_KT_COSQ_NODE_LEVEL_L0: 11807 config_mem[0] = LLS_L0_SHAPER_CONFIG_Cm; 11808 config_mem[1] = LLS_L0_MIN_CONFIG_Cm; 11809 11810 for (i = 0; i < 2; i++) { 11811 sal_memset(&l0_entry, 0, 11812 sizeof(lls_l0_shaper_config_c_entry_t)); 11813 SOC_IF_ERROR_RETURN 11814 (soc_mem_read(unit, config_mem[i], MEM_BLOCK_ALL, 11815 index, &l0_entry)); 11816 soc_mem_field32_set(unit, config_mem[i], &l0_entry, 11817 rate_exp_f[i], KT_QUEUE_FLUSH_RATE_EXP); 11818 soc_mem_field32_set(unit, config_mem[i], &l0_entry, 11819 rate_mant_f[i], KT_QUEUE_FLUSH_RATE_MANTISSA); 11820 soc_mem_field32_set(unit, config_mem[i], &l0_entry, 11821 burst_exp_f[i], KT_QUEUE_FLUSH_BURST_EXP); 11822 soc_mem_field32_set(unit, config_mem[i], &l0_entry, 11823 burst_mant_f[i], KT_QUEUE_FLUSH_BURST_MANTISSA); 11824 soc_mem_field32_set(unit, config_mem[i], &l0_entry, 11825 cycle_sel_f[i], KT_QUEUE_FLUSH_CYCLE_SEL); 11826 SOC_IF_ERROR_RETURN 11827 (soc_mem_write(unit, config_mem[i], 11828 MEM_BLOCK_ALL, index, &l0_entry)); 11829 } 11830 break; 11831 case _SOC_KT_COSQ_NODE_LEVEL_L1: 11832 config_mem[0] = LLS_L1_SHAPER_CONFIG_Cm; 11833 config_mem[1] = LLS_L1_MIN_CONFIG_Cm; 11834 11835 for (i = 0; i < 2; i++) { 11836 sal_memset(&l1_entry, 0, 11837 sizeof(lls_l1_shaper_config_c_entry_t)); 11838 idx = (i * 4) + (index % 4); 11839 SOC_IF_ERROR_RETURN 11840 (soc_mem_read(unit, config_mem[i], MEM_BLOCK_ALL, 11841 index/4, &l1_entry)); 11842 soc_mem_field32_set(unit, config_mem[i], &l1_entry, 11843 rate_exp_fields[idx], KT_QUEUE_FLUSH_RATE_EXP); 11844 soc_mem_field32_set(unit, config_mem[i], &l1_entry, 11845 rate_mant_fields[idx], KT_QUEUE_FLUSH_RATE_MANTISSA); 11846 soc_mem_field32_set(unit, config_mem[i], &l1_entry, 11847 burst_exp_fields[idx], KT_QUEUE_FLUSH_BURST_EXP); 11848 soc_mem_field32_set(unit, config_mem[i], &l1_entry, 11849 burst_mant_fields[idx], KT_QUEUE_FLUSH_BURST_MANTISSA); 11850 soc_mem_field32_set(unit, config_mem[i], &l1_entry, 11851 cycle_sel_fields[idx], KT_QUEUE_FLUSH_CYCLE_SEL); 11852 SOC_IF_ERROR_RETURN 11853 (soc_mem_write(unit, config_mem[i], 11854 MEM_BLOCK_ALL, index/4, &l1_entry)); 11855 } 11856 break; 11857 case _SOC_KT_COSQ_NODE_LEVEL_L2: 11858 if ((index % 8) < 4) { 11859 config_mem[0] = LLS_L2_SHAPER_CONFIG_LOWERm; 11860 config_mem[1] = LLS_L2_MIN_CONFIG_LOWER_Cm; 11861 } else { 11862 config_mem[0] = LLS_L2_SHAPER_CONFIG_UPPERm; 11863 config_mem[1] = LLS_L2_MIN_CONFIG_UPPER_Cm; 11864 } 11865 11866 for ( i = 0; i < 2; i++) { 11867 idx = (i * 4) + (index % 4); 11868 11869 sal_memset(&l2_entry, 0, 11870 sizeof(lls_l2_shaper_config_lower_entry_t)); 11871 SOC_IF_ERROR_RETURN 11872 (soc_mem_read(unit, config_mem[i], MEM_BLOCK_ALL, 11873 index/8, &l2_entry)); 11874 soc_mem_field32_set(unit, config_mem[i], &l2_entry, 11875 rate_exp_fields[idx], KT_QUEUE_FLUSH_RATE_EXP); 11876 soc_mem_field32_set(unit, config_mem[i], &l2_entry, 11877 rate_mant_fields[idx], KT_QUEUE_FLUSH_RATE_MANTISSA); 11878 soc_mem_field32_set(unit, config_mem[i], &l2_entry, 11879 burst_exp_fields[idx], KT_QUEUE_FLUSH_BURST_EXP); 11880 soc_mem_field32_set(unit, config_mem[i], &l2_entry, 11881 burst_mant_fields[idx], KT_QUEUE_FLUSH_BURST_MANTISSA); 11882 soc_mem_field32_set(unit, config_mem[i], &l2_entry, 11883 cycle_sel_fields[idx], KT_QUEUE_FLUSH_CYCLE_SEL); 11884 SOC_IF_ERROR_RETURN 11885 (soc_mem_write(unit, config_mem[i], 11886 MEM_BLOCK_ALL, index/8, &l2_entry)); 11887 } 11888 break; 11889 default: 11890 return SOC_E_NONE; 11891 11892 } 11893 11894 return SOC_E_NONE; 11895 11896 } 11897 11898 int 11899 _soc_kt_cosq_begin_port_flush(int unit, int port, int hw_index) 11900 { 11901 uint32 rval = 0; 11902 uint32 ext_mem = 0; 11903 int flush_active = 0; 11904 uint32 timeout_val; 11905 soc_timeout_t timeout; 11906 11907 if (IS_EXT_MEM_PORT(unit, port)) { 11908 ext_mem = 1; 11909 } 11910 11911 11912 SOC_IF_ERROR_RETURN(READ_TOQ_QUEUE_FLUSH0r(unit, &rval)); 11913 11914 soc_reg_field_set(unit, TOQ_QUEUE_FLUSH0r, &rval, Q_FLUSH_NUMf,1); 11915 soc_reg_field_set(unit, TOQ_QUEUE_FLUSH0r, 11916 &rval, Q_FLUSH_ID0f, hw_index); 11917 soc_reg_field_set(unit, TOQ_QUEUE_FLUSH0r, &rval, Q_FLUSH_EXTERNALf, 11918 ext_mem); 11919 soc_reg_field_set(unit, TOQ_QUEUE_FLUSH0r, &rval, Q_FLUSH_ACTIVEf, 1); 11920 SOC_IF_ERROR_RETURN(WRITE_TOQ_QUEUE_FLUSH0r(unit, rval)); 11921 11922 11923 /* Wait for flush completion */ 11924 flush_active = 1; 11925 timeout_val = soc_property_get(unit, spn_MMU_QUEUE_FLUSH_TIMEOUT, 1600000); 11926 soc_timeout_init(&timeout, timeout_val, 0); 11927 11928 while (flush_active) { 11929 if (SOC_REG_IS_VALID(unit, TOQ_QUEUE_FLUSH0r)) { 11930 SOC_IF_ERROR_RETURN(READ_TOQ_QUEUE_FLUSH0r(unit, &rval)); 11931 flush_active = soc_reg_field_get(unit, TOQ_QUEUE_FLUSH0r, rval, 11932 Q_FLUSH_ACTIVEf); 11933 } 11934 11935 if (soc_timeout_check(&timeout)) { 11936 LOG_ERROR(BSL_LS_SOC_COMMON, 11937 (BSL_META_U(unit, 11938 "ERROR: Port %d Queue flush operation failed for queue %d \n"), 11939 port, hw_index)); 11940 return (SOC_E_TIMEOUT); 11941 11942 } 11943 } 11944 return SOC_E_NONE; 11945 } 11946 11947 int 11948 _soc_kt_cosq_end_port_flush(int unit, int hw_index) 11949 { 11950 uint32 rval = 0, q_bmp; 11951 11952 KT_COSQ_LOCK(unit); 11953 11954 soc_reg_field_set(unit, THDO_QUEUE_DISABLE_CFG2r, &rval, QUEUE_NUMf, 11955 (hw_index & 0xfe0)); 11956 SOC_IF_ERROR_RETURN(WRITE_THDO_QUEUE_DISABLE_CFG2r(unit, rval)); 11957 11958 SOC_IF_ERROR_RETURN(READ_THDO_QUEUE_DISABLE_CFG1r(unit, &rval)); 11959 soc_reg_field_set(unit, THDO_QUEUE_DISABLE_CFG1r, &rval, QUEUE_RDf, 1); 11960 SOC_IF_ERROR_RETURN(WRITE_THDO_QUEUE_DISABLE_CFG1r(unit, rval)); 11961 11962 SOC_IF_ERROR_RETURN(READ_THDO_QUEUE_DISABLE_STATUSr(unit, &rval)); 11963 q_bmp = soc_reg_field_get(unit, THDO_QUEUE_DISABLE_STATUSr, rval, 11964 QUEUE_BITMAPf); 11965 11966 if (q_bmp & (1 << (hw_index % 32))) { 11967 SOC_IF_ERROR_RETURN(READ_THDO_QUEUE_DISABLE_CFG2r(unit, &rval)); 11968 soc_reg_field_set(unit, THDO_QUEUE_DISABLE_CFG2r, &rval, QUEUE_NUMf, 11969 hw_index ); 11970 SOC_IF_ERROR_RETURN(WRITE_THDO_QUEUE_DISABLE_CFG2r(unit, rval)); 11971 11972 SOC_IF_ERROR_RETURN(READ_THDO_QUEUE_DISABLE_CFG1r(unit, &rval)); 11973 soc_reg_field_set(unit, THDO_QUEUE_DISABLE_CFG1r, &rval, QUEUE_WRf, 1); 11974 SOC_IF_ERROR_RETURN(WRITE_THDO_QUEUE_DISABLE_CFG1r(unit, rval)); 11975 } 11976 11977 KT_COSQ_UNLOCK(unit); 11978 return SOC_E_NONE; 11979 } 11980 int soc_kt_port_flush(int unit, int port, int enable) 11981 { 11982 soc_mem_t mem; 11983 uint32 *bmap; 11984 int index, word, bit, word_count, index_count, count; 11985 /* for queue flush */ 11986 bmap = SOC_CONTROL(unit)->port_lls_l2_bmap[port]; 11987 mem = LLS_L2_PARENTm; 11988 index_count = soc_mem_index_count(unit, mem); 11989 word_count = _SHR_BITDCLSIZE(index_count); 11990 count = 0; 11991 11992 for (word = (word_count - 1); word >= 0; word--) { 11993 if (bmap[word] == 0) { 11994 continue; 11995 } 11996 for (bit = (SHR_BITWID - 1); bit >= 0; bit--) { 11997 if (!(bmap[word] & (1 << bit))) { 11998 continue; 11999 } 12000 index = word * SHR_BITWID + bit; 12001 count++; 12002 12003 if (enable == 1) { 12004 /* Set the threshold for L2 node to max shaper rate - 33 Gbps */ 12005 #ifdef BCM_SABER2_SUPPORT 12006 if (SOC_IS_SABER2(unit)) { 12007 SOC_IF_ERROR_RETURN 12008 (soc_sb2_cosq_max_bucket_set(unit, port, 12009 index, 12010 _SOC_KT2_COSQ_NODE_LVL_L2)); 12011 /* Flush the queues */ 12012 SOC_IF_ERROR_RETURN(_soc_kt2_cosq_begin_port_flush( 12013 unit, port, index)); 12014 12015 } else 12016 #endif 12017 #ifdef BCM_KATANA2_SUPPORT 12018 if (SOC_IS_KATANA2(unit)) { 12019 SOC_IF_ERROR_RETURN 12020 (soc_kt2_cosq_max_bucket_set(unit, port, 12021 index, 12022 _SOC_KT2_COSQ_NODE_LVL_L2)); 12023 /* Flush the queues */ 12024 SOC_IF_ERROR_RETURN(_soc_kt2_cosq_begin_port_flush( 12025 unit, port, index)); 12026 } else 12027 #endif 12028 { 12029 SOC_IF_ERROR_RETURN 12030 (soc_kt_cosq_max_bucket_set(unit, port, index, 12031 _SOC_KT_COSQ_NODE_LEVEL_L2)); 12032 /* Flush the queues */ 12033 SOC_IF_ERROR_RETURN(_soc_kt_cosq_begin_port_flush( 12034 unit, port, index)); 12035 } 12036 } else { 12037 #ifdef BCM_KATANA2_SUPPORT 12038 if (SOC_IS_KATANA2(unit) || SOC_IS_SABER2(unit)) { 12039 SOC_IF_ERROR_RETURN 12040 (_soc_kt2_cosq_end_port_flush( 12041 unit, index)); 12042 } else 12043 #endif 12044 { 12045 /* Enable the queues */ 12046 SOC_IF_ERROR_RETURN(_soc_kt_cosq_end_port_flush( 12047 unit, index)); 12048 } 12049 } 12050 } 12051 } 12052 12053 return SOC_E_NONE; 12054 } 12055 12056 int 12057 soc_kt_sched_get_node_config(int unit, soc_port_t port, int level, int index, 12058 int *pnum_spri, int *pfirst_child, 12059 uint32 *pspmap) 12060 { 12061 uint32 entry[SOC_MAX_MEM_WORDS]; 12062 soc_mem_t mem; 12063 uint32 num_spri = 0, f1, f2; 12064 int first_child = -1, ii; 12065 int sp_vec = soc_feature(unit, soc_feature_vector_based_spri); 12066 12067 *pspmap = 0; 12068 12069 mem = _SOC_KT_NODE_CONFIG_MEM(level); 12070 if (mem == INVALIDm) { 12071 return SOC_E_INTERNAL; 12072 } 12073 SOC_IF_ERROR_RETURN(soc_mem_read(unit, mem, MEM_BLOCK_ALL, index, &entry)); 12074 if (sp_vec) { 12075 f1 = soc_mem_field32_get(unit, mem, &entry, P_NUM_SPRIf); 12076 f2 = soc_mem_field32_get(unit, mem, &entry, P_VECT_SPRI_7_4f); 12077 *pspmap = f1 | (f2 << 4); 12078 for (ii = 0; ii < 32; ii++) { 12079 if ((1 << ii) & *pspmap) { 12080 num_spri++; 12081 } 12082 } 12083 } else { 12084 num_spri = soc_mem_field32_get(unit, mem, &entry, P_NUM_SPRIf); 12085 } 12086 first_child = soc_mem_field32_get(unit, mem, &entry, P_START_SPRIf); 12087 12088 if (pnum_spri) { 12089 *pnum_spri = num_spri; 12090 } 12091 12092 if (pfirst_child) { 12093 *pfirst_child = first_child; 12094 } 12095 return SOC_E_NONE; 12096 } 12097 12098 STATIC int 12099 soc_kt_sched_weight_get(int unit, int level, int index, int *weight) 12100 { 12101 soc_mem_t mem_weight; 12102 uint32 entry[SOC_MAX_MEM_WORDS]; 12103 12104 mem_weight = _SOC_KT_NODE_WIEGHT_MEM(level); 12105 12106 SOC_IF_ERROR_RETURN 12107 (soc_mem_read(unit, mem_weight, MEM_BLOCK_ALL, index, &entry)); 12108 12109 *weight = soc_mem_field32_get(unit, mem_weight, &entry, C_WEIGHTf); 12110 LOG_INFO(BSL_LS_SOC_COSQ, 12111 (BSL_META_U(unit, 12112 "sched_weight_get L%d index=%d wt=%d\n"), 12113 level, index, *weight)); 12114 return SOC_E_NONE; 12115 } 12116 12117 int 12118 soc_kt_cosq_get_sched_mode(int unit, soc_port_t port, int level, int index, 12119 soc_kt_sched_mode_e *pmode, int *weight) 12120 { 12121 uint32 entry[SOC_MAX_MEM_WORDS]; 12122 soc_mem_t mem; 12123 soc_kt_sched_mode_e mode = SOC_KT_SCHED_MODE_UNKNOWN; 12124 12125 SOC_IF_ERROR_RETURN(soc_kt_sched_weight_get(unit, level, index, weight)); 12126 12127 if (*weight == 0) { 12128 mode = SOC_KT_SCHED_MODE_STRICT; 12129 } else { 12130 mem = _SOC_KT_NODE_CONFIG_MEM(_SOC_KT_COSQ_NODE_LEVEL_ROOT); 12131 if (port > 41){ 12132 mem = LLS_S1_CONFIGm; 12133 } 12134 index = port; 12135 SOC_IF_ERROR_RETURN( 12136 soc_mem_read(unit, mem, MEM_BLOCK_ALL, index, &entry)); 12137 if (soc_mem_field32_get(unit, mem, entry, PACKET_MODE_WRR_ACCOUNTING_ENABLEf)) { 12138 mode = SOC_KT_SCHED_MODE_WRR; 12139 } else { 12140 mode = SOC_KT_SCHED_MODE_WDRR; 12141 } 12142 } 12143 12144 if (pmode) { 12145 *pmode = mode; 12146 } 12147 12148 return SOC_E_NONE; 12149 } 12150 12151 #define _KT_INDEX_1K_ENTRIES 1023 12152 #define _KT_OFFSET_1K_ENTRIES 1024 12153 #define _KT_INDEX_2K_ENTRIES 2047 12154 #define _KT_OFFSET_2K_ENTRIES 2048 12155 #define _KT_INDEX_3K_ENTRIES 3071 12156 #define _KT_OFFSET_3K_ENTRIES 3072 12157 12158 STATIC int 12159 _soc_katana_l3_defip_urpf_index_map(int unit, int wide, int index) 12160 { 12161 int new_index = index; 12162 int num_tcams = 0; 12163 int tcam_size = SOC_L3_DEFIP_TCAM_DEPTH_GET(unit); 12164 int entries_left_in_paired_tcam = 0; 12165 int soc_defip_index_remap = SOC_L3_DEFIP_INDEX_REMAP_GET(unit) / 2; 12166 12167 if (wide == 0) { 12168 num_tcams = soc_defip_index_remap / tcam_size; 12169 entries_left_in_paired_tcam = tcam_size - 12170 (soc_defip_index_remap % tcam_size); 12171 if (index < entries_left_in_paired_tcam) { 12172 new_index = index + (num_tcams * 2 * tcam_size) + 12173 (soc_defip_index_remap % tcam_size); 12174 } else if (index < 2 * entries_left_in_paired_tcam) { 12175 new_index = index + (num_tcams * 2 * tcam_size) + 12176 ((soc_defip_index_remap % tcam_size) * 2); 12177 } else if (index < 3 * entries_left_in_paired_tcam) { 12178 new_index = index + (num_tcams * 2 * tcam_size) + 12179 ((soc_defip_index_remap % tcam_size) * 3); 12180 } else { 12181 new_index = index + (num_tcams * 2 * tcam_size) + 12182 ((soc_defip_index_remap % tcam_size) * 4); 12183 } 12184 return new_index; 12185 } 12186 if (index >= soc_defip_index_remap) { 12187 new_index = index + tcam_size - soc_defip_index_remap; 12188 } 12189 return new_index; 12190 } 12191 12192 STATIC int 12193 _soc_katana_l3_defip_urpf_index_remap(int unit, int wide, int index) 12194 { 12195 int new_index = index; 12196 int num_tcams = 0; 12197 int tcam_size = SOC_L3_DEFIP_TCAM_DEPTH_GET(unit); 12198 int soc_defip_index_remap = SOC_L3_DEFIP_INDEX_REMAP_GET(unit) / 2; 12199 12200 if (wide == 0) { 12201 num_tcams = soc_defip_index_remap / tcam_size; 12202 12203 if (index > _KT_INDEX_3K_ENTRIES + soc_defip_index_remap % tcam_size) { 12204 new_index = (index - (num_tcams * 2 * tcam_size)) - 12205 (soc_defip_index_remap % tcam_size) * 4; 12206 } else if (index > _KT_INDEX_2K_ENTRIES + soc_defip_index_remap % tcam_size) { 12207 new_index = (index - (num_tcams * 2 * tcam_size)) - 12208 (soc_defip_index_remap % tcam_size) * 3; 12209 } else if (index > _KT_INDEX_1K_ENTRIES + soc_defip_index_remap % tcam_size) { 12210 new_index = (index - (num_tcams * 2 * tcam_size)) - 12211 (soc_defip_index_remap % tcam_size) * 2; 12212 } else { 12213 new_index = (index - (num_tcams * 2 * tcam_size)) - 12214 soc_defip_index_remap % tcam_size; 12215 } 12216 return new_index; 12217 } 12218 if (index >= _KT_OFFSET_1K_ENTRIES) { 12219 new_index = index - _KT_OFFSET_1K_ENTRIES + soc_defip_index_remap; 12220 } 12221 return new_index; 12222 } 12223 12224 12225 /* Map logical (always starts from 0 and contiguous) index to physical index 12226 which can have a starting offset and/or holes. 12227 Input : logical index 12228 Returns: physical index */ 12229 int 12230 soc_kt_l3_defip_index_map(int unit, soc_mem_t mem, int index) 12231 { 12232 int wide = 0; 12233 12234 if (SOC_CONTROL(unit)->l3_defip_index_remap == 0) { 12235 return index; 12236 } 12237 12238 if (mem == L3_DEFIP_PAIR_128m || 12239 mem == L3_DEFIP_PAIR_128_ONLYm || 12240 mem == L3_DEFIP_PAIR_128_DATA_ONLYm || 12241 mem == L3_DEFIP_PAIR_128_HIT_ONLYm) { 12242 wide = 1; 12243 } 12244 if (SOC_CONTROL(unit)->l3_defip_urpf) { 12245 return _soc_katana_l3_defip_urpf_index_map(unit, wide, index); 12246 } else { 12247 return soc_l3_defip_index_map(unit, wide, index); 12248 } 12249 } 12250 12251 /* Reverse map physical index to logical index. 12252 Input : physical index 12253 Returns: logical index */ 12254 int 12255 soc_kt_l3_defip_index_remap(int unit, soc_mem_t mem, int index) 12256 { 12257 int wide = 0; 12258 12259 if (SOC_CONTROL(unit)->l3_defip_index_remap == 0) { 12260 return index; 12261 } 12262 12263 if (mem == L3_DEFIP_PAIR_128m || 12264 mem == L3_DEFIP_PAIR_128_ONLYm || 12265 mem == L3_DEFIP_PAIR_128_DATA_ONLYm || 12266 mem == L3_DEFIP_PAIR_128_HIT_ONLYm) { 12267 wide = 1; 12268 } 12269 if (SOC_CONTROL(unit)->l3_defip_urpf) { 12270 return _soc_katana_l3_defip_urpf_index_remap(unit, wide, index); 12271 } else { 12272 return soc_l3_defip_index_remap(unit, wide, index); 12273 } 12274 } 12275 12276 /* Given a physical index (always in terms of the narrow entry) 12277 return the logical index and memory type */ 12278 int 12279 soc_kt_l3_defip_mem_index_get(int unit, int pindex, soc_mem_t *mem) 12280 { 12281 int soc_defip_index_remap = SOC_L3_DEFIP_INDEX_REMAP_GET(unit) / 2; 12282 12283 *mem = L3_DEFIPm; 12284 if (SOC_CONTROL(unit)->l3_defip_urpf) { 12285 if (SOC_CONTROL(unit)->l3_defip_index_remap == 0) { 12286 *mem = L3_DEFIPm; 12287 return pindex; 12288 } 12289 if (pindex < soc_defip_index_remap) { 12290 *mem = L3_DEFIP_PAIR_128m; 12291 return pindex; 12292 } else if ((pindex > _KT_INDEX_1K_ENTRIES) && 12293 (pindex < _KT_OFFSET_1K_ENTRIES + soc_defip_index_remap)) { 12294 *mem = L3_DEFIP_PAIR_128m; 12295 return pindex - _KT_OFFSET_1K_ENTRIES; 12296 } else if ((pindex > _KT_INDEX_2K_ENTRIES) && 12297 (pindex < _KT_OFFSET_2K_ENTRIES + soc_defip_index_remap)) { 12298 *mem = L3_DEFIP_PAIR_128m; 12299 return pindex - _KT_OFFSET_2K_ENTRIES + soc_defip_index_remap; 12300 } else if ((pindex > _KT_INDEX_3K_ENTRIES) && 12301 (pindex < _KT_OFFSET_3K_ENTRIES + soc_defip_index_remap)) { 12302 *mem = L3_DEFIP_PAIR_128m; 12303 return pindex - _KT_OFFSET_3K_ENTRIES + soc_defip_index_remap; 12304 } else { 12305 *mem = L3_DEFIPm; 12306 return _soc_katana_l3_defip_urpf_index_remap(unit, 0, pindex); 12307 } 12308 12309 } else { 12310 if (SOC_CONTROL(unit)->l3_defip_index_remap == 0) { 12311 *mem = L3_DEFIPm; 12312 return pindex; 12313 } 12314 return soc_l3_defip_index_mem_map(unit, pindex, mem); 12315 } 12316 } 12317 12318 #define _SOC_KT_DEFIP_MAX_TCAMS 6 12319 #define _SOC_KT_DEFIP_TCAM_DEPTH 1024 12320 int 12321 soc_kt_mem_config(int unit, int dev_id) 12322 { 12323 int rv = SOC_E_NONE; 12324 int num_ipv6_128b_entries = 0; 12325 int config_v6_entries = 0; 12326 int defip_config = 0; 12327 soc_persist_t *sop = SOC_PERSIST(unit); 12328 switch (dev_id) { 12329 case BCM56240_DEVICE_ID: 12330 case BCM56241_DEVICE_ID: 12331 case BCM56242_DEVICE_ID: 12332 case BCM56243_DEVICE_ID: 12333 case BCM56245_DEVICE_ID: 12334 case BCM56246_DEVICE_ID: 12335 SOC_CONTROL(unit)->l3_defip_max_tcams = _SOC_KT_DEFIP_MAX_TCAMS/3; 12336 break; 12337 default: 12338 SOC_CONTROL(unit)->l3_defip_max_tcams = _SOC_KT_DEFIP_MAX_TCAMS; 12339 break; 12340 } 12341 SOC_CONTROL(unit)->l3_defip_tcam_size = _SOC_KT_DEFIP_TCAM_DEPTH; 12342 if (soc_property_get(unit, "l3_defip_sizing", TRUE)) { 12343 defip_config = soc_property_get(unit, spn_IPV6_LPM_128B_ENABLE, 0); 12344 12345 num_ipv6_128b_entries = 12346 soc_property_get(unit, spn_NUM_IPV6_LPM_128B_ENTRIES, 12347 (defip_config ? 1024 : 0)); 12348 12349 config_v6_entries = num_ipv6_128b_entries; 12350 12351 sop->memState[L3_DEFIP_PAIR_128m].index_max = 12352 num_ipv6_128b_entries - 1; 12353 sop->memState[L3_DEFIP_PAIR_128_ONLYm].index_max = 12354 num_ipv6_128b_entries - 1; 12355 sop->memState[L3_DEFIP_PAIR_128_DATA_ONLYm].index_max = 12356 num_ipv6_128b_entries - 1; 12357 sop->memState[L3_DEFIP_PAIR_128_HIT_ONLYm].index_max = 12358 num_ipv6_128b_entries - 1; 12359 sop->memState[L3_DEFIPm].index_max = 12360 (SOC_CONTROL(unit)->l3_defip_max_tcams * 12361 SOC_CONTROL(unit)->l3_defip_tcam_size) - 12362 (num_ipv6_128b_entries * 2) - 1; 12363 sop->memState[L3_DEFIP_ONLYm].index_max = 12364 sop->memState[L3_DEFIPm].index_max; 12365 sop->memState[L3_DEFIP_DATA_ONLYm].index_max = 12366 sop->memState[L3_DEFIPm].index_max; 12367 sop->memState[L3_DEFIP_HIT_ONLYm].index_max = 12368 sop->memState[L3_DEFIPm].index_max; 12369 SOC_CONTROL(unit)->l3_defip_index_remap = num_ipv6_128b_entries; 12370 soc_l3_defip_indexes_init(unit, config_v6_entries); 12371 } 12372 return rv; 12373 } 12374 12375 12376 #endif /* BCM_KATANA_SUPPORT */