ser.c (161179B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: ser.c 8 * Purpose: SER enable/detect and test functionality. 9 * Requires: 10 */ 11 #include <shared/bsl.h> 12 #include <soc/drv.h> 13 #include <soc/error.h> 14 #include <soc/debug.h> 15 #include <soc/mem.h> 16 #include <soc/hurricane3.h> 17 18 /* Internal Use Only : Individually Test Purpose */ 19 #define _HR3_SER_TEST_MMU (1) 20 #define _HR3_SER_TEST_TCAM (1) 21 #define _HR3_SER_TEST_EP (1) 22 #define _HR3_SER_TEST_IP0 (1) 23 #define _HR3_SER_TEST_IP1 (1) 24 #define _HR3_SER_TEST_IP2 (1) 25 26 /* 27 * Chip specific SER information. 28 */ 29 static soc_ser_functions_t _hr3_ser_functions; 30 31 #define _SOC_SER_SKIP_HR3L (0x1 << 0) 32 #define _SOC_SER_SKIP_FH2 (0x1 << 1) 33 #define _SOC_SER_SKIP_BH (0x1 << 2) 34 #define _SOC_SER_SKIP_WH2 (0x1 << 3) 35 36 typedef enum { 37 _SOC_PARITY_TYPE_NONE, 38 _SOC_PARITY_TYPE_ECC, 39 _SOC_PARITY_TYPE_PARITY, 40 _SOC_PARITY_TYPE_PARITY_DUAL, 41 _SOC_PARITY_TYPE_COUNTER, 42 _SOC_PARITY_TYPE_PORT_XL, 43 _SOC_PARITY_TYPE_MMU_SER, 44 _SOC_PARITY_TYPE_MMU_ECC, 45 _SOC_PARITY_TYPE_MMU_ECC_CBPH,/* 2-level ecc */ 46 _SOC_PARITY_TYPE_MMU_ECC_XQ, /* 2-level ecc */ 47 _SOC_PARITY_TYPE_MMU_PAR_E2EFC, /* par*/ 48 _SOC_PARITY_TYPE_MMU_PAR_WRED,/* 2-level par */ 49 _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP,/* 2-level ecc_correctable */ 50 _SOC_PARITY_TYPE_MMU_ECC_IPMCVLAN, /* ecc_correctable */ 51 _SOC_PARITY_TYPE_SER 52 } _soc_hr3_ser_info_type_t; 53 54 typedef struct _soc_hr3_ser_reg_s { 55 soc_reg_t reg; 56 char *str; 57 soc_mem_t mem; 58 } _soc_hr3_ser_reg_t; 59 60 typedef struct _soc_hr3_ser_info_s { 61 _soc_hr3_ser_info_type_t type; 62 struct _soc_hr3_ser_info_s *info; /* used for MMU */ 63 /* registers sets for parity/ecc group related */ 64 soc_field_t group_reg_enable_field; 65 soc_field_t group_reg_status_field; 66 soc_mem_t mem; 67 char *mem_str; 68 /* registers sets for parity/ecc enable*/ 69 soc_reg_t enable_reg; 70 soc_field_t enable_field; 71 soc_field_t *enable_field_list; 72 /* registers sets for parity/ecc interrupt related */ 73 soc_reg_t intr_enable_reg; 74 soc_field_t intr_enable_field; 75 soc_field_t *intr_enable_field_list; 76 soc_reg_t intr_status_reg; 77 _soc_hr3_ser_reg_t *intr_status_reg_list; 78 soc_field_t intr_status_field; 79 soc_reg_t intr_clr_reg; 80 soc_field_t intr_clr_field; 81 soc_reg_t intr2_valid_reg; 82 soc_reg_t intr2_multi_err_reg; 83 soc_reg_t intr2_clr_reg; 84 uint32 sku_skip; 85 }_soc_hr3_ser_info_t; 86 87 #if _HR3_SER_TEST_IP0 88 static _soc_hr3_ser_reg_t vlan_xlate_regs[] = { 89 { VLAN_XLATE_PARITY_STATUS_0r, "",INVALIDm}, 90 { VLAN_XLATE_PARITY_STATUS_1r, "",INVALIDm}, 91 { INVALIDr } 92 }; 93 #endif /* _HR3_SER_TEST_IP0 */ 94 #if _HR3_SER_TEST_IP1 95 static _soc_hr3_ser_reg_t l3_entry_regs[] = { 96 { L3_ENTRY_PARITY_STATUS_0r, "",INVALIDm}, 97 { L3_ENTRY_PARITY_STATUS_1r, "",INVALIDm}, 98 { INVALIDr } 99 }; 100 static _soc_hr3_ser_reg_t l2_entry_regs[] = { 101 { L2_ENTRY_PARITY_STATUS_0r, "",INVALIDm}, 102 { L2_ENTRY_PARITY_STATUS_1r, "",INVALIDm}, 103 { INVALIDr } 104 }; 105 #endif /* _HR3_SER_TEST_IP1 */ 106 #if _HR3_SER_TEST_EP 107 static _soc_hr3_ser_reg_t egr_vlan_xlate_regs[] = { 108 { EGR_VLAN_XLATE_PARITY_STATUS_0r, "",INVALIDm}, 109 { EGR_VLAN_XLATE_PARITY_STATUS_1r, "",INVALIDm}, 110 { INVALIDr } 111 }; 112 #endif /* _HR3_SER_TEST_EP */ 113 static _soc_hr3_ser_info_t _soc_hr3_ip0_ser_info[] = { 114 #if _HR3_SER_TEST_IP0 115 { _SOC_PARITY_TYPE_PARITY, NULL, 116 PORT_TABLE_1BIT_ERR_INTRf, PORT_TABLE_1BIT_ERR_INTRf, 117 PORT_TABm, NULL, 118 PORT_TABLE_ECC_CONTROLr, ECC_ENf, NULL, 119 INVALIDr, INVALIDf, NULL, 120 PORT_TABLE_PARITY_STATUS_INTRr, NULL, PARITY_ERRf, 121 INVALIDr, INVALIDf, 122 INVALIDr, INVALIDr, INVALIDr, 123 0 124 }, 125 { _SOC_PARITY_TYPE_ECC, NULL, 126 PORT_TABLE_ECC_INTRf, PORT_TABLE_ECC_INTRf, 127 INVALIDm, NULL, 128 PORT_TABLE_ECC_CONTROLr, ECC_ENf, NULL, 129 INVALIDr, INVALIDf, NULL, 130 PORT_TABLE_ECC_STATUS_INTRr, NULL, ECC_ERRf, 131 INVALIDr, INVALIDf, 132 INVALIDr, INVALIDr, INVALIDr, 133 0 134 }, 135 { _SOC_PARITY_TYPE_PARITY, NULL, 136 SYSTEM_CONFIG_PAR_ERRf, SYSTEM_CONFIG_PAR_ERRf, 137 SYSTEM_CONFIG_TABLEm, NULL, 138 SYSTEM_CONFIG_TABLE_PARITY_CONTROLr, PARITY_ENf, NULL, 139 INVALIDr, INVALIDf, NULL, 140 SYSTEM_CONFIG_TABLE_PARITY_STATUSr, NULL, INVALIDf, 141 INVALIDr, INVALIDf, 142 INVALIDr, INVALIDr, INVALIDr, 143 0 144 }, 145 { _SOC_PARITY_TYPE_PARITY, NULL, 146 SYSTEM_CONFIG_MODBASE_PAR_ERRf, SYSTEM_CONFIG_MODBASE_PAR_ERRf, 147 SYSTEM_CONFIG_TABLE_MODBASEm, NULL, 148 SYSTEM_CONFIG_TABLE_MODBASE_PARITY_CONTROLr, PARITY_ENf, NULL, 149 INVALIDr, INVALIDf, NULL, 150 SYSTEM_CONFIG_TABLE_MODBASE_PARITY_STATUSr, NULL, INVALIDf, 151 INVALIDr, INVALIDf, 152 INVALIDr, INVALIDr, INVALIDr, 153 0 154 }, 155 { _SOC_PARITY_TYPE_PARITY, NULL, 156 SOURCE_TRUNK_MAP_PARITY_ERRf, SOURCE_TRUNK_MAP_PARITY_ERRf, 157 SOURCE_TRUNK_MAP_TABLEm, NULL, 158 SOURCE_TRUNK_MAP_PARITY_CONTROLr, PARITY_ENf, NULL, 159 INVALIDr, INVALIDf, NULL, 160 SOURCE_TRUNK_MAP_PARITY_STATUSr, NULL, INVALIDf, 161 INVALIDr, INVALIDf, 162 INVALIDr, INVALIDr, INVALIDr, 163 0 164 }, 165 { _SOC_PARITY_TYPE_PARITY, NULL, 166 SOURCE_TRUNK_MAP_MODBASE_PARITY_ERRf, SOURCE_TRUNK_MAP_MODBASE_PARITY_ERRf, 167 SOURCE_TRUNK_MAP_MODBASEm, NULL, 168 SOURCE_TRUNK_MAP_MODBASE_PARITY_CONTROLr, PARITY_ENf, NULL, 169 INVALIDr, INVALIDf, NULL, 170 SOURCE_TRUNK_MAP_MODBASE_PARITY_STATUSr, NULL, INVALIDf, 171 INVALIDr, INVALIDf, 172 INVALIDr, INVALIDr, INVALIDr, 173 0 174 }, 175 { _SOC_PARITY_TYPE_PARITY, NULL, 176 ING_MOD_MAP_PAR_ERRf, ING_MOD_MAP_PAR_ERRf, 177 ING_MOD_MAP_TABLEm, "ING_MOD_MAP", 178 ING_MOD_MAP_PARITY_CONTROLr, PARITY_ENf, NULL, 179 INVALIDr, INVALIDf, NULL, 180 ING_MOD_MAP_PARITY_STATUSr, NULL, INVALIDf, 181 INVALIDr, INVALIDf, 182 INVALIDr, INVALIDr, INVALIDr, 183 0 184 }, 185 { _SOC_PARITY_TYPE_ECC, NULL, 186 LPORT_TABLE_ECC_INTRf, LPORT_TABLE_ECC_INTRf, 187 INVALIDm, "LPORT_TABLE/LPORT_PROFILE_TABLE ECC", 188 LPORT_TABLE_ECC_CONTROLr, ECC_ENf, NULL, 189 INVALIDr, INVALIDf, NULL, 190 LPORT_TABLE_ECC_STATUS_INTRr, NULL, ECC_ERRf, 191 INVALIDr, INVALIDf, 192 INVALIDr, INVALIDr, INVALIDr, 193 0 194 }, 195 { _SOC_PARITY_TYPE_PARITY, NULL, 196 LPORT_TABLE_1BIT_ERR_INTRf, LPORT_TABLE_1BIT_ERR_INTRf, 197 LPORT_TABm, "LPORT_TABLE/LPORT_PROFILE_TABLE PARITY", 198 LPORT_TABLE_ECC_CONTROLr, ECC_ENf, NULL, 199 INVALIDr, INVALIDf, NULL, 200 LPORT_TABLE_PARITY_STATUSr, NULL, INVALIDf, 201 INVALIDr, INVALIDf, 202 INVALIDr, INVALIDr, INVALIDr, 203 0 204 }, 205 { _SOC_PARITY_TYPE_PARITY, NULL, 206 UDF_OFFSET_PAR_ERRf, UDF_OFFSET_PAR_ERRf, 207 FP_UDF_OFFSETm, NULL, 208 UDF_OFFSET_PARITY_CONTROLr, PARITY_ENf, NULL, 209 INVALIDr, INVALIDf, NULL, 210 UDF_OFFSET_PARITY_STATUSr, NULL, INVALIDf, 211 INVALIDr, INVALIDf, 212 INVALIDr, INVALIDr, INVALIDr, 213 0 214 }, 215 { _SOC_PARITY_TYPE_PARITY, NULL, 216 ING_ETAG_PCP_MAPPING_PAR_ERRf, ING_ETAG_PCP_MAPPING_PAR_ERRf, 217 ING_ETAG_PCP_MAPPINGm, NULL, 218 ING_ETAG_PCP_MAPPING_PARITY_CONTROLr, PARITY_ENf, NULL, 219 INVALIDr, INVALIDf, NULL, 220 ING_ETAG_PCP_MAPPING_PARITY_STATUSr, NULL, INVALIDf, 221 INVALIDr, INVALIDf, 222 INVALIDr, INVALIDr, INVALIDr, 223 0 224 }, 225 { _SOC_PARITY_TYPE_PARITY_DUAL, NULL, 226 VXLT_PAR_ERRf, VXLT_PAR_ERRf, 227 VLAN_XLATEm, NULL, 228 VLAN_XLATE_PARITY_CONTROLr, PARITY_ENf, NULL, 229 INVALIDr, INVALIDf, NULL, 230 INVALIDr, vlan_xlate_regs, INVALIDf, 231 INVALIDr, INVALIDf, 232 INVALIDr, INVALIDr, INVALIDr, 233 0 234 }, 235 { _SOC_PARITY_TYPE_PARITY, NULL, 236 VLAN_PROTOCOL_DATA_PARITY_ERRf, VLAN_PROTOCOL_DATA_PARITY_ERRf, 237 VLAN_PROTOCOL_DATAm, NULL, 238 VLAN_PROTOCOL_DATA_PARITY_CONTROLr, PARITY_ENf, NULL, 239 INVALIDr, INVALIDf, NULL, 240 VLAN_PROTOCOL_DATA_PARITY_STATUSr, NULL, INVALIDf, 241 INVALIDr, INVALIDf, 242 INVALIDr, INVALIDr, INVALIDr, 243 0 244 }, 245 { _SOC_PARITY_TYPE_PARITY, NULL, 246 VLAN_SUBNET_DATA_PARITY_ERRf, VLAN_SUBNET_DATA_PARITY_ERRf, 247 VLAN_SUBNETm, NULL, 248 VLAN_SUBNET_DATA_PARITY_CONTROLr, PARITY_ENf, NULL, 249 INVALIDr, INVALIDf, NULL, 250 VLAN_SUBNET_DATA_PARITY_STATUSr, NULL, INVALIDf, 251 INVALIDr, INVALIDf, 252 INVALIDr, INVALIDr, INVALIDr, 253 _SOC_SER_SKIP_FH2 254 }, 255 { _SOC_PARITY_TYPE_PARITY, NULL, 256 VLAN_SUBNET_DATA_PARITY_ERRf, VLAN_SUBNET_DATA_PARITY_ERRf, 257 VLAN_SUBNET_DATA_ONLYm, NULL, 258 VLAN_SUBNET_DATA_PARITY_CONTROLr, PARITY_ENf, NULL, 259 INVALIDr, INVALIDf, NULL, 260 VLAN_SUBNET_DATA_PARITY_STATUSr, NULL, INVALIDf, 261 INVALIDr, INVALIDf, 262 INVALIDr, INVALIDr, INVALIDr, 263 _SOC_SER_SKIP_FH2 264 }, 265 { _SOC_PARITY_TYPE_PARITY, NULL, 266 VFP_POLICY_PAR_ERRf, VFP_POLICY_PAR_ERRf, 267 VFP_POLICY_TABLEm, NULL, 268 VFP_POLICY_PARITY_CONTROLr, PARITY_ENf, NULL, 269 INVALIDr, INVALIDf, NULL, 270 VFP_POLICY_PARITY_STATUS_INTRr, NULL, INVALIDf, 271 INVALIDr, INVALIDf, 272 INVALIDr, INVALIDr, INVALIDr, 273 (_SOC_SER_SKIP_HR3L | _SOC_SER_SKIP_FH2 | _SOC_SER_SKIP_WH2) 274 }, 275 { _SOC_PARITY_TYPE_PARITY, NULL, 276 LMEP_PAR_ERRf, LMEP_PAR_ERRf, 277 LMEPm, NULL, 278 LMEP_PARITY_CONTROLr, PARITY_ENf, NULL, 279 INVALIDr, INVALIDf, NULL, 280 LMEP_PARITY_STATUSr, NULL, INVALIDf, 281 INVALIDr, INVALIDf, 282 INVALIDr, INVALIDr, INVALIDr, 283 0 284 }, 285 { _SOC_PARITY_TYPE_PARITY, NULL, 286 LMEP_DA_PAR_ERRf, LMEP_DA_PAR_ERRf, 287 LMEP_DAm, NULL, 288 LMEP_DA_PARITY_CONTROLr, PARITY_ENf, NULL, 289 INVALIDr, INVALIDf, NULL, 290 LMEP_DA_PARITY_STATUSr, NULL, INVALIDf, 291 INVALIDr, INVALIDf, 292 INVALIDr, INVALIDr, INVALIDr, 293 0 294 }, 295 { _SOC_PARITY_TYPE_PARITY, NULL, 296 VLAN_PARITY_ERRf, VLAN_PARITY_ERRf, 297 VLAN_TABm, NULL, 298 VLAN_PARITY_CONTROLr, PARITY_ENf, NULL, 299 INVALIDr, INVALIDf, NULL, 300 VLAN_PARITY_STATUSr, NULL, INVALIDf, 301 INVALIDr, INVALIDf, 302 INVALIDr, INVALIDr, INVALIDr, 303 0 304 }, 305 { _SOC_PARITY_TYPE_PARITY, NULL, 306 L3_IIF_PAR_ERRf, L3_IIF_PAR_ERRf, 307 L3_IIFm, NULL, 308 L3_IIF_PARITY_CONTROLr, PARITY_ENf, NULL, 309 INVALIDr, INVALIDf, NULL, 310 L3_IIF_PARITY_STATUSr, NULL, INVALIDf, 311 INVALIDr, INVALIDf, 312 INVALIDr, INVALIDr, INVALIDr, 313 _SOC_SER_SKIP_FH2 | _SOC_SER_SKIP_HR3L | _SOC_SER_SKIP_BH 314 }, 315 { _SOC_PARITY_TYPE_PARITY, NULL, 316 VLAN_STG_PARITY_ERRf, VLAN_STG_PARITY_ERRf, 317 STG_TABm, NULL, 318 VLAN_STG_PARITY_CONTROLr, PARITY_ENf, NULL, 319 INVALIDr, INVALIDf, NULL, 320 VLAN_STG_PARITY_STATUSr, NULL, INVALIDf, 321 INVALIDr, INVALIDf, 322 INVALIDr, INVALIDr, INVALIDr, 323 0 324 }, 325 { _SOC_PARITY_TYPE_ECC, NULL, 326 IARB_PKT_1BIT_ERR_INTRf, IARB_PKT_1BIT_ERR_INTRf, 327 INVALIDm, "IARB_PKT", 328 IARB_PKT_ECC_CONTROLr, ECC_ENf, NULL, 329 INVALIDr, INVALIDf, NULL, 330 IARB_PKT_ECC_STATUS_INTRr, NULL, INVALIDf, 331 INVALIDr, INVALIDf, 332 INVALIDr, INVALIDr, INVALIDr, 333 0 334 }, 335 #endif /* _HR3_SER_TEST_IP0 */ 336 { _SOC_PARITY_TYPE_NONE } /* table terminator */ 337 }; 338 static _soc_hr3_ser_info_t _soc_hr3_ip1_ser_info[] = { 339 #if _HR3_SER_TEST_IP1 340 { _SOC_PARITY_TYPE_PARITY, NULL, 341 RMEP_PAR_ERRf, RMEP_PAR_ERRf, 342 RMEPm, NULL, 343 RMEP_PARITY_CONTROLr, PARITY_ENf, NULL, 344 INVALIDr, INVALIDf, NULL, 345 RMEP_PARITY_STATUSr, NULL, INVALIDf, 346 INVALIDr, INVALIDf, 347 INVALIDr, INVALIDr, INVALIDr, 348 0 349 }, 350 { _SOC_PARITY_TYPE_PARITY, NULL, 351 L3MC_PAR_ERRf, L3MC_PAR_ERRf, 352 L3_IPMCm, NULL, 353 L3MC_PARITY_CONTROLr, PARITY_ENf, NULL, 354 INVALIDr, INVALIDf, NULL, 355 L3MC_PARITY_STATUSr, NULL, INVALIDf, 356 INVALIDr, INVALIDf, 357 INVALIDr, INVALIDr, INVALIDr, 358 _SOC_SER_SKIP_FH2 | _SOC_SER_SKIP_BH 359 }, 360 { _SOC_PARITY_TYPE_PARITY, NULL, 361 INITIAL_L3_ECMP_GROUP_PAR_ERRf, INITIAL_L3_ECMP_GROUP_PAR_ERRf, 362 INITIAL_L3_ECMP_GROUPm, NULL, 363 INITIAL_L3_ECMP_GROUP_PARITY_CONTROLr, PARITY_ENf, NULL, 364 INVALIDr, INVALIDf, NULL, 365 INITIAL_L3_ECMP_GROUP_PARITY_STATUSr, NULL, INVALIDf, 366 INVALIDr, INVALIDf, 367 INVALIDr, INVALIDr, INVALIDr, 368 _SOC_SER_SKIP_FH2 | _SOC_SER_SKIP_HR3L | _SOC_SER_SKIP_BH | 369 _SOC_SER_SKIP_WH2 370 }, 371 { _SOC_PARITY_TYPE_PARITY, NULL, 372 INITIAL_L3_ECMP_PAR_ERRf, INITIAL_L3_ECMP_PAR_ERRf, 373 INITIAL_L3_ECMPm, NULL, 374 INITIAL_L3_ECMP_PARITY_CONTROLr, PARITY_ENf, NULL, 375 INVALIDr, INVALIDf, NULL, 376 INITIAL_L3_ECMP_PARITY_STATUSr, NULL, INVALIDf, 377 INVALIDr, INVALIDf, 378 INVALIDr, INVALIDr, INVALIDr, 379 _SOC_SER_SKIP_FH2 | _SOC_SER_SKIP_HR3L | _SOC_SER_SKIP_BH | 380 _SOC_SER_SKIP_WH2 381 }, 382 { _SOC_PARITY_TYPE_PARITY_DUAL, NULL, 383 L3_ENTRY_PAR_ERRf, L3_ENTRY_PAR_ERRf, 384 L3_ENTRY_ONLYm, NULL, 385 L3_ENTRY_PARITY_CONTROLr, PARITY_ENf, NULL, 386 INVALIDr, INVALIDf, NULL, 387 INVALIDr, l3_entry_regs, INVALIDf, 388 INVALIDr, INVALIDf, 389 INVALIDr, INVALIDr, INVALIDr, 390 _SOC_SER_SKIP_FH2 391 }, 392 { _SOC_PARITY_TYPE_PARITY, NULL, 393 L2_USER_ENTRY_DATA_ONLY_PAR_ERRf, L2_USER_ENTRY_DATA_ONLY_PAR_ERRf, 394 L2_USER_ENTRYm, NULL, 395 L2_USER_ENTRY_DATA_ONLY_PARITY_CONTROLr, PARITY_ENf, NULL, 396 INVALIDr, INVALIDf, NULL, 397 L2_USER_ENTRY_DATA_ONLY_PARITY_STATUSr, NULL, INVALIDf, 398 INVALIDr, INVALIDf, 399 INVALIDr, INVALIDr, INVALIDr, 400 0 401 }, 402 { _SOC_PARITY_TYPE_PARITY, NULL, 403 L2_USER_ENTRY_DATA_ONLY_PAR_ERRf, L2_USER_ENTRY_DATA_ONLY_PAR_ERRf, 404 L2_USER_ENTRY_DATA_ONLYm, NULL, 405 L2_USER_ENTRY_DATA_ONLY_PARITY_CONTROLr, PARITY_ENf, NULL, 406 INVALIDr, INVALIDf, NULL, 407 L2_USER_ENTRY_DATA_ONLY_PARITY_STATUSr, NULL, INVALIDf, 408 INVALIDr, INVALIDf, 409 INVALIDr, INVALIDr, INVALIDr, 410 0 411 }, 412 { _SOC_PARITY_TYPE_PARITY_DUAL, NULL, 413 L2_ENTRY_PAR_ERRf, L2_ENTRY_PAR_ERRf, 414 L2Xm, "L2_ENTRY/L2_ENTRY_ONLY", 415 L2_ENTRY_PARITY_CONTROLr, PARITY_ENf, NULL, 416 INVALIDr, INVALIDf, NULL, 417 INVALIDr, l2_entry_regs, INVALIDf, 418 INVALIDr, INVALIDf, 419 INVALIDr, INVALIDr, INVALIDr, 420 0 421 }, 422 { _SOC_PARITY_TYPE_PARITY, NULL, 423 L3_DEFIP_DATA_PAR_ERRf, L3_DEFIP_DATA_PAR_ERRf, 424 L3_DEFIPm, NULL, 425 L3_DEFIP_PARITY_CONTROLr, PARITY_ENf, NULL, 426 INVALIDr, INVALIDf, NULL, 427 L3_DEFIP_PARITY_STATUSr, NULL, INVALIDf, 428 INVALIDr, INVALIDf, 429 INVALIDr, INVALIDr, INVALIDr, 430 _SOC_SER_SKIP_FH2 | _SOC_SER_SKIP_BH 431 }, 432 { _SOC_PARITY_TYPE_PARITY, NULL, 433 L3_DEFIP_DATA_PAR_ERRf, L3_DEFIP_DATA_PAR_ERRf, 434 L3_DEFIP_DATA_ONLYm, NULL, 435 L3_DEFIP_PARITY_CONTROLr, PARITY_ENf, NULL, 436 INVALIDr, INVALIDf, NULL, 437 L3_DEFIP_PARITY_STATUSr, NULL, INVALIDf, 438 INVALIDr, INVALIDf, 439 INVALIDr, INVALIDr, INVALIDr, 440 _SOC_SER_SKIP_FH2 | _SOC_SER_SKIP_BH 441 }, 442 { _SOC_PARITY_TYPE_PARITY, NULL, 443 MAID_REDUCTION_PAR_ERRf, MAID_REDUCTION_PAR_ERRf, 444 MAID_REDUCTIONm, NULL, 445 MAID_REDUCTION_PARITY_CONTROLr, PARITY_ENf, NULL, 446 INVALIDr, INVALIDf, NULL, 447 MAID_REDUCTION_PARITY_STATUSr, NULL, INVALIDf, 448 INVALIDr, INVALIDf, 449 INVALIDr, INVALIDr, INVALIDr, 450 0 451 }, 452 { _SOC_PARITY_TYPE_PARITY, NULL, 453 MA_STATE_PAR_ERRf, MA_STATE_PAR_ERRf, 454 MA_STATEm, NULL, 455 MA_STATE_PARITY_CONTROLr, PARITY_ENf, NULL, 456 INVALIDr, INVALIDf, NULL, 457 MA_STATE_PARITY_STATUSr, NULL, INVALIDf, 458 INVALIDr, INVALIDf, 459 INVALIDr, INVALIDr, INVALIDr, 460 0 461 }, 462 { _SOC_PARITY_TYPE_PARITY, NULL, 463 INITIAL_NHOP_PAR_ERRf, INITIAL_NHOP_PAR_ERRf, 464 INITIAL_ING_L3_NEXT_HOPm, NULL, 465 INITIAL_NHOP_PARITY_CONTROLr, PARITY_ENf, NULL, 466 INVALIDr, INVALIDf, NULL, 467 INITIAL_NHOP_PARITY_STATUSr, NULL, INVALIDf, 468 INVALIDr, INVALIDf, 469 INVALIDr, INVALIDr, INVALIDr, 470 _SOC_SER_SKIP_FH2 | _SOC_SER_SKIP_BH 471 }, 472 { _SOC_PARITY_TYPE_PARITY, NULL, 473 L2MC_PAR_ERRf, L2MC_PAR_ERRf, 474 L2MCm, NULL, 475 L2MC_PARITY_CONTROLr, PARITY_ENf, NULL, 476 INVALIDr, INVALIDf, NULL, 477 L2MC_PARITY_STATUSr, NULL, INVALIDf, 478 INVALIDr, INVALIDf, 479 INVALIDr, INVALIDr, INVALIDr, 480 0 481 }, 482 { _SOC_PARITY_TYPE_PARITY, NULL, 483 MA_INDEX_PAR_ERRf, MA_INDEX_PAR_ERRf, 484 MA_INDEXm, NULL, 485 MA_INDEX_PARITY_CONTROLr, PARITY_ENf, NULL, 486 INVALIDr, INVALIDf, NULL, 487 MA_INDEX_PARITY_STATUSr, NULL, INVALIDf, 488 INVALIDr, INVALIDf, 489 INVALIDr, INVALIDr, INVALIDr, 490 0 491 }, 492 #endif /* _HR3_SER_TEST_IP1 */ 493 { _SOC_PARITY_TYPE_NONE }, /* table terminator */ 494 }; 495 static _soc_hr3_ser_info_t _soc_hr3_ip2_ser_info[] = { 496 #if _HR3_SER_TEST_IP2 497 { _SOC_PARITY_TYPE_PARITY, NULL, 498 EGR_MASK_PAR_ERRf, EGR_MASK_PAR_ERRf, 499 EGR_MASKm, NULL, 500 EGR_MASK_PARITY_CONTROLr, PARITY_ENf, NULL, 501 INVALIDr, INVALIDf, NULL, 502 EGR_MASK_PARITY_STATUSr, NULL, INVALIDf, 503 INVALIDr, INVALIDf, 504 INVALIDr, INVALIDr, INVALIDr, 505 0 506 }, 507 { _SOC_PARITY_TYPE_PARITY, NULL, 508 EGR_MASK_MODBASE_PAR_ERRf, EGR_MASK_MODBASE_PAR_ERRf, 509 EGR_MASK_MODBASEm, NULL, 510 EGR_MASK_MODBASE_PARITY_CONTROLr, PARITY_ENf, NULL, 511 INVALIDr, INVALIDf, NULL, 512 EGR_MASK_MODBASE_PARITY_STATUSr, NULL, INVALIDf, 513 INVALIDr, INVALIDf, 514 INVALIDr, INVALIDr, INVALIDr, 515 0 516 }, 517 { _SOC_PARITY_TYPE_PARITY, NULL, 518 TRUNK_GROUP_PAR_ERRf, TRUNK_GROUP_PAR_ERRf, 519 TRUNK_GROUPm, NULL, 520 TRUNK_GROUP_PARITY_CONTROLr, PARITY_ENf, NULL, 521 INVALIDr, INVALIDf, NULL, 522 TRUNK_GROUP_PARITY_STATUSr, NULL, INVALIDf, 523 INVALIDr, INVALIDf, 524 INVALIDr, INVALIDr, INVALIDr, 525 0 526 }, 527 { _SOC_PARITY_TYPE_PARITY, NULL, 528 L3_ECMP_PAR_ERRf, L3_ECMP_PAR_ERRf, 529 L3_ECMPm, NULL, 530 L3_ECMP_PARITY_CONTROLr, PARITY_ENf, NULL, 531 INVALIDr, INVALIDf, NULL, 532 L3_ECMP_PARITY_STATUSr, NULL, INVALIDf, 533 INVALIDr, INVALIDf, 534 INVALIDr, INVALIDr, INVALIDr, 535 _SOC_SER_SKIP_FH2 | _SOC_SER_SKIP_BH | _SOC_SER_SKIP_HR3L | 536 _SOC_SER_SKIP_WH2 537 }, 538 { _SOC_PARITY_TYPE_PARITY, NULL, 539 L3_ECMP_GROUP_PAR_ERRf, L3_ECMP_GROUP_PAR_ERRf, 540 L3_ECMP_COUNTm, NULL, 541 L3_ECMP_GROUP_PARITY_CONTROLr, PARITY_ENf, NULL, 542 INVALIDr, INVALIDf, NULL, 543 L3_ECMP_GROUP_PARITY_STATUSr, NULL, INVALIDf, 544 INVALIDr, INVALIDf, 545 INVALIDr, INVALIDr, INVALIDr, 546 _SOC_SER_SKIP_FH2 | _SOC_SER_SKIP_BH | _SOC_SER_SKIP_HR3L | 547 _SOC_SER_SKIP_WH2 548 }, 549 { _SOC_PARITY_TYPE_PARITY, NULL, 550 VLAN_PROFILE_2_PAR_ERRf, VLAN_PROFILE_2_PAR_ERRf, 551 VLAN_PROFILE_2m, NULL, 552 VLAN_PROFILE_2_PARITY_CONTROLr, PARITY_ENf, NULL, 553 INVALIDr, INVALIDf, NULL, 554 VLAN_PROFILE_2_PARITY_STATUSr, NULL, INVALIDf, 555 INVALIDr, INVALIDf, 556 INVALIDr, INVALIDr, INVALIDr, 557 0 558 }, 559 { _SOC_PARITY_TYPE_PARITY, NULL, 560 IFP_STORM_CONTROL_PAR_ERRf, IFP_STORM_CONTROL_PAR_ERRf, 561 FP_STORM_CONTROL_METERSm, NULL, 562 IFP_STORM_CONTROL_PARITY_CONTROLr, PARITY_ENf, NULL, 563 INVALIDr, INVALIDf, NULL, 564 IFP_STORM_CONTROL_PARITY_STATUSr, NULL, INVALIDf, 565 INVALIDr, INVALIDf, 566 INVALIDr, INVALIDr, INVALIDr, 567 0 568 }, 569 { _SOC_PARITY_TYPE_PARITY, NULL, 570 NONUCAST_TRUNK_BLOCK_MASK_PAR_ERRf, NONUCAST_TRUNK_BLOCK_MASK_PAR_ERRf, 571 NONUCAST_TRUNK_BLOCK_MASKm, NULL, 572 NONUCAST_TRUNK_BLOCK_MASK_PARITY_CONTROLr, PARITY_ENf, NULL, 573 INVALIDr, INVALIDf, NULL, 574 NONUCAST_TRUNK_BLOCK_MASK_PARITY_STATUSr, NULL, INVALIDf, 575 INVALIDr, INVALIDf, 576 INVALIDr, INVALIDr, INVALIDr, 577 0 578 }, 579 { _SOC_PARITY_TYPE_PARITY, NULL, 580 SRC_MODID_BLOCK_PAR_ERRf, SRC_MODID_BLOCK_PAR_ERRf, 581 SRC_MODID_BLOCKm, NULL, 582 SRC_MODID_BLOCK_PARITY_CONTROLr, PARITY_ENf, NULL, 583 INVALIDr, INVALIDf, NULL, 584 SRC_MODID_BLOCK_PARITY_STATUSr, NULL, INVALIDf, 585 INVALIDr, INVALIDf, 586 INVALIDr, INVALIDr, INVALIDr, 587 0 588 }, 589 { _SOC_PARITY_TYPE_PARITY, NULL, 590 IFP_METER_PAR_ERRf, IFP_METER_PAR_ERRf, 591 FP_METER_TABLEm, NULL, 592 IFP_METER_PARITY_CONTROLr, PARITY_ENf, NULL, 593 INVALIDr, INVALIDf, NULL, 594 IFP_METER_PARITY_STATUSr, NULL, INVALIDf, 595 INVALIDr, INVALIDf, 596 INVALIDr, INVALIDr, INVALIDr, 597 0 598 }, 599 { _SOC_PARITY_TYPE_PARITY, NULL, 600 MODPORT_MAP_SW_PAR_ERRf, MODPORT_MAP_SW_PAR_ERRf, 601 MODPORT_MAP_SWm, NULL, 602 MODPORT_MAP_SW_PARITY_CONTROLr, PARITY_ENf, NULL, 603 INVALIDr, INVALIDf, NULL, 604 MODPORT_MAP_SW_PARITY_STATUSr, NULL, INVALIDf, 605 INVALIDr, INVALIDf, 606 INVALIDr, INVALIDr, INVALIDr, 607 0 608 }, 609 { _SOC_PARITY_TYPE_PARITY, NULL, 610 MODPORT_MAP_IM_PAR_ERRf, MODPORT_MAP_IM_PAR_ERRf, 611 MODPORT_MAP_IMm, NULL, 612 MODPORT_MAP_IM_PARITY_CONTROLr, PARITY_ENf, NULL, 613 INVALIDr, INVALIDf, NULL, 614 MODPORT_MAP_IM_PARITY_STATUSr, NULL, INVALIDf, 615 INVALIDr, INVALIDf, 616 INVALIDr, INVALIDr, INVALIDr, 617 0 618 }, 619 { _SOC_PARITY_TYPE_PARITY, NULL, 620 MODPORT_MAP_EM_PAR_ERRf, MODPORT_MAP_EM_PAR_ERRf, 621 MODPORT_MAP_EMm, NULL, 622 MODPORT_MAP_EM_PARITY_CONTROLr, PARITY_ENf, NULL, 623 INVALIDr, INVALIDf, NULL, 624 MODPORT_MAP_EM_PARITY_STATUSr, NULL, INVALIDf, 625 INVALIDr, INVALIDf, 626 INVALIDr, INVALIDr, INVALIDr, 627 0 628 }, 629 { _SOC_PARITY_TYPE_PARITY, NULL, 630 ALTERNATE_EMIRROR_BITMAP_PAR_ERRf, ALTERNATE_EMIRROR_BITMAP_PAR_ERRf, 631 ALTERNATE_EMIRROR_BITMAPm, NULL, 632 ALTERNATE_EMIRROR_BITMAP_PARITY_CONTROLr, PARITY_ENf, NULL, 633 INVALIDr, INVALIDf, NULL, 634 ALTERNATE_EMIRROR_BITMAP_PARITY_STATUSr, NULL, INVALIDf, 635 INVALIDr, INVALIDf, 636 INVALIDr, INVALIDr, INVALIDr, 637 0 638 }, 639 { _SOC_PARITY_TYPE_PARITY, NULL, 640 MAC_BLOCK_TABLE_PAR_ERRf, MAC_BLOCK_TABLE_PAR_ERRf, 641 MAC_BLOCKm, "MAC_BLOCK_TABLE", 642 MAC_BLOCK_TABLE_PARITY_CONTROLr, PARITY_ENf, NULL, 643 INVALIDr, INVALIDf, NULL, 644 MAC_BLOCK_TABLE_PARITY_STATUSr, NULL, INVALIDf, 645 INVALIDr, INVALIDf, 646 INVALIDr, INVALIDr, INVALIDr, 647 0 648 }, 649 { _SOC_PARITY_TYPE_PARITY, NULL, 650 TRUNK_EGR_MASK_PAR_ERRf, TRUNK_EGR_MASK_PAR_ERRf, 651 TRUNK_EGR_MASKm, NULL, 652 TRUNK_EGR_MASK_PARITY_CONTROLr, PARITY_ENf, NULL, 653 INVALIDr, INVALIDf, NULL, 654 TRUNK_EGR_MASK_PARITY_STATUSr, NULL, INVALIDf, 655 INVALIDr, INVALIDf, 656 INVALIDr, INVALIDr, INVALIDr, 657 0 658 }, 659 { _SOC_PARITY_TYPE_PARITY, NULL, 660 L3_MTU_VALUES_PAR_ERRf, L3_MTU_VALUES_PAR_ERRf, 661 L3_MTU_VALUESm, NULL, 662 L3_MTU_VALUES_PARITY_CONTROLr, PARITY_ENf, NULL, 663 INVALIDr, INVALIDf, NULL, 664 L3_MTU_VALUES_PARITY_STATUSr, NULL, INVALIDf, 665 INVALIDr, INVALIDf, 666 INVALIDr, INVALIDr, INVALIDr, 667 _SOC_SER_SKIP_FH2 668 }, 669 { _SOC_PARITY_TYPE_PARITY, NULL, 670 OAM_LM_COUNTERS_PAR_ERRf, OAM_LM_COUNTERS_PAR_ERRf, 671 OAM_LM_COUNTERSm, NULL, 672 OAM_LM_COUNTERS_PARITY_CONTROLr, PARITY_ENf, NULL, 673 INVALIDr, INVALIDf, NULL, 674 OAM_LM_COUNTERS_PARITY_STATUSr, NULL, INVALIDf, 675 INVALIDr, INVALIDf, 676 INVALIDr, INVALIDr, INVALIDr, 677 0 678 }, 679 { _SOC_PARITY_TYPE_PARITY, NULL, 680 ING_VLAN_COUNTER_PAR_ERRf, ING_VLAN_COUNTER_PAR_ERRf, 681 ING_VLAN_COUNTER_TABLEm, NULL, 682 ING_VLAN_COUNTER_PARITY_CONTROLr, PARITY_ENf, NULL, 683 INVALIDr, INVALIDf, NULL, 684 ING_VLAN_COUNTER_PARITY_STATUSr, NULL, INVALIDf, 685 INVALIDr, INVALIDf, 686 INVALIDr, INVALIDr, INVALIDr, 687 0 688 }, 689 { _SOC_PARITY_TYPE_PARITY, NULL, 690 TRUNK_BITMAP_TABLE_PAR_ERRf, TRUNK_BITMAP_TABLE_PAR_ERRf, 691 TRUNK_BITMAPm, NULL, 692 TRUNK_BITMAP_TABLE_PARITY_CONTROLr, PARITY_ENf, NULL, 693 INVALIDr, INVALIDf, NULL, 694 TRUNK_BITMAP_TABLE_PARITY_STATUSr, NULL, INVALIDf, 695 INVALIDr, INVALIDf, 696 INVALIDr, INVALIDr, INVALIDr, 697 0 698 }, 699 { _SOC_PARITY_TYPE_PARITY, NULL, 700 ING_NHOP_PAR_ERRf, ING_NHOP_PAR_ERRf, 701 ING_L3_NEXT_HOPm, NULL, 702 ING_L3_NEXT_HOP_PARITY_CONTROLr, PARITY_ENf, NULL, 703 INVALIDr, INVALIDf, NULL, 704 ING_L3_NEXT_HOP_PARITY_STATUSr, NULL, INVALIDf, 705 INVALIDr, INVALIDf, 706 INVALIDr, INVALIDr, INVALIDr, 707 _SOC_SER_SKIP_FH2 708 }, 709 { _SOC_PARITY_TYPE_PARITY, NULL, 710 IFP_POLICY_PAR_ERRf, IFP_POLICY_PAR_ERRf, 711 FP_POLICY_TABLEm, NULL, 712 IFP_POLICY_PARITY_CONTROLr, PARITY_ENf, NULL, 713 INVALIDr, INVALIDf, NULL, 714 IFP_POLICY_PARITY_STATUSr, NULL, INVALIDf, 715 INVALIDr, INVALIDf, 716 INVALIDr, INVALIDr, INVALIDr, 717 0 718 }, 719 { _SOC_PARITY_TYPE_PARITY, NULL, 720 IFP_COUNTER_PAR_ERRf, IFP_COUNTER_PAR_ERRf, 721 FP_COUNTER_TABLEm, NULL, 722 IFP_COUNTER_PARITY_CONTROLr, PARITY_ENf, NULL, 723 INVALIDr, INVALIDf, NULL, 724 IFP_COUNTER_PARITY_STATUSr, NULL, INVALIDf, 725 INVALIDr, INVALIDf, 726 INVALIDr, INVALIDr, INVALIDr, 727 0 728 }, 729 #endif /* _HR3_SER_TEST_IP2 */ 730 { _SOC_PARITY_TYPE_NONE }, /* table terminator */ 731 }; 732 static _soc_hr3_ser_info_t _soc_hr3_ep_ser_info[] = { 733 #if _HR3_SER_TEST_EP 734 { _SOC_PARITY_TYPE_PARITY, NULL, 735 EGR_EFP_POLICY_TABLE_PAR_ERRf, EGR_EFP_POLICY_TABLE_PAR_ERRf, 736 EFP_POLICY_TABLEm, NULL, 737 EFP_POLICY_TABLE_PARITY_CONTROLr, PARITY_ENf, NULL, 738 INVALIDr, INVALIDf, NULL, 739 EFP_POLICY_TABLE_PARITY_STATUSr, NULL, INVALIDf, 740 INVALIDr, INVALIDf, 741 INVALIDr, INVALIDr, INVALIDr, 742 _SOC_SER_SKIP_FH2 | _SOC_SER_SKIP_HR3L | _SOC_SER_SKIP_WH2 743 }, 744 { _SOC_PARITY_TYPE_PARITY, NULL, 745 EGR_EFP_METER_TABLE_PAR_ERRf, EGR_EFP_METER_TABLE_PAR_ERRf, 746 EFP_METER_TABLEm, NULL, 747 EFP_METER_TABLE_PARITY_CONTROLr, PARITY_ENf, NULL, 748 INVALIDr, INVALIDf, NULL, 749 EFP_METER_TABLE_PARITY_STATUSr, NULL, INVALIDf, 750 INVALIDr, INVALIDf, 751 INVALIDr, INVALIDr, INVALIDr, 752 _SOC_SER_SKIP_FH2 | _SOC_SER_SKIP_HR3L | _SOC_SER_SKIP_WH2 753 }, 754 { _SOC_PARITY_TYPE_PARITY, NULL, 755 EGR_PERQ_XMT_COUNTERS_PAR_ERRf, EGR_PERQ_XMT_COUNTERS_PAR_ERRf, 756 EGR_PERQ_XMT_COUNTERSm, NULL, 757 EGR_EDATABUF_PARITY_CONTROLr, EGR_PERQ_XMT_COUNTERS_PAR_ENf, NULL, 758 INVALIDr, INVALIDf, NULL, 759 EGR_PERQ_XMT_COUNTERS_PARITY_STATUSr, NULL, INVALIDf, 760 INVALIDr, INVALIDf, 761 INVALIDr, INVALIDr, INVALIDr, 762 0 763 }, 764 { _SOC_PARITY_TYPE_PARITY, NULL, 765 EFP_COUNTER_TABLE_PAR_ERRf, EFP_COUNTER_TABLE_PAR_ERRf, 766 EFP_COUNTER_TABLEm, NULL, 767 EGR_EDATABUF_PARITY_CONTROLr, EFP_COUNTER_TABLE_PAR_ENf, NULL, 768 INVALIDr, INVALIDf, NULL, 769 EFP_COUNTER_TABLE_PARITY_STATUSr, NULL, INVALIDf, 770 INVALIDr, INVALIDf, 771 INVALIDr, INVALIDr, INVALIDr, 772 _SOC_SER_SKIP_FH2 | _SOC_SER_SKIP_HR3L | _SOC_SER_SKIP_WH2 773 }, 774 { _SOC_PARITY_TYPE_PARITY, NULL, 775 EGR_NHOP_PAR_ERRf, EGR_NHOP_PAR_ERRf, 776 EGR_L3_NEXT_HOPm, NULL, 777 EGR_L3_NEXT_HOP_PARITY_CONTROLr, PARITY_ENf, NULL, 778 INVALIDr, INVALIDf, NULL, 779 EGR_L3_NEXT_HOP_PARITY_STATUSr, NULL, INVALIDf, 780 INVALIDr, INVALIDf, 781 INVALIDr, INVALIDr, INVALIDr, 782 _SOC_SER_SKIP_FH2 783 }, 784 { _SOC_PARITY_TYPE_PARITY, NULL, 785 EGR_L3_INTF_PAR_ERRf, EGR_L3_INTF_PAR_ERRf, 786 EGR_L3_INTFm, NULL, 787 EGR_L3_INTF_PARITY_CONTROLr, PARITY_ENf, NULL, 788 INVALIDr, INVALIDf, NULL, 789 EGR_L3_INTF_PARITY_STATUSr, NULL, INVALIDf, 790 INVALIDr, INVALIDf, 791 INVALIDr, INVALIDr, INVALIDr, 792 _SOC_SER_SKIP_FH2 793 }, 794 { _SOC_PARITY_TYPE_PARITY, NULL, 795 EGR_VLAN_PAR_ERRf, EGR_VLAN_PAR_ERRf, 796 EGR_VLANm, NULL, 797 EGR_VLAN_PARITY_CONTROLr, PARITY_ENf, NULL, 798 INVALIDr, INVALIDf, NULL, 799 EGR_VLAN_PARITY_STATUSr, NULL, INVALIDf, 800 INVALIDr, INVALIDf, 801 INVALIDr, INVALIDr, INVALIDr, 802 0 803 }, 804 { _SOC_PARITY_TYPE_PARITY, NULL, 805 EGR_VLAN_STG_PAR_ERRf, EGR_VLAN_STG_PAR_ERRf, 806 EGR_VLAN_STGm, NULL, 807 EGR_VLAN_STG_PARITY_CONTROLr, PARITY_ENf, NULL, 808 INVALIDr, INVALIDf, NULL, 809 EGR_VLAN_STG_PARITY_STATUSr, NULL, INVALIDf, 810 INVALIDr, INVALIDf, 811 INVALIDr, INVALIDr, INVALIDr, 812 0 813 }, 814 { _SOC_PARITY_TYPE_PARITY_DUAL, NULL, 815 EGR_VXLT_PAR_ERRf, EGR_VXLT_PAR_ERRf, 816 EGR_VLAN_XLATEm, NULL, 817 EGR_VLAN_XLATE_PARITY_CONTROLr, PARITY_ENf, NULL, 818 INVALIDr, INVALIDf, NULL, 819 INVALIDr, egr_vlan_xlate_regs, INVALIDf, 820 INVALIDr, INVALIDf, 821 INVALIDr, INVALIDr, INVALIDr, 822 0 823 }, 824 { _SOC_PARITY_TYPE_PARITY, NULL, 825 EGR_ETAG_PCP_DE_MAPPING_PAR_ERRf, EGR_ETAG_PCP_DE_MAPPING_PAR_ERRf, 826 EGR_ETAG_PCP_MAPPINGm, NULL, 827 EGR_ETAG_PCP_DE_MAPPING_PARITY_CONTROLr, PARITY_ENf, NULL, 828 INVALIDr, INVALIDf, NULL, 829 EGR_ETAG_PCP_DE_MAPPING_PARITY_STATUSr, NULL, INVALIDf, 830 INVALIDr, INVALIDf, 831 INVALIDr, INVALIDr, INVALIDr, 832 0 833 }, 834 { _SOC_PARITY_TYPE_PARITY, NULL, 835 EGR_GPP_ATTRIBUTES_PAR_ERRf, EGR_GPP_ATTRIBUTES_PAR_ERRf, 836 EGR_GPP_ATTRIBUTESm, NULL, 837 EGR_GPP_ATTRIBUTES_PARITY_CONTROLr, PARITY_ENf, NULL, 838 INVALIDr, INVALIDf, NULL, 839 EGR_GPP_ATTRIBUTES_PARITY_STATUSr, NULL, INVALIDf, 840 INVALIDr, INVALIDf, 841 INVALIDr, INVALIDr, INVALIDr, 842 0 843 }, 844 { _SOC_PARITY_TYPE_PARITY, NULL, 845 EGR_GPP_ATTRIBUTES_MODBASE_PAR_ERRf, EGR_GPP_ATTRIBUTES_MODBASE_PAR_ERRf, 846 EGR_GPP_ATTRIBUTES_MODBASEm, NULL, 847 EGR_GPP_ATTRIBUTES_MODBASE_PARITY_CONTROLr, PARITY_ENf, NULL, 848 INVALIDr, INVALIDf, NULL, 849 EGR_GPP_ATTRIBUTES_MODBASE_PARITY_STATUSr, NULL, INVALIDf, 850 INVALIDr, INVALIDf, 851 INVALIDr, INVALIDr, INVALIDr, 852 0 853 }, 854 { _SOC_PARITY_TYPE_PARITY, NULL, 855 EGR_HEADER_ENCAP_DATA_PAR_ERRf, EGR_HEADER_ENCAP_DATA_PAR_ERRf, 856 EGR_HEADER_ENCAP_DATAm, NULL, 857 EGR_HEADER_ENCAP_DATA_PARITY_CONTROLr, PARITY_ENf, NULL, 858 INVALIDr, INVALIDf, NULL, 859 EGR_HEADER_ENCAP_DATA_PARITY_STATUSr, NULL, INVALIDf, 860 INVALIDr, INVALIDf, 861 INVALIDr, INVALIDr, INVALIDr, 862 0 863 }, 864 { _SOC_PARITY_TYPE_PARITY, NULL, 865 EGR_PER_Q_ECN_MARKED_PAR_ERRf, EGR_PER_Q_ECN_MARKED_PAR_ERRf, 866 EGR_PER_Q_ECN_MARKEDm, NULL, 867 EGR_EDATABUF_PARITY_CONTROLr, EGR_PER_Q_ECN_MARKED_PAR_ENf, NULL, 868 INVALIDr, INVALIDf, NULL, 869 EGR_PER_Q_ECN_MARKED_PARITY_STATUSr, NULL, INVALIDf, 870 INVALIDr, INVALIDf, 871 INVALIDr, INVALIDr, INVALIDr, 872 0 873 }, 874 { _SOC_PARITY_TYPE_PARITY, NULL, 875 EGR_VLAN_COUNTER_TABLE_PAR_ERRf, EGR_VLAN_COUNTER_TABLE_PAR_ERRf, 876 EGR_VLAN_COUNTER_TABLEm, NULL, 877 EGR_EDATABUF_PARITY_CONTROLr, EGR_VLAN_COUNTER_TABLE_PAR_ENf, NULL, 878 INVALIDr, INVALIDf, NULL, 879 EGR_VLAN_COUNTER_TABLE_PARITY_STATUSr, NULL, INVALIDf, 880 INVALIDr, INVALIDf, 881 INVALIDr, INVALIDr, INVALIDr, 882 0 883 }, 884 /* disable ser on EGR_MOD_MAP_TABLEm */ 885 { _SOC_PARITY_TYPE_ECC, NULL, 886 EGR_INITBUF_DBE_PAR_ERRf, EGR_INITBUF_DBE_PAR_ERRf, 887 INVALIDm, "EGR_INITBUF Double-Bit error", 888 EGR_INITBUF_ECC_CONTROLr, ECC_ENf, NULL, 889 INVALIDr, INVALIDf, NULL, 890 EGR_INITBUF_ECC_STATUS_DBEr, NULL, INVALIDf, 891 INVALIDr, INVALIDf, 892 INVALIDr, INVALIDr, INVALIDr, 893 0 894 }, 895 { _SOC_PARITY_TYPE_ECC, NULL, 896 EGR_CM_PAR_ERRf, EGR_CM_PAR_ERRf, 897 INVALIDm, "EP_EDB_CM_MEM", 898 EGR_EDATABUF_PARITY_CONTROLr, CM_ECC_ENf, NULL, 899 INVALIDr, INVALIDf, NULL, 900 EGR_CM_PARITY_STATUSr, NULL, INVALIDf, 901 INVALIDr, INVALIDf, 902 INVALIDr, INVALIDr, INVALIDr, 903 0 904 }, 905 { _SOC_PARITY_TYPE_ECC, NULL, 906 EGR_GP0_PAR_ERRf, EGR_GP0_PAR_ERRf, 907 INVALIDm, "EP_EDB_GP0_MEM", 908 EGR_EDATABUF_PARITY_CONTROLr, GP0_ECC_ENf, NULL, 909 INVALIDr, INVALIDf, NULL, 910 EGR_GP0_PARITY_STATUSr, NULL, INVALIDf, 911 INVALIDr, INVALIDf, 912 INVALIDr, INVALIDr, INVALIDr, 913 0 914 }, 915 { _SOC_PARITY_TYPE_ECC, NULL, 916 EGR_GP1_PAR_ERRf, EGR_GP1_PAR_ERRf, 917 INVALIDm, "EP_EDB_GP1_MEM", 918 EGR_EDATABUF_PARITY_CONTROLr, GP1_ECC_ENf, NULL, 919 INVALIDr, INVALIDf, NULL, 920 EGR_GP1_PARITY_STATUSr, NULL, INVALIDf, 921 INVALIDr, INVALIDf, 922 INVALIDr, INVALIDr, INVALIDr, 923 0 924 }, 925 { _SOC_PARITY_TYPE_ECC, NULL, 926 EGR_GP2_PAR_ERRf, EGR_GP2_PAR_ERRf, 927 INVALIDm, "EP_EDB_GP2_MEM", 928 EGR_EDATABUF_PARITY_CONTROLr, GP2_ECC_ENf, NULL, 929 INVALIDr, INVALIDf, NULL, 930 EGR_GP2_PARITY_STATUSr, NULL, INVALIDf, 931 INVALIDr, INVALIDf, 932 INVALIDr, INVALIDr, INVALIDr, 933 0 934 }, 935 { _SOC_PARITY_TYPE_ECC, NULL, 936 EGR_GP3_PAR_ERRf, EGR_GP3_PAR_ERRf, 937 INVALIDm, "EP_EDB_GP3_MEM", 938 EGR_EDATABUF_PARITY_CONTROLr, GP3_ECC_ENf, NULL, 939 INVALIDr, INVALIDf, NULL, 940 EGR_GP3_PARITY_STATUSr, NULL, INVALIDf, 941 INVALIDr, INVALIDf, 942 INVALIDr, INVALIDr, INVALIDr, 943 0 944 }, 945 { _SOC_PARITY_TYPE_ECC, NULL, 946 EGR_GP4_PAR_ERRf, EGR_GP4_PAR_ERRf, 947 INVALIDm, "EP_EDB_GP4_MEM", 948 EGR_EDATABUF_PARITY_CONTROLr, GP4_ECC_ENf, NULL, 949 INVALIDr, INVALIDf, NULL, 950 EGR_GP4_PARITY_STATUSr, NULL, INVALIDf, 951 INVALIDr, INVALIDf, 952 INVALIDr, INVALIDr, INVALIDr, 953 _SOC_SER_SKIP_FH2 | _SOC_SER_SKIP_HR3L | _SOC_SER_SKIP_BH 954 }, 955 { _SOC_PARITY_TYPE_ECC, NULL, 956 EGR_XP0_PAR_ERRf, EGR_XP0_PAR_ERRf, 957 INVALIDm, "EP_EDB_XP0_MEM", 958 EGR_EDATABUF_PARITY_CONTROLr, XP0_ECC_ENf, NULL, 959 INVALIDr, INVALIDf, NULL, 960 EGR_XP0_PARITY_STATUSr, NULL, INVALIDf, 961 INVALIDr, INVALIDf, 962 INVALIDr, INVALIDr, INVALIDr, 963 _SOC_SER_SKIP_WH2 964 }, 965 { _SOC_PARITY_TYPE_ECC, NULL, 966 EGR_XP1_PAR_ERRf, EGR_XP1_PAR_ERRf, 967 INVALIDm, "EP_EDB_XP1_MEM", 968 EGR_EDATABUF_PARITY_CONTROLr, XP1_ECC_ENf, NULL, 969 INVALIDr, INVALIDf, NULL, 970 EGR_XP1_PARITY_STATUSr, NULL, INVALIDf, 971 INVALIDr, INVALIDf, 972 INVALIDr, INVALIDr, INVALIDr, 973 _SOC_SER_SKIP_WH2 974 }, 975 { _SOC_PARITY_TYPE_ECC, NULL, 976 EGR_XP2_PAR_ERRf, EGR_XP2_PAR_ERRf, 977 INVALIDm, "EP_EDB_XP2_MEM", 978 EGR_EDATABUF_PARITY_CONTROLr, XP2_ECC_ENf, NULL, 979 INVALIDr, INVALIDf, NULL, 980 EGR_XP2_PARITY_STATUSr, NULL, INVALIDf, 981 INVALIDr, INVALIDf, 982 INVALIDr, INVALIDr, INVALIDr, 983 _SOC_SER_SKIP_WH2 984 }, 985 { _SOC_PARITY_TYPE_ECC, NULL, 986 EGR_XP3_PAR_ERRf, EGR_XP3_PAR_ERRf, 987 INVALIDm, "EP_EDB_XP0_MEM", 988 EGR_EDATABUF_PARITY_CONTROLr, XP3_ECC_ENf, NULL, 989 INVALIDr, INVALIDf, NULL, 990 EGR_XP3_PARITY_STATUSr, NULL, INVALIDf, 991 INVALIDr, INVALIDf, 992 INVALIDr, INVALIDr, INVALIDr, 993 _SOC_SER_SKIP_WH2 994 }, 995 { _SOC_PARITY_TYPE_COUNTER, NULL, 996 EGR_STATS_COUNTER_TABLE_PAR_ERRf, EGR_STATS_COUNTER_TABLE_PAR_ERRf, 997 INVALIDm, "TDBGC0-TDBGC11", 998 EGR_EDATABUF_PARITY_CONTROLr,EGR_STATS_COUNTER_TABLE_PAR_ENf, NULL, 999 INVALIDr, INVALIDf, NULL, 1000 EGR_STATS_COUNTER_TABLE_PARITY_STATUSr, NULL, INVALIDf, 1001 INVALIDr, INVALIDf, 1002 INVALIDr, INVALIDr, INVALIDr, 1003 0 1004 }, 1005 #endif /* _HR3_SER_TEST_EP */ 1006 { _SOC_PARITY_TYPE_NONE }, /* table terminator */ 1007 }; 1008 #if _HR3_SER_TEST_MMU 1009 static _soc_hr3_ser_reg_t cbppkthdr_regs[] = { 1010 { CBPPKTHDR_ERRPTR0r, "CBPPKTHD[0:126]",INVALIDm}, 1011 { CBPPKTHDR_ERRPTR1r, "CBPPKTHD[127:253]",INVALIDm}, 1012 { CBPPKTHDR_ERRPTR2r, "CBPPKTHD[254:286]",INVALIDm}, 1013 { CBPPKTHDR_ERRPTR3r, "CBPPKTHD[287:322]",INVALIDm}, 1014 { INVALIDr } 1015 }; 1016 static _soc_hr3_ser_reg_t wred_regs[] = { 1017 { WRED_MARK_THD_PARITY_ERR_PTRr, "WRED MARK THD", MMU_WRED_MARK_THDm}, 1018 { WRED_DROP_PROFILE_GREEN_PARITY_ERR_PTRr, "WRED DROP PROFILE GREEN", MMU_WRED_DROP_PROFILE_GREENm}, 1019 { WRED_DROP_PROFILE_YELLOW_PARITY_ERR_PTRr, "WRED_DROP_PROFILE YELLOW", MMU_WRED_DROP_PROFILE_YELLOWm}, 1020 { WRED_DROP_PROFILE_RED_PARITY_ERR_PTRr, "WRED DROP PROFILE RED", MMU_WRED_DROP_PROFILE_REDm}, 1021 { WRED_MARK_PROFILE_GREEN_PARITY_ERR_PTRr, "WRED MARK PROFILE GREEN", MMU_WRED_MARK_PROFILE_GREENm}, 1022 { WRED_MARK_PROFILE_YELLOW_PARITY_ERR_PTRr, "WRED MARK PROFILE YELLOW", MMU_WRED_MARK_PROFILE_YELLOWm}, 1023 { WRED_MARK_PROFILE_RED_PARITY_ERR_PTRr, "WRED MARK PROFILE RED", MMU_WRED_MARK_PROFILE_REDm}, 1024 { WRED_AVG_QSIZE_PARITY_ERR_PTRr, "WRED AVG QSIZE", MMU_WRED_AVG_QSIZEm}, 1025 { WRED_CONFIG_PARITY_ERR_PTRr, "WRED CONFIG", MMU_WRED_CONFIGm}, 1026 { INVALIDr } 1027 }; 1028 static _soc_hr3_ser_reg_t ipmcgroup_regs[] = { 1029 { IPMC_GROUP_ERR_PTRr, "", INVALIDm }, 1030 { IPMC_GROUP_ERR_PTRr, "", INVALIDm }, 1031 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP2", MMU_IPMC_GROUP_TBL2m}, 1032 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP3", MMU_IPMC_GROUP_TBL3m}, 1033 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP4", MMU_IPMC_GROUP_TBL4m}, 1034 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP5", MMU_IPMC_GROUP_TBL5m}, 1035 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP6", MMU_IPMC_GROUP_TBL6m}, 1036 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP7", MMU_IPMC_GROUP_TBL7m}, 1037 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP8", MMU_IPMC_GROUP_TBL8m}, 1038 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP9", MMU_IPMC_GROUP_TBL9m}, 1039 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP10", MMU_IPMC_GROUP_TBL10m}, 1040 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP11", MMU_IPMC_GROUP_TBL11m}, 1041 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP12", MMU_IPMC_GROUP_TBL12m}, 1042 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP13", MMU_IPMC_GROUP_TBL13m}, 1043 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP14", MMU_IPMC_GROUP_TBL14m}, 1044 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP15", MMU_IPMC_GROUP_TBL15m}, 1045 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP16", MMU_IPMC_GROUP_TBL16m}, 1046 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP17", MMU_IPMC_GROUP_TBL17m}, 1047 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP18", MMU_IPMC_GROUP_TBL18m}, 1048 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP19", MMU_IPMC_GROUP_TBL19m}, 1049 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP20", MMU_IPMC_GROUP_TBL20m}, 1050 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP21", MMU_IPMC_GROUP_TBL21m}, 1051 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP22", MMU_IPMC_GROUP_TBL22m}, 1052 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP23", MMU_IPMC_GROUP_TBL23m}, 1053 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP24", MMU_IPMC_GROUP_TBL24m}, 1054 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP25", MMU_IPMC_GROUP_TBL25m}, 1055 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP26", MMU_IPMC_GROUP_TBL26m}, 1056 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP27", MMU_IPMC_GROUP_TBL27m}, 1057 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP28", MMU_IPMC_GROUP_TBL28m}, 1058 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP29", MMU_IPMC_GROUP_TBL29m}, 1059 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP30", MMU_IPMC_GROUP_TBL30m}, 1060 { IPMC_GROUP_ERR_PTRr, "IPMC_GROUP31", MMU_IPMC_GROUP_TBL31m}, 1061 { INVALIDr } 1062 }; 1063 #endif /*_HR3_SER_TEST_MMU */ 1064 1065 static _soc_hr3_ser_info_t _soc_hr3_mmu_ser_info[] = { 1066 #if _HR3_SER_TEST_MMU 1067 { _SOC_PARITY_TYPE_MMU_ECC, NULL, 1068 CELLECCERRORINTMASKf, CELLECCERRORf, 1069 INVALIDm, NULL, 1070 INVALIDr, INVALIDf, NULL, 1071 INVALIDr, INVALIDf, NULL, 1072 CBPCELLERRPTRr, NULL, INVALIDf, 1073 INVALIDr ,CELLECCERROR_CLRf, 1074 INVALIDr, INVALIDr, INVALIDr, 1075 0 1076 }, 1077 { _SOC_PARITY_TYPE_MMU_ECC, NULL, 1078 CBPCELLHDRPARITYERRORINTMASKf, CBPCELLHDRPARITYERRORf, 1079 INVALIDm, NULL, 1080 INVALIDr, INVALIDf, NULL, 1081 INVALIDr, INVALIDf, NULL, 1082 CBPCELLHDRPARITYERRPTRr, NULL, INVALIDf, 1083 INVALIDr, CBPCELLHDRPARITYERROR_CLRf, 1084 INVALIDr, INVALIDr, INVALIDr, 1085 0 1086 }, 1087 { _SOC_PARITY_TYPE_MMU_ECC, NULL, 1088 CFAPPARITYERRORINTMASKf, CFAPPARITYERRORf, 1089 INVALIDm, NULL, 1090 INVALIDr, INVALIDf, NULL, 1091 INVALIDr, INVALIDf, NULL, 1092 CFAPPARITYERRORPTRr, NULL, INVALIDf, 1093 INVALIDr, CFAPPARITYERROR_CLRf, 1094 INVALIDr, INVALIDr, INVALIDr, 1095 0 1096 }, 1097 { _SOC_PARITY_TYPE_MMU_ECC, NULL, 1098 CCPPARITYERRORINTMASKf, CCPPARITYERRORf, 1099 INVALIDm, NULL, 1100 INVALIDr, INVALIDf, NULL, 1101 INVALIDr, INVALIDf, NULL, 1102 CCPPARITYERRORPTRr, NULL, INVALIDf, 1103 INVALIDr, CCPPARITYERROR_CLRf, 1104 INVALIDr, INVALIDr, INVALIDr, 1105 0 1106 }, 1107 { _SOC_PARITY_TYPE_MMU_ECC_CBPH, NULL, 1108 CBPPKTHDRPARITYERRORINTMASKf, CBPPKTHDRPARITYERRORf, 1109 INVALIDm, NULL, 1110 INVALIDr, INVALIDf, NULL, 1111 INVALIDr, INVALIDf, NULL, 1112 INVALIDr, cbppkthdr_regs, INVALIDf, 1113 INVALIDr, CBPPKTHDRPARITYERROR_CLRf, 1114 CBPPKTHDR_ERR_VLDr, INVALIDr, CBPPKTHDR_ERR_CLRr, 1115 0 1116 }, 1117 { _SOC_PARITY_TYPE_MMU_ECC_XQ, NULL, 1118 XQPARITYERRORINTMASKf, XQPARITYERRORf, 1119 INVALIDm, NULL, 1120 INVALIDr, INVALIDf, NULL, 1121 INVALIDr, INVALIDf, NULL, 1122 XQPARITYERRORPTRr, NULL, INVALIDf, 1123 INVALIDr, XQPARITYERROR_CLRf, 1124 XQ_ERR_VLDr, XQ_MULTI_ERRr, XQ_ERR_CLRr, 1125 0 1126 }, 1127 { _SOC_PARITY_TYPE_MMU_ECC_XQ, NULL, 1128 XQFLLPARITYERRORINTMASKf, XQFLLPARITYERRORf, 1129 INVALIDm, NULL, 1130 INVALIDr, INVALIDf, NULL, 1131 INVALIDr, INVALIDf, NULL, 1132 XQFLLPARITYERRORPTRr, NULL, INVALIDf, 1133 INVALIDr, XQFLLPARITYERROR_CLRf, 1134 XQFLL_ERR_VLDr, XQFLL_MULTI_ERRr, XQFLL_ERR_CLRr, 1135 0 1136 }, 1137 { _SOC_PARITY_TYPE_MMU_PAR_E2EFC, NULL, 1138 E2EFCPARITYERRORINTMASKf, E2EFCPARITYERRORf, 1139 INVALIDm, NULL, 1140 INVALIDr, INVALIDf, NULL, 1141 INVALIDr, INVALIDf, NULL, 1142 E2EFC_PARITYERRORPTRr, NULL, INVALIDf, 1143 INVALIDr, E2EFCPARITYERROR_CLRf, 1144 INVALIDr, INVALIDr, INVALIDr, 1145 0 1146 }, 1147 { _SOC_PARITY_TYPE_MMU_PAR_WRED, NULL, 1148 WREDPARITYERRORINTMASKf, WREDPARITYERRORf, 1149 MMU_WRED_MARK_THDm, NULL, 1150 INVALIDr, INVALIDf, NULL, 1151 INVALIDr, INVALIDf, NULL, 1152 INVALIDr, wred_regs, INVALIDf, 1153 INVALIDr, WREDPARITYERROR_CLRf, 1154 WRED_PARITY_ERR_STATUSr, INVALIDr, WRED_ERR_CLRr, 1155 0 1156 }, 1157 { _SOC_PARITY_TYPE_MMU_PAR_WRED, NULL, 1158 WREDPARITYERRORINTMASKf, WREDPARITYERRORf, 1159 MMU_WRED_DROP_PROFILE_GREENm, NULL, 1160 INVALIDr, INVALIDf, NULL, 1161 INVALIDr, INVALIDf, NULL, 1162 INVALIDr, wred_regs, INVALIDf, 1163 INVALIDr, WREDPARITYERROR_CLRf, 1164 WRED_PARITY_ERR_STATUSr, INVALIDr, WRED_ERR_CLRr, 1165 0 1166 }, 1167 { _SOC_PARITY_TYPE_MMU_PAR_WRED, NULL, 1168 WREDPARITYERRORINTMASKf, WREDPARITYERRORf, 1169 MMU_WRED_DROP_PROFILE_YELLOWm, NULL, 1170 INVALIDr, INVALIDf, NULL, 1171 INVALIDr, INVALIDf, NULL, 1172 INVALIDr, wred_regs, INVALIDf, 1173 INVALIDr, WREDPARITYERROR_CLRf, 1174 WRED_PARITY_ERR_STATUSr, INVALIDr, WRED_ERR_CLRr, 1175 0 1176 }, 1177 { _SOC_PARITY_TYPE_MMU_PAR_WRED, NULL, 1178 WREDPARITYERRORINTMASKf, WREDPARITYERRORf, 1179 MMU_WRED_DROP_PROFILE_REDm, NULL, 1180 INVALIDr, INVALIDf, NULL, 1181 INVALIDr, INVALIDf, NULL, 1182 INVALIDr, wred_regs, INVALIDf, 1183 INVALIDr, WREDPARITYERROR_CLRf, 1184 WRED_PARITY_ERR_STATUSr, INVALIDr, WRED_ERR_CLRr, 1185 0 1186 }, 1187 { _SOC_PARITY_TYPE_MMU_PAR_WRED, NULL, 1188 WREDPARITYERRORINTMASKf, WREDPARITYERRORf, 1189 MMU_WRED_MARK_PROFILE_GREENm, NULL, 1190 INVALIDr, INVALIDf, NULL, 1191 INVALIDr, INVALIDf, NULL, 1192 INVALIDr, wred_regs, INVALIDf, 1193 INVALIDr, WREDPARITYERROR_CLRf, 1194 WRED_PARITY_ERR_STATUSr, INVALIDr, WRED_ERR_CLRr, 1195 0 1196 }, 1197 { _SOC_PARITY_TYPE_MMU_PAR_WRED, NULL, 1198 WREDPARITYERRORINTMASKf, WREDPARITYERRORf, 1199 MMU_WRED_MARK_PROFILE_YELLOWm, NULL, 1200 INVALIDr, INVALIDf, NULL, 1201 INVALIDr, INVALIDf, NULL, 1202 INVALIDr, wred_regs, INVALIDf, 1203 INVALIDr, WREDPARITYERROR_CLRf, 1204 WRED_PARITY_ERR_STATUSr, INVALIDr, WRED_ERR_CLRr, 1205 0 1206 }, 1207 { _SOC_PARITY_TYPE_MMU_PAR_WRED, NULL, 1208 WREDPARITYERRORINTMASKf, WREDPARITYERRORf, 1209 MMU_WRED_MARK_PROFILE_REDm, NULL, 1210 INVALIDr, INVALIDf, NULL, 1211 INVALIDr, INVALIDf, NULL, 1212 INVALIDr, wred_regs, INVALIDf, 1213 INVALIDr, WREDPARITYERROR_CLRf, 1214 WRED_PARITY_ERR_STATUSr, INVALIDr, WRED_ERR_CLRr, 1215 0 1216 }, 1217 { _SOC_PARITY_TYPE_MMU_PAR_WRED, NULL, 1218 WREDPARITYERRORINTMASKf, WREDPARITYERRORf, 1219 MMU_WRED_AVG_QSIZEm, NULL, 1220 INVALIDr, INVALIDf, NULL, 1221 INVALIDr, INVALIDf, NULL, 1222 INVALIDr, wred_regs, INVALIDf, 1223 INVALIDr, WREDPARITYERROR_CLRf, 1224 WRED_PARITY_ERR_STATUSr, INVALIDr, WRED_ERR_CLRr, 1225 0 1226 }, 1227 { _SOC_PARITY_TYPE_MMU_PAR_WRED, NULL, 1228 WREDPARITYERRORINTMASKf, WREDPARITYERRORf, 1229 MMU_WRED_CONFIGm, NULL, 1230 INVALIDr, INVALIDf, NULL, 1231 INVALIDr, INVALIDf, NULL, 1232 INVALIDr, wred_regs, INVALIDf, 1233 INVALIDr, WREDPARITYERROR_CLRf, 1234 WRED_PARITY_ERR_STATUSr, INVALIDr, WRED_ERR_CLRr, 1235 0 1236 }, 1237 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 1238 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 1239 MMU_IPMC_GROUP_TBL2m, NULL, 1240 INVALIDr, INVALIDf, NULL, 1241 INVALIDr, INVALIDf, NULL, 1242 INVALIDr, ipmcgroup_regs, INVALIDf, 1243 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 1244 IPMC_GROUP_ERR_VLDr, IPMC_GROUP_MULTI_ERRr, IPMC_GROUP_ERR_CLRr, 1245 0 1246 }, 1247 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 1248 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 1249 MMU_IPMC_GROUP_TBL3m, NULL, 1250 INVALIDr, INVALIDf, NULL, 1251 INVALIDr, INVALIDf, NULL, 1252 INVALIDr, ipmcgroup_regs, INVALIDf, 1253 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 1254 IPMC_GROUP_ERR_VLDr, IPMC_GROUP_MULTI_ERRr, IPMC_GROUP_ERR_CLRr, 1255 0 1256 }, 1257 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 1258 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 1259 MMU_IPMC_GROUP_TBL4m, NULL, 1260 INVALIDr, INVALIDf, NULL, 1261 INVALIDr, INVALIDf, NULL, 1262 INVALIDr, ipmcgroup_regs, INVALIDf, 1263 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 1264 IPMC_GROUP_ERR_VLDr, IPMC_GROUP_MULTI_ERRr, IPMC_GROUP_ERR_CLRr, 1265 0 1266 }, 1267 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 1268 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 1269 MMU_IPMC_GROUP_TBL5m, NULL, 1270 INVALIDr, INVALIDf, NULL, 1271 INVALIDr, INVALIDf, NULL, 1272 INVALIDr, ipmcgroup_regs, INVALIDf, 1273 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 1274 IPMC_GROUP_ERR_VLDr, IPMC_GROUP_MULTI_ERRr, IPMC_GROUP_ERR_CLRr, 1275 0 1276 }, 1277 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 1278 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 1279 MMU_IPMC_GROUP_TBL6m, NULL, 1280 INVALIDr, INVALIDf, NULL, 1281 INVALIDr, INVALIDf, NULL, 1282 INVALIDr, ipmcgroup_regs, INVALIDf, 1283 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 1284 IPMC_GROUP_ERR_VLDr, IPMC_GROUP_MULTI_ERRr, IPMC_GROUP_ERR_CLRr, 1285 0 1286 }, 1287 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 1288 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 1289 MMU_IPMC_GROUP_TBL7m, NULL, 1290 INVALIDr, INVALIDf, NULL, 1291 INVALIDr, INVALIDf, NULL, 1292 INVALIDr, ipmcgroup_regs, INVALIDf, 1293 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 1294 IPMC_GROUP_ERR_VLDr, IPMC_GROUP_MULTI_ERRr, IPMC_GROUP_ERR_CLRr, 1295 0 1296 }, 1297 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 1298 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 1299 MMU_IPMC_GROUP_TBL8m, NULL, 1300 INVALIDr, INVALIDf, NULL, 1301 INVALIDr, INVALIDf, NULL, 1302 INVALIDr, ipmcgroup_regs, INVALIDf, 1303 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 1304 IPMC_GROUP_ERR_VLDr, IPMC_GROUP_MULTI_ERRr, IPMC_GROUP_ERR_CLRr, 1305 0 1306 }, 1307 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 1308 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 1309 MMU_IPMC_GROUP_TBL9m, NULL, 1310 INVALIDr, INVALIDf, NULL, 1311 INVALIDr, INVALIDf, NULL, 1312 INVALIDr, ipmcgroup_regs, INVALIDf, 1313 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 1314 IPMC_GROUP_ERR_VLDr, IPMC_GROUP_MULTI_ERRr, IPMC_GROUP_ERR_CLRr, 1315 0 1316 }, 1317 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 1318 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 1319 MMU_IPMC_GROUP_TBL10m, NULL, 1320 INVALIDr, INVALIDf, NULL, 1321 INVALIDr, INVALIDf, NULL, 1322 INVALIDr, ipmcgroup_regs, INVALIDf, 1323 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 1324 IPMC_GROUP_ERR_VLDr, IPMC_GROUP_MULTI_ERRr, IPMC_GROUP_ERR_CLRr, 1325 0 1326 }, 1327 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 1328 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 1329 MMU_IPMC_GROUP_TBL11m, NULL, 1330 INVALIDr, INVALIDf, NULL, 1331 INVALIDr, INVALIDf, NULL, 1332 INVALIDr, ipmcgroup_regs, INVALIDf, 1333 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 1334 IPMC_GROUP_ERR_VLDr, IPMC_GROUP_MULTI_ERRr, IPMC_GROUP_ERR_CLRr, 1335 0 1336 }, 1337 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 1338 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 1339 MMU_IPMC_GROUP_TBL12m, NULL, 1340 INVALIDr, INVALIDf, NULL, 1341 INVALIDr, INVALIDf, NULL, 1342 INVALIDr, ipmcgroup_regs, INVALIDf, 1343 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 1344 IPMC_GROUP_ERR_VLDr, IPMC_GROUP_MULTI_ERRr, IPMC_GROUP_ERR_CLRr, 1345 0 1346 }, 1347 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 1348 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 1349 MMU_IPMC_GROUP_TBL13m, NULL, 1350 INVALIDr, INVALIDf, NULL, 1351 INVALIDr, INVALIDf, NULL, 1352 INVALIDr, ipmcgroup_regs, INVALIDf, 1353 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 1354 IPMC_GROUP_ERR_VLDr, IPMC_GROUP_MULTI_ERRr, IPMC_GROUP_ERR_CLRr, 1355 0 1356 }, 1357 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 1358 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 1359 MMU_IPMC_GROUP_TBL14m, NULL, 1360 INVALIDr, INVALIDf, NULL, 1361 INVALIDr, INVALIDf, NULL, 1362 INVALIDr, ipmcgroup_regs, INVALIDf, 1363 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 1364 IPMC_GROUP_ERR_VLDr, IPMC_GROUP_MULTI_ERRr, IPMC_GROUP_ERR_CLRr, 1365 0 1366 }, 1367 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 1368 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 1369 MMU_IPMC_GROUP_TBL15m, NULL, 1370 INVALIDr, INVALIDf, NULL, 1371 INVALIDr, INVALIDf, NULL, 1372 INVALIDr, ipmcgroup_regs, INVALIDf, 1373 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 1374 IPMC_GROUP_ERR_VLDr, IPMC_GROUP_MULTI_ERRr, IPMC_GROUP_ERR_CLRr, 1375 0 1376 }, 1377 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 1378 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 1379 MMU_IPMC_GROUP_TBL16m, NULL, 1380 INVALIDr, INVALIDf, NULL, 1381 INVALIDr, INVALIDf, NULL, 1382 INVALIDr, ipmcgroup_regs, INVALIDf, 1383 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 1384 IPMC_GROUP_ERR_VLDr, IPMC_GROUP_MULTI_ERRr, IPMC_GROUP_ERR_CLRr, 1385 0 1386 }, 1387 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 1388 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 1389 MMU_IPMC_GROUP_TBL17m, NULL, 1390 INVALIDr, INVALIDf, NULL, 1391 INVALIDr, INVALIDf, NULL, 1392 INVALIDr, ipmcgroup_regs, INVALIDf, 1393 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 1394 IPMC_GROUP_ERR_VLDr, IPMC_GROUP_MULTI_ERRr, IPMC_GROUP_ERR_CLRr, 1395 0 1396 }, 1397 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 1398 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 1399 MMU_IPMC_GROUP_TBL18m, NULL, 1400 INVALIDr, INVALIDf, NULL, 1401 INVALIDr, INVALIDf, NULL, 1402 INVALIDr, ipmcgroup_regs, INVALIDf, 1403 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 1404 IPMC_GROUP_ERR_VLDr, IPMC_GROUP_MULTI_ERRr, IPMC_GROUP_ERR_CLRr, 1405 0 1406 }, 1407 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 1408 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 1409 MMU_IPMC_GROUP_TBL19m, NULL, 1410 INVALIDr, INVALIDf, NULL, 1411 INVALIDr, INVALIDf, NULL, 1412 INVALIDr, ipmcgroup_regs, INVALIDf, 1413 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 1414 IPMC_GROUP_ERR_VLDr, IPMC_GROUP_MULTI_ERRr, IPMC_GROUP_ERR_CLRr, 1415 0 1416 }, 1417 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 1418 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 1419 MMU_IPMC_GROUP_TBL20m, NULL, 1420 INVALIDr, INVALIDf, NULL, 1421 INVALIDr, INVALIDf, NULL, 1422 INVALIDr, ipmcgroup_regs, INVALIDf, 1423 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 1424 IPMC_GROUP_ERR_VLDr, IPMC_GROUP_MULTI_ERRr, IPMC_GROUP_ERR_CLRr, 1425 0 1426 }, 1427 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 1428 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 1429 MMU_IPMC_GROUP_TBL21m, NULL, 1430 INVALIDr, INVALIDf, NULL, 1431 INVALIDr, INVALIDf, NULL, 1432 INVALIDr, ipmcgroup_regs, INVALIDf, 1433 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 1434 IPMC_GROUP_ERR_VLDr, IPMC_GROUP_MULTI_ERRr, IPMC_GROUP_ERR_CLRr, 1435 0 1436 }, 1437 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 1438 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 1439 MMU_IPMC_GROUP_TBL22m, NULL, 1440 INVALIDr, INVALIDf, NULL, 1441 INVALIDr, INVALIDf, NULL, 1442 INVALIDr, ipmcgroup_regs, INVALIDf, 1443 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 1444 IPMC_GROUP_ERR_VLDr, IPMC_GROUP_MULTI_ERRr, IPMC_GROUP_ERR_CLRr, 1445 0 1446 }, 1447 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 1448 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 1449 MMU_IPMC_GROUP_TBL23m, NULL, 1450 INVALIDr, INVALIDf, NULL, 1451 INVALIDr, INVALIDf, NULL, 1452 INVALIDr, ipmcgroup_regs, INVALIDf, 1453 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 1454 IPMC_GROUP_ERR_VLDr, IPMC_GROUP_MULTI_ERRr, IPMC_GROUP_ERR_CLRr, 1455 0 1456 }, 1457 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 1458 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 1459 MMU_IPMC_GROUP_TBL24m, NULL, 1460 INVALIDr, INVALIDf, NULL, 1461 INVALIDr, INVALIDf, NULL, 1462 INVALIDr, ipmcgroup_regs, INVALIDf, 1463 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 1464 IPMC_GROUP_ERR_VLDr, IPMC_GROUP_MULTI_ERRr, IPMC_GROUP_ERR_CLRr, 1465 0 1466 }, 1467 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 1468 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 1469 MMU_IPMC_GROUP_TBL25m, NULL, 1470 INVALIDr, INVALIDf, NULL, 1471 INVALIDr, INVALIDf, NULL, 1472 INVALIDr, ipmcgroup_regs, INVALIDf, 1473 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 1474 IPMC_GROUP_ERR_VLDr, IPMC_GROUP_MULTI_ERRr, IPMC_GROUP_ERR_CLRr, 1475 0 1476 }, 1477 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 1478 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 1479 MMU_IPMC_GROUP_TBL26m, NULL, 1480 INVALIDr, INVALIDf, NULL, 1481 INVALIDr, INVALIDf, NULL, 1482 INVALIDr, ipmcgroup_regs, INVALIDf, 1483 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 1484 IPMC_GROUP_ERR_VLDr, IPMC_GROUP_MULTI_ERRr, IPMC_GROUP_ERR_CLRr, 1485 0 1486 }, 1487 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 1488 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 1489 MMU_IPMC_GROUP_TBL27m, NULL, 1490 INVALIDr, INVALIDf, NULL, 1491 INVALIDr, INVALIDf, NULL, 1492 INVALIDr, ipmcgroup_regs, INVALIDf, 1493 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 1494 IPMC_GROUP_ERR_VLDr, IPMC_GROUP_MULTI_ERRr, IPMC_GROUP_ERR_CLRr, 1495 0 1496 }, 1497 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 1498 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 1499 MMU_IPMC_GROUP_TBL28m, NULL, 1500 INVALIDr, INVALIDf, NULL, 1501 INVALIDr, INVALIDf, NULL, 1502 INVALIDr, ipmcgroup_regs, INVALIDf, 1503 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 1504 IPMC_GROUP_ERR_VLDr, IPMC_GROUP_MULTI_ERRr, IPMC_GROUP_ERR_CLRr, 1505 0 1506 }, 1507 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 1508 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 1509 MMU_IPMC_GROUP_TBL29m, NULL, 1510 INVALIDr, INVALIDf, NULL, 1511 INVALIDr, INVALIDf, NULL, 1512 INVALIDr, ipmcgroup_regs, INVALIDf, 1513 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 1514 IPMC_GROUP_ERR_VLDr, IPMC_GROUP_MULTI_ERRr, IPMC_GROUP_ERR_CLRr, 1515 0 1516 }, 1517 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 1518 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 1519 MMU_IPMC_GROUP_TBL30m, NULL, 1520 INVALIDr, INVALIDf, NULL, 1521 INVALIDr, INVALIDf, NULL, 1522 INVALIDr, ipmcgroup_regs, INVALIDf, 1523 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 1524 IPMC_GROUP_ERR_VLDr, IPMC_GROUP_MULTI_ERRr, IPMC_GROUP_ERR_CLRr, 1525 0 1526 }, 1527 { _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP, NULL, 1528 IPMCGROUPPARITYERRORINTMASKf, IPMCGROUPPARITYERRORf, 1529 MMU_IPMC_GROUP_TBL31m, NULL, 1530 INVALIDr, INVALIDf, NULL, 1531 INVALIDr, INVALIDf, NULL, 1532 INVALIDr, ipmcgroup_regs, INVALIDf, 1533 INVALIDr, IPMCGROUPPARITYERROR_CLRf, 1534 IPMC_GROUP_ERR_VLDr, IPMC_GROUP_MULTI_ERRr, IPMC_GROUP_ERR_CLRr, 1535 0 1536 }, 1537 1538 { _SOC_PARITY_TYPE_MMU_ECC_IPMCVLAN, NULL, 1539 IPMCVLANXPORTPARITYERRORINTMASKf,IPMCVLANXPORTPARITYERRORf, 1540 MMU_IPMC_VLAN_TBLm, NULL, 1541 INVALIDr, INVALIDf, NULL, 1542 INVALIDr, INVALIDf, NULL, 1543 IPMCPARITYERRORPTRr, NULL, INVALIDf, 1544 INVALIDr, IPMCVLANXPORTPARITYERROR_CLRf, 1545 INVALIDr, INVALIDr, INVALIDr, 1546 0 1547 }, 1548 #endif /*_HR3_SER_TEST_MMU */ 1549 { _SOC_PARITY_TYPE_NONE }, /* table terminator */ 1550 1551 }; 1552 1553 static _soc_hr3_ser_info_t _soc_hr3_mmu_top_ser_info[] = { 1554 { _SOC_PARITY_TYPE_MMU_SER, _soc_hr3_mmu_ser_info, 1555 INVALIDf, INVALIDf, 1556 INVALIDm, "MMU MEM PAR", 1557 MISCCONFIGr, PARITY_CHECK_ENf, NULL, 1558 MEMFAILINTMASKr, INVALIDf, NULL, 1559 MEMFAILINTSTATUSr, NULL, INVALIDf, 1560 MEMFAILINT_CLRr, INVALIDf, 1561 INVALIDr, INVALIDr, INVALIDr, 1562 0 1563 }, 1564 { _SOC_PARITY_TYPE_NONE }, /* table terminator */ 1565 }; 1566 1567 static _soc_hr3_ser_info_t _soc_hr3_xlport_ser_info[] = { 1568 { _SOC_PARITY_TYPE_ECC, NULL, 1569 MIB_RX_MEM_ERRf, MIB_RX_MEM_ERRf, 1570 INVALIDm, NULL, 1571 XLPORT_ECC_CONTROLr, MIB_RSC_MEM_ENf, NULL, 1572 INVALIDr, INVALIDf, NULL, 1573 XLPORT_MIB_RSC0_ECC_STATUSr, NULL, ECC_ERRf, 1574 XLPORT_INTR_STATUSr, MIB_RX_MEM_ERRf, 1575 INVALIDr, INVALIDr, INVALIDr, 1576 0 1577 }, 1578 { _SOC_PARITY_TYPE_ECC, NULL, 1579 MIB_TX_MEM_ERRf, MIB_TX_MEM_ERRf, 1580 INVALIDm, NULL, 1581 XLPORT_ECC_CONTROLr, MIB_TSC_MEM_ENf, NULL, 1582 INVALIDr, INVALIDf, NULL, 1583 XLPORT_MIB_TSC0_ECC_STATUSr, NULL, ECC_ERRf, 1584 XLPORT_INTR_STATUSr, MIB_TX_MEM_ERRf, 1585 INVALIDr, INVALIDr, INVALIDr, 1586 0 1587 }, 1588 { _SOC_PARITY_TYPE_NONE }, /* table terminator */ 1589 }; 1590 1591 static _soc_hr3_ser_info_t _soc_hr3_pgw_xlport_ser_info[] = { 1592 { _SOC_PARITY_TYPE_PORT_XL, _soc_hr3_xlport_ser_info, 1593 PM_INTRf, PM_INTRf, 1594 INVALIDm, "XL PORT INTR", 1595 INVALIDr, INVALIDf, NULL, 1596 XLPORT_INTR_ENABLEr, INVALIDf, NULL, 1597 XLPORT_INTR_STATUSr, NULL, INVALIDf, 1598 INVALIDr, INVALIDf, 1599 INVALIDr, INVALIDr, INVALIDr, 1600 0 1601 }, 1602 { _SOC_PARITY_TYPE_ECC, NULL, 1603 RXFIFO_DBEf, RXFIFO_DBEf, 1604 INVALIDm, NULL, 1605 PGW_XL_ECC_CONTROLr, RXFIFO_ECC_ENABLEf, NULL, 1606 INVALIDr, INVALIDf, NULL, 1607 PGW_XL_RXFIFO_ECC_DBE_STATUSr, NULL, ECC_ERRf, 1608 INVALIDr, INVALIDf, 1609 INVALIDr, INVALIDr, INVALIDr, 1610 0 1611 }, 1612 { _SOC_PARITY_TYPE_ECC, NULL, 1613 TXFIFO0_DBEf, TXFIFO0_DBEf, 1614 INVALIDm, NULL, 1615 PGW_XL_ECC_CONTROLr, TXFIFO_ECC_ENf, NULL, 1616 INVALIDr, INVALIDf, NULL, 1617 PGW_XL_TXFIFO0_ECC_DBE_STATUSr, NULL, ECC_ERRf, 1618 INVALIDr, INVALIDf, 1619 INVALIDr, INVALIDr, INVALIDr, 1620 0 1621 }, 1622 { _SOC_PARITY_TYPE_ECC, NULL, 1623 TXFIFO1_DBEf, TXFIFO1_DBEf, 1624 INVALIDm, NULL, 1625 PGW_XL_ECC_CONTROLr, TXFIFO_ECC_ENf, NULL, 1626 INVALIDr, INVALIDf, NULL, 1627 PGW_XL_TXFIFO1_ECC_DBE_STATUSr, NULL, ECC_ERRf, 1628 INVALIDr, INVALIDf, 1629 INVALIDr, INVALIDr, INVALIDr, 1630 0 1631 }, 1632 { _SOC_PARITY_TYPE_ECC, NULL, 1633 TXFIFO2_DBEf, TXFIFO2_DBEf, 1634 INVALIDm, NULL, 1635 PGW_XL_ECC_CONTROLr, TXFIFO_ECC_ENf, NULL, 1636 INVALIDr, INVALIDf, NULL, 1637 PGW_XL_TXFIFO2_ECC_DBE_STATUSr, NULL, ECC_ERRf, 1638 INVALIDr, INVALIDf, 1639 INVALIDr, INVALIDr, INVALIDr, 1640 0 1641 }, 1642 { _SOC_PARITY_TYPE_ECC, NULL, 1643 TXFIFO3_DBEf, TXFIFO3_DBEf, 1644 INVALIDm, NULL, 1645 PGW_XL_ECC_CONTROLr, TXFIFO_ECC_ENf, NULL, 1646 INVALIDr, INVALIDf, NULL, 1647 PGW_XL_TXFIFO3_ECC_DBE_STATUSr, NULL, ECC_ERRf, 1648 INVALIDr, INVALIDf, 1649 INVALIDr, INVALIDr, INVALIDr, 1650 0 1651 }, 1652 { _SOC_PARITY_TYPE_ECC, NULL, 1653 TXFIFO0_DBE_Hf, TXFIFO0_DBE_Hf, 1654 INVALIDm, NULL, 1655 PGW_XL_ECC_CONTROLr, TXFIFO_ECC_ENf, NULL, 1656 INVALIDr, INVALIDf, NULL, 1657 PGW_XL_TXFIFO0_ECC_DBE_STATUS_Hr, NULL, ECC_ERRf, 1658 INVALIDr, INVALIDf, 1659 INVALIDr, INVALIDr, INVALIDr, 1660 0 1661 }, 1662 { _SOC_PARITY_TYPE_ECC, NULL, 1663 TXFIFO1_DBE_Hf, TXFIFO1_DBE_Hf, 1664 INVALIDm, NULL, 1665 PGW_XL_ECC_CONTROLr, TXFIFO_ECC_ENf, NULL, 1666 INVALIDr, INVALIDf, NULL, 1667 PGW_XL_TXFIFO1_ECC_DBE_STATUS_Hr, NULL, ECC_ERRf, 1668 INVALIDr, INVALIDf, 1669 INVALIDr, INVALIDr, INVALIDr, 1670 0 1671 }, 1672 { _SOC_PARITY_TYPE_ECC, NULL, 1673 TXFIFO2_DBE_Hf, TXFIFO2_DBE_Hf, 1674 INVALIDm, NULL, 1675 PGW_XL_ECC_CONTROLr, TXFIFO_ECC_ENf, NULL, 1676 INVALIDr, INVALIDf, NULL, 1677 PGW_XL_TXFIFO2_ECC_DBE_STATUS_Hr, NULL, ECC_ERRf, 1678 INVALIDr, INVALIDf, 1679 INVALIDr, INVALIDr, INVALIDr, 1680 0 1681 }, 1682 { _SOC_PARITY_TYPE_ECC, NULL, 1683 TXFIFO3_DBE_Hf, TXFIFO3_DBE_Hf, 1684 INVALIDm, NULL, 1685 PGW_XL_ECC_CONTROLr, TXFIFO_ECC_ENf, NULL, 1686 INVALIDr, INVALIDf, NULL, 1687 PGW_XL_TXFIFO3_ECC_DBE_STATUS_Hr, NULL, ECC_ERRf, 1688 INVALIDr, INVALIDf, 1689 INVALIDr, INVALIDr, INVALIDr, 1690 0 1691 }, 1692 { _SOC_PARITY_TYPE_NONE }, /* table terminator */ 1693 }; 1694 1695 static _soc_hr3_ser_info_t _soc_hr3_pgw_gport_ser_info[] = { 1696 { _SOC_PARITY_TYPE_ECC, NULL, 1697 TXFIFO0_DBEf, TXFIFO0_DBEf, 1698 INVALIDm, NULL, 1699 PGW_GE_ECC_CONTROLr, TXFIFO_ECC_ENf, NULL, 1700 INVALIDr, INVALIDf, NULL, 1701 PGW_GE_TXFIFO0_ECC_DBE_STATUSr, NULL, ECC_ERRf, 1702 INVALIDr, INVALIDf, 1703 INVALIDr, INVALIDr, INVALIDr, 1704 0 1705 }, 1706 { _SOC_PARITY_TYPE_ECC, NULL, 1707 TXFIFO1_DBEf, TXFIFO1_DBEf, 1708 INVALIDm, NULL, 1709 PGW_GE_ECC_CONTROLr, TXFIFO_ECC_ENf, NULL, 1710 INVALIDr, INVALIDf, NULL, 1711 PGW_GE_TXFIFO1_ECC_DBE_STATUSr, NULL, ECC_ERRf, 1712 INVALIDr, INVALIDf, 1713 INVALIDr, INVALIDr, INVALIDr, 1714 0 1715 }, 1716 { _SOC_PARITY_TYPE_ECC, NULL, 1717 TXFIFO2_DBEf, TXFIFO2_DBEf, 1718 INVALIDm, NULL, 1719 PGW_GE_ECC_CONTROLr, TXFIFO_ECC_ENf, NULL, 1720 INVALIDr, INVALIDf, NULL, 1721 PGW_GE_TXFIFO2_ECC_DBE_STATUSr, NULL, ECC_ERRf, 1722 INVALIDr, INVALIDf, 1723 INVALIDr, INVALIDr, INVALIDr, 1724 0 1725 }, 1726 { _SOC_PARITY_TYPE_ECC, NULL, 1727 TXFIFO3_DBEf, TXFIFO3_DBEf, 1728 INVALIDm, NULL, 1729 PGW_GE_ECC_CONTROLr, TXFIFO_ECC_ENf, NULL, 1730 INVALIDr, INVALIDf, NULL, 1731 PGW_GE_TXFIFO3_ECC_DBE_STATUSr, NULL, ECC_ERRf, 1732 INVALIDr, INVALIDf, 1733 INVALIDr, INVALIDr, INVALIDr, 1734 0 1735 }, 1736 { _SOC_PARITY_TYPE_ECC, NULL, 1737 RXFIFO0_DBEf, RXFIFO0_DBEf, 1738 INVALIDm, NULL, 1739 PGW_GE_ECC_CONTROLr, RXFIFO_ECC_ENABLEf, NULL, 1740 INVALIDr, INVALIDf, NULL, 1741 PGW_GE_RXFIFO0_ECC_DBE_STATUSr, NULL, ECC_ERRf, 1742 INVALIDr, INVALIDf, 1743 INVALIDr, INVALIDr, INVALIDr, 1744 0 1745 }, 1746 { _SOC_PARITY_TYPE_ECC, NULL, 1747 RXFIFO1_DBEf, RXFIFO1_DBEf, 1748 INVALIDm, NULL, 1749 PGW_GE_ECC_CONTROLr, RXFIFO_ECC_ENABLEf, NULL, 1750 INVALIDr, INVALIDf, NULL, 1751 PGW_GE_RXFIFO1_ECC_DBE_STATUSr, NULL, ECC_ERRf, 1752 INVALIDr, INVALIDf, 1753 INVALIDr, INVALIDr, INVALIDr, 1754 0 1755 }, 1756 { _SOC_PARITY_TYPE_ECC, NULL, 1757 RXFIFO2_DBEf, RXFIFO2_DBEf, 1758 INVALIDm, NULL, 1759 PGW_GE_ECC_CONTROLr, RXFIFO_ECC_ENABLEf, NULL, 1760 INVALIDr, INVALIDf, NULL, 1761 PGW_GE_RXFIFO2_ECC_DBE_STATUSr, NULL, ECC_ERRf, 1762 INVALIDr, INVALIDf, 1763 INVALIDr, INVALIDr, INVALIDr, 1764 0 1765 }, 1766 { _SOC_PARITY_TYPE_ECC, NULL, 1767 RXFIFO3_DBEf, RXFIFO3_DBEf, 1768 INVALIDm, NULL, 1769 PGW_GE_ECC_CONTROLr, RXFIFO_ECC_ENABLEf, NULL, 1770 INVALIDr, INVALIDf, NULL, 1771 PGW_GE_RXFIFO3_ECC_DBE_STATUSr, NULL, ECC_ERRf, 1772 INVALIDr, INVALIDf, 1773 INVALIDr, INVALIDr, INVALIDr, 1774 0 1775 }, 1776 { _SOC_PARITY_TYPE_NONE }, /* table terminator */ 1777 }; 1778 1779 /* from FORMAT CMIC_PARITY_INTR_STATUS */ 1780 #define _HR3_PAR_MMU (0) 1781 #define _HR3_PAR_EP (1) 1782 #define _HR3_PAR_IP0 (2) 1783 #define _HR3_PAR_IP1 (3) 1784 #define _HR3_PAR_IP2 (4) 1785 #define _WH2_PAR_GXP2 (6) 1786 #define _HR3_PAR_XLP0 (6) 1787 #define _HR3_PAR_XLP1 (7) 1788 #define _HR3_PAR_GXP0 (8) 1789 #define _HR3_PAR_GXP1 (9) 1790 1791 #define _HR3_X_TO_CMIC_INTR(bit) (1<<(bit) ) /* Bit 0-31 */ 1792 1793 typedef struct _soc_hr3_ser_route_block_s { 1794 uint32 cmic_bit; 1795 soc_block_t blocktype; 1796 uint8 id; 1797 soc_reg_t enable_reg; 1798 soc_reg_t status_reg; 1799 void *info; 1800 } _soc_hr3_ser_route_block_t; 1801 1802 STATIC const _soc_hr3_ser_route_block_t 1803 *_soc_hr3_ser_route_blocks[SOC_MAX_NUM_DEVICES] = {NULL}; 1804 1805 STATIC const _soc_hr3_ser_route_block_t 1806 _soc_hr3_ser_route_blocks_template[] = { 1807 {_HR3_X_TO_CMIC_INTR(_HR3_PAR_MMU), SOC_BLK_MMU, 0, 1808 INVALIDr, INVALIDr, 1809 _soc_hr3_mmu_top_ser_info}, 1810 {_HR3_X_TO_CMIC_INTR(_HR3_PAR_EP), SOC_BLK_EPIPE, 0, 1811 EGR_INTR_ENABLE_64r, EGR_INTR_STATUS_64r, 1812 _soc_hr3_ep_ser_info}, 1813 {_HR3_X_TO_CMIC_INTR(_HR3_PAR_IP0), SOC_BLK_IPIPE, 0, 1814 IP0_INTR_ENABLEr, IP0_INTR_STATUSr, 1815 _soc_hr3_ip0_ser_info}, 1816 {_HR3_X_TO_CMIC_INTR(_HR3_PAR_IP1), SOC_BLK_IPIPE, 0, 1817 IP1_INTR_ENABLEr, IP1_INTR_STATUSr, 1818 _soc_hr3_ip1_ser_info}, 1819 {_HR3_X_TO_CMIC_INTR(_HR3_PAR_IP2), SOC_BLK_IPIPE, 0, 1820 IP2_INTR_ENABLEr, IP2_INTR_STATUSr, 1821 _soc_hr3_ip2_ser_info}, 1822 {_HR3_X_TO_CMIC_INTR(_HR3_PAR_XLP0), SOC_BLK_XLPORT, 0, 1823 PGW_XL_INTR_ENABLEr, PGW_XL_INTR_STATUSr, 1824 _soc_hr3_pgw_xlport_ser_info}, 1825 {_HR3_X_TO_CMIC_INTR(_HR3_PAR_XLP1), SOC_BLK_XLPORT, 1, 1826 PGW_XL_INTR_ENABLEr, PGW_XL_INTR_STATUSr, 1827 _soc_hr3_pgw_xlport_ser_info}, 1828 {_HR3_X_TO_CMIC_INTR(_HR3_PAR_GXP0), SOC_BLK_PGW_GE, 0, 1829 PGW_GE_INTR_ENABLEr, PGW_GE_INTR_STATUSr, 1830 _soc_hr3_pgw_gport_ser_info}, 1831 {_HR3_X_TO_CMIC_INTR(_HR3_PAR_GXP1), SOC_BLK_PGW_GE, 1, 1832 PGW_GE_INTR_ENABLEr, PGW_GE_INTR_STATUSr, 1833 _soc_hr3_pgw_gport_ser_info}, 1834 { 0 } /* table terminator */ 1835 }; 1836 1837 STATIC const _soc_hr3_ser_route_block_t 1838 _soc_wh2_ser_route_blocks_template[] = { 1839 {_HR3_X_TO_CMIC_INTR(_HR3_PAR_MMU), SOC_BLK_MMU, 0, 1840 INVALIDr, INVALIDr, 1841 _soc_hr3_mmu_top_ser_info}, 1842 {_HR3_X_TO_CMIC_INTR(_HR3_PAR_EP), SOC_BLK_EPIPE, 0, 1843 EGR_INTR_ENABLE_64r, EGR_INTR_STATUS_64r, 1844 _soc_hr3_ep_ser_info}, 1845 {_HR3_X_TO_CMIC_INTR(_HR3_PAR_IP0), SOC_BLK_IPIPE, 0, 1846 IP0_INTR_ENABLEr, IP0_INTR_STATUSr, 1847 _soc_hr3_ip0_ser_info}, 1848 {_HR3_X_TO_CMIC_INTR(_HR3_PAR_IP1), SOC_BLK_IPIPE, 0, 1849 IP1_INTR_ENABLEr, IP1_INTR_STATUSr, 1850 _soc_hr3_ip1_ser_info}, 1851 {_HR3_X_TO_CMIC_INTR(_HR3_PAR_IP2), SOC_BLK_IPIPE, 0, 1852 IP2_INTR_ENABLEr, IP2_INTR_STATUSr, 1853 _soc_hr3_ip2_ser_info}, 1854 {_HR3_X_TO_CMIC_INTR(_HR3_PAR_GXP0), SOC_BLK_PGW_GE, 0, 1855 PGW_GE_INTR_ENABLEr, PGW_GE_INTR_STATUSr, 1856 _soc_hr3_pgw_gport_ser_info}, 1857 {_HR3_X_TO_CMIC_INTR(_HR3_PAR_GXP1), SOC_BLK_PGW_GE, 1, 1858 PGW_GE_INTR_ENABLEr, PGW_GE_INTR_STATUSr, 1859 _soc_hr3_pgw_gport_ser_info}, 1860 {_HR3_X_TO_CMIC_INTR(_WH2_PAR_GXP2), SOC_BLK_PGW_GE, 2, 1861 PGW_GE_INTR_ENABLEr, PGW_GE_INTR_STATUSr, 1862 _soc_hr3_pgw_gport_ser_info}, 1863 { 0 } /* table terminator */ 1864 }; 1865 1866 static int 1867 soc_hr3_ser_route_blocks_init(int unit) 1868 { 1869 if (soc_feature(unit, soc_feature_wh2)) { 1870 /* Wolfhound2 */ 1871 _soc_hr3_ser_route_blocks[unit] = _soc_wh2_ser_route_blocks_template; 1872 } else { 1873 /* Hurricane3 */ 1874 _soc_hr3_ser_route_blocks[unit] = _soc_hr3_ser_route_blocks_template; 1875 } 1876 1877 return SOC_E_NONE; 1878 } 1879 1880 1881 STATIC int 1882 _soc_hr3_ser_process_is_per_port_mem( 1883 int unit, 1884 _soc_hr3_ser_info_type_t type) 1885 { 1886 if (type == _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP) { 1887 return TRUE; 1888 } 1889 return FALSE; 1890 } 1891 1892 /* Skip those MMU ports (memories) which logical ports don't exist */ 1893 STATIC int 1894 _soc_hr3_ser_process_skip_disabled_mmu_port( 1895 int unit, 1896 _soc_hr3_ser_info_t *info) 1897 { 1898 int logical_port = 0; 1899 _soc_hr3_ser_reg_t *reg_ptr; 1900 int ptr; 1901 1902 if (NULL == info) { 1903 return TRUE; 1904 } 1905 1906 if (info->type == _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP && 1907 info->intr_status_reg_list != NULL) { 1908 reg_ptr = info->intr_status_reg_list; 1909 } else { 1910 return FALSE; 1911 } 1912 1913 for (ptr = 0; reg_ptr[ptr].reg != INVALIDr; ptr++) { 1914 if (reg_ptr[ptr].mem == info->mem) { 1915 break; 1916 } 1917 logical_port++; 1918 } 1919 if (!SOC_PORT_VALID(unit, logical_port)) { 1920 return TRUE; 1921 } 1922 return FALSE; 1923 } 1924 1925 STATIC int 1926 _soc_hr3_ser_mem_skip(int unit, _soc_hr3_ser_info_t *info) 1927 { 1928 int sku; 1929 int skip = FALSE; 1930 1931 if (NULL == info) { 1932 return TRUE; 1933 } 1934 if (soc_feature(unit, soc_feature_wh2)) { 1935 if (info->sku_skip & _SOC_SER_SKIP_WH2) { 1936 skip = TRUE; 1937 } 1938 } else { 1939 (void)soc_hurricane3_chip_sku_get(unit, &sku); 1940 1941 switch (sku){ 1942 case (SOC_HR3_SKU_HURRICANE3LITE): 1943 if (info->sku_skip & _SOC_SER_SKIP_HR3L) { 1944 skip = TRUE; 1945 } 1946 break; 1947 case (SOC_HR3_SKU_BUCKHOUND): 1948 if (info->sku_skip & _SOC_SER_SKIP_BH) { 1949 skip = TRUE; 1950 } 1951 break; 1952 case (SOC_HR3_SKU_FOXHOUND2): 1953 if (info->sku_skip & _SOC_SER_SKIP_FH2) { 1954 skip = TRUE; 1955 } 1956 break; 1957 default: 1958 { 1959 skip = FALSE; 1960 break; 1961 } 1962 }; 1963 } 1964 /* skip invalid logical port */ 1965 if (_soc_hr3_ser_process_is_per_port_mem(unit, info->type)) { 1966 if (_soc_hr3_ser_process_skip_disabled_mmu_port(unit, info)) { 1967 skip = TRUE; 1968 } 1969 } 1970 return skip; 1971 } 1972 1973 STATIC int 1974 _soc_hr3_ser_2bit_ecc_mem(int unit, soc_mem_t memTable) 1975 { 1976 int is_2bit_ecc_mem = FALSE; 1977 /* FOR _SOC_PARITY_TYPE_ECC_DUAL */ 1978 switch (memTable){ 1979 case MMU_IPMC_GROUP_TBL2m: 1980 case MMU_IPMC_GROUP_TBL3m: 1981 case MMU_IPMC_GROUP_TBL4m: 1982 case MMU_IPMC_GROUP_TBL5m: 1983 case MMU_IPMC_GROUP_TBL6m: 1984 case MMU_IPMC_GROUP_TBL7m: 1985 case MMU_IPMC_GROUP_TBL8m: 1986 case MMU_IPMC_GROUP_TBL9m: 1987 case MMU_IPMC_GROUP_TBL10m: 1988 case MMU_IPMC_GROUP_TBL11m: 1989 case MMU_IPMC_GROUP_TBL12m: 1990 case MMU_IPMC_GROUP_TBL13m: 1991 case MMU_IPMC_GROUP_TBL14m: 1992 case MMU_IPMC_GROUP_TBL15m: 1993 case MMU_IPMC_GROUP_TBL16m: 1994 case MMU_IPMC_GROUP_TBL17m: 1995 case MMU_IPMC_GROUP_TBL18m: 1996 case MMU_IPMC_GROUP_TBL19m: 1997 case MMU_IPMC_GROUP_TBL20m: 1998 case MMU_IPMC_GROUP_TBL21m: 1999 case MMU_IPMC_GROUP_TBL22m: 2000 case MMU_IPMC_GROUP_TBL23m: 2001 case MMU_IPMC_GROUP_TBL24m: 2002 case MMU_IPMC_GROUP_TBL25m: 2003 case MMU_IPMC_GROUP_TBL26m: 2004 case MMU_IPMC_GROUP_TBL27m: 2005 case MMU_IPMC_GROUP_TBL28m: 2006 case MMU_IPMC_GROUP_TBL29m: 2007 case MMU_IPMC_GROUP_TBL30m: 2008 case MMU_IPMC_GROUP_TBL31m: 2009 case MMU_IPMC_VLAN_TBLm: 2010 is_2bit_ecc_mem = TRUE; 2011 break; 2012 default: 2013 is_2bit_ecc_mem = FALSE; 2014 break; 2015 }; 2016 return is_2bit_ecc_mem; 2017 } 2018 2019 STATIC void 2020 _soc_hr3_mem_parity_info(int unit, int block_info_idx, int pipe, 2021 soc_field_t field_enum, uint32 *minfo) 2022 { 2023 *minfo = (SOC_BLOCK2SCH(unit, block_info_idx) << SOC_ERROR_BLK_BP) 2024 | ((pipe & 0xff) << SOC_ERROR_PIPE_BP) 2025 | (field_enum & SOC_ERROR_FIELD_ENUM_MASK); 2026 } 2027 2028 #define _SOC_HR3_MMU_E2EFC_MAX 4 2029 static soc_reg_t e2efc_regs[_SOC_HR3_MMU_E2EFC_MAX] = { 2030 INVALIDr, 2031 E2EFC_CNT_SET_LIMITr, 2032 E2EFC_CNT_RESET_LIMITr, 2033 E2EFC_CNT_DISC_LIMITr 2034 }; 2035 2036 STATIC int 2037 _soc_hr3_ser_process_mmu_e2efc(int unit,_soc_hr3_ser_info_t *info_list, 2038 int info_index, int block_info_idx, char *msg) 2039 { 2040 _soc_hr3_ser_info_t *info; 2041 soc_reg_t status_reg; 2042 uint32 intr_status; 2043 int index, mem_id; 2044 uint32 minfo; 2045 _soc_ser_correct_info_t spci; 2046 2047 info = &info_list[info_index]; 2048 status_reg = info->intr_status_reg; 2049 SOC_IF_ERROR_RETURN 2050 (soc_reg32_get(unit, status_reg, REG_PORT_ANY, 0, 2051 &intr_status)); 2052 mem_id = soc_reg_field_get(unit, status_reg, 2053 intr_status, MEM_IDf); 2054 /* CHECK if the error is valid */ 2055 if (mem_id == 0) { 2056 LOG_ERROR(BSL_LS_SOC_COMMON, 2057 (BSL_META_U(unit, 2058 "%s: parity hardware inconsistency\n"), 2059 msg)); 2060 return SOC_E_NONE; 2061 } 2062 index = soc_reg_field_get(unit, status_reg, intr_status, ENTRY_INDEXf); 2063 _soc_hr3_mem_parity_info(unit, block_info_idx, 0, 2064 info->group_reg_status_field, &minfo); 2065 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 2066 SOC_SWITCH_EVENT_DATA_ERROR_PARITY, 2067 index, minfo); 2068 LOG_ERROR(BSL_LS_SOC_COMMON, 2069 (BSL_META_U(unit, 2070 "unit %d MMU E2EFC entry %d parity error\n"), 2071 unit, index)); 2072 sal_memset(&spci, 0, sizeof(_soc_ser_correct_info_t)); 2073 spci.flags = SOC_SER_SRC_REG | SOC_SER_REG_MEM_KNOWN; 2074 spci.reg = e2efc_regs[mem_id]; 2075 spci.mem = INVALIDm; 2076 spci.blk_type = SOC_BLK_MMU; 2077 spci.index = index; 2078 spci.detect_time = sal_time_usecs(); 2079 (void)soc_ser_correction(unit, &spci); 2080 2081 return SOC_E_NONE; 2082 } 2083 2084 STATIC int 2085 _soc_hr3_ser_process_mmu_group_correct(int unit,_soc_hr3_ser_info_t *info_list, 2086 int info_index, int block_info_idx, 2087 char *msg, int report_type) 2088 { 2089 _soc_hr3_ser_info_t *info; 2090 _soc_hr3_ser_reg_t *reg_ptr; 2091 soc_reg_t valid_reg, status_reg, clear_reg; 2092 soc_reg_t multi_err_reg = INVALIDr; 2093 uint32 reg_val, valid_val; 2094 int index, double_bit = 0, multiple = 0; 2095 uint32 minfo; 2096 int ptr; 2097 _soc_ser_correct_info_t spci; 2098 int port; 2099 2100 info = &info_list[info_index]; 2101 2102 valid_reg = info->intr2_valid_reg; 2103 SOC_IF_ERROR_RETURN 2104 (soc_reg32_get(unit, valid_reg, REG_PORT_ANY, 0, 2105 ®_val)); 2106 valid_val = soc_reg_field_get(unit, valid_reg, reg_val, ERR_VALIDf); 2107 2108 if (valid_val == 0) { 2109 LOG_ERROR(BSL_LS_SOC_COMMON, 2110 (BSL_META_U(unit, 2111 "%s: ecc hardware inconsistency\n"), 2112 msg)); 2113 return SOC_E_NONE; 2114 } 2115 2116 if (SOC_REG_IS_VALID(unit, info->intr2_multi_err_reg) && 2117 soc_reg_field_valid(unit, info->intr2_multi_err_reg, MULTIPLE_ERRf)) { 2118 multi_err_reg = info->intr2_multi_err_reg; 2119 } else if (soc_reg_field_valid(unit, valid_reg, MULTIPLE_ERRf)) { 2120 multi_err_reg = valid_reg; 2121 } 2122 if (INVALIDr != multi_err_reg) { 2123 multiple = 2124 soc_reg_field_get(unit, multi_err_reg, reg_val, MULTIPLE_ERRf); 2125 } 2126 2127 if (info->intr_status_reg_list != NULL) { 2128 reg_ptr = info->intr_status_reg_list; 2129 } else { 2130 return SOC_E_INTERNAL; 2131 } 2132 2133 for (ptr = 0; reg_ptr[ptr].reg != INVALIDr; ptr++) { 2134 if (ptr > 31) { 2135 LOG_ERROR(BSL_LS_SOC_COMMON, 2136 (BSL_META_U(unit, 2137 "%s: left shifting by more" 2138 " than 31 bits, ptr = %d"), 2139 msg, ptr)); 2140 return SOC_E_INTERNAL; 2141 } 2142 if (!(valid_val & (0x1 << ptr))) { 2143 continue; 2144 } 2145 status_reg = reg_ptr[ptr].reg; 2146 2147 /* get logical port for per port memories */ 2148 if (_soc_hr3_ser_process_is_per_port_mem(unit, info->type)) { 2149 if (SOC_PORT_VALID(unit, ptr)) { 2150 port = ptr; 2151 } else { 2152 return SOC_E_INTERNAL; 2153 } 2154 } else { 2155 port = REG_PORT_ANY; 2156 } 2157 2158 SOC_IF_ERROR_RETURN( 2159 soc_reg32_get(unit, status_reg, port, 0, ®_val)); 2160 index = 2161 soc_reg_field_get(unit, status_reg, reg_val, ENTRY_INDEXf); 2162 2163 sal_memset(&spci, 0, sizeof(_soc_ser_correct_info_t)); 2164 spci.flags |= SOC_SER_SRC_MEM; 2165 if (soc_reg_field_valid(unit, status_reg, DOUBLE_BIT_ERRf)) { 2166 double_bit = 2167 soc_reg_field_get(unit, status_reg, reg_val, DOUBLE_BIT_ERRf); 2168 spci.double_bit = 1; 2169 } 2170 _soc_hr3_mem_parity_info(unit, block_info_idx, 0, 2171 info->group_reg_status_field, &minfo); 2172 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 2173 report_type, 2174 index, minfo); 2175 2176 LOG_ERROR(BSL_LS_SOC_COMMON, 2177 (BSL_META_U(unit, 2178 "%s %s entry %d %s parity error\n"), 2179 msg, reg_ptr[ptr].str, index, 2180 double_bit ? "double-bit" : "")); 2181 2182 if (multiple & (1 << ptr)) { 2183 LOG_ERROR(BSL_LS_SOC_COMMON, 2184 (BSL_META_U(unit, 2185 "%s %s has multiple parity errors\n"), 2186 msg, reg_ptr[ptr].str)); 2187 spci.flags |= SOC_SER_ERR_MULTI; 2188 } 2189 spci.reg = INVALIDr; 2190 spci.mem = reg_ptr[ptr].mem; 2191 spci.flags |= SOC_SER_REG_MEM_KNOWN; 2192 spci.blk_type = SOC_BLK_MMU; 2193 spci.detect_time = sal_time_usecs(); 2194 spci.index = index; 2195 (void)soc_ser_correction(unit, &spci); 2196 2197 } 2198 /* Clear interrupt status */ 2199 clear_reg = info->intr2_clr_reg; 2200 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, clear_reg, 2201 REG_PORT_ANY, 0, ®_val)); 2202 soc_reg_field_set(unit, clear_reg, ®_val, 2203 CLR_ERRf, valid_val); 2204 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, clear_reg, 2205 REG_PORT_ANY, 0, reg_val)); 2206 return SOC_E_NONE; 2207 } 2208 2209 STATIC int 2210 _soc_hr3_ser_process_mmu_group_ecc(int unit,_soc_hr3_ser_info_t *info_list, 2211 int info_index, int block_info_idx, char *msg) 2212 { 2213 _soc_hr3_ser_info_t *info; 2214 _soc_hr3_ser_reg_t *reg_ptr; 2215 soc_reg_t valid_reg, status_reg, clear_reg; 2216 uint32 reg_val, valid_val; 2217 int index, double_bit = 0, multiple; 2218 uint32 minfo; 2219 int ptr; 2220 2221 info = &info_list[info_index]; 2222 valid_reg = info->intr2_valid_reg; 2223 SOC_IF_ERROR_RETURN 2224 (soc_reg32_get(unit, valid_reg, REG_PORT_ANY, 0, 2225 ®_val)); 2226 valid_val = soc_reg_field_get(unit, valid_reg, reg_val, ERR_VALIDf); 2227 /* CBPPKTHDR_ERR */ 2228 multiple = 2229 soc_reg_field_get(unit, valid_reg, reg_val, MULTIPLE_ERRf); 2230 if (valid_val == 0) { 2231 LOG_ERROR(BSL_LS_SOC_COMMON, 2232 (BSL_META_U(unit, 2233 "%s: ecc hardware inconsistency\n"), 2234 msg)); 2235 return SOC_E_NONE; 2236 } 2237 2238 if (info->intr_status_reg_list != NULL) { 2239 reg_ptr = info->intr_status_reg_list; 2240 } else { 2241 return SOC_E_INTERNAL; 2242 } 2243 for (ptr = 0; reg_ptr[ptr].reg != INVALIDr; ptr++) { 2244 if (!(valid_val & (0x1 << ptr))) { 2245 continue; 2246 } 2247 status_reg = reg_ptr[ptr].reg; 2248 2249 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, status_reg, 2250 REG_PORT_ANY, 0, ®_val)); 2251 index = 2252 soc_reg_field_get(unit, status_reg, reg_val, ENTRY_INDEXf); 2253 if (soc_reg_field_valid(unit, status_reg, DOUBLE_BIT_ERRf)) { 2254 double_bit = 2255 soc_reg_field_get(unit, status_reg, reg_val, DOUBLE_BIT_ERRf); 2256 } 2257 _soc_hr3_mem_parity_info(unit, block_info_idx, 0, 2258 info->group_reg_status_field, &minfo); 2259 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 2260 SOC_SWITCH_EVENT_DATA_ERROR_ECC, 2261 index, minfo); 2262 2263 LOG_ERROR(BSL_LS_SOC_COMMON, 2264 (BSL_META_U(unit, 2265 "%s %s entry %d %s ECC error\n"), 2266 msg, reg_ptr[ptr].str, index, 2267 double_bit ? "double-bit" : "")); 2268 if (multiple & (1 << ptr)) { 2269 LOG_ERROR(BSL_LS_SOC_COMMON, 2270 (BSL_META_U(unit, 2271 "%s (%s) has multiple ECC errors\n"), 2272 msg, reg_ptr[ptr].str)); 2273 } 2274 } 2275 /* Clear interrupt status */ 2276 clear_reg = info->intr2_clr_reg; 2277 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, clear_reg, 2278 REG_PORT_ANY, 0, ®_val)); 2279 soc_reg_field_set(unit, clear_reg, ®_val, 2280 CLR_ERRf, valid_val); 2281 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, clear_reg, 2282 REG_PORT_ANY, 0, reg_val)); 2283 return SOC_E_NONE; 2284 } 2285 2286 STATIC int 2287 _soc_hr3_ser_process_mmu_ecc2(int unit,_soc_hr3_ser_info_t *info_list, 2288 int info_index, int block_info_idx, char *msg) 2289 2290 { 2291 _soc_hr3_ser_info_t *info; 2292 soc_reg_t valid_reg, status_reg, clear_reg, merr_reg; 2293 uint32 reg_val, valid_val; 2294 int index, double_bit = 0, multiple = 0; 2295 uint32 minfo; 2296 int port; 2297 2298 info = &info_list[info_index]; 2299 2300 valid_reg = info->intr2_valid_reg; 2301 SOC_IF_ERROR_RETURN 2302 (soc_reg32_get(unit, valid_reg, REG_PORT_ANY, 0, 2303 ®_val)); 2304 valid_val = soc_reg_field_get(unit, valid_reg, reg_val, ERR_VALIDf); 2305 if (valid_val == 0) { 2306 LOG_ERROR(BSL_LS_SOC_COMMON, 2307 (BSL_META_U(unit, 2308 "%s: ecc hardware inconsistency\n"), 2309 msg)); 2310 return SOC_E_NONE; 2311 } 2312 port = 0; 2313 while (!(valid_val & (0x1 << port))) { 2314 port++; 2315 } 2316 if (info->intr_status_reg != INVALIDr){ 2317 status_reg = info->intr_status_reg; 2318 } else { 2319 return SOC_E_INTERNAL; 2320 } 2321 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, status_reg, 2322 port, 0, ®_val)); 2323 index = 2324 soc_reg_field_get(unit, status_reg, reg_val, ENTRY_INDEXf); 2325 if (soc_reg_field_valid(unit, status_reg, DOUBLE_BIT_ERRf)) { 2326 double_bit = 2327 soc_reg_field_get(unit, status_reg, reg_val, DOUBLE_BIT_ERRf); 2328 } 2329 if (info->intr2_multi_err_reg != INVALIDr) { 2330 merr_reg = info->intr2_multi_err_reg; 2331 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, merr_reg, 2332 port, 0, ®_val)); 2333 multiple = 2334 soc_reg_field_get(unit, merr_reg, reg_val, MULTIPLE_ERRf); 2335 } 2336 _soc_hr3_mem_parity_info(unit, block_info_idx, 0, 2337 info->group_reg_status_field, &minfo); 2338 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 2339 SOC_SWITCH_EVENT_DATA_ERROR_ECC, 2340 index, minfo); 2341 LOG_ERROR(BSL_LS_SOC_COMMON, 2342 (BSL_META_U(unit, 2343 "%s port %d entry %d %s ECC error\n"), 2344 msg, port, index, double_bit ? "double-bit" : "")); 2345 if (multiple) { 2346 LOG_ERROR(BSL_LS_SOC_COMMON, 2347 (BSL_META_U(unit, 2348 "%s has multiple ECC errors\n"), 2349 msg)); 2350 } 2351 /* Clear interrupt status */ 2352 clear_reg = info->intr2_clr_reg; 2353 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, clear_reg, 2354 REG_PORT_ANY, 0, ®_val)); 2355 soc_reg_field_set(unit, clear_reg, ®_val, 2356 CLR_ERRf, valid_val); 2357 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, clear_reg, 2358 REG_PORT_ANY, 0, reg_val)); 2359 return SOC_E_NONE; 2360 } 2361 2362 STATIC int 2363 _soc_hr3_ser_process_mmu_ecc(int unit,_soc_hr3_ser_info_t *info_list, 2364 int info_index, int block_info_idx, char *msg, 2365 int correctable) 2366 { 2367 _soc_hr3_ser_info_t *info; 2368 soc_reg_t status_reg; 2369 uint32 intr_status; 2370 int index, double_bit = 0; 2371 uint32 minfo; 2372 _soc_ser_correct_info_t spci; 2373 2374 info = &info_list[info_index]; 2375 status_reg = info->intr_status_reg; 2376 SOC_IF_ERROR_RETURN 2377 (soc_reg32_get(unit, status_reg, REG_PORT_ANY, 0, 2378 &intr_status)); 2379 index = soc_reg_field_get(unit, status_reg, intr_status, ENTRY_INDEXf); 2380 if (soc_reg_field_valid(unit, status_reg, DOUBLE_BIT_ERRf)) { 2381 double_bit = soc_reg_field_get(unit, status_reg, 2382 intr_status, DOUBLE_BIT_ERRf); 2383 } 2384 _soc_hr3_mem_parity_info(unit, block_info_idx, 0, 2385 info->group_reg_status_field, &minfo); 2386 2387 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 2388 SOC_SWITCH_EVENT_DATA_ERROR_ECC, 2389 index, minfo); 2390 LOG_ERROR(BSL_LS_SOC_COMMON, 2391 (BSL_META_U(unit, 2392 "%s entry %d %s ECC error\n"), 2393 msg, index, double_bit ? "double-bit" : "")); 2394 if (correctable) { 2395 sal_memset(&spci, 0, sizeof(_soc_ser_correct_info_t)); 2396 spci.flags = SOC_SER_SRC_MEM | SOC_SER_REG_MEM_KNOWN; 2397 spci.reg = INVALIDr; 2398 spci.mem = info->mem; 2399 spci.blk_type = SOC_BLK_MMU; 2400 spci.index = index; 2401 (void)soc_ser_correction(unit, &spci); 2402 } 2403 return SOC_E_NONE; 2404 } 2405 2406 STATIC int 2407 _soc_hr3_ser_process_mmu_err(int unit, int block_info_idx, 2408 soc_reg_t group_reg, 2409 soc_reg_t clear_reg, 2410 _soc_hr3_ser_info_t *info_list) 2411 { 2412 soc_reg_t grp_reg, clr_reg; 2413 uint32 rval, group_rval; 2414 int rv = SOC_E_NONE; 2415 int info_index; 2416 _soc_hr3_ser_info_t *info; 2417 char *mem_str; 2418 2419 if (info_list->type == _SOC_PARITY_TYPE_MMU_SER){ 2420 grp_reg = info_list->intr_status_reg; 2421 clr_reg = info_list->intr_clr_reg; 2422 2423 2424 rv = _soc_hr3_ser_process_mmu_err(unit, block_info_idx, 2425 grp_reg, 2426 clr_reg, 2427 info_list->info); 2428 if (SOC_FAILURE(rv)) { 2429 LOG_CLI((BSL_META_U(unit, 2430 "process_mmu_err: Error processing %s !!\n"), 2431 info_list->mem_str)); 2432 return rv; 2433 } 2434 return rv; 2435 } 2436 for (info_index = 0; ; info_index++) { 2437 info = &info_list[info_index]; 2438 if (info->type == _SOC_PARITY_TYPE_NONE) { 2439 /* End of table */ 2440 break; 2441 } 2442 SOC_IF_ERROR_RETURN 2443 (soc_reg32_get(unit, group_reg, REG_PORT_ANY, 0, 2444 &group_rval)); 2445 if (!soc_reg_field_get(unit, group_reg, group_rval, 2446 info->group_reg_status_field)) { 2447 continue; 2448 } 2449 2450 if (info->mem_str) { 2451 mem_str = info->mem_str; 2452 } else if (info->mem != INVALIDm) { 2453 mem_str = SOC_MEM_NAME(unit, info->mem); 2454 } else { 2455 mem_str = SOC_FIELD_NAME(unit, info->group_reg_status_field); 2456 } 2457 LOG_VERBOSE(BSL_LS_SOC_COMMON, 2458 (BSL_META_U(unit, 2459 "process_mmu_err %s analysis\n"), 2460 mem_str)); 2461 switch (info->type) { 2462 case _SOC_PARITY_TYPE_MMU_ECC: 2463 SOC_IF_ERROR_RETURN( 2464 _soc_hr3_ser_process_mmu_ecc(unit, info_list, info_index, 2465 block_info_idx, mem_str, 0)); 2466 break; 2467 case _SOC_PARITY_TYPE_MMU_ECC_XQ: 2468 SOC_IF_ERROR_RETURN( 2469 _soc_hr3_ser_process_mmu_ecc2(unit, info_list, info_index, 2470 block_info_idx, mem_str)); 2471 break; 2472 case _SOC_PARITY_TYPE_MMU_ECC_CBPH: 2473 SOC_IF_ERROR_RETURN( 2474 _soc_hr3_ser_process_mmu_group_ecc(unit, info_list, info_index, 2475 block_info_idx, mem_str)); 2476 break; 2477 case _SOC_PARITY_TYPE_MMU_PAR_E2EFC: 2478 SOC_IF_ERROR_RETURN( 2479 _soc_hr3_ser_process_mmu_e2efc(unit, info_list, info_index, 2480 block_info_idx, mem_str)); 2481 break; 2482 case _SOC_PARITY_TYPE_MMU_PAR_WRED: 2483 SOC_IF_ERROR_RETURN(_soc_hr3_ser_process_mmu_group_correct( 2484 unit, info_list, info_index, 2485 block_info_idx, mem_str, 2486 SOC_SWITCH_EVENT_DATA_ERROR_PARITY)); 2487 break; 2488 case _SOC_PARITY_TYPE_MMU_ECC_IPMCGROUP: 2489 SOC_IF_ERROR_RETURN(_soc_hr3_ser_process_mmu_group_correct( 2490 unit, info_list, info_index, 2491 block_info_idx, mem_str, 2492 SOC_SWITCH_EVENT_DATA_ERROR_ECC)); 2493 break; 2494 case _SOC_PARITY_TYPE_MMU_ECC_IPMCVLAN: 2495 SOC_IF_ERROR_RETURN( 2496 _soc_hr3_ser_process_mmu_ecc(unit, info_list, info_index, 2497 block_info_idx, mem_str, 1)); 2498 break; 2499 default: 2500 break; 2501 } 2502 /* clear interrupt */ 2503 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, clear_reg, REG_PORT_ANY, 2504 0, &rval)); 2505 soc_reg_field_set(unit, clear_reg, &rval, 2506 info->intr_clr_field, 1); 2507 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, clear_reg, REG_PORT_ANY, 2508 0, rval)); 2509 2510 } 2511 return SOC_E_NONE; 2512 } 2513 2514 STATIC int 2515 _soc_hr3_ser_process_parity_hash(int unit, int block_info_idx, int port, 2516 _soc_hr3_ser_info_t *info, 2517 char *mem_str, 2518 soc_block_t blocktype) 2519 { 2520 _soc_hr3_ser_reg_t reg_entry[2], *reg_ptr; 2521 soc_reg_t reg; 2522 _soc_ser_correct_info_t spci; 2523 uint32 bitmap = 0, len = 0, bits, rval, minfo; 2524 uint32 multiple = 0, bucket_index = 0, entry_idx, idx, has_error; 2525 char *mem_str_ptr; 2526 2527 if (info->intr_status_reg != INVALIDr) { 2528 reg_entry[0].reg = info->intr_status_reg; 2529 reg_entry[0].str = NULL; 2530 reg_entry[1].reg = INVALIDr; 2531 reg_ptr = reg_entry; 2532 } else if (info->intr_status_reg_list != NULL) { 2533 reg_ptr = info->intr_status_reg_list; 2534 } else { 2535 return SOC_E_NONE; 2536 } 2537 2538 has_error = FALSE; 2539 for (idx = 0; reg_ptr[idx].reg != INVALIDr; idx++) { 2540 reg = reg_ptr[idx].reg; 2541 mem_str_ptr = (reg_ptr[idx].str != NULL) ? 2542 reg_ptr[idx].str : mem_str; 2543 sal_memset(&spci, 0, sizeof(spci)); 2544 2545 SOC_IF_ERROR_RETURN 2546 (soc_reg32_get(unit, reg, port, 0, &rval)); 2547 2548 if (soc_reg_field_valid(unit, reg, BUCKET_IDXf)) { 2549 bucket_index = 2550 soc_reg_field_get(unit, reg, rval, BUCKET_IDXf); 2551 multiple = 2552 soc_reg_field_get(unit, reg, rval, MULTIPLE_ERRf); 2553 bitmap = 2554 soc_reg_field_get(unit, reg, rval, PARITY_ERR_BMf); 2555 len = soc_reg_field_length(unit, reg, PARITY_ERR_BMf); 2556 } else if (soc_reg_field_valid(unit, reg, BUCKET_IDX_0f)) { 2557 bucket_index = 2558 soc_reg_field_get(unit, reg, rval, BUCKET_IDX_0f); 2559 multiple = 2560 soc_reg_field_get(unit, reg, rval, MULTIPLE_ERR_0f); 2561 bitmap = 2562 soc_reg_field_get(unit, reg, rval, PARITY_ERR_BM_0f); 2563 len = soc_reg_field_length(unit, reg, PARITY_ERR_BM_0f); 2564 } else if (soc_reg_field_valid(unit, reg, BUCKET_IDX_1f)) { 2565 bucket_index = 2566 soc_reg_field_get(unit, reg, rval, BUCKET_IDX_1f); 2567 multiple = 2568 soc_reg_field_get(unit, reg, rval, MULTIPLE_ERR_1f); 2569 bitmap = 2570 soc_reg_field_get(unit, reg, rval, PARITY_ERR_BM_1f); 2571 len = soc_reg_field_length(unit, reg, PARITY_ERR_BM_1f); 2572 } 2573 if (bitmap != 0) { 2574 for (bits = 0; bits < len; bits++) { 2575 if (bitmap & (1 << bits)) { 2576 has_error = TRUE; 2577 break; 2578 } 2579 } 2580 entry_idx = bucket_index * len * 2 + bits + (idx * len); 2581 _soc_hr3_mem_parity_info(unit, block_info_idx, 0, 2582 info->group_reg_status_field, &minfo); 2583 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 2584 SOC_SWITCH_EVENT_DATA_ERROR_PARITY, 2585 entry_idx, minfo); 2586 LOG_ERROR(BSL_LS_SOC_COMMON, 2587 (BSL_META_U(unit, 2588 "unit %d %s entry %d parity error\n"), 2589 unit, mem_str_ptr, entry_idx)); 2590 if (multiple) { 2591 LOG_ERROR(BSL_LS_SOC_COMMON, 2592 (BSL_META_U(unit, 2593 "unit %d %s has multiple parity errors\n"), 2594 unit, mem_str_ptr)); 2595 } 2596 spci.flags = SOC_SER_SRC_MEM; 2597 if (multiple) { 2598 spci.flags |= SOC_SER_ERR_MULTI; 2599 } 2600 spci.double_bit = 0; 2601 spci.reg = INVALIDr; 2602 spci.mem = info->mem; 2603 spci.blk_type = blocktype; 2604 spci.index = entry_idx; 2605 spci.detect_time = sal_time_usecs(); 2606 spci.pipe_num = 0; 2607 spci.acc_type = -1; 2608 spci.addr = (spci.mem != INVALIDm)? SOC_MEM_BASE(unit, spci.mem) : 0; 2609 if (spci.mem != INVALIDm) { 2610 spci.flags |= SOC_SER_REG_MEM_KNOWN; 2611 (void)soc_ser_correction(unit, &spci); 2612 } 2613 /* Clear parity status */ 2614 SOC_IF_ERROR_RETURN 2615 (soc_reg32_set(unit, reg, port, 0, 0)); 2616 } 2617 } 2618 if (!has_error) { 2619 LOG_VERBOSE(BSL_LS_SOC_SER, 2620 (BSL_META_U(unit, 2621 "unit %d %s parity hardware inconsistency\n"), 2622 unit, mem_str)); 2623 } 2624 2625 return SOC_E_NONE; 2626 } 2627 2628 STATIC int 2629 _soc_hr3_ser_process_parity_ecc(int unit, int block_info_idx, int port, 2630 _soc_hr3_ser_info_t *info, 2631 char *mem_str, 2632 soc_block_t blocktype, int parity_type) 2633 { 2634 _soc_hr3_ser_reg_t reg_entry[2], *reg_ptr; 2635 soc_reg_t reg; 2636 soc_field_t parity_error_field = PARITY_ERRf; 2637 _soc_ser_correct_info_t spci; 2638 uint32 rval, minfo, double_bit = 0; 2639 uint32 multiple, entry_idx, idx, has_error; 2640 char *mem_str_ptr; 2641 int report_type = SOC_SWITCH_EVENT_DATA_ERROR_PARITY; 2642 2643 if (info->intr_status_reg != INVALIDr) { 2644 reg_entry[0].reg = info->intr_status_reg; 2645 reg_entry[0].str = NULL; 2646 reg_entry[1].reg = INVALIDr; 2647 reg_ptr = reg_entry; 2648 } else if (info->intr_status_reg_list != NULL) { 2649 reg_ptr = info->intr_status_reg_list; 2650 } else { 2651 return SOC_E_NONE; 2652 } 2653 if (INVALIDf != info->intr_status_field) { 2654 parity_error_field = info->intr_status_field; 2655 } 2656 2657 has_error = FALSE; 2658 for (idx = 0; reg_ptr[idx].reg != INVALIDr; idx++) { 2659 reg = reg_ptr[idx].reg; 2660 mem_str_ptr = (reg_ptr[idx].str != NULL) ? 2661 reg_ptr[idx].str : mem_str; 2662 sal_memset(&spci, 0, sizeof(spci)); 2663 if (!soc_reg_field_valid(unit, reg, parity_error_field)) { 2664 continue; 2665 } 2666 SOC_IF_ERROR_RETURN 2667 (soc_reg32_get(unit, reg, port, 0, &rval)); 2668 if (soc_reg_field_get(unit, reg, rval, parity_error_field)) { 2669 has_error = TRUE; 2670 multiple = soc_reg_field_get(unit, reg, rval, MULTIPLE_ERRf); 2671 entry_idx = soc_reg_field_get(unit, reg, rval, ENTRY_IDXf); 2672 2673 if (soc_feature(unit, soc_feature_hr3_lite_lpm_shadow_hit) && 2674 NEED_HR3LITE_LPM_SHADOW(info->mem)){ 2675 if (entry_idx >= 512) { 2676 entry_idx = entry_idx - 512 + 32; 2677 } 2678 } 2679 _soc_hr3_mem_parity_info(unit, block_info_idx, 0, 2680 info->group_reg_status_field, &minfo); 2681 if (parity_type == _SOC_PARITY_TYPE_ECC) { 2682 report_type = SOC_SWITCH_EVENT_DATA_ERROR_ECC; 2683 if (soc_reg_field_valid(unit, reg, DOUBLE_BIT_ERRf)) { 2684 double_bit = 2685 soc_reg_field_get(unit, reg, rval, DOUBLE_BIT_ERRf); 2686 } 2687 } 2688 2689 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 2690 report_type, 2691 entry_idx, minfo); 2692 LOG_ERROR(BSL_LS_SOC_COMMON, 2693 (BSL_META_U(unit, 2694 "unit %d %s entry %d %s error\n"), 2695 unit, mem_str_ptr, entry_idx, 2696 ((parity_type == _SOC_PARITY_TYPE_ECC)? 2697 "ecc" : "parity"))); 2698 if (multiple) { 2699 LOG_ERROR(BSL_LS_SOC_COMMON, 2700 (BSL_META_U(unit, 2701 "unit %d %s has multiple %s errors\n"), 2702 unit, mem_str_ptr, 2703 ((parity_type == _SOC_PARITY_TYPE_ECC)? 2704 "ecc" : "parity"))); 2705 } 2706 spci.flags = SOC_SER_SRC_MEM; 2707 if (multiple) { 2708 spci.flags |= SOC_SER_ERR_MULTI; 2709 } 2710 if (double_bit) { 2711 spci.double_bit = 1; 2712 } 2713 spci.reg = INVALIDr; 2714 spci.mem = info->mem; 2715 spci.blk_type = blocktype; 2716 spci.index = entry_idx; 2717 spci.detect_time = sal_time_usecs(); 2718 spci.pipe_num = 0; 2719 spci.acc_type = -1; 2720 spci.addr = (spci.mem != INVALIDm)? SOC_MEM_BASE(unit, spci.mem) : 0; 2721 if (spci.mem != INVALIDm) { 2722 spci.flags |= SOC_SER_REG_MEM_KNOWN; 2723 (void)soc_ser_correction(unit, &spci); 2724 } 2725 /* Clear parity status */ 2726 SOC_IF_ERROR_RETURN 2727 (soc_reg32_set(unit, reg, port, 0, 0)); 2728 } 2729 } 2730 if (!has_error) { 2731 LOG_VERBOSE(BSL_LS_SOC_SER, 2732 (BSL_META_U(unit, 2733 "unit %d %s parity hardware inconsistency\n"), 2734 unit, mem_str)); 2735 } 2736 2737 return SOC_E_NONE; 2738 2739 } 2740 2741 #define _SOC_HR3_DBG_COUNTER_MAX 12 2742 static soc_reg_t dbgc_regs[_SOC_HR3_DBG_COUNTER_MAX] = { 2743 TDBGC0r, TDBGC1r, TDBGC2r, TDBGC3r, 2744 TDBGC4r, TDBGC5r, TDBGC6r, TDBGC7r, 2745 TDBGC8r, TDBGC9r, TDBGC10r, TDBGC11r 2746 }; 2747 STATIC int 2748 _soc_hr3_ser_process_parity_counter(int unit, int block_info_idx, int port, 2749 _soc_hr3_ser_info_t *info, 2750 char *mem_str, 2751 soc_block_t blocktype) 2752 { 2753 soc_reg_t reg, counter_reg; 2754 uint32 rval, minfo; 2755 uint32 multiple, counter_idx, port_idx; 2756 char *counter_name; 2757 _soc_ser_correct_info_t spci; 2758 soc_field_t parity_error_field = PARITY_ERRf; 2759 2760 reg = info->intr_status_reg; 2761 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, reg, 2762 port, 0, &rval)); 2763 if (soc_reg_field_get(unit, reg, rval, parity_error_field)) { 2764 multiple = soc_reg_field_get(unit, reg, rval, MULTIPLE_ERRf); 2765 counter_idx = soc_reg_field_get(unit, reg, rval, COUNTER_IDXf); 2766 port_idx = soc_reg_field_get(unit, reg, rval, PORT_IDXf); 2767 2768 counter_reg = dbgc_regs[counter_idx]; 2769 _soc_hr3_mem_parity_info(unit, block_info_idx, 0, 2770 info->group_reg_status_field, &minfo); 2771 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 2772 SOC_SWITCH_EVENT_DATA_ERROR_PARITY, 2773 counter_idx, minfo); 2774 counter_name = SOC_REG_NAME(unit, counter_reg); 2775 LOG_ERROR(BSL_LS_SOC_COMMON, 2776 (BSL_META_U(unit, 2777 "EGR STAT COUNTER port %d %s parity error\n"), 2778 port_idx, counter_name)); 2779 2780 sal_memset(&spci, 0, sizeof(spci)); 2781 spci.flags = SOC_SER_SRC_REG | SOC_SER_REG_MEM_KNOWN; 2782 spci.mem = INVALIDm; 2783 spci.port = port_idx; 2784 spci.index = -1; 2785 spci.reg = counter_reg; 2786 spci.blk_type = blocktype; 2787 (void)soc_ser_correction(unit, &spci); 2788 if (multiple) { 2789 LOG_ERROR(BSL_LS_SOC_COMMON, 2790 (BSL_META_U(unit, 2791 "EGR STAT COUNTER has multiple parity errors\n"))); 2792 } 2793 }else { 2794 LOG_ERROR(BSL_LS_SOC_COMMON, 2795 (BSL_META_U(unit, 2796 "EGR STAT COUNTER parity hardware inconsistency\n"))); 2797 } 2798 /* Clear parity status */ 2799 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, reg, port, 0, 0)); 2800 2801 return SOC_E_NONE; 2802 } 2803 2804 STATIC int 2805 _soc_hr3_process_ser(int unit, soc_block_t block_info_idx, int inst, 2806 int port, soc_reg_t group_reg, uint64 group_rval, 2807 _soc_hr3_ser_info_t *info_list, 2808 soc_block_t blocktype) 2809 2810 { 2811 _soc_hr3_ser_info_t *info; 2812 int info_index; 2813 char *mem_str; 2814 2815 for (info_index = 0; ; info_index++) { 2816 info = &info_list[info_index]; 2817 if (info->type == _SOC_PARITY_TYPE_NONE) { 2818 /* End of table */ 2819 break; 2820 } 2821 if (_soc_hr3_ser_mem_skip(unit, info)) { 2822 continue; 2823 } 2824 if (group_reg != INVALIDr) { 2825 /* Check status for the info entry in the group register */ 2826 /* for SOC_BLK_MMU, group_reg is INVALIDr */ 2827 if (!soc_reg_field_valid(unit, group_reg, 2828 info->group_reg_status_field)) { 2829 continue; 2830 } 2831 if (!soc_reg64_field32_get(unit, group_reg, group_rval, 2832 info->group_reg_status_field)) { 2833 continue; 2834 } 2835 } 2836 if (info->mem_str) { 2837 mem_str = info->mem_str; 2838 } else if (info->mem != INVALIDm) { 2839 mem_str = SOC_MEM_NAME(unit, info->mem); 2840 } else { 2841 mem_str = SOC_FIELD_NAME(unit, info->group_reg_status_field); 2842 } 2843 LOG_VERBOSE(BSL_LS_SOC_COMMON, 2844 (BSL_META_U(unit, 2845 "unit %d _soc_hr3_process_ser %s analysis\n"), 2846 unit, mem_str)); 2847 2848 /* Handle different parity error reporting style */ 2849 switch (info->type) { 2850 case _SOC_PARITY_TYPE_MMU_SER: 2851 SOC_IF_ERROR_RETURN 2852 (_soc_hr3_ser_process_mmu_err(unit, block_info_idx, 2853 INVALIDr, INVALIDr, 2854 info)); 2855 /* info points to _soc_hr3_mmu_top_ser_info[0] */ 2856 break; 2857 case _SOC_PARITY_TYPE_PARITY: 2858 SOC_IF_ERROR_RETURN 2859 (_soc_hr3_ser_process_parity_ecc(unit, block_info_idx, port, 2860 info, mem_str, blocktype, 2861 info->type)); 2862 break; 2863 case _SOC_PARITY_TYPE_PARITY_DUAL: 2864 SOC_IF_ERROR_RETURN 2865 (_soc_hr3_ser_process_parity_hash(unit, block_info_idx, port, 2866 info, mem_str, blocktype)); 2867 break; 2868 case _SOC_PARITY_TYPE_ECC: 2869 SOC_IF_ERROR_RETURN 2870 (_soc_hr3_ser_process_parity_ecc(unit, block_info_idx, port, 2871 info, mem_str, blocktype, 2872 info->type)); 2873 break; 2874 case _SOC_PARITY_TYPE_COUNTER: 2875 SOC_IF_ERROR_RETURN 2876 (_soc_hr3_ser_process_parity_counter(unit, block_info_idx, port, 2877 info, mem_str, blocktype)); 2878 break; 2879 2880 default: 2881 break; 2882 } 2883 2884 } 2885 2886 return SOC_E_NONE; 2887 } 2888 2889 STATIC int 2890 _soc_hr3_ser_process_all(int unit, uint32 cmic_rval) 2891 { 2892 uint8 rbi; 2893 const _soc_hr3_ser_route_block_t *rb; 2894 uint32 cmic_bit; 2895 int port = REG_PORT_ANY; 2896 int block_info_idx; 2897 uint64 rb_rval64, rb_enable64, temp64; 2898 soc_reg_t tmp_reg; 2899 2900 COMPILER_64_ZERO(rb_rval64); 2901 COMPILER_64_ZERO(rb_enable64); 2902 2903 if (cmic_rval == 0) { 2904 return SOC_E_NONE; 2905 } 2906 /* Loop through each place-and-route block entry */ 2907 for (rbi = 0; ; rbi++) { 2908 rb = &_soc_hr3_ser_route_blocks[unit][rbi]; 2909 cmic_bit = rb->cmic_bit; 2910 if (cmic_bit == 0) { 2911 /* End of table */ 2912 break; 2913 } 2914 if (!(cmic_rval & cmic_bit)) { 2915 /* Indicated bit not asserted for the route block */ 2916 continue; 2917 } 2918 SOC_BLOCK_ITER(unit, block_info_idx, rb->blocktype) { 2919 if (SOC_BLOCK_INFO(unit, block_info_idx).number == rb->id) { 2920 port = SOC_BLOCK_PORT(unit, block_info_idx); 2921 break; 2922 } 2923 } 2924 if (rb->enable_reg != INVALIDr) { 2925 if (SOC_BLOCK_IN_LIST(SOC_REG_INFO(unit, rb->enable_reg).block, 2926 SOC_BLK_PORT) && (port == REG_PORT_ANY)) { 2927 /* This port block is not configured */ 2928 LOG_ERROR(BSL_LS_SOC_COMMON, 2929 (BSL_META_U(unit, 2930 "unit %d SER error on disabled " 2931 "port block %d !!\n"), 2932 unit, block_info_idx)); 2933 continue; 2934 } 2935 SOC_IF_ERROR_RETURN(soc_reg_get(unit, rb->enable_reg, 2936 port, 0, &rb_enable64)); 2937 } 2938 /* Read per route block parity status register */ 2939 if (rb->status_reg != INVALIDr) { 2940 tmp_reg = rb->status_reg; 2941 SOC_IF_ERROR_RETURN( 2942 soc_reg_get(unit, tmp_reg, port, 0, &rb_rval64)); 2943 if (COMPILER_64_IS_ZERO(rb_rval64)) { 2944 continue; 2945 } 2946 if (!COMPILER_64_IS_ZERO(rb_enable64)) { 2947 /* mask out the disabled status */ 2948 COMPILER_64_AND(rb_rval64, rb_enable64); 2949 if (COMPILER_64_IS_ZERO(rb_rval64)){ 2950 continue; 2951 } 2952 } 2953 } 2954 2955 /* ser process per type */ 2956 SOC_IF_ERROR_RETURN( 2957 _soc_hr3_process_ser(unit, block_info_idx, rb->id, 2958 port, rb->status_reg, rb_rval64, 2959 rb->info, rb->blocktype)); 2960 2961 /* Enable interrupt */ 2962 if (rb->enable_reg != INVALIDr) { 2963 SOC_IF_ERROR_RETURN(soc_reg_get(unit, rb->enable_reg, 2964 port, 0, &rb_enable64)); 2965 COMPILER_64_SET(temp64, COMPILER_64_HI(rb_rval64), 2966 COMPILER_64_LO(rb_rval64)); 2967 COMPILER_64_NOT(temp64); 2968 COMPILER_64_AND(rb_enable64, temp64); 2969 SOC_IF_ERROR_RETURN(soc_reg_set(unit, rb->enable_reg, 2970 port, 0, rb_enable64)); 2971 COMPILER_64_OR(rb_enable64, rb_rval64); 2972 SOC_IF_ERROR_RETURN(soc_reg_set(unit, rb->enable_reg, 2973 port, 0, rb_enable64)); 2974 } 2975 }/* for rbi */ 2976 return SOC_E_NONE; 2977 } 2978 /* parity enable for mmu block */ 2979 STATIC int 2980 _soc_hr3_mmu_ser_config(int unit, _soc_hr3_ser_info_t *info_list, 2981 soc_reg_t group_reg, soc_mem_t mem, 2982 int enable) 2983 { 2984 _soc_hr3_ser_info_t *info; 2985 int info_index, rv; 2986 uint32 rval; 2987 2988 rv = SOC_E_NOT_FOUND; 2989 SOC_IF_ERROR_RETURN 2990 (soc_reg32_get(unit, group_reg, REG_PORT_ANY, 0, 2991 &rval)); 2992 /* Loop through each info entry in the list */ 2993 for (info_index = 0; ; info_index++) { 2994 info = &info_list[info_index]; 2995 if (info->type == _SOC_PARITY_TYPE_NONE) { 2996 /* End of table */ 2997 break; 2998 } 2999 if ((mem != INVALIDm) && (mem != info->mem)) { 3000 continue; 3001 } 3002 rv = SOC_E_NONE; 3003 soc_reg_field_set(unit, group_reg, &rval, 3004 info->group_reg_enable_field, 3005 enable ? 1 : 0); 3006 3007 SOC_IF_ERROR_RETURN 3008 (soc_reg32_set(unit, group_reg, REG_PORT_ANY, 0, rval)); 3009 } 3010 return rv; 3011 } 3012 /* parity enable for xlport */ 3013 STATIC int 3014 _soc_hr3_pm_ser_config(int unit, _soc_hr3_ser_info_t *info_list, 3015 int block_info_idx, soc_reg_t group_reg, 3016 int enable) 3017 { 3018 _soc_hr3_ser_info_t *info; 3019 int info_index, port; 3020 uint32 rval, group_rval; 3021 soc_reg_t reg; 3022 3023 3024 port = SOC_BLOCK_PORT(unit, block_info_idx); 3025 SOC_IF_ERROR_RETURN 3026 (soc_reg32_get(unit, group_reg, REG_PORT_ANY, 0, 3027 &group_rval)); 3028 /* Loop through each info entry in the list */ 3029 for (info_index = 0; ; info_index++) { 3030 info = &info_list[info_index]; 3031 if (info->type == _SOC_PARITY_TYPE_NONE) { 3032 /* End of table */ 3033 break; 3034 } 3035 reg = info->enable_reg; 3036 SOC_IF_ERROR_RETURN 3037 (soc_reg32_get(unit, reg, port, 0, &rval)); 3038 soc_reg_field_set(unit, reg, &rval, info->enable_field, 3039 enable ? 1 : 0); 3040 SOC_IF_ERROR_RETURN 3041 (soc_reg32_set(unit, reg, port, 0, rval)); 3042 3043 soc_reg_field_set(unit, group_reg, &group_rval, 3044 info->group_reg_enable_field, 3045 enable ? 1 : 0); 3046 3047 SOC_IF_ERROR_RETURN 3048 (soc_reg32_set(unit, group_reg, port, 0, group_rval)); 3049 } 3050 return SOC_E_NONE; 3051 } 3052 3053 3054 STATIC int 3055 _soc_hr3_ser_enable_info(int unit, int block_info_idx, int inst, int port, 3056 soc_reg_t group_reg, uint64 *group_rval, 3057 _soc_hr3_ser_info_t *info_list, 3058 soc_mem_t mem, int enable) 3059 { 3060 _soc_hr3_ser_info_t *info; 3061 int info_index, rv; 3062 soc_reg_t reg; 3063 uint64 rval64; 3064 3065 3066 rv = SOC_E_NOT_FOUND; 3067 3068 /* Loop through each info entry in the list */ 3069 for (info_index = 0; ; info_index++) { 3070 info = &info_list[info_index]; 3071 if (info->type == _SOC_PARITY_TYPE_NONE) { 3072 /* End of table */ 3073 break; 3074 } 3075 if (_soc_hr3_ser_mem_skip(unit, info)) { 3076 continue; 3077 } 3078 if ((mem != INVALIDm) && (mem != info->mem)) { 3079 continue; 3080 } 3081 rv = SOC_E_NONE; 3082 if (group_reg != INVALIDr && info->group_reg_enable_field != INVALIDf) { 3083 if (!soc_reg_field_valid(unit, group_reg, 3084 info->group_reg_enable_field)) { 3085 continue; 3086 } 3087 /* Enable the info entry in the group register */ 3088 soc_reg64_field32_set(unit, group_reg, group_rval, 3089 info->group_reg_enable_field, enable ? 1 : 0); 3090 } 3091 /* Handle different parity error reporting style */ 3092 switch (info->type) { 3093 case _SOC_PARITY_TYPE_PORT_XL: 3094 /* only ecc in pm, don't need mem information */ 3095 rv =_soc_hr3_pm_ser_config(unit, info->info, block_info_idx, 3096 info->intr_enable_reg, enable); 3097 break; 3098 case _SOC_PARITY_TYPE_MMU_SER: 3099 case _SOC_PARITY_TYPE_ECC: 3100 case _SOC_PARITY_TYPE_PARITY: 3101 case _SOC_PARITY_TYPE_PARITY_DUAL: 3102 reg = info->enable_reg; 3103 if (!SOC_REG_IS_VALID(unit, reg)) { 3104 break; 3105 } 3106 SOC_IF_ERROR_RETURN 3107 (soc_reg_get(unit, reg, port, 0, &rval64)); 3108 soc_reg64_field32_set(unit, reg, &rval64, info->enable_field, 3109 enable ? 1 : 0); 3110 SOC_IF_ERROR_RETURN 3111 (soc_reg_set(unit, reg, port, 0, rval64)); 3112 3113 LOG_VERBOSE(BSL_LS_SOC_SOCMEM, 3114 (BSL_META_U(unit, 3115 "SER enable for: %s\n"), 3116 (info->mem == INVALIDm) ? info->mem_str : 3117 SOC_MEM_NAME(unit, info->mem))); 3118 if (info->type == _SOC_PARITY_TYPE_MMU_SER) { 3119 rv = _soc_hr3_mmu_ser_config(unit, info->info, 3120 info->intr_enable_reg, 3121 mem, enable); 3122 } 3123 break; 3124 default: break; 3125 } 3126 } 3127 return rv; 3128 } 3129 3130 3131 int 3132 _soc_hr3_mem_parity_control(int unit, soc_mem_t mem, 3133 int copyno, int enable) 3134 { 3135 soc_reg_t parity_enable_reg = INVALIDr; 3136 soc_field_t hw_parity_field = INVALIDf; 3137 uint8 rbi; 3138 const _soc_hr3_ser_route_block_t *rb; 3139 uint32 cmic_bit; 3140 int block_info_idx; 3141 soc_mem_t memTable; 3142 int port = REG_PORT_ANY; 3143 _soc_hr3_ser_info_t *info_list, *info; 3144 int info_index; 3145 uint32 misc_cfg; 3146 3147 if (!soc_property_get(unit, spn_PARITY_ENABLE, TRUE)) { 3148 /* Parity checking is not enabled, nothing to do */ 3149 return SOC_E_NONE; 3150 } 3151 /* Convert component/aggregate memories to the table for which 3152 * the parity registers correspond. */ 3153 switch(mem) { 3154 case VLAN_SUBNET_ONLYm: 3155 case VLAN_SUBNET_DATA_ONLYm: 3156 mem = VLAN_SUBNETm; 3157 break; 3158 case L2_ENTRY_ONLYm: 3159 mem = L2Xm; 3160 break; 3161 case L2_USER_ENTRY_ONLYm: 3162 case L2_USER_ENTRY_DATA_ONLYm: 3163 mem = L2_USER_ENTRYm; 3164 break; 3165 case L3_DEFIP_DATA_ONLYm: 3166 mem = L3_DEFIPm; 3167 break; 3168 case L3_ENTRY_IPV4_UNICASTm: 3169 case L3_ENTRY_IPV6_UNICASTm: 3170 case L3_ENTRY_IPV4_MULTICASTm: 3171 case L3_ENTRY_IPV6_MULTICASTm: 3172 mem = L3_ENTRY_ONLYm; 3173 break; 3174 case VLAN_MACm: 3175 mem = VLAN_XLATEm; 3176 break; 3177 case MODPORT_MAPm: 3178 mem = MODPORT_MAP_SWm; 3179 break; 3180 default: 3181 /* Do nothing, keep memory as provided */ 3182 break; 3183 } 3184 3185 /* Loop through each place-and-route block entry */ 3186 for (rbi = 0; ; rbi++) { 3187 rb = &_soc_hr3_ser_route_blocks[unit][rbi]; 3188 cmic_bit = rb->cmic_bit; 3189 parity_enable_reg = INVALIDr; 3190 hw_parity_field = INVALIDf; 3191 if (cmic_bit == 0) { 3192 /* End of table */ 3193 break; 3194 } 3195 SOC_BLOCK_ITER(unit, block_info_idx, rb->blocktype) { 3196 if (SOC_BLOCK_INFO(unit, block_info_idx).number == rb->id) { 3197 port = SOC_BLOCK_PORT(unit, block_info_idx); 3198 break; 3199 } 3200 } 3201 if ((copyno != MEM_BLOCK_ANY) && (copyno != block_info_idx)) { 3202 continue; 3203 } 3204 info_list = rb->info; 3205 if (info_list[0].type == _SOC_PARITY_TYPE_MMU_SER) { 3206 parity_enable_reg = info_list[0].enable_reg; 3207 hw_parity_field = info_list[0].enable_field; 3208 info_list = info_list[0].info; 3209 } 3210 for (info_index = 0; ; info_index++) { 3211 info = &info_list[info_index]; 3212 if (info->type == _SOC_PARITY_TYPE_NONE) { 3213 /* End of table */ 3214 break; 3215 } 3216 if (_soc_hr3_ser_mem_skip(unit, info)) { 3217 continue; 3218 } 3219 memTable = info->mem; 3220 if (memTable == INVALIDm) { 3221 continue; 3222 } 3223 if (memTable == mem) { 3224 if (parity_enable_reg == INVALIDr) { 3225 parity_enable_reg = info->enable_reg; 3226 } 3227 if (hw_parity_field == INVALIDf) { 3228 hw_parity_field = info->enable_field; 3229 } 3230 SOC_IF_ERROR_RETURN( 3231 soc_reg_field32_modify(unit, parity_enable_reg, port, 3232 hw_parity_field, 3233 enable ? 1 : 0)); 3234 3235 return SOC_E_NONE; 3236 } 3237 } 3238 } 3239 /* MMU controls */ 3240 SOC_IF_ERROR_RETURN(READ_MISCCONFIGr(unit, &misc_cfg)); 3241 if (enable) { 3242 soc_reg_field_set(unit, MISCCONFIGr, &misc_cfg, PARITY_CHECK_ENf, 1); 3243 } else { 3244 soc_reg_field_set(unit, MISCCONFIGr, &misc_cfg, PARITY_CHECK_ENf, 0); 3245 } 3246 SOC_IF_ERROR_RETURN(WRITE_MISCCONFIGr(unit, misc_cfg)); 3247 3248 return SOC_E_NONE; 3249 } 3250 int 3251 soc_hr3_ser_enable_all(int unit, int enable) 3252 { 3253 const _soc_hr3_ser_route_block_t *rb; 3254 uint8 rbi; 3255 uint32 cmic_bit, cmic_rval = 0; 3256 int block_info_idx; 3257 int port = REG_PORT_ANY; 3258 uint64 rval64; 3259 int rv = SOC_E_NONE; 3260 3261 SOC_IF_ERROR_RETURN( 3262 soc_hr3_ser_route_blocks_init(unit)); 3263 3264 /* Loop through each place-and-route block entry */ 3265 for (rbi = 0; ; rbi++) { 3266 rb = &_soc_hr3_ser_route_blocks[unit][rbi]; 3267 cmic_bit = rb->cmic_bit; 3268 if (cmic_bit == 0) { 3269 /* End of table */ 3270 break; 3271 } 3272 cmic_rval |= cmic_bit; 3273 port = REG_PORT_ANY; 3274 SOC_BLOCK_ITER(unit, block_info_idx, rb->blocktype) { 3275 if (SOC_BLOCK_INFO(unit, block_info_idx).number == rb->id) { 3276 port = SOC_BLOCK_PORT(unit, block_info_idx); 3277 break; 3278 } 3279 } 3280 if (rb->enable_reg != INVALIDr) { 3281 if (!SOC_REG_IS_VALID(unit, rb->enable_reg)) { 3282 continue; 3283 } 3284 if (SOC_BLOCK_IN_LIST(SOC_REG_INFO(unit, rb->enable_reg).block, 3285 SOC_BLK_PORT) && (port == REG_PORT_ANY)) { 3286 /* This port block is not configured */ 3287 continue; 3288 } 3289 SOC_IF_ERROR_RETURN 3290 (soc_reg_get(unit, rb->enable_reg, port, 0, &rval64)); 3291 } 3292 rv = _soc_hr3_ser_enable_info(unit, block_info_idx, rb->id, port, 3293 rb->enable_reg, &rval64, 3294 rb->info, INVALIDm, enable); 3295 if (rv == SOC_E_NOT_FOUND) { 3296 continue; 3297 } else if (SOC_FAILURE(rv)) { 3298 return rv; 3299 } 3300 3301 if (rb->enable_reg != INVALIDr) { 3302 /* Write per route block parity enable register */ 3303 SOC_IF_ERROR_RETURN 3304 (soc_reg_set(unit, rb->enable_reg, port, 0, rval64)); 3305 } 3306 } 3307 if (enable) { 3308 /* Write CMIC enable register */ 3309 (void)soc_cmicm_intr3_enable(unit, cmic_rval); 3310 } else { 3311 /* Write CMIC disable register */ 3312 (void)soc_cmicm_intr3_disable(unit, cmic_rval); 3313 } 3314 return SOC_E_NONE; 3315 } 3316 3317 3318 void 3319 soc_hr3_ser_error(void *unit_vp, void *d1, void *d2, void *d3, 3320 void *d4) 3321 { 3322 int unit = PTR_TO_INT(unit_vp); 3323 uint32 irq_stat; 3324 uint32 ip1_stat; 3325 3326 3327 (void)READ_CMIC_CMC0_IRQ_STAT3r(unit, &irq_stat); 3328 3329 if (irq_stat & _HR3_X_TO_CMIC_INTR(_HR3_PAR_IP1)){ 3330 (void)soc_reg32_get(unit, IP1_INTR_STATUSr, REG_PORT_ANY, 3331 0, &ip1_stat); 3332 if (ip1_stat) { 3333 /* oam process */ 3334 (void) soc_hr3_process_oam_interrupt(unit); 3335 /* l2 */ 3336 (void) _soc_hr3_process_l2_overflow(unit); 3337 } 3338 } 3339 (void)_soc_hr3_ser_process_all(unit, irq_stat); 3340 sal_usleep(SAL_BOOT_QUICKTURN ? 1000000 : 10000); 3341 (void)soc_cmicm_intr3_enable(unit, PTR_TO_INT(d2)); 3342 } 3343 3344 static _soc_generic_ser_info_t _soc_hr3_tcam_ser_info_template[] = { 3345 #if _HR3_SER_TEST_TCAM 3346 { VFP_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_4BITS, 3347 _SOC_SER_INTERLEAVE_MOD2, 3348 { {0, 235}, {1, 235}, {236, 469}, {237, 469} }, 0, 0, 0, 0, 3349 _SOC_SER_FLAG_XY_READ}, 3350 { L2_USER_ENTRYm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_4BITS, 3351 _SOC_SER_INTERLEAVE_MOD2, 3352 { {0, 69}, {1, 69}, {70, 138}, {71, 138} }, 0, 0, 0, 0, 3353 _SOC_SER_FLAG_XY_READ}, 3354 { FP_GLOBAL_MASK_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, 3355 _SOC_SER_PARITY_4BITS, _SOC_SER_INTERLEAVE_MOD2, 3356 { {0, 37}, {1, 37}, {38, 74}, {39, 74} }, 0, 0, 0, 0, 3357 _SOC_SER_FLAG_XY_READ}, 3358 { VLAN_SUBNETm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_4BITS, 3359 _SOC_SER_INTERLEAVE_MOD2, 3360 { {0, 64}, {1, 64}, {65, 128}, {66, 128} }, 0, 0, 0, 0, 3361 _SOC_SER_FLAG_XY_READ}, 3362 { L3_DEFIPm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_4BITS, 3363 _SOC_SER_INTERLEAVE_MOD2, 3364 { {0, 69}, {1, 69}, {70, 138}, {71, 138} }, 0, 0, 0, 0, 3365 _SOC_SER_FLAG_XY_READ}, 3366 { CPU_COS_MAPm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_4BITS, 3367 _SOC_SER_INTERLEAVE_MOD2, 3368 { {0, 69}, {1, 69}, {70, 138}, {71, 138} }, 0, 0, 0, 0, 3369 _SOC_SER_FLAG_XY_READ}, 3370 { EFP_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_4BITS, 3371 _SOC_SER_INTERLEAVE_MOD2, 3372 { {0, 235}, {1, 235}, {236, 469}, {237, 469} }, 0, 0, 0, 0, 3373 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_NO_DMA}, 3374 { FP_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_4BITS, 3375 _SOC_SER_INTERLEAVE_MOD2, 3376 { {0, 235}, {1, 235}, {236, 469}, {237, 469} }, 0, 0, 0, 0, 3377 _SOC_SER_FLAG_XY_READ}, 3378 #endif /* _HR3_SER_TEST_TCAM */ 3379 /* End of list */ 3380 { INVALIDm }, 3381 }; 3382 static _soc_generic_ser_info_t _soc_hr3l_tcam_ser_info_template[] = { 3383 #if _HR3_SER_TEST_TCAM 3384 { L2_USER_ENTRYm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_4BITS, 3385 _SOC_SER_INTERLEAVE_MOD2, 3386 { {0, 69}, {1, 69}, {70, 138}, {71, 138} }, 0, 0, 0, 0, 3387 _SOC_SER_FLAG_XY_READ}, 3388 { FP_GLOBAL_MASK_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, 3389 _SOC_SER_PARITY_4BITS, _SOC_SER_INTERLEAVE_MOD2, 3390 { {0, 37}, {1, 37}, {38, 74}, {39, 74} }, 0, 0, 0, 0, 3391 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_NO_DMA}, 3392 { VLAN_SUBNETm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_4BITS, 3393 _SOC_SER_INTERLEAVE_MOD2, 3394 { {0, 64}, {1, 64}, {65, 128}, {66, 128} }, 0, 0, 0, 0, 3395 _SOC_SER_FLAG_XY_READ}, 3396 { L3_DEFIPm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_4BITS, 3397 _SOC_SER_INTERLEAVE_MOD2, 3398 { {0, 69}, {1, 69}, {70, 138}, {71, 138} }, 0, 0, 0, 0, 3399 _SOC_SER_FLAG_XY_READ}, 3400 { CPU_COS_MAPm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_4BITS, 3401 _SOC_SER_INTERLEAVE_MOD2, 3402 { {0, 69}, {1, 69}, {70, 138}, {71, 138} }, 0, 0, 0, 0, 3403 _SOC_SER_FLAG_XY_READ}, 3404 { FP_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_4BITS, 3405 _SOC_SER_INTERLEAVE_MOD2, 3406 { {0, 235}, {1, 235}, {236, 469}, {237, 469} }, 0, 0, 0, 0, 3407 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_NO_DMA}, 3408 #endif /* _HR3_SER_TEST_TCAM */ 3409 /* End of list */ 3410 { INVALIDm }, 3411 }; 3412 static _soc_generic_ser_info_t _soc_bh_tcam_ser_info_template[] = { 3413 #if _HR3_SER_TEST_TCAM 3414 { VFP_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_4BITS, 3415 _SOC_SER_INTERLEAVE_MOD2, 3416 { {0, 235}, {1, 235}, {236, 469}, {237, 469} }, 0, 0, 0, 0, 3417 _SOC_SER_FLAG_XY_READ}, 3418 { L2_USER_ENTRYm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_4BITS, 3419 _SOC_SER_INTERLEAVE_MOD2, 3420 { {0, 69}, {1, 69}, {70, 138}, {71, 138} }, 0, 0, 0, 0, 3421 _SOC_SER_FLAG_XY_READ}, 3422 { FP_GLOBAL_MASK_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, 3423 _SOC_SER_PARITY_4BITS, _SOC_SER_INTERLEAVE_MOD2, 3424 { {0, 37}, {1, 37}, {38, 74}, {39, 74} }, 0, 0, 0, 0, 3425 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_NO_DMA}, 3426 { VLAN_SUBNETm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_4BITS, 3427 _SOC_SER_INTERLEAVE_MOD2, 3428 { {0, 64}, {1, 64}, {65, 128}, {66, 128} }, 0, 0, 0, 0, 3429 _SOC_SER_FLAG_XY_READ}, 3430 { CPU_COS_MAPm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_4BITS, 3431 _SOC_SER_INTERLEAVE_MOD2, 3432 { {0, 69}, {1, 69}, {70, 138}, {71, 138} }, 0, 0, 0, 0, 3433 _SOC_SER_FLAG_XY_READ}, 3434 { EFP_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_4BITS, 3435 _SOC_SER_INTERLEAVE_MOD2, 3436 { {0, 235}, {1, 235}, {236, 469}, {237, 469} }, 0, 0, 0, 0, 3437 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_NO_DMA}, 3438 { FP_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_4BITS, 3439 _SOC_SER_INTERLEAVE_MOD2, 3440 { {0, 235}, {1, 235}, {236, 469}, {237, 469} }, 0, 0, 0, 0, 3441 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_NO_DMA}, 3442 #endif /* _HR3_SER_TEST_TCAM */ 3443 /* End of list */ 3444 { INVALIDm }, 3445 }; 3446 static _soc_generic_ser_info_t _soc_fh2_tcam_ser_info_template[] = { 3447 #if _HR3_SER_TEST_TCAM 3448 { L2_USER_ENTRYm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_4BITS, 3449 _SOC_SER_INTERLEAVE_MOD2, 3450 { {0, 69}, {1, 69}, {70, 138}, {71, 138} }, 0, 0, 0, 0, 3451 _SOC_SER_FLAG_XY_READ}, 3452 { FP_GLOBAL_MASK_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, 3453 _SOC_SER_PARITY_4BITS, _SOC_SER_INTERLEAVE_MOD2, 3454 { {0, 37}, {1, 37}, {38, 74}, {39, 74} }, 0, 0, 0, 0, 3455 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_NO_DMA}, 3456 { CPU_COS_MAPm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_4BITS, 3457 _SOC_SER_INTERLEAVE_MOD2, 3458 { {0, 69}, {1, 69}, {70, 138}, {71, 138} }, 0, 0, 0, 0, 3459 _SOC_SER_FLAG_XY_READ}, 3460 { FP_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_4BITS, 3461 _SOC_SER_INTERLEAVE_MOD2, 3462 { {0, 235}, {1, 235}, {236, 469}, {237, 469} }, 0, 0, 0, 0, 3463 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_NO_DMA}, 3464 #endif /* _HR3_SER_TEST_TCAM */ 3465 /* End of list */ 3466 { INVALIDm }, 3467 }; 3468 3469 static _soc_generic_ser_info_t _soc_wh2_tcam_ser_info_template[] = { 3470 #if _HR3_SER_TEST_TCAM 3471 { L2_USER_ENTRYm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_4BITS, 3472 _SOC_SER_INTERLEAVE_MOD2, 3473 { {0, 69}, {1, 69}, {70, 138}, {71, 138} }, 0, 0, 0, 0, 3474 _SOC_SER_FLAG_XY_READ}, 3475 { FP_GLOBAL_MASK_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, 3476 _SOC_SER_PARITY_4BITS, _SOC_SER_INTERLEAVE_MOD2, 3477 { {0, 37}, {1, 37}, {38, 74}, {39, 74} }, 0, 0, 0, 0, 3478 _SOC_SER_FLAG_XY_READ}, 3479 { VLAN_SUBNETm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_4BITS, 3480 _SOC_SER_INTERLEAVE_MOD2, 3481 { {0, 64}, {1, 64}, {65, 128}, {66, 128} }, 0, 0, 0, 0, 3482 _SOC_SER_FLAG_XY_READ}, 3483 { L3_DEFIPm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_4BITS, 3484 _SOC_SER_INTERLEAVE_MOD2, 3485 { {0, 69}, {1, 69}, {70, 138}, {71, 138} }, 0, 0, 0, 0, 3486 _SOC_SER_FLAG_XY_READ}, 3487 { CPU_COS_MAPm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_4BITS, 3488 _SOC_SER_INTERLEAVE_MOD2, 3489 { {0, 69}, {1, 69}, {70, 138}, {71, 138} }, 0, 0, 0, 0, 3490 _SOC_SER_FLAG_XY_READ}, 3491 { FP_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, _SOC_SER_PARITY_4BITS, 3492 _SOC_SER_INTERLEAVE_MOD2, 3493 { {0, 235}, {1, 235}, {236, 469}, {237, 469} }, 0, 0, 0, 0, 3494 _SOC_SER_FLAG_XY_READ}, 3495 #endif /* _HR3_SER_TEST_TCAM */ 3496 /* End of list */ 3497 { INVALIDm }, 3498 }; 3499 3500 static _soc_generic_ser_info_t *_soc_hr3_tcam_ser_info[SOC_MAX_NUM_DEVICES] = {NULL}; 3501 3502 int 3503 soc_hr3_tcam_ser_init(int unit) 3504 { 3505 int alloc_size; 3506 int sku; 3507 3508 /* First, make per-unit copy of the master TCAM list */ 3509 alloc_size = sizeof(_soc_hr3_tcam_ser_info_template); 3510 if (NULL == _soc_hr3_tcam_ser_info[unit]) { 3511 if ((_soc_hr3_tcam_ser_info[unit] = 3512 sal_alloc(alloc_size, "hr3 tcam list")) == NULL) { 3513 return SOC_E_MEMORY; 3514 } 3515 sal_memset(_soc_hr3_tcam_ser_info[unit], 0, alloc_size); 3516 } 3517 if (soc_feature(unit, soc_feature_wh2)) { 3518 /* Wolfhound2 */ 3519 sal_memcpy(_soc_hr3_tcam_ser_info[unit], 3520 &(_soc_wh2_tcam_ser_info_template), 3521 sizeof(_soc_wh2_tcam_ser_info_template)); 3522 } else { 3523 (void)soc_hurricane3_chip_sku_get(unit, &sku); 3524 if (sku == SOC_HR3_SKU_HURRICANE3) { 3525 /* Hurricane3 */ 3526 sal_memcpy(_soc_hr3_tcam_ser_info[unit], 3527 &(_soc_hr3_tcam_ser_info_template), 3528 alloc_size); 3529 } else if (sku == SOC_HR3_SKU_HURRICANE3LITE) { 3530 /* Hurricane3_Lite: no EFP,VFP */ 3531 sal_memcpy(_soc_hr3_tcam_ser_info[unit], 3532 &(_soc_hr3l_tcam_ser_info_template), 3533 sizeof(_soc_hr3l_tcam_ser_info_template)); 3534 } else if (sku == SOC_HR3_SKU_BUCKHOUND) { 3535 /* Buckhound,Foxhound2: no EFP, VFP, L3_DEFIP */ 3536 sal_memcpy(_soc_hr3_tcam_ser_info[unit], 3537 &(_soc_bh_tcam_ser_info_template), 3538 sizeof(_soc_bh_tcam_ser_info_template)); 3539 } else { 3540 /* Foxhound2: no EFP, VFP, L3_DEFIP, VLAN_SUBNET */ 3541 sal_memcpy(_soc_hr3_tcam_ser_info[unit], 3542 &(_soc_fh2_tcam_ser_info_template), 3543 sizeof(_soc_fh2_tcam_ser_info_template)); 3544 } 3545 } 3546 3547 #ifdef INCLUDE_MEM_SCAN 3548 soc_mem_scan_ser_list_register(unit, TRUE, 3549 _soc_hr3_tcam_ser_info[unit]); 3550 #endif 3551 return soc_generic_ser_init(unit, _soc_hr3_tcam_ser_info[unit]); 3552 } 3553 void 3554 soc_hr3_ser_fail(int unit) 3555 { 3556 soc_generic_ser_process_error(unit, _soc_hr3_tcam_ser_info[unit], 3557 _SOC_PARITY_TYPE_SER); 3558 } 3559 3560 void 3561 soc_hr3_ser_register(int unit) 3562 { 3563 memset(&_hr3_ser_functions, 0, sizeof(soc_ser_functions_t)); 3564 _hr3_ser_functions._soc_ser_fail_f = &soc_hr3_ser_fail; 3565 _hr3_ser_functions._soc_ser_parity_error_cmicm_intr_f = 3566 &soc_hr3_ser_error; 3567 soc_ser_function_register(unit, &_hr3_ser_functions); 3568 } 3569 3570 #if defined(SER_TR_TEST_SUPPORT) 3571 int 3572 ser_test_hr3_mem_index_remap(int unit, ser_test_data_t *test_data, 3573 int *mem_has_ecc) 3574 { 3575 int uft_bkt_bank = 0; 3576 int uft_le_fv = 0; 3577 int uft_le_ecc = 0; 3578 int remap_status = 0; 3579 3580 *mem_has_ecc = 0; 3581 test_data->mem = test_data->mem_fv; 3582 test_data->index = test_data->index_fv; 3583 3584 if (_soc_hr3_ser_2bit_ecc_mem(unit, test_data->mem_fv)) { 3585 *mem_has_ecc = 1; 3586 } 3587 3588 if ((test_data->mem != test_data->mem_fv) || 3589 (test_data->index != test_data->index_fv)) { 3590 LOG_VERBOSE(BSL_LS_SOC_SER, 3591 (BSL_META_U(unit, 3592 "unit %d, ser_test_mem_index_remap: " 3593 "mem_fv %s, index_fv %0d, mem %s, index %0d, " 3594 "uft_bkt_bank %0d, uft_le_fv %0d, " 3595 "uft_le_ecc %0d, remap_status %0d \n"), 3596 unit, SOC_MEM_NAME(unit, test_data->mem_fv), test_data->index_fv, 3597 SOC_MEM_NAME(unit, test_data->mem), test_data->index, 3598 uft_bkt_bank, uft_le_fv, uft_le_ecc, remap_status)); 3599 } 3600 return remap_status; 3601 } 3602 3603 soc_ser_test_functions_t ser_hr3_test_fun; 3604 3605 /* Overlay memory */ 3606 const soc_ser_overlay_test_t soc_ser_hr3_overlay_mems[] = { 3607 {L3_ENTRY_IPV4_UNICASTm, L3_ENTRY_PARITY_CONTROLr, PARITY_ENf, L3_ENTRY_ONLYm, _SOC_ACC_TYPE_PIPE_ANY}, 3608 {L3_ENTRY_IPV4_MULTICASTm, L3_ENTRY_PARITY_CONTROLr, PARITY_ENf, L3_ENTRY_ONLYm, _SOC_ACC_TYPE_PIPE_ANY}, 3609 {L3_ENTRY_IPV6_MULTICASTm, L3_ENTRY_PARITY_CONTROLr, PARITY_ENf, L3_ENTRY_ONLYm, _SOC_ACC_TYPE_PIPE_ANY}, 3610 {L3_ENTRY_IPV6_UNICASTm, L3_ENTRY_PARITY_CONTROLr, PARITY_ENf, L3_ENTRY_ONLYm, _SOC_ACC_TYPE_PIPE_ANY}, 3611 {MODPORT_MAPm, MODPORT_MAP_SW_PARITY_CONTROLr, PARITY_ENf, MODPORT_MAP_SWm, _SOC_ACC_TYPE_PIPE_ANY}, 3612 {INVALIDm} 3613 }; 3614 3615 STATIC int soc_hr3_tcam_entry_is_invalid(int unit, 3616 soc_mem_t mem, int index) 3617 { 3618 if (soc_feature(unit, soc_feature_field_slice_size128)) { 3619 if (mem == FP_GLOBAL_MASK_TCAMm || mem == FP_TCAMm) { 3620 if ((index / 64) % 2) { 3621 return TRUE; 3622 } 3623 } 3624 } 3625 return FALSE; 3626 } 3627 3628 /* 3629 * Function: 3630 * soc_hr3_ser_inject_error 3631 * Purpose: 3632 * Injects an error into a single memory 3633 * Parameters: 3634 * unit - (IN) Device Number 3635 * mem - (IN) The memory to test 3636 * pipeTarget - (IN) The pipe (x/y) to use when injecting the error 3637 * block - (IN) The index into which block will be injected. 3638 * index - (IN) The index into which the error will be injected. 3639 */ 3640 int soc_hr3_ser_inject_error(int unit, uint32 flags, soc_mem_t mem, 3641 int pipeTarget, int block, int index) 3642 { 3643 _soc_generic_ser_info_t *tcam_ser_info = _soc_hr3_tcam_ser_info[unit]; 3644 soc_reg_t parity_enable_reg = INVALIDr; 3645 soc_field_t hw_parity_field = INVALIDf; 3646 uint8 rbi; 3647 const _soc_hr3_ser_route_block_t *rb; 3648 uint32 cmic_bit; 3649 int block_info_idx; 3650 soc_mem_t memTable; 3651 uint32 tmp_entry[SOC_MAX_MEM_WORDS], fieldData[SOC_MAX_REG_FIELD_WORDS]; 3652 int i, overlay_mem = 0; 3653 ser_test_data_t test_data; 3654 int port = REG_PORT_ANY; 3655 _soc_hr3_ser_info_t *info_list, *info; 3656 int info_index; 3657 3658 if (!SOC_MEM_IS_VALID(unit, mem)) { 3659 LOG_ERROR(BSL_LS_SOC_COMMON, 3660 (BSL_META_U(unit, 3661 "unit %d, mem %d is INVALID or not valid " 3662 "for this unit !!\n"), 3663 unit, mem)); 3664 return SOC_E_UNAVAIL; 3665 } 3666 if (tcam_ser_info != NULL) { 3667 /*TCAM_test*/ 3668 for (i = 0; tcam_ser_info[i].mem != INVALIDm; i++) { 3669 if (tcam_ser_info[i].mem == mem) { 3670 /* Check if this entry is invalid or not */ 3671 if (soc_hr3_tcam_entry_is_invalid(unit, mem, index)) { 3672 return (SOC_E_PARAM); 3673 } 3674 soc_ser_create_test_data(unit, tmp_entry, fieldData, 3675 SER_RANGE_ENABLEr, i, VALIDf, mem, 3676 VALIDf, MEM_BLOCK_ANY, REG_PORT_ANY, 3677 _SOC_ACC_TYPE_PIPE_ANY, index, &test_data); 3678 /*Disable parity*/ 3679 SOC_IF_ERROR_RETURN( 3680 _ser_test_parity_control(unit, &test_data, 0)); 3681 /*Read the memory for successful injection*/ 3682 SOC_IF_ERROR_RETURN(ser_test_mem_read(unit, 0, &test_data)); 3683 /*Inject error*/ 3684 SOC_IF_ERROR_RETURN(soc_ser_test_inject_full(unit, flags, 3685 &test_data)); 3686 /*Enable parity*/ 3687 SOC_IF_ERROR_RETURN( 3688 _ser_test_parity_control(unit, &test_data, 1)); 3689 return SOC_E_NONE; 3690 } 3691 } 3692 } 3693 3694 /* Loop through each place-and-route block entry */ 3695 for (rbi = 0; ; rbi++) { 3696 rb = &_soc_hr3_ser_route_blocks[unit][rbi]; 3697 cmic_bit = rb->cmic_bit; 3698 parity_enable_reg = INVALIDr; 3699 hw_parity_field = INVALIDf; 3700 if (cmic_bit == 0) { 3701 /* End of table */ 3702 break; 3703 } 3704 SOC_BLOCK_ITER(unit, block_info_idx, rb->blocktype) { 3705 if (SOC_BLOCK_INFO(unit, block_info_idx).number == rb->id) { 3706 port = SOC_BLOCK_PORT(unit, block_info_idx); 3707 break; 3708 } 3709 } 3710 if ((block != MEM_BLOCK_ANY) && (block != block_info_idx)) { 3711 continue; 3712 } 3713 info_list = rb->info; 3714 if (info_list[0].type == _SOC_PARITY_TYPE_MMU_SER) { 3715 parity_enable_reg = info_list[0].enable_reg; 3716 hw_parity_field = info_list[0].enable_field; 3717 info_list = info_list[0].info; 3718 } 3719 for (info_index = 0; ; info_index++) { 3720 info = &info_list[info_index]; 3721 if (info->type == _SOC_PARITY_TYPE_NONE) { 3722 /* End of table */ 3723 break; 3724 } 3725 if (_soc_hr3_ser_mem_skip(unit, info)) { 3726 continue; 3727 } 3728 memTable = info->mem; 3729 if (memTable == INVALIDm) { 3730 continue; 3731 } 3732 /* Check if overlay memory */ 3733 for (i=0; soc_ser_hr3_overlay_mems[i].mem != INVALIDm; i++) { 3734 if ((soc_ser_hr3_overlay_mems[i].mem == mem) && 3735 (soc_ser_hr3_overlay_mems[i].base_mem == memTable)) { 3736 overlay_mem = 1; 3737 break; 3738 } 3739 } 3740 if ((memTable == mem) || (overlay_mem)) { 3741 /*Inject error*/ 3742 test_data.mem = mem; 3743 test_data.tcam_parity_bit = -1; 3744 if (parity_enable_reg == INVALIDr) { 3745 parity_enable_reg = info->enable_reg; 3746 } 3747 if (hw_parity_field == INVALIDf) { 3748 hw_parity_field = info->enable_field; 3749 } 3750 if (_soc_hr3_ser_2bit_ecc_mem(unit, memTable)) { 3751 flags |= SOC_INJECT_ERROR_2BIT_ECC; 3752 } 3753 soc_ser_create_test_data(unit, tmp_entry, 3754 fieldData, 3755 parity_enable_reg, 3756 SOC_INVALID_TCAM_PARITY_BIT, 3757 hw_parity_field, 3758 mem, EVEN_PARITYf, block, 3759 port, _SOC_ACC_TYPE_PIPE_ANY, 3760 index, &test_data); 3761 /*Disable parity*/ 3762 SOC_IF_ERROR_RETURN(_ser_test_parity_control( 3763 unit, &test_data, 0)); 3764 /*Read the memory for successful injection*/ 3765 SOC_IF_ERROR_RETURN(ser_test_mem_read( 3766 unit, 0, &test_data)); 3767 /*Inject error*/ 3768 SOC_IF_ERROR_RETURN(soc_ser_test_inject_full( 3769 unit, flags, &test_data)); 3770 /*Enable parity*/ 3771 SOC_IF_ERROR_RETURN(_ser_test_parity_control( 3772 unit, &test_data, 1)); 3773 return SOC_E_NONE; 3774 } 3775 } 3776 } 3777 /* The tested memory is not found in SER enabled list, can't inject error of it */ 3778 return SOC_E_UNAVAIL; 3779 } 3780 3781 STATIC soc_error_t 3782 _ser_hr3_ser_error_injection_support(int unit, soc_mem_t mem, 3783 int pipe_target) 3784 { 3785 int rv = SOC_E_UNAVAIL; 3786 int i = 0, hw_enable_ix = 0; 3787 int overlay_mem = 0, block_info_idx = 0; 3788 uint32 range_enable; 3789 3790 uint8 rbi; 3791 soc_mem_t memTable; 3792 int info_index; 3793 _soc_generic_ser_info_t *tcam_ser_info; 3794 const _soc_hr3_ser_route_block_t *rb; 3795 _soc_hr3_ser_info_t *info_list, *info; 3796 3797 if ((mem == MMU_WRED_AVG_QSIZEm) || 3798 (mem == MMU_WRED_MARK_THDm)) { 3799 /* 3800 * Inject function aim for SQA to test SER in an easiler way 3801 * To support above memories, soc_mem_read need to support 3802 * FUNCTIONAL_REFRESH_ENr which is not a general case of SER. 3803 * Also, TR144 & SER recovery have supported those memories. 3804 * Thus, we disable them on inject function. 3805 */ 3806 return rv; 3807 } 3808 LOG_VERBOSE(BSL_LS_SOC_SER, 3809 (BSL_META_U(unit, 3810 "unit %d, mem %s, pipe_target %d\n"), 3811 unit, SOC_MEM_NAME(unit,mem), pipe_target)); 3812 3813 if (!SOC_MEM_IS_VALID(unit, mem)) { 3814 LOG_ERROR(BSL_LS_SOC_COMMON, 3815 (BSL_META_U(unit, 3816 "unit %d, mem %d is INVALID or not valid " 3817 "for this unit !!\n"), 3818 unit, mem)); 3819 return rv; 3820 } 3821 3822 tcam_ser_info = _soc_hr3_tcam_ser_info[unit]; 3823 3824 /* Search TCAMs */ 3825 if (tcam_ser_info != NULL) { 3826 3827 /* Check if enable */ 3828 SOC_IF_ERROR_RETURN 3829 (READ_SER_RANGE_ENABLEr(unit, &range_enable)); 3830 LOG_DEBUG(BSL_LS_SOC_SER, 3831 (BSL_META_U(unit, 3832 "Search TCAMs: SER_RANGE_ENABLE 0x%X\n"), 3833 range_enable)); 3834 for (i = 0; tcam_ser_info[i].mem != INVALIDm; i++) { 3835 if (tcam_ser_info[i].mem == mem) { 3836 3837 hw_enable_ix = tcam_ser_info[i].ser_hw_index; 3838 LOG_DEBUG(BSL_LS_SOC_SER, 3839 (BSL_META_U(unit, 3840 "SER Range HW Enable index %d\n"), 3841 hw_enable_ix)); 3842 if (((range_enable >> hw_enable_ix) & 0x1) == 0) { 3843 LOG_WARN(BSL_LS_SOC_SER, 3844 (BSL_META_U( 3845 unit, 3846 "matched mem but SER detection is disabled\n" 3847 "SER_RANGE_ENABLE 0x%X, SER Range HW index %d\n"), 3848 range_enable, hw_enable_ix)); 3849 return rv; /* matched mem but ser_detection is disabled */ 3850 } 3851 LOG_VERBOSE(BSL_LS_SOC_SER, 3852 (BSL_META_U(unit, 3853 "TCAM found\n"))); 3854 return SOC_E_NONE; /* found */ 3855 } 3856 } 3857 } 3858 3859 3860 /* Search H/W memory (route blocks) */ 3861 /* Loop through each place-and-route block entry */ 3862 for (rbi = 0; ; rbi++) { 3863 rb = &_soc_hr3_ser_route_blocks[unit][rbi]; 3864 if (rb->cmic_bit == 0) { 3865 /* End of table */ 3866 break; 3867 } 3868 3869 SOC_BLOCK_ITER(unit, block_info_idx, rb->blocktype) { 3870 if (SOC_BLOCK_INFO(unit, block_info_idx).number == rb->id) { 3871 break; 3872 } 3873 } 3874 3875 info_list = rb->info; 3876 if (info_list[0].type == _SOC_PARITY_TYPE_MMU_SER) { 3877 info_list = info_list[0].info; 3878 } 3879 for (info_index = 0; ; info_index++) { 3880 info = &info_list[info_index]; 3881 if (info->type == _SOC_PARITY_TYPE_NONE) { 3882 /* End of table */ 3883 break; 3884 } 3885 if (_soc_hr3_ser_mem_skip(unit, info)) { 3886 continue; 3887 } 3888 memTable = info->mem; 3889 if (memTable == INVALIDm) { 3890 continue; 3891 } 3892 /* Check if overlay memory */ 3893 for (i=0; soc_ser_hr3_overlay_mems[i].mem != INVALIDm; i++) { 3894 if ((soc_ser_hr3_overlay_mems[i].mem == mem) && 3895 (soc_ser_hr3_overlay_mems[i].base_mem == memTable)) { 3896 overlay_mem = 1; 3897 LOG_DEBUG(BSL_LS_SOC_SER, 3898 (BSL_META_U(unit, 3899 "mem %s base_mem %s\n"), 3900 SOC_MEM_NAME(unit,mem),SOC_MEM_NAME(unit,memTable))); 3901 break; 3902 } 3903 } 3904 if ((memTable == mem) || (overlay_mem)) { 3905 LOG_VERBOSE(BSL_LS_SOC_SER, 3906 (BSL_META_U(unit, 3907 "H/W memory (route blocks) found\n"))); 3908 return SOC_E_NONE; 3909 } 3910 } 3911 } 3912 /* The tested memory is not found in SER enabled list, can't inject error of it */ 3913 return rv; 3914 } 3915 3916 3917 /* 3918 * Function: 3919 * soc_hr3_ser_mem_test 3920 * Purpose: 3921 * Performs a SER test on a single memory 3922 * Parameters: 3923 * unit - (IN) Device Number 3924 * mem - (IN) The memory to test 3925 * test_type - (IN) How many indices in the memory to test 3926 * cmd - (IN) TRUE if a command-line test is desired. 3927 */ 3928 int soc_hr3_ser_test_mem(int unit, soc_mem_t mem, 3929 _soc_ser_test_t test_type, int cmd) 3930 { 3931 _soc_generic_ser_info_t *tcam_ser_info = _soc_hr3_tcam_ser_info[unit]; 3932 soc_reg_t parity_enable_reg = INVALIDr; 3933 soc_field_t hw_parity_field = INVALIDf; 3934 uint8 rbi; 3935 const _soc_hr3_ser_route_block_t *rb; 3936 uint32 cmic_bit; 3937 int block_info_idx; 3938 int found_mem = FALSE; 3939 soc_mem_t memTable; 3940 int testErrors = 0; 3941 ser_test_data_t test_data; 3942 uint32 tmp_entry[SOC_MAX_MEM_WORDS], fieldData[SOC_MAX_REG_FIELD_WORDS]; 3943 int i, overlay_mem = 0; 3944 int rv = SOC_E_NONE; 3945 int port = REG_PORT_ANY; 3946 _soc_hr3_ser_info_t *info_list, *info; 3947 int info_index; 3948 uint32 wred_refresh = 0, reg_val; 3949 3950 if (!SOC_MEM_IS_VALID(unit, mem)) { 3951 LOG_ERROR(BSL_LS_SOC_COMMON, 3952 (BSL_META_U(unit, 3953 "unit %d, mem %d is INVALID or not valid " 3954 "for this unit !!\n"), 3955 unit, mem)); 3956 return SOC_E_UNAVAIL; 3957 } 3958 3959 if (!SAL_BOOT_QUICKTURN) { 3960 soc_ser_test_long_sleep = TRUE; 3961 soc_ser_test_long_sleep_time_us = 500000; 3962 } 3963 if (tcam_ser_info != NULL) { 3964 /*TCAM_test*/ 3965 for (i = 0; tcam_ser_info[i].mem != INVALIDm; i++) { 3966 if (tcam_ser_info[i].mem == mem) { 3967 memTable = mem; 3968 found_mem = TRUE; 3969 soc_ser_create_test_data(unit, tmp_entry, fieldData, 3970 SER_RANGE_ENABLEr, i, INVALIDf, memTable, 3971 VALIDf, MEM_BLOCK_ANY, REG_PORT_ANY, 3972 _SOC_ACC_TYPE_PIPE_ANY, 0, &test_data); 3973 if (cmd) { 3974 ser_test_cmd_generate(unit, &test_data); 3975 } else { 3976 rv = ser_test_mem(unit, 0, &test_data, 3977 test_type, &testErrors); 3978 if (rv != SOC_E_NONE) { 3979 LOG_CLI((BSL_META_U( 3980 unit, 3981 "Error during TCAM test. Aborting.\n"))); 3982 soc_ser_test_long_sleep = FALSE; 3983 return rv; 3984 } 3985 } 3986 } 3987 } 3988 } 3989 if (!found_mem) { 3990 /*H/W memory Test*/ 3991 /* Loop through each place-and-route block entry */ 3992 for (rbi = 0; ; rbi++) { 3993 rb = &_soc_hr3_ser_route_blocks[unit][rbi]; 3994 cmic_bit = rb->cmic_bit; 3995 parity_enable_reg = INVALIDr; 3996 hw_parity_field = INVALIDf; 3997 if (cmic_bit == 0) { 3998 /* End of table */ 3999 break; 4000 } 4001 SOC_BLOCK_ITER(unit, block_info_idx, rb->blocktype) { 4002 if (SOC_BLOCK_INFO(unit, block_info_idx).number == rb->id) { 4003 port = SOC_BLOCK_PORT(unit, block_info_idx); 4004 break; 4005 } 4006 } 4007 4008 info_list = rb->info; 4009 if (info_list[0].type == _SOC_PARITY_TYPE_MMU_SER) { 4010 parity_enable_reg = info_list[0].enable_reg; 4011 hw_parity_field = info_list[0].enable_field; 4012 info_list = info_list[0].info; 4013 } 4014 for (info_index = 0; ; info_index++) { 4015 info = &info_list[info_index]; 4016 if (info->type == _SOC_PARITY_TYPE_NONE) { 4017 /* End of table */ 4018 break; 4019 } 4020 if (_soc_hr3_ser_mem_skip(unit, info)) { 4021 continue; 4022 } 4023 memTable = info->mem; 4024 if (memTable == INVALIDm) { 4025 continue; 4026 } 4027 /* Check if overlay memory */ 4028 for (i=0; soc_ser_hr3_overlay_mems[i].mem != INVALIDm; i++) { 4029 if ((soc_ser_hr3_overlay_mems[i].mem == mem) && 4030 (soc_ser_hr3_overlay_mems[i].base_mem == memTable)) { 4031 overlay_mem = 1; 4032 break; 4033 } 4034 } 4035 if ((memTable == mem) || (overlay_mem)) { 4036 found_mem = TRUE; 4037 if (parity_enable_reg == INVALIDr) { 4038 parity_enable_reg = info->enable_reg; 4039 } 4040 if (hw_parity_field == INVALIDf) { 4041 hw_parity_field = info->enable_field; 4042 } 4043 if ((memTable == MMU_WRED_AVG_QSIZEm) || 4044 (memTable == MMU_WRED_MARK_THDm)) { 4045 rv = soc_reg32_get(unit, 4046 FUNCTIONAL_REFRESH_ENr, port, 0, 4047 ®_val); 4048 if (rv != SOC_E_NONE) { 4049 LOG_CLI((BSL_META_U( 4050 unit, 4051 "Error of getting WRED " 4052 "refresh function Aborting.\n"))); 4053 soc_ser_test_long_sleep = FALSE; 4054 return rv; 4055 } 4056 wred_refresh = soc_reg_field_get( 4057 unit, FUNCTIONAL_REFRESH_ENr, 4058 reg_val, WRED_REFRESH_ENf); 4059 if (wred_refresh) { 4060 soc_reg_field_set(unit, 4061 FUNCTIONAL_REFRESH_ENr, ®_val, 4062 WRED_REFRESH_ENf, 0); 4063 rv = soc_reg32_set(unit, 4064 FUNCTIONAL_REFRESH_ENr, port, 0, 4065 reg_val); 4066 if (rv != SOC_E_NONE) { 4067 LOG_CLI((BSL_META_U( 4068 unit, 4069 "Error of disabling WRED " 4070 "refresh function Aborting.\n"))); 4071 soc_ser_test_long_sleep = FALSE; 4072 return rv; 4073 } 4074 } 4075 } 4076 soc_ser_create_test_data(unit, tmp_entry, 4077 fieldData, 4078 parity_enable_reg, 4079 SOC_INVALID_TCAM_PARITY_BIT, 4080 hw_parity_field, 4081 mem, EVEN_PARITYf, block_info_idx, 4082 port, _SOC_ACC_TYPE_PIPE_ANY, 4083 0, &test_data); 4084 if ((memTable == MMU_WRED_AVG_QSIZEm) || 4085 (memTable == MMU_WRED_MARK_THDm)) { 4086 /* restore WRED refresh configuration */ 4087 if (wred_refresh) { 4088 soc_reg_field_set(unit, 4089 FUNCTIONAL_REFRESH_ENr, ®_val, 4090 WRED_REFRESH_ENf, 1); 4091 rv = soc_reg32_set(unit, 4092 FUNCTIONAL_REFRESH_ENr, port, 0, 4093 reg_val); 4094 if (rv != SOC_E_NONE) { 4095 LOG_CLI((BSL_META_U( 4096 unit, 4097 "Error of enabling WRED " 4098 "refresh function Aborting.\n"))); 4099 soc_ser_test_long_sleep = FALSE; 4100 return rv; 4101 } 4102 } 4103 } 4104 if (cmd) { 4105 ser_test_cmd_generate(unit, &test_data); 4106 } else { 4107 rv = ser_test_mem(unit, 0, &test_data, 4108 test_type, &testErrors); 4109 } 4110 if (rv != SOC_E_NONE) { 4111 LOG_CLI((BSL_META_U(unit, 4112 "Error during H/W test. Aborting.\n"))); 4113 soc_ser_test_long_sleep = FALSE; 4114 return rv; 4115 } 4116 break; 4117 } 4118 } 4119 if (found_mem) { 4120 break; 4121 } 4122 } 4123 4124 } 4125 if (!found_mem) { 4126 LOG_CLI((BSL_META_U(unit, 4127 "SER Test is unavaible on unit: %d for memory %s\n"), unit, 4128 SOC_MEM_NAME(unit,mem))); 4129 return SOC_E_UNAVAIL; 4130 } 4131 4132 if (testErrors == 0) { 4133 LOG_CLI((BSL_META_U(unit, 4134 "SER Test passed on unit: %d for memory %s\n"), unit, 4135 SOC_MEM_NAME(unit,mem))); 4136 } 4137 else { 4138 LOG_CLI((BSL_META_U(unit, 4139 "SER Test failed on unit: %d for memory %s\n"), unit, 4140 SOC_MEM_NAME(unit,mem))); 4141 soc_ser_test_long_sleep = FALSE; 4142 return SOC_E_MEMORY; 4143 } 4144 /* restore to default */ 4145 soc_ser_test_long_sleep = FALSE; 4146 return SOC_E_NONE; 4147 4148 } 4149 4150 /* 4151 * Function: 4152 * soc_hr3_ser_test 4153 * Purpose: 4154 * Performs a SER test on all Memories 4155 * Parameters: 4156 * unit - (IN) Device Number 4157 * test_type - (IN) Determines how comprehensive of a test to run 4158 */ 4159 int soc_hr3_ser_test(int unit, _soc_ser_test_t test_type) 4160 { 4161 _soc_generic_ser_info_t *tcam_ser_info = _soc_hr3_tcam_ser_info[unit]; 4162 int numTCAMErr = 0; 4163 int numHwMemErr = 0; 4164 soc_reg_t parity_enable_reg = INVALIDr; 4165 soc_field_t hw_parity_field = INVALIDf, testfield; 4166 int port = REG_PORT_ANY; 4167 uint8 rbi; 4168 const _soc_hr3_ser_route_block_t *rb; 4169 uint32 cmic_bit, reg_val; 4170 int block_info_idx; 4171 int rv = SOC_E_NONE; 4172 _soc_hr3_ser_info_t *info_list, *info; 4173 int info_index; 4174 soc_mem_t memTable = INVALIDm; 4175 uint32 wred_refresh = 0; 4176 4177 if (!SAL_BOOT_QUICKTURN) { 4178 soc_ser_test_long_sleep = TRUE; 4179 soc_ser_test_long_sleep_time_us = 500000; 4180 } 4181 4182 if (tcam_ser_info != NULL) { 4183 int i; 4184 /*TCAM_test*/ 4185 for (i = 0; tcam_ser_info[i].mem != INVALIDm; i++) { 4186 rv = ser_test_mem_pipe(unit, SER_RANGE_ENABLEr, i, -1, 4187 tcam_ser_info[i].mem, VALIDf, test_type, 4188 MEM_BLOCK_ANY, REG_PORT_ANY, 4189 _SOC_ACC_TYPE_PIPE_ANY, &numTCAMErr); 4190 if (rv != SOC_E_NONE) { 4191 LOG_CLI((BSL_META_U(unit, 4192 "TR 144 test failed. " 4193 "Error during TCAM test. Aborting.\n"))); 4194 soc_ser_test_long_sleep = FALSE; 4195 return rv; 4196 } 4197 } 4198 } 4199 4200 for (rbi = 0; ; rbi++) { 4201 rb = &_soc_hr3_ser_route_blocks[unit][rbi]; 4202 cmic_bit = rb->cmic_bit; 4203 parity_enable_reg = INVALIDr; 4204 hw_parity_field = INVALIDf; 4205 if (cmic_bit == 0) { 4206 /* End of table */ 4207 break; 4208 } 4209 SOC_BLOCK_ITER(unit, block_info_idx, rb->blocktype) { 4210 if (SOC_BLOCK_INFO(unit, block_info_idx).number == rb->id) { 4211 port = SOC_BLOCK_PORT(unit, block_info_idx); 4212 break; 4213 } 4214 } 4215 info_list = rb->info; 4216 4217 if (info_list[0].type == _SOC_PARITY_TYPE_MMU_SER) { 4218 parity_enable_reg = info_list[0].enable_reg; 4219 hw_parity_field = info_list[0].enable_field; 4220 info_list = info_list[0].info; 4221 } 4222 for (info_index = 0; ; info_index++) { 4223 info = &info_list[info_index]; 4224 if (info->type == _SOC_PARITY_TYPE_NONE) { 4225 /* End of table */ 4226 break; 4227 } 4228 if (_soc_hr3_ser_mem_skip(unit, info)) { 4229 continue; 4230 } 4231 memTable = info->mem; 4232 if (memTable == INVALIDm){ 4233 continue; 4234 } 4235 if (parity_enable_reg == INVALIDr) { 4236 parity_enable_reg = info->enable_reg; 4237 } 4238 if (hw_parity_field == INVALIDf) { 4239 hw_parity_field = info->enable_field; 4240 } 4241 testfield = INVALIDf; 4242 if ((memTable == MMU_WRED_AVG_QSIZEm) || 4243 (memTable == MMU_WRED_MARK_THDm)) { 4244 rv = soc_reg32_get(unit, 4245 FUNCTIONAL_REFRESH_ENr, port, 0, 4246 ®_val); 4247 if (rv != SOC_E_NONE) { 4248 LOG_CLI((BSL_META_U(unit, 4249 "Error of getting WRED " 4250 "refresh function Aborting.\n"))); 4251 soc_ser_test_long_sleep = FALSE; 4252 return rv; 4253 } 4254 wred_refresh = soc_reg_field_get( 4255 unit, FUNCTIONAL_REFRESH_ENr, 4256 reg_val, WRED_REFRESH_ENf); 4257 if (wred_refresh) { 4258 soc_reg_field_set(unit, 4259 FUNCTIONAL_REFRESH_ENr, ®_val, 4260 WRED_REFRESH_ENf, 0); 4261 rv = soc_reg32_set(unit, 4262 FUNCTIONAL_REFRESH_ENr, port, 0, 4263 reg_val); 4264 if (rv != SOC_E_NONE) { 4265 LOG_CLI((BSL_META_U( 4266 unit, 4267 "Error of disabling WRED " 4268 "refresh function Aborting.\n"))); 4269 soc_ser_test_long_sleep = FALSE; 4270 return rv; 4271 } 4272 } 4273 } 4274 rv = ser_test_mem_pipe(unit, parity_enable_reg, -1, 4275 hw_parity_field, 4276 memTable, testfield, test_type, 4277 block_info_idx, port, 4278 _SOC_ACC_TYPE_PIPE_ANY, &numHwMemErr); 4279 4280 if ((memTable == MMU_WRED_AVG_QSIZEm) || 4281 (memTable == MMU_WRED_MARK_THDm)) { 4282 /* restore WRED refresh configuration */ 4283 if (wred_refresh) { 4284 soc_reg_field_set(unit, 4285 FUNCTIONAL_REFRESH_ENr, ®_val, 4286 WRED_REFRESH_ENf, 1); 4287 rv = soc_reg32_set(unit, 4288 FUNCTIONAL_REFRESH_ENr, port, 0, 4289 reg_val); 4290 if (rv != SOC_E_NONE) { 4291 LOG_CLI((BSL_META_U( 4292 unit, 4293 "Error of enabling WRED " 4294 "refresh function Aborting.\n"))); 4295 soc_ser_test_long_sleep = FALSE; 4296 return rv; 4297 } 4298 } 4299 } 4300 4301 if (rv != SOC_E_NONE) { 4302 LOG_CLI((BSL_META_U(unit, 4303 "TR 144 test failed. " 4304 "Error during H/W test. Aborting.\n"))); 4305 soc_ser_test_long_sleep = FALSE; 4306 return rv; 4307 } 4308 if (rb->blocktype != SOC_BLK_MMU) { 4309 parity_enable_reg = INVALIDr; 4310 hw_parity_field = INVALIDf; 4311 } 4312 } 4313 } 4314 4315 if ((numTCAMErr != 0) || (numHwMemErr != 0)) { 4316 LOG_CLI((BSL_META_U(unit, 4317 "TR 144 test failed.\n"))); 4318 } 4319 4320 LOG_CLI((BSL_META_U( 4321 unit, "Total TCAM errors on unit %d: %d\n"), unit, numTCAMErr)); 4322 LOG_CLI((BSL_META_U( 4323 unit, "Total H/W parity errors on unit %d: %d\n"),unit, numHwMemErr)); 4324 soc_ser_test_long_sleep = FALSE; 4325 return SOC_E_NONE; 4326 } 4327 4328 void 4329 soc_hr3_ser_test_register(int unit) 4330 { 4331 /*Initialize chip-specific functions for SER testing*/ 4332 memset(&ser_hr3_test_fun, 0, sizeof(soc_ser_test_functions_t)); 4333 ser_hr3_test_fun.inject_error_f = &soc_hr3_ser_inject_error; 4334 ser_hr3_test_fun.test_mem = &soc_hr3_ser_test_mem; 4335 ser_hr3_test_fun.test = &soc_hr3_ser_test; 4336 ser_hr3_test_fun.injection_support = &_ser_hr3_ser_error_injection_support; 4337 4338 soc_ser_test_functions_register(unit, &ser_hr3_test_fun); 4339 } 4340 #endif /* SER_TR_TEST_SUPPORT */