hurricane3.c (261834B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: hurricane3.c 8 * Purpose: 9 * Requires: 10 */ 11 12 13 #include <sal/core/boot.h> 14 15 #include <soc/firebolt.h> 16 #include <soc/bradley.h> 17 #include <soc/greyhound.h> 18 #include <soc/hurricane3.h> 19 #include <soc/wolfhound2.h> 20 #include <soc/drv.h> 21 #include <soc/mem.h> 22 #include <soc/hash.h> 23 #include <soc/lpm.h> 24 #include <soc/error.h> 25 #include <soc/debug.h> 26 #include <soc/er_tcam.h> 27 #include <soc/memtune.h> 28 #include <soc/devids.h> 29 #include <soc/defs.h> 30 #include <soc/l2x.h> 31 #include <soc/mspi.h> 32 33 #include <shared/util.h> 34 #include <shared/l3.h> 35 #include <shared/bsl.h> 36 37 #include <soc/esw/portctrl.h> 38 39 #ifdef BCM_HURRICANE3_SUPPORT 40 41 #define SOC_MAX_PHY_PORTS 42 42 43 /* Port config related : p2l, max_speed and TDM */ 44 45 /* 56160 : option 1 46 * 24P 1G + 4P (1G/10G) + 2P (1G/10G) PHY 47 */ 48 static const int p2l_mapping_56160_op1[] = { 49 0, -1, 2, 3, 4, 5, -1, -1, 50 -1, -1, 6, 7, 8, 9, 10, 11, 51 12, 13, 14, 15, 16, 17, -1, -1, 52 -1, -1, 18, 19, 20, 21, 22, 23, 53 24, 25, 26, 27, 28, 29, 30, 31, 54 -1, -1 55 }; 56 static const int port_speed_max_56160_op1[] = { 57 -1, -1, 10, 10, 10, 10, -1, -1, 58 -1, -1, 10, 10, 10, 10, 10, 10, 59 10, 10, 10, 10, 10, 10, -1, -1, 60 -1, -1, 10, 10, 10, 10, 10, 10, 61 10, 10, 110, 110, 110, 110, 110, 110, 62 -1, -1 63 }; 64 65 /* 56160 : option 1A 66 * 24P 1G + 4P (1G/10G) + 2P (1G/10G) PHY 67 */ 68 69 static const int p2l_mapping_56160_op1a[] = { 70 0, -1, 2, 3, 4, 5, -1, -1, 71 -1, -1, 6, 7, 8, 9, 10, 11, 72 12, 13, 14, 15, 16, 17, -1, -1, 73 -1, -1, 18, 19, 20, 21, 22, 23, 74 24, 25, 26, 27, -1, -1, 28, 29, 75 30, 31 76 }; 77 static const int port_speed_max_56160_op1a[] = { 78 -1, -1, 10, 10, 10, 10, -1, -1, 79 -1, -1, 10, 10, 10, 10, 10, 10, 80 10, 10, 10, 10, 10, 10, -1, -1, 81 -1, -1, 10, 10, 10, 10, 10, 10, 82 10, 10, 110, 110, -1, -1, 110, 110, 83 110, 110 84 }; 85 86 /* 56160 : option 2 87 * 24P 1G + 2P (1G/10G) + 2P (1G/10G) + 2P 25G 88 */ 89 static const int p2l_mapping_56160_op2[] = { 90 0, -1, 2, 3, 4, 5, -1, -1, 91 -1, -1, 6, 7, 8, 9, 10, 11, 92 12, 13, 14, 15, 16, 17, -1, -1, 93 -1, -1, 18, 19, 20, 21, 22, 23, 94 24, 25, 26, 27, 28, 29, 30, -1, 95 31, -1 96 }; 97 static const int port_speed_max_56160_op2[] = { 98 -1, -1, 10, 10, 10, 10, -1, -1, 99 -1, -1, 10, 10, 10, 10, 10, 10, 100 10, 10, 10, 10, 10, 10, -1, -1, 101 -1, -1, 10, 10, 10, 10, 10, 10, 102 10, 10, 110, 110, 110, 110, 250, -1, 103 250, -1 104 }; 105 106 /* 56160 : option 2A 107 * 24P 1G + 2P (1G/10G) + 2P (1G/10G) + 2P 25G 108 */ 109 static const int p2l_mapping_56160_op2a[] = { 110 0, -1, 2, 3, 4, 5, -1, -1, 111 -1, -1, 6, 7, 8, 9, 10, 11, 112 12, 13, 14, 15, 16, 17, -1, -1, 113 -1, -1, 18, 19, 20, 21, 22, 23, 114 24, 25, 26, -1, 27, -1, 28, 29, 115 30, 31 116 }; 117 static const int port_speed_max_56160_op2a[] = { 118 -1, -1, 10, 10, 10, 10, -1, -1, 119 -1, -1, 10, 10, 10, 10, 10, 10, 120 10, 10, 10, 10, 10, 10, -1, -1, 121 -1, -1, 10, 10, 10, 10, 10, 10, 122 10, 10, 250, -1, 250, -1, 110, 110, 123 110, 110 124 }; 125 126 /* 56160 : option 3 127 * 24P 1G +4P 1G/10G+1P XAUI 128 */ 129 static const int p2l_mapping_56160_op3[] = { 130 0, -1, 2, 3, 4, 5, -1, -1, 131 -1, -1, 6, 7, 8, 9, 10, 11, 132 12, 13, 14, 15, 16, 17, -1, -1, 133 -1, -1, 18, 19, 20, 21, 22, 23, 134 24, 25, 26, 27, 28, 29, 30, -1, 135 -1, -1 136 }; 137 static const int port_speed_max_56160_op3[] = { 138 -1, -1, 10, 10, 10, 10, -1, -1, 139 -1, -1, 10, 10, 10, 10, 10, 10, 140 10, 10, 10, 10, 10, 10, -1, -1, 141 -1, -1, 10, 10, 10, 10, 10, 10, 142 10, 10, 110, 110, 110, 110, 100, -1, 143 -1, -1 144 }; 145 146 /* 56160 : option 4 147 * 24P 1G +2P XAUI 148 */ 149 static const int p2l_mapping_56160_op4[] = { 150 0, -1, 2, 3, 4, 5, -1, -1, 151 -1, -1, 6, 7, 8, 9, 10, 11, 152 12, 13, 14, 15, 16, 17, -1, -1, 153 -1, -1, 18, 19, 20, 21, 22, 23, 154 24, 25, 26, -1, -1, -1, 27, -1, 155 -1, -1 156 }; 157 static const int port_speed_max_56160_op4[] = { 158 -1, -1, 10, 10, 10, 10, -1, -1, 159 -1, -1, 10, 10, 10, 10, 10, 10, 160 10, 10, 10, 10, 10, 10, -1, -1, 161 -1, -1, 10, 10, 10, 10, 10, 10, 162 10, 10, 100, -1, -1, -1, 100, -1, 163 -1, -1 164 }; 165 166 167 /* 56160 : option 5 168 * 24P 1G + 4P 1G/10G + 2P 20G 169 */ 170 static const int p2l_mapping_56160_op5[] = { 171 0, -1, 2, 3, 4, 5, -1, -1, 172 -1, -1, 6, 7, 8, 9, 10, 11, 173 12, 13, 14, 15, 16, 17, -1, -1, 174 -1, -1, 18, 19, 20, 21, 22, 23, 175 24, 25, 26, 27, 28, -1, 29, 30, 176 31, -1 177 }; 178 static const int port_speed_max_56160_op5[] = { 179 -1, -1, 10, 10, 10, 10, -1, -1, 180 -1, -1, 10, 10, 10, 10, 10, 10, 181 10, 10, 10, 10, 10, 10, -1, -1, 182 -1, -1, 10, 10, 10, 10, 10, 10, 183 10, 10, 110, 110, 210, -1, 110, 110, 184 210, -1 185 }; 186 187 /* 56160 : option 6 188 * 24P 1G +2P 1G/10G + 2P 20G + 2P 25G 189 */ 190 static const int p2l_mapping_56160_op6[] = { 191 0, -1, 2, 3, 4, 5, -1, -1, 192 -1, -1, 6, 7, 8, 9, 10, 11, 193 12, 13, 14, 15, 16, 17, -1, -1, 194 -1, -1, 18, 19, 20, 21, 22, 23, 195 24, 25, 26, 27, 28, -1, 29, -1, 196 30, -1 197 }; 198 static const int port_speed_max_56160_op6[] = { 199 -1, -1, 10, 10, 10, 10, -1, -1, 200 -1, -1, 10, 10, 10, 10, 10, 10, 201 10, 10, 10, 10, 10, 10, -1, -1, 202 -1, -1, 10, 10, 10, 10, 10, 10, 203 10, 10, 110, 110, 210, -1, 250, -1, 204 250, -1 205 }; 206 207 /* 56160 : option 6A 208 * 24P 1G +2P 1G/10G + 2P 20G + 2P 25G 209 */ 210 static const int p2l_mapping_56160_op6a[] = { 211 0, -1, 2, 3, 4, 5, -1, -1, 212 -1, -1, 6, 7, 8, 9, 10, 11, 213 12, 13, 14, 15, 16, 17, -1, -1, 214 -1, -1, 18, 19, 20, 21, 22, 23, 215 24, 25, 26, -1, 27, -1, 28, 29, 216 30, -1 217 }; 218 static const int port_speed_max_56160_op6a[] = { 219 -1, -1, 10, 10, 10, 10, -1, -1, 220 -1, -1, 10, 10, 10, 10, 10, 10, 221 10, 10, 10, 10, 10, 10, -1, -1, 222 -1, -1, 10, 10, 10, 10, 10, 10, 223 10, 10, 250, -1, 250, -1, 110, 110, 224 210, -1 225 }; 226 227 228 /* 56160 : option 7 229 * 24P 1G +2P 40G 230 */ 231 static const int p2l_mapping_56160_op7[] = { 232 0, -1, 2, 3, 4, 5, -1, -1, 233 -1, -1, 6, 7, 8, 9, 10, 11, 234 12, 13, 14, 15, 16, 17, -1, -1, 235 -1, -1, 18, 19, 20, 21, 22, 23, 236 24, 25, 26, -1, -1, -1, 27, -1, 237 -1, -1 238 }; 239 static const int port_speed_max_56160_op7[] = { 240 -1, -1, 10, 10, 10, 10, -1, -1, 241 -1, -1, 10, 10, 10, 10, 10, 10, 242 10, 10, 10, 10, 10, 10, -1, -1, 243 -1, -1, 10, 10, 10, 10, 10, 10, 244 10, 10, 420, -1, -1, -1, 420, -1, 245 -1, -1 246 }; 247 248 /* 56160 : option 8 249 * 24P 1G +1P 40G + 2P 25G 250 */ 251 static const int p2l_mapping_56160_op8[] = { 252 0, -1, 2, 3, 4, 5, -1, -1, 253 -1, -1, 6, 7, 8, 9, 10, 11, 254 12, 13, 14, 15, 16, 17, -1, -1, 255 -1, -1, 18, 19, 20, 21, 22, 23, 256 24, 25, 26, -1, 27, -1, 28, -1, 257 -1, -1 258 }; 259 static const int port_speed_max_56160_op8[] = { 260 -1, -1, 10, 10, 10, 10, -1, -1, 261 -1, -1, 10, 10, 10, 10, 10, 10, 262 10, 10, 10, 10, 10, 10, -1, -1, 263 -1, -1, 10, 10, 10, 10, 10, 10, 264 10, 10, 250, -1, 250, -1, 420, -1, 265 -1, -1 266 }; 267 268 269 /* 56160 : option 8A 270 * 24P 1G +1P 40G + 2P 25G 271 */ 272 static const int p2l_mapping_56160_op8a[] = { 273 0, -1, 2, 3, 4, 5, -1, -1, 274 -1, -1, 6, 7, 8, 9, 10, 11, 275 12, 13, 14, 15, 16, 17, -1, -1, 276 -1, -1, 18, 19, 20, 21, 22, 23, 277 24, 25, 26, -1, -1, -1, 27, -1, 278 28, -1 279 }; 280 static const int port_speed_max_56160_op8a[] = { 281 -1, -1, 10, 10, 10, 10, -1, -1, 282 -1, -1, 10, 10, 10, 10, 10, 10, 283 10, 10, 10, 10, 10, 10, -1, -1, 284 -1, -1, 10, 10, 10, 10, 10, 10, 285 10, 10, 420, -1, -1, -1, 250, -1, 286 250, -1 287 }; 288 289 /* 56160 : option 9 290 * 24P 1G + 2P 20G + 2P 25G 291 */ 292 static const int p2l_mapping_56160_op9[] = { 293 0, -1, 2, 3, 4, 5, -1, -1, 294 -1, -1, 6, 7, 8, 9, 10, 11, 295 12, 13, 14, 15, 16, 17, -1, -1, 296 -1, -1, 18, 19, 20, 21, 22, 23, 297 24, 25, 26, -1, 27, -1, 28, -1, 298 29, -1 299 }; 300 static const int port_speed_max_56160_op9[] = { 301 -1, -1, 10, 10, 10, 10, -1, -1, 302 -1, -1, 10, 10, 10, 10, 10, 10, 303 10, 10, 10, 10, 10, 10, -1, -1, 304 -1, -1, 10, 10, 10, 10, 10, 10, 305 10, 10, 210, -1, 210, -1, 250, -1, 306 250, -1 307 }; 308 309 /* 56160 : option 9A 310 * 24P 1G + 2P 20G + 2P 25G 311 */ 312 static const int p2l_mapping_56160_op9a[] = { 313 0, -1, 2, 3, 4, 5, -1, -1, 314 -1, -1, 6, 7, 8, 9, 10, 11, 315 12, 13, 14, 15, 16, 17, -1, -1, 316 -1, -1, 18, 19, 20, 21, 22, 23, 317 24, 25, 26, -1, 27, -1, 28, -1, 318 29, -1 319 }; 320 static const int port_speed_max_56160_op9a[] = { 321 -1, -1, 10, 10, 10, 10, -1, -1, 322 -1, -1, 10, 10, 10, 10, 10, 10, 323 10, 10, 10, 10, 10, 10, -1, -1, 324 -1, -1, 10, 10, 10, 10, 10, 10, 325 10, 10, 250, -1, 250, -1, 210, -1, 326 210, -1 327 }; 328 329 /* 56160 : option 1 gphy bypass 330 * 24P 1G +4P 1G/10G +2P 1G/10G 331 */ 332 static const int p2l_mapping_56160_op1_gphy_bypass[] = { 333 0, -1, 2, 3, 4, 5, 6, 7, 334 8, 9, -1, -1, -1, -1, -1, -1, 335 -1, -1, 10, 11, 12, 13, 14, 15, 336 16, 17, 18, 19, 20, 21, 22, 23, 337 24, 25, 26, 27, 28, 29, 30, 31, 338 -1, -1 339 }; 340 static const int port_speed_max_56160_op1_gphy_bypass[] = { 341 -1, -1, 10, 10, 10, 10, 10, 10, 342 10, 10, -1, -1, -1, -1, -1, -1, 343 -1, -1, 10, 10, 10, 10, 10, 10, 344 10, 10, 10, 10, 10, 10, 10, 10, 345 10, 10, 110, 110, 110, 110, 110, 110, 346 -1, -1 347 }; 348 349 /* 56160 : option 1A gphy bypass 350 * 24P 1G +4P 1G/10G +2P 1G/10G 351 */ 352 static const int p2l_mapping_56160_op1a_gphy_bypass[] = { 353 0, -1, 2, 3, 4, 5, 6, 7, 354 8, 9, -1, -1, -1, -1, -1, -1, 355 -1, -1, 10, 11, 12, 13, 14, 15, 356 16, 17, 18, 19, 20, 21, 22, 23, 357 24, 25, 26, 27, -1, -1, 28, 29, 358 30, 31 359 }; 360 static const int port_speed_max_56160_op1a_gphy_bypass[] = { 361 -1, -1, 10, 10, 10, 10, 10, 10, 362 10, 10, -1, -1, -1, -1, -1, -1, 363 -1, -1, 10, 10, 10, 10, 10, 10, 364 10, 10, 10, 10, 10, 10, 10, 10, 365 10, 10, 110, 110, -1, -1, 110, 110, 366 110, 110 367 }; 368 369 /* 56160 : option 2 gphy bypass 370 * 24P 1G + 2P 1G/10G + 2P 1G/10G + 2P 25G 371 */ 372 static const int p2l_mapping_56160_op2_gphy_bypass[] = { 373 0, -1, 2, 3, 4, 5, 6, 7, 374 8, 9, -1, -1, -1, -1, -1, -1, 375 -1, -1, 10, 11, 12, 13, 14, 15, 376 16, 17, 18, 19, 20, 21, 22, 23, 377 24, 25, 26, 27, 28, 29, 30, -1, 378 31, -1 379 }; 380 static const int port_speed_max_56160_op2_gphy_bypass[] = { 381 -1, -1, 10, 10, 10, 10, 10, 10, 382 10, 10, -1, -1, -1, -1, -1, -1, 383 -1, -1, 10, 10, 10, 10, 10, 10, 384 10, 10, 10, 10, 10, 10, 10, 10, 385 10, 10, 110, 110, 110, 110, 250, -1, 386 250, -1 387 }; 388 389 /* 56160 : option 2A gphy bypass 390 * 24P 1G + 2P 1G/10G + 2P 1G/10G + 2P 25G 391 */ 392 static const int p2l_mapping_56160_op2a_gphy_bypass[] = { 393 0, -1, 2, 3, 4, 5, 6, 7, 394 8, 9, -1, -1, -1, -1, -1, -1, 395 -1, -1, 10, 11, 12, 13, 14, 15, 396 16, 17, 18, 19, 20, 21, 22, 23, 397 24, 25, 26, -1, 27, -1, 28, 29, 398 30, 31 399 }; 400 static const int port_speed_max_56160_op2a_gphy_bypass[] = { 401 -1, -1, 10, 10, 10, 10, 10, 10, 402 10, 10, -1, -1, -1, -1, -1, -1, 403 -1, -1, 10, 10, 10, 10, 10, 10, 404 10, 10, 10, 10, 10, 10, 10, 10, 405 10, 10, 250, -1, 250, -1, 110, 110, 406 110, 110 407 }; 408 409 /* 56160 : option 3 gphy bypass 410 * 24P 1G +4P 1G/10G+1P XAUI 411 */ 412 static const int p2l_mapping_56160_op3_gphy_bypass[] = { 413 0, -1, 2, 3, 4, 5, 6, 7, 414 8, 9, -1, -1, -1, -1, -1, -1, 415 -1, -1, 10, 11, 12, 13, 14, 15, 416 16, 17, 18, 19, 20, 21, 22, 23, 417 24, 25, 26, 27, 28, 29, 30, -1, 418 -1, -1 419 }; 420 static const int port_speed_max_56160_op3_gphy_bypass[] = { 421 -1, -1, 10, 10, 10, 10, 10, 10, 422 10, 10, -1, -1, -1, -1, -1, -1, 423 -1, -1, 10, 10, 10, 10, 10, 10, 424 10, 10, 10, 10, 10, 10, 10, 10, 425 10, 10, 110, 110, 110, 110, 100, -1, 426 -1, -1 427 }; 428 429 /* 56160 : option 4 gphy bypass 430 * 24P 1G +2P XAUI 431 */ 432 static const int p2l_mapping_56160_op4_gphy_bypass[] = { 433 0, -1, 2, 3, 4, 5, 6, 7, 434 8, 9, -1, -1, -1, -1, -1, -1, 435 -1, -1, 10, 11, 12, 13, 14, 15, 436 16, 17, 18, 19, 20, 21, 22, 23, 437 24, 25, 26, -1, -1, -1, 27, -1, 438 -1, -1 439 }; 440 static const int port_speed_max_56160_op4_gphy_bypass[] = { 441 -1, -1, 10, 10, 10, 10, 10, 10, 442 10, 10, -1, -1, -1, -1, -1, -1, 443 -1, -1, 10, 10, 10, 10, 10, 10, 444 10, 10, 10, 10, 10, 10, 10, 10, 445 10, 10, 100, -1, -1, -1, 100, -1, 446 -1, -1 447 }; 448 449 450 /* 56160 : option 5 gphy bypass 451 * 24P 1G + 4P 1G/10G + 2P 20G 452 */ 453 static const int p2l_mapping_56160_op5_gphy_bypass[] = { 454 0, -1, 2, 3, 4, 5, 6, 7, 455 8, 9, -1, -1, -1, -1, -1, -1, 456 -1, -1, 10, 11, 12, 13, 14, 15, 457 16, 17, 18, 19, 20, 21, 22, 23, 458 24, 25, 26, 27, 28, -1, 29, 30, 459 31, -1 460 }; 461 static const int port_speed_max_56160_op5_gphy_bypass[] = { 462 -1, -1, 10, 10, 10, 10, 10, 10, 463 10, 10, -1, -1, -1, -1, -1, -1, 464 -1, -1, 10, 10, 10, 10, 10, 10, 465 10, 10, 10, 10, 10, 10, 10, 10, 466 10, 10, 110, 110, 210, -1, 110, 110, 467 210, -1 468 }; 469 470 /* 56160 : option 6 gphy bypass 471 * 24P 1G +2P 1G/10G + 1P 20G + 2P 25G 472 */ 473 static const int p2l_mapping_56160_op6_gphy_bypass[] = { 474 0, -1, 2, 3, 4, 5, 6, 7, 475 8, 9, -1, -1, -1, -1, -1, -1, 476 -1, -1, 10, 11, 12, 13, 14, 15, 477 16, 17, 18, 19, 20, 21, 22, 23, 478 24, 25, 26, 27, 28, -1, 29, -1, 479 30, -1 480 }; 481 static const int port_speed_max_56160_op6_gphy_bypass[] = { 482 -1, -1, 10, 10, 10, 10, 10, 10, 483 10, 10, -1, -1, -1, -1, -1, -1, 484 -1, -1, 10, 10, 10, 10, 10, 10, 485 10, 10, 10, 10, 10, 10, 10, 10, 486 10, 10, 110, 110, 210, -1, 250, -1, 487 250, -1 488 }; 489 490 /* 56160 : option 6A gphy bypass 491 * 24P 1G +2P 1G/10G + 1P 20G + 2P 25G 492 */ 493 static const int p2l_mapping_56160_op6a_gphy_bypass[] = { 494 0, -1, 2, 3, 4, 5, 6, 7, 495 8, 9, -1, -1, -1, -1, -1, -1, 496 -1, -1, 10, 11, 12, 13, 14, 15, 497 16, 17, 18, 19, 20, 21, 22, 23, 498 24, 25, 26, -1, 27, -1, 28, 29, 499 30, -1 500 }; 501 static const int port_speed_max_56160_op6a_gphy_bypass[] = { 502 -1, -1, 10, 10, 10, 10, 10, 10, 503 10, 10, -1, -1, -1, -1, -1, -1, 504 -1, -1, 10, 10, 10, 10, 10, 10, 505 10, 10, 10, 10, 10, 10, 10, 10, 506 10, 10, 250, -1, 250, -1, 110, 110, 507 210, -1 508 }; 509 510 /* 56160 : option 7 gphy bypass 511 * 24P 1G +2P 40G 512 */ 513 static const int p2l_mapping_56160_op7_gphy_bypass[] = { 514 0, -1, 2, 3, 4, 5, 6, 7, 515 8, 9, -1, -1, -1, -1, -1, -1, 516 -1, -1, 10, 11, 12, 13, 14, 15, 517 16, 17, 18, 19, 20, 21, 22, 23, 518 24, 25, 26, -1, -1, -1, 27, -1, 519 -1, -1 520 }; 521 static const int port_speed_max_56160_op7_gphy_bypass[] = { 522 -1, -1, 10, 10, 10, 10, 10, 10, 523 10, 10, -1, -1, -1, -1, -1, -1, 524 -1, -1, 10, 10, 10, 10, 10, 10, 525 10, 10, 10, 10, 10, 10, 10, 10, 526 10, 10, 420, -1, -1, -1, 420, -1, 527 -1, -1 528 }; 529 530 /* 56160 : option 8 gphy bypass 531 * 24P 1G +1P 40G + 2P 25G 532 */ 533 static const int p2l_mapping_56160_op8_gphy_bypass[] = { 534 0, -1, 2, 3, 4, 5, 6, 7, 535 8, 9, -1, -1, -1, -1, -1, -1, 536 -1, -1, 10, 11, 12, 13, 14, 15, 537 16, 17, 18, 19, 20, 21, 22, 23, 538 24, 25, 26, -1, 27, -1, 28, -1, 539 -1, -1 540 }; 541 static const int port_speed_max_56160_op8_gphy_bypass[] = { 542 -1, -1, 10, 10, 10, 10, 10, 10, 543 10, 10, -1, -1, -1, -1, -1, -1, 544 -1, -1, 10, 10, 10, 10, 10, 10, 545 10, 10, 10, 10, 10, 10, 10, 10, 546 10, 10, 250, -1, 250, -1, 420, -1, 547 -1, -1 548 }; 549 550 /* 56160 : option 8A gphy bypass 551 * 24P 1G +1P 40G + 2P 25G 552 */ 553 static const int p2l_mapping_56160_op8a_gphy_bypass[] = { 554 0, -1, 2, 3, 4, 5, 6, 7, 555 8, 9, -1, -1, -1, -1, -1, -1, 556 -1, -1, 10, 11, 12, 13, 14, 15, 557 16, 17, 18, 19, 20, 21, 22, 23, 558 24, 25, 26, -1, -1, -1, 27, -1, 559 28, -1 560 }; 561 static const int port_speed_max_56160_op8a_gphy_bypass[] = { 562 -1, -1, 10, 10, 10, 10, 10, 10, 563 10, 10, -1, -1, -1, -1, -1, -1, 564 -1, -1, 10, 10, 10, 10, 10, 10, 565 10, 10, 10, 10, 10, 10, 10, 10, 566 10, 10, 420, -1, -1, -1, 250, -1, 567 250, -1 568 }; 569 570 /* 56160 : option 9 gphy bypass 571 * 24P 1G + 1P 20G + 2P 25G 572 */ 573 static const int p2l_mapping_56160_op9_gphy_bypass[] = { 574 0, -1, 2, 3, 4, 5, 6, 7, 575 8, 9, -1, -1, -1, -1, -1, -1, 576 -1, -1, 10, 11, 12, 13, 14, 15, 577 16, 17, 18, 19, 20, 21, 22, 23, 578 24, 25, 26, -1, 27, -1, 28, -1, 579 29, -1 580 }; 581 static const int port_speed_max_56160_op9_gphy_bypass[] = { 582 -1, -1, 10, 10, 10, 10, 10, 10, 583 10, 10, -1, -1, -1, -1, -1, -1, 584 -1, -1, 10, 10, 10, 10, 10, 10, 585 10, 10, 10, 10, 10, 10, 10, 10, 586 10, 10, 210, -1, 210, -1, 250, -1, 587 250, -1 588 }; 589 590 /* 56160 : option 9a gphy bypass 591 * 24P 1G + 1P 20G + 2P 25G 592 */ 593 static const int p2l_mapping_56160_op9a_gphy_bypass[] = { 594 0, -1, 2, 3, 4, 5, 6, 7, 595 8, 9, -1, -1, -1, -1, -1, -1, 596 -1, -1, 10, 11, 12, 13, 14, 15, 597 16, 17, 18, 19, 20, 21, 22, 23, 598 24, 25, 26, -1, 27, -1, 28, -1, 599 29, -1 600 }; 601 static const int port_speed_max_56160_op9a_gphy_bypass[] = { 602 -1, -1, 10, 10, 10, 10, 10, 10, 603 10, 10, -1, -1, -1, -1, -1, -1, 604 -1, -1, 10, 10, 10, 10, 10, 10, 605 10, 10, 10, 10, 10, 10, 10, 10, 606 10, 10, 250, -1, 250, -1, 210, -1, 607 210, -1 608 }; 609 610 /* 56162 : option 1 611 * 24P 1G +4P 1G 612 */ 613 static const int p2l_mapping_56162_op1[] = { 614 0, -1, -1, -1, -1, -1, -1, -1, 615 -1, -1, 2, 3, 4, 5, 6, 7, 616 8, 9, 10, 11, 12, 13, 14, 15, 617 16, 17, 18, 19, 20, 21, 22, 23, 618 24, 25, 26, 27, 28, 29, -1, -1, 619 -1, -1 620 }; 621 static const int port_speed_max_56162_op1[] = { 622 -1, -1, -1, -1, -1, -1, -1, -1, 623 -1, -1, 10, 10, 10, 10, 10, 10, 624 10, 10, 10, 10, 10, 10, 10, 10, 625 10, 10, 10, 10, 10, 10, 10, 10, 626 10, 10, 10, 10, 10, 10, -1, -1, 627 -1, -1 628 }; 629 630 /* 56162 : option 1A 631 * 24P 1G +4P 1G 632 */ 633 static const int p2l_mapping_56162_op1a[] = { 634 0, -1, -1, -1, -1, -1, -1, -1, 635 -1, -1, 2, 3, 4, 5, 6, 7, 636 8, 9, 10, 11, 12, 13, 14, 15, 637 16, 17, 18, 19, 20, 21, 22, 23, 638 24, 25, -1, -1, -1, -1, 26, 27, 639 28, 29 640 }; 641 static const int port_speed_max_56162_op1a[] = { 642 -1, -1, -1, -1, -1, -1, -1, -1, 643 -1, -1, 10, 10, 10, 10, 10, 10, 644 10, 10, 10, 10, 10, 10, 10, 10, 645 10, 10, 10, 10, 10, 10, 10, 10, 646 10, 10, -1, -1, -1, -1, 10, 10, 647 10, 10 648 }; 649 650 /* 56162 : option 2 651 * 24P 1G + 2P 1G + 2P 13G 652 */ 653 static const int p2l_mapping_56162_op2[] = { 654 0, -1, -1, -1, -1, -1, -1, -1, 655 -1, -1, 2, 3, 4, 5, 6, 7, 656 8, 9, 10, 11, 12, 13, 14, 15, 657 16, 17, 18, 19, 20, 21, 22, 23, 658 24, 25, 26, 27, -1, -1, 28, -1, 659 29, -1 660 }; 661 static const int port_speed_max_56162_op2[] = { 662 -1, -1, -1, -1, -1, -1, -1, -1, 663 -1, -1, 10, 10, 10, 10, 10, 10, 664 10, 10, 10, 10, 10, 10, 10, 10, 665 10, 10, 10, 10, 10, 10, 10, 10, 666 10, 10, 10, 10, -1, -1, 130, -1, 667 130, -1 668 }; 669 670 /* 56162 : option 1 gphy bypass 671 * 24P 1G +4P 1G 672 */ 673 static const int p2l_mapping_56162_op1_gphy_bypass[] = { 674 0, -1, 2, 3, 4, 5, 6, 7, 675 8, 9, -1, -1, -1, -1, -1, -1, 676 -1, -1, 10, 11, 12, 13, 14, 15, 677 16, 17, 18, 19, 20, 21, 22, 23, 678 24, 25, 26, 27, 28, 29, -1, -1, 679 -1, -1 680 }; 681 static const int port_speed_max_56162_op1_gphy_bypass[] = { 682 -1, -1, 10, 10, 10, 10, 10, 10, 683 10, 10, -1, -1, -1, -1, -1, -1, 684 -1, -1, 10, 10, 10, 10, 10, 10, 685 10, 10, 10, 10, 10, 10, 10, 10, 686 10, 10, 10, 10, 10, 10, -1, -1, 687 -1, -1 688 }; 689 690 /* 56162 : option 1A gphy bypass 691 * 24P 1G +4P 1G 692 */ 693 static const int p2l_mapping_56162_op1a_gphy_bypass[] = { 694 0, -1, 2, 3, 4, 5, 6, 7, 695 8, 9, -1, -1, -1, -1, -1, -1, 696 -1, -1, 10, 11, 12, 13, 14, 15, 697 16, 17, 18, 19, 20, 21, 22, 23, 698 24, 25, -1, -1, -1, -1, 26, 27, 699 28, 29 700 }; 701 static const int port_speed_max_56162_op1a_gphy_bypass[] = { 702 -1, -1, 10, 10, 10, 10, 10, 10, 703 10, 10, -1, -1, -1, -1, -1, -1, 704 -1, -1, 10, 10, 10, 10, 10, 10, 705 10, 10, 10, 10, 10, 10, 10, 10, 706 10, 10, -1, -1, -1, -1, 10, 10, 707 10, 10 708 }; 709 710 /* 56162 : option 2 gphy bypass 711 * 24P 1G + 2P 1G + 2P 13G 712 */ 713 static const int p2l_mapping_56162_op2_gphy_bypass[] = { 714 0, -1, 2, 3, 4, 5, 6, 7, 715 8, 9, -1, -1, -1, -1, -1, -1, 716 -1, -1, 10, 11, 12, 13, 14, 15, 717 16, 17, 18, 19, 20, 21, 22, 23, 718 24, 25, 26, 27, -1, -1, 28, -1, 719 29, -1 720 }; 721 static const int port_speed_max_56162_op2_gphy_bypass[] = { 722 -1, -1, 10, 10, 10, 10, 10, 10, 723 10, 10, -1, -1, -1, -1, -1, -1, 724 -1, -1, 10, 10, 10, 10, 10, 10, 725 10, 10, 10, 10, 10, 10, 10, 10, 726 10, 10, 10, 10, -1, -1, 130, -1, 727 130, -1 728 }; 729 730 /* Hurricane 3 Lite */ 731 732 /* 56163 : option 1 733 * 8P 1G (PHY) + 2P 1G/2.5G/5G/10G 734 */ 735 static const int p2l_mapping_56163_op1[] = { 736 0, -1, -1, -1, -1, -1, -1, -1, 737 -1, -1, 2, 3, 4, 5, 6, 7, 738 8, 9, -1, -1, -1, -1, -1, -1, 739 -1, -1, -1, -1, -1, -1, -1, -1, 740 -1, -1, 10, -1, -1, -1, 11, -1, 741 -1, -1 742 }; 743 static const int port_speed_max_56163_op1[] = { 744 -1, -1, -1, -1, -1, -1, -1, -1, 745 -1, -1, 10, 10, 10, 10, 10, 10, 746 10, 10, -1, -1, -1, -1, -1, -1, 747 -1, -1, -1, -1, -1, -1, -1, -1, 748 -1, -1, 110, -1, -1, -1, 110, -1, 749 -1, -1 750 }; 751 752 /* 56163 : option 2 753 * 8P 1G (PHY) + 4P 1G/2.5G OR 1P XAUI + 4P 1G/2.5G OR 1P XAUI 754 */ 755 static const int p2l_mapping_56163_op2[] = { 756 0, -1, -1, -1, -1, -1, -1, -1, 757 -1, -1, 2, 3, 4, 5, 6, 7, 758 8, 9, -1, -1, -1, -1, -1, -1, 759 -1, -1, -1, -1, -1, -1, -1, -1, 760 -1, -1, 10, 11, 12, 13, 14, 15, 761 16, 17 762 }; 763 static const int port_speed_max_56163_op2[] = { 764 -1, -1, -1, -1, -1, -1, -1, -1, 765 -1, -1, 10, 10, 10, 10, 10, 10, 766 10, 10, -1, -1, -1, -1, -1, -1, 767 -1, -1, -1, -1, -1, -1, -1, -1, 768 -1, -1, 25, 25, 25, 25, 25, 25, 769 25, 25 770 }; 771 772 /* 56163 : option 1 gphy bypass 773 * 8P 1G (PHY) + 2P 1G/2.5G/5G/10G 774 */ 775 static const int p2l_mapping_56163_op1_gphy_bypass[] = { 776 0, -1, 2, 3, 4, 5, -1, -1, 777 -1, -1, -1, -1, -1, -1, -1, -1, 778 -1, -1, 6, 7, 8, 9, -1, -1, 779 -1, -1, -1, -1, -1, -1, -1, -1, 780 -1, -1, 10, -1, -1, -1, 11, -1, 781 -1, -1 782 }; 783 static const int port_speed_max_56163_op1_gphy_bypass[] = { 784 -1, -1, 10, 10, 10, 10, -1, -1, 785 -1, -1, -1, -1, -1, -1, -1, -1, 786 -1, -1, 10, 10, 10, 10, -1, -1, 787 -1, -1, -1, -1, -1, -1, -1, -1, 788 -1, -1, 110, -1, -1, -1, 110, -1, 789 -1, -1 790 }; 791 792 /* 56163 : option 2 gphy bypass 793 * 8P 1G (PHY) + 4P 1G/2.5G OR 1P XAUI + 4P 1G/2.5G OR 1P XAUI 794 */ 795 static const int p2l_mapping_56163_op2_gphy_bypass[] = { 796 0, -1, 2, 3, 4, 5, -1, -1, 797 -1, -1, -1, -1, -1, -1, -1, -1, 798 -1, -1, 6, 7, 8, 9, -1, -1, 799 -1, -1, -1, -1, -1, -1, -1, -1, 800 -1, -1, 10, 11, 12, 13, 14, 15, 801 16, 17 802 }; 803 static const int port_speed_max_56163_op2_gphy_bypass[] = { 804 -1, -1, 10, 10, 10, 10, -1, -1, 805 -1, -1, -1, -1, -1, -1, -1, -1, 806 -1, -1, 10, 10, 10, 10, -1, -1, 807 -1, -1, -1, -1, -1, -1, -1, -1, 808 -1, -1, 25, 25, 25, 25, 25, 25, 809 25, 25 810 }; 811 812 813 /* 56164 814 * 24P 1G (PHY) + 4P 1G 815 */ 816 /* same as 56162 option 1 */ 817 818 819 /* Buckhound */ 820 821 /* 53440 : option 1 822 * 16P 1G + 8P 1G/2.5G + 4P 10G + 2P 20G 823 */ 824 /* same as 56160 option 5 */ 825 826 827 /* 53440 : option 2 828 * 16P 1G + 8P 1G/2.5G + 2P 10G (Uplink) + 1P 20G (stack) + 2P 25G 829 */ 830 /* same as 56160 option 6A */ 831 832 /* 53440 : option 2A 833 * 16P 1G + 8P 1G/2.5G + 2P 10G (Uplink) + 1P 20G (stack) + 2P 25G 834 */ 835 /* same as 56160 option 6 gphy bypass */ 836 837 /* 53440 : option 3 838 * 16P 1G + 8P 1G/2.5G + 4P 10G (Uplink) + 2P 10G (stack) 839 */ 840 static const int p2l_mapping_53440_op3[] = { 841 0, -1, 2, 3, 4, 5, -1, -1, 842 -1, -1, 6, 7, 8, 9, 10, 11, 843 12, 13, 14, 15, 16, 17, -1, -1, 844 -1, -1, 18, 19, 20, 21, 22, 23, 845 24, 25, 26, 27, 28, -1, 29, 30, 846 31, -1 847 }; 848 static const int port_speed_max_53440_op3[] = { 849 -1, -1, 10, 10, 10, 10, -1, -1, 850 -1, -1, 10, 10, 10, 10, 10, 10, 851 10, 10, 10, 10, 10, 10, -1, -1, 852 -1, -1, 10, 10, 10, 10, 10, 10, 853 10, 10, 110, 110, 110, -1, 110, 110, 854 110, -1 855 }; 856 857 /* 53440 : option 4 858 * 16P 1G + 8P 1G/2.5G + 2P 10G (Uplink) + 1P 10G (stack) + 2P 25G 859 */ 860 /* same as 56160 option 2A */ 861 static const int port_speed_max_53440_op4[] = { 862 -1, -1, 10, 10, 10, 10, -1, -1, 863 -1, -1, 10, 10, 10, 10, 10, 10, 864 10, 10, 10, 10, 10, 10, -1, -1, 865 -1, -1, 10, 10, 10, 10, 10, 10, 866 10, 10, 250, -1, 250, -1, 110, 110, 867 110, -1 868 }; 869 870 /* 53440 : option 4A 871 * 16P 1G + 8P 1G/2.5G + 2P 10G (Uplink) + 1P 10G (stack) + 2P 25G 872 */ 873 /* same as 56160 option 2 */ 874 static const int port_speed_max_53440_op4a[] = { 875 -1, -1, 10, 10, 10, 10, -1, -1, 876 -1, -1, 10, 10, 10, 10, 10, 10, 877 10, 10, 10, 10, 10, 10, -1, -1, 878 -1, -1, 10, 10, 10, 10, 10, 10, 879 10, 10, 110, 110, 110, -1, 250, -1, 880 250, -1 881 }; 882 883 /* 53440 : option 5 884 * 24P 1G + 4P 10G + 1P XAUI (Phy) 885 */ 886 /* same as 56160 option 3 */ 887 888 /* 53440 : option 6 889 * 24P 1G + 2P XAUI (Phy) 890 */ 891 /* same as 56160 option 4 */ 892 893 /* 53440 : option 7 894 * 16P 1G + 8x1G/2.5G + 2P 1G/10G + 4P 1G/10G (PHY) 895 */ 896 /* same as 56160 option 1 */ 897 898 /* 53440 : option 7A 899 * 16P 1G + 8x1G/2.5G + 2P 1G/10G + 4P 1G/10G (PHY) 900 */ 901 /* same as 56160 option 1A */ 902 903 /* 53440 : option 8 904 * 16P 1G + 8x1G/2.5G + 2P 1G/10G + 2P 1G/10G + 2P 25G (PHY) 905 */ 906 /* same as 56160 option 2 */ 907 908 /* 53440 : option 8A 909 * 16P 1G + 8x1G/2.5G + 2P 1G/10G 2P 1G/10G + 2P 25G (PHY) 910 */ 911 /* same as 56160 option 2A */ 912 913 /* 53440 : option 1 gphy bypass 914 * 16P 1G + 8P 1G/2.5G + 4P 10G + 2P 20G (Phy) 915 */ 916 /* same as 56160 option 5 gphy bypass */ 917 918 919 /* 53440 : option 2 gphy bypass 920 * 16P 1G + 8P 1G/2.5G + 2P 10G (Uplink) + 1P 20G (stack) + 2P 25G (Phy) 921 */ 922 /* same as 56160 option 6A gphy bypass */ 923 924 925 /* 53440 : option 2A gphy bypass 926 * 16P 1G + 8P 1G/2.5G + 2P 10G (Uplink) + 1P 20G (stack) + 2P 25G (Phy) 927 */ 928 /* same as 56160 option 6 gphy bypass */ 929 930 931 /* 53440 : option 3 gphy bypass 932 * 16P 1G + 8P 1G/2.5G + 4P 10G (Uplink) + 2P 10G (stack) 933 */ 934 static const int p2l_mapping_53440_op3_gphy_bypass[] = { 935 0, -1, 2, 3, 4, 5, 6, 7, 936 8, 9, -1, -1, -1, -1, -1, -1, 937 -1, -1, 10, 11, 12, 13, 14, 15, 938 16, 17, 18, 19, 20, 21, 22, 23, 939 24, 25, 26, 27, 28, -1, 29, 30, 940 31, -1 941 }; 942 static const int port_speed_max_53440_op3_gphy_bypass[] = { 943 -1, -1, 10, 10, 10, 10, 10, 10, 944 10, 10, -1, -1, -1, -1, -1, -1, 945 -1, -1, 10, 10, 10, 10, 10, 10, 946 10, 10, 10, 10, 10, 10, 10, 10, 947 10, 10, 110, 110, 110, -1, 110, 110, 948 110, -1 949 }; 950 951 952 /* 53440 : option 4 gphy bypass 953 * 16P 1G + 8P 1G/2.5G + 2P 10G (Uplink) + 1P 10G (stack) + 2P 25G (Phy) 954 */ 955 /* same as 56160 option 2A gphy bypass */ 956 static const int port_speed_max_53440_op4_gphy_bypass[] = { 957 -1, -1, 10, 10, 10, 10, 10, 10, 958 10, 10, -1, -1, -1, -1, -1, -1, 959 -1, -1, 10, 10, 10, 10, 10, 10, 960 10, 10, 10, 10, 10, 10, 10, 10, 961 10, 10, 250, -1, 250, -1, 110, 110, 962 110, -1 963 }; 964 965 966 /* 53440 : option 4A gphy bypass 967 * 16P 1G + 8P 1G/2.5G + 2P 10G (Uplink) + 1P 20G (stack) + 2P 25G (Phy) 968 */ 969 /* same as 56160 option 2 gphy bypass */ 970 static const int port_speed_max_53440_op4a_gphy_bypass[] = { 971 -1, -1, 10, 10, 10, 10, 10, 10, 972 10, 10, -1, -1, -1, -1, -1, -1, 973 -1, -1, 10, 10, 10, 10, 10, 10, 974 10, 10, 10, 10, 10, 10, 10, 10, 975 10, 10, 110, 110, 110, -1, 250, -1, 976 250, -1 977 }; 978 979 /* 53440 : option 5 gphy bypass 980 * 24P 1G + 4P 10G + 1P XAUI (Phy) 981 */ 982 /* same as 56160 option 3 gphy bypass */ 983 984 /* 53440 : option 6 gphy bypass 985 * 24P 1G + 2P XAUI (Phy) 986 */ 987 /* same as 56160 option 4 gphy bypass */ 988 989 /* 53440 : option 7 gphy bypass 990 * 16P 1G + 8x1G/2.5G + 2P 1G/10G + 4P 1G/10G (PHY) 991 */ 992 /* same as 56160 option 1 gphy bypass */ 993 994 /* 53440 : option 7A gphy bypass 995 * 16P 1G + 8x1G/2.5G + 2P 1G/10G + 4P 1G/10G (PHY) 996 */ 997 /* same as 56160 option 1A gphy bypass*/ 998 999 /* 53440 : option 8 gphy bypass 1000 * 16P 1G + 8x1G/2.5G + 2P 1G/10G + 2P 1G/10G + 2P 25G (PHY) 1001 */ 1002 /* same as 56160 option 2 gphy bypass*/ 1003 1004 /* 53440 : option 8A gphy bypass 1005 * 16P 1G + 8x1G/2.5G + 2P 1G/10G 2P 1G/10G + 2P 25G (PHY) 1006 */ 1007 /* same as 56160 option 2A gphy bypass*/ 1008 1009 /* 53442 : option 1 1010 * 24P 1G +4P 1G (PHY) 1011 */ 1012 /* same as 56162 option 1 */ 1013 1014 1015 /* 53442 : option 1A 1016 * 24P 1G +4P 1G (PHY) 1017 */ 1018 /* same as 56162 option 1A */ 1019 1020 1021 /* 53442 : option 2 1022 * 24P 1G + 2P 1G + 2P 13G (PHY) 1023 */ 1024 /* same as 56162 option 2 */ 1025 1026 1027 /* 53442 : option 1 gphy bypass 1028 * 24P 1G +4P 1G (PHY) 1029 */ 1030 /* same as 56162 option 1 gphy bypass */ 1031 1032 1033 /* 53442 : option 1A gphy bypass 1034 * 24P 1G +4P 1G (PHY) 1035 */ 1036 /* same as 56162 option 1A gphy bypass */ 1037 1038 1039 /* 53442 : option 2 gphy bypass 1040 * 24P 1G + 2P 1G + 2P 13G (PHY) 1041 */ 1042 /* same as 56162 option 2 gphy bypass */ 1043 1044 1045 /* 53443 : option 1 1046 * 8P 1G (PHY) + 2P 1G/2.5G/5G/10G 1047 */ 1048 /* same as 56163 option 1 */ 1049 1050 1051 /* 53443 : option 2 1052 * 8P 1G (PHY) + 4P 1G/2.5G OR 1P XAUI + 4P 1G/2.5G OR 1P XAUI 1053 */ 1054 /* same as 56163 option 2 */ 1055 1056 1057 /* 53443 : option 1 gphy bypass 1058 * 8P 1G (PHY) + 2P 1G/2.5G/5G/10G 1059 */ 1060 /* same as 56163 option 1 gphy bypass */ 1061 1062 1063 /* 53443 : option 2 gphy bypass 1064 * 8P 1G (PHY) + 4P 1G/2.5G OR 1P XAUI + 4P 1G/2.5G OR 1P XAUI 1065 */ 1066 /* same as 56163 option 2 gphy bypass */ 1067 1068 1069 1070 /* Hurricane 3 Lite */ 1071 1072 /* 56166 : option 1 1073 * 24P 1G +4P 1G/10G +2P 1G/10G 1074 */ 1075 static const int p2l_mapping_56166_op1[] = { 1076 0, -1, -1, -1, -1, -1, -1, -1, 1077 -1, -1, 2, 3, 4, 5, 6, 7, 1078 8, 9, 10, 11, 12, 13, 14, 15, 1079 16, 17, 18, 19, 20, 21, 22, 23, 1080 24, 25, 26, 27, 28, 29, 30, 31, 1081 -1, -1 1082 }; 1083 static const int port_speed_max_56166_op1[] = { 1084 -1, -1, -1, -1, -1, -1, -1, -1, 1085 -1, -1, 10, 10, 10, 10, 10, 10, 1086 10, 10, 10, 10, 10, 10, 10, 10, 1087 10, 10, 10, 10, 10, 10, 10, 10, 1088 10, 10, 110, 110, 110, 110, 110, 110, 1089 -1, -1 1090 }; 1091 1092 /* 56166 : option 1A 1093 * 24P 1G +2P 1G/10G +4P 1G/10G 1094 */ 1095 static const int p2l_mapping_56166_op1a[] = { 1096 0, -1, -1, -1, -1, -1, -1, -1, 1097 -1, -1, 2, 3, 4, 5, 6, 7, 1098 8, 9, 10, 11, 12, 13, 14, 15, 1099 16, 17, 18, 19, 20, 21, 22, 23, 1100 24, 25, 26, 27, -1, -1, 28, 29, 1101 30, 31 1102 }; 1103 static const int port_speed_max_56166_op1a[] = { 1104 -1, -1, -1, -1, -1, -1, -1, -1, 1105 -1, -1, 10, 10, 10, 10, 10, 10, 1106 10, 10, 10, 10, 10, 10, 10, 10, 1107 10, 10, 10, 10, 10, 10, 10, 10, 1108 10, 10, 110, 110, -1, -1, 110, 110, 1109 110, 110 1110 }; 1111 1112 /* 56166 : option 2 1113 * 24P 1G + 2P 1G/10G + 2P 25G 1114 */ 1115 static const int p2l_mapping_56166_op2[] = { 1116 0, -1, -1, -1, -1, -1, -1, -1, 1117 -1, -1, 2, 3, 4, 5, 6, 7, 1118 8, 9, 10, 11, 12, 13, 14, 15, 1119 16, 17, 18, 19, 20, 21, 22, 23, 1120 24, 25, 26, 27, -1, -1, 28, -1, 1121 29, -1 1122 }; 1123 static const int port_speed_max_56166_op2[] = { 1124 -1, -1, -1, -1, -1, -1, -1, -1, 1125 -1, -1, 10, 10, 10, 10, 10, 10, 1126 10, 10, 10, 10, 10, 10, 10, 10, 1127 10, 10, 10, 10, 10, 10, 10, 10, 1128 10, 10, 110, 110, -1, -1, 250, -1, 1129 250, -1 1130 }; 1131 1132 /* 56166 : option 2A 1133 * 24P 1G + 2P 25G + 2P 1G/10G 1134 */ 1135 static const int p2l_mapping_56166_op2a[] = { 1136 0, -1, -1, -1, -1, -1, -1, -1, 1137 -1, -1, 2, 3, 4, 5, 6, 7, 1138 8, 9, 10, 11, 12, 13, 14, 15, 1139 16, 17, 18, 19, 20, 21, 22, 23, 1140 24, 25, 26, -1, 27, -1, 28, 29, 1141 -1, -1 1142 }; 1143 static const int port_speed_max_56166_op2a[] = { 1144 -1, -1, -1, -1, -1, -1, -1, -1, 1145 -1, -1, 10, 10, 10, 10, 10, 10, 1146 10, 10, 10, 10, 10, 10, 10, 10, 1147 10, 10, 10, 10, 10, 10, 10, 10, 1148 10, 10, 250, -1, 250, -1, 110, 110, 1149 -1, -1 1150 }; 1151 1152 /* 56166 : option 3 1153 * 24P 1G +4P 1G/10G+1P XAUI 1154 */ 1155 static const int p2l_mapping_56166_op3[] = { 1156 0, -1, -1, -1, -1, -1, -1, -1, 1157 -1, -1, 2, 3, 4, 5, 6, 7, 1158 8, 9, 10, 11, 12, 13, 14, 15, 1159 16, 17, 18, 19, 20, 21, 22, 23, 1160 24, 25, 26, 27, 28, 29, 30, -1, 1161 -1, -1 1162 }; 1163 static const int port_speed_max_56166_op3[] = { 1164 -1, -1, -1, -1, -1, -1, -1, -1, 1165 -1, -1, 10, 10, 10, 10, 10, 10, 1166 10, 10, 10, 10, 10, 10, 10, 10, 1167 10, 10, 10, 10, 10, 10, 10, 10, 1168 10, 10, 110, 110, 110, 110, 100, -1, 1169 -1, -1 1170 }; 1171 1172 /* 56166 : option 4 1173 * 24P 1G +2P XAUI 1174 */ 1175 static const int p2l_mapping_56166_op4[] = { 1176 0, -1, -1, -1, -1, -1, -1, -1, 1177 -1, -1, 2, 3, 4, 5, 6, 7, 1178 8, 9, 10, 11, 12, 13, 14, 15, 1179 16, 17, 18, 19, 20, 21, 22, 23, 1180 24, 25, 26, -1, -1, -1, 27, -1, 1181 -1, -1 1182 }; 1183 static const int port_speed_max_56166_op4[] = { 1184 -1, -1, -1, -1, -1, -1, -1, -1, 1185 -1, -1, 10, 10, 10, 10, 10, 10, 1186 10, 10, 10, 10, 10, 10, 10, 10, 1187 10, 10, 10, 10, 10, 10, 10, 10, 1188 10, 10, 100, -1, -1, -1, 100, -1, 1189 -1, -1 1190 }; 1191 1192 /* 56166 : option 5 1193 * 24P 1G + 2P 1G/10G + 2P 20G 1194 */ 1195 static const int p2l_mapping_56166_op5[] = { 1196 0, -1, -1, -1, -1, -1, -1, -1, 1197 -1, -1, 2, 3, 4, 5, 6, 7, 1198 8, 9, 10, 11, 12, 13, 14, 15, 1199 16, 17, 18, 19, 20, 21, 22, 23, 1200 24, 25, 26, -1, 27, -1, 28, -1, 1201 29, -1 1202 }; 1203 static const int port_speed_max_56166_op5[] = { 1204 -1, -1, -1, -1, -1, -1, -1, -1, 1205 -1, -1, 10, 10, 10, 10, 10, 10, 1206 10, 10, 10, 10, 10, 10, 10, 10, 1207 10, 10, 10, 10, 10, 10, 10, 10, 1208 10, 10, 110, -1, 210, -1, 110, -1, 1209 210, -1 1210 }; 1211 1212 /* 56166 : option 6 1213 * 24P 1G +1P 1G/10G + 1P 20G + 2P 25G 1214 */ 1215 static const int p2l_mapping_56166_op6[] = { 1216 0, -1, -1, -1, -1, -1, -1, -1, 1217 -1, -1, 2, 3, 4, 5, 6, 7, 1218 8, 9, 10, 11, 12, 13, 14, 15, 1219 16, 17, 18, 19, 20, 21, 22, 23, 1220 24, 25, 26, -1, 27, -1, 28, -1, 1221 29, -1 1222 }; 1223 static const int port_speed_max_56166_op6[] = { 1224 -1, -1, -1, -1, -1, -1, -1, -1, 1225 -1, -1, 10, 10, 10, 10, 10, 10, 1226 10, 10, 10, 10, 10, 10, 10, 10, 1227 10, 10, 10, 10, 10, 10, 10, 10, 1228 10, 10, 110, -1, 210, -1, 250, -1, 1229 250, -1 1230 }; 1231 1232 /* 56166 : option 1 gphy bypass 1233 * 24P 1G +4P 1G/10G +2P 1G/10G 1234 */ 1235 static const int p2l_mapping_56166_op1_gphy_bypass[] = { 1236 0, -1, 2, 3, 4, 5, 6, 7, 1237 8, 9, -1, -1, -1, -1, -1, -1, 1238 -1, -1, 10, 11, 12, 13, 14, 15, 1239 16, 17, 18, 19, 20, 21, 22, 23, 1240 24, 25, 26, 27, 28, 29, 30, 31, 1241 -1, -1 1242 }; 1243 static const int port_speed_max_56166_op1_gphy_bypass[] = { 1244 -1, -1, 10, 10, 10, 10, 10, 10, 1245 10, 10, -1, -1, -1, -1, -1, -1, 1246 -1, -1, 10, 10, 10, 10, 10, 10, 1247 10, 10, 10, 10, 10, 10, 10, 10, 1248 10, 10, 110, 110, 110, 110, 110, 110, 1249 -1, -1 1250 }; 1251 1252 /* 56166 : option 1A gphy bypass 1253 * 24P 1G +2P 1G/10G +4P 1G/10G 1254 */ 1255 static const int p2l_mapping_56166_op1a_gphy_bypass[] = { 1256 0, -1, 2, 3, 4, 5, 6, 7, 1257 8, 9, -1, -1, -1, -1, -1, -1, 1258 -1, -1, 10, 11, 12, 13, 14, 15, 1259 16, 17, 18, 19, 20, 21, 22, 23, 1260 24, 25, 26, 27, -1, -1, 28, 29, 1261 30, 31 1262 }; 1263 static const int port_speed_max_56166_op1a_gphy_bypass[] = { 1264 -1, -1, 10, 10, 10, 10, 10, 10, 1265 10, 10, -1, -1, -1, -1, -1, -1, 1266 -1, -1, 10, 10, 10, 10, 10, 10, 1267 10, 10, 10, 10, 10, 10, 10, 10, 1268 10, 10, 110, 110, -1, -1, 110, 110, 1269 110, 110 1270 }; 1271 1272 /* 56166 : option 2 gphy bypass 1273 * 24P 1G + 2P 1G/10G + 2P 25G 1274 */ 1275 static const int p2l_mapping_56166_op2_gphy_bypass[] = { 1276 0, -1, 2, 3, 4, 5, 6, 7, 1277 8, 9, -1, -1, -1, -1, -1, -1, 1278 -1, -1, 10, 11, 12, 13, 14, 15, 1279 16, 17, 18, 19, 20, 21, 22, 23, 1280 24, 25, 26, 27, -1, -1, 28, -1, 1281 29, -1 1282 }; 1283 static const int port_speed_max_56166_op2_gphy_bypass[] = { 1284 -1, -1, 10, 10, 10, 10, 10, 10, 1285 10, 10, -1, -1, -1, -1, -1, -1, 1286 -1, -1, 10, 10, 10, 10, 10, 10, 1287 10, 10, 10, 10, 10, 10, 10, 10, 1288 10, 10, 110, 110, -1, -1, 250, -1, 1289 250, -1 1290 }; 1291 1292 /* 56166 : option 2A gphy bypass 1293 * 24P 1G + 2P 25G + 2P 1G/10G 1294 */ 1295 static const int p2l_mapping_56166_op2a_gphy_bypass[] = { 1296 0, -1, 2, 3, 4, 5, 6, 7, 1297 8, 9, -1, -1, -1, -1, -1, -1, 1298 -1, -1, 10, 11, 12, 13, 14, 15, 1299 16, 17, 18, 19, 20, 21, 22, 23, 1300 24, 25, 26, -1, 27, -1, 28, 29, 1301 -1, -1 1302 }; 1303 static const int port_speed_max_56166_op2a_gphy_bypass[] = { 1304 -1, -1, 10, 10, 10, 10, 10, 10, 1305 10, 10, -1, -1, -1, -1, -1, -1, 1306 -1, -1, 10, 10, 10, 10, 10, 10, 1307 10, 10, 10, 10, 10, 10, 10, 10, 1308 10, 10, 250, -1, 250, -1, 110, 110, 1309 -1, -1 1310 }; 1311 1312 /* 56166 : option 3 gphy bypass 1313 * 24P 1G +4P 1G/10G+1P XAUI 1314 */ 1315 static const int p2l_mapping_56166_op3_gphy_bypass[] = { 1316 0, -1, 2, 3, 4, 5, 6, 7, 1317 8, 9, -1, -1, -1, -1, -1, -1, 1318 -1, -1, 10, 11, 12, 13, 14, 15, 1319 16, 17, 18, 19, 20, 21, 22, 23, 1320 24, 25, 26, 27, 28, 29, 30, -1, 1321 -1, -1 1322 }; 1323 static const int port_speed_max_56166_op3_gphy_bypass[] = { 1324 -1, -1, 10, 10, 10, 10, 10, 10, 1325 10, 10, -1, -1, -1, -1, -1, -1, 1326 -1, -1, 10, 10, 10, 10, 10, 10, 1327 10, 10, 10, 10, 10, 10, 10, 10, 1328 10, 10, 110, 110, 110, 110, 100, -1, 1329 -1, -1 1330 }; 1331 1332 /* 56166 : option 4 gphy bypass 1333 * 24P 1G +2P XAUI 1334 */ 1335 static const int p2l_mapping_56166_op4_gphy_bypass[] = { 1336 0, -1, 2, 3, 4, 5, 6, 7, 1337 8, 9, -1, -1, -1, -1, -1, -1, 1338 -1, -1, 10, 11, 12, 13, 14, 15, 1339 16, 17, 18, 19, 20, 21, 22, 23, 1340 24, 25, 26, -1, -1, -1, 27, -1, 1341 -1, -1 1342 }; 1343 static const int port_speed_max_56166_op4_gphy_bypass[] = { 1344 -1, -1, 10, 10, 10, 10, 10, 10, 1345 10, 10, -1, -1, -1, -1, -1, -1, 1346 -1, -1, 10, 10, 10, 10, 10, 10, 1347 10, 10, 10, 10, 10, 10, 10, 10, 1348 10, 10, 100, -1, -1, -1, 100, -1, 1349 -1, -1 1350 }; 1351 1352 /* 56166 : option 5 gphy bypass 1353 * 24P 1G + 2P 1G/10G + 2P 20G 1354 */ 1355 static const int p2l_mapping_56166_op5_gphy_bypass[] = { 1356 0, -1, 2, 3, 4, 5, 6, 7, 1357 8, 9, -1, -1, -1, -1, -1, -1, 1358 -1, -1, 10, 11, 12, 13, 14, 15, 1359 16, 17, 18, 19, 20, 21, 22, 23, 1360 24, 25, 26, -1, 27, -1, 28, -1, 1361 29, -1 1362 }; 1363 static const int port_speed_max_56166_op5_gphy_bypass[] = { 1364 -1, -1, 10, 10, 10, 10, 10, 10, 1365 10, 10, -1, -1, -1, -1, -1, -1, 1366 -1, -1, 10, 10, 10, 10, 10, 10, 1367 10, 10, 10, 10, 10, 10, 10, 10, 1368 10, 10, 110, -1, 210, -1, 110, -1, 1369 210, -1 1370 }; 1371 1372 /* 56166 : option 6 gphy bypass 1373 * 24P 1G +1P 1G/10G + 1P 20G + 2P 25G 1374 */ 1375 static const int p2l_mapping_56166_op6_gphy_bypass[] = { 1376 0, -1, 2, 3, 4, 5, 6, 7, 1377 8, 9, -1, -1, -1, -1, -1, -1, 1378 -1, -1, 10, 11, 12, 13, 14, 15, 1379 16, 17, 18, 19, 20, 21, 22, 23, 1380 24, 25, 26, -1, 27, -1, 28, -1, 1381 29, -1 1382 }; 1383 static const int port_speed_max_56166_op6_gphy_bypass[] = { 1384 -1, -1, 10, 10, 10, 10, 10, 10, 1385 10, 10, -1, -1, -1, -1, -1, -1, 1386 -1, -1, 10, 10, 10, 10, 10, 10, 1387 10, 10, 10, 10, 10, 10, 10, 10, 1388 10, 10, 110, -1, 210, -1, 250, -1, 1389 250, -1 1390 }; 1391 1392 1393 1394 /* Foxhound2 */ 1395 1396 /* 53434 : 1397 * 24P 1G (PHY) 1398 */ 1399 /* Phyiscal to logical mapping as 56162 option 1 */ 1400 1401 static const int port_speed_max_53434[] = { 1402 0, -1, -1, -1, -1, -1, -1, -1, 1403 -1, -1, 10, 10, 10, 10, 10, 10, 1404 10, 10, 10, 10, 10, 10, 10, 10, 1405 10, 10, 10, 10, 10, 10, 10, 10, 1406 10, 10, -1, -1, -1, -1, -1, -1, 1407 -1, -1 1408 }; 1409 1410 1411 /* Template TDM */ 1412 /* Should be provided by design team */ 1413 uint32 hr3_tdm_template_56160_op1[50] = { 1414 38, 36, 34, 12, 1415 39, 37, 35, 13, 1416 2, 18, 26, 14, 1417 38, 36, 34, 15, 1418 39, 37, 35, 16, 1419 3, 19, 27, 17, 1420 38, 36, 34, 28, 1421 39, 37, 35, 29, 1422 4, 20, 10, 30, 1423 38, 36, 34, 31, 1424 39, 37, 35, 32, 1425 5, 21, 11, 33, 1426 0, 63 1427 }; 1428 1429 uint32 hr3_tdm_template_56160_op1a[50] = { 1430 38, 40, 34, 12, 1431 39, 41, 35, 13, 1432 2, 18, 26, 14, 1433 38, 40, 34, 15, 1434 39, 41, 35, 16, 1435 3, 19, 27, 17, 1436 38, 40, 34, 28, 1437 39, 41, 35, 29, 1438 4, 20, 10, 30, 1439 38, 40, 34, 31, 1440 39, 41, 35, 32, 1441 5, 21, 11, 33, 1442 0, 63 1443 }; 1444 1445 uint32 hr3_tdm_template_56160_op2[64] = { 1446 38, 40, 34, 10, 1447 38, 40, 35, 11, 1448 2, 18, 36, 12, 1449 38, 40, 37, 13, 1450 38, 40, 34, 14, 1451 3, 19, 35, 15, 1452 38, 40, 36, 16, 1453 38, 40, 37, 17, 1454 4, 20, 34, 26, 1455 38, 40, 35, 27, 1456 38, 40, 36, 28, 1457 5, 21, 37, 29, 1458 38, 40, 34, 30, 1459 0, 63, 35, 31, 1460 38, 40, 36, 32, 1461 63, 63, 37, 33 1462 }; 1463 1464 uint32 hr3_tdm_template_56160_op2a[64] = { 1465 34, 36, 38, 10, 1466 34, 36, 39, 11, 1467 2, 18, 40, 12, 1468 34, 36, 41, 13, 1469 34, 36, 38, 14, 1470 3, 19, 39, 15, 1471 34, 36, 40, 16, 1472 34, 36, 41, 17, 1473 4, 20, 38, 26, 1474 34, 36, 39, 27, 1475 34, 36, 40, 28, 1476 5, 21, 41, 29, 1477 34, 36, 38, 30, 1478 0, 63, 39, 31, 1479 34, 36, 40, 32, 1480 63, 63, 41, 33 1481 }; 1482 1483 1484 uint32 hr3_tdm_template_56160_op5[66] = { 1485 36, 34, 38, 2, 1486 40, 35, 39, 3, 1487 36, 10, 26, 4, 1488 40, 11, 27, 5, 1489 36, 34, 38, 18, 1490 40, 35, 39, 19, 1491 36, 12, 28, 20, 1492 40, 13, 29, 21, 1493 36, 34, 38, 2, 1494 40, 35, 39, 3, 1495 36, 14, 30, 4, 1496 40, 15, 31, 5, 1497 36, 34, 38, 18, 1498 40, 35, 39, 19, 1499 36, 16, 32, 20, 1500 40, 17, 33, 21, 1501 0, 63 1502 }; 1503 1504 uint32 hr3_tdm_template_56160_op6[64] = { 1505 38, 40, 34, 10, 1506 38, 40, 35, 11, 1507 2, 18, 36, 12, 1508 38, 40, 36, 13, 1509 38, 40, 34, 14, 1510 3, 19, 35, 15, 1511 38, 40, 36, 16, 1512 38, 40, 36, 17, 1513 4, 20, 34, 26, 1514 38, 40, 35, 27, 1515 38, 40, 36, 28, 1516 5, 21, 36, 29, 1517 38, 40, 34, 30, 1518 0, 63, 35, 31, 1519 38, 40, 36, 32, 1520 63, 63, 36, 33 1521 }; 1522 1523 uint32 hr3_tdm_template_56160_op6a[64] = { 1524 34, 36, 38, 10, 1525 34, 36, 39, 11, 1526 2, 18, 40, 12, 1527 34, 36, 40, 13, 1528 34, 36, 38, 14, 1529 3, 19, 39, 15, 1530 34, 36, 40, 16, 1531 34, 36, 40, 17, 1532 4, 20, 38, 26, 1533 34, 36, 39, 27, 1534 34, 36, 40, 28, 1535 5, 21, 40, 29, 1536 34, 36, 38, 30, 1537 0, 63, 39, 31, 1538 34, 36, 40, 32, 1539 63, 63, 40, 33 1540 }; 1541 1542 1543 uint32 hr3_tdm_template_56160_op7[68] = { 1544 34, 38, 2, 18, 1545 34, 38, 10, 26, 1546 34, 38, 3, 19, 1547 34, 38, 11, 27, 1548 34, 38, 4, 20, 1549 34, 38, 12, 28, 1550 34, 38, 5, 21, 1551 34, 38, 13, 29, 1552 34, 38, 2, 18, 1553 34, 38, 14, 30, 1554 34, 38, 3, 19, 1555 34, 38, 15, 31, 1556 34, 38, 4, 20, 1557 34, 38, 16, 32, 1558 34, 38, 5, 21, 1559 34, 38, 17, 33, 1560 34, 38, 0, 63 1561 }; 1562 1563 uint32 hr3_tdm_template_56160_op8[80] = { 1564 38, 34, 36, 18, 1565 38, 34, 36, 26, 1566 38, 34, 36, 19, 1567 38, 34, 2, 27, 1568 38, 36, 10, 20, 1569 38, 34, 3, 28, 1570 38, 36, 11, 21, 1571 38, 34, 4, 29, 1572 38, 36, 12, 18, 1573 38, 34, 5, 30, 1574 38, 36, 13, 19, 1575 38, 34, 36, 2, 1576 38, 34, 36, 14, 1577 38, 34, 36, 31, 1578 38, 34, 3, 20, 1579 38, 36, 15, 32, 1580 38, 34, 4, 21, 1581 38, 36, 16, 33, 1582 38, 34, 5, 0, 1583 38, 36, 17, 63 1584 }; 1585 1586 uint32 hr3_tdm_template_56160_op8a[80] = { 1587 34, 38, 40, 18, 1588 34, 38, 40, 26, 1589 34, 38, 40, 19, 1590 34, 38, 2, 27, 1591 34, 40, 10, 20, 1592 34, 38, 3, 28, 1593 34, 40, 11, 21, 1594 34, 38, 4, 29, 1595 34, 40, 12, 18, 1596 34, 38, 5, 30, 1597 34, 40, 13, 19, 1598 34, 38, 40, 2, 1599 34, 38, 40, 14, 1600 34, 38, 40, 31, 1601 34, 38, 3, 20, 1602 34, 40, 15, 32, 1603 34, 38, 4, 21, 1604 34, 40, 16, 33, 1605 34, 38, 5, 0, 1606 34, 40, 17, 63 1607 }; 1608 1609 uint32 hr3_tdm_template_56160_op9[64] = { 1610 38, 40, 34, 10, 1611 38, 40, 34, 11, 1612 2, 18, 36, 12, 1613 38, 40, 36, 13, 1614 38, 40, 34, 14, 1615 3, 19, 34, 15, 1616 38, 40, 36, 16, 1617 38, 40, 36, 17, 1618 4, 20, 34, 26, 1619 38, 40, 34, 27, 1620 38, 40, 36, 28, 1621 5, 21, 36, 29, 1622 38, 40, 34, 30, 1623 0, 63, 34, 31, 1624 38, 40, 36, 32, 1625 63, 63, 36, 33, 1626 }; 1627 1628 uint32 hr3_tdm_template_56160_op9a[64] = { 1629 34, 36, 38, 10, 1630 34, 36, 38, 11, 1631 2, 18, 40, 12, 1632 34, 36, 40, 13, 1633 34, 36, 38, 14, 1634 3, 19, 38, 15, 1635 34, 36, 40, 16, 1636 34, 36, 40, 17, 1637 4, 20, 38, 26, 1638 34, 36, 38, 27, 1639 34, 36, 40, 28, 1640 5, 21, 40, 29, 1641 34, 36, 38, 30, 1642 0, 63, 38, 31, 1643 34, 36, 40, 32, 1644 63, 63, 40, 33, 1645 }; 1646 1647 /* 56160 GPHY BYPASS TDMs */ 1648 1649 uint32 hr3_tdm_template_56160_op1_gphy_bypass[50] = { 1650 38, 36, 7, 22, 1651 39, 37, 34, 26, 1652 2, 18, 35, 27, 1653 38, 36, 8, 23, 1654 39, 37, 34, 28, 1655 3, 19, 35, 29, 1656 38, 36, 9, 24, 1657 39, 37, 34, 30, 1658 4, 20, 35, 31, 1659 38, 36, 6, 25, 1660 39, 37, 34, 32, 1661 5, 21, 35, 33, 1662 0, 63 1663 }; 1664 1665 uint32 hr3_tdm_template_56160_op1a_gphy_bypass[50] = { 1666 38, 40, 7, 22, 1667 39, 41, 34, 26, 1668 2, 18, 35, 27, 1669 38, 40, 8, 23, 1670 39, 41, 34, 28, 1671 3, 19, 35, 29, 1672 38, 40, 9, 24, 1673 39, 41, 34, 30, 1674 4, 20, 35, 31, 1675 38, 40, 6, 25, 1676 39, 41, 34, 32, 1677 5, 21, 35, 33, 1678 0, 63 1679 }; 1680 1681 uint32 hr3_tdm_template_56160_op2_gphy_bypass[64] = { 1682 38, 40, 34, 6, 1683 38, 40, 35, 7, 1684 0, 18, 36, 8, 1685 38, 40, 37, 9, 1686 38, 40, 34, 26, 1687 3, 19, 35, 27, 1688 38, 40, 36, 28, 1689 38, 40, 37, 29, 1690 4, 20, 34, 30, 1691 38, 40, 35, 31, 1692 38, 40, 36, 32, 1693 5, 21, 37, 33, 1694 38, 40, 34, 22, 1695 2, 63, 35, 23, 1696 38, 40, 36, 24, 1697 63, 63, 37, 25 1698 }; 1699 1700 uint32 hr3_tdm_template_56160_op2a_gphy_bypass[64] = { 1701 34, 36, 38, 6, 1702 34, 36, 39, 7, 1703 0, 18, 40, 8, 1704 34, 36, 41, 9, 1705 34, 36, 38, 26, 1706 3, 19, 39, 27, 1707 34, 36, 40, 28, 1708 34, 36, 41, 29, 1709 4, 20, 38, 30, 1710 34, 36, 39, 31, 1711 34, 36, 40, 32, 1712 5, 21, 41, 33, 1713 34, 36, 38, 22, 1714 2, 63, 39, 23, 1715 34, 36, 40, 24, 1716 63, 63, 41, 25 1717 }; 1718 1719 1720 uint32 hr3_tdm_template_56160_op5_gphy_bypass[66] = { 1721 36, 34, 38, 2, 1722 40, 35, 39, 3, 1723 36, 22, 26, 4, 1724 40, 23, 27, 5, 1725 36, 34, 38, 18, 1726 40, 35, 39, 19, 1727 36, 8, 28, 20, 1728 40, 9, 29, 21, 1729 36, 34, 38, 2, 1730 40, 35, 39, 3, 1731 36, 24, 30, 4, 1732 40, 25, 31, 5, 1733 36, 34, 38, 18, 1734 40, 35, 39, 19, 1735 36, 6, 32, 20, 1736 40, 7, 33, 21, 1737 0, 63 1738 }; 1739 1740 uint32 hr3_tdm_template_56160_op6_gphy_bypass[64] = { 1741 38, 40, 34, 6, 1742 38, 40, 35, 7, 1743 0, 18, 36, 8, 1744 38, 40, 36, 9, 1745 38, 40, 34, 26, 1746 3, 19, 35, 27, 1747 38, 40, 36, 28, 1748 38, 40, 36, 29, 1749 4, 20, 34, 30, 1750 38, 40, 35, 31, 1751 38, 40, 36, 32, 1752 5, 21, 36, 33, 1753 38, 40, 34, 22, 1754 2, 63, 35, 23, 1755 38, 40, 36, 24, 1756 63, 63, 36, 25 1757 }; 1758 1759 uint32 hr3_tdm_template_56160_op6a_gphy_bypass[64] = { 1760 34, 36, 38, 6, 1761 34, 36, 39, 7, 1762 0, 18, 40, 8, 1763 34, 36, 40, 9, 1764 34, 36, 38, 26, 1765 3, 19, 39, 27, 1766 34, 36, 40, 28, 1767 34, 36, 40, 29, 1768 4, 20, 38, 30, 1769 34, 36, 39, 31, 1770 34, 36, 40, 32, 1771 5, 21, 40, 33, 1772 34, 36, 38, 22, 1773 2, 63, 39, 23, 1774 34, 36, 40, 24, 1775 63, 63, 40, 25 1776 }; 1777 1778 uint32 hr3_tdm_template_56160_op7_gphy_bypass[68] = { 1779 34, 38, 2, 18, 1780 34, 38, 6, 26, 1781 34, 38, 3, 19, 1782 34, 38, 7, 27, 1783 34, 38, 4, 20, 1784 34, 38, 8, 28, 1785 34, 38, 5, 21, 1786 34, 38, 9, 29, 1787 34, 38, 2, 18, 1788 34, 38, 30, 22, 1789 34, 38, 3, 19, 1790 34, 38, 31, 23, 1791 34, 38, 4, 20, 1792 34, 38, 32, 24, 1793 34, 38, 5, 21, 1794 34, 38, 33, 25, 1795 34, 38, 0, 63 1796 }; 1797 1798 1799 uint32 hr3_tdm_template_56160_op8_gphy_bypass[80] = { 1800 38, 34, 36, 18, 1801 38, 34, 36, 26, 1802 38, 34, 36, 19, 1803 38, 34, 2, 27, 1804 38, 36, 6, 20, 1805 38, 34, 3, 28, 1806 38, 36, 7, 21, 1807 38, 34, 4, 29, 1808 38, 36, 8, 18, 1809 38, 34, 5, 30, 1810 38, 36, 9, 19, 1811 38, 34, 36, 2, 1812 38, 34, 36, 22, 1813 38, 34, 36, 31, 1814 38, 34, 3, 20, 1815 38, 36, 32, 23, 1816 38, 34, 4, 21, 1817 38, 36, 33, 24, 1818 38, 34, 5, 0, 1819 38, 36, 63, 25 1820 }; 1821 1822 uint32 hr3_tdm_template_56160_op8a_gphy_bypass[80] = { 1823 34, 38, 40, 18, 1824 34, 38, 40, 26, 1825 34, 38, 40, 19, 1826 34, 38, 2, 27, 1827 34, 40, 6, 20, 1828 34, 38, 3, 28, 1829 34, 40, 7, 21, 1830 34, 38, 4, 29, 1831 34, 40, 8, 18, 1832 34, 38, 5, 30, 1833 34, 40, 9, 19, 1834 34, 38, 40, 2, 1835 34, 38, 40, 22, 1836 34, 38, 40, 31, 1837 34, 38, 3, 20, 1838 34, 40, 32, 23, 1839 34, 38, 4, 21, 1840 34, 40, 33, 24, 1841 34, 38, 5, 0, 1842 34, 40, 63, 25 1843 }; 1844 1845 uint32 hr3_tdm_template_56160_op9_gphy_bypass[64] = { 1846 38, 40, 34, 6, 1847 38, 40, 34, 7, 1848 0, 18, 36, 8, 1849 38, 40, 36, 9, 1850 38, 40, 34, 26, 1851 3, 19, 34, 27, 1852 38, 40, 36, 28, 1853 38, 40, 36, 29, 1854 4, 20, 34, 30, 1855 38, 40, 34, 31, 1856 38, 40, 36, 32, 1857 5, 21, 36, 33, 1858 38, 40, 34, 22, 1859 2, 63, 34, 23, 1860 38, 40, 36, 24, 1861 63, 63, 36, 25, 1862 }; 1863 1864 uint32 hr3_tdm_template_56160_op9a_gphy_bypass[64] = { 1865 34, 36, 38, 6, 1866 34, 36, 38, 7, 1867 0, 18, 40, 8, 1868 34, 36, 40, 9, 1869 34, 36, 38, 26, 1870 3, 19, 38, 27, 1871 34, 36, 40, 28, 1872 34, 36, 40, 29, 1873 4, 20, 38, 30, 1874 34, 36, 38, 31, 1875 34, 36, 40, 32, 1876 5, 21, 40, 33, 1877 34, 36, 38, 22, 1878 2, 63, 38, 23, 1879 34, 36, 40, 24, 1880 63, 63, 40, 25, 1881 }; 1882 1883 /* 56162 TDMs */ 1884 1885 uint32 hr3_tdm_template_56162_op1[34] = { 1886 10, 18, 26, 34, 1887 11, 19, 27, 35, 1888 12, 20, 28, 36, 1889 13, 21, 29, 37, 1890 14, 22, 30, 34, 1891 15, 23, 31, 35, 1892 16, 24, 32, 36, 1893 17, 25, 33, 37, 1894 0, 63 1895 }; 1896 1897 uint32 hr3_tdm_template_56162_op1a[34] = { 1898 10, 18, 26, 38, 1899 11, 19, 27, 39, 1900 12, 20, 28, 40, 1901 13, 21, 29, 41, 1902 14, 22, 30, 38, 1903 15, 23, 31, 39, 1904 16, 24, 32, 40, 1905 17, 25, 33, 41, 1906 0, 63 1907 }; 1908 1909 uint32 hr3_tdm_template_56162_op2[54] = { 1910 38, 40, 10, 34, 1911 38, 40, 11, 35, 1912 38, 40, 12, 31, 1913 38, 40, 13, 32, 1914 38, 40, 14, 33, 1915 38, 40, 15, 18, 1916 38, 40, 16, 19, 1917 38, 40, 17, 20, 1918 38, 40, 26, 21, 1919 38, 40, 27, 22, 1920 38, 40, 28, 23, 1921 38, 40, 29, 24, 1922 38, 40, 30, 25, 1923 0, 63 1924 }; 1925 1926 /* 56162 GPHY BYPASS TDMs */ 1927 1928 uint32 hr3_tdm_template_56162_op1_gphy_bypass[34] = { 1929 2, 18, 26, 34, 1930 3, 19, 27, 35, 1931 4, 20, 28, 36, 1932 5, 21, 29, 37, 1933 6, 22, 30, 34, 1934 7, 23, 31, 35, 1935 8, 24, 32, 36, 1936 9, 25, 33, 37, 1937 0, 63 1938 }; 1939 1940 uint32 hr3_tdm_template_56162_op1a_gphy_bypass[34] = { 1941 2, 18, 26, 38, 1942 3, 19, 27, 39, 1943 4, 20, 28, 40, 1944 5, 21, 29, 41, 1945 6, 22, 30, 38, 1946 7, 23, 31, 39, 1947 8, 24, 32, 40, 1948 9, 25, 33, 41, 1949 0, 63 1950 }; 1951 1952 uint32 hr3_tdm_template_56162_op2_gphy_bypass[54] = { 1953 38, 40, 2, 34, 1954 38, 40, 3, 35, 1955 38, 40, 4, 31, 1956 38, 40, 5, 32, 1957 38, 40, 6, 33, 1958 38, 40, 7, 18, 1959 38, 40, 8, 19, 1960 38, 40, 9, 20, 1961 38, 40, 26, 21, 1962 38, 40, 27, 22, 1963 38, 40, 28, 23, 1964 38, 40, 29, 24, 1965 38, 40, 30, 25, 1966 0, 63 1967 }; 1968 1969 /* Hurricane3 Lite TDMs */ 1970 1971 uint32 hr3_tdm_template_56163_op1[32] = { 1972 34, 38, 0, 10, 1973 34, 38, 63, 11, 1974 34, 38, 63, 12, 1975 34, 38, 63, 13, 1976 34, 38, 63, 14, 1977 34, 38, 63, 15, 1978 34, 38, 63, 16, 1979 34, 38, 63, 17 1980 }; 1981 1982 uint32 hr3_tdm_template_56163_op2[32] = { 1983 34, 38, 0, 10, 1984 35, 39, 63, 11, 1985 36, 40, 63, 12, 1986 37, 41, 63, 13, 1987 34, 38, 63, 14, 1988 35, 39, 63, 15, 1989 36, 40, 63, 16, 1990 37, 41, 63, 17 1991 }; 1992 1993 /* 56163 GPHY BYPASS TDMs */ 1994 uint32 hr3_tdm_template_56163_op1_gphy_bypass[32] = { 1995 34, 38, 0, 2, 1996 34, 38, 63, 3, 1997 34, 38, 63, 4, 1998 34, 38, 63, 5, 1999 34, 38, 63, 18, 2000 34, 38, 63, 19, 2001 34, 38, 63, 20, 2002 34, 38, 63, 21 2003 }; 2004 2005 uint32 hr3_tdm_template_56163_op2_gphy_bypass[32] = { 2006 34, 38, 0, 2, 2007 35, 39, 63, 3, 2008 36, 40, 63, 4, 2009 37, 41, 63, 5, 2010 34, 38, 63, 18, 2011 35, 39, 63, 19, 2012 36, 40, 63, 20, 2013 37, 41, 63, 21 2014 }; 2015 2016 2017 /* Buckhound TDMs */ 2018 2019 /* 53440 TDMs */ 2020 uint32 hr3_tdm_template_53440_op3[50] = { 2021 38, 36, 34, 12, 2022 39, 40, 35, 13, 2023 2, 18, 26, 14, 2024 38, 36, 34, 15, 2025 39, 40, 35, 16, 2026 3, 19, 27, 17, 2027 38, 36, 34, 28, 2028 39, 40, 35, 29, 2029 4, 20, 10, 30, 2030 38, 36, 34, 31, 2031 39, 40, 35, 32, 2032 5, 21, 11, 33, 2033 0, 63 2034 }; 2035 2036 uint32 hr3_tdm_template_53440_op3_gphy_bypass[50] = { 2037 38, 40, 7, 22, 2038 39, 36, 34, 26, 2039 2, 18, 35, 27, 2040 38, 40, 8, 23, 2041 39, 36, 34, 28, 2042 3, 19, 35, 29, 2043 38, 40, 9, 24, 2044 39, 36, 34, 30, 2045 4, 20, 35, 31, 2046 38, 40, 6, 25, 2047 39, 36, 34, 32, 2048 5, 21, 35, 33, 2049 0, 63 2050 }; 2051 2052 /* 56166 GPHY BYPASS TDMs */ 2053 uint32 hr3_tdm_template_56166_op1_gphy_bypass[86] = { 2054 38, 36, 34, 18, 2055 39, 37, 35, 19, 2056 38, 36, 34, 20, 2057 39, 37, 35, 21, 2058 38, 36, 34, 22, 2059 39, 37, 35, 23, 2060 38, 36, 34, 24, 2061 39, 37, 35, 26, 2062 38, 36, 34, 27, 2063 39, 37, 35, 28, 2064 38, 36, 34, 29, 2065 39, 37, 35, 30, 2066 38, 36, 34, 31, 2067 39, 37, 35, 2, 2068 38, 36, 34, 3, 2069 39, 37, 35, 4, 2070 38, 36, 34, 5, 2071 39, 37, 35, 6, 2072 38, 36, 34, 7, 2073 39, 37, 32, 8, 2074 35, 25, 33, 9, 2075 0, 63 2076 }; 2077 2078 2079 uint32 hr3_tdm_template_56166_op1a_gphy_bypass[86] = { 2080 38, 40, 34, 18, 2081 39, 41, 35, 19, 2082 38, 40, 34, 20, 2083 39, 41, 35, 21, 2084 38, 40, 34, 22, 2085 39, 41, 35, 23, 2086 38, 40, 34, 24, 2087 39, 41, 35, 26, 2088 38, 40, 34, 27, 2089 39, 41, 35, 28, 2090 38, 40, 34, 29, 2091 39, 41, 35, 30, 2092 38, 40, 34, 31, 2093 39, 41, 35, 2, 2094 38, 40, 34, 3, 2095 39, 41, 35, 4, 2096 38, 40, 34, 5, 2097 39, 41, 35, 6, 2098 38, 40, 34, 7, 2099 39, 41, 32, 8, 2100 35, 25, 33, 9, 2101 0, 63 2102 }; 2103 2104 uint32 hr3_tdm_template_56166_op2_gphy_bypass[96] = { 2105 38, 40, 34, 2, 2106 38, 40, 35, 3, 2107 38, 40, 34, 4, 2108 38, 40, 35, 5, 2109 38, 40, 34, 6, 2110 38, 40, 35, 7, 2111 38, 40, 34, 8, 2112 38, 40, 35, 9, 2113 38, 40, 34, 18, 2114 38, 40, 35, 19, 2115 38, 40, 34, 20, 2116 38, 40, 35, 21, 2117 38, 40, 34, 22, 2118 38, 40, 35, 23, 2119 38, 40, 34, 24, 2120 38, 40, 35, 25, 2121 38, 40, 34, 26, 2122 38, 40, 35, 27, 2123 38, 40, 34, 28, 2124 38, 40, 35, 29, 2125 38, 40, 0, 30, 2126 38, 40, 34, 31, 2127 38, 40, 35, 32, 2128 38, 40, 63, 33 2129 }; 2130 2131 uint32 hr3_tdm_template_56166_op2a_gphy_bypass[96] = { 2132 34, 36, 38, 2, 2133 34, 36, 39, 3, 2134 34, 36, 38, 4, 2135 34, 36, 39, 5, 2136 34, 36, 38, 6, 2137 34, 36, 39, 7, 2138 34, 36, 38, 8, 2139 34, 36, 39, 9, 2140 34, 36, 38, 18, 2141 34, 36, 39, 19, 2142 34, 36, 38, 20, 2143 34, 36, 39, 21, 2144 34, 36, 38, 22, 2145 34, 36, 39, 23, 2146 34, 36, 38, 24, 2147 34, 36, 39, 25, 2148 34, 36, 38, 26, 2149 34, 36, 39, 27, 2150 34, 36, 38, 28, 2151 34, 36, 39, 29, 2152 34, 36, 0, 30, 2153 34, 36, 38, 31, 2154 34, 36, 39, 32, 2155 34, 36, 63, 33 2156 }; 2157 2158 uint32 hr3_tdm_template_56166_op5_gphy_bypass[86] = { 2159 36, 40, 34, 19, 2160 36, 40, 38, 20, 2161 36, 40, 34, 21, 2162 36, 40, 38, 22, 2163 36, 40, 34, 23, 2164 36, 40, 38, 24, 2165 36, 40, 34, 25, 2166 36, 40, 38, 26, 2167 36, 40, 34, 27, 2168 36, 40, 38, 28, 2169 18, 9, 0, 29, 2170 36, 40, 34, 30, 2171 36, 40, 38, 31, 2172 36, 40, 34, 32, 2173 36, 40, 38, 2, 2174 36, 40, 34, 3, 2175 36, 40, 38, 4, 2176 36, 40, 34, 5, 2177 36, 40, 38, 6, 2178 36, 40, 34, 7, 2179 36, 40, 38, 8, 2180 33, 63 2181 }; 2182 2183 uint32 hr3_tdm_template_56166_op6_gphy_bypass[92] = { 2184 38, 40, 36, 5, 2185 38, 40, 36, 6, 2186 38, 40, 36, 34, 2187 38, 40, 36, 26, 2188 2, 40, 18, 34, 2189 38, 40, 36, 27, 2190 38, 40, 36, 7, 2191 38, 40, 19, 34, 2192 38, 40, 36, 28, 2193 3, 0, 20, 34, 2194 38, 40, 36, 8, 2195 38, 40, 36, 29, 2196 38, 40, 21, 34, 2197 38, 40, 36, 30, 2198 4, 63, 22, 34, 2199 38, 40, 36, 31, 2200 38, 40, 36, 32, 2201 38, 40, 23, 34, 2202 38, 40, 36, 9, 2203 38, 63, 24, 34, 2204 38, 40, 36, 33, 2205 38, 40, 36, 34, 2206 38, 40, 36, 25 2207 }; 2208 2209 /* 56166 TDMs */ 2210 uint32 hr3_tdm_template_56166_op1[86] = { 2211 38, 36, 34, 18, 2212 39, 37, 35, 19, 2213 38, 36, 34, 20, 2214 39, 37, 35, 21, 2215 38, 36, 34, 22, 2216 39, 37, 35, 23, 2217 38, 36, 34, 24, 2218 39, 37, 35, 26, 2219 38, 36, 34, 27, 2220 39, 37, 35, 28, 2221 38, 36, 34, 29, 2222 39, 37, 35, 30, 2223 38, 36, 34, 31, 2224 39, 37, 35, 10, 2225 38, 36, 34, 11, 2226 39, 37, 35, 12, 2227 38, 36, 34, 13, 2228 39, 37, 35, 14, 2229 38, 36, 34, 15, 2230 39, 37, 32, 16, 2231 35, 25, 33, 17, 2232 0, 63 2233 }; 2234 2235 uint32 hr3_tdm_template_56166_op1a[86] = { 2236 38, 40, 34, 18, 2237 39, 41, 35, 19, 2238 38, 40, 34, 20, 2239 39, 41, 35, 21, 2240 38, 40, 34, 22, 2241 39, 41, 35, 23, 2242 38, 40, 34, 24, 2243 39, 41, 35, 26, 2244 38, 40, 34, 27, 2245 39, 41, 35, 28, 2246 38, 40, 34, 29, 2247 39, 41, 35, 30, 2248 38, 40, 34, 31, 2249 39, 41, 35, 10, 2250 38, 40, 34, 11, 2251 39, 41, 35, 12, 2252 38, 40, 34, 13, 2253 39, 41, 35, 14, 2254 38, 40, 34, 15, 2255 39, 41, 32, 16, 2256 35, 25, 33, 17, 2257 0, 63 2258 }; 2259 2260 uint32 hr3_tdm_template_56166_op2[96] = { 2261 38, 40, 34, 10, 2262 38, 40, 35, 11, 2263 38, 40, 34, 12, 2264 38, 40, 35, 13, 2265 38, 40, 34, 14, 2266 38, 40, 35, 15, 2267 38, 40, 34, 16, 2268 38, 40, 35, 17, 2269 38, 40, 34, 18, 2270 38, 40, 35, 19, 2271 38, 40, 34, 20, 2272 38, 40, 35, 21, 2273 38, 40, 34, 22, 2274 38, 40, 35, 23, 2275 38, 40, 34, 24, 2276 38, 40, 35, 25, 2277 38, 40, 34, 26, 2278 38, 40, 35, 27, 2279 38, 40, 34, 28, 2280 38, 40, 35, 29, 2281 38, 40, 0, 30, 2282 38, 40, 34, 31, 2283 38, 40, 35, 32, 2284 38, 40, 63, 33 2285 }; 2286 2287 uint32 hr3_tdm_template_56166_op2a[96] = { 2288 34, 36, 38, 10, 2289 34, 36, 39, 11, 2290 34, 36, 38, 12, 2291 34, 36, 39, 13, 2292 34, 36, 38, 14, 2293 34, 36, 39, 15, 2294 34, 36, 38, 16, 2295 34, 36, 39, 17, 2296 34, 36, 38, 18, 2297 34, 36, 39, 19, 2298 34, 36, 38, 20, 2299 34, 36, 39, 21, 2300 34, 36, 38, 22, 2301 34, 36, 39, 23, 2302 34, 36, 38, 24, 2303 34, 36, 39, 25, 2304 34, 36, 38, 26, 2305 34, 36, 39, 27, 2306 34, 36, 38, 28, 2307 34, 36, 39, 29, 2308 34, 36, 0, 30, 2309 34, 36, 38, 31, 2310 34, 36, 39, 32, 2311 34, 36, 63, 33 2312 }; 2313 2314 uint32 hr3_tdm_template_56166_op5[86] = { 2315 36, 40, 34, 19, 2316 36, 40, 38, 20, 2317 36, 40, 34, 21, 2318 36, 40, 38, 22, 2319 36, 40, 34, 23, 2320 36, 40, 38, 24, 2321 36, 40, 34, 25, 2322 36, 40, 38, 26, 2323 36, 40, 34, 27, 2324 36, 40, 38, 28, 2325 18, 17, 0, 29, 2326 36, 40, 34, 30, 2327 36, 40, 38, 31, 2328 36, 40, 34, 32, 2329 36, 40, 38, 10, 2330 36, 40, 34, 11, 2331 36, 40, 38, 12, 2332 36, 40, 34, 13, 2333 36, 40, 38, 14, 2334 36, 40, 34, 15, 2335 36, 40, 38, 16, 2336 33, 63 2337 }; 2338 2339 uint32 hr3_tdm_template_56166_op6[92] = { 2340 38, 40, 36, 13, 2341 38, 40, 36, 14, 2342 38, 40, 36, 34, 2343 38, 40, 36, 26, 2344 10, 40, 18, 34, 2345 38, 40, 36, 27, 2346 38, 40, 36, 15, 2347 38, 40, 19, 34, 2348 38, 40, 36, 28, 2349 11, 0, 20, 34, 2350 38, 40, 36, 16, 2351 38, 40, 36, 29, 2352 38, 40, 21, 34, 2353 38, 40, 36, 30, 2354 12, 63, 22, 34, 2355 38, 40, 36, 31, 2356 38, 40, 36, 32, 2357 38, 40, 23, 34, 2358 38, 40, 36, 17, 2359 38, 63, 24, 34, 2360 38, 40, 36, 33, 2361 38, 40, 36, 34, 2362 38, 40, 36, 25 2363 }; 2364 2365 2366 /* System Clock Freq (MHz) */ 2367 #define _HR3_56160_SYSTEM_FREQ (300) 2368 #define _HR3_56162_SYSTEM_FREQ (111) 2369 #define _HR3_56163_SYSTEM_FREQ (111) 2370 #define _HR3_56164_SYSTEM_FREQ (75) 2371 #define _HR3_56166_SYSTEM_FREQ (230) 2372 #define _HR3_53440_SYSTEM_FREQ (300) 2373 #define _HR3_53442_SYSTEM_FREQ (111) 2374 #define _HR3_53443_SYSTEM_FREQ (111) 2375 #define _HR3_53434_SYSTEM_FREQ (75) 2376 2377 2378 #define _HR3_MAX_TSC_COUNT (2) 2379 #define _HR3_MAX_QTC_COUNT (2) 2380 #define _HR3_MAX_QGPHY_COUNT (2) 2381 #define _HR3_PORT_COUNT_PER_TSC (4) 2382 #define _HR3_PORT_COUNT_PER_QTC (16) 2383 2384 2385 #define _HR3_QTC_SERDES_OVERRDE_NONE (0) 2386 #define _HR3_QTC_SERDES_OVERRDE_QSGMII (1) 2387 #define _HR3_QTC_SERDES_OVERRDE_SGMII (2) 2388 2389 #define _HR3_ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) 2390 2391 static const int tsc_phy_port[] = {34, 38}; 2392 static const int qtc_phy_port[] = {2, 18}; 2393 2394 2395 static int matched_devid_idx[SOC_MAX_NUM_DEVICES] = {-1}; 2396 static int _hr3_port_config_id = -1; 2397 2398 typedef struct _hr3_tsc_info_s { 2399 int port_count; 2400 uint8 valid; 2401 int phy_port_base; 2402 }_hr3_tsc_info_t; 2403 2404 typedef struct _hr3_sku_info_s { 2405 uint16 dev_id; 2406 int config_op; /* sku option */ 2407 int gphy_bypass; /* gphy_bypass_mode */ 2408 int tsc_configurable; 2409 int freq; 2410 const int *p2l_mapping; 2411 const int *speed_max; 2412 uint32 *tdm_table; 2413 int tdm_table_size; 2414 uint32 disabled_qtc_bmp; /* 2 bits: [qtc1~qtc0] */ 2415 uint32 disabled_tsc_bmp; /* 2 bits: [tsc1~tsc0] */ 2416 uint32 disabled_gphy_bmp; /* 2 bits: [gphy1~gphy0] */ 2417 int default_port_ratio[_HR3_MAX_TSC_COUNT]; 2418 int num_qsgmii_supported[_HR3_MAX_QTC_COUNT]; 2419 int num_sgmii_supported[_HR3_MAX_QTC_COUNT]; 2420 }_hr3_sku_info_t; 2421 2422 static _hr3_tsc_info_t _hr3_tsc[_HR3_MAX_TSC_COUNT]; 2423 static int _hr3_qtc_gport_port_count[_HR3_MAX_TSC_COUNT][2]; 2424 static int _hr3_qtc_serdes_override[_HR3_MAX_QTC_COUNT]; 2425 2426 2427 STATIC _hr3_sku_info_t _hr3_sku_port_config[] = { 2428 /* 56160 */ 2429 /* Option 1 */ 2430 {BCM56160_DEVICE_ID, 1, 0, 0, _HR3_56160_SYSTEM_FREQ, 2431 p2l_mapping_56160_op1, port_speed_max_56160_op1, 2432 hr3_tdm_template_56160_op1, _HR3_ARRAY_SIZE(hr3_tdm_template_56160_op1), 2433 0x0, 0x0, 0x0, 2434 {SOC_HR3_PORT_RATIO_QUAD, SOC_HR3_PORT_RATIO_QUAD}, 2435 {1, 1}, {4, 4}}, 2436 /* Option 1A */ 2437 {BCM56160_DEVICE_ID, 0x1a, 0, 0, _HR3_56160_SYSTEM_FREQ, 2438 p2l_mapping_56160_op1a, port_speed_max_56160_op1a, 2439 hr3_tdm_template_56160_op1a, _HR3_ARRAY_SIZE(hr3_tdm_template_56160_op1a), 2440 0x0, 0x0, 0x0, 2441 {SOC_HR3_PORT_RATIO_QUAD, SOC_HR3_PORT_RATIO_QUAD}, 2442 {1, 1}, {4, 4}}, 2443 /* Option 2 */ 2444 {BCM56160_DEVICE_ID, 0x2, 0, 0, _HR3_56160_SYSTEM_FREQ, 2445 p2l_mapping_56160_op2, port_speed_max_56160_op2, 2446 hr3_tdm_template_56160_op2, _HR3_ARRAY_SIZE(hr3_tdm_template_56160_op2), 2447 0x0, 0x0, 0x0, 2448 {SOC_HR3_PORT_RATIO_QUAD, SOC_HR3_PORT_RATIO_DUAL_2_2}, 2449 {1, 1}, {4, 4}}, 2450 /* Option 2A */ 2451 {BCM56160_DEVICE_ID, 0x2a, 0, 0, _HR3_56160_SYSTEM_FREQ, 2452 p2l_mapping_56160_op2a, port_speed_max_56160_op2a, 2453 hr3_tdm_template_56160_op2a, _HR3_ARRAY_SIZE(hr3_tdm_template_56160_op2a), 2454 0x0, 0x0, 0x0, 2455 {SOC_HR3_PORT_RATIO_DUAL_2_2, SOC_HR3_PORT_RATIO_QUAD}, 2456 {1, 1}, {4, 4}}, 2457 /* Option 3 */ 2458 {BCM56160_DEVICE_ID, 0x3, 0, 0, _HR3_56160_SYSTEM_FREQ, 2459 p2l_mapping_56160_op3, port_speed_max_56160_op3, 2460 hr3_tdm_template_56160_op1, _HR3_ARRAY_SIZE(hr3_tdm_template_56160_op1), 2461 0x0, 0x0, 0x0, 2462 {SOC_HR3_PORT_RATIO_QUAD, SOC_HR3_PORT_RATIO_SINGLE_XAUI}, 2463 {1, 1}, {4, 4}}, 2464 /* Option 4 */ 2465 {BCM56160_DEVICE_ID, 0x4, 0, 0, _HR3_56160_SYSTEM_FREQ, 2466 p2l_mapping_56160_op4, port_speed_max_56160_op4, 2467 hr3_tdm_template_56160_op1, _HR3_ARRAY_SIZE(hr3_tdm_template_56160_op1), 2468 0x0, 0x0, 0x0, 2469 {SOC_HR3_PORT_RATIO_SINGLE_XAUI, SOC_HR3_PORT_RATIO_SINGLE_XAUI}, 2470 {1, 1}, {4, 4}}, 2471 /* Option 5 */ 2472 {BCM56160_DEVICE_ID, 0x5, 0, 0, _HR3_56160_SYSTEM_FREQ, 2473 p2l_mapping_56160_op5, port_speed_max_56160_op5, 2474 hr3_tdm_template_56160_op5, _HR3_ARRAY_SIZE(hr3_tdm_template_56160_op5), 2475 0x0, 0x0, 0x0, 2476 {SOC_HR3_PORT_RATIO_TRI_012_1_1_2, SOC_HR3_PORT_RATIO_TRI_012_1_1_2}, 2477 {1, 1}, {4, 4}}, 2478 /* Option 6 */ 2479 {BCM56160_DEVICE_ID, 0x6, 0, 0, _HR3_56160_SYSTEM_FREQ, 2480 p2l_mapping_56160_op6, port_speed_max_56160_op6, 2481 hr3_tdm_template_56160_op6, _HR3_ARRAY_SIZE(hr3_tdm_template_56160_op6), 2482 0x0, 0x0, 0x0, 2483 {SOC_HR3_PORT_RATIO_TRI_012_1_1_2, SOC_HR3_PORT_RATIO_DUAL_2_2}, 2484 {1, 1}, {4, 4}}, 2485 /* Option 6A */ 2486 {BCM56160_DEVICE_ID, 0x6a, 0, 0, _HR3_56160_SYSTEM_FREQ, 2487 p2l_mapping_56160_op6a, port_speed_max_56160_op6a, 2488 hr3_tdm_template_56160_op6a, _HR3_ARRAY_SIZE(hr3_tdm_template_56160_op6a), 2489 0x0, 0x0, 0x0, 2490 {SOC_HR3_PORT_RATIO_DUAL_2_2, SOC_HR3_PORT_RATIO_TRI_012_1_1_2}, 2491 {1, 1}, {4, 4}}, 2492 /* Option 7 */ 2493 {BCM56160_DEVICE_ID, 0x7, 0, 0, _HR3_56160_SYSTEM_FREQ, 2494 p2l_mapping_56160_op7, port_speed_max_56160_op7, 2495 hr3_tdm_template_56160_op7, _HR3_ARRAY_SIZE(hr3_tdm_template_56160_op7), 2496 0x0, 0x0, 0x0, 2497 {SOC_HR3_PORT_RATIO_SINGLE, SOC_HR3_PORT_RATIO_SINGLE}, 2498 {1, 1}, {4, 4}}, 2499 /* Option 8 */ 2500 {BCM56160_DEVICE_ID, 0x8, 0, 0, _HR3_56160_SYSTEM_FREQ, 2501 p2l_mapping_56160_op8, port_speed_max_56160_op8, 2502 hr3_tdm_template_56160_op8, _HR3_ARRAY_SIZE(hr3_tdm_template_56160_op8), 2503 0x0, 0x0, 0x0, 2504 {SOC_HR3_PORT_RATIO_DUAL_2_2, SOC_HR3_PORT_RATIO_SINGLE}, 2505 {1, 1}, {4, 4}}, 2506 /* Option 8A */ 2507 {BCM56160_DEVICE_ID, 0x8a, 0, 0, _HR3_56160_SYSTEM_FREQ, 2508 p2l_mapping_56160_op8a, port_speed_max_56160_op8a, 2509 hr3_tdm_template_56160_op8a, _HR3_ARRAY_SIZE(hr3_tdm_template_56160_op8a), 2510 0x0, 0x0, 0x0, 2511 {SOC_HR3_PORT_RATIO_SINGLE, SOC_HR3_PORT_RATIO_DUAL_2_2}, 2512 {1, 1}, {4, 4}}, 2513 /* Option 9 */ 2514 {BCM56160_DEVICE_ID, 0x9, 0, 0, _HR3_56160_SYSTEM_FREQ, 2515 p2l_mapping_56160_op9, port_speed_max_56160_op9, 2516 hr3_tdm_template_56160_op9, _HR3_ARRAY_SIZE(hr3_tdm_template_56160_op9), 2517 0x0, 0x0, 0x0, 2518 {SOC_HR3_PORT_RATIO_DUAL_2_2, SOC_HR3_PORT_RATIO_DUAL_2_2}, 2519 {1, 1}, {4, 4}}, 2520 /* Option 9A */ 2521 {BCM56160_DEVICE_ID, 0x9a, 0, 0, _HR3_56160_SYSTEM_FREQ, 2522 p2l_mapping_56160_op9a, port_speed_max_56160_op9a, 2523 hr3_tdm_template_56160_op9a, _HR3_ARRAY_SIZE(hr3_tdm_template_56160_op9a), 2524 0x0, 0x0, 0x0, 2525 {SOC_HR3_PORT_RATIO_DUAL_2_2, SOC_HR3_PORT_RATIO_DUAL_2_2}, 2526 {1, 1}, {4, 4}}, 2527 2528 /* 56160 GPHY BYPASS */ 2529 /* Option 1 */ 2530 {BCM56160_DEVICE_ID, 0x1, 1, 0, _HR3_56160_SYSTEM_FREQ, 2531 p2l_mapping_56160_op1_gphy_bypass, port_speed_max_56160_op1_gphy_bypass, 2532 hr3_tdm_template_56160_op1_gphy_bypass, 2533 _HR3_ARRAY_SIZE(hr3_tdm_template_56160_op1_gphy_bypass), 2534 0x0, 0x0, 0x3, 2535 {SOC_HR3_PORT_RATIO_QUAD, SOC_HR3_PORT_RATIO_QUAD}, 2536 {2, 4}, {4, 4}}, 2537 /* Option 1A */ 2538 {BCM56160_DEVICE_ID, 0x1a, 1, 0, _HR3_56160_SYSTEM_FREQ, 2539 p2l_mapping_56160_op1a_gphy_bypass, port_speed_max_56160_op1a_gphy_bypass, 2540 hr3_tdm_template_56160_op1a_gphy_bypass, 2541 _HR3_ARRAY_SIZE(hr3_tdm_template_56160_op1a_gphy_bypass), 2542 0x0, 0x0, 0x3, 2543 {SOC_HR3_PORT_RATIO_QUAD, SOC_HR3_PORT_RATIO_QUAD}, 2544 {2, 4}, {4, 4}}, 2545 /* Option 2 */ 2546 {BCM56160_DEVICE_ID, 0x2, 1, 0, _HR3_56160_SYSTEM_FREQ, 2547 p2l_mapping_56160_op2_gphy_bypass, port_speed_max_56160_op2_gphy_bypass, 2548 hr3_tdm_template_56160_op2_gphy_bypass, 2549 _HR3_ARRAY_SIZE(hr3_tdm_template_56160_op2_gphy_bypass), 2550 0x0, 0x0, 0x3, 2551 {SOC_HR3_PORT_RATIO_QUAD, SOC_HR3_PORT_RATIO_DUAL_2_2}, 2552 {2, 4}, {4, 4}}, 2553 /* Option 2A */ 2554 {BCM56160_DEVICE_ID, 0x2a, 1, 0, _HR3_56160_SYSTEM_FREQ, 2555 p2l_mapping_56160_op2a_gphy_bypass, port_speed_max_56160_op2a_gphy_bypass, 2556 hr3_tdm_template_56160_op2a_gphy_bypass, 2557 _HR3_ARRAY_SIZE(hr3_tdm_template_56160_op2a_gphy_bypass), 2558 0x0, 0x0, 0x3, 2559 {SOC_HR3_PORT_RATIO_DUAL_2_2, SOC_HR3_PORT_RATIO_QUAD}, 2560 {2, 4}, {4, 4}}, 2561 /* Option 3 */ 2562 {BCM56160_DEVICE_ID, 0x3, 1, 0, _HR3_56160_SYSTEM_FREQ, 2563 p2l_mapping_56160_op3_gphy_bypass, port_speed_max_56160_op3_gphy_bypass, 2564 hr3_tdm_template_56160_op1_gphy_bypass, 2565 _HR3_ARRAY_SIZE(hr3_tdm_template_56160_op1_gphy_bypass), 2566 0x0, 0x0, 0x3, 2567 {SOC_HR3_PORT_RATIO_QUAD, SOC_HR3_PORT_RATIO_SINGLE_XAUI}, 2568 {2, 4}, {4, 4}}, 2569 /* Option 4 */ 2570 {BCM56160_DEVICE_ID, 0x4, 1, 0, _HR3_56160_SYSTEM_FREQ, 2571 p2l_mapping_56160_op4_gphy_bypass, port_speed_max_56160_op4_gphy_bypass, 2572 hr3_tdm_template_56160_op1_gphy_bypass, 2573 _HR3_ARRAY_SIZE(hr3_tdm_template_56160_op1_gphy_bypass), 2574 0x0, 0x0, 0x3, 2575 {SOC_HR3_PORT_RATIO_SINGLE_XAUI, SOC_HR3_PORT_RATIO_SINGLE_XAUI}, 2576 {2, 4}, {4, 4}}, 2577 /* Option 5 */ 2578 {BCM56160_DEVICE_ID, 0x5, 1, 0, _HR3_56160_SYSTEM_FREQ, 2579 p2l_mapping_56160_op5_gphy_bypass, port_speed_max_56160_op5_gphy_bypass, 2580 hr3_tdm_template_56160_op5_gphy_bypass, 2581 _HR3_ARRAY_SIZE(hr3_tdm_template_56160_op5_gphy_bypass), 2582 0x0, 0x0, 0x3, 2583 {SOC_HR3_PORT_RATIO_TRI_012_1_1_2, SOC_HR3_PORT_RATIO_TRI_012_1_1_2}, 2584 {2, 4}, {4, 4}}, 2585 /* Option 6 */ 2586 {BCM56160_DEVICE_ID, 0x6, 1, 0, _HR3_56160_SYSTEM_FREQ, 2587 p2l_mapping_56160_op6_gphy_bypass, port_speed_max_56160_op6_gphy_bypass, 2588 hr3_tdm_template_56160_op6_gphy_bypass, 2589 _HR3_ARRAY_SIZE(hr3_tdm_template_56160_op6_gphy_bypass), 2590 0x0, 0x0, 0x3, 2591 {SOC_HR3_PORT_RATIO_TRI_012_1_1_2, SOC_HR3_PORT_RATIO_DUAL_2_2}, 2592 {2, 4}, {4, 4}}, 2593 /* Option 6A */ 2594 {BCM56160_DEVICE_ID, 0x6a, 1, 0, _HR3_56160_SYSTEM_FREQ, 2595 p2l_mapping_56160_op6a_gphy_bypass, port_speed_max_56160_op6a_gphy_bypass, 2596 hr3_tdm_template_56160_op6a_gphy_bypass, 2597 _HR3_ARRAY_SIZE(hr3_tdm_template_56160_op6a_gphy_bypass), 2598 0x0, 0x0, 0x3, 2599 {SOC_HR3_PORT_RATIO_DUAL_2_2, SOC_HR3_PORT_RATIO_TRI_012_1_1_2}, 2600 {2, 4}, {4, 4}}, 2601 /* Option 7 */ 2602 {BCM56160_DEVICE_ID, 0x7, 1, 0, _HR3_56160_SYSTEM_FREQ, 2603 p2l_mapping_56160_op7_gphy_bypass, port_speed_max_56160_op7_gphy_bypass, 2604 hr3_tdm_template_56160_op7_gphy_bypass, 2605 _HR3_ARRAY_SIZE(hr3_tdm_template_56160_op7_gphy_bypass), 2606 0x0, 0x0, 0x3, 2607 {SOC_HR3_PORT_RATIO_SINGLE, SOC_HR3_PORT_RATIO_SINGLE}, 2608 {2, 4}, {4, 4}}, 2609 /* Option 8 */ 2610 {BCM56160_DEVICE_ID, 0x8, 1, 0, _HR3_56160_SYSTEM_FREQ, 2611 p2l_mapping_56160_op8_gphy_bypass, port_speed_max_56160_op8_gphy_bypass, 2612 hr3_tdm_template_56160_op8_gphy_bypass, 2613 _HR3_ARRAY_SIZE(hr3_tdm_template_56160_op8_gphy_bypass), 2614 0x0, 0x0, 0x3, 2615 {SOC_HR3_PORT_RATIO_DUAL_2_2, SOC_HR3_PORT_RATIO_SINGLE}, 2616 {2, 4}, {4, 4}}, 2617 /* Option 8A */ 2618 {BCM56160_DEVICE_ID, 0x8a, 1, 0, _HR3_56160_SYSTEM_FREQ, 2619 p2l_mapping_56160_op8a_gphy_bypass, port_speed_max_56160_op8a_gphy_bypass, 2620 hr3_tdm_template_56160_op8a_gphy_bypass, 2621 _HR3_ARRAY_SIZE(hr3_tdm_template_56160_op8a_gphy_bypass), 2622 0x0, 0x0, 0x3, 2623 {SOC_HR3_PORT_RATIO_SINGLE, SOC_HR3_PORT_RATIO_DUAL_2_2}, 2624 {2, 4}, {4, 4}}, 2625 /* Option 9 */ 2626 {BCM56160_DEVICE_ID, 0x9, 1, 0, _HR3_56160_SYSTEM_FREQ, 2627 p2l_mapping_56160_op9_gphy_bypass, port_speed_max_56160_op9_gphy_bypass, 2628 hr3_tdm_template_56160_op9_gphy_bypass, 2629 _HR3_ARRAY_SIZE(hr3_tdm_template_56160_op9_gphy_bypass), 2630 0x0, 0x0, 0x3, 2631 {SOC_HR3_PORT_RATIO_DUAL_2_2, SOC_HR3_PORT_RATIO_DUAL_2_2}, 2632 {2, 4}, {4, 4}}, 2633 /* Option 9A */ 2634 {BCM56160_DEVICE_ID, 0x9a, 1, 0, _HR3_56160_SYSTEM_FREQ, 2635 p2l_mapping_56160_op9a_gphy_bypass, port_speed_max_56160_op9a_gphy_bypass, 2636 hr3_tdm_template_56160_op9a_gphy_bypass, 2637 _HR3_ARRAY_SIZE(hr3_tdm_template_56160_op9a_gphy_bypass), 2638 0x0, 0x0, 0x3, 2639 {SOC_HR3_PORT_RATIO_DUAL_2_2, SOC_HR3_PORT_RATIO_DUAL_2_2}, 2640 {2, 4}, {4, 4}}, 2641 2642 /* 56162 */ 2643 /* Option 1 */ 2644 {BCM56162_DEVICE_ID, 0x1, 0, 0, _HR3_56162_SYSTEM_FREQ, 2645 p2l_mapping_56162_op1, port_speed_max_56162_op1, 2646 hr3_tdm_template_56162_op1, _HR3_ARRAY_SIZE(hr3_tdm_template_56162_op1), 2647 0x0, 0x2, 0x0, 2648 {SOC_HR3_PORT_RATIO_QUAD, -1}, 2649 {0, 2}, {0, 2}}, 2650 /* Option 1A */ 2651 {BCM56162_DEVICE_ID, 0x1a, 0, 0, _HR3_56162_SYSTEM_FREQ, 2652 p2l_mapping_56162_op1a, port_speed_max_56162_op1a, 2653 hr3_tdm_template_56162_op1a, _HR3_ARRAY_SIZE(hr3_tdm_template_56162_op1a), 2654 0x0, 0x1, 0x0, 2655 {-1, SOC_HR3_PORT_RATIO_QUAD}, 2656 {0, 2}, {0, 2}}, 2657 /* Option 2 */ 2658 {BCM56162_DEVICE_ID, 0x2, 0, 0, _HR3_56162_SYSTEM_FREQ, 2659 p2l_mapping_56162_op2, port_speed_max_56162_op2, 2660 hr3_tdm_template_56162_op2, _HR3_ARRAY_SIZE(hr3_tdm_template_56162_op2), 2661 0x0, 0x0, 0x0, 2662 {SOC_HR3_PORT_RATIO_QUAD, SOC_HR3_PORT_RATIO_DUAL_2_2}, 2663 {0, 2}, {0, 2}}, 2664 2665 /* 56162 GPHY BYPASS*/ 2666 /* Option 1 */ 2667 {BCM56162_DEVICE_ID, 0x1, 1, 0, _HR3_56162_SYSTEM_FREQ, 2668 p2l_mapping_56162_op1_gphy_bypass, port_speed_max_56162_op1_gphy_bypass, 2669 hr3_tdm_template_56162_op1_gphy_bypass, 2670 _HR3_ARRAY_SIZE(hr3_tdm_template_56162_op1_gphy_bypass), 2671 0x0, 0x2, 0x3, 2672 {SOC_HR3_PORT_RATIO_QUAD, -1}, 2673 {2, 4}, {2, 4}}, 2674 /* Option 1A */ 2675 {BCM56162_DEVICE_ID, 0x1a, 1, 0, _HR3_56162_SYSTEM_FREQ, 2676 p2l_mapping_56162_op1a_gphy_bypass, port_speed_max_56162_op1a_gphy_bypass, 2677 hr3_tdm_template_56162_op1a_gphy_bypass, 2678 _HR3_ARRAY_SIZE(hr3_tdm_template_56162_op1a_gphy_bypass), 2679 0x0, 0x1, 0x3, 2680 {-1, SOC_HR3_PORT_RATIO_QUAD}, 2681 {2, 4}, {2, 4}}, 2682 /* Option 2 */ 2683 {BCM56162_DEVICE_ID, 0x2, 1, 0, _HR3_56162_SYSTEM_FREQ, 2684 p2l_mapping_56162_op2_gphy_bypass, port_speed_max_56162_op2_gphy_bypass, 2685 hr3_tdm_template_56162_op2_gphy_bypass, 2686 _HR3_ARRAY_SIZE(hr3_tdm_template_56162_op2_gphy_bypass), 2687 0x0, 0x0, 0x3, 2688 {SOC_HR3_PORT_RATIO_QUAD, SOC_HR3_PORT_RATIO_DUAL_2_2}, 2689 {2, 4}, {2, 4}}, 2690 2691 2692 /* Huricane3 Lite */ 2693 /* 56163 */ 2694 /* Option 1 */ 2695 {BCM56163_DEVICE_ID, 0x1, 0, 0, _HR3_56163_SYSTEM_FREQ, 2696 p2l_mapping_56163_op1, port_speed_max_56163_op1, 2697 hr3_tdm_template_56163_op1, _HR3_ARRAY_SIZE(hr3_tdm_template_56163_op1), 2698 0x2, 0x0, 0x2, 2699 {SOC_HR3_PORT_RATIO_QUAD, SOC_HR3_PORT_RATIO_QUAD}, 2700 {0, 0}, {0, 0}}, 2701 /* Option 2, TSCx 4X2.5g */ 2702 {BCM56163_DEVICE_ID, 0x2, 0, 1, _HR3_56163_SYSTEM_FREQ, 2703 p2l_mapping_56163_op2, port_speed_max_56163_op2, 2704 hr3_tdm_template_56163_op2, _HR3_ARRAY_SIZE(hr3_tdm_template_56163_op2), 2705 0x2, 0x0, 0x2, 2706 {SOC_HR3_PORT_RATIO_QUAD, SOC_HR3_PORT_RATIO_QUAD}, 2707 {0, 0}, {0, 0}}, 2708 /* Option 2, TSCx XAUI */ 2709 {BCM56163_DEVICE_ID, 0x2, 0, 1, _HR3_56163_SYSTEM_FREQ, 2710 p2l_mapping_56163_op1, port_speed_max_56163_op1, 2711 hr3_tdm_template_56163_op1, _HR3_ARRAY_SIZE(hr3_tdm_template_56163_op1), 2712 0x2, 0x0, 0x2, 2713 {SOC_HR3_PORT_RATIO_SINGLE_XAUI, SOC_HR3_PORT_RATIO_SINGLE_XAUI}, 2714 {0, 0}, {0, 0}}, 2715 2716 /* 56163 GPHY BYPASS*/ 2717 /* Option 1 */ 2718 {BCM56163_DEVICE_ID, 0x1, 1, 0, _HR3_56163_SYSTEM_FREQ, 2719 p2l_mapping_56163_op1_gphy_bypass, port_speed_max_56163_op1_gphy_bypass, 2720 hr3_tdm_template_56163_op1_gphy_bypass, 2721 _HR3_ARRAY_SIZE(hr3_tdm_template_56163_op1_gphy_bypass), 2722 0x0, 0x0, 0x3, 2723 {SOC_HR3_PORT_RATIO_QUAD, SOC_HR3_PORT_RATIO_QUAD}, 2724 {0, 0}, {4, 4}}, 2725 /* Option 2, TSCx 4X2.5g */ 2726 {BCM56163_DEVICE_ID, 0x2, 1, 1, _HR3_56163_SYSTEM_FREQ, 2727 p2l_mapping_56163_op2_gphy_bypass, port_speed_max_56163_op2_gphy_bypass, 2728 hr3_tdm_template_56163_op2_gphy_bypass, 2729 _HR3_ARRAY_SIZE(hr3_tdm_template_56163_op2_gphy_bypass), 2730 0x0, 0x0, 0x3, 2731 {SOC_HR3_PORT_RATIO_QUAD, SOC_HR3_PORT_RATIO_QUAD}, 2732 {0, 0}, {4, 4}}, 2733 /* Option 2, TSCx XAUI */ 2734 {BCM56163_DEVICE_ID, 0x2, 1, 1, _HR3_56163_SYSTEM_FREQ, 2735 p2l_mapping_56163_op1_gphy_bypass, port_speed_max_56163_op1_gphy_bypass, 2736 hr3_tdm_template_56163_op1_gphy_bypass, 2737 _HR3_ARRAY_SIZE(hr3_tdm_template_56163_op1_gphy_bypass), 2738 0x0, 0x0, 0x3, 2739 {SOC_HR3_PORT_RATIO_SINGLE_XAUI, SOC_HR3_PORT_RATIO_SINGLE_XAUI}, 2740 {0, 0}, {4, 4}}, 2741 2742 /* 56164 */ 2743 {BCM56164_DEVICE_ID, -1, 0, 0, _HR3_56164_SYSTEM_FREQ, 2744 p2l_mapping_56162_op1, port_speed_max_56162_op1, 2745 hr3_tdm_template_56162_op1, _HR3_ARRAY_SIZE(hr3_tdm_template_56162_op1), 2746 0x0, 0x2, 0x0, 2747 {SOC_HR3_PORT_RATIO_QUAD, -1}, 2748 {0, 2}, {0, 2}}, 2749 2750 /* 56166 */ 2751 /* Option 1 */ 2752 {BCM56166_DEVICE_ID, 0x1, 0, 0, _HR3_56166_SYSTEM_FREQ, 2753 p2l_mapping_56166_op1, port_speed_max_56166_op1, 2754 hr3_tdm_template_56166_op1, 2755 _HR3_ARRAY_SIZE(hr3_tdm_template_56166_op1), 2756 0, 0, 0x0, 2757 {SOC_HR3_PORT_RATIO_QUAD, SOC_HR3_PORT_RATIO_QUAD}, 2758 {0, 2}, {0, 2}}, 2759 /* Option 1A */ 2760 {BCM56166_DEVICE_ID, 0x1a, 0, 0, _HR3_56166_SYSTEM_FREQ, 2761 p2l_mapping_56166_op1a, port_speed_max_56166_op1a, 2762 hr3_tdm_template_56166_op1a, 2763 _HR3_ARRAY_SIZE(hr3_tdm_template_56166_op1a), 2764 0, 0, 0x0, 2765 {SOC_HR3_PORT_RATIO_QUAD, SOC_HR3_PORT_RATIO_QUAD}, 2766 {0, 2}, {0, 2}}, 2767 /* Option 2 */ 2768 {BCM56166_DEVICE_ID, 0x2, 0, 0, _HR3_56166_SYSTEM_FREQ, 2769 p2l_mapping_56166_op2, port_speed_max_56166_op2, 2770 hr3_tdm_template_56166_op2, 2771 _HR3_ARRAY_SIZE(hr3_tdm_template_56166_op2), 2772 0, 0, 0x0, 2773 {SOC_HR3_PORT_RATIO_QUAD, SOC_HR3_PORT_RATIO_DUAL_2_2}, 2774 {0, 2}, {0, 2}}, 2775 /* Option 2A */ 2776 {BCM56166_DEVICE_ID, 0x2a, 0, 0, _HR3_56166_SYSTEM_FREQ, 2777 p2l_mapping_56166_op2a, port_speed_max_56166_op2a, 2778 hr3_tdm_template_56166_op2a, 2779 _HR3_ARRAY_SIZE(hr3_tdm_template_56166_op2a), 2780 0, 0, 0x0, 2781 {SOC_HR3_PORT_RATIO_DUAL_2_2, SOC_HR3_PORT_RATIO_QUAD}, 2782 {0, 2}, {0, 2}}, 2783 /* Option 3 */ 2784 {BCM56166_DEVICE_ID, 0x3, 0, 0, _HR3_56166_SYSTEM_FREQ, 2785 p2l_mapping_56166_op3, port_speed_max_56166_op3, 2786 hr3_tdm_template_56166_op1, 2787 _HR3_ARRAY_SIZE(hr3_tdm_template_56166_op1), 2788 0, 0, 0x0, 2789 {SOC_HR3_PORT_RATIO_QUAD, SOC_HR3_PORT_RATIO_SINGLE_XAUI}, 2790 {0, 2}, {0, 2}}, 2791 /* Option 4 */ 2792 {BCM56166_DEVICE_ID, 0x4, 0, 0, _HR3_56166_SYSTEM_FREQ, 2793 p2l_mapping_56166_op4, port_speed_max_56166_op4, 2794 hr3_tdm_template_56166_op1, 2795 _HR3_ARRAY_SIZE(hr3_tdm_template_56166_op1), 2796 0, 0, 0x0, 2797 {SOC_HR3_PORT_RATIO_SINGLE_XAUI, SOC_HR3_PORT_RATIO_SINGLE_XAUI}, 2798 {0, 2}, {0, 2}}, 2799 /* Option 5 */ 2800 {BCM56166_DEVICE_ID, 0x5, 0, 0, _HR3_56166_SYSTEM_FREQ, 2801 p2l_mapping_56166_op5, port_speed_max_56166_op5, 2802 hr3_tdm_template_56166_op5, 2803 _HR3_ARRAY_SIZE(hr3_tdm_template_56166_op5), 2804 0, 0, 0x0, 2805 {SOC_HR3_PORT_RATIO_TRI_012_1_1_2, SOC_HR3_PORT_RATIO_TRI_012_1_1_2}, 2806 {0, 2}, {0, 2}}, 2807 /* Option 6 */ 2808 {BCM56166_DEVICE_ID, 0x6, 0, 0, _HR3_56166_SYSTEM_FREQ, 2809 p2l_mapping_56166_op6, port_speed_max_56166_op6, 2810 hr3_tdm_template_56166_op6, 2811 _HR3_ARRAY_SIZE(hr3_tdm_template_56166_op6), 2812 0, 0, 0x0, 2813 {SOC_HR3_PORT_RATIO_TRI_012_1_1_2, SOC_HR3_PORT_RATIO_DUAL_2_2}, 2814 {0, 2}, {0, 2}}, 2815 2816 /* 56166 GPHY BYPASS */ 2817 /* Option 1 */ 2818 {BCM56166_DEVICE_ID, 0x1, 1, 0, _HR3_56166_SYSTEM_FREQ, 2819 p2l_mapping_56166_op1_gphy_bypass, port_speed_max_56166_op1_gphy_bypass, 2820 hr3_tdm_template_56166_op1_gphy_bypass, 2821 _HR3_ARRAY_SIZE(hr3_tdm_template_56166_op1_gphy_bypass), 2822 0x0, 0, 0x3, 2823 {SOC_HR3_PORT_RATIO_QUAD, SOC_HR3_PORT_RATIO_QUAD}, 2824 {2, 4}, {2, 4}}, 2825 /* Option 1A */ 2826 {BCM56166_DEVICE_ID, 0x1a, 1, 0, _HR3_56166_SYSTEM_FREQ, 2827 p2l_mapping_56166_op1a_gphy_bypass, port_speed_max_56166_op1a_gphy_bypass, 2828 hr3_tdm_template_56166_op1a_gphy_bypass, 2829 _HR3_ARRAY_SIZE(hr3_tdm_template_56166_op1a_gphy_bypass), 2830 0x0, 0, 0x3, 2831 {SOC_HR3_PORT_RATIO_QUAD, SOC_HR3_PORT_RATIO_QUAD}, 2832 {2, 4}, {2, 4}}, 2833 /* Option 2 */ 2834 {BCM56166_DEVICE_ID, 0x2, 1, 0, _HR3_56166_SYSTEM_FREQ, 2835 p2l_mapping_56166_op2_gphy_bypass, port_speed_max_56166_op2_gphy_bypass, 2836 hr3_tdm_template_56166_op2_gphy_bypass, 2837 _HR3_ARRAY_SIZE(hr3_tdm_template_56166_op2_gphy_bypass), 2838 0x0, 0, 0x3, 2839 {SOC_HR3_PORT_RATIO_QUAD, SOC_HR3_PORT_RATIO_DUAL_2_2}, 2840 {2, 4}, {2, 4}}, 2841 /* Option 2A */ 2842 {BCM56166_DEVICE_ID, 0x2a, 1, 0, _HR3_56166_SYSTEM_FREQ, 2843 p2l_mapping_56166_op2a_gphy_bypass, port_speed_max_56166_op2a_gphy_bypass, 2844 hr3_tdm_template_56166_op2a_gphy_bypass, 2845 _HR3_ARRAY_SIZE(hr3_tdm_template_56166_op2a_gphy_bypass), 2846 0x0, 0, 0x3, 2847 {SOC_HR3_PORT_RATIO_DUAL_2_2, SOC_HR3_PORT_RATIO_QUAD}, 2848 {2, 4}, {2, 4}}, 2849 /* Option 3 */ 2850 {BCM56166_DEVICE_ID, 0x3, 1, 0, _HR3_56166_SYSTEM_FREQ, 2851 p2l_mapping_56166_op3_gphy_bypass, port_speed_max_56166_op3_gphy_bypass, 2852 hr3_tdm_template_56166_op1_gphy_bypass, 2853 _HR3_ARRAY_SIZE(hr3_tdm_template_56166_op1_gphy_bypass), 2854 0x0, 0, 0x3, 2855 {SOC_HR3_PORT_RATIO_QUAD, SOC_HR3_PORT_RATIO_SINGLE_XAUI}, 2856 {2, 4}, {2, 4}}, 2857 /* Option 4 */ 2858 {BCM56166_DEVICE_ID, 0x4, 1, 0, _HR3_56166_SYSTEM_FREQ, 2859 p2l_mapping_56166_op4_gphy_bypass, port_speed_max_56166_op4_gphy_bypass, 2860 hr3_tdm_template_56166_op1_gphy_bypass, 2861 _HR3_ARRAY_SIZE(hr3_tdm_template_56166_op1_gphy_bypass), 2862 0x0, 0, 0x3, 2863 {SOC_HR3_PORT_RATIO_SINGLE_XAUI, SOC_HR3_PORT_RATIO_SINGLE_XAUI}, 2864 {2, 4}, {2, 4}}, 2865 /* Option 5 */ 2866 {BCM56166_DEVICE_ID, 0x5, 1, 0, _HR3_56166_SYSTEM_FREQ, 2867 p2l_mapping_56166_op5_gphy_bypass, port_speed_max_56166_op5_gphy_bypass, 2868 hr3_tdm_template_56166_op5_gphy_bypass, 2869 _HR3_ARRAY_SIZE(hr3_tdm_template_56166_op5_gphy_bypass), 2870 0x0, 0, 0x3, 2871 {SOC_HR3_PORT_RATIO_TRI_012_1_1_2, SOC_HR3_PORT_RATIO_TRI_012_1_1_2}, 2872 {2, 4}, {2, 4}}, 2873 /* Option 6 */ 2874 {BCM56166_DEVICE_ID, 0x6, 1, 0, _HR3_56166_SYSTEM_FREQ, 2875 p2l_mapping_56166_op6_gphy_bypass, port_speed_max_56166_op6_gphy_bypass, 2876 hr3_tdm_template_56166_op6_gphy_bypass, 2877 _HR3_ARRAY_SIZE(hr3_tdm_template_56166_op6_gphy_bypass), 2878 0x0, 0, 0x3, 2879 {SOC_HR3_PORT_RATIO_TRI_012_1_1_2, SOC_HR3_PORT_RATIO_DUAL_2_2}, 2880 {2, 4}, {2, 4}}, 2881 2882 2883 /* Buckhound */ 2884 /* 53440 */ 2885 /* Option 1 */ 2886 {BCM53440_DEVICE_ID, 0x1, 0, 0, _HR3_53440_SYSTEM_FREQ, 2887 p2l_mapping_56160_op5, port_speed_max_56160_op5, 2888 hr3_tdm_template_56160_op5, _HR3_ARRAY_SIZE(hr3_tdm_template_56160_op5), 2889 0x0, 0x0, 0x0, 2890 {SOC_HR3_PORT_RATIO_TRI_012_1_1_2, SOC_HR3_PORT_RATIO_TRI_012_1_1_2}, 2891 {1, 1}, {4, 4}}, 2892 /* Option 2 */ 2893 {BCM53440_DEVICE_ID, 0x2, 0, 0, _HR3_53440_SYSTEM_FREQ, 2894 p2l_mapping_56160_op6a, port_speed_max_56160_op6a, 2895 hr3_tdm_template_56160_op6a, _HR3_ARRAY_SIZE(hr3_tdm_template_56160_op6a), 2896 0x0, 0x0, 0x0, 2897 {SOC_HR3_PORT_RATIO_DUAL_2_2, SOC_HR3_PORT_RATIO_TRI_012_1_1_2}, 2898 {1, 1}, {4, 4}}, 2899 /* Option 2A */ 2900 {BCM53440_DEVICE_ID, 0x2a, 0, 0, _HR3_53440_SYSTEM_FREQ, 2901 p2l_mapping_56160_op6, port_speed_max_56160_op6, 2902 hr3_tdm_template_56160_op6, _HR3_ARRAY_SIZE(hr3_tdm_template_56160_op6), 2903 0x0, 0x0, 0x0, 2904 {SOC_HR3_PORT_RATIO_TRI_012_1_1_2, SOC_HR3_PORT_RATIO_DUAL_2_2}, 2905 {1, 1}, {4, 4}}, 2906 /* Option 3 */ 2907 {BCM53440_DEVICE_ID, 0x3, 0, 0, _HR3_53440_SYSTEM_FREQ, 2908 p2l_mapping_53440_op3, port_speed_max_53440_op3, 2909 hr3_tdm_template_53440_op3, _HR3_ARRAY_SIZE(hr3_tdm_template_53440_op3), 2910 0, 0, 0, 2911 {SOC_HR3_PORT_RATIO_QUAD, SOC_HR3_PORT_RATIO_QUAD}, 2912 {1, 1}, {4, 4}}, 2913 /* Option 4 */ 2914 {BCM53440_DEVICE_ID, 0x4, 0, 0, _HR3_53440_SYSTEM_FREQ, 2915 p2l_mapping_56160_op2a, port_speed_max_53440_op4, 2916 hr3_tdm_template_56160_op2a, _HR3_ARRAY_SIZE(hr3_tdm_template_56160_op2a), 2917 0, 0, 0, 2918 {SOC_HR3_PORT_RATIO_DUAL_2_2, SOC_HR3_PORT_RATIO_QUAD}, 2919 {1, 1}, {4, 4}}, 2920 /* Option 4A */ 2921 {BCM53440_DEVICE_ID, 0x4a, 0, 0, _HR3_53440_SYSTEM_FREQ, 2922 p2l_mapping_56160_op2, port_speed_max_53440_op4a, 2923 hr3_tdm_template_56160_op2, _HR3_ARRAY_SIZE(hr3_tdm_template_56160_op2), 2924 0, 0, 0, 2925 {SOC_HR3_PORT_RATIO_QUAD, SOC_HR3_PORT_RATIO_DUAL_2_2}, 2926 {1, 1}, {4, 4}}, 2927 /* Option 5 */ 2928 {BCM53440_DEVICE_ID, 0x5, 0, 0, _HR3_53440_SYSTEM_FREQ, 2929 p2l_mapping_56160_op3, port_speed_max_56160_op3, 2930 hr3_tdm_template_56160_op1, _HR3_ARRAY_SIZE(hr3_tdm_template_56160_op1), 2931 0x0, 0x0, 0x0, 2932 {SOC_HR3_PORT_RATIO_QUAD, SOC_HR3_PORT_RATIO_SINGLE_XAUI}, 2933 {1, 1}, {4, 4}}, 2934 /* Option 6 */ 2935 {BCM53440_DEVICE_ID, 0x6, 0, 0, _HR3_53440_SYSTEM_FREQ, 2936 p2l_mapping_56160_op4, port_speed_max_56160_op4, 2937 hr3_tdm_template_56160_op1, _HR3_ARRAY_SIZE(hr3_tdm_template_56160_op1), 2938 0x0, 0x0, 0x0, 2939 {SOC_HR3_PORT_RATIO_SINGLE_XAUI, SOC_HR3_PORT_RATIO_SINGLE_XAUI}, 2940 {1, 1}, {4, 4}}, 2941 /* Option 7 */ 2942 {BCM53440_DEVICE_ID, 0x7, 0, 0, _HR3_53440_SYSTEM_FREQ, 2943 p2l_mapping_56160_op1, port_speed_max_56160_op1, 2944 hr3_tdm_template_56160_op1, _HR3_ARRAY_SIZE(hr3_tdm_template_56160_op1), 2945 0x0, 0x0, 0x0, 2946 {SOC_HR3_PORT_RATIO_QUAD, SOC_HR3_PORT_RATIO_QUAD}, 2947 {1, 1}, {4, 4}}, 2948 /* Option 7A */ 2949 {BCM53440_DEVICE_ID, 0x7a, 0, 0, _HR3_53440_SYSTEM_FREQ, 2950 p2l_mapping_56160_op1a, port_speed_max_56160_op1a, 2951 hr3_tdm_template_56160_op1a, _HR3_ARRAY_SIZE(hr3_tdm_template_56160_op1a), 2952 0x0, 0x0, 0x0, 2953 {SOC_HR3_PORT_RATIO_QUAD, SOC_HR3_PORT_RATIO_QUAD}, 2954 {1, 1}, {4, 4}}, 2955 /* Option 8 */ 2956 {BCM53440_DEVICE_ID, 0x8, 0, 0, _HR3_53440_SYSTEM_FREQ, 2957 p2l_mapping_56160_op2, port_speed_max_56160_op2, 2958 hr3_tdm_template_56160_op2, _HR3_ARRAY_SIZE(hr3_tdm_template_56160_op2), 2959 0x0, 0x0, 0x0, 2960 {SOC_HR3_PORT_RATIO_QUAD, SOC_HR3_PORT_RATIO_DUAL_2_2}, 2961 {1, 1}, {4, 4}}, 2962 /* Option 8A */ 2963 {BCM53440_DEVICE_ID, 0x8a, 0, 0, _HR3_53440_SYSTEM_FREQ, 2964 p2l_mapping_56160_op2a, port_speed_max_56160_op2a, 2965 hr3_tdm_template_56160_op2a, _HR3_ARRAY_SIZE(hr3_tdm_template_56160_op2a), 2966 0x0, 0x0, 0x0, 2967 {SOC_HR3_PORT_RATIO_DUAL_2_2, SOC_HR3_PORT_RATIO_QUAD}, 2968 {1, 1}, {4, 4}}, 2969 2970 /* 53440 GPHY BYPASS */ 2971 /* Option 1 */ 2972 {BCM53440_DEVICE_ID, 0x1, 1, 0, _HR3_53440_SYSTEM_FREQ, 2973 p2l_mapping_56160_op5_gphy_bypass, port_speed_max_56160_op5_gphy_bypass, 2974 hr3_tdm_template_56160_op5_gphy_bypass, 2975 _HR3_ARRAY_SIZE(hr3_tdm_template_56160_op5_gphy_bypass), 2976 0x0, 0x0, 0x3, 2977 {SOC_HR3_PORT_RATIO_TRI_012_1_1_2, SOC_HR3_PORT_RATIO_TRI_012_1_1_2}, 2978 {2, 4}, {4, 4}}, 2979 /* Option 2 */ 2980 {BCM53440_DEVICE_ID, 0x2, 1, 0, _HR3_53440_SYSTEM_FREQ, 2981 p2l_mapping_56160_op6a_gphy_bypass, port_speed_max_56160_op6a_gphy_bypass, 2982 hr3_tdm_template_56160_op6a_gphy_bypass, 2983 _HR3_ARRAY_SIZE(hr3_tdm_template_56160_op6a_gphy_bypass), 2984 0x0, 0x0, 0x3, 2985 {SOC_HR3_PORT_RATIO_DUAL_2_2, SOC_HR3_PORT_RATIO_TRI_012_1_1_2}, 2986 {2, 4}, {4, 4}}, 2987 /* Option 2A */ 2988 {BCM53440_DEVICE_ID, 0x2a, 1, 0, _HR3_53440_SYSTEM_FREQ, 2989 p2l_mapping_56160_op6_gphy_bypass, port_speed_max_56160_op6_gphy_bypass, 2990 hr3_tdm_template_56160_op6_gphy_bypass, 2991 _HR3_ARRAY_SIZE(hr3_tdm_template_56160_op6_gphy_bypass), 2992 0x0, 0x0, 0x3, 2993 {SOC_HR3_PORT_RATIO_TRI_012_1_1_2, SOC_HR3_PORT_RATIO_DUAL_2_2}, 2994 {2, 4}, {4, 4}}, 2995 /* Option 3 */ 2996 {BCM53440_DEVICE_ID, 0x3, 1, 0, _HR3_53440_SYSTEM_FREQ, 2997 p2l_mapping_53440_op3_gphy_bypass, port_speed_max_53440_op3_gphy_bypass, 2998 hr3_tdm_template_53440_op3_gphy_bypass, 2999 _HR3_ARRAY_SIZE(hr3_tdm_template_53440_op3_gphy_bypass), 3000 0x0, 0x0, 0x3, 3001 {SOC_HR3_PORT_RATIO_QUAD, SOC_HR3_PORT_RATIO_QUAD}, 3002 {2, 4}, {4, 4}}, 3003 /* Option 4 */ 3004 {BCM53440_DEVICE_ID, 0x4, 1, 0, _HR3_53440_SYSTEM_FREQ, 3005 p2l_mapping_56160_op2a_gphy_bypass, port_speed_max_53440_op4_gphy_bypass, 3006 hr3_tdm_template_56160_op2a_gphy_bypass, 3007 _HR3_ARRAY_SIZE(hr3_tdm_template_56160_op2a_gphy_bypass), 3008 0x0, 0x0, 0x3, 3009 {SOC_HR3_PORT_RATIO_DUAL_2_2, SOC_HR3_PORT_RATIO_QUAD}, 3010 {2, 4}, {4, 4}}, 3011 /* Option 4A */ 3012 {BCM53440_DEVICE_ID, 0x4a, 1, 0, _HR3_53440_SYSTEM_FREQ, 3013 p2l_mapping_56160_op2_gphy_bypass, port_speed_max_53440_op4a_gphy_bypass, 3014 hr3_tdm_template_56160_op2_gphy_bypass, 3015 _HR3_ARRAY_SIZE(hr3_tdm_template_56160_op2_gphy_bypass), 3016 0x0, 0x0, 0x3, 3017 {SOC_HR3_PORT_RATIO_QUAD, SOC_HR3_PORT_RATIO_DUAL_2_2}, 3018 {2, 4}, {4, 4}}, 3019 /* Option 5 */ 3020 {BCM53440_DEVICE_ID, 0x5, 1, 0, _HR3_53440_SYSTEM_FREQ, 3021 p2l_mapping_56160_op3_gphy_bypass, port_speed_max_56160_op3_gphy_bypass, 3022 hr3_tdm_template_56160_op1_gphy_bypass, 3023 _HR3_ARRAY_SIZE(hr3_tdm_template_56160_op1_gphy_bypass), 3024 0x0, 0x0, 0x3, 3025 {SOC_HR3_PORT_RATIO_QUAD, SOC_HR3_PORT_RATIO_SINGLE_XAUI}, 3026 {2, 4}, {4, 4}}, 3027 /* Option 6 */ 3028 {BCM53440_DEVICE_ID, 0x6, 1, 0, _HR3_53440_SYSTEM_FREQ, 3029 p2l_mapping_56160_op4_gphy_bypass, port_speed_max_56160_op4_gphy_bypass, 3030 hr3_tdm_template_56160_op1_gphy_bypass, 3031 _HR3_ARRAY_SIZE(hr3_tdm_template_56160_op1_gphy_bypass), 3032 0x0, 0x0, 0x3, 3033 {SOC_HR3_PORT_RATIO_SINGLE_XAUI, SOC_HR3_PORT_RATIO_SINGLE_XAUI}, 3034 {2, 4}, {4, 4}}, 3035 /* Option 7 */ 3036 {BCM53440_DEVICE_ID, 0x7, 1, 0, _HR3_53440_SYSTEM_FREQ, 3037 p2l_mapping_56160_op1_gphy_bypass, port_speed_max_56160_op1_gphy_bypass, 3038 hr3_tdm_template_56160_op1_gphy_bypass, 3039 _HR3_ARRAY_SIZE(hr3_tdm_template_56160_op1_gphy_bypass), 3040 0x0, 0x0, 0x3, 3041 {SOC_HR3_PORT_RATIO_QUAD, SOC_HR3_PORT_RATIO_QUAD}, 3042 {2, 4}, {4, 4}}, 3043 /* Option 7A */ 3044 {BCM53440_DEVICE_ID, 0x7a, 1, 0, _HR3_53440_SYSTEM_FREQ, 3045 p2l_mapping_56160_op1a_gphy_bypass, port_speed_max_56160_op1a_gphy_bypass, 3046 hr3_tdm_template_56160_op1a_gphy_bypass, 3047 _HR3_ARRAY_SIZE(hr3_tdm_template_56160_op1a_gphy_bypass), 3048 0x0, 0x0, 0x3, 3049 {SOC_HR3_PORT_RATIO_QUAD, SOC_HR3_PORT_RATIO_QUAD}, 3050 {2, 4}, {4, 4}}, 3051 /* Option 8 */ 3052 {BCM53440_DEVICE_ID, 0x8, 1, 0, _HR3_53440_SYSTEM_FREQ, 3053 p2l_mapping_56160_op2_gphy_bypass, port_speed_max_56160_op2_gphy_bypass, 3054 hr3_tdm_template_56160_op2_gphy_bypass, 3055 _HR3_ARRAY_SIZE(hr3_tdm_template_56160_op2_gphy_bypass), 3056 0x0, 0x0, 0x3, 3057 {SOC_HR3_PORT_RATIO_QUAD, SOC_HR3_PORT_RATIO_DUAL_2_2}, 3058 {2, 4}, {4, 4}}, 3059 /* Option 8A */ 3060 {BCM53440_DEVICE_ID, 0x8a, 1, 0, _HR3_53440_SYSTEM_FREQ, 3061 p2l_mapping_56160_op2a_gphy_bypass, port_speed_max_56160_op2a_gphy_bypass, 3062 hr3_tdm_template_56160_op2a_gphy_bypass, 3063 _HR3_ARRAY_SIZE(hr3_tdm_template_56160_op2a_gphy_bypass), 3064 0x0, 0x0, 0x3, 3065 {SOC_HR3_PORT_RATIO_DUAL_2_2, SOC_HR3_PORT_RATIO_QUAD}, 3066 {2, 4}, {4, 4}}, 3067 3068 /* 53442 */ 3069 /* Option 1 */ 3070 {BCM53442_DEVICE_ID, 0x1, 0, 0, _HR3_53442_SYSTEM_FREQ, 3071 p2l_mapping_56162_op1, port_speed_max_56162_op1, 3072 hr3_tdm_template_56162_op1, _HR3_ARRAY_SIZE(hr3_tdm_template_56162_op1), 3073 0x0, 0x2, 0x0, 3074 {SOC_HR3_PORT_RATIO_QUAD, -1}, 3075 {0, 2}, {0, 2}}, 3076 /* Option 1A */ 3077 {BCM53442_DEVICE_ID, 0x1a, 0, 0, _HR3_53442_SYSTEM_FREQ, 3078 p2l_mapping_56162_op1a, port_speed_max_56162_op1a, 3079 hr3_tdm_template_56162_op1a, _HR3_ARRAY_SIZE(hr3_tdm_template_56162_op1a), 3080 0x0, 0x1, 0x0, 3081 {-1, SOC_HR3_PORT_RATIO_QUAD}, 3082 {0, 2}, {0, 2}}, 3083 /* Option 2 */ 3084 {BCM53442_DEVICE_ID, 0x2, 0, 0, _HR3_53442_SYSTEM_FREQ, 3085 p2l_mapping_56162_op2, port_speed_max_56162_op2, 3086 hr3_tdm_template_56162_op2, _HR3_ARRAY_SIZE(hr3_tdm_template_56162_op2), 3087 0x0, 0x0, 0x0, 3088 {SOC_HR3_PORT_RATIO_QUAD, SOC_HR3_PORT_RATIO_DUAL_2_2}, 3089 {0, 2}, {0, 2}}, 3090 /* 53442 GPHY BYPASS */ 3091 /* Option 1 */ 3092 {BCM53442_DEVICE_ID, 0x1, 1, 0, _HR3_53442_SYSTEM_FREQ, 3093 p2l_mapping_56162_op1_gphy_bypass, port_speed_max_56162_op1_gphy_bypass, 3094 hr3_tdm_template_56162_op1_gphy_bypass, 3095 _HR3_ARRAY_SIZE(hr3_tdm_template_56162_op1_gphy_bypass), 3096 0x0, 0x2, 0x3, 3097 {SOC_HR3_PORT_RATIO_QUAD, -1}, 3098 {2, 4}, {2, 4}}, 3099 /* Option 1A */ 3100 {BCM53442_DEVICE_ID, 0x1a, 1, 0, _HR3_53442_SYSTEM_FREQ, 3101 p2l_mapping_56162_op1a_gphy_bypass, port_speed_max_56162_op1a_gphy_bypass, 3102 hr3_tdm_template_56162_op1a_gphy_bypass, 3103 _HR3_ARRAY_SIZE(hr3_tdm_template_56162_op1a_gphy_bypass), 3104 0x0, 0x1, 0x3, 3105 {-1, SOC_HR3_PORT_RATIO_QUAD}, 3106 {2, 4}, {2, 4}}, 3107 /* Option 2 */ 3108 {BCM53442_DEVICE_ID, 0x2, 1, 0, _HR3_53442_SYSTEM_FREQ, 3109 p2l_mapping_56162_op2_gphy_bypass, port_speed_max_56162_op2_gphy_bypass, 3110 hr3_tdm_template_56162_op2_gphy_bypass, 3111 _HR3_ARRAY_SIZE(hr3_tdm_template_56162_op2_gphy_bypass), 3112 0x0, 0x0, 0x3, 3113 {SOC_HR3_PORT_RATIO_QUAD, SOC_HR3_PORT_RATIO_DUAL_2_2}, 3114 {2, 4}, {2, 4}}, 3115 3116 /* 53443 */ 3117 /* Option 1 */ 3118 {BCM53443_DEVICE_ID, 0x1, 0, 0, _HR3_53443_SYSTEM_FREQ, 3119 p2l_mapping_56163_op1, port_speed_max_56163_op1, 3120 hr3_tdm_template_56163_op1, _HR3_ARRAY_SIZE(hr3_tdm_template_56163_op1), 3121 0x2, 0x0, 0x2, 3122 {SOC_HR3_PORT_RATIO_QUAD, SOC_HR3_PORT_RATIO_QUAD}, 3123 {0, 0}, {0, 0}}, 3124 /* Option 2, TSCx 4X2.5G */ 3125 {BCM53443_DEVICE_ID, 0x2, 0, 1, _HR3_53443_SYSTEM_FREQ, 3126 p2l_mapping_56163_op2, port_speed_max_56163_op2, 3127 hr3_tdm_template_56163_op2, _HR3_ARRAY_SIZE(hr3_tdm_template_56163_op2), 3128 0x2, 0x0, 0x2, 3129 {SOC_HR3_PORT_RATIO_QUAD, SOC_HR3_PORT_RATIO_QUAD}, 3130 {0, 0}, {0, 0}}, 3131 /* Option 2, TSCx XAUI */ 3132 {BCM53443_DEVICE_ID, 0x2, 0, 1, _HR3_53443_SYSTEM_FREQ, 3133 p2l_mapping_56163_op1, port_speed_max_56163_op1, 3134 hr3_tdm_template_56163_op1, _HR3_ARRAY_SIZE(hr3_tdm_template_56163_op1), 3135 0x2, 0x0, 0x2, 3136 {SOC_HR3_PORT_RATIO_SINGLE_XAUI, SOC_HR3_PORT_RATIO_SINGLE_XAUI}, 3137 {0, 0}, {0, 0}}, 3138 3139 /* 53443 GPHY BYPASS*/ 3140 /* Option 1 */ 3141 {BCM53443_DEVICE_ID, 0x1, 1, 0, _HR3_53443_SYSTEM_FREQ, 3142 p2l_mapping_56163_op1_gphy_bypass, port_speed_max_56163_op1_gphy_bypass, 3143 hr3_tdm_template_56163_op1_gphy_bypass, 3144 _HR3_ARRAY_SIZE(hr3_tdm_template_56163_op1_gphy_bypass), 3145 0x0, 0x0, 0x3, 3146 {SOC_HR3_PORT_RATIO_QUAD, SOC_HR3_PORT_RATIO_QUAD}, 3147 {0, 0}, {4, 4}}, 3148 /* Option 2, TSCx 4X2.5G */ 3149 {BCM53443_DEVICE_ID, 0x2, 1, 1, _HR3_53443_SYSTEM_FREQ, 3150 p2l_mapping_56163_op2_gphy_bypass, port_speed_max_56163_op2_gphy_bypass, 3151 hr3_tdm_template_56163_op2_gphy_bypass, 3152 _HR3_ARRAY_SIZE(hr3_tdm_template_56163_op2_gphy_bypass), 3153 0x0, 0x0, 0x3, 3154 {SOC_HR3_PORT_RATIO_QUAD, SOC_HR3_PORT_RATIO_QUAD}, 3155 {0, 0}, {4, 4}}, 3156 /* Option 2, TSCx XAUI */ 3157 {BCM53443_DEVICE_ID, 0x2, 1, 1, _HR3_53443_SYSTEM_FREQ, 3158 p2l_mapping_56163_op1_gphy_bypass, port_speed_max_56163_op1_gphy_bypass, 3159 hr3_tdm_template_56163_op1_gphy_bypass, 3160 _HR3_ARRAY_SIZE(hr3_tdm_template_56163_op1_gphy_bypass), 3161 0x0, 0x0, 0x3, 3162 {SOC_HR3_PORT_RATIO_SINGLE_XAUI, SOC_HR3_PORT_RATIO_SINGLE_XAUI}, 3163 {0, 0}, {4, 4}}, 3164 3165 /* 53434 */ 3166 {BCM53434_DEVICE_ID, -1, 0, 0, _HR3_53434_SYSTEM_FREQ, 3167 p2l_mapping_56162_op1, port_speed_max_53434, 3168 hr3_tdm_template_56162_op1, _HR3_ARRAY_SIZE(hr3_tdm_template_56162_op1), 3169 0x0, 0x3, 0x0, 3170 {-1, -1}, 3171 {0, 2}, {0, 2}}, 3172 3173 {0,0,0,0,0,0,0,0,0,0,0,0,{-1,-1}, {0, 0}, {0, 0}}, 3174 }; 3175 3176 /* MMU related */ 3177 /* Hurricane3 uses 2MB of internal Buffers */ 3178 #define HR3_MMU_BUFFER_SIZE_2MB (2 * 1024 * 1024) 3179 /* Foxhound2 uses 512KB of internal Buffers */ 3180 #define FH2_MMU_BUFFER_SIZE_512KB (512 * 1024) 3181 3182 /* 24GE + 4HG +1CPU ports */ 3183 #define HR3_MMU_TOTAL_PORTS 29 3184 3185 #define HR3_MMU_NUM_COS 8 3186 #define HR3_MMU_CELL_SIZE 128 3187 3188 #define HR3_MMU_IN_COS_MIN_CELLS 16 3189 3190 #define HR3_MMU_IN_COS_MIN_XQS 16 3191 #define FH2_MMU_IN_COS_MIN_XQS 8 3192 3193 #define HR3_MMU_IN_XOFF_PKT 12 3194 3195 /* cos(8) * reserved cells */ 3196 #define HR3_MMU_IN_PORT_STATIC_CELLS (HR3_MMU_NUM_COS * HR3_MMU_IN_COS_MIN_CELLS) 3197 3198 /* Every port has 6K packet pointers(XQs) */ 3199 /* #define HR3_MMU_IN_PORT_TOTAL_XQS 6144 */ 3200 /* The value should be provided by desigh team, change it to 1536 temporarily. */ 3201 #define HR3_MMU_IN_PORT_TOTAL_XQS 1536 3202 /* number of cos(8) * minimum xqs per cos */ 3203 #define HR3_MMU_IN_PORT_STATIC_XQS (HR3_MMU_NUM_COS * HR3_MMU_IN_COS_MIN_XQS) 3204 #define FH2_MMU_IN_PORT_STATIC_XQS (HR3_MMU_NUM_COS * FH2_MMU_IN_COS_MIN_XQS) 3205 /* total xqs (8192)- static xqs */ 3206 #define HR3_MMU_IN_PORT_DYNAMIC_XQS (HR3_MMU_IN_PORT_TOTAL_XQS - HR3_MMU_IN_PORT_STATIC_XQS) 3207 #define FH2_MMU_IN_PORT_DYNAMIC_XQS (HR3_MMU_IN_PORT_TOTAL_XQS - FH2_MMU_IN_PORT_STATIC_XQS) 3208 3209 #define _SOC_HR3_MMU_IPMC_GROUP_MAX 32 3210 static soc_mem_t ipmc_mems[_SOC_HR3_MMU_IPMC_GROUP_MAX] = { 3211 INVALIDm, INVALIDm, 3212 MMU_IPMC_GROUP_TBL2m, MMU_IPMC_GROUP_TBL3m, 3213 MMU_IPMC_GROUP_TBL4m, MMU_IPMC_GROUP_TBL5m, 3214 MMU_IPMC_GROUP_TBL6m, MMU_IPMC_GROUP_TBL7m, 3215 MMU_IPMC_GROUP_TBL8m, MMU_IPMC_GROUP_TBL9m, 3216 MMU_IPMC_GROUP_TBL10m, MMU_IPMC_GROUP_TBL11m, 3217 MMU_IPMC_GROUP_TBL12m, MMU_IPMC_GROUP_TBL13m, 3218 MMU_IPMC_GROUP_TBL14m, MMU_IPMC_GROUP_TBL15m, 3219 MMU_IPMC_GROUP_TBL16m, MMU_IPMC_GROUP_TBL17m, 3220 MMU_IPMC_GROUP_TBL18m, MMU_IPMC_GROUP_TBL19m, 3221 MMU_IPMC_GROUP_TBL20m, MMU_IPMC_GROUP_TBL21m, 3222 MMU_IPMC_GROUP_TBL22m, MMU_IPMC_GROUP_TBL23m, 3223 MMU_IPMC_GROUP_TBL24m, MMU_IPMC_GROUP_TBL25m, 3224 MMU_IPMC_GROUP_TBL26m, MMU_IPMC_GROUP_TBL27m, 3225 MMU_IPMC_GROUP_TBL28m, MMU_IPMC_GROUP_TBL29m, 3226 MMU_IPMC_GROUP_TBL30m, MMU_IPMC_GROUP_TBL31m 3227 }; 3228 3229 static int 3230 soc_hurricane3_pipe_mem_clear(int unit) 3231 { 3232 uint32 rval; 3233 int pipe_init_usec, index; 3234 soc_timeout_t to; 3235 static const struct { 3236 soc_mem_t mem; 3237 uint32 skip_flags; /* always skip on QUICKTURN or XGSSIM */ 3238 } cam_list[] = { 3239 { CPU_COS_MAPm, BOOT_F_PLISIM }, 3240 { EFP_TCAMm, BOOT_F_PLISIM }, 3241 { FP_GLOBAL_MASK_TCAMm, BOOT_F_PLISIM }, 3242 { FP_TCAMm, BOOT_F_PLISIM }, 3243 { L2_USER_ENTRYm, BOOT_F_PLISIM }, 3244 { L2_USER_ENTRY_ONLYm, BOOT_F_PLISIM }, 3245 { L3_DEFIPm, BOOT_F_PLISIM }, 3246 { L3_DEFIP_ONLYm, BOOT_F_PLISIM }, 3247 { VFP_TCAMm, BOOT_F_PLISIM }, 3248 { VLAN_SUBNETm, 0 },/* VLAN API needs all 0 mask */ 3249 { VLAN_SUBNET_ONLYm, 0 } 3250 }; 3251 3252 /* 3253 * Reset the IPIPE and EPIPE block 3254 */ 3255 rval = 0; 3256 SOC_IF_ERROR_RETURN(WRITE_ING_HW_RESET_CONTROL_1r(unit, rval)); 3257 soc_reg_field_set(unit, ING_HW_RESET_CONTROL_2r, &rval, RESET_ALLf, 1); 3258 soc_reg_field_set(unit, ING_HW_RESET_CONTROL_2r, &rval, VALIDf, 1); 3259 /* Set count to # entries in largest IPIPE table, L2_ENTRYm */ 3260 soc_reg_field_set(unit, ING_HW_RESET_CONTROL_2r, &rval, COUNTf, 0x4000); 3261 SOC_IF_ERROR_RETURN(WRITE_ING_HW_RESET_CONTROL_2r(unit, rval)); 3262 3263 rval = 0; 3264 SOC_IF_ERROR_RETURN(WRITE_EGR_HW_RESET_CONTROL_0r(unit, rval)); 3265 soc_reg_field_set(unit, EGR_HW_RESET_CONTROL_1r, &rval, RESET_ALLf, 1); 3266 soc_reg_field_set(unit, EGR_HW_RESET_CONTROL_1r, &rval, VALIDf, 1); 3267 /* Set count to # entries in largest EPIPE table, EGR_GPP_ATTRIBUTESm */ 3268 soc_reg_field_set(unit, EGR_HW_RESET_CONTROL_1r, &rval, COUNTf, 0x2000); 3269 SOC_IF_ERROR_RETURN(WRITE_EGR_HW_RESET_CONTROL_1r(unit, rval)); 3270 3271 /* For simulation, set timeout to 10 sec. Otherwise, timeout = 50 ms */ 3272 if (SAL_BOOT_SIMULATION) { 3273 pipe_init_usec = 10000000; 3274 } else { 3275 pipe_init_usec = 50000; 3276 } 3277 soc_timeout_init(&to, pipe_init_usec, 0); 3278 3279 /* Wait for IPIPE memory initialization done. */ 3280 do { 3281 SOC_IF_ERROR_RETURN(READ_ING_HW_RESET_CONTROL_2r(unit, &rval)); 3282 if (soc_reg_field_get(unit, ING_HW_RESET_CONTROL_2r, rval, DONEf)) { 3283 break; 3284 } 3285 if (soc_timeout_check(&to)) { 3286 LOG_WARN(BSL_LS_SOC_COMMON, 3287 (BSL_META_U(unit, 3288 "unit %d : ING_HW_RESET timeout\n"), unit)); 3289 break; 3290 } 3291 } while (TRUE); 3292 3293 /* Wait for EPIPE memory initialization done. */ 3294 do { 3295 SOC_IF_ERROR_RETURN(READ_EGR_HW_RESET_CONTROL_1r(unit, &rval)); 3296 if (soc_reg_field_get(unit, EGR_HW_RESET_CONTROL_1r, rval, DONEf)) { 3297 break; 3298 } 3299 if (soc_timeout_check(&to)) { 3300 LOG_WARN(BSL_LS_SOC_COMMON, 3301 (BSL_META_U(unit, "unit %d : EGR_HW_RESET timeout\n"), unit)); 3302 break; 3303 } 3304 } while (TRUE); 3305 3306 rval = 0; 3307 SOC_IF_ERROR_RETURN(WRITE_ING_HW_RESET_CONTROL_2r(unit, rval)); 3308 SOC_IF_ERROR_RETURN(WRITE_EGR_HW_RESET_CONTROL_1r(unit, rval)); 3309 3310 if (!SAL_BOOT_SIMULATION || SAL_BOOT_BCMSIM) { 3311 /* TCAM tables are not handled by hardware reset control */ 3312 for (index = 0; index < sizeof(cam_list) / sizeof(cam_list[0]); 3313 index++) { 3314 if (sal_boot_flags_get() & cam_list[index].skip_flags) { 3315 continue; 3316 } 3317 if (((cam_list[index].mem == EFP_TCAMm) || 3318 (cam_list[index].mem == VFP_TCAMm)) && 3319 (!soc_feature(unit, soc_feature_field_multi_stage))) { 3320 continue; 3321 } 3322 SOC_IF_ERROR_RETURN 3323 (soc_mem_clear(unit, cam_list[index].mem, COPYNO_ALL, TRUE)); 3324 } 3325 3326 /* MMU_IPMC_VLAN_TBL */ 3327 SOC_IF_ERROR_RETURN 3328 (soc_mem_clear(unit, MMU_IPMC_VLAN_TBLm, COPYNO_ALL, TRUE)); 3329 3330 /* MMU_IPMC_GROUP_TBLn : n is 2 ~ 31 in HR3 */ 3331 for (index = 0; index < _SOC_HR3_MMU_IPMC_GROUP_MAX; index++) { 3332 if (ipmc_mems[index] != INVALIDm) { 3333 SOC_IF_ERROR_RETURN(soc_mem_clear(unit, 3334 ipmc_mems[index], COPYNO_ALL, TRUE)); 3335 } 3336 } 3337 3338 } 3339 3340 return SOC_E_NONE; 3341 } 3342 3343 /* 3344 * Function: 3345 * soc_hurricane3_chip_sku_get 3346 * Purpose: 3347 * Get the chip sku 3348 * Parameters : 3349 * sku - (OUT)Hurricane3 chip sku(SOC_HR3_SKU_XXX) 3350 */ 3351 int 3352 soc_hurricane3_chip_sku_get(int unit, int *sku) 3353 { 3354 uint16 dev_id; 3355 uint8 rev_id; 3356 3357 soc_cm_get_id(unit, &dev_id, &rev_id); 3358 3359 if (((dev_id & 0x00FF) == 0x0060) || ((dev_id & 0x00FF) == 0x0062)) { 3360 /* Hurricane3 (56160, 56162) */ 3361 *sku = SOC_HR3_SKU_HURRICANE3; 3362 } else if (((dev_id & 0x00FF) == 0x0063) || ((dev_id & 0x00FF) == 0x0064) || 3363 ((dev_id & 0x00FF) == 0x0066)) { 3364 /* Hurricane3Lite (56163, 56164, 56166) */ 3365 *sku = SOC_HR3_SKU_HURRICANE3LITE; 3366 } else if ((dev_id & 0x00F0) == 0x0040) { 3367 /* Buckhound (53440, 53442, 53443) */ 3368 *sku = SOC_HR3_SKU_BUCKHOUND; 3369 } else if ((dev_id & 0x00F0) == 0x0030) { 3370 /* Foxhound2 (53434) */ 3371 *sku = SOC_HR3_SKU_FOXHOUND2; 3372 } else { 3373 *sku = -1; 3374 return SOC_E_BADID; 3375 } 3376 3377 return SOC_E_NONE; 3378 } 3379 3380 int 3381 _soc_hr3_process_l2_overflow(int unit) 3382 { 3383 uint32 ip1_rval, l2_no_learn, ovf_no_learn; 3384 3385 if (SOC_CONTROL(unit)->l2_overflow_enable) { 3386 SOC_IF_ERROR_RETURN(soc_reg32_get( 3387 unit, IP1_INTR_STATUSr, REG_PORT_ANY, 0, &ip1_rval)); 3388 l2_no_learn = soc_reg_field_get(unit, IP1_INTR_STATUSr, 3389 ip1_rval, L2_ENTRY_NO_LEARN_INTRf); 3390 ovf_no_learn = soc_reg_field_get(unit, IP1_INTR_STATUSr, 3391 ip1_rval, L2_ENTRY_OVF_NO_LEARN_INTRf); 3392 if (SOC_CONTROL(unit)->l2_overflow_bucket_enable) { 3393 if (ovf_no_learn) { 3394 /* report overflow event */ 3395 soc_hr3_l2_overflow_interrupt_handler(unit); 3396 } 3397 } else { 3398 if (l2_no_learn) { 3399 /* report overflow event */ 3400 soc_hr3_l2_overflow_interrupt_handler(unit); 3401 } 3402 } 3403 /* Enable interrupt */ 3404 SOC_IF_ERROR_RETURN(soc_hr3_l2_overflow_intr_enable(unit)); 3405 } 3406 3407 return SOC_E_NONE; 3408 } 3409 3410 #define CMIC_PARITY_IP1_TO_CMIC_PERR_INTR_BIT 0x0008 3411 3412 STATIC soc_hr3_oam_ser_handler_t hr3_oam_ser_handler[SOC_MAX_NUM_DEVICES] = {NULL}; 3413 3414 void 3415 soc_hr3_oam_ser_handler_register(int unit, soc_hr3_oam_ser_handler_t handler) 3416 { 3417 hr3_oam_ser_handler[unit] = handler; 3418 } 3419 3420 int 3421 soc_hr3_oam_ser_process(int unit, soc_mem_t mem, int index) 3422 { 3423 void *null_entry = NULL; 3424 int rv = SOC_E_NONE; 3425 3426 if (hr3_oam_ser_handler[unit]) { 3427 return hr3_oam_ser_handler[unit](unit, mem, index); 3428 } else { 3429 /* Clear the entry of MA_STATE and REMP memories */ 3430 null_entry = soc_mem_entry_null(unit, mem); 3431 if ((rv = soc_mem_write(unit, mem, MEM_BLOCK_ALL, index, null_entry)) < 0) { 3432 LOG_ERROR(BSL_LS_SOC_COMMON, 3433 (BSL_META_U(unit, 3434 "OAM SER ENTRY_CLEAR failed for %s[%d]: %s\n"), 3435 SOC_MEM_NAME(unit, mem), 3436 index, soc_errmsg(rv))); 3437 return rv; 3438 } 3439 soc_event_generate(unit, SOC_SWITCH_EVENT_PARITY_ERROR, 3440 SOC_SWITCH_EVENT_DATA_ERROR_CORRECTED, mem, index); 3441 LOG_ERROR(BSL_LS_SOC_COMMON, 3442 (BSL_META_U(unit, 3443 "OAM SER ENTRY_CLEAR: %s[%d] index %d\n"), 3444 SOC_MEM_NAME(unit, mem), mem, index)); 3445 return rv; 3446 } 3447 } 3448 3449 STATIC soc_hr3_oam_handler_t hr3_oam_handler[SOC_MAX_NUM_DEVICES] = {NULL}; 3450 3451 soc_field_t _soc_hr3_oam_interrupt_fields[] = { 3452 SOME_RDI_DEFECT_INTRf, 3453 SOME_RMEP_CCM_DEFECT_INTRf, 3454 ERROR_CCM_DEFECT_INTRf, 3455 ANY_RMEP_TLV_PORT_DOWN_INTRf, 3456 ANY_RMEP_TLV_PORT_UP_INTRf, 3457 ANY_RMEP_TLV_INTERFACE_DOWN_INTRf, 3458 ANY_RMEP_TLV_INTERFACE_UP_INTRf, 3459 XCON_CCM_DEFECT_INTRf, 3460 INVALIDf 3461 }; 3462 3463 static int 3464 _soc_hr3_oam_interrupt_control(int unit, soc_field_t field, int enable) 3465 { 3466 3467 uint32 rval; 3468 int fidx = 0; 3469 3470 SOC_IF_ERROR_RETURN(READ_IP1_INTR_ENABLEr(unit, &rval)); 3471 if (field == INVALIDf){ 3472 while (_soc_hr3_oam_interrupt_fields[fidx] != INVALIDf) { 3473 soc_reg_field_set(unit, IP1_INTR_ENABLEr, &rval, 3474 _soc_hr3_oam_interrupt_fields[fidx], 3475 enable ? 1 : 0); 3476 fidx++; 3477 } 3478 } else { 3479 if (soc_reg_field_valid(unit, IP1_INTR_ENABLEr, field)) { 3480 soc_reg_field_set(unit, IP1_INTR_ENABLEr, &rval, 3481 field, enable ? 1 : 0); 3482 } else { 3483 return SOC_E_PARAM; 3484 } 3485 } 3486 SOC_IF_ERROR_RETURN(WRITE_IP1_INTR_ENABLEr(unit, rval)); 3487 return SOC_E_NONE; 3488 } 3489 3490 void 3491 soc_hr3_oam_handler_register(int unit, soc_hr3_oam_handler_t handler) 3492 { 3493 hr3_oam_handler[unit] = handler; 3494 3495 /* Enable oam interrupt */ 3496 _soc_hr3_oam_interrupt_control(unit, INVALIDf, 1); 3497 /* Write CMIC enable register */ 3498 (void)soc_cmicm_intr3_enable( 3499 unit, CMIC_PARITY_IP1_TO_CMIC_PERR_INTR_BIT); 3500 3501 } 3502 3503 int 3504 soc_hr3_process_oam_interrupt(int unit) 3505 { 3506 uint32 rval; 3507 int fidx = 0; 3508 soc_hr3_oam_handler_t oam_handler_snapshot = hr3_oam_handler[unit]; 3509 3510 3511 SOC_IF_ERROR_RETURN(READ_IP1_INTR_STATUSr(unit, &rval)); 3512 3513 while (_soc_hr3_oam_interrupt_fields[fidx] != INVALIDf) { 3514 if (soc_reg_field_get(unit, IP1_INTR_STATUSr, rval, 3515 _soc_hr3_oam_interrupt_fields[fidx])) { 3516 if (oam_handler_snapshot != NULL) 3517 { 3518 (void)(oam_handler_snapshot(unit, 3519 _soc_hr3_oam_interrupt_fields[fidx])); 3520 } 3521 } 3522 fidx++; 3523 } 3524 3525 return SOC_E_NONE; 3526 } 3527 3528 3529 #define HR3_NUM_COS 8 3530 int soc_hr3_xq_mem(int unit, soc_port_t port, soc_mem_t *xq) 3531 { 3532 soc_mem_t xq_mems[] = { MMU_XQ0m, 3533 MMU_XQ1m, 3534 MMU_XQ2m, 3535 MMU_XQ3m, 3536 MMU_XQ4m, 3537 MMU_XQ5m, 3538 MMU_XQ6m, 3539 MMU_XQ7m, 3540 MMU_XQ8m, 3541 MMU_XQ9m, 3542 MMU_XQ10m, 3543 MMU_XQ11m, 3544 MMU_XQ12m, 3545 MMU_XQ13m, 3546 MMU_XQ14m, 3547 MMU_XQ15m, 3548 MMU_XQ16m, 3549 MMU_XQ17m, 3550 MMU_XQ18m, 3551 MMU_XQ19m, 3552 MMU_XQ20m, 3553 MMU_XQ21m, 3554 MMU_XQ22m, 3555 MMU_XQ23m, 3556 MMU_XQ24m, 3557 MMU_XQ25m, 3558 MMU_XQ26m, 3559 MMU_XQ27m, 3560 MMU_XQ28m, 3561 MMU_XQ29m 3562 }; 3563 int max_port; 3564 max_port = sizeof(xq_mems) / sizeof(xq_mems[0]); 3565 if (port >= max_port) { 3566 return(SOC_E_PORT); 3567 } 3568 *xq = xq_mems[port]; 3569 return(SOC_E_NONE); 3570 } 3571 3572 3573 int 3574 soc_hurricane3_init_port_mapping(int unit) 3575 { 3576 soc_info_t *si; 3577 soc_mem_t mem; 3578 uint32 rval; 3579 ing_physical_to_logical_port_number_mapping_table_entry_t entry; 3580 int port, phy_port; 3581 int num_port, num_phy_port; 3582 3583 si = &SOC_INFO(unit); 3584 3585 /* Ingress physical to logical port mapping */ 3586 mem = ING_PHYSICAL_TO_LOGICAL_PORT_NUMBER_MAPPING_TABLEm; 3587 num_phy_port = soc_mem_index_count(unit, mem); 3588 sal_memset(&entry, 0, sizeof(entry)); 3589 for (phy_port = 0; phy_port < num_phy_port; phy_port++) { 3590 port = si->port_p2l_mapping[phy_port]; 3591 soc_mem_field32_set(unit, mem, &entry, LOGICAL_PORT_NUMBERf, 3592 port == -1 ? 0x30 : port); 3593 SOC_IF_ERROR_RETURN 3594 (soc_mem_write(unit, mem, MEM_BLOCK_ALL, phy_port, &entry)); 3595 } 3596 num_port = soc_mem_index_count(unit, PORT_TABm); 3597 3598 /* Egress logical to physical port mapping */ 3599 for (port = 0; port < num_port; port++) { 3600 phy_port = si->port_l2p_mapping[port]; 3601 rval = 0; 3602 soc_reg_field_set(unit, EGR_LOGICAL_TO_PHYSICAL_PORT_NUMBER_MAPPINGr, 3603 &rval, PHYSICAL_PORT_NUMBERf, 3604 phy_port == -1 ? 0x3f : phy_port); 3605 SOC_IF_ERROR_RETURN 3606 (WRITE_EGR_LOGICAL_TO_PHYSICAL_PORT_NUMBER_MAPPINGr(unit, port, 3607 rval)); 3608 } 3609 /* MMU logical to physical port mapping */ 3610 /*(Here, Same as Egress logical to physical port mapping) */ 3611 for (port = 0; port < num_port; port++) { 3612 phy_port = si->port_m2p_mapping[port]; 3613 if (phy_port != -1) { 3614 rval = 0; 3615 soc_reg_field_set(unit, LOG_TO_PHY_PORT_MAPPINGr, &rval, 3616 PHY_PORTf, phy_port); 3617 SOC_IF_ERROR_RETURN 3618 (WRITE_LOG_TO_PHY_PORT_MAPPINGr(unit, port, rval)); 3619 } 3620 } 3621 3622 return SOC_E_NONE; 3623 } 3624 3625 STATIC int 3626 _soc_hr3_tsc_config_supported(int unit, int sku_config_idx) 3627 { 3628 int i; 3629 char *propval; 3630 3631 for (i = 0; i <_HR3_MAX_TSC_COUNT; i++) { 3632 propval = soc_property_suffix_num_str_get(unit, i, 3633 spn_BCM5616X_INIT_PORT_CONFIG, "tsc"); 3634 if (propval) { 3635 if (sal_strcmp(propval, "XAUI") == 0) { 3636 if (_hr3_sku_port_config[sku_config_idx].default_port_ratio[i] 3637 != SOC_HR3_PORT_RATIO_SINGLE_XAUI) { 3638 return FALSE; 3639 } 3640 } else if (sal_strcmp(propval, "SINGLE") == 0) { 3641 if (_hr3_sku_port_config[sku_config_idx].default_port_ratio[i] 3642 != SOC_HR3_PORT_RATIO_QUAD) { 3643 return FALSE; 3644 } 3645 } 3646 } 3647 } 3648 3649 return TRUE; 3650 } 3651 3652 /* 3653 * Function: 3654 * _soc_hurricane3_port_gphy_mode_init 3655 * Purpose: 3656 * Init GPHY as normal or bypass mode based on the 3657 * matched SKU configuration. 3658 * (GPHY_BYPASS mode means trun off the embedded GPHYs.) 3659 * Note: 3660 * From rev B0, TOP_MISC_STATUSr.RSVD_0f is used to configure 3661 * GPHY bypass mode 3662 */ 3663 STATIC int 3664 _soc_hurricane3_port_gphy_mode_init(int unit) 3665 { 3666 uint16 dev_id; 3667 uint8 rev_id; 3668 uint32 rval = 0; 3669 3670 soc_cm_get_id(unit, &dev_id, &rev_id); 3671 3672 /* The support of gphy bypass mode is started from B0 */ 3673 if (rev_id == BCM56160_A0_REV_ID) { 3674 return SOC_E_NONE; 3675 } 3676 3677 SOC_IF_ERROR_RETURN(READ_TOP_MISC_STATUSr(unit, &rval)); 3678 3679 if (_hr3_sku_port_config[matched_devid_idx[unit]].gphy_bypass == 0) { 3680 soc_reg_field_set(unit, TOP_MISC_STATUSr, &rval, RSVD_0f, 0x0); 3681 } else { 3682 soc_reg_field_set(unit, TOP_MISC_STATUSr, &rval, RSVD_0f, 0x3); 3683 } 3684 3685 SOC_IF_ERROR_RETURN(WRITE_TOP_MISC_STATUSr(unit, rval)); 3686 3687 return SOC_E_NONE; 3688 } 3689 3690 /* 3691 * HR3 port mapping 3692 * cpu port number is fixed: physical 0, logical 0, mmu 0 3693 */ 3694 int 3695 soc_hurricane3_port_config_init(int unit, uint16 dev_id) 3696 { 3697 3698 soc_info_t *si; 3699 int rv = SOC_E_NONE; 3700 int phy_port; 3701 const int *p2l_mapping = 0,*speed_max = 0; 3702 char *propval,*option; 3703 int match = -1, i, j, match_option; 3704 int p2l_mapping_override[SOC_MAX_PHY_PORTS]; 3705 int port_speed_max_override[SOC_MAX_PHY_PORTS]; 3706 int port_num_lanes[SOC_MAX_PHY_PORTS]; 3707 _hr3_sku_info_t *matched_port_config = NULL; 3708 uint32 gphy_bypass = 0; 3709 3710 3711 matched_devid_idx[unit] = -1; 3712 option = soc_property_get_str(unit, spn_BCM5616X_INIT_PORT_CONFIG); 3713 if(option == NULL) { 3714 if ((dev_id & 0x00F0) == 0x0060) { /* Hurricane3 */ 3715 _hr3_port_config_id = 5; 3716 } else { 3717 /* default option to 1 for non-HR3 SKUs */ 3718 _hr3_port_config_id = 1; 3719 } 3720 } else { 3721 _hr3_port_config_id = sal_ctoi(option, NULL); 3722 } 3723 match_option = -1; 3724 /* gphy_bypass value */ 3725 gphy_bypass = soc_property_suffix_num_get_only_suffix(unit, 0, 3726 spn_BCM5616X_INIT_PORT_CONFIG, "gphy_bypass", 0); 3727 3728 for (i=0; _hr3_sku_port_config[i].dev_id; i++){ 3729 /* CHECK SKU ID */ 3730 if(dev_id == _hr3_sku_port_config[i].dev_id) { 3731 match = i; 3732 if (_hr3_sku_port_config[i].config_op != -1 ){ 3733 match_option = 0; 3734 3735 /* check the option ID and GPHY bypass mode */ 3736 if ((_hr3_sku_port_config[i].config_op == _hr3_port_config_id) 3737 && (_hr3_sku_port_config[i].gphy_bypass == 3738 gphy_bypass)){ 3739 /* Check the TSC configuration is supported or not */ 3740 if ((_hr3_sku_port_config[i].tsc_configurable) && 3741 (!_soc_hr3_tsc_config_supported(unit, i))) { 3742 continue; 3743 } 3744 /* match */ 3745 match = i; 3746 match_option = _hr3_port_config_id; 3747 break; 3748 } 3749 } 3750 } 3751 } 3752 for (i = 0; i < _HR3_MAX_TSC_COUNT; i++) { 3753 _hr3_tsc[i].port_count = 0; 3754 _hr3_tsc[i].valid = 0; 3755 _hr3_tsc[i].phy_port_base = tsc_phy_port[i]; 3756 if (match == -1) { 3757 _hr3_tsc[i].port_count = _hr3_sku_port_config[0].default_port_ratio[i]; 3758 } else { 3759 _hr3_tsc[i].port_count = _hr3_sku_port_config[match].default_port_ratio[i]; 3760 } 3761 } 3762 3763 /* Check QTC SGMII/QSGMII selection */ 3764 for (i = 0; i < _HR3_MAX_QTC_COUNT; i++) { 3765 _hr3_qtc_serdes_override[i] = _HR3_QTC_SERDES_OVERRDE_NONE; 3766 propval = soc_property_suffix_num_str_get(unit, i, spn_BCM5616X_INIT_PORT_CONFIG, "qtc"); 3767 if (propval) { 3768 if (sal_strcmp(propval, "SGMII") == 0) { 3769 _hr3_qtc_serdes_override[i] = _HR3_QTC_SERDES_OVERRDE_SGMII; 3770 LOG_VERBOSE(BSL_LS_SOC_COMMON, 3771 (BSL_META_U(unit,"%s: QTC%1d is SGMII\n"), 3772 FUNCTION_NAME(), i)); 3773 } else if (sal_strcmp(propval, "QSGMII") == 0) { 3774 _hr3_qtc_serdes_override[i] = _HR3_QTC_SERDES_OVERRDE_QSGMII; 3775 LOG_VERBOSE(BSL_LS_SOC_COMMON, 3776 (BSL_META_U(unit,"%s: QTC%1d is QSGMII\n"), 3777 FUNCTION_NAME(), i)); 3778 } else { 3779 _hr3_qtc_serdes_override[i] = _HR3_QTC_SERDES_OVERRDE_NONE; 3780 } 3781 } 3782 } 3783 3784 for (phy_port = 0; phy_port < SOC_MAX_PHY_PORTS; phy_port++) { 3785 p2l_mapping_override[phy_port] = 0; 3786 port_speed_max_override[phy_port] = 0; 3787 port_num_lanes[phy_port] = 1; 3788 } 3789 if (match == -1) { 3790 /* take 56160 option 1a as default config */ 3791 p2l_mapping = p2l_mapping_56160_op1a; 3792 speed_max = port_speed_max_56160_op1a; 3793 LOG_WARN(BSL_LS_SOC_COMMON, 3794 (BSL_META_U(unit,"%s: no device_id matched\n"),FUNCTION_NAME())); 3795 } else { 3796 matched_devid_idx[unit] = match; 3797 matched_port_config = &_hr3_sku_port_config[match]; 3798 if (((option != NULL) && (matched_port_config->config_op == -1)) || 3799 (match_option == 0)){ 3800 LOG_WARN(BSL_LS_SOC_COMMON, 3801 (BSL_META_U(unit, "Warning: bcm5616x_init_port_config=%d config " 3802 "is not supported in %s ! \n"),_hr3_port_config_id, 3803 soc_dev_name(unit))); 3804 } 3805 3806 p2l_mapping = matched_port_config->p2l_mapping; 3807 speed_max = matched_port_config->speed_max; 3808 3809 /* QSGMII or SGMII selection */ 3810 for (i = 0; i <_HR3_MAX_QTC_COUNT; i++) { 3811 if(!((1 << i) & matched_port_config->disabled_qtc_bmp)) { 3812 /* Override to the SGMII port mapping and max speed */ 3813 if (_hr3_qtc_serdes_override[i] == _HR3_QTC_SERDES_OVERRDE_SGMII) { 3814 LOG_VERBOSE(BSL_LS_SOC_COMMON, 3815 (BSL_META_U(unit,"%s: QTC%1d SGMII overrided.\n"), 3816 FUNCTION_NAME(), i)); 3817 if (matched_port_config->num_sgmii_supported[i] == 0) { 3818 LOG_WARN(BSL_LS_SOC_COMMON, 3819 (BSL_META_U(unit, 3820 "Warning: bcm5616x_init_port_config_qtc%d config " 3821 "is not supported in %s ! \n"),i, 3822 soc_dev_name(unit))); 3823 } 3824 /* Disable original qsgmii ports */ 3825 for (j = 0; j < matched_port_config->num_qsgmii_supported[i]; j++) { 3826 p2l_mapping_override[qtc_phy_port[i]+j * 4] = -1; 3827 p2l_mapping_override[qtc_phy_port[i]+j * 4 + 1] = -1; 3828 p2l_mapping_override[qtc_phy_port[i]+j * 4 + 2] = -1; 3829 p2l_mapping_override[qtc_phy_port[i]+j * 4 + 3] = -1; 3830 } 3831 for (j = 0; j < matched_port_config->num_sgmii_supported[i]; j++) { 3832 3833 /* Override sgmii port to max speed = 2.5 Gb*/ 3834 p2l_mapping_override[qtc_phy_port[i]+j] = 1; 3835 port_num_lanes[qtc_phy_port[i]+j] = 4; 3836 if ((dev_id == BCM56160_DEVICE_ID) || 3837 (dev_id == BCM53440_DEVICE_ID)) { 3838 port_speed_max_override[qtc_phy_port[i]+j] = 25; 3839 } else { 3840 port_speed_max_override[qtc_phy_port[i]+j] = 10; 3841 } 3842 } 3843 } else if (_hr3_qtc_serdes_override[i] == 3844 _HR3_QTC_SERDES_OVERRDE_QSGMII) { 3845 if (matched_port_config->num_qsgmii_supported[i] == 0) { 3846 LOG_WARN(BSL_LS_SOC_COMMON, 3847 (BSL_META_U(unit, 3848 "Warning: bcm5616x_init_port_config_qtc%d config " 3849 "is not supported in %s ! \n"),i, 3850 soc_dev_name(unit))); 3851 /* Defaul configuration is QSGMII except QSGMII is not supported */ 3852 /* No need to override the mapping and max port speed */ 3853 } 3854 } 3855 } 3856 } 3857 /* TSC configuration selection of 56163 and 53443 */ 3858 if (matched_port_config->tsc_configurable) { 3859 for (i = 0; i <_HR3_MAX_TSC_COUNT; i++) { 3860 propval = soc_property_suffix_num_str_get(unit, i, 3861 spn_BCM5616X_INIT_PORT_CONFIG, "tsc"); 3862 if (propval) { 3863 if (sal_strcmp(propval, "XAUI") == 0) { 3864 p2l_mapping_override[tsc_phy_port[i]] = 1; 3865 port_speed_max_override[tsc_phy_port[i]] = 100; 3866 p2l_mapping_override[tsc_phy_port[i]+ 1] = -1; 3867 p2l_mapping_override[tsc_phy_port[i]+ 2] = -1; 3868 p2l_mapping_override[tsc_phy_port[i]+ 3] = -1; 3869 LOG_VERBOSE(BSL_LS_SOC_COMMON, 3870 (BSL_META_U(unit,"%s: TSC%1d is XAUI mode\n"), 3871 FUNCTION_NAME(), i)); 3872 } else if (sal_strcmp(propval, "SINGLE") == 0) { 3873 /* default configuration */ 3874 LOG_VERBOSE(BSL_LS_SOC_COMMON, 3875 (BSL_META_U(unit,"%s: TSC%1d is SINGLE mode\n"), 3876 FUNCTION_NAME(), i)); 3877 } else { 3878 /* Using default configuration, SINGLE */ 3879 LOG_VERBOSE(BSL_LS_SOC_COMMON, 3880 (BSL_META_U(unit,"%s: TSC%1d is SINGLE mode\n"), 3881 FUNCTION_NAME(), i)); 3882 } 3883 } 3884 } 3885 } 3886 } 3887 3888 si = &SOC_INFO(unit); 3889 3890 for (phy_port = 0; phy_port < SOC_MAX_PHY_PORTS; phy_port++) { 3891 if (p2l_mapping_override[phy_port] == -1){ 3892 si->port_p2l_mapping[phy_port] = p2l_mapping_override[phy_port]; 3893 /* Same as Egr P2L */ 3894 si->port_p2m_mapping[phy_port] = p2l_mapping_override[phy_port]; 3895 /* For COSQ programming */ 3896 si->max_port_p2m_mapping[phy_port] = p2l_mapping_override[phy_port]; 3897 } else { 3898 /* speed_max reflects the valid port */ 3899 /* For the same TDM, the phy_port should be existed in p2l_mapping table */ 3900 if((speed_max[phy_port] == -1) && (phy_port != 0)){ 3901 si->port_p2l_mapping[phy_port] = -1; 3902 si->port_p2m_mapping[phy_port] = -1; 3903 si->max_port_p2m_mapping[phy_port] = -1; 3904 si->port_num_lanes[p2l_mapping[phy_port]] = -1; 3905 } else { 3906 si->port_p2l_mapping[phy_port] = p2l_mapping[phy_port]; 3907 si->port_p2m_mapping[phy_port] = p2l_mapping[phy_port]; 3908 si->max_port_p2m_mapping[phy_port] = p2l_mapping[phy_port]; 3909 si->port_num_lanes[p2l_mapping[phy_port]] = 1; 3910 } 3911 } 3912 if (port_speed_max_override[phy_port] != 0){ 3913 if (port_speed_max_override[phy_port] != -1) { 3914 si->port_speed_max[si->port_p2l_mapping[phy_port]] = 3915 port_speed_max_override[phy_port] * 100; 3916 si->port_num_lanes[p2l_mapping[phy_port]] = 3917 port_num_lanes[phy_port]; 3918 } 3919 } else { 3920 if (speed_max[phy_port] != -1) { 3921 si->port_speed_max[si->port_p2l_mapping[phy_port]] = 3922 speed_max[phy_port] * 100; 3923 } 3924 } 3925 } 3926 3927 /* QTC port count */ 3928 for (i = 0; i <_HR3_MAX_QTC_COUNT; i++) { 3929 _hr3_qtc_gport_port_count[i][0] = SOC_HR3_PORT_RATIO_NONE; 3930 _hr3_qtc_gport_port_count[i][1] = SOC_HR3_PORT_RATIO_NONE; 3931 phy_port = qtc_phy_port[i]; 3932 /* Check the port count of GPORT blocks */ 3933 if(!((1 << i) & matched_port_config->disabled_qtc_bmp)) { 3934 /* GP0 */ 3935 if (si->port_p2l_mapping[phy_port + 7] != -1) { 3936 _hr3_qtc_gport_port_count[i][0] = SOC_HR3_PORT_RATIO_OCTAL; 3937 } else if (si->port_p2l_mapping[phy_port + 3] != -1) { 3938 _hr3_qtc_gport_port_count[i][0] = SOC_HR3_PORT_RATIO_QUAD; 3939 } else if (si->port_p2l_mapping[phy_port + 1] != -1) { 3940 _hr3_qtc_gport_port_count[i][0] = SOC_HR3_PORT_RATIO_DUAL_1_1; 3941 } else if (si->port_p2l_mapping[phy_port] != -1) { 3942 _hr3_qtc_gport_port_count[i][0] = SOC_HR3_PORT_RATIO_SINGLE; 3943 } 3944 3945 /* GP1 */ 3946 if (si->port_p2l_mapping[phy_port + 15] != -1) { 3947 _hr3_qtc_gport_port_count[i][1] = SOC_HR3_PORT_RATIO_OCTAL; 3948 } else if (si->port_p2l_mapping[phy_port + 11] != -1) { 3949 _hr3_qtc_gport_port_count[i][1] = SOC_HR3_PORT_RATIO_QUAD; 3950 } else if (si->port_p2l_mapping[phy_port + 9] != -1) { 3951 _hr3_qtc_gport_port_count[i][1] = SOC_HR3_PORT_RATIO_DUAL_1_1; 3952 } else if (si->port_p2l_mapping[phy_port + 8] != -1) { 3953 _hr3_qtc_gport_port_count[i][1] = SOC_HR3_PORT_RATIO_SINGLE; 3954 } 3955 } 3956 } 3957 3958 /* system core clock */ 3959 si->frequency = matched_port_config->freq; 3960 3961 return rv; 3962 } 3963 3964 3965 int 3966 _soc_hurricane3_tdm_init(int unit, uint16 dev_id) 3967 { 3968 uint32 *arr = NULL; 3969 int tdm_size; 3970 uint32 rval; 3971 iarb_tdm_table_entry_t iarb_tdm; 3972 mmu_arb_tdm_table_entry_t mmu_arb_tdm; 3973 int i, port, phy_port; 3974 _hr3_sku_info_t *matched_sku_info; 3975 3976 3977 SOC_IF_ERROR_RETURN(READ_IARB_TDM_CONTROLr(unit, &rval)); 3978 soc_reg_field_set(unit, IARB_TDM_CONTROLr, &rval, DISABLEf, 1); 3979 soc_reg_field_set(unit, IARB_TDM_CONTROLr, &rval, TDM_WRAP_PTRf, 83); 3980 SOC_IF_ERROR_RETURN(WRITE_IARB_TDM_CONTROLr(unit, rval)); 3981 3982 if (matched_devid_idx[unit] == -1) { 3983 LOG_WARN(BSL_LS_SOC_COMMON, 3984 (BSL_META_U(unit, "Warning: soc_hurricane3_port_config_init should " 3985 "be invoked first! Choose bcm56160 port config.\n"))); 3986 matched_devid_idx[unit] = 0; 3987 } 3988 matched_sku_info = &_hr3_sku_port_config[matched_devid_idx[unit]]; 3989 3990 arr = matched_sku_info->tdm_table; 3991 tdm_size = matched_sku_info->tdm_table_size; 3992 3993 if (arr == NULL) { 3994 return SOC_E_CONFIG; 3995 } 3996 3997 for (i = 0; i < tdm_size; i++) { 3998 phy_port = arr[i]; 3999 port = (phy_port != 63) ? matched_sku_info->p2l_mapping[phy_port]:63; 4000 sal_memset(&iarb_tdm, 0, sizeof(iarb_tdm_table_entry_t)); 4001 sal_memset(&mmu_arb_tdm, 0, sizeof(mmu_arb_tdm_table_entry_t)); 4002 4003 soc_IARB_TDM_TABLEm_field32_set(unit, &iarb_tdm, PORT_NUMf, 4004 phy_port); 4005 4006 soc_MMU_ARB_TDM_TABLEm_field32_set(unit, &mmu_arb_tdm, PORT_NUMf, 4007 (port != -1) ? port : 63); 4008 if (i == tdm_size - 1) { 4009 soc_MMU_ARB_TDM_TABLEm_field32_set(unit, &mmu_arb_tdm, WRAP_ENf, 1); 4010 } 4011 SOC_IF_ERROR_RETURN(WRITE_IARB_TDM_TABLEm(unit, SOC_BLOCK_ALL, i, 4012 &iarb_tdm)); 4013 SOC_IF_ERROR_RETURN(WRITE_MMU_ARB_TDM_TABLEm(unit, SOC_BLOCK_ALL, i, 4014 &mmu_arb_tdm)); 4015 } 4016 rval = 0; 4017 soc_reg_field_set(unit, IARB_TDM_CONTROLr, &rval, DISABLEf, 0); 4018 soc_reg_field_set(unit, IARB_TDM_CONTROLr, &rval, TDM_WRAP_PTRf, 4019 tdm_size -1); 4020 SOC_IF_ERROR_RETURN(WRITE_IARB_TDM_CONTROLr(unit, rval)); 4021 4022 return SOC_E_NONE; 4023 } 4024 4025 STATIC int 4026 _soc_hr3_mmu_init_lossy(int unit) 4027 { 4028 soc_port_t port; 4029 uint32 val, oval, cfap_max_idx; 4030 uint16 dev_id; 4031 uint8 rev_id; 4032 uint32 rval; 4033 int index; 4034 int mmu_total_dyn_cells_set; 4035 int mmu_total_dyn_cells_reset; 4036 int egress_xq_min_reserve_lossy_ports; 4037 int egress_pkt_set_limit; 4038 int egress_pkt_reset_limit; 4039 int egress_cng_pkt_set_limit0; 4040 int egress_cng_pkt_set_limit1; 4041 int egress_cng_port_pkt_limit0; 4042 int egress_cng_port_pkt_limit1; 4043 int egress_dyn_xq_cnt_port; 4044 int egress_dyn_reset_lim_port; 4045 int egress_lwm_cell_set_limit; 4046 int egress_lwm_cell_reset_limit; 4047 int egress_hol_cell_max_limit; 4048 int egress_hol_cell_max_resume_limit; 4049 int egress_dyn_cell_set_limit; 4050 int egress_dyn_cell_reset_limit; 4051 4052 soc_cm_get_id(unit, &dev_id, &rev_id); 4053 4054 cfap_max_idx = soc_mem_index_max(unit, MMU_CFAPm); 4055 SOC_IF_ERROR_RETURN(READ_CFAPCONFIGr(unit, &val)); 4056 oval = val; 4057 soc_reg_field_set(unit, CFAPCONFIGr, &val, CFAPPOOLSIZEf, cfap_max_idx); 4058 if (oval != val) { 4059 SOC_IF_ERROR_RETURN(WRITE_CFAPCONFIGr(unit, val)); 4060 } 4061 4062 egress_xq_min_reserve_lossy_ports = 0xc; /* J61 */ 4063 egress_pkt_set_limit = 0x59c; /* J62 */ 4064 egress_pkt_reset_limit = 0x59b; /* J63 */ 4065 egress_cng_pkt_set_limit0 = 0x5ff; /* J64 */ 4066 egress_cng_pkt_set_limit1 = 0x5ff; /* J65 */ 4067 egress_cng_port_pkt_limit0 = 0x5ff; /* J66 */ 4068 egress_cng_port_pkt_limit1 = 0x5ff; /* J67 */ 4069 egress_dyn_xq_cnt_port = 0x590; /* J68 */ 4070 egress_dyn_reset_lim_port = 0x58e; /* J69 */ 4071 egress_lwm_cell_set_limit = 0xc; /* J70 */ 4072 egress_lwm_cell_reset_limit = 0xc; /* J71 */ 4073 4074 if (dev_id == BCM53443_DEVICE_ID) { 4075 /* downlink port 8, uplink port 4, cpu port 1 */ 4076 mmu_total_dyn_cells_set = 0x3abc; /* J15 */ 4077 mmu_total_dyn_cells_reset = 0x3a2c; /* J16 */ 4078 egress_hol_cell_max_limit = 0x764; /* J72 */ 4079 egress_hol_cell_max_resume_limit = 0x758; /* J73 */ 4080 egress_dyn_cell_set_limit = 0x3abc; /* J74 */ 4081 egress_dyn_cell_reset_limit = 0x3aa4; /* J75 */ 4082 } else if (dev_id == BCM56163_DEVICE_ID) { 4083 /* downlink port 16, uplink port 4, cpu port 1 */ 4084 mmu_total_dyn_cells_set = 0x37bc; /* J15 */ 4085 mmu_total_dyn_cells_reset = 0x372c; /* J16 */ 4086 egress_hol_cell_max_limit = 0x704; /* J72 */ 4087 egress_hol_cell_max_resume_limit = 0x6f8; /* J73 */ 4088 egress_dyn_cell_set_limit = 0x37bc; /* J74 */ 4089 egress_dyn_cell_reset_limit = 0x37a4; /* J75 */ 4090 } else if ((dev_id == BCM56162_DEVICE_ID) || 4091 (dev_id == BCM53442_DEVICE_ID) || 4092 (dev_id == BCM56164_DEVICE_ID)) { 4093 /* downlink port 24, uplink port 4, cpu port 1 */ 4094 mmu_total_dyn_cells_set = 0x34bc; /* J15 */ 4095 mmu_total_dyn_cells_reset = 0x342c; /* J16 */ 4096 egress_hol_cell_max_limit = 0x6a4; /* J72 */ 4097 egress_hol_cell_max_resume_limit = 0x698; /* J73 */ 4098 egress_dyn_cell_set_limit = 0x34bc; /* J74 */ 4099 egress_dyn_cell_reset_limit = 0x34a4; /* J75 */ 4100 } else { 4101 /* 56160, 56161, 53449, 53446 */ 4102 /* downlink port 24, uplink port 6, cpu port 1 */ 4103 mmu_total_dyn_cells_set = 0x33fc; /* J15 */ 4104 mmu_total_dyn_cells_reset = 0x336c; /* J16 */ 4105 egress_hol_cell_max_limit = 0x68c; /* J72 */ 4106 egress_hol_cell_max_resume_limit = 0x680; /* J73 */ 4107 egress_dyn_cell_set_limit = 0x33fc; /* J74 */ 4108 egress_dyn_cell_reset_limit = 0x33e4; /* J75 */ 4109 } 4110 4111 /* Device Wide Registers */ 4112 SOC_IF_ERROR_RETURN(READ_CFAPFULLTHRESHOLDr(unit, &val)); 4113 soc_reg_field_set(unit, CFAPFULLTHRESHOLDr, &val, 4114 CFAPFULLSETPOINTf, 0x3f9c); 4115 soc_reg_field_set(unit, CFAPFULLTHRESHOLDr, &val, 4116 CFAPFULLRESETPOINTf, 0x3f54); 4117 SOC_IF_ERROR_RETURN(WRITE_CFAPFULLTHRESHOLDr(unit, val)); 4118 4119 /* Ingress Thresholds */ 4120 SOC_IF_ERROR_RETURN(READ_GBLLIMITSETLIMITr(unit, &val)); 4121 soc_reg_field_set(unit, GBLLIMITSETLIMITr, &val, 4122 GBLCELLSETLIMITf, 0x3f9c); 4123 SOC_IF_ERROR_RETURN(WRITE_GBLLIMITSETLIMITr(unit, val)); 4124 4125 SOC_IF_ERROR_RETURN(READ_GBLLIMITRESETLIMITr(unit, &val)); 4126 soc_reg_field_set(unit, GBLLIMITRESETLIMITr, &val, 4127 GBLCELLRESETLIMITf, 0x3f9c); 4128 SOC_IF_ERROR_RETURN(WRITE_GBLLIMITRESETLIMITr(unit, val)); 4129 4130 /* Egress Thresholds */ 4131 rval = 0; 4132 soc_reg_field_set(unit, TOTALDYNCELLSETLIMITr, 4133 &rval, TOTALDYNCELLSETLIMITf, 4134 mmu_total_dyn_cells_set); 4135 SOC_IF_ERROR_RETURN(WRITE_TOTALDYNCELLSETLIMITr(unit, rval)); 4136 rval = 0; 4137 soc_reg_field_set(unit, TOTALDYNCELLRESETLIMITr, 4138 &rval, TOTALDYNCELLRESETLIMITf, 4139 mmu_total_dyn_cells_reset); 4140 SOC_IF_ERROR_RETURN(WRITE_TOTALDYNCELLRESETLIMITr(unit, rval)); 4141 4142 SOC_IF_ERROR_RETURN(READ_MISCCONFIGr(unit, &val)); 4143 soc_reg_field_set(unit, MISCCONFIGr, &val, MULTIPLE_ACCOUNTING_FIX_ENf, 1); 4144 soc_reg_field_set(unit, MISCCONFIGr, &val, CNG_DROP_ENf, 0); 4145 soc_reg_field_set(unit, MISCCONFIGr, &val, DYN_XQ_ENf, 1); 4146 soc_reg_field_set(unit, MISCCONFIGr, &val, HOL_CELL_SOP_DROP_ENf, 1); 4147 soc_reg_field_set(unit, MISCCONFIGr, &val, DYNAMIC_MEMORY_ENf, 1); 4148 soc_reg_field_set(unit, MISCCONFIGr, &val, SKIDMARKERf, 3); 4149 SOC_IF_ERROR_RETURN(WRITE_MISCCONFIGr(unit, val)); 4150 4151 /* Enable IP to CMICM credit transfer */ 4152 val = 0; 4153 soc_reg_field_set(unit, IP_TO_CMICM_CREDIT_TRANSFERr, &val, TRANSFER_ENABLEf, 1); 4154 soc_reg_field_set(unit, IP_TO_CMICM_CREDIT_TRANSFERr, &val, NUM_OF_CREDITSf, 32); 4155 SOC_IF_ERROR_RETURN(WRITE_IP_TO_CMICM_CREDIT_TRANSFERr(unit, val)); 4156 4157 PBMP_ALL_ITER(unit, port) { 4158 /* PG_CTRL0r */ 4159 soc_reg32_get(unit, PG_CTRL0r, port, 0, &rval); 4160 soc_reg_field_set(unit, PG_CTRL0r, &rval, PPFC_PG_ENf, 0); 4161 soc_reg_field_set(unit, PG_CTRL0r, &rval, PRI0_GRPf, 0); 4162 soc_reg_field_set(unit, PG_CTRL0r, &rval, PRI1_GRPf, 1); 4163 soc_reg_field_set(unit, PG_CTRL0r, &rval, PRI2_GRPf, 2); 4164 soc_reg_field_set(unit, PG_CTRL0r, &rval, PRI3_GRPf, 3); 4165 soc_reg_field_set(unit, PG_CTRL0r, &rval, PRI4_GRPf, 4); 4166 soc_reg_field_set(unit, PG_CTRL0r, &rval, PRI5_GRPf, 5); 4167 soc_reg_field_set(unit, PG_CTRL0r, &rval, PRI6_GRPf, 6); 4168 soc_reg_field_set(unit, PG_CTRL0r, &rval, PRI7_GRPf, 7); 4169 soc_reg32_set(unit, PG_CTRL0r, port, 0, rval); 4170 4171 /* PG_CTRL1r */ 4172 soc_reg32_get(unit, PG_CTRL1r, port, 0, &rval); 4173 soc_reg_field_set(unit, PG_CTRL1r, &rval, PRI8_GRPf, 7); 4174 soc_reg_field_set(unit, PG_CTRL1r, &rval, PRI9_GRPf, 7); 4175 soc_reg_field_set(unit, PG_CTRL1r, &rval, PRI10_GRPf, 7); 4176 soc_reg_field_set(unit, PG_CTRL1r, &rval, PRI11_GRPf, 7); 4177 soc_reg_field_set(unit, PG_CTRL1r, &rval, PRI12_GRPf, 7); 4178 soc_reg_field_set(unit, PG_CTRL1r, &rval, PRI13_GRPf, 7); 4179 soc_reg_field_set(unit, PG_CTRL1r, &rval, PRI14_GRPf, 7); 4180 soc_reg_field_set(unit, PG_CTRL1r, &rval, PRI15_GRPf, 7); 4181 soc_reg32_set(unit, PG_CTRL1r, port, 0, rval); 4182 4183 /* PG2TCr, index 0 ~ 7 */ 4184 for (index = 0; index <= 7; index++) { 4185 soc_reg32_get(unit, PG2TCr, port, index, &rval); 4186 soc_reg_field_set(unit, PG2TCr, &rval, PG_BMPf, 0); 4187 soc_reg32_set(unit, PG2TCr, port, index, rval); 4188 } 4189 4190 /* IBPPKTSETLIMITr */ 4191 val = 0; 4192 soc_reg_field_set(unit, IBPPKTSETLIMITr, &val, 4193 PKTSETLIMITf, 0x3f9c); 4194 soc_reg_field_set(unit, IBPPKTSETLIMITr, &val, RESETLIMITSELf, 3); 4195 SOC_IF_ERROR_RETURN(WRITE_IBPPKTSETLIMITr(unit, port, val)); 4196 4197 /* MMU_FC_RX_ENr */ 4198 soc_reg32_get(unit, MMU_FC_RX_ENr, port, 0, &rval); 4199 soc_reg_field_set(unit, MMU_FC_RX_ENr, &rval, MMU_FC_RX_ENABLEf, 0); 4200 soc_reg32_set(unit, MMU_FC_RX_ENr, port, 0, rval); 4201 4202 /* MMU_FC_TX_ENr */ 4203 soc_reg32_get(unit, MMU_FC_TX_ENr, port, 0, &rval); 4204 soc_reg_field_set(unit, MMU_FC_TX_ENr, &rval, MMU_FC_TX_ENABLEf, 0); 4205 soc_reg32_set(unit, MMU_FC_TX_ENr, port, 0, rval); 4206 4207 /* PGCELLLIMITr, index 0 ~ 7 */ 4208 for (index = 0; index <= 7; index++) { 4209 soc_reg32_get(unit, PGCELLLIMITr, port, index, &rval); 4210 soc_reg_field_set(unit, PGCELLLIMITr, &rval, 4211 CELLSETLIMITf, 4212 0x3f9c); 4213 soc_reg_field_set(unit, PGCELLLIMITr, &rval, 4214 CELLRESETLIMITf, 4215 0x3f9c); 4216 soc_reg32_set(unit, PGCELLLIMITr, 4217 port, index, rval); 4218 } 4219 4220 /* PGDISCARDSETLIMITr, index 0 ~ 7 */ 4221 for (index = 0; index <= 7; index++) { 4222 soc_reg32_get(unit, PGDISCARDSETLIMITr, 4223 port, index, &rval); 4224 soc_reg_field_set(unit, PGDISCARDSETLIMITr, &rval, 4225 DISCARDSETLIMITf, 4226 0x3f9c); 4227 soc_reg32_set(unit, PGDISCARDSETLIMITr, 4228 port, index, rval); 4229 } 4230 4231 /* HOLCOSMINXQCNTr, index 0 ~ 7 */ 4232 for (index = 0; index <= 7; index++) { 4233 soc_reg32_get(unit, HOLCOSMINXQCNTr, 4234 port, index, &rval); 4235 soc_reg_field_set(unit, HOLCOSMINXQCNTr, &rval, 4236 HOLCOSMINXQCNTf, 4237 egress_xq_min_reserve_lossy_ports); 4238 soc_reg32_set(unit, HOLCOSMINXQCNTr, 4239 port, index, rval); 4240 } 4241 4242 /* HOLCOSPKTSETLIMITr, index 0 ~ 7 */ 4243 for (index = 0; index <= 7; index++) { 4244 soc_reg32_get(unit, HOLCOSPKTSETLIMITr, 4245 port, index, &rval); 4246 soc_reg_field_set(unit, HOLCOSPKTSETLIMITr, &rval, 4247 PKTSETLIMITf, 4248 egress_pkt_set_limit); 4249 soc_reg32_set(unit, HOLCOSPKTSETLIMITr, 4250 port, index, rval); 4251 } 4252 4253 /* HOLCOSPKTRESETLIMITr, index 0 ~ 7 */ 4254 for (index = 0; index <= 7; index++) { 4255 soc_reg32_get(unit, HOLCOSPKTRESETLIMITr, 4256 port, index, &rval); 4257 soc_reg_field_set(unit, HOLCOSPKTRESETLIMITr, &rval, 4258 PKTRESETLIMITf, 4259 egress_pkt_reset_limit); 4260 soc_reg32_set(unit, HOLCOSPKTRESETLIMITr, 4261 port, index, rval); 4262 } 4263 4264 /* CNGCOSPKTLIMIT0r, index 0 ~ 7 */ 4265 for (index = 0; index <= 7; index++) { 4266 soc_reg32_get(unit, CNGCOSPKTLIMIT0r, 4267 port, index, &rval); 4268 soc_reg_field_set(unit, CNGCOSPKTLIMIT0r, &rval, 4269 CNGPKTSETLIMIT0f, 4270 egress_cng_pkt_set_limit0); 4271 soc_reg32_set(unit, CNGCOSPKTLIMIT0r, 4272 port, index, rval); 4273 } 4274 4275 /* CNGCOSPKTLIMIT1r, index 0 ~ 7 */ 4276 for (index = 0; index <= 7; index++) { 4277 soc_reg32_get(unit, CNGCOSPKTLIMIT1r, 4278 port, index, &rval); 4279 soc_reg_field_set(unit, CNGCOSPKTLIMIT1r, &rval, 4280 CNGPKTSETLIMIT1f, 4281 egress_cng_pkt_set_limit1); 4282 soc_reg32_set(unit, CNGCOSPKTLIMIT1r, 4283 port, index, rval); 4284 } 4285 4286 /* CNGPORTPKTLIMIT0r */ 4287 soc_reg32_get(unit, CNGPORTPKTLIMIT0r, 4288 port, 0, &rval); 4289 soc_reg_field_set(unit, CNGPORTPKTLIMIT0r, &rval, 4290 CNGPORTPKTLIMIT0f, 4291 egress_cng_port_pkt_limit0); 4292 soc_reg32_set(unit, CNGPORTPKTLIMIT0r, 4293 port, 0, rval); 4294 4295 /* CNGPORTPKTLIMIT1r */ 4296 soc_reg32_get(unit, CNGPORTPKTLIMIT1r, 4297 port, 0, &rval); 4298 soc_reg_field_set(unit, CNGPORTPKTLIMIT1r, &rval, 4299 CNGPORTPKTLIMIT1f, 4300 egress_cng_port_pkt_limit1); 4301 soc_reg32_set(unit, CNGPORTPKTLIMIT1r, 4302 port, 0, rval); 4303 4304 /* DYNXQCNTPORTr */ 4305 soc_reg32_get(unit, DYNXQCNTPORTr, 4306 port, 0, &rval); 4307 soc_reg_field_set(unit, DYNXQCNTPORTr, &rval, 4308 DYNXQCNTPORTf, 4309 egress_dyn_xq_cnt_port); 4310 soc_reg32_set(unit, DYNXQCNTPORTr, 4311 port, 0, rval); 4312 4313 /* DYNRESETLIMPORTr */ 4314 soc_reg32_get(unit, DYNRESETLIMPORTr, 4315 port, 0, &rval); 4316 soc_reg_field_set(unit, DYNRESETLIMPORTr, &rval, 4317 DYNRESETLIMPORTf, 4318 egress_dyn_reset_lim_port); 4319 soc_reg32_set(unit, DYNRESETLIMPORTr, 4320 port, 0, rval); 4321 4322 /* LWMCOSCELLSETLIMITr, index 0 ~ 7 */ 4323 for (index = 0; index <= 7; index++) { 4324 soc_reg32_get(unit, LWMCOSCELLSETLIMITr, 4325 port, index, &rval); 4326 soc_reg_field_set(unit, LWMCOSCELLSETLIMITr, &rval, 4327 CELLSETLIMITf, 4328 egress_lwm_cell_set_limit); 4329 soc_reg_field_set(unit, LWMCOSCELLSETLIMITr, &rval, 4330 CELLRESETLIMITf, 4331 egress_lwm_cell_reset_limit); 4332 soc_reg32_set(unit, LWMCOSCELLSETLIMITr, 4333 port, index, rval); 4334 } 4335 4336 /* HOLCOSCELLMAXLIMITr, index 0 ~ 7 */ 4337 for (index = 0; index <= 7; index++) { 4338 soc_reg32_get(unit, HOLCOSCELLMAXLIMITr, 4339 port, index, &rval); 4340 soc_reg_field_set(unit, HOLCOSCELLMAXLIMITr, &rval, 4341 CELLMAXLIMITf, 4342 egress_hol_cell_max_limit); 4343 soc_reg_field_set(unit, HOLCOSCELLMAXLIMITr, &rval, 4344 CELLMAXRESUMELIMITf, 4345 egress_hol_cell_max_resume_limit); 4346 soc_reg32_set(unit, HOLCOSCELLMAXLIMITr, 4347 port, index, rval); 4348 } 4349 4350 /* DYNCELLLIMITr */ 4351 soc_reg32_get(unit, DYNCELLLIMITr, 4352 port, 0, &rval); 4353 soc_reg_field_set(unit, DYNCELLLIMITr, &rval, 4354 DYNCELLSETLIMITf, 4355 egress_dyn_cell_set_limit); 4356 soc_reg_field_set(unit, DYNCELLLIMITr, &rval, 4357 DYNCELLRESETLIMITf, 4358 egress_dyn_cell_reset_limit); 4359 soc_reg32_set(unit, DYNCELLLIMITr, 4360 port, 0, rval); 4361 4362 /* COLOR_DROP_ENr */ 4363 soc_reg32_get(unit, COLOR_DROP_ENr, 4364 port, 0, &rval); 4365 soc_reg_field_set(unit, COLOR_DROP_ENr, &rval, 4366 COLOR_DROP_ENf, 4367 0); 4368 soc_reg32_set(unit, COLOR_DROP_ENr, 4369 port, 0, rval); 4370 4371 /* SHARED_POOL_CTRLr */ 4372 soc_reg32_get(unit, SHARED_POOL_CTRLr, 4373 port, 0, &rval); 4374 soc_reg_field_set(unit, SHARED_POOL_CTRLr, &rval, 4375 DYNAMIC_COS_DROP_ENf, 4376 0xff); 4377 soc_reg_field_set(unit, SHARED_POOL_CTRLr, &rval, 4378 SHARED_POOL_DISCARD_ENf, 4379 0); 4380 soc_reg_field_set(unit, SHARED_POOL_CTRLr, &rval, 4381 SHARED_POOL_XOFF_ENf, 4382 0); 4383 soc_reg32_set(unit, SHARED_POOL_CTRLr, 4384 port, 0, rval); 4385 } 4386 4387 return SOC_E_NONE; 4388 } 4389 4390 STATIC int 4391 _soc_hr3_mmu_init_lossless(int unit) 4392 { 4393 int cos; 4394 soc_port_t port; 4395 uint32 val, oval, cfap_max_idx; 4396 int skid_mark; 4397 uint32 dyn_xq_per_port; 4398 uint32 xq_limit, cell_limit; 4399 uint32 cos_min_xqs, cos_min_cells; 4400 uint16 dev_id; 4401 uint8 rev_id; 4402 int mmu_total_cells; 4403 int mmu_total_dyn_cells; 4404 int mmu_total_static_cells; 4405 int total_ports; 4406 uint32 max_cell_limit_pri0; 4407 uint32 max_cell_limit_pri1_7; 4408 uint32 dyn_cell_limit; 4409 uint32 xoff_cell_limit; 4410 uint32 reset_cell_limit; 4411 uint32 cell_resume_delta; 4412 uint32 dyn_cell_reset_delta; 4413 4414 soc_cm_get_id(unit, &dev_id, &rev_id); 4415 4416 cfap_max_idx = soc_mem_index_max(unit, MMU_CFAPm); 4417 SOC_IF_ERROR_RETURN(READ_CFAPCONFIGr(unit, &val)); 4418 oval = val; 4419 soc_reg_field_set(unit, CFAPCONFIGr, &val, CFAPPOOLSIZEf, cfap_max_idx); 4420 if (oval != val) { 4421 SOC_IF_ERROR_RETURN(WRITE_CFAPCONFIGr(unit, val)); 4422 } 4423 4424 SOC_IF_ERROR_RETURN(READ_MISCCONFIGr(unit, &val)); 4425 /* set dyn_xq_en on */ 4426 soc_reg_field_set(unit, MISCCONFIGr, &val, DYN_XQ_ENf, 1); 4427 /* set HOL_CELL_SOP_DROP_EN on */ 4428 soc_reg_field_set(unit, MISCCONFIGr, &val, HOL_CELL_SOP_DROP_ENf, 1); 4429 /* set skidmarker to 3 */ 4430 soc_reg_field_set(unit, MISCCONFIGr, &val, SKIDMARKERf, 3); 4431 SOC_IF_ERROR_RETURN(WRITE_MISCCONFIGr(unit, val)); 4432 4433 /* Every inactive COSQ consumes skid mark + 4 XQs; remove them from pool */ 4434 SOC_IF_ERROR_RETURN(READ_MISCCONFIGr(unit, &val)); 4435 skid_mark = soc_reg_field_get(unit, MISCCONFIGr, val, SKIDMARKERf) + 4; 4436 4437 /* Enable IP to CMICM credit transfer */ 4438 val = 0; 4439 soc_reg_field_set(unit, IP_TO_CMICM_CREDIT_TRANSFERr, &val, TRANSFER_ENABLEf, 1); 4440 soc_reg_field_set(unit, IP_TO_CMICM_CREDIT_TRANSFERr, &val, NUM_OF_CREDITSf, 32); 4441 SOC_IF_ERROR_RETURN(WRITE_IP_TO_CMICM_CREDIT_TRANSFERr(unit, val)); 4442 4443 if (dev_id == BCM53434_DEVICE_ID) { 4444 /* Foxhound2 with 512 KB buffer */ 4445 mmu_total_cells = FH2_MMU_BUFFER_SIZE_512KB / HR3_MMU_CELL_SIZE; 4446 } else { 4447 mmu_total_cells = HR3_MMU_BUFFER_SIZE_2MB / HR3_MMU_CELL_SIZE; 4448 } 4449 4450 if (dev_id == BCM53443_DEVICE_ID) { 4451 total_ports = 13; 4452 } else if (dev_id == BCM56163_DEVICE_ID) { 4453 total_ports = 21; 4454 } else if ((dev_id == BCM56162_DEVICE_ID) || 4455 (dev_id == BCM53442_DEVICE_ID) || 4456 (dev_id == BCM56164_DEVICE_ID)) { 4457 total_ports = 29; 4458 } else if (dev_id == BCM53434_DEVICE_ID) { 4459 total_ports = 25; 4460 } else { 4461 /* 56160, 56166, 53440 */ 4462 total_ports = 31; 4463 } 4464 4465 mmu_total_static_cells = total_ports * HR3_MMU_IN_PORT_STATIC_CELLS; 4466 mmu_total_dyn_cells = mmu_total_cells - mmu_total_static_cells; 4467 4468 /* total dynamic xqs - skid mark - 9(reserved xqs) */ 4469 dyn_xq_per_port = HR3_MMU_IN_PORT_DYNAMIC_XQS - skid_mark - 9; 4470 /* limit includes the static minimum cells as well */ 4471 xq_limit = dyn_xq_per_port + HR3_MMU_IN_COS_MIN_XQS; 4472 cos_min_xqs = HR3_MMU_IN_COS_MIN_XQS; 4473 cos_min_cells = HR3_MMU_IN_COS_MIN_CELLS; 4474 4475 cell_resume_delta = 12; 4476 dyn_cell_reset_delta = 24; 4477 xoff_cell_limit = 80; 4478 reset_cell_limit = 40; 4479 max_cell_limit_pri1_7 = 48; 4480 if (dev_id == BCM53443_DEVICE_ID) { 4481 max_cell_limit_pri0 = 3888; 4482 } else if (dev_id == BCM56163_DEVICE_ID) { 4483 max_cell_limit_pri0= 6480; 4484 } else if ((dev_id == BCM56162_DEVICE_ID) || 4485 (dev_id == BCM53442_DEVICE_ID) || 4486 (dev_id == BCM56164_DEVICE_ID)) { 4487 max_cell_limit_pri0 = 9072; 4488 } else if (dev_id == BCM53434_DEVICE_ID) { 4489 dyn_xq_per_port = FH2_MMU_IN_PORT_DYNAMIC_XQS - skid_mark - 9; 4490 xq_limit = dyn_xq_per_port + FH2_MMU_IN_COS_MIN_XQS; 4491 cos_min_xqs = FH2_MMU_IN_COS_MIN_XQS; 4492 max_cell_limit_pri1_7 = 64; 4493 max_cell_limit_pri0= 2112; 4494 dyn_cell_reset_delta = 32; 4495 cell_resume_delta = 16; 4496 xoff_cell_limit = 40; 4497 reset_cell_limit = 30; 4498 } else { 4499 /* 56160, 56161, 53449, 53446 */ 4500 max_cell_limit_pri0 = 9720; 4501 } 4502 4503 dyn_cell_limit = max_cell_limit_pri0 + \ 4504 ((HR3_MMU_NUM_COS -1) * max_cell_limit_pri1_7); 4505 PBMP_ALL_ITER(unit, port) { 4506 4507 for (cos = 0; cos < NUM_COS(unit); cos++) { 4508 /* 4509 * The HOLCOSPKTSETLIMITr register controls BOTH the XQ 4510 * size per cosq AND the HOL set limit for that cosq. 4511 */ 4512 SOC_IF_ERROR_RETURN 4513 (READ_HOLCOSPKTSETLIMITr(unit, port, cos, &val)); 4514 soc_reg_field_set(unit, HOLCOSPKTSETLIMITr, &val, 4515 PKTSETLIMITf, 4516 xq_limit); 4517 SOC_IF_ERROR_RETURN 4518 (WRITE_HOLCOSPKTSETLIMITr(unit, port, cos, val)); 4519 4520 /* reset limit is set limit - 4 */ 4521 SOC_IF_ERROR_RETURN 4522 (READ_HOLCOSPKTRESETLIMITr(unit, port, cos, &val)); 4523 soc_reg_field_set(unit, HOLCOSPKTRESETLIMITr, &val, 4524 PKTRESETLIMITf, 4525 xq_limit-4); 4526 SOC_IF_ERROR_RETURN 4527 (WRITE_HOLCOSPKTRESETLIMITr(unit, port, cos, val)); 4528 4529 val = 0; 4530 soc_reg_field_set(unit, HOLCOSMINXQCNTr, &val, 4531 HOLCOSMINXQCNTf, cos_min_xqs); 4532 SOC_IF_ERROR_RETURN 4533 (WRITE_HOLCOSMINXQCNTr(unit, port, cos, val)); 4534 4535 val = 0; 4536 soc_reg_field_set(unit, LWMCOSCELLSETLIMITr, &val, 4537 CELLSETLIMITf, cos_min_cells); 4538 soc_reg_field_set(unit, LWMCOSCELLSETLIMITr, &val, 4539 CELLRESETLIMITf, cos_min_cells); 4540 SOC_IF_ERROR_RETURN 4541 (WRITE_LWMCOSCELLSETLIMITr(unit, port, cos, val)); 4542 4543 cell_limit = 0; 4544 if(!cos) { 4545 soc_reg_field_set(unit, HOLCOSCELLMAXLIMITr, &cell_limit, 4546 CELLMAXLIMITf, max_cell_limit_pri0); 4547 soc_reg_field_set(unit, HOLCOSCELLMAXLIMITr, &cell_limit, 4548 CELLMAXRESUMELIMITf, max_cell_limit_pri0 - cell_resume_delta); 4549 } else { 4550 if (IS_CPU_PORT(unit, port)) { 4551 /* Ensure 9K bytes packets on queue 1-7 of CPU port */ 4552 soc_reg_field_set(unit, HOLCOSCELLMAXLIMITr, &cell_limit, 4553 CELLMAXLIMITf, 72); 4554 soc_reg_field_set(unit, HOLCOSCELLMAXLIMITr, &cell_limit, 4555 CELLMAXRESUMELIMITf, 60); 4556 } else { 4557 soc_reg_field_set(unit, HOLCOSCELLMAXLIMITr, &cell_limit, 4558 CELLMAXLIMITf, max_cell_limit_pri1_7); 4559 soc_reg_field_set(unit, HOLCOSCELLMAXLIMITr, &cell_limit, 4560 CELLMAXRESUMELIMITf, max_cell_limit_pri1_7 - cell_resume_delta); 4561 } 4562 } 4563 SOC_IF_ERROR_RETURN 4564 (WRITE_HOLCOSCELLMAXLIMITr(unit, port, cos, cell_limit)); 4565 4566 val = 0; 4567 soc_reg_field_set(unit, PGCELLLIMITr, &val, 4568 CELLSETLIMITf, xoff_cell_limit); 4569 soc_reg_field_set(unit, PGCELLLIMITr, &val, 4570 CELLRESETLIMITf, reset_cell_limit); 4571 SOC_IF_ERROR_RETURN 4572 (WRITE_PGCELLLIMITr(unit, port, cos, val)); 4573 4574 val = 0; 4575 soc_reg_field_set(unit, PGDISCARDSETLIMITr, &val, 4576 DISCARDSETLIMITf, mmu_total_cells-1); 4577 SOC_IF_ERROR_RETURN 4578 (WRITE_PGDISCARDSETLIMITr(unit, port, cos, val)); 4579 } 4580 4581 val = 0; 4582 soc_reg_field_set(unit, DYNXQCNTPORTr, &val, 4583 DYNXQCNTPORTf, dyn_xq_per_port); 4584 4585 SOC_IF_ERROR_RETURN(WRITE_DYNXQCNTPORTr(unit, port, val)); 4586 4587 val = 0; 4588 soc_reg_field_set(unit, DYNRESETLIMPORTr, &val, 4589 DYNRESETLIMPORTf, dyn_xq_per_port - 16); 4590 SOC_IF_ERROR_RETURN(WRITE_DYNRESETLIMPORTr(unit, port, val)); 4591 4592 val = 0; 4593 soc_reg_field_set(unit, DYNCELLLIMITr, &val, 4594 DYNCELLSETLIMITf, dyn_cell_limit); 4595 soc_reg_field_set(unit, DYNCELLLIMITr, &val, 4596 DYNCELLRESETLIMITf, dyn_cell_limit - dyn_cell_reset_delta); 4597 SOC_IF_ERROR_RETURN(WRITE_DYNCELLLIMITr(unit, port, val)); 4598 4599 cell_limit = 0; 4600 soc_reg_field_set(unit, TOTALDYNCELLSETLIMITr, 4601 &cell_limit, TOTALDYNCELLSETLIMITf, mmu_total_dyn_cells); 4602 SOC_IF_ERROR_RETURN(WRITE_TOTALDYNCELLSETLIMITr(unit, cell_limit)); 4603 cell_limit = 0; 4604 soc_reg_field_set(unit, TOTALDYNCELLRESETLIMITr, 4605 &cell_limit, TOTALDYNCELLRESETLIMITf, mmu_total_dyn_cells - dyn_cell_reset_delta); 4606 SOC_IF_ERROR_RETURN(WRITE_TOTALDYNCELLRESETLIMITr(unit, cell_limit)); 4607 4608 val = 0; 4609 soc_reg_field_set(unit, IBPPKTSETLIMITr, &val, 4610 PKTSETLIMITf, HR3_MMU_IN_XOFF_PKT); 4611 soc_reg_field_set(unit, IBPPKTSETLIMITr, &val, RESETLIMITSELf, 0); 4612 SOC_IF_ERROR_RETURN(WRITE_IBPPKTSETLIMITr(unit, port, val)); 4613 } 4614 4615 return SOC_E_NONE; 4616 } 4617 4618 STATIC int 4619 _soc_hurricane3_mmu_init(int unit) 4620 { 4621 int cos; 4622 soc_port_t port; 4623 uint32 val; 4624 int age[HR3_NUM_COS], max_age, min_age; 4625 int age_enable, disabled_age; 4626 uint32 limit; /* E2EFC configuration */ 4627 uint16 dev_id; 4628 uint8 rev_id; 4629 int i; 4630 4631 soc_cm_get_id(unit, &dev_id, &rev_id); 4632 4633 SOC_IF_ERROR_RETURN(_soc_hurricane3_tdm_init(unit, dev_id)); 4634 4635 if (soc_property_get(unit, spn_MMU_LOSSLESS, 0)) { 4636 SOC_IF_ERROR_RETURN(_soc_hr3_mmu_init_lossless(unit)); 4637 } else { 4638 SOC_IF_ERROR_RETURN(_soc_hr3_mmu_init_lossy(unit)); 4639 } 4640 4641 if (!(dev_id == BCM53434_DEVICE_ID)) { 4642 PBMP_ALL_ITER(unit, port) { 4643 /* E2EFC configuration */ 4644 if (IS_HG_PORT(unit, port)){ 4645 SOC_IF_ERROR_RETURN(READ_IE2E_CONTROLr(unit, port, &val)); 4646 soc_reg_field_set(unit, IE2E_CONTROLr, &val, IBP_ENABLEf, 1); 4647 SOC_IF_ERROR_RETURN(WRITE_IE2E_CONTROLr(unit, port, val)); 4648 4649 limit = 0; 4650 soc_reg_field_set(unit, E2EFC_CNT_SET_LIMITr, &limit, 4651 PKT_SET_LIMITf, 1456); 4652 soc_reg_field_set(unit, E2EFC_CNT_SET_LIMITr, &limit, 4653 CELL_SET_LIMITf, 9504); 4654 SOC_IF_ERROR_RETURN(WRITE_E2EFC_CNT_SET_LIMITr(unit, port, limit)); 4655 4656 limit = 0; 4657 soc_reg_field_set(unit, E2EFC_CNT_RESET_LIMITr, &limit, 4658 PKT_RESET_LIMITf, 1456); 4659 soc_reg_field_set(unit, E2EFC_CNT_RESET_LIMITr, &limit, 4660 CELL_RESET_LIMITf, 9504); 4661 SOC_IF_ERROR_RETURN(WRITE_E2EFC_CNT_RESET_LIMITr(unit, port, limit)); 4662 4663 limit = 0; 4664 soc_reg_field_set(unit, E2EFC_CNT_DISC_LIMITr, &limit, 4665 PKT_DISC_LIMITf, 1456); 4666 soc_reg_field_set(unit, E2EFC_CNT_DISC_LIMITr, &limit, 4667 CELL_DISC_LIMITf, 9504); 4668 SOC_IF_ERROR_RETURN(WRITE_E2EFC_CNT_DISC_LIMITr(unit, port, limit)); 4669 } else { 4670 limit = 0; 4671 soc_reg_field_set(unit, E2EFC_CNT_SET_LIMITr, &limit, 4672 PKT_SET_LIMITf, 12); 4673 soc_reg_field_set(unit, E2EFC_CNT_SET_LIMITr, &limit, 4674 CELL_SET_LIMITf, 80); 4675 SOC_IF_ERROR_RETURN(WRITE_E2EFC_CNT_SET_LIMITr(unit, port, limit)); 4676 4677 limit = 0; 4678 soc_reg_field_set(unit, E2EFC_CNT_RESET_LIMITr, &limit, 4679 PKT_RESET_LIMITf, 9); 4680 soc_reg_field_set(unit, E2EFC_CNT_RESET_LIMITr, &limit, 4681 CELL_RESET_LIMITf, 60); 4682 SOC_IF_ERROR_RETURN(WRITE_E2EFC_CNT_RESET_LIMITr(unit, port, limit)); 4683 4684 limit = 0; 4685 soc_reg_field_set(unit, E2EFC_CNT_DISC_LIMITr, &limit, 4686 PKT_DISC_LIMITf, 1456); 4687 soc_reg_field_set(unit, E2EFC_CNT_DISC_LIMITr, &limit, 4688 CELL_DISC_LIMITf, 9504); 4689 SOC_IF_ERROR_RETURN(WRITE_E2EFC_CNT_DISC_LIMITr(unit, port, limit)); 4690 } 4691 } 4692 4693 /* E2EFC configuration */ 4694 SOC_IF_ERROR_RETURN(READ_E2EFC_IBP_ENr(unit, &val)); 4695 soc_reg_field_set(unit, E2EFC_IBP_ENr, &val, ENf, 1); 4696 SOC_IF_ERROR_RETURN(WRITE_E2EFC_IBP_ENr(unit, val)); 4697 4698 for (i = 0; i < SOC_REG_NUMELS(unit, E2EFC_HG_MIN_TX_TIMERr); i++) { 4699 SOC_IF_ERROR_RETURN(READ_E2EFC_HG_MIN_TX_TIMERr(unit, i, &val)); 4700 soc_reg_field_set(unit, E2EFC_HG_MIN_TX_TIMERr, &val, LGf, 0); 4701 soc_reg_field_set(unit, E2EFC_HG_MIN_TX_TIMERr, &val, TIMERf, 64); 4702 SOC_IF_ERROR_RETURN(WRITE_E2EFC_HG_MIN_TX_TIMERr(unit, i, val)); 4703 } 4704 4705 for (i = 0; i < SOC_REG_NUMELS(unit, E2EFC_HG_MAX_TX_TIMERr); i++) { 4706 SOC_IF_ERROR_RETURN(READ_E2EFC_HG_MAX_TX_TIMERr(unit, i, &val)); 4707 soc_reg_field_set(unit, E2EFC_HG_MAX_TX_TIMERr, &val, LGf, 1); 4708 soc_reg_field_set(unit, E2EFC_HG_MAX_TX_TIMERr, &val, TIMERf, 640); 4709 SOC_IF_ERROR_RETURN(WRITE_E2EFC_HG_MAX_TX_TIMERr(unit, i, val)); 4710 } 4711 } 4712 4713 /* 4714 * Configure per-XQ packet aging for the various COSQs. 4715 * 4716 * The shortest age allowed by H/W is 250 microseconds. 4717 * The longest age allowed is 7.162 seconds (7162 msec). 4718 * The maximum ratio between the longest age and the shortest 4719 * (nonzero) age is 7:2. 4720 */ 4721 age_enable = disabled_age = max_age = 0; 4722 min_age = 7162; 4723 for (cos = 0; cos < NUM_COS(unit); cos++) { 4724 if ((age[cos] = 4725 soc_property_suffix_num_get(unit, cos, spn_MMU_XQ_AGING, 4726 "cos", 0)) > 0) { 4727 age_enable = 1; 4728 if (age[cos] > 7162) { 4729 age[cos] = 7162; 4730 } 4731 if (age[cos] < min_age) { 4732 min_age = age[cos]; 4733 } 4734 } else { 4735 disabled_age = 1; 4736 age[cos] = 0; 4737 } 4738 if (age[cos] > max_age) { 4739 max_age = age[cos]; 4740 } 4741 } 4742 if (!age_enable) { 4743 /* Disable packet aging on all COSQs */ 4744 SOC_IF_ERROR_RETURN(WRITE_PKTAGINGTIMERr(unit, 0)); 4745 SOC_IF_ERROR_RETURN(WRITE_PKTAGINGLIMITr(unit, 0)); /* Aesthetic */ 4746 } else { 4747 uint32 regval = 0; 4748 uint32 timerval; 4749 4750 /* Enforce the 7:2 ratio between min and max values */ 4751 if ((((max_age * 2)+6) / 7) > min_age) { 4752 /* Keep requested max age; make min_age comply */ 4753 min_age = ((max_age * 2) + 6) / 7; 4754 } 4755 4756 /* 4757 * Give up granularity for range, if we need to 4758 * "disable" (max out) aging for any COSQ(s). 4759 */ 4760 if (disabled_age) { 4761 /* Max range */ 4762 max_age = min_age * 7 / 2; 4763 } 4764 4765 /* 4766 * Compute shortest duration of one PKTAGINGTIMERr cycle. 4767 * This duration is 1/7th of the longest packet age. 4768 * This duration is in units of 125 usec (msec * 8). 4769 */ 4770 timerval = ((8 * max_age) + 6) / 7; 4771 SOC_IF_ERROR_RETURN(WRITE_PKTAGINGTIMERr(unit, timerval)); 4772 4773 for (cos = 0; cos < NUM_COS(unit); cos++) { 4774 if (!age[cos]) { 4775 /* 4776 * Requested to be disabled, but cannot disable individual 4777 * COSQs once packet aging is enabled. Therefore, mark 4778 * this COSQ's aging duration as maxed out. 4779 */ 4780 age[cos] = -1; 4781 } else if (age[cos] < min_age) { 4782 age[cos] = min_age; 4783 } 4784 4785 /* Normalize each "age" into # of PKTAGINGTIMERr cycles. */ 4786 if (age[cos] > 0) { 4787 /* coverity[divide_by_zero : FALSE] */ 4788 age[cos] = ((8 * age[cos]) + timerval - 1) / timerval; 4789 } 4790 else { 4791 age[cos] = 7; 4792 } 4793 /* Format each "age" for its appropriate field */ 4794 regval |= ((7 - age[cos]) << (cos * 3)); 4795 } 4796 SOC_IF_ERROR_RETURN(WRITE_PKTAGINGLIMITr(unit, regval)); 4797 } 4798 4799 /* 4800 * Port enable 4801 */ 4802 val = 0; 4803 soc_reg_field_set(unit, MMUPORTENABLEr, &val, MMUPORTENABLEf, 4804 SOC_PBMP_WORD_GET(PBMP_ALL(unit), 0)); 4805 SOC_IF_ERROR_RETURN(WRITE_MMUPORTENABLEr(unit, val)); 4806 4807 return SOC_E_NONE; 4808 } 4809 4810 /* soc_hurricane3_tsc_core_reset() 4811 * - to reset TSCE or QTC on Hurricane3 4812 */ 4813 int 4814 soc_hurricane3_tsc_core_reset(int unit, int port, int reset_delay_us) 4815 { 4816 int phy_id, block_idx, is_qtc; 4817 4818 phy_id = SOC_INFO(unit).port_l2p_mapping[port]; 4819 if (phy_id <= 17 && phy_id>=2) { 4820 block_idx = 13; 4821 is_qtc = 1; 4822 } else if (phy_id <=33 && phy_id >=18) { 4823 block_idx = 14; 4824 is_qtc = 1; 4825 } else if (phy_id <=37 && phy_id >=34) { 4826 is_qtc = 0; 4827 } else if (phy_id <=39 && phy_id >=38) { 4828 is_qtc = 0; 4829 } else { 4830 return SOC_E_PARAM; 4831 } 4832 4833 if (is_qtc) { 4834 block_idx = block_idx | SOC_REG_ADDR_BLOCK_ID_MASK; 4835 SOC_IF_ERROR_RETURN(soc_tsc_xgxs_reset(unit, block_idx, 0)); 4836 } else { 4837 /* TSCE */ 4838 SOC_IF_ERROR_RETURN(soc_tsc_xgxs_reset(unit, port, 0)); 4839 } 4840 return SOC_E_NONE; 4841 } 4842 4843 /* soc_hurricane3_tsc_reset() 4844 * - to reset TSCE and QTC on Hurricane3 4845 */ 4846 int 4847 soc_hurricane3_tsc_reset(int unit) 4848 { 4849 int blk, port; 4850 uint32 rval; 4851 4852 if (SOC_USE_PORTCTRL(unit)) { 4853 return SOC_E_NONE; 4854 } 4855 if (soc_feature(unit, soc_feature_wh2)) { 4856 return soc_wolfhound2_port_reset(unit); 4857 } 4858 /* Reset QTC */ 4859 SOC_BLOCK_ITER(unit, blk, SOC_BLK_PMQ) { 4860 port = blk | SOC_REG_ADDR_BLOCK_ID_MASK; 4861 SOC_IF_ERROR_RETURN(soc_tsc_xgxs_reset(unit, port, 0)); 4862 } 4863 4864 /* Reset TSCE */ 4865 SOC_BLOCK_ITER(unit, blk, SOC_BLK_XLPORT) { 4866 port = SOC_BLOCK_PORT(unit, blk); 4867 SOC_IF_ERROR_RETURN(soc_tsc_xgxs_reset(unit, port, 0)); 4868 } 4869 4870 SOC_BLOCK_ITER(unit, blk, SOC_BLK_XLPORT) { 4871 port = SOC_BLOCK_PORT(unit, blk); 4872 if (port == -1 || port == REG_PORT_ANY) { 4873 continue; 4874 } 4875 SOC_IF_ERROR_RETURN(READ_XLPORT_MAC_CONTROLr(unit, port, &rval)); 4876 soc_reg_field_set(unit, XLPORT_MAC_CONTROLr, &rval, XMAC0_RESETf, 1); 4877 SOC_IF_ERROR_RETURN(WRITE_XLPORT_MAC_CONTROLr(unit, port, rval)); 4878 sal_udelay(10); 4879 soc_reg_field_set(unit, XLPORT_MAC_CONTROLr, &rval, XMAC0_RESETf, 0); 4880 SOC_IF_ERROR_RETURN(WRITE_XLPORT_MAC_CONTROLr(unit, port, rval)); 4881 } 4882 4883 return SOC_E_NONE; 4884 } 4885 4886 /* soc_hurricane3_sbus_tsc_block() 4887 * - to report the valid blk of this port for wc_ucmem_data 4888 * (i.e. GPORT/XLPORT_WC_UCMEM_DATAm)access process. 4889 * 4890 * - Parameters : 4891 * phy_port(IN) : physical port. 4892 * blk(OUT) : the valid block 4893 */ 4894 int 4895 soc_hurricane3_sbus_tsc_block(int unit, int phy_port, int *blk) 4896 { 4897 soc_info_t *si = &SOC_INFO(unit); 4898 4899 if (SOC_PORT_BLOCK_TYPE(unit, phy_port) == SOC_BLK_GPORT) { 4900 if ((phy_port >= qtc_phy_port[0]) && 4901 (phy_port < qtc_phy_port[1])) { 4902 *blk = si->pmq_block[0]; 4903 } else if ((phy_port >= qtc_phy_port[1]) && 4904 (phy_port < tsc_phy_port[0])) { 4905 *blk = si->pmq_block[1]; 4906 } else { 4907 return SOC_E_PARAM; 4908 } 4909 } else { 4910 *blk = SOC_PORT_BLOCK(unit, phy_port); 4911 } 4912 4913 return SOC_E_NONE; 4914 } 4915 4916 extern int (*_phy_tsce_firmware_set_helper[SOC_MAX_NUM_DEVICES])(int, int, uint8 *, int); 4917 extern int (*_phy_qtce_firmware_set_helper[SOC_MAX_NUM_DEVICES])(int, int, uint8 *, int); 4918 4919 STATIC int 4920 _soc_hurricane3_tscx_firmware_set(int unit, int port, uint8 *array, int datalen) 4921 { 4922 soc_mem_t mem = IS_XL_PORT(unit, port) ? 4923 XLPORT_WC_UCMEM_DATAm : GPORT_WC_UCMEM_DATAm; 4924 soc_reg_t reg = IS_XL_PORT(unit, port) ? 4925 XLPORT_WC_UCMEM_CTRLr : GPORT_WC_UCMEM_CTRLr; 4926 4927 return soc_warpcore_firmware_set(unit, port, array, datalen, 0, mem, reg); 4928 } 4929 4930 #define TSC_REG_ADDR_TSCID_SET(_phy_reg, _phyad) \ 4931 ((_phy_reg) |= ((_phyad) & 0x1f) << 19) 4932 4933 STATIC int 4934 _soc_hurricane3_mdio_addr_to_port(uint32 phy_addr) 4935 { 4936 int bus, offset; 4937 int mdio_addr; 4938 4939 /* Must be internal MDIO address */ 4940 if ((phy_addr & 0x80) == 0) { 4941 return 0; 4942 } 4943 4944 bus = PHY_ID_BUS_NUM(phy_addr); 4945 mdio_addr = phy_addr & 0x1f; 4946 4947 if (bus == 0) { 4948 if (mdio_addr <= 0x8) { 4949 offset = 9; 4950 } else { 4951 offset = 17; 4952 } 4953 } else if (bus == 1) { 4954 if (mdio_addr <= 0x8) { 4955 offset = 33; 4956 } else if (mdio_addr <= 0xc) { 4957 offset = -7; 4958 } else { 4959 offset = 5; 4960 } 4961 } else { 4962 return 0; 4963 } 4964 4965 return mdio_addr + offset; 4966 } 4967 4968 STATIC int 4969 _soc_hurricane3_tscx_reg_read(int unit, uint32 phy_addr, 4970 uint32 phy_reg, uint32 *phy_data) 4971 { 4972 int rv, blk, port; 4973 int phy_port = _soc_hurricane3_mdio_addr_to_port(phy_addr); 4974 4975 port = SOC_INFO(unit).port_p2l_mapping[phy_port]; 4976 4977 SOC_IF_ERROR_RETURN 4978 (soc_hurricane3_sbus_tsc_block(unit, phy_port, &blk)); 4979 4980 LOG_INFO(BSL_LS_SOC_MII, 4981 (BSL_META_U(unit, 4982 "soc_hurricane3_tscx_reg_read[%d]: 0x%X/0x%X/%d/%d/%d\n"), 4983 unit, phy_addr, phy_reg,phy_port, port, blk)); 4984 4985 TSC_REG_ADDR_TSCID_SET(phy_reg, phy_addr); 4986 rv = soc_sbus_tsc_reg_read(unit, port, blk, phy_addr, 4987 phy_reg, phy_data); 4988 4989 return rv; 4990 } 4991 4992 STATIC int 4993 _soc_hurricane3_tscx_reg_write(int unit, uint32 phy_addr, 4994 uint32 phy_reg, uint32 phy_data) 4995 { 4996 int rv, blk, port; 4997 int phy_port = _soc_hurricane3_mdio_addr_to_port(phy_addr); 4998 4999 port = SOC_INFO(unit).port_p2l_mapping[phy_port]; 5000 5001 SOC_IF_ERROR_RETURN 5002 (soc_hurricane3_sbus_tsc_block(unit, phy_port, &blk)); 5003 5004 LOG_INFO(BSL_LS_SOC_MII, 5005 (BSL_META_U(unit, 5006 "soc_hurricane3_tscx_reg_read[%d]: 0x%X/0x%X/%d/%d/%d\n"), 5007 unit, phy_addr, phy_reg, phy_port, port, blk)); 5008 5009 TSC_REG_ADDR_TSCID_SET(phy_reg, phy_addr); 5010 rv = soc_sbus_tsc_reg_write(unit, port, blk, phy_addr, 5011 phy_reg, phy_data); 5012 5013 return rv; 5014 } 5015 5016 #define NUM_XLPORT 4 5017 5018 /* 5019 * Function: 5020 * _soc_hurricane3_mib_reset() 5021 * Purpose: 5022 * Reset MIB counter 5023 */ 5024 STATIC int 5025 _soc_hurricane3_mib_reset(int unit) 5026 { 5027 uint32 rval, fval; 5028 int blk, bindex; 5029 soc_info_t *si = &SOC_INFO(unit); 5030 int blk_port, phy_port; 5031 5032 if (SOC_USE_PORTCTRL(unit)) { 5033 return SOC_E_NONE; 5034 } 5035 5036 /* Reset XLPORT MIB counter (registers implemented in memory). The clear 5037 * function is implemented with read-modify-write, parity needs to be 5038 * disabled */ 5039 SOC_BLOCK_ITER(unit, blk, SOC_BLK_XLPORT) { 5040 blk_port = SOC_BLOCK_PORT(unit, blk); 5041 if (blk_port < 0) { 5042 continue; 5043 } 5044 phy_port = si->port_l2p_mapping[blk_port]; 5045 fval = 0; 5046 for (bindex = 0; bindex < 4; bindex++) { 5047 if (si->port_p2l_mapping[phy_port + bindex] != -1) { 5048 fval |= 1 << bindex; 5049 } 5050 } 5051 rval = 0; 5052 soc_reg_field_set(unit, XLPORT_MIB_RESETr, &rval, CLR_CNTf, fval); 5053 SOC_IF_ERROR_RETURN(WRITE_XLPORT_MIB_RESETr(unit, blk_port, rval)); 5054 SOC_IF_ERROR_RETURN(WRITE_XLPORT_MIB_RESETr(unit, blk_port, 0)); 5055 } 5056 5057 return SOC_E_NONE; 5058 } 5059 5060 /* 5061 * Function: 5062 * _soc_hurricane3_gport_tdm_mode_init() 5063 * Purpose: 5064 * Initialize the TDM mode of each PGW_GE blocks 5065 */ 5066 STATIC int 5067 _soc_hurricane3_gport_tdm_mode_init(int unit) 5068 { 5069 uint32 rval, fval; 5070 int blk, bindex; 5071 int blk_port; 5072 5073 /* Confiure the GPORT GP0/GP1 bus TDM mode */ 5074 SOC_BLOCK_ITER(unit, blk, SOC_BLK_PGW_GE) { 5075 bindex = SOC_BLOCK_NUMBER(unit, blk); 5076 blk_port = bindex | SOC_REG_ADDR_INSTANCE_MASK; 5077 /* port 0 ~port 7 */ 5078 SOC_IF_ERROR_RETURN(READ_PGW_GE0_MODE_REGr(unit, blk_port, &rval)); 5079 fval = 0; 5080 switch (_hr3_qtc_gport_port_count[bindex][0]) { 5081 case SOC_HR3_PORT_RATIO_OCTAL: 5082 fval = 8; 5083 break; 5084 case SOC_HR3_PORT_RATIO_QUAD: 5085 fval = 4; 5086 break; 5087 case SOC_HR3_PORT_RATIO_DUAL_1_1: 5088 fval = 2; 5089 break; 5090 case SOC_HR3_PORT_RATIO_SINGLE: 5091 fval = 1; 5092 break; 5093 default: 5094 break; 5095 } 5096 soc_reg_field_set(unit, PGW_GE0_MODE_REGr, &rval, GP0_TDM_MODEf, fval); 5097 SOC_IF_ERROR_RETURN(WRITE_PGW_GE0_MODE_REGr(unit, blk_port, rval)); 5098 5099 /* port 8 ~ port 15 */ 5100 SOC_IF_ERROR_RETURN(READ_PGW_GE1_MODE_REGr(unit, blk_port, &rval)); 5101 fval = 0; 5102 switch (_hr3_qtc_gport_port_count[bindex][1]) { 5103 case SOC_HR3_PORT_RATIO_OCTAL: 5104 fval = 8; 5105 break; 5106 case SOC_HR3_PORT_RATIO_QUAD: 5107 fval = 4; 5108 break; 5109 case SOC_HR3_PORT_RATIO_DUAL_1_1: 5110 fval = 2; 5111 break; 5112 case SOC_HR3_PORT_RATIO_SINGLE: 5113 fval = 1; 5114 break; 5115 default: 5116 break; 5117 } 5118 soc_reg_field_set(unit, PGW_GE0_MODE_REGr, &rval, GP0_TDM_MODEf, fval); 5119 SOC_IF_ERROR_RETURN(WRITE_PGW_GE1_MODE_REGr(unit, blk_port, rval)); 5120 } 5121 5122 return SOC_E_NONE; 5123 } 5124 5125 5126 /* 5127 * Function: 5128 * _soc_hurricane3_gmac_init() 5129 * Purpose: 5130 * To init GMAC (should be moved to mac) 5131 */ 5132 STATIC int 5133 _soc_hurricane3_gmac_init(int unit) 5134 { 5135 uint32 rval; 5136 uint32 prev_reg_addr; 5137 int port; 5138 5139 if (SOC_USE_PORTCTRL(unit)) { 5140 return SOC_E_NONE; 5141 } 5142 5143 rval = 0; 5144 soc_reg_field_set(unit, GPORT_CONFIGr, &rval, CLR_CNTf, 1); 5145 soc_reg_field_set(unit, GPORT_CONFIGr, &rval, GPORT_ENf, 1); 5146 5147 prev_reg_addr = 0xffffffff; 5148 PBMP_E_ITER(unit, port) { 5149 uint32 reg_addr; 5150 if (IS_XL_PORT(unit, port)) { 5151 continue; 5152 } 5153 5154 reg_addr = soc_reg_addr(unit, GPORT_CONFIGr, port, 0); 5155 if (reg_addr != prev_reg_addr) { 5156 SOC_IF_ERROR_RETURN(WRITE_GPORT_CONFIGr(unit, port, rval)); 5157 prev_reg_addr = reg_addr; 5158 } 5159 } 5160 5161 prev_reg_addr = 0xffffffff; 5162 soc_reg_field_set(unit, GPORT_CONFIGr, &rval, CLR_CNTf, 0); 5163 PBMP_E_ITER(unit, port) { 5164 uint32 reg_addr; 5165 if (IS_XL_PORT(unit, port)) { 5166 continue; 5167 } 5168 5169 reg_addr = soc_reg_addr(unit, GPORT_CONFIGr, port, 0); 5170 if (reg_addr != prev_reg_addr) { 5171 SOC_IF_ERROR_RETURN(WRITE_GPORT_CONFIGr(unit, port, rval)); 5172 prev_reg_addr = reg_addr; 5173 } 5174 } 5175 5176 return SOC_E_NONE; 5177 } 5178 5179 /* 5180 * Function: 5181 * _soc_hurricane3_higig_mode_init() 5182 * Purpose: 5183 * To init the default Higig mode for HG port 5184 */ 5185 STATIC int 5186 _soc_hurricane3_higig_mode_init(int unit) 5187 { 5188 uint32 rval; 5189 int port; 5190 5191 PBMP_PORT_ITER(unit, port) { 5192 if (!IS_HG_PORT(unit, port)) { 5193 continue; 5194 } 5195 5196 if (!SOC_USE_PORTCTRL(unit)) { 5197 /* Section below is used to config XLPORT HiGig encap 5198 * setting for normal init process. 5199 */ 5200 SOC_IF_ERROR_RETURN(READ_XLPORT_CONFIGr(unit, port, &rval)); 5201 soc_reg_field_set(unit, XLPORT_CONFIGr, &rval, HIGIG_MODEf, 1); 5202 SOC_IF_ERROR_RETURN(WRITE_XLPORT_CONFIGr(unit, port, rval)); 5203 } 5204 5205 /* PGW encap setting */ 5206 SOC_IF_ERROR_RETURN(soc_greyhound_pgw_encap_field_modify(unit, 5207 port, HIGIG_MODEf, 1)); 5208 } 5209 5210 return SOC_E_NONE; 5211 } 5212 5213 /* 5214 * Function: 5215 * _soc_hurricane3_xlport_init() 5216 * Purpose: 5217 * To init the XLPORT block 5218 * Parameters : 5219 * blk(IN): XLPORT block 5220 * mode(IN): port mode. SOC_HR3_PORT_MODE_XXX. 5221 */ 5222 STATIC int 5223 _soc_hurricane3_xlport_init(int unit, int blk, int mode) 5224 { 5225 static const soc_field_t port_field[] = { 5226 PORT0f, PORT1f, PORT2f, PORT3f 5227 }; 5228 uint32 rval; 5229 int port; 5230 int phy_port_base; 5231 int bindex; 5232 soc_info_t *si = &SOC_INFO(unit); 5233 5234 5235 if (SOC_USE_PORTCTRL(unit)) { 5236 return SOC_E_NONE; 5237 } 5238 5239 port = SOC_BLOCK_PORT(unit, blk); 5240 if (port == -1 || port == REG_PORT_ANY) { 5241 return SOC_E_PARAM; 5242 } 5243 5244 phy_port_base = si->port_l2p_mapping[port]; 5245 5246 /* Assert XLPORT soft reset */ 5247 rval = 0; 5248 for (bindex = 0; bindex < NUM_XLPORT; bindex++) { 5249 if (si->port_p2l_mapping[phy_port_base + bindex] != -1) { 5250 soc_reg_field_set(unit, XLPORT_SOFT_RESETr, &rval, 5251 port_field[bindex], 1); 5252 } 5253 } 5254 SOC_IF_ERROR_RETURN(WRITE_XLPORT_SOFT_RESETr(unit, port, rval)); 5255 5256 /* Set XLPORT mode */ 5257 rval = 0; 5258 soc_reg_field_set(unit, XLPORT_MODE_REGr, &rval, 5259 XPORT0_CORE_PORT_MODEf, mode); 5260 soc_reg_field_set(unit, XLPORT_MODE_REGr, &rval, 5261 XPORT0_PHY_PORT_MODEf, mode); 5262 SOC_IF_ERROR_RETURN(WRITE_XLPORT_MODE_REGr(unit, port, rval)); 5263 5264 /* De-assert XLPORT soft reset */ 5265 SOC_IF_ERROR_RETURN(WRITE_XLPORT_SOFT_RESETr(unit, port, 0)); 5266 5267 /* Enable XLPORT */ 5268 rval = 0; 5269 for (bindex = 0; bindex < NUM_XLPORT; bindex++) { 5270 if (si->port_p2l_mapping[phy_port_base + bindex] != -1) { 5271 soc_reg_field_set(unit, XLPORT_ENABLE_REGr, &rval, 5272 port_field[bindex], 1); 5273 } 5274 } 5275 SOC_IF_ERROR_RETURN(WRITE_XLPORT_ENABLE_REGr(unit, port, rval)); 5276 5277 return SOC_E_NONE; 5278 } 5279 5280 #define _hr3_get_pval(_map_, _idx_, _max_num_) \ 5281 ((_idx_ < _max_num_) ? _map_[_idx_]: 0) 5282 5283 #define _HR3_PGW_COUNT_GE (2) 5284 #define _HR3_PORTS_PER_PGW_GE (16) 5285 #define _HR3_FIRST_PORT_PGW_GE0 (2) 5286 #define _HR3_PGW_COUNT_XL (2) 5287 #define _HR3_PORTS_PER_PGW_XL (4) 5288 #define _HR3_FIRST_PORT_PGW_XL0 (34) 5289 5290 STATIC int 5291 _soc_hurricane3_ledup_init(int unit) 5292 { 5293 int i, j, pval0, pval1, pval2, pval3, port_idx; 5294 uint32 led_remap[64] = {0}, port_cnt = 0, rval = 0, disable_4x10 = 0; 5295 5296 struct led_remap_t { 5297 uint32 reg_addr; 5298 uint32 port0; 5299 uint32 port1; 5300 uint32 port2; 5301 uint32 port3; 5302 } ledup0_remap_r[] = { 5303 {CMIC_LEDUP0_PORT_ORDER_REMAP_0_3r, 5304 REMAP_PORT_0f, REMAP_PORT_1f, REMAP_PORT_2f, REMAP_PORT_3f}, 5305 {CMIC_LEDUP0_PORT_ORDER_REMAP_4_7r, 5306 REMAP_PORT_4f, REMAP_PORT_5f, REMAP_PORT_6f, REMAP_PORT_7f}, 5307 {CMIC_LEDUP0_PORT_ORDER_REMAP_8_11r, 5308 REMAP_PORT_8f, REMAP_PORT_9f, REMAP_PORT_10f, REMAP_PORT_11f}, 5309 {CMIC_LEDUP0_PORT_ORDER_REMAP_12_15r, 5310 REMAP_PORT_12f, REMAP_PORT_13f, REMAP_PORT_14f, REMAP_PORT_15f}, 5311 {CMIC_LEDUP0_PORT_ORDER_REMAP_16_19r, 5312 REMAP_PORT_16f, REMAP_PORT_17f, REMAP_PORT_18f, REMAP_PORT_19f}, 5313 {CMIC_LEDUP0_PORT_ORDER_REMAP_20_23r, 5314 REMAP_PORT_20f, REMAP_PORT_21f, REMAP_PORT_22f, REMAP_PORT_23f}, 5315 {CMIC_LEDUP0_PORT_ORDER_REMAP_24_27r, 5316 REMAP_PORT_24f, REMAP_PORT_25f, REMAP_PORT_26f, REMAP_PORT_27f}, 5317 {CMIC_LEDUP0_PORT_ORDER_REMAP_28_31r, 5318 REMAP_PORT_28f, REMAP_PORT_29f, REMAP_PORT_30f, REMAP_PORT_31f}, 5319 {CMIC_LEDUP0_PORT_ORDER_REMAP_32_35r, 5320 REMAP_PORT_32f, REMAP_PORT_33f, REMAP_PORT_34f, REMAP_PORT_35f}, 5321 {CMIC_LEDUP0_PORT_ORDER_REMAP_36_39r, 5322 REMAP_PORT_36f, REMAP_PORT_37f, REMAP_PORT_38f, REMAP_PORT_39f}, 5323 {CMIC_LEDUP0_PORT_ORDER_REMAP_40_43r, 5324 REMAP_PORT_40f, REMAP_PORT_41f, REMAP_PORT_42f, REMAP_PORT_43f} 5325 }; 5326 5327 /* The LED scanning out order is 5328 * PGW_XL1(41->38) -> PGW_XL0(37->34) -> PGW_GE1(18->33) -> PGW_GE0(2->17) 5329 * If PM4x10 is ON, PGW_XL will output 4 bytes LED status to the LED chain. 5330 * If PM4x10 is OFF, PGW_XL will output 1 byte to the LED chain. 5331 * PGW_GE always outputs 16 bytes. 5332 */ 5333 5334 SOC_IF_ERROR_RETURN(READ_PGW_CTRL_0r(unit, &rval)); 5335 disable_4x10 = soc_reg_field_get(unit, PGW_CTRL_0r, 5336 rval, SW_PM4X10_DISABLEf); 5337 5338 /* PGW_XL1 -> PGW_XL0 */ 5339 for (i = _HR3_PGW_COUNT_XL - 1; i >= 0; i--) { 5340 if (disable_4x10 & (1 << i)) { 5341 /* For PGW_XL, shift out 1 byte if PM4x10 is disabled */ 5342 led_remap[port_cnt++] = 0; 5343 } else { 5344 /* For PGW_XL, port 3 is shifted out first and port 0 is the last */ 5345 for (j = _HR3_PORTS_PER_PGW_XL - 1; j >= 0; j--) { 5346 led_remap[port_cnt++] = 5347 _HR3_FIRST_PORT_PGW_XL0 + _HR3_PORTS_PER_PGW_XL * i + j; 5348 } 5349 } 5350 } 5351 5352 /* PGW_GE1 -> PGW_GE0 */ 5353 for (i = _HR3_PGW_COUNT_GE - 1; i >= 0; i--) { 5354 /* For PGW_GE, port 0 is shifted out first and port 15 is the last */ 5355 for (j = 0; j < _HR3_PORTS_PER_PGW_GE; j++) { 5356 led_remap[port_cnt++] = 5357 _HR3_FIRST_PORT_PGW_GE0 + _HR3_PORTS_PER_PGW_GE * i + j; 5358 } 5359 } 5360 5361 /* Setup CMIC_LEDUP0_PORT_ORDER_REMAP registers */ 5362 for (i = 0; i < sizeof(ledup0_remap_r)/sizeof(ledup0_remap_r[0]); i++) { 5363 port_idx = i * 4; 5364 pval0 = _hr3_get_pval(led_remap, port_idx, port_cnt); 5365 pval1 = _hr3_get_pval(led_remap, port_idx + 1, port_cnt); 5366 pval2 = _hr3_get_pval(led_remap, port_idx + 2, port_cnt); 5367 pval3 = _hr3_get_pval(led_remap, port_idx + 3, port_cnt); 5368 5369 rval = 0; 5370 soc_reg_field_set(unit, ledup0_remap_r[i].reg_addr, &rval, 5371 ledup0_remap_r[i].port0, pval0); 5372 soc_reg_field_set(unit, ledup0_remap_r[i].reg_addr, &rval, 5373 ledup0_remap_r[i].port1, pval1); 5374 soc_reg_field_set(unit, ledup0_remap_r[i].reg_addr, &rval, 5375 ledup0_remap_r[i].port2, pval2); 5376 soc_reg_field_set(unit, ledup0_remap_r[i].reg_addr, &rval, 5377 ledup0_remap_r[i].port3, pval3); 5378 5379 /* coverity[result_independent_of_operands] */ 5380 SOC_IF_ERROR_RETURN 5381 (soc_pci_write(unit, 5382 soc_reg_addr(unit, ledup0_remap_r[i].reg_addr, REG_PORT_ANY, 0), 5383 rval)); 5384 } 5385 5386 /* Initialize the LEDuP0 data ram */ 5387 rval = 0; 5388 for (i = 0; i < 256; i++) { 5389 /* coverity[result_independent_of_operands] */ 5390 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP0_DATA_RAMr(unit, i, rval)); 5391 } 5392 5393 return SOC_E_NONE; 5394 } 5395 5396 STATIC int 5397 _soc_hurricane3_misc_init(int unit) 5398 { 5399 uint32 rval, fval, l2_ovf_enable, l2_tbl_size; 5400 uint64 reg64; 5401 int port; 5402 uint32 entry[SOC_MAX_MEM_WORDS]; 5403 soc_field_t fields[3]; 5404 uint32 values[3]; 5405 int blk, mode; 5406 int phy_port_base; 5407 soc_info_t *si = &SOC_INFO(unit); 5408 int delay; 5409 int freq, target_freq, divisor, dividend; 5410 int parity_enable; 5411 char *board_name; 5412 5413 if (!SOC_IS_RELOADING(unit) && !SOC_WARM_BOOT(unit)) { 5414 /* Clear IPIPE/EIPIE Memories */ 5415 SOC_IF_ERROR_RETURN(soc_hurricane3_pipe_mem_clear(unit)); 5416 5417 /* GPORT bus TDM mode */ 5418 SOC_IF_ERROR_RETURN(_soc_hurricane3_gport_tdm_mode_init(unit)); 5419 5420 /* Clear MIB counter */ 5421 SOC_IF_ERROR_RETURN(_soc_hurricane3_mib_reset(unit)); 5422 } 5423 5424 SOC_IF_ERROR_RETURN(soc_hurricane3_init_port_mapping(unit)); 5425 5426 parity_enable = soc_property_get(unit, spn_PARITY_ENABLE, TRUE); 5427 /* Do the ser register w/o checking parity_enable. 5428 OAM and l2 overflow interrupt will be dispatched from 5429 _soc_ser_parity_error_cmicm_intr_f */ 5430 soc_hr3_ser_register(unit); 5431 if (parity_enable) { 5432 SOC_IF_ERROR_RETURN(soc_hr3_tcam_ser_init(unit)); 5433 /* Enabling the packet drop when parity error occurred */ 5434 SOC_IF_ERROR_RETURN(READ_IPIPE_PERR_CONTROLr(unit, &rval)); 5435 fval = 1; 5436 soc_reg_field_set(unit, IPIPE_PERR_CONTROLr, &rval, DROPf, fval); 5437 SOC_IF_ERROR_RETURN(WRITE_IPIPE_PERR_CONTROLr(unit, rval)); 5438 SOC_IF_ERROR_RETURN(soc_hr3_ser_enable_all(unit, TRUE)); 5439 #if defined(SER_TR_TEST_SUPPORT) 5440 soc_hr3_ser_test_register(unit); 5441 #endif /* SER_TR_TEST_SUPPORT */ 5442 } else { 5443 SOC_IF_ERROR_RETURN(soc_hr3_ser_enable_all(unit, FALSE)); 5444 } 5445 5446 /* Enable L2 overflow bucket */ 5447 l2_tbl_size = soc_property_get(unit, spn_L2_TABLE_SIZE, FALSE); 5448 if (l2_tbl_size == (soc_mem_index_count(unit, L2Xm) + 5449 soc_mem_index_count(unit, L2_ENTRY_OVERFLOWm))) { 5450 /* 5451 * if l2 table size equals to l2 table size + l2 overflow table size, 5452 * it indicates the l2 overflow table is enabled. 5453 */ 5454 l2_ovf_enable = 1; 5455 } else { 5456 l2_ovf_enable = 0; 5457 } 5458 SOC_IF_ERROR_RETURN(READ_L2_LEARN_CONTROLr(unit, &rval)); 5459 soc_reg_field_set(unit, L2_LEARN_CONTROLr, &rval, 5460 OVERFLOW_BUCKET_ENABLEf, l2_ovf_enable); 5461 SOC_IF_ERROR_RETURN(WRITE_L2_LEARN_CONTROLr(unit, rval)); 5462 SOC_CONTROL_LOCK(unit); 5463 SOC_CONTROL(unit)->l2_overflow_bucket_enable = l2_ovf_enable; 5464 SOC_CONTROL_UNLOCK(unit); 5465 5466 /* Enable L2 overflow interrupt */ 5467 if(soc_property_get(unit, spn_L2_OVERFLOW_EVENT, FALSE)) { 5468 5469 SOC_CONTROL_LOCK(unit); 5470 SOC_CONTROL(unit)->l2_overflow_enable = TRUE; 5471 SOC_CONTROL_UNLOCK(unit); 5472 SOC_IF_ERROR_RETURN(soc_hr3_l2_overflow_start(unit)); 5473 } else { 5474 SOC_CONTROL_LOCK(unit); 5475 SOC_CONTROL(unit)->l2_overflow_enable = FALSE; 5476 SOC_CONTROL_UNLOCK(unit); 5477 SOC_IF_ERROR_RETURN(soc_hr3_l2_overflow_stop(unit)); 5478 } 5479 5480 /* If parity is not enabled, enable the l2 overflow interrupt */ 5481 if (!soc_property_get(unit, spn_PARITY_ENABLE, TRUE)) { 5482 /* Write CMIC enable register */ 5483 (void)soc_cmicm_intr3_enable(unit, 5484 CMIC_PARITY_IP1_TO_CMIC_PERR_INTR_BIT); 5485 } 5486 5487 /* GMAC init should be moved to mac */ 5488 SOC_IF_ERROR_RETURN(_soc_hurricane3_gmac_init(unit)); 5489 5490 /* HG init */ 5491 SOC_IF_ERROR_RETURN(_soc_hurricane3_higig_mode_init(unit)); 5492 5493 /* XLPORT blocks init */ 5494 SOC_BLOCK_ITER(unit, blk, SOC_BLK_XLPORT) { 5495 int port_count = -1, i; 5496 5497 port = SOC_BLOCK_PORT(unit, blk); 5498 if (port == -1 || port == REG_PORT_ANY) { 5499 continue; 5500 } 5501 phy_port_base = si->port_l2p_mapping[port]; 5502 5503 for(i=0; i <_HR3_MAX_TSC_COUNT ; i++){ 5504 if(_hr3_tsc[i].phy_port_base == phy_port_base){ 5505 port_count = _hr3_tsc[i].port_count; 5506 break; 5507 } 5508 } 5509 5510 if (port_count == SOC_HR3_PORT_RATIO_QUAD){ 5511 mode = SOC_HR3_PORT_MODE_QUAD; 5512 si->port_num_lanes[port] = 1; 5513 si->port_num_lanes[port + 1] = 1; 5514 si->port_num_lanes[port + 2] = 1; 5515 si->port_num_lanes[port + 3] = 1; 5516 } else if ((port_count == SOC_HR3_PORT_RATIO_SINGLE) || 5517 (port_count == SOC_HR3_PORT_RATIO_SINGLE_XAUI)) { 5518 mode = SOC_HR3_PORT_MODE_SINGLE; 5519 si->port_num_lanes[port] = 4; 5520 si->port_num_lanes[port + 1] = -1; 5521 si->port_num_lanes[port + 2] = -1; 5522 si->port_num_lanes[port + 3] = -1; 5523 } else if (port_count == SOC_HR3_PORT_RATIO_DUAL_2_2) { 5524 mode = SOC_HR3_PORT_MODE_DUAL; 5525 si->port_num_lanes[port] = 2; 5526 si->port_num_lanes[port + 1] = 2; 5527 si->port_num_lanes[port + 2] = -1; 5528 si->port_num_lanes[port + 3] = -1; 5529 } else if (port_count == SOC_HR3_PORT_RATIO_TRI_012_1_1_2){ 5530 mode = SOC_HR3_PORT_MODE_TRI_012; 5531 si->port_num_lanes[port] = 1; 5532 si->port_num_lanes[port + 1] = 1; 5533 si->port_num_lanes[port + 2] = 2; 5534 si->port_num_lanes[port + 3] = -1; 5535 if (si->port_p2l_mapping[phy_port_base] != -1) { 5536 si->port_num_lanes[port] = 1; 5537 } 5538 if (si->port_p2l_mapping[phy_port_base + 1] != -1) { 5539 si->port_num_lanes[++port] = 1; 5540 } 5541 if (si->port_p2l_mapping[phy_port_base + 2] != -1) { 5542 si->port_num_lanes[++port] = 2; 5543 } 5544 si->port_num_lanes[++port] = -1; 5545 } else { 5546 mode = SOC_HR3_PORT_MODE_QUAD; 5547 si->port_num_lanes[port] = 1; 5548 si->port_num_lanes[port + 1] = 1; 5549 si->port_num_lanes[port + 2] = 1; 5550 si->port_num_lanes[port + 3] = 1; 5551 } 5552 5553 SOC_IF_ERROR_RETURN(_soc_hurricane3_xlport_init(unit, blk, mode)); 5554 } 5555 5556 SOC_IF_ERROR_RETURN(READ_MISCCONFIGr(unit, &rval)); 5557 soc_reg_field_set(unit, MISCCONFIGr, &rval, METERING_CLK_ENf, 1); 5558 SOC_IF_ERROR_RETURN(WRITE_MISCCONFIGr(unit, rval)); 5559 5560 /* Enable dual hash on L2 and L3 tables */ 5561 fields[0] = ENABLEf; 5562 values[0] = 1; 5563 fields[1] = HASH_SELECTf; 5564 values[1] = FB_HASH_CRC32_LOWER; 5565 fields[2] = INSERT_LEAST_FULL_HALFf; 5566 values[2] = 1; 5567 SOC_IF_ERROR_RETURN 5568 (soc_reg_fields32_modify(unit, L2_AUX_HASH_CONTROLr, REG_PORT_ANY, 3, 5569 fields, values)); 5570 SOC_IF_ERROR_RETURN 5571 (soc_reg_fields32_modify(unit, L3_AUX_HASH_CONTROLr, REG_PORT_ANY, 3, 5572 fields, values)); 5573 5574 /* 5575 * Egress Enable 5576 */ 5577 sal_memset(entry, 0, sizeof(egr_enable_entry_t)); 5578 soc_mem_field32_set(unit, EGR_ENABLEm, entry, PRT_ENABLEf, 1); 5579 PBMP_ALL_ITER(unit, port) { 5580 SOC_IF_ERROR_RETURN 5581 (WRITE_EGR_ENABLEm(unit, MEM_BLOCK_ALL, SOC_INFO(unit).port_l2p_mapping[port], entry)); 5582 } 5583 5584 COMPILER_64_ZERO(reg64); 5585 soc_reg64_field32_set(unit, EPC_LINK_BMAP_64r, ®64, PORT_BITMAP_LOf, 5586 SOC_PBMP_WORD_GET(PBMP_CMIC(unit), 0)); 5587 SOC_IF_ERROR_RETURN(WRITE_EPC_LINK_BMAP_64r(unit, reg64)); 5588 5589 SOC_IF_ERROR_RETURN(READ_ING_CONFIG_64r(unit, ®64)); 5590 soc_reg64_field32_set(unit, ING_CONFIG_64r, ®64, 5591 L3SRC_HIT_ENABLEf, 1); 5592 soc_reg64_field32_set(unit, ING_CONFIG_64r, ®64, 5593 L2DST_HIT_ENABLEf, 1); 5594 soc_reg64_field32_set(unit, ING_CONFIG_64r, ®64, 5595 APPLY_EGR_MASK_ON_L2f, 1); 5596 soc_reg64_field32_set(unit, ING_CONFIG_64r, ®64, 5597 APPLY_EGR_MASK_ON_L3f, 1); 5598 soc_reg64_field32_set(unit, ING_CONFIG_64r, ®64, 5599 ARP_RARP_TO_FPf, 0x3); /* enable both ARP & RARP */ 5600 soc_reg64_field32_set(unit, ING_CONFIG_64r, ®64, 5601 ARP_VALIDATION_ENf, 1); 5602 soc_reg64_field32_set(unit, ING_CONFIG_64r, ®64, 5603 IGNORE_HG_HDR_LAG_FAILOVERf, 1); 5604 SOC_IF_ERROR_RETURN(WRITE_ING_CONFIG_64r(unit, reg64)); 5605 5606 SOC_IF_ERROR_RETURN(READ_EGR_CONFIG_1r(unit, &rval)); 5607 soc_reg_field_set(unit, EGR_CONFIG_1r, &rval, RING_MODEf, 1); 5608 SOC_IF_ERROR_RETURN(WRITE_EGR_CONFIG_1r(unit, rval)); 5609 5610 /* The HW defaults for EGR_VLAN_CONTROL_1.VT_MISS_UNTAG == 1, which 5611 * causes the outer tag to be removed from packets that don't have 5612 * a hit in the egress vlan tranlation table. Set to 0 to disable this. 5613 */ 5614 rval = 0; 5615 soc_reg_field_set(unit, EGR_VLAN_CONTROL_1r, &rval, VT_MISS_UNTAGf, 0); 5616 5617 /* Enable pri/cfi remarking on egress ports. */ 5618 soc_reg_field_set(unit, EGR_VLAN_CONTROL_1r, &rval, REMARK_OUTER_DOT1Pf, 5619 1); 5620 PBMP_ALL_ITER(unit, port) { 5621 SOC_IF_ERROR_RETURN(WRITE_EGR_VLAN_CONTROL_1r(unit, port, rval)); 5622 } 5623 5624 /* Multicast range initialization */ 5625 SOC_IF_ERROR_RETURN 5626 (soc_hbx_higig2_mcast_sizes_set(unit, 5627 soc_property_get(unit, spn_HIGIG2_MULTICAST_VLAN_RANGE, 5628 SOC_HBX_MULTICAST_RANGE_DEFAULT), 5629 soc_property_get(unit, spn_HIGIG2_MULTICAST_L2_RANGE, 5630 SOC_HBX_MULTICAST_RANGE_DEFAULT), 5631 soc_property_get(unit, spn_HIGIG2_MULTICAST_L3_RANGE, 5632 SOC_HBX_MULTICAST_RANGE_DEFAULT))); 5633 5634 /* Setup SW2_FP_DST_ACTION_CONTROL */ 5635 fields[0] = HGTRUNK_RES_ENf; 5636 fields[1] = LAG_RES_ENf; 5637 values[0] = values[1] = 1; 5638 SOC_IF_ERROR_RETURN 5639 (soc_reg_fields32_modify(unit, SW2_FP_DST_ACTION_CONTROLr, 5640 REG_PORT_ANY, 2, fields, values)); 5641 5642 freq = si->frequency; 5643 5644 /* 5645 * Set external MDIO freq to around 10MHz 5646 * target_freq = core_clock_freq * DIVIDEND / DIVISOR / 2 5647 */ 5648 target_freq = 10; 5649 divisor = (freq + (target_freq * 2 - 1)) / (target_freq * 2); 5650 divisor = soc_property_get(unit, spn_RATE_EXT_MDIO_DIVISOR, divisor); 5651 dividend = soc_property_get(unit, spn_RATE_EXT_MDIO_DIVIDEND, 1); 5652 5653 rval = 0; 5654 soc_reg_field_set(unit, CMIC_RATE_ADJUSTr, &rval, DIVISORf, divisor); 5655 soc_reg_field_set(unit, CMIC_RATE_ADJUSTr, &rval, DIVIDENDf, dividend); 5656 /* coverity[result_independent_of_operands] */ 5657 SOC_IF_ERROR_RETURN(WRITE_CMIC_RATE_ADJUSTr(unit, rval)); 5658 5659 /* 5660 * Set internal MDIO freq to around 10MHz 5661 * Valid range is from 2.5MHz to 12.5MHz 5662 * target_freq = core_clock_freq * DIVIDEND / DIVISOR / 2 5663 * or 5664 * DIVISOR = core_clock_freq * DIVIDENT / (target_freq * 2) 5665 */ 5666 target_freq = 10; 5667 divisor = (freq + (target_freq * 2 - 1)) / (target_freq * 2); 5668 divisor = soc_property_get(unit, spn_RATE_INT_MDIO_DIVISOR, divisor); 5669 dividend = soc_property_get(unit, spn_RATE_INT_MDIO_DIVIDEND, 1); 5670 rval = 0; 5671 soc_reg_field_set (unit, CMIC_RATE_ADJUST_INT_MDIOr, &rval, DIVISORf, 5672 divisor); 5673 soc_reg_field_set (unit, CMIC_RATE_ADJUST_INT_MDIOr, &rval, DIVIDENDf, 5674 dividend); 5675 /* coverity[result_independent_of_operands] */ 5676 SOC_IF_ERROR_RETURN(WRITE_CMIC_RATE_ADJUST_INT_MDIOr(unit, rval)); 5677 5678 delay = soc_property_get(unit, spn_MDIO_OUTPUT_DELAY, -1); 5679 if (delay >= 1 && delay <= 15) { 5680 /* coverity[result_independent_of_operands] */ 5681 SOC_IF_ERROR_RETURN(READ_CMIC_MIIM_CONFIGr(unit, &rval)); 5682 soc_reg_field_set(unit, CMIC_MIIM_CONFIGr, &rval, MDIO_OUT_DELAYf, 5683 delay); 5684 /* coverity[result_independent_of_operands] */ 5685 SOC_IF_ERROR_RETURN(WRITE_CMIC_MIIM_CONFIGr(unit, rval)); 5686 } 5687 5688 /* Directed Mirroring ON by default except for CPU port */ 5689 /* The src_port info will be changed as egress port if EM_SRCMOD_CHANGEf = 1 */ 5690 PBMP_PORT_ITER(unit, port) { 5691 SOC_IF_ERROR_RETURN(READ_EGR_PORT_64r(unit, port, ®64)); 5692 soc_reg64_field32_set(unit, EGR_PORT_64r, ®64, EM_SRCMOD_CHANGEf, 1); 5693 SOC_IF_ERROR_RETURN(WRITE_EGR_PORT_64r(unit, port, reg64)); 5694 SOC_IF_ERROR_RETURN(READ_IEGR_PORT_64r(unit, port, ®64)); 5695 soc_reg64_field32_set(unit, IEGR_PORT_64r, ®64, EM_SRCMOD_CHANGEf, 1); 5696 SOC_IF_ERROR_RETURN(WRITE_IEGR_PORT_64r(unit, port, reg64)); 5697 } 5698 5699 _phy_tsce_firmware_set_helper[unit] = _soc_hurricane3_tscx_firmware_set; 5700 _phy_qtce_firmware_set_helper[unit] = _soc_hurricane3_tscx_firmware_set; 5701 5702 /* LEDuP init */ 5703 SOC_IF_ERROR_RETURN(_soc_hurricane3_ledup_init(unit)); 5704 5705 /* MSPI init */ 5706 if (soc_mspi_init(unit) != SOC_E_NONE) { 5707 LOG_WARN(BSL_LS_SOC_COMMON, 5708 (BSL_META_U(unit, 5709 "unit %d : MSPI Init Failed\n"), unit)); 5710 } 5711 5712 /* Add board properity which can be used in rc.soc */ 5713 board_name = soc_property_get_str(unit, spn_BOARD_NAME); 5714 if (board_name) { 5715 if (soc_mem_config_set == NULL) { 5716 LOG_WARN(BSL_LS_SOC_COMMON, 5717 (BSL_META_U(unit, "unit %d : soc_mem_config_set() is NULL\n"), 5718 unit)); 5719 } else { 5720 if (sal_strcmp(board_name, "BCM956160R") == 0) { 5721 soc_mem_config_set("bcm956160r", "1"); 5722 } else if (sal_strcmp(board_name, "BCM956166R") == 0) { 5723 soc_mem_config_set("bcm956166r", "1"); 5724 } else if (sal_strcmp(board_name, "BCM956160K") == 0) { 5725 soc_mem_config_set("bcm956160k", "1"); 5726 } else if (sal_strcmp(board_name, "BCM953434K") == 0) { 5727 soc_mem_config_set("bcm953434k", "1"); 5728 } else if (sal_strcmp(board_name, "BCM956164K") == 0) { 5729 soc_mem_config_set("bcm956164k", "1"); 5730 } 5731 } 5732 } 5733 5734 #ifdef INCLUDE_MEM_SCAN 5735 if (parity_enable) { 5736 SOC_IF_ERROR_RETURN(soc_generic_ser_mem_scan_start(unit)); 5737 } 5738 #endif /* INCLUDE_MEM_SCAN */ 5739 5740 #ifdef INCLUDE_AVS 5741 soc_hr3_avs_init(unit); 5742 #endif /* INCLUDE_AVS */ 5743 5744 SOC_IF_ERROR_RETURN(_soc_hr3_l3iif_hw_mem_init(unit, TRUE)); 5745 return SOC_E_NONE; 5746 } 5747 5748 5749 /* 5750 * Function: 5751 * _soc_hurricane3_gpio_set 5752 * Purpose: 5753 * Write value to the specified GPIO pin 5754 */ 5755 STATIC int 5756 _soc_hurricane3_gpio_set(int unit, int pin, int output, int val) 5757 { 5758 uint32 rval = 0; 5759 uint32 fval = 0; 5760 uint8 mask = 0xFF; 5761 5762 mask &= ~(1 << pin); 5763 5764 /* coverity[result_independent_of_operands] */ 5765 SOC_IF_ERROR_RETURN(READ_CMIC_GP_OUT_ENr(unit, &rval)); 5766 fval = soc_reg_field_get(unit, CMIC_GP_OUT_ENr, rval, OUT_ENABLEf); 5767 if (output) { 5768 fval |= 1 << pin; 5769 } else { 5770 fval &= ~(1 << pin); 5771 } 5772 soc_reg_field_set(unit, CMIC_GP_OUT_ENr, &rval, OUT_ENABLEf, fval); 5773 /* coverity[result_independent_of_operands] */ 5774 SOC_IF_ERROR_RETURN(WRITE_CMIC_GP_OUT_ENr(unit, rval)); 5775 5776 if (output) { 5777 /* coverity[result_independent_of_operands] */ 5778 SOC_IF_ERROR_RETURN(READ_CMIC_GP_DATA_OUTr(unit, &rval)); 5779 fval = soc_reg_field_get(unit, CMIC_GP_DATA_OUTr, rval, DATA_OUTf); 5780 if (val) { 5781 fval |= (val << pin); 5782 } else { 5783 fval &= ~(1 << pin); 5784 } 5785 5786 soc_reg_field_set(unit, CMIC_GP_DATA_OUTr, &rval, DATA_OUTf, fval); 5787 /* coverity[result_independent_of_operands] */ 5788 SOC_IF_ERROR_RETURN(WRITE_CMIC_GP_DATA_OUTr(unit, rval)); 5789 } 5790 5791 return SOC_E_NONE; 5792 } 5793 5794 5795 /* soc_hurricane3_mem_config: 5796 * Over-ride the default table sizes (from regsfile) for any SKUs here 5797 */ 5798 int 5799 soc_hurricane3_mem_config(int unit, int dev_id) 5800 { 5801 int rv = SOC_E_NONE; 5802 soc_persist_t *sop = SOC_PERSIST(unit); 5803 5804 switch (dev_id) { 5805 case BCM56163_DEVICE_ID: 5806 case BCM56164_DEVICE_ID: 5807 case BCM56166_DEVICE_ID: 5808 /* Hurricane3 Lite */ 5809 /* -- L2 related -- */ 5810 sop->memState[L2MCm].index_max = 511; 5811 /* -- L3 related -- */ 5812 sop->memState[L3_IPMCm].index_max = 63; 5813 sop->memState[L3_DEFIPm].index_max = 63; 5814 sop->memState[L3_DEFIP_ONLYm].index_max = 63; 5815 sop->memState[L3_DEFIP_DATA_ONLYm].index_max = 63; 5816 sop->memState[L3_DEFIP_HIT_ONLYm].index_max = 63; 5817 sop->memState[ING_L3_NEXT_HOPm].index_max = 767; 5818 sop->memState[INITIAL_ING_L3_NEXT_HOPm].index_max = 767; 5819 sop->memState[EGR_L3_NEXT_HOPm].index_max = 767; 5820 sop->memState[EGR_L3_INTFm].index_max = 255; 5821 sop->memState[L3_MTU_VALUESm].index_max = 575; 5822 sop->memState[L3_IIFm].index_max = -1; 5823 sop->memState[L3_ECMP_COUNTm].index_max = -1; 5824 sop->memState[L3_ECMPm].index_max = -1; 5825 sop->memState[INITIAL_L3_ECMP_GROUPm].index_max = -1; 5826 sop->memState[INITIAL_L3_ECMPm].index_max = -1; 5827 SOC_CONTROL(unit)->l3_defip_max_tcams = 1; 5828 SOC_CONTROL(unit)->l3_defip_tcam_size = 64; 5829 5830 sop->memState[VLAN_SUBNETm].index_max = 63; 5831 sop->memState[VLAN_SUBNET_ONLYm].index_max = 63; 5832 sop->memState[VLAN_SUBNET_DATA_ONLYm].index_max = 63; 5833 sop->memState[EFP_COUNTER_TABLEm].index_max = -1; 5834 sop->memState[EFP_METER_TABLEm].index_max = -1; 5835 sop->memState[EFP_POLICY_TABLEm].index_max = -1; 5836 sop->memState[EFP_TCAMm].index_max = -1; 5837 sop->memState[VFP_POLICY_TABLEm].index_max = -1; 5838 sop->memState[VFP_TCAMm].index_max = -1; 5839 break; 5840 case BCM53440_DEVICE_ID: 5841 case BCM53442_DEVICE_ID: 5842 case BCM53443_DEVICE_ID: 5843 /* Buckhound */ 5844 /* -- L3 related -- */ 5845 /* used for miml and oam 5846 sop->memState[ING_L3_NEXT_HOPm].index_max = -1; 5847 sop->memState[EGR_L3_NEXT_HOPm].index_max = -1; 5848 sop->memState[EGR_L3_INTFm].index_max = -1; 5849 sop->memState[L3_ENTRY_IPV4_UNICASTm].index_max = -1; 5850 sop->memState[L3_ENTRY_ONLYm].index_max = -1; 5851 sop->memState[L3_MTU_VALUESm].index_max = -1; 5852 */ 5853 sop->memState[L3_IPMCm].index_max = -1; 5854 sop->memState[L3_DEFIPm].index_max = -1; 5855 sop->memState[L3_DEFIP_ONLYm].index_max = -1; 5856 sop->memState[L3_DEFIP_DATA_ONLYm].index_max = -1; 5857 sop->memState[L3_DEFIP_HIT_ONLYm].index_max = -1; 5858 sop->memState[INITIAL_ING_L3_NEXT_HOPm].index_max = -1; 5859 sop->memState[L3_ENTRY_HIT_ONLYm].index_max = -1; 5860 sop->memState[L3_ENTRY_IPV4_MULTICASTm].index_max = -1; 5861 sop->memState[L3_ENTRY_IPV6_UNICASTm].index_max = -1; 5862 sop->memState[L3_ENTRY_IPV6_MULTICASTm].index_max = -1; 5863 sop->memState[L3_ENTRY_VALID_ONLYm].index_max = -1; 5864 sop->memState[L3_ECMP_COUNTm].index_max = -1; 5865 sop->memState[L3_ECMPm].index_max = -1; 5866 sop->memState[INITIAL_L3_ECMP_GROUPm].index_max = -1; 5867 sop->memState[INITIAL_L3_ECMPm].index_max = -1; 5868 sop->memState[L3_IIFm].index_max = -1; 5869 SOC_CONTROL(unit)->l3_defip_max_tcams = 0; 5870 SOC_CONTROL(unit)->l3_defip_tcam_size = 0; 5871 break; 5872 case BCM53434_DEVICE_ID: 5873 /* Foxhound2 */ 5874 /* -- L2 related -- */ 5875 sop->memState[L2Xm].index_max = 8191; 5876 sop->memState[L2_ENTRY_ONLYm].index_max = 8191; 5877 sop->memState[L2_HITDA_ONLYm].index_max = 1023; 5878 sop->memState[L2_HITSA_ONLYm].index_max = 1023; 5879 sop->memState[L2MCm].index_max = 255; 5880 /* -- L3 related -- */ 5881 sop->memState[L3_IPMCm].index_max = -1; 5882 sop->memState[L3_DEFIPm].index_max = -1; 5883 sop->memState[L3_DEFIP_ONLYm].index_max = -1; 5884 sop->memState[L3_DEFIP_DATA_ONLYm].index_max = -1; 5885 sop->memState[L3_DEFIP_HIT_ONLYm].index_max = -1; 5886 sop->memState[ING_L3_NEXT_HOPm].index_max = -1; 5887 sop->memState[INITIAL_ING_L3_NEXT_HOPm].index_max = -1; 5888 sop->memState[EGR_L3_NEXT_HOPm].index_max = -1; 5889 sop->memState[EGR_L3_INTFm].index_max = -1; 5890 sop->memState[L3_ENTRY_HIT_ONLYm].index_max = -1; 5891 sop->memState[L3_ENTRY_IPV4_UNICASTm].index_max = -1; 5892 sop->memState[L3_ENTRY_IPV4_MULTICASTm].index_max = -1; 5893 sop->memState[L3_ENTRY_IPV6_UNICASTm].index_max = -1; 5894 sop->memState[L3_ENTRY_IPV6_MULTICASTm].index_max = -1; 5895 sop->memState[L3_ENTRY_ONLYm].index_max = -1; 5896 sop->memState[L3_ENTRY_VALID_ONLYm].index_max = -1; 5897 sop->memState[L3_MTU_VALUESm].index_max = -1; 5898 sop->memState[L3_ECMP_COUNTm].index_max = -1; 5899 sop->memState[L3_ECMPm].index_max = -1; 5900 sop->memState[INITIAL_L3_ECMP_GROUPm].index_max = -1; 5901 sop->memState[INITIAL_L3_ECMPm].index_max = -1; 5902 sop->memState[L3_IIFm].index_max = -1; 5903 5904 sop->memState[VLAN_SUBNETm].index_max = -1; 5905 sop->memState[VLAN_SUBNET_ONLYm].index_max = -1; 5906 sop->memState[VLAN_SUBNET_DATA_ONLYm].index_max = -1; 5907 sop->memState[EFP_COUNTER_TABLEm].index_max = -1; 5908 sop->memState[EFP_METER_TABLEm].index_max = -1; 5909 sop->memState[EFP_POLICY_TABLEm].index_max = -1; 5910 sop->memState[EFP_TCAMm].index_max = -1; 5911 sop->memState[VFP_POLICY_TABLEm].index_max = -1; 5912 sop->memState[VFP_TCAMm].index_max = -1; 5913 sop->memState[FP_TCAMm].index_max = 1023; 5914 sop->memState[FP_GLOBAL_MASK_TCAMm].index_max = 1023; 5915 sop->memState[FP_COUNTER_TABLEm].index_max = 1023; 5916 sop->memState[FP_METER_TABLEm].index_max = 1023; 5917 sop->memState[FP_POLICY_TABLEm].index_max = 1023; 5918 sop->memState[MMU_CBPCELLHEADERm].index_max = 4095; 5919 sop->memState[MMU_CBPDATA0m].index_max = 4095; 5920 sop->memState[MMU_CBPDATA1m].index_max = 4095; 5921 sop->memState[MMU_CBPDATA2m].index_max = 4095; 5922 sop->memState[MMU_CBPDATA3m].index_max = 4095; 5923 sop->memState[MMU_CBPDATA4m].index_max = 4095; 5924 sop->memState[MMU_CBPDATA5m].index_max = 4095; 5925 sop->memState[MMU_CBPDATA6m].index_max = 4095; 5926 sop->memState[MMU_CBPDATA7m].index_max = 4095; 5927 sop->memState[MMU_CBPPKTHEADER0m].index_max = 4095; 5928 sop->memState[MMU_CBPPKTHEADER1m].index_max = 4095; 5929 sop->memState[MMU_CBPPKTHEADER2m].index_max = 4095; 5930 sop->memState[MMU_CBPPKTHEADER_EXTm].index_max = 4095; 5931 SOC_CONTROL(unit)->l3_defip_max_tcams = 0; 5932 SOC_CONTROL(unit)->l3_defip_tcam_size = 0; 5933 break; 5934 default: 5935 SOC_CONTROL(unit)->l3_defip_max_tcams = 8; 5936 SOC_CONTROL(unit)->l3_defip_tcam_size = 64; 5937 break; 5938 } 5939 if (SAL_BOOT_QUICKTURN) { 5940 /* QuickTurn with limited TCAM entries */ 5941 sop->memState[L2_USER_ENTRYm].index_max = 11; 5942 sop->memState[L2_USER_ENTRY_ONLYm].index_max = 11; 5943 sop->memState[L2_USER_ENTRY_DATA_ONLYm].index_max = 11; 5944 sop->memState[CPU_COS_MAPm].index_max = 11; 5945 sop->memState[CPU_COS_MAP_ONLYm].index_max = 11; 5946 sop->memState[FP_GLOBAL_MASK_TCAMm].index_max = 29; 5947 sop->memState[VLAN_SUBNETm].index_max = 11; 5948 sop->memState[VLAN_SUBNET_ONLYm].index_max = 11; 5949 sop->memState[VLAN_SUBNET_DATA_ONLYm].index_max = 11; 5950 sop->memState[L3_DEFIPm].index_max = 31; 5951 sop->memState[L3_DEFIP_ONLYm].index_max = 31; 5952 sop->memState[L3_DEFIP_DATA_ONLYm].index_max = 31; 5953 sop->memState[VFP_TCAMm].index_max = 29; 5954 sop->memState[EFP_TCAMm].index_max = 29; 5955 sop->memState[FP_TCAMm].index_max = 29; 5956 } 5957 return rv; 5958 } 5959 5960 /* 5961 * Function: 5962 * _soc_hurricane3_core_disable 5963 * Purpose: 5964 * Re-config the port info for the core disabled 5965 */ 5966 STATIC int 5967 _soc_hurricane3_core_disable(int unit, int core_type, 5968 uint32 disable_core_bmp, uint32 disable_qgphy_bmp) 5969 { 5970 int i, j, idx, core_count; 5971 int phy_port, port, blk, num_port, num_port2; 5972 soc_info_t *si; 5973 const int *core_phy_port; 5974 5975 si = &SOC_INFO(unit); 5976 5977 switch (core_type) { 5978 case SOC_HR3_PORT_CORE_TYPE_TSC: 5979 num_port = _HR3_PORT_COUNT_PER_TSC; 5980 core_phy_port = &tsc_phy_port[0]; 5981 core_count = _HR3_MAX_TSC_COUNT; 5982 break; 5983 case SOC_HR3_PORT_CORE_TYPE_QTC: 5984 num_port = _HR3_PORT_COUNT_PER_QTC; 5985 core_phy_port = &qtc_phy_port[0]; 5986 core_count = _HR3_MAX_QTC_COUNT; 5987 break; 5988 default: 5989 return (SOC_E_PARAM); 5990 } 5991 for (i = 0; i < core_count; i++) { 5992 if((1 << i) & disable_core_bmp){ 5993 num_port2 = num_port; 5994 if (!((1 << i) & disable_qgphy_bmp) && 5995 (core_type == SOC_HR3_PORT_CORE_TYPE_QTC)) { 5996 /* The QGPHY ports are occupied on the same ports 5997 * as QTC lane 3 lane 4. 5998 * If these ports are used for GPHY, we should not disable them. 5999 */ 6000 num_port2 = 8; 6001 6002 } 6003 6004 for (j = 0; j < num_port2; j++) { 6005 phy_port = core_phy_port[i]+j; 6006 port = si->port_p2l_mapping[phy_port]; 6007 for (idx = 0; idx < SOC_DRIVER(unit)->port_num_blktype; idx++) { 6008 blk = SOC_PORT_IDX_BLOCK(unit, phy_port, idx); 6009 if (blk < 0) { /* end of block list of each port */ 6010 break; 6011 } 6012 if(si->block_port[blk] == port){ 6013 si->block_port[blk] = -1; 6014 } 6015 si->block_valid[blk]=0; 6016 SOC_PBMP_PORT_REMOVE(si->block_bitmap[blk],port); 6017 } 6018 si->port_p2l_mapping[phy_port]= -1; 6019 si->port_p2m_mapping[phy_port] = -1; 6020 si->max_port_p2m_mapping[phy_port] = -1; 6021 si->port_l2p_mapping[port] = -1; 6022 si->port_m2p_mapping[port] = -1; 6023 6024 SOC_PBMP_PORT_REMOVE(si->ether.bitmap,port); 6025 SOC_PBMP_PORT_REMOVE(si->ge.bitmap,port); 6026 SOC_PBMP_PORT_REMOVE(si->xe.bitmap,port); 6027 SOC_PBMP_PORT_REMOVE(si->hg.bitmap,port); 6028 SOC_PBMP_PORT_REMOVE(si->st.bitmap,port); 6029 SOC_PBMP_PORT_REMOVE(si->xl.bitmap,port); 6030 SOC_PBMP_PORT_REMOVE(si->all.bitmap,port); 6031 SOC_PBMP_PORT_REMOVE(si->port.bitmap,port); 6032 sal_snprintf(si->port_name[port], sizeof(si->port_name[port]), 6033 "?%d", port); 6034 si->port_offset[port] = port; 6035 } 6036 } 6037 } 6038 6039 #define RECONFIG_PORT_INFO(ptype,str) \ 6040 si->ptype.num = 0; \ 6041 si->ptype.min = si->ptype.max = -1; \ 6042 PBMP_ITER(si->ptype.bitmap, port) { \ 6043 if(sal_strcmp(str,"")){\ 6044 sal_snprintf(si->port_name[port], sizeof(si->port_name[port]),\ 6045 "%s%d", str, si->ptype.num);\ 6046 }\ 6047 si->ptype.port[si->ptype.num++] = port; \ 6048 if (si->ptype.min < 0) { \ 6049 si->ptype.min = port; \ 6050 } \ 6051 if (port > si->ptype.max) { \ 6052 si->ptype.max = port; \ 6053 } \ 6054 } 6055 6056 /* coverity[pointless_string_compare] */ 6057 RECONFIG_PORT_INFO(ether,""); 6058 /* coverity[pointless_string_compare] */ 6059 RECONFIG_PORT_INFO(st,""); 6060 RECONFIG_PORT_INFO(hg,"hg"); 6061 RECONFIG_PORT_INFO(xe,"xe"); 6062 RECONFIG_PORT_INFO(ge,"ge"); 6063 #undef RECONFIG_PORT_INFO 6064 6065 return SOC_E_NONE; 6066 } 6067 6068 #define TOP_STRAP_STATUS_TSC_DISABLE(val) \ 6069 (((val) >> 25) & 0x3) 6070 #define TOP_STRAP_STATUS_QTC_DISABLE(val) \ 6071 (((val) >> 27) & 0x3) 6072 #define TOP_STRAP_STATUS_LCPLL1_REF(val) \ 6073 (((val) & (1<<9)) != 0) 6074 #define TOP_STRAP_STATUS_1_REF(val) \ 6075 ((val) & 1) 6076 6077 6078 /* 6079 * Function: 6080 * soc_hurricane3_chip_reset 6081 * Purpose: 6082 * Special reset sequencing for BCM56160 6083 */ 6084 int 6085 soc_hurricane3_chip_reset(int unit) 6086 { 6087 uint32 rval, to_usec, strap_sts, strap_sts_1; 6088 _hr3_sku_info_t *matched_sku_info; 6089 uint32 disabled_bmp,disable_tsc,disable_qtc, disable_gphy; 6090 int i; 6091 uint16 dev_id; 6092 uint8 rev_id; 6093 6094 unsigned ts_ref_freq; 6095 unsigned ts_idx; 6096 static const soc_pll_param_t ts_pll[] = { /* values for 500MHz TSPLL output */ 6097 /* Fref, Ndiv_int, Ndiv_frac, Pdiv, Mdiv, Ka, Ki, Kp, VCO_div2 */ 6098 {25000000, 100, 0, 5, 1, 2, 2, 3, 1}, 6099 {50000000, 50, 0, 5, 1, 2, 2, 3, 1}, 6100 { 0, 160, 0, 1, 8, 2, 2, 3, 1}, /* 25Mhz internal clk */ 6101 { 0, 50, 0, 1, 5, 2, 2, 3, 1} /* 50Mhz internal clk */ 6102 /* 0 => 25MHz or 50Mhz depending upon strap_xtal_freq_sel - from internal reference */ 6103 }; 6104 unsigned bs_ref_freq; 6105 unsigned bs_idx; 6106 uint32 bs_ndiv_high, bs_ndiv_low; 6107 static const soc_pll_param_t bs_pll[] = { /* values for 20MHz BSPLL output */ 6108 /* Fref, Ndiv_int, Ndiv_frac, Pdiv, Mdiv, Ka, Ki, Kp, VCO_div2 */ 6109 {25000000, 120, 0, 1, 150, 4, 1, 8, 0}, 6110 {50000000, 60, 0, 1, 150, 4, 1, 8, 0}, 6111 { 0, 120, 0, 1, 150, 4, 1, 8, 0}, /* 25Mhz internal clk */ 6112 { 0, 60, 0, 1, 150, 4, 1, 8, 0} /* 50MHZ internal clk */ 6113 /* 0 => 25MHz or 50Mhz depending upon strap_xtal_freq_sel - from internal reference */ 6114 }; 6115 int hitless = 0; 6116 #if defined(BCM_HITLESS_RESET_SUPPORT) 6117 const int broadsync_default_fbdiv = 0x3c00; 6118 #endif /* BCM_HITLESS_RESET_SUPPORT */ 6119 uint32 refclk; 6120 6121 soc_cm_get_id(unit, &dev_id, &rev_id); 6122 to_usec = SAL_BOOT_QUICKTURN ? (250 * MILLISECOND_USEC) : 6123 (10 * MILLISECOND_USEC); 6124 6125 WRITE_CMIC_SBUS_RING_MAP_0_7r(unit, 0x00110000); /* block 7 - 0 */ 6126 WRITE_CMIC_SBUS_RING_MAP_8_15r(unit, 0x00430000); /* block 15 - 8 */ 6127 WRITE_CMIC_SBUS_RING_MAP_16_23r(unit, 0x00005064); /* block 23 - 16 */ 6128 WRITE_CMIC_SBUS_RING_MAP_24_31r(unit, 0x00000000); /* block 31 - 24 */ 6129 WRITE_CMIC_SBUS_RING_MAP_32_39r(unit, 0x77772222); /* block 39 - 32 */ 6130 WRITE_CMIC_SBUS_RING_MAP_40_47r(unit, 0x00000000); /* block 40 - 47 */ 6131 6132 WRITE_CMIC_SBUS_TIMEOUTr(unit, 0x7d0); 6133 6134 sal_usleep(to_usec); 6135 6136 6137 strap_sts = 0; 6138 SOC_IF_ERROR_RETURN(READ_TOP_STRAP_STATUSr(unit, &strap_sts)); 6139 strap_sts_1 = 0; 6140 SOC_IF_ERROR_RETURN(READ_TOP_STRAP_STATUS_1r(unit, &strap_sts_1)); 6141 6142 /* TSPLL configuration: 500MHz TS_CLK from 20/25/32/50MHz refclk */ 6143 /* CMICd divides by 2 on input, so this is a 250MHz clock to TS logic */ 6144 6145 ts_ref_freq = soc_property_get(unit, spn_PTP_TS_PLL_FREF, 0); /* 0->internal reference */ 6146 /* Set TS_PLL_CLK_IN_SEL based on reference frequency. If it is 0, use the internal reference */ 6147 soc_reg_field32_modify(unit, TOP_PLL_BYP_AND_REFCLK_CONTROLr, REG_PORT_ANY, 6148 TS_PLL_REFCLK_SELf, (ts_ref_freq != 0)); 6149 6150 for (ts_idx = 0; ts_idx < sizeof(ts_pll)/sizeof(ts_pll[0]); ++ts_idx) { 6151 if (ts_pll[ts_idx].ref_freq == ts_ref_freq) { 6152 break; 6153 } 6154 } 6155 /* differentiang between internal 25Mhz or 50MHz clk */ 6156 if (ts_ref_freq == 0) { 6157 if (rev_id < BCM56160_B0_REV_ID) { 6158 /* only 25Mhz internal clk */ 6159 ts_idx = 2; 6160 } else { 6161 /* 25MHz or 50MHz internal clk depeding upon strap setting */ 6162 ts_idx = (TOP_STRAP_STATUS_1_REF(strap_sts_1) == 0) ? 2 : 3; 6163 } 6164 } 6165 if (ts_idx == sizeof(ts_pll)/sizeof(ts_pll[0])) { 6166 LOG_ERROR(BSL_LS_SOC_COMMON, 6167 (BSL_META_U(unit, 6168 "Invalid value for PTP_TS_PLL_REF (%u). No default PLL params.\n"), ts_ref_freq)); 6169 /* Could check for existence of SOC properties for VCO_DIV2, KA, KI, KP, NDIV_INT, NDIV_FRAC, MDIV, PDIV, and if 6170 all exist, use them. For now, just fail. 6171 */ 6172 } else { 6173 6174 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REG_2r(unit, &rval)); 6175 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, TOP_TS_PLL_RST_Lf, 0); 6176 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REG_2r(unit, rval)); 6177 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, TOP_TS_PLL_POST_RST_Lf, 0); 6178 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REG_2r(unit, rval)); 6179 6180 /* Enable software overwrite of TimeSync PLL settings. */ 6181 soc_reg_field32_modify(unit, TOP_MISC_CONTROL_1r, REG_PORT_ANY, 6182 CMIC_TO_TS_PLL_LOADf, 1); 6183 6184 soc_reg_field32_modify(unit, TOP_TS_PLL_CTRL_0r, REG_PORT_ANY, 6185 VCO_DIV2f, soc_property_get(unit, spn_PTP_TS_VCO_DIV2, 6186 ts_pll[ts_idx].vco_div2)); 6187 6188 SOC_IF_ERROR_RETURN(READ_TOP_TS_PLL_CTRL_4r(unit,&rval)); 6189 soc_reg_field_set(unit, TOP_TS_PLL_CTRL_4r, &rval, KAf, 6190 soc_property_get(unit, spn_PTP_TS_KA, ts_pll[ts_idx].ka)); 6191 soc_reg_field_set(unit, TOP_TS_PLL_CTRL_4r, &rval, KIf, 6192 soc_property_get(unit, spn_PTP_TS_KI, ts_pll[ts_idx].ki)); 6193 soc_reg_field_set(unit, TOP_TS_PLL_CTRL_4r, &rval, KPf, 6194 soc_property_get(unit, spn_PTP_TS_KP, ts_pll[ts_idx].kp)); 6195 SOC_IF_ERROR_RETURN(WRITE_TOP_TS_PLL_CTRL_4r(unit, rval)); 6196 6197 SOC_IF_ERROR_RETURN(READ_TOP_TS_PLL_CTRL_3r(unit,&rval)); 6198 soc_reg_field_set(unit, TOP_TS_PLL_CTRL_3r, &rval, NDIV_INTf, 6199 soc_property_get(unit, spn_PTP_TS_PLL_N, ts_pll[ts_idx].ndiv_int)); 6200 soc_reg_field_set(unit, TOP_TS_PLL_CTRL_3r, &rval, NDIV_FRACf, 6201 ts_pll[ts_idx].ndiv_frac); 6202 SOC_IF_ERROR_RETURN(WRITE_TOP_TS_PLL_CTRL_3r(unit, rval)); 6203 6204 SOC_IF_ERROR_RETURN(READ_TOP_TS_PLL_CTRL_2r(unit,&rval)); 6205 soc_reg_field_set(unit, TOP_TS_PLL_CTRL_2r, &rval, PDIVf, 6206 soc_property_get(unit, spn_PTP_TS_PLL_PDIV, ts_pll[ts_idx].pdiv)); 6207 soc_reg_field_set(unit, TOP_TS_PLL_CTRL_2r, &rval, CH0_MDIVf, 6208 soc_property_get(unit, spn_PTP_TS_PLL_MNDIV, ts_pll[ts_idx].mdiv)); 6209 SOC_IF_ERROR_RETURN(WRITE_TOP_TS_PLL_CTRL_2r(unit, rval)); 6210 6211 /* Strobe channel-0 load-enable to set divisors. */ 6212 soc_reg_field32_modify(unit, TOP_TS_PLL_CTRL_2r, REG_PORT_ANY, 6213 LOAD_EN_CH0f, 0); 6214 soc_reg_field32_modify(unit, TOP_TS_PLL_CTRL_2r, REG_PORT_ANY, 6215 LOAD_EN_CH0f, 1); 6216 } 6217 6218 /* 500Mhz TSPLL -> 250MHz ref at timestamper, implies 4ns resolution */ 6219 SOC_TIMESYNC_PLL_CLOCK_NS(unit) = (1/250 * 1000); /* clock period in nanoseconds */ 6220 6221 #if defined(BCM_HITLESS_RESET_SUPPORT) 6222 /* Some SKUs do not have BSPLLs: time_v3 is true if they exist */ 6223 if (soc_feature(unit, soc_feature_time_v3) && 6224 !soc_feature(unit, soc_feature_time_v3_no_bs)) { 6225 /* Check to see if the BSPLLs have been configured yet. */ 6226 SOC_IF_ERROR_RETURN( 6227 READ_TOP_BROAD_SYNC0_LCPLL_FBDIV_CTRL_1r(unit,&rval)); 6228 6229 hitless = (soc_reg_field_get(unit, TOP_BROAD_SYNC0_LCPLL_FBDIV_CTRL_1r, 6230 rval, BROAD_SYNC1_LCPLL_FBDIV_1f) 6231 != broadsync_default_fbdiv); 6232 6233 LOG_VERBOSE(BSL_LS_SOC_COMMON, (BSL_META_U(unit, 6234 "BSPLL %s\n"), initialize_broadsync ? "Initializing" : "Hitless")); 6235 } 6236 #endif /* BCM_HITLESS_RESET_SUPPORT */ 6237 6238 /* Initialize BroadSync if we aren't booting hitless, if BroadSync exists */ 6239 if (!hitless && 6240 soc_feature(unit, soc_feature_time_v3) && 6241 !soc_feature(unit, soc_feature_time_v3_no_bs)) { 6242 /* as a signal to upper-level code that the BroadSync is newly initialized 6243 * disable BroadSync0/1 bitclock output. Checked in time.c / 1588 firmware */ 6244 soc_reg_field32_modify(unit, CMIC_BS0_CONFIGr, REG_PORT_ANY, 6245 BS_CLK_OUTPUT_ENABLEf, 0); 6246 6247 soc_reg_field32_modify(unit, CMIC_BS1_CONFIGr, REG_PORT_ANY, 6248 BS_CLK_OUTPUT_ENABLEf, 0); 6249 6250 /* BSPLL0 has not been configured, so reset/configure both BSPLL0 and BSPLL1 */ 6251 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REG_2r(unit, &rval)); 6252 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, TOP_BS_PLL0_RST_Lf, 0); 6253 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, TOP_BS_PLL1_RST_Lf, 0); 6254 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, TOP_BS_PLL0_POST_RST_Lf, 0); 6255 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, TOP_BS_PLL1_POST_RST_Lf, 0); 6256 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REG_2r(unit, rval)); 6257 6258 /* Set RATE_MANGER_MODE to 1 to enable on-the-fly setting of NDIV */ 6259 soc_reg_field32_modify(unit, TOP_BS_PLL0_CTRL_3r, 6260 REG_PORT_ANY, RATE_MANAGER_MODEf, 1); 6261 soc_reg_field32_modify(unit, TOP_BS_PLL1_CTRL_3r, 6262 REG_PORT_ANY, RATE_MANAGER_MODEf, 1); 6263 6264 /* Both BSPLLs configured the same, for 20MHz output by default */ 6265 6266 bs_ref_freq = soc_property_get(unit, spn_PTP_BS_FREF, 0); /* 0->internal reference */ 6267 /* Set BS_PLL_CLK_IN_SEL based on reference frequency. If it is 0, use the internal reference */ 6268 SOC_IF_ERROR_RETURN(READ_TOP_PLL_BYP_AND_REFCLK_CONTROLr(unit,&rval)); 6269 soc_reg_field_set(unit, TOP_PLL_BYP_AND_REFCLK_CONTROLr, &rval, BS_PLL0_REFCLK_SELf, 6270 (bs_ref_freq != 0)); 6271 soc_reg_field_set(unit, TOP_PLL_BYP_AND_REFCLK_CONTROLr, &rval, BS_PLL1_REFCLK_SELf, 6272 (bs_ref_freq != 0)); 6273 SOC_IF_ERROR_RETURN(WRITE_TOP_PLL_BYP_AND_REFCLK_CONTROLr(unit, rval)); 6274 6275 soc_reg_field32_modify(unit, TOP_BS_PLL0_CTRL_6r, REG_PORT_ANY, 6276 LDO_CTRLf, (rev_id < BCM56160_B0_REV_ID) ? 0x2a : 0x22); 6277 soc_reg_field32_modify(unit, TOP_BS_PLL0_CTRL_7r, REG_PORT_ANY, 6278 FREQ_DOUBLER_ONf, 0); 6279 soc_reg_field32_modify(unit, TOP_BS_PLL0_CTRL_6r, REG_PORT_ANY, 6280 MSC_CTRLf, 6281 (rev_id < BCM56160_B0_REV_ID) ? 0x0022 : 6282 (TOP_STRAP_STATUS_1_REF(strap_sts_1) == 0) 6283 ? 0x0022: 0x1022); 6284 soc_reg_field32_modify(unit, TOP_BS_PLL0_CTRL_7r, REG_PORT_ANY, 6285 VCO_CONT_ADJf, 1); 6286 soc_reg_field32_modify(unit, TOP_BS_PLL0_CTRL_3r, REG_PORT_ANY, 6287 VCO_CURf, 0); 6288 soc_reg_field32_modify(unit, TOP_BS_PLL0_CTRL_5r, REG_PORT_ANY, 6289 VCO_GAINf, (rev_id < BCM56160_B0_REV_ID) ? 3 : 15); 6290 soc_reg_field32_modify(unit, TOP_MISC_CONTROL_1r, REG_PORT_ANY, 6291 CMIC_TO_BS_PLL0_SW_OVWRf, 1); 6292 soc_reg_field32_modify(unit, TOP_BS_PLL0_CTRL_5r, REG_PORT_ANY, 6293 CP1f, 6294 (rev_id < BCM56160_B0_REV_ID) ? 1 : 6295 (TOP_STRAP_STATUS_1_REF(strap_sts_1) == 0) 6296 ? 0 : 1); 6297 soc_reg_field32_modify(unit, TOP_BS_PLL0_CTRL_5r, REG_PORT_ANY, 6298 CPf, 6299 (rev_id < BCM56160_B0_REV_ID) ? 3 : 6300 (TOP_STRAP_STATUS_1_REF(strap_sts_1) == 0) 6301 ? 0 : 3); 6302 soc_reg_field32_modify(unit, TOP_BS_PLL0_CTRL_5r, REG_PORT_ANY, 6303 CZf, 3); 6304 soc_reg_field32_modify(unit, TOP_BS_PLL0_CTRL_5r, REG_PORT_ANY, 6305 RPf, (rev_id < BCM56160_B0_REV_ID) ? 7 : 6306 (TOP_STRAP_STATUS_1_REF(strap_sts_1) == 0) ? 0 : 7); 6307 soc_reg_field32_modify(unit, TOP_BS_PLL0_CTRL_5r, REG_PORT_ANY, 6308 RZf, (rev_id < BCM56160_B0_REV_ID) ? 7 : 6309 (TOP_STRAP_STATUS_1_REF(strap_sts_1) == 0) ? 6 : 2); 6310 soc_reg_field32_modify(unit, TOP_BS_PLL0_CTRL_5r, REG_PORT_ANY, 6311 ICPf, (rev_id < BCM56160_B0_REV_ID) ? 16 : 6312 (TOP_STRAP_STATUS_1_REF(strap_sts_1) == 0) ? 20 : 10); 6313 soc_reg_field32_modify(unit, TOP_BS_PLL0_CTRL_7r, REG_PORT_ANY, 6314 CPPf, 0x80); 6315 6316 soc_reg_field32_modify(unit, TOP_BS_PLL1_CTRL_6r, REG_PORT_ANY, 6317 LDO_CTRLf, (rev_id < BCM56160_B0_REV_ID) ? 0x2a : 0x22); 6318 soc_reg_field32_modify(unit, TOP_BS_PLL1_CTRL_7r, REG_PORT_ANY, 6319 FREQ_DOUBLER_ONf, 0); 6320 soc_reg_field32_modify(unit, TOP_BS_PLL1_CTRL_6r, REG_PORT_ANY, 6321 MSC_CTRLf, 6322 (rev_id < BCM56160_B0_REV_ID) ? 0x0022 : 6323 (TOP_STRAP_STATUS_1_REF(strap_sts_1) == 0) 6324 ? 0x0022: 0x1022); 6325 soc_reg_field32_modify(unit, TOP_BS_PLL1_CTRL_7r, REG_PORT_ANY, 6326 VCO_CONT_ADJf, 1); 6327 soc_reg_field32_modify(unit, TOP_BS_PLL1_CTRL_3r, REG_PORT_ANY, 6328 VCO_CURf, 0); 6329 soc_reg_field32_modify(unit, TOP_BS_PLL1_CTRL_5r, REG_PORT_ANY, 6330 VCO_GAINf, (rev_id < BCM56160_B0_REV_ID) ? 3 : 15); 6331 soc_reg_field32_modify(unit, TOP_MISC_CONTROL_1r, REG_PORT_ANY, 6332 CMIC_TO_BS_PLL1_SW_OVWRf, 1); 6333 soc_reg_field32_modify(unit, TOP_BS_PLL1_CTRL_5r, REG_PORT_ANY, 6334 CP1f, 1); 6335 soc_reg_field32_modify(unit, TOP_BS_PLL1_CTRL_5r, REG_PORT_ANY, 6336 CPf, 3); 6337 soc_reg_field32_modify(unit, TOP_BS_PLL1_CTRL_5r, REG_PORT_ANY, 6338 CZf, 3); 6339 soc_reg_field32_modify(unit, TOP_BS_PLL1_CTRL_5r, REG_PORT_ANY, 6340 RPf, (rev_id < BCM56160_B0_REV_ID) ? 7 : 6341 (TOP_STRAP_STATUS_1_REF(strap_sts_1) == 0) ? 0 : 7); 6342 soc_reg_field32_modify(unit, TOP_BS_PLL1_CTRL_5r, REG_PORT_ANY, 6343 RZf, (rev_id < BCM56160_B0_REV_ID) ? 7 : 6344 (TOP_STRAP_STATUS_1_REF(strap_sts_1) == 0) ? 6 : 2); 6345 soc_reg_field32_modify(unit, TOP_BS_PLL1_CTRL_5r, REG_PORT_ANY, 6346 ICPf, (rev_id < BCM56160_B0_REV_ID) ? 16 : 6347 (TOP_STRAP_STATUS_1_REF(strap_sts_1) == 0) ? 20 : 10); 6348 soc_reg_field32_modify(unit, TOP_BS_PLL1_CTRL_7r, REG_PORT_ANY, 6349 CPPf, 0x80); 6350 6351 for (bs_idx = 0; bs_idx < sizeof(bs_pll)/sizeof(bs_pll[0]); ++bs_idx) { 6352 if (bs_pll[bs_idx].ref_freq == bs_ref_freq) { 6353 break; 6354 } 6355 } 6356 /* differentiang between internal 25Mhz or 50MHz clk */ 6357 if (bs_ref_freq == 0) { 6358 if (rev_id < BCM56160_B0_REV_ID) { 6359 /* only 25Mhz internal clk */ 6360 bs_idx = 2; 6361 } else { 6362 /* 25MHz or 50MHz internal clk depeding upon strap setting */ 6363 bs_idx = (TOP_STRAP_STATUS_1_REF(strap_sts_1) == 0) ? 2 : 3; 6364 } 6365 } 6366 6367 if (bs_idx == sizeof(bs_pll)/sizeof(bs_pll[0])) { 6368 LOG_ERROR(BSL_LS_SOC_COMMON, 6369 (BSL_META_U(unit, 6370 "Invalid value for PTP_BS_REF (%u). No default PLL params.\n"), bs_ref_freq)); 6371 /* Could check for existence of SOC properties for KA, KI, KP, NDIV_INT, 6372 NDIV_FRAC, MDIV, PDIV, and if all exist, use them. For now, just fail. 6373 */ 6374 } else { 6375 soc_reg_field32_modify(unit, TOP_BS_PLL0_CTRL_1r, REG_PORT_ANY, 6376 KAf, 6377 soc_property_get(unit, spn_PTP_BS_KA, bs_pll[bs_idx].ka)); 6378 6379 soc_reg_field32_modify(unit, TOP_BS_PLL0_CTRL_1r, REG_PORT_ANY, 6380 KIf, 6381 soc_property_get(unit, spn_PTP_BS_KI, bs_pll[bs_idx].ki)); 6382 6383 soc_reg_field32_modify(unit, TOP_BS_PLL0_CTRL_1r, REG_PORT_ANY, 6384 KPf, 6385 soc_property_get(unit, spn_PTP_BS_KP, bs_pll[bs_idx].kp)); 6386 6387 soc_reg_field32_modify(unit, TOP_BS_PLL0_CTRL_1r, REG_PORT_ANY, 6388 PDIVf, 6389 soc_property_get(unit, spn_PTP_BS_PDIV, bs_pll[bs_idx].pdiv)); 6390 6391 soc_reg_field32_modify(unit, TOP_BS_PLL1_CTRL_1r, REG_PORT_ANY, 6392 KAf, 6393 soc_property_get(unit, spn_PTP_BS_KA, bs_pll[bs_idx].ka)); 6394 6395 soc_reg_field32_modify(unit, TOP_BS_PLL1_CTRL_1r, REG_PORT_ANY, 6396 KIf, 6397 soc_property_get(unit, spn_PTP_BS_KI, bs_pll[bs_idx].ki)); 6398 6399 soc_reg_field32_modify(unit, TOP_BS_PLL1_CTRL_1r, REG_PORT_ANY, 6400 KPf, 6401 soc_property_get(unit, spn_PTP_BS_KP, bs_pll[bs_idx].kp)); 6402 6403 soc_reg_field32_modify(unit, TOP_BS_PLL1_CTRL_1r, REG_PORT_ANY, 6404 PDIVf, 6405 soc_property_get(unit, spn_PTP_BS_PDIV, bs_pll[bs_idx].pdiv)); 6406 6407 /* ndiv_int: 10 bits. ndiv_frac: 24 bits, stored in upper 24 6408 * ndiv_int = BROAD_SYNC0_LCPLL_FBDIV_1[15:6]; 6409 * ndiv_frac = {BROAD_SYNC0_LCPLL_FBDIV_1[5:0], 6410 * BROAD_SYNC0_LCPLL_FBDIV_0[31:14]}; 6411 * So FBDIV_1 = (ndiv_int << 6) | (ndiv_frac >> (32-6)) 6412 * FBDIV_2 = (ndiv_frac >> 6) 6413 */ 6414 bs_ndiv_high = ((soc_property_get(unit, spn_PTP_BS_NDIV_INT, 6415 bs_pll[bs_idx].ndiv_int) << 6) | 6416 ((soc_property_get(unit, spn_PTP_BS_NDIV_FRAC, 6417 bs_pll[bs_idx].ndiv_frac) >> (32-6)) & 0x3f)); 6418 bs_ndiv_low = (soc_property_get(unit, spn_PTP_BS_NDIV_FRAC, 6419 bs_pll[bs_idx].ndiv_frac) << 8); 6420 6421 soc_reg_field32_modify(unit, 6422 TOP_BROAD_SYNC0_LCPLL_FBDIV_CTRL_1r, REG_PORT_ANY, 6423 BROAD_SYNC0_LCPLL_FBDIV_1f, 6424 bs_ndiv_high); 6425 6426 soc_reg_field32_modify(unit, 6427 TOP_BROAD_SYNC0_LCPLL_FBDIV_CTRL_0r, REG_PORT_ANY, 6428 BROAD_SYNC0_LCPLL_FBDIV_0f, 6429 bs_ndiv_low); 6430 6431 soc_reg_field32_modify(unit, 6432 TOP_BROAD_SYNC1_LCPLL_FBDIV_CTRL_1r, REG_PORT_ANY, 6433 BROAD_SYNC1_LCPLL_FBDIV_1f, 6434 bs_ndiv_high); 6435 6436 soc_reg_field32_modify(unit, 6437 TOP_BROAD_SYNC1_LCPLL_FBDIV_CTRL_0r, REG_PORT_ANY, 6438 BROAD_SYNC1_LCPLL_FBDIV_0f, 6439 bs_ndiv_low); 6440 6441 soc_reg_field32_modify(unit, TOP_BS_PLL0_CTRL_0r, REG_PORT_ANY, 6442 CH0_MDIVf, 6443 soc_property_get(unit, spn_PTP_BS_MNDIV, bs_pll[bs_idx].mdiv)); 6444 6445 soc_reg_field32_modify(unit, TOP_BS_PLL1_CTRL_0r, REG_PORT_ANY, 6446 CH0_MDIVf, 6447 soc_property_get(unit, spn_PTP_BS_MNDIV, bs_pll[bs_idx].mdiv)); 6448 6449 soc_reg_field32_modify(unit, TOP_BS_PLL0_CTRL_1r, REG_PORT_ANY, 6450 LOAD_EN_CHf, 0); 6451 soc_reg_field32_modify(unit, TOP_BS_PLL0_CTRL_1r, REG_PORT_ANY, 6452 LOAD_EN_CHf, 1); 6453 6454 soc_reg_field32_modify(unit, TOP_BS_PLL1_CTRL_1r, REG_PORT_ANY, 6455 LOAD_EN_CHf, 0); 6456 soc_reg_field32_modify(unit, TOP_BS_PLL1_CTRL_1r, REG_PORT_ANY, 6457 LOAD_EN_CHf, 1); 6458 } 6459 6460 soc_reg_field32_modify(unit, TOP_SOFT_RESET_REG_2r, REG_PORT_ANY, 6461 TOP_BS_PLL0_RST_Lf, 1); 6462 6463 soc_reg_field32_modify(unit, TOP_SOFT_RESET_REG_2r, REG_PORT_ANY, 6464 TOP_BS_PLL1_RST_Lf, 1); 6465 6466 sal_usleep(to_usec); 6467 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REG_2r(unit, &rval)); 6468 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, TOP_BS_PLL0_POST_RST_Lf, 1); 6469 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, TOP_BS_PLL1_POST_RST_Lf, 1); 6470 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REG_2r(unit, rval)); 6471 } 6472 6473 if (!hitless) { 6474 /* Initialize XGPLLs */ 6475 soc_reg_field32_modify(unit, TOP_SOFT_RESET_REGr, REG_PORT_ANY, 6476 TOP_LCPLL_SOFT_RESETf, 1); 6477 6478 /* XGPLL0 */ 6479 soc_reg_field32_modify(unit, TOP_XG_PLL0_CTRL_1r, REG_PORT_ANY, 6480 PDIVf, 1); 6481 soc_reg_field32_modify(unit, TOP_XG_PLL0_CTRL_0r, REG_PORT_ANY, 6482 CH0_MDIVf, 0x14); 6483 soc_reg_field32_modify(unit, TOP_XG_PLL0_CTRL_6r, REG_PORT_ANY, 6484 LDO_CTRLf, (rev_id < BCM56160_B0_REV_ID) ? 0x2a : 0x22); 6485 /* Use strap for setting of FREQ_DOUBLER */ 6486 soc_reg_field32_modify(unit, TOP_XG_PLL0_CTRL_7r, REG_PORT_ANY, 6487 FREQ_DOUBLER_ONf, (TOP_STRAP_STATUS_1_REF(strap_sts_1) == 0)); 6488 soc_reg_field32_modify(unit, TOP_XG_PLL0_CTRL_7r, REG_PORT_ANY, 6489 VCO_CONT_ADJf, 1); 6490 soc_reg_field32_modify(unit, TOP_XG_PLL0_CTRL_3r, REG_PORT_ANY, 6491 VCO_CURf, 0); 6492 soc_reg_field32_modify(unit, TOP_XG_PLL0_CTRL_5r, REG_PORT_ANY, 6493 VCO_GAINf, (rev_id < BCM56160_B0_REV_ID) ? 3 : 15); 6494 soc_reg_field32_modify(unit, TOP_MISC_CONTROL_1r, REG_PORT_ANY, 6495 CMIC_TO_XG_PLL0_SW_OVWRf, 1); 6496 soc_reg_field32_modify(unit, TOP_XG0_LCPLL_FBDIV_CTRL_0r, REG_PORT_ANY, 6497 XG0_LCPLL_FBDIV_0f, 0); 6498 soc_reg_field32_modify(unit, TOP_XG0_LCPLL_FBDIV_CTRL_1r, REG_PORT_ANY, 6499 XG0_LCPLL_FBDIV_1f, 0x0fa0); 6500 soc_reg_field32_modify(unit, TOP_XG_PLL0_CTRL_5r, REG_PORT_ANY, 6501 CP1f, 1); 6502 soc_reg_field32_modify(unit, TOP_XG_PLL0_CTRL_5r, REG_PORT_ANY, 6503 CPf, 3); 6504 soc_reg_field32_modify(unit, TOP_XG_PLL0_CTRL_5r, REG_PORT_ANY, 6505 CZf, 3); 6506 soc_reg_field32_modify(unit, TOP_XG_PLL0_CTRL_5r, REG_PORT_ANY, 6507 RPf, 7); 6508 soc_reg_field32_modify(unit, TOP_XG_PLL0_CTRL_5r, REG_PORT_ANY, 6509 RZf, (rev_id < BCM56160_B0_REV_ID) ? 7 : 2); 6510 soc_reg_field32_modify(unit, TOP_XG_PLL0_CTRL_5r, REG_PORT_ANY, 6511 ICPf, (rev_id < BCM56160_B0_REV_ID) ? 16 : 10); 6512 soc_reg_field32_modify(unit, TOP_XG_PLL0_CTRL_7r, REG_PORT_ANY, 6513 CPPf, 0x80); 6514 6515 /* XGPLL1 */ 6516 6517 if (TOP_STRAP_STATUS_LCPLL1_REF(strap_sts)) { 6518 soc_reg_field32_modify(unit, TOP_XG_PLL1_CTRL_1r, REG_PORT_ANY, 6519 PDIVf, 1); 6520 soc_reg_field32_modify(unit, TOP_XG_PLL1_CTRL_0r, REG_PORT_ANY, 6521 CH0_MDIVf, 0x14); 6522 /* Use strap for setting of FREQ_DOUBLER */ 6523 soc_reg_field32_modify(unit, TOP_XG_PLL1_CTRL_7r, REG_PORT_ANY, 6524 FREQ_DOUBLER_ONf, (TOP_STRAP_STATUS_1_REF(strap_sts_1) == 0)); 6525 soc_reg_field32_modify(unit, TOP_XG_PLL1_CTRL_6r, REG_PORT_ANY, 6526 MSC_CTRLf, 0x00a2); 6527 soc_reg_field32_modify(unit, TOP_XG_PLL1_CTRL_6r, REG_PORT_ANY, 6528 LDO_CTRLf, (rev_id < BCM56160_B0_REV_ID) ? 0x2a : 0x22); 6529 soc_reg_field32_modify(unit, TOP_XG_PLL1_CTRL_7r, REG_PORT_ANY, 6530 VCO_CONT_ADJf, 1); 6531 soc_reg_field32_modify(unit, TOP_XG_PLL1_CTRL_3r, REG_PORT_ANY, 6532 VCO_CURf, 0); 6533 soc_reg_field32_modify(unit, TOP_XG_PLL1_CTRL_5r, REG_PORT_ANY, 6534 VCO_GAINf, (rev_id < BCM56160_B0_REV_ID) ? 3 : 15); 6535 soc_reg_field32_modify(unit, TOP_MISC_CONTROL_1r, REG_PORT_ANY, 6536 CMIC_TO_XG_PLL1_SW_OVWRf, 1); 6537 soc_reg_field32_modify(unit, TOP_XG_PLL1_CTRL_5r, REG_PORT_ANY, 6538 CP1f, 1); 6539 soc_reg_field32_modify(unit, TOP_XG_PLL1_CTRL_5r, REG_PORT_ANY, 6540 CPf, 3); 6541 soc_reg_field32_modify(unit, TOP_XG_PLL1_CTRL_5r, REG_PORT_ANY, 6542 CZf, 3); 6543 soc_reg_field32_modify(unit, TOP_XG_PLL1_CTRL_5r, REG_PORT_ANY, 6544 RPf, 7); 6545 soc_reg_field32_modify(unit, TOP_XG_PLL1_CTRL_5r, REG_PORT_ANY, 6546 RZf, (rev_id < BCM56160_B0_REV_ID) ? 7 : 2); 6547 soc_reg_field32_modify(unit, TOP_XG_PLL1_CTRL_5r, REG_PORT_ANY, 6548 ICPf, (rev_id < BCM56160_B0_REV_ID) ? 16 : 10); 6549 soc_reg_field32_modify(unit, TOP_XG_PLL1_CTRL_7r, REG_PORT_ANY, 6550 CPPf, 0x80); 6551 soc_reg_field32_modify(unit, TOP_XG1_LCPLL_FBDIV_CTRL_0r, REG_PORT_ANY, 6552 XG1_LCPLL_FBDIV_0f, 0); 6553 soc_reg_field32_modify(unit, TOP_XG1_LCPLL_FBDIV_CTRL_1r, REG_PORT_ANY, 6554 XG1_LCPLL_FBDIV_1f, 0x0fa0); 6555 } else { 6556 /* TOP_STRAP_STATUS_LCPLL1_REF == 0 */ 6557 soc_reg_field32_modify(unit, TOP_XG_PLL1_CTRL_1r, REG_PORT_ANY, 6558 PDIVf, 3); 6559 soc_reg_field32_modify(unit, TOP_XG_PLL1_CTRL_0r, REG_PORT_ANY, 6560 CH0_MDIVf, 0x14); 6561 soc_reg_field32_modify(unit, TOP_XG_PLL1_CTRL_7r, REG_PORT_ANY, 6562 FREQ_DOUBLER_ONf, 0); 6563 soc_reg_field32_modify(unit, TOP_XG_PLL1_CTRL_6r, REG_PORT_ANY, 6564 MSC_CTRLf, 0xcaa4); 6565 soc_reg_field32_modify(unit, TOP_XG_PLL1_CTRL_7r, REG_PORT_ANY, 6566 VCO_CONT_ADJf, 1); 6567 soc_reg_field32_modify(unit, TOP_XG_PLL1_CTRL_3r, REG_PORT_ANY, 6568 VCO_CURf, 0); 6569 soc_reg_field32_modify(unit, TOP_XG_PLL1_CTRL_5r, REG_PORT_ANY, 6570 VCO_GAINf, (rev_id < BCM56160_B0_REV_ID) ? 3 : 15); 6571 soc_reg_field32_modify(unit, TOP_MISC_CONTROL_1r, REG_PORT_ANY, 6572 CMIC_TO_XG_PLL1_SW_OVWRf, 1); 6573 soc_reg_field32_modify(unit, TOP_XG_PLL1_CTRL_5r, REG_PORT_ANY, 6574 CP1f, 1); 6575 soc_reg_field32_modify(unit, TOP_XG_PLL1_CTRL_5r, REG_PORT_ANY, 6576 CPf, 1); 6577 soc_reg_field32_modify(unit, TOP_XG_PLL1_CTRL_5r, REG_PORT_ANY, 6578 CZf, 3); 6579 soc_reg_field32_modify(unit, TOP_XG_PLL1_CTRL_5r, REG_PORT_ANY, 6580 RPf, 0); 6581 soc_reg_field32_modify(unit, TOP_XG_PLL1_CTRL_5r, REG_PORT_ANY, 6582 RZf, (rev_id < BCM56160_B0_REV_ID) ? 8 : 2); 6583 soc_reg_field32_modify(unit, TOP_XG_PLL1_CTRL_5r, REG_PORT_ANY, 6584 ICPf, (rev_id < BCM56160_B0_REV_ID) ? 32 : 20); 6585 soc_reg_field32_modify(unit, TOP_XG_PLL1_CTRL_7r, REG_PORT_ANY, 6586 CPPf, 0x80); 6587 soc_reg_field32_modify(unit, TOP_XG_PLL1_CTRL_6r, REG_PORT_ANY, 6588 LDO_CTRLf, (rev_id < BCM56160_B0_REV_ID) ? 0x2a : 0x22); 6589 soc_reg_field32_modify(unit, TOP_XG1_LCPLL_FBDIV_CTRL_0r, REG_PORT_ANY, 6590 XG1_LCPLL_FBDIV_0f, 0); 6591 soc_reg_field32_modify(unit, TOP_XG1_LCPLL_FBDIV_CTRL_1r, REG_PORT_ANY, 6592 XG1_LCPLL_FBDIV_1f, 0x0f00); 6593 } 6594 6595 soc_reg_field32_modify(unit, TOP_SOFT_RESET_REGr, REG_PORT_ANY, 6596 TOP_LCPLL_SOFT_RESETf, 0); 6597 } 6598 6599 /* Select LCPLL0 as external PHY reference clock and output 125MHz */ 6600 /* Pull GPIO3 low to reset the ext. PHY */ 6601 SOC_IF_ERROR_RETURN(_soc_hurricane3_gpio_set(unit, 3, TRUE, 0)); 6602 6603 SOC_IF_ERROR_RETURN 6604 (soc_reg_field32_modify(unit, TOP_XG_PLL0_CTRL_0r, 6605 REG_PORT_ANY, CH5_MDIVf, 0x19)); 6606 6607 /* Select LCPLL0 clock source. */ 6608 refclk = soc_property_get(unit, spn_LC_PLL_EXT_CLOCK, 0); 6609 if (refclk == 0) { 6610 /* Clock source of LCPLL0 is from internal XTAL. */ 6611 SOC_IF_ERROR_RETURN 6612 (soc_reg_field32_modify(unit, TOP_XG_PLL0_CTRL_6r, 6613 REG_PORT_ANY, MSC_CTRLf, 0x71a2)); 6614 } else { 6615 /* Clock source of LCPLL0 is from external XTAL. */ 6616 if (refclk == 25) { 6617 SOC_IF_ERROR_RETURN 6618 (soc_reg_field32_modify(unit, TOP_XG_PLL0_CTRL_6r, 6619 REG_PORT_ANY, MSC_CTRLf, 0x71a4)); 6620 /* 6621 * External source 25MHz, FREQ_DOUBLER_ONf = 1 6622 */ 6623 SOC_IF_ERROR_RETURN 6624 (soc_reg_field32_modify(unit, TOP_XG_PLL0_CTRL_7r, REG_PORT_ANY, 6625 FREQ_DOUBLER_ONf, 1)); 6626 } else if (refclk == 50) { 6627 SOC_IF_ERROR_RETURN 6628 (soc_reg_field32_modify(unit, TOP_XG_PLL0_CTRL_6r, 6629 REG_PORT_ANY, MSC_CTRLf, 0x71a4)); 6630 /* 6631 * External source 50MHz, FREQ_DOUBLER_ONf = 0 6632 */ 6633 SOC_IF_ERROR_RETURN 6634 (soc_reg_field32_modify(unit, TOP_XG_PLL0_CTRL_7r, REG_PORT_ANY, 6635 FREQ_DOUBLER_ONf, 0)); 6636 } else { 6637 /* Other values. */ 6638 LOG_WARN(BSL_LS_SOC_COMMON, 6639 (BSL_META_U(unit, "Warning: unsupported LC_PLL0 external " 6640 "source clock %d MHz.\n"), refclk)); 6641 } 6642 } 6643 6644 /* Pull GPIO high to leave the reset state */ 6645 SOC_IF_ERROR_RETURN(_soc_hurricane3_gpio_set(unit, 3, TRUE, 1)); 6646 6647 /* TSCx or QTCx should be disabled in some sku. */ 6648 if (matched_devid_idx[unit] == -1) { 6649 LOG_WARN(BSL_LS_SOC_COMMON, 6650 (BSL_META_U(unit, "Warning: soc_hurricane3_port_config_init should " 6651 "be invoked first! Choose bcm534x1 port config.\n"))); 6652 matched_devid_idx[unit] = 0; 6653 } 6654 6655 matched_sku_info = &_hr3_sku_port_config[matched_devid_idx[unit]]; 6656 disabled_bmp = matched_sku_info->disabled_tsc_bmp; 6657 disable_tsc = TOP_STRAP_STATUS_TSC_DISABLE(strap_sts); 6658 disable_qtc = TOP_STRAP_STATUS_QTC_DISABLE(strap_sts); 6659 disable_gphy = matched_sku_info->disabled_gphy_bmp; 6660 for (i = 0; i < _HR3_MAX_TSC_COUNT; i++) { 6661 if((1 << i) & disabled_bmp){ 6662 disable_tsc |= (1 << i); 6663 } 6664 } 6665 6666 disabled_bmp = matched_sku_info->disabled_qtc_bmp; 6667 for (i = 0; i < _HR3_MAX_QTC_COUNT; i++) { 6668 if((1 << i) & disabled_bmp){ 6669 disable_qtc |= (1 << i); 6670 } 6671 } 6672 6673 if (disable_tsc) { 6674 SOC_IF_ERROR_RETURN( 6675 _soc_hurricane3_core_disable(unit, SOC_HR3_PORT_CORE_TYPE_TSC, 6676 disable_tsc, 0)); 6677 } 6678 if (disable_qtc) { 6679 SOC_IF_ERROR_RETURN( 6680 _soc_hurricane3_core_disable(unit, SOC_HR3_PORT_CORE_TYPE_QTC, 6681 disable_qtc, disable_gphy)); 6682 } 6683 6684 /* Configure GPHY bypass mode */ 6685 SOC_IF_ERROR_RETURN( 6686 _soc_hurricane3_port_gphy_mode_init(unit)); 6687 6688 /* re-ordering the port sequence */ 6689 soc_esw_dport_init(unit); 6690 6691 SOC_IF_ERROR_RETURN(READ_PGW_CTRL_0r(unit, &rval)); 6692 soc_reg_field_set(unit, PGW_CTRL_0r, &rval, SW_PM4X10_DISABLEf, disable_tsc); 6693 soc_reg_field_set(unit, PGW_CTRL_0r, &rval, SW_QTC_DISABLEf, disable_qtc); 6694 SOC_IF_ERROR_RETURN(WRITE_PGW_CTRL_0r(unit, rval)); 6695 sal_usleep(to_usec); 6696 6697 /* 6698 * Bring port blocks out of reset 6699 */ 6700 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REGr(unit, &rval)); 6701 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_QGPHY_RST_Lf, 0xf); 6702 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_XLP0_RST_Lf, 1); 6703 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_XLP1_RST_Lf, 1); 6704 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_GXP0_RST_Lf, 1); 6705 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_GXP1_RST_Lf, 1); 6706 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REGr(unit, rval)); 6707 sal_usleep(to_usec); 6708 6709 /* Bring network sync out of reset */ 6710 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REGr(unit, &rval)); 6711 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_TS_RST_Lf, 1); 6712 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REGr(unit, rval)); 6713 sal_usleep(to_usec); 6714 6715 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REG_2r(unit, &rval)); 6716 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, TOP_TS_PLL_RST_Lf, 1); 6717 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REG_2r(unit, rval)); 6718 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, TOP_TS_PLL_POST_RST_Lf, 1); 6719 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REG_2r(unit, rval)); 6720 6721 /* Bring IP, EP, and MMU blocks out of reset */ 6722 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REGr(unit, &rval)); 6723 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_EP_RST_Lf, 1); 6724 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_IP_RST_Lf, 1); 6725 soc_reg_field_set(unit, TOP_SOFT_RESET_REGr, &rval, TOP_MMU_RST_Lf, 1); 6726 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REGr(unit, rval)); 6727 sal_usleep(to_usec); 6728 6729 return SOC_E_NONE; 6730 } 6731 6732 6733 STATIC int 6734 _soc_hurricane3_age_timer_get(int unit, int *age_seconds, int *enabled) 6735 { 6736 uint32 value; 6737 6738 SOC_IF_ERROR_RETURN(READ_L2_AGE_TIMERr(unit, &value)); 6739 *enabled = soc_reg_field_get(unit, L2_AGE_TIMERr, value, AGE_ENAf); 6740 *age_seconds = soc_reg_field_get(unit, L2_AGE_TIMERr, value, AGE_VALf); 6741 6742 return SOC_E_NONE; 6743 } 6744 6745 STATIC int 6746 _soc_hurricane3_age_timer_max_get(int unit, int *max_seconds) 6747 { 6748 *max_seconds = 6749 soc_reg_field_get(unit, L2_AGE_TIMERr, 0xffffffff, AGE_VALf); 6750 6751 return SOC_E_NONE; 6752 } 6753 6754 STATIC int 6755 _soc_hurricane3_age_timer_set(int unit, int age_seconds, int enable) 6756 { 6757 uint32 value; 6758 6759 value = 0; 6760 soc_reg_field_set(unit, L2_AGE_TIMERr, &value, AGE_ENAf, enable); 6761 soc_reg_field_set(unit, L2_AGE_TIMERr, &value, AGE_VALf, age_seconds); 6762 SOC_IF_ERROR_RETURN(WRITE_L2_AGE_TIMERr(unit, value)); 6763 6764 return SOC_E_NONE; 6765 } 6766 6767 static const soc_reg_t pvtmon_result_reg[] = { 6768 TOP_PVTMON_RESULT_0r 6769 }; 6770 6771 int 6772 soc_hr3_temperature_monitor_get(int unit, 6773 int temperature_max, 6774 soc_switch_temperature_monitor_t *temperature_array, 6775 int *temperature_count) 6776 { 6777 soc_reg_t reg; 6778 int index; 6779 uint32 rval; 6780 int fval, cur, peak; 6781 int num_entries_out; 6782 6783 *temperature_count = 0; 6784 if (COUNTOF(pvtmon_result_reg) > temperature_max) { 6785 num_entries_out = temperature_max; 6786 } else { 6787 num_entries_out = COUNTOF(pvtmon_result_reg); 6788 } 6789 6790 for (index = 0; index < num_entries_out; index++) { 6791 reg = pvtmon_result_reg[index]; 6792 SOC_IF_ERROR_RETURN(soc_reg32_get(unit, reg, REG_PORT_ANY, 0, &rval)); 6793 6794 fval = soc_reg_field_get(unit, reg, rval, PVT_DATAf); 6795 cur = (41004000 - (48705 * fval)) / 10000; 6796 fval = soc_reg_field_get(unit, reg, rval, PEAK_TEMP_DATAf); 6797 peak = (41004000 - (48705 * fval)) / 10000; 6798 (temperature_array + index)->curr = cur; 6799 (temperature_array + index)->peak = peak; 6800 } 6801 SOC_IF_ERROR_RETURN(READ_TOP_SOFT_RESET_REG_2r(unit, &rval)); 6802 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, 6803 TOP_TEMP_MON_PEAK_RST_Lf, 0); 6804 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REG_2r(unit, rval)); 6805 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, 6806 TOP_TEMP_MON_PEAK_RST_Lf, 1); 6807 SOC_IF_ERROR_RETURN(WRITE_TOP_SOFT_RESET_REG_2r(unit, rval)); 6808 6809 *temperature_count=num_entries_out; 6810 return SOC_E_NONE; 6811 } 6812 6813 typedef struct _hr3_pgw_reg_info_s { 6814 soc_reg_t pgw_reg; 6815 uint32 valid_bm; 6816 uint32 invalid_bm; 6817 uint32 invalid_blk_num_bm; 6818 }_hr3_pgw_reg_info_t; 6819 6820 STATIC _hr3_pgw_reg_info_t _hr3_pgw_reg_info[] = { 6821 {PGW_GX_CONFIGr, 0x3c, 0, 0x1f}, 6822 {PGW_GX_TXFIFO_CTRLr, 0x3c, 0, 0x1f}, 6823 {PGW_GX_SPARE0_REGr, 0x3c, 0, 0x1f}, 6824 {PGW_GX_RXFIFO_SOFT_RESETr, 0, 0, 0x1f}, 6825 {PGW_GX_ECC_CONTROLr, 0, 0, 0x1f}, 6826 {PGW_GX_RXFIFO0_ECC_SBE_STATUSr, 0, 0, 0x1f}, 6827 {PGW_GX_RXFIFO0_ECC_DBE_STATUSr, 0, 0, 0x1f}, 6828 {PGW_GX_RXFIFO1_ECC_SBE_STATUSr, 0, 0, 0x1f}, 6829 {PGW_GX_RXFIFO1_ECC_DBE_STATUSr, 0, 0, 0x1f}, 6830 {PGW_GX_TXFIFO0_ECC_SBE_STATUSr, 0, 0, 0x1f}, 6831 {PGW_GX_TXFIFO0_ECC_DBE_STATUSr, 0, 0, 0x1f}, 6832 {PGW_GX_TXFIFO1_ECC_SBE_STATUSr, 0, 0, 0x1f}, 6833 {PGW_GX_TXFIFO1_ECC_DBE_STATUSr, 0, 0, 0x1f}, 6834 {PGW_GX_TXFIFO2_ECC_SBE_STATUSr, 0, 0, 0x1f}, 6835 {PGW_GX_TXFIFO2_ECC_DBE_STATUSr, 0, 0, 0x1f}, 6836 {PGW_GX_TXFIFO3_ECC_SBE_STATUSr, 0, 0, 0x1f}, 6837 {PGW_GX_TXFIFO3_ECC_DBE_STATUSr, 0, 0, 0x1f}, 6838 {PGW_GX_TXFIFO_OVERFLOWr, 0, 0, 0x1f}, 6839 {PGW_GX_RXFIFO0_OVERFLOW_ERRORr, 0, 0, 0x1f}, 6840 {PGW_GX_RXFIFO1_OVERFLOW_ERRORr, 0, 0, 0x1f}, 6841 {PGW_GX_TM0_CONTROLr, 0, 0, 0x1f}, 6842 {PGW_GX_TM1_CONTROLr, 0, 0, 0x1f}, 6843 {PGW_GX_TM2_CONTROLr, 0, 0, 0x1f}, 6844 {PGW_GX_TM3_CONTROLr, 0, 0, 0x1f}, 6845 {PGW_GX_TM4_CONTROLr, 0, 0, 0x1f}, 6846 {PGW_GX_TM5_CONTROLr, 0, 0, 0x1f}, 6847 {PGW_GX_TM6_CONTROLr, 0, 0, 0x1f}, 6848 {PGW_GX_TM7_CONTROLr, 0, 0, 0x1f}, 6849 {PGW_GX_TM8_CONTROLr, 0, 0, 0x1f}, 6850 {PGW_GX_BYPASS_LED_CHAIN_CONFIGr, 0, 0, 0x1f}, 6851 {PGW_GX_INTR_STATUSr, 0, 0, 0x1f}, 6852 {PGW_GX_INTR_ENABLEr, 0, 0, 0x1f}, 6853 {PGW_XL_CONFIGr, 0, 0x3c, 0x20}, 6854 {PGW_XL_TXFIFO_CTRLr, 0, 0x3c, 0x20}, 6855 {PGW_XL_SPARE0_REGr, 0, 0x3c, 0x20}, 6856 {PGW_XL_RXFIFO_SOFT_RESETr, 0, 0, 0x20}, 6857 {PGW_XL_ECC_CONTROLr, 0, 0, 0x20}, 6858 {PGW_XL_RXFIFO_ECC_SBE_STATUSr, 0, 0, 0x20}, 6859 {PGW_XL_RXFIFO_ECC_DBE_STATUSr, 0, 0, 0x20}, 6860 {PGW_XL_TXFIFO0_ECC_SBE_STATUSr, 0, 0, 0x20}, 6861 {PGW_XL_TXFIFO0_ECC_DBE_STATUSr, 0, 0, 0x20}, 6862 {PGW_XL_TXFIFO1_ECC_SBE_STATUSr, 0, 0, 0x20}, 6863 {PGW_XL_TXFIFO1_ECC_DBE_STATUSr, 0, 0, 0x20}, 6864 {PGW_XL_TXFIFO2_ECC_SBE_STATUSr, 0, 0, 0x20}, 6865 {PGW_XL_TXFIFO2_ECC_DBE_STATUSr, 0, 0, 0x20}, 6866 {PGW_XL_TXFIFO3_ECC_SBE_STATUSr, 0, 0, 0x20}, 6867 {PGW_XL_TXFIFO3_ECC_DBE_STATUSr, 0, 0, 0x20}, 6868 {PGW_XL_TXFIFO_OVERFLOWr, 0, 0, 0x20}, 6869 {PGW_XL_RXFIFO_OVERFLOW_ERRORr, 0, 0, 0x20}, 6870 {PGW_XL_TM0_CONTROLr, 0, 0, 0x20}, 6871 {PGW_XL_TM1_CONTROLr, 0, 0, 0x20}, 6872 {PGW_XL_TM2_CONTROLr, 0, 0, 0x20}, 6873 {PGW_XL_TM3_CONTROLr, 0, 0, 0x20}, 6874 {PGW_XL_TM4_CONTROLr, 0, 0, 0x20}, 6875 {PGW_XL_TM5_CONTROLr, 0, 0, 0x20}, 6876 {PGW_XL_TM6_CONTROLr, 0, 0, 0x20}, 6877 {PGW_XL_TM7_CONTROLr, 0, 0, 0x20}, 6878 {PGW_XL_TM8_CONTROLr, 0, 0, 0x20}, 6879 {PGW_XL_BYPASS_LED_CHAIN_CONFIGr, 0, 0, 0x20}, 6880 {PGW_XL_INTR_STATUSr, 0, 0, 0x20}, 6881 {PGW_XL_INTR_ENABLEr, 0, 0, 0x20}, 6882 {INVALIDr, 0, 0}, 6883 }; 6884 6885 /* 6886 * Function: 6887 * soc_hurricane3_pgw_reg_blk_index_get 6888 * Purpose: 6889 * Deal with the blk, blknum for PGW_GX and PGW_XL registers 6890 * Parameters: 6891 * reg (IN): register. 6892 * port (IN): logical port if PGW_GX's port register. 6893 * bm (IN/OUT): bm should be added for the reg. 6894 * block (IN/OUT): blk used to access the reg. 6895 * index (OUT): port index of the reg. 6896 * invalid_blk_check (IN): perform the blk check. 6897 * skip the block if the return value = 1. 6898 * Return: 6899 * SOC_E_NOT_FOUND : w/o bm,blk,invalid_blk_check case, register not matched. 6900 * 1 : register matched and the block/index has been override. 6901 * 1 : register matched and the valid bm has been override. 6902 * 1 : skip the block when the invalid_blk_check=1 6903 * SOC_E_PARAM : invalid paramter 6904 */ 6905 int 6906 soc_hurricane3_pgw_reg_blk_index_get(int unit, 6907 soc_reg_t reg, soc_port_t port, 6908 pbmp_t *bm, int *block, int *index, int invalid_blk_check) { 6909 6910 int i, p, phy_port, blk_num, pgw_blk; 6911 soc_reg_info_t *reginfo; 6912 _hr3_pgw_reg_info_t *pgw_reg = NULL; 6913 pbmp_t pgw_pbm, pgw_invalid_pbm; 6914 6915 pgw_blk = -1; 6916 SOC_PBMP_CLEAR(pgw_pbm); 6917 6918 for (i = 0; _hr3_pgw_reg_info[i].pgw_reg != INVALIDr; i ++) { 6919 if (reg == _hr3_pgw_reg_info[i].pgw_reg){ 6920 pgw_reg = &_hr3_pgw_reg_info[i]; 6921 break; 6922 } 6923 } 6924 6925 if (!pgw_reg) { 6926 return SOC_E_NOT_FOUND; 6927 } 6928 6929 reginfo = &SOC_REG_INFO(unit, reg); 6930 phy_port = 0; 6931 if (reginfo->regtype == soc_portreg) { 6932 SOC_PBMP_WORD_SET(pgw_pbm, 0, pgw_reg->valid_bm); 6933 SOC_PBMP_WORD_SET(pgw_invalid_pbm, 0, pgw_reg->invalid_bm); 6934 phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 6935 } 6936 6937 if (bm != NULL) { 6938 SOC_PBMP_ITER(pgw_pbm, p) { 6939 SOC_PBMP_PORT_ADD(*bm, p); 6940 } 6941 return 1; 6942 } 6943 if (block) { 6944 if (reginfo->regtype == soc_portreg) { 6945 if( SOC_PORT_BLOCK_TYPE(unit,phy_port) == SOC_BLK_GXPORT ){ 6946 if(SOC_PBMP_MEMBER(pgw_pbm, port)) { 6947 /* get the blk from phy_port=2 bindex=1 i.e. XLPORT5*/ 6948 pgw_blk = SOC_PORT_IDX_BLOCK(unit, 2, 1); 6949 if (index) { 6950 *index = phy_port - 2; 6951 } 6952 if (!invalid_blk_check) { 6953 *block = pgw_blk; 6954 return 1; 6955 } 6956 } 6957 if(SOC_PBMP_MEMBER(pgw_invalid_pbm, port)) { 6958 *block = 0; 6959 return 1; 6960 } 6961 } 6962 } 6963 } 6964 if (invalid_blk_check){ 6965 if(!block){ 6966 return SOC_E_PARAM; 6967 } 6968 /* check if the *block is valid for the reg */ 6969 6970 if (pgw_blk == -1) { 6971 pgw_blk = *block; 6972 } 6973 blk_num = SOC_BLOCK_NUMBER(unit, pgw_blk) & 0xff; 6974 if (pgw_reg->invalid_blk_num_bm & (1 << blk_num)){ 6975 return 1; 6976 } 6977 } 6978 return SOC_E_NONE; 6979 } 6980 6981 int soc_hurricane3_pgw_rx_fifo_reset(int unit, int port, int reset) 6982 { 6983 int phy_port = SOC_INFO(unit).port_l2p_mapping[port]; 6984 uint32 rval; 6985 int block = -1; 6986 int pindex = -1; 6987 int port_num_blktype, i; 6988 6989 if (SOC_PORT_BLOCK_TYPE(unit, phy_port) != SOC_BLK_GPORT) { 6990 return SOC_E_UNAVAIL; 6991 } 6992 6993 if (!SOC_REG_IS_VALID(unit, PGW_GE_RXFIFO_SOFT_RESETr)) { 6994 return SOC_E_UNAVAIL; 6995 } 6996 6997 port_num_blktype = SOC_DRIVER(unit)->port_num_blktype > 1 ? 6998 SOC_DRIVER(unit)->port_num_blktype : 1; 6999 7000 for (i = 0; i < port_num_blktype; i++) { 7001 block = SOC_PORT_IDX_BLOCK(unit, phy_port, i); 7002 if (block < 0) { 7003 break; 7004 } 7005 7006 if (SOC_BLOCK_TYPE(unit, block) == SOC_BLK_PGW_GE) { 7007 pindex = SOC_PORT_IDX_BINDEX(unit, phy_port, i); 7008 7009 SOC_IF_ERROR_RETURN 7010 (READ_PGW_GE_RXFIFO_SOFT_RESETr(unit, port, &rval)); 7011 7012 if (reset) { 7013 rval |= 1 << pindex; 7014 } else { 7015 rval &= ~(1 << pindex); 7016 } 7017 7018 SOC_IF_ERROR_RETURN 7019 (WRITE_PGW_GE_RXFIFO_SOFT_RESETr(unit, port, rval)); 7020 7021 break; 7022 } 7023 } 7024 7025 return SOC_E_NONE; 7026 } 7027 7028 int 7029 _soc_hurricane3_features(int unit, soc_feature_t feature) { 7030 7031 uint16 dev_id; 7032 uint8 rev_id; 7033 int sku ; 7034 7035 soc_cm_get_id(unit, &dev_id, &rev_id); 7036 soc_hurricane3_chip_sku_get(unit, &sku); 7037 7038 switch (feature) { 7039 case soc_feature_arl_hashed: 7040 case soc_feature_arl_insert_ovr: 7041 case soc_feature_cfap_pool: 7042 case soc_feature_cos_rx_dma: 7043 case soc_feature_dcb_type34: 7044 case soc_feature_ingress_metering: 7045 case soc_feature_egress_metering: 7046 case soc_feature_l3_lookup_cmd: 7047 case soc_feature_led_proc: 7048 case soc_feature_led_data_offset_a0: 7049 case soc_feature_schmsg_alias: 7050 case soc_feature_stack_my_modid: 7051 case soc_feature_stat_dma: 7052 case soc_feature_cpuport_stat_dma: 7053 case soc_feature_table_dma: 7054 case soc_feature_tslam_dma: 7055 case soc_feature_stg: 7056 case soc_feature_stg_xgs: 7057 case soc_feature_remap_ut_prio: 7058 case soc_feature_xgxs_v7: 7059 case soc_feature_phy_cl45: 7060 case soc_feature_aging_extended: 7061 case soc_feature_modmap: 7062 case soc_feature_l2_hashed: 7063 case soc_feature_l2_lookup_cmd: 7064 case soc_feature_l2_lookup_retry: 7065 case soc_feature_l2_user_table: 7066 case soc_feature_schan_hw_timeout: 7067 case soc_feature_mdio_enhanced: 7068 case soc_feature_rxdma_cleanup: 7069 case soc_feature_fe_maxframe: 7070 case soc_feature_l2x_parity: 7071 case soc_feature_l3x_parity: 7072 case soc_feature_l2_modfifo: 7073 case soc_feature_parity_err_tocpu: 7074 case soc_feature_nip_l3_err_tocpu: 7075 case soc_feature_l3mtu_fail_tocpu: 7076 case soc_feature_meter_adjust: 7077 case soc_feature_xgxs_power: 7078 case soc_feature_src_modid_blk: 7079 case soc_feature_src_modid_blk_ucast_override: 7080 case soc_feature_src_modid_blk_opcode_override: 7081 case soc_feature_egress_blk_ucast_override: 7082 case soc_feature_stat_jumbo_adj: 7083 case soc_feature_stat_xgs3: 7084 case soc_feature_port_trunk_index: 7085 case soc_feature_port_flow_hash: 7086 case soc_feature_cpuport_switched: 7087 case soc_feature_cpuport_mirror: 7088 case soc_feature_higig2: 7089 case soc_feature_color: 7090 case soc_feature_color_inner_cfi: 7091 case soc_feature_color_prio_map: 7092 case soc_feature_untagged_vt_miss: 7093 case soc_feature_module_loopback: 7094 case soc_feature_dscp_map_per_port: 7095 case soc_feature_egr_dscp_map_per_port: 7096 case soc_feature_dscp_map_mode_all: 7097 case soc_feature_egr_mirror_path: 7098 case soc_feature_trunk_extended: 7099 case soc_feature_hg_trunking: 7100 case soc_feature_hg_trunk_override: 7101 case soc_feature_egr_vlan_check: 7102 case soc_feature_cpu_proto_prio: 7103 case soc_feature_hg_trunk_failover: 7104 case soc_feature_trunk_egress: 7105 case soc_feature_force_forward: 7106 case soc_feature_port_egr_block_ctl: 7107 case soc_feature_bucket_support: 7108 case soc_feature_remote_learn_trust: 7109 case soc_feature_src_mac_group: 7110 case soc_feature_storm_control: 7111 case soc_feature_hw_stats_calc: 7112 case soc_feature_mac_learn_limit: 7113 case soc_feature_linear_drr_weight: 7114 case soc_feature_igmp_mld_support: 7115 case soc_feature_basic_dos_ctrl: 7116 case soc_feature_enhanced_dos_ctrl: 7117 case soc_feature_proto_pkt_ctrl: 7118 case soc_feature_vlan_ctrl: 7119 case soc_feature_big_icmpv6_ping_check: 7120 case soc_feature_trunk_group_overlay: 7121 case soc_feature_xport_convertible: 7122 case soc_feature_dual_hash: 7123 case soc_feature_dscp: 7124 case soc_feature_rcpu_1: 7125 case soc_feature_unimac: 7126 case soc_feature_ifg_wb_include_unimac: 7127 case soc_feature_xlmac: 7128 case soc_feature_generic_table_ops: 7129 case soc_feature_static_pfm: 7130 case soc_feature_sgmii_autoneg: 7131 case soc_feature_rcpu_priority: 7132 case soc_feature_rcpu_tc_mapping: 7133 case soc_feature_mem_push_pop: 7134 case soc_feature_dcb_reason_hi: 7135 case soc_feature_multi_sbus_cmds: 7136 case soc_feature_new_sbus_format: 7137 case soc_feature_new_sbus_old_resp: 7138 case soc_feature_sbus_format_v4: 7139 case soc_feature_fifo_dma: 7140 case soc_feature_fifo_dma_active: 7141 case soc_feature_l2_pending: 7142 case soc_feature_internal_loopback: 7143 case soc_feature_packet_rate_limit: 7144 case soc_feature_system_mac_learn_limit: 7145 case soc_feature_field: 7146 case soc_feature_field_mirror_ovr: 7147 case soc_feature_field_udf_higig: 7148 case soc_feature_field_udf_ethertype: 7149 case soc_feature_field_comb_read: 7150 case soc_feature_field_wide: 7151 case soc_feature_field_slice_enable: 7152 case soc_feature_field_cos: 7153 case soc_feature_field_color_indep: 7154 case soc_feature_field_qual_drop: 7155 case soc_feature_field_qual_IpType: 7156 case soc_feature_field_qual_Ip6High: 7157 case soc_feature_field_ingress_global_meter_pools: 7158 case soc_feature_field_ingress_ipbm: 7159 case soc_feature_field_egress_flexible_v6_key: 7160 case soc_feature_field_egress_global_counters: 7161 case soc_feature_field_ing_egr_separate_packet_byte_counters: 7162 case soc_feature_field_egress_metering: 7163 case soc_feature_field_intraslice_double_wide: 7164 case soc_feature_field_virtual_slice_group: 7165 case soc_feature_field_action_timestamp: 7166 case soc_feature_field_action_l2_change: 7167 case soc_feature_field_virtual_queue: 7168 case soc_feature_field_action_redirect_nexthop: 7169 case soc_feature_field_slice_dest_entity_select: 7170 case soc_feature_field_packet_based_metering: 7171 case soc_feature_lport_tab_profile: 7172 case soc_feature_ignore_cmic_xgxs_pll_status: 7173 case soc_feature_use_double_freq_for_ddr_pll: 7174 case soc_feature_counter_parity: 7175 case soc_feature_extended_pci_error: 7176 case soc_feature_qos_profile: 7177 case soc_feature_rx_timestamp: 7178 case soc_feature_rx_timestamp_upper: 7179 case soc_feature_logical_port_num: 7180 case soc_feature_timestamp_counter: 7181 case soc_feature_generic_counters: 7182 case soc_feature_modport_map_profile: 7183 case soc_feature_modport_map_dest_is_hg_port_bitmap: 7184 case soc_feature_eee: 7185 case soc_feature_xy_tcam: 7186 case soc_feature_xy_tcam_direct: 7187 case soc_feature_xy_tcam_28nm: 7188 case soc_feature_uc: 7189 case soc_feature_cmicm: 7190 case soc_feature_iproc: 7191 case soc_feature_iproc_7: 7192 case soc_feature_iproc_ddr: 7193 case soc_feature_unified_port: 7194 case soc_feature_sbusdma: 7195 case soc_feature_mirror_encap_profile: 7196 case soc_feature_higig_misc_speed_support: 7197 case soc_feature_vpd_profile: 7198 case soc_feature_color_prio_map_profile: 7199 case soc_feature_mem_parity_eccmask: 7200 case soc_feature_discard_ability: 7201 case soc_feature_wred_drop_counter_per_port: 7202 case soc_feature_l2_no_vfi: 7203 case soc_feature_gmii_clkout: 7204 case soc_feature_field_action_pfc_class: 7205 case soc_feature_fifo_dma_hu2: 7206 case soc_feature_system_reserved_vlan: 7207 case soc_feature_ser_parity: 7208 case soc_feature_mem_cache: 7209 case soc_feature_mem_wb_cache_reload: 7210 case soc_feature_ser_engine: 7211 case soc_feature_ser_system_scrub: 7212 case soc_feature_regs_as_mem: 7213 case soc_feature_cmicd_v2: 7214 case soc_feature_cmicm_extended_interrupts: 7215 case soc_feature_int_common_init: 7216 case soc_feature_inner_tpid_enable: 7217 case soc_feature_no_tunnel: 7218 case soc_feature_ecn_wred: 7219 case soc_feature_eee_bb_mode: 7220 case soc_feature_field_oam_actions: 7221 case soc_feature_hg_no_speed_change: 7222 case soc_feature_src_modid_base_index: 7223 case soc_feature_avs: 7224 case soc_feature_l2_overflow: 7225 case soc_feature_l2_overflow_bucket: 7226 case soc_feature_l2_learn_stats: 7227 case soc_feature_custom_header: 7228 case soc_feature_ing_capwap_parser: 7229 case soc_feature_tsce: 7230 case soc_feature_field_qual_vlanformat_reverse: 7231 case soc_feature_cpureg_dump: 7232 case soc_feature_hr2_dual_hash: 7233 case soc_feature_ignore_mem_write_nak: 7234 case soc_feature_unimac_reset_wo_clock: 7235 case soc_feature_internal_phy_link_check: 7236 case soc_feature_field_udf_offset_hg_114B: 7237 case soc_feature_field_udf_offset_hg2_110B: 7238 case soc_feature_vlan_action: 7239 case soc_feature_eee_stat_clear_directly: 7240 case soc_feature_pktpri_as_dot1p: 7241 case soc_feature_cosq_hol_drop_packet_count: 7242 case soc_feature_hg2_light_in_portmacro: 7243 case soc_feature_vlan_egress_membership_l3_only: 7244 case soc_feature_memory_2bit_ecc_ser: 7245 case soc_feature_switch_match: 7246 case soc_feature_sync_port_lport_tab: 7247 case soc_feature_serdes_firmware_pos_by_host_endian: 7248 case soc_feature_dport_update_hl: 7249 return TRUE; 7250 case soc_feature_hr3_lite_lpm_shadow_hit: 7251 case soc_feature_field_action_l3_route_disabled: 7252 if (sku == SOC_HR3_SKU_HURRICANE3LITE) { 7253 /* HR3-Lite */ 7254 return TRUE; 7255 } else { 7256 return FALSE; 7257 } 7258 case soc_feature_field_multi_stage: 7259 if ((sku == SOC_HR3_SKU_HURRICANE3) || 7260 (sku == SOC_HR3_SKU_BUCKHOUND)) { 7261 /* Hurricane3, Buckhound */ 7262 return TRUE; 7263 } else { 7264 return FALSE; 7265 } 7266 case soc_feature_time_v3_no_bs: 7267 case soc_feature_field_slice_size128: 7268 if ((sku == SOC_HR3_SKU_HURRICANE3) || 7269 (sku == SOC_HR3_SKU_BUCKHOUND)) { /* Hurricane3/Buckhound */ 7270 return FALSE; 7271 } else { 7272 return TRUE; 7273 } 7274 case soc_feature_l3_no_ecmp: 7275 if (sku == SOC_HR3_SKU_HURRICANE3) { 7276 /* Hurricane3 has ECMP support */ 7277 return FALSE; 7278 } else { 7279 return TRUE; 7280 } 7281 case soc_feature_field_slices8: 7282 case soc_feature_field_meter_pools8: 7283 case soc_feature_e2ecc: 7284 case soc_feature_priority_flow_control: 7285 case soc_feature_gh_style_pfc_config: 7286 case soc_feature_time_support: 7287 case soc_feature_time_v3: 7288 case soc_feature_timesync_support: 7289 case soc_feature_timesync_v3: 7290 case soc_feature_timesync_timestampingmode: 7291 case soc_feature_flowcnt: 7292 case soc_feature_ip_subnet_based_vlan: 7293 case soc_feature_vlan_translation: 7294 case soc_feature_mac_based_vlan: 7295 case soc_feature_vlan_translation_range: 7296 case soc_feature_vlan_mc_flood_ctrl: 7297 case soc_feature_vlan_egr_it_inner_replace: 7298 case soc_feature_higig_lookup: 7299 case soc_feature_proxy_port_property: 7300 case soc_feature_oam: 7301 case soc_feature_miml: 7302 if (sku == SOC_HR3_SKU_FOXHOUND2) { /* Foxhound2 */ 7303 return FALSE; 7304 } else { 7305 return TRUE; 7306 } 7307 case soc_feature_miml_no_l3: 7308 /* 7309 * Buckhound doesn't support L3 feature but MiML reuses some L3 functions 7310 * for resource management. 7311 */ 7312 if (sku == SOC_HR3_SKU_BUCKHOUND) { /* Buckhound */ 7313 return TRUE; 7314 } else { 7315 return FALSE; 7316 } 7317 case soc_feature_field_slices4: 7318 case soc_feature_field_meter_pools4: 7319 if (sku == SOC_HR3_SKU_FOXHOUND2) { /* Foxhound2 */ 7320 return TRUE; 7321 } else { 7322 return FALSE; 7323 } 7324 case soc_feature_port_extension: 7325 case soc_feature_niv: 7326 if ((sku == SOC_HR3_SKU_HURRICANE3) || 7327 (sku == SOC_HR3_SKU_BUCKHOUND)) { /* Hurricane3/Buckhound */ 7328 return TRUE; 7329 } else { 7330 return FALSE; 7331 } 7332 case soc_feature_gphy: 7333 if (_hr3_sku_port_config[matched_devid_idx[unit]].gphy_bypass) { 7334 return FALSE; 7335 } else { 7336 return TRUE; 7337 } 7338 /* L3 feature for HR3 SKU basis supporting */ 7339 case soc_feature_l3: 7340 case soc_feature_l3_ip6: 7341 case soc_feature_l3_entry_key_type: 7342 case soc_feature_lpm_tcam: 7343 case soc_feature_ip_mcast: 7344 case soc_feature_ip_mcast_repl: 7345 case soc_feature_ipmc_unicast: 7346 case soc_feature_ipmc_use_configured_dest_mac: 7347 case soc_feature_l3mc_use_egress_next_hop: 7348 case soc_feature_l3_sgv: 7349 if ((sku == SOC_HR3_SKU_BUCKHOUND) || 7350 (sku == SOC_HR3_SKU_FOXHOUND2)) { 7351 /* Buckhound/Foxhound2 */ 7352 return FALSE; 7353 } else { 7354 return TRUE; 7355 } 7356 case soc_feature_l3_dynamic_ecmp_group: 7357 case soc_feature_urpf: 7358 case soc_feature_l3_ingress_interface: 7359 case soc_feature_l3_iif_zero_invalid: 7360 case soc_feature_l3_iif_under_4k: 7361 if (sku == SOC_HR3_SKU_HURRICANE3) { 7362 /* Hurricane3 */ 7363 return TRUE; 7364 } else { 7365 return FALSE; 7366 } 7367 case soc_feature_hr3_switch_encap_index_shift2_war: 7368 if (rev_id == BCM56160_A0_REV_ID) { 7369 /* WAR: Switch Encap index of EGR_HEADER_ENCAP_DATA is shifted << 2 bits */ 7370 return TRUE; 7371 } else { 7372 return FALSE; 7373 } 7374 case soc_feature_hr3_egphy28_phyrev_override: 7375 if ((sku == SOC_HR3_SKU_HURRICANE3) || 7376 (sku == SOC_HR3_SKU_HURRICANE3LITE) || 7377 (sku == SOC_HR3_SKU_BUCKHOUND) || 7378 (sku == SOC_HR3_SKU_FOXHOUND2)) { 7379 /* Use EGPHY_28 Hurricane3 family */ 7380 return TRUE; 7381 } else { 7382 return FALSE; 7383 } 7384 default: 7385 return FALSE; 7386 } 7387 } 7388 7389 7390 /* 7391 * Hurricane3 chip driver functions. 7392 */ 7393 soc_functions_t soc_hurricane3_drv_funs = { 7394 _soc_hurricane3_misc_init, 7395 _soc_hurricane3_mmu_init, 7396 _soc_hurricane3_age_timer_get, 7397 _soc_hurricane3_age_timer_max_get, 7398 _soc_hurricane3_age_timer_set, 7399 _soc_hurricane3_tscx_firmware_set, 7400 _soc_hurricane3_tscx_reg_read, 7401 _soc_hurricane3_tscx_reg_write, 7402 }; 7403 7404 #endif /* BCM_HURRICANE3_SUPPORT */