ser.c (68724B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: ser.c 8 * Purpose: SER enable/detect and test functionality. 9 * Requires: sal/soc/shared layer 10 */ 11 12 13 #include <shared/bsl.h> 14 #include <soc/debug.h> 15 #include <soc/iproc.h> 16 #ifdef BCM_CMICX_SUPPORT 17 #include <soc/intr_cmicx.h> 18 #endif 19 20 #ifdef BCM_HELIX5_SUPPORT 21 22 #include <soc/soc_ser_log.h> 23 #include <soc/helix5.h> 24 25 #define _SOC_MMU_BASE_INDEX_GLB 0 26 #define _SOC_MMU_BASE_INDEX_XPE 0 27 #define _SOC_MMU_BASE_INDEX_SC 0 28 #define _SOC_MMU_BASE_INDEX_SED 0 29 30 #define _SOC_HX5_IPIPE0_CEV_INTR 0x00000001 31 #define _SOC_HX5_IPIPE0_IDB_INTR 0x00000040 32 #define _SOC_HX5_IPIPE0_IP_INTR 0x00000080 33 #define _SOC_HX5_IPIPE0_ISW4_INTR 0x00000100 34 35 #if defined(BCM_56370_A0) 36 extern _soc_bus_ser_en_info_t _soc_bcm56370_a0_ip_bus_ser_info[]; 37 extern _soc_buffer_ser_en_info_t _soc_bcm56370_a0_ip_buffer_ser_info[]; 38 extern _soc_bus_ser_en_info_t _soc_bcm56370_a0_ep_bus_ser_info[]; 39 extern _soc_buffer_ser_en_info_t _soc_bcm56370_a0_ep_buffer_ser_info[]; 40 #endif 41 42 typedef struct _soc_hx5_ser_mmu_intr_info_s { 43 soc_reg_t int_statf; 44 int mmu_base_index; 45 int ser_info_index; 46 } _soc_hx5_ser_mmu_intr_info_t; 47 48 typedef _soc_td3_ser_info_type_t _soc_hx5_ser_info_type_t; 49 50 typedef struct _soc_hx5_ser_route_block_s { 51 uint8 cmic_reg; /* 3: intr3, 4: intr4, 5: intr5 */ 52 uint32 cmic_bit; 53 soc_block_t blocktype; 54 int pipe; 55 soc_reg_t enable_reg; 56 soc_reg_t status_reg; 57 soc_field_t enable_field; 58 void *info; 59 uint8 id; 60 } _soc_hx5_ser_route_block_t; 61 62 typedef struct _soc_hx5_tcam_wrapper_info_s { 63 soc_mem_t mem; 64 soc_reg_t enable_reg; 65 soc_field_t enable_field; 66 soc_field_t parity_field; /* used to sw inject test */ 67 } _soc_hx5_tcam_wrapper_info_t; 68 69 typedef _soc_td3_ser_reg_t _soc_hx5_ser_reg_t; 70 71 typedef _soc_td3_ser_info_t _soc_hx5_ser_info_t; 72 73 typedef struct _soc_hx5_tmp_ser_info_s { 74 soc_reg_t enable_reg; 75 soc_field_t enable_field; 76 uint32 value; 77 } _soc_hx5_tmp_ser_info_t; 78 79 typedef struct _soc_hx5_hash_table_ser_info_s { 80 soc_mem_t mem; 81 soc_field_t enable_field; 82 } _soc_hx5_hash_table_ser_info_t; 83 84 static soc_ser_functions_t _hx5_ser_functions; 85 86 static soc_field_t _soc_hx5_mmu_xpe_enable_fields[] = { 87 AGING_PARITY_ENf, 88 TCB_PARITY_ENf, 89 THDM_PARITY_ENf, 90 ENQX_PARITY_ENf, 91 EPRG_PARITY_ENf, 92 RQE_PARITY_ENf, 93 THDI_PARITY_ENf, 94 THDU_PARITY_ENf, 95 PQE_PARITY_ENf, 96 WRED_PARITY_ENf, 97 DQX_PARITY_ENf, 98 CCP_PARITY_ENf, 99 CTR_PARITY_ENf, 100 INVALIDf 101 }; 102 103 static soc_field_t _soc_hx5_mmu_sc_enable_fields[] = { 104 TDM_PARITY_ENf, 105 VBS_PARITY_ENf, 106 TOQ_PARITY_ENf, 107 INVALIDf 108 }; 109 110 static soc_field_t _soc_hx5_mmu_sed_enable_fields[] = { 111 MB0_PARITY_ENf, 112 /*MB1_PARITY_ENf,*/ 113 ENQS_PARITY_ENf, 114 MTRO_PARITY_ENf, 115 DQS_PARITY_ENf, 116 CFAP_PARITY_ENf, 117 INVALIDf 118 }; 119 120 static _soc_hx5_ser_info_t _soc_hx5_mmu_ser_info[] = { 121 { _SOC_TD3_PARITY_TYPE_MMU_GLB, NULL, 0, 122 INVALIDf, INVALIDf, 123 INVALIDm, "MMU GLB MEM PAR", 124 MMU_GCFG_PARITY_ENr, INTFO_PARITY_ENf, NULL, 125 MMU_GCFG_GLB_CPU_INT_ENr, MEM_PAR_ERR_ENf, NULL, 126 MMU_GCFG_GLB_CPU_INT_STATr, NULL, MEM_PAR_ERR_STATf, NULL, 127 MMU_GCFG_GLB_CPU_INT_CLEARr, MEM_PAR_ERR_CLRf, NULL 128 }, 129 { _SOC_TD3_PARITY_TYPE_MMU_XPE, NULL, 0, 130 INVALIDf, INVALIDf, 131 INVALIDm, "MMU XPE MEM PAR", 132 MMU_XCFG_PARITY_ENr, INVALIDf, _soc_hx5_mmu_xpe_enable_fields, 133 MMU_XCFG_XPE_CPU_INT_ENr, MEM_PAR_ERR_ENf, NULL, 134 MMU_XCFG_XPE_CPU_INT_STATr, NULL, MEM_PAR_ERR_STATf, NULL, 135 MMU_XCFG_XPE_CPU_INT_CLEARr, MEM_PAR_ERR_CLRf, NULL 136 }, 137 { _SOC_TD3_PARITY_TYPE_MMU_SC, NULL, 0, 138 INVALIDf, INVALIDf, 139 INVALIDm, "MMU SC MEM PAR", 140 MMU_SCFG_PARITY_ENr, INVALIDf, _soc_hx5_mmu_sc_enable_fields, 141 MMU_SCFG_SC_CPU_INT_ENr, MEM_PAR_ERR_ENf, NULL, 142 MMU_SCFG_SC_CPU_INT_STATr, NULL, MEM_PAR_ERR_STATf, NULL, 143 MMU_SCFG_SC_CPU_INT_CLEARr, MEM_PAR_ERR_CLRf, NULL 144 }, 145 { _SOC_TD3_PARITY_TYPE_MMU_SED, NULL, 0, 146 INVALIDf, INVALIDf, 147 INVALIDm, "MMU SED MEM PAR", 148 MMU_SEDCFG_PARITY_ENr, INVALIDf, _soc_hx5_mmu_sed_enable_fields, 149 MMU_SEDCFG_SED_CPU_INT_ENr, MEM_PAR_ERR_ENf, NULL, 150 MMU_SEDCFG_SED_CPU_INT_STATr, NULL, MEM_PAR_ERR_STATf, NULL, 151 MMU_SEDCFG_SED_CPU_INT_CLEARr, MEM_PAR_ERR_CLRf, NULL 152 }, 153 { _SOC_TD3_PARITY_TYPE_NONE } /* table terminator */ 154 }; 155 156 static soc_field_t _soc_hx5_mmu_top_int_enable_fields[] = { 157 SED_CPU_INT_ENf, 158 SC_CPU_INT_ENf, 159 XPE_CPU_INT_ENf, 160 GLB_CPU_INT_ENf, 161 INVALIDf 162 }; 163 164 static soc_field_t _soc_hx5_mmu_top_int_status_fields[] = { 165 SED_CPU_INT_STATf, 166 SC_CPU_INT_STATf, 167 XPE_CPU_INT_STATf, 168 GLB_CPU_INT_STATf, 169 INVALIDf 170 }; 171 172 static _soc_hx5_ser_info_t _soc_hx5_mmu_top_ser_info[] = { 173 { _SOC_TD3_PARITY_TYPE_MMU_SER, _soc_hx5_mmu_ser_info, 0, 174 INVALIDf, INVALIDf, 175 INVALIDm, "MMU MEM PAR", 176 INVALIDr, INVALIDf, NULL, 177 MMU_GCFG_ALL_CPU_INT_ENr, INVALIDf, 178 _soc_hx5_mmu_top_int_enable_fields, 179 MMU_GCFG_ALL_CPU_INT_STATr, 180 NULL, INVALIDf, _soc_hx5_mmu_top_int_status_fields, 181 INVALIDr, INVALIDf, NULL 182 }, 183 { _SOC_TD3_PARITY_TYPE_NONE } /* table terminator */ 184 }; 185 186 static _soc_hx5_ser_reg_t _soc_hx5_pm_clp_rx_status_reg[] = { 187 { CLPORT_MIB_RSC0_ECC_STATUSr, "CLP MIB RSC0 ECC" }, 188 { CLPORT_MIB_RSC1_ECC_STATUSr, "CLP MIB RSC1 ECC" }, 189 { INVALIDr, "INVALIDr"} 190 }; 191 192 static _soc_hx5_ser_reg_t _soc_hx5_pm_clp_tx_status_reg[] = { 193 { CLPORT_MIB_TSC0_ECC_STATUSr, "CLP MIB TSC0 ECC" }, 194 { CLPORT_MIB_TSC1_ECC_STATUSr, "CLP MIB TSC1 ECC" }, 195 { INVALIDr, "INVALIDr"} 196 }; 197 198 static _soc_hx5_ser_reg_t _soc_hx5_pm_xlp_rx_status_reg[] = { 199 { XLPORT_MIB_RSC0_ECC_STATUSr, "XLP MIB RSC0 ECC" }, 200 { XLPORT_MIB_RSC1_ECC_STATUSr, "XLP MIB RSC1 ECC" }, 201 { INVALIDr, "INVALIDr"} 202 }; 203 204 static _soc_hx5_ser_reg_t _soc_hx5_pm_xlp_tx_status_reg[] = { 205 { XLPORT_MIB_TSC0_ECC_STATUSr, "XLP MIB TSC0 ECC" }, 206 { XLPORT_MIB_TSC1_ECC_STATUSr, "XLP MIB TSC1 ECC" }, 207 { INVALIDr, "INVALIDr"} 208 }; 209 210 static _soc_hx5_ser_info_t _soc_hx5_pm_clp_ser_info[] = { 211 { _SOC_TD3_PARITY_TYPE_CLMAC, NULL, 0, 212 MAC_ERRf, MAC_ERRf, 213 INVALIDm, "MAC RX TimeStamp CDC memory", 214 CLMAC_INTR_ENABLEr, EN_RX_TS_MEM_SINGLE_BIT_ERRf, NULL, 215 INVALIDr, INVALIDf, NULL, 216 CLMAC_INTR_STATUSr, NULL, SUM_RX_TS_MEM_SINGLE_BIT_ERRf, NULL, 217 CLMAC_CLEAR_ECC_STATUSr, CLEAR_RX_TS_MEM_SINGLE_BIT_ERRf, NULL 218 }, 219 { _SOC_TD3_PARITY_TYPE_CLMAC, NULL, 0, 220 MAC_ERRf, MAC_ERRf, 221 INVALIDm, "MAC RX TimeStamp CDC memory", 222 CLMAC_INTR_ENABLEr, EN_RX_TS_MEM_DOUBLE_BIT_ERRf, NULL, 223 INVALIDr, INVALIDf, NULL, 224 CLMAC_INTR_STATUSr, NULL, SUM_TX_CDC_DOUBLE_BIT_ERRf, NULL, 225 CLMAC_CLEAR_ECC_STATUSr, CLEAR_RX_TS_MEM_DOUBLE_BIT_ERRf, NULL 226 }, 227 { _SOC_TD3_PARITY_TYPE_CLMAC, NULL, 0, 228 MAC_ERRf, MAC_ERRf, 229 INVALIDm, "CLMAC RX CDC single bit", 230 CLMAC_INTR_ENABLEr, EN_RX_CDC_SINGLE_BIT_ERRf, NULL, 231 INVALIDr, INVALIDf, NULL, 232 CLMAC_INTR_STATUSr, NULL, SUM_RX_CDC_SINGLE_BIT_ERRf, NULL, 233 CLMAC_CLEAR_ECC_STATUSr, CLEAR_RX_CDC_SINGLE_BIT_ERRf, NULL 234 }, 235 { _SOC_TD3_PARITY_TYPE_CLMAC, NULL, 0, 236 MAC_ERRf, MAC_ERRf, 237 INVALIDm, "CLMAC RX CDC double bits", 238 CLMAC_INTR_ENABLEr, EN_RX_CDC_DOUBLE_BIT_ERRf, NULL, 239 INVALIDr, INVALIDf, NULL, 240 CLMAC_INTR_STATUSr, NULL, SUM_RX_CDC_DOUBLE_BIT_ERRf, NULL, 241 CLMAC_CLEAR_ECC_STATUSr, CLEAR_RX_CDC_DOUBLE_BIT_ERRf, NULL 242 }, 243 { _SOC_TD3_PARITY_TYPE_CLMAC, NULL, 0, 244 MAC_ERRf, MAC_ERRf, 245 INVALIDm, "CLMAC TX CDC single bit", 246 CLMAC_INTR_ENABLEr, EN_TX_CDC_SINGLE_BIT_ERRf, NULL, 247 INVALIDr, INVALIDf, NULL, 248 CLMAC_INTR_STATUSr, NULL, SUM_TX_CDC_SINGLE_BIT_ERRf, NULL, 249 CLMAC_CLEAR_ECC_STATUSr, CLEAR_TX_CDC_SINGLE_BIT_ERRf, NULL 250 }, 251 { _SOC_TD3_PARITY_TYPE_CLMAC, NULL, 0, 252 MAC_ERRf, MAC_ERRf, 253 INVALIDm, "CLMAC TX CDC double bits", 254 CLMAC_INTR_ENABLEr, EN_TX_CDC_DOUBLE_BIT_ERRf, NULL, 255 INVALIDr, INVALIDf, NULL, 256 CLMAC_INTR_STATUSr, NULL, SUM_TX_CDC_DOUBLE_BIT_ERRf, NULL, 257 CLMAC_CLEAR_ECC_STATUSr, CLEAR_TX_CDC_DOUBLE_BIT_ERRf, NULL 258 }, 259 { _SOC_TD3_PARITY_TYPE_ECC, NULL, 0, 260 MIB_RX_MEM_ERRf, MIB_RX_MEM_ERRf, 261 INVALIDm, "MIB RX Statistic Counter memory", 262 CLPORT_ECC_CONTROLr, MIB_RSC_MEM_ENf, NULL, 263 INVALIDr, INVALIDf, NULL, 264 INVALIDr, _soc_hx5_pm_clp_rx_status_reg, INVALIDf, NULL, 265 CLPORT_INTR_STATUSr, MIB_RX_MEM_ERRf, NULL 266 }, 267 { _SOC_TD3_PARITY_TYPE_ECC, NULL, 0, 268 MIB_TX_MEM_ERRf, MIB_TX_MEM_ERRf, 269 INVALIDm, "MIB TX Statistic Counter memory", 270 CLPORT_ECC_CONTROLr, MIB_TSC_MEM_ENf, NULL, 271 INVALIDr, INVALIDf, NULL, 272 INVALIDr, _soc_hx5_pm_clp_tx_status_reg, INVALIDf, NULL, 273 CLPORT_INTR_STATUSr, MIB_TX_MEM_ERRf, NULL 274 }, 275 { _SOC_TD3_PARITY_TYPE_NONE } /* table terminator */ 276 }; 277 278 static _soc_hx5_ser_info_t _soc_hx5_pm_xlp_ser_info[] = { 279 { _SOC_TD3_PARITY_TYPE_XLMAC, NULL, 0, 280 MAC_ERRf, MAC_ERRf, 281 INVALIDm, "MAC RX CDC memory", 282 XLMAC_INTR_ENABLEr, EN_RX_CDC_SINGLE_BIT_ERRf, NULL, 283 INVALIDr, INVALIDf, NULL, 284 XLMAC_INTR_STATUSr, NULL, SUM_RX_CDC_SINGLE_BIT_ERRf, NULL, 285 XLMAC_CLEAR_ECC_STATUSr, CLEAR_RX_CDC_SINGLE_BIT_ERRf, NULL 286 }, 287 { _SOC_TD3_PARITY_TYPE_XLMAC, NULL, 0, 288 MAC_ERRf, MAC_ERRf, 289 INVALIDm, "MAC RX CDC memory", 290 XLMAC_INTR_ENABLEr, EN_RX_CDC_DOUBLE_BIT_ERRf, NULL, 291 INVALIDr, INVALIDf, NULL, 292 XLMAC_INTR_STATUSr, NULL, SUM_RX_CDC_DOUBLE_BIT_ERRf, NULL, 293 XLMAC_CLEAR_ECC_STATUSr, CLEAR_RX_CDC_DOUBLE_BIT_ERRf, NULL 294 }, 295 { _SOC_TD3_PARITY_TYPE_XLMAC, NULL, 0, 296 MAC_ERRf, MAC_ERRf, 297 INVALIDm, "MAC RX CDC memory", 298 XLMAC_INTR_ENABLEr, EN_TX_CDC_SINGLE_BIT_ERRf, NULL, 299 INVALIDr, INVALIDf, NULL, 300 XLMAC_INTR_STATUSr, NULL, SUM_TX_CDC_SINGLE_BIT_ERRf, NULL, 301 XLMAC_CLEAR_ECC_STATUSr, CLEAR_TX_CDC_SINGLE_BIT_ERRf, NULL 302 }, 303 { _SOC_TD3_PARITY_TYPE_XLMAC, NULL, 0, 304 MAC_ERRf, MAC_ERRf, 305 INVALIDm, "MAC TX CDC memory", 306 XLMAC_INTR_ENABLEr, EN_TX_CDC_DOUBLE_BIT_ERRf, NULL, 307 INVALIDr, INVALIDf, NULL, 308 XLMAC_INTR_STATUSr, NULL, SUM_TX_CDC_DOUBLE_BIT_ERRf, NULL, 309 XLMAC_CLEAR_ECC_STATUSr, CLEAR_TX_CDC_DOUBLE_BIT_ERRf, NULL 310 }, 311 { _SOC_TD3_PARITY_TYPE_ECC, NULL, 0, 312 MIB_RX_MEM_ERRf, MIB_RX_MEM_ERRf, 313 INVALIDm, "MIB RX Statistic Counter memory", 314 XLPORT_ECC_CONTROLr, MIB_RSC_MEM_ENf, NULL, 315 INVALIDr, INVALIDf, NULL, 316 INVALIDr, _soc_hx5_pm_xlp_rx_status_reg, INVALIDf, NULL, 317 XLPORT_INTR_STATUSr, MIB_RX_MEM_ERRf, NULL 318 }, 319 { _SOC_TD3_PARITY_TYPE_ECC, NULL, 0, 320 MIB_TX_MEM_ERRf, MIB_TX_MEM_ERRf, 321 INVALIDm, "MIB TX Statistic Counter memory", 322 XLPORT_ECC_CONTROLr, MIB_TSC_MEM_ENf, NULL, 323 INVALIDr, INVALIDf, NULL, 324 INVALIDr, _soc_hx5_pm_xlp_tx_status_reg, INVALIDf, NULL, 325 XLPORT_INTR_STATUSr, MIB_TX_MEM_ERRf, NULL 326 }, 327 { _SOC_TD3_PARITY_TYPE_NONE } /* table terminator */ 328 }; 329 330 static _soc_hx5_ser_reg_t _soc_hx5_idb_status_reg[] = { 331 { IDB_OBM0_Q_DATA_ECC_STATUSr, "IDB OBM0_Q packet data memory" }, 332 { IDB_OBM1_Q_DATA_ECC_STATUSr, "IDB OBM1_Q packet data memory" }, 333 { IDB_OBM2_Q_DATA_ECC_STATUSr, "IDB OBM2_Q packet data memory" }, 334 { IDB_OBM0_DATA_ECC_STATUSr, "IDB OBM0 packet data memory" }, 335 { IDB_OBM1_DATA_ECC_STATUSr, "IDB OBM1 packet data memory" }, 336 { IDB_OBM2_DATA_ECC_STATUSr, "IDB OBM2 packet data memory" }, 337 { IDB_OBM3_DATA_ECC_STATUSr, "IDB OBM3 packet data memory" }, 338 { IDB_OBM0_48_DATA_ECC_STATUSr, "IDB OBM0_48 packet data memory" }, 339 { IDB_OBM1_48_DATA_ECC_STATUSr, "IDB OBM1_48 packet data memory" }, 340 { IDB_OBM2_48_DATA_ECC_STATUSr, "IDB OBM2_48 packet data memory" }, 341 { IDB_OBM0_Q_CA_ECC_STATUSr, "IDB OBM0_Q CA packet buffer memory" }, 342 { IDB_OBM1_Q_CA_ECC_STATUSr, "IDB OBM1_Q CA packet buffer memory" }, 343 { IDB_OBM2_Q_CA_ECC_STATUSr, "IDB OBM2_Q CA packet buffer memory" }, 344 { IDB_OBM0_CA_ECC_STATUSr, "IDB OBM0 CA packet buffer memory" }, 345 { IDB_OBM1_CA_ECC_STATUSr, "IDB OBM1 CA packet buffer memory" }, 346 { IDB_OBM2_CA_ECC_STATUSr, "IDB OBM2 CA packet buffer memory" }, 347 { IDB_OBM3_CA_ECC_STATUSr, "IDB OBM3 CA packet buffer memory" }, 348 { IDB_OBM0_48_CA_ECC_STATUSr, "IDB OBM0_48 CA packet buffer memory" }, 349 { IDB_OBM1_48_CA_ECC_STATUSr, "IDB OBM1_48 CA packet buffer memory" }, 350 { IDB_OBM2_48_CA_ECC_STATUSr, "IDB OBM2_48 CA packet buffer memory" }, 351 { IDB_OBM0_Q_OVERSUB_MON_ECC_STATUSr, "IDB OBM0_Q oversub Monitoring memory" }, 352 { IDB_OBM1_Q_OVERSUB_MON_ECC_STATUSr, "IDB OBM1_Q oversub Monitoring memory" }, 353 { IDB_OBM2_Q_OVERSUB_MON_ECC_STATUSr, "IDB OBM2_Q oversub Monitoring memory" }, 354 { IDB_OBM0_OVERSUB_MON_ECC_STATUSr, "IDB OBM0 oversub Monitoring memory" }, 355 { IDB_OBM1_OVERSUB_MON_ECC_STATUSr, "IDB OBM1 oversub Monitoring memory" }, 356 { IDB_OBM2_OVERSUB_MON_ECC_STATUSr, "IDB OBM2 oversub Monitoring memory" }, 357 { IDB_OBM3_OVERSUB_MON_ECC_STATUSr, "IDB OBM3 oversub Monitoring memory" }, 358 { IDB_OBM0_48_OVERSUB_MON_ECC_STATUSr, "IDB OBM0_48 oversub Monitoring memory" }, 359 { IDB_OBM1_48_OVERSUB_MON_ECC_STATUSr, "IDB OBM1_48 oversub Monitoring memory" }, 360 { IDB_OBM2_48_OVERSUB_MON_ECC_STATUSr, "IDB OBM2_48 oversub Monitoring memory" }, 361 { IDB_CA_CPU_ECC_STATUSr, "CA-CPU packet buffer memory" }, 362 { IDB_CA_LPBK_ECC_STATUSr, "CA-LPBK packet buffer memory" }, 363 { IDB_CA_BSK_ECC_STATUSr, "CA-BSK packet buffer memory" }, 364 { IDB_CA_MGMT_ECC_STATUSr, "CA-MGMT packet buffer memory" }, 365 { IDB_SOP_EVENT_ECC_STATUSr, "IDB SOP Event Fifo ECC Status" }, 366 { IDB_EOP_EVENT_ECC_STATUSr, "IDB EOP Event Fifo ECC Status" }, 367 { INVALIDr } 368 }; 369 370 static _soc_hx5_ser_info_t _soc_hx5_idb_ser_info[] = { 371 { _SOC_TD3_PARITY_TYPE_ECC, NULL, 0, 372 MEM_ERROR_OCCURREDf, MEM_ERROR_OCCURREDf, 373 IS_TDM_CALENDAR0m, "IS_TDM CALENDAR0/1", 374 IDB_SER_CONTROLr, IS_TDM_ECC_ENf, NULL, 375 INVALIDr, INVALIDf, NULL, 376 IDB_IS_TDM_CAL_ECC_STATUSr, NULL, ECC_ERRf, NULL, 377 INVALIDr, INVALIDf, NULL 378 }, 379 { _SOC_TD3_PARITY_TYPE_ECC, NULL, 0, 380 MEM_ERROR_OCCURREDf, MEM_ERROR_OCCURREDf, 381 INVALIDm, "IP IDB memory", 382 INVALIDr, INVALIDf, NULL, 383 INVALIDr, INVALIDf, NULL, 384 INVALIDr, _soc_hx5_idb_status_reg, ECC_ERRf, NULL, 385 INVALIDr, INVALIDf, NULL 386 }, 387 { _SOC_TD3_PARITY_TYPE_NONE } /* table terminator */ 388 }; 389 390 static _soc_hx5_ser_info_t _soc_hx5_isw4_ser_info[] = { 391 { _SOC_TD3_PARITY_TYPE_ECC, NULL, 0, 392 SLOT_PIPELINE_ECC_ERRf, SLOT_PIPELINE_ECC_ERRf, 393 INVALIDm, "Slot pipeline", 394 SW4_SER_CONTROLr, SLOT_PIPELINE_ECC_ENf, NULL, 395 INVALIDr, INVALIDf, NULL, 396 SLOT_PIPELINE_ECC_STATUS_INTRr, NULL, ECC_ERRf, NULL, 397 INVALIDr, INVALIDf, NULL 398 }, 399 { _SOC_TD3_PARITY_TYPE_ECC, NULL, 0, 400 CELL_QUEUE_ECC_ERRf, CELL_QUEUE_ECC_ERRf, 401 INVALIDm, "Cell queue", 402 SW4_SER_CONTROLr, CELL_QUEUE_ECC_ENf, NULL, 403 INVALIDr, INVALIDf, NULL, 404 CELL_QUEUE_ECC_STATUS_INTRr, NULL, ECC_ERRf, NULL, 405 INVALIDr, INVALIDf, NULL 406 }, 407 { _SOC_TD3_PARITY_TYPE_ECC, NULL, 0, 408 EVENT_FIFO_ECC_ERRf, EVENT_FIFO_ECC_ERRf, 409 INVALIDm, "Event FIFO", 410 SW4_SER_CONTROLr, EVENT_FIFO_ECC_ENf, NULL, 411 INVALIDr, INVALIDf, NULL, 412 EVENT_FIFO_ECC_STATUS_INTRr, NULL, ECC_ERRf, NULL, 413 INVALIDr, INVALIDf, NULL 414 }, 415 416 { _SOC_TD3_PARITY_TYPE_NONE} /* table terminator */ 417 }; 418 419 static _soc_hx5_ser_info_t _soc_hx5_cev_ser_info[] = { 420 { _SOC_TD3_PARITY_TYPE_ECC, NULL, 0, 421 FIFO_PARITY_ERRORf, FIFO_PARITY_ERRORf, 422 CENTRAL_CTR_EVICTION_FIFOm, "CENTRAL CTR_EVICTION FIFO", 423 CENTRAL_CTR_EVICTION_FIFO_PARITY_CONTROLr, PARITY_ENf, NULL, 424 INVALIDr, INVALIDf, NULL, 425 CENTRAL_CTR_EVICTION_INTR_STATUSr, NULL, FIFO_PARITY_ERRORf, NULL, 426 INVALIDr, INVALIDf, NULL 427 }, 428 429 { _SOC_TD3_PARITY_TYPE_NONE} /* table terminator */ 430 }; 431 432 static const 433 _soc_hx5_ser_route_block_t _soc_hx5_ser_route_blocks[] = { 434 { 0, _SOC_HX5_IPIPE0_CEV_INTR, /* CEV_TO_CMIC_INTR */ 435 SOC_BLK_IPIPE, 0, CENTRAL_CTR_EVICTION_INTR_ENABLEr, 436 CENTRAL_CTR_EVICTION_INTR_STATUSr, INVALIDf, 437 _soc_hx5_cev_ser_info, 0 }, 438 { 0, 0x00000002, /* L2_MGMT_TO_CMIC_INTR */ 439 SOC_BLK_IPIPE, 0, L2_MGMT_INTR_MASKr, L2_MGMT_INTRr, SER_FIFO_NOT_EMPTYf, 440 NULL, 0 }, 441 { 0, 0x00000010, /* MMU_TO_CMIC_MEMFAIL_INTR */ 442 SOC_BLK_MMU, 0, MMU_GCFG_MISCCONFIGr, MMU_GCFG_MEM_SER_FIFO_STSr, PARITY_ENf, 443 _soc_hx5_mmu_top_ser_info, 0 }, 444 { 0, 0x00000020, /* PIPE0_EP_TO_CMIC_PERR_INTR */ 445 SOC_BLK_EPIPE, 0, EGR_INTR_ENABLEr, EGR_INTR_STATUSr, SER_FIFO_NON_EMPTYf, 446 NULL, 0 }, 447 { 0, _SOC_HX5_IPIPE0_IDB_INTR, /* PIPE0_IDB_TO_CMIC_PERR_INTR */ 448 SOC_BLK_IPIPE, 0, IP0_INTR_ENABLEr, IP0_INTR_STATUSr, INVALIDf, 449 _soc_hx5_idb_ser_info, 0 }, 450 { 0, _SOC_HX5_IPIPE0_IP_INTR, /* PIPE0_IP_TO_CMIC_PERR_INTR */ 451 SOC_BLK_IPIPE, 0, INVALIDr, INVALIDr, INVALIDf, 452 NULL, 0 }, 453 { 0, _SOC_HX5_IPIPE0_ISW4_INTR, /* PIPE0_ISW4_TO_CMIC_PERR_INTR */ 454 SOC_BLK_IPIPE, 0, ISW4_INTR_ENABLEr, ISW4_INTR_STATUSr, INVALIDf, 455 _soc_hx5_isw4_ser_info, 0 }, 456 { 1, 0x00000001, /* PM0_INTR */ 457 SOC_BLK_XLPORT, 0, XLPORT_INTR_ENABLEr, XLPORT_INTR_STATUSr, INVALIDf, 458 _soc_hx5_pm_xlp_ser_info, 0 }, 459 { 1, 0x00000002, /* PM1_INTR */ 460 SOC_BLK_XLPORT, 0, XLPORT_INTR_ENABLEr, XLPORT_INTR_STATUSr, INVALIDf, 461 _soc_hx5_pm_xlp_ser_info, 1 }, 462 { 1, 0x00000004, /* PM2_INTR */ 463 SOC_BLK_XLPORT, 0, XLPORT_INTR_ENABLEr, XLPORT_INTR_STATUSr, INVALIDf, 464 _soc_hx5_pm_xlp_ser_info, 2 }, 465 { 1, 0x00000001, /* PM0_INTR */ 466 SOC_BLK_PMQPORT, 0, INVALIDr, INVALIDr, INVALIDf, NULL, 0 }, 467 { 1, 0x00000002, /* PM1_INTR */ 468 SOC_BLK_PMQPORT, 0, INVALIDr, INVALIDr, INVALIDf, NULL, 1 }, 469 { 1, 0x00000004, /* PM2_INTR */ 470 SOC_BLK_PMQPORT, 0, INVALIDr, INVALIDr, INVALIDf, NULL, 2 }, 471 { 1, 0x00000008, /* PM3_INTR */ 472 SOC_BLK_XLPORT, 0, XLPORT_INTR_ENABLEr, XLPORT_INTR_STATUSr, INVALIDf, 473 _soc_hx5_pm_xlp_ser_info, 3 }, 474 { 1, 0x00000010, /* PM4_INTR */ 475 SOC_BLK_XLPORT, 0, XLPORT_INTR_ENABLEr, XLPORT_INTR_STATUSr, INVALIDf, 476 _soc_hx5_pm_xlp_ser_info, 4 }, 477 { 1, 0x00000020, /* PM5_INTR */ 478 SOC_BLK_XLPORT, 0, XLPORT_INTR_ENABLEr, XLPORT_INTR_STATUSr, INVALIDf, 479 _soc_hx5_pm_xlp_ser_info, 5 }, 480 { 1, 0x00000040, /* PM6_INTR */ 481 SOC_BLK_XLPORT, 0, XLPORT_INTR_ENABLEr, XLPORT_INTR_STATUSr, INVALIDf, 482 _soc_hx5_pm_xlp_ser_info, 6 }, 483 { 1, 0x00000080, /* PM7_INTR */ 484 SOC_BLK_CLPORT, 0, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 485 _soc_hx5_pm_clp_ser_info, 0 }, 486 { 1, 0x00000100, /* PM8_INTR */ 487 SOC_BLK_CLPORT, 0, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 488 _soc_hx5_pm_clp_ser_info, 1 }, 489 { 1, 0x00000200, /* PM9_INTR */ 490 SOC_BLK_CLPORT, 0, CLPORT_INTR_ENABLEr, CLPORT_INTR_STATUSr, INVALIDf, 491 _soc_hx5_pm_clp_ser_info, 2 }, 492 { 0 } /* table terminator */ 493 }; 494 495 static _soc_generic_ser_info_t _soc_hx5_tcam_ser_info[] = 496 { 497 { BSK_FTFP_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 498 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 499 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 500 501 { BSK_FTFP_LTS_LOGICAL_TBL_SEL_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 502 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 503 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 504 505 { CPU_COS_MAPm, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 506 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 507 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 508 509 /* Global view */ 510 { DST_COMPRESSIONm, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 511 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 512 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 513 514 { EFP_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 515 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 516 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 517 518 { EGR_ADAPT_1_LOGICAL_TBL_SEL_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 519 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 520 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 521 522 { EGR_ADAPT_2_LOGICAL_TBL_SEL_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 523 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 524 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 525 526 { EGR_FIELD_EXTRACTION_PROFILE_1_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 527 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 528 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 529 530 { EGR_FIELD_EXTRACTION_PROFILE_2_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 531 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 532 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 533 534 { EGR_PKT_FLOW_SELECT_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 535 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 536 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 537 538 { EGR_QOS_CTRL_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 539 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 540 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 541 542 { EGR_ZONE_0_EDITOR_CONTROL_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 543 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 544 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 545 546 { EGR_ZONE_1_EDITOR_CONTROL_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 547 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 548 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 549 550 { EGR_ZONE_2_EDITOR_CONTROL_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 551 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 552 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 553 554 { EGR_ZONE_3_EDITOR_CONTROL_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 555 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 556 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 557 558 { EGR_ZONE_4_EDITOR_CONTROL_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 559 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 560 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 561 562 { EXACT_MATCH_LOGICAL_TABLE_SELECTm, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 563 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 564 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 565 566 { FLEX_RTAG7_HASH_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 567 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 568 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 569 570 { FORWARDING_1_LOGICAL_TBL_SEL_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 571 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 572 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 573 574 { FORWARDING_2_LOGICAL_TBL_SEL_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 575 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 576 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 577 578 { FORWARDING_3_LOGICAL_TBL_SEL_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 579 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 580 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 581 582 { IFP_LOGICAL_TABLE_SELECTm, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 583 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 584 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 585 586 { IFP_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 587 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 588 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 589 590 { IFP_TCAM_WIDEm, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 591 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 592 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 593 594 { IP_MULTICAST_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 595 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 596 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 597 598 { IP_PARSER0_HME_STAGE_TCAM_ONLY_0m, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 599 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 600 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 601 602 { IP_PARSER1_HME_STAGE_TCAM_ONLY_0m, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 603 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 604 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 605 606 { IP_PARSER1_HME_STAGE_TCAM_ONLY_1m, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 607 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 608 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 609 610 { IP_PARSER1_HME_STAGE_TCAM_NARROW_ONLY_2m, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 611 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 612 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 613 614 { IP_PARSER1_HME_STAGE_TCAM_ONLY_3m, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 615 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 616 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 617 618 { IP_PARSER1_HME_STAGE_TCAM_ONLY_4m, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 619 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 620 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 621 622 { IP_PARSER1_MICE_TCAM_0m, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 623 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 624 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 625 626 { IP_PARSER1_MICE_TCAM_1m, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 627 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 628 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 629 630 { IP_PARSER2_HME_STAGE_TCAM_ONLY_0m, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 631 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 632 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 633 634 { IP_PARSER2_HME_STAGE_TCAM_ONLY_1m, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 635 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 636 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 637 638 { IP_PARSER2_HME_STAGE_TCAM_NARROW_ONLY_2m, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 639 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 640 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 641 642 { IP_PARSER2_HME_STAGE_TCAM_NARROW_ONLY_3m, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 643 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 644 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 645 646 { IP_PARSER2_HME_STAGE_TCAM_ONLY_4m, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 647 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 648 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 649 650 { IP_PARSER2_MICE_TCAM_0m, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 651 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 652 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 653 654 { IP_PARSER2_MICE_TCAM_1m, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 655 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 656 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 657 658 { L2_USER_ENTRYm, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 659 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 660 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 661 662 { L3_DEFIPm, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 663 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 664 _SOC_SER_FLAG_NO_DMA | _SOC_SER_FLAG_REMAP_READ | 665 _SOC_SER_FLAG_SIZE_VERIFY | _SOC_SER_FLAG_XY_READ}, 666 667 { L3_DEFIP_PAIR_128m, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 668 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 669 _SOC_SER_FLAG_NO_DMA | _SOC_SER_FLAG_REMAP_READ | 670 _SOC_SER_FLAG_SIZE_VERIFY | _SOC_SER_FLAG_XY_READ}, 671 672 { L3_TUNNELm, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 673 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 674 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 675 676 { MY_STATION_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 677 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 678 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 679 680 { MY_STATION_TCAM_2m, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 681 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 682 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 683 684 { PHB_SELECT_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 685 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 686 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 687 688 { PKT_FLOW_SELECT_TCAM_0m, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 689 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 690 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 691 692 { PKT_FLOW_SELECT_TCAM_1m, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 693 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 694 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 695 696 { PKT_FLOW_SELECT_TCAM_2m, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 697 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 698 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 699 700 /* Global view */ 701 { SRC_COMPRESSIONm, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 702 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 703 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 704 705 { TUNNEL_ADAPT_1_LOGICAL_TBL_SEL_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 706 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 707 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 708 709 { TUNNEL_ADAPT_2_LOGICAL_TBL_SEL_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 710 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 711 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 712 713 { TUNNEL_ADAPT_3_LOGICAL_TBL_SEL_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 714 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 715 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 716 717 { TUNNEL_ADAPT_4_LOGICAL_TBL_SEL_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 718 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 719 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 720 721 { VFP_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 722 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 723 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 724 725 { VLAN_SUBNETm, INVALIDm, _SOC_SER_TYPE_PARITY, 0, 0, 726 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, 0, 0, 0, 0, 727 _SOC_SER_FLAG_DISCARD_READ | _SOC_SER_FLAG_XY_READ}, 728 729 /* End of list */ 730 { INVALIDm }, 731 }; 732 733 STATIC soc_error_t 734 _soc_hx5_ser_tcam_wrapper_enable(int unit, int enable) 735 { 736 return soc_td3_ser_tcam_wrapper_enable(unit, enable); 737 } 738 739 STATIC int 740 _soc_hx5_ser_enable_info(int unit, int block_info_idx, int inst, int port, 741 soc_reg_t group_reg, uint64 *group_rval, 742 _soc_hx5_ser_info_t *info_list, 743 soc_mem_t mem, int enable) 744 { 745 return soc_td3_ser_enable_info(unit, block_info_idx, inst, port, 746 group_reg, group_rval, 747 info_list, mem, enable); 748 } 749 750 STATIC int 751 _soc_hx5_ser_block_enable(int unit, int enable, int type, 752 soc_reg_t fifo_reset_reg, void *info) 753 { 754 uint16 pcount; 755 soc_reg_t reg, ecc1b_reg; 756 soc_field_t field, ecc1b_field; 757 soc_mem_t en_mem; 758 soc_mem_t ecc1b_en_mem; 759 int field_position = -1; 760 int ecc1b_field_position = -1; 761 uint8 flag = 0; 762 uint8 ecc1b_flag = 0; 763 _soc_reg_ser_en_info_t *reg_info; 764 _soc_mem_ser_en_info_t *mem_info; 765 _soc_bus_ser_en_info_t *bus_info; 766 _soc_buffer_ser_en_info_t *buf_info; 767 char *str_type; 768 char *str_name; 769 static char *parity_module_str[4] = {"REG", "MEM", "BUS", "BUF"}; 770 int done = 0; 771 772 reg_info = (_soc_reg_ser_en_info_t*)info; 773 mem_info = (_soc_mem_ser_en_info_t*)info; 774 bus_info = (_soc_bus_ser_en_info_t*)info; 775 buf_info = (_soc_buffer_ser_en_info_t*)info; 776 for (pcount = 0;;pcount++) { /* walk thro each entry of block_info */ 777 reg = INVALIDr; 778 ecc1b_reg = INVALIDr; 779 ecc1b_en_mem = INVALIDm; 780 en_mem = INVALIDm; 781 field = INVALIDf; 782 ecc1b_field = INVALIDf; 783 switch (type) { 784 case _SOC_SER_TYPE_REG: 785 if (reg_info[pcount].reg == INVALIDr) { 786 done = 1; 787 } else { 788 reg = reg_info[pcount].en_ctrl.ctrl_type.en_reg; 789 en_mem = reg_info[pcount].en_ctrl.ctrl_type.en_mem; 790 flag = reg_info[pcount].en_ctrl.flag_reg_mem; 791 field = reg_info[pcount].en_ctrl.en_fld; 792 field_position = reg_info[pcount].en_ctrl.en_fld_position; 793 ecc1b_reg = reg_info[pcount].ecc1b_ctrl.ctrl_type.en_reg; 794 ecc1b_en_mem = reg_info[pcount].ecc1b_ctrl.ctrl_type.en_mem; 795 ecc1b_flag = reg_info[pcount].ecc1b_ctrl.flag_reg_mem; 796 ecc1b_field = reg_info[pcount].ecc1b_ctrl.en_fld; 797 ecc1b_field_position = reg_info[pcount].ecc1b_ctrl.en_fld_position; 798 str_name = SOC_REG_NAME(unit, reg_info[pcount].reg); 799 } 800 break; 801 case _SOC_SER_TYPE_MEM: 802 if (mem_info[pcount].mem == INVALIDm) { 803 done = 1; 804 } else if (!SOC_MEM_IS_VALID(unit, mem_info[pcount].mem) || 805 (SOC_MEM_INFO(unit, mem_info[pcount].mem).flags & 806 SOC_MEM_FLAG_SER_PARITY_ENABLE_SKIP)) { 807 LOG_VERBOSE(BSL_LS_SOC_SER, (BSL_META_U(unit, 808 "skip SER enable for mem %s\n"), 809 SOC_MEM_NAME(unit, mem_info[pcount].mem))); 810 continue; 811 } else { 812 reg = mem_info[pcount].en_ctrl.ctrl_type.en_reg; 813 en_mem = mem_info[pcount].en_ctrl.ctrl_type.en_mem; 814 flag = mem_info[pcount].en_ctrl.flag_reg_mem; 815 field = mem_info[pcount].en_ctrl.en_fld; 816 field_position = mem_info[pcount].en_ctrl.en_fld_position; 817 ecc1b_reg = mem_info[pcount].ecc1b_ctrl.ctrl_type.en_reg; 818 ecc1b_en_mem = mem_info[pcount].ecc1b_ctrl.ctrl_type.en_mem; 819 ecc1b_flag = mem_info[pcount].ecc1b_ctrl.flag_reg_mem; 820 ecc1b_field = mem_info[pcount].ecc1b_ctrl.en_fld; 821 ecc1b_field_position = mem_info[pcount].ecc1b_ctrl.en_fld_position; 822 str_name = SOC_MEM_NAME(unit, mem_info[pcount].mem); 823 } 824 break; 825 case _SOC_SER_TYPE_BUS: 826 if (bus_info[pcount].en_reg == INVALIDr) { 827 done = 1; 828 } else { 829 reg = bus_info[pcount].en_reg; 830 field = bus_info[pcount].en_fld; 831 ecc1b_reg = bus_info[pcount].ecc1b_en_reg; 832 ecc1b_field = bus_info[pcount].ecc1b_en_fld; 833 ecc1b_flag = 0; 834 str_name = bus_info[pcount].bus_name; 835 flag = 0; 836 } 837 break; 838 case _SOC_SER_TYPE_BUF: 839 if (buf_info[pcount].en_reg == INVALIDr) { 840 done = 1; 841 } else { 842 reg = buf_info[pcount].en_reg; 843 field = buf_info[pcount].en_fld; 844 ecc1b_reg = buf_info[pcount].ecc1b_en_reg; 845 ecc1b_field = buf_info[pcount].ecc1b_en_fld; 846 ecc1b_flag = 0; 847 str_name = buf_info[pcount].buffer_name; 848 flag = 0; 849 } 850 break; 851 default: 852 LOG_CLI((BSL_META_U(unit, 853 "Unknown parity module " 854 "[pcount: %d].\n"), pcount)); 855 return SOC_E_INTERNAL; 856 } 857 if (done) { 858 break; 859 } else { 860 str_type = parity_module_str[type]; 861 } 862 863 en_mem = flag ? en_mem : INVALIDm; 864 reg = flag ? INVALIDr : reg; 865 ecc1b_en_mem = ecc1b_flag ? ecc1b_en_mem : INVALIDm; 866 ecc1b_reg = ecc1b_flag ? INVALIDr : ecc1b_reg; 867 868 SOC_IF_ERROR_RETURN(soc_td3_parity_bit_enable 869 (unit, reg, en_mem, field, field_position, enable)); 870 871 if (ecc1b_reg == ISW3_SER_CONTROL_1r && 872 ecc1b_field == HG_COUNTERS_EN_COR_ERR_RPTf) { 873 continue; 874 } 875 876 SOC_IF_ERROR_RETURN(soc_td3_parity_bit_enable 877 (unit, ecc1b_reg, ecc1b_en_mem, ecc1b_field, ecc1b_field_position, enable)); 878 879 LOG_VERBOSE(BSL_LS_SOC_SER, 880 (BSL_META_U(unit, 881 "SER enable for %s: %s\n"), 882 str_type, str_name)); 883 } /* walk through each entry of ser_info structures */ 884 885 /* reset (toggle) fifo if applicable */ 886 if (fifo_reset_reg != INVALIDr) { 887 SOC_IF_ERROR_RETURN 888 (soc_reg_field32_modify(unit, fifo_reset_reg, 889 REG_PORT_ANY, FIFO_RESETf, 1)); 890 SOC_IF_ERROR_RETURN 891 (soc_reg_field32_modify(unit, fifo_reset_reg, 892 REG_PORT_ANY, FIFO_RESETf, 0)); 893 } 894 895 return SOC_E_NONE; 896 } 897 898 int 899 soc_hx5_ser_enable_all(int unit, int enable) 900 { 901 uint8 rbi; 902 uint32 cmic_bit; 903 uint32 cmic_rval0; 904 uint32 cmic_rval1; 905 int port; 906 int rv, block_info_idx; 907 uint64 rval64; 908 const _soc_hx5_ser_route_block_t *rb; 909 910 soc_iproc_getreg(unit,soc_reg_addr(unit, ICFG_CHIP_LP_INTR_ENABLE_REG0r, REG_PORT_ANY, 0), 911 &cmic_rval0); 912 soc_iproc_getreg(unit,soc_reg_addr(unit, ICFG_CHIP_LP_INTR_ENABLE_REG1r, REG_PORT_ANY, 0), 913 &cmic_rval1); 914 915 soc_td3_ip_pipe_fifo_bmask[unit][0] = _SOC_HX5_IPIPE0_IP_INTR; 916 917 SOC_IF_ERROR_RETURN(_soc_hx5_ser_block_enable(unit, enable, 918 _SOC_SER_TYPE_MEM, ING_SER_FIFO_CTRLr, 919 (void*) SOC_IP_MEM_SER_INFO(unit))); 920 921 SOC_IF_ERROR_RETURN(_soc_hx5_ser_block_enable(unit, enable, 922 _SOC_SER_TYPE_MEM, EGR_SER_FIFO_CTRLr, 923 (void*) SOC_EP_MEM_SER_INFO(unit))); 924 925 SOC_IF_ERROR_RETURN(_soc_hx5_ser_block_enable(unit, enable, 926 _SOC_SER_TYPE_MEM, INVALIDr, 927 (void*) SOC_MMU_MEM_SER_INFO(unit))); 928 929 SOC_IF_ERROR_RETURN(_soc_hx5_ser_block_enable(unit, enable, 930 _SOC_SER_TYPE_REG, L2_MGMT_SER_FIFO_CTRLr, 931 (void*) SOC_IP_REG_SER_INFO(unit))); 932 933 SOC_IF_ERROR_RETURN(_soc_hx5_ser_block_enable(unit, enable, 934 _SOC_SER_TYPE_REG, INVALIDr, 935 (void*) SOC_EP_REG_SER_INFO(unit))); 936 937 #if defined(BCM_56370_A0) 938 SOC_IF_ERROR_RETURN(_soc_hx5_ser_block_enable(unit, enable, 939 _SOC_SER_TYPE_BUS, INVALIDr, 940 (void*) &_soc_bcm56370_a0_ip_bus_ser_info)); 941 942 SOC_IF_ERROR_RETURN(_soc_hx5_ser_block_enable(unit, enable, 943 _SOC_SER_TYPE_BUS, INVALIDr, 944 (void*) &_soc_bcm56370_a0_ep_bus_ser_info)); 945 946 SOC_IF_ERROR_RETURN(_soc_hx5_ser_block_enable(unit, enable, 947 _SOC_SER_TYPE_BUF, INVALIDr, 948 (void*) &_soc_bcm56370_a0_ip_buffer_ser_info)); 949 950 SOC_IF_ERROR_RETURN(_soc_hx5_ser_block_enable(unit, enable, 951 _SOC_SER_TYPE_BUF, INVALIDr, 952 (void*) &_soc_bcm56370_a0_ep_buffer_ser_info)); 953 #endif 954 955 /* Loop through each place-and-route block entry to enable legacy 956 style SER stuff */ 957 for (rbi = 0; ; rbi++) { 958 rb = &_soc_hx5_ser_route_blocks[rbi]; 959 cmic_bit = rb->cmic_bit; 960 port = REG_PORT_ANY; 961 if (cmic_bit == 0) { 962 /* End of table */ 963 break; 964 } 965 966 switch (rb->cmic_reg) { 967 case 0: cmic_rval0 &= ~cmic_bit; break; 968 case 1: cmic_rval1 &= ~cmic_bit; break; 969 default: break; 970 } 971 972 SOC_BLOCK_ITER(unit, block_info_idx, rb->blocktype) { 973 if (SOC_BLOCK_INFO(unit, block_info_idx).number == rb->id) { 974 port = SOC_BLOCK_PORT(unit, block_info_idx); 975 break; 976 } 977 } 978 979 if (rb->enable_reg != INVALIDr) { 980 if (SOC_BLOCK_IN_LIST(SOC_REG_INFO(unit, rb->enable_reg).block, 981 SOC_BLK_PORT)) { 982 if (port == REG_PORT_ANY) { 983 /* This port block is not configured */ 984 continue; 985 } 986 if (IS_QSGMII_PORT(unit, port) && 987 (rb->blocktype == SOC_BLK_XLPORT)) { 988 continue; 989 } 990 } 991 } 992 993 if (enable) { 994 switch (rb->cmic_reg) { 995 case 0: cmic_rval0 |= cmic_bit; break; 996 case 1: cmic_rval1 |= cmic_bit; break; 997 default: break; 998 } 999 } 1000 1001 if (rb->enable_field != INVALIDf) { 1002 SOC_IF_ERROR_RETURN(soc_reg_field32_modify 1003 (unit, rb->enable_reg, port, rb->enable_field, enable)); 1004 } 1005 1006 if (rb->info != NULL) { 1007 SOC_IF_ERROR_RETURN(soc_reg_get(unit, rb->enable_reg, 1008 port, 0, &rval64)); 1009 rv = _soc_hx5_ser_enable_info(unit, block_info_idx, rb->id, port, 1010 rb->enable_reg, &rval64, 1011 rb->info, INVALIDm, enable); 1012 if (rv == SOC_E_NOT_FOUND) { 1013 continue; 1014 } else if (SOC_FAILURE(rv)) { 1015 return rv; 1016 } 1017 SOC_IF_ERROR_RETURN(soc_reg_set(unit, rb->enable_reg, 1018 port, 0, rval64)); 1019 } 1020 } 1021 1022 soc_iproc_setreg(unit, 1023 soc_reg_addr(unit, ICFG_CHIP_LP_INTR_ENABLE_REG0r, REG_PORT_ANY, 0), 1024 cmic_rval0); 1025 soc_iproc_setreg(unit, 1026 soc_reg_addr(unit, ICFG_CHIP_LP_INTR_ENABLE_REG1r, REG_PORT_ANY, 0), 1027 cmic_rval1); 1028 if (enable) { 1029 /* Write CMIC enable register */ 1030 soc_cmic_intr_enable(unit, CHIP_INTR_LOW_PRIORITY); 1031 (void)soc_ser_tcam_scan_engine_enable(unit, FALSE); 1032 (void)_soc_hx5_ser_tcam_wrapper_enable(unit, TRUE); 1033 } else { 1034 /* Write CMIC disable register */ 1035 soc_cmic_intr_disable(unit, CHIP_INTR_LOW_PRIORITY); 1036 (void)soc_ser_tcam_scan_engine_enable(unit, FALSE); 1037 (void)_soc_hx5_ser_tcam_wrapper_enable(unit, FALSE); 1038 } 1039 return SOC_E_NONE; 1040 } 1041 1042 STATIC int 1043 _soc_hx5_ser_process_pmqport(int unit, int blocktype, int inst) 1044 { 1045 uint32 rval; 1046 soc_stat_t *stat = SOC_STAT(unit); 1047 1048 SOC_IF_ERROR_RETURN(READ_PMQ_ECCr(unit, inst, &rval)); 1049 /* ECC_ERROR_EVENT is clear on read */ 1050 if (soc_reg_field_get(unit, PMQ_ECCr, rval, ECC_ERROR_EVENTf)) { 1051 SOC_IF_ERROR_RETURN(READ_PMQ_GP_ECCERR_STSr(unit, inst, &rval)); 1052 if (rval != 0) { 1053 LOG_ERROR(BSL_LS_SOC_SER, 1054 (BSL_META_U(unit, 1055 "ECC error on GPORT memory. Instance %d \n"), 1056 inst)); 1057 soc_ser_stat_update(unit, 0, blocktype, SOC_PARITY_TYPE_ECC, 1058 0, SocSerCorrectTypeNoAction, stat); 1059 } 1060 SOC_IF_ERROR_RETURN(READ_PMQ_UMAC_ECCERR_STSr(unit, inst, &rval)); 1061 if (rval != 0) { 1062 LOG_ERROR(BSL_LS_SOC_SER, 1063 (BSL_META_U(unit, 1064 "ECC error on UNIMAC memory. Instance %d \n"), 1065 inst)); 1066 soc_ser_stat_update(unit, 0, blocktype, SOC_PARITY_TYPE_ECC, 1067 0, SocSerCorrectTypeNoAction, stat); 1068 } 1069 } else { 1070 LOG_VERBOSE(BSL_LS_SOC_SER, 1071 (BSL_META_U(unit, 1072 "Hardware inconsistency. Instance: %d\n"), 1073 inst)); 1074 } 1075 return SOC_E_NONE; 1076 } 1077 1078 STATIC int 1079 _soc_hx5_ser_process(int unit, int block_info_idx, int inst, int pipe, 1080 int port, soc_reg_t group_reg, uint64 group_rval, 1081 const _soc_hx5_ser_info_t *info_list, 1082 soc_block_t blocktype, 1083 char *prefix_str) 1084 { 1085 if (blocktype == SOC_BLK_PMQPORT) { 1086 return _soc_hx5_ser_process_pmqport(unit, blocktype, inst); 1087 } else { 1088 return soc_td3_ser_process(unit, block_info_idx, inst, pipe, 1089 port, group_reg, group_rval, 1090 info_list, blocktype, prefix_str); 1091 } 1092 } 1093 1094 STATIC int 1095 soc_hx5_ser_process_fifo(int unit, soc_block_t blk, int pipe, 1096 char *prefix_str, int l2_mgmt_ser_fifo) 1097 { 1098 return soc_trident3_process_ser_fifo(unit, blk, pipe, 1099 prefix_str, l2_mgmt_ser_fifo); 1100 } 1101 1102 1103 STATIC int 1104 _soc_hx5_ser_process_all(int unit, int reg_type, int bit) 1105 { 1106 uint8 rbi; 1107 int port; 1108 uint32 cmic_bit; 1109 uint64 rb_rval64; 1110 const _soc_hx5_ser_route_block_t *rb; 1111 char prefix_str[10]; 1112 int block_info_idx; 1113 soc_reg_t tmp_reg; 1114 int processed_an_intr = 0; 1115 soc_stat_t *stat = SOC_STAT(unit); 1116 COMPILER_64_ZERO(rb_rval64); 1117 1118 sal_sprintf(prefix_str, "\nUnit: %d ", unit); 1119 1120 LOG_VERBOSE(BSL_LS_SOC_SER, 1121 (BSL_META_U(unit, 1122 "unit %d, _soc_hx5_ser_process_all called: reg_type %d, bit %d \n"), 1123 unit, reg_type, bit)); 1124 1125 /* Loop through each place-and-route block entry */ 1126 for (rbi = 0; ; rbi++) { 1127 port = REG_PORT_ANY; 1128 rb = &_soc_hx5_ser_route_blocks[rbi]; 1129 cmic_bit = rb->cmic_bit; 1130 if (cmic_bit == 0) { 1131 /* End of table */ 1132 break; 1133 } 1134 if (!((rb->cmic_reg == reg_type) && (cmic_bit == 1 << bit))) { 1135 continue; 1136 } 1137 if ((rb->blocktype == SOC_BLK_IPIPE || rb->blocktype == SOC_BLK_EPIPE) 1138 && (rb->cmic_bit != _SOC_HX5_IPIPE0_CEV_INTR) 1139 && (rb->cmic_bit != _SOC_HX5_IPIPE0_IDB_INTR) 1140 && (rb->cmic_bit != _SOC_HX5_IPIPE0_ISW4_INTR)) { 1141 /* New fifo style processing */ 1142 (void)soc_hx5_ser_process_fifo(unit, rb->blocktype, rb->pipe, 1143 prefix_str, 0); 1144 stat->ser_err_fifo++; 1145 processed_an_intr = 1; 1146 } else { 1147 /* Legacy processing */ 1148 SOC_BLOCK_ITER(unit, block_info_idx, rb->blocktype) { 1149 if (SOC_BLOCK_INFO(unit, block_info_idx).number == rb->id) { 1150 port = SOC_BLOCK_PORT(unit, block_info_idx); 1151 break; 1152 } 1153 } 1154 if (rb->enable_reg != INVALIDr) { 1155 if (SOC_BLOCK_IN_LIST(SOC_REG_INFO(unit, rb->enable_reg).block, 1156 SOC_BLK_PORT)) { 1157 if (port == REG_PORT_ANY) { 1158 /* This port block is not configured */ 1159 LOG_ERROR(BSL_LS_SOC_SER, 1160 (BSL_META_U(unit, 1161 "unit %d SER error on disabled " 1162 "port block %d !!\n"), 1163 unit, block_info_idx)); 1164 continue; 1165 } 1166 if (IS_QSGMII_PORT(unit, port) && 1167 (rb->blocktype == SOC_BLK_XLPORT)) { 1168 continue; 1169 } 1170 } 1171 } 1172 /* Read per route block parity status register */ 1173 if ((rb->status_reg != INVALIDr) && 1174 (rb->blocktype != SOC_BLK_MMU)){ 1175 /* Top level MMU register used to enable parity is also used 1176 * to control various other functions in MMU. 1177 * So we don't read/modify enable_reg and status_reg for MMU 1178 * It is handled in _soc_trident3_ser_process_mmu_err() 1179 */ 1180 if ((rb->blocktype == SOC_BLK_IPIPE || 1181 rb->blocktype == SOC_BLK_EPIPE) && 1182 (SOC_REG_UNIQUE_ACC(unit, rb->status_reg) != NULL)) { 1183 tmp_reg = SOC_REG_UNIQUE_ACC(unit, 1184 rb->status_reg)[rb->pipe]; 1185 } else { 1186 tmp_reg = rb->status_reg; 1187 } 1188 SOC_IF_ERROR_RETURN 1189 (soc_reg_get(unit, tmp_reg, port, 0, &rb_rval64)); 1190 1191 if (COMPILER_64_IS_ZERO(rb_rval64)) { 1192 continue; 1193 } 1194 } 1195 processed_an_intr = 1; 1196 SOC_IF_ERROR_RETURN 1197 (_soc_hx5_ser_process(unit, block_info_idx, rb->id, 1198 rb->pipe, port, rb->status_reg, 1199 rb_rval64, rb->info, rb->blocktype, 1200 prefix_str)); 1201 1202 stat->ser_err_int++; 1203 } /* legacy processing */ 1204 } 1205 if (!processed_an_intr) { 1206 LOG_WARN(BSL_LS_SOC_SER, 1207 (BSL_META_U(unit, 1208 "unit %d, reg_type %d, bit %d " 1209 "could not process interrupt !!\n"), 1210 unit, reg_type, bit)); 1211 return SOC_E_INTERNAL; 1212 } 1213 return SOC_E_NONE; 1214 } 1215 1216 void 1217 soc_hx5_ser_error(void *unit_vp, void *d1, void *d2, void *d3, 1218 void *d4) 1219 { 1220 int unit = PTR_TO_INT(unit_vp); 1221 int rv; 1222 1223 rv = _soc_hx5_ser_process_all(unit, PTR_TO_INT(d3), PTR_TO_INT(d4)); 1224 sal_usleep(SAL_BOOT_QUICKTURN ? 1000000 : 10000); 1225 1226 if (SOC_SUCCESS(rv)) { 1227 /* Interrupts not processed properly should not be enabled */ 1228 soc_ser_top_intr_reg_enable(unit, PTR_TO_INT(d3), PTR_TO_INT(d4), 1); 1229 } 1230 soc_cmic_intr_enable(unit, CHIP_INTR_LOW_PRIORITY); 1231 } 1232 1233 int 1234 soc_hx5_mem_ser_control(int unit, soc_mem_t mem, int copyno, int enable) 1235 { 1236 if (enable) { 1237 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, TOP_SOFT_RESET_REGr, 1238 REG_PORT_ANY, TOP_MMU_RST_Lf, 0)); 1239 sal_usleep(1000); 1240 SOC_IF_ERROR_RETURN(soc_reg_field32_modify(unit, TOP_SOFT_RESET_REGr, 1241 REG_PORT_ANY, TOP_MMU_RST_Lf, 1)); 1242 sal_usleep(1000); 1243 SOC_IF_ERROR_RETURN(soc_trident3_clear_mmu_memory(unit)); 1244 } 1245 1246 if (enable) { 1247 if (soc_property_get(unit, spn_PARITY_ENABLE, TRUE)) { 1248 SOC_IF_ERROR_RETURN(soc_hx5_ser_enable_all(unit, TRUE)); 1249 } 1250 } else { 1251 SOC_IF_ERROR_RETURN(soc_hx5_ser_enable_all(unit, FALSE)); 1252 } 1253 1254 if (enable) { 1255 uint32 rval; 1256 /* Initialize MMU memory */ 1257 SOC_IF_ERROR_RETURN(WRITE_MMU_GCFG_MISCCONFIGr(unit, 0)); 1258 rval = 0; 1259 soc_reg_field_set(unit, MMU_GCFG_MISCCONFIGr, &rval, INIT_MEMf, 1); 1260 SOC_IF_ERROR_RETURN(WRITE_MMU_GCFG_MISCCONFIGr(unit, rval)); 1261 SOC_IF_ERROR_RETURN(WRITE_MMU_GCFG_MISCCONFIGr(unit, 0)); 1262 } 1263 return SOC_E_NONE; 1264 } 1265 1266 void 1267 soc_hx5_ser_register(int unit) 1268 { 1269 soc_cmic_intr_handler_t handle; 1270 1271 #ifdef INCLUDE_MEM_SCAN 1272 if (!soc_feature(unit, soc_feature_tcam_scan_engine)) { 1273 /* To access Narrow view for HME stage TCAMs */ 1274 (void)WRITE_IP_PARSER1_HME_STAGE_CONFIG_2r(unit, 0); 1275 (void)WRITE_IP_PARSER2_HME_STAGE_CONFIG_2r(unit, 0); 1276 (void)WRITE_IP_PARSER2_HME_STAGE_CONFIG_3r(unit, 0); 1277 soc_mem_scan_ser_list_register(unit, TRUE, _soc_hx5_tcam_ser_info); 1278 } 1279 #endif 1280 1281 memset(&_hx5_ser_functions, 0, sizeof(soc_ser_functions_t)); 1282 _hx5_ser_functions._soc_ser_parity_error_cmicx_intr_f = &soc_hx5_ser_error; 1283 soc_ser_function_register(unit, &_hx5_ser_functions); 1284 1285 /* Handler need to be registered for CHIP_INTR_LOW_PRIORITY */ 1286 handle.num = CHIP_INTR_LOW_PRIORITY; 1287 handle.intr_fn = soc_ser_cmicx_intr_handler; 1288 handle.intr_data = NULL; 1289 soc_cmic_intr_register(unit, &handle, 1); 1290 } 1291 1292 int 1293 soc_hx5_ser_lp_mem_info_get(int unit, soc_mem_t mem, int index, 1294 soc_mem_t *hash_mem, int *hash_index) 1295 { 1296 int bank_index, uft_index, lp_index = 0, bank; 1297 int rv = SOC_E_NONE; 1298 1299 switch(mem) { 1300 case L2_ENTRY_LPm: 1301 hash_mem[0] = L2Xm; 1302 if (index < SOC_HX5_NUM_ENTRIES_L2_LP_BANK * SOC_HX5_NUM_BANKS_L2) { 1303 /* dedicated L2 entries(1W) */ 1304 lp_index = index; 1305 } else { 1306 /* UFT mem (1W, 2W, 4W) */ 1307 1308 /* index in uft space */ 1309 uft_index = index - (SOC_HX5_NUM_ENTRIES_L2_LP_BANK * SOC_HX5_NUM_BANKS_L2); 1310 bank = (uft_index / SOC_HX5_NUM_ENTRIES_UFT_LP_BANK); 1311 bank_index = uft_index % SOC_HX5_NUM_ENTRIES_UFT_LP_BANK; 1312 1313 if (bank_index >= 0 && bank_index < 4096) { 1314 /* 1W view - 4K entries per bank */ 1315 lp_index = bank_index + (4096 * bank) + 4096; 1316 } else if (bank_index >= 4096 && bank_index < 6144) { 1317 /* 2W view - 2K entries per bank */ 1318 return SOC_E_INTERNAL; 1319 } else if (bank_index >= 6144 && bank_index < 7168) { 1320 /* 4W view - 1K entries per bank */ 1321 return SOC_E_INTERNAL; 1322 } 1323 } 1324 hash_index[0] = lp_index * 4; 1325 break; 1326 case L3_ENTRY_LPm: 1327 if (index < SOC_HX5_NUM_ENTRIES_L3_LP_BANK * SOC_HX5_NUM_BANKS_L3) { 1328 /* dedicated L3 entries(1W, 2W, 4W) */ 1329 bank = index / SOC_HX5_NUM_ENTRIES_L3_LP_BANK; 1330 bank_index = index % SOC_HX5_NUM_ENTRIES_L3_LP_BANK; 1331 1332 if (bank_index >= 0 && bank_index < 2048) { 1333 /* 1W view - 2K entries per bank */ 1334 hash_mem[0] = L3_ENTRY_SINGLEm; 1335 lp_index = bank_index + (2048 * bank); 1336 } else if (bank_index >= 2048 && bank_index < 3072) { 1337 /* 2W view - 1K entries per bank */ 1338 hash_mem[0] = L3_ENTRY_DOUBLEm; 1339 lp_index = (bank_index - 2048) + (1024 * bank); 1340 } else if (bank_index >= 3072 && bank_index < 3584) { 1341 /* 4W view - 512 entries per bank */ 1342 hash_mem[0] = L3_ENTRY_QUADm; 1343 lp_index = (bank_index - 3072) + (512 * bank); 1344 } 1345 } else { 1346 /* UFT mem (1W, 2W, 4W) */ 1347 1348 /* index in uft space */ 1349 uft_index = index - (SOC_HX5_NUM_ENTRIES_L3_LP_BANK * SOC_HX5_NUM_BANKS_L3); 1350 bank = (uft_index / SOC_HX5_NUM_ENTRIES_UFT_LP_BANK); 1351 bank_index = uft_index % SOC_HX5_NUM_ENTRIES_UFT_LP_BANK; 1352 1353 if (bank_index >= 0 && bank_index < 4096) { 1354 /* 1W view - 4K entries per bank */ 1355 hash_mem[0] = L3_ENTRY_SINGLEm; 1356 lp_index = bank_index + (4096 * bank) + 4096; 1357 } else if (bank_index >= 4096 && bank_index < 6144) { 1358 /* 2W view - 2K entries per bank */ 1359 hash_mem[0] = L3_ENTRY_DOUBLEm; 1360 lp_index = (bank_index - 4096) + (2048 * bank) + 2048; 1361 } else if (bank_index >= 6144 && bank_index < 7168) { 1362 /* 4W view - 1K entries per bank */ 1363 hash_mem[0] = L3_ENTRY_QUADm; 1364 lp_index = (bank_index - 6144) + (1024 * bank) + 1024; 1365 } 1366 } 1367 hash_index[0] = lp_index * 4; 1368 break; 1369 case EXACT_MATCH_LPm: 1370 /* UFT mem (1W, 2W, 4W) */ 1371 bank = index / SOC_HX5_NUM_ENTRIES_UFT_LP_BANK; 1372 bank_index = index % SOC_HX5_NUM_ENTRIES_UFT_LP_BANK; 1373 1374 if (bank_index >= 0 && bank_index < 4096) { 1375 /* 1W view - 4K entries per bank */ 1376 return SOC_E_INTERNAL; 1377 } else if (bank_index >= 4096 && bank_index < 6144) { 1378 /* 2W view - 2K entries per bank */ 1379 hash_mem[0] = EXACT_MATCH_2m; 1380 lp_index = (bank_index - 4096) + (2048 * bank); 1381 } else if (bank_index >= 6144 && bank_index < 7168) { 1382 /* 4W view - 1K entries per bank */ 1383 hash_mem[0] = EXACT_MATCH_4m; 1384 lp_index = (bank_index - 6144) + (1024 * bank); 1385 } 1386 hash_index[0] = lp_index * 4; 1387 break; 1388 case MPLS_ENTRY_LPm: 1389 case VLAN_XLATE_1_LPm: 1390 case VLAN_XLATE_2_LPm: 1391 case EGR_VLAN_XLATE_1_LPm: 1392 case EGR_VLAN_XLATE_2_LPm: 1393 /* UAT mem (1W, 2W) */ 1394 bank = index / SOC_HX5_NUM_ENTRIES_UAT_LP_BANK; 1395 bank_index = index % SOC_HX5_NUM_ENTRIES_UAT_LP_BANK; 1396 1397 if (bank_index >= 0 && bank_index < 1024) { 1398 /* 1W view - 1K entries per bank */ 1399 switch (mem) { 1400 case MPLS_ENTRY_LPm: hash_mem[0] = MPLS_ENTRY_SINGLEm; break; 1401 case VLAN_XLATE_1_LPm: hash_mem[0] = VLAN_XLATE_1_SINGLEm; break; 1402 case VLAN_XLATE_2_LPm: hash_mem[0] = VLAN_XLATE_2_SINGLEm; break; 1403 case EGR_VLAN_XLATE_1_LPm: hash_mem[0] = EGR_VLAN_XLATE_1_SINGLEm; break; 1404 case EGR_VLAN_XLATE_2_LPm: hash_mem[0] = EGR_VLAN_XLATE_2_SINGLEm; break; 1405 } 1406 lp_index = bank_index + (1024 * bank); 1407 } else if (bank_index >= 1024 && bank_index < 1536) { 1408 /* 2W view - 512 entries per bank */ 1409 switch (mem) { 1410 case MPLS_ENTRY_LPm: hash_mem[0] = MPLS_ENTRYm; break; 1411 case VLAN_XLATE_1_LPm: hash_mem[0] = VLAN_XLATE_1_DOUBLEm; break; 1412 case VLAN_XLATE_2_LPm: hash_mem[0] = VLAN_XLATE_2_DOUBLEm; break; 1413 case EGR_VLAN_XLATE_1_LPm: hash_mem[0] = EGR_VLAN_XLATE_1_DOUBLEm; break; 1414 case EGR_VLAN_XLATE_2_LPm: hash_mem[0] = EGR_VLAN_XLATE_2_DOUBLEm; break; 1415 } 1416 lp_index = (bank_index - 1024) + (512 * bank); 1417 } 1418 hash_index[0] = lp_index * 4; 1419 break; 1420 default: 1421 rv = SOC_E_PARAM; 1422 } 1423 1424 return rv; 1425 } 1426 1427 int 1428 soc_helix5_mem_sram_info_get(int unit, soc_mem_t mem, int index, 1429 _soc_ser_sram_info_t *sram_info) 1430 { 1431 int i, base, base_index, offset; 1432 int entries_per_ram = 0, entries_per_bank, contiguous = 0; 1433 int base_bucket; 1434 1435 switch (mem) { 1436 case L2_ENTRY_ECCm: 1437 sram_info->disable_mem = L2_ENTRY_HASH_CONTROLm; 1438 sram_info->disable_mem_field = DISABLE_SBUS_MEMWR_ECC_CHECKf; 1439 sram_info->disable_mem_index = 0; 1440 entries_per_ram = SOC_HX5_NUM_ENTRIES_XOR_RAM; 1441 if (index < SOC_HX5_NUM_ENTRIES_L2) { 1442 /* dedicated L2 entries - XOR not used */ 1443 contiguous = 1; 1444 sram_info->ram_count = 1; 1445 base = index; 1446 } else { 1447 /* UFT mem, 2+1 XOR, stride 8K */ 1448 sram_info->ram_count = SOC_HX5_NUM_XOR_RAM_UFT; 1449 entries_per_bank = entries_per_ram * sram_info->ram_count; 1450 1451 /* index in uft space */ 1452 base_index = index - SOC_HX5_NUM_ENTRIES_L2; 1453 base = (base_index/entries_per_bank)*entries_per_bank; 1454 offset = base_index % entries_per_ram; 1455 /* 1st index for correction */ 1456 base += SOC_HX5_NUM_ENTRIES_L2 + offset; 1457 } 1458 break; 1459 case L3_ENTRY_ECCm: 1460 sram_info->disable_mem = L3_ENTRY_HASH_CONTROLm; 1461 sram_info->disable_mem_field = DISABLE_SBUS_MEMWR_ECC_CHECKf; 1462 sram_info->disable_mem_index = 0; 1463 entries_per_ram = SOC_HX5_NUM_ENTRIES_XOR_RAM; 1464 if (index < SOC_HX5_NUM_ENTRIES_L3) { 1465 /* dedicated L3 entries - XOR not used */ 1466 contiguous = 1; 1467 sram_info->ram_count = 1; 1468 base = index; 1469 } else { 1470 /* UFT mem, 2+1 XOR, stride 8K */ 1471 sram_info->ram_count = SOC_HX5_NUM_XOR_RAM_UFT; 1472 entries_per_bank = entries_per_ram * sram_info->ram_count; 1473 1474 /* index in uft space */ 1475 base_index = index - SOC_HX5_NUM_ENTRIES_L3; 1476 base = (base_index/entries_per_bank)*entries_per_bank; 1477 offset = base_index % entries_per_ram; 1478 base += SOC_HX5_NUM_ENTRIES_L3 + offset; 1479 } 1480 break; 1481 case EXACT_MATCH_ECCm: 1482 /* UFT mem, 2+1 XOR stride 8K */ 1483 sram_info->disable_mem = EXACT_MATCH_HASH_CONTROLm; 1484 sram_info->disable_mem_field = DISABLE_SBUS_MEMWR_ECC_CHECKf; 1485 sram_info->disable_mem_index = 0; 1486 sram_info->ram_count = SOC_HX5_NUM_XOR_RAM_UFT; 1487 entries_per_ram = SOC_HX5_NUM_ENTRIES_XOR_RAM; 1488 entries_per_bank = entries_per_ram * sram_info->ram_count; 1489 1490 /* index in uft space */ 1491 base_index = index; 1492 base = (base_index/entries_per_bank)*entries_per_bank; 1493 offset = base_index % entries_per_ram; 1494 base += offset; 1495 break; 1496 case L3_DEFIP_ALPM_ECCm: 1497 /* UFT mem, 2+1 XOR stride 8K */ 1498 if (!soc_trident3_alpm_mode_get(unit)) { 1499 return SOC_E_PARAM; 1500 } 1501 1502 sram_info->ram_count = SOC_HX5_NUM_XOR_RAM_UFT; 1503 entries_per_ram = SOC_HX5_NUM_ENTRIES_XOR_RAM; 1504 entries_per_bank = entries_per_ram * sram_info->ram_count; 1505 1506 /* index in uft space */ 1507 base_index = index; 1508 base = (base_index/entries_per_bank)*entries_per_bank; 1509 offset = base_index % entries_per_ram; 1510 base += offset; 1511 1512 for (i = 0; i < sram_info->ram_count; i++) { 1513 base_bucket = base % soc_mem_index_count(unit, L3_DEFIP_ALPM_RAWm); 1514 1515 sram_info->view[i] = L3_DEFIP_ALPM_RAWm; 1516 /* 1:4 Need to fix 1 entry for each ECC entry */ 1517 sram_info->index_count[i] = 1; 1518 sram_info->mem_indexes[i][0] = base_bucket; 1519 1520 base += entries_per_ram; 1521 } 1522 1523 return SOC_E_NONE; 1524 case VLAN_XLATE_1_ECCm: 1525 contiguous = 1; 1526 sram_info->disable_mem = VLAN_XLATE_1_HASH_CONTROLm; 1527 sram_info->disable_mem_field = DISABLE_SBUS_MEMWR_ECC_CHECKf; 1528 sram_info->disable_mem_index = 0; 1529 /* XOR not used */ 1530 sram_info->ram_count = 1; 1531 base = index; 1532 break; 1533 case VLAN_XLATE_2_ECCm: 1534 contiguous = 1; 1535 sram_info->disable_mem = VLAN_XLATE_2_HASH_CONTROLm; 1536 sram_info->disable_mem_field = DISABLE_SBUS_MEMWR_ECC_CHECKf; 1537 sram_info->disable_mem_index = 0; 1538 /* XOR not used */ 1539 sram_info->ram_count = 1; 1540 base = index; 1541 break; 1542 case EGR_VLAN_XLATE_1_ECCm: 1543 contiguous = 1; 1544 sram_info->disable_mem = EGR_VLAN_XLATE_1_HASH_CONTROLm; 1545 sram_info->disable_mem_field = DISABLE_SBUS_MEMWR_ECC_CHECKf; 1546 sram_info->disable_mem_index = 0; 1547 /* XOR not used */ 1548 sram_info->ram_count = 1; 1549 base = index; 1550 break; 1551 case EGR_VLAN_XLATE_2_ECCm: 1552 contiguous = 1; 1553 sram_info->disable_mem = EGR_VLAN_XLATE_2_HASH_CONTROLm; 1554 sram_info->disable_mem_field = DISABLE_SBUS_MEMWR_ECC_CHECKf; 1555 sram_info->disable_mem_index = 0; 1556 /* XOR not used */ 1557 sram_info->ram_count = 1; 1558 base = index; 1559 break; 1560 case MPLS_ENTRY_ECCm: 1561 contiguous = 1; 1562 sram_info->disable_mem = MPLS_ENTRY_HASH_CONTROLm; 1563 sram_info->disable_mem_field = DISABLE_SBUS_MEMWR_ECC_CHECKf; 1564 sram_info->disable_mem_index = 0; 1565 /* XOR not used */ 1566 sram_info->ram_count = 1; 1567 base = index; 1568 break; 1569 case ING_DNAT_ADDRESS_TYPE_ECCm: 1570 case ING_VP_VLAN_MEMBERSHIP_ECCm: 1571 case EGR_VP_VLAN_MEMBERSHIP_ECCm: 1572 case SUBPORT_ID_TO_SGPP_MAP_ECCm: 1573 contiguous = 1; 1574 sram_info->view[0] = mem; 1575 sram_info->index_count[0] = 1; 1576 sram_info->ram_count = 1; 1577 base = index; 1578 break; 1579 default: 1580 return SOC_E_UNAVAIL; 1581 } 1582 sram_info->mem_indexes[0][0] = base; 1583 if (contiguous) { 1584 for (i = 1; i < sram_info->ram_count; i++) { 1585 sram_info->mem_indexes[i][0] = sram_info->mem_indexes[i-1][0] + 1; 1586 } 1587 } else { 1588 for (i = 1; i < sram_info->ram_count; i++) { 1589 sram_info->mem_indexes[i][0] = sram_info->mem_indexes[i-1][0] + 1590 entries_per_ram; 1591 } 1592 } 1593 return SOC_E_NONE; 1594 } 1595 1596 STATIC soc_error_t 1597 _soc_hx5_ser_parity_control_reg_set(int unit, ser_test_data_t *test_data, int enable) 1598 { 1599 return soc_td3_ser_parity_control_reg_set(unit, test_data, enable); 1600 } 1601 1602 STATIC soc_error_t 1603 _soc_hx5_ser_error_injection_support(int unit, soc_mem_t mem, int pipe_target) 1604 { 1605 return soc_td3_ser_error_injection_support(unit, mem, pipe_target); 1606 } 1607 1608 STATIC soc_error_t 1609 _ser_hx5_ser_correction_info_get(int unit, ser_correction_info_t *corr_info) 1610 { 1611 return soc_td3_ser_correction_info_get(unit, corr_info); 1612 } 1613 1614 /* 1615 * Function: 1616 * soc_hx5_ser_inject_error 1617 * Purpose: 1618 * Injects an error into a single td3 memory 1619 * Parameters: 1620 * unit - (IN) Device Number 1621 * mem - (IN) The memory into which an error will be injected 1622 * pipeTarget - (IN) The pipe to use when injecting the error 1623 * index - (IN) The index into which the error will be injected. 1624 */ 1625 STATIC soc_error_t 1626 soc_hx5_ser_inject_error(int unit, uint32 flags, soc_mem_t mem, int pipe_target, 1627 int block, int index) 1628 { 1629 return soc_td3_ser_inject_or_test_mem(unit, mem, pipe_target, block, index, 1630 SER_SINGLE_INDEX, TRUE, FALSE, flags); 1631 } 1632 1633 /* 1634 * Function: 1635 * soc_hx5_ser_test_mem 1636 * Purpose: 1637 * Perform SER test on a single memory, or generate a test the user can 1638 * enter by the command line. 1639 * Parameters: 1640 * unit - (IN) Device Number 1641 * mem - (IN) The memory into which an error will be injected 1642 * test_type - (IN) How many indices to test in the passes memory 1643 * cmd - (IN) TRUE if a command-line test is desired. 1644 * Returns: 1645 * SOC_E_NONE if test passes, an error otherwise (multiple types of errors 1646 * are possible.) 1647 */ 1648 STATIC soc_error_t 1649 soc_hx5_ser_test_mem(int unit, soc_mem_t mem, _soc_ser_test_t test_type, 1650 int cmd) 1651 { 1652 return soc_td3_ser_inject_or_test_mem(unit, mem, -1, MEM_BLOCK_ANY, 0, 1653 test_type, FALSE, cmd, FALSE); 1654 } 1655 1656 STATIC void 1657 soc_hx5_ser_parity_control_check_all(int unit) 1658 { 1659 #if defined(BCM_56370_A0) 1660 (void)soc_ser_test_parity_control_check(unit, _SOC_SER_TYPE_BUS, 1661 (void*) _soc_bcm56370_a0_ip_bus_ser_info); 1662 (void)soc_ser_test_parity_control_check(unit, _SOC_SER_TYPE_BUS, 1663 (void*) _soc_bcm56370_a0_ep_bus_ser_info); 1664 (void)soc_ser_test_parity_control_check(unit, _SOC_SER_TYPE_BUF, 1665 (void*) _soc_bcm56370_a0_ip_buffer_ser_info); 1666 (void)soc_ser_test_parity_control_check(unit, _SOC_SER_TYPE_BUF, 1667 (void*) _soc_bcm56370_a0_ep_buffer_ser_info); 1668 #endif 1669 } 1670 /* 1671 * Function: 1672 * soc_hx5_ser_test 1673 * Purpose: 1674 * Tests that SER is working for all supported memories. 1675 * Parameters: 1676 * unit - (IN) Device Number 1677 * test_type - (IN) How many indices to test for each memory 1678 * Returns: 1679 * SOC_E_NONE if test passes, an error otherwise (multiple types of errors are 1680 * possible.) 1681 */ 1682 STATIC soc_error_t 1683 soc_hx5_ser_test(int unit, _soc_ser_test_t test_type) 1684 { 1685 soc_hx5_ser_parity_control_check_all(unit); 1686 return soc_td3_ser_test(unit, test_type); 1687 } 1688 1689 static soc_ser_test_functions_t _soc_hx5_ser_test_fun; 1690 1691 void 1692 soc_hx5_ser_test_register(int unit) 1693 { 1694 /*Initialize chip-specific functions for SER testing*/ 1695 memset(&_soc_hx5_ser_test_fun, 0, sizeof(soc_ser_test_functions_t)); 1696 _soc_hx5_ser_test_fun.inject_error_f = &soc_hx5_ser_inject_error; 1697 _soc_hx5_ser_test_fun.test_mem = &soc_hx5_ser_test_mem; 1698 _soc_hx5_ser_test_fun.test = &soc_hx5_ser_test; 1699 _soc_hx5_ser_test_fun.parity_control = &_soc_hx5_ser_parity_control_reg_set; 1700 _soc_hx5_ser_test_fun.injection_support = &_soc_hx5_ser_error_injection_support; 1701 _soc_hx5_ser_test_fun.correction_info_get = &_ser_hx5_ser_correction_info_get; 1702 soc_ser_test_functions_register(unit, &_soc_hx5_ser_test_fun); 1703 } 1704 1705 #endif /* BCM_HELIX5_SUPPORT */