counter.c (99961B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * HX5 counter module routines. 8 */ 9 10 #include <shared/bsl.h> 11 12 #include <sal/core/libc.h> 13 14 #include <soc/debug.h> 15 #include <soc/util.h> 16 #include <soc/mem.h> 17 #include <soc/helix5.h> 18 19 #ifdef BCM_HELIX5_SUPPORT 20 21 int 22 soc_counter_helix5_generic_get_info(int unit, soc_ctr_control_info_t 23 ctrl_info, soc_reg_t id, int* base_index, 24 int* num_entries) 25 { 26 soc_info_t *si = &SOC_INFO(unit); 27 soc_control_t *soc = SOC_CONTROL(unit); 28 soc_counter_non_dma_t *non_dma; 29 soc_port_t port; 30 soc_port_t phy_port = 0, mmu_port = 0; 31 int pipe, c_offset, pipe_offset = 0; 32 33 if ((id < NUM_SOC_REG) || (id >= SOC_COUNTER_NON_DMA_END)) { 34 return SOC_E_PARAM; 35 } 36 37 non_dma = &soc->counter_non_dma[id - SOC_COUNTER_NON_DMA_START]; 38 39 if (!(non_dma->flags & _SOC_COUNTER_NON_DMA_VALID) && 40 !(non_dma->flags & _SOC_COUNTER_NON_DMA_SUBSET_PARENT)) { 41 /* For Parent-Child model, return E_UNAVAIL if child non_dma is INVALID. 42 */ 43 return SOC_E_UNAVAIL; 44 } 45 46 *base_index = 0; 47 pipe = 0; 48 switch (ctrl_info.instance_type) { 49 case SOC_CTR_INSTANCE_TYPE_PORT: 50 port = ctrl_info.instance; 51 if (si->port_l2p_mapping[port] == -1) { 52 *base_index = 0; 53 *num_entries = 0; 54 return SOC_E_PARAM; 55 } 56 57 switch (id) { 58 case SOC_COUNTER_NON_DMA_EGR_PERQ_XMT_PKT: 59 case SOC_COUNTER_NON_DMA_EGR_PERQ_XMT_BYTE: 60 case SOC_COUNTER_NON_DMA_EGR_PERQ_XMT_PKT_UC: 61 case SOC_COUNTER_NON_DMA_EGR_PERQ_XMT_BYTE_UC: 62 case SOC_COUNTER_NON_DMA_PORT_DROP_PKT_OBM_LOSSY_LO: 63 case SOC_COUNTER_NON_DMA_PORT_DROP_BYTE_OBM_LOSSY_LO: 64 case SOC_COUNTER_NON_DMA_PORT_DROP_PKT_OBM_LOSSY_HI: 65 case SOC_COUNTER_NON_DMA_PORT_DROP_BYTE_OBM_LOSSY_HI: 66 case SOC_COUNTER_NON_DMA_PORT_DROP_PKT_OBM_LOSSLESS0: 67 case SOC_COUNTER_NON_DMA_PORT_DROP_BYTE_OBM_LOSSLESS0: 68 case SOC_COUNTER_NON_DMA_PORT_DROP_PKT_OBM_LOSSLESS1: 69 case SOC_COUNTER_NON_DMA_PORT_DROP_BYTE_OBM_LOSSLESS1: 70 case SOC_COUNTER_NON_DMA_PORT_OBM_FC_EVENTS: 71 return soc_counter_helix5_get_info(unit, port, id, 72 base_index, num_entries); 73 break; 74 default: 75 return SOC_E_PARAM; 76 } 77 break; 78 case SOC_CTR_INSTANCE_TYPE_XPE_PORT: 79 port = (ctrl_info.instance & 0xFFC000) >> 14; 80 phy_port = si->port_l2p_mapping[port]; 81 mmu_port = si->port_p2m_mapping[phy_port]; 82 pipe = 0; 83 84 switch (id) { 85 case SOC_COUNTER_NON_DMA_COSQ_DROP_BYTE: 86 case SOC_COUNTER_NON_DMA_COSQ_DROP_BYTE_UC: 87 case SOC_COUNTER_NON_DMA_COSQ_DROP_PKT: 88 case SOC_COUNTER_NON_DMA_COSQ_DROP_PKT_UC: 89 case SOC_COUNTER_NON_DMA_PORT_DROP_PKT_YELLOW: 90 case SOC_COUNTER_NON_DMA_PORT_DROP_PKT_RED: 91 case SOC_COUNTER_NON_DMA_PORT_WRED_PKT_GREEN: 92 case SOC_COUNTER_NON_DMA_PORT_WRED_PKT_YELLOW: 93 case SOC_COUNTER_NON_DMA_PORT_WRED_PKT_RED: 94 case SOC_COUNTER_NON_DMA_PORT_DROP_PKT_ING: 95 case SOC_COUNTER_NON_DMA_PORT_DROP_BYTE_ING: 96 return soc_counter_helix5_get_info(unit, port, id, 97 base_index, num_entries); 98 break; 99 case SOC_COUNTER_NON_DMA_PG_MIN_PEAK: 100 case SOC_COUNTER_NON_DMA_PG_MIN_CURRENT: 101 case SOC_COUNTER_NON_DMA_PG_SHARED_PEAK: 102 case SOC_COUNTER_NON_DMA_PG_SHARED_CURRENT: 103 case SOC_COUNTER_NON_DMA_PG_HDRM_PEAK: 104 case SOC_COUNTER_NON_DMA_PG_HDRM_CURRENT: 105 *num_entries = non_dma->entries_per_port; 106 pipe_offset = (non_dma->num_entries / NUM_PIPE(unit)) * pipe; 107 108 if (IS_CPU_PORT(unit, port)) { 109 *base_index += mmu_port; 110 } else { 111 *base_index += pipe_offset + 112 (mmu_port & SOC_HX5_MMU_PORT_STRIDE); 113 } 114 *base_index *= _HX5_MMU_NUM_PG; 115 break; 116 case SOC_COUNTER_NON_DMA_QUEUE_PEAK: 117 case SOC_COUNTER_NON_DMA_QUEUE_CURRENT: 118 case SOC_COUNTER_NON_DMA_UC_QUEUE_PEAK: 119 case SOC_COUNTER_NON_DMA_UC_QUEUE_CURRENT: 120 if ((id == SOC_COUNTER_NON_DMA_QUEUE_PEAK) || 121 (id == SOC_COUNTER_NON_DMA_QUEUE_CURRENT)) { 122 *base_index = si->port_cosq_base[port]; 123 *num_entries = si->port_num_cosq[port]; 124 } else { 125 *base_index = si->port_uc_cosq_base[port]; 126 *num_entries = si->port_num_uc_cosq[port]; 127 } 128 break; 129 default: 130 return SOC_E_PARAM; 131 } 132 break; 133 case SOC_CTR_INSTANCE_TYPE_XPE: 134 switch (id) { 135 case SOC_COUNTER_NON_DMA_DROP_RQ_PKT: 136 case SOC_COUNTER_NON_DMA_DROP_RQ_BYTE: 137 case SOC_COUNTER_NON_DMA_DROP_RQ_PKT_YELLOW: 138 case SOC_COUNTER_NON_DMA_DROP_RQ_PKT_RED: 139 case SOC_COUNTER_NON_DMA_POOL_PEAK: 140 case SOC_COUNTER_NON_DMA_POOL_CURRENT: 141 *base_index = 0; 142 *num_entries = non_dma->num_entries; 143 break; 144 default: 145 return SOC_E_PARAM; 146 } 147 break; 148 case SOC_CTR_INSTANCE_TYPE_PIPE: 149 pipe = ctrl_info.instance; 150 if ((pipe >= NUM_PIPE(unit)) || (pipe < -1) ) { 151 return SOC_E_PARAM; 152 } 153 switch (id) { 154 case SOC_COUNTER_NON_DMA_EFP_PKT: 155 case SOC_COUNTER_NON_DMA_EFP_BYTE: 156 *base_index = 0; 157 *num_entries = non_dma->num_entries / NUM_PIPE(unit); 158 if (pipe > 0) { 159 pipe_offset = pipe * (*num_entries); 160 *base_index += pipe_offset; 161 } 162 break; 163 default: 164 return SOC_E_INTERNAL; 165 } 166 break; 167 case SOC_CTR_INSTANCE_TYPE_POOL: 168 c_offset = ctrl_info.instance; 169 if ((c_offset < 0) || (c_offset >= non_dma->extra_ctr_ct)) { 170 return SOC_E_PARAM; 171 } 172 173 switch (id) { 174 case SOC_COUNTER_NON_DMA_ING_FLEX_BYTE: 175 case SOC_COUNTER_NON_DMA_EGR_FLEX_BYTE: 176 case SOC_COUNTER_NON_DMA_ING_FLEX_PKT: 177 case SOC_COUNTER_NON_DMA_EGR_FLEX_PKT: 178 *base_index = 0; 179 180 if ((non_dma->flags & _SOC_COUNTER_NON_DMA_SUBSET_PARENT) && 181 (non_dma->extra_ctrs != NULL)) { 182 /* Refer extra_ctrs_init for PKT/BYTE control block placement. 183 */ 184 non_dma = &non_dma->extra_ctrs[(c_offset << 1)]; 185 } 186 *num_entries = non_dma->num_entries / NUM_PIPE(unit); 187 break; 188 default: 189 return SOC_E_PARAM; 190 } 191 break; 192 case SOC_CTR_INSTANCE_TYPE_POOL_PIPE: 193 c_offset = (ctrl_info.instance & 0x3F0) >> 4; 194 pipe = ctrl_info.instance & 0xF; 195 if ((c_offset < 0) || (c_offset >= non_dma->extra_ctr_ct) || 196 (pipe >= NUM_PIPE(unit)) || (pipe < 0)) { 197 return SOC_E_PARAM; 198 } 199 switch (id) { 200 case SOC_COUNTER_NON_DMA_ING_FLEX_BYTE: 201 case SOC_COUNTER_NON_DMA_EGR_FLEX_BYTE: 202 case SOC_COUNTER_NON_DMA_ING_FLEX_PKT: 203 case SOC_COUNTER_NON_DMA_EGR_FLEX_PKT: 204 205 if ((non_dma->flags & _SOC_COUNTER_NON_DMA_SUBSET_PARENT) && 206 (non_dma->extra_ctrs != NULL)) { 207 /* Refer extra_ctrs_init for PKT/BYTE control block placement. 208 */ 209 non_dma = &non_dma->extra_ctrs[(c_offset << 1)]; 210 } 211 *num_entries = non_dma->num_entries / NUM_PIPE(unit); 212 *base_index = (*num_entries)*pipe; 213 break; 214 default: 215 return SOC_E_PARAM; 216 } 217 break; 218 219 case SOC_CTR_INSTANCE_TYPE_SFLOW: 220 c_offset = ctrl_info.instance; 221 if ((c_offset < 0) || (c_offset >= non_dma->extra_ctr_ct)) { 222 return SOC_E_PARAM; 223 } 224 225 *base_index = 0; 226 if ((non_dma->flags & _SOC_COUNTER_NON_DMA_SUBSET_PARENT) && 227 (non_dma->extra_ctrs != NULL)) { 228 non_dma = &non_dma->extra_ctrs[(c_offset << 1)]; 229 } 230 *num_entries = non_dma->num_entries; 231 break; 232 case SOC_CTR_INSTANCE_TYPE_FT_GROUP: 233 *num_entries = non_dma->num_entries; 234 break; 235 default: 236 return SOC_E_PARAM; 237 } 238 *base_index += non_dma->base_index; 239 return SOC_E_NONE; 240 } 241 242 243 int 244 soc_counter_helix5_get_info(int unit, soc_port_t port, soc_reg_t id, 245 int *base_index, int *num_entries) 246 { 247 soc_info_t *si; 248 soc_control_t *soc; 249 soc_counter_non_dma_t *non_dma; 250 soc_port_t phy_port, mmu_port; 251 int pipe, pipe_offset, obm_id = 0, lane = 0; 252 uint8 c_offset = 0; /* child offset in Parent-child model */ 253 254 soc = SOC_CONTROL(unit); 255 256 if (id >= NUM_SOC_REG) { 257 if (id >= SOC_COUNTER_NON_DMA_END) { 258 return SOC_E_PARAM; 259 } 260 } 261 262 non_dma = &soc->counter_non_dma[id - SOC_COUNTER_NON_DMA_START]; 263 264 if (!(non_dma->flags & _SOC_COUNTER_NON_DMA_VALID) && 265 !(non_dma->flags & _SOC_COUNTER_NON_DMA_SUBSET_PARENT)) { 266 /* For Parent-Child model, return E_UNAVAIL if child non_dma is INVALID. 267 */ 268 return SOC_E_UNAVAIL; 269 } 270 271 si = &SOC_INFO(unit); 272 if (si->port_l2p_mapping[port] == -1) { 273 *base_index = 0; 274 *num_entries = 0; 275 return SOC_E_NONE; 276 } 277 278 phy_port = si->port_l2p_mapping[port]; 279 mmu_port = si->port_p2m_mapping[phy_port]; 280 pipe = si->port_pipe[port]; 281 282 switch (id) { 283 case SOC_COUNTER_NON_DMA_EGR_PERQ_XMT_PKT: 284 case SOC_COUNTER_NON_DMA_EGR_PERQ_XMT_BYTE: 285 /* For EGR_PERQ_XMT_COUNTERSm 286 * MCQ range is 1280-2617 287 */ 288 *base_index = si->port_cosq_base[port] + SOC_HX5_NUM_UC_QUEUES_PER_PIPE; 289 *num_entries = si->port_num_cosq[port]; 290 break; 291 case SOC_COUNTER_NON_DMA_EGR_PERQ_XMT_PKT_UC: 292 case SOC_COUNTER_NON_DMA_EGR_PERQ_XMT_BYTE_UC: 293 /* For EGR_PERQ_XMT_COUNTERSm 294 * UCQ range is 0-1279 295 */ 296 *base_index = si->port_uc_cosq_base[port]; 297 *num_entries = si->port_num_uc_cosq[port]; 298 break; 299 case SOC_COUNTER_NON_DMA_COSQ_DROP_BYTE: 300 case SOC_COUNTER_NON_DMA_COSQ_DROP_BYTE_UC: 301 case SOC_COUNTER_NON_DMA_COSQ_DROP_PKT: 302 case SOC_COUNTER_NON_DMA_COSQ_DROP_PKT_UC: 303 if ((id == SOC_COUNTER_NON_DMA_COSQ_DROP_PKT) || 304 (id == SOC_COUNTER_NON_DMA_COSQ_DROP_BYTE)) { 305 *base_index = si->port_cosq_base[port]; 306 *num_entries = si->port_num_cosq[port]; 307 } else { 308 *base_index = si->port_uc_cosq_base[port]; 309 *num_entries = si->port_num_uc_cosq[port]; 310 } 311 pipe_offset = (non_dma->num_entries / NUM_PIPE(unit)) * pipe; 312 *base_index += pipe_offset; 313 break; 314 case SOC_COUNTER_NON_DMA_PORT_DROP_PKT_ING: 315 case SOC_COUNTER_NON_DMA_PORT_DROP_BYTE_ING: 316 *base_index = mmu_port; 317 pipe_offset = (non_dma->num_entries / NUM_PIPE(unit)) * pipe; 318 *base_index += pipe_offset; 319 *num_entries = 1; 320 break; 321 case SOC_COUNTER_NON_DMA_ING_FLEX_BYTE: 322 case SOC_COUNTER_NON_DMA_EGR_FLEX_BYTE: 323 case SOC_COUNTER_NON_DMA_ING_FLEX_PKT: 324 case SOC_COUNTER_NON_DMA_EGR_FLEX_PKT: 325 *base_index = 0; 326 327 if ((non_dma->flags & _SOC_COUNTER_NON_DMA_SUBSET_PARENT) && 328 (non_dma->extra_ctrs != NULL)) { 329 /* refer extra_ctrs_init for pkt/byte control block placement. 330 */ 331 non_dma = &non_dma->extra_ctrs[(c_offset << 1)]; 332 } 333 *num_entries = non_dma->num_entries / NUM_PIPE(unit); 334 break; 335 case SOC_COUNTER_NON_DMA_PORT_DROP_PKT_YELLOW: 336 case SOC_COUNTER_NON_DMA_PORT_DROP_PKT_RED: 337 case SOC_COUNTER_NON_DMA_PORT_WRED_PKT_GREEN: 338 case SOC_COUNTER_NON_DMA_PORT_WRED_PKT_RED: 339 case SOC_COUNTER_NON_DMA_PORT_WRED_PKT_YELLOW: 340 if (mmu_port < 72) { 341 *base_index = mmu_port; 342 *num_entries = 1; 343 } else { 344 return SOC_E_INTERNAL; 345 } 346 break; 347 348 case SOC_COUNTER_NON_DMA_EFP_PKT: 349 case SOC_COUNTER_NON_DMA_EFP_BYTE: 350 *base_index = 0; 351 *num_entries = non_dma->num_entries / NUM_PIPE(unit); 352 break; 353 case SOC_COUNTER_NON_DMA_PORT_DROP_PKT_OBM_LOSSY_LO: 354 case SOC_COUNTER_NON_DMA_PORT_DROP_BYTE_OBM_LOSSY_LO: 355 case SOC_COUNTER_NON_DMA_PORT_DROP_PKT_OBM_LOSSY_HI: 356 case SOC_COUNTER_NON_DMA_PORT_DROP_BYTE_OBM_LOSSY_HI: 357 case SOC_COUNTER_NON_DMA_PORT_DROP_PKT_OBM_LOSSLESS0: 358 case SOC_COUNTER_NON_DMA_PORT_DROP_BYTE_OBM_LOSSLESS0: 359 case SOC_COUNTER_NON_DMA_PORT_DROP_PKT_OBM_LOSSLESS1: 360 case SOC_COUNTER_NON_DMA_PORT_DROP_BYTE_OBM_LOSSLESS1: 361 case SOC_COUNTER_NON_DMA_PORT_OBM_FC_EVENTS: 362 if (IS_CPU_PORT(unit, port) || IS_LB_PORT(unit, port) || 363 IS_FAE_PORT(unit, port)) { 364 return SOC_E_PARAM; 365 } 366 *base_index = 0; 367 *num_entries = 1; 368 /* find obm from the port number */ 369 SOC_IF_ERROR_RETURN 370 (soc_helix5_port_obm_info_get(unit, port, &obm_id, &lane)); 371 if (obm_id >= _HX5_OBMS_PER_PIPE) { 372 return SOC_E_PARAM; 373 } 374 soc_counter_trident3_get_child_dma_by_idx(unit, non_dma, 375 obm_id, &non_dma); 376 *base_index += lane; 377 break; 378 default: 379 return SOC_E_INTERNAL; 380 } 381 *base_index += non_dma->base_index; 382 return SOC_E_NONE; 383 } 384 385 /* Function to initialize OBM extra counters */ 386 STATIC int 387 soc_counter_helix5_extra_obm_ctrs_init(int unit, 388 soc_counter_non_dma_t *non_dma_parent, 389 soc_counter_non_dma_t *non_dma_extra, 390 uint32 extra_ctr_ct, 391 int *total_entries) 392 { 393 #define LOSSY_LO 0 394 #define LOSSY_HI 1 395 #define LOSSLESS0 2 396 #define LOSSLESS1 3 397 char obm_type_str[][12] = {"LOSSY_LO", "LOSSY_HI", 398 "LOSSLESS0", "LOSSLESS1"}; /* For CNAME */ 399 int i, byte_flag = 0, obm_type = 0, fc = 0, parent_base_index = 0; 400 uint32 count = 0; 401 402 soc_reg_t obm_drop_pkt_regs[][4] = { 403 {IDB_OBM0_Q_LOSSY_LO_PKT_DROP_COUNTr, IDB_OBM0_Q_LOSSY_HI_PKT_DROP_COUNTr, 404 IDB_OBM0_Q_LOSSLESS0_PKT_DROP_COUNTr, IDB_OBM0_Q_LOSSLESS1_PKT_DROP_COUNTr 405 }, 406 {IDB_OBM1_Q_LOSSY_LO_PKT_DROP_COUNTr, IDB_OBM1_Q_LOSSY_HI_PKT_DROP_COUNTr, 407 IDB_OBM1_Q_LOSSLESS0_PKT_DROP_COUNTr, IDB_OBM1_Q_LOSSLESS1_PKT_DROP_COUNTr 408 }, 409 {IDB_OBM2_Q_LOSSY_LO_PKT_DROP_COUNTr, IDB_OBM2_Q_LOSSY_HI_PKT_DROP_COUNTr, 410 IDB_OBM2_Q_LOSSLESS0_PKT_DROP_COUNTr, IDB_OBM2_Q_LOSSLESS1_PKT_DROP_COUNTr 411 }, 412 {IDB_OBM0_LOSSY_LO_PKT_DROP_COUNTr, IDB_OBM0_LOSSY_HI_PKT_DROP_COUNTr, 413 IDB_OBM0_LOSSLESS0_PKT_DROP_COUNTr, IDB_OBM0_LOSSLESS1_PKT_DROP_COUNTr 414 }, 415 {IDB_OBM1_LOSSY_LO_PKT_DROP_COUNTr, IDB_OBM1_LOSSY_HI_PKT_DROP_COUNTr, 416 IDB_OBM1_LOSSLESS0_PKT_DROP_COUNTr, IDB_OBM1_LOSSLESS1_PKT_DROP_COUNTr 417 }, 418 {IDB_OBM2_LOSSY_LO_PKT_DROP_COUNTr, IDB_OBM2_LOSSY_HI_PKT_DROP_COUNTr, 419 IDB_OBM2_LOSSLESS0_PKT_DROP_COUNTr, IDB_OBM2_LOSSLESS1_PKT_DROP_COUNTr 420 }, 421 {IDB_OBM3_LOSSY_LO_PKT_DROP_COUNTr, IDB_OBM3_LOSSY_HI_PKT_DROP_COUNTr, 422 IDB_OBM3_LOSSLESS0_PKT_DROP_COUNTr, IDB_OBM3_LOSSLESS1_PKT_DROP_COUNTr 423 }, 424 {IDB_OBM0_48_LOSSY_LO_PKT_DROP_COUNTr, IDB_OBM0_48_LOSSY_HI_PKT_DROP_COUNTr, 425 IDB_OBM0_48_LOSSLESS0_PKT_DROP_COUNTr, IDB_OBM0_48_LOSSLESS1_PKT_DROP_COUNTr 426 }, 427 {IDB_OBM1_48_LOSSY_LO_PKT_DROP_COUNTr, IDB_OBM1_48_LOSSY_HI_PKT_DROP_COUNTr, 428 IDB_OBM1_48_LOSSLESS0_PKT_DROP_COUNTr, IDB_OBM1_48_LOSSLESS1_PKT_DROP_COUNTr 429 }, 430 {IDB_OBM2_48_LOSSY_LO_PKT_DROP_COUNTr, IDB_OBM2_48_LOSSY_HI_PKT_DROP_COUNTr, 431 IDB_OBM2_48_LOSSLESS0_PKT_DROP_COUNTr, IDB_OBM2_48_LOSSLESS1_PKT_DROP_COUNTr 432 }, 433 }; 434 soc_reg_t obm_drop_byte_regs[][4] = { 435 {IDB_OBM0_Q_LOSSY_LO_BYTE_DROP_COUNTr, IDB_OBM0_Q_LOSSY_HI_BYTE_DROP_COUNTr, 436 IDB_OBM0_Q_LOSSLESS0_BYTE_DROP_COUNTr, IDB_OBM0_Q_LOSSLESS1_BYTE_DROP_COUNTr 437 }, 438 {IDB_OBM1_Q_LOSSY_LO_BYTE_DROP_COUNTr, IDB_OBM1_Q_LOSSY_HI_BYTE_DROP_COUNTr, 439 IDB_OBM1_Q_LOSSLESS0_BYTE_DROP_COUNTr, IDB_OBM1_Q_LOSSLESS1_BYTE_DROP_COUNTr 440 }, 441 {IDB_OBM2_Q_LOSSY_LO_BYTE_DROP_COUNTr, IDB_OBM2_Q_LOSSY_HI_BYTE_DROP_COUNTr, 442 IDB_OBM2_Q_LOSSLESS0_BYTE_DROP_COUNTr, IDB_OBM2_Q_LOSSLESS1_BYTE_DROP_COUNTr 443 }, 444 {IDB_OBM0_LOSSY_LO_BYTE_DROP_COUNTr, IDB_OBM0_LOSSY_HI_BYTE_DROP_COUNTr, 445 IDB_OBM0_LOSSLESS0_BYTE_DROP_COUNTr, IDB_OBM0_LOSSLESS1_BYTE_DROP_COUNTr 446 }, 447 {IDB_OBM1_LOSSY_LO_BYTE_DROP_COUNTr, IDB_OBM1_LOSSY_HI_BYTE_DROP_COUNTr, 448 IDB_OBM1_LOSSLESS0_BYTE_DROP_COUNTr, IDB_OBM1_LOSSLESS1_BYTE_DROP_COUNTr 449 }, 450 {IDB_OBM2_LOSSY_LO_BYTE_DROP_COUNTr, IDB_OBM2_LOSSY_HI_BYTE_DROP_COUNTr, 451 IDB_OBM2_LOSSLESS0_BYTE_DROP_COUNTr, IDB_OBM2_LOSSLESS1_BYTE_DROP_COUNTr 452 }, 453 {IDB_OBM3_LOSSY_LO_BYTE_DROP_COUNTr, IDB_OBM3_LOSSY_HI_BYTE_DROP_COUNTr, 454 IDB_OBM3_LOSSLESS0_BYTE_DROP_COUNTr, IDB_OBM3_LOSSLESS1_BYTE_DROP_COUNTr 455 }, 456 {IDB_OBM0_48_LOSSY_LO_BYTE_DROP_COUNTr, IDB_OBM0_48_LOSSY_HI_BYTE_DROP_COUNTr, 457 IDB_OBM0_48_LOSSLESS0_BYTE_DROP_COUNTr, IDB_OBM0_48_LOSSLESS1_BYTE_DROP_COUNTr 458 }, 459 {IDB_OBM1_48_LOSSY_LO_BYTE_DROP_COUNTr, IDB_OBM1_48_LOSSY_HI_BYTE_DROP_COUNTr, 460 IDB_OBM1_48_LOSSLESS0_BYTE_DROP_COUNTr, IDB_OBM1_48_LOSSLESS1_BYTE_DROP_COUNTr 461 }, 462 {IDB_OBM2_48_LOSSY_LO_BYTE_DROP_COUNTr, IDB_OBM2_48_LOSSY_HI_BYTE_DROP_COUNTr, 463 IDB_OBM2_48_LOSSLESS0_BYTE_DROP_COUNTr, IDB_OBM2_48_LOSSLESS1_BYTE_DROP_COUNTr 464 }, 465 }; 466 soc_reg_t obm_fc_event_regs[] = { 467 IDB_OBM0_Q_FLOW_CONTROL_EVENT_COUNTr, 468 IDB_OBM1_Q_FLOW_CONTROL_EVENT_COUNTr, 469 IDB_OBM2_Q_FLOW_CONTROL_EVENT_COUNTr, 470 IDB_OBM0_FLOW_CONTROL_EVENT_COUNTr, 471 IDB_OBM1_FLOW_CONTROL_EVENT_COUNTr, 472 IDB_OBM2_FLOW_CONTROL_EVENT_COUNTr, 473 IDB_OBM3_FLOW_CONTROL_EVENT_COUNTr, 474 IDB_OBM0_48_FLOW_CONTROL_EVENT_COUNTr, 475 IDB_OBM1_48_FLOW_CONTROL_EVENT_COUNTr, 476 IDB_OBM2_48_FLOW_CONTROL_EVENT_COUNTr, 477 }; 478 479 count = COUNTOF(obm_drop_byte_regs); 480 if (count > extra_ctr_ct) { 481 return SOC_E_PARAM; 482 } 483 484 /* Do sanity check for input params */ 485 if (!(non_dma_parent->flags & _SOC_COUNTER_NON_DMA_SUBSET_PARENT)) { 486 /* Only for Extra counters */ 487 return SOC_E_PARAM; 488 } 489 switch (non_dma_parent->id) { 490 case SOC_COUNTER_NON_DMA_PORT_DROP_PKT_OBM_LOSSY_LO: 491 case SOC_COUNTER_NON_DMA_PORT_DROP_PKT_OBM_LOSSY_HI: 492 case SOC_COUNTER_NON_DMA_PORT_DROP_PKT_OBM_LOSSLESS0: 493 case SOC_COUNTER_NON_DMA_PORT_DROP_PKT_OBM_LOSSLESS1: 494 byte_flag = 0; 495 break; 496 case SOC_COUNTER_NON_DMA_PORT_DROP_BYTE_OBM_LOSSY_LO: 497 case SOC_COUNTER_NON_DMA_PORT_DROP_BYTE_OBM_LOSSY_HI: 498 case SOC_COUNTER_NON_DMA_PORT_DROP_BYTE_OBM_LOSSLESS0: 499 case SOC_COUNTER_NON_DMA_PORT_DROP_BYTE_OBM_LOSSLESS1: 500 byte_flag = 1; 501 break; 502 case SOC_COUNTER_NON_DMA_PORT_OBM_FC_EVENTS: 503 fc = 1; 504 break; 505 default: 506 return SOC_E_PARAM; 507 } 508 509 switch (non_dma_parent->id) { 510 case SOC_COUNTER_NON_DMA_PORT_DROP_PKT_OBM_LOSSY_LO: 511 case SOC_COUNTER_NON_DMA_PORT_DROP_BYTE_OBM_LOSSY_LO: 512 obm_type = LOSSY_LO; 513 break; 514 case SOC_COUNTER_NON_DMA_PORT_DROP_PKT_OBM_LOSSY_HI: 515 case SOC_COUNTER_NON_DMA_PORT_DROP_BYTE_OBM_LOSSY_HI: 516 obm_type = LOSSY_HI; 517 break; 518 case SOC_COUNTER_NON_DMA_PORT_DROP_PKT_OBM_LOSSLESS0: 519 case SOC_COUNTER_NON_DMA_PORT_DROP_BYTE_OBM_LOSSLESS0: 520 obm_type = LOSSLESS0; 521 break; 522 case SOC_COUNTER_NON_DMA_PORT_DROP_PKT_OBM_LOSSLESS1: 523 case SOC_COUNTER_NON_DMA_PORT_DROP_BYTE_OBM_LOSSLESS1: 524 obm_type = LOSSLESS1; 525 break; 526 } 527 528 parent_base_index = non_dma_parent->base_index; 529 *total_entries = 0; 530 531 for (i = 0; i < extra_ctr_ct; i++) { 532 *non_dma_extra = *non_dma_parent; 533 if (fc) { 534 non_dma_extra->reg = obm_fc_event_regs[i]; 535 } else if (byte_flag == 0) { 536 non_dma_extra->reg = obm_drop_pkt_regs[i][obm_type]; 537 } else { 538 non_dma_extra->reg = obm_drop_byte_regs[i][obm_type]; 539 } 540 non_dma_extra->extra_ctrs = NULL; 541 non_dma_extra->extra_ctr_ct = 0; 542 non_dma_extra->base_index = parent_base_index + *total_entries; 543 non_dma_extra->flags = (non_dma_parent->flags & 544 ~_SOC_COUNTER_NON_DMA_SUBSET_PARENT) | 545 _SOC_COUNTER_NON_DMA_SUBSET_CHILD; 546 547 non_dma_extra->cname = sal_alloc(sal_strlen(non_dma_parent->cname) + 9, 548 "Extra ctrs cname"); 549 550 if (non_dma_extra->cname == NULL) { 551 return SOC_E_MEMORY; 552 } 553 554 if (fc) { 555 sal_sprintf(non_dma_extra->cname, "*OBM%d_FC_EVENTS", i); 556 } else { 557 sal_sprintf(non_dma_extra->cname, "*OBM%d_%s_DRP_%s", 558 i, obm_type_str[obm_type], byte_flag ? "BYTE":"PKT"); 559 } 560 561 non_dma_extra->num_entries = non_dma_extra->entries_per_port * 562 NUM_PIPE(unit); 563 *total_entries += non_dma_extra->num_entries; 564 non_dma_extra += 2; 565 } 566 return SOC_E_NONE; 567 } 568 569 /* Trident3 Counters are of 2 types: 570 * 1. Traditional Non-StatDma 571 * 2. Counter Eviction eligible counters. 572 * 573 * When Counter Eviction is enabled, HW performs Clear on Read on the eviction 574 * enabled counters when a Read is performed. 575 * 576 * When Counter Eviction is disabled, all counters will work as in TD2. 577 */ 578 int 579 soc_counter_helix5_non_dma_init(int unit, int nports, 580 int non_dma_start_index, 581 int *non_dma_entries) 582 { 583 soc_control_t *soc; 584 soc_counter_non_dma_t *non_dma0, *non_dma1, *non_dma2, *temp; 585 int rv = SOC_E_NONE; 586 int num_entries, alloc_size, entry_words, pipe, num_extra_ctr_entries; 587 int pool_count = 0; 588 soc_mem_t child_mem = INVALIDm; 589 uint32 *buf; 590 soc_counter_control_t *soc_ctr_ctrl = SOC_CTR_CTRL(unit); 591 592 if (soc_ctr_ctrl == NULL) { 593 return SOC_E_INIT; 594 } 595 596 soc = SOC_CONTROL(unit); 597 *non_dma_entries = 0; 598 599 /* Registration of Chip specific functions to the Global Counter 600 * control structure. 601 */ 602 soc_ctr_ctrl->get_child_dma = soc_counter_trident3_get_child_dma; 603 soc_ctr_ctrl->dma_config_update = soc_counter_trident3_dma_flags_update; 604 soc_ctr_ctrl->port_obm_info_get = soc_helix5_port_obm_info_get; 605 606 /* EGR_PERQ_XMT_COUNTERSm is the largest table to be DMA'ed */ 607 num_entries = soc_mem_index_count(unit, EGR_PERQ_XMT_COUNTERSm); 608 entry_words = soc_mem_entry_words(unit, EGR_PERQ_XMT_COUNTERSm); 609 alloc_size = NUM_PIPE(unit) * num_entries * sizeof(uint32) * entry_words; 610 611 buf = soc_cm_salloc(unit, alloc_size, "non_dma_counter"); 612 if (buf == NULL) { 613 return SOC_E_MEMORY; 614 } 615 sal_memset(buf, 0, alloc_size); 616 pipe = 0; 617 618 /* EGR_PERQ counters - Control Block 619 * Eviction enabled counter 620 */ 621 non_dma0 = &soc->counter_non_dma[SOC_COUNTER_NON_DMA_EGR_PERQ_XMT_PKT - 622 SOC_COUNTER_NON_DMA_START]; 623 non_dma0->id = SOC_COUNTER_NON_DMA_EGR_PERQ_XMT_PKT; 624 non_dma0->flags = _SOC_COUNTER_NON_DMA_VALID | 625 _SOC_COUNTER_NON_DMA_DO_DMA | 626 _SOC_COUNTER_NON_DMA_ALLOC | 627 _SOC_COUNTER_NON_DMA_CTR_EVICT; 628 629 non_dma0->dma_rate_profile |= _SOC_COUNTER_DMA_RATE_PROFILE_ALL; 630 631 non_dma0->pbmp = PBMP_ALL(unit); 632 non_dma0->base_index = non_dma_start_index + *non_dma_entries; 633 non_dma0->entries_per_port = 48; /* cpu port has max number of queues */ 634 non_dma0->num_entries = 635 NUM_PIPE(unit) * soc_mem_index_count(unit, EGR_PERQ_XMT_COUNTERSm); 636 non_dma0->mem = EGR_PERQ_XMT_COUNTERSm; 637 non_dma0->reg = INVALIDr; 638 non_dma0->field = PACKET_COUNTERf; 639 non_dma0->cname = "MC_PERQ_PKT"; 640 num_entries = soc_mem_index_count(unit, EGR_PERQ_XMT_COUNTERSm); 641 entry_words = soc_mem_entry_words(unit, EGR_PERQ_XMT_COUNTERSm); 642 643 non_dma0->dma_mem[pipe] = SOC_MEM_UNIQUE_ACC(unit, non_dma0->mem)[pipe]; 644 non_dma0->dma_buf[pipe] = &buf[num_entries * entry_words * pipe]; 645 non_dma0->dma_index_max[pipe] = soc_mem_index_max(unit, non_dma0->dma_mem[pipe]); 646 647 *non_dma_entries += non_dma0->num_entries; 648 non_dma1 = &soc->counter_non_dma[SOC_COUNTER_NON_DMA_EGR_PERQ_XMT_BYTE - 649 SOC_COUNTER_NON_DMA_START]; 650 *non_dma1 = *non_dma0; 651 non_dma1->id = SOC_COUNTER_NON_DMA_EGR_PERQ_XMT_BYTE; 652 non_dma1->flags = _SOC_COUNTER_NON_DMA_VALID | 653 _SOC_COUNTER_NON_DMA_CTR_EVICT; 654 non_dma0->dma_rate_profile |= _SOC_COUNTER_DMA_RATE_PROFILE0; 655 non_dma1->base_index = non_dma_start_index + *non_dma_entries; 656 non_dma1->field = BYTE_COUNTERf; 657 non_dma1->cname = "MC_PERQ_BYTE"; 658 *non_dma_entries += non_dma1->num_entries; 659 660 non_dma2 = &soc->counter_non_dma[SOC_COUNTER_NON_DMA_EGR_PERQ_XMT_PKT_UC - 661 SOC_COUNTER_NON_DMA_START]; 662 *non_dma2 = *non_dma0; 663 non_dma2->id = SOC_COUNTER_NON_DMA_EGR_PERQ_XMT_PKT_UC; 664 non_dma2->flags = _SOC_COUNTER_NON_DMA_VALID | 665 _SOC_COUNTER_NON_DMA_CTR_EVICT; 666 non_dma2->dma_rate_profile |= _SOC_COUNTER_DMA_RATE_PROFILE0; 667 non_dma2->pbmp = PBMP_PORT_ALL(unit); 668 non_dma2->entries_per_port = 26; /* Stacking ports have max 26 UC Qs Per port */ 669 non_dma2->num_entries = 0; 670 non_dma2->cname = "UC_PERQ_PKT"; 671 672 non_dma2 = &soc->counter_non_dma[SOC_COUNTER_NON_DMA_EGR_PERQ_XMT_BYTE_UC - 673 SOC_COUNTER_NON_DMA_START]; 674 *non_dma2 = *non_dma1; 675 non_dma2->id = SOC_COUNTER_NON_DMA_EGR_PERQ_XMT_BYTE_UC; 676 non_dma2->flags = _SOC_COUNTER_NON_DMA_VALID | 677 _SOC_COUNTER_NON_DMA_CTR_EVICT; 678 non_dma2->dma_rate_profile |= _SOC_COUNTER_DMA_RATE_PROFILE0; 679 non_dma2->pbmp = PBMP_PORT_ALL(unit); 680 non_dma2->entries_per_port = 26; /* Stacking ports have max 26 UC Qs Per port */ 681 non_dma2->num_entries = 0; 682 non_dma2->cname = "UC_PERQ_BYTE"; 683 /* End of EGR_PERQ counter control block */ 684 685 /* CTR_MC_DROP Counters - Control Block */ 686 non_dma0 = &soc->counter_non_dma[SOC_COUNTER_NON_DMA_COSQ_DROP_PKT - 687 SOC_COUNTER_NON_DMA_START]; 688 non_dma0->id = SOC_COUNTER_NON_DMA_COSQ_DROP_PKT; 689 non_dma0->flags = _SOC_COUNTER_NON_DMA_VALID | 690 _SOC_COUNTER_NON_DMA_DO_DMA | 691 _SOC_COUNTER_NON_DMA_SUBSET_PARENT; 692 non_dma0->pbmp = PBMP_ALL(unit); 693 non_dma0->base_index = non_dma_start_index + *non_dma_entries; 694 non_dma0->entries_per_port = 48; /* 48 for cpu port */ 695 non_dma0->mem = MMU_CTR_MC_DROP_MEMm; 696 697 /* MMU memories with Unique access type have number of entries in base view 698 * set to zero. So, get number of entries from first expanded view 699 */ 700 child_mem = SOC_MEM_UNIQUE_ACC_XPE_PIPE(unit, non_dma0->mem, 0, 0); 701 num_entries = soc_mem_index_max(unit, child_mem) + 1; 702 entry_words = soc_mem_entry_words(unit, non_dma0->mem); 703 non_dma0->num_entries = NUM_PIPE(unit) * num_entries; 704 non_dma0->reg = INVALIDr; 705 non_dma0->field = PKTCNTf; 706 non_dma0->cname = "PERQ_DROP_PKT"; 707 708 non_dma0->dma_mem[pipe] = SOC_MEM_UNIQUE_ACC_XPE_PIPE(unit, non_dma0->mem, 0, pipe); 709 non_dma0->dma_buf[pipe] = &buf[num_entries * entry_words * pipe]; 710 non_dma0->dma_index_max[pipe] = soc_mem_index_max(unit, non_dma0->dma_mem[pipe]); 711 712 non_dma0->extra_ctr_ct = NUM_XPE(unit); 713 /* Incl. buffer for BYTE_CTR. 2x alloc size*/ 714 alloc_size = (non_dma0->extra_ctr_ct << 1) * sizeof(soc_counter_non_dma_t); 715 non_dma0->extra_ctrs = sal_alloc(alloc_size, "non_dma_ctrs_perq_drop_mc"); 716 717 if (non_dma0->extra_ctrs == NULL) { 718 non_dma0->extra_ctr_ct = 0; 719 non_dma0->flags &= ~_SOC_COUNTER_NON_DMA_VALID; 720 return SOC_E_MEMORY; 721 } else { 722 sal_memset(non_dma0->extra_ctrs, 0, alloc_size); 723 rv = soc_counter_trident3_extra_ctrs_init(unit, 724 SOC_COUNTER_NON_DMA_COSQ_DROP_PKT, 725 non_dma0, 726 non_dma0->extra_ctrs, 727 non_dma0->extra_ctr_ct, 728 &num_extra_ctr_entries); 729 if (rv != SOC_E_NONE) { 730 LOG_CLI((BSL_META_U(unit, 731 "ERR: Extra ctrs Init FAILED for id %d\n"), 732 SOC_COUNTER_NON_DMA_COSQ_DROP_PKT - 733 SOC_COUNTER_NON_DMA_START)); 734 } 735 non_dma0->num_entries = num_extra_ctr_entries; 736 } 737 738 *non_dma_entries += non_dma0->num_entries; 739 740 non_dma1 = &soc->counter_non_dma[SOC_COUNTER_NON_DMA_COSQ_DROP_BYTE - 741 SOC_COUNTER_NON_DMA_START]; 742 *non_dma1 = *non_dma0; 743 non_dma1->id = SOC_COUNTER_NON_DMA_COSQ_DROP_BYTE; 744 non_dma1->flags = _SOC_COUNTER_NON_DMA_VALID | 745 _SOC_COUNTER_NON_DMA_SUBSET_PARENT; 746 non_dma1->base_index = non_dma_start_index + *non_dma_entries; 747 non_dma1->field = BYTECNTf; 748 non_dma1->cname = "PERQ_DROP_BYTE"; 749 non_dma1->extra_ctr_ct = NUM_XPE(unit); 750 751 /* Memory for extra ctrs for BYTE_CTRS are done along with PACKET_CTR */ 752 non_dma1->extra_ctrs = non_dma0->extra_ctrs + 1; 753 754 if (non_dma0->extra_ctrs) { 755 rv = soc_counter_trident3_extra_ctrs_init(unit, 756 SOC_COUNTER_NON_DMA_COSQ_DROP_BYTE, 757 non_dma1, 758 non_dma1->extra_ctrs, 759 non_dma1->extra_ctr_ct, 760 &num_extra_ctr_entries); 761 if (rv != SOC_E_NONE) { 762 LOG_CLI((BSL_META_U(unit, 763 "ERR: Extra ctrs Init FAILED for id %d\n"), 764 SOC_COUNTER_NON_DMA_COSQ_DROP_BYTE - 765 SOC_COUNTER_NON_DMA_START)); 766 } 767 } 768 non_dma1->flags = _SOC_COUNTER_NON_DMA_SUBSET_PARENT; 769 *non_dma_entries += non_dma1->num_entries; 770 /* End of CTR_MC_DROP Control Block */ 771 772 /* DROP_PKT_UC Counters - Control Block */ 773 non_dma0 = &soc->counter_non_dma[SOC_COUNTER_NON_DMA_COSQ_DROP_PKT_UC - 774 SOC_COUNTER_NON_DMA_START]; 775 non_dma0->id = SOC_COUNTER_NON_DMA_COSQ_DROP_PKT_UC; 776 non_dma0->flags = _SOC_COUNTER_NON_DMA_VALID | 777 _SOC_COUNTER_NON_DMA_DO_DMA | 778 _SOC_COUNTER_NON_DMA_SUBSET_PARENT; 779 non_dma0->pbmp = PBMP_PORT_ALL(unit); 780 non_dma0->base_index = non_dma_start_index + *non_dma_entries; 781 non_dma0->entries_per_port = 26; /* Stacking ports have max 26 UC Qs Per port */ 782 non_dma0->mem = MMU_CTR_UC_DROP_MEMm; 783 784 /* MMU memories with Unique access type have number of entries in base view 785 * set to zero. So, get number of entries from first expanded view 786 */ 787 child_mem = SOC_MEM_UNIQUE_ACC_XPE_PIPE(unit, non_dma0->mem, 0, 0); 788 num_entries = soc_mem_index_max(unit, child_mem) + 1; 789 entry_words = soc_mem_entry_words(unit, non_dma0->mem); 790 non_dma0->num_entries = NUM_PIPE(unit) * num_entries; 791 non_dma0->reg = INVALIDr; 792 non_dma0->field = PKTCNTf; 793 non_dma0->cname = "PERQ_DROP_PKT_UC"; 794 795 non_dma0->dma_mem[pipe] = SOC_MEM_UNIQUE_ACC_XPE_PIPE(unit, non_dma0->mem, 0, pipe); 796 non_dma0->dma_buf[pipe] = &buf[num_entries * entry_words * pipe]; 797 non_dma0->dma_index_max[pipe] = soc_mem_index_max(unit, non_dma0->dma_mem[pipe]); 798 799 non_dma0->extra_ctr_ct = NUM_XPE(unit); 800 /* Incl. buffer for BYTE_CTR. 2x alloc size*/ 801 alloc_size = (non_dma0->extra_ctr_ct << 1) * sizeof(soc_counter_non_dma_t); 802 non_dma0->extra_ctrs = sal_alloc(alloc_size, "non_dma_ctrs_perq_drop_uc"); 803 804 if (non_dma0->extra_ctrs == NULL) { 805 non_dma0->extra_ctr_ct = 0; 806 non_dma0->flags &= ~_SOC_COUNTER_NON_DMA_VALID; 807 return SOC_E_MEMORY; 808 } else { 809 sal_memset(non_dma0->extra_ctrs, 0, alloc_size); 810 rv = soc_counter_trident3_extra_ctrs_init(unit, 811 SOC_COUNTER_NON_DMA_COSQ_DROP_PKT_UC, 812 non_dma0, 813 non_dma0->extra_ctrs, 814 non_dma0->extra_ctr_ct, 815 &num_extra_ctr_entries); 816 if (rv != SOC_E_NONE) { 817 LOG_CLI((BSL_META_U(unit, 818 "ERR: Extra ctrs Init FAILED for id %d\n"), 819 SOC_COUNTER_NON_DMA_COSQ_DROP_PKT_UC - 820 SOC_COUNTER_NON_DMA_START)); 821 } 822 non_dma0->num_entries = num_extra_ctr_entries; 823 } 824 825 *non_dma_entries += non_dma0->num_entries; 826 827 non_dma1 = &soc->counter_non_dma[SOC_COUNTER_NON_DMA_COSQ_DROP_BYTE_UC - 828 SOC_COUNTER_NON_DMA_START]; 829 *non_dma1 = *non_dma0; 830 non_dma1->id = SOC_COUNTER_NON_DMA_COSQ_DROP_BYTE_UC; 831 non_dma1->flags = _SOC_COUNTER_NON_DMA_VALID | 832 _SOC_COUNTER_NON_DMA_SUBSET_PARENT; 833 non_dma1->base_index = non_dma_start_index + *non_dma_entries; 834 non_dma1->field = BYTECNTf; 835 non_dma1->cname = "PERQ_DROP_BYTE_UC"; 836 non_dma1->extra_ctr_ct = NUM_XPE(unit); 837 838 /* Memory for extra ctrs for BYTE_CTRS are done along with PACKET_CTR */ 839 non_dma1->extra_ctrs = non_dma0->extra_ctrs + 1; 840 841 if (non_dma0->extra_ctrs) 842 { 843 rv = soc_counter_trident3_extra_ctrs_init(unit, 844 SOC_COUNTER_NON_DMA_COSQ_DROP_BYTE_UC, 845 non_dma1, 846 non_dma1->extra_ctrs, 847 non_dma1->extra_ctr_ct, 848 &num_extra_ctr_entries); 849 if (rv != SOC_E_NONE) { 850 LOG_CLI((BSL_META_U(unit, 851 "ERR: Extra ctrs Init FAILED for id %d\n"), 852 SOC_COUNTER_NON_DMA_COSQ_DROP_BYTE_UC - 853 SOC_COUNTER_NON_DMA_START)); 854 } 855 } 856 non_dma1->flags = _SOC_COUNTER_NON_DMA_SUBSET_PARENT; 857 858 *non_dma_entries += non_dma1->num_entries; 859 /* End of DROP_PKT_UC Counters Control Block */ 860 861 /* DROP_PKT_ING Counters - Control Block */ 862 non_dma0 = &soc->counter_non_dma[SOC_COUNTER_NON_DMA_PORT_DROP_PKT_ING - 863 SOC_COUNTER_NON_DMA_START]; 864 non_dma0->id = SOC_COUNTER_NON_DMA_PORT_DROP_PKT_ING; 865 non_dma0->flags = _SOC_COUNTER_NON_DMA_VALID | 866 _SOC_COUNTER_NON_DMA_DO_DMA | 867 _SOC_COUNTER_NON_DMA_SUBSET_PARENT; 868 non_dma0->pbmp = PBMP_ALL(unit); 869 non_dma0->base_index = non_dma_start_index + *non_dma_entries; 870 non_dma0->entries_per_port = 1; 871 non_dma0->mem = MMU_CTR_ING_DROP_MEMm; 872 873 /* MMU memories with Unique access type have number of entries in base view 874 * set to zero. So, get number of entries from first expanded view 875 */ 876 child_mem = SOC_MEM_UNIQUE_ACC_XPE_PIPE(unit, non_dma0->mem, 0, 0); 877 num_entries = soc_mem_index_max(unit, child_mem) + 1; 878 entry_words = soc_mem_entry_words(unit, non_dma0->mem); 879 non_dma0->num_entries = NUM_PIPE(unit) * num_entries; 880 non_dma0->reg = INVALIDr; 881 non_dma0->field = PKTCNTf; 882 non_dma0->cname = "DROP_PKT_ING"; 883 884 non_dma0->dma_mem[pipe] = SOC_MEM_UNIQUE_ACC_XPE_PIPE(unit, non_dma0->mem, 0, pipe); 885 non_dma0->dma_buf[pipe] = &buf[num_entries * entry_words * pipe]; 886 non_dma0->dma_index_max[pipe] = soc_mem_index_max(unit, non_dma0->dma_mem[pipe]); 887 888 non_dma0->extra_ctr_ct = NUM_XPE(unit); 889 /* Incl. buffer for BYTE_CTR. 2x alloc size*/ 890 alloc_size = (non_dma0->extra_ctr_ct << 1) * sizeof(soc_counter_non_dma_t); 891 non_dma0->extra_ctrs = sal_alloc(alloc_size, "non_dma_ctrs_ing_drop"); 892 893 if (non_dma0->extra_ctrs == NULL) { 894 non_dma0->extra_ctr_ct = 0; 895 non_dma0->flags &= ~_SOC_COUNTER_NON_DMA_VALID; 896 return SOC_E_MEMORY; 897 } else { 898 sal_memset(non_dma0->extra_ctrs, 0, alloc_size); 899 rv = soc_counter_trident3_extra_ctrs_init(unit, 900 SOC_COUNTER_NON_DMA_PORT_DROP_PKT_ING, 901 non_dma0, 902 non_dma0->extra_ctrs, 903 non_dma0->extra_ctr_ct, 904 &num_extra_ctr_entries); 905 if (rv != SOC_E_NONE) { 906 LOG_CLI((BSL_META_U(unit, 907 "ERR: Extra ctrs Init FAILED for id %d\n"), 908 SOC_COUNTER_NON_DMA_PORT_DROP_PKT_ING - 909 SOC_COUNTER_NON_DMA_START)); 910 } 911 non_dma0->num_entries = num_extra_ctr_entries; 912 } 913 *non_dma_entries += non_dma0->num_entries; 914 915 non_dma1 = &soc->counter_non_dma[SOC_COUNTER_NON_DMA_PORT_DROP_BYTE_ING - 916 SOC_COUNTER_NON_DMA_START]; 917 *non_dma1 = *non_dma0; 918 non_dma1->id = SOC_COUNTER_NON_DMA_PORT_DROP_BYTE_ING; 919 non_dma1->flags = _SOC_COUNTER_NON_DMA_VALID | 920 _SOC_COUNTER_NON_DMA_SUBSET_PARENT; 921 non_dma1->base_index = non_dma_start_index + *non_dma_entries; 922 non_dma1->field = BYTECNTf; 923 non_dma1->cname = "DROP_BYTE_ING"; 924 non_dma1->extra_ctr_ct = NUM_XPE(unit); 925 926 /* Memory for extra ctrs for BYTE_CTRS are done along with PACKET_CTR */ 927 non_dma1->extra_ctrs = non_dma0->extra_ctrs + 1; 928 929 if (non_dma0->extra_ctrs) { 930 rv = soc_counter_trident3_extra_ctrs_init(unit, 931 SOC_COUNTER_NON_DMA_PORT_DROP_BYTE_ING, 932 non_dma1, 933 non_dma1->extra_ctrs, 934 non_dma1->extra_ctr_ct, 935 &num_extra_ctr_entries); 936 if (rv != SOC_E_NONE) { 937 LOG_CLI((BSL_META_U(unit, 938 "ERR: Extra ctrs Init FAILED for id %d\n"), 939 SOC_COUNTER_NON_DMA_PORT_DROP_BYTE_ING - 940 SOC_COUNTER_NON_DMA_START)); 941 } 942 } 943 non_dma1->flags = _SOC_COUNTER_NON_DMA_SUBSET_PARENT; 944 945 *non_dma_entries += non_dma1->num_entries; 946 /* End of DROP_PKT_ING Counters - Control Block */ 947 948 /* Color Drop Counter */ 949 /* Control block for wred counter */ 950 non_dma0 = &soc->counter_non_dma[SOC_COUNTER_NON_DMA_PORT_WRED_PKT_RED - 951 SOC_COUNTER_NON_DMA_START]; 952 non_dma0->id = SOC_COUNTER_NON_DMA_PORT_WRED_PKT_RED; 953 non_dma0->flags = _SOC_COUNTER_NON_DMA_VALID | 954 _SOC_COUNTER_NON_DMA_DO_DMA | 955 _SOC_COUNTER_NON_DMA_SUBSET_PARENT; 956 non_dma0->pbmp = PBMP_ALL(unit); 957 non_dma0->base_index = non_dma_start_index + *non_dma_entries; 958 non_dma0->entries_per_port = 1; 959 non_dma0->mem = MMU_CTR_COLOR_DROP_MEMm; 960 non_dma0->reg = INVALIDr; 961 non_dma0->cname = "WRED_PKT_RED"; 962 non_dma0->field = PKTCNTf; 963 num_entries = 72; /* 1 per port, 72 per pipe */ 964 non_dma0->num_entries = NUM_PIPE(unit) * num_entries; 965 entry_words = soc_mem_entry_words(unit, non_dma0->mem); 966 967 non_dma0->dma_mem[pipe] = SOC_MEM_UNIQUE_ACC_XPE_PIPE(unit, non_dma0->mem, 0, pipe); 968 non_dma0->dma_buf[pipe] = &buf[num_entries * entry_words * pipe]; 969 non_dma0->dma_index_min[pipe] = 0; 970 non_dma0->dma_index_max[pipe] = 71; 971 non_dma0->extra_ctr_ct = NUM_XPE(unit); 972 /* Buffer allocated for 2x alloc size. Though 2nd half is NOT used. */ 973 974 alloc_size = (non_dma0->extra_ctr_ct << 1) * sizeof(soc_counter_non_dma_t); 975 non_dma0->extra_ctrs = sal_alloc(alloc_size, "non_dma_ctrs_wred_pkt_red"); 976 977 /* 978 * Below represents how Extra cntrs are arranged for wred red pkt, wred 979 * yellow pkt, wred green pkt, drop pkt red, drop pkt yellow counters. 980 * 981 * n = NUM_XPE 982 * 983 * [0] [2] [2n-2] 984 * ------ ------ ------ 985 * | || |...| | 986 * | PKT || PKT |...| PKT | 987 * | [0] || [1] |...| [n-1]| 988 * ------ ------ ... ------ 989 * | || |...| | 990 * | N/A || N/A |...| N/A | 991 * | [0] || [1] |...| [n-1]| 992 * ------ ------ ------ 993 * [1] [3] [2n-1] 994 */ 995 996 if (non_dma0->extra_ctrs == NULL) { 997 non_dma0->extra_ctr_ct = 0; 998 non_dma0->flags &= ~_SOC_COUNTER_NON_DMA_VALID; 999 return SOC_E_MEMORY; 1000 } else { 1001 sal_memset(non_dma0->extra_ctrs, 0, alloc_size); 1002 rv = soc_counter_trident3_extra_ctrs_init(unit, 1003 SOC_COUNTER_NON_DMA_PORT_WRED_PKT_RED, 1004 non_dma0, 1005 non_dma0->extra_ctrs, 1006 non_dma0->extra_ctr_ct, 1007 &num_extra_ctr_entries); 1008 if (rv != SOC_E_NONE) { 1009 LOG_CLI((BSL_META_U(unit, 1010 "ERR: Extra ctrs Init FAILED for id %d\n"), 1011 SOC_COUNTER_NON_DMA_PORT_WRED_PKT_RED - 1012 SOC_COUNTER_NON_DMA_START)); 1013 } 1014 non_dma0->num_entries = num_extra_ctr_entries; 1015 } 1016 *non_dma_entries += non_dma0->num_entries; 1017 1018 /* Control block for wred yellow counter */ 1019 non_dma1 = &soc->counter_non_dma[SOC_COUNTER_NON_DMA_PORT_WRED_PKT_YELLOW - 1020 SOC_COUNTER_NON_DMA_START]; 1021 *non_dma1 = *non_dma0; 1022 non_dma1->id = SOC_COUNTER_NON_DMA_PORT_WRED_PKT_YELLOW; 1023 non_dma1->base_index = non_dma_start_index + *non_dma_entries; 1024 non_dma1->cname = "WRED_PKT_YEL"; 1025 1026 non_dma1->dma_buf[pipe] = &buf[num_entries * entry_words * pipe]; 1027 non_dma1->dma_index_min[pipe] = 72; 1028 non_dma1->dma_index_max[pipe] = 143; 1029 /* Buffer allocated for 2x alloc size. Though 2nd half is NOT used. */ 1030 non_dma1->extra_ctrs = sal_alloc(alloc_size, "non_dma_ctrs_wred_pkt_yel"); 1031 1032 if (non_dma1->extra_ctrs == NULL) { 1033 non_dma1->extra_ctr_ct = 0; 1034 non_dma1->flags &= ~_SOC_COUNTER_NON_DMA_VALID; 1035 return SOC_E_MEMORY; 1036 } else { 1037 sal_memset(non_dma1->extra_ctrs, 0, alloc_size); 1038 rv = soc_counter_trident3_extra_ctrs_init(unit, 1039 SOC_COUNTER_NON_DMA_PORT_WRED_PKT_YELLOW, 1040 non_dma1, 1041 non_dma1->extra_ctrs, 1042 non_dma1->extra_ctr_ct, 1043 &num_extra_ctr_entries); 1044 if (rv != SOC_E_NONE) { 1045 LOG_CLI((BSL_META_U(unit, 1046 "ERR: Extra ctrs Init FAILED for id %d\n"), 1047 SOC_COUNTER_NON_DMA_PORT_WRED_PKT_YELLOW - 1048 SOC_COUNTER_NON_DMA_START)); 1049 } 1050 non_dma1->num_entries = num_extra_ctr_entries; 1051 } 1052 *non_dma_entries += non_dma1->num_entries; 1053 1054 /* Control block for wred green counter */ 1055 non_dma1 = &soc->counter_non_dma[SOC_COUNTER_NON_DMA_PORT_WRED_PKT_GREEN - 1056 SOC_COUNTER_NON_DMA_START]; 1057 *non_dma1 = *non_dma0; 1058 non_dma1->id = SOC_COUNTER_NON_DMA_PORT_WRED_PKT_GREEN; 1059 non_dma1->base_index = non_dma_start_index + *non_dma_entries; 1060 non_dma1->cname = "WRED_PKT_GRE"; 1061 1062 non_dma1->dma_buf[pipe] = &buf[num_entries * entry_words * pipe]; 1063 non_dma1->dma_index_min[pipe] = 144; 1064 non_dma1->dma_index_max[pipe] = 215; 1065 non_dma1->extra_ctrs = sal_alloc(alloc_size, "non_dma_ctrs_wred_pkt_gre"); 1066 1067 if (non_dma1->extra_ctrs == NULL) { 1068 non_dma1->extra_ctr_ct = 0; 1069 non_dma1->flags &= ~_SOC_COUNTER_NON_DMA_VALID; 1070 return SOC_E_MEMORY; 1071 } else { 1072 sal_memset(non_dma1->extra_ctrs, 0, alloc_size); 1073 rv = soc_counter_trident3_extra_ctrs_init(unit, 1074 SOC_COUNTER_NON_DMA_PORT_WRED_PKT_GREEN, 1075 non_dma1, 1076 non_dma1->extra_ctrs, 1077 non_dma1->extra_ctr_ct, 1078 &num_extra_ctr_entries); 1079 if (rv != SOC_E_NONE) { 1080 LOG_CLI((BSL_META_U(unit, 1081 "ERR: Extra ctrs Init FAILED for id %d\n"), 1082 SOC_COUNTER_NON_DMA_PORT_WRED_PKT_GREEN - 1083 SOC_COUNTER_NON_DMA_START)); 1084 } 1085 non_dma1->num_entries = num_extra_ctr_entries; 1086 } 1087 *non_dma_entries += non_dma1->num_entries; 1088 1089 /* Control block for red drop counter */ 1090 non_dma1 = &soc->counter_non_dma[SOC_COUNTER_NON_DMA_PORT_DROP_PKT_RED - 1091 SOC_COUNTER_NON_DMA_START]; 1092 *non_dma1 = *non_dma0; 1093 non_dma1->id = SOC_COUNTER_NON_DMA_PORT_DROP_PKT_RED; 1094 non_dma1->base_index = non_dma_start_index + *non_dma_entries; 1095 non_dma1->cname = "DROP_PKT_RED"; 1096 1097 non_dma1->dma_buf[pipe] = &buf[num_entries * entry_words * pipe]; 1098 non_dma1->dma_index_min[pipe] = 216; 1099 non_dma1->dma_index_max[pipe] = 287; 1100 non_dma1->extra_ctrs = sal_alloc(alloc_size, "non_dma_ctrs_drop_pkt_red"); 1101 1102 if (non_dma1->extra_ctrs == NULL) { 1103 non_dma1->extra_ctr_ct = 0; 1104 non_dma1->flags &= ~_SOC_COUNTER_NON_DMA_VALID; 1105 return SOC_E_MEMORY; 1106 } else { 1107 sal_memset(non_dma1->extra_ctrs, 0, alloc_size); 1108 rv = soc_counter_trident3_extra_ctrs_init(unit, 1109 SOC_COUNTER_NON_DMA_PORT_DROP_PKT_RED, 1110 non_dma1, 1111 non_dma1->extra_ctrs, 1112 non_dma1->extra_ctr_ct, 1113 &num_extra_ctr_entries); 1114 if (rv != SOC_E_NONE) { 1115 LOG_CLI((BSL_META_U(unit, 1116 "ERR: Extra ctrs Init FAILED for id %d\n"), 1117 SOC_COUNTER_NON_DMA_PORT_DROP_PKT_RED - 1118 SOC_COUNTER_NON_DMA_START)); 1119 } 1120 non_dma1->num_entries = num_extra_ctr_entries; 1121 } 1122 1123 *non_dma_entries += non_dma1->num_entries; 1124 1125 /* Control block for yellow drop counter */ 1126 non_dma1 = &soc->counter_non_dma[SOC_COUNTER_NON_DMA_PORT_DROP_PKT_YELLOW - 1127 SOC_COUNTER_NON_DMA_START]; 1128 *non_dma1 = *non_dma0; 1129 non_dma1->id = SOC_COUNTER_NON_DMA_PORT_DROP_PKT_YELLOW; 1130 non_dma1->base_index = non_dma_start_index + *non_dma_entries; 1131 non_dma1->cname = "DROP_PKT_YEL"; 1132 1133 non_dma1->dma_buf[pipe] = &buf[num_entries * entry_words * pipe]; 1134 non_dma1->dma_index_min[pipe] = 288; 1135 non_dma1->dma_index_max[pipe] = 359; 1136 non_dma1->extra_ctrs = sal_alloc(alloc_size, "non_dma_ctrs_drop_pkt_yel"); 1137 1138 if (non_dma1->extra_ctrs == NULL) { 1139 non_dma1->extra_ctr_ct = 0; 1140 non_dma1->flags &= ~_SOC_COUNTER_NON_DMA_VALID; 1141 return SOC_E_MEMORY; 1142 } else { 1143 sal_memset(non_dma1->extra_ctrs, 0, alloc_size); 1144 rv = soc_counter_trident3_extra_ctrs_init(unit, 1145 SOC_COUNTER_NON_DMA_PORT_DROP_PKT_YELLOW, 1146 non_dma1, 1147 non_dma1->extra_ctrs, 1148 non_dma1->extra_ctr_ct, 1149 &num_extra_ctr_entries); 1150 if (rv != SOC_E_NONE) { 1151 LOG_CLI((BSL_META_U(unit, 1152 "ERR: Extra ctrs Init FAILED for id %d\n"), 1153 SOC_COUNTER_NON_DMA_PORT_DROP_PKT_YELLOW - 1154 SOC_COUNTER_NON_DMA_START)); 1155 } 1156 non_dma1->num_entries = num_extra_ctr_entries; 1157 } 1158 *non_dma_entries += non_dma1->num_entries; 1159 1160 /* End Color Drop Counter */ 1161 1162 /* MC Queue Count Counters - Control Block */ 1163 non_dma0 = &soc->counter_non_dma[SOC_COUNTER_NON_DMA_QUEUE_PEAK - 1164 SOC_COUNTER_NON_DMA_START]; 1165 non_dma0->id = SOC_COUNTER_NON_DMA_QUEUE_PEAK; 1166 1167 non_dma0->flags = _SOC_COUNTER_NON_DMA_VALID | 1168 _SOC_COUNTER_NON_DMA_DO_DMA | 1169 _SOC_COUNTER_NON_DMA_PEAK | 1170 _SOC_COUNTER_NON_DMA_SUBSET_PARENT; 1171 non_dma0->pbmp = PBMP_ALL(unit); 1172 non_dma0->base_index = non_dma_start_index + *non_dma_entries; 1173 non_dma0->entries_per_port = 48; /* 48 for cpu port */ 1174 non_dma0->mem = MMU_THDM_DB_QUEUE_COUNTm; 1175 1176 /* MMU memories with Unique access type have number of entries in base view 1177 * set to zero. So, get number of entries from first expanded view 1178 */ 1179 child_mem = SOC_MEM_UNIQUE_ACC_XPE_PIPE(unit, non_dma0->mem, 0, 0); 1180 num_entries = soc_mem_index_max(unit, child_mem) + 1; 1181 entry_words = soc_mem_entry_words(unit, non_dma0->mem); 1182 non_dma0->num_entries = NUM_PIPE(unit) * num_entries; 1183 non_dma0->reg = INVALIDr; 1184 non_dma0->field = SHARED_COUNTf; 1185 non_dma0->cname = "QUEUE_PEAK"; 1186 non_dma0->dma_mem[pipe] = SOC_MEM_UNIQUE_ACC_XPE_PIPE(unit, non_dma0->mem, 0, pipe); 1187 non_dma0->dma_buf[pipe] = &buf[num_entries * entry_words * pipe]; 1188 non_dma0->dma_index_max[pipe] = soc_mem_index_max(unit, non_dma0->dma_mem[pipe]); 1189 1190 non_dma0->extra_ctr_ct = NUM_XPE(unit); 1191 alloc_size = (non_dma0->extra_ctr_ct << 1) * sizeof(soc_counter_non_dma_t); 1192 non_dma0->extra_ctrs = sal_alloc(alloc_size, "non_dma_ctrs_mc_q_ct"); 1193 1194 if (non_dma0->extra_ctrs == NULL) { 1195 non_dma0->extra_ctr_ct = 0; 1196 non_dma0->flags &= ~_SOC_COUNTER_NON_DMA_VALID; 1197 return SOC_E_MEMORY; 1198 } else { 1199 sal_memset(non_dma0->extra_ctrs, 0, alloc_size); 1200 rv = soc_counter_trident3_extra_ctrs_init(unit, 1201 SOC_COUNTER_NON_DMA_QUEUE_PEAK, 1202 non_dma0, 1203 non_dma0->extra_ctrs, 1204 non_dma0->extra_ctr_ct, 1205 &num_extra_ctr_entries); 1206 if (rv != SOC_E_NONE) { 1207 LOG_CLI((BSL_META_U(unit, 1208 "ERR: Extra ctrs Init FAILED for id %d\n"), 1209 SOC_COUNTER_NON_DMA_QUEUE_PEAK - 1210 SOC_COUNTER_NON_DMA_START)); 1211 } 1212 non_dma0->num_entries = num_extra_ctr_entries; 1213 } 1214 1215 *non_dma_entries += non_dma0->num_entries; 1216 non_dma2 = &soc->counter_non_dma[SOC_COUNTER_NON_DMA_QUEUE_CURRENT - 1217 SOC_COUNTER_NON_DMA_START]; 1218 *non_dma2 = *non_dma0; 1219 non_dma2->id = SOC_COUNTER_NON_DMA_QUEUE_CURRENT; 1220 non_dma2->flags = _SOC_COUNTER_NON_DMA_VALID | 1221 _SOC_COUNTER_NON_DMA_CURRENT | 1222 _SOC_COUNTER_NON_DMA_SUBSET_PARENT; 1223 non_dma2->cname = "QUEUE_CUR"; 1224 /* End of MC Queue Count Counters - Control Block */ 1225 1226 /* UC Queue Count Counters - Control Block */ 1227 non_dma0 = &soc->counter_non_dma[SOC_COUNTER_NON_DMA_UC_QUEUE_PEAK - 1228 SOC_COUNTER_NON_DMA_START]; 1229 non_dma0->id = SOC_COUNTER_NON_DMA_UC_QUEUE_PEAK; 1230 1231 non_dma0->flags = _SOC_COUNTER_NON_DMA_VALID | 1232 _SOC_COUNTER_NON_DMA_DO_DMA | 1233 _SOC_COUNTER_NON_DMA_PEAK | 1234 _SOC_COUNTER_NON_DMA_SUBSET_PARENT; 1235 non_dma0->pbmp = PBMP_PORT_ALL(unit); /* No UC queue for CPU/LB ports */ 1236 non_dma0->base_index = non_dma_start_index + *non_dma_entries; 1237 non_dma0->entries_per_port = 26; 1238 non_dma0->mem = MMU_THDU_COUNTER_QUEUEm; 1239 1240 /* MMU memories with Unique access type have number of entries in base view 1241 * set to zero. So, get number of entries from first expanded view 1242 */ 1243 child_mem = SOC_MEM_UNIQUE_ACC_XPE_PIPE(unit, non_dma0->mem, 0, 0); 1244 num_entries = soc_mem_index_max(unit, child_mem) + 1; 1245 entry_words = soc_mem_entry_words(unit, non_dma0->mem); 1246 non_dma0->num_entries = NUM_PIPE(unit) * num_entries; 1247 non_dma0->reg = INVALIDr; 1248 non_dma0->field = SHARED_COUNTf; 1249 non_dma0->cname = "UC_QUEUE_PEAK"; 1250 non_dma0->dma_mem[pipe] = SOC_MEM_UNIQUE_ACC_XPE_PIPE(unit, non_dma0->mem, 0, pipe); 1251 non_dma0->dma_buf[pipe] = &buf[num_entries * entry_words * pipe]; 1252 non_dma0->dma_index_max[pipe] = soc_mem_index_max(unit, non_dma0->dma_mem[pipe]); 1253 1254 non_dma0->extra_ctr_ct = NUM_XPE(unit); 1255 alloc_size = (non_dma0->extra_ctr_ct << 1) * sizeof(soc_counter_non_dma_t); 1256 non_dma0->extra_ctrs = sal_alloc(alloc_size, "non_dma_ctrs_uc_q_ct"); 1257 1258 if (non_dma0->extra_ctrs == NULL) { 1259 non_dma0->extra_ctr_ct = 0; 1260 non_dma0->flags &= ~_SOC_COUNTER_NON_DMA_VALID; 1261 return SOC_E_MEMORY; 1262 } else { 1263 sal_memset(non_dma0->extra_ctrs, 0, alloc_size); 1264 rv = soc_counter_trident3_extra_ctrs_init(unit, 1265 SOC_COUNTER_NON_DMA_UC_QUEUE_PEAK, 1266 non_dma0, 1267 non_dma0->extra_ctrs, 1268 non_dma0->extra_ctr_ct, 1269 &num_extra_ctr_entries); 1270 if (rv != SOC_E_NONE) { 1271 LOG_CLI((BSL_META_U(unit, 1272 "ERR: Extra ctrs Init FAILED for id %d\n"), 1273 SOC_COUNTER_NON_DMA_UC_QUEUE_PEAK - 1274 SOC_COUNTER_NON_DMA_START)); 1275 } 1276 non_dma0->num_entries = num_extra_ctr_entries; 1277 } 1278 1279 *non_dma_entries += non_dma0->num_entries; 1280 non_dma2 = &soc->counter_non_dma[SOC_COUNTER_NON_DMA_UC_QUEUE_CURRENT - 1281 SOC_COUNTER_NON_DMA_START]; 1282 *non_dma2 = *non_dma0; 1283 non_dma2->id = SOC_COUNTER_NON_DMA_UC_QUEUE_CURRENT; 1284 non_dma2->flags = _SOC_COUNTER_NON_DMA_VALID | 1285 _SOC_COUNTER_NON_DMA_CURRENT | 1286 _SOC_COUNTER_NON_DMA_SUBSET_PARENT; 1287 non_dma2->cname = "UC_QUEUE_CUR"; 1288 /* End of UC Queue Count Counters - Control Block */ 1289 1290 /* RQ Drop Counters - Control Block */ 1291 non_dma0 = &soc->counter_non_dma[SOC_COUNTER_NON_DMA_DROP_RQ_PKT - 1292 SOC_COUNTER_NON_DMA_START]; 1293 non_dma0->flags = _SOC_COUNTER_NON_DMA_VALID | 1294 _SOC_COUNTER_NON_DMA_DO_DMA; 1295 non_dma0->id = SOC_COUNTER_NON_DMA_DROP_RQ_PKT; 1296 SOC_PBMP_CLEAR(non_dma0->pbmp); /* Port = 0 */ 1297 non_dma0->base_index = non_dma_start_index + *non_dma_entries; 1298 non_dma0->entries_per_port = 0; 1299 non_dma0->num_entries = 11; 1300 non_dma0->mem = INVALIDm; 1301 non_dma0->reg = DROP_PKT_CNT_RQE_PKT_64r; 1302 non_dma0->field = PKTCNTf; 1303 non_dma0->cname = "RQ_DROP_PKT"; 1304 non_dma0->dma_buf[0] = buf; 1305 *non_dma_entries += non_dma0->num_entries; 1306 1307 non_dma1 = &soc->counter_non_dma[SOC_COUNTER_NON_DMA_DROP_RQ_BYTE - 1308 SOC_COUNTER_NON_DMA_START]; 1309 *non_dma1 = *non_dma0; 1310 non_dma1->id = SOC_COUNTER_NON_DMA_DROP_RQ_BYTE; 1311 non_dma1->base_index = non_dma_start_index + *non_dma_entries; 1312 non_dma1->reg = DROP_PKT_CNT_RQE_BYTE_64r; 1313 non_dma1->field = BYTECNTf; 1314 non_dma1->cname = "RQ_DROP_BYTE"; 1315 *non_dma_entries += non_dma1->num_entries; 1316 1317 non_dma1 = &soc->counter_non_dma[SOC_COUNTER_NON_DMA_DROP_RQ_PKT_YELLOW - 1318 SOC_COUNTER_NON_DMA_START]; 1319 *non_dma1 = *non_dma0; 1320 non_dma1->id = SOC_COUNTER_NON_DMA_DROP_RQ_PKT_YELLOW; 1321 non_dma1->base_index = non_dma_start_index + *non_dma_entries; 1322 non_dma1->reg = DROP_PKT_CNT_RQE_YEL_64r; 1323 non_dma1->field = PKTCNTf; 1324 non_dma1->cname = "RQ_DROP_PKT_YEL"; 1325 *non_dma_entries += non_dma1->num_entries; 1326 1327 non_dma1 = &soc->counter_non_dma[SOC_COUNTER_NON_DMA_DROP_RQ_PKT_RED - 1328 SOC_COUNTER_NON_DMA_START]; 1329 *non_dma1 = *non_dma0; 1330 non_dma1->id = SOC_COUNTER_NON_DMA_DROP_RQ_PKT_RED; 1331 non_dma1->base_index = non_dma_start_index + *non_dma_entries; 1332 non_dma1->reg = DROP_PKT_CNT_RQE_RED_64r; 1333 non_dma1->field = PKTCNTf; 1334 non_dma1->cname = "RQ_DROP_PKT_RED"; 1335 *non_dma_entries += non_dma1->num_entries; 1336 /* End of RQ Drop Counters - Control Block */ 1337 1338 /* Pool Peak Counters - Control Block */ 1339 non_dma0 = &soc->counter_non_dma[SOC_COUNTER_NON_DMA_POOL_PEAK - 1340 SOC_COUNTER_NON_DMA_START]; 1341 non_dma0->flags = _SOC_COUNTER_NON_DMA_VALID | 1342 _SOC_COUNTER_NON_DMA_PEAK; 1343 non_dma0->id = SOC_COUNTER_NON_DMA_POOL_PEAK; 1344 SOC_PBMP_CLEAR(non_dma0->pbmp); /* Port = 0 */ 1345 non_dma0->base_index = non_dma_start_index + *non_dma_entries; 1346 non_dma0->entries_per_port = 0; 1347 non_dma0->num_entries = 4; 1348 non_dma0->mem = INVALIDm; 1349 non_dma0->reg = THDI_POOL_SHARED_COUNT_SPr; 1350 non_dma0->field = TOTAL_BUFFER_COUNTf; 1351 non_dma0->cname = "POOL_PEAK"; 1352 non_dma0->dma_buf[0] = buf; 1353 *non_dma_entries += non_dma0->num_entries; 1354 1355 non_dma2 = &soc->counter_non_dma[SOC_COUNTER_NON_DMA_POOL_CURRENT - 1356 SOC_COUNTER_NON_DMA_START]; 1357 *non_dma2 = *non_dma0; 1358 non_dma2->id = SOC_COUNTER_NON_DMA_POOL_CURRENT; 1359 non_dma2->flags = _SOC_COUNTER_NON_DMA_VALID | 1360 _SOC_COUNTER_NON_DMA_CURRENT; 1361 non_dma2->cname = "POOL_CUR"; 1362 /* End of Pool Peak Counters - Control Block */ 1363 1364 /* PG Counters - Control Block */ 1365 non_dma0 = &soc->counter_non_dma[SOC_COUNTER_NON_DMA_PG_MIN_PEAK - 1366 SOC_COUNTER_NON_DMA_START]; 1367 non_dma0->id = SOC_COUNTER_NON_DMA_PG_MIN_PEAK; 1368 non_dma0->flags = _SOC_COUNTER_NON_DMA_VALID | 1369 _SOC_COUNTER_NON_DMA_DO_DMA | 1370 _SOC_COUNTER_NON_DMA_PEAK; 1371 non_dma0->pbmp = PBMP_ALL(unit); 1372 non_dma0->base_index = non_dma_start_index + *non_dma_entries; 1373 non_dma0->entries_per_port = 8; 1374 non_dma0->mem = THDI_PORT_PG_CNTRS_RT1m; 1375 1376 /* MMU memories with Unique access type have number of entries in base view 1377 * set to zero. So, get number of entries from first expanded view 1378 */ 1379 child_mem = SOC_MEM_UNIQUE_ACC_XPE_PIPE(unit, non_dma0->mem, 0, 0); 1380 num_entries = soc_mem_index_max(unit, child_mem) + 1; 1381 entry_words = soc_mem_entry_words(unit, non_dma0->mem); 1382 non_dma0->num_entries = NUM_PIPE(unit) * num_entries; 1383 non_dma0->reg = INVALIDr; 1384 non_dma0->field = PG_MIN_COUNTf; 1385 non_dma0->cname = "PG_MIN_PEAK"; 1386 1387 non_dma0->dma_mem[pipe] = SOC_MEM_UNIQUE_ACC_XPE_PIPE(unit, non_dma0->mem, 0, pipe); 1388 non_dma0->dma_buf[pipe] = &buf[num_entries * entry_words * pipe]; 1389 non_dma0->dma_index_max[pipe] = soc_mem_index_max(unit, non_dma0->dma_mem[pipe]); 1390 *non_dma_entries += non_dma0->num_entries; 1391 non_dma2 = &soc->counter_non_dma[SOC_COUNTER_NON_DMA_PG_MIN_CURRENT - 1392 SOC_COUNTER_NON_DMA_START]; 1393 *non_dma2 = *non_dma0; 1394 non_dma2->id = SOC_COUNTER_NON_DMA_PG_MIN_CURRENT; 1395 non_dma2->flags = _SOC_COUNTER_NON_DMA_VALID | 1396 _SOC_COUNTER_NON_DMA_CURRENT; 1397 non_dma2->cname = "PG_MIN_CUR"; 1398 1399 non_dma1 = &soc->counter_non_dma[SOC_COUNTER_NON_DMA_PG_SHARED_PEAK - 1400 SOC_COUNTER_NON_DMA_START]; 1401 *non_dma1 = *non_dma0; 1402 non_dma1->id = SOC_COUNTER_NON_DMA_PG_SHARED_PEAK; 1403 non_dma1->flags = _SOC_COUNTER_NON_DMA_VALID | 1404 _SOC_COUNTER_NON_DMA_PEAK; 1405 non_dma1->cname = "PG_SHARED_PEAK"; 1406 non_dma1->field = PG_SHARED_COUNTf; 1407 non_dma1->base_index = non_dma_start_index + *non_dma_entries; 1408 *non_dma_entries += non_dma1->num_entries; 1409 1410 non_dma2 = &soc->counter_non_dma[SOC_COUNTER_NON_DMA_PG_SHARED_CURRENT - 1411 SOC_COUNTER_NON_DMA_START]; 1412 *non_dma2 = *non_dma1; 1413 non_dma2->id = SOC_COUNTER_NON_DMA_PG_SHARED_CURRENT; 1414 non_dma2->flags = _SOC_COUNTER_NON_DMA_CURRENT | 1415 _SOC_COUNTER_NON_DMA_VALID; 1416 non_dma2->cname = "PG_SHARED_CUR"; 1417 1418 non_dma0 = &soc->counter_non_dma[SOC_COUNTER_NON_DMA_PG_HDRM_PEAK - 1419 SOC_COUNTER_NON_DMA_START]; 1420 non_dma0->id = SOC_COUNTER_NON_DMA_PG_HDRM_PEAK; 1421 non_dma0->flags = _SOC_COUNTER_NON_DMA_VALID | 1422 _SOC_COUNTER_NON_DMA_DO_DMA | 1423 _SOC_COUNTER_NON_DMA_PEAK; 1424 non_dma0->pbmp = PBMP_ALL(unit); 1425 non_dma0->base_index = non_dma_start_index + *non_dma_entries; 1426 non_dma0->entries_per_port = 8; 1427 non_dma0->mem = THDI_PORT_PG_CNTRS_RT2m; 1428 1429 /* MMU memories with Unique access type have number of entries in base view 1430 * set to zero. So, get number of entries from first expanded view 1431 */ 1432 child_mem = SOC_MEM_UNIQUE_ACC_XPE_PIPE(unit, non_dma0->mem, 0, 0); 1433 num_entries = soc_mem_index_max(unit, child_mem) + 1; 1434 entry_words = soc_mem_entry_words(unit, non_dma0->mem); 1435 non_dma0->num_entries = NUM_PIPE(unit) * num_entries; 1436 non_dma0->reg = INVALIDr; 1437 non_dma0->field = PG_HDRM_COUNTf; 1438 non_dma0->cname = "PG_HDRM_PEAK"; 1439 1440 non_dma0->dma_mem[pipe] = SOC_MEM_UNIQUE_ACC_XPE_PIPE(unit, non_dma0->mem, 0, pipe); 1441 non_dma0->dma_buf[pipe] = &buf[num_entries * entry_words * pipe]; 1442 non_dma0->dma_index_max[pipe] = soc_mem_index_max(unit, non_dma0->dma_mem[pipe]); 1443 *non_dma_entries += non_dma0->num_entries; 1444 1445 non_dma2 = &soc->counter_non_dma[SOC_COUNTER_NON_DMA_PG_HDRM_CURRENT - 1446 SOC_COUNTER_NON_DMA_START]; 1447 *non_dma2 = *non_dma0; 1448 non_dma2->id = SOC_COUNTER_NON_DMA_PG_HDRM_CURRENT; 1449 non_dma2->flags = _SOC_COUNTER_NON_DMA_VALID | 1450 _SOC_COUNTER_NON_DMA_CURRENT; 1451 non_dma2->cname = "PG_HDRM_CUR"; 1452 /* End of PG Counters - Control Block */ 1453 1454 /* ING_FLEX counters - Control Block 1455 * Eviction enabled counters 1456 */ 1457 non_dma0 = &soc->counter_non_dma[SOC_COUNTER_NON_DMA_ING_FLEX_PKT - 1458 SOC_COUNTER_NON_DMA_START]; 1459 non_dma0->id = SOC_COUNTER_NON_DMA_ING_FLEX_PKT; 1460 non_dma0->flags = _SOC_COUNTER_NON_DMA_VALID | 1461 _SOC_COUNTER_NON_DMA_DO_DMA | 1462 _SOC_COUNTER_NON_DMA_SUBSET_PARENT; 1463 1464 /* Clear on Read Flag set if eviction is enabled */ 1465 non_dma0->flags |= _SOC_COUNTER_NON_DMA_CTR_EVICT; 1466 non_dma0->flags |= _SOC_COUNTER_NON_DMA_NO_SHOW_C; 1467 SOC_PBMP_CLEAR(non_dma0->pbmp); 1468 non_dma0->base_index = non_dma_start_index + *non_dma_entries; 1469 non_dma0->entries_per_port = 0; 1470 pool_count = 20; 1471 non_dma0->num_entries = 1472 pool_count * NUM_PIPE(unit) * 1473 soc_mem_index_count(unit, ING_FLEX_CTR_COUNTER_TABLE_0m); 1474 non_dma0->mem = ING_FLEX_CTR_COUNTER_TABLE_0m; 1475 non_dma0->reg = INVALIDr; 1476 non_dma0->field = PACKET_COUNTERf; 1477 non_dma0->cname = "ING_FLEX_PKT"; 1478 1479 num_entries = soc_mem_index_count(unit, ING_FLEX_CTR_COUNTER_TABLE_0m); 1480 entry_words = soc_mem_entry_words(unit, ING_FLEX_CTR_COUNTER_TABLE_0m); 1481 non_dma0->dma_buf[pipe] = &buf[num_entries * entry_words * pipe]; 1482 non_dma0->extra_ctr_ct = pool_count; 1483 /* Incl. buffer for BYTE_CTR. 2x alloc size*/ 1484 alloc_size = (non_dma0->extra_ctr_ct << 1) * sizeof(soc_counter_non_dma_t); 1485 non_dma0->extra_ctrs = sal_alloc(alloc_size, "non_dma_ctrs_ing_flex"); 1486 1487 if (non_dma0->extra_ctrs == NULL) { 1488 non_dma0->extra_ctr_ct = 0; 1489 non_dma0->flags &= ~_SOC_COUNTER_NON_DMA_VALID; 1490 return SOC_E_MEMORY; 1491 } else { 1492 sal_memset(non_dma0->extra_ctrs, 0, alloc_size); 1493 rv = soc_counter_trident3_extra_ctrs_init 1494 (unit, 1495 SOC_COUNTER_NON_DMA_ING_FLEX_PKT, 1496 non_dma0, 1497 non_dma0->extra_ctrs, 1498 non_dma0->extra_ctr_ct, 1499 &num_extra_ctr_entries); 1500 if (rv != SOC_E_NONE) { 1501 LOG_CLI((BSL_META_U(unit, 1502 "ERR: Extra ctrs Init FAILED for id %d\n"), 1503 SOC_COUNTER_NON_DMA_ING_FLEX_PKT - 1504 SOC_COUNTER_NON_DMA_START)); 1505 } 1506 non_dma0->num_entries = num_extra_ctr_entries; 1507 } 1508 *non_dma_entries += non_dma0->num_entries; 1509 1510 non_dma1 = &soc->counter_non_dma[SOC_COUNTER_NON_DMA_ING_FLEX_BYTE - 1511 SOC_COUNTER_NON_DMA_START]; 1512 *non_dma1 = *non_dma0; 1513 non_dma1->id = SOC_COUNTER_NON_DMA_ING_FLEX_BYTE; 1514 1515 non_dma1->flags = _SOC_COUNTER_NON_DMA_VALID | 1516 _SOC_COUNTER_NON_DMA_SUBSET_PARENT; 1517 1518 /* Clear on Read Flag set if eviction is enabled */ 1519 non_dma1->flags |= _SOC_COUNTER_NON_DMA_CTR_EVICT; 1520 non_dma1->flags |= _SOC_COUNTER_NON_DMA_NO_SHOW_C; 1521 non_dma1->base_index = non_dma_start_index + *non_dma_entries; 1522 non_dma1->field = BYTE_COUNTERf; 1523 non_dma1->cname = "ING_FLEX_BYTE"; 1524 non_dma1->extra_ctr_ct = pool_count; /* Taken care by PKT_CTR */ 1525 1526 /* Memory for extra ctrs for BYTE_CTRS are done along with PACKET_CTR */ 1527 non_dma1->extra_ctrs = non_dma0->extra_ctrs + 1; 1528 1529 if (non_dma0->extra_ctrs) 1530 { 1531 rv = soc_counter_trident3_extra_ctrs_init(unit, 1532 SOC_COUNTER_NON_DMA_ING_FLEX_BYTE, 1533 non_dma1, 1534 non_dma1->extra_ctrs, 1535 non_dma1->extra_ctr_ct, 1536 &num_extra_ctr_entries); 1537 if (rv != SOC_E_NONE) { 1538 LOG_CLI((BSL_META_U(unit, 1539 "ERR: Extra ctrs Init FAILED for id %d\n"), 1540 SOC_COUNTER_NON_DMA_ING_FLEX_BYTE - 1541 SOC_COUNTER_NON_DMA_START)); 1542 } 1543 } 1544 1545 non_dma1->flags = _SOC_COUNTER_NON_DMA_SUBSET_PARENT; 1546 non_dma1->flags |= _SOC_COUNTER_NON_DMA_NO_SHOW_C; 1547 *non_dma_entries += non_dma1->num_entries; 1548 1549 /* End of ING_FLEX counters - Control Block */ 1550 1551 /* EGR_FLEX Counters - Control Block */ 1552 non_dma0 = &soc->counter_non_dma[SOC_COUNTER_NON_DMA_EGR_FLEX_PKT - 1553 SOC_COUNTER_NON_DMA_START]; 1554 non_dma0->id = SOC_COUNTER_NON_DMA_EGR_FLEX_PKT; 1555 non_dma0->flags = _SOC_COUNTER_NON_DMA_VALID | 1556 _SOC_COUNTER_NON_DMA_DO_DMA | 1557 _SOC_COUNTER_NON_DMA_SUBSET_PARENT; 1558 1559 /* Clear on Read Flag set if eviction is enabled */ 1560 non_dma0->flags |= _SOC_COUNTER_NON_DMA_CTR_EVICT; 1561 non_dma0->flags |= _SOC_COUNTER_NON_DMA_NO_SHOW_C; 1562 SOC_PBMP_CLEAR(non_dma0->pbmp); 1563 non_dma0->base_index = non_dma_start_index + *non_dma_entries; 1564 pool_count = 4; 1565 non_dma0->entries_per_port = 0; 1566 non_dma0->mem = EGR_FLEX_CTR_COUNTER_TABLE_0m; 1567 non_dma0->reg = INVALIDr; 1568 non_dma0->field = PACKET_COUNTERf; 1569 non_dma0->cname = "EGR_FLEX_PKT"; 1570 1571 num_entries = soc_mem_index_count(unit, EGR_FLEX_CTR_COUNTER_TABLE_0m); 1572 entry_words = soc_mem_entry_words(unit, EGR_FLEX_CTR_COUNTER_TABLE_0m); 1573 non_dma0->dma_buf[pipe] = &buf[num_entries * entry_words * pipe]; 1574 1575 non_dma0->extra_ctr_ct = pool_count; 1576 1577 /* Incl. buffer for BYTE_CTR. 2x alloc size*/ 1578 alloc_size = (non_dma0->extra_ctr_ct << 1) * sizeof(soc_counter_non_dma_t); 1579 non_dma0->extra_ctrs = sal_alloc(alloc_size, "non_dma_ctrs_ing_flex"); 1580 1581 if (non_dma0->extra_ctrs == NULL) { 1582 non_dma0->extra_ctr_ct = 0; 1583 non_dma0->flags &= ~_SOC_COUNTER_NON_DMA_VALID; 1584 return SOC_E_MEMORY; 1585 } else { 1586 sal_memset(non_dma0->extra_ctrs, 0, alloc_size); 1587 rv = soc_counter_trident3_extra_ctrs_init(unit, 1588 SOC_COUNTER_NON_DMA_EGR_FLEX_PKT, 1589 non_dma0, 1590 non_dma0->extra_ctrs, 1591 non_dma0->extra_ctr_ct, 1592 &num_extra_ctr_entries); 1593 if (rv != SOC_E_NONE) { 1594 LOG_CLI((BSL_META_U(unit, 1595 "ERR: Extra ctrs Init FAILED for id %d\n"), 1596 SOC_COUNTER_NON_DMA_EGR_FLEX_PKT - 1597 SOC_COUNTER_NON_DMA_START)); 1598 } 1599 non_dma0->num_entries = num_extra_ctr_entries; 1600 } 1601 1602 *non_dma_entries += non_dma0->num_entries; 1603 1604 non_dma1 = &soc->counter_non_dma[SOC_COUNTER_NON_DMA_EGR_FLEX_BYTE - 1605 SOC_COUNTER_NON_DMA_START]; 1606 *non_dma1 = *non_dma0; 1607 non_dma1->id = SOC_COUNTER_NON_DMA_EGR_FLEX_BYTE; 1608 1609 non_dma1->flags = _SOC_COUNTER_NON_DMA_VALID | 1610 _SOC_COUNTER_NON_DMA_SUBSET_PARENT; 1611 /* Clear on Read Flag set if eviction is enabled */ 1612 non_dma1->flags |= _SOC_COUNTER_NON_DMA_CTR_EVICT; 1613 non_dma1->flags |= _SOC_COUNTER_NON_DMA_NO_SHOW_C; 1614 non_dma1->base_index = non_dma_start_index + *non_dma_entries; 1615 non_dma1->field = BYTE_COUNTERf; 1616 non_dma1->cname = "EGR_FLEX_BYTE"; 1617 non_dma1->extra_ctr_ct = pool_count; /* Taken care by PKT_CTR */ 1618 1619 /* Memory for extra ctrs for BYTE_CTRS are done along with PACKET_CTR */ 1620 non_dma1->extra_ctrs = non_dma0->extra_ctrs + 1; 1621 1622 if (non_dma0->extra_ctrs) 1623 { 1624 rv = soc_counter_trident3_extra_ctrs_init(unit, 1625 SOC_COUNTER_NON_DMA_EGR_FLEX_BYTE, 1626 non_dma1, 1627 non_dma1->extra_ctrs, 1628 non_dma1->extra_ctr_ct, 1629 &num_extra_ctr_entries); 1630 if (rv != SOC_E_NONE) { 1631 LOG_CLI((BSL_META_U(unit, 1632 "ERR: Extra ctrs Init FAILED for id %d\n"), 1633 SOC_COUNTER_NON_DMA_EGR_FLEX_BYTE - 1634 SOC_COUNTER_NON_DMA_START)); 1635 } 1636 } 1637 non_dma1->flags = _SOC_COUNTER_NON_DMA_SUBSET_PARENT; 1638 non_dma1->flags |= _SOC_COUNTER_NON_DMA_NO_SHOW_C; 1639 1640 *non_dma_entries += non_dma1->num_entries; 1641 1642 /* End of EGR_FLEX Counters - Control Block */ 1643 1644 /* EFP Counters - Control Block */ 1645 non_dma0 = &soc->counter_non_dma[SOC_COUNTER_NON_DMA_EFP_PKT - 1646 SOC_COUNTER_NON_DMA_START]; 1647 non_dma0->id = SOC_COUNTER_NON_DMA_EFP_PKT; 1648 non_dma0->flags = _SOC_COUNTER_NON_DMA_VALID | 1649 _SOC_COUNTER_NON_DMA_DO_DMA; 1650 non_dma0->flags |= _SOC_COUNTER_NON_DMA_CTR_EVICT; 1651 non_dma0->flags |= _SOC_COUNTER_NON_DMA_NO_SHOW_C; 1652 1653 SOC_PBMP_CLEAR(non_dma0->pbmp); 1654 non_dma0->base_index = non_dma_start_index + *non_dma_entries; 1655 non_dma0->entries_per_port = 0; 1656 non_dma0->num_entries = 1657 NUM_PIPE(unit) * soc_mem_index_count(unit, EFP_COUNTER_TABLEm); 1658 non_dma0->mem = EFP_COUNTER_TABLEm; 1659 non_dma0->reg = INVALIDr; 1660 non_dma0->field = PACKET_COUNTERf; 1661 non_dma0->cname = "EFP_PKT"; 1662 1663 num_entries = soc_mem_index_count(unit, EFP_COUNTER_TABLEm); 1664 entry_words = soc_mem_entry_words(unit, EFP_COUNTER_TABLEm); 1665 1666 non_dma0->dma_mem[pipe] = SOC_MEM_UNIQUE_ACC(unit, non_dma0->mem)[pipe]; 1667 non_dma0->dma_buf[pipe] = &buf[num_entries * entry_words * pipe]; 1668 non_dma0->dma_index_max[pipe] = soc_mem_index_max(unit, non_dma0->dma_mem[pipe]); 1669 1670 *non_dma_entries += non_dma0->num_entries; 1671 1672 non_dma1 = &soc->counter_non_dma[SOC_COUNTER_NON_DMA_EFP_BYTE - 1673 SOC_COUNTER_NON_DMA_START]; 1674 *non_dma1 = *non_dma0; 1675 non_dma1->id = SOC_COUNTER_NON_DMA_EFP_BYTE; 1676 non_dma1->flags = _SOC_COUNTER_NON_DMA_VALID; 1677 non_dma1->flags |= _SOC_COUNTER_NON_DMA_CTR_EVICT; 1678 non_dma1->flags |= _SOC_COUNTER_NON_DMA_NO_SHOW_C; 1679 1680 non_dma1->base_index = non_dma_start_index + *non_dma_entries; 1681 non_dma1->field = BYTE_COUNTERf; 1682 non_dma1->cname = "EFP_BYTE"; 1683 *non_dma_entries += non_dma1->num_entries; 1684 /* End of EFP Counters - Control Block */ 1685 1686 /* Control block for Ingress sFlow counters */ 1687 non_dma0 = &soc->counter_non_dma[SOC_COUNTER_NON_DMA_SFLOW_ING_PKT - 1688 SOC_COUNTER_NON_DMA_START]; 1689 non_dma0->id = SOC_COUNTER_NON_DMA_SFLOW_ING_PKT; 1690 non_dma0->flags = _SOC_COUNTER_NON_DMA_VALID | _SOC_COUNTER_NON_DMA_DO_DMA 1691 | _SOC_COUNTER_NON_DMA_SUBSET_PARENT; 1692 non_dma0->pbmp = PBMP_PORT_ALL(unit); 1693 non_dma0->base_index = non_dma_start_index + *non_dma_entries; 1694 non_dma0->entries_per_port = 1; 1695 non_dma0->mem = SFLOW_ING_DATA_SOURCEm; 1696 1697 num_entries = soc_mem_index_count(unit, SFLOW_ING_DATA_SOURCEm); 1698 entry_words = soc_mem_entry_words(unit, non_dma0->mem); 1699 non_dma0->num_entries = SOC_SFLOW_CTR_TYPE_COUNT * num_entries; 1700 non_dma0->reg = INVALIDr; 1701 non_dma0->cname = "SFLOW_ING_PKT"; 1702 non_dma0->field = SAMPLE_POOLf; 1703 non_dma0->dma_buf[0] = &buf[0]; 1704 1705 non_dma0->extra_ctr_ct = SOC_SFLOW_CTR_TYPE_COUNT; 1706 1707 /* Buffer allocated for 2x alloc size. Though 2nd half is NOT used. 1708 * This memory supports BYTE Count, but not implemented yet. So space 1709 * reserved. 1710 */ 1711 alloc_size = (non_dma0->extra_ctr_ct << 1) * sizeof(soc_counter_non_dma_t); 1712 non_dma0->extra_ctrs = sal_alloc(alloc_size, "non_dma_ctrs_sflow_ing"); 1713 1714 /* 1715 * Below represents how Extra cntrs are arranged 1716 * for sFlow counters. 1717 * 1718 * -------------------------- 1719 * [0] | SAMPLE_POOL [0] | 1720 * -------------------------- 1721 * [1] | N/A [0] | 1722 * -------------------------- 1723 * [2] | SAMPLE_POOL_SNAPSHOT [0] | 1724 * -------------------------- 1725 * [3] | N/A [0] | 1726 * -------------------------- 1727 * [4] | SAMPLE_COUNT [0] | 1728 * -------------------------- 1729 * [5] | N/A [0] | 1730 * -------------------------- 1731 */ 1732 1733 if (non_dma0->extra_ctrs == NULL) { 1734 non_dma0->extra_ctr_ct = 0; 1735 non_dma0->flags &= ~_SOC_COUNTER_NON_DMA_VALID; 1736 return SOC_E_MEMORY; 1737 } else { 1738 sal_memset(non_dma0->extra_ctrs, 0, alloc_size); 1739 rv = soc_counter_td3_extra_sflow_ctrs_init(unit, 1740 non_dma0, 1741 non_dma0->extra_ctrs, 1742 non_dma0->extra_ctr_ct, 1743 &num_extra_ctr_entries); 1744 if (rv != SOC_E_NONE) { 1745 LOG_CLI((BSL_META_U(unit, 1746 "ERR: Extra ctrs Init FAILED for id %d\n"), 1747 SOC_COUNTER_NON_DMA_SFLOW_ING_PKT - 1748 SOC_COUNTER_NON_DMA_START)); 1749 } 1750 non_dma0->num_entries = num_extra_ctr_entries; 1751 } 1752 *non_dma_entries += non_dma0->num_entries; 1753 1754 /* Control block for Flex sFlow counters */ 1755 non_dma0 = &soc->counter_non_dma[SOC_COUNTER_NON_DMA_SFLOW_FLEX_PKT - 1756 SOC_COUNTER_NON_DMA_START]; 1757 non_dma0->id = SOC_COUNTER_NON_DMA_SFLOW_FLEX_PKT; 1758 non_dma0->flags = _SOC_COUNTER_NON_DMA_VALID | _SOC_COUNTER_NON_DMA_DO_DMA 1759 | _SOC_COUNTER_NON_DMA_SUBSET_PARENT; 1760 non_dma0->pbmp = PBMP_PORT_ALL(unit); 1761 non_dma0->base_index = non_dma_start_index + *non_dma_entries; 1762 non_dma0->entries_per_port = 1; 1763 non_dma0->mem = SFLOW_ING_FLEX_DATA_SOURCEm; 1764 1765 num_entries = soc_mem_index_count(unit, SFLOW_ING_FLEX_DATA_SOURCEm); 1766 entry_words = soc_mem_entry_words(unit, non_dma0->mem); 1767 non_dma0->num_entries = SOC_SFLOW_CTR_TYPE_COUNT * num_entries; 1768 non_dma0->reg = INVALIDr; 1769 non_dma0->cname = "SFLOW_FLEX_PKT"; 1770 non_dma0->field = SAMPLE_POOLf; 1771 non_dma0->dma_buf[0] = &buf[0]; 1772 1773 non_dma0->extra_ctr_ct = SOC_SFLOW_CTR_TYPE_COUNT; 1774 1775 /* Buffer allocated for 2x alloc size. Though 2nd half is NOT used. 1776 * This memory supports BYTE Count, but not implemented yet. So space 1777 * reserved. 1778 */ 1779 alloc_size = (non_dma0->extra_ctr_ct << 1) * sizeof(soc_counter_non_dma_t); 1780 non_dma0->extra_ctrs = sal_alloc(alloc_size, "non_dma_ctrs_sflow_flex"); 1781 1782 if (non_dma0->extra_ctrs == NULL) { 1783 non_dma0->extra_ctr_ct = 0; 1784 non_dma0->flags &= ~_SOC_COUNTER_NON_DMA_VALID; 1785 return SOC_E_MEMORY; 1786 } else { 1787 sal_memset(non_dma0->extra_ctrs, 0, alloc_size); 1788 rv = soc_counter_td3_extra_sflow_ctrs_init(unit, 1789 non_dma0, 1790 non_dma0->extra_ctrs, 1791 non_dma0->extra_ctr_ct, 1792 &num_extra_ctr_entries); 1793 if (rv != SOC_E_NONE) { 1794 LOG_CLI((BSL_META_U(unit, 1795 "ERR: Extra ctrs Init FAILED for id %d\n"), 1796 SOC_COUNTER_NON_DMA_SFLOW_FLEX_PKT - 1797 SOC_COUNTER_NON_DMA_START)); 1798 } 1799 non_dma0->num_entries = num_extra_ctr_entries; 1800 } 1801 *non_dma_entries += non_dma0->num_entries; 1802 1803 /* Control block for IDB OBM counters */ 1804 /* Lossy LO drop counters - Pkt Counters */ 1805 non_dma0 = 1806 &soc->counter_non_dma[SOC_COUNTER_NON_DMA_PORT_DROP_PKT_OBM_LOSSY_LO - 1807 SOC_COUNTER_NON_DMA_START]; 1808 non_dma0->id = SOC_COUNTER_NON_DMA_PORT_DROP_PKT_OBM_LOSSY_LO; 1809 non_dma0->base_index = non_dma_start_index + *non_dma_entries; 1810 non_dma0->reg = IDB_OBM0_LOSSY_LO_PKT_DROP_COUNTr; 1811 non_dma0->cname = "OBM_LOSSY_LO_DRP_PKT"; 1812 1813 /* Common across all OBM structures */ 1814 non_dma0->flags = _SOC_COUNTER_NON_DMA_VALID | 1815 _SOC_COUNTER_NON_DMA_OBM; 1816 /* Use Parent-Child model to cover all 10 OBMs */ 1817 non_dma0->flags |= _SOC_COUNTER_NON_DMA_SUBSET_PARENT; 1818 non_dma0->pbmp = PBMP_PORT_ALL(unit); 1819 non_dma0->entries_per_port = 4; 1820 non_dma0->num_entries = 4 * NUM_PIPE(unit); 1821 non_dma0->mem = INVALIDm; 1822 non_dma0->field = COUNTERf; 1823 non_dma0->dma_buf[0] = &buf[0]; 1824 1825 /* 1826 * Below represents how Extra cntrs are arranged 1827 * for OBM 0-15 Drop Counters. 1828 * n = NUM_OBMs (16) 1829 * 1830 * [0] [2] [2n-2] 1831 * ------ ------ ------ 1832 * | || |...| | 1833 * | PKT || PKT |...| PKT | 1834 * | [0] || [1] |...| [n-1]| 1835 * ------ ------ ... ------ 1836 * | || |...| | 1837 * | BYTE || BYTE |...| BYTE | 1838 * | [0] || [1] |...| [n-1]| 1839 * ------ ------ ------ 1840 * [1] [3] [2n-1] 1841 */ 1842 /* 10 OBMs for each PORTMACRO; 4 ports in each OBM; 1843 * IDB_OBM0_LOSSY_LO_PKT_DROP_COUNTr [0-2] 1844 * IDB_OBM0_Q_LOSSY_LO_PKT_DROP_COUNT [0-3] 1845 * IDB_OBM0_48_LOSSY_LO_PKT_DROP_COUNT [0-2] 1846 */ 1847 non_dma0->extra_ctr_ct = _HX5_OBMS_PER_PIPE; /* 10 OBMs per Pipe */ 1848 alloc_size = (non_dma0->extra_ctr_ct << 1) * sizeof(soc_counter_non_dma_t); 1849 temp = non_dma0->extra_ctrs = sal_alloc(alloc_size, 1850 "non_dma_ctrs_obm_lossy_lo"); 1851 1852 if (non_dma0->extra_ctrs == NULL) { 1853 non_dma0->extra_ctr_ct = 0; 1854 non_dma0->flags &= ~_SOC_COUNTER_NON_DMA_VALID; 1855 return SOC_E_MEMORY; 1856 } else { 1857 sal_memset(non_dma0->extra_ctrs, 0, alloc_size); 1858 rv = soc_counter_helix5_extra_obm_ctrs_init(unit, 1859 non_dma0, 1860 non_dma0->extra_ctrs, 1861 non_dma0->extra_ctr_ct, 1862 &num_extra_ctr_entries); 1863 if (rv != SOC_E_NONE) { 1864 LOG_CLI((BSL_META_U(unit, 1865 "ERR: Extra ctrs Init FAILED for id %d\n"), 1866 non_dma0->id - SOC_COUNTER_NON_DMA_START)); 1867 } 1868 non_dma0->num_entries = num_extra_ctr_entries; 1869 } 1870 *non_dma_entries += non_dma0->num_entries; 1871 1872 /* Lossy LO drop counters - Byte Counters */ 1873 non_dma1 = 1874 &soc->counter_non_dma[SOC_COUNTER_NON_DMA_PORT_DROP_BYTE_OBM_LOSSY_LO - 1875 SOC_COUNTER_NON_DMA_START]; 1876 *non_dma1 = *non_dma0; 1877 non_dma1->id = SOC_COUNTER_NON_DMA_PORT_DROP_BYTE_OBM_LOSSY_LO; 1878 non_dma1->base_index = non_dma_start_index + *non_dma_entries; 1879 non_dma1->reg = IDB_OBM0_LOSSY_LO_BYTE_DROP_COUNTr; 1880 non_dma1->field = COUNTERf; 1881 non_dma1->cname = "OBM_LOSSY_LO_DRP_BYTE"; 1882 1883 /* Memory for extra ctrs for BYTE_CTRS are done along with PACKET_CTR */ 1884 non_dma1->extra_ctrs = temp + 1; 1885 if (non_dma1->extra_ctrs) { 1886 rv = soc_counter_helix5_extra_obm_ctrs_init(unit, 1887 non_dma1, 1888 non_dma1->extra_ctrs, 1889 non_dma1->extra_ctr_ct, 1890 &num_extra_ctr_entries); 1891 if (rv != SOC_E_NONE) { 1892 LOG_CLI((BSL_META_U(unit, 1893 "ERR: Extra ctrs Init FAILED for id %d\n"), 1894 non_dma1->id - SOC_COUNTER_NON_DMA_START)); 1895 } 1896 } 1897 *non_dma_entries += non_dma1->num_entries; 1898 1899 /* Lossy HI drop counters - Packet Counters */ 1900 non_dma1 = 1901 &soc->counter_non_dma[SOC_COUNTER_NON_DMA_PORT_DROP_PKT_OBM_LOSSY_HI - 1902 SOC_COUNTER_NON_DMA_START]; 1903 *non_dma1 = *non_dma0; 1904 non_dma1->id = SOC_COUNTER_NON_DMA_PORT_DROP_PKT_OBM_LOSSY_HI; 1905 non_dma1->base_index = non_dma_start_index + *non_dma_entries; 1906 non_dma1->reg = IDB_OBM0_LOSSY_HI_PKT_DROP_COUNTr; 1907 non_dma1->cname = "OBM_LOSSY_HI_DRP_PKT"; 1908 1909 temp = non_dma1->extra_ctrs = sal_alloc(alloc_size, 1910 "non_dma_ctrs_obm_lossy_hi"); 1911 1912 if (non_dma1->extra_ctrs == NULL) { 1913 non_dma1->extra_ctr_ct = 0; 1914 non_dma1->flags &= ~_SOC_COUNTER_NON_DMA_VALID; 1915 return SOC_E_MEMORY; 1916 } else { 1917 sal_memset(non_dma1->extra_ctrs, 0, alloc_size); 1918 rv = soc_counter_helix5_extra_obm_ctrs_init(unit, 1919 non_dma1, 1920 non_dma1->extra_ctrs, 1921 non_dma1->extra_ctr_ct, 1922 &num_extra_ctr_entries); 1923 if (rv != SOC_E_NONE) { 1924 LOG_CLI((BSL_META_U(unit, 1925 "ERR: Extra ctrs Init FAILED for id %d\n"), 1926 non_dma1->id - SOC_COUNTER_NON_DMA_START)); 1927 } 1928 non_dma1->num_entries = num_extra_ctr_entries; 1929 } 1930 *non_dma_entries += non_dma1->num_entries; 1931 1932 1933 /* Lossy HI drop counters - Byte Counters */ 1934 non_dma1 = 1935 &soc->counter_non_dma[SOC_COUNTER_NON_DMA_PORT_DROP_BYTE_OBM_LOSSY_HI - 1936 SOC_COUNTER_NON_DMA_START]; 1937 *non_dma1 = *non_dma0; 1938 non_dma1->id = SOC_COUNTER_NON_DMA_PORT_DROP_BYTE_OBM_LOSSY_HI; 1939 non_dma1->base_index = non_dma_start_index + *non_dma_entries; 1940 non_dma1->reg = IDB_OBM0_LOSSY_HI_BYTE_DROP_COUNTr; 1941 non_dma1->field = COUNTERf; 1942 non_dma1->cname = "OBM_LOSSY_HI_DRP_BYTE"; 1943 1944 /* Memory for extra ctrs for BYTE_CTRS are done along with PACKET_CTR */ 1945 non_dma1->extra_ctrs = temp + 1; 1946 if (non_dma1->extra_ctrs) { 1947 rv = soc_counter_helix5_extra_obm_ctrs_init(unit, 1948 non_dma1, 1949 non_dma1->extra_ctrs, 1950 non_dma1->extra_ctr_ct, 1951 &num_extra_ctr_entries); 1952 if (rv != SOC_E_NONE) { 1953 LOG_CLI((BSL_META_U(unit, 1954 "ERR: Extra ctrs Init FAILED for id %d\n"), 1955 non_dma1->id - SOC_COUNTER_NON_DMA_START)); 1956 } 1957 } 1958 *non_dma_entries += non_dma1->num_entries; 1959 1960 1961 /* Lossless0 drop counters - Packet Counters */ 1962 non_dma1 = 1963 &soc->counter_non_dma[SOC_COUNTER_NON_DMA_PORT_DROP_PKT_OBM_LOSSLESS0 - 1964 SOC_COUNTER_NON_DMA_START]; 1965 *non_dma1 = *non_dma0; 1966 non_dma1->id = SOC_COUNTER_NON_DMA_PORT_DROP_PKT_OBM_LOSSLESS0; 1967 non_dma1->base_index = non_dma_start_index + *non_dma_entries; 1968 non_dma1->reg = IDB_OBM0_LOSSLESS0_PKT_DROP_COUNTr; 1969 non_dma1->cname = "OBM_LOSSLESS0_DRP_PKT"; 1970 1971 temp = non_dma1->extra_ctrs = sal_alloc(alloc_size, 1972 "non_dma_ctrs_obm_lossless0"); 1973 1974 if (non_dma1->extra_ctrs == NULL) { 1975 non_dma1->extra_ctr_ct = 0; 1976 non_dma1->flags &= ~_SOC_COUNTER_NON_DMA_VALID; 1977 return SOC_E_MEMORY; 1978 } else { 1979 sal_memset(non_dma1->extra_ctrs, 0, alloc_size); 1980 rv = soc_counter_helix5_extra_obm_ctrs_init(unit, 1981 non_dma1, 1982 non_dma1->extra_ctrs, 1983 non_dma1->extra_ctr_ct, 1984 &num_extra_ctr_entries); 1985 if (rv != SOC_E_NONE) { 1986 LOG_CLI((BSL_META_U(unit, 1987 "ERR: Extra ctrs Init FAILED for id %d\n"), 1988 non_dma1->id - SOC_COUNTER_NON_DMA_START)); 1989 } 1990 non_dma1->num_entries = num_extra_ctr_entries; 1991 } 1992 *non_dma_entries += non_dma1->num_entries; 1993 1994 /* Lossless0 drop counters - Byte Counters */ 1995 non_dma1 = 1996 &soc->counter_non_dma[SOC_COUNTER_NON_DMA_PORT_DROP_BYTE_OBM_LOSSLESS0 - 1997 SOC_COUNTER_NON_DMA_START]; 1998 *non_dma1 = *non_dma0; 1999 non_dma1->id = SOC_COUNTER_NON_DMA_PORT_DROP_BYTE_OBM_LOSSLESS0; 2000 non_dma1->base_index = non_dma_start_index + *non_dma_entries; 2001 non_dma1->reg = IDB_OBM0_LOSSLESS0_BYTE_DROP_COUNTr; 2002 non_dma1->field = COUNTERf; 2003 non_dma1->cname = "OBM_LOSSLESS0_DRP_BYTE"; 2004 2005 /* Memory for extra ctrs for BYTE_CTRS are done along with PACKET_CTR */ 2006 non_dma1->extra_ctrs = temp + 1; 2007 if (non_dma1->extra_ctrs) { 2008 rv = soc_counter_helix5_extra_obm_ctrs_init(unit, 2009 non_dma1, 2010 non_dma1->extra_ctrs, 2011 non_dma1->extra_ctr_ct, 2012 &num_extra_ctr_entries); 2013 if (rv != SOC_E_NONE) { 2014 LOG_CLI((BSL_META_U(unit, 2015 "ERR: Extra ctrs Init FAILED for id %d\n"), 2016 non_dma1->id - SOC_COUNTER_NON_DMA_START)); 2017 } 2018 } 2019 *non_dma_entries += non_dma1->num_entries; 2020 2021 /* Lossless1 drop counters - Packet counters */ 2022 non_dma1 = 2023 &soc->counter_non_dma[SOC_COUNTER_NON_DMA_PORT_DROP_PKT_OBM_LOSSLESS1 - 2024 SOC_COUNTER_NON_DMA_START]; 2025 *non_dma1 = *non_dma0; 2026 non_dma1->id = SOC_COUNTER_NON_DMA_PORT_DROP_PKT_OBM_LOSSLESS1; 2027 non_dma1->base_index = non_dma_start_index + *non_dma_entries; 2028 non_dma1->reg = IDB_OBM0_LOSSLESS1_PKT_DROP_COUNTr; 2029 non_dma1->cname = "OBM_LOSSLESS1_DRP_PKT"; 2030 2031 temp = non_dma1->extra_ctrs = sal_alloc(alloc_size, 2032 "non_dma_ctrs_obm_lossless1"); 2033 2034 if (non_dma1->extra_ctrs == NULL) { 2035 non_dma1->extra_ctr_ct = 0; 2036 non_dma1->flags &= ~_SOC_COUNTER_NON_DMA_VALID; 2037 return SOC_E_MEMORY; 2038 } else { 2039 sal_memset(non_dma1->extra_ctrs, 0, alloc_size); 2040 rv = soc_counter_helix5_extra_obm_ctrs_init(unit, 2041 non_dma1, 2042 non_dma1->extra_ctrs, 2043 non_dma1->extra_ctr_ct, 2044 &num_extra_ctr_entries); 2045 if (rv != SOC_E_NONE) { 2046 LOG_CLI((BSL_META_U(unit, 2047 "ERR: Extra ctrs Init FAILED for id %d\n"), 2048 non_dma1->id - SOC_COUNTER_NON_DMA_START)); 2049 } 2050 non_dma1->num_entries = num_extra_ctr_entries; 2051 } 2052 *non_dma_entries += non_dma1->num_entries; 2053 2054 /* Lossless1 drop counters - Byte Counters */ 2055 non_dma1 = 2056 &soc->counter_non_dma[SOC_COUNTER_NON_DMA_PORT_DROP_BYTE_OBM_LOSSLESS1 - 2057 SOC_COUNTER_NON_DMA_START]; 2058 *non_dma1 = *non_dma0; 2059 non_dma1->id = SOC_COUNTER_NON_DMA_PORT_DROP_BYTE_OBM_LOSSLESS1; 2060 non_dma1->base_index = non_dma_start_index + *non_dma_entries; 2061 non_dma1->reg = IDB_OBM0_LOSSLESS1_BYTE_DROP_COUNTr; 2062 non_dma1->field = COUNTERf; 2063 non_dma1->cname = "OBM_LOSSLESS1_DRP_BYTE"; 2064 2065 /* Memory for extra ctrs for BYTE_CTRS are done along with PACKET_CTR */ 2066 non_dma1->extra_ctrs = temp + 1; 2067 if (non_dma1->extra_ctrs) { 2068 rv = soc_counter_helix5_extra_obm_ctrs_init(unit, 2069 non_dma1, 2070 non_dma1->extra_ctrs, 2071 non_dma1->extra_ctr_ct, 2072 &num_extra_ctr_entries); 2073 if (rv != SOC_E_NONE) { 2074 LOG_CLI((BSL_META_U(unit, 2075 "ERR: Extra ctrs Init FAILED for id %d\n"), 2076 non_dma1->id - SOC_COUNTER_NON_DMA_START)); 2077 } 2078 } 2079 *non_dma_entries += non_dma1->num_entries; 2080 2081 /* FC event counters */ 2082 non_dma1 = 2083 &soc->counter_non_dma[SOC_COUNTER_NON_DMA_PORT_OBM_FC_EVENTS - 2084 SOC_COUNTER_NON_DMA_START]; 2085 *non_dma1 = *non_dma0; 2086 non_dma1->id = SOC_COUNTER_NON_DMA_PORT_OBM_FC_EVENTS; 2087 non_dma1->base_index = non_dma_start_index + *non_dma_entries; 2088 non_dma1->reg = IDB_OBM0_FLOW_CONTROL_EVENT_COUNTr; 2089 non_dma1->field = COUNTERf; 2090 non_dma1->cname = "OBM_FC_EVENTS"; 2091 2092 temp = non_dma1->extra_ctrs = sal_alloc(alloc_size, 2093 "non_dma_ctrs_obm_fc"); 2094 2095 if (non_dma1->extra_ctrs == NULL) { 2096 non_dma1->extra_ctr_ct = 0; 2097 non_dma1->flags &= ~_SOC_COUNTER_NON_DMA_VALID; 2098 return SOC_E_MEMORY; 2099 } else { 2100 sal_memset(non_dma1->extra_ctrs, 0, alloc_size); 2101 rv = soc_counter_helix5_extra_obm_ctrs_init(unit, 2102 non_dma1, 2103 non_dma1->extra_ctrs, 2104 non_dma1->extra_ctr_ct, 2105 &num_extra_ctr_entries); 2106 if (rv != SOC_E_NONE) { 2107 LOG_CLI((BSL_META_U(unit, 2108 "ERR: Extra ctrs Init FAILED for id %d\n"), 2109 non_dma1->id - SOC_COUNTER_NON_DMA_START)); 2110 } 2111 non_dma1->num_entries = num_extra_ctr_entries; 2112 } 2113 *non_dma_entries += non_dma1->num_entries; 2114 /* End of Control block for IDB OBM counters */ 2115 2116 /* Flowtracker Group Counters - Control Block */ 2117 /* GROUP_FLOW_EXCEED_COUNT */ 2118 non_dma0 = &soc->counter_non_dma[SOC_COUNTER_NON_DMA_FT_GROUP_FLOW_NUM_EXCEEDED_CNT - 2119 SOC_COUNTER_NON_DMA_START]; 2120 non_dma0->id = SOC_COUNTER_NON_DMA_FT_GROUP_FLOW_NUM_EXCEEDED_CNT; 2121 non_dma0->flags = _SOC_COUNTER_NON_DMA_VALID | 2122 _SOC_COUNTER_NON_DMA_DO_DMA; 2123 non_dma0->flags |= _SOC_COUNTER_NON_DMA_NO_SHOW_C; 2124 2125 SOC_PBMP_CLEAR(non_dma0->pbmp); 2126 non_dma0->base_index = non_dma_start_index + *non_dma_entries; 2127 non_dma0->entries_per_port = 0; 2128 non_dma0->num_entries = 2129 NUM_PIPE(unit) * soc_mem_index_count(unit, BSC_KG_GROUP_TABLEm); 2130 non_dma0->mem = BSC_KG_FLOW_EXCEED_COUNTERm; 2131 non_dma0->reg = INVALIDr; 2132 non_dma0->field = FLOW_COUNTf; 2133 non_dma0->cname = "GROUP_FLOW_EXCEED_COUNT"; 2134 2135 num_entries = soc_mem_index_count(unit, BSC_KG_GROUP_TABLEm); 2136 entry_words = soc_mem_entry_words(unit, BSC_KG_GROUP_TABLEm); 2137 2138 non_dma0->num_entries = NUM_PIPE(unit) * num_entries; 2139 non_dma0->dma_mem[pipe] = BSC_KG_FLOW_EXCEED_COUNTERm; 2140 non_dma0->dma_buf[pipe] = &buf[num_entries * entry_words * pipe]; 2141 non_dma0->dma_index_max[pipe] = soc_mem_index_max(unit, non_dma0->dma_mem[pipe]); 2142 2143 *non_dma_entries += non_dma0->num_entries; 2144 2145 /* GROUP_FLOW_LEARNED_COUNT */ 2146 non_dma0 = &soc->counter_non_dma[SOC_COUNTER_NON_DMA_FT_GROUP_FLOW_LEARNT_CNT - 2147 SOC_COUNTER_NON_DMA_START]; 2148 non_dma0->id = SOC_COUNTER_NON_DMA_FT_GROUP_FLOW_LEARNT_CNT; 2149 non_dma0->flags = _SOC_COUNTER_NON_DMA_VALID | 2150 _SOC_COUNTER_NON_DMA_DO_DMA; 2151 non_dma0->flags |= _SOC_COUNTER_NON_DMA_NO_SHOW_C; 2152 2153 SOC_PBMP_CLEAR(non_dma0->pbmp); 2154 non_dma0->base_index = non_dma_start_index + *non_dma_entries; 2155 non_dma0->entries_per_port = 0; 2156 non_dma0->num_entries = 2157 NUM_PIPE(unit) * soc_mem_index_count(unit, BSC_KG_GROUP_TABLEm); 2158 non_dma0->mem = BSC_KG_FLOW_LEARNED_COUNTERm; 2159 non_dma0->reg = INVALIDr; 2160 non_dma0->field = FLOW_COUNTf; 2161 non_dma0->cname = "GROUP_FLOW_LEARNED_COUNT"; 2162 2163 num_entries = soc_mem_index_count(unit, BSC_KG_GROUP_TABLEm); 2164 entry_words = soc_mem_entry_words(unit, BSC_KG_GROUP_TABLEm); 2165 2166 non_dma0->num_entries = NUM_PIPE(unit) * num_entries; 2167 non_dma0->dma_mem[pipe] = BSC_KG_FLOW_LEARNED_COUNTERm; 2168 non_dma0->dma_buf[pipe] = &buf[num_entries * entry_words * pipe]; 2169 non_dma0->dma_index_max[pipe] = soc_mem_index_max(unit, non_dma0->dma_mem[pipe]); 2170 2171 *non_dma_entries += non_dma0->num_entries; 2172 2173 2174 /* GROUP_AGE_OUT_COUNT */ 2175 non_dma0 = &soc->counter_non_dma[SOC_COUNTER_NON_DMA_FT_GROUP_FLOW_AGE_OUT_CNT - 2176 SOC_COUNTER_NON_DMA_START]; 2177 non_dma0->id = SOC_COUNTER_NON_DMA_FT_GROUP_FLOW_AGE_OUT_CNT; 2178 non_dma0->flags = _SOC_COUNTER_NON_DMA_VALID | 2179 _SOC_COUNTER_NON_DMA_DO_DMA; 2180 non_dma0->flags |= _SOC_COUNTER_NON_DMA_NO_SHOW_C; 2181 2182 SOC_PBMP_CLEAR(non_dma0->pbmp); 2183 non_dma0->base_index = non_dma_start_index + *non_dma_entries; 2184 non_dma0->entries_per_port = 0; 2185 non_dma0->num_entries = 2186 NUM_PIPE(unit) * soc_mem_index_count(unit, BSC_KG_GROUP_TABLEm); 2187 non_dma0->mem = BSC_KG_FLOW_AGE_OUT_COUNTERm; 2188 non_dma0->reg = INVALIDr; 2189 non_dma0->field = FLOW_COUNTf; 2190 non_dma0->cname = "GROUP_AGE_OUT_COUNT"; 2191 2192 num_entries = soc_mem_index_count(unit, BSC_KG_GROUP_TABLEm); 2193 entry_words = soc_mem_entry_words(unit, BSC_KG_GROUP_TABLEm); 2194 2195 non_dma0->num_entries = NUM_PIPE(unit) * num_entries; 2196 non_dma0->dma_mem[pipe] = BSC_KG_FLOW_AGE_OUT_COUNTERm; 2197 non_dma0->dma_buf[pipe] = &buf[num_entries * entry_words * pipe]; 2198 non_dma0->dma_index_max[pipe] = soc_mem_index_max(unit, non_dma0->dma_mem[pipe]); 2199 2200 *non_dma_entries += non_dma0->num_entries; 2201 2202 /* GROUP_FLOW_MISSED_COUNT */ 2203 non_dma0 = &soc->counter_non_dma[SOC_COUNTER_NON_DMA_FT_GROUP_FLOW_MISSED_CNT - 2204 SOC_COUNTER_NON_DMA_START]; 2205 non_dma0->id = SOC_COUNTER_NON_DMA_FT_GROUP_FLOW_MISSED_CNT; 2206 non_dma0->flags = _SOC_COUNTER_NON_DMA_VALID | 2207 _SOC_COUNTER_NON_DMA_DO_DMA; 2208 non_dma0->flags |= _SOC_COUNTER_NON_DMA_NO_SHOW_C; 2209 2210 SOC_PBMP_CLEAR(non_dma0->pbmp); 2211 non_dma0->base_index = non_dma_start_index + *non_dma_entries; 2212 non_dma0->entries_per_port = 0; 2213 non_dma0->num_entries = 2214 NUM_PIPE(unit) * soc_mem_index_count(unit, BSC_KG_GROUP_TABLEm); 2215 non_dma0->mem = BSC_KG_FLOW_MISSED_COUNTERm; 2216 non_dma0->reg = INVALIDr; 2217 non_dma0->field = FLOW_COUNTf; 2218 non_dma0->cname = "GROUP_FLOW_MISSED_COUNT"; 2219 2220 num_entries = soc_mem_index_count(unit, BSC_KG_GROUP_TABLEm); 2221 entry_words = soc_mem_entry_words(unit, BSC_KG_GROUP_TABLEm); 2222 2223 non_dma0->num_entries = NUM_PIPE(unit) * num_entries; 2224 non_dma0->dma_mem[pipe] = BSC_KG_FLOW_MISSED_COUNTERm; 2225 non_dma0->dma_buf[pipe] = &buf[num_entries * entry_words * pipe]; 2226 non_dma0->dma_index_max[pipe] = soc_mem_index_max(unit, non_dma0->dma_mem[pipe]); 2227 2228 *non_dma_entries += non_dma0->num_entries; 2229 2230 /* GROUP_METER_EXCEED_COUNT */ 2231 non_dma0 = &soc->counter_non_dma[SOC_COUNTER_NON_DMA_FT_GROUP_FLOW_METER_EXCEEDED_CNT - 2232 SOC_COUNTER_NON_DMA_START]; 2233 non_dma0->id = SOC_COUNTER_NON_DMA_FT_GROUP_FLOW_METER_EXCEEDED_CNT; 2234 non_dma0->flags = _SOC_COUNTER_NON_DMA_VALID | 2235 _SOC_COUNTER_NON_DMA_DO_DMA; 2236 non_dma0->flags |= _SOC_COUNTER_NON_DMA_NO_SHOW_C; 2237 2238 SOC_PBMP_CLEAR(non_dma0->pbmp); 2239 non_dma0->base_index = non_dma_start_index + *non_dma_entries; 2240 non_dma0->entries_per_port = 0; 2241 non_dma0->num_entries = 2242 NUM_PIPE(unit) * soc_mem_index_count(unit, BSC_DG_GROUP_TABLEm); 2243 non_dma0->mem = BSC_DG_FLOW_METER_EXCEED_COUNTERm; 2244 non_dma0->reg = INVALIDr; 2245 non_dma0->field = FLOW_COUNTf; 2246 non_dma0->cname = "GROUP_METER_EXCEED_COUNT"; 2247 2248 num_entries = soc_mem_index_count(unit, BSC_DG_GROUP_TABLEm); 2249 entry_words = soc_mem_entry_words(unit, BSC_DG_GROUP_TABLEm); 2250 2251 non_dma0->num_entries = NUM_PIPE(unit) * num_entries; 2252 non_dma0->dma_mem[pipe] = BSC_DG_FLOW_METER_EXCEED_COUNTERm; 2253 non_dma0->dma_buf[pipe] = &buf[num_entries * entry_words * pipe]; 2254 non_dma0->dma_index_max[pipe] = soc_mem_index_max(unit, non_dma0->dma_mem[pipe]); 2255 2256 *non_dma_entries += non_dma0->num_entries; 2257 2258 2259 /* Eviction table init */ 2260 SOC_IF_ERROR_RETURN(soc_counter_trident3_eviction_init(unit)); 2261 2262 return SOC_E_NONE; 2263 2264 } 2265 2266 #endif /* BCM_HELIX5_SUPPORT */