bondoptions.c (6043B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: bondoptions.c 8 * Purpose: Populates Helix5 Bond Options Info. 9 * Requires: SOC Common Bond Options Initializer. 10 */ 11 12 #include <shared/bsl.h> 13 14 #include <soc/defs.h> 15 16 #ifdef BCM_HELIX5_SUPPORT 17 18 #include <shared/bitop.h> 19 #include <soc/iproc.h> 20 #include <soc/helix5.h> 21 #include <soc/bondoptions.h> 22 23 24 /* 25 * Function to conver to Core Clock frequency encodings to 26 * real core clock frequencies. 27 */ 28 STATIC int 29 _soc_helix5_bond_option_to_core_clk_freq(int unit, int val) 30 { 31 int freq; 32 33 switch (val) { 34 case 0x0: 35 freq = 893; 36 break; 37 case 0x1: 38 freq = 762; 39 break; 40 case 0x2: 41 freq = 668; 42 break; 43 case 0x3: 44 freq = 587; 45 break; 46 case 0x4: 47 freq = 543; 48 break; 49 case 0x5: 50 freq = 450; 51 break; 52 case 0x6: 53 freq = 400; 54 break; 55 56 default: 57 freq = 893; 58 /* unknown max frequency */ 59 break; 60 } 61 62 return freq; 63 } 64 65 /* 66 * Function to initialize the bondoptions cache based on the 67 * Bond Info read from the relevant registers. 68 */ 69 int 70 soc_helix5_bond_info_init(int unit) 71 { 72 soc_bond_info_t *bond_info = SOC_BOND_INFO(unit); 73 uint32 addr, val; 74 int i, bit_val; 75 76 soc_reg_t soc_hx5_bond_info_regs[] = { 77 DMU_PCU_OTP_CONFIG_0r, 78 DMU_PCU_OTP_CONFIG_1r, 79 DMU_PCU_OTP_CONFIG_2r, 80 DMU_PCU_OTP_CONFIG_3r, 81 DMU_PCU_OTP_CONFIG_4r, 82 DMU_PCU_OTP_CONFIG_5r, 83 DMU_PCU_OTP_CONFIG_6r, 84 DMU_PCU_OTP_CONFIG_7r, 85 DMU_PCU_OTP_CONFIG_8r, 86 DMU_PCU_OTP_CONFIG_9r, 87 DMU_PCU_OTP_CONFIG_10r, 88 DMU_PCU_OTP_CONFIG_11r, 89 DMU_PCU_OTP_CONFIG_12r, 90 DMU_PCU_OTP_CONFIG_13r, 91 DMU_PCU_OTP_CONFIG_14r, 92 DMU_PCU_OTP_CONFIG_15r, 93 DMU_PCU_OTP_CONFIG_16r, 94 DMU_PCU_OTP_CONFIG_17r, 95 DMU_PCU_OTP_CONFIG_18r, 96 DMU_PCU_OTP_CONFIG_19r, 97 DMU_PCU_OTP_CONFIG_20r, 98 DMU_PCU_OTP_CONFIG_21r, 99 DMU_PCU_OTP_CONFIG_22r, 100 DMU_PCU_OTP_CONFIG_23r, 101 DMU_PCU_OTP_CONFIG_24r, 102 DMU_PCU_OTP_CONFIG_25r, 103 DMU_PCU_OTP_CONFIG_26r, 104 DMU_PCU_OTP_CONFIG_27r, 105 DMU_PCU_OTP_CONFIG_28r, 106 DMU_PCU_OTP_CONFIG_29r, 107 DMU_PCU_OTP_CONFIG_30r, 108 DMU_PCU_OTP_CONFIG_31r 109 }; 110 int reg_num = COUNTOF(soc_hx5_bond_info_regs); 111 SHR_BITDCL bond_info_regval[_SHR_BITDCLSIZE(COUNTOF(soc_hx5_bond_info_regs) * 32)] = {0}; 112 113 int feature_enables[][3] = { 114 /* Bit */ /* Bool Invert? */ /* Feature Enum */ /* Desc */ 115 {209, 0, socBondInfoNoIHost}, /* iHost Disable */ 116 {328, 0, socBondInfoBskDisable}, /* BROADSCAN disable */ 117 {329, 0, socBondInfoBskNoPktSampling}, /* BROADSCAN packet sampling disable */ 118 {330, 0, socBondInfoBskNoHWExportPktBuild}, /* BROADSCAN HW export packet build disable */ 119 {331, 0, socBondInfoBskNoTCPBidir}, /* BROADSCAN TCP bidir processing disable */ 120 {332, 0, socBondInfoBskNoDoSAttackVector}, /* BROADSCAN DOS attack vector check disable */ 121 {333, 0, socBondInfoBskNoMicroFlowPolicer}, /* BROADSCAN micro flow policer disable */ 122 {334, 0, socBondInfoBskNoALU32Inst2to11}, /* BROADSCAN ALU32 inst 2_to_11 disable */ 123 {-1, 0, -1 } /* Always last */ 124 }; 125 126 127 for (i = 0; i < reg_num; i++) { 128 addr = soc_reg_addr(unit, soc_hx5_bond_info_regs[i], REG_PORT_ANY, 0); 129 soc_iproc_getreg(unit, addr, &val); 130 SHR_BITCOPY_RANGE(bond_info_regval, i * 32, &val, 0, 32); 131 } 132 133 SOC_BOND_OPTIONS_COPY(bond_info->rev_id, uint16, bond_info_regval, 0, 7); 134 SOC_BOND_OPTIONS_COPY(bond_info->dev_id, uint16, bond_info_regval, 8, 23); 135 SOC_BOND_OPTIONS_COPY(bond_info->device_skew, uint32, bond_info_regval, 24, 27); 136 SOC_BOND_OPTIONS_COPY(bond_info->mb_bank_num, uint32, bond_info_regval, 28, 33); 137 138 /* Max Core Clock Frequency */ 139 SOC_BOND_OPTIONS_COPY(val, uint32, bond_info_regval, 28, 31); 140 bond_info->max_core_freq = _soc_helix5_bond_option_to_core_clk_freq(unit, val); 141 142 /* Default Core Clock Frequency */ 143 SOC_BOND_OPTIONS_COPY(val, uint32, bond_info_regval, 32, 35); 144 bond_info->default_core_freq = _soc_helix5_bond_option_to_core_clk_freq(unit, val); 145 146 /* A72 Frequency */ 147 SOC_BOND_OPTIONS_COPY(val, uint32, bond_info_regval, 210, 210); 148 if (val == 0x0) { 149 SOC_BOND_INFO_FEATURE_SET(unit, socBondInfoFeatureA72Frequency2Ghz); 150 } else if (val == 0x1) { 151 SOC_BOND_INFO_FEATURE_SET(unit, socBondInfoFeatureA72Frequency1Ghz); 152 } 153 154 /* BROADSCAN Session table depth */ 155 SOC_BOND_OPTIONS_COPY(val, uint32, bond_info_regval, 326, 327); 156 if (val == 1) { 157 SOC_BOND_INFO_FEATURE_SET(unit, socBondInfoBskSessionDepth8k); 158 } else if (val == 2) { 159 SOC_BOND_INFO_FEATURE_SET(unit, socBondInfoBskSessionDepth16k); 160 } else if (val == 3) { 161 SOC_BOND_INFO_FEATURE_SET(unit, socBondInfoBskSessionDepth32k); 162 } 163 164 /* ICID */ 165 for (i = 0; i < (HX5_ICID_LENGTH_BYTES/4); i++) { 166 /* For HX5 the ICID start from 1440 {20*(64+8)}. 64 are user bits and 8 are ECC bits. */ 167 bit_val = 1440 + (i * 32); 168 SOC_BOND_OPTIONS_COPY(bond_info->ic_id[i], uint32, \ 169 bond_info_regval, bit_val, bit_val + 32); 170 } 171 172 /* Set the feature enable status */ 173 for(i = 0; i < COUNTOF(feature_enables); i++) { 174 bit_val = SHR_BITGET(bond_info_regval, feature_enables[i][0]); 175 if (feature_enables[i][1]) { 176 /* Boolean invert */ 177 bit_val = !bit_val; 178 } 179 180 if (bit_val) { 181 SOC_BOND_INFO_FEATURE_SET(unit, feature_enables[i][2]); 182 } 183 } 184 185 return SOC_E_NONE; 186 } 187 188 #endif /* BCM_HELIX5_SUPPORT */ 189