helix4.c (255580B)
1 /* 2 * 3 * This license is set out in https://raw.githubusercontent.com/Broadcom-Network-Switching-Software/OpenBCM/master/Legal/LICENSE file. 4 * 5 * Copyright 2007-2019 Broadcom Inc. All rights reserved. 6 * 7 * File: helix4.c 8 * Purpose: 9 * Requires: 10 */ 11 12 13 #include <sal/core/boot.h> 14 #include <shared/bsl.h> 15 #include <soc/triumph3.h> 16 #include <soc/helix4.h> 17 #include <soc/bradley.h> 18 #include <soc/drv.h> 19 #include <soc/error.h> 20 #include <soc/debug.h> 21 #include <soc/mem.h> 22 #include <soc/mmu_config.h> 23 24 #ifdef BCM_HELIX4_SUPPORT 25 26 #define SOC_MAX_PHY_PORTS 86 27 28 #define CORE_MODE_SINGLE 0 29 #define CORE_MODE_DUAL 1 30 #define CORE_MODE_QUAD 2 31 #define CORE_MODE_NOTDM 3 32 33 #define PHY_MODE_SINGLE 0 34 #define PHY_MODE_DUAL 1 35 #define PHY_MODE_QUAD 2 36 37 #define MAC_MODE_INDEP 0 38 #define MAC_MODE_AGGR 1 39 40 #define _MAX_HX4_PORT_CFG 7 41 42 #define _MAX_TR3_TDM_SLOTS 380 43 44 #define WC40_UCMEM_DATA_ENTRY_LEN 16 45 46 #define _TR3_MMU_CELLS_RSVD_IP 100 47 48 #define _TR3_MMU_MAX_PACKET_BYTES 10240 /* bytes */ 49 #define _TR3_MMU_PACKET_HEADER_BYTES 64 /* bytes */ 50 #define _TR3_MMU_JUMBO_FRAME_BYTES 9216 /* bytes */ 51 #define _TR3_MMU_DEFAULT_MTU_BYTES 1536 /* bytes */ 52 53 #define _TR3_MMU_TOTAL_CELLS_24K 24576 /* 24k cells */ 54 #define _TR3_MMU_TOTAL_CELLS_19K 19456 /* 19k cells */ 55 #define _HX4_MMU_TOTAL_CELLS_10K 10240 /* 10k cells */ 56 57 #define _TR3_MMU_TOTAL_CELLS(unit) _soc_tr3_mmu_buffer_cells[(unit)] 58 59 #define _TR3_MMU_BYTES_PER_CELL 208 /* bytes (1664 bits) */ 60 #define _TR3_MMU_NUM_PG 8 61 #define _TR3_MMU_NUM_POOL 4 62 63 #define _MAX_HX4_FLEX_PORT_PROPS 12 64 65 /* Default ISM mem config sizes 66 * These are scaled down automatically for various SKU's 67 */ 68 #define _ISM_MEM_VLAN_XLATE_SIZE (32*1024)/6 69 #define _ISM_MEM_L2_SIZE (64*1024)/6 70 #define _ISM_MEM_L3_SIZE (32*1024)/6 71 #define _ISM_MEM_EP_VLAN_XLATE_SIZE (16*1024)/6 72 #define _ISM_MEM_MPLS_SIZE (32*1024)/6 73 74 #define _MEM_NOT_APPLICABLE -1 75 76 77 #define _SOC_HX4_DEFIP_MAX_TCAMS 32 78 #define _SOC_HX4_DEFIP_TCAM_DEPTH 1024 79 80 typedef enum { 81 _SOC_PARITY_TYPE_NONE, 82 _SOC_PARITY_TYPE_GENERIC, 83 _SOC_PARITY_TYPE_PARITY, 84 _SOC_PARITY_TYPE_ECC, 85 _SOC_PARITY_TYPE_MMU_THDO, 86 _SOC_PARITY_TYPE_MMU_THDI, 87 _SOC_PARITY_TYPE_MMU_WRED, 88 _SOC_PARITY_TYPE_MMU_QCN, 89 _SOC_PARITY_TYPE_MMU_LLS, 90 _SOC_PARITY_TYPE_AXP, 91 _SOC_PARITY_TYPE_BST, 92 _SOC_PARITY_TYPE_SER, 93 _SOC_PARITY_INFO_TYPE_OAM, 94 _SOC_PARITY_INFO_TYPE_NUM 95 } _soc_hx4_parity_info_type_t; 96 97 char *_soc_hx4_ser_hwmem_base_info[] = { 98 "CMIC PKT BUFFER - In Iarb", 99 "CPU PKT BUFFER - In Iarb", 100 "AXP PACKET BUFFER - In Iarb", 101 "IFP COUNTER MUX DATA STAGING - In Ifp", 102 "INGRESS PACKET BUFFER - In Ipars", 103 "ESM AUX1 FIFO - In Iesmif", 104 "ESM CTRL BUS FIFO - In Iesmif", 105 "ESM ADM CTRL FIFO - In Iesmif", 106 "ESM ET RSP FIFO - In Iesmif", 107 "ESM CTRL BUS FIFO 1 - In Iesmif", 108 "ESM SER STATUS BUS FIFO - In Iesmif", 109 "ISW2 EOP BUFFER A - In Iesmif", 110 "ISW2 EOP BUFFER B - In Iesmif", 111 "ISW2 EOP BUFFER C - In Iesmif", 112 "Invalid value", 113 "Invalid value", 114 "EP MPB DATA - In El3", 115 "EP INITBUF - In Ehcpm", 116 "CM DATA BUFFER - In Edatabuf", 117 "XLP0 DATA BUFFER - In Edatabuf", 118 "Invalid value", 119 "XTP0 DATA BUFFER - In Edatabuf", 120 "XTP1 DATA BUFFER - In Edatabuf", 121 "XTP2 DATA BUFFER - In Edatabuf", 122 "XTP3 DATA BUFFER - In Edatabuf", 123 "XWP0 DATA BUFFER - In Edatabuf", 124 "XWP1 DATA BUFFER - In Edatabuf", 125 "XWP2 DATA BUFFER - In Edatabuf", 126 "XTP RESI DATA BUFFER - In Edatabuf", 127 "Invalid value", 128 "Invalid value", 129 "Invalid value", 130 "IPARS - PassThrought bus parity check", 131 "IVXLT - PassThrought bus parity check", 132 "IMPLS - PassThrought bus parity check", 133 "IL2L3 - PassThrought bus parity check", 134 "Invalid value", 135 "IFP - PassThrought bus parity check", 136 "IRSEL1 - PassThrought bus parity check", 137 "ISW1 - PassThrought bus parity check", 138 "IRSEL2 - PassThrought bus parity check", 139 "Invalid value", 140 "Invalid value", 141 "Invalid value", 142 "Invalid value", 143 "Invalid value", 144 "Invalid value", 145 "Invalid value", 146 "EGR VLAN - PassThrought bus parity check", 147 "EGR HCPM - PassThrought bus parity check", 148 "EGR PMOD - PassThrought bus parity check", 149 "EGR FPPARS - PassThrought bus parity check", 150 "EFP - PassThrought bus parity check", 151 }; 152 153 /* SER processing for TCAMs */ 154 static _soc_generic_ser_info_t _soc_hx4_tcam_ser_info_template[] = { 155 { VFP_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, 156 _SOC_SER_PARITY_4BITS, _SOC_SER_INTERLEAVE_MOD2, 157 { {0, 235}, {1, 235}, {236, 469}, {237, 469} }, 0, 0, 0, 0, 158 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_DISCARD_READ}, 159 { MY_STATION_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, 160 _SOC_SER_PARITY_4BITS, _SOC_SER_INTERLEAVE_MOD2, 161 { {0, 76}, {1, 76}, {77, 152}, {78, 152} }, 0, 0, 0, 0, 162 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_DISCARD_READ}, 163 { L2_USER_ENTRYm, INVALIDm, _SOC_SER_TYPE_PARITY, 164 _SOC_SER_PARITY_4BITS, _SOC_SER_INTERLEAVE_MOD2, 165 { {0, 61}, {1, 61}, {62, 122}, {63, 122} }, 0, 0, 0, 0, 166 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_DISCARD_READ}, 167 { L3_TUNNELm, INVALIDm, _SOC_SER_TYPE_PARITY, 168 _SOC_SER_PARITY_4BITS, _SOC_SER_INTERLEAVE_MOD2, 169 { {0, 106}, {1, 106}, {107, 212}, {108, 212} }, 0, 0, 0, 0, 170 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_DISCARD_READ}, 171 { FP_GLOBAL_MASK_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, 172 _SOC_SER_PARITY_4BITS, _SOC_SER_INTERLEAVE_MOD2, 173 { {0, 88}, {1, 88}, {89, 176}, {90, 176} }, 0, 0, 0, 0, 174 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_DISCARD_READ}, 175 { VLAN_SUBNETm, INVALIDm, _SOC_SER_TYPE_PARITY, 176 _SOC_SER_PARITY_4BITS, _SOC_SER_INTERLEAVE_MOD2, 177 { {0, 64}, {1, 64}, {65, 128}, {66, 128} }, 0, 0, 0, 0, 178 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_DISCARD_READ}, 179 { L3_DEFIP_PAIR_128m, INVALIDm, _SOC_SER_TYPE_PARITY, 180 _SOC_SER_PARITY_8BITS, _SOC_SER_INTERLEAVE_NONE, 181 { {0, 95}, {96, 189}, {190, 285}, {286, 379} }, 0, 0, 0, 0, 182 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_NO_DMA | 183 _SOC_SER_FLAG_REMAP_READ | _SOC_SER_FLAG_SIZE_VERIFY}, 184 { L3_DEFIPm, INVALIDm, _SOC_SER_TYPE_PARITY, 185 _SOC_SER_PARITY_4BITS, _SOC_SER_INTERLEAVE_MOD2, 186 { {0, 95}, {1, 95}, {96, 189}, {97, 189} }, 0, 0, 0, 0, 187 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_NO_DMA | 188 _SOC_SER_FLAG_REMAP_READ | _SOC_SER_FLAG_SIZE_VERIFY}, 189 { FP_UDF_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, 190 _SOC_SER_PARITY_4BITS, _SOC_SER_INTERLEAVE_MOD2, 191 { {0, 80}, {1, 80}, {81, 160}, {82, 160} }, 0, 0, 0, 0, 192 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_DISCARD_READ}, 193 { CPU_COS_MAPm, INVALIDm, _SOC_SER_TYPE_PARITY, 194 _SOC_SER_PARITY_4BITS, _SOC_SER_INTERLEAVE_MOD2, 195 { {0, 112}, {1, 112}, {113, 224}, {114, 224} }, 0, 0, 0, 0, 196 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_DISCARD_READ}, 197 { EFP_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, 198 _SOC_SER_PARITY_4BITS, _SOC_SER_INTERLEAVE_MOD2, 199 { {0, 235}, {1, 235}, {236, 469}, {237, 469} }, 0, 0, 0, 0, 200 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_DISCARD_READ}, 201 { FP_TCAMm, INVALIDm, _SOC_SER_TYPE_PARITY, 202 _SOC_SER_PARITY_4BITS, _SOC_SER_INTERLEAVE_MOD2, 203 { {0, 235}, {1, 235}, {236, 469}, {237, 469} }, 0, 0, 0, 0, 204 _SOC_SER_FLAG_XY_READ | _SOC_SER_FLAG_DISCARD_READ}, 205 { INVALIDm }, 206 }; 207 208 _soc_generic_ser_info_t *_soc_hx4_tcam_ser_info[SOC_MAX_NUM_DEVICES]; 209 210 STATIC void 211 _soc_hx4_ser_info_flag_update(_soc_generic_ser_info_t *ser_info, 212 soc_mem_t mem, uint32 flag, int enable) 213 { 214 int ser_idx = 0; 215 216 while (INVALIDm != ser_info[ser_idx].mem) { 217 if (ser_info[ser_idx].mem == mem) { 218 if (enable) { 219 ser_info[ser_idx].ser_flags |= flag; 220 } else { 221 ser_info[ser_idx].ser_flags &= ~flag; 222 } 223 } 224 ser_idx++; 225 } 226 } 227 228 int 229 _soc_hx4_tcam_ser_init(int unit) 230 { 231 int rv = 0; 232 int alloc_size; 233 _soc_generic_ser_info_t *ser_info; 234 235 /* First, make per-unit copy of the master TCAM list */ 236 alloc_size = sizeof(_soc_hx4_tcam_ser_info_template); 237 if (NULL == _soc_hx4_tcam_ser_info[unit]) { 238 if ((_soc_hx4_tcam_ser_info[unit] = 239 sal_alloc(alloc_size, "hx4 tcam list")) == NULL) { 240 return SOC_E_MEMORY; 241 } 242 } 243 /* Make a fresh copy of the TCAM template info */ 244 sal_memcpy(_soc_hx4_tcam_ser_info[unit], 245 &(_soc_hx4_tcam_ser_info_template), 246 alloc_size); 247 248 /* Now make per-unit modifications */ 249 ser_info = _soc_hx4_tcam_ser_info[unit]; 250 251 if (soc_feature(unit, soc_feature_field_stage_half_slice) || 252 soc_feature(unit, soc_feature_field_stage_ingress_256_half_slice) || 253 soc_feature(unit, soc_feature_field_slice_size128) || 254 soc_feature(unit, soc_feature_field_stage_quarter_slice)) { 255 _soc_hx4_ser_info_flag_update(ser_info, FP_GLOBAL_MASK_TCAMm, 256 _SOC_SER_FLAG_NO_DMA, TRUE); 257 _soc_hx4_ser_info_flag_update(ser_info, FP_TCAMm, 258 _SOC_SER_FLAG_NO_DMA, TRUE); 259 } 260 261 if (soc_feature(unit, soc_feature_field_stage_half_slice) || 262 soc_feature(unit, soc_feature_field_stage_egress_256_half_slice) || 263 soc_feature(unit, soc_feature_field_stage_quarter_slice)) { 264 _soc_hx4_ser_info_flag_update(ser_info, EFP_TCAMm, 265 _SOC_SER_FLAG_NO_DMA, TRUE); 266 } 267 268 if (soc_feature(unit, soc_feature_field_stage_lookup_512_half_slice) || 269 soc_feature(unit, soc_feature_field_stage_quarter_slice)) { 270 _soc_hx4_ser_info_flag_update(ser_info, VFP_TCAMm, 271 _SOC_SER_FLAG_NO_DMA, TRUE); 272 } 273 274 rv = soc_generic_ser_init(unit, _soc_hx4_tcam_ser_info[unit]); 275 #ifdef INCLUDE_MEM_SCAN 276 soc_mem_scan_ser_list_register(unit, TRUE, _soc_hx4_tcam_ser_info[unit]); 277 #endif 278 return rv; 279 } 280 281 void 282 soc_hx4_ser_fail(int unit) 283 284 { 285 soc_generic_ser_process_error(unit, _soc_hx4_tcam_ser_info[unit], 286 _SOC_PARITY_TYPE_SER); 287 } 288 289 int 290 soc_hx4_pipe_mem_clear(int unit) 291 { 292 uint32 rval, index; 293 int pipe_init_usec; 294 soc_timeout_t to; 295 int tcam_protect_write; 296 297 static const soc_mem_t cam[] = { 298 L3_TUNNELm, 299 FP_UDF_TCAMm, 300 VLAN_SUBNET_ONLYm, 301 VFP_TCAMm, 302 MY_STATION_TCAM_ENTRY_ONLYm, 303 L2_USER_ENTRY_ONLYm, 304 L3_DEFIP_ONLYm, 305 L3_DEFIP_PAIR_128_ONLYm, 306 ESM_PKT_TYPE_IDm, 307 ESM_PKT_TYPE_ID_ONLYm, 308 FP_TCAMm, 309 FP_GLOBAL_MASK_TCAMm, 310 CPU_COS_MAP_ONLYm, 311 EFP_TCAMm 312 }; 313 314 static const soc_mem_t axp[] = { 315 AXP_WTX_TUNNELm, 316 AXP_WRX_WCDm, 317 AXP_WRX_SVP_ASSIGNMENTm, 318 AXP_WTX_DVP_PROFILEm, 319 AXP_WTX_PRI_MAPm, 320 AXP_WTX_FRAG_IDm 321 }; 322 323 /* 324 * Reset the IPIPE and EPIPE block 325 */ 326 rval = 0; 327 SOC_IF_ERROR_RETURN(WRITE_ING_HW_RESET_CONTROL_1r(unit, rval)); 328 soc_reg_field_set(unit, ING_HW_RESET_CONTROL_2r, &rval, RESET_ALLf, 1); 329 soc_reg_field_set(unit, ING_HW_RESET_CONTROL_2r, &rval, VALIDf, 1); 330 /* Set count to # entries in largest IPIPE table */ 331 soc_reg_field_set(unit, ING_HW_RESET_CONTROL_2r, &rval, COUNTf, 65536); 332 SOC_IF_ERROR_RETURN(WRITE_ING_HW_RESET_CONTROL_2r(unit, rval)); 333 334 rval = 0; 335 SOC_IF_ERROR_RETURN(WRITE_EGR_HW_RESET_CONTROL_0r(unit, rval)); 336 soc_reg_field_set(unit, EGR_HW_RESET_CONTROL_1r, &rval, RESET_ALLf, 1); 337 soc_reg_field_set(unit, EGR_HW_RESET_CONTROL_1r, &rval, VALIDf, 1); 338 /* Set count to # entries in largest EPIPE table */ 339 soc_reg_field_set(unit, EGR_HW_RESET_CONTROL_1r, &rval, COUNTf, 65536); 340 SOC_IF_ERROR_RETURN(WRITE_EGR_HW_RESET_CONTROL_1r(unit, rval)); 341 342 rval = 0; 343 SOC_IF_ERROR_RETURN(WRITE_ISM_HW_RESET_CONTROL_0r(unit, rval)); 344 soc_reg_field_set(unit, ISM_HW_RESET_CONTROL_1r, &rval, RESET_ALLf, 1); 345 soc_reg_field_set(unit, ISM_HW_RESET_CONTROL_1r, &rval, VALIDf, 1); 346 /* Set count to # entries in largest ISM table */ 347 soc_reg_field_set(unit, ISM_HW_RESET_CONTROL_1r, &rval, COUNTf, 131072); 348 SOC_IF_ERROR_RETURN(WRITE_ISM_HW_RESET_CONTROL_1r(unit, rval)); 349 350 /* Clear AXP block mems */ 351 rval = 0; 352 soc_reg_field_set(unit, AXP_WRX_MEMORY_BULK_RESETr, &rval, START_RESETf, 1); 353 SOC_IF_ERROR_RETURN(WRITE_AXP_WRX_MEMORY_BULK_RESETr(unit, rval)); 354 SOC_IF_ERROR_RETURN(WRITE_AXP_WTX_MEMORY_BULK_RESETr(unit, rval)); 355 SOC_IF_ERROR_RETURN(WRITE_AXP_SM_MEMORY_BULK_RESETr(unit, rval)); 356 357 /* For simulation, set timeout to 10 sec. Otherwise, timeout = 50 ms */ 358 if (SAL_BOOT_SIMULATION) { 359 pipe_init_usec = 10000000; 360 } else { 361 pipe_init_usec = 50000; 362 } 363 soc_timeout_init(&to, pipe_init_usec, 0); 364 /* Wait for IPIPE memory initialization done. */ 365 do { 366 SOC_IF_ERROR_RETURN(READ_ING_HW_RESET_CONTROL_2r(unit, &rval)); 367 if (soc_reg_field_get(unit, ING_HW_RESET_CONTROL_2r, rval, DONEf)) { 368 break; 369 } 370 if (soc_timeout_check(&to)) { 371 LOG_WARN(BSL_LS_SOC_COMMON, 372 (BSL_META_U(unit, 373 "unit %d : ING_HW_RESET timeout\n"), unit)); 374 break; 375 } 376 } while (TRUE); 377 soc_timeout_init(&to, pipe_init_usec, 0); 378 /* Wait for EPIPE memory initialization done. */ 379 do { 380 SOC_IF_ERROR_RETURN(READ_EGR_HW_RESET_CONTROL_1r(unit, &rval)); 381 if (soc_reg_field_get(unit, EGR_HW_RESET_CONTROL_1r, rval, DONEf)) { 382 break; 383 } 384 if (soc_timeout_check(&to)) { 385 LOG_WARN(BSL_LS_SOC_COMMON, 386 (BSL_META_U(unit, 387 "unit %d : EGR_HW_RESET timeout\n"), unit)); 388 break; 389 } 390 } while (TRUE); 391 soc_timeout_init(&to, pipe_init_usec, 0); 392 /* Wait for ISM memory initialization done. */ 393 do { 394 SOC_IF_ERROR_RETURN(READ_ISM_HW_RESET_CONTROL_1r(unit, &rval)); 395 if (soc_reg_field_get(unit, ISM_HW_RESET_CONTROL_1r, rval, DONEf)) { 396 break; 397 } 398 if (soc_timeout_check(&to)) { 399 LOG_WARN(BSL_LS_SOC_COMMON, 400 (BSL_META_U(unit, 401 "unit %d : ISM_HW_RESET timeout\n"), unit)); 402 break; 403 } 404 } while (TRUE); 405 soc_timeout_init(&to, pipe_init_usec, 0); 406 /* Wait for AXP WLAN RX memory initialization done. */ 407 do { 408 SOC_IF_ERROR_RETURN(READ_AXP_WRX_MEMORY_BULK_RESETr(unit, &rval)); 409 if (soc_reg_field_get(unit, AXP_WRX_MEMORY_BULK_RESETr, rval, RESET_DONEf) || 410 SAL_BOOT_PLISIM) { 411 break; 412 } 413 if (soc_timeout_check(&to)) { 414 LOG_WARN(BSL_LS_SOC_COMMON, 415 (BSL_META_U(unit, 416 "unit %d : AXP_WRX_MEMORY timeout\n"), unit)); 417 break; 418 } 419 } while (TRUE); 420 soc_timeout_init(&to, pipe_init_usec, 0); 421 /* Wait for AXP WLAN TX memory initialization done. */ 422 do { 423 SOC_IF_ERROR_RETURN(READ_AXP_WTX_MEMORY_BULK_RESETr(unit, &rval)); 424 if (soc_reg_field_get(unit, AXP_WTX_MEMORY_BULK_RESETr, rval, RESET_DONEf) || 425 SAL_BOOT_PLISIM) { 426 break; 427 } 428 if (soc_timeout_check(&to)) { 429 LOG_WARN(BSL_LS_SOC_COMMON, 430 (BSL_META_U(unit, 431 "unit %d : AXP_WTX_MEMORY timeout\n"), unit)); 432 break; 433 } 434 } while (TRUE); 435 soc_timeout_init(&to, pipe_init_usec, 0); 436 /* Wait for AXP SM memory initialization done. */ 437 do { 438 SOC_IF_ERROR_RETURN(READ_AXP_SM_MEMORY_BULK_RESETr(unit, &rval)); 439 if (soc_reg_field_get(unit, AXP_SM_MEMORY_BULK_RESETr, rval, RESET_DONEf) || 440 SAL_BOOT_PLISIM) { 441 break; 442 } 443 if (soc_timeout_check(&to)) { 444 LOG_WARN(BSL_LS_SOC_COMMON, 445 (BSL_META_U(unit, 446 "unit %d : AXP_SM_MEMORY timeout\n"), unit)); 447 break; 448 } 449 } while (TRUE); 450 rval = 0; 451 SOC_IF_ERROR_RETURN(WRITE_ING_HW_RESET_CONTROL_2r(unit, rval)); 452 SOC_IF_ERROR_RETURN(WRITE_EGR_HW_RESET_CONTROL_1r(unit, rval)); 453 SOC_IF_ERROR_RETURN(WRITE_ISM_HW_RESET_CONTROL_1r(unit, rval)); 454 rval = 0; 455 soc_reg_field_set(unit, AXP_WRX_MEMORY_BULK_RESETr, &rval, START_RESETf, 0); 456 SOC_IF_ERROR_RETURN(WRITE_AXP_WRX_MEMORY_BULK_RESETr(unit, rval)); 457 SOC_IF_ERROR_RETURN(WRITE_AXP_WTX_MEMORY_BULK_RESETr(unit, rval)); 458 SOC_IF_ERROR_RETURN(WRITE_AXP_SM_MEMORY_BULK_RESETr(unit, rval)); 459 460 if (!SAL_BOOT_SIMULATION || SAL_BOOT_BCMSIM) { 461 /* TCAM tables are not handled by hardware reset control */ 462 tcam_protect_write = SOC_CONTROL(unit)->tcam_protect_write; 463 SOC_CONTROL(unit)->tcam_protect_write = FALSE; 464 for (index = 0; index < sizeof(cam) / sizeof(soc_mem_t); index++) { 465 if (SOC_MEM_IS_VALID(unit, cam[index])) { 466 if (SAL_BOOT_BCMSIM && 467 !((cam[index] == VLAN_SUBNET_ONLYm) || 468 (cam[index] == VFP_TCAMm) || 469 (cam[index] == L2_USER_ENTRY_ONLYm))) { 470 continue; 471 } 472 SOC_IF_ERROR_RETURN(soc_mem_clear(unit, cam[index], 473 COPYNO_ALL, TRUE)); 474 } 475 } 476 SOC_CONTROL(unit)->tcam_protect_write = tcam_protect_write; 477 } 478 if (!SAL_BOOT_SIMULATION) { 479 for (index = 0; index < sizeof(axp) / sizeof(soc_mem_t); index++) { 480 SOC_IF_ERROR_RETURN(soc_mem_clear(unit, axp[index], COPYNO_ALL, TRUE)); 481 } 482 } 483 return SOC_E_NONE; 484 } 485 486 int 487 soc_hx4_init_port_mapping(int unit) 488 { 489 soc_info_t *si; 490 soc_mem_t mem; 491 uint32 rval; 492 ing_physical_to_logical_port_number_mapping_table_entry_t entry; 493 int port, phy_port, mmu_port; 494 int num_port, num_phy_port, num_mmu_port; 495 496 si = &SOC_INFO(unit); 497 498 /* Ingress physical to logical port mapping */ 499 mem = ING_PHYSICAL_TO_LOGICAL_PORT_NUMBER_MAPPING_TABLEm; 500 num_phy_port = soc_mem_index_count(unit, mem); 501 sal_memset(&entry, 0, sizeof(entry)); 502 for (phy_port = 0; phy_port < num_phy_port; phy_port++) { 503 port = si->port_p2l_mapping[phy_port]; 504 soc_mem_field32_set(unit, mem, &entry, LOGICAL_PORT_NUMBERf, 505 port == -1 ? 0x7f : port); 506 SOC_IF_ERROR_RETURN 507 (soc_mem_write(unit, mem, MEM_BLOCK_ALL, phy_port, &entry)); 508 } 509 num_port = soc_mem_index_count(unit, PORT_TABm); 510 /* Egress logical to physical port mapping */ 511 for (port = 0; port < num_port; port++) { 512 phy_port = si->port_l2p_mapping[port]; 513 rval = 0; 514 soc_reg_field_set(unit, EGR_LOGICAL_TO_PHYSICAL_PORT_NUMBER_MAPPINGr, 515 &rval, PHYSICAL_PORT_NUMBERf, 516 phy_port == -1 ? 0x7f : phy_port); 517 SOC_IF_ERROR_RETURN 518 (WRITE_EGR_LOGICAL_TO_PHYSICAL_PORT_NUMBER_MAPPINGr(unit, port, 519 rval)); 520 } 521 522 /* MMU to physical port mapping and MMU to logical port mapping */ 523 num_mmu_port = SOC_REG_NUMELS(unit, MMU_TO_PHY_PORT_MAPPINGr); 524 for (mmu_port = 0; mmu_port < num_mmu_port; mmu_port++) { 525 phy_port = si->port_m2p_mapping[mmu_port]; 526 port = phy_port == -1 ? -1 : si->port_p2l_mapping[phy_port]; 527 528 rval = 0; 529 soc_reg_field_set(unit, MMU_TO_PHY_PORT_MAPPINGr, &rval, PHY_PORTf, 530 phy_port == -1 ? 0x7f : phy_port); 531 SOC_IF_ERROR_RETURN 532 (WRITE_MMU_TO_PHY_PORT_MAPPINGr(unit, mmu_port, rval)); 533 534 rval = 0; 535 soc_reg_field_set(unit, MMU_TO_LOGIC_PORT_MAPPINGr, &rval, LOGIC_PORTf, 536 port == -1 ? 0x3f : port); 537 SOC_IF_ERROR_RETURN 538 (WRITE_MMU_TO_LOGIC_PORT_MAPPINGr(unit, mmu_port, rval)); 539 } 540 541 return SOC_E_NONE; 542 } 543 544 int 545 soc_hx4_init_num_cosq(int unit) 546 { 547 soc_info_t *si; 548 int port; 549 int mc_numq, mc_base; 550 int uc_numq, uc_base; 551 552 si = &SOC_INFO(unit); 553 554 SOC_PBMP_CLEAR(si->eq_pbm); 555 PBMP_ALL_ITER(unit, port) { 556 if (IS_HG_PORT(unit, port)) { 557 SOC_PBMP_PORT_ADD(si->eq_pbm, port); 558 } 559 } 560 561 PBMP_ALL_ITER(unit, port) { 562 soc_tr3_get_def_qbase(unit, port, _SOC_TR3_INDEX_STYLE_UCAST_QUEUE, 563 &uc_base, &uc_numq); 564 soc_tr3_get_def_qbase(unit, port, _SOC_TR3_INDEX_STYLE_MCAST_QUEUE, 565 &mc_base, &mc_numq); 566 si->port_num_cosq[port] = mc_numq; 567 si->port_cosq_base[port] = mc_base; 568 si->port_num_uc_cosq[port] = uc_numq; 569 si->port_uc_cosq_base[port] = uc_base; 570 si->port_group[port] = -1; 571 #if 0 572 LOG_CLI((BSL_META_U(unit, 573 "Port-%d : UC: %d:%d, MC: %d:%d, EQ:%d:%d\n"), 574 port, uc_base, uc_numq, mc_base, mc_numq, 575 eq_base, eq_numq)); 576 #endif 577 } 578 579 return SOC_E_NONE; 580 } 581 582 typedef struct { 583 uint16 dev_id; 584 uint8 opp_spacing; 585 int def_cfg; 586 int cfg[_MAX_HX4_PORT_CFG]; 587 } _soc_hx4_port_cfg_t; 588 589 typedef struct { 590 uint16 dev_id; 591 char *props[_MAX_HX4_FLEX_PORT_PROPS]; 592 } _soc_hx4_flex_port_cfg_t; 593 594 static _soc_hx4_flex_port_cfg_t hx4_flex_props[] = { 595 { BCM56548H_DEVICE_ID, { NULL } }, 596 { BCM56548_DEVICE_ID, { NULL } }, 597 { BCM56547_DEVICE_ID, { spn_BCM56547_3X42, spn_BCM56547_2X42, NULL } }, 598 { BCM56346_DEVICE_ID, { spn_BCM56340_4X10, spn_BCM56346_4X10_2X21, NULL } }, 599 { BCM56345_DEVICE_ID, { spn_BCM56340_4X10, spn_BCM56345_4X10_2X21, spn_BCM56345_2X21, NULL } }, 600 { BCM56344_DEVICE_ID, { spn_BCM56344_2X10, NULL } }, 601 { BCM56342_DEVICE_ID, { spn_BCM56340_4X10, NULL } }, 602 { BCM56340_DEVICE_ID, { spn_BCM56340_4X10, spn_BCM56340_2X10, 603 "REGRESSION", "EMULATION", NULL } }, 604 { BCM56049_DEVICE_ID, { NULL } }, 605 { BCM56048_DEVICE_ID, { NULL } }, 606 { BCM56047_DEVICE_ID, { NULL } }, 607 { BCM56042_DEVICE_ID, { NULL } }, 608 { BCM56041_DEVICE_ID, { NULL } }, 609 { BCM56040_DEVICE_ID, { NULL } } 610 }; 611 612 int16 _hx4_xc_flex_port_speeds[] = { 3, 1, -1 }; 613 int16 _hx4_xc_flex_port_lanes[] = { 4, 1, -1 }; 614 int16 _hx4_xc_def_flex_port_speeds[] = { 3, 0, 1 }; 615 int16 _hx4_wc_flex_port_speeds[] = { 21, 21, 10, 11, 10, 3, 1, -1 }; 616 int16 _hx4_wc_flex_port_lanes[] = { 4, 2, 2, 1, 1, 1, 1, -1 }; 617 int16 _hx4_wc_flex_port_speeds2[] = { 21, 11, 10, -1 }; 618 int16 _hx4_wc_flex_port_lanes2[] = {2, 1, 1, -1 }; 619 int16 _hx4_wc_def_flex_port_speeds[] = { 21, 21, 11 }; 620 621 622 /* HX4 PORT Configs: 623 624 F.HG[42] = Hot Swap between HG[42]/2xHGd[21]/2xRXAUI/4xHGs[11]/4xXFI/4xKR ?/4x1GE/4x2.5GE 625 F.HG[21] = Hot Swap between HG[21]/XAUI/4x1GE/4x2.5G 626 Flex[4x10] = Hot Swap between HG[21]/2xHGd[21]/2xRXAUI/4xHGs[11]/4xXFI/4xKR ?/4x1GE/4x2.5GE 627 F.QSGMII = NO Hot Swap between 1xQSGMII (4x1G) or 1x2.5GE/1x1GE(SGMII) 628 629 ------------------------------------------------------------------------------------------------------------------------------- 630 dev-id | cfg-id | configuration | property | Hot swap 631 ------------------------------------------------------------------------------------------------------------------------------- 632 FireScout: | | | | 633 ========= | | | | 634 BCM56548H | 492 | HX4_1G_200_D*: 5xF.QSGMII + 2x(2xHGd[21]/4xHGs[11]) + 1GE | none | yes 635 BCM56548 | 491 | HX4_1G_200_D*: 7xF.QSGMII + 3xF.HG[42] + 1GE | none | yes 636 | | | | 637 BCM56547 | 490 | HX4_1G_200_D: 10xF.QSGMII + 3xF.HG[42] + 1GE | bcm56547_3x42 | yes 638 | 500 | HX4_1G_200_E: 12xF.QSGMII + 2xF.HG[42] + 1GE | bcm56547_2x42 | yes 639 | 495 | HX4_1G_200_A, HX4_1G_200_B, HX4_1G_200_C: | | 640 | | 12xF.QSGMII + F.HG[42] + 2xHG[42] + 1GE | none | yes 641 | | | | 642 Helix4: | | | | 643 ====== | | | | 644 BCM56346 | 462 | HX4_1G_130*: 7xF.QSGMII + Flex[4x10] + 2xHG[21] + 1GE | none | yes 645 | 463 | HX4_1G_130_A:7xF.QSGMII +Flex[4x10]+ 2x(1xHGd[21]/2xHGs[11/10]) + 1GE | bcm56346_4X10_2x21 | yes 646 | | | | 647 | | | | 648 BCM56345 | 412 | HX4_1G_150* : 12xF.QSGMII + Flex[4x10] + 2xHG[21] + 1GE | | yes 649 | 413 | HX4_1G_150_E : 12xF.QSGMII+Flex[4x10]+2x(1xHGd[21]/2xHGs[11/10])+1GE | bcm56345_4X10_2x21 | yes 650 | 414 | HX4_1G_150_F : 12xF.QSGMII + 2x(2xHGd[21]/4xHGs[11/10]) + 1GE | bcm56345_2x21 | yes 651 | | | | 652 BCM56344 | 497 | HX4_1G_200_D*: 10xF.QSGMII + 3xFlex[4x10] + 1GE | none | yes 653 | 510 | HX4_1G_200_E*: 12xF.QSGMII + 2xFlex[4x10] + 1GE | bcm56344_2x10 | yes 654 | | | | 655 BCM56342 | 460 | HX4_1G_130: 7xF.QSGMII + Flex[4x10] + 2xHG[21] + 1GE | none | yes 656 | 464 | HX4_1G_130: 7xF.QSGMII + Flex[4x10] + 2xFlex[21G/1G] + 1GE | none | yes 657 | | | | 658 BCM56340 | 410 | HX4_1G_150_B, HX4_1G_150_C: | | 659 | | 12xF.QSGMII + Flex[4x10] + 2xHG[21]/1GE + 1GE | bcm56340_4x10 | yes 660 | 400 | HX4_1G_150_A: 12xF.QSGMII + 4xSGMII + 2xXFI + 2xHGd[21] + 1GE | none | no 661 | 610 | HX4_1G_200_E*: 12xF.QSGMII + 2xFlex[4x10] + 1GE | bcm56340_2x10 | yes 662 | | | | 663 Spiral: | | | | 664 ====== | | | | 665 BCM56049 | 420 | RGR_XFI_150: 1xF.QSGMII + 3xFlex[4x10] + 1GE | none | yes 666 | | | | 667 BCM56048 | 514 | HX4_1G_200_E*: 7xF.QSGMII + 2xFlex[4x10]] + 1GE | none | yes 668 | | | | 669 BCM56047 | 510 | HX4_1G_200_E*: 12xF.QSGMII + 2xFlex[4x10] + 1GE | none | yes 670 | | | | 671 Ranger: | | | | 672 ====== | | | | 673 BCM56042 | 11 | RGR_2P5G_150: 12x2.5GE/1GE + 12x2.5GE/1GE + 1GE | none | no 674 | | | | 675 BCM56041 | 420 | RGR_XFI_150: 1xF.QSGMII + 3xFlex[4x10] + 1GE | none | yes 676 | | | | 677 BCM56040 | 450 | RGR_XFI_200: 1xF.QSGMII + 3xF.HG[42] + 1GE | none | yes 678 | | | | 679 ----------------------------------------------------------------------------------------------------------------------------- 680 681 Note: use property portgroup_n=<lanes> for init time flex port selection/config." 682 Note: use property serdes_asymmetric_speed_mode=1 for GE ports to support 1/2.5G in a group */ 683 684 void 685 _soc_hx4_resolve_port_config(int unit, int dev_id) { 686 687 static _soc_hx4_port_cfg_t hx4_port_cfg[] = { 688 689 { BCM56548H_DEVICE_ID, 3, 492, { -1 } }, 690 { BCM56548_DEVICE_ID, 3, 491, { -1 } }, 691 { BCM56547_DEVICE_ID, 3, 495, { 490, 500, -1 } }, 692 { BCM56346_DEVICE_ID, 3, 462, { 6, 463, -1 } }, 693 { BCM56345_DEVICE_ID, 3, 412, { 1, 413, 414, -1 } }, 694 { BCM56344_DEVICE_ID, 3, 497, { 510, -1 } }, 695 { BCM56342_DEVICE_ID, 3, 460, { 464, -1 } }, 696 { BCM56340_DEVICE_ID, 3, 400, { 410, 610, 1, 30, -1 } }, 697 { BCM56049_DEVICE_ID, 3, 420, { -1 } }, 698 { BCM56048_DEVICE_ID, 3, 514, { -1 } }, 699 { BCM56047_DEVICE_ID, 3, 510, { -1 } }, 700 { BCM56042_DEVICE_ID, 3, 11, { -1 } }, 701 { BCM56041_DEVICE_ID, 3, 420, { -1 } }, 702 { BCM56040_DEVICE_ID, 3, 450, { -1 } } 703 }; 704 uint8 entries; 705 int i, c, config, cfg_id = 0; 706 707 config = soc_property_get(unit, spn_BCM56340_CONFIG, 0); 708 if (config) { 709 _tr3_port_config_id[unit] = config; 710 _tr3_flex_port_data[unit].dev_id = dev_id; 711 return; 712 } 713 714 entries = COUNTOF(hx4_flex_props); 715 for (i = 0; i < entries; i++) { 716 if (dev_id == hx4_flex_props[i].dev_id) { 717 _tr3_tdm_opp_spacing[unit] = hx4_port_cfg[i].opp_spacing; 718 cfg_id = hx4_port_cfg[i].def_cfg; 719 for (c = 0; hx4_flex_props[i].props[c] != NULL ;c++) { 720 config = soc_property_get(unit, hx4_flex_props[i].props[c], 0); 721 if (config) { 722 cfg_id = hx4_port_cfg[i].cfg[c]; 723 break; 724 } 725 } 726 break; 727 } 728 } 729 _tr3_port_config_id[unit] = cfg_id; 730 _tr3_flex_port_data[unit].dev_id = dev_id; 731 732 } 733 734 /* 735 * HX4 port mapping 736 * cpu port number is fixed: physical 0, logical 0, mmu 0 737 * loopback port numbers are fixed 738 */ 739 int 740 soc_hx4_get_port_mapping(int unit, uint16 dev_id) 741 { 742 743 /* 52x1GE + 4xHGd[21] + 1GE - Config for AV */ 744 static const int p2l_mapping_30[] = { 745 0, 746 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 747 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 748 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 749 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 750 49, -1, -1, -1, 751 50, 51, 52, 53, 752 54, 55, -1, -1, 753 56, -1, 57, -1, 754 -1, -1, -1, -1, 755 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 756 61, 59, 58, 60, 62 757 }; 758 static const int p2m_mapping_30[] = { 759 59, 760 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 761 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 762 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 763 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 764 60, -1, -1, -1, 765 48, 49, 50, 51, 766 52, 53, -1, -1, 767 54, -1, 55, -1, 768 -1, -1, -1, -1, 769 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 770 58, 62, 56, 61, 57 771 }; 772 static const int port_speed_max_30[] = { 773 -1, 774 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 775 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 776 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 777 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 778 1, -1, -1, -1, 779 1, 1, 1, 1, 780 12, 12, -1, -1, 781 21, -1, 21, -1, 782 -1, -1, -1, -1, 783 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 784 -1, -1, -1, -1, -1 785 }; 786 787 788 /* 52x1GE + 2xXFI + 2xHGd[21] + 1GE */ 789 static const int p2l_mapping_0[] = { 790 0, 791 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 792 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 793 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 794 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 795 49, -1, -1, -1, 796 50, 51, 52, 53, 797 54, 55, -1, -1, 798 56, -1, 57, -1, 799 -1, -1, -1, -1, 800 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 801 61, 59, 58, 60, 62 802 }; 803 static const int p2m_mapping_0[] = { 804 59, 805 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 806 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 807 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 808 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 809 60, -1, -1, -1, 810 48, 49, 50, 51, 811 52, 53, -1, -1, 812 54, -1, 55, -1, 813 -1, -1, -1, -1, 814 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 815 58, 62, 56, 61, 57 816 }; 817 static const int port_speed_max_0[] = { 818 -1, 819 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 820 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 821 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 822 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 823 1, -1, -1, -1, 824 1, 1, 1, 1, 825 10, 10, -1, -1, 826 21, -1, 21, -1, 827 -1, -1, -1, -1, 828 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 829 -1, -1, -1, -1, -1 830 }; 831 832 /* 48x1GE + 4xXFI + 2xHG[21] + 1GE */ 833 static const int p2l_mapping_1[] = { 834 0, 835 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 836 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 837 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 838 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 839 49, -1, -1, -1, 840 50, 51, 52, 53, 841 54, -1, -1, -1, 842 55, -1, -1, -1, 843 -1, -1, -1, -1, 844 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 845 61, 59, 58, 60, 62 846 }; 847 static const int p2m_mapping_1[] = { 848 59, 849 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 850 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 851 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 852 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 853 60, -1, -1, -1, 854 48, 49, 50, 51, 855 52, -1, -1, -1, 856 53, -1, -1, -1, 857 -1, -1, -1, -1, 858 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 859 58, 62, 56, 61, 57 860 }; 861 static const int port_speed_max_1[] = { 862 -1, 863 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 864 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 865 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 866 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 867 1, -1, -1, -1, 868 10, 10, 10, 10, 869 21, -1, -1, -1, 870 21, -1, -1, -1, 871 -1, -1, -1, -1, 872 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 873 -1, -1, -1, -1, -1 874 }; 875 876 /* 4x1GE + 12xXFI + 1GE */ 877 static const int p2l_mapping_2[] = { 878 0, 879 1, 2, 3, 4, -1, -1, -1, -1, -1, -1, -1, -1, 880 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 881 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 882 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 883 5, -1, -1, -1, 884 9, 10, 11, 12, 885 13, 14, 15, 16, 886 17, 18, 19, 20, 887 -1, -1, -1, -1, 888 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 889 61, 59, 58, 60, 62 890 }; 891 static const int p2m_mapping_2[] = { 892 59, 893 1, 2, 3, 4, -1, -1, -1, -1, -1, -1, -1, -1, 894 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 895 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 896 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 897 60, -1, -1, -1, 898 44, 45, 46, 47, 899 48, 49, 50, 51, 900 52, 53, 54, 55, 901 -1, -1, -1, -1, 902 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 903 58, 62, 56, 61, 57 904 }; 905 static const int port_speed_max_2[] = { 906 -1, 907 1, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1, 908 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 909 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 910 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 911 1, -1, -1, -1, 912 10, 10, 10, 10, 913 10, 10, 10, 10, 914 10, 10, 10, 10, 915 -1, -1, -1, -1, 916 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 917 -1, -1, -1, -1, -1 918 }; 919 920 /* 48x1GE + 4xXFI + 2xHG[42] + 1GE */ 921 static const int p2l_mapping_3[] = { 922 0, 923 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 924 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 925 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 926 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 927 49, -1, -1, -1, 928 50, 51, 52, 53, 929 54, -1, -1, -1, 930 55, -1, -1, -1, 931 -1, -1, -1, -1, 932 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 933 61, 59, 58, 60, 62 934 }; 935 static const int p2m_mapping_3[] = { 936 59, 937 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 938 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 939 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 940 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 941 60, -1, -1, -1, 942 48, 49, 50, 51, 943 52, -1, -1, -1, 944 53, -1, -1, -1, 945 -1, -1, -1, -1, 946 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 947 58, 62, 56, 61, 57 948 }; 949 static const int port_speed_max_3[] = { 950 -1, 951 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 952 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 953 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 954 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 955 1, -1, -1, -1, 956 10, 10, 10, 10, 957 42, -1, -1, -1, 958 42, -1, -1, -1, 959 -1, -1, -1, -1, 960 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 961 -1, -1, -1, -1, -1 962 }; 963 964 965 /* 48x1GE + 1x40G + 2xHG[42] + 1GE */ 966 static const int p2l_mapping_4[] = { 967 0, 968 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 969 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 970 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 971 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 972 49, -1, -1, -1, 973 50, -1, -1, -1, 974 54, -1, -1, -1, 975 55, -1, -1, -1, 976 -1, -1, -1, -1, 977 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 978 61, 59, 58, 60, 62 979 }; 980 static const int p2m_mapping_4[] = { 981 59, 982 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 983 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 984 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 985 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 986 60, -1, -1, -1, 987 48, -1, -1, -1, 988 52, -1, -1, -1, 989 53, -1, -1, -1, 990 -1, -1, -1, -1, 991 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 992 58, 62, 56, 61, 57 993 }; 994 static const int port_speed_max_4[] = { 995 -1, 996 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 997 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 998 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 999 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1000 1, -1, -1, -1, 1001 40, -1, -1, -1, 1002 42, -1, -1, -1, 1003 42, -1, -1, -1, 1004 -1, -1, -1, -1, 1005 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1006 -1, -1, -1, -1, -1 1007 }; 1008 1009 /* 4x1GE + 3xHG[42] + 1GE */ 1010 static const int p2l_mapping_5[] = { 1011 0, 1012 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1013 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1014 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1015 -1, -1, -1, -1, -1, -1, -1, -1, 1, 2, 3, 4, 1016 5, -1, -1, -1, 1017 9, -1, -1, -1, 1018 13, -1, -1, -1, 1019 17, -1, -1, -1, 1020 -1, -1, -1, -1, 1021 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1022 61, 59, 58, 60, 62 1023 }; 1024 static const int p2m_mapping_5[] = { 1025 59, 1026 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1027 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1028 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1029 -1, -1, -1, -1, -1, -1, -1, -1, 40, 41, 42, 43, 1030 60, -1, -1, -1, 1031 44, -1, -1, -1, 1032 48, -1, -1, -1, 1033 52, -1, -1, -1, 1034 -1, -1, -1, -1, 1035 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1036 58, 62, 56, 61, 57 1037 }; 1038 static const int port_speed_max_5[] = { 1039 -1, 1040 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1041 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1042 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1043 -1, -1, -1, -1, -1, -1, -1, -1, 1, 1, 1, 1, 1044 1, -1, -1, -1, 1045 42, -1, -1, -1, 1046 42, -1, -1, -1, 1047 42, -1, -1, -1, 1048 -1, -1, -1, -1, 1049 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1050 -1, -1, -1, -1, -1 1051 }; 1052 1053 /* 28x1GE + 4xXFI + 2xHG[21] + 1GE */ 1054 static const int p2l_mapping_6[] = { 1055 0, 1056 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 1057 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 1058 25, 26, 27, 28, -1, -1, -1, -1, -1, -1, -1, -1, 1059 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1060 49, -1, -1, -1, 1061 50, 51, 52, 53, 1062 54, -1, -1, -1, 1063 55, -1, -1, -1, 1064 -1, -1, -1, -1, 1065 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1066 61, 59, 58, 60, 62 1067 }; 1068 static const int p2m_mapping_6[] = { 1069 59, 1070 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 1071 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 1072 24, 25, 26, 27, -1, -1, -1, -1, -1, -1, -1, -1, 1073 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1074 60, -1, -1, -1, 1075 48, 49, 50, 51, 1076 52, -1, -1, -1, 1077 53, -1, -1, -1, 1078 -1, -1, -1, -1, 1079 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1080 58, 62, 56, 61, 57 1081 }; 1082 static const int port_speed_max_6[] = { 1083 -1, 1084 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1085 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1086 1, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1, 1087 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1088 1, -1, -1, -1, 1089 10, 10, 10, 10, 1090 21, -1, -1, -1, 1091 21, -1, -1, -1, 1092 -1, -1, -1, -1, 1093 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1094 -1, -1, -1, -1, -1 1095 }; 1096 1097 /* 12x2.5G (SGMII) + 4xXFI + 2xHG[21] + 1GE */ 1098 static const int p2l_mapping_7[] = { 1099 0, 1100 1, -1, -1, -1, 5, -1, -1, -1, 9, -1, -1, -1, 1101 13, -1, -1, -1, 17, -1, -1, -1, 21, -1, -1, -1, 1102 25, -1, -1, -1, 29, -1, -1, -1, 33, -1, -1, -1, 1103 37, -1, -1, -1, 41, -1, -1, -1, 45, -1, -1, -1, 1104 49, -1, -1, -1, 1105 50, 51, 52, 53, 1106 54, -1, -1, -1, 1107 55, -1, -1, -1, 1108 -1, -1, -1, -1, 1109 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1110 61, 59, 58, 60, 62 1111 }; 1112 static const int p2m_mapping_7[] = { 1113 59, 1114 0, -1, -1, -1, 4, -1, -1, -1, 8, -1, -1, -1, 1115 12, -1, -1, -1, 16, -1, -1, -1, 20, -1, -1, -1, 1116 24, -1, -1, -1, 28, -1, -1, -1, 32, -1, -1, -1, 1117 36, -1, -1, -1, 40, -1, -1, -1, 44, -1, -1, -1, 1118 60, -1, -1, -1, 1119 48, 49, 50, 51, 1120 52, -1, -1, -1, 1121 53, -1, -1, -1, 1122 -1, -1, -1, -1, 1123 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1124 58, 62, 56, 61, 57 1125 }; 1126 static const int port_speed_max_7[] = { 1127 -1, 1128 1, -1, -1, -1, 1, -1, -1, -1, 1, -1, -1, -1, 1129 1, -1, -1, -1, 1, -1, -1, -1, 1, -1, -1, -1, 1130 1, -1, -1, -1, 1, -1, -1, -1, 1, -1, -1, -1, 1131 1, -1, -1, -1, 1, -1, -1, -1, 1, -1, -1, -1, 1132 1, -1, -1, -1, 1133 10, 10, 10, 10, 1134 21, -1, -1, -1, 1135 21, -1, -1, -1, 1136 -1, -1, -1, -1, 1137 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1138 -1, -1, -1, -1, -1 1139 }; 1140 /* 12x2.5G (SGMII) + 1x40G + 2xHG[42] + 1GE */ 1141 static const int p2l_mapping_8[] = { 1142 0, 1143 1, -1, -1, -1, 5, -1, -1, -1, 9, -1, -1, -1, 1144 13, -1, -1, -1, 17, -1, -1, -1, 21, -1, -1, -1, 1145 25, -1, -1, -1, 29, -1, -1, -1, 33, -1, -1, -1, 1146 37, -1, -1, -1, 41, -1, -1, -1, 45, -1, -1, -1, 1147 49, -1, -1, -1, 1148 50, -1, -1, -1, 1149 54, -1, -1, -1, 1150 55, -1, -1, -1, 1151 -1, -1, -1, -1, 1152 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1153 61, 59, 58, 60, 62 1154 }; 1155 static const int p2m_mapping_8[] = { 1156 59, 1157 0, -1, -1, -1, 4, -1, -1, -1, 8, -1, -1, -1, 1158 12, -1, -1, -1, 16, -1, -1, -1, 20, -1, -1, -1, 1159 24, -1, -1, -1, 28, -1, -1, -1, 32, -1, -1, -1, 1160 36, -1, -1, -1, 40, -1, -1, -1, 44, -1, -1, -1, 1161 60, -1, -1, -1, 1162 48, -1, -1, -1, 1163 52, -1, -1, -1, 1164 53, -1, -1, -1, 1165 -1, -1, -1, -1, 1166 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1167 58, 62, 56, 61, 57 1168 }; 1169 static const int port_speed_max_8[] = { 1170 -1, 1171 1, -1, -1, -1, 1, -1, -1, -1, 1, -1, -1, -1, 1172 1, -1, -1, -1, 1, -1, -1, -1, 1, -1, -1, -1, 1173 1, -1, -1, -1, 1, -1, -1, -1, 1, -1, -1, -1, 1174 1, -1, -1, -1, 1, -1, -1, -1, 1, -1, -1, -1, 1175 1, -1, -1, -1, 1176 40, -1, -1, -1, 1177 42, -1, -1, -1, 1178 42, -1, -1, -1, 1179 -1, -1, -1, -1, 1180 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1181 -1, -1, -1, -1, -1 1182 }; 1183 /* 40x1GE + 12xXFI + 1GE */ 1184 static const int p2l_mapping_9[] = { 1185 0, 1186 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 1187 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 1188 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 1189 37, 38, 39, 40, -1, -1, -1, -1, -1, -1, -1, -1, 1190 41, -1, -1, -1, 1191 42, 43, 44, 45, 1192 46, 47, 48, 49, 1193 50, 51, 52, 53, 1194 -1, -1, -1, -1, 1195 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1196 61, 59, 58, 60, 62 1197 }; 1198 static const int p2m_mapping_9[] = { 1199 59, 1200 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 1201 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 1202 24, 25, 26, 27, 28, 29, 30, 31, 36, 37, 38, 39, 1203 41, 42, 43, 44, -1, -1, -1, -1, -1, -1, -1, -1, 1204 60, -1, -1, -1, 1205 48, 32, 49, 33, 1206 50, 34, 51, 35, 1207 52, 53, 54, 55, 1208 -1, -1, -1, -1, 1209 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1210 58, 62, 56, 61, 57 1211 }; 1212 static const int port_speed_max_9[] = { 1213 -1, 1214 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1215 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1216 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1217 1, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1, 1218 1, -1, -1, -1, 1219 10, 10, 10, 10, 1220 10, 10, 10, 10, 1221 10, 10, 10, 10, 1222 -1, -1, -1, -1, 1223 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1224 -1, -1, -1, -1, -1 1225 }; 1226 /* 24x1GE + 6x2.5GE + 2xHGd[21] + 1xHG[42] + 1GE */ 1227 static const int p2l_mapping_10[] = { 1228 0, 1229 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 1230 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 1231 25, -1, -1, -1, 29, -1, -1, -1, 33, -1, -1, -1, 1232 37, -1, -1, -1, 41, -1, -1, -1, 45, -1, -1, -1, 1233 49, -1, -1, -1, 1234 50, -1, 52, -1, 1235 54, -1, -1, -1, 1236 -1, -1, -1, -1, 1237 -1, -1, -1, -1, 1238 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1239 61, 59, 58, 60, 62 1240 }; 1241 static const int p2m_mapping_10[] = { 1242 59, 1243 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 1244 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 1245 24, -1, -1, -1, 28, -1, -1, -1, 32, -1, -1, -1, 1246 36, -1, -1, -1, 40, -1, -1, -1, 44, -1, -1, -1, 1247 60, -1, -1, -1, 1248 48, -1, 50, -1, 1249 52, -1, -1, -1, 1250 -1, -1, -1, -1, 1251 -1, -1, -1, -1, 1252 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1253 58, 62, 56, 61, 57 1254 }; 1255 static const int port_speed_max_10[] = { 1256 -1, 1257 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1258 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1259 3, -1, -1, -1, 3, -1, -1, -1, 3, -1, -1, -1, 1260 3, -1, -1, -1, 3, -1, -1, -1, 3, -1, -1, -1, 1261 1, -1, -1, -1, 1262 21, -1, 21, -1, 1263 42, -1, -1, -1, 1264 -1, -1, -1, -1, 1265 -1, -1, -1, -1, 1266 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1267 -1, -1, -1, -1, -1 1268 }; 1269 /* 12x2.5G (SGMII) + 12x2.5G + 1GE */ 1270 static const int p2l_mapping_11[] = { 1271 0, 1272 1, -1, -1, -1, 2, -1, -1, -1, 3, -1, -1, -1, 1273 4, -1, -1, -1, 5, -1, -1, -1, 6, -1, -1, -1, 1274 7, -1, -1, -1, 8, -1, -1, -1, 9, -1, -1, -1, 1275 10, -1, -1, -1, 11, -1, -1, -1, 12, -1, -1, -1, 1276 13, -1, -1, -1, 1277 14, 15, 16, 17, 1278 18, 19, 20, 21, 1279 22, 23, 24, 25, 1280 -1, -1, -1, -1, 1281 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1282 61, 59, 58, 60, 62 1283 }; 1284 static const int p2m_mapping_11[] = { 1285 59, 1286 0, -1, -1, -1, 1, -1, -1, -1, 2, -1, -1, -1, 1287 3, -1, -1, -1, 4, -1, -1, -1, 5, -1, -1, -1, 1288 6, -1, -1, -1, 7, -1, -1, -1, 8, -1, -1, -1, 1289 9, -1, -1, -1, 10, -1, -1, -1, 11, -1, -1, -1, 1290 60, -1, -1, -1, 1291 12, 13, 14, 15, 1292 16, 17, 18, 19, 1293 20, 21, 22, 23, 1294 -1, -1, -1, -1, 1295 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1296 58, 62, 56, 61, 57 1297 }; 1298 static const int port_speed_max_11[] = { 1299 -1, 1300 3, -1, -1, -1, 3, -1, -1, -1, 3, -1, -1, -1, 1301 3, -1, -1, -1, 3, -1, -1, -1, 3, -1, -1, -1, 1302 3, -1, -1, -1, 3, -1, -1, -1, 3, -1, -1, -1, 1303 3, -1, -1, -1, 3, -1, -1, -1, 3, -1, -1, -1, 1304 1, -1, -1, -1, 1305 3, 3, 3, 3, 1306 3, 3, 3, 3, 1307 3, 3, 3, 3, 1308 -1, -1, -1, -1, 1309 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1310 -1, -1, -1, -1, -1 1311 }; 1312 1313 /*492 : HX4_1G_200_D*: 5xF.QSGMII + 2x(2xHGd[21]/4xHGs[11]) + 1GE */ 1314 static const int p2l_mapping_492[] = { 1315 0, 1316 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 1317 13, 14, 15, 16, 17, 18, 19, 20, -1, -1, -1, -1, 1318 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1319 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1320 41, -1, -1, -1, 1321 42, 43, 44, 45, 1322 46, 47, 48, 49, 1323 50, 51, 52, 53, 1324 -1, -1, -1, -1, 1325 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1326 61, 59, 58, 60, 62 1327 }; 1328 static const int flex_p2l_mapping_492[] = { 1329 0, 1330 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 1331 13, 14, 15, 16, 17, 18, 19, 20, -1, -1, -1, -1, 1332 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1333 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1334 41, -1, -1, -1, 1335 42, -1, -1, -1, 1336 46, -1, -1, -1, 1337 50, -1, -1, -1, 1338 -1, -1, -1, -1, 1339 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1340 61, 59, 58, 60, 62 1341 }; 1342 static const int p2m_mapping_492[] = { 1343 59, 1344 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 1345 12, 13, 14, 15, 16, 17, 18, 19, -1, -1, -1, -1, 1346 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1347 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1348 60, -1, -1, -1, 1349 48, 32, 49, 33, 1350 50, 34, 51, 35, 1351 52, 53, 54, 55, 1352 -1, -1, -1, -1, 1353 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1354 58, 62, 56, 61, 57 1355 }; 1356 static const int port_speed_max_492[] = { 1357 -1, 1358 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1359 1, 1, 1, 1, 1, 1, 1, 1, -1, -1, -1, -1, 1360 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1361 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1362 1, -1, -1, -1, 1363 42, -1, -1, -1, 1364 21, -1, 21, -1, 1365 21, -1, 21, -1, 1366 -1, -1, -1, -1, 1367 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1368 -1, -1, -1, -1, -1 1369 }; 1370 static _soc_tr3_flex_port_inf_t flex_port_inf_492 = { 1371 1, 1372 { 0, 1, 2, 3, 4, 13, 14, 15, -1 }, 1373 { _hx4_xc_flex_port_speeds, _hx4_xc_flex_port_speeds, 1374 _hx4_xc_flex_port_speeds, _hx4_xc_flex_port_speeds, 1375 _hx4_xc_flex_port_speeds, 1376 _hx4_wc_flex_port_speeds, _hx4_wc_flex_port_speeds2, 1377 _hx4_wc_flex_port_speeds2, NULL }, 1378 { _hx4_xc_def_flex_port_speeds, _hx4_xc_def_flex_port_speeds, 1379 _hx4_xc_def_flex_port_speeds, _hx4_xc_def_flex_port_speeds, 1380 _hx4_xc_def_flex_port_speeds, 1381 _hx4_wc_def_flex_port_speeds, _hx4_wc_def_flex_port_speeds, 1382 _hx4_wc_def_flex_port_speeds, NULL }, 1383 { _hx4_xc_flex_port_lanes, _hx4_xc_flex_port_lanes, 1384 _hx4_xc_flex_port_lanes, _hx4_xc_flex_port_lanes, 1385 _hx4_xc_flex_port_lanes, 1386 _hx4_wc_flex_port_lanes, _hx4_wc_flex_port_lanes2, 1387 _hx4_wc_flex_port_lanes2, NULL } 1388 }; 1389 1390 /* 7xF.QSGMII + 3xF.HG[42] + 1GE */ 1391 static const int p2l_mapping_491[] = { 1392 0, 1393 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 1394 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 1395 25, 26, 27, 28, -1, -1, -1, -1, -1, -1, -1, -1, 1396 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1397 41, -1, -1, -1, 1398 42, 43, 44, 45, 1399 46, 47, 48, 49, 1400 50, 51, 52, 53, 1401 -1, -1, -1, -1, 1402 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1403 61, 59, 58, 60, 62 1404 }; 1405 static const int flex_p2l_mapping_491[] = { 1406 0, 1407 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 1408 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 1409 25, 26, 27, 28, -1, -1, -1, -1, -1, -1, -1, -1, 1410 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1411 41, -1, -1, -1, 1412 42, -1, -1, -1, 1413 46, -1, -1, -1, 1414 50, -1, -1, -1, 1415 -1, -1, -1, -1, 1416 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1417 61, 59, 58, 60, 62 1418 }; 1419 static const int p2m_mapping_491[] = { 1420 59, 1421 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 1422 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 1423 24, 25, 26, 27, -1, -1, -1, -1, -1, -1, -1, -1, 1424 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1425 60, -1, -1, -1, 1426 48, 32, 49, 33, 1427 50, 34, 51, 35, 1428 52, 53, 54, 55, 1429 -1, -1, -1, -1, 1430 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1431 58, 62, 56, 61, 57 1432 }; 1433 static const int port_speed_max_491[] = { 1434 -1, 1435 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1436 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1437 1, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1, 1438 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1439 1, -1, -1, -1, 1440 42, -1, -1, -1, 1441 42, -1, -1, -1, 1442 42, -1, -1, -1, 1443 -1, -1, -1, -1, 1444 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1445 -1, -1, -1, -1, -1 1446 }; 1447 static _soc_tr3_flex_port_inf_t flex_port_inf_491 = { 1448 1, 1449 { 0, 1, 2, 3, 4, 5, 6, 13, 14, 15, -1 }, 1450 { _hx4_xc_flex_port_speeds, _hx4_xc_flex_port_speeds, 1451 _hx4_xc_flex_port_speeds, _hx4_xc_flex_port_speeds, 1452 _hx4_xc_flex_port_speeds, _hx4_xc_flex_port_speeds, 1453 _hx4_xc_flex_port_speeds, 1454 _tr3_wc_flex_port_speeds_1, _tr3_wc_flex_port_speeds_1, 1455 _tr3_wc_flex_port_speeds_1, NULL }, 1456 { _hx4_xc_def_flex_port_speeds, _hx4_xc_def_flex_port_speeds, 1457 _hx4_xc_def_flex_port_speeds, _hx4_xc_def_flex_port_speeds, 1458 _hx4_xc_def_flex_port_speeds, _hx4_xc_def_flex_port_speeds, 1459 _hx4_xc_def_flex_port_speeds, 1460 _tr3_wc_def_flex_port_speeds_1, _tr3_wc_def_flex_port_speeds_1, 1461 _tr3_wc_def_flex_port_speeds_1, NULL }, 1462 { _hx4_xc_flex_port_lanes, _hx4_xc_flex_port_lanes, 1463 _hx4_xc_flex_port_lanes, _hx4_xc_flex_port_lanes, 1464 _hx4_xc_flex_port_lanes, _hx4_xc_flex_port_lanes, 1465 _hx4_xc_flex_port_lanes, 1466 _tr3_wc_flex_port_lanes_1, _tr3_wc_flex_port_lanes_1, 1467 _tr3_wc_flex_port_lanes_1, NULL } 1468 }; 1469 /* 10xF.QSGMII + 3xF.HG[42] + 1GE */ 1470 static const int p2l_mapping_490[] = { 1471 0, 1472 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 1473 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 1474 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 1475 37, 38, 39, 40, -1, -1, -1, -1, -1, -1, -1, -1, 1476 41, -1, -1, -1, 1477 42, 43, 44, 45, 1478 46, 47, 48, 49, 1479 50, 51, 52, 53, 1480 -1, -1, -1, -1, 1481 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1482 61, 59, 58, 60, 62 1483 }; 1484 static const int flex_p2l_mapping_490[] = { 1485 0, 1486 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 1487 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 1488 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 1489 37, 38, 39, 40, -1, -1, -1, -1, -1, -1, -1, -1, 1490 41, -1, -1, -1, 1491 42, -1, -1, -1, 1492 46, -1, -1, -1, 1493 50, -1, -1, -1, 1494 -1, -1, -1, -1, 1495 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1496 61, 59, 58, 60, 62 1497 }; 1498 static const int p2m_mapping_490[] = { 1499 59, 1500 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 1501 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 1502 24, 25, 26, 27, 28, 29, 30, 31, 36, 37, 38, 39, 1503 41, 42, 43, 44, -1, -1, -1, -1, -1, -1, -1, -1, 1504 60, -1, -1, -1, 1505 48, 32, 49, 33, 1506 50, 34, 51, 35, 1507 52, 53, 54, 55, 1508 -1, -1, -1, -1, 1509 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1510 58, 62, 56, 61, 57 1511 }; 1512 static const int port_speed_max_490[] = { 1513 -1, 1514 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1515 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1516 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1517 1, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1, 1518 1, -1, -1, -1, 1519 42, -1, -1, -1, 1520 42, -1, -1, -1, 1521 42, -1, -1, -1, 1522 -1, -1, -1, -1, 1523 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1524 -1, -1, -1, -1, -1 1525 }; 1526 static _soc_tr3_flex_port_inf_t flex_port_inf_490 = { 1527 1, 1528 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 13, 14, 15, -1 }, 1529 { _hx4_xc_flex_port_speeds, _hx4_xc_flex_port_speeds, 1530 _hx4_xc_flex_port_speeds, _hx4_xc_flex_port_speeds, 1531 _hx4_xc_flex_port_speeds, _hx4_xc_flex_port_speeds, 1532 _hx4_xc_flex_port_speeds, _hx4_xc_flex_port_speeds, 1533 _hx4_xc_flex_port_speeds, _hx4_xc_flex_port_speeds, 1534 _tr3_wc_flex_port_speeds_1, _tr3_wc_flex_port_speeds_1, 1535 _tr3_wc_flex_port_speeds_1, NULL }, 1536 { _hx4_xc_def_flex_port_speeds, _hx4_xc_def_flex_port_speeds, 1537 _hx4_xc_def_flex_port_speeds, _hx4_xc_def_flex_port_speeds, 1538 _hx4_xc_def_flex_port_speeds, _hx4_xc_def_flex_port_speeds, 1539 _hx4_xc_def_flex_port_speeds, _hx4_xc_def_flex_port_speeds, 1540 _hx4_xc_def_flex_port_speeds, _hx4_xc_def_flex_port_speeds, 1541 _tr3_wc_def_flex_port_speeds_1, _tr3_wc_def_flex_port_speeds_1, 1542 _tr3_wc_def_flex_port_speeds_1, NULL }, 1543 { _hx4_xc_flex_port_lanes, _hx4_xc_flex_port_lanes, 1544 _hx4_xc_flex_port_lanes, _hx4_xc_flex_port_lanes, 1545 _hx4_xc_flex_port_lanes, _hx4_xc_flex_port_lanes, 1546 _hx4_xc_flex_port_lanes, _hx4_xc_flex_port_lanes, 1547 _hx4_xc_flex_port_lanes, _hx4_xc_flex_port_lanes, 1548 _tr3_wc_flex_port_lanes_1, _tr3_wc_flex_port_lanes_1, 1549 _tr3_wc_flex_port_lanes_1, NULL } 1550 }; 1551 /* 12xF.QSGMII + 2xF.HG[42] + 1GE */ 1552 static const int p2l_mapping_500[] = { 1553 0, 1554 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 1555 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 1556 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 1557 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 1558 49, -1, -1, -1, 1559 50, 51, 52, 53, 1560 54, 55, 56, 57, 1561 -1, -1, -1, -1, 1562 -1, -1, -1, -1, 1563 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1564 61, 59, 58, 60, 62 1565 }; 1566 static const int flex_p2l_mapping_500[] = { 1567 0, 1568 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 1569 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 1570 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 1571 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 1572 49, -1, -1, -1, 1573 50, -1, -1, -1, 1574 54, -1, -1, -1, 1575 -1, -1, -1, -1, 1576 -1, -1, -1, -1, 1577 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1578 61, 59, 58, 60, 62 1579 }; 1580 static const int p2m_mapping_500[] = { 1581 59, 1582 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 1583 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 1584 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 1585 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 1586 60, -1, -1, -1, 1587 48, 49, 50, 51, 1588 52, 53, 54, 55, 1589 -1, -1, -1, -1, 1590 -1, -1, -1, -1, 1591 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1592 58, 62, 56, 61, 57 1593 }; 1594 static const int port_speed_max_500[] = { 1595 -1, 1596 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1597 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1598 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1599 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1600 1, -1, -1, -1, 1601 42, -1, -1, -1, 1602 42, -1, -1, -1, 1603 -1, -1, -1, -1, 1604 -1, -1, -1, -1, 1605 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1606 11, -1, -1, -1, -1 1607 }; 1608 static _soc_tr3_flex_port_inf_t flex_port_inf_500 = { 1609 1, 1610 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13, 14, -1 }, 1611 { _hx4_xc_flex_port_speeds, _hx4_xc_flex_port_speeds, 1612 _hx4_xc_flex_port_speeds, _hx4_xc_flex_port_speeds, 1613 _hx4_xc_flex_port_speeds, _hx4_xc_flex_port_speeds, 1614 _hx4_xc_flex_port_speeds, _hx4_xc_flex_port_speeds, 1615 _hx4_xc_flex_port_speeds, _hx4_xc_flex_port_speeds, 1616 _hx4_xc_flex_port_speeds, _hx4_xc_flex_port_speeds, 1617 _tr3_wc_flex_port_speeds_1, _tr3_wc_flex_port_speeds_1, 1618 NULL }, 1619 { _hx4_xc_def_flex_port_speeds, _hx4_xc_def_flex_port_speeds, 1620 _hx4_xc_def_flex_port_speeds, _hx4_xc_def_flex_port_speeds, 1621 _hx4_xc_def_flex_port_speeds, _hx4_xc_def_flex_port_speeds, 1622 _hx4_xc_def_flex_port_speeds, _hx4_xc_def_flex_port_speeds, 1623 _hx4_xc_def_flex_port_speeds, _hx4_xc_def_flex_port_speeds, 1624 _hx4_xc_def_flex_port_speeds, _hx4_xc_def_flex_port_speeds, 1625 _tr3_wc_def_flex_port_speeds_1, _tr3_wc_def_flex_port_speeds_1, 1626 NULL }, 1627 { _hx4_xc_flex_port_lanes, _hx4_xc_flex_port_lanes, 1628 _hx4_xc_flex_port_lanes, _hx4_xc_flex_port_lanes, 1629 _hx4_xc_flex_port_lanes, _hx4_xc_flex_port_lanes, 1630 _hx4_xc_flex_port_lanes, _hx4_xc_flex_port_lanes, 1631 _hx4_xc_flex_port_lanes, _hx4_xc_flex_port_lanes, 1632 _hx4_xc_flex_port_lanes, _hx4_xc_flex_port_lanes, 1633 _tr3_wc_flex_port_lanes_1, _tr3_wc_flex_port_lanes_1, 1634 NULL } 1635 }; 1636 /* 12xF.QSGMII + F.HG[42] + 2xHG[42] + 1GE */ 1637 static const int p2l_mapping_495[] = { 1638 0, 1639 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 1640 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 1641 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 1642 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 1643 49, -1, -1, -1, 1644 50, 51, 52, 53, 1645 54, -1, -1, -1, 1646 55, -1, -1, -1, 1647 -1, -1, -1, -1, 1648 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1649 61, 59, 58, 60, 62 1650 }; 1651 static const int flex_p2l_mapping_495[] = { 1652 0, 1653 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 1654 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 1655 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 1656 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 1657 49, -1, -1, -1, 1658 50, -1, -1, -1, 1659 54, -1, -1, -1, 1660 55, -1, -1, -1, 1661 -1, -1, -1, -1, 1662 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1663 61, 59, 58, 60, 62 1664 }; 1665 static const int p2m_mapping_495[] = { 1666 59, 1667 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 1668 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 1669 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 1670 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 1671 60, -1, -1, -1, 1672 48, 49, 50, 51, 1673 52, -1, -1, -1, 1674 53, -1, -1, -1, 1675 -1, -1, -1, -1, 1676 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1677 58, 62, 56, 61, 57 1678 }; 1679 static const int port_speed_max_495[] = { 1680 -1, 1681 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1682 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1683 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1684 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1685 1, -1, -1, -1, 1686 42, -1, -1, -1, 1687 42, -1, -1, -1, 1688 42, -1, -1, -1, 1689 -1, -1, -1, -1, 1690 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1691 -1, -1, -1, -1, -1 1692 }; 1693 static _soc_tr3_flex_port_inf_t flex_port_inf_495 = { 1694 1, 1695 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13, -1 }, 1696 { _hx4_xc_flex_port_speeds, _hx4_xc_flex_port_speeds, 1697 _hx4_xc_flex_port_speeds, _hx4_xc_flex_port_speeds, 1698 _hx4_xc_flex_port_speeds, _hx4_xc_flex_port_speeds, 1699 _hx4_xc_flex_port_speeds, _hx4_xc_flex_port_speeds, 1700 _hx4_xc_flex_port_speeds, _hx4_xc_flex_port_speeds, 1701 _hx4_xc_flex_port_speeds, _hx4_xc_flex_port_speeds, 1702 _tr3_wc_flex_port_speeds_1, NULL }, 1703 { _hx4_xc_def_flex_port_speeds, _hx4_xc_def_flex_port_speeds, 1704 _hx4_xc_def_flex_port_speeds, _hx4_xc_def_flex_port_speeds, 1705 _hx4_xc_def_flex_port_speeds, _hx4_xc_def_flex_port_speeds, 1706 _hx4_xc_def_flex_port_speeds, _hx4_xc_def_flex_port_speeds, 1707 _hx4_xc_def_flex_port_speeds, _hx4_xc_def_flex_port_speeds, 1708 _hx4_xc_def_flex_port_speeds, _hx4_xc_def_flex_port_speeds, 1709 _tr3_wc_def_flex_port_speeds_1, NULL }, 1710 { _hx4_xc_flex_port_lanes, _hx4_xc_flex_port_lanes, 1711 _hx4_xc_flex_port_lanes, _hx4_xc_flex_port_lanes, 1712 _hx4_xc_flex_port_lanes, _hx4_xc_flex_port_lanes, 1713 _hx4_xc_flex_port_lanes, _hx4_xc_flex_port_lanes, 1714 _hx4_xc_flex_port_lanes, _hx4_xc_flex_port_lanes, 1715 _hx4_xc_flex_port_lanes, _hx4_xc_flex_port_lanes, 1716 _tr3_wc_flex_port_lanes_1, NULL } 1717 }; 1718 /* 10xF.QSGMII + 3xFlex[4x10] + 1GE */ 1719 static const int p2l_mapping_497[] = { 1720 0, 1721 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 1722 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 1723 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 1724 37, 38, 39, 40, -1, -1, -1, -1, -1, -1, -1, -1, 1725 41, -1, -1, -1, 1726 42, 43, 44, 45, 1727 46, 47, 48, 49, 1728 50, 51, 52, 53, 1729 -1, -1, -1, -1, 1730 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1731 61, 59, 58, 60, 62 1732 }; 1733 static const int flex_p2l_mapping_497[] = { 1734 0, 1735 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 1736 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 1737 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 1738 37, 38, 39, 40, -1, -1, -1, -1, -1, -1, -1, -1, 1739 41, -1, -1, -1, 1740 42, -1, -1, -1, 1741 46, -1, -1, -1, 1742 50, -1, -1, -1, 1743 -1, -1, -1, -1, 1744 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1745 61, 59, 58, 60, 62 1746 }; 1747 static const int p2m_mapping_497[] = { 1748 59, 1749 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 1750 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 1751 24, 25, 26, 27, 28, 29, 30, 31, 36, 37, 38, 39, 1752 41, 42, 43, 44, -1, -1, -1, -1, -1, -1, -1, -1, 1753 60, -1, -1, -1, 1754 48, 32, 49, 33, 1755 50, 34, 51, 35, 1756 52, 53, 54, 55, 1757 -1, -1, -1, -1, 1758 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1759 58, 62, 56, 61, 57 1760 }; 1761 static const int port_speed_max_497[] = { 1762 -1, 1763 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1764 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1765 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1766 1, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1, 1767 1, -1, -1, -1, 1768 21, -1, -1, -1, 1769 21, -1, -1, -1, 1770 21, -1, -1, -1, 1771 -1, -1, -1, -1, 1772 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1773 -1, -1, -1, -1, -1 1774 }; 1775 static _soc_tr3_flex_port_inf_t flex_port_inf_497 = { 1776 1, 1777 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 13, 14, 15, -1 }, 1778 { _hx4_xc_flex_port_speeds, _hx4_xc_flex_port_speeds, 1779 _hx4_xc_flex_port_speeds, _hx4_xc_flex_port_speeds, 1780 _hx4_xc_flex_port_speeds, _hx4_xc_flex_port_speeds, 1781 _hx4_xc_flex_port_speeds, _hx4_xc_flex_port_speeds, 1782 _hx4_xc_flex_port_speeds, _hx4_xc_flex_port_speeds, 1783 _hx4_wc_flex_port_speeds, _hx4_wc_flex_port_speeds, 1784 _hx4_wc_flex_port_speeds, NULL }, 1785 { _hx4_xc_def_flex_port_speeds, _hx4_xc_def_flex_port_speeds, 1786 _hx4_xc_def_flex_port_speeds, _hx4_xc_def_flex_port_speeds, 1787 _hx4_xc_def_flex_port_speeds, _hx4_xc_def_flex_port_speeds, 1788 _hx4_xc_def_flex_port_speeds, _hx4_xc_def_flex_port_speeds, 1789 _hx4_xc_def_flex_port_speeds, _hx4_xc_def_flex_port_speeds, 1790 _hx4_wc_def_flex_port_speeds, _hx4_wc_def_flex_port_speeds, 1791 _hx4_wc_def_flex_port_speeds, NULL }, 1792 { _hx4_xc_flex_port_lanes, _hx4_xc_flex_port_lanes, 1793 _hx4_xc_flex_port_lanes, _hx4_xc_flex_port_lanes, 1794 _hx4_xc_flex_port_lanes, _hx4_xc_flex_port_lanes, 1795 _hx4_xc_flex_port_lanes, _hx4_xc_flex_port_lanes, 1796 _hx4_xc_flex_port_lanes, _hx4_xc_flex_port_lanes, 1797 _hx4_wc_flex_port_lanes, _hx4_wc_flex_port_lanes, 1798 _hx4_wc_flex_port_lanes, NULL } 1799 }; 1800 /* 12xF.QSGMII + 2xFlex[4x10] + 1GE */ 1801 static const int p2l_mapping_510[] = { 1802 0, 1803 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 1804 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 1805 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 1806 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 1807 49, -1, -1, -1, 1808 50, 51, 52, 53, 1809 54, 55, 56, 57, 1810 -1, -1, -1, -1, 1811 -1, -1, -1, -1, 1812 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1813 61, 59, 58, 60, 62 1814 }; 1815 static const int flex_p2l_mapping_510[] = { 1816 0, 1817 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 1818 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 1819 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 1820 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 1821 49, -1, -1, -1, 1822 50, -1, -1, -1, 1823 54, -1, -1, -1, 1824 -1, -1, -1, -1, 1825 -1, -1, -1, -1, 1826 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1827 61, 59, 58, 60, 62 1828 }; 1829 static const int p2m_mapping_510[] = { 1830 59, 1831 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 1832 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 1833 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 1834 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 1835 60, -1, -1, -1, 1836 48, 49, 50, 51, 1837 52, 53, 54, 55, 1838 -1, -1, -1, -1, 1839 -1, -1, -1, -1, 1840 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1841 58, 62, 56, 61, 57 1842 }; 1843 static const int port_speed_max_510[] = { 1844 -1, 1845 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1846 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1847 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1848 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1849 1, -1, -1, -1, 1850 21, -1, -1, -1, 1851 21, -1, -1, -1, 1852 -1, -1, -1, -1, 1853 -1, -1, -1, -1, 1854 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1855 -1, -1, -1, -1, -1 1856 }; 1857 static _soc_tr3_flex_port_inf_t flex_port_inf_510 = { 1858 1, 1859 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13, 14, -1 }, 1860 { _hx4_xc_flex_port_speeds, _hx4_xc_flex_port_speeds, 1861 _hx4_xc_flex_port_speeds, _hx4_xc_flex_port_speeds, 1862 _hx4_xc_flex_port_speeds, _hx4_xc_flex_port_speeds, 1863 _hx4_xc_flex_port_speeds, _hx4_xc_flex_port_speeds, 1864 _hx4_xc_flex_port_speeds, _hx4_xc_flex_port_speeds, 1865 _hx4_xc_flex_port_speeds, _hx4_xc_flex_port_speeds, 1866 _hx4_wc_flex_port_speeds, _hx4_wc_flex_port_speeds, 1867 NULL }, 1868 { _hx4_xc_def_flex_port_speeds, _hx4_xc_def_flex_port_speeds, 1869 _hx4_xc_def_flex_port_speeds, _hx4_xc_def_flex_port_speeds, 1870 _hx4_xc_def_flex_port_speeds, _hx4_xc_def_flex_port_speeds, 1871 _hx4_xc_def_flex_port_speeds, _hx4_xc_def_flex_port_speeds, 1872 _hx4_xc_def_flex_port_speeds, _hx4_xc_def_flex_port_speeds, 1873 _hx4_xc_def_flex_port_speeds, _hx4_xc_def_flex_port_speeds, 1874 _hx4_wc_def_flex_port_speeds, _hx4_wc_def_flex_port_speeds, 1875 NULL }, 1876 { _hx4_xc_flex_port_lanes, _hx4_xc_flex_port_lanes, 1877 _hx4_xc_flex_port_lanes, _hx4_xc_flex_port_lanes, 1878 _hx4_xc_flex_port_lanes, _hx4_xc_flex_port_lanes, 1879 _hx4_xc_flex_port_lanes, _hx4_xc_flex_port_lanes, 1880 _hx4_xc_flex_port_lanes, _hx4_xc_flex_port_lanes, 1881 _hx4_xc_flex_port_lanes, _hx4_xc_flex_port_lanes, 1882 _hx4_wc_flex_port_lanes, _hx4_wc_flex_port_lanes, 1883 NULL } 1884 }; 1885 /* 7xF.QSGMII + Flex[4x10] + 2xHG[21] + 1GE */ 1886 static const int p2l_mapping_460[] = { 1887 0, 1888 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 1889 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 1890 25, 26, 27, 28, -1, -1, -1, -1, -1, -1, -1, -1, 1891 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1892 49, -1, -1, -1, 1893 50, 51, 52, 53, 1894 54, -1, -1, -1, 1895 55, -1, -1, -1, 1896 -1, -1, -1, -1, 1897 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1898 61, 59, 58, 60, 62 1899 }; 1900 static const int flex_p2l_mapping_460[] = { 1901 0, 1902 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 1903 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 1904 25, 26, 27, 28, -1, -1, -1, -1, -1, -1, -1, -1, 1905 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1906 49, -1, -1, -1, 1907 50, -1, -1, -1, 1908 54, -1, -1, -1, 1909 55, -1, -1, -1, 1910 -1, -1, -1, -1, 1911 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1912 61, 59, 58, 60, 62 1913 }; 1914 static const int p2m_mapping_460[] = { 1915 59, 1916 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 1917 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 1918 24, 25, 26, 27, -1, -1, -1, -1, -1, -1, -1, -1, 1919 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1920 60, -1, -1, -1, 1921 48, 49, 50, 51, 1922 52, -1, -1, -1, 1923 53, -1, -1, -1, 1924 -1, -1, -1, -1, 1925 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1926 58, 62, 56, 61, 57 1927 }; 1928 static const int port_speed_max_460[] = { 1929 -1, 1930 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1931 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1932 1, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1, 1933 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1934 1, -1, -1, -1, 1935 21, -1, -1, -1, 1936 21, -1, -1, -1, 1937 21, -1, -1, -1, 1938 -1, -1, -1, -1, 1939 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1940 -1, -1, -1, -1, -1 1941 }; 1942 static _soc_tr3_flex_port_inf_t flex_port_inf_460 = { 1943 1, 1944 { 0, 1, 2, 3, 4, 5, 6, 13, -1 }, 1945 { _hx4_xc_flex_port_speeds, _hx4_xc_flex_port_speeds, 1946 _hx4_xc_flex_port_speeds, _hx4_xc_flex_port_speeds, 1947 _hx4_xc_flex_port_speeds, _hx4_xc_flex_port_speeds, 1948 _hx4_xc_flex_port_speeds, _hx4_wc_flex_port_speeds, 1949 NULL }, 1950 { _hx4_xc_def_flex_port_speeds, _hx4_xc_def_flex_port_speeds, 1951 _hx4_xc_def_flex_port_speeds, _hx4_xc_def_flex_port_speeds, 1952 _hx4_xc_def_flex_port_speeds, _hx4_xc_def_flex_port_speeds, 1953 _hx4_xc_def_flex_port_speeds, _hx4_wc_def_flex_port_speeds, 1954 NULL }, 1955 { _hx4_xc_flex_port_lanes, _hx4_xc_flex_port_lanes, 1956 _hx4_xc_flex_port_lanes, _hx4_xc_flex_port_lanes, 1957 _hx4_xc_flex_port_lanes, _hx4_xc_flex_port_lanes, 1958 _hx4_xc_flex_port_lanes, _hx4_wc_flex_port_lanes, 1959 NULL } 1960 }; 1961 /*462 : 7xF.QSGMII + 2xFlex[4x10] + 1GE*/ 1962 static const int port_speed_max_462[] = { 1963 -1, 1964 3, 1, 1, 1, 3, 1, 1, 1, 3, 1, 1, 1, 1965 3, 1, 1, 1, 3, 1, 1, 1, 3, 1, 1, 1, 1966 3, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1, 1967 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1968 1, -1, -1, -1, 1969 21, -1, -1, -1, 1970 21, -1, -1, -1, 1971 21, -1, -1, -1, 1972 -1, -1, -1, -1, 1973 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1974 -1, -1, -1, -1, -1 1975 }; 1976 1977 /*463: HX4_1G_130*:7xF.QSGMII +Flex[4x10]+ 2x(1xHGd[21]/2xHGs[11/10]) + 1GE */ 1978 static const int p2l_mapping_463[] = { 1979 0, 1980 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 1981 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 1982 25, 26, 27, 28, -1, -1, -1, -1, -1, -1, -1, -1, 1983 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1984 49, -1, -1, -1, 1985 50, 51, 52, 53, 1986 54, 55, -1, -1, 1987 56, 57, -1, -1, 1988 -1, -1, -1, -1, 1989 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1990 61, 59, 58, 60, 62 1991 }; 1992 static const int flex_p2l_mapping_463[] = { 1993 0, 1994 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 1995 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 1996 25, 26, 27, 28, -1, -1, -1, -1, -1, -1, -1, -1, 1997 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 1998 49, -1, -1, -1, 1999 50, -1, -1, -1, 2000 54, -1, -1, -1, 2001 56, -1, -1, -1, 2002 -1, -1, -1, -1, 2003 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2004 61, 59, 58, 60, 62 2005 }; 2006 static const int p2m_mapping_463[] = { 2007 59, 2008 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 2009 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 2010 24, 25, 26, 27, -1, -1, -1, -1, -1, -1, -1, -1, 2011 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2012 60, -1, -1, -1, 2013 48, 49, 50, 51, 2014 52, 53, -1, -1, 2015 54, 55, -1, -1, 2016 -1, -1, -1, -1, 2017 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2018 58, 62, 56, 61, 57 2019 }; 2020 static const int port_speed_max_463[] = { 2021 -1, 2022 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2023 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2024 1, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1, 2025 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2026 1, -1, -1, -1, 2027 21, -1, -1, -1, 2028 21, -1, -1, -1, 2029 21, -1, -1, -1, 2030 -1, -1, -1, -1, 2031 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2032 -1, -1, -1, -1, -1 2033 }; 2034 static _soc_tr3_flex_port_inf_t flex_port_inf_463 = { 2035 1, 2036 { 0, 1, 2, 3, 4, 5, 6, 13, 14, 15, -1 }, 2037 { _hx4_xc_flex_port_speeds, _hx4_xc_flex_port_speeds, 2038 _hx4_xc_flex_port_speeds, _hx4_xc_flex_port_speeds, 2039 _hx4_xc_flex_port_speeds, _hx4_xc_flex_port_speeds, 2040 _hx4_xc_flex_port_speeds, _hx4_wc_flex_port_speeds, 2041 _hx4_wc_flex_port_speeds2, _hx4_wc_flex_port_speeds2, 2042 NULL }, 2043 { _hx4_xc_def_flex_port_speeds, _hx4_xc_def_flex_port_speeds, 2044 _hx4_xc_def_flex_port_speeds, _hx4_xc_def_flex_port_speeds, 2045 _hx4_xc_def_flex_port_speeds, _hx4_xc_def_flex_port_speeds, 2046 _hx4_xc_def_flex_port_speeds, _hx4_wc_def_flex_port_speeds, 2047 _hx4_wc_def_flex_port_speeds, _hx4_wc_def_flex_port_speeds, 2048 NULL }, 2049 { _hx4_xc_flex_port_lanes, _hx4_xc_flex_port_lanes, 2050 _hx4_xc_flex_port_lanes, _hx4_xc_flex_port_lanes, 2051 _hx4_xc_flex_port_lanes, _hx4_xc_flex_port_lanes, 2052 _hx4_xc_flex_port_lanes, _hx4_wc_flex_port_lanes, 2053 _hx4_wc_flex_port_lanes2, _hx4_wc_flex_port_lanes2, 2054 NULL } 2055 }; 2056 2057 2058 2059 static const int p2l_mapping_464[] = { 2060 0, 2061 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 2062 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 2063 25, 26, 27, 28, -1, -1, -1, -1, -1, -1, -1, -1, 2064 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2065 41, -1, -1, -1, 2066 42, 43, 44, 45, 2067 46, 47, 48, 49, 2068 50, 51, 52, 53, 2069 -1, -1, -1, -1, 2070 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2071 61, 59, 58, 60, 62 2072 }; 2073 static const int flex_p2l_mapping_464[] = { 2074 0, 2075 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 2076 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 2077 25, 26, 27, 28, -1, -1, -1, -1, -1, -1, -1, -1, 2078 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2079 41, -1, -1, -1, 2080 42, -1, -1, -1, 2081 46, -1, -1, -1, 2082 50, -1, -1, -1, 2083 -1, -1, -1, -1, 2084 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2085 61, 59, 58, 60, 62 2086 }; 2087 static const int p2m_mapping_464[] = { 2088 59, 2089 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 2090 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 2091 24, 25, 26, 27, -1, -1, -1, -1, -1, -1, -1, -1, 2092 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2093 60, -1, -1, -1, 2094 48, 49, 50, 51, 2095 52, 28, 29, 30, 2096 53, 31, 32, 33, 2097 -1, -1, -1, -1, 2098 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2099 58, 62, 56, 61, 57 2100 }; 2101 static _soc_tr3_flex_port_inf_t flex_port_inf_464 = { 2102 1, 2103 { 0, 1, 2, 3, 4, 5, 6, 13, 14, 15, -1 }, 2104 { _hx4_xc_flex_port_speeds, _hx4_xc_flex_port_speeds, 2105 _hx4_xc_flex_port_speeds, _hx4_xc_flex_port_speeds, 2106 _hx4_xc_flex_port_speeds, _hx4_xc_flex_port_speeds, 2107 _hx4_xc_flex_port_speeds, 2108 _hx4_wc_flex_port_speeds, _tr3_wc_flex_port_speeds_2, 2109 _tr3_wc_flex_port_speeds_2, NULL }, 2110 { _hx4_xc_def_flex_port_speeds, _hx4_xc_def_flex_port_speeds, 2111 _hx4_xc_def_flex_port_speeds, _hx4_xc_def_flex_port_speeds, 2112 _hx4_xc_def_flex_port_speeds, _hx4_xc_def_flex_port_speeds, 2113 _hx4_xc_def_flex_port_speeds, 2114 _hx4_wc_def_flex_port_speeds, _tr3_wc_def_flex_port_speeds_2, 2115 _tr3_wc_def_flex_port_speeds_2, NULL }, 2116 { _hx4_xc_flex_port_lanes, _hx4_xc_flex_port_lanes, 2117 _hx4_xc_flex_port_lanes, _hx4_xc_flex_port_lanes, 2118 _hx4_xc_flex_port_lanes, _hx4_xc_flex_port_lanes, 2119 _hx4_xc_flex_port_lanes, 2120 _hx4_wc_flex_port_lanes, _tr3_wc_flex_port_lanes_2, 2121 _tr3_wc_flex_port_lanes_2, NULL } 2122 }; 2123 2124 /* 12xF.QSGMII + Flex[4x10] + 2xHG[21]/1GE + 1GE */ 2125 static const int p2l_mapping_410[] = { 2126 0, 2127 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 2128 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 2129 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 2130 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 2131 49, -1, -1, -1, 2132 50, 51, 52, 53, 2133 54, -1, -1, -1, 2134 55, -1, -1, -1, 2135 -1, -1, -1, -1, 2136 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2137 61, 59, 58, 60, 62 2138 }; 2139 static const int flex_p2l_mapping_410[] = { 2140 0, 2141 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 2142 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 2143 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 2144 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 2145 49, -1, -1, -1, 2146 50, -1, -1, -1, 2147 54, -1, -1, -1, 2148 55, -1, -1, -1, 2149 -1, -1, -1, -1, 2150 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2151 61, 59, 58, 60, 62 2152 }; 2153 static const int p2m_mapping_410[] = { 2154 59, 2155 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 2156 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 2157 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 2158 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 2159 60, -1, -1, -1, 2160 48, 49, 50, 51, 2161 52, -1, -1, -1, 2162 53, -1, -1, -1, 2163 -1, -1, -1, -1, 2164 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2165 58, 62, 56, 61, 57 2166 }; 2167 static const int port_speed_max_410[] = { 2168 -1, 2169 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2170 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2171 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2172 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2173 1, -1, -1, -1, 2174 21, -1, -1, -1, 2175 21, -1, -1, -1, 2176 21, -1, -1, -1, 2177 -1, -1, -1, -1, 2178 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2179 -1, -1, -1, -1, -1 2180 }; 2181 static _soc_tr3_flex_port_inf_t flex_port_inf_410 = { 2182 1, 2183 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13, -1 }, 2184 { _hx4_xc_flex_port_speeds, _hx4_xc_flex_port_speeds, 2185 _hx4_xc_flex_port_speeds, _hx4_xc_flex_port_speeds, 2186 _hx4_xc_flex_port_speeds, _hx4_xc_flex_port_speeds, 2187 _hx4_xc_flex_port_speeds, _hx4_xc_flex_port_speeds, 2188 _hx4_xc_flex_port_speeds, _hx4_xc_flex_port_speeds, 2189 _hx4_xc_flex_port_speeds, _hx4_xc_flex_port_speeds, 2190 _hx4_wc_flex_port_speeds, NULL }, 2191 { _hx4_xc_def_flex_port_speeds, _hx4_xc_def_flex_port_speeds, 2192 _hx4_xc_def_flex_port_speeds, _hx4_xc_def_flex_port_speeds, 2193 _hx4_xc_def_flex_port_speeds, _hx4_xc_def_flex_port_speeds, 2194 _hx4_xc_def_flex_port_speeds, _hx4_xc_def_flex_port_speeds, 2195 _hx4_xc_def_flex_port_speeds, _hx4_xc_def_flex_port_speeds, 2196 _hx4_xc_def_flex_port_speeds, _hx4_xc_def_flex_port_speeds, 2197 _hx4_wc_def_flex_port_speeds, NULL }, 2198 { _hx4_xc_flex_port_lanes, _hx4_xc_flex_port_lanes, 2199 _hx4_xc_flex_port_lanes, _hx4_xc_flex_port_lanes, 2200 _hx4_xc_flex_port_lanes, _hx4_xc_flex_port_lanes, 2201 _hx4_xc_flex_port_lanes, _hx4_xc_flex_port_lanes, 2202 _hx4_xc_flex_port_lanes, _hx4_xc_flex_port_lanes, 2203 _hx4_xc_flex_port_lanes, _hx4_xc_flex_port_lanes, 2204 _hx4_wc_flex_port_lanes, NULL } 2205 }; 2206 /* 12xF.QSGMII + Flex[4x10] + 2xHG[21] + 1GE */ 2207 static const int port_speed_max_412[] = { 2208 -1, 2209 3, 1, 1, 1, 3, 1, 1, 1, 3, 1, 1, 1, 2210 3, 1, 1, 1, 3, 1, 1, 1, 3, 1, 1, 1, 2211 3, 1, 1, 1, 3, 1, 1, 1, 3, 1, 1, 1, 2212 3, 1, 1, 1, 3, 1, 1, 1, 3, 1, 1, 1, 2213 1, -1, -1, -1, 2214 21, -1, -1, -1, 2215 21, -1, -1, -1, 2216 21, -1, -1, -1, 2217 -1, -1, -1, -1, 2218 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2219 -1, -1, -1, -1, -1 2220 }; 2221 2222 static _soc_tr3_flex_port_inf_t flex_port_inf_412 = { 2223 1, 2224 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13, -1 }, 2225 { _hx4_xc_flex_port_speeds, _hx4_xc_flex_port_speeds, 2226 _hx4_xc_flex_port_speeds, _hx4_xc_flex_port_speeds, 2227 _hx4_xc_flex_port_speeds, _hx4_xc_flex_port_speeds, 2228 _hx4_xc_flex_port_speeds, _hx4_xc_flex_port_speeds, 2229 _hx4_xc_flex_port_speeds, _hx4_xc_flex_port_speeds, 2230 _hx4_xc_flex_port_speeds, _hx4_xc_flex_port_speeds, 2231 _hx4_wc_flex_port_speeds, NULL }, 2232 { _hx4_xc_def_flex_port_speeds, _hx4_xc_def_flex_port_speeds, 2233 _hx4_xc_def_flex_port_speeds, _hx4_xc_def_flex_port_speeds, 2234 _hx4_xc_def_flex_port_speeds, _hx4_xc_def_flex_port_speeds, 2235 _hx4_xc_def_flex_port_speeds, _hx4_xc_def_flex_port_speeds, 2236 _hx4_xc_def_flex_port_speeds, _hx4_xc_def_flex_port_speeds, 2237 _hx4_xc_def_flex_port_speeds, _hx4_xc_def_flex_port_speeds, 2238 _hx4_wc_def_flex_port_speeds, NULL }, 2239 { _hx4_xc_flex_port_lanes, _hx4_xc_flex_port_lanes, 2240 _hx4_xc_flex_port_lanes, _hx4_xc_flex_port_lanes, 2241 _hx4_xc_flex_port_lanes, _hx4_xc_flex_port_lanes, 2242 _hx4_xc_flex_port_lanes, _hx4_xc_flex_port_lanes, 2243 _hx4_xc_flex_port_lanes, _hx4_xc_flex_port_lanes, 2244 _hx4_xc_flex_port_lanes, _hx4_xc_flex_port_lanes, 2245 _hx4_wc_flex_port_lanes, NULL } 2246 }; 2247 /* 413 : HX4_1G_150_B TDM#1 : 12xF.QSGMII+Flex[4x10]+2x(1xHGd[21]/2xHGs[11/10])+1GE */ 2248 static const int p2l_mapping_413[] = { 2249 0, 2250 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 2251 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 2252 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 2253 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 2254 49, -1, -1, -1, 2255 50, 51, 52, 53, 2256 54, 55, -1, -1, 2257 56, 57, -1, -1, 2258 -1, -1, -1, -1, 2259 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2260 61, 59, 58, 60, 62 2261 }; 2262 static const int flex_p2l_mapping_413[] = { 2263 0, 2264 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 2265 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 2266 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 2267 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 2268 49, -1, -1, -1, 2269 50, -1, -1, -1, 2270 54, -1, -1, -1, 2271 56, -1, -1, -1, 2272 -1, -1, -1, -1, 2273 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2274 61, 59, 58, 60, 62 2275 }; 2276 static const int p2m_mapping_413[] = { 2277 59, 2278 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 2279 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 2280 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 2281 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 2282 60, -1, -1, -1, 2283 48, 49, 50, 51, 2284 52, 53, -1, -1, 2285 54, 55, -1, -1, 2286 -1, -1, -1, -1, 2287 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2288 58, 62, 56, 61, 57 2289 }; 2290 static const int port_speed_max_413[] = { 2291 -1, 2292 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2293 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2294 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2295 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2296 1, -1, -1, -1, 2297 21, -1, -1, -1, 2298 21, -1, -1, -1, 2299 21, -1, -1, -1, 2300 -1, -1, -1, -1, 2301 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2302 -1, -1, -1, -1, -1 2303 }; 2304 static _soc_tr3_flex_port_inf_t flex_port_inf_413 = { 2305 1, 2306 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13, 14, 15, -1 }, 2307 { _hx4_xc_flex_port_speeds, _hx4_xc_flex_port_speeds, 2308 _hx4_xc_flex_port_speeds, _hx4_xc_flex_port_speeds, 2309 _hx4_xc_flex_port_speeds, _hx4_xc_flex_port_speeds, 2310 _hx4_xc_flex_port_speeds, _hx4_xc_flex_port_speeds, 2311 _hx4_xc_flex_port_speeds, _hx4_xc_flex_port_speeds, 2312 _hx4_xc_flex_port_speeds, _hx4_xc_flex_port_speeds, 2313 _hx4_wc_flex_port_speeds, _hx4_wc_flex_port_speeds2, 2314 _hx4_wc_flex_port_speeds2, NULL }, 2315 { _hx4_xc_def_flex_port_speeds, _hx4_xc_def_flex_port_speeds, 2316 _hx4_xc_def_flex_port_speeds, _hx4_xc_def_flex_port_speeds, 2317 _hx4_xc_def_flex_port_speeds, _hx4_xc_def_flex_port_speeds, 2318 _hx4_xc_def_flex_port_speeds, _hx4_xc_def_flex_port_speeds, 2319 _hx4_xc_def_flex_port_speeds, _hx4_xc_def_flex_port_speeds, 2320 _hx4_xc_def_flex_port_speeds, _hx4_xc_def_flex_port_speeds, 2321 _hx4_wc_def_flex_port_speeds, _hx4_wc_def_flex_port_speeds, 2322 _hx4_wc_def_flex_port_speeds, NULL }, 2323 { _hx4_xc_flex_port_lanes, _hx4_xc_flex_port_lanes, 2324 _hx4_xc_flex_port_lanes, _hx4_xc_flex_port_lanes, 2325 _hx4_xc_flex_port_lanes, _hx4_xc_flex_port_lanes, 2326 _hx4_xc_flex_port_lanes, _hx4_xc_flex_port_lanes, 2327 _hx4_xc_flex_port_lanes, _hx4_xc_flex_port_lanes, 2328 _hx4_xc_flex_port_lanes, _hx4_xc_flex_port_lanes, 2329 _hx4_wc_flex_port_lanes, _hx4_wc_flex_port_lanes2, 2330 _hx4_wc_flex_port_lanes2, NULL } 2331 }; 2332 2333 /* 414: HX4_1G_150_B TDM#12: 12xF.QSGMII + 2x(2xHGd[21]/4xHGs[11/10]) + 1GE */ 2334 static const int p2l_mapping_414[] = { 2335 0, 2336 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 2337 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 2338 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 2339 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 2340 49, -1, -1, -1, 2341 -1, -1, -1, -1, 2342 50, 51, 52, 53, 2343 54, 55, 56, 57, 2344 -1, -1, -1, -1, 2345 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2346 61, 59, 58, 60, 62 2347 }; 2348 static const int flex_p2l_mapping_414[] = { 2349 0, 2350 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 2351 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 2352 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 2353 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 2354 49, -1, -1, -1, 2355 -1, -1, -1, -1, 2356 50, -1, -1, -1, 2357 54, -1, -1, -1, 2358 -1, -1, -1, -1, 2359 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2360 61, 59, 58, 60, 62 2361 }; 2362 static const int p2m_mapping_414[] = { 2363 59, 2364 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 2365 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 2366 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 2367 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 2368 60, -1, -1, -1, 2369 -1, -1, -1, -1, 2370 48, 49, 50, 51, 2371 52, 53, 54, 55, 2372 -1, -1, -1, -1, 2373 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2374 58, 62, 56, 61, 57 2375 }; 2376 static const int port_speed_max_414[] = { 2377 -1, 2378 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2379 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2380 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2381 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2382 1, -1, -1, -1, 2383 -1, -1, -1, -1, 2384 21, -1, 21, -1, 2385 21, -1, 21, -1, 2386 -1, -1, -1, -1, 2387 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2388 -1, -1, -1, -1, -1 2389 }; 2390 static _soc_tr3_flex_port_inf_t flex_port_inf_414 = { 2391 1, 2392 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 14, 15, -1 }, 2393 { _hx4_xc_flex_port_speeds, _hx4_xc_flex_port_speeds, 2394 _hx4_xc_flex_port_speeds, _hx4_xc_flex_port_speeds, 2395 _hx4_xc_flex_port_speeds, _hx4_xc_flex_port_speeds, 2396 _hx4_xc_flex_port_speeds, _hx4_xc_flex_port_speeds, 2397 _hx4_xc_flex_port_speeds, _hx4_xc_flex_port_speeds, 2398 _hx4_xc_flex_port_speeds, _hx4_xc_flex_port_speeds, 2399 _hx4_wc_flex_port_speeds2, 2400 _hx4_wc_flex_port_speeds2, NULL }, 2401 { _hx4_xc_def_flex_port_speeds, _hx4_xc_def_flex_port_speeds, 2402 _hx4_xc_def_flex_port_speeds, _hx4_xc_def_flex_port_speeds, 2403 _hx4_xc_def_flex_port_speeds, _hx4_xc_def_flex_port_speeds, 2404 _hx4_xc_def_flex_port_speeds, _hx4_xc_def_flex_port_speeds, 2405 _hx4_xc_def_flex_port_speeds, _hx4_xc_def_flex_port_speeds, 2406 _hx4_xc_def_flex_port_speeds, _hx4_xc_def_flex_port_speeds, 2407 _hx4_wc_def_flex_port_speeds, 2408 _hx4_wc_def_flex_port_speeds, NULL }, 2409 { _hx4_xc_flex_port_lanes, _hx4_xc_flex_port_lanes, 2410 _hx4_xc_flex_port_lanes, _hx4_xc_flex_port_lanes, 2411 _hx4_xc_flex_port_lanes, _hx4_xc_flex_port_lanes, 2412 _hx4_xc_flex_port_lanes, _hx4_xc_flex_port_lanes, 2413 _hx4_xc_flex_port_lanes, _hx4_xc_flex_port_lanes, 2414 _hx4_xc_flex_port_lanes, _hx4_xc_flex_port_lanes, 2415 _hx4_wc_flex_port_speeds2, 2416 _hx4_wc_flex_port_speeds2, NULL } 2417 }; 2418 2419 /* 12xF.QSGMII + 4xSGMII + 2xXFI + 2xHGd[21] + 1GE */ 2420 static const int p2l_mapping_400[] = { 2421 0, 2422 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 2423 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 2424 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 2425 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 2426 49, -1, -1, -1, 2427 50, 51, 52, 53, 2428 54, 55, -1, -1, 2429 56, -1, 57, -1, 2430 -1, -1, -1, -1, 2431 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2432 61, 59, 58, 60, 62 2433 }; 2434 static const int flex_p2l_mapping_400[] = { 2435 0, 2436 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 2437 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 2438 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 2439 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 2440 49, -1, -1, -1, 2441 50, 51, 52, 53, 2442 54, 55, -1, -1, 2443 56, -1, 57, -1, 2444 -1, -1, -1, -1, 2445 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2446 61, 59, 58, 60, 62 2447 }; 2448 static const int p2m_mapping_400[] = { 2449 59, 2450 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 2451 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 2452 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 2453 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 2454 60, -1, -1, -1, 2455 48, 49, 50, 51, 2456 52, 53, -1, -1, 2457 54, -1, 55, -1, 2458 -1, -1, -1, -1, 2459 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2460 58, 62, 56, 61, 57 2461 }; 2462 static const int port_speed_max_400[] = { 2463 -1, 2464 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2465 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2466 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2467 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2468 1, -1, -1, -1, 2469 3, 3, 3, 3, 2470 10, 10, -1, -1, 2471 21, -1, 21, -1, 2472 -1, -1, -1, -1, 2473 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2474 -1, -1, -1, -1, -1 2475 }; 2476 static _soc_tr3_flex_port_inf_t flex_port_inf_400 = { 2477 1, 2478 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, -1 }, 2479 { _hx4_xc_flex_port_speeds, _hx4_xc_flex_port_speeds, 2480 _hx4_xc_flex_port_speeds, _hx4_xc_flex_port_speeds, 2481 _hx4_xc_flex_port_speeds, _hx4_xc_flex_port_speeds, 2482 _hx4_xc_flex_port_speeds, _hx4_xc_flex_port_speeds, 2483 _hx4_xc_flex_port_speeds, _hx4_xc_flex_port_speeds, 2484 _hx4_xc_flex_port_speeds, _hx4_xc_flex_port_speeds, 2485 NULL }, 2486 { _hx4_xc_def_flex_port_speeds, _hx4_xc_def_flex_port_speeds, 2487 _hx4_xc_def_flex_port_speeds, _hx4_xc_def_flex_port_speeds, 2488 _hx4_xc_def_flex_port_speeds, _hx4_xc_def_flex_port_speeds, 2489 _hx4_xc_def_flex_port_speeds, _hx4_xc_def_flex_port_speeds, 2490 _hx4_xc_def_flex_port_speeds, _hx4_xc_def_flex_port_speeds, 2491 _hx4_xc_def_flex_port_speeds, _hx4_xc_def_flex_port_speeds, 2492 NULL }, 2493 { _hx4_xc_flex_port_lanes, _hx4_xc_flex_port_lanes, 2494 _hx4_xc_flex_port_lanes, _hx4_xc_flex_port_lanes, 2495 _hx4_xc_flex_port_lanes, _hx4_xc_flex_port_lanes, 2496 _hx4_xc_flex_port_lanes, _hx4_xc_flex_port_lanes, 2497 _hx4_xc_flex_port_lanes, _hx4_xc_flex_port_lanes, 2498 _hx4_xc_flex_port_lanes, _hx4_xc_flex_port_lanes, 2499 NULL } 2500 }; 2501 /* 1xF.QSGMII + 3xFlex[4x10] + 1GE */ 2502 static const int p2l_mapping_420[] = { 2503 0, 2504 1, 2, 3, 4, -1, -1, -1, -1, -1, -1, -1, -1, 2505 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2506 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2507 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2508 5, -1, -1, -1, 2509 9, 10, 11, 12, 2510 13, 14, 15, 16, 2511 17, 18, 19, 20, 2512 -1, -1, -1, -1, 2513 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2514 61, 59, 58, 60, 62 2515 }; 2516 static const int flex_p2l_mapping_420[] = { 2517 0, 2518 1, 2, 3, 4, -1, -1, -1, -1, -1, -1, -1, -1, 2519 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2520 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2521 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2522 5, -1, -1, -1, 2523 9, -1, -1, -1, 2524 13, -1, -1, -1, 2525 17, -1, -1, -1, 2526 -1, -1, -1, -1, 2527 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2528 61, 59, 58, 60, 62 2529 }; 2530 static const int p2m_mapping_420[] = { 2531 59, 2532 1, 2, 3, 4, -1, -1, -1, -1, -1, -1, -1, -1, 2533 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2534 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2535 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2536 60, -1, -1, -1, 2537 44, 45, 46, 47, 2538 48, 49, 50, 51, 2539 52, 53, 54, 55, 2540 -1, -1, -1, -1, 2541 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2542 58, 62, 56, 61, 57 2543 }; 2544 static const int port_speed_max_420[] = { 2545 -1, 2546 1, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1, 2547 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2548 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2549 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2550 1, -1, -1, -1, 2551 21, -1, -1, -1, 2552 21, -1, -1, -1, 2553 21, -1, -1, -1, 2554 -1, -1, -1, -1, 2555 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2556 -1, -1, -1, -1, -1 2557 }; 2558 static _soc_tr3_flex_port_inf_t flex_port_inf_420 = { 2559 1, 2560 { 0, 13, 14, 15, -1 }, 2561 { _hx4_xc_flex_port_speeds, 2562 _hx4_wc_flex_port_speeds, _hx4_wc_flex_port_speeds, 2563 _hx4_wc_flex_port_speeds, NULL }, 2564 { _hx4_xc_def_flex_port_speeds, 2565 _hx4_wc_def_flex_port_speeds, _hx4_wc_def_flex_port_speeds, 2566 _hx4_wc_def_flex_port_speeds, NULL }, 2567 { _hx4_xc_flex_port_lanes, 2568 _hx4_wc_flex_port_lanes, _hx4_wc_flex_port_lanes, 2569 _hx4_wc_flex_port_lanes, NULL } 2570 }; 2571 /* 7xF.QSGMII + 2xFlex[4x10] + 1GE */ 2572 static const int p2l_mapping_514[] = { 2573 0, 2574 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 2575 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 2576 25, 26, 27, 28, -1, -1, -1, -1, -1, -1, -1, -1, 2577 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2578 49, -1, -1, -1, 2579 50, 51, 52, 53, 2580 54, 55, 56, 57, 2581 -1, -1, -1, -1, 2582 -1, -1, -1, -1, 2583 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2584 61, 59, 58, 60, 62 2585 }; 2586 static const int flex_p2l_mapping_514[] = { 2587 0, 2588 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 2589 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 2590 25, 26, 27, 28, -1, -1, -1, -1, -1, -1, -1, -1, 2591 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2592 49, -1, -1, -1, 2593 50, -1, -1, -1, 2594 54, -1, -1, -1, 2595 -1, -1, -1, -1, 2596 -1, -1, -1, -1, 2597 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2598 61, 59, 58, 60, 62 2599 }; 2600 static const int p2m_mapping_514[] = { 2601 59, 2602 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 2603 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 2604 24, 25, 26, 27, -1, -1, -1, -1, -1, -1, -1, -1, 2605 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2606 60, -1, -1, -1, 2607 48, 49, 50, 51, 2608 52, 53, 54, 55, 2609 -1, -1, -1, -1, 2610 -1, -1, -1, -1, 2611 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2612 58, 62, 56, 61, 57 2613 }; 2614 static const int port_speed_max_514[] = { 2615 -1, 2616 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2617 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2618 1, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1, 2619 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2620 1, -1, -1, -1, 2621 21, -1, -1, -1, 2622 21, -1, -1, -1, 2623 -1, -1, -1, -1, 2624 -1, -1, -1, -1, 2625 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2626 -1, -1, -1, -1, -1 2627 }; 2628 static _soc_tr3_flex_port_inf_t flex_port_inf_514 = { 2629 1, 2630 { 0, 1, 2, 3, 4, 5, 6, 13, 14, -1 }, 2631 { _hx4_xc_flex_port_speeds, _hx4_xc_flex_port_speeds, 2632 _hx4_xc_flex_port_speeds, _hx4_xc_flex_port_speeds, 2633 _hx4_xc_flex_port_speeds, _hx4_xc_flex_port_speeds, 2634 _hx4_xc_flex_port_speeds, 2635 _hx4_wc_flex_port_speeds, _hx4_wc_flex_port_speeds, 2636 NULL }, 2637 { _hx4_xc_def_flex_port_speeds, _hx4_xc_def_flex_port_speeds, 2638 _hx4_xc_def_flex_port_speeds, _hx4_xc_def_flex_port_speeds, 2639 _hx4_xc_def_flex_port_speeds, _hx4_xc_def_flex_port_speeds, 2640 _hx4_xc_def_flex_port_speeds, 2641 _hx4_wc_def_flex_port_speeds, _hx4_wc_def_flex_port_speeds, 2642 NULL }, 2643 { _hx4_xc_flex_port_lanes, _hx4_xc_flex_port_lanes, 2644 _hx4_xc_flex_port_lanes, _hx4_xc_flex_port_lanes, 2645 _hx4_xc_flex_port_lanes, _hx4_xc_flex_port_lanes, 2646 _hx4_xc_flex_port_lanes, 2647 _hx4_wc_flex_port_lanes, _hx4_wc_flex_port_lanes, 2648 NULL } 2649 }; 2650 /* 1xF.QSGMII + 3xF.HG[42] + 1GE */ 2651 static const int p2l_mapping_450[] = { 2652 0, 2653 1, 2, 3, 4, -1, -1, -1, -1, -1, -1, -1, -1, 2654 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2655 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2656 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2657 5, -1, -1, -1, 2658 9, 10, 11, 12, 2659 13, 14, 15, 16, 2660 17, 18, 19, 20, 2661 -1, -1, -1, -1, 2662 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2663 61, 59, 58, 60, 62 2664 }; 2665 static const int flex_p2l_mapping_450[] = { 2666 0, 2667 1, 2, 3, 4, -1, -1, -1, -1, -1, -1, -1, -1, 2668 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2669 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2670 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2671 5, -1, -1, -1, 2672 9, -1, -1, -1, 2673 13, -1, -1, -1, 2674 17, -1, -1, -1, 2675 -1, -1, -1, -1, 2676 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2677 61, 59, 58, 60, 62 2678 }; 2679 static const int p2m_mapping_450[] = { 2680 59, 2681 1, 2, 3, 4, -1, -1, -1, -1, -1, -1, -1, -1, 2682 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2683 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2684 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2685 60, -1, -1, -1, 2686 44, 45, 46, 47, 2687 48, 49, 50, 51, 2688 52, 53, 54, 55, 2689 -1, -1, -1, -1, 2690 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2691 58, 62, 56, 61, 57 2692 }; 2693 static const int port_speed_max_450[] = { 2694 -1, 2695 1, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1, 2696 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2697 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2698 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2699 1, -1, -1, -1, 2700 42, -1, -1, -1, 2701 42, -1, -1, -1, 2702 42, -1, -1, -1, 2703 -1, -1, -1, -1, 2704 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 2705 -1, -1, -1, -1, -1 2706 }; 2707 static _soc_tr3_flex_port_inf_t flex_port_inf_450 = { 2708 1, 2709 { 0, 13, 14, 15, -1 }, 2710 { _hx4_xc_flex_port_speeds, 2711 _tr3_wc_flex_port_speeds_1, _tr3_wc_flex_port_speeds_1, 2712 _tr3_wc_flex_port_speeds_1, NULL }, 2713 { _hx4_xc_def_flex_port_speeds, 2714 _tr3_wc_def_flex_port_speeds_1, _tr3_wc_def_flex_port_speeds_1, 2715 _tr3_wc_def_flex_port_speeds_1, NULL }, 2716 { _hx4_xc_flex_port_lanes, 2717 _tr3_wc_flex_port_lanes_1, _tr3_wc_flex_port_lanes_1, 2718 _tr3_wc_flex_port_lanes_1, NULL } 2719 }; 2720 soc_info_t *si; 2721 int rv = SOC_E_NONE; 2722 int phy_port; 2723 soc_pbmp_t pbmp_xport_xe; 2724 soc_pbmp_t pbmp_xport_ge; 2725 const int *p2l_mapping, *p2l_flex_mapping = NULL, *p2m_mapping, *speed_max; 2726 int flex_p2l_mapping[SOC_MAX_PHY_PORTS] = {-1}, 2727 flex_speed_max[SOC_MAX_PHY_PORTS] = {0}; 2728 2729 sal_memset(&_tr3_flex_port_inf[unit], 0, sizeof(_soc_tr3_flex_port_inf_t)); 2730 _soc_hx4_resolve_port_config(unit, dev_id); 2731 LOG_VERBOSE(BSL_LS_SOC_COMMON, 2732 (BSL_META_U(unit, 2733 "Port config id: %d\n"), _tr3_port_config_id[unit])); 2734 2735 switch (_tr3_port_config_id[unit]) { 2736 case 0: 2737 p2l_mapping = p2l_mapping_0; 2738 p2m_mapping = p2m_mapping_0; 2739 speed_max = port_speed_max_0; 2740 break; 2741 case 1: 2742 p2l_mapping = p2l_mapping_1; 2743 p2m_mapping = p2m_mapping_1; 2744 speed_max = port_speed_max_1; 2745 break; 2746 case 2: 2747 p2l_mapping = p2l_mapping_2; 2748 p2m_mapping = p2m_mapping_2; 2749 speed_max = port_speed_max_2; 2750 break; 2751 case 3: 2752 p2l_mapping = p2l_mapping_3; 2753 p2m_mapping = p2m_mapping_3; 2754 speed_max = port_speed_max_3; 2755 break; 2756 case 4: 2757 p2l_mapping = p2l_mapping_4; 2758 p2m_mapping = p2m_mapping_4; 2759 speed_max = port_speed_max_4; 2760 break; 2761 case 5: 2762 p2l_mapping = p2l_mapping_5; 2763 p2m_mapping = p2m_mapping_5; 2764 speed_max = port_speed_max_5; 2765 break; 2766 case 6: 2767 p2l_mapping = p2l_mapping_6; 2768 p2m_mapping = p2m_mapping_6; 2769 speed_max = port_speed_max_6; 2770 break; 2771 case 7: 2772 p2l_mapping = p2l_mapping_7; 2773 p2m_mapping = p2m_mapping_7; 2774 speed_max = port_speed_max_7; 2775 break; 2776 case 8: 2777 p2l_mapping = p2l_mapping_8; 2778 p2m_mapping = p2m_mapping_8; 2779 speed_max = port_speed_max_8; 2780 break; 2781 case 9: 2782 p2l_mapping = p2l_mapping_9; 2783 p2m_mapping = p2m_mapping_9; 2784 speed_max = port_speed_max_9; 2785 break; 2786 case 10: 2787 p2l_mapping = p2l_mapping_10; 2788 p2m_mapping = p2m_mapping_10; 2789 speed_max = port_speed_max_10; 2790 break; 2791 case 11: 2792 p2l_mapping = p2l_mapping_11; 2793 p2m_mapping = p2m_mapping_11; 2794 speed_max = port_speed_max_11; 2795 break; 2796 case 30: 2797 p2l_mapping = p2l_mapping_30; 2798 p2m_mapping = p2m_mapping_30; 2799 speed_max = port_speed_max_30; 2800 break; 2801 case 491: 2802 p2l_mapping = p2l_mapping_491; 2803 p2m_mapping = p2m_mapping_491; 2804 speed_max = port_speed_max_491; 2805 p2l_flex_mapping = flex_p2l_mapping_491; 2806 _tr3_flex_port_inf[unit] = flex_port_inf_491; 2807 break; 2808 case 492: 2809 p2l_mapping = p2l_mapping_492; 2810 p2m_mapping = p2m_mapping_492; 2811 speed_max = port_speed_max_492; 2812 p2l_flex_mapping = flex_p2l_mapping_492; 2813 _tr3_flex_port_inf[unit] = flex_port_inf_492; 2814 break; 2815 case 490: 2816 p2l_mapping = p2l_mapping_490; 2817 p2m_mapping = p2m_mapping_490; 2818 speed_max = port_speed_max_490; 2819 p2l_flex_mapping = flex_p2l_mapping_490; 2820 _tr3_flex_port_inf[unit] = flex_port_inf_490; 2821 break; 2822 case 495: 2823 p2l_mapping = p2l_mapping_495; 2824 p2m_mapping = p2m_mapping_495; 2825 speed_max = port_speed_max_495; 2826 p2l_flex_mapping = flex_p2l_mapping_495; 2827 _tr3_flex_port_inf[unit] = flex_port_inf_495; 2828 break; 2829 case 500: 2830 p2l_mapping = p2l_mapping_500; 2831 p2m_mapping = p2m_mapping_500; 2832 speed_max = port_speed_max_500; 2833 p2l_flex_mapping = flex_p2l_mapping_500; 2834 _tr3_flex_port_inf[unit] = flex_port_inf_500; 2835 break; 2836 case 497: 2837 p2l_mapping = p2l_mapping_497; 2838 p2m_mapping = p2m_mapping_497; 2839 speed_max = port_speed_max_497; 2840 p2l_flex_mapping = flex_p2l_mapping_497; 2841 _tr3_flex_port_inf[unit] = flex_port_inf_497; 2842 break; 2843 case 510: 2844 case 610: 2845 p2l_mapping = p2l_mapping_510; 2846 p2m_mapping = p2m_mapping_510; 2847 speed_max = port_speed_max_510; 2848 p2l_flex_mapping = flex_p2l_mapping_510; 2849 _tr3_flex_port_inf[unit] = flex_port_inf_510; 2850 break; 2851 case 464: 2852 p2l_mapping = p2l_mapping_464; 2853 p2m_mapping = p2m_mapping_464; 2854 speed_max = port_speed_max_460; 2855 p2l_flex_mapping = flex_p2l_mapping_464; 2856 _tr3_flex_port_inf[unit] = flex_port_inf_464; 2857 break; 2858 case 462: 2859 p2l_mapping = p2l_mapping_460; 2860 p2m_mapping = p2m_mapping_460; 2861 speed_max = port_speed_max_462; 2862 p2l_flex_mapping = flex_p2l_mapping_460; 2863 _tr3_flex_port_inf[unit] = flex_port_inf_460; 2864 break; 2865 case 463: 2866 p2l_mapping = p2l_mapping_463; 2867 p2m_mapping = p2m_mapping_463; 2868 speed_max = port_speed_max_463; 2869 p2l_flex_mapping = flex_p2l_mapping_463; 2870 _tr3_flex_port_inf[unit] = flex_port_inf_463; 2871 break; 2872 case 460: 2873 p2l_mapping = p2l_mapping_460; 2874 p2m_mapping = p2m_mapping_460; 2875 speed_max = port_speed_max_460; 2876 p2l_flex_mapping = flex_p2l_mapping_460; 2877 _tr3_flex_port_inf[unit] = flex_port_inf_460; 2878 break; 2879 case 414: 2880 p2l_mapping = p2l_mapping_414; 2881 p2m_mapping = p2m_mapping_414; 2882 speed_max = port_speed_max_414; 2883 p2l_flex_mapping = flex_p2l_mapping_414; 2884 _tr3_flex_port_inf[unit] = flex_port_inf_414; 2885 break; 2886 case 413: 2887 p2l_mapping = p2l_mapping_413; 2888 p2m_mapping = p2m_mapping_413; 2889 speed_max = port_speed_max_413; 2890 p2l_flex_mapping = flex_p2l_mapping_413; 2891 _tr3_flex_port_inf[unit] = flex_port_inf_413; 2892 break; 2893 case 412: 2894 p2l_mapping = p2l_mapping_410; 2895 p2m_mapping = p2m_mapping_410; 2896 speed_max = port_speed_max_412; 2897 p2l_flex_mapping = flex_p2l_mapping_410; 2898 _tr3_flex_port_inf[unit] = flex_port_inf_412; 2899 break; 2900 case 410: 2901 p2l_mapping = p2l_mapping_410; 2902 p2m_mapping = p2m_mapping_410; 2903 speed_max = port_speed_max_410; 2904 p2l_flex_mapping = flex_p2l_mapping_410; 2905 _tr3_flex_port_inf[unit] = flex_port_inf_410; 2906 break; 2907 case 400: 2908 p2l_mapping = p2l_mapping_400; 2909 p2m_mapping = p2m_mapping_400; 2910 speed_max = port_speed_max_400; 2911 p2l_flex_mapping = flex_p2l_mapping_400; 2912 _tr3_flex_port_inf[unit] = flex_port_inf_400; 2913 break; 2914 case 420: 2915 p2l_mapping = p2l_mapping_420; 2916 p2m_mapping = p2m_mapping_420; 2917 speed_max = port_speed_max_420; 2918 p2l_flex_mapping = flex_p2l_mapping_420; 2919 _tr3_flex_port_inf[unit] = flex_port_inf_420; 2920 break; 2921 case 514: 2922 p2l_mapping = p2l_mapping_514; 2923 p2m_mapping = p2m_mapping_514; 2924 speed_max = port_speed_max_514; 2925 p2l_flex_mapping = flex_p2l_mapping_514; 2926 _tr3_flex_port_inf[unit] = flex_port_inf_514; 2927 break; 2928 case 450: 2929 p2l_mapping = p2l_mapping_450; 2930 p2m_mapping = p2m_mapping_450; 2931 speed_max = port_speed_max_450; 2932 p2l_flex_mapping = flex_p2l_mapping_450; 2933 _tr3_flex_port_inf[unit] = flex_port_inf_450; 2934 break; 2935 default: 2936 return SOC_E_PARAM; 2937 } 2938 2939 /* Handle any init time flex port configs */ 2940 if (_tr3_flex_port_inf[unit].valid) { 2941 uint8 idx, i, j, port_groups = 0; 2942 char *config_str, *sub_str, *sub_str_end; 2943 int num_lanes, port_bw; 2944 2945 if (p2l_flex_mapping) { 2946 sal_memcpy(flex_p2l_mapping, p2l_flex_mapping, 2947 sizeof(int) * SOC_MAX_PHY_PORTS); 2948 } 2949 sal_memcpy(flex_speed_max, speed_max, sizeof(int) * SOC_MAX_PHY_PORTS); 2950 for (i = 0; ; i++) { 2951 if (_tr3_flex_port_inf[unit].flex_port_groups[i] == -1) { 2952 break; 2953 } 2954 } 2955 port_groups = i; 2956 LOG_VERBOSE(BSL_LS_SOC_COMMON, 2957 (BSL_META_U(unit, 2958 "Flex port groups: %d\n"), port_groups)); 2959 _tr3_flex_port_data[unit].port_groups = port_groups; 2960 for (i = 0; i < port_groups; i++) { 2961 config_str = soc_property_port_get_str(unit, i, spn_PORTGROUP); 2962 if (config_str == NULL) { 2963 continue; 2964 } 2965 LOG_VERBOSE(BSL_LS_SOC_COMMON, 2966 (BSL_META_U(unit, 2967 "Flex group cfg: %d=%s\n"), i, config_str)); 2968 /* 2969 * portgroup_<port group>=<num of lanes> 2970 */ 2971 sub_str = config_str; 2972 num_lanes = sal_ctoi(sub_str, &sub_str_end); 2973 if (sub_str == sub_str_end) { 2974 LOG_ERROR(BSL_LS_SOC_COMMON, 2975 (BSL_META_U(unit, 2976 "Port group %d: Missing number of lanes information \"%s\"\n"), 2977 i, config_str)); 2978 rv = SOC_E_FAIL; 2979 continue; 2980 } 2981 if (num_lanes == 0) { 2982 LOG_ERROR(BSL_LS_SOC_COMMON, 2983 (BSL_META_U(unit, 2984 "Port group %d: Missing number of lanes information \"%s\"\n"), 2985 i, config_str)); 2986 rv = SOC_E_FAIL; 2987 continue; 2988 } 2989 SOC_PBMP_CLEAR(pbmp_xport_xe); 2990 SOC_PBMP_CLEAR(pbmp_xport_ge); 2991 idx = _tr3_flex_port_inf[unit].flex_port_groups[i]*4 + 1; 2992 switch (num_lanes) { 2993 case 1: 2994 _tr3_flex_port_data[unit].ports[i] = 4; 2995 /* Determine bandwidth */ 2996 port_bw = _tr3_flex_port_inf[unit].def_flex_port_speeds[i][2]; 2997 /* Check for properties */ 2998 pbmp_xport_ge = soc_property_get_pbmp_default(unit, spn_PBMP_XPORT_GE, 2999 pbmp_xport_ge); 3000 /* Force 10 -> 1 */ 3001 if (SOC_PBMP_MEMBER(pbmp_xport_ge, p2l_mapping[idx])) { 3002 if (port_bw == 10) { 3003 for (j = 0; _tr3_flex_port_inf[unit].flex_port_speeds[i][j] != -1;j++) { 3004 if (_tr3_flex_port_inf[unit].flex_port_speeds[i][j] == 1 && 3005 _tr3_flex_port_inf[unit].flex_port_lanes[i][j] == num_lanes) { 3006 port_bw = 1; 3007 break; 3008 } 3009 } 3010 } 3011 } 3012 LOG_VERBOSE(BSL_LS_SOC_COMMON, 3013 (BSL_META_U(unit, 3014 "Flex group: %d, lanes: %d, ports: %d, speed: %d gbps\n"), i, 3015 num_lanes, _tr3_flex_port_data[unit].ports[i], port_bw)); 3016 if (SOC_IS_HELIX4(unit) && ((_tr3_port_config_id[unit] == 410) || 3017 (_tr3_port_config_id[unit] == 463) ||(_tr3_port_config_id[unit] == 413))) { 3018 flex_p2l_mapping[idx+1] = p2l_mapping[idx+1]; 3019 flex_p2l_mapping[idx+2] = p2l_mapping[idx+2]; 3020 flex_p2l_mapping[idx+3] = p2l_mapping[idx+3]; 3021 flex_speed_max[idx+1] = (flex_p2l_mapping[idx+1]>0) ? port_bw : -1; 3022 flex_speed_max[idx+2] = (flex_p2l_mapping[idx+2]>0) ? port_bw : -1; 3023 flex_speed_max[idx+3] = (flex_p2l_mapping[idx+3]>0) ? port_bw : -1; 3024 } else{ 3025 flex_p2l_mapping[idx+1] = flex_p2l_mapping[idx]+1; 3026 flex_p2l_mapping[idx+2] = flex_p2l_mapping[idx]+2; 3027 flex_p2l_mapping[idx+3] = flex_p2l_mapping[idx]+3; 3028 flex_speed_max[idx+1] = port_bw; 3029 flex_speed_max[idx+2] = port_bw; 3030 flex_speed_max[idx+3] = port_bw; 3031 } 3032 flex_speed_max[idx] = port_bw; 3033 break; 3034 case 2: 3035 #ifdef BCM_HELIX4_SUPPORT 3036 if (SOC_IS_HELIX4(unit) && (((_tr3_port_config_id[unit] == 464) 3037 ||(_tr3_port_config_id[unit] == 410)) && (idx == 57 || idx == 61))) { 3038 return SOC_E_PARAM; 3039 } 3040 #endif 3041 _tr3_flex_port_data[unit].ports[i] = 2; 3042 /* Determine bandwidth */ 3043 port_bw = _tr3_flex_port_inf[unit].def_flex_port_speeds[i][1]; 3044 /* Check for properties */ 3045 pbmp_xport_xe = soc_property_get_pbmp_default(unit, spn_PBMP_XPORT_XE, 3046 pbmp_xport_xe); 3047 /* Force 21 -> 10 */ 3048 if (SOC_PBMP_MEMBER(pbmp_xport_xe, flex_p2l_mapping[idx])) { 3049 if (port_bw == 21) { 3050 for (j = 0; _tr3_flex_port_inf[unit].flex_port_speeds[i][j] != -1;j++) { 3051 if (_tr3_flex_port_inf[unit].flex_port_speeds[i][j] == 10 && 3052 _tr3_flex_port_inf[unit].flex_port_lanes[i][j] == num_lanes) { 3053 port_bw = 10; 3054 break; 3055 } 3056 } 3057 } 3058 } 3059 3060 LOG_VERBOSE(BSL_LS_SOC_COMMON, 3061 (BSL_META_U(unit, 3062 "Flex group: %d, lanes: %d, ports: %d, speed: %d gbps\n"), i, 3063 num_lanes, _tr3_flex_port_data[unit].ports[i], port_bw)); 3064 if (SOC_IS_HELIX4(unit) && ((_tr3_port_config_id[unit]== 463) || 3065 (_tr3_port_config_id[unit]== 413))){ 3066 flex_p2l_mapping[idx+1] = -1; 3067 flex_p2l_mapping[idx+2] = p2l_mapping[idx+2]; 3068 flex_p2l_mapping[idx+3] = -1; 3069 flex_speed_max[idx+1] = (flex_p2l_mapping[idx+1]>0) ? port_bw : -1; 3070 flex_speed_max[idx+2] = (flex_p2l_mapping[idx+2]>0) ? port_bw : -1; 3071 flex_speed_max[idx+3] = (flex_p2l_mapping[idx+3]>0) ? port_bw : -1; 3072 } else{ 3073 flex_p2l_mapping[idx+1] = -1; 3074 flex_p2l_mapping[idx+2] = flex_p2l_mapping[idx]+2; 3075 flex_p2l_mapping[idx+3] = -1; 3076 flex_speed_max[idx] = port_bw; 3077 flex_speed_max[idx+1] = -1; 3078 flex_speed_max[idx+2] = port_bw; 3079 flex_speed_max[idx+3] = -1; 3080 } 3081 break; 3082 case 4: 3083 if ((BCM56548H_DEVICE_ID == dev_id) &&(idx == 57 || idx == 61)) { 3084 return SOC_E_PARAM; 3085 } 3086 if ( SOC_IS_HELIX4(unit) && ((_tr3_port_config_id[unit]== 463) || 3087 (_tr3_port_config_id[unit]== 413)) && ((idx == 57) || (idx == 61))) { 3088 return SOC_E_PARAM; 3089 } 3090 if ( SOC_IS_HELIX4(unit) && (_tr3_port_config_id[unit]== 414)) { 3091 return SOC_E_PARAM; 3092 } 3093 _tr3_flex_port_data[unit].ports[i] = 1; 3094 /* Determine bandwidth */ 3095 port_bw = _tr3_flex_port_inf[unit].def_flex_port_speeds[i][0]; 3096 /* Check for properties */ 3097 pbmp_xport_xe = soc_property_get_pbmp_default(unit, spn_PBMP_XPORT_XE, 3098 pbmp_xport_xe); 3099 /* Force 21 -> 10 */ 3100 if (SOC_PBMP_MEMBER(pbmp_xport_xe, flex_p2l_mapping[idx])) { 3101 if (port_bw == 21) { 3102 for (j = 0; _tr3_flex_port_inf[unit].flex_port_speeds[i][j] != -1;j++) { 3103 if (_tr3_flex_port_inf[unit].flex_port_speeds[i][j] == 10 && 3104 _tr3_flex_port_inf[unit].flex_port_lanes[i][j] == num_lanes) { 3105 port_bw = 10; 3106 break; 3107 } 3108 } 3109 } 3110 } 3111 LOG_VERBOSE(BSL_LS_SOC_COMMON, 3112 (BSL_META_U(unit, 3113 "Flex group: %d, lanes: %d, ports: %d, speed: %d gbps\n"), i, 3114 num_lanes, _tr3_flex_port_data[unit].ports[i], port_bw)); 3115 flex_p2l_mapping[idx+1] = -1; 3116 flex_p2l_mapping[idx+2] = -1; 3117 flex_p2l_mapping[idx+3] = -1; 3118 flex_speed_max[idx] = port_bw; 3119 flex_speed_max[idx+1] = -1; 3120 flex_speed_max[idx+2] = -1; 3121 flex_speed_max[idx+3] = -1; 3122 break; 3123 default: break; 3124 } 3125 } 3126 } 3127 3128 si = &SOC_INFO(unit); 3129 si->bandwidth = 260000; 3130 for (phy_port = 0; phy_port < SOC_MAX_PHY_PORTS; phy_port++) { 3131 si->port_p2l_mapping[phy_port] = p2l_mapping[phy_port]; 3132 si->flex_port_p2l_mapping[phy_port] = _tr3_flex_port_inf[unit].valid ? flex_p2l_mapping[phy_port] : 3133 p2l_mapping[phy_port]; /* for disabling unavailable ports */ 3134 si->port_p2m_mapping[phy_port] = p2m_mapping[phy_port]; 3135 _soc_tr3_port_speed_max[phy_port] = 0; 3136 if (_tr3_flex_port_inf[unit].valid) { 3137 if (flex_speed_max[phy_port] != -1) { 3138 si->port_speed_max[si->port_p2l_mapping[phy_port]] = 3139 flex_speed_max[phy_port] * 1000; 3140 _soc_tr3_port_speed_max[phy_port] = flex_speed_max[phy_port] * 1000; 3141 } 3142 } else { 3143 if (speed_max[phy_port] != -1) { 3144 si->port_speed_max[si->port_p2l_mapping[phy_port]] = 3145 speed_max[phy_port] * 1000; 3146 _soc_tr3_port_speed_max[phy_port] = speed_max[phy_port] * 1000; 3147 } 3148 } 3149 } 3150 return rv; 3151 } 3152 3153 #ifdef BCM_ISM_SUPPORT 3154 /* Default mem config size */ 3155 static soc_ism_mem_size_config_t ism_alloc_size[] = { 3156 { SOC_ISM_MEM_VLAN_XLATE, _ISM_MEM_VLAN_XLATE_SIZE , 0 , 0}, 3157 { SOC_ISM_MEM_L2_ENTRY, _ISM_MEM_L2_SIZE , 0 , 0}, 3158 { SOC_ISM_MEM_L3_ENTRY, _ISM_MEM_L3_SIZE , 0 , 0}, 3159 { SOC_ISM_MEM_EP_VLAN_XLATE, _ISM_MEM_EP_VLAN_XLATE_SIZE , 0 , 0}, 3160 { SOC_ISM_MEM_MPLS, _ISM_MEM_MPLS_SIZE , 0 , 0}, 3161 { SOC_ISM_MEM_ESM_L2, 0 , 0 , 0}, 3162 { SOC_ISM_MEM_ESM_L3, 0 , 0 , 0}, 3163 { SOC_ISM_MEM_ESM_ACL, 0 , 0 , 0} 3164 }; 3165 #endif 3166 3167 3168 int 3169 _soc_hx4_l3_defip_sizing_config(int unit) 3170 { 3171 int num_ipv6_128b_entries = 0; 3172 int config_v6_entries = 0; 3173 int defip_config = 0; 3174 int num_defip_entries = 0; 3175 uint32 lpm_scaling_enable = 0; 3176 soc_persist_t *sop = SOC_PERSIST(unit); 3177 3178 if (soc_property_get(unit, "l3_defip_sizing", TRUE) == FALSE) { 3179 return SOC_E_NONE; 3180 } 3181 3182 defip_config = soc_property_get(unit, spn_IPV6_LPM_128B_ENABLE, 1); 3183 3184 /* Pair half the tcams by default when ipv6_128b is enabled */ 3185 num_ipv6_128b_entries = 3186 ((SOC_CONTROL(unit)->l3_defip_max_tcams/2) * SOC_CONTROL(unit)->l3_defip_tcam_size) / 2; 3187 3188 num_ipv6_128b_entries = soc_property_get(unit, 3189 spn_NUM_IPV6_LPM_128B_ENTRIES, 3190 (defip_config ? num_ipv6_128b_entries : 0)); 3191 num_ipv6_128b_entries = num_ipv6_128b_entries + (num_ipv6_128b_entries % 2); 3192 3193 lpm_scaling_enable = soc_property_get(unit, spn_LPM_SCALING_ENABLE, 0); 3194 if (SOC_CONTROL(unit)->tcam_protect_write) { 3195 /* not support in non-scaling LPM mode */ 3196 if (lpm_scaling_enable == 0) { 3197 LOG_CLI((BSL_META_U(unit, 3198 "LPM non-scaling mode does not support " 3199 "tcam_protect_write. Please retry with " 3200 "lpm_scaling_enable=1.\n"))); 3201 return SOC_E_CONFIG; 3202 } 3203 num_ipv6_128b_entries = (num_ipv6_128b_entries + 3) / 4 * 4; 3204 } 3205 3206 config_v6_entries = num_ipv6_128b_entries; 3207 3208 3209 if (lpm_scaling_enable) { 3210 num_ipv6_128b_entries = 0; 3211 } 3212 num_defip_entries = (SOC_CONTROL(unit)->l3_defip_max_tcams * 3213 SOC_CONTROL(unit)->l3_defip_tcam_size) - 3214 (num_ipv6_128b_entries * 2); 3215 3216 /* Adjust numbers for tcam_protect_write */ 3217 /* Reserve one entry from each TCAM to maintain duplicate entry during modify */ 3218 if (SOC_CONTROL(unit)->tcam_protect_write) { 3219 if (num_defip_entries) { 3220 num_defip_entries -= SOC_CONTROL(unit)->l3_defip_max_tcams; 3221 /* Don't use up all entries as protect entries */ 3222 if (num_defip_entries <= 0) { 3223 return SOC_E_CONFIG; 3224 } 3225 SOC_CONTROL(unit)->l3_defip_tcam_size --; 3226 } 3227 if (num_ipv6_128b_entries) { 3228 num_ipv6_128b_entries -= SOC_CONTROL(unit)->l3_defip_max_tcams/2; 3229 /* Don't use up all entries as protect entries */ 3230 if (num_ipv6_128b_entries <= 0) { 3231 return SOC_E_CONFIG; 3232 } 3233 SOC_CONTROL(unit)->l3_defip_tcam_size --; 3234 } 3235 if (config_v6_entries) { 3236 config_v6_entries -= SOC_CONTROL(unit)->l3_defip_max_tcams/2; 3237 if (config_v6_entries < 0) { 3238 return SOC_E_CONFIG; 3239 } 3240 } 3241 } 3242 3243 if (lpm_scaling_enable) { 3244 if (!soc_property_get(unit, spn_LPM_IPV6_128B_RESERVED, 1)) { 3245 config_v6_entries = ((config_v6_entries / 3246 SOC_CONTROL(unit)->l3_defip_tcam_size) + 3247 ((config_v6_entries % 3248 SOC_CONTROL(unit)->l3_defip_tcam_size) 3249 ? 1 : 0)) * SOC_CONTROL(unit)->l3_defip_tcam_size; 3250 } 3251 } 3252 3253 sop->memState[L3_DEFIP_PAIR_128m].index_max = 3254 num_ipv6_128b_entries - 1; 3255 sop->memState[L3_DEFIP_PAIR_128_ONLYm].index_max = 3256 num_ipv6_128b_entries - 1; 3257 sop->memState[L3_DEFIP_PAIR_128_DATA_ONLYm].index_max = 3258 num_ipv6_128b_entries - 1; 3259 sop->memState[L3_DEFIP_PAIR_128_HIT_ONLYm].index_max = 3260 num_ipv6_128b_entries - 1; 3261 sop->memState[L3_DEFIPm].index_max = num_defip_entries - 1; 3262 sop->memState[L3_DEFIP_ONLYm].index_max = 3263 sop->memState[L3_DEFIPm].index_max; 3264 sop->memState[L3_DEFIP_DATA_ONLYm].index_max = 3265 sop->memState[L3_DEFIPm].index_max; 3266 sop->memState[L3_DEFIP_HIT_ONLYm].index_max = 3267 sop->memState[L3_DEFIPm].index_max; 3268 SOC_CONTROL(unit)->l3_defip_index_remap = num_ipv6_128b_entries; 3269 soc_l3_defip_indexes_init(unit, config_v6_entries); 3270 3271 return SOC_E_NONE; 3272 } 3273 3274 /* soc_hx4_mem_config: 3275 * Over-ride the default table sizes (from regsfile) for any SKUs here 3276 */ 3277 int 3278 soc_hx4_mem_config(int unit, int dev_id) 3279 { 3280 int rv = SOC_E_NONE; 3281 uint16 scale = 5; 3282 soc_persist_t *sop = SOC_PERSIST(unit); 3283 uint8 bcm56049_mode = FALSE; 3284 3285 sop->memState[ING_UNTAGGED_PHBm].index_max = 62; 3286 3287 /* MMU buffer size config */ 3288 switch (dev_id) { 3289 case BCM56040_DEVICE_ID: 3290 case BCM56041_DEVICE_ID: 3291 case BCM56042_DEVICE_ID: 3292 _soc_tr3_mmu_buffer_cells[unit] = _HX4_MMU_TOTAL_CELLS_10K; 3293 break; 3294 case BCM56548H_DEVICE_ID: 3295 case BCM56548_DEVICE_ID: 3296 case BCM56547_DEVICE_ID: 3297 case BCM56346_DEVICE_ID: 3298 case BCM56345_DEVICE_ID: 3299 case BCM56344_DEVICE_ID: 3300 case BCM56342_DEVICE_ID: 3301 case BCM56340_DEVICE_ID: 3302 case BCM56049_DEVICE_ID: 3303 case BCM56048_DEVICE_ID: 3304 case BCM56047_DEVICE_ID: 3305 _soc_tr3_mmu_buffer_cells[unit] = _TR3_MMU_TOTAL_CELLS_19K; 3306 break; 3307 default: 3308 _soc_tr3_mmu_buffer_cells[unit] = _TR3_MMU_TOTAL_CELLS_19K; 3309 break; 3310 } 3311 3312 switch (dev_id) { 3313 case BCM56548H_DEVICE_ID: 3314 case BCM56548_DEVICE_ID: 3315 case BCM56547_DEVICE_ID: 3316 /* for Firescont, only 8 tcams are used */ 3317 SOC_CONTROL(unit)->l3_defip_max_tcams = _SOC_HX4_DEFIP_MAX_TCAMS/2; 3318 SOC_CONTROL(unit)->l3_defip_tcam_size = _SOC_HX4_DEFIP_TCAM_DEPTH; 3319 /* L3_DEFIP sizing */ 3320 if (soc_property_get(unit, "l3_defip_sizing", TRUE)) { 3321 rv = _soc_hx4_l3_defip_sizing_config(unit); 3322 if (SOC_FAILURE(rv)) { 3323 return rv; 3324 } 3325 } 3326 break; 3327 case BCM56344_DEVICE_ID: 3328 case BCM56342_DEVICE_ID: 3329 case BCM56340_DEVICE_ID: 3330 /* for HX4, only 8 tcams are used */ 3331 SOC_CONTROL(unit)->l3_defip_max_tcams = _SOC_HX4_DEFIP_MAX_TCAMS/4; 3332 SOC_CONTROL(unit)->l3_defip_tcam_size = _SOC_HX4_DEFIP_TCAM_DEPTH; 3333 /* L3_DEFIP sizing */ 3334 if (soc_property_get(unit, "l3_defip_sizing", TRUE)) { 3335 rv = _soc_hx4_l3_defip_sizing_config(unit); 3336 if (SOC_FAILURE(rv)) { 3337 return rv; 3338 } 3339 } 3340 break; 3341 case BCM56346_DEVICE_ID: 3342 case BCM56345_DEVICE_ID: 3343 SOC_CONTROL(unit)->l3_defip_max_tcams = _SOC_HX4_DEFIP_MAX_TCAMS/8; 3344 SOC_CONTROL(unit)->l3_defip_tcam_size = _SOC_HX4_DEFIP_TCAM_DEPTH; 3345 3346 /* L3 Next hop */ 3347 sop->memState[INITIAL_ING_L3_NEXT_HOPm].index_max = 8191; 3348 sop->memState[ING_L3_NEXT_HOPm].index_max = 8191; 3349 sop->memState[EGR_L3_NEXT_HOPm].index_max = 8191; 3350 sop->memState[INITIAL_PROT_NHI_TABLEm].index_max = 8191; 3351 /* L3 LPM */ 3352 sop->memState[L3_DEFIPm].index_max = 8191; 3353 sop->memState[L3_DEFIP_ONLYm].index_max = 8191; 3354 sop->memState[L3_DEFIP_DATA_ONLYm].index_max = 8191; 3355 sop->memState[L3_DEFIP_HIT_ONLYm].index_max = 8191; 3356 /* L3 IPMC */ 3357 sop->memState[L3_IPMCm].index_max = 2047; 3358 sop->memState[L3_IPMC_1m].index_max = 2047; 3359 sop->memState[L3_IPMC_REMAPm].index_max = 2047; 3360 sop->memState[MMU_REPL_GROUPm].index_max = 2047; 3361 /* sop->memState[ING_UNTAGGED_PHBm].index_max = ?? */ 3362 sop->memState[EGR_IPMCm].index_max = 2047; 3363 sop->memState[EGR_L3_INTFm].index_max = 8191; 3364 /* Counters */ 3365 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_0m].index_max = -1; 3366 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_1m].index_max = -1; 3367 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_2m].index_max = -1; 3368 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_3m].index_max = -1; 3369 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_4m].index_max = -1; 3370 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_5m].index_max = -1; 3371 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_6m].index_max = -1; 3372 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_7m].index_max = -1; 3373 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_8m].index_max = -1; 3374 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_9m].index_max = -1; 3375 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_10m].index_max = -1; 3376 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_11m].index_max = -1; 3377 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_12m].index_max = -1; 3378 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_13m].index_max = -1; 3379 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_14m].index_max = -1; 3380 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_15m].index_max = -1; 3381 sop->memState[ING_FLEX_CTR_OFFSET_TABLE_8m].index_max = -1; 3382 sop->memState[ING_FLEX_CTR_OFFSET_TABLE_9m].index_max = -1; 3383 sop->memState[ING_FLEX_CTR_OFFSET_TABLE_10m].index_max = -1; 3384 sop->memState[ING_FLEX_CTR_OFFSET_TABLE_11m].index_max = -1; 3385 sop->memState[ING_FLEX_CTR_OFFSET_TABLE_12m].index_max = -1; 3386 sop->memState[ING_FLEX_CTR_OFFSET_TABLE_13m].index_max = -1; 3387 sop->memState[ING_FLEX_CTR_OFFSET_TABLE_14m].index_max = -1; 3388 sop->memState[ING_FLEX_CTR_OFFSET_TABLE_15m].index_max = -1; 3389 sop->memState[OAM_LM_COUNTERSm].index_max = -1; 3390 sop->memState[EGR_FLEX_CTR_COUNTER_TABLE_0m].index_max = -1; 3391 sop->memState[EGR_FLEX_CTR_COUNTER_TABLE_1m].index_max = -1; 3392 sop->memState[EGR_FLEX_CTR_COUNTER_TABLE_2m].index_max = -1; 3393 sop->memState[EGR_FLEX_CTR_COUNTER_TABLE_3m].index_max = -1; 3394 sop->memState[EGR_FLEX_CTR_COUNTER_TABLE_4m].index_max = -1; 3395 sop->memState[EGR_FLEX_CTR_COUNTER_TABLE_5m].index_max = -1; 3396 sop->memState[EGR_FLEX_CTR_COUNTER_TABLE_6m].index_max = -1; 3397 sop->memState[EGR_FLEX_CTR_COUNTER_TABLE_7m].index_max = -1; 3398 /* LMEP */ 3399 sop->memState[LMEPm].index_max = -1; 3400 sop->memState[LMEP_DAm].index_max = -1; 3401 /* RMEP */ 3402 sop->memState[RMEPm].index_max = -1; 3403 sop->memState[MAID_REDUCTIONm].index_max = -1; 3404 sop->memState[MA_STATEm].index_max = -1; 3405 3406 /* L3_DEFIP sizing */ 3407 if (soc_property_get(unit, "l3_defip_sizing", TRUE)) { 3408 rv = _soc_hx4_l3_defip_sizing_config(unit); 3409 if (SOC_FAILURE(rv)) { 3410 return rv; 3411 } 3412 } 3413 /* These memories are not present in Twister */ 3414 sop->memState[FT_SESSIONm].index_max = -1; 3415 sop->memState[FT_EXPORT_FIFOm].index_max = -1; 3416 sop->memState[FT_EXPORT_DATA_ONLYm].index_max = -1; 3417 sop->memState[FT_EOP_TBLm].index_max = -1; 3418 sop->memState[FT_AGE_PROFILEm].index_max = -1; 3419 sop->memState[FT_L4PORTm].index_max = -1; 3420 sop->memState[FT_DST_LAG_CONFIGm].index_max = -1; 3421 sop->memState[FT_DST_PORT_CONFIGm].index_max = -1; 3422 sop->memState[FT_POLICYm].index_max = -1; 3423 sop->memState[FT_SESSION_IPV6m].index_max = -1; 3424 sop->memState[FT_EXPORT_CNTR_ONLYm].index_max = -1; 3425 sop->memState[AXP_SM_CHAR_REMAP0m].index_max = -1; 3426 sop->memState[AXP_SM_CHAR_REMAP1m].index_max = -1; 3427 sop->memState[AXP_SM_CHAR_REMAP2m].index_max = -1; 3428 sop->memState[AXP_SM_CHAR_REMAP3m].index_max = -1; 3429 sop->memState[AXP_SM_CHAR_REMAP4m].index_max = -1; 3430 sop->memState[AXP_SM_CHAR_REMAP5m].index_max = -1; 3431 sop->memState[AXP_SM_CHAR_REMAP6m].index_max = -1; 3432 sop->memState[AXP_SM_CHAR_REMAP7m].index_max = -1; 3433 sop->memState[AXP_SM_CHAR_REMAP8m].index_max = -1; 3434 sop->memState[AXP_SM_CHAR_REMAP9m].index_max = -1; 3435 sop->memState[AXP_SM_CHAR_REMAP10m].index_max = -1; 3436 sop->memState[AXP_SM_CHAR_REMAP11m].index_max = -1; 3437 sop->memState[AXP_SM_CHAR_REMAP12m].index_max = -1; 3438 sop->memState[AXP_SM_CHAR_REMAP13m].index_max = -1; 3439 sop->memState[AXP_SM_CHAR_REMAP14m].index_max = -1; 3440 sop->memState[AXP_SM_CHAR_REMAP15m].index_max = -1; 3441 sop->memState[AXP_SM_CHAR_REMAP16m].index_max = -1; 3442 sop->memState[AXP_SM_CHAR_REMAP17m].index_max = -1; 3443 sop->memState[AXP_SM_CHAR_REMAP18m].index_max = -1; 3444 sop->memState[AXP_SM_CHAR_REMAP19m].index_max = -1; 3445 sop->memState[AXP_SM_CHAR_REMAP20m].index_max = -1; 3446 sop->memState[AXP_SM_CHAR_REMAP21m].index_max = -1; 3447 sop->memState[AXP_SM_CHAR_REMAP22m].index_max = -1; 3448 sop->memState[AXP_SM_CHAR_REMAP23m].index_max = -1; 3449 sop->memState[AXP_SM_CHAR_REMAP24m].index_max = -1; 3450 sop->memState[AXP_SM_CHAR_REMAP25m].index_max = -1; 3451 sop->memState[AXP_SM_CHAR_REMAP26m].index_max = -1; 3452 sop->memState[AXP_SM_CHAR_REMAP27m].index_max = -1; 3453 sop->memState[AXP_SM_CHAR_REMAP28m].index_max = -1; 3454 sop->memState[AXP_SM_CHAR_REMAP29m].index_max = -1; 3455 sop->memState[AXP_SM_CHAR_REMAP30m].index_max = -1; 3456 sop->memState[AXP_SM_CHAR_REMAP31m].index_max = -1; 3457 sop->memState[AXP_SM_FLOW_TABLE_BULK_MATCH_DATAm].index_max = -1; 3458 sop->memState[AXP_SM_FLOW_TABLE_BULK_MATCH_MASKm].index_max = -1; 3459 sop->memState[AXP_SM_FLOW_TABLE_BULK_REPLACE_DATAm].index_max = -1; 3460 sop->memState[AXP_SM_FLOW_TABLE_BULK_REPLACE_MASKm].index_max = -1; 3461 sop->memState[AXP_SM_FLOW_TABLE_MEMm].index_max = -1; 3462 sop->memState[AXP_SM_MATCH_COUNTERS_MEM0m].index_max = -1; 3463 sop->memState[AXP_SM_MATCH_COUNTERS_MEM1m].index_max = -1; 3464 sop->memState[AXP_SM_MATCH_COUNTERS_MEM2m].index_max = -1; 3465 sop->memState[AXP_SM_MATCH_COUNTERS_MEM3m].index_max = -1; 3466 sop->memState[AXP_SM_MATCH_TABLE_BULK_MATCH_DATAm].index_max = -1; 3467 sop->memState[AXP_SM_MATCH_TABLE_BULK_MATCH_MASKm].index_max = -1; 3468 sop->memState[AXP_SM_MATCH_TABLE_BULK_REPLACE_DATAm].index_max = -1; 3469 sop->memState[AXP_SM_MATCH_TABLE_BULK_REPLACE_MASKm].index_max = -1; 3470 sop->memState[AXP_SM_MATCH_TABLE_MEM0m].index_max = -1; 3471 sop->memState[AXP_SM_MATCH_TABLE_MEM1m].index_max = -1; 3472 sop->memState[AXP_SM_MATCH_TABLE_MEM2m].index_max = -1; 3473 sop->memState[AXP_SM_MATCH_TABLE_MEM3m].index_max = -1; 3474 sop->memState[AXP_SM_PACKET_BUFFER_MEMm].index_max = -1; 3475 sop->memState[AXP_SM_STATE_TABLE_BULK_MATCH_DATAm].index_max = -1; 3476 sop->memState[AXP_SM_STATE_TABLE_BULK_MATCH_MASKm].index_max = -1; 3477 sop->memState[AXP_SM_STATE_TABLE_BULK_REPLACE_DATAm].index_max = -1; 3478 sop->memState[AXP_SM_STATE_TABLE_BULK_REPLACE_MASKm].index_max = -1; 3479 sop->memState[AXP_SM_STATE_TABLE_MEM0m].index_max = -1; 3480 sop->memState[AXP_SM_STATE_TABLE_MEM1m].index_max = -1; 3481 sop->memState[AXP_SM_STATE_TABLE_MEM2m].index_max = -1; 3482 sop->memState[AXP_SM_STATE_TABLE_MEM3m].index_max = -1; 3483 sop->memState[AXP_SM_STATE_TABLE_MEM4m].index_max = -1; 3484 sop->memState[AXP_SM_STATE_TABLE_MEM5m].index_max = -1; 3485 sop->memState[AXP_SM_STATE_TABLE_MEM6m].index_max = -1; 3486 sop->memState[AXP_SM_STATE_TABLE_MEM7m].index_max = -1; 3487 sop->memState[SVM_METER_TABLEm].index_max = -1; 3488 sop->memState[VRFm].index_max = 127; 3489 break; 3490 case BCM56042_DEVICE_ID: 3491 case BCM56041_DEVICE_ID: 3492 case BCM56040_DEVICE_ID: 3493 /* L3 Next hop */ 3494 sop->memState[INITIAL_ING_L3_NEXT_HOPm].index_max = 1023; 3495 sop->memState[ING_L3_NEXT_HOPm].index_max = 1023; 3496 sop->memState[EGR_L3_NEXT_HOPm].index_max = 1023; 3497 sop->memState[INITIAL_PROT_NHI_TABLEm].index_max = 1023; 3498 /* L3 LPM */ 3499 sop->memState[L3_DEFIPm].index_max = 127; 3500 sop->memState[L3_DEFIP_ONLYm].index_max = 127; 3501 sop->memState[L3_DEFIP_DATA_ONLYm].index_max = 127; 3502 sop->memState[L3_DEFIP_HIT_ONLYm].index_max = 127; 3503 /* L3 IPMC */ 3504 sop->memState[L3_IPMCm].index_max = 255; 3505 sop->memState[L3_IPMC_1m].index_max = 255; 3506 sop->memState[L3_IPMC_REMAPm].index_max = 255; 3507 sop->memState[MMU_REPL_GROUPm].index_max = 255; 3508 /* sop->memState[ING_UNTAGGED_PHBm].index_max = ?? */ 3509 sop->memState[EGR_IPMCm].index_max = 255; 3510 sop->memState[EGR_L3_INTFm].index_max = 511; 3511 /* Counters */ 3512 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_0m].index_max = 255; 3513 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_1m].index_max = 255; 3514 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_2m].index_max = 255; 3515 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_3m].index_max = 255; 3516 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_4m].index_max = 255; 3517 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_5m].index_max = 255; 3518 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_6m].index_max = 255; 3519 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_7m].index_max = 255; 3520 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_8m].index_max = -1; 3521 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_9m].index_max = -1; 3522 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_10m].index_max = -1; 3523 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_11m].index_max = -1; 3524 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_12m].index_max = -1; 3525 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_13m].index_max = -1; 3526 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_14m].index_max = -1; 3527 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_15m].index_max = -1; 3528 sop->memState[ING_FLEX_CTR_OFFSET_TABLE_8m].index_max = -1; 3529 sop->memState[ING_FLEX_CTR_OFFSET_TABLE_9m].index_max = -1; 3530 sop->memState[ING_FLEX_CTR_OFFSET_TABLE_10m].index_max = -1; 3531 sop->memState[ING_FLEX_CTR_OFFSET_TABLE_11m].index_max = -1; 3532 sop->memState[ING_FLEX_CTR_OFFSET_TABLE_12m].index_max = -1; 3533 sop->memState[ING_FLEX_CTR_OFFSET_TABLE_13m].index_max = -1; 3534 sop->memState[ING_FLEX_CTR_OFFSET_TABLE_14m].index_max = -1; 3535 sop->memState[ING_FLEX_CTR_OFFSET_TABLE_15m].index_max = -1; 3536 sop->memState[VLAN_OR_VFI_MAC_COUNTm].index_max = 8191; 3537 sop->memState[VLAN_OR_VFI_MAC_LIMITm].index_max = 8191; 3538 sop->memState[OAM_LM_COUNTERSm].index_max = 8191; 3539 sop->memState[EGR_FLEX_CTR_COUNTER_TABLE_0m].index_max = 63; 3540 sop->memState[EGR_FLEX_CTR_COUNTER_TABLE_1m].index_max = 63; 3541 sop->memState[EGR_FLEX_CTR_COUNTER_TABLE_2m].index_max = 63; 3542 sop->memState[EGR_FLEX_CTR_COUNTER_TABLE_3m].index_max = 63; 3543 sop->memState[EGR_FLEX_CTR_COUNTER_TABLE_4m].index_max = 63; 3544 sop->memState[EGR_FLEX_CTR_COUNTER_TABLE_5m].index_max = 63; 3545 sop->memState[EGR_FLEX_CTR_COUNTER_TABLE_6m].index_max = 63; 3546 sop->memState[EGR_FLEX_CTR_COUNTER_TABLE_7m].index_max = 63; 3547 /* LMEP */ 3548 sop->memState[LMEPm].index_max = -1; 3549 sop->memState[LMEP_DAm].index_max = -1; 3550 /* RMEP */ 3551 sop->memState[RMEPm].index_max = -1; 3552 sop->memState[MAID_REDUCTIONm].index_max = -1; 3553 sop->memState[MA_STATEm].index_max = -1; 3554 /* L3_DEFIP sizing */ 3555 if (soc_property_get(unit, "l3_defip_sizing", TRUE)) { 3556 if (soc_property_get(unit, spn_IPV6_LPM_128B_ENABLE, 1)) { 3557 sop->memState[L3_DEFIP_PAIR_128m].index_max = 127; 3558 sop->memState[L3_DEFIP_PAIR_128_ONLYm].index_max = 127; 3559 sop->memState[L3_DEFIP_PAIR_128_DATA_ONLYm].index_max = 127; 3560 sop->memState[L3_DEFIP_PAIR_128_HIT_ONLYm].index_max = 127; 3561 sop->memState[L3_DEFIPm].index_max = 127; 3562 sop->memState[L3_DEFIP_ONLYm].index_max = 127; 3563 sop->memState[L3_DEFIP_DATA_ONLYm].index_max = 127; 3564 sop->memState[L3_DEFIP_HIT_ONLYm].index_max = 127; 3565 SOC_CONTROL(unit)->l3_defip_index_remap = 127; 3566 } else { 3567 sop->memState[L3_DEFIP_PAIR_128m].index_max = -1; 3568 sop->memState[L3_DEFIP_PAIR_128_ONLYm].index_max = -1; 3569 sop->memState[L3_DEFIP_PAIR_128_DATA_ONLYm].index_max = -1; 3570 sop->memState[L3_DEFIP_PAIR_128_HIT_ONLYm].index_max = -1; 3571 } 3572 } 3573 /* These memories are not present in Ranger */ 3574 sop->memState[AXP_SM_CHAR_REMAP0m].index_max = -1; 3575 sop->memState[AXP_SM_CHAR_REMAP1m].index_max = -1; 3576 sop->memState[AXP_SM_CHAR_REMAP2m].index_max = -1; 3577 sop->memState[AXP_SM_CHAR_REMAP3m].index_max = -1; 3578 sop->memState[AXP_SM_CHAR_REMAP4m].index_max = -1; 3579 sop->memState[AXP_SM_CHAR_REMAP5m].index_max = -1; 3580 sop->memState[AXP_SM_CHAR_REMAP6m].index_max = -1; 3581 sop->memState[AXP_SM_CHAR_REMAP7m].index_max = -1; 3582 sop->memState[AXP_SM_CHAR_REMAP8m].index_max = -1; 3583 sop->memState[AXP_SM_CHAR_REMAP9m].index_max = -1; 3584 sop->memState[AXP_SM_CHAR_REMAP10m].index_max = -1; 3585 sop->memState[AXP_SM_CHAR_REMAP11m].index_max = -1; 3586 sop->memState[AXP_SM_CHAR_REMAP12m].index_max = -1; 3587 sop->memState[AXP_SM_CHAR_REMAP13m].index_max = -1; 3588 sop->memState[AXP_SM_CHAR_REMAP14m].index_max = -1; 3589 sop->memState[AXP_SM_CHAR_REMAP15m].index_max = -1; 3590 sop->memState[AXP_SM_CHAR_REMAP16m].index_max = -1; 3591 sop->memState[AXP_SM_CHAR_REMAP17m].index_max = -1; 3592 sop->memState[AXP_SM_CHAR_REMAP18m].index_max = -1; 3593 sop->memState[AXP_SM_CHAR_REMAP19m].index_max = -1; 3594 sop->memState[AXP_SM_CHAR_REMAP20m].index_max = -1; 3595 sop->memState[AXP_SM_CHAR_REMAP21m].index_max = -1; 3596 sop->memState[AXP_SM_CHAR_REMAP22m].index_max = -1; 3597 sop->memState[AXP_SM_CHAR_REMAP23m].index_max = -1; 3598 sop->memState[AXP_SM_CHAR_REMAP24m].index_max = -1; 3599 sop->memState[AXP_SM_CHAR_REMAP25m].index_max = -1; 3600 sop->memState[AXP_SM_CHAR_REMAP26m].index_max = -1; 3601 sop->memState[AXP_SM_CHAR_REMAP27m].index_max = -1; 3602 sop->memState[AXP_SM_CHAR_REMAP28m].index_max = -1; 3603 sop->memState[AXP_SM_CHAR_REMAP29m].index_max = -1; 3604 sop->memState[AXP_SM_CHAR_REMAP30m].index_max = -1; 3605 sop->memState[AXP_SM_CHAR_REMAP31m].index_max = -1; 3606 sop->memState[AXP_SM_FLOW_TABLE_BULK_MATCH_DATAm].index_max = -1; 3607 sop->memState[AXP_SM_FLOW_TABLE_BULK_MATCH_MASKm].index_max = -1; 3608 sop->memState[AXP_SM_FLOW_TABLE_BULK_REPLACE_DATAm].index_max = -1; 3609 sop->memState[AXP_SM_FLOW_TABLE_BULK_REPLACE_MASKm].index_max = -1; 3610 sop->memState[AXP_SM_FLOW_TABLE_MEMm].index_max = -1; 3611 sop->memState[AXP_SM_MATCH_COUNTERS_MEM0m].index_max = -1; 3612 sop->memState[AXP_SM_MATCH_COUNTERS_MEM1m].index_max = -1; 3613 sop->memState[AXP_SM_MATCH_COUNTERS_MEM2m].index_max = -1; 3614 sop->memState[AXP_SM_MATCH_COUNTERS_MEM3m].index_max = -1; 3615 sop->memState[AXP_SM_MATCH_TABLE_BULK_MATCH_DATAm].index_max = -1; 3616 sop->memState[AXP_SM_MATCH_TABLE_BULK_MATCH_MASKm].index_max = -1; 3617 sop->memState[AXP_SM_MATCH_TABLE_BULK_REPLACE_DATAm].index_max = -1; 3618 sop->memState[AXP_SM_MATCH_TABLE_BULK_REPLACE_MASKm].index_max = -1; 3619 sop->memState[AXP_SM_MATCH_TABLE_MEM0m].index_max = -1; 3620 sop->memState[AXP_SM_MATCH_TABLE_MEM1m].index_max = -1; 3621 sop->memState[AXP_SM_MATCH_TABLE_MEM2m].index_max = -1; 3622 sop->memState[AXP_SM_MATCH_TABLE_MEM3m].index_max = -1; 3623 sop->memState[AXP_SM_PACKET_BUFFER_MEMm].index_max = -1; 3624 sop->memState[AXP_SM_STATE_TABLE_BULK_MATCH_DATAm].index_max = -1; 3625 sop->memState[AXP_SM_STATE_TABLE_BULK_MATCH_MASKm].index_max = -1; 3626 sop->memState[AXP_SM_STATE_TABLE_BULK_REPLACE_DATAm].index_max = -1; 3627 sop->memState[AXP_SM_STATE_TABLE_BULK_REPLACE_MASKm].index_max = -1; 3628 sop->memState[AXP_SM_STATE_TABLE_MEM0m].index_max = -1; 3629 sop->memState[AXP_SM_STATE_TABLE_MEM1m].index_max = -1; 3630 sop->memState[AXP_SM_STATE_TABLE_MEM2m].index_max = -1; 3631 sop->memState[AXP_SM_STATE_TABLE_MEM3m].index_max = -1; 3632 sop->memState[AXP_SM_STATE_TABLE_MEM4m].index_max = -1; 3633 sop->memState[AXP_SM_STATE_TABLE_MEM5m].index_max = -1; 3634 sop->memState[AXP_SM_STATE_TABLE_MEM6m].index_max = -1; 3635 sop->memState[AXP_SM_STATE_TABLE_MEM7m].index_max = -1; 3636 sop->memState[AXP_WLAN_COS_MAPm].index_max = -1; 3637 sop->memState[AXP_WRX_SVP_ASSIGNMENTm].index_max = -1; 3638 sop->memState[AXP_WRX_WCDm].index_max = -1; 3639 sop->memState[AXP_WRX_SVP_ASSIGNMENTm].index_max = -1; 3640 sop->memState[AXP_WRX_WCDm].index_max = -1; 3641 sop->memState[AXP_WTX_DSCP_MAPm].index_max = -1; 3642 sop->memState[AXP_WTX_DVP_PROFILEm].index_max = -1; 3643 sop->memState[AXP_WTX_FRAG_IDm].index_max = -1; 3644 sop->memState[AXP_WTX_PRI_MAPm].index_max = -1; 3645 sop->memState[AXP_WTX_TRUNK_BLOCK_MASKm].index_max = -1; 3646 sop->memState[AXP_WTX_TRUNK_GROUP_BITMAPm].index_max = -1; 3647 sop->memState[AXP_WTX_TUNNELm].index_max = -1; 3648 sop->memState[SVM_METER_TABLEm].index_max = -1; 3649 sop->memState[VRFm].index_max = -1; 3650 break; 3651 3652 /* Spiral & SKUs */ 3653 case BCM56049_DEVICE_ID: 3654 case BCM56048_DEVICE_ID: 3655 case BCM56047_DEVICE_ID: 3656 bcm56049_mode = TRUE; 3657 3658 /* VLAN MAC */ 3659 sop->memState[VLAN_MACm].index_max = _MEM_NOT_APPLICABLE; 3660 sop->memState[VLAN_MAC_OVERFLOWm].index_max = _MEM_NOT_APPLICABLE; 3661 sop->memState[VLAN_MAC_SCRATCHm].index_max = _MEM_NOT_APPLICABLE; 3662 3663 sop->memState[VLAN_XLATEm].index_max = _MEM_NOT_APPLICABLE; 3664 sop->memState[EGR_VLAN_XLATEm].index_max = _MEM_NOT_APPLICABLE; 3665 3666 sop->memState[L3_DEFIP_PAIR_128m].index_max = _MEM_NOT_APPLICABLE; 3667 sop->memState[L3_DEFIP_PAIR_128_ONLYm].index_max = _MEM_NOT_APPLICABLE; 3668 sop->memState[L3_DEFIP_PAIR_128_DATA_ONLYm].index_max = _MEM_NOT_APPLICABLE; 3669 sop->memState[L3_DEFIP_PAIR_128_HIT_ONLYm].index_max = _MEM_NOT_APPLICABLE; 3670 sop->memState[L3_DEFIPm].index_max = _MEM_NOT_APPLICABLE; 3671 sop->memState[L3_DEFIP_ONLYm].index_max = _MEM_NOT_APPLICABLE; 3672 sop->memState[L3_DEFIP_DATA_ONLYm].index_max = _MEM_NOT_APPLICABLE; 3673 sop->memState[L3_DEFIP_HIT_ONLYm].index_max = _MEM_NOT_APPLICABLE; 3674 3675 /* sop->memState[RPFMEMORYm].index_max = _MEM_NOT_APPLICABLE;*/ 3676 3677 /* L3 Next hop */ 3678 sop->memState[INITIAL_ING_L3_NEXT_HOPm].index_max = 1023; 3679 sop->memState[ING_L3_NEXT_HOPm].index_max = 1023; 3680 sop->memState[EGR_L3_NEXT_HOPm].index_max = 1023; 3681 sop->memState[INITIAL_PROT_NHI_TABLEm].index_max = 1023; 3682 3683 sop->memState[EGR_L3_INTFm].index_max = _MEM_NOT_APPLICABLE; 3684 3685 /* L3 IPMC */ 3686 sop->memState[L3_IPMCm].index_max = _MEM_NOT_APPLICABLE; 3687 sop->memState[L3_IPMC_1m].index_max = _MEM_NOT_APPLICABLE; 3688 sop->memState[L3_IPMC_REMAPm].index_max = _MEM_NOT_APPLICABLE; 3689 sop->memState[MMU_REPL_GROUPm].index_max = _MEM_NOT_APPLICABLE; 3690 sop->memState[IP_MULTICAST_TCAMm].index_max = _MEM_NOT_APPLICABLE; 3691 3692 /* VRF */ 3693 /* sop->memState[VRFm].index_max = _MEM_NOT_APPLICABLE; */ 3694 3695 /* AXP */ 3696 sop->memState[AXP_SM_CHAR_REMAP0m].index_max = _MEM_NOT_APPLICABLE; 3697 sop->memState[AXP_SM_CHAR_REMAP1m].index_max = _MEM_NOT_APPLICABLE; 3698 sop->memState[AXP_SM_CHAR_REMAP2m].index_max = _MEM_NOT_APPLICABLE; 3699 sop->memState[AXP_SM_CHAR_REMAP3m].index_max = _MEM_NOT_APPLICABLE; 3700 sop->memState[AXP_SM_CHAR_REMAP4m].index_max = _MEM_NOT_APPLICABLE; 3701 sop->memState[AXP_SM_CHAR_REMAP5m].index_max = _MEM_NOT_APPLICABLE; 3702 sop->memState[AXP_SM_CHAR_REMAP6m].index_max = _MEM_NOT_APPLICABLE; 3703 sop->memState[AXP_SM_CHAR_REMAP7m].index_max = _MEM_NOT_APPLICABLE; 3704 sop->memState[AXP_SM_CHAR_REMAP8m].index_max = _MEM_NOT_APPLICABLE; 3705 sop->memState[AXP_SM_CHAR_REMAP9m].index_max = _MEM_NOT_APPLICABLE; 3706 sop->memState[AXP_SM_CHAR_REMAP10m].index_max = _MEM_NOT_APPLICABLE; 3707 sop->memState[AXP_SM_CHAR_REMAP11m].index_max = _MEM_NOT_APPLICABLE; 3708 sop->memState[AXP_SM_CHAR_REMAP12m].index_max = _MEM_NOT_APPLICABLE; 3709 sop->memState[AXP_SM_CHAR_REMAP13m].index_max = _MEM_NOT_APPLICABLE; 3710 sop->memState[AXP_SM_CHAR_REMAP14m].index_max = _MEM_NOT_APPLICABLE; 3711 sop->memState[AXP_SM_CHAR_REMAP15m].index_max = _MEM_NOT_APPLICABLE; 3712 sop->memState[AXP_SM_CHAR_REMAP16m].index_max = _MEM_NOT_APPLICABLE; 3713 sop->memState[AXP_SM_CHAR_REMAP17m].index_max = _MEM_NOT_APPLICABLE; 3714 sop->memState[AXP_SM_CHAR_REMAP18m].index_max = _MEM_NOT_APPLICABLE; 3715 sop->memState[AXP_SM_CHAR_REMAP19m].index_max = _MEM_NOT_APPLICABLE; 3716 sop->memState[AXP_SM_CHAR_REMAP20m].index_max = _MEM_NOT_APPLICABLE; 3717 sop->memState[AXP_SM_CHAR_REMAP21m].index_max = _MEM_NOT_APPLICABLE; 3718 sop->memState[AXP_SM_CHAR_REMAP22m].index_max = _MEM_NOT_APPLICABLE; 3719 sop->memState[AXP_SM_CHAR_REMAP23m].index_max = _MEM_NOT_APPLICABLE; 3720 sop->memState[AXP_SM_CHAR_REMAP24m].index_max = _MEM_NOT_APPLICABLE; 3721 sop->memState[AXP_SM_CHAR_REMAP25m].index_max = _MEM_NOT_APPLICABLE; 3722 sop->memState[AXP_SM_CHAR_REMAP26m].index_max = _MEM_NOT_APPLICABLE; 3723 sop->memState[AXP_SM_CHAR_REMAP27m].index_max = _MEM_NOT_APPLICABLE; 3724 sop->memState[AXP_SM_CHAR_REMAP28m].index_max = _MEM_NOT_APPLICABLE; 3725 sop->memState[AXP_SM_CHAR_REMAP29m].index_max = _MEM_NOT_APPLICABLE; 3726 sop->memState[AXP_SM_CHAR_REMAP30m].index_max = _MEM_NOT_APPLICABLE; 3727 sop->memState[AXP_SM_CHAR_REMAP31m].index_max = _MEM_NOT_APPLICABLE; 3728 sop->memState[AXP_SM_FLOW_TABLE_BULK_MATCH_DATAm].index_max = _MEM_NOT_APPLICABLE; 3729 sop->memState[AXP_SM_FLOW_TABLE_BULK_MATCH_MASKm].index_max = _MEM_NOT_APPLICABLE; 3730 sop->memState[AXP_SM_FLOW_TABLE_BULK_REPLACE_DATAm].index_max = _MEM_NOT_APPLICABLE; 3731 sop->memState[AXP_SM_FLOW_TABLE_BULK_REPLACE_MASKm].index_max = _MEM_NOT_APPLICABLE; 3732 sop->memState[AXP_SM_FLOW_TABLE_MEMm].index_max = _MEM_NOT_APPLICABLE; 3733 sop->memState[AXP_SM_MATCH_COUNTERS_MEM0m].index_max = _MEM_NOT_APPLICABLE; 3734 sop->memState[AXP_SM_MATCH_COUNTERS_MEM1m].index_max = _MEM_NOT_APPLICABLE; 3735 sop->memState[AXP_SM_MATCH_COUNTERS_MEM2m].index_max = _MEM_NOT_APPLICABLE; 3736 sop->memState[AXP_SM_MATCH_COUNTERS_MEM3m].index_max = _MEM_NOT_APPLICABLE; 3737 sop->memState[AXP_SM_MATCH_TABLE_BULK_MATCH_DATAm].index_max = _MEM_NOT_APPLICABLE; 3738 sop->memState[AXP_SM_MATCH_TABLE_BULK_MATCH_MASKm].index_max = _MEM_NOT_APPLICABLE; 3739 sop->memState[AXP_SM_MATCH_TABLE_BULK_REPLACE_DATAm].index_max = _MEM_NOT_APPLICABLE; 3740 sop->memState[AXP_SM_MATCH_TABLE_BULK_REPLACE_MASKm].index_max = _MEM_NOT_APPLICABLE; 3741 sop->memState[AXP_SM_MATCH_TABLE_MEM0m].index_max = _MEM_NOT_APPLICABLE; 3742 sop->memState[AXP_SM_MATCH_TABLE_MEM1m].index_max = _MEM_NOT_APPLICABLE; 3743 sop->memState[AXP_SM_MATCH_TABLE_MEM2m].index_max = _MEM_NOT_APPLICABLE; 3744 sop->memState[AXP_SM_MATCH_TABLE_MEM3m].index_max = _MEM_NOT_APPLICABLE; 3745 sop->memState[AXP_SM_PACKET_BUFFER_MEMm].index_max = _MEM_NOT_APPLICABLE; 3746 sop->memState[AXP_SM_STATE_TABLE_BULK_MATCH_DATAm].index_max = _MEM_NOT_APPLICABLE; 3747 sop->memState[AXP_SM_STATE_TABLE_BULK_MATCH_MASKm].index_max = _MEM_NOT_APPLICABLE; 3748 sop->memState[AXP_SM_STATE_TABLE_BULK_REPLACE_DATAm].index_max = _MEM_NOT_APPLICABLE; 3749 sop->memState[AXP_SM_STATE_TABLE_BULK_REPLACE_MASKm].index_max = _MEM_NOT_APPLICABLE; 3750 sop->memState[AXP_SM_STATE_TABLE_MEM0m].index_max = _MEM_NOT_APPLICABLE; 3751 sop->memState[AXP_SM_STATE_TABLE_MEM1m].index_max = _MEM_NOT_APPLICABLE; 3752 sop->memState[AXP_SM_STATE_TABLE_MEM2m].index_max = _MEM_NOT_APPLICABLE; 3753 sop->memState[AXP_SM_STATE_TABLE_MEM3m].index_max = _MEM_NOT_APPLICABLE; 3754 sop->memState[AXP_SM_STATE_TABLE_MEM4m].index_max = _MEM_NOT_APPLICABLE; 3755 sop->memState[AXP_SM_STATE_TABLE_MEM5m].index_max = _MEM_NOT_APPLICABLE; 3756 sop->memState[AXP_SM_STATE_TABLE_MEM6m].index_max = _MEM_NOT_APPLICABLE; 3757 sop->memState[AXP_SM_STATE_TABLE_MEM7m].index_max = _MEM_NOT_APPLICABLE; 3758 sop->memState[AXP_WLAN_COS_MAPm].index_max = _MEM_NOT_APPLICABLE; 3759 sop->memState[AXP_WRX_SVP_ASSIGNMENTm].index_max = _MEM_NOT_APPLICABLE; 3760 sop->memState[AXP_WRX_WCDm].index_max = _MEM_NOT_APPLICABLE; 3761 sop->memState[AXP_WRX_SVP_ASSIGNMENTm].index_max = _MEM_NOT_APPLICABLE; 3762 sop->memState[AXP_WRX_WCDm].index_max = _MEM_NOT_APPLICABLE; 3763 sop->memState[AXP_WTX_DSCP_MAPm].index_max = _MEM_NOT_APPLICABLE; 3764 sop->memState[AXP_WTX_DVP_PROFILEm].index_max = _MEM_NOT_APPLICABLE; 3765 sop->memState[AXP_WTX_FRAG_IDm].index_max = _MEM_NOT_APPLICABLE; 3766 sop->memState[AXP_WTX_PRI_MAPm].index_max = _MEM_NOT_APPLICABLE; 3767 sop->memState[AXP_WTX_TRUNK_BLOCK_MASKm].index_max = _MEM_NOT_APPLICABLE; 3768 sop->memState[AXP_WTX_TRUNK_GROUP_BITMAPm].index_max = _MEM_NOT_APPLICABLE; 3769 sop->memState[AXP_WTX_TUNNELm].index_max = _MEM_NOT_APPLICABLE; 3770 3771 /* Counters */ 3772 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_0m].index_max = 1023; 3773 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_1m].index_max = 1023; 3774 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_2m].index_max = 1023; 3775 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_3m].index_max = 1023; 3776 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_4m].index_max = 1023; 3777 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_5m].index_max = 1023; 3778 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_6m].index_max = 1023; 3779 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_7m].index_max = 1023; 3780 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_8m].index_max = _MEM_NOT_APPLICABLE; 3781 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_9m].index_max = _MEM_NOT_APPLICABLE; 3782 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_10m].index_max = _MEM_NOT_APPLICABLE; 3783 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_11m].index_max = _MEM_NOT_APPLICABLE; 3784 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_12m].index_max = _MEM_NOT_APPLICABLE; 3785 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_13m].index_max = _MEM_NOT_APPLICABLE; 3786 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_14m].index_max = _MEM_NOT_APPLICABLE; 3787 sop->memState[ING_FLEX_CTR_COUNTER_TABLE_15m].index_max = _MEM_NOT_APPLICABLE; 3788 sop->memState[ING_FLEX_CTR_OFFSET_TABLE_8m].index_max = _MEM_NOT_APPLICABLE; 3789 sop->memState[ING_FLEX_CTR_OFFSET_TABLE_9m].index_max = _MEM_NOT_APPLICABLE; 3790 sop->memState[ING_FLEX_CTR_OFFSET_TABLE_10m].index_max = _MEM_NOT_APPLICABLE; 3791 sop->memState[ING_FLEX_CTR_OFFSET_TABLE_11m].index_max = _MEM_NOT_APPLICABLE; 3792 sop->memState[ING_FLEX_CTR_OFFSET_TABLE_12m].index_max = _MEM_NOT_APPLICABLE; 3793 sop->memState[ING_FLEX_CTR_OFFSET_TABLE_13m].index_max = _MEM_NOT_APPLICABLE; 3794 sop->memState[ING_FLEX_CTR_OFFSET_TABLE_14m].index_max = _MEM_NOT_APPLICABLE; 3795 sop->memState[ING_FLEX_CTR_OFFSET_TABLE_15m].index_max = _MEM_NOT_APPLICABLE; 3796 3797 break; 3798 3799 default: 3800 break; 3801 } 3802 3803 #ifdef BCM_ISM_SUPPORT 3804 switch (dev_id) { 3805 case BCM56042_DEVICE_ID: 3806 case BCM56041_DEVICE_ID: 3807 case BCM56040_DEVICE_ID: 3808 scale = 6; 3809 break; 3810 default: 3811 scale = 5; 3812 break; 3813 } 3814 3815 3816 if (soc_feature(unit, soc_feature_ism_memory)) { 3817 soc_ism_mem_size_config_t ism_alloc_size_int[SOC_ISM_MEM_TOTAL]; 3818 sal_memcpy(ism_alloc_size_int, ism_alloc_size, sizeof(ism_alloc_size_int)); 3819 ism_alloc_size_int[0].size = bcm56049_mode ? 0 : 3820 soc_property_get(unit, spn_VLAN_XLATE_MEM_ENTRIES, 3821 (ism_alloc_size_int[0].size*5)/scale); 3822 ism_alloc_size_int[1].size = 3823 soc_property_get(unit, spn_L2_MEM_ENTRIES, 3824 (ism_alloc_size_int[1].size*5)/scale); 3825 ism_alloc_size_int[2].size = bcm56049_mode ? 0 : 3826 soc_property_get(unit, spn_L3_MEM_ENTRIES, 3827 (ism_alloc_size_int[2].size*5)/scale); 3828 ism_alloc_size_int[3].size = bcm56049_mode ? 0 : 3829 soc_property_get(unit, spn_EGR_VLAN_XLATE_MEM_ENTRIES, 3830 (ism_alloc_size_int[3].size*5)/scale); 3831 ism_alloc_size_int[4].size = bcm56049_mode ? 0 : 3832 soc_property_get(unit, spn_MPLS_MEM_ENTRIES, 3833 (ism_alloc_size_int[4].size*5)/scale); 3834 if (ism_alloc_size_int[1].size <= 0 && ism_alloc_size_int[5].size <= 0) { 3835 LOG_CLI((BSL_META_U(unit, 3836 "No L2 memory configured !!\n"))); 3837 return SOC_E_RESOURCE; 3838 } 3839 ism_alloc_size_int[0].banks = 3840 soc_property_get(unit, spn_VLAN_XLATE_MEM_BANKS, 3841 ism_alloc_size_int[0].banks); 3842 ism_alloc_size_int[1].banks = 3843 soc_property_get(unit, spn_L2_MEM_BANKS, 3844 ism_alloc_size_int[1].banks); 3845 ism_alloc_size_int[2].banks = 3846 soc_property_get(unit, spn_L3_MEM_BANKS, 3847 ism_alloc_size_int[2].banks); 3848 ism_alloc_size_int[3].banks = 3849 soc_property_get(unit, spn_EGR_VLAN_XLATE_MEM_BANKS, 3850 ism_alloc_size_int[3].banks); 3851 ism_alloc_size_int[4].banks = 3852 soc_property_get(unit, spn_MPLS_MEM_BANKS, 3853 ism_alloc_size_int[4].banks); 3854 rv = soc_ism_mem_config(unit, ism_alloc_size_int, COUNTOF(ism_alloc_size_int)); 3855 if (rv != SOC_E_NONE) { 3856 LOG_CLI((BSL_META_U(unit, 3857 "Invalid or unsupported ISM memory config !!\n"))); 3858 return rv; 3859 } 3860 } 3861 #endif 3862 return rv; 3863 } 3864 3865 /* _soc_hx4_mmu_tdm_array_init 3866 * This enables reuse of TR3 code for MMU/LLS init through _soc_tr3_mmu_tdm_init 3867 * _soc_hx4_mmu_tdm_array_init copies requested tdm config into _soc_tr3_tdm_arr 3868 * and sets the _soc_tr3_tdm_size (both globals shared across TR3/HX4 code). 3869 */ 3870 void 3871 _soc_hx4_mmu_tdm_array_init(int unit) 3872 { 3873 static uint32 hx4_tdm_0[] = { /* HX4_1G_150_A */ 3874 61, 57, 1, 13, 63, 53, 25, 61, 58, 37, 5, 63, 54, 17, 29, 61, 57, 41, 63, 55, 9, 81, 61, 58, 33, 63, 56, 81, 0, 3875 61, 57, 2, 21, 63, 53, 26, 61, 58, 45, 6, 63, 54, 14, 30, 61, 57, 38, 63, 55, 18, 81, 61, 58, 42, 63, 56, 81, 0, 3876 61, 57, 10, 22, 63, 53, 34, 61, 58, 46, 3, 63, 54, 15, 27, 61, 57, 39, 63, 55, 7, 81, 61, 58, 31, 63, 56, 81, -1, 3877 61, 57, 11, 19, 63, 53, 35, 61, 58, 43, 4, 63, 54, 23, 28, 61, 57, 47, 63, 55, 16, 81, 61, 58, 40, 63, 56, 81, 0, 3878 61, 57, 8, 20, 63, 53, 32, 61, 58, 44, 12, 63, 54, 24, 36, 61, 57, 48, 63, 55, 49, 81, 61, 58, -1, 63, 56, 81, 0 3879 }; 3880 static uint32 hx4_tdm_1[] = { /* HX4_1G_150_B */ 3881 53, 57, 1, 13, 54, 61, 25, 55, 57, 37, 5, 56, 61, 17, 29, 53, 57, 41, 54, 61, 9, 81, 55, 57, 33, 56, 61, 81, 0, 3882 53, 57, 2, 21, 54, 61, 26, 55, 57, 45, 6, 56, 61, 14, 30, 53, 57, 38, 54, 61, 18, 81, 55, 57, 42, 56, 61, 81, 0, 3883 53, 57, 10, 22, 54, 61, 34, 55, 57, 46, 3, 56, 61, 15, 27, 53, 57, 39, 54, 61, 7, 81, 55, 57, 31, 56, 61, 81, -1, 3884 53, 57, 11, 19, 54, 61, 35, 55, 57, 43, 4, 56, 61, 23, 28, 53, 57, 47, 54, 61, 16, 81, 55, 57, 40, 56, 61, 81, 0, 3885 53, 57, 8, 20, 54, 61, 32, 55, 57, 44, 12, 56, 61, 24, 36, 53, 57, 48, 54, 61, 49, 81, 55, 57, -1, 56, 61, 81, 0 3886 }; 3887 static uint32 hx4_tdm_2[] = { /* RGR_XFI_150 */ 3888 53, 57, 61, 81, 54, 58, 62, 55, 59, 63, 1, 56, 60, 64, 81, 53, 57, 61, 54, 58, 62, 0, 55, 59, 63, 56, 60, 64, -1, 3889 53, 57, 61, 81, 54, 58, 62, 55, 59, 63, 2, 56, 60, 64, 81, 53, 57, 61, 54, 58, 62, 0, 55, 59, 63, 56, 60, 64, -1, 3890 53, 57, 61, 81, 54, 58, 62, 55, 59, 63, 3, 56, 60, 64, 81, 53, 57, 61, 54, 58, 62, 0, 55, 59, 63, 56, 60, 64, -1, 3891 53, 57, 61, 81, 54, 58, 62, 55, 59, 63, 4, 56, 60, 64, 81, 53, 57, 61, 54, 58, 62, 0, 55, 59, 63, 56, 60, 64, -1, 3892 53, 57, 61, 81, 54, 58, 62, 55, 59, 63, 49, 56, 60, 64, 81, 53, 57, 61, 54, 58, 62, 0, 55, 59, 63, 56, 60, 64, -1 3893 }; 3894 static uint32 hx4_tdm_3[] = { /* HX4_1G_200_A */ 3895 53, 57, 61, 1, 13, 54, 57, 61, 25, 37, 55, 57, 61, 5, 17, 56, 57, 61, 29, 41, 53, 57, 61, 81, 54, 57, 61, 9, 55, 57, 61, 33, 0, 56, 57, 61, 81, 3896 53, 57, 61, 2, 21, 54, 57, 61, 26, 45, 55, 57, 61, 6, 14, 56, 57, 61, 30, 38, 53, 57, 61, 81, 54, 57, 61, 18, 55, 57, 61, 42, 0, 56, 57, 61, 81, 3897 53, 57, 61, 10, 22, 54, 57, 61, 34, 46, 55, 57, 61, 3, 15, 56, 57, 61, 27, 39, 53, 57, 61, 81, 54, 57, 61, 7, 55, 57, 61, 31, -1, 56, 57, 61, 81, 3898 53, 57, 61, 11, 19, 54, 57, 61, 35, 43, 55, 57, 61, 4, 23, 56, 57, 61, 28, 47, 53, 57, 61, 81, 54, 57, 61, 16, 55, 57, 61, 40, 0, 56, 57, 61, 81, 3899 53, 57, 61, 8, 20, 54, 57, 61, 32, 44, 55, 57, 61, 12, 24, 56, 57, 61, 36, 48, 53, 57, 61, 81, 54, 57, 61, 49, 55, 57, 61, -1, 0, 56, 57, 61, 81 3900 }; 3901 static uint32 hx4_tdm_4[] = { /* HX4_1G_200_B */ 3902 53, 57, 61, 1, 13, 53, 57, 61, 25, 37, 53, 57, 61, 5, 17, 53, 57, 61, 29, 41, 53, 57, 61, 81, 53, 57, 61, 9, 53, 57, 61, 33, 0, 53, 57, 61, 81, 3903 53, 57, 61, 2, 21, 53, 57, 61, 26, 45, 53, 57, 61, 6, 14, 53, 57, 61, 30, 38, 53, 57, 61, 81, 53, 57, 61, 18, 53, 57, 61, 42, 0, 53, 57, 61, 81, 3904 53, 57, 61, 10, 22, 53, 57, 61, 34, 46, 53, 57, 61, 3, 15, 53, 57, 61, 27, 39, 53, 57, 61, 81, 53, 57, 61, 7, 53, 57, 61, 31, -1, 53, 57, 61, 81, 3905 53, 57, 61, 11, 19, 53, 57, 61, 35, 43, 53, 57, 61, 4, 23, 53, 57, 61, 28, 47, 53, 57, 61, 81, 53, 57, 61, 16, 53, 57, 61, 40, 0, 53, 57, 61, 81, 3906 53, 57, 61, 8, 20, 53, 57, 61, 32, 44, 53, 57, 61, 12, 24, 53, 57, 61, 36, 48, 53, 57, 61, 81, 53, 57, 61, 49, 53, 57, 61, -1, 0, 53, 57, 61, 81 3907 }; 3908 static uint32 hx4_tdm_5[] = { /* RGR_XFI_200 */ 3909 53, 57, 61, 81, 0, 53, 57, 61, -1, 53, 57, 61, 81, -1, 53, 57, 61, -1, 1, 53, 57, 61, 81, 0, 53, 57, 61, -1, 53, 57, 61, 81, -1, 53, 57, 61, -1, 3910 53, 57, 61, 81, 0, 53, 57, 61, -1, 53, 57, 61, 81, -1, 53, 57, 61, -1, 2, 53, 57, 61, 81, 0, 53, 57, 61, -1, 53, 57, 61, 81, -1, 53, 57, 61, -1, 3911 53, 57, 61, 81, 0, 53, 57, 61, -1, 53, 57, 61, 81, -1, 53, 57, 61, -1, 3, 53, 57, 61, 81, 0, 53, 57, 61, -1, 53, 57, 61, 81, -1, 53, 57, 61, -1, 3912 53, 57, 61, 81, 0, 53, 57, 61, -1, 53, 57, 61, 81, -1, 53, 57, 61, -1, 4, 53, 57, 61, 81, 0, 53, 57, 61, -1, 53, 57, 61, 81, -1, 53, 57, 61, -1, 3913 53, 57, 61, 81, 0, 53, 57, 61, -1, 53, 57, 61, 81, -1, 53, 57, 61, -1, 49, 53, 57, 61, 81, 0, 53, 57, 61, -1, 53, 57, 61, 81, -1, 53, 57, 61, -1 3914 }; 3915 static uint32 hx4_tdm_6[] = { /* HX4_1G_130 */ 3916 53, 57, 1, 13, 54, 61, 25, 55, 57, 5, 56, 61, 17, 53, 57, 81, 54, 61, 9, 55, 57, -1, 56, 61, 0, 3917 53, 57, 2, 21, 54, 61, 26, 55, 57, 6, 56, 61, 14, 53, 57, 81, 54, 61, 18, 55, 57, 81, 56, 61, 0, 3918 53, 57, 10, 22, 54, 61, 27, 55, 57, 3, 56, 61, 15, 53, 57, 81, 54, 61, 7, 55, 57, 81, 56, 61, -1, 3919 53, 57, 11, 19, 54, 61, 28, 55, 57, 4, 56, 61, 23, 53, 57, 81, 54, 61, 16, 55, 57, 81, 56, 61, 0, 3920 53, 57, 8, 20, 54, 61, -1, 55, 57, 12, 56, 61, 24, 53, 57, 81, 54, 61, 49, 55, 57, 81, 56, 61, 0 3921 }; 3922 static uint32 hx4_tdm_7[] = { /* HX4_1G_150_C */ 3923 53, 57, 1, 13, 54, 61, 25, 55, 57, 37, 5, 56, 61, 17, 29, 53, 57, 41, 54, 61, 9, 81, 55, 57, 33, 56, 61, 81, 0, 3924 53, 57, 1, 21, 54, 61, 25, 55, 57, 45, 5, 56, 61, 13, 29, 53, 57, 37, 54, 61, 17, 81, 55, 57, 41, 56, 61, 81, 0, 3925 53, 57, 9, 21, 54, 61, 33, 55, 57, 45, 1, 56, 61, 13, 25, 53, 57, 37, 54, 61, 5, 81, 55, 57, 29, 56, 61, 81, -1, 3926 53, 57, 9, 17, 54, 61, 33, 55, 57, 41, 1, 56, 61, 21, 25, 53, 57, 45, 54, 61, 13, 81, 55, 57, 37, 56, 61, 81, 0, 3927 53, 57, 5, 17, 54, 61, 29, 55, 57, 41, 9, 56, 61, 21, 33, 53, 57, 45, 54, 61, 49, 81, 55, 57, -1, 56, 61, 81, 0 3928 }; 3929 static uint32 hx4_tdm_8[] = { /* HX4_1G_200_C */ 3930 53, 57, 61, 1, 13, 53, 57, 61, 25, 37, 53, 57, 61, 5, 17, 53, 57, 61, 29, 41, 53, 57, 61, 81, 53, 57, 61, 9, 53, 57, 61, 33, 0, 53, 57, 61, 81, 3931 53, 57, 61, 1, 21, 53, 57, 61, 25, 45, 53, 57, 61, 5, 13, 53, 57, 61, 29, 37, 53, 57, 61, 81, 53, 57, 61, 17, 53, 57, 61, 41, 0, 53, 57, 61, 81, 3932 53, 57, 61, 9, 21, 53, 57, 61, 33, 45, 53, 57, 61, 1, 13, 53, 57, 61, 25, 37, 53, 57, 61, 81, 53, 57, 61, 5, 53, 57, 61, 29, -1, 53, 57, 61, 81, 3933 53, 57, 61, 9, 17, 53, 57, 61, 33, 41, 53, 57, 61, 1, 21, 53, 57, 61, 25, 45, 53, 57, 61, 81, 53, 57, 61, 13, 53, 57, 61, 37, 0, 53, 57, 61, 81, 3934 53, 57, 61, 5, 17, 53, 57, 61, 29, 41, 53, 57, 61, 9, 21, 53, 57, 61, 33, 45, 53, 57, 61, 81, 53, 57, 61, 49, 53, 57, 61, -1, 0, 53, 57, 61, 81 3935 }; 3936 static uint32 hx4_tdm_9[] = { /* HX4_1G_200_D */ 3937 53, 57, 61, 1, 13, 54, 58, 62, 25, -1, 55, 59, 63, 5, 17, 56, 60, 64, 29, 37, 53, 57, 61, 81, 54, 58, 62, 9, 55, 59, 63, 33, 0, 56, 60, 64, 81, 3938 53, 57, 61, 2, 21, 54, 58, 62, 26, -1, 55, 59, 63, 6, 14, 56, 60, 64, 30, 38, 53, 57, 61, 81, 54, 58, 62, 18, 55, 59, 63, -1, 0, 56, 60, 64, 81, 3939 53, 57, 61, 10, 22, 54, 58, 62, 34, -1, 55, 59, 63, 3, 15, 56, 60, 64, 27, 39, 53, 57, 61, 81, 54, 58, 62, 7, 55, 59, 63, 31, -1, 56, 60, 64, 81, 3940 53, 57, 61, 11, 19, 54, 58, 62, 35, -1, 55, 59, 63, 4, 23, 56, 60, 64, 28, 40, 53, 57, 61, 81, 54, 58, 62, 16, 55, 59, 63, -1, 0, 56, 60, 64, 81, 3941 53, 57, 61, 8, 20, 54, 58, 62, 32, -1, 55, 59, 63, 12, 24, 56, 60, 64, 36, -1, 53, 57, 61, 81, 54, 58, 62, 49, 55, 59, 63, -1, 0, 56, 60, 64, 81 3942 }; 3943 static uint32 hx4_tdm_10[] = { /* HX4_1G_200_E */ 3944 53, 57, -1, 1, 13, 55, 57, -1, 25, 37, 53, 57, -1, 5, 17, 55, 57, -1, 29, 41, 53, 57, -1, 81, 55, 57, -1, 9, 53, 57, -1, 33, 0, 55, 57, -1, 81, 3945 53, 57, -1, 2, 21, 55, 57, -1, 25, 45, 53, 57, -1, 6, 14, 55, 57, -1, 29, 37, 53, 57, -1, 81, 55, 57, -1, 18, 53, 57, -1, 41, 0, 55, 57, -1, 81, 3946 53, 57, -1, 10, 22, 55, 57, -1, 33, 45, 53, 57, -1, 3, 15, 55, 57, -1, 25, 37, 53, 57, -1, 81, 55, 57, -1, 7, 53, 57, -1, 29, -1, 55, 57, -1, 81, 3947 53, 57, -1, 11, 19, 55, 57, -1, 33, 41, 53, 57, -1, 4, 23, 55, 57, -1, 25, 45, 53, 57, -1, 81, 55, 57, -1, 16, 53, 57, -1, 37, 0, 55, 57, -1, 81, 3948 53, 57, -1, 8, 20, 55, 57, -1, 29, 41, 53, 57, -1, 12, 24, 55, 57, -1, 33, 45, 53, 57, -1, 81, 55, 57, -1, 49, 53, 57, -1, -1, 0, 55, 57, -1, 81 3949 }; 3950 static uint32 hx4_tdm_11[] = { /* RGR_2P5G_150 */ 3951 53, 57, 1, 13, -1, 61, 25, 54, 58, 37, 5, 81, 62, 17, 29, 55, 59, 41, -1, 63, -1, -1, 56, 60, -1, -1, 64, 81, 0, 3952 53, 57, 9, 21, -1, 61, 33, 54, 58, 45, 1, 81, 62, 13, 25, 55, 59, 37, -1, 63, -1, -1, 56, 60, -1, -1, 64, 81, 0, 3953 53, 57, 5, 17, -1, 61, 29, 54, 58, 41, 9, 81, 62, 21, 33, 55, 59, 45, -1, 63, -1, -1, 56, 60, -1, -1, 64, 81, -1, 3954 53, 57, 1, 13, -1, 61, 25, 54, 58, 37, 5, 81, 62, 17, 29, 55, 59, 41, -1, 63, -1, -1, 56, 60, -1, -1, 64, 81, 0, 3955 53, 57, 9, 21, -1, 61, 33, 54, 58, 45, 49, 81, 62, 17, -1, 55, 59, -1, -1, 63, -1, -1, 56, 60, -1, -1, 64, 81, 0 3956 }; 3957 static uint32 hx4_tdm_492[] = { /* Subset of HX4_1G_200_D - 56548H FireScout*/ 3958 53, 57, 61, 1, 13, 53, 57, 61, -1, -1, 53, 57, 61, 5, 17, 53, 57, 61, -1, -1, 53, 57, 61, 81, 53, 57, 61, 9, 53, 57, 61, -1, 0, 53, 57, 61, 81, 3959 53, 57, 61, 2, -1, 53, 57, 61, -1, -1, 53, 57, 61, 6, 14, 53, 57, 61, -1, -1, 53, 57, 61, 81, 53, 57, 61, 18, 53, 57, 61, -1, 0, 53, 57, 61, 81, 3960 53, 57, 61, 10, -1, 53, 57, 61, -1, -1, 53, 57, 61, 3, 15, 53, 57, 61, -1, -1, 53, 57, 61, 81, 53, 57, 61, 7, 53, 57, 61, -1, -1, 53, 57, 61, 81, 3961 53, 57, 61, 11, 19, 53, 57, 61, -1, -1, 53, 57, 61, 4, -1, 53, 57, 61, -1, -1, 53, 57, 61, 81, 53, 57, 61, 16, 53, 57, 61, -1, 0, 53, 57, 61, 81, 3962 53, 57, 61, 8, 20, 53, 57, 61, -1, -1, 53, 57, 61, 12, -1, 53, 57, 61, -1, -1, 53, 57, 61, 81, 53, 57, 61, 49, 53, 57, 61, -1, 0, 53, 57, 61, 81 3963 }; 3964 _soc_tr3_flex_tdm_inf_t flex_tr3_tdm_492 = { 3965 1, 3966 { 0, 0, 0, 0, 0, 37, 37, 37 }, 3967 { 3, 13, 27, 4, 14, 0, 1, 2 }, 3968 { 0, 0, 0, 0, 0, 5, 5, 5 } 3969 }; 3970 static uint32 hx4_tdm_491[] = { /* Subset of HX4_1G_200_D - 56548 FireScout*/ 3971 53, 57, 61, 1, 13, 53, 57, 61, 25, -1, 53, 57, 61, 5, 17, 53, 57, 61, -1, -1, 53, 57, 61, 81, 53, 57, 61, 9, 53, 57, 61, -1, 0, 53, 57, 61, 81, 3972 53, 57, 61, 2, 21, 53, 57, 61, 26, -1, 53, 57, 61, 6, 14, 53, 57, 61, -1, -1, 53, 57, 61, 81, 53, 57, 61, 18, 53, 57, 61, -1, 0, 53, 57, 61, 81, 3973 53, 57, 61, 10, 22, 53, 57, 61, -1, -1, 53, 57, 61, 3, 15, 53, 57, 61, 27, -1, 53, 57, 61, 81, 53, 57, 61, 7, 53, 57, 61, -1, -1, 53, 57, 61, 81, 3974 53, 57, 61, 11, 19, 53, 57, 61, -1, -1, 53, 57, 61, 4, 23, 53, 57, 61, 28, -1, 53, 57, 61, 81, 53, 57, 61, 16, 53, 57, 61, -1, 0, 53, 57, 61, 81, 3975 53, 57, 61, 8, 20, 53, 57, 61, -1, -1, 53, 57, 61, 12, 24, 53, 57, 61, -1, -1, 53, 57, 61, 81, 53, 57, 61, 49, 53, 57, 61, -1, 0, 53, 57, 61, 81 3976 }; 3977 _soc_tr3_flex_tdm_inf_t flex_tr3_tdm_491 = { 3978 1, 3979 { 0, 0, 0, 0, 0, 0, 0, 37, 37, 37 }, 3980 { 3, 13, 27, 4, 14, 41, 8, 0, 1, 2 }, 3981 { 0, 0, 0, 0, 0, 0, 0, 5, 5, 5 } 3982 }; 3983 static uint32 hx4_tdm_490[] = { /* HX4_1G_200_D - 56547 FireScout*/ 3984 53, 57, 61, 1, 13, 53, 57, 61, 25, -1, 53, 57, 61, 5, 17, 53, 57, 61, 29, 37, 53, 57, 61, 81, 53, 57, 61, 9, 53, 57, 61, 33, 0, 53, 57, 61, 81, 3985 53, 57, 61, 2, 21, 53, 57, 61, 26, -1, 53, 57, 61, 6, 14, 53, 57, 61, 30, 38, 53, 57, 61, 81, 53, 57, 61, 18, 53, 57, 61, -1, 0, 53, 57, 61, 81, 3986 53, 57, 61, 10, 22, 53, 57, 61, 34, -1, 53, 57, 61, 3, 15, 53, 57, 61, 27, 39, 53, 57, 61, 81, 53, 57, 61, 7, 53, 57, 61, 31, -1, 53, 57, 61, 81, 3987 53, 57, 61, 11, 19, 53, 57, 61, 35, -1, 53, 57, 61, 4, 23, 53, 57, 61, 28, 40, 53, 57, 61, 81, 53, 57, 61, 16, 53, 57, 61, -1, 0, 53, 57, 61, 81, 3988 53, 57, 61, 8, 20, 53, 57, 61, 32, -1, 53, 57, 61, 12, 24, 53, 57, 61, 36, -1, 53, 57, 61, 81, 53, 57, 61, 49, 53, 57, 61, -1, 0, 53, 57, 61, 81 3989 }; 3990 _soc_tr3_flex_tdm_inf_t flex_tr3_tdm_490 = { 3991 1, 3992 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 37, 37, 37 }, 3993 { 3, 13, 27, 4, 14, 41, 8, 18, 31, 19, 0, 1, 2 }, 3994 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5, 5, 5 } 3995 }; 3996 static uint32 hx4_tdm_495[] = { /* 12xF.QSGMII + F.HG[42] + 2xHG[42] + 1GE */ 3997 53, 57, 61, 1, 13, 53, 57, 61, 25, 37, 53, 57, 61, 5, 17, 53, 57, 61, 29, 41, 53, 57, 61, 81, 53, 57, 61, 9, 53, 57, 61, 33, 0, 53, 57, 61, 81, 3998 53, 57, 61, 2, 21, 53, 57, 61, 26, 45, 53, 57, 61, 6, 14, 53, 57, 61, 30, 38, 53, 57, 61, 81, 53, 57, 61, 18, 53, 57, 61, 42, 0, 53, 57, 61, 81, 3999 53, 57, 61, 10, 22, 53, 57, 61, 34, 46, 53, 57, 61, 3, 15, 53, 57, 61, 27, 39, 53, 57, 61, 81, 53, 57, 61, 7, 53, 57, 61, 31, -1, 53, 57, 61, 81, 4000 53, 57, 61, 11, 19, 53, 57, 61, 35, 43, 53, 57, 61, 4, 23, 53, 57, 61, 28, 47, 53, 57, 61, 81, 53, 57, 61, 16, 53, 57, 61, 40, 0, 53, 57, 61, 81, 4001 53, 57, 61, 8, 20, 53, 57, 61, 32, 44, 53, 57, 61, 12, 24, 53, 57, 61, 36, 48, 53, 57, 61, 81, 53, 57, 61, 49, 53, 57, 61, -1, 0, 53, 57, 61, 81 4002 }; 4003 _soc_tr3_flex_tdm_inf_t flex_tr3_tdm_495 = { 4004 1, 4005 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 37 }, 4006 { 3, 13, 27, 4, 14, 41, 8, 18, 31, 9, 19, 46, 0 }, 4007 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5 } 4008 }; 4009 static uint32 hx4_tdm_500[] = { /* HX4_1G_200_E */ 4010 53, 57, -1, 1, 13, 53, 57, -1, 25, 37, 53, 57, -1, 5, 17, 53, 57, -1, 29, 41, 53, 57, -1, 81, 53, 57, -1, 9, 53, 57, -1, 33, 0, 53, 57, -1, 81, 4011 53, 57, -1, 2, 21, 53, 57, -1, 26, 45, 53, 57, -1, 6, 14, 53, 57, -1, 30, 38, 53, 57, -1, 81, 53, 57, -1, 18, 53, 57, -1, 42, 0, 53, 57, -1, 81, 4012 53, 57, -1, 10, 22, 53, 57, -1, 34, 46, 53, 57, -1, 3, 15, 53, 57, -1, 27, 39, 53, 57, -1, 81, 53, 57, -1, 7, 53, 57, -1, 31, -1, 53, 57, -1, 81, 4013 53, 57, -1, 11, 19, 53, 57, -1, 35, 43, 53, 57, -1, 4, 23, 53, 57, -1, 28, 47, 53, 57, -1, 81, 53, 57, -1, 16, 53, 57, -1, 40, 0, 53, 57, -1, 81, 4014 53, 57, -1, 8, 20, 53, 57, -1, 32, 44, 53, 57, -1, 12, 24, 53, 57, -1, 36, 48, 53, 57, -1, 81, 53, 57, -1, 49, 53, 57, -1, -1, 0, 53, 57, -1, 81 4015 }; 4016 _soc_tr3_flex_tdm_inf_t flex_tr3_tdm_500 = { 4017 1, 4018 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 37, 37 }, 4019 { 3, 13, 27, 4, 14, 41, 8, 18, 31, 9, 19, 46, 0, 1 }, 4020 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5, 5 } 4021 }; 4022 static uint32 hx4_tdm_497[] = { /* HX4_1G_200_D*: 10xF.QSGMII + 3xFlex[4x10] + 1GE */ 4023 53, 57, 61, 1, 13, 53, 57, 61, 25, -1, 53, 57, 61, 5, 17, 53, 57, 61, 29, 37, 53, 57, 61, 81, 53, 57, 61, 9, 53, 57, 61, 33, 0, 53, 57, 61, 81, 4024 53, 57, 61, 2, 21, 53, 57, 61, 26, -1, 53, 57, 61, 6, 14, 53, 57, 61, 30, 38, 53, 57, 61, 81, 53, 57, 61, 18, 53, 57, 61, -1, 0, 53, 57, 61, 81, 4025 53, 57, 61, 10, 22, 53, 57, 61, 34, -1, 53, 57, 61, 3, 15, 53, 57, 61, 27, 39, 53, 57, 61, 81, 53, 57, 61, 7, 53, 57, 61, 31, -1, 53, 57, 61, 81, 4026 53, 57, 61, 11, 19, 53, 57, 61, 35, -1, 53, 57, 61, 4, 23, 53, 57, 61, 28, 40, 53, 57, 61, 81, 53, 57, 61, 16, 53, 57, 61, -1, 0, 53, 57, 61, 81, 4027 53, 57, 61, 8, 20, 53, 57, 61, 32, -1, 53, 57, 61, 12, 24, 53, 57, 61, 36, -1, 53, 57, 61, 81, 53, 57, 61, 49, 53, 57, 61, -1, 0, 53, 57, 61, 81 4028 }; 4029 _soc_tr3_flex_tdm_inf_t flex_tr3_tdm_497 = { 4030 1, 4031 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 37, 37, 37 }, 4032 { 3, 13, 27, 4, 14, 41, 8, 18, 31, 19, 0, 1, 2 }, 4033 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5, 5, 5 } 4034 }; 4035 static uint32 hx4_tdm_510[] = { /* HX4_1G_200_E*: 12xF.QSGMII + 2xFlex[4x10] + 1GE */ 4036 53, 57, -1, 1, 13, 53, 57, -1, 25, 37, 53, 57, -1, 5, 17, 53, 57, -1, 29, 41, 53, 57, -1, 81, 53, 57, -1, 9, 53, 57, -1, 33, 0, 53, 57, -1, 81, 4037 53, 57, -1, 2, 21, 53, 57, -1, 26, 45, 53, 57, -1, 6, 14, 53, 57, -1, 30, 38, 53, 57, -1, 81, 53, 57, -1, 18, 53, 57, -1, 42, 0, 53, 57, -1, 81, 4038 53, 57, -1, 10, 22, 53, 57, -1, 34, 46, 53, 57, -1, 3, 15, 53, 57, -1, 27, 39, 53, 57, -1, 81, 53, 57, -1, 7, 53, 57, -1, 31, -1, 53, 57, -1, 81, 4039 53, 57, -1, 11, 19, 53, 57, -1, 35, 43, 53, 57, -1, 4, 23, 53, 57, -1, 28, 47, 53, 57, -1, 81, 53, 57, -1, 16, 53, 57, -1, 40, 0, 53, 57, -1, 81, 4040 53, 57, -1, 8, 20, 53, 57, -1, 32, 44, 53, 57, -1, 12, 24, 53, 57, -1, 36, 48, 53, 57, -1, 81, 53, 57, -1, 49, 53, 57, -1, -1, 0, 53, 57, -1, 81 4041 }; 4042 _soc_tr3_flex_tdm_inf_t flex_tr3_tdm_510 = { 4043 1, 4044 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 37, 37 }, 4045 { 3, 13, 27, 4, 14, 41, 8, 18, 31, 9, 19, 46, 0, 1 }, 4046 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5, 5 } 4047 }; 4048 static uint32 hx4_tdm_610[] = { /* HX4_1G_200_E*: 12xF.QSGMII + 2xFlex[4x10] + 1GE */ 4049 53, 57, 1, 13, 53, 57, 25, 53, 57, 37, 5, 53, 57, 17, 29, 53, 57, 41, 53, 57, 9, 81, 53, 57, 33, 53, 57, 81, 0, 4050 53, 57, 2, 21, 53, 57, 26, 53, 57, 45, 6, 53, 57, 14, 30, 53, 57, 38, 53, 57, 18, 81, 53, 57, 42, 53, 57, 81, 0, 4051 53, 57, 10, 22, 53, 57, 34, 53, 57, 46, 3, 53, 57, 15, 27, 53, 57, 39, 53, 57, 7, 81, 53, 57, 31, 53, 57, 81, -1, 4052 53, 57, 11, 19, 53, 57, 35, 53, 57, 43, 4, 53, 57, 23, 28, 53, 57, 47, 53, 57, 16, 81, 53, 57, 40, 53, 57, 81, 0, 4053 53, 57, 8, 20, 53, 57, 32, 53, 57, 44, 12, 53, 57, 24, 36, 53, 57, 48, 53, 57, 49, 81, 53, 57, -1, 53, 57, 81, 0 4054 }; 4055 _soc_tr3_flex_tdm_inf_t flex_tr3_tdm_610 = { 4056 1, 4057 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 29, 29 }, 4058 { 2, 10, 20, 3, 13, 32, 6, 14, 24, 9, 17, 38, 0, 1 }, 4059 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 4 } 4060 }; 4061 static uint32 hx4_tdm_460[] = { /* HX4_1G_130: 7xF.QSGMII + Flex[4x10] + 2xHG[21] + 1GE */ 4062 53, 57, 1, 13, 53, 61, 25, 53, 57, 5, 53, 61, 17, 53, 57, 81, 53, 61, 9, 53, 57, -1, 53, 61, 0, 4063 53, 57, 2, 21, 53, 61, 26, 53, 57, 6, 53, 61, 14, 53, 57, 81, 53, 61, 18, 53, 57, 81, 53, 61, 0, 4064 53, 57, 10, 22, 53, 61, 27, 53, 57, 3, 53, 61, 15, 53, 57, 81, 53, 61, 7, 53, 57, 81, 53, 61, -1, 4065 53, 57, 11, 19, 53, 61, 28, 53, 57, 4, 53, 61, 23, 53, 57, 81, 53, 61, 16, 53, 57, 81, 53, 61, 0, 4066 53, 57, 8, 20, 53, 61, -1, 53, 57, 12, 53, 61, 24, 53, 57, 81, 53, 61, 49, 53, 57, 81, 53, 61, 0 4067 }; 4068 _soc_tr3_flex_tdm_inf_t flex_tr3_tdm_460 = { 4069 1, 4070 { 0, 0, 0, 0, 0, 0, 0, 25, }, 4071 { 2, 9, 18, 3, 12, 28, 6, 0, }, 4072 { 0, 0, 0, 0, 0, 0, 0, 3, } 4073 }; 4074 4075 _soc_tr3_flex_tdm_inf_t flex_tr3_tdm_464 = { 4076 1, 4077 { 0, 0, 0, 0, 0, 0, 0, 25, 25, 25}, 4078 { 2, 9, 18, 3, 12, 28, 6, 0, 1, 5}, 4079 { 0, 0, 0, 0, 0, 0, 0, 3, 6, 5} 4080 }; 4081 4082 /* HX4_1G_150_F : 12xF.QSGMII + 2x(2xHGd[21]/4xHGs[11/10]) + 1GE */ 4083 static uint32 hx4_tdm_414[] = { 4084 61, 57, 1, 13, 61, 57, 25, 61, 57, 37, 5, 61, 57, 17, 29, 61, 57, 41, 61, 57, 9, 81, 61, 57, 33, 61, 57, 81, 0, 4085 61, 57, 2, 21, 61, 57, 26, 61, 57, 45, 6, 61, 57, 14, 30, 61, 57, 38, 61, 57, 18, 81, 61, 57, 42, 61, 57, 81, 0, 4086 61, 57, 10, 22, 61, 57, 34, 61, 57, 46, 3, 61, 57, 15, 27, 61, 57, 39, 61, 57, 7, 81, 61, 57, 31, 61, 57, 81, -1, 4087 61, 57, 11, 19, 61, 57, 35, 61, 57, 43, 4, 61, 57, 23, 28, 61, 57, 47, 61, 57, 16, 81, 61, 57, 40, 61, 57, 81, 0, 4088 61, 57, 8, 20, 61, 57, 32, 61, 57, 44, 12, 61, 57, 24, 36, 61, 57, 48, 61, 57, 49, 81, 61, 57, -1, 61, 57, 81, 0 4089 }; 4090 _soc_tr3_flex_tdm_inf_t flex_tr3_tdm_414 = { 4091 1, 4092 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 29, 29}, 4093 { 2, 10, 20, 3, 13, 32, 6, 14, 24, 9, 17, 38, 1, 0}, 4094 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 4} 4095 }; 4096 static uint32 hx4_tdm_410[] = { /* HX4_1G_150_B, HX4_1G_150_C */ 4097 53, 57, 1, 13, 53, 61, 25, 53, 57, 37, 5, 53, 61, 17, 29, 53, 57, 41, 53, 61, 9, 81, 53, 57, 33, 53, 61, 81, 0, 4098 53, 57, 2, 21, 53, 61, 26, 53, 57, 45, 6, 53, 61, 14, 30, 53, 57, 38, 53, 61, 18, 81, 53, 57, 42, 53, 61, 81, 0, 4099 53, 57, 10, 22, 53, 61, 34, 53, 57, 46, 3, 53, 61, 15, 27, 53, 57, 39, 53, 61, 7, 81, 53, 57, 31, 53, 61, 81, -1, 4100 53, 57, 11, 19, 53, 61, 35, 53, 57, 43, 4, 53, 61, 23, 28, 53, 57, 47, 53, 61, 16, 81, 53, 57, 40, 53, 61, 81, 0, 4101 53, 57, 8, 20, 53, 61, 32, 53, 57, 44, 12, 53, 61, 24, 36, 53, 57, 48, 53, 61, 49, 81, 53, 57, -1, 53, 61, 81, 0 4102 }; 4103 _soc_tr3_flex_tdm_inf_t flex_tr3_tdm_410 = { 4104 1, 4105 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 29, 29, 29}, 4106 { 2, 10, 20, 3, 13, 32, 6, 14, 24, 9, 17, 38, 0, 1, 5}, 4107 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 7, 7} 4108 }; 4109 static uint32 hx4_tdm_400[] = { /* HX4_1G_150_A */ 4110 61, 57, 1, 13, 63, 53, 25, 61, 58, 37, 5, 63, 54, 17, 29, 61, 57, 41, 63, 55, 9, 81, 61, 58, 33, 63, 56, 81, 0, 4111 61, 57, 2, 21, 63, 53, 26, 61, 58, 45, 6, 63, 54, 14, 30, 61, 57, 38, 63, 55, 18, 81, 61, 58, 42, 63, 56, 81, 0, 4112 61, 57, 10, 22, 63, 53, 34, 61, 58, 46, 3, 63, 54, 15, 27, 61, 57, 39, 63, 55, 7, 81, 61, 58, 31, 63, 56, 81, -1, 4113 61, 57, 11, 19, 63, 53, 35, 61, 58, 43, 4, 63, 54, 23, 28, 61, 57, 47, 63, 55, 16, 81, 61, 58, 40, 63, 56, 81, 0, 4114 61, 57, 8, 20, 63, 53, 32, 61, 58, 44, 12, 63, 54, 24, 36, 61, 57, 48, 63, 55, 49, 81, 61, 58, -1, 63, 56, 81, 0 4115 }; 4116 _soc_tr3_flex_tdm_inf_t flex_tr3_tdm_400 = { 4117 1, 4118 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, 4119 { 2, 10, 20, 3, 13, 32, 6, 14, 24, 9, 17, 38, }, 4120 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, } 4121 }; 4122 static uint32 hx4_tdm_420[] = { /* RGR_XFI_150 */ 4123 53, 57, 61, 81, 53, 57, 61, 53, 57, 61, 1, 53, 57, 61, 81, 53, 57, 61, 53, 57, 61, 0, 53, 57, 61, 53, 57, 61, -1, 4124 53, 57, 61, 81, 53, 57, 61, 53, 57, 61, 2, 53, 57, 61, 81, 53, 57, 61, 53, 57, 61, 0, 53, 57, 61, 53, 57, 61, -1, 4125 53, 57, 61, 81, 53, 57, 61, 53, 57, 61, 3, 53, 57, 61, 81, 53, 57, 61, 53, 57, 61, 0, 53, 57, 61, 53, 57, 61, -1, 4126 53, 57, 61, 81, 53, 57, 61, 53, 57, 61, 4, 53, 57, 61, 81, 53, 57, 61, 53, 57, 61, 0, 53, 57, 61, 53, 57, 61, -1, 4127 53, 57, 61, 81, 53, 57, 61, 53, 57, 61, 49, 53, 57, 61, 81, 53, 57, 61, 53, 57, 61, 0, 53, 57, 61, 53, 57, 61, -1 4128 }; 4129 _soc_tr3_flex_tdm_inf_t flex_tr3_tdm_420 = { 4130 1, 4131 { 0, 29, 29, 29 }, 4132 { 10, 0, 1, 2 }, 4133 { 0, 4, 4, 4 } 4134 }; 4135 static uint32 hx4_tdm_514[] = { /* HX4_1G_200_E*: 7xF.QSGMII + 2xFlex[4x10] + 1GE */ 4136 53, 57, -1, 1, 13, 53, 57, -1, 25, -1, 53, 57, -1, 5, 17, 53, 57, -1, -1, -1, 53, 57, -1, 81, 53, 57, -1, 9, 53, 57, -1, -1, 0, 53, 57, -1, 81, 4137 53, 57, -1, 2, 21, 53, 57, -1, 26, -1, 53, 57, -1, 6, 14, 53, 57, -1, -1, -1, 53, 57, -1, 81, 53, 57, -1, 18, 53, 57, -1, -1, 0, 53, 57, -1, 81, 4138 53, 57, -1, 10, 22, 53, 57, -1, -1, -1, 53, 57, -1, 3, 15, 53, 57, -1, 27, -1, 53, 57, -1, 81, 53, 57, -1, 7, 53, 57, -1, -1, -1, 53, 57, -1, 81, 4139 53, 57, -1, 11, 19, 53, 57, -1, -1, -1, 53, 57, -1, 4, 23, 53, 57, -1, 28, -1, 53, 57, -1, 81, 53, 57, -1, 16, 53, 57, -1, -1, 0, 53, 57, -1, 81, 4140 53, 57, -1, 8, 20, 53, 57, -1, -1, -1, 53, 57, -1, 12, 24, 53, 57, -1, -1, -1, 53, 57, -1, 81, 53, 57, -1, 49, 53, 57, -1, -1, 0, 53, 57, -1, 81 4141 }; 4142 _soc_tr3_flex_tdm_inf_t flex_tr3_tdm_514 = { 4143 1, 4144 { 0, 0, 0, 0, 0, 0, 0, 37, 37 }, 4145 { 3, 13, 27, 4, 14, 41, 8, 0, 1 }, 4146 { 0, 0, 0, 0, 0, 0, 0, 5, 5 } 4147 }; 4148 static uint32 hx4_tdm_450[] = { /* RGR_XFI_200 */ 4149 53, 57, 61, 81, 0, 53, 57, 61, -1, 53, 57, 61, 81, -1, 53, 57, 61, -1, 1, 53, 57, 61, 81, 0, 53, 57, 61, -1, 53, 57, 61, 81, -1, 53, 57, 61, -1, 4150 53, 57, 61, 81, 0, 53, 57, 61, -1, 53, 57, 61, 81, -1, 53, 57, 61, -1, 2, 53, 57, 61, 81, 0, 53, 57, 61, -1, 53, 57, 61, 81, -1, 53, 57, 61, -1, 4151 53, 57, 61, 81, 0, 53, 57, 61, -1, 53, 57, 61, 81, -1, 53, 57, 61, -1, 3, 53, 57, 61, 81, 0, 53, 57, 61, -1, 53, 57, 61, 81, -1, 53, 57, 61, -1, 4152 53, 57, 61, 81, 0, 53, 57, 61, -1, 53, 57, 61, 81, -1, 53, 57, 61, -1, 4, 53, 57, 61, 81, 0, 53, 57, 61, -1, 53, 57, 61, 81, -1, 53, 57, 61, -1, 4153 53, 57, 61, 81, 0, 53, 57, 61, -1, 53, 57, 61, 81, -1, 53, 57, 61, -1, 49, 53, 57, 61, 81, 0, 53, 57, 61, -1, 53, 57, 61, 81, -1, 53, 57, 61, -1 4154 }; 4155 _soc_tr3_flex_tdm_inf_t flex_tr3_tdm_450 = { 4156 1, 4157 { 0, 37, 37, 37 }, 4158 { 18, 0, 1, 2 }, 4159 { 0, 5, 5, 5 } 4160 }; 4161 4162 switch (_tr3_port_config_id[unit]) { 4163 case 0: 4164 _soc_tr3_tdm_size = COUNTOF(hx4_tdm_0); 4165 sal_memcpy(&_soc_tr3_tdm_arr, &hx4_tdm_0, sizeof(uint32) * _soc_tr3_tdm_size); 4166 break; 4167 case 1: 4168 _soc_tr3_tdm_size = COUNTOF(hx4_tdm_1); 4169 sal_memcpy(&_soc_tr3_tdm_arr, &hx4_tdm_1, sizeof(uint32) * _soc_tr3_tdm_size); 4170 break; 4171 case 2: 4172 _soc_tr3_tdm_size = COUNTOF(hx4_tdm_2); 4173 sal_memcpy(&_soc_tr3_tdm_arr, &hx4_tdm_2, sizeof(uint32) * _soc_tr3_tdm_size); 4174 break; 4175 case 3: 4176 _soc_tr3_tdm_size = COUNTOF(hx4_tdm_3); 4177 sal_memcpy(&_soc_tr3_tdm_arr, &hx4_tdm_3, sizeof(uint32) * _soc_tr3_tdm_size); 4178 break; 4179 case 4: 4180 _soc_tr3_tdm_size = COUNTOF(hx4_tdm_4); 4181 sal_memcpy(&_soc_tr3_tdm_arr, &hx4_tdm_4, sizeof(uint32) * _soc_tr3_tdm_size); 4182 break; 4183 case 5: 4184 _soc_tr3_tdm_size = COUNTOF(hx4_tdm_5); 4185 sal_memcpy(&_soc_tr3_tdm_arr, &hx4_tdm_5, sizeof(uint32) * _soc_tr3_tdm_size); 4186 break; 4187 case 6: 4188 _soc_tr3_tdm_size = COUNTOF(hx4_tdm_6); 4189 sal_memcpy(&_soc_tr3_tdm_arr, &hx4_tdm_6, sizeof(uint32) * _soc_tr3_tdm_size); 4190 break; 4191 case 7: 4192 _soc_tr3_tdm_size = COUNTOF(hx4_tdm_7); 4193 sal_memcpy(&_soc_tr3_tdm_arr, &hx4_tdm_7, sizeof(uint32) * _soc_tr3_tdm_size); 4194 break; 4195 case 8: 4196 _soc_tr3_tdm_size = COUNTOF(hx4_tdm_8); 4197 sal_memcpy(&_soc_tr3_tdm_arr, &hx4_tdm_8, sizeof(uint32) * _soc_tr3_tdm_size); 4198 break; 4199 case 9: 4200 _soc_tr3_tdm_size = COUNTOF(hx4_tdm_9); 4201 sal_memcpy(&_soc_tr3_tdm_arr, &hx4_tdm_9, sizeof(uint32) * _soc_tr3_tdm_size); 4202 break; 4203 case 10: 4204 _soc_tr3_tdm_size = COUNTOF(hx4_tdm_10); 4205 sal_memcpy(&_soc_tr3_tdm_arr, &hx4_tdm_10, sizeof(uint32) * _soc_tr3_tdm_size); 4206 break; 4207 case 11: 4208 _soc_tr3_tdm_size = COUNTOF(hx4_tdm_11); 4209 sal_memcpy(&_soc_tr3_tdm_arr, &hx4_tdm_11, sizeof(uint32) * _soc_tr3_tdm_size); 4210 break; 4211 case 490: 4212 _soc_tr3_tdm_size = COUNTOF(hx4_tdm_490); 4213 sal_memcpy(&_soc_tr3_tdm_arr, &hx4_tdm_490, sizeof(uint32) * _soc_tr3_tdm_size); 4214 _soc_tr3_flex_tdm = flex_tr3_tdm_490; 4215 break; 4216 case 491: 4217 _soc_tr3_tdm_size = COUNTOF(hx4_tdm_491); 4218 sal_memcpy(&_soc_tr3_tdm_arr, &hx4_tdm_491, sizeof(uint32) * _soc_tr3_tdm_size); 4219 _soc_tr3_flex_tdm = flex_tr3_tdm_491; 4220 break; 4221 case 492: 4222 _soc_tr3_tdm_size = COUNTOF(hx4_tdm_492); 4223 sal_memcpy(&_soc_tr3_tdm_arr, &hx4_tdm_492, sizeof(uint32) * _soc_tr3_tdm_size); 4224 _soc_tr3_flex_tdm = flex_tr3_tdm_492; 4225 break; 4226 case 495: 4227 _soc_tr3_tdm_size = COUNTOF(hx4_tdm_495); 4228 sal_memcpy(&_soc_tr3_tdm_arr, &hx4_tdm_495, sizeof(uint32) * _soc_tr3_tdm_size); 4229 _soc_tr3_flex_tdm = flex_tr3_tdm_495; 4230 break; 4231 case 500: 4232 _soc_tr3_tdm_size = COUNTOF(hx4_tdm_500); 4233 sal_memcpy(&_soc_tr3_tdm_arr, &hx4_tdm_500, sizeof(uint32) * _soc_tr3_tdm_size); 4234 _soc_tr3_flex_tdm = flex_tr3_tdm_500; 4235 break; 4236 case 497: 4237 _soc_tr3_tdm_size = COUNTOF(hx4_tdm_497); 4238 sal_memcpy(&_soc_tr3_tdm_arr, &hx4_tdm_497, sizeof(uint32) * _soc_tr3_tdm_size); 4239 _soc_tr3_flex_tdm = flex_tr3_tdm_497; 4240 break; 4241 case 510: 4242 _soc_tr3_tdm_size = COUNTOF(hx4_tdm_510); 4243 sal_memcpy(&_soc_tr3_tdm_arr, &hx4_tdm_510, sizeof(uint32) * _soc_tr3_tdm_size); 4244 _soc_tr3_flex_tdm = flex_tr3_tdm_510; 4245 break; 4246 case 610: 4247 _soc_tr3_tdm_size = COUNTOF(hx4_tdm_610); 4248 sal_memcpy(&_soc_tr3_tdm_arr, &hx4_tdm_610, sizeof(uint32) * _soc_tr3_tdm_size); 4249 _soc_tr3_flex_tdm = flex_tr3_tdm_610; 4250 break; 4251 case 462: 4252 case 460: 4253 _soc_tr3_tdm_size = COUNTOF(hx4_tdm_460); 4254 sal_memcpy(&_soc_tr3_tdm_arr, &hx4_tdm_460, sizeof(uint32) * _soc_tr3_tdm_size); 4255 _soc_tr3_flex_tdm = flex_tr3_tdm_460; 4256 break; 4257 case 463: 4258 case 464: 4259 _soc_tr3_tdm_size = COUNTOF(hx4_tdm_460); 4260 sal_memcpy(&_soc_tr3_tdm_arr, &hx4_tdm_460, sizeof(uint32) * _soc_tr3_tdm_size); 4261 _soc_tr3_flex_tdm = flex_tr3_tdm_464; 4262 break; 4263 case 414: 4264 _soc_tr3_tdm_size = COUNTOF(hx4_tdm_414); 4265 sal_memcpy(&_soc_tr3_tdm_arr, &hx4_tdm_414, sizeof(uint32) * _soc_tr3_tdm_size); 4266 _soc_tr3_flex_tdm = flex_tr3_tdm_414; 4267 break; 4268 case 413: 4269 case 412: 4270 case 410: 4271 _soc_tr3_tdm_size = COUNTOF(hx4_tdm_410); 4272 sal_memcpy(&_soc_tr3_tdm_arr, &hx4_tdm_410, sizeof(uint32) * _soc_tr3_tdm_size); 4273 _soc_tr3_flex_tdm = flex_tr3_tdm_410; 4274 break; 4275 case 400: 4276 _soc_tr3_tdm_size = COUNTOF(hx4_tdm_400); 4277 sal_memcpy(&_soc_tr3_tdm_arr, &hx4_tdm_400, sizeof(uint32) * _soc_tr3_tdm_size); 4278 _soc_tr3_flex_tdm = flex_tr3_tdm_400; 4279 break; 4280 case 420: 4281 _soc_tr3_tdm_size = COUNTOF(hx4_tdm_420); 4282 sal_memcpy(&_soc_tr3_tdm_arr, &hx4_tdm_420, sizeof(uint32) * _soc_tr3_tdm_size); 4283 _soc_tr3_flex_tdm = flex_tr3_tdm_420; 4284 break; 4285 case 514: 4286 _soc_tr3_tdm_size = COUNTOF(hx4_tdm_514); 4287 sal_memcpy(&_soc_tr3_tdm_arr, &hx4_tdm_514, sizeof(uint32) * _soc_tr3_tdm_size); 4288 _soc_tr3_flex_tdm = flex_tr3_tdm_514; 4289 break; 4290 case 450: 4291 _soc_tr3_tdm_size = COUNTOF(hx4_tdm_450); 4292 sal_memcpy(&_soc_tr3_tdm_arr, &hx4_tdm_450, sizeof(uint32) * _soc_tr3_tdm_size); 4293 _soc_tr3_flex_tdm = flex_tr3_tdm_450; 4294 break; 4295 default: 4296 _soc_tr3_tdm_size = COUNTOF(hx4_tdm_0); 4297 sal_memcpy(&_soc_tr3_tdm_arr, &hx4_tdm_0, sizeof(uint32) * _soc_tr3_tdm_size); 4298 break; 4299 } 4300 } 4301 4302 extern int (*_phy_wc40_firmware_set_helper[SOC_MAX_NUM_DEVICES])(int, int, uint8 *,int); 4303 4304 #define _TR3_MMU_BYTES_TO_CELLS(_byte_) \ 4305 (((_byte_) + _TR3_MMU_BYTES_PER_CELL - 1) / _TR3_MMU_BYTES_PER_CELL) 4306 4307 STATIC void 4308 _soc_hx4_mmu_init_dev_config(int unit, _soc_mmu_device_info_t *devcfg) 4309 { 4310 sal_memset(devcfg, 0, sizeof(_soc_mmu_device_info_t)); 4311 4312 devcfg->max_pkt_byte = _TR3_MMU_MAX_PACKET_BYTES; 4313 devcfg->mmu_hdr_byte = _TR3_MMU_PACKET_HEADER_BYTES; 4314 devcfg->jumbo_pkt_size = _TR3_MMU_JUMBO_FRAME_BYTES; 4315 devcfg->default_mtu_size = _TR3_MMU_DEFAULT_MTU_BYTES; 4316 devcfg->mmu_cell_size = _TR3_MMU_BYTES_PER_CELL; 4317 devcfg->mmu_total_cell = _TR3_MMU_TOTAL_CELLS(unit) - _TR3_MMU_CELLS_RSVD_IP; /* cells for IP */ 4318 devcfg->num_pg = _TR3_MMU_NUM_PG; 4319 devcfg->num_service_pool = _TR3_MMU_NUM_POOL; 4320 } 4321 4322 STATIC int 4323 _soc_hx4_default_pg_headroom(int unit, soc_port_t port, int lossless) 4324 { 4325 int speed = 1000, hdrm = 0; 4326 4327 if ((!lossless) || (IS_CPU_PORT(unit, port)) || (IS_AXP_PORT(unit, port))) { 4328 return 0; 4329 } 4330 4331 speed = SOC_INFO(unit).port_speed_max[port]; 4332 4333 if ((speed >= 1000) && (speed < 10000)) { 4334 hdrm = 162; 4335 } else if ((speed >= 10000) && (speed < 20000)) { 4336 hdrm = 242; 4337 } else if ((speed >= 20000) && (speed <= 42000)) { 4338 hdrm = 344; 4339 } else if (speed >= 100000) { 4340 hdrm = 768; 4341 } else { 4342 hdrm = 162; 4343 } 4344 return hdrm; 4345 } 4346 4347 STATIC void 4348 _soc_hx4_mmu_config_buf_default(int unit, _soc_mmu_cfg_buf_t *buf) 4349 { 4350 soc_info_t *si; 4351 _soc_mmu_cfg_buf_pool_t *buf_pool; 4352 _soc_mmu_cfg_buf_port_t *buf_port; 4353 _soc_mmu_cfg_buf_port_pool_t *buf_port_pool; 4354 _soc_mmu_cfg_buf_prigroup_t *buf_prigroup; 4355 _soc_mmu_cfg_buf_queue_t *buf_queue; 4356 int max_packet_cells, jumbo_frame_cells, default_mtu_cells; 4357 int port, idx, per_q_guarentee; 4358 int total_pool_size = 0, egr_shared_total = 0, lossless = 1; 4359 int q_reserved = 0, numq, tmp; 4360 _soc_mmu_cfg_buf_qgroup_t *queue_grp; 4361 4362 si = &SOC_INFO(unit); 4363 4364 LOG_VERBOSE(BSL_LS_SOC_COMMON, 4365 (BSL_META_U(unit, 4366 "Initializing default MMU config (u=%d)\n"), unit)); 4367 max_packet_cells = _MMU_CFG_MMU_BYTES_TO_CELLS(_TR3_MMU_MAX_PACKET_BYTES + 4368 _TR3_MMU_PACKET_HEADER_BYTES, 4369 _TR3_MMU_BYTES_PER_CELL); 4370 jumbo_frame_cells = _MMU_CFG_MMU_BYTES_TO_CELLS(_TR3_MMU_JUMBO_FRAME_BYTES + 4371 _TR3_MMU_PACKET_HEADER_BYTES, 4372 _TR3_MMU_BYTES_PER_CELL); 4373 default_mtu_cells = _MMU_CFG_MMU_BYTES_TO_CELLS(_TR3_MMU_DEFAULT_MTU_BYTES + 4374 _TR3_MMU_PACKET_HEADER_BYTES, 4375 _TR3_MMU_BYTES_PER_CELL); 4376 4377 total_pool_size = _TR3_MMU_TOTAL_CELLS(unit) - _TR3_MMU_CELLS_RSVD_IP; 4378 4379 lossless = soc_property_get(unit, spn_MMU_LOSSLESS, 1); 4380 4381 buf->headroom = 2 * jumbo_frame_cells; 4382 4383 per_q_guarentee = (lossless) ? 0 : default_mtu_cells; 4384 PBMP_ALL_ITER(unit, port) { 4385 numq = 0; 4386 soc_tr3_get_def_qbase(unit, port, _SOC_TR3_INDEX_STYLE_UCAST_QUEUE, 4387 NULL, &tmp); 4388 numq += tmp; 4389 soc_tr3_get_def_qbase(unit, port, _SOC_TR3_INDEX_STYLE_MCAST_QUEUE, 4390 NULL, &tmp); 4391 numq += tmp; 4392 q_reserved += per_q_guarentee * numq; 4393 } 4394 4395 egr_shared_total = total_pool_size - q_reserved; 4396 4397 for (idx = 0; idx < _TR3_MMU_NUM_POOL; idx++) { 4398 buf_pool = &buf->pools[idx]; 4399 4400 if (idx == 0) { /* 100% scale up by 100 */ 4401 buf_pool->size = 10000 | _MMU_CFG_BUF_PERCENT_FLAG; 4402 buf_pool->yellow_size = 10000 | _MMU_CFG_BUF_PERCENT_FLAG; 4403 buf_pool->red_size = 10000 | _MMU_CFG_BUF_PERCENT_FLAG; 4404 } else { 4405 buf_pool->size = 0; 4406 buf_pool->yellow_size = 0; 4407 buf_pool->red_size = 0; 4408 } 4409 } 4410 4411 for (idx = 0; idx < SOC_MMU_CFG_QGROUP_MAX; idx++) { 4412 queue_grp = &buf->qgroups[idx]; 4413 queue_grp->guarantee = 0; 4414 queue_grp->pool_limit = total_pool_size; 4415 queue_grp->discard_enable = (lossless) ? 0 : 1; 4416 queue_grp->pool_scale = -1; 4417 queue_grp->pool_resume = default_mtu_cells * 2; 4418 queue_grp->red_limit = 7 | _MMU_CFG_BUF_DYNAMIC_FLAG; 4419 queue_grp->yellow_limit = 7 | _MMU_CFG_BUF_DYNAMIC_FLAG; 4420 queue_grp->yellow_resume = default_mtu_cells * 2; 4421 queue_grp->red_resume = default_mtu_cells * 2; 4422 } 4423 4424 PBMP_ALL_ITER(unit, port) { 4425 buf_port = &buf->ports[port]; 4426 4427 /* internal priority to priority group mapping */ 4428 for (idx = 0; idx < 16; idx++) { 4429 buf_port->pri_to_prigroup[idx] = 7; 4430 } 4431 4432 /* priority group to pool mapping */ 4433 for (idx = 0; idx < _TR3_MMU_NUM_PG; idx++) { 4434 buf_port->prigroups[idx].pool_idx = 0; 4435 } 4436 4437 for (idx = 0; idx < _TR3_MMU_NUM_POOL; idx++) { 4438 buf_port_pool = &buf_port->pools[idx]; 4439 buf_port_pool->guarantee = 0; 4440 buf_port_pool->pool_limit = 0; 4441 buf_port_pool->pool_resume = 0; 4442 if (idx == 0) { 4443 buf_port_pool->pool_limit = total_pool_size; 4444 buf_port_pool->pool_resume = 4445 total_pool_size - (default_mtu_cells * 2); 4446 } 4447 } 4448 4449 buf_port->pkt_size = max_packet_cells; 4450 4451 /* priority group */ 4452 for (idx = 0; idx < _TR3_MMU_NUM_PG; idx++) { 4453 buf_prigroup = &buf_port->prigroups[idx]; 4454 buf_prigroup->guarantee = 0; 4455 buf_prigroup->user_delay = -1; 4456 buf_prigroup->switch_delay = -1; 4457 buf_prigroup->pkt_size = max_packet_cells; 4458 buf_prigroup->device_headroom_enable = 0; 4459 buf_prigroup->pool_limit = 0; 4460 buf_prigroup->pool_floor = 0; 4461 buf_prigroup->pool_scale = -1; 4462 buf_prigroup->headroom = 0; 4463 buf_prigroup->pool_resume = 0; 4464 buf_prigroup->flow_control_enable = 0; 4465 if (idx == 7) { 4466 buf_prigroup->device_headroom_enable = 1; 4467 buf_prigroup->guarantee = jumbo_frame_cells; 4468 buf_prigroup->headroom = 4469 _soc_hx4_default_pg_headroom(unit, port, lossless); 4470 buf_prigroup->pool_resume = default_mtu_cells * 2; 4471 buf_prigroup->flow_control_enable = lossless; 4472 buf_prigroup->pool_scale = 7; 4473 } 4474 } 4475 4476 /* multicast queue */ 4477 for (idx = 0; idx < si->port_num_cosq[port]; idx++) { 4478 buf_queue = &buf_port->queues[idx]; 4479 buf_queue->qgroup_id = -1; 4480 if (lossless) { 4481 buf_queue->guarantee = 0; 4482 buf_queue->discard_enable = 0; 4483 buf_queue->pool_scale = -1; 4484 buf_queue->pool_limit = egr_shared_total; 4485 buf_queue->red_limit = egr_shared_total; 4486 buf_queue->color_discard_enable = 0; 4487 buf_queue->pool_resume = 16; 4488 } else { 4489 buf_queue->guarantee = default_mtu_cells; 4490 buf_queue->discard_enable = 1; 4491 buf_queue->pool_scale = 7; 4492 buf_queue->pool_limit = 0; 4493 buf_queue->red_limit = 7 | _MMU_CFG_BUF_DYNAMIC_FLAG 4494 | _MMU_CFG_BUF_DYNAMIC_MAPPING_TYPE_1; 4495 buf_queue->color_discard_enable = 1; 4496 buf_queue->pool_resume = 16; 4497 } 4498 } 4499 4500 /* unicast queue */ 4501 for (idx = 0; idx < si->port_num_uc_cosq[port]; idx++) { 4502 buf_queue = &buf_port->queues[si->port_num_cosq[port] + idx]; 4503 buf_queue->qgroup_id = -1; 4504 if (lossless) { 4505 buf_queue->guarantee = 0; 4506 buf_queue->discard_enable = 0; 4507 buf_queue->pool_scale = -1; 4508 buf_queue->pool_limit = egr_shared_total; 4509 buf_queue->red_limit = egr_shared_total; 4510 buf_queue->yellow_limit = egr_shared_total; 4511 buf_queue->color_discard_enable = 0; 4512 buf_queue->pool_resume = default_mtu_cells * 2; 4513 buf_queue->yellow_resume = default_mtu_cells * 2; 4514 buf_queue->red_resume = default_mtu_cells * 2; 4515 } else { 4516 buf_queue->guarantee = default_mtu_cells; 4517 buf_queue->discard_enable = 1; 4518 buf_queue->pool_scale = 7; 4519 buf_queue->pool_limit = 0; 4520 buf_queue->red_limit = 7 | _MMU_CFG_BUF_DYNAMIC_FLAG 4521 | _MMU_CFG_BUF_DYNAMIC_MAPPING_TYPE_1; 4522 buf_queue->yellow_limit = 7 | _MMU_CFG_BUF_DYNAMIC_FLAG 4523 | _MMU_CFG_BUF_DYNAMIC_MAPPING_TYPE_1; 4524 buf_queue->color_discard_enable = 1; 4525 buf_queue->pool_resume = default_mtu_cells * 2; 4526 buf_queue->yellow_resume = default_mtu_cells * 2; 4527 buf_queue->red_resume = default_mtu_cells * 2; 4528 } 4529 } 4530 4531 /* queue to pool mapping */ 4532 for (idx = 0; 4533 idx < si->port_num_cosq[port] + si->port_num_uc_cosq[port]; idx++) { 4534 buf_port->queues[idx].pool_idx = 0; 4535 } 4536 } 4537 4538 /* extended queue profiles */ 4539 for (idx = 0; idx < SOC_MMU_CFG_EQUEUE_MAX; idx++) { 4540 buf_queue = &buf->equeues[idx]; 4541 buf_queue->numq = 0; 4542 buf_queue->guarantee = 0; 4543 buf_queue->pool_limit = 0; 4544 buf_queue->discard_enable = 1; 4545 buf_queue->pool_scale = -1; 4546 buf_queue->pool_resume = default_mtu_cells * 2; 4547 buf_queue->red_limit = 7 | _MMU_CFG_BUF_DYNAMIC_FLAG; 4548 buf_queue->yellow_limit = 7 | _MMU_CFG_BUF_DYNAMIC_FLAG; 4549 buf_queue->yellow_resume = default_mtu_cells * 2; 4550 buf_queue->red_resume = default_mtu_cells * 2; 4551 } 4552 4553 } 4554 4555 STATIC int 4556 _soc_hx4_pool_scale_to_limit(int size, int scale) 4557 { 4558 int factor = 1000; 4559 4560 switch (scale) { 4561 case 7: factor = 875; break; 4562 case 6: factor = 750; break; 4563 case 5: factor = 625; break; 4564 case 4: factor = 500; break; 4565 case 3: factor = 375; break; 4566 case 2: factor = 250; break; 4567 case 1: factor = 125; break; 4568 case 0: 4569 default: 4570 factor = 1000; break; 4571 } 4572 return (size * factor)/1000; 4573 } 4574 4575 STATIC int 4576 _soc_hx4_mmu_config_buf_set_hw(int unit, _soc_mmu_cfg_buf_t *buf) 4577 { 4578 soc_info_t *si; 4579 _soc_mmu_cfg_buf_pool_t *buf_pool; 4580 _soc_mmu_cfg_buf_port_t *buf_port; 4581 _soc_mmu_cfg_buf_prigroup_t *buf_prigroup; 4582 _soc_mmu_cfg_buf_queue_t *buf_queue; 4583 _soc_mmu_cfg_buf_port_pool_t *buf_port_pool; 4584 soc_reg_t reg = INVALIDr; 4585 uint32 rval, fval; 4586 uint32 entry0[SOC_MAX_MEM_WORDS], entry1[SOC_MAX_MEM_WORDS]; 4587 thdi_port_pg_config_entry_t pg_config_mem; 4588 thdi_port_sp_config_entry_t thdi_sp_config; 4589 mmu_thdo_config_qgroup_entry_t cfg_qgrp; 4590 int default_mtu_cells, limit, midx, pri, pool; 4591 int port, phy_port, mmu_port, base, numq, idx; 4592 int jumbo_frame_cells, pval; 4593 _soc_mmu_cfg_buf_qgroup_t *queue_grp; 4594 static const soc_field_t prigroup_reg[] = { 4595 PORT_PRI_GRP0r, PORT_PRI_GRP1r 4596 }; 4597 static const soc_field_t prigroup_field[] = { 4598 PRI0_GRPf, PRI1_GRPf, PRI2_GRPf, PRI3_GRPf, 4599 PRI4_GRPf, PRI5_GRPf, PRI6_GRPf, PRI7_GRPf, 4600 PRI8_GRPf, PRI9_GRPf, PRI10_GRPf, PRI11_GRPf, 4601 PRI12_GRPf, PRI13_GRPf, PRI14_GRPf, PRI15_GRPf 4602 }; 4603 static const soc_field_t prigroup_spid_field[] = { 4604 PG0_SPIDf, PG1_SPIDf, PG2_SPIDf, PG3_SPIDf, 4605 PG4_SPIDf, PG5_SPIDf, PG6_SPIDf, PG7_SPIDf 4606 }; 4607 4608 si = &SOC_INFO(unit); 4609 4610 default_mtu_cells = _MMU_CFG_MMU_BYTES_TO_CELLS(_TR3_MMU_DEFAULT_MTU_BYTES + 4611 _TR3_MMU_PACKET_HEADER_BYTES, 4612 _TR3_MMU_BYTES_PER_CELL); 4613 4614 jumbo_frame_cells = _MMU_CFG_MMU_BYTES_TO_CELLS(_TR3_MMU_JUMBO_FRAME_BYTES + 4615 _TR3_MMU_PACKET_HEADER_BYTES, 4616 _TR3_MMU_BYTES_PER_CELL); 4617 4618 rval = 0; 4619 fval = _TR3_MMU_TOTAL_CELLS(unit) - _TR3_MMU_CELLS_RSVD_IP; 4620 soc_reg_field_set(unit, CFAPFULLTHRESHOLDr, &rval, CFAPFULLSETPOINTf, fval); 4621 soc_reg_field_set(unit, CFAPFULLTHRESHOLDr, &rval, CFAPFULLRESETPOINTf, 4622 fval - 2*jumbo_frame_cells); 4623 SOC_IF_ERROR_RETURN(WRITE_CFAPFULLTHRESHOLDr(unit, rval)); 4624 4625 /* internal priority to priority group mapping */ 4626 PBMP_ALL_ITER(unit, port) { 4627 buf_port = &buf->ports[port]; 4628 4629 for (idx = 0; idx < 16; idx++) { 4630 if (idx % 8 == 0) { /* 8 fields per register */ 4631 reg = prigroup_reg[idx / 8]; 4632 rval = 0; 4633 } 4634 soc_reg_field_set(unit, reg, &rval, prigroup_field[idx], 4635 buf_port->pri_to_prigroup[idx]); 4636 if (idx % 8 == 7) { /* 8 fields per register */ 4637 SOC_IF_ERROR_RETURN(soc_reg32_set(unit, reg, port, 0, rval)); 4638 } 4639 } 4640 } 4641 4642 /* Input port device settings */ 4643 rval = 0; 4644 soc_reg_field_set(unit, GLOBAL_HDRM_LIMITr, &rval, GLOBAL_HDRM_LIMITf, 4645 buf->headroom); 4646 SOC_IF_ERROR_RETURN(WRITE_GLOBAL_HDRM_LIMITr(unit, rval)); 4647 4648 fval = 0; 4649 for (idx = 0; idx < _TR3_MMU_NUM_POOL; idx++) { 4650 if ((buf->pools[idx].size & ~_MMU_CFG_BUF_PERCENT_FLAG) != 0) { 4651 fval |= 1 << idx; 4652 } 4653 } 4654 rval = 0; 4655 soc_reg_field_set(unit, USE_SP_SHAREDr, &rval, ENABLEf, fval); 4656 SOC_IF_ERROR_RETURN(WRITE_USE_SP_SHAREDr(unit, rval)); 4657 4658 fval = 0; 4659 for (idx = 0; idx < _TR3_MMU_NUM_POOL; idx++) { 4660 buf_pool = &buf->pools[idx]; 4661 if ((buf_pool->size & ~_MMU_CFG_BUF_PERCENT_FLAG) == 0) { 4662 continue; 4663 } 4664 4665 if (buf_pool->yellow_size & _MMU_CFG_BUF_PERCENT_FLAG) { 4666 if ((buf_pool->yellow_size & ~_MMU_CFG_BUF_PERCENT_FLAG) < 10000) { 4667 fval |= 1 << idx; 4668 } 4669 } else { 4670 if (buf->pools[idx].size != buf->pools[idx].yellow_size) { 4671 fval |= 1 << idx; 4672 } 4673 } 4674 } 4675 rval = 0; 4676 soc_reg_field_set(unit, COLOR_AWAREr, &rval, ENABLEf, fval); 4677 SOC_IF_ERROR_RETURN(WRITE_COLOR_AWAREr(unit, rval)); 4678 4679 /* configure Q-groups */ 4680 for (idx = 0; idx < SOC_MMU_CFG_QGROUP_MAX; idx++) { 4681 queue_grp = &buf->qgroups[idx]; 4682 4683 sal_memset(&cfg_qgrp, 0, sizeof(cfg_qgrp)); 4684 4685 soc_mem_field32_set(unit, MMU_THDO_CONFIG_QGROUPm, &cfg_qgrp, 4686 Q_MIN_LIMIT_CELLf, queue_grp->guarantee); 4687 if (queue_grp->pool_scale != -1) { 4688 soc_mem_field32_set(unit, MMU_THDO_CONFIG_QGROUPm, &cfg_qgrp, 4689 Q_SHARED_ALPHA_CELLf, queue_grp->pool_scale); 4690 soc_mem_field32_set(unit, MMU_THDO_CONFIG_QGROUPm, &cfg_qgrp, 4691 Q_LIMIT_DYNAMIC_CELLf, 1); 4692 } else { 4693 soc_mem_field32_set(unit, MMU_THDO_CONFIG_QGROUPm, &cfg_qgrp, 4694 Q_SHARED_LIMIT_CELLf, queue_grp->pool_limit); 4695 } 4696 4697 if ((queue_grp->red_limit & _MMU_CFG_BUF_DYNAMIC_FLAG) || 4698 (queue_grp->yellow_limit & _MMU_CFG_BUF_DYNAMIC_FLAG)) { 4699 soc_mem_field32_set(unit, MMU_THDO_CONFIG_QGROUPm, &cfg_qgrp, 4700 Q_COLOR_LIMIT_DYNAMIC_CELLf, 1); 4701 } 4702 4703 if (queue_grp->red_limit & _MMU_CFG_BUF_DYNAMIC_FLAG) { 4704 pval = _soc_hx4_pool_scale_to_limit(queue_grp->pool_limit, 4705 queue_grp->red_limit & _MMU_CFG_BUF_DYNAMIC_FLAG); 4706 soc_mem_field32_set(unit, MMU_THDO_CONFIG_QGROUPm, &cfg_qgrp, 4707 LIMIT_RED_CELLf, pval/8); 4708 4709 } else { 4710 soc_mem_field32_set(unit, MMU_THDO_CONFIG_QGROUPm, &cfg_qgrp, 4711 LIMIT_RED_CELLf, queue_grp->red_limit); 4712 } 4713 4714 if (queue_grp->yellow_limit & _MMU_CFG_BUF_DYNAMIC_FLAG) { 4715 pval = _soc_hx4_pool_scale_to_limit(queue_grp->pool_limit, 4716 queue_grp->yellow_limit & _MMU_CFG_BUF_DYNAMIC_FLAG); 4717 soc_mem_field32_set(unit, MMU_THDO_CONFIG_QGROUPm, &cfg_qgrp, 4718 LIMIT_YELLOW_CELLf, pval/8); 4719 4720 } else { 4721 soc_mem_field32_set(unit, MMU_THDO_CONFIG_QGROUPm, &cfg_qgrp, 4722 LIMIT_YELLOW_CELLf, queue_grp->yellow_limit); 4723 } 4724 4725 if (queue_grp->discard_enable) { 4726 soc_mem_field32_set(unit, MMU_THDO_CONFIG_QGROUPm, &cfg_qgrp, 4727 Q_LIMIT_ENABLE_CELLf, 1); 4728 } 4729 4730 SOC_IF_ERROR_RETURN 4731 (soc_mem_write(unit, MMU_THDO_CONFIG_QGROUPm, MEM_BLOCK_ALL, 4732 idx, &cfg_qgrp)); 4733 } 4734 4735 /* per service pool settings */ 4736 for (idx = 0; idx < _TR3_MMU_NUM_POOL; idx++) { 4737 buf_pool = &buf->pools[idx]; 4738 if ((buf_pool->size & ~_MMU_CFG_BUF_PERCENT_FLAG) == 0) { 4739 continue; 4740 } 4741 4742 limit = buf_pool->total - (buf_pool->queue_guarantee + 4743 buf_pool->prigroup_headroom + 4744 buf_pool->prigroup_guarantee); 4745 4746 rval = 0; 4747 soc_reg_field_set(unit, BUFFER_CELL_LIMIT_SPr, &rval, LIMITf, limit); 4748 SOC_IF_ERROR_RETURN(WRITE_BUFFER_CELL_LIMIT_SPr(unit, idx, rval)); 4749 4750 rval = 0; 4751 soc_reg_field_set(unit, CELL_RESET_LIMIT_OFFSET_SPr, &rval, OFFSETf, 4752 NUM_PORT(unit) * default_mtu_cells / 2); 4753 SOC_IF_ERROR_RETURN(WRITE_CELL_RESET_LIMIT_OFFSET_SPr(unit, idx, rval)); 4754 4755 if (buf_pool->yellow_size & _MMU_CFG_BUF_PERCENT_FLAG) { 4756 if ((buf_pool->yellow_size & ~_MMU_CFG_BUF_PERCENT_FLAG) == 10000) { 4757 continue; 4758 } 4759 } else { 4760 if (buf_pool->size == buf_pool->yellow_size) { 4761 continue; 4762 } 4763 } 4764 4765 if (buf_pool->yellow_size & _MMU_CFG_BUF_PERCENT_FLAG) { 4766 fval = (buf_pool->yellow_size & ~_MMU_CFG_BUF_PERCENT_FLAG) * limit / 4767 10000; 4768 } else { 4769 fval = buf_pool->yellow_size; 4770 } 4771 rval = 0; 4772 soc_reg_field_set(unit, CELL_SPAP_YELLOW_OFFSET_SPr, &rval, OFFSETf, 4773 limit - fval); 4774 SOC_IF_ERROR_RETURN 4775 (WRITE_CELL_SPAP_YELLOW_OFFSET_SPr(unit, idx, rval)); 4776 4777 if (buf_pool->red_size & _MMU_CFG_BUF_PERCENT_FLAG) { 4778 fval = (buf_pool->red_size & ~_MMU_CFG_BUF_PERCENT_FLAG) * limit / 4779 10000; 4780 } else { 4781 fval = buf_pool->red_size; 4782 } 4783 rval = 0; 4784 soc_reg_field_set(unit, CELL_SPAP_RED_OFFSET_SPr, &rval, OFFSETf, 4785 limit - fval); 4786 SOC_IF_ERROR_RETURN(WRITE_CELL_SPAP_RED_OFFSET_SPr(unit, idx, rval)); 4787 } 4788 4789 /* Input port per port settings */ 4790 PBMP_ALL_ITER(unit, port) { 4791 phy_port = si->port_l2p_mapping[port]; 4792 mmu_port = si->port_p2m_mapping[phy_port]; 4793 buf_port = &buf->ports[port]; 4794 4795 rval = 0; 4796 for (idx = 0; idx < _TR3_MMU_NUM_PG; idx++) { 4797 soc_reg_field_set(unit, PORT_PG_SPIDr, &rval, 4798 prigroup_spid_field[idx], 4799 buf_port->prigroups[idx].pool_idx); 4800 } 4801 SOC_IF_ERROR_RETURN(WRITE_PORT_PG_SPIDr(unit, port, rval)); 4802 4803 /* Per port per pool settings */ 4804 for (idx = 0; idx < _TR3_MMU_NUM_POOL; idx++) { 4805 buf_port_pool = &buf_port->pools[idx]; 4806 midx = (mmu_port * 4) + idx; 4807 sal_memset(&thdi_sp_config, 0, sizeof(thdi_sp_config)); 4808 soc_mem_field32_set(unit, THDI_PORT_SP_CONFIGm, &thdi_sp_config, 4809 PORT_SP_MIN_LIMITf, buf_port_pool->guarantee); 4810 soc_mem_field32_set(unit, THDI_PORT_SP_CONFIGm, &thdi_sp_config, 4811 PORT_SP_RESUME_LIMITf, buf_port_pool->pool_resume); 4812 soc_mem_field32_set(unit, THDI_PORT_SP_CONFIGm, &thdi_sp_config, 4813 PORT_SP_MAX_LIMITf, buf_port_pool->pool_limit); 4814 SOC_IF_ERROR_RETURN 4815 (soc_mem_write(unit, THDI_PORT_SP_CONFIGm, MEM_BLOCK_ALL, 4816 midx, &thdi_sp_config)); 4817 } 4818 4819 fval = 0; 4820 for (idx = 0; idx < _TR3_MMU_NUM_PG; idx++) { 4821 if (buf_port->prigroups[idx].flow_control_enable != 0) { 4822 for (pri=0; pri < 16; pri++) { 4823 if (buf_port->pri_to_prigroup[pri] == idx) { 4824 fval |= 1 << pri; 4825 } 4826 } 4827 } 4828 } 4829 4830 rval = 0; 4831 soc_reg_field_set(unit, PORT_PRI_XON_ENABLEr, &rval, 4832 PORT_PRI_XON_ENABLEf, fval); 4833 SOC_IF_ERROR_RETURN(WRITE_PORT_PRI_XON_ENABLEr(unit, port, rval)); 4834 4835 rval = 0; 4836 soc_reg_field_set(unit, PORT_MAX_PKT_SIZEr, &rval, PORT_MAX_PKT_SIZEf, 4837 buf_port->pkt_size); 4838 SOC_IF_ERROR_RETURN(WRITE_PORT_MAX_PKT_SIZEr(unit, port, rval)); 4839 4840 /* Input port per port per priority group settings */ 4841 for (idx = 0; idx < _TR3_MMU_NUM_PG; idx++) { 4842 buf_prigroup = &buf->ports[port].prigroups[idx]; 4843 4844 midx = (mmu_port * 8) + idx; 4845 sal_memset(&pg_config_mem, 0, sizeof(pg_config_mem)); 4846 soc_mem_field32_set(unit, THDI_PORT_PG_CONFIGm, &pg_config_mem, 4847 PG_MIN_LIMITf, buf_prigroup->guarantee); 4848 4849 if (buf_prigroup->pool_scale != -1) { 4850 soc_mem_field32_set(unit, THDI_PORT_PG_CONFIGm, &pg_config_mem, 4851 PG_SHARED_DYNAMICf, 1); 4852 soc_mem_field32_set(unit, THDI_PORT_PG_CONFIGm, &pg_config_mem, 4853 PG_SHARED_LIMITf, buf_prigroup->pool_scale); 4854 } else { 4855 soc_mem_field32_set(unit, THDI_PORT_PG_CONFIGm, &pg_config_mem, 4856 PG_SHARED_LIMITf, buf_prigroup->pool_limit); 4857 } 4858 4859 soc_mem_field32_set(unit, THDI_PORT_PG_CONFIGm, &pg_config_mem, 4860 PG_GBL_HDRM_ENf, buf_prigroup->device_headroom_enable); 4861 soc_mem_field32_set(unit, THDI_PORT_PG_CONFIGm, &pg_config_mem, 4862 PG_HDRM_LIMITf, buf_prigroup->headroom); 4863 4864 soc_mem_field32_set(unit, THDI_PORT_PG_CONFIGm, &pg_config_mem, 4865 PG_RESET_OFFSETf, buf_prigroup->pool_resume); 4866 4867 soc_mem_field32_set(unit, THDI_PORT_PG_CONFIGm, &pg_config_mem, 4868 PG_RESET_FLOORf, buf_prigroup->pool_floor); 4869 4870 SOC_IF_ERROR_RETURN(soc_mem_write(unit, THDI_PORT_PG_CONFIGm, 4871 MEM_BLOCK_ALL, midx, &pg_config_mem)); 4872 } 4873 } 4874 4875 /*********************************** 4876 * THDO 4877 */ 4878 4879 /* Output port per port per queue setting for multicast queue */ 4880 PBMP_ALL_ITER(unit, port) { 4881 for (idx = 0; idx < si->port_num_cosq[port]; idx++) { 4882 buf_queue = &buf->ports[port].queues[idx]; 4883 pool = buf_queue->pool_idx; 4884 buf_pool = &buf->pools[pool]; 4885 rval = 0; 4886 soc_reg_field_set(unit, OP_QUEUE_CONFIG_CELLr, &rval, Q_MIN_CELLf, 4887 buf_queue->guarantee); 4888 if (buf_queue->pool_scale != -1) { 4889 soc_reg_field_set(unit, OP_QUEUE_CONFIG_CELLr, &rval, 4890 Q_SHARED_ALPHA_CELLf, buf_queue->pool_scale); 4891 } else { 4892 soc_reg_field_set(unit, OP_QUEUE_CONFIG_CELLr, &rval, 4893 Q_SHARED_LIMIT_CELLf, buf_pool->total); 4894 } 4895 SOC_IF_ERROR_RETURN 4896 (WRITE_OP_QUEUE_CONFIG_CELLr(unit, port, idx, rval)); 4897 4898 rval = 0; 4899 if (buf_queue->discard_enable) { 4900 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_CELLr, &rval, 4901 Q_LIMIT_ENABLE_CELLf, 1); 4902 } 4903 if (buf_queue->pool_scale != -1) { 4904 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_CELLr, &rval, 4905 Q_LIMIT_DYNAMIC_CELLf, 1); 4906 } 4907 if (buf_queue->color_discard_enable) { 4908 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_CELLr, &rval, 4909 Q_COLOR_ENABLE_CELLf, 1); 4910 } 4911 if (buf_queue->red_limit & _MMU_CFG_BUF_DYNAMIC_FLAG) { 4912 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_CELLr, &rval, 4913 Q_COLOR_LIMIT_DYNAMIC_CELLf, 1); 4914 } 4915 soc_reg_field_set(unit, OP_QUEUE_CONFIG1_CELLr, &rval, 4916 Q_SPIDf, buf_queue->pool_idx); 4917 SOC_IF_ERROR_RETURN 4918 (WRITE_OP_QUEUE_CONFIG1_CELLr(unit, port, idx, rval)); 4919 4920 rval = 0; 4921 if (buf_queue->red_limit & _MMU_CFG_BUF_DYNAMIC_FLAG) { 4922 soc_reg_field_set(unit, OP_QUEUE_LIMIT_COLOR_CELLr, &rval, REDf, 4923 buf_queue->red_limit 4924 & ~_MMU_CFG_BUF_DYNAMIC_FLAG 4925 & ~_MMU_CFG_BUF_DYNAMIC_MAPPING_TYPE_1); 4926 } else { 4927 soc_reg_field_set(unit, OP_QUEUE_LIMIT_COLOR_CELLr, &rval, REDf, 4928 buf_queue->red_limit/8); 4929 } 4930 SOC_IF_ERROR_RETURN 4931 (WRITE_OP_QUEUE_LIMIT_COLOR_CELLr(unit, port, idx, rval)); 4932 4933 rval = 0; 4934 soc_reg_field_set(unit, OP_QUEUE_RESET_OFFSET_CELLr, &rval, 4935 Q_RESET_OFFSET_CELLf, 4936 buf_queue->pool_resume / 8); 4937 SOC_IF_ERROR_RETURN 4938 (WRITE_OP_QUEUE_RESET_OFFSET_CELLr(unit, port, idx, rval)); 4939 } 4940 } 4941 4942 /* Output port per port per queue setting for regular unicast queue */ 4943 PBMP_PORT_ITER(unit, port) { 4944 if (IS_CPU_PORT(unit, port)) { 4945 continue; 4946 } 4947 4948 /* per port regular unicast queue */ 4949 soc_tr3_get_def_qbase(unit, port, _SOC_TR3_INDEX_STYLE_UCAST_QUEUE, 4950 &base, &numq); 4951 for (idx = 0; idx < numq; idx++) { 4952 buf_queue = &buf->ports[port].queues[si->port_num_cosq[port] + idx]; 4953 4954 sal_memset(entry0, 0, sizeof(mmu_thdo_config_queue_entry_t)); 4955 sal_memset(entry1, 0, sizeof(mmu_thdo_offset_0_entry_t)); 4956 4957 soc_mem_field32_set(unit, MMU_THDO_CONFIG_QUEUEm, entry0, 4958 Q_MIN_LIMIT_CELLf, buf_queue->guarantee); 4959 if (buf_queue->discard_enable) { 4960 soc_mem_field32_set(unit, MMU_THDO_CONFIG_QUEUEm, entry0, 4961 Q_LIMIT_ENABLE_CELLf, 1); 4962 } 4963 if (buf_queue->pool_scale != -1) { 4964 soc_mem_field32_set(unit, MMU_THDO_CONFIG_QUEUEm, entry0, 4965 Q_LIMIT_DYNAMIC_CELLf, 1); 4966 soc_mem_field32_set(unit, MMU_THDO_CONFIG_QUEUEm, entry0, 4967 Q_SHARED_ALPHA_CELLf, buf_queue->pool_scale); 4968 } else { 4969 /* Q_LIMIT_DYNAMIC_CELLf is 0 */ 4970 soc_mem_field32_set(unit, MMU_THDO_CONFIG_QUEUEm, entry0, 4971 Q_SHARED_LIMIT_CELLf, buf_queue->pool_limit); 4972 } 4973 soc_mem_field32_set(unit, MMU_THDO_OFFSET_QUEUEm, 4974 entry1, RESET_OFFSET_CELLf, buf_queue->pool_resume / 8); 4975 if (buf_queue->yellow_limit & _MMU_CFG_BUF_DYNAMIC_FLAG) { 4976 soc_mem_field32_set(unit, MMU_THDO_CONFIG_QUEUEm, entry0, 4977 Q_COLOR_LIMIT_DYNAMIC_CELLf, 1); 4978 soc_mem_field32_set 4979 (unit, MMU_THDO_CONFIG_QUEUEm, entry0, LIMIT_YELLOW_CELLf, 4980 buf_queue->yellow_limit 4981 & ~_MMU_CFG_BUF_DYNAMIC_FLAG 4982 & ~_MMU_CFG_BUF_DYNAMIC_MAPPING_TYPE_1); 4983 soc_mem_field32_set 4984 (unit, MMU_THDO_CONFIG_QUEUEm, entry0, LIMIT_RED_CELLf, 4985 buf_queue->red_limit 4986 & ~_MMU_CFG_BUF_DYNAMIC_FLAG 4987 & ~_MMU_CFG_BUF_DYNAMIC_MAPPING_TYPE_1); 4988 } else { 4989 /* Q_COLOR_LIMIT_DYNAMIC_CELLf is 0 */ 4990 soc_mem_field32_set 4991 (unit, MMU_THDO_CONFIG_QUEUEm, entry0, LIMIT_YELLOW_CELLf, 4992 buf_queue->yellow_limit / 8); 4993 soc_mem_field32_set 4994 (unit, MMU_THDO_CONFIG_QUEUEm, entry0, LIMIT_RED_CELLf, 4995 buf_queue->red_limit / 8); 4996 } 4997 soc_mem_field32_set 4998 (unit, MMU_THDO_OFFSET_QUEUEm, entry1, RESET_OFFSET_YELLOW_CELLf, 4999 buf_queue->yellow_resume / 8); 5000 soc_mem_field32_set 5001 (unit, MMU_THDO_OFFSET_QUEUEm, entry1, RESET_OFFSET_RED_CELLf, 5002 buf_queue->red_resume / 8); 5003 SOC_IF_ERROR_RETURN 5004 (soc_mem_write(unit, MMU_THDO_CONFIG_QUEUEm, MEM_BLOCK_ALL, 5005 base + idx, entry0)); 5006 SOC_IF_ERROR_RETURN 5007 (soc_mem_write(unit, MMU_THDO_OFFSET_QUEUEm, MEM_BLOCK_ALL, 5008 base + idx, entry1)); 5009 5010 sal_memset(entry0, 0, sizeof(mmu_thdo_q_to_qgrp_map_entry_t)); 5011 soc_mem_field32_set(unit, MMU_THDO_Q_TO_QGRP_MAPm, 5012 entry0, Q_SPIDf, buf_queue[idx].pool_idx); 5013 if (buf_queue->color_discard_enable) { 5014 soc_mem_field32_set(unit, MMU_THDO_Q_TO_QGRP_MAPm, entry0, 5015 Q_COLOR_ENABLE_CELLf, 1); 5016 } 5017 5018 if (buf_queue->qgroup_id != -1) { 5019 soc_mem_field32_set(unit, MMU_THDO_Q_TO_QGRP_MAPm, entry0, 5020 QGROUP_VALIDf, 1); 5021 soc_mem_field32_set(unit, MMU_THDO_Q_TO_QGRP_MAPm, entry0, 5022 QGROUPf, buf_queue->qgroup_id); 5023 if (buf_queue->qgroup_min_enable) { 5024 soc_mem_field32_set(unit, MMU_THDO_Q_TO_QGRP_MAPm, entry0, 5025 USE_QGROUP_MINf, 1); 5026 } 5027 } 5028 5029 SOC_IF_ERROR_RETURN(soc_mem_write(unit, MMU_THDO_Q_TO_QGRP_MAPm, 5030 MEM_BLOCK_ALL, base + idx, entry0)); 5031 } 5032 } 5033 5034 5035 /* Output port per pool settings */ 5036 for (idx = 0; idx < _TR3_MMU_NUM_POOL; idx++) { 5037 buf_pool = &buf->pools[idx]; 5038 if ((buf_pool->size & ~_MMU_CFG_BUF_PERCENT_FLAG) == 0) { 5039 continue; 5040 } 5041 5042 limit = buf_pool->total - buf_pool->queue_guarantee; 5043 5044 rval = 0; 5045 soc_reg_field_set(unit, OP_BUFFER_SHARED_LIMIT_CELLr, &rval, 5046 OP_BUFFER_SHARED_LIMIT_CELLf, limit); 5047 SOC_IF_ERROR_RETURN 5048 (soc_reg32_set(unit, OP_BUFFER_SHARED_LIMIT_CELLr, REG_PORT_ANY, 5049 idx, rval)); 5050 5051 rval = 0; 5052 soc_reg_field_set(unit, OP_BUFFER_LIMIT_YELLOW_CELLr, &rval, 5053 OP_BUFFER_LIMIT_YELLOW_CELLf, limit / 8); 5054 SOC_IF_ERROR_RETURN 5055 (soc_reg32_set(unit, OP_BUFFER_LIMIT_YELLOW_CELLr, REG_PORT_ANY, 5056 idx, rval)); 5057 5058 rval = 0; 5059 soc_reg_field_set(unit, OP_BUFFER_LIMIT_RED_CELLr, &rval, 5060 OP_BUFFER_LIMIT_RED_CELLf, limit / 8); 5061 SOC_IF_ERROR_RETURN 5062 (soc_reg32_set(unit, OP_BUFFER_LIMIT_RED_CELLr, REG_PORT_ANY, 5063 idx, rval)); 5064 5065 rval = 0; 5066 soc_reg_field_set(unit, OP_BUFFER_SHARED_LIMIT_RESUME_CELLr, &rval, 5067 OP_BUFFER_SHARED_LIMIT_RESUME_CELLf, limit); 5068 SOC_IF_ERROR_RETURN 5069 (soc_reg32_set(unit, OP_BUFFER_SHARED_LIMIT_RESUME_CELLr, 5070 REG_PORT_ANY, idx, rval)); 5071 5072 rval = 0; 5073 soc_reg_field_set(unit, OP_BUFFER_LIMIT_RESUME_YELLOW_CELLr, &rval, 5074 OP_BUFFER_LIMIT_RESUME_YELLOW_CELLf, limit / 8); 5075 SOC_IF_ERROR_RETURN 5076 (soc_reg32_set(unit, OP_BUFFER_LIMIT_RESUME_YELLOW_CELLr, 5077 REG_PORT_ANY, idx, rval)); 5078 5079 rval = 0; 5080 soc_reg_field_set(unit, OP_BUFFER_LIMIT_RESUME_RED_CELLr, &rval, 5081 OP_BUFFER_LIMIT_RESUME_RED_CELLf, limit / 8); 5082 SOC_IF_ERROR_RETURN 5083 (soc_reg32_set(unit, OP_BUFFER_LIMIT_RESUME_RED_CELLr, 5084 REG_PORT_ANY, idx, rval)); 5085 5086 /* Output port per port per pool setting */ 5087 PBMP_PORT_ITER(unit, port) { 5088 phy_port = si->port_l2p_mapping[port]; 5089 mmu_port = si->port_p2m_mapping[phy_port]; 5090 5091 sal_memset(entry0, 0, sizeof(mmu_thdo_config_port_entry_t)); 5092 soc_mem_field32_set(unit, MMU_THDO_CONFIG_PORTm, entry0, 5093 SHARED_LIMITf, limit); 5094 soc_mem_field32_set(unit, MMU_THDO_CONFIG_PORTm, entry0, 5095 SHARED_RESUMEf, limit - (default_mtu_cells * 2)); 5096 5097 soc_mem_field32_set(unit, MMU_THDO_CONFIG_PORTm, entry0, 5098 YELLOW_LIMITf, limit/8); 5099 soc_mem_field32_set(unit, MMU_THDO_CONFIG_PORTm, entry0, 5100 YELLOW_RESUMEf, (limit - (default_mtu_cells*2))/8); 5101 5102 soc_mem_field32_set(unit, MMU_THDO_CONFIG_PORTm, entry0, 5103 RED_LIMITf, limit/8); 5104 soc_mem_field32_set(unit, MMU_THDO_CONFIG_PORTm, entry0, 5105 RED_RESUMEf, (limit - (default_mtu_cells * 2))/8); 5106 5107 SOC_IF_ERROR_RETURN 5108 (WRITE_MMU_THDO_CONFIG_PORTm(unit, MEM_BLOCK_ANY, 5109 (mmu_port*4) + idx, &entry0)); 5110 } 5111 5112 /* Output port per port per pool setting for multicast queues */ 5113 PBMP_PORT_ITER(unit, port) { 5114 rval = 0; 5115 soc_reg_field_set(unit, OP_PORT_CONFIG_CELLr, &rval, 5116 OP_SHARED_LIMIT_CELLf, limit); 5117 soc_reg_field_set(unit, OP_PORT_CONFIG_CELLr, &rval, 5118 OP_SHARED_RESET_VALUE_CELLf, 5119 limit - (2 * default_mtu_cells)); 5120 SOC_IF_ERROR_RETURN 5121 (soc_reg32_set(unit, OP_PORT_CONFIG_CELLr, port, idx, rval)); 5122 5123 rval = 0; 5124 soc_reg_field_set(unit, OP_PORT_LIMIT_COLOR_CELLr, &rval, REDf, 5125 limit / 8); 5126 SOC_IF_ERROR_RETURN 5127 (soc_reg32_set(unit, OP_PORT_LIMIT_COLOR_CELLr, port, idx, 5128 rval)); 5129 5130 rval = 0; 5131 soc_reg_field_set 5132 (unit, OP_PORT_LIMIT_RESUME_COLOR_CELLr, &rval, REDf, 5133 (limit - (2*default_mtu_cells)) / 8); 5134 SOC_IF_ERROR_RETURN 5135 (soc_reg32_set(unit, OP_PORT_LIMIT_RESUME_COLOR_CELLr, port, 5136 idx, rval)); 5137 } 5138 } 5139 5140 /* setup WAMU */ 5141 rval = 0; 5142 soc_reg_field_set(unit, WAMUTOTALSHRLMTINGr, &rval, SHRPKT_LMTf, 0xfff); 5143 soc_reg_field_set(unit, WAMUTOTALSHRLMTINGr, &rval, SHRCELL_LMTf, 0x7fff); 5144 SOC_IF_ERROR_RETURN 5145 (soc_reg32_set(unit, WAMUTOTALSHRLMTINGr, REG_PORT_ANY, 0, rval)); 5146 5147 rval = 0; 5148 soc_reg_field_set(unit, WAMUTOTALSHRLMTPKTEGRr, &rval, SHR_LMTf, 0xfff); 5149 SOC_IF_ERROR_RETURN 5150 (soc_reg32_set(unit, WAMUTOTALSHRLMTPKTEGRr, REG_PORT_ANY, 0, rval)); 5151 5152 rval = 0; 5153 soc_reg_field_set(unit, CNTX_AGING_LIMITr, &rval, AGING_LIMITf, 0x1fff); 5154 SOC_IF_ERROR_RETURN 5155 (soc_reg32_set(unit, CNTX_AGING_LIMITr, REG_PORT_ANY, 0, rval)); 5156 5157 rval = 0; 5158 SOC_IF_ERROR_RETURN 5159 (soc_reg32_set(unit, WAMUTHDBYPASSr, REG_PORT_ANY, 0, rval)); 5160 5161 rval = 0; 5162 soc_reg_field_set(unit, WAMU_PG_MIN_CELLr, &rval, PG_MIN_ENf, 1); 5163 soc_reg_field_set(unit, WAMU_PG_MIN_CELLr, &rval, PG_MINf, 5164 jumbo_frame_cells); 5165 SOC_IF_ERROR_RETURN 5166 (soc_reg32_set(unit, WAMU_PG_MIN_CELLr, REG_PORT_ANY, 0, rval)); 5167 5168 rval = 0; 5169 soc_reg_field_set(unit, WAMU_PG_SHARED_LIMIT_CELLr, &rval, 5170 PG_SHARED_LIMITf, 6); 5171 soc_reg_field_set(unit, WAMU_PG_SHARED_LIMIT_CELLr, &rval, 5172 PG_SHARED_DYNAMICf, 1); 5173 SOC_IF_ERROR_RETURN 5174 (soc_reg32_set(unit, WAMU_PG_SHARED_LIMIT_CELLr, REG_PORT_ANY, 0, rval)); 5175 5176 rval = 0; 5177 soc_reg_field_set(unit, WAMU_PG_RESET_OFFSET_CELLr, &rval, 5178 WAMU_PG_RESET_OFFSETf, 1); 5179 SOC_IF_ERROR_RETURN 5180 (soc_reg32_set(unit, WAMU_PG_RESET_OFFSET_CELLr, REG_PORT_ANY, 0, rval)); 5181 5182 rval = 0; 5183 soc_reg_field_set(unit, WAMU_PG_RESUME_LIMITr, &rval, 5184 PG_RESUME_LIMITf, 0x2fff); 5185 SOC_IF_ERROR_RETURN 5186 (soc_reg32_set(unit, WAMU_PG_RESUME_LIMITr, REG_PORT_ANY, 0, rval)); 5187 5188 rval = 0; 5189 soc_reg_field_set(unit, WAMUMINLMTPGr, &rval, PKTLMTf, 2); 5190 soc_reg_field_set(unit, WAMUMINLMTPGr, &rval, CELLLMTf, default_mtu_cells); 5191 SOC_IF_ERROR_RETURN 5192 (soc_reg32_set(unit, WAMUMINLMTPGr, REG_PORT_ANY, 0, rval)); 5193 5194 rval = 0; 5195 soc_reg_field_set(unit, WAMUSHRLMTCELLPGr, &rval, SHRLMTf, 6); 5196 soc_reg_field_set(unit, WAMUSHRLMTCELLPGr, &rval, DYNMf, 1); 5197 SOC_IF_ERROR_RETURN 5198 (soc_reg32_set(unit, WAMUSHRLMTCELLPGr, REG_PORT_ANY, 0, rval)); 5199 5200 for (idx = 0; idx < 8; idx++) { 5201 rval = 0; 5202 soc_reg_field_set(unit, WAMUSHRLMTPKTQr, &rval, SHRLMTPKTf, 0xfff); 5203 soc_reg_field_set(unit, WAMUSHRLMTPKTQr, &rval, DYNMf, 1); 5204 SOC_IF_ERROR_RETURN 5205 (soc_reg32_set(unit, WAMUSHRLMTPKTQr, REG_PORT_ANY, idx, rval)); 5206 5207 rval = 0; 5208 soc_reg_field_set(unit, WAMUMINLMTPKTQr, &rval, MINLMTPKTf, 2); 5209 SOC_IF_ERROR_RETURN 5210 (soc_reg32_set(unit, WAMUMINLMTPKTQr, REG_PORT_ANY, idx, rval)); 5211 5212 rval = 0; 5213 soc_reg_field_set(unit, WAMURSTOFFSETPKTQr, &rval, RSTOFFSETf, 2); 5214 SOC_IF_ERROR_RETURN 5215 (soc_reg32_set(unit, WAMURSTOFFSETPKTQr, REG_PORT_ANY, idx, rval)); 5216 } 5217 5218 return SOC_E_NONE; 5219 } 5220 5221 int 5222 soc_hx4_mmu_config_init(int unit, int test_only) 5223 { 5224 int rv; 5225 _soc_mmu_cfg_buf_t *buf; 5226 _soc_mmu_device_info_t devcfg; 5227 5228 buf = soc_mmu_cfg_alloc(unit); 5229 if (!buf) { 5230 return SOC_E_MEMORY; 5231 } 5232 5233 _soc_hx4_mmu_init_dev_config(unit, &devcfg); 5234 _soc_hx4_mmu_config_buf_default(unit, buf); 5235 _soc_mmu_cfg_buf_read(unit, buf, &devcfg); 5236 rv = _soc_mmu_cfg_buf_check(unit, buf, &devcfg); 5237 if (!test_only) { 5238 if (SOC_FAILURE(rv)) { 5239 LOG_VERBOSE(BSL_LS_SOC_COMMON, 5240 (BSL_META_U(unit, 5241 "MMU config: Use default setting\n"))); 5242 _soc_hx4_mmu_config_buf_default(unit, buf); 5243 _soc_mmu_cfg_buf_calculate(unit, buf, &devcfg); 5244 } 5245 rv = _soc_hx4_mmu_config_buf_set_hw(unit, buf); 5246 } 5247 5248 soc_mmu_cfg_free(unit, buf); 5249 5250 LOG_VERBOSE(BSL_LS_SOC_COMMON, 5251 (BSL_META_U(unit, 5252 "MMU THDI/THDO init done\n"))); 5253 return rv; 5254 } 5255 5256 STATIC int 5257 _soc_hx4_age_timer_get(int unit, int *age_seconds, int *enabled) 5258 { 5259 soc_control_t *soc = SOC_CONTROL(unit); 5260 *age_seconds = soc->l2x_age_interval ? (soc->l2x_age_interval) : 0; 5261 *enabled = (soc->l2x_age_pid != SAL_THREAD_ERROR) && (soc->l2x_age_interval ? 1 : 0); 5262 return SOC_E_NONE; 5263 } 5264 5265 STATIC int 5266 _soc_hx4_age_timer_max_get(int unit, int *max_seconds) 5267 { 5268 *max_seconds = 0xffffffff; 5269 return SOC_E_NONE; 5270 } 5271 5272 STATIC int 5273 _soc_hx4_age_timer_set(int unit, int age_seconds, int enable) 5274 { 5275 soc_control_t *soc = SOC_CONTROL(unit); 5276 sal_usecs_t interval = soc->l2x_age_interval; 5277 /* 5278 * SW aging thread running, 5279 * update aging interval and notify the thread 5280 */ 5281 if (soc->l2x_age_interval) { 5282 if (!enable) { 5283 SOC_IF_ERROR_RETURN(soc_tr3_l2_bulk_age_stop(unit)); 5284 } else { 5285 if (age_seconds) { 5286 SOC_CONTROL_LOCK(unit); 5287 /* Changing age interval, clear previous history */ 5288 if (soc->l2x_prev_age_timeout != age_seconds) { 5289 soc->l2x_agetime_adjust_usec = 0; 5290 } 5291 soc->l2x_age_interval = age_seconds; 5292 soc->l2x_prev_age_timeout = age_seconds; 5293 SOC_CONTROL_UNLOCK(unit); 5294 } 5295 if (interval != age_seconds) { 5296 /* Wake up thread to update the new age timer */ 5297 sal_sem_give(soc->l2x_age_notify); 5298 } 5299 } 5300 } else { 5301 /* SW aging not runninig, start the thread */ 5302 if (enable) { 5303 if (age_seconds) { 5304 SOC_CONTROL_LOCK(unit); 5305 soc->l2x_prev_age_timeout = age_seconds; 5306 SOC_CONTROL_UNLOCK(unit); 5307 } 5308 SOC_IF_ERROR_RETURN 5309 (soc_tr3_l2_bulk_age_start(unit, age_seconds)); 5310 } 5311 } 5312 return SOC_E_NONE; 5313 } 5314 5315 static soc_tr3_oam_handler_t hx4_oam_handler[SOC_MAX_NUM_DEVICES] = {NULL}; 5316 5317 void 5318 soc_hx4_oam_handler_register(int unit, soc_tr3_oam_handler_t handler) 5319 { 5320 hx4_oam_handler[unit] = handler; 5321 soc_intr_enable(unit, IRQ_MEM_FAIL); 5322 } 5323 5324 static const soc_reg_t thermal_reg[] = { 5325 TOP_PVTMON_RESULT_0r, TOP_PVTMON_RESULT_1r, 5326 TOP_PVTMON_RESULT_2r, TOP_PVTMON_RESULT_3r, 5327 TOP_PVTMON_RESULT_4r 5328 }; 5329 5330 int 5331 soc_hx4_show_temperature_monitor(int unit) 5332 { 5333 uint32 rval; 5334 soc_reg_t reg; 5335 int index; 5336 int fval, cur, peak, avg_cur, max_peak; 5337 uint16 dev_id, drv_dev_id; 5338 uint8 rev_id, drv_rev_id; 5339 5340 soc_cm_get_id(unit, &dev_id, &rev_id); 5341 soc_cm_get_id_driver(dev_id, rev_id, &drv_dev_id, &drv_rev_id); 5342 5343 reg = TOP_PVTMON_CTRL_0r; 5344 READ_TOP_PVTMON_CTRL_0r(unit, &rval); 5345 soc_reg_field_set(unit, reg, &rval, FUNC_MODE_SELf, 0); 5346 soc_reg_field_set(unit, reg, &rval, MEASUREMENT_CALLIBRATIONf, 5); 5347 soc_reg_field_set(unit, reg, &rval, BG_ADJf, 3); 5348 WRITE_TOP_PVTMON_CTRL_0r(unit, rval); 5349 5350 reg = TOP_PVTMON_CTRL_1r; 5351 READ_TOP_PVTMON_CTRL_1r(unit, &rval); 5352 soc_reg_field_set(unit, reg, &rval, PVTMON_SELECTf, 0); 5353 soc_reg_field_set(unit, reg, &rval, PVTMON_RESET_Nf, 0); 5354 WRITE_TOP_PVTMON_CTRL_1r(unit, rval); 5355 soc_reg_field_set(unit, reg, &rval, PVTMON_RESET_Nf, 1); 5356 WRITE_TOP_PVTMON_CTRL_1r(unit, rval); 5357 5358 sal_usleep(1000); 5359 5360 avg_cur = 0; 5361 max_peak = 0x80000000; 5362 for (index = 0; index < COUNTOF(thermal_reg); index++) { 5363 reg = thermal_reg[index]; 5364 soc_reg32_get(unit, reg, REG_PORT_ANY, 0, &rval); 5365 fval = soc_reg_field_get(unit, reg, rval, TEMP_DATAf); 5366 cur = (4180000 - (5556 * fval)) / 10000; 5367 fval = soc_reg_field_get(unit, reg, rval, PEAK_TEMP_DATAf); 5368 peak = (4180000 - (5556 * fval)) / 10000; 5369 LOG_CLI((BSL_META_U(unit, 5370 "Temperature monitor %d: current=%3d, peak=%3d\n"), 5371 index, cur, peak)); 5372 avg_cur += cur; 5373 if (max_peak < peak) { 5374 max_peak = peak; 5375 } 5376 } 5377 LOG_CLI((BSL_META_U(unit, 5378 "Average current temperature is %d\n"), 5379 avg_cur / COUNTOF(thermal_reg))); 5380 LOG_CLI((BSL_META_U(unit, 5381 "Maximum peak temperature is %d\n"), max_peak)); 5382 5383 READ_TOP_SOFT_RESET_REG_2r(unit, &rval); 5384 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, 5385 TOP_TEMP_MON_PEAK_RST_Lf, 0); 5386 WRITE_TOP_SOFT_RESET_REG_2r(unit, rval); 5387 soc_reg_field_set(unit, TOP_SOFT_RESET_REG_2r, &rval, 5388 TOP_TEMP_MON_PEAK_RST_Lf, 1); 5389 WRITE_TOP_SOFT_RESET_REG_2r(unit, rval); 5390 5391 return SOC_E_NONE; 5392 } 5393 5394 soc_blk_ctr_reg_desc_t _soc_hx4_blk_ctr_reg_desc[] = { 5395 { 5396 SOC_BLK_AXP, 5397 { 5398 {AXP_SM_PACKETS_RECEIVED_COUNTERr, 1, 1, 0}, 5399 {AXP_SM_PACKETS_SENT_COUNTERr, 1, 1, 0}, 5400 {AXP_SM_PACKETS_DROPPED_COUNTERr, 1, 1, 0}, 5401 {AXP_SM_BYTES_MATCHED_COUNTERr, 1, 1, 0}, 5402 {AXP_SM_MATCHED_FLOWS_COUNTERr, 1, 1, 0}, 5403 {AXP_SM_UNMATCHED_FLOWS_COUNTERr, 1, 1, 0}, 5404 {AXP_SM_TOTAL_MATCH_COUNTERr, 1, 1, 0}, 5405 {AXP_SM_TOTAL_CROSS_SIG_FLAGS_COUNTERr, 1, 1, 0}, 5406 {AXP_SM_FRAGMENTS_RECEIVED_COUNTERr, 1, 1, 0}, 5407 {AXP_SM_IN_PACKET_ERROR_COUNTERr, 1, 1, 0}, 5408 {AXP_SM_FLOW_TRACKER_ERROR_COUNTERr, 1, 1, 0}, 5409 {AXP_SM_PACKET_LENGTH_ERROR_COUNTERr, 1, 1, 0}, 5410 {AXP_SM_L4_CHECKSUM_ERROR_COUNTERr, 1, 1, 0}, 5411 {AXP_SM_FLOW_DONE_PACKET_DROP_COUNTERr, 1, 1, 0}, 5412 {AXP_SM_FLOW_TIMESTAMP_ERROR_COUNTERr, 1, 1, 0}, 5413 {AXP_SM_FLOW_PACKET_NUM_ERROR_COUNTERr, 1, 1, 0}, 5414 {AXP_SM_ECC_ERROR_COUNTERr, 1, 1, 0}, 5415 {INVALIDr, 0, 0} 5416 } 5417 } 5418 }; 5419 5420 void 5421 soc_hx4_blk_counter_config(int unit) 5422 { 5423 soc_control_t *soc = SOC_CONTROL(unit); 5424 soc->blk_ctr_desc_count = COUNTOF(_soc_hx4_blk_ctr_reg_desc); 5425 soc->blk_ctr_desc = _soc_hx4_blk_ctr_reg_desc; 5426 } 5427 5428 int 5429 _soc_hx4_ledup_init(int unit) 5430 { 5431 5432 uint32 rval = 0, ix; 5433 5434 /* configure the LED scan delay cycles */ 5435 SOC_IF_ERROR_RETURN(READ_CMIC_LEDUP0_CTRLr(unit, &rval)); 5436 soc_reg_field_set(unit, CMIC_LEDUP0_CTRLr, &rval, LEDUP_SCAN_START_DELAYf, 10); 5437 soc_reg_field_set(unit, CMIC_LEDUP0_CTRLr, &rval, LEDUP_SCAN_INTRA_PORT_DELAYf, 1); 5438 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP0_CTRLr(unit, rval)); 5439 /* coverity[result_independent_of_operands] */ 5440 SOC_IF_ERROR_RETURN(READ_CMIC_LEDUP1_CTRLr(unit, &rval)); 5441 soc_reg_field_set(unit, CMIC_LEDUP1_CTRLr, &rval, LEDUP_SCAN_START_DELAYf, 0); 5442 soc_reg_field_set(unit, CMIC_LEDUP1_CTRLr, &rval, LEDUP_SCAN_INTRA_PORT_DELAYf, 1); 5443 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP1_CTRLr(unit, rval)); 5444 5445 rval =0; 5446 /* Initialize LED Port remap registers */ 5447 5448 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP0_PORT_ORDER_REMAP_0_3r(unit, rval)); 5449 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP0_PORT_ORDER_REMAP_4_7r(unit, rval)); 5450 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP0_PORT_ORDER_REMAP_8_11r(unit, rval)); 5451 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP0_PORT_ORDER_REMAP_12_15r(unit, rval)); 5452 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP0_PORT_ORDER_REMAP_16_19r(unit, rval)); 5453 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP0_PORT_ORDER_REMAP_20_23r(unit, rval)); 5454 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP0_PORT_ORDER_REMAP_24_27r(unit, rval)); 5455 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP0_PORT_ORDER_REMAP_28_31r(unit, rval)); 5456 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP0_PORT_ORDER_REMAP_32_35r(unit, rval)); 5457 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP0_PORT_ORDER_REMAP_36_39r(unit, rval)); 5458 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP0_PORT_ORDER_REMAP_40_43r(unit, rval)); 5459 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP0_PORT_ORDER_REMAP_44_47r(unit, rval)); 5460 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP0_PORT_ORDER_REMAP_48_51r(unit, rval)); 5461 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP0_PORT_ORDER_REMAP_52_55r(unit, rval)); 5462 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP0_PORT_ORDER_REMAP_56_59r(unit, rval)); 5463 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP0_PORT_ORDER_REMAP_60_63r(unit, rval)); 5464 5465 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP1_PORT_ORDER_REMAP_0_3r(unit, rval)); 5466 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP1_PORT_ORDER_REMAP_4_7r(unit, rval)); 5467 /* coverity[result_independent_of_operands] */ 5468 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP1_PORT_ORDER_REMAP_8_11r(unit, rval)); 5469 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP1_PORT_ORDER_REMAP_12_15r(unit, rval)); 5470 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP1_PORT_ORDER_REMAP_16_19r(unit, rval)); 5471 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP1_PORT_ORDER_REMAP_20_23r(unit, rval)); 5472 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP1_PORT_ORDER_REMAP_24_27r(unit, rval)); 5473 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP1_PORT_ORDER_REMAP_28_31r(unit, rval)); 5474 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP1_PORT_ORDER_REMAP_32_35r(unit, rval)); 5475 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP1_PORT_ORDER_REMAP_36_39r(unit, rval)); 5476 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP1_PORT_ORDER_REMAP_40_43r(unit, rval)); 5477 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP1_PORT_ORDER_REMAP_44_47r(unit, rval)); 5478 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP1_PORT_ORDER_REMAP_48_51r(unit, rval)); 5479 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP1_PORT_ORDER_REMAP_52_55r(unit, rval)); 5480 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP1_PORT_ORDER_REMAP_56_59r(unit, rval)); 5481 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP1_PORT_ORDER_REMAP_60_63r(unit, rval)); 5482 5483 /* Configure LED Port remap registers */ 5484 5485 ix = 0; 5486 rval = 0; 5487 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_56_59r, &rval, REMAP_PORT_59f, ++ix); 5488 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_56_59r, &rval, REMAP_PORT_58f, ++ix); 5489 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_56_59r, &rval, REMAP_PORT_57f, ++ix); 5490 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_56_59r, &rval, REMAP_PORT_56f, ++ix); 5491 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP0_PORT_ORDER_REMAP_56_59r(unit, rval)); 5492 5493 rval = 0; 5494 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_52_55r, &rval, REMAP_PORT_55f, ++ix); 5495 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_52_55r, &rval, REMAP_PORT_54f, ++ix); 5496 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_52_55r, &rval, REMAP_PORT_53f, ++ix); 5497 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_52_55r, &rval, REMAP_PORT_52f, ++ix); 5498 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP0_PORT_ORDER_REMAP_52_55r(unit, rval)); 5499 5500 rval = 0; 5501 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_48_51r, &rval, REMAP_PORT_51f, ++ix); 5502 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_48_51r, &rval, REMAP_PORT_50f, ++ix); 5503 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_48_51r, &rval, REMAP_PORT_49f, ++ix); 5504 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_48_51r, &rval, REMAP_PORT_48f, ++ix); 5505 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP0_PORT_ORDER_REMAP_48_51r(unit, rval)); 5506 5507 rval = 0; 5508 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_44_47r, &rval, REMAP_PORT_47f, ++ix); 5509 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_44_47r, &rval, REMAP_PORT_46f, ++ix); 5510 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_44_47r, &rval, REMAP_PORT_45f, ++ix); 5511 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_44_47r, &rval, REMAP_PORT_44f, ++ix); 5512 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP0_PORT_ORDER_REMAP_44_47r(unit, rval)); 5513 5514 rval = 0; 5515 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_40_43r, &rval, REMAP_PORT_43f, ++ix); 5516 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_40_43r, &rval, REMAP_PORT_42f, ++ix); 5517 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_40_43r, &rval, REMAP_PORT_41f, ++ix); 5518 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_40_43r, &rval, REMAP_PORT_40f, ++ix); 5519 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP0_PORT_ORDER_REMAP_40_43r(unit, rval)); 5520 5521 rval = 0; 5522 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_36_39r, &rval, REMAP_PORT_39f, ++ix); 5523 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_36_39r, &rval, REMAP_PORT_38f, ++ix); 5524 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_36_39r, &rval, REMAP_PORT_37f, ++ix); 5525 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_36_39r, &rval, REMAP_PORT_36f, ++ix); 5526 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP0_PORT_ORDER_REMAP_36_39r(unit, rval)); 5527 5528 rval = 0; 5529 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_32_35r, &rval, REMAP_PORT_35f, ++ix); 5530 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_32_35r, &rval, REMAP_PORT_34f, ++ix); 5531 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_32_35r, &rval, REMAP_PORT_33f, ++ix); 5532 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_32_35r, &rval, REMAP_PORT_32f, ++ix); 5533 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP0_PORT_ORDER_REMAP_32_35r(unit, rval)); 5534 5535 rval = 0; 5536 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_28_31r, &rval, REMAP_PORT_31f, ++ix); 5537 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_28_31r, &rval, REMAP_PORT_30f, ++ix); 5538 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_28_31r, &rval, REMAP_PORT_29f, ++ix); 5539 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_28_31r, &rval, REMAP_PORT_28f, ++ix); 5540 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP0_PORT_ORDER_REMAP_28_31r(unit, rval)); 5541 5542 rval = 0; 5543 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_24_27r, &rval, REMAP_PORT_27f, ++ix); 5544 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_24_27r, &rval, REMAP_PORT_26f, ++ix); 5545 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_24_27r, &rval, REMAP_PORT_25f, ++ix); 5546 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_24_27r, &rval, REMAP_PORT_24f, ++ix); 5547 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP0_PORT_ORDER_REMAP_24_27r(unit, rval)); 5548 5549 rval = 0; 5550 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_20_23r, &rval, REMAP_PORT_23f, ++ix); 5551 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_20_23r, &rval, REMAP_PORT_22f, ++ix); 5552 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_20_23r, &rval, REMAP_PORT_21f, ++ix); 5553 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_20_23r, &rval, REMAP_PORT_20f, ++ix); 5554 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP0_PORT_ORDER_REMAP_20_23r(unit, rval)); 5555 5556 rval = 0; 5557 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_16_19r, &rval, REMAP_PORT_19f, ++ix); 5558 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_16_19r, &rval, REMAP_PORT_18f, ++ix); 5559 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_16_19r, &rval, REMAP_PORT_17f, ++ix); 5560 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_16_19r, &rval, REMAP_PORT_16f, ++ix); 5561 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP0_PORT_ORDER_REMAP_16_19r(unit, rval)); 5562 5563 rval = 0; 5564 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_12_15r, &rval, REMAP_PORT_15f, ++ix); 5565 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_12_15r, &rval, REMAP_PORT_14f, ++ix); 5566 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_12_15r, &rval, REMAP_PORT_13f, ++ix); 5567 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_12_15r, &rval, REMAP_PORT_12f, ++ix); 5568 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP0_PORT_ORDER_REMAP_12_15r(unit, rval)); 5569 5570 rval = 0; 5571 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_8_11r, &rval, REMAP_PORT_11f, ++ix); 5572 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_8_11r, &rval, REMAP_PORT_10f, ++ix); 5573 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_8_11r, &rval, REMAP_PORT_9f, ++ix); 5574 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_8_11r, &rval, REMAP_PORT_8f, ++ix); 5575 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP0_PORT_ORDER_REMAP_8_11r(unit, rval)); 5576 5577 rval = 0; 5578 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_4_7r, &rval, REMAP_PORT_7f, ++ix); 5579 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_4_7r, &rval, REMAP_PORT_6f, ++ix); 5580 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_4_7r, &rval, REMAP_PORT_5f, ++ix); 5581 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_4_7r, &rval, REMAP_PORT_4f, ++ix); 5582 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP0_PORT_ORDER_REMAP_4_7r(unit, rval)); 5583 5584 rval = 0; 5585 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_0_3r, &rval, REMAP_PORT_3f, ++ix); 5586 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_0_3r, &rval, REMAP_PORT_2f, ++ix); 5587 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_0_3r, &rval, REMAP_PORT_1f, ++ix); 5588 soc_reg_field_set(unit, CMIC_LEDUP0_PORT_ORDER_REMAP_0_3r, &rval, REMAP_PORT_0f, ++ix); 5589 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP0_PORT_ORDER_REMAP_0_3r(unit, rval)); 5590 5591 /* Configure LED Port remap registers - LED uP1*/ 5592 ix = 0; 5593 rval = 0; 5594 soc_reg_field_set(unit, CMIC_LEDUP1_PORT_ORDER_REMAP_0_3r, &rval, REMAP_PORT_3f, ++ix); 5595 soc_reg_field_set(unit, CMIC_LEDUP1_PORT_ORDER_REMAP_0_3r, &rval, REMAP_PORT_2f, ++ix); 5596 soc_reg_field_set(unit, CMIC_LEDUP1_PORT_ORDER_REMAP_0_3r, &rval, REMAP_PORT_1f, ++ix); 5597 soc_reg_field_set(unit, CMIC_LEDUP1_PORT_ORDER_REMAP_0_3r, &rval, REMAP_PORT_0f, ++ix); 5598 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP1_PORT_ORDER_REMAP_0_3r(unit, rval)); 5599 5600 rval = 0; 5601 soc_reg_field_set(unit, CMIC_LEDUP1_PORT_ORDER_REMAP_4_7r, &rval, REMAP_PORT_5f, ++ix); 5602 soc_reg_field_set(unit, CMIC_LEDUP1_PORT_ORDER_REMAP_4_7r, &rval, REMAP_PORT_4f, ++ix); 5603 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP1_PORT_ORDER_REMAP_4_7r(unit, rval)); 5604 5605 /* initialize the UP0, UP1 data ram */ 5606 rval = 0; 5607 for (ix = 0; ix < 256; ix++) { 5608 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP0_DATA_RAMr(unit,ix, rval)); 5609 SOC_IF_ERROR_RETURN(WRITE_CMIC_LEDUP1_DATA_RAMr(unit,ix, rval)); 5610 } 5611 5612 return SOC_E_NONE; 5613 } 5614 5615 5616 /* 5617 * Tr3 chip driver functions. 5618 */ 5619 soc_functions_t soc_helix4_drv_funs = { 5620 5621 _soc_tr3_misc_init, 5622 _soc_tr3_mmu_init, 5623 _soc_hx4_age_timer_get, 5624 _soc_hx4_age_timer_max_get, 5625 _soc_hx4_age_timer_set, 5626 }; 5627 5628 #endif /* BCM_HELIX4_SUPPORT */